# stackcollapse.py - format perf samples with one line per distinct call stack
# SPDX-License-Identifier: GPL-2.0
#
# This script's output has two space-separated fields.  The first is a semicolon
# separated stack including the program name (from the "comm" field) and the
# function names from the call stack.  The second is a count:
#
#  swapper;start_kernel;rest_init;cpu_idle;default_idle;native_safe_halt 2
#
# The file is sorted according to the first field.
#
# Input may be created and processed using:
#
#  perf record -a -g -F 99 sleep 60
#  perf script report stackcollapse > out.stacks-folded
#
# (perf script record stackcollapse works too).
#
# Written by Paolo Bonzini <pbonzini@redhat.com>
# Based on Brendan Gregg's stackcollapse-perf.pl script.

from __future__ import print_function

import os
import sys
from collections import defaultdict
from optparse import OptionParser, make_option

sys.path.append(os.environ['PERF_EXEC_PATH'] + \
    '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')

from perf_trace_context import *
from Core import *
from EventClass import *

# command line parsing

option_list = [
    # formatting options for the bottom entry of the stack
    make_option("--include-tid", dest="include_tid",
                 action="store_true", default=False,
                 help="include thread id in stack"),
    make_option("--include-pid", dest="include_pid",
                 action="store_true", default=False,
                 help="include process id in stack"),
    make_option("--no-comm", dest="include_comm",
                 action="store_false", default=True,
                 help="do not separate stacks according to comm"),
    make_option("--tidy-java", dest="tidy_java",
                 action="store_true", default=False,
                 help="beautify Java signatures"),
    make_option("--kernel", dest="annotate_kernel",
                 action="store_true", default=False,
                 help="annotate kernel functions with _[k]")
]

parser = OptionParser(option_list=option_list)
(opts, args) = parser.parse_args()

if len(args) != 0:
    parser.error("unexpected command line argument")
if opts.include_tid and not opts.include_comm:
    parser.error("requesting tid but not comm is invalid")
if opts.include_pid and not opts.include_comm:
    parser.error("requesting pid but not comm is invalid")

# event handlers

lines = defaultdict(lambda: 0)

def process_event(param_dict):
    def tidy_function_name(sym, dso):
        if sym is None:
            sym = '[unknown]'

        sym = sym.replace(';', ':')
        if opts.tidy_java:
            # the original stackcollapse-perf.pl script gives the
            # example of converting this:
            #    Lorg/mozilla/javascript/MemberBox;.<init>(Ljava/lang/reflect/Method;)V
            # to this:
            #    org/mozilla/javascript/MemberBox:.init
            sym = sym.replace('<', '')
            sym = sym.replace('>', '')
            if sym[0] == 'L' and sym.find('/'):
                sym = sym[1:]
            try:
                sym = sym[:sym.index('(')]
            except ValueError:
                pass

        if opts.annotate_kernel and dso == '[kernel.kallsyms]':
            return sym + '_[k]'
        else:
            return sym

    stack = list()
    if 'callchain' in param_dict:
        for entry in param_dict['callchain']:
            entry.setdefault('sym', dict())
            entry['sym'].setdefault('name', None)
            entry.setdefault('dso', None)
            stack.append(tidy_function_name(entry['sym']['name'],
                                            entry['dso']))
    else:
        param_dict.setdefault('symbol', None)
        param_dict.setdefault('dso', None)
        stack.append(tidy_function_name(param_dict['symbol'],
                                        param_dict['dso']))

    if opts.include_comm:
        comm = param_dict["comm"].replace(' ', '_')
        sep = "-"
        if opts.include_pid:
            comm = comm + sep + str(param_dict['sample']['pid'])
            sep = "/"
        if opts.include_tid:
            comm = comm + sep + str(param_dict['sample']['tid'])
        stack.append(comm)

    stack_string = ';'.join(reversed(stack))
    lines[stack_string] = lines[stack_string] + 1

def trace_end():
    list = sorted(lines)
    for stack in list:
        print("%s %d" % (stack, lines[stack]))
td class='sub'>Russell King's ARM Linux kernel tree</td><td class='sub right'>Russell King</td></tr></table>
<table class='tabs'><tr><td>
<a href='/cgit/linux-arm.git/'>summary</a><a href='/cgit/linux-arm.git/refs/'>refs</a><a href='/cgit/linux-arm.git/log/drivers/gpu/drm/amd'>log</a><a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd'>tree</a><a href='/cgit/linux-arm.git/commit/drivers/gpu/drm/amd'>commit</a><a class='active' href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>diff</a></td><td class='form'><form class='right' method='get' action='/cgit/linux-arm.git/log/drivers/gpu/drm/amd'>
<input type='hidden' name='id2' value='1e0fb113646182e073539db96016b00cfeb18ecc'/><select name='qt'>
<option value='grep'>log msg</option>
<option value='author'>author</option>
<option value='committer'>committer</option>
<option value='range'>range</option>
</select>
<input class='txt' type='search' size='10' name='q' value=''/>
<input type='submit' value='search'/>
</form>
</td></tr></table>
<div class='path'>path: <a href='/cgit/linux-arm.git/diff/?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>root</a>/<a href='/cgit/linux-arm.git/diff/drivers?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers</a>/<a href='/cgit/linux-arm.git/diff/drivers/gpu?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>gpu</a>/<a href='/cgit/linux-arm.git/diff/drivers/gpu/drm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drm</a>/<a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>amd</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id2' value='1e0fb113646182e073539db96016b00cfeb18ecc'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><div class='diffstat-header'><a href='/cgit/linux-arm.git/diff/?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>Diffstat</a> (limited to 'drivers/gpu/drm/amd')</div><table summary='diffstat' class='diffstat'><tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/acp/include/acp_gfx_if.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/Kconfig?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/Kconfig</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/Makefile</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/aldebaran.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/aldebaran.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu.h</a></td><td class='right'>360</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c</a></td><td class='right'>333</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c</a></td><td class='right'>384</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c</a></td><td class='right'>397</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c</a></td><td class='right'>333</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c</a></td><td class='right'>180</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c</a></td><td class='right'>591</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c</a></td><td class='right'>208</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c</a></td><td class='right'>215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c</a></td><td class='right'>371</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c</a></td><td class='right'>3320</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_df.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c</a></td><td class='right'>811</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c</a></td><td class='right'>183</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</a></td><td class='right'>625</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c</a></td><td class='right'>241</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c</a></td><td class='right'>311</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c</a></td><td class='right'>442</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c</a></td><td class='right'>1437</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c</a></td><td class='right'>676</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c</a></td><td class='right'>345</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_job.c</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_job.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c</a></td><td class='right'>275</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c</a></td><td class='right'>262</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c</a></td><td class='right'>410</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c</a></td><td class='right'>1455</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c</a></td><td class='right'>515</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c</a></td><td class='right'>846</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c</a></td><td class='right'>2365</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h</a></td><td class='right'>227</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c</a></td><td class='right'>735</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c</a></td><td class='right'>283</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c</a></td><td class='right'>506</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c</a></td><td class='right'>329</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c</a></td><td class='right'>576</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c</a></td><td class='right'>428</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c</a></td><td class='right'>616</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c</a></td><td class='right'>1482</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c</a></td><td class='right'>1011</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c</a></td><td class='right'>875</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c</a></td><td class='right'>852</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c</a></td><td class='right'>834</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c</a></td><td class='right'>168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c</a></td><td class='right'>700</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c</a></td><td class='right'>397</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h</a></td><td class='right'>265</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c</a></td><td class='right'>472</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/atom.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atom.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/atom.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atom.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/atombios_dp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atombios_dp.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/atombios_dp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atombios_dp.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atombios_encoders.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/cik.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cik.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/cik_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cik_ih.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/cik_sdma.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cik_sdma.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/cikd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cikd.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/cz_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cz_ih.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v10_0.c</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v11_0.c</a></td><td class='right'>3802</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.6%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v6_0.c</a></td><td class='right'>450</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v8_0.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/df_v1_7.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/df_v1_7.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/df_v3_6.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/df_v3_6.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/df_v4_15.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/df_v4_15.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/df_v4_15.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/df_v4_15.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c</a></td><td class='right'>1514</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v10_1_10_cleaner_shader.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v10_1_10_cleaner_shader.asm</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v10_3_0_cleaner_shader.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v10_3_0_cleaner_shader.asm</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c</a></td><td class='right'>1879</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c</a></td><td class='right'>5793</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v12_0.h</a> (renamed from drivers/gpu/drm/amd/amdgpu/dce_v11_0.h)</td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c</a></td><td class='right'>155</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c</a></td><td class='right'>211</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</a></td><td class='right'>1023</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c</a></td><td class='right'>1205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c</a></td><td class='right'>521</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c</a></td><td class='right'>1070</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v12_0.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c</a></td><td class='right'>535</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/iceland_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/iceland_ih.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ih_v6_0.c</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ih_v6_1.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ih_v7_0.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/imu_v11_0.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/imu_v12_0.c</a></td><td class='right'>406</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/imu_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/imu_v12_0.h</a> (renamed from drivers/gpu/drm/amd/amdgpu/mes_v10_1.h)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c</a></td><td class='right'>235</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c</a></td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c</a></td><td class='right'>665</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c</a></td><td class='right'>303</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c</a></td><td class='right'>1101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_userqueue.c</a></td><td class='right'>501</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mes_userqueue.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_userqueue.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v10_1.c</a></td><td class='right'>1187</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v11_0.c</a></td><td class='right'>689</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v12_0.c</a></td><td class='right'>1942</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mes_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v12_0.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c</a></td><td class='right'>647</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h</a></td><td class='right'>144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c</a></td><td class='right'>235</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/navi10_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/navi10_ih.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nv.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nv.c</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/nvd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nvd.h</a></td><td class='right'>208</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v10_0.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v11_0.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v12_0.c</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v13_0.c</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v14_0.c</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v3_1.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c</a></td><td class='right'>544</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c</a></td><td class='right'>739</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c</a></td><td class='right'>744</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c</a></td><td class='right'>683</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c</a></td><td class='right'>1859</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v7_0.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/si.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si.c</a></td><td class='right'>569</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/si_dma.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si_dma.c</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/si_enums.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si_enums.h</a></td><td class='right'>246</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/si_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si_ih.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sid.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sid.h</a></td><td class='right'>1964</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/soc15.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc15.c</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/soc15.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc15.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/soc15d.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc15d.h</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/soc21.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc21.c</a></td><td class='right'>181</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/soc24.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc24.c</a></td><td class='right'>601</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/soc24.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc24.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ta_ras_if.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/tonga_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/tonga_ih.c</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.c</a></td><td class='right'>632</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.h</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v8_10.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v8_14.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v8_14.c</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v8_14.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v8_14.h</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c</a></td><td class='right'>321</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v1_0.c</a></td><td class='right'>839</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v1_0.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v2_0.c</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v3_0.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v4_0.c</a></td><td class='right'>321</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c</a></td><td class='right'>425</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c</a></td><td class='right'>414</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c</a></td><td class='right'>1328</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c</a></td><td class='right'>867</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c</a></td><td class='right'>924</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c</a></td><td class='right'>1113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c</a></td><td class='right'>990</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c</a></td><td class='right'>805</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c</a></td><td class='right'>1729</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vega10_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vega10_ih.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vega20_ih.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vega20_ih.c</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vi.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vid.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vid.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/Kconfig?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h</a></td><td class='right'>4097</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm</a></td><td class='right'>296</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm</a></td><td class='right'>1136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_chardev.c</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_crat.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_crat.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_crat.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_crat.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_debug.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_debug.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_debug.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_debug.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device.c</a></td><td class='right'>478</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c</a></td><td class='right'>844</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_events.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_events.c</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c</a></td><td class='right'>216</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c</a></td><td class='right'>232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.c</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_module.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_module.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c</a></td><td class='right'>459</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_priv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_priv.h</a></td><td class='right'>140</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_process.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_process.c</a></td><td class='right'>305</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_queue.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_queue.c</a></td><td class='right'>385</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_svm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_svm.c</a></td><td class='right'>348</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_svm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_svm.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_topology.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_topology.c</a></td><td class='right'>219</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_topology.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_topology.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdkfd/soc15_int.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/soc15_int.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/Kconfig?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/Kconfig</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/Makefile</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</a></td><td class='right'>4372</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c</a></td><td class='right'>892</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c</a></td><td class='right'>209</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c)</td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c</a></td><td class='right'>565</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c</a></td><td class='right'>246</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c</a></td><td class='right'>417</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c</a></td><td class='right'>604</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c</a></td><td class='right'>178</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/Makefile</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/basics/dc_common.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/dc_common.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/basics/vector.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/vector.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser.c</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table.c</a></td><td class='right'>290</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table2.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c</a></td><td class='right'>152</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c</a></td><td class='right'>610</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c</a></td><td class='right'>1631</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c</a></td><td class='right'>472</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc.c</a></td><td class='right'>3266</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_debug.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_debug.c</a></td><td class='right'>206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c</a></td><td class='right'>3280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_resource.c</a></td><td class='right'>1207</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_stat.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_stat.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_state.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_state.c</a></td><td class='right'>296</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_stream.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_stream.c</a></td><td class='right'>654</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_surface.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_surface.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc.h</a></td><td class='right'>1392</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_bios_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_bios_types.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c</a></td><td class='right'>1314</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h</a></td><td class='right'>225</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_dp_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dp_types.h</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_dsc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dsc.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_fused_io.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_fused_io.c</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_fused_io.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_fused_io.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_helper.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_hw_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_hw_types.h</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_plane.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_plane.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_plane_priv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_spl_translate.c</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_spl_translate.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_state.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_state.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_state_priv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_state_priv.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_stream.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_stream.h</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_stream_priv.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dc_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_types.h</a></td><td class='right'>276</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/Makefile</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h)</td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h)</td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c)</td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h)</td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c)</td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h)</td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c)</td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c</a></td><td class='right'>2486</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h)</td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c</a></td><td class='right'>915</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.h</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_aux.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_opp.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_opp.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_transform.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_transform.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c</a></td><td class='right'>222</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c</a></td><td class='right'>220</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce112/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce112/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce120/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce120/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce60/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce80/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce80/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn10/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn20/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/Makefile</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn201/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/Makefile</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn21/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/Makefile</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c</a></td><td class='right'>180</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn301/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/Makefile</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn303/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn303/Makefile</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/Makefile</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn314/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn314/Makefile</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn32/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/Makefile</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn321/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn321/Makefile</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/Makefile</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c</a></td><td class='right'>893</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/Makefile</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c)</td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c)</td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h)</td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h)</td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c)</td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c)</td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c)</td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h)</td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c)</td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h)</td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c</a></td><td class='right'>391</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h)</td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c)</td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h)</td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c)</td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c</a></td><td class='right'>856</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h</a></td><td class='right'>240</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dm_helpers.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_helpers.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_pp_smu.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dm_services.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_services.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dm_services_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_services_types.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/Makefile</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c</a></td><td class='right'>368</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/Makefile</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/Makefile</a></td><td class='right'>140</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h)</td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c)</td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h)</td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h)</td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c</a></td><td class='right'>929</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c</a></td><td class='right'>516</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c</a></td><td class='right'>466</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h</a></td><td class='right'>372</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h</a></td><td class='right'>526</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h</a></td><td class='right'>215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h</a></td><td class='right'>744</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c</a></td><td class='right'>661</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c</a></td><td class='right'>13342</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h</a></td><td class='right'>2341</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c</a></td><td class='right'>788</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c</a></td><td class='right'>785</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c</a></td><td class='right'>706</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c</a></td><td class='right'>2390</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c</a></td><td class='right'>1170</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h</a></td><td class='right'>1010</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c)</td><td class='right'>337</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h)</td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c)</td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c)</td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c)</td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h)</td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c)</td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h)</td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c)</td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/Makefile</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c)</td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c)</td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c)</td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h)</td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c)</td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c)</td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c)</td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h)</td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c)</td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h)</td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h)</td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c</a></td><td class='right'>429</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h</a></td><td class='right'>740</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c</a></td><td class='right'>242</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c</a></td><td class='right'>1186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/Makefile</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c</a></td><td class='right'>317</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c</a></td><td class='right'>394</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h</a></td><td class='right'>346</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dsc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dsc.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/Makefile</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c)</td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h)</td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/Makefile</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c</a></td><td class='right'>264</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c</a></td><td class='right'>335</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/Makefile</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c)</td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c)</td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/Makefile</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c)</td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h)</td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c)</td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h)</td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c)</td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h)</td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c)</td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c)</td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c)</td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h)</td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c)</td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h)</td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c</a></td><td class='right'>1271</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h</a></td><td class='right'>206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/Makefile</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c)</td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h)</td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c)</td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h)</td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c)</td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h)</td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c)</td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c)</td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h)</td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c</a></td><td class='right'>1097</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h</a></td><td class='right'>373</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/Makefile</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c</a></td><td class='right'>426</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c)</td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c</a></td><td class='right'>585</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c</a></td><td class='right'>715</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c</a></td><td class='right'>222</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c</a></td><td class='right'>214</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c</a></td><td class='right'>542</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c</a></td><td class='right'>806</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c</a></td><td class='right'>182</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c</a></td><td class='right'>4045</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h</a></td><td class='right'>1556</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/clock_source.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/clock_source.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/core_status.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/core_status.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/core_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/core_types.h</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/audio.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h</a></td><td class='right'>822</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/opp.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/optc.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h</a></td><td class='right'>185</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/transform.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/link_service.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/link_service.h</a> (renamed from drivers/gpu/drm/amd/display/dc/inc/link.h)</td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/reg_helper.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/resource.h</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/Makefile</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c</a></td><td class='right'>381</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c</a></td><td class='right'>414</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/irq_service.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/irq_service.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq/irq_service.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/irq_service.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/irq_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq_types.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_detection.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_detection.c</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_detection.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_detection.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_dpms.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_dpms.c</a></td><td class='right'>270</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_dpms.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_dpms.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_factory.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_factory.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_factory.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_factory.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_resource.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_validation.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_validation.c</a></td><td class='right'>306</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/link_validation.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_validation.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c</a></td><td class='right'>534</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c</a></td><td class='right'>531</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c</a></td><td class='right'>385</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/Makefile</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c)</td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c)</td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c)</td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h)</td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c)</td><td class='right'>388</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h)</td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c</a></td><td class='right'>635</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h</a></td><td class='right'>257</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/Makefile</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c)</td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h)</td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c)</td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h)</td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c)</td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h</a></td><td class='right'>294</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c</a></td><td class='right'>232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c</a></td><td class='right'>300</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c</a></td><td class='right'>552</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/os_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/os_types.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/pg/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/pg/Makefile</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c)</td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/Makefile</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c)</td><td class='right'>127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c</a></td><td class='right'>250</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c)</td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c</a></td><td class='right'>2196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c</a></td><td class='right'>2282</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h</a></td><td class='right'>656</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/Makefile</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c</a></td><td class='right'>1925</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c</a></td><td class='right'>553</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c</a></td><td class='right'>2586</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c</a></td><td class='right'>1233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h</a></td><td class='right'>560</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c</a></td><td class='right'>493</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h</a></td><td class='right'>522</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/dmub_srv.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/dmub_srv.h</a></td><td class='right'>246</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h</a></td><td class='right'>2727</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c</a></td><td class='right'>163</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c</a></td><td class='right'>678</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h</a></td><td class='right'>290</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c</a></td><td class='right'>445</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/bios_parser_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/bios_parser_types.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/dal_asic_id.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/dal_asic_id.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/dal_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/dal_types.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/dpcd_defs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/dpcd_defs.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/fixed31_32.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/fixed31_32.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/gpio_service_interface.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/gpio_service_interface.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/grph_object_id.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/grph_object_id.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/link_service_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/link_service_types.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/logger_interface.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/logger_interface.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/logger_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/logger_types.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/include/signal_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/signal_types.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/color/color_gamma.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/color/color_gamma.c</a></td><td class='right'>309</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/color/color_gamma.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/color/color_gamma.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/freesync/freesync.c</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/power/power_helpers.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/power/power_helpers.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/display/modules/power/power_helpers.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/power/power_helpers.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/amd_acpi.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_acpi.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/amd_cper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_cper.h</a></td><td class='right'>269</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/amd_pcie.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_pcie.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/amd_shared.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_shared.h</a></td><td class='right'>220</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h</a> (renamed from drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_offset.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_sh_mask.h</a> (renamed from drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h</a></td><td class='right'>15485</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h</a></td><td class='right'>61940</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 42.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 57.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h</a></td><td class='right'>16662</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h</a></td><td class='right'>145870</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 100.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 0.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/df/df_4_15_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/df/df_4_15_offset.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/df/df_4_15_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/df/df_4_15_sh_mask.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_sh_mask.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_3_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_3_sh_mask.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_offset.h</a></td><td class='right'>11061</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h</a></td><td class='right'>40550</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 27.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 72.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_offset.h</a></td><td class='right'>1341</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_1_0_sh_mask.h</a></td><td class='right'>6943</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_d.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_d.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_14_0_2_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_14_0_2_offset.h</a></td><td class='right'>511</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_14_0_2_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_14_0_2_sh_mask.h</a></td><td class='right'>1106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h</a></td><td class='right'>940</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_14_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_14_0_offset.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_14_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_14_0_sh_mask.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/atombios.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/atombios.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/atomfirmware.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/atomfirmware.h</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/discovery.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/discovery.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/dm_pp_interface.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/dm_pp_interface.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_11_0_0.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_0_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_0_0.h</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/kgd_kfd_interface.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/kgd_kfd_interface.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/kgd_pp_interface.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/kgd_pp_interface.h</a></td><td class='right'>595</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/mes_api_def.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/mes_api_def.h</a></td><td class='right'>570</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/mes_v11_api_def.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/mes_v11_api_def.h</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/mes_v12_api_def.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/mes_v12_api_def.h</a></td><td class='right'>907</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/pptable.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/pptable.h</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/soc21_enum.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/soc21_enum.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/soc24_enum.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/soc24_enum.h</a></td><td class='right'>21073</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 14.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 85.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/v11_structs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/v11_structs.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/include/v12_structs.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/v12_structs.h</a></td><td class='right'>1189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/amdgpu_dpm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/amdgpu_dpm.c</a></td><td class='right'>427</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/amdgpu_pm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/amdgpu_pm.c</a></td><td class='right'>1759</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c</a></td><td class='right'>144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c</a></td><td class='right'>626</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h</a></td><td class='right'>557</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/hardwaremanager.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/pp_psm.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c</a></td><td class='right'>447</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppevvmath.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppevvmath.h</a></td><td class='right'>555</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_processpptables.c</a></td><td class='right'>574</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c</a></td><td class='right'>900</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h</a></td><td class='right'>286</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h</a></td><td class='right'>1889</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h</a></td><td class='right'>378</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h</a></td><td class='right'>152</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v12_0.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h</a> (renamed from drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h</a></td><td class='right'>204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c</a></td><td class='right'>698</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c</a></td><td class='right'>279</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c</a></td><td class='right'>1515</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c</a></td><td class='right'>168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c</a></td><td class='right'>331</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c</a></td><td class='right'>475</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c</a></td><td class='right'>1073</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c</a></td><td class='right'>1542</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c</a></td><td class='right'>389</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu14/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c</a></td><td class='right'>364</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c</a></td><td class='right'>659</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c</a></td><td class='right'>2932</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h</a></td><td class='right'>128</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/pm/swsmu/smu_internal.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/Makefile</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/Makefile</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c</a></td><td class='right'>182</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c</a></td><td class='right'>648</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c</a></td><td class='right'>279</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/Makefile?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/Makefile</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras.h</a></td><td class='right'>370</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_aca.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_aca.c</a></td><td class='right'>672</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_aca.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_aca.h</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c</a></td><td class='right'>379</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_cmd.c</a></td><td class='right'>522</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_cmd.h</a></td><td class='right'>426</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_core.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_core.c</a></td><td class='right'>603</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_core_status.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_core_status.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_cper.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_cper.c</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_cper.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_cper.h</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c</a></td><td class='right'>1339</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_gfx.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_gfx.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_gfx.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_gfx.h</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c</a></td><td class='right'>426</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h</a></td><td class='right'>259</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c</a></td><td class='right'>317</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_mp1.c</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_mp1.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_mp1.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_nbio.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_nbio.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_nbio.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_process.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_process.c</a></td><td class='right'>322</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_process.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_process.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_psp.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_psp.c</a></td><td class='right'>750</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_psp.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_psp.h</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.c</a> (renamed from drivers/gpu/drm/amd/amdkfd/kfd_pasid.c)</td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_umc.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_umc.c</a></td><td class='right'>707</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_umc.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_umc.h</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c</a></td><td class='right'>511</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux-arm.git/diff/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h?id2=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h</a></td><td class='right'>314</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
</table><div class='diffstat-summary'>1453 files changed, 536574 insertions, 52139 deletions</div><table summary='diff' class='diff'><tr><td><div class='head'>diff --git a/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h b/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h<br/>index feab8eb7f2a8..b26710cae801 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/acp/include/acp_gfx_if.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/acp/include/acp_gfx_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/acp/include/acp_gfx_if.h</a></div><div class='hunk'>@@ -19,7 +19,7 @@</div><div class='ctx'>  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='ctx'>  * OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  *</div><div class='del'>-*/</div><div class='add'>+ */</div><div class='ctx'> </div><div class='ctx'> #ifndef _ACP_GFX_IF_H</div><div class='ctx'> #define _ACP_GFX_IF_H</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig<br/>index 22d88f8ef527..7f515be5185d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/Kconfig?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/Kconfig</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/Kconfig?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/Kconfig</a></div><div class='hunk'>@@ -2,10 +2,13 @@</div><div class='ctx'> </div><div class='ctx'> config DRM_AMDGPU</div><div class='ctx'> 	tristate "AMD GPU"</div><div class='del'>-	depends on DRM &amp;&amp; PCI &amp;&amp; MMU</div><div class='add'>+	depends on DRM &amp;&amp; PCI</div><div class='ctx'> 	depends on !UML</div><div class='ctx'> 	select FW_LOADER</div><div class='add'>+	select DRM_CLIENT</div><div class='add'>+	select DRM_CLIENT_SELECTION</div><div class='ctx'> 	select DRM_DISPLAY_DP_HELPER</div><div class='add'>+	select DRM_DISPLAY_DSC_HELPER</div><div class='ctx'> 	select DRM_DISPLAY_HDMI_HELPER</div><div class='ctx'> 	select DRM_DISPLAY_HDCP_HELPER</div><div class='ctx'> 	select DRM_DISPLAY_HELPER</div><div class='hunk'>@@ -17,11 +20,13 @@ config DRM_AMDGPU</div><div class='ctx'> 	select HWMON</div><div class='ctx'> 	select I2C</div><div class='ctx'> 	select I2C_ALGOBIT</div><div class='add'>+	select CRC16</div><div class='ctx'> 	select BACKLIGHT_CLASS_DEVICE</div><div class='ctx'> 	select INTERVAL_TREE</div><div class='ctx'> 	select DRM_BUDDY</div><div class='ctx'> 	select DRM_SUBALLOC_HELPER</div><div class='ctx'> 	select DRM_EXEC</div><div class='add'>+	select DRM_PANEL_BACKLIGHT_QUIRKS</div><div class='ctx'> 	# amdgpu depends on ACPI_VIDEO when ACPI is enabled, for select to work</div><div class='ctx'> 	# ACPI_VIDEO's dependencies must also be selected.</div><div class='ctx'> 	select INPUT if ACPI</div><div class='hunk'>@@ -38,14 +43,16 @@ config DRM_AMDGPU_SI</div><div class='ctx'> 	bool "Enable amdgpu support for SI parts"</div><div class='ctx'> 	depends on DRM_AMDGPU</div><div class='ctx'> 	help</div><div class='del'>-	  Choose this option if you want to enable experimental support</div><div class='add'>+	  Choose this option if you want to enable support</div><div class='ctx'> 	  for SI (Southern Islands) asics.</div><div class='ctx'> </div><div class='del'>-	  SI is already supported in radeon. Experimental support for SI</div><div class='del'>-	  in amdgpu will be disabled by default and is still provided by</div><div class='del'>-	  radeon. Use module options to override this:</div><div class='add'>+	  SI (Southern Islands) are first generation GCN GPUs,</div><div class='add'>+	  supported by both drivers: radeon (old) and amdgpu (new).</div><div class='add'>+	  By default, SI dedicated GPUs are supported by amdgpu.</div><div class='ctx'> </div><div class='del'>-	  radeon.si_support=0 amdgpu.si_support=1</div><div class='add'>+	  Use module options to override this:</div><div class='add'>+	  To use radeon for SI,</div><div class='add'>+	  radeon.si_support=1 amdgpu.si_support=0</div><div class='ctx'> </div><div class='ctx'> config DRM_AMDGPU_CIK</div><div class='ctx'> 	bool "Enable amdgpu support for CIK parts"</div><div class='hunk'>@@ -54,22 +61,38 @@ config DRM_AMDGPU_CIK</div><div class='ctx'> 	  Choose this option if you want to enable support for CIK (Sea</div><div class='ctx'> 	  Islands) asics.</div><div class='ctx'> </div><div class='del'>-	  CIK is already supported in radeon. Support for CIK in amdgpu</div><div class='del'>-	  will be disabled by default and is still provided by radeon.</div><div class='del'>-	  Use module options to override this:</div><div class='add'>+	  CIK (Sea Islands) are second generation GCN GPUs,</div><div class='add'>+	  supported by both drivers: radeon (old) and amdgpu (new).</div><div class='add'>+	  By default,</div><div class='add'>+	  CIK dedicated GPUs are supported by amdgpu</div><div class='add'>+	  CIK APUs are supported by radeon</div><div class='ctx'> </div><div class='add'>+	  Use module options to override this:</div><div class='add'>+	  To use amdgpu for CIK,</div><div class='ctx'> 	  radeon.cik_support=0 amdgpu.cik_support=1</div><div class='add'>+	  To use radeon for CIK,</div><div class='add'>+	  radeon.cik_support=1 amdgpu.cik_support=0</div><div class='ctx'> </div><div class='ctx'> config DRM_AMDGPU_USERPTR</div><div class='ctx'> 	bool "Always enable userptr write support"</div><div class='ctx'> 	depends on DRM_AMDGPU</div><div class='del'>-	depends on MMU</div><div class='ctx'> 	select HMM_MIRROR</div><div class='ctx'> 	select MMU_NOTIFIER</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option selects CONFIG_HMM and CONFIG_HMM_MIRROR if it</div><div class='ctx'> 	  isn't already selected to enabled full userptr support.</div><div class='ctx'> </div><div class='add'>+config DRM_AMD_ISP</div><div class='add'>+	bool "Enable AMD Image Signal Processor IP support"</div><div class='add'>+	depends on DRM_AMDGPU &amp;&amp; ACPI</div><div class='add'>+	select MFD_CORE</div><div class='add'>+	select PM_GENERIC_DOMAINS if PM</div><div class='add'>+	help</div><div class='add'>+	Choose this option to enable ISP IP support for AMD SOCs.</div><div class='add'>+	This adds the ISP (Image Signal Processor) IP driver and wires</div><div class='add'>+	it up into the amdgpu driver.  It is required for cameras</div><div class='add'>+	on APUs which utilize mipi cameras.</div><div class='add'>+</div><div class='ctx'> config DRM_AMDGPU_WERROR</div><div class='ctx'> 	bool "Force the compiler to throw an error instead of a warning when compiling"</div><div class='ctx'> 	depends on DRM_AMDGPU</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile<br/>index 4536c8ad0e11..c88760fb52ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/Makefile</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> #</div><div class='del'>-# Copyright 2017 Advanced Micro Devices, Inc.</div><div class='add'>+# Copyright 2017-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'> #</div><div class='ctx'> # Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'> # copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'> # Makefile for the drm device driver.  This driver provides support for the</div><div class='ctx'> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.</div><div class='ctx'> </div><div class='del'>-FULL_AMD_PATH=$(srctree)/$(src)/..</div><div class='add'>+FULL_AMD_PATH=$(src)/..</div><div class='ctx'> DISPLAY_FOLDER_NAME=display</div><div class='ctx'> FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME)</div><div class='ctx'> </div><div class='hunk'>@@ -37,25 +37,10 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \</div><div class='ctx'> 	-I$(FULL_AMD_DISPLAY_PATH)/modules/inc \</div><div class='ctx'> 	-I$(FULL_AMD_DISPLAY_PATH)/dc \</div><div class='ctx'> 	-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \</div><div class='del'>-	-I$(FULL_AMD_PATH)/amdkfd</div><div class='del'>-</div><div class='del'>-subdir-ccflags-y := -Wextra</div><div class='del'>-subdir-ccflags-y += -Wunused</div><div class='del'>-subdir-ccflags-y += -Wmissing-prototypes</div><div class='del'>-subdir-ccflags-y += -Wmissing-declarations</div><div class='del'>-subdir-ccflags-y += -Wmissing-include-dirs</div><div class='del'>-subdir-ccflags-y += -Wold-style-definition</div><div class='del'>-subdir-ccflags-y += -Wmissing-format-attribute</div><div class='del'>-# Need this to avoid recursive variable evaluation issues</div><div class='del'>-cond-flags := $(call cc-option, -Wunused-but-set-variable) \</div><div class='del'>-	$(call cc-option, -Wunused-const-variable) \</div><div class='del'>-	$(call cc-option, -Wstringop-truncation) \</div><div class='del'>-	$(call cc-option, -Wpacked-not-aligned)</div><div class='del'>-subdir-ccflags-y += $(cond-flags)</div><div class='del'>-subdir-ccflags-y += -Wno-unused-parameter</div><div class='del'>-subdir-ccflags-y += -Wno-type-limits</div><div class='del'>-subdir-ccflags-y += -Wno-sign-compare</div><div class='del'>-subdir-ccflags-y += -Wno-missing-field-initializers</div><div class='add'>+	-I$(FULL_AMD_PATH)/amdkfd \</div><div class='add'>+	-I$(FULL_AMD_PATH)/ras/ras_mgr</div><div class='add'>+</div><div class='add'>+# Locally disable W=1 warnings enabled in drm subsystem Makefile</div><div class='ctx'> subdir-ccflags-y += -Wno-override-init</div><div class='ctx'> subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror</div><div class='ctx'> </div><div class='hunk'>@@ -70,7 +55,8 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \</div><div class='ctx'> 	amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \</div><div class='ctx'> 	atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \</div><div class='ctx'> 	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \</div><div class='del'>-	amdgpu_dma_buf.o amdgpu_vm.o amdgpu_vm_pt.o amdgpu_ib.o amdgpu_pll.o \</div><div class='add'>+	amdgpu_dma_buf.o amdgpu_vm.o amdgpu_vm_pt.o amdgpu_vm_tlb_fence.o \</div><div class='add'>+	amdgpu_ib.o amdgpu_pll.o \</div><div class='ctx'> 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \</div><div class='ctx'> 	amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \</div><div class='ctx'> 	amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \</div><div class='hunk'>@@ -80,7 +66,8 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \</div><div class='ctx'> 	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \</div><div class='ctx'> 	amdgpu_fw_attestation.o amdgpu_securedisplay.o \</div><div class='ctx'> 	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \</div><div class='del'>-	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o</div><div class='add'>+	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \</div><div class='add'>+	amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o</div><div class='ctx'> </div><div class='ctx'> amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o</div><div class='ctx'> </div><div class='hunk'>@@ -91,21 +78,23 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o \</div><div class='ctx'> 	dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o</div><div class='ctx'> </div><div class='ctx'> amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o \</div><div class='del'>-	uvd_v3_1.o</div><div class='add'>+	uvd_v3_1.o vce_v1_0.o</div><div class='ctx'> </div><div class='ctx'> amdgpu-y += \</div><div class='ctx'> 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \</div><div class='ctx'> 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \</div><div class='del'>-	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \</div><div class='add'>+	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \</div><div class='ctx'> 	sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \</div><div class='del'>-	nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o</div><div class='add'>+	nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \</div><div class='add'>+	cyan_skillfish_reg_init.o</div><div class='ctx'> </div><div class='ctx'> # add DF block</div><div class='ctx'> amdgpu-y += \</div><div class='ctx'> 	df_v1_7.o \</div><div class='ctx'> 	df_v3_6.o \</div><div class='ctx'> 	df_v4_3.o \</div><div class='del'>-	df_v4_6_2.o</div><div class='add'>+	df_v4_6_2.o \</div><div class='add'>+	df_v4_15.o</div><div class='ctx'> </div><div class='ctx'> # add GMC block</div><div class='ctx'> amdgpu-y += \</div><div class='hunk'>@@ -115,11 +104,11 @@ amdgpu-y += \</div><div class='ctx'> 	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \</div><div class='ctx'> 	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \</div><div class='ctx'> 	mmhub_v3_0_1.o gfxhub_v3_0_3.o gfxhub_v1_2.o mmhub_v1_8.o mmhub_v3_3.o \</div><div class='del'>-	gfxhub_v11_5_0.o</div><div class='add'>+	gfxhub_v11_5_0.o mmhub_v4_1_0.o gfxhub_v12_0.o gmc_v12_0.o</div><div class='ctx'> </div><div class='ctx'> # add UMC block</div><div class='ctx'> amdgpu-y += \</div><div class='del'>-	umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v12_0.o</div><div class='add'>+	umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o umc_v8_10.o umc_v12_0.o umc_v8_14.o</div><div class='ctx'> </div><div class='ctx'> # add IH block</div><div class='ctx'> amdgpu-y += \</div><div class='hunk'>@@ -150,7 +139,6 @@ amdgpu-y += \</div><div class='ctx'> # add DCE block</div><div class='ctx'> amdgpu-y += \</div><div class='ctx'> 	dce_v10_0.o \</div><div class='del'>-	dce_v11_0.o \</div><div class='ctx'> 	amdgpu_vkms.o</div><div class='ctx'> </div><div class='ctx'> # add GFX block</div><div class='hunk'>@@ -166,7 +154,9 @@ amdgpu-y += \</div><div class='ctx'> 	imu_v11_0.o \</div><div class='ctx'> 	gfx_v11_0.o \</div><div class='ctx'> 	gfx_v11_0_3.o \</div><div class='del'>-	imu_v11_0_3.o</div><div class='add'>+	imu_v11_0_3.o \</div><div class='add'>+	gfx_v12_0.o \</div><div class='add'>+	imu_v12_0.o</div><div class='ctx'> </div><div class='ctx'> # add async DMA block</div><div class='ctx'> amdgpu-y += \</div><div class='hunk'>@@ -178,13 +168,17 @@ amdgpu-y += \</div><div class='ctx'> 	sdma_v4_4_2.o \</div><div class='ctx'> 	sdma_v5_0.o \</div><div class='ctx'> 	sdma_v5_2.o \</div><div class='del'>-	sdma_v6_0.o</div><div class='add'>+	sdma_v6_0.o \</div><div class='add'>+	sdma_v7_0.o</div><div class='ctx'> </div><div class='ctx'> # add MES block</div><div class='ctx'> amdgpu-y += \</div><div class='ctx'> 	amdgpu_mes.o \</div><div class='del'>-	mes_v10_1.o \</div><div class='del'>-	mes_v11_0.o</div><div class='add'>+	mes_v11_0.o \</div><div class='add'>+	mes_v12_0.o \</div><div class='add'>+</div><div class='add'>+# add GFX userqueue support</div><div class='add'>+amdgpu-y += mes_userqueue.o</div><div class='ctx'> </div><div class='ctx'> # add UVD block</div><div class='ctx'> amdgpu-y += \</div><div class='hunk'>@@ -211,6 +205,7 @@ amdgpu-y += \</div><div class='ctx'> 	vcn_v4_0_3.o \</div><div class='ctx'> 	vcn_v4_0_5.o \</div><div class='ctx'> 	vcn_v5_0_0.o \</div><div class='add'>+	vcn_v5_0_1.o \</div><div class='ctx'> 	amdgpu_jpeg.o \</div><div class='ctx'> 	jpeg_v1_0.o \</div><div class='ctx'> 	jpeg_v2_0.o \</div><div class='hunk'>@@ -219,7 +214,8 @@ amdgpu-y += \</div><div class='ctx'> 	jpeg_v4_0.o \</div><div class='ctx'> 	jpeg_v4_0_3.o \</div><div class='ctx'> 	jpeg_v4_0_5.o \</div><div class='del'>-	jpeg_v5_0_0.o</div><div class='add'>+	jpeg_v5_0_0.o \</div><div class='add'>+	jpeg_v5_0_1.o</div><div class='ctx'> </div><div class='ctx'> # add VPE block</div><div class='ctx'> amdgpu-y += \</div><div class='hunk'>@@ -247,7 +243,8 @@ amdgpu-y += \</div><div class='ctx'> 	smuio_v11_0_6.o \</div><div class='ctx'> 	smuio_v13_0.o \</div><div class='ctx'> 	smuio_v13_0_3.o \</div><div class='del'>-	smuio_v13_0_6.o</div><div class='add'>+	smuio_v13_0_6.o \</div><div class='add'>+	smuio_v14_0_2.o</div><div class='ctx'> </div><div class='ctx'> # add reset block</div><div class='ctx'> amdgpu-y += \</div><div class='hunk'>@@ -260,6 +257,8 @@ amdgpu-y += \</div><div class='ctx'> # add amdkfd interfaces</div><div class='ctx'> amdgpu-y += amdgpu_amdkfd.o</div><div class='ctx'> </div><div class='add'>+# add gfx usermode queue</div><div class='add'>+amdgpu-y += amdgpu_userq.o</div><div class='ctx'> </div><div class='ctx'> ifneq ($(CONFIG_HSA_AMD),)</div><div class='ctx'> AMDKFD_PATH := ../amdkfd</div><div class='hunk'>@@ -275,7 +274,8 @@ amdgpu-y += \</div><div class='ctx'> 	amdgpu_amdkfd_gc_9_4_3.o \</div><div class='ctx'> 	amdgpu_amdkfd_gfx_v10.o \</div><div class='ctx'> 	amdgpu_amdkfd_gfx_v10_3.o \</div><div class='del'>-	amdgpu_amdkfd_gfx_v11.o</div><div class='add'>+	amdgpu_amdkfd_gfx_v11.o \</div><div class='add'>+	amdgpu_amdkfd_gfx_v12.o</div><div class='ctx'> </div><div class='ctx'> ifneq ($(CONFIG_DRM_AMDGPU_CIK),)</div><div class='ctx'> amdgpu-y += amdgpu_amdkfd_gfx_v7.o</div><div class='hunk'>@@ -317,4 +317,17 @@ amdgpu-y += $(AMD_DISPLAY_FILES)</div><div class='ctx'> </div><div class='ctx'> endif</div><div class='ctx'> </div><div class='add'>+# add isp block</div><div class='add'>+ifneq ($(CONFIG_DRM_AMD_ISP),)</div><div class='add'>+amdgpu-y += \</div><div class='add'>+	amdgpu_isp.o \</div><div class='add'>+	isp_v4_1_0.o \</div><div class='add'>+	isp_v4_1_1.o</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+AMD_GPU_RAS_PATH := ../ras</div><div class='add'>+AMD_GPU_RAS_FULL_PATH := $(FULL_AMD_PATH)/ras</div><div class='add'>+include $(AMD_GPU_RAS_FULL_PATH)/Makefile</div><div class='add'>+amdgpu-y += $(AMD_GPU_RAS_FILES)</div><div class='add'>+</div><div class='ctx'> obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c<br/>index 576067d66bb9..daa7b23bc775 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/aldebaran.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/aldebaran.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/aldebaran.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/aldebaran.c</a></div><div class='hunk'>@@ -71,33 +71,41 @@ aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline uint32_t aldebaran_get_ip_block_mask(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GFX) |</div><div class='add'>+				 BIT(AMD_IP_BLOCK_TYPE_SDMA);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;aid_mask)</div><div class='add'>+		ip_block_mask |= BIT(AMD_IP_BLOCK_TYPE_IH);</div><div class='add'>+</div><div class='add'>+	return ip_block_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev);</div><div class='add'>+	uint32_t ip_block;</div><div class='ctx'> 	int r, i;</div><div class='ctx'> </div><div class='add'>+	/* Skip suspend of SDMA IP versions &gt;= 4.4.2. They are multi-aid */</div><div class='add'>+	if (adev-&gt;aid_mask)</div><div class='add'>+		ip_block_mask &amp;= ~BIT(AMD_IP_BLOCK_TYPE_SDMA);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);</div><div class='ctx'> 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);</div><div class='ctx'> </div><div class='ctx'> 	for (i = adev-&gt;num_ip_blocks - 1; i &gt;= 0; i--) {</div><div class='del'>-		if (!(adev-&gt;ip_blocks[i].version-&gt;type ==</div><div class='del'>-			      AMD_IP_BLOCK_TYPE_GFX ||</div><div class='del'>-		      adev-&gt;ip_blocks[i].version-&gt;type ==</div><div class='del'>-			      AMD_IP_BLOCK_TYPE_SDMA))</div><div class='add'>+		ip_block = BIT(adev-&gt;ip_blocks[i].version-&gt;type);</div><div class='add'>+		if (!(ip_block_mask &amp; ip_block))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;suspend(adev);</div><div class='del'>-</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"suspend of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		r = amdgpu_ip_block_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='hunk'>@@ -207,8 +215,10 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];</div><div class='add'>+	uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev);</div><div class='ctx'> 	struct amdgpu_firmware_info *ucode;</div><div class='ctx'> 	struct amdgpu_ip_block *cmn_block;</div><div class='add'>+	struct amdgpu_ip_block *ih_block;</div><div class='ctx'> 	int ucode_count = 0;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='hunk'>@@ -246,10 +256,22 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to get BIF handle\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	r = cmn_block-&gt;version-&gt;funcs-&gt;resume(adev);</div><div class='add'>+	r = amdgpu_ip_block_resume(cmn_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	if (ip_block_mask &amp; BIT(AMD_IP_BLOCK_TYPE_IH)) {</div><div class='add'>+		ih_block = amdgpu_device_ip_get_ip_block(adev,</div><div class='add'>+							 AMD_IP_BLOCK_TYPE_IH);</div><div class='add'>+		if (unlikely(!ih_block)) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to get IH handle\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		r = amdgpu_ip_block_resume(ih_block);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Reinit GFXHUB */</div><div class='ctx'> 	adev-&gt;gfxhub.funcs-&gt;init(adev);</div><div class='ctx'> 	r = adev-&gt;gfxhub.funcs-&gt;gart_enable(adev);</div><div class='hunk'>@@ -282,15 +304,10 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> 		      adev-&gt;ip_blocks[i].version-&gt;type ==</div><div class='ctx'> 			      AMD_IP_BLOCK_TYPE_SDMA))</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = true;</div><div class='add'>+		r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='hunk'>@@ -304,7 +321,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init) {</div><div class='ctx'> 			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init(</div><div class='del'>-				(void *)adev);</div><div class='add'>+				&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				dev_err(adev-&gt;dev,</div><div class='ctx'> 					"late_init of IP block &lt;%s&gt; failed %d after reset\n",</div><div class='hunk'>@@ -316,8 +333,6 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ip_blocks[i].status.late_initialized = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_set_error_query_ready(adev, true);</div><div class='del'>-</div><div class='ctx'> 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);</div><div class='ctx'> 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='hunk'>@@ -344,8 +359,12 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+		amdgpu_set_init_level(tmp_adev,</div><div class='add'>+				AMDGPU_INIT_LEVEL_RESET_RECOVERY);</div><div class='ctx'> 		dev_info(tmp_adev-&gt;dev,</div><div class='ctx'> 			 "GPU reset succeeded, trying to resume\n");</div><div class='add'>+		/*TBD: Ideally should clear only GFX, SDMA blocks*/</div><div class='add'>+		amdgpu_ras_clear_err_state(tmp_adev);</div><div class='ctx'> 		r = aldebaran_mode2_restore_ip(tmp_adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto end;</div><div class='hunk'>@@ -389,6 +408,8 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> 							tmp_adev);</div><div class='ctx'> </div><div class='ctx'> 		if (!r) {</div><div class='add'>+			amdgpu_set_init_level(tmp_adev,</div><div class='add'>+					      AMDGPU_INIT_LEVEL_DEFAULT);</div><div class='ctx'> 			amdgpu_irq_gpu_reset_resume_helper(tmp_adev);</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_ib_ring_tests(tmp_adev);</div><div class='hunk'>@@ -419,6 +440,7 @@ static struct amdgpu_reset_handler aldebaran_mode2_handler = {</div><div class='ctx'> static struct amdgpu_reset_handler</div><div class='ctx'> 	*aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {</div><div class='ctx'> 		&amp;aldebaran_mode2_handler,</div><div class='add'>+		&amp;xgmi_reset_on_init_handler,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> int aldebaran_reset_init(struct amdgpu_device *adev)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br/>index 9c62552bec34..9f9774f58ce1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu.h</a></div><div class='hunk'>@@ -63,6 +63,7 @@</div><div class='ctx'> #include "kgd_pp_interface.h"</div><div class='ctx'> </div><div class='ctx'> #include "amd_shared.h"</div><div class='add'>+#include "amdgpu_utils.h"</div><div class='ctx'> #include "amdgpu_mode.h"</div><div class='ctx'> #include "amdgpu_ih.h"</div><div class='ctx'> #include "amdgpu_irq.h"</div><div class='hunk'>@@ -109,12 +110,20 @@</div><div class='ctx'> #include "amdgpu_mca.h"</div><div class='ctx'> #include "amdgpu_aca.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_cper.h"</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='ctx'> #include "amdgpu_seq64.h"</div><div class='ctx'> #include "amdgpu_reg_state.h"</div><div class='add'>+#include "amdgpu_userq.h"</div><div class='add'>+#include "amdgpu_eviction_fence.h"</div><div class='add'>+#if defined(CONFIG_DRM_AMD_ISP)</div><div class='add'>+#include "amdgpu_isp.h"</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> #define MAX_GPU_INSTANCE		64</div><div class='ctx'> </div><div class='add'>+#define GFX_SLICE_PERIOD_MS		250</div><div class='add'>+</div><div class='ctx'> struct amdgpu_gpu_instance {</div><div class='ctx'> 	struct amdgpu_device		*adev;</div><div class='ctx'> 	int				mgpu_fan_enabled;</div><div class='hunk'>@@ -126,10 +135,6 @@ struct amdgpu_mgpu_info {</div><div class='ctx'> 	uint32_t			num_gpu;</div><div class='ctx'> 	uint32_t			num_dgpu;</div><div class='ctx'> 	uint32_t			num_apu;</div><div class='del'>-</div><div class='del'>-	/* delayed reset_func for XGMI configuration if necessary */</div><div class='del'>-	struct delayed_work		delayed_reset_work;</div><div class='del'>-	bool				pending_reset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_ss {</div><div class='hunk'>@@ -139,6 +144,14 @@ enum amdgpu_ss {</div><div class='ctx'> 	AMDGPU_SS_DRV_UNLOAD</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_hwip_reg_entry {</div><div class='add'>+	u32		hwip;</div><div class='add'>+	u32		inst;</div><div class='add'>+	u32		seg;</div><div class='add'>+	u32		reg_offset;</div><div class='add'>+	const char	*reg_name;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_watchdog_timer {</div><div class='ctx'> 	bool timeout_fatal_disable;</div><div class='ctx'> 	uint32_t period; /* maxCycles = (1 &lt;&lt; period), the number of cycles before a timeout */</div><div class='hunk'>@@ -210,18 +223,21 @@ extern int amdgpu_async_gfx_ring;</div><div class='ctx'> extern int amdgpu_mcbp;</div><div class='ctx'> extern int amdgpu_discovery;</div><div class='ctx'> extern int amdgpu_mes;</div><div class='add'>+extern int amdgpu_mes_log_enable;</div><div class='ctx'> extern int amdgpu_mes_kiq;</div><div class='add'>+extern int amdgpu_uni_mes;</div><div class='ctx'> extern int amdgpu_noretry;</div><div class='ctx'> extern int amdgpu_force_asic_type;</div><div class='ctx'> extern int amdgpu_smartshift_bias;</div><div class='ctx'> extern int amdgpu_use_xgmi_p2p;</div><div class='ctx'> extern int amdgpu_mtype_local;</div><div class='del'>-extern bool enforce_isolation;</div><div class='add'>+extern int amdgpu_enforce_isolation;</div><div class='ctx'> #ifdef CONFIG_HSA_AMD</div><div class='ctx'> extern int sched_policy;</div><div class='ctx'> extern bool debug_evictions;</div><div class='ctx'> extern bool no_system_mem_limit;</div><div class='ctx'> extern int halt_if_hws_hang;</div><div class='add'>+extern uint amdgpu_svm_default_granularity;</div><div class='ctx'> #else</div><div class='ctx'> static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;</div><div class='ctx'> static const bool __maybe_unused debug_evictions; /* = false */</div><div class='hunk'>@@ -244,15 +260,19 @@ extern int amdgpu_cik_support;</div><div class='ctx'> extern int amdgpu_num_kcq;</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)</div><div class='add'>+#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)</div><div class='ctx'> extern int amdgpu_vcnfw_log;</div><div class='ctx'> extern int amdgpu_sg_display;</div><div class='ctx'> extern int amdgpu_umsch_mm;</div><div class='ctx'> extern int amdgpu_seamless;</div><div class='add'>+extern int amdgpu_umsch_mm_fwlog;</div><div class='ctx'> </div><div class='ctx'> extern int amdgpu_user_partt_mode;</div><div class='ctx'> extern int amdgpu_agp;</div><div class='add'>+extern int amdgpu_rebar;</div><div class='ctx'> </div><div class='ctx'> extern int amdgpu_wbrf;</div><div class='add'>+extern int amdgpu_user_queue;</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_VM_MAX_NUM_CTX			4096</div><div class='ctx'> #define AMDGPU_SG_THRESHOLD			(256*1024*1024)</div><div class='hunk'>@@ -285,6 +305,12 @@ extern int amdgpu_wbrf;</div><div class='ctx'> #define AMDGPU_RESET_VCE			(1 &lt;&lt; 13)</div><div class='ctx'> #define AMDGPU_RESET_VCE1			(1 &lt;&lt; 14)</div><div class='ctx'> </div><div class='add'>+/* reset mask */</div><div class='add'>+#define AMDGPU_RESET_TYPE_FULL (1 &lt;&lt; 0) /* full adapter reset, mode1/mode2/BACO/etc. */</div><div class='add'>+#define AMDGPU_RESET_TYPE_SOFT_RESET (1 &lt;&lt; 1) /* IP level soft reset */</div><div class='add'>+#define AMDGPU_RESET_TYPE_PER_QUEUE (1 &lt;&lt; 2) /* per queue */</div><div class='add'>+#define AMDGPU_RESET_TYPE_PER_PIPE (1 &lt;&lt; 3) /* per pipe */</div><div class='add'>+</div><div class='ctx'> /* max cursor sizes (in pixels) */</div><div class='ctx'> #define CIK_CURSOR_WIDTH 128</div><div class='ctx'> #define CIK_CURSOR_HEIGHT 128</div><div class='hunk'>@@ -332,7 +358,6 @@ enum amdgpu_kiq_irq {</div><div class='ctx'> 	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,</div><div class='ctx'> 	AMDGPU_CP_KIQ_IRQ_LAST</div><div class='ctx'> };</div><div class='del'>-#define SRIOV_USEC_TIMEOUT  1200000 /* wait 12 * 100ms for SRIOV */</div><div class='ctx'> #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */</div><div class='ctx'> #define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */</div><div class='ctx'> #define MAX_KIQ_REG_TRY 1000</div><div class='hunk'>@@ -347,10 +372,15 @@ void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 					    u64 *flags);</div><div class='ctx'> int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,</div><div class='ctx'> 				   enum amd_ip_block_type block_type);</div><div class='del'>-bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,</div><div class='add'>+bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev,</div><div class='add'>+			    enum amd_ip_block_type block_type);</div><div class='add'>+bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,</div><div class='ctx'> 			      enum amd_ip_block_type block_type);</div><div class='add'>+int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> </div><div class='del'>-#define AMDGPU_MAX_IP_NUM 16</div><div class='add'>+int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);</div><div class='add'>+</div><div class='add'>+#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_ip_block_status {</div><div class='ctx'> 	bool valid;</div><div class='hunk'>@@ -371,6 +401,7 @@ struct amdgpu_ip_block_version {</div><div class='ctx'> struct amdgpu_ip_block {</div><div class='ctx'> 	struct amdgpu_ip_block_status status;</div><div class='ctx'> 	const struct amdgpu_ip_block_version *version;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,</div><div class='hunk'>@@ -391,6 +422,7 @@ bool amdgpu_get_bios(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_read_bios(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,</div><div class='ctx'> 				     u8 *bios, u32 length_bytes);</div><div class='add'>+void amdgpu_bios_release(struct amdgpu_device *adev);</div><div class='ctx'> /*</div><div class='ctx'>  * Clocks</div><div class='ctx'>  */</div><div class='hunk'>@@ -405,7 +437,6 @@ struct amdgpu_clock {</div><div class='ctx'> 	uint32_t default_mclk;</div><div class='ctx'> 	uint32_t default_sclk;</div><div class='ctx'> 	uint32_t default_dispclk;</div><div class='del'>-	uint32_t current_dispclk;</div><div class='ctx'> 	uint32_t dp_extclk;</div><div class='ctx'> 	uint32_t max_pixel_clock;</div><div class='ctx'> };</div><div class='hunk'>@@ -441,9 +472,6 @@ struct amdgpu_sa_manager {</div><div class='ctx'> 	void				*cpu_ptr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int amdgpu_fence_slab_init(void);</div><div class='del'>-void amdgpu_fence_slab_fini(void);</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * IRQS.</div><div class='ctx'>  */</div><div class='hunk'>@@ -463,7 +491,6 @@ struct amdgpu_flip_work {</div><div class='ctx'> 	bool				async;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * file private structure</div><div class='ctx'>  */</div><div class='hunk'>@@ -476,6 +503,11 @@ struct amdgpu_fpriv {</div><div class='ctx'> 	struct mutex		bo_list_lock;</div><div class='ctx'> 	struct idr		bo_list_handles;</div><div class='ctx'> 	struct amdgpu_ctx_mgr	ctx_mgr;</div><div class='add'>+	struct amdgpu_userq_mgr	userq_mgr;</div><div class='add'>+</div><div class='add'>+	/* Eviction fence infra */</div><div class='add'>+	struct amdgpu_eviction_fence_mgr evf_mgr;</div><div class='add'>+</div><div class='ctx'> 	/** GPU partition selection */</div><div class='ctx'> 	uint32_t		xcp_id;</div><div class='ctx'> };</div><div class='hunk'>@@ -487,12 +519,63 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);</div><div class='ctx'>  */</div><div class='ctx'> #define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_wb - This struct is used for small GPU memory allocation.</div><div class='add'>+ *</div><div class='add'>+ * This struct is used to allocate a small amount of GPU memory that can be</div><div class='add'>+ * used to shadow certain states into the memory. This is especially useful for</div><div class='add'>+ * providing easy CPU access to some states without requiring register access</div><div class='add'>+ * (e.g., if some block is power gated, reading register may be problematic).</div><div class='add'>+ *</div><div class='add'>+ * Note: the term writeback was initially used because many of the amdgpu</div><div class='add'>+ * components had some level of writeback memory, and this struct initially</div><div class='add'>+ * described those components.</div><div class='add'>+ */</div><div class='ctx'> struct amdgpu_wb {</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @wb_obj:</div><div class='add'>+	 *</div><div class='add'>+	 * Buffer Object used for the writeback memory.</div><div class='add'>+	 */</div><div class='ctx'> 	struct amdgpu_bo	*wb_obj;</div><div class='del'>-	volatile uint32_t	*wb;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @wb:</div><div class='add'>+	 *</div><div class='add'>+	 * Pointer to the first writeback slot. In terms of CPU address</div><div class='add'>+	 * this value can be accessed directly by using the offset as an index.</div><div class='add'>+	 * For the GPU address, it is necessary to use gpu_addr and the offset.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t		*wb;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @gpu_addr:</div><div class='add'>+	 *</div><div class='add'>+	 * Writeback base address in the GPU.</div><div class='add'>+	 */</div><div class='ctx'> 	uint64_t		gpu_addr;</div><div class='del'>-	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @num_wb:</div><div class='add'>+	 *</div><div class='add'>+	 * Number of writeback slots reserved for amdgpu.</div><div class='add'>+	 */</div><div class='add'>+	u32			num_wb;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @used:</div><div class='add'>+	 *</div><div class='add'>+	 * Track the writeback slot already used.</div><div class='add'>+	 */</div><div class='ctx'> 	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @lock:</div><div class='add'>+	 *</div><div class='add'>+	 * Protects read and write of the used field array.</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t		lock;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);</div><div class='hunk'>@@ -525,6 +608,7 @@ struct amdgpu_allowed_register_entry {</div><div class='ctx'>  *                   are reset depends on the ASIC. Notably doesn't reset IPs</div><div class='ctx'>  *                   shared with the CPU on APUs or the memory controllers (so</div><div class='ctx'>  *                   VRAM is not lost). Not available on all ASICs.</div><div class='add'>+ * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs</div><div class='ctx'>  * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card</div><div class='ctx'>  *                  but without powering off the PCI bus. Suitable only for</div><div class='ctx'>  *                  discrete GPUs.</div><div class='hunk'>@@ -542,8 +626,10 @@ enum amd_reset_method {</div><div class='ctx'> 	AMD_RESET_METHOD_MODE0,</div><div class='ctx'> 	AMD_RESET_METHOD_MODE1,</div><div class='ctx'> 	AMD_RESET_METHOD_MODE2,</div><div class='add'>+	AMD_RESET_METHOD_LINK,</div><div class='ctx'> 	AMD_RESET_METHOD_BACO,</div><div class='ctx'> 	AMD_RESET_METHOD_PCI,</div><div class='add'>+	AMD_RESET_METHOD_ON_INIT,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_video_codec_info {</div><div class='hunk'>@@ -605,7 +691,7 @@ struct amdgpu_asic_funcs {</div><div class='ctx'> 	/* PCIe replay counter */</div><div class='ctx'> 	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);</div><div class='ctx'> 	/* device supports BACO */</div><div class='del'>-	bool (*supports_baco)(struct amdgpu_device *adev);</div><div class='add'>+	int (*supports_baco)(struct amdgpu_device *adev);</div><div class='ctx'> 	/* pre asic_init quirks */</div><div class='ctx'> 	void (*pre_asic_init)(struct amdgpu_device *adev);</div><div class='ctx'> 	/* enter/exit umd stable pstate */</div><div class='hunk'>@@ -637,7 +723,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> /* VRAM scratch page for HDP bug, default vram page */</div><div class='ctx'> struct amdgpu_mem_scratch {</div><div class='ctx'> 	struct amdgpu_bo		*robj;</div><div class='del'>-	volatile uint32_t		*ptr;</div><div class='add'>+	uint32_t			*ptr;</div><div class='ctx'> 	u64				gpu_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -668,6 +754,7 @@ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, u</div><div class='ctx'> struct amdgpu_mmio_remap {</div><div class='ctx'> 	u32 reg_offset;</div><div class='ctx'> 	resource_size_t bus_addr;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Define the HW IP blocks will be used in driver , add more if necessary */</div><div class='hunk'>@@ -707,6 +794,7 @@ enum amd_hw_ip_block_type {</div><div class='ctx'> 	XGMI_HWIP,</div><div class='ctx'> 	DCI_HWIP,</div><div class='ctx'> 	PCIE_HWIP,</div><div class='add'>+	ISP_HWIP,</div><div class='ctx'> 	MAX_HWIP</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -734,13 +822,25 @@ struct amdgpu_ip_map_info {</div><div class='ctx'> 					uint32_t mask);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum amdgpu_uid_type {</div><div class='add'>+	AMDGPU_UID_TYPE_XCD,</div><div class='add'>+	AMDGPU_UID_TYPE_AID,</div><div class='add'>+	AMDGPU_UID_TYPE_SOC,</div><div class='add'>+	AMDGPU_UID_TYPE_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */</div><div class='add'>+</div><div class='add'>+struct amdgpu_uid {</div><div class='add'>+	uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX];</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amd_powerplay {</div><div class='ctx'> 	void *pp_handle;</div><div class='ctx'> 	const struct amd_pm_funcs *pp_funcs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct ip_discovery_top;</div><div class='del'>-</div><div class='ctx'> /* polaris10 kickers */</div><div class='ctx'> #define ASICID_IS_P20(did, rid)		(((did == 0x67DF) &amp;&amp; \</div><div class='ctx'> 					 ((rid == 0xE3) || \</div><div class='hunk'>@@ -793,6 +893,12 @@ struct amdgpu_mqd_prop {</div><div class='ctx'> 	uint32_t hqd_queue_priority;</div><div class='ctx'> 	bool allow_tunneling;</div><div class='ctx'> 	bool hqd_active;</div><div class='add'>+	uint64_t shadow_addr;</div><div class='add'>+	uint64_t gds_bkup_addr;</div><div class='add'>+	uint64_t csa_addr;</div><div class='add'>+	uint64_t fence_address;</div><div class='add'>+	bool tmz_queue;</div><div class='add'>+	bool kernel_queue;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_mqd {</div><div class='hunk'>@@ -801,27 +907,46 @@ struct amdgpu_mqd {</div><div class='ctx'> 			struct amdgpu_mqd_prop *p);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_pcie_reset_ctx {</div><div class='add'>+	bool in_link_reset;</div><div class='add'>+	bool occurs_dpc;</div><div class='add'>+	bool audio_suspended;</div><div class='add'>+	struct pci_dev *swus;</div><div class='add'>+	struct pci_saved_state *swus_pcistate;</div><div class='add'>+	struct pci_saved_state *swds_pcistate;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Custom Init levels could be defined for different situations where a full</div><div class='add'>+ * initialization of all hardware blocks are not expected. Sample cases are</div><div class='add'>+ * custom init sequences after resume after S0i3/S3, reset on initialization,</div><div class='add'>+ * partial reset of blocks etc. Presently, this defines only two levels. Levels</div><div class='add'>+ * are described in corresponding struct definitions - amdgpu_init_default,</div><div class='add'>+ * amdgpu_init_minimal_xgmi.</div><div class='add'>+ */</div><div class='add'>+enum amdgpu_init_lvl_id {</div><div class='add'>+	AMDGPU_INIT_LEVEL_DEFAULT,</div><div class='add'>+	AMDGPU_INIT_LEVEL_MINIMAL_XGMI,</div><div class='add'>+	AMDGPU_INIT_LEVEL_RESET_RECOVERY,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_init_level {</div><div class='add'>+	enum amdgpu_init_lvl_id level;</div><div class='add'>+	uint32_t hwini_ip_block_mask;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define AMDGPU_RESET_MAGIC_NUM 64</div><div class='ctx'> #define AMDGPU_MAX_DF_PERFMONS 4</div><div class='ctx'> struct amdgpu_reset_domain;</div><div class='ctx'> struct amdgpu_fru_info;</div><div class='ctx'> </div><div class='del'>-struct amdgpu_reset_info {</div><div class='del'>-	/* reset dump register */</div><div class='del'>-	u32 *reset_dump_reg_list;</div><div class='del'>-	u32 *reset_dump_reg_value;</div><div class='del'>-	int num_regs;</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_DEV_COREDUMP</div><div class='del'>-	struct amdgpu_coredump_info *coredump_info;</div><div class='del'>-#endif</div><div class='add'>+enum amdgpu_enforce_isolation_mode {</div><div class='add'>+	AMDGPU_ENFORCE_ISOLATION_DISABLE = 0,</div><div class='add'>+	AMDGPU_ENFORCE_ISOLATION_ENABLE = 1,</div><div class='add'>+	AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2,</div><div class='add'>+	AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.</div><div class='del'>- */</div><div class='del'>-#define AMDGPU_HAS_VRAM(_adev) ((_adev)-&gt;gmc.real_vram_size)</div><div class='del'>-</div><div class='ctx'> struct amdgpu_device {</div><div class='ctx'> 	struct device			*dev;</div><div class='ctx'> 	struct pci_dev			*pdev;</div><div class='hunk'>@@ -845,9 +970,9 @@ struct amdgpu_device {</div><div class='ctx'> 	bool				need_swiotlb;</div><div class='ctx'> 	bool				accel_working;</div><div class='ctx'> 	struct notifier_block		acpi_nb;</div><div class='add'>+	struct notifier_block		pm_nb;</div><div class='ctx'> 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];</div><div class='del'>-	struct debugfs_blob_wrapper     debugfs_vbios_blob;</div><div class='del'>-	struct debugfs_blob_wrapper     debugfs_discovery_blob;</div><div class='add'>+	struct debugfs_blob_wrapper debugfs_vbios_blob;</div><div class='ctx'> 	struct mutex			srbm_mutex;</div><div class='ctx'> 	/* GRBM index mutex. Protects concurrent access to GRBM index */</div><div class='ctx'> 	struct mutex                    grbm_idx_mutex;</div><div class='hunk'>@@ -937,6 +1062,9 @@ struct amdgpu_device {</div><div class='ctx'> 		u32			log2_max_MBps;</div><div class='ctx'> 	} mm_stats;</div><div class='ctx'> </div><div class='add'>+	/* discovery*/</div><div class='add'>+	struct amdgpu_discovery_info discovery;</div><div class='add'>+</div><div class='ctx'> 	/* display */</div><div class='ctx'> 	bool				enable_virtual_display;</div><div class='ctx'> 	struct amdgpu_vkms_output       *amdgpu_vkms_output;</div><div class='hunk'>@@ -1024,20 +1152,36 @@ struct amdgpu_device {</div><div class='ctx'> 	/* for userq and VM fences */</div><div class='ctx'> 	struct amdgpu_seq64		seq64;</div><div class='ctx'> </div><div class='del'>-	/* KFD */</div><div class='del'>-	struct amdgpu_kfd_dev		kfd;</div><div class='del'>-</div><div class='ctx'> 	/* UMC */</div><div class='ctx'> 	struct amdgpu_umc		umc;</div><div class='ctx'> </div><div class='ctx'> 	/* display related functionality */</div><div class='ctx'> 	struct amdgpu_display_manager dm;</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_ISP)</div><div class='add'>+	/* isp */</div><div class='add'>+	struct amdgpu_isp		isp;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	/* mes */</div><div class='ctx'> 	bool                            enable_mes;</div><div class='ctx'> 	bool                            enable_mes_kiq;</div><div class='add'>+	bool                            enable_uni_mes;</div><div class='ctx'> 	struct amdgpu_mes               mes;</div><div class='ctx'> 	struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM];</div><div class='add'>+</div><div class='add'>+	/* xarray used to retrieve the user queue fence driver reference</div><div class='add'>+	 * in the EOP interrupt handler to signal the particular user</div><div class='add'>+	 * queue fence.</div><div class='add'>+	 */</div><div class='add'>+	struct xarray			userq_xa;</div><div class='add'>+	/**</div><div class='add'>+	 * @userq_doorbell_xa: Global user queue map (doorbell index → queue)</div><div class='add'>+	 * Key: doorbell_index (unique global identifier for the queue)</div><div class='add'>+	 * Value: struct amdgpu_usermode_queue</div><div class='add'>+	 */</div><div class='add'>+	struct xarray userq_doorbell_xa;</div><div class='ctx'> </div><div class='ctx'> 	/* df */</div><div class='ctx'> 	struct amdgpu_df                df;</div><div class='hunk'>@@ -1048,6 +1192,9 @@ struct amdgpu_device {</div><div class='ctx'> 	/* ACA */</div><div class='ctx'> 	struct amdgpu_aca		aca;</div><div class='ctx'> </div><div class='add'>+	/* CPER */</div><div class='add'>+	struct amdgpu_cper		cper;</div><div class='add'>+</div><div class='ctx'> 	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];</div><div class='ctx'> 	uint32_t		        harvest_ip_mask;</div><div class='ctx'> 	int				num_ip_blocks;</div><div class='hunk'>@@ -1068,10 +1215,6 @@ struct amdgpu_device {</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_virt	virt;</div><div class='ctx'> </div><div class='del'>-	/* link all shadow bo */</div><div class='del'>-	struct list_head                shadow_list;</div><div class='del'>-	struct mutex                    shadow_list_lock;</div><div class='del'>-</div><div class='ctx'> 	/* record hw reset is performed */</div><div class='ctx'> 	bool has_hw_reset;</div><div class='ctx'> 	u8				reset_magic[AMDGPU_RESET_MAGIC_NUM];</div><div class='hunk'>@@ -1081,8 +1224,7 @@ struct amdgpu_device {</div><div class='ctx'> 	bool				in_s3;</div><div class='ctx'> 	bool				in_s4;</div><div class='ctx'> 	bool				in_s0ix;</div><div class='del'>-	/* indicate amdgpu suspension status */</div><div class='del'>-	bool				suspend_complete;</div><div class='add'>+	suspend_state_t			last_suspend_state;</div><div class='ctx'> </div><div class='ctx'> 	enum pp_mp1_state               mp1_state;</div><div class='ctx'> 	struct amdgpu_doorbell_index doorbell_index;</div><div class='hunk'>@@ -1113,11 +1255,14 @@ struct amdgpu_device {</div><div class='ctx'> 	struct ratelimit_state		throttling_logging_rs;</div><div class='ctx'> 	uint32_t                        ras_hw_enabled;</div><div class='ctx'> 	uint32_t                        ras_enabled;</div><div class='add'>+	bool                            ras_default_ecc_enabled;</div><div class='ctx'> </div><div class='ctx'> 	bool                            no_hw_access;</div><div class='ctx'> 	struct pci_saved_state          *pci_state;</div><div class='ctx'> 	pci_channel_state_t		pci_channel_state;</div><div class='ctx'> </div><div class='add'>+	struct amdgpu_pcie_reset_ctx	pcie_reset_ctx;</div><div class='add'>+</div><div class='ctx'> 	/* Track auto wait count on s_barrier settings */</div><div class='ctx'> 	bool				barrier_has_auto_waitcnt;</div><div class='ctx'> </div><div class='hunk'>@@ -1128,20 +1273,15 @@ struct amdgpu_device {</div><div class='ctx'> </div><div class='ctx'> 	struct list_head                ras_list;</div><div class='ctx'> </div><div class='del'>-	struct ip_discovery_top         *ip_top;</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_reset_domain	*reset_domain;</div><div class='ctx'> </div><div class='ctx'> 	struct mutex			benchmark_mutex;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_reset_info	reset_info;</div><div class='del'>-</div><div class='ctx'> 	bool                            scpm_enabled;</div><div class='ctx'> 	uint32_t                        scpm_status;</div><div class='ctx'> </div><div class='ctx'> 	struct work_struct		reset_work;</div><div class='ctx'> </div><div class='del'>-	bool                            job_hang;</div><div class='ctx'> 	bool                            dc_enabled;</div><div class='ctx'> 	/* Mask of active clusters */</div><div class='ctx'> 	uint32_t			aid_mask;</div><div class='hunk'>@@ -1151,6 +1291,38 @@ struct amdgpu_device {</div><div class='ctx'> 	bool                            debug_largebar;</div><div class='ctx'> 	bool                            debug_disable_soft_recovery;</div><div class='ctx'> 	bool                            debug_use_vram_fw_buf;</div><div class='add'>+	bool                            debug_enable_ras_aca;</div><div class='add'>+	bool                            debug_exp_resets;</div><div class='add'>+	bool                            debug_disable_gpu_ring_reset;</div><div class='add'>+	bool                            debug_vm_userptr;</div><div class='add'>+	bool                            debug_disable_ce_logs;</div><div class='add'>+	bool                            debug_enable_ce_cs;</div><div class='add'>+</div><div class='add'>+	/* Protection for the following isolation structure */</div><div class='add'>+	struct mutex                    enforce_isolation_mutex;</div><div class='add'>+	enum amdgpu_enforce_isolation_mode	enforce_isolation[MAX_XCP];</div><div class='add'>+	struct amdgpu_isolation {</div><div class='add'>+		void			*owner;</div><div class='add'>+		struct dma_fence	*spearhead;</div><div class='add'>+		struct amdgpu_sync	active;</div><div class='add'>+		struct amdgpu_sync	prev;</div><div class='add'>+	} isolation[MAX_XCP];</div><div class='add'>+</div><div class='add'>+	struct amdgpu_init_level *init_lvl;</div><div class='add'>+</div><div class='add'>+	/* This flag is used to determine how VRAM allocations are handled for APUs</div><div class='add'>+	 * in KFD: VRAM or GTT.</div><div class='add'>+	 */</div><div class='add'>+	bool                            apu_prefer_gtt;</div><div class='add'>+</div><div class='add'>+	bool                            userq_halt_for_enforce_isolation;</div><div class='add'>+	struct work_struct              userq_reset_work;</div><div class='add'>+	struct amdgpu_uid *uid_info;</div><div class='add'>+</div><div class='add'>+	/* KFD</div><div class='add'>+	 * Must be last --ends in a flexible-array member.</div><div class='add'>+	 */</div><div class='add'>+	struct amdgpu_kfd_dev		kfd;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,</div><div class='hunk'>@@ -1184,6 +1356,11 @@ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)</div><div class='ctx'> 	return container_of(bdev, struct amdgpu_device, mman.bdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return !!adev-&gt;aid_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 		       uint32_t flags);</div><div class='ctx'> void amdgpu_device_fini_hw(struct amdgpu_device *adev);</div><div class='hunk'>@@ -1235,7 +1412,8 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,</div><div class='ctx'> void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,</div><div class='ctx'> 				   u64 reg_addr, u64 reg_data);</div><div class='ctx'> u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);</div><div class='del'>-bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);</div><div class='add'>+bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,</div><div class='add'>+				       enum amd_asic_type asic_type);</div><div class='ctx'> bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);</div><div class='hunk'>@@ -1246,6 +1424,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 			 struct amdgpu_reset_context *reset_context);</div><div class='ctx'> </div><div class='add'>+int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context);</div><div class='add'>+</div><div class='ctx'> int emu_soc_asic_init(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -1360,11 +1540,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);</div><div class='ctx'> #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)-&gt;asic_funcs-&gt;read_bios_from_rom((adev), (b), (l))</div><div class='ctx'> #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)-&gt;asic_funcs-&gt;read_register((adev), (se), (sh), (offset), (v)))</div><div class='ctx'> #define amdgpu_asic_get_config_memsize(adev) (adev)-&gt;asic_funcs-&gt;get_config_memsize((adev))</div><div class='del'>-#define amdgpu_asic_flush_hdp(adev, r) \</div><div class='del'>-	((adev)-&gt;asic_funcs-&gt;flush_hdp ? (adev)-&gt;asic_funcs-&gt;flush_hdp((adev), (r)) : (adev)-&gt;hdp.funcs-&gt;flush_hdp((adev), (r)))</div><div class='del'>-#define amdgpu_asic_invalidate_hdp(adev, r) \</div><div class='del'>-	((adev)-&gt;asic_funcs-&gt;invalidate_hdp ? (adev)-&gt;asic_funcs-&gt;invalidate_hdp((adev), (r)) : \</div><div class='del'>-	 ((adev)-&gt;hdp.funcs-&gt;invalidate_hdp ? (adev)-&gt;hdp.funcs-&gt;invalidate_hdp((adev), (r)) : (void)0))</div><div class='ctx'> #define amdgpu_asic_need_full_reset(adev) (adev)-&gt;asic_funcs-&gt;need_full_reset((adev))</div><div class='ctx'> #define amdgpu_asic_init_doorbell_index(adev) (adev)-&gt;asic_funcs-&gt;init_doorbell_index((adev))</div><div class='ctx'> #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)-&gt;asic_funcs-&gt;get_pcie_usage((adev), (cnt0), (cnt1)))</div><div class='hunk'>@@ -1403,15 +1578,17 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,</div><div class='ctx'> 					     const u32 array_size);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_device_mode1_reset(struct amdgpu_device *adev);</div><div class='del'>-bool amdgpu_device_supports_atpx(struct drm_device *dev);</div><div class='del'>-bool amdgpu_device_supports_px(struct drm_device *dev);</div><div class='del'>-bool amdgpu_device_supports_boco(struct drm_device *dev);</div><div class='del'>-bool amdgpu_device_supports_smart_shift(struct drm_device *dev);</div><div class='del'>-bool amdgpu_device_supports_baco(struct drm_device *dev);</div><div class='add'>+int amdgpu_device_link_reset(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_device_supports_atpx(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_device_supports_px(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_device_supports_boco(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_device_supports_baco(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,</div><div class='ctx'> 				      struct amdgpu_device *peer_adev);</div><div class='del'>-int amdgpu_device_baco_enter(struct drm_device *dev);</div><div class='del'>-int amdgpu_device_baco_exit(struct drm_device *dev);</div><div class='add'>+int amdgpu_device_baco_enter(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_device_baco_exit(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_device_flush_hdp(struct amdgpu_device *adev,</div><div class='ctx'> 		struct amdgpu_ring *ring);</div><div class='hunk'>@@ -1423,9 +1600,15 @@ u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,</div><div class='ctx'> 				u32 reg);</div><div class='ctx'> void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,</div><div class='ctx'> 				u32 reg, u32 v);</div><div class='add'>+struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);</div><div class='ctx'> struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,</div><div class='ctx'> 					    struct dma_fence *gang);</div><div class='add'>+struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+						  struct amdgpu_ring *ring,</div><div class='add'>+						  struct amdgpu_job *job);</div><div class='ctx'> bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);</div><div class='add'>+ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);</div><div class='add'>+ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);</div><div class='ctx'> </div><div class='ctx'> /* atpx handler */</div><div class='ctx'> #if defined(CONFIG_VGA_SWITCHEROO)</div><div class='hunk'>@@ -1433,23 +1616,15 @@ void amdgpu_register_atpx_handler(void);</div><div class='ctx'> void amdgpu_unregister_atpx_handler(void);</div><div class='ctx'> bool amdgpu_has_atpx_dgpu_power_cntl(void);</div><div class='ctx'> bool amdgpu_is_atpx_hybrid(void);</div><div class='del'>-bool amdgpu_atpx_dgpu_req_power_for_displays(void);</div><div class='ctx'> bool amdgpu_has_atpx(void);</div><div class='ctx'> #else</div><div class='ctx'> static inline void amdgpu_register_atpx_handler(void) {}</div><div class='ctx'> static inline void amdgpu_unregister_atpx_handler(void) {}</div><div class='ctx'> static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }</div><div class='ctx'> static inline bool amdgpu_is_atpx_hybrid(void) { return false; }</div><div class='del'>-static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }</div><div class='ctx'> static inline bool amdgpu_has_atpx(void) { return false; }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-#if defined(CONFIG_VGA_SWITCHEROO) &amp;&amp; defined(CONFIG_ACPI)</div><div class='del'>-void *amdgpu_atpx_get_dhandle(void);</div><div class='del'>-#else</div><div class='del'>-static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * KMS</div><div class='ctx'>  */</div><div class='hunk'>@@ -1458,14 +1633,13 @@ extern const int amdgpu_max_kms_ioctl;</div><div class='ctx'> </div><div class='ctx'> int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);</div><div class='ctx'> void amdgpu_driver_unload_kms(struct drm_device *dev);</div><div class='del'>-void amdgpu_driver_lastclose_kms(struct drm_device *dev);</div><div class='ctx'> int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);</div><div class='ctx'> void amdgpu_driver_postclose_kms(struct drm_device *dev,</div><div class='ctx'> 				 struct drm_file *file_priv);</div><div class='ctx'> void amdgpu_driver_release_kms(struct drm_device *dev);</div><div class='ctx'> </div><div class='del'>-int amdgpu_device_ip_suspend(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_device_prepare(struct drm_device *dev);</div><div class='add'>+void amdgpu_device_complete(struct drm_device *dev);</div><div class='ctx'> int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);</div><div class='ctx'> int amdgpu_device_resume(struct drm_device *dev, bool fbcon);</div><div class='ctx'> u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);</div><div class='hunk'>@@ -1516,7 +1690,8 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,</div><div class='ctx'> 						u8 perf_req, bool advertise);</div><div class='ctx'> int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,</div><div class='ctx'> 				    u8 dev_state, bool drv_state);</div><div class='del'>-int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);</div><div class='add'>+int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,</div><div class='add'>+				   enum amdgpu_ss ss_state);</div><div class='ctx'> int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,</div><div class='ctx'> 			     u64 *tmr_size);</div><div class='hunk'>@@ -1547,27 +1722,26 @@ static inline void amdgpu_acpi_release(void) { }</div><div class='ctx'> static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }</div><div class='ctx'> static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,</div><div class='ctx'> 						  u8 dev_state, bool drv_state) { return 0; }</div><div class='del'>-static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,</div><div class='del'>-						 enum amdgpu_ss ss_state) { return 0; }</div><div class='add'>+static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,</div><div class='add'>+						 enum amdgpu_ss ss_state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_ACPI) &amp;&amp; defined(CONFIG_SUSPEND)</div><div class='ctx'> bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);</div><div class='del'>-void amdgpu_choose_low_power_state(struct amdgpu_device *adev);</div><div class='ctx'> #else</div><div class='ctx'> static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }</div><div class='ctx'> static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }</div><div class='del'>-static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-#if defined(CONFIG_DRM_AMD_DC)</div><div class='del'>-int amdgpu_dm_display_resume(struct amdgpu_device *adev );</div><div class='del'>-#else</div><div class='del'>-static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }</div><div class='add'>+#if defined(CONFIG_DRM_AMD_ISP)</div><div class='add'>+int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> void amdgpu_register_gpu_instance(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1609,4 +1783,26 @@ extern const struct attribute_group amdgpu_vram_mgr_attr_group;</div><div class='ctx'> extern const struct attribute_group amdgpu_gtt_mgr_attr_group;</div><div class='ctx'> extern const struct attribute_group amdgpu_flash_attr_group;</div><div class='ctx'> </div><div class='add'>+void amdgpu_set_init_level(struct amdgpu_device *adev,</div><div class='add'>+			   enum amdgpu_init_lvl_id lvl);</div><div class='add'>+</div><div class='add'>+static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+       u32 status;</div><div class='add'>+       int r;</div><div class='add'>+</div><div class='add'>+       r = pci_read_config_dword(adev-&gt;pdev, PCI_COMMAND, &amp;status);</div><div class='add'>+       if (r || PCI_POSSIBLE_ERROR(status)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "device lost from bus!");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+       }</div><div class='add'>+</div><div class='add'>+       return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_device_set_uid(struct amdgpu_uid *uid_info,</div><div class='add'>+			   enum amdgpu_uid_type type, uint8_t inst,</div><div class='add'>+			   uint64_t uid);</div><div class='add'>+uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info,</div><div class='add'>+			       enum amdgpu_uid_type type, uint8_t inst);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c<br/>index 493982f94649..9b3180449150 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c</a></div><div class='hunk'>@@ -28,17 +28,7 @@</div><div class='ctx'> </div><div class='ctx'> #define ACA_BANK_HWID(type, hwid, mcatype) [ACA_HWIP_TYPE_##type] = {hwid, mcatype}</div><div class='ctx'> </div><div class='del'>-typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, void *data);</div><div class='del'>-</div><div class='del'>-struct aca_banks {</div><div class='del'>-	int nr_banks;</div><div class='del'>-	struct list_head list;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct aca_hwip {</div><div class='del'>-	int hwid;</div><div class='del'>-	int mcatype;</div><div class='del'>-};</div><div class='add'>+typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);</div><div class='ctx'> </div><div class='ctx'> static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = {</div><div class='ctx'> 	ACA_BANK_HWID(SMU,	0x01,	0x01),</div><div class='hunk'>@@ -80,13 +70,17 @@ static void aca_banks_release(struct aca_banks *banks)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_bank_node *node, *tmp;</div><div class='ctx'> </div><div class='add'>+	if (list_empty(&amp;banks-&gt;list))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(node, tmp, &amp;banks-&gt;list, node) {</div><div class='ctx'> 		list_del(&amp;node-&gt;node);</div><div class='ctx'> 		kvfree(node);</div><div class='add'>+		banks-&gt;nr_banks--;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_error_type type, u32 *count)</div><div class='add'>+static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='ctx'> 	const struct aca_smu_funcs *smu_funcs = aca-&gt;smu_funcs;</div><div class='hunk'>@@ -108,7 +102,7 @@ static struct aca_regs_dump {</div><div class='ctx'> 	{"STATUS",		ACA_REG_IDX_STATUS},</div><div class='ctx'> 	{"ADDR",		ACA_REG_IDX_ADDR},</div><div class='ctx'> 	{"MISC",		ACA_REG_IDX_MISC0},</div><div class='del'>-	{"CONFIG",		ACA_REG_IDX_CONFG},</div><div class='add'>+	{"CONFIG",		ACA_REG_IDX_CONFIG},</div><div class='ctx'> 	{"IPID",		ACA_REG_IDX_IPID},</div><div class='ctx'> 	{"SYND",		ACA_REG_IDX_SYND},</div><div class='ctx'> 	{"DESTAT",		ACA_REG_IDX_DESTAT},</div><div class='hunk'>@@ -116,20 +110,51 @@ static struct aca_regs_dump {</div><div class='ctx'> 	{"CONTROL_MASK",	ACA_REG_IDX_CTL_MASK},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank)</div><div class='add'>+static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank,</div><div class='add'>+			      struct ras_query_context *qctx)</div><div class='ctx'> {</div><div class='add'>+	u64 event_id = qctx ? qctx-&gt;evid.event_id : RAS_EVENT_INVALID_ID;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "Accelerator Check Architecture events logged\n");</div><div class='add'>+	if (adev-&gt;debug_disable_ce_logs &amp;&amp;</div><div class='add'>+	    bank-&gt;smu_err_type == ACA_SMU_TYPE_CE &amp;&amp;</div><div class='add'>+	    !ACA_BANK_ERR_IS_DEFFERED(bank))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");</div><div class='ctx'> 	/* plus 1 for output format, e.g: ACA[08/08]: xxxx */</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(aca_regs); i++)</div><div class='del'>-		dev_info(adev-&gt;dev, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",</div><div class='del'>-			 idx + 1, total, aca_regs[i].name, bank-&gt;regs[aca_regs[i].reg_idx]);</div><div class='add'>+		RAS_EVENT_LOG(adev, event_id, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",</div><div class='add'>+			      idx + 1, total, aca_regs[i].name, bank-&gt;regs[aca_regs[i].reg_idx]);</div><div class='add'>+</div><div class='add'>+	if (ACA_REG__STATUS__SCRUB(bank-&gt;regs[ACA_REG_IDX_STATUS]))</div><div class='add'>+		RAS_EVENT_LOG(adev, event_id, HW_ERR "hardware error logged by the scrubber\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct aca_hwip *hwip;</div><div class='add'>+	int hwid, mcatype;</div><div class='add'>+	u64 ipid;</div><div class='add'>+</div><div class='add'>+	if (!bank || type == ACA_HWIP_TYPE_UNKNOW)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	hwip = &amp;aca_hwid_mcatypes[type];</div><div class='add'>+	if (!hwip-&gt;hwid)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	ipid = bank-&gt;regs[ACA_REG_IDX_IPID];</div><div class='add'>+	hwid = ACA_REG__IPID__HARDWAREID(ipid);</div><div class='add'>+	mcatype = ACA_REG__IPID__MCATYPE(ipid);</div><div class='add'>+</div><div class='add'>+	return hwip-&gt;hwid == hwid &amp;&amp; hwip-&gt;mcatype == mcatype;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_error_type type,</div><div class='add'>+static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_type type,</div><div class='ctx'> 				       int start, int count,</div><div class='del'>-				       struct aca_banks *banks)</div><div class='add'>+				       struct aca_banks *banks, struct ras_query_context *qctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='ctx'> 	const struct aca_smu_funcs *smu_funcs = aca-&gt;smu_funcs;</div><div class='hunk'>@@ -143,18 +168,17 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_erro</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	switch (type) {</div><div class='del'>-	case ACA_ERROR_TYPE_UE:</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='ctx'> 		max_count = smu_funcs-&gt;max_ue_bank_count;</div><div class='ctx'> 		break;</div><div class='del'>-	case ACA_ERROR_TYPE_CE:</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='ctx'> 		max_count = smu_funcs-&gt;max_ce_bank_count;</div><div class='ctx'> 		break;</div><div class='del'>-	case ACA_ERROR_TYPE_DEFERRED:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (start + count &gt;= max_count)</div><div class='add'>+	if (start + count &gt; max_count)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	count = min_t(int, count, max_count);</div><div class='hunk'>@@ -164,7 +188,18 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_erro</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> </div><div class='del'>-		aca_smu_bank_dump(adev, i, count, &amp;bank);</div><div class='add'>+		bank.smu_err_type = type;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Poison being consumed when injecting a UE while running background workloads,</div><div class='add'>+		 * which are unexpected.</div><div class='add'>+		 */</div><div class='add'>+		if (type == ACA_SMU_TYPE_UE &amp;&amp;</div><div class='add'>+		    ACA_REG__STATUS__POISON(bank.regs[ACA_REG_IDX_STATUS]) &amp;&amp;</div><div class='add'>+		    !aca_bank_hwip_is_matched(&amp;bank, ACA_HWIP_TYPE_UMC))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		aca_smu_bank_dump(adev, i, count, &amp;bank, qctx);</div><div class='ctx'> </div><div class='ctx'> 		ret = aca_banks_add_bank(banks, &amp;bank);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -174,31 +209,14 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_erro</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-	struct aca_hwip *hwip;</div><div class='del'>-	int hwid, mcatype;</div><div class='del'>-	u64 ipid;</div><div class='del'>-</div><div class='del'>-	if (!bank || type == ACA_HWIP_TYPE_UNKNOW)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	hwip = &amp;aca_hwid_mcatypes[type];</div><div class='del'>-	if (!hwip-&gt;hwid)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	ipid = bank-&gt;regs[ACA_REG_IDX_IPID];</div><div class='del'>-	hwid = ACA_REG__IPID__HARDWAREID(ipid);</div><div class='del'>-	mcatype = ACA_REG__IPID__MCATYPE(ipid);</div><div class='del'>-</div><div class='del'>-	return hwip-&gt;hwid == hwid &amp;&amp; hwip-&gt;mcatype == mcatype;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type)</div><div class='add'>+static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)</div><div class='ctx'> {</div><div class='ctx'> 	const struct aca_bank_ops *bank_ops = handle-&gt;bank_ops;</div><div class='ctx'> </div><div class='add'>+	/* Parse all deferred errors with UMC aca handle */</div><div class='add'>+	if (ACA_BANK_ERR_IS_DEFFERED(bank))</div><div class='add'>+		return handle-&gt;hwip == ACA_HWIP_TYPE_UMC;</div><div class='add'>+</div><div class='ctx'> 	if (!aca_bank_hwip_is_matched(bank, handle-&gt;hwip))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='hunk'>@@ -221,6 +239,7 @@ static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;aerr-&gt;lock);</div><div class='ctx'> 	list_add_tail(&amp;bank_error-&gt;node, &amp;aerr-&gt;list);</div><div class='add'>+	aerr-&gt;nr_errors++;</div><div class='ctx'> 	mutex_unlock(&amp;aerr-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return bank_error;</div><div class='hunk'>@@ -273,59 +292,49 @@ static struct aca_bank_error *get_bank_error(struct aca_error *aerr, struct aca_</div><div class='ctx'> 	return new_bank_error(aerr, info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aca_log_errors(struct aca_handle *handle, enum aca_error_type type,</div><div class='del'>-			  struct aca_bank_report *report)</div><div class='add'>+int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info,</div><div class='add'>+				   enum aca_error_type type, u64 count)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_error_cache *error_cache = &amp;handle-&gt;error_cache;</div><div class='ctx'> 	struct aca_bank_error *bank_error;</div><div class='ctx'> 	struct aca_error *aerr;</div><div class='ctx'> </div><div class='del'>-	if (!handle || !report)</div><div class='add'>+	if (!handle || !info || type &gt;= ACA_ERROR_TYPE_COUNT)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (!report-&gt;count[type])</div><div class='add'>+	if (!count)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	aerr = &amp;error_cache-&gt;errors[type];</div><div class='del'>-	bank_error = get_bank_error(aerr, &amp;report-&gt;info);</div><div class='add'>+	bank_error = get_bank_error(aerr, info);</div><div class='ctx'> 	if (!bank_error)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	bank_error-&gt;count[type] += report-&gt;count[type];</div><div class='add'>+	bank_error-&gt;count += count;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aca_generate_bank_report(struct aca_handle *handle, struct aca_bank *bank,</div><div class='del'>-				    enum aca_error_type type, struct aca_bank_report *report)</div><div class='add'>+static int aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type)</div><div class='ctx'> {</div><div class='ctx'> 	const struct aca_bank_ops *bank_ops = handle-&gt;bank_ops;</div><div class='ctx'> </div><div class='del'>-	if (!bank || !report)</div><div class='add'>+	if (!bank)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (!bank_ops-&gt;aca_bank_generate_report)</div><div class='add'>+	if (!bank_ops-&gt;aca_bank_parser)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	memset(report, 0, sizeof(*report));</div><div class='del'>-	return bank_ops-&gt;aca_bank_generate_report(handle, bank, type,</div><div class='del'>-						  report, handle-&gt;data);</div><div class='add'>+	return bank_ops-&gt;aca_bank_parser(handle, bank, type,</div><div class='add'>+					 handle-&gt;data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank,</div><div class='del'>-				      enum aca_error_type type, void *data)</div><div class='add'>+				      enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct aca_bank_report report;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = aca_generate_bank_report(handle, bank, type, &amp;report);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	if (!report.count[type])</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	ret = aca_log_errors(handle, type, &amp;report);</div><div class='add'>+	ret = aca_bank_parser(handle, bank, type);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -333,7 +342,7 @@ static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank,</div><div class='del'>-			     enum aca_error_type type, bank_handler_t handler, void *data)</div><div class='add'>+			     enum aca_smu_type type, bank_handler_t handler, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_handle *handle;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -354,7 +363,7 @@ static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *ba</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks,</div><div class='del'>-			      enum aca_error_type type, bank_handler_t handler, void *data)</div><div class='add'>+			      enum aca_smu_type type, bank_handler_t handler, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_bank_node *node;</div><div class='ctx'> 	struct aca_bank *bank;</div><div class='hunk'>@@ -378,8 +387,78 @@ static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aca_banks_update(struct amdgpu_device *adev, enum aca_error_type type,</div><div class='del'>-			    bank_handler_t handler, void *data)</div><div class='add'>+static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='add'>+	bool ret = true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Because the UE Valid MCA count will only be cleared after reset,</div><div class='add'>+	 * in order to avoid repeated counting of the error count,</div><div class='add'>+	 * the aca bank is only updated once during the gpu recovery stage.</div><div class='add'>+	 */</div><div class='add'>+	if (type == ACA_SMU_TYPE_UE) {</div><div class='add'>+		if (amdgpu_ras_intr_triggered())</div><div class='add'>+			ret = atomic_cmpxchg(&amp;aca-&gt;ue_update_flag, 0, 1) == 0;</div><div class='add'>+		else</div><div class='add'>+			atomic_set(&amp;aca-&gt;ue_update_flag, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void aca_banks_generate_cper(struct amdgpu_device *adev,</div><div class='add'>+				    enum aca_smu_type type,</div><div class='add'>+				    struct aca_banks *banks,</div><div class='add'>+				    int count)</div><div class='add'>+{</div><div class='add'>+	struct aca_bank_node *node;</div><div class='add'>+	struct aca_bank *bank;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;cper.enabled)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!banks || !count) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "fail to generate cper records\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* UEs must be encoded into separate CPER entries */</div><div class='add'>+	if (type == ACA_SMU_TYPE_UE) {</div><div class='add'>+		struct aca_banks de_banks;</div><div class='add'>+</div><div class='add'>+		aca_banks_init(&amp;de_banks);</div><div class='add'>+		list_for_each_entry(node, &amp;banks-&gt;list, node) {</div><div class='add'>+			bank = &amp;node-&gt;bank;</div><div class='add'>+			if (bank-&gt;aca_err_type == ACA_ERROR_TYPE_DEFERRED) {</div><div class='add'>+				r = aca_banks_add_bank(&amp;de_banks, bank);</div><div class='add'>+				if (r)</div><div class='add'>+					dev_warn(adev-&gt;dev, "fail to add de banks, ret = %d\n", r);</div><div class='add'>+			} else {</div><div class='add'>+				if (amdgpu_cper_generate_ue_record(adev, bank))</div><div class='add'>+					dev_warn(adev-&gt;dev, "fail to generate ue cper records\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!list_empty(&amp;de_banks.list)) {</div><div class='add'>+			if (amdgpu_cper_generate_ce_records(adev, &amp;de_banks, de_banks.nr_banks))</div><div class='add'>+				dev_warn(adev-&gt;dev, "fail to generate de cper records\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		aca_banks_release(&amp;de_banks);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * SMU_TYPE_CE banks are combined into 1 CPER entries,</div><div class='add'>+		 * they could be CEs or DEs or both</div><div class='add'>+		 */</div><div class='add'>+		if (amdgpu_cper_generate_ce_records(adev, banks, count))</div><div class='add'>+			dev_warn(adev-&gt;dev, "fail to generate ce cper records\n");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,</div><div class='add'>+			    bank_handler_t handler, struct ras_query_context *qctx, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='ctx'> 	struct aca_banks banks;</div><div class='hunk'>@@ -389,9 +468,8 @@ static int aca_banks_update(struct amdgpu_device *adev, enum aca_error_type type</div><div class='ctx'> 	if (list_empty(&amp;aca-&gt;mgr.list))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	/* NOTE: pmfw is only support UE and CE */</div><div class='del'>-	if (type == ACA_ERROR_TYPE_DEFERRED)</div><div class='del'>-		type = ACA_ERROR_TYPE_CE;</div><div class='add'>+	if (!aca_bank_should_update(adev, type))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	ret = aca_smu_get_valid_aca_count(adev, type, &amp;count);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -402,7 +480,7 @@ static int aca_banks_update(struct amdgpu_device *adev, enum aca_error_type type</div><div class='ctx'> </div><div class='ctx'> 	aca_banks_init(&amp;banks);</div><div class='ctx'> </div><div class='del'>-	ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &amp;banks);</div><div class='add'>+	ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &amp;banks, qctx);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_release_banks;</div><div class='ctx'> </div><div class='hunk'>@@ -416,6 +494,8 @@ static int aca_banks_update(struct amdgpu_device *adev, enum aca_error_type type</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_release_banks;</div><div class='ctx'> </div><div class='add'>+	aca_banks_generate_cper(adev, type, &amp;banks, count);</div><div class='add'>+</div><div class='ctx'> err_release_banks:</div><div class='ctx'> 	aca_banks_release(&amp;banks);</div><div class='ctx'> </div><div class='hunk'>@@ -431,7 +511,7 @@ static int aca_log_aca_error_data(struct aca_bank_error *bank_error, enum aca_er</div><div class='ctx'> 	if (type &gt;= ACA_ERROR_TYPE_COUNT)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	count = bank_error-&gt;count[type];</div><div class='add'>+	count = bank_error-&gt;count;</div><div class='ctx'> 	if (!count)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -441,12 +521,14 @@ static int aca_log_aca_error_data(struct aca_bank_error *bank_error, enum aca_er</div><div class='ctx'> </div><div class='ctx'> 	switch (type) {</div><div class='ctx'> 	case ACA_ERROR_TYPE_UE:</div><div class='del'>-		amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, count);</div><div class='add'>+		amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, count);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACA_ERROR_TYPE_CE:</div><div class='del'>-		amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, count);</div><div class='add'>+		amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, count);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACA_ERROR_TYPE_DEFERRED:</div><div class='add'>+		amdgpu_ras_error_statistic_de_count(err_data, &amp;mcm_info, count);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -477,15 +559,32 @@ out_unlock:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle, enum aca_error_type type,</div><div class='del'>-				struct ras_err_data *err_data)</div><div class='add'>+				struct ras_err_data *err_data, struct ras_query_context *qctx)</div><div class='ctx'> {</div><div class='add'>+	enum aca_smu_type smu_type;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	/* udpate aca bank to aca source error_cache first */</div><div class='del'>-	ret = aca_banks_update(adev, type, handler_aca_log_bank_error, NULL);</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_ERROR_TYPE_UE:</div><div class='add'>+		smu_type = ACA_SMU_TYPE_UE;</div><div class='add'>+		break;</div><div class='add'>+	case ACA_ERROR_TYPE_CE:</div><div class='add'>+	case ACA_ERROR_TYPE_DEFERRED:</div><div class='add'>+		smu_type = ACA_SMU_TYPE_CE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* update aca bank to aca source error_cache first */</div><div class='add'>+	ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	/* DEs may contain in CEs or UEs */</div><div class='add'>+	if (type != ACA_ERROR_TYPE_DEFERRED)</div><div class='add'>+		aca_log_aca_error(handle, ACA_ERROR_TYPE_DEFERRED, err_data);</div><div class='add'>+</div><div class='ctx'> 	return aca_log_aca_error(handle, type, err_data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -498,20 +597,19 @@ static bool aca_handle_is_valid(struct aca_handle *handle)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle,</div><div class='del'>-			      enum aca_error_type type, void *data)</div><div class='add'>+			      enum aca_error_type type, struct ras_err_data *err_data,</div><div class='add'>+			      struct ras_query_context *qctx)</div><div class='ctx'> {</div><div class='del'>-	struct ras_err_data *err_data = (struct ras_err_data *)data;</div><div class='del'>-</div><div class='ctx'> 	if (!handle || !err_data)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (aca_handle_is_valid(handle))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!(BIT(type) &amp; handle-&gt;mask))</div><div class='add'>+	if ((type &lt; 0) || (!(BIT(type) &amp; handle-&gt;mask)))</div><div class='ctx'> 		return  0;</div><div class='ctx'> </div><div class='del'>-	return __aca_get_error_data(adev, handle, type, err_data);</div><div class='add'>+	return __aca_get_error_data(adev, handle, type, err_data, qctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void aca_error_init(struct aca_error *aerr, enum aca_error_type type)</div><div class='hunk'>@@ -536,9 +634,13 @@ static void aca_error_fini(struct aca_error *aerr)</div><div class='ctx'> 	struct aca_bank_error *bank_error, *tmp;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;aerr-&gt;lock);</div><div class='add'>+	if (list_empty(&amp;aerr-&gt;list))</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(bank_error, tmp, &amp;aerr-&gt;list, node)</div><div class='ctx'> 		aca_bank_error_remove(aerr, bank_error);</div><div class='ctx'> </div><div class='add'>+out_unlock:</div><div class='ctx'> 	mutex_destroy(&amp;aerr-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -654,13 +756,17 @@ static void aca_manager_fini(struct aca_handle_manager *mgr)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_handle *handle, *tmp;</div><div class='ctx'> </div><div class='add'>+	if (list_empty(&amp;mgr-&gt;list))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(handle, tmp, &amp;mgr-&gt;list, node)</div><div class='ctx'> 		amdgpu_aca_remove_handle(handle);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return adev-&gt;aca.is_enabled;</div><div class='add'>+	return (adev-&gt;aca.is_enabled ||</div><div class='add'>+		adev-&gt;debug_enable_ras_aca);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_aca_init(struct amdgpu_device *adev)</div><div class='hunk'>@@ -668,6 +774,8 @@ int amdgpu_aca_init(struct amdgpu_device *adev)</div><div class='ctx'> 	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	atomic_set(&amp;aca-&gt;ue_update_flag, 0);</div><div class='add'>+</div><div class='ctx'> 	ret = aca_manager_init(&amp;aca-&gt;mgr);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -680,13 +788,17 @@ void amdgpu_aca_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='ctx'> </div><div class='ctx'> 	aca_manager_fini(&amp;aca-&gt;mgr);</div><div class='add'>+</div><div class='add'>+	atomic_set(&amp;aca-&gt;ue_update_flag, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_aca_reset(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_aca_fini(adev);</div><div class='add'>+	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='ctx'> </div><div class='del'>-	return amdgpu_aca_init(adev);</div><div class='add'>+	atomic_set(&amp;aca-&gt;ue_update_flag, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs)</div><div class='hunk'>@@ -723,23 +835,13 @@ int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info)</div><div class='ctx'> </div><div class='ctx'> static int aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank)</div><div class='ctx'> {</div><div class='del'>-	int error_code;</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(13, 0, 6):</div><div class='del'>-		if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; adev-&gt;pm.fw_version &gt;= 0x00555600) {</div><div class='del'>-			error_code = ACA_REG__SYND__ERRORINFORMATION(bank-&gt;regs[ACA_REG_IDX_SYND]);</div><div class='del'>-			return error_code &amp; 0xff;</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	struct amdgpu_aca *aca = &amp;adev-&gt;aca;</div><div class='add'>+	const struct aca_smu_funcs *smu_funcs = aca-&gt;smu_funcs;</div><div class='ctx'> </div><div class='del'>-	/* NOTE: the true error code is encoded in status.errorcode[0:7] */</div><div class='del'>-	error_code = ACA_REG__STATUS__ERRORCODE(bank-&gt;regs[ACA_REG_IDX_STATUS]);</div><div class='add'>+	if (!smu_funcs || !smu_funcs-&gt;parse_error_code)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	return error_code &amp; 0xff;</div><div class='add'>+	return smu_funcs-&gt;parse_error_code(adev, bank);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size)</div><div class='hunk'>@@ -750,6 +852,9 @@ int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	error_code = aca_bank_get_error_code(adev, bank);</div><div class='add'>+	if (error_code &lt; 0)</div><div class='add'>+		return error_code;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; size; i++) {</div><div class='ctx'> 		if (err_codes[i] == error_code)</div><div class='ctx'> 			return 0;</div><div class='hunk'>@@ -784,7 +889,7 @@ static int amdgpu_aca_smu_debug_mode_set(void *data, u64 val)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_error_type type, int idx)</div><div class='add'>+static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_smu_type type, int idx)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_bank_info info;</div><div class='ctx'> 	int i, ret;</div><div class='hunk'>@@ -793,7 +898,7 @@ static void aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_e</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	seq_printf(m, "aca entry[%d].type: %s\n", idx, type ==  ACA_ERROR_TYPE_UE ? "UE" : "CE");</div><div class='add'>+	seq_printf(m, "aca entry[%d].type: %s\n", idx, type ==  ACA_SMU_TYPE_UE ? "UE" : "CE");</div><div class='ctx'> 	seq_printf(m, "aca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n",</div><div class='ctx'> 		   idx, info.socket_id, info.die_id, info.hwid, info.mcatype);</div><div class='ctx'> </div><div class='hunk'>@@ -807,7 +912,7 @@ struct aca_dump_context {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank,</div><div class='del'>-				 enum aca_error_type type, void *data)</div><div class='add'>+				 enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct aca_dump_context *ctx = (struct aca_dump_context *)data;</div><div class='ctx'> </div><div class='hunk'>@@ -816,7 +921,7 @@ static int handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *ban</div><div class='ctx'> 	return handler_aca_log_bank_error(handle, bank, type, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aca_dump_show(struct seq_file *m, enum aca_error_type type)</div><div class='add'>+static int aca_dump_show(struct seq_file *m, enum aca_smu_type type)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)m-&gt;private;</div><div class='ctx'> 	struct aca_dump_context context = {</div><div class='hunk'>@@ -824,12 +929,12 @@ static int aca_dump_show(struct seq_file *m, enum aca_error_type type)</div><div class='ctx'> 		.idx = 0,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	return aca_banks_update(adev, type, handler_aca_bank_dump, (void *)&amp;context);</div><div class='add'>+	return aca_banks_update(adev, type, handler_aca_bank_dump, NULL, (void *)&amp;context);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int aca_dump_ce_show(struct seq_file *m, void *unused)</div><div class='ctx'> {</div><div class='del'>-	return aca_dump_show(m, ACA_ERROR_TYPE_CE);</div><div class='add'>+	return aca_dump_show(m, ACA_SMU_TYPE_CE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int aca_dump_ce_open(struct inode *inode, struct file *file)</div><div class='hunk'>@@ -847,7 +952,7 @@ static const struct file_operations aca_ce_dump_debug_fops = {</div><div class='ctx'> </div><div class='ctx'> static int aca_dump_ue_show(struct seq_file *m, void *unused)</div><div class='ctx'> {</div><div class='del'>-	return aca_dump_show(m, ACA_ERROR_TYPE_UE);</div><div class='add'>+	return aca_dump_show(m, ACA_SMU_TYPE_UE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int aca_dump_ue_open(struct inode *inode, struct file *file)</div><div class='hunk'>@@ -869,7 +974,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_se</div><div class='ctx'> void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)</div><div class='ctx'> {</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='del'>-	if (!root || adev-&gt;ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6))</div><div class='add'>+	if (!root)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_file("aca_debug_mode", 0200, root, adev, &amp;aca_debug_mode_fops);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h<br/>index 2da50e095883..38c88897e1ec 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_aca.h</a></div><div class='hunk'>@@ -26,6 +26,9 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> </div><div class='add'>+struct ras_err_data;</div><div class='add'>+struct ras_query_context;</div><div class='add'>+</div><div class='ctx'> #define ACA_MAX_REGS_COUNT	(16)</div><div class='ctx'> </div><div class='ctx'> #define ACA_REG_FIELD(x, h, l)			(((x) &amp; GENMASK_ULL(h, l)) &gt;&gt; l)</div><div class='hunk'>@@ -68,12 +71,21 @@</div><div class='ctx'> #define ACA_ERROR_CE_MASK		BIT_MASK(ACA_ERROR_TYPE_CE)</div><div class='ctx'> #define ACA_ERROR_DEFERRED_MASK		BIT_MASK(ACA_ERROR_TYPE_DEFERRED)</div><div class='ctx'> </div><div class='add'>+#define mmSMNAID_AID0_MCA_SMU		0x03b30400	/* SMN AID AID0 */</div><div class='add'>+#define mmSMNAID_XCD0_MCA_SMU		0x36430400	/* SMN AID XCD0 */</div><div class='add'>+#define mmSMNAID_XCD1_MCA_SMU		0x38430400	/* SMN AID XCD1 */</div><div class='add'>+#define mmSMNXCD_XCD0_MCA_SMU		0x40430400	/* SMN XCD XCD0 */</div><div class='add'>+</div><div class='add'>+#define ACA_BANK_ERR_IS_DEFFERED(bank)                                \</div><div class='add'>+	(ACA_REG__STATUS__POISON((bank)-&gt;regs[ACA_REG_IDX_STATUS]) || \</div><div class='add'>+	 ACA_REG__STATUS__DEFERRED((bank)-&gt;regs[ACA_REG_IDX_STATUS]))</div><div class='add'>+</div><div class='ctx'> enum aca_reg_idx {</div><div class='ctx'> 	ACA_REG_IDX_CTL			= 0,</div><div class='ctx'> 	ACA_REG_IDX_STATUS		= 1,</div><div class='ctx'> 	ACA_REG_IDX_ADDR		= 2,</div><div class='ctx'> 	ACA_REG_IDX_MISC0		= 3,</div><div class='del'>-	ACA_REG_IDX_CONFG		= 4,</div><div class='add'>+	ACA_REG_IDX_CONFIG		= 4,</div><div class='ctx'> 	ACA_REG_IDX_IPID		= 5,</div><div class='ctx'> 	ACA_REG_IDX_SYND		= 6,</div><div class='ctx'> 	ACA_REG_IDX_DESTAT		= 8,</div><div class='hunk'>@@ -99,7 +111,21 @@ enum aca_error_type {</div><div class='ctx'> 	ACA_ERROR_TYPE_COUNT</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum aca_smu_type {</div><div class='add'>+	ACA_SMU_TYPE_INVALID = -1,</div><div class='add'>+	ACA_SMU_TYPE_UE = 0,</div><div class='add'>+	ACA_SMU_TYPE_CE,</div><div class='add'>+	ACA_SMU_TYPE_COUNT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct aca_hwip {</div><div class='add'>+	int hwid;</div><div class='add'>+	int mcatype;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct aca_bank {</div><div class='add'>+	enum aca_error_type aca_err_type;</div><div class='add'>+	enum aca_smu_type smu_err_type;</div><div class='ctx'> 	u64 regs[ACA_MAX_REGS_COUNT];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -108,6 +134,11 @@ struct aca_bank_node {</div><div class='ctx'> 	struct list_head node;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct aca_banks {</div><div class='add'>+	int nr_banks;</div><div class='add'>+	struct list_head list;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct aca_bank_info {</div><div class='ctx'> 	int die_id;</div><div class='ctx'> 	int socket_id;</div><div class='hunk'>@@ -115,15 +146,10 @@ struct aca_bank_info {</div><div class='ctx'> 	int mcatype;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct aca_bank_report {</div><div class='del'>-	struct aca_bank_info info;</div><div class='del'>-	u64 count[ACA_ERROR_TYPE_COUNT];</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct aca_bank_error {</div><div class='ctx'> 	struct list_head node;</div><div class='ctx'> 	struct aca_bank_info info;</div><div class='del'>-	u64 count[ACA_ERROR_TYPE_COUNT];</div><div class='add'>+	u64 count;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct aca_error {</div><div class='hunk'>@@ -157,9 +183,8 @@ struct aca_handle {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct aca_bank_ops {</div><div class='del'>-	int (*aca_bank_generate_report)(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,</div><div class='del'>-					struct aca_bank_report *report, void *data);</div><div class='del'>-	bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,</div><div class='add'>+	int (*aca_bank_parser)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);</div><div class='add'>+	bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type,</div><div class='ctx'> 				  void *data);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -167,13 +192,15 @@ struct aca_smu_funcs {</div><div class='ctx'> 	int max_ue_bank_count;</div><div class='ctx'> 	int max_ce_bank_count;</div><div class='ctx'> 	int (*set_debug_mode)(struct amdgpu_device *adev, bool enable);</div><div class='del'>-	int (*get_valid_aca_count)(struct amdgpu_device *adev, enum aca_error_type type, u32 *count);</div><div class='del'>-	int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_error_type type, int idx, struct aca_bank *bank);</div><div class='add'>+	int (*get_valid_aca_count)(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count);</div><div class='add'>+	int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_smu_type type, int idx, struct aca_bank *bank);</div><div class='add'>+	int (*parse_error_code)(struct amdgpu_device *adev, struct aca_bank *bank);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_aca {</div><div class='ctx'> 	struct aca_handle_manager mgr;</div><div class='ctx'> 	const struct aca_smu_funcs *smu_funcs;</div><div class='add'>+	atomic_t ue_update_flag;</div><div class='ctx'> 	bool is_enabled;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -196,7 +223,10 @@ int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle,</div><div class='ctx'> 			  const char *name, const struct aca_info *aca_info, void *data);</div><div class='ctx'> void amdgpu_aca_remove_handle(struct aca_handle *handle);</div><div class='ctx'> int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle,</div><div class='del'>-				     enum aca_error_type type, void *data);</div><div class='add'>+			      enum aca_error_type type, struct ras_err_data *err_data,</div><div class='add'>+			      struct ras_query_context *qctx);</div><div class='ctx'> int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en);</div><div class='ctx'> void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);</div><div class='add'>+int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info,</div><div class='add'>+				   enum aca_error_type type, u64 count);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c<br/>index 6d72355ac492..381ef205b0df 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c</a></div><div class='hunk'>@@ -98,9 +98,9 @@ enum {</div><div class='ctx'> 	ACP_TILE_DSP2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int acp_sw_init(void *handle)</div><div class='add'>+static int acp_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;acp.parent = adev-&gt;dev;</div><div class='ctx'> </div><div class='hunk'>@@ -112,9 +112,9 @@ static int acp_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int acp_sw_fini(void *handle)</div><div class='add'>+static int acp_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;acp.cgs_device)</div><div class='ctx'> 		amdgpu_cgs_destroy_device(adev-&gt;acp.cgs_device);</div><div class='hunk'>@@ -140,7 +140,7 @@ static int acp_poweroff(struct generic_pm_domain *genpd)</div><div class='ctx'> 	 * 2. power off the acp tiles</div><div class='ctx'> 	 * 3. check and enter ulv state</div><div class='ctx'> 	 */</div><div class='del'>-	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);</div><div class='add'>+	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -157,7 +157,7 @@ static int acp_poweron(struct generic_pm_domain *genpd)</div><div class='ctx'> 	 * 2. turn on acp clock</div><div class='ctx'> 	 * 3. power on acp tiles</div><div class='ctx'> 	 */</div><div class='del'>-	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);</div><div class='add'>+	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -219,10 +219,10 @@ static const struct dmi_system_id acp_quirk_table[] = {</div><div class='ctx'> /**</div><div class='ctx'>  * acp_hw_init - start and test ACP block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int acp_hw_init(void *handle)</div><div class='add'>+static int acp_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	u64 acp_base;</div><div class='hunk'>@@ -230,19 +230,13 @@ static int acp_hw_init(void *handle)</div><div class='ctx'> 	u32 count = 0;</div><div class='ctx'> 	struct i2s_platform_data *i2s_pdata = NULL;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	const struct amdgpu_ip_block *ip_block =</div><div class='del'>-		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);</div><div class='del'>-</div><div class='del'>-	if (!ip_block)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amd_acp_hw_init(adev-&gt;acp.cgs_device,</div><div class='ctx'> 			    ip_block-&gt;version-&gt;major, ip_block-&gt;version-&gt;minor);</div><div class='ctx'> 	/* -ENODEV means board uses AZ rather than ACP */</div><div class='ctx'> 	if (r == -ENODEV) {</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	} else if (r) {</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -308,17 +302,19 @@ static int acp_hw_init(void *handle)</div><div class='ctx'> 		adev-&gt;acp.acp_res[2].end = adev-&gt;acp.acp_res[2].start;</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].name = "acp_audio_dma";</div><div class='add'>+		adev-&gt;acp.acp_cell[0].id = 0;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].num_resources = 3;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].resources = &amp;adev-&gt;acp.acp_res[0];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].platform_data = &amp;adev-&gt;asic_type;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].pdata_size = sizeof(adev-&gt;asic_type);</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].name = "designware-i2s";</div><div class='add'>+		adev-&gt;acp.acp_cell[1].id = 1;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].num_resources = 1;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].resources = &amp;adev-&gt;acp.acp_res[1];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].platform_data = &amp;i2s_pdata[0];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);</div><div class='del'>-		r = mfd_add_hotplug_devices(adev-&gt;acp.parent, adev-&gt;acp.acp_cell, 2);</div><div class='add'>+		r = mfd_add_devices(adev-&gt;acp.parent, 0, adev-&gt;acp.acp_cell, 2, NULL, 0, NULL);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto failure;</div><div class='ctx'> 		r = device_for_each_child(adev-&gt;acp.parent, &amp;adev-&gt;acp.acp_genpd-&gt;gpd,</div><div class='hunk'>@@ -416,30 +412,34 @@ static int acp_hw_init(void *handle)</div><div class='ctx'> 		adev-&gt;acp.acp_res[4].end = adev-&gt;acp.acp_res[4].start;</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].name = "acp_audio_dma";</div><div class='add'>+		adev-&gt;acp.acp_cell[0].id = 0;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].num_resources = 5;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].resources = &amp;adev-&gt;acp.acp_res[0];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].platform_data = &amp;adev-&gt;asic_type;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[0].pdata_size = sizeof(adev-&gt;asic_type);</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].name = "designware-i2s";</div><div class='add'>+		adev-&gt;acp.acp_cell[1].id = 1;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].num_resources = 1;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].resources = &amp;adev-&gt;acp.acp_res[1];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].platform_data = &amp;i2s_pdata[0];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;acp.acp_cell[2].name = "designware-i2s";</div><div class='add'>+		adev-&gt;acp.acp_cell[2].id = 2;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[2].num_resources = 1;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[2].resources = &amp;adev-&gt;acp.acp_res[2];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[2].platform_data = &amp;i2s_pdata[1];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;acp.acp_cell[3].name = "designware-i2s";</div><div class='add'>+		adev-&gt;acp.acp_cell[3].id = 3;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[3].num_resources = 1;</div><div class='ctx'> 		adev-&gt;acp.acp_cell[3].resources = &amp;adev-&gt;acp.acp_res[3];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[3].platform_data = &amp;i2s_pdata[2];</div><div class='ctx'> 		adev-&gt;acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);</div><div class='ctx'> </div><div class='del'>-		r = mfd_add_hotplug_devices(adev-&gt;acp.parent, adev-&gt;acp.acp_cell, ACP_DEVS);</div><div class='add'>+		r = mfd_add_devices(adev-&gt;acp.parent, 0, adev-&gt;acp.acp_cell, ACP_DEVS, NULL, 0, NULL);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto failure;</div><div class='ctx'> </div><div class='hunk'>@@ -503,18 +503,18 @@ failure:</div><div class='ctx'> /**</div><div class='ctx'>  * acp_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int acp_hw_fini(void *handle)</div><div class='add'>+static int acp_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 val = 0;</div><div class='ctx'> 	u32 count = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* return early if no ACP */</div><div class='ctx'> 	if (!adev-&gt;acp.acp_genpd) {</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -565,67 +565,50 @@ static int acp_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int acp_suspend(void *handle)</div><div class='add'>+static int acp_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* power up on suspend */</div><div class='ctx'> 	if (!adev-&gt;acp.acp_cell)</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int acp_resume(void *handle)</div><div class='add'>+static int acp_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* power down again on resume */</div><div class='ctx'> 	if (!adev-&gt;acp.acp_cell)</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int acp_early_init(void *handle)</div><div class='del'>-{</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool acp_is_idle(void *handle)</div><div class='add'>+static bool acp_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int acp_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int acp_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int acp_set_clockgating_state(void *handle,</div><div class='add'>+static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int acp_set_powergating_state(void *handle,</div><div class='add'>+static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='del'>-	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);</div><div class='add'>+	amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs acp_ip_funcs = {</div><div class='ctx'> 	.name = "acp_ip",</div><div class='del'>-	.early_init = acp_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = acp_sw_init,</div><div class='ctx'> 	.sw_fini = acp_sw_fini,</div><div class='ctx'> 	.hw_init = acp_hw_init,</div><div class='hunk'>@@ -633,8 +616,6 @@ static const struct amd_ip_funcs acp_ip_funcs = {</div><div class='ctx'> 	.suspend = acp_suspend,</div><div class='ctx'> 	.resume = acp_resume,</div><div class='ctx'> 	.is_idle = acp_is_idle,</div><div class='del'>-	.wait_for_idle = acp_wait_for_idle,</div><div class='del'>-	.soft_reset = acp_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = acp_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = acp_set_powergating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c<br/>index 7099ff9cf8c5..d31460a9e958 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c</a></div><div class='hunk'>@@ -147,6 +147,7 @@ static union acpi_object *amdgpu_atif_call(struct amdgpu_atif *atif,</div><div class='ctx'> 					   struct acpi_buffer *params)</div><div class='ctx'> {</div><div class='ctx'> 	acpi_status status;</div><div class='add'>+	union acpi_object *obj;</div><div class='ctx'> 	union acpi_object atif_arg_elements[2];</div><div class='ctx'> 	struct acpi_object_list atif_arg;</div><div class='ctx'> 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };</div><div class='hunk'>@@ -169,16 +170,24 @@ static union acpi_object *amdgpu_atif_call(struct amdgpu_atif *atif,</div><div class='ctx'> </div><div class='ctx'> 	status = acpi_evaluate_object(atif-&gt;handle, NULL, &amp;atif_arg,</div><div class='ctx'> 				      &amp;buffer);</div><div class='add'>+	obj = (union acpi_object *)buffer.pointer;</div><div class='ctx'> </div><div class='del'>-	/* Fail only if calling the method fails and ATIF is supported */</div><div class='del'>-	if (ACPI_FAILURE(status) &amp;&amp; status != AE_NOT_FOUND) {</div><div class='add'>+	/* Fail if calling the method fails */</div><div class='add'>+	if (ACPI_FAILURE(status)) {</div><div class='ctx'> 		DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n",</div><div class='ctx'> 				 acpi_format_exception(status));</div><div class='del'>-		kfree(buffer.pointer);</div><div class='add'>+		kfree(obj);</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return buffer.pointer;</div><div class='add'>+	if (obj-&gt;type != ACPI_TYPE_BUFFER) {</div><div class='add'>+		DRM_DEBUG_DRIVER("bad object returned from ATIF: %d\n",</div><div class='add'>+				 obj-&gt;type);</div><div class='add'>+		kfree(obj);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return obj;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -383,6 +392,12 @@ static int amdgpu_atif_query_backlight_caps(struct amdgpu_atif *atif)</div><div class='ctx'> 			characteristics.min_input_signal;</div><div class='ctx'> 	atif-&gt;backlight_caps.max_input_signal =</div><div class='ctx'> 			characteristics.max_input_signal;</div><div class='add'>+	atif-&gt;backlight_caps.ac_level = characteristics.ac_level;</div><div class='add'>+	atif-&gt;backlight_caps.dc_level = characteristics.dc_level;</div><div class='add'>+	atif-&gt;backlight_caps.data_points = characteristics.number_of_points;</div><div class='add'>+	memcpy(atif-&gt;backlight_caps.luminance_data,</div><div class='add'>+	       characteristics.data_points,</div><div class='add'>+	       sizeof(atif-&gt;backlight_caps.luminance_data));</div><div class='ctx'> out:</div><div class='ctx'> 	kfree(info);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -492,7 +507,6 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,</div><div class='ctx'> 				pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 				/* Just fire off a uevent and let userspace tell us what to do */</div><div class='ctx'> 				drm_helper_hpd_irq_event(adev_to_drm(adev));</div><div class='del'>-				pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 				pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -789,24 +803,25 @@ int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfree(info);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_acpi_smart_shift_update - update dGPU device state to SBIOS</div><div class='ctx'>  *</div><div class='del'>- * @dev: drm_device pointer</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='ctx'>  * @ss_state: current smart shift event</div><div class='ctx'>  *</div><div class='ctx'>  * returns 0 on success,</div><div class='ctx'>  * otherwise return error number.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state)</div><div class='add'>+int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev,</div><div class='add'>+				   enum amdgpu_ss ss_state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_device_supports_smart_shift(dev))</div><div class='add'>+	if (!amdgpu_device_supports_smart_shift(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (ss_state) {</div><div class='hunk'>@@ -1265,9 +1280,7 @@ void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_atif *atif = &amp;amdgpu_acpi_priv.atif;</div><div class='ctx'> </div><div class='del'>-	caps-&gt;caps_valid = atif-&gt;backlight_caps.caps_valid;</div><div class='del'>-	caps-&gt;min_input_signal = atif-&gt;backlight_caps.min_input_signal;</div><div class='del'>-	caps-&gt;max_input_signal = atif-&gt;backlight_caps.max_input_signal;</div><div class='add'>+	memcpy(caps, &amp;atif-&gt;backlight_caps, sizeof(*caps));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1518,23 +1531,35 @@ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)</div><div class='ctx'> 	return true;</div><div class='ctx'> #endif /* CONFIG_AMD_PMC */</div><div class='ctx'> }</div><div class='add'>+#endif /* CONFIG_SUSPEND */</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_choose_low_power_state</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device_pointer</div><div class='del'>- *</div><div class='del'>- * Choose the target low power state for the GPU</div><div class='del'>- */</div><div class='del'>-void amdgpu_choose_low_power_state(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	if (adev-&gt;in_runpm)</div><div class='del'>-		return;</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_AMD_ISP)</div><div class='add'>+static const struct acpi_device_id isp_sensor_ids[] = {</div><div class='add'>+	{ "OMNI5C10" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_acpi_is_s0ix_active(adev))</div><div class='del'>-		adev-&gt;in_s0ix = true;</div><div class='del'>-	else if (amdgpu_acpi_is_s3_active(adev))</div><div class='del'>-		adev-&gt;in_s3 = true;</div><div class='add'>+static int isp_match_acpi_device_ids(struct device *dev, const void *data)</div><div class='add'>+{</div><div class='add'>+	return acpi_match_device(data, dev) ? 1 : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#endif /* CONFIG_SUSPEND */</div><div class='add'>+int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev)</div><div class='add'>+{</div><div class='add'>+	struct device *pdev __free(put_device) = NULL;</div><div class='add'>+	struct acpi_device *acpi_pdev;</div><div class='add'>+</div><div class='add'>+	pdev = bus_find_device(&amp;platform_bus_type, NULL, isp_sensor_ids,</div><div class='add'>+			       isp_match_acpi_device_ids);</div><div class='add'>+	if (!pdev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	acpi_pdev = ACPI_COMPANION(pdev);</div><div class='add'>+	if (!acpi_pdev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	*dev = acpi_pdev;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+#endif /* CONFIG_DRM_AMD_ISP */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c<br/>index a4d65973bf7c..80771b1480ff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c</a></div><div class='hunk'>@@ -100,6 +100,7 @@ struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)</div><div class='ctx'> 	amdgpu_afmt_calc_cts(clock, &amp;res.cts_32khz, &amp;res.n_32khz, 32000);</div><div class='ctx'> 	amdgpu_afmt_calc_cts(clock, &amp;res.cts_44_1khz, &amp;res.n_44_1khz, 44100);</div><div class='ctx'> 	amdgpu_afmt_calc_cts(clock, &amp;res.cts_48khz, &amp;res.n_48khz, 48000);</div><div class='add'>+	res.clock = clock;</div><div class='ctx'> </div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c<br/>index 35dd6effa9a3..a2879d2b7c8e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c</a></div><div class='hunk'>@@ -133,6 +133,9 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 	reset_context.reset_req_dev = adev;</div><div class='add'>+	reset_context.src = adev-&gt;enable_mes ?</div><div class='add'>+			    AMDGPU_RESET_SRC_MES :</div><div class='add'>+			    AMDGPU_RESET_SRC_HWS;</div><div class='ctx'> 	clear_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='hunk'>@@ -245,28 +248,53 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		kgd2kfd_interrupt(adev-&gt;kfd.dev, ih_ring_entry);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)</div><div class='add'>+void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;kfd.dev) {</div><div class='add'>+		if (adev-&gt;in_s0ix)</div><div class='add'>+			kgd2kfd_stop_sched_all_nodes(adev-&gt;kfd.dev);</div><div class='add'>+		else</div><div class='add'>+			kgd2kfd_suspend(adev-&gt;kfd.dev, suspend_proc);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;kfd.dev) {</div><div class='add'>+		if (adev-&gt;in_s0ix)</div><div class='add'>+			r = kgd2kfd_start_sched_all_nodes(adev-&gt;kfd.dev);</div><div class='add'>+		else</div><div class='add'>+			r = kgd2kfd_resume(adev-&gt;kfd.dev, resume_proc);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (adev-&gt;kfd.dev)</div><div class='del'>-		kgd2kfd_suspend(adev-&gt;kfd.dev, run_pm);</div><div class='add'>+		kgd2kfd_suspend_process(adev-&gt;kfd.dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)</div><div class='add'>+int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;kfd.dev)</div><div class='del'>-		r = kgd2kfd_resume(adev-&gt;kfd.dev, run_pm);</div><div class='add'>+		r = kgd2kfd_resume_process(adev-&gt;kfd.dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)</div><div class='add'>+int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,</div><div class='add'>+			    struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;kfd.dev)</div><div class='del'>-		r = kgd2kfd_pre_reset(adev-&gt;kfd.dev);</div><div class='add'>+		r = kgd2kfd_pre_reset(adev-&gt;kfd.dev, reset_context);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -360,15 +388,18 @@ allocate_mem_reserve_bo_failed:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj)</div><div class='add'>+void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;</div><div class='add'>+	struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj;</div><div class='ctx'> </div><div class='del'>-	amdgpu_bo_reserve(bo, true);</div><div class='del'>-	amdgpu_bo_kunmap(bo);</div><div class='del'>-	amdgpu_bo_unpin(bo);</div><div class='del'>-	amdgpu_bo_unreserve(bo);</div><div class='del'>-	amdgpu_bo_unref(&amp;(bo));</div><div class='add'>+	if (!bo || !*bo)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	(void)amdgpu_bo_reserve(*bo, true);</div><div class='add'>+	amdgpu_bo_kunmap(*bo);</div><div class='add'>+	amdgpu_bo_unpin(*bo);</div><div class='add'>+	amdgpu_bo_unreserve(*bo);</div><div class='add'>+	amdgpu_bo_unref(bo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,</div><div class='hunk'>@@ -455,6 +486,9 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,</div><div class='ctx'> 		else</div><div class='ctx'> 			mem_info-&gt;local_mem_size_private =</div><div class='ctx'> 					KFD_XCP_MEMORY_SIZE(adev, xcp-&gt;id);</div><div class='add'>+	} else if (adev-&gt;apu_prefer_gtt) {</div><div class='add'>+		mem_info-&gt;local_mem_size_public = (ttm_tt_pages_limit() &lt;&lt; PAGE_SHIFT);</div><div class='add'>+		mem_info-&gt;local_mem_size_private = 0;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		mem_info-&gt;local_mem_size_public = adev-&gt;gmc.visible_vram_size;</div><div class='ctx'> 		mem_info-&gt;local_mem_size_private = adev-&gt;gmc.real_vram_size -</div><div class='hunk'>@@ -548,48 +582,6 @@ out_put:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,</div><div class='del'>-					  struct amdgpu_device *src)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *peer_adev = src;</div><div class='del'>-	struct amdgpu_device *adev = dst;</div><div class='del'>-	int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);</div><div class='del'>-</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",</div><div class='del'>-			adev-&gt;gmc.xgmi.physical_node_id,</div><div class='del'>-			peer_adev-&gt;gmc.xgmi.physical_node_id, ret);</div><div class='del'>-		ret = 0;</div><div class='del'>-	}</div><div class='del'>-	return  (uint8_t)ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,</div><div class='del'>-					    struct amdgpu_device *src,</div><div class='del'>-					    bool is_min)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = dst, *peer_adev;</div><div class='del'>-	int num_links;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(9, 4, 2))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (src)</div><div class='del'>-		peer_adev = src;</div><div class='del'>-</div><div class='del'>-	/* num links returns 0 for indirect peers since indirect route is unknown. */</div><div class='del'>-	num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);</div><div class='del'>-	if (num_links &lt; 0) {</div><div class='del'>-		DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",</div><div class='del'>-			adev-&gt;gmc.xgmi.physical_node_id,</div><div class='del'>-			peer_adev-&gt;gmc.xgmi.physical_node_id, num_links);</div><div class='del'>-		num_links = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */</div><div class='del'>-	return (num_links * 16 * 25000)/BITS_PER_BYTE;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)</div><div class='ctx'> {</div><div class='ctx'> 	int num_lanes_shift = (is_min ? ffs(adev-&gt;pm.pcie_mlw_mask) :</div><div class='hunk'>@@ -674,7 +666,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &amp;job);</div><div class='add'>+	ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &amp;job, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='hunk'>@@ -708,8 +700,9 @@ err:</div><div class='ctx'> void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)</div><div class='ctx'> {</div><div class='ctx'> 	enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE;</div><div class='del'>-	if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &amp;&amp;</div><div class='del'>-	    ((adev-&gt;mes.kiq_version &amp; AMDGPU_MES_VERSION_MASK) &lt;= 64)) {</div><div class='add'>+	if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &amp;&amp;</div><div class='add'>+	    ((adev-&gt;mes.kiq_version &amp; AMDGPU_MES_VERSION_MASK) &lt;= 64)) ||</div><div class='add'>+		(IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) {</div><div class='ctx'> 		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");</div><div class='ctx'> 		amdgpu_gfx_off_ctrl(adev, idle);</div><div class='ctx'> 	} else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &amp;&amp;</div><div class='hunk'>@@ -717,7 +710,9 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)</div><div class='ctx'> 		/* Disable GFXOFF and PG. Temporary workaround</div><div class='ctx'> 		 * to fix some compute applications issue on GFX9.</div><div class='ctx'> 		 */</div><div class='del'>-		adev-&gt;ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version-&gt;funcs-&gt;set_powergating_state((void *)adev, state);</div><div class='add'>+		struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);</div><div class='add'>+		if (gfx_block != NULL)</div><div class='add'>+			gfx_block-&gt;version-&gt;funcs-&gt;set_powergating_state((void *)gfx_block, state);</div><div class='ctx'> 	}</div><div class='ctx'> 	amdgpu_dpm_switch_power_profile(adev,</div><div class='ctx'> 					PP_SMC_POWER_PROFILE_COMPUTE,</div><div class='hunk'>@@ -747,10 +742,17 @@ bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)</div><div class='ctx'> 	return amdgpu_ras_get_fed_status(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='add'>+				enum amdgpu_ras_block block, uint16_t pasid,</div><div class='add'>+				pasid_notify pasid_fn, void *data, uint32_t reset)</div><div class='add'>+{</div><div class='add'>+	amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='del'>-	enum amdgpu_ras_block block, bool reset)</div><div class='add'>+	enum amdgpu_ras_block block, uint32_t reset)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_umc_poison_handler(adev, block, reset);</div><div class='add'>+	amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,</div><div class='hunk'>@@ -769,22 +771,14 @@ int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	if (adev-&gt;gfx.ras &amp;&amp; adev-&gt;gfx.ras-&gt;query_utcl2_poison_status)</div><div class='del'>-		return adev-&gt;gfx.ras-&gt;query_utcl2_poison_status(adev);</div><div class='del'>-	else</div><div class='del'>-		return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return kgd2kfd_check_and_lock_kfd();</div><div class='add'>+	return kgd2kfd_check_and_lock_kfd(adev-&gt;kfd.dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	kgd2kfd_unlock_kfd();</div><div class='add'>+	kgd2kfd_unlock_kfd(adev-&gt;kfd.dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -809,6 +803,8 @@ u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)</div><div class='ctx'> 		}</div><div class='ctx'> 		do_div(tmp, adev-&gt;xcp_mgr-&gt;num_xcp_per_mem_partition);</div><div class='ctx'> 		return ALIGN_DOWN(tmp, PAGE_SIZE);</div><div class='add'>+	} else if (adev-&gt;apu_prefer_gtt) {</div><div class='add'>+		return (ttm_tt_pages_limit() &lt;&lt; PAGE_SHIFT);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		return adev-&gt;gmc.real_vram_size;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -826,6 +822,9 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,</div><div class='ctx'> 	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!kiq_ring-&gt;sched.ready || amdgpu_in_reset(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL);</div><div class='ctx'> 	if (!ring_funcs)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -850,8 +849,14 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,</div><div class='ctx'> </div><div class='ctx'> 	kiq-&gt;pmf-&gt;kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0);</div><div class='ctx'> </div><div class='del'>-	if (kiq_ring-&gt;sched.ready &amp;&amp; !adev-&gt;job_hang)</div><div class='del'>-		r = amdgpu_ring_test_helper(kiq_ring);</div><div class='add'>+	/* Submit unmap queue packet */</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	/*</div><div class='add'>+	 * Ring test will do a basic scratch register change check. Just run</div><div class='add'>+	 * this to ensure that unmap queues that is submitted before got</div><div class='add'>+	 * processed successfully before returning.</div><div class='add'>+	 */</div><div class='add'>+	r = amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -863,3 +868,45 @@ free_ring_funcs:</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/* Stop scheduling on KFD */</div><div class='add'>+int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;kfd.init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return kgd2kfd_stop_sched(adev-&gt;kfd.dev, node_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Start scheduling on KFD */</div><div class='add'>+int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;kfd.init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return kgd2kfd_start_sched(adev-&gt;kfd.dev, node_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* check if there are KFD queues active */</div><div class='add'>+bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;kfd.init_complete)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return kgd2kfd_compute_active(adev-&gt;kfd.dev, node_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Config CGTT_SQ_CLK_CTRL */</div><div class='add'>+int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,</div><div class='add'>+	bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;kfd.init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	r = psp_config_sq_perfmon(&amp;adev-&gt;psp, xcp_id, core_override_enable,</div><div class='add'>+					reg_override_enable, perfmon_override_enable);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h<br/>index 0ef223c2affb..8bdfcde2029b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h</a></div><div class='hunk'>@@ -47,6 +47,8 @@ enum TLB_FLUSH_TYPE {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_device;</div><div class='add'>+struct kfd_process_device;</div><div class='add'>+struct amdgpu_reset_context;</div><div class='ctx'> </div><div class='ctx'> enum kfd_mem_attachment_type {</div><div class='ctx'> 	KFD_MEM_ATT_SHARED,	/* Share kgd_mem-&gt;bo or another attachment's */</div><div class='hunk'>@@ -69,7 +71,7 @@ struct kgd_mem {</div><div class='ctx'> 	struct mutex lock;</div><div class='ctx'> 	struct amdgpu_bo *bo;</div><div class='ctx'> 	struct dma_buf *dmabuf;</div><div class='del'>-	struct hmm_range *range;</div><div class='add'>+	struct amdgpu_hmm_range *range;</div><div class='ctx'> 	struct list_head attachments;</div><div class='ctx'> 	/* protected by amdkfd_process_info.lock */</div><div class='ctx'> 	struct list_head validate_list;</div><div class='hunk'>@@ -105,11 +107,13 @@ struct amdgpu_kfd_dev {</div><div class='ctx'> 	bool init_complete;</div><div class='ctx'> 	struct work_struct reset_work;</div><div class='ctx'> </div><div class='del'>-	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping */</div><div class='del'>-	struct dev_pagemap pgmap;</div><div class='del'>-</div><div class='ctx'> 	/* Client for KFD BO GEM handle allocations */</div><div class='ctx'> 	struct drm_client_dev client;</div><div class='add'>+</div><div class='add'>+	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping</div><div class='add'>+	 * Must be last --ends in a flexible-array member.</div><div class='add'>+	 */</div><div class='add'>+	struct dev_pagemap pgmap;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum kgd_engine_type {</div><div class='hunk'>@@ -152,8 +156,10 @@ struct amdkfd_process_info {</div><div class='ctx'> int amdgpu_amdkfd_init(void);</div><div class='ctx'> void amdgpu_amdkfd_fini(void);</div><div class='ctx'> </div><div class='del'>-void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);</div><div class='del'>-int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);</div><div class='add'>+void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc);</div><div class='add'>+int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc);</div><div class='add'>+void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 			const void *ih_ring_entry);</div><div class='ctx'> void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);</div><div class='hunk'>@@ -170,7 +176,8 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,</div><div class='add'>+			    struct amdgpu_reset_context *reset_context);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -190,7 +197,7 @@ int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);</div><div class='ctx'> #if IS_ENABLED(CONFIG_HSA_AMD)</div><div class='ctx'> bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);</div><div class='ctx'> struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);</div><div class='del'>-int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);</div><div class='add'>+void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo);</div><div class='ctx'> int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,</div><div class='ctx'> 				unsigned long cur_seq, struct kgd_mem *mem);</div><div class='ctx'> int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,</div><div class='hunk'>@@ -210,9 +217,8 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline</div><div class='del'>-int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)</div><div class='add'>+void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline</div><div class='hunk'>@@ -233,7 +239,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,</div><div class='ctx'> int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,</div><div class='ctx'> 				void **mem_obj, uint64_t *gpu_addr,</div><div class='ctx'> 				void **cpu_ptr, bool mqd_gfx9);</div><div class='del'>-void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);</div><div class='add'>+void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj);</div><div class='ctx'> int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,</div><div class='ctx'> 				void **mem_obj);</div><div class='ctx'> void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);</div><div class='hunk'>@@ -252,16 +258,17 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,</div><div class='ctx'> 				  uint64_t *bo_size, void *metadata_buffer,</div><div class='ctx'> 				  size_t buffer_size, uint32_t *metadata_size,</div><div class='ctx'> 				  uint32_t *flags, int8_t *xcp_id);</div><div class='del'>-uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,</div><div class='del'>-					  struct amdgpu_device *src);</div><div class='del'>-int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,</div><div class='del'>-					    struct amdgpu_device *src,</div><div class='del'>-					    bool is_min);</div><div class='ctx'> int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);</div><div class='ctx'> int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,</div><div class='ctx'> 					uint32_t *payload);</div><div class='ctx'> int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,</div><div class='ctx'> 				u32 inst);</div><div class='add'>+int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id);</div><div class='add'>+int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id);</div><div class='add'>+int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,</div><div class='add'>+	bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);</div><div class='add'>+bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id);</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> /* Read user wptr from a specified user address space with page fault</div><div class='ctx'>  * disabled. The memory must be pinned and mapped to the hardware when</div><div class='hunk'>@@ -291,14 +298,10 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,</div><div class='ctx'> 	(&amp;((struct amdgpu_fpriv *)					\</div><div class='ctx'> 		((struct drm_file *)(drm_priv))-&gt;driver_priv)-&gt;vm)</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,</div><div class='del'>-				     struct amdgpu_vm *avm, u32 pasid);</div><div class='ctx'> int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,</div><div class='ctx'> 					struct amdgpu_vm *avm,</div><div class='ctx'> 					void **process_info,</div><div class='ctx'> 					struct dma_fence **ef);</div><div class='del'>-void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,</div><div class='del'>-					void *drm_priv);</div><div class='ctx'> uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);</div><div class='ctx'> size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,</div><div class='ctx'> 					uint8_t xcp_id);</div><div class='hunk'>@@ -320,7 +323,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,</div><div class='ctx'> 					     void **kptr, uint64_t *size);</div><div class='ctx'> void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo);</div><div class='add'>+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,</div><div class='ctx'> 					    struct dma_fence __rcu **ef);</div><div class='hunk'>@@ -336,12 +339,16 @@ void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,</div><div class='ctx'> 				struct tile_config *config);</div><div class='ctx'> void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='del'>-			enum amdgpu_ras_block block, bool reset);</div><div class='add'>+			enum amdgpu_ras_block block, uint32_t reset);</div><div class='add'>+</div><div class='add'>+void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='add'>+			enum amdgpu_ras_block block, uint16_t pasid,</div><div class='add'>+			pasid_notify pasid_fn, void *data, uint32_t reset);</div><div class='add'>+</div><div class='ctx'> bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);</div><div class='del'>-bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);</div><div class='add'>+bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem);</div><div class='ctx'> void amdgpu_amdkfd_block_mmu_notifications(void *p);</div><div class='ctx'> int amdgpu_amdkfd_criu_resume(void *p);</div><div class='del'>-bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,</div><div class='ctx'> 		uint64_t size, u32 alloc_flag, int8_t xcp_id);</div><div class='ctx'> void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,</div><div class='hunk'>@@ -408,15 +415,26 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);</div><div class='ctx'> bool kgd2kfd_device_init(struct kfd_dev *kfd,</div><div class='ctx'> 			 const struct kgd2kfd_shared_resources *gpu_resources);</div><div class='ctx'> void kgd2kfd_device_exit(struct kfd_dev *kfd);</div><div class='del'>-void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);</div><div class='del'>-int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);</div><div class='del'>-int kgd2kfd_pre_reset(struct kfd_dev *kfd);</div><div class='add'>+void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc);</div><div class='add'>+int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc);</div><div class='add'>+void kgd2kfd_suspend_process(struct kfd_dev *kfd);</div><div class='add'>+int kgd2kfd_resume_process(struct kfd_dev *kfd);</div><div class='add'>+int kgd2kfd_pre_reset(struct kfd_dev *kfd,</div><div class='add'>+		      struct amdgpu_reset_context *reset_context);</div><div class='ctx'> int kgd2kfd_post_reset(struct kfd_dev *kfd);</div><div class='ctx'> void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);</div><div class='ctx'> void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);</div><div class='ctx'> void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);</div><div class='del'>-int kgd2kfd_check_and_lock_kfd(void);</div><div class='del'>-void kgd2kfd_unlock_kfd(void);</div><div class='add'>+int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd);</div><div class='add'>+void kgd2kfd_unlock_kfd(struct kfd_dev *kfd);</div><div class='add'>+int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id);</div><div class='add'>+int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd);</div><div class='add'>+int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id);</div><div class='add'>+int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd);</div><div class='add'>+bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id);</div><div class='add'>+bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,</div><div class='add'>+			       bool retry_fault);</div><div class='add'>+</div><div class='ctx'> #else</div><div class='ctx'> static inline int kgd2kfd_init(void)</div><div class='ctx'> {</div><div class='hunk'>@@ -444,16 +462,26 @@ static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)</div><div class='add'>+static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)</div><div class='add'>+static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)</div><div class='add'>+static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int kgd2kfd_resume_process(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd,</div><div class='add'>+				    struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -478,13 +506,45 @@ void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int kgd2kfd_check_and_lock_kfd(void)</div><div class='add'>+static inline int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void kgd2kfd_unlock_kfd(void)</div><div class='add'>+static inline void kgd2kfd_unlock_kfd(struct kfd_dev *kfd)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,</div><div class='add'>+				      bool retry_fault)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='ctx'> #endif /* AMDGPU_AMDKFD_H_INCLUDED */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c<br/>index aff08321e976..7e9f7a280c1b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c</a></div><div class='hunk'>@@ -189,6 +189,9 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = {</div><div class='ctx'> 	.set_address_watch = kgd_gfx_aldebaran_set_address_watch,</div><div class='ctx'> 	.clear_address_watch = kgd_gfx_v9_clear_address_watch,</div><div class='ctx'> 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,</div><div class='del'>-	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,</div><div class='add'>+	.build_dequeue_wait_counts_packet_info = kgd_gfx_v9_build_dequeue_wait_counts_packet_info,</div><div class='ctx'> 	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v9_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c<br/>index 3a3f3ce09f00..1105a09e55dc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c</a></div><div class='hunk'>@@ -20,7 +20,6 @@</div><div class='ctx'>  * OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/fdtable.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> #include &lt;linux/firmware.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='hunk'>@@ -300,7 +299,7 @@ static int suspend_resume_compute_scheduler(struct amdgpu_device *adev, bool sus</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				goto out;</div><div class='ctx'> 		} else {</div><div class='del'>-			drm_sched_start(&amp;ring-&gt;sched, false);</div><div class='add'>+			drm_sched_start(&amp;ring-&gt;sched, 0);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -321,7 +320,7 @@ static void set_barrier_auto_waitcnt(struct amdgpu_device *adev, bool enable_wai</div><div class='ctx'> 	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	amdgpu_amdkfd_suspend(adev, false);</div><div class='add'>+	amdgpu_amdkfd_suspend(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	if (suspend_resume_compute_scheduler(adev, true))</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -334,7 +333,7 @@ static void set_barrier_auto_waitcnt(struct amdgpu_device *adev, bool enable_wai</div><div class='ctx'> out:</div><div class='ctx'> 	suspend_resume_compute_scheduler(adev, false);</div><div class='ctx'> </div><div class='del'>-	amdgpu_amdkfd_resume(adev, false);</div><div class='add'>+	amdgpu_amdkfd_resume(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> }</div><div class='hunk'>@@ -416,7 +415,10 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {</div><div class='ctx'> 	.set_address_watch = kgd_gfx_v9_set_address_watch,</div><div class='ctx'> 	.clear_address_watch = kgd_gfx_v9_clear_address_watch,</div><div class='ctx'> 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,</div><div class='del'>-	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,</div><div class='add'>+	.build_dequeue_wait_counts_packet_info = kgd_gfx_v9_build_dequeue_wait_counts_packet_info,</div><div class='ctx'> 	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,</div><div class='del'>-	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings</div><div class='add'>+	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v9_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c<br/>index a5c7259cf2a3..89a45a9218f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c</a></div><div class='hunk'>@@ -509,6 +509,17 @@ static uint32_t kgd_gfx_v9_4_3_clear_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+						     int engine, int queue)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_offset = get_sdma_rlc_reg_offset(adev, engine, queue);</div><div class='add'>+	uint32_t status = RREG32(regSDMA_RLC0_CONTEXT_STATUS + reg_offset);</div><div class='add'>+	uint32_t doorbell_off = RREG32(regSDMA_RLC0_DOORBELL_OFFSET + reg_offset);</div><div class='add'>+	bool is_active = !!REG_GET_FIELD(status, SDMA_RLC0_CONTEXT_STATUS, SELECTED);</div><div class='add'>+</div><div class='add'>+	return is_active ? doorbell_off &gt;&gt; 2 : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = {</div><div class='ctx'> 	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,</div><div class='ctx'> 	.set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping,</div><div class='hunk'>@@ -530,8 +541,8 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = {</div><div class='ctx'> 	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,</div><div class='ctx'> 	.program_trap_handler_settings =</div><div class='ctx'> 				kgd_gfx_v9_program_trap_handler_settings,</div><div class='del'>-	.build_grace_period_packet_info =</div><div class='del'>-				kgd_gfx_v9_build_grace_period_packet_info,</div><div class='add'>+	.build_dequeue_wait_counts_packet_info =</div><div class='add'>+				kgd_gfx_v9_build_dequeue_wait_counts_packet_info,</div><div class='ctx'> 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,</div><div class='ctx'> 	.enable_debug_trap = kgd_aldebaran_enable_debug_trap,</div><div class='ctx'> 	.disable_debug_trap = kgd_gfx_v9_4_3_disable_debug_trap,</div><div class='hunk'>@@ -541,5 +552,8 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = {</div><div class='ctx'> 			kgd_gfx_v9_4_3_set_wave_launch_trap_override,</div><div class='ctx'> 	.set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,</div><div class='ctx'> 	.set_address_watch = kgd_gfx_v9_4_3_set_address_watch,</div><div class='del'>-	.clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch</div><div class='add'>+	.clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v9_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c<br/>index 69810b3f1c63..0239114fb6c4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c</a></div><div class='hunk'>@@ -352,7 +352,7 @@ static int kgd_hqd_dump(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -449,7 +449,7 @@ static int kgd_hqd_sdma_dump(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (19+6+7+10)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -881,6 +881,7 @@ uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define TCP_WATCH_STRIDE (mmTCP_WATCH1_ADDR_H - mmTCP_WATCH0_ADDR_H)</div><div class='add'>+#define SQ_WATCH_STRIDE (mmSQ_WATCH1_ADDR_H - mmSQ_WATCH0_ADDR_H)</div><div class='ctx'> uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> 					uint64_t watch_address,</div><div class='ctx'> 					uint32_t watch_address_mask,</div><div class='hunk'>@@ -889,55 +890,93 @@ uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> 					uint32_t debug_vmid,</div><div class='ctx'> 					uint32_t inst)</div><div class='ctx'> {</div><div class='add'>+	/* SQ_WATCH?_ADDR_* and TCP_WATCH?_ADDR_* are programmed with the</div><div class='add'>+	 * same values.</div><div class='add'>+	 */</div><div class='ctx'> 	uint32_t watch_address_high;</div><div class='ctx'> 	uint32_t watch_address_low;</div><div class='del'>-	uint32_t watch_address_cntl;</div><div class='del'>-</div><div class='del'>-	watch_address_cntl = 0;</div><div class='add'>+	uint32_t tcp_watch_address_cntl;</div><div class='add'>+	uint32_t sq_watch_address_cntl;</div><div class='ctx'> </div><div class='ctx'> 	watch_address_low = lower_32_bits(watch_address);</div><div class='ctx'> 	watch_address_high = upper_32_bits(watch_address) &amp; 0xffff;</div><div class='ctx'> </div><div class='del'>-	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+	tcp_watch_address_cntl = 0;</div><div class='add'>+	tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,</div><div class='ctx'> 			TCP_WATCH0_CNTL,</div><div class='ctx'> 			VMID,</div><div class='ctx'> 			debug_vmid);</div><div class='del'>-	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+	tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,</div><div class='ctx'> 			TCP_WATCH0_CNTL,</div><div class='ctx'> 			MODE,</div><div class='ctx'> 			watch_mode);</div><div class='del'>-	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+	tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,</div><div class='ctx'> 			TCP_WATCH0_CNTL,</div><div class='ctx'> 			MASK,</div><div class='ctx'> 			watch_address_mask &gt;&gt; 7);</div><div class='ctx'> </div><div class='add'>+	sq_watch_address_cntl = 0;</div><div class='add'>+	sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,</div><div class='add'>+			SQ_WATCH0_CNTL,</div><div class='add'>+			VMID,</div><div class='add'>+			debug_vmid);</div><div class='add'>+	sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,</div><div class='add'>+			SQ_WATCH0_CNTL,</div><div class='add'>+			MODE,</div><div class='add'>+			watch_mode);</div><div class='add'>+	sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,</div><div class='add'>+			SQ_WATCH0_CNTL,</div><div class='add'>+			MASK,</div><div class='add'>+			watch_address_mask &gt;&gt; 6);</div><div class='add'>+</div><div class='ctx'> 	/* Turning off this watch point until we set all the registers */</div><div class='del'>-	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+	tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,</div><div class='ctx'> 			TCP_WATCH0_CNTL,</div><div class='ctx'> 			VALID,</div><div class='ctx'> 			0);</div><div class='del'>-</div><div class='ctx'> 	WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +</div><div class='ctx'> 			(watch_id * TCP_WATCH_STRIDE)),</div><div class='del'>-			watch_address_cntl);</div><div class='add'>+			tcp_watch_address_cntl);</div><div class='ctx'> </div><div class='add'>+	sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,</div><div class='add'>+			SQ_WATCH0_CNTL,</div><div class='add'>+			VALID,</div><div class='add'>+			0);</div><div class='add'>+	WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +</div><div class='add'>+			(watch_id * SQ_WATCH_STRIDE)),</div><div class='add'>+			sq_watch_address_cntl);</div><div class='add'>+</div><div class='add'>+	/* Program {TCP,SQ}_WATCH?_ADDR* */</div><div class='ctx'> 	WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) +</div><div class='ctx'> 			(watch_id * TCP_WATCH_STRIDE)),</div><div class='ctx'> 			watch_address_high);</div><div class='del'>-</div><div class='ctx'> 	WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) +</div><div class='ctx'> 			(watch_id * TCP_WATCH_STRIDE)),</div><div class='ctx'> 			watch_address_low);</div><div class='ctx'> </div><div class='add'>+	WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_H) +</div><div class='add'>+			(watch_id * SQ_WATCH_STRIDE)),</div><div class='add'>+			watch_address_high);</div><div class='add'>+	WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_L) +</div><div class='add'>+			(watch_id * SQ_WATCH_STRIDE)),</div><div class='add'>+			watch_address_low);</div><div class='add'>+</div><div class='ctx'> 	/* Enable the watch point */</div><div class='del'>-	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+	tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,</div><div class='ctx'> 			TCP_WATCH0_CNTL,</div><div class='ctx'> 			VALID,</div><div class='ctx'> 			1);</div><div class='del'>-</div><div class='ctx'> 	WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) +</div><div class='ctx'> 			(watch_id * TCP_WATCH_STRIDE)),</div><div class='del'>-			watch_address_cntl);</div><div class='add'>+			tcp_watch_address_cntl);</div><div class='add'>+</div><div class='add'>+	sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,</div><div class='add'>+			SQ_WATCH0_CNTL,</div><div class='add'>+			VALID,</div><div class='add'>+			1);</div><div class='add'>+	WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +</div><div class='add'>+			(watch_id * SQ_WATCH_STRIDE)),</div><div class='add'>+			sq_watch_address_cntl);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -953,8 +992,14 @@ uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> 			(watch_id * TCP_WATCH_STRIDE)),</div><div class='ctx'> 			watch_address_cntl);</div><div class='ctx'> </div><div class='add'>+	WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) +</div><div class='add'>+			(watch_id * SQ_WATCH_STRIDE)),</div><div class='add'>+			watch_address_cntl);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+#undef TCP_WATCH_STRIDE</div><div class='add'>+#undef SQ_WATCH_STRIDE</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> /* kgd_gfx_v10_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values</div><div class='hunk'>@@ -976,25 +1021,25 @@ void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,</div><div class='ctx'> 	*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,</div><div class='add'>+void kgd_gfx_v10_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev,</div><div class='ctx'> 						uint32_t wait_times,</div><div class='del'>-						uint32_t grace_period,</div><div class='add'>+						uint32_t sch_wave,</div><div class='add'>+						uint32_t que_sleep,</div><div class='ctx'> 						uint32_t *reg_offset,</div><div class='ctx'> 						uint32_t *reg_data)</div><div class='ctx'> {</div><div class='ctx'> 	*reg_data = wait_times;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * The CP cannont handle a 0 grace period input and will result in</div><div class='del'>-	 * an infinite grace period being set so set to 1 to prevent this.</div><div class='del'>-	 */</div><div class='del'>-	if (grace_period == 0)</div><div class='del'>-		grace_period = 1;</div><div class='del'>-</div><div class='del'>-	*reg_data = REG_SET_FIELD(*reg_data,</div><div class='del'>-			CP_IQ_WAIT_TIME2,</div><div class='del'>-			SCH_WAVE,</div><div class='del'>-			grace_period);</div><div class='add'>+	if (sch_wave)</div><div class='add'>+		*reg_data = REG_SET_FIELD(*reg_data,</div><div class='add'>+				CP_IQ_WAIT_TIME2,</div><div class='add'>+				SCH_WAVE,</div><div class='add'>+				sch_wave);</div><div class='add'>+	if (que_sleep)</div><div class='add'>+		*reg_data = REG_SET_FIELD(*reg_data,</div><div class='add'>+				CP_IQ_WAIT_TIME2,</div><div class='add'>+				QUE_SLEEP,</div><div class='add'>+				que_sleep);</div><div class='ctx'> </div><div class='ctx'> 	*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);</div><div class='ctx'> }</div><div class='hunk'>@@ -1025,6 +1070,26 @@ static void program_trap_handler_settings(struct amdgpu_device *adev,</div><div class='ctx'> 	unlock_srbm(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev,</div><div class='add'>+				     uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+				     uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint64_t kgd_gfx_v10_hqd_reset(struct amdgpu_device *adev,</div><div class='add'>+			       uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+			       uint32_t inst, unsigned int utimeout)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t kgd_gfx_v10_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					   int engine, int queue)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct kfd2kgd_calls gfx_v10_kfd2kgd = {</div><div class='ctx'> 	.program_sh_mem_settings = kgd_program_sh_mem_settings,</div><div class='ctx'> 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,</div><div class='hunk'>@@ -1050,6 +1115,9 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {</div><div class='ctx'> 	.set_address_watch = kgd_gfx_v10_set_address_watch,</div><div class='ctx'> 	.clear_address_watch = kgd_gfx_v10_clear_address_watch,</div><div class='ctx'> 	.get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,</div><div class='del'>-	.build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,</div><div class='add'>+	.build_dequeue_wait_counts_packet_info = kgd_gfx_v10_build_dequeue_wait_counts_packet_info,</div><div class='ctx'> 	.program_trap_handler_settings = program_trap_handler_settings,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v10_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v10_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v10_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h<br/>index 67bcaa3d4226..a4c607c88178 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h</a></div><div class='hunk'>@@ -51,8 +51,20 @@ uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev,</div><div class='ctx'> 				uint32_t *wait_times,</div><div class='ctx'> 				uint32_t inst);</div><div class='del'>-void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev,</div><div class='add'>+void kgd_gfx_v10_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev,</div><div class='ctx'> 					       uint32_t wait_times,</div><div class='del'>-					       uint32_t grace_period,</div><div class='add'>+					       uint32_t sch_wave,</div><div class='add'>+					       uint32_t que_sleep,</div><div class='ctx'> 					       uint32_t *reg_offset,</div><div class='ctx'> 					       uint32_t *reg_data);</div><div class='add'>+uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev,</div><div class='add'>+				    uint32_t pipe_id,</div><div class='add'>+				    uint32_t queue_id,</div><div class='add'>+				    uint32_t inst);</div><div class='add'>+uint64_t kgd_gfx_v10_hqd_reset(struct amdgpu_device *adev,</div><div class='add'>+			      uint32_t pipe_id,</div><div class='add'>+			      uint32_t queue_id,</div><div class='add'>+			      uint32_t inst,</div><div class='add'>+			      unsigned int utimeout);</div><div class='add'>+uint32_t kgd_gfx_v10_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					   int engine, int queue);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c<br/>index 8c8437a4383f..f2278a0937ff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c</a></div><div class='hunk'>@@ -338,7 +338,7 @@ static int hqd_dump_v10_3(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -435,7 +435,7 @@ static int hqd_sdma_dump_v10_3(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (19+6+7+12)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -673,12 +673,15 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = {</div><div class='ctx'> 	.set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,</div><div class='ctx'> 	.program_trap_handler_settings = program_trap_handler_settings_v10_3,</div><div class='ctx'> 	.get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,</div><div class='del'>-	.build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,</div><div class='add'>+	.build_dequeue_wait_counts_packet_info = kgd_gfx_v10_build_dequeue_wait_counts_packet_info,</div><div class='ctx'> 	.enable_debug_trap = kgd_gfx_v10_enable_debug_trap,</div><div class='ctx'> 	.disable_debug_trap = kgd_gfx_v10_disable_debug_trap,</div><div class='ctx'> 	.validate_trap_override_request = kgd_gfx_v10_validate_trap_override_request,</div><div class='ctx'> 	.set_wave_launch_trap_override = kgd_gfx_v10_set_wave_launch_trap_override,</div><div class='ctx'> 	.set_wave_launch_mode = kgd_gfx_v10_set_wave_launch_mode,</div><div class='ctx'> 	.set_address_watch = kgd_gfx_v10_set_address_watch,</div><div class='del'>-	.clear_address_watch = kgd_gfx_v10_clear_address_watch</div><div class='add'>+	.clear_address_watch = kgd_gfx_v10_clear_address_watch,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v10_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v10_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v10_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c<br/>index b61a32d6af4b..aaccf0b9947d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c</a></div><div class='hunk'>@@ -323,7 +323,7 @@ static int hqd_dump_v11(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32(addr);		\</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -420,7 +420,7 @@ static int hqd_sdma_dump_v11(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (7+11+1+12+12)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -786,6 +786,26 @@ static uint32_t kgd_gfx_v11_clear_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint64_t kgd_gfx_v11_hqd_get_pq_addr(struct amdgpu_device *adev,</div><div class='add'>+					    uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+					    uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint64_t kgd_gfx_v11_hqd_reset(struct amdgpu_device *adev,</div><div class='add'>+				      uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+				      uint32_t inst, unsigned int utimeout)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t kgd_gfx_v11_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+						  int engine, int queue)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct kfd2kgd_calls gfx_v11_kfd2kgd = {</div><div class='ctx'> 	.program_sh_mem_settings = program_sh_mem_settings_v11,</div><div class='ctx'> 	.set_pasid_vmid_mapping = set_pasid_vmid_mapping_v11,</div><div class='hunk'>@@ -808,5 +828,8 @@ const struct kfd2kgd_calls gfx_v11_kfd2kgd = {</div><div class='ctx'> 	.set_wave_launch_trap_override = kgd_gfx_v11_set_wave_launch_trap_override,</div><div class='ctx'> 	.set_wave_launch_mode = kgd_gfx_v11_set_wave_launch_mode,</div><div class='ctx'> 	.set_address_watch = kgd_gfx_v11_set_address_watch,</div><div class='del'>-	.clear_address_watch = kgd_gfx_v11_clear_address_watch</div><div class='add'>+	.clear_address_watch = kgd_gfx_v11_clear_address_watch,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v11_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v11_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v11_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c<br/>new file mode 100644<br/>index 000000000000..e0ceab400b2d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c</a></div><div class='hunk'>@@ -0,0 +1,384 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_amdkfd.h"</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "soc24.h"</div><div class='add'>+#include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='add'>+</div><div class='add'>+static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,</div><div class='add'>+			uint32_t queue, uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc24_grbm_select(adev, mec, pipe, queue, vmid);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void unlock_srbm(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,</div><div class='add'>+				uint32_t queue_id)</div><div class='add'>+{</div><div class='add'>+	uint32_t mec = (pipe_id / adev-&gt;gfx.mec.num_pipe_per_mec) + 1;</div><div class='add'>+	uint32_t pipe = (pipe_id % adev-&gt;gfx.mec.num_pipe_per_mec);</div><div class='add'>+</div><div class='add'>+	lock_srbm(adev, mec, pipe, queue_id, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void release_queue(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	unlock_srbm(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int init_interrupts_v12(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t mec;</div><div class='add'>+	uint32_t pipe;</div><div class='add'>+</div><div class='add'>+	mec = (pipe_id / adev-&gt;gfx.mec.num_pipe_per_mec) + 1;</div><div class='add'>+	pipe = (pipe_id % adev-&gt;gfx.mec.num_pipe_per_mec);</div><div class='add'>+</div><div class='add'>+	lock_srbm(adev, mec, pipe, 0, 0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCPC_INT_CNTL,</div><div class='add'>+		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |</div><div class='add'>+		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);</div><div class='add'>+</div><div class='add'>+	unlock_srbm(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,</div><div class='add'>+				unsigned int engine_id,</div><div class='add'>+				unsigned int queue_id)</div><div class='add'>+{</div><div class='add'>+	uint32_t sdma_engine_reg_base = 0;</div><div class='add'>+	uint32_t sdma_rlc_reg_offset;</div><div class='add'>+</div><div class='add'>+	switch (engine_id) {</div><div class='add'>+	case 0:</div><div class='add'>+		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,</div><div class='add'>+				regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,</div><div class='add'>+				regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BUG();</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sdma_rlc_reg_offset = sdma_engine_reg_base</div><div class='add'>+		+ queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL);</div><div class='add'>+</div><div class='add'>+	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,</div><div class='add'>+			queue_id, sdma_rlc_reg_offset);</div><div class='add'>+</div><div class='add'>+	return sdma_rlc_reg_offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hqd_dump_v12(struct amdgpu_device *adev,</div><div class='add'>+			uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+			uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t i = 0, reg;</div><div class='add'>+#define HQD_N_REGS 56</div><div class='add'>+#define DUMP_REG(addr) do {				\</div><div class='add'>+		if (WARN_ON_ONCE(i &gt;= HQD_N_REGS))	\</div><div class='add'>+			break;				\</div><div class='add'>+		(*dump)[i][0] = (addr) &lt;&lt; 2;		\</div><div class='add'>+		(*dump)[i++][1] = RREG32(addr);		\</div><div class='add'>+	} while (0)</div><div class='add'>+</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='add'>+	if (*dump == NULL)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	acquire_queue(adev, pipe_id, queue_id);</div><div class='add'>+</div><div class='add'>+	for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);</div><div class='add'>+	     reg &lt;= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)</div><div class='add'>+		DUMP_REG(reg);</div><div class='add'>+</div><div class='add'>+	release_queue(adev);</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(i != HQD_N_REGS);</div><div class='add'>+	*n_regs = i;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hqd_sdma_dump_v12(struct amdgpu_device *adev,</div><div class='add'>+			     uint32_t engine_id, uint32_t queue_id,</div><div class='add'>+			     uint32_t (**dump)[2], uint32_t *n_regs)</div><div class='add'>+{</div><div class='add'>+	uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,</div><div class='add'>+			engine_id, queue_id);</div><div class='add'>+	uint32_t i = 0, reg;</div><div class='add'>+</div><div class='add'>+	const uint32_t first_reg = regSDMA0_QUEUE0_RB_CNTL;</div><div class='add'>+	const uint32_t last_reg = regSDMA0_QUEUE0_CONTEXT_STATUS;</div><div class='add'>+#undef HQD_N_REGS</div><div class='add'>+#define HQD_N_REGS (last_reg - first_reg + 1)</div><div class='add'>+</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='add'>+	if (*dump == NULL)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (reg = first_reg;</div><div class='add'>+	     reg &lt;= last_reg; reg++)</div><div class='add'>+		DUMP_REG(sdma_rlc_reg_offset + reg);</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(i != HQD_N_REGS);</div><div class='add'>+	*n_regs = i;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave_control_execute_v12(struct amdgpu_device *adev,</div><div class='add'>+					uint32_t gfx_index_val,</div><div class='add'>+					uint32_t sq_cmd, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='add'>+</div><div class='add'>+	WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);</div><div class='add'>+	WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);</div><div class='add'>+</div><div class='add'>+	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,</div><div class='add'>+		INSTANCE_BROADCAST_WRITES, 1);</div><div class='add'>+	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,</div><div class='add'>+		SA_BROADCAST_WRITES, 1);</div><div class='add'>+	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,</div><div class='add'>+		SE_BROADCAST_WRITES, 1);</div><div class='add'>+</div><div class='add'>+	WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */</div><div class='add'>+static uint32_t kgd_gfx_v12_enable_debug_trap(struct amdgpu_device *adev,</div><div class='add'>+					    bool restore_dbg_registers,</div><div class='add'>+					    uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);</div><div class='add'>+</div><div class='add'>+	return data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */</div><div class='add'>+static uint32_t kgd_gfx_v12_disable_debug_trap(struct amdgpu_device *adev,</div><div class='add'>+						bool keep_trap_enabled,</div><div class='add'>+						uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);</div><div class='add'>+</div><div class='add'>+	return data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int kgd_gfx_v12_validate_trap_override_request(struct amdgpu_device *adev,</div><div class='add'>+							uint32_t trap_override,</div><div class='add'>+							uint32_t *trap_mask_supported)</div><div class='add'>+{</div><div class='add'>+	*trap_mask_supported &amp;= KFD_DBG_TRAP_MASK_FP_INVALID |</div><div class='add'>+				KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |</div><div class='add'>+				KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |</div><div class='add'>+				KFD_DBG_TRAP_MASK_FP_OVERFLOW |</div><div class='add'>+				KFD_DBG_TRAP_MASK_FP_UNDERFLOW |</div><div class='add'>+				KFD_DBG_TRAP_MASK_FP_INEXACT |</div><div class='add'>+				KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |</div><div class='add'>+				KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |</div><div class='add'>+				KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION |</div><div class='add'>+				KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START |</div><div class='add'>+				KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR &amp;&amp;</div><div class='add'>+			trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	uint32_t trap_on_start = (mask &amp; KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;</div><div class='add'>+	uint32_t trap_on_end = (mask &amp; KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;</div><div class='add'>+	uint32_t excp_en = mask &amp; (KFD_DBG_TRAP_MASK_FP_INVALID |</div><div class='add'>+			KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |</div><div class='add'>+			KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |</div><div class='add'>+			KFD_DBG_TRAP_MASK_FP_OVERFLOW |</div><div class='add'>+			KFD_DBG_TRAP_MASK_FP_UNDERFLOW |</div><div class='add'>+			KFD_DBG_TRAP_MASK_FP_INEXACT |</div><div class='add'>+			KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |</div><div class='add'>+			KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |</div><div class='add'>+			KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION);</div><div class='add'>+	uint32_t ret;</div><div class='add'>+</div><div class='add'>+	ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);</div><div class='add'>+	ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);</div><div class='add'>+	ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);</div><div class='add'>+</div><div class='add'>+	if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START))</div><div class='add'>+		ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START;</div><div class='add'>+</div><div class='add'>+	if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END))</div><div class='add'>+		ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */</div><div class='add'>+static uint32_t kgd_gfx_v12_set_wave_launch_trap_override(struct amdgpu_device *adev,</div><div class='add'>+					uint32_t vmid,</div><div class='add'>+					uint32_t trap_override,</div><div class='add'>+					uint32_t trap_mask_bits,</div><div class='add'>+					uint32_t trap_mask_request,</div><div class='add'>+					uint32_t *trap_mask_prev,</div><div class='add'>+					uint32_t kfd_dbg_trap_cntl_prev)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+</div><div class='add'>+	*trap_mask_prev = trap_mask_map_hw_to_sw(kfd_dbg_trap_cntl_prev);</div><div class='add'>+</div><div class='add'>+	data = (trap_mask_bits &amp; trap_mask_request) | (*trap_mask_prev &amp; ~trap_mask_request);</div><div class='add'>+	data = trap_mask_map_sw_to_hw(data);</div><div class='add'>+</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);</div><div class='add'>+	data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);</div><div class='add'>+</div><div class='add'>+	return data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* returns STALL_VMID or LAUNCH_MODE. */</div><div class='add'>+static uint32_t kgd_gfx_v12_set_wave_launch_mode(struct amdgpu_device *adev,</div><div class='add'>+					uint8_t wave_launch_mode,</div><div class='add'>+					uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+	bool is_stall_mode = wave_launch_mode == 4;</div><div class='add'>+</div><div class='add'>+	if (is_stall_mode)</div><div class='add'>+		data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID,</div><div class='add'>+									1);</div><div class='add'>+	else</div><div class='add'>+		data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE,</div><div class='add'>+							wave_launch_mode);</div><div class='add'>+</div><div class='add'>+	return data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H)</div><div class='add'>+static uint32_t kgd_gfx_v12_set_address_watch(struct amdgpu_device *adev,</div><div class='add'>+					uint64_t watch_address,</div><div class='add'>+					uint32_t watch_address_mask,</div><div class='add'>+					uint32_t watch_id,</div><div class='add'>+					uint32_t watch_mode,</div><div class='add'>+					uint32_t debug_vmid,</div><div class='add'>+					uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t watch_address_high;</div><div class='add'>+	uint32_t watch_address_low;</div><div class='add'>+	uint32_t watch_address_cntl;</div><div class='add'>+</div><div class='add'>+	watch_address_cntl = 0;</div><div class='add'>+	watch_address_low = lower_32_bits(watch_address);</div><div class='add'>+	watch_address_high = upper_32_bits(watch_address) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+			TCP_WATCH0_CNTL,</div><div class='add'>+			MODE,</div><div class='add'>+			watch_mode);</div><div class='add'>+</div><div class='add'>+	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+			TCP_WATCH0_CNTL,</div><div class='add'>+			MASK,</div><div class='add'>+			watch_address_mask &gt;&gt; 7);</div><div class='add'>+</div><div class='add'>+	watch_address_cntl = REG_SET_FIELD(watch_address_cntl,</div><div class='add'>+			TCP_WATCH0_CNTL,</div><div class='add'>+			VALID,</div><div class='add'>+			1);</div><div class='add'>+</div><div class='add'>+	WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +</div><div class='add'>+			(watch_id * TCP_WATCH_STRIDE)),</div><div class='add'>+			watch_address_high);</div><div class='add'>+</div><div class='add'>+	WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +</div><div class='add'>+			(watch_id * TCP_WATCH_STRIDE)),</div><div class='add'>+			watch_address_low);</div><div class='add'>+</div><div class='add'>+	return watch_address_cntl;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t kgd_gfx_v12_clear_address_watch(struct amdgpu_device *adev,</div><div class='add'>+					uint32_t watch_id)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t kgd_gfx_v12_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+						 int engine, int queue)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct kfd2kgd_calls gfx_v12_kfd2kgd = {</div><div class='add'>+	.init_interrupts = init_interrupts_v12,</div><div class='add'>+	.hqd_dump = hqd_dump_v12,</div><div class='add'>+	.hqd_sdma_dump = hqd_sdma_dump_v12,</div><div class='add'>+	.wave_control_execute = wave_control_execute_v12,</div><div class='add'>+	.get_atc_vmid_pasid_mapping_info = NULL,</div><div class='add'>+	.enable_debug_trap = kgd_gfx_v12_enable_debug_trap,</div><div class='add'>+	.disable_debug_trap = kgd_gfx_v12_disable_debug_trap,</div><div class='add'>+	.validate_trap_override_request = kgd_gfx_v12_validate_trap_override_request,</div><div class='add'>+	.set_wave_launch_trap_override = kgd_gfx_v12_set_wave_launch_trap_override,</div><div class='add'>+	.set_wave_launch_mode = kgd_gfx_v12_set_wave_launch_mode,</div><div class='add'>+	.set_address_watch = kgd_gfx_v12_set_address_watch,</div><div class='add'>+	.clear_address_watch = kgd_gfx_v12_clear_address_watch,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c<br/>index ca4a6b82817f..df77558e03ef 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c</a></div><div class='hunk'>@@ -561,6 +561,13 @@ static uint32_t read_vmid_from_vmfault_reg(struct amdgpu_device *adev)</div><div class='ctx'> 	return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t kgd_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					  int engine, int queue)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct kfd2kgd_calls gfx_v7_kfd2kgd = {</div><div class='ctx'> 	.program_sh_mem_settings = kgd_program_sh_mem_settings,</div><div class='ctx'> 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,</div><div class='hunk'>@@ -578,4 +585,5 @@ const struct kfd2kgd_calls gfx_v7_kfd2kgd = {</div><div class='ctx'> 	.set_scratch_backing_va = set_scratch_backing_va,</div><div class='ctx'> 	.set_vm_context_page_table_base = set_vm_context_page_table_base,</div><div class='ctx'> 	.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_hqd_sdma_get_doorbell,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c<br/>index 0f3e2944edd7..e68c0fa8d751 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c</a></div><div class='hunk'>@@ -582,6 +582,13 @@ static void set_vm_context_page_table_base(struct amdgpu_device *adev,</div><div class='ctx'> 			lower_32_bits(page_table_base));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t kgd_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					  int engine, int queue)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct kfd2kgd_calls gfx_v8_kfd2kgd = {</div><div class='ctx'> 	.program_sh_mem_settings = kgd_program_sh_mem_settings,</div><div class='ctx'> 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,</div><div class='hunk'>@@ -599,4 +606,5 @@ const struct kfd2kgd_calls gfx_v8_kfd2kgd = {</div><div class='ctx'> 			get_atc_vmid_pasid_mapping_info,</div><div class='ctx'> 	.set_scratch_backing_va = set_scratch_backing_va,</div><div class='ctx'> 	.set_vm_context_page_table_base = set_vm_context_page_table_base,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_hqd_sdma_get_doorbell,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br/>index 5a35a8ca8922..088d09cc7a72 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c</a></div><div class='hunk'>@@ -944,34 +944,34 @@ static void unlock_spi_csq_mutexes(struct amdgpu_device *adev)</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: Handle of device whose registers are to be read</div><div class='ctx'>  * @queue_idx: Index of queue in the queue-map bit-field</div><div class='del'>- * @wave_cnt: Output parameter updated with number of waves in flight</div><div class='del'>- * @vmid: Output parameter updated with VMID of queue whose wave count</div><div class='del'>- *        is being collected</div><div class='add'>+ * @queue_cnt: Stores the wave count and doorbell offset for an active queue</div><div class='ctx'>  * @inst: xcc's instance number on a multi-XCC setup</div><div class='ctx'>  */</div><div class='ctx'> static void get_wave_count(struct amdgpu_device *adev, int queue_idx,</div><div class='del'>-		int *wave_cnt, int *vmid, uint32_t inst)</div><div class='add'>+		struct kfd_cu_occupancy *queue_cnt, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	int pipe_idx;</div><div class='ctx'> 	int queue_slot;</div><div class='ctx'> 	unsigned int reg_val;</div><div class='del'>-</div><div class='add'>+	unsigned int wave_cnt;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Program GRBM with appropriate MEID, PIPEID, QUEUEID and VMID</div><div class='ctx'> 	 * parameters to read out waves in flight. Get VMID if there are</div><div class='ctx'> 	 * non-zero waves in flight.</div><div class='ctx'> 	 */</div><div class='del'>-	*vmid = 0xFF;</div><div class='del'>-	*wave_cnt = 0;</div><div class='ctx'> 	pipe_idx = queue_idx / adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='ctx'> 	queue_slot = queue_idx % adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='del'>-	soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, inst);</div><div class='del'>-	reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +</div><div class='del'>-			 queue_slot);</div><div class='del'>-	*wave_cnt = reg_val &amp; SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;</div><div class='del'>-	if (*wave_cnt != 0)</div><div class='del'>-		*vmid = (RREG32_SOC15(GC, inst, mmCP_HQD_VMID) &amp;</div><div class='del'>-			 CP_HQD_VMID__VMID_MASK) &gt;&gt; CP_HQD_VMID__VMID__SHIFT;</div><div class='add'>+	soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst));</div><div class='add'>+	reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst),</div><div class='add'>+				  mmSPI_CSQ_WF_ACTIVE_COUNT_0) + queue_slot);</div><div class='add'>+	wave_cnt = reg_val &amp; SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;</div><div class='add'>+	if (wave_cnt != 0) {</div><div class='add'>+		queue_cnt-&gt;wave_cnt += wave_cnt;</div><div class='add'>+		queue_cnt-&gt;doorbell_off =</div><div class='add'>+			(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &amp;</div><div class='add'>+			 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK) &gt;&gt;</div><div class='add'>+			 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -981,9 +981,8 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx,</div><div class='ctx'>  * or more queues running and submitting waves to compute units.</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: Handle of device from which to get number of waves in flight</div><div class='del'>- * @pasid: Identifies the process for which this query call is invoked</div><div class='del'>- * @pasid_wave_cnt: Output parameter updated with number of waves in flight that</div><div class='del'>- *                  belong to process with given pasid</div><div class='add'>+ * @cu_occupancy: Array that gets filled with wave_cnt and doorbell offset</div><div class='add'>+ *		  for comparison later.</div><div class='ctx'>  * @max_waves_per_cu: Output parameter updated with maximum number of waves</div><div class='ctx'>  *                    possible per Compute Unit</div><div class='ctx'>  * @inst: xcc's instance number on a multi-XCC setup</div><div class='hunk'>@@ -1011,34 +1010,28 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx,</div><div class='ctx'>  *    number of waves that are in flight for the queue at specified index. The</div><div class='ctx'>  *    index ranges from 0 to 7.</div><div class='ctx'>  *</div><div class='del'>- *    If non-zero waves are in flight, read CP_HQD_VMID register to obtain VMID</div><div class='del'>- *    of the wave(s).</div><div class='add'>+ *    If non-zero waves are in flight, store the corresponding doorbell offset</div><div class='add'>+ *    of the queue, along with the wave count.</div><div class='ctx'>  *</div><div class='del'>- *    Determine if VMID from above step maps to pasid provided as parameter. If</div><div class='del'>- *    it matches agrregate the wave count. That the VMID will not match pasid is</div><div class='del'>- *    a normal condition i.e. a device is expected to support multiple queues</div><div class='del'>- *    from multiple proceses.</div><div class='add'>+ *    Determine if the queue belongs to the process by comparing the doorbell</div><div class='add'>+ *    offset against the process's queues. If it matches, aggregate the wave</div><div class='add'>+ *    count for the process.</div><div class='ctx'>  *</div><div class='ctx'>  *  Reading registers referenced above involves programming GRBM appropriately</div><div class='ctx'>  */</div><div class='del'>-void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,</div><div class='del'>-		int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst)</div><div class='add'>+void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev,</div><div class='add'>+				 struct kfd_cu_occupancy *cu_occupancy,</div><div class='add'>+				 int *max_waves_per_cu, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	int qidx;</div><div class='del'>-	int vmid;</div><div class='ctx'> 	int se_idx;</div><div class='del'>-	int sh_idx;</div><div class='ctx'> 	int se_cnt;</div><div class='del'>-	int sh_cnt;</div><div class='del'>-	int wave_cnt;</div><div class='ctx'> 	int queue_map;</div><div class='del'>-	int pasid_tmp;</div><div class='ctx'> 	int max_queue_cnt;</div><div class='del'>-	int vmid_wave_cnt = 0;</div><div class='ctx'> 	DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);</div><div class='ctx'> </div><div class='ctx'> 	lock_spi_csq_mutexes(adev);</div><div class='del'>-	soc15_grbm_select(adev, 1, 0, 0, 0, inst);</div><div class='add'>+	soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst));</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Iterate through the shader engines and arrays of the device</div><div class='hunk'>@@ -1048,74 +1041,61 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,</div><div class='ctx'> 			  AMDGPU_MAX_QUEUES);</div><div class='ctx'> 	max_queue_cnt = adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='ctx'> 			adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='del'>-	sh_cnt = adev-&gt;gfx.config.max_sh_per_se;</div><div class='ctx'> 	se_cnt = adev-&gt;gfx.config.max_shader_engines;</div><div class='ctx'> 	for (se_idx = 0; se_idx &lt; se_cnt; se_idx++) {</div><div class='del'>-		for (sh_idx = 0; sh_idx &lt; sh_cnt; sh_idx++) {</div><div class='add'>+		amdgpu_gfx_select_se_sh(adev, se_idx, 0, 0xffffffff, inst);</div><div class='add'>+		queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Assumption: queue map encodes following schema: four</div><div class='add'>+		 * pipes per each micro-engine, with each pipe mapping</div><div class='add'>+		 * eight queues. This schema is true for GFX9 devices</div><div class='add'>+		 * and must be verified for newer device families</div><div class='add'>+		 */</div><div class='add'>+		for (qidx = 0; qidx &lt; max_queue_cnt; qidx++) {</div><div class='add'>+			/* Skip qeueus that are not associated with</div><div class='add'>+			 * compute functions</div><div class='add'>+			 */</div><div class='add'>+			if (!test_bit(qidx, cp_queue_bitmap))</div><div class='add'>+				continue;</div><div class='ctx'> </div><div class='del'>-			amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff, inst);</div><div class='del'>-			queue_map = RREG32_SOC15(GC, inst, mmSPI_CSQ_WF_ACTIVE_STATUS);</div><div class='add'>+			if (!(queue_map &amp; (1 &lt;&lt; qidx)))</div><div class='add'>+				continue;</div><div class='ctx'> </div><div class='del'>-			/*</div><div class='del'>-			 * Assumption: queue map encodes following schema: four</div><div class='del'>-			 * pipes per each micro-engine, with each pipe mapping</div><div class='del'>-			 * eight queues. This schema is true for GFX9 devices</div><div class='del'>-			 * and must be verified for newer device families</div><div class='del'>-			 */</div><div class='del'>-			for (qidx = 0; qidx &lt; max_queue_cnt; qidx++) {</div><div class='del'>-</div><div class='del'>-				/* Skip qeueus that are not associated with</div><div class='del'>-				 * compute functions</div><div class='del'>-				 */</div><div class='del'>-				if (!test_bit(qidx, cp_queue_bitmap))</div><div class='del'>-					continue;</div><div class='del'>-</div><div class='del'>-				if (!(queue_map &amp; (1 &lt;&lt; qidx)))</div><div class='del'>-					continue;</div><div class='del'>-</div><div class='del'>-				/* Get number of waves in flight and aggregate them */</div><div class='del'>-				get_wave_count(adev, qidx, &amp;wave_cnt, &amp;vmid,</div><div class='del'>-						inst);</div><div class='del'>-				if (wave_cnt != 0) {</div><div class='del'>-					pasid_tmp =</div><div class='del'>-					  RREG32(SOC15_REG_OFFSET(OSSSYS, inst,</div><div class='del'>-						 mmIH_VMID_0_LUT) + vmid);</div><div class='del'>-					if (pasid_tmp == pasid)</div><div class='del'>-						vmid_wave_cnt += wave_cnt;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='add'>+			/* Get number of waves in flight and aggregate them */</div><div class='add'>+			get_wave_count(adev, qidx, &amp;cu_occupancy[qidx],</div><div class='add'>+					inst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, inst);</div><div class='del'>-	soc15_grbm_select(adev, 0, 0, 0, 0, inst);</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst));</div><div class='ctx'> 	unlock_spi_csq_mutexes(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* Update the output parameters and return */</div><div class='del'>-	*pasid_wave_cnt = vmid_wave_cnt;</div><div class='ctx'> 	*max_waves_per_cu = adev-&gt;gfx.cu_info.simd_per_cu *</div><div class='ctx'> 				adev-&gt;gfx.cu_info.max_waves_per_simd;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev,</div><div class='add'>+void kgd_gfx_v9_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev,</div><div class='ctx'> 		uint32_t wait_times,</div><div class='del'>-		uint32_t grace_period,</div><div class='add'>+		uint32_t sch_wave,</div><div class='add'>+		uint32_t que_sleep,</div><div class='ctx'> 		uint32_t *reg_offset,</div><div class='ctx'> 		uint32_t *reg_data)</div><div class='ctx'> {</div><div class='ctx'> 	*reg_data = wait_times;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * The CP cannot handle a 0 grace period input and will result in</div><div class='del'>-	 * an infinite grace period being set so set to 1 to prevent this.</div><div class='del'>-	 */</div><div class='del'>-	if (grace_period == 0)</div><div class='del'>-		grace_period = 1;</div><div class='del'>-</div><div class='del'>-	*reg_data = REG_SET_FIELD(*reg_data,</div><div class='del'>-			CP_IQ_WAIT_TIME2,</div><div class='del'>-			SCH_WAVE,</div><div class='del'>-			grace_period);</div><div class='add'>+	if (sch_wave)</div><div class='add'>+		*reg_data = REG_SET_FIELD(*reg_data,</div><div class='add'>+				CP_IQ_WAIT_TIME2,</div><div class='add'>+				SCH_WAVE,</div><div class='add'>+				sch_wave);</div><div class='add'>+	if (que_sleep)</div><div class='add'>+		*reg_data = REG_SET_FIELD(*reg_data,</div><div class='add'>+				CP_IQ_WAIT_TIME2,</div><div class='add'>+				QUE_SLEEP,</div><div class='add'>+				que_sleep);</div><div class='ctx'> </div><div class='ctx'> 	*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);</div><div class='ctx'> }</div><div class='hunk'>@@ -1144,6 +1124,112 @@ void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,</div><div class='ctx'> 	kgd_gfx_v9_unlock_srbm(adev, inst);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev,</div><div class='add'>+				    uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+				    uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t low, high;</div><div class='add'>+	uint64_t queue_addr = 0;</div><div class='add'>+</div><div class='add'>+	kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, inst);</div><div class='add'>+</div><div class='add'>+	if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))</div><div class='add'>+		goto unlock_out;</div><div class='add'>+</div><div class='add'>+	low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);</div><div class='add'>+	high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);</div><div class='add'>+</div><div class='add'>+	/* only concerned with user queues. */</div><div class='add'>+	if (!high)</div><div class='add'>+		goto unlock_out;</div><div class='add'>+</div><div class='add'>+	queue_addr = (((queue_addr | high) &lt;&lt; 32) | low) &lt;&lt; 8;</div><div class='add'>+</div><div class='add'>+unlock_out:</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, inst);</div><div class='add'>+	kgd_gfx_v9_release_queue(adev, inst);</div><div class='add'>+</div><div class='add'>+	return queue_addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* assume queue acquired  */</div><div class='add'>+static int kgd_gfx_v9_hqd_dequeue_wait(struct amdgpu_device *adev, uint32_t inst,</div><div class='add'>+				       unsigned int utimeout)</div><div class='add'>+{</div><div class='add'>+	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;</div><div class='add'>+</div><div class='add'>+	while (true) {</div><div class='add'>+		uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);</div><div class='add'>+</div><div class='add'>+		if (!(temp &amp; CP_HQD_ACTIVE__ACTIVE_MASK))</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		if (time_after(jiffies, end_jiffies))</div><div class='add'>+			return -ETIME;</div><div class='add'>+</div><div class='add'>+		usleep_range(500, 1000);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev,</div><div class='add'>+			      uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+			      uint32_t inst, unsigned int utimeout)</div><div class='add'>+{</div><div class='add'>+	uint32_t low, high, pipe_reset_data = 0;</div><div class='add'>+	uint64_t queue_addr = 0;</div><div class='add'>+</div><div class='add'>+	kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, inst);</div><div class='add'>+</div><div class='add'>+	if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))</div><div class='add'>+		goto unlock_out;</div><div class='add'>+</div><div class='add'>+	low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);</div><div class='add'>+	high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);</div><div class='add'>+</div><div class='add'>+	/* only concerned with user queues. */</div><div class='add'>+	if (!high)</div><div class='add'>+		goto unlock_out;</div><div class='add'>+</div><div class='add'>+	queue_addr = (((queue_addr | high) &lt;&lt; 32) | low) &lt;&lt; 8;</div><div class='add'>+</div><div class='add'>+	pr_debug("Attempting queue reset on XCC %i pipe id %i queue id %i\n",</div><div class='add'>+		 inst, pipe_id, queue_id);</div><div class='add'>+</div><div class='add'>+	/* assume previous dequeue request issued will take affect after reset */</div><div class='add'>+	WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='add'>+</div><div class='add'>+	if (!kgd_gfx_v9_hqd_dequeue_wait(adev, inst, utimeout))</div><div class='add'>+		goto unlock_out;</div><div class='add'>+</div><div class='add'>+	pr_debug("Attempting pipe reset on XCC %i pipe id %i\n", inst, pipe_id);</div><div class='add'>+</div><div class='add'>+	pipe_reset_data = REG_SET_FIELD(pipe_reset_data, CP_MEC_CNTL, MEC_ME1_PIPE0_RESET, 1);</div><div class='add'>+	pipe_reset_data = pipe_reset_data &lt;&lt; pipe_id;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);</div><div class='add'>+	WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);</div><div class='add'>+</div><div class='add'>+	if (kgd_gfx_v9_hqd_dequeue_wait(adev, inst, utimeout))</div><div class='add'>+		queue_addr = 0;</div><div class='add'>+</div><div class='add'>+unlock_out:</div><div class='add'>+	pr_debug("queue reset on XCC %i pipe id %i queue id %i %s\n",</div><div class='add'>+		 inst, pipe_id, queue_id, !!queue_addr ? "succeeded!" : "failed!");</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, inst);</div><div class='add'>+	kgd_gfx_v9_release_queue(adev, inst);</div><div class='add'>+</div><div class='add'>+	return queue_addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					  int engine, int queue)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct kfd2kgd_calls gfx_v9_kfd2kgd = {</div><div class='ctx'> 	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,</div><div class='ctx'> 	.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,</div><div class='hunk'>@@ -1169,7 +1255,10 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {</div><div class='ctx'> 	.set_address_watch = kgd_gfx_v9_set_address_watch,</div><div class='ctx'> 	.clear_address_watch = kgd_gfx_v9_clear_address_watch,</div><div class='ctx'> 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,</div><div class='del'>-	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,</div><div class='add'>+	.build_dequeue_wait_counts_packet_info = kgd_gfx_v9_build_dequeue_wait_counts_packet_info,</div><div class='ctx'> 	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,</div><div class='ctx'> 	.program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,</div><div class='add'>+	.hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr,</div><div class='add'>+	.hqd_reset = kgd_gfx_v9_hqd_reset,</div><div class='add'>+	.hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h<br/>index ce424615f59b..704452ca62f8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h</a></div><div class='hunk'>@@ -52,8 +52,9 @@ bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,</div><div class='ctx'> 					uint8_t vmid, uint16_t *p_pasid);</div><div class='ctx'> void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,</div><div class='ctx'> 			uint32_t vmid, uint64_t page_table_base);</div><div class='del'>-void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,</div><div class='del'>-		int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst);</div><div class='add'>+void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev,</div><div class='add'>+				 struct kfd_cu_occupancy *cu_occupancy,</div><div class='add'>+				 int *max_waves_per_cu, uint32_t inst);</div><div class='ctx'> void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,</div><div class='ctx'> 		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,</div><div class='ctx'> 		uint32_t inst);</div><div class='hunk'>@@ -96,8 +97,20 @@ uint32_t kgd_gfx_v9_clear_address_watch(struct amdgpu_device *adev,</div><div class='ctx'> void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev,</div><div class='ctx'> 				uint32_t *wait_times,</div><div class='ctx'> 				uint32_t inst);</div><div class='del'>-void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev,</div><div class='add'>+void kgd_gfx_v9_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev,</div><div class='ctx'> 					       uint32_t wait_times,</div><div class='del'>-					       uint32_t grace_period,</div><div class='add'>+					       uint32_t sch_wave,</div><div class='add'>+					       uint32_t que_sleep,</div><div class='ctx'> 					       uint32_t *reg_offset,</div><div class='ctx'> 					       uint32_t *reg_data);</div><div class='add'>+uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev,</div><div class='add'>+				    uint32_t pipe_id,</div><div class='add'>+				    uint32_t queue_id,</div><div class='add'>+				    uint32_t inst);</div><div class='add'>+uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev,</div><div class='add'>+			      uint32_t pipe_id,</div><div class='add'>+			      uint32_t queue_id,</div><div class='add'>+			      uint32_t inst,</div><div class='add'>+			      unsigned int utimeout);</div><div class='add'>+uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					  int engine, int queue);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c<br/>index df58a6a1a67e..b1c24c8fa686 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c</a></div><div class='hunk'>@@ -25,7 +25,6 @@</div><div class='ctx'> #include &lt;linux/pagemap.h&gt;</div><div class='ctx'> #include &lt;linux/sched/mm.h&gt;</div><div class='ctx'> #include &lt;linux/sched/task.h&gt;</div><div class='del'>-#include &lt;linux/fdtable.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_exec.h&gt;</div><div class='hunk'>@@ -172,6 +171,8 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t reserved_for_pt =</div><div class='ctx'> 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	uint64_t reserved_for_ras = (con ? con-&gt;reserved_pages_in_bytes : 0);</div><div class='ctx'> 	size_t system_mem_needed, ttm_mem_needed, vram_needed;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	uint64_t vram_size = 0;</div><div class='hunk'>@@ -196,7 +197,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);</div><div class='del'>-		if (adev-&gt;gmc.is_app_apu) {</div><div class='add'>+		if (adev-&gt;apu_prefer_gtt) {</div><div class='ctx'> 			system_mem_needed = size;</div><div class='ctx'> 			ttm_mem_needed = size;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -212,19 +213,35 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,</div><div class='ctx'> 	spin_lock(&amp;kfd_mem_limit.mem_limit_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (kfd_mem_limit.system_mem_used + system_mem_needed &gt;</div><div class='del'>-	    kfd_mem_limit.max_system_mem_limit)</div><div class='add'>+	    kfd_mem_limit.max_system_mem_limit) {</div><div class='ctx'> 		pr_debug("Set no_system_mem_limit=1 if using shared memory\n");</div><div class='add'>+		if (!no_system_mem_limit) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto release;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if ((kfd_mem_limit.system_mem_used + system_mem_needed &gt;</div><div class='del'>-	     kfd_mem_limit.max_system_mem_limit &amp;&amp; !no_system_mem_limit) ||</div><div class='del'>-	    (kfd_mem_limit.ttm_mem_used + ttm_mem_needed &gt;</div><div class='del'>-	     kfd_mem_limit.max_ttm_mem_limit) ||</div><div class='del'>-	    (adev &amp;&amp; xcp_id &gt;= 0 &amp;&amp; adev-&gt;kfd.vram_used[xcp_id] + vram_needed &gt;</div><div class='del'>-	     vram_size - reserved_for_pt)) {</div><div class='add'>+	if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed &gt;</div><div class='add'>+		kfd_mem_limit.max_ttm_mem_limit) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='ctx'> 		goto release;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with</div><div class='add'>+	 * carve out &lt; gtt. In that case, VRAM allocation will go to gtt domain, skip</div><div class='add'>+	 * VRAM check since ttm_mem_limit check already cover this allocation</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (adev &amp;&amp; xcp_id &gt;= 0 &amp;&amp; (!adev-&gt;apu_prefer_gtt || adev-&gt;gmc.is_app_apu)) {</div><div class='add'>+		uint64_t vram_available =</div><div class='add'>+			vram_size - reserved_for_pt - reserved_for_ras -</div><div class='add'>+			atomic64_read(&amp;adev-&gt;vram_pin_size);</div><div class='add'>+		if (adev-&gt;kfd.vram_used[xcp_id] + vram_needed &gt; vram_available) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto release;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Update memory accounting by decreasing available system</div><div class='ctx'> 	 * memory, TTM memory and GPU memory as computed above</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -232,7 +249,8 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,</div><div class='ctx'> 		  "adev reference can't be null when vram is used");</div><div class='ctx'> 	if (adev &amp;&amp; xcp_id &gt;= 0) {</div><div class='ctx'> 		adev-&gt;kfd.vram_used[xcp_id] += vram_needed;</div><div class='del'>-		adev-&gt;kfd.vram_used_aligned[xcp_id] += adev-&gt;gmc.is_app_apu ?</div><div class='add'>+		adev-&gt;kfd.vram_used_aligned[xcp_id] +=</div><div class='add'>+				adev-&gt;apu_prefer_gtt ?</div><div class='ctx'> 				vram_needed :</div><div class='ctx'> 				ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -260,7 +278,7 @@ void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 		if (adev) {</div><div class='ctx'> 			adev-&gt;kfd.vram_used[xcp_id] -= size;</div><div class='del'>-			if (adev-&gt;gmc.is_app_apu) {</div><div class='add'>+			if (adev-&gt;apu_prefer_gtt) {</div><div class='ctx'> 				adev-&gt;kfd.vram_used_aligned[xcp_id] -= size;</div><div class='ctx'> 				kfd_mem_limit.system_mem_used -= size;</div><div class='ctx'> 				kfd_mem_limit.ttm_mem_used -= size;</div><div class='hunk'>@@ -368,40 +386,32 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_amdkfd_remove_all_eviction_fences - Remove all eviction fences</div><div class='add'>+ * @bo: the BO where to remove the evictions fences from.</div><div class='add'>+ *</div><div class='add'>+ * This functions should only be used on release when all references to the BO</div><div class='add'>+ * are already dropped. We remove the eviction fence from the private copy of</div><div class='add'>+ * the dma_resv object here since that is what is used during release to</div><div class='add'>+ * determine of the BO is idle or not.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *root = bo;</div><div class='del'>-	struct amdgpu_vm_bo_base *vm_bo;</div><div class='del'>-	struct amdgpu_vm *vm;</div><div class='del'>-	struct amdkfd_process_info *info;</div><div class='del'>-	struct amdgpu_amdkfd_fence *ef;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	/* we can always get vm_bo from root PD bo.*/</div><div class='del'>-	while (root-&gt;parent)</div><div class='del'>-		root = root-&gt;parent;</div><div class='add'>+	struct dma_resv *resv = &amp;bo-&gt;tbo.base._resv;</div><div class='add'>+	struct dma_fence *fence, *stub;</div><div class='add'>+	struct dma_resv_iter cursor;</div><div class='ctx'> </div><div class='del'>-	vm_bo = root-&gt;vm_bo;</div><div class='del'>-	if (!vm_bo)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	vm = vm_bo-&gt;vm;</div><div class='del'>-	if (!vm)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	info = vm-&gt;process_info;</div><div class='del'>-	if (!info || !info-&gt;eviction_fence)</div><div class='del'>-		return 0;</div><div class='add'>+	dma_resv_assert_held(resv);</div><div class='ctx'> </div><div class='del'>-	ef = container_of(dma_fence_get(&amp;info-&gt;eviction_fence-&gt;base),</div><div class='del'>-			struct amdgpu_amdkfd_fence, base);</div><div class='del'>-</div><div class='del'>-	BUG_ON(!dma_resv_trylock(bo-&gt;tbo.base.resv));</div><div class='del'>-	ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);</div><div class='del'>-	dma_resv_unlock(bo-&gt;tbo.base.resv);</div><div class='add'>+	stub = dma_fence_get_stub();</div><div class='add'>+	dma_resv_for_each_fence(&amp;cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {</div><div class='add'>+		if (!to_amdgpu_amdkfd_fence(fence))</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-	dma_fence_put(&amp;ef-&gt;base);</div><div class='del'>-	return ret;</div><div class='add'>+		dma_resv_replace_fences(resv, fence-&gt;context, stub,</div><div class='add'>+					DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	}</div><div class='add'>+	dma_fence_put(stub);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,</div><div class='hunk'>@@ -414,6 +424,10 @@ static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,</div><div class='ctx'> 		 "Called with userptr BO"))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	/* bo has been pinned, not need validate it */</div><div class='add'>+	if (bo-&gt;tbo.pin_count)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_bo_placement_from_domain(bo, domain);</div><div class='ctx'> </div><div class='ctx'> 	ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='hunk'>@@ -493,10 +507,11 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	return amdgpu_sync_fence(sync, vm-&gt;last_update);</div><div class='add'>+	return amdgpu_sync_fence(sync, vm-&gt;last_update, GFP_KERNEL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)</div><div class='add'>+static uint64_t get_pte_flags(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='add'>+			      struct kgd_mem *mem)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |</div><div class='ctx'> 				 AMDGPU_VM_MTYPE_DEFAULT;</div><div class='hunk'>@@ -506,7 +521,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)</div><div class='ctx'> 	if (mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)</div><div class='ctx'> 		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;</div><div class='ctx'> </div><div class='del'>-	return amdgpu_gem_va_map_flags(adev, mapping_flags);</div><div class='add'>+	return mapping_flags;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -597,12 +612,6 @@ kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)</div><div class='ctx'> {</div><div class='ctx'> 	struct ttm_operation_ctx ctx = {.interruptible = true};</div><div class='ctx'> 	struct amdgpu_bo *bo = attachment-&gt;bo_va-&gt;base.bo;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);</div><div class='del'>-	ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);</div><div class='ctx'> 	return ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='hunk'>@@ -724,7 +733,7 @@ kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);</div><div class='del'>-	ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+	(void)ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='ctx'> </div><div class='ctx'> 	dma_unmap_sgtable(adev-&gt;dev, ttm-&gt;sg, direction, 0);</div><div class='ctx'> 	sg_free_table(ttm-&gt;sg);</div><div class='hunk'>@@ -773,7 +782,7 @@ kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);</div><div class='del'>-	ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+	(void)ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='ctx'> </div><div class='ctx'> 	dir = mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?</div><div class='ctx'> 				DMA_BIDIRECTIONAL : DMA_TO_DEVICE;</div><div class='hunk'>@@ -811,18 +820,13 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem)</div><div class='ctx'> 	if (!mem-&gt;dmabuf) {</div><div class='ctx'> 		struct amdgpu_device *bo_adev;</div><div class='ctx'> 		struct dma_buf *dmabuf;</div><div class='del'>-		int r, fd;</div><div class='ctx'> </div><div class='ctx'> 		bo_adev = amdgpu_ttm_adev(mem-&gt;bo-&gt;tbo.bdev);</div><div class='del'>-		r = drm_gem_prime_handle_to_fd(&amp;bo_adev-&gt;ddev, bo_adev-&gt;kfd.client.file,</div><div class='add'>+		dmabuf = drm_gem_prime_handle_to_dmabuf(&amp;bo_adev-&gt;ddev, bo_adev-&gt;kfd.client.file,</div><div class='ctx'> 					       mem-&gt;gem_handle,</div><div class='ctx'> 			mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?</div><div class='del'>-					       DRM_RDWR : 0, &amp;fd);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-		dmabuf = dma_buf_get(fd);</div><div class='del'>-		close_fd(fd);</div><div class='del'>-		if (WARN_ON_ONCE(IS_ERR(dmabuf)))</div><div class='add'>+					       DRM_RDWR : 0);</div><div class='add'>+		if (IS_ERR(dmabuf))</div><div class='ctx'> 			return PTR_ERR(dmabuf);</div><div class='ctx'> 		mem-&gt;dmabuf = dmabuf;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -889,7 +893,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,</div><div class='ctx'> 	 * if peer device has large BAR. In contrast, access over xGMI is</div><div class='ctx'> 	 * allowed for both small and large BAR configurations of peer device</div><div class='ctx'> 	 */</div><div class='del'>-	if ((adev != bo_adev &amp;&amp; !adev-&gt;gmc.is_app_apu) &amp;&amp;</div><div class='add'>+	if ((adev != bo_adev &amp;&amp; !adev-&gt;apu_prefer_gtt) &amp;&amp;</div><div class='ctx'> 	    ((mem-&gt;domain == AMDGPU_GEM_DOMAIN_VRAM) ||</div><div class='ctx'> 	     (mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||</div><div class='ctx'> 	     (mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {</div><div class='hunk'>@@ -974,7 +978,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,</div><div class='ctx'> 			goto unwind;</div><div class='ctx'> 		}</div><div class='ctx'> 		attachment[i]-&gt;va = va;</div><div class='del'>-		attachment[i]-&gt;pte_flags = get_pte_flags(adev, mem);</div><div class='add'>+		attachment[i]-&gt;pte_flags = get_pte_flags(adev, vm, mem);</div><div class='ctx'> 		attachment[i]-&gt;adev = adev;</div><div class='ctx'> 		list_add(&amp;attachment[i]-&gt;list, &amp;mem-&gt;attachments);</div><div class='ctx'> </div><div class='hunk'>@@ -988,7 +992,7 @@ unwind:</div><div class='ctx'> 		if (!attachment[i])</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (attachment[i]-&gt;bo_va) {</div><div class='del'>-			amdgpu_bo_reserve(bo[i], true);</div><div class='add'>+			(void)amdgpu_bo_reserve(bo[i], true);</div><div class='ctx'> 			if (--attachment[i]-&gt;bo_va-&gt;ref_count == 0)</div><div class='ctx'> 				amdgpu_vm_bo_del(adev, attachment[i]-&gt;bo_va);</div><div class='ctx'> 			amdgpu_bo_unreserve(bo[i]);</div><div class='hunk'>@@ -1053,7 +1057,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,</div><div class='ctx'> 	struct amdkfd_process_info *process_info = mem-&gt;process_info;</div><div class='ctx'> 	struct amdgpu_bo *bo = mem-&gt;bo;</div><div class='ctx'> 	struct ttm_operation_ctx ctx = { true, false };</div><div class='del'>-	struct hmm_range *range;</div><div class='add'>+	struct amdgpu_hmm_range *range;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;process_info-&gt;lock);</div><div class='hunk'>@@ -1085,9 +1089,19 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_ttm_tt_get_user_pages(bo, bo-&gt;tbo.ttm-&gt;pages, &amp;range);</div><div class='add'>+	range = amdgpu_hmm_range_alloc(NULL);</div><div class='add'>+	if (unlikely(!range)) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto unregister_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_ttm_tt_get_user_pages(bo, range);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		pr_err("%s: Failed to get user pages: %d\n", __func__, ret);</div><div class='add'>+		amdgpu_hmm_range_free(range);</div><div class='add'>+		if (ret == -EAGAIN)</div><div class='add'>+			pr_debug("Failed to get user pages, try again\n");</div><div class='add'>+		else</div><div class='add'>+			pr_err("%s: Failed to get user pages: %d\n", __func__, ret);</div><div class='ctx'> 		goto unregister_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1096,6 +1110,9 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,</div><div class='ctx'> 		pr_err("%s: Failed to reserve BO\n", __func__);</div><div class='ctx'> 		goto release_out;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ttm_tt_set_user_pages(bo-&gt;tbo.ttm, range);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_bo_placement_from_domain(bo, mem-&gt;domain);</div><div class='ctx'> 	ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -1103,7 +1120,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,</div><div class='ctx'> 	amdgpu_bo_unreserve(bo);</div><div class='ctx'> </div><div class='ctx'> release_out:</div><div class='del'>-	amdgpu_ttm_tt_get_user_pages_done(bo-&gt;tbo.ttm, range);</div><div class='add'>+	amdgpu_hmm_range_free(range);</div><div class='ctx'> unregister_out:</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		amdgpu_hmm_unregister(bo);</div><div class='hunk'>@@ -1188,7 +1205,8 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;sync = &amp;mem-&gt;sync;</div><div class='del'>-	drm_exec_init(&amp;ctx-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+	drm_exec_init(&amp;ctx-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT |</div><div class='add'>+		      DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;ctx-&gt;exec) {</div><div class='ctx'> 		ctx-&gt;n_vms = 0;</div><div class='ctx'> 		list_for_each_entry(entry, &amp;mem-&gt;attachments, list) {</div><div class='hunk'>@@ -1241,7 +1259,7 @@ static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void unmap_bo_from_gpuvm(struct kgd_mem *mem,</div><div class='add'>+static int unmap_bo_from_gpuvm(struct kgd_mem *mem,</div><div class='ctx'> 				struct kfd_mem_attachment *entry,</div><div class='ctx'> 				struct amdgpu_sync *sync)</div><div class='ctx'> {</div><div class='hunk'>@@ -1249,11 +1267,22 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,</div><div class='ctx'> 	struct amdgpu_device *adev = entry-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vm *vm = bo_va-&gt;base.vm;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vm_bo_unmap(adev, bo_va, entry-&gt;va);</div><div class='add'>+	if (bo_va-&gt;queue_refcount) {</div><div class='add'>+		pr_debug("bo_va-&gt;queue_refcount %d\n", bo_va-&gt;queue_refcount);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	(void)amdgpu_vm_bo_unmap(adev, bo_va, entry-&gt;va);</div><div class='add'>+</div><div class='add'>+	/* VM entity stopped if process killed, don't clear freed pt bo */</div><div class='add'>+	if (!amdgpu_vm_ready(vm))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vm_clear_freed(adev, vm, &amp;bo_va-&gt;last_pt_update);</div><div class='add'>+	(void)amdgpu_vm_clear_freed(adev, vm, &amp;bo_va-&gt;last_pt_update);</div><div class='ctx'> </div><div class='del'>-	amdgpu_sync_fence(sync, bo_va-&gt;last_pt_update);</div><div class='add'>+	(void)amdgpu_sync_fence(sync, bo_va-&gt;last_pt_update, GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int update_gpuvm_pte(struct kgd_mem *mem,</div><div class='hunk'>@@ -1275,7 +1304,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return amdgpu_sync_fence(sync, bo_va-&gt;last_pt_update);</div><div class='add'>+	return amdgpu_sync_fence(sync, bo_va-&gt;last_pt_update, GFP_KERNEL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int map_bo_to_gpuvm(struct kgd_mem *mem,</div><div class='hunk'>@@ -1427,8 +1456,8 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,</div><div class='ctx'> 	list_add_tail(&amp;vm-&gt;vm_list_node,</div><div class='ctx'> 			&amp;(vm-&gt;process_info-&gt;vm_list_head));</div><div class='ctx'> 	vm-&gt;process_info-&gt;n_vms++;</div><div class='del'>-</div><div class='del'>-	*ef = dma_fence_get(&amp;vm-&gt;process_info-&gt;eviction_fence-&gt;base);</div><div class='add'>+	if (ef)</div><div class='add'>+		*ef = dma_fence_get(&amp;vm-&gt;process_info-&gt;eviction_fence-&gt;base);</div><div class='ctx'> 	mutex_unlock(&amp;vm-&gt;process_info-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1470,13 +1499,30 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)</div><div class='ctx'> 	if (unlikely(ret))</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);</div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) {</div><div class='add'>+		/*</div><div class='add'>+		 * If bo is not contiguous on VRAM, move to system memory first to ensure</div><div class='add'>+		 * we can get contiguous VRAM space after evicting other BOs.</div><div class='add'>+		 */</div><div class='add'>+		if (!(bo-&gt;tbo.resource-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS)) {</div><div class='add'>+			struct ttm_operation_ctx ctx = { true, false };</div><div class='add'>+</div><div class='add'>+			amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);</div><div class='add'>+			ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+			if (unlikely(ret)) {</div><div class='add'>+				pr_debug("validate bo 0x%p to GTT failed %d\n", &amp;bo-&gt;tbo, ret);</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_pin(bo, domain);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		pr_err("Error in Pinning BO to domain: %d\n", domain);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);</div><div class='add'>+out:</div><div class='ctx'> 	amdgpu_bo_unreserve(bo);</div><div class='del'>-</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1500,27 +1546,6 @@ static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)</div><div class='ctx'> 	amdgpu_bo_unreserve(bo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,</div><div class='del'>-				     struct amdgpu_vm *avm, u32 pasid)</div><div class='del'>-</div><div class='del'>-{</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	/* Free the original amdgpu allocated pasid,</div><div class='del'>-	 * will be replaced with kfd allocated pasid.</div><div class='del'>-	 */</div><div class='del'>-	if (avm-&gt;pasid) {</div><div class='del'>-		amdgpu_pasid_free(avm-&gt;pasid);</div><div class='del'>-		amdgpu_vm_set_pasid(adev, avm, 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = amdgpu_vm_set_pasid(adev, avm, pasid);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,</div><div class='ctx'> 					   struct amdgpu_vm *avm,</div><div class='ctx'> 					   void **process_info,</div><div class='hunk'>@@ -1578,27 +1603,6 @@ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,</div><div class='del'>-					    void *drm_priv)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_vm *avm;</div><div class='del'>-</div><div class='del'>-	if (WARN_ON(!adev || !drm_priv))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	avm = drm_priv_to_vm(drm_priv);</div><div class='del'>-</div><div class='del'>-	pr_debug("Releasing process vm %p\n", avm);</div><div class='del'>-</div><div class='del'>-	/* The original pasid of amdgpu vm has already been</div><div class='del'>-	 * released during making a amdgpu vm to a compute vm</div><div class='del'>-	 * The current pasid is managed by kfd and will be</div><div class='del'>-	 * released on kfd process destroy. Set amdgpu pasid</div><div class='del'>-	 * to 0 to avoid duplicate release.</div><div class='del'>-	 */</div><div class='del'>-	amdgpu_vm_release_compute(adev, avm);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);</div><div class='hunk'>@@ -1647,16 +1651,23 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t reserved_for_pt =</div><div class='ctx'> 		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	uint64_t reserved_for_ras = (con ? con-&gt;reserved_pages_in_bytes : 0);</div><div class='ctx'> 	ssize_t available;</div><div class='ctx'> 	uint64_t vram_available, system_mem_available, ttm_mem_available;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;kfd_mem_limit.mem_limit_lock);</div><div class='del'>-	vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)</div><div class='del'>-		- adev-&gt;kfd.vram_used_aligned[xcp_id]</div><div class='del'>-		- atomic64_read(&amp;adev-&gt;vram_pin_size)</div><div class='del'>-		- reserved_for_pt;</div><div class='add'>+	if (adev-&gt;apu_prefer_gtt &amp;&amp; !adev-&gt;gmc.is_app_apu)</div><div class='add'>+		vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)</div><div class='add'>+			- adev-&gt;kfd.vram_used_aligned[xcp_id];</div><div class='add'>+	else</div><div class='add'>+		vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)</div><div class='add'>+			- adev-&gt;kfd.vram_used_aligned[xcp_id]</div><div class='add'>+			- atomic64_read(&amp;adev-&gt;vram_pin_size)</div><div class='add'>+			- reserved_for_pt</div><div class='add'>+			- reserved_for_ras;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.is_app_apu) {</div><div class='add'>+	if (adev-&gt;apu_prefer_gtt) {</div><div class='ctx'> 		system_mem_available = no_system_mem_limit ?</div><div class='ctx'> 					kfd_mem_limit.max_system_mem_limit :</div><div class='ctx'> 					kfd_mem_limit.max_system_mem_limit -</div><div class='hunk'>@@ -1704,7 +1715,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(</div><div class='ctx'> 	if (flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {</div><div class='ctx'> 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;gmc.is_app_apu) {</div><div class='add'>+		if (adev-&gt;apu_prefer_gtt) {</div><div class='ctx'> 			domain = AMDGPU_GEM_DOMAIN_GTT;</div><div class='ctx'> 			alloc_domain = AMDGPU_GEM_DOMAIN_GTT;</div><div class='ctx'> 			alloc_flags = 0;</div><div class='hunk'>@@ -1712,6 +1723,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(</div><div class='ctx'> 			alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;</div><div class='ctx'> 			alloc_flags |= (flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?</div><div class='ctx'> 			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;</div><div class='add'>+</div><div class='add'>+			/* For contiguous VRAM allocation */</div><div class='add'>+			if (flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_CONTIGUOUS)</div><div class='add'>+				alloc_flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 		}</div><div class='ctx'> 		xcp_id = fpriv-&gt;xcp_id == AMDGPU_XCP_NO_PARTITION ?</div><div class='ctx'> 					0 : fpriv-&gt;xcp_id;</div><div class='hunk'>@@ -1854,6 +1869,7 @@ err_node_allow:</div><div class='ctx'> err_bo_create:</div><div class='ctx'> 	amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);</div><div class='ctx'> err_reserve_limit:</div><div class='add'>+	amdgpu_sync_free(&amp;(*mem)-&gt;sync);</div><div class='ctx'> 	mutex_destroy(&amp;(*mem)-&gt;lock);</div><div class='ctx'> 	if (gobj)</div><div class='ctx'> 		drm_gem_object_put(gobj);</div><div class='hunk'>@@ -1911,7 +1927,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(</div><div class='ctx'> 	if (amdgpu_ttm_tt_get_usermm(mem-&gt;bo-&gt;tbo.ttm)) {</div><div class='ctx'> 		amdgpu_hmm_unregister(mem-&gt;bo);</div><div class='ctx'> 		mutex_lock(&amp;process_info-&gt;notifier_lock);</div><div class='del'>-		amdgpu_ttm_tt_discard_user_pages(mem-&gt;bo-&gt;tbo.ttm, mem-&gt;range);</div><div class='add'>+		amdgpu_hmm_range_free(mem-&gt;range);</div><div class='ctx'> 		mutex_unlock(&amp;process_info-&gt;notifier_lock);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1949,9 +1965,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (size) {</div><div class='ctx'> 		if (!is_imported &amp;&amp;</div><div class='del'>-		   (mem-&gt;bo-&gt;preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||</div><div class='del'>-		   (adev-&gt;gmc.is_app_apu &amp;&amp;</div><div class='del'>-		    mem-&gt;bo-&gt;preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))</div><div class='add'>+		   mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_VRAM)</div><div class='ctx'> 			*size = bo_size;</div><div class='ctx'> 		else</div><div class='ctx'> 			*size = 0;</div><div class='hunk'>@@ -2155,7 +2169,10 @@ int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(</div><div class='ctx'> 		pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",</div><div class='ctx'> 			 entry-&gt;va, entry-&gt;va + bo_size, entry);</div><div class='ctx'> </div><div class='del'>-		unmap_bo_from_gpuvm(mem, entry, ctx.sync);</div><div class='add'>+		ret = unmap_bo_from_gpuvm(mem, entry, ctx.sync);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto unreserve_out;</div><div class='add'>+</div><div class='ctx'> 		entry-&gt;is_mapped = false;</div><div class='ctx'> </div><div class='ctx'> 		mem-&gt;mapped_to_gpu_memory--;</div><div class='hunk'>@@ -2190,11 +2207,12 @@ int amdgpu_amdkfd_gpuvm_sync_memory(</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count</div><div class='ctx'>  * @bo: Buffer object to be mapped</div><div class='add'>+ * @bo_gart: Return bo reference</div><div class='ctx'>  *</div><div class='ctx'>  * Before return, bo reference count is incremented. To release the reference and unpin/</div><div class='ctx'>  * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)</div><div class='add'>+int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -2221,7 +2239,7 @@ int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_unreserve(bo);</div><div class='ctx'> </div><div class='del'>-	bo = amdgpu_bo_ref(bo);</div><div class='add'>+	*bo_gart = amdgpu_bo_ref(bo);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -2311,7 +2329,7 @@ void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo *bo = mem-&gt;bo;</div><div class='ctx'> </div><div class='del'>-	amdgpu_bo_reserve(bo, true);</div><div class='add'>+	(void)amdgpu_bo_reserve(bo, true);</div><div class='ctx'> 	amdgpu_bo_kunmap(bo);</div><div class='ctx'> 	amdgpu_bo_unpin(bo);</div><div class='ctx'> 	amdgpu_bo_unreserve(bo);</div><div class='hunk'>@@ -2320,10 +2338,9 @@ void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)</div><div class='ctx'> int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,</div><div class='ctx'> 					  struct kfd_vm_fault_info *mem)</div><div class='ctx'> {</div><div class='del'>-	if (atomic_read(&amp;adev-&gt;gmc.vm_fault_info_updated) == 1) {</div><div class='add'>+	if (atomic_read_acquire(&amp;adev-&gt;gmc.vm_fault_info_updated) == 1) {</div><div class='ctx'> 		*mem = *adev-&gt;gmc.vm_fault_info;</div><div class='del'>-		mb(); /* make sure read happened */</div><div class='del'>-		atomic_set(&amp;adev-&gt;gmc.vm_fault_info_updated, 0);</div><div class='add'>+		atomic_set_release(&amp;adev-&gt;gmc.vm_fault_info_updated, 0);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2372,8 +2389,9 @@ static int import_obj_create(struct amdgpu_device *adev,</div><div class='ctx'> 	(*mem)-&gt;dmabuf = dma_buf;</div><div class='ctx'> 	(*mem)-&gt;bo = bo;</div><div class='ctx'> 	(*mem)-&gt;va = va;</div><div class='del'>-	(*mem)-&gt;domain = (bo-&gt;preferred_domains &amp; AMDGPU_GEM_DOMAIN_VRAM) &amp;&amp; !adev-&gt;gmc.is_app_apu ?</div><div class='del'>-		AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;</div><div class='add'>+	(*mem)-&gt;domain = (bo-&gt;preferred_domains &amp; AMDGPU_GEM_DOMAIN_VRAM) &amp;&amp;</div><div class='add'>+			 !adev-&gt;apu_prefer_gtt ?</div><div class='add'>+			 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;</div><div class='ctx'> </div><div class='ctx'> 	(*mem)-&gt;mapped_to_gpu_memory = 0;</div><div class='ctx'> 	(*mem)-&gt;process_info = avm-&gt;process_info;</div><div class='hunk'>@@ -2482,11 +2500,14 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,</div><div class='ctx'> 		/* First eviction, stop the queues */</div><div class='ctx'> 		r = kgd2kfd_quiesce_mm(mni-&gt;mm,</div><div class='ctx'> 				       KFD_QUEUE_EVICTION_TRIGGER_USERPTR);</div><div class='del'>-		if (r)</div><div class='add'>+</div><div class='add'>+		if (r &amp;&amp; r != -ESRCH)</div><div class='ctx'> 			pr_err("Failed to quiesce KFD\n");</div><div class='del'>-		queue_delayed_work(system_freezable_wq,</div><div class='del'>-			&amp;process_info-&gt;restore_userptr_work,</div><div class='del'>-			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));</div><div class='add'>+</div><div class='add'>+		if (r != -ESRCH)</div><div class='add'>+			queue_delayed_work(system_freezable_wq,</div><div class='add'>+				&amp;process_info-&gt;restore_userptr_work,</div><div class='add'>+				msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;process_info-&gt;notifier_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -2530,7 +2551,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,</div><div class='ctx'> </div><div class='ctx'> 		bo = mem-&gt;bo;</div><div class='ctx'> </div><div class='del'>-		amdgpu_ttm_tt_discard_user_pages(bo-&gt;tbo.ttm, mem-&gt;range);</div><div class='add'>+		amdgpu_hmm_range_free(mem-&gt;range);</div><div class='ctx'> 		mem-&gt;range = NULL;</div><div class='ctx'> </div><div class='ctx'> 		/* BO reservations and getting user pages (hmm_range_fault)</div><div class='hunk'>@@ -2554,10 +2575,14 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		mem-&gt;range = amdgpu_hmm_range_alloc(NULL);</div><div class='add'>+		if (unlikely(!mem-&gt;range))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 		/* Get updated user pages */</div><div class='del'>-		ret = amdgpu_ttm_tt_get_user_pages(bo, bo-&gt;tbo.ttm-&gt;pages,</div><div class='del'>-						   &amp;mem-&gt;range);</div><div class='add'>+		ret = amdgpu_ttm_tt_get_user_pages(bo, mem-&gt;range);</div><div class='ctx'> 		if (ret) {</div><div class='add'>+			amdgpu_hmm_range_free(mem-&gt;range);</div><div class='add'>+			mem-&gt;range = NULL;</div><div class='ctx'> 			pr_debug("Failed %d to get user pages\n", ret);</div><div class='ctx'> </div><div class='ctx'> 			/* Return -EFAULT bad address error as success. It will</div><div class='hunk'>@@ -2570,9 +2595,28 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info,</div><div class='ctx'> 			if (ret != -EFAULT)</div><div class='ctx'> 				return ret;</div><div class='ctx'> </div><div class='add'>+			/* If applications unmap memory before destroying the userptr</div><div class='add'>+			 * from the KFD, trigger a segmentation fault in VM debug mode.</div><div class='add'>+			 */</div><div class='add'>+			if (amdgpu_ttm_adev(bo-&gt;tbo.bdev)-&gt;debug_vm_userptr) {</div><div class='add'>+				struct kfd_process *p;</div><div class='add'>+</div><div class='add'>+				pr_err("Pid %d unmapped memory before destroying userptr at GPU addr 0x%llx\n",</div><div class='add'>+								pid_nr(process_info-&gt;pid), mem-&gt;va);</div><div class='add'>+</div><div class='add'>+				// Send GPU VM fault to user space</div><div class='add'>+				p = kfd_lookup_process_by_pid(process_info-&gt;pid);</div><div class='add'>+				if (p) {</div><div class='add'>+					kfd_signal_vm_fault_event_with_userptr(p, mem-&gt;va);</div><div class='add'>+					kfd_unref_process(p);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			ret = 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		amdgpu_ttm_tt_set_user_pages(bo-&gt;tbo.ttm, mem-&gt;range);</div><div class='add'>+</div><div class='ctx'> 		mutex_lock(&amp;process_info-&gt;notifier_lock);</div><div class='ctx'> </div><div class='ctx'> 		/* Mark the BO as valid unless it was invalidated</div><div class='hunk'>@@ -2708,11 +2752,11 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i</div><div class='ctx'> </div><div class='ctx'> 		/* keep mem without hmm range at userptr_inval_list */</div><div class='ctx'> 		if (!mem-&gt;range)</div><div class='del'>-			 continue;</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* Only check mem with hmm range associated */</div><div class='del'>-		valid = amdgpu_ttm_tt_get_user_pages_done(</div><div class='del'>-					mem-&gt;bo-&gt;tbo.ttm, mem-&gt;range);</div><div class='add'>+		valid = amdgpu_hmm_range_valid(mem-&gt;range);</div><div class='add'>+		amdgpu_hmm_range_free(mem-&gt;range);</div><div class='ctx'> </div><div class='ctx'> 		mem-&gt;range = NULL;</div><div class='ctx'> 		if (!valid) {</div><div class='hunk'>@@ -2900,13 +2944,12 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu *</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_create(&amp;sync_obj);</div><div class='ctx'> </div><div class='del'>-	/* Validate BOs and map them to GPUVM (update VM page tables). */</div><div class='add'>+	/* Validate BOs managed by KFD */</div><div class='ctx'> 	list_for_each_entry(mem, &amp;process_info-&gt;kfd_bo_list,</div><div class='ctx'> 			    validate_list) {</div><div class='ctx'> </div><div class='ctx'> 		struct amdgpu_bo *bo = mem-&gt;bo;</div><div class='ctx'> 		uint32_t domain = mem-&gt;domain;</div><div class='del'>-		struct kfd_mem_attachment *attachment;</div><div class='ctx'> 		struct dma_resv_iter cursor;</div><div class='ctx'> 		struct dma_fence *fence;</div><div class='ctx'> </div><div class='hunk'>@@ -2925,26 +2968,12 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu *</div><div class='ctx'> 		}</div><div class='ctx'> 		dma_resv_for_each_fence(&amp;cursor, bo-&gt;tbo.base.resv,</div><div class='ctx'> 					DMA_RESV_USAGE_KERNEL, fence) {</div><div class='del'>-			ret = amdgpu_sync_fence(&amp;sync_obj, fence);</div><div class='add'>+			ret = amdgpu_sync_fence(&amp;sync_obj, fence, GFP_KERNEL);</div><div class='ctx'> 			if (ret) {</div><div class='ctx'> 				pr_debug("Memory eviction: Sync BO fence failed. Try again\n");</div><div class='ctx'> 				goto validate_map_fail;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-		list_for_each_entry(attachment, &amp;mem-&gt;attachments, list) {</div><div class='del'>-			if (!attachment-&gt;is_mapped)</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			if (attachment-&gt;bo_va-&gt;base.bo-&gt;tbo.pin_count)</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			kfd_mem_dmaunmap_attachment(mem, attachment);</div><div class='del'>-			ret = update_gpuvm_pte(mem, attachment, &amp;sync_obj);</div><div class='del'>-			if (ret) {</div><div class='del'>-				pr_debug("Memory eviction: update PTE failed. Try again\n");</div><div class='del'>-				goto validate_map_fail;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (failed_size)</div><div class='hunk'>@@ -2959,15 +2988,46 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu *</div><div class='ctx'> 		goto validate_map_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Update mappings managed by KFD. */</div><div class='add'>+	list_for_each_entry(mem, &amp;process_info-&gt;kfd_bo_list,</div><div class='add'>+			    validate_list) {</div><div class='add'>+		struct kfd_mem_attachment *attachment;</div><div class='add'>+</div><div class='add'>+		list_for_each_entry(attachment, &amp;mem-&gt;attachments, list) {</div><div class='add'>+			if (!attachment-&gt;is_mapped)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			kfd_mem_dmaunmap_attachment(mem, attachment);</div><div class='add'>+			ret = update_gpuvm_pte(mem, attachment, &amp;sync_obj);</div><div class='add'>+			if (ret) {</div><div class='add'>+				pr_debug("Memory eviction: update PTE failed. Try again\n");</div><div class='add'>+				goto validate_map_fail;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Update mappings not managed by KFD */</div><div class='ctx'> 	list_for_each_entry(peer_vm, &amp;process_info-&gt;vm_list_head,</div><div class='ctx'> 			vm_list_node) {</div><div class='ctx'> 		struct amdgpu_device *adev = amdgpu_ttm_adev(</div><div class='ctx'> 			peer_vm-&gt;root.bo-&gt;tbo.bdev);</div><div class='ctx'> </div><div class='add'>+		struct amdgpu_fpriv *fpriv =</div><div class='add'>+			container_of(peer_vm, struct amdgpu_fpriv, vm);</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_vm_bo_update(adev, fpriv-&gt;prt_va, false);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(adev-&gt;dev,</div><div class='add'>+				"Memory eviction: handle PRT moved failed, pid %8d. Try again.\n",</div><div class='add'>+				pid_nr(process_info-&gt;pid));</div><div class='add'>+			goto validate_map_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		ret = amdgpu_vm_handle_moved(adev, peer_vm, &amp;exec.ticket);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			pr_debug("Memory eviction: handle moved failed. Try again\n");</div><div class='add'>+			dev_dbg(adev-&gt;dev,</div><div class='add'>+				"Memory eviction: handle moved failed, pid %8d. Try again.\n",</div><div class='add'>+				pid_nr(process_info-&gt;pid));</div><div class='ctx'> 			goto validate_map_fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3160,12 +3220,13 @@ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)</div><div class='add'>+bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_vm *vm = drm_priv_to_vm(drm_priv);</div><div class='ctx'> 	struct kfd_mem_attachment *entry;</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(entry, &amp;mem-&gt;attachments, list) {</div><div class='del'>-		if (entry-&gt;is_mapped &amp;&amp; entry-&gt;adev == adev)</div><div class='add'>+		if (entry-&gt;is_mapped &amp;&amp; entry-&gt;bo_va-&gt;base.vm == vm)</div><div class='ctx'> 			return true;</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c<br/>index 52b12c1718eb..763f2b8dcf13 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c</a></div><div class='hunk'>@@ -36,13 +36,6 @@</div><div class='ctx'> #include "atombios_encoders.h"</div><div class='ctx'> #include "bif/bif_4_1_d.h"</div><div class='ctx'> </div><div class='del'>-static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,</div><div class='del'>-					  ATOM_GPIO_I2C_ASSIGMENT *gpio,</div><div class='del'>-					  u8 index)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_i2c_bus_rec i2c;</div><div class='hunk'>@@ -108,9 +101,6 @@ struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *</div><div class='ctx'> </div><div class='ctx'> 		gpio = &amp;i2c_info-&gt;asGPIO_Info[0];</div><div class='ctx'> 		for (i = 0; i &lt; num_indices; i++) {</div><div class='del'>-</div><div class='del'>-			amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);</div><div class='del'>-</div><div class='ctx'> 			if (gpio-&gt;sucI2cId.ucAccess == id) {</div><div class='ctx'> 				i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);</div><div class='ctx'> 				break;</div><div class='hunk'>@@ -142,8 +132,6 @@ void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		gpio = &amp;i2c_info-&gt;asGPIO_Info[0];</div><div class='ctx'> 		for (i = 0; i &lt; num_indices; i++) {</div><div class='del'>-			amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);</div><div class='del'>-</div><div class='ctx'> 			i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);</div><div class='ctx'> </div><div class='ctx'> 			if (i2c.valid) {</div><div class='hunk'>@@ -156,6 +144,38 @@ void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id)</div><div class='add'>+{</div><div class='add'>+	struct atom_context *ctx = adev-&gt;mode_info.atom_context;</div><div class='add'>+	ATOM_GPIO_I2C_ASSIGMENT *gpio;</div><div class='add'>+	struct amdgpu_i2c_bus_rec i2c;</div><div class='add'>+	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);</div><div class='add'>+	struct _ATOM_GPIO_I2C_INFO *i2c_info;</div><div class='add'>+	uint16_t data_offset, size;</div><div class='add'>+	int i, num_indices;</div><div class='add'>+	char stmp[32];</div><div class='add'>+</div><div class='add'>+	if (amdgpu_atom_parse_data_header(ctx, index, &amp;size, NULL, NULL, &amp;data_offset)) {</div><div class='add'>+		i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx-&gt;bios + data_offset);</div><div class='add'>+</div><div class='add'>+		num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /</div><div class='add'>+			sizeof(ATOM_GPIO_I2C_ASSIGMENT);</div><div class='add'>+</div><div class='add'>+		gpio = &amp;i2c_info-&gt;asGPIO_Info[0];</div><div class='add'>+		for (i = 0; i &lt; num_indices; i++) {</div><div class='add'>+			i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);</div><div class='add'>+</div><div class='add'>+			if (i2c.valid &amp;&amp; i2c.i2c_id == i2c_id) {</div><div class='add'>+				sprintf(stmp, "OEM 0x%x", i2c.i2c_id);</div><div class='add'>+				adev-&gt;i2c_bus[i] = amdgpu_i2c_create(adev_to_drm(adev), &amp;i2c, stmp);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			gpio = (ATOM_GPIO_I2C_ASSIGMENT *)</div><div class='add'>+				((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct amdgpu_gpio_rec</div><div class='ctx'> amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,</div><div class='ctx'> 			    u8 id)</div><div class='hunk'>@@ -686,7 +706,6 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 		adev-&gt;clock.dp_extclk =</div><div class='ctx'> 			le16_to_cpu(firmware_info-&gt;info_21.usUniphyDPModeExtClkFreq);</div><div class='del'>-		adev-&gt;clock.current_dispclk = adev-&gt;clock.default_dispclk;</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;clock.max_pixel_clock = le16_to_cpu(firmware_info-&gt;info.usMaxPixelClock);</div><div class='ctx'> 		if (adev-&gt;clock.max_pixel_clock == 0)</div><div class='hunk'>@@ -1018,8 +1037,9 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 		if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {</div><div class='ctx'> 			args.v3.ulClockParams = cpu_to_le32((clock_type &lt;&lt; 24) | clock);</div><div class='ctx'> </div><div class='del'>-			amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-				sizeof(args));</div><div class='add'>+			if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+			    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+				return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 			dividers-&gt;post_div = args.v3.ucPostDiv;</div><div class='ctx'> 			dividers-&gt;enable_post_div = (args.v3.ucCntlFlag &amp;</div><div class='hunk'>@@ -1039,8 +1059,9 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 			if (strobe_mode)</div><div class='ctx'> 				args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;</div><div class='ctx'> </div><div class='del'>-			amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-				sizeof(args));</div><div class='add'>+			if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+			    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+				return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 			dividers-&gt;post_div = args.v5.ucPostDiv;</div><div class='ctx'> 			dividers-&gt;enable_post_div = (args.v5.ucCntlFlag &amp;</div><div class='hunk'>@@ -1058,8 +1079,9 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 		/* fusion */</div><div class='ctx'> 		args.v4.ulClock = cpu_to_le32(clock);	/* 10 khz */</div><div class='ctx'> </div><div class='del'>-		amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-			sizeof(args));</div><div class='add'>+		if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+		    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		dividers-&gt;post_divider = dividers-&gt;post_div = args.v4.ucPostDiv;</div><div class='ctx'> 		dividers-&gt;real_clock = le32_to_cpu(args.v4.ulClock);</div><div class='hunk'>@@ -1070,8 +1092,9 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 		args.v6_in.ulClock.ulComputeClockFlag = clock_type;</div><div class='ctx'> 		args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);	/* 10 khz */</div><div class='ctx'> </div><div class='del'>-		amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-			sizeof(args));</div><div class='add'>+		if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+		    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		dividers-&gt;whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);</div><div class='ctx'> 		dividers-&gt;frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);</div><div class='hunk'>@@ -1113,8 +1136,9 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 			if (strobe_mode)</div><div class='ctx'> 				args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;</div><div class='ctx'> </div><div class='del'>-			amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-				sizeof(args));</div><div class='add'>+			if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+			    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+				return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 			mpll_param-&gt;clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);</div><div class='ctx'> 			mpll_param-&gt;clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);</div><div class='hunk'>@@ -1140,8 +1164,8 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,</div><div class='del'>-					     u32 eng_clock, u32 mem_clock)</div><div class='add'>+int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,</div><div class='add'>+					    u32 eng_clock, u32 mem_clock)</div><div class='ctx'> {</div><div class='ctx'> 	SET_ENGINE_CLOCK_PS_ALLOCATION args;</div><div class='ctx'> 	int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);</div><div class='hunk'>@@ -1156,8 +1180,8 @@ void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,</div><div class='ctx'> 	if (mem_clock)</div><div class='ctx'> 		args.sReserved.ulClock = cpu_to_le32(mem_clock &amp; SET_CLOCK_FREQ_MASK);</div><div class='ctx'> </div><div class='del'>-	amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-		sizeof(args));</div><div class='add'>+	return amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index,</div><div class='add'>+					 (uint32_t *)&amp;args, sizeof(args));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,</div><div class='hunk'>@@ -1211,8 +1235,9 @@ int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,</div><div class='ctx'> 		args.v2.ucVoltageMode = 0;</div><div class='ctx'> 		args.v2.usVoltageLevel = 0;</div><div class='ctx'> </div><div class='del'>-		amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-			sizeof(args));</div><div class='add'>+		if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+		    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		*voltage = le16_to_cpu(args.v2.usVoltageLevel);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1221,8 +1246,9 @@ int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,</div><div class='ctx'> 		args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;</div><div class='ctx'> 		args.v3.usVoltageLevel = cpu_to_le16(voltage_id);</div><div class='ctx'> </div><div class='del'>-		amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context, index, (uint32_t *)&amp;args,</div><div class='del'>-			sizeof(args));</div><div class='add'>+		if (amdgpu_atom_execute_table(adev-&gt;mode_info.atom_context,</div><div class='add'>+		    index, (uint32_t *)&amp;args, sizeof(args)))</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		*voltage = le16_to_cpu(args.v3.usVoltageLevel);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1484,6 +1510,8 @@ int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,</div><div class='ctx'> 										(u32)le32_to_cpu(*((u32 *)reg_data + j));</div><div class='ctx'> 									j++;</div><div class='ctx'> 								} else if ((reg_table-&gt;mc_reg_address[i].pre_reg_data &amp; LOW_NIBBLE_MASK) == DATA_EQU_PREV) {</div><div class='add'>+									if (i == 0)</div><div class='add'>+										continue;</div><div class='ctx'> 									reg_table-&gt;mc_reg_table_entry[num_ranges].mc_data[i] =</div><div class='ctx'> 										reg_table-&gt;mc_reg_table_entry[num_ranges].mc_data[i - 1];</div><div class='ctx'> 								}</div><div class='hunk'>@@ -1787,16 +1815,43 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,</div><div class='ctx'> 	return sysfs_emit(buf, "%s\n", ctx-&gt;vbios_pn);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t amdgpu_atombios_get_vbios_build(struct device *dev,</div><div class='add'>+					       struct device_attribute *attr,</div><div class='add'>+					       char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	struct atom_context *ctx = adev-&gt;mode_info.atom_context;</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%s\n", ctx-&gt;build_num);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,</div><div class='ctx'> 		   NULL);</div><div class='add'>+static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL);</div><div class='ctx'> </div><div class='ctx'> static struct attribute *amdgpu_vbios_version_attrs[] = {</div><div class='del'>-	&amp;dev_attr_vbios_version.attr,</div><div class='del'>-	NULL</div><div class='add'>+	&amp;dev_attr_vbios_version.attr, &amp;dev_attr_vbios_build.attr, NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static umode_t amdgpu_vbios_version_attrs_is_visible(struct kobject *kobj,</div><div class='add'>+						     struct attribute *attr,</div><div class='add'>+						     int index)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = kobj_to_dev(kobj);</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	struct atom_context *ctx = adev-&gt;mode_info.atom_context;</div><div class='add'>+</div><div class='add'>+	if (attr == &amp;dev_attr_vbios_build.attr &amp;&amp; !strlen(ctx-&gt;build_num))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return attr-&gt;mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct attribute_group amdgpu_vbios_version_attr_group = {</div><div class='del'>-	.attrs = amdgpu_vbios_version_attrs</div><div class='add'>+	.attrs = amdgpu_vbios_version_attrs,</div><div class='add'>+	.is_visible = amdgpu_vbios_version_attrs_is_visible,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h<br/>index 0811474e8fd3..867bc5c5ce67 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h</a></div><div class='hunk'>@@ -136,6 +136,7 @@ amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,</div><div class='ctx'> struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,</div><div class='ctx'> 							  uint8_t id);</div><div class='ctx'> void amdgpu_atombios_i2c_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id);</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -163,8 +164,8 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,</div><div class='ctx'> 					    bool strobe_mode,</div><div class='ctx'> 					    struct atom_mpll_param *mpll_param);</div><div class='ctx'> </div><div class='del'>-void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,</div><div class='del'>-					     u32 eng_clock, u32 mem_clock);</div><div class='add'>+int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,</div><div class='add'>+					    u32 eng_clock, u32 mem_clock);</div><div class='ctx'> </div><div class='ctx'> bool</div><div class='ctx'> amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c<br/>index 6857c586ded7..636385c80f64 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c</a></div><div class='hunk'>@@ -34,6 +34,7 @@ union firmware_info {</div><div class='ctx'> 	struct atom_firmware_info_v3_2 v32;</div><div class='ctx'> 	struct atom_firmware_info_v3_3 v33;</div><div class='ctx'> 	struct atom_firmware_info_v3_4 v34;</div><div class='add'>+	struct atom_firmware_info_v3_5 v35;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -180,19 +181,22 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)</div><div class='ctx'> 	u8 frev, crev;</div><div class='ctx'> 	int usage_bytes = 0;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_atom_parse_data_header(ctx, index, NULL, &amp;frev, &amp;crev, &amp;data_offset)) {</div><div class='del'>-		if (frev == 2 &amp;&amp; crev == 1) {</div><div class='del'>-			fw_usage_v2_1 =</div><div class='del'>-				(struct vram_usagebyfirmware_v2_1 *)(ctx-&gt;bios + data_offset);</div><div class='del'>-			amdgpu_atomfirmware_allocate_fb_v2_1(adev,</div><div class='del'>-					fw_usage_v2_1,</div><div class='del'>-					&amp;usage_bytes);</div><div class='del'>-		} else if (frev &gt;= 2 &amp;&amp; crev &gt;= 2) {</div><div class='del'>-			fw_usage_v2_2 =</div><div class='del'>-				(struct vram_usagebyfirmware_v2_2 *)(ctx-&gt;bios + data_offset);</div><div class='del'>-			amdgpu_atomfirmware_allocate_fb_v2_2(adev,</div><div class='del'>-					fw_usage_v2_2,</div><div class='del'>-					&amp;usage_bytes);</div><div class='add'>+	/* Skip atomfirmware allocation for SRIOV VFs when dynamic crit regn is enabled */</div><div class='add'>+	if (!(amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;virt.is_dynamic_crit_regn_enabled)) {</div><div class='add'>+		if (amdgpu_atom_parse_data_header(ctx, index, NULL, &amp;frev, &amp;crev, &amp;data_offset)) {</div><div class='add'>+			if (frev == 2 &amp;&amp; crev == 1) {</div><div class='add'>+				fw_usage_v2_1 =</div><div class='add'>+					(struct vram_usagebyfirmware_v2_1 *)(ctx-&gt;bios + data_offset);</div><div class='add'>+				amdgpu_atomfirmware_allocate_fb_v2_1(adev,</div><div class='add'>+						fw_usage_v2_1,</div><div class='add'>+						&amp;usage_bytes);</div><div class='add'>+			} else if (frev &gt;= 2 &amp;&amp; crev &gt;= 2) {</div><div class='add'>+				fw_usage_v2_2 =</div><div class='add'>+					(struct vram_usagebyfirmware_v2_2 *)(ctx-&gt;bios + data_offset);</div><div class='add'>+				amdgpu_atomfirmware_allocate_fb_v2_2(adev,</div><div class='add'>+						fw_usage_v2_2,</div><div class='add'>+						&amp;usage_bytes);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -211,6 +215,7 @@ union igp_info {</div><div class='ctx'> 	struct atom_integrated_system_info_v1_11 v11;</div><div class='ctx'> 	struct atom_integrated_system_info_v1_12 v12;</div><div class='ctx'> 	struct atom_integrated_system_info_v2_1 v21;</div><div class='add'>+	struct atom_integrated_system_info_v2_3 v23;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union umc_info {</div><div class='hunk'>@@ -279,6 +284,9 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,</div><div class='ctx'> 		case ATOM_DGPU_VRAM_TYPE_GDDR6:</div><div class='ctx'> 			vram_type = AMDGPU_VRAM_TYPE_GDDR6;</div><div class='ctx'> 			break;</div><div class='add'>+		case ATOM_DGPU_VRAM_TYPE_HBM3E:</div><div class='add'>+			vram_type = AMDGPU_VRAM_TYPE_HBM3E;</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -288,7 +296,6 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,</div><div class='ctx'> 	return vram_type;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> int</div><div class='ctx'> amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,</div><div class='ctx'> 				  int *vram_width, int *vram_type,</div><div class='hunk'>@@ -299,6 +306,7 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,</div><div class='ctx'> 	u16 data_offset, size;</div><div class='ctx'> 	union igp_info *igp_info;</div><div class='ctx'> 	union vram_info *vram_info;</div><div class='add'>+	union umc_info *umc_info;</div><div class='ctx'> 	union vram_module *vram_module;</div><div class='ctx'> 	u8 frev, crev;</div><div class='ctx'> 	u8 mem_type;</div><div class='hunk'>@@ -310,10 +318,16 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,</div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='ctx'> 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,</div><div class='ctx'> 						    integratedsysteminfo);</div><div class='del'>-	else</div><div class='del'>-		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,</div><div class='del'>-						    vram_info);</div><div class='del'>-</div><div class='add'>+	else {</div><div class='add'>+		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+		case IP_VERSION(12, 0, 0):</div><div class='add'>+		case IP_VERSION(12, 0, 1):</div><div class='add'>+			index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> 	if (amdgpu_atom_parse_data_header(mode_info-&gt;atom_context,</div><div class='ctx'> 					  index, &amp;size,</div><div class='ctx'> 					  &amp;frev, &amp;crev, &amp;data_offset)) {</div><div class='hunk'>@@ -359,6 +373,20 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,</div><div class='ctx'> 					if (vram_type)</div><div class='ctx'> 						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='ctx'> 					break;</div><div class='add'>+				case 3:</div><div class='add'>+					mem_channel_number = igp_info-&gt;v23.umachannelnumber;</div><div class='add'>+					if (!mem_channel_number)</div><div class='add'>+						mem_channel_number = 1;</div><div class='add'>+					mem_type = igp_info-&gt;v23.memorytype;</div><div class='add'>+					if (mem_type == LpDdr5MemType)</div><div class='add'>+						mem_channel_width = 32;</div><div class='add'>+					else</div><div class='add'>+						mem_channel_width = 64;</div><div class='add'>+					if (vram_width)</div><div class='add'>+						*vram_width = mem_channel_number * mem_channel_width;</div><div class='add'>+					if (vram_type)</div><div class='add'>+						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+					break;</div><div class='ctx'> 				default:</div><div class='ctx'> 					return -EINVAL;</div><div class='ctx'> 				}</div><div class='hunk'>@@ -367,123 +395,150 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			vram_info = (union vram_info *)</div><div class='del'>-				(mode_info-&gt;atom_context-&gt;bios + data_offset);</div><div class='del'>-			module_id = (RREG32(adev-&gt;bios_scratch_reg_offset + 4) &amp; 0x00ff0000) &gt;&gt; 16;</div><div class='del'>-			if (frev == 3) {</div><div class='del'>-				switch (crev) {</div><div class='del'>-				/* v30 */</div><div class='del'>-				case 0:</div><div class='del'>-					vram_module = (union vram_module *)vram_info-&gt;v30.vram_module;</div><div class='del'>-					mem_vendor = (vram_module-&gt;v30.dram_vendor_id) &amp; 0xF;</div><div class='del'>-					if (vram_vendor)</div><div class='del'>-						*vram_vendor = mem_vendor;</div><div class='del'>-					mem_type = vram_info-&gt;v30.memory_type;</div><div class='del'>-					if (vram_type)</div><div class='del'>-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='del'>-					mem_channel_number = vram_info-&gt;v30.channel_num;</div><div class='del'>-					mem_channel_width = vram_info-&gt;v30.channel_width;</div><div class='del'>-					if (vram_width)</div><div class='del'>-						*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='del'>-					break;</div><div class='del'>-				default:</div><div class='del'>-					return -EINVAL;</div><div class='del'>-				}</div><div class='del'>-			} else if (frev == 2) {</div><div class='del'>-				switch (crev) {</div><div class='del'>-				/* v23 */</div><div class='del'>-				case 3:</div><div class='del'>-					if (module_id &gt; vram_info-&gt;v23.vram_module_num)</div><div class='del'>-						module_id = 0;</div><div class='del'>-					vram_module = (union vram_module *)vram_info-&gt;v23.vram_module;</div><div class='del'>-					while (i &lt; module_id) {</div><div class='del'>-						vram_module = (union vram_module *)</div><div class='del'>-							((u8 *)vram_module + vram_module-&gt;v9.vram_module_size);</div><div class='del'>-						i++;</div><div class='del'>-					}</div><div class='del'>-					mem_type = vram_module-&gt;v9.memory_type;</div><div class='del'>-					if (vram_type)</div><div class='del'>-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='del'>-					mem_channel_number = vram_module-&gt;v9.channel_num;</div><div class='del'>-					mem_channel_width = vram_module-&gt;v9.channel_width;</div><div class='del'>-					if (vram_width)</div><div class='del'>-						*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='del'>-					mem_vendor = (vram_module-&gt;v9.vender_rev_id) &amp; 0xF;</div><div class='del'>-					if (vram_vendor)</div><div class='del'>-						*vram_vendor = mem_vendor;</div><div class='del'>-					break;</div><div class='del'>-				/* v24 */</div><div class='del'>-				case 4:</div><div class='del'>-					if (module_id &gt; vram_info-&gt;v24.vram_module_num)</div><div class='del'>-						module_id = 0;</div><div class='del'>-					vram_module = (union vram_module *)vram_info-&gt;v24.vram_module;</div><div class='del'>-					while (i &lt; module_id) {</div><div class='del'>-						vram_module = (union vram_module *)</div><div class='del'>-							((u8 *)vram_module + vram_module-&gt;v10.vram_module_size);</div><div class='del'>-						i++;</div><div class='add'>+			switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+			case IP_VERSION(12, 0, 0):</div><div class='add'>+			case IP_VERSION(12, 0, 1):</div><div class='add'>+				umc_info = (union umc_info *)(mode_info-&gt;atom_context-&gt;bios + data_offset);</div><div class='add'>+</div><div class='add'>+				if (frev == 4) {</div><div class='add'>+					switch (crev) {</div><div class='add'>+					case 0:</div><div class='add'>+						mem_channel_number = le32_to_cpu(umc_info-&gt;v40.channel_num);</div><div class='add'>+						mem_type = le32_to_cpu(umc_info-&gt;v40.vram_type);</div><div class='add'>+						mem_channel_width = le32_to_cpu(umc_info-&gt;v40.channel_width);</div><div class='add'>+						mem_vendor = RREG32(adev-&gt;bios_scratch_reg_offset + 4) &amp; 0xF;</div><div class='add'>+						if (vram_vendor)</div><div class='add'>+							*vram_vendor = mem_vendor;</div><div class='add'>+						if (vram_type)</div><div class='add'>+							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+						if (vram_width)</div><div class='add'>+							*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='add'>+						break;</div><div class='add'>+					default:</div><div class='add'>+						return -EINVAL;</div><div class='ctx'> 					}</div><div class='del'>-					mem_type = vram_module-&gt;v10.memory_type;</div><div class='del'>-					if (vram_type)</div><div class='del'>-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='del'>-					mem_channel_number = vram_module-&gt;v10.channel_num;</div><div class='del'>-					mem_channel_width = vram_module-&gt;v10.channel_width;</div><div class='del'>-					if (vram_width)</div><div class='del'>-						*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='del'>-					mem_vendor = (vram_module-&gt;v10.vender_rev_id) &amp; 0xF;</div><div class='del'>-					if (vram_vendor)</div><div class='del'>-						*vram_vendor = mem_vendor;</div><div class='del'>-					break;</div><div class='del'>-				/* v25 */</div><div class='del'>-				case 5:</div><div class='del'>-					if (module_id &gt; vram_info-&gt;v25.vram_module_num)</div><div class='del'>-						module_id = 0;</div><div class='del'>-					vram_module = (union vram_module *)vram_info-&gt;v25.vram_module;</div><div class='del'>-					while (i &lt; module_id) {</div><div class='del'>-						vram_module = (union vram_module *)</div><div class='del'>-							((u8 *)vram_module + vram_module-&gt;v11.vram_module_size);</div><div class='del'>-						i++;</div><div class='add'>+				} else</div><div class='add'>+					return -EINVAL;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				vram_info = (union vram_info *)</div><div class='add'>+					(mode_info-&gt;atom_context-&gt;bios + data_offset);</div><div class='add'>+</div><div class='add'>+				module_id = (RREG32(adev-&gt;bios_scratch_reg_offset + 4) &amp; 0x00ff0000) &gt;&gt; 16;</div><div class='add'>+				if (frev == 3) {</div><div class='add'>+					switch (crev) {</div><div class='add'>+					/* v30 */</div><div class='add'>+					case 0:</div><div class='add'>+						vram_module = (union vram_module *)vram_info-&gt;v30.vram_module;</div><div class='add'>+						mem_vendor = (vram_module-&gt;v30.dram_vendor_id) &amp; 0xF;</div><div class='add'>+						if (vram_vendor)</div><div class='add'>+							*vram_vendor = mem_vendor;</div><div class='add'>+						mem_type = vram_info-&gt;v30.memory_type;</div><div class='add'>+						if (vram_type)</div><div class='add'>+							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+						mem_channel_number = vram_info-&gt;v30.channel_num;</div><div class='add'>+						mem_channel_width = vram_info-&gt;v30.channel_width;</div><div class='add'>+						if (vram_width)</div><div class='add'>+							*vram_width = mem_channel_number * 16;</div><div class='add'>+						break;</div><div class='add'>+					default:</div><div class='add'>+						return -EINVAL;</div><div class='ctx'> 					}</div><div class='del'>-					mem_type = vram_module-&gt;v11.memory_type;</div><div class='del'>-					if (vram_type)</div><div class='del'>-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='del'>-					mem_channel_number = vram_module-&gt;v11.channel_num;</div><div class='del'>-					mem_channel_width = vram_module-&gt;v11.channel_width;</div><div class='del'>-					if (vram_width)</div><div class='del'>-						*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='del'>-					mem_vendor = (vram_module-&gt;v11.vender_rev_id) &amp; 0xF;</div><div class='del'>-					if (vram_vendor)</div><div class='del'>-						*vram_vendor = mem_vendor;</div><div class='del'>-					break;</div><div class='del'>-				/* v26 */</div><div class='del'>-				case 6:</div><div class='del'>-					if (module_id &gt; vram_info-&gt;v26.vram_module_num)</div><div class='del'>-						module_id = 0;</div><div class='del'>-					vram_module = (union vram_module *)vram_info-&gt;v26.vram_module;</div><div class='del'>-					while (i &lt; module_id) {</div><div class='del'>-						vram_module = (union vram_module *)</div><div class='del'>-							((u8 *)vram_module + vram_module-&gt;v9.vram_module_size);</div><div class='del'>-						i++;</div><div class='add'>+				} else if (frev == 2) {</div><div class='add'>+					switch (crev) {</div><div class='add'>+					/* v23 */</div><div class='add'>+					case 3:</div><div class='add'>+						if (module_id &gt; vram_info-&gt;v23.vram_module_num)</div><div class='add'>+							module_id = 0;</div><div class='add'>+						vram_module = (union vram_module *)vram_info-&gt;v23.vram_module;</div><div class='add'>+						while (i &lt; module_id) {</div><div class='add'>+							vram_module = (union vram_module *)</div><div class='add'>+								((u8 *)vram_module + vram_module-&gt;v9.vram_module_size);</div><div class='add'>+							i++;</div><div class='add'>+						}</div><div class='add'>+						mem_type = vram_module-&gt;v9.memory_type;</div><div class='add'>+						if (vram_type)</div><div class='add'>+							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+						mem_channel_number = vram_module-&gt;v9.channel_num;</div><div class='add'>+						mem_channel_width = vram_module-&gt;v9.channel_width;</div><div class='add'>+						if (vram_width)</div><div class='add'>+							*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='add'>+						mem_vendor = (vram_module-&gt;v9.vender_rev_id) &amp; 0xF;</div><div class='add'>+						if (vram_vendor)</div><div class='add'>+							*vram_vendor = mem_vendor;</div><div class='add'>+						break;</div><div class='add'>+					/* v24 */</div><div class='add'>+					case 4:</div><div class='add'>+						if (module_id &gt; vram_info-&gt;v24.vram_module_num)</div><div class='add'>+							module_id = 0;</div><div class='add'>+						vram_module = (union vram_module *)vram_info-&gt;v24.vram_module;</div><div class='add'>+						while (i &lt; module_id) {</div><div class='add'>+							vram_module = (union vram_module *)</div><div class='add'>+								((u8 *)vram_module + vram_module-&gt;v10.vram_module_size);</div><div class='add'>+							i++;</div><div class='add'>+						}</div><div class='add'>+						mem_type = vram_module-&gt;v10.memory_type;</div><div class='add'>+						if (vram_type)</div><div class='add'>+							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+						mem_channel_number = vram_module-&gt;v10.channel_num;</div><div class='add'>+						mem_channel_width = vram_module-&gt;v10.channel_width;</div><div class='add'>+						if (vram_width)</div><div class='add'>+							*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='add'>+						mem_vendor = (vram_module-&gt;v10.vender_rev_id) &amp; 0xF;</div><div class='add'>+						if (vram_vendor)</div><div class='add'>+							*vram_vendor = mem_vendor;</div><div class='add'>+						break;</div><div class='add'>+					/* v25 */</div><div class='add'>+					case 5:</div><div class='add'>+						if (module_id &gt; vram_info-&gt;v25.vram_module_num)</div><div class='add'>+							module_id = 0;</div><div class='add'>+						vram_module = (union vram_module *)vram_info-&gt;v25.vram_module;</div><div class='add'>+						while (i &lt; module_id) {</div><div class='add'>+							vram_module = (union vram_module *)</div><div class='add'>+								((u8 *)vram_module + vram_module-&gt;v11.vram_module_size);</div><div class='add'>+							i++;</div><div class='add'>+						}</div><div class='add'>+						mem_type = vram_module-&gt;v11.memory_type;</div><div class='add'>+						if (vram_type)</div><div class='add'>+							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+						mem_channel_number = vram_module-&gt;v11.channel_num;</div><div class='add'>+						mem_channel_width = vram_module-&gt;v11.channel_width;</div><div class='add'>+						if (vram_width)</div><div class='add'>+							*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='add'>+						mem_vendor = (vram_module-&gt;v11.vender_rev_id) &amp; 0xF;</div><div class='add'>+						if (vram_vendor)</div><div class='add'>+							*vram_vendor = mem_vendor;</div><div class='add'>+						break;</div><div class='add'>+					/* v26 */</div><div class='add'>+					case 6:</div><div class='add'>+						if (module_id &gt; vram_info-&gt;v26.vram_module_num)</div><div class='add'>+							module_id = 0;</div><div class='add'>+						vram_module = (union vram_module *)vram_info-&gt;v26.vram_module;</div><div class='add'>+						while (i &lt; module_id) {</div><div class='add'>+							vram_module = (union vram_module *)</div><div class='add'>+								((u8 *)vram_module + vram_module-&gt;v9.vram_module_size);</div><div class='add'>+							i++;</div><div class='add'>+						}</div><div class='add'>+						mem_type = vram_module-&gt;v9.memory_type;</div><div class='add'>+						if (vram_type)</div><div class='add'>+							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='add'>+						mem_channel_number = vram_module-&gt;v9.channel_num;</div><div class='add'>+						mem_channel_width = vram_module-&gt;v9.channel_width;</div><div class='add'>+						if (vram_width)</div><div class='add'>+							*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='add'>+						mem_vendor = (vram_module-&gt;v9.vender_rev_id) &amp; 0xF;</div><div class='add'>+						if (vram_vendor)</div><div class='add'>+							*vram_vendor = mem_vendor;</div><div class='add'>+						break;</div><div class='add'>+					default:</div><div class='add'>+						return -EINVAL;</div><div class='ctx'> 					}</div><div class='del'>-					mem_type = vram_module-&gt;v9.memory_type;</div><div class='del'>-					if (vram_type)</div><div class='del'>-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);</div><div class='del'>-					mem_channel_number = vram_module-&gt;v9.channel_num;</div><div class='del'>-					mem_channel_width = vram_module-&gt;v9.channel_width;</div><div class='del'>-					if (vram_width)</div><div class='del'>-						*vram_width = mem_channel_number * (1 &lt;&lt; mem_channel_width);</div><div class='del'>-					mem_vendor = (vram_module-&gt;v9.vender_rev_id) &amp; 0xF;</div><div class='del'>-					if (vram_vendor)</div><div class='del'>-						*vram_vendor = mem_vendor;</div><div class='del'>-					break;</div><div class='del'>-				default:</div><div class='add'>+				} else {</div><div class='add'>+					/* invalid frev */</div><div class='ctx'> 					return -EINVAL;</div><div class='ctx'> 				}</div><div class='del'>-			} else {</div><div class='del'>-				/* invalid frev */</div><div class='del'>-				return -EINVAL;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -500,9 +555,10 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)</div><div class='ctx'> 	u16 data_offset, size;</div><div class='ctx'> 	union umc_info *umc_info;</div><div class='ctx'> 	u8 frev, crev;</div><div class='del'>-	bool ecc_default_enabled = false;</div><div class='add'>+	bool mem_ecc_enabled = false;</div><div class='ctx'> 	u8 umc_config;</div><div class='ctx'> 	u32 umc_config1;</div><div class='add'>+	adev-&gt;ras_default_ecc_enabled = false;</div><div class='ctx'> </div><div class='ctx'> 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,</div><div class='ctx'> 			umc_info);</div><div class='hunk'>@@ -514,20 +570,22 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)</div><div class='ctx'> 			switch (crev) {</div><div class='ctx'> 			case 1:</div><div class='ctx'> 				umc_config = le32_to_cpu(umc_info-&gt;v31.umc_config);</div><div class='del'>-				ecc_default_enabled =</div><div class='add'>+				mem_ecc_enabled =</div><div class='ctx'> 					(umc_config &amp; UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;</div><div class='ctx'> 				break;</div><div class='ctx'> 			case 2:</div><div class='ctx'> 				umc_config = le32_to_cpu(umc_info-&gt;v32.umc_config);</div><div class='del'>-				ecc_default_enabled =</div><div class='add'>+				mem_ecc_enabled =</div><div class='ctx'> 					(umc_config &amp; UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;</div><div class='ctx'> 				break;</div><div class='ctx'> 			case 3:</div><div class='ctx'> 				umc_config = le32_to_cpu(umc_info-&gt;v33.umc_config);</div><div class='ctx'> 				umc_config1 = le32_to_cpu(umc_info-&gt;v33.umc_config1);</div><div class='del'>-				ecc_default_enabled =</div><div class='add'>+				mem_ecc_enabled =</div><div class='ctx'> 					((umc_config &amp; UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||</div><div class='ctx'> 					 (umc_config1 &amp; UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;</div><div class='add'>+				adev-&gt;ras_default_ecc_enabled =</div><div class='add'>+					(umc_config &amp; UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				/* unsupported crev */</div><div class='hunk'>@@ -536,9 +594,12 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)</div><div class='ctx'> 		} else if (frev == 4) {</div><div class='ctx'> 			switch (crev) {</div><div class='ctx'> 			case 0:</div><div class='add'>+				umc_config = le32_to_cpu(umc_info-&gt;v40.umc_config);</div><div class='ctx'> 				umc_config1 = le32_to_cpu(umc_info-&gt;v40.umc_config1);</div><div class='del'>-				ecc_default_enabled =</div><div class='add'>+				mem_ecc_enabled =</div><div class='ctx'> 					(umc_config1 &amp; UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;</div><div class='add'>+				adev-&gt;ras_default_ecc_enabled =</div><div class='add'>+					(umc_config &amp; UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				/* unsupported crev */</div><div class='hunk'>@@ -550,7 +611,7 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return ecc_default_enabled;</div><div class='add'>+	return mem_ecc_enabled;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -872,6 +933,10 @@ int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)</div><div class='ctx'> 		fw_reserved_fb_size =</div><div class='ctx'> 			(firmware_info-&gt;v34.fw_reserved_size_in_kb &lt;&lt; 10);</div><div class='ctx'> 		break;</div><div class='add'>+	case 5:</div><div class='add'>+		fw_reserved_fb_size =</div><div class='add'>+			(firmware_info-&gt;v35.fw_reserved_size_in_kb &lt;&lt; 10);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		fw_reserved_fb_size = 0;</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c<br/>index 375f02002579..3893e6fc2f03 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c</a></div><div class='hunk'>@@ -89,18 +89,6 @@ bool amdgpu_is_atpx_hybrid(void)</div><div class='ctx'> 	return amdgpu_atpx_priv.atpx.is_hybrid;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool amdgpu_atpx_dgpu_req_power_for_displays(void)</div><div class='del'>-{</div><div class='del'>-	return amdgpu_atpx_priv.atpx.dgpu_req_power_for_displays;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#if defined(CONFIG_ACPI)</div><div class='del'>-void *amdgpu_atpx_get_dhandle(void)</div><div class='del'>-{</div><div class='del'>-	return amdgpu_atpx_priv.dhandle;</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_atpx_call - call an ATPX method</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c<br/>index edc6377ec5ff..199693369c7c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c</a></div><div class='hunk'>@@ -39,7 +39,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,</div><div class='ctx'> 	for (i = 0; i &lt; n; i++) {</div><div class='ctx'> 		struct amdgpu_ring *ring = adev-&gt;mman.buffer_funcs_ring;</div><div class='ctx'> 		r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &amp;fence,</div><div class='del'>-				       false, false, false);</div><div class='add'>+				       false, false, 0);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto exit_do_move;</div><div class='ctx'> 		r = dma_fence_wait(fence, false);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c<br/>index 618e469e3622..35d04e69aec0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c</a></div><div class='hunk'>@@ -47,52 +47,63 @@</div><div class='ctx'> /* Check if current bios is an ATOM BIOS.</div><div class='ctx'>  * Return true if it is ATOM BIOS. Otherwise, return false.</div><div class='ctx'>  */</div><div class='del'>-static bool check_atom_bios(uint8_t *bios, size_t size)</div><div class='add'>+static bool check_atom_bios(struct amdgpu_device *adev, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	uint16_t tmp, bios_header_start;</div><div class='add'>+	uint8_t *bios = adev-&gt;bios;</div><div class='ctx'> </div><div class='ctx'> 	if (!bios || size &lt; 0x49) {</div><div class='del'>-		DRM_INFO("vbios mem is null or mem size is wrong\n");</div><div class='add'>+		dev_dbg(adev-&gt;dev, "VBIOS mem is null or mem size is wrong\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!AMD_IS_VALID_VBIOS(bios)) {</div><div class='del'>-		DRM_INFO("BIOS signature incorrect %x %x\n", bios[0], bios[1]);</div><div class='add'>+		dev_dbg(adev-&gt;dev, "VBIOS signature incorrect %x %x\n", bios[0],</div><div class='add'>+			bios[1]);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	bios_header_start = bios[0x48] | (bios[0x49] &lt;&lt; 8);</div><div class='ctx'> 	if (!bios_header_start) {</div><div class='del'>-		DRM_INFO("Can't locate bios header\n");</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Can't locate VBIOS header\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	tmp = bios_header_start + 4;</div><div class='ctx'> 	if (size &lt; tmp) {</div><div class='del'>-		DRM_INFO("BIOS header is broken\n");</div><div class='add'>+		dev_dbg(adev-&gt;dev, "VBIOS header is broken\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!memcmp(bios + tmp, "ATOM", 4) ||</div><div class='ctx'> 	    !memcmp(bios + tmp, "MOTA", 4)) {</div><div class='del'>-		DRM_DEBUG("ATOMBIOS detected\n");</div><div class='add'>+		dev_dbg(adev-&gt;dev, "ATOMBIOS detected\n");</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_bios_release(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	kfree(adev-&gt;bios);</div><div class='add'>+	adev-&gt;bios = NULL;</div><div class='add'>+	adev-&gt;bios_size = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* If you boot an IGP board with a discrete card as the primary,</div><div class='ctx'>  * the IGP rom is not accessible via the rom bar as the IGP rom is</div><div class='ctx'>  * part of the system bios.  On boot, the system bios puts a</div><div class='ctx'>  * copy of the igp rom at the start of vram if a discrete card is</div><div class='ctx'>  * present.</div><div class='add'>+ * For SR-IOV, if dynamic critical region is not enabled,</div><div class='add'>+ * the vbios image is also put at the start of VRAM in the VF.</div><div class='ctx'>  */</div><div class='del'>-static bool igp_read_bios_from_vram(struct amdgpu_device *adev)</div><div class='add'>+static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	uint8_t __iomem *bios;</div><div class='add'>+	uint8_t __iomem *bios = NULL;</div><div class='ctx'> 	resource_size_t vram_base;</div><div class='del'>-	resource_size_t size = 256 * 1024; /* ??? */</div><div class='add'>+	u32 size = 256U * 1024U; /* ??? */</div><div class='ctx'> </div><div class='ctx'> 	if (!(adev-&gt;flags &amp; AMD_IS_APU))</div><div class='ctx'> 		if (amdgpu_device_need_post(adev))</div><div class='hunk'>@@ -104,21 +115,36 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;bios = NULL;</div><div class='ctx'> 	vram_base = pci_resource_start(adev-&gt;pdev, 0);</div><div class='del'>-	bios = ioremap_wc(vram_base, size);</div><div class='del'>-	if (!bios)</div><div class='del'>-		return false;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;bios = kmalloc(size, GFP_KERNEL);</div><div class='del'>-	if (!adev-&gt;bios) {</div><div class='del'>-		iounmap(bios);</div><div class='add'>+	if (!adev-&gt;bios)</div><div class='ctx'> 		return false;</div><div class='add'>+</div><div class='add'>+	/* For SRIOV with dynamic critical region is enabled,</div><div class='add'>+	 * the vbios image is put at a dynamic offset of VRAM in the VF.</div><div class='add'>+	 * If dynamic critical region is disabled, follow the existing logic as on baremetal.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;virt.is_dynamic_crit_regn_enabled) {</div><div class='add'>+		if (amdgpu_virt_get_dynamic_data_info(adev,</div><div class='add'>+				AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, adev-&gt;bios, &amp;size)) {</div><div class='add'>+			amdgpu_bios_release(adev);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		bios = ioremap_wc(vram_base, size);</div><div class='add'>+		if (!bios) {</div><div class='add'>+			amdgpu_bios_release(adev);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		memcpy_fromio(adev-&gt;bios, bios, size);</div><div class='add'>+		iounmap(bios);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;bios_size = size;</div><div class='del'>-	memcpy_fromio(adev-&gt;bios, bios, size);</div><div class='del'>-	iounmap(bios);</div><div class='ctx'> </div><div class='del'>-	if (!check_atom_bios(adev-&gt;bios, size)) {</div><div class='del'>-		kfree(adev-&gt;bios);</div><div class='add'>+	if (!check_atom_bios(adev, size)) {</div><div class='add'>+		amdgpu_bios_release(adev);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -145,8 +171,8 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)</div><div class='ctx'> 	memcpy_fromio(adev-&gt;bios, bios, size);</div><div class='ctx'> 	pci_unmap_rom(adev-&gt;pdev, bios);</div><div class='ctx'> </div><div class='del'>-	if (!check_atom_bios(adev-&gt;bios, size)) {</div><div class='del'>-		kfree(adev-&gt;bios);</div><div class='add'>+	if (!check_atom_bios(adev, size)) {</div><div class='add'>+		amdgpu_bios_release(adev);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -185,8 +211,8 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)</div><div class='ctx'> 	/* read complete BIOS */</div><div class='ctx'> 	amdgpu_asic_read_bios_from_rom(adev, adev-&gt;bios, len);</div><div class='ctx'> </div><div class='del'>-	if (!check_atom_bios(adev-&gt;bios, len)) {</div><div class='del'>-		kfree(adev-&gt;bios);</div><div class='add'>+	if (!check_atom_bios(adev, len)) {</div><div class='add'>+		amdgpu_bios_release(adev);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -215,14 +241,15 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)</div><div class='ctx'> 	memcpy_fromio(adev-&gt;bios, bios, romlen);</div><div class='ctx'> 	iounmap(bios);</div><div class='ctx'> </div><div class='del'>-	if (!check_atom_bios(adev-&gt;bios, romlen))</div><div class='add'>+	if (!check_atom_bios(adev, romlen))</div><div class='ctx'> 		goto free_bios;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;bios_size = romlen;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> free_bios:</div><div class='del'>-	kfree(adev-&gt;bios);</div><div class='add'>+	amdgpu_bios_release(adev);</div><div class='add'>+</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -284,10 +311,6 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)</div><div class='ctx'> 	acpi_status status;</div><div class='ctx'> 	bool found = false;</div><div class='ctx'> </div><div class='del'>-	/* ATRM is for the discrete card only */</div><div class='del'>-	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='ctx'> 	/* ATRM is for on-platform devices only */</div><div class='ctx'> 	if (dev_is_removable(&amp;adev-&gt;pdev-&gt;dev))</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -327,8 +350,8 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!check_atom_bios(adev-&gt;bios, size)) {</div><div class='del'>-		kfree(adev-&gt;bios);</div><div class='add'>+	if (!check_atom_bios(adev, size)) {</div><div class='add'>+		amdgpu_bios_release(adev);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> 	adev-&gt;bios_size = size;</div><div class='hunk'>@@ -343,11 +366,8 @@ static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='del'>-		return igp_read_bios_from_vram(adev);</div><div class='del'>-	else</div><div class='del'>-		return (!adev-&gt;asic_funcs || !adev-&gt;asic_funcs-&gt;read_disabled_bios) ?</div><div class='del'>-			false : amdgpu_asic_read_disabled_bios(adev);</div><div class='add'>+	return (!adev-&gt;asic_funcs || !adev-&gt;asic_funcs-&gt;read_disabled_bios) ?</div><div class='add'>+		false : amdgpu_asic_read_disabled_bios(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_ACPI</div><div class='hunk'>@@ -395,8 +415,8 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)</div><div class='ctx'> 					     vhdr-&gt;ImageLength,</div><div class='ctx'> 					     GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-			if (!check_atom_bios(adev-&gt;bios, vhdr-&gt;ImageLength)) {</div><div class='del'>-				kfree(adev-&gt;bios);</div><div class='add'>+			if (!check_atom_bios(adev, vhdr-&gt;ImageLength)) {</div><div class='add'>+				amdgpu_bios_release(adev);</div><div class='ctx'> 				return false;</div><div class='ctx'> 			}</div><div class='ctx'> 			adev-&gt;bios_size = vhdr-&gt;ImageLength;</div><div class='hunk'>@@ -414,7 +434,43 @@ static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-bool amdgpu_get_bios(struct amdgpu_device *adev)</div><div class='add'>+static bool amdgpu_get_bios_apu(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_acpi_vfct_bios(adev)) {</div><div class='add'>+		dev_info(adev-&gt;dev, "Fetched VBIOS from VFCT\n");</div><div class='add'>+		goto success;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_read_bios_from_vram(adev)) {</div><div class='add'>+		dev_info(adev-&gt;dev, "Fetched VBIOS from VRAM BAR\n");</div><div class='add'>+		goto success;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_read_bios(adev)) {</div><div class='add'>+		dev_info(adev-&gt;dev, "Fetched VBIOS from ROM BAR\n");</div><div class='add'>+		goto success;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_read_platform_bios(adev)) {</div><div class='add'>+		dev_info(adev-&gt;dev, "Fetched VBIOS from platform\n");</div><div class='add'>+		goto success;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_err(adev-&gt;dev, "Unable to locate a BIOS ROM\n");</div><div class='add'>+	return false;</div><div class='add'>+</div><div class='add'>+success:</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_prefer_rom_resource(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct resource *res = &amp;adev-&gt;pdev-&gt;resource[PCI_ROM_RESOURCE];</div><div class='add'>+</div><div class='add'>+	return (res-&gt;flags &amp; IORESOURCE_ROM_SHADOW);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_atrm_get_bios(adev)) {</div><div class='ctx'> 		dev_info(adev-&gt;dev, "Fetched VBIOS from ATRM\n");</div><div class='hunk'>@@ -426,14 +482,33 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)</div><div class='ctx'> 		goto success;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (igp_read_bios_from_vram(adev)) {</div><div class='add'>+	/* this is required for SR-IOV */</div><div class='add'>+	if (amdgpu_read_bios_from_vram(adev)) {</div><div class='ctx'> 		dev_info(adev-&gt;dev, "Fetched VBIOS from VRAM BAR\n");</div><div class='ctx'> 		goto success;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_read_bios(adev)) {</div><div class='del'>-		dev_info(adev-&gt;dev, "Fetched VBIOS from ROM BAR\n");</div><div class='del'>-		goto success;</div><div class='add'>+	if (amdgpu_prefer_rom_resource(adev)) {</div><div class='add'>+		if (amdgpu_read_bios(adev)) {</div><div class='add'>+			dev_info(adev-&gt;dev, "Fetched VBIOS from ROM BAR\n");</div><div class='add'>+			goto success;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_read_platform_bios(adev)) {</div><div class='add'>+			dev_info(adev-&gt;dev, "Fetched VBIOS from platform\n");</div><div class='add'>+			goto success;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		if (amdgpu_read_platform_bios(adev)) {</div><div class='add'>+			dev_info(adev-&gt;dev, "Fetched VBIOS from platform\n");</div><div class='add'>+			goto success;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_read_bios(adev)) {</div><div class='add'>+			dev_info(adev-&gt;dev, "Fetched VBIOS from ROM BAR\n");</div><div class='add'>+			goto success;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_read_bios_from_rom(adev)) {</div><div class='hunk'>@@ -446,19 +521,28 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)</div><div class='ctx'> 		goto success;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_read_platform_bios(adev)) {</div><div class='del'>-		dev_info(adev-&gt;dev, "Fetched VBIOS from platform\n");</div><div class='del'>-		goto success;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	dev_err(adev-&gt;dev, "Unable to locate a BIOS ROM\n");</div><div class='ctx'> 	return false;</div><div class='ctx'> </div><div class='ctx'> success:</div><div class='del'>-	adev-&gt;is_atom_fw = adev-&gt;asic_type &gt;= CHIP_VEGA10;</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool amdgpu_get_bios(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	bool found;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+		found = amdgpu_get_bios_apu(adev);</div><div class='add'>+	else</div><div class='add'>+		found = amdgpu_get_bios_dgpu(adev);</div><div class='add'>+</div><div class='add'>+	if (found)</div><div class='add'>+		adev-&gt;is_atom_fw = adev-&gt;asic_type &gt;= CHIP_VEGA10;</div><div class='add'>+</div><div class='add'>+	return found;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* helper function for soc15 and onwards to read bios from rom */</div><div class='ctx'> bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,</div><div class='ctx'> 				     u8 *bios, u32 length_bytes)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c<br/>index 702f6610d024..66fb37b64388 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c</a></div><div class='hunk'>@@ -184,43 +184,36 @@ void amdgpu_bo_list_put(struct amdgpu_bo_list *list)</div><div class='ctx'> int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in,</div><div class='ctx'> 				      struct drm_amdgpu_bo_list_entry **info_param)</div><div class='ctx'> {</div><div class='del'>-	const void __user *uptr = u64_to_user_ptr(in-&gt;bo_info_ptr);</div><div class='ctx'> 	const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);</div><div class='add'>+	const void __user *uptr = u64_to_user_ptr(in-&gt;bo_info_ptr);</div><div class='add'>+	const uint32_t bo_info_size = in-&gt;bo_info_size;</div><div class='add'>+	const uint32_t bo_number = in-&gt;bo_number;</div><div class='ctx'> 	struct drm_amdgpu_bo_list_entry *info;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	info = kvmalloc_array(in-&gt;bo_number, info_size, GFP_KERNEL);</div><div class='del'>-	if (!info)</div><div class='del'>-		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	/* copy the handle array from userspace to a kernel buffer */</div><div class='del'>-	r = -EFAULT;</div><div class='del'>-	if (likely(info_size == in-&gt;bo_info_size)) {</div><div class='del'>-		unsigned long bytes = in-&gt;bo_number *</div><div class='del'>-			in-&gt;bo_info_size;</div><div class='del'>-</div><div class='del'>-		if (copy_from_user(info, uptr, bytes))</div><div class='del'>-			goto error_free;</div><div class='del'>-</div><div class='add'>+	if (likely(info_size == bo_info_size)) {</div><div class='add'>+		info = vmemdup_array_user(uptr, bo_number, info_size);</div><div class='add'>+		if (IS_ERR(info))</div><div class='add'>+			return PTR_ERR(info);</div><div class='ctx'> 	} else {</div><div class='del'>-		unsigned long bytes = min(in-&gt;bo_info_size, info_size);</div><div class='add'>+		const uint32_t bytes = min(bo_info_size, info_size);</div><div class='ctx'> 		unsigned i;</div><div class='ctx'> </div><div class='del'>-		memset(info, 0, in-&gt;bo_number * info_size);</div><div class='del'>-		for (i = 0; i &lt; in-&gt;bo_number; ++i) {</div><div class='del'>-			if (copy_from_user(&amp;info[i], uptr, bytes))</div><div class='del'>-				goto error_free;</div><div class='add'>+		info = kvmalloc_array(bo_number, info_size, GFP_KERNEL);</div><div class='add'>+		if (!info)</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-			uptr += in-&gt;bo_info_size;</div><div class='add'>+		memset(info, 0, bo_number * info_size);</div><div class='add'>+		for (i = 0; i &lt; bo_number; ++i, uptr += bo_info_size) {</div><div class='add'>+			if (copy_from_user(&amp;info[i], uptr, bytes)) {</div><div class='add'>+				kvfree(info);</div><div class='add'>+				return -EFAULT;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	*info_param = info;</div><div class='ctx'> 	return 0;</div><div class='del'>-</div><div class='del'>-error_free:</div><div class='del'>-	kvfree(info);</div><div class='del'>-	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h<br/>index 555cd6d877c3..2b5e7c46a39d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h</a></div><div class='hunk'>@@ -38,8 +38,7 @@ struct amdgpu_bo_list_entry {</div><div class='ctx'> 	struct amdgpu_bo		*bo;</div><div class='ctx'> 	struct amdgpu_bo_va		*bo_va;</div><div class='ctx'> 	uint32_t			priority;</div><div class='del'>-	struct page			**user_pages;</div><div class='del'>-	struct hmm_range		*range;</div><div class='add'>+	struct amdgpu_hmm_range		*range;</div><div class='ctx'> 	bool				user_invalidated;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c<br/>index b8280be6225d..004a6a9d6b9f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c</a></div><div class='hunk'>@@ -213,6 +213,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,</div><div class='ctx'> 		struct amdgpu_firmware_info *ucode;</div><div class='ctx'> </div><div class='ctx'> 		id = fw_type_convert(cgs_device, type);</div><div class='add'>+		if (id &gt;= AMDGPU_UCODE_ID_MAXIMUM)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 		ucode = &amp;adev-&gt;firmware.ucode[id];</div><div class='ctx'> 		if (ucode-&gt;fw == NULL)</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -249,83 +252,22 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,</div><div class='ctx'> </div><div class='ctx'> 		if (!adev-&gt;pm.fw) {</div><div class='ctx'> 			switch (adev-&gt;asic_type) {</div><div class='del'>-			case CHIP_TAHITI:</div><div class='del'>-				strcpy(fw_name, "radeon/tahiti_smc.bin");</div><div class='del'>-				break;</div><div class='del'>-			case CHIP_PITCAIRN:</div><div class='del'>-				if ((adev-&gt;pdev-&gt;revision == 0x81) &amp;&amp;</div><div class='del'>-				    ((adev-&gt;pdev-&gt;device == 0x6810) ||</div><div class='del'>-				    (adev-&gt;pdev-&gt;device == 0x6811))) {</div><div class='del'>-					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "radeon/pitcairn_k_smc.bin");</div><div class='del'>-				} else {</div><div class='del'>-					strcpy(fw_name, "radeon/pitcairn_smc.bin");</div><div class='del'>-				}</div><div class='del'>-				break;</div><div class='del'>-			case CHIP_VERDE:</div><div class='del'>-				if (((adev-&gt;pdev-&gt;device == 0x6820) &amp;&amp;</div><div class='del'>-					((adev-&gt;pdev-&gt;revision == 0x81) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;revision == 0x83))) ||</div><div class='del'>-				    ((adev-&gt;pdev-&gt;device == 0x6821) &amp;&amp;</div><div class='del'>-					((adev-&gt;pdev-&gt;revision == 0x83) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;revision == 0x87))) ||</div><div class='del'>-				    ((adev-&gt;pdev-&gt;revision == 0x87) &amp;&amp;</div><div class='del'>-					((adev-&gt;pdev-&gt;device == 0x6823) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x682b)))) {</div><div class='del'>-					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "radeon/verde_k_smc.bin");</div><div class='del'>-				} else {</div><div class='del'>-					strcpy(fw_name, "radeon/verde_smc.bin");</div><div class='del'>-				}</div><div class='del'>-				break;</div><div class='del'>-			case CHIP_OLAND:</div><div class='del'>-				if (((adev-&gt;pdev-&gt;revision == 0x81) &amp;&amp;</div><div class='del'>-					((adev-&gt;pdev-&gt;device == 0x6600) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6604) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6605) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6610))) ||</div><div class='del'>-				    ((adev-&gt;pdev-&gt;revision == 0x83) &amp;&amp;</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6610))) {</div><div class='del'>-					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "radeon/oland_k_smc.bin");</div><div class='del'>-				} else {</div><div class='del'>-					strcpy(fw_name, "radeon/oland_smc.bin");</div><div class='del'>-				}</div><div class='del'>-				break;</div><div class='del'>-			case CHIP_HAINAN:</div><div class='del'>-				if (((adev-&gt;pdev-&gt;revision == 0x81) &amp;&amp;</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6660)) ||</div><div class='del'>-				    ((adev-&gt;pdev-&gt;revision == 0x83) &amp;&amp;</div><div class='del'>-					((adev-&gt;pdev-&gt;device == 0x6660) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6663) ||</div><div class='del'>-					(adev-&gt;pdev-&gt;device == 0x6665) ||</div><div class='del'>-					 (adev-&gt;pdev-&gt;device == 0x6667)))) {</div><div class='del'>-					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "radeon/hainan_k_smc.bin");</div><div class='del'>-				} else if ((adev-&gt;pdev-&gt;revision == 0xc3) &amp;&amp;</div><div class='del'>-					 (adev-&gt;pdev-&gt;device == 0x6665)) {</div><div class='del'>-					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "radeon/banks_k_2_smc.bin");</div><div class='del'>-				} else {</div><div class='del'>-					strcpy(fw_name, "radeon/hainan_smc.bin");</div><div class='del'>-				}</div><div class='del'>-				break;</div><div class='ctx'> 			case CHIP_BONAIRE:</div><div class='ctx'> 				if ((adev-&gt;pdev-&gt;revision == 0x80) ||</div><div class='ctx'> 					(adev-&gt;pdev-&gt;revision == 0x81) ||</div><div class='ctx'> 					(adev-&gt;pdev-&gt;device == 0x665f)) {</div><div class='ctx'> 					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/bonaire_k_smc.bin");</div><div class='ctx'> 				} else {</div><div class='del'>-					strcpy(fw_name, "amdgpu/bonaire_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/bonaire_smc.bin");</div><div class='ctx'> 				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_HAWAII:</div><div class='ctx'> 				if (adev-&gt;pdev-&gt;revision == 0x80) {</div><div class='ctx'> 					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/hawaii_k_smc.bin");</div><div class='ctx'> 				} else {</div><div class='del'>-					strcpy(fw_name, "amdgpu/hawaii_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/hawaii_smc.bin");</div><div class='ctx'> 				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_TOPAZ:</div><div class='hunk'>@@ -335,83 +277,85 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,</div><div class='ctx'> 				    ((adev-&gt;pdev-&gt;device == 0x6900) &amp;&amp; (adev-&gt;pdev-&gt;revision == 0xD1)) ||</div><div class='ctx'> 				    ((adev-&gt;pdev-&gt;device == 0x6900) &amp;&amp; (adev-&gt;pdev-&gt;revision == 0xD3))) {</div><div class='ctx'> 					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "amdgpu/topaz_k_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/topaz_k_smc.bin");</div><div class='ctx'> 				} else</div><div class='del'>-					strcpy(fw_name, "amdgpu/topaz_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/topaz_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_TONGA:</div><div class='ctx'> 				if (((adev-&gt;pdev-&gt;device == 0x6939) &amp;&amp; (adev-&gt;pdev-&gt;revision == 0xf1)) ||</div><div class='ctx'> 				    ((adev-&gt;pdev-&gt;device == 0x6938) &amp;&amp; (adev-&gt;pdev-&gt;revision == 0xf1))) {</div><div class='ctx'> 					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "amdgpu/tonga_k_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/tonga_k_smc.bin");</div><div class='ctx'> 				} else</div><div class='del'>-					strcpy(fw_name, "amdgpu/tonga_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/tonga_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_FIJI:</div><div class='del'>-				strcpy(fw_name, "amdgpu/fiji_smc.bin");</div><div class='add'>+				strscpy(fw_name, "amdgpu/fiji_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_POLARIS11:</div><div class='ctx'> 				if (type == CGS_UCODE_ID_SMU) {</div><div class='ctx'> 					if (ASICID_IS_P21(adev-&gt;pdev-&gt;device, adev-&gt;pdev-&gt;revision)) {</div><div class='ctx'> 						info-&gt;is_kicker = true;</div><div class='del'>-						strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");</div><div class='add'>+						strscpy(fw_name, "amdgpu/polaris11_k_smc.bin");</div><div class='ctx'> 					} else if (ASICID_IS_P31(adev-&gt;pdev-&gt;device, adev-&gt;pdev-&gt;revision)) {</div><div class='ctx'> 						info-&gt;is_kicker = true;</div><div class='del'>-						strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");</div><div class='add'>+						strscpy(fw_name, "amdgpu/polaris11_k2_smc.bin");</div><div class='ctx'> 					} else {</div><div class='del'>-						strcpy(fw_name, "amdgpu/polaris11_smc.bin");</div><div class='add'>+						strscpy(fw_name, "amdgpu/polaris11_smc.bin");</div><div class='ctx'> 					}</div><div class='ctx'> 				} else if (type == CGS_UCODE_ID_SMU_SK) {</div><div class='del'>-					strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/polaris11_smc_sk.bin");</div><div class='ctx'> 				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_POLARIS10:</div><div class='ctx'> 				if (type == CGS_UCODE_ID_SMU) {</div><div class='ctx'> 					if (ASICID_IS_P20(adev-&gt;pdev-&gt;device, adev-&gt;pdev-&gt;revision)) {</div><div class='ctx'> 						info-&gt;is_kicker = true;</div><div class='del'>-						strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");</div><div class='add'>+						strscpy(fw_name, "amdgpu/polaris10_k_smc.bin");</div><div class='ctx'> 					} else if (ASICID_IS_P30(adev-&gt;pdev-&gt;device, adev-&gt;pdev-&gt;revision)) {</div><div class='ctx'> 						info-&gt;is_kicker = true;</div><div class='del'>-						strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");</div><div class='add'>+						strscpy(fw_name, "amdgpu/polaris10_k2_smc.bin");</div><div class='ctx'> 					} else {</div><div class='del'>-						strcpy(fw_name, "amdgpu/polaris10_smc.bin");</div><div class='add'>+						strscpy(fw_name, "amdgpu/polaris10_smc.bin");</div><div class='ctx'> 					}</div><div class='ctx'> 				} else if (type == CGS_UCODE_ID_SMU_SK) {</div><div class='del'>-					strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/polaris10_smc_sk.bin");</div><div class='ctx'> 				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_POLARIS12:</div><div class='ctx'> 				if (ASICID_IS_P23(adev-&gt;pdev-&gt;device, adev-&gt;pdev-&gt;revision)) {</div><div class='ctx'> 					info-&gt;is_kicker = true;</div><div class='del'>-					strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/polaris12_k_smc.bin");</div><div class='ctx'> 				} else {</div><div class='del'>-					strcpy(fw_name, "amdgpu/polaris12_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/polaris12_smc.bin");</div><div class='ctx'> 				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_VEGAM:</div><div class='del'>-				strcpy(fw_name, "amdgpu/vegam_smc.bin");</div><div class='add'>+				strscpy(fw_name, "amdgpu/vegam_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_VEGA10:</div><div class='ctx'> 				if ((adev-&gt;pdev-&gt;device == 0x687f) &amp;&amp;</div><div class='ctx'> 					((adev-&gt;pdev-&gt;revision == 0xc0) ||</div><div class='ctx'> 					(adev-&gt;pdev-&gt;revision == 0xc1) ||</div><div class='ctx'> 					(adev-&gt;pdev-&gt;revision == 0xc3)))</div><div class='del'>-					strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/vega10_acg_smc.bin");</div><div class='ctx'> 				else</div><div class='del'>-					strcpy(fw_name, "amdgpu/vega10_smc.bin");</div><div class='add'>+					strscpy(fw_name, "amdgpu/vega10_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_VEGA12:</div><div class='del'>-				strcpy(fw_name, "amdgpu/vega12_smc.bin");</div><div class='add'>+				strscpy(fw_name, "amdgpu/vega12_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			case CHIP_VEGA20:</div><div class='del'>-				strcpy(fw_name, "amdgpu/vega20_smc.bin");</div><div class='add'>+				strscpy(fw_name, "amdgpu/vega20_smc.bin");</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				DRM_ERROR("SMC firmware not supported\n");</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;pm.fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;pm.fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "%s", fw_name);</div><div class='ctx'> 			if (err) {</div><div class='ctx'> 				DRM_ERROR("Failed to load firmware \"%s\"", fw_name);</div><div class='ctx'> 				amdgpu_ucode_release(&amp;adev-&gt;pm.fw);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c<br/>index 9caba10315a8..9f96d568acf2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c</a></div><div class='hunk'>@@ -246,30 +246,10 @@ amdgpu_connector_find_encoder(struct drm_connector *connector,</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct edid *amdgpu_connector_edid(struct drm_connector *connector)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-	struct drm_property_blob *edid_blob = connector-&gt;edid_blob_ptr;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_connector-&gt;edid) {</div><div class='del'>-		return amdgpu_connector-&gt;edid;</div><div class='del'>-	} else if (edid_blob) {</div><div class='del'>-		struct edid *edid = kmemdup(edid_blob-&gt;data, edid_blob-&gt;length, GFP_KERNEL);</div><div class='del'>-</div><div class='del'>-		if (edid)</div><div class='del'>-			amdgpu_connector-&gt;edid = edid;</div><div class='del'>-	}</div><div class='del'>-	return amdgpu_connector-&gt;edid;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct edid *</div><div class='ctx'> amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (adev-&gt;mode_info.bios_hardcoded_edid) {</div><div class='del'>-		return kmemdup((unsigned char *)adev-&gt;mode_info.bios_hardcoded_edid,</div><div class='del'>-			       adev-&gt;mode_info.bios_hardcoded_edid_size, GFP_KERNEL);</div><div class='del'>-	}</div><div class='del'>-	return NULL;</div><div class='add'>+	return drm_edid_duplicate(drm_edid_raw(adev-&gt;mode_info.bios_hardcoded_edid));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_connector_get_edid(struct drm_connector *connector)</div><div class='hunk'>@@ -418,30 +398,28 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,</div><div class='ctx'> 	struct drm_display_mode *mode = NULL;</div><div class='ctx'> 	struct drm_display_mode *native_mode = &amp;amdgpu_encoder-&gt;native_mode;</div><div class='ctx'> 	int i;</div><div class='del'>-	static const struct mode_size {</div><div class='add'>+	int n;</div><div class='add'>+	struct mode_size {</div><div class='add'>+		char name[DRM_DISPLAY_MODE_LEN];</div><div class='ctx'> 		int w;</div><div class='ctx'> 		int h;</div><div class='del'>-	} common_modes[17] = {</div><div class='del'>-		{ 640,  480},</div><div class='del'>-		{ 720,  480},</div><div class='del'>-		{ 800,  600},</div><div class='del'>-		{ 848,  480},</div><div class='del'>-		{1024,  768},</div><div class='del'>-		{1152,  768},</div><div class='del'>-		{1280,  720},</div><div class='del'>-		{1280,  800},</div><div class='del'>-		{1280,  854},</div><div class='del'>-		{1280,  960},</div><div class='del'>-		{1280, 1024},</div><div class='del'>-		{1440,  900},</div><div class='del'>-		{1400, 1050},</div><div class='del'>-		{1680, 1050},</div><div class='del'>-		{1600, 1200},</div><div class='del'>-		{1920, 1080},</div><div class='del'>-		{1920, 1200}</div><div class='add'>+	} common_modes[] = {</div><div class='add'>+		{  "640x480",  640,  480},</div><div class='add'>+		{  "800x600",  800,  600},</div><div class='add'>+		{ "1024x768", 1024,  768},</div><div class='add'>+		{ "1280x720", 1280,  720},</div><div class='add'>+		{ "1280x800", 1280,  800},</div><div class='add'>+		{"1280x1024", 1280, 1024},</div><div class='add'>+		{ "1440x900", 1440,  900},</div><div class='add'>+		{"1680x1050", 1680, 1050},</div><div class='add'>+		{"1600x1200", 1600, 1200},</div><div class='add'>+		{"1920x1080", 1920, 1080},</div><div class='add'>+		{"1920x1200", 1920, 1200}</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; 17; i++) {</div><div class='add'>+	n = ARRAY_SIZE(common_modes);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; n; i++) {</div><div class='ctx'> 		if (amdgpu_encoder-&gt;devices &amp; (ATOM_DEVICE_TV_SUPPORT)) {</div><div class='ctx'> 			if (common_modes[i].w &gt; 1024 ||</div><div class='ctx'> 			    common_modes[i].h &gt; 768)</div><div class='hunk'>@@ -454,10 +432,12 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,</div><div class='ctx'> 			     common_modes[i].h == native_mode-&gt;vdisplay))</div><div class='ctx'> 				continue;</div><div class='ctx'> 		}</div><div class='del'>-		if (common_modes[i].w &lt; 320 || common_modes[i].h &lt; 200)</div><div class='del'>-			continue;</div><div class='ctx'> </div><div class='ctx'> 		mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);</div><div class='add'>+		if (!mode)</div><div class='add'>+			return;</div><div class='add'>+		strscpy(mode-&gt;name, common_modes[i].name, DRM_DISPLAY_MODE_LEN);</div><div class='add'>+</div><div class='ctx'> 		drm_mode_probed_add(connector, mode);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -691,7 +671,7 @@ static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,</div><div class='del'>-					     struct drm_display_mode *mode)</div><div class='add'>+					     const struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);</div><div class='ctx'> </div><div class='hunk'>@@ -754,10 +734,8 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_connector_update_scratch_regs(connector, ret);</div><div class='ctx'> </div><div class='del'>-	if (!drm_kms_helper_is_poll_worker()) {</div><div class='del'>-		pm_runtime_mark_last_busy(connector-&gt;dev-&gt;dev);</div><div class='add'>+	if (!drm_kms_helper_is_poll_worker())</div><div class='ctx'> 		pm_runtime_put_autosuspend(connector-&gt;dev-&gt;dev);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -856,7 +834,7 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,</div><div class='del'>-					    struct drm_display_mode *mode)</div><div class='add'>+					    const struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = connector-&gt;dev;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='hunk'>@@ -939,10 +917,8 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)</div><div class='ctx'> 	amdgpu_connector_update_scratch_regs(connector, ret);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	if (!drm_kms_helper_is_poll_worker()) {</div><div class='del'>-		pm_runtime_mark_last_busy(connector-&gt;dev-&gt;dev);</div><div class='add'>+	if (!drm_kms_helper_is_poll_worker())</div><div class='ctx'> 		pm_runtime_put_autosuspend(connector-&gt;dev-&gt;dev);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1166,10 +1142,8 @@ out:</div><div class='ctx'> 	amdgpu_connector_update_scratch_regs(connector, ret);</div><div class='ctx'> </div><div class='ctx'> exit:</div><div class='del'>-	if (!drm_kms_helper_is_poll_worker()) {</div><div class='del'>-		pm_runtime_mark_last_busy(connector-&gt;dev-&gt;dev);</div><div class='add'>+	if (!drm_kms_helper_is_poll_worker())</div><div class='ctx'> 		pm_runtime_put_autosuspend(connector-&gt;dev-&gt;dev);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1212,29 +1186,69 @@ static void amdgpu_connector_dvi_force(struct drm_connector *connector)</div><div class='ctx'> 		amdgpu_connector-&gt;use_digital = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock</div><div class='add'>+ * @adev: pointer to amdgpu_device</div><div class='add'>+ *</div><div class='add'>+ * Return: maximum supported HDMI (TMDS) pixel clock in KHz.</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;asic_type &gt;= CHIP_POLARIS10)</div><div class='add'>+		return 600000;</div><div class='add'>+	else if (adev-&gt;asic_type &gt;= CHIP_TONGA)</div><div class='add'>+		return 300000;</div><div class='add'>+	else</div><div class='add'>+		return 297000;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors</div><div class='add'>+ * @connector: DRM connector to validate the mode on</div><div class='add'>+ * @mode: display mode to validate</div><div class='add'>+ *</div><div class='add'>+ * Validate the given display mode on DVI and HDMI connectors, including</div><div class='add'>+ * analog signals on DVI-I.</div><div class='add'>+ *</div><div class='add'>+ * Return: drm_mode_status indicating whether the mode is valid.</div><div class='add'>+ */</div><div class='ctx'> static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,</div><div class='del'>-					    struct drm_display_mode *mode)</div><div class='add'>+					    const struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = connector-&gt;dev;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='add'>+	const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev);</div><div class='add'>+	const int max_dvi_single_link_pixel_clock = 165000;</div><div class='add'>+	int max_digital_pixel_clock_khz;</div><div class='ctx'> </div><div class='ctx'> 	/* XXX check mode bandwidth */</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_connector-&gt;use_digital &amp;&amp; (mode-&gt;clock &gt; 165000)) {</div><div class='del'>-		if ((amdgpu_connector-&gt;connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||</div><div class='del'>-		    (amdgpu_connector-&gt;connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||</div><div class='del'>-		    (amdgpu_connector-&gt;connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {</div><div class='del'>-			return MODE_OK;</div><div class='del'>-		} else if (connector-&gt;display_info.is_hdmi) {</div><div class='del'>-			/* HDMI 1.3+ supports max clock of 340 Mhz */</div><div class='del'>-			if (mode-&gt;clock &gt; 340000)</div><div class='del'>-				return MODE_CLOCK_HIGH;</div><div class='del'>-			else</div><div class='del'>-				return MODE_OK;</div><div class='del'>-		} else {</div><div class='del'>-			return MODE_CLOCK_HIGH;</div><div class='add'>+	if (amdgpu_connector-&gt;use_digital) {</div><div class='add'>+		switch (amdgpu_connector-&gt;connector_object_id) {</div><div class='add'>+		case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:</div><div class='add'>+			max_digital_pixel_clock_khz = max_hdmi_pixel_clock;</div><div class='add'>+			break;</div><div class='add'>+		case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:</div><div class='add'>+		case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:</div><div class='add'>+			max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock;</div><div class='add'>+			break;</div><div class='add'>+		case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:</div><div class='add'>+		case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:</div><div class='add'>+		case CONNECTOR_OBJECT_ID_HDMI_TYPE_B:</div><div class='add'>+			max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		/* When the display EDID claims that it's an HDMI display,</div><div class='add'>+		 * we use the HDMI encoder mode of the display HW,</div><div class='add'>+		 * so we should verify against the max HDMI clock here.</div><div class='add'>+		 */</div><div class='add'>+		if (connector-&gt;display_info.is_hdmi)</div><div class='add'>+			max_digital_pixel_clock_khz = max_hdmi_pixel_clock;</div><div class='add'>+</div><div class='add'>+		if (mode-&gt;clock &gt; max_digital_pixel_clock_khz)</div><div class='add'>+			return MODE_CLOCK_HIGH;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* check against the max pixel clock */</div><div class='hunk'>@@ -1466,10 +1480,8 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_connector_update_scratch_regs(connector, ret);</div><div class='ctx'> out:</div><div class='del'>-	if (!drm_kms_helper_is_poll_worker()) {</div><div class='del'>-		pm_runtime_mark_last_busy(connector-&gt;dev-&gt;dev);</div><div class='add'>+	if (!drm_kms_helper_is_poll_worker())</div><div class='ctx'> 		pm_runtime_put_autosuspend(connector-&gt;dev-&gt;dev);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_DisplayPort ||</div><div class='ctx'> 	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='hunk'>@@ -1481,7 +1493,7 @@ out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,</div><div class='del'>-					   struct drm_display_mode *mode)</div><div class='add'>+					   const struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='ctx'> 	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector-&gt;con_priv;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h<br/>index 61fcef15ad72..eff833b6ed31 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h</a></div><div class='hunk'>@@ -24,7 +24,6 @@</div><div class='ctx'> #ifndef __AMDGPU_CONNECTORS_H__</div><div class='ctx'> #define __AMDGPU_CONNECTORS_H__</div><div class='ctx'> </div><div class='del'>-struct edid *amdgpu_connector_edid(struct drm_connector *connector);</div><div class='ctx'> void amdgpu_connector_hotplug(struct drm_connector *connector);</div><div class='ctx'> int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);</div><div class='ctx'> u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c<br/>new file mode 100644<br/>index 000000000000..425a3e564360<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c</a></div><div class='hunk'>@@ -0,0 +1,591 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+</div><div class='add'>+static const guid_t MCE			= CPER_NOTIFY_MCE;</div><div class='add'>+static const guid_t CMC			= CPER_NOTIFY_CMC;</div><div class='add'>+static const guid_t BOOT		= BOOT_TYPE;</div><div class='add'>+</div><div class='add'>+static const guid_t CRASHDUMP		= AMD_CRASHDUMP;</div><div class='add'>+static const guid_t RUNTIME		= AMD_GPU_NONSTANDARD_ERROR;</div><div class='add'>+</div><div class='add'>+static void __inc_entry_length(struct cper_hdr *hdr, uint32_t size)</div><div class='add'>+{</div><div class='add'>+	hdr-&gt;record_length += size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_cper_get_timestamp(struct cper_timestamp *timestamp)</div><div class='add'>+{</div><div class='add'>+	struct tm tm;</div><div class='add'>+	time64_t now = ktime_get_real_seconds();</div><div class='add'>+</div><div class='add'>+	time64_to_tm(now, 0, &amp;tm);</div><div class='add'>+	timestamp-&gt;seconds = tm.tm_sec;</div><div class='add'>+	timestamp-&gt;minutes = tm.tm_min;</div><div class='add'>+	timestamp-&gt;hours = tm.tm_hour;</div><div class='add'>+	timestamp-&gt;flag = 0;</div><div class='add'>+	timestamp-&gt;day = tm.tm_mday;</div><div class='add'>+	timestamp-&gt;month = 1 + tm.tm_mon;</div><div class='add'>+	timestamp-&gt;year = (1900 + tm.tm_year) % 100;</div><div class='add'>+	timestamp-&gt;century = (1900 + tm.tm_year) / 100;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,</div><div class='add'>+				struct cper_hdr *hdr,</div><div class='add'>+				enum amdgpu_cper_type type,</div><div class='add'>+				enum cper_error_severity sev)</div><div class='add'>+{</div><div class='add'>+	char record_id[16];</div><div class='add'>+</div><div class='add'>+	hdr-&gt;signature[0]		= 'C';</div><div class='add'>+	hdr-&gt;signature[1]		= 'P';</div><div class='add'>+	hdr-&gt;signature[2]		= 'E';</div><div class='add'>+	hdr-&gt;signature[3]		= 'R';</div><div class='add'>+	hdr-&gt;revision			= CPER_HDR_REV_1;</div><div class='add'>+	hdr-&gt;signature_end		= 0xFFFFFFFF;</div><div class='add'>+	hdr-&gt;error_severity		= sev;</div><div class='add'>+</div><div class='add'>+	hdr-&gt;valid_bits.platform_id	= 1;</div><div class='add'>+	hdr-&gt;valid_bits.timestamp	= 1;</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_get_timestamp(&amp;hdr-&gt;timestamp);</div><div class='add'>+</div><div class='add'>+	snprintf(record_id, 9, "%d:%X",</div><div class='add'>+		 (adev-&gt;smuio.funcs &amp;&amp; adev-&gt;smuio.funcs-&gt;get_socket_id) ?</div><div class='add'>+			 adev-&gt;smuio.funcs-&gt;get_socket_id(adev) :</div><div class='add'>+			 0,</div><div class='add'>+		 atomic_inc_return(&amp;adev-&gt;cper.unique_id));</div><div class='add'>+	memcpy(hdr-&gt;record_id, record_id, 8);</div><div class='add'>+</div><div class='add'>+	snprintf(hdr-&gt;platform_id, 16, "0x%04X:0x%04X",</div><div class='add'>+		 adev-&gt;pdev-&gt;vendor, adev-&gt;pdev-&gt;device);</div><div class='add'>+	/* pmfw version should be part of creator_id according to CPER spec */</div><div class='add'>+	snprintf(hdr-&gt;creator_id, 16, "%s", CPER_CREATOR_ID_AMDGPU);</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case AMDGPU_CPER_TYPE_BOOT:</div><div class='add'>+		hdr-&gt;notify_type = BOOT;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CPER_TYPE_FATAL:</div><div class='add'>+	case AMDGPU_CPER_TYPE_BP_THRESHOLD:</div><div class='add'>+		hdr-&gt;notify_type = MCE;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CPER_TYPE_RUNTIME:</div><div class='add'>+		if (sev == CPER_SEV_NON_FATAL_CORRECTED)</div><div class='add'>+			hdr-&gt;notify_type = CMC;</div><div class='add'>+		else</div><div class='add'>+			hdr-&gt;notify_type = MCE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "Unknown CPER Type\n");</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	__inc_entry_length(hdr, HDR_LEN);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_cper_entry_fill_section_desc(struct amdgpu_device *adev,</div><div class='add'>+					       struct cper_sec_desc *section_desc,</div><div class='add'>+					       bool bp_threshold,</div><div class='add'>+					       bool poison,</div><div class='add'>+					       enum cper_error_severity sev,</div><div class='add'>+					       guid_t sec_type,</div><div class='add'>+					       uint32_t section_length,</div><div class='add'>+					       uint32_t section_offset)</div><div class='add'>+{</div><div class='add'>+	section_desc-&gt;revision_minor		= CPER_SEC_MINOR_REV_1;</div><div class='add'>+	section_desc-&gt;revision_major		= CPER_SEC_MAJOR_REV_22;</div><div class='add'>+	section_desc-&gt;sec_offset		= section_offset;</div><div class='add'>+	section_desc-&gt;sec_length		= section_length;</div><div class='add'>+	section_desc-&gt;valid_bits.fru_text	= 1;</div><div class='add'>+	section_desc-&gt;flag_bits.primary		= 1;</div><div class='add'>+	section_desc-&gt;severity			= sev;</div><div class='add'>+	section_desc-&gt;sec_type			= sec_type;</div><div class='add'>+</div><div class='add'>+	snprintf(section_desc-&gt;fru_text, 20, "OAM%d",</div><div class='add'>+		 (adev-&gt;smuio.funcs &amp;&amp; adev-&gt;smuio.funcs-&gt;get_socket_id) ?</div><div class='add'>+			 adev-&gt;smuio.funcs-&gt;get_socket_id(adev) :</div><div class='add'>+			 0);</div><div class='add'>+</div><div class='add'>+	if (bp_threshold)</div><div class='add'>+		section_desc-&gt;flag_bits.exceed_err_threshold = 1;</div><div class='add'>+	if (poison)</div><div class='add'>+		section_desc-&gt;flag_bits.latent_err = 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,</div><div class='add'>+					 struct cper_hdr *hdr,</div><div class='add'>+					 uint32_t idx,</div><div class='add'>+					 struct cper_sec_crashdump_reg_data reg_data)</div><div class='add'>+{</div><div class='add'>+	struct cper_sec_desc *section_desc;</div><div class='add'>+	struct cper_sec_crashdump_fatal *section;</div><div class='add'>+</div><div class='add'>+	section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));</div><div class='add'>+	section = (struct cper_sec_crashdump_fatal *)((uint8_t *)hdr +</div><div class='add'>+		   FATAL_SEC_OFFSET(hdr-&gt;sec_cnt, idx));</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false,</div><div class='add'>+					    CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN,</div><div class='add'>+					    FATAL_SEC_OFFSET(hdr-&gt;sec_cnt, idx));</div><div class='add'>+</div><div class='add'>+	section-&gt;body.reg_ctx_type = CPER_CTX_TYPE_CRASH;</div><div class='add'>+	section-&gt;body.reg_arr_size = sizeof(reg_data);</div><div class='add'>+	section-&gt;body.data = reg_data;</div><div class='add'>+</div><div class='add'>+	__inc_entry_length(hdr, SEC_DESC_LEN + FATAL_SEC_LEN);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,</div><div class='add'>+					   struct cper_hdr *hdr,</div><div class='add'>+					   uint32_t idx,</div><div class='add'>+					   enum cper_error_severity sev,</div><div class='add'>+					   uint32_t *reg_dump,</div><div class='add'>+					   uint32_t reg_count)</div><div class='add'>+{</div><div class='add'>+	struct cper_sec_desc *section_desc;</div><div class='add'>+	struct cper_sec_nonstd_err *section;</div><div class='add'>+	bool poison;</div><div class='add'>+</div><div class='add'>+	poison = sev != CPER_SEV_NON_FATAL_CORRECTED;</div><div class='add'>+	section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));</div><div class='add'>+	section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +</div><div class='add'>+		   NONSTD_SEC_OFFSET(hdr-&gt;sec_cnt, idx));</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, poison,</div><div class='add'>+					    sev, RUNTIME, NONSTD_SEC_LEN,</div><div class='add'>+					    NONSTD_SEC_OFFSET(hdr-&gt;sec_cnt, idx));</div><div class='add'>+</div><div class='add'>+	reg_count = umin(reg_count, CPER_ACA_REG_COUNT);</div><div class='add'>+</div><div class='add'>+	section-&gt;hdr.valid_bits.err_info_cnt = 1;</div><div class='add'>+	section-&gt;hdr.valid_bits.err_context_cnt = 1;</div><div class='add'>+</div><div class='add'>+	section-&gt;info.error_type = RUNTIME;</div><div class='add'>+	section-&gt;info.ms_chk_bits.err_type_valid = 1;</div><div class='add'>+	section-&gt;ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH;</div><div class='add'>+	section-&gt;ctx.reg_arr_size = sizeof(section-&gt;ctx.reg_dump);</div><div class='add'>+</div><div class='add'>+	memcpy(section-&gt;ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t));</div><div class='add'>+</div><div class='add'>+	__inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,</div><div class='add'>+						      struct cper_hdr *hdr,</div><div class='add'>+						      uint32_t idx)</div><div class='add'>+{</div><div class='add'>+	struct cper_sec_desc *section_desc;</div><div class='add'>+	struct cper_sec_nonstd_err *section;</div><div class='add'>+	uint32_t socket_id;</div><div class='add'>+</div><div class='add'>+	section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx));</div><div class='add'>+	section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr +</div><div class='add'>+		   NONSTD_SEC_OFFSET(hdr-&gt;sec_cnt, idx));</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false,</div><div class='add'>+					    CPER_SEV_FATAL, RUNTIME, NONSTD_SEC_LEN,</div><div class='add'>+					    NONSTD_SEC_OFFSET(hdr-&gt;sec_cnt, idx));</div><div class='add'>+</div><div class='add'>+	section-&gt;hdr.valid_bits.err_info_cnt = 1;</div><div class='add'>+	section-&gt;hdr.valid_bits.err_context_cnt = 1;</div><div class='add'>+</div><div class='add'>+	section-&gt;info.error_type = RUNTIME;</div><div class='add'>+	section-&gt;info.valid_bits.ms_chk = 1;</div><div class='add'>+	section-&gt;info.ms_chk_bits.err_type_valid = 1;</div><div class='add'>+	section-&gt;info.ms_chk_bits.err_type = 1;</div><div class='add'>+	section-&gt;info.ms_chk_bits.pcc = 1;</div><div class='add'>+	section-&gt;ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH;</div><div class='add'>+	section-&gt;ctx.reg_arr_size = sizeof(section-&gt;ctx.reg_dump);</div><div class='add'>+</div><div class='add'>+	/* Hardcoded Reg dump for bad page threshold CPER */</div><div class='add'>+	socket_id = (adev-&gt;smuio.funcs &amp;&amp; adev-&gt;smuio.funcs-&gt;get_socket_id) ?</div><div class='add'>+				adev-&gt;smuio.funcs-&gt;get_socket_id(adev) :</div><div class='add'>+				0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_CTL_LO]    = 0x1;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_CTL_HI]    = 0x0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_ADDR_LO]   = 0x0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_ADDR_HI]   = 0x0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_MISC0_LO]  = 0x0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_MISC0_HI]  = 0x0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_IPID_LO]   = (socket_id / 4) &amp; 0x01;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_IPID_HI]   = 0x096 | (((socket_id % 4) &amp; 0x3) &lt;&lt; 12);</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_SYND_LO]   = 0x0;</div><div class='add'>+	section-&gt;ctx.reg_dump[CPER_ACA_REG_SYND_HI]   = 0x0;</div><div class='add'>+</div><div class='add'>+	__inc_entry_length(hdr, SEC_DESC_LEN + NONSTD_SEC_LEN);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,</div><div class='add'>+					 enum amdgpu_cper_type type,</div><div class='add'>+					 uint16_t section_count)</div><div class='add'>+{</div><div class='add'>+	struct cper_hdr *hdr;</div><div class='add'>+	uint32_t size = 0;</div><div class='add'>+</div><div class='add'>+	size += HDR_LEN;</div><div class='add'>+	size += (SEC_DESC_LEN * section_count);</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case AMDGPU_CPER_TYPE_RUNTIME:</div><div class='add'>+	case AMDGPU_CPER_TYPE_BP_THRESHOLD:</div><div class='add'>+		size += (NONSTD_SEC_LEN * section_count);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CPER_TYPE_FATAL:</div><div class='add'>+		size += (FATAL_SEC_LEN * section_count);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CPER_TYPE_BOOT:</div><div class='add'>+		size += (BOOT_SEC_LEN * section_count);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "Unknown CPER Type!\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hdr = kzalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!hdr)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	/* Save this early */</div><div class='add'>+	hdr-&gt;sec_cnt = section_count;</div><div class='add'>+</div><div class='add'>+	return hdr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev,</div><div class='add'>+				   struct aca_bank *bank)</div><div class='add'>+{</div><div class='add'>+	struct cper_hdr *fatal = NULL;</div><div class='add'>+	struct cper_sec_crashdump_reg_data reg_data = { 0 };</div><div class='add'>+	struct amdgpu_ring *ring = &amp;adev-&gt;cper.ring_buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	fatal = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_FATAL, 1);</div><div class='add'>+	if (!fatal) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to alloc cper entry for ue record\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg_data.status_lo = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_STATUS]);</div><div class='add'>+	reg_data.status_hi = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_STATUS]);</div><div class='add'>+	reg_data.addr_lo   = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_ADDR]);</div><div class='add'>+	reg_data.addr_hi   = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_ADDR]);</div><div class='add'>+	reg_data.ipid_lo   = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	reg_data.ipid_hi   = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	reg_data.synd_lo   = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_SYND]);</div><div class='add'>+	reg_data.synd_hi   = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_SYND]);</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL);</div><div class='add'>+	ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_ring_write(ring, fatal, fatal-&gt;record_length);</div><div class='add'>+	kfree(fatal);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct cper_hdr *bp_threshold = NULL;</div><div class='add'>+	struct amdgpu_ring *ring = &amp;adev-&gt;cper.ring_buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	bp_threshold = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_BP_THRESHOLD, 1);</div><div class='add'>+	if (!bp_threshold) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to alloc cper entry for bad page threshold record\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_entry_fill_hdr(adev, bp_threshold,</div><div class='add'>+				   AMDGPU_CPER_TYPE_BP_THRESHOLD,</div><div class='add'>+				   CPER_SEV_FATAL);</div><div class='add'>+	ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_ring_write(ring, bp_threshold, bp_threshold-&gt;record_length);</div><div class='add'>+	kfree(bp_threshold);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum cper_error_severity amdgpu_aca_err_type_to_cper_sev(struct amdgpu_device *adev,</div><div class='add'>+								enum aca_error_type aca_err_type)</div><div class='add'>+{</div><div class='add'>+	switch (aca_err_type) {</div><div class='add'>+	case ACA_ERROR_TYPE_UE:</div><div class='add'>+		return CPER_SEV_FATAL;</div><div class='add'>+	case ACA_ERROR_TYPE_CE:</div><div class='add'>+		return CPER_SEV_NON_FATAL_CORRECTED;</div><div class='add'>+	case ACA_ERROR_TYPE_DEFERRED:</div><div class='add'>+		return CPER_SEV_NON_FATAL_UNCORRECTED;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "Unknown ACA error type!\n");</div><div class='add'>+		return CPER_SEV_FATAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev,</div><div class='add'>+				    struct aca_banks *banks,</div><div class='add'>+				    uint16_t bank_count)</div><div class='add'>+{</div><div class='add'>+	struct cper_hdr *corrected = NULL;</div><div class='add'>+	enum cper_error_severity sev = CPER_SEV_NON_FATAL_CORRECTED;</div><div class='add'>+	struct amdgpu_ring *ring = &amp;adev-&gt;cper.ring_buf;</div><div class='add'>+	uint32_t reg_data[CPER_ACA_REG_COUNT] = { 0 };</div><div class='add'>+	struct aca_bank_node *node;</div><div class='add'>+	struct aca_bank *bank;</div><div class='add'>+	uint32_t i = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	corrected = amdgpu_cper_alloc_entry(adev, AMDGPU_CPER_TYPE_RUNTIME, bank_count);</div><div class='add'>+	if (!corrected) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to allocate cper entry for ce records\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Raise severity if any DE is detected in the ACA bank list */</div><div class='add'>+	list_for_each_entry(node, &amp;banks-&gt;list, node) {</div><div class='add'>+		bank = &amp;node-&gt;bank;</div><div class='add'>+		if (bank-&gt;aca_err_type == ACA_ERROR_TYPE_DEFERRED) {</div><div class='add'>+			sev = CPER_SEV_NON_FATAL_UNCORRECTED;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_entry_fill_hdr(adev, corrected, AMDGPU_CPER_TYPE_RUNTIME, sev);</div><div class='add'>+</div><div class='add'>+	/* Combine CE and DE in cper record */</div><div class='add'>+	list_for_each_entry(node, &amp;banks-&gt;list, node) {</div><div class='add'>+		bank = &amp;node-&gt;bank;</div><div class='add'>+		reg_data[CPER_ACA_REG_CTL_LO]    = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_CTL]);</div><div class='add'>+		reg_data[CPER_ACA_REG_CTL_HI]    = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_CTL]);</div><div class='add'>+		reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_STATUS]);</div><div class='add'>+		reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_STATUS]);</div><div class='add'>+		reg_data[CPER_ACA_REG_ADDR_LO]   = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_ADDR]);</div><div class='add'>+		reg_data[CPER_ACA_REG_ADDR_HI]   = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_ADDR]);</div><div class='add'>+		reg_data[CPER_ACA_REG_MISC0_LO]  = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_MISC0]);</div><div class='add'>+		reg_data[CPER_ACA_REG_MISC0_HI]  = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_MISC0]);</div><div class='add'>+		reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_CONFIG]);</div><div class='add'>+		reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_CONFIG]);</div><div class='add'>+		reg_data[CPER_ACA_REG_IPID_LO]   = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+		reg_data[CPER_ACA_REG_IPID_HI]   = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+		reg_data[CPER_ACA_REG_SYND_LO]   = lower_32_bits(bank-&gt;regs[ACA_REG_IDX_SYND]);</div><div class='add'>+		reg_data[CPER_ACA_REG_SYND_HI]   = upper_32_bits(bank-&gt;regs[ACA_REG_IDX_SYND]);</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_cper_entry_fill_runtime_section(adev, corrected, i++,</div><div class='add'>+				amdgpu_aca_err_type_to_cper_sev(adev, bank-&gt;aca_err_type),</div><div class='add'>+				reg_data, CPER_ACA_REG_COUNT);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_cper_ring_write(ring, corrected, corrected-&gt;record_length);</div><div class='add'>+	kfree(corrected);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_cper_is_hdr(struct amdgpu_ring *ring, u64 pos)</div><div class='add'>+{</div><div class='add'>+	struct cper_hdr *chdr;</div><div class='add'>+</div><div class='add'>+	chdr = (struct cper_hdr *)&amp;(ring-&gt;ring[pos]);</div><div class='add'>+	return strcmp(chdr-&gt;signature, "CPER") ? false : true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos)</div><div class='add'>+{</div><div class='add'>+	struct cper_hdr *chdr;</div><div class='add'>+	u64 p;</div><div class='add'>+	u32 chunk, rec_len = 0;</div><div class='add'>+</div><div class='add'>+	chdr = (struct cper_hdr *)&amp;(ring-&gt;ring[pos]);</div><div class='add'>+	chunk = ring-&gt;ring_size - (pos &lt;&lt; 2);</div><div class='add'>+</div><div class='add'>+	if (!strcmp(chdr-&gt;signature, "CPER")) {</div><div class='add'>+		rec_len = chdr-&gt;record_length;</div><div class='add'>+		goto calc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* ring buffer is not full, no cper data after ring-&gt;wptr */</div><div class='add'>+	if (ring-&gt;count_dw)</div><div class='add'>+		goto calc;</div><div class='add'>+</div><div class='add'>+	for (p = pos + 1; p &lt;= ring-&gt;buf_mask; p++) {</div><div class='add'>+		chdr = (struct cper_hdr *)&amp;(ring-&gt;ring[p]);</div><div class='add'>+		if (!strcmp(chdr-&gt;signature, "CPER")) {</div><div class='add'>+			rec_len = (p - pos) &lt;&lt; 2;</div><div class='add'>+			goto calc;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+calc:</div><div class='add'>+	if (!rec_len)</div><div class='add'>+		return chunk;</div><div class='add'>+	else</div><div class='add'>+		return umin(rec_len, chunk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count)</div><div class='add'>+{</div><div class='add'>+	u64 pos, wptr_old, rptr;</div><div class='add'>+	int rec_cnt_dw = count &gt;&gt; 2;</div><div class='add'>+	u32 chunk, ent_sz;</div><div class='add'>+	u8 *s = (u8 *)src;</div><div class='add'>+</div><div class='add'>+	if (count &gt;= ring-&gt;ring_size - 4) {</div><div class='add'>+		dev_err(ring-&gt;adev-&gt;dev,</div><div class='add'>+			"CPER data size(%d) is larger than ring size(%d)\n",</div><div class='add'>+			count, ring-&gt;ring_size - 4);</div><div class='add'>+</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ring-&gt;adev-&gt;cper.ring_lock);</div><div class='add'>+</div><div class='add'>+	wptr_old = ring-&gt;wptr;</div><div class='add'>+	rptr = *ring-&gt;rptr_cpu_addr &amp; ring-&gt;ptr_mask;</div><div class='add'>+</div><div class='add'>+	while (count) {</div><div class='add'>+		ent_sz = amdgpu_cper_ring_get_ent_sz(ring, ring-&gt;wptr);</div><div class='add'>+		chunk = umin(ent_sz, count);</div><div class='add'>+</div><div class='add'>+		memcpy(&amp;ring-&gt;ring[ring-&gt;wptr], s, chunk);</div><div class='add'>+</div><div class='add'>+		ring-&gt;wptr += (chunk &gt;&gt; 2);</div><div class='add'>+		ring-&gt;wptr &amp;= ring-&gt;ptr_mask;</div><div class='add'>+		count -= chunk;</div><div class='add'>+		s += chunk;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;count_dw &lt; rec_cnt_dw)</div><div class='add'>+		ring-&gt;count_dw = 0;</div><div class='add'>+</div><div class='add'>+	/* the buffer is overflow, adjust rptr */</div><div class='add'>+	if (((wptr_old &lt; rptr) &amp;&amp; (rptr &lt;= ring-&gt;wptr)) ||</div><div class='add'>+	    ((ring-&gt;wptr &lt; wptr_old) &amp;&amp; (wptr_old &lt; rptr)) ||</div><div class='add'>+	    ((rptr &lt;= ring-&gt;wptr) &amp;&amp; (ring-&gt;wptr &lt; wptr_old))) {</div><div class='add'>+		pos = (ring-&gt;wptr + 1) &amp; ring-&gt;ptr_mask;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			ent_sz = amdgpu_cper_ring_get_ent_sz(ring, pos);</div><div class='add'>+</div><div class='add'>+			rptr += (ent_sz &gt;&gt; 2);</div><div class='add'>+			rptr &amp;= ring-&gt;ptr_mask;</div><div class='add'>+			*ring-&gt;rptr_cpu_addr = rptr;</div><div class='add'>+</div><div class='add'>+			pos = rptr;</div><div class='add'>+		} while (!amdgpu_cper_is_hdr(ring, rptr));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;count_dw &gt;= rec_cnt_dw)</div><div class='add'>+		ring-&gt;count_dw -= rec_cnt_dw;</div><div class='add'>+	mutex_unlock(&amp;ring-&gt;adev-&gt;cper.ring_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 amdgpu_cper_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	return *(ring-&gt;rptr_cpu_addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 amdgpu_cper_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	return ring-&gt;wptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs cper_ring_funcs = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_CPER,</div><div class='add'>+	.align_mask = 0xff,</div><div class='add'>+	.support_64bit_ptrs = false,</div><div class='add'>+	.get_rptr = amdgpu_cper_ring_get_rptr,</div><div class='add'>+	.get_wptr = amdgpu_cper_ring_get_wptr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int amdgpu_cper_ring_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring = &amp;(adev-&gt;cper.ring_buf);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;adev-&gt;cper.ring_lock);</div><div class='add'>+</div><div class='add'>+	ring-&gt;adev = NULL;</div><div class='add'>+	ring-&gt;ring_obj = NULL;</div><div class='add'>+	ring-&gt;use_doorbell = false;</div><div class='add'>+	ring-&gt;no_scheduler = true;</div><div class='add'>+	ring-&gt;funcs = &amp;cper_ring_funcs;</div><div class='add'>+</div><div class='add'>+	sprintf(ring-&gt;name, "cper");</div><div class='add'>+	return amdgpu_ring_init(adev, ring, CPER_MAX_RING_SIZE, NULL, 0,</div><div class='add'>+				AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_aca_is_enabled(adev) &amp;&amp; !amdgpu_sriov_ras_cper_en(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_cper_ring_init(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to initialize cper ring, r = %d\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;adev-&gt;cper.cper_lock);</div><div class='add'>+</div><div class='add'>+	adev-&gt;cper.enabled = true;</div><div class='add'>+	adev-&gt;cper.max_count = CPER_MAX_ALLOWED_COUNT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_cper_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_aca_is_enabled(adev) &amp;&amp; !amdgpu_sriov_ras_cper_en(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	adev-&gt;cper.enabled = false;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_fini(&amp;(adev-&gt;cper.ring_buf));</div><div class='add'>+	adev-&gt;cper.count = 0;</div><div class='add'>+	adev-&gt;cper.wptr = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h<br/>new file mode 100644<br/>index 000000000000..353421807387<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h</a></div><div class='hunk'>@@ -0,0 +1,105 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_CPER_H__</div><div class='add'>+#define __AMDGPU_CPER_H__</div><div class='add'>+</div><div class='add'>+#include "amd_cper.h"</div><div class='add'>+#include "amdgpu_aca.h"</div><div class='add'>+</div><div class='add'>+#define CPER_MAX_ALLOWED_COUNT		0x1000</div><div class='add'>+#define CPER_MAX_RING_SIZE		0X100000</div><div class='add'>+#define HDR_LEN				(sizeof(struct cper_hdr))</div><div class='add'>+#define SEC_DESC_LEN			(sizeof(struct cper_sec_desc))</div><div class='add'>+</div><div class='add'>+#define BOOT_SEC_LEN			(sizeof(struct cper_sec_crashdump_boot))</div><div class='add'>+#define FATAL_SEC_LEN			(sizeof(struct cper_sec_crashdump_fatal))</div><div class='add'>+#define NONSTD_SEC_LEN			(sizeof(struct cper_sec_nonstd_err))</div><div class='add'>+</div><div class='add'>+#define SEC_DESC_OFFSET(idx)		(HDR_LEN + (SEC_DESC_LEN * idx))</div><div class='add'>+</div><div class='add'>+#define BOOT_SEC_OFFSET(count, idx)	(HDR_LEN + (SEC_DESC_LEN * count) + (BOOT_SEC_LEN * idx))</div><div class='add'>+#define FATAL_SEC_OFFSET(count, idx)	(HDR_LEN + (SEC_DESC_LEN * count) + (FATAL_SEC_LEN * idx))</div><div class='add'>+#define NONSTD_SEC_OFFSET(count, idx)	(HDR_LEN + (SEC_DESC_LEN * count) + (NONSTD_SEC_LEN * idx))</div><div class='add'>+</div><div class='add'>+enum amdgpu_cper_type {</div><div class='add'>+	AMDGPU_CPER_TYPE_RUNTIME,</div><div class='add'>+	AMDGPU_CPER_TYPE_FATAL,</div><div class='add'>+	AMDGPU_CPER_TYPE_BOOT,</div><div class='add'>+	AMDGPU_CPER_TYPE_BP_THRESHOLD,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_cper {</div><div class='add'>+	bool enabled;</div><div class='add'>+</div><div class='add'>+	atomic_t unique_id;</div><div class='add'>+	struct mutex cper_lock;</div><div class='add'>+</div><div class='add'>+	/* Lifetime CPERs generated */</div><div class='add'>+	uint32_t count;</div><div class='add'>+	uint32_t max_count;</div><div class='add'>+</div><div class='add'>+	uint32_t wptr;</div><div class='add'>+</div><div class='add'>+	void *ring[CPER_MAX_ALLOWED_COUNT];</div><div class='add'>+	struct amdgpu_ring ring_buf;</div><div class='add'>+	struct mutex ring_lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,</div><div class='add'>+				struct cper_hdr *hdr,</div><div class='add'>+				enum amdgpu_cper_type type,</div><div class='add'>+				enum cper_error_severity sev);</div><div class='add'>+int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,</div><div class='add'>+					 struct cper_hdr *hdr,</div><div class='add'>+					 uint32_t idx,</div><div class='add'>+					 struct cper_sec_crashdump_reg_data reg_data);</div><div class='add'>+int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,</div><div class='add'>+					   struct cper_hdr *hdr,</div><div class='add'>+					   uint32_t idx,</div><div class='add'>+					   enum cper_error_severity sev,</div><div class='add'>+					   uint32_t *reg_dump,</div><div class='add'>+					   uint32_t reg_count);</div><div class='add'>+int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,</div><div class='add'>+						      struct cper_hdr *hdr,</div><div class='add'>+						      uint32_t section_idx);</div><div class='add'>+</div><div class='add'>+struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,</div><div class='add'>+					 enum amdgpu_cper_type type,</div><div class='add'>+					 uint16_t section_count);</div><div class='add'>+/* UE must be encoded into separated cper entries, 1 UE 1 cper */</div><div class='add'>+int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev,</div><div class='add'>+				   struct aca_bank *bank);</div><div class='add'>+/* CEs and DEs are combined into 1 cper entry */</div><div class='add'>+int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev,</div><div class='add'>+				    struct aca_banks *banks,</div><div class='add'>+				    uint16_t bank_count);</div><div class='add'>+/* Bad page threshold is encoded into separated cper entry */</div><div class='add'>+int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_cper_ring_write(struct amdgpu_ring *ring,</div><div class='add'>+			void *src, int count);</div><div class='add'>+int amdgpu_cper_init(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_cper_fini(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c<br/>index 0a4b09709cfb..ecdfe6cb36cc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c</a></div><div class='hunk'>@@ -40,6 +40,7 @@</div><div class='ctx'> #include "amdgpu_gmc.h"</div><div class='ctx'> #include "amdgpu_gem.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_hmm.h"</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,</div><div class='ctx'> 				 struct amdgpu_device *adev,</div><div class='hunk'>@@ -178,25 +179,17 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv = p-&gt;filp-&gt;driver_priv;</div><div class='ctx'> 	unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };</div><div class='ctx'> 	struct amdgpu_vm *vm = &amp;fpriv-&gt;vm;</div><div class='del'>-	uint64_t *chunk_array_user;</div><div class='ctx'> 	uint64_t *chunk_array;</div><div class='ctx'> 	uint32_t uf_offset = 0;</div><div class='ctx'> 	size_t size;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	chunk_array = kvmalloc_array(cs-&gt;in.num_chunks, sizeof(uint64_t),</div><div class='del'>-				     GFP_KERNEL);</div><div class='del'>-	if (!chunk_array)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	/* get chunks */</div><div class='del'>-	chunk_array_user = u64_to_user_ptr(cs-&gt;in.chunks);</div><div class='del'>-	if (copy_from_user(chunk_array, chunk_array_user,</div><div class='del'>-			   sizeof(uint64_t)*cs-&gt;in.num_chunks)) {</div><div class='del'>-		ret = -EFAULT;</div><div class='del'>-		goto free_chunk;</div><div class='del'>-	}</div><div class='add'>+	chunk_array = memdup_array_user(u64_to_user_ptr(cs-&gt;in.chunks),</div><div class='add'>+					cs-&gt;in.num_chunks,</div><div class='add'>+					sizeof(uint64_t));</div><div class='add'>+	if (IS_ERR(chunk_array))</div><div class='add'>+		return PTR_ERR(chunk_array);</div><div class='ctx'> </div><div class='ctx'> 	p-&gt;nchunks = cs-&gt;in.num_chunks;</div><div class='ctx'> 	p-&gt;chunks = kvmalloc_array(p-&gt;nchunks, sizeof(struct amdgpu_cs_chunk),</div><div class='hunk'>@@ -209,7 +202,6 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;nchunks; i++) {</div><div class='ctx'> 		struct drm_amdgpu_cs_chunk __user *chunk_ptr = NULL;</div><div class='ctx'> 		struct drm_amdgpu_cs_chunk user_chunk;</div><div class='del'>-		uint32_t __user *cdata;</div><div class='ctx'> </div><div class='ctx'> 		chunk_ptr = u64_to_user_ptr(chunk_array[i]);</div><div class='ctx'> 		if (copy_from_user(&amp;user_chunk, chunk_ptr,</div><div class='hunk'>@@ -222,20 +214,16 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		p-&gt;chunks[i].length_dw = user_chunk.length_dw;</div><div class='ctx'> </div><div class='ctx'> 		size = p-&gt;chunks[i].length_dw;</div><div class='del'>-		cdata = u64_to_user_ptr(user_chunk.chunk_data);</div><div class='ctx'> </div><div class='del'>-		p-&gt;chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),</div><div class='del'>-						    GFP_KERNEL);</div><div class='del'>-		if (p-&gt;chunks[i].kdata == NULL) {</div><div class='del'>-			ret = -ENOMEM;</div><div class='add'>+		p-&gt;chunks[i].kdata = vmemdup_array_user(u64_to_user_ptr(user_chunk.chunk_data),</div><div class='add'>+							size,</div><div class='add'>+							sizeof(uint32_t));</div><div class='add'>+		if (IS_ERR(p-&gt;chunks[i].kdata)) {</div><div class='add'>+			ret = PTR_ERR(p-&gt;chunks[i].kdata);</div><div class='ctx'> 			i--;</div><div class='ctx'> 			goto free_partial_kdata;</div><div class='ctx'> 		}</div><div class='ctx'> 		size *= sizeof(uint32_t);</div><div class='del'>-		if (copy_from_user(p-&gt;chunks[i].kdata, cdata, size)) {</div><div class='del'>-			ret = -EFAULT;</div><div class='del'>-			goto free_partial_kdata;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		/* Assume the worst on the following checks */</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -263,6 +251,10 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,</div><div class='ctx'> 			if (size &lt; sizeof(struct drm_amdgpu_bo_list_in))</div><div class='ctx'> 				goto free_partial_kdata;</div><div class='ctx'> </div><div class='add'>+			/* Only a single BO list is allowed to simplify handling. */</div><div class='add'>+			if (p-&gt;bo_list)</div><div class='add'>+				goto free_partial_kdata;</div><div class='add'>+</div><div class='ctx'> 			ret = amdgpu_cs_p1_bo_handles(p, p-&gt;chunks[i].kdata);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				goto free_partial_kdata;</div><div class='hunk'>@@ -282,16 +274,36 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!p-&gt;gang_size) {</div><div class='add'>+	if (!p-&gt;gang_size || (amdgpu_sriov_vf(p-&gt;adev) &amp;&amp; p-&gt;gang_size &gt; 1)) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto free_all_kdata;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;gang_size; ++i) {</div><div class='ctx'> 		ret = amdgpu_job_alloc(p-&gt;adev, vm, p-&gt;entities[i], vm,</div><div class='del'>-				       num_ibs[i], &amp;p-&gt;jobs[i]);</div><div class='add'>+				       num_ibs[i], &amp;p-&gt;jobs[i],</div><div class='add'>+				       p-&gt;filp-&gt;client_id);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto free_all_kdata;</div><div class='add'>+		switch (p-&gt;adev-&gt;enforce_isolation[fpriv-&gt;xcp_id]) {</div><div class='add'>+		case AMDGPU_ENFORCE_ISOLATION_DISABLE:</div><div class='add'>+		default:</div><div class='add'>+			p-&gt;jobs[i]-&gt;enforce_isolation = false;</div><div class='add'>+			p-&gt;jobs[i]-&gt;run_cleaner_shader = false;</div><div class='add'>+			break;</div><div class='add'>+		case AMDGPU_ENFORCE_ISOLATION_ENABLE:</div><div class='add'>+			p-&gt;jobs[i]-&gt;enforce_isolation = true;</div><div class='add'>+			p-&gt;jobs[i]-&gt;run_cleaner_shader = true;</div><div class='add'>+			break;</div><div class='add'>+		case AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY:</div><div class='add'>+			p-&gt;jobs[i]-&gt;enforce_isolation = true;</div><div class='add'>+			p-&gt;jobs[i]-&gt;run_cleaner_shader = false;</div><div class='add'>+			break;</div><div class='add'>+		case AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER:</div><div class='add'>+			p-&gt;jobs[i]-&gt;enforce_isolation = true;</div><div class='add'>+			p-&gt;jobs[i]-&gt;run_cleaner_shader = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	p-&gt;gang_leader = p-&gt;jobs[p-&gt;gang_leader_idx];</div><div class='ctx'> </div><div class='hunk'>@@ -344,10 +356,20 @@ static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	ring = amdgpu_job_ring(job);</div><div class='ctx'> 	ib = &amp;job-&gt;ibs[job-&gt;num_ibs++];</div><div class='ctx'> </div><div class='add'>+	/* submissions to kernel queues are disabled */</div><div class='add'>+	if (ring-&gt;no_user_submission)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	/* MM engine doesn't support user fences */</div><div class='ctx'> 	if (p-&gt;uf_bo &amp;&amp; ring-&gt;funcs-&gt;no_user_fence)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!p-&gt;adev-&gt;debug_enable_ce_cs &amp;&amp;</div><div class='add'>+	    chunk_ib-&gt;flags &amp; AMDGPU_IB_FLAG_CE) {</div><div class='add'>+		dev_err_ratelimited(p-&gt;adev-&gt;dev, "CE CS is blocked, use debug=0x400 to override\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (chunk_ib-&gt;ip_type == AMDGPU_HW_IP_GFX &amp;&amp;</div><div class='ctx'> 	    chunk_ib-&gt;flags &amp; AMDGPU_IB_FLAG_PREEMPT) {</div><div class='ctx'> 		if (chunk_ib-&gt;flags &amp; AMDGPU_IB_FLAG_CE)</div><div class='hunk'>@@ -368,7 +390,7 @@ static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,</div><div class='ctx'> 			   chunk_ib-&gt;ib_bytes : 0,</div><div class='ctx'> 			   AMDGPU_IB_POOL_DELAYED, ib);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to get ib !\n");</div><div class='add'>+		drm_err(adev_to_drm(p-&gt;adev), "Failed to get ib !\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -423,7 +445,7 @@ static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,</div><div class='ctx'> 			dma_fence_put(old);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_sync_fence(&amp;p-&gt;sync, fence);</div><div class='add'>+		r = amdgpu_sync_fence(&amp;p-&gt;sync, fence, GFP_KERNEL);</div><div class='ctx'> 		dma_fence_put(fence);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='hunk'>@@ -440,12 +462,12 @@ static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,</div><div class='ctx'> </div><div class='ctx'> 	r = drm_syncobj_find_fence(p-&gt;filp, handle, point, flags, &amp;fence);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",</div><div class='add'>+		drm_err(adev_to_drm(p-&gt;adev), "syncobj %u failed to find fence @ %llu (%d)!\n",</div><div class='ctx'> 			  handle, point, r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_sync_fence(&amp;p-&gt;sync, fence);</div><div class='add'>+	r = amdgpu_sync_fence(&amp;p-&gt;sync, fence, GFP_KERNEL);</div><div class='ctx'> 	dma_fence_put(fence);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -686,7 +708,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,</div><div class='ctx'> 	 */</div><div class='ctx'> 	const s64 us_upper_bound = 200000;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;mm_stats.log2_max_MBps) {</div><div class='add'>+	if ((!adev-&gt;mm_stats.log2_max_MBps) || !ttm_resource_manager_used(&amp;adev-&gt;mman.vram_mgr.manager)) {</div><div class='ctx'> 		*max_bytes = 0;</div><div class='ctx'> 		*max_vis_bytes = 0;</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -819,7 +841,7 @@ retry:</div><div class='ctx'> </div><div class='ctx'> 	p-&gt;bytes_moved += ctx.bytes_moved;</div><div class='ctx'> 	if (!amdgpu_gmc_vram_full_visible(&amp;adev-&gt;gmc) &amp;&amp;</div><div class='del'>-	    amdgpu_bo_in_cpu_visible_vram(bo))</div><div class='add'>+	    amdgpu_res_cpu_visible(adev, bo-&gt;tbo.resource))</div><div class='ctx'> 		p-&gt;bytes_moved_vis += ctx.bytes_moved;</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(r == -ENOMEM) &amp;&amp; domain != bo-&gt;allowed_domains) {</div><div class='hunk'>@@ -868,26 +890,18 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	amdgpu_bo_list_for_each_userptr_entry(e, p-&gt;bo_list) {</div><div class='ctx'> 		bool userpage_invalidated = false;</div><div class='ctx'> 		struct amdgpu_bo *bo = e-&gt;bo;</div><div class='del'>-		int i;</div><div class='del'>-</div><div class='del'>-		e-&gt;user_pages = kvcalloc(bo-&gt;tbo.ttm-&gt;num_pages,</div><div class='del'>-					 sizeof(struct page *),</div><div class='del'>-					 GFP_KERNEL);</div><div class='del'>-		if (!e-&gt;user_pages) {</div><div class='del'>-			DRM_ERROR("kvmalloc_array failure\n");</div><div class='del'>-			r = -ENOMEM;</div><div class='del'>-			goto out_free_user_pages;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ttm_tt_get_user_pages(bo, e-&gt;user_pages, &amp;e-&gt;range);</div><div class='del'>-		if (r) {</div><div class='del'>-			kvfree(e-&gt;user_pages);</div><div class='del'>-			e-&gt;user_pages = NULL;</div><div class='add'>+		e-&gt;range = amdgpu_hmm_range_alloc(NULL);</div><div class='add'>+		if (unlikely(!e-&gt;range))</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_ttm_tt_get_user_pages(bo, e-&gt;range);</div><div class='add'>+		if (r)</div><div class='ctx'> 			goto out_free_user_pages;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; bo-&gt;tbo.ttm-&gt;num_pages; i++) {</div><div class='del'>-			if (bo-&gt;tbo.ttm-&gt;pages[i] != e-&gt;user_pages[i]) {</div><div class='add'>+			if (bo-&gt;tbo.ttm-&gt;pages[i] !=</div><div class='add'>+				hmm_pfn_to_page(e-&gt;range-&gt;hmm_range.hmm_pfns[i])) {</div><div class='ctx'> 				userpage_invalidated = true;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -931,7 +945,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_ttm_tt_is_userptr(e-&gt;bo-&gt;tbo.ttm) &amp;&amp;</div><div class='del'>-		    e-&gt;user_invalidated &amp;&amp; e-&gt;user_pages) {</div><div class='add'>+		    e-&gt;user_invalidated) {</div><div class='ctx'> 			amdgpu_bo_placement_from_domain(e-&gt;bo,</div><div class='ctx'> 							AMDGPU_GEM_DOMAIN_CPU);</div><div class='ctx'> 			r = ttm_bo_validate(&amp;e-&gt;bo-&gt;tbo, &amp;e-&gt;bo-&gt;placement,</div><div class='hunk'>@@ -940,11 +954,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,</div><div class='ctx'> 				goto out_free_user_pages;</div><div class='ctx'> </div><div class='ctx'> 			amdgpu_ttm_tt_set_user_pages(e-&gt;bo-&gt;tbo.ttm,</div><div class='del'>-						     e-&gt;user_pages);</div><div class='add'>+						     e-&gt;range);</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		kvfree(e-&gt;user_pages);</div><div class='del'>-		e-&gt;user_pages = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_cs_get_threshold_for_moves(p-&gt;adev, &amp;p-&gt;bytes_moved_threshold,</div><div class='hunk'>@@ -955,7 +966,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	r = amdgpu_vm_validate(p-&gt;adev, &amp;fpriv-&gt;vm, NULL,</div><div class='ctx'> 			       amdgpu_cs_bo_validate, p);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("amdgpu_vm_validate() failed.\n");</div><div class='add'>+		drm_err(adev_to_drm(p-&gt;adev), "amdgpu_vm_validate() failed.\n");</div><div class='ctx'> 		goto out_free_user_pages;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -984,13 +995,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,</div><div class='ctx'> </div><div class='ctx'> out_free_user_pages:</div><div class='ctx'> 	amdgpu_bo_list_for_each_userptr_entry(e, p-&gt;bo_list) {</div><div class='del'>-		struct amdgpu_bo *bo = e-&gt;bo;</div><div class='del'>-</div><div class='del'>-		if (!e-&gt;user_pages)</div><div class='del'>-			continue;</div><div class='del'>-		amdgpu_ttm_tt_get_user_pages_done(bo-&gt;tbo.ttm, e-&gt;range);</div><div class='del'>-		kvfree(e-&gt;user_pages);</div><div class='del'>-		e-&gt;user_pages = NULL;</div><div class='add'>+		amdgpu_hmm_range_free(e-&gt;range);</div><div class='ctx'> 		e-&gt;range = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;bo_list-&gt;bo_list_mutex);</div><div class='hunk'>@@ -1033,13 +1038,13 @@ static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		va_start = ib-&gt;gpu_addr &amp; AMDGPU_GMC_HOLE_MASK;</div><div class='ctx'> 		r = amdgpu_cs_find_mapping(p, va_start, &amp;aobj, &amp;m);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("IB va_start is invalid\n");</div><div class='add'>+			drm_err(adev_to_drm(p-&gt;adev), "IB va_start is invalid\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if ((va_start + ib-&gt;length_dw * 4) &gt;</div><div class='ctx'> 		    (m-&gt;last + 1) * AMDGPU_GPU_PAGE_SIZE) {</div><div class='del'>-			DRM_ERROR("IB va_start+ib_bytes is invalid\n");</div><div class='add'>+			drm_err(adev_to_drm(p-&gt;adev), "IB va_start+ib_bytes is invalid\n");</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1057,6 +1062,9 @@ static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,</div><div class='ctx'> 			r = amdgpu_ring_parse_cs(ring, p, job, ib);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='add'>+</div><div class='add'>+			if (ib-&gt;sa_bo)</div><div class='add'>+				ib-&gt;gpu_addr =  amdgpu_sa_bo_gpu_addr(ib-&gt;sa_bo);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			ib-&gt;ptr = (uint32_t *)kptr;</div><div class='ctx'> 			r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);</div><div class='hunk'>@@ -1093,6 +1101,24 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * We can't use gang submit on with reserved VMIDs when the VM changes</div><div class='add'>+	 * can't be invalidated by more than one engine at the same time.</div><div class='add'>+	 */</div><div class='add'>+	if (p-&gt;gang_size &gt; 1 &amp;&amp; !adev-&gt;vm_manager.concurrent_flush) {</div><div class='add'>+		for (i = 0; i &lt; p-&gt;gang_size; ++i) {</div><div class='add'>+			struct drm_sched_entity *entity = p-&gt;entities[i];</div><div class='add'>+			struct drm_gpu_scheduler *sched = entity-&gt;rq-&gt;sched;</div><div class='add'>+			struct amdgpu_ring *ring = to_amdgpu_ring(sched);</div><div class='add'>+</div><div class='add'>+			if (amdgpu_vmid_uses_reserved(vm, ring-&gt;vm_hub))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_vm_ready(vm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_vm_clear_freed(adev, vm, NULL);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -1101,7 +1127,8 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_sync_fence(&amp;p-&gt;sync, fpriv-&gt;prt_va-&gt;last_pt_update);</div><div class='add'>+	r = amdgpu_sync_fence(&amp;p-&gt;sync, fpriv-&gt;prt_va-&gt;last_pt_update,</div><div class='add'>+			      GFP_KERNEL);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -1112,7 +1139,8 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_sync_fence(&amp;p-&gt;sync, bo_va-&gt;last_pt_update);</div><div class='add'>+		r = amdgpu_sync_fence(&amp;p-&gt;sync, bo_va-&gt;last_pt_update,</div><div class='add'>+				      GFP_KERNEL);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1131,7 +1159,8 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_sync_fence(&amp;p-&gt;sync, bo_va-&gt;last_pt_update);</div><div class='add'>+		r = amdgpu_sync_fence(&amp;p-&gt;sync, bo_va-&gt;last_pt_update,</div><div class='add'>+				      GFP_KERNEL);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1144,7 +1173,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_sync_fence(&amp;p-&gt;sync, vm-&gt;last_update);</div><div class='add'>+	r = amdgpu_sync_fence(&amp;p-&gt;sync, vm-&gt;last_update, GFP_KERNEL);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -1166,7 +1195,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)</div><div class='ctx'> 			if (!bo)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			amdgpu_vm_bo_invalidate(adev, bo, false);</div><div class='add'>+			amdgpu_vm_bo_invalidate(bo, false);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1186,7 +1215,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)</div><div class='ctx'> 	r = amdgpu_ctx_wait_prev_fence(p-&gt;ctx, p-&gt;entities[p-&gt;gang_leader_idx]);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		if (r != -ERESTARTSYS)</div><div class='del'>-			DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");</div><div class='add'>+			drm_err(adev_to_drm(p-&gt;adev), "amdgpu_ctx_wait_prev_fence failed.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1225,7 +1254,8 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_sync_fence(&amp;p-&gt;gang_leader-&gt;explicit_sync, fence);</div><div class='add'>+		r = amdgpu_sync_fence(&amp;p-&gt;gang_leader-&gt;explicit_sync, fence,</div><div class='add'>+				      GFP_KERNEL);</div><div class='ctx'> 		dma_fence_put(fence);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='hunk'>@@ -1296,8 +1326,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	 */</div><div class='ctx'> 	r = 0;</div><div class='ctx'> 	amdgpu_bo_list_for_each_userptr_entry(e, p-&gt;bo_list) {</div><div class='del'>-		r |= !amdgpu_ttm_tt_get_user_pages_done(e-&gt;bo-&gt;tbo.ttm,</div><div class='del'>-							e-&gt;range);</div><div class='add'>+		r |= !amdgpu_hmm_range_valid(e-&gt;range);</div><div class='add'>+		amdgpu_hmm_range_free(e-&gt;range);</div><div class='ctx'> 		e-&gt;range = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (r) {</div><div class='hunk'>@@ -1398,7 +1428,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_cs_parser_init(&amp;parser, adev, filp, data);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR_RATELIMITED("Failed to initialize parser %d!\n", r);</div><div class='add'>+		drm_err_ratelimited(dev, "Failed to initialize parser %d!\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1413,9 +1443,9 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 	r = amdgpu_cs_parser_bos(&amp;parser, data);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		if (r == -ENOMEM)</div><div class='del'>-			DRM_ERROR("Not enough memory for command submission!\n");</div><div class='add'>+			drm_err(dev, "Not enough memory for command submission!\n");</div><div class='ctx'> 		else if (r != -ERESTARTSYS &amp;&amp; r != -EAGAIN)</div><div class='del'>-			DRM_DEBUG("Failed to process the buffer list %d!\n", r);</div><div class='add'>+			drm_dbg(dev, "Failed to process the buffer list %d!\n", r);</div><div class='ctx'> 		goto error_fini;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1714,30 +1744,21 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	union drm_amdgpu_wait_fences *wait = data;</div><div class='del'>-	uint32_t fence_count = wait-&gt;in.fence_count;</div><div class='del'>-	struct drm_amdgpu_fence *fences_user;</div><div class='ctx'> 	struct drm_amdgpu_fence *fences;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	/* Get the fences from userspace */</div><div class='del'>-	fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),</div><div class='del'>-			GFP_KERNEL);</div><div class='del'>-	if (fences == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	fences_user = u64_to_user_ptr(wait-&gt;in.fences);</div><div class='del'>-	if (copy_from_user(fences, fences_user,</div><div class='del'>-		sizeof(struct drm_amdgpu_fence) * fence_count)) {</div><div class='del'>-		r = -EFAULT;</div><div class='del'>-		goto err_free_fences;</div><div class='del'>-	}</div><div class='add'>+	fences = memdup_array_user(u64_to_user_ptr(wait-&gt;in.fences),</div><div class='add'>+				   wait-&gt;in.fence_count,</div><div class='add'>+				   sizeof(struct drm_amdgpu_fence));</div><div class='add'>+	if (IS_ERR(fences))</div><div class='add'>+		return PTR_ERR(fences);</div><div class='ctx'> </div><div class='ctx'> 	if (wait-&gt;in.wait_all)</div><div class='ctx'> 		r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);</div><div class='ctx'> 	else</div><div class='ctx'> 		r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);</div><div class='ctx'> </div><div class='del'>-err_free_fences:</div><div class='ctx'> 	kfree(fences);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1763,7 +1784,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,</div><div class='ctx'> 	struct ttm_operation_ctx ctx = { false, false };</div><div class='ctx'> 	struct amdgpu_vm *vm = &amp;fpriv-&gt;vm;</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *mapping;</div><div class='del'>-	int r;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	addr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> </div><div class='hunk'>@@ -1778,9 +1799,14 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,</div><div class='ctx'> 	if (dma_resv_locking_ctx((*bo)-&gt;tbo.base.resv) != &amp;parser-&gt;exec.ticket)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (!((*bo)-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {</div><div class='del'>-		(*bo)-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='add'>+	/* Make sure VRAM is allocated contigiously */</div><div class='add'>+	(*bo)-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='add'>+	if ((*bo)-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM &amp;&amp;</div><div class='add'>+	    !((*bo)-&gt;tbo.resource-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS)) {</div><div class='add'>+</div><div class='ctx'> 		amdgpu_bo_placement_from_domain(*bo, (*bo)-&gt;allowed_domains);</div><div class='add'>+		for (i = 0; i &lt; (*bo)-&gt;placement.num_placement; i++)</div><div class='add'>+			(*bo)-&gt;placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;</div><div class='ctx'> 		r = ttm_bo_validate(&amp;(*bo)-&gt;tbo, &amp;(*bo)-&gt;placement, &amp;ctx);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c<br/>index cfdf558b48b6..02138aa55793 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c</a></div><div class='hunk'>@@ -109,7 +109,7 @@ int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='ctx'> 		if (likely(!r))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c<br/>index 5cb33ac99f70..afedea02188d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c</a></div><div class='hunk'>@@ -236,7 +236,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,</div><div class='ctx'> 		r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv,</div><div class='ctx'> 						&amp;num_scheds, &amp;scheds);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto cleanup_entity;</div><div class='add'>+			goto error_free_entity;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* disable load balance if the hw engine retains context among dependent jobs */</div><div class='hunk'>@@ -685,16 +685,24 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> </div><div class='ctx'> 	switch (args-&gt;in.op) {</div><div class='ctx'> 	case AMDGPU_CTX_OP_ALLOC_CTX:</div><div class='add'>+		if (args-&gt;in.flags)</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &amp;id);</div><div class='ctx'> 		args-&gt;out.alloc.ctx_id = id;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_CTX_OP_FREE_CTX:</div><div class='add'>+		if (args-&gt;in.flags)</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		r = amdgpu_ctx_free(fpriv, id);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_CTX_OP_QUERY_STATE:</div><div class='add'>+		if (args-&gt;in.flags)</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		r = amdgpu_ctx_query(adev, fpriv, id, &amp;args-&gt;out);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_CTX_OP_QUERY_STATE2:</div><div class='add'>+		if (args-&gt;in.flags)</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		r = amdgpu_ctx_query2(adev, fpriv, id, &amp;args-&gt;out);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_CTX_OP_GET_STABLE_PSTATE:</div><div class='hunk'>@@ -911,7 +919,7 @@ long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout)</div><div class='ctx'> 	return timeout;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)</div><div class='add'>+static void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ctx *ctx;</div><div class='ctx'> 	struct idr *idp;</div><div class='hunk'>@@ -936,24 +944,13 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)</div><div class='ctx'> 				drm_sched_entity_fini(entity);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+		kref_put(&amp;ctx-&gt;refcount, amdgpu_ctx_fini);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ctx *ctx;</div><div class='del'>-	struct idr *idp;</div><div class='del'>-	uint32_t id;</div><div class='del'>-</div><div class='ctx'> 	amdgpu_ctx_mgr_entity_fini(mgr);</div><div class='del'>-</div><div class='del'>-	idp = &amp;mgr-&gt;ctx_handles;</div><div class='del'>-</div><div class='del'>-	idr_for_each_entry(idp, ctx, id) {</div><div class='del'>-		if (kref_put(&amp;ctx-&gt;refcount, amdgpu_ctx_fini) != 1)</div><div class='del'>-			DRM_ERROR("ctx %p is still alive\n", ctx);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	idr_destroy(&amp;mgr-&gt;ctx_handles);</div><div class='ctx'> 	mutex_destroy(&amp;mgr-&gt;lock);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h<br/>index 85376baaa92f..090dfe86f75b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h</a></div><div class='hunk'>@@ -92,7 +92,6 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr,</div><div class='ctx'> 			 struct amdgpu_device *adev);</div><div class='del'>-void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);</div><div class='ctx'> long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);</div><div class='ctx'> void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);</div><div class='ctx'> void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c<br/>index f5d0fa207a88..62d43b8cbe58 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c</a></div><div class='hunk'>@@ -129,7 +129,6 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,</div><div class='ctx'> 	if (use_bank) {</div><div class='ctx'> 		if ((sh_bank != 0xFFFFFFFF &amp;&amp; sh_bank &gt;= adev-&gt;gfx.config.max_sh_per_se) ||</div><div class='ctx'> 		    (se_bank != 0xFFFFFFFF &amp;&amp; se_bank &gt;= adev-&gt;gfx.config.max_shader_engines)) {</div><div class='del'>-			pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 			pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 			amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -179,7 +178,6 @@ end:</div><div class='ctx'> 	if (pm_pg_lock)</div><div class='ctx'> 		mutex_unlock(&amp;adev-&gt;pm.mutex);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='hunk'>@@ -255,7 +253,6 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 off</div><div class='ctx'> 	if (rd-&gt;id.use_grbm) {</div><div class='ctx'> 		if ((rd-&gt;id.grbm.sh != 0xFFFFFFFF &amp;&amp; rd-&gt;id.grbm.sh &gt;= adev-&gt;gfx.config.max_sh_per_se) ||</div><div class='ctx'> 		    (rd-&gt;id.grbm.se != 0xFFFFFFFF &amp;&amp; rd-&gt;id.grbm.se &gt;= adev-&gt;gfx.config.max_shader_engines)) {</div><div class='del'>-			pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 			pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 			amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 			mutex_unlock(&amp;rd-&gt;lock);</div><div class='hunk'>@@ -310,7 +307,6 @@ end:</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;rd-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='hunk'>@@ -402,7 +398,7 @@ static ssize_t amdgpu_debugfs_gprwave_read(struct file *f, char __user *buf, siz</div><div class='ctx'> 	int r;</div><div class='ctx'> 	uint32_t *data, x;</div><div class='ctx'> </div><div class='del'>-	if (size &amp; 0x3 || *pos &amp; 0x3)</div><div class='add'>+	if (size &gt; 4096 || size &amp; 0x3 || *pos &amp; 0x3)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	r = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='hunk'>@@ -446,7 +442,6 @@ static ssize_t amdgpu_debugfs_gprwave_read(struct file *f, char __user *buf, siz</div><div class='ctx'> 	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, rd-&gt;id.xcc_id);</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (!x) {</div><div class='hunk'>@@ -557,7 +552,6 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -617,7 +611,6 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -676,7 +669,6 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -736,7 +728,6 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -795,7 +786,6 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -855,7 +845,6 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	amdgpu_virt_disable_access_debugfs(adev);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -918,7 +907,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	/* rev==1 */</div><div class='ctx'> 	config[no_regs++] = adev-&gt;rev_id;</div><div class='del'>-	config[no_regs++] = lower_32_bits(adev-&gt;pg_flags);</div><div class='add'>+	config[no_regs++] = adev-&gt;pg_flags;</div><div class='ctx'> 	config[no_regs++] = lower_32_bits(adev-&gt;cg_flags);</div><div class='ctx'> </div><div class='ctx'> 	/* rev==2 */</div><div class='hunk'>@@ -935,7 +924,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,</div><div class='ctx'> 	config[no_regs++] = adev-&gt;flags &amp; AMD_IS_APU ? 1 : 0;</div><div class='ctx'> </div><div class='ctx'> 	/* rev==5 PG/CG flag upper 32bit */</div><div class='del'>-	config[no_regs++] = upper_32_bits(adev-&gt;pg_flags);</div><div class='add'>+	config[no_regs++] = 0;</div><div class='ctx'> 	config[no_regs++] = upper_32_bits(adev-&gt;cg_flags);</div><div class='ctx'> </div><div class='ctx'> 	while (size &amp;&amp; (*pos &lt; no_regs * 4)) {</div><div class='hunk'>@@ -1003,7 +992,6 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_dpm_read_sensor(adev, idx, &amp;values[0], &amp;valuesize);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (r) {</div><div class='hunk'>@@ -1094,7 +1082,6 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,</div><div class='ctx'> 	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (!x) {</div><div class='hunk'>@@ -1192,7 +1179,6 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,</div><div class='ctx'> 	amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='hunk'>@@ -1266,7 +1252,6 @@ static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char __user</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1315,7 +1300,6 @@ static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const char</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1365,7 +1349,6 @@ static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user *buf</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1414,7 +1397,6 @@ static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *bu</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1460,7 +1442,6 @@ static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1501,7 +1482,6 @@ static ssize_t amdgpu_debugfs_gfxoff_status_read(struct file *f, char __user *bu</div><div class='ctx'> </div><div class='ctx'> 	r = result;</div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1648,7 +1628,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(debugfs_regs); i++) {</div><div class='ctx'> 		ent = debugfs_create_file(debugfs_regs_names[i],</div><div class='del'>-					  S_IFREG | 0444, root,</div><div class='add'>+					  S_IFREG | 0400, root,</div><div class='ctx'> 					  adev, debugfs_regs[i]);</div><div class='ctx'> 		if (!i &amp;&amp; !IS_ERR_OR_NULL(ent))</div><div class='ctx'> 			i_size_write(ent-&gt;d_inode, adev-&gt;rmmio_size);</div><div class='hunk'>@@ -1701,7 +1681,6 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)</div><div class='ctx'> </div><div class='ctx'> 	up_write(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1721,7 +1700,6 @@ static int amdgpu_debugfs_evict_vram(void *data, u64 *val)</div><div class='ctx'> </div><div class='ctx'> 	*val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1742,7 +1720,6 @@ static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)</div><div class='ctx'> </div><div class='ctx'> 	*val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1762,7 +1739,6 @@ static int amdgpu_debugfs_benchmark(void *data, u64 val)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_benchmark(adev, val);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1786,7 +1762,7 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)</div><div class='ctx'> </div><div class='ctx'> 		ti = amdgpu_vm_get_task_info_vm(vm);</div><div class='ctx'> 		if (ti) {</div><div class='del'>-			seq_printf(m, "pid:%d\tProcess:%s ----------\n", ti-&gt;pid, ti-&gt;process_name);</div><div class='add'>+			seq_printf(m, "pid:%d\tProcess:%s ----------\n", ti-&gt;task.pid, ti-&gt;process_name);</div><div class='ctx'> 			amdgpu_vm_put_task_info(ti);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1902,7 +1878,7 @@ no_preempt:</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> 		job = to_amdgpu_job(s_job);</div><div class='del'>-		if (preempted &amp;&amp; (&amp;job-&gt;hw_fence) == fence)</div><div class='add'>+		if (preempted &amp;&amp; (&amp;job-&gt;hw_fence-&gt;base) == fence)</div><div class='ctx'> 			/* mark the job as preempted */</div><div class='ctx'> 			job-&gt;preemption_status |= AMDGPU_IB_PREEMPTED;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1990,7 +1966,7 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val)</div><div class='ctx'> 	uint32_t max_freq, min_freq;</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev) &amp;&amp; !amdgpu_sriov_is_pp_one_vf(adev))</div><div class='add'>+	if (amdgpu_sriov_multi_vf_mode(adev))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	ret = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='hunk'>@@ -2014,7 +1990,6 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val)</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -2026,99 +2001,6 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,</div><div class='ctx'> DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,</div><div class='ctx'> 			amdgpu_debugfs_sclk_set, "%llu\n");</div><div class='ctx'> </div><div class='del'>-static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,</div><div class='del'>-				char __user *buf, size_t size, loff_t *pos)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)-&gt;i_private;</div><div class='del'>-	char reg_offset[12];</div><div class='del'>-	int i, ret, len = 0;</div><div class='del'>-</div><div class='del'>-	if (*pos)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	memset(reg_offset, 0, 12);</div><div class='del'>-	ret = down_read_killable(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;reset_info.num_regs; i++) {</div><div class='del'>-		sprintf(reg_offset, "0x%x\n", adev-&gt;reset_info.reset_dump_reg_list[i]);</div><div class='del'>-		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-		if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))</div><div class='del'>-			return -EFAULT;</div><div class='del'>-</div><div class='del'>-		len += strlen(reg_offset);</div><div class='del'>-		ret = down_read_killable(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-	*pos += len;</div><div class='del'>-</div><div class='del'>-	return len;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,</div><div class='del'>-			const char __user *buf, size_t size, loff_t *pos)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)-&gt;i_private;</div><div class='del'>-	char reg_offset[11];</div><div class='del'>-	uint32_t *new = NULL, *tmp = NULL;</div><div class='del'>-	int ret, i = 0, len = 0;</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-		memset(reg_offset, 0, 11);</div><div class='del'>-		if (copy_from_user(reg_offset, buf + len,</div><div class='del'>-					min(10, ((int)size-len)))) {</div><div class='del'>-			ret = -EFAULT;</div><div class='del'>-			goto error_free;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		new = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);</div><div class='del'>-		if (!new) {</div><div class='del'>-			ret = -ENOMEM;</div><div class='del'>-			goto error_free;</div><div class='del'>-		}</div><div class='del'>-		tmp = new;</div><div class='del'>-		if (sscanf(reg_offset, "%X %n", &amp;tmp[i], &amp;ret) != 1) {</div><div class='del'>-			ret = -EINVAL;</div><div class='del'>-			goto error_free;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		len += ret;</div><div class='del'>-		i++;</div><div class='del'>-	} while (len &lt; size);</div><div class='del'>-</div><div class='del'>-	new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);</div><div class='del'>-	if (!new) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto error_free;</div><div class='del'>-	}</div><div class='del'>-	ret = down_write_killable(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error_free;</div><div class='del'>-</div><div class='del'>-	swap(adev-&gt;reset_info.reset_dump_reg_list, tmp);</div><div class='del'>-	swap(adev-&gt;reset_info.reset_dump_reg_value, new);</div><div class='del'>-	adev-&gt;reset_info.num_regs = i;</div><div class='del'>-	up_write(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-	ret = size;</div><div class='del'>-</div><div class='del'>-error_free:</div><div class='del'>-	if (tmp != new)</div><div class='del'>-		kfree(tmp);</div><div class='del'>-	kfree(new);</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct file_operations amdgpu_reset_dump_register_list = {</div><div class='del'>-	.owner = THIS_MODULE,</div><div class='del'>-	.read = amdgpu_reset_dump_register_list_read,</div><div class='del'>-	.write = amdgpu_reset_dump_register_list_write,</div><div class='del'>-	.llseek = default_llseek</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> int amdgpu_debugfs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dentry *root = adev_to_drm(adev)-&gt;primary-&gt;debugfs_root;</div><div class='hunk'>@@ -2185,37 +2067,99 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_debugfs_vcn_fwlog_init(adev, i, &amp;adev-&gt;vcn.inst[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_umsch_mm &amp; amdgpu_umsch_mm_fwlog)</div><div class='add'>+		amdgpu_debugfs_umsch_fwlog_init(adev, &amp;adev-&gt;umsch_mm);</div><div class='add'>+</div><div class='add'>+	amdgpu_debugfs_vcn_sched_mask_init(adev);</div><div class='add'>+	amdgpu_debugfs_jpeg_sched_mask_init(adev);</div><div class='add'>+	amdgpu_debugfs_gfx_sched_mask_init(adev);</div><div class='add'>+	amdgpu_debugfs_compute_sched_mask_init(adev);</div><div class='add'>+	amdgpu_debugfs_sdma_sched_mask_init(adev);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ras_debugfs_create_all(adev);</div><div class='ctx'> 	amdgpu_rap_debugfs_init(adev);</div><div class='ctx'> 	amdgpu_securedisplay_debugfs_init(adev);</div><div class='ctx'> 	amdgpu_fw_attestation_debugfs_init(adev);</div><div class='add'>+	amdgpu_psp_debugfs_init(adev);</div><div class='ctx'> </div><div class='del'>-	debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,</div><div class='add'>+	debugfs_create_file("amdgpu_evict_vram", 0400, root, adev,</div><div class='ctx'> 			    &amp;amdgpu_evict_vram_fops);</div><div class='del'>-	debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,</div><div class='add'>+	debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev,</div><div class='ctx'> 			    &amp;amdgpu_evict_gtt_fops);</div><div class='del'>-	debugfs_create_file("amdgpu_test_ib", 0444, root, adev,</div><div class='add'>+	debugfs_create_file("amdgpu_test_ib", 0400, root, adev,</div><div class='ctx'> 			    &amp;amdgpu_debugfs_test_ib_fops);</div><div class='ctx'> 	debugfs_create_file("amdgpu_vm_info", 0444, root, adev,</div><div class='ctx'> 			    &amp;amdgpu_debugfs_vm_info_fops);</div><div class='ctx'> 	debugfs_create_file("amdgpu_benchmark", 0200, root, adev,</div><div class='ctx'> 			    &amp;amdgpu_benchmark_fops);</div><div class='del'>-	debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,</div><div class='del'>-			    &amp;amdgpu_reset_dump_register_list);</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;debugfs_vbios_blob.data = adev-&gt;bios;</div><div class='ctx'> 	adev-&gt;debugfs_vbios_blob.size = adev-&gt;bios_size;</div><div class='ctx'> 	debugfs_create_blob("amdgpu_vbios", 0444, root,</div><div class='ctx'> 			    &amp;adev-&gt;debugfs_vbios_blob);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;debugfs_discovery_blob.data = adev-&gt;mman.discovery_bin;</div><div class='del'>-	adev-&gt;debugfs_discovery_blob.size = adev-&gt;mman.discovery_tmr_size;</div><div class='del'>-	debugfs_create_blob("amdgpu_discovery", 0444, root,</div><div class='del'>-			    &amp;adev-&gt;debugfs_discovery_blob);</div><div class='add'>+	if (adev-&gt;discovery.debugfs_blob.size)</div><div class='add'>+		debugfs_create_blob("amdgpu_discovery", 0444, root,</div><div class='add'>+				    &amp;adev-&gt;discovery.debugfs_blob);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_pt_info_read(struct seq_file *m, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct drm_file *file;</div><div class='add'>+	struct amdgpu_fpriv *fpriv;</div><div class='add'>+	struct amdgpu_bo *root_bo;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	file = m-&gt;private;</div><div class='add'>+	if (!file)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	adev = drm_to_adev(file-&gt;minor-&gt;dev);</div><div class='add'>+	fpriv = file-&gt;driver_priv;</div><div class='add'>+	if (!fpriv || !fpriv-&gt;vm.root.bo)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	root_bo = amdgpu_bo_ref(fpriv-&gt;vm.root.bo);</div><div class='add'>+	r = amdgpu_bo_reserve(root_bo, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		amdgpu_bo_unref(&amp;root_bo);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	seq_printf(m, "pd_address: 0x%llx\n", amdgpu_gmc_pd_addr(fpriv-&gt;vm.root.bo));</div><div class='add'>+	seq_printf(m, "max_pfn: 0x%llx\n", adev-&gt;vm_manager.max_pfn);</div><div class='add'>+	seq_printf(m, "num_level: 0x%x\n", adev-&gt;vm_manager.num_level);</div><div class='add'>+	seq_printf(m, "block_size: 0x%x\n", adev-&gt;vm_manager.block_size);</div><div class='add'>+	seq_printf(m, "fragment_size: 0x%x\n", adev-&gt;vm_manager.fragment_size);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(root_bo);</div><div class='add'>+	amdgpu_bo_unref(&amp;root_bo);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_pt_info_open(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	return single_open(file, amdgpu_pt_info_read, inode-&gt;i_private);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations amdgpu_pt_info_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = amdgpu_pt_info_open,</div><div class='add'>+	.read = seq_read,</div><div class='add'>+	.llseek = seq_lseek,</div><div class='add'>+	.release = single_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_vm_init(struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	debugfs_create_file("vm_pagetable_info", 0444, file-&gt;debugfs_client, file,</div><div class='add'>+			    &amp;amdgpu_pt_info_fops);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #else</div><div class='ctx'> int amdgpu_debugfs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -2225,4 +2169,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+void amdgpu_debugfs_vm_init(struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+}</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h<br/>index 0425432d8659..e7b3c38e5186 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h</a></div><div class='hunk'>@@ -33,4 +33,5 @@ void amdgpu_debugfs_fence_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_debugfs_gem_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_debugfs_vm_init(struct drm_file *file);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c<br/>new file mode 100644<br/>index 000000000000..4e2fe6674db8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c</a></div><div class='hunk'>@@ -0,0 +1,371 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;generated/utsrelease.h&gt;</div><div class='add'>+#include &lt;linux/devcoredump.h&gt;</div><div class='add'>+#include "amdgpu_dev_coredump.h"</div><div class='add'>+#include "atom.h"</div><div class='add'>+</div><div class='add'>+#ifndef CONFIG_DEV_COREDUMP</div><div class='add'>+void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,</div><div class='add'>+		     bool vram_lost, struct amdgpu_job *job)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+</div><div class='add'>+const char *hw_ip_names[MAX_HWIP] = {</div><div class='add'>+	[GC_HWIP]		= "GC",</div><div class='add'>+	[HDP_HWIP]		= "HDP",</div><div class='add'>+	[SDMA0_HWIP]		= "SDMA0",</div><div class='add'>+	[SDMA1_HWIP]		= "SDMA1",</div><div class='add'>+	[SDMA2_HWIP]		= "SDMA2",</div><div class='add'>+	[SDMA3_HWIP]		= "SDMA3",</div><div class='add'>+	[SDMA4_HWIP]		= "SDMA4",</div><div class='add'>+	[SDMA5_HWIP]		= "SDMA5",</div><div class='add'>+	[SDMA6_HWIP]		= "SDMA6",</div><div class='add'>+	[SDMA7_HWIP]		= "SDMA7",</div><div class='add'>+	[LSDMA_HWIP]		= "LSDMA",</div><div class='add'>+	[MMHUB_HWIP]		= "MMHUB",</div><div class='add'>+	[ATHUB_HWIP]		= "ATHUB",</div><div class='add'>+	[NBIO_HWIP]		= "NBIO",</div><div class='add'>+	[MP0_HWIP]		= "MP0",</div><div class='add'>+	[MP1_HWIP]		= "MP1",</div><div class='add'>+	[UVD_HWIP]		= "UVD/JPEG/VCN",</div><div class='add'>+	[VCN1_HWIP]		= "VCN1",</div><div class='add'>+	[VCE_HWIP]		= "VCE",</div><div class='add'>+	[VPE_HWIP]		= "VPE",</div><div class='add'>+	[DF_HWIP]		= "DF",</div><div class='add'>+	[DCE_HWIP]		= "DCE",</div><div class='add'>+	[OSSSYS_HWIP]		= "OSSSYS",</div><div class='add'>+	[SMUIO_HWIP]		= "SMUIO",</div><div class='add'>+	[PWR_HWIP]		= "PWR",</div><div class='add'>+	[NBIF_HWIP]		= "NBIF",</div><div class='add'>+	[THM_HWIP]		= "THM",</div><div class='add'>+	[CLK_HWIP]		= "CLK",</div><div class='add'>+	[UMC_HWIP]		= "UMC",</div><div class='add'>+	[RSMU_HWIP]		= "RSMU",</div><div class='add'>+	[XGMI_HWIP]		= "XGMI",</div><div class='add'>+	[DCI_HWIP]		= "DCI",</div><div class='add'>+	[PCIE_HWIP]		= "PCIE",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev,</div><div class='add'>+				       struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	uint32_t version;</div><div class='add'>+	uint32_t feature;</div><div class='add'>+	uint8_t smu_program, smu_major, smu_minor, smu_debug;</div><div class='add'>+	struct atom_context *ctx = adev-&gt;mode_info.atom_context;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "VCE feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;vce.fb_version, adev-&gt;vce.fw_version);</div><div class='add'>+	drm_printf(p, "UVD feature version: %u, fw version: 0x%08x\n", 0,</div><div class='add'>+		   adev-&gt;uvd.fw_version);</div><div class='add'>+	drm_printf(p, "GMC feature version: %u, fw version: 0x%08x\n", 0,</div><div class='add'>+		   adev-&gt;gmc.fw_version);</div><div class='add'>+	drm_printf(p, "ME feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.me_feature_version, adev-&gt;gfx.me_fw_version);</div><div class='add'>+	drm_printf(p, "PFP feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.pfp_feature_version, adev-&gt;gfx.pfp_fw_version);</div><div class='add'>+	drm_printf(p, "CE feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.ce_feature_version, adev-&gt;gfx.ce_fw_version);</div><div class='add'>+	drm_printf(p, "RLC feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.rlc_feature_version, adev-&gt;gfx.rlc_fw_version);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "RLC SRLC feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.rlc_srlc_feature_version,</div><div class='add'>+		   adev-&gt;gfx.rlc_srlc_fw_version);</div><div class='add'>+	drm_printf(p, "RLC SRLG feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.rlc_srlg_feature_version,</div><div class='add'>+		   adev-&gt;gfx.rlc_srlg_fw_version);</div><div class='add'>+	drm_printf(p, "RLC SRLS feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.rlc_srls_feature_version,</div><div class='add'>+		   adev-&gt;gfx.rlc_srls_fw_version);</div><div class='add'>+	drm_printf(p, "RLCP feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.rlcp_ucode_feature_version,</div><div class='add'>+		   adev-&gt;gfx.rlcp_ucode_version);</div><div class='add'>+	drm_printf(p, "RLCV feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.rlcv_ucode_feature_version,</div><div class='add'>+		   adev-&gt;gfx.rlcv_ucode_version);</div><div class='add'>+	drm_printf(p, "MEC feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;gfx.mec_feature_version, adev-&gt;gfx.mec_fw_version);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.mec2_fw)</div><div class='add'>+		drm_printf(p, "MEC2 feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+			   adev-&gt;gfx.mec2_feature_version,</div><div class='add'>+			   adev-&gt;gfx.mec2_fw_version);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "IMU feature version: %u, fw version: 0x%08x\n", 0,</div><div class='add'>+		   adev-&gt;gfx.imu_fw_version);</div><div class='add'>+	drm_printf(p, "PSP SOS feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.sos.feature_version, adev-&gt;psp.sos.fw_version);</div><div class='add'>+	drm_printf(p, "PSP ASD feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.asd_context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.asd_context.bin_desc.fw_version);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "TA XGMI feature version: 0x%08x, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.xgmi_context.context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.xgmi_context.context.bin_desc.fw_version);</div><div class='add'>+	drm_printf(p, "TA RAS feature version: 0x%08x, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.ras_context.context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.ras_context.context.bin_desc.fw_version);</div><div class='add'>+	drm_printf(p, "TA HDCP feature version: 0x%08x, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.hdcp_context.context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.hdcp_context.context.bin_desc.fw_version);</div><div class='add'>+	drm_printf(p, "TA DTM feature version: 0x%08x, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.dtm_context.context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.dtm_context.context.bin_desc.fw_version);</div><div class='add'>+	drm_printf(p, "TA RAP feature version: 0x%08x, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.rap_context.context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.rap_context.context.bin_desc.fw_version);</div><div class='add'>+	drm_printf(p,</div><div class='add'>+		   "TA SECURE DISPLAY feature version: 0x%08x, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.securedisplay_context.context.bin_desc.feature_version,</div><div class='add'>+		   adev-&gt;psp.securedisplay_context.context.bin_desc.fw_version);</div><div class='add'>+</div><div class='add'>+	/* SMC firmware */</div><div class='add'>+	version = adev-&gt;pm.fw_version;</div><div class='add'>+</div><div class='add'>+	smu_program = (version &gt;&gt; 24) &amp; 0xff;</div><div class='add'>+	smu_major = (version &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	smu_minor = (version &gt;&gt; 8) &amp; 0xff;</div><div class='add'>+	smu_debug = (version &gt;&gt; 0) &amp; 0xff;</div><div class='add'>+	drm_printf(p,</div><div class='add'>+		   "SMC feature version: %u, program: %d, fw version: 0x%08x (%d.%d.%d)\n",</div><div class='add'>+		   0, smu_program, version, smu_major, smu_minor, smu_debug);</div><div class='add'>+</div><div class='add'>+	/* SDMA firmware */</div><div class='add'>+	for (int i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		drm_printf(p,</div><div class='add'>+			   "SDMA%d feature version: %u, firmware version: 0x%08x\n",</div><div class='add'>+			   i, adev-&gt;sdma.instance[i].feature_version,</div><div class='add'>+			   adev-&gt;sdma.instance[i].fw_version);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "VCN feature version: %u, fw version: 0x%08x\n", 0,</div><div class='add'>+		   adev-&gt;vcn.fw_version);</div><div class='add'>+	drm_printf(p, "DMCU feature version: %u, fw version: 0x%08x\n", 0,</div><div class='add'>+		   adev-&gt;dm.dmcu_fw_version);</div><div class='add'>+	drm_printf(p, "DMCUB feature version: %u, fw version: 0x%08x\n", 0,</div><div class='add'>+		   adev-&gt;dm.dmcub_fw_version);</div><div class='add'>+	drm_printf(p, "PSP TOC feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;psp.toc.feature_version, adev-&gt;psp.toc.fw_version);</div><div class='add'>+</div><div class='add'>+	version = adev-&gt;mes.kiq_version &amp; AMDGPU_MES_VERSION_MASK;</div><div class='add'>+	feature = (adev-&gt;mes.kiq_version &amp; AMDGPU_MES_FEAT_VERSION_MASK) &gt;&gt;</div><div class='add'>+		  AMDGPU_MES_FEAT_VERSION_SHIFT;</div><div class='add'>+	drm_printf(p, "MES_KIQ feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   feature, version);</div><div class='add'>+</div><div class='add'>+	version = adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK;</div><div class='add'>+	feature = (adev-&gt;mes.sched_version &amp; AMDGPU_MES_FEAT_VERSION_MASK) &gt;&gt;</div><div class='add'>+		  AMDGPU_MES_FEAT_VERSION_SHIFT;</div><div class='add'>+	drm_printf(p, "MES feature version: %u, fw version: 0x%08x\n", feature,</div><div class='add'>+		   version);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "VPE feature version: %u, fw version: 0x%08x\n",</div><div class='add'>+		   adev-&gt;vpe.feature_version, adev-&gt;vpe.fw_version);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nVBIOS Information\n");</div><div class='add'>+	drm_printf(p, "vbios name       : %s\n", ctx-&gt;name);</div><div class='add'>+	drm_printf(p, "vbios pn         : %s\n", ctx-&gt;vbios_pn);</div><div class='add'>+	drm_printf(p, "vbios version    : %d\n", ctx-&gt;version);</div><div class='add'>+	drm_printf(p, "vbios ver_str    : %s\n", ctx-&gt;vbios_ver_str);</div><div class='add'>+	drm_printf(p, "vbios date       : %s\n", ctx-&gt;date);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,</div><div class='add'>+			void *data, size_t datalen)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p;</div><div class='add'>+	struct amdgpu_coredump_info *coredump = data;</div><div class='add'>+	struct drm_print_iterator iter;</div><div class='add'>+	struct amdgpu_vm_fault_info *fault_info;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='add'>+	int ver;</div><div class='add'>+</div><div class='add'>+	iter.data = buffer;</div><div class='add'>+	iter.offset = 0;</div><div class='add'>+	iter.start = offset;</div><div class='add'>+	iter.remain = count;</div><div class='add'>+</div><div class='add'>+	p = drm_coredump_printer(&amp;iter);</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "**** AMDGPU Device Coredump ****\n");</div><div class='add'>+	drm_printf(&amp;p, "version: " AMDGPU_COREDUMP_VERSION "\n");</div><div class='add'>+	drm_printf(&amp;p, "kernel: " UTS_RELEASE "\n");</div><div class='add'>+	drm_printf(&amp;p, "module: " KBUILD_MODNAME "\n");</div><div class='add'>+	drm_printf(&amp;p, "time: %ptSp\n", &amp;coredump-&gt;reset_time);</div><div class='add'>+</div><div class='add'>+	if (coredump-&gt;reset_task_info.task.pid)</div><div class='add'>+		drm_printf(&amp;p, "process_name: %s PID: %d\n",</div><div class='add'>+			   coredump-&gt;reset_task_info.process_name,</div><div class='add'>+			   coredump-&gt;reset_task_info.task.pid);</div><div class='add'>+</div><div class='add'>+	/* SOC Information */</div><div class='add'>+	drm_printf(&amp;p, "\nSOC Information\n");</div><div class='add'>+	drm_printf(&amp;p, "SOC Device id: %d\n", coredump-&gt;adev-&gt;pdev-&gt;device);</div><div class='add'>+	drm_printf(&amp;p, "SOC PCI Revision id: %d\n", coredump-&gt;adev-&gt;pdev-&gt;revision);</div><div class='add'>+	drm_printf(&amp;p, "SOC Family: %d\n", coredump-&gt;adev-&gt;family);</div><div class='add'>+	drm_printf(&amp;p, "SOC Revision id: %d\n", coredump-&gt;adev-&gt;rev_id);</div><div class='add'>+	drm_printf(&amp;p, "SOC External Revision id: %d\n", coredump-&gt;adev-&gt;external_rev_id);</div><div class='add'>+</div><div class='add'>+	/* Memory Information */</div><div class='add'>+	drm_printf(&amp;p, "\nSOC Memory Information\n");</div><div class='add'>+	drm_printf(&amp;p, "real vram size: %llu\n", coredump-&gt;adev-&gt;gmc.real_vram_size);</div><div class='add'>+	drm_printf(&amp;p, "visible vram size: %llu\n", coredump-&gt;adev-&gt;gmc.visible_vram_size);</div><div class='add'>+	drm_printf(&amp;p, "gtt size: %llu\n", coredump-&gt;adev-&gt;mman.gtt_mgr.manager.size);</div><div class='add'>+</div><div class='add'>+	/* GDS Config */</div><div class='add'>+	drm_printf(&amp;p, "\nGDS Config\n");</div><div class='add'>+	drm_printf(&amp;p, "gds: total size: %d\n", coredump-&gt;adev-&gt;gds.gds_size);</div><div class='add'>+	drm_printf(&amp;p, "gds: compute partition size: %d\n", coredump-&gt;adev-&gt;gds.gds_size);</div><div class='add'>+	drm_printf(&amp;p, "gds: gws per compute partition: %d\n", coredump-&gt;adev-&gt;gds.gws_size);</div><div class='add'>+	drm_printf(&amp;p, "gds: os per compute partition: %d\n", coredump-&gt;adev-&gt;gds.oa_size);</div><div class='add'>+</div><div class='add'>+	/* HWIP Version Information */</div><div class='add'>+	drm_printf(&amp;p, "\nHW IP Version Information\n");</div><div class='add'>+	for (int i = 1; i &lt; MAX_HWIP; i++) {</div><div class='add'>+		for (int j = 0; j &lt; HWIP_MAX_INSTANCE; j++) {</div><div class='add'>+			ver = coredump-&gt;adev-&gt;ip_versions[i][j];</div><div class='add'>+			if (ver)</div><div class='add'>+				drm_printf(&amp;p, "HWIP: %s[%d][%d]: v%d.%d.%d.%d.%d\n",</div><div class='add'>+					   hw_ip_names[i], i, j,</div><div class='add'>+					   IP_VERSION_MAJ(ver),</div><div class='add'>+					   IP_VERSION_MIN(ver),</div><div class='add'>+					   IP_VERSION_REV(ver),</div><div class='add'>+					   IP_VERSION_VARIANT(ver),</div><div class='add'>+					   IP_VERSION_SUBREV(ver));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* IP firmware information */</div><div class='add'>+	drm_printf(&amp;p, "\nIP Firmwares\n");</div><div class='add'>+	amdgpu_devcoredump_fw_info(coredump-&gt;adev, &amp;p);</div><div class='add'>+</div><div class='add'>+	if (coredump-&gt;ring) {</div><div class='add'>+		drm_printf(&amp;p, "\nRing timed out details\n");</div><div class='add'>+		drm_printf(&amp;p, "IP Type: %d Ring Name: %s\n",</div><div class='add'>+			   coredump-&gt;ring-&gt;funcs-&gt;type,</div><div class='add'>+			   coredump-&gt;ring-&gt;name);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Add page fault information */</div><div class='add'>+	fault_info = &amp;coredump-&gt;adev-&gt;vm_manager.fault_info;</div><div class='add'>+	drm_printf(&amp;p, "\n[%s] Page fault observed\n",</div><div class='add'>+		   fault_info-&gt;vmhub ? "mmhub" : "gfxhub");</div><div class='add'>+	drm_printf(&amp;p, "Faulty page starting at address: 0x%016llx\n", fault_info-&gt;addr);</div><div class='add'>+	drm_printf(&amp;p, "Protection fault status register: 0x%x\n\n", fault_info-&gt;status);</div><div class='add'>+</div><div class='add'>+	/* dump the ip state for each ip */</div><div class='add'>+	drm_printf(&amp;p, "IP Dump\n");</div><div class='add'>+	for (int i = 0; i &lt; coredump-&gt;adev-&gt;num_ip_blocks; i++) {</div><div class='add'>+		ip_block = &amp;coredump-&gt;adev-&gt;ip_blocks[i];</div><div class='add'>+		if (ip_block-&gt;version-&gt;funcs-&gt;print_ip_state) {</div><div class='add'>+			drm_printf(&amp;p, "IP: %s\n", ip_block-&gt;version-&gt;funcs-&gt;name);</div><div class='add'>+			ip_block-&gt;version-&gt;funcs-&gt;print_ip_state(ip_block, &amp;p);</div><div class='add'>+			drm_printf(&amp;p, "\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Add ring buffer information */</div><div class='add'>+	drm_printf(&amp;p, "Ring buffer information\n");</div><div class='add'>+	for (int i = 0; i &lt; coredump-&gt;adev-&gt;num_rings; i++) {</div><div class='add'>+		int j = 0;</div><div class='add'>+		struct amdgpu_ring *ring = coredump-&gt;adev-&gt;rings[i];</div><div class='add'>+</div><div class='add'>+		drm_printf(&amp;p, "ring name: %s\n", ring-&gt;name);</div><div class='add'>+		drm_printf(&amp;p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n",</div><div class='add'>+			   amdgpu_ring_get_rptr(ring),</div><div class='add'>+			   amdgpu_ring_get_wptr(ring),</div><div class='add'>+			   ring-&gt;buf_mask);</div><div class='add'>+		drm_printf(&amp;p, "Ring size in dwords: %d\n",</div><div class='add'>+			   ring-&gt;ring_size / 4);</div><div class='add'>+		drm_printf(&amp;p, "Ring contents\n");</div><div class='add'>+		drm_printf(&amp;p, "Offset \t Value\n");</div><div class='add'>+</div><div class='add'>+		while (j &lt; ring-&gt;ring_size) {</div><div class='add'>+			drm_printf(&amp;p, "0x%x \t 0x%x\n", j, ring-&gt;ring[j / 4]);</div><div class='add'>+			j += 4;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (coredump-&gt;skip_vram_check)</div><div class='add'>+		drm_printf(&amp;p, "VRAM lost check is skipped!\n");</div><div class='add'>+	else if (coredump-&gt;reset_vram_lost)</div><div class='add'>+		drm_printf(&amp;p, "VRAM is lost due to GPU reset!\n");</div><div class='add'>+</div><div class='add'>+	return count - iter.remain;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_devcoredump_free(void *data)</div><div class='add'>+{</div><div class='add'>+	kfree(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,</div><div class='add'>+		     bool vram_lost, struct amdgpu_job *job)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = adev_to_drm(adev);</div><div class='add'>+	struct amdgpu_coredump_info *coredump;</div><div class='add'>+	struct drm_sched_job *s_job;</div><div class='add'>+</div><div class='add'>+	coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT);</div><div class='add'>+</div><div class='add'>+	if (!coredump) {</div><div class='add'>+		DRM_ERROR("%s: failed to allocate memory for coredump\n", __func__);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	coredump-&gt;skip_vram_check = skip_vram_check;</div><div class='add'>+	coredump-&gt;reset_vram_lost = vram_lost;</div><div class='add'>+</div><div class='add'>+	if (job &amp;&amp; job-&gt;pasid) {</div><div class='add'>+		struct amdgpu_task_info *ti;</div><div class='add'>+</div><div class='add'>+		ti = amdgpu_vm_get_task_info_pasid(adev, job-&gt;pasid);</div><div class='add'>+		if (ti) {</div><div class='add'>+			coredump-&gt;reset_task_info = *ti;</div><div class='add'>+			amdgpu_vm_put_task_info(ti);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (job) {</div><div class='add'>+		s_job = &amp;job-&gt;base;</div><div class='add'>+		coredump-&gt;ring = to_amdgpu_ring(s_job-&gt;sched);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	coredump-&gt;adev = adev;</div><div class='add'>+</div><div class='add'>+	ktime_get_ts64(&amp;coredump-&gt;reset_time);</div><div class='add'>+</div><div class='add'>+	dev_coredumpm(dev-&gt;dev, THIS_MODULE, coredump, 0, GFP_NOWAIT,</div><div class='add'>+		      amdgpu_devcoredump_read, amdgpu_devcoredump_free);</div><div class='add'>+</div><div class='add'>+	drm_info(dev, "AMDGPU device coredump file has been created\n");</div><div class='add'>+	drm_info(dev, "Check your /sys/class/drm/card%d/device/devcoredump/data\n",</div><div class='add'>+		 dev-&gt;primary-&gt;index);</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h<br/>new file mode 100644<br/>index 000000000000..ef9772c6bcc9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_DEV_COREDUMP_H__</div><div class='add'>+#define __AMDGPU_DEV_COREDUMP_H__</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DEV_COREDUMP</div><div class='add'>+</div><div class='add'>+#define AMDGPU_COREDUMP_VERSION "1"</div><div class='add'>+</div><div class='add'>+struct amdgpu_coredump_info {</div><div class='add'>+	struct amdgpu_device            *adev;</div><div class='add'>+	struct amdgpu_task_info         reset_task_info;</div><div class='add'>+	struct timespec64               reset_time;</div><div class='add'>+	bool                            skip_vram_check;</div><div class='add'>+	bool                            reset_vram_lost;</div><div class='add'>+	struct amdgpu_ring              *ring;</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,</div><div class='add'>+		     bool vram_lost, struct amdgpu_job *job);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br/>index 5dc24c971b41..58c3ffe707d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c</a></div><div class='hunk'>@@ -25,6 +25,8 @@</div><div class='ctx'>  *          Alex Deucher</div><div class='ctx'>  *          Jerome Glisse</div><div class='ctx'>  */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/aperture.h&gt;</div><div class='ctx'> #include &lt;linux/power_supply.h&gt;</div><div class='ctx'> #include &lt;linux/kthread.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -35,10 +37,9 @@</div><div class='ctx'> #include &lt;linux/pci-p2pdma.h&gt;</div><div class='ctx'> #include &lt;linux/apple-gmux.h&gt;</div><div class='ctx'> </div><div class='del'>-#include &lt;drm/drm_aperture.h&gt;</div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_client_event.h&gt;</div><div class='ctx'> #include &lt;drm/drm_crtc_helper.h&gt;</div><div class='del'>-#include &lt;drm/drm_fb_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_probe_helper.h&gt;</div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='hunk'>@@ -70,10 +71,12 @@</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_xgmi.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> #include "amdgpu_pmu.h"</div><div class='ctx'> #include "amdgpu_fru_eeprom.h"</div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='ctx'> #include "amdgpu_virt.h"</div><div class='add'>+#include "amdgpu_dev_coredump.h"</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/suspend.h&gt;</div><div class='ctx'> #include &lt;drm/task_barrier.h&gt;</div><div class='hunk'>@@ -83,6 +86,7 @@</div><div class='ctx'> </div><div class='ctx'> #if IS_ENABLED(CONFIG_X86)</div><div class='ctx'> #include &lt;asm/intel-family.h&gt;</div><div class='add'>+#include &lt;asm/cpu_device_id.h&gt;</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");</div><div class='hunk'>@@ -92,6 +96,7 @@ MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/cyan_skillfish_gpu_info.bin");</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_RESUME_MS		2000</div><div class='ctx'> #define AMDGPU_MAX_RETRY_LIMIT		2</div><div class='hunk'>@@ -100,6 +105,9 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");</div><div class='ctx'> #define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 &gt;&gt; 2)</div><div class='ctx'> #define AMDGPU_PCIE_DATA_FALLBACK (0x3C &gt;&gt; 2)</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_VBIOS_SKIP (1U &lt;&lt; 0)</div><div class='add'>+#define AMDGPU_VBIOS_OPTIONAL (1U &lt;&lt; 1)</div><div class='add'>+</div><div class='ctx'> static const struct drm_driver amdgpu_kms_driver;</div><div class='ctx'> </div><div class='ctx'> const char *amdgpu_asic_name[] = {</div><div class='hunk'>@@ -143,13 +151,76 @@ const char *amdgpu_asic_name[] = {</div><div class='ctx'> 	"LAST",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM  - 1, 0)</div><div class='add'>+/*</div><div class='add'>+ * Default init level where all blocks are expected to be initialized. This is</div><div class='add'>+ * the level of initialization expected by default and also after a full reset</div><div class='add'>+ * of the device.</div><div class='add'>+ */</div><div class='add'>+struct amdgpu_init_level amdgpu_init_default = {</div><div class='add'>+	.level = AMDGPU_INIT_LEVEL_DEFAULT,</div><div class='add'>+	.hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_init_level amdgpu_init_recovery = {</div><div class='add'>+	.level = AMDGPU_INIT_LEVEL_RESET_RECOVERY,</div><div class='add'>+	.hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Minimal blocks needed to be initialized before a XGMI hive can be reset. This</div><div class='add'>+ * is used for cases like reset on initialization where the entire hive needs to</div><div class='add'>+ * be reset before first use.</div><div class='add'>+ */</div><div class='add'>+struct amdgpu_init_level amdgpu_init_minimal_xgmi = {</div><div class='add'>+	.level = AMDGPU_INIT_LEVEL_MINIMAL_XGMI,</div><div class='add'>+	.hwini_ip_block_mask =</div><div class='add'>+		BIT(AMD_IP_BLOCK_TYPE_GMC) | BIT(AMD_IP_BLOCK_TYPE_SMC) |</div><div class='add'>+		BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) |</div><div class='add'>+		BIT(AMD_IP_BLOCK_TYPE_PSP)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev);</div><div class='add'>+static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev);</div><div class='add'>+static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_load_switch_state(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev,</div><div class='add'>+					     enum amd_ip_block_type block)</div><div class='add'>+{</div><div class='add'>+	return (adev-&gt;init_lvl-&gt;hwini_ip_block_mask &amp; (1U &lt;&lt; block)) != 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_set_init_level(struct amdgpu_device *adev,</div><div class='add'>+			   enum amdgpu_init_lvl_id lvl)</div><div class='add'>+{</div><div class='add'>+	switch (lvl) {</div><div class='add'>+	case AMDGPU_INIT_LEVEL_MINIMAL_XGMI:</div><div class='add'>+		adev-&gt;init_lvl = &amp;amdgpu_init_minimal_xgmi;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_INIT_LEVEL_RESET_RECOVERY:</div><div class='add'>+		adev-&gt;init_lvl = &amp;amdgpu_init_recovery;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_INIT_LEVEL_DEFAULT:</div><div class='add'>+		fallthrough;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;init_lvl = &amp;amdgpu_init_default;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev);</div><div class='add'>+static int amdgpu_device_pm_notifier(struct notifier_block *nb, unsigned long mode,</div><div class='add'>+				     void *data);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: pcie_replay_count</div><div class='ctx'>  *</div><div class='ctx'>  * The amdgpu driver provides a sysfs API for reporting the total number</div><div class='del'>- * of PCIe replays (NAKs)</div><div class='add'>+ * of PCIe replays (NAKs).</div><div class='ctx'>  * The file pcie_replay_count is used for this and returns the total</div><div class='del'>- * number of replays as a sum of the NAKs generated and NAKs received</div><div class='add'>+ * number of replays as a sum of the NAKs generated and NAKs received.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,</div><div class='hunk'>@@ -165,8 +236,26 @@ static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,</div><div class='ctx'> static DEVICE_ATTR(pcie_replay_count, 0444,</div><div class='ctx'> 		amdgpu_device_get_pcie_replay_count, NULL);</div><div class='ctx'> </div><div class='add'>+static int amdgpu_device_attr_sysfs_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_nbio_is_replay_cnt_supported(adev))</div><div class='add'>+		ret = sysfs_create_file(&amp;adev-&gt;dev-&gt;kobj,</div><div class='add'>+					&amp;dev_attr_pcie_replay_count.attr);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_attr_sysfs_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_nbio_is_replay_cnt_supported(adev))</div><div class='add'>+		sysfs_remove_file(&amp;adev-&gt;dev-&gt;kobj,</div><div class='add'>+				  &amp;dev_attr_pcie_replay_count.attr);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,</div><div class='del'>-					  struct bin_attribute *attr, char *buf,</div><div class='add'>+					  const struct bin_attribute *attr, char *buf,</div><div class='ctx'> 					  loff_t ppos, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = kobj_to_dev(kobj);</div><div class='hunk'>@@ -202,8 +291,8 @@ static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,</div><div class='ctx'> 	return bytes_read;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,</div><div class='del'>-	 AMDGPU_SYS_REG_STATE_END);</div><div class='add'>+static const BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,</div><div class='add'>+		      AMDGPU_SYS_REG_STATE_END);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -224,6 +313,42 @@ void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	sysfs_remove_bin_file(&amp;adev-&gt;dev-&gt;kobj, &amp;bin_attr_reg_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ip_block-&gt;version-&gt;funcs-&gt;suspend) {</div><div class='add'>+		r = ip_block-&gt;version-&gt;funcs-&gt;suspend(ip_block);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(ip_block-&gt;adev-&gt;dev,</div><div class='add'>+				"suspend of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				ip_block-&gt;version-&gt;funcs-&gt;name, r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ip_block-&gt;status.hw = false;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ip_block-&gt;version-&gt;funcs-&gt;resume) {</div><div class='add'>+		r = ip_block-&gt;version-&gt;funcs-&gt;resume(ip_block);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(ip_block-&gt;adev-&gt;dev,</div><div class='add'>+				"resume of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				ip_block-&gt;version-&gt;funcs-&gt;name, r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ip_block-&gt;status.hw = true;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: board_info</div><div class='ctx'>  *</div><div class='hunk'>@@ -294,19 +419,16 @@ static const struct attribute_group amdgpu_board_attrs_group = {</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control</div><div class='ctx'>  *</div><div class='del'>- * @dev: drm_device pointer</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='ctx'>  *</div><div class='ctx'>  * Returns true if the device is a dGPU with ATPX power control,</div><div class='ctx'>  * otherwise return false.</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_device_supports_px(struct drm_device *dev)</div><div class='add'>+bool amdgpu_device_supports_px(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-</div><div class='ctx'> 	if ((adev-&gt;flags &amp; AMD_IS_PX) &amp;&amp; !amdgpu_is_atpx_hybrid())</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -315,14 +437,15 @@ bool amdgpu_device_supports_px(struct drm_device *dev)</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources</div><div class='ctx'>  *</div><div class='del'>- * @dev: drm_device pointer</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='ctx'>  *</div><div class='ctx'>  * Returns true if the device is a dGPU with ACPI power control,</div><div class='ctx'>  * otherwise return false.</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_device_supports_boco(struct drm_device *dev)</div><div class='add'>+bool amdgpu_device_supports_boco(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;has_pr3 ||</div><div class='ctx'> 	    ((adev-&gt;flags &amp; AMD_IS_PX) &amp;&amp; amdgpu_is_atpx_hybrid()))</div><div class='hunk'>@@ -333,30 +456,105 @@ bool amdgpu_device_supports_boco(struct drm_device *dev)</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_supports_baco - Does the device support BACO</div><div class='ctx'>  *</div><div class='del'>- * @dev: drm_device pointer</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='ctx'>  *</div><div class='del'>- * Returns true if the device supporte BACO,</div><div class='del'>- * otherwise return false.</div><div class='add'>+ * Return:</div><div class='add'>+ * 1 if the device supports BACO;</div><div class='add'>+ * 3 if the device supports MACO (only works if BACO is supported)</div><div class='add'>+ * otherwise return 0.</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_device_supports_baco(struct drm_device *dev)</div><div class='add'>+int amdgpu_device_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-</div><div class='ctx'> 	return amdgpu_asic_supports_baco(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int bamaco_support;</div><div class='add'>+</div><div class='add'>+	adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_NONE;</div><div class='add'>+	bamaco_support = amdgpu_device_supports_baco(adev);</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_runtime_pm) {</div><div class='add'>+	case 2:</div><div class='add'>+		if (bamaco_support &amp; MACO_SUPPORT) {</div><div class='add'>+			adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BAMACO;</div><div class='add'>+			dev_info(adev-&gt;dev, "Forcing BAMACO for runtime pm\n");</div><div class='add'>+		} else if (bamaco_support == BACO_SUPPORT) {</div><div class='add'>+			adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='add'>+			dev_info(adev-&gt;dev, "Requested mode BAMACO not available,fallback to use BACO\n");</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (bamaco_support &amp; BACO_SUPPORT) {</div><div class='add'>+			adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='add'>+			dev_info(adev-&gt;dev, "Forcing BACO for runtime pm\n");</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case -1:</div><div class='add'>+	case -2:</div><div class='add'>+		if (amdgpu_device_supports_px(adev)) {</div><div class='add'>+			/* enable PX as runtime mode */</div><div class='add'>+			adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_PX;</div><div class='add'>+			dev_info(adev-&gt;dev, "Using ATPX for runtime pm\n");</div><div class='add'>+		} else if (amdgpu_device_supports_boco(adev)) {</div><div class='add'>+			/* enable boco as runtime mode */</div><div class='add'>+			adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BOCO;</div><div class='add'>+			dev_info(adev-&gt;dev, "Using BOCO for runtime pm\n");</div><div class='add'>+		} else {</div><div class='add'>+			if (!bamaco_support)</div><div class='add'>+				goto no_runtime_pm;</div><div class='add'>+</div><div class='add'>+			switch (adev-&gt;asic_type) {</div><div class='add'>+			case CHIP_VEGA20:</div><div class='add'>+			case CHIP_ARCTURUS:</div><div class='add'>+				/* BACO are not supported on vega20 and arctrus */</div><div class='add'>+				break;</div><div class='add'>+			case CHIP_VEGA10:</div><div class='add'>+				/* enable BACO as runpm mode if noretry=0 */</div><div class='add'>+				if (!adev-&gt;gmc.noretry &amp;&amp; !amdgpu_passthrough(adev))</div><div class='add'>+					adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				/* enable BACO as runpm mode on CI+ */</div><div class='add'>+				if (!amdgpu_passthrough(adev))</div><div class='add'>+					adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) {</div><div class='add'>+				if (bamaco_support &amp; MACO_SUPPORT) {</div><div class='add'>+					adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BAMACO;</div><div class='add'>+					dev_info(adev-&gt;dev, "Using BAMACO for runtime pm\n");</div><div class='add'>+				} else {</div><div class='add'>+					dev_info(adev-&gt;dev, "Using BACO for runtime pm\n");</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 0:</div><div class='add'>+		dev_info(adev-&gt;dev, "runtime pm is manually disabled\n");</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+no_runtime_pm:</div><div class='add'>+	if (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_NONE)</div><div class='add'>+		dev_info(adev-&gt;dev, "Runtime PM not available\n");</div><div class='add'>+}</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_supports_smart_shift - Is the device dGPU with</div><div class='ctx'>  * smart shift support</div><div class='ctx'>  *</div><div class='del'>- * @dev: drm_device pointer</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='ctx'>  *</div><div class='ctx'>  * Returns true if the device is a dGPU with Smart Shift support,</div><div class='ctx'>  * otherwise returns false.</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_device_supports_smart_shift(struct drm_device *dev)</div><div class='add'>+bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return (amdgpu_device_supports_boco(dev) &amp;&amp;</div><div class='add'>+	return (amdgpu_device_supports_boco(adev) &amp;&amp;</div><div class='ctx'> 		amdgpu_acpi_is_power_shift_control_supported());</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -407,7 +605,7 @@ void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_device_aper_access - access vram by vram aperature</div><div class='add'>+ * amdgpu_device_aper_access - access vram by vram aperture</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @pos: offset of the buffer in vram</div><div class='hunk'>@@ -498,7 +696,7 @@ bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)</div><div class='ctx'> 	 * here is that the GPU reset is not running on another thread in parallel.</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * For this we trylock the read side of the reset semaphore, if that succeeds</div><div class='del'>-	 * we know that the reset is not running in paralell.</div><div class='add'>+	 * we know that the reset is not running in parallel.</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * If the trylock fails we assert that we are either already holding the read</div><div class='ctx'> 	 * side of the lock or are the reset thread itself and hold the write side of</div><div class='hunk'>@@ -599,7 +797,7 @@ uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,</div><div class='ctx'> 		    amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,</div><div class='ctx'> 							 GC_HWIP, false,</div><div class='ctx'> 							 &amp;rlcg_flag)) {</div><div class='del'>-			ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);</div><div class='add'>+			ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id));</div><div class='ctx'> 		} else if (!(acc_flags &amp; AMDGPU_REGS_NO_KIQ) &amp;&amp;</div><div class='ctx'> 		    amdgpu_sriov_runtime(adev) &amp;&amp;</div><div class='ctx'> 		    down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='hunk'>@@ -730,7 +928,7 @@ void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,</div><div class='ctx'> 		    amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,</div><div class='ctx'> 							 GC_HWIP, true,</div><div class='ctx'> 							 &amp;rlcg_flag)) {</div><div class='del'>-			amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);</div><div class='add'>+			amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));</div><div class='ctx'> 		} else if (!(acc_flags &amp; AMDGPU_REGS_NO_KIQ) &amp;&amp;</div><div class='ctx'> 		    amdgpu_sriov_runtime(adev) &amp;&amp;</div><div class='ctx'> 		    down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='hunk'>@@ -1090,14 +1288,14 @@ u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);</div><div class='add'>+	dev_err(adev-&gt;dev, "Invalid callback to read register 0x%04X\n", reg);</div><div class='ctx'> 	BUG();</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);</div><div class='add'>+	dev_err(adev-&gt;dev, "Invalid callback to read register 0x%llX\n", reg);</div><div class='ctx'> 	BUG();</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1114,15 +1312,17 @@ static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",</div><div class='del'>-		  reg, v);</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"Invalid callback to write register 0x%04X with 0x%08X\n", reg,</div><div class='add'>+		v);</div><div class='ctx'> 	BUG();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",</div><div class='del'>-		  reg, v);</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"Invalid callback to write register 0x%llX with 0x%08X\n", reg,</div><div class='add'>+		v);</div><div class='ctx'> 	BUG();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1138,14 +1338,15 @@ static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, ui</div><div class='ctx'>  */</div><div class='ctx'> static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);</div><div class='add'>+	dev_err(adev-&gt;dev, "Invalid callback to read 64 bit register 0x%04X\n",</div><div class='add'>+		reg);</div><div class='ctx'> 	BUG();</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);</div><div class='add'>+	dev_err(adev-&gt;dev, "Invalid callback to read register 0x%llX\n", reg);</div><div class='ctx'> 	BUG();</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1162,15 +1363,17 @@ static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t r</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",</div><div class='del'>-		  reg, v);</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",</div><div class='add'>+		reg, v);</div><div class='ctx'> 	BUG();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",</div><div class='del'>-		  reg, v);</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",</div><div class='add'>+		reg, v);</div><div class='ctx'> 	BUG();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1188,8 +1391,9 @@ static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg,</div><div class='ctx'> static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,</div><div class='ctx'> 					  uint32_t block, uint32_t reg)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",</div><div class='del'>-		  reg, block);</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"Invalid callback to read register 0x%04X in block 0x%04X\n",</div><div class='add'>+		reg, block);</div><div class='ctx'> 	BUG();</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1209,11 +1413,23 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,</div><div class='ctx'> 				      uint32_t block,</div><div class='ctx'> 				      uint32_t reg, uint32_t v)</div><div class='ctx'> {</div><div class='del'>-	DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",</div><div class='del'>-		  reg, block, v);</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",</div><div class='add'>+		reg, block, v);</div><div class='ctx'> 	BUG();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (hweight32(adev-&gt;aid_mask) &amp;&amp; (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		return AMDGPU_VBIOS_SKIP;</div><div class='add'>+</div><div class='add'>+	if (hweight32(adev-&gt;aid_mask) &amp;&amp; amdgpu_passthrough(adev))</div><div class='add'>+		return AMDGPU_VBIOS_OPTIONAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_asic_init - Wrapper for atom asic_init</div><div class='ctx'>  *</div><div class='hunk'>@@ -1223,16 +1439,28 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_asic_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint32_t flags;</div><div class='add'>+	bool optional;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_asic_pre_asic_init(adev);</div><div class='add'>+	flags = amdgpu_device_get_vbios_flags(adev);</div><div class='add'>+	optional = !!(flags &amp; (AMDGPU_VBIOS_OPTIONAL | AMDGPU_VBIOS_SKIP));</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0) ||</div><div class='ctx'> 	    amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(11, 0, 0)) {</div><div class='ctx'> 		amdgpu_psp_wait_for_bootloader(adev);</div><div class='add'>+		if (optional &amp;&amp; !adev-&gt;bios)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='ctx'> 		ret = amdgpu_atomfirmware_asic_init(adev, true);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	} else {</div><div class='add'>+		if (optional &amp;&amp; !adev-&gt;bios)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='ctx'> 		return amdgpu_atom_asic_init(adev-&gt;mode_info.atom_context);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1402,13 +1630,17 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)</div><div class='ctx'> {</div><div class='del'>-	unsigned long offset = find_first_zero_bit(adev-&gt;wb.used, adev-&gt;wb.num_wb);</div><div class='add'>+	unsigned long flags, offset;</div><div class='ctx'> </div><div class='add'>+	spin_lock_irqsave(&amp;adev-&gt;wb.lock, flags);</div><div class='add'>+	offset = find_first_zero_bit(adev-&gt;wb.used, adev-&gt;wb.num_wb);</div><div class='ctx'> 	if (offset &lt; adev-&gt;wb.num_wb) {</div><div class='ctx'> 		__set_bit(offset, adev-&gt;wb.used);</div><div class='add'>+		spin_unlock_irqrestore(&amp;adev-&gt;wb.lock, flags);</div><div class='ctx'> 		*wb = offset &lt;&lt; 3; /* convert to dw offset */</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	} else {</div><div class='add'>+		spin_unlock_irqrestore(&amp;adev-&gt;wb.lock, flags);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1423,9 +1655,13 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)</div><div class='ctx'> {</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='ctx'> 	wb &gt;&gt;= 3;</div><div class='add'>+	spin_lock_irqsave(&amp;adev-&gt;wb.lock, flags);</div><div class='ctx'> 	if (wb &lt; adev-&gt;wb.num_wb)</div><div class='ctx'> 		__clear_bit(wb, adev-&gt;wb.used);</div><div class='add'>+	spin_unlock_irqrestore(&amp;adev-&gt;wb.lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1442,9 +1678,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)</div><div class='ctx'> 	int rbar_size = pci_rebar_bytes_to_size(adev-&gt;gmc.real_vram_size);</div><div class='ctx'> 	struct pci_bus *root;</div><div class='ctx'> 	struct resource *res;</div><div class='add'>+	int max_size, r;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	u16 cmd;</div><div class='del'>-	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1453,9 +1689,21 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (!amdgpu_rebar)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* resizing on Dell G5 SE platforms causes problems with runtime pm */</div><div class='add'>+	if ((amdgpu_runtime_pm != 0) &amp;&amp;</div><div class='add'>+	    adev-&gt;pdev-&gt;vendor == PCI_VENDOR_ID_ATI &amp;&amp;</div><div class='add'>+	    adev-&gt;pdev-&gt;device == 0x731f &amp;&amp;</div><div class='add'>+	    adev-&gt;pdev-&gt;subsystem_vendor == PCI_VENDOR_ID_DELL)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	/* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */</div><div class='ctx'> 	if (!pci_find_ext_capability(adev-&gt;pdev, PCI_EXT_CAP_ID_VNDR))</div><div class='del'>-		DRM_WARN("System can't access extended configuration space,please check!!\n");</div><div class='add'>+		dev_warn(</div><div class='add'>+			adev-&gt;dev,</div><div class='add'>+			"System can't access extended configuration space, please check!!\n");</div><div class='ctx'> </div><div class='ctx'> 	/* skip if the bios has already enabled large BAR */</div><div class='ctx'> 	if (adev-&gt;gmc.real_vram_size &amp;&amp;</div><div class='hunk'>@@ -1478,28 +1726,27 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Limit the BAR size to what is available */</div><div class='del'>-	rbar_size = min(fls(pci_rebar_get_possible_sizes(adev-&gt;pdev, 0)) - 1,</div><div class='del'>-			rbar_size);</div><div class='add'>+	max_size = pci_rebar_get_max_size(adev-&gt;pdev, 0);</div><div class='add'>+	if (max_size &lt; 0)</div><div class='add'>+		return 0;</div><div class='add'>+	rbar_size = min(max_size, rbar_size);</div><div class='ctx'> </div><div class='ctx'> 	/* Disable memory decoding while we change the BAR addresses and size */</div><div class='ctx'> 	pci_read_config_word(adev-&gt;pdev, PCI_COMMAND, &amp;cmd);</div><div class='ctx'> 	pci_write_config_word(adev-&gt;pdev, PCI_COMMAND,</div><div class='ctx'> 			      cmd &amp; ~PCI_COMMAND_MEMORY);</div><div class='ctx'> </div><div class='del'>-	/* Free the VRAM and doorbell BAR, we most likely need to move both. */</div><div class='add'>+	/* Tear down doorbell as resizing will release BARs */</div><div class='ctx'> 	amdgpu_doorbell_fini(adev);</div><div class='del'>-	if (adev-&gt;asic_type &gt;= CHIP_BONAIRE)</div><div class='del'>-		pci_release_resource(adev-&gt;pdev, 2);</div><div class='del'>-</div><div class='del'>-	pci_release_resource(adev-&gt;pdev, 0);</div><div class='ctx'> </div><div class='del'>-	r = pci_resize_resource(adev-&gt;pdev, 0, rbar_size);</div><div class='add'>+	r = pci_resize_resource(adev-&gt;pdev, 0, rbar_size,</div><div class='add'>+				(adev-&gt;asic_type &gt;= CHIP_BONAIRE) ? 1 &lt;&lt; 5</div><div class='add'>+								  : 1 &lt;&lt; 2);</div><div class='ctx'> 	if (r == -ENOSPC)</div><div class='del'>-		DRM_INFO("Not enough PCI address space for a large BAR.");</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "Not enough PCI address space for a large BAR.");</div><div class='ctx'> 	else if (r &amp;&amp; r != -ENOTSUPP)</div><div class='del'>-		DRM_ERROR("Problem resizing BAR0 (%d).", r);</div><div class='del'>-</div><div class='del'>-	pci_assign_unassigned_bus_resources(adev-&gt;pdev-&gt;bus);</div><div class='add'>+		dev_err(adev-&gt;dev, "Problem resizing BAR0 (%d).", r);</div><div class='ctx'> </div><div class='ctx'> 	/* When the doorbell or fb BAR isn't available we have no chance of</div><div class='ctx'> 	 * using the device.</div><div class='hunk'>@@ -1513,14 +1760,6 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool amdgpu_device_read_bios(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	if (hweight32(adev-&gt;aid_mask) &amp;&amp; (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * GPU helpers function.</div><div class='ctx'>  */</div><div class='hunk'>@@ -1535,12 +1774,15 @@ static bool amdgpu_device_read_bios(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> bool amdgpu_device_need_post(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	uint32_t reg;</div><div class='add'>+	uint32_t reg, flags;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_device_read_bios(adev))</div><div class='add'>+	flags = amdgpu_device_get_vbios_flags(adev);</div><div class='add'>+	if (flags &amp; AMDGPU_VBIOS_SKIP)</div><div class='add'>+		return false;</div><div class='add'>+	if ((flags &amp; AMDGPU_VBIOS_OPTIONAL) &amp;&amp; !adev-&gt;bios)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_passthrough(adev)) {</div><div class='hunk'>@@ -1554,7 +1796,7 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)</div><div class='ctx'> 			uint32_t fw_ver;</div><div class='ctx'> </div><div class='ctx'> 			err = request_firmware(&amp;adev-&gt;pm.fw, "amdgpu/fiji_smc.bin", adev-&gt;dev);</div><div class='del'>-			/* force vPost if error occured */</div><div class='add'>+			/* force vPost if error occurred */</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return true;</div><div class='ctx'> </div><div class='hunk'>@@ -1566,7 +1808,7 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Don't post if we need to reset whole hive on init */</div><div class='del'>-	if (adev-&gt;gmc.xgmi.pending_reset)</div><div class='add'>+	if (adev-&gt;init_lvl-&gt;level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;has_hw_reset) {</div><div class='hunk'>@@ -1604,8 +1846,8 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)</div><div class='ctx'> 	case 0:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	default:</div><div class='del'>-		DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",</div><div class='del'>-			  amdgpu_seamless);</div><div class='add'>+		dev_err(adev-&gt;dev, "Invalid value for amdgpu.seamless: %d\n",</div><div class='add'>+			amdgpu_seamless);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1641,6 +1883,42 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4.</div><div class='add'>+	 * It's unclear if this is a platform-specific or GPU-specific issue.</div><div class='add'>+	 * Disable ASPM on SI for the time being.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;family == AMDGPU_FAMILY_SI)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_X86)</div><div class='add'>+	struct cpuinfo_x86 *c = &amp;cpu_data(0);</div><div class='add'>+</div><div class='add'>+	if (!(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 0) ||</div><div class='add'>+		  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 1)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (c-&gt;x86 == 6 &amp;&amp;</div><div class='add'>+		adev-&gt;pm.pcie_gen_mask &amp; CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) {</div><div class='add'>+		switch (c-&gt;x86_model) {</div><div class='add'>+		case VFM_MODEL(INTEL_ALDERLAKE):</div><div class='add'>+		case VFM_MODEL(INTEL_ALDERLAKE_L):</div><div class='add'>+		case VFM_MODEL(INTEL_RAPTORLAKE):</div><div class='add'>+		case VFM_MODEL(INTEL_RAPTORLAKE_P):</div><div class='add'>+		case VFM_MODEL(INTEL_RAPTORLAKE_S):</div><div class='add'>+			return true;</div><div class='add'>+		default:</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+#else</div><div class='add'>+	return false;</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_should_use_aspm - check if the device should program ASPM</div><div class='ctx'>  *</div><div class='hunk'>@@ -1665,7 +1943,7 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='ctx'> 		return false;</div><div class='del'>-	if (!(adev-&gt;pm.pp_feature &amp; PP_PCIE_DPM_MASK))</div><div class='add'>+	if (amdgpu_device_aspm_support_quirk(adev))</div><div class='ctx'> 		return false;</div><div class='ctx'> 	return pcie_aspm_enabled(adev-&gt;pdev);</div><div class='ctx'> }</div><div class='hunk'>@@ -1752,7 +2030,7 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (!is_os_64) {</div><div class='del'>-		DRM_WARN("Not 64-bit OS, feature not supported\n");</div><div class='add'>+		dev_warn(adev-&gt;dev, "Not 64-bit OS, feature not supported\n");</div><div class='ctx'> 		goto def_value;</div><div class='ctx'> 	}</div><div class='ctx'> 	si_meminfo(&amp;si);</div><div class='hunk'>@@ -1767,7 +2045,7 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)</div><div class='ctx'> 		if (total_memory &lt; dram_size_seven_GB)</div><div class='ctx'> 			goto def_value1;</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_WARN("Smu memory pool size not supported\n");</div><div class='add'>+		dev_warn(adev-&gt;dev, "Smu memory pool size not supported\n");</div><div class='ctx'> 		goto def_value;</div><div class='ctx'> 	}</div><div class='ctx'> 	adev-&gt;pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size &lt;&lt; 28;</div><div class='hunk'>@@ -1775,7 +2053,7 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return;</div><div class='ctx'> </div><div class='ctx'> def_value1:</div><div class='del'>-	DRM_WARN("No enough system memory\n");</div><div class='add'>+	dev_warn(adev-&gt;dev, "No enough system memory\n");</div><div class='ctx'> def_value:</div><div class='ctx'> 	adev-&gt;pm.smu_prv_buffer_size = 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1827,6 +2105,8 @@ static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_check_arguments(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sched_jobs &lt; 4) {</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "sched jobs (%d) must be at least 4\n",</div><div class='ctx'> 			 amdgpu_sched_jobs);</div><div class='hunk'>@@ -1881,6 +2161,32 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; i++) {</div><div class='add'>+		switch (amdgpu_enforce_isolation) {</div><div class='add'>+		case -1:</div><div class='add'>+		case 0:</div><div class='add'>+		default:</div><div class='add'>+			/* disable */</div><div class='add'>+			adev-&gt;enforce_isolation[i] = AMDGPU_ENFORCE_ISOLATION_DISABLE;</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			/* enable */</div><div class='add'>+			adev-&gt;enforce_isolation[i] =</div><div class='add'>+				AMDGPU_ENFORCE_ISOLATION_ENABLE;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			/* enable legacy mode */</div><div class='add'>+			adev-&gt;enforce_isolation[i] =</div><div class='add'>+				AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			/* enable only process isolation without submitting cleaner shader */</div><div class='add'>+			adev-&gt;enforce_isolation[i] =</div><div class='add'>+				AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1899,7 +2205,8 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,</div><div class='ctx'> 	struct drm_device *dev = pci_get_drvdata(pdev);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_device_supports_px(dev) &amp;&amp; state == VGA_SWITCHEROO_OFF)</div><div class='add'>+	if (amdgpu_device_supports_px(drm_to_adev(dev)) &amp;&amp;</div><div class='add'>+	    state == VGA_SWITCHEROO_OFF)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (state == VGA_SWITCHEROO_ON) {</div><div class='hunk'>@@ -1911,12 +2218,13 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,</div><div class='ctx'> 		amdgpu_device_load_pci_state(pdev);</div><div class='ctx'> 		r = pci_enable_device(pdev);</div><div class='ctx'> 		if (r)</div><div class='del'>-			DRM_WARN("pci_enable_device failed (%d)\n", r);</div><div class='add'>+			dev_warn(&amp;pdev-&gt;dev, "pci_enable_device failed (%d)\n",</div><div class='add'>+				 r);</div><div class='ctx'> 		amdgpu_device_resume(dev, true);</div><div class='ctx'> </div><div class='ctx'> 		dev-&gt;switch_power_state = DRM_SWITCH_POWER_ON;</div><div class='ctx'> 	} else {</div><div class='del'>-		pr_info("switched off\n");</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev, "switched off\n");</div><div class='ctx'> 		dev-&gt;switch_power_state = DRM_SWITCH_POWER_CHANGING;</div><div class='ctx'> 		amdgpu_device_prepare(dev);</div><div class='ctx'> 		amdgpu_device_suspend(dev, true);</div><div class='hunk'>@@ -1981,10 +2289,11 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_clockgating_state)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_clockgating_state(</div><div class='del'>-			(void *)adev, state);</div><div class='add'>+			&amp;adev-&gt;ip_blocks[i], state);</div><div class='ctx'> 		if (r)</div><div class='del'>-			DRM_ERROR("set_clockgating_state of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"set_clockgating_state of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='ctx'> 	}</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -2015,10 +2324,11 @@ int amdgpu_device_ip_set_powergating_state(void *dev,</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_powergating_state)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_powergating_state(</div><div class='del'>-			(void *)adev, state);</div><div class='add'>+			&amp;adev-&gt;ip_blocks[i], state);</div><div class='ctx'> 		if (r)</div><div class='del'>-			DRM_ERROR("set_powergating_state of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"set_powergating_state of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='ctx'> 	}</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -2043,7 +2353,8 @@ void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;get_clockgating_state)</div><div class='del'>-			adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;get_clockgating_state((void *)adev, flags);</div><div class='add'>+			adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;get_clockgating_state(</div><div class='add'>+				&amp;adev-&gt;ip_blocks[i], flags);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2065,9 +2376,12 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == block_type) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;wait_for_idle((void *)adev);</div><div class='del'>-			if (r)</div><div class='del'>-				return r;</div><div class='add'>+			if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;wait_for_idle) {</div><div class='add'>+				r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;wait_for_idle(</div><div class='add'>+								&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+				if (r)</div><div class='add'>+					return r;</div><div class='add'>+			}</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2076,26 +2390,45 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_device_ip_is_idle - is the hardware IP idle</div><div class='add'>+ * amdgpu_device_ip_is_hw - is the hardware IP enabled</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)</div><div class='ctx'>  *</div><div class='del'>- * Check if the hardware IP is idle or not.</div><div class='del'>- * Returns true if it the IP is idle, false if not.</div><div class='add'>+ * Check if the hardware IP is enable or not.</div><div class='add'>+ * Returns true if it the IP is enable, false if not.</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,</div><div class='del'>-			      enum amd_ip_block_type block_type)</div><div class='add'>+bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev,</div><div class='add'>+			    enum amd_ip_block_type block_type)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='del'>-		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='del'>-			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == block_type)</div><div class='del'>-			return adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;is_idle((void *)adev);</div><div class='add'>+			return adev-&gt;ip_blocks[i].status.hw;</div><div class='ctx'> 	}</div><div class='del'>-	return true;</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_ip_is_valid - is the hardware IP valid</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)</div><div class='add'>+ *</div><div class='add'>+ * Check if the hardware IP is valid or not.</div><div class='add'>+ * Returns true if it the IP is valid, false if not.</div><div class='add'>+ */</div><div class='add'>+bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,</div><div class='add'>+			       enum amd_ip_block_type block_type)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;type == block_type)</div><div class='add'>+			return adev-&gt;ip_blocks[i].status.valid;</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2146,6 +2479,34 @@ int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,</div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const char *ip_block_names[] = {</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_COMMON] = "common",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_GMC] = "gmc",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_IH] = "ih",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_SMC] = "smu",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_PSP] = "psp",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_DCE] = "dce",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_GFX] = "gfx",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_SDMA] = "sdma",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_UVD] = "uvd",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_VCE] = "vce",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_ACP] = "acp",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_VCN] = "vcn",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_MES] = "mes",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_JPEG] = "jpeg",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_VPE] = "vpe",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_ISP] = "isp",</div><div class='add'>+	[AMD_IP_BLOCK_TYPE_RAS] = "ras",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *ip_block_name(struct amdgpu_device *adev, enum amd_ip_block_type type)</div><div class='add'>+{</div><div class='add'>+	int idx = (int)type;</div><div class='add'>+</div><div class='add'>+	return idx &lt; ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : "unknown";</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_ip_block_add</div><div class='ctx'>  *</div><div class='hunk'>@@ -2174,8 +2535,15 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("add ip block number %d &lt;%s&gt;\n", adev-&gt;num_ip_blocks,</div><div class='del'>-		  ip_block_version-&gt;funcs-&gt;name);</div><div class='add'>+	dev_info(adev-&gt;dev, "detected ip block number %d &lt;%s_v%d_%d_%d&gt; (%s)\n",</div><div class='add'>+		 adev-&gt;num_ip_blocks,</div><div class='add'>+		 ip_block_name(adev, ip_block_version-&gt;type),</div><div class='add'>+		 ip_block_version-&gt;major,</div><div class='add'>+		 ip_block_version-&gt;minor,</div><div class='add'>+		 ip_block_version-&gt;rev,</div><div class='add'>+		 ip_block_version-&gt;funcs-&gt;name);</div><div class='add'>+</div><div class='add'>+	adev-&gt;ip_blocks[adev-&gt;num_ip_blocks].adev = adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;ip_blocks[adev-&gt;num_ip_blocks++].version = ip_block_version;</div><div class='ctx'> </div><div class='hunk'>@@ -2191,7 +2559,7 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,</div><div class='ctx'>  * the module parameter virtual_display.  This feature provides a virtual</div><div class='ctx'>  * display hardware on headless boards or in virtualized environments.</div><div class='ctx'>  * This function parses and validates the configuration string specified by</div><div class='del'>- * the user and configues the virtual display configuration (number of</div><div class='add'>+ * the user and configures the virtual display configuration (number of</div><div class='ctx'>  * virtual connectors, crtcs, etc.) specified.</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)</div><div class='hunk'>@@ -2230,9 +2598,11 @@ static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",</div><div class='del'>-			 amdgpu_virtual_display, pci_address_name,</div><div class='del'>-			 adev-&gt;enable_virtual_display, adev-&gt;mode_info.num_crtc);</div><div class='add'>+		dev_info(</div><div class='add'>+			adev-&gt;dev,</div><div class='add'>+			"virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",</div><div class='add'>+			amdgpu_virtual_display, pci_address_name,</div><div class='add'>+			adev-&gt;enable_virtual_display, adev-&gt;mode_info.num_crtc);</div><div class='ctx'> </div><div class='ctx'> 		kfree(pciaddstr);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2243,8 +2613,9 @@ void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) &amp;&amp; !adev-&gt;enable_virtual_display) {</div><div class='ctx'> 		adev-&gt;mode_info.num_crtc = 1;</div><div class='ctx'> 		adev-&gt;enable_virtual_display = true;</div><div class='del'>-		DRM_INFO("virtual_display:%d, num_crtc:%d\n",</div><div class='del'>-			 adev-&gt;enable_virtual_display, adev-&gt;mode_info.num_crtc);</div><div class='add'>+		dev_info(adev-&gt;dev, "virtual_display:%d, num_crtc:%d\n",</div><div class='add'>+			 adev-&gt;enable_virtual_display,</div><div class='add'>+			 adev-&gt;mode_info.num_crtc);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2254,22 +2625,18 @@ void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  *</div><div class='ctx'>  * Parses the asic configuration parameters specified in the gpu info</div><div class='del'>- * firmware and makes them availale to the driver for use in configuring</div><div class='add'>+ * firmware and makes them available to the driver for use in configuring</div><div class='ctx'>  * the asic.</div><div class='ctx'>  * Returns 0 on success, -EINVAL on failure.</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[40];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct gpu_info_firmware_header_v1_0 *hdr;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;firmware.gpu_info_fw = NULL;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mman.discovery_bin)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> 	default:</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -2291,16 +2658,24 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)</div><div class='ctx'> 		chip_name = "arcturus";</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_NAVI12:</div><div class='add'>+		if (adev-&gt;discovery.bin)</div><div class='add'>+			return 0;</div><div class='ctx'> 		chip_name = "navi12";</div><div class='ctx'> 		break;</div><div class='add'>+	case CHIP_CYAN_SKILLFISH:</div><div class='add'>+		if (adev-&gt;discovery.bin)</div><div class='add'>+			return 0;</div><div class='add'>+		chip_name = "cyan_skillfish";</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;firmware.gpu_info_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;firmware.gpu_info_fw,</div><div class='add'>+				   AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+				   "amdgpu/%s_gpu_info.bin", chip_name);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='del'>-			"Failed to get gpu_info firmware \"%s\"\n",</div><div class='del'>-			fw_name);</div><div class='add'>+			"Failed to get gpu_info firmware \"%s_gpu_info.bin\"\n",</div><div class='add'>+			chip_name);</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2315,7 +2690,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)</div><div class='ctx'> 								le32_to_cpu(hdr-&gt;header.ucode_array_offset_bytes));</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='del'>-		 * Should be droped when DAL no longer needs it.</div><div class='add'>+		 * Should be dropped when DAL no longer needs it.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (adev-&gt;asic_type == CHIP_NAVI12)</div><div class='ctx'> 			goto parse_soc_bounding_box;</div><div class='hunk'>@@ -2371,6 +2746,24 @@ out:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_uid_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* Initialize the UID for the device */</div><div class='add'>+	adev-&gt;uid_info = kzalloc(sizeof(struct amdgpu_uid), GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;uid_info) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to allocate memory for UID\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	adev-&gt;uid_info-&gt;adev = adev;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_uid_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* Free the UID memory */</div><div class='add'>+	kfree(adev-&gt;uid_info);</div><div class='add'>+	adev-&gt;uid_info = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_ip_early_init - run early init for hardware IPs</div><div class='ctx'>  *</div><div class='hunk'>@@ -2383,9 +2776,11 @@ out:</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> 	struct pci_dev *parent;</div><div class='add'>+	bool total, skip_bios;</div><div class='add'>+	uint32_t bios_flags;</div><div class='ctx'> 	int i, r;</div><div class='del'>-	bool total;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_enable_virtual_display(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2393,6 +2788,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 		r = amdgpu_virt_request_full_gpu(adev, true);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_virt_init_critical_region(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='hunk'>@@ -2449,6 +2848,13 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Check for IP version 9.4.3 with A0 hardware */</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+	    !amdgpu_device_get_rev_id(adev)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Unsupported A0 hardware\n");</div><div class='add'>+		return -ENODEV;	/* device unsupported - no device error */</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_has_atpx() &amp;&amp;</div><div class='ctx'> 	    (amdgpu_is_atpx_hybrid() ||</div><div class='ctx'> 	     amdgpu_has_atpx_dgpu_power_cntl()) &amp;&amp;</div><div class='hunk'>@@ -2461,7 +2867,6 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;has_pr3 = parent ? pci_pr3_present(parent) : false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	adev-&gt;pm.pp_feature = amdgpu_pp_feature_mask;</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)</div><div class='ctx'> 		adev-&gt;pm.pp_feature &amp;= ~PP_GFXOFF_MASK;</div><div class='hunk'>@@ -2470,27 +2875,35 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!amdgpu_device_pcie_dynamic_switching_supported(adev))</div><div class='ctx'> 		adev-&gt;pm.pp_feature &amp;= ~PP_PCIE_DPM_MASK;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;virt.is_xgmi_node_migrate_enabled = false;</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		adev-&gt;virt.is_xgmi_node_migrate_enabled =</div><div class='add'>+			amdgpu_ip_version((adev), GC_HWIP, 0) == IP_VERSION(9, 4, 4);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	total = true;</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='add'>+		ip_block = &amp;adev-&gt;ip_blocks[i];</div><div class='add'>+</div><div class='ctx'> 		if ((amdgpu_ip_block_mask &amp; (1 &lt;&lt; i)) == 0) {</div><div class='del'>-			DRM_WARN("disabled ip block: %d &lt;%s&gt;\n",</div><div class='del'>-				  i, adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name);</div><div class='add'>+			dev_warn(adev-&gt;dev, "disabled ip block: %d &lt;%s&gt;\n", i,</div><div class='add'>+				 adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name);</div><div class='ctx'> 			adev-&gt;ip_blocks[i].status.valid = false;</div><div class='del'>-		} else {</div><div class='del'>-			if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;early_init) {</div><div class='del'>-				r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;early_init((void *)adev);</div><div class='del'>-				if (r == -ENOENT) {</div><div class='del'>-					adev-&gt;ip_blocks[i].status.valid = false;</div><div class='del'>-				} else if (r) {</div><div class='del'>-					DRM_ERROR("early_init of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-						  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-					total = false;</div><div class='del'>-				} else {</div><div class='del'>-					adev-&gt;ip_blocks[i].status.valid = true;</div><div class='del'>-				}</div><div class='add'>+		} else if (ip_block-&gt;version-&gt;funcs-&gt;early_init) {</div><div class='add'>+			r = ip_block-&gt;version-&gt;funcs-&gt;early_init(ip_block);</div><div class='add'>+			if (r == -ENOENT) {</div><div class='add'>+				adev-&gt;ip_blocks[i].status.valid = false;</div><div class='add'>+			} else if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"early_init of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='add'>+				total = false;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				adev-&gt;ip_blocks[i].status.valid = true;</div><div class='ctx'> 			}</div><div class='add'>+		} else {</div><div class='add'>+			adev-&gt;ip_blocks[i].status.valid = true;</div><div class='ctx'> 		}</div><div class='ctx'> 		/* get the vbios after the asic_funcs are set up */</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_COMMON) {</div><div class='hunk'>@@ -2498,16 +2911,31 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='ctx'> </div><div class='add'>+			bios_flags = amdgpu_device_get_vbios_flags(adev);</div><div class='add'>+			skip_bios = !!(bios_flags &amp; AMDGPU_VBIOS_SKIP);</div><div class='ctx'> 			/* Read BIOS */</div><div class='del'>-			if (amdgpu_device_read_bios(adev)) {</div><div class='del'>-				if (!amdgpu_get_bios(adev))</div><div class='add'>+			if (!skip_bios) {</div><div class='add'>+				bool optional =</div><div class='add'>+					!!(bios_flags &amp; AMDGPU_VBIOS_OPTIONAL);</div><div class='add'>+				if (!amdgpu_get_bios(adev) &amp;&amp; !optional)</div><div class='ctx'> 					return -EINVAL;</div><div class='ctx'> </div><div class='del'>-				r = amdgpu_atombios_init(adev);</div><div class='del'>-				if (r) {</div><div class='del'>-					dev_err(adev-&gt;dev, "amdgpu_atombios_init failed\n");</div><div class='del'>-					amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);</div><div class='del'>-					return r;</div><div class='add'>+				if (optional &amp;&amp; !adev-&gt;bios)</div><div class='add'>+					dev_info(</div><div class='add'>+						adev-&gt;dev,</div><div class='add'>+						"VBIOS image optional, proceeding without VBIOS image");</div><div class='add'>+</div><div class='add'>+				if (adev-&gt;bios) {</div><div class='add'>+					r = amdgpu_atombios_init(adev);</div><div class='add'>+					if (r) {</div><div class='add'>+						dev_err(adev-&gt;dev,</div><div class='add'>+							"amdgpu_atombios_init failed\n");</div><div class='add'>+						amdgpu_vf_error_put(</div><div class='add'>+							adev,</div><div class='add'>+							AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL,</div><div class='add'>+							0, 0);</div><div class='add'>+						return r;</div><div class='add'>+					}</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -2520,7 +2948,15 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!total)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	amdgpu_amdkfd_device_probe(adev);</div><div class='add'>+	if (adev-&gt;gmc.xgmi.supported)</div><div class='add'>+		amdgpu_xgmi_early_init(adev);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_is_multi_aid(adev))</div><div class='add'>+		amdgpu_uid_init(adev);</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);</div><div class='add'>+	if (ip_block-&gt;status.valid != false)</div><div class='add'>+		amdgpu_amdkfd_device_probe(adev);</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;cg_flags &amp;= amdgpu_cg_mask;</div><div class='ctx'> 	adev-&gt;pg_flags &amp;= amdgpu_pg_mask;</div><div class='ctx'> </div><div class='hunk'>@@ -2536,13 +2972,18 @@ static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].status.hw)</div><div class='ctx'> 			continue;</div><div class='add'>+		if (!amdgpu_ip_member_of_hwini(</div><div class='add'>+			    adev, adev-&gt;ip_blocks[i].version-&gt;type))</div><div class='add'>+			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_COMMON ||</div><div class='ctx'> 		    (amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_PSP)) ||</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_IH) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("hw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"hw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='ctx'> 				return r;</div><div class='ctx'> 			}</div><div class='ctx'> 			adev-&gt;ip_blocks[i].status.hw = true;</div><div class='hunk'>@@ -2561,10 +3002,14 @@ static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].status.hw)</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(adev);</div><div class='add'>+		if (!amdgpu_ip_member_of_hwini(</div><div class='add'>+			    adev, adev-&gt;ip_blocks[i].version-&gt;type))</div><div class='add'>+			continue;</div><div class='add'>+		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("hw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"hw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 		adev-&gt;ip_blocks[i].status.hw = true;</div><div class='hunk'>@@ -2584,6 +3029,10 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)</div><div class='ctx'> 			if (adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_PSP)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='add'>+			if (!amdgpu_ip_member_of_hwini(adev,</div><div class='add'>+						       AMD_IP_BLOCK_TYPE_PSP))</div><div class='add'>+				break;</div><div class='add'>+</div><div class='ctx'> 			if (!adev-&gt;ip_blocks[i].status.sw)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='hunk'>@@ -2592,22 +3041,21 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='ctx'> 			if (amdgpu_in_reset(adev) || adev-&gt;in_suspend) {</div><div class='del'>-				r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-				if (r) {</div><div class='del'>-					DRM_ERROR("resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-							  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+				r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+				if (r)</div><div class='ctx'> 					return r;</div><div class='del'>-				}</div><div class='ctx'> 			} else {</div><div class='del'>-				r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(adev);</div><div class='add'>+				r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 				if (r) {</div><div class='del'>-					DRM_ERROR("hw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-							  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+					dev_err(adev-&gt;dev,</div><div class='add'>+						"hw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+						adev-&gt;ip_blocks[i]</div><div class='add'>+							.version-&gt;funcs-&gt;name,</div><div class='add'>+						r);</div><div class='ctx'> 					return r;</div><div class='ctx'> 				}</div><div class='add'>+				adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 			}</div><div class='del'>-</div><div class='del'>-			adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2620,6 +3068,12 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct drm_sched_init_args args = {</div><div class='add'>+		.ops = &amp;amdgpu_sched_ops,</div><div class='add'>+		.num_rqs = DRM_SCHED_PRIORITY_COUNT,</div><div class='add'>+		.timeout_wq = adev-&gt;reset_domain-&gt;wq,</div><div class='add'>+		.dev = adev-&gt;dev,</div><div class='add'>+	};</div><div class='ctx'> 	long timeout;</div><div class='ctx'> 	int r, i;</div><div class='ctx'> </div><div class='hunk'>@@ -2645,32 +3099,36 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		r = drm_sched_init(&amp;ring-&gt;sched, &amp;amdgpu_sched_ops, NULL,</div><div class='del'>-				   DRM_SCHED_PRIORITY_COUNT,</div><div class='del'>-				   ring-&gt;num_hw_submission, 0,</div><div class='del'>-				   timeout, adev-&gt;reset_domain-&gt;wq,</div><div class='del'>-				   ring-&gt;sched_score, ring-&gt;name,</div><div class='del'>-				   adev-&gt;dev);</div><div class='add'>+		args.timeout = timeout;</div><div class='add'>+		args.credit_limit = ring-&gt;num_hw_submission;</div><div class='add'>+		args.score = ring-&gt;sched_score;</div><div class='add'>+		args.name = ring-&gt;name;</div><div class='add'>+</div><div class='add'>+		r = drm_sched_init(&amp;ring-&gt;sched, &amp;args);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to create scheduler on ring %s.\n",</div><div class='del'>-				  ring-&gt;name);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Failed to create scheduler on ring %s.\n",</div><div class='add'>+				ring-&gt;name);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 		r = amdgpu_uvd_entity_init(adev, ring);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",</div><div class='del'>-				  ring-&gt;name);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Failed to create UVD scheduling entity on ring %s.\n",</div><div class='add'>+				ring-&gt;name);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 		r = amdgpu_vce_entity_init(adev, ring);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",</div><div class='del'>-				  ring-&gt;name);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Failed to create VCE scheduling entity on ring %s.\n",</div><div class='add'>+				ring-&gt;name);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_xcp_update_partition_sched_list(adev);</div><div class='add'>+	if (adev-&gt;xcp_mgr)</div><div class='add'>+		amdgpu_xcp_update_partition_sched_list(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2689,6 +3147,7 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	bool init_badpage;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ras_init(adev);</div><div class='hunk'>@@ -2698,19 +3157,28 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_init((void *)adev);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("sw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-			goto init_failed;</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_init) {</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"sw_init of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='add'>+				goto init_failed;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 		adev-&gt;ip_blocks[i].status.sw = true;</div><div class='ctx'> </div><div class='add'>+		if (!amdgpu_ip_member_of_hwini(</div><div class='add'>+			    adev, adev-&gt;ip_blocks[i].version-&gt;type))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_COMMON) {</div><div class='ctx'> 			/* need to do common hw init early so everything is set up for gmc */</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init((void *)adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("hw_init %d failed %d\n", i, r);</div><div class='add'>+				dev_err(adev-&gt;dev, "hw_init %d failed %d\n", i,</div><div class='add'>+					r);</div><div class='ctx'> 				goto init_failed;</div><div class='ctx'> 			}</div><div class='ctx'> 			adev-&gt;ip_blocks[i].status.hw = true;</div><div class='hunk'>@@ -2722,17 +3190,21 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_device_mem_scratch_init(adev);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"amdgpu_mem_scratch_init failed %d\n",</div><div class='add'>+					r);</div><div class='ctx'> 				goto init_failed;</div><div class='ctx'> 			}</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init((void *)adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("hw_init %d failed %d\n", i, r);</div><div class='add'>+				dev_err(adev-&gt;dev, "hw_init %d failed %d\n", i,</div><div class='add'>+					r);</div><div class='ctx'> 				goto init_failed;</div><div class='ctx'> 			}</div><div class='ctx'> 			r = amdgpu_device_wb_init(adev);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"amdgpu_device_wb_init failed %d\n", r);</div><div class='ctx'> 				goto init_failed;</div><div class='ctx'> 			}</div><div class='ctx'> 			adev-&gt;ip_blocks[i].status.hw = true;</div><div class='hunk'>@@ -2744,14 +3216,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> 							       AMDGPU_GEM_DOMAIN_GTT,</div><div class='ctx'> 							       AMDGPU_CSA_SIZE);</div><div class='ctx'> 				if (r) {</div><div class='del'>-					DRM_ERROR("allocate CSA failed %d\n", r);</div><div class='add'>+					dev_err(adev-&gt;dev,</div><div class='add'>+						"allocate CSA failed %d\n", r);</div><div class='ctx'> 					goto init_failed;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_seq64_init(adev);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("allocate seq64 failed %d\n", r);</div><div class='add'>+				dev_err(adev-&gt;dev, "allocate seq64 failed %d\n",</div><div class='add'>+					r);</div><div class='ctx'> 				goto init_failed;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2798,7 +3272,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> 	 * Note: theoretically, this should be called before all vram allocations</div><div class='ctx'> 	 * to protect retired page from abusing</div><div class='ctx'> 	 */</div><div class='del'>-	r = amdgpu_ras_recovery_init(adev);</div><div class='add'>+	init_badpage = (adev-&gt;init_lvl-&gt;level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI);</div><div class='add'>+	r = amdgpu_ras_recovery_init(adev, init_badpage);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto init_failed;</div><div class='ctx'> </div><div class='hunk'>@@ -2838,13 +3313,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_ttm_set_buffer_funcs_status(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	/* Don't init kfd if whole hive need to be reset during init */</div><div class='del'>-	if (!adev-&gt;gmc.xgmi.pending_reset) {</div><div class='add'>+	if (adev-&gt;init_lvl-&gt;level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {</div><div class='ctx'> 		kgd2kfd_init_zone_device(adev);</div><div class='ctx'> 		amdgpu_amdkfd_device_init(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_fru_get_product_info(adev);</div><div class='ctx'> </div><div class='add'>+	if (!amdgpu_sriov_vf(adev) || amdgpu_sriov_ras_cper_en(adev))</div><div class='add'>+		r = amdgpu_cper_init(adev);</div><div class='add'>+</div><div class='ctx'> init_failed:</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -2857,7 +3335,7 @@ init_failed:</div><div class='ctx'>  *</div><div class='ctx'>  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls</div><div class='ctx'>  * this function before a GPU reset.  If the value is retained after a</div><div class='del'>- * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.</div><div class='add'>+ * GPU reset, VRAM has not been lost. Some GPU resets may destroy VRAM contents.</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -2888,6 +3366,8 @@ static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)</div><div class='ctx'> 	 * always assumed to be lost.</div><div class='ctx'> 	 */</div><div class='ctx'> 	switch (amdgpu_asic_reset_method(adev)) {</div><div class='add'>+	case AMD_RESET_METHOD_LEGACY:</div><div class='add'>+	case AMD_RESET_METHOD_LINK:</div><div class='ctx'> 	case AMD_RESET_METHOD_BACO:</div><div class='ctx'> 	case AMD_RESET_METHOD_MODE1:</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -2933,11 +3413,13 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev,</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_JPEG &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_clockgating_state) {</div><div class='ctx'> 			/* enable clockgating to save power */</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_clockgating_state((void *)adev,</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_clockgating_state(&amp;adev-&gt;ip_blocks[i],</div><div class='ctx'> 										     state);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("set_clockgating_state(gate) of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"set_clockgating_state(gate) of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='ctx'> 				return r;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2963,18 +3445,21 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,</div><div class='ctx'> 		    (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_GFX ||</div><div class='ctx'> 		     adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_SDMA))</div><div class='ctx'> 			continue;</div><div class='del'>-		/* skip CG for VCE/UVD, it's handled specially */</div><div class='add'>+		/* skip CG for VCE/UVD/VPE, it's handled specially */</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_UVD &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_VCE &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_VCN &amp;&amp;</div><div class='add'>+		    adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_VPE &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_JPEG &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_powergating_state) {</div><div class='ctx'> 			/* enable powergating to save power */</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_powergating_state((void *)adev,</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;set_powergating_state(&amp;adev-&gt;ip_blocks[i],</div><div class='ctx'> 											state);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("set_powergating_state(gate) of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"set_powergating_state(gate) of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='ctx'> 				return r;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3001,7 +3486,7 @@ static int amdgpu_device_enable_mgpu_fan_boost(void)</div><div class='ctx'> 	for (i = 0; i &lt; mgpu_info.num_dgpu; i++) {</div><div class='ctx'> 		gpu_ins = &amp;(mgpu_info.gpu_ins[i]);</div><div class='ctx'> 		adev = gpu_ins-&gt;adev;</div><div class='del'>-		if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp;</div><div class='add'>+		if (!(adev-&gt;flags &amp; AMD_IS_APU || amdgpu_sriov_multi_vf_mode(adev)) &amp;&amp;</div><div class='ctx'> 		    !gpu_ins-&gt;mgpu_fan_enabled) {</div><div class='ctx'> 			ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);</div><div class='ctx'> 			if (ret)</div><div class='hunk'>@@ -3038,10 +3523,12 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.hw)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init((void *)adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='del'>-				DRM_ERROR("late_init of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"late_init of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='ctx'> 				return r;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3050,11 +3537,12 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ras_late_init(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("amdgpu_ras_late_init failed %d", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "amdgpu_ras_late_init failed %d", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_set_error_query_ready(adev, true);</div><div class='add'>+	if (!amdgpu_reset_in_recovery(adev))</div><div class='add'>+		amdgpu_ras_set_error_query_ready(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);</div><div class='ctx'> 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);</div><div class='hunk'>@@ -3063,7 +3551,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_device_enable_mgpu_fan_boost();</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "enable mgpu fan boost failed (%d).\n", r);</div><div class='ctx'> </div><div class='ctx'> 	/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */</div><div class='ctx'> 	if (amdgpu_passthrough(adev) &amp;&amp;</div><div class='hunk'>@@ -3096,7 +3584,9 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)</div><div class='ctx'> 				r = amdgpu_xgmi_set_pstate(gpu_instance-&gt;adev,</div><div class='ctx'> 						AMDGPU_XGMI_PSTATE_MIN);</div><div class='ctx'> 				if (r) {</div><div class='del'>-					DRM_ERROR("pstate setting failed (%d).\n", r);</div><div class='add'>+					dev_err(adev-&gt;dev,</div><div class='add'>+						"pstate setting failed (%d).\n",</div><div class='add'>+						r);</div><div class='ctx'> 					break;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -3108,6 +3598,27 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_ip_block_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!ip_block-&gt;version-&gt;funcs-&gt;hw_fini) {</div><div class='add'>+		dev_err(adev-&gt;dev, "hw_fini of IP block &lt;%s&gt; not defined\n",</div><div class='add'>+			ip_block-&gt;version-&gt;funcs-&gt;name);</div><div class='add'>+	} else {</div><div class='add'>+		r = ip_block-&gt;version-&gt;funcs-&gt;hw_fini(ip_block);</div><div class='add'>+		/* XXX handle errors */</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_dbg(adev-&gt;dev,</div><div class='add'>+				"hw_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				ip_block-&gt;version-&gt;funcs-&gt;name, r);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ip_block-&gt;status.hw = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_smu_fini_early - smu hw_fini wrapper</div><div class='ctx'>  *</div><div class='hunk'>@@ -3117,7 +3628,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, r;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt; IP_VERSION(9, 0, 0))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -3126,13 +3637,7 @@ static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.hw)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_SMC) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_fini((void *)adev);</div><div class='del'>-			/* XXX handle errors */</div><div class='del'>-			if (r) {</div><div class='del'>-				DRM_DEBUG("hw_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-			}</div><div class='del'>-			adev-&gt;ip_blocks[i].status.hw = false;</div><div class='add'>+			amdgpu_ip_block_hw_fini(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3146,38 +3651,48 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;early_fini)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;early_fini((void *)adev);</div><div class='add'>+		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;early_fini(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_DEBUG("early_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+			dev_dbg(adev-&gt;dev,</div><div class='add'>+				"early_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);</div><div class='ctx'> 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);</div><div class='ctx'> </div><div class='del'>-	amdgpu_amdkfd_suspend(adev, false);</div><div class='add'>+	amdgpu_amdkfd_suspend(adev, true);</div><div class='add'>+	amdgpu_userq_suspend(adev);</div><div class='ctx'> </div><div class='del'>-	/* Workaroud for ASICs need to disable SMC first */</div><div class='add'>+	/* Workaround for ASICs need to disable SMC first */</div><div class='ctx'> 	amdgpu_device_smu_fini_early(adev);</div><div class='ctx'> </div><div class='ctx'> 	for (i = adev-&gt;num_ip_blocks - 1; i &gt;= 0; i--) {</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.hw)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;hw_fini((void *)adev);</div><div class='del'>-		/* XXX handle errors */</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_DEBUG("hw_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='add'>+		amdgpu_ip_block_hw_fini(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		if (amdgpu_virt_release_full_gpu(adev, false))</div><div class='del'>-			DRM_ERROR("failed to release exclusive mode on fini\n");</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"failed to release exclusive mode on fini\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Driver reload on the APU can fail due to firmware validation because</div><div class='add'>+	 * the PSP is always running, as it is shared across the whole SoC.</div><div class='add'>+	 * This same issue does not occur on dGPU because it has a mechanism</div><div class='add'>+	 * that checks whether the PSP is running. A solution for those issues</div><div class='add'>+	 * in the APU is to trigger a GPU reset, but this should be done during</div><div class='add'>+	 * the unload phase to avoid adding boot latency and screen flicker.</div><div class='add'>+	 */</div><div class='add'>+	if ((adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; !adev-&gt;gmc.is_app_apu) {</div><div class='add'>+		r = amdgpu_asic_reset(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			dev_err(adev-&gt;dev, "asic reset on %s failed\n", __func__);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3198,6 +3713,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_cper_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;virt.ras_init_done)</div><div class='ctx'> 		amdgpu_virt_release_ras_err_handler_data(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -3217,13 +3734,17 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_device_mem_scratch_fini(adev);</div><div class='ctx'> 			amdgpu_ib_pool_fini(adev);</div><div class='ctx'> 			amdgpu_seq64_fini(adev);</div><div class='add'>+			amdgpu_doorbell_fini(adev);</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_fini((void *)adev);</div><div class='del'>-		/* XXX handle errors */</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_DEBUG("sw_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_fini) {</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_fini(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+			/* XXX handle errors */</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_dbg(adev-&gt;dev,</div><div class='add'>+					"sw_fini of IP block &lt;%s&gt; failed %d\n",</div><div class='add'>+					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name,</div><div class='add'>+					r);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 		adev-&gt;ip_blocks[i].status.sw = false;</div><div class='ctx'> 		adev-&gt;ip_blocks[i].status.valid = false;</div><div class='hunk'>@@ -3233,11 +3754,12 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.late_initialized)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_fini)</div><div class='del'>-			adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_fini((void *)adev);</div><div class='add'>+			adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_fini(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 		adev-&gt;ip_blocks[i].status.late_initialized = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_fini(adev);</div><div class='add'>+	amdgpu_uid_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3255,7 +3777,7 @@ static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ib_ring_tests(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("ib ring test failed (%d).\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "ib ring test failed (%d).\n", r);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)</div><div class='hunk'>@@ -3266,7 +3788,7 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)</div><div class='ctx'> 	WARN_ON_ONCE(adev-&gt;gfx.gfx_off_state);</div><div class='ctx'> 	WARN_ON_ONCE(adev-&gt;gfx.gfx_off_req_count);</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))</div><div class='add'>+	if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true, 0))</div><div class='ctx'> 		adev-&gt;gfx.gfx_off_state = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3283,7 +3805,7 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, r;</div><div class='add'>+	int i, r, rec;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);</div><div class='ctx'> 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);</div><div class='hunk'>@@ -3304,19 +3826,25 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type != AMD_IP_BLOCK_TYPE_DCE)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		/* XXX handle errors */</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;suspend(adev);</div><div class='del'>-		/* XXX handle errors */</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("suspend of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='add'>+		r = amdgpu_ip_block_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='add'>+			goto unwind;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+unwind:</div><div class='add'>+	rec = amdgpu_device_ip_resume_phase3(adev);</div><div class='add'>+	if (rec)</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"amdgpu_device_ip_resume_phase3 failed during unwind: %d\n",</div><div class='add'>+			rec);</div><div class='add'>+</div><div class='add'>+	amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW);</div><div class='add'>+</div><div class='add'>+	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3332,7 +3860,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, r;</div><div class='add'>+	int i, r, rec;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;in_s0ix)</div><div class='ctx'> 		amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);</div><div class='hunk'>@@ -3351,15 +3879,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* skip unnecessary suspend if we do not initialize them yet */</div><div class='del'>-		if (adev-&gt;gmc.xgmi.pending_reset &amp;&amp;</div><div class='del'>-		    !(adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_GMC ||</div><div class='del'>-		      adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_SMC ||</div><div class='del'>-		      adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_COMMON ||</div><div class='del'>-		      adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_IH)) {</div><div class='del'>-			adev-&gt;ip_blocks[i].status.hw = false;</div><div class='add'>+		if (!amdgpu_ip_member_of_hwini(</div><div class='add'>+			    adev, adev-&gt;ip_blocks[i].version-&gt;type))</div><div class='ctx'> 			continue;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='add'>+		/* Since we skip suspend for S0i3, we need to cancel the delayed</div><div class='add'>+		 * idle work here as the suspend callback never gets called.</div><div class='add'>+		 */</div><div class='add'>+		if (adev-&gt;in_s0ix &amp;&amp;</div><div class='add'>+		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_GFX &amp;&amp;</div><div class='add'>+		    amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(10, 0, 0))</div><div class='add'>+			cancel_delayed_work_sync(&amp;adev-&gt;gfx.idle_work);</div><div class='ctx'> 		/* skip suspend of gfx/mes and psp for S0ix</div><div class='ctx'> 		 * gfx is in gfxoff state, so on resume it will exit gfxoff just</div><div class='ctx'> 		 * like at runtime. PSP is also part of the always on hardware</div><div class='hunk'>@@ -3391,28 +3921,52 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_PSP)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		/* XXX handle errors */</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;suspend(adev);</div><div class='del'>-		/* XXX handle errors */</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("suspend of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='del'>-		}</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='add'>+		r = amdgpu_ip_block_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='add'>+			goto unwind;</div><div class='add'>+</div><div class='ctx'> 		/* handle putting the SMC in the appropriate state */</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_SMC) {</div><div class='ctx'> 				r = amdgpu_dpm_set_mp1_state(adev, adev-&gt;mp1_state);</div><div class='ctx'> 				if (r) {</div><div class='del'>-					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",</div><div class='del'>-							adev-&gt;mp1_state, r);</div><div class='del'>-					return r;</div><div class='add'>+					dev_err(adev-&gt;dev,</div><div class='add'>+						"SMC failed to set mp1 state %d, %d\n",</div><div class='add'>+						adev-&gt;mp1_state, r);</div><div class='add'>+					goto unwind;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+unwind:</div><div class='add'>+	/* suspend phase 2 = resume phase 1 + resume phase 2 */</div><div class='add'>+	rec = amdgpu_device_ip_resume_phase1(adev);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"amdgpu_device_ip_resume_phase1 failed during unwind: %d\n",</div><div class='add'>+			rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rec = amdgpu_device_fw_loading(adev);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"amdgpu_device_fw_loading failed during unwind: %d\n",</div><div class='add'>+			rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rec = amdgpu_device_ip_resume_phase2(adev);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"amdgpu_device_ip_resume_phase2 failed during unwind: %d\n",</div><div class='add'>+			rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3426,7 +3980,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)</div><div class='ctx'>  * in each IP into a state suitable for suspend.</div><div class='ctx'>  * Returns 0 on success, negative error code on failure.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_device_ip_suspend(struct amdgpu_device *adev)</div><div class='add'>+static int amdgpu_device_ip_suspend(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -3472,10 +4026,12 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 				!block-&gt;status.valid)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			r = block-&gt;version-&gt;funcs-&gt;hw_init(adev);</div><div class='del'>-			DRM_INFO("RE-INIT-early: %s %s\n", block-&gt;version-&gt;funcs-&gt;name, r?"failed":"succeeded");</div><div class='del'>-			if (r)</div><div class='add'>+			r = block-&gt;version-&gt;funcs-&gt;hw_init(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev, "RE-INIT-early: %s failed\n",</div><div class='add'>+					 block-&gt;version-&gt;funcs-&gt;name);</div><div class='ctx'> 				return r;</div><div class='add'>+			}</div><div class='ctx'> 			block-&gt;status.hw = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3485,7 +4041,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, r;</div><div class='add'>+	struct amdgpu_ip_block *block;</div><div class='add'>+	int i, r = 0;</div><div class='ctx'> </div><div class='ctx'> 	static enum amd_ip_block_type ip_order[] = {</div><div class='ctx'> 		AMD_IP_BLOCK_TYPE_SMC,</div><div class='hunk'>@@ -3500,30 +4057,28 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(ip_order); i++) {</div><div class='del'>-		int j;</div><div class='del'>-		struct amdgpu_ip_block *block;</div><div class='add'>+		block = amdgpu_device_ip_get_ip_block(adev, ip_order[i]);</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; adev-&gt;num_ip_blocks; j++) {</div><div class='del'>-			block = &amp;adev-&gt;ip_blocks[j];</div><div class='del'>-</div><div class='del'>-			if (block-&gt;version-&gt;type != ip_order[i] ||</div><div class='del'>-				!block-&gt;status.valid ||</div><div class='del'>-				block-&gt;status.hw)</div><div class='del'>-				continue;</div><div class='add'>+		if (!block)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-			if (block-&gt;version-&gt;type == AMD_IP_BLOCK_TYPE_SMC)</div><div class='del'>-				r = block-&gt;version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-			else</div><div class='del'>-				r = block-&gt;version-&gt;funcs-&gt;hw_init(adev);</div><div class='add'>+		if (block-&gt;status.valid &amp;&amp; !block-&gt;status.hw) {</div><div class='add'>+			if (block-&gt;version-&gt;type == AMD_IP_BLOCK_TYPE_SMC) {</div><div class='add'>+				r = amdgpu_ip_block_resume(block);</div><div class='add'>+			} else {</div><div class='add'>+				r = block-&gt;version-&gt;funcs-&gt;hw_init(block);</div><div class='add'>+			}</div><div class='ctx'> </div><div class='del'>-			DRM_INFO("RE-INIT-late: %s %s\n", block-&gt;version-&gt;funcs-&gt;name, r?"failed":"succeeded");</div><div class='del'>-			if (r)</div><div class='del'>-				return r;</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev, "RE-INIT-late: %s failed\n",</div><div class='add'>+					 block-&gt;version-&gt;funcs-&gt;name);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='ctx'> 			block-&gt;status.hw = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3550,13 +4105,9 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_IH ||</div><div class='ctx'> 		    (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_PSP &amp;&amp; amdgpu_sriov_vf(adev))) {</div><div class='ctx'> </div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-			if (r) {</div><div class='del'>-				DRM_ERROR("resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+			r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+			if (r)</div><div class='ctx'> 				return r;</div><div class='del'>-			}</div><div class='del'>-			adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3568,7 +4119,7 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  *</div><div class='del'>- * First resume function for hardware IPs.  The list of all the hardware</div><div class='add'>+ * Second resume function for hardware IPs.  The list of all the hardware</div><div class='ctx'>  * IPs that make up the asic is walked and the resume callbacks are run for</div><div class='ctx'>  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a</div><div class='ctx'>  * functional state after a suspend and updates the software state as</div><div class='hunk'>@@ -3586,15 +4137,42 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_COMMON ||</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_GMC ||</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_IH ||</div><div class='add'>+		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_DCE ||</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_PSP)</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				  adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='ctx'> 			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_ip_resume_phase3 - run resume for hardware IPs</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Third resume function for hardware IPs.  The list of all the hardware</div><div class='add'>+ * IPs that make up the asic is walked and the resume callbacks are run for</div><div class='add'>+ * all DCE.  resume puts the hardware into a functional state after a suspend</div><div class='add'>+ * and updates the software state as necessary.  This function is also used</div><div class='add'>+ * for restoring the GPU after a GPU reset.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 on success, negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='add'>+		if (!adev-&gt;ip_blocks[i].status.valid || adev-&gt;ip_blocks[i].status.hw)</div><div class='add'>+			continue;</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_DCE) {</div><div class='add'>+			r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='ctx'> 		}</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3629,6 +4207,13 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;mman.buffer_funcs_ring-&gt;sched.ready)</div><div class='ctx'> 		amdgpu_ttm_set_buffer_funcs_status(adev, true);</div><div class='ctx'> </div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	amdgpu_fence_driver_hw_init(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_ip_resume_phase3(adev);</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3658,12 +4243,14 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic</div><div class='ctx'>  *</div><div class='add'>+ * @pdev : pci device context</div><div class='ctx'>  * @asic_type: AMD asic type</div><div class='ctx'>  *</div><div class='ctx'>  * Check if there is DC (new modesetting infrastructre) support for an asic.</div><div class='ctx'>  * returns true if DC has support, false if not.</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)</div><div class='add'>+bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev,</div><div class='add'>+				       enum amd_asic_type asic_type)</div><div class='ctx'> {</div><div class='ctx'> 	switch (asic_type) {</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_SI</div><div class='hunk'>@@ -3677,25 +4264,13 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)</div><div class='ctx'> 	case CHIP_PITCAIRN:</div><div class='ctx'> 	case CHIP_VERDE:</div><div class='ctx'> 	case CHIP_OLAND:</div><div class='del'>-		/*</div><div class='del'>-		 * We have systems in the wild with these ASICs that require</div><div class='del'>-		 * LVDS and VGA support which is not supported with DC.</div><div class='del'>-		 *</div><div class='del'>-		 * Fallback to the non-DC driver here by default so as not to</div><div class='del'>-		 * cause regressions.</div><div class='del'>-		 */</div><div class='del'>-#if defined(CONFIG_DRM_AMD_DC_SI)</div><div class='del'>-		return amdgpu_dc &gt; 0;</div><div class='del'>-#else</div><div class='del'>-		return false;</div><div class='del'>-#endif</div><div class='del'>-	case CHIP_BONAIRE:</div><div class='add'>+		return amdgpu_dc != 0 &amp;&amp; IS_ENABLED(CONFIG_DRM_AMD_DC_SI);</div><div class='ctx'> 	case CHIP_KAVERI:</div><div class='ctx'> 	case CHIP_KABINI:</div><div class='ctx'> 	case CHIP_MULLINS:</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * We have systems in the wild with these ASICs that require</div><div class='del'>-		 * VGA support which is not supported with DC.</div><div class='add'>+		 * TRAVIS and NUTMEG support which is not supported with DC.</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * Fallback to the non-DC driver here by default so as not to</div><div class='ctx'> 		 * cause regressions.</div><div class='hunk'>@@ -3706,7 +4281,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)</div><div class='ctx'> #else</div><div class='ctx'> 	default:</div><div class='ctx'> 		if (amdgpu_dc &gt; 0)</div><div class='del'>-			DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");</div><div class='add'>+			dev_info_once(</div><div class='add'>+				&amp;pdev-&gt;dev,</div><div class='add'>+				"Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> #endif</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3725,7 +4302,7 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)</div><div class='ctx'> 	    (adev-&gt;harvest_ip_mask &amp; AMD_HARVEST_IP_DMU_MASK))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	return amdgpu_device_asic_has_dc_support(adev-&gt;asic_type);</div><div class='add'>+	return amdgpu_device_asic_has_dc_support(adev-&gt;pdev, adev-&gt;asic_type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)</div><div class='hunk'>@@ -3747,13 +4324,13 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)</div><div class='ctx'> 	if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {</div><div class='ctx'> </div><div class='ctx'> 		task_barrier_enter(&amp;hive-&gt;tb);</div><div class='del'>-		adev-&gt;asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));</div><div class='add'>+		adev-&gt;asic_reset_res = amdgpu_device_baco_enter(adev);</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;asic_reset_res)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> </div><div class='ctx'> 		task_barrier_exit(&amp;hive-&gt;tb);</div><div class='del'>-		adev-&gt;asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));</div><div class='add'>+		adev-&gt;asic_reset_res = amdgpu_device_baco_exit(adev);</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;asic_reset_res)</div><div class='ctx'> 			goto fail;</div><div class='hunk'>@@ -3767,7 +4344,8 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='ctx'> 	if (adev-&gt;asic_reset_res)</div><div class='del'>-		DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "ASIC reset failed with error, %d for drm dev, %s",</div><div class='ctx'> 			 adev-&gt;asic_reset_res, adev_to_drm(adev)-&gt;unique);</div><div class='ctx'> 	amdgpu_put_xgmi_hive(hive);</div><div class='ctx'> }</div><div class='hunk'>@@ -3780,66 +4358,53 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)</div><div class='ctx'> 	long timeout;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * By default timeout for non compute jobs is 10000</div><div class='del'>-	 * and 60000 for compute jobs.</div><div class='del'>-	 * In SR-IOV or passthrough mode, timeout for compute</div><div class='del'>-	 * jobs are 60000 by default.</div><div class='del'>-	 */</div><div class='del'>-	adev-&gt;gfx_timeout = msecs_to_jiffies(10000);</div><div class='del'>-	adev-&gt;sdma_timeout = adev-&gt;video_timeout = adev-&gt;gfx_timeout;</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?</div><div class='del'>-					msecs_to_jiffies(60000) : msecs_to_jiffies(10000);</div><div class='del'>-	else</div><div class='del'>-		adev-&gt;compute_timeout =  msecs_to_jiffies(60000);</div><div class='add'>+	/* By default timeout for all queues is 2 sec */</div><div class='add'>+	adev-&gt;gfx_timeout = adev-&gt;compute_timeout = adev-&gt;sdma_timeout =</div><div class='add'>+		adev-&gt;video_timeout = msecs_to_jiffies(2000);</div><div class='ctx'> </div><div class='del'>-	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {</div><div class='del'>-		while ((timeout_setting = strsep(&amp;input, ",")) &amp;&amp;</div><div class='del'>-				strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {</div><div class='del'>-			ret = kstrtol(timeout_setting, 0, &amp;timeout);</div><div class='del'>-			if (ret)</div><div class='del'>-				return ret;</div><div class='add'>+	if (!strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-			if (timeout == 0) {</div><div class='del'>-				index++;</div><div class='del'>-				continue;</div><div class='del'>-			} else if (timeout &lt; 0) {</div><div class='del'>-				timeout = MAX_SCHEDULE_TIMEOUT;</div><div class='del'>-				dev_warn(adev-&gt;dev, "lockup timeout disabled");</div><div class='del'>-				add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);</div><div class='del'>-			} else {</div><div class='del'>-				timeout = msecs_to_jiffies(timeout);</div><div class='del'>-			}</div><div class='add'>+	while ((timeout_setting = strsep(&amp;input, ",")) &amp;&amp;</div><div class='add'>+	       strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {</div><div class='add'>+		ret = kstrtol(timeout_setting, 0, &amp;timeout);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='del'>-			switch (index++) {</div><div class='del'>-			case 0:</div><div class='del'>-				adev-&gt;gfx_timeout = timeout;</div><div class='del'>-				break;</div><div class='del'>-			case 1:</div><div class='del'>-				adev-&gt;compute_timeout = timeout;</div><div class='del'>-				break;</div><div class='del'>-			case 2:</div><div class='del'>-				adev-&gt;sdma_timeout = timeout;</div><div class='del'>-				break;</div><div class='del'>-			case 3:</div><div class='del'>-				adev-&gt;video_timeout = timeout;</div><div class='del'>-				break;</div><div class='del'>-			default:</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='add'>+		if (timeout == 0) {</div><div class='add'>+			index++;</div><div class='add'>+			continue;</div><div class='add'>+		} else if (timeout &lt; 0) {</div><div class='add'>+			timeout = MAX_SCHEDULE_TIMEOUT;</div><div class='add'>+			dev_warn(adev-&gt;dev, "lockup timeout disabled");</div><div class='add'>+			add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);</div><div class='add'>+		} else {</div><div class='add'>+			timeout = msecs_to_jiffies(timeout);</div><div class='ctx'> 		}</div><div class='del'>-		/*</div><div class='del'>-		 * There is only one value specified and</div><div class='del'>-		 * it should apply to all non-compute jobs.</div><div class='del'>-		 */</div><div class='del'>-		if (index == 1) {</div><div class='del'>-			adev-&gt;sdma_timeout = adev-&gt;video_timeout = adev-&gt;gfx_timeout;</div><div class='del'>-			if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))</div><div class='del'>-				adev-&gt;compute_timeout = adev-&gt;gfx_timeout;</div><div class='add'>+</div><div class='add'>+		switch (index++) {</div><div class='add'>+		case 0:</div><div class='add'>+			adev-&gt;gfx_timeout = timeout;</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			adev-&gt;compute_timeout = timeout;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			adev-&gt;sdma_timeout = timeout;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			adev-&gt;video_timeout = timeout;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* When only one value specified apply it to all queues. */</div><div class='add'>+	if (index == 1)</div><div class='add'>+		adev-&gt;gfx_timeout = adev-&gt;compute_timeout = adev-&gt;sdma_timeout =</div><div class='add'>+			adev-&gt;video_timeout = timeout;</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3859,10 +4424,26 @@ static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ram_is_direct_mapped = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct attribute *amdgpu_dev_attributes[] = {</div><div class='del'>-	&amp;dev_attr_pcie_replay_count.attr,</div><div class='del'>-	NULL</div><div class='del'>-};</div><div class='add'>+#if defined(CONFIG_HSA_AMD_P2P)</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_check_iommu_remap - Check if DMA remapping is enabled.</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * return if IOMMU remapping bar address</div><div class='add'>+ */</div><div class='add'>+static bool amdgpu_device_check_iommu_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct iommu_domain *domain;</div><div class='add'>+</div><div class='add'>+	domain = iommu_get_domain_for_dev(adev-&gt;dev);</div><div class='add'>+	if (domain &amp;&amp; (domain-&gt;type == IOMMU_DOMAIN_DMA ||</div><div class='add'>+		domain-&gt;type ==	IOMMU_DOMAIN_DMA_FQ))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -3875,7 +4456,56 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;gfx.mcbp = true;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.mcbp)</div><div class='del'>-		DRM_INFO("MCBP is enabled\n");</div><div class='add'>+		dev_info(adev-&gt;dev, "MCBP is enabled\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_atombios_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"registering atombios sysfs failed (%d).\n", r);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_pm_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "registering pm sysfs failed (%d).\n", r);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ucode_sysfs_init(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		adev-&gt;ucode_sysfs_en = false;</div><div class='add'>+		dev_err(adev-&gt;dev, "Creating firmware sysfs failed (%d).\n", r);</div><div class='add'>+	} else</div><div class='add'>+		adev-&gt;ucode_sysfs_en = true;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_attr_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "Could not create amdgpu device attr\n");</div><div class='add'>+</div><div class='add'>+	r = devm_device_add_group(adev-&gt;dev, &amp;amdgpu_board_attrs_group);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Could not create amdgpu board attributes\n");</div><div class='add'>+</div><div class='add'>+	amdgpu_fru_sysfs_init(adev);</div><div class='add'>+	amdgpu_reg_state_sysfs_init(adev);</div><div class='add'>+	amdgpu_xcp_sysfs_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_sys_interface_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;pm.sysfs_initialized)</div><div class='add'>+		amdgpu_pm_sysfs_fini(adev);</div><div class='add'>+	if (adev-&gt;ucode_sysfs_en)</div><div class='add'>+		amdgpu_ucode_sysfs_fini(adev);</div><div class='add'>+	amdgpu_device_attr_sysfs_fini(adev);</div><div class='add'>+	amdgpu_fru_sysfs_fini(adev);</div><div class='add'>+</div><div class='add'>+	amdgpu_reg_state_sysfs_fini(adev);</div><div class='add'>+	amdgpu_xcp_sysfs_fini(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3891,7 +4521,6 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)</div><div class='ctx'> int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 		       uint32_t flags)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *ddev = adev_to_drm(adev);</div><div class='ctx'> 	struct pci_dev *pdev = adev-&gt;pdev;</div><div class='ctx'> 	int r, i;</div><div class='ctx'> 	bool px = false;</div><div class='hunk'>@@ -3943,9 +4572,11 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 	adev-&gt;audio_endpt_rreg = &amp;amdgpu_block_invalid_rreg;</div><div class='ctx'> 	adev-&gt;audio_endpt_wreg = &amp;amdgpu_block_invalid_wreg;</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",</div><div class='del'>-		 amdgpu_asic_name[adev-&gt;asic_type], pdev-&gt;vendor, pdev-&gt;device,</div><div class='del'>-		 pdev-&gt;subsystem_vendor, pdev-&gt;subsystem_device, pdev-&gt;revision);</div><div class='add'>+	dev_info(</div><div class='add'>+		adev-&gt;dev,</div><div class='add'>+		"initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",</div><div class='add'>+		amdgpu_asic_name[adev-&gt;asic_type], pdev-&gt;vendor, pdev-&gt;device,</div><div class='add'>+		pdev-&gt;subsystem_vendor, pdev-&gt;subsystem_device, pdev-&gt;revision);</div><div class='ctx'> </div><div class='ctx'> 	/* mutex initialization are all done here so we</div><div class='ctx'> 	 * can recall function without having locking issues</div><div class='hunk'>@@ -3965,6 +4596,17 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 	mutex_init(&amp;adev-&gt;notifier_lock);</div><div class='ctx'> 	mutex_init(&amp;adev-&gt;pm.stable_pstate_ctx_lock);</div><div class='ctx'> 	mutex_init(&amp;adev-&gt;benchmark_mutex);</div><div class='add'>+	mutex_init(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='add'>+	/* Initialize the mutex for cleaner shader isolation between GFX and compute processes */</div><div class='add'>+	mutex_init(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; ++i) {</div><div class='add'>+		adev-&gt;isolation[i].spearhead = dma_fence_get_stub();</div><div class='add'>+		amdgpu_sync_create(&amp;adev-&gt;isolation[i].active);</div><div class='add'>+		amdgpu_sync_create(&amp;adev-&gt;isolation[i].prev);</div><div class='add'>+	}</div><div class='add'>+	mutex_init(&amp;adev-&gt;gfx.userq_sch_mutex);</div><div class='add'>+	mutex_init(&amp;adev-&gt;gfx.workload_profile_mutex);</div><div class='add'>+	mutex_init(&amp;adev-&gt;vcn.workload_profile_mutex);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_init_apu_flags(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -3981,9 +4623,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 	spin_lock_init(&amp;adev-&gt;se_cac_idx_lock);</div><div class='ctx'> 	spin_lock_init(&amp;adev-&gt;audio_endpt_idx_lock);</div><div class='ctx'> 	spin_lock_init(&amp;adev-&gt;mm_stats.lock);</div><div class='add'>+	spin_lock_init(&amp;adev-&gt;virt.rlcg_reg_lock);</div><div class='add'>+	spin_lock_init(&amp;adev-&gt;wb.lock);</div><div class='ctx'> </div><div class='del'>-	INIT_LIST_HEAD(&amp;adev-&gt;shadow_list);</div><div class='del'>-	mutex_init(&amp;adev-&gt;shadow_list_lock);</div><div class='add'>+	xa_init_flags(&amp;adev-&gt;userq_xa, XA_FLAGS_LOCK_IRQ);</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;adev-&gt;reset_list);</div><div class='ctx'> </div><div class='hunk'>@@ -3991,12 +4634,30 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;adev-&gt;pm.od_kobj_list);</div><div class='ctx'> </div><div class='add'>+	xa_init(&amp;adev-&gt;userq_doorbell_xa);</div><div class='add'>+</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;adev-&gt;delayed_init_work,</div><div class='ctx'> 			  amdgpu_device_delayed_init_work_handler);</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;adev-&gt;gfx.gfx_off_delay_work,</div><div class='ctx'> 			  amdgpu_device_delay_enable_gfx_off);</div><div class='add'>+	/*</div><div class='add'>+	 * Initialize the enforce_isolation work structures for each XCP</div><div class='add'>+	 * partition.  This work handler is responsible for enforcing shader</div><div class='add'>+	 * isolation on AMD GPUs.  It counts the number of emitted fences for</div><div class='add'>+	 * each GFX and compute ring.  If there are any fences, it schedules</div><div class='add'>+	 * the `enforce_isolation_work` to be run after a delay.  If there are</div><div class='add'>+	 * no fences, it signals the Kernel Fusion Driver (KFD) to resume the</div><div class='add'>+	 * runqueue.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; i++) {</div><div class='add'>+		INIT_DELAYED_WORK(&amp;adev-&gt;gfx.enforce_isolation[i].work,</div><div class='add'>+				  amdgpu_gfx_enforce_isolation_handler);</div><div class='add'>+		adev-&gt;gfx.enforce_isolation[i].adev = adev;</div><div class='add'>+		adev-&gt;gfx.enforce_isolation[i].xcp_id = i;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	INIT_WORK(&amp;adev-&gt;xgmi_reset_work, amdgpu_device_xgmi_reset_func);</div><div class='add'>+	INIT_WORK(&amp;adev-&gt;userq_reset_work, amdgpu_userq_reset_work);</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.gfx_off_req_count = 1;</div><div class='ctx'> 	adev-&gt;gfx.gfx_off_residency = 0;</div><div class='hunk'>@@ -4012,6 +4673,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 	 * for throttling interrupt) = 60 seconds.</div><div class='ctx'> 	 */</div><div class='ctx'> 	ratelimit_state_init(&amp;adev-&gt;throttling_logging_rs, (60 - 1) * HZ, 1);</div><div class='add'>+</div><div class='ctx'> 	ratelimit_set_flags(&amp;adev-&gt;throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);</div><div class='ctx'> </div><div class='ctx'> 	/* Registers mapping */</div><div class='hunk'>@@ -4031,12 +4693,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!adev-&gt;rmmio)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev-&gt;rmmio_base);</div><div class='del'>-	DRM_INFO("register mmio size: %u\n", (unsigned int)adev-&gt;rmmio_size);</div><div class='add'>+	dev_info(adev-&gt;dev, "register mmio base: 0x%08X\n",</div><div class='add'>+		 (uint32_t)adev-&gt;rmmio_base);</div><div class='add'>+	dev_info(adev-&gt;dev, "register mmio size: %u\n",</div><div class='add'>+		 (unsigned int)adev-&gt;rmmio_size);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Reset domain needs to be present early, before XGMI hive discovered</div><div class='del'>-	 * (if any) and intitialized to use reset sem and in_gpu reset flag</div><div class='add'>+	 * (if any) and initialized to use reset sem and in_gpu reset flag</div><div class='ctx'> 	 * early on during init and before calling to RREG32.</div><div class='ctx'> 	 */</div><div class='ctx'> 	adev-&gt;reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");</div><div class='hunk'>@@ -4044,7 +4708,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	/* detect hw virtualization here */</div><div class='del'>-	amdgpu_detect_virtualization(adev);</div><div class='add'>+	amdgpu_virt_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_get_pcie_info(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -4056,19 +4720,39 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_set_mcbp(adev);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * By default, use default mode where all blocks are expected to be</div><div class='add'>+	 * initialized. At present a 'swinit' of blocks is required to be</div><div class='add'>+	 * completed before the need for a different level is detected.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_DEFAULT);</div><div class='ctx'> 	/* early init functions */</div><div class='ctx'> 	r = amdgpu_device_ip_early_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	/* Get rid of things like offb */</div><div class='del'>-	r = drm_aperture_remove_conflicting_pci_framebuffers(adev-&gt;pdev, &amp;amdgpu_kms_driver);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	/*</div><div class='add'>+	 * No need to remove conflicting FBs for non-display class devices.</div><div class='add'>+	 * This prevents the sysfb from being freed accidently.</div><div class='add'>+	 */</div><div class='add'>+	if ((pdev-&gt;class &gt;&gt; 8) == PCI_CLASS_DISPLAY_VGA ||</div><div class='add'>+	    (pdev-&gt;class &gt;&gt; 8) == PCI_CLASS_DISPLAY_OTHER) {</div><div class='add'>+		/* Get rid of things like offb */</div><div class='add'>+		r = aperture_remove_conflicting_pci_devices(adev-&gt;pdev, amdgpu_kms_driver.name);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Enable TMZ based on IP_VERSION */</div><div class='ctx'> 	amdgpu_gmc_tmz_set(adev);</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(10, 3, 0))</div><div class='add'>+		/* VF MMIO access (except mailbox range) from CPU</div><div class='add'>+		 * will be blocked during sriov runtime</div><div class='add'>+		 */</div><div class='add'>+		adev-&gt;virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_gmc_noretry_set(adev);</div><div class='ctx'> 	/* Need to get xgmi info early to decide the reset behavior*/</div><div class='ctx'> 	if (adev-&gt;gmc.xgmi.supported) {</div><div class='hunk'>@@ -4121,32 +4805,24 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev) &amp;&amp; amdgpu_asic_need_reset_on_init(adev)) {</div><div class='ctx'> 		if (adev-&gt;gmc.xgmi.num_physical_nodes) {</div><div class='ctx'> 			dev_info(adev-&gt;dev, "Pending hive reset.\n");</div><div class='del'>-			adev-&gt;gmc.xgmi.pending_reset = true;</div><div class='del'>-			/* Only need to init necessary block for SMU to handle the reset */</div><div class='del'>-			for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='del'>-				if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='del'>-					continue;</div><div class='del'>-				if (!(adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_GMC ||</div><div class='del'>-				      adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_COMMON ||</div><div class='del'>-				      adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_IH ||</div><div class='del'>-				      adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_SMC)) {</div><div class='del'>-					DRM_DEBUG("IP %s disabled for hw_init.\n",</div><div class='del'>-						adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name);</div><div class='del'>-					adev-&gt;ip_blocks[i].status.hw = true;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='add'>+			amdgpu_set_init_level(adev,</div><div class='add'>+					      AMDGPU_INIT_LEVEL_MINIMAL_XGMI);</div><div class='add'>+		} else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &amp;&amp;</div><div class='add'>+				   !amdgpu_device_has_display_hardware(adev)) {</div><div class='add'>+					r = psp_gpu_reset(adev);</div><div class='ctx'> 		} else {</div><div class='del'>-			tmp = amdgpu_reset_method;</div><div class='del'>-			/* It should do a default reset when loading or reloading the driver,</div><div class='del'>-			 * regardless of the module parameter reset_method.</div><div class='del'>-			 */</div><div class='del'>-			amdgpu_reset_method = AMD_RESET_METHOD_NONE;</div><div class='del'>-			r = amdgpu_asic_reset(adev);</div><div class='del'>-			amdgpu_reset_method = tmp;</div><div class='del'>-			if (r) {</div><div class='del'>-				dev_err(adev-&gt;dev, "asic reset on init failed\n");</div><div class='del'>-				goto failed;</div><div class='del'>-			}</div><div class='add'>+				tmp = amdgpu_reset_method;</div><div class='add'>+				/* It should do a default reset when loading or reloading the driver,</div><div class='add'>+				 * regardless of the module parameter reset_method.</div><div class='add'>+				 */</div><div class='add'>+				amdgpu_reset_method = AMD_RESET_METHOD_NONE;</div><div class='add'>+				r = amdgpu_asic_reset(adev);</div><div class='add'>+				amdgpu_reset_method = tmp;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (r) {</div><div class='add'>+		  dev_err(adev-&gt;dev, "asic reset on init failed\n");</div><div class='add'>+		  goto failed;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -4157,7 +4833,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto failed;</div><div class='ctx'> 		}</div><div class='del'>-		DRM_INFO("GPU posting now...\n");</div><div class='add'>+		dev_info(adev-&gt;dev, "GPU posting now...\n");</div><div class='ctx'> 		r = amdgpu_device_asic_init(adev);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "gpu post error!\n");</div><div class='hunk'>@@ -4183,8 +4859,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,</div><div class='ctx'> 				goto failed;</div><div class='ctx'> 			}</div><div class='ctx'> 			/* init i2c buses */</div><div class='del'>-			if (!amdgpu_device_has_dc_support(adev))</div><div class='del'>-				amdgpu_atombios_i2c_init(adev);</div><div class='add'>+			amdgpu_i2c_init(adev);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -4238,7 +4913,7 @@ fence_driver_init:</div><div class='ctx'> 	/* enable clockgating, etc. after ib tests, etc. since some blocks require</div><div class='ctx'> 	 * explicit gating rather than handling it automatically.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!adev-&gt;gmc.xgmi.pending_reset) {</div><div class='add'>+	if (adev-&gt;init_lvl-&gt;level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {</div><div class='ctx'> 		r = amdgpu_device_ip_late_init(adev);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "amdgpu_device_ip_late_init failed\n");</div><div class='hunk'>@@ -4256,38 +4931,14 @@ fence_driver_init:</div><div class='ctx'> 		flush_delayed_work(&amp;adev-&gt;delayed_init_work);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;init_lvl-&gt;level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI)</div><div class='add'>+		amdgpu_xgmi_reset_on_init(adev);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Place those sysfs registering after `late_init`. As some of those</div><div class='ctx'> 	 * operations performed in `late_init` might affect the sysfs</div><div class='ctx'> 	 * interfaces creating.</div><div class='ctx'> 	 */</div><div class='del'>-	r = amdgpu_atombios_sysfs_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		drm_err(&amp;adev-&gt;ddev,</div><div class='del'>-			"registering atombios sysfs failed (%d).\n", r);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_pm_sysfs_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		DRM_ERROR("registering pm sysfs failed (%d).\n", r);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_ucode_sysfs_init(adev);</div><div class='del'>-	if (r) {</div><div class='del'>-		adev-&gt;ucode_sysfs_en = false;</div><div class='del'>-		DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);</div><div class='del'>-	} else</div><div class='del'>-		adev-&gt;ucode_sysfs_en = true;</div><div class='del'>-</div><div class='del'>-	r = sysfs_create_files(&amp;adev-&gt;dev-&gt;kobj, amdgpu_dev_attributes);</div><div class='del'>-	if (r)</div><div class='del'>-		dev_err(adev-&gt;dev, "Could not create amdgpu device attr\n");</div><div class='del'>-</div><div class='del'>-	r = devm_device_add_group(adev-&gt;dev, &amp;amdgpu_board_attrs_group);</div><div class='del'>-	if (r)</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			"Could not create amdgpu board attributes\n");</div><div class='del'>-</div><div class='del'>-	amdgpu_fru_sysfs_init(adev);</div><div class='del'>-	amdgpu_reg_state_sysfs_init(adev);</div><div class='add'>+	r = amdgpu_device_sys_interface_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ENABLED(CONFIG_PERF_EVENTS))</div><div class='ctx'> 		r = amdgpu_pmu_init(adev);</div><div class='hunk'>@@ -4305,7 +4956,7 @@ fence_driver_init:</div><div class='ctx'> 	if ((adev-&gt;pdev-&gt;class &gt;&gt; 8) == PCI_CLASS_DISPLAY_VGA)</div><div class='ctx'> 		vga_client_register(adev-&gt;pdev, amdgpu_device_vga_set_decode);</div><div class='ctx'> </div><div class='del'>-	px = amdgpu_device_supports_px(ddev);</div><div class='add'>+	px = amdgpu_device_supports_px(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (px || (!dev_is_removable(&amp;adev-&gt;pdev-&gt;dev) &amp;&amp;</div><div class='ctx'> 				apple_gmux_detect(NULL, NULL)))</div><div class='hunk'>@@ -4315,12 +4966,13 @@ fence_driver_init:</div><div class='ctx'> 	if (px)</div><div class='ctx'> 		vga_switcheroo_init_domain_pm_ops(adev-&gt;dev, &amp;adev-&gt;vga_pm_domain);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.xgmi.pending_reset)</div><div class='del'>-		queue_delayed_work(system_wq, &amp;mgpu_info.delayed_reset_work,</div><div class='del'>-				   msecs_to_jiffies(AMDGPU_RESUME_MS));</div><div class='del'>-</div><div class='ctx'> 	amdgpu_device_check_iommu_direct_map(adev);</div><div class='ctx'> </div><div class='add'>+	adev-&gt;pm_nb.notifier_call = amdgpu_device_pm_notifier;</div><div class='add'>+	r = register_pm_notifier(&amp;adev-&gt;pm_nb);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failed;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> release_ras_con:</div><div class='hunk'>@@ -4380,8 +5032,13 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	dev_info(adev-&gt;dev, "amdgpu: finishing device.\n");</div><div class='ctx'> 	flush_delayed_work(&amp;adev-&gt;delayed_init_work);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;mman.initialized)</div><div class='add'>+		drain_workqueue(adev-&gt;mman.bdev.wq);</div><div class='ctx'> 	adev-&gt;shutdown = true;</div><div class='ctx'> </div><div class='add'>+	unregister_pm_notifier(&amp;adev-&gt;pm_nb);</div><div class='add'>+</div><div class='ctx'> 	/* make sure IB test finished before entering exclusive mode</div><div class='ctx'> 	 * to avoid preemption on IB test</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -4400,17 +5057,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> 	amdgpu_fence_driver_hw_fini(adev);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mman.initialized)</div><div class='del'>-		drain_workqueue(adev-&gt;mman.bdev.wq);</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;pm.sysfs_initialized)</div><div class='del'>-		amdgpu_pm_sysfs_fini(adev);</div><div class='del'>-	if (adev-&gt;ucode_sysfs_en)</div><div class='del'>-		amdgpu_ucode_sysfs_fini(adev);</div><div class='del'>-	sysfs_remove_files(&amp;adev-&gt;dev-&gt;kobj, amdgpu_dev_attributes);</div><div class='del'>-	amdgpu_fru_sysfs_fini(adev);</div><div class='del'>-</div><div class='del'>-	amdgpu_reg_state_sysfs_fini(adev);</div><div class='add'>+	amdgpu_device_sys_interface_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* disable ras feature must before hw fini */</div><div class='ctx'> 	amdgpu_ras_pre_fini(adev);</div><div class='hunk'>@@ -4433,31 +5080,38 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> void amdgpu_device_fini_sw(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int idx;</div><div class='add'>+	int i, idx;</div><div class='ctx'> 	bool px;</div><div class='ctx'> </div><div class='del'>-	amdgpu_fence_driver_sw_fini(adev);</div><div class='ctx'> 	amdgpu_device_ip_fini(adev);</div><div class='add'>+	amdgpu_fence_driver_sw_fini(adev);</div><div class='ctx'> 	amdgpu_ucode_release(&amp;adev-&gt;firmware.gpu_info_fw);</div><div class='ctx'> 	adev-&gt;accel_working = false;</div><div class='ctx'> 	dma_fence_put(rcu_dereference_protected(adev-&gt;gang_submit, true));</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; ++i) {</div><div class='add'>+		dma_fence_put(adev-&gt;isolation[i].spearhead);</div><div class='add'>+		amdgpu_sync_free(&amp;adev-&gt;isolation[i].active);</div><div class='add'>+		amdgpu_sync_free(&amp;adev-&gt;isolation[i].prev);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_reset_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* free i2c buses */</div><div class='del'>-	if (!amdgpu_device_has_dc_support(adev))</div><div class='del'>-		amdgpu_i2c_fini(adev);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_emu_mode != 1)</div><div class='del'>-		amdgpu_atombios_fini(adev);</div><div class='add'>+	amdgpu_i2c_fini(adev);</div><div class='ctx'> </div><div class='del'>-	kfree(adev-&gt;bios);</div><div class='del'>-	adev-&gt;bios = NULL;</div><div class='add'>+	if (adev-&gt;bios) {</div><div class='add'>+		if (amdgpu_emu_mode != 1)</div><div class='add'>+			amdgpu_atombios_fini(adev);</div><div class='add'>+		amdgpu_bios_release(adev);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(adev-&gt;fru_info);</div><div class='ctx'> 	adev-&gt;fru_info = NULL;</div><div class='ctx'> </div><div class='del'>-	px = amdgpu_device_supports_px(adev_to_drm(adev));</div><div class='add'>+	kfree(adev-&gt;xcp_mgr);</div><div class='add'>+	adev-&gt;xcp_mgr = NULL;</div><div class='add'>+</div><div class='add'>+	px = amdgpu_device_supports_px(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (px || (!dev_is_removable(&amp;adev-&gt;pdev-&gt;dev) &amp;&amp;</div><div class='ctx'> 				apple_gmux_detect(NULL, NULL)))</div><div class='hunk'>@@ -4473,20 +5127,20 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		iounmap(adev-&gt;rmmio);</div><div class='ctx'> 		adev-&gt;rmmio = NULL;</div><div class='del'>-		amdgpu_doorbell_fini(adev);</div><div class='ctx'> 		drm_dev_exit(idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ENABLED(CONFIG_PERF_EVENTS))</div><div class='ctx'> 		amdgpu_pmu_fini(adev);</div><div class='del'>-	if (adev-&gt;mman.discovery_bin)</div><div class='add'>+	if (adev-&gt;discovery.bin)</div><div class='ctx'> 		amdgpu_discovery_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_reset_put_reset_domain(adev-&gt;reset_domain);</div><div class='ctx'> 	adev-&gt;reset_domain = NULL;</div><div class='ctx'> </div><div class='ctx'> 	kfree(adev-&gt;pci_state);</div><div class='del'>-</div><div class='add'>+	kfree(adev-&gt;pcie_reset_ctx.swds_pcistate);</div><div class='add'>+	kfree(adev-&gt;pcie_reset_ctx.swus_pcistate);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -4502,13 +5156,25 @@ static int amdgpu_device_evict_resources(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	/* No need to evict vram on APUs for suspend to ram or s2idle */</div><div class='del'>-	if ((adev-&gt;in_s3 || adev-&gt;in_s0ix) &amp;&amp; (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+	/* No need to evict vram on APUs unless going to S4 */</div><div class='add'>+	if (!adev-&gt;in_s4 &amp;&amp; (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* No need to evict when going to S5 through S4 callbacks */</div><div class='add'>+	if (system_state == SYSTEM_POWER_OFF)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);</div><div class='del'>-	if (ret)</div><div class='del'>-		DRM_WARN("evicting device resources failed\n");</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "evicting device resources failed\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;in_s4) {</div><div class='add'>+		ret = ttm_device_prepare_hibernation(&amp;adev-&gt;mman.bdev);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_err(adev-&gt;dev, "prepare hibernation failed, %d\n", ret);</div><div class='add'>+	}</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4516,6 +5182,33 @@ static int amdgpu_device_evict_resources(struct amdgpu_device *adev)</div><div class='ctx'>  * Suspend &amp; resume.</div><div class='ctx'>  */</div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_device_pm_notifier - Notification block for Suspend/Hibernate events</div><div class='add'>+ * @nb: notifier block</div><div class='add'>+ * @mode: suspend mode</div><div class='add'>+ * @data: data</div><div class='add'>+ *</div><div class='add'>+ * This function is called when the system is about to suspend or hibernate.</div><div class='add'>+ * It is used to set the appropriate flags so that eviction can be optimized</div><div class='add'>+ * in the pm prepare callback.</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_device_pm_notifier(struct notifier_block *nb, unsigned long mode,</div><div class='add'>+				     void *data)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = container_of(nb, struct amdgpu_device, pm_nb);</div><div class='add'>+</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case PM_HIBERNATION_PREPARE:</div><div class='add'>+		adev-&gt;in_s4 = true;</div><div class='add'>+		break;</div><div class='add'>+	case PM_POST_HIBERNATION:</div><div class='add'>+		adev-&gt;in_s4 = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NOTIFY_DONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_device_prepare - prepare for device suspend</div><div class='ctx'>  *</div><div class='ctx'>  * @dev: drm dev pointer</div><div class='hunk'>@@ -4529,48 +5222,65 @@ int amdgpu_device_prepare(struct drm_device *dev)</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_choose_low_power_state(adev);</div><div class='del'>-</div><div class='ctx'> 	if (dev-&gt;switch_power_state == DRM_SWITCH_POWER_OFF)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Evict the majority of BOs before starting suspend sequence */</div><div class='ctx'> 	r = amdgpu_device_evict_resources(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto unprepare;</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	flush_delayed_work(&amp;adev-&gt;gfx.gfx_off_delay_work);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (!adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;prepare_suspend)</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;prepare_suspend((void *)adev);</div><div class='add'>+		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;prepare_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto unprepare;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-unprepare:</div><div class='del'>-	adev-&gt;in_s0ix = adev-&gt;in_s3 = false;</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_complete - complete power state transition</div><div class='add'>+ *</div><div class='add'>+ * @dev: drm dev pointer</div><div class='add'>+ *</div><div class='add'>+ * Undo the changes from amdgpu_device_prepare. This will be</div><div class='add'>+ * called on all resume transitions, including those that failed.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_device_complete(struct drm_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='add'>+		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='add'>+			continue;</div><div class='add'>+		if (!adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;complete)</div><div class='add'>+			continue;</div><div class='add'>+		adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;complete(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_device_suspend - initiate device suspend</div><div class='ctx'>  *</div><div class='ctx'>  * @dev: drm dev pointer</div><div class='del'>- * @fbcon : notify the fbdev of suspend</div><div class='add'>+ * @notify_clients: notify in-kernel DRM clients</div><div class='ctx'>  *</div><div class='ctx'>  * Puts the hw in the suspend state (all asics).</div><div class='ctx'>  * Returns 0 for success or an error on failure.</div><div class='ctx'>  * Called at driver suspend.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)</div><div class='add'>+int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	int r = 0;</div><div class='add'>+	int r, rec;</div><div class='ctx'> </div><div class='ctx'> 	if (dev-&gt;switch_power_state == DRM_SWITCH_POWER_OFF)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -4578,44 +5288,125 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)</div><div class='ctx'> 	adev-&gt;in_suspend = true;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		if (!adev-&gt;in_runpm)</div><div class='add'>+			amdgpu_amdkfd_suspend_process(adev);</div><div class='ctx'> 		amdgpu_virt_fini_data_exchange(adev);</div><div class='ctx'> 		r = amdgpu_virt_request_full_gpu(adev, false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))</div><div class='del'>-		DRM_WARN("smart shift update failed\n");</div><div class='add'>+	r = amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D3);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unwind_sriov;</div><div class='ctx'> </div><div class='del'>-	if (fbcon)</div><div class='del'>-		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)-&gt;fb_helper, true);</div><div class='add'>+	if (notify_clients)</div><div class='add'>+		drm_client_dev_suspend(adev_to_drm(adev));</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;delayed_init_work);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_suspend(adev);</div><div class='ctx'> </div><div class='del'>-	amdgpu_device_ip_suspend_phase1(adev);</div><div class='add'>+	r = amdgpu_device_ip_suspend_phase1(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unwind_smartshift;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;in_s0ix)</div><div class='del'>-		amdgpu_amdkfd_suspend(adev, adev-&gt;in_runpm);</div><div class='add'>+	amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) &amp;&amp; !adev-&gt;in_runpm);</div><div class='add'>+	r = amdgpu_userq_suspend(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unwind_ip_phase1;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_device_evict_resources(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		return r;</div><div class='add'>+		goto unwind_userq;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ttm_set_buffer_funcs_status(adev, false);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_fence_driver_hw_fini(adev);</div><div class='ctx'> </div><div class='del'>-	amdgpu_device_ip_suspend_phase2(adev);</div><div class='add'>+	r = amdgpu_device_ip_suspend_phase2(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unwind_evict;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_release_full_gpu(adev, false);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_dpm_notify_rlc_state(adev, false);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+unwind_evict:</div><div class='add'>+	if (adev-&gt;mman.buffer_funcs_ring-&gt;sched.ready)</div><div class='add'>+		amdgpu_ttm_set_buffer_funcs_status(adev, true);</div><div class='add'>+	amdgpu_fence_driver_hw_init(adev);</div><div class='add'>+</div><div class='add'>+unwind_userq:</div><div class='add'>+	rec = amdgpu_userq_resume(adev);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed to re-initialize user queues: %d\n", rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	rec = amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) &amp;&amp; !adev-&gt;in_runpm);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed to re-initialize kfd: %d\n", rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+unwind_ip_phase1:</div><div class='add'>+	/* suspend phase 1 = resume phase 3 */</div><div class='add'>+	rec = amdgpu_device_ip_resume_phase3(adev);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed to re-initialize IPs phase1: %d\n", rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+unwind_smartshift:</div><div class='add'>+	rec = amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D0);</div><div class='add'>+	if (rec) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed to re-update smart shift: %d\n", rec);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (notify_clients)</div><div class='add'>+		drm_client_dev_resume(adev_to_drm(adev));</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_resume(adev);</div><div class='add'>+</div><div class='add'>+unwind_sriov:</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		rec = amdgpu_virt_request_full_gpu(adev, true);</div><div class='add'>+		if (rec) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "failed to reinitialize sriov: %d\n", rec);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;in_suspend = adev-&gt;in_s0ix = adev-&gt;in_s3 = false;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int amdgpu_virt_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	unsigned int prev_physical_node_id = adev-&gt;gmc.xgmi.physical_node_id;</div><div class='add'>+</div><div class='add'>+	/* During VM resume, QEMU programming of VF MSIX table (register GFXMSIX_VECT0_ADDR_LO)</div><div class='add'>+	 * may not work. The access could be blocked by nBIF protection as VF isn't in</div><div class='add'>+	 * exclusive access mode. Exclusive access is enabled now, disable/enable MSIX</div><div class='add'>+	 * so that QEMU reprograms MSIX table.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_restore_msix(adev);</div><div class='add'>+</div><div class='add'>+	r = adev-&gt;gfxhub.funcs-&gt;get_xgmi_info(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	dev_info(adev-&gt;dev, "xgmi node, old id %d, new id %d\n",</div><div class='add'>+		prev_physical_node_id, adev-&gt;gmc.xgmi.physical_node_id);</div><div class='add'>+</div><div class='add'>+	adev-&gt;vm_manager.vram_base_offset = adev-&gt;gfxhub.funcs-&gt;get_mc_fb_offset(adev);</div><div class='add'>+	adev-&gt;vm_manager.vram_base_offset +=</div><div class='add'>+		adev-&gt;gmc.xgmi.physical_node_id * adev-&gt;gmc.xgmi.node_segment_size;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4623,13 +5414,13 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)</div><div class='ctx'>  * amdgpu_device_resume - initiate device resume</div><div class='ctx'>  *</div><div class='ctx'>  * @dev: drm dev pointer</div><div class='del'>- * @fbcon : notify the fbdev of resume</div><div class='add'>+ * @notify_clients: notify in-kernel DRM clients</div><div class='ctx'>  *</div><div class='ctx'>  * Bring the hw back to operating state (all asics).</div><div class='ctx'>  * Returns 0 for success or an error on failure.</div><div class='ctx'>  * Called at driver resume.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_device_resume(struct drm_device *dev, bool fbcon)</div><div class='add'>+int amdgpu_device_resume(struct drm_device *dev, bool notify_clients)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	int r = 0;</div><div class='hunk'>@@ -4640,6 +5431,12 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_virt_xgmi_migrate_enabled(adev)) {</div><div class='add'>+		r = amdgpu_virt_resume(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dev-&gt;switch_power_state == DRM_SWITCH_POWER_OFF)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -4659,13 +5456,14 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)</div><div class='ctx'> 		dev_err(adev-&gt;dev, "amdgpu_device_ip_resume failed (%d).\n", r);</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='del'>-	amdgpu_fence_driver_hw_init(adev);</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;in_s0ix) {</div><div class='del'>-		r = amdgpu_amdkfd_resume(adev, adev-&gt;in_runpm);</div><div class='del'>-		if (r)</div><div class='del'>-			goto exit;</div><div class='del'>-	}</div><div class='add'>+	r = amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) &amp;&amp; !adev-&gt;in_runpm);</div><div class='add'>+	if (r)</div><div class='add'>+		goto exit;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_userq_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto exit;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_device_ip_late_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -4677,6 +5475,9 @@ exit:</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		amdgpu_virt_init_data_exchange(adev);</div><div class='ctx'> 		amdgpu_virt_release_full_gpu(adev, true);</div><div class='add'>+</div><div class='add'>+		if (!r &amp;&amp; !adev-&gt;in_runpm)</div><div class='add'>+			r = amdgpu_amdkfd_resume_process(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -4685,8 +5486,8 @@ exit:</div><div class='ctx'> 	/* Make sure IB tests flushed */</div><div class='ctx'> 	flush_delayed_work(&amp;adev-&gt;delayed_init_work);</div><div class='ctx'> </div><div class='del'>-	if (fbcon)</div><div class='del'>-		drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)-&gt;fb_helper, false);</div><div class='add'>+	if (notify_clients)</div><div class='add'>+		drm_client_dev_resume(adev_to_drm(adev));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_resume(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -4711,13 +5512,12 @@ exit:</div><div class='ctx'> 		dev-&gt;dev-&gt;power.disable_depth--;</div><div class='ctx'> #endif</div><div class='ctx'> 	}</div><div class='del'>-	adev-&gt;in_suspend = false;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes)</div><div class='del'>-		amdgpu_mes_self_test(adev);</div><div class='add'>+	amdgpu_vram_mgr_clear_reset_blocks(adev);</div><div class='add'>+	adev-&gt;in_suspend = false;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))</div><div class='del'>-		DRM_WARN("smart shift update failed\n");</div><div class='add'>+	if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D0))</div><div class='add'>+		dev_warn(adev-&gt;dev, "smart shift update failed\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -4748,7 +5548,8 @@ static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;check_soft_reset)</div><div class='ctx'> 			adev-&gt;ip_blocks[i].status.hang =</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;check_soft_reset(adev);</div><div class='add'>+				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;check_soft_reset(</div><div class='add'>+					&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].status.hang) {</div><div class='ctx'> 			dev_info(adev-&gt;dev, "IP block:%s is hung!\n", adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name);</div><div class='ctx'> 			asic_hang = true;</div><div class='hunk'>@@ -4777,7 +5578,7 @@ static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].status.hang &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;pre_soft_reset) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;pre_soft_reset(adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;pre_soft_reset(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4839,7 +5640,7 @@ static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].status.hang &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;soft_reset) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;soft_reset(adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;soft_reset(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4868,7 +5669,7 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].status.hang &amp;&amp;</div><div class='ctx'> 		    adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;post_soft_reset)</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;post_soft_reset(adev);</div><div class='add'>+			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;post_soft_reset(&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4877,103 +5678,33 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_device_recover_vram - Recover some VRAM contents</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='del'>- * Restores the contents of VRAM buffers from the shadows in GTT.  Used to</div><div class='del'>- * restore things like GPUVM page tables after a GPU reset where</div><div class='del'>- * the contents of VRAM might be lost.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- * 0 on success, negative error code on failure.</div><div class='del'>- */</div><div class='del'>-static int amdgpu_device_recover_vram(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct dma_fence *fence = NULL, *next = NULL;</div><div class='del'>-	struct amdgpu_bo *shadow;</div><div class='del'>-	struct amdgpu_bo_vm *vmbo;</div><div class='del'>-	long r = 1, tmo;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_sriov_runtime(adev))</div><div class='del'>-		tmo = msecs_to_jiffies(8000);</div><div class='del'>-	else</div><div class='del'>-		tmo = msecs_to_jiffies(100);</div><div class='del'>-</div><div class='del'>-	dev_info(adev-&gt;dev, "recover vram bo from shadow start\n");</div><div class='del'>-	mutex_lock(&amp;adev-&gt;shadow_list_lock);</div><div class='del'>-	list_for_each_entry(vmbo, &amp;adev-&gt;shadow_list, shadow_list) {</div><div class='del'>-		/* If vm is compute context or adev is APU, shadow will be NULL */</div><div class='del'>-		if (!vmbo-&gt;shadow)</div><div class='del'>-			continue;</div><div class='del'>-		shadow = vmbo-&gt;shadow;</div><div class='del'>-</div><div class='del'>-		/* No need to recover an evicted BO */</div><div class='del'>-		if (shadow-&gt;tbo.resource-&gt;mem_type != TTM_PL_TT ||</div><div class='del'>-		    shadow-&gt;tbo.resource-&gt;start == AMDGPU_BO_INVALID_OFFSET ||</div><div class='del'>-		    shadow-&gt;parent-&gt;tbo.resource-&gt;mem_type != TTM_PL_VRAM)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_restore_shadow(shadow, &amp;next);</div><div class='del'>-		if (r)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		if (fence) {</div><div class='del'>-			tmo = dma_fence_wait_timeout(fence, false, tmo);</div><div class='del'>-			dma_fence_put(fence);</div><div class='del'>-			fence = next;</div><div class='del'>-			if (tmo == 0) {</div><div class='del'>-				r = -ETIMEDOUT;</div><div class='del'>-				break;</div><div class='del'>-			} else if (tmo &lt; 0) {</div><div class='del'>-				r = tmo;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-		} else {</div><div class='del'>-			fence = next;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;shadow_list_lock);</div><div class='del'>-</div><div class='del'>-	if (fence)</div><div class='del'>-		tmo = dma_fence_wait_timeout(fence, false, tmo);</div><div class='del'>-	dma_fence_put(fence);</div><div class='del'>-</div><div class='del'>-	if (r &lt; 0 || tmo &lt;= 0) {</div><div class='del'>-		dev_err(adev-&gt;dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);</div><div class='del'>-		return -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dev_info(adev-&gt;dev, "recover vram bo from shadow done\n");</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='del'>- * @from_hypervisor: request from hypervisor</div><div class='add'>+ * @reset_context: amdgpu reset context pointer</div><div class='ctx'>  *</div><div class='ctx'>  * do VF FLR and reinitialize Asic</div><div class='ctx'>  * return 0 means succeeded otherwise failed</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,</div><div class='del'>-				     bool from_hypervisor)</div><div class='add'>+				     struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	struct amdgpu_hive_info *hive = NULL;</div><div class='del'>-	int retry_limit = 0;</div><div class='ctx'> </div><div class='del'>-retry:</div><div class='del'>-	amdgpu_amdkfd_pre_reset(adev);</div><div class='del'>-</div><div class='del'>-	if (from_hypervisor)</div><div class='add'>+	if (test_bit(AMDGPU_HOST_FLR, &amp;reset_context-&gt;flags)) {</div><div class='add'>+		if (!amdgpu_ras_get_fed_status(adev))</div><div class='add'>+			amdgpu_virt_ready_to_reset(adev);</div><div class='add'>+		amdgpu_virt_wait_reset(adev);</div><div class='add'>+		clear_bit(AMDGPU_HOST_FLR, &amp;reset_context-&gt;flags);</div><div class='ctx'> 		r = amdgpu_virt_request_full_gpu(adev, true);</div><div class='del'>-	else</div><div class='add'>+	} else {</div><div class='ctx'> 		r = amdgpu_virt_reset_gpu(adev);</div><div class='add'>+	}</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_clear_err_state(adev);</div><div class='ctx'> 	amdgpu_irq_gpu_reset_resume_helper(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* some sw clean up VF needs to do before recover */</div><div class='hunk'>@@ -4982,7 +5713,7 @@ retry:</div><div class='ctx'> 	/* Resume IP prior to SMC */</div><div class='ctx'> 	r = amdgpu_device_ip_reinit_early_sriov(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto error;</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_virt_init_data_exchange(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -4993,51 +5724,56 @@ retry:</div><div class='ctx'> 	/* now we are okay to resume SMC/CP/SDMA */</div><div class='ctx'> 	r = amdgpu_device_ip_reinit_late_sriov(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto error;</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	hive = amdgpu_get_xgmi_hive(adev);</div><div class='ctx'> 	/* Update PSP FW topology after reset */</div><div class='ctx'> 	if (hive &amp;&amp; adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1)</div><div class='ctx'> 		r = amdgpu_xgmi_update_topology(hive, adev);</div><div class='del'>-</div><div class='ctx'> 	if (hive)</div><div class='ctx'> 		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-	if (!r) {</div><div class='del'>-		r = amdgpu_ib_ring_tests(adev);</div><div class='del'>-</div><div class='del'>-		amdgpu_amdkfd_post_reset(adev);</div><div class='del'>-	}</div><div class='add'>+	r = amdgpu_ib_ring_tests(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-error:</div><div class='del'>-	if (!r &amp;&amp; adev-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {</div><div class='add'>+	if (adev-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_GIM_FLR_VRAMLOST)</div><div class='ctx'> 		amdgpu_inc_vram_lost(adev);</div><div class='del'>-		r = amdgpu_device_recover_vram(adev);</div><div class='del'>-	}</div><div class='add'>+</div><div class='add'>+	/* need to be called during full access so we can't do it later like</div><div class='add'>+	 * bare-metal does.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_amdkfd_post_reset(adev);</div><div class='ctx'> 	amdgpu_virt_release_full_gpu(adev, true);</div><div class='ctx'> </div><div class='del'>-	if (AMDGPU_RETRY_SRIOV_RESET(r)) {</div><div class='del'>-		if (retry_limit &lt; AMDGPU_MAX_RETRY_LIMIT) {</div><div class='del'>-			retry_limit++;</div><div class='del'>-			goto retry;</div><div class='del'>-		} else</div><div class='del'>-			DRM_ERROR("GPU reset retry is beyond the retry limit\n");</div><div class='del'>-	}</div><div class='add'>+	/* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))</div><div class='add'>+		amdgpu_ras_resume(adev);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	amdgpu_virt_ras_telemetry_post_reset(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_device_has_job_running - check if there is any job in mirror list</div><div class='add'>+ * amdgpu_device_has_job_running - check if there is any unfinished job</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  *</div><div class='del'>- * check if there is any job in mirror list</div><div class='add'>+ * check if there is any job running on the device when guest driver receives</div><div class='add'>+ * FLR notification from host driver. If there are still jobs running, then</div><div class='add'>+ * the guest driver will not respond the FLR reset. Instead, let the job hit</div><div class='add'>+ * the timeout and guest driver then issue the reset request.</div><div class='ctx'>  */</div><div class='ctx'> bool amdgpu_device_has_job_running(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct drm_sched_job *job;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; AMDGPU_MAX_RINGS; ++i) {</div><div class='ctx'> 		struct amdgpu_ring *ring = adev-&gt;rings[i];</div><div class='hunk'>@@ -5045,11 +5781,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev)</div><div class='ctx'> 		if (!amdgpu_ring_sched_ready(ring))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		spin_lock(&amp;ring-&gt;sched.job_list_lock);</div><div class='del'>-		job = list_first_entry_or_null(&amp;ring-&gt;sched.pending_list,</div><div class='del'>-					       struct drm_sched_job, list);</div><div class='del'>-		spin_unlock(&amp;ring-&gt;sched.job_list_lock);</div><div class='del'>-		if (job)</div><div class='add'>+		if (amdgpu_fence_count_emitted(ring))</div><div class='ctx'> 			return true;</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -5111,15 +5843,19 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 i;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	amdgpu_atombios_scratch_regs_engine_hung(adev, true);</div><div class='add'>+	if (adev-&gt;bios)</div><div class='add'>+		amdgpu_atombios_scratch_regs_engine_hung(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	dev_info(adev-&gt;dev, "GPU mode1 reset\n");</div><div class='ctx'> </div><div class='add'>+	/* Cache the state before bus master disable. The saved config space</div><div class='add'>+	 * values are used in other cases like restore after mode-2 reset.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_device_cache_pci_state(adev-&gt;pdev);</div><div class='add'>+</div><div class='ctx'> 	/* disable BM */</div><div class='ctx'> 	pci_clear_master(adev-&gt;pdev);</div><div class='ctx'> </div><div class='del'>-	amdgpu_device_cache_pci_state(adev-&gt;pdev);</div><div class='del'>-</div><div class='ctx'> 	if (amdgpu_dpm_is_mode1_reset_supported(adev)) {</div><div class='ctx'> 		dev_info(adev-&gt;dev, "GPU smu mode1 reset\n");</div><div class='ctx'> 		ret = amdgpu_dpm_mode1_reset(adev);</div><div class='hunk'>@@ -5150,7 +5886,8 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)</div><div class='ctx'> 		goto mode1_reset_failed;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_atombios_scratch_regs_engine_hung(adev, false);</div><div class='add'>+	if (adev-&gt;bios)</div><div class='add'>+		amdgpu_atombios_scratch_regs_engine_hung(adev, false);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -5159,21 +5896,43 @@ mode1_reset_failed:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_device_link_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "GPU link reset\n");</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_reset_in_dpc(adev))</div><div class='add'>+		ret = amdgpu_dpm_link_reset(adev);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		goto link_reset_failed;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_psp_wait_for_bootloader(adev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto link_reset_failed;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+link_reset_failed:</div><div class='add'>+	dev_err(adev-&gt;dev, "GPU link reset failed\n");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,</div><div class='ctx'> 				 struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r = 0;</div><div class='ctx'> 	struct amdgpu_job *job = NULL;</div><div class='add'>+	struct amdgpu_device *tmp_adev = reset_context-&gt;reset_req_dev;</div><div class='ctx'> 	bool need_full_reset =</div><div class='ctx'> 		test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	if (reset_context-&gt;reset_req_dev == adev)</div><div class='ctx'> 		job = reset_context-&gt;job;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-		/* stop the data exchange thread */</div><div class='del'>-		amdgpu_virt_fini_data_exchange(adev);</div><div class='del'>-	}</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_virt_pre_reset(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_fence_driver_isr_toggle(adev, true);</div><div class='ctx'> </div><div class='hunk'>@@ -5184,11 +5943,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,</div><div class='ctx'> 		if (!amdgpu_ring_sched_ready(ring))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		/* Clear job fence from fence drv to avoid force_completion</div><div class='del'>-		 * leave NULL and vm flush fence in fence drv</div><div class='del'>-		 */</div><div class='del'>-		amdgpu_fence_driver_clear_job_fences(ring);</div><div class='del'>-</div><div class='ctx'> 		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */</div><div class='ctx'> 		amdgpu_fence_driver_force_completion(ring);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -5222,6 +5976,16 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (!test_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context-&gt;flags)) {</div><div class='add'>+			dev_info(tmp_adev-&gt;dev, "Dumping IP State\n");</div><div class='add'>+			/* Trigger ip dump before we reset the asic */</div><div class='add'>+			for (i = 0; i &lt; tmp_adev-&gt;num_ip_blocks; i++)</div><div class='add'>+				if (tmp_adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;dump_ip_state)</div><div class='add'>+					tmp_adev-&gt;ip_blocks[i].version-&gt;funcs</div><div class='add'>+						-&gt;dump_ip_state((void *)&amp;tmp_adev-&gt;ip_blocks[i]);</div><div class='add'>+			dev_info(tmp_adev-&gt;dev, "Dumping IP State Completed\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (need_full_reset)</div><div class='ctx'> 			r = amdgpu_device_ip_suspend(adev);</div><div class='ctx'> 		if (need_full_reset)</div><div class='hunk'>@@ -5234,94 +5998,36 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;reset_info.num_regs; i++) {</div><div class='del'>-		adev-&gt;reset_info.reset_dump_reg_value[i] =</div><div class='del'>-			RREG32(adev-&gt;reset_info.reset_dump_reg_list[i]);</div><div class='del'>-</div><div class='del'>-		trace_amdgpu_reset_reg_dumps(adev-&gt;reset_info.reset_dump_reg_list[i],</div><div class='del'>-					     adev-&gt;reset_info.reset_dump_reg_value[i]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='del'>-			 struct amdgpu_reset_context *reset_context)</div><div class='add'>+int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *tmp_adev = NULL;</div><div class='del'>-	bool need_full_reset, skip_hw_reset, vram_lost = false;</div><div class='del'>-	int r = 0;</div><div class='add'>+	struct list_head *device_list_handle;</div><div class='add'>+	bool full_reset, vram_lost = false;</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='add'>+	int r, init_level;</div><div class='ctx'> </div><div class='del'>-	/* Try reset handler method first */</div><div class='del'>-	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,</div><div class='del'>-				    reset_list);</div><div class='del'>-	amdgpu_reset_reg_dumps(tmp_adev);</div><div class='add'>+	device_list_handle = reset_context-&gt;reset_device_list;</div><div class='ctx'> </div><div class='del'>-	reset_context-&gt;reset_device_list = device_list_handle;</div><div class='del'>-	r = amdgpu_reset_perform_reset(tmp_adev, reset_context);</div><div class='del'>-	/* If reset handler not implemented, continue; otherwise return */</div><div class='del'>-	if (r == -EOPNOTSUPP)</div><div class='del'>-		r = 0;</div><div class='del'>-	else</div><div class='del'>-		return r;</div><div class='add'>+	if (!device_list_handle)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	/* Reset handler not implemented, use the default method */</div><div class='del'>-	need_full_reset =</div><div class='del'>-		test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='del'>-	skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &amp;reset_context-&gt;flags);</div><div class='add'>+	full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * ASIC reset has to be done on all XGMI hive nodes ASAP</div><div class='del'>-	 * to allow proper links negotiation in FW (within 1 sec)</div><div class='add'>+	/**</div><div class='add'>+	 * If it's reset on init, it's default init level, otherwise keep level</div><div class='add'>+	 * as recovery level.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!skip_hw_reset &amp;&amp; need_full_reset) {</div><div class='del'>-		list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='del'>-			/* For XGMI run all resets in parallel to speed up the process */</div><div class='del'>-			if (tmp_adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) {</div><div class='del'>-				tmp_adev-&gt;gmc.xgmi.pending_reset = false;</div><div class='del'>-				if (!queue_work(system_unbound_wq, &amp;tmp_adev-&gt;xgmi_reset_work))</div><div class='del'>-					r = -EALREADY;</div><div class='del'>-			} else</div><div class='del'>-				r = amdgpu_asic_reset(tmp_adev);</div><div class='del'>-</div><div class='del'>-			if (r) {</div><div class='del'>-				dev_err(tmp_adev-&gt;dev, "ASIC reset failed with error, %d for drm dev, %s",</div><div class='del'>-					 r, adev_to_drm(tmp_adev)-&gt;unique);</div><div class='del'>-				goto out;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* For XGMI wait for all resets to complete before proceed */</div><div class='del'>-		if (!r) {</div><div class='del'>-			list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='del'>-				if (tmp_adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) {</div><div class='del'>-					flush_work(&amp;tmp_adev-&gt;xgmi_reset_work);</div><div class='del'>-					r = tmp_adev-&gt;asic_reset_res;</div><div class='del'>-					if (r)</div><div class='del'>-						break;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!r &amp;&amp; amdgpu_ras_intr_triggered()) {</div><div class='del'>-		list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='del'>-			amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		amdgpu_ras_intr_cleared();</div><div class='del'>-	}</div><div class='add'>+	if (reset_context-&gt;method == AMD_RESET_METHOD_ON_INIT)</div><div class='add'>+			init_level = AMDGPU_INIT_LEVEL_DEFAULT;</div><div class='add'>+	else</div><div class='add'>+			init_level = AMDGPU_INIT_LEVEL_RESET_RECOVERY;</div><div class='ctx'> </div><div class='add'>+	r = 0;</div><div class='ctx'> 	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='del'>-		if (need_full_reset) {</div><div class='add'>+		amdgpu_set_init_level(tmp_adev, init_level);</div><div class='add'>+		if (full_reset) {</div><div class='ctx'> 			/* post card */</div><div class='del'>-			amdgpu_ras_set_fed(tmp_adev, false);</div><div class='add'>+			amdgpu_reset_set_dpc_status(tmp_adev, false);</div><div class='add'>+			amdgpu_ras_clear_err_state(tmp_adev);</div><div class='ctx'> 			r = amdgpu_device_asic_init(tmp_adev);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				dev_warn(tmp_adev-&gt;dev, "asic atom init failed!");</div><div class='hunk'>@@ -5334,10 +6040,13 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> </div><div class='ctx'> 				vram_lost = amdgpu_device_check_vram_lost(tmp_adev);</div><div class='ctx'> </div><div class='del'>-				amdgpu_coredump(tmp_adev, vram_lost, reset_context);</div><div class='add'>+				if (!test_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context-&gt;flags))</div><div class='add'>+					amdgpu_coredump(tmp_adev, false, vram_lost, reset_context-&gt;job);</div><div class='ctx'> </div><div class='ctx'> 				if (vram_lost) {</div><div class='del'>-					DRM_INFO("VRAM is lost due to GPU reset!\n");</div><div class='add'>+					dev_info(</div><div class='add'>+						tmp_adev-&gt;dev,</div><div class='add'>+						"VRAM is lost due to GPU reset!\n");</div><div class='ctx'> 					amdgpu_inc_vram_lost(tmp_adev);</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='hunk'>@@ -5357,6 +6066,10 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 				if (tmp_adev-&gt;mman.buffer_funcs_ring-&gt;sched.ready)</div><div class='ctx'> 					amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);</div><div class='ctx'> </div><div class='add'>+				r = amdgpu_device_ip_resume_phase3(tmp_adev);</div><div class='add'>+				if (r)</div><div class='add'>+					goto out;</div><div class='add'>+</div><div class='ctx'> 				if (vram_lost)</div><div class='ctx'> 					amdgpu_device_fill_reset_magic(tmp_adev);</div><div class='ctx'> </div><div class='hunk'>@@ -5374,7 +6087,11 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 				if (r)</div><div class='ctx'> 					goto out;</div><div class='ctx'> </div><div class='del'>-				drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)-&gt;fb_helper, false);</div><div class='add'>+				r = amdgpu_userq_post_reset(tmp_adev, vram_lost);</div><div class='add'>+				if (r)</div><div class='add'>+					goto out;</div><div class='add'>+</div><div class='add'>+				drm_client_dev_resume(adev_to_drm(tmp_adev));</div><div class='ctx'> </div><div class='ctx'> 				/*</div><div class='ctx'> 				 * The GPU enters bad state once faulty pages</div><div class='hunk'>@@ -5386,7 +6103,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 				 * bad_page_threshold value to fix this once</div><div class='ctx'> 				 * probing driver again.</div><div class='ctx'> 				 */</div><div class='del'>-				if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {</div><div class='add'>+				if (!amdgpu_ras_is_rma(tmp_adev)) {</div><div class='ctx'> 					/* must succeed. */</div><div class='ctx'> 					amdgpu_ras_resume(tmp_adev);</div><div class='ctx'> 				} else {</div><div class='hunk'>@@ -5404,27 +6121,102 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 		if (!r) {</div><div class='add'>+			/* IP init is complete now, set level as default */</div><div class='add'>+			amdgpu_set_init_level(tmp_adev,</div><div class='add'>+					      AMDGPU_INIT_LEVEL_DEFAULT);</div><div class='ctx'> 			amdgpu_irq_gpu_reset_resume_helper(tmp_adev);</div><div class='ctx'> 			r = amdgpu_ib_ring_tests(tmp_adev);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				dev_err(tmp_adev-&gt;dev, "ib ring test failed (%d).\n", r);</div><div class='del'>-				need_full_reset = true;</div><div class='ctx'> 				r = -EAGAIN;</div><div class='ctx'> 				goto end;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!r)</div><div class='del'>-			r = amdgpu_device_recover_vram(tmp_adev);</div><div class='del'>-		else</div><div class='add'>+		if (r)</div><div class='ctx'> 			tmp_adev-&gt;asic_reset_res = r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> end:</div><div class='del'>-	if (need_full_reset)</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='add'>+			 struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	bool need_full_reset, skip_hw_reset;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	/* Try reset handler method first */</div><div class='add'>+	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,</div><div class='add'>+				    reset_list);</div><div class='add'>+</div><div class='add'>+	reset_context-&gt;reset_device_list = device_list_handle;</div><div class='add'>+	r = amdgpu_reset_perform_reset(tmp_adev, reset_context);</div><div class='add'>+	/* If reset handler not implemented, continue; otherwise return */</div><div class='add'>+	if (r == -EOPNOTSUPP)</div><div class='add'>+		r = 0;</div><div class='add'>+	else</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* Reset handler not implemented, use the default method */</div><div class='add'>+	need_full_reset =</div><div class='add'>+		test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='add'>+	skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &amp;reset_context-&gt;flags);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * ASIC reset has to be done on all XGMI hive nodes ASAP</div><div class='add'>+	 * to allow proper links negotiation in FW (within 1 sec)</div><div class='add'>+	 */</div><div class='add'>+	if (!skip_hw_reset &amp;&amp; need_full_reset) {</div><div class='add'>+		list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+			/* For XGMI run all resets in parallel to speed up the process */</div><div class='add'>+			if (tmp_adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) {</div><div class='add'>+				if (!queue_work(system_unbound_wq,</div><div class='add'>+						&amp;tmp_adev-&gt;xgmi_reset_work))</div><div class='add'>+					r = -EALREADY;</div><div class='add'>+			} else</div><div class='add'>+				r = amdgpu_asic_reset(tmp_adev);</div><div class='add'>+</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(tmp_adev-&gt;dev,</div><div class='add'>+					"ASIC reset failed with error, %d for drm dev, %s",</div><div class='add'>+					r, adev_to_drm(tmp_adev)-&gt;unique);</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* For XGMI wait for all resets to complete before proceed */</div><div class='add'>+		if (!r) {</div><div class='add'>+			list_for_each_entry(tmp_adev, device_list_handle,</div><div class='add'>+					    reset_list) {</div><div class='add'>+				if (tmp_adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) {</div><div class='add'>+					flush_work(&amp;tmp_adev-&gt;xgmi_reset_work);</div><div class='add'>+					r = tmp_adev-&gt;asic_reset_res;</div><div class='add'>+					if (r)</div><div class='add'>+						break;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!r &amp;&amp; amdgpu_ras_intr_triggered()) {</div><div class='add'>+		list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+			amdgpu_ras_reset_error_count(tmp_adev,</div><div class='add'>+						     AMDGPU_RAS_BLOCK__MMHUB);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		amdgpu_ras_intr_cleared();</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_reinit_after_reset(reset_context);</div><div class='add'>+	if (r == -EAGAIN)</div><div class='ctx'> 		set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='ctx'> 	else</div><div class='ctx'> 		clear_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='add'>+</div><div class='add'>+out:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5433,6 +6225,7 @@ static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_asic_reset_method(adev)) {</div><div class='ctx'> 	case AMD_RESET_METHOD_MODE1:</div><div class='add'>+	case AMD_RESET_METHOD_LINK:</div><div class='ctx'> 		adev-&gt;mp1_state = PP_MP1_STATE_SHUTDOWN;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMD_RESET_METHOD_MODE2:</div><div class='hunk'>@@ -5520,6 +6313,7 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 		cancel_work(&amp;adev-&gt;reset_work);</div><div class='ctx'> #endif</div><div class='add'>+	cancel_work(&amp;adev-&gt;userq_reset_work);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;kfd.dev)</div><div class='ctx'> 		cancel_work(&amp;adev-&gt;kfd.reset_work);</div><div class='hunk'>@@ -5532,85 +6326,80 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_device_gpu_recover - reset the asic and recover scheduler</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @job: which job trigger hang</div><div class='del'>- * @reset_context: amdgpu reset context pointer</div><div class='del'>- *</div><div class='del'>- * Attempt to reset the GPU if it has hung (all asics).</div><div class='del'>- * Attempt to do soft-reset or full-reset and reinitialize Asic</div><div class='del'>- * Returns 0 for success or an error on failure.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='del'>-			      struct amdgpu_job *job,</div><div class='del'>-			      struct amdgpu_reset_context *reset_context)</div><div class='add'>+static int amdgpu_device_health_check(struct list_head *device_list_handle)</div><div class='ctx'> {</div><div class='del'>-	struct list_head device_list, *device_list_handle =  NULL;</div><div class='del'>-	bool job_signaled = false;</div><div class='del'>-	struct amdgpu_hive_info *hive = NULL;</div><div class='del'>-	struct amdgpu_device *tmp_adev = NULL;</div><div class='del'>-	int i, r = 0;</div><div class='del'>-	bool need_emergency_restart = false;</div><div class='del'>-	bool audio_suspended = false;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Special case: RAS triggered and full reset isn't supported</div><div class='del'>-	 */</div><div class='del'>-	need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Flush RAM to disk so that after reboot</div><div class='del'>-	 * the user can read log and see why the system rebooted.</div><div class='del'>-	 */</div><div class='del'>-	if (need_emergency_restart &amp;&amp; amdgpu_ras_get_context(adev) &amp;&amp;</div><div class='del'>-		amdgpu_ras_get_context(adev)-&gt;reboot) {</div><div class='del'>-		DRM_WARN("Emergency reboot.");</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-		ksys_sync_helper();</div><div class='del'>-		emergency_restart();</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+		ret |= amdgpu_device_bus_status_check(tmp_adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dev_info(adev-&gt;dev, "GPU %s begin!\n",</div><div class='del'>-		need_emergency_restart ? "jobs stop":"reset");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_sriov_vf(adev))</div><div class='del'>-		hive = amdgpu_get_xgmi_hive(adev);</div><div class='del'>-	if (hive)</div><div class='del'>-		mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+static void amdgpu_device_recovery_prepare(struct amdgpu_device *adev,</div><div class='add'>+					  struct list_head *device_list,</div><div class='add'>+					  struct amdgpu_hive_info *hive)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='ctx'> </div><div class='del'>-	reset_context-&gt;job = job;</div><div class='del'>-	reset_context-&gt;hive = hive;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Build list of devices to reset.</div><div class='ctx'> 	 * In case we are in XGMI hive mode, resort the device list</div><div class='ctx'> 	 * to put adev in the 1st position.</div><div class='ctx'> 	 */</div><div class='del'>-	INIT_LIST_HEAD(&amp;device_list);</div><div class='del'>-	if (!amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1)) {</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) &amp;&amp; hive) {</div><div class='ctx'> 		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='del'>-			list_add_tail(&amp;tmp_adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+			list_add_tail(&amp;tmp_adev-&gt;reset_list, device_list);</div><div class='ctx'> 			if (adev-&gt;shutdown)</div><div class='ctx'> 				tmp_adev-&gt;shutdown = true;</div><div class='add'>+			if (amdgpu_reset_in_dpc(adev))</div><div class='add'>+				tmp_adev-&gt;pcie_reset_ctx.in_link_reset = true;</div><div class='ctx'> 		}</div><div class='del'>-		if (!list_is_first(&amp;adev-&gt;reset_list, &amp;device_list))</div><div class='del'>-			list_rotate_to_front(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='del'>-		device_list_handle = &amp;device_list;</div><div class='add'>+		if (!list_is_first(&amp;adev-&gt;reset_list, device_list))</div><div class='add'>+			list_rotate_to_front(&amp;adev-&gt;reset_list, device_list);</div><div class='ctx'> 	} else {</div><div class='del'>-		list_add_tail(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='del'>-		device_list_handle = &amp;device_list;</div><div class='add'>+		list_add_tail(&amp;adev-&gt;reset_list, device_list);</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	/* We need to lock reset domain only once both for XGMI and single device */</div><div class='del'>-	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,</div><div class='del'>-				    reset_list);</div><div class='add'>+static void amdgpu_device_recovery_get_reset_lock(struct amdgpu_device *adev,</div><div class='add'>+						  struct list_head *device_list)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+</div><div class='add'>+	if (list_empty(device_list))</div><div class='add'>+		return;</div><div class='add'>+	tmp_adev =</div><div class='add'>+		list_first_entry(device_list, struct amdgpu_device, reset_list);</div><div class='ctx'> 	amdgpu_device_lock_reset_domain(tmp_adev-&gt;reset_domain);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	/* block all schedulers and reset given job's ring */</div><div class='del'>-	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+static void amdgpu_device_recovery_put_reset_lock(struct amdgpu_device *adev,</div><div class='add'>+						  struct list_head *device_list)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='ctx'> </div><div class='add'>+	if (list_empty(device_list))</div><div class='add'>+		return;</div><div class='add'>+	tmp_adev =</div><div class='add'>+		list_first_entry(device_list, struct amdgpu_device, reset_list);</div><div class='add'>+	amdgpu_device_unlock_reset_domain(tmp_adev-&gt;reset_domain);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_halt_activities(struct amdgpu_device *adev,</div><div class='add'>+					  struct amdgpu_job *job,</div><div class='add'>+					  struct amdgpu_reset_context *reset_context,</div><div class='add'>+					  struct list_head *device_list,</div><div class='add'>+					  struct amdgpu_hive_info *hive,</div><div class='add'>+					  bool need_emergency_restart)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* block all schedulers and reset given job's ring */</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='ctx'> 		amdgpu_device_set_mp1_state(tmp_adev);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -5624,28 +6413,29 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='ctx'> 		 * some audio codec errors.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (!amdgpu_device_suspend_display_audio(tmp_adev))</div><div class='del'>-			audio_suspended = true;</div><div class='add'>+			tmp_adev-&gt;pcie_reset_ctx.audio_suspended = true;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_ras_set_error_query_ready(tmp_adev, false);</div><div class='ctx'> </div><div class='ctx'> 		cancel_delayed_work_sync(&amp;tmp_adev-&gt;delayed_init_work);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(tmp_adev))</div><div class='del'>-			amdgpu_amdkfd_pre_reset(tmp_adev);</div><div class='add'>+		amdgpu_amdkfd_pre_reset(tmp_adev, reset_context);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='del'>-		 * Mark these ASICs to be reseted as untracked first</div><div class='add'>+		 * Mark these ASICs to be reset as untracked first</div><div class='ctx'> 		 * And add them back after reset completed</div><div class='ctx'> 		 */</div><div class='ctx'> 		amdgpu_unregister_gpu_instance(tmp_adev);</div><div class='ctx'> </div><div class='del'>-		drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)-&gt;fb_helper, true);</div><div class='add'>+		drm_client_dev_suspend(adev_to_drm(tmp_adev));</div><div class='ctx'> </div><div class='ctx'> 		/* disable ras on ALL IPs */</div><div class='del'>-		if (!need_emergency_restart &amp;&amp;</div><div class='del'>-		      amdgpu_device_ip_need_full_reset(tmp_adev))</div><div class='add'>+		if (!need_emergency_restart &amp;&amp; !amdgpu_reset_in_dpc(adev) &amp;&amp;</div><div class='add'>+		    amdgpu_device_ip_need_full_reset(tmp_adev))</div><div class='ctx'> 			amdgpu_ras_suspend(tmp_adev);</div><div class='ctx'> </div><div class='add'>+		amdgpu_userq_pre_reset(tmp_adev);</div><div class='add'>+</div><div class='ctx'> 		for (i = 0; i &lt; AMDGPU_MAX_RINGS; ++i) {</div><div class='ctx'> 			struct amdgpu_ring *ring = tmp_adev-&gt;rings[i];</div><div class='ctx'> </div><div class='hunk'>@@ -5659,24 +6449,18 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='ctx'> 		}</div><div class='ctx'> 		atomic_inc(&amp;tmp_adev-&gt;gpu_reset_counter);</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (need_emergency_restart)</div><div class='del'>-		goto skip_sched_resume;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Must check guilty signal here since after this point all old</div><div class='del'>-	 * HW fences are force signaled.</div><div class='del'>-	 *</div><div class='del'>-	 * job-&gt;base holds a reference to parent fence</div><div class='del'>-	 */</div><div class='del'>-	if (job &amp;&amp; dma_fence_is_signaled(&amp;job-&gt;hw_fence)) {</div><div class='del'>-		job_signaled = true;</div><div class='del'>-		dev_info(adev-&gt;dev, "Guilty job already signaled, skipping HW reset");</div><div class='del'>-		goto skip_hw_reset;</div><div class='del'>-	}</div><div class='add'>+static int amdgpu_device_asic_reset(struct amdgpu_device *adev,</div><div class='add'>+			      struct list_head *device_list,</div><div class='add'>+			      struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	int retry_limit = AMDGPU_MAX_RETRY_LIMIT;</div><div class='add'>+	int r = 0;</div><div class='ctx'> </div><div class='ctx'> retry:	/* Rest of adevs pre asic reset from XGMI hive. */</div><div class='del'>-	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='ctx'> 		r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);</div><div class='ctx'> 		/*TODO Should we stop ?*/</div><div class='ctx'> 		if (r) {</div><div class='hunk'>@@ -5684,37 +6468,57 @@ retry:	/* Rest of adevs pre asic reset from XGMI hive. */</div><div class='ctx'> 				  r, adev_to_drm(tmp_adev)-&gt;unique);</div><div class='ctx'> 			tmp_adev-&gt;asic_reset_res = r;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Drop all pending non scheduler resets. Scheduler resets</div><div class='del'>-		 * were already dropped during drm_sched_stop</div><div class='del'>-		 */</div><div class='del'>-		amdgpu_device_stop_pending_resets(tmp_adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Actual ASIC resets if needed.*/</div><div class='ctx'> 	/* Host driver will handle XGMI hive reset for SRIOV */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-		r = amdgpu_device_reset_sriov(adev, job ? false : true);</div><div class='add'>+</div><div class='add'>+		/* Bail out of reset early */</div><div class='add'>+		if (amdgpu_ras_is_rma(adev))</div><div class='add'>+			return -ENODEV;</div><div class='add'>+</div><div class='add'>+		if (amdgpu_ras_get_fed_status(adev) || amdgpu_virt_rcvd_ras_interrupt(adev)) {</div><div class='add'>+			dev_dbg(adev-&gt;dev, "Detected RAS error, wait for FLR completion\n");</div><div class='add'>+			amdgpu_ras_set_fed(adev, true);</div><div class='add'>+			set_bit(AMDGPU_HOST_FLR, &amp;reset_context-&gt;flags);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = amdgpu_device_reset_sriov(adev, reset_context);</div><div class='add'>+		if (AMDGPU_RETRY_SRIOV_RESET(r) &amp;&amp; (retry_limit--) &gt; 0) {</div><div class='add'>+			amdgpu_virt_release_full_gpu(adev, true);</div><div class='add'>+			goto retry;</div><div class='add'>+		}</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			adev-&gt;asic_reset_res = r;</div><div class='del'>-</div><div class='del'>-		/* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */</div><div class='del'>-		if (amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='del'>-			    IP_VERSION(9, 4, 2) ||</div><div class='del'>-		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||</div><div class='del'>-		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))</div><div class='del'>-			amdgpu_ras_resume(adev);</div><div class='ctx'> 	} else {</div><div class='del'>-		r = amdgpu_do_asic_reset(device_list_handle, reset_context);</div><div class='add'>+		r = amdgpu_do_asic_reset(device_list, reset_context);</div><div class='ctx'> 		if (r &amp;&amp; r == -EAGAIN)</div><div class='ctx'> 			goto retry;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-skip_hw_reset:</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='add'>+		/*</div><div class='add'>+		 * Drop any pending non scheduler resets queued before reset is done.</div><div class='add'>+		 * Any reset scheduled after this point would be valid. Scheduler resets</div><div class='add'>+		 * were already dropped during drm_sched_stop and no new ones can come</div><div class='add'>+		 * in before drm_sched_start.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_device_stop_pending_resets(tmp_adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_device_sched_resume(struct list_head *device_list,</div><div class='add'>+			      struct amdgpu_reset_context *reset_context,</div><div class='add'>+			      bool   job_signaled)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	int i, r = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Post ASIC reset for all devs .*/</div><div class='del'>-	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; AMDGPU_MAX_RINGS; ++i) {</div><div class='ctx'> 			struct amdgpu_ring *ring = tmp_adev-&gt;rings[i];</div><div class='hunk'>@@ -5722,30 +6526,51 @@ skip_hw_reset:</div><div class='ctx'> 			if (!amdgpu_ring_sched_ready(ring))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			drm_sched_start(&amp;ring-&gt;sched, true);</div><div class='add'>+			drm_sched_start(&amp;ring-&gt;sched, 0);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) &amp;&amp; !job_signaled)</div><div class='ctx'> 			drm_helper_resume_force_mode(adev_to_drm(tmp_adev));</div><div class='ctx'> </div><div class='del'>-		if (tmp_adev-&gt;asic_reset_res)</div><div class='del'>-			r = tmp_adev-&gt;asic_reset_res;</div><div class='del'>-</div><div class='del'>-		tmp_adev-&gt;asic_reset_res = 0;</div><div class='del'>-</div><div class='del'>-		if (r) {</div><div class='del'>-			/* bad news, how to tell it to userspace ? */</div><div class='del'>-			dev_info(tmp_adev-&gt;dev, "GPU reset(%d) failed\n", atomic_read(&amp;tmp_adev-&gt;gpu_reset_counter));</div><div class='del'>-			amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);</div><div class='add'>+		if (tmp_adev-&gt;asic_reset_res) {</div><div class='add'>+			/* bad news, how to tell it to userspace ?</div><div class='add'>+			 * for ras error, we should report GPU bad status instead of</div><div class='add'>+			 * reset failure</div><div class='add'>+			 */</div><div class='add'>+			if (reset_context-&gt;src != AMDGPU_RESET_SRC_RAS ||</div><div class='add'>+			    !amdgpu_ras_eeprom_check_err_threshold(tmp_adev))</div><div class='add'>+				dev_info(</div><div class='add'>+					tmp_adev-&gt;dev,</div><div class='add'>+					"GPU reset(%d) failed with error %d \n",</div><div class='add'>+					atomic_read(</div><div class='add'>+						&amp;tmp_adev-&gt;gpu_reset_counter),</div><div class='add'>+					tmp_adev-&gt;asic_reset_res);</div><div class='add'>+			amdgpu_vf_error_put(tmp_adev,</div><div class='add'>+					    AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0,</div><div class='add'>+					    tmp_adev-&gt;asic_reset_res);</div><div class='add'>+			if (!r)</div><div class='add'>+				r = tmp_adev-&gt;asic_reset_res;</div><div class='add'>+			tmp_adev-&gt;asic_reset_res = 0;</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_info(tmp_adev-&gt;dev, "GPU reset(%d) succeeded!\n", atomic_read(&amp;tmp_adev-&gt;gpu_reset_counter));</div><div class='del'>-			if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))</div><div class='del'>-				DRM_WARN("smart shift update failed\n");</div><div class='add'>+			dev_info(tmp_adev-&gt;dev, "GPU reset(%d) succeeded!\n",</div><div class='add'>+				 atomic_read(&amp;tmp_adev-&gt;gpu_reset_counter));</div><div class='add'>+			if (amdgpu_acpi_smart_shift_update(tmp_adev,</div><div class='add'>+							   AMDGPU_SS_DEV_D0))</div><div class='add'>+				dev_warn(tmp_adev-&gt;dev,</div><div class='add'>+					 "smart shift update failed\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-skip_sched_resume:</div><div class='del'>-	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_gpu_resume(struct amdgpu_device *adev,</div><div class='add'>+			      struct list_head *device_list,</div><div class='add'>+			      bool   need_emergency_restart)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='ctx'> 		/* unlock kfd: SRIOV would do it separately */</div><div class='ctx'> 		if (!need_emergency_restart &amp;&amp; !amdgpu_sriov_vf(tmp_adev))</div><div class='ctx'> 			amdgpu_amdkfd_post_reset(tmp_adev);</div><div class='hunk'>@@ -5756,18 +6581,125 @@ skip_sched_resume:</div><div class='ctx'> 		if (!adev-&gt;kfd.init_complete)</div><div class='ctx'> 			amdgpu_amdkfd_device_init(adev);</div><div class='ctx'> </div><div class='del'>-		if (audio_suspended)</div><div class='add'>+		if (tmp_adev-&gt;pcie_reset_ctx.audio_suspended)</div><div class='ctx'> 			amdgpu_device_resume_display_audio(tmp_adev);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_device_unset_mp1_state(tmp_adev);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_ras_set_error_query_ready(tmp_adev, true);</div><div class='add'>+</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,</div><div class='del'>-					    reset_list);</div><div class='del'>-	amdgpu_device_unlock_reset_domain(tmp_adev-&gt;reset_domain);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_gpu_recover - reset the asic and recover scheduler</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @job: which job trigger hang</div><div class='add'>+ * @reset_context: amdgpu reset context pointer</div><div class='add'>+ *</div><div class='add'>+ * Attempt to reset the GPU if it has hung (all asics).</div><div class='add'>+ * Attempt to do soft-reset or full-reset and reinitialize Asic</div><div class='add'>+ * Returns 0 for success or an error on failure.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='add'>+			      struct amdgpu_job *job,</div><div class='add'>+			      struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct list_head device_list;</div><div class='add'>+	bool job_signaled = false;</div><div class='add'>+	struct amdgpu_hive_info *hive = NULL;</div><div class='add'>+	int r = 0;</div><div class='add'>+	bool need_emergency_restart = false;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If it reaches here because of hang/timeout and a RAS error is</div><div class='add'>+	 * detected at the same time, let RAS recovery take care of it.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY) &amp;&amp;</div><div class='add'>+	    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+	    reset_context-&gt;src != AMDGPU_RESET_SRC_RAS) {</div><div class='add'>+		dev_dbg(adev-&gt;dev,</div><div class='add'>+			"Gpu recovery from source: %d yielding to RAS error recovery handling",</div><div class='add'>+			reset_context-&gt;src);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Special case: RAS triggered and full reset isn't supported</div><div class='add'>+	 */</div><div class='add'>+	need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Flush RAM to disk so that after reboot</div><div class='add'>+	 * the user can read log and see why the system rebooted.</div><div class='add'>+	 */</div><div class='add'>+	if (need_emergency_restart &amp;&amp; amdgpu_ras_get_context(adev) &amp;&amp;</div><div class='add'>+		amdgpu_ras_get_context(adev)-&gt;reboot) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "Emergency reboot.");</div><div class='add'>+</div><div class='add'>+		ksys_sync_helper();</div><div class='add'>+		emergency_restart();</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "GPU %s begin!. Source:  %d\n",</div><div class='add'>+		 need_emergency_restart ? "jobs stop" : "reset",</div><div class='add'>+		 reset_context-&gt;src);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (hive)</div><div class='add'>+		mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+</div><div class='add'>+	reset_context-&gt;job = job;</div><div class='add'>+	reset_context-&gt;hive = hive;</div><div class='add'>+	INIT_LIST_HEAD(&amp;device_list);</div><div class='add'>+</div><div class='add'>+	amdgpu_device_recovery_prepare(adev, &amp;device_list, hive);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		r = amdgpu_device_health_check(&amp;device_list);</div><div class='add'>+		if (r)</div><div class='add'>+			goto end_reset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Cannot be called after locking reset domain */</div><div class='add'>+	amdgpu_ras_pre_reset(adev, &amp;device_list);</div><div class='add'>+</div><div class='add'>+	/* We need to lock reset domain only once both for XGMI and single device */</div><div class='add'>+	amdgpu_device_recovery_get_reset_lock(adev, &amp;device_list);</div><div class='add'>+</div><div class='add'>+	amdgpu_device_halt_activities(adev, job, reset_context, &amp;device_list,</div><div class='add'>+				      hive, need_emergency_restart);</div><div class='add'>+	if (need_emergency_restart)</div><div class='add'>+		goto skip_sched_resume;</div><div class='add'>+	/*</div><div class='add'>+	 * Must check guilty signal here since after this point all old</div><div class='add'>+	 * HW fences are force signaled.</div><div class='add'>+	 *</div><div class='add'>+	 * job-&gt;base holds a reference to parent fence</div><div class='add'>+	 */</div><div class='add'>+	if (job &amp;&amp; dma_fence_is_signaled(&amp;job-&gt;hw_fence-&gt;base)) {</div><div class='add'>+		job_signaled = true;</div><div class='add'>+		dev_info(adev-&gt;dev, "Guilty job already signaled, skipping HW reset");</div><div class='add'>+		goto skip_hw_reset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_asic_reset(adev, &amp;device_list, reset_context);</div><div class='add'>+	if (r)</div><div class='add'>+		goto reset_unlock;</div><div class='add'>+skip_hw_reset:</div><div class='add'>+	r = amdgpu_device_sched_resume(&amp;device_list, reset_context, job_signaled);</div><div class='add'>+	if (r)</div><div class='add'>+		goto reset_unlock;</div><div class='add'>+skip_sched_resume:</div><div class='add'>+	amdgpu_device_gpu_resume(adev, &amp;device_list, need_emergency_restart);</div><div class='add'>+reset_unlock:</div><div class='add'>+	amdgpu_device_recovery_put_reset_lock(adev, &amp;device_list);</div><div class='add'>+	amdgpu_ras_post_reset(adev, &amp;device_list);</div><div class='add'>+end_reset:</div><div class='ctx'> 	if (hive) {</div><div class='ctx'> 		mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='ctx'> 		amdgpu_put_xgmi_hive(hive);</div><div class='hunk'>@@ -5777,6 +6709,19 @@ skip_sched_resume:</div><div class='ctx'> 		dev_info(adev-&gt;dev, "GPU reset end with ret = %d\n", r);</div><div class='ctx'> </div><div class='ctx'> 	atomic_set(&amp;adev-&gt;reset_domain-&gt;reset_res, r);</div><div class='add'>+</div><div class='add'>+	if (!r) {</div><div class='add'>+		struct amdgpu_task_info *ti = NULL;</div><div class='add'>+</div><div class='add'>+		if (job)</div><div class='add'>+			ti = amdgpu_vm_get_task_info_pasid(adev, job-&gt;pasid);</div><div class='add'>+</div><div class='add'>+		drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE,</div><div class='add'>+				     ti ? &amp;ti-&gt;task : NULL);</div><div class='add'>+</div><div class='add'>+		amdgpu_vm_put_task_info(ti);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5803,13 +6748,56 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,</div><div class='ctx'> 	*speed = PCI_SPEED_UNKNOWN;</div><div class='ctx'> 	*width = PCIE_LNK_WIDTH_UNKNOWN;</div><div class='ctx'> </div><div class='del'>-	while ((parent = pci_upstream_bridge(parent))) {</div><div class='del'>-		/* skip upstream/downstream switches internal to dGPU*/</div><div class='del'>-		if (parent-&gt;vendor == PCI_VENDOR_ID_ATI)</div><div class='del'>-			continue;</div><div class='add'>+	if (amdgpu_device_pcie_dynamic_switching_supported(adev)) {</div><div class='add'>+		while ((parent = pci_upstream_bridge(parent))) {</div><div class='add'>+			/* skip upstream/downstream switches internal to dGPU*/</div><div class='add'>+			if (parent-&gt;vendor == PCI_VENDOR_ID_ATI)</div><div class='add'>+				continue;</div><div class='add'>+			*speed = pcie_get_speed_cap(parent);</div><div class='add'>+			*width = pcie_get_width_cap(parent);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* use the current speeds rather than max if switching is not supported */</div><div class='add'>+		pcie_bandwidth_available(adev-&gt;pdev, NULL, speed, width);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_gpu_bandwidth - find the bandwidth of the GPU</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @speed: pointer to the speed of the link</div><div class='add'>+ * @width: pointer to the width of the link</div><div class='add'>+ *</div><div class='add'>+ * Evaluate the hierarchy to find the speed and bandwidth capabilities of the</div><div class='add'>+ * AMD dGPU which may be a virtual upstream bridge.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_device_gpu_bandwidth(struct amdgpu_device *adev,</div><div class='add'>+					enum pci_bus_speed *speed,</div><div class='add'>+					enum pcie_link_width *width)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *parent = adev-&gt;pdev;</div><div class='add'>+</div><div class='add'>+	if (!speed || !width)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	parent = pci_upstream_bridge(parent);</div><div class='add'>+	if (parent &amp;&amp; parent-&gt;vendor == PCI_VENDOR_ID_ATI) {</div><div class='add'>+		/* use the upstream/downstream switches internal to dGPU */</div><div class='ctx'> 		*speed = pcie_get_speed_cap(parent);</div><div class='ctx'> 		*width = pcie_get_width_cap(parent);</div><div class='del'>-		break;</div><div class='add'>+		while ((parent = pci_upstream_bridge(parent))) {</div><div class='add'>+			if (parent-&gt;vendor == PCI_VENDOR_ID_ATI) {</div><div class='add'>+				/* use the upstream/downstream switches internal to dGPU */</div><div class='add'>+				*speed = pcie_get_speed_cap(parent);</div><div class='add'>+				*width = pcie_get_width_cap(parent);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* use the device itself */</div><div class='add'>+		*speed = pcie_get_speed_cap(adev-&gt;pdev);</div><div class='add'>+		*width = pcie_get_width_cap(adev-&gt;pdev);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5818,15 +6806,14 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  *</div><div class='del'>- * Fetchs and stores in the driver the PCIE capabilities (gen speed</div><div class='add'>+ * Fetches and stores in the driver the PCIE capabilities (gen speed</div><div class='ctx'>  * and lanes) of the slot the device is in. Handles APUs and</div><div class='ctx'>  * virtualized environments where PCIE config space may not be available.</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct pci_dev *pdev;</div><div class='ctx'> 	enum pci_bus_speed speed_cap, platform_speed_cap;</div><div class='del'>-	enum pcie_link_width platform_link_width;</div><div class='add'>+	enum pcie_link_width platform_link_width, link_width;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_pcie_gen_cap)</div><div class='ctx'> 		adev-&gt;pm.pcie_gen_mask = amdgpu_pcie_gen_cap;</div><div class='hunk'>@@ -5848,11 +6835,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_partner_bandwidth(adev, &amp;platform_speed_cap,</div><div class='ctx'> 					&amp;platform_link_width);</div><div class='add'>+	amdgpu_device_gpu_bandwidth(adev, &amp;speed_cap, &amp;link_width);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.pcie_gen_mask == 0) {</div><div class='ctx'> 		/* asic caps */</div><div class='del'>-		pdev = adev-&gt;pdev;</div><div class='del'>-		speed_cap = pcie_get_speed_cap(pdev);</div><div class='ctx'> 		if (speed_cap == PCI_SPEED_UNKNOWN) {</div><div class='ctx'> 			adev-&gt;pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |</div><div class='ctx'> 						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |</div><div class='hunk'>@@ -5908,51 +6894,103 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (adev-&gt;pm.pcie_mlw_mask == 0) {</div><div class='add'>+		/* asic caps */</div><div class='add'>+		if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {</div><div class='add'>+			adev-&gt;pm.pcie_mlw_mask |= AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK;</div><div class='add'>+		} else {</div><div class='add'>+			switch (link_width) {</div><div class='add'>+			case PCIE_LNK_X32:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				break;</div><div class='add'>+			case PCIE_LNK_X16:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				break;</div><div class='add'>+			case PCIE_LNK_X12:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				break;</div><div class='add'>+			case PCIE_LNK_X8:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				break;</div><div class='add'>+			case PCIE_LNK_X4:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				break;</div><div class='add'>+			case PCIE_LNK_X2:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				break;</div><div class='add'>+			case PCIE_LNK_X1:</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		/* platform caps */</div><div class='ctx'> 		if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {</div><div class='ctx'> 			adev-&gt;pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			switch (platform_link_width) {</div><div class='ctx'> 			case PCIE_LNK_X32:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PCIE_LNK_X16:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PCIE_LNK_X12:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PCIE_LNK_X8:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PCIE_LNK_X4:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PCIE_LNK_X2:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='del'>-							  CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |</div><div class='add'>+							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PCIE_LNK_X1:</div><div class='del'>-				adev-&gt;pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;</div><div class='add'>+				adev-&gt;pm.pcie_mlw_mask |= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				break;</div><div class='hunk'>@@ -5975,29 +7013,37 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,</div><div class='ctx'> 				      struct amdgpu_device *peer_adev)</div><div class='ctx'> {</div><div class='ctx'> #ifdef CONFIG_HSA_AMD_P2P</div><div class='del'>-	uint64_t address_mask = peer_adev-&gt;dev-&gt;dma_mask ?</div><div class='del'>-		~*peer_adev-&gt;dev-&gt;dma_mask : ~((1ULL &lt;&lt; 32) - 1);</div><div class='del'>-	resource_size_t aper_limit =</div><div class='del'>-		adev-&gt;gmc.aper_base + adev-&gt;gmc.aper_size - 1;</div><div class='ctx'> 	bool p2p_access =</div><div class='ctx'> 		!adev-&gt;gmc.xgmi.connected_to_cpu &amp;&amp;</div><div class='ctx'> 		!(pci_p2pdma_distance(adev-&gt;pdev, peer_adev-&gt;dev, false) &lt; 0);</div><div class='add'>+	if (!p2p_access)</div><div class='add'>+		dev_info(adev-&gt;dev, "PCIe P2P access from peer device %s is not supported by the chipset\n",</div><div class='add'>+			pci_name(peer_adev-&gt;pdev));</div><div class='add'>+</div><div class='add'>+	bool is_large_bar = adev-&gt;gmc.visible_vram_size &amp;&amp;</div><div class='add'>+		adev-&gt;gmc.real_vram_size == adev-&gt;gmc.visible_vram_size;</div><div class='add'>+	bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev);</div><div class='ctx'> </div><div class='del'>-	return pcie_p2p &amp;&amp; p2p_access &amp;&amp; (adev-&gt;gmc.visible_vram_size &amp;&amp;</div><div class='del'>-		adev-&gt;gmc.real_vram_size == adev-&gt;gmc.visible_vram_size &amp;&amp;</div><div class='del'>-		!(adev-&gt;gmc.aper_base &amp; address_mask ||</div><div class='del'>-		  aper_limit &amp; address_mask));</div><div class='add'>+	if (!p2p_addressable) {</div><div class='add'>+		uint64_t address_mask = peer_adev-&gt;dev-&gt;dma_mask ?</div><div class='add'>+			~*peer_adev-&gt;dev-&gt;dma_mask : ~((1ULL &lt;&lt; 32) - 1);</div><div class='add'>+		resource_size_t aper_limit =</div><div class='add'>+			adev-&gt;gmc.aper_base + adev-&gt;gmc.aper_size - 1;</div><div class='add'>+</div><div class='add'>+		p2p_addressable = !(adev-&gt;gmc.aper_base &amp; address_mask ||</div><div class='add'>+				     aper_limit &amp; address_mask);</div><div class='add'>+	}</div><div class='add'>+	return pcie_p2p &amp;&amp; is_large_bar &amp;&amp; p2p_access &amp;&amp; p2p_addressable;</div><div class='ctx'> #else</div><div class='ctx'> 	return false;</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_device_baco_enter(struct drm_device *dev)</div><div class='add'>+int amdgpu_device_baco_enter(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_device_supports_baco(dev))</div><div class='add'>+	if (!amdgpu_device_supports_baco(adev))</div><div class='ctx'> 		return -ENOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (ras &amp;&amp; adev-&gt;ras_enabled &amp;&amp;</div><div class='hunk'>@@ -6007,13 +7053,12 @@ int amdgpu_device_baco_enter(struct drm_device *dev)</div><div class='ctx'> 	return amdgpu_dpm_baco_enter(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_device_baco_exit(struct drm_device *dev)</div><div class='add'>+int amdgpu_device_baco_exit(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_device_supports_baco(dev))</div><div class='add'>+	if (!amdgpu_device_supports_baco(adev))</div><div class='ctx'> 		return -ENOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_dpm_baco_exit(adev);</div><div class='hunk'>@@ -6024,7 +7069,7 @@ int amdgpu_device_baco_exit(struct drm_device *dev)</div><div class='ctx'> 	    adev-&gt;nbio.funcs-&gt;enable_doorbell_interrupt)</div><div class='ctx'> 		adev-&gt;nbio.funcs-&gt;enable_doorbell_interrupt(adev, true);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_passthrough(adev) &amp;&amp;</div><div class='add'>+	if (amdgpu_passthrough(adev) &amp;&amp; adev-&gt;nbio.funcs &amp;&amp;</div><div class='ctx'> 	    adev-&gt;nbio.funcs-&gt;clear_doorbell_interrupt)</div><div class='ctx'> 		adev-&gt;nbio.funcs-&gt;clear_doorbell_interrupt(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -6044,45 +7089,52 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = pci_get_drvdata(pdev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	int i;</div><div class='add'>+	struct amdgpu_hive_info *hive __free(xgmi_put_hive) =</div><div class='add'>+		amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	struct amdgpu_reset_context reset_context;</div><div class='add'>+	struct list_head device_list;</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) {</div><div class='del'>-		DRM_WARN("No support for XGMI hive yet...");</div><div class='del'>-		return PCI_ERS_RESULT_DISCONNECT;</div><div class='del'>-	}</div><div class='add'>+	dev_info(adev-&gt;dev, "PCI error: detected callback!!\n");</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;pci_channel_state = state;</div><div class='ctx'> </div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case pci_channel_io_normal:</div><div class='add'>+		dev_info(adev-&gt;dev, "pci_channel_io_normal: state(%d)!!\n", state);</div><div class='ctx'> 		return PCI_ERS_RESULT_CAN_RECOVER;</div><div class='del'>-	/* Fatal error, prepare for slot reset */</div><div class='ctx'> 	case pci_channel_io_frozen:</div><div class='del'>-		/*</div><div class='del'>-		 * Locking adev-&gt;reset_domain-&gt;sem will prevent any external access</div><div class='del'>-		 * to GPU during PCI error recovery</div><div class='del'>-		 */</div><div class='del'>-		amdgpu_device_lock_reset_domain(adev-&gt;reset_domain);</div><div class='del'>-		amdgpu_device_set_mp1_state(adev);</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Block any work scheduling as we do for regular GPU reset</div><div class='del'>-		 * for the duration of the recovery</div><div class='del'>-		 */</div><div class='del'>-		for (i = 0; i &lt; AMDGPU_MAX_RINGS; ++i) {</div><div class='del'>-			struct amdgpu_ring *ring = adev-&gt;rings[i];</div><div class='del'>-</div><div class='del'>-			if (!amdgpu_ring_sched_ready(ring))</div><div class='del'>-				continue;</div><div class='add'>+		/* Fatal error, prepare for slot reset */</div><div class='add'>+		dev_info(adev-&gt;dev, "pci_channel_io_frozen: state(%d)!!\n", state);</div><div class='add'>+		if (hive) {</div><div class='add'>+			/* Hive devices should be able to support FW based</div><div class='add'>+			 * link reset on other devices, if not return.</div><div class='add'>+			 */</div><div class='add'>+			if (!amdgpu_dpm_is_link_reset_supported(adev)) {</div><div class='add'>+				dev_warn(adev-&gt;dev,</div><div class='add'>+					 "No support for XGMI hive yet...\n");</div><div class='add'>+				return PCI_ERS_RESULT_DISCONNECT;</div><div class='add'>+			}</div><div class='add'>+			/* Set dpc status only if device is part of hive</div><div class='add'>+			 * Non-hive devices should be able to recover after</div><div class='add'>+			 * link reset.</div><div class='add'>+			 */</div><div class='add'>+			amdgpu_reset_set_dpc_status(adev, true);</div><div class='ctx'> </div><div class='del'>-			drm_sched_stop(&amp;ring-&gt;sched, NULL);</div><div class='add'>+			mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='ctx'> 		}</div><div class='del'>-		atomic_inc(&amp;adev-&gt;gpu_reset_counter);</div><div class='add'>+		memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='add'>+		INIT_LIST_HEAD(&amp;device_list);</div><div class='add'>+</div><div class='add'>+		amdgpu_device_recovery_prepare(adev, &amp;device_list, hive);</div><div class='add'>+		amdgpu_device_recovery_get_reset_lock(adev, &amp;device_list);</div><div class='add'>+		amdgpu_device_halt_activities(adev, NULL, &amp;reset_context, &amp;device_list,</div><div class='add'>+					      hive, false);</div><div class='add'>+		if (hive)</div><div class='add'>+			mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='ctx'> 		return PCI_ERS_RESULT_NEED_RESET;</div><div class='ctx'> 	case pci_channel_io_perm_failure:</div><div class='ctx'> 		/* Permanent error, prepare for device removal */</div><div class='add'>+		dev_info(adev-&gt;dev, "pci_channel_io_perm_failure: state(%d)!!\n", state);</div><div class='ctx'> 		return PCI_ERS_RESULT_DISCONNECT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -6095,8 +7147,10 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta</div><div class='ctx'>  */</div><div class='ctx'> pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='add'>+	struct drm_device *dev = pci_get_drvdata(pdev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("PCI error: mmio enabled callback!!\n");</div><div class='add'>+	dev_info(adev-&gt;dev, "PCI error: mmio enabled callback!!\n");</div><div class='ctx'> </div><div class='ctx'> 	/* TODO - dump whatever for debugging purposes */</div><div class='ctx'> </div><div class='hunk'>@@ -6120,35 +7174,38 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = pci_get_drvdata(pdev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	int r, i;</div><div class='ctx'> 	struct amdgpu_reset_context reset_context;</div><div class='del'>-	u32 memsize;</div><div class='del'>-	struct list_head device_list;</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='ctx'> 	struct amdgpu_hive_info *hive;</div><div class='del'>-	int hive_ras_recovery = 0;</div><div class='del'>-	struct amdgpu_ras *ras;</div><div class='del'>-</div><div class='del'>-	/* PCI error slot reset should be skipped During RAS recovery */</div><div class='del'>-	hive = amdgpu_get_xgmi_hive(adev);</div><div class='del'>-	if (hive) {</div><div class='del'>-		hive_ras_recovery = atomic_read(&amp;hive-&gt;ras_recovery);</div><div class='del'>-		amdgpu_put_xgmi_hive(hive);</div><div class='del'>-	}</div><div class='del'>-	ras = amdgpu_ras_get_context(adev);</div><div class='del'>-	if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) &amp;&amp;</div><div class='del'>-		 ras &amp;&amp; (atomic_read(&amp;ras-&gt;in_recovery) || hive_ras_recovery))</div><div class='del'>-		return PCI_ERS_RESULT_RECOVERED;</div><div class='add'>+	struct list_head device_list;</div><div class='add'>+	struct pci_dev *link_dev;</div><div class='add'>+	int r = 0, i, timeout;</div><div class='add'>+	u32 memsize;</div><div class='add'>+	u16 status;</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("PCI error: slot reset callback!!\n");</div><div class='add'>+	dev_info(adev-&gt;dev, "PCI error: slot reset callback!!\n");</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='ctx'> </div><div class='del'>-	INIT_LIST_HEAD(&amp;device_list);</div><div class='del'>-	list_add_tail(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+	if (adev-&gt;pcie_reset_ctx.swus)</div><div class='add'>+		link_dev = adev-&gt;pcie_reset_ctx.swus;</div><div class='add'>+	else</div><div class='add'>+		link_dev = adev-&gt;pdev;</div><div class='add'>+	/* wait for asic to come out of reset, timeout = 10s */</div><div class='add'>+	timeout = 10000;</div><div class='add'>+	do {</div><div class='add'>+		usleep_range(10000, 10500);</div><div class='add'>+		r = pci_read_config_word(link_dev, PCI_VENDOR_ID, &amp;status);</div><div class='add'>+		timeout -= 10;</div><div class='add'>+	} while (timeout &gt; 0 &amp;&amp; (status != PCI_VENDOR_ID_ATI) &amp;&amp;</div><div class='add'>+		 (status != PCI_VENDOR_ID_AMD));</div><div class='ctx'> </div><div class='del'>-	/* wait for asic to come out of reset */</div><div class='del'>-	msleep(500);</div><div class='add'>+	if ((status != PCI_VENDOR_ID_ATI) &amp;&amp; (status != PCI_VENDOR_ID_AMD)) {</div><div class='add'>+		r = -ETIME;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_device_load_switch_state(adev);</div><div class='ctx'> 	/* Restore PCI confspace */</div><div class='ctx'> 	amdgpu_device_load_pci_state(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -6168,26 +7225,40 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)</div><div class='ctx'> 	reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 	reset_context.reset_req_dev = adev;</div><div class='ctx'> 	set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='del'>-	set_bit(AMDGPU_SKIP_HW_RESET, &amp;reset_context.flags);</div><div class='del'>-</div><div class='del'>-	adev-&gt;no_hw_access = true;</div><div class='del'>-	r = amdgpu_device_pre_asic_reset(adev, &amp;reset_context);</div><div class='del'>-	adev-&gt;no_hw_access = false;</div><div class='del'>-	if (r)</div><div class='del'>-		goto out;</div><div class='add'>+	set_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context.flags);</div><div class='add'>+	INIT_LIST_HEAD(&amp;device_list);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_do_asic_reset(&amp;device_list, &amp;reset_context);</div><div class='add'>+	hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (hive) {</div><div class='add'>+		mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+		reset_context.hive = hive;</div><div class='add'>+		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='add'>+			tmp_adev-&gt;pcie_reset_ctx.in_link_reset = true;</div><div class='add'>+			list_add_tail(&amp;tmp_adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		set_bit(AMDGPU_SKIP_HW_RESET, &amp;reset_context.flags);</div><div class='add'>+		list_add_tail(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_device_asic_reset(adev, &amp;device_list, &amp;reset_context);</div><div class='ctx'> out:</div><div class='ctx'> 	if (!r) {</div><div class='ctx'> 		if (amdgpu_device_cache_pci_state(adev-&gt;pdev))</div><div class='ctx'> 			pci_restore_state(adev-&gt;pdev);</div><div class='del'>-</div><div class='del'>-		DRM_INFO("PCIe error recovery succeeded\n");</div><div class='add'>+		dev_info(adev-&gt;dev, "PCIe error recovery succeeded\n");</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_ERROR("PCIe error recovery failed, err:%d", r);</div><div class='del'>-		amdgpu_device_unset_mp1_state(adev);</div><div class='del'>-		amdgpu_device_unlock_reset_domain(adev-&gt;reset_domain);</div><div class='add'>+		dev_err(adev-&gt;dev, "PCIe error recovery failed, err:%d\n", r);</div><div class='add'>+		if (hive) {</div><div class='add'>+			list_for_each_entry(tmp_adev, &amp;device_list, reset_list)</div><div class='add'>+				amdgpu_device_unset_mp1_state(tmp_adev);</div><div class='add'>+		}</div><div class='add'>+		amdgpu_device_recovery_put_reset_lock(adev, &amp;device_list);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hive) {</div><div class='add'>+		mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;</div><div class='hunk'>@@ -6204,26 +7275,95 @@ void amdgpu_pci_resume(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = pci_get_drvdata(pdev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='add'>+	struct list_head device_list;</div><div class='add'>+	struct amdgpu_hive_info *hive = NULL;</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("PCI error: resume callback!!\n");</div><div class='add'>+	dev_info(adev-&gt;dev, "PCI error: resume callback!!\n");</div><div class='ctx'> </div><div class='ctx'> 	/* Only continue execution for the case of pci_channel_io_frozen */</div><div class='ctx'> 	if (adev-&gt;pci_channel_state != pci_channel_io_frozen)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MAX_RINGS; ++i) {</div><div class='del'>-		struct amdgpu_ring *ring = adev-&gt;rings[i];</div><div class='add'>+	INIT_LIST_HEAD(&amp;device_list);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_ring_sched_ready(ring))</div><div class='del'>-			continue;</div><div class='add'>+	hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (hive) {</div><div class='add'>+		mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='add'>+			tmp_adev-&gt;pcie_reset_ctx.in_link_reset = false;</div><div class='add'>+			list_add_tail(&amp;tmp_adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+		}</div><div class='add'>+	} else</div><div class='add'>+		list_add_tail(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+</div><div class='add'>+	amdgpu_device_sched_resume(&amp;device_list, NULL, NULL);</div><div class='add'>+	amdgpu_device_gpu_resume(adev, &amp;device_list, false);</div><div class='add'>+	amdgpu_device_recovery_put_reset_lock(adev, &amp;device_list);</div><div class='add'>+</div><div class='add'>+	if (hive) {</div><div class='add'>+		mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_cache_switch_state(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *swus, *swds;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	swds = pci_upstream_bridge(adev-&gt;pdev);</div><div class='add'>+	if (!swds || swds-&gt;vendor != PCI_VENDOR_ID_ATI ||</div><div class='add'>+	    pci_pcie_type(swds) != PCI_EXP_TYPE_DOWNSTREAM)</div><div class='add'>+		return;</div><div class='add'>+	swus = pci_upstream_bridge(swds);</div><div class='add'>+	if (!swus ||</div><div class='add'>+	    (swus-&gt;vendor != PCI_VENDOR_ID_ATI &amp;&amp;</div><div class='add'>+	     swus-&gt;vendor != PCI_VENDOR_ID_AMD) ||</div><div class='add'>+	    pci_pcie_type(swus) != PCI_EXP_TYPE_UPSTREAM)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* If already saved, return */</div><div class='add'>+	if (adev-&gt;pcie_reset_ctx.swus)</div><div class='add'>+		return;</div><div class='add'>+	/* Upstream bridge is ATI, assume it's SWUS/DS architecture */</div><div class='add'>+	r = pci_save_state(swds);</div><div class='add'>+	if (r)</div><div class='add'>+		return;</div><div class='add'>+	adev-&gt;pcie_reset_ctx.swds_pcistate = pci_store_saved_state(swds);</div><div class='add'>+</div><div class='add'>+	r = pci_save_state(swus);</div><div class='add'>+	if (r)</div><div class='add'>+		return;</div><div class='add'>+	adev-&gt;pcie_reset_ctx.swus_pcistate = pci_store_saved_state(swus);</div><div class='add'>+</div><div class='add'>+	adev-&gt;pcie_reset_ctx.swus = swus;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_device_load_switch_state(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='del'>-		drm_sched_start(&amp;ring-&gt;sched, true);</div><div class='add'>+	if (!adev-&gt;pcie_reset_ctx.swds_pcistate ||</div><div class='add'>+	    !adev-&gt;pcie_reset_ctx.swus_pcistate)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pdev = adev-&gt;pcie_reset_ctx.swus;</div><div class='add'>+	r = pci_load_saved_state(pdev, adev-&gt;pcie_reset_ctx.swus_pcistate);</div><div class='add'>+	if (!r) {</div><div class='add'>+		pci_restore_state(pdev);</div><div class='add'>+	} else {</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to load SWUS state, err:%d\n", r);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_device_unset_mp1_state(adev);</div><div class='del'>-	amdgpu_device_unlock_reset_domain(adev-&gt;reset_domain);</div><div class='add'>+	pdev = pci_upstream_bridge(adev-&gt;pdev);</div><div class='add'>+	r = pci_load_saved_state(pdev, adev-&gt;pcie_reset_ctx.swds_pcistate);</div><div class='add'>+	if (!r)</div><div class='add'>+		pci_restore_state(pdev);</div><div class='add'>+	else</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to load SWDS state, err:%d\n", r);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)</div><div class='hunk'>@@ -6232,6 +7372,9 @@ bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	r = pci_save_state(pdev);</div><div class='ctx'> 	if (!r) {</div><div class='ctx'> 		kfree(adev-&gt;pci_state);</div><div class='hunk'>@@ -6239,14 +7382,16 @@ bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)</div><div class='ctx'> 		adev-&gt;pci_state = pci_store_saved_state(pdev);</div><div class='ctx'> </div><div class='ctx'> 		if (!adev-&gt;pci_state) {</div><div class='del'>-			DRM_ERROR("Failed to store PCI saved state");</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to store PCI saved state");</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_WARN("Failed to save PCI state, err:%d\n", r);</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to save PCI state, err:%d\n", r);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_device_cache_switch_state(adev);</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6264,7 +7409,7 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev)</div><div class='ctx'> 	if (!r) {</div><div class='ctx'> 		pci_restore_state(pdev);</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_WARN("Failed to load PCI state, err:%d\n", r);</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to load PCI state, err:%d\n", r);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -6281,10 +7426,17 @@ void amdgpu_device_flush_hdp(struct amdgpu_device *adev,</div><div class='ctx'> 	if (adev-&gt;gmc.xgmi.connected_to_cpu)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (ring &amp;&amp; ring-&gt;funcs-&gt;emit_hdp_flush)</div><div class='add'>+	if (ring &amp;&amp; ring-&gt;funcs-&gt;emit_hdp_flush) {</div><div class='ctx'> 		amdgpu_ring_emit_hdp_flush(ring);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_asic_flush_hdp(adev, ring);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!ring &amp;&amp; amdgpu_sriov_runtime(adev)) {</div><div class='add'>+		if (!amdgpu_kiq_hdp_flush(adev))</div><div class='add'>+			return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_hdp_flush(adev, ring);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,</div><div class='hunk'>@@ -6297,7 +7449,7 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,</div><div class='ctx'> 	if (adev-&gt;gmc.xgmi.connected_to_cpu)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	amdgpu_asic_invalidate_hdp(adev, ring);</div><div class='add'>+	amdgpu_hdp_invalidate(adev, ring);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_in_reset(struct amdgpu_device *adev)</div><div class='hunk'>@@ -6379,6 +7531,22 @@ void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_device_get_gang - return a reference to the current gang</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns: A new reference to the current gang leader.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	fence = dma_fence_get_rcu_safe(&amp;adev-&gt;gang_submit);</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_device_switch_gang - switch to a new gang</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @gang: the gang to switch to</div><div class='hunk'>@@ -6392,25 +7560,117 @@ struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	struct dma_fence *old = NULL;</div><div class='ctx'> </div><div class='add'>+	dma_fence_get(gang);</div><div class='ctx'> 	do {</div><div class='ctx'> 		dma_fence_put(old);</div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		old = dma_fence_get_rcu_safe(&amp;adev-&gt;gang_submit);</div><div class='del'>-		rcu_read_unlock();</div><div class='del'>-</div><div class='add'>+		old = amdgpu_device_get_gang(adev);</div><div class='ctx'> 		if (old == gang)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='del'>-		if (!dma_fence_is_signaled(old))</div><div class='add'>+		if (!dma_fence_is_signaled(old)) {</div><div class='add'>+			dma_fence_put(gang);</div><div class='ctx'> 			return old;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 	} while (cmpxchg((struct dma_fence __force **)&amp;adev-&gt;gang_submit,</div><div class='ctx'> 			 old, gang) != old);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Drop it once for the exchanged reference in adev and once for the</div><div class='add'>+	 * thread local reference acquired in amdgpu_device_get_gang().</div><div class='add'>+	 */</div><div class='add'>+	dma_fence_put(old);</div><div class='ctx'> 	dma_fence_put(old);</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_device_enforce_isolation - enforce HW isolation</div><div class='add'>+ * @adev: the amdgpu device pointer</div><div class='add'>+ * @ring: the HW ring the job is supposed to run on</div><div class='add'>+ * @job: the job which is about to be pushed to the HW ring</div><div class='add'>+ *</div><div class='add'>+ * Makes sure that only one client at a time can use the GFX block.</div><div class='add'>+ * Returns: The dependency to wait on before the job can be pushed to the HW.</div><div class='add'>+ * The function is called multiple times until NULL is returned.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+						  struct amdgpu_ring *ring,</div><div class='add'>+						  struct amdgpu_job *job)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_isolation *isolation = &amp;adev-&gt;isolation[ring-&gt;xcp_id];</div><div class='add'>+	struct drm_sched_fence *f = job-&gt;base.s_fence;</div><div class='add'>+	struct dma_fence *dep;</div><div class='add'>+	void *owner;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For now enforce isolation only for the GFX block since we only need</div><div class='add'>+	 * the cleaner shader on those rings.</div><div class='add'>+	 */</div><div class='add'>+	if (ring-&gt;funcs-&gt;type != AMDGPU_RING_TYPE_GFX &amp;&amp;</div><div class='add'>+	    ring-&gt;funcs-&gt;type != AMDGPU_RING_TYPE_COMPUTE)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All submissions where enforce isolation is false are handled as if</div><div class='add'>+	 * they come from a single client. Use ~0l as the owner to distinct it</div><div class='add'>+	 * from kernel submissions where the owner is NULL.</div><div class='add'>+	 */</div><div class='add'>+	owner = job-&gt;enforce_isolation ? f-&gt;owner : (void *)~0l;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The "spearhead" submission is the first one which changes the</div><div class='add'>+	 * ownership to its client. We always need to wait for it to be</div><div class='add'>+	 * pushed to the HW before proceeding with anything.</div><div class='add'>+	 */</div><div class='add'>+	if (&amp;f-&gt;scheduled != isolation-&gt;spearhead &amp;&amp;</div><div class='add'>+	    !dma_fence_is_signaled(isolation-&gt;spearhead)) {</div><div class='add'>+		dep = isolation-&gt;spearhead;</div><div class='add'>+		goto out_grab_ref;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (isolation-&gt;owner != owner) {</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Wait for any gang to be assembled before switching to a</div><div class='add'>+		 * different owner or otherwise we could deadlock the</div><div class='add'>+		 * submissions.</div><div class='add'>+		 */</div><div class='add'>+		if (!job-&gt;gang_submit) {</div><div class='add'>+			dep = amdgpu_device_get_gang(adev);</div><div class='add'>+			if (!dma_fence_is_signaled(dep))</div><div class='add'>+				goto out_return_dep;</div><div class='add'>+			dma_fence_put(dep);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dma_fence_put(isolation-&gt;spearhead);</div><div class='add'>+		isolation-&gt;spearhead = dma_fence_get(&amp;f-&gt;scheduled);</div><div class='add'>+		amdgpu_sync_move(&amp;isolation-&gt;active, &amp;isolation-&gt;prev);</div><div class='add'>+		trace_amdgpu_isolation(isolation-&gt;owner, owner);</div><div class='add'>+		isolation-&gt;owner = owner;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Specifying the ring here helps to pipeline submissions even when</div><div class='add'>+	 * isolation is enabled. If that is not desired for testing NULL can be</div><div class='add'>+	 * used instead of the ring to enforce a CPU round trip while switching</div><div class='add'>+	 * between clients.</div><div class='add'>+	 */</div><div class='add'>+	dep = amdgpu_sync_peek_fence(&amp;isolation-&gt;prev, ring);</div><div class='add'>+	r = amdgpu_sync_fence(&amp;isolation-&gt;active, &amp;f-&gt;finished, GFP_NOWAIT);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_warn(adev-&gt;dev, "OOM tracking isolation\n");</div><div class='add'>+</div><div class='add'>+out_grab_ref:</div><div class='add'>+	dma_fence_get(dep);</div><div class='add'>+out_return_dep:</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	return dep;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='hunk'>@@ -6470,12 +7730,108 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,</div><div class='ctx'> 		tmp_ = RREG32(reg_addr);</div><div class='ctx'> 		loop--;</div><div class='ctx'> 		if (!loop) {</div><div class='del'>-			DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",</div><div class='del'>-				  inst, reg_name, (uint32_t)expected_value,</div><div class='del'>-				  (uint32_t)(tmp_ &amp; (mask)));</div><div class='add'>+			dev_warn(</div><div class='add'>+				adev-&gt;dev,</div><div class='add'>+				"Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",</div><div class='add'>+				inst, reg_name, (uint32_t)expected_value,</div><div class='add'>+				(uint32_t)(tmp_ &amp; (mask)));</div><div class='ctx'> 			ret = -ETIMEDOUT;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	ssize_t size = 0;</div><div class='add'>+</div><div class='add'>+	if (!ring || !ring-&gt;adev)</div><div class='add'>+		return size;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_device_should_recover_gpu(ring-&gt;adev))</div><div class='add'>+		size |= AMDGPU_RESET_TYPE_FULL;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!ring-&gt;adev-&gt;debug_disable_soft_recovery) &amp;&amp;</div><div class='add'>+	    !amdgpu_sriov_vf(ring-&gt;adev) &amp;&amp; ring-&gt;funcs-&gt;soft_recovery)</div><div class='add'>+		size |= AMDGPU_RESET_TYPE_SOFT_RESET;</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset)</div><div class='add'>+{</div><div class='add'>+	ssize_t size = 0;</div><div class='add'>+</div><div class='add'>+	if (supported_reset == 0) {</div><div class='add'>+		size += sysfs_emit_at(buf, size, "unsupported");</div><div class='add'>+		size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+		return size;</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (supported_reset &amp; AMDGPU_RESET_TYPE_SOFT_RESET)</div><div class='add'>+		size += sysfs_emit_at(buf, size, "soft ");</div><div class='add'>+</div><div class='add'>+	if (supported_reset &amp; AMDGPU_RESET_TYPE_PER_QUEUE)</div><div class='add'>+		size += sysfs_emit_at(buf, size, "queue ");</div><div class='add'>+</div><div class='add'>+	if (supported_reset &amp; AMDGPU_RESET_TYPE_PER_PIPE)</div><div class='add'>+		size += sysfs_emit_at(buf, size, "pipe ");</div><div class='add'>+</div><div class='add'>+	if (supported_reset &amp; AMDGPU_RESET_TYPE_FULL)</div><div class='add'>+		size += sysfs_emit_at(buf, size, "full ");</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_device_set_uid(struct amdgpu_uid *uid_info,</div><div class='add'>+			   enum amdgpu_uid_type type, uint8_t inst,</div><div class='add'>+			   uint64_t uid)</div><div class='add'>+{</div><div class='add'>+	if (!uid_info)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (type &gt;= AMDGPU_UID_TYPE_MAX) {</div><div class='add'>+		dev_err_once(uid_info-&gt;adev-&gt;dev, "Invalid UID type %d\n",</div><div class='add'>+			     type);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst &gt;= AMDGPU_UID_INST_MAX) {</div><div class='add'>+		dev_err_once(uid_info-&gt;adev-&gt;dev, "Invalid UID instance %d\n",</div><div class='add'>+			     inst);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (uid_info-&gt;uid[type][inst] != 0) {</div><div class='add'>+		dev_warn_once(</div><div class='add'>+			uid_info-&gt;adev-&gt;dev,</div><div class='add'>+			"Overwriting existing UID %llu for type %d instance %d\n",</div><div class='add'>+			uid_info-&gt;uid[type][inst], type, inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	uid_info-&gt;uid[type][inst] = uid;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info,</div><div class='add'>+			  enum amdgpu_uid_type type, uint8_t inst)</div><div class='add'>+{</div><div class='add'>+	if (!uid_info)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (type &gt;= AMDGPU_UID_TYPE_MAX) {</div><div class='add'>+		dev_err_once(uid_info-&gt;adev-&gt;dev, "Invalid UID type %d\n",</div><div class='add'>+			     type);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst &gt;= AMDGPU_UID_INST_MAX) {</div><div class='add'>+		dev_err_once(uid_info-&gt;adev-&gt;dev, "Invalid UID instance %d\n",</div><div class='add'>+			     inst);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return uid_info-&gt;uid[type][inst];</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h<br/>index 1538b2dbfff1..eb605e79ae0e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_df.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_df.h</a></div><div class='hunk'>@@ -33,6 +33,7 @@ struct amdgpu_df_hash_status {</div><div class='ctx'> struct amdgpu_df_funcs {</div><div class='ctx'> 	void (*sw_init)(struct amdgpu_device *adev);</div><div class='ctx'> 	void (*sw_fini)(struct amdgpu_device *adev);</div><div class='add'>+	void (*hw_init)(struct amdgpu_device *adev);</div><div class='ctx'> 	void (*enable_broadcast_mode)(struct amdgpu_device *adev,</div><div class='ctx'> 				      bool enable);</div><div class='ctx'> 	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c<br/>index a07e4b87d4ca..fa2a22dfa048 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'>  * copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -37,6 +37,7 @@</div><div class='ctx'> #include "df_v3_6.h"</div><div class='ctx'> #include "df_v4_3.h"</div><div class='ctx'> #include "df_v4_6_2.h"</div><div class='add'>+#include "df_v4_15.h"</div><div class='ctx'> #include "nbio_v6_1.h"</div><div class='ctx'> #include "nbio_v7_0.h"</div><div class='ctx'> #include "nbio_v7_4.h"</div><div class='hunk'>@@ -55,6 +56,7 @@</div><div class='ctx'> #include "smuio_v9_0.h"</div><div class='ctx'> #include "gmc_v10_0.h"</div><div class='ctx'> #include "gmc_v11_0.h"</div><div class='add'>+#include "gmc_v12_0.h"</div><div class='ctx'> #include "gfxhub_v2_0.h"</div><div class='ctx'> #include "mmhub_v2_0.h"</div><div class='ctx'> #include "nbio_v2_3.h"</div><div class='hunk'>@@ -68,15 +70,18 @@</div><div class='ctx'> #include "hdp_v7_0.h"</div><div class='ctx'> #include "nv.h"</div><div class='ctx'> #include "soc21.h"</div><div class='add'>+#include "soc24.h"</div><div class='ctx'> #include "navi10_ih.h"</div><div class='ctx'> #include "ih_v6_0.h"</div><div class='ctx'> #include "ih_v6_1.h"</div><div class='ctx'> #include "ih_v7_0.h"</div><div class='ctx'> #include "gfx_v10_0.h"</div><div class='ctx'> #include "gfx_v11_0.h"</div><div class='add'>+#include "gfx_v12_0.h"</div><div class='ctx'> #include "sdma_v5_0.h"</div><div class='ctx'> #include "sdma_v5_2.h"</div><div class='ctx'> #include "sdma_v6_0.h"</div><div class='add'>+#include "sdma_v7_0.h"</div><div class='ctx'> #include "lsdma_v6_0.h"</div><div class='ctx'> #include "lsdma_v7_0.h"</div><div class='ctx'> #include "vcn_v2_0.h"</div><div class='hunk'>@@ -90,20 +95,34 @@</div><div class='ctx'> #include "vcn_v4_0_5.h"</div><div class='ctx'> #include "jpeg_v4_0_5.h"</div><div class='ctx'> #include "amdgpu_vkms.h"</div><div class='del'>-#include "mes_v10_1.h"</div><div class='ctx'> #include "mes_v11_0.h"</div><div class='add'>+#include "mes_v12_0.h"</div><div class='ctx'> #include "smuio_v11_0.h"</div><div class='ctx'> #include "smuio_v11_0_6.h"</div><div class='ctx'> #include "smuio_v13_0.h"</div><div class='ctx'> #include "smuio_v13_0_3.h"</div><div class='ctx'> #include "smuio_v13_0_6.h"</div><div class='add'>+#include "smuio_v14_0_2.h"</div><div class='ctx'> #include "vcn_v5_0_0.h"</div><div class='add'>+#include "vcn_v5_0_1.h"</div><div class='ctx'> #include "jpeg_v5_0_0.h"</div><div class='add'>+#include "jpeg_v5_0_1.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_vpe.h"</div><div class='add'>+#if defined(CONFIG_DRM_AMD_ISP)</div><div class='add'>+#include "amdgpu_isp.h"</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='del'>-#define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"</div><div class='del'>-MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);</div><div class='add'>+MODULE_FIRMWARE("amdgpu/ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");</div><div class='ctx'> </div><div class='ctx'> #define mmIP_DISCOVERY_VERSION  0x16A00</div><div class='ctx'> #define mmRCC_CONFIG_MEMSIZE	0xde3</div><div class='hunk'>@@ -220,6 +239,7 @@ static int hw_id_map[MAX_HWIP] = {</div><div class='ctx'> 	[DCI_HWIP]	= DCI_HWID,</div><div class='ctx'> 	[PCIE_HWIP]	= PCIE_HWID,</div><div class='ctx'> 	[VPE_HWIP]	= VPE_HWID,</div><div class='add'>+	[ISP_HWIP]	= ISP_HWID,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)</div><div class='hunk'>@@ -235,9 +255,9 @@ static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev,</div><div class='ctx'> 	pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;</div><div class='ctx'> </div><div class='ctx'> 	/* This region is read-only and reserved from system use */</div><div class='del'>-	discv_regn = memremap(pos, adev-&gt;mman.discovery_tmr_size, MEMREMAP_WC);</div><div class='add'>+	discv_regn = memremap(pos, adev-&gt;discovery.size, MEMREMAP_WC);</div><div class='ctx'> 	if (discv_regn) {</div><div class='del'>-		memcpy(binary, discv_regn, adev-&gt;mman.discovery_tmr_size);</div><div class='add'>+		memcpy(binary, discv_regn, adev-&gt;discovery.size);</div><div class='ctx'> 		memunmap(discv_regn);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -245,60 +265,90 @@ static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev,</div><div class='ctx'> 	return -ENOENT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define IP_DISCOVERY_V2		2</div><div class='add'>+#define IP_DISCOVERY_V4		4</div><div class='add'>+</div><div class='ctx'> static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,</div><div class='ctx'> 						 uint8_t *binary)</div><div class='ctx'> {</div><div class='add'>+	bool sz_valid = true;</div><div class='ctx'> 	uint64_t vram_size;</div><div class='del'>-	u32 msg;</div><div class='ctx'> 	int i, ret = 0;</div><div class='add'>+	u32 msg;</div><div class='ctx'> </div><div class='del'>-	/* It can take up to a second for IFWI init to complete on some dGPUs,</div><div class='del'>-	 * but generally it should be in the 60-100ms range.  Normally this starts</div><div class='del'>-	 * as soon as the device gets power so by the time the OS loads this has long</div><div class='del'>-	 * completed.  However, when a card is hotplugged via e.g., USB4, we need to</div><div class='del'>-	 * wait for this to complete.  Once the C2PMSG is updated, we can</div><div class='del'>-	 * continue.</div><div class='del'>-	 */</div><div class='del'>-	if (dev_is_removable(&amp;adev-&gt;pdev-&gt;dev)) {</div><div class='del'>-		for (i = 0; i &lt; 1000; i++) {</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* It can take up to two second for IFWI init to complete on some dGPUs,</div><div class='add'>+		 * but generally it should be in the 60-100ms range.  Normally this starts</div><div class='add'>+		 * as soon as the device gets power so by the time the OS loads this has long</div><div class='add'>+		 * completed.  However, when a card is hotplugged via e.g., USB4, we need to</div><div class='add'>+		 * wait for this to complete.  Once the C2PMSG is updated, we can</div><div class='add'>+		 * continue.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; 2000; i++) {</div><div class='ctx'> 			msg = RREG32(mmMP0_SMN_C2PMSG_33);</div><div class='ctx'> 			if (msg &amp; 0x80000000)</div><div class='ctx'> 				break;</div><div class='ctx'> 			msleep(1);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) &lt;&lt; 20;</div><div class='ctx'> </div><div class='del'>-	if (vram_size) {</div><div class='del'>-		uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;</div><div class='del'>-		amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,</div><div class='del'>-					  adev-&gt;mman.discovery_tmr_size, false);</div><div class='add'>+	vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);</div><div class='add'>+	if (!vram_size || vram_size == U32_MAX)</div><div class='add'>+		sz_valid = false;</div><div class='add'>+	else</div><div class='add'>+		vram_size &lt;&lt;= 20;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If in VRAM, discovery TMR is marked for reservation. If it is in system mem,</div><div class='add'>+	 * then it is not required to be reserved.</div><div class='add'>+	 */</div><div class='add'>+	if (sz_valid) {</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;virt.is_dynamic_crit_regn_enabled) {</div><div class='add'>+			/* For SRIOV VFs with dynamic critical region enabled,</div><div class='add'>+			 * we will get the IPD binary via below call.</div><div class='add'>+			 * If dynamic critical is disabled, fall through to normal seq.</div><div class='add'>+			 */</div><div class='add'>+			if (amdgpu_virt_get_dynamic_data_info(adev,</div><div class='add'>+						AMD_SRIOV_MSG_IPD_TABLE_ID, binary,</div><div class='add'>+						&amp;adev-&gt;discovery.size)) {</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+						"failed to read discovery info from dynamic critical region.");</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+				goto exit;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;</div><div class='add'>+</div><div class='add'>+			amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,</div><div class='add'>+					adev-&gt;discovery.size, false);</div><div class='add'>+			adev-&gt;discovery.reserve_tmr = true;</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"failed to read discovery info from memory, vram size read: %llx",</div><div class='add'>+			vram_size);</div><div class='add'>+exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)</div><div class='add'>+static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,</div><div class='add'>+							uint8_t *binary,</div><div class='add'>+							const char *fw_name)</div><div class='ctx'> {</div><div class='ctx'> 	const struct firmware *fw;</div><div class='del'>-	const char *fw_name;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	switch (amdgpu_discovery) {</div><div class='del'>-	case 2:</div><div class='del'>-		fw_name = FIRMWARE_IP_DISCOVERY;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		dev_warn(adev-&gt;dev, "amdgpu_discovery is not set properly\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = request_firmware(&amp;fw, fw_name, adev-&gt;dev);</div><div class='add'>+	r = firmware_request_nowarn(&amp;fw, fw_name, adev-&gt;dev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "can't load firmware \"%s\"\n",</div><div class='del'>-			fw_name);</div><div class='add'>+		if (amdgpu_discovery == 2)</div><div class='add'>+			dev_err(adev-&gt;dev, "can't load firmware \"%s\"\n", fw_name);</div><div class='add'>+		else</div><div class='add'>+			drm_info(&amp;adev-&gt;ddev, "Optional firmware \"%s\" was not found\n", fw_name);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -358,55 +408,118 @@ static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,</div><div class='add'>+					   struct binary_header *bhdr)</div><div class='add'>+{</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='add'>+	struct table_info *info;</div><div class='add'>+	uint16_t checksum;</div><div class='add'>+	uint16_t offset;</div><div class='add'>+</div><div class='add'>+	info = &amp;bhdr-&gt;table_list[NPS_INFO];</div><div class='add'>+	offset = le16_to_cpu(info-&gt;offset);</div><div class='add'>+	checksum = le16_to_cpu(info-&gt;checksum);</div><div class='add'>+</div><div class='add'>+	struct nps_info_header *nhdr =</div><div class='add'>+		(struct nps_info_header *)(discovery_bin + offset);</div><div class='add'>+</div><div class='add'>+	if (le32_to_cpu(nhdr-&gt;table_id) != NPS_INFO_TABLE_ID) {</div><div class='add'>+		dev_dbg(adev-&gt;dev, "invalid ip discovery nps info table id\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_discovery_verify_checksum(discovery_bin + offset,</div><div class='add'>+					      le32_to_cpu(nhdr-&gt;size_bytes),</div><div class='add'>+					      checksum)) {</div><div class='add'>+		dev_dbg(adev-&gt;dev, "invalid nps info data table checksum\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_discovery == 2) {</div><div class='add'>+		/* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */</div><div class='add'>+		adev-&gt;discovery.reserve_tmr = true;</div><div class='add'>+		return "amdgpu/ip_discovery.bin";</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (adev-&gt;asic_type) {</div><div class='add'>+	case CHIP_VEGA10:</div><div class='add'>+		return "amdgpu/vega10_ip_discovery.bin";</div><div class='add'>+	case CHIP_VEGA12:</div><div class='add'>+		return "amdgpu/vega12_ip_discovery.bin";</div><div class='add'>+	case CHIP_RAVEN:</div><div class='add'>+		if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)</div><div class='add'>+			return "amdgpu/raven2_ip_discovery.bin";</div><div class='add'>+		else if (adev-&gt;apu_flags &amp; AMD_APU_IS_PICASSO)</div><div class='add'>+			return "amdgpu/picasso_ip_discovery.bin";</div><div class='add'>+		else</div><div class='add'>+			return "amdgpu/raven_ip_discovery.bin";</div><div class='add'>+	case CHIP_VEGA20:</div><div class='add'>+		return "amdgpu/vega20_ip_discovery.bin";</div><div class='add'>+	case CHIP_ARCTURUS:</div><div class='add'>+		return "amdgpu/arcturus_ip_discovery.bin";</div><div class='add'>+	case CHIP_ALDEBARAN:</div><div class='add'>+		return "amdgpu/aldebaran_ip_discovery.bin";</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct table_info *info;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='add'>+	uint8_t *discovery_bin;</div><div class='add'>+	const char *fw_name;</div><div class='ctx'> 	uint16_t offset;</div><div class='ctx'> 	uint16_t size;</div><div class='ctx'> 	uint16_t checksum;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;</div><div class='del'>-	adev-&gt;mman.discovery_bin = kzalloc(adev-&gt;mman.discovery_tmr_size, GFP_KERNEL);</div><div class='del'>-	if (!adev-&gt;mman.discovery_bin)</div><div class='add'>+	adev-&gt;discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;discovery.bin)</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	adev-&gt;discovery.size = DISCOVERY_TMR_SIZE;</div><div class='add'>+	adev-&gt;discovery.debugfs_blob.data = adev-&gt;discovery.bin;</div><div class='add'>+	adev-&gt;discovery.debugfs_blob.size = adev-&gt;discovery.size;</div><div class='ctx'> </div><div class='add'>+	discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	/* Read from file if it is the preferred option */</div><div class='del'>-	if (amdgpu_discovery == 2) {</div><div class='del'>-		dev_info(adev-&gt;dev, "use ip discovery information from file");</div><div class='del'>-		r = amdgpu_discovery_read_binary_from_file(adev, adev-&gt;mman.discovery_bin);</div><div class='del'>-</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "failed to read ip discovery binary from file\n");</div><div class='del'>-			r = -EINVAL;</div><div class='add'>+	fw_name = amdgpu_discovery_get_fw_name(adev);</div><div class='add'>+	if (fw_name != NULL) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "use ip discovery information from file");</div><div class='add'>+		r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin,</div><div class='add'>+							   fw_name);</div><div class='add'>+		if (r)</div><div class='ctx'> 			goto out;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 	} else {</div><div class='del'>-		r = amdgpu_discovery_read_binary_from_mem(</div><div class='del'>-			adev, adev-&gt;mman.discovery_bin);</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "use ip discovery information from memory");</div><div class='add'>+		r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* check the ip discovery binary signature */</div><div class='del'>-	if (!amdgpu_discovery_verify_binary_signature(adev-&gt;mman.discovery_bin)) {</div><div class='add'>+	if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) {</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='ctx'> 			"get invalid ip discovery binary signature\n");</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='ctx'> </div><div class='ctx'> 	offset = offsetof(struct binary_header, binary_checksum) +</div><div class='ctx'> 		sizeof(bhdr-&gt;binary_checksum);</div><div class='ctx'> 	size = le16_to_cpu(bhdr-&gt;binary_size) - offset;</div><div class='ctx'> 	checksum = le16_to_cpu(bhdr-&gt;binary_checksum);</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_discovery_verify_checksum(adev-&gt;mman.discovery_bin + offset,</div><div class='del'>-					      size, checksum)) {</div><div class='add'>+	if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size,</div><div class='add'>+					      checksum)) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "invalid ip discovery binary checksum\n");</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -418,15 +531,16 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (offset) {</div><div class='ctx'> 		struct ip_discovery_header *ihdr =</div><div class='del'>-			(struct ip_discovery_header *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+			(struct ip_discovery_header *)(discovery_bin + offset);</div><div class='ctx'> 		if (le32_to_cpu(ihdr-&gt;signature) != DISCOVERY_TABLE_SIGNATURE) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid ip discovery data table signature\n");</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_discovery_verify_checksum(adev-&gt;mman.discovery_bin + offset,</div><div class='del'>-						      le16_to_cpu(ihdr-&gt;size), checksum)) {</div><div class='add'>+		if (!amdgpu_discovery_verify_checksum(discovery_bin + offset,</div><div class='add'>+						      le16_to_cpu(ihdr-&gt;size),</div><div class='add'>+						      checksum)) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid ip discovery data table checksum\n");</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -439,7 +553,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (offset) {</div><div class='ctx'> 		struct gpu_info_header *ghdr =</div><div class='del'>-			(struct gpu_info_header *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+			(struct gpu_info_header *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 		if (le32_to_cpu(ghdr-&gt;table_id) != GC_TABLE_ID) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid ip discovery gc table id\n");</div><div class='hunk'>@@ -447,8 +561,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_discovery_verify_checksum(adev-&gt;mman.discovery_bin + offset,</div><div class='del'>-						      le32_to_cpu(ghdr-&gt;size), checksum)) {</div><div class='add'>+		if (!amdgpu_discovery_verify_checksum(discovery_bin + offset,</div><div class='add'>+						      le32_to_cpu(ghdr-&gt;size),</div><div class='add'>+						      checksum)) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid gc data table checksum\n");</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -461,7 +576,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (offset) {</div><div class='ctx'> 		struct harvest_info_header *hhdr =</div><div class='del'>-			(struct harvest_info_header *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+			(struct harvest_info_header *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 		if (le32_to_cpu(hhdr-&gt;signature) != HARVEST_TABLE_SIGNATURE) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid ip discovery harvest table signature\n");</div><div class='hunk'>@@ -469,8 +584,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_discovery_verify_checksum(adev-&gt;mman.discovery_bin + offset,</div><div class='del'>-						      sizeof(struct harvest_table), checksum)) {</div><div class='add'>+		if (!amdgpu_discovery_verify_checksum(</div><div class='add'>+			    discovery_bin + offset,</div><div class='add'>+			    sizeof(struct harvest_table), checksum)) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid harvest data table checksum\n");</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -483,7 +599,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (offset) {</div><div class='ctx'> 		struct vcn_info_header *vhdr =</div><div class='del'>-			(struct vcn_info_header *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+			(struct vcn_info_header *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 		if (le32_to_cpu(vhdr-&gt;table_id) != VCN_INFO_TABLE_ID) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid ip discovery vcn table id\n");</div><div class='hunk'>@@ -491,8 +607,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_discovery_verify_checksum(adev-&gt;mman.discovery_bin + offset,</div><div class='del'>-						      le32_to_cpu(vhdr-&gt;size_bytes), checksum)) {</div><div class='add'>+		if (!amdgpu_discovery_verify_checksum(</div><div class='add'>+			    discovery_bin + offset,</div><div class='add'>+			    le32_to_cpu(vhdr-&gt;size_bytes), checksum)) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid vcn data table checksum\n");</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -505,7 +622,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (0 &amp;&amp; offset) {</div><div class='ctx'> 		struct mall_info_header *mhdr =</div><div class='del'>-			(struct mall_info_header *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+			(struct mall_info_header *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 		if (le32_to_cpu(mhdr-&gt;table_id) != MALL_INFO_TABLE_ID) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid ip discovery mall table id\n");</div><div class='hunk'>@@ -513,8 +630,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_discovery_verify_checksum(adev-&gt;mman.discovery_bin + offset,</div><div class='del'>-						      le32_to_cpu(mhdr-&gt;size_bytes), checksum)) {</div><div class='add'>+		if (!amdgpu_discovery_verify_checksum(</div><div class='add'>+			    discovery_bin + offset,</div><div class='add'>+			    le32_to_cpu(mhdr-&gt;size_bytes), checksum)) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "invalid mall data table checksum\n");</div><div class='ctx'> 			r = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -524,8 +642,8 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	kfree(adev-&gt;mman.discovery_bin);</div><div class='del'>-	adev-&gt;mman.discovery_bin = NULL;</div><div class='add'>+	kfree(adev-&gt;discovery.bin);</div><div class='add'>+	adev-&gt;discovery.bin = NULL;</div><div class='ctx'> 	if ((amdgpu_discovery != 2) &amp;&amp;</div><div class='ctx'> 	    (RREG32(mmIP_DISCOVERY_VERSION) == 4))</div><div class='ctx'> 		amdgpu_ras_query_boot_status(adev, 4);</div><div class='hunk'>@@ -537,20 +655,23 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_discovery_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	amdgpu_discovery_sysfs_fini(adev);</div><div class='del'>-	kfree(adev-&gt;mman.discovery_bin);</div><div class='del'>-	adev-&gt;mman.discovery_bin = NULL;</div><div class='add'>+	kfree(adev-&gt;discovery.bin);</div><div class='add'>+	adev-&gt;discovery.bin = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip)</div><div class='add'>+static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev,</div><div class='add'>+					uint8_t instance, uint16_t hw_id)</div><div class='ctx'> {</div><div class='del'>-	if (ip-&gt;instance_number &gt;= HWIP_MAX_INSTANCE) {</div><div class='del'>-		DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n",</div><div class='del'>-			  ip-&gt;instance_number);</div><div class='add'>+	if (instance &gt;= HWIP_MAX_INSTANCE) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Unexpected instance_number (%d) from ip discovery blob\n",</div><div class='add'>+			instance);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	if (le16_to_cpu(ip-&gt;hw_id) &gt;= HW_ID_MAX) {</div><div class='del'>-		DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",</div><div class='del'>-			  le16_to_cpu(ip-&gt;hw_id));</div><div class='add'>+	if (hw_id &gt;= HW_ID_MAX) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Unexpected hw_id (%d) from ip discovery blob\n",</div><div class='add'>+			hw_id);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -560,36 +681,41 @@ static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip)</div><div class='ctx'> static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,</div><div class='ctx'> 						uint32_t *vcn_harvest_count)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	struct ip_discovery_header *ihdr;</div><div class='ctx'> 	struct die_header *dhdr;</div><div class='del'>-	struct ip_v4 *ip;</div><div class='add'>+	struct ip *ip;</div><div class='ctx'> 	uint16_t die_offset, ip_offset, num_dies, num_ips;</div><div class='add'>+	uint16_t hw_id;</div><div class='add'>+	uint8_t inst;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='del'>-	ihdr = (struct ip_discovery_header *)(adev-&gt;mman.discovery_bin +</div><div class='del'>-			le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset));</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='add'>+	ihdr = (struct ip_discovery_header</div><div class='add'>+			*)(discovery_bin +</div><div class='add'>+			   le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset));</div><div class='ctx'> 	num_dies = le16_to_cpu(ihdr-&gt;num_dies);</div><div class='ctx'> </div><div class='ctx'> 	/* scan harvest bit of all IP data structures */</div><div class='ctx'> 	for (i = 0; i &lt; num_dies; i++) {</div><div class='ctx'> 		die_offset = le16_to_cpu(ihdr-&gt;die_info[i].die_offset);</div><div class='del'>-		dhdr = (struct die_header *)(adev-&gt;mman.discovery_bin + die_offset);</div><div class='add'>+		dhdr = (struct die_header *)(discovery_bin + die_offset);</div><div class='ctx'> 		num_ips = le16_to_cpu(dhdr-&gt;num_ips);</div><div class='ctx'> 		ip_offset = die_offset + sizeof(*dhdr);</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; num_ips; j++) {</div><div class='del'>-			ip = (struct ip_v4 *)(adev-&gt;mman.discovery_bin + ip_offset);</div><div class='del'>-</div><div class='del'>-			if (amdgpu_discovery_validate_ip(ip))</div><div class='add'>+			ip = (struct ip *)(discovery_bin + ip_offset);</div><div class='add'>+			inst = ip-&gt;number_instance;</div><div class='add'>+			hw_id = le16_to_cpu(ip-&gt;hw_id);</div><div class='add'>+			if (amdgpu_discovery_validate_ip(adev, inst, hw_id))</div><div class='ctx'> 				goto next_ip;</div><div class='ctx'> </div><div class='del'>-			if (le16_to_cpu(ip-&gt;variant) == 1) {</div><div class='del'>-				switch (le16_to_cpu(ip-&gt;hw_id)) {</div><div class='add'>+			if (ip-&gt;harvest == 1) {</div><div class='add'>+				switch (hw_id) {</div><div class='ctx'> 				case VCN_HWID:</div><div class='ctx'> 					(*vcn_harvest_count)++;</div><div class='del'>-					if (ip-&gt;instance_number == 0) {</div><div class='add'>+					if (inst == 0) {</div><div class='ctx'> 						adev-&gt;vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;</div><div class='ctx'> 						adev-&gt;vcn.inst_mask &amp;=</div><div class='ctx'> 							~AMDGPU_VCN_HARVEST_VCN0;</div><div class='hunk'>@@ -611,10 +737,8 @@ static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> next_ip:</div><div class='del'>-			if (ihdr-&gt;base_addr_64_bit)</div><div class='del'>-				ip_offset += struct_size(ip, base_address_64, ip-&gt;num_base_address);</div><div class='del'>-			else</div><div class='del'>-				ip_offset += struct_size(ip, base_address, ip-&gt;num_base_address);</div><div class='add'>+			ip_offset += struct_size(ip, base_address,</div><div class='add'>+						 ip-&gt;num_base_address);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -623,13 +747,14 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,</div><div class='ctx'> 						     uint32_t *vcn_harvest_count,</div><div class='ctx'> 						     uint32_t *umc_harvest_count)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	struct harvest_table *harvest_info;</div><div class='ctx'> 	u16 offset;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	uint32_t umc_harvest_config = 0;</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='ctx'> 	offset = le16_to_cpu(bhdr-&gt;table_list[HARVEST_INFO].offset);</div><div class='ctx'> </div><div class='ctx'> 	if (!offset) {</div><div class='hunk'>@@ -637,7 +762,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	harvest_info = (struct harvest_table *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+	harvest_info = (struct harvest_table *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; 32; i++) {</div><div class='ctx'> 		if (le16_to_cpu(harvest_info-&gt;list[i].hw_id) == 0)</div><div class='hunk'>@@ -672,6 +797,12 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,</div><div class='ctx'> 			adev-&gt;sdma.sdma_mask &amp;=</div><div class='ctx'> 				~(1U &lt;&lt; harvest_info-&gt;list[i].number_instance);</div><div class='ctx'> 			break;</div><div class='add'>+#if defined(CONFIG_DRM_AMD_ISP)</div><div class='add'>+		case ISP_HWID:</div><div class='add'>+			adev-&gt;isp.harvest_config |=</div><div class='add'>+				~(1U &lt;&lt; harvest_info-&gt;list[i].number_instance);</div><div class='add'>+			break;</div><div class='add'>+#endif</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -927,8 +1058,8 @@ static void ip_disc_release(struct kobject *kobj)</div><div class='ctx'> 						       kobj);</div><div class='ctx'> 	struct amdgpu_device *adev = ip_top-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;ip_top = NULL;</div><div class='ctx'> 	kfree(ip_top);</div><div class='add'>+	adev-&gt;discovery.ip_top = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,</div><div class='hunk'>@@ -939,7 +1070,9 @@ static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,</div><div class='ctx'> 	/* Until a uniform way is figured, get mask based on hwid */</div><div class='ctx'> 	switch (hw_id) {</div><div class='ctx'> 	case VCN_HWID:</div><div class='del'>-		harvest = ((1 &lt;&lt; inst) &amp; adev-&gt;vcn.inst_mask) == 0;</div><div class='add'>+		/* VCN vs UVD+VCE */</div><div class='add'>+		if (!amdgpu_ip_version(adev, VCE_HWIP, 0))</div><div class='add'>+			harvest = ((1 &lt;&lt; inst) &amp; adev-&gt;vcn.inst_mask) == 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DMU_HWID:</div><div class='ctx'> 		if (adev-&gt;harvest_ip_mask &amp; AMD_HARVEST_IP_DMU_MASK)</div><div class='hunk'>@@ -966,7 +1099,10 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,</div><div class='ctx'> 				      const size_t _ip_offset, const int num_ips,</div><div class='ctx'> 				      bool reg_base_64)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	int ii, jj, kk, res;</div><div class='add'>+	uint16_t hw_id;</div><div class='add'>+	uint8_t inst;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("num_ips:%d", num_ips);</div><div class='ctx'> </div><div class='hunk'>@@ -981,9 +1117,11 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,</div><div class='ctx'> 			struct ip_v4 *ip;</div><div class='ctx'> 			struct ip_hw_instance *ip_hw_instance;</div><div class='ctx'> </div><div class='del'>-			ip = (struct ip_v4 *)(adev-&gt;mman.discovery_bin + ip_offset);</div><div class='del'>-			if (amdgpu_discovery_validate_ip(ip) ||</div><div class='del'>-			    le16_to_cpu(ip-&gt;hw_id) != ii)</div><div class='add'>+			ip = (struct ip_v4 *)(discovery_bin + ip_offset);</div><div class='add'>+			inst = ip-&gt;instance_number;</div><div class='add'>+			hw_id = le16_to_cpu(ip-&gt;hw_id);</div><div class='add'>+			if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||</div><div class='add'>+			    hw_id != ii)</div><div class='ctx'> 				goto next_ip;</div><div class='ctx'> </div><div class='ctx'> 			DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);</div><div class='hunk'>@@ -1066,17 +1204,20 @@ next_ip:</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct ip_discovery_top *ip_top = adev-&gt;discovery.ip_top;</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	struct ip_discovery_header *ihdr;</div><div class='ctx'> 	struct die_header *dhdr;</div><div class='del'>-	struct kset *die_kset = &amp;adev-&gt;ip_top-&gt;die_kset;</div><div class='add'>+	struct kset *die_kset = &amp;ip_top-&gt;die_kset;</div><div class='ctx'> 	u16 num_dies, die_offset, num_ips;</div><div class='ctx'> 	size_t ip_offset;</div><div class='ctx'> 	int ii, res;</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='del'>-	ihdr = (struct ip_discovery_header *)(adev-&gt;mman.discovery_bin +</div><div class='del'>-					      le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset));</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='add'>+	ihdr = (struct ip_discovery_header</div><div class='add'>+			*)(discovery_bin +</div><div class='add'>+			   le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset));</div><div class='ctx'> 	num_dies = le16_to_cpu(ihdr-&gt;num_dies);</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("number of dies: %d\n", num_dies);</div><div class='hunk'>@@ -1085,7 +1226,7 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)</div><div class='ctx'> 		struct ip_die_entry *ip_die_entry;</div><div class='ctx'> </div><div class='ctx'> 		die_offset = le16_to_cpu(ihdr-&gt;die_info[ii].die_offset);</div><div class='del'>-		dhdr = (struct die_header *)(adev-&gt;mman.discovery_bin + die_offset);</div><div class='add'>+		dhdr = (struct die_header *)(discovery_bin + die_offset);</div><div class='ctx'> 		num_ips = le16_to_cpu(dhdr-&gt;num_ips);</div><div class='ctx'> 		ip_offset = die_offset + sizeof(*dhdr);</div><div class='ctx'> </div><div class='hunk'>@@ -1119,30 +1260,32 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='add'>+	struct ip_discovery_top *ip_top;</div><div class='ctx'> 	struct kset *die_kset;</div><div class='ctx'> 	int res, ii;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;mman.discovery_bin)</div><div class='add'>+	if (!discovery_bin)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;ip_top = kzalloc(sizeof(*adev-&gt;ip_top), GFP_KERNEL);</div><div class='del'>-	if (!adev-&gt;ip_top)</div><div class='add'>+	ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL);</div><div class='add'>+	if (!ip_top)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;ip_top-&gt;adev = adev;</div><div class='del'>-</div><div class='del'>-	res = kobject_init_and_add(&amp;adev-&gt;ip_top-&gt;kobj, &amp;ip_discovery_ktype,</div><div class='add'>+	ip_top-&gt;adev = adev;</div><div class='add'>+	adev-&gt;discovery.ip_top = ip_top;</div><div class='add'>+	res = kobject_init_and_add(&amp;ip_top-&gt;kobj, &amp;ip_discovery_ktype,</div><div class='ctx'> 				   &amp;adev-&gt;dev-&gt;kobj, "ip_discovery");</div><div class='ctx'> 	if (res) {</div><div class='ctx'> 		DRM_ERROR("Couldn't init and add ip_discovery/");</div><div class='ctx'> 		goto Err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	die_kset = &amp;adev-&gt;ip_top-&gt;die_kset;</div><div class='add'>+	die_kset = &amp;ip_top-&gt;die_kset;</div><div class='ctx'> 	kobject_set_name(&amp;die_kset-&gt;kobj, "%s", "die");</div><div class='del'>-	die_kset-&gt;kobj.parent = &amp;adev-&gt;ip_top-&gt;kobj;</div><div class='add'>+	die_kset-&gt;kobj.parent = &amp;ip_top-&gt;kobj;</div><div class='ctx'> 	die_kset-&gt;kobj.ktype = &amp;die_kobj_ktype;</div><div class='del'>-	res = kset_register(&amp;adev-&gt;ip_top-&gt;die_kset);</div><div class='add'>+	res = kset_register(&amp;ip_top-&gt;die_kset);</div><div class='ctx'> 	if (res) {</div><div class='ctx'> 		DRM_ERROR("Couldn't register die_kset");</div><div class='ctx'> 		goto Err;</div><div class='hunk'>@@ -1156,7 +1299,7 @@ static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	return res;</div><div class='ctx'> Err:</div><div class='del'>-	kobject_put(&amp;adev-&gt;ip_top-&gt;kobj);</div><div class='add'>+	kobject_put(&amp;ip_top-&gt;kobj);</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1201,10 +1344,11 @@ static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct ip_discovery_top *ip_top = adev-&gt;discovery.ip_top;</div><div class='ctx'> 	struct list_head *el, *tmp;</div><div class='ctx'> 	struct kset *die_kset;</div><div class='ctx'> </div><div class='del'>-	die_kset = &amp;adev-&gt;ip_top-&gt;die_kset;</div><div class='add'>+	die_kset = &amp;ip_top-&gt;die_kset;</div><div class='ctx'> 	spin_lock(&amp;die_kset-&gt;list_lock);</div><div class='ctx'> 	list_for_each_prev_safe(el, tmp, &amp;die_kset-&gt;list) {</div><div class='ctx'> 		list_del_init(el);</div><div class='hunk'>@@ -1213,8 +1357,8 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		spin_lock(&amp;die_kset-&gt;list_lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock(&amp;die_kset-&gt;list_lock);</div><div class='del'>-	kobject_put(&amp;adev-&gt;ip_top-&gt;die_kset.kobj);</div><div class='del'>-	kobject_put(&amp;adev-&gt;ip_top-&gt;kobj);</div><div class='add'>+	kobject_put(&amp;ip_top-&gt;die_kset.kobj);</div><div class='add'>+	kobject_put(&amp;ip_top-&gt;kobj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* ================================================== */</div><div class='hunk'>@@ -1225,35 +1369,39 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	struct ip_discovery_header *ihdr;</div><div class='ctx'> 	struct die_header *dhdr;</div><div class='add'>+	uint8_t *discovery_bin;</div><div class='ctx'> 	struct ip_v4 *ip;</div><div class='ctx'> 	uint16_t die_offset;</div><div class='ctx'> 	uint16_t ip_offset;</div><div class='ctx'> 	uint16_t num_dies;</div><div class='add'>+	uint32_t wafl_ver;</div><div class='ctx'> 	uint16_t num_ips;</div><div class='add'>+	uint16_t hw_id;</div><div class='add'>+	uint8_t inst;</div><div class='ctx'> 	int hw_ip;</div><div class='ctx'> 	int i, j, k;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_discovery_init(adev);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("amdgpu_discovery_init failed\n");</div><div class='add'>+	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+	discovery_bin = adev-&gt;discovery.bin;</div><div class='add'>+	wafl_ver = 0;</div><div class='ctx'> 	adev-&gt;gfx.xcc_mask = 0;</div><div class='ctx'> 	adev-&gt;sdma.sdma_mask = 0;</div><div class='ctx'> 	adev-&gt;vcn.inst_mask = 0;</div><div class='ctx'> 	adev-&gt;jpeg.inst_mask = 0;</div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='del'>-	ihdr = (struct ip_discovery_header *)(adev-&gt;mman.discovery_bin +</div><div class='del'>-			le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset));</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='add'>+	ihdr = (struct ip_discovery_header</div><div class='add'>+			*)(discovery_bin +</div><div class='add'>+			   le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset));</div><div class='ctx'> 	num_dies = le16_to_cpu(ihdr-&gt;num_dies);</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("number of dies: %d\n", num_dies);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_dies; i++) {</div><div class='ctx'> 		die_offset = le16_to_cpu(ihdr-&gt;die_info[i].die_offset);</div><div class='del'>-		dhdr = (struct die_header *)(adev-&gt;mman.discovery_bin + die_offset);</div><div class='add'>+		dhdr = (struct die_header *)(discovery_bin + die_offset);</div><div class='ctx'> 		num_ips = le16_to_cpu(dhdr-&gt;num_ips);</div><div class='ctx'> 		ip_offset = die_offset + sizeof(*dhdr);</div><div class='ctx'> </div><div class='hunk'>@@ -1267,9 +1415,11 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)</div><div class='ctx'> 				le16_to_cpu(dhdr-&gt;die_id), num_ips);</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; num_ips; j++) {</div><div class='del'>-			ip = (struct ip_v4 *)(adev-&gt;mman.discovery_bin + ip_offset);</div><div class='add'>+			ip = (struct ip_v4 *)(discovery_bin + ip_offset);</div><div class='ctx'> </div><div class='del'>-			if (amdgpu_discovery_validate_ip(ip))</div><div class='add'>+			inst = ip-&gt;instance_number;</div><div class='add'>+			hw_id = le16_to_cpu(ip-&gt;hw_id);</div><div class='add'>+			if (amdgpu_discovery_validate_ip(adev, inst, hw_id))</div><div class='ctx'> 				goto next_ip;</div><div class='ctx'> </div><div class='ctx'> 			num_base_address = ip-&gt;num_base_address;</div><div class='hunk'>@@ -1290,7 +1440,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)</div><div class='ctx'> 				 */</div><div class='ctx'> 				if (adev-&gt;vcn.num_vcn_inst &lt;</div><div class='ctx'> 				    AMDGPU_MAX_VCN_INSTANCES) {</div><div class='del'>-					adev-&gt;vcn.vcn_config[adev-&gt;vcn.num_vcn_inst] =</div><div class='add'>+					adev-&gt;vcn.inst[adev-&gt;vcn.num_vcn_inst].vcn_config =</div><div class='ctx'> 						ip-&gt;revision &amp; 0xc0;</div><div class='ctx'> 					adev-&gt;vcn.num_vcn_inst++;</div><div class='ctx'> 					adev-&gt;vcn.inst_mask |=</div><div class='hunk'>@@ -1338,6 +1488,10 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)</div><div class='ctx'> 				adev-&gt;gfx.xcc_mask |=</div><div class='ctx'> 					(1U &lt;&lt; ip-&gt;instance_number);</div><div class='ctx'> </div><div class='add'>+			if (!wafl_ver &amp;&amp; le16_to_cpu(ip-&gt;hw_id) == WAFLC_HWID)</div><div class='add'>+				wafl_ver = IP_VERSION_FULL(ip-&gt;major, ip-&gt;minor,</div><div class='add'>+							   ip-&gt;revision, 0, 0);</div><div class='add'>+</div><div class='ctx'> 			for (k = 0; k &lt; num_base_address; k++) {</div><div class='ctx'> 				/*</div><div class='ctx'> 				 * convert the endianness of base addresses in place,</div><div class='hunk'>@@ -1403,21 +1557,32 @@ next_ip:</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (wafl_ver &amp;&amp; !adev-&gt;ip_versions[XGMI_HWIP][0])</div><div class='add'>+		adev-&gt;ip_versions[XGMI_HWIP][0] = wafl_ver;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='add'>+	struct ip_discovery_header *ihdr;</div><div class='add'>+	struct binary_header *bhdr;</div><div class='ctx'> 	int vcn_harvest_count = 0;</div><div class='ctx'> 	int umc_harvest_count = 0;</div><div class='add'>+	uint16_t offset, ihdr_ver;</div><div class='ctx'> </div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='add'>+	offset = le16_to_cpu(bhdr-&gt;table_list[IP_DISCOVERY].offset);</div><div class='add'>+	ihdr = (struct ip_discovery_header *)(discovery_bin + offset);</div><div class='add'>+	ihdr_ver = le16_to_cpu(ihdr-&gt;version);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Harvest table does not fit Navi1x and legacy GPUs,</div><div class='ctx'> 	 * so read harvest bit per IP data structure to set</div><div class='ctx'> 	 * harvest configuration.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(10, 2, 0) &amp;&amp;</div><div class='del'>-	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) {</div><div class='add'>+	    ihdr_ver &lt;= 2) {</div><div class='ctx'> 		if ((adev-&gt;pdev-&gt;device == 0x731E &amp;&amp;</div><div class='ctx'> 			(adev-&gt;pdev-&gt;revision == 0xC6 ||</div><div class='ctx'> 			 adev-&gt;pdev-&gt;revision == 0xC7)) ||</div><div class='hunk'>@@ -1449,28 +1614,30 @@ union gc_info {</div><div class='ctx'> 	struct gc_info_v1_0 v1;</div><div class='ctx'> 	struct gc_info_v1_1 v1_1;</div><div class='ctx'> 	struct gc_info_v1_2 v1_2;</div><div class='add'>+	struct gc_info_v1_3 v1_3;</div><div class='ctx'> 	struct gc_info_v2_0 v2;</div><div class='ctx'> 	struct gc_info_v2_1 v2_1;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	union gc_info *gc_info;</div><div class='ctx'> 	u16 offset;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;mman.discovery_bin) {</div><div class='add'>+	if (!discovery_bin) {</div><div class='ctx'> 		DRM_ERROR("ip discovery uninitialized\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='ctx'> 	offset = le16_to_cpu(bhdr-&gt;table_list[GC].offset);</div><div class='ctx'> </div><div class='ctx'> 	if (!offset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	gc_info = (union gc_info *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+	gc_info = (union gc_info *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 	switch (le16_to_cpu(gc_info-&gt;v1.header.version_major)) {</div><div class='ctx'> 	case 1:</div><div class='hunk'>@@ -1507,6 +1674,16 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info-&gt;v1_2.gc_gl1c_size_per_instance);</div><div class='ctx'> 			adev-&gt;gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info-&gt;v1_2.gc_gl2c_per_gpu);</div><div class='ctx'> 		}</div><div class='add'>+		if (le16_to_cpu(gc_info-&gt;v1.header.version_minor) &gt;= 3) {</div><div class='add'>+			adev-&gt;gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info-&gt;v1_3.gc_tcp_size_per_cu);</div><div class='add'>+			adev-&gt;gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info-&gt;v1_3.gc_tcp_cache_line_size);</div><div class='add'>+			adev-&gt;gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info-&gt;v1_3.gc_instruction_cache_size_per_sqc);</div><div class='add'>+			adev-&gt;gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info-&gt;v1_3.gc_instruction_cache_line_size);</div><div class='add'>+			adev-&gt;gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info-&gt;v1_3.gc_scalar_data_cache_size_per_sqc);</div><div class='add'>+			adev-&gt;gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info-&gt;v1_3.gc_scalar_data_cache_line_size);</div><div class='add'>+			adev-&gt;gfx.config.gc_tcc_size = le32_to_cpu(gc_info-&gt;v1_3.gc_tcc_size);</div><div class='add'>+			adev-&gt;gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info-&gt;v1_3.gc_tcc_cache_line_size);</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='ctx'> 		adev-&gt;gfx.config.max_shader_engines = le32_to_cpu(gc_info-&gt;v2.gc_num_se);</div><div class='hunk'>@@ -1553,24 +1730,25 @@ union mall_info {</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	union mall_info *mall_info;</div><div class='ctx'> 	u32 u, mall_size_per_umc, m_s_present, half_use;</div><div class='ctx'> 	u64 mall_size;</div><div class='ctx'> 	u16 offset;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;mman.discovery_bin) {</div><div class='add'>+	if (!discovery_bin) {</div><div class='ctx'> 		DRM_ERROR("ip discovery uninitialized\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='ctx'> 	offset = le16_to_cpu(bhdr-&gt;table_list[MALL_INFO].offset);</div><div class='ctx'> </div><div class='ctx'> 	if (!offset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	mall_info = (union mall_info *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+	mall_info = (union mall_info *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 	switch (le16_to_cpu(mall_info-&gt;v1.header.version_major)) {</div><div class='ctx'> 	case 1:</div><div class='hunk'>@@ -1591,7 +1769,7 @@ static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='ctx'> 		mall_size_per_umc = le32_to_cpu(mall_info-&gt;v2.mall_size_per_umc);</div><div class='del'>-		adev-&gt;gmc.mall_size = mall_size_per_umc * adev-&gt;gmc.num_umc;</div><div class='add'>+		adev-&gt;gmc.mall_size = (uint64_t)mall_size_per_umc * adev-&gt;gmc.num_umc;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='hunk'>@@ -1609,12 +1787,13 @@ union vcn_info {</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='ctx'> 	struct binary_header *bhdr;</div><div class='ctx'> 	union vcn_info *vcn_info;</div><div class='ctx'> 	u16 offset;</div><div class='ctx'> 	int v;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;mman.discovery_bin) {</div><div class='add'>+	if (!discovery_bin) {</div><div class='ctx'> 		DRM_ERROR("ip discovery uninitialized\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1629,13 +1808,13 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bhdr = (struct binary_header *)adev-&gt;mman.discovery_bin;</div><div class='add'>+	bhdr = (struct binary_header *)discovery_bin;</div><div class='ctx'> 	offset = le16_to_cpu(bhdr-&gt;table_list[VCN_INFO].offset);</div><div class='ctx'> </div><div class='ctx'> 	if (!offset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	vcn_info = (union vcn_info *)(adev-&gt;mman.discovery_bin + offset);</div><div class='add'>+	vcn_info = (union vcn_info *)(discovery_bin + offset);</div><div class='ctx'> </div><div class='ctx'> 	switch (le16_to_cpu(vcn_info-&gt;v1.header.version_major)) {</div><div class='ctx'> 	case 1:</div><div class='hunk'>@@ -1643,7 +1822,7 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)</div><div class='ctx'> 		 * so this won't overflow.</div><div class='ctx'> 		 */</div><div class='ctx'> 		for (v = 0; v &lt; adev-&gt;vcn.num_vcn_inst; v++) {</div><div class='del'>-			adev-&gt;vcn.vcn_codec_disable_mask[v] =</div><div class='add'>+			adev-&gt;vcn.inst[v].vcn_codec_disable_mask =</div><div class='ctx'> 				le32_to_cpu(vcn_info-&gt;v1.instance_info[v].fuse_data.all_bits);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1657,6 +1836,109 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+union nps_info {</div><div class='add'>+	struct nps_info_v1_0 v1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev,</div><div class='add'>+					     union nps_info *nps_data)</div><div class='add'>+{</div><div class='add'>+	uint64_t vram_size, pos, offset;</div><div class='add'>+	struct nps_info_header *nhdr;</div><div class='add'>+	struct binary_header bhdr;</div><div class='add'>+	uint16_t checksum;</div><div class='add'>+</div><div class='add'>+	vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) &lt;&lt; 20;</div><div class='add'>+	pos = vram_size - DISCOVERY_TMR_OFFSET;</div><div class='add'>+	amdgpu_device_vram_access(adev, pos, &amp;bhdr, sizeof(bhdr), false);</div><div class='add'>+</div><div class='add'>+	offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset);</div><div class='add'>+	checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum);</div><div class='add'>+</div><div class='add'>+	amdgpu_device_vram_access(adev, (pos + offset), nps_data,</div><div class='add'>+				  sizeof(*nps_data), false);</div><div class='add'>+</div><div class='add'>+	nhdr = (struct nps_info_header *)(nps_data);</div><div class='add'>+	if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data,</div><div class='add'>+					      le32_to_cpu(nhdr-&gt;size_bytes),</div><div class='add'>+					      checksum)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "nps data refresh, checksum mismatch\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,</div><div class='add'>+				  uint32_t *nps_type,</div><div class='add'>+				  struct amdgpu_gmc_memrange **ranges,</div><div class='add'>+				  int *range_cnt, bool refresh)</div><div class='add'>+{</div><div class='add'>+	uint8_t *discovery_bin = adev-&gt;discovery.bin;</div><div class='add'>+	struct amdgpu_gmc_memrange *mem_ranges;</div><div class='add'>+	struct binary_header *bhdr;</div><div class='add'>+	union nps_info *nps_info;</div><div class='add'>+	union nps_info nps_data;</div><div class='add'>+	u16 offset;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!nps_type || !range_cnt || !ranges)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (refresh) {</div><div class='add'>+		r = amdgpu_discovery_refresh_nps_info(adev, &amp;nps_data);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+		nps_info = &amp;nps_data;</div><div class='add'>+	} else {</div><div class='add'>+		if (!discovery_bin) {</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"fetch mem range failed, ip discovery uninitialized\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		bhdr = (struct binary_header *)discovery_bin;</div><div class='add'>+		offset = le16_to_cpu(bhdr-&gt;table_list[NPS_INFO].offset);</div><div class='add'>+</div><div class='add'>+		if (!offset)</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='add'>+		/* If verification fails, return as if NPS table doesn't exist */</div><div class='add'>+		if (amdgpu_discovery_verify_npsinfo(adev, bhdr))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='add'>+		nps_info = (union nps_info *)(discovery_bin + offset);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (le16_to_cpu(nps_info-&gt;v1.header.version_major)) {</div><div class='add'>+	case 1:</div><div class='add'>+		mem_ranges = kvcalloc(nps_info-&gt;v1.count,</div><div class='add'>+				      sizeof(*mem_ranges),</div><div class='add'>+				      GFP_KERNEL);</div><div class='add'>+		if (!mem_ranges)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		*nps_type = nps_info-&gt;v1.nps_type;</div><div class='add'>+		*range_cnt = nps_info-&gt;v1.count;</div><div class='add'>+		for (i = 0; i &lt; *range_cnt; i++) {</div><div class='add'>+			mem_ranges[i].base_address =</div><div class='add'>+				nps_info-&gt;v1.instance_info[i].base_address;</div><div class='add'>+			mem_ranges[i].limit_address =</div><div class='add'>+				nps_info-&gt;v1.instance_info[i].limit_address;</div><div class='add'>+			mem_ranges[i].nid_mask = -1;</div><div class='add'>+			mem_ranges[i].flags = 0;</div><div class='add'>+		}</div><div class='add'>+		*ranges = mem_ranges;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "Unhandled NPS info table %d.%d\n",</div><div class='add'>+			le16_to_cpu(nps_info-&gt;v1.header.version_major),</div><div class='add'>+			le16_to_cpu(nps_info-&gt;v1.header.version_minor));</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	/* what IP to use for this? */</div><div class='hunk'>@@ -1670,6 +1952,8 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(9, 4, 1):</div><div class='ctx'> 	case IP_VERSION(9, 4, 2):</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;vega10_common_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(10, 1, 10):</div><div class='hunk'>@@ -1694,8 +1978,14 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;soc21_common_ip_block);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;soc24_common_ip_block);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='ctx'> 			"Failed to add common ip block(GC_HWIP:0x%x)\n",</div><div class='hunk'>@@ -1718,6 +2008,8 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(9, 4, 1):</div><div class='ctx'> 	case IP_VERSION(9, 4, 2):</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gmc_v9_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(10, 1, 10):</div><div class='hunk'>@@ -1742,8 +2034,14 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gmc_v11_0_ip_block);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;gmc_v12_0_ip_block);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",</div><div class='ctx'> 			amdgpu_ip_version(adev, GC_HWIP, 0));</div><div class='hunk'>@@ -1766,6 +2064,7 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(4, 2, 1):</div><div class='ctx'> 	case IP_VERSION(4, 4, 0):</div><div class='ctx'> 	case IP_VERSION(4, 4, 2):</div><div class='add'>+	case IP_VERSION(4, 4, 5):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;vega20_ih_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(5, 0, 0):</div><div class='hunk'>@@ -1816,6 +2115,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 12):</div><div class='ctx'> 	case IP_VERSION(11, 0, 13):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;psp_v11_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 0, 8):</div><div class='hunk'>@@ -1835,8 +2135,11 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(13, 0, 8):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='ctx'> 	case IP_VERSION(13, 0, 11):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 	case IP_VERSION(14, 0, 0):</div><div class='ctx'> 	case IP_VERSION(14, 0, 1):</div><div class='add'>+	case IP_VERSION(14, 0, 4):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;psp_v13_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(13, 0, 4):</div><div class='hunk'>@@ -1844,6 +2147,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(14, 0, 2):</div><div class='ctx'> 	case IP_VERSION(14, 0, 3):</div><div class='add'>+	case IP_VERSION(14, 0, 5):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;psp_v14_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1871,13 +2175,17 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 5):</div><div class='ctx'> 	case IP_VERSION(11, 0, 9):</div><div class='ctx'> 	case IP_VERSION(11, 0, 7):</div><div class='del'>-	case IP_VERSION(11, 0, 8):</div><div class='ctx'> 	case IP_VERSION(11, 0, 11):</div><div class='ctx'> 	case IP_VERSION(11, 0, 12):</div><div class='ctx'> 	case IP_VERSION(11, 0, 13):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;smu_v11_0_ip_block);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(11, 0, 8):</div><div class='add'>+		if (adev-&gt;apu_flags &amp; AMD_APU_IS_CYAN_SKILLFISH2)</div><div class='add'>+			amdgpu_device_ip_block_add(adev, &amp;smu_v11_0_ip_block);</div><div class='add'>+		break;</div><div class='ctx'> 	case IP_VERSION(12, 0, 0):</div><div class='ctx'> 	case IP_VERSION(12, 0, 1):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;smu_v12_0_ip_block);</div><div class='hunk'>@@ -1893,9 +2201,16 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(13, 0, 8):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='ctx'> 	case IP_VERSION(13, 0, 11):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;smu_v13_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(14, 0, 0):</div><div class='add'>+	case IP_VERSION(14, 0, 1):</div><div class='add'>+	case IP_VERSION(14, 0, 2):</div><div class='add'>+	case IP_VERSION(14, 0, 3):</div><div class='add'>+	case IP_VERSION(14, 0, 4):</div><div class='add'>+	case IP_VERSION(14, 0, 5):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;smu_v14_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1947,6 +2262,12 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		case IP_VERSION(3, 2, 1):</div><div class='ctx'> 		case IP_VERSION(3, 5, 0):</div><div class='ctx'> 		case IP_VERSION(3, 5, 1):</div><div class='add'>+		case IP_VERSION(3, 6, 0):</div><div class='add'>+		case IP_VERSION(4, 1, 0):</div><div class='add'>+			/* TODO: Fix IP version. DC code expects version 4.0.1 */</div><div class='add'>+			if (adev-&gt;ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))</div><div class='add'>+				adev-&gt;ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);</div><div class='add'>+</div><div class='ctx'> 			if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 				amdgpu_discovery_set_sriov_display(adev);</div><div class='ctx'> 			else</div><div class='hunk'>@@ -1993,6 +2314,8 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gfx_v9_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gfx_v9_4_3_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(10, 1, 10):</div><div class='hunk'>@@ -2017,8 +2340,14 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gfx_v11_0_ip_block);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;gfx_v12_0_ip_block);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",</div><div class='ctx'> 			amdgpu_ip_version(adev, GC_HWIP, 0));</div><div class='hunk'>@@ -2041,6 +2370,8 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;sdma_v4_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(4, 4, 2):</div><div class='add'>+	case IP_VERSION(4, 4, 5):</div><div class='add'>+	case IP_VERSION(4, 4, 4):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;sdma_v4_4_2_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(5, 0, 0):</div><div class='hunk'>@@ -2065,14 +2396,35 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(6, 0, 3):</div><div class='ctx'> 	case IP_VERSION(6, 1, 0):</div><div class='ctx'> 	case IP_VERSION(6, 1, 1):</div><div class='add'>+	case IP_VERSION(6, 1, 2):</div><div class='add'>+	case IP_VERSION(6, 1, 3):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;sdma_v6_0_ip_block);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(7, 0, 0):</div><div class='add'>+	case IP_VERSION(7, 0, 1):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;sdma_v7_0_ip_block);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='ctx'> 			"Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",</div><div class='ctx'> 			amdgpu_ip_version(adev, SDMA0_HWIP, 0));</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;ras_v1_0_ip_block);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2159,6 +2511,10 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;vcn_v5_0_0_ip_block);</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;jpeg_v5_0_0_ip_block);</div><div class='ctx'> 			break;</div><div class='add'>+		case IP_VERSION(5, 0, 1):</div><div class='add'>+			amdgpu_device_ip_block_add(adev, &amp;vcn_v5_0_1_ip_block);</div><div class='add'>+			amdgpu_device_ip_block_add(adev, &amp;jpeg_v5_0_1_ip_block);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			dev_err(adev-&gt;dev,</div><div class='ctx'> 				"Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",</div><div class='hunk'>@@ -2172,25 +2528,6 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(10, 1, 10):</div><div class='del'>-	case IP_VERSION(10, 1, 1):</div><div class='del'>-	case IP_VERSION(10, 1, 2):</div><div class='del'>-	case IP_VERSION(10, 1, 3):</div><div class='del'>-	case IP_VERSION(10, 1, 4):</div><div class='del'>-	case IP_VERSION(10, 3, 0):</div><div class='del'>-	case IP_VERSION(10, 3, 1):</div><div class='del'>-	case IP_VERSION(10, 3, 2):</div><div class='del'>-	case IP_VERSION(10, 3, 3):</div><div class='del'>-	case IP_VERSION(10, 3, 4):</div><div class='del'>-	case IP_VERSION(10, 3, 5):</div><div class='del'>-	case IP_VERSION(10, 3, 6):</div><div class='del'>-		if (amdgpu_mes) {</div><div class='del'>-			amdgpu_device_ip_block_add(adev, &amp;mes_v10_1_ip_block);</div><div class='del'>-			adev-&gt;enable_mes = true;</div><div class='del'>-			if (amdgpu_mes_kiq)</div><div class='del'>-				adev-&gt;enable_mes_kiq = true;</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='ctx'> 	case IP_VERSION(11, 0, 0):</div><div class='ctx'> 	case IP_VERSION(11, 0, 1):</div><div class='ctx'> 	case IP_VERSION(11, 0, 2):</div><div class='hunk'>@@ -2198,10 +2535,20 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;mes_v11_0_ip_block);</div><div class='ctx'> 		adev-&gt;enable_mes = true;</div><div class='ctx'> 		adev-&gt;enable_mes_kiq = true;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;mes_v12_0_ip_block);</div><div class='add'>+		adev-&gt;enable_mes = true;</div><div class='add'>+		adev-&gt;enable_mes_kiq = true;</div><div class='add'>+		if (amdgpu_uni_mes)</div><div class='add'>+			adev-&gt;enable_uni_mes = true;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2212,6 +2559,8 @@ static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		aqua_vanjaram_init_soc_config(adev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -2224,6 +2573,7 @@ static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 1, 0):</div><div class='ctx'> 	case IP_VERSION(6, 1, 1):</div><div class='add'>+	case IP_VERSION(6, 1, 3):</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;vpe_v6_1_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -2237,6 +2587,7 @@ static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 0, 5):</div><div class='add'>+	case IP_VERSION(4, 0, 6):</div><div class='ctx'> 		if (amdgpu_umsch_mm &amp; 0x1) {</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;umsch_mm_v4_0_ip_block);</div><div class='ctx'> 			adev-&gt;enable_umsch_mm = true;</div><div class='hunk'>@@ -2249,15 +2600,40 @@ static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DRM_AMD_ISP)</div><div class='add'>+	switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(4, 1, 0):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;isp_v4_1_0_ip_block);</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(4, 1, 1):</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;isp_v4_1_1_ip_block);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> 	case CHIP_VEGA10:</div><div class='add'>+		/* This is not fatal.  We only need the discovery</div><div class='add'>+		 * binary for sysfs.  We don't need it for a</div><div class='add'>+		 * functional system.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_discovery_init(adev);</div><div class='ctx'> 		vega10_reg_base_init(adev);</div><div class='ctx'> 		adev-&gt;sdma.num_instances = 2;</div><div class='add'>+		adev-&gt;sdma.sdma_mask = 3;</div><div class='ctx'> 		adev-&gt;gmc.num_umc = 4;</div><div class='add'>+		adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 		adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);</div><div class='hunk'>@@ -2277,9 +2653,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_VEGA12:</div><div class='add'>+		/* This is not fatal.  We only need the discovery</div><div class='add'>+		 * binary for sysfs.  We don't need it for a</div><div class='add'>+		 * functional system.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_discovery_init(adev);</div><div class='ctx'> 		vega10_reg_base_init(adev);</div><div class='ctx'> 		adev-&gt;sdma.num_instances = 2;</div><div class='add'>+		adev-&gt;sdma.sdma_mask = 3;</div><div class='ctx'> 		adev-&gt;gmc.num_umc = 4;</div><div class='add'>+		adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 		adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);</div><div class='hunk'>@@ -2299,10 +2682,17 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_RAVEN:</div><div class='add'>+		/* This is not fatal.  We only need the discovery</div><div class='add'>+		 * binary for sysfs.  We don't need it for a</div><div class='add'>+		 * functional system.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_discovery_init(adev);</div><div class='ctx'> 		vega10_reg_base_init(adev);</div><div class='ctx'> 		adev-&gt;sdma.num_instances = 1;</div><div class='add'>+		adev-&gt;sdma.sdma_mask = 1;</div><div class='ctx'> 		adev-&gt;vcn.num_vcn_inst = 1;</div><div class='ctx'> 		adev-&gt;gmc.num_umc = 2;</div><div class='add'>+		adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 		if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2) {</div><div class='ctx'> 			adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);</div><div class='ctx'> 			adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);</div><div class='hunk'>@@ -2319,6 +2709,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);</div><div class='ctx'> 			adev-&gt;ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);</div><div class='ctx'> 			adev-&gt;ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);</div><div class='add'>+			adev-&gt;ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);</div><div class='ctx'> 			adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);</div><div class='hunk'>@@ -2335,12 +2726,20 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);</div><div class='ctx'> 			adev-&gt;ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);</div><div class='ctx'> 			adev-&gt;ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);</div><div class='add'>+			adev-&gt;ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_VEGA20:</div><div class='add'>+		/* This is not fatal.  We only need the discovery</div><div class='add'>+		 * binary for sysfs.  We don't need it for a</div><div class='add'>+		 * functional system.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_discovery_init(adev);</div><div class='ctx'> 		vega20_reg_base_init(adev);</div><div class='ctx'> 		adev-&gt;sdma.num_instances = 2;</div><div class='add'>+		adev-&gt;sdma.sdma_mask = 3;</div><div class='ctx'> 		adev-&gt;gmc.num_umc = 8;</div><div class='add'>+		adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 		adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);</div><div class='hunk'>@@ -2361,10 +2760,17 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_ARCTURUS:</div><div class='add'>+		/* This is not fatal.  We only need the discovery</div><div class='add'>+		 * binary for sysfs.  We don't need it for a</div><div class='add'>+		 * functional system.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_discovery_init(adev);</div><div class='ctx'> 		arct_reg_base_init(adev);</div><div class='ctx'> 		adev-&gt;sdma.num_instances = 8;</div><div class='add'>+		adev-&gt;sdma.sdma_mask = 0xff;</div><div class='ctx'> 		adev-&gt;vcn.num_vcn_inst = 2;</div><div class='ctx'> 		adev-&gt;gmc.num_umc = 8;</div><div class='add'>+		adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 		adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);</div><div class='ctx'> 		adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);</div><div class='ctx'> 		adev-&gt;ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);</div><div class='hunk'>@@ -2389,10 +2795,17 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_ALDEBARAN:</div><div class='add'>+		/* This is not fatal.  We only need the discovery</div><div class='add'>+		 * binary for sysfs.  We don't need it for a</div><div class='add'>+		 * functional system.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_discovery_init(adev);</div><div class='ctx'> 		aldebaran_reg_base_init(adev);</div><div class='ctx'> 		adev-&gt;sdma.num_instances = 5;</div><div class='add'>+		adev-&gt;sdma.sdma_mask = 0x1f;</div><div class='ctx'> 		adev-&gt;vcn.num_vcn_inst = 2;</div><div class='ctx'> 		adev-&gt;gmc.num_umc = 4;</div><div class='add'>+		adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 		adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);</div><div class='ctx'> 		adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);</div><div class='ctx'> 		adev-&gt;ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);</div><div class='hunk'>@@ -2414,10 +2827,44 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);</div><div class='ctx'> 		adev-&gt;ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);</div><div class='ctx'> 		break;</div><div class='add'>+	case CHIP_CYAN_SKILLFISH:</div><div class='add'>+		if (adev-&gt;apu_flags &amp; AMD_APU_IS_CYAN_SKILLFISH2) {</div><div class='add'>+			r = amdgpu_discovery_reg_base_init(adev);</div><div class='add'>+			if (r)</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			amdgpu_discovery_harvest_ip(adev);</div><div class='add'>+			amdgpu_discovery_get_gfx_info(adev);</div><div class='add'>+			amdgpu_discovery_get_mall_info(adev);</div><div class='add'>+			amdgpu_discovery_get_vcn_info(adev);</div><div class='add'>+		} else {</div><div class='add'>+			cyan_skillfish_reg_base_init(adev);</div><div class='add'>+			adev-&gt;sdma.num_instances = 2;</div><div class='add'>+			adev-&gt;sdma.sdma_mask = 3;</div><div class='add'>+			adev-&gt;gfx.xcc_mask = 1;</div><div class='add'>+			adev-&gt;ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3);</div><div class='add'>+			adev-&gt;ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3);</div><div class='add'>+			adev-&gt;ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1);</div><div class='add'>+			adev-&gt;ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1);</div><div class='add'>+			adev-&gt;ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1);</div><div class='add'>+			adev-&gt;ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1);</div><div class='add'>+			adev-&gt;ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0);</div><div class='add'>+			adev-&gt;ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1);</div><div class='add'>+			adev-&gt;ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1);</div><div class='add'>+			adev-&gt;ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8);</div><div class='add'>+			adev-&gt;ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8);</div><div class='add'>+			adev-&gt;ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1);</div><div class='add'>+			adev-&gt;ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8);</div><div class='add'>+			adev-&gt;ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3);</div><div class='add'>+			adev-&gt;ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		r = amdgpu_discovery_reg_base_init(adev);</div><div class='del'>-		if (r)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+		if (r) {</div><div class='add'>+			drm_err(&amp;adev-&gt;ddev, "discovery failed: %d\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_discovery_harvest_ip(adev);</div><div class='ctx'> 		amdgpu_discovery_get_gfx_info(adev);</div><div class='hunk'>@@ -2436,6 +2883,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(9, 4, 1):</div><div class='ctx'> 	case IP_VERSION(9, 4, 2):</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		adev-&gt;family = AMDGPU_FAMILY_AI;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 1, 0):</div><div class='hunk'>@@ -2478,8 +2927,14 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		adev-&gt;family = AMDGPU_FAMILY_GC_11_5_0;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		adev-&gt;family = AMDGPU_FAMILY_GC_12_0_0;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2498,18 +2953,14 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		adev-&gt;flags |= AMD_IS_APU;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(4, 8, 0))</div><div class='del'>-		adev-&gt;gmc.xgmi.supported = true;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='del'>-		adev-&gt;ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 4, 0);</div><div class='del'>-</div><div class='ctx'> 	/* set NBIO version */</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 1, 0):</div><div class='hunk'>@@ -2530,11 +2981,14 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;nbio.hdp_flush_reg = &amp;nbio_v7_4_hdp_flush_reg;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(7, 9, 0):</div><div class='add'>+	case IP_VERSION(7, 9, 1):</div><div class='ctx'> 		adev-&gt;nbio.funcs = &amp;nbio_v7_9_funcs;</div><div class='ctx'> 		adev-&gt;nbio.hdp_flush_reg = &amp;nbio_v7_9_hdp_flush_reg;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(7, 11, 0):</div><div class='ctx'> 	case IP_VERSION(7, 11, 1):</div><div class='add'>+	case IP_VERSION(7, 11, 2):</div><div class='add'>+	case IP_VERSION(7, 11, 3):</div><div class='ctx'> 		adev-&gt;nbio.funcs = &amp;nbio_v7_11_funcs;</div><div class='ctx'> 		adev-&gt;nbio.hdp_flush_reg = &amp;nbio_v7_11_hdp_flush_reg;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -2588,6 +3042,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(4, 2, 1):</div><div class='ctx'> 	case IP_VERSION(4, 4, 0):</div><div class='ctx'> 	case IP_VERSION(4, 4, 2):</div><div class='add'>+	case IP_VERSION(4, 4, 5):</div><div class='ctx'> 		adev-&gt;hdp.funcs = &amp;hdp_v4_0_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(5, 0, 0):</div><div class='hunk'>@@ -2632,6 +3087,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(4, 6, 2):</div><div class='ctx'> 		adev-&gt;df.funcs = &amp;df_v4_6_2_funcs;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(4, 15, 0):</div><div class='add'>+	case IP_VERSION(4, 15, 1):</div><div class='add'>+		adev-&gt;df.funcs = &amp;df_v4_15_funcs;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2656,6 +3115,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 10):</div><div class='ctx'> 	case IP_VERSION(11, 0, 11):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='ctx'> 	case IP_VERSION(13, 0, 1):</div><div class='ctx'> 	case IP_VERSION(13, 0, 9):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='hunk'>@@ -2665,6 +3125,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;smuio.funcs = &amp;smuio_v13_0_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(13, 0, 3):</div><div class='add'>+	case IP_VERSION(13, 0, 11):</div><div class='ctx'> 		adev-&gt;smuio.funcs = &amp;smuio_v13_0_3_funcs;</div><div class='ctx'> 		if (adev-&gt;smuio.funcs-&gt;get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {</div><div class='ctx'> 			adev-&gt;flags |= AMD_IS_APU;</div><div class='hunk'>@@ -2676,6 +3137,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(14, 0, 1):</div><div class='ctx'> 		adev-&gt;smuio.funcs = &amp;smuio_v13_0_6_funcs;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(14, 0, 2):</div><div class='add'>+		adev-&gt;smuio.funcs = &amp;smuio_v14_0_2_funcs;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2741,6 +3205,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_discovery_set_ras_ip_blocks(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	if ((adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT &amp;&amp;</div><div class='ctx'> 	     !amdgpu_sriov_vf(adev)) ||</div><div class='ctx'> 	    (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO &amp;&amp; amdgpu_dpm == 1)) {</div><div class='hunk'>@@ -2765,6 +3233,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_discovery_set_isp_ip_blocks(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h<br/>index 4d03cd5b3410..4ce04486cc31 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h</a></div><div class='hunk'>@@ -24,10 +24,27 @@</div><div class='ctx'> #ifndef __AMDGPU_DISCOVERY__</div><div class='ctx'> #define __AMDGPU_DISCOVERY__</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+</div><div class='ctx'> #define DISCOVERY_TMR_SIZE      (10 &lt;&lt; 10)</div><div class='ctx'> #define DISCOVERY_TMR_OFFSET    (64 &lt;&lt; 10)</div><div class='ctx'> </div><div class='add'>+struct ip_discovery_top;</div><div class='add'>+</div><div class='add'>+struct amdgpu_discovery_info {</div><div class='add'>+	struct debugfs_blob_wrapper debugfs_blob;</div><div class='add'>+	struct ip_discovery_top *ip_top;</div><div class='add'>+	uint32_t size;</div><div class='add'>+	uint8_t *bin;</div><div class='add'>+	bool reserve_tmr;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> void amdgpu_discovery_fini(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,</div><div class='add'>+				  uint32_t *nps_type,</div><div class='add'>+				  struct amdgpu_gmc_memrange **ranges,</div><div class='add'>+				  int *range_cnt, bool refresh);</div><div class='add'>+</div><div class='ctx'> #endif /* __AMDGPU_DISCOVERY__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c<br/>index 3ecc7ef95172..b5d34797d606 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #include "soc15_common.h"</div><div class='ctx'> #include "gc/gc_11_0_0_offset.h"</div><div class='ctx'> #include "gc/gc_11_0_0_sh_mask.h"</div><div class='add'>+#include "bif/bif_4_1_d.h"</div><div class='ctx'> #include &lt;asm/div64.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='hunk'>@@ -233,6 +234,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;enable_virtual_display) {</div><div class='add'>+		new_abo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 		r = amdgpu_bo_pin(new_abo,</div><div class='ctx'> 				  amdgpu_display_supported_domains(adev, new_abo-&gt;flags));</div><div class='ctx'> 		if (unlikely(r != 0)) {</div><div class='hunk'>@@ -330,8 +332,6 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set,</div><div class='ctx'> 		if (crtc-&gt;enabled)</div><div class='ctx'> 			active = true;</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='del'>-</div><div class='ctx'> 	adev = drm_to_adev(dev);</div><div class='ctx'> 	/* if we have active crtcs and we don't have a power ref,</div><div class='ctx'> 	 * take the current one</div><div class='hunk'>@@ -654,6 +654,10 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier)</div><div class='ctx'> 	if (!IS_AMD_FMT_MOD(modifier))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) &lt; AMD_FMT_MOD_TILE_VER_GFX9 ||</div><div class='add'>+	    AMD_FMT_MOD_GET(TILE_VERSION, modifier) &gt;= AMD_FMT_MOD_TILE_VER_GFX12)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))</div><div class='ctx'> 		return lookup_format_info(dcc_retile_formats,</div><div class='ctx'> 					  ARRAY_SIZE(dcc_retile_formats),</div><div class='hunk'>@@ -718,6 +722,30 @@ extract_render_dcc_offset(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)</div><div class='add'>+{</div><div class='add'>+	u64 modifier = 0;</div><div class='add'>+	int swizzle_mode = AMDGPU_TILING_GET(afb-&gt;tiling_flags, GFX12_SWIZZLE_MODE);</div><div class='add'>+</div><div class='add'>+	if (!swizzle_mode) {</div><div class='add'>+		modifier = DRM_FORMAT_MOD_LINEAR;</div><div class='add'>+	} else {</div><div class='add'>+		int max_comp_block =</div><div class='add'>+			AMDGPU_TILING_GET(afb-&gt;tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);</div><div class='add'>+</div><div class='add'>+		modifier =</div><div class='add'>+			AMD_FMT_MOD |</div><div class='add'>+			AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |</div><div class='add'>+			AMD_FMT_MOD_SET(TILE, swizzle_mode) |</div><div class='add'>+			AMD_FMT_MOD_SET(DCC, afb-&gt;gfx12_dcc) |</div><div class='add'>+			AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	afb-&gt;base.modifier = modifier;</div><div class='add'>+	afb-&gt;base.flags |= DRM_MODE_FB_MODIFIERS;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(afb-&gt;base.dev);</div><div class='hunk'>@@ -917,8 +945,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)</div><div class='ctx'> {</div><div class='ctx'> 	u64 micro_tile_mode;</div><div class='ctx'> </div><div class='del'>-	/* Zero swizzle mode means linear */</div><div class='del'>-	if (AMDGPU_TILING_GET(afb-&gt;tiling_flags, SWIZZLE_MODE) == 0)</div><div class='add'>+	if (AMDGPU_TILING_GET(afb-&gt;tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	micro_tile_mode = AMDGPU_TILING_GET(afb-&gt;tiling_flags, MICRO_TILE_MODE);</div><div class='hunk'>@@ -1042,6 +1069,30 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)</div><div class='ctx'> 			block_width = 256 / format_info-&gt;cpp[i];</div><div class='ctx'> 			block_height = 1;</div><div class='ctx'> 			block_size_log2 = 8;</div><div class='add'>+		} else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) &gt;= AMD_FMT_MOD_TILE_VER_GFX12) {</div><div class='add'>+			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);</div><div class='add'>+</div><div class='add'>+			switch (swizzle) {</div><div class='add'>+			case AMD_FMT_MOD_TILE_GFX12_256B_2D:</div><div class='add'>+				block_size_log2 = 8;</div><div class='add'>+				break;</div><div class='add'>+			case AMD_FMT_MOD_TILE_GFX12_4K_2D:</div><div class='add'>+				block_size_log2 = 12;</div><div class='add'>+				break;</div><div class='add'>+			case AMD_FMT_MOD_TILE_GFX12_64K_2D:</div><div class='add'>+				block_size_log2 = 16;</div><div class='add'>+				break;</div><div class='add'>+			case AMD_FMT_MOD_TILE_GFX12_256K_2D:</div><div class='add'>+				block_size_log2 = 18;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				drm_dbg_kms(rfb-&gt;base.dev,</div><div class='add'>+					    "Gfx12 swizzle mode with unknown block size: %d\n", swizzle);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			get_block_dimensions(block_size_log2, format_info-&gt;cpp[i],</div><div class='add'>+					     &amp;block_width, &amp;block_height);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);</div><div class='ctx'> </div><div class='hunk'>@@ -1077,7 +1128,8 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (AMD_FMT_MOD_GET(DCC, modifier)) {</div><div class='add'>+	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) &lt;= AMD_FMT_MOD_TILE_VER_GFX11 &amp;&amp;</div><div class='add'>+	    AMD_FMT_MOD_GET(DCC, modifier)) {</div><div class='ctx'> 		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {</div><div class='ctx'> 			block_size_log2 = get_dcc_block_size(modifier, false, false);</div><div class='ctx'> 			get_block_dimensions(block_size_log2 + 8, format_info-&gt;cpp[0],</div><div class='hunk'>@@ -1107,7 +1159,8 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,</div><div class='del'>-				      uint64_t *tiling_flags, bool *tmz_surface)</div><div class='add'>+				      uint64_t *tiling_flags, bool *tmz_surface,</div><div class='add'>+				      bool *gfx12_dcc)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo *rbo;</div><div class='ctx'> 	int r;</div><div class='hunk'>@@ -1115,6 +1168,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb</div><div class='ctx'> 	if (!amdgpu_fb) {</div><div class='ctx'> 		*tiling_flags = 0;</div><div class='ctx'> 		*tmz_surface = false;</div><div class='add'>+		*gfx12_dcc = false;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1128,11 +1182,9 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (tiling_flags)</div><div class='del'>-		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);</div><div class='del'>-</div><div class='del'>-	if (tmz_surface)</div><div class='del'>-		*tmz_surface = amdgpu_bo_encrypted(rbo);</div><div class='add'>+	amdgpu_bo_get_tiling_flags(rbo, tiling_flags);</div><div class='add'>+	*tmz_surface = amdgpu_bo_encrypted(rbo);</div><div class='add'>+	*gfx12_dcc = rbo-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_unreserve(rbo);</div><div class='ctx'> </div><div class='hunk'>@@ -1142,13 +1194,14 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb</div><div class='ctx'> static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,</div><div class='ctx'> 						 struct amdgpu_framebuffer *rfb,</div><div class='ctx'> 						 struct drm_file *file_priv,</div><div class='add'>+						 const struct drm_format_info *info,</div><div class='ctx'> 						 const struct drm_mode_fb_cmd2 *mode_cmd,</div><div class='ctx'> 						 struct drm_gem_object *obj)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	rfb-&gt;base.obj[0] = obj;</div><div class='del'>-	drm_helper_mode_fill_fb_struct(dev, &amp;rfb-&gt;base, mode_cmd);</div><div class='add'>+	drm_helper_mode_fill_fb_struct(dev, &amp;rfb-&gt;base, info, mode_cmd);</div><div class='ctx'> 	/* Verify that the modifier is supported. */</div><div class='ctx'> 	if (!drm_any_plane_has_format(dev, mode_cmd-&gt;pixel_format,</div><div class='ctx'> 				      mode_cmd-&gt;modifier[0])) {</div><div class='hunk'>@@ -1201,7 +1254,8 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_display_get_fb_info(rfb, &amp;rfb-&gt;tiling_flags, &amp;rfb-&gt;tmz_surface);</div><div class='add'>+	ret = amdgpu_display_get_fb_info(rfb, &amp;rfb-&gt;tiling_flags, &amp;rfb-&gt;tmz_surface,</div><div class='add'>+					 &amp;rfb-&gt;gfx12_dcc);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1215,7 +1269,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	if (!dev-&gt;mode_config.fb_modifiers_not_supported &amp;&amp;</div><div class='ctx'> 	    !(rfb-&gt;base.flags &amp; DRM_MODE_FB_MODIFIERS)) {</div><div class='del'>-		ret = convert_tiling_flags_to_modifier(rfb);</div><div class='add'>+		if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0))</div><div class='add'>+			ret = convert_tiling_flags_to_modifier_gfx12(rfb);</div><div class='add'>+		else</div><div class='add'>+			ret = convert_tiling_flags_to_modifier(rfb);</div><div class='add'>+</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",</div><div class='ctx'> 				    rfb-&gt;tiling_flags);</div><div class='hunk'>@@ -1238,6 +1296,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev,</div><div class='ctx'> struct drm_framebuffer *</div><div class='ctx'> amdgpu_display_user_framebuffer_create(struct drm_device *dev,</div><div class='ctx'> 				       struct drm_file *file_priv,</div><div class='add'>+				       const struct drm_format_info *info,</div><div class='ctx'> 				       const struct drm_mode_fb_cmd2 *mode_cmd)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_framebuffer *amdgpu_fb;</div><div class='hunk'>@@ -1258,7 +1317,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,</div><div class='ctx'> 	/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */</div><div class='ctx'> 	bo = gem_to_amdgpu_bo(obj);</div><div class='ctx'> 	domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo-&gt;flags);</div><div class='del'>-	if (obj-&gt;import_attach &amp;&amp; !(domains &amp; AMDGPU_GEM_DOMAIN_GTT)) {</div><div class='add'>+	if (drm_gem_is_imported(obj) &amp;&amp; !(domains &amp; AMDGPU_GEM_DOMAIN_GTT)) {</div><div class='ctx'> 		drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");</div><div class='ctx'> 		drm_gem_object_put(obj);</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='hunk'>@@ -1271,7 +1330,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,</div><div class='del'>-						    mode_cmd, obj);</div><div class='add'>+						    info, mode_cmd, obj);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		kfree(amdgpu_fb);</div><div class='ctx'> 		drm_gem_object_put(obj);</div><div class='hunk'>@@ -1304,6 +1363,64 @@ static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = {</div><div class='ctx'> 	{ AMDGPU_FMT_DITHER_ENABLE, "on" },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * DOC: property for adaptive backlight modulation</div><div class='add'>+ *</div><div class='add'>+ * The 'adaptive backlight modulation' property is used for the compositor to</div><div class='add'>+ * directly control the adaptive backlight modulation power savings feature</div><div class='add'>+ * that is part of DCN hardware.</div><div class='add'>+ *</div><div class='add'>+ * The property will be attached specifically to eDP panels that support it.</div><div class='add'>+ *</div><div class='add'>+ * The property is by default set to 'sysfs' to allow the sysfs file 'panel_power_savings'</div><div class='add'>+ * to be able to control it.</div><div class='add'>+ * If set to 'off' the compositor will ensure it stays off.</div><div class='add'>+ * The other values 'min', 'bias min', 'bias max', and 'max' will control the</div><div class='add'>+ * intensity of the power savings.</div><div class='add'>+ *</div><div class='add'>+ * Modifying this value can have implications on color accuracy, so tread</div><div class='add'>+ * carefully.</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_display_setup_abm_prop(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct drm_prop_enum_list props[] = {</div><div class='add'>+		{ ABM_SYSFS_CONTROL, "sysfs" },</div><div class='add'>+		{ ABM_LEVEL_OFF, "off" },</div><div class='add'>+		{ ABM_LEVEL_MIN, "min" },</div><div class='add'>+		{ ABM_LEVEL_BIAS_MIN, "bias min" },</div><div class='add'>+		{ ABM_LEVEL_BIAS_MAX, "bias max" },</div><div class='add'>+		{ ABM_LEVEL_MAX, "max" },</div><div class='add'>+	};</div><div class='add'>+	struct drm_property *prop;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;dc_enabled)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_ENUM,</div><div class='add'>+				"adaptive backlight modulation",</div><div class='add'>+				6);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(props); i++) {</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		ret = drm_property_add_enum(prop, props[i].type,</div><div class='add'>+						props[i].name);</div><div class='add'>+</div><div class='add'>+		if (ret) {</div><div class='add'>+			drm_property_destroy(adev_to_drm(adev), prop);</div><div class='add'>+</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;mode_info.abm_level_property = prop;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int sz;</div><div class='hunk'>@@ -1350,7 +1467,7 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)</div><div class='ctx'> 					 "dither",</div><div class='ctx'> 					 amdgpu_dither_enum_list, sz);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return amdgpu_display_setup_abm_prop(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_display_update_priority(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1417,7 +1534,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,</div><div class='ctx'> 		if ((!(mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE)) &amp;&amp;</div><div class='ctx'> 		    ((amdgpu_encoder-&gt;underscan_type == UNDERSCAN_ON) ||</div><div class='ctx'> 		     ((amdgpu_encoder-&gt;underscan_type == UNDERSCAN_AUTO) &amp;&amp;</div><div class='del'>-		      connector-&gt;display_info.is_hdmi &amp;&amp;</div><div class='add'>+		      connector &amp;&amp; connector-&gt;display_info.is_hdmi &amp;&amp;</div><div class='ctx'> 		      amdgpu_display_is_hdtv_mode(mode)))) {</div><div class='ctx'> 			if (amdgpu_encoder-&gt;underscan_hborder != 0)</div><div class='ctx'> 				amdgpu_crtc-&gt;h_border = amdgpu_encoder-&gt;underscan_hborder;</div><div class='hunk'>@@ -1702,6 +1819,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_bo_reserve(aobj, true);</div><div class='ctx'> 			if (r == 0) {</div><div class='add'>+				aobj-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 				r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 				if (r != 0)</div><div class='ctx'> 					dev_err(adev-&gt;dev, "Failed to pin cursor BO (%d)\n", r);</div><div class='hunk'>@@ -1729,3 +1847,82 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used in amdgpu_dm_set_pixel()</div><div class='add'>+ * they are called from the panic handler, and protected by the drm_panic spinlock.</div><div class='add'>+ */</div><div class='add'>+static struct amdgpu_bo *panic_abo;</div><div class='add'>+</div><div class='add'>+/* Use the indirect MMIO to write each pixel to the GPU VRAM,</div><div class='add'>+ * This is a simplified version of amdgpu_device_mm_access()</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_display_set_pixel(struct drm_scanout_buffer *sb,</div><div class='add'>+				     unsigned int x,</div><div class='add'>+				     unsigned int y,</div><div class='add'>+				     u32 color)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_res_cursor cursor;</div><div class='add'>+	unsigned long offset;</div><div class='add'>+	struct amdgpu_bo *abo = panic_abo;</div><div class='add'>+	struct amdgpu_device *adev = amdgpu_ttm_adev(abo-&gt;tbo.bdev);</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	offset = x * 4 + y * sb-&gt;pitch[0];</div><div class='add'>+	amdgpu_res_first(abo-&gt;tbo.resource, offset, 4, &amp;cursor);</div><div class='add'>+</div><div class='add'>+	tmp = cursor.start &gt;&gt; 31;</div><div class='add'>+	WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t) cursor.start) | 0x80000000);</div><div class='add'>+	if (tmp != 0xffffffff)</div><div class='add'>+		WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);</div><div class='add'>+	WREG32_NO_KIQ(mmMM_DATA, color);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_display_get_scanout_buffer(struct drm_plane *plane,</div><div class='add'>+				      struct drm_scanout_buffer *sb)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo *abo;</div><div class='add'>+	struct drm_framebuffer *fb = plane-&gt;state-&gt;fb;</div><div class='add'>+</div><div class='add'>+	if (!fb)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG_KMS("Framebuffer %dx%d %p4cc\n", fb-&gt;width, fb-&gt;height, &amp;fb-&gt;format-&gt;format);</div><div class='add'>+</div><div class='add'>+	abo = gem_to_amdgpu_bo(fb-&gt;obj[0]);</div><div class='add'>+	if (!abo)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	sb-&gt;width = fb-&gt;width;</div><div class='add'>+	sb-&gt;height = fb-&gt;height;</div><div class='add'>+	/* Use the generic linear format, because tiling will be disabled in panic_flush() */</div><div class='add'>+	sb-&gt;format = drm_format_info(fb-&gt;format-&gt;format);</div><div class='add'>+	if (!sb-&gt;format)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	sb-&gt;pitch[0] = fb-&gt;pitches[0];</div><div class='add'>+</div><div class='add'>+	if (abo-&gt;flags &amp; AMDGPU_GEM_CREATE_NO_CPU_ACCESS) {</div><div class='add'>+		if (abo-&gt;tbo.resource-&gt;mem_type != TTM_PL_VRAM) {</div><div class='add'>+			drm_warn(plane-&gt;dev, "amdgpu panic, framebuffer not in VRAM\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		/* Only handle 32bits format, to simplify mmio access */</div><div class='add'>+		if (fb-&gt;format-&gt;cpp[0] != 4) {</div><div class='add'>+			drm_warn(plane-&gt;dev, "amdgpu panic, pixel format is not 32bits\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		sb-&gt;set_pixel = amdgpu_display_set_pixel;</div><div class='add'>+		panic_abo = abo;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	if (!abo-&gt;kmap.virtual &amp;&amp;</div><div class='add'>+	    ttm_bo_kmap(&amp;abo-&gt;tbo, 0, PFN_UP(abo-&gt;tbo.base.size), &amp;abo-&gt;kmap)) {</div><div class='add'>+		drm_warn(plane-&gt;dev, "amdgpu bo map failed, panic won't be displayed\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	if (abo-&gt;kmap.bo_kmap_type &amp; TTM_BO_MAP_IOMEM_MASK)</div><div class='add'>+		iosys_map_set_vaddr_iomem(&amp;sb-&gt;map[0], abo-&gt;kmap.virtual);</div><div class='add'>+	else</div><div class='add'>+		iosys_map_set_vaddr(&amp;sb-&gt;map[0], abo-&gt;kmap.virtual);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h<br/>index 9d19940f73c8..49a29bf47a37 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.h</a></div><div class='hunk'>@@ -23,6 +23,8 @@</div><div class='ctx'> #ifndef __AMDGPU_DISPLAY_H__</div><div class='ctx'> #define __AMDGPU_DISPLAY_H__</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_panic.h&gt;</div><div class='add'>+</div><div class='ctx'> #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)-&gt;mode_info.funcs-&gt;vblank_get_counter((adev), (crtc))</div><div class='ctx'> #define amdgpu_display_backlight_set_level(adev, e, l) (adev)-&gt;mode_info.funcs-&gt;backlight_set_level((e), (l))</div><div class='ctx'> #define amdgpu_display_backlight_get_level(adev, e) (adev)-&gt;mode_info.funcs-&gt;backlight_get_level((e))</div><div class='hunk'>@@ -42,6 +44,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,</div><div class='ctx'> struct drm_framebuffer *</div><div class='ctx'> amdgpu_display_user_framebuffer_create(struct drm_device *dev,</div><div class='ctx'> 				       struct drm_file *file_priv,</div><div class='add'>+				       const struct drm_format_info *info,</div><div class='ctx'> 				       const struct drm_mode_fb_cmd2 *mode_cmd);</div><div class='ctx'> const struct drm_format_info *</div><div class='ctx'> amdgpu_lookup_format_info(u32 format, uint64_t modifier);</div><div class='hunk'>@@ -49,4 +52,14 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier);</div><div class='ctx'> int amdgpu_display_suspend_helper(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_display_resume_helper(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+int amdgpu_display_get_scanout_buffer(struct drm_plane *plane,</div><div class='add'>+				      struct drm_scanout_buffer *sb);</div><div class='add'>+</div><div class='add'>+#define ABM_SYSFS_CONTROL	-1</div><div class='add'>+#define ABM_LEVEL_OFF		0</div><div class='add'>+#define ABM_LEVEL_MIN		1</div><div class='add'>+#define ABM_LEVEL_BIAS_MIN	2</div><div class='add'>+#define ABM_LEVEL_BIAS_MAX	3</div><div class='add'>+#define ABM_LEVEL_MAX		4</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c<br/>index 055ba2ea4c12..e22cfa7c6d32 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c</a></div><div class='hunk'>@@ -36,13 +36,35 @@</div><div class='ctx'> #include "amdgpu_gem.h"</div><div class='ctx'> #include "amdgpu_dma_buf.h"</div><div class='ctx'> #include "amdgpu_xgmi.h"</div><div class='add'>+#include "amdgpu_vm.h"</div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='ctx'> #include &lt;linux/dma-buf.h&gt;</div><div class='ctx'> #include &lt;linux/dma-fence-array.h&gt;</div><div class='ctx'> #include &lt;linux/pci-p2pdma.h&gt;</div><div class='del'>-#include &lt;linux/pm_runtime.h&gt;</div><div class='del'>-#include "amdgpu_trace.h"</div><div class='add'>+</div><div class='add'>+static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dma_buf_attach_adev - Helper to get adev of an attachment</div><div class='add'>+ *</div><div class='add'>+ * @attach: attachment</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * A struct amdgpu_device * if the attaching device is an amdgpu device or</div><div class='add'>+ * partition, NULL otherwise.</div><div class='add'>+ */</div><div class='add'>+static struct amdgpu_device *dma_buf_attach_adev(struct dma_buf_attachment *attach)</div><div class='add'>+{</div><div class='add'>+	if (attach-&gt;importer_ops == &amp;amdgpu_dma_buf_attach_ops) {</div><div class='add'>+		struct drm_gem_object *obj = attach-&gt;importer_priv;</div><div class='add'>+		struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='add'>+</div><div class='add'>+		return amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dma_buf_attach - &amp;dma_buf_ops.attach implementation</div><div class='hunk'>@@ -55,45 +77,49 @@</div><div class='ctx'> static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,</div><div class='ctx'> 				 struct dma_buf_attachment *attach)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *attach_adev = dma_buf_attach_adev(attach);</div><div class='ctx'> 	struct drm_gem_object *obj = dmabuf-&gt;priv;</div><div class='ctx'> 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (pci_p2pdma_distance(adev-&gt;pdev, attach-&gt;dev, false) &lt; 0)</div><div class='add'>+	/*</div><div class='add'>+	 * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.</div><div class='add'>+	 * Such buffers cannot be safely accessed over P2P due to device-local</div><div class='add'>+	 * compression metadata. Fallback to system-memory path instead.</div><div class='add'>+	 * Device supports GFX12 (GC 12.x or newer)</div><div class='add'>+	 * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0) &amp;&amp;</div><div class='add'>+	    bo-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC)</div><div class='ctx'> 		attach-&gt;peer2peer = false;</div><div class='ctx'> </div><div class='del'>-	r = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='del'>-	trace_amdgpu_runpm_reference_dumps(1, __func__);</div><div class='del'>-	if (r &lt; 0)</div><div class='del'>-		goto out;</div><div class='add'>+	/*</div><div class='add'>+	 * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.</div><div class='add'>+	 * Such buffers cannot be safely accessed over P2P due to device-local</div><div class='add'>+	 * compression metadata. Fallback to system-memory path instead.</div><div class='add'>+	 * Device supports GFX12 (GC 12.x or newer)</div><div class='add'>+	 * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0) &amp;&amp;</div><div class='add'>+	    bo-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC)</div><div class='add'>+		attach-&gt;peer2peer = false;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &amp;&amp;</div><div class='add'>+	    pci_p2pdma_distance(adev-&gt;pdev, attach-&gt;dev, false) &lt; 0)</div><div class='add'>+		attach-&gt;peer2peer = false;</div><div class='ctx'> </div><div class='del'>-out:</div><div class='del'>-	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='del'>-	trace_amdgpu_runpm_reference_dumps(0, __func__);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='add'>+	r = dma_resv_lock(bo-&gt;tbo.base.resv, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_dma_buf_detach - &amp;dma_buf_ops.detach implementation</div><div class='del'>- *</div><div class='del'>- * @dmabuf: DMA-buf where we remove the attachment from</div><div class='del'>- * @attach: the attachment to remove</div><div class='del'>- *</div><div class='del'>- * Called when an attachment is removed from the DMA-buf.</div><div class='del'>- */</div><div class='del'>-static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,</div><div class='del'>-				  struct dma_buf_attachment *attach)</div><div class='del'>-{</div><div class='del'>-	struct drm_gem_object *obj = dmabuf-&gt;priv;</div><div class='del'>-	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='del'>-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='add'>+	amdgpu_vm_bo_update_shared(bo);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='del'>-	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='del'>-	trace_amdgpu_runpm_reference_dumps(0, __func__);</div><div class='add'>+	dma_resv_unlock(bo-&gt;tbo.base.resv);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -105,11 +131,35 @@ static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)</div><div class='ctx'> {</div><div class='del'>-	struct drm_gem_object *obj = attach-&gt;dmabuf-&gt;priv;</div><div class='del'>-	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='add'>+	struct dma_buf *dmabuf = attach-&gt;dmabuf;</div><div class='add'>+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf-&gt;priv);</div><div class='add'>+	u32 domains = bo-&gt;allowed_domains;</div><div class='add'>+</div><div class='add'>+	dma_resv_assert_held(dmabuf-&gt;resv);</div><div class='add'>+</div><div class='add'>+	/* Try pinning into VRAM to allow P2P with RDMA NICs without ODP</div><div class='add'>+	 * support if all attachments can do P2P. If any attachment can't do</div><div class='add'>+	 * P2P just pin into GTT instead.</div><div class='add'>+	 *</div><div class='add'>+	 * To avoid with conflicting pinnings between GPUs and RDMA when move</div><div class='add'>+	 * notifiers are disabled, only allow pinning in VRAM when move</div><div class='add'>+	 * notiers are enabled.</div><div class='add'>+	 */</div><div class='add'>+	if (!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY)) {</div><div class='add'>+		domains &amp;= ~AMDGPU_GEM_DOMAIN_VRAM;</div><div class='add'>+	} else {</div><div class='add'>+		list_for_each_entry(attach, &amp;dmabuf-&gt;attachments, node)</div><div class='add'>+			if (!attach-&gt;peer2peer)</div><div class='add'>+				domains &amp;= ~AMDGPU_GEM_DOMAIN_VRAM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (domains &amp; AMDGPU_GEM_DOMAIN_VRAM)</div><div class='add'>+		bo-&gt;flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!domains))</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	/* pin buffer into GTT */</div><div class='del'>-	return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);</div><div class='add'>+	return amdgpu_bo_pin(bo, domains);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -164,10 +214,6 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,</div><div class='ctx'> 		r = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return ERR_PTR(r);</div><div class='del'>-</div><div class='del'>-	} else if (!(amdgpu_mem_type_to_domain(bo-&gt;tbo.resource-&gt;mem_type) &amp;</div><div class='del'>-		     AMDGPU_GEM_DOMAIN_GTT)) {</div><div class='del'>-		return ERR_PTR(-EBUSY);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (bo-&gt;tbo.resource-&gt;mem_type) {</div><div class='hunk'>@@ -184,6 +230,11 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case TTM_PL_VRAM:</div><div class='add'>+		/* XGMI-accessible memory should never be DMA-mapped */</div><div class='add'>+		if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible(</div><div class='add'>+				dma_buf_attach_adev(attach), bo)))</div><div class='add'>+			return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='ctx'> 		r = amdgpu_vram_mgr_alloc_sgt(adev, bo-&gt;tbo.resource, 0,</div><div class='ctx'> 					      bo-&gt;tbo.base.size, attach-&gt;dev,</div><div class='ctx'> 					      dir, &amp;sgt);</div><div class='hunk'>@@ -215,7 +266,7 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,</div><div class='ctx'> 				 struct sg_table *sgt,</div><div class='ctx'> 				 enum dma_data_direction dir)</div><div class='ctx'> {</div><div class='del'>-	if (sgt-&gt;sgl-&gt;page_link) {</div><div class='add'>+	if (sg_page(sgt-&gt;sgl)) {</div><div class='ctx'> 		dma_unmap_sgtable(attach-&gt;dev, sgt, dir, 0);</div><div class='ctx'> 		sg_free_table(sgt);</div><div class='ctx'> 		kfree(sgt);</div><div class='hunk'>@@ -265,9 +316,38 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = dma_buf-&gt;priv;</div><div class='add'>+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Pin to keep buffer in place while it's vmap'ed. The actual</div><div class='add'>+	 * domain is not that important as long as it's mapable. Using</div><div class='add'>+	 * GTT and VRAM should be compatible with most use cases.</div><div class='add'>+	 */</div><div class='add'>+	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = drm_gem_dmabuf_vmap(dma_buf, map);</div><div class='add'>+	if (ret)</div><div class='add'>+		amdgpu_bo_unpin(bo);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = dma_buf-&gt;priv;</div><div class='add'>+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='add'>+</div><div class='add'>+	drm_gem_dmabuf_vunmap(dma_buf, map);</div><div class='add'>+	amdgpu_bo_unpin(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct dma_buf_ops amdgpu_dmabuf_ops = {</div><div class='ctx'> 	.attach = amdgpu_dma_buf_attach,</div><div class='del'>-	.detach = amdgpu_dma_buf_detach,</div><div class='ctx'> 	.pin = amdgpu_dma_buf_pin,</div><div class='ctx'> 	.unpin = amdgpu_dma_buf_unpin,</div><div class='ctx'> 	.map_dma_buf = amdgpu_dma_buf_map,</div><div class='hunk'>@@ -275,8 +355,8 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = {</div><div class='ctx'> 	.release = drm_gem_dmabuf_release,</div><div class='ctx'> 	.begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,</div><div class='ctx'> 	.mmap = drm_gem_dmabuf_mmap,</div><div class='del'>-	.vmap = drm_gem_dmabuf_vmap,</div><div class='del'>-	.vunmap = drm_gem_dmabuf_vunmap,</div><div class='add'>+	.vmap = amdgpu_dma_buf_vmap,</div><div class='add'>+	.vunmap = amdgpu_dma_buf_vunmap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -294,11 +374,23 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);</div><div class='ctx'> 	struct dma_buf *buf;</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = true,</div><div class='add'>+		.no_wait_gpu = true,</div><div class='add'>+		/* We opt to avoid OOM on system pages allocations */</div><div class='add'>+		.gfp_retry_mayfail = true,</div><div class='add'>+		.allow_res_evict = false,</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ttm_tt_get_usermm(bo-&gt;tbo.ttm) ||</div><div class='ctx'> 	    bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)</div><div class='ctx'> 		return ERR_PTR(-EPERM);</div><div class='ctx'> </div><div class='add'>+	ret = ttm_bo_setup_export(&amp;bo-&gt;tbo, &amp;ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+</div><div class='ctx'> 	buf = drm_gem_prime_export(gobj, flags);</div><div class='ctx'> 	if (!IS_ERR(buf))</div><div class='ctx'> 		buf-&gt;ops = &amp;amdgpu_dmabuf_ops;</div><div class='hunk'>@@ -380,7 +472,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)</div><div class='ctx'> 	/* FIXME: This should be after the "if", but needs a fix to make sure</div><div class='ctx'> 	 * DMABuf imports are initialized in the right VM list.</div><div class='ctx'> 	 */</div><div class='del'>-	amdgpu_vm_bo_invalidate(adev, bo, false);</div><div class='add'>+	amdgpu_vm_bo_invalidate(bo, false);</div><div class='ctx'> 	if (!bo-&gt;tbo.resource || bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_SYSTEM)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -491,7 +583,10 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,</div><div class='ctx'> 	struct drm_gem_object *obj = &amp;bo-&gt;tbo.base;</div><div class='ctx'> 	struct drm_gem_object *gobj;</div><div class='ctx'> </div><div class='del'>-	if (obj-&gt;import_attach) {</div><div class='add'>+	if (!adev)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (drm_gem_is_imported(obj)) {</div><div class='ctx'> 		struct dma_buf *dma_buf = obj-&gt;import_attach-&gt;dmabuf;</div><div class='ctx'> </div><div class='ctx'> 		if (dma_buf-&gt;ops != &amp;amdgpu_dmabuf_ops)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c<br/>index 3f3662e8b871..3040437d99c2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c</a></div><div class='hunk'>@@ -41,7 +41,8 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)</div><div class='ctx'> 	if (index &lt; adev-&gt;doorbell.num_kernel_doorbells)</div><div class='ctx'> 		return readl(adev-&gt;doorbell.cpu_addr + index);</div><div class='ctx'> </div><div class='del'>-	DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);</div><div class='add'>+	dev_err(adev-&gt;dev, "reading beyond doorbell aperture: 0x%08x!\n",</div><div class='add'>+		index);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -63,7 +64,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)</div><div class='ctx'> 	if (index &lt; adev-&gt;doorbell.num_kernel_doorbells)</div><div class='ctx'> 		writel(v, adev-&gt;doorbell.cpu_addr + index);</div><div class='ctx'> 	else</div><div class='del'>-		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"writing beyond doorbell aperture: 0x%08x!\n", index);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -83,7 +85,8 @@ u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)</div><div class='ctx'> 	if (index &lt; adev-&gt;doorbell.num_kernel_doorbells)</div><div class='ctx'> 		return atomic64_read((atomic64_t *)(adev-&gt;doorbell.cpu_addr + index));</div><div class='ctx'> </div><div class='del'>-	DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);</div><div class='add'>+	dev_err(adev-&gt;dev, "reading beyond doorbell aperture: 0x%08x!\n",</div><div class='add'>+		index);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -105,7 +108,8 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)</div><div class='ctx'> 	if (index &lt; adev-&gt;doorbell.num_kernel_doorbells)</div><div class='ctx'> 		atomic64_set((atomic64_t *)(adev-&gt;doorbell.cpu_addr + index), v);</div><div class='ctx'> 	else</div><div class='del'>-		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"writing beyond doorbell aperture: 0x%08x!\n", index);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -166,7 +170,8 @@ int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev)</div><div class='ctx'> 				    NULL,</div><div class='ctx'> 				    (void **)&amp;adev-&gt;doorbell.cpu_addr);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to allocate kernel doorbells, err=%d\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Failed to allocate kernel doorbells, err=%d\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c<br/>index 80b9642f2bc4..2dfbddcef9ab 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</a></div><div class='hunk'>@@ -23,8 +23,9 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='add'>+#include &lt;drm/clients/drm_client_setup.h&gt;</div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='del'>-#include &lt;drm/drm_fbdev_generic.h&gt;</div><div class='add'>+#include &lt;drm/drm_fbdev_ttm.h&gt;</div><div class='ctx'> #include &lt;drm/drm_gem.h&gt;</div><div class='ctx'> #include &lt;drm/drm_managed.h&gt;</div><div class='ctx'> #include &lt;drm/drm_pciids.h&gt;</div><div class='hunk'>@@ -50,6 +51,8 @@</div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='ctx'> #include "amdgpu_sched.h"</div><div class='ctx'> #include "amdgpu_xgmi.h"</div><div class='add'>+#include "amdgpu_userq.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='ctx'> #include "../amdxcp/amdgpu_xcp_drv.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -116,9 +119,16 @@</div><div class='ctx'>  * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query</div><div class='ctx'>  * - 3.56.0 - Update IB start address and size alignment for decode and encode</div><div class='ctx'>  * - 3.57.0 - Compute tunneling on GFX10+</div><div class='add'>+ * - 3.58.0 - Add GFX12 DCC support</div><div class='add'>+ * - 3.59.0 - Cleared VRAM</div><div class='add'>+ * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)</div><div class='add'>+ * - 3.61.0 - Contains fix for RV/PCO compute queues</div><div class='add'>+ * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF &amp; AMDGPU_IDS_FLAGS_MODE_PT</div><div class='add'>+ * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size</div><div class='add'>+ * - 3.64.0 - Userq IP support query</div><div class='ctx'>  */</div><div class='ctx'> #define KMS_DRIVER_MAJOR	3</div><div class='del'>-#define KMS_DRIVER_MINOR	57</div><div class='add'>+#define KMS_DRIVER_MINOR	64</div><div class='ctx'> #define KMS_DRIVER_PATCHLEVEL	0</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -129,6 +139,13 @@ enum AMDGPU_DEBUG_MASK {</div><div class='ctx'> 	AMDGPU_DEBUG_LARGEBAR = BIT(1),</div><div class='ctx'> 	AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),</div><div class='ctx'> 	AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),</div><div class='add'>+	AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),</div><div class='add'>+	AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),</div><div class='add'>+	AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),</div><div class='add'>+	AMDGPU_DEBUG_SMU_POOL = BIT(7),</div><div class='add'>+	AMDGPU_DEBUG_VM_USERPTR = BIT(8),</div><div class='add'>+	AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),</div><div class='add'>+	AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> unsigned int amdgpu_vram_limit = UINT_MAX;</div><div class='hunk'>@@ -165,7 +182,18 @@ uint amdgpu_pg_mask = 0xffffffff;</div><div class='ctx'> uint amdgpu_sdma_phase_quantum = 32;</div><div class='ctx'> char *amdgpu_disable_cu;</div><div class='ctx'> char *amdgpu_virtual_display;</div><div class='del'>-bool enforce_isolation;</div><div class='add'>+int amdgpu_enforce_isolation = -1;</div><div class='add'>+int amdgpu_modeset = -1;</div><div class='add'>+</div><div class='add'>+/* Specifies the default granularity for SVM, used in buffer</div><div class='add'>+ * migration and restoration of backing memory when handling</div><div class='add'>+ * recoverable page faults.</div><div class='add'>+ *</div><div class='add'>+ * The value is given as log(numPages(buffer)); for a 2 MiB</div><div class='add'>+ * buffer it computes to be 9</div><div class='add'>+ */</div><div class='add'>+uint amdgpu_svm_default_granularity = 9;</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * OverDrive(bit 14) disabled by default</div><div class='ctx'>  * GFX DCS(bit 19) disabled by default</div><div class='hunk'>@@ -195,7 +223,9 @@ int amdgpu_async_gfx_ring = 1;</div><div class='ctx'> int amdgpu_mcbp = -1;</div><div class='ctx'> int amdgpu_discovery = -1;</div><div class='ctx'> int amdgpu_mes;</div><div class='add'>+int amdgpu_mes_log_enable = 0;</div><div class='ctx'> int amdgpu_mes_kiq;</div><div class='add'>+int amdgpu_uni_mes = 1;</div><div class='ctx'> int amdgpu_noretry = -1;</div><div class='ctx'> int amdgpu_force_asic_type = -1;</div><div class='ctx'> int amdgpu_tmz = -1; /* auto */</div><div class='hunk'>@@ -213,8 +243,9 @@ uint amdgpu_debug_mask;</div><div class='ctx'> int amdgpu_agp = -1; /* auto */</div><div class='ctx'> int amdgpu_wbrf = -1;</div><div class='ctx'> int amdgpu_damage_clips = -1; /* auto */</div><div class='del'>-</div><div class='del'>-static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);</div><div class='add'>+int amdgpu_umsch_mm_fwlog;</div><div class='add'>+int amdgpu_rebar = -1; /* auto */</div><div class='add'>+int amdgpu_user_queue = -1;</div><div class='ctx'> </div><div class='ctx'> DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,</div><div class='ctx'> 			"DRM_UT_CORE",</div><div class='hunk'>@@ -230,9 +261,6 @@ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_mgpu_info mgpu_info = {</div><div class='ctx'> 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),</div><div class='del'>-	.delayed_reset_work = __DELAYED_WORK_INITIALIZER(</div><div class='del'>-			mgpu_info.delayed_reset_work,</div><div class='del'>-			amdgpu_drv_delayed_reset_work_handler, 0),</div><div class='ctx'> };</div><div class='ctx'> int amdgpu_ras_enable = -1;</div><div class='ctx'> uint amdgpu_ras_mask = 0xffffffff;</div><div class='hunk'>@@ -267,7 +295,8 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600);</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: gttsize (int)</div><div class='ctx'>  * Restrict the size of GTT domain (for userspace use) in MiB for testing.</div><div class='del'>- * The default is -1 (Use 1/2 RAM, minimum value is 3GB).</div><div class='add'>+ * The default is -1 (Use value specified by TTM).</div><div class='add'>+ * This parameter is deprecated and will be removed in the future.</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");</div><div class='ctx'> module_param_named(gttsize, amdgpu_gtt_size, int, 0600);</div><div class='hunk'>@@ -283,7 +312,7 @@ module_param_named(moverate, amdgpu_moverate, int, 0600);</div><div class='ctx'>  * DOC: audio (int)</div><div class='ctx'>  * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.</div><div class='ctx'>  */</div><div class='del'>-MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");</div><div class='add'>+MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)");</div><div class='ctx'> module_param_named(audio, amdgpu_audio, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -315,25 +344,26 @@ MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");</div><div class='ctx'> module_param_named(msi, amdgpu_msi, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * DOC: svm_default_granularity (uint)</div><div class='add'>+ * Used in buffer migration and handling of recoverable page faults</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");</div><div class='add'>+module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DOC: lockup_timeout (string)</div><div class='ctx'>  * Set GPU scheduler timeout value in ms.</div><div class='ctx'>  *</div><div class='del'>- * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or</div><div class='del'>- * multiple values specified. 0 and negative values are invalidated. They will be adjusted</div><div class='del'>- * to the default timeout.</div><div class='add'>+ * The format can be [single value] for setting all timeouts at once or</div><div class='add'>+ * [GFX,Compute,SDMA,Video] to set individual timeouts.</div><div class='add'>+ * Negative values mean infinity.</div><div class='ctx'>  *</div><div class='del'>- * - With one value specified, the setting will apply to all non-compute jobs.</div><div class='del'>- * - With multiple values specified, the first one will be for GFX.</div><div class='del'>- *   The second one is for Compute. The third and fourth ones are</div><div class='del'>- *   for SDMA and Video.</div><div class='del'>- *</div><div class='del'>- * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)</div><div class='del'>- * jobs is 10000. The timeout for compute is 60000.</div><div class='add'>+ * By default(with no lockup_timeout settings), the timeout for all queues is 2000.</div><div class='ctx'>  */</div><div class='del'>-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "</div><div class='del'>-		"for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "</div><div class='del'>-		"for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");</div><div class='del'>-module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);</div><div class='add'>+MODULE_PARM_DESC(lockup_timeout,</div><div class='add'>+		 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video].");</div><div class='add'>+module_param_string(lockup_timeout, amdgpu_lockup_timeout,</div><div class='add'>+		    sizeof(amdgpu_lockup_timeout), 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: dpm (int)</div><div class='hunk'>@@ -379,7 +409,7 @@ module_param_named(runpm, amdgpu_runtime_pm, int, 0444);</div><div class='ctx'>  * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");</div><div class='del'>-module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);</div><div class='add'>+module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: bapm (int)</div><div class='hunk'>@@ -437,7 +467,7 @@ module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);</div><div class='ctx'>  * Enable experimental hw support (1 = enable). The default is 0 (disabled).</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");</div><div class='del'>-module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);</div><div class='add'>+module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: dc (int)</div><div class='hunk'>@@ -548,14 +578,14 @@ module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);</div><div class='ctx'>  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");</div><div class='del'>-module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);</div><div class='add'>+module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: emu_mode (int)</div><div class='ctx'>  * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");</div><div class='del'>-module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);</div><div class='add'>+module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: ras_enable (int)</div><div class='hunk'>@@ -588,39 +618,39 @@ module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: si_support (int)</div><div class='del'>- * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,</div><div class='del'>- * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,</div><div class='del'>- * otherwise using amdgpu driver.</div><div class='del'>- */</div><div class='add'>+ * 1 = enabled, 0 = disabled, -1 = default</div><div class='add'>+ *</div><div class='add'>+ * SI (Southern Islands) are first generation GCN GPUs, supported by both</div><div class='add'>+ * drivers: radeon (old) and amdgpu (new). This parameter controls whether</div><div class='add'>+ * amdgpu should support SI.</div><div class='add'>+ * By default, SI dedicated GPUs are supported by amdgpu.</div><div class='add'>+ * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu.</div><div class='add'>+ * See also radeon.si_support which should be disabled when amdgpu.si_support is</div><div class='add'>+ * enabled, and vice versa.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_si_support = -1;</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_SI</div><div class='del'>-</div><div class='del'>-#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)</div><div class='del'>-int amdgpu_si_support;</div><div class='del'>-MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");</div><div class='del'>-#else</div><div class='del'>-int amdgpu_si_support = 1;</div><div class='del'>-MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");</div><div class='del'>-#endif</div><div class='del'>-</div><div class='add'>+MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)");</div><div class='ctx'> module_param_named(si_support, amdgpu_si_support, int, 0444);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: cik_support (int)</div><div class='del'>- * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,</div><div class='del'>- * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,</div><div class='del'>- * otherwise using amdgpu driver.</div><div class='del'>- */</div><div class='add'>+ * 1 = enabled, 0 = disabled, -1 = default</div><div class='add'>+ *</div><div class='add'>+ * CIK (Sea Islands) are second generation GCN GPUs, supported by both</div><div class='add'>+ * drivers: radeon (old) and amdgpu (new). This parameter controls whether</div><div class='add'>+ * amdgpu should support CIK.</div><div class='add'>+ * By default:</div><div class='add'>+ * - CIK dedicated GPUs are supported by amdgpu.</div><div class='add'>+ * - CIK APUs are supported by radeon (except when radeon is not built).</div><div class='add'>+ * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu.</div><div class='add'>+ * See also radeon.cik_support which should be disabled when amdgpu.cik_support is</div><div class='add'>+ * enabled, and vice versa.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_cik_support = -1;</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_CIK</div><div class='del'>-</div><div class='del'>-#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)</div><div class='del'>-int amdgpu_cik_support;</div><div class='del'>-MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");</div><div class='del'>-#else</div><div class='del'>-int amdgpu_cik_support = 1;</div><div class='del'>-MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");</div><div class='del'>-#endif</div><div class='del'>-</div><div class='add'>+MODULE_PARM_DESC(cik_support, "CIK support  (1 = enabled, 0 = disabled, -1 = default)");</div><div class='ctx'> module_param_named(cik_support, amdgpu_cik_support, int, 0444);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -668,6 +698,15 @@ MODULE_PARM_DESC(mes,</div><div class='ctx'> module_param_named(mes, amdgpu_mes, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * DOC: mes_log_enable (int)</div><div class='add'>+ * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.</div><div class='add'>+ * (0 = disabled (default), 1 = enabled)</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(mes_log_enable,</div><div class='add'>+	"Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");</div><div class='add'>+module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DOC: mes_kiq (int)</div><div class='ctx'>  * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.</div><div class='ctx'>  * (0 = disabled (default), 1 = enabled)</div><div class='hunk'>@@ -677,6 +716,15 @@ MODULE_PARM_DESC(mes_kiq,</div><div class='ctx'> module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * DOC: uni_mes (int)</div><div class='add'>+ * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler.</div><div class='add'>+ * (0 = disabled (default), 1 = enabled)</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(uni_mes,</div><div class='add'>+	"Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)");</div><div class='add'>+module_param_named(uni_mes, amdgpu_uni_mes, int, 0444);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DOC: noretry (int)</div><div class='ctx'>  * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that</div><div class='ctx'>  * do not support per-process XNACK this also disables retry page faults.</div><div class='hunk'>@@ -692,7 +740,7 @@ module_param_named(noretry, amdgpu_noretry, int, 0644);</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(force_asic_type,</div><div class='ctx'> 	"A non negative value used to specify the asic type for all supported GPUs");</div><div class='del'>-module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);</div><div class='add'>+module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: use_xgmi_p2p (int)</div><div class='hunk'>@@ -711,7 +759,7 @@ module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);</div><div class='ctx'>  * assigns queues to HQDs.</div><div class='ctx'>  */</div><div class='ctx'> int sched_policy = KFD_SCHED_POLICY_HWS;</div><div class='del'>-module_param(sched_policy, int, 0444);</div><div class='add'>+module_param_unsafe(sched_policy, int, 0444);</div><div class='ctx'> MODULE_PARM_DESC(sched_policy,</div><div class='ctx'> 	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");</div><div class='ctx'> </div><div class='hunk'>@@ -761,7 +809,7 @@ MODULE_PARM_DESC(send_sigterm,</div><div class='ctx'>  * Setting 1 enables halt on hang.</div><div class='ctx'>  */</div><div class='ctx'> int halt_if_hws_hang;</div><div class='del'>-module_param(halt_if_hws_hang, int, 0644);</div><div class='add'>+module_param_unsafe(halt_if_hws_hang, int, 0644);</div><div class='ctx'> MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -770,7 +818,7 @@ MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (defau</div><div class='ctx'>  * check says. Default value: false (rely on MEC2 firmware version check).</div><div class='ctx'>  */</div><div class='ctx'> bool hws_gws_support;</div><div class='del'>-module_param(hws_gws_support, bool, 0444);</div><div class='add'>+module_param_unsafe(hws_gws_support, bool, 0444);</div><div class='ctx'> MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -803,7 +851,7 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_no_queue_eviction_on_vm_fault;</div><div class='ctx'> MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");</div><div class='del'>-module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);</div><div class='add'>+module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -811,7 +859,7 @@ module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_mtype_local;</div><div class='ctx'> MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");</div><div class='del'>-module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);</div><div class='add'>+module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: pcie_p2p (bool)</div><div class='hunk'>@@ -833,7 +881,7 @@ module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: dcdebugmask (uint)</div><div class='del'>- * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.</div><div class='add'>+ * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");</div><div class='ctx'> module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);</div><div class='hunk'>@@ -850,7 +898,7 @@ module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);</div><div class='ctx'>  * the ABM algorithm, with 1 being the least reduction and 4 being the most</div><div class='ctx'>  * reduction.</div><div class='ctx'>  *</div><div class='del'>- * Defaults to -1, or disabled. Userspace can only override this level after</div><div class='add'>+ * Defaults to -1, or auto. Userspace can only override this level after</div><div class='ctx'>  * boot if it's set to auto.</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_dm_abm_level = -1;</div><div class='hunk'>@@ -907,7 +955,7 @@ module_param_named(tmz, amdgpu_tmz, int, 0444);</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(</div><div class='ctx'> 	freesync_video,</div><div class='del'>-	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");</div><div class='add'>+	"Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)");</div><div class='ctx'> module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -915,7 +963,7 @@ module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);</div><div class='ctx'>  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");</div><div class='del'>-module_param_named(reset_method, amdgpu_reset_method, int, 0444);</div><div class='add'>+module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: bad_page_threshold (int) Bad page threshold is specifies the</div><div class='hunk'>@@ -923,7 +971,7 @@ module_param_named(reset_method, amdgpu_reset_method, int, 0444);</div><div class='ctx'>  * result in the GPU entering bad status when the number of total</div><div class='ctx'>  * faulty pages by ECC exceeds the threshold value.</div><div class='ctx'>  */</div><div class='del'>-MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");</div><div class='add'>+MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 &lt; threshold &lt; max records, user-defined threshold)");</div><div class='ctx'> module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);</div><div class='ctx'> </div><div class='ctx'> MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");</div><div class='hunk'>@@ -956,6 +1004,13 @@ MODULE_PARM_DESC(umsch_mm,</div><div class='ctx'> module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * DOC: umsch_mm_fwlog (int)</div><div class='add'>+ * Enable umschfw log output for debugging, the default is disabled.</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)");</div><div class='add'>+module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DOC: smu_pptable_id (int)</div><div class='ctx'>  * Used to override pptable id. id = 0 use VBIOS pptable.</div><div class='ctx'>  * id &gt; 0 use the soft pptable with specicfied id.</div><div class='hunk'>@@ -980,11 +1035,20 @@ module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * DOC: enforce_isolation (bool)</div><div class='del'>- * enforce process isolation between graphics and compute via using the same reserved vmid.</div><div class='add'>+ * DOC: enforce_isolation (int)</div><div class='add'>+ * enforce process isolation between graphics and compute.</div><div class='add'>+ * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)</div><div class='add'>+ */</div><div class='add'>+module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444);</div><div class='add'>+MODULE_PARM_DESC(enforce_isolation,</div><div class='add'>+"enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)");</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: modeset (int)</div><div class='add'>+ * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto).</div><div class='ctx'>  */</div><div class='del'>-module_param(enforce_isolation, bool, 0444);</div><div class='del'>-MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on");</div><div class='add'>+MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)");</div><div class='add'>+module_param_named(modeset, amdgpu_modeset, int, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: seamless (int)</div><div class='hunk'>@@ -1002,9 +1066,14 @@ module_param_named(seamless, amdgpu_seamless, int, 0444);</div><div class='ctx'>  *   limits the VRAM size reported to ROCm applications to the visible</div><div class='ctx'>  *   size, usually 256MB.</div><div class='ctx'>  * - 0x4: Disable GPU soft recovery, always do a full reset</div><div class='add'>+ * - 0x8: Use VRAM for firmware loading</div><div class='add'>+ * - 0x10: Enable ACA based RAS logging</div><div class='add'>+ * - 0x20: Enable experimental resets</div><div class='add'>+ * - 0x40: Disable ring resets</div><div class='add'>+ * - 0x80: Use VRAM for SMU pool</div><div class='ctx'>  */</div><div class='ctx'> MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");</div><div class='del'>-module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);</div><div class='add'>+module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: agp (int)</div><div class='hunk'>@@ -1031,6 +1100,28 @@ MODULE_PARM_DESC(wbrf,</div><div class='ctx'> 	"Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");</div><div class='ctx'> module_param_named(wbrf, amdgpu_wbrf, int, 0444);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * DOC: rebar (int)</div><div class='add'>+ * Allow BAR resizing.  Disable this to prevent the driver from attempting</div><div class='add'>+ * to resize the BAR if the GPU supports it and there is available MMIO space.</div><div class='add'>+ * Note that this just prevents the driver from resizing the BAR.  The BIOS</div><div class='add'>+ * may have already resized the BAR at boot time.</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)");</div><div class='add'>+module_param_named(rebar, amdgpu_rebar, int, 0444);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: user_queue (int)</div><div class='add'>+ * Enable user queues on systems that support user queues. Possible values:</div><div class='add'>+ *</div><div class='add'>+ * - -1 = auto (ASIC specific default)</div><div class='add'>+ * -  0 = user queues disabled</div><div class='add'>+ * -  1 = user queues enabled and kernel queues enabled (if supported)</div><div class='add'>+ * -  2 = user queues enabled and kernel queues disabled</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");</div><div class='add'>+module_param_named(user_queue, amdgpu_user_queue, int, 0444);</div><div class='add'>+</div><div class='ctx'> /* These devices are not supported by amdgpu.</div><div class='ctx'>  * They are supported by the mach64, r128, radeon drivers</div><div class='ctx'>  */</div><div class='hunk'>@@ -1744,7 +1835,6 @@ static const u16 amdgpu_unsupported_pciidlist[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct pci_device_id pciidlist[] = {</div><div class='del'>-#ifdef CONFIG_DRM_AMDGPU_SI</div><div class='ctx'> 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},</div><div class='ctx'> 	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},</div><div class='ctx'> 	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},</div><div class='hunk'>@@ -1817,8 +1907,6 @@ static const struct pci_device_id pciidlist[] = {</div><div class='ctx'> 	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},</div><div class='ctx'> 	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},</div><div class='ctx'> 	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},</div><div class='del'>-#endif</div><div class='del'>-#ifdef CONFIG_DRM_AMDGPU_CIK</div><div class='ctx'> 	/* Kaveri */</div><div class='ctx'> 	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},</div><div class='ctx'> 	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},</div><div class='hunk'>@@ -1901,7 +1989,6 @@ static const struct pci_device_id pciidlist[] = {</div><div class='ctx'> 	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},</div><div class='ctx'> 	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},</div><div class='ctx'> 	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},</div><div class='del'>-#endif</div><div class='ctx'> 	/* topaz */</div><div class='ctx'> 	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},</div><div class='ctx'> 	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},</div><div class='hunk'>@@ -2080,6 +2167,11 @@ static const struct pci_device_id pciidlist[] = {</div><div class='ctx'> 	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},</div><div class='ctx'> </div><div class='ctx'> 	/* CYAN_SKILLFISH */</div><div class='add'>+	{0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='add'>+	{0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='add'>+	{0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='add'>+	{0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='add'>+	{0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='ctx'> 	{0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='ctx'> 	{0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},</div><div class='ctx'> </div><div class='hunk'>@@ -2136,7 +2228,6 @@ static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 						adev-&gt;pdev-&gt;bus-&gt;number, i);</div><div class='ctx'> 		if (p) {</div><div class='ctx'> 			pm_runtime_get_sync(&amp;p-&gt;dev);</div><div class='del'>-			pm_runtime_mark_last_busy(&amp;p-&gt;dev);</div><div class='ctx'> 			pm_runtime_put_autosuspend(&amp;p-&gt;dev);</div><div class='ctx'> 			pci_dev_put(p);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2164,6 +2255,39 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev)</div><div class='ctx'> 		pr_info("debug: place fw in vram for frontdoor loading\n");</div><div class='ctx'> 		adev-&gt;debug_use_vram_fw_buf = true;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_ENABLE_RAS_ACA) {</div><div class='add'>+		pr_info("debug: enable RAS ACA\n");</div><div class='add'>+		adev-&gt;debug_enable_ras_aca = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_ENABLE_EXP_RESETS) {</div><div class='add'>+		pr_info("debug: enable experimental reset features\n");</div><div class='add'>+		adev-&gt;debug_exp_resets = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) {</div><div class='add'>+		pr_info("debug: ring reset disabled\n");</div><div class='add'>+		adev-&gt;debug_disable_gpu_ring_reset = true;</div><div class='add'>+	}</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_SMU_POOL) {</div><div class='add'>+		pr_info("debug: use vram for smu pool\n");</div><div class='add'>+		adev-&gt;pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;</div><div class='add'>+	}</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_VM_USERPTR) {</div><div class='add'>+		pr_info("debug: VM mode debug for userptr is enabled\n");</div><div class='add'>+		adev-&gt;debug_vm_userptr = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) {</div><div class='add'>+		pr_info("debug: disable kernel logs of correctable errors\n");</div><div class='add'>+		adev-&gt;debug_disable_ce_logs = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_ENABLE_CE_CS) {</div><div class='add'>+		pr_info("debug: allowing command submission to CE engine\n");</div><div class='add'>+		adev-&gt;debug_enable_ce_cs = true;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)</div><div class='hunk'>@@ -2182,6 +2306,72 @@ static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long fl</div><div class='ctx'> 	return flags;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool amdgpu_support_enabled(struct device *dev,</div><div class='add'>+				   const enum amd_asic_type family)</div><div class='add'>+{</div><div class='add'>+	const char *gen;</div><div class='add'>+	const char *param;</div><div class='add'>+	int module_param = -1;</div><div class='add'>+	bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON);</div><div class='add'>+	bool amdgpu_support_built = false;</div><div class='add'>+	bool support_by_default = false;</div><div class='add'>+</div><div class='add'>+	switch (family) {</div><div class='add'>+	case CHIP_TAHITI:</div><div class='add'>+	case CHIP_PITCAIRN:</div><div class='add'>+	case CHIP_VERDE:</div><div class='add'>+	case CHIP_OLAND:</div><div class='add'>+	case CHIP_HAINAN:</div><div class='add'>+		gen = "SI";</div><div class='add'>+		param = "si_support";</div><div class='add'>+		module_param = amdgpu_si_support;</div><div class='add'>+		amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI);</div><div class='add'>+		support_by_default = true;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case CHIP_BONAIRE:</div><div class='add'>+	case CHIP_HAWAII:</div><div class='add'>+		support_by_default = true;</div><div class='add'>+		fallthrough;</div><div class='add'>+	case CHIP_KAVERI:</div><div class='add'>+	case CHIP_KABINI:</div><div class='add'>+	case CHIP_MULLINS:</div><div class='add'>+		gen = "CIK";</div><div class='add'>+		param = "cik_support";</div><div class='add'>+		module_param = amdgpu_cik_support;</div><div class='add'>+		amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		/* All other chips are supported by amdgpu only */</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_support_built) {</div><div class='add'>+		dev_info(dev, "amdgpu built without %s support\n", gen);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((module_param == -1 &amp;&amp; (support_by_default || !radeon_support_built)) ||</div><div class='add'>+	    module_param == 1) {</div><div class='add'>+		if (radeon_support_built)</div><div class='add'>+			dev_info(dev, "%s support provided by amdgpu.\n"</div><div class='add'>+				 "Use radeon.%s=1 amdgpu.%s=0 to override.\n",</div><div class='add'>+				 gen, param, param);</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (radeon_support_built)</div><div class='add'>+		dev_info(dev, "%s support provided by radeon.\n"</div><div class='add'>+			 "Use radeon.%s=0 amdgpu.%s=1 to override.\n",</div><div class='add'>+			 gen, param, param);</div><div class='add'>+	else if (module_param == 0)</div><div class='add'>+		dev_info(dev, "%s support disabled by module param\n", gen);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 			    const struct pci_device_id *ent)</div><div class='ctx'> {</div><div class='hunk'>@@ -2191,6 +2381,12 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 	int ret, retry = 0, i;</div><div class='ctx'> 	bool supports_atomic = false;</div><div class='ctx'> </div><div class='add'>+	if ((pdev-&gt;class &gt;&gt; 8) == PCI_CLASS_DISPLAY_VGA ||</div><div class='add'>+	    (pdev-&gt;class &gt;&gt; 8) == PCI_CLASS_DISPLAY_OTHER) {</div><div class='add'>+		if (drm_firmware_drivers_only() &amp;&amp; amdgpu_modeset == -1)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* skip devices which are owned by radeon */</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {</div><div class='ctx'> 		if (amdgpu_unsupported_pciidlist[i] == pdev-&gt;device)</div><div class='hunk'>@@ -2201,7 +2397,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 		amdgpu_aspm = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_virtual_display ||</div><div class='del'>-	    amdgpu_device_asic_has_dc_support(flags &amp; AMD_ASIC_MASK))</div><div class='add'>+	    amdgpu_device_asic_has_dc_support(pdev, flags &amp; AMD_ASIC_MASK))</div><div class='ctx'> 		supports_atomic = true;</div><div class='ctx'> </div><div class='ctx'> 	if ((flags &amp; AMD_EXP_HW_SUPPORT) &amp;&amp; !amdgpu_exp_hw_support) {</div><div class='hunk'>@@ -2223,40 +2419,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 		return -ENOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_DRM_AMDGPU_SI</div><div class='del'>-	if (!amdgpu_si_support) {</div><div class='del'>-		switch (flags &amp; AMD_ASIC_MASK) {</div><div class='del'>-		case CHIP_TAHITI:</div><div class='del'>-		case CHIP_PITCAIRN:</div><div class='del'>-		case CHIP_VERDE:</div><div class='del'>-		case CHIP_OLAND:</div><div class='del'>-		case CHIP_HAINAN:</div><div class='del'>-			dev_info(&amp;pdev-&gt;dev,</div><div class='del'>-				 "SI support provided by radeon.\n");</div><div class='del'>-			dev_info(&amp;pdev-&gt;dev,</div><div class='del'>-				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"</div><div class='del'>-				);</div><div class='del'>-			return -ENODEV;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-#endif</div><div class='del'>-#ifdef CONFIG_DRM_AMDGPU_CIK</div><div class='del'>-	if (!amdgpu_cik_support) {</div><div class='del'>-		switch (flags &amp; AMD_ASIC_MASK) {</div><div class='del'>-		case CHIP_KAVERI:</div><div class='del'>-		case CHIP_BONAIRE:</div><div class='del'>-		case CHIP_HAWAII:</div><div class='del'>-		case CHIP_KABINI:</div><div class='del'>-		case CHIP_MULLINS:</div><div class='del'>-			dev_info(&amp;pdev-&gt;dev,</div><div class='del'>-				 "CIK support provided by radeon.\n");</div><div class='del'>-			dev_info(&amp;pdev-&gt;dev,</div><div class='del'>-				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"</div><div class='del'>-				);</div><div class='del'>-			return -ENODEV;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-#endif</div><div class='add'>+	if (!amdgpu_support_enabled(&amp;pdev-&gt;dev, flags &amp; AMD_ASIC_MASK))</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	adev = devm_drm_dev_alloc(&amp;pdev-&gt;dev, &amp;amdgpu_kms_driver, typeof(*adev), ddev);</div><div class='ctx'> 	if (IS_ERR(adev))</div><div class='hunk'>@@ -2306,11 +2470,15 @@ retry_init:</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (adev-&gt;mode_info.mode_config_initialized &amp;&amp;</div><div class='ctx'> 	    !list_empty(&amp;adev_to_drm(adev)-&gt;mode_config.connector_list)) {</div><div class='add'>+		const struct drm_format_info *format;</div><div class='add'>+</div><div class='ctx'> 		/* select 8 bpp console on low vram cards */</div><div class='ctx'> 		if (adev-&gt;gmc.real_vram_size &lt;= (32*1024*1024))</div><div class='del'>-			drm_fbdev_generic_setup(adev_to_drm(adev), 8);</div><div class='add'>+			format = drm_format_info(DRM_FORMAT_C8);</div><div class='ctx'> 		else</div><div class='del'>-			drm_fbdev_generic_setup(adev_to_drm(adev), 32);</div><div class='add'>+			format = NULL;</div><div class='add'>+</div><div class='add'>+		drm_client_setup(adev_to_drm(adev), format);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_debugfs_init(adev);</div><div class='hunk'>@@ -2319,10 +2487,10 @@ retry_init:</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.rpm_mode != AMDGPU_RUNPM_NONE) {</div><div class='ctx'> 		/* only need to skip on ATPX */</div><div class='del'>-		if (amdgpu_device_supports_px(ddev))</div><div class='add'>+		if (amdgpu_device_supports_px(adev))</div><div class='ctx'> 			dev_pm_set_driver_flags(ddev-&gt;dev, DPM_FLAG_NO_DIRECT_COMPLETE);</div><div class='ctx'> 		/* we want direct complete for BOCO */</div><div class='del'>-		if (amdgpu_device_supports_boco(ddev))</div><div class='add'>+		if (amdgpu_device_supports_boco(adev))</div><div class='ctx'> 			dev_pm_set_driver_flags(ddev-&gt;dev, DPM_FLAG_SMART_PREPARE |</div><div class='ctx'> 						DPM_FLAG_SMART_SUSPEND |</div><div class='ctx'> 						DPM_FLAG_MAY_SKIP_RESUME);</div><div class='hunk'>@@ -2331,7 +2499,6 @@ retry_init:</div><div class='ctx'> </div><div class='ctx'> 		pm_runtime_allow(ddev-&gt;dev);</div><div class='ctx'> </div><div class='del'>-		pm_runtime_mark_last_busy(ddev-&gt;dev);</div><div class='ctx'> 		pm_runtime_put_autosuspend(ddev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 		pci_wake_from_d3(pdev, TRUE);</div><div class='hunk'>@@ -2355,9 +2522,9 @@ retry_init:</div><div class='ctx'> 		 * into D0 state. Then there will be a PMFW-aware D-state</div><div class='ctx'> 		 * transition(D0-&gt;D3) on runpm suspend.</div><div class='ctx'> 		 */</div><div class='del'>-		if (amdgpu_device_supports_baco(ddev) &amp;&amp;</div><div class='add'>+		if (amdgpu_device_supports_baco(adev) &amp;&amp;</div><div class='ctx'> 		    !(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp;</div><div class='del'>-		    (adev-&gt;asic_type &gt;= CHIP_NAVI10))</div><div class='add'>+		    adev-&gt;asic_type &gt;= CHIP_NAVI10)</div><div class='ctx'> 			amdgpu_get_secondary_funcs(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2374,7 +2541,9 @@ amdgpu_pci_remove(struct pci_dev *pdev)</div><div class='ctx'> 	struct drm_device *dev = pci_get_drvdata(pdev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_ras_eeprom_check_and_recover(adev);</div><div class='ctx'> 	amdgpu_xcp_dev_unplug(adev);</div><div class='add'>+	amdgpu_gmc_prepare_nps_mode_change(adev);</div><div class='ctx'> 	drm_dev_unplug(dev);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.rpm_mode != AMDGPU_RUNPM_NONE) {</div><div class='hunk'>@@ -2402,6 +2571,10 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)</div><div class='ctx'> 	if (amdgpu_ras_intr_triggered())</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	/* device maybe not resumed here, return immediately in this case */</div><div class='add'>+	if (adev-&gt;in_s4 &amp;&amp; adev-&gt;in_suspend)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	/* if we are running in a VM, make sure the device</div><div class='ctx'> 	 * torn down properly on reboot/shutdown.</div><div class='ctx'> 	 * unfortunately we can't detect certain</div><div class='hunk'>@@ -2409,95 +2582,24 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!amdgpu_passthrough(adev))</div><div class='ctx'> 		adev-&gt;mp1_state = PP_MP1_STATE_UNLOAD;</div><div class='del'>-	amdgpu_device_ip_suspend(adev);</div><div class='add'>+	amdgpu_device_prepare(dev);</div><div class='add'>+	amdgpu_device_suspend(dev, true);</div><div class='ctx'> 	adev-&gt;mp1_state = PP_MP1_STATE_NONE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_drv_delayed_reset_work_handler - work handler for reset</div><div class='del'>- *</div><div class='del'>- * @work: work_struct.</div><div class='del'>- */</div><div class='del'>-static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)</div><div class='del'>-{</div><div class='del'>-	struct list_head device_list;</div><div class='del'>-	struct amdgpu_device *adev;</div><div class='del'>-	int i, r;</div><div class='del'>-	struct amdgpu_reset_context reset_context;</div><div class='del'>-</div><div class='del'>-	memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;mgpu_info.mutex);</div><div class='del'>-	if (mgpu_info.pending_reset == true) {</div><div class='del'>-		mutex_unlock(&amp;mgpu_info.mutex);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-	mgpu_info.pending_reset = true;</div><div class='del'>-	mutex_unlock(&amp;mgpu_info.mutex);</div><div class='del'>-</div><div class='del'>-	/* Use a common context, just need to make sure full reset is done */</div><div class='del'>-	reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='del'>-	set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mgpu_info.num_dgpu; i++) {</div><div class='del'>-		adev = mgpu_info.gpu_ins[i].adev;</div><div class='del'>-		reset_context.reset_req_dev = adev;</div><div class='del'>-		r = amdgpu_device_pre_asic_reset(adev, &amp;reset_context);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",</div><div class='del'>-				r, adev_to_drm(adev)-&gt;unique);</div><div class='del'>-		}</div><div class='del'>-		if (!queue_work(system_unbound_wq, &amp;adev-&gt;xgmi_reset_work))</div><div class='del'>-			r = -EALREADY;</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; mgpu_info.num_dgpu; i++) {</div><div class='del'>-		adev = mgpu_info.gpu_ins[i].adev;</div><div class='del'>-		flush_work(&amp;adev-&gt;xgmi_reset_work);</div><div class='del'>-		adev-&gt;gmc.xgmi.pending_reset = false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* reset function will rebuild the xgmi hive info , clear it now */</div><div class='del'>-	for (i = 0; i &lt; mgpu_info.num_dgpu; i++)</div><div class='del'>-		amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);</div><div class='del'>-</div><div class='del'>-	INIT_LIST_HEAD(&amp;device_list);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mgpu_info.num_dgpu; i++)</div><div class='del'>-		list_add_tail(&amp;mgpu_info.gpu_ins[i].adev-&gt;reset_list, &amp;device_list);</div><div class='del'>-</div><div class='del'>-	/* unregister the GPU first, reset function will add them back */</div><div class='del'>-	list_for_each_entry(adev, &amp;device_list, reset_list)</div><div class='del'>-		amdgpu_unregister_gpu_instance(adev);</div><div class='del'>-</div><div class='del'>-	/* Use a common context, just need to make sure full reset is done */</div><div class='del'>-	set_bit(AMDGPU_SKIP_HW_RESET, &amp;reset_context.flags);</div><div class='del'>-	r = amdgpu_do_asic_reset(&amp;device_list, &amp;reset_context);</div><div class='del'>-</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("reinit gpus failure");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; mgpu_info.num_dgpu; i++) {</div><div class='del'>-		adev = mgpu_info.gpu_ins[i].adev;</div><div class='del'>-		if (!adev-&gt;kfd.init_complete) {</div><div class='del'>-			kgd2kfd_init_zone_device(adev);</div><div class='del'>-			amdgpu_amdkfd_device_init(adev);</div><div class='del'>-			amdgpu_amdkfd_drm_client_create(adev);</div><div class='del'>-		}</div><div class='del'>-		amdgpu_ttm_set_buffer_funcs_status(adev, true);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int amdgpu_pmops_prepare(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *drm_dev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='ctx'> </div><div class='add'>+	/* device maybe not resumed here, return immediately in this case */</div><div class='add'>+	if (adev-&gt;in_s4 &amp;&amp; adev-&gt;in_suspend)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	/* Return a positive number here so</div><div class='ctx'> 	 * DPM_FLAG_SMART_SUSPEND works properly</div><div class='ctx'> 	 */</div><div class='del'>-	if (amdgpu_device_supports_boco(drm_dev) &amp;&amp;</div><div class='del'>-	    pm_runtime_suspended(dev))</div><div class='add'>+	if (amdgpu_device_supports_boco(adev) &amp;&amp; pm_runtime_suspended(dev))</div><div class='ctx'> 		return 1;</div><div class='ctx'> </div><div class='ctx'> 	/* if we will not support s3 or s2i for the device</div><div class='hunk'>@@ -2512,7 +2614,7 @@ static int amdgpu_pmops_prepare(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_pmops_complete(struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	/* nothing to do */</div><div class='add'>+	amdgpu_device_complete(dev_get_drvdata(dev));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_pmops_suspend(struct device *dev)</div><div class='hunk'>@@ -2520,13 +2622,28 @@ static int amdgpu_pmops_suspend(struct device *dev)</div><div class='ctx'> 	struct drm_device *drm_dev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;suspend_complete = false;</div><div class='ctx'> 	if (amdgpu_acpi_is_s0ix_active(adev))</div><div class='ctx'> 		adev-&gt;in_s0ix = true;</div><div class='ctx'> 	else if (amdgpu_acpi_is_s3_active(adev))</div><div class='ctx'> 		adev-&gt;in_s3 = true;</div><div class='del'>-	if (!adev-&gt;in_s0ix &amp;&amp; !adev-&gt;in_s3)</div><div class='add'>+	if (!adev-&gt;in_s0ix &amp;&amp; !adev-&gt;in_s3) {</div><div class='add'>+#if IS_ENABLED(CONFIG_SUSPEND)</div><div class='add'>+		/* don't allow going deep first time followed by s2idle the next time */</div><div class='add'>+		if (adev-&gt;last_suspend_state != PM_SUSPEND_ON &amp;&amp;</div><div class='add'>+		    adev-&gt;last_suspend_state != pm_suspend_target_state) {</div><div class='add'>+			drm_err_once(drm_dev, "Unsupported suspend state %d\n",</div><div class='add'>+				     pm_suspend_target_state);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+#endif</div><div class='ctx'> 		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_SUSPEND)</div><div class='add'>+	/* cache the state last used for suspend */</div><div class='add'>+	adev-&gt;last_suspend_state = pm_suspend_target_state;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	return amdgpu_device_suspend(drm_dev, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2534,10 +2651,14 @@ static int amdgpu_pmops_suspend_noirq(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *drm_dev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;suspend_complete = true;</div><div class='del'>-	if (amdgpu_acpi_should_gpu_reset(adev))</div><div class='del'>-		return amdgpu_asic_reset(adev);</div><div class='add'>+	if (amdgpu_acpi_should_gpu_reset(adev)) {</div><div class='add'>+		amdgpu_device_lock_reset_domain(adev-&gt;reset_domain);</div><div class='add'>+		r = amdgpu_asic_reset(adev);</div><div class='add'>+		amdgpu_device_unlock_reset_domain(adev-&gt;reset_domain);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2569,9 +2690,7 @@ static int amdgpu_pmops_freeze(struct device *dev)</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;in_s4 = true;</div><div class='ctx'> 	r = amdgpu_device_suspend(drm_dev, true);</div><div class='del'>-	adev-&gt;in_s4 = false;</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -2584,12 +2703,21 @@ static int amdgpu_pmops_thaw(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *drm_dev = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='add'>+	/* do not resume device if it's normal hibernation */</div><div class='add'>+	if (!pm_hibernate_is_recovering() &amp;&amp; !pm_hibernation_mode_is_suspend())</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	return amdgpu_device_resume(drm_dev, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_pmops_poweroff(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *drm_dev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='add'>+</div><div class='add'>+	/* device maybe not resumed here, return immediately in this case */</div><div class='add'>+	if (adev-&gt;in_s4 &amp;&amp; adev-&gt;in_suspend)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_device_suspend(drm_dev, true);</div><div class='ctx'> }</div><div class='hunk'>@@ -2668,6 +2796,15 @@ static int amdgpu_runtime_idle_check_display(struct device *dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_runtime_idle_check_userq(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	struct drm_device *drm_dev = pci_get_drvdata(pdev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='add'>+</div><div class='add'>+	return xa_empty(&amp;adev-&gt;userq_doorbell_xa) ? 0 : -EBUSY;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_pmops_runtime_suspend(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='hunk'>@@ -2683,6 +2820,9 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)</div><div class='ctx'> 	ret = amdgpu_runtime_idle_check_display(dev);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='add'>+	ret = amdgpu_runtime_idle_check_userq(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* wait for all rings to drain before suspending */</div><div class='ctx'> 	for (i = 0; i &lt; AMDGPU_MAX_RINGS; i++) {</div><div class='hunk'>@@ -2734,8 +2874,9 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)</div><div class='ctx'> 		drm_dev-&gt;switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;</div><div class='ctx'> 	} else if (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BOCO) {</div><div class='ctx'> 		/* nothing to do */</div><div class='del'>-	} else if (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) {</div><div class='del'>-		amdgpu_device_baco_enter(drm_dev);</div><div class='add'>+	} else if ((adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) ||</div><div class='add'>+			(adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {</div><div class='add'>+		amdgpu_device_baco_enter(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;pdev-&gt;dev, "asic/device is runtime suspended\n");</div><div class='hunk'>@@ -2774,8 +2915,9 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)</div><div class='ctx'> 		 * PCI core handles it for _PR3.</div><div class='ctx'> 		 */</div><div class='ctx'> 		pci_set_master(pdev);</div><div class='del'>-	} else if (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) {</div><div class='del'>-		amdgpu_device_baco_exit(drm_dev);</div><div class='add'>+	} else if ((adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) ||</div><div class='add'>+			(adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {</div><div class='add'>+		amdgpu_device_baco_exit(adev);</div><div class='ctx'> 	}</div><div class='ctx'> 	ret = amdgpu_device_resume(drm_dev, false);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2802,12 +2944,32 @@ static int amdgpu_pmops_runtime_idle(struct device *dev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_runtime_idle_check_display(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev);</div><div class='add'>+	ret = amdgpu_runtime_idle_check_userq(dev);</div><div class='add'>+done:</div><div class='ctx'> 	pm_runtime_autosuspend(dev);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_drm_release(struct inode *inode, struct file *filp)</div><div class='add'>+{</div><div class='add'>+	struct drm_file *file_priv = filp-&gt;private_data;</div><div class='add'>+	struct amdgpu_fpriv *fpriv = file_priv-&gt;driver_priv;</div><div class='add'>+	struct drm_device *dev = file_priv-&gt;minor-&gt;dev;</div><div class='add'>+	int idx;</div><div class='add'>+</div><div class='add'>+	if (fpriv &amp;&amp; drm_dev_enter(dev, &amp;idx)) {</div><div class='add'>+		fpriv-&gt;evf_mgr.fd_closing = true;</div><div class='add'>+		amdgpu_eviction_fence_destroy(&amp;fpriv-&gt;evf_mgr);</div><div class='add'>+		amdgpu_userq_mgr_fini(&amp;fpriv-&gt;userq_mgr);</div><div class='add'>+		drm_dev_exit(idx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return drm_release(inode, filp);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> long amdgpu_drm_ioctl(struct file *filp,</div><div class='ctx'> 		      unsigned int cmd, unsigned long arg)</div><div class='ctx'> {</div><div class='hunk'>@@ -2822,22 +2984,21 @@ long amdgpu_drm_ioctl(struct file *filp,</div><div class='ctx'> </div><div class='ctx'> 	ret = drm_ioctl(filp, cmd, arg);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> out:</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dev_pm_ops amdgpu_pm_ops = {</div><div class='del'>-	.prepare = amdgpu_pmops_prepare,</div><div class='del'>-	.complete = amdgpu_pmops_complete,</div><div class='del'>-	.suspend = amdgpu_pmops_suspend,</div><div class='del'>-	.suspend_noirq = amdgpu_pmops_suspend_noirq,</div><div class='del'>-	.resume = amdgpu_pmops_resume,</div><div class='del'>-	.freeze = amdgpu_pmops_freeze,</div><div class='del'>-	.thaw = amdgpu_pmops_thaw,</div><div class='del'>-	.poweroff = amdgpu_pmops_poweroff,</div><div class='del'>-	.restore = amdgpu_pmops_restore,</div><div class='add'>+	.prepare = pm_sleep_ptr(amdgpu_pmops_prepare),</div><div class='add'>+	.complete = pm_sleep_ptr(amdgpu_pmops_complete),</div><div class='add'>+	.suspend = pm_sleep_ptr(amdgpu_pmops_suspend),</div><div class='add'>+	.suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq),</div><div class='add'>+	.resume = pm_sleep_ptr(amdgpu_pmops_resume),</div><div class='add'>+	.freeze = pm_sleep_ptr(amdgpu_pmops_freeze),</div><div class='add'>+	.thaw = pm_sleep_ptr(amdgpu_pmops_thaw),</div><div class='add'>+	.poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff),</div><div class='add'>+	.restore = pm_sleep_ptr(amdgpu_pmops_restore),</div><div class='ctx'> 	.runtime_suspend = amdgpu_pmops_runtime_suspend,</div><div class='ctx'> 	.runtime_resume = amdgpu_pmops_runtime_resume,</div><div class='ctx'> 	.runtime_idle = amdgpu_pmops_runtime_idle,</div><div class='hunk'>@@ -2859,7 +3020,7 @@ static const struct file_operations amdgpu_driver_kms_fops = {</div><div class='ctx'> 	.owner = THIS_MODULE,</div><div class='ctx'> 	.open = drm_open,</div><div class='ctx'> 	.flush = amdgpu_flush,</div><div class='del'>-	.release = drm_release,</div><div class='add'>+	.release = amdgpu_drm_release,</div><div class='ctx'> 	.unlocked_ioctl = amdgpu_drm_ioctl,</div><div class='ctx'> 	.mmap = drm_gem_mmap,</div><div class='ctx'> 	.poll = drm_poll,</div><div class='hunk'>@@ -2870,6 +3031,7 @@ static const struct file_operations amdgpu_driver_kms_fops = {</div><div class='ctx'> #ifdef CONFIG_PROC_FS</div><div class='ctx'> 	.show_fdinfo = drm_show_fdinfo,</div><div class='ctx'> #endif</div><div class='add'>+	.fop_flags = FOP_UNSIGNED_OFFSET,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)</div><div class='hunk'>@@ -2905,6 +3067,10 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {</div><div class='ctx'> 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='ctx'> 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='ctx'> 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct drm_driver amdgpu_kms_driver = {</div><div class='hunk'>@@ -2915,11 +3081,11 @@ static const struct drm_driver amdgpu_kms_driver = {</div><div class='ctx'> 	    DRIVER_SYNCOBJ_TIMELINE,</div><div class='ctx'> 	.open = amdgpu_driver_open_kms,</div><div class='ctx'> 	.postclose = amdgpu_driver_postclose_kms,</div><div class='del'>-	.lastclose = amdgpu_driver_lastclose_kms,</div><div class='ctx'> 	.ioctls = amdgpu_ioctls_kms,</div><div class='ctx'> 	.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),</div><div class='ctx'> 	.dumb_create = amdgpu_mode_dumb_create,</div><div class='ctx'> 	.dumb_map_offset = amdgpu_mode_dumb_mmap,</div><div class='add'>+	DRM_FBDEV_TTM_DRIVER_OPS,</div><div class='ctx'> 	.fops = &amp;amdgpu_driver_kms_fops,</div><div class='ctx'> 	.release = &amp;amdgpu_driver_release_kms,</div><div class='ctx'> #ifdef CONFIG_PROC_FS</div><div class='hunk'>@@ -2930,7 +3096,6 @@ static const struct drm_driver amdgpu_kms_driver = {</div><div class='ctx'> </div><div class='ctx'> 	.name = DRIVER_NAME,</div><div class='ctx'> 	.desc = DRIVER_DESC,</div><div class='del'>-	.date = DRIVER_DATE,</div><div class='ctx'> 	.major = KMS_DRIVER_MAJOR,</div><div class='ctx'> 	.minor = KMS_DRIVER_MINOR,</div><div class='ctx'> 	.patchlevel = KMS_DRIVER_PATCHLEVEL,</div><div class='hunk'>@@ -2942,11 +3107,11 @@ const struct drm_driver amdgpu_partition_driver = {</div><div class='ctx'> 	    DRIVER_SYNCOBJ_TIMELINE,</div><div class='ctx'> 	.open = amdgpu_driver_open_kms,</div><div class='ctx'> 	.postclose = amdgpu_driver_postclose_kms,</div><div class='del'>-	.lastclose = amdgpu_driver_lastclose_kms,</div><div class='ctx'> 	.ioctls = amdgpu_ioctls_kms,</div><div class='ctx'> 	.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),</div><div class='ctx'> 	.dumb_create = amdgpu_mode_dumb_create,</div><div class='ctx'> 	.dumb_map_offset = amdgpu_mode_dumb_mmap,</div><div class='add'>+	DRM_FBDEV_TTM_DRIVER_OPS,</div><div class='ctx'> 	.fops = &amp;amdgpu_driver_kms_fops,</div><div class='ctx'> 	.release = &amp;amdgpu_driver_release_kms,</div><div class='ctx'> </div><div class='hunk'>@@ -2954,7 +3119,6 @@ const struct drm_driver amdgpu_partition_driver = {</div><div class='ctx'> </div><div class='ctx'> 	.name = DRIVER_NAME,</div><div class='ctx'> 	.desc = DRIVER_DESC,</div><div class='del'>-	.date = DRIVER_DATE,</div><div class='ctx'> 	.major = KMS_DRIVER_MAJOR,</div><div class='ctx'> 	.minor = KMS_DRIVER_MINOR,</div><div class='ctx'> 	.patchlevel = KMS_DRIVER_PATCHLEVEL,</div><div class='hunk'>@@ -2980,7 +3144,7 @@ static struct pci_driver amdgpu_kms_pci_driver = {</div><div class='ctx'> 	.probe = amdgpu_pci_probe,</div><div class='ctx'> 	.remove = amdgpu_pci_remove,</div><div class='ctx'> 	.shutdown = amdgpu_pci_shutdown,</div><div class='del'>-	.driver.pm = &amp;amdgpu_pm_ops,</div><div class='add'>+	.driver.pm = pm_ptr(&amp;amdgpu_pm_ops),</div><div class='ctx'> 	.err_handler = &amp;amdgpu_pci_err_handler,</div><div class='ctx'> 	.dev_groups = amdgpu_sysfs_groups,</div><div class='ctx'> };</div><div class='hunk'>@@ -2989,14 +3153,11 @@ static int __init amdgpu_init(void)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (drm_firmware_drivers_only())</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 	r = amdgpu_sync_init();</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error_sync;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_fence_slab_init();</div><div class='add'>+	r = amdgpu_userq_fence_slab_init();</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error_fence;</div><div class='ctx'> </div><div class='hunk'>@@ -3007,6 +3168,12 @@ static int __init amdgpu_init(void)</div><div class='ctx'> 	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */</div><div class='ctx'> 	amdgpu_amdkfd_init();</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_pp_feature_mask &amp; PP_OVERDRIVE_MASK) {</div><div class='add'>+		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);</div><div class='add'>+		pr_crit("Overdrive is enabled, please disable it before "</div><div class='add'>+			"reporting any bugs unrelated to overdrive.\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* let modprobe override vga console setting */</div><div class='ctx'> 	return pci_register_driver(&amp;amdgpu_kms_pci_driver);</div><div class='ctx'> </div><div class='hunk'>@@ -3024,7 +3191,7 @@ static void __exit amdgpu_exit(void)</div><div class='ctx'> 	amdgpu_unregister_atpx_handler();</div><div class='ctx'> 	amdgpu_acpi_release();</div><div class='ctx'> 	amdgpu_sync_fini();</div><div class='del'>-	amdgpu_fence_slab_fini();</div><div class='add'>+	amdgpu_userq_fence_slab_fini();</div><div class='ctx'> 	mmu_notifier_synchronize();</div><div class='ctx'> 	amdgpu_xcp_drv_release();</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h<br/>index 5bc2cb661af7..2d86cc6f7f4d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h</a></div><div class='hunk'>@@ -40,7 +40,6 @@</div><div class='ctx'> </div><div class='ctx'> #define DRIVER_NAME		"amdgpu"</div><div class='ctx'> #define DRIVER_DESC		"AMD GPU"</div><div class='del'>-#define DRIVER_DATE		"20150101"</div><div class='ctx'> </div><div class='ctx'> extern const struct drm_driver amdgpu_partition_driver;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c<br/>index e71768661ca8..8cd69836dd99 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c</a></div><div class='hunk'>@@ -90,7 +90,7 @@</div><div class='ctx'> #define MAKE_I2C_ADDR(_aa) ((0xA &lt;&lt; 3) | (((_aa) &gt;&gt; 16) &amp; 0xF))</div><div class='ctx'> </div><div class='ctx'> static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,</div><div class='del'>-				u8 *eeprom_buf, u16 buf_size, bool read)</div><div class='add'>+				u8 *eeprom_buf, u32 buf_size, bool read)</div><div class='ctx'> {</div><div class='ctx'> 	u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];</div><div class='ctx'> 	struct i2c_msg msgs[] = {</div><div class='hunk'>@@ -133,15 +133,15 @@ static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,</div><div class='ctx'> 			 * cycle begins. This is implied for the</div><div class='ctx'> 			 * "i2c_transfer()" abstraction.</div><div class='ctx'> 			 */</div><div class='del'>-			len = min(EEPROM_PAGE_SIZE - (eeprom_addr &amp;</div><div class='del'>-						      EEPROM_PAGE_MASK),</div><div class='del'>-				  (u32)buf_size);</div><div class='add'>+			len = min(EEPROM_PAGE_SIZE - (eeprom_addr &amp; EEPROM_PAGE_MASK),</div><div class='add'>+					buf_size);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* Reading from the EEPROM has no limitation</div><div class='ctx'> 			 * on the number of bytes read from the EEPROM</div><div class='ctx'> 			 * device--they are simply sequenced out.</div><div class='add'>+			 * Keep in mind that i2c_msg.len is u16 type.</div><div class='ctx'> 			 */</div><div class='del'>-			len = buf_size;</div><div class='add'>+			len = min(U16_MAX, buf_size);</div><div class='ctx'> 		}</div><div class='ctx'> 		msgs[1].len = len;</div><div class='ctx'> 		msgs[1].buf = eeprom_buf;</div><div class='hunk'>@@ -179,7 +179,7 @@ static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,</div><div class='ctx'>  * Returns the number of bytes read/written; -errno on error.</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,</div><div class='del'>-			      u8 *eeprom_buf, u16 buf_size, bool read)</div><div class='add'>+			      u8 *eeprom_buf, u32 buf_size, bool read)</div><div class='ctx'> {</div><div class='ctx'> 	const struct i2c_adapter_quirks *quirks = i2c_adap-&gt;quirks;</div><div class='ctx'> 	u16 limit;</div><div class='hunk'>@@ -200,7 +200,7 @@ static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,</div><div class='ctx'> 		dev_err_ratelimited(&amp;i2c_adap-&gt;dev,</div><div class='ctx'> 				    "maddr:0x%04X size:0x%02X:quirk max_%s_len must be &gt; %d",</div><div class='ctx'> 				    eeprom_addr, buf_size,</div><div class='del'>-				    read ? "read" : "write", EEPROM_OFFSET_SIZE);</div><div class='add'>+				    str_read_write(read), EEPROM_OFFSET_SIZE);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -225,7 +225,7 @@ static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,</div><div class='ctx'> </div><div class='ctx'> int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,</div><div class='ctx'> 		       u32 eeprom_addr, u8 *eeprom_buf,</div><div class='del'>-		       u16 bytes)</div><div class='add'>+		       u32 bytes)</div><div class='ctx'> {</div><div class='ctx'> 	return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,</div><div class='ctx'> 				  true);</div><div class='hunk'>@@ -233,7 +233,7 @@ int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,</div><div class='ctx'> </div><div class='ctx'> int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,</div><div class='ctx'> 			u32 eeprom_addr, u8 *eeprom_buf,</div><div class='del'>-			u16 bytes)</div><div class='add'>+			u32 bytes)</div><div class='ctx'> {</div><div class='ctx'> 	return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,</div><div class='ctx'> 				  false);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h<br/>index 6935adb2be1f..8083b8253ef4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.h</a></div><div class='hunk'>@@ -28,10 +28,10 @@</div><div class='ctx'> </div><div class='ctx'> int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,</div><div class='ctx'> 		       u32 eeprom_addr, u8 *eeprom_buf,</div><div class='del'>-		       u16 bytes);</div><div class='add'>+		       u32 bytes);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,</div><div class='ctx'> 			u32 eeprom_addr, u8 *eeprom_buf,</div><div class='del'>-			u16 bytes);</div><div class='add'>+			u32 bytes);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c<br/>new file mode 100644<br/>index 000000000000..23d7d0b0d625<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c</a></div><div class='hunk'>@@ -0,0 +1,241 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/sched.h&gt;</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+</div><div class='add'>+#define work_to_evf_mgr(w, name) container_of(w, struct amdgpu_eviction_fence_mgr, name)</div><div class='add'>+#define evf_mgr_to_fpriv(e) container_of(e, struct amdgpu_fpriv, evf_mgr)</div><div class='add'>+</div><div class='add'>+static const char *</div><div class='add'>+amdgpu_eviction_fence_get_driver_name(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return "amdgpu_eviction_fence";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *</div><div class='add'>+amdgpu_eviction_fence_get_timeline_name(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence *ef;</div><div class='add'>+</div><div class='add'>+	ef = container_of(f, struct amdgpu_eviction_fence, base);</div><div class='add'>+	return ef-&gt;timeline_name;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int</div><div class='add'>+amdgpu_eviction_fence_replace_fence(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+				    struct drm_exec *exec)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence *old_ef, *new_ef;</div><div class='add'>+	struct drm_gem_object *obj;</div><div class='add'>+	unsigned long index;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (evf_mgr-&gt;ev_fence &amp;&amp;</div><div class='add'>+	    !dma_fence_is_signaled(&amp;evf_mgr-&gt;ev_fence-&gt;base))</div><div class='add'>+		return 0;</div><div class='add'>+	/*</div><div class='add'>+	 * Steps to replace eviction fence:</div><div class='add'>+	 * * lock all objects in exec (caller)</div><div class='add'>+	 * * create a new eviction fence</div><div class='add'>+	 * * update new eviction fence in evf_mgr</div><div class='add'>+	 * * attach the new eviction fence to BOs</div><div class='add'>+	 * * release the old fence</div><div class='add'>+	 * * unlock the objects (caller)</div><div class='add'>+	 */</div><div class='add'>+	new_ef = amdgpu_eviction_fence_create(evf_mgr);</div><div class='add'>+	if (!new_ef) {</div><div class='add'>+		DRM_ERROR("Failed to create new eviction fence\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update the eviction fence now */</div><div class='add'>+	spin_lock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	old_ef = evf_mgr-&gt;ev_fence;</div><div class='add'>+	evf_mgr-&gt;ev_fence = new_ef;</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+</div><div class='add'>+	/* Attach the new fence */</div><div class='add'>+	drm_exec_for_each_locked_object(exec, index, obj) {</div><div class='add'>+		struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);</div><div class='add'>+</div><div class='add'>+		if (!bo)</div><div class='add'>+			continue;</div><div class='add'>+		ret = amdgpu_eviction_fence_attach(evf_mgr, bo);</div><div class='add'>+		if (ret) {</div><div class='add'>+			DRM_ERROR("Failed to attch new eviction fence\n");</div><div class='add'>+			goto free_err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Free old fence */</div><div class='add'>+	if (old_ef)</div><div class='add'>+		dma_fence_put(&amp;old_ef-&gt;base);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_err:</div><div class='add'>+	kfree(new_ef);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+amdgpu_eviction_fence_suspend_worker(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence_mgr *evf_mgr = work_to_evf_mgr(work, suspend_work.work);</div><div class='add'>+	struct amdgpu_fpriv *fpriv = evf_mgr_to_fpriv(evf_mgr);</div><div class='add'>+	struct amdgpu_userq_mgr *uq_mgr = &amp;fpriv-&gt;userq_mgr;</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+	spin_lock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	ev_fence = evf_mgr-&gt;ev_fence;</div><div class='add'>+	if (ev_fence)</div><div class='add'>+		dma_fence_get(&amp;ev_fence-&gt;base);</div><div class='add'>+	else</div><div class='add'>+		goto unlock;</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+</div><div class='add'>+	amdgpu_userq_evict(uq_mgr, ev_fence);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+	dma_fence_put(&amp;ev_fence-&gt;base);</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence_mgr *evf_mgr;</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+</div><div class='add'>+	if (!f)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	ev_fence = to_ev_fence(f);</div><div class='add'>+	evf_mgr = ev_fence-&gt;evf_mgr;</div><div class='add'>+</div><div class='add'>+	schedule_delayed_work(&amp;evf_mgr-&gt;suspend_work, 0);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops amdgpu_eviction_fence_ops = {</div><div class='add'>+	.get_driver_name = amdgpu_eviction_fence_get_driver_name,</div><div class='add'>+	.get_timeline_name = amdgpu_eviction_fence_get_timeline_name,</div><div class='add'>+	.enable_signaling = amdgpu_eviction_fence_enable_signaling,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void amdgpu_eviction_fence_signal(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+				  struct amdgpu_eviction_fence *ev_fence)</div><div class='add'>+{</div><div class='add'>+	spin_lock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	dma_fence_signal(&amp;ev_fence-&gt;base);</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct amdgpu_eviction_fence *</div><div class='add'>+amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+</div><div class='add'>+	ev_fence = kzalloc(sizeof(*ev_fence), GFP_KERNEL);</div><div class='add'>+	if (!ev_fence)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	ev_fence-&gt;evf_mgr = evf_mgr;</div><div class='add'>+	get_task_comm(ev_fence-&gt;timeline_name, current);</div><div class='add'>+	spin_lock_init(&amp;ev_fence-&gt;lock);</div><div class='add'>+	dma_fence_init64(&amp;ev_fence-&gt;base, &amp;amdgpu_eviction_fence_ops,</div><div class='add'>+			 &amp;ev_fence-&gt;lock, evf_mgr-&gt;ev_fence_ctx,</div><div class='add'>+			 atomic_inc_return(&amp;evf_mgr-&gt;ev_fence_seq));</div><div class='add'>+	return ev_fence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_eviction_fence_destroy(struct amdgpu_eviction_fence_mgr *evf_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+</div><div class='add'>+	/* Wait for any pending work to execute */</div><div class='add'>+	flush_delayed_work(&amp;evf_mgr-&gt;suspend_work);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	ev_fence = evf_mgr-&gt;ev_fence;</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+</div><div class='add'>+	if (!ev_fence)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dma_fence_wait(&amp;ev_fence-&gt;base, false);</div><div class='add'>+</div><div class='add'>+	/* Last unref of ev_fence */</div><div class='add'>+	dma_fence_put(&amp;ev_fence-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+				 struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+	struct dma_resv *resv = bo-&gt;tbo.base.resv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!resv)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = dma_resv_reserve_fences(resv, 1);</div><div class='add'>+	if (ret) {</div><div class='add'>+		DRM_DEBUG_DRIVER("Failed to resv fence space\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	ev_fence = evf_mgr-&gt;ev_fence;</div><div class='add'>+	if (ev_fence)</div><div class='add'>+		dma_resv_add_fence(resv, &amp;ev_fence-&gt;base, DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+				  struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *stub = dma_fence_get_stub();</div><div class='add'>+</div><div class='add'>+	dma_resv_replace_fences(bo-&gt;tbo.base.resv, evf_mgr-&gt;ev_fence_ctx,</div><div class='add'>+				stub, DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	dma_fence_put(stub);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_eviction_fence_init(struct amdgpu_eviction_fence_mgr *evf_mgr)</div><div class='add'>+{</div><div class='add'>+	/* This needs to be done one time per open */</div><div class='add'>+	atomic_set(&amp;evf_mgr-&gt;ev_fence_seq, 0);</div><div class='add'>+	evf_mgr-&gt;ev_fence_ctx = dma_fence_context_alloc(1);</div><div class='add'>+	spin_lock_init(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+</div><div class='add'>+	INIT_DELAYED_WORK(&amp;evf_mgr-&gt;suspend_work, amdgpu_eviction_fence_suspend_worker);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h<br/>new file mode 100644<br/>index 000000000000..fcd867b7147d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h</a></div><div class='hunk'>@@ -0,0 +1,69 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef AMDGPU_EV_FENCE_H_</div><div class='add'>+#define AMDGPU_EV_FENCE_H_</div><div class='add'>+</div><div class='add'>+struct amdgpu_eviction_fence {</div><div class='add'>+	struct dma_fence base;</div><div class='add'>+	spinlock_t	 lock;</div><div class='add'>+	char		 timeline_name[TASK_COMM_LEN];</div><div class='add'>+	struct amdgpu_eviction_fence_mgr *evf_mgr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_eviction_fence_mgr {</div><div class='add'>+	u64			ev_fence_ctx;</div><div class='add'>+	atomic_t		ev_fence_seq;</div><div class='add'>+	spinlock_t		ev_fence_lock;</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+	struct delayed_work	suspend_work;</div><div class='add'>+	uint8_t fd_closing;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Eviction fence helper functions */</div><div class='add'>+struct amdgpu_eviction_fence *</div><div class='add'>+amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr);</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_eviction_fence_destroy(struct amdgpu_eviction_fence_mgr *evf_mgr);</div><div class='add'>+</div><div class='add'>+int</div><div class='add'>+amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+			     struct amdgpu_bo *bo);</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+			     struct amdgpu_bo *bo);</div><div class='add'>+</div><div class='add'>+int</div><div class='add'>+amdgpu_eviction_fence_init(struct amdgpu_eviction_fence_mgr *evf_mgr);</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_eviction_fence_signal(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+			     struct amdgpu_eviction_fence *ev_fence);</div><div class='add'>+</div><div class='add'>+int</div><div class='add'>+amdgpu_eviction_fence_replace_fence(struct amdgpu_eviction_fence_mgr *evf_mgr,</div><div class='add'>+				    struct drm_exec *exec);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c<br/>index c7df7fa3459f..b349bb3676d5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='ctx'> #include &lt;drm/drm_debugfs.h&gt;</div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/drm_file.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_vm.h"</div><div class='hunk'>@@ -59,20 +60,21 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file)</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv = file-&gt;driver_priv;</div><div class='ctx'> 	struct amdgpu_vm *vm = &amp;fpriv-&gt;vm;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_mem_stats stats;</div><div class='add'>+	struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM];</div><div class='ctx'> 	ktime_t usage[AMDGPU_HW_IP_NUM];</div><div class='del'>-	unsigned int hw_ip;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	memset(&amp;stats, 0, sizeof(stats));</div><div class='del'>-</div><div class='del'>-	ret = amdgpu_bo_reserve(vm-&gt;root.bo, false);</div><div class='del'>-	if (ret)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	amdgpu_vm_get_memory(vm, &amp;stats);</div><div class='del'>-	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+	const char *pl_name[] = {</div><div class='add'>+		[TTM_PL_VRAM] = "vram",</div><div class='add'>+		[TTM_PL_TT] = "gtt",</div><div class='add'>+		[TTM_PL_SYSTEM] = "cpu",</div><div class='add'>+		[AMDGPU_PL_GDS] = "gds",</div><div class='add'>+		[AMDGPU_PL_GWS] = "gws",</div><div class='add'>+		[AMDGPU_PL_OA] = "oa",</div><div class='add'>+		[AMDGPU_PL_DOORBELL] = "doorbell",</div><div class='add'>+		[AMDGPU_PL_MMIO_REMAP] = "mmioremap",</div><div class='add'>+	};</div><div class='add'>+	unsigned int hw_ip, i;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_get_memory(vm, stats);</div><div class='ctx'> 	amdgpu_ctx_mgr_usage(&amp;fpriv-&gt;ctx_mgr, usage);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -82,24 +84,35 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file)</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	drm_printf(p, "pasid:\t%u\n", fpriv-&gt;vm.pasid);</div><div class='del'>-	drm_printf(p, "drm-memory-vram:\t%llu KiB\n", stats.vram/1024UL);</div><div class='del'>-	drm_printf(p, "drm-memory-gtt: \t%llu KiB\n", stats.gtt/1024UL);</div><div class='del'>-	drm_printf(p, "drm-memory-cpu: \t%llu KiB\n", stats.cpu/1024UL);</div><div class='del'>-	drm_printf(p, "amd-memory-visible-vram:\t%llu KiB\n",</div><div class='del'>-		   stats.visible_vram/1024UL);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(pl_name); i++) {</div><div class='add'>+		if (!pl_name[i])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		drm_print_memory_stats(p,</div><div class='add'>+				       &amp;stats[i].drm,</div><div class='add'>+				       DRM_GEM_OBJECT_RESIDENT |</div><div class='add'>+				       DRM_GEM_OBJECT_PURGEABLE,</div><div class='add'>+				       pl_name[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Legacy amdgpu keys, alias to drm-resident-memory-: */</div><div class='add'>+	drm_printf(p, "drm-memory-vram:\t%llu KiB\n",</div><div class='add'>+		   stats[TTM_PL_VRAM].drm.resident/1024UL);</div><div class='add'>+	drm_printf(p, "drm-memory-gtt: \t%llu KiB\n",</div><div class='add'>+		   stats[TTM_PL_TT].drm.resident/1024UL);</div><div class='add'>+	drm_printf(p, "drm-memory-cpu: \t%llu KiB\n",</div><div class='add'>+		   stats[TTM_PL_SYSTEM].drm.resident/1024UL);</div><div class='add'>+</div><div class='add'>+	/* Amdgpu specific memory accounting keys: */</div><div class='ctx'> 	drm_printf(p, "amd-evicted-vram:\t%llu KiB\n",</div><div class='del'>-		   stats.evicted_vram/1024UL);</div><div class='del'>-	drm_printf(p, "amd-evicted-visible-vram:\t%llu KiB\n",</div><div class='del'>-		   stats.evicted_visible_vram/1024UL);</div><div class='add'>+		   stats[TTM_PL_VRAM].evicted/1024UL);</div><div class='ctx'> 	drm_printf(p, "amd-requested-vram:\t%llu KiB\n",</div><div class='del'>-		   stats.requested_vram/1024UL);</div><div class='del'>-	drm_printf(p, "amd-requested-visible-vram:\t%llu KiB\n",</div><div class='del'>-		   stats.requested_visible_vram/1024UL);</div><div class='add'>+		   (stats[TTM_PL_VRAM].drm.shared +</div><div class='add'>+		    stats[TTM_PL_VRAM].drm.private) / 1024UL);</div><div class='ctx'> 	drm_printf(p, "amd-requested-gtt:\t%llu KiB\n",</div><div class='del'>-		   stats.requested_gtt/1024UL);</div><div class='del'>-	drm_printf(p, "drm-shared-vram:\t%llu KiB\n", stats.vram_shared/1024UL);</div><div class='del'>-	drm_printf(p, "drm-shared-gtt:\t%llu KiB\n", stats.gtt_shared/1024UL);</div><div class='del'>-	drm_printf(p, "drm-shared-cpu:\t%llu KiB\n", stats.cpu_shared/1024UL);</div><div class='add'>+		   (stats[TTM_PL_TT].drm.shared +</div><div class='add'>+		    stats[TTM_PL_TT].drm.private) / 1024UL);</div><div class='ctx'> </div><div class='ctx'> 	for (hw_ip = 0; hw_ip &lt; AMDGPU_HW_IP_NUM; ++hw_ip) {</div><div class='ctx'> 		if (!usage[hw_ip])</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c<br/>index 10832b470448..c7843e336310 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c</a></div><div class='hunk'>@@ -42,50 +42,14 @@</div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Fences mark an event in the GPUs pipeline and are used</div><div class='del'>- * for GPU/CPU synchronization.  When the fence is written,</div><div class='del'>- * it is expected that all buffers associated with that fence</div><div class='del'>- * are no longer in use by the associated ring on the GPU and</div><div class='del'>- * that the relevant GPU caches have been flushed.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-struct amdgpu_fence {</div><div class='del'>-	struct dma_fence base;</div><div class='del'>-</div><div class='del'>-	/* RB, DMA, etc. */</div><div class='del'>-	struct amdgpu_ring		*ring;</div><div class='del'>-	ktime_t				start_timestamp;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static struct kmem_cache *amdgpu_fence_slab;</div><div class='del'>-</div><div class='del'>-int amdgpu_fence_slab_init(void)</div><div class='del'>-{</div><div class='del'>-	amdgpu_fence_slab = KMEM_CACHE(amdgpu_fence, SLAB_HWCACHE_ALIGN);</div><div class='del'>-	if (!amdgpu_fence_slab)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void amdgpu_fence_slab_fini(void)</div><div class='del'>-{</div><div class='del'>-	rcu_barrier();</div><div class='del'>-	kmem_cache_destroy(amdgpu_fence_slab);</div><div class='del'>-}</div><div class='del'>-/*</div><div class='ctx'>  * Cast helper</div><div class='ctx'>  */</div><div class='ctx'> static const struct dma_fence_ops amdgpu_fence_ops;</div><div class='del'>-static const struct dma_fence_ops amdgpu_job_fence_ops;</div><div class='ctx'> static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);</div><div class='ctx'> </div><div class='del'>-	if (__f-&gt;base.ops == &amp;amdgpu_fence_ops ||</div><div class='del'>-	    __f-&gt;base.ops == &amp;amdgpu_job_fence_ops)</div><div class='del'>-		return __f;</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='add'>+	return __f;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -129,59 +93,33 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)</div><div class='ctx'>  * amdgpu_fence_emit - emit a fence on the requested ring</div><div class='ctx'>  *</div><div class='ctx'>  * @ring: ring the fence is associated with</div><div class='del'>- * @f: resulting fence object</div><div class='del'>- * @job: job the fence is embedded in</div><div class='add'>+ * @af: amdgpu fence input</div><div class='ctx'>  * @flags: flags to pass into the subordinate .emit_fence() call</div><div class='ctx'>  *</div><div class='ctx'>  * Emits a fence command on the requested ring (all asics).</div><div class='ctx'>  * Returns 0 on success, -ENOMEM on failure.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,</div><div class='add'>+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,</div><div class='ctx'> 		      unsigned int flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct dma_fence *fence;</div><div class='del'>-	struct amdgpu_fence *am_fence;</div><div class='ctx'> 	struct dma_fence __rcu **ptr;</div><div class='ctx'> 	uint32_t seq;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (job == NULL) {</div><div class='del'>-		/* create a sperate hw fence */</div><div class='del'>-		am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);</div><div class='del'>-		if (am_fence == NULL)</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-		fence = &amp;am_fence-&gt;base;</div><div class='del'>-		am_fence-&gt;ring = ring;</div><div class='del'>-	} else {</div><div class='del'>-		/* take use of job-embedded fence */</div><div class='del'>-		fence = &amp;job-&gt;hw_fence;</div><div class='del'>-	}</div><div class='add'>+	fence = &amp;af-&gt;base;</div><div class='add'>+	af-&gt;ring = ring;</div><div class='ctx'> </div><div class='ctx'> 	seq = ++ring-&gt;fence_drv.sync_seq;</div><div class='del'>-	if (job &amp;&amp; job-&gt;job_run_counter) {</div><div class='del'>-		/* reinit seq for resubmitted jobs */</div><div class='del'>-		fence-&gt;seqno = seq;</div><div class='del'>-		/* TO be inline with external fence creation and other drivers */</div><div class='del'>-		dma_fence_get(fence);</div><div class='del'>-	} else {</div><div class='del'>-		if (job) {</div><div class='del'>-			dma_fence_init(fence, &amp;amdgpu_job_fence_ops,</div><div class='del'>-				       &amp;ring-&gt;fence_drv.lock,</div><div class='del'>-				       adev-&gt;fence_context + ring-&gt;idx, seq);</div><div class='del'>-			/* Against remove in amdgpu_job_{free, free_cb} */</div><div class='del'>-			dma_fence_get(fence);</div><div class='del'>-		} else {</div><div class='del'>-			dma_fence_init(fence, &amp;amdgpu_fence_ops,</div><div class='del'>-				       &amp;ring-&gt;fence_drv.lock,</div><div class='del'>-				       adev-&gt;fence_context + ring-&gt;idx, seq);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	dma_fence_init(fence, &amp;amdgpu_fence_ops,</div><div class='add'>+		       &amp;ring-&gt;fence_drv.lock,</div><div class='add'>+		       adev-&gt;fence_context + ring-&gt;idx, seq);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_emit_fence(ring, ring-&gt;fence_drv.gpu_addr,</div><div class='ctx'> 			       seq, flags | AMDGPU_FENCE_FLAG_INT);</div><div class='add'>+	amdgpu_fence_save_wptr(af);</div><div class='ctx'> 	pm_runtime_get_noresume(adev_to_drm(adev)-&gt;dev);</div><div class='del'>-	trace_amdgpu_runpm_reference_dumps(1, __func__);</div><div class='ctx'> 	ptr = &amp;ring-&gt;fence_drv.fences[seq &amp; ring-&gt;fence_drv.num_fences_mask];</div><div class='ctx'> 	if (unlikely(rcu_dereference_protected(*ptr, 1))) {</div><div class='ctx'> 		struct dma_fence *old;</div><div class='hunk'>@@ -205,8 +143,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd</div><div class='ctx'> 	 */</div><div class='ctx'> 	rcu_assign_pointer(*ptr, dma_fence_get(fence));</div><div class='ctx'> </div><div class='del'>-	*f = fence;</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -281,7 +217,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> 	} while (atomic_cmpxchg(&amp;drv-&gt;last_seq, last_seq, seq) != last_seq);</div><div class='ctx'> </div><div class='del'>-	if (del_timer(&amp;ring-&gt;fence_drv.fallback_timer) &amp;&amp;</div><div class='add'>+	if (timer_delete(&amp;ring-&gt;fence_drv.fallback_timer) &amp;&amp;</div><div class='ctx'> 	    seq != ring-&gt;fence_drv.sync_seq)</div><div class='ctx'> 		amdgpu_fence_schedule_fallback(ring);</div><div class='ctx'> </div><div class='hunk'>@@ -293,6 +229,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		struct dma_fence *fence, **ptr;</div><div class='add'>+		struct amdgpu_fence *am_fence;</div><div class='ctx'> </div><div class='ctx'> 		++last_seq;</div><div class='ctx'> 		last_seq &amp;= drv-&gt;num_fences_mask;</div><div class='hunk'>@@ -305,11 +242,15 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)</div><div class='ctx'> 		if (!fence)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		/* Save the wptr in the fence driver so we know what the last processed</div><div class='add'>+		 * wptr was.  This is required for re-emitting the ring state for</div><div class='add'>+		 * queues that are reset but are not guilty and thus have no guilty fence.</div><div class='add'>+		 */</div><div class='add'>+		am_fence = container_of(fence, struct amdgpu_fence, base);</div><div class='add'>+		drv-&gt;signalled_wptr = am_fence-&gt;wptr;</div><div class='ctx'> 		dma_fence_signal(fence);</div><div class='ctx'> 		dma_fence_put(fence);</div><div class='del'>-		pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 		pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='del'>-		trace_amdgpu_runpm_reference_dumps(0, __func__);</div><div class='ctx'> 	} while (last_seq != seq);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -324,11 +265,13 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_fence_fallback(struct timer_list *t)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = from_timer(ring, t,</div><div class='del'>-					      fence_drv.fallback_timer);</div><div class='add'>+	struct amdgpu_ring *ring = timer_container_of(ring, t,</div><div class='add'>+						      fence_drv.fallback_timer);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_fence_process(ring))</div><div class='del'>-		DRM_WARN("Fence fallback timer expired on ring %s\n", ring-&gt;name);</div><div class='add'>+		dev_warn(ring-&gt;adev-&gt;dev,</div><div class='add'>+			 "Fence fallback timer expired on ring %s\n",</div><div class='add'>+			 ring-&gt;name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -620,7 +563,7 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_irq_put(adev, ring-&gt;fence_drv.irq_src,</div><div class='ctx'> 				       ring-&gt;fence_drv.irq_type);</div><div class='ctx'> </div><div class='del'>-		del_timer_sync(&amp;ring-&gt;fence_drv.fallback_timer);</div><div class='add'>+		timer_delete_sync(&amp;ring-&gt;fence_drv.fallback_timer);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -700,36 +643,6 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring</div><div class='del'>- *</div><div class='del'>- * @ring: fence of the ring to be cleared</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct dma_fence *old, **ptr;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt;= ring-&gt;fence_drv.num_fences_mask; i++) {</div><div class='del'>-		ptr = &amp;ring-&gt;fence_drv.fences[i];</div><div class='del'>-		old = rcu_dereference_protected(*ptr, 1);</div><div class='del'>-		if (old &amp;&amp; old-&gt;ops == &amp;amdgpu_job_fence_ops) {</div><div class='del'>-			struct amdgpu_job *job;</div><div class='del'>-</div><div class='del'>-			/* For non-scheduler bad job, i.e. failed ib test, we need to signal</div><div class='del'>-			 * it right here or we won't be able to track them in fence_drv</div><div class='del'>-			 * and they will remain unsignaled during sa_bo free.</div><div class='del'>-			 */</div><div class='del'>-			job = container_of(old, struct amdgpu_job, hw_fence);</div><div class='del'>-			if (!job-&gt;base.s_fence &amp;&amp; !dma_fence_is_signaled(old))</div><div class='del'>-				dma_fence_signal(old);</div><div class='del'>-			RCU_INIT_POINTER(*ptr, NULL);</div><div class='del'>-			dma_fence_put(old);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * amdgpu_fence_driver_set_error - set error code on fences</div><div class='ctx'>  * @ring: the ring which contains the fences</div><div class='ctx'>  * @error: the error code to set</div><div class='hunk'>@@ -766,6 +679,120 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_fence_process(ring);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Kernel queue reset handling</div><div class='add'>+ *</div><div class='add'>+ * The driver can reset individual queues for most engines, but those queues</div><div class='add'>+ * may contain work from multiple contexts.  Resetting the queue will reset</div><div class='add'>+ * lose all of that state.  In order to minimize the collateral damage, the</div><div class='add'>+ * driver will save the ring contents which are not associated with the guilty</div><div class='add'>+ * context prior to resetting the queue.  After resetting the queue the queue</div><div class='add'>+ * contents from the other contexts is re-emitted to the rings so that it can</div><div class='add'>+ * be processed by the engine.  To handle this, we save the queue's write</div><div class='add'>+ * pointer (wptr) in the fences associated with each context.  If we get a</div><div class='add'>+ * queue timeout, we can then use the wptrs from the fences to determine</div><div class='add'>+ * which data needs to be saved out of the queue's ring buffer.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_fence_driver_guilty_force_completion - force signal of specified sequence</div><div class='add'>+ *</div><div class='add'>+ * @af: fence of the ring to signal</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *unprocessed;</div><div class='add'>+	struct dma_fence __rcu **ptr;</div><div class='add'>+	struct amdgpu_fence *fence;</div><div class='add'>+	struct amdgpu_ring *ring = af-&gt;ring;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u32 seq, last_seq;</div><div class='add'>+</div><div class='add'>+	last_seq = amdgpu_fence_read(ring) &amp; ring-&gt;fence_drv.num_fences_mask;</div><div class='add'>+	seq = ring-&gt;fence_drv.sync_seq &amp; ring-&gt;fence_drv.num_fences_mask;</div><div class='add'>+</div><div class='add'>+	/* mark all fences from the guilty context with an error */</div><div class='add'>+	spin_lock_irqsave(&amp;ring-&gt;fence_drv.lock, flags);</div><div class='add'>+	do {</div><div class='add'>+		last_seq++;</div><div class='add'>+		last_seq &amp;= ring-&gt;fence_drv.num_fences_mask;</div><div class='add'>+</div><div class='add'>+		ptr = &amp;ring-&gt;fence_drv.fences[last_seq];</div><div class='add'>+		rcu_read_lock();</div><div class='add'>+		unprocessed = rcu_dereference(*ptr);</div><div class='add'>+</div><div class='add'>+		if (unprocessed &amp;&amp; !dma_fence_is_signaled_locked(unprocessed)) {</div><div class='add'>+			fence = container_of(unprocessed, struct amdgpu_fence, base);</div><div class='add'>+</div><div class='add'>+			if (fence == af)</div><div class='add'>+				dma_fence_set_error(&amp;fence-&gt;base, -ETIME);</div><div class='add'>+			else if (fence-&gt;context == af-&gt;context)</div><div class='add'>+				dma_fence_set_error(&amp;fence-&gt;base, -ECANCELED);</div><div class='add'>+		}</div><div class='add'>+		rcu_read_unlock();</div><div class='add'>+	} while (last_seq != seq);</div><div class='add'>+	spin_unlock_irqrestore(&amp;ring-&gt;fence_drv.lock, flags);</div><div class='add'>+	/* signal the guilty fence */</div><div class='add'>+	amdgpu_fence_write(ring, (u32)af-&gt;base.seqno);</div><div class='add'>+	amdgpu_fence_process(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_fence_save_wptr(struct amdgpu_fence *af)</div><div class='add'>+{</div><div class='add'>+	af-&gt;wptr = af-&gt;ring-&gt;wptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ring_backup_unprocessed_command(struct amdgpu_ring *ring,</div><div class='add'>+						   u64 start_wptr, u32 end_wptr)</div><div class='add'>+{</div><div class='add'>+	unsigned int first_idx = start_wptr &amp; ring-&gt;buf_mask;</div><div class='add'>+	unsigned int last_idx = end_wptr &amp; ring-&gt;buf_mask;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* Backup the contents of the ring buffer. */</div><div class='add'>+	for (i = first_idx; i != last_idx; ++i, i &amp;= ring-&gt;buf_mask)</div><div class='add'>+		ring-&gt;ring_backup[ring-&gt;ring_backup_entries_to_copy++] = ring-&gt;ring[i];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,</div><div class='add'>+					     struct amdgpu_fence *guilty_fence)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *unprocessed;</div><div class='add'>+	struct dma_fence __rcu **ptr;</div><div class='add'>+	struct amdgpu_fence *fence;</div><div class='add'>+	u64 wptr;</div><div class='add'>+	u32 seq, last_seq;</div><div class='add'>+</div><div class='add'>+	last_seq = amdgpu_fence_read(ring) &amp; ring-&gt;fence_drv.num_fences_mask;</div><div class='add'>+	seq = ring-&gt;fence_drv.sync_seq &amp; ring-&gt;fence_drv.num_fences_mask;</div><div class='add'>+	wptr = ring-&gt;fence_drv.signalled_wptr;</div><div class='add'>+	ring-&gt;ring_backup_entries_to_copy = 0;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		last_seq++;</div><div class='add'>+		last_seq &amp;= ring-&gt;fence_drv.num_fences_mask;</div><div class='add'>+</div><div class='add'>+		ptr = &amp;ring-&gt;fence_drv.fences[last_seq];</div><div class='add'>+		rcu_read_lock();</div><div class='add'>+		unprocessed = rcu_dereference(*ptr);</div><div class='add'>+</div><div class='add'>+		if (unprocessed &amp;&amp; !dma_fence_is_signaled(unprocessed)) {</div><div class='add'>+			fence = container_of(unprocessed, struct amdgpu_fence, base);</div><div class='add'>+</div><div class='add'>+			/* save everything if the ring is not guilty, otherwise</div><div class='add'>+			 * just save the content from other contexts.</div><div class='add'>+			 */</div><div class='add'>+			if (!guilty_fence || (fence-&gt;context != guilty_fence-&gt;context))</div><div class='add'>+				amdgpu_ring_backup_unprocessed_command(ring, wptr,</div><div class='add'>+								       fence-&gt;wptr);</div><div class='add'>+			wptr = fence-&gt;wptr;</div><div class='add'>+		}</div><div class='add'>+		rcu_read_unlock();</div><div class='add'>+	} while (last_seq != seq);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Common fence implementation</div><div class='ctx'>  */</div><div class='hunk'>@@ -780,13 +807,6 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)</div><div class='ctx'> 	return (const char *)to_amdgpu_fence(f)-&gt;ring-&gt;name;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);</div><div class='del'>-</div><div class='del'>-	return (const char *)to_amdgpu_ring(job-&gt;base.sched)-&gt;name;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_fence_enable_signaling - enable signalling on fence</div><div class='ctx'>  * @f: fence</div><div class='hunk'>@@ -804,23 +824,6 @@ static bool amdgpu_fence_enable_signaling(struct dma_fence *f)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_job_fence_enable_signaling - enable signalling on job fence</div><div class='del'>- * @f: fence</div><div class='del'>- *</div><div class='del'>- * This is the simliar function with amdgpu_fence_enable_signaling above, it</div><div class='del'>- * only handles the job embedded fence.</div><div class='del'>- */</div><div class='del'>-static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);</div><div class='del'>-</div><div class='del'>-	if (!timer_pending(&amp;to_amdgpu_ring(job-&gt;base.sched)-&gt;fence_drv.fallback_timer))</div><div class='del'>-		amdgpu_fence_schedule_fallback(to_amdgpu_ring(job-&gt;base.sched));</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * amdgpu_fence_free - free up the fence memory</div><div class='ctx'>  *</div><div class='ctx'>  * @rcu: RCU callback head</div><div class='hunk'>@@ -832,22 +835,7 @@ static void amdgpu_fence_free(struct rcu_head *rcu)</div><div class='ctx'> 	struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);</div><div class='ctx'> </div><div class='ctx'> 	/* free fence_slab if it's separated fence*/</div><div class='del'>-	kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * amdgpu_job_fence_free - free up the job with embedded fence</div><div class='del'>- *</div><div class='del'>- * @rcu: RCU callback head</div><div class='del'>- *</div><div class='del'>- * Free up the job with embedded fence after the RCU grace period.</div><div class='del'>- */</div><div class='del'>-static void amdgpu_job_fence_free(struct rcu_head *rcu)</div><div class='del'>-{</div><div class='del'>-	struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);</div><div class='del'>-</div><div class='del'>-	/* free job if fence has a parent job */</div><div class='del'>-	kfree(container_of(f, struct amdgpu_job, hw_fence));</div><div class='add'>+	kfree(to_amdgpu_fence(f));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -863,19 +851,6 @@ static void amdgpu_fence_release(struct dma_fence *f)</div><div class='ctx'> 	call_rcu(&amp;f-&gt;rcu, amdgpu_fence_free);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_job_fence_release - callback that job embedded fence can be freed</div><div class='del'>- *</div><div class='del'>- * @f: fence</div><div class='del'>- *</div><div class='del'>- * This is the simliar function with amdgpu_fence_release above, it</div><div class='del'>- * only handles the job embedded fence.</div><div class='del'>- */</div><div class='del'>-static void amdgpu_job_fence_release(struct dma_fence *f)</div><div class='del'>-{</div><div class='del'>-	call_rcu(&amp;f-&gt;rcu, amdgpu_job_fence_free);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct dma_fence_ops amdgpu_fence_ops = {</div><div class='ctx'> 	.get_driver_name = amdgpu_fence_get_driver_name,</div><div class='ctx'> 	.get_timeline_name = amdgpu_fence_get_timeline_name,</div><div class='hunk'>@@ -883,13 +858,6 @@ static const struct dma_fence_ops amdgpu_fence_ops = {</div><div class='ctx'> 	.release = amdgpu_fence_release,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dma_fence_ops amdgpu_job_fence_ops = {</div><div class='del'>-	.get_driver_name = amdgpu_fence_get_driver_name,</div><div class='del'>-	.get_timeline_name = amdgpu_job_fence_get_timeline_name,</div><div class='del'>-	.enable_signaling = amdgpu_job_fence_enable_signaling,</div><div class='del'>-	.release = amdgpu_job_fence_release,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * Fence debugfs</div><div class='ctx'>  */</div><div class='hunk'>@@ -959,7 +927,6 @@ static int gpu_recover_get(void *data, u64 *val)</div><div class='ctx'> </div><div class='ctx'> 	*val = atomic_read(&amp;adev-&gt;reset_domain-&gt;reset_res);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -980,7 +947,9 @@ static void amdgpu_debugfs_reset_work(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 	reset_context.reset_req_dev = adev;</div><div class='add'>+	reset_context.src = AMDGPU_RESET_SRC_USER;</div><div class='ctx'> 	set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='add'>+	set_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c<br/>index a08c148b13f9..b0082aa7f3c6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> </div><div class='ctx'> #define FRU_EEPROM_MADDR_6      0x60000</div><div class='ctx'> #define FRU_EEPROM_MADDR_8      0x80000</div><div class='add'>+#define FRU_EEPROM_MADDR_INV    0xFFFFF</div><div class='ctx'> </div><div class='ctx'> static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)</div><div class='ctx'> {</div><div class='hunk'>@@ -63,10 +64,10 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)</div><div class='ctx'> 		switch (adev-&gt;asic_type) {</div><div class='ctx'> 		case CHIP_VEGA20:</div><div class='ctx'> 			/* D161 and D163 are the VG20 server SKUs */</div><div class='del'>-			if (strnstr(atom_ctx-&gt;vbios_pn, "D161",</div><div class='del'>-				    sizeof(atom_ctx-&gt;vbios_pn)) ||</div><div class='del'>-			    strnstr(atom_ctx-&gt;vbios_pn, "D163",</div><div class='del'>-				    sizeof(atom_ctx-&gt;vbios_pn))) {</div><div class='add'>+			if (atom_ctx &amp;&amp; (strnstr(atom_ctx-&gt;vbios_pn, "D161",</div><div class='add'>+						 sizeof(atom_ctx-&gt;vbios_pn)) ||</div><div class='add'>+					 strnstr(atom_ctx-&gt;vbios_pn, "D163",</div><div class='add'>+						 sizeof(atom_ctx-&gt;vbios_pn)))) {</div><div class='ctx'> 				if (fru_addr)</div><div class='ctx'> 					*fru_addr = FRU_EEPROM_MADDR_6;</div><div class='ctx'> 				return true;</div><div class='hunk'>@@ -78,8 +79,8 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> 	case IP_VERSION(11, 0, 7):</div><div class='del'>-		if (strnstr(atom_ctx-&gt;vbios_pn, "D603",</div><div class='del'>-			    sizeof(atom_ctx-&gt;vbios_pn))) {</div><div class='add'>+		if (atom_ctx &amp;&amp; strnstr(atom_ctx-&gt;vbios_pn, "D603",</div><div class='add'>+					sizeof(atom_ctx-&gt;vbios_pn))) {</div><div class='ctx'> 			if (strnstr(atom_ctx-&gt;vbios_pn, "D603GLXE",</div><div class='ctx'> 				    sizeof(atom_ctx-&gt;vbios_pn))) {</div><div class='ctx'> 				return false;</div><div class='hunk'>@@ -94,15 +95,20 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)</div><div class='ctx'> 		}</div><div class='ctx'> 	case IP_VERSION(13, 0, 2):</div><div class='ctx'> 		/* All Aldebaran SKUs have an FRU */</div><div class='del'>-		if (!strnstr(atom_ctx-&gt;vbios_pn, "D673",</div><div class='del'>-			     sizeof(atom_ctx-&gt;vbios_pn)))</div><div class='add'>+		if (atom_ctx &amp;&amp; !strnstr(atom_ctx-&gt;vbios_pn, "D673",</div><div class='add'>+					 sizeof(atom_ctx-&gt;vbios_pn)))</div><div class='ctx'> 			if (fru_addr)</div><div class='ctx'> 				*fru_addr = FRU_EEPROM_MADDR_6;</div><div class='ctx'> 		return true;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 			if (fru_addr)</div><div class='ctx'> 				*fru_addr = FRU_EEPROM_MADDR_8;</div><div class='ctx'> 			return true;</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+			if (fru_addr)</div><div class='add'>+				*fru_addr = FRU_EEPROM_MADDR_INV;</div><div class='add'>+			return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -119,6 +125,10 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!is_fru_eeprom_supported(adev, &amp;fru_addr))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	/* FRU data avaialble, but no direct EEPROM access */</div><div class='add'>+	if (fru_addr == FRU_EEPROM_MADDR_INV)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (!adev-&gt;fru_info) {</div><div class='ctx'> 		adev-&gt;fru_info = kzalloc(sizeof(*adev-&gt;fru_info), GFP_KERNEL);</div><div class='ctx'> 		if (!adev-&gt;fru_info)</div><div class='hunk'>@@ -134,7 +144,8 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	/* If algo exists, it means that the i2c_adapter's initialized */</div><div class='ctx'> 	if (!adev-&gt;pm.fru_eeprom_i2c_bus || !adev-&gt;pm.fru_eeprom_i2c_bus-&gt;algo) {</div><div class='del'>-		DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "Cannot access FRU, EEPROM accessor not initialized");</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -142,19 +153,22 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)</div><div class='ctx'> 	len = amdgpu_eeprom_read(adev-&gt;pm.fru_eeprom_i2c_bus, fru_addr, buf,</div><div class='ctx'> 				 sizeof(buf));</div><div class='ctx'> 	if (len != 8) {</div><div class='del'>-		DRM_ERROR("Couldn't read the IPMI Common Header: %d", len);</div><div class='add'>+		dev_err(adev-&gt;dev, "Couldn't read the IPMI Common Header: %d",</div><div class='add'>+			len);</div><div class='ctx'> 		return len &lt; 0 ? len : -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (buf[0] != 1) {</div><div class='del'>-		DRM_ERROR("Bad IPMI Common Header version: 0x%02x", buf[0]);</div><div class='add'>+		dev_err(adev-&gt;dev, "Bad IPMI Common Header version: 0x%02x",</div><div class='add'>+			buf[0]);</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (csum = 0; len &gt; 0; len--)</div><div class='ctx'> 		csum += buf[len - 1];</div><div class='ctx'> 	if (csum) {</div><div class='del'>-		DRM_ERROR("Bad IPMI Common Header checksum: 0x%02x", csum);</div><div class='add'>+		dev_err(adev-&gt;dev, "Bad IPMI Common Header checksum: 0x%02x",</div><div class='add'>+			csum);</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -169,12 +183,14 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)</div><div class='ctx'> 	/* Read the header of the PIA. */</div><div class='ctx'> 	len = amdgpu_eeprom_read(adev-&gt;pm.fru_eeprom_i2c_bus, addr, buf, 3);</div><div class='ctx'> 	if (len != 3) {</div><div class='del'>-		DRM_ERROR("Couldn't read the Product Info Area header: %d", len);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Couldn't read the Product Info Area header: %d", len);</div><div class='ctx'> 		return len &lt; 0 ? len : -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (buf[0] != 1) {</div><div class='del'>-		DRM_ERROR("Bad IPMI Product Info Area version: 0x%02x", buf[0]);</div><div class='add'>+		dev_err(adev-&gt;dev, "Bad IPMI Product Info Area version: 0x%02x",</div><div class='add'>+			buf[0]);</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -187,14 +203,16 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)</div><div class='ctx'> 	len = amdgpu_eeprom_read(adev-&gt;pm.fru_eeprom_i2c_bus, addr, pia, size);</div><div class='ctx'> 	if (len != size) {</div><div class='ctx'> 		kfree(pia);</div><div class='del'>-		DRM_ERROR("Couldn't read the Product Info Area: %d", len);</div><div class='add'>+		dev_err(adev-&gt;dev, "Couldn't read the Product Info Area: %d",</div><div class='add'>+			len);</div><div class='ctx'> 		return len &lt; 0 ? len : -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (csum = 0; size &gt; 0; size--)</div><div class='ctx'> 		csum += pia[size - 1];</div><div class='ctx'> 	if (csum) {</div><div class='del'>-		DRM_ERROR("Bad Product Info Area checksum: 0x%02x", csum);</div><div class='add'>+		dev_err(adev-&gt;dev, "Bad Product Info Area checksum: 0x%02x",</div><div class='add'>+			csum);</div><div class='ctx'> 		kfree(pia);</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -383,7 +401,7 @@ int amdgpu_fru_sysfs_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> void amdgpu_fru_sysfs_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (!is_fru_eeprom_supported(adev, NULL) || !adev-&gt;fru_info)</div><div class='add'>+	if (!adev-&gt;fru_info)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	sysfs_remove_files(&amp;adev-&gt;dev-&gt;kobj, amdgpu_fru_attributes);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h<br/>index bc58dca18035..98f3196599ef 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h</a></div><div class='hunk'>@@ -32,7 +32,7 @@ struct amdgpu_fru_info {</div><div class='ctx'> 	char				product_name[AMDGPU_PRODUCT_NAME_LEN];</div><div class='ctx'> 	char				serial[20];</div><div class='ctx'> 	char				manufacturer_name[32];</div><div class='del'>-	char				fru_id[32];</div><div class='add'>+	char				fru_id[50];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_fru_get_product_info(struct amdgpu_device *adev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c<br/>index 2d4b67175b55..328a1b963548 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c</a></div><div class='hunk'>@@ -122,6 +122,10 @@ static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 2) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 3))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (adev-&gt;asic_type &gt;= CHIP_SIENNA_CICHLID)</div><div class='ctx'> 		return 1;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c<br/>index c623e23049d1..d2237ce9da70 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> #include &lt;asm/set_memory.h&gt;</div><div class='ctx'> #endif</div><div class='ctx'> #include "amdgpu.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -77,8 +78,9 @@ static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;dummy_page_addr)</div><div class='ctx'> 		return 0;</div><div class='del'>-	adev-&gt;dummy_page_addr = dma_map_page(&amp;adev-&gt;pdev-&gt;dev, dummy_page, 0,</div><div class='del'>-					     PAGE_SIZE, DMA_BIDIRECTIONAL);</div><div class='add'>+	adev-&gt;dummy_page_addr = dma_map_page_attrs(&amp;adev-&gt;pdev-&gt;dev, dummy_page, 0,</div><div class='add'>+							PAGE_SIZE, DMA_BIDIRECTIONAL,</div><div class='add'>+							DMA_ATTR_SKIP_CPU_SYNC);</div><div class='ctx'> 	if (dma_mapping_error(&amp;adev-&gt;pdev-&gt;dev, adev-&gt;dummy_page_addr)) {</div><div class='ctx'> 		dev_err(&amp;adev-&gt;pdev-&gt;dev, "Failed to DMA MAP the dummy page\n");</div><div class='ctx'> 		adev-&gt;dummy_page_addr = 0;</div><div class='hunk'>@@ -98,8 +100,9 @@ void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (!adev-&gt;dummy_page_addr)</div><div class='ctx'> 		return;</div><div class='del'>-	dma_unmap_page(&amp;adev-&gt;pdev-&gt;dev, adev-&gt;dummy_page_addr, PAGE_SIZE,</div><div class='del'>-		       DMA_BIDIRECTIONAL);</div><div class='add'>+	dma_unmap_page_attrs(&amp;adev-&gt;pdev-&gt;dev, adev-&gt;dummy_page_addr, PAGE_SIZE,</div><div class='add'>+				DMA_BIDIRECTIONAL,</div><div class='add'>+				DMA_ATTR_SKIP_CPU_SYNC);</div><div class='ctx'> 	adev-&gt;dummy_page_addr = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -299,7 +302,6 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,</div><div class='ctx'> 			int pages)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned t;</div><div class='del'>-	unsigned p;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	u64 page_base;</div><div class='ctx'> 	/* Starting from VEGA10, system bit must be 0 to mean invalid. */</div><div class='hunk'>@@ -313,8 +315,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	t = offset / AMDGPU_GPU_PAGE_SIZE;</div><div class='del'>-	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;</div><div class='del'>-	for (i = 0; i &lt; pages; i++, p++) {</div><div class='add'>+	for (i = 0; i &lt; pages; i++) {</div><div class='ctx'> 		page_base = adev-&gt;dummy_page_addr;</div><div class='ctx'> 		if (!adev-&gt;gart.ptr)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -325,10 +326,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,</div><div class='ctx'> 			page_base += AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	mb();</div><div class='del'>-	amdgpu_device_flush_hdp(adev, NULL);</div><div class='del'>-	for_each_set_bit(i, adev-&gt;vmhubs_mask, AMDGPU_MAX_VMHUBS)</div><div class='del'>-		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);</div><div class='add'>+	amdgpu_gart_invalidate_tlb(adev);</div><div class='ctx'> </div><div class='ctx'> 	drm_dev_exit(idx);</div><div class='ctx'> }</div><div class='hunk'>@@ -370,6 +368,42 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_gart_map_vram_range - map VRAM pages into the GART page table</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @pa: physical address of the first page to be mapped</div><div class='add'>+ * @start_page: first page to map in the GART aperture</div><div class='add'>+ * @num_pages: number of pages to be mapped</div><div class='add'>+ * @flags: page table entry flags</div><div class='add'>+ * @dst: CPU address of the GART table</div><div class='add'>+ *</div><div class='add'>+ * Binds a BO that is allocated in VRAM to the GART page table</div><div class='add'>+ * (all ASICs).</div><div class='add'>+ *</div><div class='add'>+ * Useful when a kernel BO is located in VRAM but</div><div class='add'>+ * needs to be accessed from the GART address space.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,</div><div class='add'>+				uint64_t start_page, uint64_t num_pages,</div><div class='add'>+				uint64_t flags, void *dst)</div><div class='add'>+{</div><div class='add'>+	u32 i, idx;</div><div class='add'>+</div><div class='add'>+	/* The SYSTEM flag indicates the pages aren't in VRAM. */</div><div class='add'>+	WARN_ON_ONCE(flags &amp; AMDGPU_PTE_SYSTEM);</div><div class='add'>+</div><div class='add'>+	if (!drm_dev_enter(adev_to_drm(adev), &amp;idx))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_pages; ++i) {</div><div class='add'>+		amdgpu_gmc_set_pte_pde(adev, adev-&gt;gart.ptr,</div><div class='add'>+			start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_dev_exit(idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_gart_bind - bind pages into the gart page table</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='hunk'>@@ -408,7 +442,10 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	mb();</div><div class='del'>-	amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+	if (down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='ctx'> 	for_each_set_bit(i, adev-&gt;vmhubs_mask, AMDGPU_MAX_VMHUBS)</div><div class='ctx'> 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h<br/>index 8283d682f543..d3118275ddae 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h</a></div><div class='hunk'>@@ -55,8 +55,6 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);</div><div class='del'>-void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_gart_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,</div><div class='hunk'>@@ -66,5 +64,8 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,</div><div class='ctx'> 		     void *dst);</div><div class='ctx'> void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,</div><div class='ctx'> 		      int pages, dma_addr_t *dma_addr, uint64_t flags);</div><div class='add'>+void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,</div><div class='add'>+				uint64_t start_page, uint64_t num_pages,</div><div class='add'>+				uint64_t flags, void *dst);</div><div class='ctx'> void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c<br/>index 67c234bcf89f..3e38c5db2987 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c</a></div><div class='hunk'>@@ -36,14 +36,122 @@</div><div class='ctx'> #include &lt;drm/drm_exec.h&gt;</div><div class='ctx'> #include &lt;drm/drm_gem_ttm_helper.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+#include &lt;drm/drm_syncobj.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_display.h"</div><div class='ctx'> #include "amdgpu_dma_buf.h"</div><div class='ctx'> #include "amdgpu_hmm.h"</div><div class='ctx'> #include "amdgpu_xgmi.h"</div><div class='add'>+#include "amdgpu_vm.h"</div><div class='ctx'> </div><div class='del'>-static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;</div><div class='add'>+static int</div><div class='add'>+amdgpu_gem_add_input_fence(struct drm_file *filp,</div><div class='add'>+			   uint64_t syncobj_handles_array,</div><div class='add'>+			   uint32_t num_syncobj_handles)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	uint32_t *syncobj_handles;</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	if (!num_syncobj_handles)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	syncobj_handles = memdup_user(u64_to_user_ptr(syncobj_handles_array),</div><div class='add'>+				      size_mul(sizeof(uint32_t), num_syncobj_handles));</div><div class='add'>+	if (IS_ERR(syncobj_handles))</div><div class='add'>+		return PTR_ERR(syncobj_handles);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_syncobj_handles; i++) {</div><div class='add'>+</div><div class='add'>+		if (!syncobj_handles[i]) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto free_memdup;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, 0, &amp;fence);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_memdup;</div><div class='add'>+</div><div class='add'>+		dma_fence_wait(fence, false);</div><div class='add'>+</div><div class='add'>+		/* TODO: optimize async handling */</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+free_memdup:</div><div class='add'>+	kfree(syncobj_handles);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_gem_update_timeline_node(struct drm_file *filp,</div><div class='add'>+				uint32_t syncobj_handle,</div><div class='add'>+				uint64_t point,</div><div class='add'>+				struct drm_syncobj **syncobj,</div><div class='add'>+				struct dma_fence_chain **chain)</div><div class='add'>+{</div><div class='add'>+	if (!syncobj_handle)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Find the sync object */</div><div class='add'>+	*syncobj = drm_syncobj_find(filp, syncobj_handle);</div><div class='add'>+	if (!*syncobj)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (!point)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Allocate the chain node */</div><div class='add'>+	*chain = dma_fence_chain_alloc();</div><div class='add'>+	if (!*chain) {</div><div class='add'>+		drm_syncobj_put(*syncobj);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+amdgpu_gem_update_bo_mapping(struct drm_file *filp,</div><div class='add'>+			     struct amdgpu_bo_va *bo_va,</div><div class='add'>+			     uint32_t operation,</div><div class='add'>+			     uint64_t point,</div><div class='add'>+			     struct dma_fence *fence,</div><div class='add'>+			     struct drm_syncobj *syncobj,</div><div class='add'>+			     struct dma_fence_chain *chain)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo *bo = bo_va ? bo_va-&gt;base.bo : NULL;</div><div class='add'>+	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='add'>+	struct amdgpu_vm *vm = &amp;fpriv-&gt;vm;</div><div class='add'>+	struct dma_fence *last_update;</div><div class='add'>+</div><div class='add'>+	if (!syncobj)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Find the last update fence */</div><div class='add'>+	switch (operation) {</div><div class='add'>+	case AMDGPU_VA_OP_MAP:</div><div class='add'>+	case AMDGPU_VA_OP_REPLACE:</div><div class='add'>+		if (bo &amp;&amp; (bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv))</div><div class='add'>+			last_update = vm-&gt;last_update;</div><div class='add'>+		else</div><div class='add'>+			last_update = bo_va-&gt;last_pt_update;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VA_OP_UNMAP:</div><div class='add'>+	case AMDGPU_VA_OP_CLEAR:</div><div class='add'>+		last_update = fence;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Add fence to timeline */</div><div class='add'>+	if (!point)</div><div class='add'>+		drm_syncobj_replace_fence(syncobj, last_update);</div><div class='add'>+	else</div><div class='add'>+		drm_syncobj_add_point(syncobj, chain, last_update, point);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)</div><div class='ctx'> {</div><div class='hunk'>@@ -87,12 +195,10 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = {</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_gem_object_free(struct drm_gem_object *gobj)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);</div><div class='add'>+	struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj);</div><div class='ctx'> </div><div class='del'>-	if (robj) {</div><div class='del'>-		amdgpu_hmm_unregister(robj);</div><div class='del'>-		amdgpu_bo_unref(&amp;robj);</div><div class='del'>-	}</div><div class='add'>+	amdgpu_hmm_unregister(aobj);</div><div class='add'>+	ttm_bo_fini(&amp;aobj-&gt;tbo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,</div><div class='hunk'>@@ -108,6 +214,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;bp, 0, sizeof(bp));</div><div class='ctx'> 	*obj = NULL;</div><div class='add'>+	flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;</div><div class='ctx'> </div><div class='ctx'> 	bp.size = size;</div><div class='ctx'> 	bp.byte_align = alignment;</div><div class='hunk'>@@ -125,7 +232,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,</div><div class='ctx'> </div><div class='ctx'> 	bo = &amp;ubo-&gt;bo;</div><div class='ctx'> 	*obj = &amp;bo-&gt;tbo.base;</div><div class='del'>-	(*obj)-&gt;funcs = &amp;amdgpu_gem_object_funcs;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -174,18 +280,28 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,</div><div class='ctx'> 		return -EPERM;</div><div class='ctx'> </div><div class='ctx'> 	if (abo-&gt;flags &amp; AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &amp;&amp;</div><div class='del'>-	    abo-&gt;tbo.base.resv != vm-&gt;root.bo-&gt;tbo.base.resv)</div><div class='add'>+	    !amdgpu_vm_is_bo_always_valid(vm, abo))</div><div class='ctx'> 		return -EPERM;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_bo_reserve(abo, false);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_bo_update_shared(abo);</div><div class='ctx'> 	bo_va = amdgpu_vm_bo_find(vm, abo);</div><div class='ctx'> 	if (!bo_va)</div><div class='ctx'> 		bo_va = amdgpu_vm_bo_add(adev, vm, abo);</div><div class='ctx'> 	else</div><div class='ctx'> 		++bo_va-&gt;ref_count;</div><div class='add'>+</div><div class='add'>+	/* attach gfx eviction fence */</div><div class='add'>+	r = amdgpu_eviction_fence_attach(&amp;fpriv-&gt;evf_mgr, abo);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_DEBUG_DRIVER("Failed to attach eviction fence to BO\n");</div><div class='add'>+		amdgpu_bo_unreserve(abo);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	amdgpu_bo_unreserve(abo);</div><div class='ctx'> </div><div class='ctx'> 	/* Validate and add eviction fence to DMABuf imports with dynamic</div><div class='hunk'>@@ -201,7 +317,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!vm-&gt;is_compute_context || !vm-&gt;process_info)</div><div class='ctx'> 		return 0;</div><div class='del'>-	if (!obj-&gt;import_attach ||</div><div class='add'>+	if (!drm_gem_is_imported(obj) ||</div><div class='ctx'> 	    !dma_buf_is_dynamic(obj-&gt;import_attach-&gt;dmabuf))</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	mutex_lock_nested(&amp;vm-&gt;process_info-&gt;lock, 1);</div><div class='hunk'>@@ -213,7 +329,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj,</div><div class='ctx'> </div><div class='ctx'> 			dev_warn(adev-&gt;dev, "validate_and_fence failed: %d\n", r);</div><div class='ctx'> 			if (ti) {</div><div class='del'>-				dev_warn(adev-&gt;dev, "pid %d\n", ti-&gt;pid);</div><div class='add'>+				dev_warn(adev-&gt;dev, "pid %d\n", ti-&gt;task.pid);</div><div class='ctx'> 				amdgpu_vm_put_task_info(ti);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -249,11 +365,15 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj,</div><div class='ctx'> 			goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!amdgpu_vm_is_bo_always_valid(vm, bo))</div><div class='add'>+		amdgpu_eviction_fence_detach(&amp;fpriv-&gt;evf_mgr, bo);</div><div class='add'>+</div><div class='ctx'> 	bo_va = amdgpu_vm_bo_find(vm, bo);</div><div class='ctx'> 	if (!bo_va || --bo_va-&gt;ref_count)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_vm_bo_del(adev, bo_va);</div><div class='add'>+	amdgpu_vm_bo_update_shared(bo);</div><div class='ctx'> 	if (!amdgpu_vm_ready(vm))</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -294,7 +414,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str</div><div class='ctx'> 	return drm_gem_ttm_mmap(obj, vma);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {</div><div class='add'>+const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {</div><div class='ctx'> 	.free = amdgpu_gem_object_free,</div><div class='ctx'> 	.open = amdgpu_gem_object_open,</div><div class='ctx'> 	.close = amdgpu_gem_object_close,</div><div class='hunk'>@@ -322,19 +442,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 	uint32_t handle, initial_domain;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* reject DOORBELLs until userspace code to use it is available */</div><div class='del'>-	if (args-&gt;in.domains &amp; AMDGPU_GEM_DOMAIN_DOORBELL)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 	/* reject invalid gem flags */</div><div class='del'>-	if (flags &amp; ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |</div><div class='del'>-		      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |</div><div class='del'>-		      AMDGPU_GEM_CREATE_CPU_GTT_USWC |</div><div class='del'>-		      AMDGPU_GEM_CREATE_VRAM_CLEARED |</div><div class='del'>-		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |</div><div class='del'>-		      AMDGPU_GEM_CREATE_EXPLICIT_SYNC |</div><div class='del'>-		      AMDGPU_GEM_CREATE_ENCRYPTED |</div><div class='del'>-		      AMDGPU_GEM_CREATE_DISCARDABLE))</div><div class='add'>+	if (flags &amp; ~AMDGPU_GEM_CREATE_SETTABLE_MASK)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* reject invalid gem domains */</div><div class='hunk'>@@ -346,6 +455,12 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* always clear VRAM */</div><div class='add'>+	flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;in.domains &amp; AMDGPU_GEM_DOMAIN_MMIO_REMAP)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	/* create a gem object to contain this object in */</div><div class='ctx'> 	if (args-&gt;in.domains &amp; (AMDGPU_GEM_DOMAIN_GDS |</div><div class='ctx'> 	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {</div><div class='hunk'>@@ -416,7 +531,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 	struct drm_amdgpu_gem_userptr *args = data;</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='ctx'> 	struct drm_gem_object *gobj;</div><div class='del'>-	struct hmm_range *range;</div><div class='add'>+	struct amdgpu_hmm_range *range;</div><div class='ctx'> 	struct amdgpu_bo *bo;</div><div class='ctx'> 	uint32_t handle;</div><div class='ctx'> 	int r;</div><div class='hunk'>@@ -457,15 +572,20 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 		goto release_object;</div><div class='ctx'> </div><div class='ctx'> 	if (args-&gt;flags &amp; AMDGPU_GEM_USERPTR_VALIDATE) {</div><div class='del'>-		r = amdgpu_ttm_tt_get_user_pages(bo, bo-&gt;tbo.ttm-&gt;pages,</div><div class='del'>-						 &amp;range);</div><div class='del'>-		if (r)</div><div class='add'>+		range = amdgpu_hmm_range_alloc(NULL);</div><div class='add'>+		if (unlikely(!range))</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		r = amdgpu_ttm_tt_get_user_pages(bo, range);</div><div class='add'>+		if (r) {</div><div class='add'>+			amdgpu_hmm_range_free(range);</div><div class='ctx'> 			goto release_object;</div><div class='del'>-</div><div class='add'>+		}</div><div class='ctx'> 		r = amdgpu_bo_reserve(bo, true);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto user_pages_done;</div><div class='ctx'> </div><div class='add'>+		amdgpu_ttm_tt_set_user_pages(bo-&gt;tbo.ttm, range);</div><div class='add'>+</div><div class='ctx'> 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);</div><div class='ctx'> 		r = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='ctx'> 		amdgpu_bo_unreserve(bo);</div><div class='hunk'>@@ -481,8 +601,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> </div><div class='ctx'> user_pages_done:</div><div class='ctx'> 	if (args-&gt;flags &amp; AMDGPU_GEM_USERPTR_VALIDATE)</div><div class='del'>-		amdgpu_ttm_tt_get_user_pages_done(bo-&gt;tbo.ttm, range);</div><div class='del'>-</div><div class='add'>+		amdgpu_hmm_range_free(range);</div><div class='ctx'> release_object:</div><div class='ctx'> 	drm_gem_object_put(gobj);</div><div class='ctx'> </div><div class='hunk'>@@ -635,18 +754,23 @@ out:</div><div class='ctx'>  *</div><div class='ctx'>  * Update the bo_va directly after setting its address. Errors are not</div><div class='ctx'>  * vital here, so they are not reported back to userspace.</div><div class='add'>+ *</div><div class='add'>+ * Returns resulting fence if freed BO(s) got cleared from the PT.</div><div class='add'>+ * otherwise stub fence in case of error.</div><div class='ctx'>  */</div><div class='del'>-static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,</div><div class='del'>-				    struct amdgpu_vm *vm,</div><div class='del'>-				    struct amdgpu_bo_va *bo_va,</div><div class='del'>-				    uint32_t operation)</div><div class='add'>+static struct dma_fence *</div><div class='add'>+amdgpu_gem_va_update_vm(struct amdgpu_device *adev,</div><div class='add'>+			struct amdgpu_vm *vm,</div><div class='add'>+			struct amdgpu_bo_va *bo_va,</div><div class='add'>+			uint32_t operation)</div><div class='ctx'> {</div><div class='add'>+	struct dma_fence *fence = dma_fence_get_stub();</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_vm_ready(vm))</div><div class='del'>-		return;</div><div class='add'>+		return fence;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vm_clear_freed(adev, vm, NULL);</div><div class='add'>+	r = amdgpu_vm_clear_freed(adev, vm, &amp;fence);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -662,36 +786,8 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,</div><div class='ctx'> error:</div><div class='ctx'> 	if (r &amp;&amp; r != -ERESTARTSYS)</div><div class='ctx'> 		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);</div><div class='del'>-}</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @flags: GEM UAPI flags</div><div class='del'>- *</div><div class='del'>- * Returns the GEM UAPI flags mapped into hardware for the ASIC.</div><div class='del'>- */</div><div class='del'>-uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)</div><div class='del'>-{</div><div class='del'>-	uint64_t pte_flag = 0;</div><div class='del'>-</div><div class='del'>-	if (flags &amp; AMDGPU_VM_PAGE_EXECUTABLE)</div><div class='del'>-		pte_flag |= AMDGPU_PTE_EXECUTABLE;</div><div class='del'>-	if (flags &amp; AMDGPU_VM_PAGE_READABLE)</div><div class='del'>-		pte_flag |= AMDGPU_PTE_READABLE;</div><div class='del'>-	if (flags &amp; AMDGPU_VM_PAGE_WRITEABLE)</div><div class='del'>-		pte_flag |= AMDGPU_PTE_WRITEABLE;</div><div class='del'>-	if (flags &amp; AMDGPU_VM_PAGE_PRT)</div><div class='del'>-		pte_flag |= AMDGPU_PTE_PRT;</div><div class='del'>-	if (flags &amp; AMDGPU_VM_PAGE_NOALLOC)</div><div class='del'>-		pte_flag |= AMDGPU_PTE_NOALLOC;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;gmc.gmc_funcs-&gt;map_mtype)</div><div class='del'>-		pte_flag |= amdgpu_gmc_map_mtype(adev,</div><div class='del'>-						 flags &amp; AMDGPU_VM_MTYPE_MASK);</div><div class='del'>-</div><div class='del'>-	return pte_flag;</div><div class='add'>+	return fence;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='hunk'>@@ -710,8 +806,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='ctx'> 	struct amdgpu_bo *abo;</div><div class='ctx'> 	struct amdgpu_bo_va *bo_va;</div><div class='add'>+	struct drm_syncobj *timeline_syncobj = NULL;</div><div class='add'>+	struct dma_fence_chain *timeline_chain = NULL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='ctx'> 	struct drm_exec exec;</div><div class='del'>-	uint64_t va_flags;</div><div class='ctx'> 	uint64_t vm_size;</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -771,6 +869,12 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 		abo = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_gem_add_input_fence(filp,</div><div class='add'>+				       args-&gt;input_fence_syncobj_handles,</div><div class='add'>+				       args-&gt;num_syncobj_handles);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_put_gobj;</div><div class='add'>+</div><div class='ctx'> 	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT |</div><div class='ctx'> 		      DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='hunk'>@@ -799,12 +903,19 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 		bo_va = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_gem_update_timeline_node(filp,</div><div class='add'>+					    args-&gt;vm_timeline_syncobj_out,</div><div class='add'>+					    args-&gt;vm_timeline_point,</div><div class='add'>+					    &amp;timeline_syncobj,</div><div class='add'>+					    &amp;timeline_chain);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error;</div><div class='add'>+</div><div class='ctx'> 	switch (args-&gt;operation) {</div><div class='ctx'> 	case AMDGPU_VA_OP_MAP:</div><div class='del'>-		va_flags = amdgpu_gem_va_map_flags(adev, args-&gt;flags);</div><div class='ctx'> 		r = amdgpu_vm_bo_map(adev, bo_va, args-&gt;va_address,</div><div class='ctx'> 				     args-&gt;offset_in_bo, args-&gt;map_size,</div><div class='del'>-				     va_flags);</div><div class='add'>+				     args-&gt;flags);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_VA_OP_UNMAP:</div><div class='ctx'> 		r = amdgpu_vm_bo_unmap(adev, bo_va, args-&gt;va_address);</div><div class='hunk'>@@ -816,20 +927,31 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 						args-&gt;map_size);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_VA_OP_REPLACE:</div><div class='del'>-		va_flags = amdgpu_gem_va_map_flags(adev, args-&gt;flags);</div><div class='ctx'> 		r = amdgpu_vm_bo_replace_map(adev, bo_va, args-&gt;va_address,</div><div class='ctx'> 					     args-&gt;offset_in_bo, args-&gt;map_size,</div><div class='del'>-					     va_flags);</div><div class='add'>+					     args-&gt;flags);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='del'>-	if (!r &amp;&amp; !(args-&gt;flags &amp; AMDGPU_VM_DELAY_UPDATE) &amp;&amp; !adev-&gt;debug_vm)</div><div class='del'>-		amdgpu_gem_va_update_vm(adev, &amp;fpriv-&gt;vm, bo_va,</div><div class='del'>-					args-&gt;operation);</div><div class='add'>+	if (!r &amp;&amp; !(args-&gt;flags &amp; AMDGPU_VM_DELAY_UPDATE) &amp;&amp; !adev-&gt;debug_vm) {</div><div class='add'>+		fence = amdgpu_gem_va_update_vm(adev, &amp;fpriv-&gt;vm, bo_va,</div><div class='add'>+						args-&gt;operation);</div><div class='add'>+</div><div class='add'>+		if (timeline_syncobj)</div><div class='add'>+			amdgpu_gem_update_bo_mapping(filp, bo_va,</div><div class='add'>+					     args-&gt;operation,</div><div class='add'>+					     args-&gt;vm_timeline_point,</div><div class='add'>+					     fence, timeline_syncobj,</div><div class='add'>+					     timeline_chain);</div><div class='add'>+		else</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='ctx'> 	drm_exec_fini(&amp;exec);</div><div class='add'>+error_put_gobj:</div><div class='ctx'> 	drm_gem_object_put(gobj);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -837,22 +959,38 @@ error:</div><div class='ctx'> int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 			struct drm_file *filp)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct drm_amdgpu_gem_op *args = data;</div><div class='ctx'> 	struct drm_gem_object *gobj;</div><div class='ctx'> 	struct amdgpu_vm_bo_base *base;</div><div class='ctx'> 	struct amdgpu_bo *robj;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	if (args-&gt;padding)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	gobj = drm_gem_object_lookup(filp, args-&gt;handle);</div><div class='ctx'> 	if (!gobj)</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> </div><div class='ctx'> 	robj = gem_to_amdgpu_bo(gobj);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_bo_reserve(robj, false);</div><div class='del'>-	if (unlikely(r))</div><div class='del'>-		goto out;</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT |</div><div class='add'>+			  DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		r = drm_exec_lock_obj(&amp;exec, gobj);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (r)</div><div class='add'>+			goto out_exec;</div><div class='add'>+</div><div class='add'>+		if (args-&gt;op == AMDGPU_GEM_OP_GET_MAPPING_INFO) {</div><div class='add'>+			r = amdgpu_vm_lock_pd(&amp;fpriv-&gt;vm, &amp;exec, 0);</div><div class='add'>+			drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+			if (r)</div><div class='add'>+				goto out_exec;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	switch (args-&gt;op) {</div><div class='ctx'> 	case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {</div><div class='hunk'>@@ -863,29 +1001,26 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 		info.alignment = robj-&gt;tbo.page_alignment &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 		info.domains = robj-&gt;preferred_domains;</div><div class='ctx'> 		info.domain_flags = robj-&gt;flags;</div><div class='del'>-		amdgpu_bo_unreserve(robj);</div><div class='add'>+		drm_exec_fini(&amp;exec);</div><div class='ctx'> 		if (copy_to_user(out, &amp;info, sizeof(info)))</div><div class='ctx'> 			r = -EFAULT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	case AMDGPU_GEM_OP_SET_PLACEMENT:</div><div class='del'>-		if (robj-&gt;tbo.base.import_attach &amp;&amp;</div><div class='add'>+		if (drm_gem_is_imported(&amp;robj-&gt;tbo.base) &amp;&amp;</div><div class='ctx'> 		    args-&gt;value &amp; AMDGPU_GEM_DOMAIN_VRAM) {</div><div class='ctx'> 			r = -EINVAL;</div><div class='del'>-			amdgpu_bo_unreserve(robj);</div><div class='del'>-			break;</div><div class='add'>+			goto out_exec;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (amdgpu_ttm_tt_get_usermm(robj-&gt;tbo.ttm)) {</div><div class='ctx'> 			r = -EPERM;</div><div class='del'>-			amdgpu_bo_unreserve(robj);</div><div class='del'>-			break;</div><div class='add'>+			goto out_exec;</div><div class='ctx'> 		}</div><div class='ctx'> 		for (base = robj-&gt;vm_bo; base; base = base-&gt;next)</div><div class='ctx'> 			if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj-&gt;tbo.bdev),</div><div class='ctx'> 				amdgpu_ttm_adev(base-&gt;vm-&gt;root.bo-&gt;tbo.bdev))) {</div><div class='ctx'> 				r = -EINVAL;</div><div class='del'>-				amdgpu_bo_unreserve(robj);</div><div class='del'>-				goto out;</div><div class='add'>+				goto out_exec;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -897,18 +1032,147 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 			robj-&gt;allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;</div><div class='ctx'> </div><div class='ctx'> 		if (robj-&gt;flags &amp; AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)</div><div class='del'>-			amdgpu_vm_bo_invalidate(adev, robj, true);</div><div class='add'>+			amdgpu_vm_bo_invalidate(robj, true);</div><div class='add'>+		drm_exec_fini(&amp;exec);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_GEM_OP_GET_MAPPING_INFO: {</div><div class='add'>+		struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(&amp;fpriv-&gt;vm, robj);</div><div class='add'>+		struct drm_amdgpu_gem_vm_entry *vm_entries;</div><div class='add'>+		struct amdgpu_bo_va_mapping *mapping;</div><div class='add'>+		int num_mappings = 0;</div><div class='add'>+		/*</div><div class='add'>+		 * num_entries is set as an input to the size of the user-allocated array of</div><div class='add'>+		 * drm_amdgpu_gem_vm_entry stored at args-&gt;value.</div><div class='add'>+		 * num_entries is sent back as output as the number of mappings the bo has.</div><div class='add'>+		 * If that number is larger than the size of the array, the ioctl must</div><div class='add'>+		 * be retried.</div><div class='add'>+		 */</div><div class='add'>+		vm_entries = kvcalloc(args-&gt;num_entries, sizeof(*vm_entries), GFP_KERNEL);</div><div class='add'>+		if (!vm_entries)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) {</div><div class='add'>+			if (num_mappings &lt; args-&gt;num_entries) {</div><div class='add'>+				vm_entries[num_mappings].addr = mapping-&gt;start * AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+				vm_entries[num_mappings].size = (mapping-&gt;last - mapping-&gt;start + 1) * AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+				vm_entries[num_mappings].offset = mapping-&gt;offset;</div><div class='add'>+				vm_entries[num_mappings].flags = mapping-&gt;flags;</div><div class='add'>+			}</div><div class='add'>+			num_mappings += 1;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) {</div><div class='add'>+			if (num_mappings &lt; args-&gt;num_entries) {</div><div class='add'>+				vm_entries[num_mappings].addr = mapping-&gt;start * AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+				vm_entries[num_mappings].size = (mapping-&gt;last - mapping-&gt;start + 1) * AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+				vm_entries[num_mappings].offset = mapping-&gt;offset;</div><div class='add'>+				vm_entries[num_mappings].flags = mapping-&gt;flags;</div><div class='add'>+			}</div><div class='add'>+			num_mappings += 1;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		amdgpu_bo_unreserve(robj);</div><div class='add'>+		drm_exec_fini(&amp;exec);</div><div class='add'>+</div><div class='add'>+		if (num_mappings &gt; 0 &amp;&amp; num_mappings &lt;= args-&gt;num_entries)</div><div class='add'>+			if (copy_to_user(u64_to_user_ptr(args-&gt;value), vm_entries, num_mappings * sizeof(*vm_entries)))</div><div class='add'>+				r = -EFAULT;</div><div class='add'>+</div><div class='add'>+		args-&gt;num_entries = num_mappings;</div><div class='add'>+</div><div class='add'>+		kvfree(vm_entries);</div><div class='ctx'> 		break;</div><div class='add'>+	}</div><div class='ctx'> 	default:</div><div class='del'>-		amdgpu_bo_unreserve(robj);</div><div class='add'>+		drm_exec_fini(&amp;exec);</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-out:</div><div class='ctx'> 	drm_gem_object_put(gobj);</div><div class='ctx'> 	return r;</div><div class='add'>+out_exec:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+	drm_gem_object_put(gobj);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects</div><div class='add'>+ *</div><div class='add'>+ * @dev: drm device pointer</div><div class='add'>+ * @data: drm_amdgpu_gem_list_handles</div><div class='add'>+ * @filp: drm file pointer</div><div class='add'>+ *</div><div class='add'>+ * num_entries is set as an input to the size of the entries array.</div><div class='add'>+ * num_entries is sent back as output as the number of bos in the process.</div><div class='add'>+ * If that number is larger than the size of the array, the ioctl must</div><div class='add'>+ * be retried.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 for success, -errno for errors.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+				  struct drm_file *filp)</div><div class='add'>+{</div><div class='add'>+	struct drm_amdgpu_gem_list_handles *args = data;</div><div class='add'>+	struct drm_amdgpu_gem_list_handles_entry *bo_entries;</div><div class='add'>+	struct drm_gem_object *gobj;</div><div class='add'>+	int id, ret = 0;</div><div class='add'>+	int bo_index = 0;</div><div class='add'>+	int num_bos = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;filp-&gt;table_lock);</div><div class='add'>+	idr_for_each_entry(&amp;filp-&gt;object_idr, gobj, id)</div><div class='add'>+		num_bos += 1;</div><div class='add'>+	spin_unlock(&amp;filp-&gt;table_lock);</div><div class='add'>+</div><div class='add'>+	if (args-&gt;num_entries &lt; num_bos) {</div><div class='add'>+		args-&gt;num_entries = num_bos;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (num_bos == 0) {</div><div class='add'>+		args-&gt;num_entries = 0;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);</div><div class='add'>+	if (!bo_entries)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;filp-&gt;table_lock);</div><div class='add'>+	idr_for_each_entry(&amp;filp-&gt;object_idr, gobj, id) {</div><div class='add'>+		struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);</div><div class='add'>+		struct drm_amdgpu_gem_list_handles_entry *bo_entry;</div><div class='add'>+</div><div class='add'>+		if (bo_index &gt;= num_bos) {</div><div class='add'>+			ret = -EAGAIN;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		bo_entry = &amp;bo_entries[bo_index];</div><div class='add'>+</div><div class='add'>+		bo_entry-&gt;size = amdgpu_bo_size(bo);</div><div class='add'>+		bo_entry-&gt;alloc_flags = bo-&gt;flags &amp; AMDGPU_GEM_CREATE_SETTABLE_MASK;</div><div class='add'>+		bo_entry-&gt;preferred_domains = bo-&gt;preferred_domains;</div><div class='add'>+		bo_entry-&gt;gem_handle = id;</div><div class='add'>+		bo_entry-&gt;alignment = bo-&gt;tbo.page_alignment;</div><div class='add'>+</div><div class='add'>+		if (bo-&gt;tbo.base.import_attach)</div><div class='add'>+			bo_entry-&gt;flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;</div><div class='add'>+</div><div class='add'>+		bo_index += 1;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;filp-&gt;table_lock);</div><div class='add'>+</div><div class='add'>+	args-&gt;num_entries = bo_index;</div><div class='add'>+</div><div class='add'>+	if (!ret)</div><div class='add'>+		if (copy_to_user(u64_to_user_ptr(args-&gt;entries), bo_entries, num_bos * sizeof(*bo_entries)))</div><div class='add'>+			ret = -EFAULT;</div><div class='add'>+</div><div class='add'>+	kvfree(bo_entries);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h<br/>index f30264782ba2..b558336bc4c6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h</a></div><div class='hunk'>@@ -33,6 +33,8 @@</div><div class='ctx'> #define AMDGPU_GEM_DOMAIN_MAX		0x3</div><div class='ctx'> #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base)</div><div class='ctx'> </div><div class='add'>+extern const struct drm_gem_object_funcs amdgpu_gem_object_funcs;</div><div class='add'>+</div><div class='ctx'> unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -61,13 +63,28 @@ int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 			  struct drm_file *filp);</div><div class='ctx'> int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 			      struct drm_file *filp);</div><div class='del'>-uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags);</div><div class='ctx'> int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 			  struct drm_file *filp);</div><div class='ctx'> int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 			struct drm_file *filp);</div><div class='add'>+int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+				  struct drm_file *filp);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 				struct drm_file *filp);</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_GEM_CREATE_SETTABLE_MASK	(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \</div><div class='add'>+	AMDGPU_GEM_CREATE_NO_CPU_ACCESS | \</div><div class='add'>+	AMDGPU_GEM_CREATE_CPU_GTT_USWC | \</div><div class='add'>+	AMDGPU_GEM_CREATE_VRAM_CLEARED | \</div><div class='add'>+	AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | \</div><div class='add'>+	AMDGPU_GEM_CREATE_EXPLICIT_SYNC | \</div><div class='add'>+	AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE | \</div><div class='add'>+	AMDGPU_GEM_CREATE_ENCRYPTED | \</div><div class='add'>+	AMDGPU_GEM_CREATE_GFX12_DCC | \</div><div class='add'>+	AMDGPU_GEM_CREATE_DISCARDABLE | \</div><div class='add'>+	AMDGPU_GEM_CREATE_COHERENT | \</div><div class='add'>+	AMDGPU_GEM_CREATE_UNCACHED | \</div><div class='add'>+	AMDGPU_GEM_CREATE_EXT_COHERENT)</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c<br/>index 55d5508987ff..8b118c53f351 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c</a></div><div class='hunk'>@@ -24,12 +24,17 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_gfx.h"</div><div class='ctx'> #include "amdgpu_rlc.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='ctx'> #include "amdgpu_xgmi.h"</div><div class='add'>+#include "amdgpu_mes.h"</div><div class='add'>+#include "nvd.h"</div><div class='ctx'> </div><div class='ctx'> /* delay 0.1 second to enable gfx off feature */</div><div class='ctx'> #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)</div><div class='hunk'>@@ -71,29 +76,20 @@ bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,</div><div class='ctx'> 			adev-&gt;gfx.mec_bitmap[xcc_id].queue_bitmap);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,</div><div class='del'>-			       int me, int pipe, int queue)</div><div class='add'>+static int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe, int queue)</div><div class='ctx'> {</div><div class='add'>+	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */</div><div class='ctx'> 	int bit = 0;</div><div class='ctx'> </div><div class='ctx'> 	bit += me * adev-&gt;gfx.me.num_pipe_per_me</div><div class='del'>-		* adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='del'>-	bit += pipe * adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='add'>+		* num_queue_per_pipe;</div><div class='add'>+	bit += pipe * num_queue_per_pipe;</div><div class='ctx'> 	bit += queue;</div><div class='ctx'> </div><div class='ctx'> 	return bit;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,</div><div class='del'>-				int *me, int *pipe, int *queue)</div><div class='del'>-{</div><div class='del'>-	*queue = bit % adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='del'>-	*pipe = (bit / adev-&gt;gfx.me.num_queue_per_pipe)</div><div class='del'>-		% adev-&gt;gfx.me.num_pipe_per_me;</div><div class='del'>-	*me = (bit / adev-&gt;gfx.me.num_queue_per_pipe)</div><div class='del'>-		/ adev-&gt;gfx.me.num_pipe_per_me;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,</div><div class='ctx'> 				    int me, int pipe, int queue)</div><div class='ctx'> {</div><div class='hunk'>@@ -154,7 +150,7 @@ static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)</div><div class='ctx'> static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_compute_multipipe != -1) {</div><div class='del'>-		DRM_INFO("amdgpu: forcing compute pipe policy %d\n",</div><div class='add'>+		dev_info(adev-&gt;dev, "amdgpu: forcing compute pipe policy %d\n",</div><div class='ctx'> 			 amdgpu_compute_multipipe);</div><div class='ctx'> 		return amdgpu_compute_multipipe == 1;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -245,8 +241,8 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i, queue, pipe;</div><div class='ctx'> 	bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);</div><div class='del'>-	int max_queues_per_me = adev-&gt;gfx.me.num_pipe_per_me *</div><div class='del'>-					adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='add'>+	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */</div><div class='add'>+	int max_queues_per_me = adev-&gt;gfx.me.num_pipe_per_me * num_queue_per_pipe;</div><div class='ctx'> </div><div class='ctx'> 	if (multipipe_policy) {</div><div class='ctx'> 		/* policy: amdgpu owns the first queue per pipe at this stage</div><div class='hunk'>@@ -254,9 +250,9 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)</div><div class='ctx'> 		for (i = 0; i &lt; max_queues_per_me; i++) {</div><div class='ctx'> 			pipe = i % adev-&gt;gfx.me.num_pipe_per_me;</div><div class='ctx'> 			queue = (i / adev-&gt;gfx.me.num_pipe_per_me) %</div><div class='del'>-				adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='add'>+				num_queue_per_pipe;</div><div class='ctx'> </div><div class='del'>-			set_bit(pipe * adev-&gt;gfx.me.num_queue_per_pipe + queue,</div><div class='add'>+			set_bit(pipe * num_queue_per_pipe + queue,</div><div class='ctx'> 				adev-&gt;gfx.me.queue_bitmap);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -265,8 +261,9 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* update the number of active graphics rings */</div><div class='del'>-	adev-&gt;gfx.num_gfx_rings =</div><div class='del'>-		bitmap_weight(adev-&gt;gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+		adev-&gt;gfx.num_gfx_rings =</div><div class='add'>+			bitmap_weight(adev-&gt;gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,</div><div class='hunk'>@@ -329,8 +326,9 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;eop_gpu_addr = kiq-&gt;eop_gpu_addr;</div><div class='ctx'> 	ring-&gt;no_scheduler = true;</div><div class='del'>-	snprintf(ring-&gt;name, sizeof(ring-&gt;name), "kiq_%d.%d.%d.%d",</div><div class='del'>-		 xcc_id, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='add'>+	snprintf(ring-&gt;name, sizeof(ring-&gt;name), "kiq_%hhu.%hhu.%hhu.%hhu",</div><div class='add'>+		 (unsigned char)xcc_id, (unsigned char)ring-&gt;me,</div><div class='add'>+		 (unsigned char)ring-&gt;pipe, (unsigned char)ring-&gt;queue);</div><div class='ctx'> 	r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,</div><div class='ctx'> 			     AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -411,7 +409,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* prepare MQD backup */</div><div class='del'>-		kiq-&gt;mqd_backup = kmalloc(mqd_size, GFP_KERNEL);</div><div class='add'>+		kiq-&gt;mqd_backup = kzalloc(mqd_size, GFP_KERNEL);</div><div class='ctx'> 		if (!kiq-&gt;mqd_backup) {</div><div class='ctx'> 			dev_warn(adev-&gt;dev,</div><div class='ctx'> 				 "no memory to create MQD backup for ring %s\n", ring-&gt;name);</div><div class='hunk'>@@ -434,7 +432,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 				ring-&gt;mqd_size = mqd_size;</div><div class='ctx'> 				/* prepare MQD backup */</div><div class='del'>-				adev-&gt;gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);</div><div class='add'>+				adev-&gt;gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL);</div><div class='ctx'> 				if (!adev-&gt;gfx.me.mqd_backup[i]) {</div><div class='ctx'> 					dev_warn(adev-&gt;dev, "no memory to create MQD backup for ring %s\n", ring-&gt;name);</div><div class='ctx'> 					return -ENOMEM;</div><div class='hunk'>@@ -458,7 +456,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 			ring-&gt;mqd_size = mqd_size;</div><div class='ctx'> 			/* prepare MQD backup */</div><div class='del'>-			adev-&gt;gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);</div><div class='add'>+			adev-&gt;gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL);</div><div class='ctx'> 			if (!adev-&gt;gfx.mec.mqd_backup[j]) {</div><div class='ctx'> 				dev_warn(adev-&gt;dev, "no memory to create MQD backup for ring %s\n", ring-&gt;name);</div><div class='ctx'> 				return -ENOMEM;</div><div class='hunk'>@@ -505,15 +503,25 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[xcc_id];</div><div class='ctx'> 	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='del'>-	struct amdgpu_hive_info *hive;</div><div class='del'>-	struct amdgpu_ras *ras;</div><div class='del'>-	int hive_ras_recovery = 0;</div><div class='ctx'> 	int i, r = 0;</div><div class='ctx'> 	int j;</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;enable_mes) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+			j = i + xcc_id * adev-&gt;gfx.num_compute_rings;</div><div class='add'>+			amdgpu_mes_unmap_legacy_queue(adev,</div><div class='add'>+						   &amp;adev-&gt;gfx.compute_ring[j],</div><div class='add'>+						   RESET_QUEUES, 0, 0);</div><div class='add'>+		}</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!kiq_ring-&gt;sched.ready || amdgpu_in_reset(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	spin_lock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;unmap_queues_size *</div><div class='ctx'> 					adev-&gt;gfx.num_compute_rings)) {</div><div class='hunk'>@@ -527,26 +535,15 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 					   &amp;adev-&gt;gfx.compute_ring[j],</div><div class='ctx'> 					   RESET_QUEUES, 0, 0);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	/**</div><div class='del'>-	 * This is workaround: only skip kiq_ring test</div><div class='del'>-	 * during ras recovery in suspend stage for gfx9.4.3</div><div class='add'>+	/* Submit unmap queue packet */</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	/*</div><div class='add'>+	 * Ring test will do a basic scratch register change check. Just run</div><div class='add'>+	 * this to ensure that unmap queues that is submitted before got</div><div class='add'>+	 * processed successfully before returning.</div><div class='ctx'> 	 */</div><div class='del'>-	hive = amdgpu_get_xgmi_hive(adev);</div><div class='del'>-	if (hive) {</div><div class='del'>-		hive_ras_recovery = atomic_read(&amp;hive-&gt;ras_recovery);</div><div class='del'>-		amdgpu_put_xgmi_hive(hive);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ras = amdgpu_ras_get_context(adev);</div><div class='del'>-	if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) &amp;&amp;</div><div class='del'>-		ras &amp;&amp; (atomic_read(&amp;ras-&gt;in_recovery) || hive_ras_recovery)) {</div><div class='del'>-		spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='add'>+	r = amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> </div><div class='del'>-	if (kiq_ring-&gt;sched.ready &amp;&amp; !adev-&gt;job_hang)</div><div class='del'>-		r = amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> 	spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -559,11 +556,26 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 	int i, r = 0;</div><div class='ctx'> 	int j;</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;enable_mes) {</div><div class='add'>+		if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+				j = i + xcc_id * adev-&gt;gfx.num_gfx_rings;</div><div class='add'>+				amdgpu_mes_unmap_legacy_queue(adev,</div><div class='add'>+						      &amp;adev-&gt;gfx.gfx_ring[j],</div><div class='add'>+						      PREEMPT_QUEUES, 0, 0);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;kiq-&gt;ring_lock);</div><div class='add'>+	if (!adev-&gt;gfx.kiq[0].ring.sched.ready || amdgpu_in_reset(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {</div><div class='add'>+		spin_lock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 		if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;unmap_queues_size *</div><div class='ctx'> 						adev-&gt;gfx.num_gfx_rings)) {</div><div class='ctx'> 			spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='hunk'>@@ -576,11 +588,17 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 						   &amp;adev-&gt;gfx.gfx_ring[j],</div><div class='ctx'> 						   PREEMPT_QUEUES, 0, 0);</div><div class='ctx'> 		}</div><div class='del'>-	}</div><div class='add'>+		/* Submit unmap queue packet */</div><div class='add'>+		amdgpu_ring_commit(kiq_ring);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gfx.kiq[0].ring.sched.ready &amp;&amp; !adev-&gt;job_hang)</div><div class='add'>+		/*</div><div class='add'>+		 * Ring test will do a basic scratch register change check.</div><div class='add'>+		 * Just run this to ensure that unmap queues that is submitted</div><div class='add'>+		 * before got processed successfully before returning.</div><div class='add'>+		 */</div><div class='ctx'> 		r = amdgpu_ring_test_helper(kiq_ring);</div><div class='del'>-	spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='add'>+		spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -598,6 +616,44 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,</div><div class='ctx'> 	return set_resource_bit;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_gfx_mes_enable_kcq(struct amdgpu_device *adev, int xcc_id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[xcc_id];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='add'>+	uint64_t queue_mask = ~0ULL;</div><div class='add'>+	int r, i, j;</div><div class='add'>+</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_uni_mes) {</div><div class='add'>+		spin_lock(&amp;kiq-&gt;ring_lock);</div><div class='add'>+		r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;set_resources_size);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to lock KIQ (%d).\n", r);</div><div class='add'>+			spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		kiq-&gt;pmf-&gt;kiq_set_resources(kiq_ring, queue_mask);</div><div class='add'>+		r = amdgpu_ring_test_helper(kiq_ring);</div><div class='add'>+		spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='add'>+		if (r)</div><div class='add'>+			dev_err(adev-&gt;dev, "KIQ failed to set resources\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+		j = i + xcc_id * adev-&gt;gfx.num_compute_rings;</div><div class='add'>+		r = amdgpu_mes_map_legacy_queue(adev,</div><div class='add'>+						&amp;adev-&gt;gfx.compute_ring[j]);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to map compute queue\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[xcc_id];</div><div class='hunk'>@@ -605,6 +661,9 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 	uint64_t queue_mask = 0;</div><div class='ctx'> 	int r, i, j;</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;mes.enable_legacy_queue_map)</div><div class='add'>+		return amdgpu_gfx_mes_enable_kcq(adev, xcc_id);</div><div class='add'>+</div><div class='ctx'> 	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_map_queues || !kiq-&gt;pmf-&gt;kiq_set_resources)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -616,41 +675,45 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 		 * generation exposes more than 64 queues. If so, the</div><div class='ctx'> 		 * definition of queue_mask needs updating */</div><div class='ctx'> 		if (WARN_ON(i &gt; (sizeof(queue_mask)*8))) {</div><div class='del'>-			DRM_ERROR("Invalid KCQ enabled: %d\n", i);</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid KCQ enabled: %d\n", i);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		queue_mask |= (1ull &lt;&lt; amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring-&gt;me, kiq_ring-&gt;pipe,</div><div class='del'>-							kiq_ring-&gt;queue);</div><div class='ctx'> 	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='add'>+	dev_info(adev-&gt;dev, "kiq ring mec %d pipe %d q %d\n", kiq_ring-&gt;me,</div><div class='add'>+		 kiq_ring-&gt;pipe, kiq_ring-&gt;queue);</div><div class='add'>+</div><div class='ctx'> 	spin_lock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 	r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size *</div><div class='ctx'> 					adev-&gt;gfx.num_compute_rings +</div><div class='ctx'> 					kiq-&gt;pmf-&gt;set_resources_size);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to lock KIQ (%d).\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to lock KIQ (%d).\n", r);</div><div class='ctx'> 		spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes)</div><div class='del'>-		queue_mask = ~0ULL;</div><div class='del'>-</div><div class='ctx'> 	kiq-&gt;pmf-&gt;kiq_set_resources(kiq_ring, queue_mask);</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='ctx'> 		j = i + xcc_id * adev-&gt;gfx.num_compute_rings;</div><div class='ctx'> 		kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring,</div><div class='ctx'> 					 &amp;adev-&gt;gfx.compute_ring[j]);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	/* Submit map queue packet */</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	/*</div><div class='add'>+	 * Ring test will do a basic scratch register change check. Just run</div><div class='add'>+	 * this to ensure that map queues that is submitted before got</div><div class='add'>+	 * processed successfully before returning.</div><div class='add'>+	 */</div><div class='ctx'> 	r = amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> 	spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("KCQ enable failed\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "KCQ enable failed\n");</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -666,13 +729,27 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;mes.enable_legacy_queue_map) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+			j = i + xcc_id * adev-&gt;gfx.num_gfx_rings;</div><div class='add'>+			r = amdgpu_mes_map_legacy_queue(adev,</div><div class='add'>+							&amp;adev-&gt;gfx.gfx_ring[j]);</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev, "failed to map gfx queue\n");</div><div class='add'>+				return r;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	spin_lock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 	/* No need to map kcq on the slave */</div><div class='ctx'> 	if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {</div><div class='ctx'> 		r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size *</div><div class='ctx'> 						adev-&gt;gfx.num_gfx_rings);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to lock KIQ (%d).\n", r);</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to lock KIQ (%d).\n", r);</div><div class='ctx'> 			spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -683,27 +760,23 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 						 &amp;adev-&gt;gfx.gfx_ring[j]);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	/* Submit map queue packet */</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	/*</div><div class='add'>+	 * Ring test will do a basic scratch register change check. Just run</div><div class='add'>+	 * this to ensure that map queues that is submitted before got</div><div class='add'>+	 * processed successfully before returning.</div><div class='add'>+	 */</div><div class='ctx'> 	r = amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> 	spin_unlock(&amp;kiq-&gt;ring_lock);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("KGQ enable failed\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "KGQ enable failed\n");</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @bool enable true: enable gfx off feature, false: disable gfx off feature</div><div class='del'>- *</div><div class='del'>- * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.</div><div class='del'>- * 2. other client can send request to disable gfx off feature, the request should be honored.</div><div class='del'>- * 3. other client can cancel their request of disable gfx off feature</div><div class='del'>- * 4. other client should not send request to enable gfx off feature before disable gfx off feature.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)</div><div class='add'>+static void amdgpu_gfx_do_off_ctrl(struct amdgpu_device *adev, bool enable,</div><div class='add'>+				   bool no_delay)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long delay = GFX_OFF_DELAY_ENABLE;</div><div class='ctx'> </div><div class='hunk'>@@ -725,9 +798,9 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 		if (adev-&gt;gfx.gfx_off_req_count == 0 &amp;&amp;</div><div class='ctx'> 		    !adev-&gt;gfx.gfx_off_state) {</div><div class='ctx'> 			/* If going to s2idle, no need to wait */</div><div class='del'>-			if (adev-&gt;in_s0ix) {</div><div class='add'>+			if (no_delay) {</div><div class='ctx'> 				if (!amdgpu_dpm_set_powergating_by_smu(adev,</div><div class='del'>-						AMD_IP_BLOCK_TYPE_GFX, true))</div><div class='add'>+						AMD_IP_BLOCK_TYPE_GFX, true, 0))</div><div class='ctx'> 					adev-&gt;gfx.gfx_off_state = true;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				schedule_delayed_work(&amp;adev-&gt;gfx.gfx_off_delay_work,</div><div class='hunk'>@@ -739,7 +812,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 			cancel_delayed_work_sync(&amp;adev-&gt;gfx.gfx_off_delay_work);</div><div class='ctx'> </div><div class='ctx'> 			if (adev-&gt;gfx.gfx_off_state &amp;&amp;</div><div class='del'>-			    !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {</div><div class='add'>+			    !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false, 0)) {</div><div class='ctx'> 				adev-&gt;gfx.gfx_off_state = false;</div><div class='ctx'> </div><div class='ctx'> 				if (adev-&gt;gfx.funcs-&gt;init_spm_golden) {</div><div class='hunk'>@@ -757,6 +830,43 @@ unlock:</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;gfx.gfx_off_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @bool enable true: enable gfx off feature, false: disable gfx off feature</div><div class='add'>+ *</div><div class='add'>+ * 1. gfx off feature will be enabled by gfx ip after gfx cg pg enabled.</div><div class='add'>+ * 2. other client can send request to disable gfx off feature, the request should be honored.</div><div class='add'>+ * 3. other client can cancel their request of disable gfx off feature</div><div class='add'>+ * 4. other client should not send request to enable gfx off feature before disable gfx off feature.</div><div class='add'>+ *</div><div class='add'>+ * gfx off allow will be delayed by GFX_OFF_DELAY_ENABLE ms.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	/* If going to s2idle, no need to wait */</div><div class='add'>+	bool no_delay = adev-&gt;in_s0ix ? true : false;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_do_off_ctrl(adev, enable, no_delay);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* amdgpu_gfx_off_ctrl_immediate - Handle gfx off feature enable/disable</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @bool enable true: enable gfx off feature, false: disable gfx off feature</div><div class='add'>+ *</div><div class='add'>+ * 1. gfx off feature will be enabled by gfx ip after gfx cg pg enabled.</div><div class='add'>+ * 2. other client can send request to disable gfx off feature, the request should be honored.</div><div class='add'>+ * 3. other client can cancel their request of disable gfx off feature</div><div class='add'>+ * 4. other client should not send request to enable gfx off feature before disable gfx off feature.</div><div class='add'>+ *</div><div class='add'>+ * gfx off allow will be issued immediately.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_do_off_ctrl(adev, enable, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)</div><div class='ctx'> {</div><div class='ctx'> 	int r = 0;</div><div class='hunk'>@@ -815,13 +925,19 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ras_is_supported(adev, ras_block-&gt;block)) {</div><div class='del'>-		if (!amdgpu_persistent_edc_harvesting_supported(adev))</div><div class='del'>-			amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);</div><div class='add'>+		if (!amdgpu_persistent_edc_harvesting_supported(adev)) {</div><div class='add'>+			r = amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_ras_block_late_init(adev, ras_block);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='add'>+		if (amdgpu_sriov_vf(adev))</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;gfx.cp_ecc_error_irq.funcs) {</div><div class='ctx'> 			r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.cp_ecc_error_irq, 0);</div><div class='ctx'> 			if (r)</div><div class='hunk'>@@ -915,7 +1031,7 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	ih_data.head = *ras_if;</div><div class='ctx'> </div><div class='del'>-	DRM_ERROR("CP ECC ERROR IRQ\n");</div><div class='add'>+	dev_err(adev-&gt;dev, "CP ECC ERROR IRQ\n");</div><div class='ctx'> 	amdgpu_ras_interrupt_dispatch(adev, &amp;ih_data);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -950,7 +1066,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_</div><div class='ctx'> 	if (amdgpu_device_skip_hw_access(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mes.ring.sched.ready)</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready)</div><div class='ctx'> 		return amdgpu_mes_rreg(adev, reg);</div><div class='ctx'> </div><div class='ctx'> 	BUG_ON(!ring-&gt;funcs-&gt;emit_rreg);</div><div class='hunk'>@@ -960,7 +1076,10 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_</div><div class='ctx'> 		pr_err("critical bug! too many kiq readers\n");</div><div class='ctx'> 		goto failed_unlock;</div><div class='ctx'> 	}</div><div class='del'>-	amdgpu_ring_alloc(ring, 32);</div><div class='add'>+	r = amdgpu_ring_alloc(ring, 32);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failed_unlock;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);</div><div class='ctx'> 	r = amdgpu_fence_emit_polling(ring, &amp;seq, MAX_KIQ_REG_WAIT);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -984,6 +1103,9 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_</div><div class='ctx'> </div><div class='ctx'> 	might_sleep();</div><div class='ctx'> 	while (r &lt; 1 &amp;&amp; cnt++ &lt; MAX_KIQ_REG_TRY) {</div><div class='add'>+		if (amdgpu_in_reset(adev))</div><div class='add'>+			goto failed_kiq_read;</div><div class='add'>+</div><div class='ctx'> 		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);</div><div class='ctx'> 		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1020,13 +1142,16 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3</div><div class='ctx'> 	if (amdgpu_device_skip_hw_access(adev))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mes.ring.sched.ready) {</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready) {</div><div class='ctx'> 		amdgpu_mes_wreg(adev, reg, v);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='del'>-	amdgpu_ring_alloc(ring, 32);</div><div class='add'>+	r = amdgpu_ring_alloc(ring, 32);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failed_unlock;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_emit_wreg(ring, reg, v);</div><div class='ctx'> 	r = amdgpu_fence_emit_polling(ring, &amp;seq, MAX_KIQ_REG_WAIT);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -1050,6 +1175,8 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3</div><div class='ctx'> </div><div class='ctx'> 	might_sleep();</div><div class='ctx'> 	while (r &lt; 1 &amp;&amp; cnt++ &lt; MAX_KIQ_REG_TRY) {</div><div class='add'>+		if (amdgpu_in_reset(adev))</div><div class='add'>+			goto failed_kiq_write;</div><div class='ctx'> </div><div class='ctx'> 		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);</div><div class='ctx'> 		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='hunk'>@@ -1062,11 +1189,81 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3</div><div class='ctx'> </div><div class='ctx'> failed_undo:</div><div class='ctx'> 	amdgpu_ring_undo(ring);</div><div class='add'>+failed_unlock:</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='ctx'> failed_kiq_write:</div><div class='ctx'> 	dev_err(adev-&gt;dev, "failed to write reg:%x\n", reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	signed long r, cnt = 0;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	uint32_t seq;</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='add'>+	struct amdgpu_ring *ring = &amp;kiq-&gt;ring;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_device_skip_hw_access(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes_kiq &amp;&amp; adev-&gt;mes.ring[0].sched.ready)</div><div class='add'>+		return amdgpu_mes_hdp_flush(adev);</div><div class='add'>+</div><div class='add'>+	if (!ring-&gt;funcs-&gt;emit_hdp_flush) {</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	r = amdgpu_ring_alloc(ring, 32);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failed_unlock;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_emit_hdp_flush(ring);</div><div class='add'>+	r = amdgpu_fence_emit_polling(ring, &amp;seq, MAX_KIQ_REG_WAIT);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failed_undo;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_commit(ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='add'>+</div><div class='add'>+	/* don't wait anymore for gpu reset case because this way may</div><div class='add'>+	 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg</div><div class='add'>+	 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will</div><div class='add'>+	 * never return if we keep waiting in virt_kiq_rreg, which cause</div><div class='add'>+	 * gpu_recover() hang there.</div><div class='add'>+	 *</div><div class='add'>+	 * also don't wait anymore for IRQ context</div><div class='add'>+	 * */</div><div class='add'>+	if (r &lt; 1 &amp;&amp; (amdgpu_in_reset(adev) || in_interrupt()))</div><div class='add'>+		goto failed_kiq_hdp_flush;</div><div class='add'>+</div><div class='add'>+	might_sleep();</div><div class='add'>+	while (r &lt; 1 &amp;&amp; cnt++ &lt; MAX_KIQ_REG_TRY) {</div><div class='add'>+		if (amdgpu_in_reset(adev))</div><div class='add'>+			goto failed_kiq_hdp_flush;</div><div class='add'>+</div><div class='add'>+		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);</div><div class='add'>+		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cnt &gt; MAX_KIQ_REG_TRY) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to flush HDP via KIQ timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+failed_undo:</div><div class='add'>+	amdgpu_ring_undo(ring);</div><div class='add'>+failed_unlock:</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+failed_kiq_hdp_flush:</div><div class='add'>+	dev_err(adev-&gt;dev, "failed to flush HDP via KIQ\n");</div><div class='add'>+	return r &lt; 0 ? r : -EIO;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_num_kcq == -1) {</div><div class='hunk'>@@ -1206,7 +1403,8 @@ void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 		fw_size = le32_to_cpu(cp_hdr_v2_0-&gt;data_size_bytes);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		break;</div><div class='add'>+		dev_err(adev-&gt;dev, "Invalid ucode id %u\n", ucode_id);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='hunk'>@@ -1231,6 +1429,10 @@ static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='ctx'> 	int mode;</div><div class='ctx'> </div><div class='add'>+	/* Only minimal precaution taken to reject requests while in reset.*/</div><div class='add'>+	if (amdgpu_in_reset(adev))</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='ctx'> 	mode = amdgpu_xcp_query_partition_mode(adev-&gt;xcp_mgr,</div><div class='ctx'> 					       AMDGPU_XCP_FL_NONE);</div><div class='ctx'> </div><div class='hunk'>@@ -1274,67 +1476,1082 @@ static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Don't allow a switch while under reset */</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='ctx'> 	ret = amdgpu_xcp_switch_partition_mode(adev-&gt;xcp_mgr, mode);</div><div class='ctx'> </div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const char *xcp_desc[] = {</div><div class='add'>+	[AMDGPU_SPX_PARTITION_MODE] = "SPX",</div><div class='add'>+	[AMDGPU_DPX_PARTITION_MODE] = "DPX",</div><div class='add'>+	[AMDGPU_TPX_PARTITION_MODE] = "TPX",</div><div class='add'>+	[AMDGPU_QPX_PARTITION_MODE] = "QPX",</div><div class='add'>+	[AMDGPU_CPX_PARTITION_MODE] = "CPX",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,</div><div class='ctx'> 						struct device_attribute *addr,</div><div class='ctx'> 						char *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='del'>-	char *supported_partition;</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr = adev-&gt;xcp_mgr;</div><div class='add'>+	int size = 0, mode;</div><div class='add'>+	char *sep = "";</div><div class='ctx'> </div><div class='del'>-	/* TBD */</div><div class='del'>-	switch (NUM_XCC(adev-&gt;gfx.xcc_mask)) {</div><div class='del'>-	case 8:</div><div class='del'>-		supported_partition = "SPX, DPX, QPX, CPX";</div><div class='del'>-		break;</div><div class='del'>-	case 6:</div><div class='del'>-		supported_partition = "SPX, TPX, CPX";</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		supported_partition = "SPX, DPX, CPX";</div><div class='del'>-		break;</div><div class='del'>-	/* this seems only existing in emulation phase */</div><div class='del'>-	case 2:</div><div class='del'>-		supported_partition = "SPX, CPX";</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		supported_partition = "Not supported";</div><div class='del'>-		break;</div><div class='add'>+	if (!xcp_mgr || !xcp_mgr-&gt;avail_xcp_modes)</div><div class='add'>+		return sysfs_emit(buf, "Not supported\n");</div><div class='add'>+</div><div class='add'>+	for_each_inst(mode, xcp_mgr-&gt;avail_xcp_modes) {</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s%s", sep, xcp_desc[mode]);</div><div class='add'>+		sep = ", ";</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct drm_gpu_scheduler *sched = &amp;ring-&gt;sched;</div><div class='add'>+	struct drm_sched_entity entity;</div><div class='add'>+	static atomic_t counter;</div><div class='add'>+	struct dma_fence *f;</div><div class='add'>+	struct amdgpu_job *job;</div><div class='add'>+	struct amdgpu_ib *ib;</div><div class='add'>+	void *owner;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	/* Initialize the scheduler entity */</div><div class='add'>+	r = drm_sched_entity_init(&amp;entity, DRM_SCHED_PRIORITY_NORMAL,</div><div class='add'>+				  &amp;sched, 1, NULL);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed setting up GFX kernel entity.\n");</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Use some unique dummy value as the owner to make sure we execute</div><div class='add'>+	 * the cleaner shader on each submission. The value just need to change</div><div class='add'>+	 * for each submission and is otherwise meaningless.</div><div class='add'>+	 */</div><div class='add'>+	owner = (void *)(unsigned long)atomic_inc_return(&amp;counter);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, &amp;entity, owner,</div><div class='add'>+				     64, 0, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER);</div><div class='add'>+	if (r)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	job-&gt;enforce_isolation = true;</div><div class='add'>+	/* always run the cleaner shader */</div><div class='add'>+	job-&gt;run_cleaner_shader = true;</div><div class='add'>+</div><div class='add'>+	ib = &amp;job-&gt;ibs[0];</div><div class='add'>+	for (i = 0; i &lt;= ring-&gt;funcs-&gt;align_mask; ++i)</div><div class='add'>+		ib-&gt;ptr[i] = ring-&gt;funcs-&gt;nop;</div><div class='add'>+	ib-&gt;length_dw = ring-&gt;funcs-&gt;align_mask + 1;</div><div class='add'>+</div><div class='add'>+	f = amdgpu_job_submit(job);</div><div class='add'>+</div><div class='add'>+	r = dma_fence_wait(f, false);</div><div class='add'>+	if (r)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	dma_fence_put(f);</div><div class='add'>+</div><div class='add'>+	/* Clean up the scheduler entity */</div><div class='add'>+	drm_sched_entity_destroy(&amp;entity);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_gfx_run_cleaner_shader(struct amdgpu_device *adev, int xcp_id)</div><div class='add'>+{</div><div class='add'>+	int num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int num_xcc_to_clear;</div><div class='add'>+	int i, r, xcc_id;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_xcc_per_xcp)</div><div class='add'>+		num_xcc_to_clear = adev-&gt;gfx.num_xcc_per_xcp;</div><div class='add'>+	else</div><div class='add'>+		num_xcc_to_clear = 1;</div><div class='add'>+</div><div class='add'>+	for (xcc_id = 0; xcc_id &lt; num_xcc; xcc_id++) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+			ring = &amp;adev-&gt;gfx.compute_ring[i + xcc_id * adev-&gt;gfx.num_compute_rings];</div><div class='add'>+			if ((ring-&gt;xcp_id == xcp_id) &amp;&amp; ring-&gt;sched.ready) {</div><div class='add'>+				r = amdgpu_gfx_run_cleaner_shader_job(ring);</div><div class='add'>+				if (r)</div><div class='add'>+					return r;</div><div class='add'>+				num_xcc_to_clear--;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (num_xcc_to_clear)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_set_run_cleaner_shader - Execute the AMDGPU GFX Cleaner Shader</div><div class='add'>+ * @dev: The device structure</div><div class='add'>+ * @attr: The device attribute structure</div><div class='add'>+ * @buf: The buffer containing the input data</div><div class='add'>+ * @count: The size of the input data</div><div class='add'>+ *</div><div class='add'>+ * Provides the sysfs interface to manually run a cleaner shader, which is</div><div class='add'>+ * used to clear the GPU state between different tasks. Writing a value to the</div><div class='add'>+ * 'run_cleaner_shader' sysfs file triggers the cleaner shader execution.</div><div class='add'>+ * The value written corresponds to the partition index on multi-partition</div><div class='add'>+ * devices. On single-partition devices, the value should be '0'.</div><div class='add'>+ *</div><div class='add'>+ * The cleaner shader clears the Local Data Store (LDS) and General Purpose</div><div class='add'>+ * Registers (GPRs) to ensure data isolation between GPU workloads.</div><div class='add'>+ *</div><div class='add'>+ * Return: The number of bytes written to the sysfs file.</div><div class='add'>+ */</div><div class='add'>+static ssize_t amdgpu_gfx_set_run_cleaner_shader(struct device *dev,</div><div class='add'>+						 struct device_attribute *attr,</div><div class='add'>+						 const char *buf,</div><div class='add'>+						 size_t count)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	int ret;</div><div class='add'>+	long value;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_in_reset(adev))</div><div class='add'>+		return -EPERM;</div><div class='add'>+	if (adev-&gt;in_suspend &amp;&amp; !adev-&gt;in_runpm)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.disable_kq)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	ret = kstrtol(buf, 0, &amp;value);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (value &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;xcp_mgr) {</div><div class='add'>+		if (value &gt;= adev-&gt;xcp_mgr-&gt;num_xcps)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	} else {</div><div class='add'>+		if (value &gt; 1)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_get_sync(ddev-&gt;dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		pm_runtime_put_autosuspend(ddev-&gt;dev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_gfx_run_cleaner_shader(adev, value);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_autosuspend(ddev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_get_enforce_isolation - Query AMDGPU GFX Enforce Isolation Settings</div><div class='add'>+ * @dev: The device structure</div><div class='add'>+ * @attr: The device attribute structure</div><div class='add'>+ * @buf: The buffer to store the output data</div><div class='add'>+ *</div><div class='add'>+ * Provides the sysfs read interface to get the current settings of the 'enforce_isolation'</div><div class='add'>+ * feature for each GPU partition. Reading from the 'enforce_isolation'</div><div class='add'>+ * sysfs file returns the isolation settings for all partitions, where '0'</div><div class='add'>+ * indicates disabled, '1' indicates enabled, and '2' indicates enabled in legacy mode,</div><div class='add'>+ * and '3' indicates enabled without cleaner shader.</div><div class='add'>+ *</div><div class='add'>+ * Return: The number of bytes read from the sysfs file.</div><div class='add'>+ */</div><div class='add'>+static ssize_t amdgpu_gfx_get_enforce_isolation(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	int i;</div><div class='add'>+	ssize_t size = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;xcp_mgr) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;xcp_mgr-&gt;num_xcps; i++) {</div><div class='add'>+			size += sysfs_emit_at(buf, size, "%u", adev-&gt;enforce_isolation[i]);</div><div class='add'>+			if (i &lt; (adev-&gt;xcp_mgr-&gt;num_xcps - 1))</div><div class='add'>+				size += sysfs_emit_at(buf, size, " ");</div><div class='add'>+		}</div><div class='add'>+		buf[size++] = '\n';</div><div class='add'>+	} else {</div><div class='add'>+		size = sysfs_emit_at(buf, 0, "%u\n", adev-&gt;enforce_isolation[0]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_set_enforce_isolation - Control AMDGPU GFX Enforce Isolation</div><div class='add'>+ * @dev: The device structure</div><div class='add'>+ * @attr: The device attribute structure</div><div class='add'>+ * @buf: The buffer containing the input data</div><div class='add'>+ * @count: The size of the input data</div><div class='add'>+ *</div><div class='add'>+ * This function allows control over the 'enforce_isolation' feature, which</div><div class='add'>+ * serializes access to the graphics engine. Writing '0' to disable, '1' to</div><div class='add'>+ * enable isolation with cleaner shader, '2' to enable legacy isolation without</div><div class='add'>+ * cleaner shader, or '3' to enable process isolation without submitting the</div><div class='add'>+ * cleaner shader to the 'enforce_isolation' sysfs file sets the isolation mode</div><div class='add'>+ * for each partition. The input should specify the setting for all</div><div class='add'>+ * partitions.</div><div class='add'>+ *</div><div class='add'>+ * Return: The number of bytes written to the sysfs file.</div><div class='add'>+ */</div><div class='add'>+static ssize_t amdgpu_gfx_set_enforce_isolation(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	long partition_values[MAX_XCP] = {0};</div><div class='add'>+	int ret, i, num_partitions;</div><div class='add'>+	const char *input_buf = buf;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; (adev-&gt;xcp_mgr ? adev-&gt;xcp_mgr-&gt;num_xcps : 1); i++) {</div><div class='add'>+		ret = sscanf(input_buf, "%ld", &amp;partition_values[i]);</div><div class='add'>+		if (ret &lt;= 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		/* Move the pointer to the next value in the string */</div><div class='add'>+		input_buf = strchr(input_buf, ' ');</div><div class='add'>+		if (input_buf) {</div><div class='add'>+			input_buf++;</div><div class='add'>+		} else {</div><div class='add'>+			i++;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	num_partitions = i;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;xcp_mgr &amp;&amp; num_partitions != adev-&gt;xcp_mgr-&gt;num_xcps)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;xcp_mgr &amp;&amp; num_partitions != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_partitions; i++) {</div><div class='add'>+		if (partition_values[i] != 0 &amp;&amp;</div><div class='add'>+		    partition_values[i] != 1 &amp;&amp;</div><div class='add'>+		    partition_values[i] != 2 &amp;&amp;</div><div class='add'>+		    partition_values[i] != 3)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	for (i = 0; i &lt; num_partitions; i++) {</div><div class='add'>+		switch (partition_values[i]) {</div><div class='add'>+		case 0:</div><div class='add'>+		default:</div><div class='add'>+			adev-&gt;enforce_isolation[i] = AMDGPU_ENFORCE_ISOLATION_DISABLE;</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			adev-&gt;enforce_isolation[i] =</div><div class='add'>+				AMDGPU_ENFORCE_ISOLATION_ENABLE;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			adev-&gt;enforce_isolation[i] =</div><div class='add'>+				AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			adev-&gt;enforce_isolation[i] =</div><div class='add'>+				AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_update_enforce_isolation(adev);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_gfx_get_gfx_reset_mask(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	return amdgpu_show_reset_mask(buf, adev-&gt;gfx.gfx_supported_reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_gfx_get_compute_reset_mask(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	return sysfs_emit(buf, "%s\n", supported_partition);</div><div class='add'>+	return amdgpu_show_reset_mask(buf, adev-&gt;gfx.compute_supported_reset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static DEVICE_ATTR(run_cleaner_shader, 0200,</div><div class='add'>+		   NULL, amdgpu_gfx_set_run_cleaner_shader);</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR(enforce_isolation, 0644,</div><div class='add'>+		   amdgpu_gfx_get_enforce_isolation,</div><div class='add'>+		   amdgpu_gfx_set_enforce_isolation);</div><div class='add'>+</div><div class='ctx'> static DEVICE_ATTR(current_compute_partition, 0644,</div><div class='ctx'> 		   amdgpu_gfx_get_current_compute_partition,</div><div class='ctx'> 		   amdgpu_gfx_set_compute_partition);</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(available_compute_partition, 0444,</div><div class='ctx'> 		   amdgpu_gfx_get_available_compute_partition, NULL);</div><div class='add'>+static DEVICE_ATTR(gfx_reset_mask, 0444,</div><div class='add'>+		   amdgpu_gfx_get_gfx_reset_mask, NULL);</div><div class='ctx'> </div><div class='del'>-int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)</div><div class='add'>+static DEVICE_ATTR(compute_reset_mask, 0444,</div><div class='add'>+		   amdgpu_gfx_get_compute_reset_mask, NULL);</div><div class='add'>+</div><div class='add'>+static int amdgpu_gfx_sysfs_xcp_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr = adev-&gt;xcp_mgr;</div><div class='add'>+	bool xcp_switch_supported;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	if (!xcp_mgr)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	xcp_switch_supported =</div><div class='add'>+		(xcp_mgr-&gt;funcs &amp;&amp; xcp_mgr-&gt;funcs-&gt;switch_partition_mode);</div><div class='add'>+</div><div class='add'>+	if (!xcp_switch_supported)</div><div class='add'>+		dev_attr_current_compute_partition.attr.mode &amp;=</div><div class='add'>+			~(S_IWUSR | S_IWGRP | S_IWOTH);</div><div class='add'>+</div><div class='ctx'> 	r = device_create_file(adev-&gt;dev, &amp;dev_attr_current_compute_partition);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = device_create_file(adev-&gt;dev, &amp;dev_attr_available_compute_partition);</div><div class='add'>+	if (xcp_switch_supported)</div><div class='add'>+		r = device_create_file(adev-&gt;dev,</div><div class='add'>+				       &amp;dev_attr_available_compute_partition);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)</div><div class='add'>+static void amdgpu_gfx_sysfs_xcp_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr = adev-&gt;xcp_mgr;</div><div class='add'>+	bool xcp_switch_supported;</div><div class='add'>+</div><div class='add'>+	if (!xcp_mgr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xcp_switch_supported =</div><div class='add'>+		(xcp_mgr-&gt;funcs &amp;&amp; xcp_mgr-&gt;funcs-&gt;switch_partition_mode);</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_current_compute_partition);</div><div class='del'>-	device_remove_file(adev-&gt;dev, &amp;dev_attr_available_compute_partition);</div><div class='add'>+</div><div class='add'>+	if (xcp_switch_supported)</div><div class='add'>+		device_remove_file(adev-&gt;dev,</div><div class='add'>+				   &amp;dev_attr_available_compute_partition);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = device_create_file(adev-&gt;dev, &amp;dev_attr_enforce_isolation);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	if (adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_run_cleaner_shader);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	device_remove_file(adev-&gt;dev, &amp;dev_attr_enforce_isolation);</div><div class='add'>+	if (adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_run_cleaner_shader);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_gfx_sysfs_reset_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_gpu_recovery)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings) {</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_gfx_reset_mask);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_compute_rings) {</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_compute_reset_mask);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_gfx_sysfs_reset_mask_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_gpu_recovery)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_gfx_reset_mask);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_compute_rings)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_compute_reset_mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_xcp_init(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to create xcp sysfs files");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_isolation_shader_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to create isolation sysfs files");</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to create reset mask sysfs files");</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd) {</div><div class='add'>+		amdgpu_gfx_sysfs_xcp_fini(adev);</div><div class='add'>+		amdgpu_gfx_sysfs_isolation_shader_fini(adev);</div><div class='add'>+		amdgpu_gfx_sysfs_reset_mask_fini(adev);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev,</div><div class='add'>+				      unsigned int cleaner_shader_size)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return amdgpu_bo_create_kernel(adev, cleaner_shader_size, PAGE_SIZE,</div><div class='add'>+				       AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				       &amp;adev-&gt;gfx.cleaner_shader_obj,</div><div class='add'>+				       &amp;adev-&gt;gfx.cleaner_shader_gpu_addr,</div><div class='add'>+				       (void **)&amp;adev-&gt;gfx.cleaner_shader_cpu_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.cleaner_shader_obj,</div><div class='add'>+			      &amp;adev-&gt;gfx.cleaner_shader_gpu_addr,</div><div class='add'>+			      (void **)&amp;adev-&gt;gfx.cleaner_shader_cpu_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev,</div><div class='add'>+				    unsigned int cleaner_shader_size,</div><div class='add'>+				    const void *cleaner_shader_ptr)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.cleaner_shader_cpu_ptr &amp;&amp; cleaner_shader_ptr)</div><div class='add'>+		memcpy_toio(adev-&gt;gfx.cleaner_shader_cpu_ptr, cleaner_shader_ptr,</div><div class='add'>+			    cleaner_shader_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_kfd_sch_ctrl - Control the KFD scheduler from the KGD (Graphics Driver)</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @idx: Index of the scheduler to control</div><div class='add'>+ * @enable: Whether to enable or disable the KFD scheduler</div><div class='add'>+ *</div><div class='add'>+ * This function is used to control the KFD (Kernel Fusion Driver) scheduler</div><div class='add'>+ * from the KGD. It is part of the cleaner shader feature. This function plays</div><div class='add'>+ * a key role in enforcing process isolation on the GPU.</div><div class='add'>+ *</div><div class='add'>+ * The function uses a reference count mechanism (kfd_sch_req_count) to keep</div><div class='add'>+ * track of the number of requests to enable the KFD scheduler. When a request</div><div class='add'>+ * to enable the KFD scheduler is made, the reference count is decremented.</div><div class='add'>+ * When the reference count reaches zero, a delayed work is scheduled to</div><div class='add'>+ * enforce isolation after a delay of GFX_SLICE_PERIOD.</div><div class='add'>+ *</div><div class='add'>+ * When a request to disable the KFD scheduler is made, the function first</div><div class='add'>+ * checks if the reference count is zero. If it is, it cancels the delayed work</div><div class='add'>+ * for enforcing isolation and checks if the KFD scheduler is active. If the</div><div class='add'>+ * KFD scheduler is active, it sends a request to stop the KFD scheduler and</div><div class='add'>+ * sets the KFD scheduler state to inactive. Then, it increments the reference</div><div class='add'>+ * count.</div><div class='add'>+ *</div><div class='add'>+ * The function is synchronized using the kfd_sch_mutex to ensure that the KFD</div><div class='add'>+ * scheduler state and reference count are updated atomically.</div><div class='add'>+ *</div><div class='add'>+ * Note: If the reference count is already zero when a request to enable the</div><div class='add'>+ * KFD scheduler is made, it means there's an imbalance bug somewhere. The</div><div class='add'>+ * function triggers a warning in this case.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_gfx_kfd_sch_ctrl(struct amdgpu_device *adev, u32 idx,</div><div class='add'>+				    bool enable)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;adev-&gt;gfx.userq_sch_mutex);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		/* If the count is already 0, it means there's an imbalance bug somewhere.</div><div class='add'>+		 * Note that the bug may be in a different caller than the one which triggers the</div><div class='add'>+		 * WARN_ON_ONCE.</div><div class='add'>+		 */</div><div class='add'>+		if (WARN_ON_ONCE(adev-&gt;gfx.userq_sch_req_count[idx] == 0)) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Attempted to enable KFD scheduler when reference count is already zero\n");</div><div class='add'>+			goto unlock;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;gfx.userq_sch_req_count[idx]--;</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;gfx.userq_sch_req_count[idx] == 0 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.userq_sch_inactive[idx]) {</div><div class='add'>+			schedule_delayed_work(&amp;adev-&gt;gfx.enforce_isolation[idx].work,</div><div class='add'>+					      msecs_to_jiffies(adev-&gt;gfx.enforce_isolation_time[idx]));</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;gfx.userq_sch_req_count[idx] == 0) {</div><div class='add'>+			cancel_delayed_work_sync(&amp;adev-&gt;gfx.enforce_isolation[idx].work);</div><div class='add'>+			if (!adev-&gt;gfx.userq_sch_inactive[idx]) {</div><div class='add'>+				amdgpu_userq_stop_sched_for_enforce_isolation(adev, idx);</div><div class='add'>+				if (adev-&gt;kfd.init_complete)</div><div class='add'>+					amdgpu_amdkfd_stop_sched(adev, idx);</div><div class='add'>+				adev-&gt;gfx.userq_sch_inactive[idx] = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;gfx.userq_sch_req_count[idx]++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;gfx.userq_sch_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_enforce_isolation_handler - work handler for enforcing shader isolation</div><div class='add'>+ *</div><div class='add'>+ * @work: work_struct.</div><div class='add'>+ *</div><div class='add'>+ * This function is the work handler for enforcing shader isolation on AMD GPUs.</div><div class='add'>+ * It counts the number of emitted fences for each GFX and compute ring. If there</div><div class='add'>+ * are any fences, it schedules the `enforce_isolation_work` to be run after a</div><div class='add'>+ * delay of `GFX_SLICE_PERIOD`. If there are no fences, it signals the Kernel Fusion</div><div class='add'>+ * Driver (KFD) to resume the runqueue. The function is synchronized using the</div><div class='add'>+ * `enforce_isolation_mutex`.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_isolation_work *isolation_work =</div><div class='add'>+		container_of(work, struct amdgpu_isolation_work, work.work);</div><div class='add'>+	struct amdgpu_device *adev = isolation_work-&gt;adev;</div><div class='add'>+	u32 i, idx, fences = 0;</div><div class='add'>+</div><div class='add'>+	if (isolation_work-&gt;xcp_id == AMDGPU_XCP_NO_PARTITION)</div><div class='add'>+		idx = 0;</div><div class='add'>+	else</div><div class='add'>+		idx = isolation_work-&gt;xcp_id;</div><div class='add'>+</div><div class='add'>+	if (idx &gt;= MAX_XCP)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_GFX_RINGS; ++i) {</div><div class='add'>+		if (isolation_work-&gt;xcp_id == adev-&gt;gfx.gfx_ring[i].xcp_id)</div><div class='add'>+			fences += amdgpu_fence_count_emitted(&amp;adev-&gt;gfx.gfx_ring[i]);</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; (AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES); ++i) {</div><div class='add'>+		if (isolation_work-&gt;xcp_id == adev-&gt;gfx.compute_ring[i].xcp_id)</div><div class='add'>+			fences += amdgpu_fence_count_emitted(&amp;adev-&gt;gfx.compute_ring[i]);</div><div class='add'>+	}</div><div class='add'>+	if (fences) {</div><div class='add'>+		/* we've already had our timeslice, so let's wrap this up */</div><div class='add'>+		schedule_delayed_work(&amp;adev-&gt;gfx.enforce_isolation[idx].work,</div><div class='add'>+				      msecs_to_jiffies(1));</div><div class='add'>+	} else {</div><div class='add'>+		/* Tell KFD to resume the runqueue */</div><div class='add'>+		WARN_ON_ONCE(!adev-&gt;gfx.userq_sch_inactive[idx]);</div><div class='add'>+		WARN_ON_ONCE(adev-&gt;gfx.userq_sch_req_count[idx]);</div><div class='add'>+</div><div class='add'>+		amdgpu_userq_start_sched_for_enforce_isolation(adev, idx);</div><div class='add'>+		if (adev-&gt;kfd.init_complete)</div><div class='add'>+			amdgpu_amdkfd_start_sched(adev, idx);</div><div class='add'>+		adev-&gt;gfx.userq_sch_inactive[idx] = false;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_enforce_isolation_wait_for_kfd - Manage KFD wait period for process isolation</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @idx: Index of the GPU partition</div><div class='add'>+ *</div><div class='add'>+ * When kernel submissions come in, the jobs are given a time slice and once</div><div class='add'>+ * that time slice is up, if there are KFD user queues active, kernel</div><div class='add'>+ * submissions are blocked until KFD has had its time slice. Once the KFD time</div><div class='add'>+ * slice is up, KFD user queues are preempted and kernel submissions are</div><div class='add'>+ * unblocked and allowed to run again.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+amdgpu_gfx_enforce_isolation_wait_for_kfd(struct amdgpu_device *adev,</div><div class='add'>+					  u32 idx)</div><div class='add'>+{</div><div class='add'>+	unsigned long cjiffies;</div><div class='add'>+	bool wait = false;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	if (adev-&gt;enforce_isolation[idx] == AMDGPU_ENFORCE_ISOLATION_ENABLE) {</div><div class='add'>+		/* set the initial values if nothing is set */</div><div class='add'>+		if (!adev-&gt;gfx.enforce_isolation_jiffies[idx]) {</div><div class='add'>+			adev-&gt;gfx.enforce_isolation_jiffies[idx] = jiffies;</div><div class='add'>+			adev-&gt;gfx.enforce_isolation_time[idx] =	GFX_SLICE_PERIOD_MS;</div><div class='add'>+		}</div><div class='add'>+		/* Make sure KFD gets a chance to run */</div><div class='add'>+		if (amdgpu_amdkfd_compute_active(adev, idx)) {</div><div class='add'>+			cjiffies = jiffies;</div><div class='add'>+			if (time_after(cjiffies, adev-&gt;gfx.enforce_isolation_jiffies[idx])) {</div><div class='add'>+				cjiffies -= adev-&gt;gfx.enforce_isolation_jiffies[idx];</div><div class='add'>+				if ((jiffies_to_msecs(cjiffies) &gt;= GFX_SLICE_PERIOD_MS)) {</div><div class='add'>+					/* if our time is up, let KGD work drain before scheduling more */</div><div class='add'>+					wait = true;</div><div class='add'>+					/* reset the timer period */</div><div class='add'>+					adev-&gt;gfx.enforce_isolation_time[idx] =	GFX_SLICE_PERIOD_MS;</div><div class='add'>+				} else {</div><div class='add'>+					/* set the timer period to what's left in our time slice */</div><div class='add'>+					adev-&gt;gfx.enforce_isolation_time[idx] =</div><div class='add'>+						GFX_SLICE_PERIOD_MS - jiffies_to_msecs(cjiffies);</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				/* if jiffies wrap around we will just wait a little longer */</div><div class='add'>+				adev-&gt;gfx.enforce_isolation_jiffies[idx] = jiffies;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* if there is no KFD work, then set the full slice period */</div><div class='add'>+			adev-&gt;gfx.enforce_isolation_jiffies[idx] = jiffies;</div><div class='add'>+			adev-&gt;gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+</div><div class='add'>+	if (wait)</div><div class='add'>+		msleep(GFX_SLICE_PERIOD_MS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_enforce_isolation_ring_begin_use - Begin use of a ring with enforced isolation</div><div class='add'>+ * @ring: Pointer to the amdgpu_ring structure</div><div class='add'>+ *</div><div class='add'>+ * Ring begin_use helper implementation for gfx which serializes access to the</div><div class='add'>+ * gfx IP between kernel submission IOCTLs and KFD user queues when isolation</div><div class='add'>+ * enforcement is enabled. The kernel submission IOCTLs and KFD user queues</div><div class='add'>+ * each get a time slice when both are active.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 idx;</div><div class='add'>+	bool sched_work = false;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;xcp_id == AMDGPU_XCP_NO_PARTITION)</div><div class='add'>+		idx = 0;</div><div class='add'>+	else</div><div class='add'>+		idx = ring-&gt;xcp_id;</div><div class='add'>+</div><div class='add'>+	if (idx &gt;= MAX_XCP)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Don't submit more work until KFD has had some time */</div><div class='add'>+	amdgpu_gfx_enforce_isolation_wait_for_kfd(adev, idx);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	if (adev-&gt;enforce_isolation[idx] == AMDGPU_ENFORCE_ISOLATION_ENABLE) {</div><div class='add'>+		if (adev-&gt;kfd.init_complete)</div><div class='add'>+			sched_work = true;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+</div><div class='add'>+	if (sched_work)</div><div class='add'>+		amdgpu_gfx_kfd_sch_ctrl(adev, idx, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_enforce_isolation_ring_end_use - End use of a ring with enforced isolation</div><div class='add'>+ * @ring: Pointer to the amdgpu_ring structure</div><div class='add'>+ *</div><div class='add'>+ * Ring end_use helper implementation for gfx which serializes access to the</div><div class='add'>+ * gfx IP between kernel submission IOCTLs and KFD user queues when isolation</div><div class='add'>+ * enforcement is enabled. The kernel submission IOCTLs and KFD user queues</div><div class='add'>+ * each get a time slice when both are active.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 idx;</div><div class='add'>+	bool sched_work = false;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.enable_cleaner_shader)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;xcp_id == AMDGPU_XCP_NO_PARTITION)</div><div class='add'>+		idx = 0;</div><div class='add'>+	else</div><div class='add'>+		idx = ring-&gt;xcp_id;</div><div class='add'>+</div><div class='add'>+	if (idx &gt;= MAX_XCP)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	if (adev-&gt;enforce_isolation[idx] == AMDGPU_ENFORCE_ISOLATION_ENABLE) {</div><div class='add'>+		if (adev-&gt;kfd.init_complete)</div><div class='add'>+			sched_work = true;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+</div><div class='add'>+	if (sched_work)</div><div class='add'>+		amdgpu_gfx_kfd_sch_ctrl(adev, idx, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev =</div><div class='add'>+		container_of(work, struct amdgpu_device, gfx.idle_work.work);</div><div class='add'>+	enum PP_SMC_POWER_PROFILE profile;</div><div class='add'>+	u32 i, fences = 0;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+		profile = PP_SMC_POWER_PROFILE_FULLSCREEN3D;</div><div class='add'>+	else</div><div class='add'>+		profile = PP_SMC_POWER_PROFILE_COMPUTE;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_GFX_RINGS; ++i)</div><div class='add'>+		fences += amdgpu_fence_count_emitted(&amp;adev-&gt;gfx.gfx_ring[i]);</div><div class='add'>+	for (i = 0; i &lt; (AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES); ++i)</div><div class='add'>+		fences += amdgpu_fence_count_emitted(&amp;adev-&gt;gfx.compute_ring[i]);</div><div class='add'>+	if (!fences &amp;&amp; !atomic_read(&amp;adev-&gt;gfx.total_submission_cnt)) {</div><div class='add'>+		mutex_lock(&amp;adev-&gt;gfx.workload_profile_mutex);</div><div class='add'>+		if (adev-&gt;gfx.workload_profile_active) {</div><div class='add'>+			r = amdgpu_dpm_switch_power_profile(adev, profile, false);</div><div class='add'>+			if (r)</div><div class='add'>+				dev_warn(adev-&gt;dev, "(%d) failed to disable %s power profile mode\n", r,</div><div class='add'>+					 profile == PP_SMC_POWER_PROFILE_FULLSCREEN3D ?</div><div class='add'>+					 "fullscreen 3D" : "compute");</div><div class='add'>+			adev-&gt;gfx.workload_profile_active = false;</div><div class='add'>+		}</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;gfx.workload_profile_mutex);</div><div class='add'>+	} else {</div><div class='add'>+		schedule_delayed_work(&amp;adev-&gt;gfx.idle_work, GFX_PROFILE_IDLE_TIMEOUT);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	enum PP_SMC_POWER_PROFILE profile;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dpm_is_overdrive_enabled(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+		profile = PP_SMC_POWER_PROFILE_FULLSCREEN3D;</div><div class='add'>+	else</div><div class='add'>+		profile = PP_SMC_POWER_PROFILE_COMPUTE;</div><div class='add'>+</div><div class='add'>+	atomic_inc(&amp;adev-&gt;gfx.total_submission_cnt);</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;gfx.idle_work);</div><div class='add'>+</div><div class='add'>+	/* We can safely return early here because we've cancelled the</div><div class='add'>+	 * the delayed work so there is no one else to set it to false</div><div class='add'>+	 * and we don't care if someone else sets it to true.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;gfx.workload_profile_active)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;gfx.workload_profile_mutex);</div><div class='add'>+	if (!adev-&gt;gfx.workload_profile_active) {</div><div class='add'>+		r = amdgpu_dpm_switch_power_profile(adev, profile, true);</div><div class='add'>+		if (r)</div><div class='add'>+			dev_warn(adev-&gt;dev, "(%d) failed to disable %s power profile mode\n", r,</div><div class='add'>+				 profile == PP_SMC_POWER_PROFILE_FULLSCREEN3D ?</div><div class='add'>+				 "fullscreen 3D" : "compute");</div><div class='add'>+		adev-&gt;gfx.workload_profile_active = true;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;gfx.workload_profile_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dpm_is_overdrive_enabled(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	atomic_dec(&amp;ring-&gt;adev-&gt;gfx.total_submission_cnt);</div><div class='add'>+</div><div class='add'>+	schedule_delayed_work(&amp;ring-&gt;adev-&gt;gfx.idle_work, GFX_PROFILE_IDLE_TIMEOUT);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_csb_preamble_start - Set CSB preamble start</div><div class='add'>+ *</div><div class='add'>+ * @buffer: This is an output variable that gets the PACKET3 preamble setup.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ * return the latest index.</div><div class='add'>+ */</div><div class='add'>+u32 amdgpu_gfx_csb_preamble_start(u32 *buffer)</div><div class='add'>+{</div><div class='add'>+	u32 count = 0;</div><div class='add'>+</div><div class='add'>+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='add'>+	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='add'>+</div><div class='add'>+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='add'>+	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='add'>+	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_csb_data_parser - Parser CS data</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer used to get the CS data and other gfx info.</div><div class='add'>+ * @buffer: This is an output variable that gets the PACKET3 preamble end.</div><div class='add'>+ * @count: Index to start set the preemble end.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ * return the latest index.</div><div class='add'>+ */</div><div class='add'>+u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count)</div><div class='add'>+{</div><div class='add'>+	const struct cs_section_def *sect = NULL;</div><div class='add'>+	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='add'>+		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='add'>+			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='add'>+				buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='add'>+				buffer[count++] = cpu_to_le32(ext-&gt;reg_index - PACKET3_SET_CONTEXT_REG_START);</div><div class='add'>+</div><div class='add'>+				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='add'>+					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_gfx_csb_preamble_end - Set CSB preamble end</div><div class='add'>+ *</div><div class='add'>+ * @buffer: This is an output variable that gets the PACKET3 preamble end.</div><div class='add'>+ * @count: Index to start set the preemble end.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count)</div><div class='add'>+{</div><div class='add'>+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='add'>+	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='add'>+</div><div class='add'>+	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='add'>+	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * debugfs for to enable/disable gfx job submission to specific core.</div><div class='add'>+ */</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int amdgpu_debugfs_gfx_sched_mask_set(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	mask = (1ULL &lt;&lt; adev-&gt;gfx.num_gfx_rings) - 1;</div><div class='add'>+	if ((val &amp; mask) == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+		if (val &amp; (1 &lt;&lt; i))</div><div class='add'>+			ring-&gt;sched.ready = true;</div><div class='add'>+		else</div><div class='add'>+			ring-&gt;sched.ready = false;</div><div class='add'>+	}</div><div class='add'>+	/* publish sched.ready flag update effective immediately across smp */</div><div class='add'>+	smp_rmb();</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+		if (ring-&gt;sched.ready)</div><div class='add'>+			mask |= 1ULL &lt;&lt; i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = mask;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops,</div><div class='add'>+			 amdgpu_debugfs_gfx_sched_mask_get,</div><div class='add'>+			 amdgpu_debugfs_gfx_sched_mask_set, "%llx\n");</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	char name[32];</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;gfx.num_gfx_rings &gt; 1))</div><div class='add'>+		return;</div><div class='add'>+	sprintf(name, "amdgpu_gfx_sched_mask");</div><div class='add'>+	debugfs_create_file(name, 0600, root, adev,</div><div class='add'>+			    &amp;amdgpu_debugfs_gfx_sched_mask_fops);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * debugfs for to enable/disable compute job submission to specific core.</div><div class='add'>+ */</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int amdgpu_debugfs_compute_sched_mask_set(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	mask = (1ULL &lt;&lt; adev-&gt;gfx.num_compute_rings) - 1;</div><div class='add'>+	if ((val &amp; mask) == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+		if (val &amp; (1 &lt;&lt; i))</div><div class='add'>+			ring-&gt;sched.ready = true;</div><div class='add'>+		else</div><div class='add'>+			ring-&gt;sched.ready = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* publish sched.ready flag update effective immediately across smp */</div><div class='add'>+	smp_rmb();</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+		if (ring-&gt;sched.ready)</div><div class='add'>+			mask |= 1ULL &lt;&lt; i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = mask;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops,</div><div class='add'>+			 amdgpu_debugfs_compute_sched_mask_get,</div><div class='add'>+			 amdgpu_debugfs_compute_sched_mask_set, "%llx\n");</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	char name[32];</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;gfx.num_compute_rings &gt; 1))</div><div class='add'>+		return;</div><div class='add'>+	sprintf(name, "amdgpu_compute_sched_mask");</div><div class='add'>+	debugfs_create_file(name, 0600, root, adev,</div><div class='add'>+			    &amp;amdgpu_debugfs_compute_sched_mask_fops);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h<br/>index 8fcf889ddce9..efd61a1ccc66 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> #include "amdgpu_ring_mux.h"</div><div class='add'>+#include "amdgpu_xcp.h"</div><div class='ctx'> </div><div class='ctx'> /* GFX current status */</div><div class='ctx'> #define AMDGPU_GFX_NORMAL_MODE			0x00000000L</div><div class='hunk'>@@ -56,6 +57,9 @@ enum amdgpu_gfx_pipe_priority {</div><div class='ctx'> #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0</div><div class='ctx'> #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15</div><div class='ctx'> </div><div class='add'>+/* 1 second timeout */</div><div class='add'>+#define GFX_PROFILE_IDLE_TIMEOUT	msecs_to_jiffies(1000)</div><div class='add'>+</div><div class='ctx'> enum amdgpu_gfx_partition {</div><div class='ctx'> 	AMDGPU_SPX_PARTITION_MODE = 0,</div><div class='ctx'> 	AMDGPU_DPX_PARTITION_MODE = 1,</div><div class='hunk'>@@ -138,6 +142,10 @@ struct kiq_pm4_funcs {</div><div class='ctx'> 	void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 				uint16_t pasid, uint32_t flush_type,</div><div class='ctx'> 				bool all_hub);</div><div class='add'>+	void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring,</div><div class='add'>+				   uint32_t queue_type, uint32_t me_id,</div><div class='add'>+				   uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+				   uint32_t xcc_id, uint32_t vmid);</div><div class='ctx'> 	/* Packet sizes */</div><div class='ctx'> 	int set_resources_size;</div><div class='ctx'> 	int map_queues_size;</div><div class='hunk'>@@ -162,10 +170,46 @@ struct amdgpu_kiq {</div><div class='ctx'> #define AMDGPU_GFX_MAX_SE 4</div><div class='ctx'> #define AMDGPU_GFX_MAX_SH_PER_SE 2</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_rb_config - Configure a single Render Backend (RB)</div><div class='add'>+ *</div><div class='add'>+ * Bad RBs are fused off and there is a harvest register the driver reads to</div><div class='add'>+ * determine which RB(s) are fused off so that the driver can configure the</div><div class='add'>+ * hardware state so that nothing gets sent to them. There are also user</div><div class='add'>+ * harvest registers that the driver can program to disable additional RBs,</div><div class='add'>+ * etc., for testing purposes.</div><div class='add'>+ */</div><div class='ctx'> struct amdgpu_rb_config {</div><div class='add'>+	/**</div><div class='add'>+	 * @rb_backend_disable:</div><div class='add'>+	 *</div><div class='add'>+	 * The value captured from register RB_BACKEND_DISABLE indicates if the</div><div class='add'>+	 * RB backend is disabled or not.</div><div class='add'>+	 */</div><div class='ctx'> 	uint32_t rb_backend_disable;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @user_rb_backend_disable:</div><div class='add'>+	 *</div><div class='add'>+	 * The value captured from register USER_RB_BACKEND_DISABLE indicates</div><div class='add'>+	 * if the User RB backend is disabled or not.</div><div class='add'>+	 */</div><div class='ctx'> 	uint32_t user_rb_backend_disable;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @raster_config:</div><div class='add'>+	 *</div><div class='add'>+	 * To set up all of the states, it is necessary to have two registers</div><div class='add'>+	 * to keep all of the states. This field holds the first register.</div><div class='add'>+	 */</div><div class='ctx'> 	uint32_t raster_config;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @raster_config_1:</div><div class='add'>+	 *</div><div class='add'>+	 * To set up all of the states, it is necessary to have two registers</div><div class='add'>+	 * to keep all of the states. This field holds the second register.</div><div class='add'>+	 */</div><div class='ctx'> 	uint32_t raster_config_1;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -213,6 +257,13 @@ struct amdgpu_gfx_config {</div><div class='ctx'> 	uint32_t macrotile_mode_array[16];</div><div class='ctx'> </div><div class='ctx'> 	struct gb_addr_config gb_addr_config_fields;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @rb_config:</div><div class='add'>+	 *</div><div class='add'>+	 * Matrix that keeps all the Render Backend (color and depth buffer</div><div class='add'>+	 * handling) configuration on the 3D engine.</div><div class='add'>+	 */</div><div class='ctx'> 	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];</div><div class='ctx'> </div><div class='ctx'> 	/* gfx configure feature */</div><div class='hunk'>@@ -240,6 +291,12 @@ struct amdgpu_gfx_config {</div><div class='ctx'> 	uint32_t gc_tcp_size_per_cu;</div><div class='ctx'> 	uint32_t gc_num_cu_per_sqc;</div><div class='ctx'> 	uint32_t gc_tcc_size;</div><div class='add'>+	uint32_t gc_tcp_cache_line_size;</div><div class='add'>+	uint32_t gc_instruction_cache_size_per_sqc;</div><div class='add'>+	uint32_t gc_instruction_cache_line_size;</div><div class='add'>+	uint32_t gc_scalar_data_cache_size_per_sqc;</div><div class='add'>+	uint32_t gc_scalar_data_cache_line_size;</div><div class='add'>+	uint32_t gc_tcc_cache_line_size;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_cu_info {</div><div class='hunk'>@@ -259,7 +316,6 @@ struct amdgpu_cu_info {</div><div class='ctx'> struct amdgpu_gfx_ras {</div><div class='ctx'> 	struct amdgpu_ras_block_object  ras_block;</div><div class='ctx'> 	void (*enable_watchdog_timer)(struct amdgpu_device *adev);</div><div class='del'>-	bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);</div><div class='ctx'> 	int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,</div><div class='ctx'> 				struct amdgpu_irq_src *source,</div><div class='ctx'> 				struct amdgpu_iv_entry *entry);</div><div class='hunk'>@@ -292,12 +348,14 @@ struct amdgpu_gfx_funcs {</div><div class='ctx'> 	void (*init_spm_golden)(struct amdgpu_device *adev);</div><div class='ctx'> 	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> 	int (*get_gfx_shadow_info)(struct amdgpu_device *adev,</div><div class='del'>-				   struct amdgpu_gfx_shadow_info *shadow_info);</div><div class='add'>+				   struct amdgpu_gfx_shadow_info *shadow_info,</div><div class='add'>+				   bool skip_check);</div><div class='ctx'> 	enum amdgpu_gfx_partition</div><div class='ctx'> 			(*query_partition_mode)(struct amdgpu_device *adev);</div><div class='ctx'> 	int (*switch_partition_mode)(struct amdgpu_device *adev,</div><div class='ctx'> 				     int num_xccs_per_xcp);</div><div class='ctx'> 	int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);</div><div class='add'>+	int (*get_xccs_per_xcp)(struct amdgpu_device *adev);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct sq_work {</div><div class='hunk'>@@ -339,6 +397,12 @@ struct amdgpu_me {</div><div class='ctx'> 	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_isolation_work {</div><div class='add'>+	struct amdgpu_device		*adev;</div><div class='add'>+	u32				xcp_id;</div><div class='add'>+	struct delayed_work		work;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_gfx {</div><div class='ctx'> 	struct mutex			gpu_clock_mutex;</div><div class='ctx'> 	struct amdgpu_gfx_config	config;</div><div class='hunk'>@@ -391,6 +455,7 @@ struct amdgpu_gfx {</div><div class='ctx'> 	struct amdgpu_irq_src		eop_irq;</div><div class='ctx'> 	struct amdgpu_irq_src		priv_reg_irq;</div><div class='ctx'> 	struct amdgpu_irq_src		priv_inst_irq;</div><div class='add'>+	struct amdgpu_irq_src		bad_op_irq;</div><div class='ctx'> 	struct amdgpu_irq_src		cp_ecc_error_irq;</div><div class='ctx'> 	struct amdgpu_irq_src		sq_irq;</div><div class='ctx'> 	struct amdgpu_irq_src		rlc_gc_fed_irq;</div><div class='hunk'>@@ -406,6 +471,8 @@ struct amdgpu_gfx {</div><div class='ctx'> 	/* reset mask */</div><div class='ctx'> 	uint32_t                        grbm_soft_reset;</div><div class='ctx'> 	uint32_t                        srbm_soft_reset;</div><div class='add'>+	uint32_t 			gfx_supported_reset;</div><div class='add'>+	uint32_t 			compute_supported_reset;</div><div class='ctx'> </div><div class='ctx'> 	/* gfx off */</div><div class='ctx'> 	bool                            gfx_off_state;      /* true: enabled, false: disabled */</div><div class='hunk'>@@ -434,6 +501,36 @@ struct amdgpu_gfx {</div><div class='ctx'> 	uint32_t			num_xcc_per_xcp;</div><div class='ctx'> 	struct mutex			partition_mutex;</div><div class='ctx'> 	bool				mcbp; /* mid command buffer preemption */</div><div class='add'>+</div><div class='add'>+	/* IP reg dump */</div><div class='add'>+	uint32_t			*ip_dump_core;</div><div class='add'>+	uint32_t			*ip_dump_compute_queues;</div><div class='add'>+	uint32_t			*ip_dump_gfx_queues;</div><div class='add'>+</div><div class='add'>+	struct mutex			reset_sem_mutex;</div><div class='add'>+</div><div class='add'>+	/* cleaner shader */</div><div class='add'>+	struct amdgpu_bo		*cleaner_shader_obj;</div><div class='add'>+	unsigned int                    cleaner_shader_size;</div><div class='add'>+	u64				cleaner_shader_gpu_addr;</div><div class='add'>+	void				*cleaner_shader_cpu_ptr;</div><div class='add'>+	const void			*cleaner_shader_ptr;</div><div class='add'>+	bool				enable_cleaner_shader;</div><div class='add'>+	struct amdgpu_isolation_work	enforce_isolation[MAX_XCP];</div><div class='add'>+	/* Mutex for synchronizing KFD scheduler operations */</div><div class='add'>+	struct mutex                    userq_sch_mutex;</div><div class='add'>+	u64				userq_sch_req_count[MAX_XCP];</div><div class='add'>+	bool				userq_sch_inactive[MAX_XCP];</div><div class='add'>+	unsigned long			enforce_isolation_jiffies[MAX_XCP];</div><div class='add'>+	unsigned long			enforce_isolation_time[MAX_XCP];</div><div class='add'>+</div><div class='add'>+	atomic_t			total_submission_cnt;</div><div class='add'>+	struct delayed_work		idle_work;</div><div class='add'>+	bool				workload_profile_active;</div><div class='add'>+	struct mutex                    workload_profile_mutex;</div><div class='add'>+</div><div class='add'>+	bool				disable_kq;</div><div class='add'>+	bool				disable_uq;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_gfx_ras_reg_entry {</div><div class='hunk'>@@ -453,7 +550,7 @@ struct amdgpu_gfx_ras_mem_id_entry {</div><div class='ctx'> #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)-&gt;gfx.funcs-&gt;select_se_sh((adev), (se), (sh), (instance), (xcc_id)))</div><div class='ctx'> #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)-&gt;gfx.funcs-&gt;select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))</div><div class='ctx'> #define amdgpu_gfx_init_spm_golden(adev) (adev)-&gt;gfx.funcs-&gt;init_spm_golden((adev))</div><div class='del'>-#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)-&gt;gfx.funcs-&gt;get_gfx_shadow_info((adev), (si)))</div><div class='add'>+#define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)-&gt;gfx.funcs-&gt;get_gfx_shadow_info((adev), (si), false))</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_gfx_create_bitmask - create a bitmask</div><div class='hunk'>@@ -500,13 +597,10 @@ bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,</div><div class='ctx'> 					       struct amdgpu_ring *ring);</div><div class='ctx'> bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,</div><div class='ctx'> 						struct amdgpu_ring *ring);</div><div class='del'>-int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,</div><div class='del'>-			       int pipe, int queue);</div><div class='del'>-void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,</div><div class='del'>-				int *me, int *pipe, int *queue);</div><div class='ctx'> bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,</div><div class='ctx'> 				    int pipe, int queue);</div><div class='ctx'> void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);</div><div class='add'>+void amdgpu_gfx_off_ctrl_immediate(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);</div><div class='ctx'> int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);</div><div class='ctx'> void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);</div><div class='hunk'>@@ -521,6 +615,7 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				  struct amdgpu_iv_entry *entry);</div><div class='ctx'> uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);</div><div class='ctx'> void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);</div><div class='add'>+int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);</div><div class='ctx'> </div><div class='hunk'>@@ -535,6 +630,25 @@ void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,</div><div class='ctx'> 		void *ras_error_status,</div><div class='ctx'> 		void (*func)(struct amdgpu_device *adev, void *ras_error_status,</div><div class='ctx'> 				int xcc_id));</div><div class='add'>+int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev,</div><div class='add'>+				      unsigned int cleaner_shader_size);</div><div class='add'>+void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev,</div><div class='add'>+				    unsigned int cleaner_shader_size,</div><div class='add'>+				    const void *cleaner_shader_ptr);</div><div class='add'>+void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work);</div><div class='add'>+void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring);</div><div class='add'>+void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring);</div><div class='add'>+</div><div class='add'>+void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work);</div><div class='add'>+void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring);</div><div class='add'>+void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring);</div><div class='add'>+u32 amdgpu_gfx_csb_preamble_start(u32 *buffer);</div><div class='add'>+u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count);</div><div class='add'>+void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count);</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> static inline const char *amdgpu_gfx_compute_mode_desc(int mode)</div><div class='ctx'> {</div><div class='hunk'>@@ -552,8 +666,6 @@ static inline const char *amdgpu_gfx_compute_mode_desc(int mode)</div><div class='ctx'> 	default:</div><div class='ctx'> 		return "UNKNOWN";</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return "UNKNOWN";</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c<br/>index be4629cdac04..869bceb0fe2c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c</a></div><div class='hunk'>@@ -38,6 +38,13 @@</div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='ctx'> </div><div class='add'>+static const u64 four_gb = 0x100000000ULL;</div><div class='add'>+</div><div class='add'>+bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return adev-&gt;gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0</div><div class='ctx'>  *</div><div class='hunk'>@@ -251,10 +258,20 @@ void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc</div><div class='ctx'> 	u64 hive_vram_end = mc-&gt;xgmi.node_segment_size * mc-&gt;xgmi.num_physical_nodes - 1;</div><div class='ctx'> 	mc-&gt;vram_start = mc-&gt;xgmi.node_segment_size * mc-&gt;xgmi.physical_node_id;</div><div class='ctx'> 	mc-&gt;vram_end = mc-&gt;vram_start + mc-&gt;xgmi.node_segment_size - 1;</div><div class='del'>-	mc-&gt;gart_start = hive_vram_end + 1;</div><div class='add'>+	/* node_segment_size may not 4GB aligned on SRIOV, align up is needed. */</div><div class='add'>+	mc-&gt;gart_start = ALIGN(hive_vram_end + 1, four_gb);</div><div class='ctx'> 	mc-&gt;gart_end = mc-&gt;gart_start + mc-&gt;gart_size - 1;</div><div class='del'>-	mc-&gt;fb_start = hive_vram_start;</div><div class='del'>-	mc-&gt;fb_end = hive_vram_end;</div><div class='add'>+	if (amdgpu_virt_xgmi_migrate_enabled(adev)) {</div><div class='add'>+		/* set mc-&gt;vram_start to 0 to switch the returned GPU address of</div><div class='add'>+		 * amdgpu_bo_create_reserved() from FB aperture to GART aperture.</div><div class='add'>+		 */</div><div class='add'>+		mc-&gt;vram_start = 0;</div><div class='add'>+		mc-&gt;vram_end = mc-&gt;vram_start + mc-&gt;mc_vram_size - 1;</div><div class='add'>+		mc-&gt;visible_vram_size = min(mc-&gt;visible_vram_size, mc-&gt;real_vram_size);</div><div class='add'>+	} else {</div><div class='add'>+		mc-&gt;fb_start = hive_vram_start;</div><div class='add'>+		mc-&gt;fb_end = hive_vram_end;</div><div class='add'>+	}</div><div class='ctx'> 	dev_info(adev-&gt;dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",</div><div class='ctx'> 			mc-&gt;mc_vram_size &gt;&gt; 20, mc-&gt;vram_start,</div><div class='ctx'> 			mc-&gt;vram_end, mc-&gt;real_vram_size &gt;&gt; 20);</div><div class='hunk'>@@ -269,14 +286,13 @@ void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc</div><div class='ctx'>  * @mc: memory controller structure holding memory information</div><div class='ctx'>  * @gart_placement: GART placement policy with respect to VRAM</div><div class='ctx'>  *</div><div class='del'>- * Function will place try to place GART before or after VRAM.</div><div class='add'>+ * Function will try to place GART before or after VRAM.</div><div class='ctx'>  * If GART size is bigger than space left then we ajust GART size.</div><div class='ctx'>  * Thus function will never fails.</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,</div><div class='ctx'> 			      enum amdgpu_gart_placement gart_placement)</div><div class='ctx'> {</div><div class='del'>-	const uint64_t four_gb = 0x100000000ULL;</div><div class='ctx'> 	u64 size_af, size_bf;</div><div class='ctx'> 	/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/</div><div class='ctx'> 	u64 max_mc_address = min(adev-&gt;gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);</div><div class='hunk'>@@ -573,6 +589,7 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)</div><div class='ctx'> 	unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = {0};</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	unsigned vmhub, inv_eng;</div><div class='add'>+	struct amdgpu_ring *shared_ring;</div><div class='ctx'> </div><div class='ctx'> 	/* init the vm inv eng for all vmhubs */</div><div class='ctx'> 	for_each_set_bit(i, adev-&gt;vmhubs_mask, AMDGPU_MAX_VMHUBS) {</div><div class='hunk'>@@ -580,6 +597,9 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)</div><div class='ctx'> 		/* reserve engine 5 for firmware */</div><div class='ctx'> 		if (adev-&gt;enable_mes)</div><div class='ctx'> 			vm_inv_engs[i] &amp;= ~(1 &lt;&lt; 5);</div><div class='add'>+		/* reserve engine 6 for uni mes */</div><div class='add'>+		if (adev-&gt;enable_uni_mes)</div><div class='add'>+			vm_inv_engs[i] &amp;= ~(1 &lt;&lt; 6);</div><div class='ctx'> 		/* reserve mmhub engine 3 for firmware */</div><div class='ctx'> 		if (adev-&gt;enable_umsch_mm)</div><div class='ctx'> 			vm_inv_engs[i] &amp;= ~(1 &lt;&lt; 3);</div><div class='hunk'>@@ -589,8 +609,14 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)</div><div class='ctx'> 		ring = adev-&gt;rings[i];</div><div class='ctx'> 		vmhub = ring-&gt;vm_hub;</div><div class='ctx'> </div><div class='del'>-		if (ring == &amp;adev-&gt;mes.ring ||</div><div class='del'>-		    ring == &amp;adev-&gt;umsch_mm.ring)</div><div class='add'>+		if (ring == &amp;adev-&gt;mes.ring[0] ||</div><div class='add'>+		    ring == &amp;adev-&gt;mes.ring[1] ||</div><div class='add'>+		    ring == &amp;adev-&gt;umsch_mm.ring ||</div><div class='add'>+		    ring == &amp;adev-&gt;cper.ring_buf)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Skip if the ring is a shared ring */</div><div class='add'>+		if (amdgpu_sdma_is_shared_inv_eng(adev, ring))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		inv_eng = ffs(vm_inv_engs[vmhub]);</div><div class='hunk'>@@ -605,6 +631,21 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		dev_info(adev-&gt;dev, "ring %s uses VM inv eng %u on hub %u\n",</div><div class='ctx'> 			 ring-&gt;name, ring-&gt;vm_inv_eng, ring-&gt;vm_hub);</div><div class='add'>+		/* SDMA has a special packet which allows it to use the same</div><div class='add'>+		 * invalidation engine for all the rings in one instance.</div><div class='add'>+		 * Therefore, we do not allocate a separate VM invalidation engine</div><div class='add'>+		 * for SDMA page rings. Instead, they share the VM invalidation</div><div class='add'>+		 * engine with the SDMA gfx ring. This change ensures efficient</div><div class='add'>+		 * resource management and avoids the issue of insufficient VM</div><div class='add'>+		 * invalidation engines.</div><div class='add'>+		 */</div><div class='add'>+		shared_ring = amdgpu_sdma_get_shared_ring(adev, ring);</div><div class='add'>+		if (shared_ring) {</div><div class='add'>+			shared_ring-&gt;vm_inv_eng = ring-&gt;vm_inv_eng;</div><div class='add'>+			dev_info(adev-&gt;dev, "ring %s shares VM invalidation engine %u with ring %s on hub %u\n",</div><div class='add'>+					ring-&gt;name, ring-&gt;vm_inv_eng, shared_ring-&gt;name, ring-&gt;vm_hub);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -620,10 +661,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!hub-&gt;sdma_invalidation_workaround || vmid ||</div><div class='del'>-	    !adev-&gt;mman.buffer_funcs_enabled ||</div><div class='del'>-	    !adev-&gt;ib_pool_ready || amdgpu_in_reset(adev) ||</div><div class='add'>+	    !adev-&gt;mman.buffer_funcs_enabled || !adev-&gt;ib_pool_ready ||</div><div class='ctx'> 	    !ring-&gt;sched.ready) {</div><div class='del'>-</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * A GPU reset should flush all TLBs anyway, so no need to do</div><div class='ctx'> 		 * this while one is ongoing.</div><div class='hunk'>@@ -654,7 +693,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, &amp;adev-&gt;mman.high_pr,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     16 * 4, AMDGPU_IB_POOL_IMMEDIATE,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error_alloc;</div><div class='ctx'> </div><div class='hunk'>@@ -679,17 +718,20 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid,</div><div class='ctx'> 				   uint32_t flush_type, bool all_hub,</div><div class='ctx'> 				   uint32_t inst)</div><div class='ctx'> {</div><div class='del'>-	u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT :</div><div class='del'>-		adev-&gt;usec_timeout;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;gfx.kiq[inst].ring;</div><div class='ctx'> 	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[inst];</div><div class='ctx'> 	unsigned int ndw;</div><div class='del'>-	signed long r;</div><div class='add'>+	int r, cnt = 0;</div><div class='ctx'> 	uint32_t seq;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;gmc.flush_pasid_uses_kiq || !ring-&gt;sched.ready ||</div><div class='del'>-	    !down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+	/*</div><div class='add'>+	 * A GPU reset should flush all TLBs anyway, so no need to do</div><div class='add'>+	 * this while one is ongoing.</div><div class='add'>+	 */</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='add'>+	if (!adev-&gt;gmc.flush_pasid_uses_kiq || !ring-&gt;sched.ready) {</div><div class='ctx'> 		if (adev-&gt;gmc.flush_tlb_needs_extra_type_2)</div><div class='ctx'> 			adev-&gt;gmc.gmc_funcs-&gt;flush_gpu_tlb_pasid(adev, pasid,</div><div class='ctx'> 								 2, all_hub,</div><div class='hunk'>@@ -703,43 +745,55 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid,</div><div class='ctx'> 		adev-&gt;gmc.gmc_funcs-&gt;flush_gpu_tlb_pasid(adev, pasid,</div><div class='ctx'> 							 flush_type, all_hub,</div><div class='ctx'> 							 inst);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='add'>+		r = 0;</div><div class='add'>+	} else {</div><div class='add'>+		/* 2 dwords flush + 8 dwords fence */</div><div class='add'>+		ndw = kiq-&gt;pmf-&gt;invalidate_tlbs_size + 8;</div><div class='ctx'> </div><div class='del'>-	/* 2 dwords flush + 8 dwords fence */</div><div class='del'>-	ndw = kiq-&gt;pmf-&gt;invalidate_tlbs_size + 8;</div><div class='add'>+		if (adev-&gt;gmc.flush_tlb_needs_extra_type_2)</div><div class='add'>+			ndw += kiq-&gt;pmf-&gt;invalidate_tlbs_size;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.flush_tlb_needs_extra_type_2)</div><div class='del'>-		ndw += kiq-&gt;pmf-&gt;invalidate_tlbs_size;</div><div class='add'>+		if (adev-&gt;gmc.flush_tlb_needs_extra_type_0)</div><div class='add'>+			ndw += kiq-&gt;pmf-&gt;invalidate_tlbs_size;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.flush_tlb_needs_extra_type_0)</div><div class='del'>-		ndw += kiq-&gt;pmf-&gt;invalidate_tlbs_size;</div><div class='add'>+		spin_lock(&amp;adev-&gt;gfx.kiq[inst].ring_lock);</div><div class='add'>+		r = amdgpu_ring_alloc(ring, ndw);</div><div class='add'>+		if (r) {</div><div class='add'>+			spin_unlock(&amp;adev-&gt;gfx.kiq[inst].ring_lock);</div><div class='add'>+			goto error_unlock_reset;</div><div class='add'>+		}</div><div class='add'>+		if (adev-&gt;gmc.flush_tlb_needs_extra_type_2)</div><div class='add'>+			kiq-&gt;pmf-&gt;kiq_invalidate_tlbs(ring, pasid, 2, all_hub);</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;adev-&gt;gfx.kiq[inst].ring_lock);</div><div class='del'>-	amdgpu_ring_alloc(ring, ndw);</div><div class='del'>-	if (adev-&gt;gmc.flush_tlb_needs_extra_type_2)</div><div class='del'>-		kiq-&gt;pmf-&gt;kiq_invalidate_tlbs(ring, pasid, 2, all_hub);</div><div class='add'>+		if (flush_type == 2 &amp;&amp; adev-&gt;gmc.flush_tlb_needs_extra_type_0)</div><div class='add'>+			kiq-&gt;pmf-&gt;kiq_invalidate_tlbs(ring, pasid, 0, all_hub);</div><div class='ctx'> </div><div class='del'>-	if (flush_type == 2 &amp;&amp; adev-&gt;gmc.flush_tlb_needs_extra_type_0)</div><div class='del'>-		kiq-&gt;pmf-&gt;kiq_invalidate_tlbs(ring, pasid, 0, all_hub);</div><div class='add'>+		kiq-&gt;pmf-&gt;kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub);</div><div class='add'>+		r = amdgpu_fence_emit_polling(ring, &amp;seq, MAX_KIQ_REG_WAIT);</div><div class='add'>+		if (r) {</div><div class='add'>+			amdgpu_ring_undo(ring);</div><div class='add'>+			spin_unlock(&amp;adev-&gt;gfx.kiq[inst].ring_lock);</div><div class='add'>+			goto error_unlock_reset;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	kiq-&gt;pmf-&gt;kiq_invalidate_tlbs(ring, pasid, flush_type, all_hub);</div><div class='del'>-	r = amdgpu_fence_emit_polling(ring, &amp;seq, MAX_KIQ_REG_WAIT);</div><div class='del'>-	if (r) {</div><div class='del'>-		amdgpu_ring_undo(ring);</div><div class='add'>+		amdgpu_ring_commit(ring);</div><div class='ctx'> 		spin_unlock(&amp;adev-&gt;gfx.kiq[inst].ring_lock);</div><div class='del'>-		goto error_unlock_reset;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_commit(ring);</div><div class='del'>-	spin_unlock(&amp;adev-&gt;gfx.kiq[inst].ring_lock);</div><div class='del'>-	r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);</div><div class='del'>-	if (r &lt; 1) {</div><div class='del'>-		dev_err(adev-&gt;dev, "wait for kiq fence error: %ld.\n", r);</div><div class='del'>-		r = -ETIME;</div><div class='del'>-		goto error_unlock_reset;</div><div class='add'>+		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='add'>+</div><div class='add'>+		might_sleep();</div><div class='add'>+		while (r &lt; 1 &amp;&amp; cnt++ &lt; MAX_KIQ_REG_TRY &amp;&amp;</div><div class='add'>+		       !amdgpu_reset_pending(adev-&gt;reset_domain)) {</div><div class='add'>+			msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);</div><div class='add'>+			r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (cnt &gt; MAX_KIQ_REG_TRY) {</div><div class='add'>+			dev_err(adev-&gt;dev, "timeout waiting for kiq fence\n");</div><div class='add'>+			r = -ETIME;</div><div class='add'>+		} else</div><div class='add'>+			r = 0;</div><div class='ctx'> 	}</div><div class='del'>-	r = 0;</div><div class='ctx'> </div><div class='ctx'> error_unlock_reset:</div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='hunk'>@@ -757,7 +811,7 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	uint32_t seq;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mes.ring.sched.ready) {</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready) {</div><div class='ctx'> 		amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,</div><div class='ctx'> 					      ref, mask);</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -781,7 +835,8 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,</div><div class='ctx'> 		goto failed_kiq;</div><div class='ctx'> </div><div class='ctx'> 	might_sleep();</div><div class='del'>-	while (r &lt; 1 &amp;&amp; cnt++ &lt; MAX_KIQ_REG_TRY) {</div><div class='add'>+	while (r &lt; 1 &amp;&amp; cnt++ &lt; MAX_KIQ_REG_TRY &amp;&amp;</div><div class='add'>+	       !amdgpu_reset_pending(adev-&gt;reset_domain)) {</div><div class='ctx'> </div><div class='ctx'> 		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);</div><div class='ctx'> 		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);</div><div class='hunk'>@@ -844,6 +899,8 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		/* Don't enable it by default yet.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (amdgpu_tmz &lt; 1) {</div><div class='hunk'>@@ -876,11 +933,12 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)</div><div class='ctx'> 	struct amdgpu_gmc *gmc = &amp;adev-&gt;gmc;</div><div class='ctx'> 	uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);</div><div class='ctx'> 	bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||</div><div class='del'>-				gc_ver == IP_VERSION(9, 3, 0) ||</div><div class='ctx'> 				gc_ver == IP_VERSION(9, 4, 0) ||</div><div class='ctx'> 				gc_ver == IP_VERSION(9, 4, 1) ||</div><div class='ctx'> 				gc_ver == IP_VERSION(9, 4, 2) ||</div><div class='ctx'> 				gc_ver == IP_VERSION(9, 4, 3) ||</div><div class='add'>+				gc_ver == IP_VERSION(9, 4, 4) ||</div><div class='add'>+				gc_ver == IP_VERSION(9, 5, 0) ||</div><div class='ctx'> 				gc_ver &gt;= IP_VERSION(10, 3, 0));</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_xnack_support(adev))</div><div class='hunk'>@@ -1002,9 +1060,7 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	u64 vram_size = adev-&gt;gmc.xgmi.node_segment_size * adev-&gt;gmc.xgmi.num_physical_nodes;</div><div class='ctx'> 	u64 pde0_page_size = (1ULL&lt;&lt;adev-&gt;gmc.vmid0_page_table_block_size)&lt;&lt;21;</div><div class='del'>-	u64 vram_addr = adev-&gt;vm_manager.vram_base_offset -</div><div class='del'>-		adev-&gt;gmc.xgmi.physical_node_id * adev-&gt;gmc.xgmi.node_segment_size;</div><div class='del'>-	u64 vram_end = vram_addr + vram_size;</div><div class='add'>+	u64 vram_addr, vram_end;</div><div class='ctx'> 	u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev-&gt;gart.bo);</div><div class='ctx'> 	int idx;</div><div class='ctx'> </div><div class='hunk'>@@ -1015,7 +1071,12 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)</div><div class='ctx'> 	flags |= AMDGPU_PTE_WRITEABLE;</div><div class='ctx'> 	flags |= AMDGPU_PTE_SNOOPED;</div><div class='ctx'> 	flags |= AMDGPU_PTE_FRAG((adev-&gt;gmc.vmid0_page_table_block_size + 9*1));</div><div class='del'>-	flags |= AMDGPU_PDE_PTE;</div><div class='add'>+	flags |= AMDGPU_PDE_PTE_FLAG(adev);</div><div class='add'>+</div><div class='add'>+	vram_addr = adev-&gt;vm_manager.vram_base_offset;</div><div class='add'>+	if (!amdgpu_virt_xgmi_migrate_enabled(adev))</div><div class='add'>+		vram_addr -= adev-&gt;gmc.xgmi.physical_node_id * adev-&gt;gmc.xgmi.node_segment_size;</div><div class='add'>+	vram_end = vram_addr + vram_size;</div><div class='ctx'> </div><div class='ctx'> 	/* The first n PDE0 entries are used as PTE,</div><div class='ctx'> 	 * pointing to vram</div><div class='hunk'>@@ -1028,7 +1089,7 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)</div><div class='ctx'> 	 * pointing to a 4K system page</div><div class='ctx'> 	 */</div><div class='ctx'> 	flags = AMDGPU_PTE_VALID;</div><div class='del'>-	flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;</div><div class='add'>+	flags |= AMDGPU_PTE_SNOOPED | AMDGPU_PDE_BFS_FLAG(adev, 0);</div><div class='ctx'> 	/* Requires gart_ptb_gpu_pa to be 4K aligned */</div><div class='ctx'> 	amdgpu_gmc_set_pte_pde(adev, adev-&gt;gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);</div><div class='ctx'> 	drm_dev_exit(idx);</div><div class='hunk'>@@ -1058,18 +1119,6 @@ uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)</div><div class='ctx'> 	return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address</div><div class='del'>- * from CPU's view</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @bo: amdgpu buffer object</div><div class='del'>- */</div><div class='del'>-uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)</div><div class='del'>-{</div><div class='del'>-	return amdgpu_bo_gpu_offset(bo) - adev-&gt;gmc.vram_start + adev-&gt;gmc.aper_base;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo *vram_bo = NULL;</div><div class='hunk'>@@ -1123,6 +1172,79 @@ release_buffer:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const char *nps_desc[] = {</div><div class='add'>+	[AMDGPU_NPS1_PARTITION_MODE] = "NPS1",</div><div class='add'>+	[AMDGPU_NPS2_PARTITION_MODE] = "NPS2",</div><div class='add'>+	[AMDGPU_NPS3_PARTITION_MODE] = "NPS3",</div><div class='add'>+	[AMDGPU_NPS4_PARTITION_MODE] = "NPS4",</div><div class='add'>+	[AMDGPU_NPS6_PARTITION_MODE] = "NPS6",</div><div class='add'>+	[AMDGPU_NPS8_PARTITION_MODE] = "NPS8",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t available_memory_partition_show(struct device *dev,</div><div class='add'>+					       struct device_attribute *addr,</div><div class='add'>+					       char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	int size = 0, mode;</div><div class='add'>+	char *sep = "";</div><div class='add'>+</div><div class='add'>+	for_each_inst(mode, adev-&gt;gmc.supported_nps_modes) {</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s%s", sep, nps_desc[mode]);</div><div class='add'>+		sep = ", ";</div><div class='add'>+	}</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t current_memory_partition_store(struct device *dev,</div><div class='add'>+					      struct device_attribute *attr,</div><div class='add'>+					      const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	enum amdgpu_memory_partition mode;</div><div class='add'>+	struct amdgpu_hive_info *hive;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	mode = UNKNOWN_MEMORY_PARTITION_MODE;</div><div class='add'>+	for_each_inst(i, adev-&gt;gmc.supported_nps_modes) {</div><div class='add'>+		if (!strncasecmp(nps_desc[i], buf, strlen(nps_desc[i]))) {</div><div class='add'>+			mode = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mode == UNKNOWN_MEMORY_PARTITION_MODE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (mode == adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev)) {</div><div class='add'>+		dev_info(</div><div class='add'>+			adev-&gt;dev,</div><div class='add'>+			"requested NPS mode is same as current NPS mode, skipping\n");</div><div class='add'>+		return count;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If device is part of hive, all devices in the hive should request the</div><div class='add'>+	 * same mode. Hence store the requested mode in hive.</div><div class='add'>+	 */</div><div class='add'>+	hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (hive) {</div><div class='add'>+		atomic_set(&amp;hive-&gt;requested_nps_mode, mode);</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gmc.requested_nps_mode = mode;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_info(</div><div class='add'>+		adev-&gt;dev,</div><div class='add'>+		"NPS mode change requested, please remove and reload the driver\n");</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t current_memory_partition_show(</div><div class='ctx'> 	struct device *dev, struct device_attribute *addr, char *buf)</div><div class='ctx'> {</div><div class='hunk'>@@ -1130,39 +1252,431 @@ static ssize_t current_memory_partition_show(</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='ctx'> 	enum amdgpu_memory_partition mode;</div><div class='ctx'> </div><div class='add'>+	/* Only minimal precaution taken to reject requests while in reset */</div><div class='add'>+	if (amdgpu_in_reset(adev))</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='ctx'> 	mode = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='del'>-	switch (mode) {</div><div class='del'>-	case AMDGPU_NPS1_PARTITION_MODE:</div><div class='del'>-		return sysfs_emit(buf, "NPS1\n");</div><div class='del'>-	case AMDGPU_NPS2_PARTITION_MODE:</div><div class='del'>-		return sysfs_emit(buf, "NPS2\n");</div><div class='del'>-	case AMDGPU_NPS3_PARTITION_MODE:</div><div class='del'>-		return sysfs_emit(buf, "NPS3\n");</div><div class='del'>-	case AMDGPU_NPS4_PARTITION_MODE:</div><div class='del'>-		return sysfs_emit(buf, "NPS4\n");</div><div class='del'>-	case AMDGPU_NPS6_PARTITION_MODE:</div><div class='del'>-		return sysfs_emit(buf, "NPS6\n");</div><div class='del'>-	case AMDGPU_NPS8_PARTITION_MODE:</div><div class='del'>-		return sysfs_emit(buf, "NPS8\n");</div><div class='del'>-	default:</div><div class='add'>+	if ((mode &gt;= ARRAY_SIZE(nps_desc)) ||</div><div class='add'>+	    (BIT(mode) &amp; AMDGPU_ALL_NPS_MASK) != BIT(mode))</div><div class='ctx'> 		return sysfs_emit(buf, "UNKNOWN\n");</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	return sysfs_emit(buf, "UNKNOWN\n");</div><div class='add'>+	return sysfs_emit(buf, "%s\n", nps_desc[mode]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static DEVICE_ATTR_RO(current_memory_partition);</div><div class='add'>+static DEVICE_ATTR_RW(current_memory_partition);</div><div class='add'>+static DEVICE_ATTR_RO(available_memory_partition);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	bool nps_switch_support;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='ctx'> 	if (!adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	nps_switch_support = (hweight32(adev-&gt;gmc.supported_nps_modes &amp;</div><div class='add'>+					AMDGPU_ALL_NPS_MASK) &gt; 1);</div><div class='add'>+	if (!nps_switch_support)</div><div class='add'>+		dev_attr_current_memory_partition.attr.mode &amp;=</div><div class='add'>+			~(S_IWUSR | S_IWGRP | S_IWOTH);</div><div class='add'>+	else</div><div class='add'>+		r = device_create_file(adev-&gt;dev,</div><div class='add'>+				       &amp;dev_attr_available_memory_partition);</div><div class='add'>+</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return device_create_file(adev-&gt;dev,</div><div class='ctx'> 				  &amp;dev_attr_current_memory_partition);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	if (!adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_current_memory_partition);</div><div class='add'>+	device_remove_file(adev-&gt;dev, &amp;dev_attr_available_memory_partition);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_mem_partition_info *mem_ranges,</div><div class='add'>+				 uint8_t *exp_ranges)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_gmc_memrange *ranges;</div><div class='add'>+	int range_cnt, ret, i, j;</div><div class='add'>+	uint32_t nps_type;</div><div class='add'>+	bool refresh;</div><div class='add'>+</div><div class='add'>+	if (!mem_ranges || !exp_ranges)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	refresh = (adev-&gt;init_lvl-&gt;level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &amp;&amp;</div><div class='add'>+		  (adev-&gt;gmc.reset_flags &amp; AMDGPU_GMC_INIT_RESET_NPS);</div><div class='add'>+	ret = amdgpu_discovery_get_nps_info(adev, &amp;nps_type, &amp;ranges,</div><div class='add'>+					    &amp;range_cnt, refresh);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* TODO: For now, expect ranges and partition count to be the same.</div><div class='add'>+	 * Adjust if there are holes expected in any NPS domain.</div><div class='add'>+	 */</div><div class='add'>+	if (*exp_ranges &amp;&amp; (range_cnt != *exp_ranges)) {</div><div class='add'>+		dev_warn(</div><div class='add'>+			adev-&gt;dev,</div><div class='add'>+			"NPS config mismatch - expected ranges: %d discovery - nps mode: %d, nps ranges: %d",</div><div class='add'>+			*exp_ranges, nps_type, range_cnt);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; range_cnt; ++i) {</div><div class='add'>+		if (ranges[i].base_address &gt;= ranges[i].limit_address) {</div><div class='add'>+			dev_warn(</div><div class='add'>+				adev-&gt;dev,</div><div class='add'>+				"Invalid NPS range - nps mode: %d, range[%d]: base: %llx limit: %llx",</div><div class='add'>+				nps_type, i, ranges[i].base_address,</div><div class='add'>+				ranges[i].limit_address);</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Check for overlaps, not expecting any now */</div><div class='add'>+		for (j = i - 1; j &gt;= 0; j--) {</div><div class='add'>+			if (max(ranges[j].base_address,</div><div class='add'>+				ranges[i].base_address) &lt;=</div><div class='add'>+			    min(ranges[j].limit_address,</div><div class='add'>+				ranges[i].limit_address)) {</div><div class='add'>+				dev_warn(</div><div class='add'>+					adev-&gt;dev,</div><div class='add'>+					"overlapping ranges detected [ %llx - %llx ] | [%llx - %llx]",</div><div class='add'>+					ranges[j].base_address,</div><div class='add'>+					ranges[j].limit_address,</div><div class='add'>+					ranges[i].base_address,</div><div class='add'>+					ranges[i].limit_address);</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+				goto err;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mem_ranges[i].range.fpfn =</div><div class='add'>+			(ranges[i].base_address -</div><div class='add'>+			 adev-&gt;vm_manager.vram_base_offset) &gt;&gt;</div><div class='add'>+			AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+		mem_ranges[i].range.lpfn =</div><div class='add'>+			(ranges[i].limit_address -</div><div class='add'>+			 adev-&gt;vm_manager.vram_base_offset) &gt;&gt;</div><div class='add'>+			AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+		mem_ranges[i].size =</div><div class='add'>+			ranges[i].limit_address - ranges[i].base_address + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!*exp_ranges)</div><div class='add'>+		*exp_ranges = range_cnt;</div><div class='add'>+err:</div><div class='add'>+	kfree(ranges);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev,</div><div class='add'>+					int nps_mode)</div><div class='add'>+{</div><div class='add'>+	/* Not supported on VF devices and APUs */</div><div class='add'>+	if (amdgpu_sriov_vf(adev) || (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;psp.funcs) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"PSP interface not available for nps mode change request");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return psp_memory_partition(&amp;adev-&gt;psp, nps_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool amdgpu_gmc_need_nps_switch_req(struct amdgpu_device *adev,</div><div class='add'>+						  int req_nps_mode,</div><div class='add'>+						  int cur_nps_mode)</div><div class='add'>+{</div><div class='add'>+	return (((BIT(req_nps_mode) &amp; adev-&gt;gmc.supported_nps_modes) ==</div><div class='add'>+			BIT(req_nps_mode)) &amp;&amp;</div><div class='add'>+		req_nps_mode != cur_nps_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int req_nps_mode, cur_nps_mode, r;</div><div class='add'>+	struct amdgpu_hive_info *hive;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev) || !adev-&gt;gmc.supported_nps_modes ||</div><div class='add'>+	    !adev-&gt;gmc.gmc_funcs-&gt;request_mem_partition_mode)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cur_nps_mode = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='add'>+	hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (hive) {</div><div class='add'>+		req_nps_mode = atomic_read(&amp;hive-&gt;requested_nps_mode);</div><div class='add'>+		if (!amdgpu_gmc_need_nps_switch_req(adev, req_nps_mode,</div><div class='add'>+						    cur_nps_mode)) {</div><div class='add'>+			amdgpu_put_xgmi_hive(hive);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+		r = amdgpu_xgmi_request_nps_change(adev, hive, req_nps_mode);</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	req_nps_mode = adev-&gt;gmc.requested_nps_mode;</div><div class='add'>+	if (!amdgpu_gmc_need_nps_switch_req(adev, req_nps_mode, cur_nps_mode))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* even if this fails, we should let driver unload w/o blocking */</div><div class='add'>+	r = adev-&gt;gmc.gmc_funcs-&gt;request_mem_partition_mode(adev, req_nps_mode);</div><div class='add'>+out:</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "NPS mode change request failed\n");</div><div class='add'>+	else</div><div class='add'>+		dev_info(</div><div class='add'>+			adev-&gt;dev,</div><div class='add'>+			"NPS mode change request done, reload driver to complete the change\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;gmc.gmc_funcs-&gt;need_reset_on_init)</div><div class='add'>+		return adev-&gt;gmc.gmc_funcs-&gt;need_reset_on_init(adev);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum amdgpu_memory_partition</div><div class='add'>+amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (adev-&gt;gmc.num_mem_partitions) {</div><div class='add'>+	case 0:</div><div class='add'>+		return UNKNOWN_MEMORY_PARTITION_MODE;</div><div class='add'>+	case 1:</div><div class='add'>+		return AMDGPU_NPS1_PARTITION_MODE;</div><div class='add'>+	case 2:</div><div class='add'>+		return AMDGPU_NPS2_PARTITION_MODE;</div><div class='add'>+	case 4:</div><div class='add'>+		return AMDGPU_NPS4_PARTITION_MODE;</div><div class='add'>+	case 8:</div><div class='add'>+		return AMDGPU_NPS8_PARTITION_MODE;</div><div class='add'>+	default:</div><div class='add'>+		return AMDGPU_NPS1_PARTITION_MODE;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum amdgpu_memory_partition</div><div class='add'>+amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)</div><div class='add'>+{</div><div class='add'>+	enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;nbio.funcs &amp;&amp;</div><div class='add'>+	    adev-&gt;nbio.funcs-&gt;get_memory_partition_mode)</div><div class='add'>+		mode = adev-&gt;nbio.funcs-&gt;get_memory_partition_mode(adev,</div><div class='add'>+								   supp_modes);</div><div class='add'>+	else</div><div class='add'>+		dev_warn(adev-&gt;dev, "memory partition mode query is not supported\n");</div><div class='add'>+</div><div class='add'>+	return mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum amdgpu_memory_partition</div><div class='add'>+amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return amdgpu_gmc_get_vf_memory_partition(adev);</div><div class='add'>+	else</div><div class='add'>+		return amdgpu_gmc_get_memory_partition(adev, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_gmc_validate_partition_info(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	enum amdgpu_memory_partition mode;</div><div class='add'>+	u32 supp_modes;</div><div class='add'>+	bool valid;</div><div class='add'>+</div><div class='add'>+	mode = amdgpu_gmc_get_memory_partition(adev, &amp;supp_modes);</div><div class='add'>+</div><div class='add'>+	/* Mode detected by hardware not present in supported modes */</div><div class='add'>+	if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &amp;&amp;</div><div class='add'>+	    !(BIT(mode - 1) &amp; supp_modes))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case UNKNOWN_MEMORY_PARTITION_MODE:</div><div class='add'>+	case AMDGPU_NPS1_PARTITION_MODE:</div><div class='add'>+		valid = (adev-&gt;gmc.num_mem_partitions == 1);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS2_PARTITION_MODE:</div><div class='add'>+		valid = (adev-&gt;gmc.num_mem_partitions == 2);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS4_PARTITION_MODE:</div><div class='add'>+		valid = (adev-&gt;gmc.num_mem_partitions == 3 ||</div><div class='add'>+			 adev-&gt;gmc.num_mem_partitions == 4);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS8_PARTITION_MODE:</div><div class='add'>+		valid = (adev-&gt;gmc.num_mem_partitions == 8);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		valid = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return valid;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_gmc_is_node_present(int *node_ids, int num_ids, int nid)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Check if node with id 'nid' is present in 'node_ids' array */</div><div class='add'>+	for (i = 0; i &lt; num_ids; ++i)</div><div class='add'>+		if (node_ids[i] == nid)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+amdgpu_gmc_init_acpi_mem_ranges(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_mem_partition_info *mem_ranges)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_numa_info numa_info;</div><div class='add'>+	int node_ids[AMDGPU_MAX_MEM_RANGES];</div><div class='add'>+	int num_ranges = 0, ret;</div><div class='add'>+	int num_xcc, xcc_id;</div><div class='add'>+	uint32_t xcc_mask;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+	xcc_mask = (1U &lt;&lt; num_xcc) - 1;</div><div class='add'>+</div><div class='add'>+	for_each_inst(xcc_id, xcc_mask)	{</div><div class='add'>+		ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &amp;numa_info);</div><div class='add'>+		if (ret)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (numa_info.nid == NUMA_NO_NODE) {</div><div class='add'>+			mem_ranges[0].size = numa_info.size;</div><div class='add'>+			mem_ranges[0].numa.node = numa_info.nid;</div><div class='add'>+			num_ranges = 1;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_gmc_is_node_present(node_ids, num_ranges,</div><div class='add'>+					     numa_info.nid))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		node_ids[num_ranges] = numa_info.nid;</div><div class='add'>+		mem_ranges[num_ranges].numa.node = numa_info.nid;</div><div class='add'>+		mem_ranges[num_ranges].size = numa_info.size;</div><div class='add'>+		++num_ranges;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;gmc.num_mem_partitions = num_ranges;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev,</div><div class='add'>+				   struct amdgpu_mem_partition_info *mem_ranges)</div><div class='add'>+{</div><div class='add'>+	enum amdgpu_memory_partition mode;</div><div class='add'>+	u32 start_addr = 0, size;</div><div class='add'>+	int i, r, l;</div><div class='add'>+</div><div class='add'>+	mode = amdgpu_gmc_query_memory_partition(adev);</div><div class='add'>+</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case UNKNOWN_MEMORY_PARTITION_MODE:</div><div class='add'>+		adev-&gt;gmc.num_mem_partitions = 0;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS1_PARTITION_MODE:</div><div class='add'>+		adev-&gt;gmc.num_mem_partitions = 1;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS2_PARTITION_MODE:</div><div class='add'>+		adev-&gt;gmc.num_mem_partitions = 2;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS4_PARTITION_MODE:</div><div class='add'>+		if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+			adev-&gt;gmc.num_mem_partitions = 3;</div><div class='add'>+		else</div><div class='add'>+			adev-&gt;gmc.num_mem_partitions = 4;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_NPS8_PARTITION_MODE:</div><div class='add'>+		adev-&gt;gmc.num_mem_partitions = 8;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gmc.num_mem_partitions = 1;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Use NPS range info, if populated */</div><div class='add'>+	r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges,</div><div class='add'>+					 &amp;adev-&gt;gmc.num_mem_partitions);</div><div class='add'>+	if (!r) {</div><div class='add'>+		l = 0;</div><div class='add'>+		for (i = 1; i &lt; adev-&gt;gmc.num_mem_partitions; ++i) {</div><div class='add'>+			if (mem_ranges[i].range.lpfn &gt;</div><div class='add'>+			    mem_ranges[i - 1].range.lpfn)</div><div class='add'>+				l = i;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		if (!adev-&gt;gmc.num_mem_partitions) {</div><div class='add'>+			dev_warn(adev-&gt;dev,</div><div class='add'>+				 "Not able to detect NPS mode, fall back to NPS1\n");</div><div class='add'>+			adev-&gt;gmc.num_mem_partitions = 1;</div><div class='add'>+		}</div><div class='add'>+		/* Fallback to sw based calculation */</div><div class='add'>+		size = (adev-&gt;gmc.real_vram_size + SZ_16M) &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+		size /= adev-&gt;gmc.num_mem_partitions;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gmc.num_mem_partitions; ++i) {</div><div class='add'>+			mem_ranges[i].range.fpfn = start_addr;</div><div class='add'>+			mem_ranges[i].size =</div><div class='add'>+				((u64)size &lt;&lt; AMDGPU_GPU_PAGE_SHIFT);</div><div class='add'>+			mem_ranges[i].range.lpfn = start_addr + size - 1;</div><div class='add'>+			start_addr += size;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		l = adev-&gt;gmc.num_mem_partitions - 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Adjust the last one */</div><div class='add'>+	mem_ranges[l].range.lpfn =</div><div class='add'>+		(adev-&gt;gmc.real_vram_size &gt;&gt; AMDGPU_GPU_PAGE_SHIFT) - 1;</div><div class='add'>+	mem_ranges[l].size =</div><div class='add'>+		adev-&gt;gmc.real_vram_size -</div><div class='add'>+		((u64)mem_ranges[l].range.fpfn &lt;&lt; AMDGPU_GPU_PAGE_SHIFT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	bool valid;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gmc.mem_partitions = kcalloc(AMDGPU_MAX_MEM_RANGES,</div><div class='add'>+					   sizeof(struct amdgpu_mem_partition_info),</div><div class='add'>+					   GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;gmc.mem_partitions)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.is_app_apu)</div><div class='add'>+		amdgpu_gmc_init_acpi_mem_ranges(adev, adev-&gt;gmc.mem_partitions);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_gmc_init_sw_mem_ranges(adev, adev-&gt;gmc.mem_partitions);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		valid = true;</div><div class='add'>+	else</div><div class='add'>+		valid = amdgpu_gmc_validate_partition_info(adev);</div><div class='add'>+	if (!valid) {</div><div class='add'>+		/* TODO: handle invalid case */</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "Mem ranges not matching with hardware config\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h<br/>index 17f40ea1104b..727342689d4b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_irq.h"</div><div class='add'>+#include "amdgpu_xgmi.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> </div><div class='ctx'> /* VA hole for 48bit addresses on Vega10 */</div><div class='hunk'>@@ -61,6 +62,9 @@</div><div class='ctx'>  */</div><div class='ctx'> #define AMDGPU_GMC_FAULT_TIMEOUT	5000ULL</div><div class='ctx'> </div><div class='add'>+/* XNACK flags */</div><div class='add'>+#define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0)</div><div class='add'>+</div><div class='ctx'> struct firmware;</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_memory_partition {</div><div class='hunk'>@@ -73,6 +77,20 @@ enum amdgpu_memory_partition {</div><div class='ctx'> 	AMDGPU_NPS8_PARTITION_MODE = 8,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_ALL_NPS_MASK                                                  \</div><div class='add'>+	(BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \</div><div class='add'>+	 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \</div><div class='add'>+	 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE))</div><div class='add'>+</div><div class='add'>+#define AMDGPU_GMC_INIT_RESET_NPS  BIT(0)</div><div class='add'>+</div><div class='add'>+#define AMDGPU_MAX_MEM_RANGES 8</div><div class='add'>+</div><div class='add'>+#define AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY 0x80</div><div class='add'>+#define AMDGPU_GMC9_FAULT_SOURCE_DATA_READ  0x40</div><div class='add'>+#define AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE 0x20</div><div class='add'>+#define AMDGPU_GMC9_FAULT_SOURCE_DATA_EXE   0x10</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * GMC page fault information</div><div class='ctx'>  */</div><div class='hunk'>@@ -141,47 +159,30 @@ struct amdgpu_gmc_funcs {</div><div class='ctx'> 				   unsigned pasid);</div><div class='ctx'> 	/* enable/disable PRT support */</div><div class='ctx'> 	void (*set_prt)(struct amdgpu_device *adev, bool enable);</div><div class='del'>-	/* map mtype to hardware flags */</div><div class='del'>-	uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);</div><div class='ctx'> 	/* get the pde for a given mc addr */</div><div class='ctx'> 	void (*get_vm_pde)(struct amdgpu_device *adev, int level,</div><div class='ctx'> 			   u64 *dst, u64 *flags);</div><div class='del'>-	/* get the pte flags to use for a BO VA mapping */</div><div class='add'>+	/* get the pte flags to use for PTEs */</div><div class='ctx'> 	void (*get_vm_pte)(struct amdgpu_device *adev,</div><div class='del'>-			   struct amdgpu_bo_va_mapping *mapping,</div><div class='del'>-			   uint64_t *flags);</div><div class='add'>+			   struct amdgpu_vm *vm,</div><div class='add'>+			   struct amdgpu_bo *bo,</div><div class='add'>+			   uint32_t vm_flags,</div><div class='add'>+			   uint64_t *pte_flags);</div><div class='ctx'> 	/* override per-page pte flags */</div><div class='ctx'> 	void (*override_vm_pte_flags)(struct amdgpu_device *dev,</div><div class='ctx'> 				      struct amdgpu_vm *vm,</div><div class='ctx'> 				      uint64_t addr, uint64_t *flags);</div><div class='ctx'> 	/* get the amount of memory used by the vbios for pre-OS console */</div><div class='ctx'> 	unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);</div><div class='add'>+	/* get the DCC buffer alignment */</div><div class='add'>+	unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> 	enum amdgpu_memory_partition (*query_mem_partition_mode)(</div><div class='ctx'> 		struct amdgpu_device *adev);</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct amdgpu_xgmi_ras {</div><div class='del'>-	struct amdgpu_ras_block_object ras_block;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct amdgpu_xgmi {</div><div class='del'>-	/* from psp */</div><div class='del'>-	u64 node_id;</div><div class='del'>-	u64 hive_id;</div><div class='del'>-	/* fixed per family */</div><div class='del'>-	u64 node_segment_size;</div><div class='del'>-	/* physical node (0-3) */</div><div class='del'>-	unsigned physical_node_id;</div><div class='del'>-	/* number of nodes (0-4) */</div><div class='del'>-	unsigned num_physical_nodes;</div><div class='del'>-	/* gpu list in the same hive */</div><div class='del'>-	struct list_head head;</div><div class='del'>-	bool supported;</div><div class='del'>-	struct ras_common_if *ras_if;</div><div class='del'>-	bool connected_to_cpu;</div><div class='del'>-	bool pending_reset;</div><div class='del'>-	struct amdgpu_xgmi_ras *ras;</div><div class='add'>+	/* Request NPS mode */</div><div class='add'>+	int (*request_mem_partition_mode)(struct amdgpu_device *adev,</div><div class='add'>+					  int nps_mode);</div><div class='add'>+	bool (*need_reset_on_init)(struct amdgpu_device *adev);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_mem_partition_info {</div><div class='hunk'>@@ -199,6 +200,13 @@ struct amdgpu_mem_partition_info {</div><div class='ctx'> </div><div class='ctx'> #define INVALID_PFN    -1</div><div class='ctx'> </div><div class='add'>+struct amdgpu_gmc_memrange {</div><div class='add'>+	uint64_t base_address;</div><div class='add'>+	uint64_t limit_address;</div><div class='add'>+	uint32_t flags;</div><div class='add'>+	int nid_mask;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum amdgpu_gart_placement {</div><div class='ctx'> 	AMDGPU_GART_PLACEMENT_BEST_FIT = 0,</div><div class='ctx'> 	AMDGPU_GART_PLACEMENT_HIGH,</div><div class='hunk'>@@ -296,10 +304,14 @@ struct amdgpu_gmc {</div><div class='ctx'> 	struct amdgpu_mem_partition_info *mem_partitions;</div><div class='ctx'> 	uint8_t num_mem_partitions;</div><div class='ctx'> 	const struct amdgpu_gmc_funcs	*gmc_funcs;</div><div class='add'>+	enum amdgpu_memory_partition	requested_nps_mode;</div><div class='add'>+	uint32_t supported_nps_modes;</div><div class='add'>+	uint32_t reset_flags;</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_xgmi xgmi;</div><div class='ctx'> 	struct amdgpu_irq_src	ecc_irq;</div><div class='ctx'> 	int noretry;</div><div class='add'>+	uint32_t xnack_flags;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t	vmid0_page_table_block_size;</div><div class='ctx'> 	uint32_t	vmid0_page_table_depth;</div><div class='hunk'>@@ -349,13 +361,18 @@ struct amdgpu_gmc {</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)-&gt;adev-&gt;gmc.gmc_funcs-&gt;emit_flush_gpu_tlb((r), (vmid), (addr))</div><div class='ctx'> #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)-&gt;adev-&gt;gmc.gmc_funcs-&gt;emit_pasid_mapping((r), (vmid), (pasid))</div><div class='del'>-#define amdgpu_gmc_map_mtype(adev, flags) (adev)-&gt;gmc.gmc_funcs-&gt;map_mtype((adev),(flags))</div><div class='ctx'> #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)-&gt;gmc.gmc_funcs-&gt;get_vm_pde((adev), (level), (dst), (flags))</div><div class='del'>-#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)-&gt;gmc.gmc_funcs-&gt;get_vm_pte((adev), (mapping), (flags))</div><div class='add'>+#define amdgpu_gmc_get_vm_pte(adev, vm, bo, vm_flags, pte_flags) \</div><div class='add'>+	((adev)-&gt;gmc.gmc_funcs-&gt;get_vm_pte((adev), (vm), (bo), (vm_flags), \</div><div class='add'>+					   (pte_flags)))</div><div class='ctx'> #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags)	\</div><div class='ctx'> 	(adev)-&gt;gmc.gmc_funcs-&gt;override_vm_pte_flags			\</div><div class='ctx'> 		((adev), (vm), (addr), (pte_flags))</div><div class='ctx'> #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)-&gt;gmc.gmc_funcs-&gt;get_vbios_fb_size((adev))</div><div class='add'>+#define amdgpu_gmc_get_dcc_alignment(adev) ({			\</div><div class='add'>+	typeof(adev) _adev = (adev);				\</div><div class='add'>+	_adev-&gt;gmc.gmc_funcs-&gt;get_dcc_alignment(_adev);		\</div><div class='add'>+})</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR</div><div class='hunk'>@@ -385,6 +402,7 @@ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)</div><div class='ctx'> 	return addr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,</div><div class='ctx'> 			       uint64_t *addr, uint64_t *flags);</div><div class='hunk'>@@ -434,9 +452,25 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);</div><div class='ctx'> uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);</div><div class='ctx'> uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);</div><div class='del'>-uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);</div><div class='ctx'> int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_mem_partition_info *mem_ranges,</div><div class='add'>+				 uint8_t *exp_ranges);</div><div class='add'>+</div><div class='add'>+int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev,</div><div class='add'>+					int nps_mode);</div><div class='add'>+void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev);</div><div class='add'>+enum amdgpu_memory_partition</div><div class='add'>+amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev);</div><div class='add'>+enum amdgpu_memory_partition</div><div class='add'>+amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes);</div><div class='add'>+enum amdgpu_memory_partition</div><div class='add'>+amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev,</div><div class='add'>+				   struct amdgpu_mem_partition_info *mem_ranges);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c<br/>index 44367f03316f..895c1e4c6747 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c</a></div><div class='hunk'>@@ -200,8 +200,6 @@ void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)</div><div class='ctx'> 		amdgpu_ttm_recover_gart(node-&gt;base.bo);</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock(&amp;mgr-&gt;lock);</div><div class='del'>-</div><div class='del'>-	amdgpu_gart_invalidate_tlb(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -286,6 +284,7 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)</div><div class='ctx'> 	ttm_resource_manager_init(man, &amp;adev-&gt;mman.bdev, gtt_size);</div><div class='ctx'> </div><div class='ctx'> 	start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;</div><div class='add'>+	start += amdgpu_vce_required_gart_pages(adev);</div><div class='ctx'> 	size = (adev-&gt;gmc.gart_size &gt;&gt; PAGE_SHIFT) - start;</div><div class='ctx'> 	drm_mm_init(&amp;mgr-&gt;mm, start, size);</div><div class='ctx'> 	spin_lock_init(&amp;mgr-&gt;lock);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c<br/>index b6cf801939aa..5a60d69a3e1f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c</a></div><div class='hunk'>@@ -22,6 +22,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='ctx'> </div><div class='ctx'> int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -46,3 +47,38 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* hdp ras follows amdgpu_ras_block_late_init_default for late init */</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,</div><div class='add'>+			      struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	if (!ring || !ring-&gt;funcs-&gt;emit_wreg) {</div><div class='add'>+		WREG32((adev-&gt;rmmio_remap.reg_offset +</div><div class='add'>+			KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt;</div><div class='add'>+			       2,</div><div class='add'>+		       0);</div><div class='add'>+		if (adev-&gt;nbio.funcs-&gt;get_memsize)</div><div class='add'>+			adev-&gt;nbio.funcs-&gt;get_memsize(adev);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_ring_emit_wreg(ring,</div><div class='add'>+				      (adev-&gt;rmmio_remap.reg_offset +</div><div class='add'>+				       KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt;</div><div class='add'>+					      2,</div><div class='add'>+				      0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_hdp_invalidate(struct amdgpu_device *adev, struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;asic_funcs &amp;&amp; adev-&gt;asic_funcs-&gt;invalidate_hdp)</div><div class='add'>+		adev-&gt;asic_funcs-&gt;invalidate_hdp(adev, ring);</div><div class='add'>+	else if (adev-&gt;hdp.funcs &amp;&amp; adev-&gt;hdp.funcs-&gt;invalidate_hdp)</div><div class='add'>+		adev-&gt;hdp.funcs-&gt;invalidate_hdp(adev, ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_hdp_flush(struct amdgpu_device *adev, struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;asic_funcs &amp;&amp; adev-&gt;asic_funcs-&gt;flush_hdp)</div><div class='add'>+		adev-&gt;asic_funcs-&gt;flush_hdp(adev, ring);</div><div class='add'>+	else if (adev-&gt;hdp.funcs &amp;&amp; adev-&gt;hdp.funcs-&gt;flush_hdp)</div><div class='add'>+		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, ring);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h<br/>index 7b8a6152dc8d..d9f488fa76b9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h</a></div><div class='hunk'>@@ -44,4 +44,10 @@ struct amdgpu_hdp {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,</div><div class='add'>+			      struct amdgpu_ring *ring);</div><div class='add'>+void amdgpu_hdp_invalidate(struct amdgpu_device *adev,</div><div class='add'>+			   struct amdgpu_ring *ring);</div><div class='add'>+void amdgpu_hdp_flush(struct amdgpu_device *adev,</div><div class='add'>+		      struct amdgpu_ring *ring);</div><div class='ctx'> #endif /* __AMDGPU_HDP_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c<br/>index 431ec72655ec..90d26d820bac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c</a></div><div class='hunk'>@@ -167,19 +167,14 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo)</div><div class='ctx'> </div><div class='ctx'> int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,</div><div class='ctx'> 			       uint64_t start, uint64_t npages, bool readonly,</div><div class='del'>-			       void *owner, struct page **pages,</div><div class='del'>-			       struct hmm_range **phmm_range)</div><div class='add'>+			       void *owner,</div><div class='add'>+			       struct amdgpu_hmm_range *range)</div><div class='ctx'> {</div><div class='del'>-	struct hmm_range *hmm_range;</div><div class='ctx'> 	unsigned long end;</div><div class='ctx'> 	unsigned long timeout;</div><div class='del'>-	unsigned long i;</div><div class='ctx'> 	unsigned long *pfns;</div><div class='ctx'> 	int r = 0;</div><div class='del'>-</div><div class='del'>-	hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL);</div><div class='del'>-	if (unlikely(!hmm_range))</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	struct hmm_range *hmm_range = &amp;range-&gt;hmm_range;</div><div class='ctx'> </div><div class='ctx'> 	pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL);</div><div class='ctx'> 	if (unlikely(!pfns)) {</div><div class='hunk'>@@ -202,20 +197,12 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,</div><div class='ctx'> 		pr_debug("hmm range: start = 0x%lx, end = 0x%lx",</div><div class='ctx'> 			hmm_range-&gt;start, hmm_range-&gt;end);</div><div class='ctx'> </div><div class='del'>-		/* Assuming 64MB takes maximum 1 second to fault page address */</div><div class='del'>-		timeout = max((hmm_range-&gt;end - hmm_range-&gt;start) &gt;&gt; 26, 1UL);</div><div class='del'>-		timeout *= HMM_RANGE_DEFAULT_TIMEOUT;</div><div class='del'>-		timeout = jiffies + msecs_to_jiffies(timeout);</div><div class='add'>+		timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);</div><div class='ctx'> </div><div class='ctx'> retry:</div><div class='ctx'> 		hmm_range-&gt;notifier_seq = mmu_interval_read_begin(notifier);</div><div class='ctx'> 		r = hmm_range_fault(hmm_range);</div><div class='ctx'> 		if (unlikely(r)) {</div><div class='del'>-			schedule();</div><div class='del'>-			/*</div><div class='del'>-			 * FIXME: This timeout should encompass the retry from</div><div class='del'>-			 * mmu_interval_read_retry() as well.</div><div class='del'>-			 */</div><div class='ctx'> 			if (r == -EBUSY &amp;&amp; !time_after(jiffies, timeout))</div><div class='ctx'> 				goto retry;</div><div class='ctx'> 			goto out_free_pfns;</div><div class='hunk'>@@ -230,34 +217,77 @@ retry:</div><div class='ctx'> 	hmm_range-&gt;start = start;</div><div class='ctx'> 	hmm_range-&gt;hmm_pfns = pfns;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Due to default_flags, all pages are HMM_PFN_VALID or</div><div class='del'>-	 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside</div><div class='del'>-	 * the notifier_lock, and mmu_interval_read_retry() must be done first.</div><div class='del'>-	 */</div><div class='del'>-	for (i = 0; pages &amp;&amp; i &lt; npages; i++)</div><div class='del'>-		pages[i] = hmm_pfn_to_page(pfns[i]);</div><div class='del'>-</div><div class='del'>-	*phmm_range = hmm_range;</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_free_pfns:</div><div class='ctx'> 	kvfree(pfns);</div><div class='add'>+	hmm_range-&gt;hmm_pfns = NULL;</div><div class='ctx'> out_free_range:</div><div class='del'>-	kfree(hmm_range);</div><div class='del'>-</div><div class='add'>+	if (r == -EBUSY)</div><div class='add'>+		r = -EAGAIN;</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range)</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_hmm_range_valid - check if an HMM range is still valid</div><div class='add'>+ * @range: pointer to the &amp;struct amdgpu_hmm_range to validate</div><div class='add'>+ *</div><div class='add'>+ * Determines whether the given HMM range @range is still valid by</div><div class='add'>+ * checking for invalidations via the MMU notifier sequence. This is</div><div class='add'>+ * typically used to verify that the range has not been invalidated</div><div class='add'>+ * by concurrent address space updates before it is accessed.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ * * true if @range is valid and can be used safely</div><div class='add'>+ * * false if @range is NULL or has been invalidated</div><div class='add'>+ */</div><div class='add'>+bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range)</div><div class='ctx'> {</div><div class='del'>-	bool r;</div><div class='add'>+	if (!range)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	r = mmu_interval_read_retry(hmm_range-&gt;notifier,</div><div class='del'>-				    hmm_range-&gt;notifier_seq);</div><div class='del'>-	kvfree(hmm_range-&gt;hmm_pfns);</div><div class='del'>-	kfree(hmm_range);</div><div class='add'>+	return !mmu_interval_read_retry(range-&gt;hmm_range.notifier,</div><div class='add'>+					range-&gt;hmm_range.notifier_seq);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_hmm_range_alloc - allocate and initialize an AMDGPU HMM range</div><div class='add'>+ * @bo: optional buffer object to associate with this HMM range</div><div class='add'>+ *</div><div class='add'>+ * Allocates memory for amdgpu_hmm_range and associates it with the @bo passed.</div><div class='add'>+ * The reference count of the @bo is incremented.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ * Pointer to a newly allocated struct amdgpu_hmm_range on success,</div><div class='add'>+ * or NULL if memory allocation fails.</div><div class='add'>+ */</div><div class='add'>+struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_hmm_range *range;</div><div class='add'>+</div><div class='add'>+	range = kzalloc(sizeof(*range), GFP_KERNEL);</div><div class='add'>+	if (!range)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	range-&gt;bo = amdgpu_bo_ref(bo);</div><div class='add'>+	return range;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_hmm_range_free - release an AMDGPU HMM range</div><div class='add'>+ * @range: pointer to the range object to free</div><div class='add'>+ *</div><div class='add'>+ * Releases all resources held by @range, including the associated</div><div class='add'>+ * hmm_pfns and the dropping reference of associated bo if any.</div><div class='add'>+ *</div><div class='add'>+ * Return: void</div><div class='add'>+ */</div><div class='add'>+void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range)</div><div class='add'>+{</div><div class='add'>+	if (!range)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	kvfree(range-&gt;hmm_range.hmm_pfns);</div><div class='add'>+	amdgpu_bo_unref(&amp;range-&gt;bo);</div><div class='add'>+	kfree(range);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h<br/>index e2edcd010ccc..140bc9cd57b4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h</a></div><div class='hunk'>@@ -31,13 +31,20 @@</div><div class='ctx'> #include &lt;linux/interval_tree.h&gt;</div><div class='ctx'> #include &lt;linux/mmu_notifier.h&gt;</div><div class='ctx'> </div><div class='add'>+struct amdgpu_hmm_range {</div><div class='add'>+	struct hmm_range hmm_range;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,</div><div class='ctx'> 			       uint64_t start, uint64_t npages, bool readonly,</div><div class='del'>-			       void *owner, struct page **pages,</div><div class='del'>-			       struct hmm_range **phmm_range);</div><div class='del'>-bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range);</div><div class='add'>+			       void *owner,</div><div class='add'>+			       struct amdgpu_hmm_range *range);</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_HMM_MIRROR)</div><div class='add'>+bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range);</div><div class='add'>+struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo);</div><div class='add'>+void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range);</div><div class='ctx'> int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr);</div><div class='ctx'> void amdgpu_hmm_unregister(struct amdgpu_bo *bo);</div><div class='ctx'> #else</div><div class='hunk'>@@ -47,7 +54,20 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr)</div><div class='ctx'> 		      "add CONFIG_ZONE_DEVICE=y in config file to fix this\n");</div><div class='ctx'> 	return -ENODEV;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {}</div><div class='add'>+</div><div class='add'>+static inline bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) {}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c<br/>index d79cb13e1aa8..9cb72f0c5277 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c</a></div><div class='hunk'>@@ -24,7 +24,6 @@</div><div class='ctx'>  *          Alex Deucher</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/export.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_edid.h&gt;</div><div class='hunk'>@@ -185,7 +184,7 @@ struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,</div><div class='ctx'> 		snprintf(i2c-&gt;adapter.name, sizeof(i2c-&gt;adapter.name),</div><div class='ctx'> 			 "AMDGPU i2c hw bus %s", name);</div><div class='ctx'> 		i2c-&gt;adapter.algo = &amp;amdgpu_atombios_i2c_algo;</div><div class='del'>-		ret = i2c_add_adapter(&amp;i2c-&gt;adapter);</div><div class='add'>+		ret = devm_i2c_add_adapter(dev-&gt;dev, &amp;i2c-&gt;adapter);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto out_free;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -216,22 +215,23 @@ out_free:</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)</div><div class='del'>-{</div><div class='del'>-	if (!i2c)</div><div class='del'>-		return;</div><div class='del'>-	WARN_ON(i2c-&gt;has_aux);</div><div class='del'>-	i2c_del_adapter(&amp;i2c-&gt;adapter);</div><div class='del'>-	kfree(i2c);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Add the default buses */</div><div class='ctx'> void amdgpu_i2c_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (amdgpu_hw_i2c)</div><div class='del'>-		DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");</div><div class='del'>-</div><div class='del'>-	amdgpu_atombios_i2c_init(adev);</div><div class='add'>+	if (!adev-&gt;is_atom_fw) {</div><div class='add'>+		if (!amdgpu_device_has_dc_support(adev)) {</div><div class='add'>+			amdgpu_atombios_i2c_init(adev);</div><div class='add'>+		} else {</div><div class='add'>+			switch (adev-&gt;asic_type) {</div><div class='add'>+			case CHIP_POLARIS10:</div><div class='add'>+			case CHIP_POLARIS11:</div><div class='add'>+			case CHIP_POLARIS12:</div><div class='add'>+				amdgpu_atombios_oem_i2c_init(adev, 0x97);</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* remove all the buses */</div><div class='hunk'>@@ -239,28 +239,9 @@ void amdgpu_i2c_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MAX_I2C_BUS; i++) {</div><div class='del'>-		if (adev-&gt;i2c_bus[i]) {</div><div class='del'>-			amdgpu_i2c_destroy(adev-&gt;i2c_bus[i]);</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_I2C_BUS; i++)</div><div class='add'>+		if (adev-&gt;i2c_bus[i])</div><div class='ctx'> 			adev-&gt;i2c_bus[i] = NULL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Add additional buses */</div><div class='del'>-void amdgpu_i2c_add(struct amdgpu_device *adev,</div><div class='del'>-		    const struct amdgpu_i2c_bus_rec *rec,</div><div class='del'>-		    const char *name)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = adev_to_drm(adev);</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MAX_I2C_BUS; i++) {</div><div class='del'>-		if (!adev-&gt;i2c_bus[i]) {</div><div class='del'>-			adev-&gt;i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* looks up bus based on id */</div><div class='hunk'>@@ -279,7 +260,7 @@ amdgpu_i2c_lookup(struct amdgpu_device *adev,</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,</div><div class='add'>+static int amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,</div><div class='ctx'> 				 u8 slave_addr,</div><div class='ctx'> 				 u8 addr,</div><div class='ctx'> 				 u8 *val)</div><div class='hunk'>@@ -304,16 +285,18 @@ static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,</div><div class='ctx'> 	out_buf[0] = addr;</div><div class='ctx'> 	out_buf[1] = 0;</div><div class='ctx'> </div><div class='del'>-	if (i2c_transfer(&amp;i2c_bus-&gt;adapter, msgs, 2) == 2) {</div><div class='del'>-		*val = in_buf[0];</div><div class='del'>-		DRM_DEBUG("val = 0x%02x\n", *val);</div><div class='del'>-	} else {</div><div class='del'>-		DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",</div><div class='del'>-			  addr, *val);</div><div class='add'>+	if (i2c_transfer(&amp;i2c_bus-&gt;adapter, msgs, 2) != 2) {</div><div class='add'>+		DRM_DEBUG("i2c 0x%02x read failed\n", addr);</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	*val = in_buf[0];</div><div class='add'>+	DRM_DEBUG("val = 0x%02x\n", *val);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,</div><div class='add'>+static int amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,</div><div class='ctx'> 				 u8 slave_addr,</div><div class='ctx'> 				 u8 addr,</div><div class='ctx'> 				 u8 val)</div><div class='hunk'>@@ -329,9 +312,12 @@ static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,</div><div class='ctx'> 	out_buf[0] = addr;</div><div class='ctx'> 	out_buf[1] = val;</div><div class='ctx'> </div><div class='del'>-	if (i2c_transfer(&amp;i2c_bus-&gt;adapter, &amp;msg, 1) != 1)</div><div class='del'>-		DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",</div><div class='del'>-			  addr, val);</div><div class='add'>+	if (i2c_transfer(&amp;i2c_bus-&gt;adapter, &amp;msg, 1) != 1) {</div><div class='add'>+		DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", addr, val);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* ddc router switching */</div><div class='hunk'>@@ -346,16 +332,18 @@ amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connecto</div><div class='ctx'> 	if (!amdgpu_connector-&gt;router_bus)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='add'>+	if (amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='ctx'> 			    amdgpu_connector-&gt;router.i2c_addr,</div><div class='del'>-			    0x3, &amp;val);</div><div class='add'>+			    0x3, &amp;val))</div><div class='add'>+		return;</div><div class='ctx'> 	val &amp;= ~amdgpu_connector-&gt;router.ddc_mux_control_pin;</div><div class='ctx'> 	amdgpu_i2c_put_byte(amdgpu_connector-&gt;router_bus,</div><div class='ctx'> 			    amdgpu_connector-&gt;router.i2c_addr,</div><div class='ctx'> 			    0x3, val);</div><div class='del'>-	amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='add'>+	if (amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='ctx'> 			    amdgpu_connector-&gt;router.i2c_addr,</div><div class='del'>-			    0x1, &amp;val);</div><div class='add'>+			    0x1, &amp;val))</div><div class='add'>+		return;</div><div class='ctx'> 	val &amp;= ~amdgpu_connector-&gt;router.ddc_mux_control_pin;</div><div class='ctx'> 	val |= amdgpu_connector-&gt;router.ddc_mux_state;</div><div class='ctx'> 	amdgpu_i2c_put_byte(amdgpu_connector-&gt;router_bus,</div><div class='hunk'>@@ -375,16 +363,18 @@ amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector</div><div class='ctx'> 	if (!amdgpu_connector-&gt;router_bus)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='add'>+	if (amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='ctx'> 			    amdgpu_connector-&gt;router.i2c_addr,</div><div class='del'>-			    0x3, &amp;val);</div><div class='add'>+			    0x3, &amp;val))</div><div class='add'>+		return;</div><div class='ctx'> 	val &amp;= ~amdgpu_connector-&gt;router.cd_mux_control_pin;</div><div class='ctx'> 	amdgpu_i2c_put_byte(amdgpu_connector-&gt;router_bus,</div><div class='ctx'> 			    amdgpu_connector-&gt;router.i2c_addr,</div><div class='ctx'> 			    0x3, val);</div><div class='del'>-	amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='add'>+	if (amdgpu_i2c_get_byte(amdgpu_connector-&gt;router_bus,</div><div class='ctx'> 			    amdgpu_connector-&gt;router.i2c_addr,</div><div class='del'>-			    0x1, &amp;val);</div><div class='add'>+			    0x1, &amp;val))</div><div class='add'>+		return;</div><div class='ctx'> 	val &amp;= ~amdgpu_connector-&gt;router.cd_mux_control_pin;</div><div class='ctx'> 	val |= amdgpu_connector-&gt;router.cd_mux_state;</div><div class='ctx'> 	amdgpu_i2c_put_byte(amdgpu_connector-&gt;router_bus,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h<br/>index 63c2ff7499e1..1d3d3806e0dd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h</a></div><div class='hunk'>@@ -30,9 +30,6 @@ struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,</div><div class='ctx'> void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c);</div><div class='ctx'> void amdgpu_i2c_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_i2c_fini(struct amdgpu_device *adev);</div><div class='del'>-void amdgpu_i2c_add(struct amdgpu_device *adev,</div><div class='del'>-		    const struct amdgpu_i2c_bus_rec *rec,</div><div class='del'>-		    const char *name);</div><div class='ctx'> struct amdgpu_i2c_chan *</div><div class='ctx'> amdgpu_i2c_lookup(struct amdgpu_device *adev,</div><div class='ctx'> 		  const struct amdgpu_i2c_bus_rec *i2c_bus);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c<br/>index 8b512dc28df8..586a58facca1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c</a></div><div class='hunk'>@@ -89,16 +89,14 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_ib_free - free an IB (Indirect Buffer)</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='ctx'>  * @ib: IB object to free</div><div class='ctx'>  * @f: the fence SA bo need wait on for the ib alloation</div><div class='ctx'>  *</div><div class='ctx'>  * Free an IB (all asics).</div><div class='ctx'>  */</div><div class='del'>-void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,</div><div class='del'>-		    struct dma_fence *f)</div><div class='add'>+void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_sa_bo_free(adev, &amp;ib-&gt;sa_bo, f);</div><div class='add'>+	amdgpu_sa_bo_free(&amp;ib-&gt;sa_bo, f);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -130,6 +128,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ib *ib = &amp;ibs[0];</div><div class='ctx'> 	struct dma_fence *tmp = NULL;</div><div class='add'>+	struct amdgpu_fence *af;</div><div class='ctx'> 	bool need_ctx_switch;</div><div class='ctx'> 	struct amdgpu_vm *vm;</div><div class='ctx'> 	uint64_t fence_ctx;</div><div class='hunk'>@@ -140,7 +139,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 	int vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='ctx'> 	bool need_pipe_sync = false;</div><div class='ctx'> 	unsigned int cond_exec;</div><div class='del'>-</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -151,11 +149,19 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 	if (job) {</div><div class='ctx'> 		vm = job-&gt;vm;</div><div class='ctx'> 		fence_ctx = job-&gt;base.s_fence ?</div><div class='del'>-			job-&gt;base.s_fence-&gt;scheduled.context : 0;</div><div class='add'>+			job-&gt;base.s_fence-&gt;finished.context : 0;</div><div class='ctx'> 		shadow_va = job-&gt;shadow_va;</div><div class='ctx'> 		csa_va = job-&gt;csa_va;</div><div class='ctx'> 		gds_va = job-&gt;gds_va;</div><div class='ctx'> 		init_shadow = job-&gt;init_shadow;</div><div class='add'>+		af = job-&gt;hw_fence;</div><div class='add'>+		/* Save the context of the job for reset handling.</div><div class='add'>+		 * The driver needs this so it can skip the ring</div><div class='add'>+		 * contents for guilty contexts.</div><div class='add'>+		 */</div><div class='add'>+		af-&gt;context = fence_ctx;</div><div class='add'>+		/* the vm fence is also part of the job's context */</div><div class='add'>+		job-&gt;hw_vm_fence-&gt;context = fence_ctx;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		vm = NULL;</div><div class='ctx'> 		fence_ctx = 0;</div><div class='hunk'>@@ -163,22 +169,28 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 		csa_va = 0;</div><div class='ctx'> 		gds_va = 0;</div><div class='ctx'> 		init_shadow = false;</div><div class='add'>+		af = kzalloc(sizeof(*af), GFP_ATOMIC);</div><div class='add'>+		if (!af)</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;sched.ready &amp;&amp; !ring-&gt;is_mes_queue) {</div><div class='add'>+	if (!ring-&gt;sched.ready) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "couldn't schedule ib on ring &lt;%s&gt;\n", ring-&gt;name);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto free_fence;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vm &amp;&amp; !job-&gt;vmid &amp;&amp; !ring-&gt;is_mes_queue) {</div><div class='add'>+	if (vm &amp;&amp; !job-&gt;vmid) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "VM IB without ID\n");</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto free_fence;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if ((ib-&gt;flags &amp; AMDGPU_IB_FLAGS_SECURE) &amp;&amp;</div><div class='ctx'> 	    (!ring-&gt;funcs-&gt;secure_submission_supported)) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "secure submissions not supported on ring &lt;%s&gt;\n", ring-&gt;name);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto free_fence;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	alloc_size = ring-&gt;funcs-&gt;emit_frame_size + num_ibs *</div><div class='hunk'>@@ -187,14 +199,14 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, alloc_size);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "scheduling IB failed (%d).\n", r);</div><div class='del'>-		return r;</div><div class='add'>+		goto free_fence;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	need_ctx_switch = ring-&gt;current_ctx != fence_ctx;</div><div class='ctx'> 	if (ring-&gt;funcs-&gt;emit_pipeline_sync &amp;&amp; job &amp;&amp;</div><div class='ctx'> 	    ((tmp = amdgpu_sync_get_fence(&amp;job-&gt;explicit_sync)) ||</div><div class='del'>-	     (amdgpu_sriov_vf(adev) &amp;&amp; need_ctx_switch) ||</div><div class='del'>-	     amdgpu_vm_need_pipeline_sync(ring, job))) {</div><div class='add'>+	     need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {</div><div class='add'>+</div><div class='ctx'> 		need_pipe_sync = true;</div><div class='ctx'> </div><div class='ctx'> 		if (tmp)</div><div class='hunk'>@@ -284,7 +296,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 		amdgpu_ring_init_cond_exec(ring, ring-&gt;cond_exe_gpu_addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_fence_emit(ring, f, job, fence_flags);</div><div class='add'>+	r = amdgpu_fence_emit(ring, af, fence_flags);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "failed to emit fence (%d)\n", r);</div><div class='ctx'> 		if (job &amp;&amp; job-&gt;vmid)</div><div class='hunk'>@@ -292,6 +304,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 		amdgpu_ring_undo(ring);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='add'>+	*f = &amp;af-&gt;base;</div><div class='add'>+	/* get a ref for the job */</div><div class='add'>+	if (job)</div><div class='add'>+		dma_fence_get(*f);</div><div class='ctx'> </div><div class='ctx'> 	if (ring-&gt;funcs-&gt;insert_end)</div><div class='ctx'> 		ring-&gt;funcs-&gt;insert_end(ring);</div><div class='hunk'>@@ -299,16 +315,30 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,</div><div class='ctx'> 	amdgpu_ring_patch_cond_exec(ring, cond_exec);</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;current_ctx = fence_ctx;</div><div class='del'>-	if (vm &amp;&amp; ring-&gt;funcs-&gt;emit_switch_buffer)</div><div class='add'>+	if (job &amp;&amp; ring-&gt;funcs-&gt;emit_switch_buffer)</div><div class='ctx'> 		amdgpu_ring_emit_switch_buffer(ring);</div><div class='ctx'> </div><div class='ctx'> 	if (ring-&gt;funcs-&gt;emit_wave_limit &amp;&amp;</div><div class='ctx'> 	    ring-&gt;hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)</div><div class='ctx'> 		ring-&gt;funcs-&gt;emit_wave_limit(ring, false);</div><div class='ctx'> </div><div class='add'>+	/* Save the wptr associated with this fence.</div><div class='add'>+	 * This must be last for resets to work properly</div><div class='add'>+	 * as we need to save the wptr associated with this</div><div class='add'>+	 * fence so we know what rings contents to backup</div><div class='add'>+	 * after we reset the queue.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_fence_save_wptr(af);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_ib_end(ring);</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+free_fence:</div><div class='add'>+	if (!job)</div><div class='add'>+		kfree(af);</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c<br/>index 3d7fcdeaf8cf..9cab36322c16 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c</a></div><div class='hunk'>@@ -201,58 +201,34 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_ring *ring,</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	unsigned vmhub = ring-&gt;vm_hub;</div><div class='ctx'> 	struct amdgpu_vmid_mgr *id_mgr = &amp;adev-&gt;vm_manager.id_mgr[vmhub];</div><div class='del'>-	struct dma_fence **fences;</div><div class='del'>-	unsigned i;</div><div class='ctx'> </div><div class='add'>+	/* If anybody is waiting for a VMID let everybody wait for fairness */</div><div class='ctx'> 	if (!dma_fence_is_signaled(ring-&gt;vmid_wait)) {</div><div class='ctx'> 		*fence = dma_fence_get(ring-&gt;vmid_wait);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	fences = kmalloc_array(id_mgr-&gt;num_ids, sizeof(void *), GFP_KERNEL);</div><div class='del'>-	if (!fences)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='ctx'> 	/* Check if we have an idle VMID */</div><div class='del'>-	i = 0;</div><div class='del'>-	list_for_each_entry((*idle), &amp;id_mgr-&gt;ids_lru, list) {</div><div class='add'>+	list_for_each_entry_reverse((*idle), &amp;id_mgr-&gt;ids_lru, list) {</div><div class='ctx'> 		/* Don't use per engine and per process VMID at the same time */</div><div class='ctx'> 		struct amdgpu_ring *r = adev-&gt;vm_manager.concurrent_flush ?</div><div class='ctx'> 			NULL : ring;</div><div class='ctx'> </div><div class='del'>-		fences[i] = amdgpu_sync_peek_fence(&amp;(*idle)-&gt;active, r);</div><div class='del'>-		if (!fences[i])</div><div class='del'>-			break;</div><div class='del'>-		++i;</div><div class='add'>+		*fence = amdgpu_sync_peek_fence(&amp;(*idle)-&gt;active, r);</div><div class='add'>+		if (!(*fence))</div><div class='add'>+			return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* If we can't find a idle VMID to use, wait till one becomes available */</div><div class='del'>-	if (&amp;(*idle)-&gt;list == &amp;id_mgr-&gt;ids_lru) {</div><div class='del'>-		u64 fence_context = adev-&gt;vm_manager.fence_context + ring-&gt;idx;</div><div class='del'>-		unsigned seqno = ++adev-&gt;vm_manager.seqno[ring-&gt;idx];</div><div class='del'>-		struct dma_fence_array *array;</div><div class='del'>-		unsigned j;</div><div class='del'>-</div><div class='del'>-		*idle = NULL;</div><div class='del'>-		for (j = 0; j &lt; i; ++j)</div><div class='del'>-			dma_fence_get(fences[j]);</div><div class='del'>-</div><div class='del'>-		array = dma_fence_array_create(i, fences, fence_context,</div><div class='del'>-					       seqno, true);</div><div class='del'>-		if (!array) {</div><div class='del'>-			for (j = 0; j &lt; i; ++j)</div><div class='del'>-				dma_fence_put(fences[j]);</div><div class='del'>-			kfree(fences);</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		*fence = dma_fence_get(&amp;array-&gt;base);</div><div class='del'>-		dma_fence_put(ring-&gt;vmid_wait);</div><div class='del'>-		ring-&gt;vmid_wait = &amp;array-&gt;base;</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-	kfree(fences);</div><div class='add'>+	/*</div><div class='add'>+	 * If we can't find a idle VMID to use, wait on a fence from the least</div><div class='add'>+	 * recently used in the hope that it will be available soon.</div><div class='add'>+	 */</div><div class='add'>+	*idle = NULL;</div><div class='add'>+	dma_fence_put(ring-&gt;vmid_wait);</div><div class='add'>+	ring-&gt;vmid_wait = dma_fence_get(*fence);</div><div class='ctx'> </div><div class='add'>+	/* This is the reference we return */</div><div class='add'>+	dma_fence_get(*fence);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -275,22 +251,27 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	unsigned vmhub = ring-&gt;vm_hub;</div><div class='del'>-	struct amdgpu_vmid_mgr *id_mgr = &amp;adev-&gt;vm_manager.id_mgr[vmhub];</div><div class='ctx'> 	uint64_t fence_context = adev-&gt;fence_context + ring-&gt;idx;</div><div class='ctx'> 	bool needs_flush = vm-&gt;use_cpu_for_update;</div><div class='ctx'> 	uint64_t updates = amdgpu_vm_tlb_seq(vm);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	*id = id_mgr-&gt;reserved;</div><div class='add'>+	*id = vm-&gt;reserved_vmid[vmhub];</div><div class='ctx'> 	if ((*id)-&gt;owner != vm-&gt;immediate.fence_context ||</div><div class='ctx'> 	    !amdgpu_vmid_compatible(*id, job) ||</div><div class='ctx'> 	    (*id)-&gt;flushed_updates &lt; updates ||</div><div class='ctx'> 	    !(*id)-&gt;last_flush ||</div><div class='ctx'> 	    ((*id)-&gt;last_flush-&gt;context != fence_context &amp;&amp;</div><div class='del'>-	     !dma_fence_is_signaled((*id)-&gt;last_flush))) {</div><div class='add'>+	     !dma_fence_is_signaled((*id)-&gt;last_flush)))</div><div class='add'>+		needs_flush = true;</div><div class='add'>+</div><div class='add'>+	if ((*id)-&gt;owner != vm-&gt;immediate.fence_context ||</div><div class='add'>+	    (!adev-&gt;vm_manager.concurrent_flush &amp;&amp; needs_flush)) {</div><div class='ctx'> 		struct dma_fence *tmp;</div><div class='ctx'> </div><div class='del'>-		/* Don't use per engine and per process VMID at the same time */</div><div class='add'>+		/* Don't use per engine and per process VMID at the</div><div class='add'>+		 * same time</div><div class='add'>+		 */</div><div class='ctx'> 		if (adev-&gt;vm_manager.concurrent_flush)</div><div class='ctx'> 			ring = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -302,13 +283,13 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,</div><div class='ctx'> 			*fence = dma_fence_get(tmp);</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		}</div><div class='del'>-		needs_flush = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Good we can use this VMID. Remember this submission as</div><div class='ctx'> 	* user of the VMID.</div><div class='ctx'> 	*/</div><div class='del'>-	r = amdgpu_sync_fence(&amp;(*id)-&gt;active, &amp;job-&gt;base.s_fence-&gt;finished);</div><div class='add'>+	r = amdgpu_sync_fence(&amp;(*id)-&gt;active, &amp;job-&gt;base.s_fence-&gt;finished,</div><div class='add'>+			      GFP_ATOMIC);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -324,15 +305,13 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,</div><div class='ctx'>  * @ring: ring we want to submit job to</div><div class='ctx'>  * @job: job who wants to use the VMID</div><div class='ctx'>  * @id: resulting VMID</div><div class='del'>- * @fence: fence to wait for if no id could be grabbed</div><div class='ctx'>  *</div><div class='ctx'>  * Try to reuse a VMID for this submission.</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,</div><div class='ctx'> 				 struct amdgpu_ring *ring,</div><div class='ctx'> 				 struct amdgpu_job *job,</div><div class='del'>-				 struct amdgpu_vmid **id,</div><div class='del'>-				 struct dma_fence **fence)</div><div class='add'>+				 struct amdgpu_vmid **id)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	unsigned vmhub = ring-&gt;vm_hub;</div><div class='hunk'>@@ -369,7 +348,8 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,</div><div class='ctx'> 		 * user of the VMID.</div><div class='ctx'> 		 */</div><div class='ctx'> 		r = amdgpu_sync_fence(&amp;(*id)-&gt;active,</div><div class='del'>-				      &amp;job-&gt;base.s_fence-&gt;finished);</div><div class='add'>+				      &amp;job-&gt;base.s_fence-&gt;finished,</div><div class='add'>+				      GFP_ATOMIC);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='hunk'>@@ -406,12 +386,12 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,</div><div class='ctx'> 	if (r || !idle)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='del'>-	if (vm-&gt;reserved_vmid[vmhub] || (enforce_isolation &amp;&amp; (vmhub == AMDGPU_GFXHUB(0)))) {</div><div class='add'>+	if (amdgpu_vmid_uses_reserved(vm, vmhub)) {</div><div class='ctx'> 		r = amdgpu_vmid_grab_reserved(vm, ring, job, &amp;id, fence);</div><div class='ctx'> 		if (r || !id)</div><div class='ctx'> 			goto error;</div><div class='ctx'> 	} else {</div><div class='del'>-		r = amdgpu_vmid_grab_used(vm, ring, job, &amp;id, fence);</div><div class='add'>+		r = amdgpu_vmid_grab_used(vm, ring, job, &amp;id);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -421,7 +401,8 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 			/* Remember this submission as user of the VMID */</div><div class='ctx'> 			r = amdgpu_sync_fence(&amp;id-&gt;active,</div><div class='del'>-					      &amp;job-&gt;base.s_fence-&gt;finished);</div><div class='add'>+					      &amp;job-&gt;base.s_fence-&gt;finished,</div><div class='add'>+					      GFP_ATOMIC);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -456,40 +437,73 @@ error:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,</div><div class='add'>+/*</div><div class='add'>+ * amdgpu_vmid_uses_reserved - check if a VM will use a reserved VMID</div><div class='add'>+ * @vm: the VM to check</div><div class='add'>+ * @vmhub: the VMHUB which will be used</div><div class='add'>+ *</div><div class='add'>+ * Returns: True if the VM will use a reserved VMID.</div><div class='add'>+ */</div><div class='add'>+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;reserved_vmid[vmhub];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * amdgpu_vmid_alloc_reserved - reserve a specific VMID for this vm</div><div class='add'>+ * @adev: amdgpu device structure</div><div class='add'>+ * @vm: the VM to reserve an ID for</div><div class='add'>+ * @vmhub: the VMHUB which should be used</div><div class='add'>+ *</div><div class='add'>+ * Mostly used to have a reserved VMID for debugging and SPM.</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 for success, -ENOENT if an ID is already reserved.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 			       unsigned vmhub)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vmid_mgr *id_mgr = &amp;adev-&gt;vm_manager.id_mgr[vmhub];</div><div class='add'>+	struct amdgpu_vmid *id;</div><div class='add'>+	int r = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;id_mgr-&gt;lock);</div><div class='del'>-</div><div class='del'>-	++id_mgr-&gt;reserved_use_count;</div><div class='del'>-	if (!id_mgr-&gt;reserved) {</div><div class='del'>-		struct amdgpu_vmid *id;</div><div class='del'>-</div><div class='del'>-		id = list_first_entry(&amp;id_mgr-&gt;ids_lru, struct amdgpu_vmid,</div><div class='del'>-				      list);</div><div class='del'>-		/* Remove from normal round robin handling */</div><div class='del'>-		list_del_init(&amp;id-&gt;list);</div><div class='del'>-		id_mgr-&gt;reserved = id;</div><div class='add'>+	if (vm-&gt;reserved_vmid[vmhub])</div><div class='add'>+		goto unlock;</div><div class='add'>+	if (id_mgr-&gt;reserved_vmid) {</div><div class='add'>+		r = -ENOENT;</div><div class='add'>+		goto unlock;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	/* Remove from normal round robin handling */</div><div class='add'>+	id = list_first_entry(&amp;id_mgr-&gt;ids_lru, struct amdgpu_vmid, list);</div><div class='add'>+	list_del_init(&amp;id-&gt;list);</div><div class='add'>+	vm-&gt;reserved_vmid[vmhub] = id;</div><div class='add'>+	id_mgr-&gt;reserved_vmid = true;</div><div class='ctx'> 	mutex_unlock(&amp;id_mgr-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;id_mgr-&gt;lock);</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,</div><div class='add'>+/*</div><div class='add'>+ * amdgpu_vmid_free_reserved - free up a reserved VMID again</div><div class='add'>+ * @adev: amdgpu device structure</div><div class='add'>+ * @vm: the VM with the reserved ID</div><div class='add'>+ * @vmhub: the VMHUB which should be used</div><div class='add'>+ */</div><div class='add'>+void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 			       unsigned vmhub)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vmid_mgr *id_mgr = &amp;adev-&gt;vm_manager.id_mgr[vmhub];</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;id_mgr-&gt;lock);</div><div class='del'>-	if (!--id_mgr-&gt;reserved_use_count) {</div><div class='del'>-		/* give the reserved ID back to normal round robin */</div><div class='del'>-		list_add(&amp;id_mgr-&gt;reserved-&gt;list, &amp;id_mgr-&gt;ids_lru);</div><div class='del'>-		id_mgr-&gt;reserved = NULL;</div><div class='add'>+	if (vm-&gt;reserved_vmid[vmhub]) {</div><div class='add'>+		list_add(&amp;vm-&gt;reserved_vmid[vmhub]-&gt;list,</div><div class='add'>+			&amp;id_mgr-&gt;ids_lru);</div><div class='add'>+		vm-&gt;reserved_vmid[vmhub] = NULL;</div><div class='add'>+		id_mgr-&gt;reserved_vmid = false;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> 	mutex_unlock(&amp;id_mgr-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -556,10 +570,17 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		mutex_init(&amp;id_mgr-&gt;lock);</div><div class='ctx'> 		INIT_LIST_HEAD(&amp;id_mgr-&gt;ids_lru);</div><div class='del'>-		id_mgr-&gt;reserved_use_count = 0;</div><div class='ctx'> </div><div class='del'>-		/* manage only VMIDs not used by KFD */</div><div class='del'>-		id_mgr-&gt;num_ids = adev-&gt;vm_manager.first_kfd_vmid;</div><div class='add'>+		/* for GC &lt;10, SDMA uses MMHUB so use first_kfd_vmid for both GC and MM */</div><div class='add'>+		if (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(10, 0, 0))</div><div class='add'>+			/* manage only VMIDs not used by KFD */</div><div class='add'>+			id_mgr-&gt;num_ids = adev-&gt;vm_manager.first_kfd_vmid;</div><div class='add'>+		else if (AMDGPU_IS_MMHUB0(i) ||</div><div class='add'>+			 AMDGPU_IS_MMHUB1(i))</div><div class='add'>+			id_mgr-&gt;num_ids = 16;</div><div class='add'>+		else</div><div class='add'>+			/* manage only VMIDs not used by KFD */</div><div class='add'>+			id_mgr-&gt;num_ids = adev-&gt;vm_manager.first_kfd_vmid;</div><div class='ctx'> </div><div class='ctx'> 		/* skip over VMID 0, since it is the system VM */</div><div class='ctx'> 		for (j = 1; j &lt; id_mgr-&gt;num_ids; ++j) {</div><div class='hunk'>@@ -568,10 +589,6 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)</div><div class='ctx'> 			list_add_tail(&amp;id_mgr-&gt;ids[j].list, &amp;id_mgr-&gt;ids_lru);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	/* alloc a default reserved vmid to enforce isolation */</div><div class='del'>-	if (enforce_isolation)</div><div class='del'>-		amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h<br/>index fa8c42c83d5d..b3649cd3af56 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h</a></div><div class='hunk'>@@ -67,8 +67,7 @@ struct amdgpu_vmid_mgr {</div><div class='ctx'> 	unsigned		num_ids;</div><div class='ctx'> 	struct list_head	ids_lru;</div><div class='ctx'> 	struct amdgpu_vmid	ids[AMDGPU_NUM_VMID];</div><div class='del'>-	struct amdgpu_vmid	*reserved;</div><div class='del'>-	unsigned int		reserved_use_count;</div><div class='add'>+	bool			reserved_vmid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_pasid_alloc(unsigned int bits);</div><div class='hunk'>@@ -78,10 +77,11 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv,</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,</div><div class='ctx'> 			       struct amdgpu_vmid *id);</div><div class='del'>-int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,</div><div class='del'>-				unsigned vmhub);</div><div class='del'>-void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,</div><div class='del'>-				unsigned vmhub);</div><div class='add'>+bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub);</div><div class='add'>+int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='add'>+			       unsigned vmhub);</div><div class='add'>+void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='add'>+			       unsigned vmhub);</div><div class='ctx'> int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,</div><div class='ctx'> 		     struct amdgpu_job *job, struct dma_fence **fence);</div><div class='ctx'> void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c<br/>index f3b0aaf3ebc6..a6419246e9c2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c</a></div><div class='hunk'>@@ -25,6 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_ih.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_ih_ring_init - initialize the IH state</div><div class='hunk'>@@ -217,7 +218,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)</div><div class='ctx'> </div><div class='ctx'> restart_ih:</div><div class='ctx'> 	count  = AMDGPU_IH_MAX_NUM_IVS;</div><div class='del'>-	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih-&gt;rptr, wptr);</div><div class='add'>+	dev_dbg(adev-&gt;dev, "%s: rptr %d, wptr %d\n", __func__, ih-&gt;rptr, wptr);</div><div class='ctx'> </div><div class='ctx'> 	/* Order reading of wptr vs. reading of IH ring data */</div><div class='ctx'> 	rmb();</div><div class='hunk'>@@ -227,13 +228,23 @@ restart_ih:</div><div class='ctx'> 		ih-&gt;rptr &amp;= ih-&gt;ptr_mask;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_ih_set_rptr(adev, ih);</div><div class='add'>+	if (!ih-&gt;overflow)</div><div class='add'>+		amdgpu_ih_set_rptr(adev, ih);</div><div class='add'>+</div><div class='ctx'> 	wake_up_all(&amp;ih-&gt;wait_process);</div><div class='ctx'> </div><div class='ctx'> 	/* make sure wptr hasn't changed while processing */</div><div class='ctx'> 	wptr = amdgpu_ih_get_wptr(adev, ih);</div><div class='ctx'> 	if (wptr != ih-&gt;rptr)</div><div class='del'>-		goto restart_ih;</div><div class='add'>+		if (!ih-&gt;overflow)</div><div class='add'>+			goto restart_ih;</div><div class='add'>+</div><div class='add'>+	if (ih-&gt;overflow)</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			WARN_ONCE(!amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='add'>+				   &amp;adev-&gt;virt.flr_work),</div><div class='add'>+				  "Failed to queue work! at %s",</div><div class='add'>+				  __func__);</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='hunk'>@@ -298,3 +309,9 @@ uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,</div><div class='ctx'> 	dw2 = le32_to_cpu(ih-&gt;ring[ring_index + 2]);</div><div class='ctx'> 	return dw1 | ((u64)(dw2 &amp; 0xffff) &lt;&lt; 32);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)</div><div class='add'>+{</div><div class='add'>+	return ih == &amp;adev-&gt;irq.ih ? "ih" : ih == &amp;adev-&gt;irq.ih_soft ? "sw ih" :</div><div class='add'>+	       ih == &amp;adev-&gt;irq.ih1 ? "ih1" : ih == &amp;adev-&gt;irq.ih2 ? "ih2" : "unknown";</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h<br/>index 508f02eb0cf8..f58b6be7fccc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h</a></div><div class='hunk'>@@ -56,14 +56,14 @@ struct amdgpu_ih_ring {</div><div class='ctx'> 	bool			use_bus_addr;</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_bo	*ring_obj;</div><div class='del'>-	volatile uint32_t	*ring;</div><div class='add'>+	uint32_t		*ring;</div><div class='ctx'> 	uint64_t		gpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	uint64_t		wptr_addr;</div><div class='del'>-	volatile uint32_t	*wptr_cpu;</div><div class='add'>+	uint32_t		*wptr_cpu;</div><div class='ctx'> </div><div class='ctx'> 	uint64_t		rptr_addr;</div><div class='del'>-	volatile uint32_t	*rptr_cpu;</div><div class='add'>+	uint32_t		*rptr_cpu;</div><div class='ctx'> </div><div class='ctx'> 	bool                    enabled;</div><div class='ctx'> 	unsigned		rptr;</div><div class='hunk'>@@ -72,12 +72,16 @@ struct amdgpu_ih_ring {</div><div class='ctx'> 	/* For waiting on IH processing at checkpoint. */</div><div class='ctx'> 	wait_queue_head_t wait_process;</div><div class='ctx'> 	uint64_t		processed_timestamp;</div><div class='add'>+	bool overflow;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* return true if time stamp t2 is after t1 with 48bit wrap around */</div><div class='ctx'> #define amdgpu_ih_ts_after(t1, t2) \</div><div class='ctx'> 		(((int64_t)((t2) &lt;&lt; 16) - (int64_t)((t1) &lt;&lt; 16)) &gt; 0LL)</div><div class='ctx'> </div><div class='add'>+#define amdgpu_ih_ts_after_or_equal(t1, t2) \</div><div class='add'>+		(((int64_t)((t2) &lt;&lt; 16) - (int64_t)((t1) &lt;&lt; 16)) &gt;= 0LL)</div><div class='add'>+</div><div class='ctx'> /* provided by the ih block */</div><div class='ctx'> struct amdgpu_ih_funcs {</div><div class='ctx'> 	/* ring read/write ptr handling, called from interrupt context */</div><div class='hunk'>@@ -110,4 +114,5 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,</div><div class='ctx'> 				struct amdgpu_iv_entry *entry);</div><div class='ctx'> uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,</div><div class='ctx'> 				       signed int offset);</div><div class='add'>+const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c<br/>new file mode 100644<br/>index 000000000000..99e1cf4fc955<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c</a></div><div class='hunk'>@@ -0,0 +1,96 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_ip.h"</div><div class='add'>+</div><div class='add'>+static int8_t amdgpu_logical_to_dev_inst(struct amdgpu_device *adev,</div><div class='add'>+					 enum amd_hw_ip_block_type block,</div><div class='add'>+					 int8_t inst)</div><div class='add'>+{</div><div class='add'>+	int8_t dev_inst;</div><div class='add'>+</div><div class='add'>+	switch (block) {</div><div class='add'>+	case GC_HWIP:</div><div class='add'>+	case SDMA0_HWIP:</div><div class='add'>+	/* Both JPEG and VCN as JPEG is only alias of VCN */</div><div class='add'>+	case VCN_HWIP:</div><div class='add'>+		dev_inst = adev-&gt;ip_map.dev_inst[block][inst];</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		/* For rest of the IPs, no look up required.</div><div class='add'>+		 * Assume 'logical instance == physical instance' for all configs. */</div><div class='add'>+		dev_inst = inst;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dev_inst;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t amdgpu_logical_to_dev_mask(struct amdgpu_device *adev,</div><div class='add'>+					   enum amd_hw_ip_block_type block,</div><div class='add'>+					   uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	uint32_t dev_mask = 0;</div><div class='add'>+	int8_t log_inst, dev_inst;</div><div class='add'>+</div><div class='add'>+	while (mask) {</div><div class='add'>+		log_inst = ffs(mask) - 1;</div><div class='add'>+		dev_inst = amdgpu_logical_to_dev_inst(adev, block, log_inst);</div><div class='add'>+		dev_mask |= (1 &lt;&lt; dev_inst);</div><div class='add'>+		mask &amp;= ~(1 &lt;&lt; log_inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dev_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_populate_ip_map(struct amdgpu_device *adev,</div><div class='add'>+				   enum amd_hw_ip_block_type ip_block,</div><div class='add'>+				   uint32_t inst_mask)</div><div class='add'>+{</div><div class='add'>+	int l = 0, i;</div><div class='add'>+</div><div class='add'>+	while (inst_mask) {</div><div class='add'>+		i = ffs(inst_mask) - 1;</div><div class='add'>+		adev-&gt;ip_map.dev_inst[ip_block][l++] = i;</div><div class='add'>+		inst_mask &amp;= ~(1 &lt;&lt; i);</div><div class='add'>+	}</div><div class='add'>+	for (; l &lt; HWIP_MAX_INSTANCE; l++)</div><div class='add'>+		adev-&gt;ip_map.dev_inst[ip_block][l] = -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ip_map_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 ip_map[][2] = {</div><div class='add'>+		{ GC_HWIP, adev-&gt;gfx.xcc_mask },</div><div class='add'>+		{ SDMA0_HWIP, adev-&gt;sdma.sdma_mask },</div><div class='add'>+		{ VCN_HWIP, adev-&gt;vcn.inst_mask },</div><div class='add'>+	};</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(ip_map); ++i)</div><div class='add'>+		amdgpu_populate_ip_map(adev, ip_map[i][0], ip_map[i][1]);</div><div class='add'>+</div><div class='add'>+	adev-&gt;ip_map.logical_to_dev_inst = amdgpu_logical_to_dev_inst;</div><div class='add'>+	adev-&gt;ip_map.logical_to_dev_mask = amdgpu_logical_to_dev_mask;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h<br/>new file mode 100644<br/>index 000000000000..2490fd322aec<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_IP_H__</div><div class='add'>+#define __AMDGPU_IP_H__</div><div class='add'>+</div><div class='add'>+void amdgpu_ip_map_init(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+#endif /* __AMDGPU_IP_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c<br/>index 7e6d09730e6d..8112ffc85995 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c</a></div><div class='hunk'>@@ -142,8 +142,9 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)</div><div class='ctx'> 				r = src-&gt;funcs-&gt;set(adev, src, k,</div><div class='ctx'> 						    AMDGPU_IRQ_STATE_DISABLE);</div><div class='ctx'> 				if (r)</div><div class='del'>-					DRM_ERROR("error disabling interrupt (%d)\n",</div><div class='del'>-						  r);</div><div class='add'>+					dev_err(adev-&gt;dev,</div><div class='add'>+						"error disabling interrupt (%d)\n",</div><div class='add'>+						r);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -242,7 +243,7 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_restore_msix(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_restore_msix(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	u16 ctrl;</div><div class='ctx'> </div><div class='hunk'>@@ -279,7 +280,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.msi_enabled = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_msi_ok(adev))</div><div class='del'>-		flags = PCI_IRQ_LEGACY;</div><div class='add'>+		flags = PCI_IRQ_INTX;</div><div class='ctx'> 	else</div><div class='ctx'> 		flags = PCI_IRQ_ALL_TYPES;</div><div class='ctx'> </div><div class='hunk'>@@ -315,7 +316,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.irq = irq;</div><div class='ctx'> 	adev_to_drm(adev)-&gt;max_vblank_count = 0x00ffffff;</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG("amdgpu: irq initialized.\n");</div><div class='add'>+	dev_dbg(adev-&gt;dev, "amdgpu: irq initialized.\n");</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> free_vectors:</div><div class='hunk'>@@ -445,6 +446,14 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	entry.ih = ih;</div><div class='ctx'> 	entry.iv_entry = (const uint32_t *)&amp;ih-&gt;ring[ring_index];</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * timestamp is not supported on some legacy SOCs (cik, cz, iceland,</div><div class='add'>+	 * si and tonga), so initialize timestamp and timestamp_src to 0</div><div class='add'>+	 */</div><div class='add'>+	entry.timestamp = 0;</div><div class='add'>+	entry.timestamp_src = 0;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ih_decode_iv(adev, &amp;entry);</div><div class='ctx'> </div><div class='ctx'> 	trace_amdgpu_iv(ih - &amp;adev-&gt;irq.ih, &amp;entry);</div><div class='hunk'>@@ -453,28 +462,32 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,</div><div class='ctx'> 	src_id = entry.src_id;</div><div class='ctx'> </div><div class='ctx'> 	if (client_id &gt;= AMDGPU_IRQ_CLIENTID_MAX) {</div><div class='del'>-		DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Invalid client_id in IV: %d\n", client_id);</div><div class='ctx'> </div><div class='ctx'> 	} else	if (src_id &gt;= AMDGPU_MAX_IRQ_SRC_ID) {</div><div class='del'>-		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Invalid src_id in IV: %d\n", src_id);</div><div class='ctx'> </div><div class='del'>-	} else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &amp;&amp;</div><div class='add'>+	} else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) ||</div><div class='add'>+		    (client_id == SOC15_IH_CLIENTID_ISP)) &amp;&amp;</div><div class='ctx'> 		   adev-&gt;irq.virq[src_id]) {</div><div class='ctx'> 		generic_handle_domain_irq(adev-&gt;irq.domain, src_id);</div><div class='ctx'> </div><div class='ctx'> 	} else if (!adev-&gt;irq.client[client_id].sources) {</div><div class='del'>-		DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",</div><div class='del'>-			  client_id, src_id);</div><div class='add'>+		dev_dbg(adev-&gt;dev,</div><div class='add'>+			"Unregistered interrupt client_id: %d src_id: %d\n",</div><div class='add'>+			client_id, src_id);</div><div class='ctx'> </div><div class='ctx'> 	} else if ((src = adev-&gt;irq.client[client_id].sources[src_id])) {</div><div class='ctx'> 		r = src-&gt;funcs-&gt;process(adev, src, &amp;entry);</div><div class='ctx'> 		if (r &lt; 0)</div><div class='del'>-			DRM_ERROR("error processing interrupt (%d)\n", r);</div><div class='add'>+			dev_err(adev-&gt;dev, "error processing interrupt (%d)\n",</div><div class='add'>+				r);</div><div class='ctx'> 		else if (r)</div><div class='ctx'> 			handled = true;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",</div><div class='add'>+		dev_dbg(adev-&gt;dev,</div><div class='add'>+			"Unregistered interrupt src_id: %d of client_id:%d\n",</div><div class='ctx'> 			src_id, client_id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -610,6 +623,10 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,</div><div class='ctx'> int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,</div><div class='ctx'> 		   unsigned int type)</div><div class='ctx'> {</div><div class='add'>+	/* When the threshold is reached,the interrupt source may not be enabled.return -EINVAL */</div><div class='add'>+	if (amdgpu_ras_is_rma(adev) &amp;&amp; !amdgpu_irq_enabled(adev, src, type))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (!adev-&gt;irq.installed)</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> </div><div class='hunk'>@@ -716,10 +733,10 @@ static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_irq_add_domain(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	adev-&gt;irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,</div><div class='del'>-						 &amp;amdgpu_hw_irqdomain_ops, adev);</div><div class='add'>+	adev-&gt;irq.domain = irq_domain_create_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,</div><div class='add'>+						    &amp;amdgpu_hw_irqdomain_ops, adev);</div><div class='ctx'> 	if (!adev-&gt;irq.domain) {</div><div class='del'>-		DRM_ERROR("GPU irq add domain failed\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "GPU irq add domain failed\n");</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h<br/>index 04c0b4fa17a4..9f0417456abd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h</a></div><div class='hunk'>@@ -146,5 +146,6 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_irq_add_domain(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_irq_remove_domain(struct amdgpu_device *adev);</div><div class='ctx'> unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);</div><div class='add'>+void amdgpu_restore_msix(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c<br/>new file mode 100644<br/>index 000000000000..37270c4dab8d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c</a></div><div class='hunk'>@@ -0,0 +1,345 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/mfd/core.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_isp.h"</div><div class='add'>+#include "isp_v4_1_0.h"</div><div class='add'>+#include "isp_v4_1_1.h"</div><div class='add'>+</div><div class='add'>+#define ISP_MC_ADDR_ALIGN (1024 * 32)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * isp_hw_init - start and test isp block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static int isp_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_isp *isp = &amp;adev-&gt;isp;</div><div class='add'>+</div><div class='add'>+	if (isp-&gt;funcs-&gt;hw_init != NULL)</div><div class='add'>+		return isp-&gt;funcs-&gt;hw_init(isp);</div><div class='add'>+</div><div class='add'>+	return -ENODEV;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * isp_hw_fini - stop the hardware block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static int isp_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_isp *isp = &amp;ip_block-&gt;adev-&gt;isp;</div><div class='add'>+</div><div class='add'>+	if (isp-&gt;funcs-&gt;hw_fini != NULL)</div><div class='add'>+		return isp-&gt;funcs-&gt;hw_fini(isp);</div><div class='add'>+</div><div class='add'>+	return -ENODEV;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_load_fw_by_psp(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct common_firmware_header *hdr;</div><div class='add'>+	char ucode_prefix[10];</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	/* get isp fw binary name and path */</div><div class='add'>+	amdgpu_ucode_ip_version_decode(adev, ISP_HWIP, ucode_prefix,</div><div class='add'>+				       sizeof(ucode_prefix));</div><div class='add'>+</div><div class='add'>+	/* read isp fw */</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;isp.fw, AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+				"amdgpu/%s.bin", ucode_prefix);</div><div class='add'>+	if (r) {</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;isp.fw);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;isp.fw-&gt;data;</div><div class='add'>+</div><div class='add'>+	adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_ISP].ucode_id =</div><div class='add'>+		AMDGPU_UCODE_ID_ISP;</div><div class='add'>+	adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_ISP].fw = adev-&gt;isp.fw;</div><div class='add'>+</div><div class='add'>+	adev-&gt;firmware.fw_size +=</div><div class='add'>+		ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes), PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_isp *isp = &amp;adev-&gt;isp;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(4, 1, 0):</div><div class='add'>+		isp_v4_1_0_set_isp_funcs(isp);</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(4, 1, 1):</div><div class='add'>+		isp_v4_1_1_set_isp_funcs(isp);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;adev = adev;</div><div class='add'>+	isp-&gt;parent = adev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (isp_load_fw_by_psp(adev)) {</div><div class='add'>+		DRM_DEBUG_DRIVER("%s: isp fw load failed\n", __func__);</div><div class='add'>+		return -ENOENT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool isp_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+				     enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+				     enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int is_valid_isp_device(struct device *isp_parent, struct device *amdgpu_dev)</div><div class='add'>+{</div><div class='add'>+	if (isp_parent != amdgpu_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * isp_user_buffer_alloc - create user buffer object (BO) for isp</div><div class='add'>+ *</div><div class='add'>+ * @dev: isp device handle</div><div class='add'>+ * @dmabuf: DMABUF handle for isp buffer allocated in system memory</div><div class='add'>+ * @buf_obj: GPU buffer object handle to initialize</div><div class='add'>+ * @buf_addr: GPU addr of the pinned BO to initialize</div><div class='add'>+ *</div><div class='add'>+ * Imports isp DMABUF to allocate and pin a user BO for isp internal use. It does</div><div class='add'>+ * GART alloc to generate GPU addr for BO to make it accessible through the</div><div class='add'>+ * GART aperture for ISP HW.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device external to drm device</div><div class='add'>+ * to create and access the isp user BO.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int isp_user_buffer_alloc(struct device *dev, void *dmabuf,</div><div class='add'>+			  void **buf_obj, u64 *buf_addr)</div><div class='add'>+{</div><div class='add'>+	struct platform_device *ispdev = to_platform_device(dev);</div><div class='add'>+	const struct isp_platform_data *isp_pdata;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	struct mfd_cell *mfd_cell;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	u64 gpu_addr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!ispdev))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!buf_obj))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!buf_addr))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mfd_cell = &amp;ispdev-&gt;mfd_cell[0];</div><div class='add'>+	if (!mfd_cell)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	isp_pdata = mfd_cell-&gt;platform_data;</div><div class='add'>+	adev = isp_pdata-&gt;adev;</div><div class='add'>+</div><div class='add'>+	ret = is_valid_isp_device(ispdev-&gt;dev.parent, adev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_create_isp_user(adev, dmabuf,</div><div class='add'>+					AMDGPU_GEM_DOMAIN_GTT, &amp;bo, &amp;gpu_addr);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "failed to alloc gart user buffer (%d)", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*buf_obj = (void *)bo;</div><div class='add'>+	*buf_addr = gpu_addr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(isp_user_buffer_alloc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * isp_user_buffer_free - free isp user buffer object (BO)</div><div class='add'>+ *</div><div class='add'>+ * @buf_obj: amdgpu isp user BO to free</div><div class='add'>+ *</div><div class='add'>+ * unpin and unref BO for isp internal use.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device</div><div class='add'>+ * external to drm device to free the isp user BO.</div><div class='add'>+ */</div><div class='add'>+void isp_user_buffer_free(void *buf_obj)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_isp_user(buf_obj);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(isp_user_buffer_free);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * isp_kernel_buffer_alloc - create kernel buffer object (BO) for isp</div><div class='add'>+ *</div><div class='add'>+ * @dev: isp device handle</div><div class='add'>+ * @size: size for the new BO</div><div class='add'>+ * @buf_obj: GPU BO handle to initialize</div><div class='add'>+ * @gpu_addr: GPU addr of the pinned BO</div><div class='add'>+ * @cpu_addr: CPU address mapping of BO</div><div class='add'>+ *</div><div class='add'>+ * Allocates and pins a kernel BO for internal isp firmware use.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device</div><div class='add'>+ * external to drm device to create and access the kernel BO.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int isp_kernel_buffer_alloc(struct device *dev, u64 size,</div><div class='add'>+			    void **buf_obj, u64 *gpu_addr, void **cpu_addr)</div><div class='add'>+{</div><div class='add'>+	struct platform_device *ispdev = to_platform_device(dev);</div><div class='add'>+	struct amdgpu_bo **bo = (struct amdgpu_bo **)buf_obj;</div><div class='add'>+	const struct isp_platform_data *isp_pdata;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	struct mfd_cell *mfd_cell;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!ispdev))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!buf_obj))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!gpu_addr))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!cpu_addr))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mfd_cell = &amp;ispdev-&gt;mfd_cell[0];</div><div class='add'>+	if (!mfd_cell)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	isp_pdata = mfd_cell-&gt;platform_data;</div><div class='add'>+	adev = isp_pdata-&gt;adev;</div><div class='add'>+</div><div class='add'>+	ret = is_valid_isp_device(ispdev-&gt;dev.parent, adev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Ensure *bo is NULL so a new BO will be created */</div><div class='add'>+	*bo = NULL;</div><div class='add'>+	ret = amdgpu_bo_create_kernel(adev,</div><div class='add'>+				      size,</div><div class='add'>+				      ISP_MC_ADDR_ALIGN,</div><div class='add'>+				      AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				      bo,</div><div class='add'>+				      gpu_addr,</div><div class='add'>+				      cpu_addr);</div><div class='add'>+	if (!cpu_addr || ret) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "failed to alloc gart kernel buffer (%d)", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(isp_kernel_buffer_alloc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * isp_kernel_buffer_free - free isp kernel buffer object (BO)</div><div class='add'>+ *</div><div class='add'>+ * @buf_obj: amdgpu isp user BO to free</div><div class='add'>+ * @gpu_addr: GPU addr of isp kernel BO</div><div class='add'>+ * @cpu_addr: CPU addr of isp kernel BO</div><div class='add'>+ *</div><div class='add'>+ * unmaps and unpin a isp kernel BO.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device</div><div class='add'>+ * external to drm device to free the kernel BO.</div><div class='add'>+ */</div><div class='add'>+void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo **bo = (struct amdgpu_bo **)buf_obj;</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(bo, gpu_addr, cpu_addr);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(isp_kernel_buffer_free);</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs isp_ip_funcs = {</div><div class='add'>+	.name = "isp_ip",</div><div class='add'>+	.early_init = isp_early_init,</div><div class='add'>+	.hw_init = isp_hw_init,</div><div class='add'>+	.hw_fini = isp_hw_fini,</div><div class='add'>+	.is_idle = isp_is_idle,</div><div class='add'>+	.set_clockgating_state = isp_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = isp_set_powergating_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version isp_v4_1_0_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_ISP,</div><div class='add'>+	.major = 4,</div><div class='add'>+	.minor = 1,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;isp_ip_funcs,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version isp_v4_1_1_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_ISP,</div><div class='add'>+	.major = 4,</div><div class='add'>+	.minor = 1,</div><div class='add'>+	.rev = 1,</div><div class='add'>+	.funcs = &amp;isp_ip_funcs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h<br/>new file mode 100644<br/>index 000000000000..d6f4ffa4c97c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h</a></div><div class='hunk'>@@ -0,0 +1,60 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_ISP_H__</div><div class='add'>+#define __AMDGPU_ISP_H__</div><div class='add'>+</div><div class='add'>+#include &lt;drm/amd/isp.h&gt;</div><div class='add'>+#include &lt;linux/pm_domain.h&gt;</div><div class='add'>+</div><div class='add'>+#define ISP_REGS_OFFSET_END 0x629A4</div><div class='add'>+</div><div class='add'>+struct amdgpu_isp;</div><div class='add'>+</div><div class='add'>+struct isp_funcs {</div><div class='add'>+	int (*hw_init)(struct amdgpu_isp *isp);</div><div class='add'>+	int (*hw_fini)(struct amdgpu_isp *isp);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_isp {</div><div class='add'>+	struct device *parent;</div><div class='add'>+	struct amdgpu_device	*adev;</div><div class='add'>+	const struct isp_funcs	*funcs;</div><div class='add'>+	struct mfd_cell *isp_cell;</div><div class='add'>+	struct resource *isp_res;</div><div class='add'>+	struct resource *isp_i2c_res;</div><div class='add'>+	struct resource *isp_gpio_res;</div><div class='add'>+	struct isp_platform_data *isp_pdata;</div><div class='add'>+	unsigned int harvest_config;</div><div class='add'>+	const struct firmware	*fw;</div><div class='add'>+	struct generic_pm_domain ispgpd;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_ip_block_version isp_v4_1_0_ip_block;</div><div class='add'>+extern const struct amdgpu_ip_block_version isp_v4_1_1_ip_block;</div><div class='add'>+</div><div class='add'>+#endif /* __AMDGPU_ISP_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c<br/>index 4b3000c21ef2..0a0dcbf0798d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_job.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_job.c</a></div><div class='hunk'>@@ -30,43 +30,121 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_trace.h"</div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='add'>+#include "amdgpu_dev_coredump.h"</div><div class='add'>+#include "amdgpu_xgmi.h"</div><div class='add'>+</div><div class='add'>+static void amdgpu_job_do_core_dump(struct amdgpu_device *adev,</div><div class='add'>+				    struct amdgpu_job *job)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "Dumping IP State\n");</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++)</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;dump_ip_state)</div><div class='add'>+			adev-&gt;ip_blocks[i].version-&gt;funcs</div><div class='add'>+				-&gt;dump_ip_state((void *)&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+	dev_info(adev-&gt;dev, "Dumping IP State Completed\n");</div><div class='add'>+</div><div class='add'>+	amdgpu_coredump(adev, true, false, job);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_job_core_dump(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_job *job)</div><div class='add'>+{</div><div class='add'>+	struct list_head device_list, *device_list_handle =  NULL;</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	struct amdgpu_hive_info *hive = NULL;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (hive)</div><div class='add'>+		mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+	/*</div><div class='add'>+	 * Reuse the logic in amdgpu_device_gpu_recover() to build list of</div><div class='add'>+	 * devices for code dump</div><div class='add'>+	 */</div><div class='add'>+	INIT_LIST_HEAD(&amp;device_list);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) &amp;&amp; hive) {</div><div class='add'>+		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head)</div><div class='add'>+			list_add_tail(&amp;tmp_adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+		if (!list_is_first(&amp;adev-&gt;reset_list, &amp;device_list))</div><div class='add'>+			list_rotate_to_front(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+		device_list_handle = &amp;device_list;</div><div class='add'>+	} else {</div><div class='add'>+		list_add_tail(&amp;adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+		device_list_handle = &amp;device_list;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Do the coredump for each device */</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list_handle, reset_list)</div><div class='add'>+		amdgpu_job_do_core_dump(tmp_adev, job);</div><div class='add'>+</div><div class='add'>+	if (hive) {</div><div class='add'>+		mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = to_amdgpu_ring(s_job-&gt;sched);</div><div class='ctx'> 	struct amdgpu_job *job = to_amdgpu_job(s_job);</div><div class='del'>-	struct amdgpu_task_info *ti;</div><div class='add'>+	struct drm_wedge_task_info *info = NULL;</div><div class='add'>+	struct amdgpu_task_info *ti = NULL;</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	int idx;</div><div class='del'>-	int r;</div><div class='add'>+	int idx, r;</div><div class='ctx'> </div><div class='ctx'> 	if (!drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='del'>-		DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",</div><div class='add'>+		dev_info(adev-&gt;dev, "%s - device unplugged skipping recovery on scheduler:%s",</div><div class='ctx'> 			 __func__, s_job-&gt;sched-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 		/* Effectively the job is aborted as the device is gone */</div><div class='ctx'> 		return DRM_GPU_SCHED_STAT_ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-	adev-&gt;job_hang = true;</div><div class='add'>+	/*</div><div class='add'>+	 * Do the coredump immediately after a job timeout to get a very</div><div class='add'>+	 * close dump/snapshot/representation of GPU's current error status</div><div class='add'>+	 * Skip it for SRIOV, since VF FLR will be triggered by host driver</div><div class='add'>+	 * before job timeout</div><div class='add'>+	 */</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_job_core_dump(adev, job);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_gpu_recovery &amp;&amp;</div><div class='add'>+	    amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_SOFT_RESET) &amp;&amp;</div><div class='ctx'> 	    amdgpu_ring_soft_recovery(ring, job-&gt;vmid, s_job-&gt;s_fence-&gt;parent)) {</div><div class='del'>-		DRM_ERROR("ring %s timeout, but soft recovered\n",</div><div class='del'>-			  s_job-&gt;sched-&gt;name);</div><div class='add'>+		dev_err(adev-&gt;dev, "ring %s timeout, but soft recovered\n",</div><div class='add'>+			s_job-&gt;sched-&gt;name);</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",</div><div class='del'>-		   job-&gt;base.sched-&gt;name, atomic_read(&amp;ring-&gt;fence_drv.last_seq),</div><div class='del'>-		   ring-&gt;fence_drv.sync_seq);</div><div class='add'>+	dev_err(adev-&gt;dev, "ring %s timeout, signaled seq=%u, emitted seq=%u\n",</div><div class='add'>+		job-&gt;base.sched-&gt;name, atomic_read(&amp;ring-&gt;fence_drv.last_seq),</div><div class='add'>+		ring-&gt;fence_drv.sync_seq);</div><div class='ctx'> </div><div class='ctx'> 	ti = amdgpu_vm_get_task_info_pasid(ring-&gt;adev, job-&gt;pasid);</div><div class='ctx'> 	if (ti) {</div><div class='del'>-		DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",</div><div class='del'>-			  ti-&gt;process_name, ti-&gt;tgid, ti-&gt;task_name, ti-&gt;pid);</div><div class='del'>-		amdgpu_vm_put_task_info(ti);</div><div class='add'>+		amdgpu_vm_print_task_info(adev, ti);</div><div class='add'>+		info = &amp;ti-&gt;task;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* attempt a per ring reset */</div><div class='add'>+	if (amdgpu_gpu_recovery &amp;&amp;</div><div class='add'>+	    amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) &amp;&amp;</div><div class='add'>+	    ring-&gt;funcs-&gt;reset) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Starting %s ring reset\n",</div><div class='add'>+			s_job-&gt;sched-&gt;name);</div><div class='add'>+		r = amdgpu_ring_reset(ring, job-&gt;vmid, job-&gt;hw_fence);</div><div class='add'>+		if (!r) {</div><div class='add'>+			atomic_inc(&amp;ring-&gt;adev-&gt;gpu_reset_counter);</div><div class='add'>+			dev_err(adev-&gt;dev, "Ring %s reset succeeded\n",</div><div class='add'>+				ring-&gt;sched.name);</div><div class='add'>+			drm_dev_wedged_event(adev_to_drm(adev),</div><div class='add'>+					     DRM_WEDGE_RECOVERY_NONE, info);</div><div class='add'>+			goto exit;</div><div class='add'>+		}</div><div class='add'>+		dev_err(adev-&gt;dev, "Ring %s reset failed\n", ring-&gt;sched.name);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dma_fence_set_error(&amp;s_job-&gt;s_fence-&gt;finished, -ETIME);</div><div class='hunk'>@@ -77,11 +155,18 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)</div><div class='ctx'> </div><div class='ctx'> 		reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 		reset_context.reset_req_dev = adev;</div><div class='add'>+		reset_context.src = AMDGPU_RESET_SRC_JOB;</div><div class='ctx'> 		clear_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='add'>+		/*</div><div class='add'>+		 * To avoid an unnecessary extra coredump, as we have already</div><div class='add'>+		 * got the very close representation of GPU's error status</div><div class='add'>+		 */</div><div class='add'>+		set_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context.flags);</div><div class='add'>+</div><div class='ctx'> 		r = amdgpu_device_gpu_recover(ring-&gt;adev, job, &amp;reset_context);</div><div class='ctx'> 		if (r)</div><div class='del'>-			DRM_ERROR("GPU Recovery Failed: %d\n", r);</div><div class='add'>+			dev_err(adev-&gt;dev, "GPU Recovery Failed: %d\n", r);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		drm_sched_suspend_timeout(&amp;ring-&gt;sched);</div><div class='ctx'> 		if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -89,15 +174,19 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> exit:</div><div class='del'>-	adev-&gt;job_hang = false;</div><div class='add'>+	amdgpu_vm_put_task_info(ti);</div><div class='ctx'> 	drm_dev_exit(idx);</div><div class='del'>-	return DRM_GPU_SCHED_STAT_NOMINAL;</div><div class='add'>+	return DRM_GPU_SCHED_STAT_RESET;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		     struct drm_sched_entity *entity, void *owner,</div><div class='del'>-		     unsigned int num_ibs, struct amdgpu_job **job)</div><div class='add'>+		     unsigned int num_ibs, struct amdgpu_job **job,</div><div class='add'>+		     u64 drm_client_id)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_fence *af;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='ctx'> 	if (num_ibs == 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -105,11 +194,20 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	if (!*job)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Initialize the scheduler to at least some ring so that we always</div><div class='del'>-	 * have a pointer to adev.</div><div class='del'>-	 */</div><div class='del'>-	(*job)-&gt;base.sched = &amp;adev-&gt;rings[0]-&gt;sched;</div><div class='add'>+	af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);</div><div class='add'>+	if (!af) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto err_job;</div><div class='add'>+	}</div><div class='add'>+	(*job)-&gt;hw_fence = af;</div><div class='add'>+</div><div class='add'>+	af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);</div><div class='add'>+	if (!af) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto err_fence;</div><div class='add'>+	}</div><div class='add'>+	(*job)-&gt;hw_vm_fence = af;</div><div class='add'>+</div><div class='ctx'> 	(*job)-&gt;vm = vm;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_create(&amp;(*job)-&gt;explicit_sync);</div><div class='hunk'>@@ -119,17 +217,27 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	if (!entity)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return drm_sched_job_init(&amp;(*job)-&gt;base, entity, 1, owner);</div><div class='add'>+	return drm_sched_job_init(&amp;(*job)-&gt;base, entity, 1, owner,</div><div class='add'>+				  drm_client_id);</div><div class='add'>+</div><div class='add'>+err_fence:</div><div class='add'>+	kfree((*job)-&gt;hw_fence);</div><div class='add'>+err_job:</div><div class='add'>+	kfree(*job);</div><div class='add'>+	*job = NULL;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,</div><div class='ctx'> 			     struct drm_sched_entity *entity, void *owner,</div><div class='ctx'> 			     size_t size, enum amdgpu_ib_pool_type pool_type,</div><div class='del'>-			     struct amdgpu_job **job)</div><div class='add'>+			     struct amdgpu_job **job, u64 k_job_id)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job);</div><div class='add'>+	r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job,</div><div class='add'>+			     k_job_id);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -138,7 +246,10 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		if (entity)</div><div class='ctx'> 			drm_sched_job_cleanup(&amp;(*job)-&gt;base);</div><div class='add'>+		kfree((*job)-&gt;hw_vm_fence);</div><div class='add'>+		kfree((*job)-&gt;hw_fence);</div><div class='ctx'> 		kfree(*job);</div><div class='add'>+		*job = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -163,20 +274,19 @@ void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,</div><div class='ctx'> </div><div class='ctx'> void amdgpu_job_free_resources(struct amdgpu_job *job)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = to_amdgpu_ring(job-&gt;base.sched);</div><div class='ctx'> 	struct dma_fence *f;</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> </div><div class='del'>-	/* Check if any fences where initialized */</div><div class='add'>+	/* Check if any fences were initialized */</div><div class='ctx'> 	if (job-&gt;base.s_fence &amp;&amp; job-&gt;base.s_fence-&gt;finished.ops)</div><div class='ctx'> 		f = &amp;job-&gt;base.s_fence-&gt;finished;</div><div class='del'>-	else if (job-&gt;hw_fence.ops)</div><div class='del'>-		f = &amp;job-&gt;hw_fence;</div><div class='add'>+	else if (job-&gt;hw_fence &amp;&amp; job-&gt;hw_fence-&gt;base.ops)</div><div class='add'>+		f = &amp;job-&gt;hw_fence-&gt;base;</div><div class='ctx'> 	else</div><div class='ctx'> 		f = NULL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; job-&gt;num_ibs; ++i)</div><div class='del'>-		amdgpu_ib_free(ring-&gt;adev, &amp;job-&gt;ibs[i], f);</div><div class='add'>+		amdgpu_ib_free(&amp;job-&gt;ibs[i], f);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_job_free_cb(struct drm_sched_job *s_job)</div><div class='hunk'>@@ -187,11 +297,16 @@ static void amdgpu_job_free_cb(struct drm_sched_job *s_job)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_free(&amp;job-&gt;explicit_sync);</div><div class='ctx'> </div><div class='del'>-	/* only put the hw fence if has embedded fence */</div><div class='del'>-	if (!job-&gt;hw_fence.ops)</div><div class='del'>-		kfree(job);</div><div class='add'>+	if (job-&gt;hw_fence-&gt;base.ops)</div><div class='add'>+		dma_fence_put(&amp;job-&gt;hw_fence-&gt;base);</div><div class='ctx'> 	else</div><div class='del'>-		dma_fence_put(&amp;job-&gt;hw_fence);</div><div class='add'>+		kfree(job-&gt;hw_fence);</div><div class='add'>+	if (job-&gt;hw_vm_fence-&gt;base.ops)</div><div class='add'>+		dma_fence_put(&amp;job-&gt;hw_vm_fence-&gt;base);</div><div class='add'>+	else</div><div class='add'>+		kfree(job-&gt;hw_vm_fence);</div><div class='add'>+</div><div class='add'>+	kfree(job);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_job_set_gang_leader(struct amdgpu_job *job,</div><div class='hunk'>@@ -220,10 +335,16 @@ void amdgpu_job_free(struct amdgpu_job *job)</div><div class='ctx'> 	if (job-&gt;gang_submit != &amp;job-&gt;base.s_fence-&gt;scheduled)</div><div class='ctx'> 		dma_fence_put(job-&gt;gang_submit);</div><div class='ctx'> </div><div class='del'>-	if (!job-&gt;hw_fence.ops)</div><div class='del'>-		kfree(job);</div><div class='add'>+	if (job-&gt;hw_fence-&gt;base.ops)</div><div class='add'>+		dma_fence_put(&amp;job-&gt;hw_fence-&gt;base);</div><div class='add'>+	else</div><div class='add'>+		kfree(job-&gt;hw_fence);</div><div class='add'>+	if (job-&gt;hw_vm_fence-&gt;base.ops)</div><div class='add'>+		dma_fence_put(&amp;job-&gt;hw_vm_fence-&gt;base);</div><div class='ctx'> 	else</div><div class='del'>-		dma_fence_put(&amp;job-&gt;hw_fence);</div><div class='add'>+		kfree(job-&gt;hw_vm_fence);</div><div class='add'>+</div><div class='add'>+	kfree(job);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)</div><div class='hunk'>@@ -259,26 +380,33 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = to_amdgpu_ring(s_entity-&gt;rq-&gt;sched);</div><div class='ctx'> 	struct amdgpu_job *job = to_amdgpu_job(sched_job);</div><div class='del'>-	struct dma_fence *fence = NULL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* Ignore soft recovered fences here */</div><div class='ctx'> 	r = drm_sched_entity_error(s_entity);</div><div class='del'>-	if (r &amp;&amp; r != -ENODATA)</div><div class='add'>+	if (r)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='del'>-	if (!fence &amp;&amp; job-&gt;gang_submit)</div><div class='add'>+	if (job-&gt;gang_submit) {</div><div class='ctx'> 		fence = amdgpu_device_switch_gang(ring-&gt;adev, job-&gt;gang_submit);</div><div class='add'>+		if (fence)</div><div class='add'>+			return fence;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fence = amdgpu_device_enforce_isolation(ring-&gt;adev, ring, job);</div><div class='add'>+	if (fence)</div><div class='add'>+		return fence;</div><div class='ctx'> </div><div class='del'>-	while (!fence &amp;&amp; job-&gt;vm &amp;&amp; !job-&gt;vmid) {</div><div class='add'>+	if (job-&gt;vm &amp;&amp; !job-&gt;vmid) {</div><div class='ctx'> 		r = amdgpu_vmid_grab(job-&gt;vm, ring, job, &amp;fence);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Error getting VM ID (%d)\n", r);</div><div class='add'>+			dev_err(ring-&gt;adev-&gt;dev, "Error getting VM ID (%d)\n", r);</div><div class='ctx'> 			goto error;</div><div class='ctx'> 		}</div><div class='add'>+		return fence;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return fence;</div><div class='add'>+	return NULL;</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='ctx'> 	dma_fence_set_error(&amp;job-&gt;base.s_fence-&gt;finished, r);</div><div class='hunk'>@@ -304,12 +432,15 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)</div><div class='ctx'> 		dma_fence_set_error(finished, -ECANCELED);</div><div class='ctx'> </div><div class='ctx'> 	if (finished-&gt;error &lt; 0) {</div><div class='del'>-		DRM_INFO("Skip scheduling IBs!\n");</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Skip scheduling IBs in ring(%s)",</div><div class='add'>+			ring-&gt;name);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		r = amdgpu_ib_schedule(ring, job-&gt;num_ibs, job-&gt;ibs, job,</div><div class='ctx'> 				       &amp;fence);</div><div class='ctx'> 		if (r)</div><div class='del'>-			DRM_ERROR("Error scheduling IBs (%d)\n", r);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Error scheduling IBs (%d) in ring(%s)", r,</div><div class='add'>+				ring-&gt;name);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	job-&gt;job_run_counter++;</div><div class='hunk'>@@ -319,8 +450,24 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)</div><div class='ctx'> 	return fence;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define to_drm_sched_job(sched_job)		\</div><div class='del'>-		container_of((sched_job), struct drm_sched_job, queue_node)</div><div class='add'>+/*</div><div class='add'>+ * This is a duplicate function from DRM scheduler sched_internal.h.</div><div class='add'>+ * Plan is to remove it when amdgpu_job_stop_all_jobs_on_sched is removed, due</div><div class='add'>+ * latter being incorrect and racy.</div><div class='add'>+ *</div><div class='add'>+ * See https://lore.kernel.org/amd-gfx/44edde63-7181-44fb-a4f7-94e50514f539@amd.com/</div><div class='add'>+ */</div><div class='add'>+static struct drm_sched_job *</div><div class='add'>+drm_sched_entity_queue_pop(struct drm_sched_entity *entity)</div><div class='add'>+{</div><div class='add'>+	struct spsc_node *node;</div><div class='add'>+</div><div class='add'>+	node = spsc_queue_pop(&amp;entity-&gt;job_queue);</div><div class='add'>+	if (!node)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return container_of(node, struct drm_sched_job, queue_node);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)</div><div class='ctx'> {</div><div class='hunk'>@@ -333,7 +480,7 @@ void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)</div><div class='ctx'> 		struct drm_sched_rq *rq = sched-&gt;sched_rq[i];</div><div class='ctx'> 		spin_lock(&amp;rq-&gt;lock);</div><div class='ctx'> 		list_for_each_entry(s_entity, &amp;rq-&gt;entities, list) {</div><div class='del'>-			while ((s_job = to_drm_sched_job(spsc_queue_pop(&amp;s_entity-&gt;job_queue)))) {</div><div class='add'>+			while ((s_job = drm_sched_entity_queue_pop(s_entity))) {</div><div class='ctx'> 				struct drm_sched_fence *s_fence = s_job-&gt;s_fence;</div><div class='ctx'> </div><div class='ctx'> 				dma_fence_signal(&amp;s_fence-&gt;scheduled);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h<br/>index a963a25ddd62..7abf069d17d4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_job.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_job.h</a></div><div class='hunk'>@@ -44,11 +44,28 @@</div><div class='ctx'> struct amdgpu_fence;</div><div class='ctx'> enum amdgpu_ib_pool_type;</div><div class='ctx'> </div><div class='add'>+/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE              (18446744073709551615ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES         (18446744073709551614ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE        (18446744073709551613ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR            (18446744073709551612ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER         (18446744073709551611ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER        (18446744073709551609ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE       (18446744073709551608ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT              (18446744073709551607ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER       (18446744073709551606ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER         (18446744073709551605ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB          (18446744073709551604ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP           (18446744073709551603ULL)</div><div class='add'>+#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST          (18446744073709551602ULL)</div><div class='add'>+</div><div class='ctx'> struct amdgpu_job {</div><div class='ctx'> 	struct drm_sched_job    base;</div><div class='ctx'> 	struct amdgpu_vm	*vm;</div><div class='ctx'> 	struct amdgpu_sync	explicit_sync;</div><div class='del'>-	struct dma_fence	hw_fence;</div><div class='add'>+	struct amdgpu_fence	*hw_fence;</div><div class='add'>+	struct amdgpu_fence	*hw_vm_fence;</div><div class='ctx'> 	struct dma_fence	*gang_submit;</div><div class='ctx'> 	uint32_t		preamble_status;</div><div class='ctx'> 	uint32_t                preemption_status;</div><div class='hunk'>@@ -76,6 +93,10 @@ struct amdgpu_job {</div><div class='ctx'> 	/* job_run_counter &gt;= 1 means a resubmit job */</div><div class='ctx'> 	uint32_t		job_run_counter;</div><div class='ctx'> </div><div class='add'>+	/* enforce isolation */</div><div class='add'>+	bool			enforce_isolation;</div><div class='add'>+	bool			run_cleaner_shader;</div><div class='add'>+</div><div class='ctx'> 	uint32_t		num_ibs;</div><div class='ctx'> 	struct amdgpu_ib	ibs[];</div><div class='ctx'> };</div><div class='hunk'>@@ -87,11 +108,13 @@ static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job)</div><div class='ctx'> </div><div class='ctx'> int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		     struct drm_sched_entity *entity, void *owner,</div><div class='del'>-		     unsigned int num_ibs, struct amdgpu_job **job);</div><div class='add'>+		     unsigned int num_ibs, struct amdgpu_job **job,</div><div class='add'>+		     u64 drm_client_id);</div><div class='ctx'> int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,</div><div class='ctx'> 			     struct drm_sched_entity *entity, void *owner,</div><div class='ctx'> 			     size_t size, enum amdgpu_ib_pool_type pool_type,</div><div class='del'>-			     struct amdgpu_job **job);</div><div class='add'>+			     struct amdgpu_job **job,</div><div class='add'>+			     u64 k_job_id);</div><div class='ctx'> void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,</div><div class='ctx'> 			      struct amdgpu_bo *gws, struct amdgpu_bo *oa);</div><div class='ctx'> void amdgpu_job_free_resources(struct amdgpu_job *job);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c<br/>index 6df99cb00d9a..63ee6ba6a931 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #define JPEG_IDLE_TIMEOUT	msecs_to_jiffies(1000)</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);</div><div class='add'>+static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -47,7 +48,7 @@ int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;jpeg.indirect_sram = true;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; i++) {</div><div class='del'>-		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		if (adev-&gt;jpeg.harvest_config &amp; (1U &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;jpeg.indirect_sram) {</div><div class='hunk'>@@ -73,7 +74,7 @@ int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='del'>-		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		if (adev-&gt;jpeg.harvest_config &amp; (1U &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_bo_free_kernel(</div><div class='hunk'>@@ -85,6 +86,9 @@ int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_ring_fini(&amp;adev-&gt;jpeg.inst[i].ring_dec[j]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;jpeg.reg_list)</div><div class='add'>+		amdgpu_jpeg_reg_dump_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	mutex_destroy(&amp;adev-&gt;jpeg.jpeg_pg_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -110,17 +114,19 @@ static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)</div><div class='ctx'> 	unsigned int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='del'>-		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		if (adev-&gt;jpeg.harvest_config &amp; (1U &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j)</div><div class='ctx'> 			fences += amdgpu_fence_count_emitted(&amp;adev-&gt;jpeg.inst[i].ring_dec[j]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!fences &amp;&amp; !atomic_read(&amp;adev-&gt;jpeg.total_submission_cnt))</div><div class='add'>+	if (!fences &amp;&amp; !atomic_read(&amp;adev-&gt;jpeg.total_submission_cnt)) {</div><div class='add'>+		mutex_lock(&amp;adev-&gt;jpeg.jpeg_pg_lock);</div><div class='ctx'> 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,</div><div class='ctx'> 						       AMD_PG_STATE_GATE);</div><div class='del'>-	else</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;jpeg.jpeg_pg_lock);</div><div class='add'>+	} else</div><div class='ctx'> 		schedule_delayed_work(&amp;adev-&gt;jpeg.idle_work, JPEG_IDLE_TIMEOUT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -190,7 +196,8 @@ static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL, ib_size_dw * 4,</div><div class='del'>-				     AMDGPU_IB_POOL_DIRECT, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DIRECT, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -342,3 +349,259 @@ int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,</div><div class='ctx'> </div><div class='ctx'> 	return psp_execute_ip_fw_load(&amp;adev-&gt;psp, &amp;ucode);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * debugfs for to enable/disable jpeg job submission to specific core.</div><div class='add'>+ */</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i, j;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	mask = (1ULL &lt;&lt; (adev-&gt;jpeg.num_jpeg_inst * adev-&gt;jpeg.num_jpeg_rings)) - 1;</div><div class='add'>+	if ((val &amp; mask) == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+			if (val &amp; (BIT_ULL((i * adev-&gt;jpeg.num_jpeg_rings) + j)))</div><div class='add'>+				ring-&gt;sched.ready = true;</div><div class='add'>+			else</div><div class='add'>+				ring-&gt;sched.ready = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/* publish sched.ready flag update effective immediately across smp */</div><div class='add'>+	smp_rmb();</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i, j;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+			if (ring-&gt;sched.ready)</div><div class='add'>+				mask |= 1ULL &lt;&lt; ((i * adev-&gt;jpeg.num_jpeg_rings) + j);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	*val = mask;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,</div><div class='add'>+			 amdgpu_debugfs_jpeg_sched_mask_get,</div><div class='add'>+			 amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	char name[32];</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;jpeg.num_jpeg_inst &gt; 1) &amp;&amp; !(adev-&gt;jpeg.num_jpeg_rings &gt; 1))</div><div class='add'>+		return;</div><div class='add'>+	sprintf(name, "amdgpu_jpeg_sched_mask");</div><div class='add'>+	debugfs_create_file(name, 0600, root, adev,</div><div class='add'>+			    &amp;amdgpu_debugfs_jpeg_sched_mask_fops);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	return amdgpu_show_reset_mask(buf, adev-&gt;jpeg.supported_reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR(jpeg_reset_mask, 0444,</div><div class='add'>+		   amdgpu_get_jpeg_reset_mask, NULL);</div><div class='add'>+</div><div class='add'>+int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;jpeg.num_jpeg_inst) {</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_jpeg_reset_mask);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd) {</div><div class='add'>+		if (adev-&gt;jpeg.num_jpeg_inst)</div><div class='add'>+			device_remove_file(adev-&gt;dev, &amp;dev_attr_jpeg_reset_mask);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev,</div><div class='add'>+			       const struct amdgpu_hwip_reg_entry *reg, u32 count)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;jpeg.ip_dump = kcalloc(adev-&gt;jpeg.num_jpeg_inst * count,</div><div class='add'>+				     sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;jpeg.ip_dump) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Failed to allocate memory for JPEG IP Dump\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	adev-&gt;jpeg.reg_list = reg;</div><div class='add'>+	adev-&gt;jpeg.reg_count = count;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	kfree(adev-&gt;jpeg.ip_dump);</div><div class='add'>+	adev-&gt;jpeg.reg_list = NULL;</div><div class='add'>+	adev-&gt;jpeg.reg_count = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	u32 inst_off, inst_id, is_powered;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;jpeg.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; i++) {</div><div class='add'>+		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		inst_id = GET_INST(JPEG, i);</div><div class='add'>+		inst_off = i * adev-&gt;jpeg.reg_count;</div><div class='add'>+		/* check power status from UVD_JPEG_POWER_STATUS */</div><div class='add'>+		adev-&gt;jpeg.ip_dump[inst_off] =</div><div class='add'>+			RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev-&gt;jpeg.reg_list[0],</div><div class='add'>+							   inst_id));</div><div class='add'>+		is_powered = ((adev-&gt;jpeg.ip_dump[inst_off] &amp; 0x1) != 1);</div><div class='add'>+</div><div class='add'>+		if (is_powered)</div><div class='add'>+			for (j = 1; j &lt; adev-&gt;jpeg.reg_count; j++)</div><div class='add'>+				adev-&gt;jpeg.ip_dump[inst_off + j] =</div><div class='add'>+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev-&gt;jpeg.reg_list[j],</div><div class='add'>+									   inst_id));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	u32 inst_off, is_powered;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;jpeg.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;jpeg.num_jpeg_inst);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; i++) {</div><div class='add'>+		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i)) {</div><div class='add'>+			drm_printf(p, "\nHarvested Instance:JPEG%d Skipping dump\n", i);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		inst_off = i * adev-&gt;jpeg.reg_count;</div><div class='add'>+		is_powered = ((adev-&gt;jpeg.ip_dump[inst_off] &amp; 0x1) != 1);</div><div class='add'>+</div><div class='add'>+		if (is_powered) {</div><div class='add'>+			drm_printf(p, "Active Instance:JPEG%d\n", i);</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;jpeg.reg_count; j++)</div><div class='add'>+				drm_printf(p, "%-50s \t 0x%08x\n", adev-&gt;jpeg.reg_list[j].reg_name,</div><div class='add'>+					   adev-&gt;jpeg.ip_dump[inst_off + j]);</div><div class='add'>+		} else</div><div class='add'>+			drm_printf(p, "\nInactive Instance:JPEG%d\n", i);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool amdgpu_jpeg_reg_valid(u32 reg)</div><div class='add'>+{</div><div class='add'>+	if (reg &lt; JPEG_REG_RANGE_START || reg &gt; JPEG_REG_RANGE_END ||</div><div class='add'>+	    (reg &gt;= JPEG_ATOMIC_RANGE_START &amp;&amp; reg &lt;= JPEG_ATOMIC_RANGE_END))</div><div class='add'>+		return false;</div><div class='add'>+	else</div><div class='add'>+		return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_jpeg_dec_parse_cs - command submission parser</div><div class='add'>+ *</div><div class='add'>+ * @parser: Command submission parser context</div><div class='add'>+ * @job: the job to parse</div><div class='add'>+ * @ib: the IB to parse</div><div class='add'>+ *</div><div class='add'>+ * Parse the command stream, return -EINVAL for invalid packet,</div><div class='add'>+ * 0 otherwise</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser,</div><div class='add'>+			      struct amdgpu_job *job,</div><div class='add'>+			      struct amdgpu_ib *ib)</div><div class='add'>+{</div><div class='add'>+	u32 i, reg, res, cond, type;</div><div class='add'>+	struct amdgpu_device *adev = parser-&gt;adev;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ib-&gt;length_dw ; i += 2) {</div><div class='add'>+		reg  = CP_PACKETJ_GET_REG(ib-&gt;ptr[i]);</div><div class='add'>+		res  = CP_PACKETJ_GET_RES(ib-&gt;ptr[i]);</div><div class='add'>+		cond = CP_PACKETJ_GET_COND(ib-&gt;ptr[i]);</div><div class='add'>+		type = CP_PACKETJ_GET_TYPE(ib-&gt;ptr[i]);</div><div class='add'>+</div><div class='add'>+		if (res) /* only support 0 at the moment */</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		switch (type) {</div><div class='add'>+		case PACKETJ_TYPE0:</div><div class='add'>+			if (cond != PACKETJ_CONDITION_CHECK0 ||</div><div class='add'>+			    !amdgpu_jpeg_reg_valid(reg)) {</div><div class='add'>+				dev_err(adev-&gt;dev, "Invalid packet [0x%08x]!\n", ib-&gt;ptr[i]);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case PACKETJ_TYPE3:</div><div class='add'>+			if (cond != PACKETJ_CONDITION_CHECK3 ||</div><div class='add'>+			    !amdgpu_jpeg_reg_valid(reg)) {</div><div class='add'>+				dev_err(adev-&gt;dev, "Invalid packet [0x%08x]!\n", ib-&gt;ptr[i]);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case PACKETJ_TYPE6:</div><div class='add'>+			if (ib-&gt;ptr[i] == CP_PACKETJ_NOP)</div><div class='add'>+				continue;</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid packet [0x%08x]!\n", ib-&gt;ptr[i]);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		default:</div><div class='add'>+			dev_err(adev-&gt;dev, "Unknown packet type %d !\n", type);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h<br/>index aea31d61d991..346ae0ab09d3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h</a></div><div class='hunk'>@@ -25,9 +25,17 @@</div><div class='ctx'> #define __AMDGPU_JPEG_H__</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_cs.h"</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_MAX_JPEG_INSTANCES	4</div><div class='del'>-#define AMDGPU_MAX_JPEG_RINGS		8</div><div class='add'>+#define AMDGPU_MAX_JPEG_RINGS           10</div><div class='add'>+#define AMDGPU_MAX_JPEG_RINGS_4_0_3     8</div><div class='add'>+</div><div class='add'>+#define JPEG_REG_RANGE_START            0x4000</div><div class='add'>+#define JPEG_REG_RANGE_END              0x41c2</div><div class='add'>+#define JPEG_ATOMIC_RANGE_START         0x4120</div><div class='add'>+#define JPEG_ATOMIC_RANGE_END           0x412A</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_JPEG_HARVEST_JPEG0 (1 &lt;&lt; 0)</div><div class='ctx'> #define AMDGPU_JPEG_HARVEST_JPEG1 (1 &lt;&lt; 1)</div><div class='hunk'>@@ -60,6 +68,45 @@</div><div class='ctx'> 		RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA);				\</div><div class='ctx'> 	})</div><div class='ctx'> </div><div class='add'>+#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect)		\</div><div class='add'>+	do {									\</div><div class='add'>+		WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),			\</div><div class='add'>+			     regUVD_DPG_LMA_DATA, value);			\</div><div class='add'>+		WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),			\</div><div class='add'>+			     regUVD_DPG_LMA_MASK, 0xFFFFFFFF);			\</div><div class='add'>+		WREG32_SOC15(							\</div><div class='add'>+			JPEG, GET_INST(JPEG, inst_idx),				\</div><div class='add'>+			regUVD_DPG_LMA_CTL,					\</div><div class='add'>+			(UVD_DPG_LMA_CTL__READ_WRITE_MASK |			\</div><div class='add'>+			 offset &lt;&lt; UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT |	\</div><div class='add'>+			 indirect &lt;&lt; UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));	\</div><div class='add'>+	} while (0)</div><div class='add'>+</div><div class='add'>+#define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en)			\</div><div class='add'>+	do {									\</div><div class='add'>+		WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),			\</div><div class='add'>+			regUVD_DPG_LMA_MASK, 0xFFFFFFFF);			\</div><div class='add'>+		WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),			\</div><div class='add'>+			regUVD_DPG_LMA_CTL,					\</div><div class='add'>+			(UVD_DPG_LMA_CTL__MASK_EN_MASK |			\</div><div class='add'>+			offset &lt;&lt; UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));	\</div><div class='add'>+		RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA);		\</div><div class='add'>+	} while (0)</div><div class='add'>+</div><div class='add'>+#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect)		\</div><div class='add'>+	do {									\</div><div class='add'>+		*adev-&gt;jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset;	\</div><div class='add'>+		*adev-&gt;jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value;	\</div><div class='add'>+	} while (0)</div><div class='add'>+</div><div class='add'>+struct amdgpu_hwip_reg_entry;</div><div class='add'>+</div><div class='add'>+enum amdgpu_jpeg_caps {</div><div class='add'>+	AMDGPU_JPEG_RRMT_ENABLED,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define AMDGPU_JPEG_CAPS(caps) BIT(AMDGPU_JPEG_##caps)</div><div class='add'>+</div><div class='ctx'> struct amdgpu_jpeg_reg{</div><div class='ctx'> 	unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];</div><div class='ctx'> };</div><div class='hunk'>@@ -97,6 +144,11 @@ struct amdgpu_jpeg {</div><div class='ctx'> 	uint16_t inst_mask;</div><div class='ctx'> 	uint8_t num_inst_per_aid;</div><div class='ctx'> 	bool	indirect_sram;</div><div class='add'>+	uint32_t supported_reset;</div><div class='add'>+	uint32_t caps;</div><div class='add'>+	u32 *ip_dump;</div><div class='add'>+	u32 reg_count;</div><div class='add'>+	const struct amdgpu_hwip_reg_entry *reg_list;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);</div><div class='hunk'>@@ -118,5 +170,15 @@ int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,</div><div class='ctx'> 			       enum AMDGPU_UCODE_ID ucode_id);</div><div class='add'>+void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev,</div><div class='add'>+			       const struct amdgpu_hwip_reg_entry *reg, u32 count);</div><div class='add'>+void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block);</div><div class='add'>+void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p);</div><div class='add'>+int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser,</div><div class='add'>+			     struct amdgpu_job *job,</div><div class='add'>+			     struct amdgpu_ib *ib);</div><div class='ctx'> </div><div class='ctx'> #endif /*__AMDGPU_JPEG_H__*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br/>index a2df3025a754..6ee77f431d56 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c</a></div><div class='hunk'>@@ -43,7 +43,9 @@</div><div class='ctx'> #include "amdgpu_gem.h"</div><div class='ctx'> #include "amdgpu_display.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> #include "amd_pcie.h"</div><div class='add'>+#include "amdgpu_userq.h"</div><div class='ctx'> </div><div class='ctx'> void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -89,7 +91,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)</div><div class='ctx'> 	if (adev-&gt;rmmio == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))</div><div class='add'>+	if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD))</div><div class='ctx'> 		DRM_WARN("smart shift update failed\n");</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_acpi_fini(adev);</div><div class='hunk'>@@ -149,38 +151,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_NONE;</div><div class='del'>-	if (amdgpu_device_supports_px(dev) &amp;&amp;</div><div class='del'>-	    (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */</div><div class='del'>-		adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_PX;</div><div class='del'>-		dev_info(adev-&gt;dev, "Using ATPX for runtime pm\n");</div><div class='del'>-	} else if (amdgpu_device_supports_boco(dev) &amp;&amp;</div><div class='del'>-		   (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */</div><div class='del'>-		adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BOCO;</div><div class='del'>-		dev_info(adev-&gt;dev, "Using BOCO for runtime pm\n");</div><div class='del'>-	} else if (amdgpu_device_supports_baco(dev) &amp;&amp;</div><div class='del'>-		   (amdgpu_runtime_pm != 0)) {</div><div class='del'>-		switch (adev-&gt;asic_type) {</div><div class='del'>-		case CHIP_VEGA20:</div><div class='del'>-		case CHIP_ARCTURUS:</div><div class='del'>-			/* enable BACO as runpm mode if runpm=1 */</div><div class='del'>-			if (amdgpu_runtime_pm &gt; 0)</div><div class='del'>-				adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='del'>-			break;</div><div class='del'>-		case CHIP_VEGA10:</div><div class='del'>-			/* enable BACO as runpm mode if noretry=0 */</div><div class='del'>-			if (!adev-&gt;gmc.noretry)</div><div class='del'>-				adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			/* enable BACO as runpm mode on CI+ */</div><div class='del'>-			adev-&gt;pm.rpm_mode = AMDGPU_RUNPM_BACO;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO)</div><div class='del'>-			dev_info(adev-&gt;dev, "Using BACO for runtime pm\n");</div><div class='del'>-	}</div><div class='add'>+	amdgpu_device_detect_runtime_pm_mode(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* Call ACPI methods: require modeset init</div><div class='ctx'> 	 * but failure is not fatal</div><div class='hunk'>@@ -190,7 +161,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)</div><div class='ctx'> 	if (acpi_status)</div><div class='ctx'> 		dev_dbg(dev-&gt;dev, "Error during ACPI methods call\n");</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))</div><div class='add'>+	if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD))</div><div class='ctx'> 		DRM_WARN("smart shift update failed\n");</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='hunk'>@@ -400,6 +371,26 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev,</div><div class='add'>+					  struct drm_amdgpu_info *info,</div><div class='add'>+					  struct drm_amdgpu_info_uq_metadata_gfx *meta)</div><div class='add'>+{</div><div class='add'>+	int ret = -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.funcs-&gt;get_gfx_shadow_info) {</div><div class='add'>+		struct amdgpu_gfx_shadow_info shadow = {};</div><div class='add'>+</div><div class='add'>+		adev-&gt;gfx.funcs-&gt;get_gfx_shadow_info(adev, &amp;shadow, true);</div><div class='add'>+		meta-&gt;shadow_size = shadow.shadow_size;</div><div class='add'>+		meta-&gt;shadow_alignment = shadow.shadow_alignment;</div><div class='add'>+		meta-&gt;csa_size = shadow.csa_size;</div><div class='add'>+		meta-&gt;csa_alignment = shadow.csa_alignment;</div><div class='add'>+		ret = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 			     struct drm_amdgpu_info *info,</div><div class='ctx'> 			     struct drm_amdgpu_info_hw_ip *result)</div><div class='hunk'>@@ -408,6 +399,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 	uint32_t ib_size_alignment = 0;</div><div class='ctx'> 	enum amd_ip_block_type type;</div><div class='ctx'> 	unsigned int num_rings = 0;</div><div class='add'>+	uint32_t num_slots = 0;</div><div class='ctx'> 	unsigned int i, j;</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;query_hw_ip.ip_instance &gt;= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)</div><div class='hunk'>@@ -417,24 +409,45 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 	case AMDGPU_HW_IP_GFX:</div><div class='ctx'> 		type = AMD_IP_BLOCK_TYPE_GFX;</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='del'>-			if (adev-&gt;gfx.gfx_ring[i].sched.ready)</div><div class='add'>+			if (adev-&gt;gfx.gfx_ring[i].sched.ready &amp;&amp;</div><div class='add'>+			    !adev-&gt;gfx.gfx_ring[i].no_user_submission)</div><div class='ctx'> 				++num_rings;</div><div class='add'>+</div><div class='add'>+		if (!adev-&gt;gfx.disable_uq) {</div><div class='add'>+			for (i = 0; i &lt; AMDGPU_MES_MAX_GFX_PIPES; i++)</div><div class='add'>+				num_slots += hweight32(adev-&gt;mes.gfx_hqd_mask[i]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		ib_start_alignment = 32;</div><div class='ctx'> 		ib_size_alignment = 32;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_HW_IP_COMPUTE:</div><div class='ctx'> 		type = AMD_IP_BLOCK_TYPE_GFX;</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++)</div><div class='del'>-			if (adev-&gt;gfx.compute_ring[i].sched.ready)</div><div class='add'>+			if (adev-&gt;gfx.compute_ring[i].sched.ready &amp;&amp;</div><div class='add'>+			    !adev-&gt;gfx.compute_ring[i].no_user_submission)</div><div class='ctx'> 				++num_rings;</div><div class='add'>+</div><div class='add'>+		if (!adev-&gt;sdma.disable_uq) {</div><div class='add'>+			for (i = 0; i &lt; AMDGPU_MES_MAX_COMPUTE_PIPES; i++)</div><div class='add'>+				num_slots += hweight32(adev-&gt;mes.compute_hqd_mask[i]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		ib_start_alignment = 32;</div><div class='ctx'> 		ib_size_alignment = 32;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_HW_IP_DMA:</div><div class='ctx'> 		type = AMD_IP_BLOCK_TYPE_SDMA;</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='del'>-			if (adev-&gt;sdma.instance[i].ring.sched.ready)</div><div class='add'>+			if (adev-&gt;sdma.instance[i].ring.sched.ready &amp;&amp;</div><div class='add'>+			    !adev-&gt;sdma.instance[i].ring.no_user_submission)</div><div class='ctx'> 				++num_rings;</div><div class='add'>+</div><div class='add'>+		if (!adev-&gt;gfx.disable_uq) {</div><div class='add'>+			for (i = 0; i &lt; AMDGPU_MES_MAX_SDMA_PIPES; i++)</div><div class='add'>+				num_slots += hweight32(adev-&gt;mes.sdma_hqd_mask[i]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='ctx'> 		ib_size_alignment = 4;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -444,7 +457,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 			if (adev-&gt;uvd.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			if (adev-&gt;uvd.inst[i].ring.sched.ready)</div><div class='add'>+			if (adev-&gt;uvd.inst[i].ring.sched.ready &amp;&amp;</div><div class='add'>+			    !adev-&gt;uvd.inst[i].ring.no_user_submission)</div><div class='ctx'> 				++num_rings;</div><div class='ctx'> 		}</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='hunk'>@@ -453,7 +467,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 	case AMDGPU_HW_IP_VCE:</div><div class='ctx'> 		type = AMD_IP_BLOCK_TYPE_VCE;</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vce.num_rings; i++)</div><div class='del'>-			if (adev-&gt;vce.ring[i].sched.ready)</div><div class='add'>+			if (adev-&gt;vce.ring[i].sched.ready &amp;&amp;</div><div class='add'>+			    !adev-&gt;vce.ring[i].no_user_submission)</div><div class='ctx'> 				++num_rings;</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='ctx'> 		ib_size_alignment = 4;</div><div class='hunk'>@@ -465,7 +480,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			for (j = 0; j &lt; adev-&gt;uvd.num_enc_rings; j++)</div><div class='del'>-				if (adev-&gt;uvd.inst[i].ring_enc[j].sched.ready)</div><div class='add'>+				if (adev-&gt;uvd.inst[i].ring_enc[j].sched.ready &amp;&amp;</div><div class='add'>+				    !adev-&gt;uvd.inst[i].ring_enc[j].no_user_submission)</div><div class='ctx'> 					++num_rings;</div><div class='ctx'> 		}</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='hunk'>@@ -477,7 +493,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			if (adev-&gt;vcn.inst[i].ring_dec.sched.ready)</div><div class='add'>+			if (adev-&gt;vcn.inst[i].ring_dec.sched.ready &amp;&amp;</div><div class='add'>+			    !adev-&gt;vcn.inst[i].ring_dec.no_user_submission)</div><div class='ctx'> 				++num_rings;</div><div class='ctx'> 		}</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='hunk'>@@ -489,8 +506,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			for (j = 0; j &lt; adev-&gt;vcn.num_enc_rings; j++)</div><div class='del'>-				if (adev-&gt;vcn.inst[i].ring_enc[j].sched.ready)</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; j++)</div><div class='add'>+				if (adev-&gt;vcn.inst[i].ring_enc[j].sched.ready &amp;&amp;</div><div class='add'>+				    !adev-&gt;vcn.inst[i].ring_enc[j].no_user_submission)</div><div class='ctx'> 					++num_rings;</div><div class='ctx'> 		}</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='hunk'>@@ -505,7 +523,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; j++)</div><div class='del'>-				if (adev-&gt;jpeg.inst[i].ring_dec[j].sched.ready)</div><div class='add'>+				if (adev-&gt;jpeg.inst[i].ring_dec[j].sched.ready &amp;&amp;</div><div class='add'>+				    !adev-&gt;jpeg.inst[i].ring_dec[j].no_user_submission)</div><div class='ctx'> 					++num_rings;</div><div class='ctx'> 		}</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='hunk'>@@ -513,7 +532,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_HW_IP_VPE:</div><div class='ctx'> 		type = AMD_IP_BLOCK_TYPE_VPE;</div><div class='del'>-		if (adev-&gt;vpe.ring.sched.ready)</div><div class='add'>+		if (adev-&gt;vpe.ring.sched.ready &amp;&amp;</div><div class='add'>+		    !adev-&gt;vpe.ring.no_user_submission)</div><div class='ctx'> 			++num_rings;</div><div class='ctx'> 		ib_start_alignment = 256;</div><div class='ctx'> 		ib_size_alignment = 4;</div><div class='hunk'>@@ -569,6 +589,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> 	result-&gt;capabilities_flags = 0;</div><div class='ctx'> 	result-&gt;available_rings = (1 &lt;&lt; num_rings) - 1;</div><div class='add'>+	result-&gt;userq_num_slots = num_slots;</div><div class='ctx'> 	result-&gt;ib_start_alignment = ib_start_alignment;</div><div class='ctx'> 	result-&gt;ib_size_alignment = ib_size_alignment;</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -649,30 +670,37 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;xcp_mgr &amp;&amp; adev-&gt;xcp_mgr-&gt;num_xcps &gt; 0 &amp;&amp;</div><div class='del'>-		    fpriv-&gt;xcp_id &gt;= 0 &amp;&amp; fpriv-&gt;xcp_id &lt; adev-&gt;xcp_mgr-&gt;num_xcps) {</div><div class='add'>+		    fpriv-&gt;xcp_id &lt; adev-&gt;xcp_mgr-&gt;num_xcps) {</div><div class='ctx'> 			xcp = &amp;adev-&gt;xcp_mgr-&gt;xcp[fpriv-&gt;xcp_id];</div><div class='ctx'> 			switch (type) {</div><div class='ctx'> 			case AMD_IP_BLOCK_TYPE_GFX:</div><div class='ctx'> 				ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &amp;inst_mask);</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 				count = hweight32(inst_mask);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case AMD_IP_BLOCK_TYPE_SDMA:</div><div class='ctx'> 				ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &amp;inst_mask);</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 				count = hweight32(inst_mask);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case AMD_IP_BLOCK_TYPE_JPEG:</div><div class='ctx'> 				ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &amp;inst_mask);</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 				count = hweight32(inst_mask) * adev-&gt;jpeg.num_jpeg_rings;</div><div class='ctx'> 				break;</div><div class='ctx'> 			case AMD_IP_BLOCK_TYPE_VCN:</div><div class='ctx'> 				ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &amp;inst_mask);</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 				count = hweight32(inst_mask);</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> 			}</div><div class='del'>-			if (ret)</div><div class='del'>-				return ret;</div><div class='add'>+</div><div class='ctx'> 			return copy_to_user(out, &amp;count, min(size, 4u)) ? -EFAULT : 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -730,7 +758,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 		ui64 = atomic64_read(&amp;adev-&gt;num_vram_cpu_page_faults);</div><div class='ctx'> 		return copy_to_user(out, &amp;ui64, min(size, 8u)) ? -EFAULT : 0;</div><div class='ctx'> 	case AMDGPU_INFO_VRAM_USAGE:</div><div class='del'>-		ui64 = ttm_resource_manager_usage(&amp;adev-&gt;mman.vram_mgr.manager);</div><div class='add'>+		ui64 = ttm_resource_manager_used(&amp;adev-&gt;mman.vram_mgr.manager) ?</div><div class='add'>+			ttm_resource_manager_usage(&amp;adev-&gt;mman.vram_mgr.manager) : 0;</div><div class='ctx'> 		return copy_to_user(out, &amp;ui64, min(size, 8u)) ? -EFAULT : 0;</div><div class='ctx'> 	case AMDGPU_INFO_VIS_VRAM_USAGE:</div><div class='ctx'> 		ui64 = amdgpu_vram_mgr_vis_usage(&amp;adev-&gt;mman.vram_mgr);</div><div class='hunk'>@@ -776,8 +805,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 		mem.vram.usable_heap_size = adev-&gt;gmc.real_vram_size -</div><div class='ctx'> 			atomic64_read(&amp;adev-&gt;vram_pin_size) -</div><div class='ctx'> 			AMDGPU_VM_RESERVED_VRAM;</div><div class='del'>-		mem.vram.heap_usage =</div><div class='del'>-			ttm_resource_manager_usage(vram_man);</div><div class='add'>+		mem.vram.heap_usage = ttm_resource_manager_used(&amp;adev-&gt;mman.vram_mgr.manager) ?</div><div class='add'>+				ttm_resource_manager_usage(vram_man) : 0;</div><div class='ctx'> 		mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;</div><div class='ctx'> </div><div class='ctx'> 		mem.cpu_accessible_vram.total_heap_size =</div><div class='hunk'>@@ -802,6 +831,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 				    ? -EFAULT : 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	case AMDGPU_INFO_READ_MMR_REG: {</div><div class='add'>+		int ret = 0;</div><div class='ctx'> 		unsigned int n, alloc_size;</div><div class='ctx'> 		uint32_t *regs;</div><div class='ctx'> 		unsigned int se_num = (info-&gt;read_mmr_reg.instance &gt;&gt;</div><div class='hunk'>@@ -811,24 +841,37 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 				   AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &amp;</div><div class='ctx'> 				  AMDGPU_INFO_MMR_SH_INDEX_MASK;</div><div class='ctx'> </div><div class='add'>+		if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='ctx'> 		/* set full masks if the userspace set all bits</div><div class='ctx'> 		 * in the bitfields</div><div class='ctx'> 		 */</div><div class='del'>-		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)</div><div class='add'>+		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {</div><div class='ctx'> 			se_num = 0xffffffff;</div><div class='del'>-		else if (se_num &gt;= AMDGPU_GFX_MAX_SE)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)</div><div class='add'>+		} else if (se_num &gt;= AMDGPU_GFX_MAX_SE) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {</div><div class='ctx'> 			sh_num = 0xffffffff;</div><div class='del'>-		else if (sh_num &gt;= AMDGPU_GFX_MAX_SH_PER_SE)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+		} else if (sh_num &gt;= AMDGPU_GFX_MAX_SH_PER_SE) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (info-&gt;read_mmr_reg.count &gt; 128)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+		if (info-&gt;read_mmr_reg.count &gt; 128) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		regs = kmalloc_array(info-&gt;read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);</div><div class='del'>-		if (!regs)</div><div class='del'>-			return -ENOMEM;</div><div class='add'>+		if (!regs) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		alloc_size = info-&gt;read_mmr_reg.count * sizeof(*regs);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_gfx_off_ctrl(adev, false);</div><div class='hunk'>@@ -840,18 +883,22 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 					      info-&gt;read_mmr_reg.dword_offset + i);</div><div class='ctx'> 				kfree(regs);</div><div class='ctx'> 				amdgpu_gfx_off_ctrl(adev, true);</div><div class='del'>-				return -EFAULT;</div><div class='add'>+				ret = -EFAULT;</div><div class='add'>+				goto out;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		amdgpu_gfx_off_ctrl(adev, true);</div><div class='ctx'> 		n = copy_to_user(out, regs, min(size, alloc_size));</div><div class='ctx'> 		kfree(regs);</div><div class='del'>-		return n ? -EFAULT : 0;</div><div class='add'>+		ret = (n ? -EFAULT : 0);</div><div class='add'>+out:</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	case AMDGPU_INFO_DEV_INFO: {</div><div class='ctx'> 		struct drm_amdgpu_info_device *dev_info;</div><div class='ctx'> 		uint64_t vm_size;</div><div class='del'>-		uint32_t pcie_gen_mask;</div><div class='add'>+		uint32_t pcie_gen_mask, pcie_width_mask;</div><div class='ctx'> </div><div class='ctx'> 		dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);</div><div class='ctx'> 		if (!dev_info)</div><div class='hunk'>@@ -893,6 +940,19 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 		if (adev-&gt;gfx.config.ta_cntl2_truncate_coord_mode)</div><div class='ctx'> 			dev_info-&gt;ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;</div><div class='ctx'> </div><div class='add'>+		/* Gang submit is not supported under SRIOV currently */</div><div class='add'>+		if (!amdgpu_sriov_vf(adev))</div><div class='add'>+			dev_info-&gt;ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT;</div><div class='add'>+</div><div class='add'>+		if (amdgpu_passthrough(adev))</div><div class='add'>+			dev_info-&gt;ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT &lt;&lt;</div><div class='add'>+						AMDGPU_IDS_FLAGS_MODE_SHIFT) &amp;</div><div class='add'>+						AMDGPU_IDS_FLAGS_MODE_MASK;</div><div class='add'>+		else if (amdgpu_sriov_vf(adev))</div><div class='add'>+			dev_info-&gt;ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF &lt;&lt;</div><div class='add'>+						AMDGPU_IDS_FLAGS_MODE_SHIFT) &amp;</div><div class='add'>+						AMDGPU_IDS_FLAGS_MODE_MASK;</div><div class='add'>+</div><div class='ctx'> 		vm_size = adev-&gt;vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> 		vm_size -= AMDGPU_VA_RESERVED_TOP;</div><div class='ctx'> </div><div class='hunk'>@@ -939,15 +999,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 		dev_info-&gt;tcc_disabled_mask = adev-&gt;gfx.config.tcc_disabled_mask;</div><div class='ctx'> </div><div class='ctx'> 		/* Combine the chip gen mask with the platform (CPU/mobo) mask. */</div><div class='del'>-		pcie_gen_mask = adev-&gt;pm.pcie_gen_mask &amp; (adev-&gt;pm.pcie_gen_mask &gt;&gt; 16);</div><div class='add'>+		pcie_gen_mask = adev-&gt;pm.pcie_gen_mask &amp;</div><div class='add'>+			(adev-&gt;pm.pcie_gen_mask &gt;&gt; CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT);</div><div class='add'>+		pcie_width_mask = adev-&gt;pm.pcie_mlw_mask &amp;</div><div class='add'>+			(adev-&gt;pm.pcie_mlw_mask &gt;&gt; CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT);</div><div class='ctx'> 		dev_info-&gt;pcie_gen = fls(pcie_gen_mask);</div><div class='ctx'> 		dev_info-&gt;pcie_num_lanes =</div><div class='del'>-			adev-&gt;pm.pcie_mlw_mask &amp; CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :</div><div class='del'>-			adev-&gt;pm.pcie_mlw_mask &amp; CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :</div><div class='del'>-			adev-&gt;pm.pcie_mlw_mask &amp; CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :</div><div class='del'>-			adev-&gt;pm.pcie_mlw_mask &amp; CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :</div><div class='del'>-			adev-&gt;pm.pcie_mlw_mask &amp; CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :</div><div class='del'>-			adev-&gt;pm.pcie_mlw_mask &amp; CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;</div><div class='add'>+			pcie_width_mask &amp; CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :</div><div class='add'>+			pcie_width_mask &amp; CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :</div><div class='add'>+			pcie_width_mask &amp; CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :</div><div class='add'>+			pcie_width_mask &amp; CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :</div><div class='add'>+			pcie_width_mask &amp; CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :</div><div class='add'>+			pcie_width_mask &amp; CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;</div><div class='ctx'> </div><div class='ctx'> 		dev_info-&gt;tcp_cache_size = adev-&gt;gfx.config.gc_tcp_l1_size;</div><div class='ctx'> 		dev_info-&gt;num_sqc_per_wgp = adev-&gt;gfx.config.gc_num_sqc_per_wgp;</div><div class='hunk'>@@ -971,6 +1034,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		dev_info-&gt;userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev);</div><div class='add'>+</div><div class='ctx'> 		ret = copy_to_user(out, dev_info,</div><div class='ctx'> 				   min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;</div><div class='ctx'> 		kfree(dev_info);</div><div class='hunk'>@@ -1286,6 +1351,22 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 		return copy_to_user(out, &amp;gpuvm_fault,</div><div class='ctx'> 				    min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;</div><div class='ctx'> 	}</div><div class='add'>+	case AMDGPU_INFO_UQ_FW_AREAS: {</div><div class='add'>+		struct drm_amdgpu_info_uq_metadata meta_info = {};</div><div class='add'>+</div><div class='add'>+		switch (info-&gt;query_hw_ip.type) {</div><div class='add'>+		case AMDGPU_HW_IP_GFX:</div><div class='add'>+			ret = amdgpu_userq_metadata_info_gfx(adev, info, &amp;meta_info.gfx);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			ret = copy_to_user(out, &amp;meta_info,</div><div class='add'>+						min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0;</div><div class='add'>+			return 0;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> 	default:</div><div class='ctx'> 		DRM_DEBUG_KMS("Invalid request %d\n", info-&gt;query);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1293,23 +1374,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Outdated mess for old drm with Xorg being in charge (void function now).</div><div class='del'>- */</div><div class='del'>-/**</div><div class='del'>- * amdgpu_driver_lastclose_kms - drm callback for last close</div><div class='del'>- *</div><div class='del'>- * @dev: drm dev pointer</div><div class='del'>- *</div><div class='del'>- * Switch vga_switcheroo state after last close (all asics).</div><div class='del'>- */</div><div class='del'>-void amdgpu_driver_lastclose_kms(struct drm_device *dev)</div><div class='del'>-{</div><div class='del'>-	drm_fb_helper_lastclose(dev);</div><div class='del'>-	vga_switcheroo_process_delayed_switch();</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_driver_open_kms - drm callback for open</div><div class='ctx'>  *</div><div class='hunk'>@@ -1356,13 +1420,11 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error_pasid;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vm_init(adev, &amp;fpriv-&gt;vm, fpriv-&gt;xcp_id);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_pasid;</div><div class='add'>+	amdgpu_debugfs_vm_init(file_priv);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vm_set_pasid(adev, &amp;fpriv-&gt;vm, pasid);</div><div class='add'>+	r = amdgpu_vm_init(adev, &amp;fpriv-&gt;vm, fpriv-&gt;xcp_id, pasid);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto error_vm;</div><div class='add'>+		goto error_pasid;</div><div class='ctx'> </div><div class='ctx'> 	fpriv-&gt;prt_va = amdgpu_vm_bo_add(adev, &amp;fpriv-&gt;vm, NULL);</div><div class='ctx'> 	if (!fpriv-&gt;prt_va) {</div><div class='hunk'>@@ -1386,6 +1448,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)</div><div class='ctx'> 	mutex_init(&amp;fpriv-&gt;bo_list_lock);</div><div class='ctx'> 	idr_init_base(&amp;fpriv-&gt;bo_list_handles, 1);</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_userq_mgr_init(&amp;fpriv-&gt;userq_mgr, file_priv, adev);</div><div class='add'>+	if (r)</div><div class='add'>+		DRM_WARN("Can't setup usermode queues, use legacy workload submission only\n");</div><div class='add'>+</div><div class='add'>+	r = amdgpu_eviction_fence_init(&amp;fpriv-&gt;evf_mgr);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_vm;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ctx_mgr_init(&amp;fpriv-&gt;ctx_mgr, adev);</div><div class='ctx'> </div><div class='ctx'> 	file_priv-&gt;driver_priv = fpriv;</div><div class='hunk'>@@ -1395,15 +1465,12 @@ error_vm:</div><div class='ctx'> 	amdgpu_vm_fini(adev, &amp;fpriv-&gt;vm);</div><div class='ctx'> </div><div class='ctx'> error_pasid:</div><div class='del'>-	if (pasid) {</div><div class='add'>+	if (pasid)</div><div class='ctx'> 		amdgpu_pasid_free(pasid);</div><div class='del'>-		amdgpu_vm_set_pasid(adev, &amp;fpriv-&gt;vm, 0);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(fpriv);</div><div class='ctx'> </div><div class='ctx'> out_suspend:</div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> pm_put:</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -1471,7 +1538,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,</div><div class='ctx'> 	kfree(fpriv);</div><div class='ctx'> 	file_priv-&gt;driver_priv = NULL;</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c<br/>index 24ad4b97177b..3ca03b5e0f91 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c</a></div><div class='hunk'>@@ -153,7 +153,7 @@ int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)</div><div class='add'>+static void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)</div><div class='ctx'> {</div><div class='ctx'> 	if (!mca_set)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -162,7 +162,7 @@ void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;mca_set-&gt;list);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry)</div><div class='add'>+static int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry)</div><div class='ctx'> {</div><div class='ctx'> 	struct mca_bank_node *node;</div><div class='ctx'> </div><div class='hunk'>@@ -183,107 +183,113 @@ int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set)</div><div class='add'>+static int amdgpu_mca_bank_set_merge(struct mca_bank_set *mca_set, struct mca_bank_set *new)</div><div class='ctx'> {</div><div class='del'>-	struct mca_bank_node *node, *tmp;</div><div class='add'>+	struct mca_bank_node *node;</div><div class='ctx'> </div><div class='del'>-	list_for_each_entry_safe(node, tmp, &amp;mca_set-&gt;list, node) {</div><div class='del'>-		list_del(&amp;node-&gt;node);</div><div class='del'>-		kvfree(node);</div><div class='del'>-	}</div><div class='add'>+	list_for_each_entry(node, &amp;new-&gt;list, node)</div><div class='add'>+		amdgpu_mca_bank_set_add_entry(mca_set, &amp;node-&gt;entry);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs)</div><div class='add'>+static void amdgpu_mca_bank_set_remove_node(struct mca_bank_set *mca_set, struct mca_bank_node *node)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_mca *mca = &amp;adev-&gt;mca;</div><div class='add'>+	if (!node)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	mca-&gt;mca_funcs = mca_funcs;</div><div class='add'>+	list_del(&amp;node-&gt;node);</div><div class='add'>+	kvfree(node);</div><div class='add'>+</div><div class='add'>+	mca_set-&gt;nr_entries--;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)</div><div class='add'>+static void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set)</div><div class='ctx'> {</div><div class='del'>-	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='add'>+	struct mca_bank_node *node, *tmp;</div><div class='ctx'> </div><div class='del'>-	if (mca_funcs &amp;&amp; mca_funcs-&gt;mca_set_debug_mode)</div><div class='del'>-		return mca_funcs-&gt;mca_set_debug_mode(adev, enable);</div><div class='add'>+	if (list_empty(&amp;mca_set-&gt;list))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	return -EOPNOTSUPP;</div><div class='add'>+	list_for_each_entry_safe(node, tmp, &amp;mca_set-&gt;list, node)</div><div class='add'>+		amdgpu_mca_bank_set_remove_node(mca_set, node);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry)</div><div class='add'>+void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs)</div><div class='ctx'> {</div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "Accelerator Check Architecture events logged\n");</div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n",</div><div class='del'>-		 idx, entry-&gt;regs[MCA_REG_IDX_STATUS]);</div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "aca entry[%02d].ADDR=0x%016llx\n",</div><div class='del'>-		 idx, entry-&gt;regs[MCA_REG_IDX_ADDR]);</div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "aca entry[%02d].MISC0=0x%016llx\n",</div><div class='del'>-		 idx, entry-&gt;regs[MCA_REG_IDX_MISC0]);</div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "aca entry[%02d].IPID=0x%016llx\n",</div><div class='del'>-		 idx, entry-&gt;regs[MCA_REG_IDX_IPID]);</div><div class='del'>-	dev_info(adev-&gt;dev, HW_ERR "aca entry[%02d].SYND=0x%016llx\n",</div><div class='del'>-		 idx, entry-&gt;regs[MCA_REG_IDX_SYND]);</div><div class='add'>+	struct amdgpu_mca *mca = &amp;adev-&gt;mca;</div><div class='add'>+</div><div class='add'>+	mca-&gt;mca_funcs = mca_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data)</div><div class='add'>+int amdgpu_mca_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_smuio_mcm_config_info mcm_info;</div><div class='del'>-	struct ras_err_addr err_addr = {0};</div><div class='del'>-	struct mca_bank_set mca_set;</div><div class='del'>-	struct mca_bank_node *node;</div><div class='del'>-	struct mca_bank_entry *entry;</div><div class='del'>-	uint32_t count;</div><div class='del'>-	int ret, i = 0;</div><div class='add'>+	struct amdgpu_mca *mca = &amp;adev-&gt;mca;</div><div class='add'>+	struct mca_bank_cache *mca_cache;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	amdgpu_mca_bank_set_init(&amp;mca_set);</div><div class='add'>+	atomic_set(&amp;mca-&gt;ue_update_flag, 0);</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_mca_smu_get_mca_set(adev, blk, type, &amp;mca_set);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto out_mca_release;</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(mca-&gt;mca_caches); i++) {</div><div class='add'>+		mca_cache = &amp;mca-&gt;mca_caches[i];</div><div class='add'>+		mutex_init(&amp;mca_cache-&gt;lock);</div><div class='add'>+		amdgpu_mca_bank_set_init(&amp;mca_cache-&gt;mca_set);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	list_for_each_entry(node, &amp;mca_set.list, node) {</div><div class='del'>-		entry = &amp;node-&gt;entry;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		amdgpu_mca_smu_mca_bank_dump(adev, i++, entry);</div><div class='add'>+void amdgpu_mca_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_mca *mca = &amp;adev-&gt;mca;</div><div class='add'>+	struct mca_bank_cache *mca_cache;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-		count = 0;</div><div class='del'>-		ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &amp;count);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto out_mca_release;</div><div class='add'>+	atomic_set(&amp;mca-&gt;ue_update_flag, 0);</div><div class='ctx'> </div><div class='del'>-		if (!count)</div><div class='del'>-			continue;</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(mca-&gt;mca_caches); i++) {</div><div class='add'>+		mca_cache = &amp;mca-&gt;mca_caches[i];</div><div class='add'>+		amdgpu_mca_bank_set_release(&amp;mca_cache-&gt;mca_set);</div><div class='add'>+		mutex_destroy(&amp;mca_cache-&gt;lock);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		mcm_info.socket_id = entry-&gt;info.socket_id;</div><div class='del'>-		mcm_info.die_id = entry-&gt;info.aid;</div><div class='add'>+int amdgpu_mca_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_mca_fini(adev);</div><div class='ctx'> </div><div class='del'>-		if (blk == AMDGPU_RAS_BLOCK__UMC) {</div><div class='del'>-			err_addr.err_status = entry-&gt;regs[MCA_REG_IDX_STATUS];</div><div class='del'>-			err_addr.err_ipid = entry-&gt;regs[MCA_REG_IDX_IPID];</div><div class='del'>-			err_addr.err_addr = entry-&gt;regs[MCA_REG_IDX_ADDR];</div><div class='del'>-		}</div><div class='add'>+	return amdgpu_mca_init(adev);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		if (type == AMDGPU_MCA_ERROR_TYPE_UE)</div><div class='del'>-			amdgpu_ras_error_statistic_ue_count(err_data,</div><div class='del'>-				&amp;mcm_info, &amp;err_addr, (uint64_t)count);</div><div class='del'>-		else {</div><div class='del'>-			if (amdgpu_mca_is_deferred_error(adev, entry-&gt;regs[MCA_REG_IDX_STATUS]))</div><div class='del'>-				amdgpu_ras_error_statistic_de_count(err_data,</div><div class='del'>-					&amp;mcm_info, &amp;err_addr, (uint64_t)count);</div><div class='del'>-			else</div><div class='del'>-				amdgpu_ras_error_statistic_ce_count(err_data,</div><div class='del'>-					&amp;mcm_info, &amp;err_addr, (uint64_t)count);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='ctx'> </div><div class='del'>-out_mca_release:</div><div class='del'>-	amdgpu_mca_bank_set_release(&amp;mca_set);</div><div class='add'>+	if (mca_funcs &amp;&amp; mca_funcs-&gt;mca_set_debug_mode)</div><div class='add'>+		return mca_funcs-&gt;mca_set_debug_mode(adev, enable);</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry,</div><div class='add'>+					 struct ras_query_context *qctx)</div><div class='add'>+{</div><div class='add'>+	u64 event_id = qctx ? qctx-&gt;evid.event_id : RAS_EVENT_INVALID_ID;</div><div class='add'>+</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].STATUS=0x%016llx\n",</div><div class='add'>+		      idx, entry-&gt;regs[MCA_REG_IDX_STATUS]);</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].ADDR=0x%016llx\n",</div><div class='add'>+		      idx, entry-&gt;regs[MCA_REG_IDX_ADDR]);</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].MISC0=0x%016llx\n",</div><div class='add'>+		      idx, entry-&gt;regs[MCA_REG_IDX_MISC0]);</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].IPID=0x%016llx\n",</div><div class='add'>+		      idx, entry-&gt;regs[MCA_REG_IDX_IPID]);</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, HW_ERR "aca entry[%02d].SYND=0x%016llx\n",</div><div class='add'>+		      idx, entry-&gt;regs[MCA_REG_IDX_SYND]);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)</div><div class='add'>+static int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)</div><div class='ctx'> {</div><div class='ctx'> 	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -296,103 +302,211 @@ int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_m</div><div class='ctx'> 	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-					    enum amdgpu_mca_error_type type, uint32_t *total)</div><div class='add'>+static int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,</div><div class='add'>+					int idx, struct mca_bank_entry *entry)</div><div class='ctx'> {</div><div class='ctx'> 	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='del'>-	struct mca_bank_set mca_set;</div><div class='del'>-	struct mca_bank_node *node;</div><div class='del'>-	struct mca_bank_entry *entry;</div><div class='del'>-	uint32_t count;</div><div class='del'>-	int ret;</div><div class='add'>+	int count;</div><div class='add'>+</div><div class='add'>+	if (!mca_funcs || !mca_funcs-&gt;mca_get_mca_entry)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!total)</div><div class='add'>+	switch (type) {</div><div class='add'>+	case AMDGPU_MCA_ERROR_TYPE_UE:</div><div class='add'>+		count = mca_funcs-&gt;max_ue_count;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_MCA_ERROR_TYPE_CE:</div><div class='add'>+		count = mca_funcs-&gt;max_ce_count;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (!mca_funcs)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='add'>+	if (idx &gt;= count)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (!mca_funcs-&gt;mca_get_ras_mca_set || !mca_funcs-&gt;mca_get_valid_mca_count)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='add'>+	return mca_funcs-&gt;mca_get_mca_entry(adev, type, idx, entry);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	amdgpu_mca_bank_set_init(&amp;mca_set);</div><div class='add'>+static bool amdgpu_mca_bank_should_update(struct amdgpu_device *adev, enum amdgpu_mca_error_type type)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_mca *mca = &amp;adev-&gt;mca;</div><div class='add'>+	bool ret = true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Because the UE Valid MCA count will only be cleared after reset,</div><div class='add'>+	 * in order to avoid repeated counting of the error count,</div><div class='add'>+	 * the aca bank is only updated once during the gpu recovery stage.</div><div class='add'>+	 */</div><div class='add'>+	if (type == AMDGPU_MCA_ERROR_TYPE_UE) {</div><div class='add'>+		if (amdgpu_ras_intr_triggered())</div><div class='add'>+			ret = atomic_cmpxchg(&amp;mca-&gt;ue_update_flag, 0, 1) == 0;</div><div class='add'>+		else</div><div class='add'>+			atomic_set(&amp;mca-&gt;ue_update_flag, 0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	ret = mca_funcs-&gt;mca_get_ras_mca_set(adev, blk, type, &amp;mca_set);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err_mca_set_release;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	*total = 0;</div><div class='del'>-	list_for_each_entry(node, &amp;mca_set.list, node) {</div><div class='del'>-		entry = &amp;node-&gt;entry;</div><div class='add'>+static bool amdgpu_mca_bank_should_dump(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,</div><div class='add'>+					struct mca_bank_entry *entry)</div><div class='add'>+{</div><div class='add'>+	bool ret;</div><div class='ctx'> </div><div class='del'>-		count = 0;</div><div class='del'>-		ret = mca_funcs-&gt;mca_parse_mca_error_count(adev, blk, type, entry, &amp;count);</div><div class='add'>+	switch (type) {</div><div class='add'>+	case AMDGPU_MCA_ERROR_TYPE_CE:</div><div class='add'>+		ret = amdgpu_mca_is_deferred_error(adev, entry-&gt;regs[MCA_REG_IDX_STATUS]);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_MCA_ERROR_TYPE_UE:</div><div class='add'>+	default:</div><div class='add'>+		ret = true;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set,</div><div class='add'>+				      struct ras_query_context *qctx)</div><div class='add'>+{</div><div class='add'>+	struct mca_bank_entry entry;</div><div class='add'>+	uint32_t count = 0, i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!mca_set)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_mca_bank_should_update(adev, type))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &amp;count);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		memset(&amp;entry, 0, sizeof(entry));</div><div class='add'>+		ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, &amp;entry);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			goto err_mca_set_release;</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='del'>-		*total += count;</div><div class='del'>-	}</div><div class='add'>+		amdgpu_mca_bank_set_add_entry(mca_set, &amp;entry);</div><div class='ctx'> </div><div class='del'>-err_mca_set_release:</div><div class='del'>-	amdgpu_mca_bank_set_release(&amp;mca_set);</div><div class='add'>+		if (amdgpu_mca_bank_should_dump(adev, type, &amp;entry))</div><div class='add'>+			amdgpu_mca_smu_mca_bank_dump(adev, i, &amp;entry, qctx);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-					 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)</div><div class='add'>+static int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='add'>+						enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)</div><div class='ctx'> {</div><div class='ctx'> 	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='add'>+</div><div class='ctx'> 	if (!count || !entry)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (!mca_funcs || !mca_funcs-&gt;mca_parse_mca_error_count)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	return mca_funcs-&gt;mca_parse_mca_error_count(adev, blk, type, entry, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-			       enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set)</div><div class='add'>+static int amdgpu_mca_dispatch_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,</div><div class='add'>+				       struct mca_bank_set *mca_set, struct ras_err_data *err_data)</div><div class='ctx'> {</div><div class='del'>-	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='add'>+	struct amdgpu_smuio_mcm_config_info mcm_info;</div><div class='add'>+	struct mca_bank_node *node, *tmp;</div><div class='add'>+	struct mca_bank_entry *entry;</div><div class='add'>+	uint32_t count;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!mca_set)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (!mca_funcs || !mca_funcs-&gt;mca_get_ras_mca_set)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='add'>+	if (!mca_set-&gt;nr_entries)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(node, tmp, &amp;mca_set-&gt;list, node) {</div><div class='add'>+		entry = &amp;node-&gt;entry;</div><div class='ctx'> </div><div class='del'>-	WARN_ON(!list_empty(&amp;mca_set-&gt;list));</div><div class='add'>+		count = 0;</div><div class='add'>+		ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &amp;count);</div><div class='add'>+		if (ret &amp;&amp; ret != -EOPNOTSUPP)</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='del'>-	return mca_funcs-&gt;mca_get_ras_mca_set(adev, blk, type, mca_set);</div><div class='add'>+		if (!count)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		memset(&amp;mcm_info, 0, sizeof(mcm_info));</div><div class='add'>+</div><div class='add'>+		mcm_info.socket_id = entry-&gt;info.socket_id;</div><div class='add'>+		mcm_info.die_id = entry-&gt;info.aid;</div><div class='add'>+</div><div class='add'>+		if (type == AMDGPU_MCA_ERROR_TYPE_UE) {</div><div class='add'>+			amdgpu_ras_error_statistic_ue_count(err_data,</div><div class='add'>+							    &amp;mcm_info, (uint64_t)count);</div><div class='add'>+		} else {</div><div class='add'>+			if (amdgpu_mca_is_deferred_error(adev, entry-&gt;regs[MCA_REG_IDX_STATUS]))</div><div class='add'>+				amdgpu_ras_error_statistic_de_count(err_data,</div><div class='add'>+								    &amp;mcm_info, (uint64_t)count);</div><div class='add'>+			else</div><div class='add'>+				amdgpu_ras_error_statistic_ce_count(err_data,</div><div class='add'>+								    &amp;mcm_info, (uint64_t)count);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		amdgpu_mca_bank_set_remove_node(mca_set, node);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,</div><div class='del'>-				 int idx, struct mca_bank_entry *entry)</div><div class='add'>+static int amdgpu_mca_add_mca_set_to_cache(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, struct mca_bank_set *new)</div><div class='ctx'> {</div><div class='del'>-	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='del'>-	int count;</div><div class='add'>+	struct mca_bank_cache *mca_cache = &amp;adev-&gt;mca.mca_caches[type];</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!mca_funcs || !mca_funcs-&gt;mca_get_mca_entry)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='add'>+	mutex_lock(&amp;mca_cache-&gt;lock);</div><div class='add'>+	ret = amdgpu_mca_bank_set_merge(&amp;mca_cache-&gt;mca_set, new);</div><div class='add'>+	mutex_unlock(&amp;mca_cache-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	switch (type) {</div><div class='del'>-	case AMDGPU_MCA_ERROR_TYPE_UE:</div><div class='del'>-		count = mca_funcs-&gt;max_ue_count;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_MCA_ERROR_TYPE_CE:</div><div class='del'>-		count = mca_funcs-&gt;max_ce_count;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,</div><div class='add'>+				 struct ras_err_data *err_data, struct ras_query_context *qctx)</div><div class='add'>+{</div><div class='add'>+	struct mca_bank_set mca_set;</div><div class='add'>+	struct mca_bank_cache *mca_cache = &amp;adev-&gt;mca.mca_caches[type];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	amdgpu_mca_bank_set_init(&amp;mca_set);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_mca_smu_get_mca_set(adev, type, &amp;mca_set, qctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_mca_release;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_mca_dispatch_mca_set(adev, blk, type, &amp;mca_set, err_data);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_mca_release;</div><div class='add'>+</div><div class='add'>+	/* add remain mca bank to mca cache */</div><div class='add'>+	if (mca_set.nr_entries) {</div><div class='add'>+		ret = amdgpu_mca_add_mca_set_to_cache(adev, type, &amp;mca_set);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out_mca_release;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (idx &gt;= count)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	/* dispatch mca set again if mca cache has valid data */</div><div class='add'>+	mutex_lock(&amp;mca_cache-&gt;lock);</div><div class='add'>+	if (mca_cache-&gt;mca_set.nr_entries)</div><div class='add'>+		ret = amdgpu_mca_dispatch_mca_set(adev, blk, type, &amp;mca_cache-&gt;mca_set, err_data);</div><div class='add'>+	mutex_unlock(&amp;mca_cache-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	return mca_funcs-&gt;mca_get_mca_entry(adev, type, idx, entry);</div><div class='add'>+out_mca_release:</div><div class='add'>+	amdgpu_mca_bank_set_release(&amp;mca_set);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='hunk'>@@ -433,36 +547,32 @@ static void mca_dump_entry(struct seq_file *m, struct mca_bank_entry *entry)</div><div class='ctx'> static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)m-&gt;private;</div><div class='del'>-	struct mca_bank_entry *entry;</div><div class='del'>-	uint32_t count = 0;</div><div class='del'>-	int i, ret;</div><div class='add'>+	struct mca_bank_node *node;</div><div class='add'>+	struct mca_bank_set mca_set;</div><div class='add'>+	struct ras_query_context qctx;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &amp;count);</div><div class='add'>+	amdgpu_mca_bank_set_init(&amp;mca_set);</div><div class='add'>+</div><div class='add'>+	qctx.evid.event_id = RAS_EVENT_INVALID_ID;</div><div class='add'>+	ret = amdgpu_mca_smu_get_mca_set(adev, type, &amp;mca_set, &amp;qctx);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_free_mca_set;</div><div class='ctx'> </div><div class='ctx'> 	seq_printf(m, "amdgpu smu %s valid mca count: %d\n",</div><div class='del'>-		   type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", count);</div><div class='add'>+		   type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", mca_set.nr_entries);</div><div class='ctx'> </div><div class='del'>-	if (!count)</div><div class='del'>-		return 0;</div><div class='add'>+	if (!mca_set.nr_entries)</div><div class='add'>+		goto err_free_mca_set;</div><div class='ctx'> </div><div class='del'>-	entry = kmalloc(sizeof(*entry), GFP_KERNEL);</div><div class='del'>-	if (!entry)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	list_for_each_entry(node, &amp;mca_set.list, node)</div><div class='add'>+		mca_dump_entry(m, &amp;node-&gt;entry);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; count; i++) {</div><div class='del'>-		memset(entry, 0, sizeof(*entry));</div><div class='del'>-</div><div class='del'>-		ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, entry);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err_free_entry;</div><div class='add'>+	/* add mca bank to mca bank cache */</div><div class='add'>+	ret = amdgpu_mca_add_mca_set_to_cache(adev, type, &amp;mca_set);</div><div class='ctx'> </div><div class='del'>-		mca_dump_entry(m, entry);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-err_free_entry:</div><div class='del'>-	kfree(entry);</div><div class='add'>+err_free_mca_set:</div><div class='add'>+	amdgpu_mca_bank_set_release(&amp;mca_set);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -509,7 +619,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_se</div><div class='ctx'> void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)</div><div class='ctx'> {</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='del'>-	if (!root || amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6))</div><div class='add'>+	if (!root)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_file("mca_debug_mode", 0200, root, adev, &amp;mca_debug_mode_fops);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h<br/>index b964110ed1e0..e80323ff90c1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h</a></div><div class='hunk'>@@ -77,11 +77,23 @@ struct amdgpu_mca_ras {</div><div class='ctx'> 	struct amdgpu_mca_ras_block *ras;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mca_bank_set {</div><div class='add'>+	int nr_entries;</div><div class='add'>+	struct list_head list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mca_bank_cache {</div><div class='add'>+	struct mca_bank_set mca_set;</div><div class='add'>+	struct mutex lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_mca {</div><div class='ctx'> 	struct amdgpu_mca_ras mp0;</div><div class='ctx'> 	struct amdgpu_mca_ras mp1;</div><div class='ctx'> 	struct amdgpu_mca_ras mpio;</div><div class='ctx'> 	const struct amdgpu_mca_smu_funcs *mca_funcs;</div><div class='add'>+	struct mca_bank_cache mca_caches[AMDGPU_MCA_ERROR_TYPE_DE];</div><div class='add'>+	atomic_t ue_update_flag;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum mca_reg_idx {</div><div class='hunk'>@@ -113,17 +125,10 @@ struct mca_bank_node {</div><div class='ctx'> 	struct list_head node;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct mca_bank_set {</div><div class='del'>-	int nr_entries;</div><div class='del'>-	struct list_head list;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct amdgpu_mca_smu_funcs {</div><div class='ctx'> 	int max_ue_count;</div><div class='ctx'> 	int max_ce_count;</div><div class='ctx'> 	int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);</div><div class='del'>-	int (*mca_get_ras_mca_set)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,</div><div class='del'>-				   struct mca_bank_set *mca_set);</div><div class='ctx'> 	int (*mca_parse_mca_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,</div><div class='ctx'> 					 struct mca_bank_entry *entry, uint32_t *count);</div><div class='ctx'> 	int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,</div><div class='hunk'>@@ -151,24 +156,14 @@ int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs);</div><div class='add'>+int amdgpu_mca_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_mca_fini(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_mca_reset(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);</div><div class='del'>-int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count);</div><div class='ctx'> int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='ctx'> 					   enum amdgpu_mca_error_type type, uint32_t *total);</div><div class='del'>-int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-				   enum amdgpu_mca_error_type type, uint32_t *count);</div><div class='del'>-int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-					 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);</div><div class='del'>-int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-			       enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set);</div><div class='del'>-int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,</div><div class='del'>-				 int idx, struct mca_bank_entry *entry);</div><div class='del'>-</div><div class='ctx'> void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);</div><div class='del'>-</div><div class='del'>-void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set);</div><div class='del'>-int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry);</div><div class='del'>-void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set);</div><div class='del'>-int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data);</div><div class='add'>+int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,</div><div class='add'>+				 struct ras_err_data *err_data, struct ras_query_context *qctx);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c<br/>index a98e03e0a51f..9c182ce501af 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c</a></div><div class='hunk'>@@ -39,44 +39,6 @@ int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev)</div><div class='ctx'> 		       PAGE_SIZE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_mes_kernel_doorbell_get(struct amdgpu_device *adev,</div><div class='del'>-					 struct amdgpu_mes_process *process,</div><div class='del'>-					 int ip_type, uint64_t *doorbell_index)</div><div class='del'>-{</div><div class='del'>-	unsigned int offset, found;</div><div class='del'>-	struct amdgpu_mes *mes = &amp;adev-&gt;mes;</div><div class='del'>-</div><div class='del'>-	if (ip_type == AMDGPU_RING_TYPE_SDMA)</div><div class='del'>-		offset = adev-&gt;doorbell_index.sdma_engine[0];</div><div class='del'>-	else</div><div class='del'>-		offset = 0;</div><div class='del'>-</div><div class='del'>-	found = find_next_zero_bit(mes-&gt;doorbell_bitmap, mes-&gt;num_mes_dbs, offset);</div><div class='del'>-	if (found &gt;= mes-&gt;num_mes_dbs) {</div><div class='del'>-		DRM_WARN("No doorbell available\n");</div><div class='del'>-		return -ENOSPC;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	set_bit(found, mes-&gt;doorbell_bitmap);</div><div class='del'>-</div><div class='del'>-	/* Get the absolute doorbell index on BAR */</div><div class='del'>-	*doorbell_index = mes-&gt;db_start_dw_offset + found * 2;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void amdgpu_mes_kernel_doorbell_free(struct amdgpu_device *adev,</div><div class='del'>-					   struct amdgpu_mes_process *process,</div><div class='del'>-					   uint32_t doorbell_index)</div><div class='del'>-{</div><div class='del'>-	unsigned int old, rel_index;</div><div class='del'>-	struct amdgpu_mes *mes = &amp;adev-&gt;mes;</div><div class='del'>-</div><div class='del'>-	/* Find the relative index of the doorbell in this object */</div><div class='del'>-	rel_index = (doorbell_index - mes-&gt;db_start_dw_offset) / 2;</div><div class='del'>-	old = test_and_clear_bit(rel_index, mes-&gt;doorbell_bitmap);</div><div class='del'>-	WARN_ON(!old);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -85,7 +47,7 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* Bitmap for dynamic allocation of kernel doorbells */</div><div class='ctx'> 	mes-&gt;doorbell_bitmap = bitmap_zalloc(PAGE_SIZE / sizeof(u32), GFP_KERNEL);</div><div class='ctx'> 	if (!mes-&gt;doorbell_bitmap) {</div><div class='del'>-		DRM_ERROR("Failed to allocate MES doorbell bitmap\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to allocate MES doorbell bitmap\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -102,8 +64,11 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+	if (!amdgpu_mes_log_enable)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_kernel(adev, adev-&gt;mes.event_log_size, PAGE_SIZE,</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_VRAM,</div><div class='ctx'> 				    &amp;adev-&gt;mes.event_log_gpu_obj,</div><div class='ctx'> 				    &amp;adev-&gt;mes.event_log_gpu_addr,</div><div class='ctx'> 				    &amp;adev-&gt;mes.event_log_cpu_addr);</div><div class='hunk'>@@ -112,7 +77,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	memset(adev-&gt;mes.event_log_cpu_addr, 0, PAGE_SIZE);</div><div class='add'>+	memset(adev-&gt;mes.event_log_cpu_addr, 0, adev-&gt;mes.event_log_size);</div><div class='ctx'> </div><div class='ctx'> 	return  0;</div><div class='ctx'> </div><div class='hunk'>@@ -125,7 +90,7 @@ static void amdgpu_mes_doorbell_free(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> int amdgpu_mes_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, r;</div><div class='add'>+	int i, r, num_pipes;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mes.adev = adev;</div><div class='ctx'> </div><div class='hunk'>@@ -134,69 +99,89 @@ int amdgpu_mes_init(struct amdgpu_device *adev)</div><div class='ctx'> 	idr_init(&amp;adev-&gt;mes.queue_id_idr);</div><div class='ctx'> 	ida_init(&amp;adev-&gt;mes.doorbell_ida);</div><div class='ctx'> 	spin_lock_init(&amp;adev-&gt;mes.queue_id_lock);</div><div class='del'>-	spin_lock_init(&amp;adev-&gt;mes.ring_lock);</div><div class='ctx'> 	mutex_init(&amp;adev-&gt;mes.mutex_hidden);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;</div><div class='del'>-	adev-&gt;mes.vmid_mask_mmhub = 0xffffff00;</div><div class='del'>-	adev-&gt;mes.vmid_mask_gfxhub = 0xffffff00;</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_MES_PIPES; i++)</div><div class='add'>+		spin_lock_init(&amp;adev-&gt;mes.ring_lock[i]);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {</div><div class='del'>-		/* use only 1st MEC pipes */</div><div class='del'>-		if (i &gt;= 4)</div><div class='del'>-			continue;</div><div class='del'>-		adev-&gt;mes.compute_hqd_mask[i] = 0xc;</div><div class='del'>-	}</div><div class='add'>+	adev-&gt;mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;</div><div class='add'>+	adev-&gt;mes.vmid_mask_mmhub = 0xFF00;</div><div class='add'>+	adev-&gt;mes.vmid_mask_gfxhub = adev-&gt;gfx.disable_kq ? 0xFFFE : 0xFF00;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MES_MAX_GFX_PIPES; i++)</div><div class='del'>-		adev-&gt;mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;</div><div class='add'>+	num_pipes = adev-&gt;gfx.me.num_pipe_per_me * adev-&gt;gfx.me.num_me;</div><div class='add'>+	if (num_pipes &gt; AMDGPU_MES_MAX_GFX_PIPES)</div><div class='add'>+		dev_warn(adev-&gt;dev, "more gfx pipes than supported by MES! (%d vs %d)\n",</div><div class='add'>+			 num_pipes, AMDGPU_MES_MAX_GFX_PIPES);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MES_MAX_SDMA_PIPES; i++) {</div><div class='del'>-		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) &lt;</div><div class='del'>-		    IP_VERSION(6, 0, 0))</div><div class='del'>-			adev-&gt;mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;</div><div class='del'>-		/* zero sdma_hqd_mask for non-existent engine */</div><div class='del'>-		else if (adev-&gt;sdma.num_instances == 1)</div><div class='del'>-			adev-&gt;mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MES_MAX_GFX_PIPES; i++) {</div><div class='add'>+		if (i &gt;= num_pipes)</div><div class='add'>+			break;</div><div class='add'>+		if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;=</div><div class='add'>+		    IP_VERSION(12, 0, 0))</div><div class='add'>+			/*</div><div class='add'>+			 * GFX V12 has only one GFX pipe, but 8 queues in it.</div><div class='add'>+			 * GFX pipe 0 queue 0 is being used by Kernel queue.</div><div class='add'>+			 * Set GFX pipe 0 queue 1-7 for MES scheduling</div><div class='add'>+			 * mask = 1111 1110b</div><div class='add'>+			 */</div><div class='add'>+			adev-&gt;mes.gfx_hqd_mask[i] = adev-&gt;gfx.disable_kq ? 0xFF : 0xFE;</div><div class='ctx'> 		else</div><div class='del'>-			adev-&gt;mes.sdma_hqd_mask[i] = 0xfc;</div><div class='add'>+			/*</div><div class='add'>+			 * GFX pipe 0 queue 0 is being used by Kernel queue.</div><div class='add'>+			 * Set GFX pipe 0 queue 1 for MES scheduling</div><div class='add'>+			 * mask = 10b</div><div class='add'>+			 */</div><div class='add'>+			adev-&gt;mes.gfx_hqd_mask[i] = adev-&gt;gfx.disable_kq ? 0x3 : 0x2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_device_wb_get(adev, &amp;adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			"(%d) ring trail_fence_offs wb alloc failed\n", r);</div><div class='del'>-		goto error_ids;</div><div class='add'>+	num_pipes = adev-&gt;gfx.mec.num_pipe_per_mec * adev-&gt;gfx.mec.num_mec;</div><div class='add'>+	if (num_pipes &gt; AMDGPU_MES_MAX_COMPUTE_PIPES)</div><div class='add'>+		dev_warn(adev-&gt;dev, "more compute pipes than supported by MES! (%d vs %d)\n",</div><div class='add'>+			 num_pipes, AMDGPU_MES_MAX_COMPUTE_PIPES);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {</div><div class='add'>+		if (i &gt;= num_pipes)</div><div class='add'>+			break;</div><div class='add'>+		adev-&gt;mes.compute_hqd_mask[i] = adev-&gt;gfx.disable_kq ? 0xF : 0xC;</div><div class='ctx'> 	}</div><div class='del'>-	adev-&gt;mes.sch_ctx_gpu_addr =</div><div class='del'>-		adev-&gt;wb.gpu_addr + (adev-&gt;mes.sch_ctx_offs * 4);</div><div class='del'>-	adev-&gt;mes.sch_ctx_ptr =</div><div class='del'>-		(uint64_t *)&amp;adev-&gt;wb.wb[adev-&gt;mes.sch_ctx_offs];</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_device_wb_get(adev, &amp;adev-&gt;mes.query_status_fence_offs);</div><div class='del'>-	if (r) {</div><div class='del'>-		amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			"(%d) query_status_fence_offs wb alloc failed\n", r);</div><div class='del'>-		goto error_ids;</div><div class='add'>+	num_pipes = adev-&gt;sdma.num_instances;</div><div class='add'>+	if (num_pipes &gt; AMDGPU_MES_MAX_SDMA_PIPES)</div><div class='add'>+		dev_warn(adev-&gt;dev, "more SDMA pipes than supported by MES! (%d vs %d)\n",</div><div class='add'>+			 num_pipes, AMDGPU_MES_MAX_SDMA_PIPES);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MES_MAX_SDMA_PIPES; i++) {</div><div class='add'>+		if (i &gt;= num_pipes)</div><div class='add'>+			break;</div><div class='add'>+		adev-&gt;mes.sdma_hqd_mask[i] = 0xfc;</div><div class='ctx'> 	}</div><div class='del'>-	adev-&gt;mes.query_status_fence_gpu_addr =</div><div class='del'>-		adev-&gt;wb.gpu_addr + (adev-&gt;mes.query_status_fence_offs * 4);</div><div class='del'>-	adev-&gt;mes.query_status_fence_ptr =</div><div class='del'>-		(uint64_t *)&amp;adev-&gt;wb.wb[adev-&gt;mes.query_status_fence_offs];</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_device_wb_get(adev, &amp;adev-&gt;mes.read_val_offs);</div><div class='del'>-	if (r) {</div><div class='del'>-		amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-		amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			"(%d) read_val_offs alloc failed\n", r);</div><div class='del'>-		goto error_ids;</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_MES_PIPES; i++) {</div><div class='add'>+		r = amdgpu_device_wb_get(adev, &amp;adev-&gt;mes.sch_ctx_offs[i]);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"(%d) ring trail_fence_offs wb alloc failed\n",</div><div class='add'>+				r);</div><div class='add'>+			goto error;</div><div class='add'>+		}</div><div class='add'>+		adev-&gt;mes.sch_ctx_gpu_addr[i] =</div><div class='add'>+			adev-&gt;wb.gpu_addr + (adev-&gt;mes.sch_ctx_offs[i] * 4);</div><div class='add'>+		adev-&gt;mes.sch_ctx_ptr[i] =</div><div class='add'>+			(uint64_t *)&amp;adev-&gt;wb.wb[adev-&gt;mes.sch_ctx_offs[i]];</div><div class='add'>+</div><div class='add'>+		r = amdgpu_device_wb_get(adev,</div><div class='add'>+				 &amp;adev-&gt;mes.query_status_fence_offs[i]);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+			      "(%d) query_status_fence_offs wb alloc failed\n",</div><div class='add'>+			      r);</div><div class='add'>+			goto error;</div><div class='add'>+		}</div><div class='add'>+		adev-&gt;mes.query_status_fence_gpu_addr[i] = adev-&gt;wb.gpu_addr +</div><div class='add'>+			(adev-&gt;mes.query_status_fence_offs[i] * 4);</div><div class='add'>+		adev-&gt;mes.query_status_fence_ptr[i] =</div><div class='add'>+			(uint64_t *)&amp;adev-&gt;wb.wb[adev-&gt;mes.query_status_fence_offs[i]];</div><div class='ctx'> 	}</div><div class='del'>-	adev-&gt;mes.read_val_gpu_addr =</div><div class='del'>-		adev-&gt;wb.gpu_addr + (adev-&gt;mes.read_val_offs * 4);</div><div class='del'>-	adev-&gt;mes.read_val_ptr =</div><div class='del'>-		(uint32_t *)&amp;adev-&gt;wb.wb[adev-&gt;mes.read_val_offs];</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_mes_doorbell_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -206,15 +191,33 @@ int amdgpu_mes_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error_doorbell;</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;mes.hung_queue_db_array_size) {</div><div class='add'>+		r = amdgpu_bo_create_kernel(adev,</div><div class='add'>+					    adev-&gt;mes.hung_queue_db_array_size * sizeof(u32),</div><div class='add'>+					    PAGE_SIZE,</div><div class='add'>+					    AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+					    &amp;adev-&gt;mes.hung_queue_db_array_gpu_obj,</div><div class='add'>+					    &amp;adev-&gt;mes.hung_queue_db_array_gpu_addr,</div><div class='add'>+					    &amp;adev-&gt;mes.hung_queue_db_array_cpu_addr);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "failed to create MES hung db array buffer (%d)", r);</div><div class='add'>+			goto error_doorbell;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> error_doorbell:</div><div class='ctx'> 	amdgpu_mes_doorbell_free(adev);</div><div class='ctx'> error:</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.read_val_offs);</div><div class='del'>-error_ids:</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_MES_PIPES; i++) {</div><div class='add'>+		if (adev-&gt;mes.sch_ctx_ptr[i])</div><div class='add'>+			amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs[i]);</div><div class='add'>+		if (adev-&gt;mes.query_status_fence_ptr[i])</div><div class='add'>+			amdgpu_device_wb_free(adev,</div><div class='add'>+				      adev-&gt;mes.query_status_fence_offs[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	idr_destroy(&amp;adev-&gt;mes.pasid_idr);</div><div class='ctx'> 	idr_destroy(&amp;adev-&gt;mes.gang_id_idr);</div><div class='ctx'> 	idr_destroy(&amp;adev-&gt;mes.queue_id_idr);</div><div class='hunk'>@@ -225,13 +228,24 @@ error_ids:</div><div class='ctx'> </div><div class='ctx'> void amdgpu_mes_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.hung_queue_db_array_gpu_obj,</div><div class='add'>+			      &amp;adev-&gt;mes.hung_queue_db_array_gpu_addr,</div><div class='add'>+			      &amp;adev-&gt;mes.hung_queue_db_array_cpu_addr);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.event_log_gpu_obj,</div><div class='ctx'> 			      &amp;adev-&gt;mes.event_log_gpu_addr,</div><div class='ctx'> 			      &amp;adev-&gt;mes.event_log_cpu_addr);</div><div class='ctx'> </div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.read_val_offs);</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_MES_PIPES; i++) {</div><div class='add'>+		if (adev-&gt;mes.sch_ctx_ptr[i])</div><div class='add'>+			amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs[i]);</div><div class='add'>+		if (adev-&gt;mes.query_status_fence_ptr[i])</div><div class='add'>+			amdgpu_device_wb_free(adev,</div><div class='add'>+				      adev-&gt;mes.query_status_fence_offs[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	amdgpu_mes_doorbell_free(adev);</div><div class='ctx'> </div><div class='ctx'> 	idr_destroy(&amp;adev-&gt;mes.pasid_idr);</div><div class='hunk'>@@ -241,559 +255,183 @@ void amdgpu_mes_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	mutex_destroy(&amp;adev-&gt;mes.mutex_hidden);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_mes_queue_free_mqd(struct amdgpu_mes_queue *q)</div><div class='del'>-{</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;q-&gt;mqd_obj,</div><div class='del'>-			      &amp;q-&gt;mqd_gpu_addr,</div><div class='del'>-			      &amp;q-&gt;mqd_cpu_ptr);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,</div><div class='del'>-			      struct amdgpu_vm *vm)</div><div class='add'>+int amdgpu_mes_suspend(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_mes_process *process;</div><div class='add'>+	struct mes_suspend_gang_input input;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* allocate the mes process buffer */</div><div class='del'>-	process = kzalloc(sizeof(struct amdgpu_mes_process), GFP_KERNEL);</div><div class='del'>-	if (!process) {</div><div class='del'>-		DRM_ERROR("no more memory to create mes process\n");</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='add'>+	if (!amdgpu_mes_suspend_resume_all_supported(adev))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	/* allocate the process context bo and map it */</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, AMDGPU_MES_PROC_CTX_SIZE, PAGE_SIZE,</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;process-&gt;proc_ctx_bo,</div><div class='del'>-				    &amp;process-&gt;proc_ctx_gpu_addr,</div><div class='del'>-				    &amp;process-&gt;proc_ctx_cpu_ptr);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to allocate process context bo\n");</div><div class='del'>-		goto clean_up_memory;</div><div class='del'>-	}</div><div class='del'>-	memset(process-&gt;proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);</div><div class='add'>+	memset(&amp;input, 0x0, sizeof(struct mes_suspend_gang_input));</div><div class='add'>+	input.suspend_all_gangs = 1;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='ctx'> 	 * lock dependencies.</div><div class='ctx'> 	 */</div><div class='ctx'> 	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	/* add the mes process to idr list */</div><div class='del'>-	r = idr_alloc(&amp;adev-&gt;mes.pasid_idr, process, pasid, pasid + 1,</div><div class='del'>-		      GFP_KERNEL);</div><div class='del'>-	if (r &lt; 0) {</div><div class='del'>-		DRM_ERROR("failed to lock pasid=%d\n", pasid);</div><div class='del'>-		goto clean_up_ctx;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	INIT_LIST_HEAD(&amp;process-&gt;gang_list);</div><div class='del'>-	process-&gt;vm = vm;</div><div class='del'>-	process-&gt;pasid = pasid;</div><div class='del'>-	process-&gt;process_quantum = adev-&gt;mes.default_process_quantum;</div><div class='del'>-	process-&gt;pd_gpu_addr = amdgpu_bo_gpu_offset(vm-&gt;root.bo);</div><div class='del'>-</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;suspend_gang(&amp;adev-&gt;mes, &amp;input);</div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	return 0;</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to suspend all gangs");</div><div class='ctx'> </div><div class='del'>-clean_up_ctx:</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;process-&gt;proc_ctx_bo,</div><div class='del'>-			      &amp;process-&gt;proc_ctx_gpu_addr,</div><div class='del'>-			      &amp;process-&gt;proc_ctx_cpu_ptr);</div><div class='del'>-clean_up_memory:</div><div class='del'>-	kfree(process);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_mes_process *process;</div><div class='del'>-	struct amdgpu_mes_gang *gang, *tmp1;</div><div class='del'>-	struct amdgpu_mes_queue *queue, *tmp2;</div><div class='del'>-	struct mes_remove_queue_input queue_input;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='del'>-	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	process = idr_find(&amp;adev-&gt;mes.pasid_idr, pasid);</div><div class='del'>-	if (!process) {</div><div class='del'>-		DRM_WARN("pasid %d doesn't exist\n", pasid);</div><div class='del'>-		amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Remove all queues from hardware */</div><div class='del'>-	list_for_each_entry_safe(gang, tmp1, &amp;process-&gt;gang_list, list) {</div><div class='del'>-		list_for_each_entry_safe(queue, tmp2, &amp;gang-&gt;queue_list, list) {</div><div class='del'>-			spin_lock_irqsave(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-			idr_remove(&amp;adev-&gt;mes.queue_id_idr, queue-&gt;queue_id);</div><div class='del'>-			spin_unlock_irqrestore(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-</div><div class='del'>-			queue_input.doorbell_offset = queue-&gt;doorbell_off;</div><div class='del'>-			queue_input.gang_context_addr = gang-&gt;gang_ctx_gpu_addr;</div><div class='del'>-</div><div class='del'>-			r = adev-&gt;mes.funcs-&gt;remove_hw_queue(&amp;adev-&gt;mes,</div><div class='del'>-							     &amp;queue_input);</div><div class='del'>-			if (r)</div><div class='del'>-				DRM_WARN("failed to remove hardware queue\n");</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		idr_remove(&amp;adev-&gt;mes.gang_id_idr, gang-&gt;gang_id);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	idr_remove(&amp;adev-&gt;mes.pasid_idr, pasid);</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	/* free all memory allocated by the process */</div><div class='del'>-	list_for_each_entry_safe(gang, tmp1, &amp;process-&gt;gang_list, list) {</div><div class='del'>-		/* free all queues in the gang */</div><div class='del'>-		list_for_each_entry_safe(queue, tmp2, &amp;gang-&gt;queue_list, list) {</div><div class='del'>-			amdgpu_mes_queue_free_mqd(queue);</div><div class='del'>-			list_del(&amp;queue-&gt;list);</div><div class='del'>-			kfree(queue);</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_free_kernel(&amp;gang-&gt;gang_ctx_bo,</div><div class='del'>-				      &amp;gang-&gt;gang_ctx_gpu_addr,</div><div class='del'>-				      &amp;gang-&gt;gang_ctx_cpu_ptr);</div><div class='del'>-		list_del(&amp;gang-&gt;list);</div><div class='del'>-		kfree(gang);</div><div class='del'>-</div><div class='del'>-	}</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;process-&gt;proc_ctx_bo,</div><div class='del'>-			      &amp;process-&gt;proc_ctx_gpu_addr,</div><div class='del'>-			      &amp;process-&gt;proc_ctx_cpu_ptr);</div><div class='del'>-	kfree(process);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,</div><div class='del'>-			struct amdgpu_mes_gang_properties *gprops,</div><div class='del'>-			int *gang_id)</div><div class='add'>+int amdgpu_mes_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_mes_process *process;</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='add'>+	struct mes_resume_gang_input input;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* allocate the mes gang buffer */</div><div class='del'>-	gang = kzalloc(sizeof(struct amdgpu_mes_gang), GFP_KERNEL);</div><div class='del'>-	if (!gang) {</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='add'>+	if (!amdgpu_mes_suspend_resume_all_supported(adev))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	/* allocate the gang context bo and map it to cpu space */</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, AMDGPU_MES_GANG_CTX_SIZE, PAGE_SIZE,</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;gang-&gt;gang_ctx_bo,</div><div class='del'>-				    &amp;gang-&gt;gang_ctx_gpu_addr,</div><div class='del'>-				    &amp;gang-&gt;gang_ctx_cpu_ptr);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to allocate process context bo\n");</div><div class='del'>-		goto clean_up_mem;</div><div class='del'>-	}</div><div class='del'>-	memset(gang-&gt;gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);</div><div class='add'>+	memset(&amp;input, 0x0, sizeof(struct mes_resume_gang_input));</div><div class='add'>+	input.resume_all_gangs = 1;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='ctx'> 	 * lock dependencies.</div><div class='ctx'> 	 */</div><div class='ctx'> 	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	process = idr_find(&amp;adev-&gt;mes.pasid_idr, pasid);</div><div class='del'>-	if (!process) {</div><div class='del'>-		DRM_ERROR("pasid %d doesn't exist\n", pasid);</div><div class='del'>-		r = -EINVAL;</div><div class='del'>-		goto clean_up_ctx;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* add the mes gang to idr list */</div><div class='del'>-	r = idr_alloc(&amp;adev-&gt;mes.gang_id_idr, gang, 1, 0,</div><div class='del'>-		      GFP_KERNEL);</div><div class='del'>-	if (r &lt; 0) {</div><div class='del'>-		DRM_ERROR("failed to allocate idr for gang\n");</div><div class='del'>-		goto clean_up_ctx;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gang-&gt;gang_id = r;</div><div class='del'>-	*gang_id = r;</div><div class='del'>-</div><div class='del'>-	INIT_LIST_HEAD(&amp;gang-&gt;queue_list);</div><div class='del'>-	gang-&gt;process = process;</div><div class='del'>-	gang-&gt;priority = gprops-&gt;priority;</div><div class='del'>-	gang-&gt;gang_quantum = gprops-&gt;gang_quantum ?</div><div class='del'>-		gprops-&gt;gang_quantum : adev-&gt;mes.default_gang_quantum;</div><div class='del'>-	gang-&gt;global_priority_level = gprops-&gt;global_priority_level;</div><div class='del'>-	gang-&gt;inprocess_gang_priority = gprops-&gt;inprocess_gang_priority;</div><div class='del'>-	list_add_tail(&amp;gang-&gt;list, &amp;process-&gt;gang_list);</div><div class='del'>-</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;resume_gang(&amp;adev-&gt;mes, &amp;input);</div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	return 0;</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to resume all gangs");</div><div class='ctx'> </div><div class='del'>-clean_up_ctx:</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;gang-&gt;gang_ctx_bo,</div><div class='del'>-			      &amp;gang-&gt;gang_ctx_gpu_addr,</div><div class='del'>-			      &amp;gang-&gt;gang_ctx_cpu_ptr);</div><div class='del'>-clean_up_mem:</div><div class='del'>-	kfree(gang);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id)</div><div class='add'>+int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='del'>-	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	gang = idr_find(&amp;adev-&gt;mes.gang_id_idr, gang_id);</div><div class='del'>-	if (!gang) {</div><div class='del'>-		DRM_ERROR("gang id %d doesn't exist\n", gang_id);</div><div class='del'>-		amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!list_empty(&amp;gang-&gt;queue_list)) {</div><div class='del'>-		DRM_ERROR("queue list is not empty\n");</div><div class='del'>-		amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-		return -EBUSY;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	idr_remove(&amp;adev-&gt;mes.gang_id_idr, gang-&gt;gang_id);</div><div class='del'>-	list_del(&amp;gang-&gt;list);</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;gang-&gt;gang_ctx_bo,</div><div class='del'>-			      &amp;gang-&gt;gang_ctx_gpu_addr,</div><div class='del'>-			      &amp;gang-&gt;gang_ctx_cpu_ptr);</div><div class='add'>+	struct mes_map_legacy_queue_input queue_input;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='del'>-	kfree(gang);</div><div class='add'>+	memset(&amp;queue_input, 0, sizeof(queue_input));</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_suspend(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct idr *idp;</div><div class='del'>-	struct amdgpu_mes_process *process;</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='del'>-	struct mes_suspend_gang_input input;</div><div class='del'>-	int r, pasid;</div><div class='add'>+	queue_input.queue_type = ring-&gt;funcs-&gt;type;</div><div class='add'>+	queue_input.doorbell_offset = ring-&gt;doorbell_index;</div><div class='add'>+	queue_input.pipe_id = ring-&gt;pipe;</div><div class='add'>+	queue_input.queue_id = ring-&gt;queue;</div><div class='add'>+	queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring-&gt;mqd_obj);</div><div class='add'>+	queue_input.wptr_addr = ring-&gt;wptr_gpu_addr;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='ctx'> 	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	idp = &amp;adev-&gt;mes.pasid_idr;</div><div class='del'>-</div><div class='del'>-	idr_for_each_entry(idp, process, pasid) {</div><div class='del'>-		list_for_each_entry(gang, &amp;process-&gt;gang_list, list) {</div><div class='del'>-			r = adev-&gt;mes.funcs-&gt;suspend_gang(&amp;adev-&gt;mes, &amp;input);</div><div class='del'>-			if (r)</div><div class='del'>-				DRM_ERROR("failed to suspend pasid %d gangid %d",</div><div class='del'>-					 pasid, gang-&gt;gang_id);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;map_legacy_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_resume(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct idr *idp;</div><div class='del'>-	struct amdgpu_mes_process *process;</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='del'>-	struct mes_resume_gang_input input;</div><div class='del'>-	int r, pasid;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='del'>-	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	idp = &amp;adev-&gt;mes.pasid_idr;</div><div class='del'>-</div><div class='del'>-	idr_for_each_entry(idp, process, pasid) {</div><div class='del'>-		list_for_each_entry(gang, &amp;process-&gt;gang_list, list) {</div><div class='del'>-			r = adev-&gt;mes.funcs-&gt;resume_gang(&amp;adev-&gt;mes, &amp;input);</div><div class='del'>-			if (r)</div><div class='del'>-				DRM_ERROR("failed to resume pasid %d gangid %d",</div><div class='del'>-					 pasid, gang-&gt;gang_id);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to map legacy queue\n");</div><div class='ctx'> </div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_mes_queue_alloc_mqd(struct amdgpu_device *adev,</div><div class='del'>-				     struct amdgpu_mes_queue *q,</div><div class='del'>-				     struct amdgpu_mes_queue_properties *p)</div><div class='add'>+int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,</div><div class='add'>+				  struct amdgpu_ring *ring,</div><div class='add'>+				  enum amdgpu_unmap_queues_action action,</div><div class='add'>+				  u64 gpu_addr, u64 seq)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_mqd *mqd_mgr = &amp;adev-&gt;mqds[p-&gt;queue_type];</div><div class='del'>-	u32 mqd_size = mqd_mgr-&gt;mqd_size;</div><div class='add'>+	struct mes_unmap_legacy_queue_input queue_input;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;q-&gt;mqd_obj,</div><div class='del'>-				    &amp;q-&gt;mqd_gpu_addr, &amp;q-&gt;mqd_cpu_ptr);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "failed to create queue mqd bo (%d)", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-	memset(q-&gt;mqd_cpu_ptr, 0, mqd_size);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(q-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		goto clean_up;</div><div class='add'>+	queue_input.action = action;</div><div class='add'>+	queue_input.queue_type = ring-&gt;funcs-&gt;type;</div><div class='add'>+	queue_input.doorbell_offset = ring-&gt;doorbell_index;</div><div class='add'>+	queue_input.pipe_id = ring-&gt;pipe;</div><div class='add'>+	queue_input.queue_id = ring-&gt;queue;</div><div class='add'>+	queue_input.trail_fence_addr = gpu_addr;</div><div class='add'>+	queue_input.trail_fence_data = seq;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;unmap_legacy_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to unmap legacy queue\n");</div><div class='ctx'> </div><div class='del'>-clean_up:</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;q-&gt;mqd_obj,</div><div class='del'>-			      &amp;q-&gt;mqd_gpu_addr,</div><div class='del'>-			      &amp;q-&gt;mqd_cpu_ptr);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_mes_queue_init_mqd(struct amdgpu_device *adev,</div><div class='del'>-				     struct amdgpu_mes_queue *q,</div><div class='del'>-				     struct amdgpu_mes_queue_properties *p)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_mqd *mqd_mgr = &amp;adev-&gt;mqds[p-&gt;queue_type];</div><div class='del'>-	struct amdgpu_mqd_prop mqd_prop = {0};</div><div class='del'>-</div><div class='del'>-	mqd_prop.mqd_gpu_addr = q-&gt;mqd_gpu_addr;</div><div class='del'>-	mqd_prop.hqd_base_gpu_addr = p-&gt;hqd_base_gpu_addr;</div><div class='del'>-	mqd_prop.rptr_gpu_addr = p-&gt;rptr_gpu_addr;</div><div class='del'>-	mqd_prop.wptr_gpu_addr = p-&gt;wptr_gpu_addr;</div><div class='del'>-	mqd_prop.queue_size = p-&gt;queue_size;</div><div class='del'>-	mqd_prop.use_doorbell = true;</div><div class='del'>-	mqd_prop.doorbell_index = p-&gt;doorbell_off;</div><div class='del'>-	mqd_prop.eop_gpu_addr = p-&gt;eop_gpu_addr;</div><div class='del'>-	mqd_prop.hqd_pipe_priority = p-&gt;hqd_pipe_priority;</div><div class='del'>-	mqd_prop.hqd_queue_priority = p-&gt;hqd_queue_priority;</div><div class='del'>-	mqd_prop.hqd_active = false;</div><div class='del'>-</div><div class='del'>-	if (p-&gt;queue_type == AMDGPU_RING_TYPE_GFX ||</div><div class='del'>-	    p-&gt;queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='del'>-		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-		amdgpu_gfx_select_me_pipe_q(adev, p-&gt;ring-&gt;me, p-&gt;ring-&gt;pipe, 0, 0, 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mqd_mgr-&gt;init_mqd(adev, q-&gt;mqd_cpu_ptr, &amp;mqd_prop);</div><div class='del'>-</div><div class='del'>-	if (p-&gt;queue_type == AMDGPU_RING_TYPE_GFX ||</div><div class='del'>-	    p-&gt;queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='del'>-		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);</div><div class='del'>-		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_unreserve(q-&gt;mqd_obj);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,</div><div class='del'>-			    struct amdgpu_mes_queue_properties *qprops,</div><div class='del'>-			    int *queue_id)</div><div class='add'>+int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,</div><div class='add'>+				  struct amdgpu_ring *ring,</div><div class='add'>+				  unsigned int vmid,</div><div class='add'>+				  bool use_mmio)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_mes_queue *queue;</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='del'>-	struct mes_add_queue_input queue_input;</div><div class='del'>-	unsigned long flags;</div><div class='add'>+	struct mes_reset_queue_input queue_input;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	memset(&amp;queue_input, 0, sizeof(struct mes_add_queue_input));</div><div class='add'>+	memset(&amp;queue_input, 0, sizeof(queue_input));</div><div class='ctx'> </div><div class='del'>-	/* allocate the mes queue buffer */</div><div class='del'>-	queue = kzalloc(sizeof(struct amdgpu_mes_queue), GFP_KERNEL);</div><div class='del'>-	if (!queue) {</div><div class='del'>-		DRM_ERROR("Failed to allocate memory for queue\n");</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Allocate the queue mqd */</div><div class='del'>-	r = amdgpu_mes_queue_alloc_mqd(adev, queue, qprops);</div><div class='del'>-	if (r)</div><div class='del'>-		goto clean_up_memory;</div><div class='add'>+	queue_input.queue_type = ring-&gt;funcs-&gt;type;</div><div class='add'>+	queue_input.doorbell_offset = ring-&gt;doorbell_index;</div><div class='add'>+	queue_input.me_id = ring-&gt;me;</div><div class='add'>+	queue_input.pipe_id = ring-&gt;pipe;</div><div class='add'>+	queue_input.queue_id = ring-&gt;queue;</div><div class='add'>+	queue_input.mqd_addr = ring-&gt;mqd_obj ? amdgpu_bo_gpu_offset(ring-&gt;mqd_obj) : 0;</div><div class='add'>+	queue_input.wptr_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	queue_input.vmid = vmid;</div><div class='add'>+	queue_input.use_mmio = use_mmio;</div><div class='add'>+	queue_input.is_kq = true;</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX)</div><div class='add'>+		queue_input.legacy_gfx = true;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='ctx'> 	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	gang = idr_find(&amp;adev-&gt;mes.gang_id_idr, gang_id);</div><div class='del'>-	if (!gang) {</div><div class='del'>-		DRM_ERROR("gang id %d doesn't exist\n", gang_id);</div><div class='del'>-		r = -EINVAL;</div><div class='del'>-		goto clean_up_mqd;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* add the mes gang to idr list */</div><div class='del'>-	spin_lock_irqsave(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-	r = idr_alloc(&amp;adev-&gt;mes.queue_id_idr, queue, 1, 0,</div><div class='del'>-		      GFP_ATOMIC);</div><div class='del'>-	if (r &lt; 0) {</div><div class='del'>-		spin_unlock_irqrestore(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-		goto clean_up_mqd;</div><div class='del'>-	}</div><div class='del'>-	spin_unlock_irqrestore(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-	*queue_id = queue-&gt;queue_id = r;</div><div class='del'>-</div><div class='del'>-	/* allocate a doorbell index for the queue */</div><div class='del'>-	r = amdgpu_mes_kernel_doorbell_get(adev, gang-&gt;process,</div><div class='del'>-					  qprops-&gt;queue_type,</div><div class='del'>-					  &amp;qprops-&gt;doorbell_off);</div><div class='del'>-	if (r)</div><div class='del'>-		goto clean_up_queue_id;</div><div class='del'>-</div><div class='del'>-	/* initialize the queue mqd */</div><div class='del'>-	amdgpu_mes_queue_init_mqd(adev, queue, qprops);</div><div class='del'>-</div><div class='del'>-	/* add hw queue to mes */</div><div class='del'>-	queue_input.process_id = gang-&gt;process-&gt;pasid;</div><div class='del'>-</div><div class='del'>-	queue_input.page_table_base_addr =</div><div class='del'>-		adev-&gt;vm_manager.vram_base_offset + gang-&gt;process-&gt;pd_gpu_addr -</div><div class='del'>-		adev-&gt;gmc.vram_start;</div><div class='del'>-</div><div class='del'>-	queue_input.process_va_start = 0;</div><div class='del'>-	queue_input.process_va_end =</div><div class='del'>-		(adev-&gt;vm_manager.max_pfn - 1) &lt;&lt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='del'>-	queue_input.process_quantum = gang-&gt;process-&gt;process_quantum;</div><div class='del'>-	queue_input.process_context_addr = gang-&gt;process-&gt;proc_ctx_gpu_addr;</div><div class='del'>-	queue_input.gang_quantum = gang-&gt;gang_quantum;</div><div class='del'>-	queue_input.gang_context_addr = gang-&gt;gang_ctx_gpu_addr;</div><div class='del'>-	queue_input.inprocess_gang_priority = gang-&gt;inprocess_gang_priority;</div><div class='del'>-	queue_input.gang_global_priority_level = gang-&gt;global_priority_level;</div><div class='del'>-	queue_input.doorbell_offset = qprops-&gt;doorbell_off;</div><div class='del'>-	queue_input.mqd_addr = queue-&gt;mqd_gpu_addr;</div><div class='del'>-	queue_input.wptr_addr = qprops-&gt;wptr_gpu_addr;</div><div class='del'>-	queue_input.wptr_mc_addr = qprops-&gt;wptr_mc_addr;</div><div class='del'>-	queue_input.queue_type = qprops-&gt;queue_type;</div><div class='del'>-	queue_input.paging = qprops-&gt;paging;</div><div class='del'>-	queue_input.is_kfd_process = 0;</div><div class='del'>-</div><div class='del'>-	r = adev-&gt;mes.funcs-&gt;add_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to add hardware queue to MES, doorbell=0x%llx\n",</div><div class='del'>-			  qprops-&gt;doorbell_off);</div><div class='del'>-		goto clean_up_doorbell;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG("MES hw queue was added, pasid=%d, gang id=%d, "</div><div class='del'>-		  "queue type=%d, doorbell=0x%llx\n",</div><div class='del'>-		  gang-&gt;process-&gt;pasid, gang_id, qprops-&gt;queue_type,</div><div class='del'>-		  qprops-&gt;doorbell_off);</div><div class='del'>-</div><div class='del'>-	queue-&gt;ring = qprops-&gt;ring;</div><div class='del'>-	queue-&gt;doorbell_off = qprops-&gt;doorbell_off;</div><div class='del'>-	queue-&gt;wptr_gpu_addr = qprops-&gt;wptr_gpu_addr;</div><div class='del'>-	queue-&gt;queue_type = qprops-&gt;queue_type;</div><div class='del'>-	queue-&gt;paging = qprops-&gt;paging;</div><div class='del'>-	queue-&gt;gang = gang;</div><div class='del'>-	queue-&gt;ring-&gt;mqd_ptr = queue-&gt;mqd_cpu_ptr;</div><div class='del'>-	list_add_tail(&amp;queue-&gt;list, &amp;gang-&gt;queue_list);</div><div class='del'>-</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;reset_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	return 0;</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to reset legacy queue\n");</div><div class='ctx'> </div><div class='del'>-clean_up_doorbell:</div><div class='del'>-	amdgpu_mes_kernel_doorbell_free(adev, gang-&gt;process,</div><div class='del'>-				       qprops-&gt;doorbell_off);</div><div class='del'>-clean_up_queue_id:</div><div class='del'>-	spin_lock_irqsave(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-	idr_remove(&amp;adev-&gt;mes.queue_id_idr, queue-&gt;queue_id);</div><div class='del'>-	spin_unlock_irqrestore(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-clean_up_mqd:</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	amdgpu_mes_queue_free_mqd(queue);</div><div class='del'>-clean_up_memory:</div><div class='del'>-	kfree(queue);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id)</div><div class='add'>+int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	struct amdgpu_mes_queue *queue;</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='del'>-	struct mes_remove_queue_input queue_input;</div><div class='del'>-	int r;</div><div class='add'>+	return adev-&gt;mes.hung_queue_db_array_size;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='del'>-	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,</div><div class='add'>+					    int queue_type,</div><div class='add'>+					    bool detect_only,</div><div class='add'>+					    unsigned int *hung_db_num,</div><div class='add'>+					    u32 *hung_db_array)</div><div class='ctx'> </div><div class='del'>-	/* remove the mes gang from idr list */</div><div class='del'>-	spin_lock_irqsave(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='add'>+{</div><div class='add'>+	struct mes_detect_and_reset_queue_input input;</div><div class='add'>+	u32 *db_array = adev-&gt;mes.hung_queue_db_array_cpu_addr;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	queue = idr_find(&amp;adev-&gt;mes.queue_id_idr, queue_id);</div><div class='del'>-	if (!queue) {</div><div class='del'>-		spin_unlock_irqrestore(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-		amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-		DRM_ERROR("queue id %d doesn't exist\n", queue_id);</div><div class='add'>+	if (!hung_db_num || !hung_db_array)</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	idr_remove(&amp;adev-&gt;mes.queue_id_idr, queue_id);</div><div class='del'>-	spin_unlock_irqrestore(&amp;adev-&gt;mes.queue_id_lock, flags);</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG("try to remove queue, doorbell off = 0x%llx\n",</div><div class='del'>-		  queue-&gt;doorbell_off);</div><div class='del'>-</div><div class='del'>-	gang = queue-&gt;gang;</div><div class='del'>-	queue_input.doorbell_offset = queue-&gt;doorbell_off;</div><div class='del'>-	queue_input.gang_context_addr = gang-&gt;gang_ctx_gpu_addr;</div><div class='del'>-</div><div class='del'>-	r = adev-&gt;mes.funcs-&gt;remove_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='del'>-	if (r)</div><div class='del'>-		DRM_ERROR("failed to remove hardware queue, queue id = %d\n",</div><div class='del'>-			  queue_id);</div><div class='ctx'> </div><div class='del'>-	list_del(&amp;queue-&gt;list);</div><div class='del'>-	amdgpu_mes_kernel_doorbell_free(adev, gang-&gt;process,</div><div class='del'>-				       queue-&gt;doorbell_off);</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if ((queue_type != AMDGPU_RING_TYPE_GFX) &amp;&amp;</div><div class='add'>+	    (queue_type != AMDGPU_RING_TYPE_COMPUTE) &amp;&amp;</div><div class='add'>+	    (queue_type != AMDGPU_RING_TYPE_SDMA))</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	amdgpu_mes_queue_free_mqd(queue);</div><div class='del'>-	kfree(queue);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='add'>+	/* Clear the doorbell array before detection */</div><div class='add'>+	memset(adev-&gt;mes.hung_queue_db_array_cpu_addr, AMDGPU_MES_INVALID_DB_OFFSET,</div><div class='add'>+		adev-&gt;mes.hung_queue_db_array_size * sizeof(u32));</div><div class='add'>+	input.queue_type = queue_type;</div><div class='add'>+	input.detect_only = detect_only;</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,</div><div class='del'>-				  struct amdgpu_ring *ring,</div><div class='del'>-				  enum amdgpu_unmap_queues_action action,</div><div class='del'>-				  u64 gpu_addr, u64 seq)</div><div class='del'>-{</div><div class='del'>-	struct mes_unmap_legacy_queue_input queue_input;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	queue_input.action = action;</div><div class='del'>-	queue_input.queue_type = ring-&gt;funcs-&gt;type;</div><div class='del'>-	queue_input.doorbell_offset = ring-&gt;doorbell_index;</div><div class='del'>-	queue_input.pipe_id = ring-&gt;pipe;</div><div class='del'>-	queue_input.queue_id = ring-&gt;queue;</div><div class='del'>-	queue_input.trail_fence_addr = gpu_addr;</div><div class='del'>-	queue_input.trail_fence_data = seq;</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;detect_and_reset_hung_queues(&amp;adev-&gt;mes,</div><div class='add'>+							  &amp;input);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to detect and reset\n");</div><div class='add'>+	} else {</div><div class='add'>+		*hung_db_num = 0;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;mes.hung_queue_hqd_info_offset; i++) {</div><div class='add'>+			if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) {</div><div class='add'>+				hung_db_array[i] = db_array[i];</div><div class='add'>+				*hung_db_num += 1;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	r = adev-&gt;mes.funcs-&gt;unmap_legacy_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='del'>-	if (r)</div><div class='del'>-		DRM_ERROR("failed to unmap legacy queue\n");</div><div class='add'>+		/*</div><div class='add'>+		 * TODO: return HQD info for MES scheduled user compute queue reset cases</div><div class='add'>+		 * stored in hung_db_array hqd info offset to full array size</div><div class='add'>+		 */</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -802,23 +440,36 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)</div><div class='ctx'> {</div><div class='ctx'> 	struct mes_misc_op_input op_input;</div><div class='ctx'> 	int r, val = 0;</div><div class='add'>+	uint32_t addr_offset = 0;</div><div class='add'>+	uint64_t read_val_gpu_addr;</div><div class='add'>+	uint32_t *read_val_ptr;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_device_wb_get(adev, &amp;addr_offset)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "critical bug! too many mes readers\n");</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+	read_val_gpu_addr = adev-&gt;wb.gpu_addr + (addr_offset * 4);</div><div class='add'>+	read_val_ptr = (uint32_t *)&amp;adev-&gt;wb.wb[addr_offset];</div><div class='ctx'> 	op_input.op = MES_MISC_OP_READ_REG;</div><div class='ctx'> 	op_input.read_reg.reg_offset = reg;</div><div class='del'>-	op_input.read_reg.buffer_addr = adev-&gt;mes.read_val_gpu_addr;</div><div class='add'>+	op_input.read_reg.buffer_addr = read_val_gpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='del'>-		DRM_ERROR("mes rreg is not supported!\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "mes rreg is not supported!\n");</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("failed to read reg (0x%x)\n", reg);</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to read reg (0x%x)\n", reg);</div><div class='ctx'> 	else</div><div class='del'>-		val = *(adev-&gt;mes.read_val_ptr);</div><div class='add'>+		val = *(read_val_ptr);</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='add'>+	if (addr_offset)</div><div class='add'>+		amdgpu_device_wb_free(adev, addr_offset);</div><div class='ctx'> 	return val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -833,14 +484,16 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev,</div><div class='ctx'> 	op_input.write_reg.reg_value = val;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='del'>-		DRM_ERROR("mes wreg is not supported!\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "mes wreg is not supported!\n");</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("failed to write reg (0x%x)\n", reg);</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to write reg (0x%x)\n", reg);</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -860,42 +513,31 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,</div><div class='ctx'> 	op_input.wrm_reg.mask = mask;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='del'>-		DRM_ERROR("mes reg_write_reg_wait is not supported!\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "mes reg_write_reg_wait is not supported!\n");</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("failed to reg_write_reg_wait\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to reg_write_reg_wait\n");</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,</div><div class='del'>-			uint32_t val, uint32_t mask)</div><div class='add'>+int amdgpu_mes_hdp_flush(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct mes_misc_op_input op_input;</div><div class='del'>-	int r;</div><div class='add'>+	uint32_t hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask;</div><div class='ctx'> </div><div class='del'>-	op_input.op = MES_MISC_OP_WRM_REG_WAIT;</div><div class='del'>-	op_input.wrm_reg.reg0 = reg;</div><div class='del'>-	op_input.wrm_reg.ref = val;</div><div class='del'>-	op_input.wrm_reg.mask = mask;</div><div class='add'>+	hdp_flush_req_offset = adev-&gt;nbio.funcs-&gt;get_hdp_flush_req_offset(adev);</div><div class='add'>+	hdp_flush_done_offset = adev-&gt;nbio.funcs-&gt;get_hdp_flush_done_offset(adev);</div><div class='add'>+	ref_and_mask = adev-&gt;nbio.hdp_flush_reg-&gt;ref_and_mask_cp0;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='del'>-		DRM_ERROR("mes reg wait is not supported!\n");</div><div class='del'>-		r = -EINVAL;</div><div class='del'>-		goto error;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='del'>-	if (r)</div><div class='del'>-		DRM_ERROR("failed to reg_write_reg_wait\n");</div><div class='del'>-</div><div class='del'>-error:</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset,</div><div class='add'>+					     ref_and_mask, ref_and_mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='hunk'>@@ -909,7 +551,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='del'>-		DRM_ERROR("mes set shader debugger is not supported!\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"mes set shader debugger is not supported!\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -933,7 +576,7 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("failed to set_shader_debugger\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to set_shader_debugger\n");</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='ctx'> </div><div class='hunk'>@@ -947,7 +590,8 @@ int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='del'>-		DRM_ERROR("mes flush shader debugger is not supported!\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"mes flush shader debugger is not supported!\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -959,525 +603,36 @@ int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_ERROR("failed to set_shader_debugger\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to set_shader_debugger\n");</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void</div><div class='del'>-amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,</div><div class='del'>-			       struct amdgpu_ring *ring,</div><div class='del'>-			       struct amdgpu_mes_queue_properties *props)</div><div class='del'>-{</div><div class='del'>-	props-&gt;queue_type = ring-&gt;funcs-&gt;type;</div><div class='del'>-	props-&gt;hqd_base_gpu_addr = ring-&gt;gpu_addr;</div><div class='del'>-	props-&gt;rptr_gpu_addr = ring-&gt;rptr_gpu_addr;</div><div class='del'>-	props-&gt;wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='del'>-	props-&gt;wptr_mc_addr =</div><div class='del'>-		ring-&gt;mes_ctx-&gt;meta_data_mc_addr + ring-&gt;wptr_offs;</div><div class='del'>-	props-&gt;queue_size = ring-&gt;ring_size;</div><div class='del'>-	props-&gt;eop_gpu_addr = ring-&gt;eop_gpu_addr;</div><div class='del'>-	props-&gt;hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;</div><div class='del'>-	props-&gt;hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM;</div><div class='del'>-	props-&gt;paging = false;</div><div class='del'>-	props-&gt;ring = ring;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#define DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(_eng)			\</div><div class='del'>-do {									\</div><div class='del'>-       if (id_offs &lt; AMDGPU_MES_CTX_MAX_OFFS)				\</div><div class='del'>-		return offsetof(struct amdgpu_mes_ctx_meta_data,	\</div><div class='del'>-				_eng[ring-&gt;idx].slots[id_offs]);        \</div><div class='del'>-       else if (id_offs == AMDGPU_MES_CTX_RING_OFFS)			\</div><div class='del'>-		return offsetof(struct amdgpu_mes_ctx_meta_data,        \</div><div class='del'>-				_eng[ring-&gt;idx].ring);                  \</div><div class='del'>-       else if (id_offs == AMDGPU_MES_CTX_IB_OFFS)			\</div><div class='del'>-		return offsetof(struct amdgpu_mes_ctx_meta_data,        \</div><div class='del'>-				_eng[ring-&gt;idx].ib);                    \</div><div class='del'>-       else if (id_offs == AMDGPU_MES_CTX_PADDING_OFFS)			\</div><div class='del'>-		return offsetof(struct amdgpu_mes_ctx_meta_data,        \</div><div class='del'>-				_eng[ring-&gt;idx].padding);               \</div><div class='del'>-} while(0)</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs)</div><div class='del'>-{</div><div class='del'>-	switch (ring-&gt;funcs-&gt;type) {</div><div class='del'>-	case AMDGPU_RING_TYPE_GFX:</div><div class='del'>-		DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(gfx);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='del'>-		DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(compute);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_RING_TYPE_SDMA:</div><div class='del'>-		DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(sdma);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	WARN_ON(1);</div><div class='del'>-	return -EINVAL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,</div><div class='del'>-			int queue_type, int idx,</div><div class='del'>-			struct amdgpu_mes_ctx_data *ctx_data,</div><div class='del'>-			struct amdgpu_ring **out)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_mes_gang *gang;</div><div class='del'>-	struct amdgpu_mes_queue_properties qprops = {0};</div><div class='del'>-	int r, queue_id, pasid;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Avoid taking any other locks under MES lock to avoid circular</div><div class='del'>-	 * lock dependencies.</div><div class='del'>-	 */</div><div class='del'>-	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='del'>-	gang = idr_find(&amp;adev-&gt;mes.gang_id_idr, gang_id);</div><div class='del'>-	if (!gang) {</div><div class='del'>-		DRM_ERROR("gang id %d doesn't exist\n", gang_id);</div><div class='del'>-		amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-	pasid = gang-&gt;process-&gt;pasid;</div><div class='del'>-</div><div class='del'>-	ring = kzalloc(sizeof(struct amdgpu_ring), GFP_KERNEL);</div><div class='del'>-	if (!ring) {</div><div class='del'>-		amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ring-&gt;ring_obj = NULL;</div><div class='del'>-	ring-&gt;use_doorbell = true;</div><div class='del'>-	ring-&gt;is_mes_queue = true;</div><div class='del'>-	ring-&gt;mes_ctx = ctx_data;</div><div class='del'>-	ring-&gt;idx = idx;</div><div class='del'>-	ring-&gt;no_scheduler = true;</div><div class='del'>-</div><div class='del'>-	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='del'>-		int offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				      compute[ring-&gt;idx].mec_hpd);</div><div class='del'>-		ring-&gt;eop_gpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (queue_type) {</div><div class='del'>-	case AMDGPU_RING_TYPE_GFX:</div><div class='del'>-		ring-&gt;funcs = adev-&gt;gfx.gfx_ring[0].funcs;</div><div class='del'>-		ring-&gt;me = adev-&gt;gfx.gfx_ring[0].me;</div><div class='del'>-		ring-&gt;pipe = adev-&gt;gfx.gfx_ring[0].pipe;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='del'>-		ring-&gt;funcs = adev-&gt;gfx.compute_ring[0].funcs;</div><div class='del'>-		ring-&gt;me = adev-&gt;gfx.compute_ring[0].me;</div><div class='del'>-		ring-&gt;pipe = adev-&gt;gfx.compute_ring[0].pipe;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_RING_TYPE_SDMA:</div><div class='del'>-		ring-&gt;funcs = adev-&gt;sdma.instance[0].ring.funcs;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BUG();</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_ring_init(adev, ring, 1024, NULL, 0,</div><div class='del'>-			     AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='del'>-	if (r)</div><div class='del'>-		goto clean_up_memory;</div><div class='del'>-</div><div class='del'>-	amdgpu_mes_ring_to_queue_props(adev, ring, &amp;qprops);</div><div class='del'>-</div><div class='del'>-	dma_fence_wait(gang-&gt;process-&gt;vm-&gt;last_update, false);</div><div class='del'>-	dma_fence_wait(ctx_data-&gt;meta_data_va-&gt;last_pt_update, false);</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_add_hw_queue(adev, gang_id, &amp;qprops, &amp;queue_id);</div><div class='del'>-	if (r)</div><div class='del'>-		goto clean_up_ring;</div><div class='del'>-</div><div class='del'>-	ring-&gt;hw_queue_id = queue_id;</div><div class='del'>-	ring-&gt;doorbell_index = qprops.doorbell_off;</div><div class='del'>-</div><div class='del'>-	if (queue_type == AMDGPU_RING_TYPE_GFX)</div><div class='del'>-		sprintf(ring-&gt;name, "gfx_%d.%d.%d", pasid, gang_id, queue_id);</div><div class='del'>-	else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)</div><div class='del'>-		sprintf(ring-&gt;name, "compute_%d.%d.%d", pasid, gang_id,</div><div class='del'>-			queue_id);</div><div class='del'>-	else if (queue_type == AMDGPU_RING_TYPE_SDMA)</div><div class='del'>-		sprintf(ring-&gt;name, "sdma_%d.%d.%d", pasid, gang_id,</div><div class='del'>-			queue_id);</div><div class='del'>-	else</div><div class='del'>-		BUG();</div><div class='del'>-</div><div class='del'>-	*out = ring;</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-clean_up_ring:</div><div class='del'>-	amdgpu_ring_fini(ring);</div><div class='del'>-clean_up_memory:</div><div class='del'>-	kfree(ring);</div><div class='del'>-	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void amdgpu_mes_remove_ring(struct amdgpu_device *adev,</div><div class='del'>-			    struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	if (!ring)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	amdgpu_mes_remove_hw_queue(adev, ring-&gt;hw_queue_id);</div><div class='del'>-	amdgpu_ring_fini(ring);</div><div class='del'>-	kfree(ring);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,</div><div class='ctx'> 						   enum amdgpu_mes_priority_level prio)</div><div class='ctx'> {</div><div class='ctx'> 	return adev-&gt;mes.aggregated_doorbells[prio];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,</div><div class='del'>-				   struct amdgpu_mes_ctx_data *ctx_data)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev,</div><div class='del'>-			    sizeof(struct amdgpu_mes_ctx_meta_data),</div><div class='del'>-			    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-			    &amp;ctx_data-&gt;meta_data_obj,</div><div class='del'>-			    &amp;ctx_data-&gt;meta_data_mc_addr,</div><div class='del'>-			    &amp;ctx_data-&gt;meta_data_ptr);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "(%d) create CTX bo failed\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!ctx_data-&gt;meta_data_obj)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	memset(ctx_data-&gt;meta_data_ptr, 0,</div><div class='del'>-	       sizeof(struct amdgpu_mes_ctx_meta_data));</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data)</div><div class='del'>-{</div><div class='del'>-	if (ctx_data-&gt;meta_data_obj)</div><div class='del'>-		amdgpu_bo_free_kernel(&amp;ctx_data-&gt;meta_data_obj,</div><div class='del'>-				      &amp;ctx_data-&gt;meta_data_mc_addr,</div><div class='del'>-				      &amp;ctx_data-&gt;meta_data_ptr);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,</div><div class='del'>-				 struct amdgpu_vm *vm,</div><div class='del'>-				 struct amdgpu_mes_ctx_data *ctx_data)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_bo_va *bo_va;</div><div class='del'>-	struct amdgpu_sync sync;</div><div class='del'>-	struct drm_exec exec;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_create(&amp;sync);</div><div class='del'>-</div><div class='del'>-	drm_exec_init(&amp;exec, 0, 0);</div><div class='del'>-	drm_exec_until_all_locked(&amp;exec) {</div><div class='del'>-		r = drm_exec_lock_obj(&amp;exec,</div><div class='del'>-				      &amp;ctx_data-&gt;meta_data_obj-&gt;tbo.base);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto error_fini_exec;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto error_fini_exec;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	bo_va = amdgpu_vm_bo_add(adev, vm, ctx_data-&gt;meta_data_obj);</div><div class='del'>-	if (!bo_va) {</div><div class='del'>-		DRM_ERROR("failed to create bo_va for meta data BO\n");</div><div class='del'>-		r = -ENOMEM;</div><div class='del'>-		goto error_fini_exec;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_bo_map(adev, bo_va, ctx_data-&gt;meta_data_gpu_addr, 0,</div><div class='del'>-			     sizeof(struct amdgpu_mes_ctx_meta_data),</div><div class='del'>-			     AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |</div><div class='del'>-			     AMDGPU_PTE_EXECUTABLE);</div><div class='del'>-</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to do bo_map on meta data, err=%d\n", r);</div><div class='del'>-		goto error_del_bo_va;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_bo_update(adev, bo_va, false);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to do vm_bo_update on meta data\n");</div><div class='del'>-		goto error_del_bo_va;</div><div class='del'>-	}</div><div class='del'>-	amdgpu_sync_fence(&amp;sync, bo_va-&gt;last_pt_update);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_update_pdes(adev, vm, false);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to update pdes on meta data\n");</div><div class='del'>-		goto error_del_bo_va;</div><div class='del'>-	}</div><div class='del'>-	amdgpu_sync_fence(&amp;sync, vm-&gt;last_update);</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_wait(&amp;sync, false);</div><div class='del'>-	drm_exec_fini(&amp;exec);</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_free(&amp;sync);</div><div class='del'>-	ctx_data-&gt;meta_data_va = bo_va;</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-error_del_bo_va:</div><div class='del'>-	amdgpu_vm_bo_del(adev, bo_va);</div><div class='del'>-</div><div class='del'>-error_fini_exec:</div><div class='del'>-	drm_exec_fini(&amp;exec);</div><div class='del'>-	amdgpu_sync_free(&amp;sync);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,</div><div class='del'>-				   struct amdgpu_mes_ctx_data *ctx_data)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_bo_va *bo_va = ctx_data-&gt;meta_data_va;</div><div class='del'>-	struct amdgpu_bo *bo = ctx_data-&gt;meta_data_obj;</div><div class='del'>-	struct amdgpu_vm *vm = bo_va-&gt;base.vm;</div><div class='del'>-	struct dma_fence *fence;</div><div class='del'>-	struct drm_exec exec;</div><div class='del'>-	long r;</div><div class='del'>-</div><div class='del'>-	drm_exec_init(&amp;exec, 0, 0);</div><div class='del'>-	drm_exec_until_all_locked(&amp;exec) {</div><div class='del'>-		r = drm_exec_lock_obj(&amp;exec,</div><div class='del'>-				      &amp;ctx_data-&gt;meta_data_obj-&gt;tbo.base);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto out_unlock;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto out_unlock;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_vm_bo_del(adev, bo_va);</div><div class='del'>-	if (!amdgpu_vm_ready(vm))</div><div class='del'>-		goto out_unlock;</div><div class='del'>-</div><div class='del'>-	r = dma_resv_get_singleton(bo-&gt;tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP,</div><div class='del'>-				   &amp;fence);</div><div class='del'>-	if (r)</div><div class='del'>-		goto out_unlock;</div><div class='del'>-	if (fence) {</div><div class='del'>-		amdgpu_bo_fence(bo, fence, true);</div><div class='del'>-		fence = NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_clear_freed(adev, vm, &amp;fence);</div><div class='del'>-	if (r || !fence)</div><div class='del'>-		goto out_unlock;</div><div class='del'>-</div><div class='del'>-	dma_fence_wait(fence, false);</div><div class='del'>-	amdgpu_bo_fence(bo, fence, true);</div><div class='del'>-	dma_fence_put(fence);</div><div class='del'>-</div><div class='del'>-out_unlock:</div><div class='del'>-	if (unlikely(r &lt; 0))</div><div class='del'>-		dev_err(adev-&gt;dev, "failed to clear page tables (%ld)\n", r);</div><div class='del'>-	drm_exec_fini(&amp;exec);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int amdgpu_mes_test_create_gang_and_queues(struct amdgpu_device *adev,</div><div class='del'>-					  int pasid, int *gang_id,</div><div class='del'>-					  int queue_type, int num_queue,</div><div class='del'>-					  struct amdgpu_ring **added_rings,</div><div class='del'>-					  struct amdgpu_mes_ctx_data *ctx_data)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_mes_gang_properties gprops = {0};</div><div class='del'>-	int r, j;</div><div class='del'>-</div><div class='del'>-	/* create a gang for the process */</div><div class='del'>-	gprops.priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;</div><div class='del'>-	gprops.gang_quantum = adev-&gt;mes.default_gang_quantum;</div><div class='del'>-	gprops.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;</div><div class='del'>-	gprops.priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;</div><div class='del'>-	gprops.global_priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_add_gang(adev, pasid, &amp;gprops, gang_id);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to add gang\n");</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* create queues for the gang */</div><div class='del'>-	for (j = 0; j &lt; num_queue; j++) {</div><div class='del'>-		r = amdgpu_mes_add_ring(adev, *gang_id, queue_type, j,</div><div class='del'>-					ctx_data, &amp;ring);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("failed to add ring\n");</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		DRM_INFO("ring %s was added\n", ring-&gt;name);</div><div class='del'>-		added_rings[j] = ring;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int amdgpu_mes_test_queues(struct amdgpu_ring **added_rings)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int i, r;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MES_CTX_MAX_RINGS; i++) {</div><div class='del'>-		ring = added_rings[i];</div><div class='del'>-		if (!ring)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_ring_test_helper(ring);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_ring_test_ib(ring, 1000 * 10);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_DEV_ERROR(ring-&gt;adev-&gt;dev,</div><div class='del'>-				      "ring %s ib test failed (%d)\n",</div><div class='del'>-				      ring-&gt;name, r);</div><div class='del'>-			return r;</div><div class='del'>-		} else</div><div class='del'>-			DRM_INFO("ring %s ib test pass\n", ring-&gt;name);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_self_test(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_vm *vm = NULL;</div><div class='del'>-	struct amdgpu_mes_ctx_data ctx_data = {0};</div><div class='del'>-	struct amdgpu_ring *added_rings[AMDGPU_MES_CTX_MAX_RINGS] = { NULL };</div><div class='del'>-	int gang_ids[3] = {0};</div><div class='del'>-	int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX, 1 },</div><div class='del'>-				 { AMDGPU_RING_TYPE_COMPUTE, 1 },</div><div class='del'>-				 { AMDGPU_RING_TYPE_SDMA, 1} };</div><div class='del'>-	int i, r, pasid, k = 0;</div><div class='del'>-</div><div class='del'>-	pasid = amdgpu_pasid_alloc(16);</div><div class='del'>-	if (pasid &lt; 0) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "No more PASIDs available!");</div><div class='del'>-		pasid = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	vm = kzalloc(sizeof(*vm), GFP_KERNEL);</div><div class='del'>-	if (!vm) {</div><div class='del'>-		r = -ENOMEM;</div><div class='del'>-		goto error_pasid;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_init(adev, vm, -1);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to initialize vm\n");</div><div class='del'>-		goto error_pasid;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_ctx_alloc_meta_data(adev, &amp;ctx_data);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to alloc ctx meta data\n");</div><div class='del'>-		goto error_fini;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ctx_data.meta_data_gpu_addr = AMDGPU_VA_RESERVED_BOTTOM;</div><div class='del'>-	r = amdgpu_mes_ctx_map_meta_data(adev, vm, &amp;ctx_data);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to map ctx meta data\n");</div><div class='del'>-		goto error_vm;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_create_process(adev, pasid, vm);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("failed to create MES process\n");</div><div class='del'>-		goto error_vm;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(queue_types); i++) {</div><div class='del'>-		/* On GFX v10.3, fw hasn't supported to map sdma queue. */</div><div class='del'>-		if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;=</div><div class='del'>-			    IP_VERSION(10, 3, 0) &amp;&amp;</div><div class='del'>-		    amdgpu_ip_version(adev, GC_HWIP, 0) &lt;</div><div class='del'>-			    IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='del'>-		    queue_types[i][0] == AMDGPU_RING_TYPE_SDMA)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_mes_test_create_gang_and_queues(adev, pasid,</div><div class='del'>-							   &amp;gang_ids[i],</div><div class='del'>-							   queue_types[i][0],</div><div class='del'>-							   queue_types[i][1],</div><div class='del'>-							   &amp;added_rings[k],</div><div class='del'>-							   &amp;ctx_data);</div><div class='del'>-		if (r)</div><div class='del'>-			goto error_queues;</div><div class='del'>-</div><div class='del'>-		k += queue_types[i][1];</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* start ring test and ib test for MES queues */</div><div class='del'>-	amdgpu_mes_test_queues(added_rings);</div><div class='del'>-</div><div class='del'>-error_queues:</div><div class='del'>-	/* remove all queues */</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(added_rings); i++) {</div><div class='del'>-		if (!added_rings[i])</div><div class='del'>-			continue;</div><div class='del'>-		amdgpu_mes_remove_ring(adev, added_rings[i]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(gang_ids); i++) {</div><div class='del'>-		if (!gang_ids[i])</div><div class='del'>-			continue;</div><div class='del'>-		amdgpu_mes_remove_gang(adev, gang_ids[i]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_mes_destroy_process(adev, pasid);</div><div class='del'>-</div><div class='del'>-error_vm:</div><div class='del'>-	amdgpu_mes_ctx_unmap_meta_data(adev, &amp;ctx_data);</div><div class='del'>-</div><div class='del'>-error_fini:</div><div class='del'>-	amdgpu_vm_fini(adev, vm);</div><div class='del'>-</div><div class='del'>-error_pasid:</div><div class='del'>-	if (pasid)</div><div class='del'>-		amdgpu_pasid_free(pasid);</div><div class='del'>-</div><div class='del'>-	amdgpu_mes_ctx_free_meta_data(&amp;ctx_data);</div><div class='del'>-	kfree(vm);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)</div><div class='ctx'> {</div><div class='ctx'> 	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='ctx'> 	struct amdgpu_firmware_info *info;</div><div class='ctx'> 	char ucode_prefix[30];</div><div class='del'>-	char fw_name[40];</div><div class='add'>+	char fw_name[50];</div><div class='ctx'> 	bool need_retry = false;</div><div class='add'>+	u32 *ucode_ptr;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix,</div><div class='ctx'> 				       sizeof(ucode_prefix));</div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(11, 0, 0)) {</div><div class='add'>+	if (adev-&gt;enable_uni_mes) {</div><div class='add'>+		snprintf(fw_name, sizeof(fw_name),</div><div class='add'>+			 "amdgpu/%s_uni_mes.bin", ucode_prefix);</div><div class='add'>+	} else if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(12, 0, 0)) {</div><div class='ctx'> 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes%s.bin",</div><div class='ctx'> 			 ucode_prefix,</div><div class='ctx'> 			 pipe == AMDGPU_MES_SCHED_PIPE ? "_2" : "1");</div><div class='hunk'>@@ -1488,13 +643,13 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)</div><div class='ctx'> 			 pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ucode_request(adev, &amp;adev-&gt;mes.fw[pipe], fw_name);</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;mes.fw[pipe], AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				 "%s", fw_name);</div><div class='ctx'> 	if (r &amp;&amp; need_retry &amp;&amp; pipe == AMDGPU_MES_SCHED_PIPE) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",</div><div class='del'>-			 ucode_prefix);</div><div class='del'>-		DRM_INFO("try to fall back to %s\n", fw_name);</div><div class='add'>+		dev_info(adev-&gt;dev, "try to fall back to %s_mes.bin\n", ucode_prefix);</div><div class='ctx'> 		r = amdgpu_ucode_request(adev, &amp;adev-&gt;mes.fw[pipe],</div><div class='del'>-					 fw_name);</div><div class='add'>+					 AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					 "amdgpu/%s_mes.bin", ucode_prefix);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -1508,6 +663,10 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)</div><div class='ctx'> 	adev-&gt;mes.data_start_addr[pipe] =</div><div class='ctx'> 		le32_to_cpu(mes_hdr-&gt;mes_data_start_addr_lo) |</div><div class='ctx'> 		((uint64_t)(le32_to_cpu(mes_hdr-&gt;mes_data_start_addr_hi)) &lt;&lt; 32);</div><div class='add'>+	ucode_ptr = (u32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='add'>+			  sizeof(union amdgpu_firmware_header));</div><div class='add'>+	adev-&gt;mes.fw_version[pipe] =</div><div class='add'>+		le32_to_cpu(ucode_ptr[24]) &amp; AMDGPU_MES_VERSION_MASK;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 		int ucode, ucode_data;</div><div class='hunk'>@@ -1541,6 +700,59 @@ out:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t mes_rev = adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK;</div><div class='add'>+</div><div class='add'>+	return ((amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='add'>+		 amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(12, 0, 0) &amp;&amp;</div><div class='add'>+		 mes_rev &gt;= 0x63) ||</div><div class='add'>+		amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Fix me -- node_id is used to identify the correct MES instances in the future */</div><div class='add'>+static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+					    uint32_t node_id, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct mes_misc_op_input op_input = {0};</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	op_input.op = MES_MISC_OP_CHANGE_CONFIG;</div><div class='add'>+	op_input.change_config.option.limit_single_process = enable ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='add'>+		dev_err(adev-&gt;dev, "mes change config is not supported!\n");</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to change_config.\n");</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; adev-&gt;gfx.enable_cleaner_shader) {</div><div class='add'>+		mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+		for (i = 0; i &lt; (adev-&gt;xcp_mgr ? adev-&gt;xcp_mgr-&gt;num_xcps : 1); i++) {</div><div class='add'>+			if (adev-&gt;enforce_isolation[i] == AMDGPU_ENFORCE_ISOLATION_ENABLE)</div><div class='add'>+				r |= amdgpu_mes_set_enforce_isolation(adev, i, true);</div><div class='add'>+			else</div><div class='add'>+				r |= amdgpu_mes_set_enforce_isolation(adev, i, false);</div><div class='add'>+		}</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	}</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused)</div><div class='hunk'>@@ -1549,12 +761,11 @@ static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused)</div><div class='ctx'> 	uint32_t *mem = (uint32_t *)(adev-&gt;mes.event_log_cpu_addr);</div><div class='ctx'> </div><div class='ctx'> 	seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4,</div><div class='del'>-		     mem, PAGE_SIZE, false);</div><div class='add'>+		     mem, adev-&gt;mes.event_log_size, false);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_mes_event_log);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='hunk'>@@ -1565,7 +776,7 @@ void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev)</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='ctx'> 	struct dentry *root = minor-&gt;debugfs_root;</div><div class='del'>-	if (adev-&gt;enable_mes)</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; amdgpu_mes_log_enable)</div><div class='ctx'> 		debugfs_create_file("amdgpu_mes_event_log", 0444, root,</div><div class='ctx'> 				    adev, &amp;amdgpu_debugfs_mes_event_log_fops);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h<br/>index 7d4f93fea937..e989225b354b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h</a></div><div class='hunk'>@@ -40,6 +40,8 @@</div><div class='ctx'> #define AMDGPU_MES_VERSION_MASK		0x00000fff</div><div class='ctx'> #define AMDGPU_MES_API_VERSION_MASK	0x00fff000</div><div class='ctx'> #define AMDGPU_MES_FEAT_VERSION_MASK	0xff000000</div><div class='add'>+#define AMDGPU_MES_MSCRATCH_SIZE	0x40000</div><div class='add'>+#define AMDGPU_MES_INVALID_DB_OFFSET	0xffffffff</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_mes_priority_level {</div><div class='ctx'> 	AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,</div><div class='hunk'>@@ -55,7 +57,7 @@ enum amdgpu_mes_priority_level {</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_mes_funcs;</div><div class='ctx'> </div><div class='del'>-enum admgpu_mes_pipe {</div><div class='add'>+enum amdgpu_mes_pipe {</div><div class='ctx'> 	AMDGPU_MES_SCHED_PIPE = 0,</div><div class='ctx'> 	AMDGPU_MES_KIQ_PIPE,</div><div class='ctx'> 	AMDGPU_MAX_MES_PIPES = 2,</div><div class='hunk'>@@ -75,6 +77,8 @@ struct amdgpu_mes {</div><div class='ctx'> </div><div class='ctx'> 	uint32_t			sched_version;</div><div class='ctx'> 	uint32_t			kiq_version;</div><div class='add'>+	uint32_t			fw_version[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	bool                            enable_legacy_queue_map;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t                        total_max_queue;</div><div class='ctx'> 	uint32_t                        max_doorbell_slices;</div><div class='hunk'>@@ -82,8 +86,8 @@ struct amdgpu_mes {</div><div class='ctx'> 	uint64_t                        default_process_quantum;</div><div class='ctx'> 	uint64_t                        default_gang_quantum;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_ring              ring;</div><div class='del'>-	spinlock_t                      ring_lock;</div><div class='add'>+	struct amdgpu_ring              ring[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	spinlock_t                      ring_lock[AMDGPU_MAX_MES_PIPES];</div><div class='ctx'> </div><div class='ctx'> 	const struct firmware           *fw[AMDGPU_MAX_MES_PIPES];</div><div class='ctx'> </div><div class='hunk'>@@ -108,19 +112,16 @@ struct amdgpu_mes {</div><div class='ctx'> </div><div class='ctx'> 	uint32_t                        vmid_mask_gfxhub;</div><div class='ctx'> 	uint32_t                        vmid_mask_mmhub;</div><div class='del'>-	uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];</div><div class='ctx'> 	uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];</div><div class='add'>+	uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];</div><div class='ctx'> 	uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];</div><div class='ctx'> 	uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];</div><div class='del'>-	uint32_t                        sch_ctx_offs;</div><div class='del'>-	uint64_t			sch_ctx_gpu_addr;</div><div class='del'>-	uint64_t			*sch_ctx_ptr;</div><div class='del'>-	uint32_t			query_status_fence_offs;</div><div class='del'>-	uint64_t			query_status_fence_gpu_addr;</div><div class='del'>-	uint64_t			*query_status_fence_ptr;</div><div class='del'>-	uint32_t                        read_val_offs;</div><div class='del'>-	uint64_t			read_val_gpu_addr;</div><div class='del'>-	uint32_t			*read_val_ptr;</div><div class='add'>+	uint32_t                        sch_ctx_offs[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	uint64_t			sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	uint64_t			*sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	uint32_t			query_status_fence_offs[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	uint64_t			query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	uint64_t			*query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];</div><div class='ctx'> </div><div class='ctx'> 	uint32_t			saved_flags;</div><div class='ctx'> </div><div class='hunk'>@@ -134,25 +135,24 @@ struct amdgpu_mes {</div><div class='ctx'> 	unsigned long			*doorbell_bitmap;</div><div class='ctx'> </div><div class='ctx'> 	/* MES event log buffer */</div><div class='del'>-	struct amdgpu_bo		*event_log_gpu_obj;</div><div class='del'>-	uint64_t                        event_log_gpu_addr;</div><div class='add'>+	uint32_t			event_log_size;</div><div class='add'>+	struct amdgpu_bo	*event_log_gpu_obj;</div><div class='add'>+	uint64_t			event_log_gpu_addr;</div><div class='ctx'> 	void				*event_log_cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	/* ip specific functions */</div><div class='ctx'> 	const struct amdgpu_mes_funcs   *funcs;</div><div class='del'>-};</div><div class='ctx'> </div><div class='del'>-struct amdgpu_mes_process {</div><div class='del'>-	int			pasid;</div><div class='del'>-	struct			amdgpu_vm *vm;</div><div class='del'>-	uint64_t		pd_gpu_addr;</div><div class='del'>-	struct amdgpu_bo 	*proc_ctx_bo;</div><div class='del'>-	uint64_t 		proc_ctx_gpu_addr;</div><div class='del'>-	void 			*proc_ctx_cpu_ptr;</div><div class='del'>-	uint64_t 		process_quantum;</div><div class='del'>-	struct 			list_head gang_list;</div><div class='del'>-	uint32_t 		doorbell_index;</div><div class='del'>-	struct mutex		doorbell_lock;</div><div class='add'>+	/* mes resource_1 bo*/</div><div class='add'>+	struct amdgpu_bo    *resource_1[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	uint64_t            resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+	void                *resource_1_addr[AMDGPU_MAX_MES_PIPES];</div><div class='add'>+</div><div class='add'>+	int				hung_queue_db_array_size;</div><div class='add'>+	int				hung_queue_hqd_info_offset;</div><div class='add'>+	struct amdgpu_bo		*hung_queue_db_array_gpu_obj;</div><div class='add'>+	uint64_t			hung_queue_db_array_gpu_addr;</div><div class='add'>+	void				*hung_queue_db_array_cpu_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_mes_gang {</div><div class='hunk'>@@ -239,6 +239,16 @@ struct mes_add_queue_input {</div><div class='ctx'> struct mes_remove_queue_input {</div><div class='ctx'> 	uint32_t	doorbell_offset;</div><div class='ctx'> 	uint64_t	gang_context_addr;</div><div class='add'>+	bool		remove_queue_after_reset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mes_map_legacy_queue_input {</div><div class='add'>+	uint32_t                           queue_type;</div><div class='add'>+	uint32_t                           doorbell_offset;</div><div class='add'>+	uint32_t                           pipe_id;</div><div class='add'>+	uint32_t                           queue_id;</div><div class='add'>+	uint64_t                           mqd_addr;</div><div class='add'>+	uint64_t                           wptr_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mes_unmap_legacy_queue_input {</div><div class='hunk'>@@ -263,12 +273,39 @@ struct mes_resume_gang_input {</div><div class='ctx'> 	uint64_t	gang_context_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mes_reset_queue_input {</div><div class='add'>+	uint32_t                           queue_type;</div><div class='add'>+	uint32_t                           doorbell_offset;</div><div class='add'>+	bool                               use_mmio;</div><div class='add'>+	uint32_t                           me_id;</div><div class='add'>+	uint32_t                           pipe_id;</div><div class='add'>+	uint32_t                           queue_id;</div><div class='add'>+	uint64_t                           mqd_addr;</div><div class='add'>+	uint64_t                           wptr_addr;</div><div class='add'>+	uint32_t                           vmid;</div><div class='add'>+	bool                               legacy_gfx;</div><div class='add'>+	bool                               is_kq;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mes_detect_and_reset_queue_input {</div><div class='add'>+	uint32_t                           queue_type;</div><div class='add'>+	bool                               detect_only;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mes_inv_tlbs_pasid_input {</div><div class='add'>+	uint32_t        xcc_id;</div><div class='add'>+	uint16_t        pasid;</div><div class='add'>+	uint8_t         hub_id;</div><div class='add'>+	uint8_t         flush_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum mes_misc_opcode {</div><div class='ctx'> 	MES_MISC_OP_WRITE_REG,</div><div class='ctx'> 	MES_MISC_OP_READ_REG,</div><div class='ctx'> 	MES_MISC_OP_WRM_REG_WAIT,</div><div class='ctx'> 	MES_MISC_OP_WRM_REG_WR_WAIT,</div><div class='ctx'> 	MES_MISC_OP_SET_SHADER_DEBUGGER,</div><div class='add'>+	MES_MISC_OP_CHANGE_CONFIG,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mes_misc_op_input {</div><div class='hunk'>@@ -307,6 +344,21 @@ struct mes_misc_op_input {</div><div class='ctx'> 			uint32_t tcp_watch_cntl[4];</div><div class='ctx'> 			uint32_t trap_en;</div><div class='ctx'> 		} set_shader_debugger;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			union {</div><div class='add'>+				struct {</div><div class='add'>+					uint32_t limit_single_process : 1;</div><div class='add'>+					uint32_t enable_hws_logging_buffer : 1;</div><div class='add'>+					uint32_t reserved : 30;</div><div class='add'>+				};</div><div class='add'>+				uint32_t all;</div><div class='add'>+			} option;</div><div class='add'>+			struct {</div><div class='add'>+				uint32_t tdr_level;</div><div class='add'>+				uint32_t tdr_delay;</div><div class='add'>+			} tdr_config;</div><div class='add'>+		} change_config;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -317,6 +369,9 @@ struct amdgpu_mes_funcs {</div><div class='ctx'> 	int (*remove_hw_queue)(struct amdgpu_mes *mes,</div><div class='ctx'> 			       struct mes_remove_queue_input *input);</div><div class='ctx'> </div><div class='add'>+	int (*map_legacy_queue)(struct amdgpu_mes *mes,</div><div class='add'>+				struct mes_map_legacy_queue_input *input);</div><div class='add'>+</div><div class='ctx'> 	int (*unmap_legacy_queue)(struct amdgpu_mes *mes,</div><div class='ctx'> 				  struct mes_unmap_legacy_queue_input *input);</div><div class='ctx'> </div><div class='hunk'>@@ -328,47 +383,53 @@ struct amdgpu_mes_funcs {</div><div class='ctx'> </div><div class='ctx'> 	int (*misc_op)(struct amdgpu_mes *mes,</div><div class='ctx'> 		       struct mes_misc_op_input *input);</div><div class='add'>+</div><div class='add'>+	int (*reset_hw_queue)(struct amdgpu_mes *mes,</div><div class='add'>+			      struct mes_reset_queue_input *input);</div><div class='add'>+</div><div class='add'>+	int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes,</div><div class='add'>+			      struct mes_detect_and_reset_queue_input *input);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes,</div><div class='add'>+			      struct mes_inv_tlbs_pasid_input *input);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_mes_kiq_hw_init(adev) (adev)-&gt;mes.kiq_hw_init((adev))</div><div class='ctx'> #define amdgpu_mes_kiq_hw_fini(adev) (adev)-&gt;mes.kiq_hw_fini((adev))</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);</div><div class='del'>-</div><div class='ctx'> int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);</div><div class='ctx'> int amdgpu_mes_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_mes_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,</div><div class='del'>-			      struct amdgpu_vm *vm);</div><div class='del'>-void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,</div><div class='del'>-			struct amdgpu_mes_gang_properties *gprops,</div><div class='del'>-			int *gang_id);</div><div class='del'>-int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);</div><div class='del'>-</div><div class='ctx'> int amdgpu_mes_suspend(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_mes_resume(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,</div><div class='del'>-			    struct amdgpu_mes_queue_properties *qprops,</div><div class='del'>-			    int *queue_id);</div><div class='del'>-int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);</div><div class='del'>-</div><div class='add'>+int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_ring *ring);</div><div class='ctx'> int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,</div><div class='ctx'> 				  struct amdgpu_ring *ring,</div><div class='ctx'> 				  enum amdgpu_unmap_queues_action action,</div><div class='ctx'> 				  u64 gpu_addr, u64 seq);</div><div class='add'>+int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,</div><div class='add'>+				  struct amdgpu_ring *ring,</div><div class='add'>+				  unsigned int vmid,</div><div class='add'>+				  bool use_mmio);</div><div class='add'>+</div><div class='add'>+int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,</div><div class='add'>+					    int queue_type,</div><div class='add'>+					    bool detect_only,</div><div class='add'>+					    unsigned int *hung_db_num,</div><div class='add'>+					    u32 *hung_db_array);</div><div class='ctx'> </div><div class='ctx'> uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);</div><div class='ctx'> int amdgpu_mes_wreg(struct amdgpu_device *adev,</div><div class='ctx'> 		    uint32_t reg, uint32_t val);</div><div class='del'>-int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,</div><div class='del'>-			uint32_t val, uint32_t mask);</div><div class='ctx'> int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,</div><div class='ctx'> 				  uint32_t reg0, uint32_t reg1,</div><div class='ctx'> 				  uint32_t ref, uint32_t mask);</div><div class='add'>+int amdgpu_mes_hdp_flush(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 				uint64_t process_context_addr,</div><div class='ctx'> 				uint32_t spi_gdbg_per_vmid_cntl,</div><div class='hunk'>@@ -377,27 +438,10 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 				bool trap_en);</div><div class='ctx'> int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 				uint64_t process_context_addr);</div><div class='del'>-int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,</div><div class='del'>-			int queue_type, int idx,</div><div class='del'>-			struct amdgpu_mes_ctx_data *ctx_data,</div><div class='del'>-			struct amdgpu_ring **out);</div><div class='del'>-void amdgpu_mes_remove_ring(struct amdgpu_device *adev,</div><div class='del'>-			    struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,</div><div class='ctx'> 						   enum amdgpu_mes_priority_level prio);</div><div class='ctx'> </div><div class='del'>-int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,</div><div class='del'>-				   struct amdgpu_mes_ctx_data *ctx_data);</div><div class='del'>-void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);</div><div class='del'>-int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,</div><div class='del'>-				 struct amdgpu_vm *vm,</div><div class='del'>-				 struct amdgpu_mes_ctx_data *ctx_data);</div><div class='del'>-int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,</div><div class='del'>-				   struct amdgpu_mes_ctx_data *ctx_data);</div><div class='del'>-</div><div class='del'>-int amdgpu_mes_self_test(struct amdgpu_device *adev);</div><div class='del'>-</div><div class='ctx'> int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -457,4 +501,9 @@ static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)</div><div class='ctx'> 	memalloc_noreclaim_restore(mes-&gt;saved_flags);</div><div class='ctx'> 	mutex_unlock(&amp;mes-&gt;mutex_hidden);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='ctx'> #endif /* __AMDGPU_MES_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h<br/>index 1fe21a70ddd0..dc8d2f52c7d6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h</a></div><div class='hunk'>@@ -51,6 +51,7 @@ struct amdgpu_encoder;</div><div class='ctx'> struct amdgpu_router;</div><div class='ctx'> struct amdgpu_hpd;</div><div class='ctx'> struct edid;</div><div class='add'>+struct drm_edid;</div><div class='ctx'> </div><div class='ctx'> #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)</div><div class='ctx'> #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)</div><div class='hunk'>@@ -300,6 +301,7 @@ struct amdgpu_framebuffer {</div><div class='ctx'> </div><div class='ctx'> 	uint64_t tiling_flags;</div><div class='ctx'> 	bool tmz_surface;</div><div class='add'>+	bool gfx12_dcc;</div><div class='ctx'> </div><div class='ctx'> 	/* caching for later use */</div><div class='ctx'> 	uint64_t address;</div><div class='hunk'>@@ -324,9 +326,10 @@ struct amdgpu_mode_info {</div><div class='ctx'> 	struct drm_property *audio_property;</div><div class='ctx'> 	/* FMT dithering */</div><div class='ctx'> 	struct drm_property *dither_property;</div><div class='add'>+	/* Adaptive Backlight Modulation (power feature) */</div><div class='add'>+	struct drm_property *abm_level_property;</div><div class='ctx'> 	/* hardcoded DFP edid from BIOS */</div><div class='del'>-	struct edid *bios_hardcoded_edid;</div><div class='del'>-	int bios_hardcoded_edid_size;</div><div class='add'>+	const struct drm_edid *bios_hardcoded_edid;</div><div class='ctx'> </div><div class='ctx'> 	/* firmware flags */</div><div class='ctx'> 	u32 firmware_flags;</div><div class='hunk'>@@ -495,8 +498,6 @@ struct amdgpu_crtc {</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	/* for dpm */</div><div class='ctx'> 	u32 line_time;</div><div class='del'>-	u32 wm_low;</div><div class='del'>-	u32 wm_high;</div><div class='ctx'> 	u32 lb_vblank_lead_lines;</div><div class='ctx'> 	struct drm_display_mode hw_mode;</div><div class='ctx'> 	/* for virtual dce */</div><div class='hunk'>@@ -608,6 +609,7 @@ struct amdgpu_i2c_adapter {</div><div class='ctx'> 	struct i2c_adapter base;</div><div class='ctx'> </div><div class='ctx'> 	struct ddc_service *ddc_service;</div><div class='add'>+	bool oem;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c<br/>index d085687a47ea..a974265837f0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c</a></div><div class='hunk'>@@ -53,6 +53,16 @@ u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_sriov_vf(adev) || !adev-&gt;asic_funcs ||</div><div class='add'>+	    !adev-&gt;asic_funcs-&gt;get_pcie_replay_count ||</div><div class='add'>+	    (!adev-&gt;nbio.funcs || !adev-&gt;nbio.funcs-&gt;get_pcie_replay_count))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h<br/>index 7b8c03be1d9e..b528de6a01f6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h</a></div><div class='hunk'>@@ -101,7 +101,9 @@ struct amdgpu_nbio_funcs {</div><div class='ctx'> 	int (*get_compute_partition_mode)(struct amdgpu_device *adev);</div><div class='ctx'> 	u32 (*get_memory_partition_mode)(struct amdgpu_device *adev,</div><div class='ctx'> 					 u32 *supp_modes);</div><div class='add'>+	bool (*is_nps_switch_requested)(struct amdgpu_device *adev);</div><div class='ctx'> 	u64 (*get_pcie_replay_count)(struct amdgpu_device *adev);</div><div class='add'>+	void (*set_reg_remap)(struct amdgpu_device *adev);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_nbio {</div><div class='hunk'>@@ -117,4 +119,6 @@ int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);</div><div class='ctx'> u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c<br/>index 010b0cb7693c..e08f58de4b17 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/dma-buf.h&gt;</div><div class='add'>+#include &lt;linux/export.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='hunk'>@@ -39,6 +40,9 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_trace.h"</div><div class='ctx'> #include "amdgpu_amdkfd.h"</div><div class='add'>+#include "amdgpu_vram_mgr.h"</div><div class='add'>+#include "amdgpu_vm.h"</div><div class='add'>+#include "amdgpu_dma_buf.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: amdgpu_object</div><div class='hunk'>@@ -59,7 +63,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_kunmap(bo);</div><div class='ctx'> </div><div class='del'>-	if (bo-&gt;tbo.base.import_attach)</div><div class='add'>+	if (drm_gem_is_imported(&amp;bo-&gt;tbo.base))</div><div class='ctx'> 		drm_prime_gem_destroy(&amp;bo-&gt;tbo.base, bo-&gt;tbo.sg);</div><div class='ctx'> 	drm_gem_object_release(&amp;bo-&gt;tbo.base);</div><div class='ctx'> 	amdgpu_bo_unref(&amp;bo-&gt;parent);</div><div class='hunk'>@@ -76,24 +80,6 @@ static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)</div><div class='ctx'> 	amdgpu_bo_destroy(tbo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo-&gt;bdev);</div><div class='del'>-	struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo;</div><div class='del'>-	struct amdgpu_bo_vm *vmbo;</div><div class='del'>-</div><div class='del'>-	bo = shadow_bo-&gt;parent;</div><div class='del'>-	vmbo = to_amdgpu_bo_vm(bo);</div><div class='del'>-	/* in case amdgpu_device_recover_vram got NULL of bo-&gt;parent */</div><div class='del'>-	if (!list_empty(&amp;vmbo-&gt;shadow_list)) {</div><div class='del'>-		mutex_lock(&amp;adev-&gt;shadow_list_lock);</div><div class='del'>-		list_del_init(&amp;vmbo-&gt;shadow_list);</div><div class='del'>-		mutex_unlock(&amp;adev-&gt;shadow_list_lock);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_destroy(tbo);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amp;amdgpu_bo</div><div class='ctx'>  * @bo: buffer object to be checked</div><div class='hunk'>@@ -107,8 +93,7 @@ static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)</div><div class='ctx'> bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)</div><div class='ctx'> {</div><div class='ctx'> 	if (bo-&gt;destroy == &amp;amdgpu_bo_destroy ||</div><div class='del'>-	    bo-&gt;destroy == &amp;amdgpu_bo_user_destroy ||</div><div class='del'>-	    bo-&gt;destroy == &amp;amdgpu_bo_vm_destroy)</div><div class='add'>+	    bo-&gt;destroy == &amp;amdgpu_bo_user_destroy)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -153,8 +138,10 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)</div><div class='ctx'> 		else</div><div class='ctx'> 			places[c].flags |= TTM_PL_FLAG_TOPDOWN;</div><div class='ctx'> </div><div class='del'>-		if (flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)</div><div class='add'>+		if (abo-&gt;tbo.type == ttm_bo_type_kernel &amp;&amp;</div><div class='add'>+		    flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)</div><div class='ctx'> 			places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;</div><div class='add'>+</div><div class='ctx'> 		c++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -166,6 +153,14 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)</div><div class='ctx'> 		c++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (domain &amp; AMDGPU_GEM_DOMAIN_MMIO_REMAP) {</div><div class='add'>+		places[c].fpfn = 0;</div><div class='add'>+		places[c].lpfn = 0;</div><div class='add'>+		places[c].mem_type = AMDGPU_PL_MMIO_REMAP;</div><div class='add'>+		places[c].flags = 0;</div><div class='add'>+		c++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (domain &amp; AMDGPU_GEM_DOMAIN_GTT) {</div><div class='ctx'> 		places[c].fpfn = 0;</div><div class='ctx'> 		places[c].lpfn = 0;</div><div class='hunk'>@@ -173,6 +168,13 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)</div><div class='ctx'> 			abo-&gt;flags &amp; AMDGPU_GEM_CREATE_PREEMPTIBLE ?</div><div class='ctx'> 			AMDGPU_PL_PREEMPT : TTM_PL_TT;</div><div class='ctx'> 		places[c].flags = 0;</div><div class='add'>+		/*</div><div class='add'>+		 * When GTT is just an alternative to VRAM make sure that we</div><div class='add'>+		 * only use it as fallback and still try to fill up VRAM first.</div><div class='add'>+		 */</div><div class='add'>+		if (abo-&gt;tbo.resource &amp;&amp; !(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp;</div><div class='add'>+		    domain &amp; abo-&gt;preferred_domains &amp; AMDGPU_GEM_DOMAIN_VRAM)</div><div class='add'>+			places[c].flags |= TTM_PL_FLAG_FALLBACK;</div><div class='ctx'> 		c++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -332,6 +334,9 @@ error_free:</div><div class='ctx'>  *</div><div class='ctx'>  * Allocates and pins a BO for kernel internal use.</div><div class='ctx'>  *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device</div><div class='add'>+ * external to drm device to create and access the kernel BO.</div><div class='add'>+ *</div><div class='ctx'>  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.</div><div class='ctx'>  *</div><div class='ctx'>  * Returns:</div><div class='hunk'>@@ -357,6 +362,74 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_bo_create_isp_user - create user BO for isp</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu device object</div><div class='add'>+ * @dma_buf: DMABUF handle for isp buffer</div><div class='add'>+ * @domain: where to place it</div><div class='add'>+ * @bo:  used to initialize BOs in structures</div><div class='add'>+ * @gpu_addr: GPU addr of the pinned BO</div><div class='add'>+ *</div><div class='add'>+ * Imports isp DMABUF to allocate and pin a user BO for isp internal use. It does</div><div class='add'>+ * GART alloc to generate gpu_addr for BO to make it accessible through the</div><div class='add'>+ * GART aperture for ISP HW.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device external to drm device</div><div class='add'>+ * to create and access the isp user BO.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_bo_create_isp_user(struct amdgpu_device *adev,</div><div class='add'>+			   struct dma_buf *dma_buf, u32 domain, struct amdgpu_bo **bo,</div><div class='add'>+			   u64 *gpu_addr)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *gem_obj;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	gem_obj = amdgpu_gem_prime_import(&amp;adev-&gt;ddev, dma_buf);</div><div class='add'>+	*bo = gem_to_amdgpu_bo(gem_obj);</div><div class='add'>+	if (!(*bo)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to get valid isp user bo\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(*bo, false);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to reserve isp user bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_pin(*bo, domain);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) isp user bo pin failed\n", r);</div><div class='add'>+		goto error_unreserve;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ttm_alloc_gart(&amp;(*bo)-&gt;tbo);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "%p bind failed\n", *bo);</div><div class='add'>+		goto error_unpin;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!WARN_ON(!gpu_addr))</div><div class='add'>+		*gpu_addr = amdgpu_bo_gpu_offset(*bo);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(*bo);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_unpin:</div><div class='add'>+	amdgpu_bo_unpin(*bo);</div><div class='add'>+error_unreserve:</div><div class='add'>+	amdgpu_bo_unreserve(*bo);</div><div class='add'>+	amdgpu_bo_unref(bo);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu device object</div><div class='hunk'>@@ -431,6 +504,9 @@ error:</div><div class='ctx'>  * @cpu_addr: pointer to where the BO's CPU memory space address was stored</div><div class='ctx'>  *</div><div class='ctx'>  * unmaps and unpin a BO for kernel internal use.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device</div><div class='add'>+ * external to drm device to free the kernel BO.</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,</div><div class='ctx'> 			   void **cpu_addr)</div><div class='hunk'>@@ -456,6 +532,28 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,</div><div class='ctx'> 		*cpu_addr = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_bo_free_isp_user - free BO for isp use</div><div class='add'>+ *</div><div class='add'>+ * @bo: amdgpu isp user BO to free</div><div class='add'>+ *</div><div class='add'>+ * unpin and unref BO for isp internal use.</div><div class='add'>+ *</div><div class='add'>+ * This function is exported to allow the V4L2 isp device</div><div class='add'>+ * external to drm device to free the isp user BO.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_bo_free_isp_user(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_bo_reserve(bo, true) == 0) {</div><div class='add'>+		amdgpu_bo_unpin(bo);</div><div class='add'>+		amdgpu_bo_unreserve(bo);</div><div class='add'>+	}</div><div class='add'>+	amdgpu_bo_unref(&amp;bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Validate bo size is bit bigger than the request domain */</div><div class='ctx'> static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,</div><div class='ctx'> 					  unsigned long size, u32 domain)</div><div class='hunk'>@@ -574,6 +672,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,</div><div class='ctx'> 	if (bo == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	drm_gem_private_object_init(adev_to_drm(adev), &amp;bo-&gt;tbo.base, size);</div><div class='add'>+	bo-&gt;tbo.base.funcs = &amp;amdgpu_gem_object_funcs;</div><div class='ctx'> 	bo-&gt;vm_bo = NULL;</div><div class='ctx'> 	bo-&gt;preferred_domains = bp-&gt;preferred_domain ? bp-&gt;preferred_domain :</div><div class='ctx'> 		bp-&gt;domain;</div><div class='hunk'>@@ -595,9 +694,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!amdgpu_bo_support_uswc(bo-&gt;flags))</div><div class='ctx'> 		bo-&gt;flags &amp;= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;ras_enabled)</div><div class='del'>-		bo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;</div><div class='del'>-</div><div class='ctx'> 	bo-&gt;tbo.bdev = &amp;adev-&gt;mman.bdev;</div><div class='ctx'> 	if (bp-&gt;domain &amp; (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |</div><div class='ctx'> 			  AMDGPU_GEM_DOMAIN_GDS))</div><div class='hunk'>@@ -605,6 +701,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,</div><div class='ctx'> 	else</div><div class='ctx'> 		amdgpu_bo_placement_from_domain(bo, bp-&gt;domain);</div><div class='ctx'> 	if (bp-&gt;type == ttm_bo_type_kernel)</div><div class='add'>+		bo-&gt;tbo.priority = 2;</div><div class='add'>+	else if (!(bp-&gt;flags &amp; AMDGPU_GEM_CREATE_DISCARDABLE))</div><div class='ctx'> 		bo-&gt;tbo.priority = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (!bp-&gt;destroy)</div><div class='hunk'>@@ -617,8 +715,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_gmc_vram_full_visible(&amp;adev-&gt;gmc) &amp;&amp;</div><div class='del'>-	    bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM &amp;&amp;</div><div class='del'>-	    amdgpu_bo_in_cpu_visible_vram(bo))</div><div class='add'>+	    amdgpu_res_cpu_visible(adev, bo-&gt;tbo.resource))</div><div class='ctx'> 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,</div><div class='ctx'> 					     ctx.bytes_moved);</div><div class='ctx'> 	else</div><div class='hunk'>@@ -628,7 +725,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,</div><div class='ctx'> 	    bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM) {</div><div class='ctx'> 		struct dma_fence *fence;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_fill_buffer(bo, 0, bo-&gt;tbo.base.resv, &amp;fence, true);</div><div class='add'>+		r = amdgpu_ttm_clear_buffer(bo, bo-&gt;tbo.base.resv, &amp;fence);</div><div class='ctx'> 		if (unlikely(r))</div><div class='ctx'> 			goto fail_unreserve;</div><div class='ctx'> </div><div class='hunk'>@@ -716,52 +813,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list</div><div class='del'>- *</div><div class='del'>- * @vmbo: BO that will be inserted into the shadow list</div><div class='del'>- *</div><div class='del'>- * Insert a BO to the shadow list.</div><div class='del'>- */</div><div class='del'>-void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo-&gt;bo.tbo.bdev);</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;adev-&gt;shadow_list_lock);</div><div class='del'>-	list_add_tail(&amp;vmbo-&gt;shadow_list, &amp;adev-&gt;shadow_list);</div><div class='del'>-	vmbo-&gt;shadow-&gt;parent = amdgpu_bo_ref(&amp;vmbo-&gt;bo);</div><div class='del'>-	vmbo-&gt;shadow-&gt;tbo.destroy = &amp;amdgpu_bo_vm_destroy;</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;shadow_list_lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * amdgpu_bo_restore_shadow - restore an &amp;amdgpu_bo shadow</div><div class='del'>- *</div><div class='del'>- * @shadow: &amp;amdgpu_bo shadow to be restored</div><div class='del'>- * @fence: dma_fence associated with the operation</div><div class='del'>- *</div><div class='del'>- * Copies a buffer object's shadow content back to the object.</div><div class='del'>- * This is used for recovering a buffer from its shadow in case of a gpu</div><div class='del'>- * reset where vram context may be lost.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- * 0 for success or a negative error code on failure.</div><div class='del'>- */</div><div class='del'>-int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)</div><div class='del'>-</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = amdgpu_ttm_adev(shadow-&gt;tbo.bdev);</div><div class='del'>-	struct amdgpu_ring *ring = adev-&gt;mman.buffer_funcs_ring;</div><div class='del'>-	uint64_t shadow_addr, parent_addr;</div><div class='del'>-</div><div class='del'>-	shadow_addr = amdgpu_bo_gpu_offset(shadow);</div><div class='del'>-	parent_addr = amdgpu_bo_gpu_offset(shadow-&gt;parent);</div><div class='del'>-</div><div class='del'>-	return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,</div><div class='del'>-				  amdgpu_bo_size(shadow), NULL, fence,</div><div class='del'>-				  true, false, false);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * amdgpu_bo_kmap - map an &amp;amdgpu_bo buffer object</div><div class='ctx'>  * @bo: &amp;amdgpu_bo buffer object to be mapped</div><div class='ctx'>  * @ptr: kernel virtual address to be returned</div><div class='hunk'>@@ -844,7 +895,7 @@ struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)</div><div class='ctx'> 	if (bo == NULL)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	ttm_bo_get(&amp;bo-&gt;tbo);</div><div class='add'>+	drm_gem_object_get(&amp;bo-&gt;tbo.base);</div><div class='ctx'> 	return bo;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -856,40 +907,30 @@ struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_bo_unref(struct amdgpu_bo **bo)</div><div class='ctx'> {</div><div class='del'>-	struct ttm_buffer_object *tbo;</div><div class='del'>-</div><div class='ctx'> 	if ((*bo) == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	tbo = &amp;((*bo)-&gt;tbo);</div><div class='del'>-	ttm_bo_put(tbo);</div><div class='add'>+	drm_gem_object_put(&amp;(*bo)-&gt;tbo.base);</div><div class='ctx'> 	*bo = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_bo_pin_restricted - pin an &amp;amdgpu_bo buffer object</div><div class='add'>+ * amdgpu_bo_pin - pin an &amp;amdgpu_bo buffer object</div><div class='ctx'>  * @bo: &amp;amdgpu_bo buffer object to be pinned</div><div class='ctx'>  * @domain: domain to be pinned to</div><div class='del'>- * @min_offset: the start of requested address range</div><div class='del'>- * @max_offset: the end of requested address range</div><div class='ctx'>  *</div><div class='del'>- * Pins the buffer object according to requested domain and address range. If</div><div class='del'>- * the memory is unbound gart memory, binds the pages into gart table. Adjusts</div><div class='del'>- * pin_count and pin_size accordingly.</div><div class='add'>+ * Pins the buffer object according to requested domain. If the memory is</div><div class='add'>+ * unbound gart memory, binds the pages into gart table. Adjusts pin_count and</div><div class='add'>+ * pin_size accordingly.</div><div class='ctx'>  *</div><div class='ctx'>  * Pinning means to lock pages in memory along with keeping them at a fixed</div><div class='ctx'>  * offset. It is required when a buffer can not be moved, for example, when</div><div class='ctx'>  * a display buffer is being scanned out.</div><div class='ctx'>  *</div><div class='del'>- * Compared with amdgpu_bo_pin(), this function gives more flexibility on</div><div class='del'>- * where to pin a buffer if there are specific restrictions on where a buffer</div><div class='del'>- * must be located.</div><div class='del'>- *</div><div class='ctx'>  * Returns:</div><div class='ctx'>  * 0 for success or a negative error code on failure.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='del'>-			     u64 min_offset, u64 max_offset)</div><div class='add'>+int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='ctx'> 	struct ttm_operation_ctx ctx = { false, false };</div><div class='hunk'>@@ -898,15 +939,12 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='ctx'> 	if (amdgpu_ttm_tt_get_usermm(bo-&gt;tbo.ttm))</div><div class='ctx'> 		return -EPERM;</div><div class='ctx'> </div><div class='del'>-	if (WARN_ON_ONCE(min_offset &gt; max_offset))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 	/* Check domain to be pinned to against preferred domains */</div><div class='ctx'> 	if (bo-&gt;preferred_domains &amp; domain)</div><div class='ctx'> 		domain = bo-&gt;preferred_domains &amp; domain;</div><div class='ctx'> </div><div class='ctx'> 	/* A shared bo cannot be migrated to VRAM */</div><div class='del'>-	if (bo-&gt;tbo.base.import_attach) {</div><div class='add'>+	if (drm_gem_is_imported(&amp;bo-&gt;tbo.base)) {</div><div class='ctx'> 		if (domain &amp; AMDGPU_GEM_DOMAIN_GTT)</div><div class='ctx'> 			domain = AMDGPU_GEM_DOMAIN_GTT;</div><div class='ctx'> 		else</div><div class='hunk'>@@ -926,14 +964,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		ttm_bo_pin(&amp;bo-&gt;tbo);</div><div class='del'>-</div><div class='del'>-		if (max_offset != 0) {</div><div class='del'>-			u64 domain_start = amdgpu_ttm_domain_start(adev,</div><div class='del'>-								   mem_type);</div><div class='del'>-			WARN_ON_ONCE(max_offset &lt;</div><div class='del'>-				     (amdgpu_bo_gpu_offset(bo) - domain_start));</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -942,7 +972,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='ctx'> 	 */</div><div class='ctx'> 	domain = amdgpu_bo_get_preferred_domain(adev, domain);</div><div class='ctx'> </div><div class='del'>-	if (bo-&gt;tbo.base.import_attach)</div><div class='add'>+	if (drm_gem_is_imported(&amp;bo-&gt;tbo.base))</div><div class='ctx'> 		dma_buf_pin(bo-&gt;tbo.base.import_attach);</div><div class='ctx'> </div><div class='ctx'> 	/* force to pin into visible video ram */</div><div class='hunk'>@@ -950,16 +980,9 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='ctx'> 		bo-&gt;flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;</div><div class='ctx'> 	amdgpu_bo_placement_from_domain(bo, domain);</div><div class='ctx'> 	for (i = 0; i &lt; bo-&gt;placement.num_placement; i++) {</div><div class='del'>-		unsigned int fpfn, lpfn;</div><div class='del'>-</div><div class='del'>-		fpfn = min_offset &gt;&gt; PAGE_SHIFT;</div><div class='del'>-		lpfn = max_offset &gt;&gt; PAGE_SHIFT;</div><div class='del'>-</div><div class='del'>-		if (fpfn &gt; bo-&gt;placements[i].fpfn)</div><div class='del'>-			bo-&gt;placements[i].fpfn = fpfn;</div><div class='del'>-		if (!bo-&gt;placements[i].lpfn ||</div><div class='del'>-		    (lpfn &amp;&amp; lpfn &lt; bo-&gt;placements[i].lpfn))</div><div class='del'>-			bo-&gt;placements[i].lpfn = lpfn;</div><div class='add'>+		if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &amp;&amp;</div><div class='add'>+		    bo-&gt;placements[i].mem_type == TTM_PL_VRAM)</div><div class='add'>+			bo-&gt;placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='hunk'>@@ -970,12 +993,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='ctx'> </div><div class='ctx'> 	ttm_bo_pin(&amp;bo-&gt;tbo);</div><div class='ctx'> </div><div class='del'>-	domain = amdgpu_mem_type_to_domain(bo-&gt;tbo.resource-&gt;mem_type);</div><div class='del'>-	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {</div><div class='add'>+	if (bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM) {</div><div class='ctx'> 		atomic64_add(amdgpu_bo_size(bo), &amp;adev-&gt;vram_pin_size);</div><div class='ctx'> 		atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),</div><div class='ctx'> 			     &amp;adev-&gt;visible_pin_size);</div><div class='del'>-	} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {</div><div class='add'>+	} else if (bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_TT) {</div><div class='ctx'> 		atomic64_add(amdgpu_bo_size(bo), &amp;adev-&gt;gart_pin_size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -984,24 +1006,6 @@ error:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_bo_pin - pin an &amp;amdgpu_bo buffer object</div><div class='del'>- * @bo: &amp;amdgpu_bo buffer object to be pinned</div><div class='del'>- * @domain: domain to be pinned to</div><div class='del'>- *</div><div class='del'>- * A simple wrapper to amdgpu_bo_pin_restricted().</div><div class='del'>- * Provides a simpler API for buffers that do not have any strict restrictions</div><div class='del'>- * on where a buffer must be located.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- * 0 for success or a negative error code on failure.</div><div class='del'>- */</div><div class='del'>-int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)</div><div class='del'>-{</div><div class='del'>-	bo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='del'>-	return amdgpu_bo_pin_restricted(bo, domain, 0, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * amdgpu_bo_unpin - unpin an &amp;amdgpu_bo buffer object</div><div class='ctx'>  * @bo: &amp;amdgpu_bo buffer object to be unpinned</div><div class='ctx'>  *</div><div class='hunk'>@@ -1019,7 +1023,7 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo)</div><div class='ctx'> 	if (bo-&gt;tbo.pin_count)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (bo-&gt;tbo.base.import_attach)</div><div class='add'>+	if (drm_gem_is_imported(&amp;bo-&gt;tbo.base))</div><div class='ctx'> 		dma_buf_unpin(bo-&gt;tbo.base.import_attach);</div><div class='ctx'> </div><div class='ctx'> 	if (bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM) {</div><div class='hunk'>@@ -1045,7 +1049,8 @@ static const char * const amdgpu_vram_names[] = {</div><div class='ctx'> 	"GDDR6",</div><div class='ctx'> 	"DDR5",</div><div class='ctx'> 	"LPDDR4",</div><div class='del'>-	"LPDDR5"</div><div class='add'>+	"LPDDR5",</div><div class='add'>+	"HBM3E"</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1242,83 +1247,34 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,</div><div class='ctx'>  * amdgpu_bo_move_notify - notification about a memory move</div><div class='ctx'>  * @bo: pointer to a buffer object</div><div class='ctx'>  * @evict: if this move is evicting the buffer from the graphics address space</div><div class='add'>+ * @new_mem: new resource for backing the BO</div><div class='ctx'>  *</div><div class='ctx'>  * Marks the corresponding &amp;amdgpu_bo buffer object as invalid, also performs</div><div class='ctx'>  * bookkeeping.</div><div class='ctx'>  * TTM driver callback which is called when ttm moves a buffer.</div><div class='ctx'>  */</div><div class='del'>-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)</div><div class='add'>+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,</div><div class='add'>+			   bool evict,</div><div class='add'>+			   struct ttm_resource *new_mem)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;bdev);</div><div class='add'>+	struct ttm_resource *old_mem = bo-&gt;resource;</div><div class='ctx'> 	struct amdgpu_bo *abo;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_bo_is_amdgpu_bo(bo))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	abo = ttm_to_amdgpu_bo(bo);</div><div class='del'>-	amdgpu_vm_bo_invalidate(adev, abo, evict);</div><div class='add'>+	amdgpu_vm_bo_move(abo, new_mem, evict);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_kunmap(abo);</div><div class='ctx'> </div><div class='del'>-	if (abo-&gt;tbo.base.dma_buf &amp;&amp; !abo-&gt;tbo.base.import_attach &amp;&amp;</div><div class='del'>-	    bo-&gt;resource-&gt;mem_type != TTM_PL_SYSTEM)</div><div class='add'>+	if (abo-&gt;tbo.base.dma_buf &amp;&amp; !drm_gem_is_imported(&amp;abo-&gt;tbo.base) &amp;&amp;</div><div class='add'>+	    old_mem &amp;&amp; old_mem-&gt;mem_type != TTM_PL_SYSTEM)</div><div class='ctx'> 		dma_buf_move_notify(abo-&gt;tbo.base.dma_buf);</div><div class='ctx'> </div><div class='del'>-	/* remember the eviction */</div><div class='del'>-	if (evict)</div><div class='del'>-		atomic64_inc(&amp;adev-&gt;num_evictions);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void amdgpu_bo_get_memory(struct amdgpu_bo *bo,</div><div class='del'>-			  struct amdgpu_mem_stats *stats)</div><div class='del'>-{</div><div class='del'>-	uint64_t size = amdgpu_bo_size(bo);</div><div class='del'>-	struct drm_gem_object *obj;</div><div class='del'>-	unsigned int domain;</div><div class='del'>-	bool shared;</div><div class='del'>-</div><div class='del'>-	/* Abort if the BO doesn't currently have a backing store */</div><div class='del'>-	if (!bo-&gt;tbo.resource)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	obj = &amp;bo-&gt;tbo.base;</div><div class='del'>-	shared = drm_gem_object_is_shared_for_memory_stats(obj);</div><div class='del'>-</div><div class='del'>-	domain = amdgpu_mem_type_to_domain(bo-&gt;tbo.resource-&gt;mem_type);</div><div class='del'>-	switch (domain) {</div><div class='del'>-	case AMDGPU_GEM_DOMAIN_VRAM:</div><div class='del'>-		stats-&gt;vram += size;</div><div class='del'>-		if (amdgpu_bo_in_cpu_visible_vram(bo))</div><div class='del'>-			stats-&gt;visible_vram += size;</div><div class='del'>-		if (shared)</div><div class='del'>-			stats-&gt;vram_shared += size;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_GEM_DOMAIN_GTT:</div><div class='del'>-		stats-&gt;gtt += size;</div><div class='del'>-		if (shared)</div><div class='del'>-			stats-&gt;gtt_shared += size;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_GEM_DOMAIN_CPU:</div><div class='del'>-	default:</div><div class='del'>-		stats-&gt;cpu += size;</div><div class='del'>-		if (shared)</div><div class='del'>-			stats-&gt;cpu_shared += size;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (bo-&gt;preferred_domains &amp; AMDGPU_GEM_DOMAIN_VRAM) {</div><div class='del'>-		stats-&gt;requested_vram += size;</div><div class='del'>-		if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)</div><div class='del'>-			stats-&gt;requested_visible_vram += size;</div><div class='del'>-</div><div class='del'>-		if (domain != AMDGPU_GEM_DOMAIN_VRAM) {</div><div class='del'>-			stats-&gt;evicted_vram += size;</div><div class='del'>-			if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)</div><div class='del'>-				stats-&gt;evicted_visible_vram += size;</div><div class='del'>-		}</div><div class='del'>-	} else if (bo-&gt;preferred_domains &amp; AMDGPU_GEM_DOMAIN_GTT) {</div><div class='del'>-		stats-&gt;requested_gtt += size;</div><div class='del'>-	}</div><div class='add'>+	/* move_notify is called before move happens */</div><div class='add'>+	trace_amdgpu_bo_move(abo, new_mem ? new_mem-&gt;mem_type : -1,</div><div class='add'>+			     old_mem ? old_mem-&gt;mem_type : -1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1345,27 +1301,37 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)</div><div class='ctx'> 	if (abo-&gt;kfd_bo)</div><div class='ctx'> 		amdgpu_amdkfd_release_notify(abo);</div><div class='ctx'> </div><div class='del'>-	/* We only remove the fence if the resv has individualized. */</div><div class='del'>-	WARN_ON_ONCE(bo-&gt;type == ttm_bo_type_kernel</div><div class='del'>-			&amp;&amp; bo-&gt;base.resv != &amp;bo-&gt;base._resv);</div><div class='del'>-	if (bo-&gt;base.resv == &amp;bo-&gt;base._resv)</div><div class='del'>-		amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);</div><div class='add'>+	/*</div><div class='add'>+	 * We lock the private dma_resv object here and since the BO is about to</div><div class='add'>+	 * be released nobody else should have a pointer to it.</div><div class='add'>+	 * So when this locking here fails something is wrong with the reference</div><div class='add'>+	 * counting.</div><div class='add'>+	 */</div><div class='add'>+	if (WARN_ON_ONCE(!dma_resv_trylock(&amp;bo-&gt;base._resv)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_amdkfd_remove_all_eviction_fences(abo);</div><div class='ctx'> </div><div class='ctx'> 	if (!bo-&gt;resource || bo-&gt;resource-&gt;mem_type != TTM_PL_VRAM ||</div><div class='ctx'> 	    !(abo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||</div><div class='ctx'> 	    adev-&gt;in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))</div><div class='del'>-		return;</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='del'>-	if (WARN_ON_ONCE(!dma_resv_trylock(bo-&gt;base.resv)))</div><div class='del'>-		return;</div><div class='add'>+	r = dma_resv_reserve_fences(&amp;bo-&gt;base._resv, 1);</div><div class='add'>+	if (r)</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo-&gt;base.resv, &amp;fence, true);</div><div class='del'>-	if (!WARN_ON(r)) {</div><div class='del'>-		amdgpu_bo_fence(abo, fence, false);</div><div class='del'>-		dma_fence_put(fence);</div><div class='del'>-	}</div><div class='add'>+	r = amdgpu_fill_buffer(abo, 0, &amp;bo-&gt;base._resv, &amp;fence, true,</div><div class='add'>+			       AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);</div><div class='add'>+	if (WARN_ON(r))</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='del'>-	dma_resv_unlock(bo-&gt;base.resv);</div><div class='add'>+	amdgpu_vram_mgr_set_cleared(bo-&gt;resource);</div><div class='add'>+	dma_resv_add_fence(&amp;bo-&gt;base._resv, fence, DMA_RESV_USAGE_KERNEL);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	dma_resv_unlock(&amp;bo-&gt;base._resv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1389,10 +1355,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)</div><div class='ctx'> 	/* Remember that this BO was accessed by the CPU */</div><div class='ctx'> 	abo-&gt;flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;</div><div class='ctx'> </div><div class='del'>-	if (bo-&gt;resource-&gt;mem_type != TTM_PL_VRAM)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_bo_in_cpu_visible_vram(abo))</div><div class='add'>+	if (amdgpu_res_cpu_visible(adev, bo-&gt;resource))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Can't move a pinned BO to visible VRAM */</div><div class='hunk'>@@ -1415,7 +1378,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)</div><div class='ctx'> </div><div class='ctx'> 	/* this should never happen */</div><div class='ctx'> 	if (bo-&gt;resource-&gt;mem_type == TTM_PL_VRAM &amp;&amp;</div><div class='del'>-	    !amdgpu_bo_in_cpu_visible_vram(abo))</div><div class='add'>+	    !amdgpu_res_cpu_visible(adev, bo-&gt;resource))</div><div class='ctx'> 		return VM_FAULT_SIGBUS;</div><div class='ctx'> </div><div class='ctx'> 	ttm_bo_move_to_lru_tail_unlocked(bo);</div><div class='hunk'>@@ -1516,6 +1479,26 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_bo_fb_aper_addr - return FB aperture GPU offset of the VRAM bo</div><div class='add'>+ * @bo:	amdgpu VRAM buffer object for which we query the offset</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * current FB aperture GPU offset of the object.</div><div class='add'>+ */</div><div class='add'>+u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='add'>+	uint64_t offset, fb_base;</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(bo-&gt;tbo.resource-&gt;mem_type != TTM_PL_VRAM);</div><div class='add'>+</div><div class='add'>+	fb_base = adev-&gt;gmc.fb_start;</div><div class='add'>+	fb_base += adev-&gt;gmc.xgmi.physical_node_id * adev-&gt;gmc.xgmi.node_segment_size;</div><div class='add'>+	offset = (bo-&gt;tbo.resource-&gt;start &lt;&lt; PAGE_SHIFT) + fb_base;</div><div class='add'>+	return amdgpu_gmc_sign_extend(offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo</div><div class='ctx'>  * @bo:	amdgpu object for which we query the offset</div><div class='ctx'>  *</div><div class='hunk'>@@ -1538,6 +1521,47 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_bo_mem_stats_placement - bo placement for memory accounting</div><div class='add'>+ * @bo:	the buffer object we should look at</div><div class='add'>+ *</div><div class='add'>+ * BO can have multiple preferred placements, to avoid double counting we want</div><div class='add'>+ * to file it under a single placement for memory stats.</div><div class='add'>+ * Luckily, if we take the highest set bit in preferred_domains the result is</div><div class='add'>+ * quite sensible.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * Which of the placements should the BO be accounted under.</div><div class='add'>+ */</div><div class='add'>+uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	uint32_t domain = bo-&gt;preferred_domains &amp; AMDGPU_GEM_DOMAIN_MASK;</div><div class='add'>+</div><div class='add'>+	if (!domain)</div><div class='add'>+		return TTM_PL_SYSTEM;</div><div class='add'>+</div><div class='add'>+	switch (rounddown_pow_of_two(domain)) {</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_CPU:</div><div class='add'>+		return TTM_PL_SYSTEM;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_GTT:</div><div class='add'>+		return TTM_PL_TT;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_VRAM:</div><div class='add'>+		return TTM_PL_VRAM;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_GDS:</div><div class='add'>+		return AMDGPU_PL_GDS;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_GWS:</div><div class='add'>+		return AMDGPU_PL_GWS;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_OA:</div><div class='add'>+		return AMDGPU_PL_OA;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_DOORBELL:</div><div class='add'>+		return AMDGPU_PL_DOORBELL;</div><div class='add'>+	case AMDGPU_GEM_DOMAIN_MMIO_REMAP:</div><div class='add'>+		return AMDGPU_PL_MMIO_REMAP;</div><div class='add'>+	default:</div><div class='add'>+		return TTM_PL_SYSTEM;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_bo_get_preferred_domain - get preferred domain</div><div class='ctx'>  * @adev: amdgpu device object</div><div class='ctx'>  * @domain: allowed :ref:`memory domains &lt;amdgpu_memory_domains&gt;`</div><div class='hunk'>@@ -1579,6 +1603,7 @@ uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,</div><div class='ctx'>  */</div><div class='ctx'> u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='ctx'> 	struct dma_buf_attachment *attachment;</div><div class='ctx'> 	struct dma_buf *dma_buf;</div><div class='ctx'> 	const char *placement;</div><div class='hunk'>@@ -1586,22 +1611,42 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)</div><div class='ctx'> 	u64 size;</div><div class='ctx'> </div><div class='ctx'> 	if (dma_resv_trylock(bo-&gt;tbo.base.resv)) {</div><div class='del'>-		unsigned int domain;</div><div class='del'>-		domain = amdgpu_mem_type_to_domain(bo-&gt;tbo.resource-&gt;mem_type);</div><div class='del'>-		switch (domain) {</div><div class='del'>-		case AMDGPU_GEM_DOMAIN_VRAM:</div><div class='del'>-			if (amdgpu_bo_in_cpu_visible_vram(bo))</div><div class='del'>-				placement = "VRAM VISIBLE";</div><div class='del'>-			else</div><div class='del'>-				placement = "VRAM";</div><div class='del'>-			break;</div><div class='del'>-		case AMDGPU_GEM_DOMAIN_GTT:</div><div class='del'>-			placement = "GTT";</div><div class='del'>-			break;</div><div class='del'>-		case AMDGPU_GEM_DOMAIN_CPU:</div><div class='del'>-		default:</div><div class='del'>-			placement = "CPU";</div><div class='del'>-			break;</div><div class='add'>+		if (!bo-&gt;tbo.resource) {</div><div class='add'>+			placement = "NONE";</div><div class='add'>+		} else {</div><div class='add'>+			switch (bo-&gt;tbo.resource-&gt;mem_type) {</div><div class='add'>+			case TTM_PL_VRAM:</div><div class='add'>+				if (amdgpu_res_cpu_visible(adev, bo-&gt;tbo.resource))</div><div class='add'>+					placement = "VRAM VISIBLE";</div><div class='add'>+				else</div><div class='add'>+					placement = "VRAM";</div><div class='add'>+				break;</div><div class='add'>+			case TTM_PL_TT:</div><div class='add'>+				placement = "GTT";</div><div class='add'>+				break;</div><div class='add'>+			case AMDGPU_PL_GDS:</div><div class='add'>+				placement = "GDS";</div><div class='add'>+				break;</div><div class='add'>+			case AMDGPU_PL_GWS:</div><div class='add'>+				placement = "GWS";</div><div class='add'>+				break;</div><div class='add'>+			case AMDGPU_PL_OA:</div><div class='add'>+				placement = "OA";</div><div class='add'>+				break;</div><div class='add'>+			case AMDGPU_PL_PREEMPT:</div><div class='add'>+				placement = "PREEMPTIBLE";</div><div class='add'>+				break;</div><div class='add'>+			case AMDGPU_PL_DOORBELL:</div><div class='add'>+				placement = "DOORBELL";</div><div class='add'>+				break;</div><div class='add'>+			case AMDGPU_PL_MMIO_REMAP:</div><div class='add'>+				placement = "MMIO REMAP";</div><div class='add'>+				break;</div><div class='add'>+			case TTM_PL_SYSTEM:</div><div class='add'>+			default:</div><div class='add'>+				placement = "CPU";</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 		dma_resv_unlock(bo-&gt;tbo.base.resv);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1631,7 +1676,11 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)</div><div class='ctx'> 	amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);</div><div class='ctx'> 	amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);</div><div class='ctx'> 	amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);</div><div class='del'>-</div><div class='add'>+	/* Add the gem obj resv fence dump*/</div><div class='add'>+	if (dma_resv_trylock(bo-&gt;tbo.base.resv)) {</div><div class='add'>+		dma_resv_describe(bo-&gt;tbo.base.resv, m);</div><div class='add'>+		dma_resv_unlock(bo-&gt;tbo.base.resv);</div><div class='add'>+	}</div><div class='ctx'> 	seq_puts(m, "\n");</div><div class='ctx'> </div><div class='ctx'> 	return size;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h<br/>index be679c42b0b8..52c2d1731aab 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h</a></div><div class='hunk'>@@ -69,7 +69,7 @@ struct amdgpu_bo_va_mapping {</div><div class='ctx'> 	uint64_t			last;</div><div class='ctx'> 	uint64_t			__subtree_last;</div><div class='ctx'> 	uint64_t			offset;</div><div class='del'>-	uint64_t			flags;</div><div class='add'>+	uint32_t			flags;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* User space allocated BO in a VM */</div><div class='hunk'>@@ -90,6 +90,13 @@ struct amdgpu_bo_va {</div><div class='ctx'> 	bool				cleared;</div><div class='ctx'> </div><div class='ctx'> 	bool				is_xgmi;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * protected by vm reservation lock</div><div class='add'>+	 * if non-zero, cannot unmap from GPU because user queues may still access it</div><div class='add'>+	 */</div><div class='add'>+	unsigned int			queue_refcount;</div><div class='add'>+	atomic_t			userq_va_mapped;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_bo {</div><div class='hunk'>@@ -130,38 +137,9 @@ struct amdgpu_bo_user {</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_bo_vm {</div><div class='ctx'> 	struct amdgpu_bo		bo;</div><div class='del'>-	struct amdgpu_bo		*shadow;</div><div class='del'>-	struct list_head		shadow_list;</div><div class='ctx'> 	struct amdgpu_vm_bo_base        entries[];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct amdgpu_mem_stats {</div><div class='del'>-	/* current VRAM usage, includes visible VRAM */</div><div class='del'>-	uint64_t vram;</div><div class='del'>-	/* current shared VRAM usage, includes visible VRAM */</div><div class='del'>-	uint64_t vram_shared;</div><div class='del'>-	/* current visible VRAM usage */</div><div class='del'>-	uint64_t visible_vram;</div><div class='del'>-	/* current GTT usage */</div><div class='del'>-	uint64_t gtt;</div><div class='del'>-	/* current shared GTT usage */</div><div class='del'>-	uint64_t gtt_shared;</div><div class='del'>-	/* current system memory usage */</div><div class='del'>-	uint64_t cpu;</div><div class='del'>-	/* current shared system memory usage */</div><div class='del'>-	uint64_t cpu_shared;</div><div class='del'>-	/* sum of evicted buffers, includes visible VRAM */</div><div class='del'>-	uint64_t evicted_vram;</div><div class='del'>-	/* sum of evicted buffers due to CPU access */</div><div class='del'>-	uint64_t evicted_visible_vram;</div><div class='del'>-	/* how much userspace asked for, includes vis.VRAM */</div><div class='del'>-	uint64_t requested_vram;</div><div class='del'>-	/* how much userspace asked for */</div><div class='del'>-	uint64_t requested_visible_vram;</div><div class='del'>-	/* how much userspace asked for */</div><div class='del'>-	uint64_t requested_gtt;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)</div><div class='ctx'> {</div><div class='ctx'> 	return container_of(tbo, struct amdgpu_bo, tbo);</div><div class='hunk'>@@ -190,6 +168,8 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)</div><div class='ctx'> 		return AMDGPU_GEM_DOMAIN_OA;</div><div class='ctx'> 	case AMDGPU_PL_DOORBELL:</div><div class='ctx'> 		return AMDGPU_GEM_DOMAIN_DOORBELL;</div><div class='add'>+	case AMDGPU_PL_MMIO_REMAP:</div><div class='add'>+		return AMDGPU_GEM_DOMAIN_MMIO_REMAP;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -251,28 +231,6 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM</div><div class='del'>- */</div><div class='del'>-static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='del'>-	struct amdgpu_res_cursor cursor;</div><div class='del'>-</div><div class='del'>-	if (!bo-&gt;tbo.resource || bo-&gt;tbo.resource-&gt;mem_type != TTM_PL_VRAM)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	amdgpu_res_first(bo-&gt;tbo.resource, 0, amdgpu_bo_size(bo), &amp;cursor);</div><div class='del'>-	while (cursor.remaining) {</div><div class='del'>-		if (cursor.start &lt; adev-&gt;gmc.visible_vram_size)</div><div class='del'>-			return true;</div><div class='del'>-</div><div class='del'>-		amdgpu_res_next(&amp;cursor, cursor.size);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced</div><div class='ctx'>  */</div><div class='ctx'> static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)</div><div class='hunk'>@@ -291,22 +249,6 @@ static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)</div><div class='ctx'> 	return bo-&gt;flags &amp; AMDGPU_GEM_CREATE_ENCRYPTED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_bo_shadowed - check if the BO is shadowed</div><div class='del'>- *</div><div class='del'>- * @bo: BO to be tested.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- * NULL if not shadowed or else return a BO pointer.</div><div class='del'>- */</div><div class='del'>-static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo)</div><div class='del'>-{</div><div class='del'>-	if (bo-&gt;tbo.type == ttm_bo_type_kernel)</div><div class='del'>-		return to_amdgpu_bo_vm(bo)-&gt;shadow;</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);</div><div class='ctx'> void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);</div><div class='ctx'> </div><div class='hunk'>@@ -321,6 +263,10 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,</div><div class='ctx'> 			    unsigned long size, int align,</div><div class='ctx'> 			    u32 domain, struct amdgpu_bo **bo_ptr,</div><div class='ctx'> 			    u64 *gpu_addr, void **cpu_addr);</div><div class='add'>+int amdgpu_bo_create_isp_user(struct amdgpu_device *adev,</div><div class='add'>+			   struct dma_buf *dbuf, u32 domain,</div><div class='add'>+			   struct amdgpu_bo **bo,</div><div class='add'>+			   u64 *gpu_addr);</div><div class='ctx'> int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,</div><div class='ctx'> 			       uint64_t offset, uint64_t size,</div><div class='ctx'> 			       struct amdgpu_bo **bo_ptr, void **cpu_addr);</div><div class='hunk'>@@ -332,14 +278,13 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev,</div><div class='ctx'> 			struct amdgpu_bo_vm **ubo_ptr);</div><div class='ctx'> void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,</div><div class='ctx'> 			   void **cpu_addr);</div><div class='add'>+void amdgpu_bo_free_isp_user(struct amdgpu_bo *bo);</div><div class='ctx'> int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);</div><div class='ctx'> void *amdgpu_bo_kptr(struct amdgpu_bo *bo);</div><div class='ctx'> void amdgpu_bo_kunmap(struct amdgpu_bo *bo);</div><div class='ctx'> struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);</div><div class='ctx'> void amdgpu_bo_unref(struct amdgpu_bo **bo);</div><div class='ctx'> int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);</div><div class='del'>-int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,</div><div class='del'>-			     u64 min_offset, u64 max_offset);</div><div class='ctx'> void amdgpu_bo_unpin(struct amdgpu_bo *bo);</div><div class='ctx'> int amdgpu_bo_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_bo_fini(struct amdgpu_device *adev);</div><div class='hunk'>@@ -350,7 +295,9 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,</div><div class='ctx'> int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,</div><div class='ctx'> 			   size_t buffer_size, uint32_t *metadata_size,</div><div class='ctx'> 			   uint64_t *flags);</div><div class='del'>-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);</div><div class='add'>+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,</div><div class='add'>+			   bool evict,</div><div class='add'>+			   struct ttm_resource *new_mem);</div><div class='ctx'> void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);</div><div class='ctx'> vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);</div><div class='ctx'> void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,</div><div class='hunk'>@@ -360,12 +307,9 @@ int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,</div><div class='ctx'> 			     bool intr);</div><div class='ctx'> int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);</div><div class='ctx'> u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);</div><div class='add'>+u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo);</div><div class='ctx'> u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);</div><div class='del'>-void amdgpu_bo_get_memory(struct amdgpu_bo *bo,</div><div class='del'>-			  struct amdgpu_mem_stats *stats);</div><div class='del'>-void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);</div><div class='del'>-int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,</div><div class='del'>-			     struct dma_fence **fence);</div><div class='add'>+uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo);</div><div class='ctx'> uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,</div><div class='ctx'> 					    uint32_t domain);</div><div class='ctx'> </div><div class='hunk'>@@ -400,8 +344,7 @@ int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,</div><div class='ctx'> 		     struct drm_suballoc **sa_bo,</div><div class='ctx'> 		     unsigned int size);</div><div class='del'>-void amdgpu_sa_bo_free(struct amdgpu_device *adev,</div><div class='del'>-		       struct drm_suballoc **sa_bo,</div><div class='add'>+void amdgpu_sa_bo_free(struct drm_suballoc **sa_bo,</div><div class='ctx'> 		       struct dma_fence *fence);</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c<br/>index 0bb2466d539a..675aa138ea11 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c</a></div><div class='hunk'>@@ -94,7 +94,7 @@ static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int n</div><div class='ctx'> 		ref_div_max = min(128 / post_div, ref_div_max);</div><div class='ctx'> </div><div class='ctx'> 	/* get matching reference and feedback divider */</div><div class='del'>-	*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);</div><div class='add'>+	*ref_div = clamp(DIV_ROUND_CLOSEST(den, post_div), 1u, ref_div_max);</div><div class='ctx'> 	*fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);</div><div class='ctx'> </div><div class='ctx'> 	/* limit fb divider to its maximum */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c<br/>index e8adfd0a570a..34b5e22b44e5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c</a></div><div class='hunk'>@@ -137,7 +137,8 @@ void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	device_remove_file(adev-&gt;dev, &amp;dev_attr_mem_info_preempt_used);</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_mem_info_preempt_used);</div><div class='ctx'> </div><div class='ctx'> 	ttm_resource_manager_cleanup(man);</div><div class='ctx'> 	ttm_set_driver_manager(&amp;adev-&gt;mman.bdev, AMDGPU_PL_PREEMPT, NULL);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br/>index 94b310fdb719..0b10497d487c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c</a></div><div class='hunk'>@@ -44,7 +44,7 @@</div><div class='ctx'> #include "amdgpu_securedisplay.h"</div><div class='ctx'> #include "amdgpu_atomfirmware.h"</div><div class='ctx'> </div><div class='del'>-#define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)</div><div class='add'>+#define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*16)</div><div class='ctx'> </div><div class='ctx'> static int psp_load_smu_fw(struct psp_context *psp);</div><div class='ctx'> static int psp_rap_terminate(struct psp_context *psp);</div><div class='hunk'>@@ -145,6 +145,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp)</div><div class='ctx'> 		adev-&gt;virt.autoload_ucode_id = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		ret = psp_init_cap_microcode(psp, ucode_prefix);</div><div class='ctx'> 		ret &amp;= psp_init_ta_microcode(psp, ucode_prefix);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -152,15 +153,18 @@ static int psp_init_sriov_microcode(struct psp_context *psp)</div><div class='ctx'> 		adev-&gt;virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;</div><div class='ctx'> 		ret = psp_init_cap_microcode(psp, ucode_prefix);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+		ret = psp_init_ta_microcode(psp, ucode_prefix);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_early_init(void *handle)</div><div class='add'>+static int psp_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='ctx'> </div><div class='ctx'> 	psp-&gt;autoload_supported = true;</div><div class='hunk'>@@ -192,6 +196,7 @@ static int psp_early_init(void *handle)</div><div class='ctx'> 	case IP_VERSION(11, 0, 9):</div><div class='ctx'> 	case IP_VERSION(11, 0, 11):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='ctx'> 	case IP_VERSION(11, 0, 12):</div><div class='ctx'> 	case IP_VERSION(11, 0, 13):</div><div class='ctx'> 		psp_v11_0_set_psp_funcs(psp);</div><div class='hunk'>@@ -207,9 +212,15 @@ static int psp_early_init(void *handle)</div><div class='ctx'> 		psp-&gt;boot_time_tmr = false;</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		psp_v13_0_set_psp_funcs(psp);</div><div class='ctx'> 		psp-&gt;autoload_supported = false;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+		psp_v13_0_set_psp_funcs(psp);</div><div class='add'>+		psp-&gt;autoload_supported = false;</div><div class='add'>+		adev-&gt;psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);</div><div class='add'>+		break;</div><div class='ctx'> 	case IP_VERSION(13, 0, 1):</div><div class='ctx'> 	case IP_VERSION(13, 0, 3):</div><div class='ctx'> 	case IP_VERSION(13, 0, 5):</div><div class='hunk'>@@ -217,6 +228,7 @@ static int psp_early_init(void *handle)</div><div class='ctx'> 	case IP_VERSION(13, 0, 11):</div><div class='ctx'> 	case IP_VERSION(14, 0, 0):</div><div class='ctx'> 	case IP_VERSION(14, 0, 1):</div><div class='add'>+	case IP_VERSION(14, 0, 4):</div><div class='ctx'> 		psp_v13_0_set_psp_funcs(psp);</div><div class='ctx'> 		psp-&gt;boot_time_tmr = false;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -240,8 +252,13 @@ static int psp_early_init(void *handle)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(14, 0, 2):</div><div class='ctx'> 	case IP_VERSION(14, 0, 3):</div><div class='add'>+		adev-&gt;psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);</div><div class='ctx'> 		psp_v14_0_set_psp_funcs(psp);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(14, 0, 5):</div><div class='add'>+		psp_v14_0_set_psp_funcs(psp);</div><div class='add'>+		psp-&gt;boot_time_tmr = false;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -355,7 +372,9 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6))</div><div class='add'>+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	db_header_pos = adev-&gt;gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;</div><div class='hunk'>@@ -417,9 +436,9 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_sw_init(void *handle)</div><div class='add'>+static int psp_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	struct psp_runtime_boot_cfg_entry boot_cfg_entry;</div><div class='hunk'>@@ -429,7 +448,7 @@ static int psp_sw_init(void *handle)</div><div class='ctx'> 	psp-&gt;cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);</div><div class='ctx'> 	if (!psp-&gt;cmd) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to allocate memory to command buffer!\n");</div><div class='del'>-		ret = -ENOMEM;</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;psp.xgmi_context.supports_extended_data =</div><div class='hunk'>@@ -523,11 +542,10 @@ failed1:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_sw_fini(void *handle)</div><div class='add'>+static int psp_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='del'>-	struct psp_gfx_cmd_resp *cmd = psp-&gt;cmd;</div><div class='ctx'> </div><div class='ctx'> 	psp_memory_training_fini(psp);</div><div class='ctx'> </div><div class='hunk'>@@ -537,8 +555,8 @@ static int psp_sw_fini(void *handle)</div><div class='ctx'> 	amdgpu_ucode_release(&amp;psp-&gt;cap_fw);</div><div class='ctx'> 	amdgpu_ucode_release(&amp;psp-&gt;toc_fw);</div><div class='ctx'> </div><div class='del'>-	kfree(cmd);</div><div class='del'>-	cmd = NULL;</div><div class='add'>+	kfree(psp-&gt;cmd);</div><div class='add'>+	psp-&gt;cmd = NULL;</div><div class='ctx'> </div><div class='ctx'> 	psp_free_shared_bufs(psp);</div><div class='ctx'> </div><div class='hunk'>@@ -557,9 +575,11 @@ static int psp_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int psp_wait_for(struct psp_context *psp, uint32_t reg_index,</div><div class='del'>-		 uint32_t reg_val, uint32_t mask, bool check_changed)</div><div class='add'>+int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,</div><div class='add'>+		 uint32_t mask, uint32_t flags)</div><div class='ctx'> {</div><div class='add'>+	bool check_changed = flags &amp; PSP_WAITREG_CHANGED;</div><div class='add'>+	bool verbose = !(flags &amp; PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> 	uint32_t val;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='hunk'>@@ -579,6 +599,11 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (verbose)</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",</div><div class='add'>+			reg_index, mask, val, reg_val);</div><div class='add'>+</div><div class='ctx'> 	return -ETIME;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -635,11 +660,35 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)</div><div class='ctx'> 		return "AUTOLOAD_RLC";</div><div class='ctx'> 	case GFX_CMD_ID_BOOT_CFG:</div><div class='ctx'> 		return "BOOT_CFG";</div><div class='add'>+	case GFX_CMD_ID_CONFIG_SQ_PERFMON:</div><div class='add'>+		return "CONFIG_SQ_PERFMON";</div><div class='add'>+	case GFX_CMD_ID_FB_FW_RESERV_ADDR:</div><div class='add'>+		return "FB_FW_RESERV_ADDR";</div><div class='add'>+	case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR:</div><div class='add'>+		return "FB_FW_RESERV_EXT_ADDR";</div><div class='add'>+	case GFX_CMD_ID_SRIOV_SPATIAL_PART:</div><div class='add'>+		return "SPATIAL_PARTITION";</div><div class='add'>+	case GFX_CMD_ID_FB_NPS_MODE:</div><div class='add'>+		return "NPS_MODE_CHANGE";</div><div class='ctx'> 	default:</div><div class='ctx'> 		return "UNKNOWN CMD";</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool psp_err_warn(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	struct psp_gfx_cmd_resp *cmd = psp-&gt;cmd_buf_mem;</div><div class='add'>+</div><div class='add'>+	/* This response indicates reg list is already loaded */</div><div class='add'>+	if (amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &amp;&amp;</div><div class='add'>+	    cmd-&gt;cmd_id == GFX_CMD_ID_LOAD_IP_FW &amp;&amp;</div><div class='add'>+	    cmd-&gt;cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST &amp;&amp;</div><div class='add'>+	    cmd-&gt;resp.status == TEE_ERROR_CANCEL)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int</div><div class='ctx'> psp_cmd_submit_buf(struct psp_context *psp,</div><div class='ctx'> 		   struct amdgpu_firmware_info *ucode,</div><div class='hunk'>@@ -699,10 +748,13 @@ psp_cmd_submit_buf(struct psp_context *psp,</div><div class='ctx'> 			dev_warn(psp-&gt;adev-&gt;dev,</div><div class='ctx'> 				 "failed to load ucode %s(0x%X) ",</div><div class='ctx'> 				 amdgpu_ucode_name(ucode-&gt;ucode_id), ucode-&gt;ucode_id);</div><div class='del'>-		dev_warn(psp-&gt;adev-&gt;dev,</div><div class='del'>-			 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n",</div><div class='del'>-			 psp_gfx_cmd_name(psp-&gt;cmd_buf_mem-&gt;cmd_id), psp-&gt;cmd_buf_mem-&gt;cmd_id,</div><div class='del'>-			 psp-&gt;cmd_buf_mem-&gt;resp.status);</div><div class='add'>+		if (psp_err_warn(psp))</div><div class='add'>+			dev_warn(</div><div class='add'>+				psp-&gt;adev-&gt;dev,</div><div class='add'>+				"psp gfx command %s(0x%X) failed and response status is (0x%X)\n",</div><div class='add'>+				psp_gfx_cmd_name(psp-&gt;cmd_buf_mem-&gt;cmd_id),</div><div class='add'>+				psp-&gt;cmd_buf_mem-&gt;cmd_id,</div><div class='add'>+				psp-&gt;cmd_buf_mem-&gt;resp.status);</div><div class='ctx'> 		/* If any firmware (including CAP) load fails under SRIOV, it should</div><div class='ctx'> 		 * return failure to stop the VF from initializing.</div><div class='ctx'> 		 * Also return failure in case of timeout</div><div class='hunk'>@@ -829,12 +881,12 @@ static int psp_tmr_init(struct psp_context *psp)</div><div class='ctx'> 		pptr = amdgpu_sriov_vf(psp-&gt;adev) ? &amp;tmr_buf : NULL;</div><div class='ctx'> 		ret = amdgpu_bo_create_kernel(psp-&gt;adev, tmr_size,</div><div class='ctx'> 					      PSP_TMR_ALIGNMENT,</div><div class='del'>-					      AMDGPU_HAS_VRAM(psp-&gt;adev) ?</div><div class='del'>-					      AMDGPU_GEM_DOMAIN_VRAM :</div><div class='del'>-					      AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+					      AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM,</div><div class='ctx'> 					      &amp;psp-&gt;tmr_bo, &amp;psp-&gt;tmr_mc_addr,</div><div class='ctx'> 					      pptr);</div><div class='ctx'> 	}</div><div class='add'>+	if (amdgpu_virt_xgmi_migrate_enabled(psp-&gt;adev) &amp;&amp; psp-&gt;tmr_bo)</div><div class='add'>+		psp-&gt;tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp-&gt;tmr_bo);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -847,6 +899,8 @@ static bool psp_skip_tmr(struct psp_context *psp)</div><div class='ctx'> 	case IP_VERSION(13, 0, 2):</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -946,6 +1000,106 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int psp_get_fw_reservation_info(struct psp_context *psp,</div><div class='add'>+						   uint32_t cmd_id,</div><div class='add'>+						   uint64_t *addr,</div><div class='add'>+						   uint32_t *size)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	uint32_t status;</div><div class='add'>+	struct psp_gfx_cmd_resp *cmd;</div><div class='add'>+</div><div class='add'>+	cmd = acquire_psp_cmd_buf(psp);</div><div class='add'>+</div><div class='add'>+	cmd-&gt;cmd_id = cmd_id;</div><div class='add'>+</div><div class='add'>+	ret = psp_cmd_submit_buf(psp, NULL, cmd,</div><div class='add'>+				 psp-&gt;fence_buf_mc_addr);</div><div class='add'>+	if (ret) {</div><div class='add'>+		release_psp_cmd_buf(psp);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	status = cmd-&gt;resp.status;</div><div class='add'>+	if (status == PSP_ERR_UNKNOWN_COMMAND) {</div><div class='add'>+		release_psp_cmd_buf(psp);</div><div class='add'>+		*addr = 0;</div><div class='add'>+		*size = 0;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*addr = (uint64_t)cmd-&gt;resp.uresp.fw_reserve_info.reserve_base_address_hi &lt;&lt; 32 |</div><div class='add'>+		cmd-&gt;resp.uresp.fw_reserve_info.reserve_base_address_lo;</div><div class='add'>+	*size = cmd-&gt;resp.uresp.fw_reserve_info.reserve_size;</div><div class='add'>+</div><div class='add'>+	release_psp_cmd_buf(psp);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int psp_update_fw_reservation(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	uint64_t reserv_addr, reserv_addr_ext;</div><div class='add'>+	uint32_t reserv_size, reserv_size_ext, mp0_ip_ver;</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+</div><div class='add'>+	mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(psp-&gt;adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (mp0_ip_ver) {</div><div class='add'>+	case IP_VERSION(14, 0, 2):</div><div class='add'>+		if (adev-&gt;psp.sos.fw_version &lt; 0x3b0e0d)</div><div class='add'>+			return 0;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case IP_VERSION(14, 0, 3):</div><div class='add'>+		if (adev-&gt;psp.sos.fw_version &lt; 0x3a0e14)</div><div class='add'>+			return 0;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &amp;reserv_addr, &amp;reserv_size);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &amp;reserv_addr_ext, &amp;reserv_size_ext);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (reserv_addr != adev-&gt;gmc.real_vram_size - reserv_size) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "reserve fw region is not valid!\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory, NULL, NULL);</div><div class='add'>+</div><div class='add'>+	reserv_size = roundup(reserv_size, SZ_1M);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_create_kernel_at(adev, reserv_addr, reserv_size, &amp;adev-&gt;mman.fw_reserved_memory, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "reserve fw region failed(%d)!\n", ret);</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory, NULL, NULL);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reserv_size_ext = roundup(reserv_size_ext, SZ_1M);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_create_kernel_at(adev, reserv_addr_ext, reserv_size_ext,</div><div class='add'>+					 &amp;adev-&gt;mman.fw_reserved_memory_extend, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "reserve extend fw region failed(%d)!\n", ret);</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory_extend, NULL, NULL);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)</div><div class='ctx'> {</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='hunk'>@@ -1021,6 +1175,31 @@ static int psp_rl_load(struct amdgpu_device *adev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int psp_memory_partition(struct psp_context *psp, int mode)</div><div class='add'>+{</div><div class='add'>+	struct psp_gfx_cmd_resp *cmd;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(psp-&gt;adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	cmd = acquire_psp_cmd_buf(psp);</div><div class='add'>+</div><div class='add'>+	cmd-&gt;cmd_id = GFX_CMD_ID_FB_NPS_MODE;</div><div class='add'>+	cmd-&gt;cmd.cmd_memory_part.mode = mode;</div><div class='add'>+</div><div class='add'>+	dev_info(psp-&gt;adev-&gt;dev,</div><div class='add'>+		 "Requesting %d memory partition change through PSP", mode);</div><div class='add'>+	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp-&gt;fence_buf_mc_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(psp-&gt;adev-&gt;dev,</div><div class='add'>+			"PSP request failed to change to NPS%d mode\n", mode);</div><div class='add'>+</div><div class='add'>+	release_psp_cmd_buf(psp);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int psp_spatial_partition(struct psp_context *psp, int mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct psp_gfx_cmd_resp *cmd;</div><div class='hunk'>@@ -1053,6 +1232,11 @@ static int psp_asd_initialize(struct psp_context *psp)</div><div class='ctx'> 	if (amdgpu_sriov_vf(psp-&gt;adev) || !psp-&gt;asd_context.bin_desc.size_bytes)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	/* bypass asd if display hardware is not available */</div><div class='add'>+	if (!amdgpu_device_has_display_hardware(psp-&gt;adev) &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0) &gt;= IP_VERSION(13, 0, 10))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	psp-&gt;asd_context.mem_context.shared_mc_addr  = 0;</div><div class='ctx'> 	psp-&gt;asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;</div><div class='ctx'> 	psp-&gt;asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;</div><div class='hunk'>@@ -1202,6 +1386,11 @@ int psp_ta_load(struct psp_context *psp, struct ta_context *context)</div><div class='ctx'> 	psp_copy_fw(psp, context-&gt;bin_desc.start_addr,</div><div class='ctx'> 		    context-&gt;bin_desc.size_bytes);</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_virt_xgmi_migrate_enabled(psp-&gt;adev) &amp;&amp;</div><div class='add'>+		context-&gt;mem_context.shared_bo)</div><div class='add'>+		context-&gt;mem_context.shared_mc_addr =</div><div class='add'>+			amdgpu_bo_fb_aper_addr(context-&gt;mem_context.shared_bo);</div><div class='add'>+</div><div class='ctx'> 	psp_prep_ta_load_cmd_buf(cmd, psp-&gt;fw_pri_mc_addr, context);</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_cmd_submit_buf(psp, NULL, cmd,</div><div class='hunk'>@@ -1350,9 +1539,13 @@ static void psp_xgmi_reflect_topology_info(struct psp_context *psp,</div><div class='ctx'> 	uint64_t src_node_id = psp-&gt;adev-&gt;gmc.xgmi.node_id;</div><div class='ctx'> 	uint64_t dst_node_id = node_info.node_id;</div><div class='ctx'> 	uint8_t dst_num_hops = node_info.num_hops;</div><div class='add'>+	uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled;</div><div class='ctx'> 	uint8_t dst_num_links = node_info.num_links;</div><div class='ctx'> </div><div class='ctx'> 	hive = amdgpu_get_xgmi_hive(psp-&gt;adev);</div><div class='add'>+	if (WARN_ON(!hive))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry(mirror_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='ctx'> 		struct psp_xgmi_topology_info *mirror_top_info;</div><div class='ctx'> 		int j;</div><div class='hunk'>@@ -1366,13 +1559,20 @@ static void psp_xgmi_reflect_topology_info(struct psp_context *psp,</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			mirror_top_info-&gt;nodes[j].num_hops = dst_num_hops;</div><div class='del'>-			/*</div><div class='del'>-			 * prevent 0 num_links value re-reflection since reflection</div><div class='add'>+			mirror_top_info-&gt;nodes[j].is_sharing_enabled = dst_is_sharing_enabled;</div><div class='add'>+			/* prevent 0 num_links value re-reflection since reflection</div><div class='ctx'> 			 * criteria is based on num_hops (direct or indirect).</div><div class='del'>-			 *</div><div class='ctx'> 			 */</div><div class='del'>-			if (dst_num_links)</div><div class='add'>+			if (dst_num_links) {</div><div class='ctx'> 				mirror_top_info-&gt;nodes[j].num_links = dst_num_links;</div><div class='add'>+				/* swap src and dst due to frame of reference */</div><div class='add'>+				for (int k = 0; k &lt; dst_num_links; k++) {</div><div class='add'>+					mirror_top_info-&gt;nodes[j].port_num[k].src_xgmi_port_num =</div><div class='add'>+						node_info.port_num[k].dst_xgmi_port_num;</div><div class='add'>+					mirror_top_info-&gt;nodes[j].port_num[k].dst_xgmi_port_num =</div><div class='add'>+						node_info.port_num[k].src_xgmi_port_num;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1445,9 +1645,12 @@ int psp_xgmi_get_topology_info(struct psp_context *psp,</div><div class='ctx'> 			(psp-&gt;xgmi_context.supports_extended_data &amp;&amp;</div><div class='ctx'> 			 get_extended_data) ||</div><div class='ctx'> 			amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0) ==</div><div class='del'>-				IP_VERSION(13, 0, 6);</div><div class='del'>-		bool ta_port_num_support = amdgpu_sriov_vf(psp-&gt;adev) ? 0 :</div><div class='del'>-				psp-&gt;xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG;</div><div class='add'>+				IP_VERSION(13, 0, 6) ||</div><div class='add'>+			amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0) ==</div><div class='add'>+				IP_VERSION(13, 0, 14) ||</div><div class='add'>+			amdgpu_sriov_vf(psp-&gt;adev);</div><div class='add'>+		bool ta_port_num_support = psp-&gt;xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG ||</div><div class='add'>+			amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 		/* popluate the shared output buffer rather than the cmd input buffer</div><div class='ctx'> 		 * with node_ids as the input for GET_PEER_LINKS command execution.</div><div class='hunk'>@@ -1559,6 +1762,66 @@ static void psp_ras_ta_check_status(struct psp_context *psp)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int psp_ras_send_cmd(struct psp_context *psp,</div><div class='add'>+		enum ras_command cmd_id, void *in, void *out)</div><div class='add'>+{</div><div class='add'>+	struct ta_ras_shared_memory *ras_cmd;</div><div class='add'>+	uint32_t cmd = cmd_id;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!in)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;psp-&gt;ras_context.mutex);</div><div class='add'>+	ras_cmd = (struct ta_ras_shared_memory *)psp-&gt;ras_context.context.mem_context.shared_buf;</div><div class='add'>+	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));</div><div class='add'>+</div><div class='add'>+	switch (cmd) {</div><div class='add'>+	case TA_RAS_COMMAND__ENABLE_FEATURES:</div><div class='add'>+	case TA_RAS_COMMAND__DISABLE_FEATURES:</div><div class='add'>+		memcpy(&amp;ras_cmd-&gt;ras_in_message,</div><div class='add'>+			in, sizeof(ras_cmd-&gt;ras_in_message));</div><div class='add'>+		break;</div><div class='add'>+	case TA_RAS_COMMAND__TRIGGER_ERROR:</div><div class='add'>+		memcpy(&amp;ras_cmd-&gt;ras_in_message.trigger_error,</div><div class='add'>+			in, sizeof(ras_cmd-&gt;ras_in_message.trigger_error));</div><div class='add'>+		break;</div><div class='add'>+	case TA_RAS_COMMAND__QUERY_ADDRESS:</div><div class='add'>+		memcpy(&amp;ras_cmd-&gt;ras_in_message.address,</div><div class='add'>+			in, sizeof(ras_cmd-&gt;ras_in_message.address));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(psp-&gt;adev-&gt;dev, "Invalid ras cmd id: %u\n", cmd);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ras_cmd-&gt;cmd_id = cmd;</div><div class='add'>+	ret = psp_ras_invoke(psp, ras_cmd-&gt;cmd_id);</div><div class='add'>+</div><div class='add'>+	switch (cmd) {</div><div class='add'>+	case TA_RAS_COMMAND__TRIGGER_ERROR:</div><div class='add'>+		if (!ret &amp;&amp; out)</div><div class='add'>+			memcpy(out, &amp;ras_cmd-&gt;ras_status, sizeof(ras_cmd-&gt;ras_status));</div><div class='add'>+		break;</div><div class='add'>+	case TA_RAS_COMMAND__QUERY_ADDRESS:</div><div class='add'>+		if (ret || ras_cmd-&gt;ras_status || psp-&gt;cmd_buf_mem-&gt;resp.status)</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		else if (out)</div><div class='add'>+			memcpy(out,</div><div class='add'>+				&amp;ras_cmd-&gt;ras_out_message.address,</div><div class='add'>+				sizeof(ras_cmd-&gt;ras_out_message.address));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	mutex_unlock(&amp;psp-&gt;ras_context.mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct ta_ras_shared_memory *ras_cmd;</div><div class='hunk'>@@ -1600,23 +1863,15 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)</div><div class='ctx'> int psp_ras_enable_features(struct psp_context *psp,</div><div class='ctx'> 		union ta_ras_cmd_input *info, bool enable)</div><div class='ctx'> {</div><div class='del'>-	struct ta_ras_shared_memory *ras_cmd;</div><div class='add'>+	enum ras_command cmd_id;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!psp-&gt;ras_context.context.initialized)</div><div class='add'>+	if (!psp-&gt;ras_context.context.initialized || !info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ras_cmd = (struct ta_ras_shared_memory *)psp-&gt;ras_context.context.mem_context.shared_buf;</div><div class='del'>-	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));</div><div class='del'>-</div><div class='del'>-	if (enable)</div><div class='del'>-		ras_cmd-&gt;cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;</div><div class='del'>-	else</div><div class='del'>-		ras_cmd-&gt;cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;</div><div class='del'>-</div><div class='del'>-	ras_cmd-&gt;ras_in_message = *info;</div><div class='del'>-</div><div class='del'>-	ret = psp_ras_invoke(psp, ras_cmd-&gt;cmd_id);</div><div class='add'>+	cmd_id = enable ?</div><div class='add'>+		TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES;</div><div class='add'>+	ret = psp_ras_send_cmd(psp, cmd_id, info, NULL);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1640,6 +1895,8 @@ int psp_ras_terminate(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	psp-&gt;ras_context.context.initialized = false;</div><div class='ctx'> </div><div class='add'>+	mutex_destroy(&amp;psp-&gt;ras_context.mutex);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1670,34 +1927,47 @@ int psp_ras_initialize(struct psp_context *psp)</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "PSP get boot config failed\n");</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_ras_is_supported(psp-&gt;adev, AMDGPU_RAS_BLOCK__UMC)) {</div><div class='del'>-			if (!boot_cfg) {</div><div class='del'>-				dev_info(adev-&gt;dev, "GECC is disabled\n");</div><div class='del'>-			} else {</div><div class='del'>-				/* disable GECC in next boot cycle if ras is</div><div class='del'>-				 * disabled by module parameter amdgpu_ras_enable</div><div class='del'>-				 * and/or amdgpu_ras_mask, or boot_config_get call</div><div class='del'>-				 * is failed</div><div class='del'>-				 */</div><div class='del'>-				ret = psp_boot_config_set(adev, 0);</div><div class='del'>-				if (ret)</div><div class='del'>-					dev_warn(adev-&gt;dev, "PSP set boot config failed\n");</div><div class='del'>-				else</div><div class='del'>-					dev_warn(adev-&gt;dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");</div><div class='del'>-			}</div><div class='add'>+		if (boot_cfg == 1 &amp;&amp; !adev-&gt;ras_default_ecc_enabled &amp;&amp;</div><div class='add'>+		    amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "GECC is currently enabled, which may affect performance\n");</div><div class='add'>+			dev_warn(adev-&gt;dev,</div><div class='add'>+				"To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n");</div><div class='ctx'> 		} else {</div><div class='del'>-			if (boot_cfg == 1) {</div><div class='del'>-				dev_info(adev-&gt;dev, "GECC is enabled\n");</div><div class='add'>+			if ((adev-&gt;ras_default_ecc_enabled || amdgpu_ras_enable == 1) &amp;&amp;</div><div class='add'>+				amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {</div><div class='add'>+				if (boot_cfg == 1) {</div><div class='add'>+					dev_info(adev-&gt;dev, "GECC is enabled\n");</div><div class='add'>+				} else {</div><div class='add'>+					/* enable GECC in next boot cycle if it is disabled</div><div class='add'>+					 * in boot config, or force enable GECC if failed to</div><div class='add'>+					 * get boot configuration</div><div class='add'>+					 */</div><div class='add'>+					ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);</div><div class='add'>+					if (ret)</div><div class='add'>+						dev_warn(adev-&gt;dev, "PSP set boot config failed\n");</div><div class='add'>+					else</div><div class='add'>+						dev_warn(adev-&gt;dev, "GECC will be enabled in next boot cycle\n");</div><div class='add'>+				}</div><div class='ctx'> 			} else {</div><div class='del'>-				/* enable GECC in next boot cycle if it is disabled</div><div class='del'>-				 * in boot config, or force enable GECC if failed to</div><div class='del'>-				 * get boot configuration</div><div class='del'>-				 */</div><div class='del'>-				ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);</div><div class='del'>-				if (ret)</div><div class='del'>-					dev_warn(adev-&gt;dev, "PSP set boot config failed\n");</div><div class='del'>-				else</div><div class='del'>-					dev_warn(adev-&gt;dev, "GECC will be enabled in next boot cycle\n");</div><div class='add'>+				if (!boot_cfg) {</div><div class='add'>+					if (!adev-&gt;ras_default_ecc_enabled &amp;&amp;</div><div class='add'>+					    amdgpu_ras_enable != 1 &amp;&amp;</div><div class='add'>+					    amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='add'>+						dev_warn(adev-&gt;dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n");</div><div class='add'>+					else</div><div class='add'>+						dev_info(adev-&gt;dev, "GECC is disabled\n");</div><div class='add'>+				} else {</div><div class='add'>+					/* disable GECC in next boot cycle if ras is</div><div class='add'>+					 * disabled by module parameter amdgpu_ras_enable</div><div class='add'>+					 * and/or amdgpu_ras_mask, or boot_config_get call</div><div class='add'>+					 * is failed</div><div class='add'>+					 */</div><div class='add'>+					ret = psp_boot_config_set(adev, 0);</div><div class='add'>+					if (ret)</div><div class='add'>+						dev_warn(adev-&gt;dev, "PSP set boot config failed\n");</div><div class='add'>+					else</div><div class='add'>+						dev_warn(adev-&gt;dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1721,12 +1991,17 @@ int psp_ras_initialize(struct psp_context *psp)</div><div class='ctx'> 	ras_cmd-&gt;ras_in_message.init_flags.xcc_mask =</div><div class='ctx'> 		adev-&gt;gfx.xcc_mask;</div><div class='ctx'> 	ras_cmd-&gt;ras_in_message.init_flags.channel_dis_num = hweight32(adev-&gt;gmc.m_half_use) * 2;</div><div class='add'>+	if (adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode)</div><div class='add'>+		ras_cmd-&gt;ras_in_message.init_flags.nps_mode =</div><div class='add'>+			adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='add'>+	ras_cmd-&gt;ras_in_message.init_flags.active_umc_mask = adev-&gt;umc.active_mask;</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_ta_load(psp, &amp;psp-&gt;ras_context.context);</div><div class='ctx'> </div><div class='del'>-	if (!ret &amp;&amp; !ras_cmd-&gt;ras_status)</div><div class='add'>+	if (!ret &amp;&amp; !ras_cmd-&gt;ras_status) {</div><div class='ctx'> 		psp-&gt;ras_context.context.initialized = true;</div><div class='del'>-	else {</div><div class='add'>+		mutex_init(&amp;psp-&gt;ras_context.mutex);</div><div class='add'>+	} else {</div><div class='ctx'> 		if (ras_cmd-&gt;ras_status)</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "RAS Init Status: 0x%X\n", ras_cmd-&gt;ras_status);</div><div class='ctx'> </div><div class='hunk'>@@ -1740,12 +2015,12 @@ int psp_ras_initialize(struct psp_context *psp)</div><div class='ctx'> int psp_ras_trigger_error(struct psp_context *psp,</div><div class='ctx'> 			  struct ta_ras_trigger_error_input *info, uint32_t instance_mask)</div><div class='ctx'> {</div><div class='del'>-	struct ta_ras_shared_memory *ras_cmd;</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	uint32_t dev_mask;</div><div class='add'>+	uint32_t ras_status = 0;</div><div class='ctx'> </div><div class='del'>-	if (!psp-&gt;ras_context.context.initialized)</div><div class='add'>+	if (!psp-&gt;ras_context.context.initialized || !info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	switch (info-&gt;block_id) {</div><div class='hunk'>@@ -1769,13 +2044,8 @@ int psp_ras_trigger_error(struct psp_context *psp,</div><div class='ctx'> 	dev_mask &amp;= AMDGPU_RAS_INST_MASK;</div><div class='ctx'> 	info-&gt;sub_block_index |= dev_mask;</div><div class='ctx'> </div><div class='del'>-	ras_cmd = (struct ta_ras_shared_memory *)psp-&gt;ras_context.context.mem_context.shared_buf;</div><div class='del'>-	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));</div><div class='del'>-</div><div class='del'>-	ras_cmd-&gt;cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;</div><div class='del'>-	ras_cmd-&gt;ras_in_message.trigger_error = *info;</div><div class='del'>-</div><div class='del'>-	ret = psp_ras_invoke(psp, ras_cmd-&gt;cmd_id);</div><div class='add'>+	ret = psp_ras_send_cmd(psp,</div><div class='add'>+			TA_RAS_COMMAND__TRIGGER_ERROR, info, &amp;ras_status);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1785,9 +2055,9 @@ int psp_ras_trigger_error(struct psp_context *psp,</div><div class='ctx'> 	if (amdgpu_ras_intr_triggered())</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (ras_cmd-&gt;ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)</div><div class='add'>+	if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)</div><div class='ctx'> 		return -EACCES;</div><div class='del'>-	else if (ras_cmd-&gt;ras_status)</div><div class='add'>+	else if (ras_status)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1797,25 +2067,16 @@ int psp_ras_query_address(struct psp_context *psp,</div><div class='ctx'> 			  struct ta_ras_query_address_input *addr_in,</div><div class='ctx'> 			  struct ta_ras_query_address_output *addr_out)</div><div class='ctx'> {</div><div class='del'>-	struct ta_ras_shared_memory *ras_cmd;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!psp-&gt;ras_context.context.initialized)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	ras_cmd = (struct ta_ras_shared_memory *)psp-&gt;ras_context.context.mem_context.shared_buf;</div><div class='del'>-	memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));</div><div class='del'>-</div><div class='del'>-	ras_cmd-&gt;cmd_id = TA_RAS_COMMAND__QUERY_ADDRESS;</div><div class='del'>-	ras_cmd-&gt;ras_in_message.address = *addr_in;</div><div class='del'>-</div><div class='del'>-	ret = psp_ras_invoke(psp, ras_cmd-&gt;cmd_id);</div><div class='del'>-	if (ret || ras_cmd-&gt;ras_status || psp-&gt;cmd_buf_mem-&gt;resp.status)</div><div class='add'>+	if (!psp-&gt;ras_context.context.initialized ||</div><div class='add'>+		!addr_in || !addr_out)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	*addr_out = ras_cmd-&gt;ras_out_message.address;</div><div class='add'>+	ret = psp_ras_send_cmd(psp,</div><div class='add'>+			TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> // ras end</div><div class='ctx'> </div><div class='hunk'>@@ -2083,7 +2344,8 @@ static int psp_securedisplay_initialize(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	if (!psp-&gt;securedisplay_context.context.bin_desc.size_bytes ||</div><div class='ctx'> 	    !psp-&gt;securedisplay_context.context.bin_desc.start_addr) {</div><div class='del'>-		dev_info(psp-&gt;adev-&gt;dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");</div><div class='add'>+		dev_info(psp-&gt;adev-&gt;dev,</div><div class='add'>+			 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2099,11 +2361,14 @@ static int psp_securedisplay_initialize(struct psp_context *psp)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_ta_load(psp, &amp;psp-&gt;securedisplay_context.context);</div><div class='del'>-	if (!ret) {</div><div class='add'>+	if (!ret &amp;&amp; !psp-&gt;securedisplay_context.context.resp_status) {</div><div class='ctx'> 		psp-&gt;securedisplay_context.context.initialized = true;</div><div class='ctx'> 		mutex_init(&amp;psp-&gt;securedisplay_context.mutex);</div><div class='del'>-	} else</div><div class='add'>+	} else {</div><div class='add'>+		/* don't try again */</div><div class='add'>+		psp-&gt;securedisplay_context.context.bin_desc.size_bytes = 0;</div><div class='ctx'> 		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;psp-&gt;securedisplay_context.mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -2161,7 +2426,8 @@ int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &amp;&amp;</div><div class='del'>-	    ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)</div><div class='add'>+	    ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC &amp;&amp;</div><div class='add'>+	    ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_ta_invoke(psp, ta_cmd_id, &amp;psp-&gt;securedisplay_context.context);</div><div class='hunk'>@@ -2191,11 +2457,40 @@ bool amdgpu_psp_get_ras_capability(struct psp_context *psp)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev) || (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (psp-&gt;funcs &amp;&amp; psp-&gt;funcs-&gt;is_reload_needed)</div><div class='add'>+		return psp-&gt;funcs-&gt;is_reload_needed(psp);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void psp_update_gpu_addresses(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='add'>+</div><div class='add'>+	if (psp-&gt;cmd_buf_bo &amp;&amp; psp-&gt;cmd_buf_mem) {</div><div class='add'>+		psp-&gt;fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp-&gt;fw_pri_bo);</div><div class='add'>+		psp-&gt;fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp-&gt;fence_buf_bo);</div><div class='add'>+		psp-&gt;cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp-&gt;cmd_buf_bo);</div><div class='add'>+	}</div><div class='add'>+	if (adev-&gt;firmware.rbuf &amp;&amp; psp-&gt;km_ring.ring_mem)</div><div class='add'>+		psp-&gt;km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev-&gt;firmware.rbuf);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int psp_hw_start(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_virt_xgmi_migrate_enabled(adev))</div><div class='add'>+		psp_update_gpu_addresses(adev);</div><div class='add'>+</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		if ((is_psp_fw_valid(psp-&gt;kdb)) &amp;&amp;</div><div class='ctx'> 		    (psp-&gt;funcs-&gt;bootloader_load_kdb != NULL)) {</div><div class='hunk'>@@ -2260,6 +2555,24 @@ static int psp_hw_start(struct psp_context *psp)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if ((is_psp_fw_valid(psp-&gt;ipkeymgr_drv)) &amp;&amp;</div><div class='add'>+		    (psp-&gt;funcs-&gt;bootloader_load_ipkeymgr_drv != NULL)) {</div><div class='add'>+			ret = psp_bootloader_load_ipkeymgr_drv(psp);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dev_err(adev-&gt;dev, "PSP load ipkeymgr_drv failed!\n");</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((is_psp_fw_valid(psp-&gt;spdm_drv)) &amp;&amp;</div><div class='add'>+		    (psp-&gt;funcs-&gt;bootloader_load_spdm_drv != NULL)) {</div><div class='add'>+			ret = psp_bootloader_load_spdm_drv(psp);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dev_err(adev-&gt;dev, "PSP load spdm_drv failed!\n");</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if ((is_psp_fw_valid(psp-&gt;sos)) &amp;&amp;</div><div class='ctx'> 		    (psp-&gt;funcs-&gt;bootloader_load_sos != NULL)) {</div><div class='ctx'> 			ret = psp_bootloader_load_sos(psp);</div><div class='hunk'>@@ -2276,6 +2589,14 @@ static int psp_hw_start(struct psp_context *psp)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+		ret = psp_update_fw_reservation(psp);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "update fw reservation failed!\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) &amp;&amp; amdgpu_in_reset(adev))</div><div class='ctx'> 		goto skip_pin_bo;</div><div class='ctx'> </div><div class='hunk'>@@ -2450,6 +2771,7 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,</div><div class='ctx'> 		*type = GFX_FW_TYPE_DMUB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:</div><div class='add'>+	case AMDGPU_UCODE_ID_SDMA_RS64:</div><div class='ctx'> 		*type = GFX_FW_TYPE_SDMA_UCODE_TH0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:</div><div class='hunk'>@@ -2518,6 +2840,9 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,</div><div class='ctx'> 	case AMDGPU_UCODE_ID_JPEG_RAM:</div><div class='ctx'> 		*type = GFX_FW_TYPE_JPEG_RAM;</div><div class='ctx'> 		break;</div><div class='add'>+	case AMDGPU_UCODE_ID_ISP:</div><div class='add'>+		*type = GFX_FW_TYPE_ISP;</div><div class='add'>+		break;</div><div class='ctx'> 	case AMDGPU_UCODE_ID_MAXIMUM:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2617,10 +2942,12 @@ static int psp_load_p2s_table(struct psp_context *psp)</div><div class='ctx'> 	struct amdgpu_firmware_info *ucode =</div><div class='ctx'> 		&amp;adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;in_runpm &amp;&amp; (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO))</div><div class='add'>+	if (adev-&gt;in_runpm &amp;&amp; ((adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) ||</div><div class='add'>+				(adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {</div><div class='ctx'> 		uint32_t supp_vers = adev-&gt;flags &amp; AMD_IS_APU ? 0x0036013D :</div><div class='ctx'> 								0x0036003C;</div><div class='ctx'> 		if (psp-&gt;sos.fw_version &lt; supp_vers)</div><div class='hunk'>@@ -2647,7 +2974,8 @@ static int psp_load_smu_fw(struct psp_context *psp)</div><div class='ctx'> 	 * Skip SMU FW reloading in case of using BACO for runpm only,</div><div class='ctx'> 	 * as SMU is always alive.</div><div class='ctx'> 	 */</div><div class='del'>-	if (adev-&gt;in_runpm &amp;&amp; (adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO))</div><div class='add'>+	if (adev-&gt;in_runpm &amp;&amp; ((adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BACO) ||</div><div class='add'>+				(adev-&gt;pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!ucode-&gt;fw || amdgpu_sriov_vf(psp-&gt;adev))</div><div class='hunk'>@@ -2764,7 +3092,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp)</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> </div><div class='del'>-		/* Start rlc autoload after psp recieved all the gfx firmware */</div><div class='add'>+		/* Start rlc autoload after psp received all the gfx firmware */</div><div class='ctx'> 		if (psp-&gt;autoload_supported &amp;&amp; ucode-&gt;ucode_id == (amdgpu_sriov_vf(adev) ?</div><div class='ctx'> 		    adev-&gt;virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {</div><div class='ctx'> 			ret = psp_rlc_autoload_start(psp);</div><div class='hunk'>@@ -2869,16 +3197,13 @@ failed:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_hw_init(void *handle)</div><div class='add'>+static int psp_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;firmware.mutex);</div><div class='del'>-	/*</div><div class='del'>-	 * This sequence is just used on hw_init only once, no need on</div><div class='del'>-	 * resume.</div><div class='del'>-	 */</div><div class='add'>+</div><div class='ctx'> 	ret = amdgpu_ucode_init_bo(adev);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto failed;</div><div class='hunk'>@@ -2898,9 +3223,9 @@ failed:</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_hw_fini(void *handle)</div><div class='add'>+static int psp_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='ctx'> </div><div class='ctx'> 	if (psp-&gt;ta_fw) {</div><div class='hunk'>@@ -2922,10 +3247,10 @@ static int psp_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_suspend(void *handle)</div><div class='add'>+static int psp_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int ret = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1 &amp;&amp;</div><div class='hunk'>@@ -2985,10 +3310,10 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_resume(void *handle)</div><div class='add'>+static int psp_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct psp_context *psp = &amp;adev-&gt;psp;</div><div class='ctx'> </div><div class='ctx'> 	dev_info(adev-&gt;dev, "PSP is resuming...\n");</div><div class='hunk'>@@ -3003,6 +3328,10 @@ static int psp_resume(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;firmware.mutex);</div><div class='ctx'> </div><div class='add'>+	ret = amdgpu_ucode_init_bo(adev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto failed;</div><div class='add'>+</div><div class='ctx'> 	ret = psp_hw_start(psp);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto failed;</div><div class='hunk'>@@ -3154,12 +3483,11 @@ int psp_ring_cmd_submit(struct psp_context *psp,</div><div class='ctx'> int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	char fw_name[PSP_FW_NAME_LEN];</div><div class='ctx'> 	const struct psp_firmware_header_v1_0 *asd_hdr;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.asd_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.asd_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_asd.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -3178,12 +3506,11 @@ out:</div><div class='ctx'> int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	char fw_name[PSP_FW_NAME_LEN];</div><div class='ctx'> 	const struct psp_firmware_header_v1_0 *toc_hdr;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.toc_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.toc_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_toc.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -3273,6 +3600,18 @@ static int parse_sos_bin_descriptor(struct psp_context *psp,</div><div class='ctx'> 		psp-&gt;ras_drv.size_bytes         = le32_to_cpu(desc-&gt;size_bytes);</div><div class='ctx'> 		psp-&gt;ras_drv.start_addr         = ucode_start_addr;</div><div class='ctx'> 		break;</div><div class='add'>+	case PSP_FW_TYPE_PSP_IPKEYMGR_DRV:</div><div class='add'>+		psp-&gt;ipkeymgr_drv.fw_version         = le32_to_cpu(desc-&gt;fw_version);</div><div class='add'>+		psp-&gt;ipkeymgr_drv.feature_version    = le32_to_cpu(desc-&gt;fw_version);</div><div class='add'>+		psp-&gt;ipkeymgr_drv.size_bytes         = le32_to_cpu(desc-&gt;size_bytes);</div><div class='add'>+		psp-&gt;ipkeymgr_drv.start_addr         = ucode_start_addr;</div><div class='add'>+		break;</div><div class='add'>+	case PSP_FW_TYPE_PSP_SPDM_DRV:</div><div class='add'>+		psp-&gt;spdm_drv.fw_version	= le32_to_cpu(desc-&gt;fw_version);</div><div class='add'>+		psp-&gt;spdm_drv.feature_version	= le32_to_cpu(desc-&gt;fw_version);</div><div class='add'>+		psp-&gt;spdm_drv.size_bytes	= le32_to_cpu(desc-&gt;size_bytes);</div><div class='add'>+		psp-&gt;spdm_drv.start_addr	= ucode_start_addr;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_warn(psp-&gt;adev-&gt;dev, "Unsupported PSP FW type: %d\n", desc-&gt;fw_type);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -3329,18 +3668,23 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)</div><div class='ctx'> int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	char fw_name[PSP_FW_NAME_LEN];</div><div class='ctx'> 	const struct psp_firmware_header_v1_0 *sos_hdr;</div><div class='ctx'> 	const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;</div><div class='ctx'> 	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;</div><div class='ctx'> 	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;</div><div class='ctx'> 	const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;</div><div class='del'>-	int err = 0;</div><div class='add'>+	const struct psp_firmware_header_v2_1 *sos_hdr_v2_1;</div><div class='add'>+	int fw_index, fw_bin_count, start_index = 0;</div><div class='add'>+	const struct psp_fw_bin_desc *fw_bin;</div><div class='ctx'> 	uint8_t *ucode_array_start_addr;</div><div class='del'>-	int fw_index = 0;</div><div class='add'>+	int err = 0;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.sos_fw, fw_name);</div><div class='add'>+	if (amdgpu_is_kicker_fw(adev))</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.sos_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_sos_kicker.bin", chip_name);</div><div class='add'>+	else</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.sos_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_sos.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -3389,15 +3733,30 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> 	case 2:</div><div class='ctx'> 		sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev-&gt;psp.sos_fw-&gt;data;</div><div class='ctx'> </div><div class='del'>-		if (le32_to_cpu(sos_hdr_v2_0-&gt;psp_fw_bin_count) &gt;= UCODE_MAX_PSP_PACKAGING) {</div><div class='add'>+		fw_bin_count = le32_to_cpu(sos_hdr_v2_0-&gt;psp_fw_bin_count);</div><div class='add'>+</div><div class='add'>+		if (fw_bin_count &gt;= UCODE_MAX_PSP_PACKAGING) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "packed SOS count exceeds maximum limit\n");</div><div class='ctx'> 			err = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		for (fw_index = 0; fw_index &lt; le32_to_cpu(sos_hdr_v2_0-&gt;psp_fw_bin_count); fw_index++) {</div><div class='del'>-			err = parse_sos_bin_descriptor(psp,</div><div class='del'>-						       &amp;sos_hdr_v2_0-&gt;psp_fw_bin[fw_index],</div><div class='add'>+		if (sos_hdr_v2_0-&gt;header.header_version_minor == 1) {</div><div class='add'>+			sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev-&gt;psp.sos_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+			fw_bin = sos_hdr_v2_1-&gt;psp_fw_bin;</div><div class='add'>+</div><div class='add'>+			if (psp_is_aux_sos_load_required(psp))</div><div class='add'>+				start_index = le32_to_cpu(sos_hdr_v2_1-&gt;psp_aux_fw_bin_index);</div><div class='add'>+			else</div><div class='add'>+				fw_bin_count -= le32_to_cpu(sos_hdr_v2_1-&gt;psp_aux_fw_bin_index);</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			fw_bin = sos_hdr_v2_0-&gt;psp_fw_bin;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (fw_index = start_index; fw_index &lt; fw_bin_count; fw_index++) {</div><div class='add'>+			err = parse_sos_bin_descriptor(psp, fw_bin + fw_index,</div><div class='ctx'> 						       sos_hdr_v2_0);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				goto out;</div><div class='hunk'>@@ -3417,6 +3776,36 @@ out:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool is_ta_fw_applicable(struct psp_context *psp,</div><div class='add'>+			     const struct psp_fw_bin_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+	uint32_t fw_version;</div><div class='add'>+</div><div class='add'>+	switch (desc-&gt;fw_type) {</div><div class='add'>+	case TA_FW_TYPE_PSP_XGMI:</div><div class='add'>+	case TA_FW_TYPE_PSP_XGMI_AUX:</div><div class='add'>+		/* for now, AUX TA only exists on 13.0.6 ta bin,</div><div class='add'>+		 * from v20.00.0x.14</div><div class='add'>+		 */</div><div class='add'>+		if (amdgpu_ip_version(adev, MP0_HWIP, 0) ==</div><div class='add'>+		    IP_VERSION(13, 0, 6)) {</div><div class='add'>+			fw_version = le32_to_cpu(desc-&gt;fw_version);</div><div class='add'>+</div><div class='add'>+			if (adev-&gt;flags &amp; AMD_IS_APU &amp;&amp;</div><div class='add'>+			    (fw_version &amp; 0xff) &gt;= 0x14)</div><div class='add'>+				return desc-&gt;fw_type == TA_FW_TYPE_PSP_XGMI_AUX;</div><div class='add'>+			else</div><div class='add'>+				return desc-&gt;fw_type == TA_FW_TYPE_PSP_XGMI;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int parse_ta_bin_descriptor(struct psp_context *psp,</div><div class='ctx'> 				   const struct psp_fw_bin_desc *desc,</div><div class='ctx'> 				   const struct ta_firmware_header_v2_0 *ta_hdr)</div><div class='hunk'>@@ -3426,6 +3815,9 @@ static int parse_ta_bin_descriptor(struct psp_context *psp,</div><div class='ctx'> 	if (!psp || !desc || !ta_hdr)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!is_ta_fw_applicable(psp, desc))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	ucode_start_addr  = (uint8_t *)ta_hdr +</div><div class='ctx'> 			    le32_to_cpu(desc-&gt;offset_bytes) +</div><div class='ctx'> 			    le32_to_cpu(ta_hdr-&gt;header.ucode_array_offset_bytes);</div><div class='hunk'>@@ -3438,6 +3830,7 @@ static int parse_ta_bin_descriptor(struct psp_context *psp,</div><div class='ctx'> 		psp-&gt;asd_context.bin_desc.start_addr        = ucode_start_addr;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TA_FW_TYPE_PSP_XGMI:</div><div class='add'>+	case TA_FW_TYPE_PSP_XGMI_AUX:</div><div class='ctx'> 		psp-&gt;xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc-&gt;fw_version);</div><div class='ctx'> 		psp-&gt;xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc-&gt;size_bytes);</div><div class='ctx'> 		psp-&gt;xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;</div><div class='hunk'>@@ -3565,11 +3958,14 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> {</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	char fw_name[PSP_FW_NAME_LEN];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.ta_fw, fw_name);</div><div class='add'>+	if (amdgpu_is_kicker_fw(adev))</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.ta_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_ta_kicker.bin", chip_name);</div><div class='add'>+	else</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.ta_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_ta.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -3595,7 +3991,6 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	char fw_name[PSP_FW_NAME_LEN];</div><div class='ctx'> 	const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;</div><div class='ctx'> 	struct amdgpu_firmware_info *info = NULL;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -3605,15 +4000,16 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.cap_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.cap_fw, AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+				   "amdgpu/%s_cap.bin", chip_name);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		if (err == -ENODEV) {</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "cap microcode does not exist, skip\n");</div><div class='ctx'> 			err = 0;</div><div class='del'>-			goto out;</div><div class='add'>+		} else {</div><div class='add'>+			dev_err(adev-&gt;dev, "fail to initialize cap microcode\n");</div><div class='ctx'> 		}</div><div class='del'>-		dev_err(adev-&gt;dev, "fail to initialize cap microcode\n");</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	info = &amp;adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_CAP];</div><div class='hunk'>@@ -3634,13 +4030,49 @@ out:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_set_clockgating_state(void *handle,</div><div class='del'>-				     enum amd_clockgating_state state)</div><div class='add'>+int psp_config_sq_perfmon(struct psp_context *psp,</div><div class='add'>+		uint32_t xcp_id, bool core_override_enable,</div><div class='add'>+		bool reg_override_enable, bool perfmon_override_enable)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(psp-&gt;adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (xcp_id &gt; MAX_XCP) {</div><div class='add'>+		dev_err(psp-&gt;adev-&gt;dev, "invalid xcp_id %d\n", xcp_id);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) {</div><div class='add'>+		dev_err(psp-&gt;adev-&gt;dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n",</div><div class='add'>+			amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0));</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);</div><div class='add'>+</div><div class='add'>+	cmd-&gt;cmd_id	=	GFX_CMD_ID_CONFIG_SQ_PERFMON;</div><div class='add'>+	cmd-&gt;cmd.config_sq_perfmon.gfx_xcp_mask	=	BIT_MASK(xcp_id);</div><div class='add'>+	cmd-&gt;cmd.config_sq_perfmon.core_override	=	core_override_enable;</div><div class='add'>+	cmd-&gt;cmd.config_sq_perfmon.reg_override	=	reg_override_enable;</div><div class='add'>+	cmd-&gt;cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable;</div><div class='add'>+</div><div class='add'>+	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp-&gt;fence_buf_mc_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_warn(psp-&gt;adev-&gt;dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n",</div><div class='add'>+			xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable);</div><div class='add'>+</div><div class='add'>+	release_psp_cmd_buf(psp);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_set_powergating_state(void *handle,</div><div class='add'>+static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3652,10 +4084,12 @@ static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> 	uint32_t fw_ver;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP);</div><div class='add'>+	if (!ip_block || !ip_block-&gt;status.late_initialized) {</div><div class='ctx'> 		dev_info(adev-&gt;dev, "PSP block is not ready yet\n.");</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3680,13 +4114,14 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,</div><div class='ctx'> 	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='ctx'> 	int ret, idx;</div><div class='del'>-	char fw_name[100];</div><div class='ctx'> 	const struct firmware *usbc_pd_fw;</div><div class='ctx'> 	struct amdgpu_bo *fw_buf_bo = NULL;</div><div class='ctx'> 	uint64_t fw_pri_mc_addr;</div><div class='ctx'> 	void *fw_pri_cpu_addr;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP);</div><div class='add'>+	if (!ip_block || !ip_block-&gt;status.late_initialized) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "PSP block is not ready yet.");</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3694,8 +4129,8 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,</div><div class='ctx'> 	if (!drm_dev_enter(ddev, &amp;idx))</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);</div><div class='del'>-	ret = request_firmware(&amp;usbc_pd_fw, fw_name, adev-&gt;dev);</div><div class='add'>+	ret = amdgpu_ucode_request(adev, &amp;usbc_pd_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s", buf);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto fail;</div><div class='ctx'> </div><div class='hunk'>@@ -3717,7 +4152,7 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,</div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;fw_buf_bo, &amp;fw_pri_mc_addr, &amp;fw_pri_cpu_addr);</div><div class='ctx'> </div><div class='ctx'> rel_buf:</div><div class='del'>-	release_firmware(usbc_pd_fw);</div><div class='add'>+	amdgpu_ucode_release(&amp;usbc_pd_fw);</div><div class='ctx'> fail:</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to load USBC PD FW, err = %d", ret);</div><div class='hunk'>@@ -3756,7 +4191,7 @@ int is_psp_fw_valid(struct psp_bin_desc bin)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,</div><div class='del'>-					struct bin_attribute *bin_attr,</div><div class='add'>+					const struct bin_attribute *bin_attr,</div><div class='ctx'> 					char *buffer, loff_t pos, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = kobj_to_dev(kobj);</div><div class='hunk'>@@ -3792,7 +4227,7 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,</div><div class='del'>-				       struct bin_attribute *bin_attr, char *buffer,</div><div class='add'>+				       const struct bin_attribute *bin_attr, char *buffer,</div><div class='ctx'> 				       loff_t pos, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = kobj_to_dev(kobj);</div><div class='hunk'>@@ -3844,7 +4279,7 @@ rel_buf:</div><div class='ctx'>  * Writing to this file will stage an IFWI for update. Reading from this file</div><div class='ctx'>  * will trigger the update process.</div><div class='ctx'>  */</div><div class='del'>-static struct bin_attribute psp_vbflash_bin_attr = {</div><div class='add'>+static const struct bin_attribute psp_vbflash_bin_attr = {</div><div class='ctx'> 	.attr = {.name = "psp_vbflash", .mode = 0660},</div><div class='ctx'> 	.size = 0,</div><div class='ctx'> 	.write = amdgpu_psp_vbflash_write,</div><div class='hunk'>@@ -3875,7 +4310,7 @@ static ssize_t amdgpu_psp_vbflash_status(struct device *dev,</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);</div><div class='ctx'> </div><div class='del'>-static struct bin_attribute *bin_flash_attrs[] = {</div><div class='add'>+static const struct bin_attribute *const bin_flash_attrs[] = {</div><div class='ctx'> 	&amp;psp_vbflash_bin_attr,</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='hunk'>@@ -3899,7 +4334,7 @@ static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribu</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,</div><div class='del'>-						struct bin_attribute *attr,</div><div class='add'>+						const struct bin_attribute *attr,</div><div class='ctx'> 						int idx)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = kobj_to_dev(kobj);</div><div class='hunk'>@@ -3916,20 +4351,119 @@ const struct attribute_group amdgpu_flash_attr_group = {</div><div class='ctx'> 	.is_visible = amdgpu_flash_attr_is_visible,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = filp-&gt;f_inode-&gt;i_private;</div><div class='add'>+	struct spirom_bo *bo_triplet;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* serialize the open() file calling */</div><div class='add'>+	if (!mutex_trylock(&amp;adev-&gt;psp.mutex))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * make sure only one userpace process is alive for dumping so that</div><div class='add'>+	 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed.</div><div class='add'>+	 * let's say the case where one process try opening the file while</div><div class='add'>+	 * another one has proceeded to read or release. In this way, eliminate</div><div class='add'>+	 * the use of mutex for read() or release() callback as well.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;psp.spirom_dump_trip) {</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;psp.mutex);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo_triplet = kzalloc(sizeof(struct spirom_bo), GFP_KERNEL);</div><div class='add'>+	if (!bo_triplet) {</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;psp.mutex);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2,</div><div class='add'>+				      AMDGPU_GPU_PAGE_SIZE,</div><div class='add'>+				      AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				      &amp;bo_triplet-&gt;bo,</div><div class='add'>+				      &amp;bo_triplet-&gt;mc_addr,</div><div class='add'>+				      &amp;bo_triplet-&gt;cpu_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto rel_trip;</div><div class='add'>+</div><div class='add'>+	ret = psp_dump_spirom(&amp;adev-&gt;psp, bo_triplet-&gt;mc_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto rel_bo;</div><div class='add'>+</div><div class='add'>+	adev-&gt;psp.spirom_dump_trip = bo_triplet;</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;psp.mutex);</div><div class='add'>+	return 0;</div><div class='add'>+rel_bo:</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;bo_triplet-&gt;bo, &amp;bo_triplet-&gt;mc_addr,</div><div class='add'>+			      &amp;bo_triplet-&gt;cpu_addr);</div><div class='add'>+rel_trip:</div><div class='add'>+	kfree(bo_triplet);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;psp.mutex);</div><div class='add'>+	dev_err(adev-&gt;dev, "Trying IFWI dump fails, err = %d\n", ret);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size,</div><div class='add'>+					    loff_t *pos)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = filp-&gt;f_inode-&gt;i_private;</div><div class='add'>+	struct spirom_bo *bo_triplet = adev-&gt;psp.spirom_dump_trip;</div><div class='add'>+</div><div class='add'>+	if (!bo_triplet)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return simple_read_from_buffer(buf,</div><div class='add'>+				       size,</div><div class='add'>+				       pos, bo_triplet-&gt;cpu_addr,</div><div class='add'>+				       AMD_VBIOS_FILE_MAX_SIZE_B * 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = filp-&gt;f_inode-&gt;i_private;</div><div class='add'>+	struct spirom_bo *bo_triplet = adev-&gt;psp.spirom_dump_trip;</div><div class='add'>+</div><div class='add'>+	if (bo_triplet) {</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;bo_triplet-&gt;bo, &amp;bo_triplet-&gt;mc_addr,</div><div class='add'>+				      &amp;bo_triplet-&gt;cpu_addr);</div><div class='add'>+		kfree(bo_triplet);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;psp.spirom_dump_trip = NULL;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations psp_dump_spirom_debugfs_ops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = psp_read_spirom_debugfs_open,</div><div class='add'>+	.read = psp_read_spirom_debugfs_read,</div><div class='add'>+	.release = psp_read_spirom_debugfs_release,</div><div class='add'>+	.llseek = default_llseek,</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_psp_debugfs_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+</div><div class='add'>+	debugfs_create_file_size("psp_spirom_dump", 0444, minor-&gt;debugfs_root,</div><div class='add'>+				 adev, &amp;psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amd_ip_funcs psp_ip_funcs = {</div><div class='ctx'> 	.name = "psp",</div><div class='ctx'> 	.early_init = psp_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = psp_sw_init,</div><div class='ctx'> 	.sw_fini = psp_sw_fini,</div><div class='ctx'> 	.hw_init = psp_hw_init,</div><div class='ctx'> 	.hw_fini = psp_hw_fini,</div><div class='ctx'> 	.suspend = psp_suspend,</div><div class='ctx'> 	.resume = psp_resume,</div><div class='del'>-	.is_idle = NULL,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.wait_for_idle = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = psp_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = psp_set_powergating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h<br/>index ee16f134ae92..237b624aa51c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h</a></div><div class='hunk'>@@ -39,6 +39,29 @@</div><div class='ctx'> #define PSP_TMR_ALIGNMENT	0x100000</div><div class='ctx'> #define PSP_FW_NAME_LEN		0x24</div><div class='ctx'> </div><div class='add'>+/* VBIOS gfl defines */</div><div class='add'>+#define MBOX_READY_MASK 0x80000000</div><div class='add'>+#define MBOX_STATUS_MASK 0x0000FFFF</div><div class='add'>+#define MBOX_COMMAND_MASK 0x00FF0000</div><div class='add'>+#define MBOX_READY_FLAG 0x80000000</div><div class='add'>+#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2</div><div class='add'>+#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3</div><div class='add'>+#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4</div><div class='add'>+#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO 0xf</div><div class='add'>+#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10</div><div class='add'>+#define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11</div><div class='add'>+</div><div class='add'>+/* Command register bit 31 set to indicate readiness */</div><div class='add'>+#define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE)</div><div class='add'>+#define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)</div><div class='add'>+</div><div class='add'>+/* Values to check for a successful GFX_CMD response wait. Check against</div><div class='add'>+ * both status bits and response state - helps to detect a command failure</div><div class='add'>+ * or other unexpected cases like a device drop reading all 0xFFs</div><div class='add'>+ */</div><div class='add'>+#define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE)</div><div class='add'>+#define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)</div><div class='add'>+</div><div class='ctx'> extern const struct attribute_group amdgpu_flash_attr_group;</div><div class='ctx'> </div><div class='ctx'> enum psp_shared_mem_size {</div><div class='hunk'>@@ -73,11 +96,14 @@ enum psp_bootloader_cmd {</div><div class='ctx'> 	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,</div><div class='ctx'> 	PSP_BL__LOAD_SOCDRV             = 0xB0000,</div><div class='ctx'> 	PSP_BL__LOAD_DBGDRV             = 0xC0000,</div><div class='add'>+	PSP_BL__LOAD_HADDRV		= PSP_BL__LOAD_DBGDRV,</div><div class='ctx'> 	PSP_BL__LOAD_INTFDRV		= 0xD0000,</div><div class='del'>-	PSP_BL__LOAD_RASDRV		    = 0xE0000,</div><div class='add'>+	PSP_BL__LOAD_RASDRV		= 0xE0000,</div><div class='add'>+	PSP_BL__LOAD_IPKEYMGRDRV	= 0xF0000,</div><div class='ctx'> 	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,</div><div class='ctx'> 	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,</div><div class='ctx'> 	PSP_BL__LOAD_TOS_SPL_TABLE	= 0x10000000,</div><div class='add'>+	PSP_BL__LOAD_SPDMDRV		= 0x20000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum psp_ring_type {</div><div class='hunk'>@@ -104,9 +130,13 @@ enum psp_reg_prog_id {</div><div class='ctx'> 	PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */</div><div class='ctx'> 	PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */</div><div class='ctx'> 	PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */</div><div class='add'>+	PSP_REG_MMHUB_L1_TLB_CNTL = 25,</div><div class='ctx'> 	PSP_REG_LAST</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */</div><div class='add'>+#define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */</div><div class='add'>+</div><div class='ctx'> struct psp_funcs {</div><div class='ctx'> 	int (*init_microcode)(struct psp_context *psp);</div><div class='ctx'> 	int (*wait_for_bootloader)(struct psp_context *psp);</div><div class='hunk'>@@ -117,6 +147,8 @@ struct psp_funcs {</div><div class='ctx'> 	int (*bootloader_load_intf_drv)(struct psp_context *psp);</div><div class='ctx'> 	int (*bootloader_load_dbg_drv)(struct psp_context *psp);</div><div class='ctx'> 	int (*bootloader_load_ras_drv)(struct psp_context *psp);</div><div class='add'>+	int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp);</div><div class='add'>+	int (*bootloader_load_spdm_drv)(struct psp_context *psp);</div><div class='ctx'> 	int (*bootloader_load_sos)(struct psp_context *psp);</div><div class='ctx'> 	int (*ring_create)(struct psp_context *psp,</div><div class='ctx'> 			   enum psp_ring_type ring_type);</div><div class='hunk'>@@ -132,9 +164,14 @@ struct psp_funcs {</div><div class='ctx'> 	int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);</div><div class='ctx'> 	int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);</div><div class='ctx'> 	int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);</div><div class='add'>+	int (*dump_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);</div><div class='ctx'> 	int (*vbflash_stat)(struct psp_context *psp);</div><div class='ctx'> 	int (*fatal_error_recovery_quirk)(struct psp_context *psp);</div><div class='ctx'> 	bool (*get_ras_capability)(struct psp_context *psp);</div><div class='add'>+	bool (*is_aux_sos_load_required)(struct psp_context *psp);</div><div class='add'>+	bool (*is_reload_needed)(struct psp_context *psp);</div><div class='add'>+	int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val,</div><div class='add'>+				   enum psp_reg_prog_id id);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ta_funcs {</div><div class='hunk'>@@ -197,6 +234,7 @@ struct psp_xgmi_context {</div><div class='ctx'> struct psp_ras_context {</div><div class='ctx'> 	struct ta_context		context;</div><div class='ctx'> 	struct amdgpu_ras		*ras;</div><div class='add'>+	struct mutex			mutex;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942</div><div class='hunk'>@@ -311,6 +349,14 @@ struct psp_runtime_scpm_entry {</div><div class='ctx'> 	enum psp_runtime_scpm_authentication scpm_status;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+struct spirom_bo {</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	uint64_t mc_addr;</div><div class='add'>+	void *cpu_addr;</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> struct psp_context {</div><div class='ctx'> 	struct amdgpu_device		*adev;</div><div class='ctx'> 	struct psp_ring			km_ring;</div><div class='hunk'>@@ -336,6 +382,8 @@ struct psp_context {</div><div class='ctx'> 	struct psp_bin_desc		intf_drv;</div><div class='ctx'> 	struct psp_bin_desc		dbg_drv;</div><div class='ctx'> 	struct psp_bin_desc		ras_drv;</div><div class='add'>+	struct psp_bin_desc		ipkeymgr_drv;</div><div class='add'>+	struct psp_bin_desc		spdm_drv;</div><div class='ctx'> </div><div class='ctx'> 	/* tmr buffer */</div><div class='ctx'> 	struct amdgpu_bo		*tmr_bo;</div><div class='hunk'>@@ -396,6 +444,9 @@ struct psp_context {</div><div class='ctx'> 	char				*vbflash_tmp_buf;</div><div class='ctx'> 	size_t				vbflash_image_size;</div><div class='ctx'> 	bool				vbflash_done;</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct spirom_bo *spirom_dump_trip;</div><div class='add'>+#endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_psp_funcs {</div><div class='hunk'>@@ -424,6 +475,12 @@ struct amdgpu_psp_funcs {</div><div class='ctx'> #define psp_bootloader_load_ras_drv(psp) \</div><div class='ctx'> 		((psp)-&gt;funcs-&gt;bootloader_load_ras_drv ? \</div><div class='ctx'> 		(psp)-&gt;funcs-&gt;bootloader_load_ras_drv((psp)) : 0)</div><div class='add'>+#define psp_bootloader_load_ipkeymgr_drv(psp) \</div><div class='add'>+		((psp)-&gt;funcs-&gt;bootloader_load_ipkeymgr_drv ? \</div><div class='add'>+		 (psp)-&gt;funcs-&gt;bootloader_load_ipkeymgr_drv((psp)) : 0)</div><div class='add'>+#define psp_bootloader_load_spdm_drv(psp) \</div><div class='add'>+		((psp)-&gt;funcs-&gt;bootloader_load_spdm_drv ? \</div><div class='add'>+		 (psp)-&gt;funcs-&gt;bootloader_load_spdm_drv((psp)) : 0)</div><div class='ctx'> #define psp_bootloader_load_sos(psp) \</div><div class='ctx'> 		((psp)-&gt;funcs-&gt;bootloader_load_sos ? (psp)-&gt;funcs-&gt;bootloader_load_sos((psp)) : 0)</div><div class='ctx'> #define psp_smu_reload_quirk(psp) \</div><div class='hunk'>@@ -448,6 +505,10 @@ struct amdgpu_psp_funcs {</div><div class='ctx'> 	((psp)-&gt;funcs-&gt;update_spirom ? \</div><div class='ctx'> 	(psp)-&gt;funcs-&gt;update_spirom((psp), fw_pri_mc_addr) : -EINVAL)</div><div class='ctx'> </div><div class='add'>+#define psp_dump_spirom(psp, fw_pri_mc_addr) \</div><div class='add'>+	((psp)-&gt;funcs-&gt;dump_spirom ? \</div><div class='add'>+	(psp)-&gt;funcs-&gt;dump_spirom((psp), fw_pri_mc_addr) : -EINVAL)</div><div class='add'>+</div><div class='ctx'> #define psp_vbflash_status(psp) \</div><div class='ctx'> 	((psp)-&gt;funcs-&gt;vbflash_stat ? \</div><div class='ctx'> 	(psp)-&gt;funcs-&gt;vbflash_stat((psp)) : -EINVAL)</div><div class='hunk'>@@ -456,6 +517,13 @@ struct amdgpu_psp_funcs {</div><div class='ctx'> 	((psp)-&gt;funcs-&gt;fatal_error_recovery_quirk ? \</div><div class='ctx'> 	(psp)-&gt;funcs-&gt;fatal_error_recovery_quirk((psp)) : 0)</div><div class='ctx'> </div><div class='add'>+#define psp_is_aux_sos_load_required(psp) \</div><div class='add'>+	((psp)-&gt;funcs-&gt;is_aux_sos_load_required ? (psp)-&gt;funcs-&gt;is_aux_sos_load_required((psp)) : 0)</div><div class='add'>+</div><div class='add'>+#define psp_reg_program_no_ring(psp, val, id) \</div><div class='add'>+	((psp)-&gt;funcs-&gt;reg_program_no_ring ? \</div><div class='add'>+	(psp)-&gt;funcs-&gt;reg_program_no_ring((psp), val, id) : -EINVAL)</div><div class='add'>+</div><div class='ctx'> extern const struct amd_ip_funcs psp_ip_funcs;</div><div class='ctx'> </div><div class='ctx'> extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;</div><div class='hunk'>@@ -467,8 +535,8 @@ extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;</div><div class='ctx'> extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;</div><div class='ctx'> extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;</div><div class='ctx'> </div><div class='del'>-extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,</div><div class='del'>-			uint32_t field_val, uint32_t mask, bool check_changed);</div><div class='add'>+int psp_wait_for(struct psp_context *psp, uint32_t reg_index,</div><div class='add'>+		 uint32_t field_val, uint32_t mask, uint32_t flags);</div><div class='ctx'> extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,</div><div class='ctx'> 			uint32_t field_val, uint32_t mask, uint32_t msec_timeout);</div><div class='ctx'> </div><div class='hunk'>@@ -534,15 +602,25 @@ int psp_init_cap_microcode(struct psp_context *psp,</div><div class='ctx'> 			  const char *chip_name);</div><div class='ctx'> int psp_get_fw_attestation_records_addr(struct psp_context *psp,</div><div class='ctx'> 					uint64_t *output_ptr);</div><div class='del'>-</div><div class='add'>+int psp_update_fw_reservation(struct psp_context *psp);</div><div class='ctx'> int psp_load_fw_list(struct psp_context *psp,</div><div class='ctx'> 		     struct amdgpu_firmware_info **ucode_list, int ucode_count);</div><div class='ctx'> void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);</div><div class='ctx'> </div><div class='ctx'> int psp_spatial_partition(struct psp_context *psp, int mode);</div><div class='add'>+int psp_memory_partition(struct psp_context *psp, int mode);</div><div class='ctx'> </div><div class='ctx'> int is_psp_fw_valid(struct psp_bin_desc bin);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_psp_get_ras_capability(struct psp_context *psp);</div><div class='add'>+</div><div class='add'>+int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id,</div><div class='add'>+	bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);</div><div class='add'>+bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val,</div><div class='add'>+				   enum psp_reg_prog_id id);</div><div class='add'>+void amdgpu_psp_debugfs_init(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c<br/>index ca5c86e5f7cd..6e8aad91bcd3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c</a></div><div class='hunk'>@@ -166,15 +166,14 @@ static ssize_t ta_if_load_debugfs_write(struct file *fp, const char *buf, size_t</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> </div><div class='add'>+	if (ta_bin_len &gt; PSP_1_MEG)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	copy_pos += sizeof(uint32_t);</div><div class='ctx'> </div><div class='del'>-	ta_bin = kzalloc(ta_bin_len, GFP_KERNEL);</div><div class='del'>-	if (!ta_bin)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	if (copy_from_user((void *)ta_bin, &amp;buf[copy_pos], ta_bin_len)) {</div><div class='del'>-		ret = -EFAULT;</div><div class='del'>-		goto err_free_bin;</div><div class='del'>-	}</div><div class='add'>+	ta_bin = memdup_user(&amp;buf[copy_pos], ta_bin_len);</div><div class='add'>+	if (IS_ERR(ta_bin))</div><div class='add'>+		return PTR_ERR(ta_bin);</div><div class='ctx'> </div><div class='ctx'> 	/* Set TA context and functions */</div><div class='ctx'> 	set_ta_context_funcs(psp, ta_type, &amp;context);</div><div class='hunk'>@@ -324,17 +323,13 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> 	copy_pos += sizeof(uint32_t);</div><div class='ctx'> </div><div class='del'>-	shared_buf = kzalloc(shared_buf_len, GFP_KERNEL);</div><div class='del'>-	if (!shared_buf)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	if (copy_from_user((void *)shared_buf, &amp;buf[copy_pos], shared_buf_len)) {</div><div class='del'>-		ret = -EFAULT;</div><div class='del'>-		goto err_free_shared_buf;</div><div class='del'>-	}</div><div class='add'>+	shared_buf = memdup_user(&amp;buf[copy_pos], shared_buf_len);</div><div class='add'>+	if (IS_ERR(shared_buf))</div><div class='add'>+		return PTR_ERR(shared_buf);</div><div class='ctx'> </div><div class='ctx'> 	set_ta_context_funcs(psp, ta_type, &amp;context);</div><div class='ctx'> </div><div class='del'>-	if (!context-&gt;initialized) {</div><div class='add'>+	if (!context || !context-&gt;initialized) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "TA is not initialized\n");</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto err_free_shared_buf;</div><div class='hunk'>@@ -348,6 +343,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size</div><div class='ctx'> </div><div class='ctx'> 	context-&gt;session_id = ta_id;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;psp-&gt;ras_context.mutex);</div><div class='ctx'> 	ret = prep_ta_mem_context(&amp;context-&gt;mem_context, shared_buf, shared_buf_len);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_free_shared_buf;</div><div class='hunk'>@@ -366,6 +362,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size</div><div class='ctx'> 		ret = -EFAULT;</div><div class='ctx'> </div><div class='ctx'> err_free_shared_buf:</div><div class='add'>+	mutex_unlock(&amp;psp-&gt;ras_context.mutex);</div><div class='ctx'> 	kfree(shared_buf);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c<br/>index 123bcf5c2bb1..bacf888735db 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c</a></div><div class='hunk'>@@ -101,7 +101,6 @@ static ssize_t amdgpu_rap_debugfs_write(struct file *f, const char __user *buf,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gfx_off_ctrl(adev, true);</div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return size;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br/>index 8ebab6f22e5a..2a6cf7963dde 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c</a></div><div class='hunk'>@@ -36,10 +36,12 @@</div><div class='ctx'> #include "amdgpu_xgmi.h"</div><div class='ctx'> #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"</div><div class='ctx'> #include "nbio_v4_3.h"</div><div class='add'>+#include "nbif_v6_3_1.h"</div><div class='ctx'> #include "nbio_v7_9.h"</div><div class='ctx'> #include "atom.h"</div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='ctx'> #include "amdgpu_psp.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_X86_MCE_AMD</div><div class='ctx'> #include &lt;asm/mce.h&gt;</div><div class='hunk'>@@ -76,6 +78,7 @@ const char *ras_block_string[] = {</div><div class='ctx'> 	"jpeg",</div><div class='ctx'> 	"ih",</div><div class='ctx'> 	"mpio",</div><div class='add'>+	"mmsch",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const char *ras_mca_block_string[] = {</div><div class='hunk'>@@ -120,7 +123,14 @@ const char *get_ras_block_str(struct ras_common_if *ras_block)</div><div class='ctx'> /* typical ECC bad page rate is 1 bad page per 100MB VRAM */</div><div class='ctx'> #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)</div><div class='ctx'> </div><div class='del'>-#define MAX_UMC_POISON_POLLING_TIME_ASYNC  100  //ms</div><div class='add'>+#define MAX_UMC_POISON_POLLING_TIME_ASYNC  10</div><div class='add'>+</div><div class='add'>+#define AMDGPU_RAS_RETIRE_PAGE_INTERVAL 100  //ms</div><div class='add'>+</div><div class='add'>+#define MAX_FLUSH_RETIRE_DWORK_TIMES  100</div><div class='add'>+</div><div class='add'>+#define BYPASS_ALLOCATED_ADDRESS        0x0</div><div class='add'>+#define BYPASS_INITIALIZATION_ADDRESS   0x1</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_ras_retire_page_reservation {</div><div class='ctx'> 	AMDGPU_RAS_RETIRE_PAGE_RESERVED,</div><div class='hunk'>@@ -130,12 +140,18 @@ enum amdgpu_ras_retire_page_reservation {</div><div class='ctx'> </div><div class='ctx'> atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);</div><div class='ctx'> </div><div class='del'>-static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,</div><div class='add'>+static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,</div><div class='ctx'> 				uint64_t addr);</div><div class='del'>-static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,</div><div class='add'>+static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev,</div><div class='ctx'> 				uint64_t addr);</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev);</div><div class='add'>+static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_X86_MCE_AMD</div><div class='ctx'> static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);</div><div class='add'>+static void</div><div class='add'>+amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev);</div><div class='ctx'> struct mce_notifier_adev_list {</div><div class='ctx'> 	struct amdgpu_device *devs[MAX_GPU_INSTANCE];</div><div class='ctx'> 	int num_gpu;</div><div class='hunk'>@@ -163,18 +179,16 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre</div><div class='ctx'> 	struct eeprom_table_record err_rec;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if ((address &gt;= adev-&gt;gmc.mc_vram_size) ||</div><div class='del'>-	    (address &gt;= RAS_UMC_INJECT_ADDR_LIMIT)) {</div><div class='add'>+	ret = amdgpu_ras_check_bad_page(adev, address);</div><div class='add'>+	if (ret == -EINVAL) {</div><div class='ctx'> 		dev_warn(adev-&gt;dev,</div><div class='del'>-		         "RAS WARN: input address 0x%llx is invalid.\n",</div><div class='del'>-		         address);</div><div class='add'>+			"RAS WARN: input address 0x%llx is invalid.\n",</div><div class='add'>+			address);</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (amdgpu_ras_check_bad_page(adev, address)) {</div><div class='add'>+	} else if (ret == 1) {</div><div class='ctx'> 		dev_warn(adev-&gt;dev,</div><div class='del'>-			 "RAS WARN: 0x%llx has already been marked as bad page!\n",</div><div class='del'>-			 address);</div><div class='add'>+			"RAS WARN: 0x%llx has already been marked as bad page!\n",</div><div class='add'>+			address);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -188,7 +202,7 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_bad_page_threshold != 0) {</div><div class='ctx'> 		amdgpu_ras_add_bad_pages(adev, err_data.err_addr,</div><div class='del'>-					 err_data.err_addr_cnt);</div><div class='add'>+					 err_data.err_addr_cnt, false);</div><div class='ctx'> 		amdgpu_ras_save_bad_pages(adev, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -201,6 +215,56 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_check_address_validity(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t address, uint64_t flags)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_vram_block_info blk_info;</div><div class='add'>+	uint64_t page_pfns[32] = {0};</div><div class='add'>+	int i, ret, count;</div><div class='add'>+	bool hit = false;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, UMC_HWIP, 0) &lt; IP_VERSION(12, 0, 0))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		if (amdgpu_virt_check_vf_critical_region(adev, address, &amp;hit))</div><div class='add'>+			return -EPERM;</div><div class='add'>+		return hit ? -EACCES : 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((address &gt;= adev-&gt;gmc.mc_vram_size) ||</div><div class='add'>+	    (address &gt;= RAS_UMC_INJECT_ADDR_LIMIT))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	count = amdgpu_umc_lookup_bad_pages_in_a_row(adev,</div><div class='add'>+				address, page_pfns, ARRAY_SIZE(page_pfns));</div><div class='add'>+	if (count &lt;= 0)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		memset(&amp;blk_info, 0, sizeof(blk_info));</div><div class='add'>+		ret = amdgpu_vram_mgr_query_address_block_info(&amp;adev-&gt;mman.vram_mgr,</div><div class='add'>+					page_pfns[i] &lt;&lt; AMDGPU_GPU_PAGE_SHIFT, &amp;blk_info);</div><div class='add'>+		if (!ret) {</div><div class='add'>+			/* The input address that needs to be checked is allocated by</div><div class='add'>+			 * current calling process, so it is necessary to exclude</div><div class='add'>+			 * the calling process.</div><div class='add'>+			 */</div><div class='add'>+			if ((flags == BYPASS_ALLOCATED_ADDRESS) &amp;&amp;</div><div class='add'>+			    ((blk_info.task.pid != task_pid_nr(current)) ||</div><div class='add'>+				strncmp(blk_info.task.comm, current-&gt;comm, TASK_COMM_LEN)))</div><div class='add'>+				return -EACCES;</div><div class='add'>+			else if ((flags == BYPASS_INITIALIZATION_ADDRESS) &amp;&amp;</div><div class='add'>+				(blk_info.task.pid == con-&gt;init_task_pid) &amp;&amp;</div><div class='add'>+				!strncmp(blk_info.task.comm, con-&gt;init_task_comm, TASK_COMM_LEN))</div><div class='add'>+				return -EACCES;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,</div><div class='ctx'> 					size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='hunk'>@@ -291,6 +355,8 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,</div><div class='ctx'> 		op = 2;</div><div class='ctx'> 	else if (strstr(str, "retire_page") != NULL)</div><div class='ctx'> 		op = 3;</div><div class='add'>+	else if (strstr(str, "check_address") != NULL)</div><div class='add'>+		op = 4;</div><div class='ctx'> 	else if (str[0] &amp;&amp; str[1] &amp;&amp; str[2] &amp;&amp; str[3])</div><div class='ctx'> 		/* ascii string, but commands are not matched. */</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -305,6 +371,15 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,</div><div class='ctx'> 			data-&gt;inject.address = address;</div><div class='ctx'> </div><div class='ctx'> 			return 0;</div><div class='add'>+		} else if (op == 4) {</div><div class='add'>+			if (sscanf(str, "%*s 0x%llx 0x%llx", &amp;address, &amp;value) != 2 &amp;&amp;</div><div class='add'>+			    sscanf(str, "%*s %llu %llu", &amp;address, &amp;value) != 2)</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			data-&gt;op = op;</div><div class='add'>+			data-&gt;inject.address = address;</div><div class='add'>+			data-&gt;inject.value = value;</div><div class='add'>+			return 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_ras_find_block_id_by_name(block_name, &amp;block_id))</div><div class='hunk'>@@ -494,6 +569,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,</div><div class='ctx'> 			return size;</div><div class='ctx'> 		else</div><div class='ctx'> 			return ret;</div><div class='add'>+	} else if (data.op == 4) {</div><div class='add'>+		ret = amdgpu_check_address_validity(adev, data.inject.address, data.inject.value);</div><div class='add'>+		return ret ? ret : size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_ras_is_supported(adev, data.head.block))</div><div class='hunk'>@@ -507,22 +585,16 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,</div><div class='ctx'> 		ret = amdgpu_ras_feature_enable(adev, &amp;data.head, 1);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='del'>-		if ((data.inject.address &gt;= adev-&gt;gmc.mc_vram_size &amp;&amp;</div><div class='del'>-		    adev-&gt;gmc.mc_vram_size) ||</div><div class='del'>-		    (data.inject.address &gt;= RAS_UMC_INJECT_ADDR_LIMIT)) {</div><div class='del'>-			dev_warn(adev-&gt;dev, "RAS WARN: input address "</div><div class='del'>-					"0x%llx is invalid.",</div><div class='add'>+		/* umc ce/ue error injection for a bad page is not allowed */</div><div class='add'>+		if (data.head.block == AMDGPU_RAS_BLOCK__UMC)</div><div class='add'>+			ret = amdgpu_ras_check_bad_page(adev, data.inject.address);</div><div class='add'>+		if (ret == -EINVAL) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "RAS WARN: input address 0x%llx is invalid.",</div><div class='ctx'> 					data.inject.address);</div><div class='del'>-			ret = -EINVAL;</div><div class='ctx'> 			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* umc ce/ue error injection for a bad page is not allowed */</div><div class='del'>-		if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &amp;&amp;</div><div class='del'>-		    amdgpu_ras_check_bad_page(adev, data.inject.address)) {</div><div class='del'>-			dev_warn(adev-&gt;dev, "RAS WARN: inject: 0x%llx has "</div><div class='del'>-				 "already been marked as bad!\n",</div><div class='del'>-				 data.inject.address);</div><div class='add'>+		} else if (ret == 1) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "RAS WARN: inject: 0x%llx has already been marked as bad!\n",</div><div class='add'>+					data.inject.address);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -542,6 +614,8 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,</div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: AMDGPU RAS debugfs EEPROM table reset interface</div><div class='ctx'>  *</div><div class='hunk'>@@ -566,6 +640,11 @@ static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,</div><div class='ctx'> 		(struct amdgpu_device *)file_inode(f)-&gt;i_private;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_uniras_enabled(adev)) {</div><div class='add'>+		ret = amdgpu_uniras_clear_badpages_info(adev);</div><div class='add'>+		return ret ? ret : size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = amdgpu_ras_eeprom_reset_table(</div><div class='ctx'> 		&amp;(amdgpu_ras_get_context(adev)-&gt;eeprom_control));</div><div class='ctx'> </div><div class='hunk'>@@ -878,7 +957,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> </div><div class='del'>-			/* gfx block ras dsiable cmd must send to ras-ta */</div><div class='add'>+			/* gfx block ras disable cmd must send to ras-ta */</div><div class='ctx'> 			if (head-&gt;block == AMDGPU_RAS_BLOCK__GFX)</div><div class='ctx'> 				con-&gt;features |= BIT(head-&gt;block);</div><div class='ctx'> </div><div class='hunk'>@@ -1045,6 +1124,7 @@ static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_d</div><div class='ctx'> static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,</div><div class='ctx'> 					      struct ras_manager *ras_mgr,</div><div class='ctx'> 					      struct ras_err_data *err_data,</div><div class='add'>+					      struct ras_query_context *qctx,</div><div class='ctx'> 					      const char *blk_name,</div><div class='ctx'> 					      bool is_ue,</div><div class='ctx'> 					      bool is_de)</div><div class='hunk'>@@ -1052,27 +1132,28 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,</div><div class='ctx'> 	struct amdgpu_smuio_mcm_config_info *mcm_info;</div><div class='ctx'> 	struct ras_err_node *err_node;</div><div class='ctx'> 	struct ras_err_info *err_info;</div><div class='add'>+	u64 event_id = qctx-&gt;evid.event_id;</div><div class='ctx'> </div><div class='ctx'> 	if (is_ue) {</div><div class='ctx'> 		for_each_ras_error(err_node, err_data) {</div><div class='ctx'> 			err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 			mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='ctx'> 			if (err_info-&gt;ue_count) {</div><div class='del'>-				dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-					 "%lld new uncorrectable hardware errors detected in %s block\n",</div><div class='del'>-					 mcm_info-&gt;socket_id,</div><div class='del'>-					 mcm_info-&gt;die_id,</div><div class='del'>-					 err_info-&gt;ue_count,</div><div class='del'>-					 blk_name);</div><div class='add'>+				RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "</div><div class='add'>+					      "%lld new uncorrectable hardware errors detected in %s block\n",</div><div class='add'>+					      mcm_info-&gt;socket_id,</div><div class='add'>+					      mcm_info-&gt;die_id,</div><div class='add'>+					      err_info-&gt;ue_count,</div><div class='add'>+					      blk_name);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for_each_ras_error(err_node, &amp;ras_mgr-&gt;err_data) {</div><div class='ctx'> 			err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 			mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='del'>-			dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-				 "%lld uncorrectable hardware errors detected in total in %s block\n",</div><div class='del'>-				 mcm_info-&gt;socket_id, mcm_info-&gt;die_id, err_info-&gt;ue_count, blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "</div><div class='add'>+				      "%lld uncorrectable hardware errors detected in total in %s block\n",</div><div class='add'>+				      mcm_info-&gt;socket_id, mcm_info-&gt;die_id, err_info-&gt;ue_count, blk_name);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1081,44 +1162,47 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,</div><div class='ctx'> 				err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 				mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='ctx'> 				if (err_info-&gt;de_count) {</div><div class='del'>-					dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-						"%lld new deferred hardware errors detected in %s block\n",</div><div class='del'>-						mcm_info-&gt;socket_id,</div><div class='del'>-						mcm_info-&gt;die_id,</div><div class='del'>-						err_info-&gt;de_count,</div><div class='del'>-						blk_name);</div><div class='add'>+					RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "</div><div class='add'>+						      "%lld new deferred hardware errors detected in %s block\n",</div><div class='add'>+						      mcm_info-&gt;socket_id,</div><div class='add'>+						      mcm_info-&gt;die_id,</div><div class='add'>+						      err_info-&gt;de_count,</div><div class='add'>+						      blk_name);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			for_each_ras_error(err_node, &amp;ras_mgr-&gt;err_data) {</div><div class='ctx'> 				err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 				mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='del'>-				dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-					"%lld deferred hardware errors detected in total in %s block\n",</div><div class='del'>-					mcm_info-&gt;socket_id, mcm_info-&gt;die_id,</div><div class='del'>-					err_info-&gt;de_count, blk_name);</div><div class='add'>+				RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "</div><div class='add'>+					      "%lld deferred hardware errors detected in total in %s block\n",</div><div class='add'>+					      mcm_info-&gt;socket_id, mcm_info-&gt;die_id,</div><div class='add'>+					      err_info-&gt;de_count, blk_name);</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='add'>+			if (adev-&gt;debug_disable_ce_logs)</div><div class='add'>+				return;</div><div class='add'>+</div><div class='ctx'> 			for_each_ras_error(err_node, err_data) {</div><div class='ctx'> 				err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 				mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='ctx'> 				if (err_info-&gt;ce_count) {</div><div class='del'>-					dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-						"%lld new correctable hardware errors detected in %s block\n",</div><div class='del'>-						mcm_info-&gt;socket_id,</div><div class='del'>-						mcm_info-&gt;die_id,</div><div class='del'>-						err_info-&gt;ce_count,</div><div class='del'>-						blk_name);</div><div class='add'>+					RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "</div><div class='add'>+						      "%lld new correctable hardware errors detected in %s block\n",</div><div class='add'>+						      mcm_info-&gt;socket_id,</div><div class='add'>+						      mcm_info-&gt;die_id,</div><div class='add'>+						      err_info-&gt;ce_count,</div><div class='add'>+						      blk_name);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			for_each_ras_error(err_node, &amp;ras_mgr-&gt;err_data) {</div><div class='ctx'> 				err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 				mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='del'>-				dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-					"%lld correctable hardware errors detected in total in %s block\n",</div><div class='del'>-					mcm_info-&gt;socket_id, mcm_info-&gt;die_id,</div><div class='del'>-					err_info-&gt;ce_count, blk_name);</div><div class='add'>+				RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "</div><div class='add'>+					      "%lld correctable hardware errors detected in total in %s block\n",</div><div class='add'>+					      mcm_info-&gt;socket_id, mcm_info-&gt;die_id,</div><div class='add'>+					      err_info-&gt;ce_count, blk_name);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1131,81 +1215,119 @@ static inline bool err_data_has_source_info(struct ras_err_data *data)</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,</div><div class='ctx'> 					     struct ras_query_if *query_if,</div><div class='del'>-					     struct ras_err_data *err_data)</div><div class='add'>+					     struct ras_err_data *err_data,</div><div class='add'>+					     struct ras_query_context *qctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &amp;query_if-&gt;head);</div><div class='ctx'> 	const char *blk_name = get_ras_block_str(&amp;query_if-&gt;head);</div><div class='add'>+	u64 event_id = qctx-&gt;evid.event_id;</div><div class='ctx'> </div><div class='ctx'> 	if (err_data-&gt;ce_count) {</div><div class='ctx'> 		if (err_data_has_source_info(err_data)) {</div><div class='del'>-			amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data,</div><div class='add'>+			amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx,</div><div class='ctx'> 							  blk_name, false, false);</div><div class='ctx'> 		} else if (!adev-&gt;aid_mask &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_socket_id &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_die_id) {</div><div class='del'>-			dev_info(adev-&gt;dev, "socket: %d, die: %d "</div><div class='del'>-				 "%ld correctable hardware errors "</div><div class='del'>-				 "detected in %s block\n",</div><div class='del'>-				 adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='del'>-				 adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='del'>-				 ras_mgr-&gt;err_data.ce_count,</div><div class='del'>-				 blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "</div><div class='add'>+				      "%ld correctable hardware errors "</div><div class='add'>+				      "detected in %s block\n",</div><div class='add'>+				      adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='add'>+				      adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='add'>+				      ras_mgr-&gt;err_data.ce_count,</div><div class='add'>+				      blk_name);</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_info(adev-&gt;dev, "%ld correctable hardware errors "</div><div class='del'>-				 "detected in %s block\n",</div><div class='del'>-				 ras_mgr-&gt;err_data.ce_count,</div><div class='del'>-				 blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "%ld correctable hardware errors "</div><div class='add'>+				      "detected in %s block\n",</div><div class='add'>+				      ras_mgr-&gt;err_data.ce_count,</div><div class='add'>+				      blk_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (err_data-&gt;ue_count) {</div><div class='ctx'> 		if (err_data_has_source_info(err_data)) {</div><div class='del'>-			amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data,</div><div class='add'>+			amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx,</div><div class='ctx'> 							  blk_name, true, false);</div><div class='ctx'> 		} else if (!adev-&gt;aid_mask &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_socket_id &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_die_id) {</div><div class='del'>-			dev_info(adev-&gt;dev, "socket: %d, die: %d "</div><div class='del'>-				 "%ld uncorrectable hardware errors "</div><div class='del'>-				 "detected in %s block\n",</div><div class='del'>-				 adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='del'>-				 adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='del'>-				 ras_mgr-&gt;err_data.ue_count,</div><div class='del'>-				 blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "</div><div class='add'>+				      "%ld uncorrectable hardware errors "</div><div class='add'>+				      "detected in %s block\n",</div><div class='add'>+				      adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='add'>+				      adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='add'>+				      ras_mgr-&gt;err_data.ue_count,</div><div class='add'>+				      blk_name);</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_info(adev-&gt;dev, "%ld uncorrectable hardware errors "</div><div class='del'>-				 "detected in %s block\n",</div><div class='del'>-				 ras_mgr-&gt;err_data.ue_count,</div><div class='del'>-				 blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "%ld uncorrectable hardware errors "</div><div class='add'>+				      "detected in %s block\n",</div><div class='add'>+				      ras_mgr-&gt;err_data.ue_count,</div><div class='add'>+				      blk_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (err_data-&gt;de_count) {</div><div class='ctx'> 		if (err_data_has_source_info(err_data)) {</div><div class='del'>-			amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data,</div><div class='add'>+			amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx,</div><div class='ctx'> 							  blk_name, false, true);</div><div class='ctx'> 		} else if (!adev-&gt;aid_mask &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_socket_id &amp;&amp;</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_die_id) {</div><div class='del'>-			dev_info(adev-&gt;dev, "socket: %d, die: %d "</div><div class='del'>-				 "%ld deferred hardware errors "</div><div class='del'>-				 "detected in %s block\n",</div><div class='del'>-				 adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='del'>-				 adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='del'>-				 ras_mgr-&gt;err_data.de_count,</div><div class='del'>-				 blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "</div><div class='add'>+				      "%ld deferred hardware errors "</div><div class='add'>+				      "detected in %s block\n",</div><div class='add'>+				      adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='add'>+				      adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='add'>+				      ras_mgr-&gt;err_data.de_count,</div><div class='add'>+				      blk_name);</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_info(adev-&gt;dev, "%ld deferred hardware errors "</div><div class='del'>-				 "detected in %s block\n",</div><div class='del'>-				 ras_mgr-&gt;err_data.de_count,</div><div class='del'>-				 blk_name);</div><div class='add'>+			RAS_EVENT_LOG(adev, event_id, "%ld deferred hardware errors "</div><div class='add'>+				      "detected in %s block\n",</div><div class='add'>+				      ras_mgr-&gt;err_data.de_count,</div><div class='add'>+				      blk_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_ras_virt_error_generate_report(struct amdgpu_device *adev,</div><div class='add'>+						  struct ras_query_if *query_if,</div><div class='add'>+						  struct ras_err_data *err_data,</div><div class='add'>+						  struct ras_query_context *qctx)</div><div class='add'>+{</div><div class='add'>+	unsigned long new_ue, new_ce, new_de;</div><div class='add'>+	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &amp;query_if-&gt;head);</div><div class='add'>+	const char *blk_name = get_ras_block_str(&amp;query_if-&gt;head);</div><div class='add'>+	u64 event_id = qctx-&gt;evid.event_id;</div><div class='add'>+</div><div class='add'>+	new_ce = err_data-&gt;ce_count - obj-&gt;err_data.ce_count;</div><div class='add'>+	new_ue = err_data-&gt;ue_count - obj-&gt;err_data.ue_count;</div><div class='add'>+	new_de = err_data-&gt;de_count - obj-&gt;err_data.de_count;</div><div class='add'>+</div><div class='add'>+	if (new_ce) {</div><div class='add'>+		RAS_EVENT_LOG(adev, event_id, "%lu correctable hardware errors "</div><div class='add'>+			      "detected in %s block\n",</div><div class='add'>+			      new_ce,</div><div class='add'>+			      blk_name);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (new_ue) {</div><div class='add'>+		RAS_EVENT_LOG(adev, event_id, "%lu uncorrectable hardware errors "</div><div class='add'>+			      "detected in %s block\n",</div><div class='add'>+			      new_ue,</div><div class='add'>+			      blk_name);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (new_de) {</div><div class='add'>+		RAS_EVENT_LOG(adev, event_id, "%lu deferred hardware errors "</div><div class='add'>+			      "detected in %s block\n",</div><div class='add'>+			      new_de,</div><div class='add'>+			      blk_name);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_node *err_node;</div><div class='hunk'>@@ -1215,11 +1337,11 @@ static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s</div><div class='ctx'> 		for_each_ras_error(err_node, err_data) {</div><div class='ctx'> 			err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 			amdgpu_ras_error_statistic_de_count(&amp;obj-&gt;err_data,</div><div class='del'>-					&amp;err_info-&gt;mcm_info, NULL, err_info-&gt;de_count);</div><div class='add'>+					&amp;err_info-&gt;mcm_info, err_info-&gt;de_count);</div><div class='ctx'> 			amdgpu_ras_error_statistic_ce_count(&amp;obj-&gt;err_data,</div><div class='del'>-					&amp;err_info-&gt;mcm_info, NULL, err_info-&gt;ce_count);</div><div class='add'>+					&amp;err_info-&gt;mcm_info, err_info-&gt;ce_count);</div><div class='ctx'> 			amdgpu_ras_error_statistic_ue_count(&amp;obj-&gt;err_data,</div><div class='del'>-					&amp;err_info-&gt;mcm_info, NULL, err_info-&gt;ue_count);</div><div class='add'>+					&amp;err_info-&gt;mcm_info, err_info-&gt;ue_count);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* for legacy asic path which doesn't has error source info */</div><div class='hunk'>@@ -1229,6 +1351,15 @@ static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_ras_mgr_virt_error_data_statistics_update(struct ras_manager *obj,</div><div class='add'>+							     struct ras_err_data *err_data)</div><div class='add'>+{</div><div class='add'>+	/* Host reports absolute counts */</div><div class='add'>+	obj-&gt;err_data.ue_count = err_data-&gt;ue_count;</div><div class='add'>+	obj-&gt;err_data.ce_count = err_data-&gt;ce_count;</div><div class='add'>+	obj-&gt;err_data.de_count = err_data-&gt;de_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct ras_manager *get_ras_manager(struct amdgpu_device *adev, enum amdgpu_ras_block blk)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_common_if head;</div><div class='hunk'>@@ -1244,6 +1375,10 @@ int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_manager *obj;</div><div class='ctx'> </div><div class='add'>+	/* in resume phase, no need to create aca fs node */</div><div class='add'>+	if (adev-&gt;in_suspend || amdgpu_reset_in_recovery(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	obj = get_ras_manager(adev, blk);</div><div class='ctx'> 	if (!obj)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1265,7 +1400,8 @@ int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='del'>-					 enum aca_error_type type, struct ras_err_data *err_data)</div><div class='add'>+					 enum aca_error_type type, struct ras_err_data *err_data,</div><div class='add'>+					 struct ras_query_context *qctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_manager *obj;</div><div class='ctx'> </div><div class='hunk'>@@ -1273,7 +1409,7 @@ static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu</div><div class='ctx'> 	if (!obj)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return amdgpu_aca_get_error_data(adev, &amp;obj-&gt;aca_handle, type, err_data);</div><div class='add'>+	return amdgpu_aca_get_error_data(adev, &amp;obj-&gt;aca_handle, type, err_data, qctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,</div><div class='hunk'>@@ -1284,16 +1420,20 @@ ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *a</div><div class='ctx'> 		.head = obj-&gt;head,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	if (!amdgpu_ras_get_error_query_ready(obj-&gt;adev))</div><div class='add'>+		return sysfs_emit(buf, "Query currently inaccessible\n");</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_ras_query_error_status(obj-&gt;adev, &amp;info))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,</div><div class='del'>-			  "ce", info.ce_count);</div><div class='add'>+	return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count,</div><div class='add'>+			  "ce", info.ce_count, "de", info.de_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,</div><div class='ctx'> 						struct ras_query_if *info,</div><div class='ctx'> 						struct ras_err_data *err_data,</div><div class='add'>+						struct ras_query_context *qctx,</div><div class='ctx'> 						unsigned int error_query_mode)</div><div class='ctx'> {</div><div class='ctx'> 	enum amdgpu_ras_block blk = info ? info-&gt;head.block : AMDGPU_RAS_BLOCK_COUNT;</div><div class='hunk'>@@ -1306,7 +1446,9 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,</div><div class='ctx'> 	if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {</div><div class='add'>+	if (error_query_mode == AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) {</div><div class='add'>+		return amdgpu_virt_req_ras_err_count(adev, blk, err_data);</div><div class='add'>+	} else if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {</div><div class='ctx'> 		if (info-&gt;head.block == AMDGPU_RAS_BLOCK__UMC) {</div><div class='ctx'> 			amdgpu_ras_get_ecc_info(adev, err_data);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -1329,17 +1471,21 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (amdgpu_aca_is_enabled(adev)) {</div><div class='del'>-			ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_UE, err_data);</div><div class='add'>+			ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_UE, err_data, qctx);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> </div><div class='del'>-			ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data);</div><div class='add'>+			ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data, qctx);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_DEFERRED, err_data, qctx);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* FIXME: add code to check return value later */</div><div class='del'>-			amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data);</div><div class='del'>-			amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data);</div><div class='add'>+			amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data, qctx);</div><div class='add'>+			amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data, qctx);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1347,10 +1493,13 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* query/inject/cure begin */</div><div class='del'>-int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)</div><div class='add'>+static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev,</div><div class='add'>+						    struct ras_query_if *info,</div><div class='add'>+						    enum ras_event_type type)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &amp;info-&gt;head);</div><div class='ctx'> 	struct ras_err_data err_data;</div><div class='add'>+	struct ras_query_context qctx;</div><div class='ctx'> 	unsigned int error_query_mode;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1364,35 +1513,98 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_i</div><div class='ctx'> 	if (!amdgpu_ras_get_error_query_mode(adev, &amp;error_query_mode))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	memset(&amp;qctx, 0, sizeof(qctx));</div><div class='add'>+	qctx.evid.type = type;</div><div class='add'>+	qctx.evid.event_id = amdgpu_ras_acquire_event_id(adev, type);</div><div class='add'>+</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out_fini_err_data;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = amdgpu_ras_query_error_status_helper(adev, info,</div><div class='ctx'> 						   &amp;err_data,</div><div class='add'>+						   &amp;qctx,</div><div class='ctx'> 						   error_query_mode);</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out_fini_err_data;</div><div class='ctx'> </div><div class='del'>-	amdgpu_rasmgr_error_data_statistic_update(obj, &amp;err_data);</div><div class='add'>+	if (error_query_mode != AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) {</div><div class='add'>+		amdgpu_rasmgr_error_data_statistic_update(obj, &amp;err_data);</div><div class='add'>+		amdgpu_ras_error_generate_report(adev, info, &amp;err_data, &amp;qctx);</div><div class='add'>+	} else {</div><div class='add'>+		/* Host provides absolute error counts. First generate the report</div><div class='add'>+		 * using the previous VF internal count against new host count.</div><div class='add'>+		 * Then Update VF internal count.</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_ras_virt_error_generate_report(adev, info, &amp;err_data, &amp;qctx);</div><div class='add'>+		amdgpu_ras_mgr_virt_error_data_statistics_update(obj, &amp;err_data);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;ue_count = obj-&gt;err_data.ue_count;</div><div class='ctx'> 	info-&gt;ce_count = obj-&gt;err_data.ce_count;</div><div class='ctx'> 	info-&gt;de_count = obj-&gt;err_data.de_count;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_generate_report(adev, info, &amp;err_data);</div><div class='del'>-</div><div class='ctx'> out_fini_err_data:</div><div class='ctx'> 	amdgpu_ras_error_data_fini(&amp;err_data);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct ras_cmd_dev_handle req = {0};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CLEAR_BAD_PAGE_INFO,</div><div class='add'>+				&amp;req, sizeof(req), NULL, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to clear bad pages info, ret: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_uniras_query_block_ecc(struct amdgpu_device *adev,</div><div class='add'>+			struct ras_query_if *info)</div><div class='add'>+{</div><div class='add'>+	struct ras_cmd_block_ecc_info_req req = {0};</div><div class='add'>+	struct ras_cmd_block_ecc_info_rsp rsp = {0};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	req.block_id = info-&gt;head.block;</div><div class='add'>+	req.subblock_id = info-&gt;head.sub_block_index;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BLOCK_ECC_STATUS,</div><div class='add'>+				&amp;req, sizeof(req), &amp;rsp, sizeof(rsp));</div><div class='add'>+	if (!ret) {</div><div class='add'>+		info-&gt;ce_count = rsp.ce_count;</div><div class='add'>+		info-&gt;ue_count = rsp.ue_count;</div><div class='add'>+		info-&gt;de_count = rsp.de_count;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		return amdgpu_uniras_query_block_ecc(adev, info);</div><div class='add'>+	else</div><div class='add'>+		return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 		enum amdgpu_ras_block block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);</div><div class='del'>-	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='ctx'> 	const struct aca_smu_funcs *smu_funcs = adev-&gt;aca.smu_funcs;</div><div class='del'>-	struct amdgpu_hive_info *hive;</div><div class='del'>-	int hive_ras_recovery = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!block_obj || !block_obj-&gt;hw_ops) {</div><div class='ctx'> 		dev_dbg_once(adev-&gt;dev, "%s doesn't config RAS function\n",</div><div class='hunk'>@@ -1404,15 +1616,11 @@ int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 	    !amdgpu_ras_get_aca_debug_mode(adev))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	hive = amdgpu_get_xgmi_hive(adev);</div><div class='del'>-	if (hive) {</div><div class='del'>-		hive_ras_recovery = atomic_read(&amp;hive-&gt;ras_recovery);</div><div class='del'>-		amdgpu_put_xgmi_hive(hive);</div><div class='del'>-	}</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	/* skip ras error reset in gpu reset */</div><div class='del'>-	if ((amdgpu_in_reset(adev) || atomic_read(&amp;ras-&gt;in_recovery) ||</div><div class='del'>-	    hive_ras_recovery) &amp;&amp;</div><div class='add'>+	if ((amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) &amp;&amp;</div><div class='ctx'> 	    ((smu_funcs &amp;&amp; smu_funcs-&gt;set_debug_mode) ||</div><div class='ctx'> 	     (mca_funcs &amp;&amp; mca_funcs-&gt;mca_set_debug_mode)))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='hunk'>@@ -1440,6 +1648,27 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_uniras_error_inject(struct amdgpu_device *adev,</div><div class='add'>+		struct ras_inject_if *info)</div><div class='add'>+{</div><div class='add'>+	struct ras_cmd_inject_error_req inject_req;</div><div class='add'>+	struct ras_cmd_inject_error_rsp rsp;</div><div class='add'>+</div><div class='add'>+	if (!info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	memset(&amp;inject_req, 0, sizeof(inject_req));</div><div class='add'>+	inject_req.block_id = info-&gt;head.block;</div><div class='add'>+	inject_req.subblock_id = info-&gt;head.sub_block_index;</div><div class='add'>+	inject_req.address = info-&gt;address;</div><div class='add'>+	inject_req.error_type = info-&gt;head.type;</div><div class='add'>+	inject_req.instance_mask = info-&gt;instance_mask;</div><div class='add'>+	inject_req.method = info-&gt;value;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__INJECT_ERROR,</div><div class='add'>+			&amp;inject_req, sizeof(inject_req), &amp;rsp, sizeof(rsp));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* wrapper of psp_ras_trigger_error */</div><div class='ctx'> int amdgpu_ras_error_inject(struct amdgpu_device *adev,</div><div class='ctx'> 		struct ras_inject_if *info)</div><div class='hunk'>@@ -1457,6 +1686,9 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,</div><div class='ctx'> 							info-&gt;head.block,</div><div class='ctx'> 							info-&gt;head.sub_block_index);</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		return amdgpu_uniras_error_inject(adev, info);</div><div class='add'>+</div><div class='ctx'> 	/* inject on guest isn't allowed, return success directly */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1601,7 +1833,9 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,</div><div class='ctx'> /* sysfs begin */</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,</div><div class='del'>-		struct ras_badpage **bps, unsigned int *count);</div><div class='add'>+		struct ras_badpage *bps, uint32_t count, uint32_t start);</div><div class='add'>+static int amdgpu_uniras_badpages_read(struct amdgpu_device *adev,</div><div class='add'>+		struct ras_badpage *bps, uint32_t count, uint32_t start);</div><div class='ctx'> </div><div class='ctx'> static char *amdgpu_ras_badpage_flags_str(unsigned int flags)</div><div class='ctx'> {</div><div class='hunk'>@@ -1647,7 +1881,7 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags)</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,</div><div class='del'>-		struct kobject *kobj, struct bin_attribute *attr,</div><div class='add'>+		struct kobject *kobj, const struct bin_attribute *attr,</div><div class='ctx'> 		char *buf, loff_t ppos, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con =</div><div class='hunk'>@@ -1659,19 +1893,50 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,</div><div class='ctx'> 	unsigned int end = div64_ul(ppos + count - 1, element_size);</div><div class='ctx'> 	ssize_t s = 0;</div><div class='ctx'> 	struct ras_badpage *bps = NULL;</div><div class='del'>-	unsigned int bps_count = 0;</div><div class='add'>+	int bps_count = 0, i, status;</div><div class='add'>+	uint64_t address;</div><div class='ctx'> </div><div class='ctx'> 	memset(buf, 0, count);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ras_badpages_read(adev, &amp;bps, &amp;bps_count))</div><div class='add'>+	bps_count = end - start;</div><div class='add'>+	bps = kmalloc_array(bps_count, sizeof(*bps), GFP_KERNEL);</div><div class='add'>+	if (!bps)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	memset(bps, 0, sizeof(*bps) * bps_count);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		bps_count = amdgpu_uniras_badpages_read(adev, bps, bps_count, start);</div><div class='add'>+	else</div><div class='add'>+		bps_count = amdgpu_ras_badpages_read(adev, bps, bps_count, start);</div><div class='add'>+</div><div class='add'>+	if (bps_count &lt;= 0) {</div><div class='add'>+		kfree(bps);</div><div class='ctx'> 		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; bps_count; i++) {</div><div class='add'>+		address = ((uint64_t)bps[i].bp) &lt;&lt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+		if (amdgpu_ras_check_critical_address(adev, address))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		bps[i].size = AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+		status = amdgpu_vram_mgr_query_page_status(&amp;adev-&gt;mman.vram_mgr,</div><div class='add'>+					address);</div><div class='add'>+		if (status == -EBUSY)</div><div class='add'>+			bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;</div><div class='add'>+		else if (status == -ENOENT)</div><div class='add'>+			bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;</div><div class='add'>+		else</div><div class='add'>+			bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED;</div><div class='ctx'> </div><div class='del'>-	for (; start &lt; end &amp;&amp; start &lt; bps_count; start++)</div><div class='ctx'> 		s += scnprintf(&amp;buf[s], element_size + 1,</div><div class='ctx'> 				"0x%08x : 0x%08x : %1s\n",</div><div class='del'>-				bps[start].bp,</div><div class='del'>-				bps[start].size,</div><div class='del'>-				amdgpu_ras_badpage_flags_str(bps[start].flags));</div><div class='add'>+				bps[i].bp,</div><div class='add'>+				bps[i].size,</div><div class='add'>+				amdgpu_ras_badpage_flags_str(bps[i].flags));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(bps);</div><div class='ctx'> </div><div class='hunk'>@@ -1687,12 +1952,42 @@ static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,</div><div class='ctx'> 	return sysfs_emit(buf, "feature mask: 0x%x\n", con-&gt;features);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool amdgpu_ras_get_version_info(struct amdgpu_device *adev, u32 *major,</div><div class='add'>+			u32 *minor, u32 *rev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!adev || !major || !minor || !rev || !amdgpu_uniras_enabled(adev))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_RAS) {</div><div class='add'>+			*major = adev-&gt;ip_blocks[i].version-&gt;major;</div><div class='add'>+			*minor = adev-&gt;ip_blocks[i].version-&gt;minor;</div><div class='add'>+			*rev = adev-&gt;ip_blocks[i].version-&gt;rev;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,</div><div class='ctx'> 		struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con =</div><div class='ctx'> 		container_of(attr, struct amdgpu_ras, version_attr);</div><div class='del'>-	return sysfs_emit(buf, "table version: 0x%x\n", con-&gt;eeprom_control.tbl_hdr.version);</div><div class='add'>+	u32 major, minor, rev;</div><div class='add'>+	ssize_t size = 0;</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "table version: 0x%x\n",</div><div class='add'>+			con-&gt;eeprom_control.tbl_hdr.version);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_get_version_info(con-&gt;adev, &amp;major, &amp;minor, &amp;rev))</div><div class='add'>+		size += sysfs_emit_at(buf, size, "ras version: %u.%u.%u\n",</div><div class='add'>+			major, minor, rev);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,</div><div class='hunk'>@@ -1703,6 +1998,39 @@ static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,</div><div class='ctx'> 	return sysfs_emit(buf, "schema: 0x%x\n", con-&gt;schema);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct {</div><div class='add'>+	enum ras_event_type type;</div><div class='add'>+	const char *name;</div><div class='add'>+} dump_event[] = {</div><div class='add'>+	{RAS_EVENT_TYPE_FATAL, "Fatal Error"},</div><div class='add'>+	{RAS_EVENT_TYPE_POISON_CREATION, "Poison Creation"},</div><div class='add'>+	{RAS_EVENT_TYPE_POISON_CONSUMPTION, "Poison Consumption"},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_ras_sysfs_event_state_show(struct device *dev,</div><div class='add'>+						 struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con =</div><div class='add'>+		container_of(attr, struct amdgpu_ras, event_state_attr);</div><div class='add'>+	struct ras_event_manager *event_mgr = con-&gt;event_mgr;</div><div class='add'>+	struct ras_event_state *event_state;</div><div class='add'>+	int i, size = 0;</div><div class='add'>+</div><div class='add'>+	if (!event_mgr)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "current seqno: %llu\n", atomic64_read(&amp;event_mgr-&gt;seqno));</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(dump_event); i++) {</div><div class='add'>+		event_state = &amp;event_mgr-&gt;event_state[dump_event[i].type];</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s: count:%llu, last_seqno:%llu\n",</div><div class='add'>+				      dump_event[i].name,</div><div class='add'>+				      atomic64_read(&amp;event_state-&gt;count),</div><div class='add'>+				      event_state-&gt;last_seqno);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return (ssize_t)size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='hunk'>@@ -1720,6 +2048,7 @@ static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)</div><div class='ctx'> 		&amp;con-&gt;features_attr.attr,</div><div class='ctx'> 		&amp;con-&gt;version_attr.attr,</div><div class='ctx'> 		&amp;con-&gt;schema_attr.attr,</div><div class='add'>+		&amp;con-&gt;event_state_attr.attr,</div><div class='ctx'> 		NULL</div><div class='ctx'> 	};</div><div class='ctx'> 	struct attribute_group group = {</div><div class='hunk'>@@ -1738,9 +2067,15 @@ int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (!obj || obj-&gt;attr_inuse)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_sriov_vf(adev) &amp;&amp; !amdgpu_virt_ras_telemetry_block_en(adev, head-&gt;block))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	get_obj(obj);</div><div class='ctx'> </div><div class='ctx'> 	snprintf(obj-&gt;fs_data.sysfs_name, sizeof(obj-&gt;fs_data.sysfs_name),</div><div class='hunk'>@@ -1772,6 +2107,9 @@ int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (!obj || !obj-&gt;attr_inuse)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1884,6 +2222,24 @@ static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,</div><div class='ctx'> 			    obj, &amp;amdgpu_ras_debugfs_ops);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool amdgpu_ras_aca_is_supported(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	bool ret;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='add'>+		ret = true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='hunk'>@@ -1910,23 +2266,27 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_aca_is_enabled(adev))</div><div class='del'>-		amdgpu_aca_smu_debugfs_init(adev, dir);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_mca_smu_debugfs_init(adev, dir);</div><div class='add'>+	if (amdgpu_ras_aca_is_supported(adev)) {</div><div class='add'>+		if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+			amdgpu_aca_smu_debugfs_init(adev, dir);</div><div class='add'>+		else</div><div class='add'>+			amdgpu_mca_smu_debugfs_init(adev, dir);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* debugfs end */</div><div class='ctx'> </div><div class='ctx'> /* ras fs */</div><div class='del'>-static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,</div><div class='del'>-		amdgpu_ras_sysfs_badpages_read, NULL, 0);</div><div class='add'>+static const BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,</div><div class='add'>+		      amdgpu_ras_sysfs_badpages_read, NULL, 0);</div><div class='ctx'> static DEVICE_ATTR(features, S_IRUGO,</div><div class='ctx'> 		amdgpu_ras_sysfs_features_read, NULL);</div><div class='ctx'> static DEVICE_ATTR(version, 0444,</div><div class='ctx'> 		amdgpu_ras_sysfs_version_show, NULL);</div><div class='ctx'> static DEVICE_ATTR(schema, 0444,</div><div class='ctx'> 		amdgpu_ras_sysfs_schema_show, NULL);</div><div class='add'>+static DEVICE_ATTR(event_state, 0444,</div><div class='add'>+		   amdgpu_ras_sysfs_event_state_show, NULL);</div><div class='ctx'> static int amdgpu_ras_fs_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='hunk'>@@ -1937,9 +2297,10 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev)</div><div class='ctx'> 		&amp;con-&gt;features_attr.attr,</div><div class='ctx'> 		&amp;con-&gt;version_attr.attr,</div><div class='ctx'> 		&amp;con-&gt;schema_attr.attr,</div><div class='add'>+		&amp;con-&gt;event_state_attr.attr,</div><div class='ctx'> 		NULL</div><div class='ctx'> 	};</div><div class='del'>-	struct bin_attribute *bin_attrs[] = {</div><div class='add'>+	const struct bin_attribute *bin_attrs[] = {</div><div class='ctx'> 		NULL,</div><div class='ctx'> 		NULL,</div><div class='ctx'> 	};</div><div class='hunk'>@@ -1959,13 +2320,16 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev)</div><div class='ctx'> 	con-&gt;schema_attr = dev_attr_schema;</div><div class='ctx'> 	sysfs_attr_init(attrs[2]);</div><div class='ctx'> </div><div class='add'>+	/* add event_state entry */</div><div class='add'>+	con-&gt;event_state_attr = dev_attr_event_state;</div><div class='add'>+	sysfs_attr_init(attrs[3]);</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_bad_page_threshold != 0) {</div><div class='ctx'> 		/* add bad_page_features entry */</div><div class='del'>-		bin_attr_gpu_vram_bad_pages.private = NULL;</div><div class='ctx'> 		con-&gt;badpages_attr = bin_attr_gpu_vram_bad_pages;</div><div class='add'>+		sysfs_bin_attr_init(&amp;con-&gt;badpages_attr);</div><div class='ctx'> 		bin_attrs[0] = &amp;con-&gt;badpages_attr;</div><div class='ctx'> 		group.bin_attrs = bin_attrs;</div><div class='del'>-		sysfs_bin_attr_init(bin_attrs[0]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = sysfs_create_group(&amp;adev-&gt;dev-&gt;kobj, &amp;group);</div><div class='hunk'>@@ -2005,6 +2369,21 @@ void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)</div><div class='ctx'> 	/* Fatal error events are handled on host side */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return;</div><div class='add'>+	/*</div><div class='add'>+	 * If the current interrupt is caused by a non-fatal RAS error, skip</div><div class='add'>+	 * check for fatal error. For fatal errors, FED status of all devices</div><div class='add'>+	 * in XGMI hive gets set when the first device gets fatal error</div><div class='add'>+	 * interrupt. The error gets propagated to other devices as well, so</div><div class='add'>+	 * make sure to ack the interrupt regardless of FED status.</div><div class='add'>+	 */</div><div class='add'>+	if (!amdgpu_ras_get_fed_status(adev) &amp;&amp;</div><div class='add'>+	    amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_uniras_enabled(adev)) {</div><div class='add'>+		amdgpu_ras_mgr_handle_fatal_interrupt(adev, NULL);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;nbio.ras &amp;&amp;</div><div class='ctx'> 	    adev-&gt;nbio.ras-&gt;handle_ras_controller_intr_no_bifring)</div><div class='hunk'>@@ -2022,10 +2401,19 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *</div><div class='ctx'> 	struct amdgpu_device *adev = obj-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ras_block_object *block_obj =</div><div class='ctx'> 		amdgpu_ras_get_ras_block(adev, obj-&gt;head.block, 0);</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	enum ras_event_type type = RAS_EVENT_TYPE_POISON_CONSUMPTION;</div><div class='add'>+	u64 event_id;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!block_obj)</div><div class='add'>+	if (!block_obj || !con)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	ret = amdgpu_ras_mark_ras_event(adev, type);</div><div class='add'>+	if (ret)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_set_err_poison(adev, block_obj-&gt;ras_comm.block);</div><div class='ctx'> 	/* both query_poison_status and handle_poison_consumption are optional,</div><div class='ctx'> 	 * but at least one of them should be implemented if we need poison</div><div class='ctx'> 	 * consumption handler</div><div class='hunk'>@@ -2041,26 +2429,49 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_umc_poison_handler(adev, obj-&gt;head.block, false);</div><div class='add'>+	amdgpu_umc_poison_handler(adev, obj-&gt;head.block, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (block_obj-&gt;hw_ops &amp;&amp; block_obj-&gt;hw_ops-&gt;handle_poison_consumption)</div><div class='ctx'> 		poison_stat = block_obj-&gt;hw_ops-&gt;handle_poison_consumption(adev);</div><div class='ctx'> </div><div class='del'>-	/* gpu reset is fallback for failed and default cases */</div><div class='del'>-	if (poison_stat) {</div><div class='del'>-		dev_info(adev-&gt;dev, "GPU reset for %s RAS poison consumption is issued!\n",</div><div class='del'>-				block_obj-&gt;ras_comm.name);</div><div class='add'>+	/* gpu reset is fallback for failed and default cases.</div><div class='add'>+	 * For RMA case, amdgpu_umc_poison_handler will handle gpu reset.</div><div class='add'>+	 */</div><div class='add'>+	if (poison_stat &amp;&amp; !amdgpu_ras_is_rma(adev)) {</div><div class='add'>+		event_id = amdgpu_ras_acquire_event_id(adev, type);</div><div class='add'>+		RAS_EVENT_LOG(adev, event_id,</div><div class='add'>+			      "GPU reset for %s RAS poison consumption is issued!\n",</div><div class='add'>+			      block_obj-&gt;ras_comm.name);</div><div class='ctx'> 		amdgpu_ras_reset_gpu(adev);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_gfx_poison_consumption_handler(adev, entry);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (!poison_stat)</div><div class='add'>+		amdgpu_gfx_poison_consumption_handler(adev, entry);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,</div><div class='ctx'> 				struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	dev_info(obj-&gt;adev-&gt;dev,</div><div class='del'>-		"Poison is created\n");</div><div class='add'>+	struct amdgpu_device *adev = obj-&gt;adev;</div><div class='add'>+	enum ras_event_type type = RAS_EVENT_TYPE_POISON_CREATION;</div><div class='add'>+	u64 event_id;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_ras_mark_ras_event(adev, type);</div><div class='add'>+	if (ret)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	event_id = amdgpu_ras_acquire_event_id(adev, type);</div><div class='add'>+	RAS_EVENT_LOG(adev, event_id, "Poison is created\n");</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(obj-&gt;adev, UMC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0)) {</div><div class='add'>+		struct amdgpu_ras *con = amdgpu_ras_get_context(obj-&gt;adev);</div><div class='add'>+</div><div class='add'>+		atomic_inc(&amp;con-&gt;page_retirement_req_cnt);</div><div class='add'>+		atomic_inc(&amp;con-&gt;poison_creation_count);</div><div class='add'>+</div><div class='add'>+		wake_up(&amp;con-&gt;page_retirement_wq);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,</div><div class='hunk'>@@ -2080,6 +2491,7 @@ static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,</div><div class='ctx'> 	/* Let IP handle its data, maybe we need get the output</div><div class='ctx'> 	 * from the callback to update the error type/count, etc</div><div class='ctx'> 	 */</div><div class='add'>+	amdgpu_ras_set_fed(obj-&gt;adev, true);</div><div class='ctx'> 	ret = data-&gt;cb(obj-&gt;adev, &amp;err_data, entry);</div><div class='ctx'> 	/* ue will trigger an interrupt, and in that case</div><div class='ctx'> 	 * we need do a reset to recovery the whole system.</div><div class='hunk'>@@ -2140,12 +2552,25 @@ static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)</div><div class='ctx'> int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,</div><div class='ctx'> 		struct ras_dispatch_if *info)</div><div class='ctx'> {</div><div class='del'>-	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &amp;info-&gt;head);</div><div class='del'>-	struct ras_ih_data *data = &amp;obj-&gt;ih_data;</div><div class='add'>+	struct ras_manager *obj;</div><div class='add'>+	struct ras_ih_data *data;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_uniras_enabled(adev)) {</div><div class='add'>+		struct ras_ih_info ih_info;</div><div class='add'>+</div><div class='add'>+		memset(&amp;ih_info, 0, sizeof(ih_info));</div><div class='add'>+		ih_info.block = info-&gt;head.block;</div><div class='add'>+		memcpy(&amp;ih_info.iv_entry, info-&gt;entry, sizeof(struct amdgpu_iv_entry));</div><div class='add'>+</div><div class='add'>+		return amdgpu_ras_mgr_handle_controller_interrupt(adev, &amp;ih_info);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	obj = amdgpu_ras_find_obj(adev, &amp;info-&gt;head);</div><div class='ctx'> 	if (!obj)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	data = &amp;obj-&gt;ih_data;</div><div class='add'>+</div><div class='ctx'> 	if (data-&gt;inuse == 0)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -2242,7 +2667,7 @@ static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)</div><div class='ctx'> /* ih end */</div><div class='ctx'> </div><div class='ctx'> /* traversal all IPs except NBIO to query error counter */</div><div class='del'>-static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)</div><div class='add'>+static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev, enum ras_event_type type)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	struct ras_manager *obj;</div><div class='hunk'>@@ -2275,7 +2700,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)</div><div class='ctx'> 		     IP_VERSION(13, 0, 2)))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		amdgpu_ras_query_error_status(adev, &amp;info);</div><div class='add'>+		amdgpu_ras_query_error_status_with_event(adev, &amp;info, type);</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=</div><div class='ctx'> 			    IP_VERSION(11, 0, 2) &amp;&amp;</div><div class='hunk'>@@ -2334,54 +2759,121 @@ static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* recovery begin */</div><div class='del'>-</div><div class='del'>-/* return 0 on success.</div><div class='del'>- * caller need free bps.</div><div class='del'>- */</div><div class='ctx'> static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,</div><div class='del'>-		struct ras_badpage **bps, unsigned int *count)</div><div class='add'>+		struct ras_badpage *bps, uint32_t count, uint32_t start)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	struct ras_err_handler_data *data;</div><div class='del'>-	int i = 0;</div><div class='del'>-	int ret = 0, status;</div><div class='add'>+	int r = 0;</div><div class='add'>+	uint32_t i;</div><div class='ctx'> </div><div class='ctx'> 	if (!con || !con-&gt;eh_data || !bps || !count)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> 	data = con-&gt;eh_data;</div><div class='del'>-	if (!data || data-&gt;count == 0) {</div><div class='del'>-		*bps = NULL;</div><div class='del'>-		ret = -EINVAL;</div><div class='del'>-		goto out;</div><div class='add'>+	if (start &lt; data-&gt;count) {</div><div class='add'>+		for (i = start; i &lt; data-&gt;count; i++) {</div><div class='add'>+			if (!data-&gt;bps[i].ts)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			bps[r].bp = data-&gt;bps[i].retired_page;</div><div class='add'>+			r++;</div><div class='add'>+			if (r &gt;= count)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+	mutex_unlock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> </div><div class='del'>-	*bps = kmalloc(sizeof(struct ras_badpage) * data-&gt;count, GFP_KERNEL);</div><div class='del'>-	if (!*bps) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	for (; i &lt; data-&gt;count; i++) {</div><div class='del'>-		(*bps)[i] = (struct ras_badpage){</div><div class='del'>-			.bp = data-&gt;bps[i].retired_page,</div><div class='del'>-			.size = AMDGPU_GPU_PAGE_SIZE,</div><div class='del'>-			.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,</div><div class='del'>-		};</div><div class='del'>-		status = amdgpu_vram_mgr_query_page_status(&amp;adev-&gt;mman.vram_mgr,</div><div class='del'>-				data-&gt;bps[i].retired_page);</div><div class='del'>-		if (status == -EBUSY)</div><div class='del'>-			(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;</div><div class='del'>-		else if (status == -ENOENT)</div><div class='del'>-			(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;</div><div class='add'>+static int amdgpu_uniras_badpages_read(struct amdgpu_device *adev,</div><div class='add'>+		struct ras_badpage *bps, uint32_t count, uint32_t start)</div><div class='add'>+{</div><div class='add'>+	struct ras_cmd_bad_pages_info_req cmd_input;</div><div class='add'>+	struct ras_cmd_bad_pages_info_rsp *output;</div><div class='add'>+	uint32_t group, start_group, end_group;</div><div class='add'>+	uint32_t pos, pos_in_group;</div><div class='add'>+	int r = 0, i;</div><div class='add'>+</div><div class='add'>+	if (!bps || !count)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	output = kmalloc(sizeof(*output), GFP_KERNEL);</div><div class='add'>+	if (!output)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd_input, 0, sizeof(cmd_input));</div><div class='add'>+</div><div class='add'>+	start_group = start / RAS_CMD_MAX_BAD_PAGES_PER_GROUP;</div><div class='add'>+	end_group = (start + count + RAS_CMD_MAX_BAD_PAGES_PER_GROUP - 1) /</div><div class='add'>+				RAS_CMD_MAX_BAD_PAGES_PER_GROUP;</div><div class='add'>+</div><div class='add'>+	pos = start;</div><div class='add'>+	for (group = start_group; group &lt; end_group; group++) {</div><div class='add'>+		memset(output, 0, sizeof(*output));</div><div class='add'>+		cmd_input.group_index = group;</div><div class='add'>+		if (amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BAD_PAGES,</div><div class='add'>+			&amp;cmd_input, sizeof(cmd_input), output, sizeof(*output)))</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		if (pos &gt;= output-&gt;bp_total_cnt)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		pos_in_group = pos - group * RAS_CMD_MAX_BAD_PAGES_PER_GROUP;</div><div class='add'>+		for (i = pos_in_group; i &lt; output-&gt;bp_in_group; i++, pos++) {</div><div class='add'>+			if (!output-&gt;records[i].ts)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			bps[r].bp = output-&gt;records[i].retired_page;</div><div class='add'>+			r++;</div><div class='add'>+			if (r &gt;= count)</div><div class='add'>+				goto out;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	*count = data-&gt;count;</div><div class='ctx'> out:</div><div class='del'>-	mutex_unlock(&amp;con-&gt;recovery_lock);</div><div class='del'>-	return ret;</div><div class='add'>+	kfree(output);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_set_fed_all(struct amdgpu_device *adev,</div><div class='add'>+				   struct amdgpu_hive_info *hive, bool status)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='add'>+</div><div class='add'>+	if (hive) {</div><div class='add'>+		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head)</div><div class='add'>+			amdgpu_ras_set_fed(tmp_adev, status);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_ras_set_fed(adev, status);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_in_recovery(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	int hive_ras_recovery = 0;</div><div class='add'>+</div><div class='add'>+	if (hive) {</div><div class='add'>+		hive_ras_recovery = atomic_read(&amp;hive-&gt;ras_recovery);</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ras &amp;&amp; (atomic_read(&amp;ras-&gt;in_recovery) || hive_ras_recovery))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum ras_event_type amdgpu_ras_get_fatal_error_event(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_ras_intr_triggered())</div><div class='add'>+		return RAS_EVENT_TYPE_FATAL;</div><div class='add'>+	else</div><div class='add'>+		return RAS_EVENT_TYPE_POISON_CONSUMPTION;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_ras_do_recovery(struct work_struct *work)</div><div class='hunk'>@@ -2392,9 +2884,24 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)</div><div class='ctx'> 	struct amdgpu_device *adev = ras-&gt;adev;</div><div class='ctx'> 	struct list_head device_list, *device_list_handle =  NULL;</div><div class='ctx'> 	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	unsigned int error_query_mode;</div><div class='add'>+	enum ras_event_type type;</div><div class='ctx'> </div><div class='del'>-	if (hive)</div><div class='add'>+	if (hive) {</div><div class='ctx'> 		atomic_set(&amp;hive-&gt;ras_recovery, 1);</div><div class='add'>+</div><div class='add'>+		/* If any device which is part of the hive received RAS fatal</div><div class='add'>+		 * error interrupt, set fatal error status on all. This</div><div class='add'>+		 * condition will need a recovery, and flag will be cleared</div><div class='add'>+		 * as part of recovery.</div><div class='add'>+		 */</div><div class='add'>+		list_for_each_entry(remote_adev, &amp;hive-&gt;device_list,</div><div class='add'>+				    gmc.xgmi.head)</div><div class='add'>+			if (amdgpu_ras_get_fed_status(remote_adev)) {</div><div class='add'>+				amdgpu_ras_set_fed_all(adev, hive, true);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+	}</div><div class='ctx'> 	if (!ras-&gt;disable_ras_err_cnt_harvest) {</div><div class='ctx'> </div><div class='ctx'> 		/* Build list of devices to query RAS related errors */</div><div class='hunk'>@@ -2406,10 +2913,22 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)</div><div class='ctx'> 			device_list_handle = &amp;device_list;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (amdgpu_ras_get_error_query_mode(adev, &amp;error_query_mode)) {</div><div class='add'>+			if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY) {</div><div class='add'>+				/* wait 500ms to ensure pmfw polling mca bank info done */</div><div class='add'>+				msleep(500);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		type = amdgpu_ras_get_fatal_error_event(adev);</div><div class='ctx'> 		list_for_each_entry(remote_adev,</div><div class='ctx'> 				device_list_handle, gmc.xgmi.head) {</div><div class='del'>-			amdgpu_ras_query_err_status(remote_adev);</div><div class='del'>-			amdgpu_ras_log_on_err_counter(remote_adev);</div><div class='add'>+			if (amdgpu_uniras_enabled(remote_adev)) {</div><div class='add'>+				amdgpu_ras_mgr_update_ras_ecc(remote_adev);</div><div class='add'>+			} else {</div><div class='add'>+				amdgpu_ras_query_err_status(remote_adev);</div><div class='add'>+				amdgpu_ras_log_on_err_counter(remote_adev, type);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='hunk'>@@ -2420,6 +2939,8 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 		reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 		reset_context.reset_req_dev = adev;</div><div class='add'>+		reset_context.src = AMDGPU_RESET_SRC_RAS;</div><div class='add'>+		set_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='ctx'> 		/* Perform full reset in fatal error mode */</div><div class='ctx'> 		if (!amdgpu_ras_is_poison_mode_supported(ras-&gt;adev))</div><div class='hunk'>@@ -2439,18 +2960,6 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)</div><div class='ctx'> 				ras-&gt;gpu_reset_flags &amp;= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='ctx'> 				set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='del'>-				/* For any RAS error that needs a full reset to</div><div class='del'>-				 * recover, set the fatal error status</div><div class='del'>-				 */</div><div class='del'>-				if (hive) {</div><div class='del'>-					list_for_each_entry(remote_adev,</div><div class='del'>-							    &amp;hive-&gt;device_list,</div><div class='del'>-							    gmc.xgmi.head)</div><div class='del'>-						amdgpu_ras_set_fed(remote_adev,</div><div class='del'>-								   true);</div><div class='del'>-				} else {</div><div class='del'>-					amdgpu_ras_set_fed(adev, true);</div><div class='del'>-				}</div><div class='ctx'> 				psp_fatal_error_recovery_quirk(&amp;adev-&gt;psp);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2471,7 +2980,7 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,</div><div class='ctx'> 	unsigned int old_space = data-&gt;count + data-&gt;space_left;</div><div class='ctx'> 	unsigned int new_space = old_space + pages;</div><div class='ctx'> 	unsigned int align_space = ALIGN(new_space, 512);</div><div class='del'>-	void *bps = kmalloc(align_space * sizeof(*data-&gt;bps), GFP_KERNEL);</div><div class='add'>+	void *bps = kmalloc_array(align_space, sizeof(*data-&gt;bps), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!bps) {</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -2488,43 +2997,283 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* it deal with vram only. */</div><div class='del'>-int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,</div><div class='del'>-		struct eeprom_table_record *bps, int pages)</div><div class='add'>+static int amdgpu_ras_mca2pa_by_idx(struct amdgpu_device *adev,</div><div class='add'>+			struct eeprom_table_record *bps,</div><div class='add'>+			struct ras_err_data *err_data)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='del'>-	struct ras_err_handler_data *data;</div><div class='add'>+	struct ta_ras_query_address_input addr_in;</div><div class='add'>+	uint32_t socket = 0;</div><div class='ctx'> 	int ret = 0;</div><div class='del'>-	uint32_t i;</div><div class='ctx'> </div><div class='del'>-	if (!con || !con-&gt;eh_data || !bps || pages &lt;= 0)</div><div class='del'>-		return 0;</div><div class='add'>+	if (adev-&gt;smuio.funcs &amp;&amp; adev-&gt;smuio.funcs-&gt;get_socket_id)</div><div class='add'>+		socket = adev-&gt;smuio.funcs-&gt;get_socket_id(adev);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;con-&gt;recovery_lock);</div><div class='del'>-	data = con-&gt;eh_data;</div><div class='del'>-	if (!data)</div><div class='del'>-		goto out;</div><div class='add'>+	/* reinit err_data */</div><div class='add'>+	err_data-&gt;err_addr_cnt = 0;</div><div class='add'>+	err_data-&gt;err_addr_len = adev-&gt;umc.retire_unit;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; pages; i++) {</div><div class='add'>+	memset(&amp;addr_in, 0, sizeof(addr_in));</div><div class='add'>+	addr_in.ma.err_addr = bps-&gt;address;</div><div class='add'>+	addr_in.ma.socket_id = socket;</div><div class='add'>+	addr_in.ma.ch_inst = bps-&gt;mem_channel;</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev)) {</div><div class='add'>+		/* tell RAS TA the node instance is not used */</div><div class='add'>+		addr_in.ma.node_inst = TA_RAS_INV_NODE;</div><div class='add'>+	} else {</div><div class='add'>+		addr_in.ma.umc_inst = bps-&gt;mcumc_id;</div><div class='add'>+		addr_in.ma.node_inst = bps-&gt;cu;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;convert_ras_err_addr)</div><div class='add'>+		ret = adev-&gt;umc.ras-&gt;convert_ras_err_addr(adev, err_data,</div><div class='add'>+				&amp;addr_in, NULL, false);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_ras_mca2pa(struct amdgpu_device *adev,</div><div class='add'>+			struct eeprom_table_record *bps,</div><div class='add'>+			struct ras_err_data *err_data)</div><div class='add'>+{</div><div class='add'>+	struct ta_ras_query_address_input addr_in;</div><div class='add'>+	uint32_t die_id, socket = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;smuio.funcs &amp;&amp; adev-&gt;smuio.funcs-&gt;get_socket_id)</div><div class='add'>+		socket = adev-&gt;smuio.funcs-&gt;get_socket_id(adev);</div><div class='add'>+</div><div class='add'>+	/* although die id is gotten from PA in nps1 mode, the id is</div><div class='add'>+	 * fitable for any nps mode</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;get_die_id_from_pa)</div><div class='add'>+		die_id = adev-&gt;umc.ras-&gt;get_die_id_from_pa(adev, bps-&gt;address,</div><div class='add'>+					bps-&gt;retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT);</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* reinit err_data */</div><div class='add'>+	err_data-&gt;err_addr_cnt = 0;</div><div class='add'>+	err_data-&gt;err_addr_len = adev-&gt;umc.retire_unit;</div><div class='add'>+</div><div class='add'>+	memset(&amp;addr_in, 0, sizeof(addr_in));</div><div class='add'>+	addr_in.ma.err_addr = bps-&gt;address;</div><div class='add'>+	addr_in.ma.ch_inst = bps-&gt;mem_channel;</div><div class='add'>+	addr_in.ma.umc_inst = bps-&gt;mcumc_id;</div><div class='add'>+	addr_in.ma.node_inst = die_id;</div><div class='add'>+	addr_in.ma.socket_id = socket;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;convert_ras_err_addr)</div><div class='add'>+		return adev-&gt;umc.ras-&gt;convert_ras_err_addr(adev, err_data,</div><div class='add'>+					&amp;addr_in, NULL, false);</div><div class='add'>+	else</div><div class='add'>+		return  -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev,</div><div class='add'>+					struct eeprom_table_record *bps, int count)</div><div class='add'>+{</div><div class='add'>+	int j;</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_err_handler_data *data = con-&gt;eh_data;</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; count; j++) {</div><div class='ctx'> 		if (amdgpu_ras_check_bad_page_unlock(con,</div><div class='del'>-			bps[i].retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT))</div><div class='add'>+			bps[j].retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT)) {</div><div class='add'>+			data-&gt;count++;</div><div class='add'>+			data-&gt;space_left--;</div><div class='ctx'> 			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!data-&gt;space_left &amp;&amp;</div><div class='del'>-			amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {</div><div class='del'>-			ret = -ENOMEM;</div><div class='del'>-			goto out;</div><div class='add'>+		    amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		amdgpu_vram_mgr_reserve_range(&amp;adev-&gt;mman.vram_mgr,</div><div class='del'>-			bps[i].retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='del'>-			AMDGPU_GPU_PAGE_SIZE);</div><div class='add'>+		amdgpu_ras_reserve_page(adev, bps[j].retired_page);</div><div class='ctx'> </div><div class='del'>-		memcpy(&amp;data-&gt;bps[data-&gt;count], &amp;bps[i], sizeof(*data-&gt;bps));</div><div class='add'>+		memcpy(&amp;data-&gt;bps[data-&gt;count], &amp;(bps[j]),</div><div class='add'>+				sizeof(struct eeprom_table_record));</div><div class='ctx'> 		data-&gt;count++;</div><div class='ctx'> 		data-&gt;space_left--;</div><div class='add'>+		con-&gt;bad_page_num++;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev,</div><div class='add'>+				struct eeprom_table_record *bps, struct ras_err_data *err_data,</div><div class='add'>+				enum amdgpu_memory_partition nps)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	enum amdgpu_memory_partition save_nps;</div><div class='add'>+</div><div class='add'>+	save_nps = (bps[0].retired_page &gt;&gt; UMC_NPS_SHIFT) &amp; UMC_NPS_MASK;</div><div class='add'>+</div><div class='add'>+	/*old asics just have pa in eeprom*/</div><div class='add'>+	if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) &lt; 12) {</div><div class='add'>+		memcpy(err_data-&gt;err_addr, bps,</div><div class='add'>+			sizeof(struct eeprom_table_record) * adev-&gt;umc.retire_unit);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;umc.retire_unit; i++)</div><div class='add'>+		bps[i].retired_page &amp;= ~(UMC_NPS_MASK &lt;&lt; UMC_NPS_SHIFT);</div><div class='add'>+</div><div class='add'>+	if (save_nps) {</div><div class='add'>+		if (save_nps == nps) {</div><div class='add'>+			if (amdgpu_umc_pages_in_a_row(adev, err_data,</div><div class='add'>+					bps[0].retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;umc.retire_unit; i++) {</div><div class='add'>+				err_data-&gt;err_addr[i].address = bps[0].address;</div><div class='add'>+				err_data-&gt;err_addr[i].mem_channel = bps[0].mem_channel;</div><div class='add'>+				err_data-&gt;err_addr[i].bank = bps[0].bank;</div><div class='add'>+				err_data-&gt;err_addr[i].err_type = bps[0].err_type;</div><div class='add'>+				err_data-&gt;err_addr[i].mcumc_id = bps[0].mcumc_id;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			if (amdgpu_ras_mca2pa_by_idx(adev, &amp;bps[0], err_data))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (bps[0].address == 0) {</div><div class='add'>+			/* for specific old eeprom data, mca address is not stored,</div><div class='add'>+			 * calc it from pa</div><div class='add'>+			 */</div><div class='add'>+			if (amdgpu_umc_pa2mca(adev, bps[0].retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='add'>+				&amp;(bps[0].address), AMDGPU_NPS1_PARTITION_MODE))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_ras_mca2pa(adev, &amp;bps[0], err_data)) {</div><div class='add'>+			if (nps == AMDGPU_NPS1_PARTITION_MODE)</div><div class='add'>+				memcpy(err_data-&gt;err_addr, bps,</div><div class='add'>+					sizeof(struct eeprom_table_record) * adev-&gt;umc.retire_unit);</div><div class='add'>+			else</div><div class='add'>+				return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> out:</div><div class='add'>+	return __amdgpu_ras_restore_bad_pages(adev, err_data-&gt;err_addr, adev-&gt;umc.retire_unit);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev,</div><div class='add'>+				struct eeprom_table_record *bps, struct ras_err_data *err_data,</div><div class='add'>+				enum amdgpu_memory_partition nps)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	enum amdgpu_memory_partition save_nps;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev)) {</div><div class='add'>+		save_nps = (bps-&gt;retired_page &gt;&gt; UMC_NPS_SHIFT) &amp; UMC_NPS_MASK;</div><div class='add'>+		bps-&gt;retired_page &amp;= ~(UMC_NPS_MASK &lt;&lt; UMC_NPS_SHIFT);</div><div class='add'>+	} else {</div><div class='add'>+		/* if pmfw manages eeprom, save_nps is not stored on eeprom,</div><div class='add'>+		 * we should always convert mca address into physical address,</div><div class='add'>+		 * make save_nps different from nps</div><div class='add'>+		 */</div><div class='add'>+		save_nps = nps + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (save_nps == nps) {</div><div class='add'>+		if (amdgpu_umc_pages_in_a_row(adev, err_data,</div><div class='add'>+				bps-&gt;retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;umc.retire_unit; i++) {</div><div class='add'>+			err_data-&gt;err_addr[i].address = bps-&gt;address;</div><div class='add'>+			err_data-&gt;err_addr[i].mem_channel = bps-&gt;mem_channel;</div><div class='add'>+			err_data-&gt;err_addr[i].bank = bps-&gt;bank;</div><div class='add'>+			err_data-&gt;err_addr[i].err_type = bps-&gt;err_type;</div><div class='add'>+			err_data-&gt;err_addr[i].mcumc_id = bps-&gt;mcumc_id;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (bps-&gt;address) {</div><div class='add'>+			if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		} else {</div><div class='add'>+			/* for specific old eeprom data, mca address is not stored,</div><div class='add'>+			 * calc it from pa</div><div class='add'>+			 */</div><div class='add'>+			if (amdgpu_umc_pa2mca(adev, bps-&gt;retired_page &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='add'>+				&amp;(bps-&gt;address), AMDGPU_NPS1_PARTITION_MODE))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			if (amdgpu_ras_mca2pa(adev, bps, err_data))</div><div class='add'>+				return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return __amdgpu_ras_restore_bad_pages(adev, err_data-&gt;err_addr,</div><div class='add'>+									adev-&gt;umc.retire_unit);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* it deal with vram only. */</div><div class='add'>+int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,</div><div class='add'>+		struct eeprom_table_record *bps, int pages, bool from_rom)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_err_data err_data;</div><div class='add'>+	struct amdgpu_ras_eeprom_control *control =</div><div class='add'>+			&amp;adev-&gt;psp.ras_context.ras-&gt;eeprom_control;</div><div class='add'>+	enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	uint32_t i = 0;</div><div class='add'>+</div><div class='add'>+	if (!con || !con-&gt;eh_data || !bps || pages &lt;= 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (from_rom) {</div><div class='add'>+		err_data.err_addr =</div><div class='add'>+			kcalloc(adev-&gt;umc.retire_unit,</div><div class='add'>+				sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='add'>+		if (!err_data.err_addr) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "Failed to alloc UMC error address record in mca2pa conversion!\n");</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode)</div><div class='add'>+			nps = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;recovery_lock);</div><div class='add'>+</div><div class='add'>+	if (from_rom) {</div><div class='add'>+		/* there is no pa recs in V3, so skip pa recs processing */</div><div class='add'>+		if ((control-&gt;tbl_hdr.version &lt; RAS_TABLE_VER_V3) &amp;&amp;</div><div class='add'>+		    !amdgpu_ras_smu_eeprom_supported(adev)) {</div><div class='add'>+			for (i = 0; i &lt; pages; i++) {</div><div class='add'>+				if (control-&gt;ras_num_recs - i &gt;= adev-&gt;umc.retire_unit) {</div><div class='add'>+					if ((bps[i].address == bps[i + 1].address) &amp;&amp;</div><div class='add'>+						(bps[i].mem_channel == bps[i + 1].mem_channel)) {</div><div class='add'>+						/* deal with retire_unit records a time */</div><div class='add'>+						ret = __amdgpu_ras_convert_rec_array_from_rom(adev,</div><div class='add'>+										&amp;bps[i], &amp;err_data, nps);</div><div class='add'>+						if (ret)</div><div class='add'>+							con-&gt;bad_page_num -= adev-&gt;umc.retire_unit;</div><div class='add'>+						i += (adev-&gt;umc.retire_unit - 1);</div><div class='add'>+					} else {</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (; i &lt; pages; i++) {</div><div class='add'>+			ret = __amdgpu_ras_convert_rec_from_rom(adev,</div><div class='add'>+				&amp;bps[i], &amp;err_data, nps);</div><div class='add'>+			if (ret)</div><div class='add'>+				con-&gt;bad_page_num -= adev-&gt;umc.retire_unit;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		con-&gt;eh_data-&gt;count_saved = con-&gt;eh_data-&gt;count;</div><div class='add'>+	} else {</div><div class='add'>+		ret = __amdgpu_ras_restore_bad_pages(adev, bps, pages);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (from_rom)</div><div class='add'>+		kfree(err_data.err_addr);</div><div class='ctx'> 	mutex_unlock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -2541,7 +3290,7 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	struct ras_err_handler_data *data;</div><div class='ctx'> 	struct amdgpu_ras_eeprom_control *control;</div><div class='del'>-	int save_count;</div><div class='add'>+	int save_count, unit_num, i;</div><div class='ctx'> </div><div class='ctx'> 	if (!con || !con-&gt;eh_data) {</div><div class='ctx'> 		if (new_cnt)</div><div class='hunk'>@@ -2550,25 +3299,53 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!con-&gt;eeprom_control.is_eeprom_valid) {</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			"Failed to save EEPROM table data because of EEPROM data corruption!");</div><div class='add'>+		if (new_cnt)</div><div class='add'>+			*new_cnt = 0;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> 	control = &amp;con-&gt;eeprom_control;</div><div class='ctx'> 	data = con-&gt;eh_data;</div><div class='del'>-	save_count = data-&gt;count - control-&gt;ras_num_recs;</div><div class='add'>+	if (amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		unit_num = control-&gt;ras_num_recs -</div><div class='add'>+			control-&gt;ras_num_recs_old;</div><div class='add'>+	else</div><div class='add'>+		unit_num = data-&gt;count / adev-&gt;umc.retire_unit -</div><div class='add'>+			control-&gt;ras_num_recs;</div><div class='add'>+</div><div class='add'>+	save_count = con-&gt;bad_page_num - control-&gt;ras_num_bad_pages;</div><div class='ctx'> 	mutex_unlock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (new_cnt)</div><div class='del'>-		*new_cnt = save_count / adev-&gt;umc.retire_unit;</div><div class='add'>+		*new_cnt = unit_num;</div><div class='ctx'> </div><div class='ctx'> 	/* only new entries are saved */</div><div class='del'>-	if (save_count &gt; 0) {</div><div class='del'>-		if (amdgpu_ras_eeprom_append(control,</div><div class='del'>-					     &amp;data-&gt;bps[control-&gt;ras_num_recs],</div><div class='del'>-					     save_count)) {</div><div class='del'>-			dev_err(adev-&gt;dev, "Failed to save EEPROM table data!");</div><div class='del'>-			return -EIO;</div><div class='add'>+	if (unit_num &amp;&amp; save_count) {</div><div class='add'>+		/*old asics only save pa to eeprom like before*/</div><div class='add'>+		if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) &lt; 12) {</div><div class='add'>+			if (amdgpu_ras_eeprom_append(control,</div><div class='add'>+					&amp;data-&gt;bps[data-&gt;count_saved], unit_num)) {</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to save EEPROM table data!");</div><div class='add'>+				return -EIO;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			for (i = 0; i &lt; unit_num; i++) {</div><div class='add'>+				if (amdgpu_ras_eeprom_append(control,</div><div class='add'>+						&amp;data-&gt;bps[data-&gt;count_saved +</div><div class='add'>+						i * adev-&gt;umc.retire_unit], 1)) {</div><div class='add'>+					dev_err(adev-&gt;dev, "Failed to save EEPROM table data!");</div><div class='add'>+					return -EIO;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dev_info(adev-&gt;dev, "Saved %d pages to EEPROM table.\n", save_count);</div><div class='add'>+		data-&gt;count_saved = data-&gt;count;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2583,7 +3360,7 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)</div><div class='ctx'> 	struct amdgpu_ras_eeprom_control *control =</div><div class='ctx'> 		&amp;adev-&gt;psp.ras_context.ras-&gt;eeprom_control;</div><div class='ctx'> 	struct eeprom_table_record *bps;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret, i = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* no bad page record, skip eeprom access */</div><div class='ctx'> 	if (control-&gt;ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)</div><div class='hunk'>@@ -2594,27 +3371,72 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_ras_eeprom_read(control, bps, control-&gt;ras_num_recs);</div><div class='del'>-	if (ret)</div><div class='add'>+	if (ret) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to load EEPROM table records!");</div><div class='del'>-	else</div><div class='del'>-		ret = amdgpu_ras_add_bad_pages(adev, bps, control-&gt;ras_num_recs);</div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;convert_ras_err_addr) {</div><div class='add'>+			/*In V3, there is no pa recs, and some cases(when address==0) may be parsed</div><div class='add'>+			as pa recs, so add verion check to avoid it.</div><div class='add'>+			*/</div><div class='add'>+			if ((control-&gt;tbl_hdr.version &lt; RAS_TABLE_VER_V3) &amp;&amp;</div><div class='add'>+			    !amdgpu_ras_smu_eeprom_supported(adev)) {</div><div class='add'>+				for (i = 0; i &lt; control-&gt;ras_num_recs; i++) {</div><div class='add'>+					if ((control-&gt;ras_num_recs - i) &gt;= adev-&gt;umc.retire_unit) {</div><div class='add'>+						if ((bps[i].address == bps[i + 1].address) &amp;&amp;</div><div class='add'>+							(bps[i].mem_channel == bps[i + 1].mem_channel)) {</div><div class='add'>+							control-&gt;ras_num_pa_recs += adev-&gt;umc.retire_unit;</div><div class='add'>+							i += (adev-&gt;umc.retire_unit - 1);</div><div class='add'>+						} else {</div><div class='add'>+							control-&gt;ras_num_mca_recs +=</div><div class='add'>+										(control-&gt;ras_num_recs - i);</div><div class='add'>+							break;</div><div class='add'>+						}</div><div class='add'>+					} else {</div><div class='add'>+						control-&gt;ras_num_mca_recs += (control-&gt;ras_num_recs - i);</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				control-&gt;ras_num_mca_recs = control-&gt;ras_num_recs;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='add'>+		ret = amdgpu_ras_add_bad_pages(adev, bps, control-&gt;ras_num_recs, true);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_ras_eeprom_check(control);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		/* HW not usable */</div><div class='add'>+		if (amdgpu_ras_is_rma(adev))</div><div class='add'>+			ret = -EHWPOISON;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='ctx'> 	kfree(bps);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,</div><div class='add'>+static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,</div><div class='ctx'> 				uint64_t addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_handler_data *data = con-&gt;eh_data;</div><div class='add'>+	struct amdgpu_device *adev = con-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if ((addr &gt;= adev-&gt;gmc.mc_vram_size &amp;&amp;</div><div class='add'>+	    adev-&gt;gmc.mc_vram_size) ||</div><div class='add'>+	    (addr &gt;= RAS_UMC_INJECT_ADDR_LIMIT))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	addr &gt;&gt;= AMDGPU_GPU_PAGE_SHIFT;</div><div class='ctx'> 	for (i = 0; i &lt; data-&gt;count; i++)</div><div class='ctx'> 		if (addr == data-&gt;bps[i].retired_page)</div><div class='del'>-			return true;</div><div class='add'>+			return 1;</div><div class='ctx'> </div><div class='del'>-	return false;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -2622,11 +3444,11 @@ static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,</div><div class='ctx'>  *</div><div class='ctx'>  * Note: this check is only for umc block</div><div class='ctx'>  */</div><div class='del'>-static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,</div><div class='add'>+static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev,</div><div class='ctx'> 				uint64_t addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='del'>-	bool ret = false;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!con || !con-&gt;eh_data)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -2643,41 +3465,245 @@ static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Justification of value bad_page_cnt_threshold in ras structure</div><div class='del'>-	 *</div><div class='del'>-	 * Generally, 0 &lt;= amdgpu_bad_page_threshold &lt;= max record length</div><div class='del'>-	 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two</div><div class='del'>-	 * scenarios accordingly.</div><div class='del'>-	 *</div><div class='del'>-	 * Bad page retirement enablement:</div><div class='del'>-	 *    - If amdgpu_bad_page_threshold = -2,</div><div class='del'>-	 *      bad_page_cnt_threshold = typical value by formula.</div><div class='del'>-	 *</div><div class='del'>-	 *    - When the value from user is 0 &lt; amdgpu_bad_page_threshold &lt;</div><div class='del'>-	 *      max record length in eeprom, use it directly.</div><div class='del'>-	 *</div><div class='del'>-	 * Bad page retirement disablement:</div><div class='del'>-	 *    - If amdgpu_bad_page_threshold = 0, bad page retirement</div><div class='del'>-	 *      functionality is disabled, and bad_page_cnt_threshold will</div><div class='del'>-	 *      take no effect.</div><div class='add'>+	 * amdgpu_bad_page_threshold is used to config</div><div class='add'>+	 * the threshold for the number of bad pages.</div><div class='add'>+	 * -1:  Threshold is set to default value</div><div class='add'>+	 *      Driver will issue a warning message when threshold is reached</div><div class='add'>+	 *      and continue runtime services.</div><div class='add'>+	 * 0:   Disable bad page retirement</div><div class='add'>+	 *      Driver will not retire bad pages</div><div class='add'>+	 *      which is intended for debugging purpose.</div><div class='add'>+	 * -2:  Threshold is determined by a formula</div><div class='add'>+	 *      that assumes 1 bad page per 100M of local memory.</div><div class='add'>+	 *      Driver will continue runtime services when threhold is reached.</div><div class='add'>+	 * 0 &lt; threshold &lt; max number of bad page records in EEPROM,</div><div class='add'>+	 *      A user-defined threshold is set</div><div class='add'>+	 *      Driver will halt runtime services when this custom threshold is reached.</div><div class='ctx'> 	 */</div><div class='del'>-</div><div class='del'>-	if (amdgpu_bad_page_threshold &lt; 0) {</div><div class='add'>+	if (amdgpu_bad_page_threshold == -2) {</div><div class='ctx'> 		u64 val = adev-&gt;gmc.mc_vram_size;</div><div class='ctx'> </div><div class='ctx'> 		do_div(val, RAS_BAD_PAGE_COVER);</div><div class='ctx'> 		con-&gt;bad_page_cnt_threshold = min(lower_32_bits(val),</div><div class='ctx'> 						  max_count);</div><div class='add'>+	} else if (amdgpu_bad_page_threshold == -1) {</div><div class='add'>+		con-&gt;bad_page_cnt_threshold = ((con-&gt;reserved_pages_in_bytes) &gt;&gt; 21) &lt;&lt; 4;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		con-&gt;bad_page_cnt_threshold = min_t(int, max_count,</div><div class='ctx'> 						    amdgpu_bad_page_threshold);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,</div><div class='add'>+		enum amdgpu_ras_block block, uint16_t pasid,</div><div class='add'>+		pasid_notify pasid_fn, void *data, uint32_t reset)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	struct ras_poison_msg poison_msg;</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	memset(&amp;poison_msg, 0, sizeof(poison_msg));</div><div class='add'>+	poison_msg.block = block;</div><div class='add'>+	poison_msg.pasid = pasid;</div><div class='add'>+	poison_msg.reset = reset;</div><div class='add'>+	poison_msg.pasid_fn = pasid_fn;</div><div class='add'>+	poison_msg.data = data;</div><div class='add'>+</div><div class='add'>+	ret = kfifo_put(&amp;con-&gt;poison_fifo, poison_msg);</div><div class='add'>+	if (!ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Poison message fifo is full!\n");</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev,</div><div class='add'>+		struct ras_poison_msg *poison_msg)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	return kfifo_get(&amp;con-&gt;poison_fifo, poison_msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log)</div><div class='add'>+{</div><div class='add'>+	mutex_init(&amp;ecc_log-&gt;lock);</div><div class='add'>+</div><div class='add'>+	INIT_RADIX_TREE(&amp;ecc_log-&gt;de_page_tree, GFP_KERNEL);</div><div class='add'>+	ecc_log-&gt;de_queried_count = 0;</div><div class='add'>+	ecc_log-&gt;consumption_q_count = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log)</div><div class='add'>+{</div><div class='add'>+	struct radix_tree_iter iter;</div><div class='add'>+	void __rcu **slot;</div><div class='add'>+	struct ras_ecc_err *ecc_err;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ecc_log-&gt;lock);</div><div class='add'>+	radix_tree_for_each_slot(slot, &amp;ecc_log-&gt;de_page_tree, &amp;iter, 0) {</div><div class='add'>+		ecc_err = radix_tree_deref_slot(slot);</div><div class='add'>+		kfree(ecc_err-&gt;err_pages.pfn);</div><div class='add'>+		kfree(ecc_err);</div><div class='add'>+		radix_tree_iter_delete(&amp;ecc_log-&gt;de_page_tree, &amp;iter, slot);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;ecc_log-&gt;lock);</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;ecc_log-&gt;lock);</div><div class='add'>+	ecc_log-&gt;de_queried_count = 0;</div><div class='add'>+	ecc_log-&gt;consumption_q_count = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_ras_schedule_retirement_dwork(struct amdgpu_ras *con,</div><div class='add'>+				uint32_t delayed_ms)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;umc_ecc_log.lock);</div><div class='add'>+	ret = radix_tree_tagged(&amp;con-&gt;umc_ecc_log.de_page_tree,</div><div class='add'>+			UMC_ECC_NEW_DETECTED_TAG);</div><div class='add'>+	mutex_unlock(&amp;con-&gt;umc_ecc_log.lock);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		schedule_delayed_work(&amp;con-&gt;page_retirement_dwork,</div><div class='add'>+			msecs_to_jiffies(delayed_ms));</div><div class='add'>+</div><div class='add'>+	return ret ? true : false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_do_page_retirement(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,</div><div class='add'>+					      page_retirement_dwork.work);</div><div class='add'>+	struct amdgpu_device *adev = con-&gt;adev;</div><div class='add'>+	struct ras_err_data err_data;</div><div class='add'>+</div><div class='add'>+	/* If gpu reset is ongoing, delay retiring the bad pages */</div><div class='add'>+	if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) {</div><div class='add'>+		amdgpu_ras_schedule_retirement_dwork(con,</div><div class='add'>+				AMDGPU_RAS_RETIRE_PAGE_INTERVAL * 3);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_error_data_init(&amp;err_data);</div><div class='add'>+</div><div class='add'>+	amdgpu_umc_handle_bad_pages(adev, &amp;err_data);</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_error_data_fini(&amp;err_data);</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_schedule_retirement_dwork(con,</div><div class='add'>+			AMDGPU_RAS_RETIRE_PAGE_INTERVAL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,</div><div class='add'>+				uint32_t poison_creation_count)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	struct ras_ecc_log_info *ecc_log;</div><div class='add'>+	struct ras_query_if info;</div><div class='add'>+	u32 timeout = MAX_UMC_POISON_POLLING_TIME_ASYNC;</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	u64 de_queried_count;</div><div class='add'>+	u64 consumption_q_count;</div><div class='add'>+	enum ras_event_type type = RAS_EVENT_TYPE_POISON_CREATION;</div><div class='add'>+</div><div class='add'>+	memset(&amp;info, 0, sizeof(info));</div><div class='add'>+	info.head.block = AMDGPU_RAS_BLOCK__UMC;</div><div class='add'>+</div><div class='add'>+	ecc_log = &amp;ras-&gt;umc_ecc_log;</div><div class='add'>+	ecc_log-&gt;de_queried_count = 0;</div><div class='add'>+	ecc_log-&gt;consumption_q_count = 0;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = amdgpu_ras_query_error_status_with_event(adev, &amp;info, type);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		de_queried_count = ecc_log-&gt;de_queried_count;</div><div class='add'>+		consumption_q_count = ecc_log-&gt;consumption_q_count;</div><div class='add'>+</div><div class='add'>+		if (de_queried_count &amp;&amp; consumption_q_count)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		msleep(100);</div><div class='add'>+	} while (--timeout);</div><div class='add'>+</div><div class='add'>+	if (de_queried_count)</div><div class='add'>+		schedule_delayed_work(&amp;ras-&gt;page_retirement_dwork, 0);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_rma(adev) &amp;&amp; atomic_cmpxchg(&amp;ras-&gt;rma_in_recovery, 0, 1) == 0)</div><div class='add'>+		amdgpu_ras_reset_gpu(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_clear_poison_fifo(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_poison_msg msg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = kfifo_get(&amp;con-&gt;poison_fifo, &amp;msg);</div><div class='add'>+	} while (ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='add'>+			uint32_t msg_count, uint32_t *gpu_reset)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	uint32_t reset_flags = 0, reset = 0;</div><div class='add'>+	struct ras_poison_msg msg;</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	kgd2kfd_set_sram_ecc_flag(adev-&gt;kfd.dev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; msg_count; i++) {</div><div class='add'>+		ret = amdgpu_ras_get_poison_req(adev, &amp;msg);</div><div class='add'>+		if (!ret)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (msg.pasid_fn)</div><div class='add'>+			msg.pasid_fn(adev, msg.pasid, msg.data);</div><div class='add'>+</div><div class='add'>+		reset_flags |= msg.reset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Try to ensure poison creation handler is completed first</div><div class='add'>+	 * to set rma if bad page exceed threshold.</div><div class='add'>+	 */</div><div class='add'>+	flush_delayed_work(&amp;con-&gt;page_retirement_dwork);</div><div class='add'>+</div><div class='add'>+	/* for RMA, amdgpu_ras_poison_creation_handler will trigger gpu reset */</div><div class='add'>+	if (reset_flags &amp;&amp; !amdgpu_ras_is_rma(adev)) {</div><div class='add'>+		if (reset_flags &amp; AMDGPU_RAS_GPU_RESET_MODE1_RESET)</div><div class='add'>+			reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='add'>+		else if (reset_flags &amp; AMDGPU_RAS_GPU_RESET_MODE2_RESET)</div><div class='add'>+			reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		else</div><div class='add'>+			reset = reset_flags;</div><div class='add'>+</div><div class='add'>+		con-&gt;gpu_reset_flags |= reset;</div><div class='add'>+		amdgpu_ras_reset_gpu(adev);</div><div class='add'>+</div><div class='add'>+		*gpu_reset = reset;</div><div class='add'>+</div><div class='add'>+		/* Wait for gpu recovery to complete */</div><div class='add'>+		flush_work(&amp;con-&gt;recovery_work);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_ras_page_retirement_thread(void *param)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)param;</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	uint32_t poison_creation_count, msg_count;</div><div class='add'>+	uint32_t gpu_reset;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	while (!kthread_should_stop()) {</div><div class='ctx'> </div><div class='hunk'>@@ -2688,24 +3714,130 @@ static int amdgpu_ras_page_retirement_thread(void *param)</div><div class='ctx'> 		if (kthread_should_stop())</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='del'>-		dev_info(adev-&gt;dev, "Start processing page retirement. request:%d\n",</div><div class='del'>-			atomic_read(&amp;con-&gt;page_retirement_req_cnt));</div><div class='add'>+		mutex_lock(&amp;con-&gt;poison_lock);</div><div class='add'>+		gpu_reset = 0;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			poison_creation_count = atomic_read(&amp;con-&gt;poison_creation_count);</div><div class='add'>+			ret = amdgpu_ras_poison_creation_handler(adev, poison_creation_count);</div><div class='add'>+			if (ret == -EIO)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			if (poison_creation_count) {</div><div class='add'>+				atomic_sub(poison_creation_count, &amp;con-&gt;poison_creation_count);</div><div class='add'>+				atomic_sub(poison_creation_count, &amp;con-&gt;page_retirement_req_cnt);</div><div class='add'>+			}</div><div class='add'>+		} while (atomic_read(&amp;con-&gt;poison_creation_count) &amp;&amp;</div><div class='add'>+			!atomic_read(&amp;con-&gt;poison_consumption_count));</div><div class='add'>+</div><div class='add'>+		if (ret != -EIO) {</div><div class='add'>+			msg_count = kfifo_len(&amp;con-&gt;poison_fifo);</div><div class='add'>+			if (msg_count) {</div><div class='add'>+				ret = amdgpu_ras_poison_consumption_handler(adev,</div><div class='add'>+						msg_count, &amp;gpu_reset);</div><div class='add'>+				if ((ret != -EIO) &amp;&amp;</div><div class='add'>+				    (gpu_reset != AMDGPU_RAS_GPU_RESET_MODE1_RESET))</div><div class='add'>+					atomic_sub(msg_count, &amp;con-&gt;page_retirement_req_cnt);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((ret == -EIO) || (gpu_reset == AMDGPU_RAS_GPU_RESET_MODE1_RESET)) {</div><div class='add'>+			/* gpu mode-1 reset is ongoing or just completed ras mode-1 reset */</div><div class='add'>+			/* Clear poison creation request */</div><div class='add'>+			atomic_set(&amp;con-&gt;poison_creation_count, 0);</div><div class='add'>+			atomic_set(&amp;con-&gt;poison_consumption_count, 0);</div><div class='add'>+</div><div class='add'>+			/* Clear poison fifo */</div><div class='add'>+			amdgpu_ras_clear_poison_fifo(adev);</div><div class='add'>+</div><div class='add'>+			/* Clear all poison requests */</div><div class='add'>+			atomic_set(&amp;con-&gt;page_retirement_req_cnt, 0);</div><div class='add'>+</div><div class='add'>+			if (ret == -EIO) {</div><div class='add'>+				/* Wait for mode-1 reset to complete */</div><div class='add'>+				down_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+				up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Wake up work to save bad pages to eeprom */</div><div class='add'>+			schedule_delayed_work(&amp;con-&gt;page_retirement_dwork, 0);</div><div class='add'>+		} else if (gpu_reset) {</div><div class='add'>+			/* gpu just completed mode-2 reset or other reset */</div><div class='add'>+			/* Clear poison consumption messages cached in fifo */</div><div class='add'>+			msg_count = kfifo_len(&amp;con-&gt;poison_fifo);</div><div class='add'>+			if (msg_count) {</div><div class='add'>+				amdgpu_ras_clear_poison_fifo(adev);</div><div class='add'>+				atomic_sub(msg_count, &amp;con-&gt;page_retirement_req_cnt);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			atomic_set(&amp;con-&gt;poison_consumption_count, 0);</div><div class='add'>+</div><div class='add'>+			/* Wake up work to save bad pages to eeprom */</div><div class='add'>+			schedule_delayed_work(&amp;con-&gt;page_retirement_dwork, 0);</div><div class='add'>+		}</div><div class='add'>+		mutex_unlock(&amp;con-&gt;poison_lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_ras_eeprom_control *control;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!con || amdgpu_sriov_vf(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	control = &amp;con-&gt;eeprom_control;</div><div class='add'>+	con-&gt;ras_smu_drv = amdgpu_dpm_get_ras_smu_driver(adev);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_ras_eeprom_init(control);</div><div class='add'>+	control-&gt;is_eeprom_valid = !ret;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;umc.ras || !adev-&gt;umc.ras-&gt;convert_ras_err_addr)</div><div class='add'>+		control-&gt;ras_num_pa_recs = control-&gt;ras_num_recs;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;umc.ras &amp;&amp;</div><div class='add'>+	    adev-&gt;umc.ras-&gt;get_retire_flip_bits)</div><div class='add'>+		adev-&gt;umc.ras-&gt;get_retire_flip_bits(adev);</div><div class='add'>+</div><div class='add'>+	if (control-&gt;ras_num_recs &amp;&amp; control-&gt;is_eeprom_valid) {</div><div class='add'>+		ret = amdgpu_ras_load_bad_pages(adev);</div><div class='add'>+		if (ret) {</div><div class='add'>+			control-&gt;is_eeprom_valid = false;</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		amdgpu_dpm_send_hbm_bad_pages_num(</div><div class='add'>+			adev, control-&gt;ras_num_bad_pages);</div><div class='ctx'> </div><div class='del'>-		atomic_dec(&amp;con-&gt;page_retirement_req_cnt);</div><div class='add'>+		if (con-&gt;update_channel_flag == true) {</div><div class='add'>+			amdgpu_dpm_send_hbm_bad_channel_flag(</div><div class='add'>+				adev, control-&gt;bad_channel_bitmap);</div><div class='add'>+			con-&gt;update_channel_flag = false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		amdgpu_umc_bad_page_polling_timeout(adev,</div><div class='del'>-				false, MAX_UMC_POISON_POLLING_TIME_ASYNC);</div><div class='add'>+		/* The format action is only applied to new ASICs */</div><div class='add'>+		if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) &gt;= 12 &amp;&amp;</div><div class='add'>+		    control-&gt;tbl_hdr.version &lt; RAS_TABLE_VER_V3)</div><div class='add'>+			if (!amdgpu_ras_eeprom_reset_table(control))</div><div class='add'>+				if (amdgpu_ras_save_bad_pages(adev, NULL))</div><div class='add'>+					dev_warn(adev-&gt;dev, "Failed to format RAS EEPROM data in V3 version!\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_ras_recovery_init(struct amdgpu_device *adev)</div><div class='add'>+int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	struct ras_err_handler_data **data;</div><div class='ctx'> 	u32  max_eeprom_records_count = 0;</div><div class='del'>-	bool exc_err_limit = false;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!con || amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -2729,43 +3861,28 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;con-&gt;recovery_lock);</div><div class='add'>+	mutex_init(&amp;con-&gt;poison_lock);</div><div class='ctx'> 	INIT_WORK(&amp;con-&gt;recovery_work, amdgpu_ras_do_recovery);</div><div class='ctx'> 	atomic_set(&amp;con-&gt;in_recovery, 0);</div><div class='add'>+	atomic_set(&amp;con-&gt;rma_in_recovery, 0);</div><div class='ctx'> 	con-&gt;eeprom_control.bad_channel_bitmap = 0;</div><div class='ctx'> </div><div class='ctx'> 	max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&amp;con-&gt;eeprom_control);</div><div class='ctx'> 	amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);</div><div class='ctx'> </div><div class='del'>-	/* Todo: During test the SMU might fail to read the eeprom through I2C</div><div class='del'>-	 * when the GPU is pending on XGMI reset during probe time</div><div class='del'>-	 * (Mostly after second bus reset), skip it now</div><div class='del'>-	 */</div><div class='del'>-	if (adev-&gt;gmc.xgmi.pending_reset)</div><div class='del'>-		return 0;</div><div class='del'>-	ret = amdgpu_ras_eeprom_init(&amp;con-&gt;eeprom_control, &amp;exc_err_limit);</div><div class='del'>-	/*</div><div class='del'>-	 * This calling fails when exc_err_limit is true or</div><div class='del'>-	 * ret != 0.</div><div class='del'>-	 */</div><div class='del'>-	if (exc_err_limit || ret)</div><div class='del'>-		goto free;</div><div class='del'>-</div><div class='del'>-	if (con-&gt;eeprom_control.ras_num_recs) {</div><div class='del'>-		ret = amdgpu_ras_load_bad_pages(adev);</div><div class='add'>+	if (init_bp_info) {</div><div class='add'>+		ret = amdgpu_ras_init_badpage_info(adev);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto free;</div><div class='del'>-</div><div class='del'>-		amdgpu_dpm_send_hbm_bad_pages_num(adev, con-&gt;eeprom_control.ras_num_recs);</div><div class='del'>-</div><div class='del'>-		if (con-&gt;update_channel_flag == true) {</div><div class='del'>-			amdgpu_dpm_send_hbm_bad_channel_flag(adev, con-&gt;eeprom_control.bad_channel_bitmap);</div><div class='del'>-			con-&gt;update_channel_flag = false;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	mutex_init(&amp;con-&gt;page_rsv_lock);</div><div class='add'>+	INIT_KFIFO(con-&gt;poison_fifo);</div><div class='ctx'> 	mutex_init(&amp;con-&gt;page_retirement_lock);</div><div class='ctx'> 	init_waitqueue_head(&amp;con-&gt;page_retirement_wq);</div><div class='ctx'> 	atomic_set(&amp;con-&gt;page_retirement_req_cnt, 0);</div><div class='add'>+	atomic_set(&amp;con-&gt;poison_creation_count, 0);</div><div class='add'>+	atomic_set(&amp;con-&gt;poison_consumption_count, 0);</div><div class='ctx'> 	con-&gt;page_retirement_thread =</div><div class='ctx'> 		kthread_run(amdgpu_ras_page_retirement_thread, adev, "umc_page_retirement");</div><div class='ctx'> 	if (IS_ERR(con-&gt;page_retirement_thread)) {</div><div class='hunk'>@@ -2773,6 +3890,8 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Failed to create umc_page_retirement thread!!!\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	INIT_DELAYED_WORK(&amp;con-&gt;page_retirement_dwork, amdgpu_ras_do_page_retirement);</div><div class='add'>+	amdgpu_ras_ecc_log_init(&amp;con-&gt;umc_ecc_log);</div><div class='ctx'> #ifdef CONFIG_X86_MCE_AMD</div><div class='ctx'> 	if ((adev-&gt;asic_type == CHIP_ALDEBARAN) &amp;&amp;</div><div class='ctx'> 	    (adev-&gt;gmc.xgmi.connected_to_cpu))</div><div class='hunk'>@@ -2791,7 +3910,7 @@ out:</div><div class='ctx'> 	 * Except error threshold exceeding case, other failure cases in this</div><div class='ctx'> 	 * function would not fail amdgpu driver init.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!exc_err_limit)</div><div class='add'>+	if (!amdgpu_ras_is_rma(adev))</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	else</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -2803,24 +3922,43 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	struct ras_err_handler_data *data = con-&gt;eh_data;</div><div class='add'>+	int max_flush_timeout = MAX_FLUSH_RETIRE_DWORK_TIMES;</div><div class='add'>+	bool ret;</div><div class='ctx'> </div><div class='ctx'> 	/* recovery_init failed to init it, fini is useless */</div><div class='ctx'> 	if (!data)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	/* Save all cached bad pages to eeprom */</div><div class='add'>+	do {</div><div class='add'>+		flush_delayed_work(&amp;con-&gt;page_retirement_dwork);</div><div class='add'>+		ret = amdgpu_ras_schedule_retirement_dwork(con, 0);</div><div class='add'>+	} while (ret &amp;&amp; max_flush_timeout--);</div><div class='add'>+</div><div class='ctx'> 	if (con-&gt;page_retirement_thread)</div><div class='ctx'> 		kthread_stop(con-&gt;page_retirement_thread);</div><div class='ctx'> </div><div class='ctx'> 	atomic_set(&amp;con-&gt;page_retirement_req_cnt, 0);</div><div class='add'>+	atomic_set(&amp;con-&gt;poison_creation_count, 0);</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;con-&gt;page_rsv_lock);</div><div class='ctx'> </div><div class='ctx'> 	cancel_work_sync(&amp;con-&gt;recovery_work);</div><div class='ctx'> </div><div class='add'>+	cancel_delayed_work_sync(&amp;con-&gt;page_retirement_dwork);</div><div class='add'>+</div><div class='add'>+	amdgpu_ras_ecc_log_fini(&amp;con-&gt;umc_ecc_log);</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> 	con-&gt;eh_data = NULL;</div><div class='ctx'> 	kfree(data-&gt;bps);</div><div class='ctx'> 	kfree(data);</div><div class='ctx'> 	mutex_unlock(&amp;con-&gt;recovery_lock);</div><div class='ctx'> </div><div class='add'>+	amdgpu_ras_critical_region_init(adev);</div><div class='add'>+#ifdef CONFIG_X86_MCE_AMD</div><div class='add'>+	amdgpu_unregister_bad_pages_mca_notifier(adev);</div><div class='add'>+#endif</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> /* recovery end */</div><div class='hunk'>@@ -2831,6 +3969,8 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)</div><div class='ctx'> 		switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {</div><div class='ctx'> 		case IP_VERSION(13, 0, 2):</div><div class='ctx'> 		case IP_VERSION(13, 0, 6):</div><div class='add'>+		case IP_VERSION(13, 0, 12):</div><div class='add'>+		case IP_VERSION(13, 0, 14):</div><div class='ctx'> 			return true;</div><div class='ctx'> 		default:</div><div class='ctx'> 			return false;</div><div class='hunk'>@@ -2842,6 +3982,9 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)</div><div class='ctx'> 		case IP_VERSION(13, 0, 0):</div><div class='ctx'> 		case IP_VERSION(13, 0, 6):</div><div class='ctx'> 		case IP_VERSION(13, 0, 10):</div><div class='add'>+		case IP_VERSION(13, 0, 12):</div><div class='add'>+		case IP_VERSION(13, 0, 14):</div><div class='add'>+		case IP_VERSION(14, 0, 3):</div><div class='ctx'> 			return true;</div><div class='ctx'> 		default:</div><div class='ctx'> 			return false;</div><div class='hunk'>@@ -2903,7 +4046,8 @@ static void amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) ||</div><div class='ctx'> 		    amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) ||</div><div class='del'>-		    amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3))</div><div class='add'>+		    amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3) ||</div><div class='add'>+		    amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(5, 0, 1))</div><div class='ctx'> 			adev-&gt;ras_hw_enabled |= (1 &lt;&lt; AMDGPU_RAS_BLOCK__VCN |</div><div class='ctx'> 						 1 &lt;&lt; AMDGPU_RAS_BLOCK__JPEG);</div><div class='ctx'> 		else</div><div class='hunk'>@@ -2971,6 +4115,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!amdgpu_ras_asic_supported(adev))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		if (amdgpu_virt_get_ras_capability(adev))</div><div class='add'>+			goto init_ras_enabled_flag;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* query ras capability from psp */</div><div class='ctx'> 	if (amdgpu_psp_get_ras_capability(&amp;adev-&gt;psp))</div><div class='ctx'> 		goto init_ras_enabled_flag;</div><div class='hunk'>@@ -2999,8 +4148,18 @@ init_ras_enabled_flag:</div><div class='ctx'> 	adev-&gt;ras_enabled = amdgpu_ras_enable == 0 ? 0 :</div><div class='ctx'> 		adev-&gt;ras_hw_enabled &amp; amdgpu_ras_mask;</div><div class='ctx'> </div><div class='del'>-	/* aca is disabled by default */</div><div class='del'>-	adev-&gt;aca.is_enabled = false;</div><div class='add'>+	/* aca is disabled by default except for psp v13_0_6/v13_0_12/v13_0_14 */</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		adev-&gt;aca.is_enabled =</div><div class='add'>+			(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+			amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+			amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* bad page feature is not applicable to specific app platform */</div><div class='add'>+	if (adev-&gt;gmc.is_app_apu &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(12, 0, 0))</div><div class='add'>+		amdgpu_bad_page_threshold = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_ras_counte_dw(struct work_struct *work)</div><div class='hunk'>@@ -3023,7 +4182,6 @@ static void amdgpu_ras_counte_dw(struct work_struct *work)</div><div class='ctx'> 		atomic_set(&amp;con-&gt;ras_ue_count, ue_count);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> Out:</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> }</div><div class='hunk'>@@ -3036,6 +4194,63 @@ static int amdgpu_get_ras_schema(struct amdgpu_device *adev)</div><div class='ctx'> 			AMDGPU_RAS_ERROR__PARITY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ras_event_mgr_init(struct ras_event_manager *mgr)</div><div class='add'>+{</div><div class='add'>+	struct ras_event_state *event_state;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	memset(mgr, 0, sizeof(*mgr));</div><div class='add'>+	atomic64_set(&amp;mgr-&gt;seqno, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(mgr-&gt;event_state); i++) {</div><div class='add'>+		event_state = &amp;mgr-&gt;event_state[i];</div><div class='add'>+		event_state-&gt;last_seqno = RAS_EVENT_INVALID_ID;</div><div class='add'>+		atomic64_set(&amp;event_state-&gt;count, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_event_mgr_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_hive_info *hive;</div><div class='add'>+</div><div class='add'>+	if (!ras)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	ras-&gt;event_mgr = hive ? &amp;hive-&gt;event_mgr : &amp;ras-&gt;__event_mgr;</div><div class='add'>+</div><div class='add'>+	/* init event manager with node 0 on xgmi system */</div><div class='add'>+	if (!amdgpu_reset_in_recovery(adev)) {</div><div class='add'>+		if (!hive || adev-&gt;gmc.xgmi.node_id == 0)</div><div class='add'>+			ras_event_mgr_init(ras-&gt;event_mgr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hive)</div><div class='add'>+		amdgpu_put_xgmi_hive(hive);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_init_reserved_vram_size(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	if (!con || (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(13, 0, 2):</div><div class='add'>+	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+		con-&gt;reserved_pages_in_bytes = AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='add'>+		con-&gt;reserved_pages_in_bytes = (AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT &lt;&lt; 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_ras_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='hunk'>@@ -3103,7 +4318,19 @@ int amdgpu_ras_init(struct amdgpu_device *adev)</div><div class='ctx'> 			 * check DF RAS */</div><div class='ctx'> 			adev-&gt;nbio.ras = &amp;nbio_v4_3_ras;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(6, 3, 1):</div><div class='add'>+		if (adev-&gt;ras_hw_enabled &amp; (1 &lt;&lt; AMDGPU_RAS_BLOCK__DF))</div><div class='add'>+			/* unlike other generation of nbio ras,</div><div class='add'>+			 * nbif v6_3_1 only support fatal error interrupt</div><div class='add'>+			 * to inform software that DF is freezed due to</div><div class='add'>+			 * system fatal error event. driver should not</div><div class='add'>+			 * enable nbio ras in such case. Instead,</div><div class='add'>+			 * check DF RAS</div><div class='add'>+			 */</div><div class='add'>+			adev-&gt;nbio.ras = &amp;nbif_v6_3_1_ras;</div><div class='add'>+		break;</div><div class='ctx'> 	case IP_VERSION(7, 9, 0):</div><div class='add'>+	case IP_VERSION(7, 9, 1):</div><div class='ctx'> 		if (!adev-&gt;gmc.is_app_apu)</div><div class='ctx'> 			adev-&gt;nbio.ras = &amp;nbio_v7_9_ras;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -3141,11 +4368,28 @@ int amdgpu_ras_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* Get RAS schema for particular SOC */</div><div class='ctx'> 	con-&gt;schema = amdgpu_get_ras_schema(adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_ras_init_reserved_vram_size(adev);</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_ras_fs_init(adev)) {</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> 		goto release_con;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ras_aca_is_supported(adev)) {</div><div class='add'>+		if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+			r = amdgpu_aca_init(adev);</div><div class='add'>+		else</div><div class='add'>+			r = amdgpu_mca_init(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			goto release_con;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	con-&gt;init_task_pid = task_pid_nr(current);</div><div class='add'>+	get_task_comm(con-&gt;init_task_comm, current);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;con-&gt;critical_region_lock);</div><div class='add'>+	INIT_LIST_HEAD(&amp;con-&gt;critical_region_head);</div><div class='add'>+</div><div class='ctx'> 	dev_info(adev-&gt;dev, "RAS INFO: ras initialized successfully, "</div><div class='ctx'> 		 "hardware ability[%x] ras_mask[%x]\n",</div><div class='ctx'> 		 adev-&gt;ras_hw_enabled, adev-&gt;ras_enabled);</div><div class='hunk'>@@ -3213,7 +4457,7 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		if (adev-&gt;in_suspend || amdgpu_in_reset(adev)) {</div><div class='add'>+		if (adev-&gt;in_suspend || amdgpu_reset_in_recovery(adev)) {</div><div class='ctx'> 			/* in resume phase, if fail to enable ras,</div><div class='ctx'> 			 * clean up all ras fs nodes, and disable ras */</div><div class='ctx'> 			goto cleanup;</div><div class='hunk'>@@ -3225,7 +4469,7 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev,</div><div class='ctx'> 	amdgpu_persistent_edc_harvesting(adev, ras_block);</div><div class='ctx'> </div><div class='ctx'> 	/* in resume phase, no need to create ras fs node */</div><div class='del'>-	if (adev-&gt;in_suspend || amdgpu_in_reset(adev))</div><div class='add'>+	if (adev-&gt;in_suspend || amdgpu_reset_in_recovery(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);</div><div class='hunk'>@@ -3352,23 +4596,30 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)</div><div class='ctx'> 	struct amdgpu_ras_block_object *obj;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* Guest side doesn't need init ras feature */</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		return 0;</div><div class='add'>+	amdgpu_ras_event_mgr_init(adev);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_aca_is_enabled(adev)) {</div><div class='del'>-		if (amdgpu_in_reset(adev))</div><div class='del'>-			r = amdgpu_aca_reset(adev);</div><div class='del'>-		 else</div><div class='del'>-			r = amdgpu_aca_init(adev);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	if (amdgpu_ras_aca_is_supported(adev)) {</div><div class='add'>+		if (amdgpu_reset_in_recovery(adev)) {</div><div class='add'>+			if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+				r = amdgpu_aca_reset(adev);</div><div class='add'>+			else</div><div class='add'>+				r = amdgpu_mca_reset(adev);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		amdgpu_ras_set_aca_debug_mode(adev, false);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_ras_set_mca_debug_mode(adev, false);</div><div class='add'>+		if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+			if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+				amdgpu_ras_set_aca_debug_mode(adev, false);</div><div class='add'>+			else</div><div class='add'>+				amdgpu_ras_set_mca_debug_mode(adev, false);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Guest side doesn't need init ras feature */</div><div class='add'>+	if (amdgpu_sriov_vf(adev) &amp;&amp; !amdgpu_sriov_ras_telemetry_en(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(node, tmp, &amp;adev-&gt;ras_list, node) {</div><div class='ctx'> 		obj = node-&gt;ras_obj;</div><div class='ctx'> 		if (!obj) {</div><div class='hunk'>@@ -3418,6 +4669,9 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!adev-&gt;ras_enabled || !con)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	amdgpu_ras_critical_region_fini(adev);</div><div class='add'>+	mutex_destroy(&amp;con-&gt;critical_region_lock);</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(ras_node, tmp, &amp;adev-&gt;ras_list, node) {</div><div class='ctx'> 		if (ras_node-&gt;ras_obj) {</div><div class='ctx'> 			obj = ras_node-&gt;ras_obj;</div><div class='hunk'>@@ -3436,8 +4690,12 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_ras_fs_fini(adev);</div><div class='ctx'> 	amdgpu_ras_interrupt_remove_all(adev);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_aca_is_enabled(adev))</div><div class='del'>-		amdgpu_aca_fini(adev);</div><div class='add'>+	if (amdgpu_ras_aca_is_supported(adev)) {</div><div class='add'>+		if (amdgpu_aca_is_enabled(adev))</div><div class='add'>+			amdgpu_aca_fini(adev);</div><div class='add'>+		else</div><div class='add'>+			amdgpu_mca_fini(adev);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	WARN(AMDGPU_RAS_GET_FEATURES(con-&gt;features), "Feature mask is not cleared");</div><div class='ctx'> </div><div class='hunk'>@@ -3460,7 +4718,7 @@ bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!ras)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	return atomic_read(&amp;ras-&gt;fed);</div><div class='add'>+	return test_bit(AMDGPU_RAS_BLOCK__LAST, &amp;ras-&gt;ras_err_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status)</div><div class='hunk'>@@ -3468,21 +4726,145 @@ void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status)</div><div class='ctx'> 	struct amdgpu_ras *ras;</div><div class='ctx'> </div><div class='ctx'> 	ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	if (ras) {</div><div class='add'>+		if (status)</div><div class='add'>+			set_bit(AMDGPU_RAS_BLOCK__LAST, &amp;ras-&gt;ras_err_state);</div><div class='add'>+		else</div><div class='add'>+			clear_bit(AMDGPU_RAS_BLOCK__LAST, &amp;ras-&gt;ras_err_state);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_clear_err_state(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras;</div><div class='add'>+</div><div class='add'>+	ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	if (ras) {</div><div class='add'>+		ras-&gt;ras_err_state = 0;</div><div class='add'>+		ras-&gt;gpu_reset_flags = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_set_err_poison(struct amdgpu_device *adev,</div><div class='add'>+			       enum amdgpu_ras_block block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras;</div><div class='add'>+</div><div class='add'>+	ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	if (ras)</div><div class='del'>-		atomic_set(&amp;ras-&gt;fed, !!status);</div><div class='add'>+		set_bit(block, &amp;ras-&gt;ras_err_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras;</div><div class='add'>+</div><div class='add'>+	ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	if (ras) {</div><div class='add'>+		if (block == AMDGPU_RAS_BLOCK__ANY)</div><div class='add'>+			return (ras-&gt;ras_err_state != 0);</div><div class='add'>+		else</div><div class='add'>+			return test_bit(block, &amp;ras-&gt;ras_err_state) ||</div><div class='add'>+			       test_bit(AMDGPU_RAS_BLOCK__LAST,</div><div class='add'>+					&amp;ras-&gt;ras_err_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct ras_event_manager *__get_ras_event_mgr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras;</div><div class='add'>+</div><div class='add'>+	ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	if (!ras)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return ras-&gt;event_mgr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)</div><div class='add'>+int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,</div><div class='add'>+				     const void *caller)</div><div class='add'>+{</div><div class='add'>+	struct ras_event_manager *event_mgr;</div><div class='add'>+	struct ras_event_state *event_state;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (type &gt;= RAS_EVENT_TYPE_COUNT) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	event_mgr = __get_ras_event_mgr(adev);</div><div class='add'>+	if (!event_mgr) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	event_state = &amp;event_mgr-&gt;event_state[type];</div><div class='add'>+	event_state-&gt;last_seqno = atomic64_inc_return(&amp;event_mgr-&gt;seqno);</div><div class='add'>+	atomic64_inc(&amp;event_state-&gt;count);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	if (ret &amp;&amp; caller)</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed mark ras event (%d) in %ps, ret:%d\n",</div><div class='add'>+			 (int)type, caller, ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type)</div><div class='add'>+{</div><div class='add'>+	struct ras_event_manager *event_mgr;</div><div class='add'>+	u64 id;</div><div class='add'>+</div><div class='add'>+	if (type &gt;= RAS_EVENT_TYPE_COUNT)</div><div class='add'>+		return RAS_EVENT_INVALID_ID;</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case RAS_EVENT_TYPE_FATAL:</div><div class='add'>+	case RAS_EVENT_TYPE_POISON_CREATION:</div><div class='add'>+	case RAS_EVENT_TYPE_POISON_CONSUMPTION:</div><div class='add'>+		event_mgr = __get_ras_event_mgr(adev);</div><div class='add'>+		if (!event_mgr)</div><div class='add'>+			return RAS_EVENT_INVALID_ID;</div><div class='add'>+</div><div class='add'>+		id = event_mgr-&gt;event_state[type].last_seqno;</div><div class='add'>+		break;</div><div class='add'>+	case RAS_EVENT_TYPE_INVALID:</div><div class='add'>+	default:</div><div class='add'>+		id = RAS_EVENT_INVALID_ID;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return id;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (atomic_cmpxchg(&amp;amdgpu_ras_in_intr, 0, 1) == 0) {</div><div class='ctx'> 		struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+		enum ras_event_type type = RAS_EVENT_TYPE_FATAL;</div><div class='add'>+		u64 event_id = RAS_EVENT_INVALID_ID;</div><div class='add'>+</div><div class='add'>+		if (amdgpu_uniras_enabled(adev))</div><div class='add'>+			return 0;</div><div class='ctx'> </div><div class='del'>-		dev_info(adev-&gt;dev, "uncorrectable hardware error"</div><div class='del'>-			"(ERREVENT_ATHUB_INTERRUPT) detected!\n");</div><div class='add'>+		if (!amdgpu_ras_mark_ras_event(adev, type))</div><div class='add'>+			event_id = amdgpu_ras_acquire_event_id(adev, type);</div><div class='ctx'> </div><div class='add'>+		RAS_EVENT_LOG(adev, event_id, "uncorrectable hardware error"</div><div class='add'>+			      "(ERREVENT_ATHUB_INTERRUPT) detected!\n");</div><div class='add'>+</div><div class='add'>+		amdgpu_ras_set_fed(adev, true);</div><div class='ctx'> 		ras-&gt;gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='ctx'> 		amdgpu_ras_reset_gpu(adev);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return -EBUSY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3610,6 +4992,28 @@ static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)</div><div class='ctx'> 		notifier_registered = true;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+static void amdgpu_unregister_bad_pages_mca_notifier(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (!notifier_registered &amp;&amp; !mce_adev_list.num_gpu)</div><div class='add'>+		return;</div><div class='add'>+	for (i = 0, j = 0; i &lt; mce_adev_list.num_gpu; i++) {</div><div class='add'>+		if (mce_adev_list.devs[i] == adev)</div><div class='add'>+			mce_adev_list.devs[i] = NULL;</div><div class='add'>+		if (!mce_adev_list.devs[i])</div><div class='add'>+			++j;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (j == mce_adev_list.num_gpu) {</div><div class='add'>+		mce_adev_list.num_gpu = 0;</div><div class='add'>+		/* Unregister x86 notifier with MCE subsystem. */</div><div class='add'>+		if (notifier_registered) {</div><div class='add'>+			mce_unregister_decode_chain(&amp;amdgpu_bad_page_nb);</div><div class='add'>+			notifier_registered = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3664,8 +5068,33 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='del'>-	if (atomic_cmpxchg(&amp;ras-&gt;in_recovery, 0, 1) == 0)</div><div class='add'>+	/* mode1 is the only selection for RMA status */</div><div class='add'>+	if (amdgpu_ras_is_rma(adev)) {</div><div class='add'>+		ras-&gt;gpu_reset_flags = 0;</div><div class='add'>+		ras-&gt;gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (atomic_cmpxchg(&amp;ras-&gt;in_recovery, 0, 1) == 0) {</div><div class='add'>+		struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+		int hive_ras_recovery = 0;</div><div class='add'>+</div><div class='add'>+		if (hive) {</div><div class='add'>+			hive_ras_recovery = atomic_read(&amp;hive-&gt;ras_recovery);</div><div class='add'>+			amdgpu_put_xgmi_hive(hive);</div><div class='add'>+		}</div><div class='add'>+		/* In the case of multiple GPUs, after a GPU has started</div><div class='add'>+		 * resetting all GPUs on hive, other GPUs do not need to</div><div class='add'>+		 * trigger GPU reset again.</div><div class='add'>+		 */</div><div class='add'>+		if (!hive_ras_recovery)</div><div class='add'>+			amdgpu_reset_domain_schedule(ras-&gt;adev-&gt;reset_domain, &amp;ras-&gt;recovery_work);</div><div class='add'>+		else</div><div class='add'>+			atomic_set(&amp;ras-&gt;in_recovery, 0);</div><div class='add'>+	} else {</div><div class='add'>+		flush_work(&amp;ras-&gt;recovery_work);</div><div class='ctx'> 		amdgpu_reset_domain_schedule(ras-&gt;adev-&gt;reset_domain, &amp;ras-&gt;recovery_work);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3728,11 +5157,14 @@ bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((smu_funcs &amp;&amp; smu_funcs-&gt;set_debug_mode) || (mca_funcs &amp;&amp; mca_funcs-&gt;mca_set_debug_mode))</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		*error_query_mode = AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY;</div><div class='add'>+	} else if ((smu_funcs &amp;&amp; smu_funcs-&gt;set_debug_mode) || (mca_funcs &amp;&amp; mca_funcs-&gt;mca_set_debug_mode)) {</div><div class='ctx'> 		*error_query_mode =</div><div class='ctx'> 			(con-&gt;is_aca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY;</div><div class='del'>-	else</div><div class='add'>+	} else {</div><div class='ctx'> 		*error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -3983,8 +5415,6 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d</div><div class='ctx'> 	if (!err_node)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	INIT_LIST_HEAD(&amp;err_node-&gt;err_info.err_addr_list);</div><div class='del'>-</div><div class='ctx'> 	memcpy(&amp;err_node-&gt;err_info.mcm_info, mcm_info, sizeof(*mcm_info));</div><div class='ctx'> </div><div class='ctx'> 	err_data-&gt;err_list_count++;</div><div class='hunk'>@@ -3994,32 +5424,9 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d</div><div class='ctx'> 	return &amp;err_node-&gt;err_info;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *err_addr)</div><div class='del'>-{</div><div class='del'>-	struct ras_err_addr *mca_err_addr;</div><div class='del'>-</div><div class='del'>-	mca_err_addr = kzalloc(sizeof(*mca_err_addr), GFP_KERNEL);</div><div class='del'>-	if (!mca_err_addr)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	INIT_LIST_HEAD(&amp;mca_err_addr-&gt;node);</div><div class='del'>-</div><div class='del'>-	mca_err_addr-&gt;err_status = err_addr-&gt;err_status;</div><div class='del'>-	mca_err_addr-&gt;err_ipid = err_addr-&gt;err_ipid;</div><div class='del'>-	mca_err_addr-&gt;err_addr = err_addr-&gt;err_addr;</div><div class='del'>-</div><div class='del'>-	list_add_tail(&amp;mca_err_addr-&gt;node, &amp;err_info-&gt;err_addr_list);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *mca_err_addr)</div><div class='del'>-{</div><div class='del'>-	list_del(&amp;mca_err_addr-&gt;node);</div><div class='del'>-	kfree(mca_err_addr);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='del'>-		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='del'>-		struct ras_err_addr *err_addr, u64 count)</div><div class='add'>+					struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+					u64 count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_info *err_info;</div><div class='ctx'> </div><div class='hunk'>@@ -4033,9 +5440,6 @@ int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='ctx'> 	if (!err_info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (err_addr &amp;&amp; err_addr-&gt;err_status)</div><div class='del'>-		amdgpu_ras_add_mca_err_addr(err_info, err_addr);</div><div class='del'>-</div><div class='ctx'> 	err_info-&gt;ue_count += count;</div><div class='ctx'> 	err_data-&gt;ue_count += count;</div><div class='ctx'> </div><div class='hunk'>@@ -4043,8 +5447,8 @@ int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,</div><div class='del'>-		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='del'>-		struct ras_err_addr *err_addr, u64 count)</div><div class='add'>+					struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+					u64 count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_info *err_info;</div><div class='ctx'> </div><div class='hunk'>@@ -4065,8 +5469,8 @@ int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,</div><div class='del'>-		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='del'>-		struct ras_err_addr *err_addr, u64 count)</div><div class='add'>+					struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+					u64 count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_info *err_info;</div><div class='ctx'> </div><div class='hunk'>@@ -4080,9 +5484,6 @@ int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,</div><div class='ctx'> 	if (!err_info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (err_addr &amp;&amp; err_addr-&gt;err_status)</div><div class='del'>-		amdgpu_ras_add_mca_err_addr(err_info, err_addr);</div><div class='del'>-</div><div class='ctx'> 	err_info-&gt;de_count += count;</div><div class='ctx'> 	err_data-&gt;de_count += count;</div><div class='ctx'> </div><div class='hunk'>@@ -4092,64 +5493,84 @@ int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,</div><div class='ctx'> #define mmMP0_SMN_C2PMSG_92	0x1609C</div><div class='ctx'> #define mmMP0_SMN_C2PMSG_126	0x160BE</div><div class='ctx'> static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev,</div><div class='del'>-						 u32 instance, u32 boot_error)</div><div class='add'>+						 u32 instance)</div><div class='ctx'> {</div><div class='ctx'> 	u32 socket_id, aid_id, hbm_id;</div><div class='del'>-	u32 reg_data;</div><div class='add'>+	u32 fw_status;</div><div class='add'>+	u32 boot_error;</div><div class='ctx'> 	u64 reg_addr;</div><div class='ctx'> </div><div class='del'>-	socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);</div><div class='del'>-	aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);</div><div class='del'>-	hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error);</div><div class='del'>-</div><div class='ctx'> 	/* The pattern for smn addressing in other SOC could be different from</div><div class='ctx'> 	 * the one for aqua_vanjaram. We should revisit the code if the pattern</div><div class='ctx'> 	 * is changed. In such case, replace the aqua_vanjaram implementation</div><div class='ctx'> 	 * with more common helper */</div><div class='ctx'> 	reg_addr = (mmMP0_SMN_C2PMSG_92 &lt;&lt; 2) +</div><div class='ctx'> 		   aqua_vanjaram_encode_ext_smn_addressing(instance);</div><div class='add'>+	fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr);</div><div class='add'>+</div><div class='add'>+	reg_addr = (mmMP0_SMN_C2PMSG_126 &lt;&lt; 2) +</div><div class='add'>+		   aqua_vanjaram_encode_ext_smn_addressing(instance);</div><div class='add'>+	boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr);</div><div class='ctx'> </div><div class='del'>-	reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);</div><div class='del'>-	dev_err(adev-&gt;dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n",</div><div class='del'>-		socket_id, aid_id, reg_data);</div><div class='add'>+	socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);</div><div class='add'>+	aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);</div><div class='add'>+	hbm_id = ((1 == AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error)) ? 0 : 1);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n",</div><div class='del'>-			 socket_id, aid_id, hbm_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, memory training failed\n",</div><div class='add'>+			 socket_id, aid_id, hbm_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, firmware load failed at boot time\n",</div><div class='del'>-			 socket_id, aid_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, firmware load failed at boot time\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, wafl link training failed\n",</div><div class='del'>-			 socket_id, aid_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, wafl link training failed\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, xgmi link training failed\n",</div><div class='del'>-			 socket_id, aid_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, xgmi link training failed\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, usr cp link training failed\n",</div><div class='del'>-			 socket_id, aid_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, usr cp link training failed\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, usr dp link training failed\n",</div><div class='del'>-			 socket_id, aid_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, usr dp link training failed\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n",</div><div class='del'>-			 socket_id, aid_id, hbm_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, hbm memory test failed\n",</div><div class='add'>+			 socket_id, aid_id, hbm_id, fw_status);</div><div class='ctx'> </div><div class='ctx'> 	if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_error))</div><div class='del'>-		dev_info(adev-&gt;dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n",</div><div class='del'>-			 socket_id, aid_id, hbm_id);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, hbm: %d, fw_status: 0x%x, hbm bist test failed\n",</div><div class='add'>+			 socket_id, aid_id, hbm_id, fw_status);</div><div class='add'>+</div><div class='add'>+	if (AMDGPU_RAS_GPU_ERR_DATA_ABORT(boot_error))</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, data abort exception\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='add'>+</div><div class='add'>+	if (AMDGPU_RAS_GPU_ERR_GENERIC(boot_error))</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "socket: %d, aid: %d, fw_status: 0x%x, Boot Controller Generic Error\n",</div><div class='add'>+			 socket_id, aid_id, fw_status);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_ras_wait_for_boot_complete(struct amdgpu_device *adev,</div><div class='del'>-					     u32 instance, u32 *boot_error)</div><div class='add'>+static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev,</div><div class='add'>+					   u32 instance)</div><div class='ctx'> {</div><div class='del'>-	u32 reg_addr;</div><div class='add'>+	u64 reg_addr;</div><div class='ctx'> 	u32 reg_data;</div><div class='ctx'> 	int retry_loop;</div><div class='ctx'> </div><div class='hunk'>@@ -4158,40 +5579,170 @@ static int amdgpu_ras_wait_for_boot_complete(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	for (retry_loop = 0; retry_loop &lt; AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {</div><div class='ctx'> 		reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);</div><div class='del'>-		if ((reg_data &amp; AMDGPU_RAS_BOOT_STATUS_MASK) == AMDGPU_RAS_BOOT_STEADY_STATUS) {</div><div class='del'>-			*boot_error = AMDGPU_RAS_BOOT_SUCEESS;</div><div class='del'>-			return 0;</div><div class='add'>+		if ((reg_data &amp; AMDGPU_RAS_BOOT_STATUS_MASK) == AMDGPU_RAS_BOOT_STEADY_STATUS)</div><div class='add'>+			return false;</div><div class='add'>+		else</div><div class='add'>+			msleep(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances)</div><div class='add'>+{</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_instances; i++) {</div><div class='add'>+		if (amdgpu_ras_boot_error_detected(adev, i))</div><div class='add'>+			amdgpu_ras_boot_time_error_reporting(adev, i);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_vram_mgr *mgr = &amp;adev-&gt;mman.vram_mgr;</div><div class='add'>+	uint64_t start = pfn &lt;&lt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_check_critical_address(adev, start))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;page_rsv_lock);</div><div class='add'>+	ret = amdgpu_vram_mgr_query_page_status(mgr, start);</div><div class='add'>+	if (ret == -ENOENT)</div><div class='add'>+		ret = amdgpu_vram_mgr_reserve_range(mgr, start, AMDGPU_GPU_PAGE_SIZE);</div><div class='add'>+	mutex_unlock(&amp;con-&gt;page_rsv_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,</div><div class='add'>+				const char *fmt, ...)</div><div class='add'>+{</div><div class='add'>+	struct va_format vaf;</div><div class='add'>+	va_list args;</div><div class='add'>+</div><div class='add'>+	va_start(args, fmt);</div><div class='add'>+	vaf.fmt = fmt;</div><div class='add'>+	vaf.va = &amp;args;</div><div class='add'>+</div><div class='add'>+	if (RAS_EVENT_ID_IS_VALID(event_id))</div><div class='add'>+		dev_printk(KERN_INFO, adev-&gt;dev, "{%llu}%pV", event_id, &amp;vaf);</div><div class='add'>+	else</div><div class='add'>+		dev_printk(KERN_INFO, adev-&gt;dev, "%pV", &amp;vaf);</div><div class='add'>+</div><div class='add'>+	va_end(args);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_is_rma(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		return amdgpu_ras_mgr_is_rma(adev);</div><div class='add'>+</div><div class='add'>+	if (!con)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return con-&gt;is_rma;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_add_critical_region(struct amdgpu_device *adev,</div><div class='add'>+			struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_vram_mgr_resource *vres;</div><div class='add'>+	struct ras_critical_region *region;</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!bo || !bo-&gt;tbo.resource)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	vres = to_amdgpu_vram_mgr_resource(bo-&gt;tbo.resource);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;critical_region_lock);</div><div class='add'>+</div><div class='add'>+	/* Check if the bo had been recorded */</div><div class='add'>+	list_for_each_entry(region, &amp;con-&gt;critical_region_head, node)</div><div class='add'>+		if (region-&gt;bo == bo)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+	/* Record new critical amdgpu bo */</div><div class='add'>+	list_for_each_entry(block, &amp;vres-&gt;blocks, link) {</div><div class='add'>+		region = kzalloc(sizeof(*region), GFP_KERNEL);</div><div class='add'>+		if (!region) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='del'>-		msleep(1);</div><div class='add'>+		region-&gt;bo = bo;</div><div class='add'>+		region-&gt;start = amdgpu_vram_mgr_block_start(block);</div><div class='add'>+		region-&gt;size = amdgpu_vram_mgr_block_size(block);</div><div class='add'>+		list_add_tail(&amp;region-&gt;node, &amp;con-&gt;critical_region_head);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* The pattern for smn addressing in other SOC could be different from</div><div class='del'>-	 * the one for aqua_vanjaram. We should revisit the code if the pattern</div><div class='del'>-	 * is changed. In such case, replace the aqua_vanjaram implementation</div><div class='del'>-	 * with more common helper */</div><div class='del'>-	reg_addr = (mmMP0_SMN_C2PMSG_126 &lt;&lt; 2) +</div><div class='del'>-		   aqua_vanjaram_encode_ext_smn_addressing(instance);</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;con-&gt;critical_region_lock);</div><div class='ctx'> </div><div class='del'>-	for (retry_loop = 0; retry_loop &lt; AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {</div><div class='del'>-		reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);</div><div class='del'>-		if (AMDGPU_RAS_GPU_ERR_BOOT_STATUS(reg_data)) {</div><div class='del'>-			*boot_error = reg_data;</div><div class='del'>-			return 0;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ras_add_critical_region(adev, adev-&gt;mman.fw_reserved_memory);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_critical_region *region, *tmp;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;critical_region_lock);</div><div class='add'>+	list_for_each_entry_safe(region, tmp, &amp;con-&gt;critical_region_head, node) {</div><div class='add'>+		list_del(&amp;region-&gt;node);</div><div class='add'>+		kfree(region);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;con-&gt;critical_region_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_critical_region *region;</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;critical_region_lock);</div><div class='add'>+	list_for_each_entry(region, &amp;con-&gt;critical_region_head, node) {</div><div class='add'>+		if ((region-&gt;start &lt;= addr) &amp;&amp;</div><div class='add'>+		    (addr &lt; (region-&gt;start + region-&gt;size))) {</div><div class='add'>+			ret = true;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='del'>-		msleep(1);</div><div class='ctx'> 	}</div><div class='add'>+	mutex_unlock(&amp;con-&gt;critical_region_lock);</div><div class='ctx'> </div><div class='del'>-	*boot_error = reg_data;</div><div class='del'>-	return -ETIME;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances)</div><div class='add'>+void amdgpu_ras_pre_reset(struct amdgpu_device *adev,</div><div class='add'>+					  struct list_head *device_list)</div><div class='ctx'> {</div><div class='del'>-	u32 boot_error = 0;</div><div class='del'>-	u32 i;</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; num_instances; i++) {</div><div class='del'>-		if (amdgpu_ras_wait_for_boot_complete(adev, i, &amp;boot_error))</div><div class='del'>-			amdgpu_ras_boot_time_error_reporting(adev, i, boot_error);</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='add'>+		if (amdgpu_uniras_enabled(tmp_adev))</div><div class='add'>+			amdgpu_ras_mgr_pre_reset(tmp_adev);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_post_reset(struct amdgpu_device *adev,</div><div class='add'>+					  struct list_head *device_list)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(tmp_adev, device_list, reset_list) {</div><div class='add'>+		if (amdgpu_uniras_enabled(tmp_adev))</div><div class='add'>+			amdgpu_ras_mgr_post_reset(tmp_adev);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h<br/>index e0f8ce9d8440..ff44190d7d98 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h</a></div><div class='hunk'>@@ -26,6 +26,8 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='add'>+#include &lt;linux/kfifo.h&gt;</div><div class='add'>+#include &lt;linux/radix-tree.h&gt;</div><div class='ctx'> #include "ta_ras_if.h"</div><div class='ctx'> #include "amdgpu_ras_eeprom.h"</div><div class='ctx'> #include "amdgpu_smuio.h"</div><div class='hunk'>@@ -43,13 +45,13 @@ struct amdgpu_iv_entry;</div><div class='ctx'> #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x)		AMDGPU_GET_REG_FIELD(x, 7, 7)</div><div class='ctx'> #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x)			AMDGPU_GET_REG_FIELD(x, 10, 8)</div><div class='ctx'> #define AMDGPU_RAS_GPU_ERR_AID_ID(x)			AMDGPU_GET_REG_FIELD(x, 12, 11)</div><div class='del'>-#define AMDGPU_RAS_GPU_ERR_HBM_ID(x)			AMDGPU_GET_REG_FIELD(x, 13, 13)</div><div class='del'>-#define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x)		AMDGPU_GET_REG_FIELD(x, 31, 31)</div><div class='add'>+#define AMDGPU_RAS_GPU_ERR_HBM_ID(x)			AMDGPU_GET_REG_FIELD(x, 14, 13)</div><div class='add'>+#define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x)		AMDGPU_GET_REG_FIELD(x, 29, 29)</div><div class='add'>+#define AMDGPU_RAS_GPU_ERR_GENERIC(x)			AMDGPU_GET_REG_FIELD(x, 30, 30)</div><div class='ctx'> </div><div class='del'>-#define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT	1000</div><div class='add'>+#define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT	100</div><div class='ctx'> #define AMDGPU_RAS_BOOT_STEADY_STATUS		0xBA</div><div class='ctx'> #define AMDGPU_RAS_BOOT_STATUS_MASK		0xFF</div><div class='del'>-#define AMDGPU_RAS_BOOT_SUCEESS			0x80000000</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS		(0x1 &lt;&lt; 0)</div><div class='ctx'> /* position of instance value in sub_block_index of</div><div class='hunk'>@@ -61,9 +63,21 @@ struct amdgpu_iv_entry;</div><div class='ctx'> #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29</div><div class='ctx'> #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000</div><div class='ctx'> </div><div class='add'>+/* Reserve 8 physical dram row for possible retirement.</div><div class='add'>+ * In worst cases, it will lose 8 * 2MB memory in vram domain */</div><div class='add'>+#define AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT	(16ULL &lt;&lt; 20)</div><div class='ctx'> /* The high three bits indicates socketid */</div><div class='ctx'> #define AMDGPU_RAS_GET_FEATURES(val)  ((val) &amp; ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)</div><div class='ctx'> </div><div class='add'>+#define RAS_EVENT_INVALID_ID		(BIT_ULL(63))</div><div class='add'>+#define RAS_EVENT_ID_IS_VALID(x)	(!((x) &amp; BIT_ULL(63)))</div><div class='add'>+</div><div class='add'>+#define RAS_EVENT_LOG(adev, id, fmt, ...)	\</div><div class='add'>+	amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define amdgpu_ras_mark_ras_event(adev, type)	\</div><div class='add'>+	(amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0)))</div><div class='add'>+</div><div class='ctx'> enum amdgpu_ras_block {</div><div class='ctx'> 	AMDGPU_RAS_BLOCK__UMC = 0,</div><div class='ctx'> 	AMDGPU_RAS_BLOCK__SDMA,</div><div class='hunk'>@@ -84,8 +98,10 @@ enum amdgpu_ras_block {</div><div class='ctx'> 	AMDGPU_RAS_BLOCK__JPEG,</div><div class='ctx'> 	AMDGPU_RAS_BLOCK__IH,</div><div class='ctx'> 	AMDGPU_RAS_BLOCK__MPIO,</div><div class='add'>+	AMDGPU_RAS_BLOCK__MMSCH,</div><div class='ctx'> </div><div class='del'>-	AMDGPU_RAS_BLOCK__LAST</div><div class='add'>+	AMDGPU_RAS_BLOCK__LAST,</div><div class='add'>+	AMDGPU_RAS_BLOCK__ANY = -1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_ras_mca_block {</div><div class='hunk'>@@ -351,6 +367,7 @@ enum amdgpu_ras_error_query_mode {</div><div class='ctx'> 	AMDGPU_RAS_INVALID_ERROR_QUERY		= 0,</div><div class='ctx'> 	AMDGPU_RAS_DIRECT_ERROR_QUERY		= 1,</div><div class='ctx'> 	AMDGPU_RAS_FIRMWARE_ERROR_QUERY		= 2,</div><div class='add'>+	AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY	= 3,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ras error status reisger fields */</div><div class='hunk'>@@ -419,7 +436,101 @@ struct umc_ecc_info {</div><div class='ctx'> 	int record_ce_addr_supported;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum ras_event_type {</div><div class='add'>+	RAS_EVENT_TYPE_INVALID = 0,</div><div class='add'>+	RAS_EVENT_TYPE_FATAL,</div><div class='add'>+	RAS_EVENT_TYPE_POISON_CREATION,</div><div class='add'>+	RAS_EVENT_TYPE_POISON_CONSUMPTION,</div><div class='add'>+	RAS_EVENT_TYPE_COUNT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_event_state {</div><div class='add'>+	u64 last_seqno;</div><div class='add'>+	atomic64_t count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_event_manager {</div><div class='add'>+	atomic64_t seqno;</div><div class='add'>+	struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_event_id {</div><div class='add'>+	enum ras_event_type type;</div><div class='add'>+	u64 event_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_query_context {</div><div class='add'>+	struct ras_event_id evid;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+typedef int (*pasid_notify)(struct amdgpu_device *adev,</div><div class='add'>+		uint16_t pasid, void *data);</div><div class='add'>+</div><div class='add'>+struct ras_poison_msg {</div><div class='add'>+	enum amdgpu_ras_block block;</div><div class='add'>+	uint16_t pasid;</div><div class='add'>+	uint32_t reset;</div><div class='add'>+	pasid_notify pasid_fn;</div><div class='add'>+	void *data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_err_pages {</div><div class='add'>+	uint32_t count;</div><div class='add'>+	uint64_t *pfn;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_ecc_err {</div><div class='add'>+	uint64_t status;</div><div class='add'>+	uint64_t ipid;</div><div class='add'>+	uint64_t addr;</div><div class='add'>+	uint64_t pa_pfn;</div><div class='add'>+	/* save global channel index across all UMC instances */</div><div class='add'>+	uint32_t channel_idx;</div><div class='add'>+	struct ras_err_pages err_pages;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_ecc_log_info {</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	struct radix_tree_root de_page_tree;</div><div class='add'>+	uint64_t de_queried_count;</div><div class='add'>+	uint64_t consumption_q_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_critical_region {</div><div class='add'>+	struct list_head node;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	uint64_t start;</div><div class='add'>+	uint64_t size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_eeprom_table_version {</div><div class='add'>+	uint32_t minor    : 16;</div><div class='add'>+	uint32_t major    : 16;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_eeprom_smu_funcs {</div><div class='add'>+	int (*get_ras_table_version)(struct amdgpu_device *adev,</div><div class='add'>+							uint32_t *table_version);</div><div class='add'>+	int (*get_badpage_count)(struct amdgpu_device *adev, uint32_t *count, uint32_t timeout);</div><div class='add'>+	int (*get_badpage_mca_addr)(struct amdgpu_device *adev, uint16_t index, uint64_t *mca_addr);</div><div class='add'>+	int (*set_timestamp)(struct amdgpu_device *adev, uint64_t timestamp);</div><div class='add'>+	int (*get_timestamp)(struct amdgpu_device *adev,</div><div class='add'>+							uint16_t index, uint64_t *timestamp);</div><div class='add'>+	int (*get_badpage_ipid)(struct amdgpu_device *adev, uint16_t index, uint64_t *ipid);</div><div class='add'>+	int (*erase_ras_table)(struct amdgpu_device *adev, uint32_t *result);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum ras_smu_feature_flags {</div><div class='add'>+	RAS_SMU_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ras_smu_drv {</div><div class='add'>+	const struct ras_eeprom_smu_funcs *smu_eeprom_funcs;</div><div class='add'>+	void (*ras_smu_feature_flags)(struct amdgpu_device *adev, uint64_t *flags);</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_ras {</div><div class='add'>+	void *ras_mgr;</div><div class='ctx'> 	/* ras infrastructure */</div><div class='ctx'> 	/* for ras itself. */</div><div class='ctx'> 	uint32_t features;</div><div class='hunk'>@@ -429,6 +540,7 @@ struct amdgpu_ras {</div><div class='ctx'> 	struct device_attribute features_attr;</div><div class='ctx'> 	struct device_attribute version_attr;</div><div class='ctx'> 	struct device_attribute schema_attr;</div><div class='add'>+	struct device_attribute event_state_attr;</div><div class='ctx'> 	struct bin_attribute badpages_attr;</div><div class='ctx'> 	struct dentry *de_ras_eeprom_table;</div><div class='ctx'> 	/* block array */</div><div class='hunk'>@@ -437,6 +549,7 @@ struct amdgpu_ras {</div><div class='ctx'> 	/* gpu recovery */</div><div class='ctx'> 	struct work_struct recovery_work;</div><div class='ctx'> 	atomic_t in_recovery;</div><div class='add'>+	atomic_t rma_in_recovery;</div><div class='ctx'> 	struct amdgpu_device *adev;</div><div class='ctx'> 	/* error handler data */</div><div class='ctx'> 	struct ras_err_handler_data *eh_data;</div><div class='hunk'>@@ -469,6 +582,7 @@ struct amdgpu_ras {</div><div class='ctx'> 	bool update_channel_flag;</div><div class='ctx'> 	/* Record status of smu mca debug mode */</div><div class='ctx'> 	bool is_aca_debug_mode;</div><div class='add'>+	bool is_rma;</div><div class='ctx'> </div><div class='ctx'> 	/* Record special requirements of gpu reset caller */</div><div class='ctx'> 	uint32_t  gpu_reset_flags;</div><div class='hunk'>@@ -477,8 +591,36 @@ struct amdgpu_ras {</div><div class='ctx'> 	wait_queue_head_t page_retirement_wq;</div><div class='ctx'> 	struct mutex page_retirement_lock;</div><div class='ctx'> 	atomic_t page_retirement_req_cnt;</div><div class='del'>-	/* Fatal error detected flag */</div><div class='del'>-	atomic_t fed;</div><div class='add'>+	atomic_t poison_creation_count;</div><div class='add'>+	atomic_t poison_consumption_count;</div><div class='add'>+	struct mutex page_rsv_lock;</div><div class='add'>+	DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128);</div><div class='add'>+	struct ras_ecc_log_info  umc_ecc_log;</div><div class='add'>+	struct delayed_work page_retirement_dwork;</div><div class='add'>+</div><div class='add'>+	/* ras errors detected */</div><div class='add'>+	unsigned long ras_err_state;</div><div class='add'>+</div><div class='add'>+	/* RAS event manager */</div><div class='add'>+	struct ras_event_manager __event_mgr;</div><div class='add'>+	struct ras_event_manager *event_mgr;</div><div class='add'>+</div><div class='add'>+	uint64_t reserved_pages_in_bytes;</div><div class='add'>+</div><div class='add'>+	pid_t init_task_pid;</div><div class='add'>+	char init_task_comm[TASK_COMM_LEN];</div><div class='add'>+</div><div class='add'>+	int bad_page_num;</div><div class='add'>+</div><div class='add'>+	struct list_head critical_region_head;</div><div class='add'>+	struct mutex critical_region_lock;</div><div class='add'>+</div><div class='add'>+	/* Protect poison injection */</div><div class='add'>+	struct mutex poison_lock;</div><div class='add'>+</div><div class='add'>+	/* Disable/Enable uniras switch */</div><div class='add'>+	bool uniras_enabled;</div><div class='add'>+	const struct ras_smu_drv *ras_smu_drv;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ras_fs_data {</div><div class='hunk'>@@ -486,19 +628,11 @@ struct ras_fs_data {</div><div class='ctx'> 	char debugfs_name[32];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct ras_err_addr {</div><div class='del'>-	struct list_head node;</div><div class='del'>-	uint64_t err_status;</div><div class='del'>-	uint64_t err_ipid;</div><div class='del'>-	uint64_t err_addr;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct ras_err_info {</div><div class='ctx'> 	struct amdgpu_smuio_mcm_config_info mcm_info;</div><div class='ctx'> 	u64 ce_count;</div><div class='ctx'> 	u64 ue_count;</div><div class='ctx'> 	u64 de_count;</div><div class='del'>-	struct list_head err_addr_list;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ras_err_node {</div><div class='hunk'>@@ -512,6 +646,7 @@ struct ras_err_data {</div><div class='ctx'> 	unsigned long de_count;</div><div class='ctx'> 	unsigned long err_addr_cnt;</div><div class='ctx'> 	struct eeprom_table_record *err_addr;</div><div class='add'>+	unsigned long err_addr_len;</div><div class='ctx'> 	u32 err_list_count;</div><div class='ctx'> 	struct list_head err_node_list;</div><div class='ctx'> };</div><div class='hunk'>@@ -524,6 +659,7 @@ struct ras_err_handler_data {</div><div class='ctx'> 	struct eeprom_table_record *bps;</div><div class='ctx'> 	/* the count of entries */</div><div class='ctx'> 	int count;</div><div class='add'>+	int count_saved;</div><div class='ctx'> 	/* the space can place new entries */</div><div class='ctx'> 	int space_left;</div><div class='ctx'> };</div><div class='hunk'>@@ -657,8 +793,8 @@ struct amdgpu_ras_block_hw_ops {</div><div class='ctx'>  * 8: feature disable</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-int amdgpu_ras_recovery_init(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ras_resume(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_ras_suspend(struct amdgpu_device *adev);</div><div class='hunk'>@@ -670,7 +806,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> /* error handling functions */</div><div class='ctx'> int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,</div><div class='del'>-		struct eeprom_table_record *bps, int pages);</div><div class='add'>+		struct eeprom_table_record *bps, int pages, bool from_rom);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> 		unsigned long *new_cnt);</div><div class='hunk'>@@ -712,6 +848,12 @@ amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {</div><div class='ctx'> 		return TA_RAS_BLOCK__VCN;</div><div class='ctx'> 	case AMDGPU_RAS_BLOCK__JPEG:</div><div class='ctx'> 		return TA_RAS_BLOCK__JPEG;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__IH:</div><div class='add'>+		return TA_RAS_BLOCK__IH;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MPIO:</div><div class='add'>+		return TA_RAS_BLOCK__MPIO;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MMSCH:</div><div class='add'>+		return TA_RAS_BLOCK__MMSCH;</div><div class='ctx'> 	default:</div><div class='ctx'> 		WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);</div><div class='ctx'> 		return TA_RAS_BLOCK__UMC;</div><div class='hunk'>@@ -798,7 +940,7 @@ static inline void amdgpu_ras_intr_cleared(void)</div><div class='ctx'> 	atomic_set(&amp;amdgpu_ras_in_intr, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);</div><div class='ctx'> </div><div class='hunk'>@@ -854,14 +996,14 @@ void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_ras_error_data_init(struct ras_err_data *err_data);</div><div class='ctx'> void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);</div><div class='ctx'> int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,</div><div class='del'>-		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='del'>-		struct ras_err_addr *err_addr, u64 count);</div><div class='add'>+					struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+					u64 count);</div><div class='ctx'> int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='del'>-		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='del'>-		struct ras_err_addr *err_addr, u64 count);</div><div class='add'>+					struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+					u64 count);</div><div class='ctx'> int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,</div><div class='del'>-		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='del'>-		struct ras_err_addr *err_addr, u64 count);</div><div class='add'>+					struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+					u64 count);</div><div class='ctx'> void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);</div><div class='ctx'> int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,</div><div class='ctx'> 			       const struct aca_info *aca_info, void *data);</div><div class='hunk'>@@ -870,13 +1012,36 @@ int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk)</div><div class='ctx'> ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 				  struct aca_handle *handle, char *buf, void *data);</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info,</div><div class='del'>-			struct ras_err_addr *err_addr);</div><div class='del'>-</div><div class='del'>-void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info,</div><div class='del'>-		struct ras_err_addr *mca_err_addr);</div><div class='del'>-</div><div class='ctx'> void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);</div><div class='ctx'> bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_ras_set_err_poison(struct amdgpu_device *adev,</div><div class='add'>+			       enum amdgpu_ras_block block);</div><div class='add'>+void amdgpu_ras_clear_err_state(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block);</div><div class='add'>+</div><div class='add'>+u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);</div><div class='add'>+int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,</div><div class='add'>+				     const void *caller);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_add_critical_region(struct amdgpu_device *adev, struct amdgpu_bo *bo);</div><div class='add'>+bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,</div><div class='add'>+		enum amdgpu_ras_block block, uint16_t pasid,</div><div class='add'>+		pasid_notify pasid_fn, void *data, uint32_t reset);</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_in_recovery(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+__printf(3, 4)</div><div class='add'>+void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,</div><div class='add'>+				const char *fmt, ...);</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_is_rma(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+void amdgpu_ras_pre_reset(struct amdgpu_device *adev,</div><div class='add'>+					  struct list_head *device_list);</div><div class='add'>+void amdgpu_ras_post_reset(struct amdgpu_device *adev,</div><div class='add'>+					  struct list_head *device_list);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c<br/>index b12808c0c331..64dd7a81bff5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> </div><div class='ctx'> /* These are memory addresses as would be seen by one or more EEPROM</div><div class='ctx'>  * chips strung on the I2C bus, usually by manipulating pins 1-3 of a</div><div class='hunk'>@@ -58,7 +59,7 @@</div><div class='ctx'> #define EEPROM_I2C_MADDR_4      0x40000</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * The 2 macros bellow represent the actual size in bytes that</div><div class='add'>+ * The 2 macros below represent the actual size in bytes that</div><div class='ctx'>  * those entities occupy in the EEPROM memory.</div><div class='ctx'>  * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which</div><div class='ctx'>  * uses uint64 to store 6b fields such as retired_page.</div><div class='hunk'>@@ -123,6 +124,8 @@</div><div class='ctx'> 					RAS_TABLE_V2_1_INFO_SIZE) \</div><div class='ctx'> 					/ RAS_TABLE_RECORD_SIZE)</div><div class='ctx'> </div><div class='add'>+#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */</div><div class='add'>+</div><div class='ctx'> /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM</div><div class='ctx'>  * offset off of RAS_TABLE_START.  That is, this is something you can</div><div class='ctx'>  * add to control-&gt;i2c_address, and then tell I2C layer to read</div><div class='hunk'>@@ -161,6 +164,8 @@ static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='ctx'> 		return true;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		return (adev-&gt;gmc.is_app_apu) ? false : true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -176,7 +181,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!control)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_atomfirmware_ras_rom_addr(adev, &amp;i2c_addr)) {</div><div class='add'>+	if (adev-&gt;bios &amp;&amp; amdgpu_atomfirmware_ras_rom_addr(adev, &amp;i2c_addr)) {</div><div class='ctx'> 		/* The address given by VBIOS is an 8-bit, wire-format</div><div class='ctx'> 		 * address, i.e. the most significant byte.</div><div class='ctx'> 		 *</div><div class='hunk'>@@ -222,6 +227,8 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,</div><div class='ctx'> 		return true;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		control-&gt;i2c_address = EEPROM_I2C_MADDR_4;</div><div class='ctx'> 		return true;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -273,10 +280,11 @@ static int __write_table_header(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> </div><div class='ctx'> 	if (res &lt; 0) {</div><div class='del'>-		DRM_ERROR("Failed to write EEPROM table header:%d", res);</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to write EEPROM table header:%d",</div><div class='add'>+			res);</div><div class='ctx'> 	} else if (res &lt; RAS_TABLE_HEADER_SIZE) {</div><div class='del'>-		DRM_ERROR("Short write:%d out of %d\n",</div><div class='del'>-			  res, RAS_TABLE_HEADER_SIZE);</div><div class='add'>+		dev_err(adev-&gt;dev, "Short write:%d out of %d\n", res,</div><div class='add'>+			RAS_TABLE_HEADER_SIZE);</div><div class='ctx'> 		res = -EIO;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		res = 0;</div><div class='hunk'>@@ -319,7 +327,8 @@ static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> </div><div class='ctx'> 	buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);</div><div class='ctx'> 	if (!buf) {</div><div class='del'>-		DRM_ERROR("Failed to alloc buf to write table ras info\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Failed to alloc buf to write table ras info\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -334,10 +343,11 @@ static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> </div><div class='ctx'> 	if (res &lt; 0) {</div><div class='del'>-		DRM_ERROR("Failed to write EEPROM table ras info:%d", res);</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to write EEPROM table ras info:%d",</div><div class='add'>+			res);</div><div class='ctx'> 	} else if (res &lt; RAS_TABLE_V2_1_INFO_SIZE) {</div><div class='del'>-		DRM_ERROR("Short write:%d out of %d\n",</div><div class='del'>-			  res, RAS_TABLE_V2_1_INFO_SIZE);</div><div class='add'>+		dev_err(adev-&gt;dev, "Short write:%d out of %d\n", res,</div><div class='add'>+			RAS_TABLE_V2_1_INFO_SIZE);</div><div class='ctx'> 		res = -EIO;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		res = 0;</div><div class='hunk'>@@ -404,6 +414,25 @@ static int amdgpu_ras_eeprom_correct_header_tag(</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	struct amdgpu_ras_eeprom_table_header *hdr = &amp;control-&gt;tbl_hdr;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(8, 10, 0):</div><div class='add'>+		hdr-&gt;version = RAS_TABLE_VER_V2_1;</div><div class='add'>+		return;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 5, 0):</div><div class='add'>+		hdr-&gt;version = RAS_TABLE_VER_V3;</div><div class='add'>+		return;</div><div class='add'>+	default:</div><div class='add'>+		hdr-&gt;version = RAS_TABLE_VER_V1;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table</div><div class='ctx'>  * @control: pointer to control structure</div><div class='hunk'>@@ -417,48 +446,64 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 	struct amdgpu_ras_eeprom_table_header *hdr = &amp;control-&gt;tbl_hdr;</div><div class='ctx'> 	struct amdgpu_ras_eeprom_table_ras_info *rai = &amp;control-&gt;tbl_rai;</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	u32 erase_res = 0;</div><div class='ctx'> 	u8 csum;</div><div class='ctx'> 	int res;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;control-&gt;ras_tbl_mutex);</div><div class='ctx'> </div><div class='del'>-	hdr-&gt;header = RAS_TABLE_HDR_VAL;</div><div class='del'>-	if (adev-&gt;umc.ras &amp;&amp;</div><div class='del'>-	    adev-&gt;umc.ras-&gt;set_eeprom_table_version)</div><div class='del'>-		adev-&gt;umc.ras-&gt;set_eeprom_table_version(hdr);</div><div class='del'>-	else</div><div class='del'>-		hdr-&gt;version = RAS_TABLE_VER_V1;</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev)) {</div><div class='add'>+		hdr-&gt;header = RAS_TABLE_HDR_VAL;</div><div class='add'>+		amdgpu_ras_set_eeprom_table_version(control);</div><div class='add'>+</div><div class='add'>+		if (hdr-&gt;version &gt;= RAS_TABLE_VER_V2_1) {</div><div class='add'>+			hdr-&gt;first_rec_offset = RAS_RECORD_START_V2_1;</div><div class='add'>+			hdr-&gt;tbl_size = RAS_TABLE_HEADER_SIZE +</div><div class='add'>+					RAS_TABLE_V2_1_INFO_SIZE;</div><div class='add'>+			rai-&gt;rma_status = GPU_HEALTH_USABLE;</div><div class='add'>+</div><div class='add'>+			control-&gt;ras_record_offset = RAS_RECORD_START_V2_1;</div><div class='add'>+			control-&gt;ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;</div><div class='add'>+			/**</div><div class='add'>+			 * GPU health represented as a percentage.</div><div class='add'>+			 * 0 means worst health, 100 means fully health.</div><div class='add'>+			 */</div><div class='add'>+			rai-&gt;health_percent = 100;</div><div class='add'>+			/* ecc_page_threshold = 0 means disable bad page retirement */</div><div class='add'>+			rai-&gt;ecc_page_threshold = con-&gt;bad_page_cnt_threshold;</div><div class='add'>+		} else {</div><div class='add'>+			hdr-&gt;first_rec_offset = RAS_RECORD_START;</div><div class='add'>+			hdr-&gt;tbl_size = RAS_TABLE_HEADER_SIZE;</div><div class='ctx'> </div><div class='del'>-	if (hdr-&gt;version == RAS_TABLE_VER_V2_1) {</div><div class='del'>-		hdr-&gt;first_rec_offset = RAS_RECORD_START_V2_1;</div><div class='del'>-		hdr-&gt;tbl_size = RAS_TABLE_HEADER_SIZE +</div><div class='del'>-				RAS_TABLE_V2_1_INFO_SIZE;</div><div class='del'>-		rai-&gt;rma_status = GPU_HEALTH_USABLE;</div><div class='del'>-		/**</div><div class='del'>-		 * GPU health represented as a percentage.</div><div class='del'>-		 * 0 means worst health, 100 means fully health.</div><div class='del'>-		 */</div><div class='del'>-		rai-&gt;health_percent = 100;</div><div class='del'>-		/* ecc_page_threshold = 0 means disable bad page retirement */</div><div class='del'>-		rai-&gt;ecc_page_threshold = con-&gt;bad_page_cnt_threshold;</div><div class='add'>+			control-&gt;ras_record_offset = RAS_RECORD_START;</div><div class='add'>+			control-&gt;ras_max_record_count = RAS_MAX_RECORD_COUNT;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		csum = __calc_hdr_byte_sum(control);</div><div class='add'>+		if (hdr-&gt;version &gt;= RAS_TABLE_VER_V2_1)</div><div class='add'>+			csum += __calc_ras_info_byte_sum(control);</div><div class='add'>+		csum = -csum;</div><div class='add'>+		hdr-&gt;checksum = csum;</div><div class='add'>+		res = __write_table_header(control);</div><div class='add'>+		if (!res &amp;&amp; hdr-&gt;version &gt; RAS_TABLE_VER_V1)</div><div class='add'>+			res = __write_table_ras_info(control);</div><div class='ctx'> 	} else {</div><div class='del'>-		hdr-&gt;first_rec_offset = RAS_RECORD_START;</div><div class='del'>-		hdr-&gt;tbl_size = RAS_TABLE_HEADER_SIZE;</div><div class='add'>+		res = amdgpu_ras_smu_erase_ras_table(adev, &amp;erase_res);</div><div class='add'>+		if (res || erase_res) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "RAS EEPROM reset failed, res:%d result:%d",</div><div class='add'>+										res, erase_res);</div><div class='add'>+			if (!res)</div><div class='add'>+				res = -EIO;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	csum = __calc_hdr_byte_sum(control);</div><div class='del'>-	if (hdr-&gt;version == RAS_TABLE_VER_V2_1)</div><div class='del'>-		csum += __calc_ras_info_byte_sum(control);</div><div class='del'>-	csum = -csum;</div><div class='del'>-	hdr-&gt;checksum = csum;</div><div class='del'>-	res = __write_table_header(control);</div><div class='del'>-	if (!res &amp;&amp; hdr-&gt;version &gt; RAS_TABLE_VER_V1)</div><div class='del'>-		res = __write_table_ras_info(control);</div><div class='del'>-</div><div class='ctx'> 	control-&gt;ras_num_recs = 0;</div><div class='add'>+	control-&gt;ras_num_bad_pages = 0;</div><div class='add'>+	control-&gt;ras_num_mca_recs = 0;</div><div class='add'>+	control-&gt;ras_num_pa_recs = 0;</div><div class='ctx'> 	control-&gt;ras_fri = 0;</div><div class='ctx'> </div><div class='del'>-	amdgpu_dpm_send_hbm_bad_pages_num(adev, control-&gt;ras_num_recs);</div><div class='add'>+	amdgpu_dpm_send_hbm_bad_pages_num(adev, control-&gt;ras_num_bad_pages);</div><div class='ctx'> </div><div class='ctx'> 	control-&gt;bad_channel_bitmap = 0;</div><div class='ctx'> 	amdgpu_dpm_send_hbm_bad_channel_flag(adev, control-&gt;bad_channel_bitmap);</div><div class='hunk'>@@ -531,6 +576,9 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_uniras_enabled(adev))</div><div class='add'>+		return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev);</div><div class='add'>+</div><div class='ctx'> 	if (!__is_ras_eeprom_supported(adev) ||</div><div class='ctx'> 	    !amdgpu_bad_page_threshold)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -543,16 +591,17 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)</div><div class='ctx'> 			return false;</div><div class='ctx'> </div><div class='ctx'> 	if (con-&gt;eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {</div><div class='del'>-		if (amdgpu_bad_page_threshold == -1) {</div><div class='add'>+		if (con-&gt;eeprom_control.ras_num_bad_pages &gt; con-&gt;bad_page_cnt_threshold)</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "RAS records:%d exceed threshold:%d",</div><div class='del'>-				con-&gt;eeprom_control.ras_num_recs, con-&gt;bad_page_cnt_threshold);</div><div class='add'>+				 con-&gt;eeprom_control.ras_num_bad_pages, con-&gt;bad_page_cnt_threshold);</div><div class='add'>+		if ((amdgpu_bad_page_threshold == -1) ||</div><div class='add'>+		    (amdgpu_bad_page_threshold == -2)) {</div><div class='ctx'> 			dev_warn(adev-&gt;dev,</div><div class='del'>-				"But GPU can be operated due to bad_page_threshold = -1.\n");</div><div class='add'>+				 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n");</div><div class='ctx'> 			return false;</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_warn(adev-&gt;dev, "This GPU is in BAD status.");</div><div class='del'>-			dev_warn(adev-&gt;dev, "Please retire it or set a larger "</div><div class='del'>-				 "threshold value when reloading driver.\n");</div><div class='add'>+			dev_warn(adev-&gt;dev,</div><div class='add'>+				 "Please consider adjusting the customized threshold.\n");</div><div class='ctx'> 			return true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -586,13 +635,13 @@ static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 				  buf, buf_size);</div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	if (res &lt; 0) {</div><div class='del'>-		DRM_ERROR("Writing %d EEPROM table records error:%d",</div><div class='del'>-			  num, res);</div><div class='add'>+		dev_err(adev-&gt;dev, "Writing %d EEPROM table records error:%d",</div><div class='add'>+			num, res);</div><div class='ctx'> 	} else if (res &lt; buf_size) {</div><div class='ctx'> 		/* Short write, return error.</div><div class='ctx'> 		 */</div><div class='del'>-		DRM_ERROR("Wrote %d records out of %d",</div><div class='del'>-			  res / RAS_TABLE_RECORD_SIZE, num);</div><div class='add'>+		dev_err(adev-&gt;dev, "Wrote %d records out of %d",</div><div class='add'>+			res / RAS_TABLE_RECORD_SIZE, num);</div><div class='ctx'> 		res = -EIO;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		res = 0;</div><div class='hunk'>@@ -607,6 +656,7 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 			       const u32 num)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='ctx'> 	u32 a, b, i;</div><div class='ctx'> 	u8 *buf, *pp;</div><div class='ctx'> 	int res;</div><div class='hunk'>@@ -709,6 +759,14 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 	control-&gt;ras_num_recs = 1 + (control-&gt;ras_max_record_count + b</div><div class='ctx'> 				     - control-&gt;ras_fri)</div><div class='ctx'> 		% control-&gt;ras_max_record_count;</div><div class='add'>+</div><div class='add'>+	/*old asics only save pa to eeprom like before*/</div><div class='add'>+	if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) &lt; 12)</div><div class='add'>+		control-&gt;ras_num_pa_recs += num;</div><div class='add'>+	else</div><div class='add'>+		control-&gt;ras_num_mca_recs += num;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_num_bad_pages = con-&gt;bad_page_num;</div><div class='ctx'> Out:</div><div class='ctx'> 	kfree(buf);</div><div class='ctx'> 	return res;</div><div class='hunk'>@@ -726,21 +784,30 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 	/* Modify the header if it exceeds.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_bad_page_threshold != 0 &amp;&amp;</div><div class='del'>-	    control-&gt;ras_num_recs &gt;= ras-&gt;bad_page_cnt_threshold) {</div><div class='add'>+	    control-&gt;ras_num_bad_pages &gt; ras-&gt;bad_page_cnt_threshold) {</div><div class='ctx'> 		dev_warn(adev-&gt;dev,</div><div class='ctx'> 			"Saved bad pages %d reaches threshold value %d\n",</div><div class='del'>-			control-&gt;ras_num_recs, ras-&gt;bad_page_cnt_threshold);</div><div class='del'>-		control-&gt;tbl_hdr.header = RAS_TABLE_HDR_BAD;</div><div class='del'>-		if (control-&gt;tbl_hdr.version == RAS_TABLE_VER_V2_1) {</div><div class='del'>-			control-&gt;tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;</div><div class='del'>-			control-&gt;tbl_rai.health_percent = 0;</div><div class='add'>+			control-&gt;ras_num_bad_pages, ras-&gt;bad_page_cnt_threshold);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cper.enabled &amp;&amp; !amdgpu_uniras_enabled(adev) &amp;&amp;</div><div class='add'>+		    amdgpu_cper_generate_bp_threshold_record(adev))</div><div class='add'>+			dev_warn(adev-&gt;dev, "fail to generate bad page threshold cper records\n");</div><div class='add'>+</div><div class='add'>+		if ((amdgpu_bad_page_threshold != -1) &amp;&amp;</div><div class='add'>+		    (amdgpu_bad_page_threshold != -2)) {</div><div class='add'>+			control-&gt;tbl_hdr.header = RAS_TABLE_HDR_BAD;</div><div class='add'>+			if (control-&gt;tbl_hdr.version &gt;= RAS_TABLE_VER_V2_1) {</div><div class='add'>+				control-&gt;tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;</div><div class='add'>+				control-&gt;tbl_rai.health_percent = 0;</div><div class='add'>+			}</div><div class='add'>+			ras-&gt;is_rma = true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* ignore the -ENOTSUPP return value */</div><div class='ctx'> 		amdgpu_dpm_send_rma_reason(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (control-&gt;tbl_hdr.version == RAS_TABLE_VER_V2_1)</div><div class='add'>+	if (control-&gt;tbl_hdr.version &gt;= RAS_TABLE_VER_V2_1)</div><div class='ctx'> 		control-&gt;tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +</div><div class='ctx'> 					    RAS_TABLE_V2_1_INFO_SIZE +</div><div class='ctx'> 					    control-&gt;ras_num_recs * RAS_TABLE_RECORD_SIZE;</div><div class='hunk'>@@ -752,8 +819,9 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 	buf_size = control-&gt;ras_num_recs * RAS_TABLE_RECORD_SIZE;</div><div class='ctx'> 	buf = kcalloc(control-&gt;ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);</div><div class='ctx'> 	if (!buf) {</div><div class='del'>-		DRM_ERROR("allocating memory for table of size %d bytes failed\n",</div><div class='del'>-			  control-&gt;tbl_hdr.tbl_size);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"allocating memory for table of size %d bytes failed\n",</div><div class='add'>+			control-&gt;tbl_hdr.tbl_size);</div><div class='ctx'> 		res = -ENOMEM;</div><div class='ctx'> 		goto Out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -765,12 +833,11 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 				 buf, buf_size);</div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	if (res &lt; 0) {</div><div class='del'>-		DRM_ERROR("EEPROM failed reading records:%d\n",</div><div class='del'>-			  res);</div><div class='add'>+		dev_err(adev-&gt;dev, "EEPROM failed reading records:%d\n", res);</div><div class='ctx'> 		goto Out;</div><div class='ctx'> 	} else if (res &lt; buf_size) {</div><div class='del'>-		DRM_ERROR("EEPROM read %d out of %d bytes\n",</div><div class='del'>-			  res, buf_size);</div><div class='add'>+		dev_err(adev-&gt;dev, "EEPROM read %d out of %d bytes\n", res,</div><div class='add'>+			buf_size);</div><div class='ctx'> 		res = -EIO;</div><div class='ctx'> 		goto Out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -780,10 +847,10 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 	 * now calculate gpu health percent</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_bad_page_threshold != 0 &amp;&amp;</div><div class='del'>-	    control-&gt;tbl_hdr.version == RAS_TABLE_VER_V2_1 &amp;&amp;</div><div class='del'>-	    control-&gt;ras_num_recs &lt; ras-&gt;bad_page_cnt_threshold)</div><div class='add'>+	    control-&gt;tbl_hdr.version &gt;= RAS_TABLE_VER_V2_1 &amp;&amp;</div><div class='add'>+	    control-&gt;ras_num_bad_pages &lt;= ras-&gt;bad_page_cnt_threshold)</div><div class='ctx'> 		control-&gt;tbl_rai.health_percent = ((ras-&gt;bad_page_cnt_threshold -</div><div class='del'>-						   control-&gt;ras_num_recs) * 100) /</div><div class='add'>+						   control-&gt;ras_num_bad_pages) * 100) /</div><div class='ctx'> 						   ras-&gt;bad_page_cnt_threshold;</div><div class='ctx'> </div><div class='ctx'> 	/* Recalc the checksum.</div><div class='hunk'>@@ -793,7 +860,7 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 		csum += *pp;</div><div class='ctx'> </div><div class='ctx'> 	csum += __calc_hdr_byte_sum(control);</div><div class='del'>-	if (control-&gt;tbl_hdr.version == RAS_TABLE_VER_V2_1)</div><div class='add'>+	if (control-&gt;tbl_hdr.version &gt;= RAS_TABLE_VER_V2_1)</div><div class='ctx'> 		csum += __calc_ras_info_byte_sum(control);</div><div class='ctx'> 	/* avoid sign extension when assigning to "checksum" */</div><div class='ctx'> 	csum = -csum;</div><div class='hunk'>@@ -806,6 +873,71 @@ Out:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	int ret, retry = 20;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_num_recs_old = control-&gt;ras_num_recs;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		/* 1000ms timeout is long enough, smu_get_badpage_count won't</div><div class='add'>+		 * return -EBUSY before timeout.</div><div class='add'>+		 */</div><div class='add'>+		ret = amdgpu_ras_smu_get_badpage_count(adev,</div><div class='add'>+			&amp;(control-&gt;ras_num_recs), RAS_SMU_MESSAGE_TIMEOUT_MS);</div><div class='add'>+		if (!ret &amp;&amp;</div><div class='add'>+		    (control-&gt;ras_num_recs_old == control-&gt;ras_num_recs)) {</div><div class='add'>+			/* record number update in PMFW needs some time,</div><div class='add'>+			 * smu_get_badpage_count may return immediately without</div><div class='add'>+			 * count update, sleep for a while and retry again.</div><div class='add'>+			 */</div><div class='add'>+			msleep(50);</div><div class='add'>+			retry--;</div><div class='add'>+		} else {</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	} while (retry);</div><div class='add'>+</div><div class='add'>+	/* no update of record number is not a real failure,</div><div class='add'>+	 * don't print warning here</div><div class='add'>+	 */</div><div class='add'>+	if (!ret &amp;&amp; (control-&gt;ras_num_recs_old == control-&gt;ras_num_recs))</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_ras_smu_eeprom_append(struct amdgpu_ras_eeprom_control *control)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev) || !con)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_num_bad_pages = con-&gt;bad_page_num;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_bad_page_threshold != 0 &amp;&amp;</div><div class='add'>+	    control-&gt;ras_num_bad_pages &gt; con-&gt;bad_page_cnt_threshold) {</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			"Saved bad pages %d reaches threshold value %d\n",</div><div class='add'>+			control-&gt;ras_num_bad_pages, con-&gt;bad_page_cnt_threshold);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cper.enabled &amp;&amp; amdgpu_cper_generate_bp_threshold_record(adev))</div><div class='add'>+			dev_warn(adev-&gt;dev, "fail to generate bad page threshold cper records\n");</div><div class='add'>+</div><div class='add'>+		if ((amdgpu_bad_page_threshold != -1) &amp;&amp;</div><div class='add'>+		    (amdgpu_bad_page_threshold != -2))</div><div class='add'>+			con-&gt;is_rma = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table</div><div class='ctx'>  * @control: pointer to control structure</div><div class='hunk'>@@ -824,20 +956,32 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 			     const u32 num)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='del'>-	int res;</div><div class='add'>+	int res, i;</div><div class='add'>+	uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;</div><div class='ctx'> </div><div class='ctx'> 	if (!__is_ras_eeprom_supported(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return amdgpu_ras_smu_eeprom_append(control);</div><div class='add'>+</div><div class='ctx'> 	if (num == 0) {</div><div class='del'>-		DRM_ERROR("will not append 0 records\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "will not append 0 records\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	} else if (num &gt; control-&gt;ras_max_record_count) {</div><div class='del'>-		DRM_ERROR("cannot append %d records than the size of table %d\n",</div><div class='del'>-			  num, control-&gt;ras_max_record_count);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"cannot append %d records than the size of table %d\n",</div><div class='add'>+			num, control-&gt;ras_max_record_count);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode)</div><div class='add'>+		nps = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='add'>+</div><div class='add'>+	/* set the new channel index flag */</div><div class='add'>+	for (i = 0; i &lt; num; i++)</div><div class='add'>+		record[i].retired_page |= (nps &lt;&lt; UMC_NPS_SHIFT);</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;control-&gt;ras_tbl_mutex);</div><div class='ctx'> </div><div class='ctx'> 	res = amdgpu_ras_eeprom_append_table(control, record, num);</div><div class='hunk'>@@ -847,6 +991,11 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 		amdgpu_ras_debugfs_set_ret_size(control);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;control-&gt;ras_tbl_mutex);</div><div class='add'>+</div><div class='add'>+	/* clear channel index flag, the flag is only saved on eeprom */</div><div class='add'>+	for (i = 0; i &lt; num; i++)</div><div class='add'>+		record[i].retired_page &amp;= ~(nps &lt;&lt; UMC_NPS_SHIFT);</div><div class='add'>+</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -876,13 +1025,13 @@ static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 				 buf, buf_size);</div><div class='ctx'> 	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	if (res &lt; 0) {</div><div class='del'>-		DRM_ERROR("Reading %d EEPROM table records error:%d",</div><div class='del'>-			  num, res);</div><div class='add'>+		dev_err(adev-&gt;dev, "Reading %d EEPROM table records error:%d",</div><div class='add'>+			num, res);</div><div class='ctx'> 	} else if (res &lt; buf_size) {</div><div class='ctx'> 		/* Short read, return error.</div><div class='ctx'> 		 */</div><div class='del'>-		DRM_ERROR("Read %d records out of %d",</div><div class='del'>-			  res / RAS_TABLE_RECORD_SIZE, num);</div><div class='add'>+		dev_err(adev-&gt;dev, "Read %d records out of %d",</div><div class='add'>+			res / RAS_TABLE_RECORD_SIZE, num);</div><div class='ctx'> 		res = -EIO;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		res = 0;</div><div class='hunk'>@@ -891,6 +1040,50 @@ static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control,</div><div class='add'>+			struct eeprom_table_record *record, u32 rec_idx,</div><div class='add'>+			const u32 num)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	uint64_t ts, end_idx;</div><div class='add'>+	int i, ret;</div><div class='add'>+	u64 mca, ipid;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;umc.ras || !adev-&gt;umc.ras-&gt;mca_ipid_parse)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	end_idx = rec_idx + num;</div><div class='add'>+	for (i = rec_idx; i &lt; end_idx; i++) {</div><div class='add'>+		ret = amdgpu_ras_smu_get_badpage_mca_addr(adev, i, &amp;mca);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_ras_smu_get_badpage_ipid(adev, i, &amp;ipid);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_ras_smu_get_timestamp(adev, i, &amp;ts);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		record[i - rec_idx].address = mca;</div><div class='add'>+		/* retired_page (pa) is unused now */</div><div class='add'>+		record[i - rec_idx].retired_page = 0x1ULL;</div><div class='add'>+		record[i - rec_idx].ts = ts;</div><div class='add'>+		record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;</div><div class='add'>+</div><div class='add'>+		adev-&gt;umc.ras-&gt;mca_ipid_parse(adev, ipid,</div><div class='add'>+			(uint32_t *)&amp;(record[i - rec_idx].cu),</div><div class='add'>+			(uint32_t *)&amp;(record[i - rec_idx].mem_channel),</div><div class='add'>+			(uint32_t *)&amp;(record[i - rec_idx].mcumc_id), NULL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_ras_eeprom_read -- read EEPROM</div><div class='ctx'>  * @control: pointer to control structure</div><div class='hunk'>@@ -912,15 +1105,18 @@ int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 	u8 *buf, *pp;</div><div class='ctx'> 	u32 g0, g1;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return amdgpu_ras_eeprom_read_idx(control, record, 0, num);</div><div class='add'>+</div><div class='ctx'> 	if (!__is_ras_eeprom_supported(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (num == 0) {</div><div class='del'>-		DRM_ERROR("will not read 0 records\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "will not read 0 records\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	} else if (num &gt; control-&gt;ras_num_recs) {</div><div class='del'>-		DRM_ERROR("too many records to read:%d available:%d\n",</div><div class='del'>-			  num, control-&gt;ras_num_recs);</div><div class='add'>+		dev_err(adev-&gt;dev, "too many records to read:%d available:%d\n",</div><div class='add'>+			num, control-&gt;ras_num_recs);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -994,7 +1190,10 @@ Out:</div><div class='ctx'> </div><div class='ctx'> uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> {</div><div class='del'>-	if (control-&gt;tbl_hdr.version == RAS_TABLE_VER_V2_1)</div><div class='add'>+	/* get available eeprom table version first before eeprom table init */</div><div class='add'>+	amdgpu_ras_set_eeprom_table_version(control);</div><div class='add'>+</div><div class='add'>+	if (control-&gt;tbl_hdr.version &gt;= RAS_TABLE_VER_V2_1)</div><div class='ctx'> 		return RAS_MAX_RECORD_COUNT_V2_1;</div><div class='ctx'> 	else</div><div class='ctx'> 		return RAS_MAX_RECORD_COUNT;</div><div class='hunk'>@@ -1080,6 +1279,10 @@ static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,</div><div class='ctx'> 	int res = -EFAULT;</div><div class='ctx'> 	size_t data_len;</div><div class='ctx'> </div><div class='add'>+	/* pmfw manages eeprom data by itself */</div><div class='add'>+	if (amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;control-&gt;ras_tbl_mutex);</div><div class='ctx'> </div><div class='ctx'> 	/* We want *pos - data_len &gt; 0, which means there's</div><div class='hunk'>@@ -1239,7 +1442,7 @@ static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control</div><div class='ctx'> 	int buf_size, res;</div><div class='ctx'> 	u8  csum, *buf, *pp;</div><div class='ctx'> </div><div class='del'>-	if (control-&gt;tbl_hdr.version == RAS_TABLE_VER_V2_1)</div><div class='add'>+	if (control-&gt;tbl_hdr.version &gt;= RAS_TABLE_VER_V2_1)</div><div class='ctx'> 		buf_size = RAS_TABLE_HEADER_SIZE +</div><div class='ctx'> 			   RAS_TABLE_V2_1_INFO_SIZE +</div><div class='ctx'> 			   control-&gt;ras_num_recs * RAS_TABLE_RECORD_SIZE;</div><div class='hunk'>@@ -1249,7 +1452,8 @@ static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control</div><div class='ctx'> </div><div class='ctx'> 	buf = kzalloc(buf_size, GFP_KERNEL);</div><div class='ctx'> 	if (!buf) {</div><div class='del'>-		DRM_ERROR("Out of memory checking RAS table checksum.\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Out of memory checking RAS table checksum.\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1258,7 +1462,7 @@ static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control</div><div class='ctx'> 				 control-&gt;ras_header_offset,</div><div class='ctx'> 				 buf, buf_size);</div><div class='ctx'> 	if (res &lt; buf_size) {</div><div class='del'>-		DRM_ERROR("Partial read for checksum, res:%d\n", res);</div><div class='add'>+		dev_err(adev-&gt;dev, "Partial read for checksum, res:%d\n", res);</div><div class='ctx'> 		/* On partial reads, return -EIO.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (res &gt;= 0)</div><div class='hunk'>@@ -1283,7 +1487,8 @@ static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> </div><div class='ctx'> 	buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);</div><div class='ctx'> 	if (!buf) {</div><div class='del'>-		DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Failed to alloc buf to read EEPROM table ras info\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1295,7 +1500,8 @@ static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> 				 control-&gt;i2c_address + control-&gt;ras_info_offset,</div><div class='ctx'> 				 buf, RAS_TABLE_V2_1_INFO_SIZE);</div><div class='ctx'> 	if (res &lt; RAS_TABLE_V2_1_INFO_SIZE) {</div><div class='del'>-		DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Failed to read EEPROM table ras info, res:%d", res);</div><div class='ctx'> 		res = res &gt;= 0 ? -EIO : res;</div><div class='ctx'> 		goto Out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1307,8 +1513,43 @@ Out:</div><div class='ctx'> 	return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,</div><div class='del'>-			   bool *exceed_err_limit)</div><div class='add'>+static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	struct amdgpu_ras_eeprom_table_header *hdr = &amp;control-&gt;tbl_hdr;</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	uint64_t local_time;</div><div class='add'>+	int res;</div><div class='add'>+</div><div class='add'>+	ras-&gt;is_rma = false;</div><div class='add'>+</div><div class='add'>+	if (!__is_ras_eeprom_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+	mutex_init(&amp;control-&gt;ras_tbl_mutex);</div><div class='add'>+</div><div class='add'>+	res = amdgpu_ras_smu_get_table_version(adev, &amp;(hdr-&gt;version));</div><div class='add'>+	if (res)</div><div class='add'>+		return res;</div><div class='add'>+</div><div class='add'>+	res = amdgpu_ras_smu_get_badpage_count(adev,</div><div class='add'>+								&amp;(control-&gt;ras_num_recs), 100);</div><div class='add'>+	if (res)</div><div class='add'>+		return res;</div><div class='add'>+</div><div class='add'>+	local_time = (uint64_t)ktime_get_real_seconds();</div><div class='add'>+	res = amdgpu_ras_smu_set_timestamp(adev, local_time);</div><div class='add'>+	if (res)</div><div class='add'>+		return res;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_max_record_count = 4000;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_num_mca_recs = 0;</div><div class='add'>+	control-&gt;ras_num_pa_recs = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='ctx'> 	unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };</div><div class='hunk'>@@ -1316,7 +1557,10 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> 	int res;</div><div class='ctx'> </div><div class='del'>-	*exceed_err_limit = false;</div><div class='add'>+	if (amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return amdgpu_ras_smu_eeprom_init(control);</div><div class='add'>+</div><div class='add'>+	ras-&gt;is_rma = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!__is_ras_eeprom_supported(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1337,28 +1581,120 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 				 control-&gt;i2c_address + control-&gt;ras_header_offset,</div><div class='ctx'> 				 buf, RAS_TABLE_HEADER_SIZE);</div><div class='ctx'> 	if (res &lt; RAS_TABLE_HEADER_SIZE) {</div><div class='del'>-		DRM_ERROR("Failed to read EEPROM table header, res:%d", res);</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to read EEPROM table header, res:%d",</div><div class='add'>+			res);</div><div class='ctx'> 		return res &gt;= 0 ? -EIO : res;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	__decode_table_header_from_buf(hdr, buf);</div><div class='ctx'> </div><div class='del'>-	if (hdr-&gt;version == RAS_TABLE_VER_V2_1) {</div><div class='add'>+	if (hdr-&gt;header != RAS_TABLE_HDR_VAL &amp;&amp;</div><div class='add'>+	    hdr-&gt;header != RAS_TABLE_HDR_BAD) {</div><div class='add'>+		dev_info(adev-&gt;dev, "Creating a new EEPROM table");</div><div class='add'>+		return amdgpu_ras_eeprom_reset_table(control);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (hdr-&gt;version) {</div><div class='add'>+	case RAS_TABLE_VER_V2_1:</div><div class='add'>+	case RAS_TABLE_VER_V3:</div><div class='ctx'> 		control-&gt;ras_num_recs = RAS_NUM_RECS_V2_1(hdr);</div><div class='ctx'> 		control-&gt;ras_record_offset = RAS_RECORD_START_V2_1;</div><div class='ctx'> 		control-&gt;ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;</div><div class='del'>-	} else {</div><div class='add'>+		break;</div><div class='add'>+	case RAS_TABLE_VER_V1:</div><div class='ctx'> 		control-&gt;ras_num_recs = RAS_NUM_RECS(hdr);</div><div class='ctx'> 		control-&gt;ras_record_offset = RAS_RECORD_START;</div><div class='ctx'> 		control-&gt;ras_max_record_count = RAS_MAX_RECORD_COUNT;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"RAS header invalid, unsupported version: %u",</div><div class='add'>+			hdr-&gt;version);</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (control-&gt;ras_num_recs &gt; control-&gt;ras_max_record_count) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"RAS header invalid, records in header: %u max allowed :%u",</div><div class='add'>+			control-&gt;ras_num_recs, control-&gt;ras_max_record_count);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	control-&gt;ras_fri = RAS_OFFSET_TO_INDEX(control, hdr-&gt;first_rec_offset);</div><div class='add'>+	control-&gt;ras_num_mca_recs = 0;</div><div class='add'>+	control-&gt;ras_num_pa_recs = 0;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	if (!__is_ras_eeprom_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_num_bad_pages = ras-&gt;bad_page_num;</div><div class='add'>+</div><div class='add'>+	if ((ras-&gt;bad_page_cnt_threshold &lt; control-&gt;ras_num_bad_pages) &amp;&amp;</div><div class='add'>+	    amdgpu_bad_page_threshold != 0) {</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			"RAS records:%d exceed threshold:%d\n",</div><div class='add'>+			control-&gt;ras_num_bad_pages, ras-&gt;bad_page_cnt_threshold);</div><div class='add'>+		if ((amdgpu_bad_page_threshold == -1) ||</div><div class='add'>+			(amdgpu_bad_page_threshold == -2)) {</div><div class='add'>+			dev_warn(adev-&gt;dev,</div><div class='add'>+				 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n");</div><div class='add'>+		} else {</div><div class='add'>+			ras-&gt;is_rma = true;</div><div class='add'>+			dev_warn(adev-&gt;dev,</div><div class='add'>+				 "User defined threshold is set, runtime service will be halt when threshold is reached\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(adev-&gt;dev,</div><div class='add'>+		"Found existing EEPROM table with %d records",</div><div class='add'>+		control-&gt;ras_num_bad_pages);</div><div class='add'>+</div><div class='add'>+	/* Warn if we are at 90% of the threshold or above</div><div class='add'>+	 */</div><div class='add'>+	if (10 * control-&gt;ras_num_bad_pages &gt;= 9 * ras-&gt;bad_page_cnt_threshold)</div><div class='add'>+		dev_warn(adev-&gt;dev, "RAS records:%u exceeds 90%% of threshold:%d",</div><div class='add'>+				control-&gt;ras_num_bad_pages,</div><div class='add'>+				ras-&gt;bad_page_cnt_threshold);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = to_amdgpu_device(control);</div><div class='add'>+	struct amdgpu_ras_eeprom_table_header *hdr = &amp;control-&gt;tbl_hdr;</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	int res = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return amdgpu_ras_smu_eeprom_check(control);</div><div class='add'>+</div><div class='add'>+	if (!__is_ras_eeprom_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Verify i2c adapter is initialized */</div><div class='add'>+	if (!adev-&gt;pm.ras_eeprom_i2c_bus || !adev-&gt;pm.ras_eeprom_i2c_bus-&gt;algo)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (!__get_eeprom_i2c_addr(adev, control))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	control-&gt;ras_num_bad_pages = ras-&gt;bad_page_num;</div><div class='ctx'> </div><div class='ctx'> 	if (hdr-&gt;header == RAS_TABLE_HDR_VAL) {</div><div class='del'>-		DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",</div><div class='del'>-				 control-&gt;ras_num_recs);</div><div class='add'>+		dev_dbg(adev-&gt;dev,</div><div class='add'>+			"Found existing EEPROM table with %d records",</div><div class='add'>+			control-&gt;ras_num_bad_pages);</div><div class='ctx'> </div><div class='del'>-		if (hdr-&gt;version == RAS_TABLE_VER_V2_1) {</div><div class='add'>+		if (hdr-&gt;version &gt;= RAS_TABLE_VER_V2_1) {</div><div class='ctx'> 			res = __read_table_ras_info(control);</div><div class='ctx'> 			if (res)</div><div class='ctx'> 				return res;</div><div class='hunk'>@@ -1366,28 +1702,32 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> </div><div class='ctx'> 		res = __verify_ras_table_checksum(control);</div><div class='ctx'> 		if (res)</div><div class='del'>-			DRM_ERROR("RAS table incorrect checksum or error:%d\n",</div><div class='del'>-				  res);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"RAS table incorrect checksum or error:%d\n",</div><div class='add'>+				res);</div><div class='ctx'> </div><div class='ctx'> 		/* Warn if we are at 90% of the threshold or above</div><div class='ctx'> 		 */</div><div class='del'>-		if (10 * control-&gt;ras_num_recs &gt;= 9 * ras-&gt;bad_page_cnt_threshold)</div><div class='add'>+		if (10 * control-&gt;ras_num_bad_pages &gt;= 9 * ras-&gt;bad_page_cnt_threshold)</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "RAS records:%u exceeds 90%% of threshold:%d",</div><div class='del'>-					control-&gt;ras_num_recs,</div><div class='add'>+					control-&gt;ras_num_bad_pages,</div><div class='ctx'> 					ras-&gt;bad_page_cnt_threshold);</div><div class='ctx'> 	} else if (hdr-&gt;header == RAS_TABLE_HDR_BAD &amp;&amp;</div><div class='ctx'> 		   amdgpu_bad_page_threshold != 0) {</div><div class='del'>-		if (hdr-&gt;version == RAS_TABLE_VER_V2_1) {</div><div class='add'>+		if (hdr-&gt;version &gt;= RAS_TABLE_VER_V2_1) {</div><div class='ctx'> 			res = __read_table_ras_info(control);</div><div class='ctx'> 			if (res)</div><div class='ctx'> 				return res;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		res = __verify_ras_table_checksum(control);</div><div class='del'>-		if (res)</div><div class='del'>-			DRM_ERROR("RAS Table incorrect checksum or error:%d\n",</div><div class='del'>-				  res);</div><div class='del'>-		if (ras-&gt;bad_page_cnt_threshold &gt; control-&gt;ras_num_recs) {</div><div class='add'>+		if (res) {</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"RAS Table incorrect checksum or error:%d\n",</div><div class='add'>+				res);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		if (ras-&gt;bad_page_cnt_threshold &gt;= control-&gt;ras_num_bad_pages) {</div><div class='ctx'> 			/* This means that, the threshold was increased since</div><div class='ctx'> 			 * the last time the system was booted, and now,</div><div class='ctx'> 			 * ras-&gt;bad_page_cnt_threshold - control-&gt;num_recs &gt; 0,</div><div class='hunk'>@@ -1397,29 +1737,194 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,</div><div class='ctx'> 			dev_info(adev-&gt;dev,</div><div class='ctx'> 				 "records:%d threshold:%d, resetting "</div><div class='ctx'> 				 "RAS table header signature",</div><div class='del'>-				 control-&gt;ras_num_recs,</div><div class='add'>+				 control-&gt;ras_num_bad_pages,</div><div class='ctx'> 				 ras-&gt;bad_page_cnt_threshold);</div><div class='ctx'> 			res = amdgpu_ras_eeprom_correct_header_tag(control,</div><div class='ctx'> 								   RAS_TABLE_HDR_VAL);</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_err(adev-&gt;dev, "RAS records:%d exceed threshold:%d",</div><div class='del'>-				control-&gt;ras_num_recs, ras-&gt;bad_page_cnt_threshold);</div><div class='del'>-			if (amdgpu_bad_page_threshold == -1) {</div><div class='del'>-				dev_warn(adev-&gt;dev, "GPU will be initialized due to bad_page_threshold = -1.");</div><div class='add'>+			dev_warn(adev-&gt;dev,</div><div class='add'>+				"RAS records:%d exceed threshold:%d\n",</div><div class='add'>+				control-&gt;ras_num_bad_pages, ras-&gt;bad_page_cnt_threshold);</div><div class='add'>+			if ((amdgpu_bad_page_threshold == -1) ||</div><div class='add'>+			    (amdgpu_bad_page_threshold == -2)) {</div><div class='ctx'> 				res = 0;</div><div class='add'>+				dev_warn(adev-&gt;dev,</div><div class='add'>+					 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n");</div><div class='ctx'> 			} else {</div><div class='del'>-				*exceed_err_limit = true;</div><div class='del'>-				dev_err(adev-&gt;dev,</div><div class='del'>-					"RAS records:%d exceed threshold:%d, "</div><div class='del'>-					"GPU will not be initialized. Replace this GPU or increase the threshold",</div><div class='del'>-					control-&gt;ras_num_recs, ras-&gt;bad_page_cnt_threshold);</div><div class='add'>+				ras-&gt;is_rma = true;</div><div class='add'>+				dev_warn(adev-&gt;dev,</div><div class='add'>+					 "User defined threshold is set, runtime service will be halt when threshold is reached\n");</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-	} else {</div><div class='del'>-		DRM_INFO("Creating a new EEPROM table");</div><div class='del'>-</div><div class='del'>-		res = amdgpu_ras_eeprom_reset_table(control);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return res &lt; 0 ? res : 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_ras_eeprom_control *control;</div><div class='add'>+	int res;</div><div class='add'>+</div><div class='add'>+	if (!__is_ras_eeprom_supported(adev) || !ras ||</div><div class='add'>+	    amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return;</div><div class='add'>+	control = &amp;ras-&gt;eeprom_control;</div><div class='add'>+	if (!control-&gt;is_eeprom_valid)</div><div class='add'>+		return;</div><div class='add'>+	res = __verify_ras_table_checksum(control);</div><div class='add'>+	if (res) {</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			"RAS table incorrect checksum or error:%d, try to recover\n",</div><div class='add'>+			res);</div><div class='add'>+		if (!amdgpu_ras_eeprom_reset_table(control))</div><div class='add'>+			if (!amdgpu_ras_save_bad_pages(adev, NULL))</div><div class='add'>+				if (!__verify_ras_table_checksum(control)) {</div><div class='add'>+					dev_info(adev-&gt;dev, "RAS table recovery succeed\n");</div><div class='add'>+					return;</div><div class='add'>+				}</div><div class='add'>+		dev_err(adev-&gt;dev, "RAS table recovery failed\n");</div><div class='add'>+		control-&gt;is_eeprom_valid = false;</div><div class='add'>+	}</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct ras_smu_drv *amdgpu_ras_get_smu_ras_drv(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	if (!ras)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return ras-&gt;ras_smu_drv;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint64_t amdgpu_ras_smu_get_feature_flags(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *ras_smu_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+	uint64_t flags = 0ULL;</div><div class='add'>+</div><div class='add'>+	if (!ras_smu_drv)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (ras_smu_drv-&gt;ras_smu_feature_flags)</div><div class='add'>+		ras_smu_drv-&gt;ras_smu_feature_flags(adev, &amp;flags);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+	uint64_t flags = 0ULL;</div><div class='add'>+</div><div class='add'>+	if (!__is_ras_eeprom_supported(adev) || !smu_ras_drv)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!smu_ras_drv-&gt;smu_eeprom_funcs)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	flags = amdgpu_ras_smu_get_feature_flags(adev);</div><div class='add'>+</div><div class='add'>+	return !!(flags &amp; RAS_SMU_FEATURE_BIT__RAS_EEPROM);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev,</div><div class='add'>+				     uint32_t *table_version)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_ras_table_version)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_ras_table_version(adev,</div><div class='add'>+										 table_version);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev,</div><div class='add'>+				     uint32_t *count, uint32_t timeout)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_badpage_count)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_badpage_count(adev,</div><div class='add'>+									     count, timeout);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev,</div><div class='add'>+					uint16_t index, uint64_t *mca_addr)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_badpage_mca_addr)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_badpage_mca_addr(adev,</div><div class='add'>+										index, mca_addr);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev,</div><div class='add'>+				 uint64_t timestamp)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;set_timestamp)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;set_timestamp(adev,</div><div class='add'>+									 timestamp);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev,</div><div class='add'>+				 uint16_t index, uint64_t *timestamp)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_timestamp)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_timestamp(adev,</div><div class='add'>+									 index, timestamp);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev,</div><div class='add'>+				    uint16_t index, uint64_t *ipid)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_badpage_ipid)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;get_badpage_ipid(adev,</div><div class='add'>+									    index, ipid);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev,</div><div class='add'>+				   uint32_t *result)</div><div class='add'>+{</div><div class='add'>+	const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (smu_ras_drv-&gt;smu_eeprom_funcs-&gt;erase_ras_table)</div><div class='add'>+		return smu_ras_drv-&gt;smu_eeprom_funcs-&gt;erase_ras_table(adev,</div><div class='add'>+									   result);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h<br/>index 6dfd667f3013..2e5d63957e71 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> </div><div class='ctx'> #define RAS_TABLE_VER_V1           0x00010000</div><div class='ctx'> #define RAS_TABLE_VER_V2_1         0x00021000</div><div class='add'>+#define RAS_TABLE_VER_V3           0x00030000</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_device;</div><div class='ctx'> </div><div class='hunk'>@@ -81,6 +82,18 @@ struct amdgpu_ras_eeprom_control {</div><div class='ctx'> 	/* Number of records in the table.</div><div class='ctx'> 	 */</div><div class='ctx'> 	u32 ras_num_recs;</div><div class='add'>+	u32 ras_num_recs_old;</div><div class='add'>+</div><div class='add'>+	/* the bad page number is ras_num_recs or</div><div class='add'>+	 * ras_num_recs * umc.retire_unit</div><div class='add'>+	 */</div><div class='add'>+	u32 ras_num_bad_pages;</div><div class='add'>+</div><div class='add'>+	/* Number of records store mca address */</div><div class='add'>+	u32 ras_num_mca_recs;</div><div class='add'>+</div><div class='add'>+	/* Number of records store physical address */</div><div class='add'>+	u32 ras_num_pa_recs;</div><div class='ctx'> </div><div class='ctx'> 	/* First record index to read, 0-based.</div><div class='ctx'> 	 * Range is [0, num_recs-1]. This is</div><div class='hunk'>@@ -102,6 +115,8 @@ struct amdgpu_ras_eeprom_control {</div><div class='ctx'> 	/* Record channel info which occurred bad pages</div><div class='ctx'> 	 */</div><div class='ctx'> 	u32 bad_channel_bitmap;</div><div class='add'>+</div><div class='add'>+	bool is_eeprom_valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -129,8 +144,7 @@ struct eeprom_table_record {</div><div class='ctx'> 	unsigned char mcumc_id;</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='del'>-int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,</div><div class='del'>-			   bool *exceed_err_limit);</div><div class='add'>+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);</div><div class='ctx'> </div><div class='hunk'>@@ -146,6 +160,39 @@ uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *co</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);</div><div class='ctx'> </div><div class='add'>+int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control);</div><div class='add'>+</div><div class='add'>+void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev,</div><div class='add'>+							uint32_t *table_version);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev,</div><div class='add'>+								uint32_t *count, uint32_t timeout);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev,</div><div class='add'>+								uint16_t index, uint64_t *mca_addr);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev,</div><div class='add'>+										uint64_t timestamp);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev,</div><div class='add'>+							uint16_t index, uint64_t *timestamp);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev,</div><div class='add'>+								uint16_t index, uint64_t *ipid);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev,</div><div class='add'>+									uint32_t *result);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control,</div><div class='add'>+			struct eeprom_table_record *record, u32 rec_idx,</div><div class='add'>+			const u32 num);</div><div class='add'>+</div><div class='add'>+int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control);</div><div class='add'>+</div><div class='ctx'> extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;</div><div class='ctx'> extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h<br/>index 381101d2bf05..be2e56ce1355 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h</a></div><div class='hunk'>@@ -91,6 +91,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TTM_PL_TT:</div><div class='ctx'> 	case AMDGPU_PL_DOORBELL:</div><div class='add'>+	case AMDGPU_PL_MMIO_REMAP:</div><div class='ctx'> 		node = to_ttm_range_mgr_node(res)-&gt;mm_nodes;</div><div class='ctx'> 		while (start &gt;= node-&gt;size &lt;&lt; PAGE_SHIFT)</div><div class='ctx'> 			start -= node++-&gt;size &lt;&lt; PAGE_SHIFT;</div><div class='hunk'>@@ -153,6 +154,7 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TTM_PL_TT:</div><div class='ctx'> 	case AMDGPU_PL_DOORBELL:</div><div class='add'>+	case AMDGPU_PL_MMIO_REMAP:</div><div class='ctx'> 		node = cur-&gt;node;</div><div class='ctx'> </div><div class='ctx'> 		cur-&gt;node = ++node;</div><div class='hunk'>@@ -164,4 +166,29 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_res_cleared - check if blocks are cleared</div><div class='add'>+ *</div><div class='add'>+ * @cur: the cursor to extract the block</div><div class='add'>+ *</div><div class='add'>+ * Check if the @cur block is cleared</div><div class='add'>+ */</div><div class='add'>+static inline bool amdgpu_res_cleared(struct amdgpu_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+</div><div class='add'>+	switch (cur-&gt;mem_type) {</div><div class='add'>+	case TTM_PL_VRAM:</div><div class='add'>+		block = cur-&gt;node;</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_vram_mgr_is_cleared(block))</div><div class='add'>+			return false;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c<br/>index 147100c27c2d..28c4ad62f50e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c</a></div><div class='hunk'>@@ -21,14 +21,161 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/devcoredump.h&gt;</div><div class='del'>-#include &lt;generated/utsrelease.h&gt;</div><div class='del'>-</div><div class='ctx'> #include "amdgpu_reset.h"</div><div class='ctx'> #include "aldebaran.h"</div><div class='ctx'> #include "sienna_cichlid.h"</div><div class='ctx'> #include "smu_v13_0_10.h"</div><div class='ctx'> </div><div class='add'>+static int amdgpu_reset_xgmi_reset_on_init_suspend(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = adev-&gt;num_ip_blocks - 1; i &gt;= 0; i--) {</div><div class='add'>+		if (!adev-&gt;ip_blocks[i].status.valid)</div><div class='add'>+			continue;</div><div class='add'>+		if (!adev-&gt;ip_blocks[i].status.hw)</div><div class='add'>+			continue;</div><div class='add'>+		/* displays are handled in phase1 */</div><div class='add'>+		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_DCE)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* XXX handle errors */</div><div class='add'>+		amdgpu_ip_block_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* VCN FW shared region is in frambuffer, there are some flags</div><div class='add'>+	 * initialized in that region during sw_init. Make sure the region is</div><div class='add'>+	 * backed up.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_vcn_save_vcpu_bo(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_reset_xgmi_reset_on_init_prep_hwctxt(</div><div class='add'>+	struct amdgpu_reset_control *reset_ctl,</div><div class='add'>+	struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct list_head *reset_device_list = reset_context-&gt;reset_device_list;</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+		amdgpu_unregister_gpu_instance(tmp_adev);</div><div class='add'>+		r = amdgpu_reset_xgmi_reset_on_init_suspend(tmp_adev);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(tmp_adev-&gt;dev,</div><div class='add'>+				"xgmi reset on init: prepare for reset failed");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt(</div><div class='add'>+	struct amdgpu_reset_control *reset_ctl,</div><div class='add'>+	struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct list_head *reset_device_list = reset_context-&gt;reset_device_list;</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_reinit_after_reset(reset_context);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+		if (!tmp_adev-&gt;kfd.init_complete) {</div><div class='add'>+			kgd2kfd_init_zone_device(tmp_adev);</div><div class='add'>+			amdgpu_amdkfd_device_init(tmp_adev);</div><div class='add'>+			amdgpu_amdkfd_drm_client_create(tmp_adev);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_reset_xgmi_reset_on_init_perform_reset(</div><div class='add'>+	struct amdgpu_reset_control *reset_ctl,</div><div class='add'>+	struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl-&gt;handle;</div><div class='add'>+	struct list_head *reset_device_list = reset_context-&gt;reset_device_list;</div><div class='add'>+	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	dev_dbg(adev-&gt;dev, "xgmi roi - hw reset\n");</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+		mutex_lock(&amp;tmp_adev-&gt;reset_cntl-&gt;reset_lock);</div><div class='add'>+		tmp_adev-&gt;reset_cntl-&gt;active_reset =</div><div class='add'>+			amdgpu_asic_reset_method(adev);</div><div class='add'>+	}</div><div class='add'>+	r = 0;</div><div class='add'>+	/* Mode1 reset needs to be triggered on all devices together */</div><div class='add'>+	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+		/* For XGMI run all resets in parallel to speed up the process */</div><div class='add'>+		if (!queue_work(system_unbound_wq, &amp;tmp_adev-&gt;xgmi_reset_work))</div><div class='add'>+			r = -EALREADY;</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(tmp_adev-&gt;dev,</div><div class='add'>+				"xgmi reset on init: reset failed with error, %d",</div><div class='add'>+				r);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* For XGMI wait for all resets to complete before proceed */</div><div class='add'>+	if (!r) {</div><div class='add'>+		list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+			flush_work(&amp;tmp_adev-&gt;xgmi_reset_work);</div><div class='add'>+			r = tmp_adev-&gt;asic_reset_res;</div><div class='add'>+			if (r)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(tmp_adev, reset_device_list, reset_list) {</div><div class='add'>+		mutex_unlock(&amp;tmp_adev-&gt;reset_cntl-&gt;reset_lock);</div><div class='add'>+		tmp_adev-&gt;reset_cntl-&gt;active_reset = AMD_RESET_METHOD_NONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_reset_do_xgmi_reset_on_init(</div><div class='add'>+	struct amdgpu_reset_context *reset_context)</div><div class='add'>+{</div><div class='add'>+	struct list_head *reset_device_list = reset_context-&gt;reset_device_list;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!reset_device_list || list_empty(reset_device_list) ||</div><div class='add'>+	    list_is_singular(reset_device_list))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	adev = list_first_entry(reset_device_list, struct amdgpu_device,</div><div class='add'>+				reset_list);</div><div class='add'>+	r = amdgpu_reset_prepare_hwcontext(adev, reset_context);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_reset_perform_reset(adev, reset_context);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct amdgpu_reset_handler xgmi_reset_on_init_handler = {</div><div class='add'>+	.reset_method = AMD_RESET_METHOD_ON_INIT,</div><div class='add'>+	.prepare_env = NULL,</div><div class='add'>+	.prepare_hwcontext = amdgpu_reset_xgmi_reset_on_init_prep_hwctxt,</div><div class='add'>+	.perform_reset = amdgpu_reset_xgmi_reset_on_init_perform_reset,</div><div class='add'>+	.restore_hwcontext = amdgpu_reset_xgmi_reset_on_init_restore_hwctxt,</div><div class='add'>+	.restore_env = NULL,</div><div class='add'>+	.do_reset = NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int amdgpu_reset_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -36,6 +183,8 @@ int amdgpu_reset_init(struct amdgpu_device *adev)</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(13, 0, 2):</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		ret = aldebaran_reset_init(adev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 0, 7):</div><div class='hunk'>@@ -58,6 +207,8 @@ int amdgpu_reset_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(13, 0, 2):</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		ret = aldebaran_reset_fini(adev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 0, 7):</div><div class='hunk'>@@ -162,104 +313,42 @@ void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)</div><div class='ctx'> 	up_write(&amp;reset_domain-&gt;sem);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifndef CONFIG_DEV_COREDUMP</div><div class='del'>-void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,</div><div class='del'>-		     struct amdgpu_reset_context *reset_context)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-#else</div><div class='del'>-static ssize_t</div><div class='del'>-amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,</div><div class='del'>-			void *data, size_t datalen)</div><div class='del'>-{</div><div class='del'>-	struct drm_printer p;</div><div class='del'>-	struct amdgpu_coredump_info *coredump = data;</div><div class='del'>-	struct drm_print_iterator iter;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	iter.data = buffer;</div><div class='del'>-	iter.offset = 0;</div><div class='del'>-	iter.start = offset;</div><div class='del'>-	iter.remain = count;</div><div class='del'>-</div><div class='del'>-	p = drm_coredump_printer(&amp;iter);</div><div class='del'>-</div><div class='del'>-	drm_printf(&amp;p, "**** AMDGPU Device Coredump ****\n");</div><div class='del'>-	drm_printf(&amp;p, "version: " AMDGPU_COREDUMP_VERSION "\n");</div><div class='del'>-	drm_printf(&amp;p, "kernel: " UTS_RELEASE "\n");</div><div class='del'>-	drm_printf(&amp;p, "module: " KBUILD_MODNAME "\n");</div><div class='del'>-	drm_printf(&amp;p, "time: %lld.%09ld\n", coredump-&gt;reset_time.tv_sec,</div><div class='del'>-			coredump-&gt;reset_time.tv_nsec);</div><div class='del'>-</div><div class='del'>-	if (coredump-&gt;reset_task_info.pid)</div><div class='del'>-		drm_printf(&amp;p, "process_name: %s PID: %d\n",</div><div class='del'>-			   coredump-&gt;reset_task_info.process_name,</div><div class='del'>-			   coredump-&gt;reset_task_info.pid);</div><div class='del'>-</div><div class='del'>-	if (coredump-&gt;ring) {</div><div class='del'>-		drm_printf(&amp;p, "\nRing timed out details\n");</div><div class='del'>-		drm_printf(&amp;p, "IP Type: %d Ring Name: %s\n",</div><div class='del'>-			   coredump-&gt;ring-&gt;funcs-&gt;type,</div><div class='del'>-			   coredump-&gt;ring-&gt;name);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (coredump-&gt;reset_vram_lost)</div><div class='del'>-		drm_printf(&amp;p, "VRAM is lost due to GPU reset!\n");</div><div class='del'>-	if (coredump-&gt;adev-&gt;reset_info.num_regs) {</div><div class='del'>-		drm_printf(&amp;p, "AMDGPU register dumps:\nOffset:     Value:\n");</div><div class='del'>-</div><div class='del'>-		for (i = 0; i &lt; coredump-&gt;adev-&gt;reset_info.num_regs; i++)</div><div class='del'>-			drm_printf(&amp;p, "0x%08x: 0x%08x\n",</div><div class='del'>-				   coredump-&gt;adev-&gt;reset_info.reset_dump_reg_list[i],</div><div class='del'>-				   coredump-&gt;adev-&gt;reset_info.reset_dump_reg_value[i]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return count - iter.remain;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void amdgpu_devcoredump_free(void *data)</div><div class='del'>-{</div><div class='del'>-	kfree(data);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,</div><div class='del'>-		     struct amdgpu_reset_context *reset_context)</div><div class='add'>+void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,</div><div class='add'>+			   size_t len)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_coredump_info *coredump;</div><div class='del'>-	struct drm_device *dev = adev_to_drm(adev);</div><div class='del'>-	struct amdgpu_job *job = reset_context-&gt;job;</div><div class='del'>-	struct drm_sched_job *s_job;</div><div class='del'>-</div><div class='del'>-	coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT);</div><div class='del'>-</div><div class='del'>-	if (!coredump) {</div><div class='del'>-		DRM_ERROR("%s: failed to allocate memory for coredump\n", __func__);</div><div class='add'>+	if (!buf || !len)</div><div class='ctx'> 		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	coredump-&gt;reset_vram_lost = vram_lost;</div><div class='ctx'> </div><div class='del'>-	if (reset_context-&gt;job &amp;&amp; reset_context-&gt;job-&gt;vm) {</div><div class='del'>-		struct amdgpu_task_info *ti;</div><div class='del'>-		struct amdgpu_vm *vm = reset_context-&gt;job-&gt;vm;</div><div class='del'>-</div><div class='del'>-		ti = amdgpu_vm_get_task_info_vm(vm);</div><div class='del'>-		if (ti) {</div><div class='del'>-			coredump-&gt;reset_task_info = *ti;</div><div class='del'>-			amdgpu_vm_put_task_info(ti);</div><div class='add'>+	switch (rst_ctxt-&gt;src) {</div><div class='add'>+	case AMDGPU_RESET_SRC_JOB:</div><div class='add'>+		if (rst_ctxt-&gt;job) {</div><div class='add'>+			snprintf(buf, len, "job hang on ring:%s",</div><div class='add'>+				 rst_ctxt-&gt;job-&gt;base.sched-&gt;name);</div><div class='add'>+		} else {</div><div class='add'>+			strscpy(buf, "job hang", len);</div><div class='ctx'> 		}</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RESET_SRC_RAS:</div><div class='add'>+		strscpy(buf, "RAS error", len);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RESET_SRC_MES:</div><div class='add'>+		strscpy(buf, "MES hang", len);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RESET_SRC_HWS:</div><div class='add'>+		strscpy(buf, "HWS hang", len);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RESET_SRC_USER:</div><div class='add'>+		strscpy(buf, "user trigger", len);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RESET_SRC_USERQ:</div><div class='add'>+		strscpy(buf, "user queue trigger", len);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		strscpy(buf, "unknown", len);</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (job) {</div><div class='del'>-		s_job = &amp;job-&gt;base;</div><div class='del'>-		coredump-&gt;ring = to_amdgpu_ring(s_job-&gt;sched);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	coredump-&gt;adev = adev;</div><div class='del'>-</div><div class='del'>-	ktime_get_ts64(&amp;coredump-&gt;reset_time);</div><div class='del'>-</div><div class='del'>-	dev_coredumpm(dev-&gt;dev, THIS_MODULE, coredump, 0, GFP_NOWAIT,</div><div class='del'>-		      amdgpu_devcoredump_read, amdgpu_devcoredump_free);</div><div class='add'>+bool amdgpu_reset_in_recovery(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return (adev-&gt;init_lvl-&gt;level == AMDGPU_INIT_LEVEL_RESET_RECOVERY);</div><div class='ctx'> }</div><div class='del'>-#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h<br/>index 60522963aaca..07b4d37f1db6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h</a></div><div class='hunk'>@@ -32,6 +32,18 @@ enum AMDGPU_RESET_FLAGS {</div><div class='ctx'> </div><div class='ctx'> 	AMDGPU_NEED_FULL_RESET = 0,</div><div class='ctx'> 	AMDGPU_SKIP_HW_RESET = 1,</div><div class='add'>+	AMDGPU_SKIP_COREDUMP = 2,</div><div class='add'>+	AMDGPU_HOST_FLR = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum AMDGPU_RESET_SRCS {</div><div class='add'>+	AMDGPU_RESET_SRC_UNKNOWN,</div><div class='add'>+	AMDGPU_RESET_SRC_JOB,</div><div class='add'>+	AMDGPU_RESET_SRC_RAS,</div><div class='add'>+	AMDGPU_RESET_SRC_MES,</div><div class='add'>+	AMDGPU_RESET_SRC_HWS,</div><div class='add'>+	AMDGPU_RESET_SRC_USER,</div><div class='add'>+	AMDGPU_RESET_SRC_USERQ,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_reset_context {</div><div class='hunk'>@@ -41,6 +53,7 @@ struct amdgpu_reset_context {</div><div class='ctx'> 	struct amdgpu_hive_info *hive;</div><div class='ctx'> 	struct list_head *reset_device_list;</div><div class='ctx'> 	unsigned long flags;</div><div class='add'>+	enum AMDGPU_RESET_SRCS src;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_reset_handler {</div><div class='hunk'>@@ -88,19 +101,6 @@ struct amdgpu_reset_domain {</div><div class='ctx'> 	atomic_t reset_res;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_DEV_COREDUMP</div><div class='del'>-</div><div class='del'>-#define AMDGPU_COREDUMP_VERSION "1"</div><div class='del'>-</div><div class='del'>-struct amdgpu_coredump_info {</div><div class='del'>-	struct amdgpu_device		*adev;</div><div class='del'>-	struct amdgpu_task_info         reset_task_info;</div><div class='del'>-	struct timespec64               reset_time;</div><div class='del'>-	bool                            reset_vram_lost;</div><div class='del'>-	struct amdgpu_ring			*ring;</div><div class='del'>-};</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> int amdgpu_reset_init(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_reset_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -137,15 +137,40 @@ static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *doma</div><div class='ctx'> 	return queue_work(domain-&gt;wq, work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;domain-&gt;sem);</div><div class='add'>+	return rwsem_is_contended(&amp;domain-&gt;sem);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);</div><div class='ctx'> </div><div class='del'>-void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost,</div><div class='del'>-		     struct amdgpu_reset_context *reset_context);</div><div class='add'>+void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,</div><div class='add'>+			   size_t len);</div><div class='ctx'> </div><div class='ctx'> #define for_each_handler(i, handler, reset_ctl)                  \</div><div class='ctx'> 	for (i = 0; (i &lt; AMDGPU_RESET_MAX_HANDLERS) &amp;&amp;           \</div><div class='ctx'> 		    (handler = (*reset_ctl-&gt;reset_handlers)[i]); \</div><div class='ctx'> 	     ++i)</div><div class='add'>+</div><div class='add'>+extern struct amdgpu_reset_handler xgmi_reset_on_init_handler;</div><div class='add'>+int amdgpu_reset_do_xgmi_reset_on_init(</div><div class='add'>+	struct amdgpu_reset_context *reset_context);</div><div class='add'>+</div><div class='add'>+bool amdgpu_reset_in_recovery(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+static inline void amdgpu_reset_set_dpc_status(struct amdgpu_device *adev,</div><div class='add'>+					       bool status)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;pcie_reset_ctx.occurs_dpc = status;</div><div class='add'>+	adev-&gt;no_hw_access = status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool amdgpu_reset_in_dpc(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return adev-&gt;pcie_reset_ctx.occurs_dpc;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c<br/>index 5505d646f43a..c596b6df2e2d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> #include "atom.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -99,6 +100,29 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_ring_alloc_reemit - allocate space on the ring buffer for reemit</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring structure holding ring information</div><div class='add'>+ * @ndw: number of dwords to allocate in the ring buffer</div><div class='add'>+ *</div><div class='add'>+ * Allocate @ndw dwords in the ring buffer (all asics).</div><div class='add'>+ * doesn't check the max_dw limit as we may be reemitting</div><div class='add'>+ * several submissions.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)</div><div class='add'>+{</div><div class='add'>+	/* Align requested size with padding so unlock_commit can</div><div class='add'>+	 * pad safely */</div><div class='add'>+	ndw = (ndw + ring-&gt;funcs-&gt;align_mask) &amp; ~ring-&gt;funcs-&gt;align_mask;</div><div class='add'>+</div><div class='add'>+	ring-&gt;count_dw = ndw;</div><div class='add'>+	ring-&gt;wptr_old = ring-&gt;wptr;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;begin_use)</div><div class='add'>+		ring-&gt;funcs-&gt;begin_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /** amdgpu_ring_insert_nop - insert NOP packets</div><div class='ctx'>  *</div><div class='ctx'>  * @ring: amdgpu_ring structure holding ring information</div><div class='hunk'>@@ -108,10 +132,22 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	uint32_t occupied, chunk1, chunk2;</div><div class='add'>+</div><div class='add'>+	occupied = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='add'>+	chunk1 = ring-&gt;buf_mask + 1 - occupied;</div><div class='add'>+	chunk1 = (chunk1 &gt;= count) ? count : chunk1;</div><div class='add'>+	chunk2 = count - chunk1;</div><div class='add'>+</div><div class='add'>+	if (chunk1)</div><div class='add'>+		memset32(&amp;ring-&gt;ring[occupied], ring-&gt;funcs-&gt;nop, chunk1);</div><div class='add'>+</div><div class='add'>+	if (chunk2)</div><div class='add'>+		memset32(ring-&gt;ring, ring-&gt;funcs-&gt;nop, chunk2);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; count; i++)</div><div class='del'>-		amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+	ring-&gt;wptr += count;</div><div class='add'>+	ring-&gt;wptr &amp;= ring-&gt;ptr_mask;</div><div class='add'>+	ring-&gt;count_dw -= count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -124,8 +160,16 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)</div><div class='ctx'> {</div><div class='del'>-	while (ib-&gt;length_dw &amp; ring-&gt;funcs-&gt;align_mask)</div><div class='del'>-		ib-&gt;ptr[ib-&gt;length_dw++] = ring-&gt;funcs-&gt;nop;</div><div class='add'>+	u32 align_mask = ring-&gt;funcs-&gt;align_mask;</div><div class='add'>+	u32 count = ib-&gt;length_dw &amp; align_mask;</div><div class='add'>+</div><div class='add'>+	if (count) {</div><div class='add'>+		count = align_mask + 1 - count;</div><div class='add'>+</div><div class='add'>+		memset32(&amp;ib-&gt;ptr[ib-&gt;length_dw], ring-&gt;funcs-&gt;nop, count);</div><div class='add'>+</div><div class='add'>+		ib-&gt;length_dw += count;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -141,11 +185,16 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t count;</div><div class='ctx'> </div><div class='add'>+	if (ring-&gt;count_dw &lt; 0)</div><div class='add'>+		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");</div><div class='add'>+</div><div class='ctx'> 	/* We pad to match fetch size */</div><div class='ctx'> 	count = ring-&gt;funcs-&gt;align_mask + 1 -</div><div class='ctx'> 		(ring-&gt;wptr &amp; ring-&gt;funcs-&gt;align_mask);</div><div class='del'>-	count %= ring-&gt;funcs-&gt;align_mask + 1;</div><div class='del'>-	ring-&gt;funcs-&gt;insert_nop(ring, count);</div><div class='add'>+	count &amp;= ring-&gt;funcs-&gt;align_mask;</div><div class='add'>+</div><div class='add'>+	if (count != 0)</div><div class='add'>+		ring-&gt;funcs-&gt;insert_nop(ring, count);</div><div class='ctx'> </div><div class='ctx'> 	mb();</div><div class='ctx'> 	amdgpu_ring_set_wptr(ring);</div><div class='hunk'>@@ -170,14 +219,10 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_ring_get_gpu_addr(ring, offset)				\</div><div class='del'>-	(ring-&gt;is_mes_queue ?						\</div><div class='del'>-	 (ring-&gt;mes_ctx-&gt;meta_data_gpu_addr + offset) :			\</div><div class='del'>-	 (ring-&gt;adev-&gt;wb.gpu_addr + offset * 4))</div><div class='add'>+	 (ring-&gt;adev-&gt;wb.gpu_addr + offset * 4)</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_ring_get_cpu_addr(ring, offset)				\</div><div class='del'>-	(ring-&gt;is_mes_queue ?						\</div><div class='del'>-	 (void *)((uint8_t *)(ring-&gt;mes_ctx-&gt;meta_data_ptr) + offset) : \</div><div class='del'>-	 (&amp;ring-&gt;adev-&gt;wb.wb[offset]))</div><div class='add'>+	 (&amp;ring-&gt;adev-&gt;wb.wb[offset])</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_ring_init - init driver ring struct.</div><div class='hunk'>@@ -212,6 +257,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_KIQ)</div><div class='ctx'> 		sched_hw_submission = max(sched_hw_submission, 256);</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_MES)</div><div class='add'>+		sched_hw_submission = 8;</div><div class='ctx'> 	else if (ring == &amp;adev-&gt;sdma.instance[0].page)</div><div class='ctx'> 		sched_hw_submission = 256;</div><div class='ctx'> </div><div class='hunk'>@@ -224,57 +271,42 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,</div><div class='ctx'> 		ring-&gt;sched_score = sched_score;</div><div class='ctx'> 		ring-&gt;vmid_wait = dma_fence_get_stub();</div><div class='ctx'> </div><div class='del'>-		if (!ring-&gt;is_mes_queue) {</div><div class='del'>-			ring-&gt;idx = adev-&gt;num_rings++;</div><div class='del'>-			adev-&gt;rings[ring-&gt;idx] = ring;</div><div class='del'>-		}</div><div class='add'>+		ring-&gt;idx = adev-&gt;num_rings++;</div><div class='add'>+		adev-&gt;rings[ring-&gt;idx] = ring;</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_fence_driver_init_ring(ring);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		ring-&gt;rptr_offs = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-				AMDGPU_MES_CTX_RPTR_OFFS);</div><div class='del'>-		ring-&gt;wptr_offs = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-				AMDGPU_MES_CTX_WPTR_OFFS);</div><div class='del'>-		ring-&gt;fence_offs = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-				AMDGPU_MES_CTX_FENCE_OFFS);</div><div class='del'>-		ring-&gt;trail_fence_offs = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-				AMDGPU_MES_CTX_TRAIL_FENCE_OFFS);</div><div class='del'>-		ring-&gt;cond_exe_offs = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-				AMDGPU_MES_CTX_COND_EXE_OFFS);</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;ring-&gt;rptr_offs);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) ring rptr_offs wb alloc failed\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;ring-&gt;rptr_offs);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) ring rptr_offs wb alloc failed\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;ring-&gt;wptr_offs);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) ring wptr_offs wb alloc failed\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;ring-&gt;wptr_offs);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) ring wptr_offs wb alloc failed\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;ring-&gt;fence_offs);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) ring fence_offs wb alloc failed\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;ring-&gt;fence_offs);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) ring fence_offs wb alloc failed\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;ring-&gt;trail_fence_offs);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) ring trail_fence_offs wb alloc failed\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;ring-&gt;trail_fence_offs);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) ring trail_fence_offs wb alloc failed\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;ring-&gt;cond_exe_offs);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;ring-&gt;cond_exe_offs);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);</div><div class='add'>+		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;fence_gpu_addr =</div><div class='hunk'>@@ -305,45 +337,51 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,</div><div class='ctx'> 	/* always set cond_exec_polling to CONTINUE */</div><div class='ctx'> 	*ring-&gt;cond_exe_cpu_addr = 1;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "failed initializing fences (%d).\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='add'>+	if (ring-&gt;funcs-&gt;type != AMDGPU_RING_TYPE_CPER) {</div><div class='add'>+		r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed initializing fences (%d).\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	max_ibs_dw = ring-&gt;funcs-&gt;emit_frame_size +</div><div class='del'>-		     amdgpu_ring_max_ibs(ring-&gt;funcs-&gt;type) * ring-&gt;funcs-&gt;emit_ib_size;</div><div class='del'>-	max_ibs_dw = (max_ibs_dw + ring-&gt;funcs-&gt;align_mask) &amp; ~ring-&gt;funcs-&gt;align_mask;</div><div class='add'>+		max_ibs_dw = ring-&gt;funcs-&gt;emit_frame_size +</div><div class='add'>+			     amdgpu_ring_max_ibs(ring-&gt;funcs-&gt;type) * ring-&gt;funcs-&gt;emit_ib_size;</div><div class='add'>+		max_ibs_dw = (max_ibs_dw + ring-&gt;funcs-&gt;align_mask) &amp; ~ring-&gt;funcs-&gt;align_mask;</div><div class='ctx'> </div><div class='del'>-	if (WARN_ON(max_ibs_dw &gt; max_dw))</div><div class='del'>-		max_dw = max_ibs_dw;</div><div class='add'>+		if (WARN_ON(max_ibs_dw &gt; max_dw))</div><div class='add'>+			max_dw = max_ibs_dw;</div><div class='ctx'> </div><div class='del'>-	ring-&gt;ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);</div><div class='add'>+		ring-&gt;ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);</div><div class='add'>+	} else {</div><div class='add'>+		ring-&gt;ring_size = roundup_pow_of_two(max_dw * 4);</div><div class='add'>+		ring-&gt;count_dw = (ring-&gt;ring_size - 4) &gt;&gt; 2;</div><div class='add'>+		/* ring buffer is empty now */</div><div class='add'>+		ring-&gt;wptr = *ring-&gt;rptr_cpu_addr = 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;buf_mask = (ring-&gt;ring_size / 4) - 1;</div><div class='ctx'> 	ring-&gt;ptr_mask = ring-&gt;funcs-&gt;support_64bit_ptrs ?</div><div class='ctx'> 		0xffffffffffffffff : ring-&gt;buf_mask;</div><div class='add'>+	/*  Initialize cached_rptr to 0 */</div><div class='add'>+	ring-&gt;cached_rptr = 0;</div><div class='ctx'> </div><div class='del'>-	/* Allocate ring buffer */</div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		int offset = 0;</div><div class='del'>-</div><div class='del'>-		BUG_ON(ring-&gt;ring_size &gt; PAGE_SIZE*4);</div><div class='del'>-</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_RING_OFFS);</div><div class='del'>-		ring-&gt;gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ring-&gt;ring = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		amdgpu_ring_clear_ring(ring);</div><div class='add'>+	if (!ring-&gt;ring_backup) {</div><div class='add'>+		ring-&gt;ring_backup = kvzalloc(ring-&gt;ring_size, GFP_KERNEL);</div><div class='add'>+		if (!ring-&gt;ring_backup)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	} else if (ring-&gt;ring_obj == NULL) {</div><div class='del'>-		r = amdgpu_bo_create_kernel(adev, ring-&gt;ring_size + ring-&gt;funcs-&gt;extra_dw, PAGE_SIZE,</div><div class='add'>+	/* Allocate ring buffer */</div><div class='add'>+	if (ring-&gt;ring_obj == NULL) {</div><div class='add'>+		r = amdgpu_bo_create_kernel(adev, ring-&gt;ring_size + ring-&gt;funcs-&gt;extra_bytes,</div><div class='add'>+					    PAGE_SIZE,</div><div class='ctx'> 					    AMDGPU_GEM_DOMAIN_GTT,</div><div class='ctx'> 					    &amp;ring-&gt;ring_obj,</div><div class='ctx'> 					    &amp;ring-&gt;gpu_addr,</div><div class='ctx'> 					    (void **)&amp;ring-&gt;ring);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "(%d) ring create failed\n", r);</div><div class='add'>+			kvfree(ring-&gt;ring_backup);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 		amdgpu_ring_clear_ring(ring);</div><div class='hunk'>@@ -352,7 +390,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,</div><div class='ctx'> 	ring-&gt;max_dw = max_dw;</div><div class='ctx'> 	ring-&gt;hw_prio = hw_prio;</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;no_scheduler) {</div><div class='add'>+	if (!ring-&gt;no_scheduler &amp;&amp; ring-&gt;funcs-&gt;type &lt; AMDGPU_HW_IP_NUM) {</div><div class='ctx'> 		hw_ip = ring-&gt;funcs-&gt;type;</div><div class='ctx'> 		num_sched = &amp;adev-&gt;gpu_sched[hw_ip][hw_prio].num_scheds;</div><div class='ctx'> 		adev-&gt;gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =</div><div class='hunk'>@@ -373,32 +411,26 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> </div><div class='ctx'> 	/* Not to finish a ring which is not initialized */</div><div class='del'>-	if (!(ring-&gt;adev) ||</div><div class='del'>-	    (!ring-&gt;is_mes_queue &amp;&amp; !(ring-&gt;adev-&gt;rings[ring-&gt;idx])))</div><div class='add'>+	if (!(ring-&gt;adev) || !(ring-&gt;adev-&gt;rings[ring-&gt;idx]))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;sched.ready = false;</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;is_mes_queue) {</div><div class='del'>-		amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;rptr_offs);</div><div class='del'>-		amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;wptr_offs);</div><div class='add'>+	amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;rptr_offs);</div><div class='add'>+	amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;wptr_offs);</div><div class='ctx'> </div><div class='del'>-		amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;cond_exe_offs);</div><div class='del'>-		amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;fence_offs);</div><div class='add'>+	amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;cond_exe_offs);</div><div class='add'>+	amdgpu_device_wb_free(ring-&gt;adev, ring-&gt;fence_offs);</div><div class='ctx'> </div><div class='del'>-		amdgpu_bo_free_kernel(&amp;ring-&gt;ring_obj,</div><div class='del'>-				      &amp;ring-&gt;gpu_addr,</div><div class='del'>-				      (void **)&amp;ring-&gt;ring);</div><div class='del'>-	} else {</div><div class='del'>-		kfree(ring-&gt;fence_drv.fences);</div><div class='del'>-	}</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;ring-&gt;ring_obj,</div><div class='add'>+			      &amp;ring-&gt;gpu_addr,</div><div class='add'>+			      (void **)&amp;ring-&gt;ring);</div><div class='add'>+	kvfree(ring-&gt;ring_backup);</div><div class='add'>+	ring-&gt;ring_backup = NULL;</div><div class='ctx'> </div><div class='ctx'> 	dma_fence_put(ring-&gt;vmid_wait);</div><div class='ctx'> 	ring-&gt;vmid_wait = NULL;</div><div class='ctx'> 	ring-&gt;me = 0;</div><div class='del'>-</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		ring-&gt;adev-&gt;rings[ring-&gt;idx] = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -435,9 +467,7 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	ktime_t deadline;</div><div class='del'>-</div><div class='del'>-	if (unlikely(ring-&gt;adev-&gt;debug_disable_soft_recovery))</div><div class='del'>-		return false;</div><div class='add'>+	bool ret;</div><div class='ctx'> </div><div class='ctx'> 	deadline = ktime_add_us(ktime_get(), 10000);</div><div class='ctx'> </div><div class='hunk'>@@ -449,12 +479,16 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,</div><div class='ctx'> 		dma_fence_set_error(fence, -ENODATA);</div><div class='ctx'> 	spin_unlock_irqrestore(fence-&gt;lock, flags);</div><div class='ctx'> </div><div class='del'>-	atomic_inc(&amp;ring-&gt;adev-&gt;gpu_reset_counter);</div><div class='ctx'> 	while (!dma_fence_is_signaled(fence) &amp;&amp;</div><div class='ctx'> 	       ktime_to_ns(ktime_sub(deadline, ktime_get())) &gt; 0)</div><div class='ctx'> 		ring-&gt;funcs-&gt;soft_recovery(ring, vmid);</div><div class='ctx'> </div><div class='del'>-	return dma_fence_is_signaled(fence);</div><div class='add'>+	ret = dma_fence_is_signaled(fence);</div><div class='add'>+	/* increment the counter only if soft reset worked */</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic_inc(&amp;ring-&gt;adev-&gt;gpu_reset_counter);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -462,6 +496,66 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,</div><div class='ctx'>  */</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> </div><div class='add'>+static ssize_t amdgpu_ras_cper_debugfs_read(struct file *f, char __user *buf,</div><div class='add'>+					    size_t size, loff_t *offset)</div><div class='add'>+{</div><div class='add'>+	const uint8_t ring_header_size = 12;</div><div class='add'>+	struct amdgpu_ring *ring = file_inode(f)-&gt;i_private;</div><div class='add'>+	struct ras_cmd_cper_snapshot_req *snapshot_req __free(kfree) =</div><div class='add'>+		kzalloc(sizeof(struct ras_cmd_cper_snapshot_req), GFP_KERNEL);</div><div class='add'>+	struct ras_cmd_cper_snapshot_rsp *snapshot_rsp __free(kfree) =</div><div class='add'>+		kzalloc(sizeof(struct ras_cmd_cper_snapshot_rsp), GFP_KERNEL);</div><div class='add'>+	struct ras_cmd_cper_record_req *record_req __free(kfree) =</div><div class='add'>+		kzalloc(sizeof(struct ras_cmd_cper_record_req), GFP_KERNEL);</div><div class='add'>+	struct ras_cmd_cper_record_rsp *record_rsp __free(kfree) =</div><div class='add'>+		kzalloc(sizeof(struct ras_cmd_cper_record_rsp), GFP_KERNEL);</div><div class='add'>+	uint8_t *ring_header __free(kfree) =</div><div class='add'>+		kzalloc(ring_header_size, GFP_KERNEL);</div><div class='add'>+	uint32_t total_cper_num;</div><div class='add'>+	uint64_t start_cper_id;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!snapshot_req || !snapshot_rsp || !record_req || !record_rsp ||</div><div class='add'>+	    !ring_header)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	if (!(*offset)) {</div><div class='add'>+		/* Need at least 12 bytes for the header on the first read */</div><div class='add'>+		if (size &lt; ring_header_size)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (copy_to_user(buf, ring_header, ring_header_size))</div><div class='add'>+			return -EFAULT;</div><div class='add'>+		buf += ring_header_size;</div><div class='add'>+		size -= ring_header_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_mgr_handle_ras_cmd(ring-&gt;adev,</div><div class='add'>+					  RAS_CMD__GET_CPER_SNAPSHOT,</div><div class='add'>+					  snapshot_req, sizeof(struct ras_cmd_cper_snapshot_req),</div><div class='add'>+					  snapshot_rsp, sizeof(struct ras_cmd_cper_snapshot_rsp));</div><div class='add'>+	if (r || !snapshot_rsp-&gt;total_cper_num)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	start_cper_id = snapshot_rsp-&gt;start_cper_id;</div><div class='add'>+	total_cper_num = snapshot_rsp-&gt;total_cper_num;</div><div class='add'>+</div><div class='add'>+	record_req-&gt;buf_ptr = (uint64_t)(uintptr_t)buf;</div><div class='add'>+	record_req-&gt;buf_size = size;</div><div class='add'>+	record_req-&gt;cper_start_id = start_cper_id + *offset;</div><div class='add'>+	record_req-&gt;cper_num = total_cper_num;</div><div class='add'>+	r = amdgpu_ras_mgr_handle_ras_cmd(ring-&gt;adev, RAS_CMD__GET_CPER_RECORD,</div><div class='add'>+					  record_req, sizeof(struct ras_cmd_cper_record_req),</div><div class='add'>+					  record_rsp, sizeof(struct ras_cmd_cper_record_rsp));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = *offset ? record_rsp-&gt;real_data_size : record_rsp-&gt;real_data_size + ring_header_size;</div><div class='add'>+	(*offset) += record_rsp-&gt;real_cper_num;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Layout of file is 12 bytes consisting of</div><div class='ctx'>  * - rptr</div><div class='ctx'>  * - wptr</div><div class='hunk'>@@ -473,8 +567,13 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,</div><div class='ctx'> 					size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = file_inode(f)-&gt;i_private;</div><div class='del'>-	int r, i;</div><div class='ctx'> 	uint32_t value, result, early[3];</div><div class='add'>+	uint64_t p;</div><div class='add'>+	loff_t i;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_CPER &amp;&amp; amdgpu_uniras_enabled(ring-&gt;adev))</div><div class='add'>+		return amdgpu_ras_cper_debugfs_read(f, buf, size, pos);</div><div class='ctx'> </div><div class='ctx'> 	if (*pos &amp; 3 || size &amp; 3)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -482,13 +581,18 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,</div><div class='ctx'> 	result = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (*pos &lt; 12) {</div><div class='add'>+		if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_CPER)</div><div class='add'>+			mutex_lock(&amp;ring-&gt;adev-&gt;cper.ring_lock);</div><div class='add'>+</div><div class='ctx'> 		early[0] = amdgpu_ring_get_rptr(ring) &amp; ring-&gt;buf_mask;</div><div class='ctx'> 		early[1] = amdgpu_ring_get_wptr(ring) &amp; ring-&gt;buf_mask;</div><div class='ctx'> 		early[2] = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='ctx'> 		for (i = *pos / 4; i &lt; 3 &amp;&amp; size; i++) {</div><div class='ctx'> 			r = put_user(early[i], (uint32_t *)buf);</div><div class='del'>-			if (r)</div><div class='del'>-				return r;</div><div class='add'>+			if (r) {</div><div class='add'>+				result = r;</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='ctx'> 			buf += 4;</div><div class='ctx'> 			result += 4;</div><div class='ctx'> 			size -= 4;</div><div class='hunk'>@@ -496,74 +600,94 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	while (size) {</div><div class='del'>-		if (*pos &gt;= (ring-&gt;ring_size + 12))</div><div class='del'>-			return result;</div><div class='add'>+	if (ring-&gt;funcs-&gt;type != AMDGPU_RING_TYPE_CPER) {</div><div class='add'>+		while (size) {</div><div class='add'>+			if (*pos &gt;= (ring-&gt;ring_size + 12))</div><div class='add'>+				return result;</div><div class='ctx'> </div><div class='del'>-		value = ring-&gt;ring[(*pos - 12)/4];</div><div class='del'>-		r = put_user(value, (uint32_t *)buf);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-		buf += 4;</div><div class='del'>-		result += 4;</div><div class='del'>-		size -= 4;</div><div class='del'>-		*pos += 4;</div><div class='add'>+			value = ring-&gt;ring[(*pos - 12)/4];</div><div class='add'>+			r = put_user(value, (uint32_t *)buf);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+			buf += 4;</div><div class='add'>+			result += 4;</div><div class='add'>+			size -= 4;</div><div class='add'>+			*pos += 4;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		p = early[0];</div><div class='add'>+		if (early[0] &lt;= early[1])</div><div class='add'>+			size = (early[1] - early[0]);</div><div class='add'>+		else</div><div class='add'>+			size = ring-&gt;ring_size - (early[0] - early[1]);</div><div class='add'>+</div><div class='add'>+		while (size) {</div><div class='add'>+			if (p == early[1])</div><div class='add'>+				goto out;</div><div class='add'>+</div><div class='add'>+			value = ring-&gt;ring[p];</div><div class='add'>+			r = put_user(value, (uint32_t *)buf);</div><div class='add'>+			if (r) {</div><div class='add'>+				result = r;</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			buf += 4;</div><div class='add'>+			result += 4;</div><div class='add'>+			size--;</div><div class='add'>+			p++;</div><div class='add'>+			p &amp;= ring-&gt;ptr_mask;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_CPER)</div><div class='add'>+		mutex_unlock(&amp;ring-&gt;adev-&gt;cper.ring_lock);</div><div class='add'>+</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t amdgpu_debugfs_virt_ring_read(struct file *f, char __user *buf,</div><div class='add'>+	size_t size, loff_t *pos)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring = file_inode(f)-&gt;i_private;</div><div class='add'>+</div><div class='add'>+	if (*pos &amp; 3 || size &amp; 3)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_CPER)</div><div class='add'>+		amdgpu_virt_req_ras_cper_dump(ring-&gt;adev, false);</div><div class='add'>+</div><div class='add'>+	return amdgpu_debugfs_ring_read(f, buf, size, pos);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct file_operations amdgpu_debugfs_ring_fops = {</div><div class='ctx'> 	.owner = THIS_MODULE,</div><div class='ctx'> 	.read = amdgpu_debugfs_ring_read,</div><div class='ctx'> 	.llseek = default_llseek</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct file_operations amdgpu_debugfs_virt_ring_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.read = amdgpu_debugfs_virt_ring_read,</div><div class='add'>+	.llseek = default_llseek</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf,</div><div class='ctx'> 				       size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = file_inode(f)-&gt;i_private;</div><div class='del'>-	volatile u32 *mqd;</div><div class='del'>-	int r;</div><div class='del'>-	uint32_t value, result;</div><div class='del'>-</div><div class='del'>-	if (*pos &amp; 3 || size &amp; 3)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	result = 0;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;mqd);</div><div class='del'>-	if (r) {</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	while (size) {</div><div class='del'>-		if (*pos &gt;= ring-&gt;mqd_size)</div><div class='del'>-			goto done;</div><div class='add'>+	ssize_t bytes = min_t(ssize_t, ring-&gt;mqd_size - *pos, size);</div><div class='add'>+	void *from = ((u8 *)ring-&gt;mqd_ptr) + *pos;</div><div class='ctx'> </div><div class='del'>-		value = mqd[*pos/4];</div><div class='del'>-		r = put_user(value, (uint32_t *)buf);</div><div class='del'>-		if (r)</div><div class='del'>-			goto done;</div><div class='del'>-		buf += 4;</div><div class='del'>-		result += 4;</div><div class='del'>-		size -= 4;</div><div class='del'>-		*pos += 4;</div><div class='del'>-	}</div><div class='add'>+	if (*pos &gt; ring-&gt;mqd_size)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-	mqd = NULL;</div><div class='del'>-	amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	if (copy_to_user(buf, from, bytes))</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> </div><div class='del'>-	return result;</div><div class='add'>+	*pos += bytes;</div><div class='add'>+	return bytes;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct file_operations amdgpu_debugfs_mqd_fops = {</div><div class='hunk'>@@ -594,9 +718,14 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,</div><div class='ctx'> 	char name[32];</div><div class='ctx'> </div><div class='ctx'> 	sprintf(name, "amdgpu_ring_%s", ring-&gt;name);</div><div class='del'>-	debugfs_create_file_size(name, S_IFREG | 0444, root, ring,</div><div class='del'>-				 &amp;amdgpu_debugfs_ring_fops,</div><div class='del'>-				 ring-&gt;ring_size + 12);</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		debugfs_create_file_size(name, S_IFREG | 0444, root, ring,</div><div class='add'>+					 &amp;amdgpu_debugfs_virt_ring_fops,</div><div class='add'>+					 ring-&gt;ring_size + 12);</div><div class='add'>+	else</div><div class='add'>+		debugfs_create_file_size(name, S_IFREG | 0444, root, ring,</div><div class='add'>+					 &amp;amdgpu_debugfs_ring_fops,</div><div class='add'>+					 ring-&gt;ring_size + 12);</div><div class='ctx'> </div><div class='ctx'> 	if (ring-&gt;mqd_obj) {</div><div class='ctx'> 		sprintf(name, "amdgpu_mqd_%s", ring-&gt;name);</div><div class='hunk'>@@ -658,6 +787,7 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,</div><div class='ctx'> 	prop-&gt;eop_gpu_addr = ring-&gt;eop_gpu_addr;</div><div class='ctx'> 	prop-&gt;use_doorbell = ring-&gt;use_doorbell;</div><div class='ctx'> 	prop-&gt;doorbell_index = ring-&gt;doorbell_index;</div><div class='add'>+	prop-&gt;kernel_queue = true;</div><div class='ctx'> </div><div class='ctx'> 	/* map_queues packet doesn't need activate the queue,</div><div class='ctx'> 	 * so only kiq need set this field.</div><div class='hunk'>@@ -729,3 +859,69 @@ bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,</div><div class='add'>+				    struct amdgpu_fence *guilty_fence)</div><div class='add'>+{</div><div class='add'>+	/* Stop the scheduler to prevent anybody else from touching the ring buffer. */</div><div class='add'>+	drm_sched_wqueue_stop(&amp;ring-&gt;sched);</div><div class='add'>+	/* back up the non-guilty commands */</div><div class='add'>+	amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,</div><div class='add'>+				 struct amdgpu_fence *guilty_fence)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/* verify that the ring is functional */</div><div class='add'>+	r = amdgpu_ring_test_ring(ring);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* signal the guilty fence and set an error on all fences from the context */</div><div class='add'>+	if (guilty_fence)</div><div class='add'>+		amdgpu_fence_driver_guilty_force_completion(guilty_fence);</div><div class='add'>+	/* Re-emit the non-guilty commands */</div><div class='add'>+	if (ring-&gt;ring_backup_entries_to_copy) {</div><div class='add'>+		amdgpu_ring_alloc_reemit(ring, ring-&gt;ring_backup_entries_to_copy);</div><div class='add'>+		for (i = 0; i &lt; ring-&gt;ring_backup_entries_to_copy; i++)</div><div class='add'>+			amdgpu_ring_write(ring, ring-&gt;ring_backup[i]);</div><div class='add'>+		amdgpu_ring_commit(ring);</div><div class='add'>+	}</div><div class='add'>+	/* Start the scheduler again */</div><div class='add'>+	drm_sched_wqueue_start(&amp;ring-&gt;sched);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,</div><div class='add'>+					 u32 reset_type)</div><div class='add'>+{</div><div class='add'>+	switch (ring-&gt;funcs-&gt;type) {</div><div class='add'>+	case AMDGPU_RING_TYPE_GFX:</div><div class='add'>+		if (ring-&gt;adev-&gt;gfx.gfx_supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='add'>+		if (ring-&gt;adev-&gt;gfx.compute_supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_SDMA:</div><div class='add'>+		if (ring-&gt;adev-&gt;sdma.supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_DEC:</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_ENC:</div><div class='add'>+		if (ring-&gt;adev-&gt;vcn.supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_JPEG:</div><div class='add'>+		if (ring-&gt;adev-&gt;jpeg.supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h<br/>index 582053f1cd56..7a27c6c4bb44 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h</a></div><div class='hunk'>@@ -37,7 +37,7 @@ struct amdgpu_job;</div><div class='ctx'> struct amdgpu_vm;</div><div class='ctx'> </div><div class='ctx'> /* max number of rings */</div><div class='del'>-#define AMDGPU_MAX_RINGS		124</div><div class='add'>+#define AMDGPU_MAX_RINGS		149</div><div class='ctx'> #define AMDGPU_MAX_HWIP_RINGS		64</div><div class='ctx'> #define AMDGPU_MAX_GFX_RINGS		2</div><div class='ctx'> #define AMDGPU_MAX_SW_GFX_RINGS         2</div><div class='hunk'>@@ -82,6 +82,8 @@ enum amdgpu_ring_type {</div><div class='ctx'> 	AMDGPU_RING_TYPE_KIQ,</div><div class='ctx'> 	AMDGPU_RING_TYPE_MES,</div><div class='ctx'> 	AMDGPU_RING_TYPE_UMSCH_MM,</div><div class='add'>+	AMDGPU_RING_TYPE_CPER,</div><div class='add'>+	AMDGPU_RING_TYPE_MAX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_ib_pool_type {</div><div class='hunk'>@@ -113,10 +115,11 @@ struct amdgpu_sched {</div><div class='ctx'>  */</div><div class='ctx'> struct amdgpu_fence_driver {</div><div class='ctx'> 	uint64_t			gpu_addr;</div><div class='del'>-	volatile uint32_t		*cpu_addr;</div><div class='add'>+	uint32_t			*cpu_addr;</div><div class='ctx'> 	/* sync_seq is protected by ring emission lock */</div><div class='ctx'> 	uint32_t			sync_seq;</div><div class='ctx'> 	atomic_t			last_seq;</div><div class='add'>+	u64				signalled_wptr;</div><div class='ctx'> 	bool				initialized;</div><div class='ctx'> 	struct amdgpu_irq_src		*irq_src;</div><div class='ctx'> 	unsigned			irq_type;</div><div class='hunk'>@@ -126,11 +129,33 @@ struct amdgpu_fence_driver {</div><div class='ctx'> 	struct dma_fence		**fences;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Fences mark an event in the GPUs pipeline and are used</div><div class='add'>+ * for GPU/CPU synchronization.  When the fence is written,</div><div class='add'>+ * it is expected that all buffers associated with that fence</div><div class='add'>+ * are no longer in use by the associated ring on the GPU and</div><div class='add'>+ * that the relevant GPU caches have been flushed.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct amdgpu_fence {</div><div class='add'>+	struct dma_fence base;</div><div class='add'>+</div><div class='add'>+	/* RB, DMA, etc. */</div><div class='add'>+	struct amdgpu_ring		*ring;</div><div class='add'>+	ktime_t				start_timestamp;</div><div class='add'>+</div><div class='add'>+	/* wptr for the fence for resets */</div><div class='add'>+	u64				wptr;</div><div class='add'>+	/* fence context for resets */</div><div class='add'>+	u64				context;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> extern const struct drm_sched_backend_ops amdgpu_sched_ops;</div><div class='ctx'> </div><div class='del'>-void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);</div><div class='ctx'> void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);</div><div class='ctx'> void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);</div><div class='add'>+void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af);</div><div class='add'>+void amdgpu_fence_save_wptr(struct amdgpu_fence *af);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);</div><div class='ctx'> int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,</div><div class='hunk'>@@ -140,8 +165,8 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,</div><div class='del'>-		      unsigned flags);</div><div class='add'>+int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,</div><div class='add'>+		      unsigned int flags);</div><div class='ctx'> int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,</div><div class='ctx'> 			      uint32_t timeout);</div><div class='ctx'> bool amdgpu_fence_process(struct amdgpu_ring *ring);</div><div class='hunk'>@@ -163,13 +188,40 @@ void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,</div><div class='ctx'> </div><div class='ctx'> /* provided by hw blocks that expose a ring buffer for commands */</div><div class='ctx'> struct amdgpu_ring_funcs {</div><div class='add'>+	/**</div><div class='add'>+	 * @type:</div><div class='add'>+	 *</div><div class='add'>+	 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER</div><div class='add'>+	 * use ring buffers. The type field just identifies which component the</div><div class='add'>+	 * ring buffer is associated with.</div><div class='add'>+	 */</div><div class='ctx'> 	enum amdgpu_ring_type	type;</div><div class='ctx'> 	uint32_t		align_mask;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @nop:</div><div class='add'>+	 *</div><div class='add'>+	 * Every block in the amdgpu has no-op instructions (e.g., GFX 10</div><div class='add'>+	 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP,</div><div class='add'>+	 * etc). This field receives the specific no-op for the component</div><div class='add'>+	 * that initializes the ring.</div><div class='add'>+	 */</div><div class='ctx'> 	u32			nop;</div><div class='ctx'> 	bool			support_64bit_ptrs;</div><div class='ctx'> 	bool			no_user_fence;</div><div class='ctx'> 	bool			secure_submission_supported;</div><div class='del'>-	unsigned		extra_dw;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @extra_bytes:</div><div class='add'>+	 *</div><div class='add'>+	 * Optional extra space in bytes that is added to the ring size</div><div class='add'>+	 * when allocating the BO that holds the contents of the ring.</div><div class='add'>+	 * This space isn't used for command submission to the ring,</div><div class='add'>+	 * but is just there to satisfy some hardware requirements or</div><div class='add'>+	 * implement workarounds. It's up to the implementation of each</div><div class='add'>+	 * specific ring to initialize this space.</div><div class='add'>+	 */</div><div class='add'>+	unsigned		extra_bytes;</div><div class='ctx'> </div><div class='ctx'> 	/* ring read/write ptr handling */</div><div class='ctx'> 	u64 (*get_rptr)(struct amdgpu_ring *ring);</div><div class='hunk'>@@ -235,8 +287,14 @@ struct amdgpu_ring_funcs {</div><div class='ctx'> 	void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);</div><div class='ctx'> 	void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);</div><div class='ctx'> 	void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);</div><div class='add'>+	int (*reset)(struct amdgpu_ring *ring, unsigned int vmid,</div><div class='add'>+		     struct amdgpu_fence *timedout_fence);</div><div class='add'>+	void (*emit_cleaner_shader)(struct amdgpu_ring *ring);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_ring - Holds ring information</div><div class='add'>+ */</div><div class='ctx'> struct amdgpu_ring {</div><div class='ctx'> 	struct amdgpu_device		*adev;</div><div class='ctx'> 	const struct amdgpu_ring_funcs	*funcs;</div><div class='hunk'>@@ -244,17 +302,68 @@ struct amdgpu_ring {</div><div class='ctx'> 	struct drm_gpu_scheduler	sched;</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_bo	*ring_obj;</div><div class='del'>-	volatile uint32_t	*ring;</div><div class='add'>+	uint32_t		*ring;</div><div class='add'>+	/* backups for resets */</div><div class='add'>+	uint32_t		*ring_backup;</div><div class='add'>+	unsigned int		ring_backup_entries_to_copy;</div><div class='ctx'> 	unsigned		rptr_offs;</div><div class='ctx'> 	u64			rptr_gpu_addr;</div><div class='del'>-	volatile u32		*rptr_cpu_addr;</div><div class='add'>+	u32			*rptr_cpu_addr;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @wptr:</div><div class='add'>+	 *</div><div class='add'>+	 * This is part of the Ring buffer implementation and represents the</div><div class='add'>+	 * write pointer. The wptr determines where the host has written.</div><div class='add'>+	 */</div><div class='ctx'> 	u64			wptr;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @wptr_old:</div><div class='add'>+	 *</div><div class='add'>+	 * Before update wptr with the new value, usually the old value is</div><div class='add'>+	 * stored in the wptr_old.</div><div class='add'>+	 */</div><div class='ctx'> 	u64			wptr_old;</div><div class='ctx'> 	unsigned		ring_size;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @max_dw:</div><div class='add'>+	 *</div><div class='add'>+	 * Maximum number of DWords for ring allocation. This information is</div><div class='add'>+	 * provided at the ring initialization time, and each IP block can</div><div class='add'>+	 * specify a specific value. Check places that invoke</div><div class='add'>+	 * amdgpu_ring_init() to see the maximum size per block.</div><div class='add'>+	 */</div><div class='ctx'> 	unsigned		max_dw;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @count_dw:</div><div class='add'>+	 *</div><div class='add'>+	 * This value starts with the maximum amount of DWords supported by the</div><div class='add'>+	 * ring. This value is updated based on the ring manipulation.</div><div class='add'>+	 */</div><div class='ctx'> 	int			count_dw;</div><div class='ctx'> 	uint64_t		gpu_addr;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @ptr_mask:</div><div class='add'>+	 *</div><div class='add'>+	 * Some IPs provide support for 64-bit pointers and others for 32-bit</div><div class='add'>+	 * only; this behavior is component-specific and defined by the field</div><div class='add'>+	 * support_64bit_ptr. If the IP block supports 64-bits, the mask</div><div class='add'>+	 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask.</div><div class='add'>+	 * Notice that this field is used to keep wptr under a valid range.</div><div class='add'>+	 */</div><div class='ctx'> 	uint64_t		ptr_mask;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @buf_mask:</div><div class='add'>+	 *</div><div class='add'>+	 * Buffer mask is a value used to keep wptr count under its</div><div class='add'>+	 * thresholding. Buffer mask initialized during the ring buffer</div><div class='add'>+	 * initialization time, and it is defined as (ring_size / 4) -1.</div><div class='add'>+	 */</div><div class='ctx'> 	uint32_t		buf_mask;</div><div class='ctx'> 	u32			idx;</div><div class='ctx'> 	u32			xcc_id;</div><div class='hunk'>@@ -272,39 +381,43 @@ struct amdgpu_ring {</div><div class='ctx'> 	bool			use_pollmem;</div><div class='ctx'> 	unsigned		wptr_offs;</div><div class='ctx'> 	u64			wptr_gpu_addr;</div><div class='del'>-	volatile u32		*wptr_cpu_addr;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @wptr_cpu_addr:</div><div class='add'>+	 *</div><div class='add'>+	 * This is the CPU address pointer in the writeback slot. This is used</div><div class='add'>+	 * to commit changes to the GPU.</div><div class='add'>+	 */</div><div class='add'>+	u32			*wptr_cpu_addr;</div><div class='ctx'> 	unsigned		fence_offs;</div><div class='ctx'> 	u64			fence_gpu_addr;</div><div class='del'>-	volatile u32		*fence_cpu_addr;</div><div class='add'>+	u32			*fence_cpu_addr;</div><div class='ctx'> 	uint64_t		current_ctx;</div><div class='ctx'> 	char			name[16];</div><div class='ctx'> 	u32                     trail_seq;</div><div class='ctx'> 	unsigned		trail_fence_offs;</div><div class='ctx'> 	u64			trail_fence_gpu_addr;</div><div class='del'>-	volatile u32		*trail_fence_cpu_addr;</div><div class='add'>+	u32			*trail_fence_cpu_addr;</div><div class='ctx'> 	unsigned		cond_exe_offs;</div><div class='ctx'> 	u64			cond_exe_gpu_addr;</div><div class='del'>-	volatile u32		*cond_exe_cpu_addr;</div><div class='add'>+	u32			*cond_exe_cpu_addr;</div><div class='ctx'> 	unsigned int		set_q_mode_offs;</div><div class='del'>-	volatile u32		*set_q_mode_ptr;</div><div class='add'>+	u32			*set_q_mode_ptr;</div><div class='ctx'> 	u64			set_q_mode_token;</div><div class='ctx'> 	unsigned		vm_hub;</div><div class='ctx'> 	unsigned		vm_inv_eng;</div><div class='ctx'> 	struct dma_fence	*vmid_wait;</div><div class='ctx'> 	bool			has_compute_vm_bug;</div><div class='ctx'> 	bool			no_scheduler;</div><div class='add'>+	bool			no_user_submission;</div><div class='ctx'> 	int			hw_prio;</div><div class='ctx'> 	unsigned 		num_hw_submission;</div><div class='ctx'> 	atomic_t		*sched_score;</div><div class='ctx'> </div><div class='del'>-	/* used for mes */</div><div class='del'>-	bool			is_mes_queue;</div><div class='del'>-	uint32_t		hw_queue_id;</div><div class='del'>-	struct amdgpu_mes_ctx_data *mes_ctx;</div><div class='del'>-</div><div class='ctx'> 	bool            is_sw_ring;</div><div class='ctx'> 	unsigned int    entry_index;</div><div class='del'>-</div><div class='add'>+	/* store the cached rptr to restore after reset */</div><div class='add'>+	uint64_t cached_rptr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)-&gt;funcs-&gt;parse_cs((p), (job), (ib)))</div><div class='hunk'>@@ -334,6 +447,7 @@ struct amdgpu_ring {</div><div class='ctx'> #define amdgpu_ring_patch_cntl(r, o) ((r)-&gt;funcs-&gt;patch_cntl((r), (o)))</div><div class='ctx'> #define amdgpu_ring_patch_ce(r, o) ((r)-&gt;funcs-&gt;patch_ce((r), (o)))</div><div class='ctx'> #define amdgpu_ring_patch_de(r, o) ((r)-&gt;funcs-&gt;patch_de((r), (o)))</div><div class='add'>+#define amdgpu_ring_reset(r, v, f) (r)-&gt;funcs-&gt;reset((r), (v), (f))</div><div class='ctx'> </div><div class='ctx'> unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);</div><div class='ctx'> int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);</div><div class='hunk'>@@ -366,16 +480,11 @@ static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='del'>-	int i = 0;</div><div class='del'>-	while (i &lt;= ring-&gt;buf_mask)</div><div class='del'>-		ring-&gt;ring[i++] = ring-&gt;funcs-&gt;nop;</div><div class='del'>-</div><div class='add'>+	memset32(ring-&gt;ring, ring-&gt;funcs-&gt;nop, ring-&gt;buf_mask + 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)</div><div class='ctx'> {</div><div class='del'>-	if (ring-&gt;count_dw &lt;= 0)</div><div class='del'>-		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");</div><div class='ctx'> 	ring-&gt;ring[ring-&gt;wptr++ &amp; ring-&gt;buf_mask] = v;</div><div class='ctx'> 	ring-&gt;wptr &amp;= ring-&gt;ptr_mask;</div><div class='ctx'> 	ring-&gt;count_dw--;</div><div class='hunk'>@@ -385,13 +494,8 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,</div><div class='ctx'> 					      void *src, int count_dw)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned occupied, chunk1, chunk2;</div><div class='del'>-	void *dst;</div><div class='del'>-</div><div class='del'>-	if (unlikely(ring-&gt;count_dw &lt; count_dw))</div><div class='del'>-		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");</div><div class='ctx'> </div><div class='ctx'> 	occupied = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='del'>-	dst = (void *)&amp;ring-&gt;ring[occupied];</div><div class='ctx'> 	chunk1 = ring-&gt;buf_mask + 1 - occupied;</div><div class='ctx'> 	chunk1 = (chunk1 &gt;= count_dw) ? count_dw : chunk1;</div><div class='ctx'> 	chunk2 = count_dw - chunk1;</div><div class='hunk'>@@ -399,12 +503,11 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,</div><div class='ctx'> 	chunk2 &lt;&lt;= 2;</div><div class='ctx'> </div><div class='ctx'> 	if (chunk1)</div><div class='del'>-		memcpy(dst, src, chunk1);</div><div class='add'>+		memcpy(&amp;ring-&gt;ring[occupied], src, chunk1);</div><div class='ctx'> </div><div class='ctx'> 	if (chunk2) {</div><div class='ctx'> 		src += chunk1;</div><div class='del'>-		dst = (void *)ring-&gt;ring;</div><div class='del'>-		memcpy(dst, src, chunk2);</div><div class='add'>+		memcpy(ring-&gt;ring, src, chunk2);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;wptr += count_dw;</div><div class='hunk'>@@ -436,15 +539,6 @@ static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring,</div><div class='ctx'> 	ring-&gt;ring[offset] = cur - offset;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)			\</div><div class='del'>-	(ring-&gt;is_mes_queue &amp;&amp; ring-&gt;mes_ctx ?				\</div><div class='del'>-	 (ring-&gt;mes_ctx-&gt;meta_data_gpu_addr + offset) : 0)</div><div class='del'>-</div><div class='del'>-#define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)			\</div><div class='del'>-	(ring-&gt;is_mes_queue &amp;&amp; ring-&gt;mes_ctx ?				\</div><div class='del'>-	 (void *)((uint8_t *)(ring-&gt;mes_ctx-&gt;meta_data_ptr) + offset) : \</div><div class='del'>-	 NULL)</div><div class='del'>-</div><div class='ctx'> int amdgpu_ring_test_helper(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,</div><div class='hunk'>@@ -467,8 +561,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		  unsigned size,</div><div class='ctx'> 		  enum amdgpu_ib_pool_type pool,</div><div class='ctx'> 		  struct amdgpu_ib *ib);</div><div class='del'>-void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,</div><div class='del'>-		    struct dma_fence *f);</div><div class='add'>+void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f);</div><div class='ctx'> int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,</div><div class='ctx'> 		       struct amdgpu_ib *ibs, struct amdgpu_job *job,</div><div class='ctx'> 		       struct dma_fence **f);</div><div class='hunk'>@@ -476,4 +569,12 @@ int amdgpu_ib_pool_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_ib_pool_fini(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_ib_ring_tests(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);</div><div class='add'>+void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,</div><div class='add'>+					     struct amdgpu_fence *guilty_fence);</div><div class='add'>+void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,</div><div class='add'>+				    struct amdgpu_fence *guilty_fence);</div><div class='add'>+int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,</div><div class='add'>+				 struct amdgpu_fence *guilty_fence);</div><div class='add'>+bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,</div><div class='add'>+					 u32 reset_type);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c<br/>index d234b7ccfaaf..7e7d6c3865bc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c</a></div><div class='hunk'>@@ -124,7 +124,7 @@ static void amdgpu_mux_resubmit_chunks(struct amdgpu_ring_mux *mux)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	del_timer(&amp;mux-&gt;resubmit_timer);</div><div class='add'>+	timer_delete(&amp;mux-&gt;resubmit_timer);</div><div class='ctx'> 	mux-&gt;s_resubmit = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -135,7 +135,8 @@ static void amdgpu_ring_mux_schedule_resubmit(struct amdgpu_ring_mux *mux)</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_mux_resubmit_fallback(struct timer_list *t)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring_mux *mux = from_timer(mux, t, resubmit_timer);</div><div class='add'>+	struct amdgpu_ring_mux *mux = timer_container_of(mux, t,</div><div class='add'>+							 resubmit_timer);</div><div class='ctx'> </div><div class='ctx'> 	if (!spin_trylock(&amp;mux-&gt;lock)) {</div><div class='ctx'> 		amdgpu_ring_mux_schedule_resubmit(mux);</div><div class='hunk'>@@ -410,7 +411,7 @@ void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring)</div><div class='ctx'> 	struct amdgpu_ring_mux *mux = &amp;adev-&gt;gfx.muxer;</div><div class='ctx'> </div><div class='ctx'> 	WARN_ON(!ring-&gt;is_sw_ring);</div><div class='del'>-	if (ring-&gt;hw_prio &gt; AMDGPU_RING_PRIO_DEFAULT)</div><div class='add'>+	if (adev-&gt;gfx.mcbp &amp;&amp; ring-&gt;hw_prio &gt; AMDGPU_RING_PRIO_DEFAULT)</div><div class='ctx'> 		return;</div><div class='ctx'> 	amdgpu_ring_mux_end_ib(mux, ring);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c<br/>index db5791e1a7ce..5aa830a02d80 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c</a></div><div class='hunk'>@@ -89,7 +89,7 @@ void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)</div><div class='ctx'> {</div><div class='ctx'> 	const u32 *src_ptr;</div><div class='del'>-	volatile u32 *dst_ptr;</div><div class='add'>+	u32 *dst_ptr;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -189,7 +189,7 @@ int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev)</div><div class='ctx'> void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const __le32 *fw_data;</div><div class='del'>-	volatile u32 *dst_ptr;</div><div class='add'>+	u32 *dst_ptr;</div><div class='ctx'> 	int me, i, max_me;</div><div class='ctx'> 	u32 bo_offset = 0;</div><div class='ctx'> 	u32 table_offset, table_size;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h<br/>index 5a17e0ff2ab8..2ce310b31942 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h</a></div><div class='hunk'>@@ -112,6 +112,53 @@ typedef enum _SOC21_FIRMWARE_ID_ {</div><div class='ctx'>     SOC21_FIRMWARE_ID_MAX                         = 37</div><div class='ctx'> } SOC21_FIRMWARE_ID;</div><div class='ctx'> </div><div class='add'>+typedef enum _SOC24_FIRMWARE_ID_ {</div><div class='add'>+    SOC24_FIRMWARE_ID_INVALID                     = 0,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLC_G_UCODE                 = 1,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLC_TOC                     = 2,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLCG_SCRATCH                = 3,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLC_SRM_ARAM                = 4,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLC_P_UCODE                 = 5,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLC_V_UCODE                 = 6,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLX6_UCODE                  = 7,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLX6_UCODE_CORE1            = 8,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT              = 9,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1        = 10,</div><div class='add'>+    SOC24_FIRMWARE_ID_SDMA_UCODE_TH0              = 11,</div><div class='add'>+    SOC24_FIRMWARE_ID_SDMA_UCODE_TH1              = 12,</div><div class='add'>+    SOC24_FIRMWARE_ID_CP_PFP                      = 13,</div><div class='add'>+    SOC24_FIRMWARE_ID_CP_ME                       = 14,</div><div class='add'>+    SOC24_FIRMWARE_ID_CP_MEC                      = 15,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MES_P0                 = 16,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MES_P1                 = 17,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_PFP                    = 18,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_ME                     = 19,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MEC                    = 20,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MES_P0_STACK           = 21,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MES_P1_STACK           = 22,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK           = 23,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK           = 24,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_ME_P0_STACK            = 25,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_ME_P1_STACK            = 26,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK           = 27,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK           = 28,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK           = 29,</div><div class='add'>+    SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK           = 30,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLC_SRM_DRAM_SR             = 31,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLCG_SCRATCH_SR             = 32,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLCP_SCRATCH_SR             = 33,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLCV_SCRATCH_SR             = 34,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLX6_DRAM_SR                = 35,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLX6_DRAM_SR_CORE1          = 36,</div><div class='add'>+    SOC24_FIRMWARE_ID_RLCDEBUGLOG                 = 37,</div><div class='add'>+    SOC24_FIRMWARE_ID_SRIOV_DEBUG                 = 38,</div><div class='add'>+    SOC24_FIRMWARE_ID_SRIOV_CSA_RLC               = 39,</div><div class='add'>+    SOC24_FIRMWARE_ID_SRIOV_CSA_SDMA              = 40,</div><div class='add'>+    SOC24_FIRMWARE_ID_SRIOV_CSA_CP                = 41,</div><div class='add'>+    SOC24_FIRMWARE_ID_UMF_ZONE_PAD                = 42,</div><div class='add'>+    SOC24_FIRMWARE_ID_MAX                         = 43</div><div class='add'>+} SOC24_FIRMWARE_ID;</div><div class='add'>+</div><div class='ctx'> typedef struct _RLC_TABLE_OF_CONTENT {</div><div class='ctx'> 	union {</div><div class='ctx'> 		unsigned int	DW0;</div><div class='hunk'>@@ -155,6 +202,33 @@ typedef struct _RLC_TABLE_OF_CONTENT {</div><div class='ctx'> 	};</div><div class='ctx'> } RLC_TABLE_OF_CONTENT;</div><div class='ctx'> </div><div class='add'>+typedef struct _RLC_TABLE_OF_CONTENT_V2 {</div><div class='add'>+	union {</div><div class='add'>+		unsigned int    DW0;</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t offset         : 25;</div><div class='add'>+			uint32_t id             : 7;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		unsigned int    DW1;</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t reserved0              : 1;</div><div class='add'>+			uint32_t reserved1              : 1;</div><div class='add'>+			uint32_t reserved2              : 1;</div><div class='add'>+			uint32_t memory_destination     : 2;</div><div class='add'>+			uint32_t vfflr_image_code       : 4;</div><div class='add'>+			uint32_t reserved9              : 1;</div><div class='add'>+			uint32_t reserved10             : 1;</div><div class='add'>+			uint32_t reserved11             : 1;</div><div class='add'>+			uint32_t size_x16               : 1;</div><div class='add'>+			uint32_t reserved13             : 1;</div><div class='add'>+			uint32_t size                   : 18;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+} RLC_TABLE_OF_CONTENT_V2;</div><div class='add'>+</div><div class='ctx'> #define RLC_TOC_MAX_SIZE		64</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_rlc_funcs {</div><div class='hunk'>@@ -163,7 +237,21 @@ struct amdgpu_rlc_funcs {</div><div class='ctx'> 	void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);</div><div class='ctx'> 	int  (*init)(struct amdgpu_device *adev);</div><div class='ctx'> 	u32  (*get_csb_size)(struct amdgpu_device *adev);</div><div class='del'>-	void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @get_csb_buffer: Get the clear state to be put into the hardware.</div><div class='add'>+	 *</div><div class='add'>+	 * The parameter adev is used to get the CS data and other gfx info,</div><div class='add'>+	 * and buffer is the RLC CS pointer</div><div class='add'>+	 *</div><div class='add'>+	 * Sometimes, the user space puts a request to clear the state in the</div><div class='add'>+	 * command buffer; this function provides the clear state that gets put</div><div class='add'>+	 * into the hardware. Note that the driver programs Clear State</div><div class='add'>+	 * Indirect Buffer (CSB) explicitly when it sets up the kernel rings,</div><div class='add'>+	 * and it also provides a pointer to it which is used by the firmware</div><div class='add'>+	 * to load the clear state in some cases.</div><div class='add'>+	 */</div><div class='add'>+	void (*get_csb_buffer)(struct amdgpu_device *adev, u32 *buffer);</div><div class='ctx'> 	int  (*get_cp_table_num)(struct amdgpu_device *adev);</div><div class='ctx'> 	int  (*resume)(struct amdgpu_device *adev);</div><div class='ctx'> 	void (*stop)(struct amdgpu_device *adev);</div><div class='hunk'>@@ -187,19 +275,19 @@ struct amdgpu_rlc {</div><div class='ctx'> 	/* for power gating */</div><div class='ctx'> 	struct amdgpu_bo        *save_restore_obj;</div><div class='ctx'> 	uint64_t                save_restore_gpu_addr;</div><div class='del'>-	volatile uint32_t       *sr_ptr;</div><div class='add'>+	uint32_t		*sr_ptr;</div><div class='ctx'> 	const u32               *reg_list;</div><div class='ctx'> 	u32                     reg_list_size;</div><div class='ctx'> 	/* for clear state */</div><div class='ctx'> 	struct amdgpu_bo        *clear_state_obj;</div><div class='ctx'> 	uint64_t                clear_state_gpu_addr;</div><div class='del'>-	volatile uint32_t       *cs_ptr;</div><div class='add'>+	uint32_t		*cs_ptr;</div><div class='ctx'> 	const struct cs_section_def   *cs_data;</div><div class='ctx'> 	u32                     clear_state_size;</div><div class='ctx'> 	/* for cp tables */</div><div class='ctx'> 	struct amdgpu_bo        *cp_table_obj;</div><div class='ctx'> 	uint64_t                cp_table_gpu_addr;</div><div class='del'>-	volatile uint32_t       *cp_table_ptr;</div><div class='add'>+	uint32_t		*cp_table_ptr;</div><div class='ctx'> 	u32                     cp_table_size;</div><div class='ctx'> </div><div class='ctx'> 	/* safe mode for updating CG/PG state */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c<br/>index 10df731998b2..39070b2a4c04 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c</a></div><div class='hunk'>@@ -93,8 +93,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct drm_suballoc **sa_bo,</div><div class='del'>-		       struct dma_fence *fence)</div><div class='add'>+void amdgpu_sa_bo_free(struct drm_suballoc **sa_bo, struct dma_fence *fence)</div><div class='ctx'> {</div><div class='ctx'> 	if (sa_bo == NULL || *sa_bo == NULL) {</div><div class='ctx'> 		return;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c<br/>index 863b2a34b2d6..341beec59537 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c</a></div><div class='hunk'>@@ -22,7 +22,6 @@</div><div class='ctx'>  * Authors: Andres Rodriguez &lt;andresx7@gmail.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/fdtable.h&gt;</div><div class='ctx'> #include &lt;linux/file.h&gt;</div><div class='ctx'> #include &lt;linux/pid.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -36,21 +35,19 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,</div><div class='ctx'> 						  int fd,</div><div class='ctx'> 						  int32_t priority)</div><div class='ctx'> {</div><div class='del'>-	struct fd f = fdget(fd);</div><div class='add'>+	CLASS(fd, f)(fd);</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv;</div><div class='ctx'> 	struct amdgpu_ctx_mgr *mgr;</div><div class='ctx'> 	struct amdgpu_ctx *ctx;</div><div class='ctx'> 	uint32_t id;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (!f.file)</div><div class='add'>+	if (fd_empty(f))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_file_to_fpriv(f.file, &amp;fpriv);</div><div class='del'>-	if (r) {</div><div class='del'>-		fdput(f);</div><div class='add'>+	r = amdgpu_file_to_fpriv(fd_file(f), &amp;fpriv);</div><div class='add'>+	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	mgr = &amp;fpriv-&gt;ctx_mgr;</div><div class='ctx'> 	mutex_lock(&amp;mgr-&gt;lock);</div><div class='hunk'>@@ -58,7 +55,6 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,</div><div class='ctx'> 		amdgpu_ctx_priority_override(ctx, priority);</div><div class='ctx'> 	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	fdput(f);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -67,31 +63,25 @@ static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev,</div><div class='ctx'> 						  unsigned ctx_id,</div><div class='ctx'> 						  int32_t priority)</div><div class='ctx'> {</div><div class='del'>-	struct fd f = fdget(fd);</div><div class='add'>+	CLASS(fd, f)(fd);</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv;</div><div class='ctx'> 	struct amdgpu_ctx *ctx;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (!f.file)</div><div class='add'>+	if (fd_empty(f))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_file_to_fpriv(f.file, &amp;fpriv);</div><div class='del'>-	if (r) {</div><div class='del'>-		fdput(f);</div><div class='add'>+	r = amdgpu_file_to_fpriv(fd_file(f), &amp;fpriv);</div><div class='add'>+	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	ctx = amdgpu_ctx_get(fpriv, ctx_id);</div><div class='ctx'> </div><div class='del'>-	if (!ctx) {</div><div class='del'>-		fdput(f);</div><div class='add'>+	if (!ctx)</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ctx_priority_override(ctx, priority);</div><div class='ctx'> 	amdgpu_ctx_put(ctx);</div><div class='del'>-	fdput(f);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c<br/>index 1d9d187de6ee..8b8a04138711 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c</a></div><div class='hunk'>@@ -25,6 +25,9 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_sdma.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='add'>+#include "gc/gc_10_1_0_offset.h"</div><div class='add'>+#include "gc/gc_10_3_0_sh_mask.h"</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_CSA_SDMA_SIZE 64</div><div class='ctx'> /* SDMA CSA reside in the 3rd page of CSA */</div><div class='hunk'>@@ -75,22 +78,14 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev-&gt;gfx.mcbp)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='add'>+	r = amdgpu_sdma_get_index_from_ring(ring, &amp;index);</div><div class='ctx'> </div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  sdma[ring-&gt;idx].sdma_meta_data);</div><div class='del'>-		csa_mc_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_sdma_get_index_from_ring(ring, &amp;index);</div><div class='del'>-</div><div class='del'>-		if (r || index &gt; 31)</div><div class='del'>-			csa_mc_addr = 0;</div><div class='del'>-		else</div><div class='del'>-			csa_mc_addr = amdgpu_csa_vaddr(adev) +</div><div class='del'>-				AMDGPU_CSA_SDMA_OFFSET +</div><div class='del'>-				index * AMDGPU_CSA_SDMA_SIZE;</div><div class='del'>-	}</div><div class='add'>+	if (r || index &gt; 31)</div><div class='add'>+		csa_mc_addr = 0;</div><div class='add'>+	else</div><div class='add'>+		csa_mc_addr = amdgpu_csa_vaddr(adev) +</div><div class='add'>+			AMDGPU_CSA_SDMA_OFFSET +</div><div class='add'>+			index * AMDGPU_CSA_SDMA_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	return csa_mc_addr;</div><div class='ctx'> }</div><div class='hunk'>@@ -158,6 +153,7 @@ static int amdgpu_sdma_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)</div><div class='ctx'> 	const struct common_firmware_header *header = NULL;</div><div class='ctx'> 	const struct sdma_firmware_header_v1_0 *hdr;</div><div class='ctx'> 	const struct sdma_firmware_header_v2_0 *hdr_v2;</div><div class='add'>+	const struct sdma_firmware_header_v3_0 *hdr_v3;</div><div class='ctx'> </div><div class='ctx'> 	header = (const struct common_firmware_header *)</div><div class='ctx'> 		sdma_inst-&gt;fw-&gt;data;</div><div class='hunk'>@@ -174,6 +170,11 @@ static int amdgpu_sdma_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)</div><div class='ctx'> 		sdma_inst-&gt;fw_version = le32_to_cpu(hdr_v2-&gt;header.ucode_version);</div><div class='ctx'> 		sdma_inst-&gt;feature_version = le32_to_cpu(hdr_v2-&gt;ucode_feature_version);</div><div class='ctx'> 		break;</div><div class='add'>+	case 3:</div><div class='add'>+		hdr_v3 = (const struct sdma_firmware_header_v3_0 *)sdma_inst-&gt;fw-&gt;data;</div><div class='add'>+		sdma_inst-&gt;fw_version = le32_to_cpu(hdr_v3-&gt;header.ucode_version);</div><div class='add'>+		sdma_inst-&gt;feature_version = le32_to_cpu(hdr_v3-&gt;ucode_feature_version);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -206,16 +207,19 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 	const struct common_firmware_header *header = NULL;</div><div class='ctx'> 	int err, i;</div><div class='ctx'> 	const struct sdma_firmware_header_v2_0 *sdma_hdr;</div><div class='add'>+	const struct sdma_firmware_header_v3_0 *sdma_hv3;</div><div class='ctx'> 	uint16_t version_major;</div><div class='ctx'> 	char ucode_prefix[30];</div><div class='del'>-	char fw_name[52];</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='ctx'> 	if (instance == 0)</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[instance].fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s.bin", ucode_prefix);</div><div class='ctx'> 	else</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s%d.bin", ucode_prefix, instance);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[instance].fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[instance].fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s%d.bin", ucode_prefix, instance);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -251,11 +255,14 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 				else {</div><div class='ctx'> 					/* Use a single copy per SDMA firmware type. PSP uses the same instance for all</div><div class='ctx'> 					 * groups of SDMAs */</div><div class='del'>-					if (amdgpu_ip_version(adev, SDMA0_HWIP,</div><div class='del'>-							      0) ==</div><div class='del'>-						    IP_VERSION(4, 4, 2) &amp;&amp;</div><div class='add'>+					if ((amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==</div><div class='add'>+						IP_VERSION(4, 4, 2) ||</div><div class='add'>+					     amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==</div><div class='add'>+						IP_VERSION(4, 4, 4) ||</div><div class='add'>+					     amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==</div><div class='add'>+						IP_VERSION(4, 4, 5)) &amp;&amp;</div><div class='ctx'> 					    adev-&gt;firmware.load_type ==</div><div class='del'>-						    AMDGPU_FW_LOAD_PSP &amp;&amp;</div><div class='add'>+						AMDGPU_FW_LOAD_PSP &amp;&amp;</div><div class='ctx'> 					    adev-&gt;sdma.num_inst_per_aid == i) {</div><div class='ctx'> 						break;</div><div class='ctx'> 					}</div><div class='hunk'>@@ -281,6 +288,15 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 			adev-&gt;firmware.fw_size +=</div><div class='ctx'> 				ALIGN(le32_to_cpu(sdma_hdr-&gt;ctl_ucode_size_bytes), PAGE_SIZE);</div><div class='ctx'> 			break;</div><div class='add'>+		case 3:</div><div class='add'>+			sdma_hv3 = (const struct sdma_firmware_header_v3_0 *)</div><div class='add'>+				adev-&gt;sdma.instance[0].fw-&gt;data;</div><div class='add'>+			info = &amp;adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_SDMA_RS64];</div><div class='add'>+			info-&gt;ucode_id = AMDGPU_UCODE_ID_SDMA_RS64;</div><div class='add'>+			info-&gt;fw = adev-&gt;sdma.instance[0].fw;</div><div class='add'>+			adev-&gt;firmware.fw_size +=</div><div class='add'>+				ALIGN(le32_to_cpu(sdma_hv3-&gt;ucode_size_bytes), PAGE_SIZE);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			err = -EINVAL;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -326,3 +342,270 @@ int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * debugfs for to enable/disable sdma job submission to specific core.</div><div class='add'>+ */</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int amdgpu_debugfs_sdma_sched_mask_set(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u64 i, num_ring;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring, *page = NULL;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	/* Determine the number of rings per SDMA instance</div><div class='add'>+	 * (1 for sdma gfx ring, 2 if page queue exists)</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+		num_ring = 2;</div><div class='add'>+	else</div><div class='add'>+		num_ring = 1;</div><div class='add'>+</div><div class='add'>+	/* Calculate the maximum possible mask value</div><div class='add'>+	 * based on the number of SDMA instances and rings</div><div class='add'>+	*/</div><div class='add'>+	mask = BIT_ULL(adev-&gt;sdma.num_instances * num_ring) - 1;</div><div class='add'>+</div><div class='add'>+	if ((val &amp; mask) == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+		if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+			page = &amp;adev-&gt;sdma.instance[i].page;</div><div class='add'>+		if (val &amp; BIT_ULL(i * num_ring))</div><div class='add'>+			ring-&gt;sched.ready = true;</div><div class='add'>+		else</div><div class='add'>+			ring-&gt;sched.ready = false;</div><div class='add'>+</div><div class='add'>+		if (page) {</div><div class='add'>+			if (val &amp; BIT_ULL(i * num_ring + 1))</div><div class='add'>+				page-&gt;sched.ready = true;</div><div class='add'>+			else</div><div class='add'>+				page-&gt;sched.ready = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/* publish sched.ready flag update effective immediately across smp */</div><div class='add'>+	smp_rmb();</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u64 i, num_ring;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring, *page = NULL;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	/* Determine the number of rings per SDMA instance</div><div class='add'>+	 * (1 for sdma gfx ring, 2 if page queue exists)</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+		num_ring = 2;</div><div class='add'>+	else</div><div class='add'>+		num_ring = 1;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+		if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+			page = &amp;adev-&gt;sdma.instance[i].page;</div><div class='add'>+</div><div class='add'>+		if (ring-&gt;sched.ready)</div><div class='add'>+			mask |= BIT_ULL(i * num_ring);</div><div class='add'>+		else</div><div class='add'>+			mask &amp;= ~BIT_ULL(i * num_ring);</div><div class='add'>+</div><div class='add'>+		if (page) {</div><div class='add'>+			if (page-&gt;sched.ready)</div><div class='add'>+				mask |= BIT_ULL(i * num_ring + 1);</div><div class='add'>+			else</div><div class='add'>+				mask &amp;= ~BIT_ULL(i * num_ring + 1);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = mask;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops,</div><div class='add'>+			 amdgpu_debugfs_sdma_sched_mask_get,</div><div class='add'>+			 amdgpu_debugfs_sdma_sched_mask_set, "%llx\n");</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	char name[32];</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;sdma.num_instances &gt; 1))</div><div class='add'>+		return;</div><div class='add'>+	sprintf(name, "amdgpu_sdma_sched_mask");</div><div class='add'>+	debugfs_create_file(name, 0600, root, adev,</div><div class='add'>+			    &amp;amdgpu_debugfs_sdma_sched_mask_fops);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_get_sdma_reset_mask(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	return amdgpu_show_reset_mask(buf, adev-&gt;sdma.supported_reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR(sdma_reset_mask, 0444,</div><div class='add'>+		   amdgpu_get_sdma_reset_mask, NULL);</div><div class='add'>+</div><div class='add'>+int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_gpu_recovery)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;sdma.num_instances) {</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_sdma_reset_mask);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_gpu_recovery)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd) {</div><div class='add'>+		if (adev-&gt;sdma.num_instances)</div><div class='add'>+			device_remove_file(adev-&gt;dev, &amp;dev_attr_sdma_reset_mask);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct amdgpu_ring *amdgpu_sdma_get_shared_ring(struct amdgpu_device *adev, struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;sdma.has_page_queue &amp;&amp;</div><div class='add'>+	    (ring-&gt;me &lt; adev-&gt;sdma.num_instances) &amp;&amp;</div><div class='add'>+	    (ring == &amp;adev-&gt;sdma.instance[ring-&gt;me].ring))</div><div class='add'>+		return &amp;adev-&gt;sdma.instance[ring-&gt;me].page;</div><div class='add'>+	else</div><div class='add'>+		return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+* amdgpu_sdma_is_shared_inv_eng - Check if a ring is an SDMA ring that shares a VM invalidation engine</div><div class='add'>+* @adev: Pointer to the AMDGPU device structure</div><div class='add'>+* @ring: Pointer to the ring structure to check</div><div class='add'>+*</div><div class='add'>+* This function checks if the given ring is an SDMA ring that shares a VM invalidation engine.</div><div class='add'>+* It returns true if the ring is such an SDMA ring, false otherwise.</div><div class='add'>+*/</div><div class='add'>+bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	int i = ring-&gt;me;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.has_page_queue || i &gt;= adev-&gt;sdma.num_instances)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))</div><div class='add'>+		return (ring == &amp;adev-&gt;sdma.instance[i].page);</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_sdma_instance *sdma_instance = &amp;adev-&gt;sdma.instance[instance_id];</div><div class='add'>+</div><div class='add'>+	if (sdma_instance-&gt;funcs-&gt;soft_reset_kernel_queue)</div><div class='add'>+		return sdma_instance-&gt;funcs-&gt;soft_reset_kernel_queue(adev, instance_id);</div><div class='add'>+</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_sdma_reset_engine - Reset a specific SDMA engine</div><div class='add'>+ * @adev: Pointer to the AMDGPU device</div><div class='add'>+ * @instance_id: Logical ID of the SDMA engine instance to reset</div><div class='add'>+ * @caller_handles_kernel_queues: Skip kernel queue processing. Caller</div><div class='add'>+ * will handle it.</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success, or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,</div><div class='add'>+			     bool caller_handles_kernel_queues)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	struct amdgpu_sdma_instance *sdma_instance = &amp;adev-&gt;sdma.instance[instance_id];</div><div class='add'>+	struct amdgpu_ring *gfx_ring = &amp;sdma_instance-&gt;ring;</div><div class='add'>+	struct amdgpu_ring *page_ring = &amp;sdma_instance-&gt;page;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;sdma_instance-&gt;engine_reset_mutex);</div><div class='add'>+</div><div class='add'>+	if (!caller_handles_kernel_queues) {</div><div class='add'>+		/* Stop the scheduler's work queue for the GFX and page rings if they are running.</div><div class='add'>+		 * This ensures that no new tasks are submitted to the queues while</div><div class='add'>+		 * the reset is in progress.</div><div class='add'>+		 */</div><div class='add'>+		drm_sched_wqueue_stop(&amp;gfx_ring-&gt;sched);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+			drm_sched_wqueue_stop(&amp;page_ring-&gt;sched);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (sdma_instance-&gt;funcs-&gt;stop_kernel_queue) {</div><div class='add'>+		sdma_instance-&gt;funcs-&gt;stop_kernel_queue(gfx_ring);</div><div class='add'>+		if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+			sdma_instance-&gt;funcs-&gt;stop_kernel_queue(page_ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Perform the SDMA reset for the specified instance */</div><div class='add'>+	ret = amdgpu_sdma_soft_reset(adev, instance_id);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to reset SDMA logical instance %u\n", instance_id);</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (sdma_instance-&gt;funcs-&gt;start_kernel_queue) {</div><div class='add'>+		sdma_instance-&gt;funcs-&gt;start_kernel_queue(gfx_ring);</div><div class='add'>+		if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+			sdma_instance-&gt;funcs-&gt;start_kernel_queue(page_ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+exit:</div><div class='add'>+	if (!caller_handles_kernel_queues) {</div><div class='add'>+		/* Restart the scheduler's work queue for the GFX and page rings</div><div class='add'>+		 * if they were stopped by this function. This allows new tasks</div><div class='add'>+		 * to be submitted to the queues after the reset is complete.</div><div class='add'>+		 */</div><div class='add'>+		if (!ret) {</div><div class='add'>+			amdgpu_fence_driver_force_completion(gfx_ring);</div><div class='add'>+			drm_sched_wqueue_start(&amp;gfx_ring-&gt;sched);</div><div class='add'>+			if (adev-&gt;sdma.has_page_queue) {</div><div class='add'>+				amdgpu_fence_driver_force_completion(page_ring);</div><div class='add'>+				drm_sched_wqueue_start(&amp;page_ring-&gt;sched);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;sdma_instance-&gt;engine_reset_mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h<br/>index 173a2a308078..34311f32be4c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h</a></div><div class='hunk'>@@ -50,6 +50,12 @@ enum amdgpu_sdma_irq {</div><div class='ctx'> </div><div class='ctx'> #define NUM_SDMA(x) hweight32(x)</div><div class='ctx'> </div><div class='add'>+struct amdgpu_sdma_funcs {</div><div class='add'>+	int (*stop_kernel_queue)(struct amdgpu_ring *ring);</div><div class='add'>+	int (*start_kernel_queue)(struct amdgpu_ring *ring);</div><div class='add'>+	int (*soft_reset_kernel_queue)(struct amdgpu_device *adev, u32 instance_id);</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_sdma_instance {</div><div class='ctx'> 	/* SDMA firmware */</div><div class='ctx'> 	const struct firmware	*fw;</div><div class='hunk'>@@ -60,6 +66,15 @@ struct amdgpu_sdma_instance {</div><div class='ctx'> 	struct amdgpu_ring	page;</div><div class='ctx'> 	bool			burst_nop;</div><div class='ctx'> 	uint32_t		aid_id;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_bo	*sdma_fw_obj;</div><div class='add'>+	uint64_t		sdma_fw_gpu_addr;</div><div class='add'>+	uint32_t		*sdma_fw_ptr;</div><div class='add'>+	struct mutex		engine_reset_mutex;</div><div class='add'>+	/* track guilty state of GFX and PAGE queues */</div><div class='add'>+	bool			gfx_guilty;</div><div class='add'>+	bool			page_guilty;</div><div class='add'>+	const struct amdgpu_sdma_funcs   *funcs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_sdma_ras_memory_id {</div><div class='hunk'>@@ -98,11 +113,13 @@ struct amdgpu_sdma {</div><div class='ctx'> 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];</div><div class='ctx'> 	struct amdgpu_irq_src	trap_irq;</div><div class='ctx'> 	struct amdgpu_irq_src	illegal_inst_irq;</div><div class='add'>+	struct amdgpu_irq_src	fence_irq;</div><div class='ctx'> 	struct amdgpu_irq_src	ecc_irq;</div><div class='ctx'> 	struct amdgpu_irq_src	vm_hole_irq;</div><div class='ctx'> 	struct amdgpu_irq_src	doorbell_invalid_irq;</div><div class='ctx'> 	struct amdgpu_irq_src	pool_timeout_irq;</div><div class='ctx'> 	struct amdgpu_irq_src	srbm_write_irq;</div><div class='add'>+	struct amdgpu_irq_src	ctxt_empty_irq;</div><div class='ctx'> </div><div class='ctx'> 	int			num_instances;</div><div class='ctx'> 	uint32_t 		sdma_mask;</div><div class='hunk'>@@ -111,6 +128,11 @@ struct amdgpu_sdma {</div><div class='ctx'> 	bool			has_page_queue;</div><div class='ctx'> 	struct ras_common_if	*ras_if;</div><div class='ctx'> 	struct amdgpu_sdma_ras	*ras;</div><div class='add'>+	uint32_t		*ip_dump;</div><div class='add'>+	uint32_t 		supported_reset;</div><div class='add'>+	struct list_head	reset_callback_list;</div><div class='add'>+	bool			no_user_submission;</div><div class='add'>+	bool			disable_uq;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -132,7 +154,7 @@ struct amdgpu_buffer_funcs {</div><div class='ctx'> 				 uint64_t dst_offset,</div><div class='ctx'> 				 /* number of byte to transfer */</div><div class='ctx'> 				 uint32_t byte_count,</div><div class='del'>-				 bool tmz);</div><div class='add'>+				 uint32_t copy_flags);</div><div class='ctx'> </div><div class='ctx'> 	/* maximum bytes in a single operation */</div><div class='ctx'> 	uint32_t	fill_max_bytes;</div><div class='hunk'>@@ -150,6 +172,9 @@ struct amdgpu_buffer_funcs {</div><div class='ctx'> 				 uint32_t byte_count);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,</div><div class='add'>+			     bool caller_handles_kernel_queues);</div><div class='add'>+</div><div class='ctx'> #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)-&gt;mman.buffer_funcs-&gt;emit_copy_buffer((ib),  (s), (d), (b), (t))</div><div class='ctx'> #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)-&gt;mman.buffer_funcs-&gt;emit_fill_buffer((ib), (s), (d), (b))</div><div class='ctx'> </div><div class='hunk'>@@ -170,5 +195,10 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev, u32 instance,</div><div class='ctx'> void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev,</div><div class='ctx'>         bool duplicate);</div><div class='ctx'> int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev);</div><div class='del'>-</div><div class='add'>+void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_sdma_sysfs_reset_mask_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_sdma_sysfs_reset_mask_fini(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_sdma_is_shared_inv_eng(struct amdgpu_device *adev, struct amdgpu_ring *ring);</div><div class='add'>+struct amdgpu_ring *amdgpu_sdma_get_shared_ring(struct amdgpu_device *adev,</div><div class='add'>+	struct amdgpu_ring *ring);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c<br/>index 8ed0e073656f..3739be1b71e0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c</a></div><div class='hunk'>@@ -135,6 +135,10 @@ static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __u</div><div class='ctx'> 		mutex_unlock(&amp;psp-&gt;securedisplay_context.mutex);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='add'>+		if (size &lt; 3 || phy_id &gt;= TA_SECUREDISPLAY_MAX_PHY) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid input: %s\n", str);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 		mutex_lock(&amp;psp-&gt;securedisplay_context.mutex);</div><div class='ctx'> 		psp_prep_securedisplay_cmd_buf(psp, &amp;securedisplay_cmd,</div><div class='ctx'> 			TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);</div><div class='hunk'>@@ -155,7 +159,6 @@ static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __u</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Invalid input: %s\n", str);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return size;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c<br/>index e22cb2b5cd92..a0b479d5fff1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c</a></div><div class='hunk'>@@ -45,7 +45,11 @@</div><div class='ctx'>  */</div><div class='ctx'> static inline u64 amdgpu_seq64_get_va_base(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return AMDGPU_VA_RESERVED_SEQ64_START(adev);</div><div class='add'>+	u64 addr = AMDGPU_VA_RESERVED_SEQ64_START(adev);</div><div class='add'>+</div><div class='add'>+	addr = amdgpu_gmc_sign_extend(addr);</div><div class='add'>+</div><div class='add'>+	return addr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -88,9 +92,11 @@ int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	seq64_addr = amdgpu_seq64_get_va_base(adev);</div><div class='del'>-	r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, AMDGPU_VA_RESERVED_SEQ64_SIZE,</div><div class='del'>-			     AMDGPU_PTE_READABLE);</div><div class='add'>+	seq64_addr = amdgpu_seq64_get_va_base(adev) &amp; AMDGPU_GMC_HOLE_MASK;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0,</div><div class='add'>+			     AMDGPU_VA_RESERVED_SEQ64_SIZE,</div><div class='add'>+			     AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_MTYPE_UC);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("failed to do bo_map on userq sem, err=%d\n", r);</div><div class='ctx'> 		amdgpu_vm_bo_del(adev, *bo_va);</div><div class='hunk'>@@ -133,7 +139,7 @@ void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv)</div><div class='ctx'> </div><div class='ctx'> 	vm = &amp;fpriv-&gt;vm;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='ctx'> 		if (likely(!r))</div><div class='hunk'>@@ -156,6 +162,7 @@ error:</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @va: VA to access the seq in process address space</div><div class='add'>+ * @gpu_addr: GPU address to access the seq</div><div class='ctx'>  * @cpu_addr: CPU address to access the seq</div><div class='ctx'>  *</div><div class='ctx'>  * Alloc a 64 bit memory from seq64 pool.</div><div class='hunk'>@@ -163,7 +170,8 @@ error:</div><div class='ctx'>  * Returns:</div><div class='ctx'>  * 0 on success or a negative error code on failure</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 **cpu_addr)</div><div class='add'>+int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va,</div><div class='add'>+		       u64 *gpu_addr, u64 **cpu_addr)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long bit_pos;</div><div class='ctx'> </div><div class='hunk'>@@ -172,7 +180,12 @@ int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 **cpu_addr)</div><div class='ctx'> 		return -ENOSPC;</div><div class='ctx'> </div><div class='ctx'> 	__set_bit(bit_pos, adev-&gt;seq64.used);</div><div class='add'>+</div><div class='ctx'> 	*va = bit_pos * sizeof(u64) + amdgpu_seq64_get_va_base(adev);</div><div class='add'>+</div><div class='add'>+	if (gpu_addr)</div><div class='add'>+		*gpu_addr = bit_pos * sizeof(u64) + adev-&gt;seq64.gpu_addr;</div><div class='add'>+</div><div class='ctx'> 	*cpu_addr = bit_pos + adev-&gt;seq64.cpu_base_addr;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -233,7 +246,7 @@ int amdgpu_seq64_init(struct amdgpu_device *adev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	r = amdgpu_bo_create_kernel(adev, AMDGPU_VA_RESERVED_SEQ64_SIZE,</div><div class='ctx'> 				    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;adev-&gt;seq64.sbo, NULL,</div><div class='add'>+				    &amp;adev-&gt;seq64.sbo, &amp;adev-&gt;seq64.gpu_addr,</div><div class='ctx'> 				    (void **)&amp;adev-&gt;seq64.cpu_base_addr);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "(%d) create seq64 failed\n", r);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h<br/>index 4203b2ab318d..26a249aaaee1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h</a></div><div class='hunk'>@@ -32,13 +32,14 @@</div><div class='ctx'> struct amdgpu_seq64 {</div><div class='ctx'> 	struct amdgpu_bo *sbo;</div><div class='ctx'> 	u32 num_sem;</div><div class='add'>+	u64 gpu_addr;</div><div class='ctx'> 	u64 *cpu_base_addr;</div><div class='ctx'> 	DECLARE_BITMAP(used, AMDGPU_MAX_SEQ64_SLOTS);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void amdgpu_seq64_fini(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_seq64_init(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64 **cpu_addr);</div><div class='add'>+int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 *gpu_addr, u64 **cpu_addr);</div><div class='ctx'> void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);</div><div class='ctx'> int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		     struct amdgpu_bo_va **bo_va);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h<br/>index ff4435181055..ec9d12f85f39 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h</a></div><div class='hunk'>@@ -44,6 +44,7 @@ struct amdgpu_smuio_funcs {</div><div class='ctx'> 	u32 (*get_socket_id)(struct amdgpu_device *adev);</div><div class='ctx'> 	enum amdgpu_pkg_type (*get_pkg_type)(struct amdgpu_device *adev);</div><div class='ctx'> 	bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev);</div><div class='add'>+	u64 (*get_gpu_clock_counter)(struct amdgpu_device *adev);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_smuio {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c<br/>index bdf1ef825d89..d6ae9974c952 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c</a></div><div class='hunk'>@@ -135,11 +135,16 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f)</div><div class='ctx'> 	struct amdgpu_sync_entry *e;</div><div class='ctx'> </div><div class='ctx'> 	hash_for_each_possible(sync-&gt;fences, e, node, f-&gt;context) {</div><div class='del'>-		if (unlikely(e-&gt;fence-&gt;context != f-&gt;context))</div><div class='del'>-			continue;</div><div class='add'>+		if (dma_fence_is_signaled(e-&gt;fence)) {</div><div class='add'>+			dma_fence_put(e-&gt;fence);</div><div class='add'>+			e-&gt;fence = dma_fence_get(f);</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		amdgpu_sync_keep_later(&amp;e-&gt;fence, f);</div><div class='del'>-		return true;</div><div class='add'>+		if (likely(e-&gt;fence-&gt;context == f-&gt;context)) {</div><div class='add'>+			amdgpu_sync_keep_later(&amp;e-&gt;fence, f);</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -149,10 +154,12 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f)</div><div class='ctx'>  *</div><div class='ctx'>  * @sync: sync object to add fence to</div><div class='ctx'>  * @f: fence to sync to</div><div class='add'>+ * @flags: memory allocation flags to use when allocating sync entry</div><div class='ctx'>  *</div><div class='ctx'>  * Add the fence to the sync object.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f)</div><div class='add'>+int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,</div><div class='add'>+		      gfp_t flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_sync_entry *e;</div><div class='ctx'> </div><div class='hunk'>@@ -162,7 +169,7 @@ int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f)</div><div class='ctx'> 	if (amdgpu_sync_add_later(sync, f))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);</div><div class='add'>+	e = kmem_cache_alloc(amdgpu_sync_slab, flags);</div><div class='ctx'> 	if (!e)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -242,14 +249,13 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,</div><div class='ctx'> </div><div class='ctx'> 	if (resv == NULL)</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	/* TODO: Use DMA_RESV_USAGE_READ here */</div><div class='del'>-	dma_resv_for_each_fence(&amp;cursor, resv, DMA_RESV_USAGE_BOOKKEEP, f) {</div><div class='add'>+	/* Implicitly sync only to KERNEL, WRITE and READ */</div><div class='add'>+	dma_resv_for_each_fence(&amp;cursor, resv, DMA_RESV_USAGE_READ, f) {</div><div class='ctx'> 		dma_fence_chain_for_each(f, f) {</div><div class='ctx'> 			struct dma_fence *tmp = dma_fence_chain_contained(f);</div><div class='ctx'> </div><div class='ctx'> 			if (amdgpu_sync_test_fence(adev, mode, owner, tmp)) {</div><div class='del'>-				r = amdgpu_sync_fence(sync, f);</div><div class='add'>+				r = amdgpu_sync_fence(sync, f, GFP_KERNEL);</div><div class='ctx'> 				dma_fence_put(f);</div><div class='ctx'> 				if (r)</div><div class='ctx'> 					return r;</div><div class='hunk'>@@ -260,6 +266,36 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_sync_kfd - sync to KFD fences</div><div class='add'>+ *</div><div class='add'>+ * @sync: sync object to add KFD fences to</div><div class='add'>+ * @resv: reservation object with KFD fences</div><div class='add'>+ *</div><div class='add'>+ * Extract all KFD fences and add them to the sync object.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_sync_kfd(struct amdgpu_sync *sync, struct dma_resv *resv)</div><div class='add'>+{</div><div class='add'>+	struct dma_resv_iter cursor;</div><div class='add'>+	struct dma_fence *f;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	dma_resv_iter_begin(&amp;cursor, resv, DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	dma_resv_for_each_fence_unlocked(&amp;cursor, f) {</div><div class='add'>+		void *fence_owner = amdgpu_sync_get_owner(f);</div><div class='add'>+</div><div class='add'>+		if (fence_owner != AMDGPU_FENCE_OWNER_KFD)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_sync_fence(sync, f, GFP_KERNEL);</div><div class='add'>+		if (r)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	dma_resv_iter_end(&amp;cursor);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Free the entry back to the slab */</div><div class='ctx'> static void amdgpu_sync_entry_free(struct amdgpu_sync_entry *e)</div><div class='ctx'> {</div><div class='hunk'>@@ -358,7 +394,7 @@ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone)</div><div class='ctx'> 	hash_for_each_safe(source-&gt;fences, i, tmp, e, node) {</div><div class='ctx'> 		f = e-&gt;fence;</div><div class='ctx'> 		if (!dma_fence_is_signaled(f)) {</div><div class='del'>-			r = amdgpu_sync_fence(clone, f);</div><div class='add'>+			r = amdgpu_sync_fence(clone, f, GFP_KERNEL);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -370,6 +406,25 @@ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_sync_move - move all fences from src to dst</div><div class='add'>+ *</div><div class='add'>+ * @src: source of the fences, empty after function</div><div class='add'>+ * @dst: destination for the fences</div><div class='add'>+ *</div><div class='add'>+ * Moves all fences from source to destination. All fences in destination are</div><div class='add'>+ * freed and source is empty after the function call.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_sync_move(struct amdgpu_sync *src, struct amdgpu_sync *dst)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	amdgpu_sync_free(dst);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; HASH_SIZE(src-&gt;fences); ++i)</div><div class='add'>+		hlist_move_list(&amp;src-&gt;fences[i], &amp;dst-&gt;fences[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_sync_push_to_job - push fences into job</div><div class='ctx'>  * @sync: sync object to get the fences from</div><div class='ctx'>  * @job: job to push the fences into</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h<br/>index cf1e9e858efd..51eb4382c91e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h</a></div><div class='hunk'>@@ -47,14 +47,17 @@ struct amdgpu_sync {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void amdgpu_sync_create(struct amdgpu_sync *sync);</div><div class='del'>-int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f);</div><div class='add'>+int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,</div><div class='add'>+		      gfp_t flags);</div><div class='ctx'> int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,</div><div class='ctx'> 		     struct dma_resv *resv, enum amdgpu_sync_mode mode,</div><div class='ctx'> 		     void *owner);</div><div class='add'>+int amdgpu_sync_kfd(struct amdgpu_sync *sync, struct dma_resv *resv);</div><div class='ctx'> struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,</div><div class='ctx'> 				     struct amdgpu_ring *ring);</div><div class='ctx'> struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);</div><div class='ctx'> int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);</div><div class='add'>+void amdgpu_sync_move(struct amdgpu_sync *src, struct amdgpu_sync *dst);</div><div class='ctx'> int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job);</div><div class='ctx'> int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);</div><div class='ctx'> void amdgpu_sync_free(struct amdgpu_sync *sync);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h<br/>index f539b1d00234..d13e64a69e25 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h</a></div><div class='hunk'>@@ -167,25 +167,23 @@ TRACE_EVENT(amdgpu_cs_ioctl,</div><div class='ctx'> 	    TP_PROTO(struct amdgpu_job *job),</div><div class='ctx'> 	    TP_ARGS(job),</div><div class='ctx'> 	    TP_STRUCT__entry(</div><div class='del'>-			     __field(uint64_t, sched_job_id)</div><div class='ctx'> 			     __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))</div><div class='del'>-			     __field(unsigned int, context)</div><div class='del'>-			     __field(unsigned int, seqno)</div><div class='add'>+			     __field(u64, context)</div><div class='add'>+			     __field(u64, seqno)</div><div class='ctx'> 			     __field(struct dma_fence *, fence)</div><div class='ctx'> 			     __string(ring, to_amdgpu_ring(job-&gt;base.sched)-&gt;name)</div><div class='ctx'> 			     __field(u32, num_ibs)</div><div class='ctx'> 			     ),</div><div class='ctx'> </div><div class='ctx'> 	    TP_fast_assign(</div><div class='del'>-			   __entry-&gt;sched_job_id = job-&gt;base.id;</div><div class='del'>-			   __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job));</div><div class='add'>+			   __assign_str(timeline);</div><div class='ctx'> 			   __entry-&gt;context = job-&gt;base.s_fence-&gt;finished.context;</div><div class='ctx'> 			   __entry-&gt;seqno = job-&gt;base.s_fence-&gt;finished.seqno;</div><div class='del'>-			   __assign_str(ring, to_amdgpu_ring(job-&gt;base.sched)-&gt;name);</div><div class='add'>+			   __assign_str(ring);</div><div class='ctx'> 			   __entry-&gt;num_ibs = job-&gt;num_ibs;</div><div class='ctx'> 			   ),</div><div class='del'>-	    TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",</div><div class='del'>-		      __entry-&gt;sched_job_id, __get_str(timeline), __entry-&gt;context,</div><div class='add'>+	    TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u",</div><div class='add'>+		      __get_str(timeline), __entry-&gt;context,</div><div class='ctx'> 		      __entry-&gt;seqno, __get_str(ring), __entry-&gt;num_ibs)</div><div class='ctx'> );</div><div class='ctx'> </div><div class='hunk'>@@ -193,24 +191,22 @@ TRACE_EVENT(amdgpu_sched_run_job,</div><div class='ctx'> 	    TP_PROTO(struct amdgpu_job *job),</div><div class='ctx'> 	    TP_ARGS(job),</div><div class='ctx'> 	    TP_STRUCT__entry(</div><div class='del'>-			     __field(uint64_t, sched_job_id)</div><div class='ctx'> 			     __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))</div><div class='del'>-			     __field(unsigned int, context)</div><div class='del'>-			     __field(unsigned int, seqno)</div><div class='add'>+			     __field(u64, context)</div><div class='add'>+			     __field(u64, seqno)</div><div class='ctx'> 			     __string(ring, to_amdgpu_ring(job-&gt;base.sched)-&gt;name)</div><div class='ctx'> 			     __field(u32, num_ibs)</div><div class='ctx'> 			     ),</div><div class='ctx'> </div><div class='ctx'> 	    TP_fast_assign(</div><div class='del'>-			   __entry-&gt;sched_job_id = job-&gt;base.id;</div><div class='del'>-			   __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job));</div><div class='add'>+			   __assign_str(timeline);</div><div class='ctx'> 			   __entry-&gt;context = job-&gt;base.s_fence-&gt;finished.context;</div><div class='ctx'> 			   __entry-&gt;seqno = job-&gt;base.s_fence-&gt;finished.seqno;</div><div class='del'>-			   __assign_str(ring, to_amdgpu_ring(job-&gt;base.sched)-&gt;name);</div><div class='add'>+			   __assign_str(ring);</div><div class='ctx'> 			   __entry-&gt;num_ibs = job-&gt;num_ibs;</div><div class='ctx'> 			   ),</div><div class='del'>-	    TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",</div><div class='del'>-		      __entry-&gt;sched_job_id, __get_str(timeline), __entry-&gt;context,</div><div class='add'>+	    TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u",</div><div class='add'>+		      __get_str(timeline), __entry-&gt;context,</div><div class='ctx'> 		      __entry-&gt;seqno, __get_str(ring), __entry-&gt;num_ibs)</div><div class='ctx'> );</div><div class='ctx'> </div><div class='hunk'>@@ -231,7 +227,7 @@ TRACE_EVENT(amdgpu_vm_grab_id,</div><div class='ctx'> </div><div class='ctx'> 	    TP_fast_assign(</div><div class='ctx'> 			   __entry-&gt;pasid = vm-&gt;pasid;</div><div class='del'>-			   __assign_str(ring, ring-&gt;name);</div><div class='add'>+			   __assign_str(ring);</div><div class='ctx'> 			   __entry-&gt;vmid = job-&gt;vmid;</div><div class='ctx'> 			   __entry-&gt;vm_hub = ring-&gt;vm_hub,</div><div class='ctx'> 			   __entry-&gt;pd_addr = job-&gt;vm_pd_addr;</div><div class='hunk'>@@ -425,7 +421,7 @@ TRACE_EVENT(amdgpu_vm_flush,</div><div class='ctx'> 			     ),</div><div class='ctx'> </div><div class='ctx'> 	    TP_fast_assign(</div><div class='del'>-			   __assign_str(ring, ring-&gt;name);</div><div class='add'>+			   __assign_str(ring);</div><div class='ctx'> 			   __entry-&gt;vmid = vmid;</div><div class='ctx'> 			   __entry-&gt;vm_hub = ring-&gt;vm_hub;</div><div class='ctx'> 			   __entry-&gt;pd_addr = pd_addr;</div><div class='hunk'>@@ -457,6 +453,38 @@ DEFINE_EVENT(amdgpu_pasid, amdgpu_pasid_freed,</div><div class='ctx'> 	    TP_ARGS(pasid)</div><div class='ctx'> );</div><div class='ctx'> </div><div class='add'>+TRACE_EVENT(amdgpu_isolation,</div><div class='add'>+	    TP_PROTO(void *prev, void *next),</div><div class='add'>+	    TP_ARGS(prev, next),</div><div class='add'>+	    TP_STRUCT__entry(</div><div class='add'>+			     __field(void *, prev)</div><div class='add'>+			     __field(void *, next)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+	    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;prev = prev;</div><div class='add'>+			   __entry-&gt;next = next;</div><div class='add'>+			   ),</div><div class='add'>+	    TP_printk("prev=%p, next=%p",</div><div class='add'>+		      __entry-&gt;prev,</div><div class='add'>+		      __entry-&gt;next)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+TRACE_EVENT(amdgpu_cleaner_shader,</div><div class='add'>+	    TP_PROTO(struct amdgpu_ring *ring, struct dma_fence *fence),</div><div class='add'>+	    TP_ARGS(ring, fence),</div><div class='add'>+	    TP_STRUCT__entry(</div><div class='add'>+			     __string(ring, ring-&gt;name)</div><div class='add'>+			     __field(u64, seqno)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+	    TP_fast_assign(</div><div class='add'>+			   __assign_str(ring);</div><div class='add'>+			   __entry-&gt;seqno = fence-&gt;seqno;</div><div class='add'>+			   ),</div><div class='add'>+	    TP_printk("ring=%s, seqno=%Lu", __get_str(ring), __entry-&gt;seqno)</div><div class='add'>+);</div><div class='add'>+</div><div class='ctx'> TRACE_EVENT(amdgpu_bo_list_set,</div><div class='ctx'> 	    TP_PROTO(struct amdgpu_bo_list *list, struct amdgpu_bo *bo),</div><div class='ctx'> 	    TP_ARGS(list, bo),</div><div class='hunk'>@@ -519,23 +547,19 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,</div><div class='ctx'> 	    TP_ARGS(sched_job, fence),</div><div class='ctx'> 	    TP_STRUCT__entry(</div><div class='ctx'> 			     __string(ring, sched_job-&gt;base.sched-&gt;name)</div><div class='del'>-			     __field(uint64_t, id)</div><div class='ctx'> 			     __field(struct dma_fence *, fence)</div><div class='del'>-			     __field(uint64_t, ctx)</div><div class='del'>-			     __field(unsigned, seqno)</div><div class='add'>+			     __field(u64, ctx)</div><div class='add'>+			     __field(u64, seqno)</div><div class='ctx'> 			     ),</div><div class='ctx'> </div><div class='ctx'> 	    TP_fast_assign(</div><div class='del'>-			   __assign_str(ring, sched_job-&gt;base.sched-&gt;name);</div><div class='del'>-			   __entry-&gt;id = sched_job-&gt;base.id;</div><div class='add'>+			   __assign_str(ring);</div><div class='ctx'> 			   __entry-&gt;fence = fence;</div><div class='ctx'> 			   __entry-&gt;ctx = fence-&gt;context;</div><div class='ctx'> 			   __entry-&gt;seqno = fence-&gt;seqno;</div><div class='ctx'> 			   ),</div><div class='del'>-	    TP_printk("job ring=%s, id=%llu, need pipe sync to fence=%p, context=%llu, seq=%u",</div><div class='del'>-		      __get_str(ring), __entry-&gt;id,</div><div class='del'>-		      __entry-&gt;fence, __entry-&gt;ctx,</div><div class='del'>-		      __entry-&gt;seqno)</div><div class='add'>+	    TP_printk("job ring=%s need pipe sync to fence=%llu:%llu",</div><div class='add'>+		      __get_str(ring), __entry-&gt;ctx, __entry-&gt;seqno)</div><div class='ctx'> );</div><div class='ctx'> </div><div class='ctx'> TRACE_EVENT(amdgpu_reset_reg_dumps,</div><div class='hunk'>@@ -554,21 +578,6 @@ TRACE_EVENT(amdgpu_reset_reg_dumps,</div><div class='ctx'> 		      __entry-&gt;value)</div><div class='ctx'> );</div><div class='ctx'> </div><div class='del'>-TRACE_EVENT(amdgpu_runpm_reference_dumps,</div><div class='del'>-	    TP_PROTO(uint32_t index, const char *func),</div><div class='del'>-	    TP_ARGS(index, func),</div><div class='del'>-	    TP_STRUCT__entry(</div><div class='del'>-			     __field(uint32_t, index)</div><div class='del'>-			     __string(func, func)</div><div class='del'>-			     ),</div><div class='del'>-	    TP_fast_assign(</div><div class='del'>-			   __entry-&gt;index = index;</div><div class='del'>-			   __assign_str(func, func);</div><div class='del'>-			   ),</div><div class='del'>-	    TP_printk("amdgpu runpm reference dump 0x%x: 0x%s\n",</div><div class='del'>-		      __entry-&gt;index,</div><div class='del'>-		      __get_str(func))</div><div class='del'>-);</div><div class='ctx'> #undef AMDGPU_JOB_GET_TIMELINE_NAME</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br/>index fc418e670fda..2b931e855abd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c</a></div><div class='hunk'>@@ -61,7 +61,7 @@</div><div class='ctx'> #include "amdgpu_res_cursor.h"</div><div class='ctx'> #include "bif/bif_4_1_d.h"</div><div class='ctx'> </div><div class='del'>-MODULE_IMPORT_NS(DMA_BUF);</div><div class='add'>+MODULE_IMPORT_NS("DMA_BUF");</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_TTM_VRAM_MAX_DW_READ	((size_t)128)</div><div class='ctx'> </div><div class='hunk'>@@ -123,6 +123,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,</div><div class='ctx'> 	case AMDGPU_PL_GWS:</div><div class='ctx'> 	case AMDGPU_PL_OA:</div><div class='ctx'> 	case AMDGPU_PL_DOORBELL:</div><div class='add'>+	case AMDGPU_PL_MMIO_REMAP:</div><div class='ctx'> 		placement-&gt;num_placement = 0;</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -133,7 +134,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,</div><div class='ctx'> </div><div class='ctx'> 		} else if (!amdgpu_gmc_vram_full_visible(&amp;adev-&gt;gmc) &amp;&amp;</div><div class='ctx'> 			   !(abo-&gt;flags &amp; AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &amp;&amp;</div><div class='del'>-			   amdgpu_bo_in_cpu_visible_vram(abo)) {</div><div class='add'>+			   amdgpu_res_cpu_visible(adev, bo-&gt;resource)) {</div><div class='ctx'> </div><div class='ctx'> 			/* Try evicting to the CPU inaccessible part of VRAM</div><div class='ctx'> 			 * first, but only set GTT as busy placement, so this</div><div class='hunk'>@@ -187,7 +188,6 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,</div><div class='ctx'> 	struct amdgpu_job *job;</div><div class='ctx'> 	void *cpu_addr;</div><div class='ctx'> 	uint64_t flags;</div><div class='del'>-	unsigned int i;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	BUG_ON(adev-&gt;mman.buffer_funcs-&gt;copy_max_bytes &lt;</div><div class='hunk'>@@ -226,7 +226,8 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,</div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(adev, &amp;adev-&gt;mman.high_pr,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     num_dw * 4 + num_bytes,</div><div class='del'>-				     AMDGPU_IB_POOL_DELAYED, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DELAYED, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -236,7 +237,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,</div><div class='ctx'> 	dst_addr = amdgpu_bo_gpu_offset(adev-&gt;gart.bo);</div><div class='ctx'> 	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;</div><div class='ctx'> 	amdgpu_emit_copy_buffer(adev, &amp;job-&gt;ibs[0], src_addr,</div><div class='del'>-				dst_addr, num_bytes, false);</div><div class='add'>+				dst_addr, num_bytes, 0);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_pad_ib(ring, &amp;job-&gt;ibs[0]);</div><div class='ctx'> 	WARN_ON(job-&gt;ibs[0].length_dw &gt; num_dw);</div><div class='hunk'>@@ -253,16 +254,9 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,</div><div class='ctx'> 		dma_addr = &amp;bo-&gt;ttm-&gt;dma_address[mm_cur-&gt;start &gt;&gt; PAGE_SHIFT];</div><div class='ctx'> 		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);</div><div class='ctx'> 	} else {</div><div class='del'>-		dma_addr_t dma_address;</div><div class='del'>-</div><div class='del'>-		dma_address = mm_cur-&gt;start;</div><div class='del'>-		dma_address += adev-&gt;vm_manager.vram_base_offset;</div><div class='add'>+		u64 pa = mm_cur-&gt;start + adev-&gt;vm_manager.vram_base_offset;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; num_pages; ++i) {</div><div class='del'>-			amdgpu_gart_map(adev, i &lt;&lt; PAGE_SHIFT, 1, &amp;dma_address,</div><div class='del'>-					flags, cpu_addr);</div><div class='del'>-			dma_address += PAGE_SIZE;</div><div class='del'>-		}</div><div class='add'>+		amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dma_fence_put(amdgpu_job_submit(job));</div><div class='hunk'>@@ -284,20 +278,24 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,</div><div class='ctx'>  * move and different for a BO to BO copy.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,</div><div class='del'>-			       const struct amdgpu_copy_mem *src,</div><div class='del'>-			       const struct amdgpu_copy_mem *dst,</div><div class='del'>-			       uint64_t size, bool tmz,</div><div class='del'>-			       struct dma_resv *resv,</div><div class='del'>-			       struct dma_fence **f)</div><div class='add'>+__attribute__((nonnull))</div><div class='add'>+static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,</div><div class='add'>+				      const struct amdgpu_copy_mem *src,</div><div class='add'>+				      const struct amdgpu_copy_mem *dst,</div><div class='add'>+				      uint64_t size, bool tmz,</div><div class='add'>+				      struct dma_resv *resv,</div><div class='add'>+				      struct dma_fence **f)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;mman.buffer_funcs_ring;</div><div class='ctx'> 	struct amdgpu_res_cursor src_mm, dst_mm;</div><div class='ctx'> 	struct dma_fence *fence = NULL;</div><div class='ctx'> 	int r = 0;</div><div class='add'>+	uint32_t copy_flags = 0;</div><div class='add'>+	struct amdgpu_bo *abo_src, *abo_dst;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mman.buffer_funcs_enabled) {</div><div class='del'>-		DRM_ERROR("Trying to move memory with ring turned off.\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Trying to move memory with ring turned off.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -306,7 +304,8 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='ctx'> 	while (src_mm.remaining) {</div><div class='del'>-		uint64_t from, to, cur_size;</div><div class='add'>+		uint64_t from, to, cur_size, tiling_flags;</div><div class='add'>+		uint32_t num_type, data_format, max_com, write_compress_disable;</div><div class='ctx'> 		struct dma_fence *next;</div><div class='ctx'> </div><div class='ctx'> 		/* Never copy more than 256MiB at once to avoid a timeout */</div><div class='hunk'>@@ -323,8 +322,31 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto error;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_copy_buffer(ring, from, to, cur_size,</div><div class='del'>-				       resv, &amp;next, false, true, tmz);</div><div class='add'>+		abo_src = ttm_to_amdgpu_bo(src-&gt;bo);</div><div class='add'>+		abo_dst = ttm_to_amdgpu_bo(dst-&gt;bo);</div><div class='add'>+		if (tmz)</div><div class='add'>+			copy_flags |= AMDGPU_COPY_FLAGS_TMZ;</div><div class='add'>+		if ((abo_src-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC) &amp;&amp;</div><div class='add'>+		    (abo_src-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM))</div><div class='add'>+			copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;</div><div class='add'>+		if ((abo_dst-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC) &amp;&amp;</div><div class='add'>+		    (dst-&gt;mem-&gt;mem_type == TTM_PL_VRAM)) {</div><div class='add'>+			copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;</div><div class='add'>+			amdgpu_bo_get_tiling_flags(abo_dst, &amp;tiling_flags);</div><div class='add'>+			max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);</div><div class='add'>+			num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);</div><div class='add'>+			data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);</div><div class='add'>+			write_compress_disable =</div><div class='add'>+				AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);</div><div class='add'>+			copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |</div><div class='add'>+				       AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |</div><div class='add'>+				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |</div><div class='add'>+				       AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,</div><div class='add'>+							     write_compress_disable));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,</div><div class='add'>+				       &amp;next, false, true, copy_flags);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -336,9 +358,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> error:</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='del'>-	if (f)</div><div class='del'>-		*f = dma_fence_get(fence);</div><div class='del'>-	dma_fence_put(fence);</div><div class='add'>+	*f = fence;</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -378,11 +398,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,</div><div class='ctx'> 	    (abo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {</div><div class='ctx'> 		struct dma_fence *wipe_fence = NULL;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &amp;wipe_fence,</div><div class='del'>-					false);</div><div class='add'>+		r = amdgpu_fill_buffer(abo, 0, NULL, &amp;wipe_fence,</div><div class='add'>+				       false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			goto error;</div><div class='ctx'> 		} else if (wipe_fence) {</div><div class='add'>+			amdgpu_vram_mgr_set_cleared(bo-&gt;resource);</div><div class='ctx'> 			dma_fence_put(fence);</div><div class='ctx'> 			fence = wipe_fence;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -403,40 +424,56 @@ error:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU</div><div class='add'>+ * @adev: amdgpu device</div><div class='add'>+ * @res: the resource to check</div><div class='ctx'>  *</div><div class='del'>- * Called by amdgpu_bo_move()</div><div class='add'>+ * Returns: true if the full resource is CPU visible, false otherwise.</div><div class='ctx'>  */</div><div class='del'>-static bool amdgpu_mem_visible(struct amdgpu_device *adev,</div><div class='del'>-			       struct ttm_resource *mem)</div><div class='add'>+bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,</div><div class='add'>+			    struct ttm_resource *res)</div><div class='ctx'> {</div><div class='del'>-	u64 mem_size = (u64)mem-&gt;size;</div><div class='ctx'> 	struct amdgpu_res_cursor cursor;</div><div class='del'>-	u64 end;</div><div class='ctx'> </div><div class='del'>-	if (mem-&gt;mem_type == TTM_PL_SYSTEM ||</div><div class='del'>-	    mem-&gt;mem_type == TTM_PL_TT)</div><div class='add'>+	if (!res)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (res-&gt;mem_type == TTM_PL_SYSTEM || res-&gt;mem_type == TTM_PL_TT ||</div><div class='add'>+	    res-&gt;mem_type == AMDGPU_PL_PREEMPT || res-&gt;mem_type == AMDGPU_PL_DOORBELL ||</div><div class='add'>+	    res-&gt;mem_type == AMDGPU_PL_MMIO_REMAP)</div><div class='ctx'> 		return true;</div><div class='del'>-	if (mem-&gt;mem_type != TTM_PL_VRAM)</div><div class='add'>+</div><div class='add'>+	if (res-&gt;mem_type != TTM_PL_VRAM)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	amdgpu_res_first(mem, 0, mem_size, &amp;cursor);</div><div class='del'>-	end = cursor.start + cursor.size;</div><div class='add'>+	amdgpu_res_first(res, 0, res-&gt;size, &amp;cursor);</div><div class='ctx'> 	while (cursor.remaining) {</div><div class='add'>+		if ((cursor.start + cursor.size) &gt; adev-&gt;gmc.visible_vram_size)</div><div class='add'>+			return false;</div><div class='ctx'> 		amdgpu_res_next(&amp;cursor, cursor.size);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (!cursor.remaining)</div><div class='del'>-			break;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		/* ttm_resource_ioremap only supports contiguous memory */</div><div class='del'>-		if (end != cursor.start)</div><div class='del'>-			return false;</div><div class='add'>+/*</div><div class='add'>+ * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy</div><div class='add'>+ *</div><div class='add'>+ * Called by amdgpu_bo_move()</div><div class='add'>+ */</div><div class='add'>+static bool amdgpu_res_copyable(struct amdgpu_device *adev,</div><div class='add'>+				struct ttm_resource *mem)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_res_cpu_visible(adev, mem))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-		end = cursor.start + cursor.size;</div><div class='del'>-	}</div><div class='add'>+	/* ttm_resource_ioremap only supports contiguous memory */</div><div class='add'>+	if (mem-&gt;mem_type == TTM_PL_VRAM &amp;&amp;</div><div class='add'>+	    !(mem-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	return end &lt;= adev-&gt;gmc.visible_vram_size;</div><div class='add'>+	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -466,14 +503,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,</div><div class='ctx'> </div><div class='ctx'> 	if (!old_mem || (old_mem-&gt;mem_type == TTM_PL_SYSTEM &amp;&amp;</div><div class='ctx'> 			 bo-&gt;ttm == NULL)) {</div><div class='add'>+		amdgpu_bo_move_notify(bo, evict, new_mem);</div><div class='ctx'> 		ttm_bo_move_null(bo, new_mem);</div><div class='del'>-		goto out;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (old_mem-&gt;mem_type == TTM_PL_SYSTEM &amp;&amp;</div><div class='ctx'> 	    (new_mem-&gt;mem_type == TTM_PL_TT ||</div><div class='ctx'> 	     new_mem-&gt;mem_type == AMDGPU_PL_PREEMPT)) {</div><div class='add'>+		amdgpu_bo_move_notify(bo, evict, new_mem);</div><div class='ctx'> 		ttm_bo_move_null(bo, new_mem);</div><div class='del'>-		goto out;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	if ((old_mem-&gt;mem_type == TTM_PL_TT ||</div><div class='ctx'> 	     old_mem-&gt;mem_type == AMDGPU_PL_PREEMPT) &amp;&amp;</div><div class='hunk'>@@ -483,22 +522,26 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_ttm_backend_unbind(bo-&gt;bdev, bo-&gt;ttm);</div><div class='add'>+		amdgpu_bo_move_notify(bo, evict, new_mem);</div><div class='ctx'> 		ttm_resource_free(bo, &amp;bo-&gt;resource);</div><div class='ctx'> 		ttm_bo_assign_mem(bo, new_mem);</div><div class='del'>-		goto out;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (old_mem-&gt;mem_type == AMDGPU_PL_GDS ||</div><div class='ctx'> 	    old_mem-&gt;mem_type == AMDGPU_PL_GWS ||</div><div class='ctx'> 	    old_mem-&gt;mem_type == AMDGPU_PL_OA ||</div><div class='ctx'> 	    old_mem-&gt;mem_type == AMDGPU_PL_DOORBELL ||</div><div class='add'>+	    old_mem-&gt;mem_type == AMDGPU_PL_MMIO_REMAP ||</div><div class='ctx'> 	    new_mem-&gt;mem_type == AMDGPU_PL_GDS ||</div><div class='ctx'> 	    new_mem-&gt;mem_type == AMDGPU_PL_GWS ||</div><div class='ctx'> 	    new_mem-&gt;mem_type == AMDGPU_PL_OA ||</div><div class='del'>-	    new_mem-&gt;mem_type == AMDGPU_PL_DOORBELL) {</div><div class='add'>+	    new_mem-&gt;mem_type == AMDGPU_PL_DOORBELL ||</div><div class='add'>+	    new_mem-&gt;mem_type == AMDGPU_PL_MMIO_REMAP) {</div><div class='ctx'> 		/* Nothing to save here */</div><div class='add'>+		amdgpu_bo_move_notify(bo, evict, new_mem);</div><div class='ctx'> 		ttm_bo_move_null(bo, new_mem);</div><div class='del'>-		goto out;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (bo-&gt;type == ttm_bo_type_device &amp;&amp;</div><div class='hunk'>@@ -510,27 +553,28 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,</div><div class='ctx'> 		abo-&gt;flags &amp;= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mman.buffer_funcs_enabled) {</div><div class='del'>-		if (((old_mem-&gt;mem_type == TTM_PL_SYSTEM &amp;&amp;</div><div class='del'>-		      new_mem-&gt;mem_type == TTM_PL_VRAM) ||</div><div class='del'>-		     (old_mem-&gt;mem_type == TTM_PL_VRAM &amp;&amp;</div><div class='del'>-		      new_mem-&gt;mem_type == TTM_PL_SYSTEM))) {</div><div class='del'>-			hop-&gt;fpfn = 0;</div><div class='del'>-			hop-&gt;lpfn = 0;</div><div class='del'>-			hop-&gt;mem_type = TTM_PL_TT;</div><div class='del'>-			hop-&gt;flags = TTM_PL_FLAG_TEMPORARY;</div><div class='del'>-			return -EMULTIHOP;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;mman.buffer_funcs_enabled &amp;&amp;</div><div class='add'>+	    ((old_mem-&gt;mem_type == TTM_PL_SYSTEM &amp;&amp;</div><div class='add'>+	      new_mem-&gt;mem_type == TTM_PL_VRAM) ||</div><div class='add'>+	     (old_mem-&gt;mem_type == TTM_PL_VRAM &amp;&amp;</div><div class='add'>+	      new_mem-&gt;mem_type == TTM_PL_SYSTEM))) {</div><div class='add'>+		hop-&gt;fpfn = 0;</div><div class='add'>+		hop-&gt;lpfn = 0;</div><div class='add'>+		hop-&gt;mem_type = TTM_PL_TT;</div><div class='add'>+		hop-&gt;flags = TTM_PL_FLAG_TEMPORARY;</div><div class='add'>+		return -EMULTIHOP;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_bo_move_notify(bo, evict, new_mem);</div><div class='add'>+	if (adev-&gt;mman.buffer_funcs_enabled)</div><div class='ctx'> 		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);</div><div class='del'>-	} else {</div><div class='add'>+	else</div><div class='ctx'> 		r = -ENODEV;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		/* Check that all memory is CPU accessible */</div><div class='del'>-		if (!amdgpu_mem_visible(adev, old_mem) ||</div><div class='del'>-		    !amdgpu_mem_visible(adev, new_mem)) {</div><div class='add'>+		if (!amdgpu_res_copyable(adev, old_mem) ||</div><div class='add'>+		    !amdgpu_res_copyable(adev, new_mem)) {</div><div class='ctx'> 			pr_err("Move buffer fallback to memcpy unavailable\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -540,11 +584,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	trace_amdgpu_bo_move(abo, new_mem-&gt;mem_type, old_mem-&gt;mem_type);</div><div class='del'>-out:</div><div class='del'>-	/* update statistics */</div><div class='add'>+	/* update statistics after the move */</div><div class='add'>+	if (evict)</div><div class='add'>+		atomic64_inc(&amp;adev-&gt;num_evictions);</div><div class='ctx'> 	atomic64_add(bo-&gt;base.size, &amp;adev-&gt;num_bytes_moved);</div><div class='del'>-	amdgpu_bo_move_notify(bo, evict);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -557,7 +600,6 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,</div><div class='ctx'> 				     struct ttm_resource *mem)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);</div><div class='del'>-	size_t bus_size = (size_t)mem-&gt;size;</div><div class='ctx'> </div><div class='ctx'> 	switch (mem-&gt;mem_type) {</div><div class='ctx'> 	case TTM_PL_SYSTEM:</div><div class='hunk'>@@ -568,9 +610,6 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TTM_PL_VRAM:</div><div class='ctx'> 		mem-&gt;bus.offset = mem-&gt;start &lt;&lt; PAGE_SHIFT;</div><div class='del'>-		/* check if it's visible */</div><div class='del'>-		if ((mem-&gt;bus.offset + bus_size) &gt; adev-&gt;gmc.visible_vram_size)</div><div class='del'>-			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;mman.aper_base_kaddr &amp;&amp;</div><div class='ctx'> 		    mem-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS)</div><div class='hunk'>@@ -586,6 +625,12 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,</div><div class='ctx'> 		mem-&gt;bus.is_iomem = true;</div><div class='ctx'> 		mem-&gt;bus.caching = ttm_uncached;</div><div class='ctx'> 		break;</div><div class='add'>+	case AMDGPU_PL_MMIO_REMAP:</div><div class='add'>+		mem-&gt;bus.offset = mem-&gt;start &lt;&lt; PAGE_SHIFT;</div><div class='add'>+		mem-&gt;bus.offset += adev-&gt;rmmio_remap.bus_addr;</div><div class='add'>+		mem-&gt;bus.is_iomem = true;</div><div class='add'>+		mem-&gt;bus.caching = ttm_uncached;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -603,6 +648,8 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,</div><div class='ctx'> </div><div class='ctx'> 	if (bo-&gt;resource-&gt;mem_type == AMDGPU_PL_DOORBELL)</div><div class='ctx'> 		return ((uint64_t)(adev-&gt;doorbell.base + cursor.start)) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	else if (bo-&gt;resource-&gt;mem_type == AMDGPU_PL_MMIO_REMAP)</div><div class='add'>+		return ((uint64_t)(adev-&gt;rmmio_remap.bus_addr + cursor.start)) &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	return (adev-&gt;gmc.aper_base + cursor.start) &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> }</div><div class='hunk'>@@ -650,10 +697,11 @@ struct amdgpu_ttm_tt {</div><div class='ctx'>  * memory and start HMM tracking CPU page table update</div><div class='ctx'>  *</div><div class='ctx'>  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only</div><div class='del'>- * once afterwards to stop HMM tracking</div><div class='add'>+ * once afterwards to stop HMM tracking. Its the caller responsibility to ensure</div><div class='add'>+ * that range is a valid memory and it is freed too.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,</div><div class='del'>-				 struct hmm_range **range)</div><div class='add'>+int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,</div><div class='add'>+				 struct amdgpu_hmm_range *range)</div><div class='ctx'> {</div><div class='ctx'> 	struct ttm_tt *ttm = bo-&gt;tbo.ttm;</div><div class='ctx'> 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);</div><div class='hunk'>@@ -663,9 +711,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,</div><div class='ctx'> 	bool readonly;</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='del'>-	/* Make sure get_user_pages_done() can cleanup gracefully */</div><div class='del'>-	*range = NULL;</div><div class='del'>-</div><div class='ctx'> 	mm = bo-&gt;notifier.mm;</div><div class='ctx'> 	if (unlikely(!mm)) {</div><div class='ctx'> 		DRM_DEBUG_DRIVER("BO is not registered?\n");</div><div class='hunk'>@@ -689,7 +734,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,</div><div class='ctx'> </div><div class='ctx'> 	readonly = amdgpu_ttm_tt_is_readonly(ttm);</div><div class='ctx'> 	r = amdgpu_hmm_range_get_pages(&amp;bo-&gt;notifier, start, ttm-&gt;num_pages,</div><div class='del'>-				       readonly, NULL, pages, range);</div><div class='add'>+				       readonly, NULL, range);</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mmap_read_unlock(mm);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -700,38 +745,6 @@ out_unlock:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations</div><div class='del'>- */</div><div class='del'>-void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,</div><div class='del'>-				      struct hmm_range *range)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ttm_tt *gtt = (void *)ttm;</div><div class='del'>-</div><div class='del'>-	if (gtt &amp;&amp; gtt-&gt;userptr &amp;&amp; range)</div><div class='del'>-		amdgpu_hmm_range_get_pages_done(range);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change</div><div class='del'>- * Check if the pages backing this ttm range have been invalidated</div><div class='del'>- *</div><div class='del'>- * Returns: true if pages are still valid</div><div class='del'>- */</div><div class='del'>-bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,</div><div class='del'>-				       struct hmm_range *range)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);</div><div class='del'>-</div><div class='del'>-	if (!gtt || !gtt-&gt;userptr || !range)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",</div><div class='del'>-		gtt-&gt;userptr, ttm-&gt;num_pages);</div><div class='del'>-</div><div class='del'>-	WARN_ONCE(!range-&gt;hmm_pfns, "No user pages to check\n");</div><div class='del'>-</div><div class='del'>-	return !amdgpu_hmm_range_get_pages_done(range);</div><div class='del'>-}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -741,12 +754,12 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,</div><div class='ctx'>  * that backs user memory and will ultimately be mapped into the device</div><div class='ctx'>  * address space.</div><div class='ctx'>  */</div><div class='del'>-void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)</div><div class='add'>+void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ttm-&gt;num_pages; ++i)</div><div class='del'>-		ttm-&gt;pages[i] = pages ? pages[i] : NULL;</div><div class='add'>+		ttm-&gt;pages[i] = range ? hmm_pfn_to_page(range-&gt;hmm_range.hmm_pfns[i]) : NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -774,7 +787,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,</div><div class='ctx'> 	/* Map SG to device */</div><div class='ctx'> 	r = dma_map_sgtable(adev-&gt;dev, ttm-&gt;sg, direction, 0);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto release_sg;</div><div class='add'>+		goto release_sg_table;</div><div class='ctx'> </div><div class='ctx'> 	/* convert SG to linear array of pages and dma addresses */</div><div class='ctx'> 	drm_prime_sg_to_dma_addr_array(ttm-&gt;sg, gtt-&gt;ttm.dma_address,</div><div class='hunk'>@@ -782,6 +795,8 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+release_sg_table:</div><div class='add'>+	sg_free_table(ttm-&gt;sg);</div><div class='ctx'> release_sg:</div><div class='ctx'> 	kfree(ttm-&gt;sg);</div><div class='ctx'> 	ttm-&gt;sg = NULL;</div><div class='hunk'>@@ -824,8 +839,7 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,</div><div class='ctx'> 	int num_xcc = max(1U, adev-&gt;gfx.num_xcc_per_xcp);</div><div class='ctx'> 	uint64_t page_idx, pages_per_xcc;</div><div class='ctx'> 	int i;</div><div class='del'>-	uint64_t ctrl_flags = (flags &amp; ~AMDGPU_PTE_MTYPE_VG10_MASK) |</div><div class='del'>-			AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);</div><div class='add'>+	uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);</div><div class='ctx'> </div><div class='ctx'> 	pages_per_xcc = total_pages;</div><div class='ctx'> 	do_div(pages_per_xcc, num_xcc);</div><div class='hunk'>@@ -891,7 +905,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,</div><div class='ctx'> 	if (gtt-&gt;userptr) {</div><div class='ctx'> 		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("failed to pin userptr\n");</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to pin userptr\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (ttm-&gt;page_flags &amp; TTM_TT_FLAG_EXTERNAL) {</div><div class='hunk'>@@ -1017,7 +1031,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,</div><div class='ctx'> 	/* if the pages have userptr pinning then clear that first */</div><div class='ctx'> 	if (gtt-&gt;userptr) {</div><div class='ctx'> 		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);</div><div class='del'>-	} else if (ttm-&gt;sg &amp;&amp; gtt-&gt;gobj-&gt;import_attach) {</div><div class='add'>+	} else if (ttm-&gt;sg &amp;&amp; drm_gem_is_imported(gtt-&gt;gobj)) {</div><div class='ctx'> 		struct dma_buf_attachment *attach;</div><div class='ctx'> </div><div class='ctx'> 		attach = gtt-&gt;gobj-&gt;import_attach;</div><div class='hunk'>@@ -1311,10 +1325,11 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)</div><div class='ctx'> </div><div class='ctx'> 	if (mem &amp;&amp; (mem-&gt;mem_type == TTM_PL_TT ||</div><div class='ctx'> 		    mem-&gt;mem_type == AMDGPU_PL_DOORBELL ||</div><div class='del'>-		    mem-&gt;mem_type == AMDGPU_PL_PREEMPT)) {</div><div class='add'>+		    mem-&gt;mem_type == AMDGPU_PL_PREEMPT ||</div><div class='add'>+		    mem-&gt;mem_type == AMDGPU_PL_MMIO_REMAP)) {</div><div class='ctx'> 		flags |= AMDGPU_PTE_SYSTEM;</div><div class='ctx'> </div><div class='del'>-		if (ttm-&gt;caching == ttm_cached)</div><div class='add'>+		if (ttm &amp;&amp; ttm-&gt;caching == ttm_cached)</div><div class='ctx'> 			flags |= AMDGPU_PTE_SNOOPED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1380,7 +1395,8 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,</div><div class='ctx'> 	 */</div><div class='ctx'> 	dma_resv_for_each_fence(&amp;resv_cursor, bo-&gt;base.resv,</div><div class='ctx'> 				DMA_RESV_USAGE_BOOKKEEP, f) {</div><div class='del'>-		if (amdkfd_fence_check_mm(f, current-&gt;mm))</div><div class='add'>+		if (amdkfd_fence_check_mm(f, current-&gt;mm) &amp;&amp;</div><div class='add'>+		    !(place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS))</div><div class='ctx'> 			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1465,10 +1481,12 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,</div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(adev, &amp;adev-&gt;mman.high_pr,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     num_dw * 4, AMDGPU_IB_POOL_DELAYED,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='ctx'> 	amdgpu_res_first(abo-&gt;tbo.resource, offset, len, &amp;src_mm);</div><div class='ctx'> 	src_addr = amdgpu_ttm_domain_start(adev, bo-&gt;resource-&gt;mem_type) +</div><div class='ctx'> 		src_mm.start;</div><div class='hunk'>@@ -1477,12 +1495,13 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,</div><div class='ctx'> 		swap(src_addr, dst_addr);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_emit_copy_buffer(adev, &amp;job-&gt;ibs[0], src_addr, dst_addr,</div><div class='del'>-				PAGE_SIZE, false);</div><div class='add'>+				PAGE_SIZE, 0);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_pad_ib(adev-&gt;mman.buffer_funcs_ring, &amp;job-&gt;ibs[0]);</div><div class='ctx'> 	WARN_ON(job-&gt;ibs[0].length_dw &gt; num_dw);</div><div class='ctx'> </div><div class='ctx'> 	fence = amdgpu_job_submit(job);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (!dma_fence_wait_timeout(fence, false, adev-&gt;sdma_timeout))</div><div class='ctx'> 		r = -ETIMEDOUT;</div><div class='hunk'>@@ -1548,7 +1567,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,</div><div class='ctx'> static void</div><div class='ctx'> amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_bo_move_notify(bo, false);</div><div class='add'>+	amdgpu_bo_move_notify(bo, false, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct ttm_device_funcs amdgpu_bo_driver = {</div><div class='hunk'>@@ -1721,7 +1740,9 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;bios &amp;&amp;</div><div class='del'>-	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	    (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+	     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)))</div><div class='ctx'> 		reserve_size = max(reserve_size, (uint32_t)280 &lt;&lt; 20);</div><div class='ctx'> 	else if (!reserve_size)</div><div class='ctx'> 		reserve_size = DISCOVERY_TMR_OFFSET;</div><div class='hunk'>@@ -1735,25 +1756,21 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)</div><div class='ctx'> 						 &amp;ctx-&gt;c2p_bo,</div><div class='ctx'> 						 NULL);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);</div><div class='add'>+			dev_err(adev-&gt;dev, "alloc c2p_bo failed(%d)!\n", ret);</div><div class='ctx'> 			amdgpu_ttm_training_reserve_vram_fini(adev);</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		}</div><div class='ctx'> 		ctx-&gt;init = PSP_MEM_TRAIN_RESERVE_SUCCESS;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;gmc.is_app_apu) {</div><div class='del'>-		ret = amdgpu_bo_create_kernel_at(</div><div class='del'>-			adev, adev-&gt;gmc.real_vram_size - reserve_size,</div><div class='del'>-			reserve_size, &amp;adev-&gt;mman.fw_reserved_memory, NULL);</div><div class='del'>-		if (ret) {</div><div class='del'>-			DRM_ERROR("alloc tmr failed(%d)!\n", ret);</div><div class='del'>-			amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory,</div><div class='del'>-					      NULL, NULL);</div><div class='del'>-			return ret;</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n");</div><div class='add'>+	ret = amdgpu_bo_create_kernel_at(</div><div class='add'>+		adev, adev-&gt;gmc.real_vram_size - reserve_size, reserve_size,</div><div class='add'>+		&amp;adev-&gt;mman.fw_reserved_memory, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "alloc tmr failed(%d)!\n", ret);</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory, NULL,</div><div class='add'>+				      NULL);</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1775,7 +1792,7 @@ static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gmc.num_mem_partitions; i++) {</div><div class='ctx'> 		ttm_pool_init(&amp;adev-&gt;mman.ttm_pools[i], adev-&gt;dev,</div><div class='ctx'> 			      adev-&gt;gmc.mem_partitions[i].numa.node,</div><div class='del'>-			      false, false);</div><div class='add'>+			      TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M)));</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1794,6 +1811,59 @@ static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;mman.ttm_pools = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton 4K MMIO_REMAP BO</div><div class='add'>+ * @adev: amdgpu device</div><div class='add'>+ *</div><div class='add'>+ * Allocates a one-page (4K) GEM BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP when the</div><div class='add'>+ * hardware exposes a remap base (adev-&gt;rmmio_remap.bus_addr) and the host</div><div class='add'>+ * PAGE_SIZE is &lt;= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular</div><div class='add'>+ * GEM object (amdgpu_bo_create).</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *  * 0 on success or intentional skip (feature not present/unsupported)</div><div class='add'>+ *  * negative errno on allocation failure</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_ttm_mmio_remap_bo_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo_param bp;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/* Skip if HW doesn't expose remap, or if PAGE_SIZE &gt; AMDGPU_GPU_PAGE_SIZE (4K). */</div><div class='add'>+	if (!adev-&gt;rmmio_remap.bus_addr || PAGE_SIZE &gt; AMDGPU_GPU_PAGE_SIZE)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	memset(&amp;bp, 0, sizeof(bp));</div><div class='add'>+</div><div class='add'>+	/* Create exactly one GEM BO in the MMIO_REMAP domain. */</div><div class='add'>+	bp.type        = ttm_bo_type_device;          /* userspace-mappable GEM */</div><div class='add'>+	bp.size        = AMDGPU_GPU_PAGE_SIZE;        /* 4K */</div><div class='add'>+	bp.byte_align  = AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	bp.domain      = AMDGPU_GEM_DOMAIN_MMIO_REMAP;</div><div class='add'>+	bp.flags       = 0;</div><div class='add'>+	bp.resv        = NULL;</div><div class='add'>+	bp.bo_ptr_size = sizeof(struct amdgpu_bo);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create(adev, &amp;bp, &amp;adev-&gt;rmmio_remap.bo);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_ttm_mmio_remap_bo_fini - Free the singleton MMIO_REMAP BO</div><div class='add'>+ * @adev: amdgpu device</div><div class='add'>+ *</div><div class='add'>+ * Frees the kernel-owned MMIO_REMAP BO if it was allocated by</div><div class='add'>+ * amdgpu_ttm_mmio_remap_bo_init().</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_ttm_mmio_remap_bo_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_unref(&amp;adev-&gt;rmmio_remap.bo);</div><div class='add'>+	adev-&gt;rmmio_remap.bo = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * amdgpu_ttm_init - Init the memory management (ttm) as well as various</div><div class='ctx'>  * gtt/vram related fields.</div><div class='hunk'>@@ -1810,29 +1880,36 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='ctx'> </div><div class='add'>+	dma_set_max_seg_size(adev-&gt;dev, UINT_MAX);</div><div class='ctx'> 	/* No others user of address space so set it to 0 */</div><div class='ctx'> 	r = ttm_device_init(&amp;adev-&gt;mman.bdev, &amp;amdgpu_bo_driver, adev-&gt;dev,</div><div class='ctx'> 			       adev_to_drm(adev)-&gt;anon_inode-&gt;i_mapping,</div><div class='ctx'> 			       adev_to_drm(adev)-&gt;vma_offset_manager,</div><div class='del'>-			       adev-&gt;need_swiotlb,</div><div class='del'>-			       dma_addressing_limited(adev-&gt;dev));</div><div class='add'>+			       (adev-&gt;need_swiotlb ?</div><div class='add'>+				TTM_ALLOCATION_POOL_USE_DMA_ALLOC : 0) |</div><div class='add'>+			       (dma_addressing_limited(adev-&gt;dev) ?</div><div class='add'>+				TTM_ALLOCATION_POOL_USE_DMA32 : 0) |</div><div class='add'>+			       TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M)));</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"failed initializing buffer object driver(%d).\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ttm_pools_init(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("failed to init ttm pools(%d).\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to init ttm pools(%d).\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> 	adev-&gt;mman.initialized = true;</div><div class='ctx'> </div><div class='del'>-	/* Initialize VRAM pool with all of VRAM divided into pages */</div><div class='del'>-	r = amdgpu_vram_mgr_init(adev);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing VRAM heap.\n");</div><div class='del'>-		return r;</div><div class='add'>+	if (!adev-&gt;gmc.is_app_apu) {</div><div class='add'>+		/* Initialize VRAM pool with all of VRAM divided into pages */</div><div class='add'>+		r = amdgpu_vram_mgr_init(adev);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed initializing VRAM heap.\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Change the size here instead of the init above so only lpfn is affected */</div><div class='hunk'>@@ -1861,19 +1938,19 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 *The reserved vram for driver must be pinned to the specified</div><div class='del'>-	 *place on the VRAM, so reserve it early.</div><div class='add'>+	 * The reserved VRAM for the driver must be pinned to a specific</div><div class='add'>+	 * location in VRAM, so reserve it early.</div><div class='ctx'> 	 */</div><div class='ctx'> 	r = amdgpu_ttm_drv_reserve_vram_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * only NAVI10 and onwards ASIC support for IP discovery.</div><div class='del'>-	 * If IP discovery enabled, a block of memory should be</div><div class='del'>-	 * reserved for IP discovey.</div><div class='add'>+	 * only NAVI10 and later ASICs support IP discovery.</div><div class='add'>+	 * If IP discovery is enabled, a block of memory should be</div><div class='add'>+	 * reserved for it.</div><div class='ctx'> 	 */</div><div class='del'>-	if (adev-&gt;mman.discovery_bin) {</div><div class='add'>+	if (adev-&gt;discovery.reserve_tmr) {</div><div class='ctx'> 		r = amdgpu_ttm_reserve_tmr(adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='hunk'>@@ -1911,63 +1988,89 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",</div><div class='add'>+	dev_info(adev-&gt;dev, "amdgpu: %uM of VRAM memory ready\n",</div><div class='ctx'> 		 (unsigned int)(adev-&gt;gmc.real_vram_size / (1024 * 1024)));</div><div class='ctx'> </div><div class='ctx'> 	/* Compute GTT size, either based on TTM limit</div><div class='ctx'> 	 * or whatever the user passed on module init.</div><div class='ctx'> 	 */</div><div class='del'>-	if (amdgpu_gtt_size == -1)</div><div class='del'>-		gtt_size = ttm_tt_pages_limit() &lt;&lt; PAGE_SHIFT;</div><div class='del'>-	else</div><div class='del'>-		gtt_size = (uint64_t)amdgpu_gtt_size &lt;&lt; 20;</div><div class='add'>+	gtt_size = ttm_tt_pages_limit() &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	if (amdgpu_gtt_size != -1) {</div><div class='add'>+		uint64_t configured_size = (uint64_t)amdgpu_gtt_size &lt;&lt; 20;</div><div class='add'>+</div><div class='add'>+		drm_warn(&amp;adev-&gt;ddev,</div><div class='add'>+			"Configuring gttsize via module parameter is deprecated, please use ttm.pages_limit\n");</div><div class='add'>+		if (gtt_size != configured_size)</div><div class='add'>+			drm_warn(&amp;adev-&gt;ddev,</div><div class='add'>+				"GTT size has been set as %llu but TTM size has been set as %llu, this is unusual\n",</div><div class='add'>+				configured_size, gtt_size);</div><div class='add'>+</div><div class='add'>+		gtt_size = configured_size;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize GTT memory pool */</div><div class='ctx'> 	r = amdgpu_gtt_mgr_init(adev, gtt_size);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing GTT heap.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing GTT heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='del'>-	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",</div><div class='add'>+	dev_info(adev-&gt;dev, "amdgpu: %uM of GTT memory ready.\n",</div><div class='ctx'> 		 (unsigned int)(gtt_size / (1024 * 1024)));</div><div class='ctx'> </div><div class='del'>-	/* Initiailize doorbell pool on PCI BAR */</div><div class='add'>+	if (adev-&gt;flags &amp; AMD_IS_APU) {</div><div class='add'>+		if (adev-&gt;gmc.real_vram_size &lt; gtt_size)</div><div class='add'>+			adev-&gt;apu_prefer_gtt = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize doorbell pool on PCI BAR */</div><div class='ctx'> 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev-&gt;doorbell.size / PAGE_SIZE);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing doorbell heap.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing doorbell heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Create a boorbell page for kernel usages */</div><div class='ctx'> 	r = amdgpu_doorbell_create_kernel_doorbells(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to initialize kernel doorbells.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to initialize kernel doorbells.\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize MMIO-remap pool (single page 4K) */</div><div class='add'>+	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_MMIO_REMAP, 1);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing MMIO-remap heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Allocate the singleton MMIO_REMAP BO (4K) if supported */</div><div class='add'>+	r = amdgpu_ttm_mmio_remap_bo_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	/* Initialize preemptible memory pool */</div><div class='ctx'> 	r = amdgpu_preempt_mgr_init(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing PREEMPT heap.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing PREEMPT heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize various on-chip memory pools */</div><div class='ctx'> 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev-&gt;gds.gds_size);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing GDS heap.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing GDS heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev-&gt;gds.gws_size);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing gws heap.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing gws heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev-&gt;gds.oa_size);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed initializing oa heap.\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed initializing oa heap.\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,</div><div class='hunk'>@@ -1999,12 +2102,16 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		/* return the FW reserved memory back to VRAM */</div><div class='ctx'> 		amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory, NULL,</div><div class='ctx'> 				      NULL);</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;mman.fw_reserved_memory_extend, NULL,</div><div class='add'>+				      NULL);</div><div class='ctx'> 		if (adev-&gt;mman.stolen_reserved_size)</div><div class='ctx'> 			amdgpu_bo_free_kernel(&amp;adev-&gt;mman.stolen_reserved_memory,</div><div class='ctx'> 					      NULL, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;adev-&gt;mman.sdma_access_bo, NULL,</div><div class='ctx'> 					&amp;adev-&gt;mman.sdma_access_ptr);</div><div class='add'>+</div><div class='add'>+	amdgpu_ttm_mmio_remap_bo_fini(adev);</div><div class='ctx'> 	amdgpu_ttm_fw_reserve_vram_fini(adev);</div><div class='ctx'> 	amdgpu_ttm_drv_reserve_vram_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2017,15 +2124,20 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		drm_dev_exit(idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_vram_mgr_fini(adev);</div><div class='add'>+	if (!adev-&gt;gmc.is_app_apu)</div><div class='add'>+		amdgpu_vram_mgr_fini(adev);</div><div class='ctx'> 	amdgpu_gtt_mgr_fini(adev);</div><div class='ctx'> 	amdgpu_preempt_mgr_fini(adev);</div><div class='add'>+	amdgpu_doorbell_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	ttm_range_man_fini(&amp;adev-&gt;mman.bdev, AMDGPU_PL_GDS);</div><div class='ctx'> 	ttm_range_man_fini(&amp;adev-&gt;mman.bdev, AMDGPU_PL_GWS);</div><div class='ctx'> 	ttm_range_man_fini(&amp;adev-&gt;mman.bdev, AMDGPU_PL_OA);</div><div class='add'>+	ttm_range_man_fini(&amp;adev-&gt;mman.bdev, AMDGPU_PL_DOORBELL);</div><div class='add'>+	ttm_range_man_fini(&amp;adev-&gt;mman.bdev, AMDGPU_PL_MMIO_REMAP);</div><div class='ctx'> 	ttm_device_fini(&amp;adev-&gt;mman.bdev);</div><div class='ctx'> 	adev-&gt;mman.initialized = false;</div><div class='del'>-	DRM_INFO("amdgpu: ttm finalized\n");</div><div class='add'>+	dev_info(adev-&gt;dev, "amdgpu: ttm finalized\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2057,8 +2169,9 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 					  DRM_SCHED_PRIORITY_KERNEL, &amp;sched,</div><div class='ctx'> 					  1, NULL);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",</div><div class='del'>-				  r);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Failed setting up TTM BO move entity (%d)\n",</div><div class='add'>+				r);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -2066,15 +2179,18 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 					  DRM_SCHED_PRIORITY_NORMAL, &amp;sched,</div><div class='ctx'> 					  1, NULL);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",</div><div class='del'>-				  r);</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Failed setting up TTM BO move entity (%d)\n",</div><div class='add'>+				r);</div><div class='ctx'> 			goto error_free_entity;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		drm_sched_entity_destroy(&amp;adev-&gt;mman.high_pr);</div><div class='ctx'> 		drm_sched_entity_destroy(&amp;adev-&gt;mman.low_pr);</div><div class='del'>-		dma_fence_put(man-&gt;move);</div><div class='del'>-		man-&gt;move = NULL;</div><div class='add'>+		/* Drop all the old fences since re-creating the scheduler entities</div><div class='add'>+		 * will allocate new contexts.</div><div class='add'>+		 */</div><div class='add'>+		ttm_resource_manager_cleanup(man);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */</div><div class='hunk'>@@ -2097,7 +2213,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,</div><div class='ctx'> 				  struct dma_resv *resv,</div><div class='ctx'> 				  bool vm_needs_flush,</div><div class='ctx'> 				  struct amdgpu_job **job,</div><div class='del'>-				  bool delayed)</div><div class='add'>+				  bool delayed, u64 k_job_id)</div><div class='ctx'> {</div><div class='ctx'> 	enum amdgpu_ib_pool_type pool = direct_submit ?</div><div class='ctx'> 		AMDGPU_IB_POOL_DIRECT :</div><div class='hunk'>@@ -2107,7 +2223,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,</div><div class='ctx'> 						    &amp;adev-&gt;mman.high_pr;</div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(adev, entity,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='del'>-				     num_dw * 4, pool, job);</div><div class='add'>+				     num_dw * 4, pool, job, k_job_id);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -2128,7 +2244,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,</div><div class='ctx'> 		       uint64_t dst_offset, uint32_t byte_count,</div><div class='ctx'> 		       struct dma_resv *resv,</div><div class='ctx'> 		       struct dma_fence **fence, bool direct_submit,</div><div class='del'>-		       bool vm_needs_flush, bool tmz)</div><div class='add'>+		       bool vm_needs_flush, uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	unsigned int num_loops, num_dw;</div><div class='hunk'>@@ -2138,7 +2254,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!direct_submit &amp;&amp; !ring-&gt;sched.ready) {</div><div class='del'>-		DRM_ERROR("Trying to move memory with ring turned off.\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Trying to move memory with ring turned off.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2146,7 +2263,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,</div><div class='ctx'> 	num_loops = DIV_ROUND_UP(byte_count, max_bytes);</div><div class='ctx'> 	num_dw = ALIGN(num_loops * adev-&gt;mman.buffer_funcs-&gt;copy_num_dw, 8);</div><div class='ctx'> 	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,</div><div class='del'>-				   resv, vm_needs_flush, &amp;job, false);</div><div class='add'>+				   resv, vm_needs_flush, &amp;job, false,</div><div class='add'>+				   AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -2154,8 +2272,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,</div><div class='ctx'> 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_emit_copy_buffer(adev, &amp;job-&gt;ibs[0], src_offset,</div><div class='del'>-					dst_offset, cur_size_in_bytes, tmz);</div><div class='del'>-</div><div class='add'>+					dst_offset, cur_size_in_bytes, copy_flags);</div><div class='ctx'> 		src_offset += cur_size_in_bytes;</div><div class='ctx'> 		dst_offset += cur_size_in_bytes;</div><div class='ctx'> 		byte_count -= cur_size_in_bytes;</div><div class='hunk'>@@ -2174,7 +2291,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,</div><div class='ctx'> </div><div class='ctx'> error_free:</div><div class='ctx'> 	amdgpu_job_free(job);</div><div class='del'>-	DRM_ERROR("Error scheduling IBs (%d)\n", r);</div><div class='add'>+	dev_err(adev-&gt;dev, "Error scheduling IBs (%d)\n", r);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2182,7 +2299,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,</div><div class='ctx'> 			       uint64_t dst_addr, uint32_t byte_count,</div><div class='ctx'> 			       struct dma_resv *resv,</div><div class='ctx'> 			       struct dma_fence **fence,</div><div class='del'>-			       bool vm_needs_flush, bool delayed)</div><div class='add'>+			       bool vm_needs_flush, bool delayed,</div><div class='add'>+			       u64 k_job_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	unsigned int num_loops, num_dw;</div><div class='hunk'>@@ -2195,7 +2313,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,</div><div class='ctx'> 	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);</div><div class='ctx'> 	num_dw = ALIGN(num_loops * adev-&gt;mman.buffer_funcs-&gt;fill_num_dw, 8);</div><div class='ctx'> 	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,</div><div class='del'>-				   &amp;job, delayed);</div><div class='add'>+				   &amp;job, delayed, k_job_id);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -2215,11 +2333,78 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_ttm_clear_buffer - clear memory buffers</div><div class='add'>+ * @bo: amdgpu buffer object</div><div class='add'>+ * @resv: reservation object</div><div class='add'>+ * @fence: dma_fence associated with the operation</div><div class='add'>+ *</div><div class='add'>+ * Clear the memory buffer resource.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 for success or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,</div><div class='add'>+			    struct dma_resv *resv,</div><div class='add'>+			    struct dma_fence **fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='add'>+	struct amdgpu_ring *ring = adev-&gt;mman.buffer_funcs_ring;</div><div class='add'>+	struct amdgpu_res_cursor cursor;</div><div class='add'>+	u64 addr;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;mman.buffer_funcs_enabled)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!fence)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*fence = dma_fence_get_stub();</div><div class='add'>+</div><div class='add'>+	amdgpu_res_first(bo-&gt;tbo.resource, 0, amdgpu_bo_size(bo), &amp;cursor);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='add'>+	while (cursor.remaining) {</div><div class='add'>+		struct dma_fence *next = NULL;</div><div class='add'>+		u64 size;</div><div class='add'>+</div><div class='add'>+		if (amdgpu_res_cleared(&amp;cursor)) {</div><div class='add'>+			amdgpu_res_next(&amp;cursor, cursor.size);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Never clear more than 256MiB at once to avoid timeouts */</div><div class='add'>+		size = min(cursor.size, 256ULL &lt;&lt; 20);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_ttm_map_buffer(&amp;bo-&gt;tbo, bo-&gt;tbo.resource, &amp;cursor,</div><div class='add'>+					  1, ring, false, &amp;size, &amp;addr);</div><div class='add'>+		if (r)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv,</div><div class='add'>+					&amp;next, true, true,</div><div class='add'>+					AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);</div><div class='add'>+		if (r)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		dma_fence_put(*fence);</div><div class='add'>+		*fence = next;</div><div class='add'>+</div><div class='add'>+		amdgpu_res_next(&amp;cursor, size);</div><div class='add'>+	}</div><div class='add'>+err:</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_fill_buffer(struct amdgpu_bo *bo,</div><div class='ctx'> 			uint32_t src_data,</div><div class='ctx'> 			struct dma_resv *resv,</div><div class='ctx'> 			struct dma_fence **f,</div><div class='del'>-			bool delayed)</div><div class='add'>+			bool delayed,</div><div class='add'>+			u64 k_job_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;mman.buffer_funcs_ring;</div><div class='hunk'>@@ -2228,7 +2413,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mman.buffer_funcs_enabled) {</div><div class='del'>-		DRM_ERROR("Trying to clear memory with ring turned off.\n");</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"Trying to clear memory with ring turned off.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2248,7 +2434,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,</div><div class='ctx'> 			goto error;</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,</div><div class='del'>-					&amp;next, true, delayed);</div><div class='add'>+					&amp;next, true, delayed, k_job_id);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -2288,7 +2474,7 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)</div><div class='ctx'> 		man = ttm_manager_type(&amp;adev-&gt;mman.bdev, mem_type);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		DRM_ERROR("Trying to evict invalid memory type\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Trying to evict invalid memory type\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h<br/>index 65ec82141a8e..577ee04ce0bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h</a></div><div class='hunk'>@@ -26,20 +26,21 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma-direction.h&gt;</div><div class='ctx'> #include &lt;drm/gpu_scheduler.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='ctx'> #include "amdgpu_vram_mgr.h"</div><div class='del'>-#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_hmm.h"</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)</div><div class='ctx'> #define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)</div><div class='ctx'> #define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)</div><div class='ctx'> #define AMDGPU_PL_PREEMPT	(TTM_PL_PRIV + 3)</div><div class='ctx'> #define AMDGPU_PL_DOORBELL	(TTM_PL_PRIV + 4)</div><div class='add'>+#define AMDGPU_PL_MMIO_REMAP	(TTM_PL_PRIV + 5)</div><div class='add'>+#define __AMDGPU_PL_NUM	(TTM_PL_PRIV + 6)</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_GTT_MAX_TRANSFER_SIZE	512</div><div class='ctx'> #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2</div><div class='ctx'> </div><div class='del'>-#define AMDGPU_POISON	0xd0bed0be</div><div class='del'>-</div><div class='ctx'> extern const struct attribute_group amdgpu_vram_mgr_attr_group;</div><div class='ctx'> extern const struct attribute_group amdgpu_gtt_mgr_attr_group;</div><div class='ctx'> </div><div class='hunk'>@@ -82,11 +83,9 @@ struct amdgpu_mman {</div><div class='ctx'> 	uint64_t		stolen_reserved_offset;</div><div class='ctx'> 	uint64_t		stolen_reserved_size;</div><div class='ctx'> </div><div class='del'>-	/* discovery */</div><div class='del'>-	uint8_t				*discovery_bin;</div><div class='del'>-	uint32_t			discovery_tmr_size;</div><div class='ctx'> 	/* fw reserved memory */</div><div class='ctx'> 	struct amdgpu_bo		*fw_reserved_memory;</div><div class='add'>+	struct amdgpu_bo		*fw_reserved_memory_extend;</div><div class='ctx'> </div><div class='ctx'> 	/* firmware VRAM reservation */</div><div class='ctx'> 	u64		fw_vram_usage_start_offset;</div><div class='hunk'>@@ -111,6 +110,23 @@ struct amdgpu_copy_mem {</div><div class='ctx'> 	unsigned long			offset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_COPY_FLAGS_TMZ		(1 &lt;&lt; 0)</div><div class='add'>+#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED	(1 &lt;&lt; 1)</div><div class='add'>+#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED	(1 &lt;&lt; 2)</div><div class='add'>+#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT		3</div><div class='add'>+#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK		0x03</div><div class='add'>+#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT		5</div><div class='add'>+#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK		0x07</div><div class='add'>+#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT		8</div><div class='add'>+#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK		0x3f</div><div class='add'>+#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT	14</div><div class='add'>+#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK	0x1</div><div class='add'>+</div><div class='add'>+#define AMDGPU_COPY_FLAGS_SET(field, value) \</div><div class='add'>+	(((__u32)(value) &amp; AMDGPU_COPY_FLAGS_##field##_MASK) &lt;&lt; AMDGPU_COPY_FLAGS_##field##_SHIFT)</div><div class='add'>+#define AMDGPU_COPY_FLAGS_GET(value, field) \</div><div class='add'>+	(((__u32)(value) &gt;&gt; AMDGPU_COPY_FLAGS_##field##_SHIFT) &amp; AMDGPU_COPY_FLAGS_##field##_MASK)</div><div class='add'>+</div><div class='ctx'> int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);</div><div class='ctx'> void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);</div><div class='hunk'>@@ -138,59 +154,46 @@ int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,</div><div class='ctx'> 				  uint64_t start, uint64_t size);</div><div class='ctx'> int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,</div><div class='ctx'> 				      uint64_t start);</div><div class='add'>+void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,</div><div class='add'>+			    struct ttm_resource *res);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ttm_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_ttm_fini(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,</div><div class='ctx'> 					bool enable);</div><div class='del'>-</div><div class='ctx'> int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,</div><div class='ctx'> 		       uint64_t dst_offset, uint32_t byte_count,</div><div class='ctx'> 		       struct dma_resv *resv,</div><div class='ctx'> 		       struct dma_fence **fence, bool direct_submit,</div><div class='del'>-		       bool vm_needs_flush, bool tmz);</div><div class='del'>-int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,</div><div class='del'>-			       const struct amdgpu_copy_mem *src,</div><div class='del'>-			       const struct amdgpu_copy_mem *dst,</div><div class='del'>-			       uint64_t size, bool tmz,</div><div class='del'>-			       struct dma_resv *resv,</div><div class='del'>-			       struct dma_fence **f);</div><div class='add'>+		       bool vm_needs_flush, uint32_t copy_flags);</div><div class='add'>+int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,</div><div class='add'>+			    struct dma_resv *resv,</div><div class='add'>+			    struct dma_fence **fence);</div><div class='ctx'> int amdgpu_fill_buffer(struct amdgpu_bo *bo,</div><div class='ctx'> 			uint32_t src_data,</div><div class='ctx'> 			struct dma_resv *resv,</div><div class='ctx'> 			struct dma_fence **fence,</div><div class='del'>-			bool delayed);</div><div class='add'>+			bool delayed,</div><div class='add'>+			u64 k_job_id);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);</div><div class='ctx'> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);</div><div class='ctx'> uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);</div><div class='ctx'> </div><div class='ctx'> #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)</div><div class='del'>-int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,</div><div class='del'>-				 struct hmm_range **range);</div><div class='del'>-void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,</div><div class='del'>-				      struct hmm_range *range);</div><div class='del'>-bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,</div><div class='del'>-				       struct hmm_range *range);</div><div class='add'>+int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,</div><div class='add'>+				 struct amdgpu_hmm_range *range);</div><div class='ctx'> #else</div><div class='ctx'> static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,</div><div class='del'>-					       struct page **pages,</div><div class='del'>-					       struct hmm_range **range)</div><div class='add'>+					       struct amdgpu_hmm_range *range)</div><div class='ctx'> {</div><div class='ctx'> 	return -EPERM;</div><div class='ctx'> }</div><div class='del'>-static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,</div><div class='del'>-						    struct hmm_range *range)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,</div><div class='del'>-						     struct hmm_range *range)</div><div class='del'>-{</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);</div><div class='add'>+void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range);</div><div class='ctx'> int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,</div><div class='ctx'> 			      uint64_t *user_addr);</div><div class='ctx'> int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c<br/>index 0867fd9e15ba..e96f24e9ad57 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c</a></div><div class='hunk'>@@ -28,6 +28,13 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_ucode.h"</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_UCODE_NAME_MAX		(128)</div><div class='add'>+</div><div class='add'>+static const struct kicker_device kicker_device_list[] = {</div><div class='add'>+	{0x744B, 0x00},</div><div class='add'>+	{0x7551, 0xC8}</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)</div><div class='ctx'> {</div><div class='ctx'> 	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr-&gt;size_bytes));</div><div class='hunk'>@@ -323,6 +330,12 @@ void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)</div><div class='ctx'> 		DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr-&gt;ctl_ucode_offset));</div><div class='ctx'> 		DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr-&gt;ctl_jt_offset));</div><div class='ctx'> 		DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr-&gt;ctl_jt_size));</div><div class='add'>+	} else if (version_major == 3) {</div><div class='add'>+		const struct sdma_firmware_header_v3_0 *sdma_hdr =</div><div class='add'>+			container_of(hdr, struct sdma_firmware_header_v3_0, header);</div><div class='add'>+</div><div class='add'>+		DRM_DEBUG("ucode_reversion: %u\n",</div><div class='add'>+			  le32_to_cpu(sdma_hdr-&gt;ucode_feature_version));</div><div class='ctx'> 	} else {</div><div class='ctx'> 		DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",</div><div class='ctx'> 			  version_major, version_minor);</div><div class='hunk'>@@ -682,6 +695,32 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)</div><div class='ctx'> 		return "UMSCH_MM_CMD_BUFFER";</div><div class='ctx'> 	case AMDGPU_UCODE_ID_JPEG_RAM:</div><div class='ctx'> 		return "JPEG";</div><div class='add'>+	case AMDGPU_UCODE_ID_SDMA_RS64:</div><div class='add'>+		return "RS64_SDMA";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_PFP:</div><div class='add'>+		return "RS64_PFP";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_ME:</div><div class='add'>+		return "RS64_ME";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_MEC:</div><div class='add'>+		return "RS64_MEC";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:</div><div class='add'>+		return "RS64_PFP_P0_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:</div><div class='add'>+		return "RS64_PFP_P1_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:</div><div class='add'>+		return "RS64_ME_P0_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:</div><div class='add'>+		return "RS64_ME_P1_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:</div><div class='add'>+		return "RS64_MEC_P0_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:</div><div class='add'>+		return "RS64_MEC_P1_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:</div><div class='add'>+		return "RS64_MEC_P2_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:</div><div class='add'>+		return "RS64_MEC_P3_STACK";</div><div class='add'>+	case AMDGPU_UCODE_ID_ISP:</div><div class='add'>+		return "ISP";</div><div class='ctx'> 	default:</div><div class='ctx'> 		return "UNKNOWN UCODE";</div><div class='ctx'> 	}</div><div class='hunk'>@@ -731,8 +770,10 @@ FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);</div><div class='ctx'> FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);</div><div class='ctx'> FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);</div><div class='ctx'> FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);</div><div class='add'>+FW_VERSION_ATTR(dmcub_fw_version, 0444, dm.dmcub_fw_version);</div><div class='ctx'> FW_VERSION_ATTR(mes_fw_version, 0444, mes.sched_version &amp; AMDGPU_MES_VERSION_MASK);</div><div class='ctx'> FW_VERSION_ATTR(mes_kiq_fw_version, 0444, mes.kiq_version &amp; AMDGPU_MES_VERSION_MASK);</div><div class='add'>+FW_VERSION_ATTR(pldm_fw_version, 0444, firmware.pldm_version);</div><div class='ctx'> </div><div class='ctx'> static struct attribute *fw_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_vce_fw_version.attr, &amp;dev_attr_uvd_fw_version.attr,</div><div class='hunk'>@@ -745,8 +786,9 @@ static struct attribute *fw_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_ta_ras_fw_version.attr, &amp;dev_attr_ta_xgmi_fw_version.attr,</div><div class='ctx'> 	&amp;dev_attr_smc_fw_version.attr, &amp;dev_attr_sdma_fw_version.attr,</div><div class='ctx'> 	&amp;dev_attr_sdma2_fw_version.attr, &amp;dev_attr_vcn_fw_version.attr,</div><div class='del'>-	&amp;dev_attr_dmcu_fw_version.attr, &amp;dev_attr_imu_fw_version.attr,</div><div class='del'>-	&amp;dev_attr_mes_fw_version.attr, &amp;dev_attr_mes_kiq_fw_version.attr,</div><div class='add'>+	&amp;dev_attr_dmcu_fw_version.attr, &amp;dev_attr_dmcub_fw_version.attr,</div><div class='add'>+	&amp;dev_attr_imu_fw_version.attr, &amp;dev_attr_mes_fw_version.attr,</div><div class='add'>+	&amp;dev_attr_mes_kiq_fw_version.attr, &amp;dev_attr_pldm_fw_version.attr,</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -791,6 +833,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,</div><div class='ctx'> 	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;</div><div class='ctx'> 	const struct mes_firmware_header_v1_0 *mes_hdr = NULL;</div><div class='ctx'> 	const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;</div><div class='add'>+	const struct sdma_firmware_header_v3_0 *sdmav3_hdr = NULL;</div><div class='ctx'> 	const struct imu_firmware_header_v1_0 *imu_hdr = NULL;</div><div class='ctx'> 	const struct vpe_firmware_header_v1_0 *vpe_hdr = NULL;</div><div class='ctx'> 	const struct umsch_mm_firmware_header_v1_0 *umsch_mm_hdr = NULL;</div><div class='hunk'>@@ -812,6 +855,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,</div><div class='ctx'> 	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode-&gt;fw-&gt;data;</div><div class='ctx'> 	mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode-&gt;fw-&gt;data;</div><div class='ctx'> 	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode-&gt;fw-&gt;data;</div><div class='add'>+	sdmav3_hdr = (const struct sdma_firmware_header_v3_0 *)ucode-&gt;fw-&gt;data;</div><div class='ctx'> 	imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode-&gt;fw-&gt;data;</div><div class='ctx'> 	vpe_hdr = (const struct vpe_firmware_header_v1_0 *)ucode-&gt;fw-&gt;data;</div><div class='ctx'> 	umsch_mm_hdr = (const struct umsch_mm_firmware_header_v1_0 *)ucode-&gt;fw-&gt;data;</div><div class='hunk'>@@ -828,6 +872,11 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,</div><div class='ctx'> 			ucode_addr = (u8 *)ucode-&gt;fw-&gt;data +</div><div class='ctx'> 				le32_to_cpu(sdma_hdr-&gt;ctl_ucode_offset);</div><div class='ctx'> 			break;</div><div class='add'>+		case AMDGPU_UCODE_ID_SDMA_RS64:</div><div class='add'>+			ucode-&gt;ucode_size = le32_to_cpu(sdmav3_hdr-&gt;ucode_size_bytes);</div><div class='add'>+			ucode_addr = (u8 *)ucode-&gt;fw-&gt;data +</div><div class='add'>+				le32_to_cpu(sdmav3_hdr-&gt;header.ucode_array_offset_bytes);</div><div class='add'>+			break;</div><div class='ctx'> 		case AMDGPU_UCODE_ID_CP_MEC1:</div><div class='ctx'> 		case AMDGPU_UCODE_ID_CP_MEC2:</div><div class='ctx'> 			ucode-&gt;ucode_size = le32_to_cpu(header-&gt;ucode_size_bytes) -</div><div class='hunk'>@@ -1111,6 +1160,9 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_virt_xgmi_migrate_enabled(adev) &amp;&amp; adev-&gt;firmware.fw_buf)</div><div class='add'>+		adev-&gt;firmware.fw_buf_mc = amdgpu_bo_fb_aper_addr(adev-&gt;firmware.fw_buf);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;firmware.max_ucodes; i++) {</div><div class='ctx'> 		ucode = &amp;adev-&gt;firmware.ucode[i];</div><div class='ctx'> 		if (ucode-&gt;fw) {</div><div class='hunk'>@@ -1175,6 +1227,7 @@ static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int bl</div><div class='ctx'> 		case IP_VERSION(11, 0, 13):</div><div class='ctx'> 			return "beige_goby";</div><div class='ctx'> 		case IP_VERSION(11, 5, 0):</div><div class='add'>+		case IP_VERSION(11, 5, 2):</div><div class='ctx'> 			return "vangogh";</div><div class='ctx'> 		case IP_VERSION(12, 0, 1):</div><div class='ctx'> 			return "green_sardine";</div><div class='hunk'>@@ -1342,6 +1395,19 @@ static const char *amdgpu_ucode_legacy_naming(struct amdgpu_device *adev, int bl</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool amdgpu_is_kicker_fw(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(kicker_device_list); i++) {</div><div class='add'>+		if (adev-&gt;pdev-&gt;device == kicker_device_list[i].device &amp;&amp;</div><div class='add'>+		    adev-&gt;pdev-&gt;revision == kicker_device_list[i].revision)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)</div><div class='ctx'> {</div><div class='ctx'> 	int maj, min, rev;</div><div class='hunk'>@@ -1374,6 +1440,9 @@ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type,</div><div class='ctx'> 	case VPE_HWIP:</div><div class='ctx'> 		ip_name = "vpe";</div><div class='ctx'> 		break;</div><div class='add'>+	case ISP_HWIP:</div><div class='add'>+		ip_name = "isp";</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		BUG();</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1390,28 +1459,49 @@ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type,</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu device</div><div class='ctx'>  * @fw: pointer to load firmware to</div><div class='del'>- * @fw_name: firmware to load</div><div class='add'>+ * @required: whether the firmware is required</div><div class='add'>+ * @fmt: firmware name format string</div><div class='add'>+ * @...: variable arguments</div><div class='ctx'>  *</div><div class='ctx'>  * This is a helper that will use request_firmware and amdgpu_ucode_validate</div><div class='ctx'>  * to load and run basic validation on firmware. If the load fails, remap</div><div class='ctx'>  * the error code to -ENODEV, so that early_init functions will fail to load.</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,</div><div class='del'>-			 const char *fw_name)</div><div class='add'>+			 enum amdgpu_ucode_required required, const char *fmt, ...)</div><div class='ctx'> {</div><div class='del'>-	int err = request_firmware(fw, fw_name, adev-&gt;dev);</div><div class='add'>+	char fname[AMDGPU_UCODE_NAME_MAX];</div><div class='add'>+	va_list ap;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	va_start(ap, fmt);</div><div class='add'>+	r = vsnprintf(fname, sizeof(fname), fmt, ap);</div><div class='add'>+	va_end(ap);</div><div class='add'>+	if (r == sizeof(fname)) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "amdgpu firmware name buffer overflow\n");</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (err)</div><div class='add'>+	if (required == AMDGPU_UCODE_REQUIRED)</div><div class='add'>+		r = request_firmware(fw, fname, adev-&gt;dev);</div><div class='add'>+	else {</div><div class='add'>+		r = firmware_request_nowarn(fw, fname, adev-&gt;dev);</div><div class='add'>+		if (r)</div><div class='add'>+			drm_info(&amp;adev-&gt;ddev, "Optional firmware \"%s\" was not found\n", fname);</div><div class='add'>+	}</div><div class='add'>+	if (r)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	err = amdgpu_ucode_validate(*fw);</div><div class='del'>-	if (err) {</div><div class='del'>-		dev_dbg(adev-&gt;dev, "\"%s\" failed to validate\n", fw_name);</div><div class='del'>-		release_firmware(*fw);</div><div class='del'>-		*fw = NULL;</div><div class='del'>-	}</div><div class='add'>+	r = amdgpu_ucode_validate(*fw);</div><div class='add'>+	if (r)</div><div class='add'>+		/*</div><div class='add'>+		 * The amdgpu_ucode_request() should be paired with amdgpu_ucode_release()</div><div class='add'>+		 * regardless of success/failure, and the amdgpu_ucode_release() takes care of</div><div class='add'>+		 * firmware release and need to avoid redundant release FW operation here.</div><div class='add'>+		 */</div><div class='add'>+		dev_dbg(adev-&gt;dev, "\"%s\" failed to validate\n", fname);</div><div class='ctx'> </div><div class='del'>-	return err;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h<br/>index 619445760037..6349aad6da35 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h</a></div><div class='hunk'>@@ -25,6 +25,8 @@</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_socbb.h"</div><div class='ctx'> </div><div class='add'>+#define RS64_FW_UC_START_ADDR_LO 0x3000</div><div class='add'>+</div><div class='ctx'> struct common_firmware_header {</div><div class='ctx'> 	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */</div><div class='ctx'> 	uint32_t header_size_bytes; /* size of just the header in bytes */</div><div class='hunk'>@@ -125,6 +127,8 @@ enum psp_fw_type {</div><div class='ctx'> 	PSP_FW_TYPE_PSP_INTF_DRV,</div><div class='ctx'> 	PSP_FW_TYPE_PSP_DBG_DRV,</div><div class='ctx'> 	PSP_FW_TYPE_PSP_RAS_DRV,</div><div class='add'>+	PSP_FW_TYPE_PSP_IPKEYMGR_DRV,</div><div class='add'>+	PSP_FW_TYPE_PSP_SPDM_DRV,</div><div class='ctx'> 	PSP_FW_TYPE_MAX_INDEX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -135,6 +139,14 @@ struct psp_firmware_header_v2_0 {</div><div class='ctx'> 	struct psp_fw_bin_desc psp_fw_bin[];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* version_major=2, version_minor=1 */</div><div class='add'>+struct psp_firmware_header_v2_1 {</div><div class='add'>+	struct common_firmware_header header;</div><div class='add'>+	uint32_t psp_fw_bin_count;</div><div class='add'>+	uint32_t psp_aux_fw_bin_index;</div><div class='add'>+	struct psp_fw_bin_desc psp_fw_bin[];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* version_major=1, version_minor=0 */</div><div class='ctx'> struct ta_firmware_header_v1_0 {</div><div class='ctx'> 	struct common_firmware_header header;</div><div class='hunk'>@@ -154,6 +166,7 @@ enum ta_fw_type {</div><div class='ctx'> 	TA_FW_TYPE_PSP_DTM,</div><div class='ctx'> 	TA_FW_TYPE_PSP_RAP,</div><div class='ctx'> 	TA_FW_TYPE_PSP_SECUREDISPLAY,</div><div class='add'>+	TA_FW_TYPE_PSP_XGMI_AUX,</div><div class='ctx'> 	TA_FW_TYPE_MAX_INDEX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -345,6 +358,14 @@ struct umsch_mm_firmware_header_v1_0 {</div><div class='ctx'> 	uint32_t umsch_mm_data_start_addr_hi;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* version_major=3, version_minor=0 */</div><div class='add'>+struct sdma_firmware_header_v3_0 {</div><div class='add'>+    struct common_firmware_header header;</div><div class='add'>+    uint32_t ucode_feature_version;</div><div class='add'>+    uint32_t ucode_offset_bytes;</div><div class='add'>+    uint32_t ucode_size_bytes;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* gpu info payload */</div><div class='ctx'> struct gpu_info_firmware_v1_0 {</div><div class='ctx'> 	uint32_t gc_num_se;</div><div class='hunk'>@@ -417,6 +438,7 @@ union amdgpu_firmware_header {</div><div class='ctx'> 	struct psp_firmware_header_v1_1 psp_v1_1;</div><div class='ctx'> 	struct psp_firmware_header_v1_3 psp_v1_3;</div><div class='ctx'> 	struct psp_firmware_header_v2_0 psp_v2_0;</div><div class='add'>+	struct psp_firmware_header_v2_0 psp_v2_1;</div><div class='ctx'> 	struct ta_firmware_header_v1_0 ta;</div><div class='ctx'> 	struct ta_firmware_header_v2_0 ta_v2_0;</div><div class='ctx'> 	struct gfx_firmware_header_v1_0 gfx;</div><div class='hunk'>@@ -430,6 +452,7 @@ union amdgpu_firmware_header {</div><div class='ctx'> 	struct sdma_firmware_header_v1_0 sdma;</div><div class='ctx'> 	struct sdma_firmware_header_v1_1 sdma_v1_1;</div><div class='ctx'> 	struct sdma_firmware_header_v2_0 sdma_v2_0;</div><div class='add'>+	struct sdma_firmware_header_v3_0 sdma_v3_0;</div><div class='ctx'> 	struct gpu_info_firmware_header_v1_0 gpu_info;</div><div class='ctx'> 	struct dmcu_firmware_header_v1_0 dmcu;</div><div class='ctx'> 	struct dmcub_firmware_header_v1_0 dmcub;</div><div class='hunk'>@@ -437,7 +460,7 @@ union amdgpu_firmware_header {</div><div class='ctx'> 	uint8_t raw[0x100];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc))</div><div class='add'>+#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * fw loading support</div><div class='hunk'>@@ -454,6 +477,7 @@ enum AMDGPU_UCODE_ID {</div><div class='ctx'> 	AMDGPU_UCODE_ID_SDMA7,</div><div class='ctx'> 	AMDGPU_UCODE_ID_SDMA_UCODE_TH0,</div><div class='ctx'> 	AMDGPU_UCODE_ID_SDMA_UCODE_TH1,</div><div class='add'>+	AMDGPU_UCODE_ID_SDMA_RS64,</div><div class='ctx'> 	AMDGPU_UCODE_ID_CP_CE,</div><div class='ctx'> 	AMDGPU_UCODE_ID_CP_PFP,</div><div class='ctx'> 	AMDGPU_UCODE_ID_CP_ME,</div><div class='hunk'>@@ -512,6 +536,7 @@ enum AMDGPU_UCODE_ID {</div><div class='ctx'> 	AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,</div><div class='ctx'> 	AMDGPU_UCODE_ID_P2S_TABLE,</div><div class='ctx'> 	AMDGPU_UCODE_ID_JPEG_RAM,</div><div class='add'>+	AMDGPU_UCODE_ID_ISP,</div><div class='ctx'> 	AMDGPU_UCODE_ID_MAXIMUM,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -529,6 +554,11 @@ enum amdgpu_firmware_load_type {</div><div class='ctx'> 	AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum amdgpu_ucode_required {</div><div class='add'>+	AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+	AMDGPU_UCODE_REQUIRED,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* conform to smu_ucode_xfer_cz.h */</div><div class='ctx'> #define AMDGPU_SDMA0_UCODE_LOADED	0x00000001</div><div class='ctx'> #define AMDGPU_SDMA1_UCODE_LOADED	0x00000002</div><div class='hunk'>@@ -572,6 +602,12 @@ struct amdgpu_firmware {</div><div class='ctx'> </div><div class='ctx'> 	void *fw_buf_ptr;</div><div class='ctx'> 	uint64_t fw_buf_mc;</div><div class='add'>+	uint32_t pldm_version;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct kicker_device{</div><div class='add'>+	unsigned short device;</div><div class='add'>+	u8 revision;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);</div><div class='hunk'>@@ -582,8 +618,9 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);</div><div class='ctx'> void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);</div><div class='ctx'> void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);</div><div class='ctx'> void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);</div><div class='add'>+__printf(4, 5)</div><div class='ctx'> int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,</div><div class='del'>-			 const char *fw_name);</div><div class='add'>+			 enum amdgpu_ucode_required required, const char *fmt, ...);</div><div class='ctx'> void amdgpu_ucode_release(const struct firmware **fw);</div><div class='ctx'> bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,</div><div class='ctx'> 				uint16_t hdr_major, uint16_t hdr_minor);</div><div class='hunk'>@@ -600,5 +637,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);</div><div class='ctx'> const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);</div><div class='add'>+bool amdgpu_is_kicker_fw(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c<br/>index 20436f81856a..3f0b0e9af4f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c</a></div><div class='hunk'>@@ -21,10 +21,14 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/sort.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "umc_v6_7.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> #define MAX_UMC_POISON_POLLING_TIME_SYNC   20  //ms</div><div class='ctx'> </div><div class='add'>+#define MAX_UMC_HASH_STRING_SIZE  256</div><div class='add'>+</div><div class='ctx'> static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev,</div><div class='ctx'> 				    struct ras_err_data *err_data, uint64_t err_addr,</div><div class='ctx'> 				    uint32_t ch_inst, uint32_t umc_inst)</div><div class='hunk'>@@ -63,6 +67,8 @@ int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,</div><div class='ctx'> 		goto out_fini_err_data;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	err_data.err_addr_len = adev-&gt;umc.max_ras_err_cnt_per_query;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Translate UMC channel address to Physical address</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -73,7 +79,7 @@ int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_bad_page_threshold != 0) {</div><div class='ctx'> 		amdgpu_ras_add_bad_pages(adev, err_data.err_addr,</div><div class='del'>-						err_data.err_addr_cnt);</div><div class='add'>+						err_data.err_addr_cnt, false);</div><div class='ctx'> 		amdgpu_ras_save_bad_pages(adev, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -86,68 +92,101 @@ out_fini_err_data:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,</div><div class='add'>+void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> 			void *ras_error_status)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct amdgpu_ras_eeprom_control *control = &amp;con-&gt;eeprom_control;</div><div class='ctx'> 	unsigned int error_query_mode;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	unsigned long err_count;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_get_error_query_mode(adev, &amp;error_query_mode);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;con-&gt;page_retirement_lock);</div><div class='del'>-	ret = amdgpu_dpm_get_ecc_info(adev, (void *)&amp;(con-&gt;umc_ecc));</div><div class='del'>-	if (ret == -EOPNOTSUPP &amp;&amp;</div><div class='del'>-	    error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {</div><div class='del'>-		if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;ras_block.hw_ops &amp;&amp;</div><div class='del'>-		    adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_count)</div><div class='del'>-		    adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_count(adev, ras_error_status);</div><div class='del'>-</div><div class='del'>-		if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;ras_block.hw_ops &amp;&amp;</div><div class='del'>-		    adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_address &amp;&amp;</div><div class='del'>-		    adev-&gt;umc.max_ras_err_cnt_per_query) {</div><div class='del'>-			err_data-&gt;err_addr =</div><div class='del'>-				kcalloc(adev-&gt;umc.max_ras_err_cnt_per_query,</div><div class='del'>-					sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='del'>-</div><div class='del'>-			/* still call query_ras_error_address to clear error status</div><div class='del'>-			 * even NOMEM error is encountered</div><div class='del'>-			 */</div><div class='del'>-			if(!err_data-&gt;err_addr)</div><div class='del'>-				dev_warn(adev-&gt;dev, "Failed to alloc memory for "</div><div class='del'>-						"umc error address record!\n");</div><div class='add'>+	err_data-&gt;err_addr =</div><div class='add'>+		kcalloc(adev-&gt;umc.max_ras_err_cnt_per_query,</div><div class='add'>+			sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-			/* umc query_ras_error_address is also responsible for clearing</div><div class='del'>-			 * error status</div><div class='del'>-			 */</div><div class='del'>-			adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_address(adev, ras_error_status);</div><div class='del'>-		}</div><div class='del'>-	} else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||</div><div class='del'>-	    (!ret &amp;&amp; error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {</div><div class='del'>-		if (adev-&gt;umc.ras &amp;&amp;</div><div class='del'>-		    adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_count)</div><div class='del'>-		    adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_count(adev, ras_error_status);</div><div class='del'>-</div><div class='del'>-		if (adev-&gt;umc.ras &amp;&amp;</div><div class='del'>-		    adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_address &amp;&amp;</div><div class='del'>-		    adev-&gt;umc.max_ras_err_cnt_per_query) {</div><div class='del'>-			err_data-&gt;err_addr =</div><div class='del'>-				kcalloc(adev-&gt;umc.max_ras_err_cnt_per_query,</div><div class='del'>-					sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='del'>-</div><div class='del'>-			/* still call query_ras_error_address to clear error status</div><div class='del'>-			 * even NOMEM error is encountered</div><div class='del'>-			 */</div><div class='del'>-			if(!err_data-&gt;err_addr)</div><div class='del'>-				dev_warn(adev-&gt;dev, "Failed to alloc memory for "</div><div class='del'>-						"umc error address record!\n");</div><div class='add'>+	/* still call query_ras_error_address to clear error status</div><div class='add'>+	 * even NOMEM error is encountered</div><div class='add'>+	 */</div><div class='add'>+	if (!err_data-&gt;err_addr)</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			"Failed to alloc memory for umc error address record!\n");</div><div class='add'>+	else</div><div class='add'>+		err_data-&gt;err_addr_len = adev-&gt;umc.max_ras_err_cnt_per_query;</div><div class='ctx'> </div><div class='del'>-			/* umc query_ras_error_address is also responsible for clearing</div><div class='del'>-			 * error status</div><div class='del'>-			 */</div><div class='del'>-			adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_address(adev, ras_error_status);</div><div class='add'>+	mutex_lock(&amp;con-&gt;page_retirement_lock);</div><div class='add'>+	if (!amdgpu_ras_smu_eeprom_supported(adev)) {</div><div class='add'>+		ret = amdgpu_dpm_get_ecc_info(adev, (void *)&amp;(con-&gt;umc_ecc));</div><div class='add'>+		if (ret == -EOPNOTSUPP &amp;&amp;</div><div class='add'>+		    error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {</div><div class='add'>+			if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;ras_block.hw_ops &amp;&amp;</div><div class='add'>+			    adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_count)</div><div class='add'>+				adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_count(adev,</div><div class='add'>+								ras_error_status);</div><div class='add'>+</div><div class='add'>+			if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;ras_block.hw_ops &amp;&amp;</div><div class='add'>+			    adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_address &amp;&amp;</div><div class='add'>+			    adev-&gt;umc.max_ras_err_cnt_per_query) {</div><div class='add'>+				err_data-&gt;err_addr =</div><div class='add'>+					kcalloc(adev-&gt;umc.max_ras_err_cnt_per_query,</div><div class='add'>+						sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+				/* still call query_ras_error_address to clear error status</div><div class='add'>+				 * even NOMEM error is encountered</div><div class='add'>+				 */</div><div class='add'>+				if (!err_data-&gt;err_addr)</div><div class='add'>+					dev_warn(adev-&gt;dev,</div><div class='add'>+						"Failed to alloc memory for umc error address record!\n");</div><div class='add'>+				else</div><div class='add'>+					err_data-&gt;err_addr_len =</div><div class='add'>+						adev-&gt;umc.max_ras_err_cnt_per_query;</div><div class='add'>+</div><div class='add'>+				/* umc query_ras_error_address is also responsible for clearing</div><div class='add'>+				 * error status</div><div class='add'>+				 */</div><div class='add'>+				adev-&gt;umc.ras-&gt;ras_block.hw_ops-&gt;query_ras_error_address(adev,</div><div class='add'>+								ras_error_status);</div><div class='add'>+			}</div><div class='add'>+		} else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||</div><div class='add'>+		    (!ret &amp;&amp; error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {</div><div class='add'>+			if (adev-&gt;umc.ras &amp;&amp;</div><div class='add'>+			    adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_count)</div><div class='add'>+				adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_count(adev,</div><div class='add'>+								ras_error_status);</div><div class='add'>+</div><div class='add'>+			if (adev-&gt;umc.ras &amp;&amp;</div><div class='add'>+			    adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_address &amp;&amp;</div><div class='add'>+			    adev-&gt;umc.max_ras_err_cnt_per_query) {</div><div class='add'>+				err_data-&gt;err_addr =</div><div class='add'>+					kcalloc(adev-&gt;umc.max_ras_err_cnt_per_query,</div><div class='add'>+						sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+				/* still call query_ras_error_address to clear error status</div><div class='add'>+				 * even NOMEM error is encountered</div><div class='add'>+				 */</div><div class='add'>+				if (!err_data-&gt;err_addr)</div><div class='add'>+					dev_warn(adev-&gt;dev,</div><div class='add'>+						"Failed to alloc memory for umc error address record!\n");</div><div class='add'>+				else</div><div class='add'>+					err_data-&gt;err_addr_len =</div><div class='add'>+						adev-&gt;umc.max_ras_err_cnt_per_query;</div><div class='add'>+</div><div class='add'>+				/* umc query_ras_error_address is also responsible for clearing</div><div class='add'>+				 * error status</div><div class='add'>+				 */</div><div class='add'>+				adev-&gt;umc.ras-&gt;ecc_info_query_ras_error_address(adev,</div><div class='add'>+								ras_error_status);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (!amdgpu_ras_eeprom_update_record_num(control)) {</div><div class='add'>+			err_data-&gt;err_addr_cnt = err_data-&gt;de_count =</div><div class='add'>+				control-&gt;ras_num_recs -	control-&gt;ras_num_recs_old;</div><div class='add'>+			amdgpu_ras_eeprom_read_idx(control, err_data-&gt;err_addr,</div><div class='add'>+				control-&gt;ras_num_recs_old, err_data-&gt;de_count);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -157,10 +196,11 @@ static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> 		if ((amdgpu_bad_page_threshold != 0) &amp;&amp;</div><div class='ctx'> 			err_data-&gt;err_addr_cnt) {</div><div class='ctx'> 			amdgpu_ras_add_bad_pages(adev, err_data-&gt;err_addr,</div><div class='del'>-						err_data-&gt;err_addr_cnt);</div><div class='add'>+				err_data-&gt;err_addr_cnt, amdgpu_ras_smu_eeprom_supported(adev));</div><div class='ctx'> 			amdgpu_ras_save_bad_pages(adev, &amp;err_count);</div><div class='ctx'> </div><div class='del'>-			amdgpu_dpm_send_hbm_bad_pages_num(adev, con-&gt;eeprom_control.ras_num_recs);</div><div class='add'>+			amdgpu_dpm_send_hbm_bad_pages_num(adev,</div><div class='add'>+					con-&gt;eeprom_control.ras_num_bad_pages);</div><div class='ctx'> </div><div class='ctx'> 			if (con-&gt;update_channel_flag == true) {</div><div class='ctx'> 				amdgpu_dpm_send_hbm_bad_channel_flag(adev, con-&gt;eeprom_control.bad_channel_bitmap);</div><div class='hunk'>@@ -170,6 +210,7 @@ static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(err_data-&gt;err_addr);</div><div class='add'>+	err_data-&gt;err_addr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;con-&gt;page_retirement_lock);</div><div class='ctx'> }</div><div class='hunk'>@@ -177,7 +218,7 @@ static void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,</div><div class='ctx'> static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,</div><div class='ctx'> 		void *ras_error_status,</div><div class='ctx'> 		struct amdgpu_iv_entry *entry,</div><div class='del'>-		bool reset)</div><div class='add'>+		uint32_t reset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='hunk'>@@ -185,69 +226,18 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,</div><div class='ctx'> 	kgd2kfd_set_sram_ecc_flag(adev-&gt;kfd.dev);</div><div class='ctx'> 	amdgpu_umc_handle_bad_pages(adev, ras_error_status);</div><div class='ctx'> </div><div class='del'>-	if (err_data-&gt;ue_count &amp;&amp; reset) {</div><div class='del'>-		/* use mode-2 reset for poison consumption */</div><div class='del'>-		if (!entry)</div><div class='del'>-			con-&gt;gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+	if ((err_data-&gt;ue_count || err_data-&gt;de_count) &amp;&amp;</div><div class='add'>+	    (reset || amdgpu_ras_is_rma(adev))) {</div><div class='add'>+		con-&gt;gpu_reset_flags |= reset;</div><div class='ctx'> 		amdgpu_ras_reset_gpu(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return AMDGPU_RAS_SUCCESS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,</div><div class='del'>-			bool reset, uint32_t timeout_ms)</div><div class='del'>-{</div><div class='del'>-	struct ras_err_data err_data;</div><div class='del'>-	struct ras_common_if head = {</div><div class='del'>-		.block = AMDGPU_RAS_BLOCK__UMC,</div><div class='del'>-	};</div><div class='del'>-	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &amp;head);</div><div class='del'>-	uint32_t timeout = timeout_ms;</div><div class='del'>-</div><div class='del'>-	memset(&amp;err_data, 0, sizeof(err_data));</div><div class='del'>-	amdgpu_ras_error_data_init(&amp;err_data);</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-</div><div class='del'>-		amdgpu_umc_handle_bad_pages(adev, &amp;err_data);</div><div class='del'>-</div><div class='del'>-		if (timeout &amp;&amp; !err_data.de_count) {</div><div class='del'>-			msleep(1);</div><div class='del'>-			timeout--;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	} while (timeout &amp;&amp; !err_data.de_count);</div><div class='del'>-</div><div class='del'>-	if (!timeout)</div><div class='del'>-		dev_warn(adev-&gt;dev, "Can't find bad pages\n");</div><div class='del'>-</div><div class='del'>-	if (err_data.de_count)</div><div class='del'>-		dev_info(adev-&gt;dev, "%ld new deferred hardware errors detected\n", err_data.de_count);</div><div class='del'>-</div><div class='del'>-	if (obj) {</div><div class='del'>-		obj-&gt;err_data.ue_count += err_data.ue_count;</div><div class='del'>-		obj-&gt;err_data.ce_count += err_data.ce_count;</div><div class='del'>-		obj-&gt;err_data.de_count += err_data.de_count;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_ras_error_data_fini(&amp;err_data);</div><div class='del'>-</div><div class='del'>-	kgd2kfd_set_sram_ecc_flag(adev-&gt;kfd.dev);</div><div class='del'>-</div><div class='del'>-	if (reset) {</div><div class='del'>-		struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='del'>-</div><div class='del'>-		/* use mode-2 reset for poison consumption */</div><div class='del'>-		con-&gt;gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='del'>-		amdgpu_ras_reset_gpu(adev);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_umc_poison_handler(struct amdgpu_device *adev,</div><div class='del'>-			enum amdgpu_ras_block block, bool reset)</div><div class='add'>+int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev,</div><div class='add'>+			enum amdgpu_ras_block block, uint16_t pasid,</div><div class='add'>+			pasid_notify pasid_fn, void *data, uint32_t reset)</div><div class='ctx'> {</div><div class='ctx'> 	int ret = AMDGPU_RAS_SUCCESS;</div><div class='ctx'> </div><div class='hunk'>@@ -284,15 +274,24 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev,</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			amdgpu_ras_error_data_fini(&amp;err_data);</div><div class='add'>+		} else if (amdgpu_uniras_enabled(adev)) {</div><div class='add'>+			struct ras_ih_info ih_info = {0};</div><div class='add'>+</div><div class='add'>+			ih_info.block = block;</div><div class='add'>+			ih_info.pasid = pasid;</div><div class='add'>+			ih_info.reset = reset;</div><div class='add'>+			ih_info.pasid_fn = pasid_fn;</div><div class='add'>+			ih_info.data = data;</div><div class='add'>+			amdgpu_ras_mgr_handle_consumer_interrupt(adev, &amp;ih_info);</div><div class='ctx'> 		} else {</div><div class='del'>-			if (reset) {</div><div class='del'>-				amdgpu_umc_bad_page_polling_timeout(adev,</div><div class='del'>-							reset, MAX_UMC_POISON_POLLING_TIME_SYNC);</div><div class='del'>-			} else {</div><div class='del'>-				struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+			struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+			int ret;</div><div class='ctx'> </div><div class='add'>+			ret = amdgpu_ras_put_poison_req(adev,</div><div class='add'>+				block, pasid, pasid_fn, data, reset);</div><div class='add'>+			if (!ret) {</div><div class='ctx'> 				atomic_inc(&amp;con-&gt;page_retirement_req_cnt);</div><div class='del'>-</div><div class='add'>+				atomic_inc(&amp;con-&gt;poison_consumption_count);</div><div class='ctx'> 				wake_up(&amp;con-&gt;page_retirement_wq);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -307,11 +306,19 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_umc_poison_handler(struct amdgpu_device *adev,</div><div class='add'>+			enum amdgpu_ras_block block, uint32_t reset)</div><div class='add'>+{</div><div class='add'>+	return amdgpu_umc_pasid_poison_handler(adev,</div><div class='add'>+				block, 0, NULL, NULL, reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,</div><div class='ctx'> 		void *ras_error_status,</div><div class='ctx'> 		struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);</div><div class='add'>+	return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry,</div><div class='add'>+				AMDGPU_RAS_GPU_RESET_MODE1_RESET);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev)</div><div class='hunk'>@@ -352,6 +359,9 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_ras_is_supported(adev, ras_block-&gt;block)) {</div><div class='ctx'> 		r = amdgpu_irq_get(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='ctx'> 		if (r)</div><div class='hunk'>@@ -388,14 +398,20 @@ int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,</div><div class='add'>+int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,</div><div class='ctx'> 		uint64_t err_addr,</div><div class='ctx'> 		uint64_t retired_page,</div><div class='ctx'> 		uint32_t channel_index,</div><div class='ctx'> 		uint32_t umc_inst)</div><div class='ctx'> {</div><div class='del'>-	struct eeprom_table_record *err_rec =</div><div class='del'>-		&amp;err_data-&gt;err_addr[err_data-&gt;err_addr_cnt];</div><div class='add'>+	struct eeprom_table_record *err_rec;</div><div class='add'>+</div><div class='add'>+	if (!err_data ||</div><div class='add'>+	    !err_data-&gt;err_addr ||</div><div class='add'>+	    (err_data-&gt;err_addr_cnt &gt;= err_data-&gt;err_addr_len))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	err_rec = &amp;err_data-&gt;err_addr[err_data-&gt;err_addr_cnt];</div><div class='ctx'> </div><div class='ctx'> 	err_rec-&gt;address = err_addr;</div><div class='ctx'> 	/* page frame address is saved */</div><div class='hunk'>@@ -407,6 +423,47 @@ void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,</div><div class='ctx'> 	err_rec-&gt;mcumc_id = umc_inst;</div><div class='ctx'> </div><div class='ctx'> 	err_data-&gt;err_addr_cnt++;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_umc_loop_all_aid(struct amdgpu_device *adev, umc_func func,</div><div class='add'>+				   void *data)</div><div class='add'>+{</div><div class='add'>+	uint32_t umc_node_inst;</div><div class='add'>+	uint32_t node_inst;</div><div class='add'>+	uint32_t umc_inst;</div><div class='add'>+	uint32_t ch_inst;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This loop is done based on the following -</div><div class='add'>+	 * umc.active mask = mask of active umc instances across all nodes</div><div class='add'>+	 * umc.umc_inst_num = maximum number of umc instancess per node</div><div class='add'>+	 * umc.node_inst_num = maximum number of node instances</div><div class='add'>+	 * Channel instances are not assumed to be harvested.</div><div class='add'>+	 */</div><div class='add'>+	dev_dbg(adev-&gt;dev, "active umcs :%lx umc_inst per node: %d",</div><div class='add'>+		adev-&gt;umc.active_mask, adev-&gt;umc.umc_inst_num);</div><div class='add'>+	for_each_set_bit(umc_node_inst, &amp;(adev-&gt;umc.active_mask),</div><div class='add'>+			 adev-&gt;umc.node_inst_num * adev-&gt;umc.umc_inst_num) {</div><div class='add'>+		node_inst = umc_node_inst / adev-&gt;umc.umc_inst_num;</div><div class='add'>+		umc_inst = umc_node_inst % adev-&gt;umc.umc_inst_num;</div><div class='add'>+		LOOP_UMC_CH_INST(ch_inst) {</div><div class='add'>+			dev_dbg(adev-&gt;dev,</div><div class='add'>+				"node_inst :%d umc_inst: %d ch_inst: %d",</div><div class='add'>+				node_inst, umc_inst, ch_inst);</div><div class='add'>+			ret = func(adev, node_inst, umc_inst, ch_inst, data);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='add'>+					"Node %d umc %d ch %d func returns %d\n",</div><div class='add'>+					node_inst, umc_inst, ch_inst, ret);</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_umc_loop_channels(struct amdgpu_device *adev,</div><div class='hunk'>@@ -417,6 +474,9 @@ int amdgpu_umc_loop_channels(struct amdgpu_device *adev,</div><div class='ctx'> 	uint32_t ch_inst         = 0;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;aid_mask)</div><div class='add'>+		return amdgpu_umc_loop_all_aid(adev, func, data);</div><div class='add'>+</div><div class='ctx'> 	if (adev-&gt;umc.node_inst_num) {</div><div class='ctx'> 		LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {</div><div class='ctx'> 			ret = func(adev, node_inst, umc_inst, ch_inst, data);</div><div class='hunk'>@@ -439,3 +499,129 @@ int amdgpu_umc_loop_channels(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev,</div><div class='add'>+				uint64_t status, uint64_t ipid, uint64_t addr)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;umc.ras-&gt;update_ecc_status)</div><div class='add'>+		return adev-&gt;umc.ras-&gt;update_ecc_status(adev,</div><div class='add'>+					status, ipid, addr);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev,</div><div class='add'>+		struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_ecc_log_info *ecc_log;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ecc_log = &amp;con-&gt;umc_ecc_log;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ecc_log-&gt;lock);</div><div class='add'>+	ret = radix_tree_insert(ecc_tree, ecc_err-&gt;pa_pfn, ecc_err);</div><div class='add'>+	if (!ret)</div><div class='add'>+		radix_tree_tag_set(ecc_tree,</div><div class='add'>+			ecc_err-&gt;pa_pfn, UMC_ECC_NEW_DETECTED_TAG);</div><div class='add'>+	mutex_unlock(&amp;ecc_log-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_umc_pages_in_a_row(struct amdgpu_device *adev,</div><div class='add'>+			struct ras_err_data *err_data, uint64_t pa_addr)</div><div class='add'>+{</div><div class='add'>+	struct ta_ras_query_address_output addr_out;</div><div class='add'>+</div><div class='add'>+	/* reinit err_data */</div><div class='add'>+	err_data-&gt;err_addr_cnt = 0;</div><div class='add'>+	err_data-&gt;err_addr_len = adev-&gt;umc.retire_unit;</div><div class='add'>+</div><div class='add'>+	addr_out.pa.pa = pa_addr;</div><div class='add'>+	if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;convert_ras_err_addr)</div><div class='add'>+		return adev-&gt;umc.ras-&gt;convert_ras_err_addr(adev, err_data, NULL,</div><div class='add'>+				&amp;addr_out, false);</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_umc_lookup_bad_pages_in_a_row(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t pa_addr, uint64_t *pfns, int len)</div><div class='add'>+{</div><div class='add'>+	int i, ret;</div><div class='add'>+	struct ras_err_data err_data;</div><div class='add'>+</div><div class='add'>+	err_data.err_addr = kcalloc(adev-&gt;umc.retire_unit,</div><div class='add'>+				sizeof(struct eeprom_table_record), GFP_KERNEL);</div><div class='add'>+	if (!err_data.err_addr) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to alloc memory in bad page lookup!\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_umc_pages_in_a_row(adev, &amp;err_data, pa_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;umc.retire_unit; i++) {</div><div class='add'>+		if (i &gt;= len)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		pfns[i] = err_data.err_addr[i].retired_page;</div><div class='add'>+	}</div><div class='add'>+	ret = i;</div><div class='add'>+	adev-&gt;umc.err_addr_cnt = err_data.err_addr_cnt;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(err_data.err_addr);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_umc_mca_to_addr(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t err_addr, uint32_t ch, uint32_t umc,</div><div class='add'>+			uint32_t node, uint32_t socket,</div><div class='add'>+			struct ta_ras_query_address_output *addr_out, bool dump_addr)</div><div class='add'>+{</div><div class='add'>+	struct ta_ras_query_address_input addr_in;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	memset(&amp;addr_in, 0, sizeof(addr_in));</div><div class='add'>+	addr_in.ma.err_addr = err_addr;</div><div class='add'>+	addr_in.ma.ch_inst = ch;</div><div class='add'>+	addr_in.ma.umc_inst = umc;</div><div class='add'>+	addr_in.ma.node_inst = node;</div><div class='add'>+	addr_in.ma.socket_id = socket;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;umc.ras &amp;&amp; adev-&gt;umc.ras-&gt;convert_ras_err_addr) {</div><div class='add'>+		ret = adev-&gt;umc.ras-&gt;convert_ras_err_addr(adev, NULL, &amp;addr_in,</div><div class='add'>+				addr_out, dump_addr);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	} else {</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_umc_pa2mca(struct amdgpu_device *adev,</div><div class='add'>+		uint64_t pa, uint64_t *mca, enum amdgpu_memory_partition nps)</div><div class='add'>+{</div><div class='add'>+	struct ta_ras_query_address_input addr_in;</div><div class='add'>+	struct ta_ras_query_address_output addr_out;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* nps: the pa belongs to */</div><div class='add'>+	addr_in.pa.pa = pa | ((uint64_t)nps &lt;&lt; 58);</div><div class='add'>+	addr_in.addr_type = TA_RAS_PA_TO_MCA;</div><div class='add'>+	ret = psp_ras_query_address(&amp;adev-&gt;psp, &amp;addr_in, &amp;addr_out);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "Failed to query RAS MCA address for 0x%llx",</div><div class='add'>+			pa);</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*mca = addr_out.ma.err_addr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h<br/>index 26d2ae498daf..28dff750c47e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h</a></div><div class='hunk'>@@ -52,6 +52,43 @@</div><div class='ctx'> #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \</div><div class='ctx'> 		LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))</div><div class='ctx'> </div><div class='add'>+/* Page retirement tag */</div><div class='add'>+#define UMC_ECC_NEW_DETECTED_TAG       0x1</div><div class='add'>+/*</div><div class='add'>+ * a flag to indicate v2 of channel index stored in eeprom</div><div class='add'>+ *</div><div class='add'>+ * v1 (legacy way): store channel index within a umc instance in eeprom</div><div class='add'>+ *    range in UMC v12: 0 ~ 7</div><div class='add'>+ * v2: store global channel index in eeprom</div><div class='add'>+ *    range in UMC v12: 0 ~ 127</div><div class='add'>+ *</div><div class='add'>+ * NOTE: it's better to store it in eeprom_table_record.mem_channel,</div><div class='add'>+ * but there is only 8 bits in mem_channel, and the channel number may</div><div class='add'>+ * increase in the future, we decide to save it in</div><div class='add'>+ * eeprom_table_record.retired_page. retired_page is useless in v2,</div><div class='add'>+ * we depend on eeprom_table_record.address instead of retired_page in v2.</div><div class='add'>+ * Only 48 bits are saved on eeprom, use bit 47 here.</div><div class='add'>+ */</div><div class='add'>+#define UMC_CHANNEL_IDX_V2	BIT_ULL(47)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * save nps value to eeprom_table_record.retired_page[47:40],</div><div class='add'>+ * the channel index flag above will be retired.</div><div class='add'>+ */</div><div class='add'>+#define UMC_NPS_SHIFT 40</div><div class='add'>+#define UMC_NPS_MASK 0xffULL</div><div class='add'>+</div><div class='add'>+/* three column bits and one row bit in MCA address flip</div><div class='add'>+ * in bad page retirement</div><div class='add'>+ */</div><div class='add'>+#define RETIRE_FLIP_BITS_NUM 4</div><div class='add'>+</div><div class='add'>+struct amdgpu_umc_flip_bits {</div><div class='add'>+	uint32_t flip_bits_in_pa[RETIRE_FLIP_BITS_NUM];</div><div class='add'>+	uint32_t flip_row_bit;</div><div class='add'>+	uint32_t r13_in_pa;</div><div class='add'>+	uint32_t bit_num;</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,</div><div class='ctx'> 			uint32_t umc_inst, uint32_t ch_inst, void *data);</div><div class='hunk'>@@ -66,8 +103,18 @@ struct amdgpu_umc_ras {</div><div class='ctx'> 					void *ras_error_status);</div><div class='ctx'> 	bool (*check_ecc_err_status)(struct amdgpu_device *adev,</div><div class='ctx'> 			enum amdgpu_mca_error_type type, void *ras_error_status);</div><div class='del'>-	/* support different eeprom table version for different asic */</div><div class='del'>-	void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr);</div><div class='add'>+	int (*update_ecc_status)(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t status, uint64_t ipid, uint64_t addr);</div><div class='add'>+	int (*convert_ras_err_addr)(struct amdgpu_device *adev,</div><div class='add'>+			struct ras_err_data *err_data,</div><div class='add'>+			struct ta_ras_query_address_input *addr_in,</div><div class='add'>+			struct ta_ras_query_address_output *addr_out,</div><div class='add'>+			bool dump_addr);</div><div class='add'>+	uint32_t (*get_die_id_from_pa)(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t mca_addr, uint64_t retired_page);</div><div class='add'>+	void (*get_retire_flip_bits)(struct amdgpu_device *adev);</div><div class='add'>+	void (*mca_ipid_parse)(struct amdgpu_device *adev, uint64_t ipid,</div><div class='add'>+			uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_umc_funcs {</div><div class='hunk'>@@ -98,16 +145,23 @@ struct amdgpu_umc {</div><div class='ctx'> </div><div class='ctx'> 	/* active mask for umc node instance */</div><div class='ctx'> 	unsigned long active_mask;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_umc_flip_bits flip_bits;</div><div class='add'>+</div><div class='add'>+	unsigned long err_addr_cnt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);</div><div class='ctx'> int amdgpu_umc_poison_handler(struct amdgpu_device *adev,</div><div class='del'>-			enum amdgpu_ras_block block, bool reset);</div><div class='add'>+			enum amdgpu_ras_block block, uint32_t reset);</div><div class='add'>+int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev,</div><div class='add'>+			enum amdgpu_ras_block block, uint16_t pasid,</div><div class='add'>+			pasid_notify pasid_fn, void *data, uint32_t reset);</div><div class='ctx'> int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,</div><div class='ctx'> 		struct amdgpu_irq_src *source,</div><div class='ctx'> 		struct amdgpu_iv_entry *entry);</div><div class='del'>-void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,</div><div class='add'>+int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,</div><div class='ctx'> 		uint64_t err_addr,</div><div class='ctx'> 		uint64_t retired_page,</div><div class='ctx'> 		uint32_t channel_index,</div><div class='hunk'>@@ -122,6 +176,21 @@ int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_umc_loop_channels(struct amdgpu_device *adev,</div><div class='ctx'> 			umc_func func, void *data);</div><div class='ctx'> </div><div class='del'>-int amdgpu_umc_bad_page_polling_timeout(struct amdgpu_device *adev,</div><div class='del'>-			bool reset, uint32_t timeout_ms);</div><div class='add'>+int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev,</div><div class='add'>+				uint64_t status, uint64_t ipid, uint64_t addr);</div><div class='add'>+int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev,</div><div class='add'>+		struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err);</div><div class='add'>+</div><div class='add'>+void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,</div><div class='add'>+			void *ras_error_status);</div><div class='add'>+int amdgpu_umc_pages_in_a_row(struct amdgpu_device *adev,</div><div class='add'>+			struct ras_err_data *err_data, uint64_t pa_addr);</div><div class='add'>+int amdgpu_umc_lookup_bad_pages_in_a_row(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t pa_addr, uint64_t *pfns, int len);</div><div class='add'>+int amdgpu_umc_mca_to_addr(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t err_addr, uint32_t ch, uint32_t umc,</div><div class='add'>+			uint32_t node, uint32_t socket,</div><div class='add'>+			struct ta_ras_query_address_output *addr_out, bool dump_addr);</div><div class='add'>+int amdgpu_umc_pa2mca(struct amdgpu_device *adev,</div><div class='add'>+		uint64_t pa, uint64_t *mca, enum amdgpu_memory_partition nps);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c<br/>index ab820cf52668..cd707d70a0bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c</a></div><div class='hunk'>@@ -23,462 +23,16 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_umsch_mm.h"</div><div class='ctx'> #include "umsch_mm_v4_0.h"</div><div class='ctx'> </div><div class='del'>-struct umsch_mm_test_ctx_data {</div><div class='del'>-	uint8_t process_csa[PAGE_SIZE];</div><div class='del'>-	uint8_t vpe_ctx_csa[PAGE_SIZE];</div><div class='del'>-	uint8_t vcn_ctx_csa[PAGE_SIZE];</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct umsch_mm_test_mqd_data {</div><div class='del'>-	uint8_t vpe_mqd[PAGE_SIZE];</div><div class='del'>-	uint8_t vcn_mqd[PAGE_SIZE];</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct umsch_mm_test_ring_data {</div><div class='del'>-	uint8_t vpe_ring[PAGE_SIZE];</div><div class='del'>-	uint8_t vpe_ib[PAGE_SIZE];</div><div class='del'>-	uint8_t vcn_ring[PAGE_SIZE];</div><div class='del'>-	uint8_t vcn_ib[PAGE_SIZE];</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct umsch_mm_test_queue_info {</div><div class='del'>-	uint64_t mqd_addr;</div><div class='del'>-	uint64_t csa_addr;</div><div class='del'>-	uint32_t doorbell_offset_0;</div><div class='del'>-	uint32_t doorbell_offset_1;</div><div class='del'>-	enum UMSCH_SWIP_ENGINE_TYPE engine;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct umsch_mm_test {</div><div class='del'>-	struct amdgpu_bo	*ctx_data_obj;</div><div class='del'>-	uint64_t		ctx_data_gpu_addr;</div><div class='del'>-	uint32_t		*ctx_data_cpu_addr;</div><div class='del'>-</div><div class='del'>-	struct amdgpu_bo	*mqd_data_obj;</div><div class='del'>-	uint64_t		mqd_data_gpu_addr;</div><div class='del'>-	uint32_t		*mqd_data_cpu_addr;</div><div class='del'>-</div><div class='del'>-	struct amdgpu_bo	*ring_data_obj;</div><div class='del'>-	uint64_t		ring_data_gpu_addr;</div><div class='del'>-	uint32_t		*ring_data_cpu_addr;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	struct amdgpu_vm	*vm;</div><div class='del'>-	struct amdgpu_bo_va	*bo_va;</div><div class='del'>-	uint32_t		pasid;</div><div class='del'>-	uint32_t		vm_cntx_cntl;</div><div class='del'>-	uint32_t		num_queues;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-			  struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,</div><div class='del'>-			  uint64_t addr, uint32_t size)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_sync sync;</div><div class='del'>-	struct drm_exec exec;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_create(&amp;sync);</div><div class='del'>-</div><div class='del'>-	drm_exec_init(&amp;exec, 0, 0);</div><div class='del'>-	drm_exec_until_all_locked(&amp;exec) {</div><div class='del'>-		r = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;tbo.base);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto error_fini_exec;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto error_fini_exec;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	*bo_va = amdgpu_vm_bo_add(adev, vm, bo);</div><div class='del'>-	if (!*bo_va) {</div><div class='del'>-		r = -ENOMEM;</div><div class='del'>-		goto error_fini_exec;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_bo_map(adev, *bo_va, addr, 0, size,</div><div class='del'>-			     AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |</div><div class='del'>-			     AMDGPU_PTE_EXECUTABLE);</div><div class='del'>-</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_del_bo_va;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_bo_update(adev, *bo_va, false);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_del_bo_va;</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_fence(&amp;sync, (*bo_va)-&gt;last_pt_update);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_update_pdes(adev, vm, false);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_del_bo_va;</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_fence(&amp;sync, vm-&gt;last_update);</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_wait(&amp;sync, false);</div><div class='del'>-	drm_exec_fini(&amp;exec);</div><div class='del'>-</div><div class='del'>-	amdgpu_sync_free(&amp;sync);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-error_del_bo_va:</div><div class='del'>-	amdgpu_vm_bo_del(adev, *bo_va);</div><div class='del'>-	amdgpu_sync_free(&amp;sync);</div><div class='del'>-</div><div class='del'>-error_fini_exec:</div><div class='del'>-	drm_exec_fini(&amp;exec);</div><div class='del'>-	amdgpu_sync_free(&amp;sync);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int unmap_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-			    struct amdgpu_bo *bo, struct amdgpu_bo_va *bo_va,</div><div class='del'>-			    uint64_t addr)</div><div class='del'>-{</div><div class='del'>-	struct drm_exec exec;</div><div class='del'>-	long r;</div><div class='del'>-</div><div class='del'>-	drm_exec_init(&amp;exec, 0, 0);</div><div class='del'>-	drm_exec_until_all_locked(&amp;exec) {</div><div class='del'>-		r = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;tbo.base);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto out_unlock;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='del'>-		drm_exec_retry_on_contention(&amp;exec);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			goto out_unlock;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_bo_unmap(adev, bo_va, addr);</div><div class='del'>-	if (r)</div><div class='del'>-		goto out_unlock;</div><div class='del'>-</div><div class='del'>-	amdgpu_vm_bo_del(adev, bo_va);</div><div class='del'>-</div><div class='del'>-out_unlock:</div><div class='del'>-	drm_exec_fini(&amp;exec);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void setup_vpe_queue(struct amdgpu_device *adev,</div><div class='del'>-			    struct umsch_mm_test *test,</div><div class='del'>-			    struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-	struct MQD_INFO *mqd = (struct MQD_INFO *)test-&gt;mqd_data_cpu_addr;</div><div class='del'>-	uint64_t ring_gpu_addr = test-&gt;ring_data_gpu_addr;</div><div class='del'>-</div><div class='del'>-	mqd-&gt;rb_base_lo = (ring_gpu_addr &gt;&gt; 8);</div><div class='del'>-	mqd-&gt;rb_base_hi = (ring_gpu_addr &gt;&gt; 40);</div><div class='del'>-	mqd-&gt;rb_size = PAGE_SIZE / 4;</div><div class='del'>-	mqd-&gt;wptr_val = 0;</div><div class='del'>-	mqd-&gt;rptr_val = 0;</div><div class='del'>-	mqd-&gt;unmapped = 1;</div><div class='del'>-</div><div class='del'>-	qinfo-&gt;mqd_addr = test-&gt;mqd_data_gpu_addr;</div><div class='del'>-	qinfo-&gt;csa_addr = test-&gt;ctx_data_gpu_addr +</div><div class='del'>-		offsetof(struct umsch_mm_test_ctx_data, vpe_ctx_csa);</div><div class='del'>-	qinfo-&gt;doorbell_offset_0 = (adev-&gt;doorbell_index.vpe_ring + 1) &lt;&lt; 1;</div><div class='del'>-	qinfo-&gt;doorbell_offset_1 = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void setup_vcn_queue(struct amdgpu_device *adev,</div><div class='del'>-			    struct umsch_mm_test *test,</div><div class='del'>-			    struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int add_test_queue(struct amdgpu_device *adev,</div><div class='del'>-			  struct umsch_mm_test *test,</div><div class='del'>-			  struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-	struct umsch_mm_add_queue_input queue_input = {};</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	queue_input.process_id = test-&gt;pasid;</div><div class='del'>-	queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(test-&gt;vm-&gt;root.bo);</div><div class='del'>-</div><div class='del'>-	queue_input.process_va_start = 0;</div><div class='del'>-	queue_input.process_va_end = (adev-&gt;vm_manager.max_pfn - 1) &lt;&lt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='del'>-</div><div class='del'>-	queue_input.process_quantum = 100000; /* 10ms */</div><div class='del'>-	queue_input.process_csa_addr = test-&gt;ctx_data_gpu_addr +</div><div class='del'>-				       offsetof(struct umsch_mm_test_ctx_data, process_csa);</div><div class='del'>-</div><div class='del'>-	queue_input.context_quantum = 10000; /* 1ms */</div><div class='del'>-	queue_input.context_csa_addr = qinfo-&gt;csa_addr;</div><div class='del'>-</div><div class='del'>-	queue_input.inprocess_context_priority = CONTEXT_PRIORITY_LEVEL_NORMAL;</div><div class='del'>-	queue_input.context_global_priority_level = CONTEXT_PRIORITY_LEVEL_NORMAL;</div><div class='del'>-	queue_input.doorbell_offset_0 = qinfo-&gt;doorbell_offset_0;</div><div class='del'>-	queue_input.doorbell_offset_1 = qinfo-&gt;doorbell_offset_1;</div><div class='del'>-</div><div class='del'>-	queue_input.engine_type = qinfo-&gt;engine;</div><div class='del'>-	queue_input.mqd_addr = qinfo-&gt;mqd_addr;</div><div class='del'>-	queue_input.vm_context_cntl = test-&gt;vm_cntx_cntl;</div><div class='del'>-</div><div class='del'>-	amdgpu_umsch_mm_lock(&amp;adev-&gt;umsch_mm);</div><div class='del'>-	r = adev-&gt;umsch_mm.funcs-&gt;add_queue(&amp;adev-&gt;umsch_mm, &amp;queue_input);</div><div class='del'>-	amdgpu_umsch_mm_unlock(&amp;adev-&gt;umsch_mm);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int remove_test_queue(struct amdgpu_device *adev,</div><div class='del'>-			     struct umsch_mm_test *test,</div><div class='del'>-			     struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-	struct umsch_mm_remove_queue_input queue_input = {};</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	queue_input.doorbell_offset_0 = qinfo-&gt;doorbell_offset_0;</div><div class='del'>-	queue_input.doorbell_offset_1 = qinfo-&gt;doorbell_offset_1;</div><div class='del'>-	queue_input.context_csa_addr = qinfo-&gt;csa_addr;</div><div class='del'>-</div><div class='del'>-	amdgpu_umsch_mm_lock(&amp;adev-&gt;umsch_mm);</div><div class='del'>-	r = adev-&gt;umsch_mm.funcs-&gt;remove_queue(&amp;adev-&gt;umsch_mm, &amp;queue_input);</div><div class='del'>-	amdgpu_umsch_mm_unlock(&amp;adev-&gt;umsch_mm);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int submit_vpe_queue(struct amdgpu_device *adev, struct umsch_mm_test *test)</div><div class='del'>-{</div><div class='del'>-	struct MQD_INFO *mqd = (struct MQD_INFO *)test-&gt;mqd_data_cpu_addr;</div><div class='del'>-	uint32_t *ring = test-&gt;ring_data_cpu_addr +</div><div class='del'>-		offsetof(struct umsch_mm_test_ring_data, vpe_ring) / 4;</div><div class='del'>-	uint32_t *ib = test-&gt;ring_data_cpu_addr +</div><div class='del'>-		offsetof(struct umsch_mm_test_ring_data, vpe_ib) / 4;</div><div class='del'>-	uint64_t ib_gpu_addr = test-&gt;ring_data_gpu_addr +</div><div class='del'>-		offsetof(struct umsch_mm_test_ring_data, vpe_ib);</div><div class='del'>-	uint32_t *fence = ib + 2048 / 4;</div><div class='del'>-	uint64_t fence_gpu_addr = ib_gpu_addr + 2048;</div><div class='del'>-	const uint32_t test_pattern = 0xdeadbeef;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	ib[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);</div><div class='del'>-	ib[1] = lower_32_bits(fence_gpu_addr);</div><div class='del'>-	ib[2] = upper_32_bits(fence_gpu_addr);</div><div class='del'>-	ib[3] = test_pattern;</div><div class='del'>-</div><div class='del'>-	ring[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0);</div><div class='del'>-	ring[1] = (ib_gpu_addr &amp; 0xffffffe0);</div><div class='del'>-	ring[2] = upper_32_bits(ib_gpu_addr);</div><div class='del'>-	ring[3] = 4;</div><div class='del'>-	ring[4] = 0;</div><div class='del'>-	ring[5] = 0;</div><div class='del'>-</div><div class='del'>-	mqd-&gt;wptr_val = (6 &lt;&lt; 2);</div><div class='del'>-	// WDOORBELL32(adev-&gt;umsch_mm.agdb_index[CONTEXT_PRIORITY_LEVEL_NORMAL], mqd-&gt;wptr_val);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (*fence == test_pattern)</div><div class='del'>-			return 0;</div><div class='del'>-		udelay(1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dev_err(adev-&gt;dev, "vpe queue submission timeout\n");</div><div class='del'>-</div><div class='del'>-	return -ETIMEDOUT;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int submit_vcn_queue(struct amdgpu_device *adev, struct umsch_mm_test *test)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int setup_umsch_mm_test(struct amdgpu_device *adev,</div><div class='del'>-			  struct umsch_mm_test *test)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	test-&gt;vm_cntx_cntl = hub-&gt;vm_cntx_cntl;</div><div class='del'>-</div><div class='del'>-	test-&gt;vm = kzalloc(sizeof(*test-&gt;vm), GFP_KERNEL);</div><div class='del'>-	if (!test-&gt;vm) {</div><div class='del'>-		r = -ENOMEM;</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vm_init(adev, test-&gt;vm, -1);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_free_vm;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_pasid_alloc(16);</div><div class='del'>-	if (r &lt; 0)</div><div class='del'>-		goto error_fini_vm;</div><div class='del'>-	test-&gt;pasid = r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, sizeof(struct umsch_mm_test_ctx_data),</div><div class='del'>-				    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;test-&gt;ctx_data_obj,</div><div class='del'>-				    &amp;test-&gt;ctx_data_gpu_addr,</div><div class='del'>-				    (void **)&amp;test-&gt;ctx_data_cpu_addr);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_free_pasid;</div><div class='del'>-</div><div class='del'>-	memset(test-&gt;ctx_data_cpu_addr, 0, sizeof(struct umsch_mm_test_ctx_data));</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE,</div><div class='del'>-				    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;test-&gt;mqd_data_obj,</div><div class='del'>-				    &amp;test-&gt;mqd_data_gpu_addr,</div><div class='del'>-				    (void **)&amp;test-&gt;mqd_data_cpu_addr);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_free_ctx_data_obj;</div><div class='del'>-</div><div class='del'>-	memset(test-&gt;mqd_data_cpu_addr, 0, PAGE_SIZE);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, sizeof(struct umsch_mm_test_ring_data),</div><div class='del'>-				    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				    &amp;test-&gt;ring_data_obj,</div><div class='del'>-				    NULL,</div><div class='del'>-				    (void **)&amp;test-&gt;ring_data_cpu_addr);</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_free_mqd_data_obj;</div><div class='del'>-</div><div class='del'>-	memset(test-&gt;ring_data_cpu_addr, 0, sizeof(struct umsch_mm_test_ring_data));</div><div class='del'>-</div><div class='del'>-	test-&gt;ring_data_gpu_addr = AMDGPU_VA_RESERVED_BOTTOM;</div><div class='del'>-	r = map_ring_data(adev, test-&gt;vm, test-&gt;ring_data_obj, &amp;test-&gt;bo_va,</div><div class='del'>-			  test-&gt;ring_data_gpu_addr, sizeof(struct umsch_mm_test_ring_data));</div><div class='del'>-	if (r)</div><div class='del'>-		goto error_free_ring_data_obj;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-error_free_ring_data_obj:</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;test-&gt;ring_data_obj, NULL,</div><div class='del'>-			      (void **)&amp;test-&gt;ring_data_cpu_addr);</div><div class='del'>-error_free_mqd_data_obj:</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;test-&gt;mqd_data_obj, &amp;test-&gt;mqd_data_gpu_addr,</div><div class='del'>-			      (void **)&amp;test-&gt;mqd_data_cpu_addr);</div><div class='del'>-error_free_ctx_data_obj:</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;test-&gt;ctx_data_obj, &amp;test-&gt;ctx_data_gpu_addr,</div><div class='del'>-			      (void **)&amp;test-&gt;ctx_data_cpu_addr);</div><div class='del'>-error_free_pasid:</div><div class='del'>-	amdgpu_pasid_free(test-&gt;pasid);</div><div class='del'>-error_fini_vm:</div><div class='del'>-	amdgpu_vm_fini(adev, test-&gt;vm);</div><div class='del'>-error_free_vm:</div><div class='del'>-	kfree(test-&gt;vm);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void cleanup_umsch_mm_test(struct amdgpu_device *adev,</div><div class='del'>-				  struct umsch_mm_test *test)</div><div class='del'>-{</div><div class='del'>-	unmap_ring_data(adev, test-&gt;vm, test-&gt;ring_data_obj,</div><div class='del'>-			test-&gt;bo_va, test-&gt;ring_data_gpu_addr);</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;test-&gt;mqd_data_obj, &amp;test-&gt;mqd_data_gpu_addr,</div><div class='del'>-			      (void **)&amp;test-&gt;mqd_data_cpu_addr);</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;test-&gt;ring_data_obj, NULL,</div><div class='del'>-			      (void **)&amp;test-&gt;ring_data_cpu_addr);</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;test-&gt;ctx_data_obj, &amp;test-&gt;ctx_data_gpu_addr,</div><div class='del'>-			       (void **)&amp;test-&gt;ctx_data_cpu_addr);</div><div class='del'>-	amdgpu_pasid_free(test-&gt;pasid);</div><div class='del'>-	amdgpu_vm_fini(adev, test-&gt;vm);</div><div class='del'>-	kfree(test-&gt;vm);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int setup_test_queues(struct amdgpu_device *adev,</div><div class='del'>-			     struct umsch_mm_test *test,</div><div class='del'>-			     struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-	int i, r;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; test-&gt;num_queues; i++) {</div><div class='del'>-		if (qinfo[i].engine == UMSCH_SWIP_ENGINE_TYPE_VPE)</div><div class='del'>-			setup_vpe_queue(adev, test, &amp;qinfo[i]);</div><div class='del'>-		else</div><div class='del'>-			setup_vcn_queue(adev, test, &amp;qinfo[i]);</div><div class='del'>-</div><div class='del'>-		r = add_test_queue(adev, test, &amp;qinfo[i]);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int submit_test_queues(struct amdgpu_device *adev,</div><div class='del'>-			      struct umsch_mm_test *test,</div><div class='del'>-			      struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-	int i, r;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; test-&gt;num_queues; i++) {</div><div class='del'>-		if (qinfo[i].engine == UMSCH_SWIP_ENGINE_TYPE_VPE)</div><div class='del'>-			r = submit_vpe_queue(adev, test);</div><div class='del'>-		else</div><div class='del'>-			r = submit_vcn_queue(adev, test);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void cleanup_test_queues(struct amdgpu_device *adev,</div><div class='del'>-			      struct umsch_mm_test *test,</div><div class='del'>-			      struct umsch_mm_test_queue_info *qinfo)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; test-&gt;num_queues; i++)</div><div class='del'>-		remove_test_queue(adev, test, &amp;qinfo[i]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int umsch_mm_test(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct umsch_mm_test_queue_info qinfo[] = {</div><div class='del'>-		{ .engine = UMSCH_SWIP_ENGINE_TYPE_VPE },</div><div class='del'>-	};</div><div class='del'>-	struct umsch_mm_test test = { .num_queues = ARRAY_SIZE(qinfo) };</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	r = setup_umsch_mm_test(adev, &amp;test);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = setup_test_queues(adev, &amp;test, qinfo);</div><div class='del'>-	if (r)</div><div class='del'>-		goto cleanup;</div><div class='del'>-</div><div class='del'>-	r = submit_test_queues(adev, &amp;test, qinfo);</div><div class='del'>-	if (r)</div><div class='del'>-		goto cleanup;</div><div class='del'>-</div><div class='del'>-	cleanup_test_queues(adev, &amp;test, qinfo);</div><div class='del'>-	cleanup_umsch_mm_test(adev, &amp;test);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-cleanup:</div><div class='del'>-	cleanup_test_queues(adev, &amp;test, qinfo);</div><div class='del'>-	cleanup_umsch_mm_test(adev, &amp;test);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='add'>+MODULE_FIRMWARE("amdgpu/umsch_mm_4_0_0.bin");</div><div class='ctx'> </div><div class='ctx'> int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws)</div><div class='ctx'> {</div><div class='hunk'>@@ -571,13 +125,15 @@ int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 0, 5):</div><div class='del'>-		fw_name = "amdgpu/umsch_mm_4_0_0.bin";</div><div class='add'>+	case IP_VERSION(4, 0, 6):</div><div class='add'>+		fw_name = "4_0_0";</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		break;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ucode_request(adev, &amp;adev-&gt;umsch_mm.fw, fw_name);</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;umsch_mm.fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				 "amdgpu/umsch_mm_%s.bin", fw_name);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		release_firmware(adev-&gt;umsch_mm.fw);</div><div class='ctx'> 		adev-&gt;umsch_mm.fw = NULL;</div><div class='hunk'>@@ -736,6 +292,17 @@ static int umsch_mm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_bo_create_kernel(adev, AMDGPU_UMSCHFW_LOG_SIZE, PAGE_SIZE,</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_VRAM |</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				    &amp;adev-&gt;umsch_mm.dbglog_bo,</div><div class='add'>+				    &amp;adev-&gt;umsch_mm.log_gpu_addr,</div><div class='add'>+				    &amp;adev-&gt;umsch_mm.log_cpu_addr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to allocate umsch debug bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	mutex_init(&amp;adev-&gt;umsch_mm.mutex_hidden);</div><div class='ctx'> </div><div class='ctx'> 	umsch_mm_agdb_index_init(adev);</div><div class='hunk'>@@ -744,12 +311,13 @@ static int umsch_mm_init(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int umsch_mm_early_init(void *handle)</div><div class='add'>+static int umsch_mm_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 0, 5):</div><div class='add'>+	case IP_VERSION(4, 0, 6):</div><div class='ctx'> 		umsch_mm_v4_0_set_funcs(&amp;adev-&gt;umsch_mm);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -762,22 +330,26 @@ static int umsch_mm_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_late_init(void *handle)</div><div class='add'>+static int umsch_mm_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_in_reset(adev) || adev-&gt;in_s0ix || adev-&gt;in_suspend)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	return umsch_mm_test(adev);</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_sw_init(void *handle)</div><div class='add'>+static int umsch_mm_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = umsch_mm_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_umsch_fwlog_init(&amp;adev-&gt;umsch_mm);</div><div class='ctx'> 	r = umsch_mm_ring_init(&amp;adev-&gt;umsch_mm);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -789,9 +361,9 @@ static int umsch_mm_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_sw_fini(void *handle)</div><div class='add'>+static int umsch_mm_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	release_firmware(adev-&gt;umsch_mm.fw);</div><div class='ctx'> 	adev-&gt;umsch_mm.fw = NULL;</div><div class='hunk'>@@ -804,14 +376,18 @@ static int umsch_mm_sw_fini(void *handle)</div><div class='ctx'> 			      &amp;adev-&gt;umsch_mm.cmd_buf_gpu_addr,</div><div class='ctx'> 			      (void **)&amp;adev-&gt;umsch_mm.cmd_buf_ptr);</div><div class='ctx'> </div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;umsch_mm.dbglog_bo,</div><div class='add'>+				    &amp;adev-&gt;umsch_mm.log_gpu_addr,</div><div class='add'>+				    (void **)&amp;adev-&gt;umsch_mm.log_cpu_addr);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_device_wb_free(adev, adev-&gt;umsch_mm.wb_index);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_hw_init(void *handle)</div><div class='add'>+static int umsch_mm_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = umsch_mm_load_microcode(&amp;adev-&gt;umsch_mm);</div><div class='hunk'>@@ -827,9 +403,9 @@ static int umsch_mm_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_hw_fini(void *handle)</div><div class='add'>+static int umsch_mm_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	umsch_mm_ring_stop(&amp;adev-&gt;umsch_mm);</div><div class='ctx'> </div><div class='hunk'>@@ -843,18 +419,114 @@ static int umsch_mm_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_suspend(void *handle)</div><div class='add'>+static int umsch_mm_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return umsch_mm_hw_fini(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int umsch_mm_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return umsch_mm_hw_init(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	void *fw_log_cpu_addr = umsch_mm-&gt;log_cpu_addr;</div><div class='add'>+	volatile struct amdgpu_umsch_fwlog *log_buf = fw_log_cpu_addr;</div><div class='ctx'> </div><div class='del'>-	return umsch_mm_hw_fini(adev);</div><div class='add'>+	log_buf-&gt;header_size = sizeof(struct amdgpu_umsch_fwlog);</div><div class='add'>+	log_buf-&gt;buffer_size = AMDGPU_UMSCHFW_LOG_SIZE;</div><div class='add'>+	log_buf-&gt;rptr = log_buf-&gt;header_size;</div><div class='add'>+	log_buf-&gt;wptr = log_buf-&gt;header_size;</div><div class='add'>+	log_buf-&gt;wrapped = 0;</div><div class='add'>+#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int umsch_mm_resume(void *handle)</div><div class='add'>+/*</div><div class='add'>+ * debugfs for mapping umsch firmware log buffer.</div><div class='add'>+ */</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static ssize_t amdgpu_debugfs_umsch_fwlog_read(struct file *f, char __user *buf,</div><div class='add'>+					     size_t size, loff_t *pos)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_umsch_mm *umsch_mm;</div><div class='add'>+	void *log_buf;</div><div class='add'>+	volatile struct amdgpu_umsch_fwlog *plog;</div><div class='add'>+	unsigned int read_pos, write_pos, available, i, read_bytes = 0;</div><div class='add'>+	unsigned int read_num[2] = {0};</div><div class='add'>+</div><div class='add'>+	umsch_mm = file_inode(f)-&gt;i_private;</div><div class='add'>+	if (!umsch_mm)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (!umsch_mm-&gt;log_cpu_addr)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	log_buf = umsch_mm-&gt;log_cpu_addr;</div><div class='add'>+</div><div class='add'>+	plog = (volatile struct amdgpu_umsch_fwlog *)log_buf;</div><div class='add'>+	read_pos = plog-&gt;rptr;</div><div class='add'>+	write_pos = plog-&gt;wptr;</div><div class='add'>+</div><div class='add'>+	if (read_pos &gt; AMDGPU_UMSCHFW_LOG_SIZE || write_pos &gt; AMDGPU_UMSCHFW_LOG_SIZE)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (!size || (read_pos == write_pos))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (write_pos &gt; read_pos) {</div><div class='add'>+		available = write_pos - read_pos;</div><div class='add'>+		read_num[0] = min_t(size_t, size, available);</div><div class='add'>+	} else {</div><div class='add'>+		read_num[0] = AMDGPU_UMSCHFW_LOG_SIZE - read_pos;</div><div class='add'>+		available = read_num[0] + write_pos - plog-&gt;header_size;</div><div class='add'>+		if (size &gt; available)</div><div class='add'>+			read_num[1] = write_pos - plog-&gt;header_size;</div><div class='add'>+		else if (size &gt; read_num[0])</div><div class='add'>+			read_num[1] = size - read_num[0];</div><div class='add'>+		else</div><div class='add'>+			read_num[0] = size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 2; i++) {</div><div class='add'>+		if (read_num[i]) {</div><div class='add'>+			if (read_pos == AMDGPU_UMSCHFW_LOG_SIZE)</div><div class='add'>+				read_pos = plog-&gt;header_size;</div><div class='add'>+			if (read_num[i] == copy_to_user((buf + read_bytes),</div><div class='add'>+							(log_buf + read_pos), read_num[i]))</div><div class='add'>+				return -EFAULT;</div><div class='add'>+</div><div class='add'>+			read_bytes += read_num[i];</div><div class='add'>+			read_pos += read_num[i];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	plog-&gt;rptr = read_pos;</div><div class='add'>+	*pos += read_bytes;</div><div class='add'>+	return read_bytes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations amdgpu_debugfs_umschfwlog_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.read = amdgpu_debugfs_umsch_fwlog_read,</div><div class='add'>+	.llseek = default_llseek</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_umsch_fwlog_init(struct amdgpu_device *adev,</div><div class='add'>+			struct amdgpu_umsch_mm *umsch_mm)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	char name[32];</div><div class='ctx'> </div><div class='del'>-	return umsch_mm_hw_init(adev);</div><div class='add'>+	sprintf(name, "amdgpu_umsch_fwlog");</div><div class='add'>+	debugfs_create_file_size(name, S_IFREG | 0444, root, umsch_mm,</div><div class='add'>+				 &amp;amdgpu_debugfs_umschfwlog_fops,</div><div class='add'>+				 AMDGPU_UMSCHFW_LOG_SIZE);</div><div class='add'>+#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h<br/>index 8258a43a6236..2c771a753778 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h</a></div><div class='hunk'>@@ -33,13 +33,6 @@ enum UMSCH_SWIP_ENGINE_TYPE {</div><div class='ctx'> 	UMSCH_SWIP_ENGINE_TYPE_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-enum UMSCH_SWIP_AFFINITY_TYPE {</div><div class='del'>-	UMSCH_SWIP_AFFINITY_TYPE_ANY = 0,</div><div class='del'>-	UMSCH_SWIP_AFFINITY_TYPE_VCN0 = 1,</div><div class='del'>-	UMSCH_SWIP_AFFINITY_TYPE_VCN1 = 2,</div><div class='del'>-	UMSCH_SWIP_AFFINITY_TYPE_MAX</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> enum UMSCH_CONTEXT_PRIORITY_LEVEL {</div><div class='ctx'> 	CONTEXT_PRIORITY_LEVEL_IDLE = 0,</div><div class='ctx'> 	CONTEXT_PRIORITY_LEVEL_NORMAL = 1,</div><div class='hunk'>@@ -51,18 +44,28 @@ enum UMSCH_CONTEXT_PRIORITY_LEVEL {</div><div class='ctx'> struct umsch_mm_set_resource_input {</div><div class='ctx'> 	uint32_t vmid_mask_mm_vcn;</div><div class='ctx'> 	uint32_t vmid_mask_mm_vpe;</div><div class='add'>+	uint32_t collaboration_mask_vpe;</div><div class='ctx'> 	uint32_t logging_vmid;</div><div class='ctx'> 	uint32_t engine_mask;</div><div class='ctx'> 	union {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			uint32_t disable_reset : 1;</div><div class='ctx'> 			uint32_t disable_umsch_mm_log : 1;</div><div class='del'>-			uint32_t reserved : 30;</div><div class='add'>+			uint32_t use_rs64mem_for_proc_ctx_csa : 1;</div><div class='add'>+			uint32_t reserved : 29;</div><div class='ctx'> 		};</div><div class='ctx'> 		uint32_t uint32_all;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_umsch_fwlog {</div><div class='add'>+	uint32_t rptr;</div><div class='add'>+	uint32_t wptr;</div><div class='add'>+	uint32_t buffer_size;</div><div class='add'>+	uint32_t header_size;</div><div class='add'>+	uint32_t wrapped;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct umsch_mm_add_queue_input {</div><div class='ctx'> 	uint32_t process_id;</div><div class='ctx'> 	uint64_t page_table_base_addr;</div><div class='hunk'>@@ -78,15 +81,18 @@ struct umsch_mm_add_queue_input {</div><div class='ctx'> 	uint32_t doorbell_offset_1;</div><div class='ctx'> 	enum UMSCH_SWIP_ENGINE_TYPE engine_type;</div><div class='ctx'> 	uint32_t affinity;</div><div class='del'>-	enum UMSCH_SWIP_AFFINITY_TYPE affinity_type;</div><div class='ctx'> 	uint64_t mqd_addr;</div><div class='ctx'> 	uint64_t h_context;</div><div class='ctx'> 	uint64_t h_queue;</div><div class='ctx'> 	uint32_t vm_context_cntl;</div><div class='ctx'> </div><div class='add'>+	uint32_t process_csa_array_index;</div><div class='add'>+	uint32_t context_csa_array_index;</div><div class='add'>+</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint32_t is_context_suspended : 1;</div><div class='del'>-		uint32_t reserved : 31;</div><div class='add'>+		uint32_t collaboration_mode : 1;</div><div class='add'>+		uint32_t reserved : 30;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -94,6 +100,7 @@ struct umsch_mm_remove_queue_input {</div><div class='ctx'> 	uint32_t doorbell_offset_0;</div><div class='ctx'> 	uint32_t doorbell_offset_1;</div><div class='ctx'> 	uint64_t context_csa_addr;</div><div class='add'>+	uint32_t context_csa_array_index;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct MQD_INFO {</div><div class='hunk'>@@ -103,6 +110,7 @@ struct MQD_INFO {</div><div class='ctx'> 	uint32_t wptr_val;</div><div class='ctx'> 	uint32_t rptr_val;</div><div class='ctx'> 	uint32_t unmapped;</div><div class='add'>+	uint32_t vmid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_umsch_mm;</div><div class='hunk'>@@ -166,6 +174,11 @@ struct amdgpu_umsch_mm {</div><div class='ctx'> 	uint32_t			agdb_index[CONTEXT_PRIORITY_NUM_LEVELS];</div><div class='ctx'> </div><div class='ctx'> 	struct mutex			mutex_hidden;</div><div class='add'>+	struct amdgpu_bo		*dbglog_bo;</div><div class='add'>+	void				*log_cpu_addr;</div><div class='add'>+	uint64_t			log_gpu_addr;</div><div class='add'>+	uint32_t			mem_size;</div><div class='add'>+	uint32_t			log_offset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws);</div><div class='hunk'>@@ -179,6 +192,11 @@ int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch);</div><div class='ctx'> </div><div class='add'>+void amdgpu_debugfs_umsch_fwlog_init(struct amdgpu_device *adev,</div><div class='add'>+			struct amdgpu_umsch_mm *umsch);</div><div class='add'>+</div><div class='add'>+void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm);</div><div class='add'>+</div><div class='ctx'> #define WREG32_SOC15_UMSCH(reg, value)								\</div><div class='ctx'> 	do {											\</div><div class='ctx'> 		uint32_t reg_offset = adev-&gt;reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg;	\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c<br/>new file mode 100644<br/>index 000000000000..9a969175900e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c</a></div><div class='hunk'>@@ -0,0 +1,1482 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_auth.h&gt;</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='add'>+#include "amdgpu_vm.h"</div><div class='add'>+#include "amdgpu_userq.h"</div><div class='add'>+#include "amdgpu_hmm.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='add'>+</div><div class='add'>+u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	u32 userq_ip_mask = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_HW_IP_NUM; i++) {</div><div class='add'>+		if (adev-&gt;userq_funcs[i])</div><div class='add'>+			userq_ip_mask |= (1 &lt;&lt; i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return userq_ip_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_userq_is_reset_type_supported(struct amdgpu_device *adev,</div><div class='add'>+				enum amdgpu_ring_type ring_type, int reset_type)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	if (ring_type &lt; 0 || ring_type &gt;= AMDGPU_RING_TYPE_MAX)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	switch (ring_type) {</div><div class='add'>+	case AMDGPU_RING_TYPE_GFX:</div><div class='add'>+		if (adev-&gt;gfx.gfx_supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='add'>+		if (adev-&gt;gfx.compute_supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_SDMA:</div><div class='add'>+		if (adev-&gt;sdma.supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_DEC:</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_ENC:</div><div class='add'>+		if (adev-&gt;vcn.supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_JPEG:</div><div class='add'>+		if (adev-&gt;jpeg.supported_reset &amp; reset_type)</div><div class='add'>+			return true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_gpu_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_device_should_recover_gpu(adev)) {</div><div class='add'>+		amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='add'>+					     &amp;adev-&gt;userq_reset_work);</div><div class='add'>+		/* Wait for the reset job to complete */</div><div class='add'>+		flush_work(&amp;adev-&gt;userq_reset_work);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const int queue_types[] = {</div><div class='add'>+		AMDGPU_RING_TYPE_COMPUTE,</div><div class='add'>+		AMDGPU_RING_TYPE_GFX,</div><div class='add'>+		AMDGPU_RING_TYPE_SDMA</div><div class='add'>+	};</div><div class='add'>+	const int num_queue_types = ARRAY_SIZE(queue_types);</div><div class='add'>+	bool gpu_reset = false;</div><div class='add'>+	int r = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Warning if current process mutex is not held */</div><div class='add'>+	WARN_ON(!mutex_is_locked(&amp;uq_mgr-&gt;userq_mutex));</div><div class='add'>+</div><div class='add'>+	if (unlikely(adev-&gt;debug_disable_gpu_ring_reset)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "userq reset disabled by debug mask\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If GPU recovery feature is disabled system-wide,</div><div class='add'>+	 * skip all reset detection logic</div><div class='add'>+	 */</div><div class='add'>+	if (!amdgpu_gpu_recovery)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Iterate through all queue types to detect and reset problematic queues</div><div class='add'>+	 * Process each queue type in the defined order</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; num_queue_types; i++) {</div><div class='add'>+		int ring_type = queue_types[i];</div><div class='add'>+		const struct amdgpu_userq_funcs *funcs = adev-&gt;userq_funcs[ring_type];</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, AMDGPU_RESET_TYPE_PER_QUEUE))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+		if (atomic_read(&amp;uq_mgr-&gt;userq_count[ring_type]) &gt; 0 &amp;&amp;</div><div class='add'>+		    funcs &amp;&amp; funcs-&gt;detect_and_reset) {</div><div class='add'>+			r = funcs-&gt;detect_and_reset(adev, ring_type);</div><div class='add'>+			if (r) {</div><div class='add'>+				gpu_reset = true;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gpu_reset)</div><div class='add'>+		amdgpu_userq_gpu_reset(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue,</div><div class='add'>+					   struct amdgpu_bo_va_mapping *va_map, u64 addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_va_cursor *va_cursor;</div><div class='add'>+	struct userq_va_list;</div><div class='add'>+</div><div class='add'>+	va_cursor = kzalloc(sizeof(*va_cursor), GFP_KERNEL);</div><div class='add'>+	if (!va_cursor)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;va_cursor-&gt;list);</div><div class='add'>+	va_cursor-&gt;gpu_addr = addr;</div><div class='add'>+	atomic_set(&amp;va_map-&gt;bo_va-&gt;userq_va_mapped, 1);</div><div class='add'>+	list_add(&amp;va_cursor-&gt;list, &amp;queue-&gt;userq_va_list);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue,</div><div class='add'>+				   u64 addr, u64 expected_size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo_va_mapping *va_map;</div><div class='add'>+	struct amdgpu_vm *vm = queue-&gt;vm;</div><div class='add'>+	u64 user_addr;</div><div class='add'>+	u64 size;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	user_addr = (addr &amp; AMDGPU_GMC_HOLE_MASK) &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+	size = expected_size &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(vm-&gt;root.bo, false);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	va_map = amdgpu_vm_bo_lookup_mapping(vm, user_addr);</div><div class='add'>+	if (!va_map) {</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+	/* Only validate the userq whether resident in the VM mapping range */</div><div class='add'>+	if (user_addr &gt;= va_map-&gt;start  &amp;&amp;</div><div class='add'>+	    va_map-&gt;last - user_addr + 1 &gt;= size) {</div><div class='add'>+		amdgpu_userq_buffer_va_list_add(queue, va_map, user_addr);</div><div class='add'>+		amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = -EINVAL;</div><div class='add'>+out_err:</div><div class='add'>+	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_userq_buffer_va_mapped(struct amdgpu_vm *vm, u64 addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo_va_mapping *mapping;</div><div class='add'>+	bool r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_bo_reserve(vm-&gt;root.bo, false))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);</div><div class='add'>+	if (!IS_ERR_OR_NULL(mapping) &amp;&amp; atomic_read(&amp;mapping-&gt;bo_va-&gt;userq_va_mapped))</div><div class='add'>+		r = true;</div><div class='add'>+	else</div><div class='add'>+		r = false;</div><div class='add'>+	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_userq_buffer_vas_mapped(struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_va_cursor *va_cursor, *tmp;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(va_cursor, tmp, &amp;queue-&gt;userq_va_list, list) {</div><div class='add'>+		r += amdgpu_userq_buffer_va_mapped(queue-&gt;vm, va_cursor-&gt;gpu_addr);</div><div class='add'>+		dev_dbg(queue-&gt;userq_mgr-&gt;adev-&gt;dev,</div><div class='add'>+			"validate the userq mapping:%p va:%llx r:%d\n",</div><div class='add'>+			queue, va_cursor-&gt;gpu_addr, r);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (r != 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_buffer_va_list_del(struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+					    struct amdgpu_userq_va_cursor *va_cursor)</div><div class='add'>+{</div><div class='add'>+	atomic_set(&amp;mapping-&gt;bo_va-&gt;userq_va_mapped, 0);</div><div class='add'>+	list_del(&amp;va_cursor-&gt;list);</div><div class='add'>+	kfree(va_cursor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev,</div><div class='add'>+						struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_va_cursor *va_cursor, *tmp;</div><div class='add'>+	struct amdgpu_bo_va_mapping *mapping;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(queue-&gt;vm-&gt;root.bo, false);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(va_cursor, tmp, &amp;queue-&gt;userq_va_list, list) {</div><div class='add'>+		mapping = amdgpu_vm_bo_lookup_mapping(queue-&gt;vm, va_cursor-&gt;gpu_addr);</div><div class='add'>+		if (!mapping) {</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+		dev_dbg(adev-&gt;dev, "delete the userq:%p va:%llx\n",</div><div class='add'>+			queue, va_cursor-&gt;gpu_addr);</div><div class='add'>+		amdgpu_userq_buffer_va_list_del(mapping, va_cursor);</div><div class='add'>+	}</div><div class='add'>+err:</div><div class='add'>+	amdgpu_bo_unreserve(queue-&gt;vm-&gt;root.bo);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			  struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs =</div><div class='add'>+		adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+	bool found_hung_queue = false;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (queue-&gt;state == AMDGPU_USERQ_STATE_MAPPED) {</div><div class='add'>+		r = userq_funcs-&gt;preempt(uq_mgr, queue);</div><div class='add'>+		if (r) {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+			found_hung_queue = true;</div><div class='add'>+		} else {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_PREEMPTED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (found_hung_queue)</div><div class='add'>+		amdgpu_userq_detect_and_reset_queues(uq_mgr);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_restore_helper(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs =</div><div class='add'>+		adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (queue-&gt;state == AMDGPU_USERQ_STATE_PREEMPTED) {</div><div class='add'>+		r = userq_funcs-&gt;restore(uq_mgr, queue);</div><div class='add'>+		if (r) {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+		} else {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_MAPPED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			  struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs =</div><div class='add'>+		adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+	bool found_hung_queue = false;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if ((queue-&gt;state == AMDGPU_USERQ_STATE_MAPPED) ||</div><div class='add'>+		(queue-&gt;state == AMDGPU_USERQ_STATE_PREEMPTED)) {</div><div class='add'>+		r = userq_funcs-&gt;unmap(uq_mgr, queue);</div><div class='add'>+		if (r) {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+			found_hung_queue = true;</div><div class='add'>+		} else {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_UNMAPPED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (found_hung_queue)</div><div class='add'>+		amdgpu_userq_detect_and_reset_queues(uq_mgr);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_map_helper(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs =</div><div class='add'>+		adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (queue-&gt;state == AMDGPU_USERQ_STATE_UNMAPPED) {</div><div class='add'>+		r = userq_funcs-&gt;map(uq_mgr, queue);</div><div class='add'>+		if (r) {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+			amdgpu_userq_detect_and_reset_queues(uq_mgr);</div><div class='add'>+		} else {</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_MAPPED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_wait_for_last_fence(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				 struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *f = queue-&gt;last_fence;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (f &amp;&amp; !dma_fence_is_signaled(f)) {</div><div class='add'>+		ret = dma_fence_wait_timeout(f, true, MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+		if (ret &lt;= 0) {</div><div class='add'>+			drm_file_err(uq_mgr-&gt;file, "Timed out waiting for fence=%llu:%llu\n",</div><div class='add'>+				     f-&gt;context, f-&gt;seqno);</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+			return -ETIME;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		     struct amdgpu_usermode_queue *queue,</div><div class='add'>+		     int queue_id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const struct amdgpu_userq_funcs *uq_funcs = adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+</div><div class='add'>+	/* Wait for mode-1 reset to complete */</div><div class='add'>+	down_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+</div><div class='add'>+	/* Drop the userq reference. */</div><div class='add'>+	amdgpu_userq_buffer_vas_list_cleanup(adev, queue);</div><div class='add'>+	uq_funcs-&gt;mqd_destroy(uq_mgr, queue);</div><div class='add'>+	amdgpu_userq_fence_driver_free(queue);</div><div class='add'>+	/* Use interrupt-safe locking since IRQ handlers may access these XArrays */</div><div class='add'>+	xa_erase_irq(&amp;uq_mgr-&gt;userq_mgr_xa, (unsigned long)queue_id);</div><div class='add'>+	xa_erase_irq(&amp;adev-&gt;userq_doorbell_xa, queue-&gt;doorbell_index);</div><div class='add'>+	queue-&gt;userq_mgr = NULL;</div><div class='add'>+	list_del(&amp;queue-&gt;userq_va_list);</div><div class='add'>+	kfree(queue);</div><div class='add'>+</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct amdgpu_usermode_queue *</div><div class='add'>+amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid)</div><div class='add'>+{</div><div class='add'>+	return xa_load(&amp;uq_mgr-&gt;userq_mgr_xa, qid);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			     struct amdgpu_eviction_fence_mgr *evf_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_eviction_fence *ev_fence;</div><div class='add'>+</div><div class='add'>+retry:</div><div class='add'>+	/* Flush any pending resume work to create ev_fence */</div><div class='add'>+	flush_delayed_work(&amp;uq_mgr-&gt;resume_work);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+	spin_lock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	ev_fence = evf_mgr-&gt;ev_fence;</div><div class='add'>+	spin_unlock(&amp;evf_mgr-&gt;ev_fence_lock);</div><div class='add'>+	if (!ev_fence || dma_fence_is_signaled(&amp;ev_fence-&gt;base)) {</div><div class='add'>+		mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+		/*</div><div class='add'>+		 * Looks like there was no pending resume work,</div><div class='add'>+		 * add one now to create a valid eviction fence</div><div class='add'>+		 */</div><div class='add'>+		schedule_delayed_work(&amp;uq_mgr-&gt;resume_work, 0);</div><div class='add'>+		goto retry;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			       struct amdgpu_userq_obj *userq_obj,</div><div class='add'>+			       int size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct amdgpu_bo_param bp;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	memset(&amp;bp, 0, sizeof(bp));</div><div class='add'>+	bp.byte_align = PAGE_SIZE;</div><div class='add'>+	bp.domain = AMDGPU_GEM_DOMAIN_GTT;</div><div class='add'>+	bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |</div><div class='add'>+		   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;</div><div class='add'>+	bp.type = ttm_bo_type_kernel;</div><div class='add'>+	bp.size = size;</div><div class='add'>+	bp.resv = NULL;</div><div class='add'>+	bp.bo_ptr_size = sizeof(struct amdgpu_bo);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create(adev, &amp;bp, &amp;userq_obj-&gt;obj);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to allocate BO for userqueue (%d)", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(userq_obj-&gt;obj, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to reserve BO to map (%d)", r);</div><div class='add'>+		goto free_obj;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ttm_alloc_gart(&amp;(userq_obj-&gt;obj)-&gt;tbo);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to alloc GART for userqueue object (%d)", r);</div><div class='add'>+		goto unresv;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_kmap(userq_obj-&gt;obj, &amp;userq_obj-&gt;cpu_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to map BO for userqueue (%d)", r);</div><div class='add'>+		goto unresv;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	userq_obj-&gt;gpu_addr = amdgpu_bo_gpu_offset(userq_obj-&gt;obj);</div><div class='add'>+	amdgpu_bo_unreserve(userq_obj-&gt;obj);</div><div class='add'>+	memset(userq_obj-&gt;cpu_ptr, 0, size);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+unresv:</div><div class='add'>+	amdgpu_bo_unreserve(userq_obj-&gt;obj);</div><div class='add'>+</div><div class='add'>+free_obj:</div><div class='add'>+	amdgpu_bo_unref(&amp;userq_obj-&gt;obj);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				 struct amdgpu_userq_obj *userq_obj)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_kunmap(userq_obj-&gt;obj);</div><div class='add'>+	amdgpu_bo_unref(&amp;userq_obj-&gt;obj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint64_t</div><div class='add'>+amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				struct amdgpu_db_info *db_info,</div><div class='add'>+				struct drm_file *filp)</div><div class='add'>+{</div><div class='add'>+	uint64_t index;</div><div class='add'>+	struct drm_gem_object *gobj;</div><div class='add'>+	struct amdgpu_userq_obj *db_obj = db_info-&gt;db_obj;</div><div class='add'>+	int r, db_size;</div><div class='add'>+</div><div class='add'>+	gobj = drm_gem_object_lookup(filp, db_info-&gt;doorbell_handle);</div><div class='add'>+	if (gobj == NULL) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Can't find GEM object for doorbell\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	db_obj-&gt;obj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));</div><div class='add'>+	drm_gem_object_put(gobj);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(db_obj-&gt;obj, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "[Usermode queues] Failed to pin doorbell object\n");</div><div class='add'>+		goto unref_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Pin the BO before generating the index, unpin in queue destroy */</div><div class='add'>+	r = amdgpu_bo_pin(db_obj-&gt;obj, AMDGPU_GEM_DOMAIN_DOORBELL);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "[Usermode queues] Failed to pin doorbell object\n");</div><div class='add'>+		goto unresv_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (db_info-&gt;queue_type) {</div><div class='add'>+	case AMDGPU_HW_IP_GFX:</div><div class='add'>+	case AMDGPU_HW_IP_COMPUTE:</div><div class='add'>+	case AMDGPU_HW_IP_DMA:</div><div class='add'>+		db_size = sizeof(u64);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "[Usermode queues] IP %d not support\n",</div><div class='add'>+			     db_info-&gt;queue_type);</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto unpin_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	index = amdgpu_doorbell_index_on_bar(uq_mgr-&gt;adev, db_obj-&gt;obj,</div><div class='add'>+					     db_info-&gt;doorbell_offset, db_size);</div><div class='add'>+	drm_dbg_driver(adev_to_drm(uq_mgr-&gt;adev),</div><div class='add'>+		       "[Usermode queues] doorbell index=%lld\n", index);</div><div class='add'>+	amdgpu_bo_unreserve(db_obj-&gt;obj);</div><div class='add'>+	return index;</div><div class='add'>+</div><div class='add'>+unpin_bo:</div><div class='add'>+	amdgpu_bo_unpin(db_obj-&gt;obj);</div><div class='add'>+unresv_bo:</div><div class='add'>+	amdgpu_bo_unreserve(db_obj-&gt;obj);</div><div class='add'>+unref_bo:</div><div class='add'>+	amdgpu_bo_unref(&amp;db_obj-&gt;obj);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_destroy(struct drm_file *filp, int queue_id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='add'>+	struct amdgpu_userq_mgr *uq_mgr = &amp;fpriv-&gt;userq_mgr;</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;uq_mgr-&gt;resume_work);</div><div class='add'>+	mutex_lock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+</div><div class='add'>+	queue = amdgpu_userq_find(uq_mgr, queue_id);</div><div class='add'>+	if (!queue) {</div><div class='add'>+		drm_dbg_driver(adev_to_drm(uq_mgr-&gt;adev), "Invalid queue id to destroy\n");</div><div class='add'>+		mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	amdgpu_userq_wait_for_last_fence(uq_mgr, queue);</div><div class='add'>+	r = amdgpu_bo_reserve(queue-&gt;db_obj.obj, true);</div><div class='add'>+	if (!r) {</div><div class='add'>+		amdgpu_bo_unpin(queue-&gt;db_obj.obj);</div><div class='add'>+		amdgpu_bo_unreserve(queue-&gt;db_obj.obj);</div><div class='add'>+	}</div><div class='add'>+	amdgpu_bo_unref(&amp;queue-&gt;db_obj.obj);</div><div class='add'>+	atomic_dec(&amp;uq_mgr-&gt;userq_count[queue-&gt;queue_type]);</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	debugfs_remove_recursive(queue-&gt;debugfs_queue);</div><div class='add'>+#endif</div><div class='add'>+	amdgpu_userq_detect_and_reset_queues(uq_mgr);</div><div class='add'>+	r = amdgpu_userq_unmap_helper(uq_mgr, queue);</div><div class='add'>+	/*TODO: It requires a reset for userq hw unmap error*/</div><div class='add'>+	if (unlikely(r != AMDGPU_USERQ_STATE_UNMAPPED)) {</div><div class='add'>+		drm_warn(adev_to_drm(uq_mgr-&gt;adev), "trying to destroy a HW mapping userq\n");</div><div class='add'>+		queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+	}</div><div class='add'>+	amdgpu_userq_cleanup(uq_mgr, queue, queue_id);</div><div class='add'>+	mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_priority_permit(struct drm_file *filp,</div><div class='add'>+					int priority)</div><div class='add'>+{</div><div class='add'>+	if (priority &lt; AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (capable(CAP_SYS_NICE))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (drm_is_current_master(filp))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return -EACCES;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int amdgpu_mqd_info_read(struct seq_file *m, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_usermode_queue *queue = m-&gt;private;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!queue || !queue-&gt;mqd.obj)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	bo = amdgpu_bo_ref(queue-&gt;mqd.obj);</div><div class='add'>+	r = amdgpu_bo_reserve(bo, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		amdgpu_bo_unref(&amp;bo);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	seq_printf(m, "queue_type: %d\n", queue-&gt;queue_type);</div><div class='add'>+	seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue-&gt;mqd.obj));</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(bo);</div><div class='add'>+	amdgpu_bo_unref(&amp;bo);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_mqd_info_open(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	return single_open(file, amdgpu_mqd_info_read, inode-&gt;i_private);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations amdgpu_mqd_info_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = amdgpu_mqd_info_open,</div><div class='add'>+	.read = seq_read,</div><div class='add'>+	.llseek = seq_lseek,</div><div class='add'>+	.release = single_release,</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='add'>+	struct amdgpu_userq_mgr *uq_mgr = &amp;fpriv-&gt;userq_mgr;</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	const struct amdgpu_userq_funcs *uq_funcs;</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_db_info db_info;</div><div class='add'>+	char *queue_name;</div><div class='add'>+	bool skip_map_queue;</div><div class='add'>+	u32 qid;</div><div class='add'>+	uint64_t index;</div><div class='add'>+	int r = 0;</div><div class='add'>+	int priority =</div><div class='add'>+		(args-&gt;in.flags &amp; AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK) &gt;&gt;</div><div class='add'>+		AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_userq_priority_permit(filp, priority);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+	if (r &lt; 0) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "pm_runtime_get_sync() failed for userqueue create\n");</div><div class='add'>+		pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * There could be a situation that we are creating a new queue while</div><div class='add'>+	 * the other queues under this UQ_mgr are suspended. So if there is any</div><div class='add'>+	 * resume work pending, wait for it to get done.</div><div class='add'>+	 *</div><div class='add'>+	 * This will also make sure we have a valid eviction fence ready to be used.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_userq_ensure_ev_fence(&amp;fpriv-&gt;userq_mgr, &amp;fpriv-&gt;evf_mgr);</div><div class='add'>+</div><div class='add'>+	uq_funcs = adev-&gt;userq_funcs[args-&gt;in.ip_type];</div><div class='add'>+	if (!uq_funcs) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Usermode queue is not supported for this IP (%u)\n",</div><div class='add'>+			     args-&gt;in.ip_type);</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue = kzalloc(sizeof(struct amdgpu_usermode_queue), GFP_KERNEL);</div><div class='add'>+	if (!queue) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to allocate memory for queue\n");</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;queue-&gt;userq_va_list);</div><div class='add'>+	queue-&gt;doorbell_handle = args-&gt;in.doorbell_handle;</div><div class='add'>+	queue-&gt;queue_type = args-&gt;in.ip_type;</div><div class='add'>+	queue-&gt;vm = &amp;fpriv-&gt;vm;</div><div class='add'>+	queue-&gt;priority = priority;</div><div class='add'>+</div><div class='add'>+	db_info.queue_type = queue-&gt;queue_type;</div><div class='add'>+	db_info.doorbell_handle = queue-&gt;doorbell_handle;</div><div class='add'>+	db_info.db_obj = &amp;queue-&gt;db_obj;</div><div class='add'>+	db_info.doorbell_offset = args-&gt;in.doorbell_offset;</div><div class='add'>+</div><div class='add'>+	/* Validate the userq virtual address.*/</div><div class='add'>+	if (amdgpu_userq_input_va_validate(queue, args-&gt;in.queue_va, args-&gt;in.queue_size) ||</div><div class='add'>+	    amdgpu_userq_input_va_validate(queue, args-&gt;in.rptr_va, AMDGPU_GPU_PAGE_SIZE) ||</div><div class='add'>+	    amdgpu_userq_input_va_validate(queue, args-&gt;in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) {</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		kfree(queue);</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Convert relative doorbell offset into absolute doorbell index */</div><div class='add'>+	index = amdgpu_userq_get_doorbell_index(uq_mgr, &amp;db_info, filp);</div><div class='add'>+	if (index == (uint64_t)-EINVAL) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to get doorbell for queue\n");</div><div class='add'>+		kfree(queue);</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue-&gt;doorbell_index = index;</div><div class='add'>+	xa_init_flags(&amp;queue-&gt;fence_drv_xa, XA_FLAGS_ALLOC);</div><div class='add'>+	r = amdgpu_userq_fence_driver_alloc(adev, queue);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to alloc fence driver\n");</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = uq_funcs-&gt;mqd_create(uq_mgr, &amp;args-&gt;in, queue);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to create Queue\n");</div><div class='add'>+		amdgpu_userq_fence_driver_free(queue);</div><div class='add'>+		kfree(queue);</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for mode-1 reset to complete */</div><div class='add'>+	down_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	r = xa_err(xa_store_irq(&amp;adev-&gt;userq_doorbell_xa, index, queue, GFP_KERNEL));</div><div class='add'>+	if (r) {</div><div class='add'>+		kfree(queue);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = xa_alloc(&amp;uq_mgr-&gt;userq_mgr_xa, &amp;qid, queue, XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to allocate a queue id\n");</div><div class='add'>+		amdgpu_userq_fence_driver_free(queue);</div><div class='add'>+		uq_funcs-&gt;mqd_destroy(uq_mgr, queue);</div><div class='add'>+		kfree(queue);</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	queue-&gt;userq_mgr = uq_mgr;</div><div class='add'>+</div><div class='add'>+	/* don't map the queue if scheduling is halted */</div><div class='add'>+	if (adev-&gt;userq_halt_for_enforce_isolation &amp;&amp;</div><div class='add'>+	    ((queue-&gt;queue_type == AMDGPU_HW_IP_GFX) ||</div><div class='add'>+	     (queue-&gt;queue_type == AMDGPU_HW_IP_COMPUTE)))</div><div class='add'>+		skip_map_queue = true;</div><div class='add'>+	else</div><div class='add'>+		skip_map_queue = false;</div><div class='add'>+	if (!skip_map_queue) {</div><div class='add'>+		r = amdgpu_userq_map_helper(uq_mgr, queue);</div><div class='add'>+		if (r) {</div><div class='add'>+			drm_file_err(uq_mgr-&gt;file, "Failed to map Queue\n");</div><div class='add'>+			xa_erase(&amp;uq_mgr-&gt;userq_mgr_xa, qid);</div><div class='add'>+			amdgpu_userq_fence_driver_free(queue);</div><div class='add'>+			uq_funcs-&gt;mqd_destroy(uq_mgr, queue);</div><div class='add'>+			kfree(queue);</div><div class='add'>+			goto unlock;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue_name = kasprintf(GFP_KERNEL, "queue-%d", qid);</div><div class='add'>+	if (!queue_name) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	/* Queue dentry per client to hold MQD information   */</div><div class='add'>+	queue-&gt;debugfs_queue = debugfs_create_dir(queue_name, filp-&gt;debugfs_client);</div><div class='add'>+	debugfs_create_file("mqd_info", 0444, queue-&gt;debugfs_queue, queue, &amp;amdgpu_mqd_info_fops);</div><div class='add'>+#endif</div><div class='add'>+	kfree(queue_name);</div><div class='add'>+</div><div class='add'>+	args-&gt;out.queue_id = qid;</div><div class='add'>+	atomic_inc(&amp;uq_mgr-&gt;userq_count[queue-&gt;queue_type]);</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_input_args_validate(struct drm_device *dev,</div><div class='add'>+					union drm_amdgpu_userq *args,</div><div class='add'>+					struct drm_file *filp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+</div><div class='add'>+	switch (args-&gt;in.op) {</div><div class='add'>+	case AMDGPU_USERQ_OP_CREATE:</div><div class='add'>+		if (args-&gt;in.flags &amp; ~(AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK |</div><div class='add'>+				       AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		/* Usermode queues are only supported for GFX IP as of now */</div><div class='add'>+		if (args-&gt;in.ip_type != AMDGPU_HW_IP_GFX &amp;&amp;</div><div class='add'>+		    args-&gt;in.ip_type != AMDGPU_HW_IP_DMA &amp;&amp;</div><div class='add'>+		    args-&gt;in.ip_type != AMDGPU_HW_IP_COMPUTE) {</div><div class='add'>+			drm_file_err(filp, "Usermode queue doesn't support IP type %u\n",</div><div class='add'>+				     args-&gt;in.ip_type);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((args-&gt;in.flags &amp; AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE) &amp;&amp;</div><div class='add'>+		    (args-&gt;in.ip_type != AMDGPU_HW_IP_GFX) &amp;&amp;</div><div class='add'>+		    (args-&gt;in.ip_type != AMDGPU_HW_IP_COMPUTE) &amp;&amp;</div><div class='add'>+		    !amdgpu_is_tmz(adev)) {</div><div class='add'>+			drm_file_err(filp, "Secure only supported on GFX/Compute queues\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (args-&gt;in.queue_va == AMDGPU_BO_INVALID_OFFSET ||</div><div class='add'>+		    args-&gt;in.queue_va == 0 ||</div><div class='add'>+		    args-&gt;in.queue_size == 0) {</div><div class='add'>+			drm_file_err(filp, "invalidate userq queue va or size\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		if (!args-&gt;in.wptr_va || !args-&gt;in.rptr_va) {</div><div class='add'>+			drm_file_err(filp, "invalidate userq queue rptr or wptr\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_USERQ_OP_FREE:</div><div class='add'>+		if (args-&gt;in.ip_type ||</div><div class='add'>+		    args-&gt;in.doorbell_handle ||</div><div class='add'>+		    args-&gt;in.doorbell_offset ||</div><div class='add'>+		    args-&gt;in.flags ||</div><div class='add'>+		    args-&gt;in.queue_va ||</div><div class='add'>+		    args-&gt;in.queue_size ||</div><div class='add'>+		    args-&gt;in.rptr_va ||</div><div class='add'>+		    args-&gt;in.wptr_va ||</div><div class='add'>+		    args-&gt;in.mqd ||</div><div class='add'>+		    args-&gt;in.mqd_size)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+		       struct drm_file *filp)</div><div class='add'>+{</div><div class='add'>+	union drm_amdgpu_userq *args = data;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_userq_input_args_validate(dev, args, filp) &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (args-&gt;in.op) {</div><div class='add'>+	case AMDGPU_USERQ_OP_CREATE:</div><div class='add'>+		r = amdgpu_userq_create(filp, args);</div><div class='add'>+		if (r)</div><div class='add'>+			drm_file_err(filp, "Failed to create usermode queue\n");</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case AMDGPU_USERQ_OP_FREE:</div><div class='add'>+		r = amdgpu_userq_destroy(filp, args-&gt;in.queue_id);</div><div class='add'>+		if (r)</div><div class='add'>+			drm_file_err(filp, "Failed to destroy usermode queue\n");</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		drm_dbg_driver(dev, "Invalid user queue op specified: %d\n", args-&gt;in.op);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int ret = 0, r;</div><div class='add'>+</div><div class='add'>+	/* Resume all the queues for this process */</div><div class='add'>+	xa_for_each(&amp;uq_mgr-&gt;userq_mgr_xa, queue_id, queue) {</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_userq_buffer_vas_mapped(queue)) {</div><div class='add'>+			drm_file_err(uq_mgr-&gt;file,</div><div class='add'>+				     "trying restore queue without va mapping\n");</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_INVALID_VA;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = amdgpu_userq_restore_helper(uq_mgr, queue);</div><div class='add'>+		if (r)</div><div class='add'>+			ret = r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to map all the queues\n");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_validate_vm(void *param, struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct ttm_operation_ctx ctx = { false, false };</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_placement_from_domain(bo, bo-&gt;allowed_domains);</div><div class='add'>+	return ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Handle all BOs on the invalidated list, validate them and update the PTs */</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec,</div><div class='add'>+			 struct amdgpu_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct ttm_operation_ctx ctx = { false, false };</div><div class='add'>+	struct amdgpu_bo_va *bo_va;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+	while (!list_empty(&amp;vm-&gt;invalidated)) {</div><div class='add'>+		bo_va = list_first_entry(&amp;vm-&gt;invalidated,</div><div class='add'>+					 struct amdgpu_bo_va,</div><div class='add'>+					 base.vm_status);</div><div class='add'>+		spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+</div><div class='add'>+		bo = bo_va-&gt;base.bo;</div><div class='add'>+		ret = drm_exec_prepare_obj(exec, &amp;bo-&gt;tbo.base, 2);</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		amdgpu_bo_placement_from_domain(bo, bo-&gt;allowed_domains);</div><div class='add'>+		ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/* This moves the bo_va to the done list */</div><div class='add'>+		ret = amdgpu_vm_bo_update(adev, bo_va, false);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Make sure the whole VM is ready to be used */</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr);</div><div class='add'>+	bool invalidated = false, new_addition = false;</div><div class='add'>+	struct ttm_operation_ctx ctx = { true, false };</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct amdgpu_hmm_range *range;</div><div class='add'>+	struct amdgpu_vm *vm = &amp;fpriv-&gt;vm;</div><div class='add'>+	unsigned long key, tmp_key;</div><div class='add'>+	struct amdgpu_bo_va *bo_va;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	struct xarray xa;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xa_init(&amp;xa);</div><div class='add'>+</div><div class='add'>+retry_lock:</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		ret = amdgpu_vm_lock_pd(vm, &amp;exec, 1);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			goto unlock_all;</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_vm_lock_done_list(vm, &amp;exec, 1);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			goto unlock_all;</div><div class='add'>+</div><div class='add'>+		/* This validates PDs, PTs and per VM BOs */</div><div class='add'>+		ret = amdgpu_vm_validate(adev, vm, NULL,</div><div class='add'>+					 amdgpu_userq_validate_vm,</div><div class='add'>+					 NULL);</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			goto unlock_all;</div><div class='add'>+</div><div class='add'>+		/* This locks and validates the remaining evicted BOs */</div><div class='add'>+		ret = amdgpu_userq_bo_validate(adev, &amp;exec, vm);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			goto unlock_all;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (invalidated) {</div><div class='add'>+		xa_for_each(&amp;xa, tmp_key, range) {</div><div class='add'>+			bo = range-&gt;bo;</div><div class='add'>+			amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);</div><div class='add'>+			ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto unlock_all;</div><div class='add'>+</div><div class='add'>+			amdgpu_ttm_tt_set_user_pages(bo-&gt;tbo.ttm, range);</div><div class='add'>+</div><div class='add'>+			amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);</div><div class='add'>+			ret = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto unlock_all;</div><div class='add'>+		}</div><div class='add'>+		invalidated = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_vm_handle_moved(adev, vm, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock_all;</div><div class='add'>+</div><div class='add'>+	key = 0;</div><div class='add'>+	/* Validate User Ptr BOs */</div><div class='add'>+	list_for_each_entry(bo_va, &amp;vm-&gt;done, base.vm_status) {</div><div class='add'>+		bo = bo_va-&gt;base.bo;</div><div class='add'>+		if (!bo)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_ttm_tt_is_userptr(bo-&gt;tbo.ttm))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		range = xa_load(&amp;xa, key);</div><div class='add'>+		if (range &amp;&amp; range-&gt;bo != bo) {</div><div class='add'>+			xa_erase(&amp;xa, key);</div><div class='add'>+			amdgpu_hmm_range_free(range);</div><div class='add'>+			range = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!range) {</div><div class='add'>+			range = amdgpu_hmm_range_alloc(bo);</div><div class='add'>+			if (!range) {</div><div class='add'>+				ret = -ENOMEM;</div><div class='add'>+				goto unlock_all;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			xa_store(&amp;xa, key, range, GFP_KERNEL);</div><div class='add'>+			new_addition = true;</div><div class='add'>+		}</div><div class='add'>+		key++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (new_addition) {</div><div class='add'>+		drm_exec_fini(&amp;exec);</div><div class='add'>+		xa_for_each(&amp;xa, tmp_key, range) {</div><div class='add'>+			if (!range)</div><div class='add'>+				continue;</div><div class='add'>+			bo = range-&gt;bo;</div><div class='add'>+			ret = amdgpu_ttm_tt_get_user_pages(bo, range);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto unlock_all;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		invalidated = true;</div><div class='add'>+		new_addition = false;</div><div class='add'>+		goto retry_lock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_vm_update_pdes(adev, vm, false);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock_all;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We need to wait for all VM updates to finish before restarting the</div><div class='add'>+	 * queues. Using the done list like that is now ok since everything is</div><div class='add'>+	 * locked in place.</div><div class='add'>+	 */</div><div class='add'>+	list_for_each_entry(bo_va, &amp;vm-&gt;done, base.vm_status)</div><div class='add'>+		dma_fence_wait(bo_va-&gt;last_pt_update, false);</div><div class='add'>+	dma_fence_wait(vm-&gt;last_update, false);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_eviction_fence_replace_fence(&amp;fpriv-&gt;evf_mgr, &amp;exec);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to replace eviction fence\n");</div><div class='add'>+</div><div class='add'>+unlock_all:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+	xa_for_each(&amp;xa, tmp_key, range) {</div><div class='add'>+		if (!range)</div><div class='add'>+			continue;</div><div class='add'>+		bo = range-&gt;bo;</div><div class='add'>+		amdgpu_hmm_range_free(range);</div><div class='add'>+	}</div><div class='add'>+	xa_destroy(&amp;xa);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_restore_worker(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_mgr *uq_mgr = work_to_uq_mgr(work, resume_work.work);</div><div class='add'>+	struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	flush_delayed_work(&amp;fpriv-&gt;evf_mgr.suspend_work);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_userq_vm_validate(uq_mgr);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to validate BOs to restore\n");</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_userq_restore_all(uq_mgr);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Failed to restore all queues\n");</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;uq_mgr-&gt;userq_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int ret = 0, r;</div><div class='add'>+</div><div class='add'>+	amdgpu_userq_detect_and_reset_queues(uq_mgr);</div><div class='add'>+	/* Try to unmap all the queues in this process ctx */</div><div class='add'>+	xa_for_each(&amp;uq_mgr-&gt;userq_mgr_xa, queue_id, queue) {</div><div class='add'>+		r = amdgpu_userq_preempt_helper(uq_mgr, queue);</div><div class='add'>+		if (r)</div><div class='add'>+			ret = r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_file_err(uq_mgr-&gt;file, "Couldn't unmap all the queues\n");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_reset_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,</div><div class='add'>+						  userq_reset_work);</div><div class='add'>+	struct amdgpu_reset_context reset_context;</div><div class='add'>+</div><div class='add'>+	memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='add'>+</div><div class='add'>+	reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='add'>+	reset_context.reset_req_dev = adev;</div><div class='add'>+	reset_context.src = AMDGPU_RESET_SRC_USERQ;</div><div class='add'>+	set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='add'>+	/*set_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context.flags);*/</div><div class='add'>+</div><div class='add'>+	amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;uq_mgr-&gt;userq_mgr_xa, queue_id, queue) {</div><div class='add'>+		struct dma_fence *f = queue-&gt;last_fence;</div><div class='add'>+</div><div class='add'>+		if (!f || dma_fence_is_signaled(f))</div><div class='add'>+			continue;</div><div class='add'>+		ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100));</div><div class='add'>+		if (ret &lt;= 0) {</div><div class='add'>+			drm_file_err(uq_mgr-&gt;file, "Timed out waiting for fence=%llu:%llu\n",</div><div class='add'>+				     f-&gt;context, f-&gt;seqno);</div><div class='add'>+			return -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		   struct amdgpu_eviction_fence *ev_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr);</div><div class='add'>+	struct amdgpu_eviction_fence_mgr *evf_mgr = &amp;fpriv-&gt;evf_mgr;</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Wait for any pending userqueue fence work to finish */</div><div class='add'>+	ret = amdgpu_userq_wait_for_signal(uq_mgr);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(adev-&gt;dev, "Not evicting userqueue, timeout waiting for work\n");</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_userq_evict_all(uq_mgr);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to evict userqueue\n");</div><div class='add'>+</div><div class='add'>+	/* Signal current eviction fence */</div><div class='add'>+	amdgpu_eviction_fence_signal(evf_mgr, ev_fence);</div><div class='add'>+</div><div class='add'>+	if (evf_mgr-&gt;fd_closing) {</div><div class='add'>+		cancel_delayed_work_sync(&amp;uq_mgr-&gt;resume_work);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Schedule a resume work */</div><div class='add'>+	schedule_delayed_work(&amp;uq_mgr-&gt;resume_work, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv,</div><div class='add'>+			  struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	mutex_init(&amp;userq_mgr-&gt;userq_mutex);</div><div class='add'>+	xa_init_flags(&amp;userq_mgr-&gt;userq_mgr_xa, XA_FLAGS_ALLOC);</div><div class='add'>+	userq_mgr-&gt;adev = adev;</div><div class='add'>+	userq_mgr-&gt;file = file_priv;</div><div class='add'>+</div><div class='add'>+	INIT_DELAYED_WORK(&amp;userq_mgr-&gt;resume_work, amdgpu_userq_restore_worker);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;userq_mgr-&gt;resume_work);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;userq_mgr-&gt;userq_mutex);</div><div class='add'>+	amdgpu_userq_detect_and_reset_queues(userq_mgr);</div><div class='add'>+	xa_for_each(&amp;userq_mgr-&gt;userq_mgr_xa, queue_id, queue) {</div><div class='add'>+		amdgpu_userq_wait_for_last_fence(userq_mgr, queue);</div><div class='add'>+		amdgpu_userq_unmap_helper(userq_mgr, queue);</div><div class='add'>+		amdgpu_userq_cleanup(userq_mgr, queue, queue_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xa_destroy(&amp;userq_mgr-&gt;userq_mgr_xa);</div><div class='add'>+	mutex_unlock(&amp;userq_mgr-&gt;userq_mutex);</div><div class='add'>+	mutex_destroy(&amp;userq_mgr-&gt;userq_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_suspend(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_userq_mgr *uqm;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!ip_mask)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+		uqm = queue-&gt;userq_mgr;</div><div class='add'>+		cancel_delayed_work_sync(&amp;uqm-&gt;resume_work);</div><div class='add'>+		guard(mutex)(&amp;uqm-&gt;userq_mutex);</div><div class='add'>+		amdgpu_userq_detect_and_reset_queues(uqm);</div><div class='add'>+		if (adev-&gt;in_s0ix)</div><div class='add'>+			r = amdgpu_userq_preempt_helper(uqm, queue);</div><div class='add'>+		else</div><div class='add'>+			r = amdgpu_userq_unmap_helper(uqm, queue);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_userq_mgr *uqm;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!ip_mask)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+		uqm = queue-&gt;userq_mgr;</div><div class='add'>+		guard(mutex)(&amp;uqm-&gt;userq_mutex);</div><div class='add'>+		if (adev-&gt;in_s0ix)</div><div class='add'>+			r = amdgpu_userq_restore_helper(uqm, queue);</div><div class='add'>+		else</div><div class='add'>+			r = amdgpu_userq_map_helper(uqm, queue);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+						  u32 idx)</div><div class='add'>+{</div><div class='add'>+	u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_userq_mgr *uqm;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int ret = 0, r;</div><div class='add'>+</div><div class='add'>+	/* only need to stop gfx/compute */</div><div class='add'>+	if (!(ip_mask &amp; ((1 &lt;&lt; AMDGPU_HW_IP_GFX) | (1 &lt;&lt; AMDGPU_HW_IP_COMPUTE))))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;userq_halt_for_enforce_isolation)</div><div class='add'>+		dev_warn(adev-&gt;dev, "userq scheduling already stopped!\n");</div><div class='add'>+	adev-&gt;userq_halt_for_enforce_isolation = true;</div><div class='add'>+	xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+		uqm = queue-&gt;userq_mgr;</div><div class='add'>+		cancel_delayed_work_sync(&amp;uqm-&gt;resume_work);</div><div class='add'>+		mutex_lock(&amp;uqm-&gt;userq_mutex);</div><div class='add'>+		if (((queue-&gt;queue_type == AMDGPU_HW_IP_GFX) ||</div><div class='add'>+		     (queue-&gt;queue_type == AMDGPU_HW_IP_COMPUTE)) &amp;&amp;</div><div class='add'>+		    (queue-&gt;xcp_id == idx)) {</div><div class='add'>+			amdgpu_userq_detect_and_reset_queues(uqm);</div><div class='add'>+			r = amdgpu_userq_preempt_helper(uqm, queue);</div><div class='add'>+			if (r)</div><div class='add'>+				ret = r;</div><div class='add'>+		}</div><div class='add'>+		mutex_unlock(&amp;uqm-&gt;userq_mutex);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+						   u32 idx)</div><div class='add'>+{</div><div class='add'>+	u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_userq_mgr *uqm;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int ret = 0, r;</div><div class='add'>+</div><div class='add'>+	/* only need to stop gfx/compute */</div><div class='add'>+	if (!(ip_mask &amp; ((1 &lt;&lt; AMDGPU_HW_IP_GFX) | (1 &lt;&lt; AMDGPU_HW_IP_COMPUTE))))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;userq_halt_for_enforce_isolation)</div><div class='add'>+		dev_warn(adev-&gt;dev, "userq scheduling already started!\n");</div><div class='add'>+	adev-&gt;userq_halt_for_enforce_isolation = false;</div><div class='add'>+	xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+		uqm = queue-&gt;userq_mgr;</div><div class='add'>+		mutex_lock(&amp;uqm-&gt;userq_mutex);</div><div class='add'>+			if (((queue-&gt;queue_type == AMDGPU_HW_IP_GFX) ||</div><div class='add'>+			     (queue-&gt;queue_type == AMDGPU_HW_IP_COMPUTE)) &amp;&amp;</div><div class='add'>+			    (queue-&gt;xcp_id == idx)) {</div><div class='add'>+				r = amdgpu_userq_restore_helper(uqm, queue);</div><div class='add'>+				if (r)</div><div class='add'>+					ret = r;</div><div class='add'>+			}</div><div class='add'>+		mutex_unlock(&amp;uqm-&gt;userq_mutex);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev,</div><div class='add'>+				       struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				       uint64_t saddr)</div><div class='add'>+{</div><div class='add'>+	u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev);</div><div class='add'>+	struct amdgpu_bo_va *bo_va = mapping-&gt;bo_va;</div><div class='add'>+	struct dma_resv *resv = bo_va-&gt;base.bo-&gt;tbo.base.resv;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!ip_mask)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	dev_warn_once(adev-&gt;dev, "now unmapping a vital queue va:%llx\n", saddr);</div><div class='add'>+	/**</div><div class='add'>+	 * The userq VA mapping reservation should include the eviction fence,</div><div class='add'>+	 * if the eviction fence can't signal successfully during unmapping,</div><div class='add'>+	 * then driver will warn to flag this improper unmap of the userq VA.</div><div class='add'>+	 * Note: The eviction fence may be attached to different BOs, and this</div><div class='add'>+	 * unmap is only for one kind of userq VAs, so at this point suppose</div><div class='add'>+	 * the eviction fence is always unsignaled.</div><div class='add'>+	 */</div><div class='add'>+	if (!dma_resv_test_signaled(resv, DMA_RESV_USAGE_BOOKKEEP)) {</div><div class='add'>+		ret = dma_resv_wait_timeout(resv, DMA_RESV_USAGE_BOOKKEEP, true,</div><div class='add'>+					    MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+		if (ret &lt;= 0)</div><div class='add'>+			return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_pre_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs;</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_userq_mgr *uqm;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+		uqm = queue-&gt;userq_mgr;</div><div class='add'>+		cancel_delayed_work_sync(&amp;uqm-&gt;resume_work);</div><div class='add'>+		if (queue-&gt;state == AMDGPU_USERQ_STATE_MAPPED) {</div><div class='add'>+			amdgpu_userq_wait_for_last_fence(uqm, queue);</div><div class='add'>+			userq_funcs = adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+			userq_funcs-&gt;unmap(uqm, queue);</div><div class='add'>+			/* just mark all queues as hung at this point.</div><div class='add'>+			 * if unmap succeeds, we could map again</div><div class='add'>+			 * in amdgpu_userq_post_reset() if vram is not lost</div><div class='add'>+			 */</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+			amdgpu_userq_fence_driver_force_completion(queue);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)</div><div class='add'>+{</div><div class='add'>+	/* if any queue state is AMDGPU_USERQ_STATE_UNMAPPED</div><div class='add'>+	 * at this point, we should be able to map it again</div><div class='add'>+	 * and continue if vram is not lost.</div><div class='add'>+	 */</div><div class='add'>+	struct amdgpu_userq_mgr *uqm;</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	const struct amdgpu_userq_funcs *userq_funcs;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+		uqm = queue-&gt;userq_mgr;</div><div class='add'>+		if (queue-&gt;state == AMDGPU_USERQ_STATE_HUNG &amp;&amp; !vram_lost) {</div><div class='add'>+			userq_funcs = adev-&gt;userq_funcs[queue-&gt;queue_type];</div><div class='add'>+			/* Re-map queue */</div><div class='add'>+			r = userq_funcs-&gt;map(uqm, queue);</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to remap queue %ld\n", queue_id);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+			queue-&gt;state = AMDGPU_USERQ_STATE_MAPPED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h<br/>new file mode 100644<br/>index 000000000000..c37444427a14<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef AMDGPU_USERQ_H_</div><div class='add'>+#define AMDGPU_USERQ_H_</div><div class='add'>+#include "amdgpu_eviction_fence.h"</div><div class='add'>+</div><div class='add'>+#define AMDGPU_MAX_USERQ_COUNT 512</div><div class='add'>+</div><div class='add'>+#define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base)</div><div class='add'>+#define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr)</div><div class='add'>+#define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name)</div><div class='add'>+</div><div class='add'>+enum amdgpu_userq_state {</div><div class='add'>+	AMDGPU_USERQ_STATE_UNMAPPED = 0,</div><div class='add'>+	AMDGPU_USERQ_STATE_MAPPED,</div><div class='add'>+	AMDGPU_USERQ_STATE_PREEMPTED,</div><div class='add'>+	AMDGPU_USERQ_STATE_HUNG,</div><div class='add'>+	AMDGPU_USERQ_STATE_INVALID_VA,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_mqd_prop;</div><div class='add'>+</div><div class='add'>+struct amdgpu_userq_obj {</div><div class='add'>+	void		 *cpu_ptr;</div><div class='add'>+	uint64_t	 gpu_addr;</div><div class='add'>+	struct amdgpu_bo *obj;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_userq_va_cursor {</div><div class='add'>+	u64			gpu_addr;</div><div class='add'>+	struct list_head	list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_usermode_queue {</div><div class='add'>+	int			queue_type;</div><div class='add'>+	enum amdgpu_userq_state state;</div><div class='add'>+	uint64_t		doorbell_handle;</div><div class='add'>+	uint64_t		doorbell_index;</div><div class='add'>+	uint64_t		flags;</div><div class='add'>+	struct amdgpu_mqd_prop	*userq_prop;</div><div class='add'>+	struct amdgpu_userq_mgr *userq_mgr;</div><div class='add'>+	struct amdgpu_vm	*vm;</div><div class='add'>+	struct amdgpu_userq_obj mqd;</div><div class='add'>+	struct amdgpu_userq_obj	db_obj;</div><div class='add'>+	struct amdgpu_userq_obj fw_obj;</div><div class='add'>+	struct amdgpu_userq_obj wptr_obj;</div><div class='add'>+	struct xarray		fence_drv_xa;</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv;</div><div class='add'>+	struct dma_fence	*last_fence;</div><div class='add'>+	u32			xcp_id;</div><div class='add'>+	int			priority;</div><div class='add'>+	struct dentry		*debugfs_queue;</div><div class='add'>+</div><div class='add'>+	struct list_head	userq_va_list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_userq_funcs {</div><div class='add'>+	int (*mqd_create)(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			  struct drm_amdgpu_userq_in *args,</div><div class='add'>+			  struct amdgpu_usermode_queue *queue);</div><div class='add'>+	void (*mqd_destroy)(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			    struct amdgpu_usermode_queue *uq);</div><div class='add'>+	int (*unmap)(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		     struct amdgpu_usermode_queue *queue);</div><div class='add'>+	int (*map)(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		   struct amdgpu_usermode_queue *queue);</div><div class='add'>+	int (*preempt)(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		   struct amdgpu_usermode_queue *queue);</div><div class='add'>+	int (*restore)(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		   struct amdgpu_usermode_queue *queue);</div><div class='add'>+	int (*detect_and_reset)(struct amdgpu_device *adev,</div><div class='add'>+		  int queue_type);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Usermode queues for gfx */</div><div class='add'>+struct amdgpu_userq_mgr {</div><div class='add'>+	/**</div><div class='add'>+	 * @userq_mgr_xa: Per-process user queue map (queue ID → queue)</div><div class='add'>+	 * Key: queue_id (unique ID within the process's userq manager)</div><div class='add'>+	 * Value: struct amdgpu_usermode_queue</div><div class='add'>+	 */</div><div class='add'>+	struct xarray			userq_mgr_xa;</div><div class='add'>+	struct mutex			userq_mutex;</div><div class='add'>+	struct amdgpu_device		*adev;</div><div class='add'>+	struct delayed_work		resume_work;</div><div class='add'>+	struct drm_file			*file;</div><div class='add'>+	atomic_t                        userq_count[AMDGPU_RING_TYPE_MAX];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_db_info {</div><div class='add'>+	uint64_t doorbell_handle;</div><div class='add'>+	uint32_t queue_type;</div><div class='add'>+	uint32_t doorbell_offset;</div><div class='add'>+	struct amdgpu_userq_obj	*db_obj;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv,</div><div class='add'>+			  struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr);</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			       struct amdgpu_userq_obj *userq_obj,</div><div class='add'>+			       int size);</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				 struct amdgpu_userq_obj *userq_obj);</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			struct amdgpu_eviction_fence *ev_fence);</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr,</div><div class='add'>+				  struct amdgpu_eviction_fence_mgr *evf_mgr);</div><div class='add'>+</div><div class='add'>+uint64_t amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+					 struct amdgpu_db_info *db_info,</div><div class='add'>+					     struct drm_file *filp);</div><div class='add'>+</div><div class='add'>+u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_suspend(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_userq_resume(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+						  u32 idx);</div><div class='add'>+int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev,</div><div class='add'>+						   u32 idx);</div><div class='add'>+void amdgpu_userq_reset_work(struct work_struct *work);</div><div class='add'>+void amdgpu_userq_pre_reset(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost);</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue,</div><div class='add'>+				   u64 addr, u64 expected_size);</div><div class='add'>+int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev,</div><div class='add'>+				       struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				       uint64_t saddr);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c<br/>new file mode 100644<br/>index 000000000000..eba9fb359047<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c</a></div><div class='hunk'>@@ -0,0 +1,1011 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kref.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/dma-fence-unwrap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include &lt;drm/drm_syncobj.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops amdgpu_userq_fence_ops;</div><div class='add'>+static struct kmem_cache *amdgpu_userq_fence_slab;</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_fence_slab_init(void)</div><div class='add'>+{</div><div class='add'>+	amdgpu_userq_fence_slab = kmem_cache_create("amdgpu_userq_fence",</div><div class='add'>+						    sizeof(struct amdgpu_userq_fence),</div><div class='add'>+						    0,</div><div class='add'>+						    SLAB_HWCACHE_ALIGN,</div><div class='add'>+						    NULL);</div><div class='add'>+	if (!amdgpu_userq_fence_slab)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_fence_slab_fini(void)</div><div class='add'>+{</div><div class='add'>+	rcu_barrier();</div><div class='add'>+	kmem_cache_destroy(amdgpu_userq_fence_slab);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct amdgpu_userq_fence *to_amdgpu_userq_fence(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	if (!f || f-&gt;ops != &amp;amdgpu_userq_fence_ops)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return container_of(f, struct amdgpu_userq_fence, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 amdgpu_userq_fence_read(struct amdgpu_userq_fence_driver *fence_drv)</div><div class='add'>+{</div><div class='add'>+	return le64_to_cpu(*fence_drv-&gt;cpu_addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+amdgpu_userq_fence_write(struct amdgpu_userq_fence_driver *fence_drv,</div><div class='add'>+			 u64 seq)</div><div class='add'>+{</div><div class='add'>+	if (fence_drv-&gt;cpu_addr)</div><div class='add'>+		*fence_drv-&gt;cpu_addr = cpu_to_le64(seq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev,</div><div class='add'>+				    struct amdgpu_usermode_queue *userq)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	fence_drv = kzalloc(sizeof(*fence_drv), GFP_KERNEL);</div><div class='add'>+	if (!fence_drv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Acquire seq64 memory */</div><div class='add'>+	r = amdgpu_seq64_alloc(adev, &amp;fence_drv-&gt;va, &amp;fence_drv-&gt;gpu_addr,</div><div class='add'>+			       &amp;fence_drv-&gt;cpu_addr);</div><div class='add'>+	if (r)</div><div class='add'>+		goto free_fence_drv;</div><div class='add'>+</div><div class='add'>+	memset(fence_drv-&gt;cpu_addr, 0, sizeof(u64));</div><div class='add'>+</div><div class='add'>+	kref_init(&amp;fence_drv-&gt;refcount);</div><div class='add'>+	INIT_LIST_HEAD(&amp;fence_drv-&gt;fences);</div><div class='add'>+	spin_lock_init(&amp;fence_drv-&gt;fence_list_lock);</div><div class='add'>+</div><div class='add'>+	fence_drv-&gt;adev = adev;</div><div class='add'>+	fence_drv-&gt;context = dma_fence_context_alloc(1);</div><div class='add'>+	get_task_comm(fence_drv-&gt;timeline_name, current);</div><div class='add'>+</div><div class='add'>+	xa_lock_irqsave(&amp;adev-&gt;userq_xa, flags);</div><div class='add'>+	r = xa_err(__xa_store(&amp;adev-&gt;userq_xa, userq-&gt;doorbell_index,</div><div class='add'>+			      fence_drv, GFP_KERNEL));</div><div class='add'>+	xa_unlock_irqrestore(&amp;adev-&gt;userq_xa, flags);</div><div class='add'>+	if (r)</div><div class='add'>+		goto free_seq64;</div><div class='add'>+</div><div class='add'>+	userq-&gt;fence_drv = fence_drv;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_seq64:</div><div class='add'>+	amdgpu_seq64_free(adev, fence_drv-&gt;va);</div><div class='add'>+free_fence_drv:</div><div class='add'>+	kfree(fence_drv);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv;</div><div class='add'>+	unsigned long index;</div><div class='add'>+</div><div class='add'>+	if (xa_empty(xa))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xa_lock(xa);</div><div class='add'>+	xa_for_each(xa, index, fence_drv) {</div><div class='add'>+		__xa_erase(xa, index);</div><div class='add'>+		amdgpu_userq_fence_driver_put(fence_drv);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xa_unlock(xa);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq)</div><div class='add'>+{</div><div class='add'>+	amdgpu_userq_walk_and_drop_fence_drv(&amp;userq-&gt;fence_drv_xa);</div><div class='add'>+	xa_destroy(&amp;userq-&gt;fence_drv_xa);</div><div class='add'>+	/* Drop the fence_drv reference held by user queue */</div><div class='add'>+	amdgpu_userq_fence_driver_put(userq-&gt;fence_drv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence *userq_fence, *tmp;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u64 rptr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!fence_drv)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+	rptr = amdgpu_userq_fence_read(fence_drv);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(userq_fence, tmp, &amp;fence_drv-&gt;fences, link) {</div><div class='add'>+		fence = &amp;userq_fence-&gt;base;</div><div class='add'>+</div><div class='add'>+		if (rptr &lt; fence-&gt;seqno)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		dma_fence_signal(fence);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; userq_fence-&gt;fence_drv_array_count; i++)</div><div class='add'>+			amdgpu_userq_fence_driver_put(userq_fence-&gt;fence_drv_array[i]);</div><div class='add'>+</div><div class='add'>+		list_del(&amp;userq_fence-&gt;link);</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_fence_driver_destroy(struct kref *ref)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv = container_of(ref,</div><div class='add'>+					 struct amdgpu_userq_fence_driver,</div><div class='add'>+					 refcount);</div><div class='add'>+	struct amdgpu_userq_fence_driver *xa_fence_drv;</div><div class='add'>+	struct amdgpu_device *adev = fence_drv-&gt;adev;</div><div class='add'>+	struct amdgpu_userq_fence *fence, *tmp;</div><div class='add'>+	struct xarray *xa = &amp;adev-&gt;userq_xa;</div><div class='add'>+	unsigned long index, flags;</div><div class='add'>+	struct dma_fence *f;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+	list_for_each_entry_safe(fence, tmp, &amp;fence_drv-&gt;fences, link) {</div><div class='add'>+		f = &amp;fence-&gt;base;</div><div class='add'>+</div><div class='add'>+		if (!dma_fence_is_signaled(f)) {</div><div class='add'>+			dma_fence_set_error(f, -ECANCELED);</div><div class='add'>+			dma_fence_signal(f);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		list_del(&amp;fence-&gt;link);</div><div class='add'>+		dma_fence_put(f);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+</div><div class='add'>+	xa_lock_irqsave(xa, flags);</div><div class='add'>+	xa_for_each(xa, index, xa_fence_drv)</div><div class='add'>+		if (xa_fence_drv == fence_drv)</div><div class='add'>+			__xa_erase(xa, index);</div><div class='add'>+	xa_unlock_irqrestore(xa, flags);</div><div class='add'>+</div><div class='add'>+	/* Free seq64 memory */</div><div class='add'>+	amdgpu_seq64_free(adev, fence_drv-&gt;va);</div><div class='add'>+	kfree(fence_drv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv)</div><div class='add'>+{</div><div class='add'>+	kref_get(&amp;fence_drv-&gt;refcount);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv)</div><div class='add'>+{</div><div class='add'>+	kref_put(&amp;fence_drv-&gt;refcount, amdgpu_userq_fence_driver_destroy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence)</div><div class='add'>+{</div><div class='add'>+	*userq_fence = kmem_cache_alloc(amdgpu_userq_fence_slab, GFP_ATOMIC);</div><div class='add'>+	return *userq_fence ? 0 : -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq,</div><div class='add'>+				     struct amdgpu_userq_fence *userq_fence,</div><div class='add'>+				     u64 seq, struct dma_fence **f)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	fence_drv = userq-&gt;fence_drv;</div><div class='add'>+	if (!fence_drv)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;userq_fence-&gt;lock);</div><div class='add'>+	INIT_LIST_HEAD(&amp;userq_fence-&gt;link);</div><div class='add'>+	fence = &amp;userq_fence-&gt;base;</div><div class='add'>+	userq_fence-&gt;fence_drv = fence_drv;</div><div class='add'>+</div><div class='add'>+	dma_fence_init64(fence, &amp;amdgpu_userq_fence_ops, &amp;userq_fence-&gt;lock,</div><div class='add'>+			 fence_drv-&gt;context, seq);</div><div class='add'>+</div><div class='add'>+	amdgpu_userq_fence_driver_get(fence_drv);</div><div class='add'>+	dma_fence_get(fence);</div><div class='add'>+</div><div class='add'>+	if (!xa_empty(&amp;userq-&gt;fence_drv_xa)) {</div><div class='add'>+		struct amdgpu_userq_fence_driver *stored_fence_drv;</div><div class='add'>+		unsigned long index, count = 0;</div><div class='add'>+		int i = 0;</div><div class='add'>+</div><div class='add'>+		xa_lock(&amp;userq-&gt;fence_drv_xa);</div><div class='add'>+		xa_for_each(&amp;userq-&gt;fence_drv_xa, index, stored_fence_drv)</div><div class='add'>+			count++;</div><div class='add'>+</div><div class='add'>+		userq_fence-&gt;fence_drv_array =</div><div class='add'>+			kvmalloc_array(count,</div><div class='add'>+				       sizeof(struct amdgpu_userq_fence_driver *),</div><div class='add'>+				       GFP_ATOMIC);</div><div class='add'>+</div><div class='add'>+		if (userq_fence-&gt;fence_drv_array) {</div><div class='add'>+			xa_for_each(&amp;userq-&gt;fence_drv_xa, index, stored_fence_drv) {</div><div class='add'>+				userq_fence-&gt;fence_drv_array[i] = stored_fence_drv;</div><div class='add'>+				__xa_erase(&amp;userq-&gt;fence_drv_xa, index);</div><div class='add'>+				i++;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		userq_fence-&gt;fence_drv_array_count = i;</div><div class='add'>+		xa_unlock(&amp;userq-&gt;fence_drv_xa);</div><div class='add'>+	} else {</div><div class='add'>+		userq_fence-&gt;fence_drv_array = NULL;</div><div class='add'>+		userq_fence-&gt;fence_drv_array_count = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check if hardware has already processed the job */</div><div class='add'>+	spin_lock_irqsave(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+	if (!dma_fence_is_signaled(fence))</div><div class='add'>+		list_add_tail(&amp;userq_fence-&gt;link, &amp;fence_drv-&gt;fences);</div><div class='add'>+	else</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+</div><div class='add'>+	*f = fence;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *amdgpu_userq_fence_get_driver_name(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	return "amdgpu_userq_fence";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *amdgpu_userq_fence_get_timeline_name(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f);</div><div class='add'>+</div><div class='add'>+	return fence-&gt;fence_drv-&gt;timeline_name;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_userq_fence_signaled(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f);</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv = fence-&gt;fence_drv;</div><div class='add'>+	u64 rptr, wptr;</div><div class='add'>+</div><div class='add'>+	rptr = amdgpu_userq_fence_read(fence_drv);</div><div class='add'>+	wptr = fence-&gt;base.seqno;</div><div class='add'>+</div><div class='add'>+	if (rptr &gt;= wptr)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_fence_free(struct rcu_head *rcu)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence = container_of(rcu, struct dma_fence, rcu);</div><div class='add'>+	struct amdgpu_userq_fence *userq_fence = to_amdgpu_userq_fence(fence);</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv = userq_fence-&gt;fence_drv;</div><div class='add'>+</div><div class='add'>+	/* Release the fence driver reference */</div><div class='add'>+	amdgpu_userq_fence_driver_put(fence_drv);</div><div class='add'>+</div><div class='add'>+	kvfree(userq_fence-&gt;fence_drv_array);</div><div class='add'>+	kmem_cache_free(amdgpu_userq_fence_slab, userq_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_fence_release(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	call_rcu(&amp;f-&gt;rcu, amdgpu_userq_fence_free);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops amdgpu_userq_fence_ops = {</div><div class='add'>+	.get_driver_name = amdgpu_userq_fence_get_driver_name,</div><div class='add'>+	.get_timeline_name = amdgpu_userq_fence_get_timeline_name,</div><div class='add'>+	.signaled = amdgpu_userq_fence_signaled,</div><div class='add'>+	.release = amdgpu_userq_fence_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_userq_fence_read_wptr - Read the userq wptr value</div><div class='add'>+ *</div><div class='add'>+ * @queue: user mode queue structure pointer</div><div class='add'>+ * @wptr: write pointer value</div><div class='add'>+ *</div><div class='add'>+ * Read the wptr value from userq's MQD. The userq signal IOCTL</div><div class='add'>+ * creates a dma_fence for the shared buffers that expects the</div><div class='add'>+ * RPTR value written to seq64 memory &gt;= WPTR.</div><div class='add'>+ *</div><div class='add'>+ * Returns wptr value on success, error on failure.</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_userq_fence_read_wptr(struct amdgpu_usermode_queue *queue,</div><div class='add'>+					u64 *wptr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo_va_mapping *mapping;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	u64 addr, *ptr;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(queue-&gt;vm-&gt;root.bo, false);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	addr = queue-&gt;userq_prop-&gt;wptr_gpu_addr;</div><div class='add'>+	addr &amp;= AMDGPU_GMC_HOLE_MASK;</div><div class='add'>+</div><div class='add'>+	mapping = amdgpu_vm_bo_lookup_mapping(queue-&gt;vm, addr &gt;&gt; PAGE_SHIFT);</div><div class='add'>+	if (!mapping) {</div><div class='add'>+		amdgpu_bo_unreserve(queue-&gt;vm-&gt;root.bo);</div><div class='add'>+		DRM_ERROR("Failed to lookup amdgpu_bo_va_mapping\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo = amdgpu_bo_ref(mapping-&gt;bo_va-&gt;base.bo);</div><div class='add'>+	amdgpu_bo_unreserve(queue-&gt;vm-&gt;root.bo);</div><div class='add'>+	r = amdgpu_bo_reserve(bo, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		amdgpu_bo_unref(&amp;bo);</div><div class='add'>+		DRM_ERROR("Failed to reserve userqueue wptr bo");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_kmap(bo, (void **)&amp;ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed mapping the userqueue wptr bo");</div><div class='add'>+		goto map_error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*wptr = le64_to_cpu(*ptr);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(bo);</div><div class='add'>+	amdgpu_bo_unreserve(bo);</div><div class='add'>+	amdgpu_bo_unref(&amp;bo);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+map_error:</div><div class='add'>+	amdgpu_bo_unreserve(bo);</div><div class='add'>+	amdgpu_bo_unref(&amp;bo);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_userq_fence_cleanup(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+amdgpu_userq_fence_driver_set_error(struct amdgpu_userq_fence *fence,</div><div class='add'>+				    int error)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv = fence-&gt;fence_drv;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	struct dma_fence *f;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+</div><div class='add'>+	f = rcu_dereference_protected(&amp;fence-&gt;base,</div><div class='add'>+				      lockdep_is_held(&amp;fence_drv-&gt;fence_list_lock));</div><div class='add'>+	if (f &amp;&amp; !dma_fence_is_signaled_locked(f))</div><div class='add'>+		dma_fence_set_error(f, error);</div><div class='add'>+	spin_unlock_irqrestore(&amp;fence_drv-&gt;fence_list_lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *f = userq-&gt;last_fence;</div><div class='add'>+</div><div class='add'>+	if (f) {</div><div class='add'>+		struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f);</div><div class='add'>+		struct amdgpu_userq_fence_driver *fence_drv = fence-&gt;fence_drv;</div><div class='add'>+		u64 wptr = fence-&gt;base.seqno;</div><div class='add'>+</div><div class='add'>+		amdgpu_userq_fence_driver_set_error(fence, -ECANCELED);</div><div class='add'>+		amdgpu_userq_fence_write(fence_drv, wptr);</div><div class='add'>+		amdgpu_userq_fence_driver_process(fence_drv);</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			      struct drm_file *filp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='add'>+	struct amdgpu_userq_mgr *userq_mgr = &amp;fpriv-&gt;userq_mgr;</div><div class='add'>+	struct drm_amdgpu_userq_signal *args = data;</div><div class='add'>+	struct drm_gem_object **gobj_write = NULL;</div><div class='add'>+	struct drm_gem_object **gobj_read = NULL;</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	struct amdgpu_userq_fence *userq_fence;</div><div class='add'>+	struct drm_syncobj **syncobj = NULL;</div><div class='add'>+	u32 *bo_handles_write, num_write_bo_handles;</div><div class='add'>+	u32 *syncobj_handles, num_syncobj_handles;</div><div class='add'>+	u32 *bo_handles_read, num_read_bo_handles;</div><div class='add'>+	int r, i, entry, rentry, wentry;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	u64 wptr;</div><div class='add'>+</div><div class='add'>+	num_syncobj_handles = args-&gt;num_syncobj_handles;</div><div class='add'>+	syncobj_handles = memdup_user(u64_to_user_ptr(args-&gt;syncobj_handles),</div><div class='add'>+				      size_mul(sizeof(u32), num_syncobj_handles));</div><div class='add'>+	if (IS_ERR(syncobj_handles))</div><div class='add'>+		return PTR_ERR(syncobj_handles);</div><div class='add'>+</div><div class='add'>+	/* Array of pointers to the looked up syncobjs */</div><div class='add'>+	syncobj = kmalloc_array(num_syncobj_handles, sizeof(*syncobj), GFP_KERNEL);</div><div class='add'>+	if (!syncobj) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto free_syncobj_handles;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (entry = 0; entry &lt; num_syncobj_handles; entry++) {</div><div class='add'>+		syncobj[entry] = drm_syncobj_find(filp, syncobj_handles[entry]);</div><div class='add'>+		if (!syncobj[entry]) {</div><div class='add'>+			r = -ENOENT;</div><div class='add'>+			goto free_syncobj;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_read_bo_handles = args-&gt;num_bo_read_handles;</div><div class='add'>+	bo_handles_read = memdup_user(u64_to_user_ptr(args-&gt;bo_read_handles),</div><div class='add'>+				      sizeof(u32) * num_read_bo_handles);</div><div class='add'>+	if (IS_ERR(bo_handles_read)) {</div><div class='add'>+		r = PTR_ERR(bo_handles_read);</div><div class='add'>+		goto free_syncobj;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Array of pointers to the GEM read objects */</div><div class='add'>+	gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL);</div><div class='add'>+	if (!gobj_read) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto free_bo_handles_read;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (rentry = 0; rentry &lt; num_read_bo_handles; rentry++) {</div><div class='add'>+		gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]);</div><div class='add'>+		if (!gobj_read[rentry]) {</div><div class='add'>+			r = -ENOENT;</div><div class='add'>+			goto put_gobj_read;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_write_bo_handles = args-&gt;num_bo_write_handles;</div><div class='add'>+	bo_handles_write = memdup_user(u64_to_user_ptr(args-&gt;bo_write_handles),</div><div class='add'>+				       sizeof(u32) * num_write_bo_handles);</div><div class='add'>+	if (IS_ERR(bo_handles_write)) {</div><div class='add'>+		r = PTR_ERR(bo_handles_write);</div><div class='add'>+		goto put_gobj_read;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Array of pointers to the GEM write objects */</div><div class='add'>+	gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL);</div><div class='add'>+	if (!gobj_write) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto free_bo_handles_write;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (wentry = 0; wentry &lt; num_write_bo_handles; wentry++) {</div><div class='add'>+		gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]);</div><div class='add'>+		if (!gobj_write[wentry]) {</div><div class='add'>+			r = -ENOENT;</div><div class='add'>+			goto put_gobj_write;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Retrieve the user queue */</div><div class='add'>+	queue = xa_load(&amp;userq_mgr-&gt;userq_mgr_xa, args-&gt;queue_id);</div><div class='add'>+	if (!queue) {</div><div class='add'>+		r = -ENOENT;</div><div class='add'>+		goto put_gobj_write;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_userq_fence_read_wptr(queue, &amp;wptr);</div><div class='add'>+	if (r)</div><div class='add'>+		goto put_gobj_write;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_userq_fence_alloc(&amp;userq_fence);</div><div class='add'>+	if (r)</div><div class='add'>+		goto put_gobj_write;</div><div class='add'>+</div><div class='add'>+	/* We are here means UQ is active, make sure the eviction fence is valid */</div><div class='add'>+	amdgpu_userq_ensure_ev_fence(&amp;fpriv-&gt;userq_mgr, &amp;fpriv-&gt;evf_mgr);</div><div class='add'>+</div><div class='add'>+	/* Create a new fence */</div><div class='add'>+	r = amdgpu_userq_fence_create(queue, userq_fence, wptr, &amp;fence);</div><div class='add'>+	if (r) {</div><div class='add'>+		mutex_unlock(&amp;userq_mgr-&gt;userq_mutex);</div><div class='add'>+		kmem_cache_free(amdgpu_userq_fence_slab, userq_fence);</div><div class='add'>+		goto put_gobj_write;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dma_fence_put(queue-&gt;last_fence);</div><div class='add'>+	queue-&gt;last_fence = dma_fence_get(fence);</div><div class='add'>+	mutex_unlock(&amp;userq_mgr-&gt;userq_mutex);</div><div class='add'>+</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT,</div><div class='add'>+		      (num_read_bo_handles + num_write_bo_handles));</div><div class='add'>+</div><div class='add'>+	/* Lock all BOs with retry handling */</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		r = drm_exec_prepare_array(&amp;exec, gobj_read, num_read_bo_handles, 1);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (r) {</div><div class='add'>+			amdgpu_userq_fence_cleanup(fence);</div><div class='add'>+			goto exec_fini;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = drm_exec_prepare_array(&amp;exec, gobj_write, num_write_bo_handles, 1);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (r) {</div><div class='add'>+			amdgpu_userq_fence_cleanup(fence);</div><div class='add'>+			goto exec_fini;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_read_bo_handles; i++) {</div><div class='add'>+		if (!gobj_read || !gobj_read[i]-&gt;resv)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		dma_resv_add_fence(gobj_read[i]-&gt;resv, fence,</div><div class='add'>+				   DMA_RESV_USAGE_READ);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_write_bo_handles; i++) {</div><div class='add'>+		if (!gobj_write || !gobj_write[i]-&gt;resv)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		dma_resv_add_fence(gobj_write[i]-&gt;resv, fence,</div><div class='add'>+				   DMA_RESV_USAGE_WRITE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Add the created fence to syncobj/BO's */</div><div class='add'>+	for (i = 0; i &lt; num_syncobj_handles; i++)</div><div class='add'>+		drm_syncobj_replace_fence(syncobj[i], fence);</div><div class='add'>+</div><div class='add'>+	/* drop the reference acquired in fence creation function */</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+exec_fini:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+put_gobj_write:</div><div class='add'>+	while (wentry-- &gt; 0)</div><div class='add'>+		drm_gem_object_put(gobj_write[wentry]);</div><div class='add'>+	kfree(gobj_write);</div><div class='add'>+free_bo_handles_write:</div><div class='add'>+	kfree(bo_handles_write);</div><div class='add'>+put_gobj_read:</div><div class='add'>+	while (rentry-- &gt; 0)</div><div class='add'>+		drm_gem_object_put(gobj_read[rentry]);</div><div class='add'>+	kfree(gobj_read);</div><div class='add'>+free_bo_handles_read:</div><div class='add'>+	kfree(bo_handles_read);</div><div class='add'>+free_syncobj:</div><div class='add'>+	while (entry-- &gt; 0)</div><div class='add'>+		if (syncobj[entry])</div><div class='add'>+			drm_syncobj_put(syncobj[entry]);</div><div class='add'>+	kfree(syncobj);</div><div class='add'>+free_syncobj_handles:</div><div class='add'>+	kfree(syncobj_handles);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			    struct drm_file *filp)</div><div class='add'>+{</div><div class='add'>+	u32 *syncobj_handles, *timeline_points, *timeline_handles, *bo_handles_read, *bo_handles_write;</div><div class='add'>+	u32 num_syncobj, num_read_bo_handles, num_write_bo_handles;</div><div class='add'>+	struct drm_amdgpu_userq_fence_info *fence_info = NULL;</div><div class='add'>+	struct drm_amdgpu_userq_wait *wait_info = data;</div><div class='add'>+	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='add'>+	struct amdgpu_userq_mgr *userq_mgr = &amp;fpriv-&gt;userq_mgr;</div><div class='add'>+	struct amdgpu_usermode_queue *waitq;</div><div class='add'>+	struct drm_gem_object **gobj_write;</div><div class='add'>+	struct drm_gem_object **gobj_read;</div><div class='add'>+	struct dma_fence **fences = NULL;</div><div class='add'>+	u16 num_points, num_fences = 0;</div><div class='add'>+	int r, i, rentry, wentry, cnt;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+</div><div class='add'>+	num_read_bo_handles = wait_info-&gt;num_bo_read_handles;</div><div class='add'>+	bo_handles_read = memdup_user(u64_to_user_ptr(wait_info-&gt;bo_read_handles),</div><div class='add'>+				      size_mul(sizeof(u32), num_read_bo_handles));</div><div class='add'>+	if (IS_ERR(bo_handles_read))</div><div class='add'>+		return PTR_ERR(bo_handles_read);</div><div class='add'>+</div><div class='add'>+	num_write_bo_handles = wait_info-&gt;num_bo_write_handles;</div><div class='add'>+	bo_handles_write = memdup_user(u64_to_user_ptr(wait_info-&gt;bo_write_handles),</div><div class='add'>+				       size_mul(sizeof(u32), num_write_bo_handles));</div><div class='add'>+	if (IS_ERR(bo_handles_write)) {</div><div class='add'>+		r = PTR_ERR(bo_handles_write);</div><div class='add'>+		goto free_bo_handles_read;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_syncobj = wait_info-&gt;num_syncobj_handles;</div><div class='add'>+	syncobj_handles = memdup_user(u64_to_user_ptr(wait_info-&gt;syncobj_handles),</div><div class='add'>+				      size_mul(sizeof(u32), num_syncobj));</div><div class='add'>+	if (IS_ERR(syncobj_handles)) {</div><div class='add'>+		r = PTR_ERR(syncobj_handles);</div><div class='add'>+		goto free_bo_handles_write;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_points = wait_info-&gt;num_syncobj_timeline_handles;</div><div class='add'>+	timeline_handles = memdup_user(u64_to_user_ptr(wait_info-&gt;syncobj_timeline_handles),</div><div class='add'>+				       sizeof(u32) * num_points);</div><div class='add'>+	if (IS_ERR(timeline_handles)) {</div><div class='add'>+		r = PTR_ERR(timeline_handles);</div><div class='add'>+		goto free_syncobj_handles;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	timeline_points = memdup_user(u64_to_user_ptr(wait_info-&gt;syncobj_timeline_points),</div><div class='add'>+				      sizeof(u32) * num_points);</div><div class='add'>+	if (IS_ERR(timeline_points)) {</div><div class='add'>+		r = PTR_ERR(timeline_points);</div><div class='add'>+		goto free_timeline_handles;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL);</div><div class='add'>+	if (!gobj_read) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto free_timeline_points;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (rentry = 0; rentry &lt; num_read_bo_handles; rentry++) {</div><div class='add'>+		gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]);</div><div class='add'>+		if (!gobj_read[rentry]) {</div><div class='add'>+			r = -ENOENT;</div><div class='add'>+			goto put_gobj_read;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL);</div><div class='add'>+	if (!gobj_write) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto put_gobj_read;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (wentry = 0; wentry &lt; num_write_bo_handles; wentry++) {</div><div class='add'>+		gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]);</div><div class='add'>+		if (!gobj_write[wentry]) {</div><div class='add'>+			r = -ENOENT;</div><div class='add'>+			goto put_gobj_write;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT,</div><div class='add'>+		      (num_read_bo_handles + num_write_bo_handles));</div><div class='add'>+</div><div class='add'>+	/* Lock all BOs with retry handling */</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		r = drm_exec_prepare_array(&amp;exec, gobj_read, num_read_bo_handles, 1);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (r) {</div><div class='add'>+			drm_exec_fini(&amp;exec);</div><div class='add'>+			goto put_gobj_write;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = drm_exec_prepare_array(&amp;exec, gobj_write, num_write_bo_handles, 1);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (r) {</div><div class='add'>+			drm_exec_fini(&amp;exec);</div><div class='add'>+			goto put_gobj_write;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!wait_info-&gt;num_fences) {</div><div class='add'>+		if (num_points) {</div><div class='add'>+			struct dma_fence_unwrap iter;</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+			struct dma_fence *f;</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; num_points; i++) {</div><div class='add'>+				r = drm_syncobj_find_fence(filp, timeline_handles[i],</div><div class='add'>+							   timeline_points[i],</div><div class='add'>+							   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,</div><div class='add'>+							   &amp;fence);</div><div class='add'>+				if (r)</div><div class='add'>+					goto exec_fini;</div><div class='add'>+</div><div class='add'>+				dma_fence_unwrap_for_each(f, &amp;iter, fence)</div><div class='add'>+					num_fences++;</div><div class='add'>+</div><div class='add'>+				dma_fence_put(fence);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Count syncobj's fence */</div><div class='add'>+		for (i = 0; i &lt; num_syncobj; i++) {</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			r = drm_syncobj_find_fence(filp, syncobj_handles[i],</div><div class='add'>+						   0,</div><div class='add'>+						   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,</div><div class='add'>+						   &amp;fence);</div><div class='add'>+			if (r)</div><div class='add'>+				goto exec_fini;</div><div class='add'>+</div><div class='add'>+			num_fences++;</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Count GEM objects fence */</div><div class='add'>+		for (i = 0; i &lt; num_read_bo_handles; i++) {</div><div class='add'>+			struct dma_resv_iter resv_cursor;</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			dma_resv_for_each_fence(&amp;resv_cursor, gobj_read[i]-&gt;resv,</div><div class='add'>+						DMA_RESV_USAGE_READ, fence)</div><div class='add'>+				num_fences++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; num_write_bo_handles; i++) {</div><div class='add'>+			struct dma_resv_iter resv_cursor;</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			dma_resv_for_each_fence(&amp;resv_cursor, gobj_write[i]-&gt;resv,</div><div class='add'>+						DMA_RESV_USAGE_WRITE, fence)</div><div class='add'>+				num_fences++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Passing num_fences = 0 means that userspace doesn't want to</div><div class='add'>+		 * retrieve userq_fence_info. If num_fences = 0 we skip filling</div><div class='add'>+		 * userq_fence_info and return the actual number of fences on</div><div class='add'>+		 * args-&gt;num_fences.</div><div class='add'>+		 */</div><div class='add'>+		wait_info-&gt;num_fences = num_fences;</div><div class='add'>+	} else {</div><div class='add'>+		/* Array of fence info */</div><div class='add'>+		fence_info = kmalloc_array(wait_info-&gt;num_fences, sizeof(*fence_info), GFP_KERNEL);</div><div class='add'>+		if (!fence_info) {</div><div class='add'>+			r = -ENOMEM;</div><div class='add'>+			goto exec_fini;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Array of fences */</div><div class='add'>+		fences = kmalloc_array(wait_info-&gt;num_fences, sizeof(*fences), GFP_KERNEL);</div><div class='add'>+		if (!fences) {</div><div class='add'>+			r = -ENOMEM;</div><div class='add'>+			goto free_fence_info;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Retrieve GEM read objects fence */</div><div class='add'>+		for (i = 0; i &lt; num_read_bo_handles; i++) {</div><div class='add'>+			struct dma_resv_iter resv_cursor;</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			dma_resv_for_each_fence(&amp;resv_cursor, gobj_read[i]-&gt;resv,</div><div class='add'>+						DMA_RESV_USAGE_READ, fence) {</div><div class='add'>+				if (WARN_ON_ONCE(num_fences &gt;= wait_info-&gt;num_fences)) {</div><div class='add'>+					r = -EINVAL;</div><div class='add'>+					goto free_fences;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				fences[num_fences++] = fence;</div><div class='add'>+				dma_fence_get(fence);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Retrieve GEM write objects fence */</div><div class='add'>+		for (i = 0; i &lt; num_write_bo_handles; i++) {</div><div class='add'>+			struct dma_resv_iter resv_cursor;</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			dma_resv_for_each_fence(&amp;resv_cursor, gobj_write[i]-&gt;resv,</div><div class='add'>+						DMA_RESV_USAGE_WRITE, fence) {</div><div class='add'>+				if (WARN_ON_ONCE(num_fences &gt;= wait_info-&gt;num_fences)) {</div><div class='add'>+					r = -EINVAL;</div><div class='add'>+					goto free_fences;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				fences[num_fences++] = fence;</div><div class='add'>+				dma_fence_get(fence);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (num_points) {</div><div class='add'>+			struct dma_fence_unwrap iter;</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+			struct dma_fence *f;</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; num_points; i++) {</div><div class='add'>+				r = drm_syncobj_find_fence(filp, timeline_handles[i],</div><div class='add'>+							   timeline_points[i],</div><div class='add'>+							   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,</div><div class='add'>+							   &amp;fence);</div><div class='add'>+				if (r)</div><div class='add'>+					goto free_fences;</div><div class='add'>+</div><div class='add'>+				dma_fence_unwrap_for_each(f, &amp;iter, fence) {</div><div class='add'>+					if (WARN_ON_ONCE(num_fences &gt;= wait_info-&gt;num_fences)) {</div><div class='add'>+						r = -EINVAL;</div><div class='add'>+						goto free_fences;</div><div class='add'>+					}</div><div class='add'>+</div><div class='add'>+					dma_fence_get(f);</div><div class='add'>+					fences[num_fences++] = f;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				dma_fence_put(fence);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Retrieve syncobj's fence */</div><div class='add'>+		for (i = 0; i &lt; num_syncobj; i++) {</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			r = drm_syncobj_find_fence(filp, syncobj_handles[i],</div><div class='add'>+						   0,</div><div class='add'>+						   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,</div><div class='add'>+						   &amp;fence);</div><div class='add'>+			if (r)</div><div class='add'>+				goto free_fences;</div><div class='add'>+</div><div class='add'>+			if (WARN_ON_ONCE(num_fences &gt;= wait_info-&gt;num_fences)) {</div><div class='add'>+				r = -EINVAL;</div><div class='add'>+				goto free_fences;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			fences[num_fences++] = fence;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Keep only the latest fences to reduce the number of values</div><div class='add'>+		 * given back to userspace.</div><div class='add'>+		 */</div><div class='add'>+		num_fences = dma_fence_dedup_array(fences, num_fences);</div><div class='add'>+</div><div class='add'>+		waitq = xa_load(&amp;userq_mgr-&gt;userq_mgr_xa, wait_info-&gt;waitq_id);</div><div class='add'>+		if (!waitq) {</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto free_fences;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0, cnt = 0; i &lt; num_fences; i++) {</div><div class='add'>+			struct amdgpu_userq_fence_driver *fence_drv;</div><div class='add'>+			struct amdgpu_userq_fence *userq_fence;</div><div class='add'>+			u32 index;</div><div class='add'>+</div><div class='add'>+			userq_fence = to_amdgpu_userq_fence(fences[i]);</div><div class='add'>+			if (!userq_fence) {</div><div class='add'>+				/*</div><div class='add'>+				 * Just waiting on other driver fences should</div><div class='add'>+				 * be good for now</div><div class='add'>+				 */</div><div class='add'>+				r = dma_fence_wait(fences[i], true);</div><div class='add'>+				if (r) {</div><div class='add'>+					dma_fence_put(fences[i]);</div><div class='add'>+					goto free_fences;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				dma_fence_put(fences[i]);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			fence_drv = userq_fence-&gt;fence_drv;</div><div class='add'>+			/*</div><div class='add'>+			 * We need to make sure the user queue release their reference</div><div class='add'>+			 * to the fence drivers at some point before queue destruction.</div><div class='add'>+			 * Otherwise, we would gather those references until we don't</div><div class='add'>+			 * have any more space left and crash.</div><div class='add'>+			 */</div><div class='add'>+			r = xa_alloc(&amp;waitq-&gt;fence_drv_xa, &amp;index, fence_drv,</div><div class='add'>+				     xa_limit_32b, GFP_KERNEL);</div><div class='add'>+			if (r)</div><div class='add'>+				goto free_fences;</div><div class='add'>+</div><div class='add'>+			amdgpu_userq_fence_driver_get(fence_drv);</div><div class='add'>+</div><div class='add'>+			/* Store drm syncobj's gpu va address and value */</div><div class='add'>+			fence_info[cnt].va = fence_drv-&gt;va;</div><div class='add'>+			fence_info[cnt].value = fences[i]-&gt;seqno;</div><div class='add'>+</div><div class='add'>+			dma_fence_put(fences[i]);</div><div class='add'>+			/* Increment the actual userq fence count */</div><div class='add'>+			cnt++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		wait_info-&gt;num_fences = cnt;</div><div class='add'>+		/* Copy userq fence info to user space */</div><div class='add'>+		if (copy_to_user(u64_to_user_ptr(wait_info-&gt;out_fences),</div><div class='add'>+				 fence_info, wait_info-&gt;num_fences * sizeof(*fence_info))) {</div><div class='add'>+			r = -EFAULT;</div><div class='add'>+			goto free_fences;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		kfree(fences);</div><div class='add'>+		kfree(fence_info);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+	for (i = 0; i &lt; num_read_bo_handles; i++)</div><div class='add'>+		drm_gem_object_put(gobj_read[i]);</div><div class='add'>+	kfree(gobj_read);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_write_bo_handles; i++)</div><div class='add'>+		drm_gem_object_put(gobj_write[i]);</div><div class='add'>+	kfree(gobj_write);</div><div class='add'>+</div><div class='add'>+	kfree(timeline_points);</div><div class='add'>+	kfree(timeline_handles);</div><div class='add'>+	kfree(syncobj_handles);</div><div class='add'>+	kfree(bo_handles_write);</div><div class='add'>+	kfree(bo_handles_read);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_fences:</div><div class='add'>+	while (num_fences-- &gt; 0)</div><div class='add'>+		dma_fence_put(fences[num_fences]);</div><div class='add'>+	kfree(fences);</div><div class='add'>+free_fence_info:</div><div class='add'>+	kfree(fence_info);</div><div class='add'>+exec_fini:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+put_gobj_write:</div><div class='add'>+	while (wentry-- &gt; 0)</div><div class='add'>+		drm_gem_object_put(gobj_write[wentry]);</div><div class='add'>+	kfree(gobj_write);</div><div class='add'>+put_gobj_read:</div><div class='add'>+	while (rentry-- &gt; 0)</div><div class='add'>+		drm_gem_object_put(gobj_read[rentry]);</div><div class='add'>+	kfree(gobj_read);</div><div class='add'>+free_timeline_points:</div><div class='add'>+	kfree(timeline_points);</div><div class='add'>+free_timeline_handles:</div><div class='add'>+	kfree(timeline_handles);</div><div class='add'>+free_syncobj_handles:</div><div class='add'>+	kfree(syncobj_handles);</div><div class='add'>+free_bo_handles_write:</div><div class='add'>+	kfree(bo_handles_write);</div><div class='add'>+free_bo_handles_read:</div><div class='add'>+	kfree(bo_handles_read);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h<br/>new file mode 100644<br/>index 000000000000..d76add2afc77<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_USERQ_FENCE_H__</div><div class='add'>+#define __AMDGPU_USERQ_FENCE_H__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu_userq.h"</div><div class='add'>+</div><div class='add'>+struct amdgpu_userq_fence {</div><div class='add'>+	struct dma_fence base;</div><div class='add'>+	/*</div><div class='add'>+	 * This lock is necessary to synchronize the</div><div class='add'>+	 * userqueue dma fence operations.</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t lock;</div><div class='add'>+	struct list_head link;</div><div class='add'>+	unsigned long fence_drv_array_count;</div><div class='add'>+	struct amdgpu_userq_fence_driver *fence_drv;</div><div class='add'>+	struct amdgpu_userq_fence_driver **fence_drv_array;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_userq_fence_driver {</div><div class='add'>+	struct kref refcount;</div><div class='add'>+	u64 va;</div><div class='add'>+	u64 gpu_addr;</div><div class='add'>+	u64 *cpu_addr;</div><div class='add'>+	u64 context;</div><div class='add'>+	/*</div><div class='add'>+	 * This lock is necesaary to synchronize the access</div><div class='add'>+	 * to the fences list by the fence driver.</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t fence_list_lock;</div><div class='add'>+	struct list_head fences;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	char timeline_name[TASK_COMM_LEN];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int amdgpu_userq_fence_slab_init(void);</div><div class='add'>+void amdgpu_userq_fence_slab_fini(void);</div><div class='add'>+</div><div class='add'>+void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv);</div><div class='add'>+void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv);</div><div class='add'>+int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev,</div><div class='add'>+				    struct amdgpu_usermode_queue *userq);</div><div class='add'>+void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq);</div><div class='add'>+void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv);</div><div class='add'>+void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq);</div><div class='add'>+void amdgpu_userq_fence_driver_destroy(struct kref *ref);</div><div class='add'>+int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			      struct drm_file *filp);</div><div class='add'>+int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			    struct drm_file *filp);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h<br/>new file mode 100644<br/>index 000000000000..1e40ca3b1584<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef AMDGPU_UTILS_H_</div><div class='add'>+#define AMDGPU_UTILS_H_</div><div class='add'>+</div><div class='add'>+/* ---------- Generic 2‑bit capability attribute encoding ----------</div><div class='add'>+ * 00 INVALID, 01 RO, 10 WO, 11 RW</div><div class='add'>+ */</div><div class='add'>+enum amdgpu_cap_attr {</div><div class='add'>+	AMDGPU_CAP_ATTR_INVALID = 0,</div><div class='add'>+	AMDGPU_CAP_ATTR_RO      = 1 &lt;&lt; 0,</div><div class='add'>+	AMDGPU_CAP_ATTR_WO      = 1 &lt;&lt; 1,</div><div class='add'>+	AMDGPU_CAP_ATTR_RW      = (AMDGPU_CAP_ATTR_RO | AMDGPU_CAP_ATTR_WO),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define AMDGPU_CAP_ATTR_BITS 2</div><div class='add'>+#define AMDGPU_CAP_ATTR_MAX  ((1U &lt;&lt; AMDGPU_CAP_ATTR_BITS) - 1)</div><div class='add'>+</div><div class='add'>+/* Internal helper to build helpers for a given enum NAME */</div><div class='add'>+#define DECLARE_ATTR_CAP_CLASS_HELPERS(NAME)							\</div><div class='add'>+enum { NAME##_BITMAP_BITS = NAME##_COUNT * AMDGPU_CAP_ATTR_BITS };				\</div><div class='add'>+struct NAME##_caps {										\</div><div class='add'>+	DECLARE_BITMAP(bmap, NAME##_BITMAP_BITS);						\</div><div class='add'>+};												\</div><div class='add'>+static inline unsigned int NAME##_ATTR_START(enum NAME##_cap_id cap)				\</div><div class='add'>+{ return (unsigned int)cap * AMDGPU_CAP_ATTR_BITS; }						\</div><div class='add'>+static inline void NAME##_attr_init(struct NAME##_caps *c)					\</div><div class='add'>+{ if (c) bitmap_zero(c-&gt;bmap, NAME##_BITMAP_BITS); }						\</div><div class='add'>+static inline int NAME##_attr_set(struct NAME##_caps *c,					\</div><div class='add'>+				  enum NAME##_cap_id cap, enum amdgpu_cap_attr attr)		\</div><div class='add'>+{												\</div><div class='add'>+	if (!c)											\</div><div class='add'>+		return -EINVAL;									\</div><div class='add'>+	if (cap &gt;= NAME##_COUNT)								\</div><div class='add'>+		return -EINVAL;									\</div><div class='add'>+	if ((unsigned int)attr &gt; AMDGPU_CAP_ATTR_MAX)						\</div><div class='add'>+		return -EINVAL;									\</div><div class='add'>+	bitmap_write(c-&gt;bmap, (unsigned long)attr,						\</div><div class='add'>+			NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS);				\</div><div class='add'>+	return 0;										\</div><div class='add'>+}												\</div><div class='add'>+static inline int NAME##_attr_get(const struct NAME##_caps *c,					\</div><div class='add'>+				  enum NAME##_cap_id cap, enum amdgpu_cap_attr *out)		\</div><div class='add'>+{												\</div><div class='add'>+	unsigned long v;									\</div><div class='add'>+	if (!c || !out)										\</div><div class='add'>+		return -EINVAL;									\</div><div class='add'>+	if (cap &gt;= NAME##_COUNT)								\</div><div class='add'>+		return -EINVAL;									\</div><div class='add'>+	v = bitmap_read(c-&gt;bmap, NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS);			\</div><div class='add'>+	*out = (enum amdgpu_cap_attr)v;								\</div><div class='add'>+	return 0;										\</div><div class='add'>+}												\</div><div class='add'>+static inline bool NAME##_cap_is_ro(const struct NAME##_caps *c, enum NAME##_cap_id id)		\</div><div class='add'>+{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &amp;a) &amp;&amp; a == AMDGPU_CAP_ATTR_RO; }	\</div><div class='add'>+static inline bool NAME##_cap_is_wo(const struct NAME##_caps *c, enum NAME##_cap_id id)		\</div><div class='add'>+{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &amp;a) &amp;&amp; a == AMDGPU_CAP_ATTR_WO; }	\</div><div class='add'>+static inline bool NAME##_cap_is_rw(const struct NAME##_caps *c, enum NAME##_cap_id id)		\</div><div class='add'>+{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &amp;a) &amp;&amp; a == AMDGPU_CAP_ATTR_RW; }</div><div class='add'>+</div><div class='add'>+/* Element expander for enum creation */</div><div class='add'>+#define _CAP_ENUM_ELEM(x) x,</div><div class='add'>+</div><div class='add'>+/* Public macro: declare enum + helpers from an X‑macro list */</div><div class='add'>+#define DECLARE_ATTR_CAP_CLASS(NAME, LIST_MACRO)						\</div><div class='add'>+	enum NAME##_cap_id { LIST_MACRO(_CAP_ENUM_ELEM) NAME##_COUNT };				\</div><div class='add'>+	DECLARE_ATTR_CAP_CLASS_HELPERS(NAME)</div><div class='add'>+</div><div class='add'>+#endif /* AMDGPU_UTILS_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c<br/>index 07d930339b07..5c38f0d30c87 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c</a></div><div class='hunk'>@@ -260,7 +260,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ucode_request(adev, &amp;adev-&gt;uvd.fw, fw_name);</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",</div><div class='ctx'> 			fw_name);</div><div class='hunk'>@@ -551,6 +551,8 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)</div><div class='ctx'> 	for (i = 0; i &lt; abo-&gt;placement.num_placement; ++i) {</div><div class='ctx'> 		abo-&gt;placements[i].fpfn = 0 &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> 		abo-&gt;placements[i].lpfn = (256 * 1024 * 1024) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+		if (abo-&gt;placements[i].mem_type == TTM_PL_VRAM)</div><div class='add'>+			abo-&gt;placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1088,7 +1090,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	job-&gt;vm = NULL;</div><div class='del'>-	ib-&gt;gpu_addr = amdgpu_sa_bo_gpu_addr(ib-&gt;sa_bo);</div><div class='ctx'> </div><div class='ctx'> 	if (ib-&gt;length_dw % 16) {</div><div class='ctx'> 		DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",</div><div class='hunk'>@@ -1135,7 +1136,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,</div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, &amp;adev-&gt;uvd.entity,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     64, direct ? AMDGPU_IB_POOL_DIRECT :</div><div class='del'>-				     AMDGPU_IB_POOL_DELAYED, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DELAYED, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c<br/>index 59acf424a078..a7d8f1ce6ac2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c</a></div><div class='hunk'>@@ -41,6 +41,9 @@</div><div class='ctx'> #define VCE_IDLE_TIMEOUT	msecs_to_jiffies(1000)</div><div class='ctx'> </div><div class='ctx'> /* Firmware Names */</div><div class='add'>+#ifdef CONFIG_DRM_AMDGPU_SI</div><div class='add'>+#define FIRMWARE_VCE_V1_0	"amdgpu/vce_1_0_0.bin"</div><div class='add'>+#endif</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_CIK</div><div class='ctx'> #define FIRMWARE_BONAIRE	"amdgpu/bonaire_vce.bin"</div><div class='ctx'> #define FIRMWARE_KABINI	"amdgpu/kabini_vce.bin"</div><div class='hunk'>@@ -61,6 +64,9 @@</div><div class='ctx'> #define FIRMWARE_VEGA12		"amdgpu/vega12_vce.bin"</div><div class='ctx'> #define FIRMWARE_VEGA20		"amdgpu/vega20_vce.bin"</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_DRM_AMDGPU_SI</div><div class='add'>+MODULE_FIRMWARE(FIRMWARE_VCE_V1_0);</div><div class='add'>+#endif</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_CIK</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_BONAIRE);</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_KABINI);</div><div class='hunk'>@@ -88,82 +94,93 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,</div><div class='ctx'> 				      bool direct, struct dma_fence **fence);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_vce_sw_init - allocate memory, load vce firmware</div><div class='add'>+ * amdgpu_vce_firmware_name() - determine the firmware file name for VCE</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='del'>- * @size: size for the new BO</div><div class='ctx'>  *</div><div class='del'>- * First step to get VCE online, allocate memory and load the firmware</div><div class='add'>+ * Each chip that has VCE IP may need a different firmware.</div><div class='add'>+ * This function returns the name of the VCE firmware file</div><div class='add'>+ * appropriate for the current chip.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)</div><div class='add'>+static const char *amdgpu_vce_firmware_name(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	const char *fw_name;</div><div class='del'>-	const struct common_firmware_header *hdr;</div><div class='del'>-	unsigned int ucode_version, version_major, version_minor, binary_id;</div><div class='del'>-	int i, r;</div><div class='del'>-</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='add'>+#ifdef CONFIG_DRM_AMDGPU_SI</div><div class='add'>+	case CHIP_PITCAIRN:</div><div class='add'>+	case CHIP_TAHITI:</div><div class='add'>+	case CHIP_VERDE:</div><div class='add'>+		return FIRMWARE_VCE_V1_0;</div><div class='add'>+#endif</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_CIK</div><div class='ctx'> 	case CHIP_BONAIRE:</div><div class='del'>-		fw_name = FIRMWARE_BONAIRE;</div><div class='del'>-		break;</div><div class='add'>+		return FIRMWARE_BONAIRE;</div><div class='ctx'> 	case CHIP_KAVERI:</div><div class='del'>-		fw_name = FIRMWARE_KAVERI;</div><div class='del'>-		break;</div><div class='add'>+		return FIRMWARE_KAVERI;</div><div class='ctx'> 	case CHIP_KABINI:</div><div class='del'>-		fw_name = FIRMWARE_KABINI;</div><div class='del'>-		break;</div><div class='add'>+		return FIRMWARE_KABINI;</div><div class='ctx'> 	case CHIP_HAWAII:</div><div class='del'>-		fw_name = FIRMWARE_HAWAII;</div><div class='del'>-		break;</div><div class='add'>+		return FIRMWARE_HAWAII;</div><div class='ctx'> 	case CHIP_MULLINS:</div><div class='del'>-		fw_name = FIRMWARE_MULLINS;</div><div class='del'>-		break;</div><div class='add'>+		return FIRMWARE_MULLINS;</div><div class='ctx'> #endif</div><div class='ctx'> 	case CHIP_TONGA:</div><div class='del'>-		fw_name = FIRMWARE_TONGA;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_TONGA;</div><div class='ctx'> 	case CHIP_CARRIZO:</div><div class='del'>-		fw_name = FIRMWARE_CARRIZO;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_CARRIZO;</div><div class='ctx'> 	case CHIP_FIJI:</div><div class='del'>-		fw_name = FIRMWARE_FIJI;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_FIJI;</div><div class='ctx'> 	case CHIP_STONEY:</div><div class='del'>-		fw_name = FIRMWARE_STONEY;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_STONEY;</div><div class='ctx'> 	case CHIP_POLARIS10:</div><div class='del'>-		fw_name = FIRMWARE_POLARIS10;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_POLARIS10;</div><div class='ctx'> 	case CHIP_POLARIS11:</div><div class='del'>-		fw_name = FIRMWARE_POLARIS11;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_POLARIS11;</div><div class='ctx'> 	case CHIP_POLARIS12:</div><div class='del'>-		fw_name = FIRMWARE_POLARIS12;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_POLARIS12;</div><div class='ctx'> 	case CHIP_VEGAM:</div><div class='del'>-		fw_name = FIRMWARE_VEGAM;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_VEGAM;</div><div class='ctx'> 	case CHIP_VEGA10:</div><div class='del'>-		fw_name = FIRMWARE_VEGA10;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_VEGA10;</div><div class='ctx'> 	case CHIP_VEGA12:</div><div class='del'>-		fw_name = FIRMWARE_VEGA12;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_VEGA12;</div><div class='ctx'> 	case CHIP_VEGA20:</div><div class='del'>-		fw_name = FIRMWARE_VEGA20;</div><div class='del'>-		break;</div><div class='add'>+		return  FIRMWARE_VEGA20;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return NULL;</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ucode_request(adev, &amp;adev-&gt;vce.fw, fw_name);</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vce_early_init() - try to load VCE firmware</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Tries to load the VCE firmware.</div><div class='add'>+ *</div><div class='add'>+ * When not found, returns ENOENT so that the driver can</div><div class='add'>+ * still load and initialize the rest of the IP blocks.</div><div class='add'>+ * The GPU can function just fine without VCE, they will just</div><div class='add'>+ * not support video encoding.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vce_early_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const char *fw_name = amdgpu_vce_firmware_name(adev);</div><div class='add'>+	const struct common_firmware_header *hdr;</div><div class='add'>+	unsigned int ucode_version, version_major, version_minor, binary_id;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!fw_name)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;vce.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",</div><div class='del'>-			fw_name);</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"amdgpu_vce: Firmware \"%s\" not found or failed to validate (%d)\n",</div><div class='add'>+			fw_name, r);</div><div class='add'>+</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;vce.fw);</div><div class='del'>-		return r;</div><div class='add'>+		return -ENOENT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	hdr = (const struct common_firmware_header *)adev-&gt;vce.fw-&gt;data;</div><div class='hunk'>@@ -172,11 +189,35 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)</div><div class='ctx'> 	version_major = (ucode_version &gt;&gt; 20) &amp; 0xfff;</div><div class='ctx'> 	version_minor = (ucode_version &gt;&gt; 8) &amp; 0xfff;</div><div class='ctx'> 	binary_id = ucode_version &amp; 0xff;</div><div class='del'>-	DRM_INFO("Found VCE firmware Version: %d.%d Binary ID: %d\n",</div><div class='add'>+	dev_info(adev-&gt;dev, "Found VCE firmware Version: %d.%d Binary ID: %d\n",</div><div class='ctx'> 		version_major, version_minor, binary_id);</div><div class='ctx'> 	adev-&gt;vce.fw_version = ((version_major &lt;&lt; 24) | (version_minor &lt;&lt; 16) |</div><div class='ctx'> 				(binary_id &lt;&lt; 8));</div><div class='ctx'> </div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vce_sw_init() - allocate memory for VCE BO</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @size: size for the new BO</div><div class='add'>+ *</div><div class='add'>+ * First step to get VCE online: allocate memory for VCE BO.</div><div class='add'>+ * The VCE firmware binary is copied into the VCE BO later,</div><div class='add'>+ * in amdgpu_vce_resume. The VCE executes its code from the</div><div class='add'>+ * VCE BO and also uses the space in this BO for its stack and data.</div><div class='add'>+ *</div><div class='add'>+ * Ideally this BO should be placed in VRAM for optimal performance,</div><div class='add'>+ * although technically it also runs from system RAM (albeit slowly).</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;vce.fw)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,</div><div class='ctx'> 				    AMDGPU_GEM_DOMAIN_VRAM |</div><div class='ctx'> 				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='hunk'>@@ -214,15 +255,15 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	drm_sched_entity_destroy(&amp;adev-&gt;vce.entity);</div><div class='ctx'> </div><div class='del'>-	amdgpu_bo_free_kernel(&amp;adev-&gt;vce.vcpu_bo, &amp;adev-&gt;vce.gpu_addr,</div><div class='del'>-		(void **)&amp;adev-&gt;vce.cpu_addr);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vce.num_rings; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;vce.ring[i]);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ucode_release(&amp;adev-&gt;vce.fw);</div><div class='ctx'> 	mutex_destroy(&amp;adev-&gt;vce.idle_mutex);</div><div class='ctx'> </div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;vce.vcpu_bo, &amp;adev-&gt;vce.gpu_addr,</div><div class='add'>+		(void **)&amp;adev-&gt;vce.cpu_addr);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -285,40 +326,23 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_vce_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	void *cpu_addr;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> 	unsigned int offset;</div><div class='del'>-	int r, idx;</div><div class='add'>+	int idx;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;vce.vcpu_bo == NULL)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_bo_reserve(adev-&gt;vce.vcpu_bo, false);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "(%d) failed to reserve VCE bo\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(adev-&gt;vce.vcpu_bo, &amp;cpu_addr);</div><div class='del'>-	if (r) {</div><div class='del'>-		amdgpu_bo_unreserve(adev-&gt;vce.vcpu_bo);</div><div class='del'>-		dev_err(adev-&gt;dev, "(%d) VCE map failed\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	hdr = (const struct common_firmware_header *)adev-&gt;vce.fw-&gt;data;</div><div class='ctx'> 	offset = le32_to_cpu(hdr-&gt;ucode_array_offset_bytes);</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='del'>-		memcpy_toio(cpu_addr, adev-&gt;vce.fw-&gt;data + offset,</div><div class='add'>+		memset_io(adev-&gt;vce.cpu_addr, 0, amdgpu_bo_size(adev-&gt;vce.vcpu_bo));</div><div class='add'>+		memcpy_toio(adev-&gt;vce.cpu_addr, adev-&gt;vce.fw-&gt;data + offset,</div><div class='ctx'> 			    adev-&gt;vce.fw-&gt;size - offset);</div><div class='ctx'> 		drm_dev_exit(idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_bo_kunmap(adev-&gt;vce.vcpu_bo);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_unreserve(adev-&gt;vce.vcpu_bo);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -427,6 +451,24 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vce_required_gart_pages() - gets number of GART pages required by VCE</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns how many GART pages we need before GTT for the VCE IP block.</div><div class='add'>+ * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details.</div><div class='add'>+ * For VCE2+, this is not needed so return zero.</div><div class='add'>+ */</div><div class='add'>+u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* VCE IP block not added yet, so can't use amdgpu_ip_version */</div><div class='add'>+	if (adev-&gt;family == AMDGPU_FAMILY_SI)</div><div class='add'>+		return 512;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vce_get_create_msg - generate a VCE create msg</div><div class='ctx'>  *</div><div class='ctx'>  * @ring: ring we should submit the msg to</div><div class='hunk'>@@ -449,7 +491,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,</div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, &amp;ring-&gt;adev-&gt;vce.entity,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -503,7 +545,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,</div><div class='ctx'> 		ib-&gt;ptr[i] = 0x0;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_submit_direct(job, ring, &amp;f);</div><div class='del'>-	amdgpu_ib_free(ring-&gt;adev, &amp;ib_msg, f);</div><div class='add'>+	amdgpu_ib_free(&amp;ib_msg, f);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='hunk'>@@ -540,7 +582,8 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     ib_size_dw * 4,</div><div class='ctx'> 				     direct ? AMDGPU_IB_POOL_DIRECT :</div><div class='del'>-				     AMDGPU_IB_POOL_DELAYED, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DELAYED, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -743,12 +786,12 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	uint32_t created = 0;</div><div class='ctx'> 	uint32_t allocated = 0;</div><div class='ctx'> 	uint32_t tmp, handle = 0;</div><div class='del'>-	uint32_t *size = &amp;tmp;</div><div class='add'>+	uint32_t dummy = 0xffffffff;</div><div class='add'>+	uint32_t *size = &amp;dummy;</div><div class='ctx'> 	unsigned int idx;</div><div class='ctx'> 	int i, r = 0;</div><div class='ctx'> </div><div class='ctx'> 	job-&gt;vm = NULL;</div><div class='del'>-	ib-&gt;gpu_addr = amdgpu_sa_bo_gpu_addr(ib-&gt;sa_bo);</div><div class='ctx'> </div><div class='ctx'> 	for (idx = 0; idx &lt; ib-&gt;length_dw;) {</div><div class='ctx'> 		uint32_t len = amdgpu_ib_get_value(ib, idx);</div><div class='hunk'>@@ -1043,7 +1086,6 @@ out:</div><div class='ctx'> 	if (!r) {</div><div class='ctx'> 		/* No error, free all destroyed handle slots */</div><div class='ctx'> 		tmp = destroyed;</div><div class='del'>-		amdgpu_ib_free(p-&gt;adev, ib, NULL);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Error during parsing, free all allocated handle slots */</div><div class='ctx'> 		tmp = allocated;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h<br/>index 6e53f872d084..1c3464ce5037 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h</a></div><div class='hunk'>@@ -51,14 +51,17 @@ struct amdgpu_vce {</div><div class='ctx'> 	struct drm_sched_entity	entity;</div><div class='ctx'> 	uint32_t                srbm_soft_reset;</div><div class='ctx'> 	unsigned		num_rings;</div><div class='add'>+	uint32_t		keyselect;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+int amdgpu_vce_early_init(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);</div><div class='ctx'> int amdgpu_vce_sw_fini(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);</div><div class='ctx'> int amdgpu_vce_suspend(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_vce_resume(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);</div><div class='add'>+u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job,</div><div class='ctx'> 			     struct amdgpu_ib *ib);</div><div class='ctx'> int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c<br/>index 9c514a606a2f..5e0786ea911b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2016 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2016-2024 Advanced Micro Devices, Inc.</div><div class='ctx'>  * All Rights Reserved.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='hunk'>@@ -62,6 +62,7 @@</div><div class='ctx'> #define FIRMWARE_VCN4_0_6		"amdgpu/vcn_4_0_6.bin"</div><div class='ctx'> #define FIRMWARE_VCN4_0_6_1		"amdgpu/vcn_4_0_6_1.bin"</div><div class='ctx'> #define FIRMWARE_VCN5_0_0		"amdgpu/vcn_5_0_0.bin"</div><div class='add'>+#define FIRMWARE_VCN5_0_1		"amdgpu/vcn_5_0_1.bin"</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_RAVEN);</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_PICASSO);</div><div class='hunk'>@@ -88,50 +89,59 @@ MODULE_FIRMWARE(FIRMWARE_VCN4_0_5);</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_VCN4_0_6);</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1);</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_VCN5_0_0);</div><div class='add'>+MODULE_FIRMWARE(FIRMWARE_VCN5_0_1);</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_vcn_idle_work_handler(struct work_struct *work);</div><div class='add'>+static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='del'>-int amdgpu_vcn_early_init(struct amdgpu_device *adev)</div><div class='add'>+int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i)</div><div class='ctx'> {</div><div class='del'>-	char ucode_prefix[30];</div><div class='del'>-	char fw_name[40];</div><div class='del'>-	int r, i;</div><div class='add'>+	char ucode_prefix[25];</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);</div><div class='del'>-		if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==  IP_VERSION(4, 0, 6) &amp;&amp;</div><div class='del'>-			i == 1) {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_%d.bin", ucode_prefix, i);</div><div class='del'>-		}</div><div class='add'>+	adev-&gt;vcn.inst[i].adev = adev;</div><div class='add'>+	adev-&gt;vcn.inst[i].inst = i;</div><div class='add'>+	amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ucode_request(adev, &amp;adev-&gt;vcn.fw[i], fw_name);</div><div class='del'>-		if (r) {</div><div class='del'>-			amdgpu_ucode_release(&amp;adev-&gt;vcn.fw[i]);</div><div class='del'>-			return r;</div><div class='add'>+	if (i != 0 &amp;&amp; adev-&gt;vcn.per_inst_fw) {</div><div class='add'>+		r = amdgpu_ucode_request(adev, &amp;adev-&gt;vcn.inst[i].fw,</div><div class='add'>+					 AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					 "amdgpu/%s_%d.bin", ucode_prefix, i);</div><div class='add'>+		if (r)</div><div class='add'>+			amdgpu_ucode_release(&amp;adev-&gt;vcn.inst[i].fw);</div><div class='add'>+	} else {</div><div class='add'>+		if (!adev-&gt;vcn.inst[0].fw) {</div><div class='add'>+			r = amdgpu_ucode_request(adev, &amp;adev-&gt;vcn.inst[0].fw,</div><div class='add'>+						 AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						 "amdgpu/%s.bin", ucode_prefix);</div><div class='add'>+			if (r)</div><div class='add'>+				amdgpu_ucode_release(&amp;adev-&gt;vcn.inst[0].fw);</div><div class='add'>+		} else {</div><div class='add'>+			r = 0;</div><div class='ctx'> 		}</div><div class='add'>+		adev-&gt;vcn.inst[i].fw = adev-&gt;vcn.inst[0].fw;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_vcn_sw_init(struct amdgpu_device *adev)</div><div class='add'>+int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long bo_size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> 	unsigned char fw_check;</div><div class='ctx'> 	unsigned int fw_shared_size, log_offset;</div><div class='del'>-	int i, r;</div><div class='del'>-</div><div class='del'>-	INIT_DELAYED_WORK(&amp;adev-&gt;vcn.idle_work, amdgpu_vcn_idle_work_handler);</div><div class='del'>-	mutex_init(&amp;adev-&gt;vcn.vcn_pg_lock);</div><div class='del'>-	mutex_init(&amp;adev-&gt;vcn.vcn1_jpeg1_workaround);</div><div class='del'>-	atomic_set(&amp;adev-&gt;vcn.total_submission_cnt, 0);</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='del'>-		atomic_set(&amp;adev-&gt;vcn.inst[i].dpg_enc_submission_cnt, 0);</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='add'>+	mutex_init(&amp;adev-&gt;vcn.inst[i].vcn1_jpeg1_workaround);</div><div class='add'>+	mutex_init(&amp;adev-&gt;vcn.inst[i].vcn_pg_lock);</div><div class='add'>+	mutex_init(&amp;adev-&gt;vcn.inst[i].engine_reset_mutex);</div><div class='add'>+	atomic_set(&amp;adev-&gt;vcn.inst[i].total_submission_cnt, 0);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;adev-&gt;vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);</div><div class='add'>+	atomic_set(&amp;adev-&gt;vcn.inst[i].dpg_enc_submission_cnt, 0);</div><div class='ctx'> 	if ((adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) &amp;&amp;</div><div class='ctx'> 	    (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG))</div><div class='del'>-		adev-&gt;vcn.indirect_sram = true;</div><div class='add'>+		adev-&gt;vcn.inst[i].indirect_sram = true;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Some Steam Deck's BIOS versions are incompatible with the</div><div class='hunk'>@@ -144,14 +154,19 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);</div><div class='ctx'> </div><div class='ctx'> 		if (bios_ver &amp;&amp; (!strncmp("F7A0113", bios_ver, 7) ||</div><div class='del'>-		     !strncmp("F7A0114", bios_ver, 7))) {</div><div class='del'>-			adev-&gt;vcn.indirect_sram = false;</div><div class='add'>+				 !strncmp("F7A0114", bios_ver, 7))) {</div><div class='add'>+			adev-&gt;vcn.inst[i].indirect_sram = false;</div><div class='ctx'> 			dev_info(adev-&gt;dev,</div><div class='del'>-				"Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);</div><div class='add'>+				 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[0]-&gt;data;</div><div class='add'>+	/* from vcn4 and above, only unified queue is used */</div><div class='add'>+	adev-&gt;vcn.inst[i].using_unified_queue =</div><div class='add'>+		amdgpu_ip_version(adev, UVD_HWIP, 0) &gt;= IP_VERSION(4, 0, 0);</div><div class='add'>+</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[i].fw-&gt;data;</div><div class='add'>+	adev-&gt;vcn.inst[i].fw_version = le32_to_cpu(hdr-&gt;ucode_version);</div><div class='ctx'> 	adev-&gt;vcn.fw_version = le32_to_cpu(hdr-&gt;ucode_version);</div><div class='ctx'> </div><div class='ctx'> 	/* Bit 20-23, it is encode major and non-zero for new naming convention.</div><div class='hunk'>@@ -169,23 +184,27 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		enc_major = fw_check;</div><div class='ctx'> 		dec_ver = (le32_to_cpu(hdr-&gt;ucode_version) &gt;&gt; 24) &amp; 0xf;</div><div class='ctx'> 		vep = (le32_to_cpu(hdr-&gt;ucode_version) &gt;&gt; 28) &amp; 0xf;</div><div class='del'>-		DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",</div><div class='del'>-			enc_major, enc_minor, dec_ver, vep, fw_rev);</div><div class='add'>+		dev_info(adev-&gt;dev,</div><div class='add'>+			 "[VCN instance %d] Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",</div><div class='add'>+			 i, enc_major, enc_minor, dec_ver, vep, fw_rev);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		unsigned int version_major, version_minor, family_id;</div><div class='ctx'> </div><div class='ctx'> 		family_id = le32_to_cpu(hdr-&gt;ucode_version) &amp; 0xff;</div><div class='ctx'> 		version_major = (le32_to_cpu(hdr-&gt;ucode_version) &gt;&gt; 24) &amp; 0xff;</div><div class='ctx'> 		version_minor = (le32_to_cpu(hdr-&gt;ucode_version) &gt;&gt; 8) &amp; 0xff;</div><div class='del'>-		DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",</div><div class='del'>-			version_major, version_minor, family_id);</div><div class='add'>+		dev_info(adev-&gt;dev, "[VCN instance %d] Found VCN firmware Version: %u.%u Family ID: %u\n",</div><div class='add'>+			 i, version_major, version_minor, family_id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;</div><div class='ctx'> 	if (adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP)</div><div class='ctx'> 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, UVD_HWIP, 0) &gt;= IP_VERSION(4, 0, 0)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, UVD_HWIP, 0) &gt;= IP_VERSION(5, 0, 0)) {</div><div class='add'>+		fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared));</div><div class='add'>+		log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log);</div><div class='add'>+	} else if (amdgpu_ip_version(adev, UVD_HWIP, 0) &gt;= IP_VERSION(4, 0, 0)) {</div><div class='ctx'> 		fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));</div><div class='ctx'> 		log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -198,100 +217,87 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_vcnfw_log)</div><div class='ctx'> 		bo_size += AMDGPU_VCNFW_LOG_SIZE;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='add'>+	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_VRAM |</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				    &amp;adev-&gt;vcn.inst[i].vcpu_bo,</div><div class='add'>+				    &amp;adev-&gt;vcn.inst[i].gpu_addr,</div><div class='add'>+				    &amp;adev-&gt;vcn.inst[i].cpu_addr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to allocate vcn bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.inst[i].fw_shared.cpu_addr = adev-&gt;vcn.inst[i].cpu_addr +</div><div class='add'>+		bo_size - fw_shared_size;</div><div class='add'>+	adev-&gt;vcn.inst[i].fw_shared.gpu_addr = adev-&gt;vcn.inst[i].gpu_addr +</div><div class='add'>+		bo_size - fw_shared_size;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,</div><div class='add'>+	adev-&gt;vcn.inst[i].fw_shared.mem_size = fw_shared_size;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_vcnfw_log) {</div><div class='add'>+		adev-&gt;vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;</div><div class='add'>+		adev-&gt;vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;</div><div class='add'>+		adev-&gt;vcn.inst[i].fw_shared.log_offset = log_offset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.inst[i].indirect_sram) {</div><div class='add'>+		r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,</div><div class='ctx'> 					    AMDGPU_GEM_DOMAIN_VRAM |</div><div class='ctx'> 					    AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-					    &amp;adev-&gt;vcn.inst[i].vcpu_bo,</div><div class='del'>-					    &amp;adev-&gt;vcn.inst[i].gpu_addr,</div><div class='del'>-					    &amp;adev-&gt;vcn.inst[i].cpu_addr);</div><div class='add'>+					    &amp;adev-&gt;vcn.inst[i].dpg_sram_bo,</div><div class='add'>+					    &amp;adev-&gt;vcn.inst[i].dpg_sram_gpu_addr,</div><div class='add'>+					    &amp;adev-&gt;vcn.inst[i].dpg_sram_cpu_addr);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) failed to allocate vcn bo\n", r);</div><div class='add'>+			dev_err(adev-&gt;dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		adev-&gt;vcn.inst[i].fw_shared.cpu_addr = adev-&gt;vcn.inst[i].cpu_addr +</div><div class='del'>-				bo_size - fw_shared_size;</div><div class='del'>-		adev-&gt;vcn.inst[i].fw_shared.gpu_addr = adev-&gt;vcn.inst[i].gpu_addr +</div><div class='del'>-				bo_size - fw_shared_size;</div><div class='del'>-</div><div class='del'>-		adev-&gt;vcn.inst[i].fw_shared.mem_size = fw_shared_size;</div><div class='del'>-</div><div class='del'>-		if (amdgpu_vcnfw_log) {</div><div class='del'>-			adev-&gt;vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;</div><div class='del'>-			adev-&gt;vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;</div><div class='del'>-			adev-&gt;vcn.inst[i].fw_shared.log_offset = log_offset;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (adev-&gt;vcn.indirect_sram) {</div><div class='del'>-			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,</div><div class='del'>-					AMDGPU_GEM_DOMAIN_VRAM |</div><div class='del'>-					AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-					&amp;adev-&gt;vcn.inst[i].dpg_sram_bo,</div><div class='del'>-					&amp;adev-&gt;vcn.inst[i].dpg_sram_gpu_addr,</div><div class='del'>-					&amp;adev-&gt;vcn.inst[i].dpg_sram_cpu_addr);</div><div class='del'>-			if (r) {</div><div class='del'>-				dev_err(adev-&gt;dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);</div><div class='del'>-				return r;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i)</div><div class='ctx'> {</div><div class='del'>-	int i, j;</div><div class='add'>+	int j;</div><div class='ctx'> </div><div class='del'>-	for (j = 0; j &lt; adev-&gt;vcn.num_vcn_inst; ++j) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; j))</div><div class='del'>-			continue;</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-		amdgpu_bo_free_kernel(</div><div class='del'>-			&amp;adev-&gt;vcn.inst[j].dpg_sram_bo,</div><div class='del'>-			&amp;adev-&gt;vcn.inst[j].dpg_sram_gpu_addr,</div><div class='del'>-			(void **)&amp;adev-&gt;vcn.inst[j].dpg_sram_cpu_addr);</div><div class='add'>+	amdgpu_bo_free_kernel(</div><div class='add'>+		&amp;adev-&gt;vcn.inst[i].dpg_sram_bo,</div><div class='add'>+		&amp;adev-&gt;vcn.inst[i].dpg_sram_gpu_addr,</div><div class='add'>+		(void **)&amp;adev-&gt;vcn.inst[i].dpg_sram_cpu_addr);</div><div class='ctx'> </div><div class='del'>-		kvfree(adev-&gt;vcn.inst[j].saved_bo);</div><div class='add'>+	kvfree(adev-&gt;vcn.inst[i].saved_bo);</div><div class='ctx'> </div><div class='del'>-		amdgpu_bo_free_kernel(&amp;adev-&gt;vcn.inst[j].vcpu_bo,</div><div class='del'>-					  &amp;adev-&gt;vcn.inst[j].gpu_addr,</div><div class='del'>-					  (void **)&amp;adev-&gt;vcn.inst[j].cpu_addr);</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;vcn.inst[i].vcpu_bo,</div><div class='add'>+			      &amp;adev-&gt;vcn.inst[i].gpu_addr,</div><div class='add'>+			      (void **)&amp;adev-&gt;vcn.inst[i].cpu_addr);</div><div class='ctx'> </div><div class='del'>-		amdgpu_ring_fini(&amp;adev-&gt;vcn.inst[j].ring_dec);</div><div class='add'>+	amdgpu_ring_fini(&amp;adev-&gt;vcn.inst[i].ring_dec);</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='del'>-			amdgpu_ring_fini(&amp;adev-&gt;vcn.inst[j].ring_enc[i]);</div><div class='add'>+	for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j)</div><div class='add'>+		amdgpu_ring_fini(&amp;adev-&gt;vcn.inst[i].ring_enc[j]);</div><div class='ctx'> </div><div class='del'>-		amdgpu_ucode_release(&amp;adev-&gt;vcn.fw[j]);</div><div class='add'>+	if (adev-&gt;vcn.per_inst_fw) {</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;vcn.inst[i].fw);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;vcn.inst[0].fw);</div><div class='add'>+		adev-&gt;vcn.inst[i].fw = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_destroy(&amp;adev-&gt;vcn.vcn1_jpeg1_workaround);</div><div class='del'>-	mutex_destroy(&amp;adev-&gt;vcn.vcn_pg_lock);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* from vcn4 and above, only unified queue is used */</div><div class='del'>-static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	bool ret = false;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_ip_version(adev, UVD_HWIP, 0) &gt;= IP_VERSION(4, 0, 0))</div><div class='del'>-		ret = true;</div><div class='add'>+	if (adev-&gt;vcn.reg_list)</div><div class='add'>+		amdgpu_vcn_reg_dump_fini(adev);</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	mutex_destroy(&amp;adev-&gt;vcn.inst[i].vcn_pg_lock);</div><div class='add'>+	mutex_destroy(&amp;adev-&gt;vcn.inst[i].vcn1_jpeg1_workaround);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)</div><div class='ctx'> {</div><div class='ctx'> 	bool ret = false;</div><div class='del'>-	int vcn_config = adev-&gt;vcn.vcn_config[vcn_instance];</div><div class='add'>+	int vcn_config = adev-&gt;vcn.inst[vcn_instance].vcn_config;</div><div class='ctx'> </div><div class='ctx'> 	if ((type == VCN_ENCODE_RING) &amp;&amp; (vcn_config &amp; VCN_BLOCK_ENCODE_DISABLE_MASK))</div><div class='ctx'> 		ret = true;</div><div class='hunk'>@@ -303,180 +309,246 @@ bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type t</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_vcn_suspend(struct amdgpu_device *adev)</div><div class='add'>+static int amdgpu_vcn_save_vcpu_bo_inst(struct amdgpu_device *adev, int i)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int size;</div><div class='ctx'> 	void *ptr;</div><div class='del'>-	int i, idx;</div><div class='add'>+	int idx;</div><div class='ctx'> </div><div class='del'>-	bool in_ras_intr = amdgpu_ras_intr_triggered();</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='add'>+	if (adev-&gt;vcn.inst[i].vcpu_bo == NULL)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	size = amdgpu_bo_size(adev-&gt;vcn.inst[i].vcpu_bo);</div><div class='add'>+	ptr = adev-&gt;vcn.inst[i].cpu_addr;</div><div class='ctx'> </div><div class='del'>-	/* err_event_athub will corrupt VCPU buffer, so we need to</div><div class='del'>-	 * restore fw data and clear buffer in amdgpu_vcn_resume() */</div><div class='del'>-	if (in_ras_intr)</div><div class='del'>-		return 0;</div><div class='add'>+	adev-&gt;vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;vcn.inst[i].saved_bo)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		if (adev-&gt;vcn.inst[i].vcpu_bo == NULL)</div><div class='del'>-			return 0;</div><div class='add'>+	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='add'>+		memcpy_fromio(adev-&gt;vcn.inst[i].saved_bo, ptr, size);</div><div class='add'>+		drm_dev_exit(idx);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		size = amdgpu_bo_size(adev-&gt;vcn.inst[i].vcpu_bo);</div><div class='del'>-		ptr = adev-&gt;vcn.inst[i].cpu_addr;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);</div><div class='del'>-		if (!adev-&gt;vcn.inst[i].saved_bo)</div><div class='del'>-			return -ENOMEM;</div><div class='add'>+int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int ret, i;</div><div class='ctx'> </div><div class='del'>-		if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='del'>-			memcpy_fromio(adev-&gt;vcn.inst[i].saved_bo, ptr, size);</div><div class='del'>-			drm_dev_exit(idx);</div><div class='del'>-		}</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		ret = amdgpu_vcn_save_vcpu_bo_inst(adev, i);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_vcn_resume(struct amdgpu_device *adev)</div><div class='add'>+int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i)</div><div class='add'>+{</div><div class='add'>+	bool in_ras_intr = amdgpu_ras_intr_triggered();</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* err_event_athub and dpc recovery will corrupt VCPU buffer, so we need to</div><div class='add'>+	 * restore fw data and clear buffer in amdgpu_vcn_resume() */</div><div class='add'>+	if (in_ras_intr || adev-&gt;pcie_reset_ctx.in_link_reset)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return amdgpu_vcn_save_vcpu_bo_inst(adev, i);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_vcn_resume(struct amdgpu_device *adev, int i)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int size;</div><div class='ctx'> 	void *ptr;</div><div class='del'>-	int i, idx;</div><div class='add'>+	int idx;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		if (adev-&gt;vcn.inst[i].vcpu_bo == NULL)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='add'>+	if (adev-&gt;vcn.inst[i].vcpu_bo == NULL)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		size = amdgpu_bo_size(adev-&gt;vcn.inst[i].vcpu_bo);</div><div class='del'>-		ptr = adev-&gt;vcn.inst[i].cpu_addr;</div><div class='add'>+	size = amdgpu_bo_size(adev-&gt;vcn.inst[i].vcpu_bo);</div><div class='add'>+	ptr = adev-&gt;vcn.inst[i].cpu_addr;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.inst[i].saved_bo != NULL) {</div><div class='add'>+		if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='add'>+			memcpy_toio(ptr, adev-&gt;vcn.inst[i].saved_bo, size);</div><div class='add'>+			drm_dev_exit(idx);</div><div class='add'>+		}</div><div class='add'>+		kvfree(adev-&gt;vcn.inst[i].saved_bo);</div><div class='add'>+		adev-&gt;vcn.inst[i].saved_bo = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		const struct common_firmware_header *hdr;</div><div class='add'>+		unsigned int offset;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;vcn.inst[i].saved_bo != NULL) {</div><div class='add'>+		hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[i].fw-&gt;data;</div><div class='add'>+		if (adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+			offset = le32_to_cpu(hdr-&gt;ucode_array_offset_bytes);</div><div class='ctx'> 			if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='del'>-				memcpy_toio(ptr, adev-&gt;vcn.inst[i].saved_bo, size);</div><div class='add'>+				memcpy_toio(adev-&gt;vcn.inst[i].cpu_addr,</div><div class='add'>+					    adev-&gt;vcn.inst[i].fw-&gt;data + offset,</div><div class='add'>+					    le32_to_cpu(hdr-&gt;ucode_size_bytes));</div><div class='ctx'> 				drm_dev_exit(idx);</div><div class='ctx'> 			}</div><div class='del'>-			kvfree(adev-&gt;vcn.inst[i].saved_bo);</div><div class='del'>-			adev-&gt;vcn.inst[i].saved_bo = NULL;</div><div class='del'>-		} else {</div><div class='del'>-			const struct common_firmware_header *hdr;</div><div class='del'>-			unsigned int offset;</div><div class='del'>-</div><div class='del'>-			hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[i]-&gt;data;</div><div class='del'>-			if (adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP) {</div><div class='del'>-				offset = le32_to_cpu(hdr-&gt;ucode_array_offset_bytes);</div><div class='del'>-				if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='del'>-					memcpy_toio(adev-&gt;vcn.inst[i].cpu_addr,</div><div class='del'>-						    adev-&gt;vcn.fw[i]-&gt;data + offset,</div><div class='del'>-						    le32_to_cpu(hdr-&gt;ucode_size_bytes));</div><div class='del'>-					drm_dev_exit(idx);</div><div class='del'>-				}</div><div class='del'>-				size -= le32_to_cpu(hdr-&gt;ucode_size_bytes);</div><div class='del'>-				ptr += le32_to_cpu(hdr-&gt;ucode_size_bytes);</div><div class='del'>-			}</div><div class='del'>-			memset_io(ptr, 0, size);</div><div class='add'>+			size -= le32_to_cpu(hdr-&gt;ucode_size_bytes);</div><div class='add'>+			ptr += le32_to_cpu(hdr-&gt;ucode_size_bytes);</div><div class='ctx'> 		}</div><div class='add'>+		memset_io(ptr, 0, size);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_vcn_get_profile(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;vcn.workload_profile_mutex);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.workload_profile_active) {</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;vcn.workload_profile_mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,</div><div class='add'>+					    true);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "(%d) failed to enable video power profile mode\n", r);</div><div class='add'>+	else</div><div class='add'>+		adev-&gt;vcn.workload_profile_active = true;</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;vcn.workload_profile_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_vcn_put_profile(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	bool pg = true;</div><div class='add'>+	int r, i;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;vcn.workload_profile_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		if (adev-&gt;vcn.inst[i].cur_state != AMD_PG_STATE_GATE) {</div><div class='add'>+			pg = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pg) {</div><div class='add'>+		r = amdgpu_dpm_switch_power_profile(</div><div class='add'>+			adev, PP_SMC_POWER_PROFILE_VIDEO, false);</div><div class='add'>+		if (r)</div><div class='add'>+			dev_warn(</div><div class='add'>+				adev-&gt;dev,</div><div class='add'>+				"(%d) failed to disable video power profile mode\n",</div><div class='add'>+				r);</div><div class='add'>+		else</div><div class='add'>+			adev-&gt;vcn.workload_profile_active = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;vcn.workload_profile_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_vcn_idle_work_handler(struct work_struct *work)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev =</div><div class='del'>-		container_of(work, struct amdgpu_device, vcn.idle_work.work);</div><div class='add'>+	struct amdgpu_vcn_inst *vcn_inst =</div><div class='add'>+		container_of(work, struct amdgpu_vcn_inst, idle_work.work);</div><div class='add'>+	struct amdgpu_device *adev = vcn_inst-&gt;adev;</div><div class='ctx'> 	unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};</div><div class='del'>-	unsigned int i, j;</div><div class='del'>-	int r = 0;</div><div class='del'>-</div><div class='del'>-	for (j = 0; j &lt; adev-&gt;vcn.num_vcn_inst; ++j) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; j))</div><div class='del'>-			continue;</div><div class='add'>+	unsigned int i = vcn_inst-&gt;inst, j;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='del'>-			fence[j] += amdgpu_fence_count_emitted(&amp;adev-&gt;vcn.inst[j].ring_enc[i]);</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)	{</div><div class='del'>-			struct dpg_pause_state new_state;</div><div class='add'>+	for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j)</div><div class='add'>+		fence[i] += amdgpu_fence_count_emitted(&amp;vcn_inst-&gt;ring_enc[j]);</div><div class='ctx'> </div><div class='del'>-			if (fence[j] ||</div><div class='del'>-				unlikely(atomic_read(&amp;adev-&gt;vcn.inst[j].dpg_enc_submission_cnt)))</div><div class='del'>-				new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='del'>-			else</div><div class='del'>-				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;</div><div class='add'>+	/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG &amp;&amp;</div><div class='add'>+	    !adev-&gt;vcn.inst[i].using_unified_queue) {</div><div class='add'>+		struct dpg_pause_state new_state;</div><div class='ctx'> </div><div class='del'>-			adev-&gt;vcn.pause_dpg_mode(adev, j, &amp;new_state);</div><div class='del'>-		}</div><div class='add'>+		if (fence[i] ||</div><div class='add'>+		    unlikely(atomic_read(&amp;vcn_inst-&gt;dpg_enc_submission_cnt)))</div><div class='add'>+			new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='add'>+		else</div><div class='add'>+			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;</div><div class='ctx'> </div><div class='del'>-		fence[j] += amdgpu_fence_count_emitted(&amp;adev-&gt;vcn.inst[j].ring_dec);</div><div class='del'>-		fences += fence[j];</div><div class='add'>+		adev-&gt;vcn.inst[i].pause_dpg_mode(vcn_inst, &amp;new_state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!fences &amp;&amp; !atomic_read(&amp;adev-&gt;vcn.total_submission_cnt)) {</div><div class='del'>-		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,</div><div class='del'>-		       AMD_PG_STATE_GATE);</div><div class='del'>-		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,</div><div class='del'>-				false);</div><div class='del'>-		if (r)</div><div class='del'>-			dev_warn(adev-&gt;dev, "(%d) failed to disable video power profile mode\n", r);</div><div class='add'>+	fence[i] += amdgpu_fence_count_emitted(&amp;vcn_inst-&gt;ring_dec);</div><div class='add'>+	fences += fence[i];</div><div class='add'>+</div><div class='add'>+	if (!fences &amp;&amp; !atomic_read(&amp;vcn_inst-&gt;total_submission_cnt)) {</div><div class='add'>+		mutex_lock(&amp;vcn_inst-&gt;vcn_pg_lock);</div><div class='add'>+		vcn_inst-&gt;set_pg_state(vcn_inst, AMD_PG_STATE_GATE);</div><div class='add'>+		mutex_unlock(&amp;vcn_inst-&gt;vcn_pg_lock);</div><div class='add'>+		amdgpu_vcn_put_profile(adev);</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='del'>-		schedule_delayed_work(&amp;adev-&gt;vcn.idle_work, VCN_IDLE_TIMEOUT);</div><div class='add'>+		schedule_delayed_work(&amp;vcn_inst-&gt;idle_work, VCN_IDLE_TIMEOUT);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	int r = 0;</div><div class='add'>+	struct amdgpu_vcn_inst *vcn_inst = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='ctx'> </div><div class='del'>-	atomic_inc(&amp;adev-&gt;vcn.total_submission_cnt);</div><div class='add'>+	atomic_inc(&amp;vcn_inst-&gt;total_submission_cnt);</div><div class='ctx'> </div><div class='del'>-	if (!cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work)) {</div><div class='del'>-		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,</div><div class='del'>-				true);</div><div class='del'>-		if (r)</div><div class='del'>-			dev_warn(adev-&gt;dev, "(%d) failed to switch to video power profile mode\n", r);</div><div class='del'>-	}</div><div class='add'>+	cancel_delayed_work_sync(&amp;vcn_inst-&gt;idle_work);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;adev-&gt;vcn.vcn_pg_lock);</div><div class='del'>-	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,</div><div class='del'>-	       AMD_PG_STATE_UNGATE);</div><div class='add'>+	mutex_lock(&amp;vcn_inst-&gt;vcn_pg_lock);</div><div class='add'>+	vcn_inst-&gt;set_pg_state(vcn_inst, AMD_PG_STATE_UNGATE);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)	{</div><div class='add'>+	/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG &amp;&amp;</div><div class='add'>+	    !vcn_inst-&gt;using_unified_queue) {</div><div class='ctx'> 		struct dpg_pause_state new_state;</div><div class='ctx'> </div><div class='ctx'> 		if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC) {</div><div class='del'>-			atomic_inc(&amp;adev-&gt;vcn.inst[ring-&gt;me].dpg_enc_submission_cnt);</div><div class='add'>+			atomic_inc(&amp;vcn_inst-&gt;dpg_enc_submission_cnt);</div><div class='ctx'> 			new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			unsigned int fences = 0;</div><div class='ctx'> 			unsigned int i;</div><div class='ctx'> </div><div class='del'>-			for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='del'>-				fences += amdgpu_fence_count_emitted(&amp;adev-&gt;vcn.inst[ring-&gt;me].ring_enc[i]);</div><div class='add'>+			for (i = 0; i &lt; vcn_inst-&gt;num_enc_rings; ++i)</div><div class='add'>+				fences += amdgpu_fence_count_emitted(&amp;vcn_inst-&gt;ring_enc[i]);</div><div class='ctx'> </div><div class='del'>-			if (fences || atomic_read(&amp;adev-&gt;vcn.inst[ring-&gt;me].dpg_enc_submission_cnt))</div><div class='add'>+			if (fences || atomic_read(&amp;vcn_inst-&gt;dpg_enc_submission_cnt))</div><div class='ctx'> 				new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='ctx'> 			else</div><div class='ctx'> 				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode(adev, ring-&gt;me, &amp;new_state);</div><div class='add'>+		vcn_inst-&gt;pause_dpg_mode(vcn_inst, &amp;new_state);</div><div class='ctx'> 	}</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;vcn.vcn_pg_lock);</div><div class='add'>+	mutex_unlock(&amp;vcn_inst-&gt;vcn_pg_lock);</div><div class='add'>+	amdgpu_vcn_get_profile(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */</div><div class='ctx'> 	if (ring-&gt;adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG &amp;&amp;</div><div class='del'>-		ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC)</div><div class='add'>+	    ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC &amp;&amp;</div><div class='add'>+	    !adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		atomic_dec(&amp;ring-&gt;adev-&gt;vcn.inst[ring-&gt;me].dpg_enc_submission_cnt);</div><div class='ctx'> </div><div class='del'>-	atomic_dec(&amp;ring-&gt;adev-&gt;vcn.total_submission_cnt);</div><div class='add'>+	atomic_dec(&amp;ring-&gt;adev-&gt;vcn.inst[ring-&gt;me].total_submission_cnt);</div><div class='ctx'> </div><div class='del'>-	schedule_delayed_work(&amp;ring-&gt;adev-&gt;vcn.idle_work, VCN_IDLE_TIMEOUT);</div><div class='add'>+	schedule_delayed_work(&amp;ring-&gt;adev-&gt;vcn.inst[ring-&gt;me].idle_work,</div><div class='add'>+			      VCN_IDLE_TIMEOUT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)</div><div class='hunk'>@@ -494,7 +566,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, 3);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.scratch9, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.scratch9, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0xDEADBEEF);</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='hunk'>@@ -554,19 +626,19 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL,</div><div class='ctx'> 				     64, AMDGPU_IB_POOL_DIRECT,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='ctx'> 	ib = &amp;job-&gt;ibs[0];</div><div class='del'>-	ib-&gt;ptr[0] = PACKET0(adev-&gt;vcn.internal.data0, 0);</div><div class='add'>+	ib-&gt;ptr[0] = PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0);</div><div class='ctx'> 	ib-&gt;ptr[1] = addr;</div><div class='del'>-	ib-&gt;ptr[2] = PACKET0(adev-&gt;vcn.internal.data1, 0);</div><div class='add'>+	ib-&gt;ptr[2] = PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data1, 0);</div><div class='ctx'> 	ib-&gt;ptr[3] = addr &gt;&gt; 32;</div><div class='del'>-	ib-&gt;ptr[4] = PACKET0(adev-&gt;vcn.internal.cmd, 0);</div><div class='add'>+	ib-&gt;ptr[4] = PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0);</div><div class='ctx'> 	ib-&gt;ptr[5] = 0;</div><div class='ctx'> 	for (i = 6; i &lt; 16; i += 2) {</div><div class='del'>-		ib-&gt;ptr[i] = PACKET0(adev-&gt;vcn.internal.nop, 0);</div><div class='add'>+		ib-&gt;ptr[i] = PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.nop, 0);</div><div class='ctx'> 		ib-&gt;ptr[i+1] = 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	ib-&gt;length_dw = 16;</div><div class='hunk'>@@ -575,7 +647,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ib_free(adev, ib_msg, f);</div><div class='add'>+	amdgpu_ib_free(ib_msg, f);</div><div class='ctx'> </div><div class='ctx'> 	if (fence)</div><div class='ctx'> 		*fence = dma_fence_get(f);</div><div class='hunk'>@@ -586,7 +658,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> err_free:</div><div class='ctx'> 	amdgpu_job_free(job);</div><div class='ctx'> err:</div><div class='del'>-	amdgpu_ib_free(adev, ib_msg, f);</div><div class='add'>+	amdgpu_ib_free(ib_msg, f);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -725,17 +797,16 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> 	struct amdgpu_job *job;</div><div class='ctx'> 	struct amdgpu_ib *ib;</div><div class='ctx'> 	uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg-&gt;gpu_addr);</div><div class='del'>-	bool sq = amdgpu_vcn_using_unified_queue(ring);</div><div class='ctx'> 	uint32_t *ib_checksum;</div><div class='ctx'> 	uint32_t ib_pack_in_dw;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		ib_size_dw += 8;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL,</div><div class='ctx'> 				     ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='hunk'>@@ -743,7 +814,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> 	ib-&gt;length_dw = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* single queue headers */</div><div class='del'>-	if (sq) {</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue) {</div><div class='ctx'> 		ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)</div><div class='ctx'> 						+ 4 + 2; /* engine info + decoding ib in dw */</div><div class='ctx'> 		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);</div><div class='hunk'>@@ -762,14 +833,14 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> 	for (i = ib-&gt;length_dw; i &lt; ib_size_dw; ++i)</div><div class='ctx'> 		ib-&gt;ptr[i] = 0x0;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		amdgpu_vcn_unified_ring_ib_checksum(&amp;ib_checksum, ib_pack_in_dw);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_submit_direct(job, ring, &amp;f);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ib_free(adev, ib_msg, f);</div><div class='add'>+	amdgpu_ib_free(ib_msg, f);</div><div class='ctx'> </div><div class='ctx'> 	if (fence)</div><div class='ctx'> 		*fence = dma_fence_get(f);</div><div class='hunk'>@@ -780,7 +851,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,</div><div class='ctx'> err_free:</div><div class='ctx'> 	amdgpu_job_free(job);</div><div class='ctx'> err:</div><div class='del'>-	amdgpu_ib_free(adev, ib_msg, f);</div><div class='add'>+	amdgpu_ib_free(ib_msg, f);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -852,20 +923,20 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand</div><div class='ctx'> 					 struct dma_fence **fence)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int ib_size_dw = 16;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct amdgpu_job *job;</div><div class='ctx'> 	struct amdgpu_ib *ib;</div><div class='ctx'> 	struct dma_fence *f = NULL;</div><div class='ctx'> 	uint32_t *ib_checksum = NULL;</div><div class='ctx'> 	uint64_t addr;</div><div class='del'>-	bool sq = amdgpu_vcn_using_unified_queue(ring);</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		ib_size_dw += 8;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL,</div><div class='ctx'> 				     ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -874,7 +945,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand</div><div class='ctx'> </div><div class='ctx'> 	ib-&gt;length_dw = 0;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);</div><div class='ctx'> </div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000018;</div><div class='hunk'>@@ -882,7 +953,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = handle;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(addr);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = addr;</div><div class='del'>-	ib-&gt;ptr[ib-&gt;length_dw++] = 0x0000000b;</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000000;</div><div class='ctx'> </div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000014;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000002; /* task info */</div><div class='hunk'>@@ -896,7 +967,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand</div><div class='ctx'> 	for (i = ib-&gt;length_dw; i &lt; ib_size_dw; ++i)</div><div class='ctx'> 		ib-&gt;ptr[i] = 0x0;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		amdgpu_vcn_unified_ring_ib_checksum(&amp;ib_checksum, 0x11);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_submit_direct(job, ring, &amp;f);</div><div class='hunk'>@@ -919,20 +990,20 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han</div><div class='ctx'> 					  struct dma_fence **fence)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int ib_size_dw = 16;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct amdgpu_job *job;</div><div class='ctx'> 	struct amdgpu_ib *ib;</div><div class='ctx'> 	struct dma_fence *f = NULL;</div><div class='ctx'> 	uint32_t *ib_checksum = NULL;</div><div class='ctx'> 	uint64_t addr;</div><div class='del'>-	bool sq = amdgpu_vcn_using_unified_queue(ring);</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		ib_size_dw += 8;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL,</div><div class='ctx'> 				     ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -941,7 +1012,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han</div><div class='ctx'> </div><div class='ctx'> 	ib-&gt;length_dw = 0;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);</div><div class='ctx'> </div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000018;</div><div class='hunk'>@@ -949,7 +1020,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = handle;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(addr);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = addr;</div><div class='del'>-	ib-&gt;ptr[ib-&gt;length_dw++] = 0x0000000b;</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000000;</div><div class='ctx'> </div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000014;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0x00000002;</div><div class='hunk'>@@ -963,7 +1034,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han</div><div class='ctx'> 	for (i = ib-&gt;length_dw; i &lt; ib_size_dw; ++i)</div><div class='ctx'> 		ib-&gt;ptr[i] = 0x0;</div><div class='ctx'> </div><div class='del'>-	if (sq)</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='ctx'> 		amdgpu_vcn_unified_ring_ib_checksum(&amp;ib_checksum, 0x11);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_submit_direct(job, ring, &amp;f);</div><div class='hunk'>@@ -1010,7 +1081,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = 0;</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, fence);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, fence);</div><div class='ctx'> 	dma_fence_put(fence);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1021,7 +1092,8 @@ int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	long r;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) {</div><div class='add'>+	if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) &amp;&amp;</div><div class='add'>+	    (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1))) {</div><div class='ctx'> 		r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto error;</div><div class='hunk'>@@ -1047,35 +1119,32 @@ enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='ctx'> 	unsigned int idx;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 		const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[i]-&gt;data;</div><div class='del'>-			/* currently only support 2 FW instances */</div><div class='del'>-			if (i &gt;= 2) {</div><div class='del'>-				dev_info(adev-&gt;dev, "More then 2 VCN FW instances!\n");</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-			idx = AMDGPU_UCODE_ID_VCN + i;</div><div class='del'>-			adev-&gt;firmware.ucode[idx].ucode_id = idx;</div><div class='del'>-			adev-&gt;firmware.ucode[idx].fw = adev-&gt;vcn.fw[i];</div><div class='del'>-			adev-&gt;firmware.fw_size +=</div><div class='del'>-				ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes), PAGE_SIZE);</div><div class='del'>-</div><div class='del'>-			if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==</div><div class='del'>-			    IP_VERSION(4, 0, 3))</div><div class='del'>-				break;</div><div class='add'>+		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) ||</div><div class='add'>+		     amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1))</div><div class='add'>+		    &amp;&amp; (i &gt; 0))</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[i].fw-&gt;data;</div><div class='add'>+		/* currently only support 2 FW instances */</div><div class='add'>+		if (i &gt;= 2) {</div><div class='add'>+			dev_info(adev-&gt;dev, "More then 2 VCN FW instances!\n");</div><div class='add'>+			return;</div><div class='ctx'> 		}</div><div class='del'>-		dev_info(adev-&gt;dev, "Will use PSP to load VCN firmware\n");</div><div class='add'>+		idx = AMDGPU_UCODE_ID_VCN + i;</div><div class='add'>+		adev-&gt;firmware.ucode[idx].ucode_id = idx;</div><div class='add'>+		adev-&gt;firmware.ucode[idx].fw = adev-&gt;vcn.inst[i].fw;</div><div class='add'>+		adev-&gt;firmware.fw_size +=</div><div class='add'>+			ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes), PAGE_SIZE);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1088,7 +1157,7 @@ static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vcn_inst *vcn;</div><div class='ctx'> 	void *log_buf;</div><div class='del'>-	volatile struct amdgpu_vcn_fwlog *plog;</div><div class='add'>+	struct amdgpu_vcn_fwlog *plog;</div><div class='ctx'> 	unsigned int read_pos, write_pos, available, i, read_bytes = 0;</div><div class='ctx'> 	unsigned int read_num[2] = {0};</div><div class='ctx'> </div><div class='hunk'>@@ -1101,7 +1170,7 @@ static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,</div><div class='ctx'> </div><div class='ctx'> 	log_buf = vcn-&gt;fw_shared.cpu_addr + vcn-&gt;fw_shared.mem_size;</div><div class='ctx'> </div><div class='del'>-	plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;</div><div class='add'>+	plog = (struct amdgpu_vcn_fwlog *)log_buf;</div><div class='ctx'> 	read_pos = plog-&gt;rptr;</div><div class='ctx'> 	write_pos = plog-&gt;wptr;</div><div class='ctx'> </div><div class='hunk'>@@ -1168,11 +1237,11 @@ void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,</div><div class='ctx'> void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)</div><div class='ctx'> {</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='del'>-	volatile uint32_t *flag = vcn-&gt;fw_shared.cpu_addr;</div><div class='add'>+	uint32_t *flag = vcn-&gt;fw_shared.cpu_addr;</div><div class='ctx'> 	void *fw_log_cpu_addr = vcn-&gt;fw_shared.cpu_addr + vcn-&gt;fw_shared.mem_size;</div><div class='ctx'> 	uint64_t fw_log_gpu_addr = vcn-&gt;fw_shared.gpu_addr + vcn-&gt;fw_shared.mem_size;</div><div class='del'>-	volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;</div><div class='del'>-	volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn-&gt;fw_shared.cpu_addr</div><div class='add'>+	struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;</div><div class='add'>+	struct amdgpu_fw_shared_fw_logging *fw_log = vcn-&gt;fw_shared.cpu_addr</div><div class='ctx'> 							 + vcn-&gt;fw_shared.log_offset;</div><div class='ctx'> 	*flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);</div><div class='ctx'> 	fw_log-&gt;is_enabled = 1;</div><div class='hunk'>@@ -1280,3 +1349,289 @@ int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,</div><div class='ctx'> </div><div class='ctx'> 	return psp_execute_ip_fw_load(&amp;adev-&gt;psp, &amp;ucode);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	return amdgpu_show_reset_mask(buf, adev-&gt;vcn.supported_reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR(vcn_reset_mask, 0444,</div><div class='add'>+		   amdgpu_get_vcn_reset_mask, NULL);</div><div class='add'>+</div><div class='add'>+int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.num_vcn_inst) {</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_vcn_reset_mask);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd) {</div><div class='add'>+		if (adev-&gt;vcn.num_vcn_inst)</div><div class='add'>+			device_remove_file(adev-&gt;dev, &amp;dev_attr_vcn_reset_mask);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * debugfs to enable/disable vcn job submission to specific core or</div><div class='add'>+ * instance. It is created only if the queue type is unified.</div><div class='add'>+ */</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i;</div><div class='add'>+	u64 mask;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	mask = (1ULL &lt;&lt; adev-&gt;vcn.num_vcn_inst) - 1;</div><div class='add'>+	if ((val &amp; mask) == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+		if (val &amp; (1ULL &lt;&lt; i))</div><div class='add'>+			ring-&gt;sched.ready = true;</div><div class='add'>+		else</div><div class='add'>+			ring-&gt;sched.ready = false;</div><div class='add'>+	}</div><div class='add'>+	/* publish sched.ready flag update effective immediately across smp */</div><div class='add'>+	smp_rmb();</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='add'>+	u32 i;</div><div class='add'>+	u64 mask = 0;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+		if (ring-&gt;sched.ready)</div><div class='add'>+			mask |= 1ULL &lt;&lt; i;</div><div class='add'>+		}</div><div class='add'>+	*val = mask;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops,</div><div class='add'>+			 amdgpu_debugfs_vcn_sched_mask_get,</div><div class='add'>+			 amdgpu_debugfs_vcn_sched_mask_set, "%llx\n");</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	char name[32];</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.num_vcn_inst &lt;= 1 || !adev-&gt;vcn.inst[0].using_unified_queue)</div><div class='add'>+		return;</div><div class='add'>+	sprintf(name, "amdgpu_vcn_sched_mask");</div><div class='add'>+	debugfs_create_file(name, 0600, root, adev,</div><div class='add'>+			    &amp;amdgpu_debugfs_vcn_sched_mask_fops);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_set_powergating_state - set VCN block powergating state</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: amdgpu_ip_block pointer</div><div class='add'>+ * @state: power gating state</div><div class='add'>+ *</div><div class='add'>+ * Set VCN block powergating state</div><div class='add'>+ */</div><div class='add'>+int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+			      enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int ret = 0, i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='add'>+		ret |= vinst-&gt;set_pg_state(vinst, state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vcn_reset_engine - Reset a specific VCN engine</div><div class='add'>+ * @adev: Pointer to the AMDGPU device</div><div class='add'>+ * @instance_id: VCN engine instance to reset</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success, or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev,</div><div class='add'>+				   uint32_t instance_id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[instance_id];</div><div class='add'>+	int r, i;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;vinst-&gt;engine_reset_mutex);</div><div class='add'>+	/* Stop the scheduler's work queue for the dec and enc rings if they are running.</div><div class='add'>+	 * This ensures that no new tasks are submitted to the queues while</div><div class='add'>+	 * the reset is in progress.</div><div class='add'>+	 */</div><div class='add'>+	drm_sched_wqueue_stop(&amp;vinst-&gt;ring_dec.sched);</div><div class='add'>+	for (i = 0; i &lt; vinst-&gt;num_enc_rings; i++)</div><div class='add'>+		drm_sched_wqueue_stop(&amp;vinst-&gt;ring_enc[i].sched);</div><div class='add'>+</div><div class='add'>+	/* Perform the VCN reset for the specified instance */</div><div class='add'>+	r = vinst-&gt;reset(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unlock;</div><div class='add'>+	r = amdgpu_ring_test_ring(&amp;vinst-&gt;ring_dec);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unlock;</div><div class='add'>+	for (i = 0; i &lt; vinst-&gt;num_enc_rings; i++) {</div><div class='add'>+		r = amdgpu_ring_test_ring(&amp;vinst-&gt;ring_enc[i]);</div><div class='add'>+		if (r)</div><div class='add'>+			goto unlock;</div><div class='add'>+	}</div><div class='add'>+	amdgpu_fence_driver_force_completion(&amp;vinst-&gt;ring_dec);</div><div class='add'>+	for (i = 0; i &lt; vinst-&gt;num_enc_rings; i++)</div><div class='add'>+		amdgpu_fence_driver_force_completion(&amp;vinst-&gt;ring_enc[i]);</div><div class='add'>+</div><div class='add'>+	/* Restart the scheduler's work queue for the dec and enc rings</div><div class='add'>+	 * if they were stopped by this function. This allows new tasks</div><div class='add'>+	 * to be submitted to the queues after the reset is complete.</div><div class='add'>+	 */</div><div class='add'>+	drm_sched_wqueue_start(&amp;vinst-&gt;ring_dec.sched);</div><div class='add'>+	for (i = 0; i &lt; vinst-&gt;num_enc_rings; i++)</div><div class='add'>+		drm_sched_wqueue_start(&amp;vinst-&gt;ring_enc[i].sched);</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;vinst-&gt;engine_reset_mutex);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vcn_ring_reset - Reset a VCN ring</div><div class='add'>+ * @ring: ring to reset</div><div class='add'>+ * @vmid: vmid of guilty job</div><div class='add'>+ * @timedout_fence: fence of timed out job</div><div class='add'>+ *</div><div class='add'>+ * This helper is for VCN blocks without unified queues because</div><div class='add'>+ * resetting the engine resets all queues in that case.  With</div><div class='add'>+ * unified queues we have one queue per engine.</div><div class='add'>+ * Returns: 0 on success, or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+			  unsigned int vmid,</div><div class='add'>+			  struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return amdgpu_vcn_reset_engine(adev, ring-&gt;me);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev,</div><div class='add'>+			     const struct amdgpu_hwip_reg_entry *reg, u32 count)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;vcn.ip_dump = kcalloc(adev-&gt;vcn.num_vcn_inst * count,</div><div class='add'>+				     sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;vcn.ip_dump)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;vcn.reg_list = reg;</div><div class='add'>+	adev-&gt;vcn.reg_count = count;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	kfree(adev-&gt;vcn.ip_dump);</div><div class='add'>+	adev-&gt;vcn.ip_dump = NULL;</div><div class='add'>+	adev-&gt;vcn.reg_list = NULL;</div><div class='add'>+	adev-&gt;vcn.reg_count = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	bool is_powered;</div><div class='add'>+	u32 inst_off;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;vcn.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		inst_off = i * adev-&gt;vcn.reg_count;</div><div class='add'>+		/* mmUVD_POWER_STATUS is always readable and is the first in reg_list */</div><div class='add'>+		adev-&gt;vcn.ip_dump[inst_off] =</div><div class='add'>+			RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev-&gt;vcn.reg_list[0], i));</div><div class='add'>+		is_powered = (adev-&gt;vcn.ip_dump[inst_off] &amp;</div><div class='add'>+			      UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) !=</div><div class='add'>+			      UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;</div><div class='add'>+</div><div class='add'>+		if (is_powered)</div><div class='add'>+			for (j = 1; j &lt; adev-&gt;vcn.reg_count; j++)</div><div class='add'>+				adev-&gt;vcn.ip_dump[inst_off + j] =</div><div class='add'>+				RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev-&gt;vcn.reg_list[j], i));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	bool is_powered;</div><div class='add'>+	u32 inst_off;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;vcn.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;vcn.num_vcn_inst);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i)) {</div><div class='add'>+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		inst_off = i * adev-&gt;vcn.reg_count;</div><div class='add'>+		is_powered = (adev-&gt;vcn.ip_dump[inst_off] &amp;</div><div class='add'>+			      UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) !=</div><div class='add'>+			      UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;</div><div class='add'>+</div><div class='add'>+		if (is_powered) {</div><div class='add'>+			drm_printf(p, "\nActive Instance:VCN%d\n", i);</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;vcn.reg_count; j++)</div><div class='add'>+				drm_printf(p, "%-50s \t 0x%08x\n", adev-&gt;vcn.reg_list[j].reg_name,</div><div class='add'>+					   adev-&gt;vcn.ip_dump[inst_off + j]);</div><div class='add'>+		} else {</div><div class='add'>+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h<br/>index a418393d89ec..82624b44e661 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2016 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2016-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'>  * copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -66,7 +66,6 @@</div><div class='ctx'> #define VCN_ENC_CMD_REG_WAIT		0x0000000c</div><div class='ctx'> </div><div class='ctx'> #define VCN_AON_SOC_ADDRESS_2_0 	0x1f800</div><div class='del'>-#define VCN1_AON_SOC_ADDRESS_3_0 	0x48000</div><div class='ctx'> #define VCN_VID_IP_ADDRESS_2_0		0x0</div><div class='ctx'> #define VCN_AON_IP_ADDRESS_2_0		0x30000</div><div class='ctx'> </div><div class='hunk'>@@ -101,7 +100,8 @@</div><div class='ctx'> </div><div class='ctx'> #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) 						\</div><div class='ctx'> 	({											\</div><div class='del'>-		uint32_t internal_reg_offset, addr;						\</div><div class='add'>+		/* To avoid a -Wunused-but-set-variable warning. */				\</div><div class='add'>+		uint32_t internal_reg_offset __maybe_unused, addr;				\</div><div class='ctx'> 		bool video_range, video1_range, aon_range, aon1_range;				\</div><div class='ctx'> 												\</div><div class='ctx'> 		addr = (adev-&gt;reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);		\</div><div class='hunk'>@@ -162,21 +162,32 @@</div><div class='ctx'> </div><div class='ctx'> #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg)						\</div><div class='ctx'> 	({											\</div><div class='del'>-		uint32_t internal_reg_offset, addr;						\</div><div class='del'>-		bool video_range, aon_range;				\</div><div class='add'>+		/* To avoid a -Wunused-but-set-variable warning. */				\</div><div class='add'>+		uint32_t internal_reg_offset __maybe_unused, addr;				\</div><div class='add'>+		bool video_range, video1_range, aon_range, aon1_range;				\</div><div class='ctx'> 												\</div><div class='ctx'> 		addr = (adev-&gt;reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);		\</div><div class='ctx'> 		addr &lt;&lt;= 2;									\</div><div class='ctx'> 		video_range = ((((0xFFFFF &amp; addr) &gt;= (VCN_VID_SOC_ADDRESS)) &amp;&amp;			\</div><div class='ctx'> 				((0xFFFFF &amp; addr) &lt; ((VCN_VID_SOC_ADDRESS + 0x2600)))));	\</div><div class='add'>+		video1_range = ((((0xFFFFF &amp; addr) &gt;= (VCN1_VID_SOC_ADDRESS)) &amp;&amp;		\</div><div class='add'>+				((0xFFFFF &amp; addr) &lt; ((VCN1_VID_SOC_ADDRESS + 0x2600)))));	\</div><div class='ctx'> 		aon_range   = ((((0xFFFFF &amp; addr) &gt;= (VCN_AON_SOC_ADDRESS)) &amp;&amp;			\</div><div class='ctx'> 				((0xFFFFF &amp; addr) &lt; ((VCN_AON_SOC_ADDRESS + 0x600)))));		\</div><div class='add'>+		aon1_range   = ((((0xFFFFF &amp; addr) &gt;= (VCN1_AON_SOC_ADDRESS)) &amp;&amp;		\</div><div class='add'>+				((0xFFFFF &amp; addr) &lt; ((VCN1_AON_SOC_ADDRESS + 0x600)))));	\</div><div class='ctx'> 		if (video_range)								\</div><div class='ctx'> 			internal_reg_offset = ((0xFFFFF &amp; addr) - (VCN_VID_SOC_ADDRESS) +	\</div><div class='ctx'> 				(VCN_VID_IP_ADDRESS));						\</div><div class='ctx'> 		else if (aon_range)								\</div><div class='ctx'> 			internal_reg_offset = ((0xFFFFF &amp; addr) - (VCN_AON_SOC_ADDRESS) +	\</div><div class='ctx'> 				(VCN_AON_IP_ADDRESS));						\</div><div class='add'>+		else if (video1_range)								\</div><div class='add'>+			internal_reg_offset = ((0xFFFFF &amp; addr) - (VCN1_VID_SOC_ADDRESS) +	\</div><div class='add'>+				(VCN_VID_IP_ADDRESS));						\</div><div class='add'>+		else if (aon1_range)								\</div><div class='add'>+			internal_reg_offset = ((0xFFFFF &amp; addr) - (VCN1_AON_SOC_ADDRESS) +	\</div><div class='add'>+				(VCN_AON_IP_ADDRESS));						\</div><div class='ctx'> 		else										\</div><div class='ctx'> 			internal_reg_offset = (0xFFFFF &amp; addr);					\</div><div class='ctx'> 												\</div><div class='hunk'>@@ -228,6 +239,14 @@</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2</div><div class='ctx'> </div><div class='add'>+struct amdgpu_hwip_reg_entry;</div><div class='add'>+</div><div class='add'>+enum amdgpu_vcn_caps {</div><div class='add'>+	AMDGPU_VCN_RRMT_ENABLED,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define AMDGPU_VCN_CAPS(caps) BIT(AMDGPU_VCN_##caps)</div><div class='add'>+</div><div class='ctx'> enum fw_queue_mode {</div><div class='ctx'> 	FW_QUEUE_RING_RESET = 1,</div><div class='ctx'> 	FW_QUEUE_DPG_HOLD_OFF = 2,</div><div class='hunk'>@@ -279,6 +298,8 @@ struct amdgpu_vcn_fw_shared {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_vcn_inst {</div><div class='add'>+	struct amdgpu_device	*adev;</div><div class='add'>+	int			inst;</div><div class='ctx'> 	struct amdgpu_bo	*vcpu_bo;</div><div class='ctx'> 	void			*cpu_addr;</div><div class='ctx'> 	uint64_t		gpu_addr;</div><div class='hunk'>@@ -297,6 +318,25 @@ struct amdgpu_vcn_inst {</div><div class='ctx'> 	atomic_t		dpg_enc_submission_cnt;</div><div class='ctx'> 	struct amdgpu_vcn_fw_shared fw_shared;</div><div class='ctx'> 	uint8_t			aid_id;</div><div class='add'>+	const struct firmware	*fw; /* VCN firmware */</div><div class='add'>+	uint8_t			vcn_config;</div><div class='add'>+	uint32_t		vcn_codec_disable_mask;</div><div class='add'>+	atomic_t		total_submission_cnt;</div><div class='add'>+	struct mutex		vcn_pg_lock;</div><div class='add'>+	enum amd_powergating_state cur_state;</div><div class='add'>+	struct delayed_work	idle_work;</div><div class='add'>+	unsigned		fw_version;</div><div class='add'>+	unsigned		num_enc_rings;</div><div class='add'>+	bool			indirect_sram;</div><div class='add'>+	struct amdgpu_vcn_reg	 internal;</div><div class='add'>+	struct mutex		vcn1_jpeg1_workaround;</div><div class='add'>+	int (*pause_dpg_mode)(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+			      struct dpg_pause_state *new_state);</div><div class='add'>+	int (*set_pg_state)(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+			    enum amd_powergating_state state);</div><div class='add'>+	int (*reset)(struct amdgpu_vcn_inst *vinst);</div><div class='add'>+	bool using_unified_queue;</div><div class='add'>+	struct mutex		engine_reset_mutex;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_vcn_ras {</div><div class='hunk'>@@ -304,31 +344,30 @@ struct amdgpu_vcn_ras {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_vcn {</div><div class='del'>-	unsigned		fw_version;</div><div class='del'>-	struct delayed_work	idle_work;</div><div class='del'>-	const struct firmware	*fw[AMDGPU_MAX_VCN_INSTANCES];	/* VCN firmware */</div><div class='del'>-	unsigned		num_enc_rings;</div><div class='del'>-	enum amd_powergating_state cur_state;</div><div class='del'>-	bool			indirect_sram;</div><div class='del'>-</div><div class='ctx'> 	uint8_t	num_vcn_inst;</div><div class='ctx'> 	struct amdgpu_vcn_inst	 inst[AMDGPU_MAX_VCN_INSTANCES];</div><div class='del'>-	uint8_t			 vcn_config[AMDGPU_MAX_VCN_INSTANCES];</div><div class='del'>-	uint32_t		 vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];</div><div class='del'>-	struct amdgpu_vcn_reg	 internal;</div><div class='del'>-	struct mutex		 vcn_pg_lock;</div><div class='del'>-	struct mutex		vcn1_jpeg1_workaround;</div><div class='del'>-	atomic_t		 total_submission_cnt;</div><div class='ctx'> </div><div class='ctx'> 	unsigned	harvest_config;</div><div class='del'>-	int (*pause_dpg_mode)(struct amdgpu_device *adev,</div><div class='del'>-		int inst_idx, struct dpg_pause_state *new_state);</div><div class='ctx'> </div><div class='ctx'> 	struct ras_common_if    *ras_if;</div><div class='ctx'> 	struct amdgpu_vcn_ras   *ras;</div><div class='ctx'> </div><div class='ctx'> 	uint16_t inst_mask;</div><div class='ctx'> 	uint8_t	num_inst_per_aid;</div><div class='add'>+</div><div class='add'>+	/* IP reg dump */</div><div class='add'>+	uint32_t		*ip_dump;</div><div class='add'>+</div><div class='add'>+	uint32_t		supported_reset;</div><div class='add'>+	uint32_t		caps;</div><div class='add'>+</div><div class='add'>+	bool			per_inst_fw;</div><div class='add'>+	unsigned		fw_version;</div><div class='add'>+</div><div class='add'>+	bool			workload_profile_active;</div><div class='add'>+	struct mutex            workload_profile_mutex;</div><div class='add'>+	u32 reg_count;</div><div class='add'>+	const struct amdgpu_hwip_reg_entry *reg_list;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_fw_shared_rb_ptrs_struct {</div><div class='hunk'>@@ -454,6 +493,19 @@ struct amdgpu_vcn_rb_metadata {</div><div class='ctx'> 	uint8_t pad[26];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_vcn5_fw_shared {</div><div class='add'>+	uint32_t present_flag_0;</div><div class='add'>+	uint8_t pad[12];</div><div class='add'>+	struct amdgpu_fw_shared_unified_queue_struct sq;</div><div class='add'>+	uint8_t pad1[8];</div><div class='add'>+	struct amdgpu_fw_shared_fw_logging fw_log;</div><div class='add'>+	uint8_t pad2[20];</div><div class='add'>+	struct amdgpu_fw_shared_rb_setup rb_setup;</div><div class='add'>+	struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;</div><div class='add'>+	struct amdgpu_fw_shared_drm_key_wa drm_key_wa;</div><div class='add'>+	uint8_t pad3[404];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80</div><div class='ctx'> #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40</div><div class='ctx'> #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0</div><div class='hunk'>@@ -464,11 +516,11 @@ enum vcn_ring_type {</div><div class='ctx'> 	VCN_UNIFIED_RING,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int amdgpu_vcn_early_init(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_vcn_sw_init(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_vcn_suspend(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_vcn_resume(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i);</div><div class='add'>+int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i);</div><div class='add'>+void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i);</div><div class='add'>+int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i);</div><div class='add'>+int amdgpu_vcn_resume(struct amdgpu_device *adev, int i);</div><div class='ctx'> void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);</div><div class='ctx'> void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='hunk'>@@ -486,7 +538,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);</div><div class='ctx'> </div><div class='ctx'> enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);</div><div class='ctx'> </div><div class='del'>-void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);</div><div class='ctx'> void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,</div><div class='hunk'>@@ -501,5 +553,21 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,</div><div class='ctx'> 			       enum AMDGPU_UCODE_ID ucode_id);</div><div class='add'>+int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+			      enum amd_powergating_state state);</div><div class='add'>+int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+			  unsigned int vmid,</div><div class='add'>+			  struct amdgpu_fence *guilty_fence);</div><div class='add'>+int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev,</div><div class='add'>+			     const struct amdgpu_hwip_reg_entry *reg, u32 count);</div><div class='add'>+void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block);</div><div class='add'>+void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p);</div><div class='add'>+void amdgpu_vcn_get_profile(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_vcn_put_profile(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br/>index 7a4eae36778a..47a6ce4fdc74 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c</a></div><div class='hunk'>@@ -32,6 +32,8 @@</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='add'>+#include "amdgpu_dpm.h"</div><div class='ctx'> #include "vi.h"</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "nv.h"</div><div class='hunk'>@@ -42,6 +44,18 @@</div><div class='ctx'> 		vf2pf_info-&gt;ucode_info[ucode].version = ver; \</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='add'>+#define mmRCC_CONFIG_MEMSIZE    0xde3</div><div class='add'>+</div><div class='add'>+const char *amdgpu_virt_dynamic_crit_table_name[] = {</div><div class='add'>+	"IP DISCOVERY",</div><div class='add'>+	"VBIOS IMG",</div><div class='add'>+	"RAS TELEMETRY",</div><div class='add'>+	"DATA EXCHANGE",</div><div class='add'>+	"BAD PAGE INFO",</div><div class='add'>+	"INIT HEADER",</div><div class='add'>+	"LAST",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	/* By now all MMIO pages except mailbox are blocked */</div><div class='hunk'>@@ -85,8 +99,10 @@ int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)</div><div class='ctx'> </div><div class='ctx'> 	if (virt-&gt;ops &amp;&amp; virt-&gt;ops-&gt;req_full_gpu) {</div><div class='ctx'> 		r = virt-&gt;ops-&gt;req_full_gpu(adev, init);</div><div class='del'>-		if (r)</div><div class='add'>+		if (r) {</div><div class='add'>+			adev-&gt;no_hw_access = true;</div><div class='ctx'> 			return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;virt.caps &amp;= ~AMDGPU_SRIOV_CAPS_RUNTIME;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -146,9 +162,24 @@ void amdgpu_virt_request_init_data(struct amdgpu_device *adev)</div><div class='ctx'> 		virt-&gt;ops-&gt;req_init_data(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;virt.req_init_data_ver &gt; 0)</div><div class='del'>-		DRM_INFO("host supports REQ_INIT_DATA handshake\n");</div><div class='add'>+		dev_info(adev-&gt;dev, "host supports REQ_INIT_DATA handshake of critical_region_version %d\n",</div><div class='add'>+				 adev-&gt;virt.req_init_data_ver);</div><div class='ctx'> 	else</div><div class='del'>-		DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");</div><div class='add'>+		dev_warn(adev-&gt;dev, "host doesn't support REQ_INIT_DATA handshake\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_virt_ready_to_reset() - send ready to reset to host</div><div class='add'>+ * @adev:	amdgpu device.</div><div class='add'>+ * Send ready to reset message to GPU hypervisor to signal we have stopped GPU</div><div class='add'>+ * activity and is ready for host FLR</div><div class='add'>+ */</div><div class='add'>+void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+</div><div class='add'>+	if (virt-&gt;ops &amp;&amp; virt-&gt;ops-&gt;reset_gpu)</div><div class='add'>+		virt-&gt;ops-&gt;ready_to_reset(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -187,12 +218,12 @@ int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)</div><div class='ctx'> 				    &amp;adev-&gt;virt.mm_table.gpu_addr,</div><div class='ctx'> 				    (void *)&amp;adev-&gt;virt.mm_table.cpu_addr);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("failed to alloc mm table and error = %d.\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to alloc mm table and error = %d.\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memset((void *)adev-&gt;virt.mm_table.cpu_addr, 0, PAGE_SIZE);</div><div class='del'>-	DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",</div><div class='add'>+	dev_info(adev-&gt;dev, "MM table gpu addr = 0x%llx, cpu addr = %p.\n",</div><div class='ctx'> 		 adev-&gt;virt.mm_table.gpu_addr,</div><div class='ctx'> 		 adev-&gt;virt.mm_table.cpu_addr);</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -214,6 +245,22 @@ void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;virt.mm_table.gpu_addr = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt</div><div class='add'>+ * @adev:	amdgpu device.</div><div class='add'>+ * Check whether host sent RAS error message</div><div class='add'>+ * Return: true if found, otherwise false</div><div class='add'>+ */</div><div class='add'>+bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+</div><div class='add'>+	if (!virt-&gt;ops || !virt-&gt;ops-&gt;rcvd_ras_intr)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return virt-&gt;ops-&gt;rcvd_ras_intr(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> unsigned int amd_sriov_msg_checksum(void *obj,</div><div class='ctx'> 				unsigned long obj_size,</div><div class='hunk'>@@ -356,7 +403,9 @@ static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)</div><div class='ctx'> 			if (amdgpu_bo_create_kernel_at(adev, bp &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='ctx'> 							AMDGPU_GPU_PAGE_SIZE,</div><div class='ctx'> 							&amp;bo, NULL))</div><div class='del'>-				DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);</div><div class='add'>+				dev_dbg(adev-&gt;dev,</div><div class='add'>+						"RAS WARN: reserve vram for retired page %llx fail\n",</div><div class='add'>+						bp);</div><div class='ctx'> 			data-&gt;bps_bo[i] = bo;</div><div class='ctx'> 		}</div><div class='ctx'> 		data-&gt;last_reserved = i + 1;</div><div class='hunk'>@@ -394,6 +443,8 @@ static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,</div><div class='ctx'> 	else</div><div class='ctx'> 		vram_usage_va = adev-&gt;mman.drv_vram_usage_va;</div><div class='ctx'> </div><div class='add'>+	memset(&amp;bp, 0, sizeof(bp));</div><div class='add'>+</div><div class='ctx'> 	if (bp_block_size) {</div><div class='ctx'> 		bp_cnt = bp_block_size / sizeof(uint64_t);</div><div class='ctx'> 		for (bp_idx = 0; bp_idx &lt; bp_cnt; bp_idx++) {</div><div class='hunk'>@@ -424,7 +475,7 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (pf2vf_info-&gt;size &gt; 1024) {</div><div class='del'>-		DRM_ERROR("invalid pf2vf message size\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info-&gt;size);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -435,7 +486,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;virt.fw_reserve.p_pf2vf, pf2vf_info-&gt;size,</div><div class='ctx'> 			adev-&gt;virt.fw_reserve.checksum_key, checksum);</div><div class='ctx'> 		if (checksum != checkval) {</div><div class='del'>-			DRM_ERROR("invalid pf2vf message\n");</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n",</div><div class='add'>+				checksum, checkval);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -449,7 +502,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;virt.fw_reserve.p_pf2vf, pf2vf_info-&gt;size,</div><div class='ctx'> 			0, checksum);</div><div class='ctx'> 		if (checksum != checkval) {</div><div class='del'>-			DRM_ERROR("invalid pf2vf message\n");</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"invalid pf2vf message: header checksum=0x%x calculated checksum=0x%x\n",</div><div class='add'>+				checksum, checkval);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -483,9 +538,12 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;unique_id =</div><div class='ctx'> 			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)-&gt;uuid;</div><div class='add'>+		adev-&gt;virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)-&gt;ras_en_caps.all;</div><div class='add'>+		adev-&gt;virt.ras_telemetry_en_caps.all =</div><div class='add'>+			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)-&gt;ras_telemetry_en_caps.all;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		DRM_ERROR("invalid pf2vf version\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "invalid pf2vf version: 0x%x\n", pf2vf_info-&gt;version);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -555,8 +613,8 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)</div><div class='ctx'> 	vf2pf_info-&gt;driver_cert = 0;</div><div class='ctx'> 	vf2pf_info-&gt;os_info.all = 0;</div><div class='ctx'> </div><div class='del'>-	vf2pf_info-&gt;fb_usage =</div><div class='del'>-		ttm_resource_manager_usage(&amp;adev-&gt;mman.vram_mgr.manager) &gt;&gt; 20;</div><div class='add'>+	vf2pf_info-&gt;fb_usage = ttm_resource_manager_used(&amp;adev-&gt;mman.vram_mgr.manager) ?</div><div class='add'>+		 ttm_resource_manager_usage(&amp;adev-&gt;mman.vram_mgr.manager) &gt;&gt; 20 : 0;</div><div class='ctx'> 	vf2pf_info-&gt;fb_vis_usage =</div><div class='ctx'> 		amdgpu_vram_mgr_vis_usage(&amp;adev-&gt;mman.vram_mgr) &gt;&gt; 20;</div><div class='ctx'> 	vf2pf_info-&gt;fb_size = adev-&gt;gmc.real_vram_size &gt;&gt; 20;</div><div class='hunk'>@@ -571,9 +629,15 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)</div><div class='ctx'> 	vf2pf_info-&gt;decode_usage = 0;</div><div class='ctx'> </div><div class='ctx'> 	vf2pf_info-&gt;dummy_page_addr = (uint64_t)adev-&gt;dummy_page_addr;</div><div class='add'>+	if (amdgpu_sriov_is_mes_info_enable(adev)) {</div><div class='add'>+		vf2pf_info-&gt;mes_info_addr =</div><div class='add'>+			(uint64_t)(adev-&gt;mes.resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE);</div><div class='add'>+		vf2pf_info-&gt;mes_info_size =</div><div class='add'>+			adev-&gt;mes.resource_1[0]-&gt;tbo.base.size - AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	}</div><div class='ctx'> 	vf2pf_info-&gt;checksum =</div><div class='ctx'> 		amd_sriov_msg_checksum(</div><div class='del'>-		vf2pf_info, vf2pf_info-&gt;header.size, 0, 0);</div><div class='add'>+		vf2pf_info, sizeof(*vf2pf_info), 0, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -584,18 +648,59 @@ static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_virt_read_pf2vf_data(adev);</div><div class='del'>-	if (ret)</div><div class='add'>+	if (ret) {</div><div class='add'>+		adev-&gt;virt.vf2pf_update_retry_cnt++;</div><div class='add'>+</div><div class='add'>+		if ((amdgpu_virt_rcvd_ras_interrupt(adev) ||</div><div class='add'>+			adev-&gt;virt.vf2pf_update_retry_cnt &gt;= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) &amp;&amp;</div><div class='add'>+			amdgpu_sriov_runtime(adev)) {</div><div class='add'>+</div><div class='add'>+			amdgpu_ras_set_fed(adev, true);</div><div class='add'>+			if (amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='add'>+							&amp;adev-&gt;kfd.reset_work))</div><div class='add'>+				return;</div><div class='add'>+			else</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to queue work! at %s", __func__);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;virt.vf2pf_update_retry_cnt = 0;</div><div class='ctx'> 	amdgpu_virt_write_vf2pf_data(adev);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	schedule_delayed_work(&amp;(adev-&gt;virt.vf2pf_work), adev-&gt;virt.vf2pf_update_interval_ms);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_virt_read_exchange_data_from_mem(struct amdgpu_device *adev, uint32_t *pfvf_data)</div><div class='add'>+{</div><div class='add'>+	uint32_t dataexchange_offset =</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset;</div><div class='add'>+	uint32_t dataexchange_size =</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb &lt;&lt; 10;</div><div class='add'>+	uint64_t pos = 0;</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev,</div><div class='add'>+			"Got data exchange info from dynamic crit_region_table at offset 0x%x with size of 0x%x bytes.\n",</div><div class='add'>+			dataexchange_offset, dataexchange_size);</div><div class='add'>+</div><div class='add'>+	if (!IS_ALIGNED(dataexchange_offset, 4) || !IS_ALIGNED(dataexchange_size, 4)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Data exchange data not aligned to 4 bytes\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pos = (uint64_t)dataexchange_offset;</div><div class='add'>+	amdgpu_device_vram_access(adev, pos, pfvf_data,</div><div class='add'>+			dataexchange_size, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (adev-&gt;virt.vf2pf_update_interval_ms != 0) {</div><div class='del'>-		DRM_INFO("clean up the vf2pf work item\n");</div><div class='add'>+		dev_info(adev-&gt;dev, "clean up the vf2pf work item\n");</div><div class='ctx'> 		cancel_delayed_work_sync(&amp;adev-&gt;virt.vf2pf_work);</div><div class='ctx'> 		adev-&gt;virt.vf2pf_update_interval_ms = 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -603,12 +708,15 @@ void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint32_t *pfvf_data = NULL;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;virt.fw_reserve.p_pf2vf = NULL;</div><div class='ctx'> 	adev-&gt;virt.fw_reserve.p_vf2pf = NULL;</div><div class='ctx'> 	adev-&gt;virt.vf2pf_update_interval_ms = 0;</div><div class='add'>+	adev-&gt;virt.vf2pf_update_retry_cnt = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;mman.fw_vram_usage_va &amp;&amp; adev-&gt;mman.drv_vram_usage_va) {</div><div class='del'>-		DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!");</div><div class='add'>+		dev_warn(adev-&gt;dev, "Currently fw_vram and drv_vram should not have values at the same time!");</div><div class='ctx'> 	} else if (adev-&gt;mman.fw_vram_usage_va || adev-&gt;mman.drv_vram_usage_va) {</div><div class='ctx'> 		/* go through this logic in ip_init and reset to init workqueue*/</div><div class='ctx'> 		amdgpu_virt_exchange_data(adev);</div><div class='hunk'>@@ -617,11 +725,34 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)</div><div class='ctx'> 		schedule_delayed_work(&amp;(adev-&gt;virt.vf2pf_work), msecs_to_jiffies(adev-&gt;virt.vf2pf_update_interval_ms));</div><div class='ctx'> 	} else if (adev-&gt;bios != NULL) {</div><div class='ctx'> 		/* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/</div><div class='del'>-		adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='del'>-			(struct amd_sriov_msg_pf2vf_info_header *)</div><div class='del'>-			(adev-&gt;bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB &lt;&lt; 10));</div><div class='add'>+		if (adev-&gt;virt.req_init_data_ver == GPU_CRIT_REGION_V2) {</div><div class='add'>+			pfvf_data =</div><div class='add'>+				kzalloc(adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb &lt;&lt; 10,</div><div class='add'>+					GFP_KERNEL);</div><div class='add'>+			if (!pfvf_data) {</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to allocate memory for pfvf_data\n");</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='ctx'> </div><div class='del'>-		amdgpu_virt_read_pf2vf_data(adev);</div><div class='add'>+			if (amdgpu_virt_read_exchange_data_from_mem(adev, pfvf_data))</div><div class='add'>+				goto free_pfvf_data;</div><div class='add'>+</div><div class='add'>+			adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='add'>+				(struct amd_sriov_msg_pf2vf_info_header *)pfvf_data;</div><div class='add'>+</div><div class='add'>+			amdgpu_virt_read_pf2vf_data(adev);</div><div class='add'>+</div><div class='add'>+free_pfvf_data:</div><div class='add'>+			kfree(pfvf_data);</div><div class='add'>+			pfvf_data = NULL;</div><div class='add'>+			adev-&gt;virt.fw_reserve.p_pf2vf = NULL;</div><div class='add'>+		} else {</div><div class='add'>+			adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='add'>+				(struct amd_sriov_msg_pf2vf_info_header *)</div><div class='add'>+				(adev-&gt;bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='add'>+</div><div class='add'>+			amdgpu_virt_read_pf2vf_data(adev);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -634,19 +765,38 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;mman.fw_vram_usage_va || adev-&gt;mman.drv_vram_usage_va) {</div><div class='ctx'> 		if (adev-&gt;mman.fw_vram_usage_va) {</div><div class='del'>-			adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='del'>-				(struct amd_sriov_msg_pf2vf_info_header *)</div><div class='del'>-				(adev-&gt;mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB &lt;&lt; 10));</div><div class='del'>-			adev-&gt;virt.fw_reserve.p_vf2pf =</div><div class='del'>-				(struct amd_sriov_msg_vf2pf_info_header *)</div><div class='del'>-				(adev-&gt;mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB &lt;&lt; 10));</div><div class='add'>+			if (adev-&gt;virt.req_init_data_ver == GPU_CRIT_REGION_V2) {</div><div class='add'>+				adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='add'>+					(struct amd_sriov_msg_pf2vf_info_header *)</div><div class='add'>+					(adev-&gt;mman.fw_vram_usage_va +</div><div class='add'>+					adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset);</div><div class='add'>+				adev-&gt;virt.fw_reserve.p_vf2pf =</div><div class='add'>+					(struct amd_sriov_msg_vf2pf_info_header *)</div><div class='add'>+					(adev-&gt;mman.fw_vram_usage_va +</div><div class='add'>+					adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset +</div><div class='add'>+					(AMD_SRIOV_MSG_SIZE_KB &lt;&lt; 10));</div><div class='add'>+				adev-&gt;virt.fw_reserve.ras_telemetry =</div><div class='add'>+					(adev-&gt;mman.fw_vram_usage_va +</div><div class='add'>+					adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset);</div><div class='add'>+			} else {</div><div class='add'>+				adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='add'>+					(struct amd_sriov_msg_pf2vf_info_header *)</div><div class='add'>+					(adev-&gt;mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='add'>+				adev-&gt;virt.fw_reserve.p_vf2pf =</div><div class='add'>+					(struct amd_sriov_msg_vf2pf_info_header *)</div><div class='add'>+					(adev-&gt;mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='add'>+				adev-&gt;virt.fw_reserve.ras_telemetry =</div><div class='add'>+					(adev-&gt;mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='add'>+			}</div><div class='ctx'> 		} else if (adev-&gt;mman.drv_vram_usage_va) {</div><div class='ctx'> 			adev-&gt;virt.fw_reserve.p_pf2vf =</div><div class='ctx'> 				(struct amd_sriov_msg_pf2vf_info_header *)</div><div class='del'>-				(adev-&gt;mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB &lt;&lt; 10));</div><div class='add'>+				(adev-&gt;mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='ctx'> 			adev-&gt;virt.fw_reserve.p_vf2pf =</div><div class='ctx'> 				(struct amd_sriov_msg_vf2pf_info_header *)</div><div class='del'>-				(adev-&gt;mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB &lt;&lt; 10));</div><div class='add'>+				(adev-&gt;mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='add'>+			adev-&gt;virt.fw_reserve.ras_telemetry =</div><div class='add'>+				(adev-&gt;mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 &lt;&lt; 10));</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_virt_read_pf2vf_data(adev);</div><div class='hunk'>@@ -669,7 +819,7 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_detect_virtualization(struct amdgpu_device *adev)</div><div class='add'>+static u32 amdgpu_virt_init_detect_asic(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t reg;</div><div class='ctx'> </div><div class='hunk'>@@ -705,14 +855,17 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;virt.caps |= AMDGPU_PASSTHROUGH_MODE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;asic_type == CHIP_SIENNA_CICHLID)</div><div class='del'>-		/* VF MMIO access (except mailbox range) from CPU</div><div class='del'>-		 * will be blocked during sriov runtime</div><div class='del'>-		 */</div><div class='del'>-		adev-&gt;virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg)</div><div class='add'>+{</div><div class='add'>+	bool is_sriov = false;</div><div class='ctx'> </div><div class='ctx'> 	/* we have the ability to check now */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		is_sriov = true;</div><div class='add'>+</div><div class='ctx'> 		switch (adev-&gt;asic_type) {</div><div class='ctx'> 		case CHIP_TONGA:</div><div class='ctx'> 		case CHIP_FIJI:</div><div class='hunk'>@@ -741,10 +894,252 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_virt_request_init_data(adev);</div><div class='ctx'> 			break;</div><div class='ctx'> 		default: /* other chip doesn't support SRIOV */</div><div class='del'>-			DRM_ERROR("Unknown asic type: %d!\n", adev-&gt;asic_type);</div><div class='add'>+			is_sriov = false;</div><div class='add'>+			dev_err(adev-&gt;dev, "Unknown asic type: %d!\n", adev-&gt;asic_type);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return is_sriov;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_virt_init_ras(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	ratelimit_state_init(&amp;adev-&gt;virt.ras.ras_error_cnt_rs, 5 * HZ, 1);</div><div class='add'>+	ratelimit_state_init(&amp;adev-&gt;virt.ras.ras_cper_dump_rs, 5 * HZ, 1);</div><div class='add'>+	ratelimit_state_init(&amp;adev-&gt;virt.ras.ras_chk_criti_rs, 5 * HZ, 1);</div><div class='add'>+</div><div class='add'>+	ratelimit_set_flags(&amp;adev-&gt;virt.ras.ras_error_cnt_rs,</div><div class='add'>+			    RATELIMIT_MSG_ON_RELEASE);</div><div class='add'>+	ratelimit_set_flags(&amp;adev-&gt;virt.ras.ras_cper_dump_rs,</div><div class='add'>+			    RATELIMIT_MSG_ON_RELEASE);</div><div class='add'>+	ratelimit_set_flags(&amp;adev-&gt;virt.ras.ras_chk_criti_rs,</div><div class='add'>+			    RATELIMIT_MSG_ON_RELEASE);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;adev-&gt;virt.ras.ras_telemetry_mutex);</div><div class='add'>+	mutex_init(&amp;adev-&gt;virt.access_req_mutex);</div><div class='add'>+</div><div class='add'>+	adev-&gt;virt.ras.cper_rptr = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint8_t amdgpu_virt_crit_region_calc_checksum(uint8_t *buf_start, uint8_t *buf_end)</div><div class='add'>+{</div><div class='add'>+	uint32_t sum = 0;</div><div class='add'>+</div><div class='add'>+	if (buf_start &gt;= buf_end)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (; buf_start &lt; buf_end; buf_start++)</div><div class='add'>+		sum += buf_start[0];</div><div class='add'>+</div><div class='add'>+	return 0xffffffff - sum;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_virt_init_critical_region(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amd_sriov_msg_init_data_header *init_data_hdr = NULL;</div><div class='add'>+	u64 init_hdr_offset = adev-&gt;virt.init_data_header.offset;</div><div class='add'>+	u64 init_hdr_size = (u64)adev-&gt;virt.init_data_header.size_kb &lt;&lt; 10; /* KB → bytes */</div><div class='add'>+	u64 vram_size;</div><div class='add'>+	u64 end;</div><div class='add'>+	int r = 0;</div><div class='add'>+	uint8_t checksum = 0;</div><div class='add'>+</div><div class='add'>+	/* Skip below init if critical region version != v2 */</div><div class='add'>+	if (adev-&gt;virt.req_init_data_ver != GPU_CRIT_REGION_V2)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (init_hdr_offset &lt; 0) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Invalid init header offset\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);</div><div class='add'>+	if (!vram_size || vram_size == U32_MAX)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	vram_size &lt;&lt;= 20;</div><div class='add'>+</div><div class='add'>+	if (check_add_overflow(init_hdr_offset, init_hdr_size, &amp;end) || end &gt; vram_size) {</div><div class='add'>+		dev_err(adev-&gt;dev, "init_data_header exceeds VRAM size, exiting\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate for init_data_hdr */</div><div class='add'>+	init_data_hdr = kzalloc(sizeof(struct amd_sriov_msg_init_data_header), GFP_KERNEL);</div><div class='add'>+	if (!init_data_hdr)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	amdgpu_device_vram_access(adev, (uint64_t)init_hdr_offset, (uint32_t *)init_data_hdr,</div><div class='add'>+					sizeof(struct amd_sriov_msg_init_data_header), false);</div><div class='add'>+</div><div class='add'>+	/* Table validation */</div><div class='add'>+	if (strncmp(init_data_hdr-&gt;signature,</div><div class='add'>+				AMDGPU_SRIOV_CRIT_DATA_SIGNATURE,</div><div class='add'>+				AMDGPU_SRIOV_CRIT_DATA_SIG_LEN) != 0) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Invalid init data signature: %.4s\n",</div><div class='add'>+			init_data_hdr-&gt;signature);</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	checksum = amdgpu_virt_crit_region_calc_checksum(</div><div class='add'>+			(uint8_t *)&amp;init_data_hdr-&gt;initdata_offset,</div><div class='add'>+			(uint8_t *)init_data_hdr +</div><div class='add'>+			sizeof(struct amd_sriov_msg_init_data_header));</div><div class='add'>+	if (checksum != init_data_hdr-&gt;checksum) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Found unmatching checksum from calculation 0x%x and init_data 0x%x\n",</div><div class='add'>+				checksum, init_data_hdr-&gt;checksum);</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(&amp;adev-&gt;virt.crit_regn, 0, sizeof(adev-&gt;virt.crit_regn));</div><div class='add'>+	memset(adev-&gt;virt.crit_regn_tbl, 0, sizeof(adev-&gt;virt.crit_regn_tbl));</div><div class='add'>+</div><div class='add'>+	adev-&gt;virt.crit_regn.offset = init_data_hdr-&gt;initdata_offset;</div><div class='add'>+	adev-&gt;virt.crit_regn.size_kb = init_data_hdr-&gt;initdata_size_in_kb;</div><div class='add'>+</div><div class='add'>+	/* Validation and initialization for each table entry */</div><div class='add'>+	if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_IPD_TABLE_ID)) {</div><div class='add'>+		if (!init_data_hdr-&gt;ip_discovery_size_in_kb ||</div><div class='add'>+				init_data_hdr-&gt;ip_discovery_size_in_kb &gt; DISCOVERY_TMR_SIZE) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid %s size: 0x%x\n",</div><div class='add'>+				amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_IPD_TABLE_ID],</div><div class='add'>+				init_data_hdr-&gt;ip_discovery_size_in_kb);</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset =</div><div class='add'>+			init_data_hdr-&gt;ip_discovery_offset;</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb =</div><div class='add'>+			init_data_hdr-&gt;ip_discovery_size_in_kb;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID)) {</div><div class='add'>+		if (!init_data_hdr-&gt;vbios_img_size_in_kb) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid %s size: 0x%x\n",</div><div class='add'>+				amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID],</div><div class='add'>+				init_data_hdr-&gt;vbios_img_size_in_kb);</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].offset =</div><div class='add'>+			init_data_hdr-&gt;vbios_img_offset;</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].size_kb =</div><div class='add'>+			init_data_hdr-&gt;vbios_img_size_in_kb;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID)) {</div><div class='add'>+		if (!init_data_hdr-&gt;ras_tele_info_size_in_kb) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid %s size: 0x%x\n",</div><div class='add'>+				amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID],</div><div class='add'>+				init_data_hdr-&gt;ras_tele_info_size_in_kb);</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset =</div><div class='add'>+			init_data_hdr-&gt;ras_tele_info_offset;</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].size_kb =</div><div class='add'>+			init_data_hdr-&gt;ras_tele_info_size_in_kb;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID)) {</div><div class='add'>+		if (!init_data_hdr-&gt;dataexchange_size_in_kb) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid %s size: 0x%x\n",</div><div class='add'>+				amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID],</div><div class='add'>+				init_data_hdr-&gt;dataexchange_size_in_kb);</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset =</div><div class='add'>+			init_data_hdr-&gt;dataexchange_offset;</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb =</div><div class='add'>+			init_data_hdr-&gt;dataexchange_size_in_kb;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID)) {</div><div class='add'>+		if (!init_data_hdr-&gt;bad_page_size_in_kb) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid %s size: 0x%x\n",</div><div class='add'>+				amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID],</div><div class='add'>+				init_data_hdr-&gt;bad_page_size_in_kb);</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].offset =</div><div class='add'>+			init_data_hdr-&gt;bad_page_info_offset;</div><div class='add'>+		adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].size_kb =</div><div class='add'>+			init_data_hdr-&gt;bad_page_size_in_kb;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Validation for critical region info */</div><div class='add'>+	if (adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb &gt; DISCOVERY_TMR_SIZE) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Invalid IP discovery size: 0x%x\n",</div><div class='add'>+				adev-&gt;virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb);</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* reserved memory starts from crit region base offset with the size of 5MB */</div><div class='add'>+	adev-&gt;mman.fw_vram_usage_start_offset = adev-&gt;virt.crit_regn.offset;</div><div class='add'>+	adev-&gt;mman.fw_vram_usage_size = adev-&gt;virt.crit_regn.size_kb &lt;&lt; 10;</div><div class='add'>+	dev_info(adev-&gt;dev,</div><div class='add'>+		"critical region v%d requested to reserve memory start at %08llx with %llu KB.\n",</div><div class='add'>+			init_data_hdr-&gt;version,</div><div class='add'>+			adev-&gt;mman.fw_vram_usage_start_offset,</div><div class='add'>+			adev-&gt;mman.fw_vram_usage_size &gt;&gt; 10);</div><div class='add'>+</div><div class='add'>+	adev-&gt;virt.is_dynamic_crit_regn_enabled = true;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(init_data_hdr);</div><div class='add'>+	init_data_hdr = NULL;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev,</div><div class='add'>+	int data_id, uint8_t *binary, u32 *size)</div><div class='add'>+{</div><div class='add'>+	uint32_t data_offset = 0;</div><div class='add'>+	uint32_t data_size = 0;</div><div class='add'>+	enum amd_sriov_msg_table_id_enum data_table_id = data_id;</div><div class='add'>+</div><div class='add'>+	if (data_table_id &gt;= AMD_SRIOV_MSG_MAX_TABLE_ID)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	data_offset = adev-&gt;virt.crit_regn_tbl[data_table_id].offset;</div><div class='add'>+	data_size = adev-&gt;virt.crit_regn_tbl[data_table_id].size_kb &lt;&lt; 10;</div><div class='add'>+</div><div class='add'>+	/* Validate on input params */</div><div class='add'>+	if (!binary || !size || *size &lt; (uint64_t)data_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Proceed to copy the dynamic content */</div><div class='add'>+	amdgpu_device_vram_access(adev,</div><div class='add'>+			(uint64_t)data_offset, (uint32_t *)binary, data_size, false);</div><div class='add'>+	*size = (uint64_t)data_size;</div><div class='add'>+</div><div class='add'>+	dev_dbg(adev-&gt;dev,</div><div class='add'>+		"Got %s info from dynamic crit_region_table at offset 0x%x with size of 0x%x bytes.\n",</div><div class='add'>+		amdgpu_virt_dynamic_crit_table_name[data_id], data_offset, data_size);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_virt_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	bool is_sriov = false;</div><div class='add'>+	uint32_t reg = amdgpu_virt_init_detect_asic(adev);</div><div class='add'>+</div><div class='add'>+	is_sriov = amdgpu_virt_init_req_data(adev, reg);</div><div class='add'>+</div><div class='add'>+	if (is_sriov)</div><div class='add'>+		amdgpu_virt_init_ras(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)</div><div class='hunk'>@@ -793,6 +1188,13 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad</div><div class='ctx'> 	return mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_virt_pre_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* stop the data exchange thread */</div><div class='add'>+	amdgpu_virt_fini_data_exchange(adev);</div><div class='add'>+	amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void amdgpu_virt_post_reset(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) {</div><div class='hunk'>@@ -801,6 +1203,8 @@ void amdgpu_virt_post_reset(struct amdgpu_device *adev)</div><div class='ctx'> 		 */</div><div class='ctx'> 		adev-&gt;gfx.is_poweron = false;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;mes.ring[0].sched.ready = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)</div><div class='hunk'>@@ -944,6 +1348,7 @@ u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 f</div><div class='ctx'> 	void *scratch_reg2;</div><div class='ctx'> 	void *scratch_reg3;</div><div class='ctx'> 	void *spare_int;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;gfx.rlc.rlcg_reg_access_supported) {</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='hunk'>@@ -956,11 +1361,17 @@ u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 f</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_device_skip_hw_access(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	reg_access_ctrl = &amp;adev-&gt;gfx.rlc.reg_access_ctrl[xcc_id];</div><div class='ctx'> 	scratch_reg0 = (void __iomem *)adev-&gt;rmmio + 4 * reg_access_ctrl-&gt;scratch_reg0;</div><div class='ctx'> 	scratch_reg1 = (void __iomem *)adev-&gt;rmmio + 4 * reg_access_ctrl-&gt;scratch_reg1;</div><div class='ctx'> 	scratch_reg2 = (void __iomem *)adev-&gt;rmmio + 4 * reg_access_ctrl-&gt;scratch_reg2;</div><div class='ctx'> 	scratch_reg3 = (void __iomem *)adev-&gt;rmmio + 4 * reg_access_ctrl-&gt;scratch_reg3;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;adev-&gt;virt.rlcg_reg_lock, flags);</div><div class='add'>+</div><div class='ctx'> 	if (reg_access_ctrl-&gt;spare_int)</div><div class='ctx'> 		spare_int = (void __iomem *)adev-&gt;rmmio + 4 * reg_access_ctrl-&gt;spare_int;</div><div class='ctx'> </div><div class='hunk'>@@ -1017,6 +1428,9 @@ u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 f</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = readl(scratch_reg0);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;adev-&gt;virt.rlcg_reg_lock, flags);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1026,6 +1440,9 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	u32 rlcg_flag;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_device_skip_hw_access(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (!amdgpu_sriov_runtime(adev) &amp;&amp;</div><div class='ctx'> 		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &amp;rlcg_flag)) {</div><div class='ctx'> 		amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id);</div><div class='hunk'>@@ -1043,6 +1460,9 @@ u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	u32 rlcg_flag;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_device_skip_hw_access(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (!amdgpu_sriov_runtime(adev) &amp;&amp;</div><div class='ctx'> 		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &amp;rlcg_flag))</div><div class='ctx'> 		return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id);</div><div class='hunk'>@@ -1063,3 +1483,365 @@ bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	return xnack_mode;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_ras_caps_en(adev))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_umc)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_sdma)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_gfx)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_mmhub)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_athub)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_pcie_bif)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_hdp)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_xgmi_wafl)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_df)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_smn)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_sem)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_mp0)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_mp1)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_fuse)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_mca)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_vcn)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_jpeg)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_ih)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH);</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.block_mpio)</div><div class='add'>+		adev-&gt;ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;virt.ras_en_caps.bits.poison_propogation_mode)</div><div class='add'>+		con-&gt;poison_supported = true; /* Poison is handled by host */</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline enum amd_sriov_ras_telemetry_gpu_block</div><div class='add'>+amdgpu_ras_block_to_sriov(struct amdgpu_device *adev, enum amdgpu_ras_block block) {</div><div class='add'>+	switch (block) {</div><div class='add'>+	case AMDGPU_RAS_BLOCK__UMC:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_UMC;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__SDMA:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_SDMA;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__GFX:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_GFX;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MMHUB:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_MMHUB;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__ATHUB:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_ATHUB;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__PCIE_BIF:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__HDP:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_HDP;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__XGMI_WAFL:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__DF:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_DF;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__SMN:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_SMN;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__SEM:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_SEM;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MP0:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_MP0;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MP1:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_MP1;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__FUSE:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_FUSE;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MCA:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_MCA;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__VCN:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_VCN;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__JPEG:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_JPEG;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__IH:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_IH;</div><div class='add'>+	case AMDGPU_RAS_BLOCK__MPIO:</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_MPIO;</div><div class='add'>+	default:</div><div class='add'>+		dev_warn(adev-&gt;dev, "Unsupported SRIOV RAS telemetry block 0x%x\n",</div><div class='add'>+			      block);</div><div class='add'>+		return RAS_TELEMETRY_GPU_BLOCK_COUNT;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_virt_cache_host_error_counts(struct amdgpu_device *adev,</div><div class='add'>+					       struct amdsriov_ras_telemetry *host_telemetry)</div><div class='add'>+{</div><div class='add'>+	struct amd_sriov_ras_telemetry_error_count *tmp = NULL;</div><div class='add'>+	uint32_t checksum, used_size;</div><div class='add'>+</div><div class='add'>+	checksum = host_telemetry-&gt;header.checksum;</div><div class='add'>+	used_size = host_telemetry-&gt;header.used_size;</div><div class='add'>+</div><div class='add'>+	if (used_size &gt; (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 &lt;&lt; 10))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	tmp = kmemdup(&amp;host_telemetry-&gt;body.error_count, used_size, GFP_KERNEL);</div><div class='add'>+	if (!tmp)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;adev-&gt;virt.count_cache, tmp,</div><div class='add'>+	       min(used_size, sizeof(adev-&gt;virt.count_cache)));</div><div class='add'>+out:</div><div class='add'>+	kfree(tmp);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_virt_req_ras_err_count_internal(struct amdgpu_device *adev, bool force_update)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+</div><div class='add'>+	if (!virt-&gt;ops || !virt-&gt;ops-&gt;req_ras_err_count)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	/* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host</div><div class='add'>+	 * will ignore incoming guest messages. Ratelimit the guest messages to</div><div class='add'>+	 * prevent guest self DOS.</div><div class='add'>+	 */</div><div class='add'>+	if (__ratelimit(&amp;virt-&gt;ras.ras_error_cnt_rs) || force_update) {</div><div class='add'>+		mutex_lock(&amp;virt-&gt;ras.ras_telemetry_mutex);</div><div class='add'>+		if (!virt-&gt;ops-&gt;req_ras_err_count(adev))</div><div class='add'>+			amdgpu_virt_cache_host_error_counts(adev,</div><div class='add'>+				virt-&gt;fw_reserve.ras_telemetry);</div><div class='add'>+		mutex_unlock(&amp;virt-&gt;ras.ras_telemetry_mutex);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Bypass ACA interface and query ECC counts directly from host */</div><div class='add'>+int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block,</div><div class='add'>+				  struct ras_err_data *err_data)</div><div class='add'>+{</div><div class='add'>+	enum amd_sriov_ras_telemetry_gpu_block sriov_block;</div><div class='add'>+</div><div class='add'>+	sriov_block = amdgpu_ras_block_to_sriov(adev, block);</div><div class='add'>+</div><div class='add'>+	if (sriov_block &gt;= RAS_TELEMETRY_GPU_BLOCK_COUNT ||</div><div class='add'>+	    !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	/* Host Access may be lost during reset, just return last cached data. */</div><div class='add'>+	if (down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_virt_req_ras_err_count_internal(adev, false);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err_data-&gt;ue_count = adev-&gt;virt.count_cache.block[sriov_block].ue_count;</div><div class='add'>+	err_data-&gt;ce_count = adev-&gt;virt.count_cache.block[sriov_block].ce_count;</div><div class='add'>+	err_data-&gt;de_count = adev-&gt;virt.count_cache.block[sriov_block].de_count;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_virt_write_cpers_to_ring(struct amdgpu_device *adev,</div><div class='add'>+				struct amdsriov_ras_telemetry *host_telemetry,</div><div class='add'>+				u32 *more)</div><div class='add'>+{</div><div class='add'>+	struct amd_sriov_ras_cper_dump *cper_dump = NULL;</div><div class='add'>+	struct cper_hdr *entry = NULL;</div><div class='add'>+	struct amdgpu_ring *ring = &amp;adev-&gt;cper.ring_buf;</div><div class='add'>+	uint32_t checksum, used_size, i;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	checksum = host_telemetry-&gt;header.checksum;</div><div class='add'>+	used_size = host_telemetry-&gt;header.used_size;</div><div class='add'>+</div><div class='add'>+	if (used_size &gt; (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 &lt;&lt; 10))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cper_dump = kmemdup(&amp;host_telemetry-&gt;body.cper_dump, used_size, GFP_KERNEL);</div><div class='add'>+	if (!cper_dump)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	if (checksum != amd_sriov_msg_checksum(cper_dump, used_size, 0, 0)) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*more = cper_dump-&gt;more;</div><div class='add'>+</div><div class='add'>+	if (cper_dump-&gt;wptr &lt; adev-&gt;virt.ras.cper_rptr) {</div><div class='add'>+		dev_warn(</div><div class='add'>+			adev-&gt;dev,</div><div class='add'>+			"guest specified rptr that was too high! guest rptr: 0x%llx, host rptr: 0x%llx\n",</div><div class='add'>+			adev-&gt;virt.ras.cper_rptr, cper_dump-&gt;wptr);</div><div class='add'>+</div><div class='add'>+		adev-&gt;virt.ras.cper_rptr = cper_dump-&gt;wptr;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	entry = (struct cper_hdr *)&amp;cper_dump-&gt;buf[0];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; cper_dump-&gt;count; i++) {</div><div class='add'>+		amdgpu_cper_ring_write(ring, entry, entry-&gt;record_length);</div><div class='add'>+		entry = (struct cper_hdr *)((char *)entry +</div><div class='add'>+					    entry-&gt;record_length);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cper_dump-&gt;overflow_count)</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "host reported CPER overflow of 0x%llx entries!\n",</div><div class='add'>+			 cper_dump-&gt;overflow_count);</div><div class='add'>+</div><div class='add'>+	adev-&gt;virt.ras.cper_rptr = cper_dump-&gt;wptr;</div><div class='add'>+out:</div><div class='add'>+	kfree(cper_dump);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_virt_req_ras_cper_dump_internal(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	uint32_t more = 0;</div><div class='add'>+</div><div class='add'>+	if (!virt-&gt;ops || !virt-&gt;ops-&gt;req_ras_cper_dump)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		if (!virt-&gt;ops-&gt;req_ras_cper_dump(adev, virt-&gt;ras.cper_rptr))</div><div class='add'>+			ret = amdgpu_virt_write_cpers_to_ring(</div><div class='add'>+				adev, virt-&gt;fw_reserve.ras_telemetry, &amp;more);</div><div class='add'>+		else</div><div class='add'>+			ret = 0;</div><div class='add'>+	} while (more &amp;&amp; !ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_ras_cper_en(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if ((__ratelimit(&amp;virt-&gt;ras.ras_cper_dump_rs) || force_update) &amp;&amp;</div><div class='add'>+	    down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		mutex_lock(&amp;virt-&gt;ras.ras_telemetry_mutex);</div><div class='add'>+		ret = amdgpu_virt_req_ras_cper_dump_internal(adev);</div><div class='add'>+		mutex_unlock(&amp;virt-&gt;ras.ras_telemetry_mutex);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	unsigned long ue_count, ce_count;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_ras_telemetry_en(adev)) {</div><div class='add'>+		amdgpu_virt_req_ras_err_count_internal(adev, true);</div><div class='add'>+		amdgpu_ras_query_error_count(adev, &amp;ce_count, &amp;ue_count, NULL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,</div><div class='add'>+					enum amdgpu_ras_block block)</div><div class='add'>+{</div><div class='add'>+	enum amd_sriov_ras_telemetry_gpu_block sriov_block;</div><div class='add'>+</div><div class='add'>+	sriov_block = amdgpu_ras_block_to_sriov(adev, block);</div><div class='add'>+</div><div class='add'>+	if (sriov_block &gt;= RAS_TELEMETRY_GPU_BLOCK_COUNT ||</div><div class='add'>+	    !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * amdgpu_virt_request_bad_pages() - request bad pages</div><div class='add'>+ * @adev: amdgpu device.</div><div class='add'>+ * Send command to GPU hypervisor to write new bad pages into the shared PF2VF region</div><div class='add'>+ */</div><div class='add'>+void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+</div><div class='add'>+	if (virt-&gt;ops &amp;&amp; virt-&gt;ops-&gt;req_bad_pages)</div><div class='add'>+		virt-&gt;ops-&gt;req_bad_pages(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_virt_cache_chk_criti_hit(struct amdgpu_device *adev,</div><div class='add'>+					   struct amdsriov_ras_telemetry *host_telemetry,</div><div class='add'>+					   bool *hit)</div><div class='add'>+{</div><div class='add'>+	struct amd_sriov_ras_chk_criti *tmp = NULL;</div><div class='add'>+	uint32_t checksum, used_size;</div><div class='add'>+</div><div class='add'>+	checksum = host_telemetry-&gt;header.checksum;</div><div class='add'>+	used_size = host_telemetry-&gt;header.used_size;</div><div class='add'>+</div><div class='add'>+	if (used_size &gt; (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 &lt;&lt; 10))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	tmp = kmemdup(&amp;host_telemetry-&gt;body.chk_criti, used_size, GFP_KERNEL);</div><div class='add'>+	if (!tmp)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (hit)</div><div class='add'>+		*hit = tmp-&gt;hit ? true : false;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(tmp);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+	int r = -EPERM;</div><div class='add'>+</div><div class='add'>+	if (!virt-&gt;ops || !virt-&gt;ops-&gt;req_ras_chk_criti)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	/* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host</div><div class='add'>+	 * will ignore incoming guest messages. Ratelimit the guest messages to</div><div class='add'>+	 * prevent guest self DOS.</div><div class='add'>+	 */</div><div class='add'>+	if (__ratelimit(&amp;virt-&gt;ras.ras_chk_criti_rs)) {</div><div class='add'>+		mutex_lock(&amp;virt-&gt;ras.ras_telemetry_mutex);</div><div class='add'>+		if (!virt-&gt;ops-&gt;req_ras_chk_criti(adev, addr))</div><div class='add'>+			r = amdgpu_virt_cache_chk_criti_hit(</div><div class='add'>+				adev, virt-&gt;fw_reserve.ras_telemetry, hit);</div><div class='add'>+		mutex_unlock(&amp;virt-&gt;ras.ras_telemetry_mutex);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br/>index 3f59b7b5523f..01d5bca2dee1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h</a></div><div class='hunk'>@@ -52,6 +52,14 @@</div><div class='ctx'> /* tonga/fiji use this offset */</div><div class='ctx'> #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2</div><div class='add'>+</div><div class='add'>+/* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */</div><div class='add'>+#define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA"</div><div class='add'>+#define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN   4</div><div class='add'>+</div><div class='add'>+#define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)-&gt;valid_tables &amp; (1 &lt;&lt; (id)))</div><div class='add'>+</div><div class='ctx'> enum amdgpu_sriov_vf_mode {</div><div class='ctx'> 	SRIOV_VF_MODE_BARE_METAL = 0,</div><div class='ctx'> 	SRIOV_VF_MODE_ONE_VF,</div><div class='hunk'>@@ -86,11 +94,17 @@ struct amdgpu_virt_ops {</div><div class='ctx'> 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);</div><div class='ctx'> 	int (*req_init_data)(struct amdgpu_device *adev);</div><div class='ctx'> 	int (*reset_gpu)(struct amdgpu_device *adev);</div><div class='add'>+	void (*ready_to_reset)(struct amdgpu_device *adev);</div><div class='ctx'> 	int (*wait_reset)(struct amdgpu_device *adev);</div><div class='ctx'> 	void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,</div><div class='ctx'> 			  u32 data1, u32 data2, u32 data3);</div><div class='ctx'> 	void (*ras_poison_handler)(struct amdgpu_device *adev,</div><div class='ctx'> 					enum amdgpu_ras_block block);</div><div class='add'>+	bool (*rcvd_ras_intr)(struct amdgpu_device *adev);</div><div class='add'>+	int (*req_ras_err_count)(struct amdgpu_device *adev);</div><div class='add'>+	int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);</div><div class='add'>+	int (*req_bad_pages)(struct amdgpu_device *adev);</div><div class='add'>+	int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -99,6 +113,7 @@ struct amdgpu_virt_ops {</div><div class='ctx'> struct amdgpu_virt_fw_reserve {</div><div class='ctx'> 	struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;</div><div class='ctx'> 	struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;</div><div class='add'>+	void *ras_telemetry;</div><div class='ctx'> 	unsigned int checksum_key;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -130,15 +145,25 @@ enum AMDGIM_FEATURE_FLAG {</div><div class='ctx'> 	AMDGIM_FEATURE_AV1_SUPPORT = (1 &lt;&lt; 6),</div><div class='ctx'> 	/* VCN RB decouple */</div><div class='ctx'> 	AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 &lt;&lt; 7),</div><div class='add'>+	/* MES info */</div><div class='add'>+	AMDGIM_FEATURE_MES_INFO_ENABLE = (1 &lt;&lt; 8),</div><div class='add'>+	AMDGIM_FEATURE_RAS_CAPS = (1 &lt;&lt; 9),</div><div class='add'>+	AMDGIM_FEATURE_RAS_TELEMETRY = (1 &lt;&lt; 10),</div><div class='add'>+	AMDGIM_FEATURE_RAS_CPER = (1 &lt;&lt; 11),</div><div class='add'>+	AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 &lt;&lt; 12),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum AMDGIM_REG_ACCESS_FLAG {</div><div class='ctx'> 	/* Use PSP to program IH_RB_CNTL */</div><div class='del'>-	AMDGIM_FEATURE_IH_REG_PSP_EN     = (1 &lt;&lt; 0),</div><div class='add'>+	AMDGIM_FEATURE_IH_REG_PSP_EN      = (1 &lt;&lt; 0),</div><div class='ctx'> 	/* Use RLC to program MMHUB regs */</div><div class='del'>-	AMDGIM_FEATURE_MMHUB_REG_RLC_EN  = (1 &lt;&lt; 1),</div><div class='add'>+	AMDGIM_FEATURE_MMHUB_REG_RLC_EN   = (1 &lt;&lt; 1),</div><div class='ctx'> 	/* Use RLC to program GC regs */</div><div class='del'>-	AMDGIM_FEATURE_GC_REG_RLC_EN     = (1 &lt;&lt; 2),</div><div class='add'>+	AMDGIM_FEATURE_GC_REG_RLC_EN      = (1 &lt;&lt; 2),</div><div class='add'>+	/* Use PSP to program L1_TLB_CNTL */</div><div class='add'>+	AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 &lt;&lt; 3),</div><div class='add'>+	/* Use RLCG to program SQ_CONFIG1 */</div><div class='add'>+	AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 &lt;&lt; 4),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgim_pf2vf_info_v1 {</div><div class='hunk'>@@ -232,6 +257,23 @@ struct amdgpu_virt_ras_err_handler_data {</div><div class='ctx'> 	int last_reserved;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_virt_ras {</div><div class='add'>+	struct ratelimit_state ras_error_cnt_rs;</div><div class='add'>+	struct ratelimit_state ras_cper_dump_rs;</div><div class='add'>+	struct ratelimit_state ras_chk_criti_rs;</div><div class='add'>+	struct mutex ras_telemetry_mutex;</div><div class='add'>+	uint64_t cper_rptr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT)</div><div class='add'>+</div><div class='add'>+DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST);</div><div class='add'>+</div><div class='add'>+struct amdgpu_virt_region {</div><div class='add'>+	uint32_t offset;</div><div class='add'>+	uint32_t size_kb;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* GPU virtualization */</div><div class='ctx'> struct amdgpu_virt {</div><div class='ctx'> 	uint32_t			caps;</div><div class='hunk'>@@ -241,11 +283,16 @@ struct amdgpu_virt {</div><div class='ctx'> 	uint32_t			reg_val_offs;</div><div class='ctx'> 	struct amdgpu_irq_src		ack_irq;</div><div class='ctx'> 	struct amdgpu_irq_src		rcv_irq;</div><div class='add'>+</div><div class='ctx'> 	struct work_struct		flr_work;</div><div class='add'>+	struct work_struct		req_bad_pages_work;</div><div class='add'>+	struct work_struct		handle_bad_pages_work;</div><div class='add'>+</div><div class='ctx'> 	struct amdgpu_mm_table		mm_table;</div><div class='ctx'> 	const struct amdgpu_virt_ops	*ops;</div><div class='ctx'> 	struct amdgpu_vf_error_buffer	vf_errors;</div><div class='ctx'> 	struct amdgpu_virt_fw_reserve	fw_reserve;</div><div class='add'>+	struct amdgpu_virt_caps virt_caps;</div><div class='ctx'> 	uint32_t gim_feature;</div><div class='ctx'> 	uint32_t reg_access_mode;</div><div class='ctx'> 	int req_init_data_ver;</div><div class='hunk'>@@ -254,9 +301,16 @@ struct amdgpu_virt {</div><div class='ctx'> 	bool ras_init_done;</div><div class='ctx'> 	uint32_t reg_access;</div><div class='ctx'> </div><div class='add'>+	/* dynamic(v2) critical regions */</div><div class='add'>+	struct amdgpu_virt_region init_data_header;</div><div class='add'>+	struct amdgpu_virt_region crit_regn;</div><div class='add'>+	struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID];</div><div class='add'>+	bool is_dynamic_crit_regn_enabled;</div><div class='add'>+</div><div class='ctx'> 	/* vf2pf message */</div><div class='ctx'> 	struct delayed_work vf2pf_work;</div><div class='ctx'> 	uint32_t vf2pf_update_interval_ms;</div><div class='add'>+	int vf2pf_update_retry_cnt;</div><div class='ctx'> </div><div class='ctx'> 	/* multimedia bandwidth config */</div><div class='ctx'> 	bool     is_mm_bw_enabled;</div><div class='hunk'>@@ -267,6 +321,19 @@ struct amdgpu_virt {</div><div class='ctx'> </div><div class='ctx'> 	/* the ucode id to signal the autoload */</div><div class='ctx'> 	uint32_t autoload_ucode_id;</div><div class='add'>+</div><div class='add'>+	/* Spinlock to protect access to the RLCG register interface */</div><div class='add'>+	spinlock_t rlcg_reg_lock;</div><div class='add'>+</div><div class='add'>+	struct mutex access_req_mutex;</div><div class='add'>+</div><div class='add'>+	union amd_sriov_ras_caps ras_en_caps;</div><div class='add'>+	union amd_sriov_ras_caps ras_telemetry_en_caps;</div><div class='add'>+	struct amdgpu_virt_ras ras;</div><div class='add'>+	struct amd_sriov_ras_telemetry_error_count count_cache;</div><div class='add'>+</div><div class='add'>+	/* hibernate and resume with different VF feature for xgmi enabled system */</div><div class='add'>+	bool is_xgmi_node_migrate_enabled;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_video_codec_info;</div><div class='hunk'>@@ -302,15 +369,38 @@ struct amdgpu_video_codec_info;</div><div class='ctx'> (amdgpu_sriov_vf((adev)) &amp;&amp; \</div><div class='ctx'> 	((adev)-&gt;virt.reg_access &amp; (AMDGIM_FEATURE_GC_REG_RLC_EN)))</div><div class='ctx'> </div><div class='add'>+#define amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev) \</div><div class='add'>+(amdgpu_sriov_vf((adev)) &amp;&amp; \</div><div class='add'>+	((adev)-&gt;virt.reg_access &amp; (AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN)))</div><div class='add'>+</div><div class='ctx'> #define amdgpu_sriov_rlcg_error_report_enabled(adev) \</div><div class='ctx'>         (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))</div><div class='ctx'> </div><div class='add'>+#define amdgpu_sriov_reg_access_sq_config(adev) \</div><div class='add'>+(amdgpu_sriov_vf((adev)) &amp;&amp; \</div><div class='add'>+	((adev)-&gt;virt.reg_access &amp; (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG)))</div><div class='add'>+</div><div class='ctx'> #define amdgpu_passthrough(adev) \</div><div class='ctx'> ((adev)-&gt;virt.caps &amp; AMDGPU_PASSTHROUGH_MODE)</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_sriov_vf_mmio_access_protection(adev) \</div><div class='ctx'> ((adev)-&gt;virt.caps &amp; AMDGPU_VF_MMIO_ACCESS_PROTECT)</div><div class='ctx'> </div><div class='add'>+#define amdgpu_sriov_ras_caps_en(adev) \</div><div class='add'>+((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_RAS_CAPS)</div><div class='add'>+</div><div class='add'>+#define amdgpu_sriov_ras_telemetry_en(adev) \</div><div class='add'>+(((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_RAS_TELEMETRY) &amp;&amp; (adev)-&gt;virt.fw_reserve.ras_telemetry)</div><div class='add'>+</div><div class='add'>+#define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \</div><div class='add'>+(amdgpu_sriov_ras_telemetry_en((adev)) &amp;&amp; (adev)-&gt;virt.ras_telemetry_en_caps.all &amp; BIT(sriov_blk))</div><div class='add'>+</div><div class='add'>+#define amdgpu_sriov_ras_cper_en(adev) \</div><div class='add'>+((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_RAS_CPER)</div><div class='add'>+</div><div class='add'>+#define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \</div><div class='add'>+((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK)</div><div class='add'>+</div><div class='ctx'> static inline bool is_virtual_machine(void)</div><div class='ctx'> {</div><div class='ctx'> #if defined(CONFIG_X86)</div><div class='hunk'>@@ -324,6 +414,8 @@ static inline bool is_virtual_machine(void)</div><div class='ctx'> </div><div class='ctx'> #define amdgpu_sriov_is_pp_one_vf(adev) \</div><div class='ctx'> 	((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_PP_ONE_VF)</div><div class='add'>+#define amdgpu_sriov_multi_vf_mode(adev) \</div><div class='add'>+	(amdgpu_sriov_vf(adev) &amp;&amp; !amdgpu_sriov_is_pp_one_vf(adev))</div><div class='ctx'> #define amdgpu_sriov_is_debug(adev) \</div><div class='ctx'> 	((!amdgpu_in_reset(adev)) &amp;&amp; adev-&gt;virt.tdr_debug)</div><div class='ctx'> #define amdgpu_sriov_is_normal(adev) \</div><div class='hunk'>@@ -332,20 +424,32 @@ static inline bool is_virtual_machine(void)</div><div class='ctx'> 	((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_AV1_SUPPORT)</div><div class='ctx'> #define amdgpu_sriov_is_vcn_rb_decouple(adev) \</div><div class='ctx'> 	((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_VCN_RB_DECOUPLE)</div><div class='add'>+#define amdgpu_sriov_is_mes_info_enable(adev) \</div><div class='add'>+	((adev)-&gt;virt.gim_feature &amp; AMDGIM_FEATURE_MES_INFO_ENABLE)</div><div class='add'>+</div><div class='add'>+#define amdgpu_virt_xgmi_migrate_enabled(adev) \</div><div class='add'>+	((adev)-&gt;virt.is_xgmi_node_migrate_enabled &amp;&amp; (adev)-&gt;gmc.xgmi.node_segment_size != 0)</div><div class='add'>+</div><div class='ctx'> bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_init_setting(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);</div><div class='ctx'> int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);</div><div class='ctx'> int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_request_init_data(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_virt_wait_reset(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_exchange_data(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);</div><div class='del'>-void amdgpu_detect_virtualization(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_virt_init(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int amdgpu_virt_init_critical_region(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev,</div><div class='add'>+	int data_id, uint8_t *binary, u32 *size);</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);</div><div class='hunk'>@@ -363,10 +467,20 @@ u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,</div><div class='ctx'> 		      u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);</div><div class='ctx'> bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,</div><div class='ctx'> 			uint32_t ucode_id);</div><div class='add'>+void amdgpu_virt_pre_reset(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_virt_post_reset(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,</div><div class='ctx'> 					  u32 acc_flags, u32 hwip,</div><div class='ctx'> 					  bool write, u32 *rlcg_flag);</div><div class='ctx'> u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);</div><div class='add'>+bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block,</div><div class='add'>+				  struct ras_err_data *err_data);</div><div class='add'>+int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update);</div><div class='add'>+int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev);</div><div class='add'>+bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,</div><div class='add'>+					enum amdgpu_ras_block block);</div><div class='add'>+void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c<br/>index 8baa2e0935cc..79bad9cbe2ab 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_simple_kms_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_gem_framebuffer_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_vblank.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='hunk'>@@ -13,7 +14,6 @@</div><div class='ctx'> #include "dce_v8_0.h"</div><div class='ctx'> #endif</div><div class='ctx'> #include "dce_v10_0.h"</div><div class='del'>-#include "dce_v11_0.h"</div><div class='ctx'> #include "ivsrcid/ivsrcid_vislands30.h"</div><div class='ctx'> #include "amdgpu_vkms.h"</div><div class='ctx'> #include "amdgpu_display.h"</div><div class='hunk'>@@ -65,9 +65,7 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer)</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	unsigned int pipe = drm_crtc_index(crtc);</div><div class='del'>-	struct drm_vblank_crtc *vblank = &amp;dev-&gt;vblank[pipe];</div><div class='add'>+	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);</div><div class='ctx'> 	struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='hunk'>@@ -91,10 +89,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,</div><div class='ctx'> 					     ktime_t *vblank_time,</div><div class='ctx'> 					     bool in_vblank_irq)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	unsigned int pipe = crtc-&gt;index;</div><div class='ctx'> 	struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);</div><div class='del'>-	struct drm_vblank_crtc *vblank = &amp;dev-&gt;vblank[pipe];</div><div class='add'>+	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	if (!READ_ONCE(vblank-&gt;enabled)) {</div><div class='hunk'>@@ -191,8 +187,8 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,</div><div class='ctx'> 	amdgpu_crtc-&gt;connector = NULL;</div><div class='ctx'> 	amdgpu_crtc-&gt;vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;</div><div class='ctx'> </div><div class='del'>-	hrtimer_init(&amp;amdgpu_crtc-&gt;vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);</div><div class='del'>-	amdgpu_crtc-&gt;vblank_timer.function = &amp;amdgpu_vkms_vblank_simulate;</div><div class='add'>+	hrtimer_setup(&amp;amdgpu_crtc-&gt;vblank_timer, &amp;amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC,</div><div class='add'>+		      HRTIMER_MODE_REL);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -314,7 +310,13 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	afb = to_amdgpu_framebuffer(new_state-&gt;fb);</div><div class='del'>-	obj = new_state-&gt;fb-&gt;obj[0];</div><div class='add'>+</div><div class='add'>+	obj = drm_gem_fb_get_obj(new_state-&gt;fb, 0);</div><div class='add'>+	if (!obj) {</div><div class='add'>+		DRM_ERROR("Failed to get obj from framebuffer\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rbo = gem_to_amdgpu_bo(obj);</div><div class='ctx'> 	adev = amdgpu_ttm_adev(rbo-&gt;tbo.bdev);</div><div class='ctx'> </div><div class='hunk'>@@ -335,6 +337,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,</div><div class='ctx'> 	else</div><div class='ctx'> 		domain = AMDGPU_GEM_DOMAIN_VRAM;</div><div class='ctx'> </div><div class='add'>+	rbo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 	r = amdgpu_bo_pin(rbo, domain);</div><div class='ctx'> 	if (unlikely(r != 0)) {</div><div class='ctx'> 		if (r != -ERESTARTSYS)</div><div class='hunk'>@@ -368,12 +371,19 @@ static void amdgpu_vkms_cleanup_fb(struct drm_plane *plane,</div><div class='ctx'> 				   struct drm_plane_state *old_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo *rbo;</div><div class='add'>+	struct drm_gem_object *obj;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!old_state-&gt;fb)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	rbo = gem_to_amdgpu_bo(old_state-&gt;fb-&gt;obj[0]);</div><div class='add'>+	obj = drm_gem_fb_get_obj(old_state-&gt;fb, 0);</div><div class='add'>+	if (!obj) {</div><div class='add'>+		DRM_ERROR("Failed to get obj from framebuffer\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rbo = gem_to_amdgpu_bo(obj);</div><div class='ctx'> 	r = amdgpu_bo_reserve(rbo, false);</div><div class='ctx'> 	if (unlikely(r)) {</div><div class='ctx'> 		DRM_ERROR("failed to reserve rbo before unpin\n");</div><div class='hunk'>@@ -482,10 +492,10 @@ const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = {</div><div class='ctx'> 	.atomic_commit = drm_atomic_helper_commit,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_sw_init(void *handle)</div><div class='add'>+static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;amdgpu_vkms_output = kcalloc(adev-&gt;mode_info.num_crtc,</div><div class='ctx'> 		sizeof(struct amdgpu_vkms_output), GFP_KERNEL);</div><div class='hunk'>@@ -525,9 +535,9 @@ static int amdgpu_vkms_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_sw_fini(void *handle)</div><div class='add'>+static int amdgpu_vkms_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++)</div><div class='hunk'>@@ -539,14 +549,14 @@ static int amdgpu_vkms_sw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mode_info.mode_config_initialized = false;</div><div class='ctx'> </div><div class='del'>-	kfree(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='add'>+	drm_edid_free(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='ctx'> 	kfree(adev-&gt;amdgpu_vkms_output);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_hw_init(void *handle)</div><div class='add'>+static int amdgpu_vkms_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_SI</div><div class='hunk'>@@ -570,13 +580,6 @@ static int amdgpu_vkms_hw_init(void *handle)</div><div class='ctx'> 	case CHIP_TONGA:</div><div class='ctx'> 		dce_v10_0_disable_dce(adev);</div><div class='ctx'> 		break;</div><div class='del'>-	case CHIP_CARRIZO:</div><div class='del'>-	case CHIP_STONEY:</div><div class='del'>-	case CHIP_POLARIS10:</div><div class='del'>-	case CHIP_POLARIS11:</div><div class='del'>-	case CHIP_VEGAM:</div><div class='del'>-		dce_v11_0_disable_dce(adev);</div><div class='del'>-		break;</div><div class='ctx'> 	case CHIP_TOPAZ:</div><div class='ctx'> #ifdef CONFIG_DRM_AMDGPU_SI</div><div class='ctx'> 	case CHIP_HAINAN:</div><div class='hunk'>@@ -589,55 +592,45 @@ static int amdgpu_vkms_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_hw_fini(void *handle)</div><div class='add'>+static int amdgpu_vkms_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_suspend(void *handle)</div><div class='add'>+static int amdgpu_vkms_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = drm_mode_config_helper_suspend(adev_to_drm(adev));</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	return amdgpu_vkms_hw_fini(handle);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_resume(void *handle)</div><div class='add'>+static int amdgpu_vkms_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vkms_hw_init(handle);</div><div class='add'>+	r = amdgpu_vkms_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	return drm_mode_config_helper_resume(adev_to_drm(adev));</div><div class='add'>+	return drm_mode_config_helper_resume(adev_to_drm(ip_block-&gt;adev));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool amdgpu_vkms_is_idle(void *handle)</div><div class='add'>+static bool amdgpu_vkms_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int amdgpu_vkms_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int amdgpu_vkms_set_clockgating_state(void *handle,</div><div class='add'>+static int amdgpu_vkms_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_vkms_set_powergating_state(void *handle,</div><div class='add'>+static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -645,8 +638,6 @@ static int amdgpu_vkms_set_powergating_state(void *handle,</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {</div><div class='ctx'> 	.name = "amdgpu_vkms",</div><div class='del'>-	.early_init = NULL,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = amdgpu_vkms_sw_init,</div><div class='ctx'> 	.sw_fini = amdgpu_vkms_sw_fini,</div><div class='ctx'> 	.hw_init = amdgpu_vkms_hw_init,</div><div class='hunk'>@@ -654,8 +645,6 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {</div><div class='ctx'> 	.suspend = amdgpu_vkms_suspend,</div><div class='ctx'> 	.resume = amdgpu_vkms_resume,</div><div class='ctx'> 	.is_idle = amdgpu_vkms_is_idle,</div><div class='del'>-	.wait_for_idle = amdgpu_vkms_wait_for_idle,</div><div class='del'>-	.soft_reset = amdgpu_vkms_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = amdgpu_vkms_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = amdgpu_vkms_set_powergating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c<br/>index 4299ce386322..a67285118c37 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c</a></div><div class='hunk'>@@ -36,6 +36,7 @@</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='ctx'> #include &lt;drm/drm_exec.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='add'>+#include "amdgpu_vm.h"</div><div class='ctx'> #include "amdgpu_trace.h"</div><div class='ctx'> #include "amdgpu_amdkfd.h"</div><div class='ctx'> #include "amdgpu_gmc.h"</div><div class='hunk'>@@ -127,43 +128,14 @@ struct amdgpu_vm_tlb_seq_struct {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @vm: amdgpu_vm pointer</div><div class='del'>- * @pasid: the pasid the VM is using on this GPU</div><div class='del'>- *</div><div class='del'>- * Set the pasid this VM is using on this GPU, can also be used to remove the</div><div class='del'>- * pasid by passing in zero.</div><div class='add'>+ * amdgpu_vm_assert_locked - check if VM is correctly locked</div><div class='add'>+ * @vm: the VM which schould be tested</div><div class='ctx'>  *</div><div class='add'>+ * Asserts that the VM root PD is locked.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-			u32 pasid)</div><div class='add'>+static void amdgpu_vm_assert_locked(struct amdgpu_vm *vm)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	if (vm-&gt;pasid == pasid)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (vm-&gt;pasid) {</div><div class='del'>-		r = xa_err(xa_erase_irq(&amp;adev-&gt;vm_manager.pasids, vm-&gt;pasid));</div><div class='del'>-		if (r &lt; 0)</div><div class='del'>-			return r;</div><div class='del'>-</div><div class='del'>-		vm-&gt;pasid = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (pasid) {</div><div class='del'>-		r = xa_err(xa_store_irq(&amp;adev-&gt;vm_manager.pasids, pasid, vm,</div><div class='del'>-					GFP_KERNEL));</div><div class='del'>-		if (r &lt; 0)</div><div class='del'>-			return r;</div><div class='del'>-</div><div class='del'>-		vm-&gt;pasid = pasid;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	dma_resv_assert_held(vm-&gt;root.bo-&gt;tbo.base.resv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -180,6 +152,7 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'> 	struct amdgpu_bo *bo = vm_bo-&gt;bo;</div><div class='ctx'> </div><div class='ctx'> 	vm_bo-&gt;moved = true;</div><div class='add'>+	amdgpu_vm_assert_locked(vm);</div><div class='ctx'> 	spin_lock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='ctx'> 	if (bo-&gt;tbo.type == ttm_bo_type_kernel)</div><div class='ctx'> 		list_move(&amp;vm_bo-&gt;vm_status, &amp;vm-&gt;evicted);</div><div class='hunk'>@@ -197,6 +170,7 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_vm_assert_locked(vm_bo-&gt;vm);</div><div class='ctx'> 	spin_lock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='ctx'> 	list_move(&amp;vm_bo-&gt;vm_status, &amp;vm_bo-&gt;vm-&gt;moved);</div><div class='ctx'> 	spin_unlock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='hunk'>@@ -212,6 +186,7 @@ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_vm_assert_locked(vm_bo-&gt;vm);</div><div class='ctx'> 	spin_lock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='ctx'> 	list_move(&amp;vm_bo-&gt;vm_status, &amp;vm_bo-&gt;vm-&gt;idle);</div><div class='ctx'> 	spin_unlock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='hunk'>@@ -259,6 +234,7 @@ static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_vm_assert_locked(vm_bo-&gt;vm);</div><div class='ctx'> 	if (vm_bo-&gt;bo-&gt;parent) {</div><div class='ctx'> 		spin_lock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='ctx'> 		list_move(&amp;vm_bo-&gt;vm_status, &amp;vm_bo-&gt;vm-&gt;relocated);</div><div class='hunk'>@@ -278,6 +254,7 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_vm_assert_locked(vm_bo-&gt;vm);</div><div class='ctx'> 	spin_lock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='ctx'> 	list_move(&amp;vm_bo-&gt;vm_status, &amp;vm_bo-&gt;vm-&gt;done);</div><div class='ctx'> 	spin_unlock(&amp;vm_bo-&gt;vm-&gt;status_lock);</div><div class='hunk'>@@ -294,10 +271,13 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vm_bo_base *vm_bo, *tmp;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_assert_locked(vm);</div><div class='add'>+</div><div class='ctx'> 	spin_lock(&amp;vm-&gt;status_lock);</div><div class='ctx'> 	list_splice_init(&amp;vm-&gt;done, &amp;vm-&gt;invalidated);</div><div class='ctx'> 	list_for_each_entry(vm_bo, &amp;vm-&gt;invalidated, vm_status)</div><div class='ctx'> 		vm_bo-&gt;moved = true;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(vm_bo, tmp, &amp;vm-&gt;idle, vm_status) {</div><div class='ctx'> 		struct amdgpu_bo *bo = vm_bo-&gt;bo;</div><div class='ctx'> </div><div class='hunk'>@@ -311,6 +291,112 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vm_update_shared - helper to update shared memory stat</div><div class='add'>+ * @base: base structure for tracking BO usage in a VM</div><div class='add'>+ *</div><div class='add'>+ * Takes the vm status_lock and updates the shared memory stat. If the basic</div><div class='add'>+ * stat changed (e.g. buffer was moved) amdgpu_vm_update_stats need to be called</div><div class='add'>+ * as well.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm *vm = base-&gt;vm;</div><div class='add'>+	struct amdgpu_bo *bo = base-&gt;bo;</div><div class='add'>+	uint64_t size = amdgpu_bo_size(bo);</div><div class='add'>+	uint32_t bo_memtype = amdgpu_bo_mem_stats_placement(bo);</div><div class='add'>+	bool shared;</div><div class='add'>+</div><div class='add'>+	dma_resv_assert_held(bo-&gt;tbo.base.resv);</div><div class='add'>+	spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+	shared = drm_gem_object_is_shared_for_memory_stats(&amp;bo-&gt;tbo.base);</div><div class='add'>+	if (base-&gt;shared != shared) {</div><div class='add'>+		base-&gt;shared = shared;</div><div class='add'>+		if (shared) {</div><div class='add'>+			vm-&gt;stats[bo_memtype].drm.shared += size;</div><div class='add'>+			vm-&gt;stats[bo_memtype].drm.private -= size;</div><div class='add'>+		} else {</div><div class='add'>+			vm-&gt;stats[bo_memtype].drm.shared -= size;</div><div class='add'>+			vm-&gt;stats[bo_memtype].drm.private += size;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vm_bo_update_shared - callback when bo gets shared/unshared</div><div class='add'>+ * @bo: amdgpu buffer object</div><div class='add'>+ *</div><div class='add'>+ * Update the per VM stats for all the vm if needed from private to shared or</div><div class='add'>+ * vice versa.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm_bo_base *base;</div><div class='add'>+</div><div class='add'>+	for (base = bo-&gt;vm_bo; base; base = base-&gt;next)</div><div class='add'>+		amdgpu_vm_update_shared(base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vm_update_stats_locked - helper to update normal memory stat</div><div class='add'>+ * @base: base structure for tracking BO usage in a VM</div><div class='add'>+ * @res:  the ttm_resource to use for the purpose of accounting, may or may not</div><div class='add'>+ *        be bo-&gt;tbo.resource</div><div class='add'>+ * @sign: if we should add (+1) or subtract (-1) from the stat</div><div class='add'>+ *</div><div class='add'>+ * Caller need to have the vm status_lock held. Useful for when multiple update</div><div class='add'>+ * need to happen at the same time.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base,</div><div class='add'>+			    struct ttm_resource *res, int sign)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm *vm = base-&gt;vm;</div><div class='add'>+	struct amdgpu_bo *bo = base-&gt;bo;</div><div class='add'>+	int64_t size = sign * amdgpu_bo_size(bo);</div><div class='add'>+	uint32_t bo_memtype = amdgpu_bo_mem_stats_placement(bo);</div><div class='add'>+</div><div class='add'>+	/* For drm-total- and drm-shared-, BO are accounted by their preferred</div><div class='add'>+	 * placement, see also amdgpu_bo_mem_stats_placement.</div><div class='add'>+	 */</div><div class='add'>+	if (base-&gt;shared)</div><div class='add'>+		vm-&gt;stats[bo_memtype].drm.shared += size;</div><div class='add'>+	else</div><div class='add'>+		vm-&gt;stats[bo_memtype].drm.private += size;</div><div class='add'>+</div><div class='add'>+	if (res &amp;&amp; res-&gt;mem_type &lt; __AMDGPU_PL_NUM) {</div><div class='add'>+		uint32_t res_memtype = res-&gt;mem_type;</div><div class='add'>+</div><div class='add'>+		vm-&gt;stats[res_memtype].drm.resident += size;</div><div class='add'>+		/* BO only count as purgeable if it is resident,</div><div class='add'>+		 * since otherwise there's nothing to purge.</div><div class='add'>+		 */</div><div class='add'>+		if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_DISCARDABLE)</div><div class='add'>+			vm-&gt;stats[res_memtype].drm.purgeable += size;</div><div class='add'>+		if (!(bo-&gt;preferred_domains &amp; amdgpu_mem_type_to_domain(res_memtype)))</div><div class='add'>+			vm-&gt;stats[bo_memtype].evicted += size;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vm_update_stats - helper to update normal memory stat</div><div class='add'>+ * @base: base structure for tracking BO usage in a VM</div><div class='add'>+ * @res:  the ttm_resource to use for the purpose of accounting, may or may not</div><div class='add'>+ *        be bo-&gt;tbo.resource</div><div class='add'>+ * @sign: if we should add (+1) or subtract (-1) from the stat</div><div class='add'>+ *</div><div class='add'>+ * Updates the basic memory stat when bo is added/deleted/moved.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base,</div><div class='add'>+			    struct ttm_resource *res, int sign)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm *vm = base-&gt;vm;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+	amdgpu_vm_update_stats_locked(base, res, sign);</div><div class='add'>+	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm</div><div class='ctx'>  *</div><div class='ctx'>  * @base: base structure for tracking BO usage in a VM</div><div class='hunk'>@@ -333,7 +419,12 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,</div><div class='ctx'> 	base-&gt;next = bo-&gt;vm_bo;</div><div class='ctx'> 	bo-&gt;vm_bo = base;</div><div class='ctx'> </div><div class='del'>-	if (bo-&gt;tbo.base.resv != vm-&gt;root.bo-&gt;tbo.base.resv)</div><div class='add'>+	spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+	base-&gt;shared = drm_gem_object_is_shared_for_memory_stats(&amp;bo-&gt;tbo.base);</div><div class='add'>+	amdgpu_vm_update_stats_locked(base, bo-&gt;tbo.resource, +1);</div><div class='add'>+	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_vm_is_bo_always_valid(vm, bo))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	dma_resv_assert_held(vm-&gt;root.bo-&gt;tbo.base.resv);</div><div class='hunk'>@@ -374,6 +465,46 @@ int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vm_lock_done_list - lock all BOs on the done list</div><div class='add'>+ * @vm: vm providing the BOs</div><div class='add'>+ * @exec: drm execution context</div><div class='add'>+ * @num_fences: number of extra fences to reserve</div><div class='add'>+ *</div><div class='add'>+ * Lock the BOs on the done list in the DRM execution context.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec,</div><div class='add'>+			     unsigned int num_fences)</div><div class='add'>+{</div><div class='add'>+	struct list_head *prev = &amp;vm-&gt;done;</div><div class='add'>+	struct amdgpu_bo_va *bo_va;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* We can only trust prev-&gt;next while holding the lock */</div><div class='add'>+	spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+	while (!list_is_head(prev-&gt;next, &amp;vm-&gt;done)) {</div><div class='add'>+		bo_va = list_entry(prev-&gt;next, typeof(*bo_va), base.vm_status);</div><div class='add'>+</div><div class='add'>+		bo = bo_va-&gt;base.bo;</div><div class='add'>+		if (bo) {</div><div class='add'>+			amdgpu_bo_ref(bo);</div><div class='add'>+			spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+</div><div class='add'>+			ret = drm_exec_prepare_obj(exec, &amp;bo-&gt;tbo.base, 1);</div><div class='add'>+			amdgpu_bo_unref(&amp;bo);</div><div class='add'>+			if (unlikely(ret))</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+		}</div><div class='add'>+		prev = prev-&gt;next;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu device pointer</div><div class='hunk'>@@ -434,7 +565,7 @@ uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> 	if (!vm)</div><div class='ctx'> 		return result;</div><div class='ctx'> </div><div class='del'>-	result += vm-&gt;generation;</div><div class='add'>+	result += lower_32_bits(vm-&gt;generation);</div><div class='ctx'> 	/* Add one if the page tables will be re-generated on next CS */</div><div class='ctx'> 	if (drm_sched_entity_error(&amp;vm-&gt;delayed))</div><div class='ctx'> 		++result;</div><div class='hunk'>@@ -463,13 +594,13 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		       int (*validate)(void *p, struct amdgpu_bo *bo),</div><div class='ctx'> 		       void *param)</div><div class='ctx'> {</div><div class='add'>+	uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm);</div><div class='ctx'> 	struct amdgpu_vm_bo_base *bo_base;</div><div class='del'>-	struct amdgpu_bo *shadow;</div><div class='ctx'> 	struct amdgpu_bo *bo;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (drm_sched_entity_error(&amp;vm-&gt;delayed)) {</div><div class='del'>-		++vm-&gt;generation;</div><div class='add'>+	if (vm-&gt;generation != new_vm_generation) {</div><div class='add'>+		vm-&gt;generation = new_vm_generation;</div><div class='ctx'> 		amdgpu_vm_bo_reset_state_machine(vm);</div><div class='ctx'> 		amdgpu_vm_fini_entities(vm);</div><div class='ctx'> 		r = amdgpu_vm_init_entities(adev, vm);</div><div class='hunk'>@@ -485,16 +616,10 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		spin_unlock(&amp;vm-&gt;status_lock);</div><div class='ctx'> </div><div class='ctx'> 		bo = bo_base-&gt;bo;</div><div class='del'>-		shadow = amdgpu_bo_shadowed(bo);</div><div class='ctx'> </div><div class='ctx'> 		r = validate(param, bo);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-		if (shadow) {</div><div class='del'>-			r = validate(param, shadow);</div><div class='del'>-			if (r)</div><div class='del'>-				return r;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		if (bo-&gt;tbo.type != ttm_bo_type_kernel) {</div><div class='ctx'> 			amdgpu_vm_bo_moved(bo_base);</div><div class='hunk'>@@ -511,18 +636,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		spin_unlock(&amp;vm-&gt;status_lock);</div><div class='ctx'> </div><div class='ctx'> 		bo = bo_base-&gt;bo;</div><div class='del'>-</div><div class='del'>-		if (dma_resv_locking_ctx(bo-&gt;tbo.base.resv) != ticket) {</div><div class='del'>-			struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);</div><div class='del'>-</div><div class='del'>-			pr_warn_ratelimited("Evicted user BO is not reserved\n");</div><div class='del'>-			if (ti) {</div><div class='del'>-				pr_warn_ratelimited("pid %d\n", ti-&gt;pid);</div><div class='del'>-				amdgpu_vm_put_task_info(ti);</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='add'>+		dma_resv_assert_held(bo-&gt;tbo.base.resv);</div><div class='ctx'> </div><div class='ctx'> 		r = validate(param, bo);</div><div class='ctx'> 		if (r)</div><div class='hunk'>@@ -549,22 +663,31 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'>  * Check if all VM PDs/PTs are ready for updates</div><div class='ctx'>  *</div><div class='ctx'>  * Returns:</div><div class='del'>- * True if VM is not evicting.</div><div class='add'>+ * True if VM is not evicting and all VM entities are not stopped</div><div class='ctx'>  */</div><div class='ctx'> bool amdgpu_vm_ready(struct amdgpu_vm *vm)</div><div class='ctx'> {</div><div class='del'>-	bool empty;</div><div class='ctx'> 	bool ret;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_assert_locked(vm);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_vm_eviction_lock(vm);</div><div class='ctx'> 	ret = !vm-&gt;evicting;</div><div class='ctx'> 	amdgpu_vm_eviction_unlock(vm);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;vm-&gt;status_lock);</div><div class='del'>-	empty = list_empty(&amp;vm-&gt;evicted);</div><div class='add'>+	ret &amp;= list_empty(&amp;vm-&gt;evicted);</div><div class='ctx'> 	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='ctx'> </div><div class='del'>-	return ret &amp;&amp; empty;</div><div class='add'>+	spin_lock(&amp;vm-&gt;immediate.lock);</div><div class='add'>+	ret &amp;= !vm-&gt;immediate.stopped;</div><div class='add'>+	spin_unlock(&amp;vm-&gt;immediate.lock);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;vm-&gt;delayed.lock);</div><div class='add'>+	ret &amp;= !vm-&gt;delayed.stopped;</div><div class='add'>+	spin_unlock(&amp;vm-&gt;delayed.lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -649,6 +772,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 		    bool need_pipe_sync)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_isolation *isolation = &amp;adev-&gt;isolation[ring-&gt;xcp_id];</div><div class='ctx'> 	unsigned vmhub = ring-&gt;vm_hub;</div><div class='ctx'> 	struct amdgpu_vmid_mgr *id_mgr = &amp;adev-&gt;vm_manager.id_mgr[vmhub];</div><div class='ctx'> 	struct amdgpu_vmid *id = &amp;id_mgr-&gt;ids[job-&gt;vmid];</div><div class='hunk'>@@ -656,8 +780,9 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 	bool gds_switch_needed = ring-&gt;funcs-&gt;emit_gds_switch &amp;&amp;</div><div class='ctx'> 		job-&gt;gds_switch_needed;</div><div class='ctx'> 	bool vm_flush_needed = job-&gt;vm_needs_flush;</div><div class='del'>-	struct dma_fence *fence = NULL;</div><div class='add'>+	bool cleaner_shader_needed = false;</div><div class='ctx'> 	bool pasid_mapping_needed = false;</div><div class='add'>+	struct dma_fence *fence = NULL;</div><div class='ctx'> 	unsigned int patch;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -680,7 +805,13 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 	pasid_mapping_needed &amp;= adev-&gt;gmc.gmc_funcs-&gt;emit_pasid_mapping &amp;&amp;</div><div class='ctx'> 		ring-&gt;funcs-&gt;emit_wreg;</div><div class='ctx'> </div><div class='del'>-	if (!vm_flush_needed &amp;&amp; !gds_switch_needed &amp;&amp; !need_pipe_sync)</div><div class='add'>+	cleaner_shader_needed = job-&gt;run_cleaner_shader &amp;&amp;</div><div class='add'>+		adev-&gt;gfx.enable_cleaner_shader &amp;&amp;</div><div class='add'>+		ring-&gt;funcs-&gt;emit_cleaner_shader &amp;&amp; job-&gt;base.s_fence &amp;&amp;</div><div class='add'>+		&amp;job-&gt;base.s_fence-&gt;scheduled == isolation-&gt;spearhead;</div><div class='add'>+</div><div class='add'>+	if (!vm_flush_needed &amp;&amp; !gds_switch_needed &amp;&amp; !need_pipe_sync &amp;&amp;</div><div class='add'>+	    !cleaner_shader_needed)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_ib_begin(ring);</div><div class='hunk'>@@ -691,6 +822,9 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 	if (need_pipe_sync)</div><div class='ctx'> 		amdgpu_ring_emit_pipeline_sync(ring);</div><div class='ctx'> </div><div class='add'>+	if (cleaner_shader_needed)</div><div class='add'>+		ring-&gt;funcs-&gt;emit_cleaner_shader(ring);</div><div class='add'>+</div><div class='ctx'> 	if (vm_flush_needed) {</div><div class='ctx'> 		trace_amdgpu_vm_flush(ring, job-&gt;vmid, job-&gt;vm_pd_addr);</div><div class='ctx'> 		amdgpu_ring_emit_vm_flush(ring, job-&gt;vmid, job-&gt;vm_pd_addr);</div><div class='hunk'>@@ -702,7 +836,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 	if (spm_update_needed &amp;&amp; adev-&gt;gfx.rlc.funcs-&gt;update_spm_vmid)</div><div class='ctx'> 		adev-&gt;gfx.rlc.funcs-&gt;update_spm_vmid(adev, ring, job-&gt;vmid);</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;is_mes_queue &amp;&amp; ring-&gt;funcs-&gt;emit_gds_switch &amp;&amp;</div><div class='add'>+	if (ring-&gt;funcs-&gt;emit_gds_switch &amp;&amp;</div><div class='ctx'> 	    gds_switch_needed) {</div><div class='ctx'> 		amdgpu_ring_emit_gds_switch(ring, job-&gt;vmid, job-&gt;gds_base,</div><div class='ctx'> 					    job-&gt;gds_size, job-&gt;gws_base,</div><div class='hunk'>@@ -710,10 +844,13 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 					    job-&gt;oa_size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vm_flush_needed || pasid_mapping_needed) {</div><div class='del'>-		r = amdgpu_fence_emit(ring, &amp;fence, NULL, 0);</div><div class='add'>+	if (vm_flush_needed || pasid_mapping_needed || cleaner_shader_needed) {</div><div class='add'>+		r = amdgpu_fence_emit(ring, job-&gt;hw_vm_fence, 0);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='add'>+		fence = &amp;job-&gt;hw_vm_fence-&gt;base;</div><div class='add'>+		/* get a ref for the job */</div><div class='add'>+		dma_fence_get(fence);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (vm_flush_needed) {</div><div class='hunk'>@@ -732,6 +869,18 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 		id-&gt;pasid_mapping = dma_fence_get(fence);</div><div class='ctx'> 		mutex_unlock(&amp;id_mgr-&gt;lock);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Make sure that all other submissions wait for the cleaner shader to</div><div class='add'>+	 * finish before we push them to the HW.</div><div class='add'>+	 */</div><div class='add'>+	if (cleaner_shader_needed) {</div><div class='add'>+		trace_amdgpu_cleaner_shader(ring, fence);</div><div class='add'>+		mutex_lock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+		dma_fence_put(isolation-&gt;spearhead);</div><div class='add'>+		isolation-&gt;spearhead = dma_fence_get(fence);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;enforce_isolation_mutex);</div><div class='add'>+	}</div><div class='ctx'> 	dma_fence_put(fence);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_patch_cond_exec(ring, patch);</div><div class='hunk'>@@ -741,6 +890,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,</div><div class='ctx'> 		amdgpu_ring_emit_switch_buffer(ring);</div><div class='ctx'> 		amdgpu_ring_emit_switch_buffer(ring);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_ib_end(ring);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -822,6 +972,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev,</div><div class='ctx'> 	LIST_HEAD(relocated);</div><div class='ctx'> 	int r, idx;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_assert_locked(vm);</div><div class='add'>+</div><div class='ctx'> 	spin_lock(&amp;vm-&gt;status_lock);</div><div class='ctx'> 	list_splice_init(&amp;vm-&gt;relocated, &amp;relocated);</div><div class='ctx'> 	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='hunk'>@@ -837,7 +989,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev,</div><div class='ctx'> 	params.vm = vm;</div><div class='ctx'> 	params.immediate = immediate;</div><div class='ctx'> </div><div class='del'>-	r = vm-&gt;update_funcs-&gt;prepare(&amp;params, NULL, AMDGPU_SYNC_EXPLICIT);</div><div class='add'>+	r = vm-&gt;update_funcs-&gt;prepare(&amp;params, NULL,</div><div class='add'>+				      AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -886,6 +1039,46 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vm_tlb_flush - prepare TLB flush</div><div class='add'>+ *</div><div class='add'>+ * @params: parameters for update</div><div class='add'>+ * @fence: input fence to sync TLB flush with</div><div class='add'>+ * @tlb_cb: the callback structure</div><div class='add'>+ *</div><div class='add'>+ * Increments the tlb sequence to make sure that future CS execute a VM flush.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,</div><div class='add'>+		    struct dma_fence **fence,</div><div class='add'>+		    struct amdgpu_vm_tlb_seq_struct *tlb_cb)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm *vm = params-&gt;vm;</div><div class='add'>+</div><div class='add'>+	tlb_cb-&gt;vm = vm;</div><div class='add'>+	if (!fence || !*fence) {</div><div class='add'>+		amdgpu_vm_tlb_seq_cb(NULL, &amp;tlb_cb-&gt;cb);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dma_fence_add_callback(*fence, &amp;tlb_cb-&gt;cb,</div><div class='add'>+				    amdgpu_vm_tlb_seq_cb)) {</div><div class='add'>+		dma_fence_put(vm-&gt;last_tlb_flush);</div><div class='add'>+		vm-&gt;last_tlb_flush = dma_fence_get(*fence);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_vm_tlb_seq_cb(NULL, &amp;tlb_cb-&gt;cb);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Prepare a TLB flush fence to be attached to PTs */</div><div class='add'>+	if (!params-&gt;unlocked) {</div><div class='add'>+		amdgpu_vm_tlb_fence_create(params-&gt;adev, vm, fence);</div><div class='add'>+</div><div class='add'>+		/* Makes sure no PD/PT is freed before the flush */</div><div class='add'>+		dma_resv_add_fence(vm-&gt;root.bo-&gt;tbo.base.resv, *fence,</div><div class='add'>+				   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vm_update_range - update a range in the vm page table</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer to use for commands</div><div class='hunk'>@@ -894,7 +1087,7 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,</div><div class='ctx'>  * @unlocked: unlocked invalidation during MM callback</div><div class='ctx'>  * @flush_tlb: trigger tlb invalidation after update completed</div><div class='ctx'>  * @allow_override: change MTYPE for local NUMA nodes</div><div class='del'>- * @resv: fences we need to sync to</div><div class='add'>+ * @sync: fences we need to sync to</div><div class='ctx'>  * @start: start of mapped range</div><div class='ctx'>  * @last: last mapped entry</div><div class='ctx'>  * @flags: flags for the entries</div><div class='hunk'>@@ -910,16 +1103,16 @@ static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,</div><div class='ctx'>  * 0 for success, negative erro code for failure.</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-			   bool immediate, bool unlocked, bool flush_tlb, bool allow_override,</div><div class='del'>-			   struct dma_resv *resv, uint64_t start, uint64_t last,</div><div class='del'>-			   uint64_t flags, uint64_t offset, uint64_t vram_base,</div><div class='add'>+			   bool immediate, bool unlocked, bool flush_tlb,</div><div class='add'>+			   bool allow_override, struct amdgpu_sync *sync,</div><div class='add'>+			   uint64_t start, uint64_t last, uint64_t flags,</div><div class='add'>+			   uint64_t offset, uint64_t vram_base,</div><div class='ctx'> 			   struct ttm_resource *res, dma_addr_t *pages_addr,</div><div class='ctx'> 			   struct dma_fence **fence)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_vm_update_params params;</div><div class='ctx'> 	struct amdgpu_vm_tlb_seq_struct *tlb_cb;</div><div class='add'>+	struct amdgpu_vm_update_params params;</div><div class='ctx'> 	struct amdgpu_res_cursor cursor;</div><div class='del'>-	enum amdgpu_sync_mode sync_mode;</div><div class='ctx'> 	int r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (!drm_dev_enter(adev_to_drm(adev), &amp;idx))</div><div class='hunk'>@@ -927,8 +1120,8 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> </div><div class='ctx'> 	tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);</div><div class='ctx'> 	if (!tlb_cb) {</div><div class='del'>-		r = -ENOMEM;</div><div class='del'>-		goto error_unlock;</div><div class='add'>+		drm_dev_exit(idx);</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,</div><div class='hunk'>@@ -948,15 +1141,9 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	params.immediate = immediate;</div><div class='ctx'> 	params.pages_addr = pages_addr;</div><div class='ctx'> 	params.unlocked = unlocked;</div><div class='add'>+	params.needs_flush = flush_tlb;</div><div class='ctx'> 	params.allow_override = allow_override;</div><div class='del'>-</div><div class='del'>-	/* Implicitly sync to command submissions in the same VM before</div><div class='del'>-	 * unmapping. Sync to moving fences before mapping.</div><div class='del'>-	 */</div><div class='del'>-	if (!(flags &amp; AMDGPU_PTE_VALID))</div><div class='del'>-		sync_mode = AMDGPU_SYNC_EQ_OWNER;</div><div class='del'>-	else</div><div class='del'>-		sync_mode = AMDGPU_SYNC_EXPLICIT;</div><div class='add'>+	INIT_LIST_HEAD(&amp;params.tlb_flush_waitlist);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_vm_eviction_lock(vm);</div><div class='ctx'> 	if (vm-&gt;evicting) {</div><div class='hunk'>@@ -972,7 +1159,8 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		dma_fence_put(tmp);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = vm-&gt;update_funcs-&gt;prepare(&amp;params, resv, sync_mode);</div><div class='add'>+	r = vm-&gt;update_funcs-&gt;prepare(&amp;params, sync,</div><div class='add'>+				      AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error_free;</div><div class='ctx'> </div><div class='hunk'>@@ -1015,7 +1203,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 				params.pages_addr = NULL;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-		} else if (flags &amp; (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {</div><div class='add'>+		} else if (flags &amp; (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) {</div><div class='ctx'> 			addr = vram_base + cursor.start;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			addr = 0;</div><div class='hunk'>@@ -1031,74 +1219,28 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = vm-&gt;update_funcs-&gt;commit(&amp;params, fence);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_free;</div><div class='ctx'> </div><div class='del'>-	if (flush_tlb || params.table_freed) {</div><div class='del'>-		tlb_cb-&gt;vm = vm;</div><div class='del'>-		if (fence &amp;&amp; *fence &amp;&amp;</div><div class='del'>-		    !dma_fence_add_callback(*fence, &amp;tlb_cb-&gt;cb,</div><div class='del'>-					   amdgpu_vm_tlb_seq_cb)) {</div><div class='del'>-			dma_fence_put(vm-&gt;last_tlb_flush);</div><div class='del'>-			vm-&gt;last_tlb_flush = dma_fence_get(*fence);</div><div class='del'>-		} else {</div><div class='del'>-			amdgpu_vm_tlb_seq_cb(NULL, &amp;tlb_cb-&gt;cb);</div><div class='del'>-		}</div><div class='add'>+	if (params.needs_flush) {</div><div class='add'>+		amdgpu_vm_tlb_flush(&amp;params, fence, tlb_cb);</div><div class='ctx'> 		tlb_cb = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_pt_free_list(adev, &amp;params);</div><div class='add'>+</div><div class='ctx'> error_free:</div><div class='ctx'> 	kfree(tlb_cb);</div><div class='del'>-</div><div class='del'>-error_unlock:</div><div class='ctx'> 	amdgpu_vm_eviction_unlock(vm);</div><div class='ctx'> 	drm_dev_exit(idx);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,</div><div class='del'>-				    struct amdgpu_mem_stats *stats)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_vm *vm = bo_va-&gt;base.vm;</div><div class='del'>-	struct amdgpu_bo *bo = bo_va-&gt;base.bo;</div><div class='del'>-</div><div class='del'>-	if (!bo)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * For now ignore BOs which are currently locked and potentially</div><div class='del'>-	 * changing their location.</div><div class='del'>-	 */</div><div class='del'>-	if (bo-&gt;tbo.base.resv != vm-&gt;root.bo-&gt;tbo.base.resv &amp;&amp;</div><div class='del'>-	    !dma_resv_trylock(bo-&gt;tbo.base.resv))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_get_memory(bo, stats);</div><div class='del'>-	if (bo-&gt;tbo.base.resv != vm-&gt;root.bo-&gt;tbo.base.resv)</div><div class='del'>-	    dma_resv_unlock(bo-&gt;tbo.base.resv);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void amdgpu_vm_get_memory(struct amdgpu_vm *vm,</div><div class='del'>-			  struct amdgpu_mem_stats *stats)</div><div class='add'>+			  struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM])</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo_va *bo_va, *tmp;</div><div class='del'>-</div><div class='ctx'> 	spin_lock(&amp;vm-&gt;status_lock);</div><div class='del'>-	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;idle, base.vm_status)</div><div class='del'>-		amdgpu_vm_bo_get_memory(bo_va, stats);</div><div class='del'>-</div><div class='del'>-	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;evicted, base.vm_status)</div><div class='del'>-		amdgpu_vm_bo_get_memory(bo_va, stats);</div><div class='del'>-</div><div class='del'>-	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;relocated, base.vm_status)</div><div class='del'>-		amdgpu_vm_bo_get_memory(bo_va, stats);</div><div class='del'>-</div><div class='del'>-	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;moved, base.vm_status)</div><div class='del'>-		amdgpu_vm_bo_get_memory(bo_va, stats);</div><div class='del'>-</div><div class='del'>-	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;invalidated, base.vm_status)</div><div class='del'>-		amdgpu_vm_bo_get_memory(bo_va, stats);</div><div class='del'>-</div><div class='del'>-	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;done, base.vm_status)</div><div class='del'>-		amdgpu_vm_bo_get_memory(bo_va, stats);</div><div class='add'>+	memcpy(stats, vm-&gt;stats, sizeof(*stats) * __AMDGPU_PL_NUM);</div><div class='ctx'> 	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1120,24 +1262,41 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 	struct amdgpu_bo *bo = bo_va-&gt;base.bo;</div><div class='ctx'> 	struct amdgpu_vm *vm = bo_va-&gt;base.vm;</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *mapping;</div><div class='add'>+	struct dma_fence **last_update;</div><div class='ctx'> 	dma_addr_t *pages_addr = NULL;</div><div class='ctx'> 	struct ttm_resource *mem;</div><div class='del'>-	struct dma_fence **last_update;</div><div class='add'>+	struct amdgpu_sync sync;</div><div class='ctx'> 	bool flush_tlb = clear;</div><div class='del'>-	bool uncached;</div><div class='del'>-	struct dma_resv *resv;</div><div class='ctx'> 	uint64_t vram_base;</div><div class='ctx'> 	uint64_t flags;</div><div class='add'>+	bool uncached;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (clear || !bo) {</div><div class='add'>+	amdgpu_sync_create(&amp;sync);</div><div class='add'>+	if (clear) {</div><div class='ctx'> 		mem = NULL;</div><div class='del'>-		resv = vm-&gt;root.bo-&gt;tbo.base.resv;</div><div class='add'>+</div><div class='add'>+		/* Implicitly sync to command submissions in the same VM before</div><div class='add'>+		 * unmapping.</div><div class='add'>+		 */</div><div class='add'>+		r = amdgpu_sync_resv(adev, &amp;sync, vm-&gt;root.bo-&gt;tbo.base.resv,</div><div class='add'>+				     AMDGPU_SYNC_EQ_OWNER, vm);</div><div class='add'>+		if (r)</div><div class='add'>+			goto error_free;</div><div class='add'>+		if (bo) {</div><div class='add'>+			r = amdgpu_sync_kfd(&amp;sync, bo-&gt;tbo.base.resv);</div><div class='add'>+			if (r)</div><div class='add'>+				goto error_free;</div><div class='add'>+		}</div><div class='add'>+	} else if (!bo) {</div><div class='add'>+		mem = NULL;</div><div class='add'>+</div><div class='add'>+		/* PRT map operations don't need to sync to anything. */</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='ctx'> 		struct drm_gem_object *obj = &amp;bo-&gt;tbo.base;</div><div class='ctx'> </div><div class='del'>-		resv = bo-&gt;tbo.base.resv;</div><div class='del'>-		if (obj-&gt;import_attach &amp;&amp; bo_va-&gt;is_xgmi) {</div><div class='add'>+		if (drm_gem_is_imported(obj) &amp;&amp; bo_va-&gt;is_xgmi) {</div><div class='ctx'> 			struct dma_buf *dma_buf = obj-&gt;import_attach-&gt;dmabuf;</div><div class='ctx'> 			struct drm_gem_object *gobj = dma_buf-&gt;priv;</div><div class='ctx'> 			struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);</div><div class='hunk'>@@ -1150,6 +1309,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 		if (mem &amp;&amp; (mem-&gt;mem_type == TTM_PL_TT ||</div><div class='ctx'> 			    mem-&gt;mem_type == AMDGPU_PL_PREEMPT))</div><div class='ctx'> 			pages_addr = bo-&gt;tbo.ttm-&gt;dma_address;</div><div class='add'>+</div><div class='add'>+		/* Implicitly sync to moving fences before mapping anything */</div><div class='add'>+		r = amdgpu_sync_resv(adev, &amp;sync, bo-&gt;tbo.base.resv,</div><div class='add'>+				     AMDGPU_SYNC_EXPLICIT, vm);</div><div class='add'>+		if (r)</div><div class='add'>+			goto error_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (bo) {</div><div class='hunk'>@@ -1169,8 +1334,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 		uncached = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (clear || (bo &amp;&amp; bo-&gt;tbo.base.resv ==</div><div class='del'>-		      vm-&gt;root.bo-&gt;tbo.base.resv))</div><div class='add'>+	if (clear || amdgpu_vm_is_bo_always_valid(vm, bo))</div><div class='ctx'> 		last_update = &amp;vm-&gt;last_update;</div><div class='ctx'> 	else</div><div class='ctx'> 		last_update = &amp;bo_va-&gt;last_pt_update;</div><div class='hunk'>@@ -1189,34 +1353,34 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 		/* normally,bo_va-&gt;flags only contians READABLE and WIRTEABLE bit go here</div><div class='ctx'> 		 * but in case of something, we filter the flags in first place</div><div class='ctx'> 		 */</div><div class='del'>-		if (!(mapping-&gt;flags &amp; AMDGPU_PTE_READABLE))</div><div class='add'>+		if (!(mapping-&gt;flags &amp; AMDGPU_VM_PAGE_READABLE))</div><div class='ctx'> 			update_flags &amp;= ~AMDGPU_PTE_READABLE;</div><div class='del'>-		if (!(mapping-&gt;flags &amp; AMDGPU_PTE_WRITEABLE))</div><div class='add'>+		if (!(mapping-&gt;flags &amp; AMDGPU_VM_PAGE_WRITEABLE))</div><div class='ctx'> 			update_flags &amp;= ~AMDGPU_PTE_WRITEABLE;</div><div class='ctx'> </div><div class='ctx'> 		/* Apply ASIC specific mapping flags */</div><div class='del'>-		amdgpu_gmc_get_vm_pte(adev, mapping, &amp;update_flags);</div><div class='add'>+		amdgpu_gmc_get_vm_pte(adev, vm, bo, mapping-&gt;flags,</div><div class='add'>+				      &amp;update_flags);</div><div class='ctx'> </div><div class='ctx'> 		trace_amdgpu_vm_bo_update(mapping);</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,</div><div class='del'>-					   !uncached, resv, mapping-&gt;start, mapping-&gt;last,</div><div class='del'>-					   update_flags, mapping-&gt;offset,</div><div class='del'>-					   vram_base, mem, pages_addr,</div><div class='del'>-					   last_update);</div><div class='add'>+					   !uncached, &amp;sync, mapping-&gt;start,</div><div class='add'>+					   mapping-&gt;last, update_flags,</div><div class='add'>+					   mapping-&gt;offset, vram_base, mem,</div><div class='add'>+					   pages_addr, last_update);</div><div class='ctx'> 		if (r)</div><div class='del'>-			return r;</div><div class='add'>+			goto error_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* If the BO is not in its preferred location add it back to</div><div class='ctx'> 	 * the evicted list so that it gets validated again on the</div><div class='ctx'> 	 * next command submission.</div><div class='ctx'> 	 */</div><div class='del'>-	if (bo &amp;&amp; bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv) {</div><div class='del'>-		uint32_t mem_type = bo-&gt;tbo.resource-&gt;mem_type;</div><div class='del'>-</div><div class='del'>-		if (!(bo-&gt;preferred_domains &amp;</div><div class='del'>-		      amdgpu_mem_type_to_domain(mem_type)))</div><div class='add'>+	if (amdgpu_vm_is_bo_always_valid(vm, bo)) {</div><div class='add'>+		if (bo-&gt;tbo.resource &amp;&amp;</div><div class='add'>+		    !(bo-&gt;preferred_domains &amp;</div><div class='add'>+		      amdgpu_mem_type_to_domain(bo-&gt;tbo.resource-&gt;mem_type)))</div><div class='ctx'> 			amdgpu_vm_bo_evicted(&amp;bo_va-&gt;base);</div><div class='ctx'> 		else</div><div class='ctx'> 			amdgpu_vm_bo_idle(&amp;bo_va-&gt;base);</div><div class='hunk'>@@ -1233,7 +1397,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 			trace_amdgpu_vm_bo_mapping(mapping);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+error_free:</div><div class='add'>+	amdgpu_sync_free(&amp;sync);</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1335,7 +1501,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,</div><div class='ctx'> 				   struct amdgpu_bo_va_mapping *mapping,</div><div class='ctx'> 				   struct dma_fence *fence)</div><div class='ctx'> {</div><div class='del'>-	if (mapping-&gt;flags &amp; AMDGPU_PTE_PRT)</div><div class='add'>+	if (mapping-&gt;flags &amp; AMDGPU_VM_PAGE_PRT)</div><div class='ctx'> 		amdgpu_vm_add_prt_cb(adev, fence);</div><div class='ctx'> 	kfree(mapping);</div><div class='ctx'> }</div><div class='hunk'>@@ -1380,25 +1546,34 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,</div><div class='ctx'> 			  struct amdgpu_vm *vm,</div><div class='ctx'> 			  struct dma_fence **fence)</div><div class='ctx'> {</div><div class='del'>-	struct dma_resv *resv = vm-&gt;root.bo-&gt;tbo.base.resv;</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *mapping;</div><div class='del'>-	uint64_t init_pte_value = 0;</div><div class='ctx'> 	struct dma_fence *f = NULL;</div><div class='add'>+	struct amdgpu_sync sync;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Implicitly sync to command submissions in the same VM before</div><div class='add'>+	 * unmapping.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_sync_create(&amp;sync);</div><div class='add'>+	r = amdgpu_sync_resv(adev, &amp;sync, vm-&gt;root.bo-&gt;tbo.base.resv,</div><div class='add'>+			     AMDGPU_SYNC_EQ_OWNER, vm);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_free;</div><div class='add'>+</div><div class='ctx'> 	while (!list_empty(&amp;vm-&gt;freed)) {</div><div class='ctx'> 		mapping = list_first_entry(&amp;vm-&gt;freed,</div><div class='ctx'> 			struct amdgpu_bo_va_mapping, list);</div><div class='ctx'> 		list_del(&amp;mapping-&gt;list);</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_vm_update_range(adev, vm, false, false, true, false,</div><div class='del'>-					   resv, mapping-&gt;start, mapping-&gt;last,</div><div class='del'>-					   init_pte_value, 0, 0, NULL, NULL,</div><div class='del'>-					   &amp;f);</div><div class='add'>+					   &amp;sync, mapping-&gt;start, mapping-&gt;last,</div><div class='add'>+					   0, 0, 0, NULL, NULL, &amp;f);</div><div class='ctx'> 		amdgpu_vm_free_mapping(adev, vm, mapping, f);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dma_fence_put(f);</div><div class='del'>-			return r;</div><div class='add'>+			goto error_free;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1409,7 +1584,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,</div><div class='ctx'> 		dma_fence_put(f);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+error_free:</div><div class='add'>+	amdgpu_sync_free(&amp;sync);</div><div class='add'>+	return r;</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1480,7 +1657,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,</div><div class='ctx'> 		 * validation</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (vm-&gt;is_compute_context &amp;&amp;</div><div class='del'>-		    bo_va-&gt;base.bo-&gt;tbo.base.import_attach &amp;&amp;</div><div class='add'>+		    drm_gem_is_imported(&amp;bo_va-&gt;base.bo-&gt;tbo.base) &amp;&amp;</div><div class='ctx'> 		    (!bo_va-&gt;base.bo-&gt;tbo.resource ||</div><div class='ctx'> 		     bo_va-&gt;base.bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_SYSTEM))</div><div class='ctx'> 			amdgpu_vm_bo_evicted_user(&amp;bo_va-&gt;base);</div><div class='hunk'>@@ -1603,16 +1780,46 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,</div><div class='ctx'> 	list_add(&amp;mapping-&gt;list, &amp;bo_va-&gt;invalids);</div><div class='ctx'> 	amdgpu_vm_it_insert(mapping, &amp;vm-&gt;va);</div><div class='ctx'> </div><div class='del'>-	if (mapping-&gt;flags &amp; AMDGPU_PTE_PRT)</div><div class='add'>+	if (mapping-&gt;flags &amp; AMDGPU_VM_PAGE_PRT)</div><div class='ctx'> 		amdgpu_vm_prt_get(adev);</div><div class='ctx'> </div><div class='del'>-	if (bo &amp;&amp; bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv &amp;&amp;</div><div class='del'>-	    !bo_va-&gt;base.moved) {</div><div class='add'>+	if (amdgpu_vm_is_bo_always_valid(vm, bo) &amp;&amp; !bo_va-&gt;base.moved)</div><div class='ctx'> 		amdgpu_vm_bo_moved(&amp;bo_va-&gt;base);</div><div class='del'>-	}</div><div class='add'>+</div><div class='ctx'> 	trace_amdgpu_vm_bo_map(bo_va, mapping);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Validate operation parameters to prevent potential abuse */</div><div class='add'>+static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,</div><div class='add'>+					  struct amdgpu_bo *bo,</div><div class='add'>+					  uint64_t saddr,</div><div class='add'>+					  uint64_t offset,</div><div class='add'>+					  uint64_t size)</div><div class='add'>+{</div><div class='add'>+	uint64_t tmp, lpfn;</div><div class='add'>+</div><div class='add'>+	if (saddr &amp; AMDGPU_GPU_PAGE_MASK</div><div class='add'>+	    || offset &amp; AMDGPU_GPU_PAGE_MASK</div><div class='add'>+	    || size &amp; AMDGPU_GPU_PAGE_MASK)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (check_add_overflow(saddr, size, &amp;tmp)</div><div class='add'>+	    || check_add_overflow(offset, size, &amp;tmp)</div><div class='add'>+	    || size == 0 /* which also leads to end &lt; begin */)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* make sure object fit at this offset */</div><div class='add'>+	if (bo &amp;&amp; offset + size &gt; amdgpu_bo_size(bo))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Ensure last pfn not exceed max_pfn */</div><div class='add'>+	lpfn = (saddr + size - 1) &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+	if (lpfn &gt;= adev-&gt;vm_manager.max_pfn)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_vm_bo_map - map bo inside a vm</div><div class='ctx'>  *</div><div class='hunk'>@@ -1633,27 +1840,20 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_vm_bo_map(struct amdgpu_device *adev,</div><div class='ctx'> 		     struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 		     uint64_t saddr, uint64_t offset,</div><div class='del'>-		     uint64_t size, uint64_t flags)</div><div class='add'>+		     uint64_t size, uint32_t flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *mapping, *tmp;</div><div class='ctx'> 	struct amdgpu_bo *bo = bo_va-&gt;base.bo;</div><div class='ctx'> 	struct amdgpu_vm *vm = bo_va-&gt;base.vm;</div><div class='ctx'> 	uint64_t eaddr;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='del'>-	/* validate the parameters */</div><div class='del'>-	if (saddr &amp; ~PAGE_MASK || offset &amp; ~PAGE_MASK || size &amp; ~PAGE_MASK)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	if (saddr + size &lt;= saddr || offset + size &lt;= offset)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	/* make sure object fit at this offset */</div><div class='del'>-	eaddr = saddr + size - 1;</div><div class='del'>-	if ((bo &amp;&amp; offset + size &gt; amdgpu_bo_size(bo)) ||</div><div class='del'>-	    (eaddr &gt;= adev-&gt;vm_manager.max_pfn &lt;&lt; AMDGPU_GPU_PAGE_SHIFT))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	saddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='del'>-	eaddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	tmp = amdgpu_vm_it_iter_first(&amp;vm-&gt;va, saddr, eaddr);</div><div class='ctx'> 	if (tmp) {</div><div class='hunk'>@@ -1699,24 +1899,16 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,</div><div class='ctx'> 			     struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 			     uint64_t saddr, uint64_t offset,</div><div class='del'>-			     uint64_t size, uint64_t flags)</div><div class='add'>+			     uint64_t size, uint32_t flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *mapping;</div><div class='ctx'> 	struct amdgpu_bo *bo = bo_va-&gt;base.bo;</div><div class='ctx'> 	uint64_t eaddr;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* validate the parameters */</div><div class='del'>-	if (saddr &amp; ~PAGE_MASK || offset &amp; ~PAGE_MASK || size &amp; ~PAGE_MASK)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	if (saddr + size &lt;= saddr || offset + size &lt;= offset)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	/* make sure object fit at this offset */</div><div class='del'>-	eaddr = saddr + size - 1;</div><div class='del'>-	if ((bo &amp;&amp; offset + size &gt; amdgpu_bo_size(bo)) ||</div><div class='del'>-	    (eaddr &gt;= adev-&gt;vm_manager.max_pfn &lt;&lt; AMDGPU_GPU_PAGE_SHIFT))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate all the needed memory */</div><div class='ctx'> 	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);</div><div class='hunk'>@@ -1730,7 +1922,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	saddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='del'>-	eaddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	mapping-&gt;start = saddr;</div><div class='ctx'> 	mapping-&gt;last = eaddr;</div><div class='hunk'>@@ -1763,6 +1955,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *mapping;</div><div class='ctx'> 	struct amdgpu_vm *vm = bo_va-&gt;base.vm;</div><div class='ctx'> 	bool valid = true;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='ctx'> 	saddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> </div><div class='hunk'>@@ -1783,6 +1976,17 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,</div><div class='ctx'> 			return -ENOENT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* It's unlikely to happen that the mapping userq hasn't been idled</div><div class='add'>+	 * during user requests GEM unmap IOCTL except for forcing the unmap</div><div class='add'>+	 * from user space.</div><div class='add'>+	 */</div><div class='add'>+	if (unlikely(atomic_read(&amp;bo_va-&gt;userq_va_mapped) &gt; 0)) {</div><div class='add'>+		r = amdgpu_userq_gem_va_unmap_validate(adev, mapping, saddr);</div><div class='add'>+		if (unlikely(r == -EBUSY))</div><div class='add'>+			dev_warn_once(adev-&gt;dev,</div><div class='add'>+				      "Attempt to unmap an active userq buffer\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	list_del(&amp;mapping-&gt;list);</div><div class='ctx'> 	amdgpu_vm_it_remove(mapping, &amp;vm-&gt;va);</div><div class='ctx'> 	mapping-&gt;bo_va = NULL;</div><div class='hunk'>@@ -1817,10 +2021,14 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,</div><div class='ctx'> 	struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;</div><div class='ctx'> 	LIST_HEAD(removed);</div><div class='ctx'> 	uint64_t eaddr;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-	eaddr = saddr + size - 1;</div><div class='ctx'> 	saddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='del'>-	eaddr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate all the needed memory */</div><div class='ctx'> 	before = kzalloc(sizeof(*before), GFP_KERNEL);</div><div class='hunk'>@@ -1885,10 +2093,10 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,</div><div class='ctx'> 		struct amdgpu_bo *bo = before-&gt;bo_va-&gt;base.bo;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_vm_it_insert(before, &amp;vm-&gt;va);</div><div class='del'>-		if (before-&gt;flags &amp; AMDGPU_PTE_PRT)</div><div class='add'>+		if (before-&gt;flags &amp; AMDGPU_VM_PAGE_PRT)</div><div class='ctx'> 			amdgpu_vm_prt_get(adev);</div><div class='ctx'> </div><div class='del'>-		if (bo &amp;&amp; bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv &amp;&amp;</div><div class='add'>+		if (amdgpu_vm_is_bo_always_valid(vm, bo) &amp;&amp;</div><div class='ctx'> 		    !before-&gt;bo_va-&gt;base.moved)</div><div class='ctx'> 			amdgpu_vm_bo_moved(&amp;before-&gt;bo_va-&gt;base);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1900,10 +2108,10 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,</div><div class='ctx'> 		struct amdgpu_bo *bo = after-&gt;bo_va-&gt;base.bo;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_vm_it_insert(after, &amp;vm-&gt;va);</div><div class='del'>-		if (after-&gt;flags &amp; AMDGPU_PTE_PRT)</div><div class='add'>+		if (after-&gt;flags &amp; AMDGPU_VM_PAGE_PRT)</div><div class='ctx'> 			amdgpu_vm_prt_get(adev);</div><div class='ctx'> </div><div class='del'>-		if (bo &amp;&amp; bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv &amp;&amp;</div><div class='add'>+		if (amdgpu_vm_is_bo_always_valid(vm, bo) &amp;&amp;</div><div class='ctx'> 		    !after-&gt;bo_va-&gt;base.moved)</div><div class='ctx'> 			amdgpu_vm_bo_moved(&amp;after-&gt;bo_va-&gt;base);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1983,7 +2191,7 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	if (bo) {</div><div class='ctx'> 		dma_resv_assert_held(bo-&gt;tbo.base.resv);</div><div class='del'>-		if (bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv)</div><div class='add'>+		if (amdgpu_vm_is_bo_always_valid(vm, bo))</div><div class='ctx'> 			ttm_bo_set_bulk_move(&amp;bo-&gt;tbo, NULL);</div><div class='ctx'> </div><div class='ctx'> 		for (base = &amp;bo_va-&gt;base.bo-&gt;vm_bo; *base;</div><div class='hunk'>@@ -1991,6 +2199,7 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev,</div><div class='ctx'> 			if (*base != &amp;bo_va-&gt;base)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='add'>+			amdgpu_vm_update_stats(*base, bo-&gt;tbo.resource, -1);</div><div class='ctx'> 			*base = bo_va-&gt;base.next;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2059,25 +2268,19 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo)</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_vm_bo_invalidate - mark the bo as invalid</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='ctx'>  * @bo: amdgpu buffer object</div><div class='ctx'>  * @evicted: is the BO evicted</div><div class='ctx'>  *</div><div class='ctx'>  * Mark @bo as invalid.</div><div class='ctx'>  */</div><div class='del'>-void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,</div><div class='del'>-			     struct amdgpu_bo *bo, bool evicted)</div><div class='add'>+void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vm_bo_base *bo_base;</div><div class='ctx'> </div><div class='del'>-	/* shadow bo doesn't have bo base, its validation needs its parent */</div><div class='del'>-	if (bo-&gt;parent &amp;&amp; (amdgpu_bo_shadowed(bo-&gt;parent) == bo))</div><div class='del'>-		bo = bo-&gt;parent;</div><div class='del'>-</div><div class='ctx'> 	for (bo_base = bo-&gt;vm_bo; bo_base; bo_base = bo_base-&gt;next) {</div><div class='ctx'> 		struct amdgpu_vm *vm = bo_base-&gt;vm;</div><div class='ctx'> </div><div class='del'>-		if (evicted &amp;&amp; bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv) {</div><div class='add'>+		if (evicted &amp;&amp; amdgpu_vm_is_bo_always_valid(vm, bo)) {</div><div class='ctx'> 			amdgpu_vm_bo_evicted(bo_base);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2088,7 +2291,7 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 		if (bo-&gt;tbo.type == ttm_bo_type_kernel)</div><div class='ctx'> 			amdgpu_vm_bo_relocated(bo_base);</div><div class='del'>-		else if (bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv)</div><div class='add'>+		else if (amdgpu_vm_is_bo_always_valid(vm, bo))</div><div class='ctx'> 			amdgpu_vm_bo_moved(bo_base);</div><div class='ctx'> 		else</div><div class='ctx'> 			amdgpu_vm_bo_invalidated(bo_base);</div><div class='hunk'>@@ -2096,6 +2299,32 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vm_bo_move - handle BO move</div><div class='add'>+ *</div><div class='add'>+ * @bo: amdgpu buffer object</div><div class='add'>+ * @new_mem: the new placement of the BO move</div><div class='add'>+ * @evicted: is the BO evicted</div><div class='add'>+ *</div><div class='add'>+ * Update the memory stats for the new placement and mark @bo as invalid.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem,</div><div class='add'>+		       bool evicted)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm_bo_base *bo_base;</div><div class='add'>+</div><div class='add'>+	for (bo_base = bo-&gt;vm_bo; bo_base; bo_base = bo_base-&gt;next) {</div><div class='add'>+		struct amdgpu_vm *vm = bo_base-&gt;vm;</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;vm-&gt;status_lock);</div><div class='add'>+		amdgpu_vm_update_stats_locked(bo_base, bo-&gt;tbo.resource, -1);</div><div class='add'>+		amdgpu_vm_update_stats_locked(bo_base, new_mem, +1);</div><div class='add'>+		spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_vm_bo_invalidate(bo, evicted);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vm_get_block_size - calculate VM page table size as power of two</div><div class='ctx'>  *</div><div class='ctx'>  * @vm_size: VM size</div><div class='hunk'>@@ -2165,7 +2394,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,</div><div class='ctx'> 		phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +</div><div class='ctx'> 			       (1 &lt;&lt; 30) - 1) &gt;&gt; 30;</div><div class='ctx'> 		vm_size = roundup_pow_of_two(</div><div class='del'>-			min(max(phys_ram_gb * 3, min_vm_size), max_size));</div><div class='add'>+			clamp(phys_ram_gb * 3, min_vm_size, max_size));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;vm_manager.max_pfn = (uint64_t)vm_size &lt;&lt; 18;</div><div class='hunk'>@@ -2204,10 +2433,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,</div><div class='ctx'> 	else</div><div class='ctx'> 		adev-&gt;vm_manager.fragment_size = amdgpu_vm_fragment_size;</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",</div><div class='del'>-		 vm_size, adev-&gt;vm_manager.num_level + 1,</div><div class='del'>-		 adev-&gt;vm_manager.block_size,</div><div class='del'>-		 adev-&gt;vm_manager.fragment_size);</div><div class='add'>+	dev_info(</div><div class='add'>+		adev-&gt;dev,</div><div class='add'>+		"vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",</div><div class='add'>+		vm_size, adev-&gt;vm_manager.num_level + 1,</div><div class='add'>+		adev-&gt;vm_manager.block_size, adev-&gt;vm_manager.fragment_size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2218,13 +2448,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,</div><div class='ctx'>  */</div><div class='ctx'> long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)</div><div class='ctx'> {</div><div class='del'>-	timeout = dma_resv_wait_timeout(vm-&gt;root.bo-&gt;tbo.base.resv,</div><div class='del'>-					DMA_RESV_USAGE_BOOKKEEP,</div><div class='del'>-					true, timeout);</div><div class='add'>+	timeout = drm_sched_entity_flush(&amp;vm-&gt;immediate, timeout);</div><div class='ctx'> 	if (timeout &lt;= 0)</div><div class='ctx'> 		return timeout;</div><div class='ctx'> </div><div class='del'>-	return dma_fence_wait_timeout(vm-&gt;last_unlocked, true, timeout);</div><div class='add'>+	return drm_sched_entity_flush(&amp;vm-&gt;delayed, timeout);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_vm_destroy_task_info(struct kref *kref)</div><div class='hunk'>@@ -2256,7 +2484,8 @@ amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)</div><div class='ctx'> {</div><div class='del'>-	kref_put(&amp;task_info-&gt;refcount, amdgpu_vm_destroy_task_info);</div><div class='add'>+	if (task_info)</div><div class='add'>+		kref_put(&amp;task_info-&gt;refcount, amdgpu_vm_destroy_task_info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2316,11 +2545,11 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)</div><div class='ctx'> 	if (!vm-&gt;task_info)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (vm-&gt;task_info-&gt;pid == current-&gt;pid)</div><div class='add'>+	if (vm-&gt;task_info-&gt;task.pid == current-&gt;pid)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	vm-&gt;task_info-&gt;pid = current-&gt;pid;</div><div class='del'>-	get_task_comm(vm-&gt;task_info-&gt;task_name, current);</div><div class='add'>+	vm-&gt;task_info-&gt;task.pid = current-&gt;pid;</div><div class='add'>+	get_task_comm(vm-&gt;task_info-&gt;task.comm, current);</div><div class='ctx'> </div><div class='ctx'> 	if (current-&gt;group_leader-&gt;mm != current-&gt;mm)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -2335,6 +2564,7 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @vm: requested vm</div><div class='ctx'>  * @xcp_id: GPU partition selection id</div><div class='add'>+ * @pasid: the pasid the VM is using on this GPU</div><div class='ctx'>  *</div><div class='ctx'>  * Init @vm fields.</div><div class='ctx'>  *</div><div class='hunk'>@@ -2342,7 +2572,7 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)</div><div class='ctx'>  * 0 for success, error for failure.</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-		   int32_t xcp_id)</div><div class='add'>+		   int32_t xcp_id, uint32_t pasid)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo *root_bo;</div><div class='ctx'> 	struct amdgpu_bo_vm *root;</div><div class='hunk'>@@ -2360,21 +2590,21 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	spin_lock_init(&amp;vm-&gt;status_lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;vm-&gt;freed);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;vm-&gt;done);</div><div class='del'>-	INIT_LIST_HEAD(&amp;vm-&gt;pt_freed);</div><div class='del'>-	INIT_WORK(&amp;vm-&gt;pt_free_work, amdgpu_vm_pt_free_work);</div><div class='ctx'> 	INIT_KFIFO(vm-&gt;faults);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_vm_init_entities(adev, vm);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	ttm_lru_bulk_move_init(&amp;vm-&gt;lru_bulk_move);</div><div class='add'>+</div><div class='ctx'> 	vm-&gt;is_compute_context = false;</div><div class='ctx'> </div><div class='ctx'> 	vm-&gt;use_cpu_for_update = !!(adev-&gt;vm_manager.vm_update_mode &amp;</div><div class='ctx'> 				    AMDGPU_VM_USE_CPU_FOR_GFX);</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG_DRIVER("VM update mode is %s\n",</div><div class='del'>-			 vm-&gt;use_cpu_for_update ? "CPU" : "SDMA");</div><div class='add'>+	dev_dbg(adev-&gt;dev, "VM update mode is %s\n",</div><div class='add'>+		vm-&gt;use_cpu_for_update ? "CPU" : "SDMA");</div><div class='ctx'> 	WARN_ONCE((vm-&gt;use_cpu_for_update &amp;&amp;</div><div class='ctx'> 		   !amdgpu_gmc_vram_full_visible(&amp;adev-&gt;gmc)),</div><div class='ctx'> 		  "CPU update of VM recommended only for large BAR system\n");</div><div class='hunk'>@@ -2387,10 +2617,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	vm-&gt;last_update = dma_fence_get_stub();</div><div class='ctx'> 	vm-&gt;last_unlocked = dma_fence_get_stub();</div><div class='ctx'> 	vm-&gt;last_tlb_flush = dma_fence_get_stub();</div><div class='del'>-	vm-&gt;generation = 0;</div><div class='add'>+	vm-&gt;generation = amdgpu_vm_generation(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;vm-&gt;eviction_lock);</div><div class='ctx'> 	vm-&gt;evicting = false;</div><div class='add'>+	vm-&gt;tlb_fence_context = dma_fence_context_alloc(1);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_vm_pt_create(adev, vm, adev-&gt;vm_manager.root_level,</div><div class='ctx'> 				false, &amp;root, xcp_id);</div><div class='hunk'>@@ -2400,7 +2631,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	root_bo = amdgpu_bo_ref(&amp;root-&gt;bo);</div><div class='ctx'> 	r = amdgpu_bo_reserve(root_bo, true);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		amdgpu_bo_unref(&amp;root-&gt;shadow);</div><div class='ctx'> 		amdgpu_bo_unref(&amp;root_bo);</div><div class='ctx'> 		goto error_free_delayed;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2416,7 +2646,16 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_vm_create_task_info(vm);</div><div class='ctx'> 	if (r)</div><div class='del'>-		DRM_DEBUG("Failed to create task info for VM\n");</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Failed to create task info for VM\n");</div><div class='add'>+</div><div class='add'>+	/* Store new PASID in XArray (if non-zero) */</div><div class='add'>+	if (pasid != 0) {</div><div class='add'>+		r = xa_err(xa_store_irq(&amp;adev-&gt;vm_manager.pasids, pasid, vm, GFP_KERNEL));</div><div class='add'>+		if (r &lt; 0)</div><div class='add'>+			goto error_free_root;</div><div class='add'>+</div><div class='add'>+		vm-&gt;pasid = pasid;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='ctx'> 	amdgpu_bo_unref(&amp;root_bo);</div><div class='hunk'>@@ -2424,6 +2663,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> error_free_root:</div><div class='add'>+	/* If PASID was partially set, erase it from XArray before failing */</div><div class='add'>+	if (vm-&gt;pasid != 0) {</div><div class='add'>+		xa_erase_irq(&amp;adev-&gt;vm_manager.pasids, vm-&gt;pasid);</div><div class='add'>+		vm-&gt;pasid = 0;</div><div class='add'>+	}</div><div class='ctx'> 	amdgpu_vm_pt_free_root(adev, vm);</div><div class='ctx'> 	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='ctx'> 	amdgpu_bo_unref(&amp;root_bo);</div><div class='hunk'>@@ -2431,6 +2675,7 @@ error_free_root:</div><div class='ctx'> error_free_delayed:</div><div class='ctx'> 	dma_fence_put(vm-&gt;last_tlb_flush);</div><div class='ctx'> 	dma_fence_put(vm-&gt;last_unlocked);</div><div class='add'>+	ttm_lru_bulk_move_fini(&amp;adev-&gt;mman.bdev, &amp;vm-&gt;lru_bulk_move);</div><div class='ctx'> 	amdgpu_vm_fini_entities(vm);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -2466,8 +2711,8 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> 	/* Update VM state */</div><div class='ctx'> 	vm-&gt;use_cpu_for_update = !!(adev-&gt;vm_manager.vm_update_mode &amp;</div><div class='ctx'> 				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);</div><div class='del'>-	DRM_DEBUG_DRIVER("VM update mode is %s\n",</div><div class='del'>-			 vm-&gt;use_cpu_for_update ? "CPU" : "SDMA");</div><div class='add'>+	dev_dbg(adev-&gt;dev, "VM update mode is %s\n",</div><div class='add'>+		vm-&gt;use_cpu_for_update ? "CPU" : "SDMA");</div><div class='ctx'> 	WARN_ONCE((vm-&gt;use_cpu_for_update &amp;&amp;</div><div class='ctx'> 		   !amdgpu_gmc_vram_full_visible(&amp;adev-&gt;gmc)),</div><div class='ctx'> 		  "CPU update of VM recommended only for large BAR system\n");</div><div class='hunk'>@@ -2492,28 +2737,19 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> 	vm-&gt;last_update = dma_fence_get_stub();</div><div class='ctx'> 	vm-&gt;is_compute_context = true;</div><div class='ctx'> </div><div class='del'>-	/* Free the shadow bo for compute VM */</div><div class='del'>-	amdgpu_bo_unref(&amp;to_amdgpu_bo_vm(vm-&gt;root.bo)-&gt;shadow);</div><div class='del'>-</div><div class='del'>-	goto unreserve_bo;</div><div class='del'>-</div><div class='ctx'> unreserve_bo:</div><div class='ctx'> 	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_vm_release_compute - release a compute vm</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute</div><div class='del'>- *</div><div class='del'>- * This is a correspondant of amdgpu_vm_make_compute. It decouples compute</div><div class='del'>- * pasid from vm. Compute should stop use of vm after this call.</div><div class='del'>- */</div><div class='del'>-void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='add'>+static int amdgpu_vm_stats_is_zero(struct amdgpu_vm *vm)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_vm_set_pasid(adev, vm, 0);</div><div class='del'>-	vm-&gt;is_compute_context = false;</div><div class='add'>+	for (int i = 0; i &lt; __AMDGPU_PL_NUM; ++i) {</div><div class='add'>+		if (!(drm_memory_stats_is_zero(&amp;vm-&gt;stats[i].drm) &amp;&amp;</div><div class='add'>+		      vm-&gt;stats[i].evicted == 0))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2535,12 +2771,13 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);</div><div class='ctx'> </div><div class='del'>-	flush_work(&amp;vm-&gt;pt_free_work);</div><div class='del'>-</div><div class='ctx'> 	root = amdgpu_bo_ref(vm-&gt;root.bo);</div><div class='ctx'> 	amdgpu_bo_reserve(root, true);</div><div class='del'>-	amdgpu_vm_put_task_info(vm-&gt;task_info);</div><div class='del'>-	amdgpu_vm_set_pasid(adev, vm, 0);</div><div class='add'>+	/* Remove PASID mapping before destroying VM */</div><div class='add'>+	if (vm-&gt;pasid != 0) {</div><div class='add'>+		xa_erase_irq(&amp;adev-&gt;vm_manager.pasids, vm-&gt;pasid);</div><div class='add'>+		vm-&gt;pasid = 0;</div><div class='add'>+	}</div><div class='ctx'> 	dma_fence_wait(vm-&gt;last_unlocked, false);</div><div class='ctx'> 	dma_fence_put(vm-&gt;last_unlocked);</div><div class='ctx'> 	dma_fence_wait(vm-&gt;last_tlb_flush, false);</div><div class='hunk'>@@ -2550,7 +2787,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> 	dma_fence_put(vm-&gt;last_tlb_flush);</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(mapping, tmp, &amp;vm-&gt;freed, list) {</div><div class='del'>-		if (mapping-&gt;flags &amp; AMDGPU_PTE_PRT &amp;&amp; prt_fini_needed) {</div><div class='add'>+		if (mapping-&gt;flags &amp; AMDGPU_VM_PAGE_PRT &amp;&amp; prt_fini_needed) {</div><div class='ctx'> 			amdgpu_vm_prt_fini(adev, vm);</div><div class='ctx'> 			prt_fini_needed = false;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2581,12 +2818,20 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> 	dma_fence_put(vm-&gt;last_update);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; AMDGPU_MAX_VMHUBS; i++) {</div><div class='del'>-		if (vm-&gt;reserved_vmid[i]) {</div><div class='del'>-			amdgpu_vmid_free_reserved(adev, i);</div><div class='del'>-			vm-&gt;reserved_vmid[i] = false;</div><div class='del'>-		}</div><div class='add'>+		amdgpu_vmid_free_reserved(adev, vm, i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ttm_lru_bulk_move_fini(&amp;adev-&gt;mman.bdev, &amp;vm-&gt;lru_bulk_move);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_vm_stats_is_zero(vm)) {</div><div class='add'>+		struct amdgpu_task_info *ti = vm-&gt;task_info;</div><div class='add'>+</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "VM memory stats for proc %s(%d) task %s(%d) is non-zero when fini\n",</div><div class='add'>+			 ti-&gt;process_name, ti-&gt;task.pid, ti-&gt;task.comm, ti-&gt;tgid);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_put_task_info(vm-&gt;task_info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2598,8 +2843,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_vm_manager_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	unsigned i;</div><div class='del'>-</div><div class='ctx'> 	/* Concurrent flushes are only possible starting with Vega10 and</div><div class='ctx'> 	 * are broken on Navi10 and Navi14.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -2608,11 +2851,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)</div><div class='ctx'> 					      adev-&gt;asic_type == CHIP_NAVI14);</div><div class='ctx'> 	amdgpu_vmid_mgr_init(adev);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vm_manager.fence_context =</div><div class='del'>-		dma_fence_context_alloc(AMDGPU_MAX_RINGS);</div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MAX_RINGS; ++i)</div><div class='del'>-		adev-&gt;vm_manager.seqno[i] = 0;</div><div class='del'>-</div><div class='ctx'> 	spin_lock_init(&amp;adev-&gt;vm_manager.prt_lock);</div><div class='ctx'> 	atomic_set(&amp;adev-&gt;vm_manager.num_prt_users, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -2669,6 +2907,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 	union drm_amdgpu_vm *args = data;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct amdgpu_fpriv *fpriv = filp-&gt;driver_priv;</div><div class='add'>+	struct amdgpu_vm *vm = &amp;fpriv-&gt;vm;</div><div class='ctx'> </div><div class='ctx'> 	/* No valid flags defined yet */</div><div class='ctx'> 	if (args-&gt;in.flags)</div><div class='hunk'>@@ -2677,17 +2916,9 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 	switch (args-&gt;in.op) {</div><div class='ctx'> 	case AMDGPU_VM_OP_RESERVE_VMID:</div><div class='ctx'> 		/* We only have requirement to reserve vmid from gfxhub */</div><div class='del'>-		if (!fpriv-&gt;vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {</div><div class='del'>-			amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));</div><div class='del'>-			fpriv-&gt;vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		break;</div><div class='add'>+		return amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0));</div><div class='ctx'> 	case AMDGPU_VM_OP_UNRESERVE_VMID:</div><div class='del'>-		if (fpriv-&gt;vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {</div><div class='del'>-			amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));</div><div class='del'>-			fpriv-&gt;vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;</div><div class='del'>-		}</div><div class='add'>+		amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0));</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2700,6 +2931,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'>  * amdgpu_vm_handle_fault - graceful handling of VM faults.</div><div class='ctx'>  * @adev: amdgpu device pointer</div><div class='ctx'>  * @pasid: PASID of the VM</div><div class='add'>+ * @ts: Timestamp of the fault</div><div class='ctx'>  * @vmid: VMID, only used for GFX 9.4.3.</div><div class='ctx'>  * @node_id: Node_id received in IH cookie. Only applicable for</div><div class='ctx'>  *           GFX 9.4.3.</div><div class='hunk'>@@ -2710,7 +2942,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'>  * shouldn't be reported any more.</div><div class='ctx'>  */</div><div class='ctx'> bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,</div><div class='del'>-			    u32 vmid, u32 node_id, uint64_t addr,</div><div class='add'>+			    u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,</div><div class='ctx'> 			    bool write_fault)</div><div class='ctx'> {</div><div class='ctx'> 	bool is_compute_context = false;</div><div class='hunk'>@@ -2736,7 +2968,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,</div><div class='ctx'> 	addr /= AMDGPU_GPU_PAGE_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	if (is_compute_context &amp;&amp; !svm_range_restore_pages(adev, pasid, vmid,</div><div class='del'>-	    node_id, addr, write_fault)) {</div><div class='add'>+	    node_id, addr, ts, write_fault)) {</div><div class='ctx'> 		amdgpu_bo_unref(&amp;root);</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2790,7 +3022,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,</div><div class='ctx'> error_unlock:</div><div class='ctx'> 	amdgpu_bo_unreserve(root);</div><div class='ctx'> 	if (r &lt; 0)</div><div class='del'>-		DRM_ERROR("Can't handle page fault (%d)\n", r);</div><div class='add'>+		dev_err(adev-&gt;dev, "Can't handle page fault (%d)\n", r);</div><div class='ctx'> </div><div class='ctx'> error_unref:</div><div class='ctx'> 	amdgpu_bo_unref(&amp;root);</div><div class='hunk'>@@ -2824,6 +3056,8 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)</div><div class='ctx'> 	unsigned int total_done_objs = 0;</div><div class='ctx'> 	unsigned int id = 0;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_assert_locked(vm);</div><div class='add'>+</div><div class='ctx'> 	spin_lock(&amp;vm-&gt;status_lock);</div><div class='ctx'> 	seq_puts(m, "\tIdle BOs:\n");</div><div class='ctx'> 	list_for_each_entry_safe(bo_va, tmp, &amp;vm-&gt;idle, base.vm_status) {</div><div class='hunk'>@@ -2924,6 +3158,14 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,</div><div class='ctx'> 	if (vm &amp;&amp; status) {</div><div class='ctx'> 		vm-&gt;fault_info.addr = addr;</div><div class='ctx'> 		vm-&gt;fault_info.status = status;</div><div class='add'>+		/*</div><div class='add'>+		 * Update the fault information globally for later usage</div><div class='add'>+		 * when vm could be stale or freed.</div><div class='add'>+		 */</div><div class='add'>+		adev-&gt;vm_manager.fault_info.addr = addr;</div><div class='add'>+		adev-&gt;vm_manager.fault_info.vmhub = vmhub;</div><div class='add'>+		adev-&gt;vm_manager.fault_info.status = status;</div><div class='add'>+</div><div class='ctx'> 		if (AMDGPU_IS_GFXHUB(vmhub)) {</div><div class='ctx'> 			vm-&gt;fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;</div><div class='ctx'> 			vm-&gt;fault_info.vmhub |=</div><div class='hunk'>@@ -2943,3 +3185,25 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,</div><div class='ctx'> 	xa_unlock_irqrestore(&amp;adev-&gt;vm_manager.pasids, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid</div><div class='add'>+ *</div><div class='add'>+ * @vm: VM to test against.</div><div class='add'>+ * @bo: BO to be tested.</div><div class='add'>+ *</div><div class='add'>+ * Returns true if the BO shares the dma_resv object with the root PD and is</div><div class='add'>+ * always guaranteed to be valid inside the VM.</div><div class='add'>+ */</div><div class='add'>+bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return bo &amp;&amp; bo-&gt;tbo.base.resv == vm-&gt;root.bo-&gt;tbo.base.resv;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_vm_print_task_info(struct amdgpu_device *adev,</div><div class='add'>+			       struct amdgpu_task_info *task_info)</div><div class='add'>+{</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		" Process %s pid %d thread %s pid %d\n",</div><div class='add'>+		task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='add'>+		task_info-&gt;task.comm, task_info-&gt;task.pid);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h<br/>index 047ec1930d12..15d757c016cb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h</a></div><div class='hunk'>@@ -35,6 +35,7 @@</div><div class='ctx'> #include "amdgpu_sync.h"</div><div class='ctx'> #include "amdgpu_ring.h"</div><div class='ctx'> #include "amdgpu_ids.h"</div><div class='add'>+#include "amdgpu_ttm.h"</div><div class='ctx'> </div><div class='ctx'> struct drm_exec;</div><div class='ctx'> </div><div class='hunk'>@@ -42,7 +43,6 @@ struct amdgpu_bo_va;</div><div class='ctx'> struct amdgpu_job;</div><div class='ctx'> struct amdgpu_bo_list_entry;</div><div class='ctx'> struct amdgpu_bo_vm;</div><div class='del'>-struct amdgpu_mem_stats;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * GPUVM handling</div><div class='hunk'>@@ -94,8 +94,11 @@ struct amdgpu_mem_stats;</div><div class='ctx'> #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \</div><div class='ctx'> 				   AMDGPU_PTE_PRT)</div><div class='ctx'> /* For GFX9 */</div><div class='del'>-#define AMDGPU_PTE_MTYPE_VG10(a)	((uint64_t)(a) &lt;&lt; 57)</div><div class='del'>-#define AMDGPU_PTE_MTYPE_VG10_MASK	AMDGPU_PTE_MTYPE_VG10(3ULL)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype)	((uint64_t)(mtype) &lt;&lt; 57)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_VG10_MASK	AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_VG10(flags, mtype)			\</div><div class='add'>+	(((uint64_t)(flags) &amp; (~AMDGPU_PTE_MTYPE_VG10_MASK)) |	\</div><div class='add'>+	  AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_MTYPE_NC 0</div><div class='ctx'> #define AMDGPU_MTYPE_CC 2</div><div class='hunk'>@@ -108,8 +111,34 @@ struct amdgpu_mem_stats;</div><div class='ctx'>                                 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))</div><div class='ctx'> </div><div class='ctx'> /* gfx10 */</div><div class='del'>-#define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) &lt;&lt; 48)</div><div class='del'>-#define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype)	((uint64_t)(mtype) &lt;&lt; 48)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_NV10(flags, mtype)			\</div><div class='add'>+	(((uint64_t)(flags) &amp; (~AMDGPU_PTE_MTYPE_NV10_MASK)) |	\</div><div class='add'>+	  AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype))</div><div class='add'>+</div><div class='add'>+/* gfx12 */</div><div class='add'>+#define AMDGPU_PTE_PRT_GFX12		(1ULL &lt;&lt; 56)</div><div class='add'>+#define AMDGPU_PTE_PRT_FLAG(adev)	\</div><div class='add'>+	((amdgpu_ip_version((adev), GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)</div><div class='add'>+</div><div class='add'>+#define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)	((uint64_t)(mtype) &lt;&lt; 54)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_GFX12_MASK	AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL)</div><div class='add'>+#define AMDGPU_PTE_MTYPE_GFX12(flags, mtype)				\</div><div class='add'>+	(((uint64_t)(flags) &amp; (~AMDGPU_PTE_MTYPE_GFX12_MASK)) |	\</div><div class='add'>+	  AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype))</div><div class='add'>+</div><div class='add'>+#define AMDGPU_PTE_DCC			(1ULL &lt;&lt; 58)</div><div class='add'>+#define AMDGPU_PTE_IS_PTE		(1ULL &lt;&lt; 63)</div><div class='add'>+</div><div class='add'>+/* PDE Block Fragment Size for gfx v12 */</div><div class='add'>+#define AMDGPU_PDE_BFS_GFX12(a)		((uint64_t)((a) &amp; 0x1fULL) &lt;&lt; 58)</div><div class='add'>+#define AMDGPU_PDE_BFS_FLAG(adev, a)	\</div><div class='add'>+	((amdgpu_ip_version((adev), GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a))</div><div class='add'>+/* PDE is handled as PTE for gfx v12 */</div><div class='add'>+#define AMDGPU_PDE_PTE_GFX12		(1ULL &lt;&lt; 63)</div><div class='add'>+#define AMDGPU_PDE_PTE_FLAG(adev)	\</div><div class='add'>+	((amdgpu_ip_version((adev), GC_HWIP, 0) &gt;= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE)</div><div class='ctx'> </div><div class='ctx'> /* How to program VM fault handling */</div><div class='ctx'> #define AMDGPU_VM_FAULT_STOP_NEVER	0</div><div class='hunk'>@@ -174,9 +203,13 @@ struct amdgpu_vm_bo_base {</div><div class='ctx'> 	/* protected by bo being reserved */</div><div class='ctx'> 	struct amdgpu_vm_bo_base	*next;</div><div class='ctx'> </div><div class='del'>-	/* protected by spinlock */</div><div class='add'>+	/* protected by vm status_lock */</div><div class='ctx'> 	struct list_head		vm_status;</div><div class='ctx'> </div><div class='add'>+	/* if the bo is counted as shared in mem stats</div><div class='add'>+	 * protected by vm status_lock */</div><div class='add'>+	bool				shared;</div><div class='add'>+</div><div class='ctx'> 	/* protected by the BO being reserved */</div><div class='ctx'> 	bool				moved;</div><div class='ctx'> };</div><div class='hunk'>@@ -203,9 +236,8 @@ struct amdgpu_vm_pte_funcs {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_task_info {</div><div class='add'>+	struct drm_wedge_task_info task;</div><div class='ctx'> 	char		process_name[TASK_COMM_LEN];</div><div class='del'>-	char		task_name[TASK_COMM_LEN];</div><div class='del'>-	pid_t		pid;</div><div class='ctx'> 	pid_t		tgid;</div><div class='ctx'> 	struct kref	refcount;</div><div class='ctx'> };</div><div class='hunk'>@@ -257,21 +289,26 @@ struct amdgpu_vm_update_params {</div><div class='ctx'> 	unsigned int num_dw_left;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @table_freed: return true if page table is freed when updating</div><div class='add'>+	 * @needs_flush: true whenever we need to invalidate the TLB</div><div class='ctx'> 	 */</div><div class='del'>-	bool table_freed;</div><div class='add'>+	bool needs_flush;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='ctx'> 	 * @allow_override: true for memory that is not uncached: allows MTYPE</div><div class='ctx'> 	 * to be overridden for NUMA local memory.</div><div class='ctx'> 	 */</div><div class='ctx'> 	bool allow_override;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush</div><div class='add'>+	 */</div><div class='add'>+	struct list_head tlb_flush_waitlist;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_vm_update_funcs {</div><div class='ctx'> 	int (*map_table)(struct amdgpu_bo_vm *bo);</div><div class='del'>-	int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,</div><div class='del'>-		       enum amdgpu_sync_mode sync_mode);</div><div class='add'>+	int (*prepare)(struct amdgpu_vm_update_params *p,</div><div class='add'>+		       struct amdgpu_sync *sync, u64 k_job_id);</div><div class='ctx'> 	int (*update)(struct amdgpu_vm_update_params *p,</div><div class='ctx'> 		      struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,</div><div class='ctx'> 		      unsigned count, uint32_t incr, uint64_t flags);</div><div class='hunk'>@@ -288,6 +325,13 @@ struct amdgpu_vm_fault_info {</div><div class='ctx'> 	unsigned int	vmhub;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct amdgpu_mem_stats {</div><div class='add'>+	struct drm_memory_stats drm;</div><div class='add'>+</div><div class='add'>+	/* buffers that requested this placement but are currently evicted */</div><div class='add'>+	uint64_t evicted;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_vm {</div><div class='ctx'> 	/* tree of virtual addresses mapped */</div><div class='ctx'> 	struct rb_root_cached	va;</div><div class='hunk'>@@ -302,12 +346,19 @@ struct amdgpu_vm {</div><div class='ctx'> 	/* Lock to protect vm_bo add/del/move on all lists of vm */</div><div class='ctx'> 	spinlock_t		status_lock;</div><div class='ctx'> </div><div class='add'>+	/* Memory statistics for this vm, protected by status_lock */</div><div class='add'>+	struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM];</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The following lists contain amdgpu_vm_bo_base objects for either</div><div class='add'>+	 * PDs, PTs or per VM BOs. The state transits are:</div><div class='add'>+	 *</div><div class='add'>+	 * evicted -&gt; relocated (PDs, PTs) or moved (per VM BOs) -&gt; idle</div><div class='add'>+	 */</div><div class='add'>+</div><div class='ctx'> 	/* Per-VM and PT BOs who needs a validation */</div><div class='ctx'> 	struct list_head	evicted;</div><div class='ctx'> </div><div class='del'>-	/* BOs for user mode queues that need a validation */</div><div class='del'>-	struct list_head	evicted_user;</div><div class='del'>-</div><div class='ctx'> 	/* PT BOs which relocated and their parent need an update */</div><div class='ctx'> 	struct list_head	relocated;</div><div class='ctx'> </div><div class='hunk'>@@ -317,18 +368,28 @@ struct amdgpu_vm {</div><div class='ctx'> 	/* All BOs of this VM not currently in the state machine */</div><div class='ctx'> 	struct list_head	idle;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * The following lists contain amdgpu_vm_bo_base objects for BOs which</div><div class='add'>+	 * have their own dma_resv object and not depend on the root PD. Their</div><div class='add'>+	 * state transits are:</div><div class='add'>+	 *</div><div class='add'>+	 * evicted_user or invalidated -&gt; done</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	/* BOs for user mode queues that need a validation */</div><div class='add'>+	struct list_head	evicted_user;</div><div class='add'>+</div><div class='ctx'> 	/* regular invalidated BOs, but not yet updated in the PT */</div><div class='ctx'> 	struct list_head	invalidated;</div><div class='ctx'> </div><div class='del'>-	/* BO mappings freed, but not yet updated in the PT */</div><div class='del'>-	struct list_head	freed;</div><div class='del'>-</div><div class='ctx'> 	/* BOs which are invalidated, has been updated in the PTs */</div><div class='ctx'> 	struct list_head        done;</div><div class='ctx'> </div><div class='del'>-	/* PT BOs scheduled to free and fill with zero if vm_resv is not hold */</div><div class='del'>-	struct list_head	pt_freed;</div><div class='del'>-	struct work_struct	pt_free_work;</div><div class='add'>+	/*</div><div class='add'>+	 * This list contains amdgpu_bo_va_mapping objects which have been freed</div><div class='add'>+	 * but not updated in the PTs</div><div class='add'>+	 */</div><div class='add'>+	struct list_head	freed;</div><div class='ctx'> </div><div class='ctx'> 	/* contains the page directory */</div><div class='ctx'> 	struct amdgpu_vm_bo_base     root;</div><div class='hunk'>@@ -342,6 +403,7 @@ struct amdgpu_vm {</div><div class='ctx'> 	atomic64_t		tlb_seq;</div><div class='ctx'> 	struct dma_fence	*last_tlb_flush;</div><div class='ctx'> 	atomic64_t		kfd_last_flushed_seq;</div><div class='add'>+	uint64_t		tlb_fence_context;</div><div class='ctx'> </div><div class='ctx'> 	/* How many times we had to re-generate the page tables */</div><div class='ctx'> 	uint64_t		generation;</div><div class='hunk'>@@ -350,7 +412,7 @@ struct amdgpu_vm {</div><div class='ctx'> 	struct dma_fence	*last_unlocked;</div><div class='ctx'> </div><div class='ctx'> 	unsigned int		pasid;</div><div class='del'>-	bool			reserved_vmid[AMDGPU_MAX_VMHUBS];</div><div class='add'>+	struct amdgpu_vmid	*reserved_vmid[AMDGPU_MAX_VMHUBS];</div><div class='ctx'> </div><div class='ctx'> 	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */</div><div class='ctx'> 	bool					use_cpu_for_update;</div><div class='hunk'>@@ -391,10 +453,6 @@ struct amdgpu_vm_manager {</div><div class='ctx'> 	unsigned int				first_kfd_vmid;</div><div class='ctx'> 	bool					concurrent_flush;</div><div class='ctx'> </div><div class='del'>-	/* Handling of VM fences */</div><div class='del'>-	u64					fence_context;</div><div class='del'>-	unsigned				seqno[AMDGPU_MAX_RINGS];</div><div class='del'>-</div><div class='ctx'> 	uint64_t				max_pfn;</div><div class='ctx'> 	uint32_t				num_level;</div><div class='ctx'> 	uint32_t				block_size;</div><div class='hunk'>@@ -422,6 +480,8 @@ struct amdgpu_vm_manager {</div><div class='ctx'> 	 * look up VM of a page fault</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct xarray				pasids;</div><div class='add'>+	/* Global registration of recent page fault information */</div><div class='add'>+	struct amdgpu_vm_fault_info	fault_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_bo_va_mapping;</div><div class='hunk'>@@ -436,16 +496,14 @@ extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;</div><div class='ctx'> void amdgpu_vm_manager_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_vm_manager_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='del'>-int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-			u32 pasid);</div><div class='del'>-</div><div class='ctx'> long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);</div><div class='del'>-int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id);</div><div class='add'>+int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id, uint32_t pasid);</div><div class='ctx'> int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);</div><div class='del'>-void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);</div><div class='ctx'> void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);</div><div class='ctx'> int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,</div><div class='ctx'> 		      unsigned int num_fences);</div><div class='add'>+int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec,</div><div class='add'>+			     unsigned int num_fences);</div><div class='ctx'> bool amdgpu_vm_ready(struct amdgpu_vm *vm);</div><div class='ctx'> uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);</div><div class='ctx'> int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='hunk'>@@ -468,17 +526,22 @@ int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,</div><div class='ctx'> void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,</div><div class='ctx'> 			    struct amdgpu_vm *vm, struct amdgpu_bo *bo);</div><div class='ctx'> int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='del'>-			   bool immediate, bool unlocked, bool flush_tlb, bool allow_override,</div><div class='del'>-			   struct dma_resv *resv, uint64_t start, uint64_t last,</div><div class='del'>-			   uint64_t flags, uint64_t offset, uint64_t vram_base,</div><div class='add'>+			   bool immediate, bool unlocked, bool flush_tlb,</div><div class='add'>+			   bool allow_override, struct amdgpu_sync *sync,</div><div class='add'>+			   uint64_t start, uint64_t last, uint64_t flags,</div><div class='add'>+			   uint64_t offset, uint64_t vram_base,</div><div class='ctx'> 			   struct ttm_resource *res, dma_addr_t *pages_addr,</div><div class='ctx'> 			   struct dma_fence **fence);</div><div class='ctx'> int amdgpu_vm_bo_update(struct amdgpu_device *adev,</div><div class='ctx'> 			struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 			bool clear);</div><div class='ctx'> bool amdgpu_vm_evictable(struct amdgpu_bo *bo);</div><div class='del'>-void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,</div><div class='del'>-			     struct amdgpu_bo *bo, bool evicted);</div><div class='add'>+void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted);</div><div class='add'>+void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base,</div><div class='add'>+			    struct ttm_resource *new_res, int sign);</div><div class='add'>+void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo);</div><div class='add'>+void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem,</div><div class='add'>+		       bool evicted);</div><div class='ctx'> uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);</div><div class='ctx'> struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,</div><div class='ctx'> 				       struct amdgpu_bo *bo);</div><div class='hunk'>@@ -488,11 +551,11 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_vm_bo_map(struct amdgpu_device *adev,</div><div class='ctx'> 		     struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 		     uint64_t addr, uint64_t offset,</div><div class='del'>-		     uint64_t size, uint64_t flags);</div><div class='add'>+		     uint64_t size, uint32_t flags);</div><div class='ctx'> int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,</div><div class='ctx'> 			     struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 			     uint64_t addr, uint64_t offset,</div><div class='del'>-			     uint64_t size, uint64_t flags);</div><div class='add'>+			     uint64_t size, uint32_t flags);</div><div class='ctx'> int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,</div><div class='ctx'> 		       struct amdgpu_bo_va *bo_va,</div><div class='ctx'> 		       uint64_t addr);</div><div class='hunk'>@@ -521,7 +584,7 @@ amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm);</div><div class='ctx'> void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info);</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,</div><div class='del'>-			    u32 vmid, u32 node_id, uint64_t addr,</div><div class='add'>+			    u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,</div><div class='ctx'> 			    bool write_fault);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);</div><div class='hunk'>@@ -529,7 +592,7 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);</div><div class='ctx'> void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,</div><div class='ctx'> 				struct amdgpu_vm *vm);</div><div class='ctx'> void amdgpu_vm_get_memory(struct amdgpu_vm *vm,</div><div class='del'>-			  struct amdgpu_mem_stats *stats);</div><div class='add'>+			  struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 		       struct amdgpu_bo_vm *vmbo, bool immediate);</div><div class='hunk'>@@ -544,6 +607,8 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,</div><div class='ctx'> 			  uint64_t start, uint64_t end,</div><div class='ctx'> 			  uint64_t dst, uint64_t flags);</div><div class='ctx'> void amdgpu_vm_pt_free_work(struct work_struct *work);</div><div class='add'>+void amdgpu_vm_pt_free_list(struct amdgpu_device *adev,</div><div class='add'>+			    struct amdgpu_vm_update_params *params);</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);</div><div class='hunk'>@@ -551,6 +616,8 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm);</div><div class='ctx'> </div><div class='add'>+bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_vm_tlb_seq - return tlb flush sequence number</div><div class='ctx'>  * @vm: the amdgpu_vm structure to query</div><div class='hunk'>@@ -609,5 +676,16 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,</div><div class='ctx'> 				  uint64_t addr,</div><div class='ctx'> 				  uint32_t status,</div><div class='ctx'> 				  unsigned int vmhub);</div><div class='add'>+void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_vm *vm,</div><div class='add'>+				 struct dma_fence **fence);</div><div class='add'>+</div><div class='add'>+void amdgpu_vm_print_task_info(struct amdgpu_device *adev,</div><div class='add'>+			       struct amdgpu_task_info *task_info);</div><div class='add'>+</div><div class='add'>+#define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \</div><div class='add'>+		list_for_each_entry(mapping, &amp;(bo_va)-&gt;valids, list)</div><div class='add'>+#define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \</div><div class='add'>+		list_for_each_entry(mapping, &amp;(bo_va)-&gt;invalids, list)</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c<br/>index 6e31621452de..22e2e5b47341 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c</a></div><div class='hunk'>@@ -39,20 +39,20 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)</div><div class='ctx'>  * amdgpu_vm_cpu_prepare - prepare page table update with the CPU</div><div class='ctx'>  *</div><div class='ctx'>  * @p: see amdgpu_vm_update_params definition</div><div class='del'>- * @resv: reservation object with embedded fence</div><div class='del'>- * @sync_mode: synchronization mode</div><div class='add'>+ * @sync: sync obj with fences to wait on</div><div class='add'>+ * @k_job_id: the id for tracing/debug purposes</div><div class='ctx'>  *</div><div class='ctx'>  * Returns:</div><div class='ctx'>  * Negativ errno, 0 for success.</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,</div><div class='del'>-				 struct dma_resv *resv,</div><div class='del'>-				 enum amdgpu_sync_mode sync_mode)</div><div class='add'>+				 struct amdgpu_sync *sync,</div><div class='add'>+				 u64 k_job_id)</div><div class='ctx'> {</div><div class='del'>-	if (!resv)</div><div class='add'>+	if (!sync)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return amdgpu_bo_sync_wait_resv(p-&gt;adev, resv, sync_mode, p-&gt;vm, true);</div><div class='add'>+	return amdgpu_sync_wait(sync, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -108,7 +108,9 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,</div><div class='ctx'> static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,</div><div class='ctx'> 				struct dma_fence **fence)</div><div class='ctx'> {</div><div class='del'>-	/* Flush HDP */</div><div class='add'>+	if (p-&gt;needs_flush)</div><div class='add'>+		atomic64_inc(&amp;p-&gt;vm-&gt;tlb_seq);</div><div class='add'>+</div><div class='ctx'> 	mb();</div><div class='ctx'> 	amdgpu_device_flush_hdp(p-&gt;adev, NULL);</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c<br/>index 124389a6bf48..f794fb1cc06e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_trace.h"</div><div class='ctx'> #include "amdgpu_vm.h"</div><div class='add'>+#include "amdgpu_job.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt</div><div class='hunk'>@@ -383,14 +384,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	if (vmbo-&gt;shadow) {</div><div class='del'>-		struct amdgpu_bo *shadow = vmbo-&gt;shadow;</div><div class='del'>-</div><div class='del'>-		r = ttm_bo_validate(&amp;shadow-&gt;tbo, &amp;shadow-&gt;placement, &amp;ctx);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (!drm_dev_enter(adev_to_drm(adev), &amp;idx))</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -403,7 +396,8 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	params.vm = vm;</div><div class='ctx'> 	params.immediate = immediate;</div><div class='ctx'> </div><div class='del'>-	r = vm-&gt;update_funcs-&gt;prepare(&amp;params, NULL, AMDGPU_SYNC_EXPLICIT);</div><div class='add'>+	r = vm-&gt;update_funcs-&gt;prepare(&amp;params, NULL,</div><div class='add'>+				      AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto exit;</div><div class='ctx'> </div><div class='hunk'>@@ -413,7 +407,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	if (adev-&gt;asic_type &gt;= CHIP_VEGA10) {</div><div class='ctx'> 		if (level != AMDGPU_VM_PTB) {</div><div class='ctx'> 			/* Handle leaf PDEs as PTEs */</div><div class='del'>-			flags |= AMDGPU_PDE_PTE;</div><div class='add'>+			flags |= AMDGPU_PDE_PTE_FLAG(adev);</div><div class='ctx'> 			amdgpu_gmc_get_vm_pde(adev, level,</div><div class='ctx'> 					      &amp;value, &amp;flags);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -448,10 +442,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 			int32_t xcp_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_bo_param bp;</div><div class='del'>-	struct amdgpu_bo *bo;</div><div class='del'>-	struct dma_resv *resv;</div><div class='ctx'> 	unsigned int num_entries;</div><div class='del'>-	int r;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;bp, 0, sizeof(bp));</div><div class='ctx'> </div><div class='hunk'>@@ -484,42 +475,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	if (vm-&gt;root.bo)</div><div class='ctx'> 		bp.resv = vm-&gt;root.bo-&gt;tbo.base.resv;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_bo_create_vm(adev, &amp;bp, vmbo);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	bo = &amp;(*vmbo)-&gt;bo;</div><div class='del'>-	if (vm-&gt;is_compute_context || (adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='del'>-		(*vmbo)-&gt;shadow = NULL;</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!bp.resv)</div><div class='del'>-		WARN_ON(dma_resv_lock(bo-&gt;tbo.base.resv,</div><div class='del'>-				      NULL));</div><div class='del'>-	resv = bp.resv;</div><div class='del'>-	memset(&amp;bp, 0, sizeof(bp));</div><div class='del'>-	bp.size = amdgpu_vm_pt_size(adev, level);</div><div class='del'>-	bp.domain = AMDGPU_GEM_DOMAIN_GTT;</div><div class='del'>-	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;</div><div class='del'>-	bp.type = ttm_bo_type_kernel;</div><div class='del'>-	bp.resv = bo-&gt;tbo.base.resv;</div><div class='del'>-	bp.bo_ptr_size = sizeof(struct amdgpu_bo);</div><div class='del'>-	bp.xcp_id_plus1 = xcp_id + 1;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create(adev, &amp;bp, &amp;(*vmbo)-&gt;shadow);</div><div class='del'>-</div><div class='del'>-	if (!resv)</div><div class='del'>-		dma_resv_unlock(bo-&gt;tbo.base.resv);</div><div class='del'>-</div><div class='del'>-	if (r) {</div><div class='del'>-		amdgpu_bo_unref(&amp;bo);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_add_to_shadow_list(*vmbo);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return amdgpu_bo_create_vm(adev, &amp;bp, vmbo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -569,7 +525,6 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> error_free_pt:</div><div class='del'>-	amdgpu_bo_unref(&amp;pt-&gt;shadow);</div><div class='ctx'> 	amdgpu_bo_unref(&amp;pt_bo);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -581,17 +536,11 @@ error_free_pt:</div><div class='ctx'>  */</div><div class='ctx'> static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *shadow;</div><div class='del'>-</div><div class='ctx'> 	if (!entry-&gt;bo)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_update_stats(entry, entry-&gt;bo-&gt;tbo.resource, -1);</div><div class='ctx'> 	entry-&gt;bo-&gt;vm_bo = NULL;</div><div class='del'>-	shadow = amdgpu_bo_shadowed(entry-&gt;bo);</div><div class='del'>-	if (shadow) {</div><div class='del'>-		ttm_bo_set_bulk_move(&amp;shadow-&gt;tbo, NULL);</div><div class='del'>-		amdgpu_bo_unref(&amp;shadow);</div><div class='del'>-	}</div><div class='ctx'> 	ttm_bo_set_bulk_move(&amp;entry-&gt;bo-&gt;tbo, NULL);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;entry-&gt;vm-&gt;status_lock);</div><div class='hunk'>@@ -600,62 +549,55 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)</div><div class='ctx'> 	amdgpu_bo_unref(&amp;entry-&gt;bo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_vm_pt_free_work(struct work_struct *work)</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_vm_pt_free_list - free PD/PT levels</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu device structure</div><div class='add'>+ * @params: see amdgpu_vm_update_params definition</div><div class='add'>+ *</div><div class='add'>+ * Free the page directory objects saved in the flush list</div><div class='add'>+ */</div><div class='add'>+void amdgpu_vm_pt_free_list(struct amdgpu_device *adev,</div><div class='add'>+			    struct amdgpu_vm_update_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vm_bo_base *entry, *next;</div><div class='del'>-	struct amdgpu_vm *vm;</div><div class='del'>-	LIST_HEAD(pt_freed);</div><div class='del'>-</div><div class='del'>-	vm = container_of(work, struct amdgpu_vm, pt_free_work);</div><div class='add'>+	bool unlocked = params-&gt;unlocked;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;vm-&gt;status_lock);</div><div class='del'>-	list_splice_init(&amp;vm-&gt;pt_freed, &amp;pt_freed);</div><div class='del'>-	spin_unlock(&amp;vm-&gt;status_lock);</div><div class='add'>+	if (list_empty(&amp;params-&gt;tlb_flush_waitlist))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	/* flush_work in amdgpu_vm_fini ensure vm-&gt;root.bo is valid. */</div><div class='del'>-	amdgpu_bo_reserve(vm-&gt;root.bo, true);</div><div class='add'>+	/*</div><div class='add'>+	 * unlocked unmap clear page table leaves, warning to free the page entry.</div><div class='add'>+	 */</div><div class='add'>+	WARN_ON(unlocked);</div><div class='ctx'> </div><div class='del'>-	list_for_each_entry_safe(entry, next, &amp;pt_freed, vm_status)</div><div class='add'>+	list_for_each_entry_safe(entry, next, &amp;params-&gt;tlb_flush_waitlist, vm_status)</div><div class='ctx'> 		amdgpu_vm_pt_free(entry);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_vm_pt_free_dfs - free PD/PT levels</div><div class='add'>+ * amdgpu_vm_pt_add_list - add PD/PT level to the flush list</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu device structure</div><div class='del'>- * @vm: amdgpu vm structure</div><div class='del'>- * @start: optional cursor where to start freeing PDs/PTs</div><div class='del'>- * @unlocked: vm resv unlock status</div><div class='add'>+ * @params: parameters for the update</div><div class='add'>+ * @cursor: first PT entry to start DF search from, non NULL</div><div class='ctx'>  *</div><div class='del'>- * Free the page directory or page table level and all sub levels.</div><div class='add'>+ * This list will be freed after TLB flush.</div><div class='ctx'>  */</div><div class='del'>-static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,</div><div class='del'>-				  struct amdgpu_vm *vm,</div><div class='del'>-				  struct amdgpu_vm_pt_cursor *start,</div><div class='del'>-				  bool unlocked)</div><div class='add'>+static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params,</div><div class='add'>+				  struct amdgpu_vm_pt_cursor *cursor)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_vm_pt_cursor cursor;</div><div class='add'>+	struct amdgpu_vm_pt_cursor seek;</div><div class='ctx'> 	struct amdgpu_vm_bo_base *entry;</div><div class='ctx'> </div><div class='del'>-	if (unlocked) {</div><div class='del'>-		spin_lock(&amp;vm-&gt;status_lock);</div><div class='del'>-		for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)</div><div class='del'>-			list_move(&amp;entry-&gt;vm_status, &amp;vm-&gt;pt_freed);</div><div class='del'>-</div><div class='del'>-		if (start)</div><div class='del'>-			list_move(&amp;start-&gt;entry-&gt;vm_status, &amp;vm-&gt;pt_freed);</div><div class='del'>-		spin_unlock(&amp;vm-&gt;status_lock);</div><div class='del'>-		schedule_work(&amp;vm-&gt;pt_free_work);</div><div class='del'>-		return;</div><div class='add'>+	spin_lock(&amp;params-&gt;vm-&gt;status_lock);</div><div class='add'>+	for_each_amdgpu_vm_pt_dfs_safe(params-&gt;adev, params-&gt;vm, cursor, seek, entry) {</div><div class='add'>+		if (entry &amp;&amp; entry-&gt;bo)</div><div class='add'>+			list_move(&amp;entry-&gt;vm_status, &amp;params-&gt;tlb_flush_waitlist);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)</div><div class='del'>-		amdgpu_vm_pt_free(entry);</div><div class='del'>-</div><div class='del'>-	if (start)</div><div class='del'>-		amdgpu_vm_pt_free(start-&gt;entry);</div><div class='add'>+	/* enter start node now */</div><div class='add'>+	list_move(&amp;cursor-&gt;entry-&gt;vm_status, &amp;params-&gt;tlb_flush_waitlist);</div><div class='add'>+	spin_unlock(&amp;params-&gt;vm-&gt;status_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -667,7 +609,13 @@ static void amdgpu_vm_pt_free_dfs(struct amdgpu_device *adev,</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_vm_pt_free_dfs(adev, vm, NULL, false);</div><div class='add'>+	struct amdgpu_vm_pt_cursor cursor;</div><div class='add'>+	struct amdgpu_vm_bo_base *entry;</div><div class='add'>+</div><div class='add'>+	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry) {</div><div class='add'>+		if (entry)</div><div class='add'>+			amdgpu_vm_pt_free(entry);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -682,11 +630,15 @@ int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,</div><div class='ctx'> 			 struct amdgpu_vm_bo_base *entry)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);</div><div class='del'>-	struct amdgpu_bo *bo = parent-&gt;bo, *pbo;</div><div class='add'>+	struct amdgpu_bo *bo, *pbo;</div><div class='ctx'> 	struct amdgpu_vm *vm = params-&gt;vm;</div><div class='ctx'> 	uint64_t pde, pt, flags;</div><div class='ctx'> 	unsigned int level;</div><div class='ctx'> </div><div class='add'>+	if (WARN_ON(!parent))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	bo = parent-&gt;bo;</div><div class='ctx'> 	for (level = 0, pbo = bo-&gt;parent; pbo; ++level)</div><div class='ctx'> 		pbo = pbo-&gt;parent;</div><div class='ctx'> </div><div class='hunk'>@@ -733,12 +685,12 @@ static void amdgpu_vm_pte_update_flags(struct amdgpu_vm_update_params *params,</div><div class='ctx'> 	struct amdgpu_device *adev = params-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (level != AMDGPU_VM_PTB) {</div><div class='del'>-		flags |= AMDGPU_PDE_PTE;</div><div class='add'>+		flags |= AMDGPU_PDE_PTE_FLAG(params-&gt;adev);</div><div class='ctx'> 		amdgpu_gmc_get_vm_pde(adev, level, &amp;addr, &amp;flags);</div><div class='ctx'> </div><div class='ctx'> 	} else if (adev-&gt;asic_type &gt;= CHIP_VEGA10 &amp;&amp;</div><div class='ctx'> 		   !(flags &amp; AMDGPU_PTE_VALID) &amp;&amp;</div><div class='del'>-		   !(flags &amp; AMDGPU_PTE_PRT)) {</div><div class='add'>+		   !(flags &amp; AMDGPU_PTE_PRT_FLAG(params-&gt;adev))) {</div><div class='ctx'> </div><div class='ctx'> 		/* Workaround for fault priority problem on GMC9 */</div><div class='ctx'> 		flags |= AMDGPU_PTE_EXECUTABLE;</div><div class='hunk'>@@ -925,7 +877,15 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,</div><div class='ctx'> 		incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE &lt;&lt; shift;</div><div class='ctx'> 		mask = amdgpu_vm_pt_entries_mask(adev, cursor.level);</div><div class='ctx'> 		pe_start = ((cursor.pfn &gt;&gt; shift) &amp; mask) * 8;</div><div class='del'>-		entry_end = ((uint64_t)mask + 1) &lt;&lt; shift;</div><div class='add'>+</div><div class='add'>+		if (cursor.level &lt; AMDGPU_VM_PTB &amp;&amp; params-&gt;unlocked)</div><div class='add'>+			/*</div><div class='add'>+			 * MMU notifier callback unlocked unmap huge page, leave is PDE entry,</div><div class='add'>+			 * only clear one entry. Next entry search again for PDE or PTE leave.</div><div class='add'>+			 */</div><div class='add'>+			entry_end = 1ULL &lt;&lt; shift;</div><div class='add'>+		else</div><div class='add'>+			entry_end = ((uint64_t)mask + 1) &lt;&lt; shift;</div><div class='ctx'> 		entry_end += cursor.pfn &amp; ~(entry_end - 1);</div><div class='ctx'> 		entry_end = min(entry_end, end);</div><div class='ctx'> </div><div class='hunk'>@@ -972,10 +932,8 @@ int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,</div><div class='ctx'> 			while (cursor.pfn &lt; frag_start) {</div><div class='ctx'> 				/* Make sure previous mapping is freed */</div><div class='ctx'> 				if (cursor.entry-&gt;bo) {</div><div class='del'>-					params-&gt;table_freed = true;</div><div class='del'>-					amdgpu_vm_pt_free_dfs(adev, params-&gt;vm,</div><div class='del'>-							      &amp;cursor,</div><div class='del'>-							      params-&gt;unlocked);</div><div class='add'>+					params-&gt;needs_flush = true;</div><div class='add'>+					amdgpu_vm_pt_add_list(params, &amp;cursor);</div><div class='ctx'> 				}</div><div class='ctx'> 				amdgpu_vm_pt_next(adev, &amp;cursor);</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c<br/>index 349416e176a1..36805dcfa159 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c</a></div><div class='hunk'>@@ -35,21 +35,12 @@</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_ttm_alloc_gart(&amp;table-&gt;bo.tbo);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	if (table-&gt;shadow)</div><div class='del'>-		r = amdgpu_ttm_alloc_gart(&amp;table-&gt;shadow-&gt;tbo);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_ttm_alloc_gart(&amp;table-&gt;bo.tbo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Allocate a new job for @count PTE updates */</div><div class='ctx'> static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,</div><div class='del'>-				    unsigned int count)</div><div class='add'>+				    unsigned int count, u64 k_job_id)</div><div class='ctx'> {</div><div class='ctx'> 	enum amdgpu_ib_pool_type pool = p-&gt;immediate ? AMDGPU_IB_POOL_IMMEDIATE</div><div class='ctx'> 		: AMDGPU_IB_POOL_DELAYED;</div><div class='hunk'>@@ -65,7 +56,7 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,</div><div class='ctx'> 	ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(p-&gt;adev, entity, AMDGPU_FENCE_OWNER_VM,</div><div class='del'>-				     ndw * 4, pool, &amp;p-&gt;job);</div><div class='add'>+				     ndw * 4, pool, &amp;p-&gt;job, k_job_id);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -77,31 +68,29 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,</div><div class='ctx'>  * amdgpu_vm_sdma_prepare - prepare SDMA command submission</div><div class='ctx'>  *</div><div class='ctx'>  * @p: see amdgpu_vm_update_params definition</div><div class='del'>- * @resv: reservation object with embedded fence</div><div class='del'>- * @sync_mode: synchronization mode</div><div class='add'>+ * @sync: amdgpu_sync object with fences to wait for</div><div class='add'>+ * @k_job_id: identifier of the job, for tracing purpose</div><div class='ctx'>  *</div><div class='ctx'>  * Returns:</div><div class='ctx'>  * Negativ errno, 0 for success.</div><div class='ctx'>  */</div><div class='ctx'> static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,</div><div class='del'>-				  struct dma_resv *resv,</div><div class='del'>-				  enum amdgpu_sync_mode sync_mode)</div><div class='add'>+				  struct amdgpu_sync *sync, u64 k_job_id)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_sync sync;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vm_sdma_alloc_job(p, 0);</div><div class='add'>+	r = amdgpu_vm_sdma_alloc_job(p, 0, k_job_id);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	if (!resv)</div><div class='add'>+	if (!sync)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	amdgpu_sync_create(&amp;sync);</div><div class='del'>-	r = amdgpu_sync_resv(p-&gt;adev, &amp;sync, resv, sync_mode, p-&gt;vm);</div><div class='del'>-	if (!r)</div><div class='del'>-		r = amdgpu_sync_push_to_job(&amp;sync, p-&gt;job);</div><div class='del'>-	amdgpu_sync_free(&amp;sync);</div><div class='add'>+	r = amdgpu_sync_push_to_job(sync, p-&gt;job);</div><div class='add'>+	if (r) {</div><div class='add'>+		p-&gt;num_dw_left = 0;</div><div class='add'>+		amdgpu_job_free(p-&gt;job);</div><div class='add'>+	}</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -126,6 +115,10 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,</div><div class='ctx'> </div><div class='ctx'> 	WARN_ON(ib-&gt;length_dw == 0);</div><div class='ctx'> 	amdgpu_ring_pad_ib(ring, ib);</div><div class='add'>+</div><div class='add'>+	if (p-&gt;needs_flush)</div><div class='add'>+		atomic64_inc(&amp;p-&gt;vm-&gt;tlb_seq);</div><div class='add'>+</div><div class='ctx'> 	WARN_ON(ib-&gt;length_dw &gt; p-&gt;num_dw_left);</div><div class='ctx'> 	f = amdgpu_job_submit(p-&gt;job);</div><div class='ctx'> </div><div class='hunk'>@@ -257,24 +250,21 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='ctx'> </div><div class='del'>-			r = amdgpu_vm_sdma_alloc_job(p, count);</div><div class='add'>+			r = amdgpu_vm_sdma_alloc_job(p, count,</div><div class='add'>+						     AMDGPU_KERNEL_JOB_ID_VM_UPDATE);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (!p-&gt;pages_addr) {</div><div class='ctx'> 			/* set page commands needed */</div><div class='del'>-			if (vmbo-&gt;shadow)</div><div class='del'>-				amdgpu_vm_sdma_set_ptes(p, vmbo-&gt;shadow, pe, addr,</div><div class='del'>-							count, incr, flags);</div><div class='ctx'> 			amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count,</div><div class='ctx'> 						incr, flags);</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* copy commands needed */</div><div class='del'>-		ndw -= p-&gt;adev-&gt;vm_manager.vm_pte_funcs-&gt;copy_pte_num_dw *</div><div class='del'>-			(vmbo-&gt;shadow ? 2 : 1);</div><div class='add'>+		ndw -= p-&gt;adev-&gt;vm_manager.vm_pte_funcs-&gt;copy_pte_num_dw;</div><div class='ctx'> </div><div class='ctx'> 		/* for padding */</div><div class='ctx'> 		ndw -= 7;</div><div class='hunk'>@@ -289,8 +279,6 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,</div><div class='ctx'> 			pte[i] |= flags;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (vmbo-&gt;shadow)</div><div class='del'>-			amdgpu_vm_sdma_copy_ptes(p, vmbo-&gt;shadow, pe, nptes);</div><div class='ctx'> 		amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes);</div><div class='ctx'> </div><div class='ctx'> 		pe += nptes * 8;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<br/>new file mode 100644<br/>index 000000000000..5d26797356a3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_vm.h"</div><div class='add'>+#include "amdgpu_gmc.h"</div><div class='add'>+</div><div class='add'>+struct amdgpu_tlb_fence {</div><div class='add'>+	struct dma_fence	base;</div><div class='add'>+	struct amdgpu_device	*adev;</div><div class='add'>+	struct dma_fence	*dependency;</div><div class='add'>+	struct work_struct	work;</div><div class='add'>+	spinlock_t		lock;</div><div class='add'>+	uint16_t		pasid;</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *amdgpu_tlb_fence_get_driver_name(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return "amdgpu tlb fence";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *amdgpu_tlb_fence_get_timeline_name(struct dma_fence *f)</div><div class='add'>+{</div><div class='add'>+	return "amdgpu tlb timeline";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_tlb_fence_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_tlb_fence *f = container_of(work, typeof(*f), work);</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (f-&gt;dependency) {</div><div class='add'>+		dma_fence_wait(f-&gt;dependency, false);</div><div class='add'>+		dma_fence_put(f-&gt;dependency);</div><div class='add'>+		f-&gt;dependency = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gmc_flush_gpu_tlb_pasid(f-&gt;adev, f-&gt;pasid, 2, true, 0);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(f-&gt;adev-&gt;dev, "TLB flush failed for PASID %d.\n",</div><div class='add'>+			f-&gt;pasid);</div><div class='add'>+		dma_fence_set_error(&amp;f-&gt;base, r);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dma_fence_signal(&amp;f-&gt;base);</div><div class='add'>+	dma_fence_put(&amp;f-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops amdgpu_tlb_fence_ops = {</div><div class='add'>+	.get_driver_name = amdgpu_tlb_fence_get_driver_name,</div><div class='add'>+	.get_timeline_name = amdgpu_tlb_fence_get_timeline_name</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='add'>+				struct dma_fence **fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_tlb_fence *f;</div><div class='add'>+</div><div class='add'>+	f = kmalloc(sizeof(*f), GFP_KERNEL);</div><div class='add'>+	if (!f) {</div><div class='add'>+		/*</div><div class='add'>+		 * We can't fail since the PDEs and PTEs are already updated, so</div><div class='add'>+		 * just block for the dependency and execute the TLB flush</div><div class='add'>+		 */</div><div class='add'>+		if (*fence)</div><div class='add'>+			dma_fence_wait(*fence, false);</div><div class='add'>+</div><div class='add'>+		amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm-&gt;pasid, 2, true, 0);</div><div class='add'>+		*fence = dma_fence_get_stub();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;adev = adev;</div><div class='add'>+	f-&gt;dependency = *fence;</div><div class='add'>+	f-&gt;pasid = vm-&gt;pasid;</div><div class='add'>+	INIT_WORK(&amp;f-&gt;work, amdgpu_tlb_fence_work);</div><div class='add'>+	spin_lock_init(&amp;f-&gt;lock);</div><div class='add'>+</div><div class='add'>+	dma_fence_init64(&amp;f-&gt;base, &amp;amdgpu_tlb_fence_ops, &amp;f-&gt;lock,</div><div class='add'>+			 vm-&gt;tlb_fence_context, atomic64_read(&amp;vm-&gt;tlb_seq));</div><div class='add'>+</div><div class='add'>+	/* TODO: We probably need a separate wq here */</div><div class='add'>+	dma_fence_get(&amp;f-&gt;base);</div><div class='add'>+	schedule_work(&amp;f-&gt;work);</div><div class='add'>+</div><div class='add'>+	*fence = &amp;f-&gt;base;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c<br/>index 7a65a2b128ec..aa78c2ee9e21 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c</a></div><div class='hunk'>@@ -128,6 +128,7 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)</div><div class='ctx'> 		struct dpm_clock *VPEClks;</div><div class='ctx'> 		struct dpm_clock *SOCClks;</div><div class='ctx'> 		uint32_t idx;</div><div class='add'>+		uint32_t vpeclk_enalbled_num = 0;</div><div class='ctx'> 		uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;</div><div class='ctx'> 		uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -144,6 +145,14 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)</div><div class='ctx'> 		SOCClks = clock_table.SocClocks;</div><div class='ctx'> 		VPEClks = clock_table.VPEClocks;</div><div class='ctx'> </div><div class='add'>+		/* Comfirm enabled vpe clk num</div><div class='add'>+		 * Enabled VPE clocks are ordered from low to high in VPEClks</div><div class='add'>+		 * The highest valid clock index+1 is the number of VPEClks</div><div class='add'>+		 */</div><div class='add'>+		for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx &amp;&amp; !vpeclk_enalbled_num; idx--)</div><div class='add'>+			if (VPEClks[idx-1].Freq)</div><div class='add'>+				vpeclk_enalbled_num = idx;</div><div class='add'>+</div><div class='ctx'> 		/* vpe dpm only cares 4 levels. */</div><div class='ctx'> 		for (idx = 0; idx &lt; VPE_MAX_DPM_LEVEL; idx++) {</div><div class='ctx'> 			uint32_t soc_dpm_level;</div><div class='hunk'>@@ -155,8 +164,8 @@ int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)</div><div class='ctx'> 				soc_dpm_level = (idx * 2) + 1;</div><div class='ctx'> </div><div class='ctx'> 			/* clamp the max level */</div><div class='del'>-			if (soc_dpm_level &gt; PP_SMU_NUM_VPECLK_DPM_LEVELS - 1)</div><div class='del'>-				soc_dpm_level = PP_SMU_NUM_VPECLK_DPM_LEVELS - 1;</div><div class='add'>+			if (soc_dpm_level &gt; vpeclk_enalbled_num - 1)</div><div class='add'>+				soc_dpm_level = vpeclk_enalbled_num - 1;</div><div class='ctx'> </div><div class='ctx'> 			min_freq = (SOCClks[soc_dpm_level].Freq &lt; VPEClks[soc_dpm_level].Freq) ?</div><div class='ctx'> 				   SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;</div><div class='hunk'>@@ -205,7 +214,7 @@ disable_dpm:</div><div class='ctx'> 	dpm_ctl &amp;= 0xfffffffe; /* Disable DPM */</div><div class='ctx'> 	WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_enable), dpm_ctl);</div><div class='ctx'> 	dev_dbg(adev-&gt;dev, "%s: disable vpe dpm\n", __func__);</div><div class='del'>-	return 0;</div><div class='add'>+	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)</div><div class='hunk'>@@ -223,13 +232,12 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = vpe-&gt;ring.adev;</div><div class='ctx'> 	const struct vpe_firmware_header_v1_0 *vpe_hdr;</div><div class='del'>-	char fw_prefix[32], fw_name[64];</div><div class='add'>+	char fw_prefix[32];</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix));</div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", fw_prefix);</div><div class='del'>-</div><div class='del'>-	ret = amdgpu_ucode_request(adev, &amp;adev-&gt;vpe.fw, fw_name);</div><div class='add'>+	ret = amdgpu_ucode_request(adev, &amp;adev-&gt;vpe.fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s.bin", fw_prefix);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -288,13 +296,14 @@ int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_early_init(void *handle)</div><div class='add'>+static int vpe_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 1, 0):</div><div class='add'>+	case IP_VERSION(6, 1, 3):</div><div class='ctx'> 		vpe_v6_1_set_funcs(vpe);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(6, 1, 1):</div><div class='hunk'>@@ -313,6 +322,26 @@ static int vpe_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 1, 1):</div><div class='add'>+		return adev-&gt;pm.fw_version &lt; 0x0a640500;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vpe_get_dpm_level(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;pm.dpm_enabled)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return RREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_request_lv));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void vpe_idle_work_handler(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev =</div><div class='hunk'>@@ -320,11 +349,17 @@ static void vpe_idle_work_handler(struct work_struct *work)</div><div class='ctx'> 	unsigned int fences = 0;</div><div class='ctx'> </div><div class='ctx'> 	fences += amdgpu_fence_count_emitted(&amp;adev-&gt;vpe.ring);</div><div class='add'>+	if (fences)</div><div class='add'>+		goto reschedule;</div><div class='add'>+</div><div class='add'>+	if (vpe_need_dpm0_at_power_down(adev) &amp;&amp; vpe_get_dpm_level(adev) != 0)</div><div class='add'>+		goto reschedule;</div><div class='add'>+</div><div class='add'>+	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);</div><div class='add'>+	return;</div><div class='ctx'> </div><div class='del'>-	if (fences == 0)</div><div class='del'>-		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);</div><div class='del'>-	else</div><div class='del'>-		schedule_delayed_work(&amp;adev-&gt;vpe.idle_work, VPE_IDLE_TIMEOUT);</div><div class='add'>+reschedule:</div><div class='add'>+	schedule_delayed_work(&amp;adev-&gt;vpe.idle_work, VPE_IDLE_TIMEOUT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vpe_common_init(struct amdgpu_vpe *vpe)</div><div class='hunk'>@@ -348,9 +383,9 @@ static int vpe_common_init(struct amdgpu_vpe *vpe)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_sw_init(void *handle)</div><div class='add'>+static int vpe_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -369,18 +404,27 @@ static int vpe_sw_init(void *handle)</div><div class='ctx'> 	ret = vpe_init_microcode(vpe);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vpe.supported_reset =</div><div class='add'>+		 amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vpe.ring);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	ret = amdgpu_vpe_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='ctx'> out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_sw_fini(void *handle)</div><div class='add'>+static int vpe_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='ctx'> </div><div class='ctx'> 	release_firmware(vpe-&gt;fw);</div><div class='ctx'> 	vpe-&gt;fw = NULL;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vpe_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	vpe_ring_fini(vpe);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;adev-&gt;vpe.cmdbuf_obj,</div><div class='hunk'>@@ -390,12 +434,18 @@ static int vpe_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_hw_init(void *handle)</div><div class='add'>+static int vpe_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/* Power on VPE */</div><div class='add'>+	ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,</div><div class='add'>+						     AMD_PG_STATE_UNGATE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	ret = vpe_load_microcode(vpe);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -407,11 +457,13 @@ static int vpe_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_hw_fini(void *handle)</div><div class='add'>+static int vpe_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='ctx'> </div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;vpe.idle_work);</div><div class='add'>+</div><div class='ctx'> 	vpe_ring_stop(vpe);</div><div class='ctx'> </div><div class='ctx'> 	/* Power off VPE */</div><div class='hunk'>@@ -420,20 +472,14 @@ static int vpe_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_suspend(void *handle)</div><div class='add'>+static int vpe_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vpe.idle_work);</div><div class='del'>-</div><div class='del'>-	return vpe_hw_fini(adev);</div><div class='add'>+	return vpe_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_resume(void *handle)</div><div class='add'>+static int vpe_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vpe_hw_init(adev);</div><div class='add'>+	return vpe_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='hunk'>@@ -626,16 +672,16 @@ static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_set_clockgating_state(void *handle,</div><div class='add'>+static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vpe_set_powergating_state(void *handle,</div><div class='add'>+static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;pm.dpm_enabled)</div><div class='hunk'>@@ -813,7 +859,7 @@ static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	ret = (le32_to_cpu(adev-&gt;wb.wb[index]) == test_pattern) ? 0 : -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -853,6 +899,64 @@ static void vpe_ring_end_use(struct amdgpu_ring *ring)</div><div class='ctx'> 	schedule_delayed_work(&amp;adev-&gt;vpe.idle_work, VPE_IDLE_TIMEOUT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vpe_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+			  unsigned int vmid,</div><div class='add'>+			  struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,</div><div class='add'>+						   AMD_PG_STATE_GATE);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,</div><div class='add'>+						   AMD_PG_STATE_UNGATE);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev,</div><div class='add'>+						struct device_attribute *attr,</div><div class='add'>+						char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	return amdgpu_show_reset_mask(buf, adev-&gt;vpe.supported_reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR(vpe_reset_mask, 0444,</div><div class='add'>+		   amdgpu_get_vpe_reset_mask, NULL);</div><div class='add'>+</div><div class='add'>+int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vpe.num_instances) {</div><div class='add'>+		r = device_create_file(adev-&gt;dev, &amp;dev_attr_vpe_reset_mask);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd) {</div><div class='add'>+		if (adev-&gt;vpe.num_instances)</div><div class='add'>+			device_remove_file(adev-&gt;dev, &amp;dev_attr_vpe_reset_mask);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_ring_funcs vpe_ring_funcs = {</div><div class='ctx'> 	.type = AMDGPU_RING_TYPE_VPE,</div><div class='ctx'> 	.align_mask = 0xf,</div><div class='hunk'>@@ -884,6 +988,7 @@ static const struct amdgpu_ring_funcs vpe_ring_funcs = {</div><div class='ctx'> 	.preempt_ib = vpe_ring_preempt_ib,</div><div class='ctx'> 	.begin_use = vpe_ring_begin_use,</div><div class='ctx'> 	.end_use = vpe_ring_end_use,</div><div class='add'>+	.reset = vpe_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void vpe_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -894,14 +999,12 @@ static void vpe_set_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> const struct amd_ip_funcs vpe_ip_funcs = {</div><div class='ctx'> 	.name = "vpe_v6_1",</div><div class='ctx'> 	.early_init = vpe_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vpe_sw_init,</div><div class='ctx'> 	.sw_fini = vpe_sw_fini,</div><div class='ctx'> 	.hw_init = vpe_hw_init,</div><div class='ctx'> 	.hw_fini = vpe_hw_fini,</div><div class='ctx'> 	.suspend = vpe_suspend,</div><div class='ctx'> 	.resume = vpe_resume,</div><div class='del'>-	.soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vpe_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = vpe_set_powergating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h<br/>index 231d86d0953e..695da740a97e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h</a></div><div class='hunk'>@@ -79,6 +79,7 @@ struct amdgpu_vpe {</div><div class='ctx'> </div><div class='ctx'> 	uint32_t			num_instances;</div><div class='ctx'> 	bool				collaborate_mode;</div><div class='add'>+	uint32_t			supported_reset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);</div><div class='hunk'>@@ -86,6 +87,8 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);</div><div class='ctx'> int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);</div><div class='ctx'> int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);</div><div class='ctx'> int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);</div><div class='add'>+void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #define vpe_ring_init(vpe) ((vpe)-&gt;funcs-&gt;ring_init ? (vpe)-&gt;funcs-&gt;ring_init((vpe)) : 0)</div><div class='ctx'> #define vpe_ring_start(vpe) ((vpe)-&gt;funcs-&gt;ring_start ? (vpe)-&gt;funcs-&gt;ring_start((vpe)) : 0)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c<br/>index 8db880244324..9d934c07fa6b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c</a></div><div class='hunk'>@@ -24,13 +24,15 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_range_manager.h&gt;</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_vm.h"</div><div class='ctx'> #include "amdgpu_res_cursor.h"</div><div class='del'>-#include "amdgpu_atomfirmware.h"</div><div class='ctx'> #include "atom.h"</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_MAX_SG_SEGMENT_SIZE	(2UL &lt;&lt; 30)</div><div class='add'>+</div><div class='ctx'> struct amdgpu_vram_reservation {</div><div class='ctx'> 	u64 start;</div><div class='ctx'> 	u64 size;</div><div class='hunk'>@@ -232,6 +234,9 @@ static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj,</div><div class='ctx'> 	    !adev-&gt;gmc.vram_vendor)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (!ttm_resource_manager_used(&amp;adev-&gt;mman.vram_mgr.manager))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	return attr-&gt;mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -394,43 +399,33 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_dummy_vram_mgr_debug(struct ttm_resource_manager *man,</div><div class='del'>-				  struct drm_printer *printer)</div><div class='del'>-{</div><div class='del'>-	DRM_DEBUG_DRIVER("Dummy vram mgr debug\n");</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool amdgpu_dummy_vram_mgr_compatible(struct ttm_resource_manager *man,</div><div class='del'>-				       struct ttm_resource *res,</div><div class='del'>-				       const struct ttm_place *place,</div><div class='del'>-				       size_t size)</div><div class='add'>+int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr,</div><div class='add'>+			uint64_t address, struct amdgpu_vram_block_info *info)</div><div class='ctx'> {</div><div class='del'>-	DRM_DEBUG_DRIVER("Dummy vram mgr compatible\n");</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='add'>+	struct amdgpu_vram_mgr_resource *vres;</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+	u64 start, size;</div><div class='add'>+	int ret = -ENOENT;</div><div class='ctx'> </div><div class='del'>-static bool amdgpu_dummy_vram_mgr_intersects(struct ttm_resource_manager *man,</div><div class='del'>-				       struct ttm_resource *res,</div><div class='del'>-				       const struct ttm_place *place,</div><div class='del'>-				       size_t size)</div><div class='del'>-{</div><div class='del'>-	DRM_DEBUG_DRIVER("Dummy vram mgr intersects\n");</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='add'>+	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+	list_for_each_entry(vres, &amp;mgr-&gt;allocated_vres_list, vres_node) {</div><div class='add'>+		list_for_each_entry(block, &amp;vres-&gt;blocks, link) {</div><div class='add'>+			start = amdgpu_vram_mgr_block_start(block);</div><div class='add'>+			size = amdgpu_vram_mgr_block_size(block);</div><div class='add'>+			if ((start &lt;= address) &amp;&amp; (address &lt; (start + size))) {</div><div class='add'>+				info-&gt;start = start;</div><div class='add'>+				info-&gt;size = size;</div><div class='add'>+				memcpy(&amp;info-&gt;task, &amp;vres-&gt;task, sizeof(vres-&gt;task));</div><div class='add'>+				ret = 0;</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-static void amdgpu_dummy_vram_mgr_del(struct ttm_resource_manager *man,</div><div class='del'>-				struct ttm_resource *res)</div><div class='del'>-{</div><div class='del'>-	DRM_DEBUG_DRIVER("Dummy vram mgr deleted\n");</div><div class='del'>-}</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> </div><div class='del'>-static int amdgpu_dummy_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='del'>-			       struct ttm_buffer_object *tbo,</div><div class='del'>-			       const struct ttm_place *place,</div><div class='del'>-			       struct ttm_resource **res)</div><div class='del'>-{</div><div class='del'>-	DRM_DEBUG_DRIVER("Dummy vram mgr new\n");</div><div class='del'>-	return -ENOSPC;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -450,16 +445,18 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);</div><div class='ctx'> 	struct amdgpu_device *adev = to_amdgpu_device(mgr);</div><div class='add'>+	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);</div><div class='ctx'> 	u64 vis_usage = 0, max_bytes, min_block_size;</div><div class='ctx'> 	struct amdgpu_vram_mgr_resource *vres;</div><div class='ctx'> 	u64 size, remaining_size, lpfn, fpfn;</div><div class='add'>+	unsigned int adjust_dcc_size = 0;</div><div class='ctx'> 	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='ctx'> 	struct drm_buddy_block *block;</div><div class='ctx'> 	unsigned long pages_per_block;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	lpfn = (u64)place-&gt;lpfn &lt;&lt; PAGE_SHIFT;</div><div class='del'>-	if (!lpfn)</div><div class='add'>+	if (!lpfn || lpfn &gt; man-&gt;size)</div><div class='ctx'> 		lpfn = man-&gt;size;</div><div class='ctx'> </div><div class='ctx'> 	fpfn = (u64)place-&gt;fpfn &lt;&lt; PAGE_SHIFT;</div><div class='hunk'>@@ -468,7 +465,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> 	if (tbo-&gt;type != ttm_bo_type_kernel)</div><div class='ctx'> 		max_bytes -= AMDGPU_VM_RESERVED_VRAM;</div><div class='ctx'> </div><div class='del'>-	if (place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS) {</div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) {</div><div class='ctx'> 		pages_per_block = ~0ul;</div><div class='ctx'> 	} else {</div><div class='ctx'> #ifdef CONFIG_TRANSPARENT_HUGEPAGE</div><div class='hunk'>@@ -477,7 +474,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> 		/* default to 2MB */</div><div class='ctx'> 		pages_per_block = 2UL &lt;&lt; (20UL - PAGE_SHIFT);</div><div class='ctx'> #endif</div><div class='del'>-		pages_per_block = max_t(uint32_t, pages_per_block,</div><div class='add'>+		pages_per_block = max_t(u32, pages_per_block,</div><div class='ctx'> 					tbo-&gt;page_alignment);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -498,14 +495,29 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> 	if (place-&gt;flags &amp; TTM_PL_FLAG_TOPDOWN)</div><div class='ctx'> 		vres-&gt;flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;</div><div class='ctx'> </div><div class='del'>-	if (place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS)</div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)</div><div class='ctx'> 		vres-&gt;flags |= DRM_BUDDY_CONTIGUOUS_ALLOCATION;</div><div class='ctx'> </div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CLEARED)</div><div class='add'>+		vres-&gt;flags |= DRM_BUDDY_CLEAR_ALLOCATION;</div><div class='add'>+</div><div class='ctx'> 	if (fpfn || lpfn != mgr-&gt;mm.size)</div><div class='ctx'> 		/* Allocate blocks in desired range */</div><div class='ctx'> 		vres-&gt;flags |= DRM_BUDDY_RANGE_ALLOCATION;</div><div class='ctx'> </div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC &amp;&amp;</div><div class='add'>+	    adev-&gt;gmc.gmc_funcs-&gt;get_dcc_alignment)</div><div class='add'>+		adjust_dcc_size = amdgpu_gmc_get_dcc_alignment(adev);</div><div class='add'>+</div><div class='ctx'> 	remaining_size = (u64)vres-&gt;base.size;</div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &amp;&amp; adjust_dcc_size) {</div><div class='add'>+		unsigned int dcc_size;</div><div class='add'>+</div><div class='add'>+		dcc_size = roundup_pow_of_two(vres-&gt;base.size + adjust_dcc_size);</div><div class='add'>+		remaining_size = (u64)dcc_size;</div><div class='add'>+</div><div class='add'>+		vres-&gt;flags |= DRM_BUDDY_TRIM_DISABLE;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;mgr-&gt;lock);</div><div class='ctx'> 	while (remaining_size) {</div><div class='hunk'>@@ -514,21 +526,32 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> 		else</div><div class='ctx'> 			min_block_size = mgr-&gt;default_page_size;</div><div class='ctx'> </div><div class='del'>-		BUG_ON(min_block_size &lt; mm-&gt;chunk_size);</div><div class='del'>-</div><div class='del'>-		/* Limit maximum size to 2GiB due to SG table limitations */</div><div class='del'>-		size = min(remaining_size, 2ULL &lt;&lt; 30);</div><div class='add'>+		size = remaining_size;</div><div class='ctx'> </div><div class='del'>-		if ((size &gt;= (u64)pages_per_block &lt;&lt; PAGE_SHIFT) &amp;&amp;</div><div class='del'>-				!(size &amp; (((u64)pages_per_block &lt;&lt; PAGE_SHIFT) - 1)))</div><div class='add'>+		if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &amp;&amp; adjust_dcc_size)</div><div class='add'>+			min_block_size = size;</div><div class='add'>+		else if ((size &gt;= (u64)pages_per_block &lt;&lt; PAGE_SHIFT) &amp;&amp;</div><div class='add'>+			 !(size &amp; (((u64)pages_per_block &lt;&lt; PAGE_SHIFT) - 1)))</div><div class='ctx'> 			min_block_size = (u64)pages_per_block &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='add'>+		BUG_ON(min_block_size &lt; mm-&gt;chunk_size);</div><div class='add'>+</div><div class='ctx'> 		r = drm_buddy_alloc_blocks(mm, fpfn,</div><div class='ctx'> 					   lpfn,</div><div class='ctx'> 					   size,</div><div class='ctx'> 					   min_block_size,</div><div class='ctx'> 					   &amp;vres-&gt;blocks,</div><div class='ctx'> 					   vres-&gt;flags);</div><div class='add'>+</div><div class='add'>+		if (unlikely(r == -ENOSPC) &amp;&amp; pages_per_block == ~0ul &amp;&amp;</div><div class='add'>+		    !(place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS)) {</div><div class='add'>+			vres-&gt;flags &amp;= ~DRM_BUDDY_CONTIGUOUS_ALLOCATION;</div><div class='add'>+			pages_per_block = max_t(u32, 2UL &lt;&lt; (20UL - PAGE_SHIFT),</div><div class='add'>+						tbo-&gt;page_alignment);</div><div class='add'>+</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (unlikely(r))</div><div class='ctx'> 			goto error_free_blocks;</div><div class='ctx'> </div><div class='hunk'>@@ -537,6 +560,26 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> 		else</div><div class='ctx'> 			remaining_size -= size;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	vres-&gt;task.pid = task_pid_nr(current);</div><div class='add'>+	get_task_comm(vres-&gt;task.comm, current);</div><div class='add'>+	list_add_tail(&amp;vres-&gt;vres_node, &amp;mgr-&gt;allocated_vres_list);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;flags &amp; AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS &amp;&amp; adjust_dcc_size) {</div><div class='add'>+		struct drm_buddy_block *dcc_block;</div><div class='add'>+		unsigned long dcc_start;</div><div class='add'>+		u64 trim_start;</div><div class='add'>+</div><div class='add'>+		dcc_block = amdgpu_vram_mgr_first_block(&amp;vres-&gt;blocks);</div><div class='add'>+		/* Adjust the start address for DCC buffers only */</div><div class='add'>+		dcc_start =</div><div class='add'>+			roundup((unsigned long)amdgpu_vram_mgr_block_start(dcc_block),</div><div class='add'>+				adjust_dcc_size);</div><div class='add'>+		trim_start = (u64)dcc_start;</div><div class='add'>+		drm_buddy_block_trim(mm, &amp;trim_start,</div><div class='add'>+				     (u64)vres-&gt;base.size,</div><div class='add'>+				     &amp;vres-&gt;blocks);</div><div class='add'>+	}</div><div class='ctx'> 	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	vres-&gt;base.start = 0;</div><div class='hunk'>@@ -571,7 +614,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> error_free_blocks:</div><div class='del'>-	drm_buddy_free_list(mm, &amp;vres-&gt;blocks);</div><div class='add'>+	drm_buddy_free_list(mm, &amp;vres-&gt;blocks, 0);</div><div class='ctx'> 	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> error_fini:</div><div class='ctx'> 	ttm_resource_fini(man, &amp;vres-&gt;base);</div><div class='hunk'>@@ -599,12 +642,15 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man,</div><div class='ctx'> 	uint64_t vis_usage = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+</div><div class='add'>+	list_del(&amp;vres-&gt;vres_node);</div><div class='add'>+	memset(&amp;vres-&gt;task, 0, sizeof(vres-&gt;task));</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry(block, &amp;vres-&gt;blocks, link)</div><div class='ctx'> 		vis_usage += amdgpu_vram_mgr_vis_size(adev, block);</div><div class='ctx'> </div><div class='add'>+	drm_buddy_free_list(mm, &amp;vres-&gt;blocks, vres-&gt;flags);</div><div class='ctx'> 	amdgpu_vram_mgr_do_reserve(man);</div><div class='del'>-</div><div class='del'>-	drm_buddy_free_list(mm, &amp;vres-&gt;blocks);</div><div class='ctx'> 	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	atomic64_sub(vis_usage, &amp;mgr-&gt;vis_usage);</div><div class='hunk'>@@ -646,7 +692,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,</div><div class='ctx'> 	amdgpu_res_first(res, offset, length, &amp;cursor);</div><div class='ctx'> 	while (cursor.remaining) {</div><div class='ctx'> 		num_entries++;</div><div class='del'>-		amdgpu_res_next(&amp;cursor, cursor.size);</div><div class='add'>+		amdgpu_res_next(&amp;cursor, min(cursor.size, AMDGPU_MAX_SG_SEGMENT_SIZE));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = sg_alloc_table(*sgt, num_entries, GFP_KERNEL);</div><div class='hunk'>@@ -666,7 +712,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,</div><div class='ctx'> 	amdgpu_res_first(res, offset, length, &amp;cursor);</div><div class='ctx'> 	for_each_sgtable_sg((*sgt), sg, i) {</div><div class='ctx'> 		phys_addr_t phys = cursor.start + adev-&gt;gmc.aper_base;</div><div class='del'>-		size_t size = cursor.size;</div><div class='add'>+		unsigned long size = min(cursor.size, AMDGPU_MAX_SG_SEGMENT_SIZE);</div><div class='ctx'> 		dma_addr_t addr;</div><div class='ctx'> </div><div class='ctx'> 		addr = dma_map_resource(dev, phys, size, dir,</div><div class='hunk'>@@ -679,7 +725,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,</div><div class='ctx'> 		sg_dma_address(sg) = addr;</div><div class='ctx'> 		sg_dma_len(sg) = size;</div><div class='ctx'> </div><div class='del'>-		amdgpu_res_next(&amp;cursor, cursor.size);</div><div class='add'>+		amdgpu_res_next(&amp;cursor, size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -737,6 +783,23 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vram_mgr_clear_reset_blocks - reset clear blocks</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='add'>+ *</div><div class='add'>+ * Reset the cleared drm buddy blocks.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vram_mgr *mgr = &amp;adev-&gt;mman.vram_mgr;</div><div class='add'>+	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+	drm_buddy_reset_clear(mm, false);</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vram_mgr_intersects - test each drm buddy block for intersection</div><div class='ctx'>  *</div><div class='ctx'>  * @man: TTM memory type manager</div><div class='hunk'>@@ -833,14 +896,6 @@ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man,</div><div class='ctx'> 	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct ttm_resource_manager_func amdgpu_dummy_vram_mgr_func = {</div><div class='del'>-	.alloc	= amdgpu_dummy_vram_mgr_new,</div><div class='del'>-	.free	= amdgpu_dummy_vram_mgr_del,</div><div class='del'>-	.intersects = amdgpu_dummy_vram_mgr_intersects,</div><div class='del'>-	.compatible = amdgpu_dummy_vram_mgr_compatible,</div><div class='del'>-	.debug	= amdgpu_dummy_vram_mgr_debug</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = {</div><div class='ctx'> 	.alloc	= amdgpu_vram_mgr_new,</div><div class='ctx'> 	.free	= amdgpu_vram_mgr_del,</div><div class='hunk'>@@ -862,24 +917,22 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev)</div><div class='ctx'> 	struct ttm_resource_manager *man = &amp;mgr-&gt;manager;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='add'>+	man-&gt;cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev-&gt;gmc.real_vram_size);</div><div class='add'>+	if (IS_ERR(man-&gt;cg))</div><div class='add'>+		return PTR_ERR(man-&gt;cg);</div><div class='ctx'> 	ttm_resource_manager_init(man, &amp;adev-&gt;mman.bdev,</div><div class='ctx'> 				  adev-&gt;gmc.real_vram_size);</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;mgr-&gt;lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;mgr-&gt;reservations_pending);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;mgr-&gt;reserved_pages);</div><div class='add'>+	INIT_LIST_HEAD(&amp;mgr-&gt;allocated_vres_list);</div><div class='ctx'> 	mgr-&gt;default_page_size = PAGE_SIZE;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;gmc.is_app_apu) {</div><div class='del'>-		man-&gt;func = &amp;amdgpu_vram_mgr_func;</div><div class='del'>-</div><div class='del'>-		err = drm_buddy_init(&amp;mgr-&gt;mm, man-&gt;size, PAGE_SIZE);</div><div class='del'>-		if (err)</div><div class='del'>-			return err;</div><div class='del'>-	} else {</div><div class='del'>-		man-&gt;func = &amp;amdgpu_dummy_vram_mgr_func;</div><div class='del'>-		DRM_INFO("Setup dummy vram mgr\n");</div><div class='del'>-	}</div><div class='add'>+	man-&gt;func = &amp;amdgpu_vram_mgr_func;</div><div class='add'>+	err = drm_buddy_init(&amp;mgr-&gt;mm, man-&gt;size, PAGE_SIZE);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='ctx'> 	ttm_set_driver_manager(&amp;adev-&gt;mman.bdev, TTM_PL_VRAM, &amp;mgr-&gt;manager);</div><div class='ctx'> 	ttm_resource_manager_set_used(man, true);</div><div class='hunk'>@@ -912,7 +965,7 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		kfree(rsv);</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(rsv, temp, &amp;mgr-&gt;reserved_pages, blocks) {</div><div class='del'>-		drm_buddy_free_list(&amp;mgr-&gt;mm, &amp;rsv-&gt;allocated);</div><div class='add'>+		drm_buddy_free_list(&amp;mgr-&gt;mm, &amp;rsv-&gt;allocated, 0);</div><div class='ctx'> 		kfree(rsv);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!adev-&gt;gmc.is_app_apu)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h<br/>index 0e04e42cf809..5f5fd9a911c2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h</a></div><div class='hunk'>@@ -35,12 +35,26 @@ struct amdgpu_vram_mgr {</div><div class='ctx'> 	struct list_head reserved_pages;</div><div class='ctx'> 	atomic64_t vis_usage;</div><div class='ctx'> 	u64 default_page_size;</div><div class='add'>+	struct list_head allocated_vres_list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_vres_task {</div><div class='add'>+	pid_t pid;</div><div class='add'>+	char  comm[TASK_COMM_LEN];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_vram_block_info {</div><div class='add'>+	u64 start;</div><div class='add'>+	u64 size;</div><div class='add'>+	struct amdgpu_vres_task task;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_vram_mgr_resource {</div><div class='ctx'> 	struct ttm_resource base;</div><div class='ctx'> 	struct list_head blocks;</div><div class='ctx'> 	unsigned long flags;</div><div class='add'>+	struct list_head vres_node;</div><div class='add'>+	struct amdgpu_vres_task task;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline u64 amdgpu_vram_mgr_block_start(struct drm_buddy_block *block)</div><div class='hunk'>@@ -53,10 +67,26 @@ static inline u64 amdgpu_vram_mgr_block_size(struct drm_buddy_block *block)</div><div class='ctx'> 	return (u64)PAGE_SIZE &lt;&lt; drm_buddy_block_order(block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool amdgpu_vram_mgr_is_cleared(struct drm_buddy_block *block)</div><div class='add'>+{</div><div class='add'>+	return drm_buddy_block_is_clear(block);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline struct amdgpu_vram_mgr_resource *</div><div class='ctx'> to_amdgpu_vram_mgr_resource(struct ttm_resource *res)</div><div class='ctx'> {</div><div class='ctx'> 	return container_of(res, struct amdgpu_vram_mgr_resource, base);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline void amdgpu_vram_mgr_set_cleared(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vram_mgr_resource *ares = to_amdgpu_vram_mgr_resource(res);</div><div class='add'>+</div><div class='add'>+	WARN_ON(ares-&gt;flags &amp; DRM_BUDDY_CLEARED);</div><div class='add'>+	ares-&gt;flags |= DRM_BUDDY_CLEARED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr,</div><div class='add'>+		uint64_t address, struct amdgpu_vram_block_info *info);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c<br/>index 2b99eed5ba19..1083db8cea2e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c</a></div><div class='hunk'>@@ -27,6 +27,9 @@</div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> #include "../amdxcp/amdgpu_xcp_drv.h"</div><div class='ctx'> </div><div class='add'>+static void amdgpu_xcp_sysfs_entries_init(struct amdgpu_xcp_mgr *xcp_mgr);</div><div class='add'>+static void amdgpu_xcp_sysfs_entries_update(struct amdgpu_xcp_mgr *xcp_mgr);</div><div class='add'>+</div><div class='ctx'> static int __amdgpu_xcp_run(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 			    struct amdgpu_xcp_ip *xcp_ip, int xcp_state)</div><div class='ctx'> {</div><div class='hunk'>@@ -117,6 +120,25 @@ static void __amdgpu_xcp_add_block(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,</div><div class='ctx'> 	xcp-&gt;valid = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void __amdgpu_xcp_set_unique_id(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='add'>+				       int xcp_id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp *xcp = &amp;xcp_mgr-&gt;xcp[xcp_id];</div><div class='add'>+	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='add'>+	uint32_t inst_mask;</div><div class='add'>+	uint64_t uid;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &amp;inst_mask) &amp;&amp;</div><div class='add'>+	    inst_mask) {</div><div class='add'>+		i = GET_INST(GC, (ffs(inst_mask) - 1));</div><div class='add'>+		uid = amdgpu_device_get_uid(xcp_mgr-&gt;adev-&gt;uid_info,</div><div class='add'>+					    AMDGPU_UID_TYPE_XCD, i);</div><div class='add'>+		if (uid)</div><div class='add'>+			xcp-&gt;unique_id = uid;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_xcp_init(struct amdgpu_xcp_mgr *xcp_mgr, int num_xcps, int mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='hunk'>@@ -155,6 +177,7 @@ int amdgpu_xcp_init(struct amdgpu_xcp_mgr *xcp_mgr, int num_xcps, int mode)</div><div class='ctx'> 			else</div><div class='ctx'> 				xcp_mgr-&gt;xcp[i].mem_id = mem_id;</div><div class='ctx'> 		}</div><div class='add'>+		__amdgpu_xcp_set_unique_id(xcp_mgr, i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	xcp_mgr-&gt;num_xcps = num_xcps;</div><div class='hunk'>@@ -189,7 +212,7 @@ static int __amdgpu_xcp_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> </div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	amdgpu_xcp_sysfs_entries_update(xcp_mgr);</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;xcp_mgr-&gt;xcp_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -215,19 +238,38 @@ int amdgpu_xcp_restore_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='ctx'> 	return __amdgpu_xcp_switch_partition_mode(xcp_mgr, xcp_mgr-&gt;mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool __amdgpu_xcp_is_cached_mode_valid(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='add'>+{</div><div class='add'>+	if (!xcp_mgr-&gt;funcs || !xcp_mgr-&gt;funcs-&gt;query_partition_mode)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(xcp_mgr-&gt;adev) &amp;&amp;</div><div class='add'>+	    xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (xcp_mgr-&gt;mode != AMDGPU_XCP_MODE_NONE &amp;&amp;</div><div class='add'>+	    xcp_mgr-&gt;mode != AMDGPU_XCP_MODE_TRANS)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_xcp_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)</div><div class='ctx'> {</div><div class='ctx'> 	int mode;</div><div class='ctx'> </div><div class='del'>-	if (xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE)</div><div class='del'>-		return xcp_mgr-&gt;mode;</div><div class='del'>-</div><div class='del'>-	if (!xcp_mgr-&gt;funcs || !xcp_mgr-&gt;funcs-&gt;query_partition_mode)</div><div class='add'>+	if (__amdgpu_xcp_is_cached_mode_valid(xcp_mgr))</div><div class='ctx'> 		return xcp_mgr-&gt;mode;</div><div class='ctx'> </div><div class='ctx'> 	if (!(flags &amp; AMDGPU_XCP_FL_LOCKED))</div><div class='ctx'> 		mutex_lock(&amp;xcp_mgr-&gt;xcp_lock);</div><div class='ctx'> 	mode = xcp_mgr-&gt;funcs-&gt;query_partition_mode(xcp_mgr);</div><div class='add'>+</div><div class='add'>+	/* First time query for VF, set the mode here */</div><div class='add'>+	if (amdgpu_sriov_vf(xcp_mgr-&gt;adev) &amp;&amp;</div><div class='add'>+	    xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE)</div><div class='add'>+		xcp_mgr-&gt;mode = mode;</div><div class='add'>+</div><div class='ctx'> 	if (xcp_mgr-&gt;mode != AMDGPU_XCP_MODE_TRANS &amp;&amp; mode != xcp_mgr-&gt;mode)</div><div class='ctx'> 		dev_WARN(</div><div class='ctx'> 			xcp_mgr-&gt;adev-&gt;dev,</div><div class='hunk'>@@ -256,9 +298,10 @@ static int amdgpu_xcp_dev_alloc(struct amdgpu_device *adev)</div><div class='ctx'> 		if (ret == -ENOSPC) {</div><div class='ctx'> 			dev_warn(adev-&gt;dev,</div><div class='ctx'> 			"Skip xcp node #%d when out of drm node resource.", i);</div><div class='del'>-			return 0;</div><div class='add'>+			ret = 0;</div><div class='add'>+			goto out;</div><div class='ctx'> 		} else if (ret) {</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Redirect all IOCTLs to the primary device */</div><div class='hunk'>@@ -271,9 +314,14 @@ static int amdgpu_xcp_dev_alloc(struct amdgpu_device *adev)</div><div class='ctx'> 		p_ddev-&gt;vma_offset_manager = ddev-&gt;vma_offset_manager;</div><div class='ctx'> 		p_ddev-&gt;driver = &amp;amdgpu_partition_driver;</div><div class='ctx'> 		adev-&gt;xcp_mgr-&gt;xcp[i].ddev = p_ddev;</div><div class='add'>+</div><div class='add'>+		dev_set_drvdata(p_ddev-&gt;dev, &amp;adev-&gt;xcp_mgr-&gt;xcp[i]);</div><div class='ctx'> 	}</div><div class='add'>+	ret = 0;</div><div class='add'>+out:</div><div class='add'>+	amdgpu_xcp_sysfs_entries_init(adev-&gt;xcp_mgr);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_xcp_mgr_init(struct amdgpu_device *adev, int init_mode,</div><div class='hunk'>@@ -281,9 +329,9 @@ int amdgpu_xcp_mgr_init(struct amdgpu_device *adev, int init_mode,</div><div class='ctx'> 			struct amdgpu_xcp_mgr_funcs *xcp_funcs)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_xcp_mgr *xcp_mgr;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	if (!xcp_funcs || !xcp_funcs-&gt;switch_partition_mode ||</div><div class='del'>-	    !xcp_funcs-&gt;get_ip_details)</div><div class='add'>+	if (!xcp_funcs || !xcp_funcs-&gt;get_ip_details)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	xcp_mgr = kzalloc(sizeof(*xcp_mgr), GFP_KERNEL);</div><div class='hunk'>@@ -300,6 +348,8 @@ int amdgpu_xcp_mgr_init(struct amdgpu_device *adev, int init_mode,</div><div class='ctx'> 		amdgpu_xcp_init(xcp_mgr, init_num_xcps, init_mode);</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;xcp_mgr = xcp_mgr;</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; ++i)</div><div class='add'>+		xcp_mgr-&gt;xcp[i].xcp_mgr = xcp_mgr;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_xcp_dev_alloc(adev);</div><div class='ctx'> }</div><div class='hunk'>@@ -376,6 +426,7 @@ void amdgpu_xcp_dev_unplug(struct amdgpu_device *adev)</div><div class='ctx'> 		p_ddev-&gt;primary-&gt;dev = adev-&gt;xcp_mgr-&gt;xcp[i].pdev;</div><div class='ctx'> 		p_ddev-&gt;driver =  adev-&gt;xcp_mgr-&gt;xcp[i].driver;</div><div class='ctx'> 		p_ddev-&gt;vma_offset_manager = adev-&gt;xcp_mgr-&gt;xcp[i].vma_offset_manager;</div><div class='add'>+		amdgpu_xcp_drm_dev_free(p_ddev);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -421,9 +472,636 @@ void amdgpu_xcp_release_sched(struct amdgpu_device *adev,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	sched = entity-&gt;entity.rq-&gt;sched;</div><div class='del'>-	if (sched-&gt;ready) {</div><div class='add'>+	if (drm_sched_wqueue_ready(sched)) {</div><div class='ctx'> 		ring = to_amdgpu_ring(entity-&gt;entity.rq-&gt;sched);</div><div class='ctx'> 		atomic_dec(&amp;adev-&gt;xcp_mgr-&gt;xcp[ring-&gt;xcp_id].ref_cnt);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_xcp_select_scheds(struct amdgpu_device *adev,</div><div class='add'>+			     u32 hw_ip, u32 hw_prio,</div><div class='add'>+			     struct amdgpu_fpriv *fpriv,</div><div class='add'>+			     unsigned int *num_scheds,</div><div class='add'>+			     struct drm_gpu_scheduler ***scheds)</div><div class='add'>+{</div><div class='add'>+	u32 sel_xcp_id;</div><div class='add'>+	int i;</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr = adev-&gt;xcp_mgr;</div><div class='add'>+</div><div class='add'>+	if (fpriv-&gt;xcp_id == AMDGPU_XCP_NO_PARTITION) {</div><div class='add'>+		u32 least_ref_cnt = ~0;</div><div class='add'>+</div><div class='add'>+		fpriv-&gt;xcp_id = 0;</div><div class='add'>+		for (i = 0; i &lt; xcp_mgr-&gt;num_xcps; i++) {</div><div class='add'>+			u32 total_ref_cnt;</div><div class='add'>+</div><div class='add'>+			total_ref_cnt = atomic_read(&amp;xcp_mgr-&gt;xcp[i].ref_cnt);</div><div class='add'>+			if (total_ref_cnt &lt; least_ref_cnt) {</div><div class='add'>+				fpriv-&gt;xcp_id = i;</div><div class='add'>+				least_ref_cnt = total_ref_cnt;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	sel_xcp_id = fpriv-&gt;xcp_id;</div><div class='add'>+</div><div class='add'>+	if (xcp_mgr-&gt;xcp[sel_xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds) {</div><div class='add'>+		*num_scheds =</div><div class='add'>+			xcp_mgr-&gt;xcp[fpriv-&gt;xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds;</div><div class='add'>+		*scheds =</div><div class='add'>+			xcp_mgr-&gt;xcp[fpriv-&gt;xcp_id].gpu_sched[hw_ip][hw_prio].sched;</div><div class='add'>+		atomic_inc(&amp;adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id].ref_cnt);</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Selected partition #%d", sel_xcp_id);</div><div class='add'>+	} else {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to schedule partition #%d.", sel_xcp_id);</div><div class='add'>+		return -ENOENT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_set_xcp_id(struct amdgpu_device *adev,</div><div class='add'>+			      uint32_t inst_idx,</div><div class='add'>+			      struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	int xcp_id;</div><div class='add'>+	enum AMDGPU_XCP_IP_BLOCK ip_blk;</div><div class='add'>+	uint32_t inst_mask;</div><div class='add'>+</div><div class='add'>+	ring-&gt;xcp_id = AMDGPU_XCP_NO_PARTITION;</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE)</div><div class='add'>+		adev-&gt;gfx.enforce_isolation[0].xcp_id = ring-&gt;xcp_id;</div><div class='add'>+	if ((adev-&gt;xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE) ||</div><div class='add'>+	    (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_CPER))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	inst_mask = 1 &lt;&lt; inst_idx;</div><div class='add'>+</div><div class='add'>+	switch (ring-&gt;funcs-&gt;type) {</div><div class='add'>+	case AMDGPU_HW_IP_GFX:</div><div class='add'>+	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='add'>+	case AMDGPU_RING_TYPE_KIQ:</div><div class='add'>+		ip_blk = AMDGPU_XCP_GFX;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_SDMA:</div><div class='add'>+		ip_blk = AMDGPU_XCP_SDMA;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_ENC:</div><div class='add'>+	case AMDGPU_RING_TYPE_VCN_JPEG:</div><div class='add'>+		ip_blk = AMDGPU_XCP_VCN;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "Not support ring type %d!", ring-&gt;funcs-&gt;type);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (xcp_id = 0; xcp_id &lt; adev-&gt;xcp_mgr-&gt;num_xcps; xcp_id++) {</div><div class='add'>+		if (adev-&gt;xcp_mgr-&gt;xcp[xcp_id].ip[ip_blk].inst_mask &amp; inst_mask) {</div><div class='add'>+			ring-&gt;xcp_id = xcp_id;</div><div class='add'>+			dev_dbg(adev-&gt;dev, "ring:%s xcp_id :%u", ring-&gt;name,</div><div class='add'>+				ring-&gt;xcp_id);</div><div class='add'>+			if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE)</div><div class='add'>+				adev-&gt;gfx.enforce_isolation[xcp_id].xcp_id = xcp_id;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_xcp_gpu_sched_update(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_ring *ring,</div><div class='add'>+					unsigned int sel_xcp_id)</div><div class='add'>+{</div><div class='add'>+	unsigned int *num_gpu_sched;</div><div class='add'>+</div><div class='add'>+	num_gpu_sched = &amp;adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id]</div><div class='add'>+			.gpu_sched[ring-&gt;funcs-&gt;type][ring-&gt;hw_prio].num_scheds;</div><div class='add'>+	adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id].gpu_sched[ring-&gt;funcs-&gt;type][ring-&gt;hw_prio]</div><div class='add'>+			.sched[(*num_gpu_sched)++] = &amp;ring-&gt;sched;</div><div class='add'>+	dev_dbg(adev-&gt;dev, "%s :[%d] gpu_sched[%d][%d] = %d",</div><div class='add'>+		ring-&gt;name, sel_xcp_id, ring-&gt;funcs-&gt;type,</div><div class='add'>+		ring-&gt;hw_prio, *num_gpu_sched);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_xcp_sched_list_update(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; i++) {</div><div class='add'>+		atomic_set(&amp;adev-&gt;xcp_mgr-&gt;xcp[i].ref_cnt, 0);</div><div class='add'>+		memset(adev-&gt;xcp_mgr-&gt;xcp[i].gpu_sched, 0, sizeof(adev-&gt;xcp_mgr-&gt;xcp-&gt;gpu_sched));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_RINGS; i++) {</div><div class='add'>+		ring = adev-&gt;rings[i];</div><div class='add'>+		if (!ring || !ring-&gt;sched.ready || ring-&gt;no_scheduler)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		amdgpu_xcp_gpu_sched_update(adev, ring, ring-&gt;xcp_id);</div><div class='add'>+</div><div class='add'>+		/* VCN may be shared by two partitions under CPX MODE in certain</div><div class='add'>+		 * configs.</div><div class='add'>+		 */</div><div class='add'>+		if ((ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC ||</div><div class='add'>+		     ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_JPEG) &amp;&amp;</div><div class='add'>+		    (adev-&gt;xcp_mgr-&gt;num_xcps &gt; adev-&gt;vcn.num_vcn_inst))</div><div class='add'>+			amdgpu_xcp_gpu_sched_update(adev, ring, ring-&gt;xcp_id + 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;num_rings; i++) {</div><div class='add'>+		struct amdgpu_ring *ring = adev-&gt;rings[i];</div><div class='add'>+</div><div class='add'>+		if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE ||</div><div class='add'>+			ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_KIQ)</div><div class='add'>+			amdgpu_set_xcp_id(adev, ring-&gt;xcc_id, ring);</div><div class='add'>+		else</div><div class='add'>+			amdgpu_set_xcp_id(adev, ring-&gt;me, ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_xcp_sched_list_update(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='add'>+</div><div class='add'>+	xcp_mgr-&gt;supp_xcp_modes = 0;</div><div class='add'>+</div><div class='add'>+	switch (NUM_XCC(adev-&gt;gfx.xcc_mask)) {</div><div class='add'>+	case 8:</div><div class='add'>+		xcp_mgr-&gt;supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_DPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_QPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_CPX_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case 6:</div><div class='add'>+		xcp_mgr-&gt;supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_TPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_CPX_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		xcp_mgr-&gt;supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_DPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_CPX_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		xcp_mgr-&gt;supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_CPX_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		xcp_mgr-&gt;supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |</div><div class='add'>+					  BIT(AMDGPU_CPX_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_xcp_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)</div><div class='add'>+{</div><div class='add'>+	/* TODO:</div><div class='add'>+	 * Stop user queues and threads, and make sure GPU is empty of work.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (flags &amp; AMDGPU_XCP_OPS_KFD)</div><div class='add'>+		amdgpu_amdkfd_device_fini_sw(xcp_mgr-&gt;adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_xcp_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (flags &amp; AMDGPU_XCP_OPS_KFD) {</div><div class='add'>+		amdgpu_amdkfd_device_probe(xcp_mgr-&gt;adev);</div><div class='add'>+		amdgpu_amdkfd_device_init(xcp_mgr-&gt;adev);</div><div class='add'>+		/* If KFD init failed, return failure */</div><div class='add'>+		if (!xcp_mgr-&gt;adev-&gt;kfd.init_complete)</div><div class='add'>+			ret = -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*====================== xcp sysfs - configuration ======================*/</div><div class='add'>+#define XCP_CFG_SYSFS_RES_ATTR_SHOW(_name)                         \</div><div class='add'>+	static ssize_t amdgpu_xcp_res_sysfs_##_name##_show(        \</div><div class='add'>+		struct amdgpu_xcp_res_details *xcp_res, char *buf) \</div><div class='add'>+	{                                                          \</div><div class='add'>+		return sysfs_emit(buf, "%d\n", xcp_res-&gt;_name);    \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+struct amdgpu_xcp_res_sysfs_attribute {</div><div class='add'>+	struct attribute attr;</div><div class='add'>+	ssize_t (*show)(struct amdgpu_xcp_res_details *xcp_res, char *buf);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XCP_CFG_SYSFS_RES_ATTR(_name)                                        \</div><div class='add'>+	struct amdgpu_xcp_res_sysfs_attribute xcp_res_sysfs_attr_##_name = { \</div><div class='add'>+		.attr = { .name = __stringify(_name), .mode = 0400 },        \</div><div class='add'>+		.show = amdgpu_xcp_res_sysfs_##_name##_show,                 \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+XCP_CFG_SYSFS_RES_ATTR_SHOW(num_inst)</div><div class='add'>+XCP_CFG_SYSFS_RES_ATTR(num_inst);</div><div class='add'>+XCP_CFG_SYSFS_RES_ATTR_SHOW(num_shared)</div><div class='add'>+XCP_CFG_SYSFS_RES_ATTR(num_shared);</div><div class='add'>+</div><div class='add'>+#define XCP_CFG_SYSFS_RES_ATTR_PTR(_name) xcp_res_sysfs_attr_##_name.attr</div><div class='add'>+</div><div class='add'>+static struct attribute *xcp_cfg_res_sysfs_attrs[] = {</div><div class='add'>+	&amp;XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst),</div><div class='add'>+	&amp;XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *xcp_desc[] = {</div><div class='add'>+	[AMDGPU_SPX_PARTITION_MODE] = "SPX",</div><div class='add'>+	[AMDGPU_DPX_PARTITION_MODE] = "DPX",</div><div class='add'>+	[AMDGPU_TPX_PARTITION_MODE] = "TPX",</div><div class='add'>+	[AMDGPU_QPX_PARTITION_MODE] = "QPX",</div><div class='add'>+	[AMDGPU_CPX_PARTITION_MODE] = "CPX",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *nps_desc[] = {</div><div class='add'>+	[UNKNOWN_MEMORY_PARTITION_MODE] = "UNKNOWN",</div><div class='add'>+	[AMDGPU_NPS1_PARTITION_MODE] = "NPS1",</div><div class='add'>+	[AMDGPU_NPS2_PARTITION_MODE] = "NPS2",</div><div class='add'>+	[AMDGPU_NPS3_PARTITION_MODE] = "NPS3",</div><div class='add'>+	[AMDGPU_NPS4_PARTITION_MODE] = "NPS4",</div><div class='add'>+	[AMDGPU_NPS6_PARTITION_MODE] = "NPS6",</div><div class='add'>+	[AMDGPU_NPS8_PARTITION_MODE] = "NPS8",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs);</div><div class='add'>+</div><div class='add'>+#define to_xcp_attr(x) \</div><div class='add'>+	container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr)</div><div class='add'>+#define to_xcp_res(x) container_of(x, struct amdgpu_xcp_res_details, kobj)</div><div class='add'>+</div><div class='add'>+static ssize_t xcp_cfg_res_sysfs_attr_show(struct kobject *kobj,</div><div class='add'>+					   struct attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_res_sysfs_attribute *attribute;</div><div class='add'>+	struct amdgpu_xcp_res_details *xcp_res;</div><div class='add'>+</div><div class='add'>+	attribute = to_xcp_attr(attr);</div><div class='add'>+	xcp_res = to_xcp_res(kobj);</div><div class='add'>+</div><div class='add'>+	if (!attribute-&gt;show)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	return attribute-&gt;show(xcp_res, buf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct sysfs_ops xcp_cfg_res_sysfs_ops = {</div><div class='add'>+	.show = xcp_cfg_res_sysfs_attr_show,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct kobj_type xcp_cfg_res_sysfs_ktype = {</div><div class='add'>+	.sysfs_ops = &amp;xcp_cfg_res_sysfs_ops,</div><div class='add'>+	.default_groups = xcp_cfg_res_sysfs_groups,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const char *xcp_res_names[] = {</div><div class='add'>+	[AMDGPU_XCP_RES_XCC] = "xcc",</div><div class='add'>+	[AMDGPU_XCP_RES_DMA] = "dma",</div><div class='add'>+	[AMDGPU_XCP_RES_DEC] = "dec",</div><div class='add'>+	[AMDGPU_XCP_RES_JPEG] = "jpeg",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int amdgpu_xcp_get_res_info(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='add'>+				   int mode,</div><div class='add'>+				   struct amdgpu_xcp_cfg *xcp_cfg)</div><div class='add'>+{</div><div class='add'>+	if (xcp_mgr-&gt;funcs &amp;&amp; xcp_mgr-&gt;funcs-&gt;get_xcp_res_info)</div><div class='add'>+		return xcp_mgr-&gt;funcs-&gt;get_xcp_res_info(xcp_mgr, mode, xcp_cfg);</div><div class='add'>+</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define to_xcp_cfg(x) container_of(x, struct amdgpu_xcp_cfg, kobj)</div><div class='add'>+static ssize_t supported_xcp_configs_show(struct kobject *kobj,</div><div class='add'>+					  struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr = xcp_cfg-&gt;xcp_mgr;</div><div class='add'>+	int size = 0, mode;</div><div class='add'>+	char *sep = "";</div><div class='add'>+</div><div class='add'>+	if (!xcp_mgr || !xcp_mgr-&gt;supp_xcp_modes)</div><div class='add'>+		return sysfs_emit(buf, "Not supported\n");</div><div class='add'>+</div><div class='add'>+	for_each_inst(mode, xcp_mgr-&gt;supp_xcp_modes) {</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s%s", sep, xcp_desc[mode]);</div><div class='add'>+		sep = ", ";</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t supported_nps_configs_show(struct kobject *kobj,</div><div class='add'>+					  struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);</div><div class='add'>+	int size = 0, mode;</div><div class='add'>+	char *sep = "";</div><div class='add'>+</div><div class='add'>+	if (!xcp_cfg || !xcp_cfg-&gt;compatible_nps_modes)</div><div class='add'>+		return sysfs_emit(buf, "Not supported\n");</div><div class='add'>+</div><div class='add'>+	for_each_inst(mode, xcp_cfg-&gt;compatible_nps_modes) {</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s%s", sep, nps_desc[mode]);</div><div class='add'>+		sep = ", ";</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t xcp_config_show(struct kobject *kobj,</div><div class='add'>+			       struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%s\n",</div><div class='add'>+			  amdgpu_gfx_compute_mode_desc(xcp_cfg-&gt;mode));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t xcp_config_store(struct kobject *kobj,</div><div class='add'>+				struct kobj_attribute *attr,</div><div class='add'>+				const char *buf, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);</div><div class='add'>+	int mode, r;</div><div class='add'>+</div><div class='add'>+	if (!strncasecmp("SPX", buf, strlen("SPX")))</div><div class='add'>+		mode = AMDGPU_SPX_PARTITION_MODE;</div><div class='add'>+	else if (!strncasecmp("DPX", buf, strlen("DPX")))</div><div class='add'>+		mode = AMDGPU_DPX_PARTITION_MODE;</div><div class='add'>+	else if (!strncasecmp("TPX", buf, strlen("TPX")))</div><div class='add'>+		mode = AMDGPU_TPX_PARTITION_MODE;</div><div class='add'>+	else if (!strncasecmp("QPX", buf, strlen("QPX")))</div><div class='add'>+		mode = AMDGPU_QPX_PARTITION_MODE;</div><div class='add'>+	else if (!strncasecmp("CPX", buf, strlen("CPX")))</div><div class='add'>+		mode = AMDGPU_CPX_PARTITION_MODE;</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_xcp_get_res_info(xcp_cfg-&gt;xcp_mgr, mode, xcp_cfg);</div><div class='add'>+</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	xcp_cfg-&gt;mode = mode;</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute xcp_cfg_sysfs_mode =</div><div class='add'>+	__ATTR_RW_MODE(xcp_config, 0644);</div><div class='add'>+</div><div class='add'>+static void xcp_cfg_sysfs_release(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);</div><div class='add'>+</div><div class='add'>+	kfree(xcp_cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kobj_type xcp_cfg_sysfs_ktype = {</div><div class='add'>+	.release = xcp_cfg_sysfs_release,</div><div class='add'>+	.sysfs_ops = &amp;kobj_sysfs_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute supp_part_sysfs_mode =</div><div class='add'>+	__ATTR_RO(supported_xcp_configs);</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute supp_nps_sysfs_mode =</div><div class='add'>+	__ATTR_RO(supported_nps_configs);</div><div class='add'>+</div><div class='add'>+static const struct attribute *xcp_attrs[] = {</div><div class='add'>+	&amp;supp_part_sysfs_mode.attr,</div><div class='add'>+	&amp;xcp_cfg_sysfs_mode.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_res_details *xcp_res;</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg;</div><div class='add'>+	int i, r, j, rid, mode;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;xcp_mgr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xcp_cfg = kzalloc(sizeof(*xcp_cfg), GFP_KERNEL);</div><div class='add'>+	if (!xcp_cfg)</div><div class='add'>+		return;</div><div class='add'>+	xcp_cfg-&gt;xcp_mgr = adev-&gt;xcp_mgr;</div><div class='add'>+</div><div class='add'>+	r = kobject_init_and_add(&amp;xcp_cfg-&gt;kobj, &amp;xcp_cfg_sysfs_ktype,</div><div class='add'>+				 &amp;adev-&gt;dev-&gt;kobj, "compute_partition_config");</div><div class='add'>+	if (r)</div><div class='add'>+		goto err1;</div><div class='add'>+</div><div class='add'>+	r = sysfs_create_files(&amp;xcp_cfg-&gt;kobj, xcp_attrs);</div><div class='add'>+	if (r)</div><div class='add'>+		goto err1;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.supported_nps_modes != 0) {</div><div class='add'>+		r = sysfs_create_file(&amp;xcp_cfg-&gt;kobj, &amp;supp_nps_sysfs_mode.attr);</div><div class='add'>+		if (r) {</div><div class='add'>+			sysfs_remove_files(&amp;xcp_cfg-&gt;kobj, xcp_attrs);</div><div class='add'>+			goto err1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode = (xcp_cfg-&gt;xcp_mgr-&gt;mode ==</div><div class='add'>+		AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) ?</div><div class='add'>+		       AMDGPU_SPX_PARTITION_MODE :</div><div class='add'>+		       xcp_cfg-&gt;xcp_mgr-&gt;mode;</div><div class='add'>+	r = amdgpu_xcp_get_res_info(xcp_cfg-&gt;xcp_mgr, mode, xcp_cfg);</div><div class='add'>+	if (r) {</div><div class='add'>+		sysfs_remove_file(&amp;xcp_cfg-&gt;kobj, &amp;supp_nps_sysfs_mode.attr);</div><div class='add'>+		sysfs_remove_files(&amp;xcp_cfg-&gt;kobj, xcp_attrs);</div><div class='add'>+		goto err1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xcp_cfg-&gt;mode = mode;</div><div class='add'>+	for (i = 0; i &lt; xcp_cfg-&gt;num_res; i++) {</div><div class='add'>+		xcp_res = &amp;xcp_cfg-&gt;xcp_res[i];</div><div class='add'>+		rid = xcp_res-&gt;id;</div><div class='add'>+		r = kobject_init_and_add(&amp;xcp_res-&gt;kobj,</div><div class='add'>+					 &amp;xcp_cfg_res_sysfs_ktype,</div><div class='add'>+					 &amp;xcp_cfg-&gt;kobj, "%s",</div><div class='add'>+					 xcp_res_names[rid]);</div><div class='add'>+		if (r)</div><div class='add'>+			goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;xcp_mgr-&gt;xcp_cfg = xcp_cfg;</div><div class='add'>+	return;</div><div class='add'>+err:</div><div class='add'>+	for (j = 0; j &lt; i; j++) {</div><div class='add'>+		xcp_res = &amp;xcp_cfg-&gt;xcp_res[i];</div><div class='add'>+		kobject_put(&amp;xcp_res-&gt;kobj);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sysfs_remove_file(&amp;xcp_cfg-&gt;kobj, &amp;supp_nps_sysfs_mode.attr);</div><div class='add'>+	sysfs_remove_files(&amp;xcp_cfg-&gt;kobj, xcp_attrs);</div><div class='add'>+err1:</div><div class='add'>+	kobject_put(&amp;xcp_cfg-&gt;kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp_res_details *xcp_res;</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;xcp_mgr || !adev-&gt;xcp_mgr-&gt;xcp_cfg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xcp_cfg = adev-&gt;xcp_mgr-&gt;xcp_cfg;</div><div class='add'>+	for (i = 0; i &lt; xcp_cfg-&gt;num_res; i++) {</div><div class='add'>+		xcp_res = &amp;xcp_cfg-&gt;xcp_res[i];</div><div class='add'>+		kobject_put(&amp;xcp_res-&gt;kobj);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sysfs_remove_file(&amp;xcp_cfg-&gt;kobj, &amp;supp_nps_sysfs_mode.attr);</div><div class='add'>+	sysfs_remove_files(&amp;xcp_cfg-&gt;kobj, xcp_attrs);</div><div class='add'>+	kobject_put(&amp;xcp_cfg-&gt;kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*====================== xcp sysfs - data entries ======================*/</div><div class='add'>+</div><div class='add'>+#define to_xcp(x) container_of(x, struct amdgpu_xcp, kobj)</div><div class='add'>+</div><div class='add'>+static ssize_t xcp_metrics_show(struct kobject *kobj,</div><div class='add'>+				struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp *xcp = to_xcp(kobj);</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr;</div><div class='add'>+	ssize_t size;</div><div class='add'>+</div><div class='add'>+	xcp_mgr = xcp-&gt;xcp_mgr;</div><div class='add'>+	size = amdgpu_dpm_get_xcp_metrics(xcp_mgr-&gt;adev, xcp-&gt;id, NULL);</div><div class='add'>+	if (size &lt;= 0)</div><div class='add'>+		return size;</div><div class='add'>+</div><div class='add'>+	if (size &gt; PAGE_SIZE)</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+</div><div class='add'>+	return amdgpu_dpm_get_xcp_metrics(xcp_mgr-&gt;adev, xcp-&gt;id, buf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t amdgpu_xcp_attrs_is_visible(struct kobject *kobj,</div><div class='add'>+					   struct attribute *attr, int n)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp *xcp = to_xcp(kobj);</div><div class='add'>+</div><div class='add'>+	if (!xcp || !xcp-&gt;valid)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return attr-&gt;mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute xcp_sysfs_metrics = __ATTR_RO(xcp_metrics);</div><div class='add'>+</div><div class='add'>+static struct attribute *amdgpu_xcp_attrs[] = {</div><div class='add'>+	&amp;xcp_sysfs_metrics.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct attribute_group amdgpu_xcp_attrs_group = {</div><div class='add'>+	.attrs = amdgpu_xcp_attrs,</div><div class='add'>+	.is_visible = amdgpu_xcp_attrs_is_visible</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct kobj_type xcp_sysfs_ktype = {</div><div class='add'>+	.sysfs_ops = &amp;kobj_sysfs_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void amdgpu_xcp_sysfs_entries_fini(struct amdgpu_xcp_mgr *xcp_mgr, int n)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp *xcp;</div><div class='add'>+</div><div class='add'>+	for (n--; n &gt;= 0; n--) {</div><div class='add'>+		xcp = &amp;xcp_mgr-&gt;xcp[n];</div><div class='add'>+		if (!xcp-&gt;ddev || !xcp-&gt;valid)</div><div class='add'>+			continue;</div><div class='add'>+		sysfs_remove_group(&amp;xcp-&gt;kobj, &amp;amdgpu_xcp_attrs_group);</div><div class='add'>+		kobject_put(&amp;xcp-&gt;kobj);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_xcp_sysfs_entries_init(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp *xcp;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; i++) {</div><div class='add'>+		/* Redirect all IOCTLs to the primary device */</div><div class='add'>+		xcp = &amp;xcp_mgr-&gt;xcp[i];</div><div class='add'>+		if (!xcp-&gt;ddev)</div><div class='add'>+			break;</div><div class='add'>+		r = kobject_init_and_add(&amp;xcp-&gt;kobj, &amp;xcp_sysfs_ktype,</div><div class='add'>+					 &amp;xcp-&gt;ddev-&gt;dev-&gt;kobj, "xcp");</div><div class='add'>+		if (r)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		r = sysfs_create_group(&amp;xcp-&gt;kobj, &amp;amdgpu_xcp_attrs_group);</div><div class='add'>+		if (r)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+out:</div><div class='add'>+	kobject_put(&amp;xcp-&gt;kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_xcp_sysfs_entries_update(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_xcp *xcp;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP; i++) {</div><div class='add'>+		/* Redirect all IOCTLs to the primary device */</div><div class='add'>+		xcp = &amp;xcp_mgr-&gt;xcp[i];</div><div class='add'>+		if (!xcp-&gt;ddev)</div><div class='add'>+			continue;</div><div class='add'>+		sysfs_update_group(&amp;xcp-&gt;kobj, &amp;amdgpu_xcp_attrs_group);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_xcp_sysfs_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;xcp_mgr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_xcp_cfg_sysfs_init(adev);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_xcp_sysfs_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;xcp_mgr)</div><div class='add'>+		return;</div><div class='add'>+	amdgpu_xcp_sysfs_entries_fini(adev-&gt;xcp_mgr, MAX_XCP);</div><div class='add'>+	amdgpu_xcp_cfg_sysfs_fini(adev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h<br/>index 90138bc5f03d..1928d9e224fc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h</a></div><div class='hunk'>@@ -39,6 +39,8 @@</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_XCP_NO_PARTITION (~0)</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_XCP_OPS_KFD	(1 &lt;&lt; 0)</div><div class='add'>+</div><div class='ctx'> struct amdgpu_fpriv;</div><div class='ctx'> </div><div class='ctx'> enum AMDGPU_XCP_IP_BLOCK {</div><div class='hunk'>@@ -56,6 +58,30 @@ enum AMDGPU_XCP_STATE {</div><div class='ctx'> 	AMDGPU_XCP_RESUME,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum amdgpu_xcp_res_id {</div><div class='add'>+	AMDGPU_XCP_RES_XCC,</div><div class='add'>+	AMDGPU_XCP_RES_DMA,</div><div class='add'>+	AMDGPU_XCP_RES_DEC,</div><div class='add'>+	AMDGPU_XCP_RES_JPEG,</div><div class='add'>+	AMDGPU_XCP_RES_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_xcp_res_details {</div><div class='add'>+	enum amdgpu_xcp_res_id id;</div><div class='add'>+	u8 num_inst;</div><div class='add'>+	u8 num_shared;</div><div class='add'>+	struct kobject kobj;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_xcp_cfg {</div><div class='add'>+	u8 mode;</div><div class='add'>+	struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX];</div><div class='add'>+	u8 num_res;</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr;</div><div class='add'>+	struct kobject kobj;</div><div class='add'>+	u16 compatible_nps_modes;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_xcp_ip_funcs {</div><div class='ctx'> 	int (*prepare_suspend)(void *handle, uint32_t inst_mask);</div><div class='ctx'> 	int (*suspend)(void *handle, uint32_t inst_mask);</div><div class='hunk'>@@ -84,6 +110,9 @@ struct amdgpu_xcp {</div><div class='ctx'> 	struct drm_driver *driver;</div><div class='ctx'> 	struct drm_vma_offset_manager *vma_offset_manager;</div><div class='ctx'> 	struct amdgpu_sched	gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];</div><div class='add'>+	struct amdgpu_xcp_mgr *xcp_mgr;</div><div class='add'>+	struct kobject kobj;</div><div class='add'>+	uint64_t unique_id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_xcp_mgr {</div><div class='hunk'>@@ -97,6 +126,9 @@ struct amdgpu_xcp_mgr {</div><div class='ctx'> </div><div class='ctx'> 	 /* Used to determine KFD memory size limits per XCP */</div><div class='ctx'> 	unsigned int num_xcp_per_mem_partition;</div><div class='add'>+	struct amdgpu_xcp_cfg *xcp_cfg;</div><div class='add'>+	uint32_t supp_xcp_modes;</div><div class='add'>+	uint32_t avail_xcp_modes;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_xcp_mgr_funcs {</div><div class='hunk'>@@ -108,15 +140,13 @@ struct amdgpu_xcp_mgr_funcs {</div><div class='ctx'> 			      struct amdgpu_xcp_ip *ip);</div><div class='ctx'> 	int (*get_xcp_mem_id)(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 			      struct amdgpu_xcp *xcp, uint8_t *mem_id);</div><div class='del'>-</div><div class='add'>+	int (*get_xcp_res_info)(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='add'>+				int mode,</div><div class='add'>+				struct amdgpu_xcp_cfg *xcp_cfg);</div><div class='ctx'> 	int (*prepare_suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);</div><div class='ctx'> 	int (*suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);</div><div class='ctx'> 	int (*prepare_resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);</div><div class='ctx'> 	int (*resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);</div><div class='del'>-	int (*select_scheds)(struct amdgpu_device *adev,</div><div class='del'>-				  u32 hw_ip, u32 hw_prio, struct amdgpu_fpriv *fpriv,</div><div class='del'>-				  unsigned int *num_scheds, struct drm_gpu_scheduler ***scheds);</div><div class='del'>-	int (*update_partition_sched_list)(struct amdgpu_device *adev);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_xcp_prepare_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);</div><div class='hunk'>@@ -145,15 +175,17 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,</div><div class='ctx'> 			   struct drm_file *file_priv);</div><div class='ctx'> void amdgpu_xcp_release_sched(struct amdgpu_device *adev,</div><div class='ctx'> 			      struct amdgpu_ctx_entity *entity);</div><div class='del'>-</div><div class='del'>-#define amdgpu_xcp_select_scheds(adev, e, c, d, x, y) \</div><div class='del'>-	((adev)-&gt;xcp_mgr &amp;&amp; (adev)-&gt;xcp_mgr-&gt;funcs &amp;&amp; \</div><div class='del'>-	(adev)-&gt;xcp_mgr-&gt;funcs-&gt;select_scheds ? \</div><div class='del'>-	(adev)-&gt;xcp_mgr-&gt;funcs-&gt;select_scheds((adev), (e), (c), (d), (x), (y)) : -ENOENT)</div><div class='del'>-#define amdgpu_xcp_update_partition_sched_list(adev) \</div><div class='del'>-	((adev)-&gt;xcp_mgr &amp;&amp; (adev)-&gt;xcp_mgr-&gt;funcs &amp;&amp; \</div><div class='del'>-	(adev)-&gt;xcp_mgr-&gt;funcs-&gt;update_partition_sched_list ? \</div><div class='del'>-	(adev)-&gt;xcp_mgr-&gt;funcs-&gt;update_partition_sched_list(adev) : 0)</div><div class='add'>+int amdgpu_xcp_select_scheds(struct amdgpu_device *adev,</div><div class='add'>+			     u32 hw_ip, u32 hw_prio,</div><div class='add'>+			     struct amdgpu_fpriv *fpriv,</div><div class='add'>+			     unsigned int *num_scheds,</div><div class='add'>+			     struct drm_gpu_scheduler ***scheds);</div><div class='add'>+void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr);</div><div class='add'>+int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_xcp_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags);</div><div class='add'>+int amdgpu_xcp_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags);</div><div class='add'>+void amdgpu_xcp_sysfs_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_xcp_sysfs_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> static inline int amdgpu_xcp_get_num_xcp(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='ctx'> {</div><div class='hunk'>@@ -180,6 +212,6 @@ amdgpu_get_next_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int *from)</div><div class='ctx'> </div><div class='ctx'> #define for_each_xcp(xcp_mgr, xcp, i)                            \</div><div class='ctx'> 	for (i = 0, xcp = amdgpu_get_next_xcp(xcp_mgr, &amp;i); xcp; \</div><div class='del'>-	     xcp = amdgpu_get_next_xcp(xcp_mgr, &amp;i))</div><div class='add'>+	     ++i, xcp = amdgpu_get_next_xcp(xcp_mgr, &amp;i))</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c<br/>index 20d51f6c9bb8..aad530c46a9f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c</a></div><div class='hunk'>@@ -40,6 +40,11 @@</div><div class='ctx'> #define smnPCS_GOPX1_PCS_ERROR_STATUS    0x12200210</div><div class='ctx'> #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK      0x12200218</div><div class='ctx'> </div><div class='add'>+#define XGMI_STATE_DISABLE                      0xD1</div><div class='add'>+#define XGMI_STATE_LS0                          0x81</div><div class='add'>+#define XGMI_LINK_ACTIVE			1</div><div class='add'>+#define XGMI_LINK_INACTIVE			0</div><div class='add'>+</div><div class='ctx'> static DEFINE_MUTEX(xgmi_mutex);</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE		4</div><div class='hunk'>@@ -289,6 +294,82 @@ static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = {</div><div class='ctx'> 	 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+int amdgpu_xgmi_get_ext_link(struct amdgpu_device *adev, int link_num)</div><div class='add'>+{</div><div class='add'>+	int link_map_6_4_x[8] = { 0, 3, 1, 2, 7, 6, 4, 5 };</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.xgmi.num_physical_nodes &lt;= 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='add'>+		if (link_num &lt; ARRAY_SIZE(link_map_6_4_x))</div><div class='add'>+			return link_map_6_4_x[link_num];</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link_num)</div><div class='add'>+{</div><div class='add'>+	const u32 smn_xgmi_6_4_pcs_state_hist1[2] = { 0x11a00070, 0x11b00070 };</div><div class='add'>+	const u32 smn_xgmi_6_4_1_pcs_state_hist1[2] = { 0x12100070,</div><div class='add'>+							0x11b00070 };</div><div class='add'>+	u32 i, n;</div><div class='add'>+	u64 addr;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 4, 0):</div><div class='add'>+		n = ARRAY_SIZE(smn_xgmi_6_4_pcs_state_hist1);</div><div class='add'>+		addr = smn_xgmi_6_4_pcs_state_hist1[global_link_num % n];</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='add'>+		n = ARRAY_SIZE(smn_xgmi_6_4_1_pcs_state_hist1);</div><div class='add'>+		addr = smn_xgmi_6_4_1_pcs_state_hist1[global_link_num % n];</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return U32_MAX;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	i = global_link_num / n;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;aid_mask &amp; BIT(i)))</div><div class='add'>+		return U32_MAX;</div><div class='add'>+</div><div class='add'>+	addr += adev-&gt;asic_funcs-&gt;encode_ext_smn_addressing(i);</div><div class='add'>+</div><div class='add'>+	return RREG32_PCIE_EXT(addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num)</div><div class='add'>+{</div><div class='add'>+	u32 xgmi_state_reg_val;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.xgmi.num_physical_nodes &lt;= 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='add'>+		xgmi_state_reg_val = xgmi_v6_4_get_link_status(adev, global_link_num);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((xgmi_state_reg_val &amp; 0xFF) == XGMI_STATE_DISABLE)</div><div class='add'>+		return -ENOLINK;</div><div class='add'>+</div><div class='add'>+	if ((xgmi_state_reg_val &amp; 0xFF) == XGMI_STATE_LS0)</div><div class='add'>+		return XGMI_LINK_ACTIVE;</div><div class='add'>+</div><div class='add'>+	return XGMI_LINK_INACTIVE;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: AMDGPU XGMI Support</div><div class='ctx'>  *</div><div class='hunk'>@@ -434,6 +515,9 @@ static ssize_t amdgpu_xgmi_show_connected_port_num(struct device *dev,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (i == top-&gt;num_nodes)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; top-&gt;num_nodes; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; top-&gt;nodes[i].num_links; j++)</div><div class='ctx'> 			/* node id in sysfs starts from 1 rather than 0 so +1 here */</div><div class='hunk'>@@ -664,6 +748,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)</div><div class='ctx'> 	task_barrier_init(&amp;hive-&gt;tb);</div><div class='ctx'> 	hive-&gt;pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;</div><div class='ctx'> 	hive-&gt;hi_req_gpu = NULL;</div><div class='add'>+	atomic_set(&amp;hive-&gt;requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * hive pstate on boot is high in vega20 so we have to go to low</div><div class='hunk'>@@ -773,28 +858,88 @@ int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_dev</div><div class='ctx'>  * num_hops[2:0] = number of hops</div><div class='ctx'>  */</div><div class='ctx'> int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,</div><div class='del'>-		struct amdgpu_device *peer_adev)</div><div class='add'>+			       struct amdgpu_device *peer_adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct psp_xgmi_topology_info *top = &amp;adev-&gt;psp.xgmi_context.top_info;</div><div class='ctx'> 	uint8_t num_hops_mask = 0x7;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if (!adev-&gt;gmc.xgmi.supported)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0 ; i &lt; top-&gt;num_nodes; ++i)</div><div class='ctx'> 		if (top-&gt;nodes[i].node_id == peer_adev-&gt;gmc.xgmi.node_id)</div><div class='ctx'> 			return top-&gt;nodes[i].num_hops &amp; num_hops_mask;</div><div class='del'>-	return	-EINVAL;</div><div class='add'>+</div><div class='add'>+	dev_err(adev-&gt;dev, "Failed to get xgmi hops count for peer %d.\n",</div><div class='add'>+		peer_adev-&gt;gmc.xgmi.physical_node_id);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,</div><div class='del'>-		struct amdgpu_device *peer_adev)</div><div class='add'>+int amdgpu_xgmi_get_bandwidth(struct amdgpu_device *adev, struct amdgpu_device *peer_adev,</div><div class='add'>+			      enum amdgpu_xgmi_bw_mode bw_mode, enum amdgpu_xgmi_bw_unit bw_unit,</div><div class='add'>+			      uint32_t *min_bw, uint32_t *max_bw)</div><div class='add'>+{</div><div class='add'>+	bool peer_mode = bw_mode == AMDGPU_XGMI_BW_MODE_PER_PEER;</div><div class='add'>+	int unit_scale = bw_unit == AMDGPU_XGMI_BW_UNIT_MBYTES ? 1000 : 1;</div><div class='add'>+	int num_lanes = adev-&gt;gmc.xgmi.max_width;</div><div class='add'>+	int speed = adev-&gt;gmc.xgmi.max_speed;</div><div class='add'>+	int num_links = !peer_mode ? 1 : -1;</div><div class='add'>+</div><div class='add'>+	if (!(min_bw &amp;&amp; max_bw))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*min_bw = 0;</div><div class='add'>+	*max_bw = 0;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gmc.xgmi.supported)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	if (peer_mode &amp;&amp; !peer_adev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (peer_mode) {</div><div class='add'>+		struct psp_xgmi_topology_info *top = &amp;adev-&gt;psp.xgmi_context.top_info;</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0 ; i &lt; top-&gt;num_nodes; ++i) {</div><div class='add'>+			if (top-&gt;nodes[i].node_id != peer_adev-&gt;gmc.xgmi.node_id)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			num_links =  top-&gt;nodes[i].num_links;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (num_links == -1) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to get number of xgmi links for peer %d.\n",</div><div class='add'>+			peer_adev-&gt;gmc.xgmi.physical_node_id);</div><div class='add'>+	} else if (num_links) {</div><div class='add'>+		int per_link_bw = (speed * num_lanes * unit_scale)/BITS_PER_BYTE;</div><div class='add'>+</div><div class='add'>+		*min_bw = per_link_bw;</div><div class='add'>+		*max_bw = num_links * per_link_bw;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_device *peer_adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct psp_xgmi_topology_info *top = &amp;adev-&gt;psp.xgmi_context.top_info;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	/* Sharing should always be enabled for non-SRIOV. */</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0 ; i &lt; top-&gt;num_nodes; ++i)</div><div class='ctx'> 		if (top-&gt;nodes[i].node_id == peer_adev-&gt;gmc.xgmi.node_id)</div><div class='del'>-			return top-&gt;nodes[i].num_links;</div><div class='del'>-	return	-EINVAL;</div><div class='add'>+			return !!top-&gt;nodes[i].is_sharing_enabled;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -823,28 +968,6 @@ static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_inf</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_xgmi_fill_topology_info(struct amdgpu_device *adev,</div><div class='del'>-	struct amdgpu_device *peer_adev)</div><div class='del'>-{</div><div class='del'>-	struct psp_xgmi_topology_info *top_info = &amp;adev-&gt;psp.xgmi_context.top_info;</div><div class='del'>-	struct psp_xgmi_topology_info *peer_info = &amp;peer_adev-&gt;psp.xgmi_context.top_info;</div><div class='del'>-</div><div class='del'>-	for (int i = 0; i &lt; peer_info-&gt;num_nodes; i++) {</div><div class='del'>-		if (peer_info-&gt;nodes[i].node_id == adev-&gt;gmc.xgmi.node_id) {</div><div class='del'>-			for (int j = 0; j &lt; top_info-&gt;num_nodes; j++) {</div><div class='del'>-				if (top_info-&gt;nodes[j].node_id == peer_adev-&gt;gmc.xgmi.node_id) {</div><div class='del'>-					peer_info-&gt;nodes[i].num_hops = top_info-&gt;nodes[j].num_hops;</div><div class='del'>-					peer_info-&gt;nodes[i].is_sharing_enabled =</div><div class='del'>-							top_info-&gt;nodes[j].is_sharing_enabled;</div><div class='del'>-					peer_info-&gt;nodes[i].num_links =</div><div class='del'>-							top_info-&gt;nodes[j].num_links;</div><div class='del'>-					return;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct psp_xgmi_topology_info *top_info;</div><div class='hunk'>@@ -857,8 +980,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!adev-&gt;gmc.xgmi.supported)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;gmc.xgmi.pending_reset &amp;&amp;</div><div class='del'>-	    amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {</div><div class='add'>+	if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {</div><div class='ctx'> 		ret = psp_xgmi_initialize(&amp;adev-&gt;psp, false, true);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(adev-&gt;dev,</div><div class='hunk'>@@ -904,8 +1026,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	task_barrier_add_task(&amp;hive-&gt;tb);</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;gmc.xgmi.pending_reset &amp;&amp;</div><div class='del'>-	    amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {</div><div class='add'>+	if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {</div><div class='ctx'> 		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='ctx'> 			/* update node list for other device in the hive */</div><div class='ctx'> 			if (tmp_adev != adev) {</div><div class='hunk'>@@ -932,11 +1053,6 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> 				/* To do: continue with some node failed or disable the whole hive*/</div><div class='ctx'> 				goto exit_unlock;</div><div class='ctx'> 			}</div><div class='del'>-</div><div class='del'>-			/* fill the topology info for peers instead of getting from PSP */</div><div class='del'>-			list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='del'>-				amdgpu_xgmi_fill_topology_info(adev, tmp_adev);</div><div class='del'>-			}</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* get latest topology info for each device from psp */</div><div class='ctx'> 			list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='hunk'>@@ -982,7 +1098,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!ret &amp;&amp; !adev-&gt;gmc.xgmi.pending_reset)</div><div class='add'>+	if (!ret)</div><div class='ctx'> 		ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);</div><div class='ctx'> </div><div class='ctx'> exit_unlock:</div><div class='hunk'>@@ -1035,15 +1151,16 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int xgmi_v6_4_0_aca_bank_generate_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,</div><div class='del'>-						struct aca_bank_report *report, void *data)</div><div class='add'>+static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				       enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = handle-&gt;adev;</div><div class='add'>+	struct aca_bank_info info;</div><div class='ctx'> 	const char *error_str;</div><div class='del'>-	u64 status;</div><div class='add'>+	u64 status, count;</div><div class='ctx'> 	int ret, ext_error_code;</div><div class='ctx'> </div><div class='del'>-	ret = aca_bank_info_decode(bank, &amp;report-&gt;info);</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1055,15 +1172,30 @@ static int xgmi_v6_4_0_aca_bank_generate_report(struct aca_handle *handle, struc</div><div class='ctx'> 	if (error_str)</div><div class='ctx'> 		dev_info(adev-&gt;dev, "%s detected\n", error_str);</div><div class='ctx'> </div><div class='del'>-	if ((type == ACA_ERROR_TYPE_UE &amp;&amp; ext_error_code == 0) ||</div><div class='del'>-	    (type == ACA_ERROR_TYPE_CE &amp;&amp; ext_error_code == 6))</div><div class='del'>-		report-&gt;count[type] = ACA_REG__MISC0__ERRCNT(bank-&gt;regs[ACA_REG_IDX_MISC0]);</div><div class='add'>+	count = ACA_REG__MISC0__ERRCNT(bank-&gt;regs[ACA_REG_IDX_MISC0]);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		if (ext_error_code != 0 &amp;&amp; ext_error_code != 9)</div><div class='add'>+			count = 0ULL;</div><div class='add'>+</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE, count);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		count = ext_error_code == 6 ? count : 0ULL;</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type, count);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct aca_bank_ops xgmi_v6_4_0_aca_bank_ops = {</div><div class='del'>-	.aca_bank_generate_report = xgmi_v6_4_0_aca_bank_generate_report,</div><div class='add'>+	.aca_bank_parser = xgmi_v6_4_0_aca_bank_parser,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct aca_info xgmi_v6_4_0_aca_info = {</div><div class='hunk'>@@ -1088,6 +1220,7 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_comm</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='ctx'> 		r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL,</div><div class='ctx'> 					&amp;xgmi_v6_4_0_aca_info, NULL);</div><div class='ctx'> 		if (r)</div><div class='hunk'>@@ -1147,6 +1280,7 @@ static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++)</div><div class='ctx'> 			pcs_clear_status(adev,</div><div class='ctx'> 					xgmi3x16_pcs_err_status_reg_v6_4[i]);</div><div class='hunk'>@@ -1181,6 +1315,7 @@ static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='ctx'> 		xgmi_v6_4_0_reset_ras_error_count(adev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1206,7 +1341,9 @@ static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,</div><div class='ctx'> 		if (amdgpu_ip_version(adev, XGMI_HWIP, 0) ==</div><div class='ctx'> 		    IP_VERSION(6, 1, 0) ||</div><div class='ctx'> 		    amdgpu_ip_version(adev, XGMI_HWIP, 0) ==</div><div class='del'>-		    IP_VERSION(6, 4, 0)) {</div><div class='add'>+		    IP_VERSION(6, 4, 0) ||</div><div class='add'>+		    amdgpu_ip_version(adev, XGMI_HWIP, 0) ==</div><div class='add'>+		    IP_VERSION(6, 4, 1)) {</div><div class='ctx'> 			pcs_ras_fields = &amp;xgmi3x16_pcs_ras_fields[0];</div><div class='ctx'> 			field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -1314,6 +1451,7 @@ static void amdgpu_xgmi_legacy_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='ctx'> 		/* check xgmi3x16 pcs error */</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) {</div><div class='ctx'> 			data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]);</div><div class='hunk'>@@ -1372,10 +1510,10 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a</div><div class='ctx'> </div><div class='ctx'> 	switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) {</div><div class='ctx'> 	case ACA_ERROR_TYPE_UE:</div><div class='del'>-		amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, NULL, 1ULL);</div><div class='add'>+		amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, 1ULL);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACA_ERROR_TYPE_CE:</div><div class='del'>-		amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, NULL, 1ULL);</div><div class='add'>+		amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, 1ULL);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1410,6 +1548,7 @@ static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 4, 0):</div><div class='add'>+	case IP_VERSION(6, 4, 1):</div><div class='ctx'> 		xgmi_v6_4_0_query_ras_error_count(adev, ras_error_status);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1429,7 +1568,7 @@ static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,</div><div class='ctx'> 	if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Failed to disallow df cstate");</div><div class='ctx'> </div><div class='del'>-	ret1 = amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DISALLOW);</div><div class='add'>+	ret1 = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DISALLOW);</div><div class='ctx'> 	if (ret1 &amp;&amp; ret1 != -EOPNOTSUPP)</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Failed to disallow XGMI power down");</div><div class='ctx'> </div><div class='hunk'>@@ -1438,7 +1577,7 @@ static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,</div><div class='ctx'> 	if (amdgpu_ras_intr_triggered())</div><div class='ctx'> 		return ret2;</div><div class='ctx'> </div><div class='del'>-	ret1 = amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DEFAULT);</div><div class='add'>+	ret1 = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DEFAULT);</div><div class='ctx'> 	if (ret1 &amp;&amp; ret1 != -EOPNOTSUPP)</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Failed to allow XGMI power down");</div><div class='ctx'> </div><div class='hunk'>@@ -1483,3 +1622,157 @@ int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static void amdgpu_xgmi_reset_on_init_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_hive_info *hive =</div><div class='add'>+		container_of(work, struct amdgpu_hive_info, reset_on_init_work);</div><div class='add'>+	struct amdgpu_reset_context reset_context;</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='add'>+	struct list_head device_list;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;device_list);</div><div class='add'>+	list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head)</div><div class='add'>+		list_add_tail(&amp;tmp_adev-&gt;reset_list, &amp;device_list);</div><div class='add'>+</div><div class='add'>+	tmp_adev = list_first_entry(&amp;device_list, struct amdgpu_device,</div><div class='add'>+				    reset_list);</div><div class='add'>+	amdgpu_device_lock_reset_domain(tmp_adev-&gt;reset_domain);</div><div class='add'>+</div><div class='add'>+	reset_context.method = AMD_RESET_METHOD_ON_INIT;</div><div class='add'>+	reset_context.reset_req_dev = tmp_adev;</div><div class='add'>+	reset_context.hive = hive;</div><div class='add'>+	reset_context.reset_device_list = &amp;device_list;</div><div class='add'>+	set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='add'>+	set_bit(AMDGPU_SKIP_COREDUMP, &amp;reset_context.flags);</div><div class='add'>+</div><div class='add'>+	amdgpu_reset_do_xgmi_reset_on_init(&amp;reset_context);</div><div class='add'>+	mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+	amdgpu_device_unlock_reset_domain(tmp_adev-&gt;reset_domain);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='add'>+		r = amdgpu_ras_init_badpage_info(tmp_adev);</div><div class='add'>+		if (r &amp;&amp; r != -EHWPOISON)</div><div class='add'>+			dev_err(tmp_adev-&gt;dev,</div><div class='add'>+				"error during bad page data initialization");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_xgmi_schedule_reset_on_init(struct amdgpu_hive_info *hive)</div><div class='add'>+{</div><div class='add'>+	INIT_WORK(&amp;hive-&gt;reset_on_init_work, amdgpu_xgmi_reset_on_init_work);</div><div class='add'>+	amdgpu_reset_domain_schedule(hive-&gt;reset_domain,</div><div class='add'>+				     &amp;hive-&gt;reset_on_init_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_hive_info *hive;</div><div class='add'>+	bool reset_scheduled;</div><div class='add'>+	int num_devs;</div><div class='add'>+</div><div class='add'>+	hive = amdgpu_get_xgmi_hive(adev);</div><div class='add'>+	if (!hive)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+	num_devs = atomic_read(&amp;hive-&gt;number_devices);</div><div class='add'>+	reset_scheduled = false;</div><div class='add'>+	if (num_devs == adev-&gt;gmc.xgmi.num_physical_nodes) {</div><div class='add'>+		amdgpu_xgmi_schedule_reset_on_init(hive);</div><div class='add'>+		reset_scheduled = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+	amdgpu_put_xgmi_hive(hive);</div><div class='add'>+</div><div class='add'>+	if (reset_scheduled)</div><div class='add'>+		flush_work(&amp;hive-&gt;reset_on_init_work);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev,</div><div class='add'>+				   struct amdgpu_hive_info *hive,</div><div class='add'>+				   int req_nps_mode)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *tmp_adev;</div><div class='add'>+	int cur_nps_mode, r;</div><div class='add'>+</div><div class='add'>+	/* This is expected to be called only during unload of driver. The</div><div class='add'>+	 * request needs to be placed only once for all devices in the hive. If</div><div class='add'>+	 * one of them fail, revert the request for previous successful devices.</div><div class='add'>+	 * After placing the request, make hive mode as UNKNOWN so that other</div><div class='add'>+	 * devices don't request anymore.</div><div class='add'>+	 */</div><div class='add'>+	mutex_lock(&amp;hive-&gt;hive_lock);</div><div class='add'>+	if (atomic_read(&amp;hive-&gt;requested_nps_mode) ==</div><div class='add'>+	    UNKNOWN_MEMORY_PARTITION_MODE) {</div><div class='add'>+		dev_dbg(adev-&gt;dev, "Unexpected entry for hive NPS change");</div><div class='add'>+		mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='add'>+		r = adev-&gt;gmc.gmc_funcs-&gt;request_mem_partition_mode(</div><div class='add'>+			tmp_adev, req_nps_mode);</div><div class='add'>+		if (r)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	if (r) {</div><div class='add'>+		/* Request back current mode if one of the requests failed */</div><div class='add'>+		cur_nps_mode =</div><div class='add'>+			adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(tmp_adev);</div><div class='add'>+		list_for_each_entry_continue_reverse(</div><div class='add'>+			tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head)</div><div class='add'>+			adev-&gt;gmc.gmc_funcs-&gt;request_mem_partition_mode(</div><div class='add'>+				tmp_adev, cur_nps_mode);</div><div class='add'>+	}</div><div class='add'>+	/* Set to UNKNOWN so that other devices don't request anymore */</div><div class='add'>+	atomic_set(&amp;hive-&gt;requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE);</div><div class='add'>+	mutex_unlock(&amp;hive-&gt;hive_lock);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,</div><div class='add'>+			   struct amdgpu_device *bo_adev)</div><div class='add'>+{</div><div class='add'>+	return (amdgpu_use_xgmi_p2p &amp;&amp; adev != bo_adev &amp;&amp;</div><div class='add'>+		adev-&gt;gmc.xgmi.hive_id &amp;&amp;</div><div class='add'>+		adev-&gt;gmc.xgmi.hive_id == bo_adev-&gt;gmc.xgmi.hive_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_xgmi_early_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!adev-&gt;gmc.xgmi.supported)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(9, 4, 0):</div><div class='add'>+	case IP_VERSION(9, 4, 1):</div><div class='add'>+	case IP_VERSION(9, 4, 2):</div><div class='add'>+		/* 25 GT/s */</div><div class='add'>+		adev-&gt;gmc.xgmi.max_speed = 25;</div><div class='add'>+		adev-&gt;gmc.xgmi.max_width = 16;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='add'>+		/* 32 GT/s */</div><div class='add'>+		adev-&gt;gmc.xgmi.max_speed = 32;</div><div class='add'>+		adev-&gt;gmc.xgmi.max_width = 16;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amgpu_xgmi_set_max_speed_width(struct amdgpu_device *adev,</div><div class='add'>+				    uint16_t max_speed, uint8_t max_width)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gmc.xgmi.max_speed = max_speed;</div><div class='add'>+	adev-&gt;gmc.xgmi.max_width = max_width;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h<br/>index 1592c63b3099..5f36aff17e79 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h</a></div><div class='hunk'>@@ -23,7 +23,6 @@</div><div class='ctx'> #define __AMDGPU_XGMI_H__</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/task_barrier.h&gt;</div><div class='del'>-#include "amdgpu_psp.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_hive_info {</div><div class='hunk'>@@ -44,6 +43,9 @@ struct amdgpu_hive_info {</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_reset_domain *reset_domain;</div><div class='ctx'> 	atomic_t ras_recovery;</div><div class='add'>+	struct ras_event_manager event_mgr;</div><div class='add'>+	struct work_struct reset_on_init_work;</div><div class='add'>+	atomic_t requested_nps_mode;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_pcs_ras_field {</div><div class='hunk'>@@ -52,27 +54,80 @@ struct amdgpu_pcs_ras_field {</div><div class='ctx'> 	uint32_t pcs_err_shift;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-extern struct amdgpu_xgmi_ras  xgmi_ras;</div><div class='add'>+/**</div><div class='add'>+ * Bandwidth range reporting comes in two modes.</div><div class='add'>+ *</div><div class='add'>+ * PER_LINK - range for any xgmi link</div><div class='add'>+ * PER_PEER - range of max of single xgmi link to max of multiple links based on source peer</div><div class='add'>+ */</div><div class='add'>+enum amdgpu_xgmi_bw_mode {</div><div class='add'>+	AMDGPU_XGMI_BW_MODE_PER_LINK = 0,</div><div class='add'>+	AMDGPU_XGMI_BW_MODE_PER_PEER</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum amdgpu_xgmi_bw_unit {</div><div class='add'>+	AMDGPU_XGMI_BW_UNIT_GBYTES = 0,</div><div class='add'>+	AMDGPU_XGMI_BW_UNIT_MBYTES</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_xgmi_ras {</div><div class='add'>+	struct amdgpu_ras_block_object ras_block;</div><div class='add'>+};</div><div class='add'>+extern struct amdgpu_xgmi_ras xgmi_ras;</div><div class='add'>+</div><div class='add'>+struct amdgpu_xgmi {</div><div class='add'>+	/* from psp */</div><div class='add'>+	u64 node_id;</div><div class='add'>+	u64 hive_id;</div><div class='add'>+	/* fixed per family */</div><div class='add'>+	u64 node_segment_size;</div><div class='add'>+	/* physical node (0-3) */</div><div class='add'>+	unsigned physical_node_id;</div><div class='add'>+	/* number of nodes (0-4) */</div><div class='add'>+	unsigned num_physical_nodes;</div><div class='add'>+	/* gpu list in the same hive */</div><div class='add'>+	struct list_head head;</div><div class='add'>+	bool supported;</div><div class='add'>+	struct ras_common_if *ras_if;</div><div class='add'>+	bool connected_to_cpu;</div><div class='add'>+	struct amdgpu_xgmi_ras *ras;</div><div class='add'>+	uint16_t max_speed;</div><div class='add'>+	uint8_t max_width;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);</div><div class='ctx'> int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_xgmi_add_device(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);</div><div class='del'>-int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,</div><div class='del'>-		struct amdgpu_device *peer_adev);</div><div class='del'>-int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,</div><div class='del'>-		struct amdgpu_device *peer_adev);</div><div class='add'>+int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, struct amdgpu_device *peer_adev);</div><div class='add'>+int amdgpu_xgmi_get_bandwidth(struct amdgpu_device *adev, struct amdgpu_device *peer_adev,</div><div class='add'>+			      enum amdgpu_xgmi_bw_mode bw_mode, enum amdgpu_xgmi_bw_unit bw_unit,</div><div class='add'>+			      uint32_t *min_bw, uint32_t *max_bw);</div><div class='add'>+bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_device *peer_adev);</div><div class='ctx'> uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,</div><div class='ctx'> 					   uint64_t addr);</div><div class='del'>-static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,</div><div class='del'>-		struct amdgpu_device *bo_adev)</div><div class='del'>-{</div><div class='del'>-	return (amdgpu_use_xgmi_p2p &amp;&amp;</div><div class='del'>-		adev != bo_adev &amp;&amp;</div><div class='del'>-		adev-&gt;gmc.xgmi.hive_id &amp;&amp;</div><div class='del'>-		adev-&gt;gmc.xgmi.hive_id == bo_adev-&gt;gmc.xgmi.hive_id);</div><div class='del'>-}</div><div class='add'>+bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,</div><div class='add'>+			   struct amdgpu_device *bo_adev);</div><div class='ctx'> int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev,</div><div class='add'>+				   struct amdgpu_hive_info *hive,</div><div class='add'>+				   int req_nps_mode);</div><div class='add'>+int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev,</div><div class='add'>+				int global_link_num);</div><div class='add'>+int amdgpu_xgmi_get_ext_link(struct amdgpu_device *adev, int link_num);</div><div class='add'>+</div><div class='add'>+void amdgpu_xgmi_early_init(struct amdgpu_device *adev);</div><div class='add'>+uint32_t amdgpu_xgmi_get_max_bandwidth(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+void amgpu_xgmi_set_max_speed_width(struct amdgpu_device *adev,</div><div class='add'>+				    uint16_t max_speed, uint8_t max_width);</div><div class='add'>+</div><div class='add'>+/* Cleanup macro for use with __free(xgmi_put_hive) */</div><div class='add'>+DEFINE_FREE(xgmi_put_hive, struct amdgpu_hive_info *, if (_T) amdgpu_put_xgmi_hive(_T))</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h<br/>index 51a14f6d93bd..3cdb1e0eca37 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h</a></div><div class='hunk'>@@ -23,22 +23,84 @@</div><div class='ctx'> #ifndef AMDGV_SRIOV_MSG__H_</div><div class='ctx'> #define AMDGV_SRIOV_MSG__H_</div><div class='ctx'> </div><div class='del'>-/* unit in kilobytes */</div><div class='del'>-#define AMD_SRIOV_MSG_VBIOS_OFFSET	     0</div><div class='del'>-#define AMD_SRIOV_MSG_VBIOS_SIZE_KB	     64</div><div class='del'>-#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB</div><div class='del'>-#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB   4</div><div class='add'>+#define AMD_SRIOV_MSG_SIZE_KB                           1</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * layout</div><div class='del'>- * 0           64KB        65KB        66KB</div><div class='del'>- * |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | ...</div><div class='del'>- * |   64KB    |   1KB     |   1KB     |</div><div class='add'>+ * layout v1</div><div class='add'>+ * 0           64KB        65KB        66KB           68KB                   132KB</div><div class='add'>+ * |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | RAS Telemetry Region | ...</div><div class='add'>+ * |   64KB    |   1KB     |   1KB     |   2KB        | 64KB                 | ...</div><div class='ctx'>  */</div><div class='del'>-#define AMD_SRIOV_MSG_SIZE_KB                   1</div><div class='del'>-#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB           AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB</div><div class='del'>-#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB           (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)</div><div class='del'>-#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB        (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * layout v2 (offsets are dynamically allocated and the offsets below are examples)</div><div class='add'>+ * 0           1KB         64KB        65KB        66KB           68KB                   132KB</div><div class='add'>+ * |  INITD_H  |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | RAS Telemetry Region | ...</div><div class='add'>+ * |   1KB     |   64KB    |   1KB     |   1KB     |   2KB        | 64KB                 | ...</div><div class='add'>+ *</div><div class='add'>+ * Note: PF2VF + VF2PF + Bad Page = DataExchange region (allocated contiguously)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* v1 layout sizes */</div><div class='add'>+#define AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1			64</div><div class='add'>+#define AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1			1</div><div class='add'>+#define AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1			1</div><div class='add'>+#define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1		2</div><div class='add'>+#define AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1		64</div><div class='add'>+#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1		\</div><div class='add'>+	(AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 + AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 + \</div><div class='add'>+	 AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1)</div><div class='add'>+</div><div class='add'>+/* v1 offsets */</div><div class='add'>+#define AMD_SRIOV_MSG_VBIOS_OFFSET_V1			0</div><div class='add'>+#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1		AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1</div><div class='add'>+#define AMD_SRIOV_MSG_TMR_OFFSET_KB			2048</div><div class='add'>+#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1		AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1</div><div class='add'>+#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1		\</div><div class='add'>+	(AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB)</div><div class='add'>+#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1		\</div><div class='add'>+	(AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB)</div><div class='add'>+#define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1	\</div><div class='add'>+	(AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1)</div><div class='add'>+#define AMD_SRIOV_MSG_INIT_DATA_TOT_SIZE_KB_V1		\</div><div class='add'>+	(AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 + AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 + \</div><div class='add'>+	 AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1)</div><div class='add'>+</div><div class='add'>+enum amd_sriov_crit_region_version {</div><div class='add'>+	GPU_CRIT_REGION_V1 = 1,</div><div class='add'>+	GPU_CRIT_REGION_V2 = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* v2 layout offset enum (in order of allocation) */</div><div class='add'>+enum amd_sriov_msg_table_id_enum {</div><div class='add'>+	AMD_SRIOV_MSG_IPD_TABLE_ID = 0,</div><div class='add'>+	AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID,</div><div class='add'>+	AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID,</div><div class='add'>+	AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID,</div><div class='add'>+	AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID,</div><div class='add'>+	AMD_SRIOV_MSG_INITD_H_TABLE_ID,</div><div class='add'>+	AMD_SRIOV_MSG_MAX_TABLE_ID,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amd_sriov_msg_init_data_header {</div><div class='add'>+	char     signature[4];  /* "INDA"  */</div><div class='add'>+	uint32_t version;</div><div class='add'>+	uint32_t checksum;</div><div class='add'>+	uint32_t initdata_offset; /* 0 */</div><div class='add'>+	uint32_t initdata_size_in_kb; /* 5MB */</div><div class='add'>+	uint32_t valid_tables;</div><div class='add'>+	uint32_t vbios_img_offset;</div><div class='add'>+	uint32_t vbios_img_size_in_kb;</div><div class='add'>+	uint32_t dataexchange_offset;</div><div class='add'>+	uint32_t dataexchange_size_in_kb;</div><div class='add'>+	uint32_t ras_tele_info_offset;</div><div class='add'>+	uint32_t ras_tele_info_size_in_kb;</div><div class='add'>+	uint32_t ip_discovery_offset;</div><div class='add'>+	uint32_t ip_discovery_size_in_kb;</div><div class='add'>+	uint32_t bad_page_info_offset;</div><div class='add'>+	uint32_t bad_page_size_in_kb;</div><div class='add'>+	uint32_t reserved[8];</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * PF2VF history log:</div><div class='hunk'>@@ -86,29 +148,64 @@ enum amd_sriov_ucode_engine_id {</div><div class='ctx'> </div><div class='ctx'> union amd_sriov_msg_feature_flags {</div><div class='ctx'> 	struct {</div><div class='del'>-		uint32_t error_log_collect : 1;</div><div class='del'>-		uint32_t host_load_ucodes  : 1;</div><div class='del'>-		uint32_t host_flr_vramlost : 1;</div><div class='del'>-		uint32_t mm_bw_management  : 1;</div><div class='del'>-		uint32_t pp_one_vf_mode    : 1;</div><div class='del'>-		uint32_t reg_indirect_acc  : 1;</div><div class='del'>-		uint32_t av1_support       : 1;</div><div class='del'>-		uint32_t vcn_rb_decouple   : 1;</div><div class='del'>-		uint32_t reserved          : 24;</div><div class='add'>+		uint32_t error_log_collect	: 1;</div><div class='add'>+		uint32_t host_load_ucodes	: 1;</div><div class='add'>+		uint32_t host_flr_vramlost	: 1;</div><div class='add'>+		uint32_t mm_bw_management	: 1;</div><div class='add'>+		uint32_t pp_one_vf_mode		: 1;</div><div class='add'>+		uint32_t reg_indirect_acc	: 1;</div><div class='add'>+		uint32_t av1_support		: 1;</div><div class='add'>+		uint32_t vcn_rb_decouple	: 1;</div><div class='add'>+		uint32_t mes_info_dump_enable	: 1;</div><div class='add'>+		uint32_t ras_caps		: 1;</div><div class='add'>+		uint32_t ras_telemetry		: 1;</div><div class='add'>+		uint32_t ras_cper		: 1;</div><div class='add'>+		uint32_t xgmi_ta_ext_peer_link	: 1;</div><div class='add'>+		uint32_t reserved		: 19;</div><div class='ctx'> 	} flags;</div><div class='ctx'> 	uint32_t all;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union amd_sriov_reg_access_flags {</div><div class='ctx'> 	struct {</div><div class='del'>-		uint32_t vf_reg_access_ih 	 : 1;</div><div class='del'>-		uint32_t vf_reg_access_mmhub : 1;</div><div class='del'>-		uint32_t vf_reg_access_gc 	 : 1;</div><div class='del'>-		uint32_t reserved	         : 29;</div><div class='add'>+		uint32_t vf_reg_access_ih		: 1;</div><div class='add'>+		uint32_t vf_reg_access_mmhub		: 1;</div><div class='add'>+		uint32_t vf_reg_access_gc		: 1;</div><div class='add'>+		uint32_t vf_reg_access_l1_tlb_cntl	: 1;</div><div class='add'>+		uint32_t vf_reg_access_sq_config	: 1;</div><div class='add'>+		uint32_t reserved			: 27;</div><div class='ctx'> 	} flags;</div><div class='ctx'> 	uint32_t all;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union amd_sriov_ras_caps {</div><div class='add'>+	struct {</div><div class='add'>+		uint64_t block_umc			: 1;</div><div class='add'>+		uint64_t block_sdma			: 1;</div><div class='add'>+		uint64_t block_gfx			: 1;</div><div class='add'>+		uint64_t block_mmhub			: 1;</div><div class='add'>+		uint64_t block_athub			: 1;</div><div class='add'>+		uint64_t block_pcie_bif			: 1;</div><div class='add'>+		uint64_t block_hdp			: 1;</div><div class='add'>+		uint64_t block_xgmi_wafl		: 1;</div><div class='add'>+		uint64_t block_df			: 1;</div><div class='add'>+		uint64_t block_smn			: 1;</div><div class='add'>+		uint64_t block_sem			: 1;</div><div class='add'>+		uint64_t block_mp0			: 1;</div><div class='add'>+		uint64_t block_mp1			: 1;</div><div class='add'>+		uint64_t block_fuse			: 1;</div><div class='add'>+		uint64_t block_mca			: 1;</div><div class='add'>+		uint64_t block_vcn			: 1;</div><div class='add'>+		uint64_t block_jpeg			: 1;</div><div class='add'>+		uint64_t block_ih			: 1;</div><div class='add'>+		uint64_t block_mpio			: 1;</div><div class='add'>+		uint64_t block_mmsch			: 1;</div><div class='add'>+		uint64_t poison_propogation_mode	: 1;</div><div class='add'>+		uint64_t reserved			: 43;</div><div class='add'>+	} bits;</div><div class='add'>+	uint64_t all;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union amd_sriov_msg_os_info {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint32_t windows  : 1;</div><div class='hunk'>@@ -157,7 +254,7 @@ struct amd_sriov_msg_pf2vf_info_header {</div><div class='ctx'> 	uint32_t reserved[2];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (48)</div><div class='add'>+#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55)</div><div class='ctx'> struct amd_sriov_msg_pf2vf_info {</div><div class='ctx'> 	/* header contains size and version */</div><div class='ctx'> 	struct amd_sriov_msg_pf2vf_info_header header;</div><div class='hunk'>@@ -208,9 +305,17 @@ struct amd_sriov_msg_pf2vf_info {</div><div class='ctx'> 	struct amd_sriov_msg_uuid_info uuid_info;</div><div class='ctx'> 	/* PCIE atomic ops support flag */</div><div class='ctx'> 	uint32_t pcie_atomic_ops_support_flags;</div><div class='add'>+	/* Portion of GPU memory occupied by VF.  MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */</div><div class='add'>+	uint32_t gpu_capacity;</div><div class='add'>+	/* vf bdf on host pci tree for debug only */</div><div class='add'>+	uint32_t bdf_on_host;</div><div class='add'>+	uint32_t more_bp;	//Reserved for future use.</div><div class='add'>+	union amd_sriov_ras_caps ras_en_caps;</div><div class='add'>+	union amd_sriov_ras_caps ras_telemetry_en_caps;</div><div class='add'>+</div><div class='ctx'> 	/* reserved */</div><div class='ctx'> 	uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];</div><div class='del'>-};</div><div class='add'>+} __packed;</div><div class='ctx'> </div><div class='ctx'> struct amd_sriov_msg_vf2pf_info_header {</div><div class='ctx'> 	/* the total structure size in byte */</div><div class='hunk'>@@ -221,7 +326,7 @@ struct amd_sriov_msg_vf2pf_info_header {</div><div class='ctx'> 	uint32_t reserved[2];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (70)</div><div class='add'>+#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73)</div><div class='ctx'> struct amd_sriov_msg_vf2pf_info {</div><div class='ctx'> 	/* header contains size and version */</div><div class='ctx'> 	struct amd_sriov_msg_vf2pf_info_header header;</div><div class='hunk'>@@ -265,10 +370,12 @@ struct amd_sriov_msg_vf2pf_info {</div><div class='ctx'> 		uint32_t version;</div><div class='ctx'> 	} ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];</div><div class='ctx'> 	uint64_t dummy_page_addr;</div><div class='del'>-</div><div class='add'>+	/* FB allocated for guest MES to record UQ info */</div><div class='add'>+	uint64_t mes_info_addr;</div><div class='add'>+	uint32_t mes_info_size;</div><div class='ctx'> 	/* reserved */</div><div class='ctx'> 	uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];</div><div class='del'>-};</div><div class='add'>+} __packed;</div><div class='ctx'> </div><div class='ctx'> /* mailbox message send from guest to host  */</div><div class='ctx'> enum amd_sriov_mailbox_request_message {</div><div class='hunk'>@@ -278,22 +385,98 @@ enum amd_sriov_mailbox_request_message {</div><div class='ctx'> 	MB_REQ_MSG_REL_GPU_FINI_ACCESS,</div><div class='ctx'> 	MB_REQ_MSG_REQ_GPU_RESET_ACCESS,</div><div class='ctx'> 	MB_REQ_MSG_REQ_GPU_INIT_DATA,</div><div class='add'>+	MB_REQ_MSG_PSP_VF_CMD_RELAY,</div><div class='ctx'> </div><div class='ctx'> 	MB_REQ_MSG_LOG_VF_ERROR = 200,</div><div class='add'>+	MB_REQ_MSG_READY_TO_RESET = 201,</div><div class='add'>+	MB_REQ_MSG_RAS_POISON = 202,</div><div class='add'>+	MB_REQ_RAS_ERROR_COUNT = 203,</div><div class='add'>+	MB_REQ_RAS_CPER_DUMP = 204,</div><div class='add'>+	MB_REQ_RAS_BAD_PAGES = 205,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* mailbox message send from host to guest  */</div><div class='ctx'> enum amd_sriov_mailbox_response_message {</div><div class='del'>-	MB_RES_MSG_CLR_MSG_BUF = 0,</div><div class='del'>-	MB_RES_MSG_READY_TO_ACCESS_GPU = 1,</div><div class='del'>-	MB_RES_MSG_FLR_NOTIFICATION,</div><div class='del'>-	MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,</div><div class='del'>-	MB_RES_MSG_SUCCESS,</div><div class='del'>-	MB_RES_MSG_FAIL,</div><div class='del'>-	MB_RES_MSG_QUERY_ALIVE,</div><div class='del'>-	MB_RES_MSG_GPU_INIT_DATA_READY,</div><div class='del'>-</div><div class='del'>-	MB_RES_MSG_TEXT_MESSAGE = 255</div><div class='add'>+	MB_RES_MSG_CLR_MSG_BUF			= 0,</div><div class='add'>+	MB_RES_MSG_READY_TO_ACCESS_GPU		= 1,</div><div class='add'>+	MB_RES_MSG_FLR_NOTIFICATION		= 2,</div><div class='add'>+	MB_RES_MSG_FLR_NOTIFICATION_COMPLETION  = 3,</div><div class='add'>+	MB_RES_MSG_SUCCESS			= 4,</div><div class='add'>+	MB_RES_MSG_FAIL				= 5,</div><div class='add'>+	MB_RES_MSG_QUERY_ALIVE			= 6,</div><div class='add'>+	MB_RES_MSG_GPU_INIT_DATA_READY		= 7,</div><div class='add'>+	MB_RES_MSG_RAS_POISON_READY		= 8,</div><div class='add'>+	MB_RES_MSG_PF_SOFT_FLR_NOTIFICATION	= 9,</div><div class='add'>+	MB_RES_MSG_GPU_RMA			= 10,</div><div class='add'>+	MB_RES_MSG_RAS_ERROR_COUNT_READY	= 11,</div><div class='add'>+	MB_REQ_RAS_CPER_DUMP_READY		= 14,</div><div class='add'>+	MB_RES_MSG_RAS_BAD_PAGES_READY		= 15,</div><div class='add'>+	MB_RES_MSG_RAS_BAD_PAGES_NOTIFICATION	= 16,</div><div class='add'>+	MB_RES_MSG_UNRECOV_ERR_NOTIFICATION	= 17,</div><div class='add'>+	MB_RES_MSG_TEXT_MESSAGE			= 255</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum amd_sriov_ras_telemetry_gpu_block {</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_UMC		= 0,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_SDMA		= 1,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_GFX		= 2,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_MMHUB		= 3,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_ATHUB		= 4,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF	= 5,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_HDP		= 6,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL	= 7,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_DF		= 8,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_SMN		= 9,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_SEM		= 10,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_MP0		= 11,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_MP1		= 12,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_FUSE		= 13,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_MCA		= 14,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_VCN		= 15,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_JPEG		= 16,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_IH		= 17,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_MPIO		= 18,</div><div class='add'>+	RAS_TELEMETRY_GPU_BLOCK_COUNT		= 19,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amd_sriov_ras_telemetry_header {</div><div class='add'>+	uint32_t checksum;</div><div class='add'>+	uint32_t used_size;</div><div class='add'>+	uint32_t reserved[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amd_sriov_ras_telemetry_error_count {</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t ce_count;</div><div class='add'>+		uint32_t ue_count;</div><div class='add'>+		uint32_t de_count;</div><div class='add'>+		uint32_t ce_overflow_count;</div><div class='add'>+		uint32_t ue_overflow_count;</div><div class='add'>+		uint32_t de_overflow_count;</div><div class='add'>+		uint32_t reserved[6];</div><div class='add'>+	} block[RAS_TELEMETRY_GPU_BLOCK_COUNT];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amd_sriov_ras_cper_dump {</div><div class='add'>+	uint32_t more;</div><div class='add'>+	uint64_t overflow_count;</div><div class='add'>+	uint64_t count;</div><div class='add'>+	uint64_t wptr;</div><div class='add'>+	uint32_t buf[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amd_sriov_ras_chk_criti {</div><div class='add'>+	uint32_t hit;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdsriov_ras_telemetry {</div><div class='add'>+	struct amd_sriov_ras_telemetry_header header;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct amd_sriov_ras_telemetry_error_count error_count;</div><div class='add'>+		struct amd_sriov_ras_cper_dump cper_dump;</div><div class='add'>+		struct amd_sriov_ras_chk_criti chk_criti;</div><div class='add'>+	} body;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c<br/>index d6f808acfb17..f9e2edf5260b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c</a></div><div class='hunk'>@@ -29,12 +29,11 @@</div><div class='ctx'> #include "gfx_v9_4_3.h"</div><div class='ctx'> #include "gfxhub_v1_2.h"</div><div class='ctx'> #include "sdma_v4_4_2.h"</div><div class='add'>+#include "amdgpu_ip.h"</div><div class='ctx'> </div><div class='ctx'> #define XCP_INST_MASK(num_inst, xcp_id)                                        \</div><div class='ctx'> 	(num_inst ? GENMASK(num_inst - 1, 0) &lt;&lt; (xcp_id * num_inst) : 0)</div><div class='ctx'> </div><div class='del'>-#define AMDGPU_XCP_OPS_KFD	(1 &lt;&lt; 0)</div><div class='del'>-</div><div class='ctx'> void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -62,222 +61,6 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT &lt;&lt; 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,</div><div class='del'>-			     uint32_t inst_idx, struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	int xcp_id;</div><div class='del'>-	enum AMDGPU_XCP_IP_BLOCK ip_blk;</div><div class='del'>-	uint32_t inst_mask;</div><div class='del'>-</div><div class='del'>-	ring-&gt;xcp_id = AMDGPU_XCP_NO_PARTITION;</div><div class='del'>-	if (adev-&gt;xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	inst_mask = 1 &lt;&lt; inst_idx;</div><div class='del'>-</div><div class='del'>-	switch (ring-&gt;funcs-&gt;type) {</div><div class='del'>-	case AMDGPU_HW_IP_GFX:</div><div class='del'>-	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='del'>-	case AMDGPU_RING_TYPE_KIQ:</div><div class='del'>-		ip_blk = AMDGPU_XCP_GFX;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_RING_TYPE_SDMA:</div><div class='del'>-		ip_blk = AMDGPU_XCP_SDMA;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_RING_TYPE_VCN_ENC:</div><div class='del'>-	case AMDGPU_RING_TYPE_VCN_JPEG:</div><div class='del'>-		ip_blk = AMDGPU_XCP_VCN;</div><div class='del'>-		if (adev-&gt;xcp_mgr-&gt;mode == AMDGPU_CPX_PARTITION_MODE)</div><div class='del'>-			inst_mask = 1 &lt;&lt; (inst_idx * 2);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		DRM_ERROR("Not support ring type %d!", ring-&gt;funcs-&gt;type);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (xcp_id = 0; xcp_id &lt; adev-&gt;xcp_mgr-&gt;num_xcps; xcp_id++) {</div><div class='del'>-		if (adev-&gt;xcp_mgr-&gt;xcp[xcp_id].ip[ip_blk].inst_mask &amp; inst_mask) {</div><div class='del'>-			ring-&gt;xcp_id = xcp_id;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void aqua_vanjaram_xcp_gpu_sched_update(</div><div class='del'>-		struct amdgpu_device *adev,</div><div class='del'>-		struct amdgpu_ring *ring,</div><div class='del'>-		unsigned int sel_xcp_id)</div><div class='del'>-{</div><div class='del'>-	unsigned int *num_gpu_sched;</div><div class='del'>-</div><div class='del'>-	num_gpu_sched = &amp;adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id]</div><div class='del'>-			.gpu_sched[ring-&gt;funcs-&gt;type][ring-&gt;hw_prio].num_scheds;</div><div class='del'>-	adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id].gpu_sched[ring-&gt;funcs-&gt;type][ring-&gt;hw_prio]</div><div class='del'>-			.sched[(*num_gpu_sched)++] = &amp;ring-&gt;sched;</div><div class='del'>-	DRM_DEBUG("%s :[%d] gpu_sched[%d][%d] = %d", ring-&gt;name,</div><div class='del'>-			sel_xcp_id, ring-&gt;funcs-&gt;type,</div><div class='del'>-			ring-&gt;hw_prio, *num_gpu_sched);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aqua_vanjaram_xcp_sched_list_update(</div><div class='del'>-		struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_XCP; i++) {</div><div class='del'>-		atomic_set(&amp;adev-&gt;xcp_mgr-&gt;xcp[i].ref_cnt, 0);</div><div class='del'>-		memset(adev-&gt;xcp_mgr-&gt;xcp[i].gpu_sched, 0, sizeof(adev-&gt;xcp_mgr-&gt;xcp-&gt;gpu_sched));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;xcp_mgr-&gt;mode == AMDGPU_XCP_MODE_NONE)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; AMDGPU_MAX_RINGS; i++) {</div><div class='del'>-		ring = adev-&gt;rings[i];</div><div class='del'>-		if (!ring || !ring-&gt;sched.ready || ring-&gt;no_scheduler)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring-&gt;xcp_id);</div><div class='del'>-</div><div class='del'>-		/* VCN is shared by two partitions under CPX MODE */</div><div class='del'>-		if ((ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC ||</div><div class='del'>-			ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_JPEG) &amp;&amp;</div><div class='del'>-			adev-&gt;xcp_mgr-&gt;mode == AMDGPU_CPX_PARTITION_MODE)</div><div class='del'>-			aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring-&gt;xcp_id + 1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aqua_vanjaram_update_partition_sched_list(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;num_rings; i++) {</div><div class='del'>-		struct amdgpu_ring *ring = adev-&gt;rings[i];</div><div class='del'>-</div><div class='del'>-		if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE ||</div><div class='del'>-			ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_KIQ)</div><div class='del'>-			aqua_vanjaram_set_xcp_id(adev, ring-&gt;xcc_id, ring);</div><div class='del'>-		else</div><div class='del'>-			aqua_vanjaram_set_xcp_id(adev, ring-&gt;me, ring);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return aqua_vanjaram_xcp_sched_list_update(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aqua_vanjaram_select_scheds(</div><div class='del'>-		struct amdgpu_device *adev,</div><div class='del'>-		u32 hw_ip,</div><div class='del'>-		u32 hw_prio,</div><div class='del'>-		struct amdgpu_fpriv *fpriv,</div><div class='del'>-		unsigned int *num_scheds,</div><div class='del'>-		struct drm_gpu_scheduler ***scheds)</div><div class='del'>-{</div><div class='del'>-	u32 sel_xcp_id;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (fpriv-&gt;xcp_id == AMDGPU_XCP_NO_PARTITION) {</div><div class='del'>-		u32 least_ref_cnt = ~0;</div><div class='del'>-</div><div class='del'>-		fpriv-&gt;xcp_id = 0;</div><div class='del'>-		for (i = 0; i &lt; adev-&gt;xcp_mgr-&gt;num_xcps; i++) {</div><div class='del'>-			u32 total_ref_cnt;</div><div class='del'>-</div><div class='del'>-			total_ref_cnt = atomic_read(&amp;adev-&gt;xcp_mgr-&gt;xcp[i].ref_cnt);</div><div class='del'>-			if (total_ref_cnt &lt; least_ref_cnt) {</div><div class='del'>-				fpriv-&gt;xcp_id = i;</div><div class='del'>-				least_ref_cnt = total_ref_cnt;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	sel_xcp_id = fpriv-&gt;xcp_id;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds) {</div><div class='del'>-		*num_scheds = adev-&gt;xcp_mgr-&gt;xcp[fpriv-&gt;xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds;</div><div class='del'>-		*scheds = adev-&gt;xcp_mgr-&gt;xcp[fpriv-&gt;xcp_id].gpu_sched[hw_ip][hw_prio].sched;</div><div class='del'>-		atomic_inc(&amp;adev-&gt;xcp_mgr-&gt;xcp[sel_xcp_id].ref_cnt);</div><div class='del'>-		DRM_DEBUG("Selected partition #%d", sel_xcp_id);</div><div class='del'>-	} else {</div><div class='del'>-		DRM_ERROR("Failed to schedule partition #%d.", sel_xcp_id);</div><div class='del'>-		return -ENOENT;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int8_t aqua_vanjaram_logical_to_dev_inst(struct amdgpu_device *adev,</div><div class='del'>-					 enum amd_hw_ip_block_type block,</div><div class='del'>-					 int8_t inst)</div><div class='del'>-{</div><div class='del'>-	int8_t dev_inst;</div><div class='del'>-</div><div class='del'>-	switch (block) {</div><div class='del'>-	case GC_HWIP:</div><div class='del'>-	case SDMA0_HWIP:</div><div class='del'>-	/* Both JPEG and VCN as JPEG is only alias of VCN */</div><div class='del'>-	case VCN_HWIP:</div><div class='del'>-		dev_inst = adev-&gt;ip_map.dev_inst[block][inst];</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		/* For rest of the IPs, no look up required.</div><div class='del'>-		 * Assume 'logical instance == physical instance' for all configs. */</div><div class='del'>-		dev_inst = inst;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return dev_inst;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static uint32_t aqua_vanjaram_logical_to_dev_mask(struct amdgpu_device *adev,</div><div class='del'>-					 enum amd_hw_ip_block_type block,</div><div class='del'>-					 uint32_t mask)</div><div class='del'>-{</div><div class='del'>-	uint32_t dev_mask = 0;</div><div class='del'>-	int8_t log_inst, dev_inst;</div><div class='del'>-</div><div class='del'>-	while (mask) {</div><div class='del'>-		log_inst = ffs(mask) - 1;</div><div class='del'>-		dev_inst = aqua_vanjaram_logical_to_dev_inst(adev, block, log_inst);</div><div class='del'>-		dev_mask |= (1 &lt;&lt; dev_inst);</div><div class='del'>-		mask &amp;= ~(1 &lt;&lt; log_inst);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return dev_mask;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void aqua_vanjaram_populate_ip_map(struct amdgpu_device *adev,</div><div class='del'>-					  enum amd_hw_ip_block_type ip_block,</div><div class='del'>-					  uint32_t inst_mask)</div><div class='del'>-{</div><div class='del'>-	int l = 0, i;</div><div class='del'>-</div><div class='del'>-	while (inst_mask) {</div><div class='del'>-		i = ffs(inst_mask) - 1;</div><div class='del'>-		adev-&gt;ip_map.dev_inst[ip_block][l++] = i;</div><div class='del'>-		inst_mask &amp;= ~(1 &lt;&lt; i);</div><div class='del'>-	}</div><div class='del'>-	for (; l &lt; HWIP_MAX_INSTANCE; l++)</div><div class='del'>-		adev-&gt;ip_map.dev_inst[ip_block][l] = -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	u32 ip_map[][2] = {</div><div class='del'>-		{ GC_HWIP, adev-&gt;gfx.xcc_mask },</div><div class='del'>-		{ SDMA0_HWIP, adev-&gt;sdma.sdma_mask },</div><div class='del'>-		{ VCN_HWIP, adev-&gt;vcn.inst_mask },</div><div class='del'>-	};</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(ip_map); ++i)</div><div class='del'>-		aqua_vanjaram_populate_ip_map(adev, ip_map[i][0], ip_map[i][1]);</div><div class='del'>-</div><div class='del'>-	adev-&gt;ip_map.logical_to_dev_inst = aqua_vanjaram_logical_to_dev_inst;</div><div class='del'>-	adev-&gt;ip_map.logical_to_dev_mask = aqua_vanjaram_logical_to_dev_mask;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* Fixed pattern for smn addressing on different AIDs:</div><div class='ctx'>  *   bit[34]: indicate cross AID access</div><div class='ctx'>  *   bit[33:32]: indicate target AID id</div><div class='hunk'>@@ -297,13 +80,59 @@ u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id)</div><div class='ctx'> 	return ext_offset;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum amdgpu_gfx_partition</div><div class='add'>+__aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='add'>+	int num_xcc, num_xcc_per_xcp = 0, mode = 0;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(xcp_mgr-&gt;adev-&gt;gfx.xcc_mask);</div><div class='add'>+	if (adev-&gt;gfx.funcs-&gt;get_xccs_per_xcp)</div><div class='add'>+		num_xcc_per_xcp = adev-&gt;gfx.funcs-&gt;get_xccs_per_xcp(adev);</div><div class='add'>+	if ((num_xcc_per_xcp) &amp;&amp; (num_xcc % num_xcc_per_xcp == 0))</div><div class='add'>+		mode = num_xcc / num_xcc_per_xcp;</div><div class='add'>+</div><div class='add'>+	if (num_xcc_per_xcp == 1)</div><div class='add'>+		return AMDGPU_CPX_PARTITION_MODE;</div><div class='add'>+</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case 1:</div><div class='add'>+		return AMDGPU_SPX_PARTITION_MODE;</div><div class='add'>+	case 2:</div><div class='add'>+		return AMDGPU_DPX_PARTITION_MODE;</div><div class='add'>+	case 3:</div><div class='add'>+		return AMDGPU_TPX_PARTITION_MODE;</div><div class='add'>+	case 4:</div><div class='add'>+		return AMDGPU_QPX_PARTITION_MODE;</div><div class='add'>+	default:</div><div class='add'>+		return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int aqua_vanjaram_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='ctx'> {</div><div class='del'>-	enum amdgpu_gfx_partition mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;</div><div class='add'>+	enum amdgpu_gfx_partition derv_mode,</div><div class='add'>+		mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;</div><div class='ctx'> 	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;nbio.funcs-&gt;get_compute_partition_mode)</div><div class='add'>+	derv_mode = __aqua_vanjaram_calc_xcp_mode(xcp_mgr);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return derv_mode;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;nbio.funcs-&gt;get_compute_partition_mode) {</div><div class='ctx'> 		mode = adev-&gt;nbio.funcs-&gt;get_compute_partition_mode(adev);</div><div class='add'>+		if (mode != derv_mode) {</div><div class='add'>+			dev_warn(</div><div class='add'>+				adev-&gt;dev,</div><div class='add'>+				"Mismatch in compute partition mode - reported : %d derived : %d",</div><div class='add'>+				mode, derv_mode);</div><div class='add'>+			if (derv_mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)</div><div class='add'>+				amdgpu_device_bus_status_check(adev);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return mode;</div><div class='ctx'> }</div><div class='hunk'>@@ -340,38 +169,31 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x</div><div class='ctx'> 				    struct amdgpu_xcp_ip *ip)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='add'>+	int num_sdma, num_vcn, num_shared_vcn, num_xcp;</div><div class='ctx'> 	int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp;</div><div class='del'>-	int num_sdma, num_vcn;</div><div class='ctx'> </div><div class='ctx'> 	num_sdma = adev-&gt;sdma.num_instances;</div><div class='ctx'> 	num_vcn = adev-&gt;vcn.num_vcn_inst;</div><div class='add'>+	num_shared_vcn = 1;</div><div class='add'>+</div><div class='add'>+	num_xcc_xcp = adev-&gt;gfx.num_xcc_per_xcp;</div><div class='add'>+	num_xcp = NUM_XCC(adev-&gt;gfx.xcc_mask) / num_xcc_xcp;</div><div class='ctx'> </div><div class='ctx'> 	switch (xcp_mgr-&gt;mode) {</div><div class='ctx'> 	case AMDGPU_SPX_PARTITION_MODE:</div><div class='del'>-		num_sdma_xcp = num_sdma;</div><div class='del'>-		num_vcn_xcp = num_vcn;</div><div class='del'>-		break;</div><div class='ctx'> 	case AMDGPU_DPX_PARTITION_MODE:</div><div class='del'>-		num_sdma_xcp = num_sdma / 2;</div><div class='del'>-		num_vcn_xcp = num_vcn / 2;</div><div class='del'>-		break;</div><div class='ctx'> 	case AMDGPU_TPX_PARTITION_MODE:</div><div class='del'>-		num_sdma_xcp = num_sdma / 3;</div><div class='del'>-		num_vcn_xcp = num_vcn / 3;</div><div class='del'>-		break;</div><div class='ctx'> 	case AMDGPU_QPX_PARTITION_MODE:</div><div class='del'>-		num_sdma_xcp = num_sdma / 4;</div><div class='del'>-		num_vcn_xcp = num_vcn / 4;</div><div class='del'>-		break;</div><div class='ctx'> 	case AMDGPU_CPX_PARTITION_MODE:</div><div class='del'>-		num_sdma_xcp = 2;</div><div class='del'>-		num_vcn_xcp = num_vcn ? 1 : 0;</div><div class='add'>+		num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp);</div><div class='add'>+		num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	num_xcc_xcp = adev-&gt;gfx.num_xcc_per_xcp;</div><div class='add'>+	if (num_vcn &amp;&amp; num_xcp &gt; num_vcn)</div><div class='add'>+		num_shared_vcn = num_xcp / num_vcn;</div><div class='ctx'> </div><div class='ctx'> 	switch (ip_id) {</div><div class='ctx'> 	case AMDGPU_XCP_GFXHUB:</div><div class='hunk'>@@ -387,7 +209,8 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x</div><div class='ctx'> 		ip-&gt;ip_funcs = &amp;sdma_v4_4_2_xcp_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_XCP_VCN:</div><div class='del'>-		ip-&gt;inst_mask = XCP_INST_MASK(num_vcn_xcp, xcp_id);</div><div class='add'>+		ip-&gt;inst_mask =</div><div class='add'>+			XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn);</div><div class='ctx'> 		/* TODO : Assign IP funcs */</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -399,6 +222,94 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int __aqua_vanjaram_get_px_mode_info(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='add'>+					    int px_mode, int *num_xcp,</div><div class='add'>+					    uint16_t *nps_modes)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='add'>+	uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);</div><div class='add'>+</div><div class='add'>+	if (!num_xcp || !nps_modes || !(xcp_mgr-&gt;supp_xcp_modes &amp; BIT(px_mode)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (px_mode) {</div><div class='add'>+	case AMDGPU_SPX_PARTITION_MODE:</div><div class='add'>+		*num_xcp = 1;</div><div class='add'>+		*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_DPX_PARTITION_MODE:</div><div class='add'>+		*num_xcp = 2;</div><div class='add'>+		*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |</div><div class='add'>+			     BIT(AMDGPU_NPS2_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_TPX_PARTITION_MODE:</div><div class='add'>+		*num_xcp = 3;</div><div class='add'>+		*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |</div><div class='add'>+			     BIT(AMDGPU_NPS4_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_QPX_PARTITION_MODE:</div><div class='add'>+		*num_xcp = 4;</div><div class='add'>+		*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |</div><div class='add'>+			     BIT(AMDGPU_NPS4_PARTITION_MODE);</div><div class='add'>+		if (gc_ver == IP_VERSION(9, 5, 0))</div><div class='add'>+			*nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CPX_PARTITION_MODE:</div><div class='add'>+		*num_xcp = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+		*nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |</div><div class='add'>+			     BIT(AMDGPU_NPS4_PARTITION_MODE);</div><div class='add'>+		if (gc_ver == IP_VERSION(9, 5, 0))</div><div class='add'>+			*nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='add'>+					  int mode,</div><div class='add'>+					  struct amdgpu_xcp_cfg *xcp_cfg)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='add'>+	int max_res[AMDGPU_XCP_RES_MAX] = {};</div><div class='add'>+	bool res_lt_xcp;</div><div class='add'>+	int num_xcp, i, r;</div><div class='add'>+	u16 nps_modes;</div><div class='add'>+</div><div class='add'>+	if (!(xcp_mgr-&gt;supp_xcp_modes &amp; BIT(mode)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+	max_res[AMDGPU_XCP_RES_DMA] = adev-&gt;sdma.num_instances;</div><div class='add'>+	max_res[AMDGPU_XCP_RES_DEC] = adev-&gt;vcn.num_vcn_inst;</div><div class='add'>+	max_res[AMDGPU_XCP_RES_JPEG] = adev-&gt;jpeg.num_jpeg_inst;</div><div class='add'>+</div><div class='add'>+	r = __aqua_vanjaram_get_px_mode_info(xcp_mgr, mode, &amp;num_xcp, &amp;nps_modes);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	xcp_cfg-&gt;compatible_nps_modes =</div><div class='add'>+		(adev-&gt;gmc.supported_nps_modes &amp; nps_modes);</div><div class='add'>+	xcp_cfg-&gt;num_res = ARRAY_SIZE(max_res);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xcp_cfg-&gt;num_res; i++) {</div><div class='add'>+		res_lt_xcp = max_res[i] &lt; num_xcp;</div><div class='add'>+		xcp_cfg-&gt;xcp_res[i].id = i;</div><div class='add'>+		xcp_cfg-&gt;xcp_res[i].num_inst =</div><div class='add'>+			res_lt_xcp ? 1 : max_res[i] / num_xcp;</div><div class='add'>+		xcp_cfg-&gt;xcp_res[i].num_inst =</div><div class='add'>+			i == AMDGPU_XCP_RES_JPEG ?</div><div class='add'>+			xcp_cfg-&gt;xcp_res[i].num_inst *</div><div class='add'>+			adev-&gt;jpeg.num_jpeg_rings : xcp_cfg-&gt;xcp_res[i].num_inst;</div><div class='add'>+		xcp_cfg-&gt;xcp_res[i].num_shared =</div><div class='add'>+			res_lt_xcp ? num_xcp / max_res[i] : 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum amdgpu_gfx_partition</div><div class='ctx'> __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='ctx'> {</div><div class='hunk'>@@ -415,7 +326,7 @@ __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gmc.num_mem_partitions == num_xcc / 2)</div><div class='ctx'> 		return (adev-&gt;flags &amp; AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE :</div><div class='del'>-						    AMDGPU_QPX_PARTITION_MODE;</div><div class='add'>+						    AMDGPU_CPX_PARTITION_MODE;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gmc.num_mem_partitions == 2 &amp;&amp; !(adev-&gt;flags &amp; AMD_IS_APU))</div><div class='ctx'> 		return AMDGPU_DPX_PARTITION_MODE;</div><div class='hunk'>@@ -427,27 +338,31 @@ static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 					  enum amdgpu_gfx_partition mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = xcp_mgr-&gt;adev;</div><div class='del'>-	int num_xcc, num_xccs_per_xcp;</div><div class='add'>+	int num_xcc, num_xccs_per_xcp, r;</div><div class='add'>+	int num_xcp, nps_mode;</div><div class='add'>+	u16 supp_nps_modes;</div><div class='add'>+	bool comp_mode;</div><div class='add'>+</div><div class='add'>+	nps_mode = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='add'>+	r = __aqua_vanjaram_get_px_mode_info(xcp_mgr, mode, &amp;num_xcp,</div><div class='add'>+					       &amp;supp_nps_modes);</div><div class='add'>+	if (r)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='add'>+	comp_mode = !!(BIT(nps_mode) &amp; supp_nps_modes);</div><div class='ctx'> 	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='ctx'> 	switch (mode) {</div><div class='ctx'> 	case AMDGPU_SPX_PARTITION_MODE:</div><div class='del'>-		return adev-&gt;gmc.num_mem_partitions == 1 &amp;&amp; num_xcc &gt; 0;</div><div class='add'>+		return comp_mode &amp;&amp; num_xcc &gt; 0;</div><div class='ctx'> 	case AMDGPU_DPX_PARTITION_MODE:</div><div class='del'>-		return adev-&gt;gmc.num_mem_partitions != 8 &amp;&amp; (num_xcc % 4) == 0;</div><div class='add'>+		return comp_mode &amp;&amp; (num_xcc % 4) == 0;</div><div class='ctx'> 	case AMDGPU_TPX_PARTITION_MODE:</div><div class='del'>-		return (adev-&gt;gmc.num_mem_partitions == 1 ||</div><div class='del'>-			adev-&gt;gmc.num_mem_partitions == 3) &amp;&amp;</div><div class='del'>-		       ((num_xcc % 3) == 0);</div><div class='add'>+		return comp_mode &amp;&amp; ((num_xcc % 3) == 0);</div><div class='ctx'> 	case AMDGPU_QPX_PARTITION_MODE:</div><div class='ctx'> 		num_xccs_per_xcp = num_xcc / 4;</div><div class='del'>-		return (adev-&gt;gmc.num_mem_partitions == 1 ||</div><div class='del'>-			adev-&gt;gmc.num_mem_partitions == 4) &amp;&amp;</div><div class='del'>-		       (num_xccs_per_xcp &gt;= 2);</div><div class='add'>+		return comp_mode &amp;&amp; (num_xccs_per_xcp &gt;= 2);</div><div class='ctx'> 	case AMDGPU_CPX_PARTITION_MODE:</div><div class='del'>-		return ((num_xcc &gt; 1) &amp;&amp;</div><div class='del'>-		       (adev-&gt;gmc.num_mem_partitions == 1 || adev-&gt;gmc.num_mem_partitions == 4) &amp;&amp;</div><div class='del'>-		       (num_xcc % adev-&gt;gmc.num_mem_partitions) == 0);</div><div class='add'>+		return comp_mode &amp;&amp; (num_xcc &gt; 1);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -455,31 +370,16 @@ static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __aqua_vanjaram_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)</div><div class='add'>+static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)</div><div class='ctx'> {</div><div class='del'>-	/* TODO:</div><div class='del'>-	 * Stop user queues and threads, and make sure GPU is empty of work.</div><div class='del'>-	 */</div><div class='add'>+	int mode;</div><div class='ctx'> </div><div class='del'>-	if (flags &amp; AMDGPU_XCP_OPS_KFD)</div><div class='del'>-		amdgpu_amdkfd_device_fini_sw(xcp_mgr-&gt;adev);</div><div class='add'>+	xcp_mgr-&gt;avail_xcp_modes = 0;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)</div><div class='del'>-{</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	if (flags &amp; AMDGPU_XCP_OPS_KFD) {</div><div class='del'>-		amdgpu_amdkfd_device_probe(xcp_mgr-&gt;adev);</div><div class='del'>-		amdgpu_amdkfd_device_init(xcp_mgr-&gt;adev);</div><div class='del'>-		/* If KFD init failed, return failure */</div><div class='del'>-		if (!xcp_mgr-&gt;adev-&gt;kfd.init_complete)</div><div class='del'>-			ret = -EIO;</div><div class='add'>+	for_each_inst(mode, xcp_mgr-&gt;supp_xcp_modes) {</div><div class='add'>+		if (__aqua_vanjaram_is_valid_mode(xcp_mgr, mode))</div><div class='add'>+			xcp_mgr-&gt;avail_xcp_modes |= BIT(mode);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='hunk'>@@ -494,6 +394,12 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> </div><div class='ctx'> 	if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) {</div><div class='ctx'> 		mode = __aqua_vanjaram_get_auto_mode(xcp_mgr);</div><div class='add'>+		if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) {</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Invalid config, no compatible compute partition mode found, available memory partitions: %d",</div><div class='add'>+				adev-&gt;gmc.num_mem_partitions);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 	} else if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) {</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='ctx'> 			"Invalid compute partition mode requested, requested: %s, available memory partitions: %d",</div><div class='hunk'>@@ -501,7 +407,8 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;kfd.init_complete &amp;&amp; !amdgpu_in_reset(adev))</div><div class='add'>+	if (adev-&gt;kfd.init_complete &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp;</div><div class='add'>+		!adev-&gt;in_suspend)</div><div class='ctx'> 		flags |= AMDGPU_XCP_OPS_KFD;</div><div class='ctx'> </div><div class='ctx'> 	if (flags &amp; AMDGPU_XCP_OPS_KFD) {</div><div class='hunk'>@@ -510,7 +417,7 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = __aqua_vanjaram_pre_partition_switch(xcp_mgr, flags);</div><div class='add'>+	ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -523,7 +430,9 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,</div><div class='ctx'> 	*num_xcps = num_xcc / num_xcc_per_xcp;</div><div class='ctx'> 	amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);</div><div class='ctx'> </div><div class='del'>-	ret = __aqua_vanjaram_post_partition_switch(xcp_mgr, flags);</div><div class='add'>+	ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags);</div><div class='add'>+	if (!ret)</div><div class='add'>+		__aqua_vanjaram_update_available_partition_mode(xcp_mgr);</div><div class='ctx'> unlock:</div><div class='ctx'> 	if (flags &amp; AMDGPU_XCP_OPS_KFD)</div><div class='ctx'> 		amdgpu_amdkfd_unlock_kfd(adev);</div><div class='hunk'>@@ -602,20 +511,23 @@ struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = {</div><div class='ctx'> 	.switch_partition_mode = &amp;aqua_vanjaram_switch_partition_mode,</div><div class='ctx'> 	.query_partition_mode = &amp;aqua_vanjaram_query_partition_mode,</div><div class='ctx'> 	.get_ip_details = &amp;aqua_vanjaram_get_xcp_ip_details,</div><div class='add'>+	.get_xcp_res_info = &amp;aqua_vanjaram_get_xcp_res_info,</div><div class='ctx'> 	.get_xcp_mem_id = &amp;aqua_vanjaram_get_xcp_mem_id,</div><div class='del'>-	.select_scheds = &amp;aqua_vanjaram_select_scheds,</div><div class='del'>-	.update_partition_sched_list = &amp;aqua_vanjaram_update_partition_sched_list</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		aqua_vanjaram_xcp_funcs.switch_partition_mode = NULL;</div><div class='add'>+</div><div class='ctx'> 	ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 1,</div><div class='ctx'> 				  &amp;aqua_vanjaram_xcp_funcs);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	amdgpu_xcp_update_supported_modes(adev-&gt;xcp_mgr);</div><div class='ctx'> 	/* TODO: Default memory node affinity init */</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -623,7 +535,7 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	u32 mask, inst_mask = adev-&gt;sdma.sdma_mask;</div><div class='add'>+	u32 mask, avail_inst, inst_mask = adev-&gt;sdma.sdma_mask;</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	/* generally 1 AID supports 4 instances */</div><div class='hunk'>@@ -635,7 +547,9 @@ int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (mask = (1 &lt;&lt; adev-&gt;sdma.num_inst_per_aid) - 1; inst_mask;</div><div class='ctx'> 	     inst_mask &gt;&gt;= adev-&gt;sdma.num_inst_per_aid, ++i) {</div><div class='del'>-		if ((inst_mask &amp; mask) == mask)</div><div class='add'>+		avail_inst = inst_mask &amp; mask;</div><div class='add'>+		if (avail_inst == mask || avail_inst == 0x3 ||</div><div class='add'>+		    avail_inst == 0xc)</div><div class='ctx'> 			adev-&gt;aid_mask |= (1 &lt;&lt; i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -653,7 +567,7 @@ int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	aqua_vanjaram_ip_map_init(adev);</div><div class='add'>+	amdgpu_ip_map_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c<br/>index 72362df352f6..7a063e44d429 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atom.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atom.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atom.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/atom.c</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/string_helpers.h&gt;</div><div class='ctx'> </div><div class='del'>-#include &lt;asm/unaligned.h&gt;</div><div class='add'>+#include &lt;linux/unaligned.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_util.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -301,7 +301,7 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,</div><div class='ctx'> 			(*ptr) += 4;</div><div class='ctx'> 			if (print)</div><div class='ctx'> 				DEBUG("IMM 0x%08X\n", val);</div><div class='del'>-			return val;</div><div class='add'>+			break;</div><div class='ctx'> 		case ATOM_SRC_WORD0:</div><div class='ctx'> 		case ATOM_SRC_WORD8:</div><div class='ctx'> 		case ATOM_SRC_WORD16:</div><div class='hunk'>@@ -309,7 +309,7 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,</div><div class='ctx'> 			(*ptr) += 2;</div><div class='ctx'> 			if (print)</div><div class='ctx'> 				DEBUG("IMM 0x%04X\n", val);</div><div class='del'>-			return val;</div><div class='add'>+			break;</div><div class='ctx'> 		case ATOM_SRC_BYTE0:</div><div class='ctx'> 		case ATOM_SRC_BYTE8:</div><div class='ctx'> 		case ATOM_SRC_BYTE16:</div><div class='hunk'>@@ -318,9 +318,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,</div><div class='ctx'> 			(*ptr)++;</div><div class='ctx'> 			if (print)</div><div class='ctx'> 				DEBUG("IMM 0x%02X\n", val);</div><div class='del'>-			return val;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='del'>-		break;</div><div class='add'>+		return val;</div><div class='ctx'> 	case ATOM_ARG_PLL:</div><div class='ctx'> 		idx = U8(*ptr);</div><div class='ctx'> 		(*ptr)++;</div><div class='hunk'>@@ -1243,8 +1243,13 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index,</div><div class='ctx'> 	ectx.ps_size = params_size;</div><div class='ctx'> 	ectx.abort = false;</div><div class='ctx'> 	ectx.last_jump = 0;</div><div class='add'>+	ectx.last_jump_jiffies = 0;</div><div class='ctx'> 	if (ws) {</div><div class='ctx'> 		ectx.ws = kcalloc(4, ws, GFP_KERNEL);</div><div class='add'>+		if (!ectx.ws) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto free;</div><div class='add'>+		}</div><div class='ctx'> 		ectx.ws_size = ws;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ectx.ws = NULL;</div><div class='hunk'>@@ -1443,6 +1448,7 @@ static void atom_get_vbios_pn(struct atom_context *ctx)</div><div class='ctx'> 		if (vbios_str == NULL)</div><div class='ctx'> 			vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1;</div><div class='ctx'> 	}</div><div class='add'>+	OPTIMIZER_HIDE_VAR(vbios_str);</div><div class='ctx'> 	if (vbios_str != NULL &amp;&amp; *vbios_str == 0)</div><div class='ctx'> 		vbios_str++;</div><div class='ctx'> </div><div class='hunk'>@@ -1492,6 +1498,28 @@ static void atom_get_vbios_version(struct atom_context *ctx)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void atom_get_vbios_build(struct atom_context *ctx)</div><div class='add'>+{</div><div class='add'>+	unsigned char *atom_rom_hdr;</div><div class='add'>+	unsigned char *str;</div><div class='add'>+	uint16_t base, len;</div><div class='add'>+</div><div class='add'>+	base = CU16(ATOM_ROM_TABLE_PTR);</div><div class='add'>+	atom_rom_hdr = CSTR(base);</div><div class='add'>+</div><div class='add'>+	str = CSTR(CU16(base + ATOM_ROM_CFG_PTR));</div><div class='add'>+	/* Skip config string */</div><div class='add'>+	while (str &lt; atom_rom_hdr &amp;&amp; *str++)</div><div class='add'>+		;</div><div class='add'>+	/* Skip change list string */</div><div class='add'>+	while (str &lt; atom_rom_hdr &amp;&amp; *str++)</div><div class='add'>+		;</div><div class='add'>+</div><div class='add'>+	len = min(atom_rom_hdr - str, STRLEN_NORMAL);</div><div class='add'>+	if (len)</div><div class='add'>+		strscpy(ctx-&gt;build_num, str, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)</div><div class='ctx'> {</div><div class='ctx'> 	int base;</div><div class='hunk'>@@ -1552,6 +1580,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)</div><div class='ctx'> 	atom_get_vbios_pn(ctx);</div><div class='ctx'> 	atom_get_vbios_date(ctx);</div><div class='ctx'> 	atom_get_vbios_version(ctx);</div><div class='add'>+	atom_get_vbios_build(ctx);</div><div class='ctx'> </div><div class='ctx'> 	return ctx;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h<br/>index b807f6639a4c..825ff28731f5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atom.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atom.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atom.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/atom.h</a></div><div class='hunk'>@@ -37,6 +37,7 @@ struct drm_device;</div><div class='ctx'> #define ATOM_ROM_MAGIC		"ATOM"</div><div class='ctx'> #define ATOM_ROM_MAGIC_PTR	4</div><div class='ctx'> </div><div class='add'>+#define ATOM_ROM_CFG_PTR 0xC</div><div class='ctx'> #define ATOM_ROM_MSG_PTR	0x10</div><div class='ctx'> #define ATOM_ROM_CMD_PTR	0x1E</div><div class='ctx'> #define ATOM_ROM_DATA_PTR	0x20</div><div class='hunk'>@@ -151,6 +152,7 @@ struct atom_context {</div><div class='ctx'> 	uint32_t version;</div><div class='ctx'> 	uint8_t vbios_ver_str[STRLEN_NORMAL];</div><div class='ctx'> 	uint8_t date[STRLEN_NORMAL];</div><div class='add'>+	uint8_t build_num[STRLEN_NORMAL];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern int amdgpu_atom_debug;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c<br/>index 622634c08c7b..492813ab1b54 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_dp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atombios_dp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_dp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/atombios_dp.c</a></div><div class='hunk'>@@ -430,7 +430,7 @@ void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,</div><div class='del'>-				  struct drm_display_mode *mode)</div><div class='add'>+				  const struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='ctx'> 	struct amdgpu_connector_atom_dig *dig_connector;</div><div class='hunk'>@@ -458,8 +458,8 @@ bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connect</div><div class='ctx'> 	u8 link_status[DP_LINK_STATUS_SIZE];</div><div class='ctx'> 	struct amdgpu_connector_atom_dig *dig = amdgpu_connector-&gt;con_priv;</div><div class='ctx'> </div><div class='del'>-	if (drm_dp_dpcd_read_link_status(&amp;amdgpu_connector-&gt;ddc_bus-&gt;aux, link_status)</div><div class='del'>-	    &lt;= 0)</div><div class='add'>+	if (drm_dp_dpcd_read_link_status(&amp;amdgpu_connector-&gt;ddc_bus-&gt;aux,</div><div class='add'>+					 link_status) &lt; 0)</div><div class='ctx'> 		return false;</div><div class='ctx'> 	if (drm_dp_channel_eq_ok(link_status, dig-&gt;dp_lane_count))</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -616,7 +616,7 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i</div><div class='ctx'> 		drm_dp_link_train_clock_recovery_delay(dp_info-&gt;aux, dp_info-&gt;dpcd);</div><div class='ctx'> </div><div class='ctx'> 		if (drm_dp_dpcd_read_link_status(dp_info-&gt;aux,</div><div class='del'>-						 dp_info-&gt;link_status) &lt;= 0) {</div><div class='add'>+						 dp_info-&gt;link_status) &lt; 0) {</div><div class='ctx'> 			DRM_ERROR("displayport link status failed\n");</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -681,7 +681,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i</div><div class='ctx'> 		drm_dp_link_train_channel_eq_delay(dp_info-&gt;aux, dp_info-&gt;dpcd);</div><div class='ctx'> </div><div class='ctx'> 		if (drm_dp_dpcd_read_link_status(dp_info-&gt;aux,</div><div class='del'>-						 dp_info-&gt;link_status) &lt;= 0) {</div><div class='add'>+						 dp_info-&gt;link_status) &lt; 0) {</div><div class='ctx'> 			DRM_ERROR("displayport link status failed\n");</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.h b/drivers/gpu/drm/amd/amdgpu/atombios_dp.h<br/>index f59d85eaddf0..3e24acf8133f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_dp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atombios_dp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_dp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/atombios_dp.h</a></div><div class='hunk'>@@ -32,7 +32,7 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,</div><div class='ctx'> void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,</div><div class='ctx'> 				 const struct drm_display_mode *mode);</div><div class='ctx'> int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,</div><div class='del'>-				  struct drm_display_mode *mode);</div><div class='add'>+				  const struct drm_display_mode *mode);</div><div class='ctx'> bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector);</div><div class='ctx'> void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,</div><div class='ctx'> 				    u8 power_state);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c<br/>index 25feab188dfe..a51f3414b65d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/atombios_encoders.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/atombios_encoders.c</a></div><div class='hunk'>@@ -215,7 +215,7 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode</div><div class='ctx'> 	dig-&gt;bl_dev = bd;</div><div class='ctx'> </div><div class='ctx'> 	bd-&gt;props.brightness = amdgpu_atombios_encoder_get_backlight_brightness(bd);</div><div class='del'>-	bd-&gt;props.power = FB_BLANK_UNBLANK;</div><div class='add'>+	bd-&gt;props.power = BACKLIGHT_POWER_ON;</div><div class='ctx'> 	backlight_update_status(bd);</div><div class='ctx'> </div><div class='ctx'> 	DRM_INFO("amdgpu atom DIG backlight initialized\n");</div><div class='hunk'>@@ -2064,27 +2064,25 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)</div><div class='ctx'> 				case LCD_FAKE_EDID_PATCH_RECORD_TYPE:</div><div class='ctx'> 					fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;</div><div class='ctx'> 					if (fake_edid_record-&gt;ucFakeEDIDLength) {</div><div class='del'>-						struct edid *edid;</div><div class='del'>-						int edid_size =</div><div class='del'>-							max((int)EDID_LENGTH, (int)fake_edid_record-&gt;ucFakeEDIDLength);</div><div class='del'>-						edid = kmalloc(edid_size, GFP_KERNEL);</div><div class='del'>-						if (edid) {</div><div class='del'>-							memcpy((u8 *)edid, (u8 *)&amp;fake_edid_record-&gt;ucFakeEDIDString[0],</div><div class='del'>-							       fake_edid_record-&gt;ucFakeEDIDLength);</div><div class='del'>-</div><div class='del'>-							if (drm_edid_is_valid(edid)) {</div><div class='del'>-								adev-&gt;mode_info.bios_hardcoded_edid = edid;</div><div class='del'>-								adev-&gt;mode_info.bios_hardcoded_edid_size = edid_size;</div><div class='del'>-							} else</div><div class='del'>-								kfree(edid);</div><div class='del'>-						}</div><div class='add'>+						const struct drm_edid *edid;</div><div class='add'>+						int edid_size;</div><div class='add'>+</div><div class='add'>+						if (fake_edid_record-&gt;ucFakeEDIDLength == 128)</div><div class='add'>+							edid_size = fake_edid_record-&gt;ucFakeEDIDLength;</div><div class='add'>+						else</div><div class='add'>+							edid_size = fake_edid_record-&gt;ucFakeEDIDLength * 128;</div><div class='add'>+						edid = drm_edid_alloc(fake_edid_record-&gt;ucFakeEDIDString, edid_size);</div><div class='add'>+						if (drm_edid_valid(edid))</div><div class='add'>+							adev-&gt;mode_info.bios_hardcoded_edid = edid;</div><div class='add'>+						else</div><div class='add'>+							drm_edid_free(edid);</div><div class='add'>+						record += struct_size(fake_edid_record,</div><div class='add'>+								      ucFakeEDIDString,</div><div class='add'>+								      edid_size);</div><div class='add'>+					} else {</div><div class='add'>+						/* empty fake edid record must be 3 bytes long */</div><div class='add'>+						record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;</div><div class='ctx'> 					}</div><div class='del'>-					record += fake_edid_record-&gt;ucFakeEDIDLength ?</div><div class='del'>-						  struct_size(fake_edid_record,</div><div class='del'>-							      ucFakeEDIDString,</div><div class='del'>-							      fake_edid_record-&gt;ucFakeEDIDLength) :</div><div class='del'>-						  /* empty fake edid record must be 3 bytes long */</div><div class='del'>-						  sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;</div><div class='ctx'> 					break;</div><div class='ctx'> 				case LCD_PANEL_RESOLUTION_RECORD_TYPE:</div><div class='ctx'> 					panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c<br/>index a3a643254d7a..9cd63b4177bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cik.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cik.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cik.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/cik.c</a></div><div class='hunk'>@@ -1375,14 +1375,14 @@ static int cik_asic_pci_config_reset(struct amdgpu_device *adev)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool cik_asic_supports_baco(struct amdgpu_device *adev)</div><div class='add'>+static int cik_asic_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> 	case CHIP_BONAIRE:</div><div class='ctx'> 	case CHIP_HAWAII:</div><div class='ctx'> 		return amdgpu_dpm_is_baco_supported(adev);</div><div class='ctx'> 	default:</div><div class='del'>-		return false;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1985,9 +1985,9 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =</div><div class='ctx'> 	.query_video_codecs = &amp;cik_query_video_codecs,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int cik_common_early_init(void *handle)</div><div class='add'>+static int cik_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;smc_rreg = &amp;cik_smc_rreg;</div><div class='ctx'> 	adev-&gt;smc_wreg = &amp;cik_smc_wreg;</div><div class='hunk'>@@ -2124,19 +2124,9 @@ static int cik_common_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_common_sw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int cik_common_sw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int cik_common_hw_init(void *handle)</div><div class='add'>+static int cik_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* move the golden regs per IP block */</div><div class='ctx'> 	cik_init_golden_registers(adev);</div><div class='hunk'>@@ -2148,48 +2138,36 @@ static int cik_common_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_common_hw_fini(void *handle)</div><div class='add'>+static int cik_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_common_suspend(void *handle)</div><div class='add'>+static int cik_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cik_common_hw_fini(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int cik_common_resume(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cik_common_hw_init(adev);</div><div class='add'>+	return cik_common_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool cik_common_is_idle(void *handle)</div><div class='add'>+static bool cik_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_common_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='ctx'> </div><div class='del'>-static int cik_common_soft_reset(void *handle)</div><div class='add'>+</div><div class='add'>+static int cik_common_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* XXX hard reset?? */</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_common_set_clockgating_state(void *handle,</div><div class='add'>+static int cik_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_common_set_powergating_state(void *handle,</div><div class='add'>+static int cik_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2198,15 +2176,10 @@ static int cik_common_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs cik_common_ip_funcs = {</div><div class='ctx'> 	.name = "cik_common",</div><div class='ctx'> 	.early_init = cik_common_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='del'>-	.sw_init = cik_common_sw_init,</div><div class='del'>-	.sw_fini = cik_common_sw_fini,</div><div class='ctx'> 	.hw_init = cik_common_hw_init,</div><div class='ctx'> 	.hw_fini = cik_common_hw_fini,</div><div class='del'>-	.suspend = cik_common_suspend,</div><div class='ctx'> 	.resume = cik_common_resume,</div><div class='ctx'> 	.is_idle = cik_common_is_idle,</div><div class='del'>-	.wait_for_idle = cik_common_wait_for_idle,</div><div class='ctx'> 	.soft_reset = cik_common_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = cik_common_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = cik_common_set_powergating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c<br/>index f24e34dc33d1..876a3256dba4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cik_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cik_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cik_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/cik_ih.c</a></div><div class='hunk'>@@ -156,6 +156,9 @@ static int cik_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* enable irqs */</div><div class='ctx'> 	cik_ih_enable_interrupts(adev);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;irq.ih_soft.ring_size)</div><div class='add'>+		adev-&gt;irq.ih_soft.enabled = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -192,6 +195,9 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	wptr = le32_to_cpu(*ih-&gt;wptr_cpu);</div><div class='ctx'> </div><div class='add'>+	if (ih == &amp;adev-&gt;irq.ih_soft)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	if (wptr &amp; IH_RB_WPTR__RB_OVERFLOW_MASK) {</div><div class='ctx'> 		wptr &amp;= ~IH_RB_WPTR__RB_OVERFLOW_MASK;</div><div class='ctx'> 		/* When a ring buffer overflow happen start parsing interrupt</div><div class='hunk'>@@ -211,6 +217,8 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> 		tmp &amp;= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;</div><div class='ctx'> 		WREG32(mmIH_RB_CNTL, tmp);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='ctx'> 	return (wptr &amp; ih-&gt;ptr_mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -283,9 +291,9 @@ static void cik_ih_set_rptr(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32(mmIH_RB_RPTR, ih-&gt;rptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_early_init(void *handle)</div><div class='add'>+static int cik_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_irq_add_domain(adev);</div><div class='hunk'>@@ -297,23 +305,27 @@ static int cik_ih_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_sw_init(void *handle)</div><div class='add'>+static int cik_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 64 * 1024, false);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih_soft, IH_SW_RING_SIZE, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_irq_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_sw_fini(void *handle)</div><div class='add'>+static int cik_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> 	amdgpu_irq_remove_domain(adev);</div><div class='hunk'>@@ -321,39 +333,33 @@ static int cik_ih_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_hw_init(void *handle)</div><div class='add'>+static int cik_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return cik_ih_irq_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_hw_fini(void *handle)</div><div class='add'>+static int cik_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	cik_ih_irq_disable(adev);</div><div class='add'>+	cik_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_suspend(void *handle)</div><div class='add'>+static int cik_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cik_ih_hw_fini(adev);</div><div class='add'>+	return cik_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_resume(void *handle)</div><div class='add'>+static int cik_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cik_ih_hw_init(adev);</div><div class='add'>+	return cik_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool cik_ih_is_idle(void *handle)</div><div class='add'>+static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS__IH_BUSY_MASK)</div><div class='hunk'>@@ -362,11 +368,11 @@ static bool cik_ih_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_wait_for_idle(void *handle)</div><div class='add'>+static int cik_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -378,9 +384,9 @@ static int cik_ih_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_soft_reset(void *handle)</div><div class='add'>+static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='hunk'>@@ -408,13 +414,13 @@ static int cik_ih_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int cik_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_ih_set_powergating_state(void *handle,</div><div class='add'>+static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -423,7 +429,6 @@ static int cik_ih_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs cik_ih_ip_funcs = {</div><div class='ctx'> 	.name = "cik_ih",</div><div class='ctx'> 	.early_init = cik_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = cik_ih_sw_init,</div><div class='ctx'> 	.sw_fini = cik_ih_sw_fini,</div><div class='ctx'> 	.hw_init = cik_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c<br/>index a3fccc4c1f43..9e8715b4739d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cik_sdma.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cik_sdma.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cik_sdma.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/cik_sdma.c</a></div><div class='hunk'>@@ -54,7 +54,9 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int cik_sdma_soft_reset(void *handle);</div><div class='add'>+static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block);</div><div class='add'>+</div><div class='add'>+u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");</div><div class='hunk'>@@ -67,9 +69,6 @@ MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");</div><div class='ctx'> </div><div class='del'>-u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> static void cik_sdma_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -107,7 +106,6 @@ static void cik_sdma_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> static int cik_sdma_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err = 0, i;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='hunk'>@@ -133,16 +131,20 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='ctx'> 		if (i == 0)</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sdma.bin", chip_name);</div><div class='ctx'> 		else</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sdma1.bin", chip_name);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("cik_sdma: Failed to load firmware \"%s_sdma%s.bin\"\n",</div><div class='add'>+		       chip_name, i == 0 ? "" : "1");</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='ctx'> 			amdgpu_ucode_release(&amp;adev-&gt;sdma.instance[i].fw);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -695,7 +697,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -917,9 +919,9 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_early_init(void *handle)</div><div class='add'>+static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;sdma.num_instances = SDMA_MAX_INSTANCE;</div><div class='hunk'>@@ -936,10 +938,10 @@ static int cik_sdma_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_sw_init(void *handle)</div><div class='add'>+static int cik_sdma_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r, i;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='hunk'>@@ -976,9 +978,9 @@ static int cik_sdma_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_sw_fini(void *handle)</div><div class='add'>+static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='hunk'>@@ -988,21 +990,16 @@ static int cik_sdma_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_hw_init(void *handle)</div><div class='add'>+static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	r = cik_sdma_start(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return cik_sdma_start(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_hw_fini(void *handle)</div><div class='add'>+static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cik_ctx_switch_enable(adev, false);</div><div class='ctx'> 	cik_sdma_enable(adev, false);</div><div class='hunk'>@@ -1010,25 +1007,21 @@ static int cik_sdma_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_suspend(void *handle)</div><div class='add'>+static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cik_sdma_hw_fini(adev);</div><div class='add'>+	return cik_sdma_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_resume(void *handle)</div><div class='add'>+static int cik_sdma_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	cik_sdma_soft_reset(ip_block);</div><div class='ctx'> </div><div class='del'>-	cik_sdma_soft_reset(handle);</div><div class='del'>-</div><div class='del'>-	return cik_sdma_hw_init(adev);</div><div class='add'>+	return cik_sdma_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool cik_sdma_is_idle(void *handle)</div><div class='add'>+static bool cik_sdma_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS2);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; (SRBM_STATUS2__SDMA_BUSY_MASK |</div><div class='hunk'>@@ -1038,27 +1031,23 @@ static bool cik_sdma_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_wait_for_idle(void *handle)</div><div class='add'>+static int cik_sdma_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		tmp = RREG32(mmSRBM_STATUS2) &amp; (SRBM_STATUS2__SDMA_BUSY_MASK |</div><div class='del'>-				SRBM_STATUS2__SDMA1_BUSY_MASK);</div><div class='del'>-</div><div class='del'>-		if (!tmp)</div><div class='add'>+		if (cik_sdma_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_soft_reset(void *handle)</div><div class='add'>+static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* sdma0 */</div><div class='hunk'>@@ -1192,11 +1181,11 @@ static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_set_clockgating_state(void *handle,</div><div class='add'>+static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_CG_STATE_GATE)</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -1207,7 +1196,7 @@ static int cik_sdma_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cik_sdma_set_powergating_state(void *handle,</div><div class='add'>+static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1216,7 +1205,6 @@ static int cik_sdma_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs cik_sdma_ip_funcs = {</div><div class='ctx'> 	.name = "cik_sdma",</div><div class='ctx'> 	.early_init = cik_sdma_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = cik_sdma_sw_init,</div><div class='ctx'> 	.sw_fini = cik_sdma_sw_fini,</div><div class='ctx'> 	.hw_init = cik_sdma_hw_init,</div><div class='hunk'>@@ -1290,7 +1278,7 @@ static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: is this a secure operation</div><div class='add'>+ * @copy_flags: unused</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine (CIK).</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1300,7 +1288,7 @@ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				      uint64_t src_offset,</div><div class='ctx'> 				      uint64_t dst_offset,</div><div class='ctx'> 				      uint32_t byte_count,</div><div class='del'>-				      bool tmz)</div><div class='add'>+				      uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h<br/>index 55982c0064b5..8aca4f2734f2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cikd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cikd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cikd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/cikd.h</a></div><div class='hunk'>@@ -51,8 +51,14 @@</div><div class='ctx'> #define HPD4_REGISTER_OFFSET                 (0x1813 - 0x1807)</div><div class='ctx'> #define HPD5_REGISTER_OFFSET                 (0x1816 - 0x1807)</div><div class='ctx'> </div><div class='del'>-#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001</div><div class='del'>-#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003</div><div class='add'>+/* audio endpt instance offsets */</div><div class='add'>+#define AUD0_REGISTER_OFFSET                 (0x1780 - 0x1780)</div><div class='add'>+#define AUD1_REGISTER_OFFSET                 (0x1786 - 0x1780)</div><div class='add'>+#define AUD2_REGISTER_OFFSET                 (0x178c - 0x1780)</div><div class='add'>+#define AUD3_REGISTER_OFFSET                 (0x1792 - 0x1780)</div><div class='add'>+#define AUD4_REGISTER_OFFSET                 (0x1798 - 0x1780)</div><div class='add'>+#define AUD5_REGISTER_OFFSET                 (0x179d - 0x1780)</div><div class='add'>+#define AUD6_REGISTER_OFFSET                 (0x17a4 - 0x1780)</div><div class='ctx'> </div><div class='ctx'> #define		PIPEID(x)					((x) &lt;&lt; 0)</div><div class='ctx'> #define		MEID(x)						((x) &lt;&lt; 2)</div><div class='hunk'>@@ -364,6 +370,7 @@</div><div class='ctx'> 		 * 1 - Stream</div><div class='ctx'> 		 * 2 - Bypass</div><div class='ctx'> 		 */</div><div class='add'>+#define		EOP_EXEC				(1 &lt;&lt; 28) /* For Trailing Fence */</div><div class='ctx'> #define		DATA_SEL(x)                             ((x) &lt;&lt; 29)</div><div class='ctx'> 		/* 0 - discard</div><div class='ctx'> 		 * 1 - send low 32bit data</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h<br/>new file mode 100644<br/>index 000000000000..2f6c9d11d5ae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h</a></div><div class='hunk'>@@ -0,0 +1,121 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#ifndef __CLEARSTATE_GFX12_H_</div><div class='add'>+#define __CLEARSTATE_GFX12_H_</div><div class='add'>+</div><div class='add'>+static const unsigned int gfx12_SECT_CONTEXT_def_1[] = {</div><div class='add'>+0x00000000, //mmSC_MEM_TEMPORAL</div><div class='add'>+0x00000000, //mmSC_MEM_SPEC_READ</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_0_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_0_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_1_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_1_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_2_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_2_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_3_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_3_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_4_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_4_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_5_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_5_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_6_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_6_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_7_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_7_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_8_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_8_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_9_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_9_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_10_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_10_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_11_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_11_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_12_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_12_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_13_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_13_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_14_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_14_BR</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_15_TL</div><div class='add'>+0x00000000, //mmPA_SC_VPORT_15_BR</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int gfx12_SECT_CONTEXT_def_2[] = {</div><div class='add'>+0x00000000, //mmPA_CL_PROG_NEAR_CLIP_Z</div><div class='add'>+0x00000000, //mmPA_RATE_CNTL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int gfx12_SECT_CONTEXT_def_3[] = {</div><div class='add'>+0x00000000, //mmCP_PERFMON_CNTX_CNTL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int gfx12_SECT_CONTEXT_def_4[] = {</div><div class='add'>+0x00000000, //mmCONTEXT_RESERVED_REG0</div><div class='add'>+0x00000000, //mmCONTEXT_RESERVED_REG1</div><div class='add'>+0x00000000, //mmPA_SC_CLIPRECT_0_EXT</div><div class='add'>+0x00000000, //mmPA_SC_CLIPRECT_1_EXT</div><div class='add'>+0x00000000, //mmPA_SC_CLIPRECT_2_EXT</div><div class='add'>+0x00000000, //mmPA_SC_CLIPRECT_3_EXT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int gfx12_SECT_CONTEXT_def_5[] = {</div><div class='add'>+0x00000000, //mmPA_SC_HIZ_INFO</div><div class='add'>+0x00000000, //mmPA_SC_HIS_INFO</div><div class='add'>+0x00000000, //mmPA_SC_HIZ_BASE</div><div class='add'>+0x00000000, //mmPA_SC_HIZ_BASE_EXT</div><div class='add'>+0x00000000, //mmPA_SC_HIZ_SIZE_XY</div><div class='add'>+0x00000000, //mmPA_SC_HIS_BASE</div><div class='add'>+0x00000000, //mmPA_SC_HIS_BASE_EXT</div><div class='add'>+0x00000000, //mmPA_SC_HIS_SIZE_XY</div><div class='add'>+0x00000000, //mmPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL</div><div class='add'>+0x00000000, //mmPA_SC_BINNER_DYNAMIC_BATCH_LIMIT</div><div class='add'>+0x00000000, //mmPA_SC_HISZ_CONTROL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int gfx12_SECT_CONTEXT_def_6[] = {</div><div class='add'>+0x00000000, //mmCB_MEM0_INFO</div><div class='add'>+0x00000000, //mmCB_MEM1_INFO</div><div class='add'>+0x00000000, //mmCB_MEM2_INFO</div><div class='add'>+0x00000000, //mmCB_MEM3_INFO</div><div class='add'>+0x00000000, //mmCB_MEM4_INFO</div><div class='add'>+0x00000000, //mmCB_MEM5_INFO</div><div class='add'>+0x00000000, //mmCB_MEM6_INFO</div><div class='add'>+0x00000000, //mmCB_MEM7_INFO</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cs_extent_def gfx12_SECT_CONTEXT_defs[] = {</div><div class='add'>+    {gfx12_SECT_CONTEXT_def_1, 0x0000a03e, 34 },</div><div class='add'>+    {gfx12_SECT_CONTEXT_def_2, 0x0000a0cc, 2 },</div><div class='add'>+    {gfx12_SECT_CONTEXT_def_3, 0x0000a0d8, 1 },</div><div class='add'>+    {gfx12_SECT_CONTEXT_def_4, 0x0000a0db, 6 },</div><div class='add'>+    {gfx12_SECT_CONTEXT_def_5, 0x0000a2e5, 11 },</div><div class='add'>+    {gfx12_SECT_CONTEXT_def_6, 0x0000a3c0, 8 },</div><div class='add'>+    { 0, 0, 0 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cs_section_def gfx12_cs_data[] = {</div><div class='add'>+    { gfx12_SECT_CONTEXT_defs, SECT_CONTEXT },</div><div class='add'>+    { 0, SECT_NONE }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif /* __CLEARSTATE_GFX12_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c b/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c<br/>new file mode 100644<br/>index 000000000000..ed1e25661706<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "nv.h"</div><div class='add'>+</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "soc15_hw_ip.h"</div><div class='add'>+#include "cyan_skillfish_ip_offset.h"</div><div class='add'>+</div><div class='add'>+int cyan_skillfish_reg_base_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* HW has more IP blocks,  only initialized the blocke needed by driver */</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.xcc_mask = 1;</div><div class='add'>+	for (i = 0 ; i &lt; MAX_INSTANCE ; ++i) {</div><div class='add'>+		adev-&gt;reg_offset[GC_HWIP][i] = (uint32_t *)(&amp;(GC_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[HDP_HWIP][i] = (uint32_t *)(&amp;(HDP_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&amp;(MMHUB_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&amp;(ATHUB_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[NBIO_HWIP][i] = (uint32_t *)(&amp;(NBIO_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[MP0_HWIP][i] = (uint32_t *)(&amp;(MP0_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[MP1_HWIP][i] = (uint32_t *)(&amp;(MP1_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[VCN_HWIP][i] = (uint32_t *)(&amp;(UVD0_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[DF_HWIP][i] = (uint32_t *)(&amp;(DF_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[DCE_HWIP][i] = (uint32_t *)(&amp;(DMU_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&amp;(OSSSYS_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&amp;(GC_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&amp;(GC_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&amp;(SMUIO_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[THM_HWIP][i] = (uint32_t *)(&amp;(THM_BASE.instance[i]));</div><div class='add'>+		adev-&gt;reg_offset[CLK_HWIP][i] = (uint32_t *)(&amp;(CLK_BASE.instance[i]));</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c<br/>index c19681492efa..bc7a2e06ab5f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cz_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/cz_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/cz_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/cz_ih.c</a></div><div class='hunk'>@@ -157,6 +157,9 @@ static int cz_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* enable interrupts */</div><div class='ctx'> 	cz_ih_enable_interrupts(adev);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;irq.ih_soft.ring_size)</div><div class='add'>+		adev-&gt;irq.ih_soft.enabled = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -194,6 +197,9 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	wptr = le32_to_cpu(*ih-&gt;wptr_cpu);</div><div class='ctx'> </div><div class='add'>+	if (ih == &amp;adev-&gt;irq.ih_soft)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -274,9 +280,9 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32(mmIH_RB_RPTR, ih-&gt;rptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_early_init(void *handle)</div><div class='add'>+static int cz_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_irq_add_domain(adev);</div><div class='hunk'>@@ -288,23 +294,27 @@ static int cz_ih_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_sw_init(void *handle)</div><div class='add'>+static int cz_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 64 * 1024, false);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih_soft, IH_SW_RING_SIZE, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_irq_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_sw_fini(void *handle)</div><div class='add'>+static int cz_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> 	amdgpu_irq_remove_domain(adev);</div><div class='hunk'>@@ -312,10 +322,10 @@ static int cz_ih_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_hw_init(void *handle)</div><div class='add'>+static int cz_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = cz_ih_irq_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -324,32 +334,26 @@ static int cz_ih_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_hw_fini(void *handle)</div><div class='add'>+static int cz_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	cz_ih_irq_disable(adev);</div><div class='add'>+	cz_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_suspend(void *handle)</div><div class='add'>+static int cz_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cz_ih_hw_fini(adev);</div><div class='add'>+	return cz_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_resume(void *handle)</div><div class='add'>+static int cz_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return cz_ih_hw_init(adev);</div><div class='add'>+	return cz_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool cz_ih_is_idle(void *handle)</div><div class='add'>+static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))</div><div class='hunk'>@@ -358,11 +362,11 @@ static bool cz_ih_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_wait_for_idle(void *handle)</div><div class='add'>+static int cz_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -374,10 +378,10 @@ static int cz_ih_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_soft_reset(void *handle)</div><div class='add'>+static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS__IH_BUSY_MASK)</div><div class='hunk'>@@ -404,14 +408,14 @@ static int cz_ih_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int cz_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	// TODO</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cz_ih_set_powergating_state(void *handle,</div><div class='add'>+static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	// TODO</div><div class='hunk'>@@ -421,7 +425,6 @@ static int cz_ih_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs cz_ih_ip_funcs = {</div><div class='ctx'> 	.name = "cz_ih",</div><div class='ctx'> 	.early_init = cz_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = cz_ih_sw_init,</div><div class='ctx'> 	.sw_fini = cz_ih_sw_fini,</div><div class='ctx'> 	.hw_init = cz_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c<br/>index 221af054d874..72ca6538b2e4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v10_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/dce_v10_0.c</a></div><div class='hunk'>@@ -1141,8 +1141,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	/* save values for DPM */</div><div class='ctx'> 	amdgpu_crtc-&gt;line_time = line_time;</div><div class='del'>-	amdgpu_crtc-&gt;wm_high = latency_watermark_a;</div><div class='del'>-	amdgpu_crtc-&gt;wm_low = latency_watermark_b;</div><div class='add'>+</div><div class='ctx'> 	/* Save number of lines the linebuffer leads before the scanout */</div><div class='ctx'> 	amdgpu_crtc-&gt;lb_vblank_lead_lines = lb_vblank_lead_lines;</div><div class='ctx'> }</div><div class='hunk'>@@ -1299,7 +1298,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &amp;sadb);</div><div class='add'>+	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector-&gt;edid, &amp;sadb);</div><div class='ctx'> 	if (sad_count &lt; 0) {</div><div class='ctx'> 		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);</div><div class='ctx'> 		sad_count = 0;</div><div class='hunk'>@@ -1369,7 +1368,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &amp;sads);</div><div class='add'>+	sad_count = drm_edid_to_sad(amdgpu_connector-&gt;edid, &amp;sads);</div><div class='ctx'> 	if (sad_count &lt; 0)</div><div class='ctx'> 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);</div><div class='ctx'> 	if (sad_count &lt;= 0)</div><div class='hunk'>@@ -1462,17 +1461,12 @@ static int dce_v10_0_audio_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void dce_v10_0_audio_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='ctx'> 	if (!amdgpu_audio)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mode_info.audio.enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++)</div><div class='del'>-		dce_v10_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-</div><div class='ctx'> 	adev-&gt;mode_info.audio.enabled = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1881,6 +1875,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	if (!atomic) {</div><div class='add'>+		abo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 		if (unlikely(r != 0)) {</div><div class='ctx'> 			amdgpu_bo_unreserve(abo);</div><div class='hunk'>@@ -2401,6 +2396,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	aobj-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 	ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 	amdgpu_bo_unreserve(aobj);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2685,6 +2681,32 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {</div><div class='ctx'> 	.get_scanout_position = amdgpu_crtc_get_scanout_position,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void dce_v10_0_panic_flush(struct drm_plane *plane)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	struct amdgpu_crtc *amdgpu_crtc;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	uint32_t fb_format;</div><div class='add'>+</div><div class='add'>+	if (!plane-&gt;fb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fb = plane-&gt;fb;</div><div class='add'>+	amdgpu_crtc = to_amdgpu_crtc(plane-&gt;crtc);</div><div class='add'>+	adev = drm_to_adev(fb-&gt;dev);</div><div class='add'>+</div><div class='add'>+	/* Disable DC tiling */</div><div class='add'>+	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='add'>+	fb_format &amp;= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK;</div><div class='add'>+	WREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset, fb_format);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_funcs = {</div><div class='add'>+	.get_scanout_buffer = amdgpu_display_get_scanout_buffer,</div><div class='add'>+	.panic_flush = dce_v10_0_panic_flush,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc;</div><div class='hunk'>@@ -2732,13 +2754,14 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='ctx'> 	amdgpu_crtc-&gt;encoder = NULL;</div><div class='ctx'> 	amdgpu_crtc-&gt;connector = NULL;</div><div class='ctx'> 	drm_crtc_helper_add(&amp;amdgpu_crtc-&gt;base, &amp;dce_v10_0_crtc_helper_funcs);</div><div class='add'>+	drm_plane_helper_add(amdgpu_crtc-&gt;base.primary, &amp;dce_v10_0_drm_primary_plane_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_early_init(void *handle)</div><div class='add'>+static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;audio_endpt_rreg = &amp;dce_v10_0_audio_endpt_rreg;</div><div class='ctx'> 	adev-&gt;audio_endpt_wreg = &amp;dce_v10_0_audio_endpt_wreg;</div><div class='hunk'>@@ -2763,10 +2786,10 @@ static int dce_v10_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_sw_init(void *handle)</div><div class='add'>+static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &amp;adev-&gt;crtc_irq);</div><div class='hunk'>@@ -2842,11 +2865,11 @@ static int dce_v10_0_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_sw_fini(void *handle)</div><div class='add'>+static int dce_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	kfree(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='add'>+	drm_edid_free(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='ctx'> </div><div class='ctx'> 	drm_kms_helper_poll_fini(adev_to_drm(adev));</div><div class='ctx'> </div><div class='hunk'>@@ -2860,10 +2883,10 @@ static int dce_v10_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_hw_init(void *handle)</div><div class='add'>+static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	dce_v10_0_init_golden_registers(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2885,10 +2908,10 @@ static int dce_v10_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_hw_fini(void *handle)</div><div class='add'>+static int dce_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	dce_v10_0_hpd_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2903,9 +2926,9 @@ static int dce_v10_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_suspend(void *handle)</div><div class='add'>+static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_display_suspend_helper(adev);</div><div class='hunk'>@@ -2915,18 +2938,18 @@ static int dce_v10_0_suspend(void *handle)</div><div class='ctx'> 	adev-&gt;mode_info.bl_level =</div><div class='ctx'> 		amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);</div><div class='ctx'> </div><div class='del'>-	return dce_v10_0_hw_fini(handle);</div><div class='add'>+	return dce_v10_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_resume(void *handle)</div><div class='add'>+static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,</div><div class='ctx'> 							   adev-&gt;mode_info.bl_level);</div><div class='ctx'> </div><div class='del'>-	ret = dce_v10_0_hw_init(handle);</div><div class='add'>+	ret = dce_v10_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	/* turn on the BL */</div><div class='ctx'> 	if (adev-&gt;mode_info.bl_encoder) {</div><div class='hunk'>@@ -2941,27 +2964,22 @@ static int dce_v10_0_resume(void *handle)</div><div class='ctx'> 	return amdgpu_display_resume_helper(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce_v10_0_is_idle(void *handle)</div><div class='add'>+static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dce_v10_0_check_soft_reset(void *handle)</div><div class='add'>+static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return dce_v10_0_is_display_hung(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_soft_reset(void *handle)</div><div class='add'>+static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0, tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (dce_v10_0_is_display_hung(adev))</div><div class='ctx'> 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;</div><div class='hunk'>@@ -3051,7 +3069,7 @@ static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", hpd);</div><div class='add'>+		DRM_DEBUG("invalid hpd %d\n", hpd);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3203,7 +3221,7 @@ static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", hpd);</div><div class='add'>+		DRM_DEBUG("invalid hpd %d\n", hpd);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3305,13 +3323,13 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_set_clockgating_state(void *handle,</div><div class='add'>+static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v10_0_set_powergating_state(void *handle,</div><div class='add'>+static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3320,7 +3338,6 @@ static int dce_v10_0_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs dce_v10_0_ip_funcs = {</div><div class='ctx'> 	.name = "dce_v10_0",</div><div class='ctx'> 	.early_init = dce_v10_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = dce_v10_0_sw_init,</div><div class='ctx'> 	.sw_fini = dce_v10_0_sw_fini,</div><div class='ctx'> 	.hw_init = dce_v10_0_hw_init,</div><div class='hunk'>@@ -3328,7 +3345,6 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = {</div><div class='ctx'> 	.suspend = dce_v10_0_suspend,</div><div class='ctx'> 	.resume = dce_v10_0_resume,</div><div class='ctx'> 	.is_idle = dce_v10_0_is_idle,</div><div class='del'>-	.wait_for_idle = dce_v10_0_wait_for_idle,</div><div class='ctx'> 	.check_soft_reset = dce_v10_0_check_soft_reset,</div><div class='ctx'> 	.soft_reset = dce_v10_0_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = dce_v10_0_set_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c<br/>deleted file mode 100644<br/>index 69e8b0db6cf7..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v11_0.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,3802 +0,0 @@</div><div class='del'>-/*</div><div class='del'>- * Copyright 2014 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include &lt;drm/drm_edid.h&gt;</div><div class='del'>-#include &lt;drm/drm_fourcc.h&gt;</div><div class='del'>-#include &lt;drm/drm_modeset_helper.h&gt;</div><div class='del'>-#include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='del'>-#include &lt;drm/drm_vblank.h&gt;</div><div class='del'>-</div><div class='del'>-#include "amdgpu.h"</div><div class='del'>-#include "amdgpu_pm.h"</div><div class='del'>-#include "amdgpu_i2c.h"</div><div class='del'>-#include "vid.h"</div><div class='del'>-#include "atom.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='del'>-#include "atombios_crtc.h"</div><div class='del'>-#include "atombios_encoders.h"</div><div class='del'>-#include "amdgpu_pll.h"</div><div class='del'>-#include "amdgpu_connectors.h"</div><div class='del'>-#include "amdgpu_display.h"</div><div class='del'>-#include "dce_v11_0.h"</div><div class='del'>-</div><div class='del'>-#include "dce/dce_11_0_d.h"</div><div class='del'>-#include "dce/dce_11_0_sh_mask.h"</div><div class='del'>-#include "dce/dce_11_0_enum.h"</div><div class='del'>-#include "oss/oss_3_0_d.h"</div><div class='del'>-#include "oss/oss_3_0_sh_mask.h"</div><div class='del'>-#include "gmc/gmc_8_1_d.h"</div><div class='del'>-#include "gmc/gmc_8_1_sh_mask.h"</div><div class='del'>-</div><div class='del'>-#include "ivsrcid/ivsrcid_vislands30.h"</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);</div><div class='del'>-static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);</div><div class='del'>-</div><div class='del'>-static const u32 crtc_offsets[] =</div><div class='del'>-{</div><div class='del'>-	CRTC0_REGISTER_OFFSET,</div><div class='del'>-	CRTC1_REGISTER_OFFSET,</div><div class='del'>-	CRTC2_REGISTER_OFFSET,</div><div class='del'>-	CRTC3_REGISTER_OFFSET,</div><div class='del'>-	CRTC4_REGISTER_OFFSET,</div><div class='del'>-	CRTC5_REGISTER_OFFSET,</div><div class='del'>-	CRTC6_REGISTER_OFFSET</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 hpd_offsets[] =</div><div class='del'>-{</div><div class='del'>-	HPD0_REGISTER_OFFSET,</div><div class='del'>-	HPD1_REGISTER_OFFSET,</div><div class='del'>-	HPD2_REGISTER_OFFSET,</div><div class='del'>-	HPD3_REGISTER_OFFSET,</div><div class='del'>-	HPD4_REGISTER_OFFSET,</div><div class='del'>-	HPD5_REGISTER_OFFSET</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const uint32_t dig_offsets[] = {</div><div class='del'>-	DIG0_REGISTER_OFFSET,</div><div class='del'>-	DIG1_REGISTER_OFFSET,</div><div class='del'>-	DIG2_REGISTER_OFFSET,</div><div class='del'>-	DIG3_REGISTER_OFFSET,</div><div class='del'>-	DIG4_REGISTER_OFFSET,</div><div class='del'>-	DIG5_REGISTER_OFFSET,</div><div class='del'>-	DIG6_REGISTER_OFFSET,</div><div class='del'>-	DIG7_REGISTER_OFFSET,</div><div class='del'>-	DIG8_REGISTER_OFFSET</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct {</div><div class='del'>-	uint32_t        reg;</div><div class='del'>-	uint32_t        vblank;</div><div class='del'>-	uint32_t        vline;</div><div class='del'>-	uint32_t        hpd;</div><div class='del'>-</div><div class='del'>-} interrupt_status_offsets[] = { {</div><div class='del'>-	.reg = mmDISP_INTERRUPT_STATUS,</div><div class='del'>-	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,</div><div class='del'>-	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,</div><div class='del'>-	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK</div><div class='del'>-}, {</div><div class='del'>-	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,</div><div class='del'>-	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,</div><div class='del'>-	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,</div><div class='del'>-	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK</div><div class='del'>-}, {</div><div class='del'>-	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,</div><div class='del'>-	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,</div><div class='del'>-	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,</div><div class='del'>-	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK</div><div class='del'>-}, {</div><div class='del'>-	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,</div><div class='del'>-	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,</div><div class='del'>-	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,</div><div class='del'>-	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK</div><div class='del'>-}, {</div><div class='del'>-	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,</div><div class='del'>-	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,</div><div class='del'>-	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,</div><div class='del'>-	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK</div><div class='del'>-}, {</div><div class='del'>-	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,</div><div class='del'>-	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,</div><div class='del'>-	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,</div><div class='del'>-	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK</div><div class='del'>-} };</div><div class='del'>-</div><div class='del'>-static const u32 cz_golden_settings_a11[] =</div><div class='del'>-{</div><div class='del'>-	mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,</div><div class='del'>-	mmFBC_MISC, 0x1f311fff, 0x14300000,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 cz_mgcg_cgcg_init[] =</div><div class='del'>-{</div><div class='del'>-	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,</div><div class='del'>-	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 stoney_golden_settings_a11[] =</div><div class='del'>-{</div><div class='del'>-	mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,</div><div class='del'>-	mmFBC_MISC, 0x1f311fff, 0x14302000,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 polaris11_golden_settings_a11[] =</div><div class='del'>-{</div><div class='del'>-	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,</div><div class='del'>-	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,</div><div class='del'>-	mmFBC_DEBUG1, 0xffffffff, 0x00000008,</div><div class='del'>-	mmFBC_MISC, 0x9f313fff, 0x14302008,</div><div class='del'>-	mmHDMI_CONTROL, 0x313f031f, 0x00000011,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 polaris10_golden_settings_a11[] =</div><div class='del'>-{</div><div class='del'>-	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,</div><div class='del'>-	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,</div><div class='del'>-	mmFBC_MISC, 0x9f313fff, 0x14302008,</div><div class='del'>-	mmHDMI_CONTROL, 0x313f031f, 0x00000011,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	switch (adev-&gt;asic_type) {</div><div class='del'>-	case CHIP_CARRIZO:</div><div class='del'>-		amdgpu_device_program_register_sequence(adev,</div><div class='del'>-							cz_mgcg_cgcg_init,</div><div class='del'>-							ARRAY_SIZE(cz_mgcg_cgcg_init));</div><div class='del'>-		amdgpu_device_program_register_sequence(adev,</div><div class='del'>-							cz_golden_settings_a11,</div><div class='del'>-							ARRAY_SIZE(cz_golden_settings_a11));</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_STONEY:</div><div class='del'>-		amdgpu_device_program_register_sequence(adev,</div><div class='del'>-							stoney_golden_settings_a11,</div><div class='del'>-							ARRAY_SIZE(stoney_golden_settings_a11));</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS11:</div><div class='del'>-	case CHIP_POLARIS12:</div><div class='del'>-		amdgpu_device_program_register_sequence(adev,</div><div class='del'>-							polaris11_golden_settings_a11,</div><div class='del'>-							ARRAY_SIZE(polaris11_golden_settings_a11));</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS10:</div><div class='del'>-	case CHIP_VEGAM:</div><div class='del'>-		amdgpu_device_program_register_sequence(adev,</div><div class='del'>-							polaris10_golden_settings_a11,</div><div class='del'>-							ARRAY_SIZE(polaris10_golden_settings_a11));</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,</div><div class='del'>-				     u32 block_offset, u32 reg)</div><div class='del'>-{</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	u32 r;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;adev-&gt;audio_endpt_idx_lock, flags);</div><div class='del'>-	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);</div><div class='del'>-	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);</div><div class='del'>-	spin_unlock_irqrestore(&amp;adev-&gt;audio_endpt_idx_lock, flags);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,</div><div class='del'>-				      u32 block_offset, u32 reg, u32 v)</div><div class='del'>-{</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;adev-&gt;audio_endpt_idx_lock, flags);</div><div class='del'>-	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);</div><div class='del'>-	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);</div><div class='del'>-	spin_unlock_irqrestore(&amp;adev-&gt;audio_endpt_idx_lock, flags);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)</div><div class='del'>-{</div><div class='del'>-	if (crtc &lt; 0 || crtc &gt;= adev-&gt;mode_info.num_crtc)</div><div class='del'>-		return 0;</div><div class='del'>-	else</div><div class='del'>-		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	unsigned i;</div><div class='del'>-</div><div class='del'>-	/* Enable pflip interrupts */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++)</div><div class='del'>-		amdgpu_irq_get(adev, &amp;adev-&gt;pageflip_irq, i);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	unsigned i;</div><div class='del'>-</div><div class='del'>-	/* Disable pflip interrupts */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++)</div><div class='del'>-		amdgpu_irq_put(adev, &amp;adev-&gt;pageflip_irq, i);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_page_flip - pageflip callback.</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @crtc_id: crtc to cleanup pageflip on</div><div class='del'>- * @crtc_base: new address of the crtc (GPU MC address)</div><div class='del'>- * @async: asynchronous flip</div><div class='del'>- *</div><div class='del'>- * Triggers the actual pageflip by updating the primary</div><div class='del'>- * surface base address.</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_page_flip(struct amdgpu_device *adev,</div><div class='del'>-				int crtc_id, u64 crtc_base, bool async)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = adev-&gt;mode_info.crtcs[crtc_id];</div><div class='del'>-	struct drm_framebuffer *fb = amdgpu_crtc-&gt;base.primary-&gt;fb;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	/* flip immediate for async, default is vsync */</div><div class='del'>-	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,</div><div class='del'>-			    GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);</div><div class='del'>-	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-	/* update pitch */</div><div class='del'>-	WREG32(mmGRPH_PITCH + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       fb-&gt;pitches[0] / fb-&gt;format-&gt;cpp[0]);</div><div class='del'>-	/* update the scanout addresses */</div><div class='del'>-	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       upper_32_bits(crtc_base));</div><div class='del'>-	/* writing to the low address triggers the update */</div><div class='del'>-	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       lower_32_bits(crtc_base));</div><div class='del'>-	/* post the write */</div><div class='del'>-	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,</div><div class='del'>-					u32 *vbl, u32 *position)</div><div class='del'>-{</div><div class='del'>-	if ((crtc &lt; 0) || (crtc &gt;= adev-&gt;mode_info.num_crtc))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);</div><div class='del'>-	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_hpd_sense - hpd sense callback.</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @hpd: hpd (hotplug detect) pin</div><div class='del'>- *</div><div class='del'>- * Checks if a digital monitor is connected (evergreen+).</div><div class='del'>- * Returns true if connected, false if not connected.</div><div class='del'>- */</div><div class='del'>-static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,</div><div class='del'>-			       enum amdgpu_hpd_id hpd)</div><div class='del'>-{</div><div class='del'>-	bool connected = false;</div><div class='del'>-</div><div class='del'>-	if (hpd &gt;= adev-&gt;mode_info.num_hpd)</div><div class='del'>-		return connected;</div><div class='del'>-</div><div class='del'>-	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &amp;</div><div class='del'>-	    DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)</div><div class='del'>-		connected = true;</div><div class='del'>-</div><div class='del'>-	return connected;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_hpd_set_polarity - hpd set polarity callback.</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @hpd: hpd (hotplug detect) pin</div><div class='del'>- *</div><div class='del'>- * Set the polarity of the hpd pin (evergreen+).</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,</div><div class='del'>-				      enum amdgpu_hpd_id hpd)</div><div class='del'>-{</div><div class='del'>-	u32 tmp;</div><div class='del'>-	bool connected = dce_v11_0_hpd_sense(adev, hpd);</div><div class='del'>-</div><div class='del'>-	if (hpd &gt;= adev-&gt;mode_info.num_hpd)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);</div><div class='del'>-	if (connected)</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);</div><div class='del'>-	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_hpd_init - hpd setup callback.</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='del'>- * Setup the hpd pins used by the card (evergreen+).</div><div class='del'>- * Enable the pin, set the polarity, and enable the hpd interrupts.</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_hpd_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = adev_to_drm(adev);</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_list_iter iter;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='del'>-	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-</div><div class='del'>-		if (amdgpu_connector-&gt;hpd.hpd &gt;= adev-&gt;mode_info.num_hpd)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP ||</div><div class='del'>-		    connector-&gt;connector_type == DRM_MODE_CONNECTOR_LVDS) {</div><div class='del'>-			/* don't try to enable hpd on eDP or LVDS avoid breaking the</div><div class='del'>-			 * aux dp channel on imac and help (but not completely fix)</div><div class='del'>-			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143</div><div class='del'>-			 * also avoid interrupt storms during dpms.</div><div class='del'>-			 */</div><div class='del'>-			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd]);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);</div><div class='del'>-			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd], tmp);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd]);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);</div><div class='del'>-		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd], tmp);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd]);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,</div><div class='del'>-				    DC_HPD_CONNECT_INT_DELAY,</div><div class='del'>-				    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,</div><div class='del'>-				    DC_HPD_DISCONNECT_INT_DELAY,</div><div class='del'>-				    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);</div><div class='del'>-		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd], tmp);</div><div class='del'>-</div><div class='del'>-		dce_v11_0_hpd_int_ack(adev, amdgpu_connector-&gt;hpd.hpd);</div><div class='del'>-		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector-&gt;hpd.hpd);</div><div class='del'>-		amdgpu_irq_get(adev, &amp;adev-&gt;hpd_irq, amdgpu_connector-&gt;hpd.hpd);</div><div class='del'>-	}</div><div class='del'>-	drm_connector_list_iter_end(&amp;iter);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_hpd_fini - hpd tear down callback.</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='del'>- * Tear down the hpd pins used by the card (evergreen+).</div><div class='del'>- * Disable the hpd interrupts.</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = adev_to_drm(adev);</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_list_iter iter;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='del'>-	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-</div><div class='del'>-		if (amdgpu_connector-&gt;hpd.hpd &gt;= adev-&gt;mode_info.num_hpd)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd]);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);</div><div class='del'>-		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector-&gt;hpd.hpd], tmp);</div><div class='del'>-</div><div class='del'>-		amdgpu_irq_put(adev, &amp;adev-&gt;hpd_irq, amdgpu_connector-&gt;hpd.hpd);</div><div class='del'>-	}</div><div class='del'>-	drm_connector_list_iter_end(&amp;iter);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	return mmDC_GPIO_HPD_A;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	u32 crtc_hung = 0;</div><div class='del'>-	u32 crtc_status[6];</div><div class='del'>-	u32 i, j, tmp;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);</div><div class='del'>-		if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {</div><div class='del'>-			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);</div><div class='del'>-			crtc_hung |= (1 &lt;&lt; i);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (j = 0; j &lt; 10; j++) {</div><div class='del'>-		for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-			if (crtc_hung &amp; (1 &lt;&lt; i)) {</div><div class='del'>-				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);</div><div class='del'>-				if (tmp != crtc_status[i])</div><div class='del'>-					crtc_hung &amp;= ~(1 &lt;&lt; i);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		if (crtc_hung == 0)</div><div class='del'>-			return false;</div><div class='del'>-		udelay(100);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,</div><div class='del'>-					   bool render)</div><div class='del'>-{</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	/* Lockout access through VGA aperture*/</div><div class='del'>-	tmp = RREG32(mmVGA_HDP_CONTROL);</div><div class='del'>-	if (render)</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);</div><div class='del'>-	WREG32(mmVGA_HDP_CONTROL, tmp);</div><div class='del'>-</div><div class='del'>-	/* disable VGA render */</div><div class='del'>-	tmp = RREG32(mmVGA_RENDER_CONTROL);</div><div class='del'>-	if (render)</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);</div><div class='del'>-	WREG32(mmVGA_RENDER_CONTROL, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int num_crtc = 0;</div><div class='del'>-</div><div class='del'>-	switch (adev-&gt;asic_type) {</div><div class='del'>-	case CHIP_CARRIZO:</div><div class='del'>-		num_crtc = 3;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_STONEY:</div><div class='del'>-		num_crtc = 2;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS10:</div><div class='del'>-	case CHIP_VEGAM:</div><div class='del'>-		num_crtc = 6;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS11:</div><div class='del'>-	case CHIP_POLARIS12:</div><div class='del'>-		num_crtc = 5;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		num_crtc = 0;</div><div class='del'>-	}</div><div class='del'>-	return num_crtc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dce_v11_0_disable_dce(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	/*Disable VGA render and enabled crtc, if has DCE engine*/</div><div class='del'>-	if (amdgpu_atombios_has_dce_engine_info(adev)) {</div><div class='del'>-		u32 tmp;</div><div class='del'>-		int crtc_enabled, i;</div><div class='del'>-</div><div class='del'>-		dce_v11_0_set_vga_render_state(adev, false);</div><div class='del'>-</div><div class='del'>-		/*Disable crtc*/</div><div class='del'>-		for (i = 0; i &lt; dce_v11_0_get_num_crtc(adev); i++) {</div><div class='del'>-			crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),</div><div class='del'>-									 CRTC_CONTROL, CRTC_MASTER_EN);</div><div class='del'>-			if (crtc_enabled) {</div><div class='del'>-				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);</div><div class='del'>-				tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);</div><div class='del'>-				WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);</div><div class='del'>-				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_program_fmt(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder-&gt;crtc);</div><div class='del'>-	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);</div><div class='del'>-	int bpc = 0;</div><div class='del'>-	u32 tmp = 0;</div><div class='del'>-	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;</div><div class='del'>-</div><div class='del'>-	if (connector) {</div><div class='del'>-		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-		bpc = amdgpu_connector_get_monitor_bpc(connector);</div><div class='del'>-		dither = amdgpu_connector-&gt;dither;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* LVDS/eDP FMT is set up by atom */</div><div class='del'>-	if (amdgpu_encoder-&gt;devices &amp; ATOM_DEVICE_LCD_SUPPORT)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* not needed for analog */</div><div class='del'>-	if ((amdgpu_encoder-&gt;encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||</div><div class='del'>-	    (amdgpu_encoder-&gt;encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (bpc == 0)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (bpc) {</div><div class='del'>-	case 6:</div><div class='del'>-		if (dither == AMDGPU_FMT_DITHER_ENABLE) {</div><div class='del'>-			/* XXX sort out optimal dither settings */</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);</div><div class='del'>-		} else {</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 8:</div><div class='del'>-		if (dither == AMDGPU_FMT_DITHER_ENABLE) {</div><div class='del'>-			/* XXX sort out optimal dither settings */</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);</div><div class='del'>-		} else {</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 10:</div><div class='del'>-		if (dither == AMDGPU_FMT_DITHER_ENABLE) {</div><div class='del'>-			/* XXX sort out optimal dither settings */</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);</div><div class='del'>-		} else {</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);</div><div class='del'>-			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		/* not needed */</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/* display watermark setup */</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_line_buffer_adjust - Set up the line buffer</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @amdgpu_crtc: the selected display controller</div><div class='del'>- * @mode: the current display mode on the selected display</div><div class='del'>- * controller</div><div class='del'>- *</div><div class='del'>- * Setup up the line buffer allocation for</div><div class='del'>- * the selected display controller (CIK).</div><div class='del'>- * Returns the line buffer size in pixels.</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,</div><div class='del'>-				       struct amdgpu_crtc *amdgpu_crtc,</div><div class='del'>-				       struct drm_display_mode *mode)</div><div class='del'>-{</div><div class='del'>-	u32 tmp, buffer_alloc, i, mem_cfg;</div><div class='del'>-	u32 pipe_offset = amdgpu_crtc-&gt;crtc_id;</div><div class='del'>-	/*</div><div class='del'>-	 * Line Buffer Setup</div><div class='del'>-	 * There are 6 line buffers, one for each display controllers.</div><div class='del'>-	 * There are 3 partitions per LB. Select the number of partitions</div><div class='del'>-	 * to enable based on the display width.  For display widths larger</div><div class='del'>-	 * than 4096, you need use to use 2 display controllers and combine</div><div class='del'>-	 * them using the stereo blender.</div><div class='del'>-	 */</div><div class='del'>-	if (amdgpu_crtc-&gt;base.enabled &amp;&amp; mode) {</div><div class='del'>-		if (mode-&gt;crtc_hdisplay &lt; 1920) {</div><div class='del'>-			mem_cfg = 1;</div><div class='del'>-			buffer_alloc = 2;</div><div class='del'>-		} else if (mode-&gt;crtc_hdisplay &lt; 2560) {</div><div class='del'>-			mem_cfg = 2;</div><div class='del'>-			buffer_alloc = 2;</div><div class='del'>-		} else if (mode-&gt;crtc_hdisplay &lt; 4096) {</div><div class='del'>-			mem_cfg = 0;</div><div class='del'>-			buffer_alloc = (adev-&gt;flags &amp; AMD_IS_APU) ? 2 : 4;</div><div class='del'>-		} else {</div><div class='del'>-			DRM_DEBUG_KMS("Mode too big for LB!\n");</div><div class='del'>-			mem_cfg = 0;</div><div class='del'>-			buffer_alloc = (adev-&gt;flags &amp; AMD_IS_APU) ? 2 : 4;</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		mem_cfg = 1;</div><div class='del'>-		buffer_alloc = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);</div><div class='del'>-	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);</div><div class='del'>-	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);</div><div class='del'>-		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))</div><div class='del'>-			break;</div><div class='del'>-		udelay(1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (amdgpu_crtc-&gt;base.enabled &amp;&amp; mode) {</div><div class='del'>-		switch (mem_cfg) {</div><div class='del'>-		case 0:</div><div class='del'>-		default:</div><div class='del'>-			return 4096 * 2;</div><div class='del'>-		case 1:</div><div class='del'>-			return 1920 * 2;</div><div class='del'>-		case 2:</div><div class='del'>-			return 2560 * 2;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* controller not enabled, so no lb used */</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * cik_get_number_of_dram_channels - get the number of dram channels</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='del'>- * Look up the number of video ram channels (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the number of dram channels</div><div class='del'>- */</div><div class='del'>-static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	u32 tmp = RREG32(mmMC_SHARED_CHMAP);</div><div class='del'>-</div><div class='del'>-	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {</div><div class='del'>-	case 0:</div><div class='del'>-	default:</div><div class='del'>-		return 1;</div><div class='del'>-	case 1:</div><div class='del'>-		return 2;</div><div class='del'>-	case 2:</div><div class='del'>-		return 4;</div><div class='del'>-	case 3:</div><div class='del'>-		return 8;</div><div class='del'>-	case 4:</div><div class='del'>-		return 3;</div><div class='del'>-	case 5:</div><div class='del'>-		return 6;</div><div class='del'>-	case 6:</div><div class='del'>-		return 10;</div><div class='del'>-	case 7:</div><div class='del'>-		return 12;</div><div class='del'>-	case 8:</div><div class='del'>-		return 16;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct dce10_wm_params {</div><div class='del'>-	u32 dram_channels; /* number of dram channels */</div><div class='del'>-	u32 yclk;          /* bandwidth per dram data pin in kHz */</div><div class='del'>-	u32 sclk;          /* engine clock in kHz */</div><div class='del'>-	u32 disp_clk;      /* display clock in kHz */</div><div class='del'>-	u32 src_width;     /* viewport width */</div><div class='del'>-	u32 active_time;   /* active display time in ns */</div><div class='del'>-	u32 blank_time;    /* blank time in ns */</div><div class='del'>-	bool interlaced;    /* mode is interlaced */</div><div class='del'>-	fixed20_12 vsc;    /* vertical scale ratio */</div><div class='del'>-	u32 num_heads;     /* number of active crtcs */</div><div class='del'>-	u32 bytes_per_pixel; /* bytes per pixel display + overlay */</div><div class='del'>-	u32 lb_size;       /* line buffer allocated to pipe */</div><div class='del'>-	u32 vtaps;         /* vertical scaler taps */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_dram_bandwidth - get the dram bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the raw dram bandwidth (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the dram bandwidth in MBytes/s</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* Calculate raw DRAM Bandwidth */</div><div class='del'>-	fixed20_12 dram_efficiency; /* 0.7 */</div><div class='del'>-	fixed20_12 yclk, dram_channels, bandwidth;</div><div class='del'>-	fixed20_12 a;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(1000);</div><div class='del'>-	yclk.full = dfixed_const(wm-&gt;yclk);</div><div class='del'>-	yclk.full = dfixed_div(yclk, a);</div><div class='del'>-	dram_channels.full = dfixed_const(wm-&gt;dram_channels * 4);</div><div class='del'>-	a.full = dfixed_const(10);</div><div class='del'>-	dram_efficiency.full = dfixed_const(7);</div><div class='del'>-	dram_efficiency.full = dfixed_div(dram_efficiency, a);</div><div class='del'>-	bandwidth.full = dfixed_mul(dram_channels, yclk);</div><div class='del'>-	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);</div><div class='del'>-</div><div class='del'>-	return dfixed_trunc(bandwidth);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the dram bandwidth used for display (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the dram bandwidth for display in MBytes/s</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* Calculate DRAM Bandwidth and the part allocated to display. */</div><div class='del'>-	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */</div><div class='del'>-	fixed20_12 yclk, dram_channels, bandwidth;</div><div class='del'>-	fixed20_12 a;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(1000);</div><div class='del'>-	yclk.full = dfixed_const(wm-&gt;yclk);</div><div class='del'>-	yclk.full = dfixed_div(yclk, a);</div><div class='del'>-	dram_channels.full = dfixed_const(wm-&gt;dram_channels * 4);</div><div class='del'>-	a.full = dfixed_const(10);</div><div class='del'>-	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */</div><div class='del'>-	disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);</div><div class='del'>-	bandwidth.full = dfixed_mul(dram_channels, yclk);</div><div class='del'>-	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);</div><div class='del'>-</div><div class='del'>-	return dfixed_trunc(bandwidth);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_data_return_bandwidth - get the data return bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the data return bandwidth used for display (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the data return bandwidth in MBytes/s</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* Calculate the display Data return Bandwidth */</div><div class='del'>-	fixed20_12 return_efficiency; /* 0.8 */</div><div class='del'>-	fixed20_12 sclk, bandwidth;</div><div class='del'>-	fixed20_12 a;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(1000);</div><div class='del'>-	sclk.full = dfixed_const(wm-&gt;sclk);</div><div class='del'>-	sclk.full = dfixed_div(sclk, a);</div><div class='del'>-	a.full = dfixed_const(10);</div><div class='del'>-	return_efficiency.full = dfixed_const(8);</div><div class='del'>-	return_efficiency.full = dfixed_div(return_efficiency, a);</div><div class='del'>-	a.full = dfixed_const(32);</div><div class='del'>-	bandwidth.full = dfixed_mul(a, sclk);</div><div class='del'>-	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);</div><div class='del'>-</div><div class='del'>-	return dfixed_trunc(bandwidth);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the dmif bandwidth used for display (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the dmif bandwidth in MBytes/s</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* Calculate the DMIF Request Bandwidth */</div><div class='del'>-	fixed20_12 disp_clk_request_efficiency; /* 0.8 */</div><div class='del'>-	fixed20_12 disp_clk, bandwidth;</div><div class='del'>-	fixed20_12 a, b;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(1000);</div><div class='del'>-	disp_clk.full = dfixed_const(wm-&gt;disp_clk);</div><div class='del'>-	disp_clk.full = dfixed_div(disp_clk, a);</div><div class='del'>-	a.full = dfixed_const(32);</div><div class='del'>-	b.full = dfixed_mul(a, disp_clk);</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(10);</div><div class='del'>-	disp_clk_request_efficiency.full = dfixed_const(8);</div><div class='del'>-	disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);</div><div class='del'>-</div><div class='del'>-	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);</div><div class='del'>-</div><div class='del'>-	return dfixed_trunc(bandwidth);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_available_bandwidth - get the min available bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the min available bandwidth used for display (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the min available bandwidth in MBytes/s</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */</div><div class='del'>-	u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);</div><div class='del'>-	u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);</div><div class='del'>-	u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);</div><div class='del'>-</div><div class='del'>-	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_average_bandwidth - get the average available bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the average available bandwidth used for display (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the average available bandwidth in MBytes/s</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* Calculate the display mode Average Bandwidth</div><div class='del'>-	 * DisplayMode should contain the source and destination dimensions,</div><div class='del'>-	 * timing, etc.</div><div class='del'>-	 */</div><div class='del'>-	fixed20_12 bpp;</div><div class='del'>-	fixed20_12 line_time;</div><div class='del'>-	fixed20_12 src_width;</div><div class='del'>-	fixed20_12 bandwidth;</div><div class='del'>-	fixed20_12 a;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(1000);</div><div class='del'>-	line_time.full = dfixed_const(wm-&gt;active_time + wm-&gt;blank_time);</div><div class='del'>-	line_time.full = dfixed_div(line_time, a);</div><div class='del'>-	bpp.full = dfixed_const(wm-&gt;bytes_per_pixel);</div><div class='del'>-	src_width.full = dfixed_const(wm-&gt;src_width);</div><div class='del'>-	bandwidth.full = dfixed_mul(src_width, bpp);</div><div class='del'>-	bandwidth.full = dfixed_mul(bandwidth, wm-&gt;vsc);</div><div class='del'>-	bandwidth.full = dfixed_div(bandwidth, line_time);</div><div class='del'>-</div><div class='del'>-	return dfixed_trunc(bandwidth);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_latency_watermark - get the latency watermark</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Calculate the latency watermark (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns the latency watermark in ns</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	/* First calculate the latency in ns */</div><div class='del'>-	u32 mc_latency = 2000; /* 2000 ns. */</div><div class='del'>-	u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);</div><div class='del'>-	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;</div><div class='del'>-	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;</div><div class='del'>-	u32 dc_latency = 40000000 / wm-&gt;disp_clk; /* dc pipe latency */</div><div class='del'>-	u32 other_heads_data_return_time = ((wm-&gt;num_heads + 1) * worst_chunk_return_time) +</div><div class='del'>-		(wm-&gt;num_heads * cursor_line_pair_return_time);</div><div class='del'>-	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;</div><div class='del'>-	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;</div><div class='del'>-	u32 tmp, dmif_size = 12288;</div><div class='del'>-	fixed20_12 a, b, c;</div><div class='del'>-</div><div class='del'>-	if (wm-&gt;num_heads == 0)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(2);</div><div class='del'>-	b.full = dfixed_const(1);</div><div class='del'>-	if ((wm-&gt;vsc.full &gt; a.full) ||</div><div class='del'>-	    ((wm-&gt;vsc.full &gt; b.full) &amp;&amp; (wm-&gt;vtaps &gt;= 3)) ||</div><div class='del'>-	    (wm-&gt;vtaps &gt;= 5) ||</div><div class='del'>-	    ((wm-&gt;vsc.full &gt;= a.full) &amp;&amp; wm-&gt;interlaced))</div><div class='del'>-		max_src_lines_per_dst_line = 4;</div><div class='del'>-	else</div><div class='del'>-		max_src_lines_per_dst_line = 2;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(available_bandwidth);</div><div class='del'>-	b.full = dfixed_const(wm-&gt;num_heads);</div><div class='del'>-	a.full = dfixed_div(a, b);</div><div class='del'>-	tmp = div_u64((u64) dmif_size * (u64) wm-&gt;disp_clk, mc_latency + 512);</div><div class='del'>-	tmp = min(dfixed_trunc(a), tmp);</div><div class='del'>-</div><div class='del'>-	lb_fill_bw = min(tmp, wm-&gt;disp_clk * wm-&gt;bytes_per_pixel / 1000);</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(max_src_lines_per_dst_line * wm-&gt;src_width * wm-&gt;bytes_per_pixel);</div><div class='del'>-	b.full = dfixed_const(1000);</div><div class='del'>-	c.full = dfixed_const(lb_fill_bw);</div><div class='del'>-	b.full = dfixed_div(c, b);</div><div class='del'>-	a.full = dfixed_div(a, b);</div><div class='del'>-	line_fill_time = dfixed_trunc(a);</div><div class='del'>-</div><div class='del'>-	if (line_fill_time &lt; wm-&gt;active_time)</div><div class='del'>-		return latency;</div><div class='del'>-	else</div><div class='del'>-		return latency + (line_fill_time - wm-&gt;active_time);</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check</div><div class='del'>- * average and available dram bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Check if the display average bandwidth fits in the display</div><div class='del'>- * dram bandwidth (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns true if the display fits, false if not.</div><div class='del'>- */</div><div class='del'>-static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	if (dce_v11_0_average_bandwidth(wm) &lt;=</div><div class='del'>-	    (dce_v11_0_dram_bandwidth_for_display(wm) / wm-&gt;num_heads))</div><div class='del'>-		return true;</div><div class='del'>-	else</div><div class='del'>-		return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_average_bandwidth_vs_available_bandwidth - check</div><div class='del'>- * average and available bandwidth</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Check if the display average bandwidth fits in the display</div><div class='del'>- * available bandwidth (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns true if the display fits, false if not.</div><div class='del'>- */</div><div class='del'>-static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	if (dce_v11_0_average_bandwidth(wm) &lt;=</div><div class='del'>-	    (dce_v11_0_available_bandwidth(wm) / wm-&gt;num_heads))</div><div class='del'>-		return true;</div><div class='del'>-	else</div><div class='del'>-		return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_check_latency_hiding - check latency hiding</div><div class='del'>- *</div><div class='del'>- * @wm: watermark calculation data</div><div class='del'>- *</div><div class='del'>- * Check latency hiding (CIK).</div><div class='del'>- * Used for display watermark bandwidth calculations</div><div class='del'>- * Returns true if the display fits, false if not.</div><div class='del'>- */</div><div class='del'>-static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)</div><div class='del'>-{</div><div class='del'>-	u32 lb_partitions = wm-&gt;lb_size / wm-&gt;src_width;</div><div class='del'>-	u32 line_time = wm-&gt;active_time + wm-&gt;blank_time;</div><div class='del'>-	u32 latency_tolerant_lines;</div><div class='del'>-	u32 latency_hiding;</div><div class='del'>-	fixed20_12 a;</div><div class='del'>-</div><div class='del'>-	a.full = dfixed_const(1);</div><div class='del'>-	if (wm-&gt;vsc.full &gt; a.full)</div><div class='del'>-		latency_tolerant_lines = 1;</div><div class='del'>-	else {</div><div class='del'>-		if (lb_partitions &lt;= (wm-&gt;vtaps + 1))</div><div class='del'>-			latency_tolerant_lines = 1;</div><div class='del'>-		else</div><div class='del'>-			latency_tolerant_lines = 2;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	latency_hiding = (latency_tolerant_lines * line_time + wm-&gt;blank_time);</div><div class='del'>-</div><div class='del'>-	if (dce_v11_0_latency_watermark(wm) &lt;= latency_hiding)</div><div class='del'>-		return true;</div><div class='del'>-	else</div><div class='del'>-		return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_program_watermarks - program display watermarks</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @amdgpu_crtc: the selected display controller</div><div class='del'>- * @lb_size: line buffer size</div><div class='del'>- * @num_heads: number of display controllers in use</div><div class='del'>- *</div><div class='del'>- * Calculate and program the display watermarks for the</div><div class='del'>- * selected display controller (CIK).</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,</div><div class='del'>-					struct amdgpu_crtc *amdgpu_crtc,</div><div class='del'>-					u32 lb_size, u32 num_heads)</div><div class='del'>-{</div><div class='del'>-	struct drm_display_mode *mode = &amp;amdgpu_crtc-&gt;base.mode;</div><div class='del'>-	struct dce10_wm_params wm_low, wm_high;</div><div class='del'>-	u32 active_time;</div><div class='del'>-	u32 line_time = 0;</div><div class='del'>-	u32 latency_watermark_a = 0, latency_watermark_b = 0;</div><div class='del'>-	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_crtc-&gt;base.enabled &amp;&amp; num_heads &amp;&amp; mode) {</div><div class='del'>-		active_time = (u32) div_u64((u64)mode-&gt;crtc_hdisplay * 1000000,</div><div class='del'>-					    (u32)mode-&gt;clock);</div><div class='del'>-		line_time = (u32) div_u64((u64)mode-&gt;crtc_htotal * 1000000,</div><div class='del'>-					  (u32)mode-&gt;clock);</div><div class='del'>-		line_time = min_t(u32, line_time, 65535);</div><div class='del'>-</div><div class='del'>-		/* watermark for high clocks */</div><div class='del'>-		if (adev-&gt;pm.dpm_enabled) {</div><div class='del'>-			wm_high.yclk =</div><div class='del'>-				amdgpu_dpm_get_mclk(adev, false) * 10;</div><div class='del'>-			wm_high.sclk =</div><div class='del'>-				amdgpu_dpm_get_sclk(adev, false) * 10;</div><div class='del'>-		} else {</div><div class='del'>-			wm_high.yclk = adev-&gt;pm.current_mclk * 10;</div><div class='del'>-			wm_high.sclk = adev-&gt;pm.current_sclk * 10;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		wm_high.disp_clk = mode-&gt;clock;</div><div class='del'>-		wm_high.src_width = mode-&gt;crtc_hdisplay;</div><div class='del'>-		wm_high.active_time = active_time;</div><div class='del'>-		wm_high.blank_time = line_time - wm_high.active_time;</div><div class='del'>-		wm_high.interlaced = false;</div><div class='del'>-		if (mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE)</div><div class='del'>-			wm_high.interlaced = true;</div><div class='del'>-		wm_high.vsc = amdgpu_crtc-&gt;vsc;</div><div class='del'>-		wm_high.vtaps = 1;</div><div class='del'>-		if (amdgpu_crtc-&gt;rmx_type != RMX_OFF)</div><div class='del'>-			wm_high.vtaps = 2;</div><div class='del'>-		wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */</div><div class='del'>-		wm_high.lb_size = lb_size;</div><div class='del'>-		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);</div><div class='del'>-		wm_high.num_heads = num_heads;</div><div class='del'>-</div><div class='del'>-		/* set for high clocks */</div><div class='del'>-		latency_watermark_a = min_t(u32, dce_v11_0_latency_watermark(&amp;wm_high), 65535);</div><div class='del'>-</div><div class='del'>-		/* possibly force display priority to high */</div><div class='del'>-		/* should really do this at mode validation time... */</div><div class='del'>-		if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&amp;wm_high) ||</div><div class='del'>-		    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&amp;wm_high) ||</div><div class='del'>-		    !dce_v11_0_check_latency_hiding(&amp;wm_high) ||</div><div class='del'>-		    (adev-&gt;mode_info.disp_priority == 2)) {</div><div class='del'>-			DRM_DEBUG_KMS("force priority to high\n");</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* watermark for low clocks */</div><div class='del'>-		if (adev-&gt;pm.dpm_enabled) {</div><div class='del'>-			wm_low.yclk =</div><div class='del'>-				amdgpu_dpm_get_mclk(adev, true) * 10;</div><div class='del'>-			wm_low.sclk =</div><div class='del'>-				amdgpu_dpm_get_sclk(adev, true) * 10;</div><div class='del'>-		} else {</div><div class='del'>-			wm_low.yclk = adev-&gt;pm.current_mclk * 10;</div><div class='del'>-			wm_low.sclk = adev-&gt;pm.current_sclk * 10;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		wm_low.disp_clk = mode-&gt;clock;</div><div class='del'>-		wm_low.src_width = mode-&gt;crtc_hdisplay;</div><div class='del'>-		wm_low.active_time = active_time;</div><div class='del'>-		wm_low.blank_time = line_time - wm_low.active_time;</div><div class='del'>-		wm_low.interlaced = false;</div><div class='del'>-		if (mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE)</div><div class='del'>-			wm_low.interlaced = true;</div><div class='del'>-		wm_low.vsc = amdgpu_crtc-&gt;vsc;</div><div class='del'>-		wm_low.vtaps = 1;</div><div class='del'>-		if (amdgpu_crtc-&gt;rmx_type != RMX_OFF)</div><div class='del'>-			wm_low.vtaps = 2;</div><div class='del'>-		wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */</div><div class='del'>-		wm_low.lb_size = lb_size;</div><div class='del'>-		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);</div><div class='del'>-		wm_low.num_heads = num_heads;</div><div class='del'>-</div><div class='del'>-		/* set for low clocks */</div><div class='del'>-		latency_watermark_b = min_t(u32, dce_v11_0_latency_watermark(&amp;wm_low), 65535);</div><div class='del'>-</div><div class='del'>-		/* possibly force display priority to high */</div><div class='del'>-		/* should really do this at mode validation time... */</div><div class='del'>-		if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&amp;wm_low) ||</div><div class='del'>-		    !dce_v11_0_average_bandwidth_vs_available_bandwidth(&amp;wm_low) ||</div><div class='del'>-		    !dce_v11_0_check_latency_hiding(&amp;wm_low) ||</div><div class='del'>-		    (adev-&gt;mode_info.disp_priority == 2)) {</div><div class='del'>-			DRM_DEBUG_KMS("force priority to high\n");</div><div class='del'>-		}</div><div class='del'>-		lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode-&gt;crtc_hdisplay);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* select wm A */</div><div class='del'>-	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);</div><div class='del'>-	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);</div><div class='del'>-	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-	/* select wm B */</div><div class='del'>-	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);</div><div class='del'>-	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);</div><div class='del'>-	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-	/* restore original selection */</div><div class='del'>-	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc-&gt;crtc_offset, wm_mask);</div><div class='del'>-</div><div class='del'>-	/* save values for DPM */</div><div class='del'>-	amdgpu_crtc-&gt;line_time = line_time;</div><div class='del'>-	amdgpu_crtc-&gt;wm_high = latency_watermark_a;</div><div class='del'>-	amdgpu_crtc-&gt;wm_low = latency_watermark_b;</div><div class='del'>-	/* Save number of lines the linebuffer leads before the scanout */</div><div class='del'>-	amdgpu_crtc-&gt;lb_vblank_lead_lines = lb_vblank_lead_lines;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_bandwidth_update - program display watermarks</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='del'>- * Calculate and program the display watermarks and line</div><div class='del'>- * buffer allocation (CIK).</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct drm_display_mode *mode = NULL;</div><div class='del'>-	u32 num_heads = 0, lb_size;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	amdgpu_display_update_priority(adev);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		if (adev-&gt;mode_info.crtcs[i]-&gt;base.enabled)</div><div class='del'>-			num_heads++;</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		mode = &amp;adev-&gt;mode_info.crtcs[i]-&gt;base.mode;</div><div class='del'>-		lb_size = dce_v11_0_line_buffer_adjust(adev, adev-&gt;mode_info.crtcs[i], mode);</div><div class='del'>-		dce_v11_0_program_watermarks(adev, adev-&gt;mode_info.crtcs[i],</div><div class='del'>-					    lb_size, num_heads);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	u32 offset, tmp;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++) {</div><div class='del'>-		offset = adev-&gt;mode_info.audio.pin[i].offset;</div><div class='del'>-		tmp = RREG32_AUDIO_ENDPT(offset,</div><div class='del'>-					 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);</div><div class='del'>-		if (((tmp &amp;</div><div class='del'>-		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) &gt;&gt;</div><div class='del'>-		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)</div><div class='del'>-			adev-&gt;mode_info.audio.pin[i].connected = false;</div><div class='del'>-		else</div><div class='del'>-			adev-&gt;mode_info.audio.pin[i].connected = true;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	dce_v11_0_audio_get_connected_pins(adev);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++) {</div><div class='del'>-		if (adev-&gt;mode_info.audio.pin[i].connected)</div><div class='del'>-			return &amp;adev-&gt;mode_info.audio.pin[i];</div><div class='del'>-	}</div><div class='del'>-	DRM_ERROR("No connected audio pins found!\n");</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(encoder-&gt;dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt || !dig-&gt;afmt-&gt;pin)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig-&gt;afmt-&gt;pin-&gt;id);</div><div class='del'>-	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,</div><div class='del'>-						struct drm_display_mode *mode)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_list_iter iter;</div><div class='del'>-	struct amdgpu_connector *amdgpu_connector = NULL;</div><div class='del'>-	u32 tmp;</div><div class='del'>-	int interlace = 0;</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt || !dig-&gt;afmt-&gt;pin)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='del'>-	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		if (connector-&gt;encoder == encoder) {</div><div class='del'>-			amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	drm_connector_list_iter_end(&amp;iter);</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_connector) {</div><div class='del'>-		DRM_ERROR("Couldn't find encoder's connector\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE)</div><div class='del'>-		interlace = 1;</div><div class='del'>-	if (connector-&gt;latency_present[interlace]) {</div><div class='del'>-		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,</div><div class='del'>-				    VIDEO_LIPSYNC, connector-&gt;video_latency[interlace]);</div><div class='del'>-		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,</div><div class='del'>-				    AUDIO_LIPSYNC, connector-&gt;audio_latency[interlace]);</div><div class='del'>-	} else {</div><div class='del'>-		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,</div><div class='del'>-				    VIDEO_LIPSYNC, 0);</div><div class='del'>-		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,</div><div class='del'>-				    AUDIO_LIPSYNC, 0);</div><div class='del'>-	}</div><div class='del'>-	WREG32_AUDIO_ENDPT(dig-&gt;afmt-&gt;pin-&gt;offset,</div><div class='del'>-			   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_list_iter iter;</div><div class='del'>-	struct amdgpu_connector *amdgpu_connector = NULL;</div><div class='del'>-	u32 tmp;</div><div class='del'>-	u8 *sadb = NULL;</div><div class='del'>-	int sad_count;</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt || !dig-&gt;afmt-&gt;pin)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='del'>-	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		if (connector-&gt;encoder == encoder) {</div><div class='del'>-			amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	drm_connector_list_iter_end(&amp;iter);</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_connector) {</div><div class='del'>-		DRM_ERROR("Couldn't find encoder's connector\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &amp;sadb);</div><div class='del'>-	if (sad_count &lt; 0) {</div><div class='del'>-		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);</div><div class='del'>-		sad_count = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* program the speaker allocation */</div><div class='del'>-	tmp = RREG32_AUDIO_ENDPT(dig-&gt;afmt-&gt;pin-&gt;offset,</div><div class='del'>-				 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,</div><div class='del'>-			    DP_CONNECTION, 0);</div><div class='del'>-	/* set HDMI mode */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,</div><div class='del'>-			    HDMI_CONNECTION, 1);</div><div class='del'>-	if (sad_count)</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,</div><div class='del'>-				    SPEAKER_ALLOCATION, sadb[0]);</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,</div><div class='del'>-				    SPEAKER_ALLOCATION, 5); /* stereo */</div><div class='del'>-	WREG32_AUDIO_ENDPT(dig-&gt;afmt-&gt;pin-&gt;offset,</div><div class='del'>-			   ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);</div><div class='del'>-</div><div class='del'>-	kfree(sadb);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_list_iter iter;</div><div class='del'>-	struct amdgpu_connector *amdgpu_connector = NULL;</div><div class='del'>-	struct cea_sad *sads;</div><div class='del'>-	int i, sad_count;</div><div class='del'>-</div><div class='del'>-	static const u16 eld_reg_to_type[][2] = {</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },</div><div class='del'>-		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt || !dig-&gt;afmt-&gt;pin)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='del'>-	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		if (connector-&gt;encoder == encoder) {</div><div class='del'>-			amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	drm_connector_list_iter_end(&amp;iter);</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_connector) {</div><div class='del'>-		DRM_ERROR("Couldn't find encoder's connector\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &amp;sads);</div><div class='del'>-	if (sad_count &lt; 0)</div><div class='del'>-		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);</div><div class='del'>-	if (sad_count &lt;= 0)</div><div class='del'>-		return;</div><div class='del'>-	BUG_ON(!sads);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(eld_reg_to_type); i++) {</div><div class='del'>-		u32 tmp = 0;</div><div class='del'>-		u8 stereo_freqs = 0;</div><div class='del'>-		int max_channels = -1;</div><div class='del'>-		int j;</div><div class='del'>-</div><div class='del'>-		for (j = 0; j &lt; sad_count; j++) {</div><div class='del'>-			struct cea_sad *sad = &amp;sads[j];</div><div class='del'>-</div><div class='del'>-			if (sad-&gt;format == eld_reg_to_type[i][1]) {</div><div class='del'>-				if (sad-&gt;channels &gt; max_channels) {</div><div class='del'>-					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-							    MAX_CHANNELS, sad-&gt;channels);</div><div class='del'>-					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-							    DESCRIPTOR_BYTE_2, sad-&gt;byte2);</div><div class='del'>-					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-							    SUPPORTED_FREQUENCIES, sad-&gt;freq);</div><div class='del'>-					max_channels = sad-&gt;channels;</div><div class='del'>-				}</div><div class='del'>-</div><div class='del'>-				if (sad-&gt;format == HDMI_AUDIO_CODING_TYPE_PCM)</div><div class='del'>-					stereo_freqs |= sad-&gt;freq;</div><div class='del'>-				else</div><div class='del'>-					break;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-				    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);</div><div class='del'>-		WREG32_AUDIO_ENDPT(dig-&gt;afmt-&gt;pin-&gt;offset, eld_reg_to_type[i][0], tmp);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kfree(sads);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_enable(struct amdgpu_device *adev,</div><div class='del'>-				  struct amdgpu_audio_pin *pin,</div><div class='del'>-				  bool enable)</div><div class='del'>-{</div><div class='del'>-	if (!pin)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	WREG32_AUDIO_ENDPT(pin-&gt;offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,</div><div class='del'>-			   enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const u32 pin_offsets[] =</div><div class='del'>-{</div><div class='del'>-	AUD0_REGISTER_OFFSET,</div><div class='del'>-	AUD1_REGISTER_OFFSET,</div><div class='del'>-	AUD2_REGISTER_OFFSET,</div><div class='del'>-	AUD3_REGISTER_OFFSET,</div><div class='del'>-	AUD4_REGISTER_OFFSET,</div><div class='del'>-	AUD5_REGISTER_OFFSET,</div><div class='del'>-	AUD6_REGISTER_OFFSET,</div><div class='del'>-	AUD7_REGISTER_OFFSET,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_audio_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_audio)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	adev-&gt;mode_info.audio.enabled = true;</div><div class='del'>-</div><div class='del'>-	switch (adev-&gt;asic_type) {</div><div class='del'>-	case CHIP_CARRIZO:</div><div class='del'>-	case CHIP_STONEY:</div><div class='del'>-		adev-&gt;mode_info.audio.num_pins = 7;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS10:</div><div class='del'>-	case CHIP_VEGAM:</div><div class='del'>-		adev-&gt;mode_info.audio.num_pins = 8;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS11:</div><div class='del'>-	case CHIP_POLARIS12:</div><div class='del'>-		adev-&gt;mode_info.audio.num_pins = 6;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++) {</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].channels = -1;</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].rate = -1;</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].bits_per_sample = -1;</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].status_bits = 0;</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].category_code = 0;</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].connected = false;</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].offset = pin_offsets[i];</div><div class='del'>-		adev-&gt;mode_info.audio.pin[i].id = i;</div><div class='del'>-		/* disable audio.  it will be set up later */</div><div class='del'>-		/* XXX remove once we switch to ip funcs */</div><div class='del'>-		dce_v11_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_fini(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_audio)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;mode_info.audio.enabled)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++)</div><div class='del'>-		dce_v11_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-</div><div class='del'>-	adev-&gt;mode_info.audio.enabled = false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * update the N and CTS parameters for a given pixel clock rate</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_32_0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);</div><div class='del'>-	WREG32(mmHDMI_ACR_32_0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_32_1 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);</div><div class='del'>-	WREG32(mmHDMI_ACR_32_1 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_44_0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);</div><div class='del'>-	WREG32(mmHDMI_ACR_44_0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_44_1 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);</div><div class='del'>-	WREG32(mmHDMI_ACR_44_1 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_48_0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);</div><div class='del'>-	WREG32(mmHDMI_ACR_48_0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_48_1 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);</div><div class='del'>-	WREG32(mmHDMI_ACR_48_1 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * build a HDMI Video Info Frame</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,</div><div class='del'>-					       void *buffer, size_t size)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	uint8_t *frame = buffer + 3;</div><div class='del'>-	uint8_t *header = buffer;</div><div class='del'>-</div><div class='del'>-	WREG32(mmAFMT_AVI_INFO0 + dig-&gt;afmt-&gt;offset,</div><div class='del'>-		frame[0x0] | (frame[0x1] &lt;&lt; 8) | (frame[0x2] &lt;&lt; 16) | (frame[0x3] &lt;&lt; 24));</div><div class='del'>-	WREG32(mmAFMT_AVI_INFO1 + dig-&gt;afmt-&gt;offset,</div><div class='del'>-		frame[0x4] | (frame[0x5] &lt;&lt; 8) | (frame[0x6] &lt;&lt; 16) | (frame[0x7] &lt;&lt; 24));</div><div class='del'>-	WREG32(mmAFMT_AVI_INFO2 + dig-&gt;afmt-&gt;offset,</div><div class='del'>-		frame[0x8] | (frame[0x9] &lt;&lt; 8) | (frame[0xA] &lt;&lt; 16) | (frame[0xB] &lt;&lt; 24));</div><div class='del'>-	WREG32(mmAFMT_AVI_INFO3 + dig-&gt;afmt-&gt;offset,</div><div class='del'>-		frame[0xC] | (frame[0xD] &lt;&lt; 8) | (header[1] &lt;&lt; 24));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder-&gt;crtc);</div><div class='del'>-	u32 dto_phase = 24 * 1000;</div><div class='del'>-	u32 dto_modulo = clock;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* XXX two dtos; generally use dto0 for hdmi */</div><div class='del'>-	/* Express [24MHz / target pixel clock] as an exact rational</div><div class='del'>-	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE</div><div class='del'>-	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator</div><div class='del'>-	 */</div><div class='del'>-	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,</div><div class='del'>-			    amdgpu_crtc-&gt;crtc_id);</div><div class='del'>-	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);</div><div class='del'>-	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);</div><div class='del'>-	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * update the info frames with the data from the current display mode</div><div class='del'>- */</div><div class='del'>-static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,</div><div class='del'>-				  struct drm_display_mode *mode)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);</div><div class='del'>-	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];</div><div class='del'>-	struct hdmi_avi_infoframe frame;</div><div class='del'>-	ssize_t err;</div><div class='del'>-	u32 tmp;</div><div class='del'>-	int bpc = 8;</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* Silent, r600_hdmi_enable will raise WARN for us */</div><div class='del'>-	if (!dig-&gt;afmt-&gt;enabled)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* hdmi deep color mode general control packets setup, if bpc &gt; 8 */</div><div class='del'>-	if (encoder-&gt;crtc) {</div><div class='del'>-		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder-&gt;crtc);</div><div class='del'>-		bpc = amdgpu_crtc-&gt;bpc;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* disable audio prior to setting up hw */</div><div class='del'>-	dig-&gt;afmt-&gt;pin = dce_v11_0_audio_get_pin(adev);</div><div class='del'>-	dce_v11_0_audio_enable(adev, dig-&gt;afmt-&gt;pin, false);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_audio_set_dto(encoder, mode-&gt;clock);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);</div><div class='del'>-	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig-&gt;afmt-&gt;offset, tmp); /* send null packets when required */</div><div class='del'>-</div><div class='del'>-	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig-&gt;afmt-&gt;offset, 0x1000);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	switch (bpc) {</div><div class='del'>-	case 0:</div><div class='del'>-	case 6:</div><div class='del'>-	case 8:</div><div class='del'>-	case 16:</div><div class='del'>-	default:</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);</div><div class='del'>-		DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",</div><div class='del'>-			  connector-&gt;name, bpc);</div><div class='del'>-		break;</div><div class='del'>-	case 10:</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);</div><div class='del'>-		DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",</div><div class='del'>-			  connector-&gt;name);</div><div class='del'>-		break;</div><div class='del'>-	case 12:</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);</div><div class='del'>-		DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",</div><div class='del'>-			  connector-&gt;name);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	WREG32(mmHDMI_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */</div><div class='del'>-	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* enable audio info frames (frames won't be set until audio is enabled) */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);</div><div class='del'>-	/* required for audio info values to be updated */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);</div><div class='del'>-	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* required for audio info values to be updated */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);</div><div class='del'>-	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* anything other than 0 */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);</div><div class='del'>-	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	WREG32(mmHDMI_GC + dig-&gt;afmt-&gt;offset, 0); /* unset HDMI_GC_AVMUTE */</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* set the default audio delay */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);</div><div class='del'>-	/* should be suffient for all audio modes and small enough for all hblanks */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);</div><div class='del'>-	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* allow 60958 channel status fields to be updated */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);</div><div class='del'>-	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	if (bpc &gt; 8)</div><div class='del'>-		/* clear SW CTS value */</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);</div><div class='del'>-	else</div><div class='del'>-		/* select SW CTS value */</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);</div><div class='del'>-	/* allow hw to sent ACR packets when required */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);</div><div class='del'>-	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_afmt_update_ACR(encoder, mode-&gt;clock);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_60958_0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);</div><div class='del'>-	WREG32(mmAFMT_60958_0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_60958_1 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);</div><div class='del'>-	WREG32(mmAFMT_60958_1 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_60958_2 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);</div><div class='del'>-	WREG32(mmAFMT_60958_2 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_audio_write_speaker_allocation(encoder);</div><div class='del'>-</div><div class='del'>-	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig-&gt;afmt-&gt;offset,</div><div class='del'>-	       (0xff &lt;&lt; AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));</div><div class='del'>-</div><div class='del'>-	dce_v11_0_afmt_audio_select_pin(encoder);</div><div class='del'>-	dce_v11_0_audio_write_sad_regs(encoder);</div><div class='del'>-	dce_v11_0_audio_write_latency_fields(encoder, mode);</div><div class='del'>-</div><div class='del'>-	err = drm_hdmi_avi_infoframe_from_display_mode(&amp;frame, connector, mode);</div><div class='del'>-	if (err &lt; 0) {</div><div class='del'>-		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	err = hdmi_avi_infoframe_pack(&amp;frame, buffer, sizeof(buffer));</div><div class='del'>-	if (err &lt; 0) {</div><div class='del'>-		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* enable AVI info frames */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);</div><div class='del'>-	/* required for audio info values to be updated */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);</div><div class='del'>-	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);</div><div class='del'>-	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig-&gt;afmt-&gt;offset);</div><div class='del'>-	/* send audio packets */</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);</div><div class='del'>-	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig-&gt;afmt-&gt;offset, tmp);</div><div class='del'>-</div><div class='del'>-	WREG32(mmAFMT_RAMP_CONTROL0 + dig-&gt;afmt-&gt;offset, 0x00FFFFFF);</div><div class='del'>-	WREG32(mmAFMT_RAMP_CONTROL1 + dig-&gt;afmt-&gt;offset, 0x007FFFFF);</div><div class='del'>-	WREG32(mmAFMT_RAMP_CONTROL2 + dig-&gt;afmt-&gt;offset, 0x00000001);</div><div class='del'>-	WREG32(mmAFMT_RAMP_CONTROL3 + dig-&gt;afmt-&gt;offset, 0x00000001);</div><div class='del'>-</div><div class='del'>-	/* enable audio after to setting up hw */</div><div class='del'>-	dce_v11_0_audio_enable(adev, dig-&gt;afmt-&gt;pin, true);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-</div><div class='del'>-	if (!dig || !dig-&gt;afmt)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* Silent, r600_hdmi_enable will raise WARN for us */</div><div class='del'>-	if (enable &amp;&amp; dig-&gt;afmt-&gt;enabled)</div><div class='del'>-		return;</div><div class='del'>-	if (!enable &amp;&amp; !dig-&gt;afmt-&gt;enabled)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (!enable &amp;&amp; dig-&gt;afmt-&gt;pin) {</div><div class='del'>-		dce_v11_0_audio_enable(adev, dig-&gt;afmt-&gt;pin, false);</div><div class='del'>-		dig-&gt;afmt-&gt;pin = NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dig-&gt;afmt-&gt;enabled = enable;</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",</div><div class='del'>-		  enable ? "En" : "Dis", dig-&gt;afmt-&gt;offset, amdgpu_encoder-&gt;encoder_id);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_afmt_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_dig; i++)</div><div class='del'>-		adev-&gt;mode_info.afmt[i] = NULL;</div><div class='del'>-</div><div class='del'>-	/* DCE11 has audio blocks tied to DIG encoders */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_dig; i++) {</div><div class='del'>-		adev-&gt;mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);</div><div class='del'>-		if (adev-&gt;mode_info.afmt[i]) {</div><div class='del'>-			adev-&gt;mode_info.afmt[i]-&gt;offset = dig_offsets[i];</div><div class='del'>-			adev-&gt;mode_info.afmt[i]-&gt;id = i;</div><div class='del'>-		} else {</div><div class='del'>-			int j;</div><div class='del'>-			for (j = 0; j &lt; i; j++) {</div><div class='del'>-				kfree(adev-&gt;mode_info.afmt[j]);</div><div class='del'>-				adev-&gt;mode_info.afmt[j] = NULL;</div><div class='del'>-			}</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_dig; i++) {</div><div class='del'>-		kfree(adev-&gt;mode_info.afmt[i]);</div><div class='del'>-		adev-&gt;mode_info.afmt[i] = NULL;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const u32 vga_control_regs[6] =</div><div class='del'>-{</div><div class='del'>-	mmD1VGA_CONTROL,</div><div class='del'>-	mmD2VGA_CONTROL,</div><div class='del'>-	mmD3VGA_CONTROL,</div><div class='del'>-	mmD4VGA_CONTROL,</div><div class='del'>-	mmD5VGA_CONTROL,</div><div class='del'>-	mmD6VGA_CONTROL,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	u32 vga_control;</div><div class='del'>-</div><div class='del'>-	vga_control = RREG32(vga_control_regs[amdgpu_crtc-&gt;crtc_id]) &amp; ~1;</div><div class='del'>-	if (enable)</div><div class='del'>-		WREG32(vga_control_regs[amdgpu_crtc-&gt;crtc_id], vga_control | 1);</div><div class='del'>-	else</div><div class='del'>-		WREG32(vga_control_regs[amdgpu_crtc-&gt;crtc_id], vga_control);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-</div><div class='del'>-	if (enable)</div><div class='del'>-		WREG32(mmGRPH_ENABLE + amdgpu_crtc-&gt;crtc_offset, 1);</div><div class='del'>-	else</div><div class='del'>-		WREG32(mmGRPH_ENABLE + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='del'>-				     struct drm_framebuffer *fb,</div><div class='del'>-				     int x, int y, int atomic)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct drm_framebuffer *target_fb;</div><div class='del'>-	struct drm_gem_object *obj;</div><div class='del'>-	struct amdgpu_bo *abo;</div><div class='del'>-	uint64_t fb_location, tiling_flags;</div><div class='del'>-	uint32_t fb_format, fb_pitch_pixels;</div><div class='del'>-	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);</div><div class='del'>-	u32 pipe_config;</div><div class='del'>-	u32 tmp, viewport_w, viewport_h;</div><div class='del'>-	int r;</div><div class='del'>-	bool bypass_lut = false;</div><div class='del'>-</div><div class='del'>-	/* no fb bound */</div><div class='del'>-	if (!atomic &amp;&amp; !crtc-&gt;primary-&gt;fb) {</div><div class='del'>-		DRM_DEBUG_KMS("No FB bound\n");</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (atomic)</div><div class='del'>-		target_fb = fb;</div><div class='del'>-	else</div><div class='del'>-		target_fb = crtc-&gt;primary-&gt;fb;</div><div class='del'>-</div><div class='del'>-	/* If atomic, assume fb object is pinned &amp; idle &amp; fenced and</div><div class='del'>-	 * just update base pointers</div><div class='del'>-	 */</div><div class='del'>-	obj = target_fb-&gt;obj[0];</div><div class='del'>-	abo = gem_to_amdgpu_bo(obj);</div><div class='del'>-	r = amdgpu_bo_reserve(abo, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	if (!atomic) {</div><div class='del'>-		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='del'>-		if (unlikely(r != 0)) {</div><div class='del'>-			amdgpu_bo_unreserve(abo);</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	fb_location = amdgpu_bo_gpu_offset(abo);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_get_tiling_flags(abo, &amp;tiling_flags);</div><div class='del'>-	amdgpu_bo_unreserve(abo);</div><div class='del'>-</div><div class='del'>-	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);</div><div class='del'>-</div><div class='del'>-	switch (target_fb-&gt;format-&gt;format) {</div><div class='del'>-	case DRM_FORMAT_C8:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_XRGB4444:</div><div class='del'>-	case DRM_FORMAT_ARGB4444:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN16);</div><div class='del'>-#endif</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_XRGB1555:</div><div class='del'>-	case DRM_FORMAT_ARGB1555:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN16);</div><div class='del'>-#endif</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_BGRX5551:</div><div class='del'>-	case DRM_FORMAT_BGRA5551:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN16);</div><div class='del'>-#endif</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_RGB565:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN16);</div><div class='del'>-#endif</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_XRGB8888:</div><div class='del'>-	case DRM_FORMAT_ARGB8888:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN32);</div><div class='del'>-#endif</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_XRGB2101010:</div><div class='del'>-	case DRM_FORMAT_ARGB2101010:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN32);</div><div class='del'>-#endif</div><div class='del'>-		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */</div><div class='del'>-		bypass_lut = true;</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_BGRX1010102:</div><div class='del'>-	case DRM_FORMAT_BGRA1010102:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN32);</div><div class='del'>-#endif</div><div class='del'>-		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */</div><div class='del'>-		bypass_lut = true;</div><div class='del'>-		break;</div><div class='del'>-	case DRM_FORMAT_XBGR8888:</div><div class='del'>-	case DRM_FORMAT_ABGR8888:</div><div class='del'>-		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,</div><div class='del'>-					ENDIAN_8IN32);</div><div class='del'>-#endif</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		DRM_ERROR("Unsupported screen format %p4cc\n",</div><div class='del'>-			  &amp;target_fb-&gt;format-&gt;format);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {</div><div class='del'>-		unsigned bankw, bankh, mtaspect, tile_split, num_banks;</div><div class='del'>-</div><div class='del'>-		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);</div><div class='del'>-		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);</div><div class='del'>-		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);</div><div class='del'>-		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);</div><div class='del'>-		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);</div><div class='del'>-</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,</div><div class='del'>-					  ARRAY_2D_TILED_THIN1);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,</div><div class='del'>-					  tile_split);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,</div><div class='del'>-					  mtaspect);</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,</div><div class='del'>-					  ADDR_SURF_MICRO_TILING_DISPLAY);</div><div class='del'>-	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {</div><div class='del'>-		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,</div><div class='del'>-					  ARRAY_1D_TILED_THIN1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,</div><div class='del'>-				  pipe_config);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_vga_enable(crtc, false);</div><div class='del'>-</div><div class='del'>-	/* Make sure surface address is updated at vertical blank rather than</div><div class='del'>-	 * horizontal blank</div><div class='del'>-	 */</div><div class='del'>-	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,</div><div class='del'>-			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);</div><div class='del'>-	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       upper_32_bits(fb_location));</div><div class='del'>-	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       upper_32_bits(fb_location));</div><div class='del'>-	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       (u32)fb_location &amp; GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);</div><div class='del'>-	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       (u32) fb_location &amp; GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);</div><div class='del'>-	WREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset, fb_format);</div><div class='del'>-	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc-&gt;crtc_offset, fb_swap);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT</div><div class='del'>-	 * for &gt; 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to</div><div class='del'>-	 * retain the full precision throughout the pipeline.</div><div class='del'>-	 */</div><div class='del'>-	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	if (bypass_lut)</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);</div><div class='del'>-	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	if (bypass_lut)</div><div class='del'>-		DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");</div><div class='del'>-</div><div class='del'>-	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmGRPH_X_START + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmGRPH_Y_START + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmGRPH_X_END + amdgpu_crtc-&gt;crtc_offset, target_fb-&gt;width);</div><div class='del'>-	WREG32(mmGRPH_Y_END + amdgpu_crtc-&gt;crtc_offset, target_fb-&gt;height);</div><div class='del'>-</div><div class='del'>-	fb_pitch_pixels = target_fb-&gt;pitches[0] / target_fb-&gt;format-&gt;cpp[0];</div><div class='del'>-	WREG32(mmGRPH_PITCH + amdgpu_crtc-&gt;crtc_offset, fb_pitch_pixels);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_grph_enable(crtc, true);</div><div class='del'>-</div><div class='del'>-	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       target_fb-&gt;height);</div><div class='del'>-</div><div class='del'>-	x &amp;= ~3;</div><div class='del'>-	y &amp;= ~1;</div><div class='del'>-	WREG32(mmVIEWPORT_START + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       (x &lt;&lt; 16) | y);</div><div class='del'>-	viewport_w = crtc-&gt;mode.hdisplay;</div><div class='del'>-	viewport_h = (crtc-&gt;mode.vdisplay + 1) &amp; ~1;</div><div class='del'>-	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       (viewport_w &lt;&lt; 16) | viewport_h);</div><div class='del'>-</div><div class='del'>-	/* set pageflip to happen anywhere in vblank interval */</div><div class='del'>-	WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-</div><div class='del'>-	if (!atomic &amp;&amp; fb &amp;&amp; fb != crtc-&gt;primary-&gt;fb) {</div><div class='del'>-		abo = gem_to_amdgpu_bo(fb-&gt;obj[0]);</div><div class='del'>-		r = amdgpu_bo_reserve(abo, true);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			return r;</div><div class='del'>-		amdgpu_bo_unpin(abo);</div><div class='del'>-		amdgpu_bo_unreserve(abo);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Bytes per pixel may have changed */</div><div class='del'>-	dce_v11_0_bandwidth_update(adev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_interleave(struct drm_crtc *crtc,</div><div class='del'>-				     struct drm_display_mode *mode)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	if (mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE)</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);</div><div class='del'>-	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	u16 *r, *g, *b;</div><div class='del'>-	int i;</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG_KMS("%d\n", amdgpu_crtc-&gt;crtc_id);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);</div><div class='del'>-	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);</div><div class='del'>-	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);</div><div class='del'>-	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-</div><div class='del'>-	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-</div><div class='del'>-	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc-&gt;crtc_offset, 0xffff);</div><div class='del'>-	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc-&gt;crtc_offset, 0xffff);</div><div class='del'>-	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc-&gt;crtc_offset, 0xffff);</div><div class='del'>-</div><div class='del'>-	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc-&gt;crtc_offset, 0x00000007);</div><div class='del'>-</div><div class='del'>-	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	r = crtc-&gt;gamma_store;</div><div class='del'>-	g = r + crtc-&gt;gamma_size;</div><div class='del'>-	b = g + crtc-&gt;gamma_size;</div><div class='del'>-	for (i = 0; i &lt; 256; i++) {</div><div class='del'>-		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-		       ((*r++ &amp; 0xffc0) &lt;&lt; 14) |</div><div class='del'>-		       ((*g++ &amp; 0xffc0) &lt;&lt; 4) |</div><div class='del'>-		       (*b++ &gt;&gt; 6));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);</div><div class='del'>-	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);</div><div class='del'>-	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);</div><div class='del'>-	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);</div><div class='del'>-	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-</div><div class='del'>-	/* XXX match this to the depth of the crtc fmt block, move to modeset? */</div><div class='del'>-	WREG32(mmDENORM_CONTROL + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='del'>-	/* XXX this only needs to be programmed once per crtc at startup,</div><div class='del'>-	 * not sure where the best place for it is</div><div class='del'>-	 */</div><div class='del'>-	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);</div><div class='del'>-	WREG32(mmALPHA_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_encoder-&gt;encoder_id) {</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:</div><div class='del'>-		if (dig-&gt;linkb)</div><div class='del'>-			return 1;</div><div class='del'>-		else</div><div class='del'>-			return 0;</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:</div><div class='del'>-		if (dig-&gt;linkb)</div><div class='del'>-			return 3;</div><div class='del'>-		else</div><div class='del'>-			return 2;</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:</div><div class='del'>-		if (dig-&gt;linkb)</div><div class='del'>-			return 5;</div><div class='del'>-		else</div><div class='del'>-			return 4;</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:</div><div class='del'>-		return 6;</div><div class='del'>-	default:</div><div class='del'>-		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder-&gt;encoder_id);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.</div><div class='del'>- *</div><div class='del'>- * @crtc: drm crtc</div><div class='del'>- *</div><div class='del'>- * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors</div><div class='del'>- * a single PPLL can be used for all DP crtcs/encoders.  For non-DP</div><div class='del'>- * monitors a dedicated PPLL must be used.  If a particular board has</div><div class='del'>- * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming</div><div class='del'>- * as there is no need to program the PLL itself.  If we are not able to</div><div class='del'>- * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to</div><div class='del'>- * avoid messing up an existing monitor.</div><div class='del'>- *</div><div class='del'>- * Asic specific PLL information</div><div class='del'>- *</div><div class='del'>- * DCE 10.x</div><div class='del'>- * Tonga</div><div class='del'>- * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)</div><div class='del'>- * CI</div><div class='del'>- * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	u32 pll_in_use;</div><div class='del'>-	int pll;</div><div class='del'>-</div><div class='del'>-	if ((adev-&gt;asic_type == CHIP_POLARIS10) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_POLARIS11) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_POLARIS12) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_VEGAM)) {</div><div class='del'>-		struct amdgpu_encoder *amdgpu_encoder =</div><div class='del'>-			to_amdgpu_encoder(amdgpu_crtc-&gt;encoder);</div><div class='del'>-		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-</div><div class='del'>-		if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc-&gt;encoder)))</div><div class='del'>-			return ATOM_DP_DTO;</div><div class='del'>-</div><div class='del'>-		switch (amdgpu_encoder-&gt;encoder_id) {</div><div class='del'>-		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:</div><div class='del'>-			if (dig-&gt;linkb)</div><div class='del'>-				return ATOM_COMBOPHY_PLL1;</div><div class='del'>-			else</div><div class='del'>-				return ATOM_COMBOPHY_PLL0;</div><div class='del'>-		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:</div><div class='del'>-			if (dig-&gt;linkb)</div><div class='del'>-				return ATOM_COMBOPHY_PLL3;</div><div class='del'>-			else</div><div class='del'>-				return ATOM_COMBOPHY_PLL2;</div><div class='del'>-		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:</div><div class='del'>-			if (dig-&gt;linkb)</div><div class='del'>-				return ATOM_COMBOPHY_PLL5;</div><div class='del'>-			else</div><div class='del'>-				return ATOM_COMBOPHY_PLL4;</div><div class='del'>-		default:</div><div class='del'>-			DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder-&gt;encoder_id);</div><div class='del'>-			return ATOM_PPLL_INVALID;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc-&gt;encoder))) {</div><div class='del'>-		if (adev-&gt;clock.dp_extclk)</div><div class='del'>-			/* skip PPLL programming if using ext clock */</div><div class='del'>-			return ATOM_PPLL_INVALID;</div><div class='del'>-		else {</div><div class='del'>-			/* use the same PPLL for all DP monitors */</div><div class='del'>-			pll = amdgpu_pll_get_shared_dp_ppll(crtc);</div><div class='del'>-			if (pll != ATOM_PPLL_INVALID)</div><div class='del'>-				return pll;</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		/* use the same PPLL for all monitors with the same clock */</div><div class='del'>-		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);</div><div class='del'>-		if (pll != ATOM_PPLL_INVALID)</div><div class='del'>-			return pll;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* XXX need to determine what plls are available on each DCE11 part */</div><div class='del'>-	pll_in_use = amdgpu_pll_get_use_mask(crtc);</div><div class='del'>-	if (adev-&gt;flags &amp; AMD_IS_APU) {</div><div class='del'>-		if (!(pll_in_use &amp; (1 &lt;&lt; ATOM_PPLL1)))</div><div class='del'>-			return ATOM_PPLL1;</div><div class='del'>-		if (!(pll_in_use &amp; (1 &lt;&lt; ATOM_PPLL0)))</div><div class='del'>-			return ATOM_PPLL0;</div><div class='del'>-		DRM_ERROR("unable to allocate a PPLL\n");</div><div class='del'>-		return ATOM_PPLL_INVALID;</div><div class='del'>-	} else {</div><div class='del'>-		if (!(pll_in_use &amp; (1 &lt;&lt; ATOM_PPLL2)))</div><div class='del'>-			return ATOM_PPLL2;</div><div class='del'>-		if (!(pll_in_use &amp; (1 &lt;&lt; ATOM_PPLL1)))</div><div class='del'>-			return ATOM_PPLL1;</div><div class='del'>-		if (!(pll_in_use &amp; (1 &lt;&lt; ATOM_PPLL0)))</div><div class='del'>-			return ATOM_PPLL0;</div><div class='del'>-		DRM_ERROR("unable to allocate a PPLL\n");</div><div class='del'>-		return ATOM_PPLL_INVALID;</div><div class='del'>-	}</div><div class='del'>-	return ATOM_PPLL_INVALID;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	uint32_t cur_lock;</div><div class='del'>-</div><div class='del'>-	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	if (lock)</div><div class='del'>-		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);</div><div class='del'>-	else</div><div class='del'>-		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);</div><div class='del'>-	WREG32(mmCUR_UPDATE + amdgpu_crtc-&gt;crtc_offset, cur_lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);</div><div class='del'>-	WREG32(mmCUR_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_show_cursor(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       upper_32_bits(amdgpu_crtc-&gt;cursor_addr));</div><div class='del'>-	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       lower_32_bits(amdgpu_crtc-&gt;cursor_addr));</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);</div><div class='del'>-	WREG32(mmCUR_CONTROL + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,</div><div class='del'>-					int x, int y)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='del'>-	int xorigin = 0, yorigin = 0;</div><div class='del'>-</div><div class='del'>-	amdgpu_crtc-&gt;cursor_x = x;</div><div class='del'>-	amdgpu_crtc-&gt;cursor_y = y;</div><div class='del'>-</div><div class='del'>-	/* avivo cursor are offset into the total surface */</div><div class='del'>-	x += crtc-&gt;x;</div><div class='del'>-	y += crtc-&gt;y;</div><div class='del'>-	DRM_DEBUG("x %d y %d c-&gt;x %d c-&gt;y %d\n", x, y, crtc-&gt;x, crtc-&gt;y);</div><div class='del'>-</div><div class='del'>-	if (x &lt; 0) {</div><div class='del'>-		xorigin = min(-x, amdgpu_crtc-&gt;max_cursor_width - 1);</div><div class='del'>-		x = 0;</div><div class='del'>-	}</div><div class='del'>-	if (y &lt; 0) {</div><div class='del'>-		yorigin = min(-y, amdgpu_crtc-&gt;max_cursor_height - 1);</div><div class='del'>-		y = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	WREG32(mmCUR_POSITION + amdgpu_crtc-&gt;crtc_offset, (x &lt;&lt; 16) | y);</div><div class='del'>-	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc-&gt;crtc_offset, (xorigin &lt;&lt; 16) | yorigin);</div><div class='del'>-	WREG32(mmCUR_SIZE + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((amdgpu_crtc-&gt;cursor_width - 1) &lt;&lt; 16) | (amdgpu_crtc-&gt;cursor_height - 1));</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,</div><div class='del'>-				      int x, int y)</div><div class='del'>-{</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	dce_v11_0_lock_cursor(crtc, true);</div><div class='del'>-	ret = dce_v11_0_cursor_move_locked(crtc, x, y);</div><div class='del'>-	dce_v11_0_lock_cursor(crtc, false);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,</div><div class='del'>-				      struct drm_file *file_priv,</div><div class='del'>-				      uint32_t handle,</div><div class='del'>-				      uint32_t width,</div><div class='del'>-				      uint32_t height,</div><div class='del'>-				      int32_t hot_x,</div><div class='del'>-				      int32_t hot_y)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_gem_object *obj;</div><div class='del'>-	struct amdgpu_bo *aobj;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (!handle) {</div><div class='del'>-		/* turn off cursor */</div><div class='del'>-		dce_v11_0_hide_cursor(crtc);</div><div class='del'>-		obj = NULL;</div><div class='del'>-		goto unpin;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if ((width &gt; amdgpu_crtc-&gt;max_cursor_width) ||</div><div class='del'>-	    (height &gt; amdgpu_crtc-&gt;max_cursor_height)) {</div><div class='del'>-		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	obj = drm_gem_object_lookup(file_priv, handle);</div><div class='del'>-	if (!obj) {</div><div class='del'>-		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc-&gt;crtc_id);</div><div class='del'>-		return -ENOENT;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	aobj = gem_to_amdgpu_bo(obj);</div><div class='del'>-	ret = amdgpu_bo_reserve(aobj, false);</div><div class='del'>-	if (ret != 0) {</div><div class='del'>-		drm_gem_object_put(obj);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='del'>-	amdgpu_bo_unreserve(aobj);</div><div class='del'>-	if (ret) {</div><div class='del'>-		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);</div><div class='del'>-		drm_gem_object_put(obj);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-	amdgpu_crtc-&gt;cursor_addr = amdgpu_bo_gpu_offset(aobj);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_lock_cursor(crtc, true);</div><div class='del'>-</div><div class='del'>-	if (width != amdgpu_crtc-&gt;cursor_width ||</div><div class='del'>-	    height != amdgpu_crtc-&gt;cursor_height ||</div><div class='del'>-	    hot_x != amdgpu_crtc-&gt;cursor_hot_x ||</div><div class='del'>-	    hot_y != amdgpu_crtc-&gt;cursor_hot_y) {</div><div class='del'>-		int x, y;</div><div class='del'>-</div><div class='del'>-		x = amdgpu_crtc-&gt;cursor_x + amdgpu_crtc-&gt;cursor_hot_x - hot_x;</div><div class='del'>-		y = amdgpu_crtc-&gt;cursor_y + amdgpu_crtc-&gt;cursor_hot_y - hot_y;</div><div class='del'>-</div><div class='del'>-		dce_v11_0_cursor_move_locked(crtc, x, y);</div><div class='del'>-</div><div class='del'>-		amdgpu_crtc-&gt;cursor_width = width;</div><div class='del'>-		amdgpu_crtc-&gt;cursor_height = height;</div><div class='del'>-		amdgpu_crtc-&gt;cursor_hot_x = hot_x;</div><div class='del'>-		amdgpu_crtc-&gt;cursor_hot_y = hot_y;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dce_v11_0_show_cursor(crtc);</div><div class='del'>-	dce_v11_0_lock_cursor(crtc, false);</div><div class='del'>-</div><div class='del'>-unpin:</div><div class='del'>-	if (amdgpu_crtc-&gt;cursor_bo) {</div><div class='del'>-		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc-&gt;cursor_bo);</div><div class='del'>-		ret = amdgpu_bo_reserve(aobj, true);</div><div class='del'>-		if (likely(ret == 0)) {</div><div class='del'>-			amdgpu_bo_unpin(aobj);</div><div class='del'>-			amdgpu_bo_unreserve(aobj);</div><div class='del'>-		}</div><div class='del'>-		drm_gem_object_put(amdgpu_crtc-&gt;cursor_bo);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_crtc-&gt;cursor_bo = obj;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_crtc-&gt;cursor_bo) {</div><div class='del'>-		dce_v11_0_lock_cursor(crtc, true);</div><div class='del'>-</div><div class='del'>-		dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc-&gt;cursor_x,</div><div class='del'>-					     amdgpu_crtc-&gt;cursor_y);</div><div class='del'>-</div><div class='del'>-		dce_v11_0_show_cursor(crtc);</div><div class='del'>-</div><div class='del'>-		dce_v11_0_lock_cursor(crtc, false);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,</div><div class='del'>-				    u16 *blue, uint32_t size,</div><div class='del'>-				    struct drm_modeset_acquire_ctx *ctx)</div><div class='del'>-{</div><div class='del'>-	dce_v11_0_crtc_load_lut(crtc);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-</div><div class='del'>-	drm_crtc_cleanup(crtc);</div><div class='del'>-	kfree(amdgpu_crtc);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {</div><div class='del'>-	.cursor_set2 = dce_v11_0_crtc_cursor_set2,</div><div class='del'>-	.cursor_move = dce_v11_0_crtc_cursor_move,</div><div class='del'>-	.gamma_set = dce_v11_0_crtc_gamma_set,</div><div class='del'>-	.set_config = amdgpu_display_crtc_set_config,</div><div class='del'>-	.destroy = dce_v11_0_crtc_destroy,</div><div class='del'>-	.page_flip_target = amdgpu_display_crtc_page_flip_target,</div><div class='del'>-	.get_vblank_counter = amdgpu_get_vblank_counter_kms,</div><div class='del'>-	.enable_vblank = amdgpu_enable_vblank_kms,</div><div class='del'>-	.disable_vblank = amdgpu_disable_vblank_kms,</div><div class='del'>-	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	unsigned type;</div><div class='del'>-</div><div class='del'>-	switch (mode) {</div><div class='del'>-	case DRM_MODE_DPMS_ON:</div><div class='del'>-		amdgpu_crtc-&gt;enabled = true;</div><div class='del'>-		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);</div><div class='del'>-		dce_v11_0_vga_enable(crtc, true);</div><div class='del'>-		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);</div><div class='del'>-		dce_v11_0_vga_enable(crtc, false);</div><div class='del'>-		/* Make sure VBLANK and PFLIP interrupts are still enabled */</div><div class='del'>-		type = amdgpu_display_crtc_idx_to_irq_type(adev,</div><div class='del'>-						amdgpu_crtc-&gt;crtc_id);</div><div class='del'>-		amdgpu_irq_update(adev, &amp;adev-&gt;crtc_irq, type);</div><div class='del'>-		amdgpu_irq_update(adev, &amp;adev-&gt;pageflip_irq, type);</div><div class='del'>-		drm_crtc_vblank_on(crtc);</div><div class='del'>-		dce_v11_0_crtc_load_lut(crtc);</div><div class='del'>-		break;</div><div class='del'>-	case DRM_MODE_DPMS_STANDBY:</div><div class='del'>-	case DRM_MODE_DPMS_SUSPEND:</div><div class='del'>-	case DRM_MODE_DPMS_OFF:</div><div class='del'>-		drm_crtc_vblank_off(crtc);</div><div class='del'>-		if (amdgpu_crtc-&gt;enabled) {</div><div class='del'>-			dce_v11_0_vga_enable(crtc, true);</div><div class='del'>-			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);</div><div class='del'>-			dce_v11_0_vga_enable(crtc, false);</div><div class='del'>-		}</div><div class='del'>-		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);</div><div class='del'>-		amdgpu_crtc-&gt;enabled = false;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	/* adjust pm to dpms */</div><div class='del'>-	amdgpu_dpm_compute_clocks(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	/* disable crtc pair power gating before programming */</div><div class='del'>-	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);</div><div class='del'>-	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);</div><div class='del'>-	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);</div><div class='del'>-	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_atom_ss ss;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);</div><div class='del'>-	if (crtc-&gt;primary-&gt;fb) {</div><div class='del'>-		int r;</div><div class='del'>-		struct amdgpu_bo *abo;</div><div class='del'>-</div><div class='del'>-		abo = gem_to_amdgpu_bo(crtc-&gt;primary-&gt;fb-&gt;obj[0]);</div><div class='del'>-		r = amdgpu_bo_reserve(abo, true);</div><div class='del'>-		if (unlikely(r))</div><div class='del'>-			DRM_ERROR("failed to reserve abo before unpin\n");</div><div class='del'>-		else {</div><div class='del'>-			amdgpu_bo_unpin(abo);</div><div class='del'>-			amdgpu_bo_unreserve(abo);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	/* disable the GRPH */</div><div class='del'>-	dce_v11_0_grph_enable(crtc, false);</div><div class='del'>-</div><div class='del'>-	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		if (adev-&gt;mode_info.crtcs[i] &amp;&amp;</div><div class='del'>-		    adev-&gt;mode_info.crtcs[i]-&gt;enabled &amp;&amp;</div><div class='del'>-		    i != amdgpu_crtc-&gt;crtc_id &amp;&amp;</div><div class='del'>-		    amdgpu_crtc-&gt;pll_id == adev-&gt;mode_info.crtcs[i]-&gt;pll_id) {</div><div class='del'>-			/* one other crtc is using this pll don't turn</div><div class='del'>-			 * off the pll</div><div class='del'>-			 */</div><div class='del'>-			goto done;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_crtc-&gt;pll_id) {</div><div class='del'>-	case ATOM_PPLL0:</div><div class='del'>-	case ATOM_PPLL1:</div><div class='del'>-	case ATOM_PPLL2:</div><div class='del'>-		/* disable the ppll */</div><div class='del'>-		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc-&gt;crtc_id, amdgpu_crtc-&gt;pll_id,</div><div class='del'>-						 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &amp;ss);</div><div class='del'>-		break;</div><div class='del'>-	case ATOM_COMBOPHY_PLL0:</div><div class='del'>-	case ATOM_COMBOPHY_PLL1:</div><div class='del'>-	case ATOM_COMBOPHY_PLL2:</div><div class='del'>-	case ATOM_COMBOPHY_PLL3:</div><div class='del'>-	case ATOM_COMBOPHY_PLL4:</div><div class='del'>-	case ATOM_COMBOPHY_PLL5:</div><div class='del'>-		/* disable the ppll */</div><div class='del'>-		amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc-&gt;pll_id,</div><div class='del'>-						 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &amp;ss);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-done:</div><div class='del'>-	amdgpu_crtc-&gt;pll_id = ATOM_PPLL_INVALID;</div><div class='del'>-	amdgpu_crtc-&gt;adjusted_clock = 0;</div><div class='del'>-	amdgpu_crtc-&gt;encoder = NULL;</div><div class='del'>-	amdgpu_crtc-&gt;connector = NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,</div><div class='del'>-				  struct drm_display_mode *mode,</div><div class='del'>-				  struct drm_display_mode *adjusted_mode,</div><div class='del'>-				  int x, int y, struct drm_framebuffer *old_fb)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_crtc-&gt;adjusted_clock)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	if ((adev-&gt;asic_type == CHIP_POLARIS10) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_POLARIS11) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_POLARIS12) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_VEGAM)) {</div><div class='del'>-		struct amdgpu_encoder *amdgpu_encoder =</div><div class='del'>-			to_amdgpu_encoder(amdgpu_crtc-&gt;encoder);</div><div class='del'>-		int encoder_mode =</div><div class='del'>-			amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc-&gt;encoder);</div><div class='del'>-</div><div class='del'>-		/* SetPixelClock calculates the plls and ss values now */</div><div class='del'>-		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc-&gt;crtc_id,</div><div class='del'>-						 amdgpu_crtc-&gt;pll_id,</div><div class='del'>-						 encoder_mode, amdgpu_encoder-&gt;encoder_id,</div><div class='del'>-						 adjusted_mode-&gt;clock, 0, 0, 0, 0,</div><div class='del'>-						 amdgpu_crtc-&gt;bpc, amdgpu_crtc-&gt;ss_enabled, &amp;amdgpu_crtc-&gt;ss);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);</div><div class='del'>-	}</div><div class='del'>-	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);</div><div class='del'>-	dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);</div><div class='del'>-	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);</div><div class='del'>-	amdgpu_atombios_crtc_scaler_setup(crtc);</div><div class='del'>-	dce_v11_0_cursor_reset(crtc);</div><div class='del'>-	/* update the hw version fpr dpm */</div><div class='del'>-	amdgpu_crtc-&gt;hw_mode = *adjusted_mode;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,</div><div class='del'>-				     const struct drm_display_mode *mode,</div><div class='del'>-				     struct drm_display_mode *adjusted_mode)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	struct drm_device *dev = crtc-&gt;dev;</div><div class='del'>-	struct drm_encoder *encoder;</div><div class='del'>-</div><div class='del'>-	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */</div><div class='del'>-	list_for_each_entry(encoder, &amp;dev-&gt;mode_config.encoder_list, head) {</div><div class='del'>-		if (encoder-&gt;crtc == crtc) {</div><div class='del'>-			amdgpu_crtc-&gt;encoder = encoder;</div><div class='del'>-			amdgpu_crtc-&gt;connector = amdgpu_get_connector_for_encoder(encoder);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	if ((amdgpu_crtc-&gt;encoder == NULL) || (amdgpu_crtc-&gt;connector == NULL)) {</div><div class='del'>-		amdgpu_crtc-&gt;encoder = NULL;</div><div class='del'>-		amdgpu_crtc-&gt;connector = NULL;</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-	if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))</div><div class='del'>-		return false;</div><div class='del'>-	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))</div><div class='del'>-		return false;</div><div class='del'>-	/* pick pll */</div><div class='del'>-	amdgpu_crtc-&gt;pll_id = dce_v11_0_pick_pll(crtc);</div><div class='del'>-	/* if we can't get a PPLL for a non-DP encoder, fail */</div><div class='del'>-	if ((amdgpu_crtc-&gt;pll_id == ATOM_PPLL_INVALID) &amp;&amp;</div><div class='del'>-	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc-&gt;encoder)))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,</div><div class='del'>-				  struct drm_framebuffer *old_fb)</div><div class='del'>-{</div><div class='del'>-	return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,</div><div class='del'>-					 struct drm_framebuffer *fb,</div><div class='del'>-					 int x, int y, enum mode_set_atomic state)</div><div class='del'>-{</div><div class='del'>-	return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {</div><div class='del'>-	.dpms = dce_v11_0_crtc_dpms,</div><div class='del'>-	.mode_fixup = dce_v11_0_crtc_mode_fixup,</div><div class='del'>-	.mode_set = dce_v11_0_crtc_mode_set,</div><div class='del'>-	.mode_set_base = dce_v11_0_crtc_set_base,</div><div class='del'>-	.mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,</div><div class='del'>-	.prepare = dce_v11_0_crtc_prepare,</div><div class='del'>-	.commit = dce_v11_0_crtc_commit,</div><div class='del'>-	.disable = dce_v11_0_crtc_disable,</div><div class='del'>-	.get_scanout_position = amdgpu_crtc_get_scanout_position,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc;</div><div class='del'>-</div><div class='del'>-	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +</div><div class='del'>-			      (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);</div><div class='del'>-	if (amdgpu_crtc == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	drm_crtc_init(adev_to_drm(adev), &amp;amdgpu_crtc-&gt;base, &amp;dce_v11_0_crtc_funcs);</div><div class='del'>-</div><div class='del'>-	drm_mode_crtc_set_gamma_size(&amp;amdgpu_crtc-&gt;base, 256);</div><div class='del'>-	amdgpu_crtc-&gt;crtc_id = index;</div><div class='del'>-	adev-&gt;mode_info.crtcs[index] = amdgpu_crtc;</div><div class='del'>-</div><div class='del'>-	amdgpu_crtc-&gt;max_cursor_width = 128;</div><div class='del'>-	amdgpu_crtc-&gt;max_cursor_height = 128;</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.cursor_width = amdgpu_crtc-&gt;max_cursor_width;</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.cursor_height = amdgpu_crtc-&gt;max_cursor_height;</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_crtc-&gt;crtc_id) {</div><div class='del'>-	case 0:</div><div class='del'>-	default:</div><div class='del'>-		amdgpu_crtc-&gt;crtc_offset = CRTC0_REGISTER_OFFSET;</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		amdgpu_crtc-&gt;crtc_offset = CRTC1_REGISTER_OFFSET;</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		amdgpu_crtc-&gt;crtc_offset = CRTC2_REGISTER_OFFSET;</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		amdgpu_crtc-&gt;crtc_offset = CRTC3_REGISTER_OFFSET;</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		amdgpu_crtc-&gt;crtc_offset = CRTC4_REGISTER_OFFSET;</div><div class='del'>-		break;</div><div class='del'>-	case 5:</div><div class='del'>-		amdgpu_crtc-&gt;crtc_offset = CRTC5_REGISTER_OFFSET;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_crtc-&gt;pll_id = ATOM_PPLL_INVALID;</div><div class='del'>-	amdgpu_crtc-&gt;adjusted_clock = 0;</div><div class='del'>-	amdgpu_crtc-&gt;encoder = NULL;</div><div class='del'>-	amdgpu_crtc-&gt;connector = NULL;</div><div class='del'>-	drm_crtc_helper_add(&amp;amdgpu_crtc-&gt;base, &amp;dce_v11_0_crtc_helper_funcs);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_early_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	adev-&gt;audio_endpt_rreg = &amp;dce_v11_0_audio_endpt_rreg;</div><div class='del'>-	adev-&gt;audio_endpt_wreg = &amp;dce_v11_0_audio_endpt_wreg;</div><div class='del'>-</div><div class='del'>-	dce_v11_0_set_display_funcs(adev);</div><div class='del'>-</div><div class='del'>-	adev-&gt;mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);</div><div class='del'>-</div><div class='del'>-	switch (adev-&gt;asic_type) {</div><div class='del'>-	case CHIP_CARRIZO:</div><div class='del'>-		adev-&gt;mode_info.num_hpd = 6;</div><div class='del'>-		adev-&gt;mode_info.num_dig = 9;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_STONEY:</div><div class='del'>-		adev-&gt;mode_info.num_hpd = 6;</div><div class='del'>-		adev-&gt;mode_info.num_dig = 9;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS10:</div><div class='del'>-	case CHIP_VEGAM:</div><div class='del'>-		adev-&gt;mode_info.num_hpd = 6;</div><div class='del'>-		adev-&gt;mode_info.num_dig = 6;</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_POLARIS11:</div><div class='del'>-	case CHIP_POLARIS12:</div><div class='del'>-		adev-&gt;mode_info.num_hpd = 5;</div><div class='del'>-		adev-&gt;mode_info.num_dig = 5;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		/* FIXME: not supported yet */</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dce_v11_0_set_irq_funcs(adev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_sw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &amp;adev-&gt;crtc_irq);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i &lt; 20; i += 2) {</div><div class='del'>-		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &amp;adev-&gt;pageflip_irq);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* HPD hotplug */</div><div class='del'>-	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &amp;adev-&gt;hpd_irq);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.funcs = &amp;amdgpu_mode_funcs;</div><div class='del'>-</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.async_page_flip = true;</div><div class='del'>-</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.max_width = 16384;</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.max_height = 16384;</div><div class='del'>-</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.preferred_depth = 24;</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.prefer_shadow = 1;</div><div class='del'>-</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.fb_modifiers_not_supported = true;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_display_modeset_create_props(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.max_width = 16384;</div><div class='del'>-	adev_to_drm(adev)-&gt;mode_config.max_height = 16384;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	/* allocate crtcs */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		r = dce_v11_0_crtc_init(adev, i);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (amdgpu_atombios_get_connector_info_from_object_table(adev))</div><div class='del'>-		amdgpu_display_print_display_setup(adev_to_drm(adev));</div><div class='del'>-	else</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	/* setup afmt */</div><div class='del'>-	r = dce_v11_0_afmt_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = dce_v11_0_audio_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	/* Disable vblank IRQs aggressively for power-saving */</div><div class='del'>-	/* XXX: can this be enabled for DC? */</div><div class='del'>-	adev_to_drm(adev)-&gt;vblank_disable_immediate = true;</div><div class='del'>-</div><div class='del'>-	r = drm_vblank_init(adev_to_drm(adev), adev-&gt;mode_info.num_crtc);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	INIT_DELAYED_WORK(&amp;adev-&gt;hotplug_work,</div><div class='del'>-		  amdgpu_display_hotplug_work_func);</div><div class='del'>-</div><div class='del'>-	drm_kms_helper_poll_init(adev_to_drm(adev));</div><div class='del'>-</div><div class='del'>-	adev-&gt;mode_info.mode_config_initialized = true;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_sw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	kfree(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='del'>-</div><div class='del'>-	drm_kms_helper_poll_fini(adev_to_drm(adev));</div><div class='del'>-</div><div class='del'>-	dce_v11_0_audio_fini(adev);</div><div class='del'>-</div><div class='del'>-	dce_v11_0_afmt_fini(adev);</div><div class='del'>-</div><div class='del'>-	drm_mode_config_cleanup(adev_to_drm(adev));</div><div class='del'>-	adev-&gt;mode_info.mode_config_initialized = false;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_hw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	dce_v11_0_init_golden_registers(adev);</div><div class='del'>-</div><div class='del'>-	/* disable vga render */</div><div class='del'>-	dce_v11_0_set_vga_render_state(adev, false);</div><div class='del'>-	/* init dig PHYs, disp eng pll */</div><div class='del'>-	amdgpu_atombios_crtc_powergate_init(adev);</div><div class='del'>-	amdgpu_atombios_encoder_init_dig(adev);</div><div class='del'>-	if ((adev-&gt;asic_type == CHIP_POLARIS10) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_POLARIS11) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_POLARIS12) ||</div><div class='del'>-	    (adev-&gt;asic_type == CHIP_VEGAM)) {</div><div class='del'>-		amdgpu_atombios_crtc_set_dce_clock(adev, adev-&gt;clock.default_dispclk,</div><div class='del'>-						   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);</div><div class='del'>-		amdgpu_atombios_crtc_set_dce_clock(adev, 0,</div><div class='del'>-						   DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev-&gt;clock.default_dispclk);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* initialize hpd */</div><div class='del'>-	dce_v11_0_hpd_init(adev);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++) {</div><div class='del'>-		dce_v11_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dce_v11_0_pageflip_interrupt_init(adev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_hw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	dce_v11_0_hpd_fini(adev);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++) {</div><div class='del'>-		dce_v11_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dce_v11_0_pageflip_interrupt_fini(adev);</div><div class='del'>-</div><div class='del'>-	flush_delayed_work(&amp;adev-&gt;hotplug_work);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_suspend(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_display_suspend_helper(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	adev-&gt;mode_info.bl_level =</div><div class='del'>-		amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);</div><div class='del'>-</div><div class='del'>-	return dce_v11_0_hw_fini(handle);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_resume(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,</div><div class='del'>-							   adev-&gt;mode_info.bl_level);</div><div class='del'>-</div><div class='del'>-	ret = dce_v11_0_hw_init(handle);</div><div class='del'>-</div><div class='del'>-	/* turn on the BL */</div><div class='del'>-	if (adev-&gt;mode_info.bl_encoder) {</div><div class='del'>-		u8 bl_level = amdgpu_display_backlight_get_level(adev,</div><div class='del'>-								  adev-&gt;mode_info.bl_encoder);</div><div class='del'>-		amdgpu_display_backlight_set_level(adev, adev-&gt;mode_info.bl_encoder,</div><div class='del'>-						    bl_level);</div><div class='del'>-	}</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	return amdgpu_display_resume_helper(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dce_v11_0_is_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	u32 srbm_soft_reset = 0, tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (dce_v11_0_is_display_hung(adev))</div><div class='del'>-		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;</div><div class='del'>-</div><div class='del'>-	if (srbm_soft_reset) {</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-		tmp |= srbm_soft_reset;</div><div class='del'>-		dev_info(adev-&gt;dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-</div><div class='del'>-		udelay(50);</div><div class='del'>-</div><div class='del'>-		tmp &amp;= ~srbm_soft_reset;</div><div class='del'>-		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-</div><div class='del'>-		/* Wait a little for things to settle down */</div><div class='del'>-		udelay(50);</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,</div><div class='del'>-						     int crtc,</div><div class='del'>-						     enum amdgpu_interrupt_state state)</div><div class='del'>-{</div><div class='del'>-	u32 lb_interrupt_mask;</div><div class='del'>-</div><div class='del'>-	if (crtc &gt;= adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		DRM_DEBUG("invalid crtc %d\n", crtc);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (state) {</div><div class='del'>-	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);</div><div class='del'>-		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,</div><div class='del'>-						  VBLANK_INTERRUPT_MASK, 0);</div><div class='del'>-		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);</div><div class='del'>-		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,</div><div class='del'>-						  VBLANK_INTERRUPT_MASK, 1);</div><div class='del'>-		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,</div><div class='del'>-						    int crtc,</div><div class='del'>-						    enum amdgpu_interrupt_state state)</div><div class='del'>-{</div><div class='del'>-	u32 lb_interrupt_mask;</div><div class='del'>-</div><div class='del'>-	if (crtc &gt;= adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		DRM_DEBUG("invalid crtc %d\n", crtc);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (state) {</div><div class='del'>-	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);</div><div class='del'>-		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,</div><div class='del'>-						  VLINE_INTERRUPT_MASK, 0);</div><div class='del'>-		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);</div><div class='del'>-		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,</div><div class='del'>-						  VLINE_INTERRUPT_MASK, 1);</div><div class='del'>-		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,</div><div class='del'>-					struct amdgpu_irq_src *source,</div><div class='del'>-					unsigned hpd,</div><div class='del'>-					enum amdgpu_interrupt_state state)</div><div class='del'>-{</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", hpd);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (state) {</div><div class='del'>-	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);</div><div class='del'>-		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);</div><div class='del'>-		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,</div><div class='del'>-					struct amdgpu_irq_src *source,</div><div class='del'>-					unsigned type,</div><div class='del'>-					enum amdgpu_interrupt_state state)</div><div class='del'>-{</div><div class='del'>-	switch (type) {</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VBLANK1:</div><div class='del'>-		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VBLANK2:</div><div class='del'>-		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VBLANK3:</div><div class='del'>-		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VBLANK4:</div><div class='del'>-		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VBLANK5:</div><div class='del'>-		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VBLANK6:</div><div class='del'>-		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VLINE1:</div><div class='del'>-		dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VLINE2:</div><div class='del'>-		dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VLINE3:</div><div class='del'>-		dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VLINE4:</div><div class='del'>-		dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_CRTC_IRQ_VLINE5:</div><div class='del'>-		dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);</div><div class='del'>-		break;</div><div class='del'>-	 case AMDGPU_CRTC_IRQ_VLINE6:</div><div class='del'>-		dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,</div><div class='del'>-					    struct amdgpu_irq_src *src,</div><div class='del'>-					    unsigned type,</div><div class='del'>-					    enum amdgpu_interrupt_state state)</div><div class='del'>-{</div><div class='del'>-	u32 reg;</div><div class='del'>-</div><div class='del'>-	if (type &gt;= adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		DRM_ERROR("invalid pageflip crtc %d\n", type);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);</div><div class='del'>-	if (state == AMDGPU_IRQ_STATE_DISABLE)</div><div class='del'>-		WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],</div><div class='del'>-		       reg &amp; ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);</div><div class='del'>-	else</div><div class='del'>-		WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],</div><div class='del'>-		       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,</div><div class='del'>-				  struct amdgpu_irq_src *source,</div><div class='del'>-				  struct amdgpu_iv_entry *entry)</div><div class='del'>-{</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	unsigned crtc_id;</div><div class='del'>-	struct amdgpu_crtc *amdgpu_crtc;</div><div class='del'>-	struct amdgpu_flip_work *works;</div><div class='del'>-</div><div class='del'>-	crtc_id = (entry-&gt;src_id - 8) &gt;&gt; 1;</div><div class='del'>-	amdgpu_crtc = adev-&gt;mode_info.crtcs[crtc_id];</div><div class='del'>-</div><div class='del'>-	if (crtc_id &gt;= adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &amp;</div><div class='del'>-	    GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)</div><div class='del'>-		WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],</div><div class='del'>-		       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);</div><div class='del'>-</div><div class='del'>-	/* IRQ could occur when in initial stage */</div><div class='del'>-	if(amdgpu_crtc == NULL)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='del'>-	works = amdgpu_crtc-&gt;pflip_works;</div><div class='del'>-	if (amdgpu_crtc-&gt;pflip_status != AMDGPU_FLIP_SUBMITTED){</div><div class='del'>-		DRM_DEBUG_DRIVER("amdgpu_crtc-&gt;pflip_status = %d != "</div><div class='del'>-						 "AMDGPU_FLIP_SUBMITTED(%d)\n",</div><div class='del'>-						 amdgpu_crtc-&gt;pflip_status,</div><div class='del'>-						 AMDGPU_FLIP_SUBMITTED);</div><div class='del'>-		spin_unlock_irqrestore(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* page flip completed. clean up */</div><div class='del'>-	amdgpu_crtc-&gt;pflip_status = AMDGPU_FLIP_NONE;</div><div class='del'>-	amdgpu_crtc-&gt;pflip_works = NULL;</div><div class='del'>-</div><div class='del'>-	/* wakeup usersapce */</div><div class='del'>-	if(works-&gt;event)</div><div class='del'>-		drm_crtc_send_vblank_event(&amp;amdgpu_crtc-&gt;base, works-&gt;event);</div><div class='del'>-</div><div class='del'>-	spin_unlock_irqrestore(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='del'>-</div><div class='del'>-	drm_crtc_vblank_put(&amp;amdgpu_crtc-&gt;base);</div><div class='del'>-	schedule_work(&amp;works-&gt;unpin_work);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,</div><div class='del'>-				  int hpd)</div><div class='del'>-{</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", hpd);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);</div><div class='del'>-	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,</div><div class='del'>-					  int crtc)</div><div class='del'>-{</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	if (crtc &lt; 0 || crtc &gt;= adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		DRM_DEBUG("invalid crtc %d\n", crtc);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);</div><div class='del'>-	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,</div><div class='del'>-					 int crtc)</div><div class='del'>-{</div><div class='del'>-	u32 tmp;</div><div class='del'>-</div><div class='del'>-	if (crtc &lt; 0 || crtc &gt;= adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		DRM_DEBUG("invalid crtc %d\n", crtc);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);</div><div class='del'>-	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_irq_src *source,</div><div class='del'>-				struct amdgpu_iv_entry *entry)</div><div class='del'>-{</div><div class='del'>-	unsigned crtc = entry-&gt;src_id - 1;</div><div class='del'>-	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);</div><div class='del'>-	unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,</div><div class='del'>-								    crtc);</div><div class='del'>-</div><div class='del'>-	switch (entry-&gt;src_data[0]) {</div><div class='del'>-	case 0: /* vblank */</div><div class='del'>-		if (disp_int &amp; interrupt_status_offsets[crtc].vblank)</div><div class='del'>-			dce_v11_0_crtc_vblank_int_ack(adev, crtc);</div><div class='del'>-		else</div><div class='del'>-			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");</div><div class='del'>-</div><div class='del'>-		if (amdgpu_irq_enabled(adev, source, irq_type)) {</div><div class='del'>-			drm_handle_vblank(adev_to_drm(adev), crtc);</div><div class='del'>-		}</div><div class='del'>-		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);</div><div class='del'>-</div><div class='del'>-		break;</div><div class='del'>-	case 1: /* vline */</div><div class='del'>-		if (disp_int &amp; interrupt_status_offsets[crtc].vline)</div><div class='del'>-			dce_v11_0_crtc_vline_int_ack(adev, crtc);</div><div class='del'>-		else</div><div class='del'>-			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");</div><div class='del'>-</div><div class='del'>-		DRM_DEBUG("IH: D%d vline\n", crtc + 1);</div><div class='del'>-</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry-&gt;src_id, entry-&gt;src_data[0]);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,</div><div class='del'>-			     struct amdgpu_irq_src *source,</div><div class='del'>-			     struct amdgpu_iv_entry *entry)</div><div class='del'>-{</div><div class='del'>-	uint32_t disp_int, mask;</div><div class='del'>-	unsigned hpd;</div><div class='del'>-</div><div class='del'>-	if (entry-&gt;src_data[0] &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry-&gt;src_id, entry-&gt;src_data[0]);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hpd = entry-&gt;src_data[0];</div><div class='del'>-	disp_int = RREG32(interrupt_status_offsets[hpd].reg);</div><div class='del'>-	mask = interrupt_status_offsets[hpd].hpd;</div><div class='del'>-</div><div class='del'>-	if (disp_int &amp; mask) {</div><div class='del'>-		dce_v11_0_hpd_int_ack(adev, hpd);</div><div class='del'>-		schedule_delayed_work(&amp;adev-&gt;hotplug_work, 0);</div><div class='del'>-		DRM_DEBUG("IH: HPD%d\n", hpd + 1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_set_clockgating_state(void *handle,</div><div class='del'>-					  enum amd_clockgating_state state)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v11_0_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct amd_ip_funcs dce_v11_0_ip_funcs = {</div><div class='del'>-	.name = "dce_v11_0",</div><div class='del'>-	.early_init = dce_v11_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='del'>-	.sw_init = dce_v11_0_sw_init,</div><div class='del'>-	.sw_fini = dce_v11_0_sw_fini,</div><div class='del'>-	.hw_init = dce_v11_0_hw_init,</div><div class='del'>-	.hw_fini = dce_v11_0_hw_fini,</div><div class='del'>-	.suspend = dce_v11_0_suspend,</div><div class='del'>-	.resume = dce_v11_0_resume,</div><div class='del'>-	.is_idle = dce_v11_0_is_idle,</div><div class='del'>-	.wait_for_idle = dce_v11_0_wait_for_idle,</div><div class='del'>-	.soft_reset = dce_v11_0_soft_reset,</div><div class='del'>-	.set_clockgating_state = dce_v11_0_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = dce_v11_0_set_powergating_state,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,</div><div class='del'>-			  struct drm_display_mode *mode,</div><div class='del'>-			  struct drm_display_mode *adjusted_mode)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-</div><div class='del'>-	amdgpu_encoder-&gt;pixel_clock = adjusted_mode-&gt;clock;</div><div class='del'>-</div><div class='del'>-	/* need to call this here rather than in prepare() since we need some crtc info */</div><div class='del'>-	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);</div><div class='del'>-</div><div class='del'>-	/* set scaler clears this on some chips */</div><div class='del'>-	dce_v11_0_set_interleave(encoder-&gt;crtc, mode);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {</div><div class='del'>-		dce_v11_0_afmt_enable(encoder, true);</div><div class='del'>-		dce_v11_0_afmt_setmode(encoder, adjusted_mode);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(encoder-&gt;dev);</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);</div><div class='del'>-</div><div class='del'>-	if ((amdgpu_encoder-&gt;active_device &amp;</div><div class='del'>-	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||</div><div class='del'>-	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=</div><div class='del'>-	     ENCODER_OBJECT_ID_NONE)) {</div><div class='del'>-		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-		if (dig) {</div><div class='del'>-			dig-&gt;dig_encoder = dce_v11_0_pick_dig_encoder(encoder);</div><div class='del'>-			if (amdgpu_encoder-&gt;active_device &amp; ATOM_DEVICE_DFP_SUPPORT)</div><div class='del'>-				dig-&gt;afmt = adev-&gt;mode_info.afmt[dig-&gt;dig_encoder];</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_atombios_scratch_regs_lock(adev, true);</div><div class='del'>-</div><div class='del'>-	if (connector) {</div><div class='del'>-		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='del'>-</div><div class='del'>-		/* select the clock/data port if it uses a router */</div><div class='del'>-		if (amdgpu_connector-&gt;router.cd_valid)</div><div class='del'>-			amdgpu_i2c_router_select_cd_port(amdgpu_connector);</div><div class='del'>-</div><div class='del'>-		/* turn eDP panel on for mode set */</div><div class='del'>-		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='del'>-			amdgpu_atombios_encoder_set_edp_panel_power(connector,</div><div class='del'>-							     ATOM_TRANSMITTER_ACTION_POWER_ON);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* this is needed for the pll/ss setup to work correctly in some cases */</div><div class='del'>-	amdgpu_atombios_encoder_set_crtc_source(encoder);</div><div class='del'>-	/* set up the FMT blocks */</div><div class='del'>-	dce_v11_0_program_fmt(encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-</div><div class='del'>-	/* need to call this here as we need the crtc set up */</div><div class='del'>-	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);</div><div class='del'>-	amdgpu_atombios_scratch_regs_lock(adev, false);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	struct amdgpu_encoder_atom_dig *dig;</div><div class='del'>-</div><div class='del'>-	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_atombios_encoder_is_digital(encoder)) {</div><div class='del'>-		if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)</div><div class='del'>-			dce_v11_0_afmt_enable(encoder, false);</div><div class='del'>-		dig = amdgpu_encoder-&gt;enc_priv;</div><div class='del'>-		dig-&gt;dig_encoder = -1;</div><div class='del'>-	}</div><div class='del'>-	amdgpu_encoder-&gt;active_device = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* these are handled by the primary encoders */</div><div class='del'>-static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_ext_commit(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-dce_v11_0_ext_mode_set(struct drm_encoder *encoder,</div><div class='del'>-		      struct drm_display_mode *mode,</div><div class='del'>-		      struct drm_display_mode *adjusted_mode)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_ext_disable(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {</div><div class='del'>-	.dpms = dce_v11_0_ext_dpms,</div><div class='del'>-	.prepare = dce_v11_0_ext_prepare,</div><div class='del'>-	.mode_set = dce_v11_0_ext_mode_set,</div><div class='del'>-	.commit = dce_v11_0_ext_commit,</div><div class='del'>-	.disable = dce_v11_0_ext_disable,</div><div class='del'>-	/* no detect for TMDS/LVDS yet */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {</div><div class='del'>-	.dpms = amdgpu_atombios_encoder_dpms,</div><div class='del'>-	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,</div><div class='del'>-	.prepare = dce_v11_0_encoder_prepare,</div><div class='del'>-	.mode_set = dce_v11_0_encoder_mode_set,</div><div class='del'>-	.commit = dce_v11_0_encoder_commit,</div><div class='del'>-	.disable = dce_v11_0_encoder_disable,</div><div class='del'>-	.detect = amdgpu_atombios_encoder_dig_detect,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {</div><div class='del'>-	.dpms = amdgpu_atombios_encoder_dpms,</div><div class='del'>-	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,</div><div class='del'>-	.prepare = dce_v11_0_encoder_prepare,</div><div class='del'>-	.mode_set = dce_v11_0_encoder_mode_set,</div><div class='del'>-	.commit = dce_v11_0_encoder_commit,</div><div class='del'>-	.detect = amdgpu_atombios_encoder_dac_detect,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-	if (amdgpu_encoder-&gt;devices &amp; (ATOM_DEVICE_LCD_SUPPORT))</div><div class='del'>-		amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);</div><div class='del'>-	kfree(amdgpu_encoder-&gt;enc_priv);</div><div class='del'>-	drm_encoder_cleanup(encoder);</div><div class='del'>-	kfree(amdgpu_encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {</div><div class='del'>-	.destroy = dce_v11_0_encoder_destroy,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_encoder_add(struct amdgpu_device *adev,</div><div class='del'>-				 uint32_t encoder_enum,</div><div class='del'>-				 uint32_t supported_device,</div><div class='del'>-				 u16 caps)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *dev = adev_to_drm(adev);</div><div class='del'>-	struct drm_encoder *encoder;</div><div class='del'>-	struct amdgpu_encoder *amdgpu_encoder;</div><div class='del'>-</div><div class='del'>-	/* see if we already added it */</div><div class='del'>-	list_for_each_entry(encoder, &amp;dev-&gt;mode_config.encoder_list, head) {</div><div class='del'>-		amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='del'>-		if (amdgpu_encoder-&gt;encoder_enum == encoder_enum) {</div><div class='del'>-			amdgpu_encoder-&gt;devices |= supported_device;</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* add a new one */</div><div class='del'>-	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);</div><div class='del'>-	if (!amdgpu_encoder)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	encoder = &amp;amdgpu_encoder-&gt;base;</div><div class='del'>-	switch (adev-&gt;mode_info.num_crtc) {</div><div class='del'>-	case 1:</div><div class='del'>-		encoder-&gt;possible_crtcs = 0x1;</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-	default:</div><div class='del'>-		encoder-&gt;possible_crtcs = 0x3;</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		encoder-&gt;possible_crtcs = 0x7;</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		encoder-&gt;possible_crtcs = 0xf;</div><div class='del'>-		break;</div><div class='del'>-	case 5:</div><div class='del'>-		encoder-&gt;possible_crtcs = 0x1f;</div><div class='del'>-		break;</div><div class='del'>-	case 6:</div><div class='del'>-		encoder-&gt;possible_crtcs = 0x3f;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_encoder-&gt;enc_priv = NULL;</div><div class='del'>-</div><div class='del'>-	amdgpu_encoder-&gt;encoder_enum = encoder_enum;</div><div class='del'>-	amdgpu_encoder-&gt;encoder_id = (encoder_enum &amp; OBJECT_ID_MASK) &gt;&gt; OBJECT_ID_SHIFT;</div><div class='del'>-	amdgpu_encoder-&gt;devices = supported_device;</div><div class='del'>-	amdgpu_encoder-&gt;rmx_type = RMX_OFF;</div><div class='del'>-	amdgpu_encoder-&gt;underscan_type = UNDERSCAN_OFF;</div><div class='del'>-	amdgpu_encoder-&gt;is_ext_encoder = false;</div><div class='del'>-	amdgpu_encoder-&gt;caps = caps;</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_encoder-&gt;encoder_id) {</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:</div><div class='del'>-		drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-				 DRM_MODE_ENCODER_DAC, NULL);</div><div class='del'>-		drm_encoder_helper_add(encoder, &amp;dce_v11_0_dac_helper_funcs);</div><div class='del'>-		break;</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:</div><div class='del'>-	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:</div><div class='del'>-		if (amdgpu_encoder-&gt;devices &amp; (ATOM_DEVICE_LCD_SUPPORT)) {</div><div class='del'>-			amdgpu_encoder-&gt;rmx_type = RMX_FULL;</div><div class='del'>-			drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-					 DRM_MODE_ENCODER_LVDS, NULL);</div><div class='del'>-			amdgpu_encoder-&gt;enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);</div><div class='del'>-		} else if (amdgpu_encoder-&gt;devices &amp; (ATOM_DEVICE_CRT_SUPPORT)) {</div><div class='del'>-			drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-					 DRM_MODE_ENCODER_DAC, NULL);</div><div class='del'>-			amdgpu_encoder-&gt;enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);</div><div class='del'>-		} else {</div><div class='del'>-			drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-					 DRM_MODE_ENCODER_TMDS, NULL);</div><div class='del'>-			amdgpu_encoder-&gt;enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);</div><div class='del'>-		}</div><div class='del'>-		drm_encoder_helper_add(encoder, &amp;dce_v11_0_dig_helper_funcs);</div><div class='del'>-		break;</div><div class='del'>-	case ENCODER_OBJECT_ID_SI170B:</div><div class='del'>-	case ENCODER_OBJECT_ID_CH7303:</div><div class='del'>-	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:</div><div class='del'>-	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:</div><div class='del'>-	case ENCODER_OBJECT_ID_TITFP513:</div><div class='del'>-	case ENCODER_OBJECT_ID_VT1623:</div><div class='del'>-	case ENCODER_OBJECT_ID_HDMI_SI1930:</div><div class='del'>-	case ENCODER_OBJECT_ID_TRAVIS:</div><div class='del'>-	case ENCODER_OBJECT_ID_NUTMEG:</div><div class='del'>-		/* these are handled by the primary encoders */</div><div class='del'>-		amdgpu_encoder-&gt;is_ext_encoder = true;</div><div class='del'>-		if (amdgpu_encoder-&gt;devices &amp; (ATOM_DEVICE_LCD_SUPPORT))</div><div class='del'>-			drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-					 DRM_MODE_ENCODER_LVDS, NULL);</div><div class='del'>-		else if (amdgpu_encoder-&gt;devices &amp; (ATOM_DEVICE_CRT_SUPPORT))</div><div class='del'>-			drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-					 DRM_MODE_ENCODER_DAC, NULL);</div><div class='del'>-		else</div><div class='del'>-			drm_encoder_init(dev, encoder, &amp;dce_v11_0_encoder_funcs,</div><div class='del'>-					 DRM_MODE_ENCODER_TMDS, NULL);</div><div class='del'>-		drm_encoder_helper_add(encoder, &amp;dce_v11_0_ext_helper_funcs);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {</div><div class='del'>-	.bandwidth_update = &amp;dce_v11_0_bandwidth_update,</div><div class='del'>-	.vblank_get_counter = &amp;dce_v11_0_vblank_get_counter,</div><div class='del'>-	.backlight_set_level = &amp;amdgpu_atombios_encoder_set_backlight_level,</div><div class='del'>-	.backlight_get_level = &amp;amdgpu_atombios_encoder_get_backlight_level,</div><div class='del'>-	.hpd_sense = &amp;dce_v11_0_hpd_sense,</div><div class='del'>-	.hpd_set_polarity = &amp;dce_v11_0_hpd_set_polarity,</div><div class='del'>-	.hpd_get_gpio_reg = &amp;dce_v11_0_hpd_get_gpio_reg,</div><div class='del'>-	.page_flip = &amp;dce_v11_0_page_flip,</div><div class='del'>-	.page_flip_get_scanoutpos = &amp;dce_v11_0_crtc_get_scanoutpos,</div><div class='del'>-	.add_encoder = &amp;dce_v11_0_encoder_add,</div><div class='del'>-	.add_connector = &amp;amdgpu_connector_add,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	adev-&gt;mode_info.funcs = &amp;dce_v11_0_display_funcs;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {</div><div class='del'>-	.set = dce_v11_0_set_crtc_irq_state,</div><div class='del'>-	.process = dce_v11_0_crtc_irq,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {</div><div class='del'>-	.set = dce_v11_0_set_pageflip_irq_state,</div><div class='del'>-	.process = dce_v11_0_pageflip_irq,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {</div><div class='del'>-	.set = dce_v11_0_set_hpd_irq_state,</div><div class='del'>-	.process = dce_v11_0_hpd_irq,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	if (adev-&gt;mode_info.num_crtc &gt; 0)</div><div class='del'>-		adev-&gt;crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev-&gt;mode_info.num_crtc;</div><div class='del'>-	else</div><div class='del'>-		adev-&gt;crtc_irq.num_types = 0;</div><div class='del'>-	adev-&gt;crtc_irq.funcs = &amp;dce_v11_0_crtc_irq_funcs;</div><div class='del'>-</div><div class='del'>-	adev-&gt;pageflip_irq.num_types = adev-&gt;mode_info.num_crtc;</div><div class='del'>-	adev-&gt;pageflip_irq.funcs = &amp;dce_v11_0_pageflip_irq_funcs;</div><div class='del'>-</div><div class='del'>-	adev-&gt;hpd_irq.num_types = adev-&gt;mode_info.num_hpd;</div><div class='del'>-	adev-&gt;hpd_irq.funcs = &amp;dce_v11_0_hpd_irq_funcs;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-const struct amdgpu_ip_block_version dce_v11_0_ip_block =</div><div class='del'>-{</div><div class='del'>-	.type = AMD_IP_BLOCK_TYPE_DCE,</div><div class='del'>-	.major = 11,</div><div class='del'>-	.minor = 0,</div><div class='del'>-	.rev = 0,</div><div class='del'>-	.funcs = &amp;dce_v11_0_ip_funcs,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-const struct amdgpu_ip_block_version dce_v11_2_ip_block =</div><div class='del'>-{</div><div class='del'>-	.type = AMD_IP_BLOCK_TYPE_DCE,</div><div class='del'>-	.major = 11,</div><div class='del'>-	.minor = 2,</div><div class='del'>-	.rev = 0,</div><div class='del'>-	.funcs = &amp;dce_v11_0_ip_funcs,</div><div class='del'>-};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c<br/>index 60d40201fdd1..acc887a58518 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/dce_v6_0.c</a></div><div class='hunk'>@@ -40,18 +40,25 @@</div><div class='ctx'> #include "amdgpu_connectors.h"</div><div class='ctx'> #include "amdgpu_display.h"</div><div class='ctx'> </div><div class='add'>+#include "dce_v6_0.h"</div><div class='add'>+#include "sid.h"</div><div class='add'>+</div><div class='ctx'> #include "bif/bif_3_0_d.h"</div><div class='ctx'> #include "bif/bif_3_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "oss/oss_1_0_d.h"</div><div class='ctx'> #include "oss/oss_1_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "gca/gfx_6_0_d.h"</div><div class='ctx'> #include "gca/gfx_6_0_sh_mask.h"</div><div class='add'>+#include "gca/gfx_7_2_enum.h"</div><div class='add'>+</div><div class='ctx'> #include "gmc/gmc_6_0_d.h"</div><div class='ctx'> #include "gmc/gmc_6_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "dce/dce_6_0_d.h"</div><div class='ctx'> #include "dce/dce_6_0_sh_mask.h"</div><div class='del'>-#include "gca/gfx_7_2_enum.h"</div><div class='del'>-#include "dce_v6_0.h"</div><div class='add'>+</div><div class='ctx'> #include "si_enums.h"</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);</div><div class='hunk'>@@ -59,31 +66,31 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> static const u32 crtc_offsets[6] =</div><div class='ctx'> {</div><div class='del'>-	SI_CRTC0_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC1_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC2_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC3_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC4_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC5_REGISTER_OFFSET</div><div class='add'>+	CRTC0_REGISTER_OFFSET,</div><div class='add'>+	CRTC1_REGISTER_OFFSET,</div><div class='add'>+	CRTC2_REGISTER_OFFSET,</div><div class='add'>+	CRTC3_REGISTER_OFFSET,</div><div class='add'>+	CRTC4_REGISTER_OFFSET,</div><div class='add'>+	CRTC5_REGISTER_OFFSET</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const u32 hpd_offsets[] =</div><div class='ctx'> {</div><div class='del'>-	mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,</div><div class='del'>-	mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,</div><div class='del'>-	mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,</div><div class='del'>-	mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,</div><div class='del'>-	mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,</div><div class='del'>-	mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,</div><div class='add'>+	HPD0_REGISTER_OFFSET,</div><div class='add'>+	HPD1_REGISTER_OFFSET,</div><div class='add'>+	HPD2_REGISTER_OFFSET,</div><div class='add'>+	HPD3_REGISTER_OFFSET,</div><div class='add'>+	HPD4_REGISTER_OFFSET,</div><div class='add'>+	HPD5_REGISTER_OFFSET</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t dig_offsets[] = {</div><div class='del'>-	SI_CRTC0_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC1_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC2_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC3_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC4_REGISTER_OFFSET,</div><div class='del'>-	SI_CRTC5_REGISTER_OFFSET,</div><div class='add'>+	CRTC0_REGISTER_OFFSET,</div><div class='add'>+	CRTC1_REGISTER_OFFSET,</div><div class='add'>+	CRTC2_REGISTER_OFFSET,</div><div class='add'>+	CRTC3_REGISTER_OFFSET,</div><div class='add'>+	CRTC4_REGISTER_OFFSET,</div><div class='add'>+	CRTC5_REGISTER_OFFSET,</div><div class='ctx'> 	(0x13830 - 0x7030) &gt;&gt; 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -206,9 +213,9 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,</div><div class='ctx'> 	/* update the scanout addresses */</div><div class='ctx'> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       upper_32_bits(crtc_base));</div><div class='add'>+	/* writing to the low address triggers the update */</div><div class='ctx'> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       (u32)crtc_base);</div><div class='del'>-</div><div class='ctx'> 	/* post the write */</div><div class='ctx'> 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset);</div><div class='ctx'> }</div><div class='hunk'>@@ -218,11 +225,11 @@ static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,</div><div class='ctx'> {</div><div class='ctx'> 	if ((crtc &lt; 0) || (crtc &gt;= adev-&gt;mode_info.num_crtc))</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);</div><div class='ctx'> 	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -242,7 +249,8 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,</div><div class='ctx'> 	if (hpd &gt;= adev-&gt;mode_info.num_hpd)</div><div class='ctx'> 		return connected;</div><div class='ctx'> </div><div class='del'>-	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &amp; DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)</div><div class='add'>+	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &amp;</div><div class='add'>+	    DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)</div><div class='ctx'> 		connected = true;</div><div class='ctx'> </div><div class='ctx'> 	return connected;</div><div class='hunk'>@@ -279,7 +287,7 @@ static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev,</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", hpd);</div><div class='add'>+		DRM_DEBUG("invalid hpd %d\n", hpd);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -370,13 +378,41 @@ static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)</div><div class='ctx'> 	return mmDC_GPIO_HPD_A;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool dce_v6_0_is_display_hung(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 crtc_hung = 0;</div><div class='add'>+	u32 crtc_status[6];</div><div class='add'>+	u32 i, j, tmp;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='add'>+		if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &amp; CRTC_CONTROL__CRTC_MASTER_EN_MASK) {</div><div class='add'>+			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);</div><div class='add'>+			crtc_hung |= (1 &lt;&lt; i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; 10; j++) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='add'>+			if (crtc_hung &amp; (1 &lt;&lt; i)) {</div><div class='add'>+				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);</div><div class='add'>+				if (tmp != crtc_status[i])</div><div class='add'>+					crtc_hung &amp;= ~(1 &lt;&lt; i);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (crtc_hung == 0)</div><div class='add'>+			return false;</div><div class='add'>+		udelay(100);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,</div><div class='ctx'> 					  bool render)</div><div class='ctx'> {</div><div class='ctx'> 	if (!render)</div><div class='ctx'> 		WREG32(mmVGA_RENDER_CONTROL,</div><div class='del'>-			RREG32(mmVGA_RENDER_CONTROL) &amp; VGA_VSTATUS_CNTL);</div><div class='del'>-</div><div class='add'>+		       RREG32(mmVGA_RENDER_CONTROL) &amp; ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)</div><div class='hunk'>@@ -419,7 +455,6 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_program_fmt(struct drm_encoder *encoder)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct drm_device *dev = encoder-&gt;dev;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='hunk'>@@ -895,8 +930,8 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,</div><div class='ctx'> 		wm_high.dram_channels = dram_channels;</div><div class='ctx'> 		wm_high.num_heads = num_heads;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pm.dpm_enabled) {</div><div class='ctx'> 		/* watermark for low clocks */</div><div class='add'>+		if (adev-&gt;pm.dpm_enabled) {</div><div class='ctx'> 			wm_low.yclk =</div><div class='ctx'> 				amdgpu_dpm_get_mclk(adev, true) * 10;</div><div class='ctx'> 			wm_low.sclk =</div><div class='hunk'>@@ -976,16 +1011,16 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,</div><div class='ctx'> 	/* select wm A */</div><div class='ctx'> 	arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc-&gt;crtc_offset);</div><div class='ctx'> 	tmp = arb_control3;</div><div class='del'>-	tmp &amp;= ~LATENCY_WATERMARK_MASK(3);</div><div class='del'>-	tmp |= LATENCY_WATERMARK_MASK(1);</div><div class='add'>+	tmp &amp;= ~(3 &lt;&lt; DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);</div><div class='add'>+	tmp |= (1 &lt;&lt; DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);</div><div class='ctx'> 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='ctx'> 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       ((latency_watermark_a &lt;&lt; DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT)  |</div><div class='ctx'> 		(line_time &lt;&lt; DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));</div><div class='ctx'> 	/* select wm B */</div><div class='ctx'> 	tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc-&gt;crtc_offset);</div><div class='del'>-	tmp &amp;= ~LATENCY_WATERMARK_MASK(3);</div><div class='del'>-	tmp |= LATENCY_WATERMARK_MASK(2);</div><div class='add'>+	tmp &amp;= ~(3 &lt;&lt; DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);</div><div class='add'>+	tmp |= (2 &lt;&lt; DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT);</div><div class='ctx'> 	WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc-&gt;crtc_offset, tmp);</div><div class='ctx'> 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       ((latency_watermark_b &lt;&lt; DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |</div><div class='hunk'>@@ -999,13 +1034,26 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	/* save values for DPM */</div><div class='ctx'> 	amdgpu_crtc-&gt;line_time = line_time;</div><div class='del'>-	amdgpu_crtc-&gt;wm_high = latency_watermark_a;</div><div class='ctx'> </div><div class='ctx'> 	/* Save number of lines the linebuffer leads before the scanout */</div><div class='ctx'> 	amdgpu_crtc-&gt;lb_vblank_lead_lines = lb_vblank_lead_lines;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* watermark setup */</div><div class='add'>+/**</div><div class='add'>+ * dce_v6_0_line_buffer_adjust - Set up the line buffer</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @amdgpu_crtc: the selected display controller</div><div class='add'>+ * @mode: the current display mode on the selected display</div><div class='add'>+ * controller</div><div class='add'>+ * @other_mode: the display mode of another display controller</div><div class='add'>+ *              that may be sharing the line buffer</div><div class='add'>+ *</div><div class='add'>+ * Setup up the line buffer allocation for</div><div class='add'>+ * the selected display controller (CIK).</div><div class='add'>+ * Returns the line buffer size in pixels.</div><div class='add'>+ */</div><div class='ctx'> static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,</div><div class='ctx'> 				   struct amdgpu_crtc *amdgpu_crtc,</div><div class='ctx'> 				   struct drm_display_mode *mode,</div><div class='hunk'>@@ -1040,7 +1088,7 @@ static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       DC_LB_MEMORY_CONFIG(tmp));</div><div class='add'>+	       (tmp &lt;&lt; DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT));</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,</div><div class='ctx'> 	       (buffer_alloc &lt;&lt; PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));</div><div class='hunk'>@@ -1217,7 +1265,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &amp;sadb);</div><div class='add'>+	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector-&gt;edid, &amp;sadb);</div><div class='ctx'> 	if (sad_count &lt; 0) {</div><div class='ctx'> 		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);</div><div class='ctx'> 		sad_count = 0;</div><div class='hunk'>@@ -1257,6 +1305,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='ctx'> 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder-&gt;enc_priv;</div><div class='add'>+	u32 offset;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	struct drm_connector_list_iter iter;</div><div class='ctx'> 	struct amdgpu_connector *amdgpu_connector = NULL;</div><div class='hunk'>@@ -1278,6 +1327,11 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	if (!dig || !dig-&gt;afmt || !dig-&gt;afmt-&gt;pin)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	offset = dig-&gt;afmt-&gt;pin-&gt;offset;</div><div class='add'>+</div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='ctx'> 		if (connector-&gt;encoder == encoder) {</div><div class='hunk'>@@ -1292,14 +1346,14 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &amp;sads);</div><div class='add'>+	sad_count = drm_edid_to_sad(amdgpu_connector-&gt;edid, &amp;sads);</div><div class='ctx'> 	if (sad_count &lt; 0)</div><div class='ctx'> 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);</div><div class='ctx'> 	if (sad_count &lt;= 0)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(eld_reg_to_type); i++) {</div><div class='del'>-		u32 tmp = 0;</div><div class='add'>+		u32 value = 0;</div><div class='ctx'> 		u8 stereo_freqs = 0;</div><div class='ctx'> 		int max_channels = -1;</div><div class='ctx'> 		int j;</div><div class='hunk'>@@ -1309,12 +1363,12 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> 			if (sad-&gt;format == eld_reg_to_type[i][1]) {</div><div class='ctx'> 				if (sad-&gt;channels &gt; max_channels) {</div><div class='del'>-					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-							MAX_CHANNELS, sad-&gt;channels);</div><div class='del'>-					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-							DESCRIPTOR_BYTE_2, sad-&gt;byte2);</div><div class='del'>-					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-							SUPPORTED_FREQUENCIES, sad-&gt;freq);</div><div class='add'>+					value = (sad-&gt;channels &lt;&lt;</div><div class='add'>+						AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |</div><div class='add'>+					       (sad-&gt;byte2 &lt;&lt;</div><div class='add'>+						AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |</div><div class='add'>+					       (sad-&gt;freq &lt;&lt;</div><div class='add'>+						AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);</div><div class='ctx'> 					max_channels = sad-&gt;channels;</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='hunk'>@@ -1325,13 +1379,13 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,</div><div class='del'>-				SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);</div><div class='del'>-		WREG32_AUDIO_ENDPT(dig-&gt;afmt-&gt;pin-&gt;offset, eld_reg_to_type[i][0], tmp);</div><div class='add'>+		value |= (stereo_freqs &lt;&lt;</div><div class='add'>+			AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);</div><div class='add'>+</div><div class='add'>+		WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(sads);</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_audio_enable(struct amdgpu_device *adev,</div><div class='hunk'>@@ -1347,13 +1401,13 @@ static void dce_v6_0_audio_enable(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static const u32 pin_offsets[7] =</div><div class='ctx'> {</div><div class='del'>-	(0x1780 - 0x1780),</div><div class='del'>-	(0x1786 - 0x1780),</div><div class='del'>-	(0x178c - 0x1780),</div><div class='del'>-	(0x1792 - 0x1780),</div><div class='del'>-	(0x1798 - 0x1780),</div><div class='del'>-	(0x179d - 0x1780),</div><div class='del'>-	(0x17a4 - 0x1780),</div><div class='add'>+	AUD0_REGISTER_OFFSET,</div><div class='add'>+	AUD1_REGISTER_OFFSET,</div><div class='add'>+	AUD2_REGISTER_OFFSET,</div><div class='add'>+	AUD3_REGISTER_OFFSET,</div><div class='add'>+	AUD4_REGISTER_OFFSET,</div><div class='add'>+	AUD5_REGISTER_OFFSET,</div><div class='add'>+	AUD6_REGISTER_OFFSET,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int dce_v6_0_audio_init(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1386,6 +1440,8 @@ static int dce_v6_0_audio_init(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;mode_info.audio.pin[i].connected = false;</div><div class='ctx'> 		adev-&gt;mode_info.audio.pin[i].offset = pin_offsets[i];</div><div class='ctx'> 		adev-&gt;mode_info.audio.pin[i].id = i;</div><div class='add'>+		/* disable audio.  it will be set up later */</div><div class='add'>+		/* XXX remove once we switch to ip funcs */</div><div class='ctx'> 		dce_v6_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1394,17 +1450,12 @@ static int dce_v6_0_audio_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_audio_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='ctx'> 	if (!amdgpu_audio)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mode_info.audio.enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++)</div><div class='del'>-		dce_v6_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-</div><div class='ctx'> 	adev-&gt;mode_info.audio.enabled = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1835,7 +1886,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> 	struct amdgpu_bo *abo;</div><div class='ctx'> 	uint64_t fb_location, tiling_flags;</div><div class='ctx'> 	uint32_t fb_format, fb_pitch_pixels, pipe_config;</div><div class='del'>-	u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);</div><div class='add'>+	u32 fb_swap = (GRPH_ENDIAN_NONE &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> 	u32 viewport_w, viewport_h;</div><div class='ctx'> 	int r;</div><div class='ctx'> 	bool bypass_lut = false;</div><div class='hunk'>@@ -1861,6 +1912,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	if (!atomic) {</div><div class='add'>+		abo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 		if (unlikely(r != 0)) {</div><div class='ctx'> 			amdgpu_bo_unreserve(abo);</div><div class='hunk'>@@ -1874,76 +1926,76 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	switch (target_fb-&gt;format-&gt;format) {</div><div class='ctx'> 	case DRM_FORMAT_C8:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_INDEXED));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_8BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_INDEXED &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_XRGB4444:</div><div class='ctx'> 	case DRM_FORMAT_ARGB4444:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_ARGB4444));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_16BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_ARGB4444 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN16 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_XRGB1555:</div><div class='ctx'> 	case DRM_FORMAT_ARGB1555:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_ARGB1555));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_16BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_ARGB1555 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN16 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_BGRX5551:</div><div class='ctx'> 	case DRM_FORMAT_BGRA5551:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_BGRA5551));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_16BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_BGRA5551 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN16 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_RGB565:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_ARGB565));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_16BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_ARGB565 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN16 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_XRGB8888:</div><div class='ctx'> 	case DRM_FORMAT_ARGB8888:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_ARGB8888));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_32BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_ARGB8888 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN32 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_XRGB2101010:</div><div class='ctx'> 	case DRM_FORMAT_ARGB2101010:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_32BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_ARGB2101010 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN32 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */</div><div class='ctx'> 		bypass_lut = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_BGRX1010102:</div><div class='ctx'> 	case DRM_FORMAT_BGRA1010102:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_32BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_BGRA1010102 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);</div><div class='add'>+		fb_swap = (GRPH_ENDIAN_8IN32 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */</div><div class='ctx'> 		bypass_lut = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_FORMAT_XBGR8888:</div><div class='ctx'> 	case DRM_FORMAT_ABGR8888:</div><div class='del'>-		fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |</div><div class='del'>-			     GRPH_FORMAT(GRPH_FORMAT_ARGB8888));</div><div class='del'>-		fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) |</div><div class='del'>-			   GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R));</div><div class='add'>+		fb_format = ((GRPH_DEPTH_32BPP &lt;&lt; GRPH_CONTROL__GRPH_DEPTH__SHIFT) |</div><div class='add'>+			     (GRPH_FORMAT_ARGB8888 &lt;&lt; GRPH_CONTROL__GRPH_FORMAT__SHIFT));</div><div class='add'>+		fb_swap = ((GRPH_RED_SEL_B &lt;&lt; GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |</div><div class='add'>+			   (GRPH_BLUE_SEL_R &lt;&lt; GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);</div><div class='add'>+		fb_swap |= (GRPH_ENDIAN_8IN32 &lt;&lt; GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);</div><div class='ctx'> #endif</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1961,18 +2013,18 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);</div><div class='ctx'> 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);</div><div class='ctx'> </div><div class='del'>-		fb_format |= GRPH_NUM_BANKS(num_banks);</div><div class='del'>-		fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);</div><div class='del'>-		fb_format |= GRPH_TILE_SPLIT(tile_split);</div><div class='del'>-		fb_format |= GRPH_BANK_WIDTH(bankw);</div><div class='del'>-		fb_format |= GRPH_BANK_HEIGHT(bankh);</div><div class='del'>-		fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);</div><div class='add'>+		fb_format |= (num_banks &lt;&lt; GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);</div><div class='add'>+		fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 &lt;&lt; GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);</div><div class='add'>+		fb_format |= (tile_split &lt;&lt; GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);</div><div class='add'>+		fb_format |= (bankw &lt;&lt; GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);</div><div class='add'>+		fb_format |= (bankh &lt;&lt; GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);</div><div class='add'>+		fb_format |= (mtaspect &lt;&lt; GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);</div><div class='ctx'> 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {</div><div class='del'>-		fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);</div><div class='add'>+		fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 &lt;&lt; GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);</div><div class='del'>-	fb_format |= GRPH_PIPE_CONFIG(pipe_config);</div><div class='add'>+	fb_format |= (pipe_config &lt;&lt; GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);</div><div class='ctx'> </div><div class='ctx'> 	dce_v6_0_vga_enable(crtc, false);</div><div class='ctx'> </div><div class='hunk'>@@ -1988,7 +2040,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       (u32)fb_location &amp; GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);</div><div class='ctx'> 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       (u32) fb_location &amp; GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);</div><div class='add'>+	       (u32) fb_location &amp; GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);</div><div class='ctx'> 	WREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset, fb_format);</div><div class='ctx'> 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc-&gt;crtc_offset, fb_swap);</div><div class='ctx'> </div><div class='hunk'>@@ -2056,14 +2108,13 @@ static void dce_v6_0_set_interleave(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE)</div><div class='ctx'> 		WREG32(mmDATA_FORMAT + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-		       INTERLEAVE_EN);</div><div class='add'>+			DATA_FORMAT__INTERLEAVE_EN_MASK);</div><div class='ctx'> 	else</div><div class='ctx'> 		WREG32(mmDATA_FORMAT + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> 	struct drm_device *dev = crtc-&gt;dev;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='hunk'>@@ -2073,15 +2124,15 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)</div><div class='ctx'> 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc-&gt;crtc_id);</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((0 &lt;&lt; INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |</div><div class='del'>-		(0 &lt;&lt; INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));</div><div class='add'>+	       ((INPUT_CSC_BYPASS &lt;&lt; INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |</div><div class='add'>+		(INPUT_CSC_BYPASS &lt;&lt; INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));</div><div class='ctx'> 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);</div><div class='ctx'> 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);</div><div class='ctx'> 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((0 &lt;&lt; INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |</div><div class='del'>-		(0 &lt;&lt; INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));</div><div class='add'>+	       ((INPUT_GAMMA_USE_LUT &lt;&lt; INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |</div><div class='add'>+		(INPUT_GAMMA_USE_LUT &lt;&lt; INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -2108,19 +2159,19 @@ static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((0 &lt;&lt; DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |</div><div class='del'>-		(0 &lt;&lt; DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |</div><div class='del'>-		ICON_DEGAMMA_MODE(0) |</div><div class='del'>-		(0 &lt;&lt; DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));</div><div class='add'>+	       ((DEGAMMA_BYPASS &lt;&lt; DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |</div><div class='add'>+		(DEGAMMA_BYPASS &lt;&lt; DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |</div><div class='add'>+		(DEGAMMA_BYPASS &lt;&lt; DEGAMMA_CONTROL__ICON_DEGAMMA_MODE__SHIFT) |</div><div class='add'>+		(DEGAMMA_BYPASS &lt;&lt; DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));</div><div class='ctx'> 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((0 &lt;&lt; GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |</div><div class='del'>-		(0 &lt;&lt; GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));</div><div class='add'>+	       ((GAMUT_REMAP_BYPASS &lt;&lt; GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |</div><div class='add'>+		(GAMUT_REMAP_BYPASS &lt;&lt; GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));</div><div class='ctx'> 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((0 &lt;&lt; REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |</div><div class='del'>-		(0 &lt;&lt; REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));</div><div class='add'>+	       ((REGAMMA_BYPASS &lt;&lt; REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |</div><div class='add'>+		(REGAMMA_BYPASS &lt;&lt; REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));</div><div class='ctx'> 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='del'>-	       ((0 &lt;&lt; OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |</div><div class='del'>-		(0 &lt;&lt; OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));</div><div class='add'>+	       ((OUTPUT_CSC_BYPASS &lt;&lt; OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |</div><div class='add'>+		(OUTPUT_CSC_BYPASS &lt;&lt; OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));</div><div class='ctx'> 	/* XXX match this to the depth of the crtc fmt block, move to modeset? */</div><div class='ctx'> 	WREG32(0x1a50 + amdgpu_crtc-&gt;crtc_offset, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -2215,8 +2266,6 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)</div><div class='ctx'> 	WREG32(mmCUR_CONTROL + amdgpu_crtc-&gt;crtc_offset,</div><div class='ctx'> 	       (CURSOR_24_8_PRE_MULT &lt;&lt; CUR_CONTROL__CURSOR_MODE__SHIFT) |</div><div class='ctx'> 	       (CURSOR_URGENT_1_2 &lt;&lt; CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_show_cursor(struct drm_crtc *crtc)</div><div class='hunk'>@@ -2233,7 +2282,6 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc)</div><div class='ctx'> 	       CUR_CONTROL__CURSOR_EN_MASK |</div><div class='ctx'> 	       (CURSOR_24_8_PRE_MULT &lt;&lt; CUR_CONTROL__CURSOR_MODE__SHIFT) |</div><div class='ctx'> 	       (CURSOR_URGENT_1_2 &lt;&lt; CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,</div><div class='hunk'>@@ -2321,6 +2369,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	aobj-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 	ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 	amdgpu_bo_unreserve(aobj);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2543,7 +2592,6 @@ static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,</div><div class='ctx'> 				     const struct drm_display_mode *mode,</div><div class='ctx'> 				     struct drm_display_mode *adjusted_mode)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> 	struct drm_device *dev = crtc-&gt;dev;</div><div class='ctx'> 	struct drm_encoder *encoder;</div><div class='hunk'>@@ -2600,6 +2648,32 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {</div><div class='ctx'> 	.get_scanout_position = amdgpu_crtc_get_scanout_position,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void dce_v6_0_panic_flush(struct drm_plane *plane)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	struct amdgpu_crtc *amdgpu_crtc;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	uint32_t fb_format;</div><div class='add'>+</div><div class='add'>+	if (!plane-&gt;fb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fb = plane-&gt;fb;</div><div class='add'>+	amdgpu_crtc = to_amdgpu_crtc(plane-&gt;crtc);</div><div class='add'>+	adev = drm_to_adev(fb-&gt;dev);</div><div class='add'>+</div><div class='add'>+	/* Disable DC tiling */</div><div class='add'>+	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='add'>+	fb_format &amp;= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK;</div><div class='add'>+	WREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset, fb_format);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_funcs = {</div><div class='add'>+	.get_scanout_buffer = amdgpu_display_get_scanout_buffer,</div><div class='add'>+	.panic_flush = dce_v6_0_panic_flush,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc;</div><div class='hunk'>@@ -2627,13 +2701,14 @@ static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='ctx'> 	amdgpu_crtc-&gt;encoder = NULL;</div><div class='ctx'> 	amdgpu_crtc-&gt;connector = NULL;</div><div class='ctx'> 	drm_crtc_helper_add(&amp;amdgpu_crtc-&gt;base, &amp;dce_v6_0_crtc_helper_funcs);</div><div class='add'>+	drm_plane_helper_add(amdgpu_crtc-&gt;base.primary, &amp;dce_v6_0_drm_primary_plane_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_early_init(void *handle)</div><div class='add'>+static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;audio_endpt_rreg = &amp;dce_v6_0_audio_endpt_rreg;</div><div class='ctx'> 	adev-&gt;audio_endpt_wreg = &amp;dce_v6_0_audio_endpt_wreg;</div><div class='hunk'>@@ -2662,11 +2737,10 @@ static int dce_v6_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_sw_init(void *handle)</div><div class='add'>+static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	bool ret;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &amp;adev-&gt;crtc_irq);</div><div class='hunk'>@@ -2709,8 +2783,7 @@ static int dce_v6_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_atombios_get_connector_info_from_object_table(adev);</div><div class='del'>-	if (ret)</div><div class='add'>+	if (amdgpu_atombios_get_connector_info_from_object_table(adev))</div><div class='ctx'> 		amdgpu_display_print_display_setup(adev_to_drm(adev));</div><div class='ctx'> 	else</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2741,11 +2814,11 @@ static int dce_v6_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_sw_fini(void *handle)</div><div class='add'>+static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	kfree(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='add'>+	drm_edid_free(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='ctx'> </div><div class='ctx'> 	drm_kms_helper_poll_fini(adev_to_drm(adev));</div><div class='ctx'> </div><div class='hunk'>@@ -2758,10 +2831,10 @@ static int dce_v6_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_hw_init(void *handle)</div><div class='add'>+static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* disable vga render */</div><div class='ctx'> 	dce_v6_0_set_vga_render_state(adev, false);</div><div class='hunk'>@@ -2781,10 +2854,10 @@ static int dce_v6_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_hw_fini(void *handle)</div><div class='add'>+static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	dce_v6_0_hpd_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2799,9 +2872,9 @@ static int dce_v6_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_suspend(void *handle)</div><div class='add'>+static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_display_suspend_helper(adev);</div><div class='hunk'>@@ -2810,18 +2883,18 @@ static int dce_v6_0_suspend(void *handle)</div><div class='ctx'> 	adev-&gt;mode_info.bl_level =</div><div class='ctx'> 		amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);</div><div class='ctx'> </div><div class='del'>-	return dce_v6_0_hw_fini(handle);</div><div class='add'>+	return dce_v6_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_resume(void *handle)</div><div class='add'>+static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,</div><div class='ctx'> 							   adev-&gt;mode_info.bl_level);</div><div class='ctx'> </div><div class='del'>-	ret = dce_v6_0_hw_init(handle);</div><div class='add'>+	ret = dce_v6_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	/* turn on the BL */</div><div class='ctx'> 	if (adev-&gt;mode_info.bl_encoder) {</div><div class='hunk'>@@ -2836,19 +2909,35 @@ static int dce_v6_0_resume(void *handle)</div><div class='ctx'> 	return amdgpu_display_resume_helper(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce_v6_0_is_idle(void *handle)</div><div class='add'>+static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_wait_for_idle(void *handle)</div><div class='add'>+static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='add'>+	u32 srbm_soft_reset = 0, tmp;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");</div><div class='add'>+	if (dce_v6_0_is_display_hung(adev))</div><div class='add'>+		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;</div><div class='add'>+</div><div class='add'>+	if (srbm_soft_reset) {</div><div class='add'>+		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='add'>+		tmp |= srbm_soft_reset;</div><div class='add'>+		dev_info(adev-&gt;dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='add'>+</div><div class='add'>+		udelay(50);</div><div class='add'>+</div><div class='add'>+		tmp &amp;= ~srbm_soft_reset;</div><div class='add'>+		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='add'>+</div><div class='add'>+		/* Wait a little for things to settle down */</div><div class='add'>+		udelay(50);</div><div class='add'>+	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2865,22 +2954,22 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	switch (crtc) {</div><div class='ctx'> 	case 0:</div><div class='del'>-		reg_block = SI_CRTC0_REGISTER_OFFSET;</div><div class='add'>+		reg_block = CRTC0_REGISTER_OFFSET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 1:</div><div class='del'>-		reg_block = SI_CRTC1_REGISTER_OFFSET;</div><div class='add'>+		reg_block = CRTC1_REGISTER_OFFSET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='del'>-		reg_block = SI_CRTC2_REGISTER_OFFSET;</div><div class='add'>+		reg_block = CRTC2_REGISTER_OFFSET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 3:</div><div class='del'>-		reg_block = SI_CRTC3_REGISTER_OFFSET;</div><div class='add'>+		reg_block = CRTC3_REGISTER_OFFSET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 4:</div><div class='del'>-		reg_block = SI_CRTC4_REGISTER_OFFSET;</div><div class='add'>+		reg_block = CRTC4_REGISTER_OFFSET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 5:</div><div class='del'>-		reg_block = SI_CRTC5_REGISTER_OFFSET;</div><div class='add'>+		reg_block = CRTC5_REGISTER_OFFSET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		DRM_DEBUG("invalid crtc %d\n", crtc);</div><div class='hunk'>@@ -2890,12 +2979,12 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 		interrupt_mask = RREG32(mmINT_MASK + reg_block);</div><div class='del'>-		interrupt_mask &amp;= ~VBLANK_INT_MASK;</div><div class='add'>+		interrupt_mask &amp;= ~INT_MASK__VBLANK_INT_MASK;</div><div class='ctx'> 		WREG32(mmINT_MASK + reg_block, interrupt_mask);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='ctx'> 		interrupt_mask = RREG32(mmINT_MASK + reg_block);</div><div class='del'>-		interrupt_mask |= VBLANK_INT_MASK;</div><div class='add'>+		interrupt_mask |= INT_MASK__VBLANK_INT_MASK;</div><div class='ctx'> 		WREG32(mmINT_MASK + reg_block, interrupt_mask);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -2910,28 +2999,28 @@ static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+static int dce_v6_0_set_hpd_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 					    struct amdgpu_irq_src *src,</div><div class='del'>-					    unsigned type,</div><div class='add'>+					    unsigned hpd,</div><div class='ctx'> 					    enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='ctx'> 	u32 dc_hpd_int_cntl;</div><div class='ctx'> </div><div class='del'>-	if (type &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", type);</div><div class='add'>+	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='add'>+		DRM_DEBUG("invalid hpd %d\n", hpd);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);</div><div class='del'>-		dc_hpd_int_cntl &amp;= ~DC_HPDx_INT_EN;</div><div class='del'>-		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);</div><div class='add'>+		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);</div><div class='add'>+		dc_hpd_int_cntl &amp;= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;</div><div class='add'>+		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);</div><div class='del'>-		dc_hpd_int_cntl |= DC_HPDx_INT_EN;</div><div class='del'>-		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);</div><div class='add'>+		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);</div><div class='add'>+		dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;</div><div class='add'>+		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], dc_hpd_int_cntl);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -2940,7 +3029,7 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+static int dce_v6_0_set_crtc_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 					     struct amdgpu_irq_src *src,</div><div class='ctx'> 					     unsigned type,</div><div class='ctx'> 					     enum amdgpu_interrupt_state state)</div><div class='hunk'>@@ -3000,7 +3089,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	switch (entry-&gt;src_data[0]) {</div><div class='ctx'> 	case 0: /* vblank */</div><div class='ctx'> 		if (disp_int &amp; interrupt_status_offsets[crtc].vblank)</div><div class='del'>-			WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);</div><div class='add'>+			WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_STATUS__VBLANK_ACK_MASK);</div><div class='ctx'> 		else</div><div class='ctx'> 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");</div><div class='ctx'> </div><div class='hunk'>@@ -3011,7 +3100,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 1: /* vline */</div><div class='ctx'> 		if (disp_int &amp; interrupt_status_offsets[crtc].vline)</div><div class='del'>-			WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);</div><div class='add'>+			WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_STATUS__VLINE_ACK_MASK);</div><div class='ctx'> 		else</div><div class='ctx'> 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");</div><div class='ctx'> </div><div class='hunk'>@@ -3025,7 +3114,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+static int dce_v6_0_set_pageflip_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 						 struct amdgpu_irq_src *src,</div><div class='ctx'> 						 unsigned type,</div><div class='ctx'> 						 enum amdgpu_interrupt_state state)</div><div class='hunk'>@@ -3076,7 +3165,7 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='ctx'> 	works = amdgpu_crtc-&gt;pflip_works;</div><div class='del'>-	if (amdgpu_crtc-&gt;pflip_status != AMDGPU_FLIP_SUBMITTED){</div><div class='add'>+	if (amdgpu_crtc-&gt;pflip_status != AMDGPU_FLIP_SUBMITTED) {</div><div class='ctx'> 		DRM_DEBUG_DRIVER("amdgpu_crtc-&gt;pflip_status = %d != "</div><div class='ctx'> 						"AMDGPU_FLIP_SUBMITTED(%d)\n",</div><div class='ctx'> 						amdgpu_crtc-&gt;pflip_status,</div><div class='hunk'>@@ -3124,16 +3213,15 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v6_0_set_powergating_state(void *handle,</div><div class='add'>+static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3142,7 +3230,6 @@ static int dce_v6_0_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs dce_v6_0_ip_funcs = {</div><div class='ctx'> 	.name = "dce_v6_0",</div><div class='ctx'> 	.early_init = dce_v6_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = dce_v6_0_sw_init,</div><div class='ctx'> 	.sw_fini = dce_v6_0_sw_fini,</div><div class='ctx'> 	.hw_init = dce_v6_0_hw_init,</div><div class='hunk'>@@ -3150,18 +3237,15 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = {</div><div class='ctx'> 	.suspend = dce_v6_0_suspend,</div><div class='ctx'> 	.resume = dce_v6_0_resume,</div><div class='ctx'> 	.is_idle = dce_v6_0_is_idle,</div><div class='del'>-	.wait_for_idle = dce_v6_0_wait_for_idle,</div><div class='ctx'> 	.soft_reset = dce_v6_0_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = dce_v6_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = dce_v6_0_set_powergating_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void</div><div class='del'>-dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,</div><div class='add'>+static void dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> 			  struct drm_display_mode *mode,</div><div class='ctx'> 			  struct drm_display_mode *adjusted_mode)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='ctx'> 	int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);</div><div class='ctx'> </div><div class='hunk'>@@ -3181,7 +3265,6 @@ dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(encoder-&gt;dev);</div><div class='ctx'> 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='ctx'> 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);</div><div class='hunk'>@@ -3221,7 +3304,6 @@ static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct drm_device *dev = encoder-&gt;dev;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> </div><div class='hunk'>@@ -3232,7 +3314,6 @@ static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='ctx'> 	struct amdgpu_encoder_atom_dig *dig;</div><div class='ctx'> 	int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);</div><div class='hunk'>@@ -3259,8 +3340,7 @@ static void dce_v6_0_ext_commit(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void</div><div class='del'>-dce_v6_0_ext_mode_set(struct drm_encoder *encoder,</div><div class='add'>+static void dce_v6_0_ext_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> 		      struct drm_display_mode *mode,</div><div class='ctx'> 		      struct drm_display_mode *adjusted_mode)</div><div class='ctx'> {</div><div class='hunk'>@@ -3272,8 +3352,7 @@ static void dce_v6_0_ext_disable(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void</div><div class='del'>-dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)</div><div class='add'>+static void dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)</div><div class='ctx'> {</div><div class='ctx'> </div><div class='ctx'> }</div><div class='hunk'>@@ -3344,7 +3423,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device *adev,</div><div class='ctx'> 			amdgpu_encoder-&gt;devices |= supported_device;</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* add a new one */</div><div class='hunk'>@@ -3451,17 +3529,17 @@ static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {</div><div class='del'>-	.set = dce_v6_0_set_crtc_interrupt_state,</div><div class='add'>+	.set = dce_v6_0_set_crtc_irq_state,</div><div class='ctx'> 	.process = dce_v6_0_crtc_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {</div><div class='del'>-	.set = dce_v6_0_set_pageflip_interrupt_state,</div><div class='add'>+	.set = dce_v6_0_set_pageflip_irq_state,</div><div class='ctx'> 	.process = dce_v6_0_pageflip_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {</div><div class='del'>-	.set = dce_v6_0_set_hpd_interrupt_state,</div><div class='add'>+	.set = dce_v6_0_set_hpd_irq_state,</div><div class='ctx'> 	.process = dce_v6_0_hpd_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c<br/>index 5a5fcc45e452..2ccd6aad8dd6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v8_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/dce_v8_0.c</a></div><div class='hunk'>@@ -271,7 +271,7 @@ static void dce_v8_0_hpd_int_ack(struct amdgpu_device *adev,</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (hpd &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", hpd);</div><div class='add'>+		DRM_DEBUG("invalid hpd %d\n", hpd);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1096,8 +1096,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	/* save values for DPM */</div><div class='ctx'> 	amdgpu_crtc-&gt;line_time = line_time;</div><div class='del'>-	amdgpu_crtc-&gt;wm_high = latency_watermark_a;</div><div class='del'>-	amdgpu_crtc-&gt;wm_low = latency_watermark_b;</div><div class='add'>+</div><div class='ctx'> 	/* Save number of lines the linebuffer leads before the scanout */</div><div class='ctx'> 	amdgpu_crtc-&gt;lb_vblank_lead_lines = lb_vblank_lead_lines;</div><div class='ctx'> }</div><div class='hunk'>@@ -1272,7 +1271,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &amp;sadb);</div><div class='add'>+	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector-&gt;edid, &amp;sadb);</div><div class='ctx'> 	if (sad_count &lt; 0) {</div><div class='ctx'> 		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);</div><div class='ctx'> 		sad_count = 0;</div><div class='hunk'>@@ -1340,7 +1339,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &amp;sads);</div><div class='add'>+	sad_count = drm_edid_to_sad(amdgpu_connector-&gt;edid, &amp;sads);</div><div class='ctx'> 	if (sad_count &lt; 0)</div><div class='ctx'> 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);</div><div class='ctx'> 	if (sad_count &lt;= 0)</div><div class='hunk'>@@ -1395,13 +1394,13 @@ static void dce_v8_0_audio_enable(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const u32 pin_offsets[7] = {</div><div class='del'>-	(0x1780 - 0x1780),</div><div class='del'>-	(0x1786 - 0x1780),</div><div class='del'>-	(0x178c - 0x1780),</div><div class='del'>-	(0x1792 - 0x1780),</div><div class='del'>-	(0x1798 - 0x1780),</div><div class='del'>-	(0x179d - 0x1780),</div><div class='del'>-	(0x17a4 - 0x1780),</div><div class='add'>+	AUD0_REGISTER_OFFSET,</div><div class='add'>+	AUD1_REGISTER_OFFSET,</div><div class='add'>+	AUD2_REGISTER_OFFSET,</div><div class='add'>+	AUD3_REGISTER_OFFSET,</div><div class='add'>+	AUD4_REGISTER_OFFSET,</div><div class='add'>+	AUD5_REGISTER_OFFSET,</div><div class='add'>+	AUD6_REGISTER_OFFSET,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int dce_v8_0_audio_init(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1443,17 +1442,12 @@ static int dce_v8_0_audio_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void dce_v8_0_audio_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='ctx'> 	if (!amdgpu_audio)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;mode_info.audio.enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;mode_info.audio.num_pins; i++)</div><div class='del'>-		dce_v8_0_audio_enable(adev, &amp;adev-&gt;mode_info.audio.pin[i], false);</div><div class='del'>-</div><div class='ctx'> 	adev-&gt;mode_info.audio.enabled = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1828,6 +1822,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	if (!atomic) {</div><div class='add'>+		abo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 		if (unlikely(r != 0)) {</div><div class='ctx'> 			amdgpu_bo_unreserve(abo);</div><div class='hunk'>@@ -2320,6 +2315,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	aobj-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 	ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 	amdgpu_bo_unreserve(aobj);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2611,6 +2607,31 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {</div><div class='ctx'> 	.get_scanout_position = amdgpu_crtc_get_scanout_position,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void dce_v8_0_panic_flush(struct drm_plane *plane)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	struct amdgpu_crtc *amdgpu_crtc;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	uint32_t fb_format;</div><div class='add'>+</div><div class='add'>+	if (!plane-&gt;fb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fb = plane-&gt;fb;</div><div class='add'>+	amdgpu_crtc = to_amdgpu_crtc(plane-&gt;crtc);</div><div class='add'>+	adev = drm_to_adev(fb-&gt;dev);</div><div class='add'>+</div><div class='add'>+	/* Disable DC tiling */</div><div class='add'>+	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset);</div><div class='add'>+	fb_format &amp;= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK;</div><div class='add'>+	WREG32(mmGRPH_CONTROL + amdgpu_crtc-&gt;crtc_offset, fb_format);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_plane_helper_funcs dce_v8_0_drm_primary_plane_helper_funcs = {</div><div class='add'>+	.get_scanout_buffer = amdgpu_display_get_scanout_buffer,</div><div class='add'>+	.panic_flush = dce_v8_0_panic_flush,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc;</div><div class='hunk'>@@ -2638,13 +2659,14 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)</div><div class='ctx'> 	amdgpu_crtc-&gt;encoder = NULL;</div><div class='ctx'> 	amdgpu_crtc-&gt;connector = NULL;</div><div class='ctx'> 	drm_crtc_helper_add(&amp;amdgpu_crtc-&gt;base, &amp;dce_v8_0_crtc_helper_funcs);</div><div class='add'>+	drm_plane_helper_add(amdgpu_crtc-&gt;base.primary, &amp;dce_v8_0_drm_primary_plane_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_early_init(void *handle)</div><div class='add'>+static int dce_v8_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;audio_endpt_rreg = &amp;dce_v8_0_audio_endpt_rreg;</div><div class='ctx'> 	adev-&gt;audio_endpt_wreg = &amp;dce_v8_0_audio_endpt_wreg;</div><div class='hunk'>@@ -2678,10 +2700,10 @@ static int dce_v8_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_sw_init(void *handle)</div><div class='add'>+static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &amp;adev-&gt;crtc_irq);</div><div class='hunk'>@@ -2762,11 +2784,11 @@ static int dce_v8_0_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_sw_fini(void *handle)</div><div class='add'>+static int dce_v8_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	kfree(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='add'>+	drm_edid_free(adev-&gt;mode_info.bios_hardcoded_edid);</div><div class='ctx'> </div><div class='ctx'> 	drm_kms_helper_poll_fini(adev_to_drm(adev));</div><div class='ctx'> </div><div class='hunk'>@@ -2780,10 +2802,10 @@ static int dce_v8_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_hw_init(void *handle)</div><div class='add'>+static int dce_v8_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* disable vga render */</div><div class='ctx'> 	dce_v8_0_set_vga_render_state(adev, false);</div><div class='hunk'>@@ -2803,10 +2825,10 @@ static int dce_v8_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_hw_fini(void *handle)</div><div class='add'>+static int dce_v8_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	dce_v8_0_hpd_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2821,9 +2843,9 @@ static int dce_v8_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_suspend(void *handle)</div><div class='add'>+static int dce_v8_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_display_suspend_helper(adev);</div><div class='hunk'>@@ -2833,18 +2855,18 @@ static int dce_v8_0_suspend(void *handle)</div><div class='ctx'> 	adev-&gt;mode_info.bl_level =</div><div class='ctx'> 		amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);</div><div class='ctx'> </div><div class='del'>-	return dce_v8_0_hw_fini(handle);</div><div class='add'>+	return dce_v8_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_resume(void *handle)</div><div class='add'>+static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,</div><div class='ctx'> 							   adev-&gt;mode_info.bl_level);</div><div class='ctx'> </div><div class='del'>-	ret = dce_v8_0_hw_init(handle);</div><div class='add'>+	ret = dce_v8_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	/* turn on the BL */</div><div class='ctx'> 	if (adev-&gt;mode_info.bl_encoder) {</div><div class='hunk'>@@ -2859,20 +2881,15 @@ static int dce_v8_0_resume(void *handle)</div><div class='ctx'> 	return amdgpu_display_resume_helper(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce_v8_0_is_idle(void *handle)</div><div class='add'>+static bool dce_v8_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dce_v8_0_soft_reset(void *handle)</div><div class='add'>+static int dce_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0, tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (dce_v8_0_is_display_hung(adev))</div><div class='ctx'> 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;</div><div class='hunk'>@@ -2998,7 +3015,7 @@ static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+static int dce_v8_0_set_hpd_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 					    struct amdgpu_irq_src *src,</div><div class='ctx'> 					    unsigned type,</div><div class='ctx'> 					    enum amdgpu_interrupt_state state)</div><div class='hunk'>@@ -3006,7 +3023,7 @@ static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	u32 dc_hpd_int_cntl;</div><div class='ctx'> </div><div class='ctx'> 	if (type &gt;= adev-&gt;mode_info.num_hpd) {</div><div class='del'>-		DRM_DEBUG("invalid hdp %d\n", type);</div><div class='add'>+		DRM_DEBUG("invalid hpd %d\n", type);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3028,7 +3045,7 @@ static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+static int dce_v8_0_set_crtc_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 					     struct amdgpu_irq_src *src,</div><div class='ctx'> 					     unsigned type,</div><div class='ctx'> 					     enum amdgpu_interrupt_state state)</div><div class='hunk'>@@ -3113,7 +3130,7 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+static int dce_v8_0_set_pageflip_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 						 struct amdgpu_irq_src *src,</div><div class='ctx'> 						 unsigned type,</div><div class='ctx'> 						 enum amdgpu_interrupt_state state)</div><div class='hunk'>@@ -3215,13 +3232,13 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_set_clockgating_state(void *handle,</div><div class='add'>+static int dce_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dce_v8_0_set_powergating_state(void *handle,</div><div class='add'>+static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3230,7 +3247,6 @@ static int dce_v8_0_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs dce_v8_0_ip_funcs = {</div><div class='ctx'> 	.name = "dce_v8_0",</div><div class='ctx'> 	.early_init = dce_v8_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = dce_v8_0_sw_init,</div><div class='ctx'> 	.sw_fini = dce_v8_0_sw_fini,</div><div class='ctx'> 	.hw_init = dce_v8_0_hw_init,</div><div class='hunk'>@@ -3238,7 +3254,6 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = {</div><div class='ctx'> 	.suspend = dce_v8_0_suspend,</div><div class='ctx'> 	.resume = dce_v8_0_resume,</div><div class='ctx'> 	.is_idle = dce_v8_0_is_idle,</div><div class='del'>-	.wait_for_idle = dce_v8_0_wait_for_idle,</div><div class='ctx'> 	.soft_reset = dce_v8_0_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = dce_v8_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = dce_v8_0_set_powergating_state,</div><div class='hunk'>@@ -3526,17 +3541,17 @@ static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {</div><div class='del'>-	.set = dce_v8_0_set_crtc_interrupt_state,</div><div class='add'>+	.set = dce_v8_0_set_crtc_irq_state,</div><div class='ctx'> 	.process = dce_v8_0_crtc_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {</div><div class='del'>-	.set = dce_v8_0_set_pageflip_interrupt_state,</div><div class='add'>+	.set = dce_v8_0_set_pageflip_irq_state,</div><div class='ctx'> 	.process = dce_v8_0_pageflip_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {</div><div class='del'>-	.set = dce_v8_0_set_hpd_interrupt_state,</div><div class='add'>+	.set = dce_v8_0_set_hpd_irq_state,</div><div class='ctx'> 	.process = dce_v8_0_hpd_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c<br/>index 5dfab80ffff2..cd298556f7a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/df_v1_7.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/df_v1_7.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/df_v1_7.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/df_v1_7.c</a></div><div class='hunk'>@@ -70,6 +70,8 @@ static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)</div><div class='ctx'> 	int fb_channel_number;</div><div class='ctx'> </div><div class='ctx'> 	fb_channel_number = adev-&gt;df.funcs-&gt;get_fb_channel_number(adev);</div><div class='add'>+	if (fb_channel_number &gt;= ARRAY_SIZE(df_v1_7_channel_number))</div><div class='add'>+		fb_channel_number = 0;</div><div class='ctx'> </div><div class='ctx'> 	return df_v1_7_channel_number[fb_channel_number];</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c<br/>index 483a441b46aa..621aeca53880 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/df_v3_6.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/df_v3_6.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/df_v3_6.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/df_v3_6.c</a></div><div class='hunk'>@@ -254,8 +254,8 @@ static void df_v3_6_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void df_v3_6_sw_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-</div><div class='del'>-	device_remove_file(adev-&gt;dev, &amp;dev_attr_df_cntr_avail);</div><div class='add'>+	if (adev-&gt;dev-&gt;kobj.sd)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_df_cntr_avail);</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/df_v4_15.c b/drivers/gpu/drm/amd/amdgpu/df_v4_15.c<br/>new file mode 100644<br/>index 000000000000..2a573e33908b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/df_v4_15.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/df_v4_15.c</a></div><div class='hunk'>@@ -0,0 +1,45 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "df_v4_15.h"</div><div class='add'>+</div><div class='add'>+#include "df/df_4_15_offset.h"</div><div class='add'>+#include "df/df_4_15_sh_mask.h"</div><div class='add'>+</div><div class='add'>+static void df_v4_15_hw_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;have_atomics_support) {</div><div class='add'>+		uint32_t tmp;</div><div class='add'>+		uint32_t dis_lcl_proc = (1 &lt;&lt;  1 |</div><div class='add'>+					1 &lt;&lt;  2 |</div><div class='add'>+					1 &lt;&lt; 13);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15(DF, 0, regNCSConfigurationRegister1);</div><div class='add'>+		tmp |= (dis_lcl_proc &lt;&lt; NCSConfigurationRegister1__DisIntAtomicsLclProcessing__SHIFT);</div><div class='add'>+		WREG32_SOC15(DF, 0, regNCSConfigurationRegister1, tmp);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_df_funcs df_v4_15_funcs = {</div><div class='add'>+	.hw_init = df_v4_15_hw_init</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/df_v4_15.h b/drivers/gpu/drm/amd/amdgpu/df_v4_15.h<br/>new file mode 100644<br/>index 000000000000..dddf2422112a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/df_v4_15.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/df_v4_15.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DF_V4_15_H__</div><div class='add'>+#define __DF_V4_15_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_df_funcs df_v4_15_funcs;</div><div class='add'>+</div><div class='add'>+#endif /* __DF_V4_15_H__ */</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br/>index f90905ef32c7..d75b9940f248 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c</a></div><div class='hunk'>@@ -40,11 +40,11 @@</div><div class='ctx'> #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"</div><div class='ctx'> </div><div class='ctx'> #include "soc15.h"</div><div class='del'>-#include "soc15d.h"</div><div class='ctx'> #include "soc15_common.h"</div><div class='ctx'> #include "clearstate_gfx10.h"</div><div class='ctx'> #include "v10_structs.h"</div><div class='ctx'> #include "gfx_v10_0.h"</div><div class='add'>+#include "gfx_v10_0_cleaner_shader.h"</div><div class='ctx'> #include "nbio_v2_3.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -276,6 +276,210 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),</div><div class='add'>+	/* SE status registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {</div><div class='add'>+	/* compute registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {</div><div class='add'>+	/* gfx queue registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	/* gfx header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),</div><div class='hunk'>@@ -3498,17 +3702,23 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,</div><div class='ctx'> static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,</div><div class='ctx'> 					       unsigned int vmid);</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state);</div><div class='ctx'> static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	u64 shader_mc_addr;</div><div class='add'>+</div><div class='add'>+	/* Cleaner shader MC address */</div><div class='add'>+	shader_mc_addr = adev-&gt;gfx.cleaner_shader_gpu_addr &gt;&gt; 8;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |</div><div class='ctx'> 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */</div><div class='ctx'> }</div><div class='hunk'>@@ -3558,14 +3768,8 @@ static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 				   enum amdgpu_unmap_queues_action action,</div><div class='ctx'> 				   u64 gpu_addr, u64 seq)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='ctx'> 	uint32_t eng_sel = ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX ? 4 : 0;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes &amp;&amp; !adev-&gt;gfx.kiq[0].ring.sched.ready) {</div><div class='del'>-		amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */</div><div class='ctx'> 			  PACKET3_UNMAP_QUEUES_ACTION(action) |</div><div class='hunk'>@@ -3614,12 +3818,65 @@ static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 	gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,</div><div class='add'>+					uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+					uint32_t xcc_id, uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	unsigned i;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* enter save mode */</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);</div><div class='add'>+</div><div class='add'>+	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='add'>+		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+			dev_err(adev-&gt;dev, "fail to wait on hqd deactive\n");</div><div class='add'>+	} else if (queue_type == AMDGPU_RING_TYPE_GFX) {</div><div class='add'>+		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,</div><div class='add'>+			     (uint32_t)(0x1 &lt;&lt; GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));</div><div class='add'>+		tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 &lt;&lt; vmid);</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 &lt;&lt; queue_id);</div><div class='add'>+		else</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 &lt;&lt; queue_id);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);</div><div class='add'>+</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on gfx hqd deactivate\n");</div><div class='add'>+	} else {</div><div class='add'>+		dev_err(adev-&gt;dev, "reset queue_type(%d) not supported\n", queue_type);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	/* exit safe mode */</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {</div><div class='ctx'> 	.kiq_set_resources = gfx10_kiq_set_resources,</div><div class='ctx'> 	.kiq_map_queues = gfx10_kiq_map_queues,</div><div class='ctx'> 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,</div><div class='ctx'> 	.kiq_query_status = gfx10_kiq_query_status,</div><div class='ctx'> 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,</div><div class='add'>+	.kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,</div><div class='ctx'> 	.set_resources_size = 8,</div><div class='ctx'> 	.map_queues_size = 7,</div><div class='ctx'> 	.unmap_queues_size = 6,</div><div class='hunk'>@@ -3818,38 +4075,23 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	struct dma_fence *f = NULL;</div><div class='ctx'> 	unsigned int index;</div><div class='ctx'> 	uint64_t gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr;</div><div class='add'>+	uint32_t *cpu_ptr;</div><div class='ctx'> 	long r;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t padding, offset;</div><div class='del'>-</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);</div><div class='del'>-		padding = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-						  AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-</div><div class='del'>-		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);</div><div class='del'>-		*cpu_ptr = cpu_to_le32(0xCAFEDEAD);</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='del'>-		cpu_ptr = &amp;adev-&gt;wb.wb[index];</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='add'>+	cpu_ptr = &amp;adev-&gt;wb.wb[index];</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='del'>-			goto err1;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);</div><div class='hunk'>@@ -3876,12 +4118,10 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	else</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> err2:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err1:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3964,7 +4204,7 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[40];</div><div class='add'>+	char fw_name[53];</div><div class='ctx'> 	char ucode_prefix[30];</div><div class='ctx'> 	const char *wks = "";</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -3979,20 +4219,23 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		wks = "_wks";</div><div class='ctx'> 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wks);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_me%s.bin", ucode_prefix, wks);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wks);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_ce%s.bin", ucode_prefix, wks);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);</div><div class='hunk'>@@ -4014,15 +4257,17 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, wks);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mec%s.bin", ucode_prefix, wks);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);</div><div class='ctx'> 	if (!err) {</div><div class='ctx'> 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);</div><div class='ctx'> 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);</div><div class='hunk'>@@ -4077,12 +4322,9 @@ static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='del'>-				    volatile u32 *buffer)</div><div class='add'>+static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='ctx'> {</div><div class='del'>-	u32 count = 0, i;</div><div class='del'>-	const struct cs_section_def *sect = NULL;</div><div class='del'>-	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> 	int ctx_reg_offset;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='hunk'>@@ -4090,39 +4332,15 @@ static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='ctx'> 	if (buffer == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-</div><div class='del'>-	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='del'>-		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='del'>-			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='del'>-				buffer[count++] =</div><div class='del'>-					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='del'>-				buffer[count++] = cpu_to_le32(ext-&gt;reg_index -</div><div class='del'>-						PACKET3_SET_CONTEXT_REG_START);</div><div class='del'>-				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='del'>-					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='del'>-			} else {</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	count = amdgpu_gfx_csb_preamble_start(buffer);</div><div class='add'>+	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);</div><div class='ctx'> </div><div class='del'>-	ctx_reg_offset =</div><div class='del'>-		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;</div><div class='add'>+	ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(ctx_reg_offset);</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.pa_sc_tile_steering_override);</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+	amdgpu_gfx_csb_preamble_end(buffer, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4490,11 +4708,55 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> 			     hw_prio, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_sw_init(void *handle)</div><div class='add'>+static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);</div><div class='add'>+	uint32_t *ptr;</div><div class='add'>+	uint32_t inst;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for compute queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);</div><div class='add'>+	inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for gfx queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);</div><div class='add'>+	inst = adev-&gt;gfx.me.num_me * adev-&gt;gfx.me.num_pipe_per_me *</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_gfx_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_gfx_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j, k, r, ring_id = 0;</div><div class='ctx'> 	int xcc_id = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */</div><div class='add'>+</div><div class='add'>+	INIT_DELAYED_WORK(&amp;adev-&gt;gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(10, 1, 10):</div><div class='hunk'>@@ -4504,7 +4766,7 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> 	case IP_VERSION(10, 1, 4):</div><div class='ctx'> 		adev-&gt;gfx.me.num_me = 1;</div><div class='ctx'> 		adev-&gt;gfx.me.num_pipe_per_me = 1;</div><div class='del'>-		adev-&gt;gfx.me.num_queue_per_pipe = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe = 8;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_mec = 2;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_queue_per_pipe = 8;</div><div class='hunk'>@@ -4518,8 +4780,8 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> 	case IP_VERSION(10, 3, 3):</div><div class='ctx'> 	case IP_VERSION(10, 3, 7):</div><div class='ctx'> 		adev-&gt;gfx.me.num_me = 1;</div><div class='del'>-		adev-&gt;gfx.me.num_pipe_per_me = 1;</div><div class='del'>-		adev-&gt;gfx.me.num_queue_per_pipe = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_pipe_per_me = 2;</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe = 2;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_mec = 2;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_queue_per_pipe = 4;</div><div class='hunk'>@@ -4533,6 +4795,74 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> 		adev-&gt;gfx.mec.num_queue_per_pipe = 8;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(10, 1, 10):</div><div class='add'>+	case IP_VERSION(10, 1, 1):</div><div class='add'>+	case IP_VERSION(10, 1, 2):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version &gt;= 101 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version  &gt;= 158 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 151) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(10, 3, 0):</div><div class='add'>+	case IP_VERSION(10, 3, 1):</div><div class='add'>+	case IP_VERSION(10, 3, 2):</div><div class='add'>+	case IP_VERSION(10, 3, 3):</div><div class='add'>+	case IP_VERSION(10, 3, 4):</div><div class='add'>+	case IP_VERSION(10, 3, 5):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version &gt;= 64 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 100 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 122) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(10, 3, 6):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version &gt;= 14 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 17 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 24) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(10, 3, 7):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version &gt;= 4 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 9 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 12) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* KIQ event */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,</div><div class='hunk'>@@ -4548,6 +4878,13 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	/* Bad opcode Event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,</div><div class='add'>+			      &amp;adev-&gt;gfx.bad_op_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	/* Privileged reg */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,</div><div class='ctx'> 			      &amp;adev-&gt;gfx.priv_reg_irq);</div><div class='hunk'>@@ -4582,7 +4919,7 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	/* set up the gfx ring */</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='del'>-		for (j = 0; j &lt; adev-&gt;gfx.me.num_queue_per_pipe; j++) {</div><div class='add'>+		for (j = 0; j &lt; num_queue_per_pipe; j++) {</div><div class='ctx'> 			for (k = 0; k &lt; adev-&gt;gfx.me.num_pipe_per_me; k++) {</div><div class='ctx'> 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))</div><div class='ctx'> 					continue;</div><div class='hunk'>@@ -4615,18 +4952,26 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;enable_mes_kiq) {</div><div class='del'>-		r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to init KIQ BOs!\n");</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+	    !adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+		adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		adev-&gt;gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to init KIQ BOs!\n");</div><div class='add'>+		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -4642,6 +4987,12 @@ static int gfx_v10_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	gfx_v10_0_gpu_early_init(adev);</div><div class='ctx'> </div><div class='add'>+	gfx_v10_0_alloc_ip_dump(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4666,10 +5017,10 @@ static void gfx_v10_0_me_fini(struct amdgpu_device *adev)</div><div class='ctx'> 			      (void **)&amp;adev-&gt;gfx.me.me_fw_ptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_sw_fini(void *handle)</div><div class='add'>+static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;gfx.gfx_ring[i]);</div><div class='hunk'>@@ -4678,10 +5029,10 @@ static int gfx_v10_0_sw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gfx_mqd_sw_fini(adev, 0);</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;enable_mes_kiq) {</div><div class='del'>-		amdgpu_gfx_kiq_free_ring(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='del'>-		amdgpu_gfx_kiq_fini(adev, 0);</div><div class='del'>-	}</div><div class='add'>+	amdgpu_gfx_kiq_free_ring(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='add'>+	amdgpu_gfx_kiq_fini(adev, 0);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_cleaner_shader_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	gfx_v10_0_pfp_fini(adev);</div><div class='ctx'> 	gfx_v10_0_ce_fini(adev);</div><div class='hunk'>@@ -4693,6 +5044,11 @@ static int gfx_v10_0_sw_fini(void *handle)</div><div class='ctx'> 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	gfx_v10_0_free_microcode(adev);</div><div class='add'>+	amdgpu_gfx_sysfs_fini(adev);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_core);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_compute_queues);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_gfx_queues);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -5018,26 +5374,74 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	if (me != 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * amdgpu controls only the first MEC. That's why this function only</div><div class='add'>+	 * handles the setting of interrupts for this specific MEC. All other</div><div class='add'>+	 * pipes' interrupts are set by amdkfd.</div><div class='add'>+	 */</div><div class='add'>+	if (me != 1)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);</div><div class='add'>+	case 2:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);</div><div class='add'>+	case 3:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 					       bool enable)</div><div class='ctx'> {</div><div class='del'>-	u32 tmp;</div><div class='add'>+	u32 tmp, cp_int_cntl_reg;</div><div class='add'>+	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);</div><div class='del'>-</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+			if (cp_int_cntl_reg) {</div><div class='add'>+				tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v10_0_init_csb(struct amdgpu_device *adev)</div><div class='hunk'>@@ -5679,7 +6083,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 	else</div><div class='ctx'> 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;job_hang &amp;&amp; !enable)</div><div class='add'>+	if (amdgpu_in_reset(adev) &amp;&amp; !enable)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='hunk'>@@ -5748,7 +6152,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);</div><div class='hunk'>@@ -5826,7 +6230,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);</div><div class='hunk'>@@ -5903,7 +6307,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);</div><div class='hunk'>@@ -6124,7 +6528,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring-&gt;wptr));</div><div class='ctx'> </div><div class='del'>-	/* set the wb address wether it's enabled or not */</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp;</div><div class='hunk'>@@ -6162,7 +6566,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 		ring-&gt;wptr = 0;</div><div class='ctx'> 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring-&gt;wptr));</div><div class='del'>-		/* Set the wb address wether it's enabled or not */</div><div class='add'>+		/* Set the wb address whether it's enabled or not */</div><div class='ctx'> 		rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp;</div><div class='hunk'>@@ -6278,7 +6682,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='hunk'>@@ -6326,17 +6730,13 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='ctx'> 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);</div><div class='ctx'> 		tmp &amp;= 0xffffff00;</div><div class='ctx'> 		tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);</div><div class='del'>-		tmp |= 0x80;</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);</div><div class='ctx'> 		tmp &amp;= 0xffffff00;</div><div class='ctx'> 		tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-		tmp |= 0x80;</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -6442,13 +6842,13 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)</div><div class='add'>+static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct v10_gfx_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='ctx'> 	int mqd_idx = ring - &amp;adev-&gt;gfx.gfx_ring[0];</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+	if (!reset &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='ctx'> 		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> 		nv_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='hunk'>@@ -6489,22 +6889,9 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			return r;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v10_0_gfx_init_queue(ring);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+		r = gfx_v10_0_kgq_init_queue(&amp;adev-&gt;gfx.gfx_ring[i], false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -6780,13 +7167,13 @@ static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='add'>+static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct v10_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='ctx'> 	int mqd_idx = ring - &amp;adev-&gt;gfx.compute_ring[0];</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+	if (!restore &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='ctx'> 		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> 		nv_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='hunk'>@@ -6811,55 +7198,24 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-	if (unlikely(r != 0)) {</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gfx_v10_0_kiq_init_queue(ring);</div><div class='del'>-	amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-	ring-&gt;mqd_ptr = NULL;</div><div class='del'>-	amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+	gfx_v10_0_kiq_init_queue(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = NULL;</div><div class='del'>-	int r = 0, i;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v10_0_cp_compute_enable(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			goto done;</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v10_0_kcq_init_queue(ring);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+		r = gfx_v10_0_kcq_init_queue(&amp;adev-&gt;gfx.compute_ring[i],</div><div class='add'>+					     false);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_gfx_enable_kcq(adev, 0);</div><div class='del'>-done:</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_gfx_enable_kcq(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)</div><div class='hunk'>@@ -6881,10 +7237,7 @@ static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes_kiq &amp;&amp; adev-&gt;mes.kiq_hw_init)</div><div class='del'>-		r = amdgpu_mes_kiq_hw_init(adev);</div><div class='del'>-	else</div><div class='del'>-		r = gfx_v10_0_kiq_resume(adev);</div><div class='add'>+	r = gfx_v10_0_kiq_resume(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -7119,25 +7472,26 @@ static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_hw_init(void *handle)</div><div class='add'>+static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_emu_mode)</div><div class='ctx'> 		gfx_v10_0_init_golden_registers(adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_gfx_cleaner_shader_init(adev, adev-&gt;gfx.cleaner_shader_size,</div><div class='add'>+				       adev-&gt;gfx.cleaner_shader_ptr);</div><div class='add'>+</div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='ctx'> 		/**</div><div class='ctx'> 		 * For gfx 10, rlc firmware loading relies on smu firmware is</div><div class='ctx'> 		 * loaded firstly, so in direct type, it has to load smc ucode</div><div class='ctx'> 		 * here before rlc.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='del'>-			r = amdgpu_pm_load_smu_firmware(adev, NULL);</div><div class='del'>-			if (r)</div><div class='del'>-				return r;</div><div class='del'>-		}</div><div class='add'>+		r = amdgpu_pm_load_smu_firmware(adev, NULL);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> 		gfx_v10_0_disable_gpa_mode(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -7173,19 +7527,22 @@ static int gfx_v10_0_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_hw_fini(void *handle)</div><div class='add'>+static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;gfx.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* WA added for Vangogh asic fixing the SMU suspend failure</div><div class='ctx'> 	 * It needs to set power gating again during gfxoff control</div><div class='ctx'> 	 * otherwise the gfxoff disallowing will be failed to set.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))</div><div class='del'>-		gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);</div><div class='add'>+		gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;no_hw_access) {</div><div class='ctx'> 		if (amdgpu_async_gfx_ring) {</div><div class='hunk'>@@ -7210,19 +7567,19 @@ static int gfx_v10_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_suspend(void *handle)</div><div class='add'>+static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v10_0_hw_fini(handle);</div><div class='add'>+	return gfx_v10_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_resume(void *handle)</div><div class='add'>+static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v10_0_hw_init(handle);</div><div class='add'>+	return gfx_v10_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v10_0_is_idle(void *handle)</div><div class='add'>+static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),</div><div class='ctx'> 				GRBM_STATUS, GUI_ACTIVE))</div><div class='hunk'>@@ -7231,11 +7588,11 @@ static bool gfx_v10_0_is_idle(void *handle)</div><div class='ctx'> 		return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -7249,11 +7606,11 @@ static int gfx_v10_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_soft_reset(void *handle)</div><div class='add'>+static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* GRBM_STATUS */</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);</div><div class='hunk'>@@ -7311,19 +7668,17 @@ static int gfx_v10_0_soft_reset(void *handle)</div><div class='ctx'> 		/* Disable MEC parsing/prefetching */</div><div class='ctx'> 		gfx_v10_0_cp_compute_enable(adev, false);</div><div class='ctx'> </div><div class='del'>-		if (grbm_soft_reset) {</div><div class='del'>-			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='del'>-			tmp |= grbm_soft_reset;</div><div class='del'>-			dev_info(adev-&gt;dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='del'>-			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+		tmp |= grbm_soft_reset;</div><div class='add'>+		dev_info(adev-&gt;dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='del'>-			udelay(50);</div><div class='add'>+		udelay(50);</div><div class='ctx'> </div><div class='del'>-			tmp &amp;= ~grbm_soft_reset;</div><div class='del'>-			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='del'>-			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='del'>-		}</div><div class='add'>+		tmp &amp;= ~grbm_soft_reset;</div><div class='add'>+		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait a little for things to settle down */</div><div class='ctx'> 		udelay(50);</div><div class='hunk'>@@ -7432,9 +7787,9 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,</div><div class='ctx'> 				    (1 &lt;&lt; (oa_size + oa_base)) - (1 &lt;&lt; oa_base));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_early_init(void *handle)</div><div class='add'>+static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.funcs = &amp;gfx_v10_0_gfx_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -7476,9 +7831,9 @@ static int gfx_v10_0_early_init(void *handle)</div><div class='ctx'> 	return gfx_v10_0_init_microcode(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_late_init(void *handle)</div><div class='add'>+static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='hunk'>@@ -7489,6 +7844,10 @@ static int gfx_v10_0_late_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -7939,15 +8298,24 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,</div><div class='ctx'> 					       unsigned int vmid)</div><div class='ctx'> {</div><div class='del'>-	u32 data;</div><div class='add'>+	u32 reg, pre_data, data;</div><div class='ctx'> </div><div class='add'>+	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);</div><div class='ctx'> 	/* not for *_SOC15 */</div><div class='del'>-	data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);</div><div class='add'>+	if (amdgpu_sriov_is_pp_one_vf(adev) &amp;&amp; !amdgpu_sriov_runtime(adev))</div><div class='add'>+		pre_data = RREG32_NO_KIQ(reg);</div><div class='add'>+	else</div><div class='add'>+		pre_data = RREG32(reg);</div><div class='ctx'> </div><div class='del'>-	data &amp;= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;</div><div class='add'>+	data = pre_data &amp; (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);</div><div class='ctx'> 	data |= (vmid &amp; RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) &lt;&lt; RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;</div><div class='ctx'> </div><div class='del'>-	WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);</div><div class='add'>+	if (pre_data != data) {</div><div class='add'>+		if (amdgpu_sriov_is_pp_one_vf(adev) &amp;&amp; !amdgpu_sriov_runtime(adev)) {</div><div class='add'>+			WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);</div><div class='add'>+		} else</div><div class='add'>+			WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)</div><div class='hunk'>@@ -8060,10 +8428,10 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {</div><div class='ctx'> 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -8098,10 +8466,10 @@ static int gfx_v10_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v10_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -8127,9 +8495,9 @@ static int gfx_v10_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	/* AMD_CG_SUPPORT_GFX_FGCG */</div><div class='hunk'>@@ -8196,45 +8564,17 @@ static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)</div><div class='ctx'> static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	uint32_t *wptr_saved;</div><div class='del'>-	uint32_t *is_queue_unmap;</div><div class='del'>-	uint64_t aggregated_db_index;</div><div class='del'>-	uint32_t mqd_size = adev-&gt;mqds[AMDGPU_HW_IP_GFX].mqd_size;</div><div class='del'>-	uint64_t wptr_tmp;</div><div class='del'>-</div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		wptr_saved = (uint32_t *)(ring-&gt;mqd_ptr + mqd_size);</div><div class='del'>-		is_queue_unmap = (uint32_t *)(ring-&gt;mqd_ptr + mqd_size +</div><div class='del'>-					      sizeof(uint32_t));</div><div class='del'>-		aggregated_db_index =</div><div class='del'>-			amdgpu_mes_get_aggregated_doorbell_index(adev,</div><div class='del'>-			AMDGPU_MES_PRIORITY_LEVEL_NORMAL);</div><div class='del'>-</div><div class='del'>-		wptr_tmp = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='del'>-		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr, wptr_tmp);</div><div class='del'>-		*wptr_saved = wptr_tmp;</div><div class='del'>-		/* assume doorbell always being used by mes mapped queue */</div><div class='del'>-		if (*is_queue_unmap) {</div><div class='del'>-			WDOORBELL64(aggregated_db_index, wptr_tmp);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, wptr_tmp);</div><div class='del'>-		} else {</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, wptr_tmp);</div><div class='ctx'> </div><div class='del'>-			if (*is_queue_unmap)</div><div class='del'>-				WDOORBELL64(aggregated_db_index, wptr_tmp);</div><div class='del'>-		}</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		/* XXX check if swapping is necessary on BE */</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='add'>+			     ring-&gt;wptr);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='ctx'> 	} else {</div><div class='del'>-		if (ring-&gt;use_doorbell) {</div><div class='del'>-			/* XXX check if swapping is necessary on BE */</div><div class='del'>-			atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='del'>-				     ring-&gt;wptr);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='del'>-		} else {</div><div class='del'>-			WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,</div><div class='del'>-				     lower_32_bits(ring-&gt;wptr));</div><div class='del'>-			WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,</div><div class='del'>-				     upper_32_bits(ring-&gt;wptr));</div><div class='del'>-		}</div><div class='add'>+		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,</div><div class='add'>+			     lower_32_bits(ring-&gt;wptr));</div><div class='add'>+		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,</div><div class='add'>+			     upper_32_bits(ring-&gt;wptr));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -8259,42 +8599,13 @@ static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)</div><div class='ctx'> static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	uint32_t *wptr_saved;</div><div class='del'>-	uint32_t *is_queue_unmap;</div><div class='del'>-	uint64_t aggregated_db_index;</div><div class='del'>-	uint32_t mqd_size = adev-&gt;mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;</div><div class='del'>-	uint64_t wptr_tmp;</div><div class='del'>-</div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		wptr_saved = (uint32_t *)(ring-&gt;mqd_ptr + mqd_size);</div><div class='del'>-		is_queue_unmap = (uint32_t *)(ring-&gt;mqd_ptr + mqd_size +</div><div class='del'>-					      sizeof(uint32_t));</div><div class='del'>-		aggregated_db_index =</div><div class='del'>-			amdgpu_mes_get_aggregated_doorbell_index(adev,</div><div class='del'>-			AMDGPU_MES_PRIORITY_LEVEL_NORMAL);</div><div class='del'>-</div><div class='del'>-		wptr_tmp = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='del'>-		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr, wptr_tmp);</div><div class='del'>-		*wptr_saved = wptr_tmp;</div><div class='del'>-		/* assume doorbell always used by mes mapped queue */</div><div class='del'>-		if (*is_queue_unmap) {</div><div class='del'>-			WDOORBELL64(aggregated_db_index, wptr_tmp);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, wptr_tmp);</div><div class='del'>-		} else {</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, wptr_tmp);</div><div class='ctx'> </div><div class='del'>-			if (*is_queue_unmap)</div><div class='del'>-				WDOORBELL64(aggregated_db_index, wptr_tmp);</div><div class='del'>-		}</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='add'>+			     ring-&gt;wptr);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='ctx'> 	} else {</div><div class='del'>-		/* XXX check if swapping is necessary on BE */</div><div class='del'>-		if (ring-&gt;use_doorbell) {</div><div class='del'>-			atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='del'>-				     ring-&gt;wptr);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='del'>-		} else {</div><div class='del'>-			BUG(); /* only DOORBELL method supported on gfx10 now */</div><div class='del'>-		}</div><div class='add'>+		BUG(); /* only DOORBELL method supported on gfx10 now */</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -8317,7 +8628,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='ctx'> 		}</div><div class='ctx'> 		reg_mem_engine = 0;</div><div class='ctx'> 	} else {</div><div class='del'>-		ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp0;</div><div class='add'>+		ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp0 &lt;&lt; ring-&gt;pipe;</div><div class='ctx'> 		reg_mem_engine = 1; /* pfp */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -8353,10 +8664,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,</div><div class='ctx'> 				    (!amdgpu_sriov_vf(ring-&gt;adev) &amp;&amp; flags &amp; AMDGPU_IB_PREEMPTED) ? true : false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		/* inherit vmid from mqd */</div><div class='del'>-		control |= 0x400000;</div><div class='del'>-</div><div class='ctx'> 	amdgpu_ring_write(ring, header);</div><div class='ctx'> 	BUG_ON(ib-&gt;gpu_addr &amp; 0x3); /* Dword align */</div><div class='ctx'> 	amdgpu_ring_write(ring,</div><div class='hunk'>@@ -8376,10 +8683,6 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,</div><div class='ctx'> 	unsigned int vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='ctx'> 	u32 control = INDIRECT_BUFFER_VALID | ib-&gt;length_dw | (vmid &lt;&lt; 24);</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		/* inherit vmid from mqd */</div><div class='del'>-		control |= 0x40000000;</div><div class='del'>-</div><div class='ctx'> 	/* Currently, there is a high possibility to get wave ID mismatch</div><div class='ctx'> 	 * between ME and GDS, leading to a hw deadlock, because ME generates</div><div class='ctx'> 	 * different wave IDs than the GDS expects. This situation happens</div><div class='hunk'>@@ -8437,8 +8740,7 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> 	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='ctx'> 	amdgpu_ring_write(ring, lower_32_bits(seq));</div><div class='ctx'> 	amdgpu_ring_write(ring, upper_32_bits(seq));</div><div class='del'>-	amdgpu_ring_write(ring, ring-&gt;is_mes_queue ?</div><div class='del'>-			 (ring-&gt;hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)</div><div class='hunk'>@@ -8466,10 +8768,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,</div><div class='ctx'> static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> 					 unsigned int vmid, uint64_t pd_addr)</div><div class='ctx'> {</div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='add'>+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='ctx'> </div><div class='ctx'> 	/* compute doesn't have PFP */</div><div class='ctx'> 	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX) {</div><div class='hunk'>@@ -8620,19 +8919,9 @@ static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)</div><div class='ctx'> </div><div class='ctx'> 	cnt = (sizeof(ce_payload) &gt;&gt; 2) + 4 - 2;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v10_gfx_meta_data, ce_payload);</div><div class='del'>-		ce_payload_gpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ce_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-	} else {</div><div class='del'>-		offset = offsetof(struct v10_gfx_meta_data, ce_payload);</div><div class='del'>-		ce_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='del'>-		ce_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='del'>-	}</div><div class='add'>+	offset = offsetof(struct v10_gfx_meta_data, ce_payload);</div><div class='add'>+	ce_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='add'>+	ce_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));</div><div class='ctx'> 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |</div><div class='hunk'>@@ -8658,28 +8947,13 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)</div><div class='ctx'> 	void *de_payload_cpu_addr;</div><div class='ctx'> 	int cnt;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_gpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		de_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gds_backup) +</div><div class='del'>-			offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='del'>-		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-	} else {</div><div class='del'>-		offset = offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='del'>-		de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='add'>+	offset = offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='add'>+	de_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='add'>+	de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='ctx'> </div><div class='del'>-		gds_addr = ALIGN(amdgpu_csa_vaddr(ring-&gt;adev) +</div><div class='del'>-				 AMDGPU_CSA_SIZE - adev-&gt;gds.gds_size,</div><div class='del'>-				 PAGE_SIZE);</div><div class='del'>-	}</div><div class='add'>+	gds_addr = ALIGN(amdgpu_csa_vaddr(ring-&gt;adev) +</div><div class='add'>+			 AMDGPU_CSA_SIZE - adev-&gt;gds.gds_size,</div><div class='add'>+			 PAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);</div><div class='ctx'> 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);</div><div class='hunk'>@@ -8774,19 +9048,6 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='ctx'> 							   ref, mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,</div><div class='del'>-					 unsigned int vmid)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	uint32_t value = 0;</div><div class='del'>-</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmSQ_CMD, value);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void</div><div class='ctx'> gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 				      uint32_t me, uint32_t pipe,</div><div class='hunk'>@@ -8931,49 +9192,34 @@ static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	int i;</div><div class='ctx'> 	u8 me_id, pipe_id, queue_id;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	uint32_t mes_queue_id = entry-&gt;src_data[0];</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("IH: CP EOP\n");</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes &amp;&amp; (mes_queue_id &amp; AMDGPU_FENCE_MES_QUEUE_FLAG)) {</div><div class='del'>-		struct amdgpu_mes_queue *queue;</div><div class='del'>-</div><div class='del'>-		mes_queue_id &amp;= AMDGPU_FENCE_MES_QUEUE_ID_MASK;</div><div class='del'>-</div><div class='del'>-		spin_lock(&amp;adev-&gt;mes.queue_id_lock);</div><div class='del'>-		queue = idr_find(&amp;adev-&gt;mes.queue_id_idr, mes_queue_id);</div><div class='del'>-		if (queue) {</div><div class='del'>-			DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);</div><div class='del'>-			amdgpu_fence_process(queue-&gt;ring);</div><div class='del'>-		}</div><div class='del'>-		spin_unlock(&amp;adev-&gt;mes.queue_id_lock);</div><div class='del'>-	} else {</div><div class='del'>-		me_id = (entry-&gt;ring_id &amp; 0x0c) &gt;&gt; 2;</div><div class='del'>-		pipe_id = (entry-&gt;ring_id &amp; 0x03) &gt;&gt; 0;</div><div class='del'>-		queue_id = (entry-&gt;ring_id &amp; 0x70) &gt;&gt; 4;</div><div class='add'>+	me_id = (entry-&gt;ring_id &amp; 0x0c) &gt;&gt; 2;</div><div class='add'>+	pipe_id = (entry-&gt;ring_id &amp; 0x03) &gt;&gt; 0;</div><div class='add'>+	queue_id = (entry-&gt;ring_id &amp; 0x70) &gt;&gt; 4;</div><div class='ctx'> </div><div class='del'>-		switch (me_id) {</div><div class='del'>-		case 0:</div><div class='del'>-			if (pipe_id == 0)</div><div class='del'>-				amdgpu_fence_process(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='del'>-			else</div><div class='del'>-				amdgpu_fence_process(&amp;adev-&gt;gfx.gfx_ring[1]);</div><div class='del'>-			break;</div><div class='del'>-		case 1:</div><div class='del'>-		case 2:</div><div class='del'>-			for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-				ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='del'>-				/* Per-queue interrupt is supported for MEC starting from VI.</div><div class='del'>-				 * The interrupt can only be enabled/disabled per pipe instead</div><div class='del'>-				 * of per queue.</div><div class='del'>-				 */</div><div class='del'>-				if ((ring-&gt;me == me_id) &amp;&amp;</div><div class='del'>-				    (ring-&gt;pipe == pipe_id) &amp;&amp;</div><div class='del'>-				    (ring-&gt;queue == queue_id))</div><div class='del'>-					amdgpu_fence_process(ring);</div><div class='del'>-			}</div><div class='del'>-			break;</div><div class='add'>+	switch (me_id) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			amdgpu_fence_process(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+		else</div><div class='add'>+			amdgpu_fence_process(&amp;adev-&gt;gfx.gfx_ring[1]);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+	case 2:</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+			ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+			/* Per-queue interrupt is supported for MEC starting from VI.</div><div class='add'>+			 * The interrupt can only be enabled/disabled per pipe instead</div><div class='add'>+			 * of per queue.</div><div class='add'>+			 */</div><div class='add'>+			if ((ring-&gt;me == me_id) &amp;&amp;</div><div class='add'>+			    (ring-&gt;pipe == pipe_id) &amp;&amp;</div><div class='add'>+			    (ring-&gt;queue == queue_id))</div><div class='add'>+				amdgpu_fence_process(ring);</div><div class='ctx'> 		}</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -8984,12 +9230,39 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 					      unsigned int type,</div><div class='ctx'> 					      enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,</div><div class='del'>-			       PRIV_REG_INT_ENABLE,</div><div class='del'>-			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -8998,17 +9271,75 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					    struct amdgpu_irq_src *source,</div><div class='add'>+					    unsigned type,</div><div class='add'>+					    enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 					       struct amdgpu_irq_src *source,</div><div class='ctx'> 					       unsigned int type,</div><div class='ctx'> 					       enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,</div><div class='del'>-			       PRIV_INSTR_INT_ENABLE,</div><div class='del'>-			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    PRIV_INSTR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -9032,8 +9363,8 @@ static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,</div><div class='ctx'> 	case 0:</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='ctx'> 			ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='del'>-			/* we only enabled 1 gfx queue per pipe for now */</div><div class='del'>-			if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id)</div><div class='add'>+			if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id &amp;&amp;</div><div class='add'>+			    ring-&gt;queue == queue_id)</div><div class='ctx'> 				drm_sched_fault(&amp;ring-&gt;sched);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -9060,6 +9391,15 @@ static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_irq_src *source,</div><div class='add'>+				struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal opcode in command stream \n");</div><div class='add'>+	gfx_v10_0_handle_priv_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				   struct amdgpu_irq_src *source,</div><div class='ctx'> 				   struct amdgpu_iv_entry *entry)</div><div class='hunk'>@@ -9154,6 +9494,319 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)</div><div class='add'>+{</div><div class='add'>+	/* Header itself is a NOP packet */</div><div class='add'>+	if (num_nop == 1) {</div><div class='add'>+		amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));</div><div class='add'>+</div><div class='add'>+	/* Header is at index 0, followed by num_nops - 1 NOP packet's */</div><div class='add'>+	amdgpu_ring_insert_nop(ring, num_nop - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u32 tmp;</div><div class='add'>+	u64 addr;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	addr = amdgpu_bo_gpu_offset(ring-&gt;mqd_obj) +</div><div class='add'>+		offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);</div><div class='add'>+	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 &lt;&lt; vmid);</div><div class='add'>+	if (ring-&gt;pipe == 0)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 &lt;&lt; ring-&gt;queue);</div><div class='add'>+	else</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 &lt;&lt; ring-&gt;queue);</div><div class='add'>+</div><div class='add'>+	gfx_v10_0_ring_emit_wreg(kiq_ring,</div><div class='add'>+				 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);</div><div class='add'>+	gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,</div><div class='add'>+			       lower_32_bits(addr), upper_32_bits(addr),</div><div class='add'>+			       0, 1, 0x20);</div><div class='add'>+	gfx_v10_0_ring_emit_reg_wait(kiq_ring,</div><div class='add'>+				     SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = gfx_v10_0_kgq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("fail to init kgq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, ring);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;unmap_queues_size)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,</div><div class='add'>+				   0, 0);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* make sure dequeue is complete*/</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	nv_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+	nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to wait on hqd deactivate\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v10_0_kcq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to init kcq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, ring);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+			   gc_reg_list_10_1[i].reg_name,</div><div class='add'>+			   adev-&gt;gfx.ip_dump_core[i]);</div><div class='add'>+</div><div class='add'>+	/* print compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);</div><div class='add'>+	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.mec.num_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_pipe_per_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					if (i &amp;&amp; gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+						drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+							   "mmCP_MEC_ME2_HEADER_DUMP",</div><div class='add'>+							   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+					else</div><div class='add'>+						drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+							   gc_cp_reg_list_10[reg].reg_name,</div><div class='add'>+							   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* print gfx queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_gfx_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	index = 0;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);</div><div class='add'>+	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.me.num_me,</div><div class='add'>+		   adev-&gt;gfx.me.num_pipe_per_me,</div><div class='add'>+		   adev-&gt;gfx.me.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.me.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+						   gc_gfx_queue_reg_list_10[reg].reg_name,</div><div class='add'>+						   adev-&gt;gfx.ip_dump_gfx_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		adev-&gt;gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				/* ME0 is for GFX so start from 1 for CP */</div><div class='add'>+				nv_grbm_select(adev, adev-&gt;gfx.me.num_me + i, j, k, 0);</div><div class='add'>+</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					if (i &amp;&amp; gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+						adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+							RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));</div><div class='add'>+					else</div><div class='add'>+						adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+							RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+								       gc_cp_reg_list_10[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump gfx queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_gfx_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	index = 0;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.me.num_queue_per_pipe; k++) {</div><div class='add'>+				nv_grbm_select(adev, i, j, k, 0);</div><div class='add'>+</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					adev-&gt;gfx.ip_dump_gfx_queues[index + reg] =</div><div class='add'>+						RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+							gc_gfx_queue_reg_list_10[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* Emit the cleaner shader */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));</div><div class='add'>+	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_profile_ring_begin_use(ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_profile_ring_end_use(ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_end_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {</div><div class='ctx'> 	.name = "gfx_v10_0",</div><div class='ctx'> 	.early_init = gfx_v10_0_early_init,</div><div class='hunk'>@@ -9170,6 +9823,8 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gfx_v10_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = gfx_v10_ip_dump,</div><div class='add'>+	.print_ip_state = gfx_v10_ip_print,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {</div><div class='hunk'>@@ -9186,7 +9841,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {</div><div class='ctx'> 		7 + /* PIPELINE_SYNC */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='del'>-		2 + /* VM_FLUSH */</div><div class='add'>+		4 + /* VM_FLUSH */</div><div class='ctx'> 		8 + /* FENCE for VM_FLUSH */</div><div class='ctx'> 		20 + /* GDS switch */</div><div class='ctx'> 		4 + /* double SWITCH_BUFFER,</div><div class='hunk'>@@ -9202,7 +9857,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {</div><div class='ctx'> 		5 + /* HDP_INVL */</div><div class='ctx'> 		8 + 8 + /* FENCE x2 */</div><div class='ctx'> 		2 + /* SWITCH_BUFFER */</div><div class='del'>-		8, /* gfx_v10_0_emit_mem_sync */</div><div class='add'>+		8 + /* gfx_v10_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v10_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */</div><div class='ctx'> 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,</div><div class='ctx'> 	.emit_fence = gfx_v10_0_ring_emit_fence,</div><div class='hunk'>@@ -9212,7 +9868,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v10_0_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v10_0_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v10_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,</div><div class='ctx'> 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,</div><div class='hunk'>@@ -9222,8 +9878,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_wreg = gfx_v10_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,</div><div class='del'>-	.soft_recovery = gfx_v10_0_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,</div><div class='add'>+	.reset = gfx_v10_0_reset_kgq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v10_0_ring_begin_use,</div><div class='add'>+	.end_use = gfx_v10_0_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {</div><div class='hunk'>@@ -9243,7 +9902,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='ctx'> 		2 + /* gfx_v10_0_ring_emit_vm_flush */</div><div class='ctx'> 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */</div><div class='del'>-		8, /* gfx_v10_0_emit_mem_sync */</div><div class='add'>+		8 + /* gfx_v10_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v10_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,</div><div class='ctx'> 	.emit_fence = gfx_v10_0_ring_emit_fence,</div><div class='hunk'>@@ -9253,12 +9913,16 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v10_0_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v10_0_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v10_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_wreg = gfx_v10_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,</div><div class='ctx'> 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,</div><div class='add'>+	.reset = gfx_v10_0_reset_kcq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v10_0_ring_begin_use,</div><div class='add'>+	.end_use = gfx_v10_0_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {</div><div class='hunk'>@@ -9276,7 +9940,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {</div><div class='ctx'> 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='del'>-		2 + /* gfx_v10_0_ring_emit_vm_flush */</div><div class='ctx'> 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,</div><div class='hunk'>@@ -9289,6 +9952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {</div><div class='ctx'> 	.emit_wreg = gfx_v10_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -9314,6 +9978,11 @@ static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {</div><div class='ctx'> 	.process = gfx_v10_0_priv_reg_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {</div><div class='add'>+	.set = gfx_v10_0_set_bad_op_fault_state,</div><div class='add'>+	.process = gfx_v10_0_bad_op_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {</div><div class='ctx'> 	.set = gfx_v10_0_set_priv_inst_fault_state,</div><div class='ctx'> 	.process = gfx_v10_0_priv_inst_irq,</div><div class='hunk'>@@ -9335,6 +10004,9 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.funcs = &amp;gfx_v10_0_priv_reg_irq_funcs;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.bad_op_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.bad_op_irq.funcs = &amp;gfx_v10_0_bad_op_irq_funcs;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.funcs = &amp;gfx_v10_0_priv_inst_irq_funcs;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h<br/>new file mode 100644<br/>index 000000000000..f67569ccf9f6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0_cleaner_shader.h</a></div><div class='hunk'>@@ -0,0 +1,91 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Define the cleaner shader gfx_10_1_10 */</div><div class='add'>+static const u32 gfx_10_1_10_cleaner_shader_hex[] = {</div><div class='add'>+	0xb0804004, 0xbf8a0000,</div><div class='add'>+	0xbf068100, 0xbf840023,</div><div class='add'>+	0xbe8203b8, 0xbefc0380,</div><div class='add'>+	0x7e008480, 0x7e028480,</div><div class='add'>+	0x7e048480, 0x7e068480,</div><div class='add'>+	0x7e088480, 0x7e0a8480,</div><div class='add'>+	0x7e0c8480, 0x7e0e8480,</div><div class='add'>+	0xbefc0302, 0x80828802,</div><div class='add'>+	0xbf84fff5, 0xbe8203ff,</div><div class='add'>+	0x80000000, 0x87020102,</div><div class='add'>+	0xbf840012, 0xbefe03c1,</div><div class='add'>+	0xbeff03c1, 0xd7650001,</div><div class='add'>+	0x0001007f, 0xd7660001,</div><div class='add'>+	0x0002027e, 0x16020288,</div><div class='add'>+	0xbe8203bf, 0xbefc03c1,</div><div class='add'>+	0xd9382000, 0x00020201,</div><div class='add'>+	0xd9386040, 0x00040401,</div><div class='add'>+	0xd70f6a01, 0x000202ff,</div><div class='add'>+	0x00000400, 0x80828102,</div><div class='add'>+	0xbf84fff7, 0xbefc03ff,</div><div class='add'>+	0x00000068, 0xbe803000,</div><div class='add'>+	0xbe813000, 0xbe823000,</div><div class='add'>+	0xbe833000, 0x80fc847c,</div><div class='add'>+	0xbf84fffa, 0xbeea0480,</div><div class='add'>+	0xbeec0480, 0xbeee0480,</div><div class='add'>+	0xbef00480, 0xbef20480,</div><div class='add'>+	0xbef40480, 0xbef60480,</div><div class='add'>+	0xbef80480, 0xbefa0480,</div><div class='add'>+	0xbf810000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Define the cleaner shader gfx_10_3_0 */</div><div class='add'>+static const u32 gfx_10_3_0_cleaner_shader_hex[] = {</div><div class='add'>+	0xb0804004, 0xbf8a0000,</div><div class='add'>+	0xbe8203b8, 0xbefc0380,</div><div class='add'>+	0x7e008480, 0x7e028480,</div><div class='add'>+	0x7e048480, 0x7e068480,</div><div class='add'>+	0x7e088480, 0x7e0a8480,</div><div class='add'>+	0x7e0c8480, 0x7e0e8480,</div><div class='add'>+	0xbefc0302, 0x80828802,</div><div class='add'>+	0xbf84fff5, 0xbe8203ff,</div><div class='add'>+	0x80000000, 0x87020002,</div><div class='add'>+	0xbf840012, 0xbefe03c1,</div><div class='add'>+	0xbeff03c1, 0xd7650001,</div><div class='add'>+	0x0001007f, 0xd7660001,</div><div class='add'>+	0x0002027e, 0x16020288,</div><div class='add'>+	0xbe8203bf, 0xbefc03c1,</div><div class='add'>+	0xd9382000, 0x00020201,</div><div class='add'>+	0xd9386040, 0x00040401,</div><div class='add'>+	0xd70f6a01, 0x000202ff,</div><div class='add'>+	0x00000400, 0x80828102,</div><div class='add'>+	0xbf84fff7, 0xbefc03ff,</div><div class='add'>+	0x00000068, 0xbe803080,</div><div class='add'>+	0xbe813080, 0xbe823080,</div><div class='add'>+	0xbe833080, 0x80fc847c,</div><div class='add'>+	0xbf84fffa, 0xbeea0480,</div><div class='add'>+	0xbeec0480, 0xbeee0480,</div><div class='add'>+	0xbef00480, 0xbef20480,</div><div class='add'>+	0xbef40480, 0xbef60480,</div><div class='add'>+	0xbef80480, 0xbefa0480,</div><div class='add'>+	0xbf810000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_1_10_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v10_1_10_cleaner_shader.asm<br/>new file mode 100644<br/>index 000000000000..54f7ed9e2801<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_1_10_cleaner_shader.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v10_1_10_cleaner_shader.asm</a></div><div class='hunk'>@@ -0,0 +1,125 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+// This shader is to clean LDS, SGPRs and VGPRs. It is  first 64 Dwords or 256 bytes of 256 Dwords cleaner shader.</div><div class='add'>+</div><div class='add'>+// GFX10.1 : Clear SGPRs, VGPRs and LDS</div><div class='add'>+//   Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot</div><div class='add'>+//   Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD</div><div class='add'>+//   Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS)</div><div class='add'>+//      It takes 2 workgroups to use all of LDS: one on each CU of the WGP</div><div class='add'>+//   Each wave clears SGPRs 0 - 107</div><div class='add'>+//   Each wave clears VGPRs 0 - 63</div><div class='add'>+//   The first wave of the workgroup clears its 64KB of LDS</div><div class='add'>+//   The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup</div><div class='add'>+//       before any wave in the workgroup could end.  Without this, it is possible not all SGPRs get cleared.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+shader main</div><div class='add'>+  asic(GFX10.1)</div><div class='add'>+  type(CS)</div><div class='add'>+  wave_size(32)</div><div class='add'>+// Note: original source code from SQ team</div><div class='add'>+//</div><div class='add'>+// Create 32 waves in a threadgroup (CS waves)</div><div class='add'>+// Each allocates 64 VGPRs</div><div class='add'>+// The workgroup allocates all of LDS (64kbytes)</div><div class='add'>+//</div><div class='add'>+// Takes about 2500 clocks to run.</div><div class='add'>+//   (theorhetical fastest = 1024clks vgpr + 640lds = 1660 clks)</div><div class='add'>+//</div><div class='add'>+  S_BARRIER</div><div class='add'>+  s_cmp_eq_u32 s0, 1                                // Bit0 is set, sgpr0 is set then clear VGPRS and LDS as FW set COMPUTE_USER_DATA_0</div><div class='add'>+  s_cbranch_scc0  label_0023                        // Clean VGPRs and LDS if sgpr0 of wave is set, scc = (s0 == 1)</div><div class='add'>+</div><div class='add'>+  s_mov_b32     s2, 0x00000038  // Loop 64/8=8 times  (loop unrolled for performance)</div><div class='add'>+  s_mov_b32     m0, 0</div><div class='add'>+  //</div><div class='add'>+  // CLEAR VGPRs</div><div class='add'>+  //</div><div class='add'>+label_0005:</div><div class='add'>+  v_movreld_b32     v0, 0</div><div class='add'>+  v_movreld_b32     v1, 0</div><div class='add'>+  v_movreld_b32     v2, 0</div><div class='add'>+  v_movreld_b32     v3, 0</div><div class='add'>+  v_movreld_b32     v4, 0</div><div class='add'>+  v_movreld_b32     v5, 0</div><div class='add'>+  v_movreld_b32     v6, 0</div><div class='add'>+  v_movreld_b32     v7, 0</div><div class='add'>+  s_mov_b32         m0, s2</div><div class='add'>+  s_sub_u32     s2, s2, 8</div><div class='add'>+  s_cbranch_scc0  label_0005</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32     s2, 0x80000000                       // Bit31 is first_wave</div><div class='add'>+  s_and_b32     s2, s2, s1                           // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set</div><div class='add'>+  s_cbranch_scc0  label_0023                         // Clean LDS if its first wave of ThreadGroup/WorkGroup</div><div class='add'>+  // CLEAR LDS</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32 exec_lo, 0xffffffff</div><div class='add'>+  s_mov_b32 exec_hi, 0xffffffff</div><div class='add'>+  v_mbcnt_lo_u32_b32  v1, exec_hi, 0          // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mbcnt_hi_u32_b32  v1, exec_lo, v1        // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mul_u32_u24  v1, 0x00000008, v1          // * 8, so each thread is a double-dword address (8byte)</div><div class='add'>+  s_mov_b32     s2, 0x00000003f                    // 64 loop iterations</div><div class='add'>+  s_mov_b32     m0, 0xffffffff</div><div class='add'>+  // Clear all of LDS space</div><div class='add'>+  // Each FirstWave of WorkGroup clears 64kbyte block</div><div class='add'>+</div><div class='add'>+label_001F:</div><div class='add'>+  ds_write2_b64  v1, v[2:3], v[2:3] offset1:32</div><div class='add'>+  ds_write2_b64  v1, v[4:5], v[4:5] offset0:64 offset1:96</div><div class='add'>+  v_add_co_u32     v1, vcc, 0x00000400, v1</div><div class='add'>+  s_sub_u32     s2, s2, 1</div><div class='add'>+  s_cbranch_scc0  label_001F</div><div class='add'>+</div><div class='add'>+  //</div><div class='add'>+  // CLEAR SGPRs</div><div class='add'>+  //</div><div class='add'>+label_0023:</div><div class='add'>+  s_mov_b32     m0, 0x00000068  // Loop 108/4=27 times  (loop unrolled for performance)</div><div class='add'>+label_sgpr_loop:</div><div class='add'>+  s_movreld_b32     s0, s0</div><div class='add'>+  s_movreld_b32     s1, s0</div><div class='add'>+  s_movreld_b32     s2, s0</div><div class='add'>+  s_movreld_b32     s3, s0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop</div><div class='add'>+</div><div class='add'>+  //clear vcc</div><div class='add'>+  s_mov_b64 vcc, 0          //clear vcc</div><div class='add'>+  //s_setreg_imm32_b32 hw_reg_shader_flat_scratch_lo, 0   //clear  flat scratch lo SGPR</div><div class='add'>+  //s_setreg_imm32_b32 hw_reg_shader_flat_scratch_hi, 0    //clear  flat scratch hi SGPR</div><div class='add'>+  s_mov_b64 ttmp0, 0        //Clear ttmp0 and ttmp1</div><div class='add'>+  s_mov_b64 ttmp2, 0        //Clear ttmp2 and ttmp3</div><div class='add'>+  s_mov_b64 ttmp4, 0        //Clear ttmp4 and ttmp5</div><div class='add'>+  s_mov_b64 ttmp6, 0        //Clear ttmp6 and ttmp7</div><div class='add'>+  s_mov_b64 ttmp8, 0        //Clear ttmp8 and ttmp9</div><div class='add'>+  s_mov_b64 ttmp10, 0       //Clear ttmp10 and ttmp11</div><div class='add'>+  s_mov_b64 ttmp12, 0       //Clear ttmp12 and ttmp13</div><div class='add'>+  s_mov_b64 ttmp14, 0       //Clear ttmp14 and ttmp15</div><div class='add'>+</div><div class='add'>+ s_endpgm</div><div class='add'>+</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_3_0_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v10_3_0_cleaner_shader.asm<br/>new file mode 100644<br/>index 000000000000..0e1c246166c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_3_0_cleaner_shader.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v10_3_0_cleaner_shader.asm</a></div><div class='hunk'>@@ -0,0 +1,124 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+// This shader is to clean LDS, SGPRs and VGPRs. It is  first 64 Dwords or 256 bytes of 192 Dwords cleaner shader.</div><div class='add'>+//To turn this shader program on for complitaion change this to main and lower shader main to main_1</div><div class='add'>+</div><div class='add'>+// GFX10.3 : Clear SGPRs, VGPRs and LDS</div><div class='add'>+//   Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot</div><div class='add'>+//   Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD</div><div class='add'>+//   Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS)</div><div class='add'>+//      It takes 2 workgroups to use all of LDS: one on each CU of the WGP</div><div class='add'>+//   Each wave clears SGPRs 0 - 107</div><div class='add'>+//   Each wave clears VGPRs 0 - 63</div><div class='add'>+//   The first wave of the workgroup clears its 64KB of LDS</div><div class='add'>+//   The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup</div><div class='add'>+//       before any wave in the workgroup could end.  Without this, it is possible not all SGPRs get cleared.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+shader main</div><div class='add'>+  asic(GFX10)</div><div class='add'>+  type(CS)</div><div class='add'>+  wave_size(32)</div><div class='add'>+// Note: original source code from SQ team</div><div class='add'>+</div><div class='add'>+//</div><div class='add'>+// Create 32 waves in a threadgroup (CS waves)</div><div class='add'>+// Each allocates 64 VGPRs</div><div class='add'>+// The workgroup allocates all of LDS (64kbytes)</div><div class='add'>+//</div><div class='add'>+// Takes about 2500 clocks to run.</div><div class='add'>+//   (theorhetical fastest = 1024clks vgpr + 640lds = 1660 clks)</div><div class='add'>+//</div><div class='add'>+  S_BARRIER</div><div class='add'>+  s_mov_b32     s2, 0x00000038  // Loop 64/8=8 times  (loop unrolled for performance)</div><div class='add'>+  s_mov_b32     m0, 0</div><div class='add'>+  //</div><div class='add'>+  // CLEAR VGPRs</div><div class='add'>+  //</div><div class='add'>+label_0005:</div><div class='add'>+  v_movreld_b32     v0, 0</div><div class='add'>+  v_movreld_b32     v1, 0</div><div class='add'>+  v_movreld_b32     v2, 0</div><div class='add'>+  v_movreld_b32     v3, 0</div><div class='add'>+  v_movreld_b32     v4, 0</div><div class='add'>+  v_movreld_b32     v5, 0</div><div class='add'>+  v_movreld_b32     v6, 0</div><div class='add'>+  v_movreld_b32     v7, 0</div><div class='add'>+  s_mov_b32         m0, s2</div><div class='add'>+  s_sub_u32     s2, s2, 8</div><div class='add'>+  s_cbranch_scc0  label_0005</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32     s2, 0x80000000                     // Bit31 is first_wave</div><div class='add'>+  s_and_b32     s2, s2, s0                                  // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set</div><div class='add'>+  s_cbranch_scc0  label_0023                         // Clean LDS if its first wave of ThreadGroup/WorkGroup</div><div class='add'>+  // CLEAR LDS</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32 exec_lo, 0xffffffff</div><div class='add'>+  s_mov_b32 exec_hi, 0xffffffff</div><div class='add'>+  v_mbcnt_lo_u32_b32  v1, exec_hi, 0          // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mbcnt_hi_u32_b32  v1, exec_lo, v1        // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mul_u32_u24  v1, 0x00000008, v1          // * 8, so each thread is a double-dword address (8byte)</div><div class='add'>+  s_mov_b32     s2, 0x00000003f                    // 64 loop iterations</div><div class='add'>+  s_mov_b32     m0, 0xffffffff</div><div class='add'>+  // Clear all of LDS space</div><div class='add'>+  // Each FirstWave of WorkGroup clears 64kbyte block</div><div class='add'>+</div><div class='add'>+label_001F:</div><div class='add'>+  ds_write2_b64  v1, v[2:3], v[2:3] offset1:32</div><div class='add'>+  ds_write2_b64  v1, v[4:5], v[4:5] offset0:64 offset1:96</div><div class='add'>+  v_add_co_u32     v1, vcc, 0x00000400, v1</div><div class='add'>+  s_sub_u32     s2, s2, 1</div><div class='add'>+  s_cbranch_scc0  label_001F</div><div class='add'>+</div><div class='add'>+  //</div><div class='add'>+  // CLEAR SGPRs</div><div class='add'>+  //</div><div class='add'>+label_0023:</div><div class='add'>+  s_mov_b32     m0, 0x00000068  // Loop 108/4=27 times  (loop unrolled for performance)</div><div class='add'>+label_sgpr_loop:</div><div class='add'>+  s_movreld_b32     s0, 0</div><div class='add'>+  s_movreld_b32     s1, 0</div><div class='add'>+  s_movreld_b32     s2, 0</div><div class='add'>+  s_movreld_b32     s3, 0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop</div><div class='add'>+</div><div class='add'>+  //clear vcc</div><div class='add'>+  s_mov_b32 flat_scratch_lo, 0   //clear  flat scratch lo SGPR</div><div class='add'>+  s_mov_b32 flat_scratch_hi, 0   //clear  flat scratch hi SGPR</div><div class='add'>+  s_mov_b64 vcc, 0          //clear vcc</div><div class='add'>+  s_mov_b64 ttmp0, 0        //Clear ttmp0 and ttmp1</div><div class='add'>+  s_mov_b64 ttmp2, 0        //Clear ttmp2 and ttmp3</div><div class='add'>+  s_mov_b64 ttmp4, 0        //Clear ttmp4 and ttmp5</div><div class='add'>+  s_mov_b64 ttmp6, 0        //Clear ttmp6 and ttmp7</div><div class='add'>+  s_mov_b64 ttmp8, 0        //Clear ttmp8 and ttmp9</div><div class='add'>+  s_mov_b64 ttmp10, 0       //Clear ttmp10 and ttmp11</div><div class='add'>+  s_mov_b64 ttmp12, 0       //Clear ttmp12 and ttmp13</div><div class='add'>+  s_mov_b64 ttmp14, 0       //Clear ttmp14 and ttmp15</div><div class='add'>+</div><div class='add'>+ s_endpgm</div><div class='add'>+</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br/>index 1770e496c1b7..8a2ee2de390f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c</a></div><div class='hunk'>@@ -29,7 +29,6 @@</div><div class='ctx'> #include "amdgpu_gfx.h"</div><div class='ctx'> #include "amdgpu_psp.h"</div><div class='ctx'> #include "amdgpu_smu.h"</div><div class='del'>-#include "amdgpu_atomfirmware.h"</div><div class='ctx'> #include "imu_v11_0.h"</div><div class='ctx'> #include "soc21.h"</div><div class='ctx'> #include "nvd.h"</div><div class='hunk'>@@ -42,13 +41,15 @@</div><div class='ctx'> #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"</div><div class='ctx'> </div><div class='ctx'> #include "soc15.h"</div><div class='del'>-#include "soc15d.h"</div><div class='ctx'> #include "clearstate_gfx11.h"</div><div class='ctx'> #include "v11_structs.h"</div><div class='ctx'> #include "gfx_v11_0.h"</div><div class='add'>+#include "gfx_v11_0_cleaner_shader.h"</div><div class='ctx'> #include "gfx_v11_0_3.h"</div><div class='ctx'> #include "nbio_v4_3.h"</div><div class='ctx'> #include "mes_v11_0.h"</div><div class='add'>+#include "mes_userqueue.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='ctx'> </div><div class='ctx'> #define GFX11_NUM_GFX_RINGS		1</div><div class='ctx'> #define GFX11_MEC_HPD_SIZE	2048</div><div class='hunk'>@@ -63,10 +64,28 @@</div><div class='ctx'> #define regPC_CONFIG_CNTL_1		0x194d</div><div class='ctx'> #define regPC_CONFIG_CNTL_1_BASE_IDX	1</div><div class='ctx'> </div><div class='add'>+#define regCP_GFX_MQD_CONTROL_DEFAULT                                             0x00000100</div><div class='add'>+#define regCP_GFX_HQD_VMID_DEFAULT                                                0x00000000</div><div class='add'>+#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT                                      0x00000000</div><div class='add'>+#define regCP_GFX_HQD_QUANTUM_DEFAULT                                             0x00000a01</div><div class='add'>+#define regCP_GFX_HQD_CNTL_DEFAULT                                                0x00a00000</div><div class='add'>+#define regCP_RB_DOORBELL_CONTROL_DEFAULT                                         0x00000000</div><div class='add'>+#define regCP_GFX_HQD_RPTR_DEFAULT                                                0x00000000</div><div class='add'>+</div><div class='add'>+#define regCP_HQD_EOP_CONTROL_DEFAULT                                             0x00000006</div><div class='add'>+#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000</div><div class='add'>+#define regCP_MQD_CONTROL_DEFAULT                                                 0x00000100</div><div class='add'>+#define regCP_HQD_PQ_CONTROL_DEFAULT                                              0x00308509</div><div class='add'>+#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000</div><div class='add'>+#define regCP_HQD_PQ_RPTR_DEFAULT                                                 0x00000000</div><div class='add'>+#define regCP_HQD_PERSISTENT_STATE_DEFAULT                                        0x0be05501</div><div class='add'>+#define regCP_HQD_IB_CONTROL_DEFAULT                                              0x00300000</div><div class='add'>+</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_kicker.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");</div><div class='hunk'>@@ -93,6 +112,188 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_1_pfp.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_1_me.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_1_mec.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_1_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_pfp.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_me.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin");</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	/* SE status registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_11[] = {</div><div class='add'>+	/* compute registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_11[] = {</div><div class='add'>+	/* gfx queue registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> static const struct soc15_reg_golden golden_settings_gc_11_0[] = {</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)</div><div class='hunk'>@@ -145,14 +346,20 @@ static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	u64 shader_mc_addr;</div><div class='add'>+</div><div class='add'>+	/* Cleaner shader MC address */</div><div class='add'>+	shader_mc_addr = adev-&gt;gfx.cleaner_shader_gpu_addr &gt;&gt; 8;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |</div><div class='ctx'> 			  PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */</div><div class='ctx'> 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */</div><div class='ctx'> }</div><div class='hunk'>@@ -333,6 +540,21 @@ static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,</div><div class='ctx'> 	amdgpu_ring_write(ring, inv); /* poll interval */</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v11_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)</div><div class='add'>+{</div><div class='add'>+	/* Header itself is a NOP packet */</div><div class='add'>+	if (num_nop == 1) {</div><div class='add'>+		amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));</div><div class='add'>+</div><div class='add'>+	/* Header is at index 0, followed by num_nops - 1 NOP packet's */</div><div class='add'>+	amdgpu_ring_insert_nop(ring, num_nop - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='hunk'>@@ -381,7 +603,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	struct dma_fence *f = NULL;</div><div class='ctx'> 	unsigned index;</div><div class='ctx'> 	uint64_t gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr;</div><div class='add'>+	uint32_t *cpu_ptr;</div><div class='ctx'> 	long r;</div><div class='ctx'> </div><div class='ctx'> 	/* MES KIQ fw hasn't indirect buffer support for now */</div><div class='hunk'>@@ -391,33 +613,18 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t padding, offset;</div><div class='del'>-</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);</div><div class='del'>-		padding = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-						  AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-</div><div class='del'>-		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);</div><div class='del'>-		*cpu_ptr = cpu_to_le32(0xCAFEDEAD);</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='del'>-		cpu_ptr = &amp;adev-&gt;wb.wb[index];</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='add'>+	cpu_ptr = &amp;adev-&gt;wb.wb[index];</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='del'>-			goto err1;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);</div><div class='hunk'>@@ -444,12 +651,10 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	else</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> err2:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err1:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -467,10 +672,10 @@ static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *</div><div class='ctx'> {</div><div class='ctx'> 	const struct psp_firmware_header_v1_0 *toc_hdr;</div><div class='ctx'> 	int err = 0;</div><div class='del'>-	char fw_name[40];</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.toc_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.toc_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_toc.bin", ucode_prefix);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -509,8 +714,7 @@ static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[40];</div><div class='del'>-	char ucode_prefix[30];</div><div class='add'>+	char ucode_prefix[25];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct rlc_firmware_header_v2_0 *rlc_hdr;</div><div class='ctx'> 	uint16_t version_major;</div><div class='hunk'>@@ -519,9 +723,9 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='del'>-</div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_pfp.bin", ucode_prefix);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	/* check pfp fw hdr version to decide if enable rs64 for gfx11.*/</div><div class='hunk'>@@ -537,8 +741,9 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_me.bin", ucode_prefix);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	if (adev-&gt;gfx.rs64_enable) {</div><div class='hunk'>@@ -552,10 +757,17 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='ctx'> 		    adev-&gt;pdev-&gt;revision == 0xCE)</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/gc_11_0_0_rlc_1.bin");</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/gc_11_0_0_rlc_1.bin");</div><div class='add'>+		else if (amdgpu_is_kicker_fw(adev))</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_rlc_kicker.bin", ucode_prefix);</div><div class='ctx'> 		else</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_rlc.bin", ucode_prefix);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='hunk'>@@ -566,8 +778,9 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mec.bin", ucode_prefix);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	if (adev-&gt;gfx.rs64_enable) {</div><div class='hunk'>@@ -637,12 +850,9 @@ static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='del'>-				    volatile u32 *buffer)</div><div class='add'>+static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='ctx'> {</div><div class='del'>-	u32 count = 0, i;</div><div class='del'>-	const struct cs_section_def *sect = NULL;</div><div class='del'>-	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> 	int ctx_reg_offset;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='hunk'>@@ -650,39 +860,15 @@ static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='ctx'> 	if (buffer == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='add'>+	count = amdgpu_gfx_csb_preamble_start(buffer);</div><div class='add'>+	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);</div><div class='ctx'> </div><div class='del'>-	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='del'>-		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='del'>-			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='del'>-				buffer[count++] =</div><div class='del'>-					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='del'>-				buffer[count++] = cpu_to_le32(ext-&gt;reg_index -</div><div class='del'>-						PACKET3_SET_CONTEXT_REG_START);</div><div class='del'>-				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='del'>-					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='del'>-			} else {</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ctx_reg_offset =</div><div class='del'>-		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;</div><div class='add'>+	ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(ctx_reg_offset);</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.pa_sc_tile_steering_override);</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+	amdgpu_gfx_csb_preamble_end(buffer, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)</div><div class='hunk'>@@ -863,14 +1049,21 @@ static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,</div><div class='ctx'> #define MQD_FWWORKAREA_SIZE       484</div><div class='ctx'> #define MQD_FWWORKAREA_ALIGNMENT  256</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,</div><div class='add'>+static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,</div><div class='ctx'> 					 struct amdgpu_gfx_shadow_info *shadow_info)</div><div class='ctx'> {</div><div class='del'>-	if (adev-&gt;gfx.cp_gfx_shadow) {</div><div class='del'>-		shadow_info-&gt;shadow_size = MQD_SHADOW_BASE_SIZE;</div><div class='del'>-		shadow_info-&gt;shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;</div><div class='del'>-		shadow_info-&gt;csa_size = MQD_FWWORKAREA_SIZE;</div><div class='del'>-		shadow_info-&gt;csa_alignment = MQD_FWWORKAREA_ALIGNMENT;</div><div class='add'>+	shadow_info-&gt;shadow_size = MQD_SHADOW_BASE_SIZE;</div><div class='add'>+	shadow_info-&gt;shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;</div><div class='add'>+	shadow_info-&gt;csa_size = MQD_FWWORKAREA_SIZE;</div><div class='add'>+	shadow_info-&gt;csa_alignment = MQD_FWWORKAREA_ALIGNMENT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,</div><div class='add'>+					 struct amdgpu_gfx_shadow_info *shadow_info,</div><div class='add'>+					 bool skip_check)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;gfx.cp_gfx_shadow || skip_check) {</div><div class='add'>+		gfx_v11_0_get_gfx_shadow_info_nocheck(adev, shadow_info);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));</div><div class='hunk'>@@ -912,6 +1105,8 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		adev-&gt;gfx.config.max_hw_contexts = 8;</div><div class='ctx'> 		adev-&gt;gfx.config.sc_prim_fifo_size_frontend = 0x20;</div><div class='ctx'> 		adev-&gt;gfx.config.sc_prim_fifo_size_backend = 0x100;</div><div class='hunk'>@@ -929,9 +1124,9 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)</div><div class='ctx'> static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> 				   int me, int pipe, int queue)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	unsigned int irq_type;</div><div class='add'>+	unsigned int hw_prio;</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;gfx.gfx_ring[ring_id];</div><div class='ctx'> </div><div class='hunk'>@@ -941,6 +1136,10 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;ring_obj = NULL;</div><div class='ctx'> 	ring-&gt;use_doorbell = true;</div><div class='add'>+	if (adev-&gt;gfx.disable_kq) {</div><div class='add'>+		ring-&gt;no_scheduler = true;</div><div class='add'>+		ring-&gt;no_user_submission = true;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (!ring_id)</div><div class='ctx'> 		ring-&gt;doorbell_index = adev-&gt;doorbell_index.gfx_ring0 &lt;&lt; 1;</div><div class='hunk'>@@ -950,11 +1149,10 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> 	sprintf(ring-&gt;name, "gfx_%d.%d.%d", ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='ctx'> </div><div class='ctx'> 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring-&gt;pipe;</div><div class='del'>-	r = amdgpu_ring_init(adev, ring, 1024, &amp;adev-&gt;gfx.eop_irq, irq_type,</div><div class='del'>-			     AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-	return 0;</div><div class='add'>+	hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?</div><div class='add'>+		AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;</div><div class='add'>+	return amdgpu_ring_init(adev, ring, 1024, &amp;adev-&gt;gfx.eop_irq, irq_type,</div><div class='add'>+				hw_prio, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='hunk'>@@ -1331,30 +1529,69 @@ static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_sw_init(void *handle)</div><div class='add'>+static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, j, k, r, ring_id = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='add'>+	uint32_t inst;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for compute queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_11);</div><div class='add'>+	inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for gfx queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);</div><div class='add'>+	inst = adev-&gt;gfx.me.num_me * adev-&gt;gfx.me.num_pipe_per_me *</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_gfx_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_gfx_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int i, j, k, r, ring_id;</div><div class='ctx'> 	int xcc_id = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */</div><div class='add'>+</div><div class='add'>+	INIT_DELAYED_WORK(&amp;adev-&gt;gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(11, 0, 0):</div><div class='add'>+	case IP_VERSION(11, 0, 1):</div><div class='ctx'> 	case IP_VERSION(11, 0, 2):</div><div class='ctx'> 	case IP_VERSION(11, 0, 3):</div><div class='del'>-		adev-&gt;gfx.me.num_me = 1;</div><div class='del'>-		adev-&gt;gfx.me.num_pipe_per_me = 1;</div><div class='del'>-		adev-&gt;gfx.me.num_queue_per_pipe = 1;</div><div class='del'>-		adev-&gt;gfx.mec.num_mec = 2;</div><div class='del'>-		adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='del'>-		adev-&gt;gfx.mec.num_queue_per_pipe = 4;</div><div class='del'>-		break;</div><div class='del'>-	case IP_VERSION(11, 0, 1):</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		adev-&gt;gfx.me.num_me = 1;</div><div class='ctx'> 		adev-&gt;gfx.me.num_pipe_per_me = 1;</div><div class='del'>-		adev-&gt;gfx.me.num_queue_per_pipe = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe = 2;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_mec = 1;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='ctx'> 		adev-&gt;gfx.mec.num_queue_per_pipe = 4;</div><div class='hunk'>@@ -1369,6 +1606,115 @@ static int gfx_v11_0_sw_init(void *handle)</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(11, 0, 0):</div><div class='add'>+	case IP_VERSION(11, 0, 2):</div><div class='add'>+	case IP_VERSION(11, 0, 3):</div><div class='add'>+		if (!adev-&gt;gfx.disable_uq &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.me_fw_version  &gt;= 2420 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 2580 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 2650 &amp;&amp;</div><div class='add'>+		    adev-&gt;mes.fw_version[0] &gt;= 120) {</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_GFX] = &amp;userq_mes_funcs;</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_COMPUTE] = &amp;userq_mes_funcs;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(11, 0, 1):</div><div class='add'>+	case IP_VERSION(11, 0, 4):</div><div class='add'>+	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='add'>+		/* add firmware version checks here */</div><div class='add'>+		if (0 &amp;&amp; !adev-&gt;gfx.disable_uq) {</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_GFX] = &amp;userq_mes_funcs;</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_COMPUTE] = &amp;userq_mes_funcs;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(11, 0, 0):</div><div class='add'>+	case IP_VERSION(11, 0, 2):</div><div class='add'>+	case IP_VERSION(11, 0, 3):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version  &gt;= 2280 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 2370 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 2450  &amp;&amp;</div><div class='add'>+		    adev-&gt;mes.fw_version[0] &gt;= 99) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(11, 0, 1):</div><div class='add'>+	case IP_VERSION(11, 0, 4):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.pfp_fw_version &gt;= 102 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 66 &amp;&amp;</div><div class='add'>+		    adev-&gt;mes.fw_version[0] &gt;= 128) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 1):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.mec_fw_version &gt;= 26 &amp;&amp;</div><div class='add'>+		    adev-&gt;mes.fw_version[0] &gt;= 114) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version  &gt;= 12 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 15 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 15) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version  &gt;= 7 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 8 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 8) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &amp;&amp;</div><div class='ctx'> 	    amdgpu_sriov_is_pp_one_vf(adev))</div><div class='hunk'>@@ -1381,6 +1727,13 @@ static int gfx_v11_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	/* Bad opcode Event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR,</div><div class='add'>+			      &amp;adev-&gt;gfx.bad_op_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	/* Privileged reg */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,</div><div class='ctx'> 			      GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,</div><div class='hunk'>@@ -1418,41 +1771,71 @@ static int gfx_v11_0_sw_init(void *handle)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* set up the gfx ring */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='del'>-		for (j = 0; j &lt; adev-&gt;gfx.me.num_queue_per_pipe; j++) {</div><div class='del'>-			for (k = 0; k &lt; adev-&gt;gfx.me.num_pipe_per_me; k++) {</div><div class='del'>-				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))</div><div class='del'>-					continue;</div><div class='del'>-</div><div class='del'>-				r = gfx_v11_0_gfx_ring_init(adev, ring_id,</div><div class='del'>-							    i, k, j);</div><div class='del'>-				if (r)</div><div class='del'>-					return r;</div><div class='del'>-				ring_id++;</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings) {</div><div class='add'>+		ring_id = 0;</div><div class='add'>+		/* set up the gfx ring */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; num_queue_per_pipe; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.me.num_pipe_per_me; k++) {</div><div class='add'>+					if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))</div><div class='add'>+						continue;</div><div class='add'>+</div><div class='add'>+					r = gfx_v11_0_gfx_ring_init(adev, ring_id,</div><div class='add'>+								    i, k, j);</div><div class='add'>+					if (r)</div><div class='add'>+						return r;</div><div class='add'>+					ring_id++;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ring_id = 0;</div><div class='del'>-	/* set up the compute queues - allocate horizontally across pipes */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; ++i) {</div><div class='del'>-		for (j = 0; j &lt; adev-&gt;gfx.mec.num_queue_per_pipe; j++) {</div><div class='del'>-			for (k = 0; k &lt; adev-&gt;gfx.mec.num_pipe_per_mec; k++) {</div><div class='del'>-				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,</div><div class='del'>-								     k, j))</div><div class='del'>-					continue;</div><div class='add'>+	if (adev-&gt;gfx.num_compute_rings) {</div><div class='add'>+		ring_id = 0;</div><div class='add'>+		/* set up the compute queues - allocate horizontally across pipes */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; ++i) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_queue_per_pipe; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.mec.num_pipe_per_mec; k++) {</div><div class='add'>+					if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,</div><div class='add'>+									     k, j))</div><div class='add'>+						continue;</div><div class='ctx'> </div><div class='del'>-				r = gfx_v11_0_compute_ring_init(adev, ring_id,</div><div class='del'>-								i, k, j);</div><div class='del'>-				if (r)</div><div class='del'>-					return r;</div><div class='add'>+					r = gfx_v11_0_compute_ring_init(adev, ring_id,</div><div class='add'>+									i, k, j);</div><div class='add'>+					if (r)</div><div class='add'>+						return r;</div><div class='ctx'> </div><div class='del'>-				ring_id++;</div><div class='add'>+					ring_id++;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(11, 0, 0):</div><div class='add'>+	case IP_VERSION(11, 0, 2):</div><div class='add'>+	case IP_VERSION(11, 0, 3):</div><div class='add'>+		if ((adev-&gt;gfx.me_fw_version &gt;= 2280) &amp;&amp;</div><div class='add'>+		    (adev-&gt;gfx.mec_fw_version &gt;= 2410) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+			adev-&gt;gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		if (!amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+			adev-&gt;gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!adev-&gt;enable_mes_kiq) {</div><div class='ctx'> 		r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);</div><div class='ctx'> 		if (r) {</div><div class='hunk'>@@ -1485,6 +1868,12 @@ static int gfx_v11_0_sw_init(void *handle)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gfx_v11_0_alloc_ip_dump(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1517,10 +1906,10 @@ static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)</div><div class='ctx'> 			(void **)&amp;adev-&gt;gfx.rlc.rlc_autoload_ptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_sw_fini(void *handle)</div><div class='add'>+static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;gfx.gfx_ring[i]);</div><div class='hunk'>@@ -1534,6 +1923,8 @@ static int gfx_v11_0_sw_fini(void *handle)</div><div class='ctx'> 		amdgpu_gfx_kiq_fini(adev, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_gfx_cleaner_shader_sw_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	gfx_v11_0_pfp_fini(adev);</div><div class='ctx'> 	gfx_v11_0_me_fini(adev);</div><div class='ctx'> 	gfx_v11_0_rlc_fini(adev);</div><div class='hunk'>@@ -1544,6 +1935,12 @@ static int gfx_v11_0_sw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	gfx_v11_0_free_microcode(adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_gfx_sysfs_fini(adev);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_core);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_compute_queues);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_gfx_queues);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1613,6 +2010,7 @@ static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	u32 rb_bitmap_per_sa;</div><div class='ctx'> 	u32 rb_bitmap_width_per_sa;</div><div class='ctx'> 	u32 max_sa;</div><div class='ctx'> 	u32 active_sa_bitmap;</div><div class='hunk'>@@ -1630,12 +2028,14 @@ static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)</div><div class='ctx'> 		 adev-&gt;gfx.config.max_sh_per_se;</div><div class='ctx'> 	rb_bitmap_width_per_sa = adev-&gt;gfx.config.max_backends_per_se /</div><div class='ctx'> 				 adev-&gt;gfx.config.max_sh_per_se;</div><div class='add'>+	rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; max_sa; i++) {</div><div class='ctx'> 		if (active_sa_bitmap &amp; (1 &lt;&lt; i))</div><div class='del'>-			active_rb_bitmap |= (0x3 &lt;&lt; (i * rb_bitmap_width_per_sa));</div><div class='add'>+			active_rb_bitmap |= (rb_bitmap_per_sa &lt;&lt; (i * rb_bitmap_width_per_sa));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	active_rb_bitmap |= global_active_rb_bitmap;</div><div class='add'>+	active_rb_bitmap &amp;= global_active_rb_bitmap;</div><div class='ctx'> 	adev-&gt;gfx.config.backend_enable_mask = active_rb_bitmap;</div><div class='ctx'> 	adev-&gt;gfx.config.num_rbs = hweight32(active_rb_bitmap);</div><div class='ctx'> }</div><div class='hunk'>@@ -1674,8 +2074,10 @@ static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)</div><div class='ctx'> 	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> </div><div class='del'>-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA</div><div class='del'>-	   acccess. These should be enabled by FW for target VMIDs. */</div><div class='add'>+	/*</div><div class='add'>+	 * Initialize all compute VMIDs to have no GDS, GWS, or OA</div><div class='add'>+	 * access. These should be enabled by FW for target VMIDs.</div><div class='add'>+	 */</div><div class='ctx'> 	for (i = adev-&gt;vm_manager.first_kfd_vmid; i &lt; AMDGPU_NUM_VMID; i++) {</div><div class='ctx'> 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);</div><div class='ctx'> 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);</div><div class='hunk'>@@ -1759,26 +2161,74 @@ static void gfx_v11_0_constants_init(struct amdgpu_device *adev)</div><div class='ctx'> 	gfx_v11_0_init_gds_vmid(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 gfx_v11_0_get_cpg_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	if (me != 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v11_0_get_cpc_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * amdgpu controls only the first MEC. That's why this function only</div><div class='add'>+	 * handles the setting of interrupts for this specific MEC. All other</div><div class='add'>+	 * pipes' interrupts are set by amdkfd.</div><div class='add'>+	 */</div><div class='add'>+	if (me != 1)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);</div><div class='add'>+	case 2:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);</div><div class='add'>+	case 3:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 					       bool enable)</div><div class='ctx'> {</div><div class='del'>-	u32 tmp;</div><div class='add'>+	u32 tmp, cp_int_cntl_reg;</div><div class='add'>+	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);</div><div class='del'>-</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,</div><div class='del'>-			    enable ? 1 : 0);</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+			if (cp_int_cntl_reg) {</div><div class='add'>+				tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_init_csb(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1990,7 +2440,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 			if (version_minor == 3)</div><div class='ctx'> 				gfx_v11_0_load_rlcp_rlcv_microcode(adev);</div><div class='ctx'> 		}</div><div class='del'>-		</div><div class='add'>+</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2060,7 +2510,7 @@ static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);</div><div class='hunk'>@@ -2104,7 +2554,7 @@ static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);</div><div class='hunk'>@@ -2149,7 +2599,7 @@ static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='hunk'>@@ -2594,7 +3044,9 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)</div><div class='ctx'> 		    amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='ctx'> 			    IP_VERSION(11, 0, 4) ||</div><div class='ctx'> 		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) ||</div><div class='del'>-		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1))</div><div class='add'>+		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) ||</div><div class='add'>+		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) ||</div><div class='add'>+		    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3))</div><div class='ctx'> 			bootload_status = RREG32_SOC15(GC, 0,</div><div class='ctx'> 					regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);</div><div class='ctx'> 		else</div><div class='hunk'>@@ -2783,7 +3235,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_bo_unreserve(adev-&gt;gfx.pfp.pfp_fw_data_obj);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,</div><div class='ctx'> 		lower_32_bits(adev-&gt;gfx.pfp.pfp_fw_gpu_addr));</div><div class='hunk'>@@ -3001,7 +3453,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_bo_unreserve(adev-&gt;gfx.me.me_fw_data_obj);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode == 1)</div><div class='del'>-		adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,</div><div class='ctx'> 		lower_32_bits(adev-&gt;gfx.me.me_fw_gpu_addr));</div><div class='hunk'>@@ -3287,7 +3739,7 @@ static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring-&gt;wptr));</div><div class='ctx'> </div><div class='del'>-	/* set the wb address wether it's enabled or not */</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp;</div><div class='hunk'>@@ -3325,7 +3777,7 @@ static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 		ring-&gt;wptr = 0;</div><div class='ctx'> 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring-&gt;wptr));</div><div class='del'>-		/* Set the wb address wether it's enabled or not */</div><div class='add'>+		/* Set the wb address whether it's enabled or not */</div><div class='ctx'> 		rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp;</div><div class='hunk'>@@ -3436,7 +3888,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(fw, fw_data, fw_size);</div><div class='del'>-	</div><div class='add'>+</div><div class='ctx'> 	amdgpu_bo_kunmap(adev-&gt;gfx.mec.mec_fw_obj);</div><div class='ctx'> 	amdgpu_bo_unreserve(adev-&gt;gfx.mec.mec_fw_obj);</div><div class='ctx'> </div><div class='hunk'>@@ -3595,9 +4047,7 @@ static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);</div><div class='ctx'> 	tmp &amp;= 0xffffff00;</div><div class='ctx'> 	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-	tmp |= 0x80;</div><div class='del'>-	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3615,6 +4065,24 @@ static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)</div><div class='ctx'> 		     (adev-&gt;doorbell_index.userqueue_end * 2) &lt;&lt; 2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev,</div><div class='add'>+					   struct v11_gfx_mqd *mqd,</div><div class='add'>+					   struct amdgpu_mqd_prop *prop)</div><div class='add'>+{</div><div class='add'>+	bool priority = 0;</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	/* set up default queue priority level</div><div class='add'>+	 * 0x0 = low priority, 0x1 = high priority</div><div class='add'>+	 */</div><div class='add'>+	if (prop-&gt;hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)</div><div class='add'>+		priority = 1;</div><div class='add'>+</div><div class='add'>+	tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_queue_priority = tmp;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 				  struct amdgpu_mqd_prop *prop)</div><div class='ctx'> {</div><div class='hunk'>@@ -3632,25 +4100,22 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	mqd-&gt;cp_mqd_base_addr_hi = upper_32_bits(prop-&gt;mqd_gpu_addr);</div><div class='ctx'> </div><div class='ctx'> 	/* set up mqd control */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);</div><div class='add'>+	tmp = regCP_GFX_MQD_CONTROL_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);</div><div class='ctx'> 	mqd-&gt;cp_gfx_mqd_control = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);</div><div class='add'>+	tmp = regCP_GFX_HQD_VMID_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);</div><div class='ctx'> 	mqd-&gt;cp_gfx_hqd_vmid = 0;</div><div class='ctx'> </div><div class='del'>-	/* set up default queue priority level</div><div class='del'>-	 * 0x0 = low priority, 0x1 = high priority */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);</div><div class='del'>-	mqd-&gt;cp_gfx_hqd_queue_priority = tmp;</div><div class='add'>+	/* set up gfx queue priority */</div><div class='add'>+	gfx_v11_0_gfx_mqd_set_priority(adev, mqd, prop);</div><div class='ctx'> </div><div class='ctx'> 	/* set up time quantum */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);</div><div class='add'>+	tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);</div><div class='ctx'> 	mqd-&gt;cp_gfx_hqd_quantum = tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -3672,16 +4137,20 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> </div><div class='ctx'> 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */</div><div class='ctx'> 	rb_bufsz = order_base_2(prop-&gt;queue_size / 4) - 1;</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);</div><div class='add'>+	tmp = regCP_GFX_HQD_CNTL_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);</div><div class='ctx'> #endif</div><div class='add'>+	if (prop-&gt;tmz_queue)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);</div><div class='add'>+	if (!prop-&gt;kernel_queue)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);</div><div class='ctx'> 	mqd-&gt;cp_gfx_hqd_cntl = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* set up cp_doorbell_control */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);</div><div class='add'>+	tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;</div><div class='ctx'> 	if (prop-&gt;use_doorbell) {</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='ctx'> 				    DOORBELL_OFFSET, prop-&gt;doorbell_index);</div><div class='hunk'>@@ -3693,21 +4162,31 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	mqd-&gt;cp_rb_doorbell_control = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */</div><div class='del'>-	mqd-&gt;cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;</div><div class='ctx'> </div><div class='ctx'> 	/* active the queue */</div><div class='ctx'> 	mqd-&gt;cp_gfx_hqd_active = 1;</div><div class='ctx'> </div><div class='add'>+	/* set gfx UQ items */</div><div class='add'>+	mqd-&gt;shadow_base_lo = lower_32_bits(prop-&gt;shadow_addr);</div><div class='add'>+	mqd-&gt;shadow_base_hi = upper_32_bits(prop-&gt;shadow_addr);</div><div class='add'>+	mqd-&gt;gds_bkup_base_lo = lower_32_bits(prop-&gt;gds_bkup_addr);</div><div class='add'>+	mqd-&gt;gds_bkup_base_hi = upper_32_bits(prop-&gt;gds_bkup_addr);</div><div class='add'>+	mqd-&gt;fw_work_area_base_lo = lower_32_bits(prop-&gt;csa_addr);</div><div class='add'>+	mqd-&gt;fw_work_area_base_hi = upper_32_bits(prop-&gt;csa_addr);</div><div class='add'>+	mqd-&gt;fence_address_lo = lower_32_bits(prop-&gt;fence_address);</div><div class='add'>+	mqd-&gt;fence_address_hi = upper_32_bits(prop-&gt;fence_address);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)</div><div class='add'>+static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct v11_gfx_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='ctx'> 	int mqd_idx = ring - &amp;adev-&gt;gfx.gfx_ring[0];</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+	if (!reset &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='ctx'> 		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> 		soc21_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='hunk'>@@ -3732,22 +4211,9 @@ static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			return r;</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v11_0_gfx_init_queue(ring);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+		r = gfx_v11_0_kgq_init_queue(&amp;adev-&gt;gfx.gfx_ring[i], false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3779,14 +4245,14 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	mqd-&gt;cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);</div><div class='ctx'> </div><div class='ctx'> 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);</div><div class='add'>+	tmp = regCP_HQD_EOP_CONTROL_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,</div><div class='ctx'> 			(order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));</div><div class='ctx'> </div><div class='ctx'> 	mqd-&gt;cp_hqd_eop_control = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* enable doorbell? */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);</div><div class='add'>+	tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;</div><div class='ctx'> </div><div class='ctx'> 	if (prop-&gt;use_doorbell) {</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='hunk'>@@ -3815,7 +4281,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	mqd-&gt;cp_mqd_base_addr_hi = upper_32_bits(prop-&gt;mqd_gpu_addr);</div><div class='ctx'> </div><div class='ctx'> 	/* set MQD vmid to 0 */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);</div><div class='add'>+	tmp = regCP_MQD_CONTROL_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);</div><div class='ctx'> 	mqd-&gt;cp_mqd_control = tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -3825,7 +4291,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);</div><div class='ctx'> </div><div class='ctx'> 	/* set up the HQD, this is similar to CP_RB0_CNTL */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);</div><div class='add'>+	tmp = regCP_HQD_PQ_CONTROL_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,</div><div class='ctx'> 			    (order_base_2(prop-&gt;queue_size / 4) - 1));</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,</div><div class='hunk'>@@ -3833,8 +4299,12 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,</div><div class='ctx'> 			    prop-&gt;allow_tunneling);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='add'>+	if (prop-&gt;kernel_queue) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='add'>+	}</div><div class='add'>+	if (prop-&gt;tmz_queue)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_control = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* set the wb address whether it's enabled or not */</div><div class='hunk'>@@ -3851,7 +4321,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	tmp = 0;</div><div class='ctx'> 	/* enable the doorbell if requested */</div><div class='ctx'> 	if (prop-&gt;use_doorbell) {</div><div class='del'>-		tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);</div><div class='add'>+		tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='ctx'> 				DOORBELL_OFFSET, prop-&gt;doorbell_index);</div><div class='ctx'> </div><div class='hunk'>@@ -3866,17 +4336,17 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_doorbell_control = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */</div><div class='del'>-	mqd-&gt;cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;</div><div class='ctx'> </div><div class='ctx'> 	/* set the vmid for the queue */</div><div class='ctx'> 	mqd-&gt;cp_hqd_vmid = 0;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);</div><div class='add'>+	tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);</div><div class='ctx'> 	mqd-&gt;cp_hqd_persistent_state = tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* set MIN_IB_AVAIL_SIZE */</div><div class='del'>-	tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);</div><div class='add'>+	tmp = regCP_HQD_IB_CONTROL_DEFAULT;</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);</div><div class='ctx'> 	mqd-&gt;cp_hqd_ib_control = tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -3886,6 +4356,10 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> </div><div class='ctx'> 	mqd-&gt;cp_hqd_active = prop-&gt;hqd_active;</div><div class='ctx'> </div><div class='add'>+	/* set UQ fenceaddress */</div><div class='add'>+	mqd-&gt;fence_address_lo = lower_32_bits(prop-&gt;fence_address);</div><div class='add'>+	mqd-&gt;fence_address_hi = upper_32_bits(prop-&gt;fence_address);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4038,13 +4512,13 @@ static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='add'>+static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct v11_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='ctx'> 	int mqd_idx = ring - &amp;adev-&gt;gfx.compute_ring[0];</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+	if (!reset &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='ctx'> 		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> 		soc21_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='hunk'>@@ -4069,57 +4543,24 @@ static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-	if (unlikely(r != 0)) {</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gfx_v11_0_kiq_init_queue(ring);</div><div class='del'>-	amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-	ring-&gt;mqd_ptr = NULL;</div><div class='del'>-	amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-	ring-&gt;sched.ready = true;</div><div class='add'>+	gfx_v11_0_kiq_init_queue(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = NULL;</div><div class='del'>-	int r = 0, i;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_async_gfx_ring)</div><div class='ctx'> 		gfx_v11_0_cp_compute_enable(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			goto done;</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v11_0_kcq_init_queue(ring);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+		r = gfx_v11_0_kcq_init_queue(&amp;adev-&gt;gfx.compute_ring[i], false);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_gfx_enable_kcq(adev, 0);</div><div class='del'>-done:</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_gfx_enable_kcq(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4172,11 +4613,23 @@ static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='del'>-		r = amdgpu_ring_test_helper(ring);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	if (adev-&gt;gfx.disable_kq) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+			ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+			/* we don't want to set ring-&gt;ready */</div><div class='add'>+			r = amdgpu_ring_test_ring(ring);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='add'>+		if (amdgpu_async_gfx_ring)</div><div class='add'>+			amdgpu_gfx_disable_kgq(adev, 0);</div><div class='add'>+	} else {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+			ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+			r = amdgpu_ring_test_helper(ring);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='hunk'>@@ -4204,13 +4657,14 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='del'>-	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?</div><div class='del'>-		false : true;</div><div class='add'>+	value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfxhub.funcs-&gt;set_fault_enable_default(adev, value);</div><div class='del'>-	amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);</div><div class='add'>+	/* TODO investigate why this and the hdp flush above is needed,</div><div class='add'>+	 * are we missing a flush somewhere else? */</div><div class='add'>+	adev-&gt;gmc.gmc_funcs-&gt;flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -4283,21 +4737,24 @@ static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_hw_init(void *handle)</div><div class='add'>+static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_cleaner_shader_init(adev, adev-&gt;gfx.cleaner_shader_size,</div><div class='add'>+				       adev-&gt;gfx.cleaner_shader_ptr);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {</div><div class='ctx'> 		if (adev-&gt;gfx.imu.funcs) {</div><div class='ctx'> 			/* RLC autoload sequence 1: Program rlc ram */</div><div class='ctx'> 			if (adev-&gt;gfx.imu.funcs-&gt;program_rlc_ram)</div><div class='ctx'> 				adev-&gt;gfx.imu.funcs-&gt;program_rlc_ram(adev);</div><div class='add'>+			/* rlc autoload firmware */</div><div class='add'>+			r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='ctx'> 		}</div><div class='del'>-		/* rlc autoload firmware */</div><div class='del'>-		r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='ctx'> 			if (adev-&gt;gfx.imu.funcs &amp;&amp; (amdgpu_dpm &gt; 0)) {</div><div class='hunk'>@@ -4346,11 +4803,9 @@ static int gfx_v11_0_hw_init(void *handle)</div><div class='ctx'> 		 * loaded firstly, so in direct type, it has to load smc ucode</div><div class='ctx'> 		 * here before rlc.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='del'>-			r = amdgpu_pm_load_smu_firmware(adev, NULL);</div><div class='del'>-			if (r)</div><div class='del'>-				return r;</div><div class='del'>-		}</div><div class='add'>+		r = amdgpu_pm_load_smu_firmware(adev, NULL);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	gfx_v11_0_constants_init(adev);</div><div class='hunk'>@@ -4382,15 +4837,63 @@ static int gfx_v11_0_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_hw_fini(void *handle)</div><div class='add'>+static int gfx_v11_0_set_userq_eop_interrupts(struct amdgpu_device *adev,</div><div class='add'>+					      bool enable)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	unsigned int irq_type;</div><div class='add'>+	int m, p, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;userq_funcs[AMDGPU_HW_IP_GFX]) {</div><div class='add'>+		for (m = 0; m &lt; adev-&gt;gfx.me.num_me; m++) {</div><div class='add'>+			for (p = 0; p &lt; adev-&gt;gfx.me.num_pipe_per_me; p++) {</div><div class='add'>+				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;</div><div class='add'>+				if (enable)</div><div class='add'>+					r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				else</div><div class='add'>+					r = amdgpu_irq_put(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				if (r)</div><div class='add'>+					return r;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;userq_funcs[AMDGPU_HW_IP_COMPUTE]) {</div><div class='add'>+		for (m = 0; m &lt; adev-&gt;gfx.mec.num_mec; ++m) {</div><div class='add'>+			for (p = 0; p &lt; adev-&gt;gfx.mec.num_pipe_per_mec; p++) {</div><div class='add'>+				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP</div><div class='add'>+					+ (m * adev-&gt;gfx.mec.num_pipe_per_mec)</div><div class='add'>+					+ p;</div><div class='add'>+				if (enable)</div><div class='add'>+					r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				else</div><div class='add'>+					r = amdgpu_irq_put(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				if (r)</div><div class='add'>+					return r;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;gfx.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	gfx_v11_0_set_userq_eop_interrupts(adev, false);</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;no_hw_access) {</div><div class='del'>-		if (amdgpu_async_gfx_ring) {</div><div class='add'>+		if (amdgpu_async_gfx_ring &amp;&amp;</div><div class='add'>+		    !adev-&gt;gfx.disable_kq) {</div><div class='ctx'> 			if (amdgpu_gfx_disable_kgq(adev, 0))</div><div class='ctx'> 				DRM_ERROR("KGQ disable failed\n");</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4419,19 +4922,19 @@ static int gfx_v11_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_suspend(void *handle)</div><div class='add'>+static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v11_0_hw_fini(handle);</div><div class='add'>+	return gfx_v11_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_resume(void *handle)</div><div class='add'>+static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v11_0_hw_init(handle);</div><div class='add'>+	return gfx_v11_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v11_0_is_idle(void *handle)</div><div class='add'>+static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),</div><div class='ctx'> 				GRBM_STATUS, GUI_ACTIVE))</div><div class='hunk'>@@ -4440,11 +4943,11 @@ static bool gfx_v11_0_is_idle(void *handle)</div><div class='ctx'> 		return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -4458,8 +4961,8 @@ static int gfx_v11_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='del'>-					     int req)</div><div class='add'>+int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='add'>+				      bool req)</div><div class='ctx'> {</div><div class='ctx'> 	u32 i, tmp, val;</div><div class='ctx'> </div><div class='hunk'>@@ -4490,12 +4993,14 @@ static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_soft_reset(void *handle)</div><div class='add'>+static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	int r, i, j, k;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);</div><div class='hunk'>@@ -4504,16 +5009,11 @@ static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-	gfx_v11_0_set_safe_mode(adev, 0);</div><div class='del'>-</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; ++i) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;gfx.mec.num_queue_per_pipe; j++) {</div><div class='ctx'> 			for (k = 0; k &lt; adev-&gt;gfx.mec.num_pipe_per_mec; k++) {</div><div class='del'>-				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);</div><div class='del'>-				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);</div><div class='add'>+				soc21_grbm_select(adev, i, k, j, 0);</div><div class='ctx'> </div><div class='ctx'> 				WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);</div><div class='ctx'> 				WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='hunk'>@@ -4523,20 +5023,20 @@ static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; ++i) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;gfx.me.num_queue_per_pipe; j++) {</div><div class='ctx'> 			for (k = 0; k &lt; adev-&gt;gfx.me.num_pipe_per_me; k++) {</div><div class='del'>-				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);</div><div class='del'>-				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);</div><div class='del'>-				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);</div><div class='add'>+				soc21_grbm_select(adev, i, k, j, 0);</div><div class='ctx'> </div><div class='ctx'> 				WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> </div><div class='ctx'> 	/* Try to acquire the gfx mutex before access to CP_VMID_RESET */</div><div class='del'>-	r = gfx_v11_0_request_gfx_index_mutex(adev, 1);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='add'>+	r = gfx_v11_0_request_gfx_index_mutex(adev, true);</div><div class='ctx'> 	if (r) {</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='ctx'> 		DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4550,7 +5050,8 @@ static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);</div><div class='ctx'> </div><div class='ctx'> 	/* release the gfx mutex */</div><div class='del'>-	r = gfx_v11_0_request_gfx_index_mutex(adev, 0);</div><div class='add'>+	r = gfx_v11_0_request_gfx_index_mutex(adev, false);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("Failed to release the gfx mutex during soft reset\n");</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -4618,15 +5119,15 @@ static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-	gfx_v11_0_unset_safe_mode(adev, 0);</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> </div><div class='ctx'> 	return gfx_v11_0_cp_resume(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v11_0_check_soft_reset(void *handle)</div><div class='add'>+static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	long tmo = msecs_to_jiffies(1000);</div><div class='ctx'> </div><div class='hunk'>@@ -4647,12 +5148,13 @@ static bool gfx_v11_0_check_soft_reset(void *handle)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_post_soft_reset(void *handle)</div><div class='add'>+static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * GFX soft reset will impact MES, need resume MES when do GFX soft reset</div><div class='ctx'> 	 */</div><div class='del'>-	return amdgpu_mes_resume((struct amdgpu_device *)handle);</div><div class='add'>+	return amdgpu_mes_resume(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4713,15 +5215,40 @@ static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,</div><div class='ctx'> 				    (1 &lt;&lt; (oa_size + oa_base)) - (1 &lt;&lt; oa_base));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_early_init(void *handle)</div><div class='add'>+static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_user_queue) {</div><div class='add'>+	case -1:</div><div class='add'>+	case 0:</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.disable_kq = false;</div><div class='add'>+		adev-&gt;gfx.disable_uq = true;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		adev-&gt;gfx.disable_kq = false;</div><div class='add'>+		adev-&gt;gfx.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		adev-&gt;gfx.disable_kq = true;</div><div class='add'>+		adev-&gt;gfx.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.funcs = &amp;gfx_v11_0_gfx_funcs;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;</div><div class='del'>-	adev-&gt;gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),</div><div class='del'>-					  AMDGPU_MAX_COMPUTE_RINGS);</div><div class='add'>+	if (adev-&gt;gfx.disable_kq) {</div><div class='add'>+		/* We need one GFX ring temporarily to set up</div><div class='add'>+		 * the clear state.</div><div class='add'>+		 */</div><div class='add'>+		adev-&gt;gfx.num_gfx_rings = 1;</div><div class='add'>+		adev-&gt;gfx.num_compute_rings = 0;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;</div><div class='add'>+		adev-&gt;gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),</div><div class='add'>+						  AMDGPU_MAX_COMPUTE_RINGS);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	gfx_v11_0_set_kiq_pm4_funcs(adev);</div><div class='ctx'> 	gfx_v11_0_set_ring_funcs(adev);</div><div class='hunk'>@@ -4736,9 +5263,9 @@ static int gfx_v11_0_early_init(void *handle)</div><div class='ctx'> 	return gfx_v11_0_init_microcode(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_late_init(void *handle)</div><div class='add'>+static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='hunk'>@@ -4749,6 +5276,14 @@ static int gfx_v11_0_late_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = gfx_v11_0_set_userq_eop_interrupts(adev, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5035,24 +5570,31 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)</div><div class='ctx'> {</div><div class='del'>-	u32 data;</div><div class='add'>+	u32 reg, pre_data, data;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);</div><div class='add'>+	if (amdgpu_sriov_is_pp_one_vf(adev) &amp;&amp; !amdgpu_sriov_runtime(adev))</div><div class='add'>+		pre_data = RREG32_NO_KIQ(reg);</div><div class='add'>+	else</div><div class='add'>+		pre_data = RREG32(reg);</div><div class='ctx'> </div><div class='del'>-	data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);</div><div class='del'>-</div><div class='del'>-	data &amp;= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;</div><div class='add'>+	data = pre_data &amp; (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);</div><div class='ctx'> 	data |= (vmid &amp; RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) &lt;&lt; RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;</div><div class='ctx'> </div><div class='del'>-	WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);</div><div class='del'>-</div><div class='add'>+	if (pre_data != data) {</div><div class='add'>+		if (amdgpu_sriov_is_pp_one_vf(adev) &amp;&amp; !amdgpu_sriov_runtime(adev)) {</div><div class='add'>+			WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);</div><div class='add'>+		} else</div><div class='add'>+			WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);</div><div class='add'>+	}</div><div class='ctx'> 	amdgpu_gfx_off_ctrl(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	if (ring</div><div class='ctx'> 		&amp;&amp; amdgpu_sriov_is_pp_one_vf(adev)</div><div class='add'>+		&amp;&amp; (pre_data != data)</div><div class='ctx'> 		&amp;&amp; ((ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX)</div><div class='ctx'> 			|| (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE))) {</div><div class='del'>-		uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);</div><div class='ctx'> 		amdgpu_ring_emit_wreg(ring, reg, data);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -5089,6 +5631,8 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 		case IP_VERSION(11, 0, 4):</div><div class='ctx'> 		case IP_VERSION(11, 5, 0):</div><div class='ctx'> 		case IP_VERSION(11, 5, 1):</div><div class='add'>+		case IP_VERSION(11, 5, 2):</div><div class='add'>+		case IP_VERSION(11, 5, 3):</div><div class='ctx'> 			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='hunk'>@@ -5106,10 +5650,10 @@ static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -5125,6 +5669,8 @@ static int gfx_v11_0_set_powergating_state(void *handle,</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		if (!enable)</div><div class='ctx'> 			amdgpu_gfx_off_ctrl(adev, false);</div><div class='ctx'> </div><div class='hunk'>@@ -5141,10 +5687,10 @@ static int gfx_v11_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v11_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 	        return 0;</div><div class='hunk'>@@ -5157,6 +5703,8 @@ static int gfx_v11_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 	        gfx_v11_0_update_gfx_clock_gating(adev,</div><div class='ctx'> 	                        state ==  AMD_CG_STATE_GATE);</div><div class='ctx'> 	        break;</div><div class='hunk'>@@ -5167,9 +5715,9 @@ static int gfx_v11_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gfx_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	/* AMD_CG_SUPPORT_GFX_MGCG */</div><div class='hunk'>@@ -5298,7 +5846,7 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='ctx'> 		}</div><div class='ctx'> 		reg_mem_engine = 0;</div><div class='ctx'> 	} else {</div><div class='del'>-		ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp0;</div><div class='add'>+		ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp0 &lt;&lt; ring-&gt;pipe;</div><div class='ctx'> 		reg_mem_engine = 1; /* pfp */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -5316,8 +5864,6 @@ static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,</div><div class='ctx'> 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='ctx'> 	u32 header, control = 0;</div><div class='ctx'> </div><div class='del'>-	BUG_ON(ib-&gt;flags &amp; AMDGPU_IB_FLAG_CE);</div><div class='del'>-</div><div class='ctx'> 	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);</div><div class='ctx'> </div><div class='ctx'> 	control |= ib-&gt;length_dw | (vmid &lt;&lt; 24);</div><div class='hunk'>@@ -5328,15 +5874,11 @@ static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,</div><div class='ctx'> 		if (flags &amp; AMDGPU_IB_PREEMPTED)</div><div class='ctx'> 			control |= INDIRECT_BUFFER_PRE_RESUME(1);</div><div class='ctx'> </div><div class='del'>-		if (vmid)</div><div class='add'>+		if (vmid &amp;&amp; !ring-&gt;adev-&gt;gfx.rs64_enable)</div><div class='ctx'> 			gfx_v11_0_ring_emit_de_meta(ring,</div><div class='del'>-				    (!amdgpu_sriov_vf(ring-&gt;adev) &amp;&amp; flags &amp; AMDGPU_IB_PREEMPTED) ? true : false);</div><div class='add'>+				!amdgpu_sriov_vf(ring-&gt;adev) &amp;&amp; (flags &amp; AMDGPU_IB_PREEMPTED));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		/* inherit vmid from mqd */</div><div class='del'>-		control |= 0x400000;</div><div class='del'>-</div><div class='ctx'> 	amdgpu_ring_write(ring, header);</div><div class='ctx'> 	BUG_ON(ib-&gt;gpu_addr &amp; 0x3); /* Dword align */</div><div class='ctx'> 	amdgpu_ring_write(ring,</div><div class='hunk'>@@ -5356,10 +5898,6 @@ static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,</div><div class='ctx'> 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='ctx'> 	u32 control = INDIRECT_BUFFER_VALID | ib-&gt;length_dw | (vmid &lt;&lt; 24);</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		/* inherit vmid from mqd */</div><div class='del'>-		control |= 0x40000000;</div><div class='del'>-</div><div class='ctx'> 	/* Currently, there is a high possibility to get wave ID mismatch</div><div class='ctx'> 	 * between ME and GDS, leading to a hw deadlock, because ME generates</div><div class='ctx'> 	 * different wave IDs than the GDS expects. This situation happens</div><div class='hunk'>@@ -5397,11 +5935,7 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));</div><div class='ctx'> 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |</div><div class='ctx'> 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |</div><div class='del'>-				 PACKET3_RELEASE_MEM_GCR_GL2_INV |</div><div class='del'>-				 PACKET3_RELEASE_MEM_GCR_GL2_US |</div><div class='del'>-				 PACKET3_RELEASE_MEM_GCR_GL1_INV |</div><div class='del'>-				 PACKET3_RELEASE_MEM_GCR_GLV_INV |</div><div class='del'>-				 PACKET3_RELEASE_MEM_GCR_GLM_INV |</div><div class='add'>+				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */</div><div class='ctx'> 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |</div><div class='ctx'> 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |</div><div class='ctx'> 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |</div><div class='hunk'>@@ -5421,8 +5955,7 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> 	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='ctx'> 	amdgpu_ring_write(ring, lower_32_bits(seq));</div><div class='ctx'> 	amdgpu_ring_write(ring, upper_32_bits(seq));</div><div class='del'>-	amdgpu_ring_write(ring, ring-&gt;is_mes_queue ?</div><div class='del'>-			 (ring-&gt;hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)</div><div class='hunk'>@@ -5450,10 +5983,7 @@ static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,</div><div class='ctx'> static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> 					 unsigned vmid, uint64_t pd_addr)</div><div class='ctx'> {</div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='add'>+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='ctx'> </div><div class='ctx'> 	/* compute doesn't have PFP */</div><div class='ctx'> 	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX) {</div><div class='hunk'>@@ -5465,6 +5995,7 @@ static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> 	/* Make sure that we can't skip the SET_Q_MODE packets when the VM</div><div class='ctx'> 	 * changed in any way.</div><div class='ctx'> 	 */</div><div class='add'>+	ring-&gt;set_q_mode_offs = 0;</div><div class='ctx'> 	ring-&gt;set_q_mode_ptr = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5631,6 +6162,9 @@ static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='ctx'> 	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;enable_mes)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -5678,28 +6212,13 @@ static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)</div><div class='ctx'> 	void *de_payload_cpu_addr;</div><div class='ctx'> 	int cnt;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_gpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		de_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gds_backup) +</div><div class='del'>-			offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='del'>-		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-	} else {</div><div class='del'>-		offset = offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='del'>-		de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='add'>+	offset = offsetof(struct v10_gfx_meta_data, de_payload);</div><div class='add'>+	de_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='add'>+	de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='ctx'> </div><div class='del'>-		gds_addr = ALIGN(amdgpu_csa_vaddr(ring-&gt;adev) +</div><div class='del'>-				 AMDGPU_CSA_SIZE - adev-&gt;gds.gds_size,</div><div class='del'>-				 PAGE_SIZE);</div><div class='del'>-	}</div><div class='add'>+	gds_addr = ALIGN(amdgpu_csa_vaddr(ring-&gt;adev) +</div><div class='add'>+			 AMDGPU_CSA_SIZE - adev-&gt;gds.gds_size,</div><div class='add'>+			 PAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);</div><div class='ctx'> 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);</div><div class='hunk'>@@ -5786,19 +6305,6 @@ static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='ctx'> 			       ref, mask, 0x20);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,</div><div class='del'>-					 unsigned vmid)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	uint32_t value = 0;</div><div class='del'>-</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);</div><div class='del'>-	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);</div><div class='del'>-	WREG32_SOC15(GC, 0, regSQ_CMD, value);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void</div><div class='ctx'> gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 				      uint32_t me, uint32_t pipe,</div><div class='hunk'>@@ -5936,25 +6442,23 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,</div><div class='ctx'> 			     struct amdgpu_irq_src *source,</div><div class='ctx'> 			     struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	u32 doorbell_offset = entry-&gt;src_data[0];</div><div class='ctx'> 	u8 me_id, pipe_id, queue_id;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	uint32_t mes_queue_id = entry-&gt;src_data[0];</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("IH: CP EOP\n");</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes &amp;&amp; (mes_queue_id &amp; AMDGPU_FENCE_MES_QUEUE_FLAG)) {</div><div class='del'>-		struct amdgpu_mes_queue *queue;</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; doorbell_offset) {</div><div class='add'>+		struct amdgpu_userq_fence_driver *fence_drv = NULL;</div><div class='add'>+		struct xarray *xa = &amp;adev-&gt;userq_xa;</div><div class='add'>+		unsigned long flags;</div><div class='ctx'> </div><div class='del'>-		mes_queue_id &amp;= AMDGPU_FENCE_MES_QUEUE_ID_MASK;</div><div class='del'>-</div><div class='del'>-		spin_lock(&amp;adev-&gt;mes.queue_id_lock);</div><div class='del'>-		queue = idr_find(&amp;adev-&gt;mes.queue_id_idr, mes_queue_id);</div><div class='del'>-		if (queue) {</div><div class='del'>-			DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);</div><div class='del'>-			amdgpu_fence_process(queue-&gt;ring);</div><div class='del'>-		}</div><div class='del'>-		spin_unlock(&amp;adev-&gt;mes.queue_id_lock);</div><div class='add'>+		xa_lock_irqsave(xa, flags);</div><div class='add'>+		fence_drv = xa_load(xa, doorbell_offset);</div><div class='add'>+		if (fence_drv)</div><div class='add'>+			amdgpu_userq_fence_driver_process(fence_drv);</div><div class='add'>+		xa_unlock_irqrestore(xa, flags);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		me_id = (entry-&gt;ring_id &amp; 0x0c) &gt;&gt; 2;</div><div class='ctx'> 		pipe_id = (entry-&gt;ring_id &amp; 0x03) &gt;&gt; 0;</div><div class='hunk'>@@ -5989,15 +6493,42 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 					      struct amdgpu_irq_src *source,</div><div class='del'>-					      unsigned type,</div><div class='add'>+					      unsigned int type,</div><div class='ctx'> 					      enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,</div><div class='del'>-			       PRIV_REG_INT_ENABLE,</div><div class='del'>-			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -6006,17 +6537,75 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					    struct amdgpu_irq_src *source,</div><div class='add'>+					    unsigned type,</div><div class='add'>+					    enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v11_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 					       struct amdgpu_irq_src *source,</div><div class='del'>-					       unsigned type,</div><div class='add'>+					       unsigned int type,</div><div class='ctx'> 					       enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,</div><div class='del'>-			       PRIV_INSTR_INT_ENABLE,</div><div class='del'>-			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    PRIV_INSTR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -6036,27 +6625,29 @@ static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,</div><div class='ctx'> 	pipe_id = (entry-&gt;ring_id &amp; 0x03) &gt;&gt; 0;</div><div class='ctx'> 	queue_id = (entry-&gt;ring_id &amp; 0x70) &gt;&gt; 4;</div><div class='ctx'> </div><div class='del'>-	switch (me_id) {</div><div class='del'>-	case 0:</div><div class='del'>-		for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='del'>-			ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='del'>-			/* we only enabled 1 gfx queue per pipe for now */</div><div class='del'>-			if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id)</div><div class='del'>-				drm_sched_fault(&amp;ring-&gt;sched);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-	case 2:</div><div class='del'>-		for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-			ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='del'>-			if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id &amp;&amp;</div><div class='del'>-			    ring-&gt;queue == queue_id)</div><div class='del'>-				drm_sched_fault(&amp;ring-&gt;sched);</div><div class='add'>+	if (!adev-&gt;gfx.disable_kq) {</div><div class='add'>+		switch (me_id) {</div><div class='add'>+		case 0:</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+				ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+				if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id &amp;&amp;</div><div class='add'>+				    ring-&gt;queue == queue_id)</div><div class='add'>+					drm_sched_fault(&amp;ring-&gt;sched);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+		case 2:</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+				ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+				if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id &amp;&amp;</div><div class='add'>+				    ring-&gt;queue == queue_id)</div><div class='add'>+					drm_sched_fault(&amp;ring-&gt;sched);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			BUG();</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BUG();</div><div class='del'>-		break;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6069,6 +6660,15 @@ static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_irq_src *source,</div><div class='add'>+				struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal opcode in command stream \n");</div><div class='add'>+	gfx_v11_0_handle_priv_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				   struct amdgpu_irq_src *source,</div><div class='ctx'> 				   struct amdgpu_iv_entry *entry)</div><div class='hunk'>@@ -6155,6 +6755,426 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* Disable the pipe reset until the CPFW fully support it.*/</div><div class='add'>+	dev_warn_once(adev-&gt;dev, "The CPFW hasn't support pipe reset yet.\n");</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int gfx_v11_reset_gfx_pipe(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t reset_pipe = 0, clean_pipe = 0;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!gfx_v11_pipe_reset_support(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	gfx_v11_0_set_safe_mode(adev, 0);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc21_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+</div><div class='add'>+	switch (ring-&gt;pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE0_RESET, 1);</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE0_RESET, 1);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE0_RESET, 0);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE0_RESET, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE1_RESET, 1);</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE1_RESET, 1);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE1_RESET, 0);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE1_RESET, 0);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);</div><div class='add'>+</div><div class='add'>+	r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) &lt;&lt; 2) -</div><div class='add'>+						RS64_FW_UC_START_ADDR_LO;</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v11_0_unset_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "The ring %s pipe reset to the ME firmware start PC: %s\n", ring-&gt;name,</div><div class='add'>+			r == 0 ? "successfully" : "failed");</div><div class='add'>+	/* FIXME: Sometimes driver can't cache the ME firmware start PC correctly,</div><div class='add'>+	 * so the pipe reset status relies on the later gfx ring test result.</div><div class='add'>+	 */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_reset_legacy_queue(ring-&gt;adev, ring, vmid, false);</div><div class='add'>+	if (r) {</div><div class='add'>+</div><div class='add'>+		dev_warn(adev-&gt;dev, "reset via MES failed and try pipe reset %d\n", r);</div><div class='add'>+		r = gfx_v11_reset_gfx_pipe(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v11_0_kgq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to init kgq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_map_legacy_queue(adev, ring);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to remap kgq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t reset_pipe = 0, clean_pipe = 0;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!gfx_v11_pipe_reset_support(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	gfx_v11_0_set_safe_mode(adev, 0);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc21_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+</div><div class='add'>+	reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);</div><div class='add'>+	clean_pipe = reset_pipe;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.rs64_enable) {</div><div class='add'>+</div><div class='add'>+		switch (ring-&gt;pipe) {</div><div class='add'>+		case 0:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE0_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE0_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE1_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE1_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE2_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE2_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE3_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE3_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);</div><div class='add'>+		r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) &lt;&lt; 2) -</div><div class='add'>+					RS64_FW_UC_START_ADDR_LO;</div><div class='add'>+	} else {</div><div class='add'>+		if (ring-&gt;me == 1) {</div><div class='add'>+			switch (ring-&gt;pipe) {</div><div class='add'>+			case 0:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE0_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE0_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			case 1:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE1_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE1_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			case 2:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE2_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE2_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			case 3:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE3_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE3_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			/* mec1 fw pc: CP_MEC1_INSTR_PNTR */</div><div class='add'>+		} else {</div><div class='add'>+			switch (ring-&gt;pipe) {</div><div class='add'>+			case 0:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE0_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE0_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			case 1:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE1_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE1_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			case 2:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE2_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE2_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			case 3:</div><div class='add'>+				reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE3_RESET, 1);</div><div class='add'>+				clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME2_PIPE3_RESET, 0);</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			/* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */</div><div class='add'>+		}</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);</div><div class='add'>+		r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v11_0_unset_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "The ring %s pipe resets to MEC FW start PC: %s\n", ring-&gt;name,</div><div class='add'>+			r == 0 ? "successfully" : "failed");</div><div class='add'>+	/*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe</div><div class='add'>+	 * reset status relies on the compute ring test result.</div><div class='add'>+	 */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_reset_legacy_queue(ring-&gt;adev, ring, vmid, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "fail(%d) to reset kcq and try pipe reset\n", r);</div><div class='add'>+		r = gfx_v11_0_reset_compute_pipe(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v11_0_kcq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to init kcq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	r = amdgpu_mes_map_legacy_queue(adev, ring);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to remap kcq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+			   gc_reg_list_11_0[i].reg_name,</div><div class='add'>+			   adev-&gt;gfx.ip_dump_core[i]);</div><div class='add'>+</div><div class='add'>+	/* print compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_11);</div><div class='add'>+	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.mec.num_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_pipe_per_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					if (i &amp;&amp; gc_cp_reg_list_11[reg].reg_offset == regCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+						drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+							   "regCP_MEC_ME2_HEADER_DUMP",</div><div class='add'>+							   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+					else</div><div class='add'>+						drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+							   gc_cp_reg_list_11[reg].reg_name,</div><div class='add'>+							   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* print gfx queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_gfx_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	index = 0;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);</div><div class='add'>+	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.me.num_me,</div><div class='add'>+		   adev-&gt;gfx.me.num_pipe_per_me,</div><div class='add'>+		   adev-&gt;gfx.me.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.me.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+						   gc_gfx_queue_reg_list_11[reg].reg_name,</div><div class='add'>+						   adev-&gt;gfx.ip_dump_gfx_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		adev-&gt;gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i]));</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_11);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				/* ME0 is for GFX so start from 1 for CP */</div><div class='add'>+				soc21_grbm_select(adev, adev-&gt;gfx.me.num_me + i, j, k, 0);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					if (i &amp;&amp;</div><div class='add'>+					    gc_cp_reg_list_11[reg].reg_offset ==</div><div class='add'>+						    regCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+						adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+							RREG32(SOC15_REG_OFFSET(GC, 0,</div><div class='add'>+							       regCP_MEC_ME2_HEADER_DUMP));</div><div class='add'>+					else</div><div class='add'>+						adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+							RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+								       gc_cp_reg_list_11[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump gfx queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_gfx_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	index = 0;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_11);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.me.num_queue_per_pipe; k++) {</div><div class='add'>+				soc21_grbm_select(adev, i, j, k, 0);</div><div class='add'>+</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					adev-&gt;gfx.ip_dump_gfx_queues[index + reg] =</div><div class='add'>+						RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+							gc_gfx_queue_reg_list_11[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v11_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* Emit the cleaner shader */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));</div><div class='add'>+	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v11_0_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_profile_ring_begin_use(ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v11_0_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_profile_ring_end_use(ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_end_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {</div><div class='ctx'> 	.name = "gfx_v11_0",</div><div class='ctx'> 	.early_init = gfx_v11_0_early_init,</div><div class='hunk'>@@ -6173,6 +7193,8 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = gfx_v11_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gfx_v11_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = gfx_v11_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = gfx_v11_ip_dump,</div><div class='add'>+	.print_ip_state = gfx_v11_ip_print,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {</div><div class='hunk'>@@ -6191,7 +7213,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {</div><div class='ctx'> 		7 + /* PIPELINE_SYNC */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='del'>-		2 + /* VM_FLUSH */</div><div class='add'>+		4 + /* VM_FLUSH */</div><div class='ctx'> 		8 + /* FENCE for VM_FLUSH */</div><div class='ctx'> 		20 + /* GDS switch */</div><div class='ctx'> 		5 + /* COND_EXEC */</div><div class='hunk'>@@ -6202,7 +7224,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {</div><div class='ctx'> 		5 + /* HDP_INVL */</div><div class='ctx'> 		22 + /* SET_Q_PREEMPTION_MODE */</div><div class='ctx'> 		8 + 8 + /* FENCE x2 */</div><div class='del'>-		8, /* gfx_v11_0_emit_mem_sync */</div><div class='add'>+		8 + /* gfx_v11_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v11_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	4, /* gfx_v11_0_ring_emit_ib_gfx */</div><div class='ctx'> 	.emit_ib = gfx_v11_0_ring_emit_ib_gfx,</div><div class='ctx'> 	.emit_fence = gfx_v11_0_ring_emit_fence,</div><div class='hunk'>@@ -6212,7 +7235,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v11_0_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v11_0_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v11_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,</div><div class='ctx'> 	.emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,</div><div class='hunk'>@@ -6222,8 +7245,11 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_wreg = gfx_v11_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,</div><div class='del'>-	.soft_recovery = gfx_v11_0_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v11_0_emit_mem_sync,</div><div class='add'>+	.reset = gfx_v11_0_reset_kgq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v11_0_ring_begin_use,</div><div class='add'>+	.end_use = gfx_v11_0_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {</div><div class='hunk'>@@ -6244,7 +7270,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='ctx'> 		2 + /* gfx_v11_0_ring_emit_vm_flush */</div><div class='ctx'> 		8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */</div><div class='del'>-		8, /* gfx_v11_0_emit_mem_sync */</div><div class='add'>+		8 + /* gfx_v11_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v11_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v11_0_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_ib = gfx_v11_0_ring_emit_ib_compute,</div><div class='ctx'> 	.emit_fence = gfx_v11_0_ring_emit_fence,</div><div class='hunk'>@@ -6254,12 +7281,16 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v11_0_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v11_0_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v11_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_wreg = gfx_v11_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,</div><div class='ctx'> 	.emit_mem_sync = gfx_v11_0_emit_mem_sync,</div><div class='add'>+	.reset = gfx_v11_0_reset_kcq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v11_0_ring_begin_use,</div><div class='add'>+	.end_use = gfx_v11_0_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {</div><div class='hunk'>@@ -6277,7 +7308,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {</div><div class='ctx'> 		7 + /* gfx_v11_0_ring_emit_pipeline_sync */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='del'>-		2 + /* gfx_v11_0_ring_emit_vm_flush */</div><div class='ctx'> 		8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v11_0_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_ib = gfx_v11_0_ring_emit_ib_compute,</div><div class='hunk'>@@ -6290,6 +7320,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {</div><div class='ctx'> 	.emit_wreg = gfx_v11_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -6315,6 +7346,11 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {</div><div class='ctx'> 	.process = gfx_v11_0_priv_reg_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v11_0_bad_op_irq_funcs = {</div><div class='add'>+	.set = gfx_v11_0_set_bad_op_fault_state,</div><div class='add'>+	.process = gfx_v11_0_bad_op_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {</div><div class='ctx'> 	.set = gfx_v11_0_set_priv_inst_fault_state,</div><div class='ctx'> 	.process = gfx_v11_0_priv_inst_irq,</div><div class='hunk'>@@ -6332,6 +7368,9 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.funcs = &amp;gfx_v11_0_priv_reg_irq_funcs;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.bad_op_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.bad_op_irq.funcs = &amp;gfx_v11_0_bad_op_irq_funcs;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.funcs = &amp;gfx_v11_0_priv_inst_irq_funcs;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h<br/>index 10cfc29c27c9..157a5c812259 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h</a></div><div class='hunk'>@@ -26,4 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> extern const struct amdgpu_ip_block_version gfx_v11_0_ip_block;</div><div class='ctx'> </div><div class='add'>+int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='add'>+				      bool req);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c<br/>index 9e7ce1e6bc06..999bb3cc88b7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c</a></div><div class='hunk'>@@ -85,6 +85,7 @@ static int gfx_v11_0_3_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='ctx'> 	if (entry &amp;&amp; (entry-&gt;client_id == SOC21_IH_CLIENTID_GFX) &amp;&amp;</div><div class='ctx'> 	    (entry-&gt;src_id == GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT) &amp;&amp;</div><div class='ctx'> 	     !entry-&gt;vmid &amp;&amp; !entry-&gt;pasid) {</div><div class='add'>+		struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='ctx'> 		uint32_t rlc_status0 = 0;</div><div class='ctx'> </div><div class='ctx'> 		rlc_status0 = RREG32_SOC15(GC, 0, regRLC_RLCS_FED_STATUS_0);</div><div class='hunk'>@@ -96,7 +97,8 @@ static int gfx_v11_0_3_poison_consumption_handler(struct amdgpu_device *adev,</div><div class='ctx'> 			ras-&gt;gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		amdgpu_ras_reset_gpu(adev);</div><div class='add'>+		if (con &amp;&amp; !amdgpu_ras_is_rma(adev))</div><div class='add'>+			amdgpu_ras_reset_gpu(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm<br/>new file mode 100644<br/>index 000000000000..9b90b66368c7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm</a></div><div class='hunk'>@@ -0,0 +1,118 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+// This shader is to clean LDS, SGPRs and VGPRs. It is  first 64 Dwords or 256 bytes of 192 Dwords cleaner shader.</div><div class='add'>+//To turn this shader program on for complitaion change this to main and lower shader main to main_1</div><div class='add'>+</div><div class='add'>+// Navi3 : Clear SGPRs, VGPRs and LDS</div><div class='add'>+//   Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot</div><div class='add'>+//   Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD</div><div class='add'>+//   Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS)</div><div class='add'>+//      It takes 2 workgroups to use all of LDS: one on each CU of the WGP</div><div class='add'>+//   Each wave clears SGPRs 0 - 107</div><div class='add'>+//   Each wave clears VGPRs 0 - 63</div><div class='add'>+//   The first wave of the workgroup clears its 64KB of LDS</div><div class='add'>+//   The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup</div><div class='add'>+//       before any wave in the workgroup could end.  Without this, it is possible not all SGPRs get cleared.</div><div class='add'>+</div><div class='add'>+shader main</div><div class='add'>+  asic(GFX11)</div><div class='add'>+  type(CS)</div><div class='add'>+  wave_size(32)</div><div class='add'>+// Note: original source code from SQ team</div><div class='add'>+</div><div class='add'>+// Takes about 2500 clocks to run.</div><div class='add'>+//   (theorhetical fastest = 1024clks vgpr + 640lds = 1660 clks)</div><div class='add'>+//</div><div class='add'>+  S_BARRIER</div><div class='add'>+</div><div class='add'>+  //</div><div class='add'>+  // CLEAR VGPRs</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32     m0, 0x00000058  // Loop 96/8=12 times  (loop unrolled for performance)</div><div class='add'>+</div><div class='add'>+label_0005:</div><div class='add'>+  v_movreld_b32     v0, 0</div><div class='add'>+  v_movreld_b32     v1, 0</div><div class='add'>+  v_movreld_b32     v2, 0</div><div class='add'>+  v_movreld_b32     v3, 0</div><div class='add'>+  v_movreld_b32     v4, 0</div><div class='add'>+  v_movreld_b32     v5, 0</div><div class='add'>+  v_movreld_b32     v6, 0</div><div class='add'>+  v_movreld_b32     v7, 0</div><div class='add'>+  s_sub_u32     m0, m0, 8</div><div class='add'>+  s_cbranch_scc0  label_0005</div><div class='add'>+  //</div><div class='add'>+  //</div><div class='add'>+</div><div class='add'>+  s_mov_b32     s2, 0x80000000                      // Bit31 is first_wave</div><div class='add'>+  s_and_b32     s2, s2, s0                          // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set</div><div class='add'>+  s_cbranch_scc0  label_0023                        // Clean LDS if its first wave of ThreadGroup/WorkGroup</div><div class='add'>+  // CLEAR LDS</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32 exec_lo, 0xffffffff</div><div class='add'>+  s_mov_b32 exec_hi, 0xffffffff</div><div class='add'>+  v_mbcnt_lo_u32_b32  v1, exec_hi, 0          // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mbcnt_hi_u32_b32  v1, exec_lo, v1        // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mul_u32_u24  v1, 0x00000008, v1          // * 8, so each thread is a double-dword address (8byte)</div><div class='add'>+  s_mov_b32     s2, 0x00000003f                    // 64 loop iterations</div><div class='add'>+  s_mov_b32     m0, 0xffffffff</div><div class='add'>+  // Clear all of LDS space</div><div class='add'>+  // Each FirstWave of WorkGroup clears 64kbyte block</div><div class='add'>+</div><div class='add'>+label_001F:</div><div class='add'>+  ds_write2_b64  v1, v[2:3], v[2:3] offset1:32</div><div class='add'>+  ds_write2_b64  v1, v[4:5], v[4:5] offset0:64 offset1:96</div><div class='add'>+  v_add_co_u32     v1, vcc, 0x00000400, v1</div><div class='add'>+  s_sub_u32     s2, s2, 1</div><div class='add'>+  s_cbranch_scc0  label_001F</div><div class='add'>+  //</div><div class='add'>+  // CLEAR SGPRs</div><div class='add'>+  //</div><div class='add'>+label_0023:</div><div class='add'>+  s_mov_b32     m0, 0x00000068  // Loop 108/4=27 times  (loop unrolled for performance)</div><div class='add'>+label_sgpr_loop:</div><div class='add'>+  s_movreld_b32     s0, 0</div><div class='add'>+  s_movreld_b32     s1, 0</div><div class='add'>+  s_movreld_b32     s2, 0</div><div class='add'>+  s_movreld_b32     s3, 0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop</div><div class='add'>+</div><div class='add'>+  //clear vcc</div><div class='add'>+  s_mov_b64 vcc, 0          //clear vcc</div><div class='add'>+  s_mov_b32 flat_scratch_lo, 0   //clear  flat scratch lo SGPR</div><div class='add'>+  s_mov_b32 flat_scratch_hi, 0   //clear  flat scratch hi SGPR</div><div class='add'>+  s_mov_b64 ttmp0, 0        //Clear ttmp0 and ttmp1</div><div class='add'>+  s_mov_b64 ttmp2, 0        //Clear ttmp2 and ttmp3</div><div class='add'>+  s_mov_b64 ttmp4, 0        //Clear ttmp4 and ttmp5</div><div class='add'>+  s_mov_b64 ttmp6, 0        //Clear ttmp6 and ttmp7</div><div class='add'>+  s_mov_b64 ttmp8, 0        //Clear ttmp8 and ttmp9</div><div class='add'>+  s_mov_b64 ttmp10, 0       //Clear ttmp10 and ttmp11</div><div class='add'>+  s_mov_b64 ttmp12, 0       //Clear ttmp12 and ttmp13</div><div class='add'>+  s_mov_b64 ttmp14, 0       //Clear ttmp14 and ttmp15</div><div class='add'>+</div><div class='add'>+ s_endpgm</div><div class='add'>+</div><div class='add'>+end</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h<br/>new file mode 100644<br/>index 000000000000..3218cc04f543<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Define the cleaner shader gfx_11_0_3 */</div><div class='add'>+static const u32 gfx_11_0_3_cleaner_shader_hex[] = {</div><div class='add'>+	0xb0804006, 0xbe8200ff,</div><div class='add'>+	0x00000058, 0xbefd0080,</div><div class='add'>+	0x7e008480, 0x7e028480,</div><div class='add'>+	0x7e048480, 0x7e068480,</div><div class='add'>+	0x7e088480, 0x7e0a8480,</div><div class='add'>+	0x7e0c8480, 0x7e0e8480,</div><div class='add'>+	0xbefd0002, 0x80828802,</div><div class='add'>+	0xbfa1fff5, 0xbe8200ff,</div><div class='add'>+	0x80000000, 0x8b020002,</div><div class='add'>+	0xbfa10012, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xd71f0001,</div><div class='add'>+	0x0001007f, 0xd7200001,</div><div class='add'>+	0x0002027e, 0x16020288,</div><div class='add'>+	0xbe8200bf, 0xbefd00c1,</div><div class='add'>+	0xd9382000, 0x00020201,</div><div class='add'>+	0xd9386040, 0x00040401,</div><div class='add'>+	0xd7006a01, 0x000202ff,</div><div class='add'>+	0x00000400, 0x80828102,</div><div class='add'>+	0xbfa1fff7, 0xbefd00ff,</div><div class='add'>+	0x00000068, 0xbe804280,</div><div class='add'>+	0xbe814280, 0xbe824280,</div><div class='add'>+	0xbe834280, 0x80fd847d,</div><div class='add'>+	0xbfa1fffa, 0xbeea0180,</div><div class='add'>+	0xbeec0180, 0xbeee0180,</div><div class='add'>+	0xbef00180, 0xbef20180,</div><div class='add'>+	0xbef40180, 0xbef60180,</div><div class='add'>+	0xbef80180, 0xbefa0180,</div><div class='add'>+	0xbfb00000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c<br/>new file mode 100644<br/>index 000000000000..d01d2712cf57<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c</a></div><div class='hunk'>@@ -0,0 +1,5793 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_gfx.h"</div><div class='add'>+#include "amdgpu_psp.h"</div><div class='add'>+#include "amdgpu_smu.h"</div><div class='add'>+#include "imu_v12_0.h"</div><div class='add'>+#include "soc24.h"</div><div class='add'>+#include "nvd.h"</div><div class='add'>+</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "soc24_enum.h"</div><div class='add'>+#include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"</div><div class='add'>+</div><div class='add'>+#include "soc15.h"</div><div class='add'>+#include "clearstate_gfx12.h"</div><div class='add'>+#include "v12_structs.h"</div><div class='add'>+#include "gfx_v12_0.h"</div><div class='add'>+#include "nbif_v6_3_1.h"</div><div class='add'>+#include "mes_v12_0.h"</div><div class='add'>+#include "mes_userqueue.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='add'>+</div><div class='add'>+#define GFX12_NUM_GFX_RINGS	1</div><div class='add'>+#define GFX12_MEC_HPD_SIZE	2048</div><div class='add'>+</div><div class='add'>+#define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L</div><div class='add'>+</div><div class='add'>+#define regCP_GFX_MQD_CONTROL_DEFAULT                                             0x00000100</div><div class='add'>+#define regCP_GFX_HQD_VMID_DEFAULT                                                0x00000000</div><div class='add'>+#define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT                                      0x00000000</div><div class='add'>+#define regCP_GFX_HQD_QUANTUM_DEFAULT                                             0x00000a01</div><div class='add'>+#define regCP_GFX_HQD_CNTL_DEFAULT                                                0x00f00000</div><div class='add'>+#define regCP_RB_DOORBELL_CONTROL_DEFAULT                                         0x00000000</div><div class='add'>+#define regCP_GFX_HQD_RPTR_DEFAULT                                                0x00000000</div><div class='add'>+</div><div class='add'>+#define regCP_HQD_EOP_CONTROL_DEFAULT                                             0x00000006</div><div class='add'>+#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000</div><div class='add'>+#define regCP_MQD_CONTROL_DEFAULT                                                 0x00000100</div><div class='add'>+#define regCP_HQD_PQ_CONTROL_DEFAULT                                              0x00308509</div><div class='add'>+#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT                                     0x00000000</div><div class='add'>+#define regCP_HQD_PQ_RPTR_DEFAULT                                                 0x00000000</div><div class='add'>+#define regCP_HQD_PERSISTENT_STATE_DEFAULT                                        0x0be05501</div><div class='add'>+#define regCP_HQD_IB_CONTROL_DEFAULT                                              0x00300000</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),</div><div class='add'>+	/* SE status registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {</div><div class='add'>+	/* compute registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {</div><div class='add'>+	/* gfx queue registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),</div><div class='add'>+	/* cp header registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {</div><div class='add'>+	SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),</div><div class='add'>+	SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),</div><div class='add'>+	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct soc15_reg_golden golden_settings_gc_12_0[] = {</div><div class='add'>+	SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DEFAULT_SH_MEM_CONFIG \</div><div class='add'>+	((SH_MEM_ADDRESS_MODE_64 &lt;&lt; SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \</div><div class='add'>+	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt; SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \</div><div class='add'>+	 (3 &lt;&lt; SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_cu_info *cu_info);</div><div class='add'>+static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,</div><div class='add'>+				   u32 sh_num, u32 instance, int xcc_id);</div><div class='add'>+static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);</div><div class='add'>+static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+				     uint32_t val);</div><div class='add'>+static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);</div><div class='add'>+static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,</div><div class='add'>+					   uint16_t pasid, uint32_t flush_type,</div><div class='add'>+					   bool all_hub, uint8_t dst_sel);</div><div class='add'>+static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);</div><div class='add'>+static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);</div><div class='add'>+static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,</div><div class='add'>+				      bool enable);</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,</div><div class='add'>+					uint64_t queue_mask)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |</div><div class='add'>+			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,</div><div class='add'>+				     struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring-&gt;mqd_obj);</div><div class='add'>+	uint64_t wptr_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	uint32_t me = 0, eng_sel = 0;</div><div class='add'>+</div><div class='add'>+	switch (ring-&gt;funcs-&gt;type) {</div><div class='add'>+	case AMDGPU_RING_TYPE_COMPUTE:</div><div class='add'>+		me = 1;</div><div class='add'>+		eng_sel = 0;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_GFX:</div><div class='add'>+		me = 0;</div><div class='add'>+		eng_sel = 4;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_MES:</div><div class='add'>+		me = 2;</div><div class='add'>+		eng_sel = 5;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		WARN_ON(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));</div><div class='add'>+	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/</div><div class='add'>+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */</div><div class='add'>+			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */</div><div class='add'>+			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */</div><div class='add'>+			  PACKET3_MAP_QUEUES_QUEUE(ring-&gt;queue) |</div><div class='add'>+			  PACKET3_MAP_QUEUES_PIPE(ring-&gt;pipe) |</div><div class='add'>+			  PACKET3_MAP_QUEUES_ME((me)) |</div><div class='add'>+			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */</div><div class='add'>+			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */</div><div class='add'>+			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |</div><div class='add'>+			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring-&gt;doorbell_index));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,</div><div class='add'>+				       struct amdgpu_ring *ring,</div><div class='add'>+				       enum amdgpu_unmap_queues_action action,</div><div class='add'>+				       u64 gpu_addr, u64 seq)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	uint32_t eng_sel = ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX ? 4 : 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; !adev-&gt;gfx.kiq[0].ring.sched.ready) {</div><div class='add'>+		amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */</div><div class='add'>+			  PACKET3_UNMAP_QUEUES_ACTION(action) |</div><div class='add'>+			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |</div><div class='add'>+			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |</div><div class='add'>+			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));</div><div class='add'>+	amdgpu_ring_write(kiq_ring,</div><div class='add'>+		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring-&gt;doorbell_index));</div><div class='add'>+</div><div class='add'>+	if (action == PREEMPT_QUEUES_NO_UNMAP) {</div><div class='add'>+		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));</div><div class='add'>+		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));</div><div class='add'>+		amdgpu_ring_write(kiq_ring, seq);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_ring_write(kiq_ring, 0);</div><div class='add'>+		amdgpu_ring_write(kiq_ring, 0);</div><div class='add'>+		amdgpu_ring_write(kiq_ring, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring,</div><div class='add'>+				       struct amdgpu_ring *ring,</div><div class='add'>+				       u64 addr, u64 seq)</div><div class='add'>+{</div><div class='add'>+	uint32_t eng_sel = ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX ? 4 : 0;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));</div><div class='add'>+	amdgpu_ring_write(kiq_ring,</div><div class='add'>+			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |</div><div class='add'>+			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |</div><div class='add'>+			  PACKET3_QUERY_STATUS_COMMAND(2));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */</div><div class='add'>+			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring-&gt;doorbell_index) |</div><div class='add'>+			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,</div><div class='add'>+					  uint16_t pasid,</div><div class='add'>+					  uint32_t flush_type,</div><div class='add'>+					  bool all_hub)</div><div class='add'>+{</div><div class='add'>+	gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = {</div><div class='add'>+	.kiq_set_resources = gfx_v12_0_kiq_set_resources,</div><div class='add'>+	.kiq_map_queues = gfx_v12_0_kiq_map_queues,</div><div class='add'>+	.kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues,</div><div class='add'>+	.kiq_query_status = gfx_v12_0_kiq_query_status,</div><div class='add'>+	.kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs,</div><div class='add'>+	.set_resources_size = 8,</div><div class='add'>+	.map_queues_size = 7,</div><div class='add'>+	.unmap_queues_size = 6,</div><div class='add'>+	.query_status_size = 7,</div><div class='add'>+	.invalidate_tlbs_size = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gfx.kiq[0].pmf = &amp;gfx_v12_0_kiq_pm4_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,</div><div class='add'>+				   int mem_space, int opt, uint32_t addr0,</div><div class='add'>+				   uint32_t addr1, uint32_t ref,</div><div class='add'>+				   uint32_t mask, uint32_t inv)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));</div><div class='add'>+	amdgpu_ring_write(ring,</div><div class='add'>+			  /* memory (1) or register (0) */</div><div class='add'>+			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |</div><div class='add'>+			   WAIT_REG_MEM_OPERATION(opt) | /* wait */</div><div class='add'>+			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */</div><div class='add'>+			   WAIT_REG_MEM_ENGINE(eng_sel)));</div><div class='add'>+</div><div class='add'>+	if (mem_space)</div><div class='add'>+		BUG_ON(addr0 &amp; 0x3); /* Dword align */</div><div class='add'>+	amdgpu_ring_write(ring, addr0);</div><div class='add'>+	amdgpu_ring_write(ring, addr1);</div><div class='add'>+	amdgpu_ring_write(ring, ref);</div><div class='add'>+	amdgpu_ring_write(ring, mask);</div><div class='add'>+	amdgpu_ring_write(ring, inv); /* poll interval */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);</div><div class='add'>+	uint32_t tmp = 0;</div><div class='add'>+	unsigned i;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	WREG32(scratch, 0xCAFEDEAD);</div><div class='add'>+	r = amdgpu_ring_alloc(ring, 5);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"amdgpu: cp failed to lock ring %d (%d).\n",</div><div class='add'>+			ring-&gt;idx, r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_KIQ) {</div><div class='add'>+		gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));</div><div class='add'>+		amdgpu_ring_write(ring, scratch -</div><div class='add'>+				  PACKET3_SET_UCONFIG_REG_START);</div><div class='add'>+		amdgpu_ring_write(ring, 0xDEADBEEF);</div><div class='add'>+	}</div><div class='add'>+	amdgpu_ring_commit(ring);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32(scratch);</div><div class='add'>+		if (tmp == 0xDEADBEEF)</div><div class='add'>+			break;</div><div class='add'>+		if (amdgpu_emu_mode == 1)</div><div class='add'>+			msleep(1);</div><div class='add'>+		else</div><div class='add'>+			udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_ib ib;</div><div class='add'>+	struct dma_fence *f = NULL;</div><div class='add'>+	unsigned index;</div><div class='add'>+	uint64_t gpu_addr;</div><div class='add'>+	uint32_t *cpu_ptr;</div><div class='add'>+	long r;</div><div class='add'>+</div><div class='add'>+	/* MES KIQ fw hasn't indirect buffer support for now */</div><div class='add'>+	if (adev-&gt;enable_mes_kiq &amp;&amp;</div><div class='add'>+	    ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_KIQ)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	memset(&amp;ib, 0, sizeof(ib));</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='add'>+	cpu_ptr = &amp;adev-&gt;wb.wb[index];</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);</div><div class='add'>+	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;</div><div class='add'>+	ib.ptr[2] = lower_32_bits(gpu_addr);</div><div class='add'>+	ib.ptr[3] = upper_32_bits(gpu_addr);</div><div class='add'>+	ib.ptr[4] = 0xDEADBEEF;</div><div class='add'>+	ib.length_dw = 5;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_schedule(ring, 1, &amp;ib, NULL, &amp;f);</div><div class='add'>+	if (r)</div><div class='add'>+		goto err2;</div><div class='add'>+</div><div class='add'>+	r = dma_fence_wait_timeout(f, false, timeout);</div><div class='add'>+	if (r == 0) {</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+		goto err2;</div><div class='add'>+	} else if (r &lt; 0) {</div><div class='add'>+		goto err2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)</div><div class='add'>+		r = 0;</div><div class='add'>+	else</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+err2:</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='add'>+	dma_fence_put(f);</div><div class='add'>+err1:</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_free_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ucode_release(&amp;adev-&gt;gfx.pfp_fw);</div><div class='add'>+	amdgpu_ucode_release(&amp;adev-&gt;gfx.me_fw);</div><div class='add'>+	amdgpu_ucode_release(&amp;adev-&gt;gfx.rlc_fw);</div><div class='add'>+	amdgpu_ucode_release(&amp;adev-&gt;gfx.mec_fw);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;gfx.rlc.register_list_format);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)</div><div class='add'>+{</div><div class='add'>+	const struct psp_firmware_header_v1_0 *toc_hdr;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;psp.toc_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_toc.bin", ucode_prefix);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev-&gt;psp.toc_fw-&gt;data;</div><div class='add'>+	adev-&gt;psp.toc.fw_version = le32_to_cpu(toc_hdr-&gt;header.ucode_version);</div><div class='add'>+	adev-&gt;psp.toc.feature_version = le32_to_cpu(toc_hdr-&gt;sos.fw_version);</div><div class='add'>+	adev-&gt;psp.toc.size_bytes = le32_to_cpu(toc_hdr-&gt;header.ucode_size_bytes);</div><div class='add'>+	adev-&gt;psp.toc.start_addr = (uint8_t *)toc_hdr +</div><div class='add'>+			le32_to_cpu(toc_hdr-&gt;header.ucode_array_offset_bytes);</div><div class='add'>+	return 0;</div><div class='add'>+out:</div><div class='add'>+	amdgpu_ucode_release(&amp;adev-&gt;psp.toc_fw);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	char ucode_prefix[30];</div><div class='add'>+	int err;</div><div class='add'>+	const struct rlc_firmware_header_v2_0 *rlc_hdr;</div><div class='add'>+	uint16_t version_major;</div><div class='add'>+	uint16_t version_minor;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG("\n");</div><div class='add'>+</div><div class='add'>+	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='add'>+</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_pfp.bin", ucode_prefix);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out;</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);</div><div class='add'>+</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_me.bin", ucode_prefix);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out;</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		if (amdgpu_is_kicker_fw(adev))</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_rlc_kicker.bin", ucode_prefix);</div><div class='add'>+		else</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_rlc.bin", ucode_prefix);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out;</div><div class='add'>+		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+		version_major = le16_to_cpu(rlc_hdr-&gt;header.header_version_major);</div><div class='add'>+		version_minor = le16_to_cpu(rlc_hdr-&gt;header.header_version_minor);</div><div class='add'>+		err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mec.bin", ucode_prefix);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out;</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);</div><div class='add'>+	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)</div><div class='add'>+		err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix);</div><div class='add'>+</div><div class='add'>+	/* only one MEC for gfx 12 */</div><div class='add'>+	adev-&gt;gfx.mec2_fw = NULL;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.imu.funcs) {</div><div class='add'>+		if (adev-&gt;gfx.imu.funcs-&gt;init_microcode) {</div><div class='add'>+			err = adev-&gt;gfx.imu.funcs-&gt;init_microcode(adev);</div><div class='add'>+			if (err)</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to load imu firmware!\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	if (err) {</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;gfx.pfp_fw);</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;gfx.me_fw);</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;gfx.rlc_fw);</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;gfx.mec_fw);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 count = 0;</div><div class='add'>+	const struct cs_section_def *sect = NULL;</div><div class='add'>+	const struct cs_extent_def *ext = NULL;</div><div class='add'>+</div><div class='add'>+	count += 1;</div><div class='add'>+</div><div class='add'>+	for (sect = gfx12_cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='add'>+		if (sect-&gt;id == SECT_CONTEXT) {</div><div class='add'>+			for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext)</div><div class='add'>+				count += 2 + ext-&gt;reg_count;</div><div class='add'>+		} else</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='add'>+{</div><div class='add'>+	u32 count = 0, clustercount = 0, i;</div><div class='add'>+	const struct cs_section_def *sect = NULL;</div><div class='add'>+	const struct cs_extent_def *ext = NULL;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='add'>+		return;</div><div class='add'>+	if (buffer == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	count += 1;</div><div class='add'>+</div><div class='add'>+	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='add'>+		if (sect-&gt;id == SECT_CONTEXT) {</div><div class='add'>+			for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='add'>+				clustercount++;</div><div class='add'>+				buffer[count++] = ext-&gt;reg_count;</div><div class='add'>+				buffer[count++] = ext-&gt;reg_index;</div><div class='add'>+</div><div class='add'>+				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='add'>+					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='add'>+			}</div><div class='add'>+		} else</div><div class='add'>+			return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	buffer[0] = clustercount;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* clear state block */</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.rlc.clear_state_obj,</div><div class='add'>+			&amp;adev-&gt;gfx.rlc.clear_state_gpu_addr,</div><div class='add'>+			(void **)&amp;adev-&gt;gfx.rlc.cs_ptr);</div><div class='add'>+</div><div class='add'>+	/* jump table block */</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.rlc.cp_table_obj,</div><div class='add'>+			&amp;adev-&gt;gfx.rlc.cp_table_gpu_addr,</div><div class='add'>+			(void **)&amp;adev-&gt;gfx.rlc.cp_table_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;</div><div class='add'>+</div><div class='add'>+	reg_access_ctrl = &amp;adev-&gt;gfx.rlc.reg_access_ctrl[0];</div><div class='add'>+	reg_access_ctrl-&gt;scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);</div><div class='add'>+	reg_access_ctrl-&gt;scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);</div><div class='add'>+	reg_access_ctrl-&gt;scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);</div><div class='add'>+	reg_access_ctrl-&gt;scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);</div><div class='add'>+	reg_access_ctrl-&gt;grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);</div><div class='add'>+	reg_access_ctrl-&gt;grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);</div><div class='add'>+	reg_access_ctrl-&gt;spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);</div><div class='add'>+	adev-&gt;gfx.rlc.rlcg_reg_access_supported = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct cs_section_def *cs_data;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.rlc.cs_data = gfx12_cs_data;</div><div class='add'>+</div><div class='add'>+	cs_data = adev-&gt;gfx.rlc.cs_data;</div><div class='add'>+</div><div class='add'>+	if (cs_data) {</div><div class='add'>+		/* init clear state block */</div><div class='add'>+		r = amdgpu_gfx_rlc_init_csb(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* init spm vmid with 0xf */</div><div class='add'>+	if (adev-&gt;gfx.rlc.funcs-&gt;update_spm_vmid)</div><div class='add'>+		adev-&gt;gfx.rlc.funcs-&gt;update_spm_vmid(adev, NULL, 0xf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_mec_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.mec.hpd_eop_obj, NULL, NULL);</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.mec.mec_fw_obj, NULL, NULL);</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.mec.mec_fw_data_obj, NULL, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_me_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	bitmap_zero(adev-&gt;gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_graphics_queue_acquire(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_mec_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	u32 *hpd;</div><div class='add'>+	size_t mec_hpd_size;</div><div class='add'>+</div><div class='add'>+	bitmap_zero(adev-&gt;gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);</div><div class='add'>+</div><div class='add'>+	/* take ownership of the relevant compute queues */</div><div class='add'>+	amdgpu_gfx_compute_queue_acquire(adev);</div><div class='add'>+	mec_hpd_size = adev-&gt;gfx.num_compute_rings * GFX12_MEC_HPD_SIZE;</div><div class='add'>+</div><div class='add'>+	if (mec_hpd_size) {</div><div class='add'>+		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,</div><div class='add'>+					      AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+					      &amp;adev-&gt;gfx.mec.hpd_eop_obj,</div><div class='add'>+					      &amp;adev-&gt;gfx.mec.hpd_eop_gpu_addr,</div><div class='add'>+					      (void **)&amp;hpd);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "(%d) create HDP EOP bo failed\n", r);</div><div class='add'>+			gfx_v12_0_mec_fini(adev);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		memset(hpd, 0, mec_hpd_size);</div><div class='add'>+</div><div class='add'>+		amdgpu_bo_kunmap(adev-&gt;gfx.mec.hpd_eop_obj);</div><div class='add'>+		amdgpu_bo_unreserve(adev-&gt;gfx.mec.hpd_eop_obj);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)</div><div class='add'>+{</div><div class='add'>+	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,</div><div class='add'>+		(wave &lt;&lt; SQ_IND_INDEX__WAVE_ID__SHIFT) |</div><div class='add'>+		(address &lt;&lt; SQ_IND_INDEX__INDEX__SHIFT));</div><div class='add'>+	return RREG32_SOC15(GC, 0, regSQ_IND_DATA);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,</div><div class='add'>+			   uint32_t thread, uint32_t regno,</div><div class='add'>+			   uint32_t num, uint32_t *out)</div><div class='add'>+{</div><div class='add'>+	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,</div><div class='add'>+		(wave &lt;&lt; SQ_IND_INDEX__WAVE_ID__SHIFT) |</div><div class='add'>+		(regno &lt;&lt; SQ_IND_INDEX__INDEX__SHIFT) |</div><div class='add'>+		(thread &lt;&lt; SQ_IND_INDEX__WORKITEM_ID__SHIFT) |</div><div class='add'>+		(SQ_IND_INDEX__AUTO_INCR_MASK));</div><div class='add'>+	while (num--)</div><div class='add'>+		*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,</div><div class='add'>+				     uint32_t xcc_id,</div><div class='add'>+				     uint32_t simd, uint32_t wave,</div><div class='add'>+				     uint32_t *dst, int *no_fields)</div><div class='add'>+{</div><div class='add'>+	/* in gfx12 the SIMD_ID is specified as part of the INSTANCE</div><div class='add'>+	 * field when performing a select_se_sh so it should be</div><div class='add'>+	 * zero here */</div><div class='add'>+	WARN_ON(simd != 0);</div><div class='add'>+</div><div class='add'>+	/* type 4 wave data */</div><div class='add'>+	dst[(*no_fields)++] = 4;</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);</div><div class='add'>+	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,</div><div class='add'>+				      uint32_t xcc_id, uint32_t simd,</div><div class='add'>+				      uint32_t wave, uint32_t start,</div><div class='add'>+				      uint32_t size, uint32_t *dst)</div><div class='add'>+{</div><div class='add'>+	WARN_ON(simd != 0);</div><div class='add'>+</div><div class='add'>+	wave_read_regs(</div><div class='add'>+		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,</div><div class='add'>+		dst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev,</div><div class='add'>+				      uint32_t xcc_id, uint32_t simd,</div><div class='add'>+				      uint32_t wave, uint32_t thread,</div><div class='add'>+				      uint32_t start, uint32_t size,</div><div class='add'>+				      uint32_t *dst)</div><div class='add'>+{</div><div class='add'>+	wave_read_regs(</div><div class='add'>+		adev, wave, thread,</div><div class='add'>+		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev,</div><div class='add'>+				       u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)</div><div class='add'>+{</div><div class='add'>+	soc24_grbm_select(adev, me, pipe, q, vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* all sizes are in bytes */</div><div class='add'>+#define MQD_SHADOW_BASE_SIZE      73728</div><div class='add'>+#define MQD_SHADOW_BASE_ALIGNMENT 256</div><div class='add'>+#define MQD_FWWORKAREA_SIZE       484</div><div class='add'>+#define MQD_FWWORKAREA_ALIGNMENT  256</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,</div><div class='add'>+						  struct amdgpu_gfx_shadow_info *shadow_info)</div><div class='add'>+{</div><div class='add'>+	shadow_info-&gt;shadow_size = MQD_SHADOW_BASE_SIZE;</div><div class='add'>+	shadow_info-&gt;shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;</div><div class='add'>+	shadow_info-&gt;csa_size = MQD_FWWORKAREA_SIZE;</div><div class='add'>+	shadow_info-&gt;csa_alignment = MQD_FWWORKAREA_ALIGNMENT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev,</div><div class='add'>+					 struct amdgpu_gfx_shadow_info *shadow_info,</div><div class='add'>+					 bool skip_check)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;gfx.cp_gfx_shadow || skip_check) {</div><div class='add'>+		gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {</div><div class='add'>+	.get_gpu_clock_counter = &amp;gfx_v12_0_get_gpu_clock_counter,</div><div class='add'>+	.select_se_sh = &amp;gfx_v12_0_select_se_sh,</div><div class='add'>+	.read_wave_data = &amp;gfx_v12_0_read_wave_data,</div><div class='add'>+	.read_wave_sgprs = &amp;gfx_v12_0_read_wave_sgprs,</div><div class='add'>+	.read_wave_vgprs = &amp;gfx_v12_0_read_wave_vgprs,</div><div class='add'>+	.select_me_pipe_q = &amp;gfx_v12_0_select_me_pipe_q,</div><div class='add'>+	.update_perfmon_mgcg = &amp;gfx_v12_0_update_perf_clk,</div><div class='add'>+	.get_gfx_shadow_info = &amp;gfx_v12_0_get_gfx_shadow_info,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		adev-&gt;gfx.config.max_hw_contexts = 8;</div><div class='add'>+		adev-&gt;gfx.config.sc_prim_fifo_size_frontend = 0x20;</div><div class='add'>+		adev-&gt;gfx.config.sc_prim_fifo_size_backend = 0x100;</div><div class='add'>+		adev-&gt;gfx.config.sc_hiz_tile_fifo_size = 0;</div><div class='add'>+		adev-&gt;gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BUG();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='add'>+				   int me, int pipe, int queue)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	unsigned int irq_type;</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;gfx.gfx_ring[ring_id];</div><div class='add'>+</div><div class='add'>+	ring-&gt;me = me;</div><div class='add'>+	ring-&gt;pipe = pipe;</div><div class='add'>+	ring-&gt;queue = queue;</div><div class='add'>+</div><div class='add'>+	ring-&gt;ring_obj = NULL;</div><div class='add'>+	ring-&gt;use_doorbell = true;</div><div class='add'>+</div><div class='add'>+	if (!ring_id)</div><div class='add'>+		ring-&gt;doorbell_index = adev-&gt;doorbell_index.gfx_ring0 &lt;&lt; 1;</div><div class='add'>+	else</div><div class='add'>+		ring-&gt;doorbell_index = adev-&gt;doorbell_index.gfx_ring1 &lt;&lt; 1;</div><div class='add'>+	ring-&gt;vm_hub = AMDGPU_GFXHUB(0);</div><div class='add'>+	sprintf(ring-&gt;name, "gfx_%d.%d.%d", ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='add'>+</div><div class='add'>+	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring-&gt;pipe;</div><div class='add'>+	r = amdgpu_ring_init(adev, ring, 1024, &amp;adev-&gt;gfx.eop_irq, irq_type,</div><div class='add'>+			     AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='add'>+				       int mec, int pipe, int queue)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	unsigned irq_type;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	unsigned int hw_prio;</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;gfx.compute_ring[ring_id];</div><div class='add'>+</div><div class='add'>+	/* mec0 is me1 */</div><div class='add'>+	ring-&gt;me = mec + 1;</div><div class='add'>+	ring-&gt;pipe = pipe;</div><div class='add'>+	ring-&gt;queue = queue;</div><div class='add'>+</div><div class='add'>+	ring-&gt;ring_obj = NULL;</div><div class='add'>+	ring-&gt;use_doorbell = true;</div><div class='add'>+	ring-&gt;doorbell_index = (adev-&gt;doorbell_index.mec_ring0 + ring_id) &lt;&lt; 1;</div><div class='add'>+	ring-&gt;eop_gpu_addr = adev-&gt;gfx.mec.hpd_eop_gpu_addr</div><div class='add'>+				+ (ring_id * GFX12_MEC_HPD_SIZE);</div><div class='add'>+	ring-&gt;vm_hub = AMDGPU_GFXHUB(0);</div><div class='add'>+	sprintf(ring-&gt;name, "comp_%d.%d.%d", ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='add'>+</div><div class='add'>+	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP</div><div class='add'>+		+ ((ring-&gt;me - 1) * adev-&gt;gfx.mec.num_pipe_per_mec)</div><div class='add'>+		+ ring-&gt;pipe;</div><div class='add'>+	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?</div><div class='add'>+			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;</div><div class='add'>+	/* type-2 packets are deprecated on MEC, use type-3 instead */</div><div class='add'>+	r = amdgpu_ring_init(adev, ring, 1024, &amp;adev-&gt;gfx.eop_irq, irq_type,</div><div class='add'>+			     hw_prio, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct {</div><div class='add'>+	SOC24_FIRMWARE_ID	id;</div><div class='add'>+	unsigned int		offset;</div><div class='add'>+	unsigned int		size;</div><div class='add'>+	unsigned int		size_x16;</div><div class='add'>+} rlc_autoload_info[SOC24_FIRMWARE_ID_MAX];</div><div class='add'>+</div><div class='add'>+#define RLC_TOC_OFFSET_DWUNIT   8</div><div class='add'>+#define RLC_SIZE_MULTIPLE       1024</div><div class='add'>+#define RLC_TOC_UMF_SIZE_inM	23ULL</div><div class='add'>+#define RLC_TOC_FORMAT_API	165ULL</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)</div><div class='add'>+{</div><div class='add'>+	RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc;</div><div class='add'>+</div><div class='add'>+	while (ucode &amp;&amp; (ucode-&gt;id &gt; SOC24_FIRMWARE_ID_INVALID)) {</div><div class='add'>+		rlc_autoload_info[ucode-&gt;id].id = ucode-&gt;id;</div><div class='add'>+		rlc_autoload_info[ucode-&gt;id].offset =</div><div class='add'>+			ucode-&gt;offset * RLC_TOC_OFFSET_DWUNIT * 4;</div><div class='add'>+		rlc_autoload_info[ucode-&gt;id].size =</div><div class='add'>+			ucode-&gt;size_x16 ? ucode-&gt;size * RLC_SIZE_MULTIPLE * 4 :</div><div class='add'>+					  ucode-&gt;size * 4;</div><div class='add'>+		ucode++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t total_size = 0;</div><div class='add'>+	SOC24_FIRMWARE_ID id;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_parse_rlc_toc(adev, adev-&gt;psp.toc.start_addr);</div><div class='add'>+</div><div class='add'>+	for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id &lt; SOC24_FIRMWARE_ID_MAX; id++)</div><div class='add'>+		total_size += rlc_autoload_info[id].size;</div><div class='add'>+</div><div class='add'>+	/* In case the offset in rlc toc ucode is aligned */</div><div class='add'>+	if (total_size &lt; rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset)</div><div class='add'>+		total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset +</div><div class='add'>+			rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size;</div><div class='add'>+	if (total_size &lt; (RLC_TOC_UMF_SIZE_inM &lt;&lt; 20))</div><div class='add'>+		total_size = RLC_TOC_UMF_SIZE_inM &lt;&lt; 20;</div><div class='add'>+</div><div class='add'>+	return total_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	uint32_t total_size;</div><div class='add'>+</div><div class='add'>+	total_size = gfx_v12_0_calc_toc_total_size(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,</div><div class='add'>+				      AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.rlc.rlc_autoload_bo,</div><div class='add'>+				      &amp;adev-&gt;gfx.rlc.rlc_autoload_gpu_addr,</div><div class='add'>+				      (void **)&amp;adev-&gt;gfx.rlc.rlc_autoload_ptr);</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create fw autoload bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,</div><div class='add'>+						       SOC24_FIRMWARE_ID id,</div><div class='add'>+						       const void *fw_data,</div><div class='add'>+						       uint32_t fw_size)</div><div class='add'>+{</div><div class='add'>+	uint32_t toc_offset;</div><div class='add'>+	uint32_t toc_fw_size;</div><div class='add'>+	char *ptr = adev-&gt;gfx.rlc.rlc_autoload_ptr;</div><div class='add'>+</div><div class='add'>+	if (id &lt;= SOC24_FIRMWARE_ID_INVALID || id &gt;= SOC24_FIRMWARE_ID_MAX)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	toc_offset = rlc_autoload_info[id].offset;</div><div class='add'>+	toc_fw_size = rlc_autoload_info[id].size;</div><div class='add'>+</div><div class='add'>+	if (fw_size == 0)</div><div class='add'>+		fw_size = toc_fw_size;</div><div class='add'>+</div><div class='add'>+	if (fw_size &gt; toc_fw_size)</div><div class='add'>+		fw_size = toc_fw_size;</div><div class='add'>+</div><div class='add'>+	memcpy(ptr + toc_offset, fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+	if (fw_size &lt; toc_fw_size)</div><div class='add'>+		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	void *data;</div><div class='add'>+	uint32_t size;</div><div class='add'>+	uint32_t *toc_ptr;</div><div class='add'>+</div><div class='add'>+	data = adev-&gt;psp.toc.start_addr;</div><div class='add'>+	size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size;</div><div class='add'>+</div><div class='add'>+	toc_ptr = (uint32_t *)data + size / 4 - 2;</div><div class='add'>+	*toc_ptr = (RLC_TOC_FORMAT_API &lt;&lt; 24) | 0x1;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC,</div><div class='add'>+						   data, size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	uint32_t fw_size;</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *cpv2_hdr;</div><div class='add'>+	const struct rlc_firmware_header_v2_0 *rlc_hdr;</div><div class='add'>+	const struct rlc_firmware_header_v2_1 *rlcv21_hdr;</div><div class='add'>+	const struct rlc_firmware_header_v2_2 *rlcv22_hdr;</div><div class='add'>+	uint16_t version_major, version_minor;</div><div class='add'>+</div><div class='add'>+	/* pfp ucode */</div><div class='add'>+	cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.pfp_fw-&gt;data;</div><div class='add'>+	/* instruction */</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.pfp_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(cpv2_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(cpv2_hdr-&gt;ucode_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	/* data */</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.pfp_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(cpv2_hdr-&gt;data_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(cpv2_hdr-&gt;data_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	/* me ucode */</div><div class='add'>+	cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.me_fw-&gt;data;</div><div class='add'>+	/* instruction */</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.me_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(cpv2_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(cpv2_hdr-&gt;ucode_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	/* data */</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.me_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(cpv2_hdr-&gt;data_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(cpv2_hdr-&gt;data_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	/* mec ucode */</div><div class='add'>+	cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.mec_fw-&gt;data;</div><div class='add'>+	/* instruction */</div><div class='add'>+	fw_data = (const __le32 *) (adev-&gt;gfx.mec_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(cpv2_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(cpv2_hdr-&gt;ucode_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	/* data */</div><div class='add'>+	fw_data = (const __le32 *) (adev-&gt;gfx.mec_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(cpv2_hdr-&gt;data_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(cpv2_hdr-&gt;data_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+	/* rlc ucode */</div><div class='add'>+	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+			le32_to_cpu(rlc_hdr-&gt;header.ucode_array_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(rlc_hdr-&gt;header.ucode_size_bytes);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+	version_major = le16_to_cpu(rlc_hdr-&gt;header.header_version_major);</div><div class='add'>+	version_minor = le16_to_cpu(rlc_hdr-&gt;header.header_version_minor);</div><div class='add'>+	if (version_major == 2) {</div><div class='add'>+		if (version_minor &gt;= 1) {</div><div class='add'>+			rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+			fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+					le32_to_cpu(rlcv21_hdr-&gt;save_restore_list_gpm_offset_bytes));</div><div class='add'>+			fw_size = le32_to_cpu(rlcv21_hdr-&gt;save_restore_list_gpm_size_bytes);</div><div class='add'>+			gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+			fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+					le32_to_cpu(rlcv21_hdr-&gt;save_restore_list_srm_offset_bytes));</div><div class='add'>+			fw_size = le32_to_cpu(rlcv21_hdr-&gt;save_restore_list_srm_size_bytes);</div><div class='add'>+			gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+		}</div><div class='add'>+		if (version_minor &gt;= 2) {</div><div class='add'>+			rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+			fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+					le32_to_cpu(rlcv22_hdr-&gt;rlc_iram_ucode_offset_bytes));</div><div class='add'>+			fw_size = le32_to_cpu(rlcv22_hdr-&gt;rlc_iram_ucode_size_bytes);</div><div class='add'>+			gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+			fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+					le32_to_cpu(rlcv22_hdr-&gt;rlc_dram_ucode_offset_bytes));</div><div class='add'>+			fw_size = le32_to_cpu(rlcv22_hdr-&gt;rlc_dram_ucode_size_bytes);</div><div class='add'>+			gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	uint32_t fw_size;</div><div class='add'>+	const struct sdma_firmware_header_v3_0 *sdma_hdr;</div><div class='add'>+</div><div class='add'>+	sdma_hdr = (const struct sdma_firmware_header_v3_0 *)</div><div class='add'>+		adev-&gt;sdma.instance[0].fw-&gt;data;</div><div class='add'>+	fw_data = (const __le32 *) (adev-&gt;sdma.instance[0].fw-&gt;data +</div><div class='add'>+			le32_to_cpu(sdma_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(sdma_hdr-&gt;ucode_size_bytes);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0,</div><div class='add'>+						   fw_data, fw_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	unsigned fw_size;</div><div class='add'>+	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='add'>+	int pipe, ucode_id, data_id;</div><div class='add'>+</div><div class='add'>+	for (pipe = 0; pipe &lt; 2; pipe++) {</div><div class='add'>+		if (pipe == 0) {</div><div class='add'>+			ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0;</div><div class='add'>+			data_id  = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK;</div><div class='add'>+		} else {</div><div class='add'>+			ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1;</div><div class='add'>+			data_id  = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mes_hdr = (const struct mes_firmware_header_v1_0 *)</div><div class='add'>+			adev-&gt;mes.fw[pipe]-&gt;data;</div><div class='add'>+</div><div class='add'>+		fw_data = (const __le32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='add'>+				le32_to_cpu(mes_hdr-&gt;mes_ucode_offset_bytes));</div><div class='add'>+		fw_size = le32_to_cpu(mes_hdr-&gt;mes_ucode_size_bytes);</div><div class='add'>+</div><div class='add'>+		gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+		fw_data = (const __le32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='add'>+				le32_to_cpu(mes_hdr-&gt;mes_ucode_data_offset_bytes));</div><div class='add'>+		fw_size = le32_to_cpu(mes_hdr-&gt;mes_ucode_data_size_bytes);</div><div class='add'>+</div><div class='add'>+		gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t rlc_g_offset, rlc_g_size;</div><div class='add'>+	uint64_t gpu_addr;</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	/* RLC autoload sequence 2: copy ucode */</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev);</div><div class='add'>+	gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev);</div><div class='add'>+</div><div class='add'>+	rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset;</div><div class='add'>+	rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;</div><div class='add'>+	gpu_addr = adev-&gt;gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev-&gt;gmc.vram_start;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.imu.funcs &amp;&amp; (amdgpu_dpm &gt; 0)) {</div><div class='add'>+		/* RLC autoload sequence 3: load IMU fw */</div><div class='add'>+		if (adev-&gt;gfx.imu.funcs-&gt;load_microcode)</div><div class='add'>+			adev-&gt;gfx.imu.funcs-&gt;load_microcode(adev);</div><div class='add'>+		/* RLC autoload sequence 4 init IMU fw */</div><div class='add'>+		if (adev-&gt;gfx.imu.funcs-&gt;setup_imu)</div><div class='add'>+			adev-&gt;gfx.imu.funcs-&gt;setup_imu(adev);</div><div class='add'>+		if (adev-&gt;gfx.imu.funcs-&gt;start_imu)</div><div class='add'>+			adev-&gt;gfx.imu.funcs-&gt;start_imu(adev);</div><div class='add'>+</div><div class='add'>+		/* RLC autoload sequence 5 disable gpa mode */</div><div class='add'>+		gfx_v12_0_disable_gpa_mode(adev);</div><div class='add'>+	} else {</div><div class='add'>+		/* unhalt rlc to start autoload without imu */</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);</div><div class='add'>+		data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='add'>+	uint32_t inst;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for compute queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_12);</div><div class='add'>+	inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for gfx queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);</div><div class='add'>+	inst = adev-&gt;gfx.me.num_me * adev-&gt;gfx.me.num_pipe_per_me *</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_gfx_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_gfx_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int i, j, k, r, ring_id = 0;</div><div class='add'>+	unsigned num_compute_rings;</div><div class='add'>+	int xcc_id = 0;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */</div><div class='add'>+</div><div class='add'>+	INIT_DELAYED_WORK(&amp;adev-&gt;gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		adev-&gt;gfx.me.num_me = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_pipe_per_me = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe = 8;</div><div class='add'>+		adev-&gt;gfx.mec.num_mec = 1;</div><div class='add'>+		adev-&gt;gfx.mec.num_pipe_per_mec = 2;</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe = 4;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.me.num_me = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_pipe_per_me = 1;</div><div class='add'>+		adev-&gt;gfx.me.num_queue_per_pipe = 1;</div><div class='add'>+		adev-&gt;gfx.mec.num_mec = 1;</div><div class='add'>+		adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe = 8;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		if (!adev-&gt;gfx.disable_uq &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.me_fw_version  &gt;= 2780 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 2840 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 3050 &amp;&amp;</div><div class='add'>+		    adev-&gt;mes.fw_version[0] &gt;= 123) {</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_GFX] = &amp;userq_mes_funcs;</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_COMPUTE] = &amp;userq_mes_funcs;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version  &gt;= 2480 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 2530 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 2680 &amp;&amp;</div><div class='add'>+		    adev-&gt;mes.fw_version[0] &gt;= 100)</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_compute_rings) {</div><div class='add'>+		/* recalculate compute rings to use based on hardware configuration */</div><div class='add'>+		num_compute_rings = (adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+				     adev-&gt;gfx.mec.num_queue_per_pipe) / 2;</div><div class='add'>+		adev-&gt;gfx.num_compute_rings = min(adev-&gt;gfx.num_compute_rings,</div><div class='add'>+						  num_compute_rings);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* EOP Event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_12_0_0__SRCID__CP_EOP_INTERRUPT,</div><div class='add'>+			      &amp;adev-&gt;gfx.eop_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* Bad opcode Event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_12_0_0__SRCID__CP_BAD_OPCODE_ERROR,</div><div class='add'>+			      &amp;adev-&gt;gfx.bad_op_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* Privileged reg */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_12_0_0__SRCID__CP_PRIV_REG_FAULT,</div><div class='add'>+			      &amp;adev-&gt;gfx.priv_reg_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* Privileged inst */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_12_0_0__SRCID__CP_PRIV_INSTR_FAULT,</div><div class='add'>+			      &amp;adev-&gt;gfx.priv_inst_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_me_init(adev);</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_rlc_init(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to init rlc BOs!\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_mec_init(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to init MEC BOs!\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings) {</div><div class='add'>+		/* set up the gfx ring */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; num_queue_per_pipe; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.me.num_pipe_per_me; k++) {</div><div class='add'>+					if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))</div><div class='add'>+						continue;</div><div class='add'>+</div><div class='add'>+					r = gfx_v12_0_gfx_ring_init(adev, ring_id,</div><div class='add'>+								    i, k, j);</div><div class='add'>+					if (r)</div><div class='add'>+						return r;</div><div class='add'>+					ring_id++;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.num_compute_rings) {</div><div class='add'>+		ring_id = 0;</div><div class='add'>+		/* set up the compute queues - allocate horizontally across pipes */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; ++i) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_queue_per_pipe; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.mec.num_pipe_per_mec; k++) {</div><div class='add'>+					if (!amdgpu_gfx_is_mec_queue_enabled(adev,</div><div class='add'>+									     0, i, k, j))</div><div class='add'>+						continue;</div><div class='add'>+</div><div class='add'>+					r = gfx_v12_0_compute_ring_init(adev, ring_id,</div><div class='add'>+									i, k, j);</div><div class='add'>+					if (r)</div><div class='add'>+						return r;</div><div class='add'>+</div><div class='add'>+					ring_id++;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		if ((adev-&gt;gfx.me_fw_version &gt;= 2660) &amp;&amp;</div><div class='add'>+		    (adev-&gt;gfx.mec_fw_version &gt;= 2920) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+			adev-&gt;gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_mes_kiq) {</div><div class='add'>+		r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to init KIQ BOs!\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* allocate visible FB for rlc auto-loading fw */</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {</div><div class='add'>+		r = gfx_v12_0_rlc_autoload_buffer_init(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_gpu_early_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_alloc_ip_dump(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.pfp.pfp_fw_obj,</div><div class='add'>+			      &amp;adev-&gt;gfx.pfp.pfp_fw_gpu_addr,</div><div class='add'>+			      (void **)&amp;adev-&gt;gfx.pfp.pfp_fw_ptr);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.pfp.pfp_fw_data_obj,</div><div class='add'>+			      &amp;adev-&gt;gfx.pfp.pfp_fw_data_gpu_addr,</div><div class='add'>+			      (void **)&amp;adev-&gt;gfx.pfp.pfp_fw_data_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_me_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.me.me_fw_obj,</div><div class='add'>+			      &amp;adev-&gt;gfx.me.me_fw_gpu_addr,</div><div class='add'>+			      (void **)&amp;adev-&gt;gfx.me.me_fw_ptr);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.me.me_fw_data_obj,</div><div class='add'>+			       &amp;adev-&gt;gfx.me.me_fw_data_gpu_addr,</div><div class='add'>+			       (void **)&amp;adev-&gt;gfx.me.me_fw_data_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.rlc.rlc_autoload_bo,</div><div class='add'>+			&amp;adev-&gt;gfx.rlc.rlc_autoload_gpu_addr,</div><div class='add'>+			(void **)&amp;adev-&gt;gfx.rlc.rlc_autoload_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='add'>+		amdgpu_ring_fini(&amp;adev-&gt;gfx.gfx_ring[i]);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++)</div><div class='add'>+		amdgpu_ring_fini(&amp;adev-&gt;gfx.compute_ring[i]);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_mqd_sw_fini(adev, 0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_mes_kiq) {</div><div class='add'>+		amdgpu_gfx_kiq_free_ring(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='add'>+		amdgpu_gfx_kiq_fini(adev, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_pfp_fini(adev);</div><div class='add'>+	gfx_v12_0_me_fini(adev);</div><div class='add'>+	gfx_v12_0_rlc_fini(adev);</div><div class='add'>+	gfx_v12_0_mec_fini(adev);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)</div><div class='add'>+		gfx_v12_0_rlc_autoload_buffer_fini(adev);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_free_microcode(adev);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_sysfs_fini(adev);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_core);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_compute_queues);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_gfx_queues);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,</div><div class='add'>+				   u32 sh_num, u32 instance, int xcc_id)</div><div class='add'>+{</div><div class='add'>+	u32 data;</div><div class='add'>+</div><div class='add'>+	if (instance == 0xffffffff)</div><div class='add'>+		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,</div><div class='add'>+				     INSTANCE_BROADCAST_WRITES, 1);</div><div class='add'>+	else</div><div class='add'>+		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,</div><div class='add'>+				     instance);</div><div class='add'>+</div><div class='add'>+	if (se_num == 0xffffffff)</div><div class='add'>+		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,</div><div class='add'>+				     1);</div><div class='add'>+	else</div><div class='add'>+		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);</div><div class='add'>+</div><div class='add'>+	if (sh_num == 0xffffffff)</div><div class='add'>+		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,</div><div class='add'>+				     1);</div><div class='add'>+	else</div><div class='add'>+		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;</div><div class='add'>+</div><div class='add'>+	gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);</div><div class='add'>+	gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,</div><div class='add'>+					    GRBM_CC_GC_SA_UNIT_DISABLE,</div><div class='add'>+					    SA_DISABLE);</div><div class='add'>+	gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);</div><div class='add'>+	gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,</div><div class='add'>+						 GRBM_GC_USER_SA_UNIT_DISABLE,</div><div class='add'>+						 SA_DISABLE);</div><div class='add'>+	sa_mask = amdgpu_gfx_create_bitmask(adev-&gt;gfx.config.max_sh_per_se *</div><div class='add'>+					    adev-&gt;gfx.config.max_shader_engines);</div><div class='add'>+</div><div class='add'>+	return sa_mask &amp; (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;</div><div class='add'>+	u32 rb_mask;</div><div class='add'>+</div><div class='add'>+	gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);</div><div class='add'>+	gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,</div><div class='add'>+					    CC_RB_BACKEND_DISABLE,</div><div class='add'>+					    BACKEND_DISABLE);</div><div class='add'>+	gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);</div><div class='add'>+	gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,</div><div class='add'>+						 GC_USER_RB_BACKEND_DISABLE,</div><div class='add'>+						 BACKEND_DISABLE);</div><div class='add'>+	rb_mask = amdgpu_gfx_create_bitmask(adev-&gt;gfx.config.max_backends_per_se *</div><div class='add'>+					    adev-&gt;gfx.config.max_shader_engines);</div><div class='add'>+</div><div class='add'>+	return rb_mask &amp; (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 rb_bitmap_per_sa;</div><div class='add'>+	u32 rb_bitmap_width_per_sa;</div><div class='add'>+	u32 max_sa;</div><div class='add'>+	u32 active_sa_bitmap;</div><div class='add'>+	u32 global_active_rb_bitmap;</div><div class='add'>+	u32 active_rb_bitmap = 0;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	/* query sa bitmap from SA_UNIT_DISABLE registers */</div><div class='add'>+	active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);</div><div class='add'>+	/* query rb bitmap from RB_BACKEND_DISABLE registers */</div><div class='add'>+	global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);</div><div class='add'>+</div><div class='add'>+	/* generate active rb bitmap according to active sa bitmap */</div><div class='add'>+	max_sa = adev-&gt;gfx.config.max_shader_engines *</div><div class='add'>+		 adev-&gt;gfx.config.max_sh_per_se;</div><div class='add'>+	rb_bitmap_width_per_sa = adev-&gt;gfx.config.max_backends_per_se /</div><div class='add'>+				 adev-&gt;gfx.config.max_sh_per_se;</div><div class='add'>+	rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; max_sa; i++) {</div><div class='add'>+		if (active_sa_bitmap &amp; (1 &lt;&lt; i))</div><div class='add'>+			active_rb_bitmap |= (rb_bitmap_per_sa &lt;&lt; (i * rb_bitmap_width_per_sa));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	active_rb_bitmap &amp;= global_active_rb_bitmap;</div><div class='add'>+	adev-&gt;gfx.config.backend_enable_mask = active_rb_bitmap;</div><div class='add'>+	adev-&gt;gfx.config.num_rbs = hweight32(active_rb_bitmap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define LDS_APP_BASE           0x1</div><div class='add'>+#define SCRATCH_APP_BASE       0x2</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t sh_mem_bases;</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Configure apertures:</div><div class='add'>+	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)</div><div class='add'>+	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)</div><div class='add'>+	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)</div><div class='add'>+	 */</div><div class='add'>+	sh_mem_bases = (LDS_APP_BASE &lt;&lt; SH_MEM_BASES__SHARED_BASE__SHIFT) |</div><div class='add'>+			SCRATCH_APP_BASE;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = adev-&gt;vm_manager.first_kfd_vmid; i &lt; AMDGPU_NUM_VMID; i++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, 0, 0, i);</div><div class='add'>+		/* CP and shaders */</div><div class='add'>+		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);</div><div class='add'>+		WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);</div><div class='add'>+</div><div class='add'>+		/* Enable trap for each kfd vmid. */</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);</div><div class='add'>+		data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* TODO: harvest feature to be added later. */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_constants_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_setup_rb(adev);</div><div class='add'>+	gfx_v12_0_get_cu_info(adev, &amp;adev-&gt;gfx.cu_info);</div><div class='add'>+	gfx_v12_0_get_tcc_info(adev);</div><div class='add'>+	adev-&gt;gfx.config.pa_sc_tile_steering_override = 0;</div><div class='add'>+</div><div class='add'>+	/* XXX SH_MEM regs */</div><div class='add'>+	/* where to put LDS, scratch, GPUVM in FSA64 space */</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, 0, 0, i);</div><div class='add'>+		/* CP and shaders */</div><div class='add'>+		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);</div><div class='add'>+		if (i != 0) {</div><div class='add'>+			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,</div><div class='add'>+				(adev-&gt;gmc.private_aperture_start &gt;&gt; 48));</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,</div><div class='add'>+				(adev-&gt;gmc.shared_aperture_start &gt;&gt; 48));</div><div class='add'>+			WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_init_compute_vmid(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	if (me != 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				      int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * amdgpu controls only the first MEC. That's why this function only</div><div class='add'>+	 * handles the setting of interrupts for this specific MEC. All other</div><div class='add'>+	 * pipes' interrupts are set by amdkfd.</div><div class='add'>+	 */</div><div class='add'>+	if (me != 1)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,</div><div class='add'>+					       bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 tmp, cp_int_cntl_reg;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+			if (cp_int_cntl_reg) {</div><div class='add'>+				tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,</div><div class='add'>+						    enable ? 1 : 0);</div><div class='add'>+				WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_init_csb(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gfx.rlc.funcs-&gt;get_csb_buffer(adev, adev-&gt;gfx.rlc.cs_ptr);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,</div><div class='add'>+			adev-&gt;gfx.rlc.clear_state_gpu_addr &gt;&gt; 32);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,</div><div class='add'>+			adev-&gt;gfx.rlc.clear_state_gpu_addr &amp; 0xfffffffc);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev-&gt;gfx.rlc.clear_state_size);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);</div><div class='add'>+</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);</div><div class='add'>+	udelay(50);</div><div class='add'>+	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);</div><div class='add'>+	udelay(50);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,</div><div class='add'>+					     bool enable)</div><div class='add'>+{</div><div class='add'>+	uint32_t rlc_pg_cntl;</div><div class='add'>+</div><div class='add'>+	rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);</div><div class='add'>+</div><div class='add'>+	if (!enable) {</div><div class='add'>+		/* RLC_PG_CNTL[23] = 0 (default)</div><div class='add'>+		 * RLC will wait for handshake acks with SMU</div><div class='add'>+		 * GFXOFF will be enabled</div><div class='add'>+		 * RLC_PG_CNTL[23] = 1</div><div class='add'>+		 * RLC will not issue any message to SMU</div><div class='add'>+		 * hence no handshake between SMU &amp; RLC</div><div class='add'>+		 * GFXOFF will be disabled</div><div class='add'>+		 */</div><div class='add'>+		rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;</div><div class='add'>+	} else</div><div class='add'>+		rlc_pg_cntl &amp;= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_start(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* TODO: enable rlc &amp; smu handshake until smu</div><div class='add'>+	 * and gfxoff feature works as expected */</div><div class='add'>+	if (!(amdgpu_pp_feature_mask &amp; PP_GFXOFF_MASK))</div><div class='add'>+		gfx_v12_0_rlc_smu_handshake_cntl(adev, false);</div><div class='add'>+</div><div class='add'>+	WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);</div><div class='add'>+	udelay(50);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* enable Save Restore Machine */</div><div class='add'>+	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));</div><div class='add'>+	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;</div><div class='add'>+	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;</div><div class='add'>+	WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct rlc_firmware_header_v2_0 *hdr;</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	unsigned i, fw_size;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+			   le32_to_cpu(hdr-&gt;header.ucode_array_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(hdr-&gt;header.ucode_size_bytes) / 4;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,</div><div class='add'>+		     RLCG_UCODE_LOADING_START_ADDRESS);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; fw_size; i++)</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,</div><div class='add'>+			     le32_to_cpup(fw_data++));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev-&gt;gfx.rlc_fw_version);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct rlc_firmware_header_v2_2 *hdr;</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	unsigned i, fw_size;</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct rlc_firmware_header_v2_2 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+			le32_to_cpu(hdr-&gt;rlc_iram_ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(hdr-&gt;rlc_iram_ucode_size_bytes) / 4;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; fw_size; i++) {</div><div class='add'>+		if ((amdgpu_emu_mode == 1) &amp;&amp; (i % 100 == 99))</div><div class='add'>+			msleep(1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,</div><div class='add'>+				le32_to_cpup(fw_data++));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev-&gt;gfx.rlc_fw_version);</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.rlc_fw-&gt;data +</div><div class='add'>+			le32_to_cpu(hdr-&gt;rlc_dram_ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(hdr-&gt;rlc_dram_ucode_size_bytes) / 4;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);</div><div class='add'>+	for (i = 0; i &lt; fw_size; i++) {</div><div class='add'>+		if ((amdgpu_emu_mode == 1) &amp;&amp; (i % 100 == 99))</div><div class='add'>+			msleep(1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,</div><div class='add'>+				le32_to_cpup(fw_data++));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev-&gt;gfx.rlc_fw_version);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct rlc_firmware_header_v2_0 *hdr;</div><div class='add'>+	uint16_t version_major;</div><div class='add'>+	uint16_t version_minor;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.rlc_fw)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='add'>+	amdgpu_ucode_print_rlc_hdr(&amp;hdr-&gt;header);</div><div class='add'>+</div><div class='add'>+	version_major = le16_to_cpu(hdr-&gt;header.header_version_major);</div><div class='add'>+	version_minor = le16_to_cpu(hdr-&gt;header.header_version_minor);</div><div class='add'>+</div><div class='add'>+	if (version_major == 2) {</div><div class='add'>+		gfx_v12_0_load_rlcg_microcode(adev);</div><div class='add'>+		if (amdgpu_dpm == 1) {</div><div class='add'>+			if (version_minor &gt;= 2)</div><div class='add'>+				gfx_v12_0_load_rlc_iram_dram_microcode(adev);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+		gfx_v12_0_init_csb(adev);</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */</div><div class='add'>+			gfx_v12_0_rlc_enable_srm(adev);</div><div class='add'>+	} else {</div><div class='add'>+		if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+			gfx_v12_0_init_csb(adev);</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		adev-&gt;gfx.rlc.funcs-&gt;stop(adev);</div><div class='add'>+</div><div class='add'>+		/* disable CG */</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);</div><div class='add'>+</div><div class='add'>+		/* disable PG */</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+			/* legacy rlc firmware loading */</div><div class='add'>+			r = gfx_v12_0_rlc_load_microcode(adev);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		gfx_v12_0_init_csb(adev);</div><div class='add'>+</div><div class='add'>+		adev-&gt;gfx.rlc.funcs-&gt;start(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *pfp_hdr;</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *me_hdr;</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *mec_hdr;</div><div class='add'>+	uint32_t pipe_id, tmp;</div><div class='add'>+</div><div class='add'>+	mec_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.mec_fw-&gt;data;</div><div class='add'>+	me_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.me_fw-&gt;data;</div><div class='add'>+	pfp_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.pfp_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+	/* config pfp program start addr */</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; 2; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, pipe_id, 0, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,</div><div class='add'>+			(pfp_hdr-&gt;ucode_start_addr_hi &lt;&lt; 30) |</div><div class='add'>+			(pfp_hdr-&gt;ucode_start_addr_lo &gt;&gt; 2));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,</div><div class='add'>+			pfp_hdr-&gt;ucode_start_addr_hi &gt;&gt; 2);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* reset pfp pipe */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* clear pfp pipe reset */</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* config me program start addr */</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; 2; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, pipe_id, 0, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,</div><div class='add'>+			(me_hdr-&gt;ucode_start_addr_hi &lt;&lt; 30) |</div><div class='add'>+			(me_hdr-&gt;ucode_start_addr_lo &gt;&gt; 2));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,</div><div class='add'>+			me_hdr-&gt;ucode_start_addr_hi&gt;&gt;2);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* reset me pipe */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* clear me pipe reset */</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* config mec program start addr */</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; 4; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 1, pipe_id, 0, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,</div><div class='add'>+					mec_hdr-&gt;ucode_start_addr_lo &gt;&gt; 2 |</div><div class='add'>+					mec_hdr-&gt;ucode_start_addr_hi &lt;&lt; 30);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,</div><div class='add'>+					mec_hdr-&gt;ucode_start_addr_hi &gt;&gt; 2);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* reset mec pipe */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* clear mec pipe reset */</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *cp_hdr;</div><div class='add'>+	unsigned pipe_id, tmp;</div><div class='add'>+</div><div class='add'>+	cp_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.pfp_fw-&gt;data;</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; adev-&gt;gfx.me.num_pipe_per_me; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, pipe_id, 0, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,</div><div class='add'>+			     (cp_hdr-&gt;ucode_start_addr_hi &lt;&lt; 30) |</div><div class='add'>+			     (cp_hdr-&gt;ucode_start_addr_lo &gt;&gt; 2));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,</div><div class='add'>+			     cp_hdr-&gt;ucode_start_addr_hi&gt;&gt;2);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Program CP_ME_CNTL to reset given PIPE to take</div><div class='add'>+		 * effect of CP_PFP_PRGRM_CNTR_START.</div><div class='add'>+		 */</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					PFP_PIPE0_RESET, 1);</div><div class='add'>+		else</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					PFP_PIPE1_RESET, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+		/* Clear pfp pipe0 reset bit. */</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					PFP_PIPE0_RESET, 0);</div><div class='add'>+		else</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					PFP_PIPE1_RESET, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *cp_hdr;</div><div class='add'>+	unsigned pipe_id, tmp;</div><div class='add'>+</div><div class='add'>+	cp_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.me_fw-&gt;data;</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; adev-&gt;gfx.me.num_pipe_per_me; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, pipe_id, 0, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,</div><div class='add'>+			     (cp_hdr-&gt;ucode_start_addr_hi &lt;&lt; 30) |</div><div class='add'>+			     (cp_hdr-&gt;ucode_start_addr_lo &gt;&gt; 2) );</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,</div><div class='add'>+			     cp_hdr-&gt;ucode_start_addr_hi&gt;&gt;2);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Program CP_ME_CNTL to reset given PIPE to take</div><div class='add'>+		 * effect of CP_ME_PRGRM_CNTR_START.</div><div class='add'>+		 */</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					ME_PIPE0_RESET, 1);</div><div class='add'>+		else</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					ME_PIPE1_RESET, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+		/* Clear pfp pipe0 reset bit. */</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					ME_PIPE0_RESET, 0);</div><div class='add'>+		else</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,</div><div class='add'>+					ME_PIPE1_RESET, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *cp_hdr;</div><div class='add'>+	unsigned pipe_id;</div><div class='add'>+</div><div class='add'>+	cp_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.mec_fw-&gt;data;</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; adev-&gt;gfx.mec.num_pipe_per_mec; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 1, pipe_id, 0, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,</div><div class='add'>+			     cp_hdr-&gt;ucode_start_addr_lo &gt;&gt; 2 |</div><div class='add'>+			     cp_hdr-&gt;ucode_start_addr_hi &lt;&lt; 30);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,</div><div class='add'>+			     cp_hdr-&gt;ucode_start_addr_hi &gt;&gt; 2);</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t cp_status;</div><div class='add'>+	uint32_t bootload_status;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		cp_status = RREG32_SOC15(GC, 0, regCP_STAT);</div><div class='add'>+		bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);</div><div class='add'>+</div><div class='add'>+		if ((cp_status == 0) &amp;&amp;</div><div class='add'>+		    (REG_GET_FIELD(bootload_status,</div><div class='add'>+			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		udelay(1);</div><div class='add'>+		if (amdgpu_emu_mode)</div><div class='add'>+			msleep(10);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "rlc autoload: gc ucode autoload timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {</div><div class='add'>+		gfx_v12_0_set_pfp_ucode_start_addr(adev);</div><div class='add'>+		gfx_v12_0_set_me_ucode_start_addr(adev);</div><div class='add'>+		gfx_v12_0_set_mec_ucode_start_addr(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);</div><div class='add'>+</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *pfp_hdr;</div><div class='add'>+	const __le32 *fw_ucode, *fw_data;</div><div class='add'>+	unsigned i, pipe_id, fw_ucode_size, fw_data_size;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	uint32_t usec_timeout = 50000;  /* wait for 50ms */</div><div class='add'>+</div><div class='add'>+	pfp_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.pfp_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+	amdgpu_ucode_print_gfx_hdr(&amp;pfp_hdr-&gt;header);</div><div class='add'>+</div><div class='add'>+	/* instruction */</div><div class='add'>+	fw_ucode = (const __le32 *)(adev-&gt;gfx.pfp_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(pfp_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_ucode_size = le32_to_cpu(pfp_hdr-&gt;ucode_size_bytes);</div><div class='add'>+	/* data */</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.pfp_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(pfp_hdr-&gt;data_offset_bytes));</div><div class='add'>+	fw_data_size = le32_to_cpu(pfp_hdr-&gt;data_size_bytes);</div><div class='add'>+</div><div class='add'>+	/* 64kb align */</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,</div><div class='add'>+				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.pfp.pfp_fw_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.pfp.pfp_fw_gpu_addr,</div><div class='add'>+				      (void **)&amp;adev-&gt;gfx.pfp.pfp_fw_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create pfp ucode fw bo\n", r);</div><div class='add'>+		gfx_v12_0_pfp_fini(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_data_size,</div><div class='add'>+				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.pfp.pfp_fw_data_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.pfp.pfp_fw_data_gpu_addr,</div><div class='add'>+				      (void **)&amp;adev-&gt;gfx.pfp.pfp_fw_data_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create pfp data fw bo\n", r);</div><div class='add'>+		gfx_v12_0_pfp_fini(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(adev-&gt;gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);</div><div class='add'>+	memcpy(adev-&gt;gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;gfx.pfp.pfp_fw_obj);</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;gfx.pfp.pfp_fw_data_obj);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;gfx.pfp.pfp_fw_obj);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;gfx.pfp.pfp_fw_data_obj);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_emu_mode == 1)</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,</div><div class='add'>+		lower_32_bits(adev-&gt;gfx.pfp.pfp_fw_gpu_addr));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,</div><div class='add'>+		upper_32_bits(adev-&gt;gfx.pfp.pfp_fw_gpu_addr));</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Programming any of the CP_PFP_IC_BASE registers</div><div class='add'>+	 * forces invalidation of the ME L1 I$. Wait for the</div><div class='add'>+	 * invalidation complete</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,</div><div class='add'>+			INVALIDATE_CACHE_COMPLETE))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to invalidate instruction cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Prime the L1 instruction caches */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);</div><div class='add'>+	/* Waiting for cache primed*/</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,</div><div class='add'>+			ICACHE_PRIMED))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to prime instruction cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; adev-&gt;gfx.me.num_pipe_per_me; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, pipe_id, 0, 0);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,</div><div class='add'>+			lower_32_bits(adev-&gt;gfx.pfp.pfp_fw_data_gpu_addr));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,</div><div class='add'>+			upper_32_bits(adev-&gt;gfx.pfp.pfp_fw_data_gpu_addr));</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Invalidate the data caches */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,</div><div class='add'>+			INVALIDATE_DCACHE_COMPLETE))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to invalidate RS64 data cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_set_pfp_ucode_start_addr(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *me_hdr;</div><div class='add'>+	const __le32 *fw_ucode, *fw_data;</div><div class='add'>+	unsigned i, pipe_id, fw_ucode_size, fw_data_size;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	uint32_t usec_timeout = 50000;  /* wait for 50ms */</div><div class='add'>+</div><div class='add'>+	me_hdr = (const struct gfx_firmware_header_v2_0 *)</div><div class='add'>+		adev-&gt;gfx.me_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+	amdgpu_ucode_print_gfx_hdr(&amp;me_hdr-&gt;header);</div><div class='add'>+</div><div class='add'>+	/* instruction */</div><div class='add'>+	fw_ucode = (const __le32 *)(adev-&gt;gfx.me_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(me_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_ucode_size = le32_to_cpu(me_hdr-&gt;ucode_size_bytes);</div><div class='add'>+	/* data */</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.me_fw-&gt;data +</div><div class='add'>+		le32_to_cpu(me_hdr-&gt;data_offset_bytes));</div><div class='add'>+	fw_data_size = le32_to_cpu(me_hdr-&gt;data_size_bytes);</div><div class='add'>+</div><div class='add'>+	/* 64kb align*/</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,</div><div class='add'>+				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.me.me_fw_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.me.me_fw_gpu_addr,</div><div class='add'>+				      (void **)&amp;adev-&gt;gfx.me.me_fw_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create me ucode bo\n", r);</div><div class='add'>+		gfx_v12_0_me_fini(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_data_size,</div><div class='add'>+				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.me.me_fw_data_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.me.me_fw_data_gpu_addr,</div><div class='add'>+				      (void **)&amp;adev-&gt;gfx.me.me_fw_data_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create me data bo\n", r);</div><div class='add'>+		gfx_v12_0_me_fini(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(adev-&gt;gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);</div><div class='add'>+	memcpy(adev-&gt;gfx.me.me_fw_data_ptr, fw_data, fw_data_size);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;gfx.me.me_fw_obj);</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;gfx.me.me_fw_data_obj);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;gfx.me.me_fw_obj);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;gfx.me.me_fw_data_obj);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_emu_mode == 1)</div><div class='add'>+		amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,</div><div class='add'>+		lower_32_bits(adev-&gt;gfx.me.me_fw_gpu_addr));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,</div><div class='add'>+		upper_32_bits(adev-&gt;gfx.me.me_fw_gpu_addr));</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Programming any of the CP_ME_IC_BASE registers</div><div class='add'>+	 * forces invalidation of the ME L1 I$. Wait for the</div><div class='add'>+	 * invalidation complete</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,</div><div class='add'>+			INVALIDATE_CACHE_COMPLETE))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to invalidate instruction cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Prime the instruction caches */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Waiting for instruction cache primed*/</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,</div><div class='add'>+			ICACHE_PRIMED))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to prime instruction cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (pipe_id = 0; pipe_id &lt; adev-&gt;gfx.me.num_pipe_per_me; pipe_id++) {</div><div class='add'>+		soc24_grbm_select(adev, 0, pipe_id, 0, 0);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,</div><div class='add'>+			lower_32_bits(adev-&gt;gfx.me.me_fw_data_gpu_addr));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,</div><div class='add'>+			upper_32_bits(adev-&gt;gfx.me.me_fw_data_gpu_addr));</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Invalidate the data caches */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,</div><div class='add'>+			INVALIDATE_DCACHE_COMPLETE))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to invalidate RS64 data cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_set_me_ucode_start_addr(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.me_fw || !adev-&gt;gfx.pfp_fw)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_cp_gfx_enable(adev, false);</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to load pfp fw\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to load me fw\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* init the CP */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,</div><div class='add'>+		     adev-&gt;gfx.config.max_hw_contexts - 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_async_gfx_ring)</div><div class='add'>+		gfx_v12_0_cp_gfx_enable(adev, true);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,</div><div class='add'>+					 CP_PIPE_ID pipe)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,</div><div class='add'>+					  struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_OFFSET, ring-&gt;doorbell_index);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 1);</div><div class='add'>+	} else {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 0);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,</div><div class='add'>+			    DOORBELL_RANGE_LOWER, ring-&gt;doorbell_index);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,</div><div class='add'>+		     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	u32 tmp;</div><div class='add'>+	u32 rb_bufsz;</div><div class='add'>+	u64 rb_addr, rptr_addr, wptr_gpu_addr;</div><div class='add'>+</div><div class='add'>+	/* Set the write pointer delay */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);</div><div class='add'>+</div><div class='add'>+	/* set the RB to use vmid 0 */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);</div><div class='add'>+</div><div class='add'>+	/* Init gfx ring 0 for pipe 0 */</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);</div><div class='add'>+</div><div class='add'>+	/* Set ring buffer size */</div><div class='add'>+	ring = &amp;adev-&gt;gfx.gfx_ring[0];</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size / 8);</div><div class='add'>+	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Initialize the ring buffer's write pointers */</div><div class='add'>+	ring-&gt;wptr = 0;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring-&gt;wptr));</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp;</div><div class='add'>+		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);</div><div class='add'>+</div><div class='add'>+	wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,</div><div class='add'>+		     lower_32_bits(wptr_gpu_addr));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,</div><div class='add'>+		     upper_32_bits(wptr_gpu_addr));</div><div class='add'>+</div><div class='add'>+	mdelay(1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	rb_addr = ring-&gt;gpu_addr &gt;&gt; 8;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_cp_gfx_set_doorbell(adev, ring);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	/* Switch to pipe 0 */</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	/* start the ring */</div><div class='add'>+	gfx_v12_0_cp_gfx_start(adev);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 data;</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,</div><div class='add'>+						 enable ? 0 : 1);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,</div><div class='add'>+						 enable ? 0 : 1);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,</div><div class='add'>+						 enable ? 0 : 1);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,</div><div class='add'>+						 enable ? 0 : 1);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,</div><div class='add'>+						 enable ? 0 : 1);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,</div><div class='add'>+						 enable ? 1 : 0);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,</div><div class='add'>+			                         enable ? 1 : 0);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,</div><div class='add'>+						 enable ? 1 : 0);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,</div><div class='add'>+						 enable ? 1 : 0);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,</div><div class='add'>+						 enable ? 0 : 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.kiq[0].ring.sched.ready = enable;</div><div class='add'>+</div><div class='add'>+	udelay(50);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct gfx_firmware_header_v2_0 *mec_hdr;</div><div class='add'>+	const __le32 *fw_ucode, *fw_data;</div><div class='add'>+	u32 tmp, fw_ucode_size, fw_data_size;</div><div class='add'>+	u32 i, usec_timeout = 50000; /* Wait for 50 ms */</div><div class='add'>+	u32 *fw_ucode_ptr, *fw_data_ptr;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.mec_fw)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_cp_compute_enable(adev, false);</div><div class='add'>+</div><div class='add'>+	mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev-&gt;gfx.mec_fw-&gt;data;</div><div class='add'>+	amdgpu_ucode_print_gfx_hdr(&amp;mec_hdr-&gt;header);</div><div class='add'>+</div><div class='add'>+	fw_ucode = (const __le32 *) (adev-&gt;gfx.mec_fw-&gt;data +</div><div class='add'>+				le32_to_cpu(mec_hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_ucode_size = le32_to_cpu(mec_hdr-&gt;ucode_size_bytes);</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *) (adev-&gt;gfx.mec_fw-&gt;data +</div><div class='add'>+				le32_to_cpu(mec_hdr-&gt;data_offset_bytes));</div><div class='add'>+	fw_data_size = le32_to_cpu(mec_hdr-&gt;data_size_bytes);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,</div><div class='add'>+				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.mec.mec_fw_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.mec.mec_fw_gpu_addr,</div><div class='add'>+				      (void **)&amp;fw_ucode_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create mec fw ucode bo\n", r);</div><div class='add'>+		gfx_v12_0_mec_fini(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev,</div><div class='add'>+				      ALIGN(fw_data_size, 64 * 1024) *</div><div class='add'>+				      adev-&gt;gfx.mec.num_pipe_per_mec,</div><div class='add'>+				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;gfx.mec.mec_fw_data_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.mec.mec_fw_data_gpu_addr,</div><div class='add'>+				      (void **)&amp;fw_data_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create mec fw ucode bo\n", r);</div><div class='add'>+		gfx_v12_0_mec_fini(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_pipe_per_mec; i++) {</div><div class='add'>+		memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;gfx.mec.mec_fw_obj);</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;gfx.mec.mec_fw_data_obj);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;gfx.mec.mec_fw_obj);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;gfx.mec.mec_fw_data_obj);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_pipe_per_mec; i++) {</div><div class='add'>+		soc24_grbm_select(adev, 1, i, 0, 0);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,</div><div class='add'>+			     lower_32_bits(adev-&gt;gfx.mec.mec_fw_data_gpu_addr +</div><div class='add'>+					   i * ALIGN(fw_data_size, 64 * 1024)));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,</div><div class='add'>+			     upper_32_bits(adev-&gt;gfx.mec.mec_fw_data_gpu_addr +</div><div class='add'>+					   i * ALIGN(fw_data_size, 64 * 1024)));</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,</div><div class='add'>+			     lower_32_bits(adev-&gt;gfx.mec.mec_fw_gpu_addr));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,</div><div class='add'>+			     upper_32_bits(adev-&gt;gfx.mec.mec_fw_gpu_addr));</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* Trigger an invalidation of the L1 instruction caches */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Wait for invalidation complete */</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,</div><div class='add'>+				       INVALIDATE_DCACHE_COMPLETE))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to invalidate instruction cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Trigger an invalidation of the L1 instruction caches */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Wait for invalidation complete */</div><div class='add'>+	for (i = 0; i &lt; usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);</div><div class='add'>+		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,</div><div class='add'>+				       INVALIDATE_CACHE_COMPLETE))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to invalidate instruction cache\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_set_mec_ucode_start_addr(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* tell RLC which is KIQ queue */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);</div><div class='add'>+	tmp &amp;= 0xffffff00;</div><div class='add'>+	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* set graphics engine doorbell range */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,</div><div class='add'>+		     (adev-&gt;doorbell_index.gfx_ring0 * 2) &lt;&lt; 2);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,</div><div class='add'>+		     (adev-&gt;doorbell_index.gfx_userqueue_end * 2) &lt;&lt; 2);</div><div class='add'>+</div><div class='add'>+	/* set compute engine doorbell range */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,</div><div class='add'>+		     (adev-&gt;doorbell_index.kiq * 2) &lt;&lt; 2);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,</div><div class='add'>+		     (adev-&gt;doorbell_index.userqueue_end * 2) &lt;&lt; 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='add'>+				  struct amdgpu_mqd_prop *prop)</div><div class='add'>+{</div><div class='add'>+	struct v12_gfx_mqd *mqd = m;</div><div class='add'>+	uint64_t hqd_gpu_addr, wb_gpu_addr;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	uint32_t rb_bufsz;</div><div class='add'>+</div><div class='add'>+	/* set up gfx hqd wptr */</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_wptr = 0;</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_wptr_hi = 0;</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the MQD */</div><div class='add'>+	mqd-&gt;cp_mqd_base_addr = prop-&gt;mqd_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_mqd_base_addr_hi = upper_32_bits(prop-&gt;mqd_gpu_addr);</div><div class='add'>+</div><div class='add'>+	/* set up mqd control */</div><div class='add'>+	tmp = regCP_GFX_MQD_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);</div><div class='add'>+	mqd-&gt;cp_gfx_mqd_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */</div><div class='add'>+	tmp = regCP_GFX_HQD_VMID_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_vmid = 0;</div><div class='add'>+</div><div class='add'>+	/* set up default queue priority level</div><div class='add'>+	 * 0x0 = low priority, 0x1 = high priority */</div><div class='add'>+	tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_queue_priority = tmp;</div><div class='add'>+</div><div class='add'>+	/* set up time quantum */</div><div class='add'>+	tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_quantum = tmp;</div><div class='add'>+</div><div class='add'>+	/* set up gfx hqd base. this is similar as CP_RB_BASE */</div><div class='add'>+	hqd_gpu_addr = prop-&gt;hqd_base_gpu_addr &gt;&gt; 8;</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_base = hqd_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);</div><div class='add'>+</div><div class='add'>+	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */</div><div class='add'>+	wb_gpu_addr = prop-&gt;rptr_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_rptr_addr = wb_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_rptr_addr_hi =</div><div class='add'>+		upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	/* set up rb_wptr_poll addr */</div><div class='add'>+	wb_gpu_addr = prop-&gt;wptr_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_rb_wptr_poll_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */</div><div class='add'>+	rb_bufsz = order_base_2(prop-&gt;queue_size / 4) - 1;</div><div class='add'>+	tmp = regCP_GFX_HQD_CNTL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);</div><div class='add'>+#ifdef __BIG_ENDIAN</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);</div><div class='add'>+#endif</div><div class='add'>+	if (prop-&gt;tmz_queue)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);</div><div class='add'>+	if (!prop-&gt;kernel_queue)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_cntl = tmp;</div><div class='add'>+</div><div class='add'>+	/* set up cp_doorbell_control */</div><div class='add'>+	tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;</div><div class='add'>+	if (prop-&gt;use_doorbell) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_OFFSET, prop-&gt;doorbell_index);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 1);</div><div class='add'>+	} else</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 0);</div><div class='add'>+	mqd-&gt;cp_rb_doorbell_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;</div><div class='add'>+</div><div class='add'>+	/* active the queue */</div><div class='add'>+	mqd-&gt;cp_gfx_hqd_active = 1;</div><div class='add'>+</div><div class='add'>+	/* set gfx UQ items */</div><div class='add'>+	mqd-&gt;shadow_base_lo = lower_32_bits(prop-&gt;shadow_addr);</div><div class='add'>+	mqd-&gt;shadow_base_hi = upper_32_bits(prop-&gt;shadow_addr);</div><div class='add'>+	mqd-&gt;fw_work_area_base_lo = lower_32_bits(prop-&gt;csa_addr);</div><div class='add'>+	mqd-&gt;fw_work_area_base_hi = upper_32_bits(prop-&gt;csa_addr);</div><div class='add'>+	mqd-&gt;fence_address_lo = lower_32_bits(prop-&gt;fence_address);</div><div class='add'>+	mqd-&gt;fence_address_hi = upper_32_bits(prop-&gt;fence_address);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct v12_gfx_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='add'>+	int mqd_idx = ring - &amp;adev-&gt;gfx.gfx_ring[0];</div><div class='add'>+</div><div class='add'>+	if (!reset &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc24_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+		amdgpu_ring_init_mqd(ring);</div><div class='add'>+		soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		if (adev-&gt;gfx.me.mqd_backup[mqd_idx])</div><div class='add'>+			memcpy_fromio(adev-&gt;gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));</div><div class='add'>+	} else {</div><div class='add'>+		/* restore mqd with the backup copy */</div><div class='add'>+		if (adev-&gt;gfx.me.mqd_backup[mqd_idx])</div><div class='add'>+			memcpy_toio(mqd, adev-&gt;gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));</div><div class='add'>+		/* reset the ring */</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='add'>+		*ring-&gt;wptr_cpu_addr = 0;</div><div class='add'>+		amdgpu_ring_clear_ring(ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+		r = gfx_v12_0_kgq_init_queue(&amp;adev-&gt;gfx.gfx_ring[i], false);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_enable_kgq(adev, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return gfx_v12_0_cp_gfx_start(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='add'>+				      struct amdgpu_mqd_prop *prop)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *mqd = m;</div><div class='add'>+	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	mqd-&gt;header = 0xC0310800;</div><div class='add'>+	mqd-&gt;compute_pipelinestat_enable = 0x00000001;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se0 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se1 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se2 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se3 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_misc_reserved = 0x00000007;</div><div class='add'>+</div><div class='add'>+	eop_base_addr = prop-&gt;eop_gpu_addr &gt;&gt; 8;</div><div class='add'>+	mqd-&gt;cp_hqd_eop_base_addr_lo = eop_base_addr;</div><div class='add'>+	mqd-&gt;cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);</div><div class='add'>+</div><div class='add'>+	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */</div><div class='add'>+	tmp = regCP_HQD_EOP_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,</div><div class='add'>+			(order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_eop_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* enable doorbell? */</div><div class='add'>+	tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;</div><div class='add'>+</div><div class='add'>+	if (prop-&gt;use_doorbell) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_OFFSET, prop-&gt;doorbell_index);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_SOURCE, 0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_HIT, 0);</div><div class='add'>+	} else {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_pq_doorbell_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* disable the queue if it's active */</div><div class='add'>+	mqd-&gt;cp_hqd_dequeue_request = 0;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr = 0;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_lo = 0;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_hi = 0;</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the MQD */</div><div class='add'>+	mqd-&gt;cp_mqd_base_addr_lo = prop-&gt;mqd_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_mqd_base_addr_hi = upper_32_bits(prop-&gt;mqd_gpu_addr);</div><div class='add'>+</div><div class='add'>+	/* set MQD vmid to 0 */</div><div class='add'>+	tmp = regCP_MQD_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);</div><div class='add'>+	mqd-&gt;cp_mqd_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */</div><div class='add'>+	hqd_gpu_addr = prop-&gt;hqd_base_gpu_addr &gt;&gt; 8;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_base_lo = hqd_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);</div><div class='add'>+</div><div class='add'>+	/* set up the HQD, this is similar to CP_RB0_CNTL */</div><div class='add'>+	tmp = regCP_HQD_PQ_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,</div><div class='add'>+			    (order_base_2(prop-&gt;queue_size / 4) - 1));</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,</div><div class='add'>+			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);</div><div class='add'>+	if (prop-&gt;kernel_queue) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='add'>+	}</div><div class='add'>+	if (prop-&gt;tmz_queue)</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);</div><div class='add'>+	mqd-&gt;cp_hqd_pq_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	wb_gpu_addr = prop-&gt;rptr_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr_report_addr_hi =</div><div class='add'>+		upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */</div><div class='add'>+	wb_gpu_addr = prop-&gt;wptr_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	tmp = 0;</div><div class='add'>+	/* enable the doorbell if requested */</div><div class='add'>+	if (prop-&gt;use_doorbell) {</div><div class='add'>+		tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				DOORBELL_OFFSET, prop-&gt;doorbell_index);</div><div class='add'>+</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_SOURCE, 0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_HIT, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_pq_doorbell_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;</div><div class='add'>+</div><div class='add'>+	/* set the vmid for the queue */</div><div class='add'>+	mqd-&gt;cp_hqd_vmid = 0;</div><div class='add'>+</div><div class='add'>+	tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);</div><div class='add'>+	mqd-&gt;cp_hqd_persistent_state = tmp;</div><div class='add'>+</div><div class='add'>+	/* set MIN_IB_AVAIL_SIZE */</div><div class='add'>+	tmp = regCP_HQD_IB_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);</div><div class='add'>+	mqd-&gt;cp_hqd_ib_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* set static priority for a compute queue/ring */</div><div class='add'>+	mqd-&gt;cp_hqd_pipe_priority = prop-&gt;hqd_pipe_priority;</div><div class='add'>+	mqd-&gt;cp_hqd_queue_priority = prop-&gt;hqd_queue_priority;</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_active = prop-&gt;hqd_active;</div><div class='add'>+</div><div class='add'>+	/* set UQ fenceaddress */</div><div class='add'>+	mqd-&gt;fence_address_lo = lower_32_bits(prop-&gt;fence_address);</div><div class='add'>+	mqd-&gt;fence_address_hi = upper_32_bits(prop-&gt;fence_address);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct v12_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='add'>+	int j;</div><div class='add'>+</div><div class='add'>+	/* inactivate the queue */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);</div><div class='add'>+</div><div class='add'>+	/* disable wptr polling */</div><div class='add'>+	WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);</div><div class='add'>+</div><div class='add'>+	/* write the EOP addr */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,</div><div class='add'>+	       mqd-&gt;cp_hqd_eop_base_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,</div><div class='add'>+	       mqd-&gt;cp_hqd_eop_base_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,</div><div class='add'>+	       mqd-&gt;cp_hqd_eop_control);</div><div class='add'>+</div><div class='add'>+	/* enable doorbell? */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_doorbell_control);</div><div class='add'>+</div><div class='add'>+	/* disable the queue if it's active */</div><div class='add'>+	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp; 1) {</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,</div><div class='add'>+		       mqd-&gt;cp_hqd_dequeue_request);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,</div><div class='add'>+		       mqd-&gt;cp_hqd_pq_rptr);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,</div><div class='add'>+		       mqd-&gt;cp_hqd_pq_wptr_lo);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,</div><div class='add'>+		       mqd-&gt;cp_hqd_pq_wptr_hi);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the MQD */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,</div><div class='add'>+	       mqd-&gt;cp_mqd_base_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,</div><div class='add'>+	       mqd-&gt;cp_mqd_base_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* set MQD vmid to 0 */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,</div><div class='add'>+	       mqd-&gt;cp_mqd_control);</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_base_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_base_hi);</div><div class='add'>+</div><div class='add'>+	/* set up the HQD, this is similar to CP_RB0_CNTL */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_control);</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,</div><div class='add'>+		mqd-&gt;cp_hqd_pq_rptr_report_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,</div><div class='add'>+		mqd-&gt;cp_hqd_pq_rptr_report_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* enable the doorbell if requested */</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,</div><div class='add'>+			(adev-&gt;doorbell_index.kiq * 2) &lt;&lt; 2);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,</div><div class='add'>+			(adev-&gt;doorbell_index.userqueue_end * 2) &lt;&lt; 2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_doorbell_control);</div><div class='add'>+</div><div class='add'>+	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_wptr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,</div><div class='add'>+	       mqd-&gt;cp_hqd_pq_wptr_hi);</div><div class='add'>+</div><div class='add'>+	/* set the vmid for the queue */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd-&gt;cp_hqd_vmid);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,</div><div class='add'>+	       mqd-&gt;cp_hqd_persistent_state);</div><div class='add'>+</div><div class='add'>+	/* activate the queue */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,</div><div class='add'>+	       mqd-&gt;cp_hqd_active);</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell)</div><div class='add'>+		WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct v12_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='add'>+	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_kiq_setting(ring);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */</div><div class='add'>+		/* reset MQD to a clean status */</div><div class='add'>+		if (adev-&gt;gfx.mec.mqd_backup[mqd_idx])</div><div class='add'>+			memcpy(mqd, adev-&gt;gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));</div><div class='add'>+</div><div class='add'>+		/* reset ring buffer */</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='add'>+		amdgpu_ring_clear_ring(ring);</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc24_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+		gfx_v12_0_kiq_init_register(ring);</div><div class='add'>+		soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	} else {</div><div class='add'>+		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;in_suspend)</div><div class='add'>+			amdgpu_ring_clear_ring(ring);</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc24_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+		amdgpu_ring_init_mqd(ring);</div><div class='add'>+		gfx_v12_0_kiq_init_register(ring);</div><div class='add'>+		soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;gfx.mec.mqd_backup[mqd_idx])</div><div class='add'>+			memcpy(adev-&gt;gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct v12_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='add'>+	int mqd_idx = ring - &amp;adev-&gt;gfx.compute_ring[0];</div><div class='add'>+</div><div class='add'>+	if (!reset &amp;&amp; !amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend) {</div><div class='add'>+		memset((void *)mqd, 0, sizeof(*mqd));</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc24_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+		amdgpu_ring_init_mqd(ring);</div><div class='add'>+		soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;gfx.mec.mqd_backup[mqd_idx])</div><div class='add'>+			memcpy_fromio(adev-&gt;gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));</div><div class='add'>+	} else {</div><div class='add'>+		/* restore MQD to a clean status */</div><div class='add'>+		if (adev-&gt;gfx.mec.mqd_backup[mqd_idx])</div><div class='add'>+			memcpy_toio(mqd, adev-&gt;gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));</div><div class='add'>+		/* reset ring buffer */</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr, 0);</div><div class='add'>+		amdgpu_ring_clear_ring(ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	gfx_v12_0_kiq_init_queue(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='add'>+	adev-&gt;gfx.kiq[0].ring.sched.ready = true;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_async_gfx_ring)</div><div class='add'>+		gfx_v12_0_cp_compute_enable(adev, true);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+		r = gfx_v12_0_kcq_init_queue(&amp;adev-&gt;gfx.compute_ring[i], false);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_gfx_enable_kcq(adev, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r, i;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		gfx_v12_0_enable_gui_idle_interrupt(adev, false);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+		/* legacy firmware loading */</div><div class='add'>+		r = gfx_v12_0_cp_gfx_load_microcode(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		r = gfx_v12_0_cp_compute_load_microcode_rs64(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_cp_set_doorbell_range(adev);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_async_gfx_ring) {</div><div class='add'>+		gfx_v12_0_cp_compute_enable(adev, true);</div><div class='add'>+		gfx_v12_0_cp_gfx_enable(adev, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes_kiq &amp;&amp; adev-&gt;mes.kiq_hw_init)</div><div class='add'>+		r = amdgpu_mes_kiq_hw_init(adev);</div><div class='add'>+	else</div><div class='add'>+		r = gfx_v12_0_kiq_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_kcq_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_async_gfx_ring) {</div><div class='add'>+		r = gfx_v12_0_cp_gfx_resume(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	} else {</div><div class='add'>+		r = gfx_v12_0_cp_async_gfx_ring_resume(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+		ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+		r = amdgpu_ring_test_helper(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+		r = amdgpu_ring_test_helper(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	gfx_v12_0_cp_gfx_enable(adev, enable);</div><div class='add'>+	gfx_v12_0_cp_compute_enable(adev, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	bool value;</div><div class='add'>+</div><div class='add'>+	r = adev-&gt;gfxhub.funcs-&gt;gart_enable(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+</div><div class='add'>+	value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfxhub.funcs-&gt;set_fault_enable_default(adev, value);</div><div class='add'>+	/* TODO investigate why this and the hdp flush above is needed,</div><div class='add'>+	 * are we missing a flush somewhere else? */</div><div class='add'>+	adev-&gt;gmc.gmc_funcs-&gt;flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_gb_addr_config(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 gb_addr_config;</div><div class='add'>+</div><div class='add'>+	gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);</div><div class='add'>+	if (gb_addr_config == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config_fields.num_pkrs =</div><div class='add'>+		1 &lt;&lt; REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config = gb_addr_config;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config_fields.num_pipes = 1 &lt;&lt;</div><div class='add'>+			REG_GET_FIELD(adev-&gt;gfx.config.gb_addr_config,</div><div class='add'>+				      GB_ADDR_CONFIG, NUM_PIPES);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.config.max_tile_pipes =</div><div class='add'>+		adev-&gt;gfx.config.gb_addr_config_fields.num_pipes;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config_fields.max_compress_frags = 1 &lt;&lt;</div><div class='add'>+			REG_GET_FIELD(adev-&gt;gfx.config.gb_addr_config,</div><div class='add'>+				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config_fields.num_rb_per_se = 1 &lt;&lt;</div><div class='add'>+			REG_GET_FIELD(adev-&gt;gfx.config.gb_addr_config,</div><div class='add'>+				      GB_ADDR_CONFIG, NUM_RB_PER_SE);</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config_fields.num_se = 1 &lt;&lt;</div><div class='add'>+			REG_GET_FIELD(adev-&gt;gfx.config.gb_addr_config,</div><div class='add'>+				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 &lt;&lt; (8 +</div><div class='add'>+			REG_GET_FIELD(adev-&gt;gfx.config.gb_addr_config,</div><div class='add'>+				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);</div><div class='add'>+	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);</div><div class='add'>+	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		soc15_program_register_sequence(adev,</div><div class='add'>+						golden_settings_gc_12_0,</div><div class='add'>+						(const u32)ARRAY_SIZE(golden_settings_gc_12_0));</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;rev_id == 0)</div><div class='add'>+			soc15_program_register_sequence(adev,</div><div class='add'>+					golden_settings_gc_12_0_rev0,</div><div class='add'>+					(const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {</div><div class='add'>+		if (adev-&gt;gfx.imu.funcs &amp;&amp; (amdgpu_dpm &gt; 0)) {</div><div class='add'>+			/* RLC autoload sequence 1: Program rlc ram */</div><div class='add'>+			if (adev-&gt;gfx.imu.funcs-&gt;program_rlc_ram)</div><div class='add'>+				adev-&gt;gfx.imu.funcs-&gt;program_rlc_ram(adev);</div><div class='add'>+		}</div><div class='add'>+		/* rlc autoload firmware */</div><div class='add'>+		r = gfx_v12_0_rlc_backdoor_autoload_enable(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+			if (adev-&gt;gfx.imu.funcs &amp;&amp; (amdgpu_dpm &gt; 0)) {</div><div class='add'>+				if (adev-&gt;gfx.imu.funcs-&gt;load_microcode)</div><div class='add'>+					adev-&gt;gfx.imu.funcs-&gt;load_microcode(adev);</div><div class='add'>+				if (adev-&gt;gfx.imu.funcs-&gt;setup_imu)</div><div class='add'>+					adev-&gt;gfx.imu.funcs-&gt;setup_imu(adev);</div><div class='add'>+				if (adev-&gt;gfx.imu.funcs-&gt;start_imu)</div><div class='add'>+					adev-&gt;gfx.imu.funcs-&gt;start_imu(adev);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* disable gpa mode in backdoor loading */</div><div class='add'>+			gfx_v12_0_disable_gpa_mode(adev);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||</div><div class='add'>+	    (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP)) {</div><div class='add'>+		r = gfx_v12_0_wait_for_rlc_autoload_complete(adev);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "(%d) failed to wait rlc autoload complete\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_emu_mode)</div><div class='add'>+		gfx_v12_0_init_golden_registers(adev);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.is_poweron = true;</div><div class='add'>+</div><div class='add'>+	if (get_gb_addr_config(adev))</div><div class='add'>+		DRM_WARN("Invalid gb_addr_config !\n");</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP)</div><div class='add'>+		gfx_v12_0_config_gfx_rs64(adev);</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_gfxhub_enable(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if ((adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT ||</div><div class='add'>+	     adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) &amp;&amp;</div><div class='add'>+	     (amdgpu_dpm == 1)) {</div><div class='add'>+		/**</div><div class='add'>+		 * For gfx 12, rlc firmware loading relies on smu firmware is</div><div class='add'>+		 * loaded firstly, so in direct type, it has to load smc ucode</div><div class='add'>+		 * here before rlc.</div><div class='add'>+		 */</div><div class='add'>+		r = amdgpu_pm_load_smu_firmware(adev, NULL);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_constants_init(adev);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;nbio.funcs-&gt;gc_doorbell_init)</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;gc_doorbell_init(adev);</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_rlc_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * init golden registers and rlc resume may override some registers,</div><div class='add'>+	 * reconfig them here</div><div class='add'>+	 */</div><div class='add'>+	gfx_v12_0_tcp_harvest(adev);</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_cp_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_userq_eop_interrupts(struct amdgpu_device *adev,</div><div class='add'>+					      bool enable)</div><div class='add'>+{</div><div class='add'>+	unsigned int irq_type;</div><div class='add'>+	int m, p, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;userq_funcs[AMDGPU_HW_IP_GFX]) {</div><div class='add'>+		for (m = 0; m &lt; adev-&gt;gfx.me.num_me; m++) {</div><div class='add'>+			for (p = 0; p &lt; adev-&gt;gfx.me.num_pipe_per_me; p++) {</div><div class='add'>+				irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;</div><div class='add'>+				if (enable)</div><div class='add'>+					r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				else</div><div class='add'>+					r = amdgpu_irq_put(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				if (r)</div><div class='add'>+					return r;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;userq_funcs[AMDGPU_HW_IP_COMPUTE]) {</div><div class='add'>+		for (m = 0; m &lt; adev-&gt;gfx.mec.num_mec; ++m) {</div><div class='add'>+			for (p = 0; p &lt; adev-&gt;gfx.mec.num_pipe_per_mec; p++) {</div><div class='add'>+				irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP</div><div class='add'>+					+ (m * adev-&gt;gfx.mec.num_pipe_per_mec)</div><div class='add'>+					+ p;</div><div class='add'>+				if (enable)</div><div class='add'>+					r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				else</div><div class='add'>+					r = amdgpu_irq_put(adev, &amp;adev-&gt;gfx.eop_irq,</div><div class='add'>+							   irq_type);</div><div class='add'>+				if (r)</div><div class='add'>+					return r;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;gfx.idle_work);</div><div class='add'>+</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	gfx_v12_0_set_userq_eop_interrupts(adev, false);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;no_hw_access) {</div><div class='add'>+		if (amdgpu_async_gfx_ring) {</div><div class='add'>+			if (amdgpu_gfx_disable_kgq(adev, 0))</div><div class='add'>+				DRM_ERROR("KGQ disable failed\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_gfx_disable_kcq(adev, 0))</div><div class='add'>+			DRM_ERROR("KCQ disable failed\n");</div><div class='add'>+</div><div class='add'>+		amdgpu_mes_kiq_hw_fini(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		gfx_v12_0_cp_gfx_enable(adev, false);</div><div class='add'>+		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);</div><div class='add'>+		tmp &amp;= 0xffffff00;</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	gfx_v12_0_cp_enable(adev, false);</div><div class='add'>+	gfx_v12_0_enable_gui_idle_interrupt(adev, false);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfxhub.funcs-&gt;gart_disable(adev);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.is_poweron = false;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return gfx_v12_0_hw_fini(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return gfx_v12_0_hw_init(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),</div><div class='add'>+				GRBM_STATUS, GUI_ACTIVE))</div><div class='add'>+		return false;</div><div class='add'>+	else</div><div class='add'>+		return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	unsigned i;</div><div class='add'>+	u32 tmp;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		/* read MC_STATUS */</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &amp;</div><div class='add'>+			GRBM_STATUS__GUI_ACTIVE_MASK;</div><div class='add'>+</div><div class='add'>+		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))</div><div class='add'>+			return 0;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t clock = 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;smuio.funcs &amp;&amp;</div><div class='add'>+	    adev-&gt;smuio.funcs-&gt;get_gpu_clock_counter)</div><div class='add'>+		clock = adev-&gt;smuio.funcs-&gt;get_gpu_clock_counter(adev);</div><div class='add'>+	else</div><div class='add'>+		dev_warn(adev-&gt;dev, "query gpu clock counter is not supported\n");</div><div class='add'>+</div><div class='add'>+	return clock;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_user_queue) {</div><div class='add'>+	case -1:</div><div class='add'>+	case 0:</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.disable_kq = false;</div><div class='add'>+		adev-&gt;gfx.disable_uq = true;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		adev-&gt;gfx.disable_kq = false;</div><div class='add'>+		adev-&gt;gfx.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		adev-&gt;gfx.disable_kq = true;</div><div class='add'>+		adev-&gt;gfx.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.funcs = &amp;gfx_v12_0_gfx_funcs;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.disable_kq) {</div><div class='add'>+		adev-&gt;gfx.num_gfx_rings = 0;</div><div class='add'>+		adev-&gt;gfx.num_compute_rings = 0;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;</div><div class='add'>+		adev-&gt;gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),</div><div class='add'>+						  AMDGPU_MAX_COMPUTE_RINGS);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_set_kiq_pm4_funcs(adev);</div><div class='add'>+	gfx_v12_0_set_ring_funcs(adev);</div><div class='add'>+	gfx_v12_0_set_irq_funcs(adev);</div><div class='add'>+	gfx_v12_0_set_rlc_funcs(adev);</div><div class='add'>+	gfx_v12_0_set_mqd_funcs(adev);</div><div class='add'>+	gfx_v12_0_set_imu_funcs(adev);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_init_rlcg_reg_access_ctrl(adev);</div><div class='add'>+</div><div class='add'>+	return gfx_v12_0_init_microcode(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_set_userq_eop_interrupts(adev, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t rlc_cntl;</div><div class='add'>+</div><div class='add'>+	/* if RLC is not enabled, do nothing */</div><div class='add'>+	rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);</div><div class='add'>+	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev,</div><div class='add'>+				    int xcc_id)</div><div class='add'>+{</div><div class='add'>+	uint32_t data;</div><div class='add'>+	unsigned i;</div><div class='add'>+</div><div class='add'>+	data = RLC_SAFE_MODE__CMD_MASK;</div><div class='add'>+	data |= (1 &lt;&lt; RLC_SAFE_MODE__MESSAGE__SHIFT);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);</div><div class='add'>+</div><div class='add'>+	/* wait for RLC_SAFE_MODE */</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),</div><div class='add'>+				   RLC_SAFE_MODE, CMD))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,</div><div class='add'>+				      int xcc_id)</div><div class='add'>+{</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,</div><div class='add'>+				      bool enable)</div><div class='add'>+{</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_PERF_CLK))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		data &amp;= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;</div><div class='add'>+	else</div><div class='add'>+		data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;</div><div class='add'>+</div><div class='add'>+	if (def != data)</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,</div><div class='add'>+				      struct amdgpu_ring *ring,</div><div class='add'>+				      unsigned vmid)</div><div class='add'>+{</div><div class='add'>+	u32 reg, data;</div><div class='add'>+</div><div class='add'>+	reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);</div><div class='add'>+	if (amdgpu_sriov_is_pp_one_vf(adev))</div><div class='add'>+		data = RREG32_NO_KIQ(reg);</div><div class='add'>+	else</div><div class='add'>+		data = RREG32(reg);</div><div class='add'>+</div><div class='add'>+	data &amp;= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;</div><div class='add'>+	data |= (vmid &amp; RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) &lt;&lt; RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_is_pp_one_vf(adev))</div><div class='add'>+		WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);</div><div class='add'>+	else</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);</div><div class='add'>+</div><div class='add'>+	if (ring</div><div class='add'>+	    &amp;&amp; amdgpu_sriov_is_pp_one_vf(adev)</div><div class='add'>+	    &amp;&amp; ((ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX)</div><div class='add'>+		|| (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE))) {</div><div class='add'>+		uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);</div><div class='add'>+		amdgpu_ring_emit_wreg(ring, reg, data);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = {</div><div class='add'>+	.is_rlc_enabled = gfx_v12_0_is_rlc_enabled,</div><div class='add'>+	.set_safe_mode = gfx_v12_0_set_safe_mode,</div><div class='add'>+	.unset_safe_mode = gfx_v12_0_unset_safe_mode,</div><div class='add'>+	.init = gfx_v12_0_rlc_init,</div><div class='add'>+	.get_csb_size = gfx_v12_0_get_csb_size,</div><div class='add'>+	.get_csb_buffer = gfx_v12_0_get_csb_buffer,</div><div class='add'>+	.resume = gfx_v12_0_rlc_resume,</div><div class='add'>+	.stop = gfx_v12_0_rlc_stop,</div><div class='add'>+	.reset = gfx_v12_0_rlc_reset,</div><div class='add'>+	.start = gfx_v12_0_rlc_start,</div><div class='add'>+	.update_spm_vmid = gfx_v12_0_update_spm_vmid,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#if 0</div><div class='add'>+static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	/* TODO */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	/* TODO */</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					   enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		amdgpu_gfx_off_ctrl(adev, enable);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,</div><div class='add'>+						       bool enable)</div><div class='add'>+{</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;cg_flags &amp;</div><div class='add'>+	      (AMD_CG_SUPPORT_GFX_CGCG |</div><div class='add'>+	      AMD_CG_SUPPORT_GFX_CGLS |</div><div class='add'>+	      AMD_CG_SUPPORT_GFX_3D_CGCG |</div><div class='add'>+	      AMD_CG_SUPPORT_GFX_3D_CGLS)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+</div><div class='add'>+		/* unset CGCG override */</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGCG)</div><div class='add'>+			data &amp;= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGLS)</div><div class='add'>+			data &amp;= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_3D_CGCG ||</div><div class='add'>+		    adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_3D_CGLS)</div><div class='add'>+			data &amp;= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;</div><div class='add'>+</div><div class='add'>+		/* update CGCG override bits */</div><div class='add'>+		if (def != data)</div><div class='add'>+			WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='add'>+</div><div class='add'>+		/* enable cgcg FSM(0x0000363F) */</div><div class='add'>+		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGCG) {</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;</div><div class='add'>+			data |= (0x36 &lt;&lt; RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |</div><div class='add'>+				 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGLS) {</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;</div><div class='add'>+			data |= (0x000F &lt;&lt; RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |</div><div class='add'>+				 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (def != data)</div><div class='add'>+			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);</div><div class='add'>+</div><div class='add'>+		/* Program RLC_CGCG_CGLS_CTRL_3D */</div><div class='add'>+		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_3D_CGCG) {</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;</div><div class='add'>+			data |= (0x36 &lt;&lt; RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |</div><div class='add'>+				 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_3D_CGLS) {</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;</div><div class='add'>+			data |= (0xf &lt;&lt; RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |</div><div class='add'>+				 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (def != data)</div><div class='add'>+			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);</div><div class='add'>+</div><div class='add'>+		/* set IDLE_POLL_COUNT(0x00900100) */</div><div class='add'>+		def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);</div><div class='add'>+</div><div class='add'>+		data &amp;= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);</div><div class='add'>+		data |= (0x0100 &lt;&lt; CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |</div><div class='add'>+			(0x0090 &lt;&lt; CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);</div><div class='add'>+</div><div class='add'>+		if (def != data)</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);</div><div class='add'>+</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);</div><div class='add'>+</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);</div><div class='add'>+		data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);</div><div class='add'>+</div><div class='add'>+		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */</div><div class='add'>+		if (adev-&gt;sdma.num_instances &gt; 1) {</div><div class='add'>+			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);</div><div class='add'>+			data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);</div><div class='add'>+			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* Program RLC_CGCG_CGLS_CTRL */</div><div class='add'>+		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGCG)</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGLS)</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;</div><div class='add'>+</div><div class='add'>+		if (def != data)</div><div class='add'>+			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);</div><div class='add'>+</div><div class='add'>+		/* Program RLC_CGCG_CGLS_CTRL_3D */</div><div class='add'>+		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_3D_CGCG)</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_3D_CGLS)</div><div class='add'>+			data &amp;= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;</div><div class='add'>+</div><div class='add'>+		if (def != data)</div><div class='add'>+			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,</div><div class='add'>+						       bool enable)</div><div class='add'>+{</div><div class='add'>+	uint32_t data, def;</div><div class='add'>+	if (!(adev-&gt;cg_flags &amp; (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* It is disabled by HW by default */</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_MGCG) {</div><div class='add'>+			/* 1 - RLC_CGTT_MGCG_OVERRIDE */</div><div class='add'>+			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+</div><div class='add'>+			data &amp;= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |</div><div class='add'>+				  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |</div><div class='add'>+				  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);</div><div class='add'>+</div><div class='add'>+			if (def != data)</div><div class='add'>+				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_MGCG) {</div><div class='add'>+			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+</div><div class='add'>+			data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |</div><div class='add'>+				 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |</div><div class='add'>+				 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);</div><div class='add'>+</div><div class='add'>+			if (def != data)</div><div class='add'>+				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,</div><div class='add'>+					   bool enable)</div><div class='add'>+{</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_REPEATER_FGCG))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		data &amp;= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |</div><div class='add'>+				  RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);</div><div class='add'>+	else</div><div class='add'>+		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |</div><div class='add'>+				RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;</div><div class='add'>+</div><div class='add'>+	if (def != data)</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,</div><div class='add'>+				       bool enable)</div><div class='add'>+{</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_FGCG))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		data &amp;= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;</div><div class='add'>+	else</div><div class='add'>+		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;</div><div class='add'>+</div><div class='add'>+	if (def != data)</div><div class='add'>+		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='add'>+					    bool enable)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_update_medium_grain_clock_gating(adev, enable);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_update_repeater_fgcg(adev, enable);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_update_sram_fgcg(adev, enable);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_update_perf_clk(adev, enable);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;cg_flags &amp;</div><div class='add'>+	    (AMD_CG_SUPPORT_GFX_MGCG |</div><div class='add'>+	     AMD_CG_SUPPORT_GFX_CGLS |</div><div class='add'>+	     AMD_CG_SUPPORT_GFX_CGCG |</div><div class='add'>+	     AMD_CG_SUPPORT_GFX_3D_CGCG |</div><div class='add'>+	     AMD_CG_SUPPORT_GFX_3D_CGLS))</div><div class='add'>+		gfx_v12_0_enable_gui_idle_interrupt(adev, enable);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					   enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		gfx_v12_0_update_gfx_clock_gating(adev,</div><div class='add'>+						  state == AMD_CG_STATE_GATE);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int data;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_MGCG */</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);</div><div class='add'>+	if (!(data &amp; RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_MGCG;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_REPEATER_FGCG */</div><div class='add'>+	if (!(data &amp; RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_REPEATER_FGCG;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_FGCG */</div><div class='add'>+	if (!(data &amp; RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_FGCG;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_PERF_CLK */</div><div class='add'>+	if (!(data &amp; RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_CGCG */</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);</div><div class='add'>+	if (data &amp; RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_CGCG;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_CGLS */</div><div class='add'>+	if (data &amp; RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_CGLS;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_3D_CGCG */</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);</div><div class='add'>+	if (data &amp; RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_GFX_3D_CGLS */</div><div class='add'>+	if (data &amp; RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* gfx12 is 32bit rptr*/</div><div class='add'>+	return *(uint32_t *)ring-&gt;rptr_cpu_addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u64 wptr;</div><div class='add'>+</div><div class='add'>+	/* XXX check if swapping is necessary on BE */</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		wptr = atomic64_read((atomic64_t *)ring-&gt;wptr_cpu_addr);</div><div class='add'>+	} else {</div><div class='add'>+		wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);</div><div class='add'>+		wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) &lt;&lt; 32;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return wptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		/* XXX check if swapping is necessary on BE */</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='add'>+			     ring-&gt;wptr);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_RB0_WPTR,</div><div class='add'>+			     lower_32_bits(ring-&gt;wptr));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,</div><div class='add'>+			     upper_32_bits(ring-&gt;wptr));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* gfx12 hardware is 32bit rptr */</div><div class='add'>+	return *(uint32_t *)ring-&gt;rptr_cpu_addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u64 wptr;</div><div class='add'>+</div><div class='add'>+	/* XXX check if swapping is necessary on BE */</div><div class='add'>+	if (ring-&gt;use_doorbell)</div><div class='add'>+		wptr = atomic64_read((atomic64_t *)ring-&gt;wptr_cpu_addr);</div><div class='add'>+	else</div><div class='add'>+		BUG();</div><div class='add'>+	return wptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* XXX check if swapping is necessary on BE */</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='add'>+			     ring-&gt;wptr);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='add'>+	} else {</div><div class='add'>+		BUG(); /* only DOORBELL method supported on gfx12 now */</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 ref_and_mask, reg_mem_engine;</div><div class='add'>+	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev-&gt;nbio.hdp_flush_reg;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='add'>+		switch (ring-&gt;me) {</div><div class='add'>+		case 1:</div><div class='add'>+			ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp2 &lt;&lt; ring-&gt;pipe;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp6 &lt;&lt; ring-&gt;pipe;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+		reg_mem_engine = 0;</div><div class='add'>+	} else {</div><div class='add'>+		ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_cp0;</div><div class='add'>+		reg_mem_engine = 1; /* pfp */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,</div><div class='add'>+			       adev-&gt;nbio.funcs-&gt;get_hdp_flush_req_offset(adev),</div><div class='add'>+			       adev-&gt;nbio.funcs-&gt;get_hdp_flush_done_offset(adev),</div><div class='add'>+			       ref_and_mask, ref_and_mask, 0x20);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,</div><div class='add'>+				       struct amdgpu_job *job,</div><div class='add'>+				       struct amdgpu_ib *ib,</div><div class='add'>+				       uint32_t flags)</div><div class='add'>+{</div><div class='add'>+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='add'>+	u32 header, control = 0;</div><div class='add'>+</div><div class='add'>+	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);</div><div class='add'>+</div><div class='add'>+	control |= ib-&gt;length_dw | (vmid &lt;&lt; 24);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, header);</div><div class='add'>+	BUG_ON(ib-&gt;gpu_addr &amp; 0x3); /* Dword align */</div><div class='add'>+	amdgpu_ring_write(ring,</div><div class='add'>+#ifdef __BIG_ENDIAN</div><div class='add'>+		(2 &lt;&lt; 0) |</div><div class='add'>+#endif</div><div class='add'>+		lower_32_bits(ib-&gt;gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(ib-&gt;gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, control);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,</div><div class='add'>+					   struct amdgpu_job *job,</div><div class='add'>+					   struct amdgpu_ib *ib,</div><div class='add'>+					   uint32_t flags)</div><div class='add'>+{</div><div class='add'>+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='add'>+	u32 control = INDIRECT_BUFFER_VALID | ib-&gt;length_dw | (vmid &lt;&lt; 24);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));</div><div class='add'>+	BUG_ON(ib-&gt;gpu_addr &amp; 0x3); /* Dword align */</div><div class='add'>+	amdgpu_ring_write(ring,</div><div class='add'>+#ifdef __BIG_ENDIAN</div><div class='add'>+				(2 &lt;&lt; 0) |</div><div class='add'>+#endif</div><div class='add'>+				lower_32_bits(ib-&gt;gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(ib-&gt;gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, control);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,</div><div class='add'>+				     u64 seq, unsigned flags)</div><div class='add'>+{</div><div class='add'>+	bool write64bit = flags &amp; AMDGPU_FENCE_FLAG_64BIT;</div><div class='add'>+	bool int_sel = flags &amp; AMDGPU_FENCE_FLAG_INT;</div><div class='add'>+</div><div class='add'>+	/* RELEASE_MEM - flush caches, send int */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));</div><div class='add'>+	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |</div><div class='add'>+				 PACKET3_RELEASE_MEM_GCR_GL2_WB |</div><div class='add'>+				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |</div><div class='add'>+				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |</div><div class='add'>+				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));</div><div class='add'>+	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |</div><div class='add'>+				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * the address should be Qword aligned if 64bit write, Dword</div><div class='add'>+	 * aligned if only send 32bit data low (discard data high)</div><div class='add'>+	 */</div><div class='add'>+	if (write64bit)</div><div class='add'>+		BUG_ON(addr &amp; 0x7);</div><div class='add'>+	else</div><div class='add'>+		BUG_ON(addr &amp; 0x3);</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(seq));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(seq));</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	int usepfp = (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX);</div><div class='add'>+	uint32_t seq = ring-&gt;fence_drv.sync_seq;</div><div class='add'>+	uint64_t addr = ring-&gt;fence_drv.gpu_addr;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),</div><div class='add'>+			       upper_32_bits(addr), seq, 0xffffffff, 4);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,</div><div class='add'>+				   uint16_t pasid, uint32_t flush_type,</div><div class='add'>+				   bool all_hub, uint8_t dst_sel)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));</div><div class='add'>+	amdgpu_ring_write(ring,</div><div class='add'>+			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |</div><div class='add'>+			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |</div><div class='add'>+			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |</div><div class='add'>+			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='add'>+					 unsigned vmid, uint64_t pd_addr)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='add'>+</div><div class='add'>+	/* compute doesn't have PFP */</div><div class='add'>+	if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX) {</div><div class='add'>+		/* sync PFP to ME, otherwise we might get invalid PFP reads */</div><div class='add'>+		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));</div><div class='add'>+		amdgpu_ring_write(ring, 0x0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,</div><div class='add'>+					  u64 seq, unsigned int flags)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* we only allocate 32bit for each seq wb address */</div><div class='add'>+	BUG_ON(flags &amp; AMDGPU_FENCE_FLAG_64BIT);</div><div class='add'>+</div><div class='add'>+	/* write fence seq to the "addr" */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));</div><div class='add'>+	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |</div><div class='add'>+				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(seq));</div><div class='add'>+</div><div class='add'>+	if (flags &amp; AMDGPU_FENCE_FLAG_INT) {</div><div class='add'>+		/* set register to trigger INT */</div><div class='add'>+		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));</div><div class='add'>+		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |</div><div class='add'>+					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));</div><div class='add'>+		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));</div><div class='add'>+		amdgpu_ring_write(ring, 0);</div><div class='add'>+		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,</div><div class='add'>+					 uint32_t flags)</div><div class='add'>+{</div><div class='add'>+	uint32_t dw2 = 0;</div><div class='add'>+</div><div class='add'>+	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */</div><div class='add'>+	if (flags &amp; AMDGPU_HAVE_CTX_SWITCH) {</div><div class='add'>+		/* set load_global_config &amp; load_global_uconfig */</div><div class='add'>+		dw2 |= 0x8001;</div><div class='add'>+		/* set load_cs_sh_regs */</div><div class='add'>+		dw2 |= 0x01000000;</div><div class='add'>+		/* set load_per_context_state &amp; load_gfx_sh_regs for GFX */</div><div class='add'>+		dw2 |= 0x10002;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='add'>+	amdgpu_ring_write(ring, dw2);</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,</div><div class='add'>+						   uint64_t addr)</div><div class='add'>+{</div><div class='add'>+	unsigned ret;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='add'>+	/* discard following DWs if *cond_exec_gpu_addr==0 */</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+	ret = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='add'>+	/* patch dummy value later */</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	int i, r = 0;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;unmap_queues_size)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* assert preemption condition */</div><div class='add'>+	amdgpu_ring_set_preempt_cond_exec(ring, false);</div><div class='add'>+</div><div class='add'>+	/* assert IB preemption, emit the trailing fence */</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,</div><div class='add'>+				   ring-&gt;trail_fence_gpu_addr,</div><div class='add'>+				   ++ring-&gt;trail_seq);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	/* poll the trailing fence */</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (ring-&gt;trail_seq ==</div><div class='add'>+		    le32_to_cpu(*(ring-&gt;trail_fence_cpu_addr)))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		DRM_ERROR("ring %d failed to preempt ib\n", ring-&gt;idx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* deassert preemption condition */</div><div class='add'>+	amdgpu_ring_set_preempt_cond_exec(ring, true);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring,</div><div class='add'>+					   bool start,</div><div class='add'>+					   bool secure)</div><div class='add'>+{</div><div class='add'>+	uint32_t v = secure ? FRAME_TMZ : 0;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));</div><div class='add'>+	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+				     uint32_t reg_val_offs)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));</div><div class='add'>+	amdgpu_ring_write(ring, 0 |	/* src: register*/</div><div class='add'>+				(5 &lt;&lt; 8) |	/* dst: memory */</div><div class='add'>+				(1 &lt;&lt; 20));	/* write confirm */</div><div class='add'>+	amdgpu_ring_write(ring, reg);</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(adev-&gt;wb.gpu_addr +</div><div class='add'>+				reg_val_offs * 4));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(adev-&gt;wb.gpu_addr +</div><div class='add'>+				reg_val_offs * 4));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='add'>+				     uint32_t reg,</div><div class='add'>+				     uint32_t val)</div><div class='add'>+{</div><div class='add'>+	uint32_t cmd = 0;</div><div class='add'>+</div><div class='add'>+	switch (ring-&gt;funcs-&gt;type) {</div><div class='add'>+	case AMDGPU_RING_TYPE_GFX:</div><div class='add'>+		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_RING_TYPE_KIQ:</div><div class='add'>+		cmd = (1 &lt;&lt; 16); /* no inc addr */</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cmd = WR_CONFIRM;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));</div><div class='add'>+	amdgpu_ring_write(ring, cmd);</div><div class='add'>+	amdgpu_ring_write(ring, reg);</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+	amdgpu_ring_write(ring, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+					uint32_t val, uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='add'>+						   uint32_t reg0, uint32_t reg1,</div><div class='add'>+						   uint32_t ref, uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	int usepfp = (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX);</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,</div><div class='add'>+			       ref, mask, 0x20);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+				      uint32_t me, uint32_t pipe,</div><div class='add'>+				      enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	uint32_t cp_int_cntl, cp_int_cntl_reg;</div><div class='add'>+</div><div class='add'>+	if (!me) {</div><div class='add'>+		switch (pipe) {</div><div class='add'>+		case 0:</div><div class='add'>+			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			DRM_DEBUG("invalid pipe %d\n", pipe);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		DRM_DEBUG("invalid me %d\n", me);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+					    TIME_STAMP_INT_ENABLE, 0);</div><div class='add'>+		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+					    GENERIC0_INT_ENABLE, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+					    TIME_STAMP_INT_ENABLE, 1);</div><div class='add'>+		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+					    GENERIC0_INT_ENABLE, 1);</div><div class='add'>+		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+						     int me, int pipe,</div><div class='add'>+						     enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 mec_int_cntl, mec_int_cntl_reg;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * amdgpu controls only the first MEC. That's why this function only</div><div class='add'>+	 * handles the setting of interrupts for this specific MEC. All other</div><div class='add'>+	 * pipes' interrupts are set by amdkfd.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (me == 1) {</div><div class='add'>+		switch (pipe) {</div><div class='add'>+		case 0:</div><div class='add'>+			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			DRM_DEBUG("invalid pipe %d\n", pipe);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		DRM_DEBUG("invalid me %d\n", me);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);</div><div class='add'>+		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+					     TIME_STAMP_INT_ENABLE, 0);</div><div class='add'>+		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+					     GENERIC0_INT_ENABLE, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);</div><div class='add'>+		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+					     TIME_STAMP_INT_ENABLE, 1);</div><div class='add'>+		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+					     GENERIC0_INT_ENABLE, 1);</div><div class='add'>+		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					    struct amdgpu_irq_src *src,</div><div class='add'>+					    unsigned type,</div><div class='add'>+					    enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:</div><div class='add'>+		gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:</div><div class='add'>+		gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:</div><div class='add'>+		gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:</div><div class='add'>+		gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:</div><div class='add'>+		gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:</div><div class='add'>+		gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,</div><div class='add'>+			     struct amdgpu_irq_src *source,</div><div class='add'>+			     struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 doorbell_offset = entry-&gt;src_data[0];</div><div class='add'>+	u8 me_id, pipe_id, queue_id;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG("IH: CP EOP\n");</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; doorbell_offset) {</div><div class='add'>+		struct amdgpu_userq_fence_driver *fence_drv = NULL;</div><div class='add'>+		struct xarray *xa = &amp;adev-&gt;userq_xa;</div><div class='add'>+		unsigned long flags;</div><div class='add'>+</div><div class='add'>+		xa_lock_irqsave(xa, flags);</div><div class='add'>+		fence_drv = xa_load(xa, doorbell_offset);</div><div class='add'>+		if (fence_drv)</div><div class='add'>+			amdgpu_userq_fence_driver_process(fence_drv);</div><div class='add'>+		xa_unlock_irqrestore(xa, flags);</div><div class='add'>+	} else {</div><div class='add'>+		me_id = (entry-&gt;ring_id &amp; 0x0c) &gt;&gt; 2;</div><div class='add'>+		pipe_id = (entry-&gt;ring_id &amp; 0x03) &gt;&gt; 0;</div><div class='add'>+		queue_id = (entry-&gt;ring_id &amp; 0x70) &gt;&gt; 4;</div><div class='add'>+</div><div class='add'>+		switch (me_id) {</div><div class='add'>+		case 0:</div><div class='add'>+			if (pipe_id == 0)</div><div class='add'>+				amdgpu_fence_process(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+			else</div><div class='add'>+				amdgpu_fence_process(&amp;adev-&gt;gfx.gfx_ring[1]);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+		case 2:</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+				ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+				/* Per-queue interrupt is supported for MEC starting from VI.</div><div class='add'>+				 * The interrupt can only be enabled/disabled per pipe instead</div><div class='add'>+				 * of per queue.</div><div class='add'>+				 */</div><div class='add'>+				if ((ring-&gt;me == me_id) &amp;&amp;</div><div class='add'>+				    (ring-&gt;pipe == pipe_id) &amp;&amp;</div><div class='add'>+				    (ring-&gt;queue == queue_id))</div><div class='add'>+					amdgpu_fence_process(ring);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					      struct amdgpu_irq_src *source,</div><div class='add'>+					      unsigned int type,</div><div class='add'>+					      enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					    struct amdgpu_irq_src *source,</div><div class='add'>+					    unsigned type,</div><div class='add'>+					    enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					       struct amdgpu_irq_src *source,</div><div class='add'>+					       unsigned int type,</div><div class='add'>+					       enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+				cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,</div><div class='add'>+								    PRIV_INSTR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u8 me_id, pipe_id, queue_id;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	me_id = (entry-&gt;ring_id &amp; 0x0c) &gt;&gt; 2;</div><div class='add'>+	pipe_id = (entry-&gt;ring_id &amp; 0x03) &gt;&gt; 0;</div><div class='add'>+	queue_id = (entry-&gt;ring_id &amp; 0x70) &gt;&gt; 4;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.disable_kq) {</div><div class='add'>+		switch (me_id) {</div><div class='add'>+		case 0:</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++) {</div><div class='add'>+				ring = &amp;adev-&gt;gfx.gfx_ring[i];</div><div class='add'>+				if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id &amp;&amp;</div><div class='add'>+				    ring-&gt;queue == queue_id)</div><div class='add'>+					drm_sched_fault(&amp;ring-&gt;sched);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+		case 2:</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='add'>+				ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='add'>+				if (ring-&gt;me == me_id &amp;&amp; ring-&gt;pipe == pipe_id &amp;&amp;</div><div class='add'>+				    ring-&gt;queue == queue_id)</div><div class='add'>+					drm_sched_fault(&amp;ring-&gt;sched);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			BUG();</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,</div><div class='add'>+				  struct amdgpu_irq_src *source,</div><div class='add'>+				  struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal register access in command stream\n");</div><div class='add'>+	gfx_v12_0_handle_priv_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_irq_src *source,</div><div class='add'>+				struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal opcode in command stream \n");</div><div class='add'>+	gfx_v12_0_handle_priv_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,</div><div class='add'>+				   struct amdgpu_irq_src *source,</div><div class='add'>+				   struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal instruction in command stream\n");</div><div class='add'>+	gfx_v12_0_handle_priv_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	const unsigned int gcr_cntl =</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |</div><div class='add'>+			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);</div><div class='add'>+</div><div class='add'>+	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));</div><div class='add'>+	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */</div><div class='add'>+	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */</div><div class='add'>+	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */</div><div class='add'>+	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */</div><div class='add'>+	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */</div><div class='add'>+	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */</div><div class='add'>+	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)</div><div class='add'>+{</div><div class='add'>+	/* Header itself is a NOP packet */</div><div class='add'>+	if (num_nop == 1) {</div><div class='add'>+		amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));</div><div class='add'>+</div><div class='add'>+	/* Header is at index 0, followed by num_nops - 1 NOP packet's */</div><div class='add'>+	amdgpu_ring_insert_nop(ring, num_nop - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* Emit the cleaner shader */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));</div><div class='add'>+	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+			   gc_reg_list_12_0[i].reg_name,</div><div class='add'>+			   adev-&gt;gfx.ip_dump_core[i]);</div><div class='add'>+</div><div class='add'>+	/* print compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_12);</div><div class='add'>+	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.mec.num_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_pipe_per_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+						   gc_cp_reg_list_12[reg].reg_name,</div><div class='add'>+						   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* print gfx queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_gfx_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	index = 0;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);</div><div class='add'>+	drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.me.num_me,</div><div class='add'>+		   adev-&gt;gfx.me.num_pipe_per_me,</div><div class='add'>+		   adev-&gt;gfx.me.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.me.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+						   gc_gfx_queue_reg_list_12[reg].reg_name,</div><div class='add'>+						   adev-&gt;gfx.ip_dump_gfx_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		adev-&gt;gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_12);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				/* ME0 is for GFX so start from 1 for CP */</div><div class='add'>+				soc24_grbm_select(adev, adev-&gt;gfx.me.num_me + i, j, k, 0);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+						RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+							gc_cp_reg_list_12[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump gfx queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_gfx_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	index = 0;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.me.num_me; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.me.num_pipe_per_me; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.me.num_queue_per_pipe; k++) {</div><div class='add'>+				soc24_grbm_select(adev, i, j, k, 0);</div><div class='add'>+</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					adev-&gt;gfx.ip_dump_gfx_queues[index + reg] =</div><div class='add'>+						RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+							gc_gfx_queue_reg_list_12[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool gfx_v12_pipe_reset_support(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* Disable the pipe reset until the CPFW fully support it.*/</div><div class='add'>+	dev_warn_once(adev-&gt;dev, "The CPFW hasn't support pipe reset yet.\n");</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_reset_gfx_pipe(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t reset_pipe = 0, clean_pipe = 0;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!gfx_v12_pipe_reset_support(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_set_safe_mode(adev, 0);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc24_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+</div><div class='add'>+	switch (ring-&gt;pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE0_RESET, 1);</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE0_RESET, 1);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE0_RESET, 0);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE0_RESET, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE1_RESET, 1);</div><div class='add'>+		reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE1_RESET, 1);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   PFP_PIPE1_RESET, 0);</div><div class='add'>+		clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,</div><div class='add'>+					   ME_PIPE1_RESET, 0);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);</div><div class='add'>+</div><div class='add'>+	r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) &lt;&lt; 2) -</div><div class='add'>+					RS64_FW_UC_START_ADDR_LO;</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v12_0_unset_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "The ring %s pipe reset: %s\n", ring-&gt;name,</div><div class='add'>+			r == 0 ? "successfully" : "failed");</div><div class='add'>+	/* Sometimes the ME start pc counter can't cache correctly, so the</div><div class='add'>+	 * PC check only as a reference and pipe reset result rely on the</div><div class='add'>+	 * later ring test.</div><div class='add'>+	 */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_reset_legacy_queue(ring-&gt;adev, ring, vmid, false);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "reset via MES failed and try pipe reset %d\n", r);</div><div class='add'>+		r = gfx_v12_reset_gfx_pipe(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_kgq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to init kgq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_map_legacy_queue(adev, ring);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to remap kgq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t reset_pipe = 0, clean_pipe = 0;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!gfx_v12_pipe_reset_support(adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	gfx_v12_0_set_safe_mode(adev, 0);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc24_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0);</div><div class='add'>+</div><div class='add'>+	reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);</div><div class='add'>+	clean_pipe = reset_pipe;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.rs64_enable) {</div><div class='add'>+		switch (ring-&gt;pipe) {</div><div class='add'>+		case 0:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE0_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE0_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE1_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE1_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE2_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE2_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE3_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,</div><div class='add'>+						   MEC_PIPE3_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);</div><div class='add'>+		r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) &lt;&lt; 2) -</div><div class='add'>+				RS64_FW_UC_START_ADDR_LO;</div><div class='add'>+	} else {</div><div class='add'>+		switch (ring-&gt;pipe) {</div><div class='add'>+		case 0:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE0_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE0_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE1_RESET, 1);</div><div class='add'>+			clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,</div><div class='add'>+							   MEC_ME1_PIPE1_RESET, 0);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+		break;</div><div class='add'>+		}</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);</div><div class='add'>+		/* Doesn't find the F32 MEC instruction pointer register, and suppose</div><div class='add'>+		 * the driver won't run into the F32 mode.</div><div class='add'>+		 */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	soc24_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v12_0_unset_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "The ring %s pipe resets: %s\n", ring-&gt;name,</div><div class='add'>+			r == 0 ? "successfully" : "failed");</div><div class='add'>+	/* Need the ring test to verify the pipe reset result.*/</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_reset_legacy_queue(ring-&gt;adev, ring, vmid, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "fail(%d) to reset kcq  and try pipe reset\n", r);</div><div class='add'>+		r = gfx_v12_0_reset_compute_pipe(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v12_0_kcq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to init kcq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	r = amdgpu_mes_map_legacy_queue(adev, ring);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to remap kcq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_profile_ring_begin_use(ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gfx_profile_ring_end_use(ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_end_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {</div><div class='add'>+	.name = "gfx_v12_0",</div><div class='add'>+	.early_init = gfx_v12_0_early_init,</div><div class='add'>+	.late_init = gfx_v12_0_late_init,</div><div class='add'>+	.sw_init = gfx_v12_0_sw_init,</div><div class='add'>+	.sw_fini = gfx_v12_0_sw_fini,</div><div class='add'>+	.hw_init = gfx_v12_0_hw_init,</div><div class='add'>+	.hw_fini = gfx_v12_0_hw_fini,</div><div class='add'>+	.suspend = gfx_v12_0_suspend,</div><div class='add'>+	.resume = gfx_v12_0_resume,</div><div class='add'>+	.is_idle = gfx_v12_0_is_idle,</div><div class='add'>+	.wait_for_idle = gfx_v12_0_wait_for_idle,</div><div class='add'>+	.set_clockgating_state = gfx_v12_0_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = gfx_v12_0_set_powergating_state,</div><div class='add'>+	.get_clockgating_state = gfx_v12_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = gfx_v12_ip_dump,</div><div class='add'>+	.print_ip_state = gfx_v12_ip_print,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_GFX,</div><div class='add'>+	.align_mask = 0xff,</div><div class='add'>+	.nop = PACKET3(PACKET3_NOP, 0x3FFF),</div><div class='add'>+	.support_64bit_ptrs = true,</div><div class='add'>+	.secure_submission_supported = true,</div><div class='add'>+	.get_rptr = gfx_v12_0_ring_get_rptr_gfx,</div><div class='add'>+	.get_wptr = gfx_v12_0_ring_get_wptr_gfx,</div><div class='add'>+	.set_wptr = gfx_v12_0_ring_set_wptr_gfx,</div><div class='add'>+	.emit_frame_size = /* totally 242 maximum if 16 IBs */</div><div class='add'>+		5 + /* COND_EXEC */</div><div class='add'>+		7 + /* PIPELINE_SYNC */</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='add'>+		2 + /* VM_FLUSH */</div><div class='add'>+		8 + /* FENCE for VM_FLUSH */</div><div class='add'>+		5 + /* COND_EXEC */</div><div class='add'>+		7 + /* HDP_flush */</div><div class='add'>+		4 + /* VGT_flush */</div><div class='add'>+		31 + /*	DE_META */</div><div class='add'>+		3 + /* CNTX_CTRL */</div><div class='add'>+		5 + /* HDP_INVL */</div><div class='add'>+		8 + 8 + /* FENCE x2 */</div><div class='add'>+		8 + /* gfx_v12_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v12_0_ring_emit_cleaner_shader */</div><div class='add'>+	.emit_ib_size =	4, /* gfx_v12_0_ring_emit_ib_gfx */</div><div class='add'>+	.emit_ib = gfx_v12_0_ring_emit_ib_gfx,</div><div class='add'>+	.emit_fence = gfx_v12_0_ring_emit_fence,</div><div class='add'>+	.emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,</div><div class='add'>+	.emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,</div><div class='add'>+	.test_ring = gfx_v12_0_ring_test_ring,</div><div class='add'>+	.test_ib = gfx_v12_0_ring_test_ib,</div><div class='add'>+	.insert_nop = gfx_v12_ring_insert_nop,</div><div class='add'>+	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='add'>+	.emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,</div><div class='add'>+	.init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,</div><div class='add'>+	.preempt_ib = gfx_v12_0_ring_preempt_ib,</div><div class='add'>+	.emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl,</div><div class='add'>+	.emit_wreg = gfx_v12_0_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,</div><div class='add'>+	.emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_mem_sync = gfx_v12_0_emit_mem_sync,</div><div class='add'>+	.reset = gfx_v12_0_reset_kgq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v12_0_ring_begin_use,</div><div class='add'>+	.end_use = gfx_v12_0_ring_end_use,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_COMPUTE,</div><div class='add'>+	.align_mask = 0xff,</div><div class='add'>+	.nop = PACKET3(PACKET3_NOP, 0x3FFF),</div><div class='add'>+	.support_64bit_ptrs = true,</div><div class='add'>+	.get_rptr = gfx_v12_0_ring_get_rptr_compute,</div><div class='add'>+	.get_wptr = gfx_v12_0_ring_get_wptr_compute,</div><div class='add'>+	.set_wptr = gfx_v12_0_ring_set_wptr_compute,</div><div class='add'>+	.emit_frame_size =</div><div class='add'>+		7 + /* gfx_v12_0_ring_emit_hdp_flush */</div><div class='add'>+		5 + /* hdp invalidate */</div><div class='add'>+		7 + /* gfx_v12_0_ring_emit_pipeline_sync */</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='add'>+		2 + /* gfx_v12_0_ring_emit_vm_flush */</div><div class='add'>+		8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */</div><div class='add'>+		8 + /* gfx_v12_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v12_0_ring_emit_cleaner_shader */</div><div class='add'>+	.emit_ib_size =	7, /* gfx_v12_0_ring_emit_ib_compute */</div><div class='add'>+	.emit_ib = gfx_v12_0_ring_emit_ib_compute,</div><div class='add'>+	.emit_fence = gfx_v12_0_ring_emit_fence,</div><div class='add'>+	.emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,</div><div class='add'>+	.emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,</div><div class='add'>+	.test_ring = gfx_v12_0_ring_test_ring,</div><div class='add'>+	.test_ib = gfx_v12_0_ring_test_ib,</div><div class='add'>+	.insert_nop = gfx_v12_ring_insert_nop,</div><div class='add'>+	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='add'>+	.emit_wreg = gfx_v12_0_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,</div><div class='add'>+	.emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_mem_sync = gfx_v12_0_emit_mem_sync,</div><div class='add'>+	.reset = gfx_v12_0_reset_kcq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v12_0_ring_begin_use,</div><div class='add'>+	.end_use = gfx_v12_0_ring_end_use,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_KIQ,</div><div class='add'>+	.align_mask = 0xff,</div><div class='add'>+	.nop = PACKET3(PACKET3_NOP, 0x3FFF),</div><div class='add'>+	.support_64bit_ptrs = true,</div><div class='add'>+	.get_rptr = gfx_v12_0_ring_get_rptr_compute,</div><div class='add'>+	.get_wptr = gfx_v12_0_ring_get_wptr_compute,</div><div class='add'>+	.set_wptr = gfx_v12_0_ring_set_wptr_compute,</div><div class='add'>+	.emit_frame_size =</div><div class='add'>+		7 + /* gfx_v12_0_ring_emit_hdp_flush */</div><div class='add'>+		5 + /*hdp invalidate */</div><div class='add'>+		7 + /* gfx_v12_0_ring_emit_pipeline_sync */</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='add'>+		2 + /* gfx_v12_0_ring_emit_vm_flush */</div><div class='add'>+		8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */</div><div class='add'>+	.emit_ib_size =	7, /* gfx_v12_0_ring_emit_ib_compute */</div><div class='add'>+	.emit_ib = gfx_v12_0_ring_emit_ib_compute,</div><div class='add'>+	.emit_fence = gfx_v12_0_ring_emit_fence_kiq,</div><div class='add'>+	.test_ring = gfx_v12_0_ring_test_ring,</div><div class='add'>+	.test_ib = gfx_v12_0_ring_test_ib,</div><div class='add'>+	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='add'>+	.emit_rreg = gfx_v12_0_ring_emit_rreg,</div><div class='add'>+	.emit_wreg = gfx_v12_0_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,</div><div class='add'>+	.emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.kiq[0].ring.funcs = &amp;gfx_v12_0_ring_funcs_kiq;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='add'>+		adev-&gt;gfx.gfx_ring[i].funcs = &amp;gfx_v12_0_ring_funcs_gfx;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++)</div><div class='add'>+		adev-&gt;gfx.compute_ring[i].funcs = &amp;gfx_v12_0_ring_funcs_compute;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = {</div><div class='add'>+	.set = gfx_v12_0_set_eop_interrupt_state,</div><div class='add'>+	.process = gfx_v12_0_eop_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {</div><div class='add'>+	.set = gfx_v12_0_set_priv_reg_fault_state,</div><div class='add'>+	.process = gfx_v12_0_priv_reg_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {</div><div class='add'>+	.set = gfx_v12_0_set_bad_op_fault_state,</div><div class='add'>+	.process = gfx_v12_0_bad_op_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {</div><div class='add'>+	.set = gfx_v12_0_set_priv_inst_fault_state,</div><div class='add'>+	.process = gfx_v12_0_priv_inst_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;</div><div class='add'>+	adev-&gt;gfx.eop_irq.funcs = &amp;gfx_v12_0_eop_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.priv_reg_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.priv_reg_irq.funcs = &amp;gfx_v12_0_priv_reg_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.bad_op_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.bad_op_irq.funcs = &amp;gfx_v12_0_bad_op_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.priv_inst_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.priv_inst_irq.funcs = &amp;gfx_v12_0_priv_inst_irq_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+		adev-&gt;gfx.imu.mode = MISSION_MODE;</div><div class='add'>+	else</div><div class='add'>+		adev-&gt;gfx.imu.mode = DEBUG_MODE;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfx.imu.funcs = &amp;gfx_v12_0_imu_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gfx.rlc.funcs = &amp;gfx_v12_0_rlc_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* set gfx eng mqd */</div><div class='add'>+	adev-&gt;mqds[AMDGPU_HW_IP_GFX].mqd_size =</div><div class='add'>+		sizeof(struct v12_gfx_mqd);</div><div class='add'>+	adev-&gt;mqds[AMDGPU_HW_IP_GFX].init_mqd =</div><div class='add'>+		gfx_v12_0_gfx_mqd_init;</div><div class='add'>+	/* set compute eng mqd */</div><div class='add'>+	adev-&gt;mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =</div><div class='add'>+		sizeof(struct v12_compute_mqd);</div><div class='add'>+	adev-&gt;mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =</div><div class='add'>+		gfx_v12_0_compute_mqd_init;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,</div><div class='add'>+							  u32 bitmap)</div><div class='add'>+{</div><div class='add'>+	u32 data;</div><div class='add'>+</div><div class='add'>+	if (!bitmap)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	data = bitmap &lt;&lt; GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;</div><div class='add'>+	data &amp;= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 data, wgp_bitmask;</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);</div><div class='add'>+	data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);</div><div class='add'>+</div><div class='add'>+	data &amp;= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;</div><div class='add'>+	data &gt;&gt;= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;</div><div class='add'>+</div><div class='add'>+	wgp_bitmask =</div><div class='add'>+		amdgpu_gfx_create_bitmask(adev-&gt;gfx.config.max_cu_per_sh &gt;&gt; 1);</div><div class='add'>+</div><div class='add'>+	return (~data) &amp; wgp_bitmask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 wgp_idx, wgp_active_bitmap;</div><div class='add'>+	u32 cu_bitmap_per_wgp, cu_active_bitmap;</div><div class='add'>+</div><div class='add'>+	wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev);</div><div class='add'>+	cu_active_bitmap = 0;</div><div class='add'>+</div><div class='add'>+	for (wgp_idx = 0; wgp_idx &lt; 16; wgp_idx++) {</div><div class='add'>+		/* if there is one WGP enabled, it means 2 CUs will be enabled */</div><div class='add'>+		cu_bitmap_per_wgp = 3 &lt;&lt; (2 * wgp_idx);</div><div class='add'>+		if (wgp_active_bitmap &amp; (1 &lt;&lt; wgp_idx))</div><div class='add'>+			cu_active_bitmap |= cu_bitmap_per_wgp;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return cu_active_bitmap;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_cu_info *cu_info)</div><div class='add'>+{</div><div class='add'>+	int i, j, k, counter, active_cu_number = 0;</div><div class='add'>+	u32 mask, bitmap;</div><div class='add'>+	unsigned disable_masks[8 * 2];</div><div class='add'>+</div><div class='add'>+	if (!adev || !cu_info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.config.max_shader_engines; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.config.max_sh_per_se; j++) {</div><div class='add'>+			bitmap = i * adev-&gt;gfx.config.max_sh_per_se + j;</div><div class='add'>+			if (!((gfx_v12_0_get_sa_active_bitmap(adev) &gt;&gt; bitmap) &amp; 1))</div><div class='add'>+				continue;</div><div class='add'>+			mask = 1;</div><div class='add'>+			counter = 0;</div><div class='add'>+			gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);</div><div class='add'>+			if (i &lt; 8 &amp;&amp; j &lt; 2)</div><div class='add'>+				gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(</div><div class='add'>+					adev, disable_masks[i * 2 + j]);</div><div class='add'>+			bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev);</div><div class='add'>+</div><div class='add'>+			/**</div><div class='add'>+			 * GFX12 could support more than 4 SEs, while the bitmap</div><div class='add'>+			 * in cu_info struct is 4x4 and ioctl interface struct</div><div class='add'>+			 * drm_amdgpu_info_device should keep stable.</div><div class='add'>+			 * So we use last two columns of bitmap to store cu mask for</div><div class='add'>+			 * SEs 4 to 7, the layout of the bitmap is as below:</div><div class='add'>+			 *    SE0: {SH0,SH1} --&gt; {bitmap[0][0], bitmap[0][1]}</div><div class='add'>+			 *    SE1: {SH0,SH1} --&gt; {bitmap[1][0], bitmap[1][1]}</div><div class='add'>+			 *    SE2: {SH0,SH1} --&gt; {bitmap[2][0], bitmap[2][1]}</div><div class='add'>+			 *    SE3: {SH0,SH1} --&gt; {bitmap[3][0], bitmap[3][1]}</div><div class='add'>+			 *    SE4: {SH0,SH1} --&gt; {bitmap[0][2], bitmap[0][3]}</div><div class='add'>+			 *    SE5: {SH0,SH1} --&gt; {bitmap[1][2], bitmap[1][3]}</div><div class='add'>+			 *    SE6: {SH0,SH1} --&gt; {bitmap[2][2], bitmap[2][3]}</div><div class='add'>+			 *    SE7: {SH0,SH1} --&gt; {bitmap[3][2], bitmap[3][3]}</div><div class='add'>+			 */</div><div class='add'>+			cu_info-&gt;bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;</div><div class='add'>+</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.config.max_cu_per_sh; k++) {</div><div class='add'>+				if (bitmap &amp; mask)</div><div class='add'>+					counter++;</div><div class='add'>+</div><div class='add'>+				mask &lt;&lt;= 1;</div><div class='add'>+			}</div><div class='add'>+			active_cu_number += counter;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='add'>+</div><div class='add'>+	cu_info-&gt;number = active_cu_number;</div><div class='add'>+	cu_info-&gt;simd_per_cu = NUM_SIMD_PER_CU;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version gfx_v12_0_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_GFX,</div><div class='add'>+	.major = 12,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;gfx_v12_0_ip_funcs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.h<br/>index 0d878ca3acba..f7184b2dc4e8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/dce_v11_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v12_0.h</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2014 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2023 dvanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'>  * copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -21,12 +21,11 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#ifndef __DCE_V11_0_H__</div><div class='del'>-#define __DCE_V11_0_H__</div><div class='add'>+#ifndef __GFX_V12_0_H__</div><div class='add'>+#define __GFX_V12_0_H__</div><div class='ctx'> </div><div class='del'>-extern const struct amdgpu_ip_block_version dce_v11_0_ip_block;</div><div class='del'>-extern const struct amdgpu_ip_block_version dce_v11_2_ip_block;</div><div class='del'>-</div><div class='del'>-void dce_v11_0_disable_dce(struct amdgpu_device *adev);</div><div class='add'>+extern const struct amdgpu_ip_block_version gfx_v12_0_ip_block;</div><div class='ctx'> </div><div class='add'>+int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='add'>+				      bool req);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c<br/>index 34f9211b2679..80565392313f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c</a></div><div class='hunk'>@@ -28,19 +28,33 @@</div><div class='ctx'> #include "amdgpu_gfx.h"</div><div class='ctx'> #include "amdgpu_ucode.h"</div><div class='ctx'> #include "clearstate_si.h"</div><div class='add'>+#include "si.h"</div><div class='add'>+#include "sid.h"</div><div class='add'>+</div><div class='ctx'> #include "bif/bif_3_0_d.h"</div><div class='ctx'> #include "bif/bif_3_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "oss/oss_1_0_d.h"</div><div class='ctx'> #include "oss/oss_1_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "gca/gfx_6_0_d.h"</div><div class='ctx'> #include "gca/gfx_6_0_sh_mask.h"</div><div class='add'>+#include "gca/gfx_7_2_enum.h"</div><div class='add'>+</div><div class='ctx'> #include "gmc/gmc_6_0_d.h"</div><div class='ctx'> #include "gmc/gmc_6_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "dce/dce_6_0_d.h"</div><div class='ctx'> #include "dce/dce_6_0_sh_mask.h"</div><div class='del'>-#include "gca/gfx_7_2_enum.h"</div><div class='add'>+</div><div class='ctx'> #include "si_enums.h"</div><div class='del'>-#include "si.h"</div><div class='add'>+</div><div class='add'>+#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003</div><div class='add'>+#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002</div><div class='add'>+#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001</div><div class='add'>+</div><div class='add'>+#define GFX6_NUM_GFX_RINGS     1</div><div class='add'>+#define GFX6_NUM_COMPUTE_RINGS 2</div><div class='ctx'> </div><div class='ctx'> static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='hunk'>@@ -72,7 +86,7 @@ MODULE_FIRMWARE("amdgpu/hainan_ce.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");</div><div class='ctx'> </div><div class='ctx'> static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);</div><div class='del'>-static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);</div><div class='add'>+static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer);</div><div class='ctx'> //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v6_0_init_pg(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -311,7 +325,6 @@ static const u32 verde_rlc_save_restore_register_list[] =</div><div class='ctx'> static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct gfx_firmware_header_v1_0 *cp_hdr;</div><div class='ctx'> 	const struct rlc_firmware_header_v1_0 *rlc_hdr;</div><div class='hunk'>@@ -337,32 +350,36 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	default: BUG();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_pfp.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev-&gt;gfx.pfp_fw-&gt;data;</div><div class='ctx'> 	adev-&gt;gfx.pfp_fw_version = le32_to_cpu(cp_hdr-&gt;header.ucode_version);</div><div class='ctx'> 	adev-&gt;gfx.pfp_feature_version = le32_to_cpu(cp_hdr-&gt;ucode_feature_version);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_me.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev-&gt;gfx.me_fw-&gt;data;</div><div class='ctx'> 	adev-&gt;gfx.me_fw_version = le32_to_cpu(cp_hdr-&gt;header.ucode_version);</div><div class='ctx'> 	adev-&gt;gfx.me_feature_version = le32_to_cpu(cp_hdr-&gt;ucode_feature_version);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_ce.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev-&gt;gfx.ce_fw-&gt;data;</div><div class='ctx'> 	adev-&gt;gfx.ce_fw_version = le32_to_cpu(cp_hdr-&gt;header.ucode_version);</div><div class='ctx'> 	adev-&gt;gfx.ce_feature_version = le32_to_cpu(cp_hdr-&gt;ucode_feature_version);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_rlc.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='hunk'>@@ -371,7 +388,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.pfp_fw);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.me_fw);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.ce_fw);</div><div class='hunk'>@@ -1718,10 +1735,14 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)</div><div class='ctx'> 	gfx_v6_0_get_cu_info(adev);</div><div class='ctx'> 	gfx_v6_0_config_init(adev);</div><div class='ctx'> </div><div class='del'>-	WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 &lt;&lt; CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |</div><div class='del'>-				       (0x2b &lt;&lt; CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));</div><div class='del'>-	WREG32(mmCP_MEQ_THRESHOLDS, (0x30 &lt;&lt; CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |</div><div class='del'>-				    (0x60 &lt;&lt; CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));</div><div class='add'>+	WREG32(mmCP_QUEUE_THRESHOLDS,</div><div class='add'>+		((0x16 &lt;&lt; CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |</div><div class='add'>+		(0x2b &lt;&lt; CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* set HW defaults for 3D engine */</div><div class='add'>+	WREG32(mmCP_MEQ_THRESHOLDS,</div><div class='add'>+		(0x30 &lt;&lt; CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |</div><div class='add'>+		(0x60 &lt;&lt; CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));</div><div class='ctx'> </div><div class='ctx'> 	sx_debug_1 = RREG32(mmSX_DEBUG_1);</div><div class='ctx'> 	WREG32(mmSX_DEBUG_1, sx_debug_1);</div><div class='hunk'>@@ -1907,7 +1928,7 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -2333,7 +2354,7 @@ static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='ctx'> static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const u32 *src_ptr;</div><div class='del'>-	volatile u32 *dst_ptr;</div><div class='add'>+	u32 *dst_ptr;</div><div class='ctx'> 	u32 dws;</div><div class='ctx'> 	u64 reg_list_mc_addr;</div><div class='ctx'> 	const struct cs_section_def *cs_data;</div><div class='hunk'>@@ -2834,47 +2855,23 @@ static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='del'>-				    volatile u32 *buffer)</div><div class='add'>+static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='ctx'> {</div><div class='del'>-	u32 count = 0, i;</div><div class='del'>-	const struct cs_section_def *sect = NULL;</div><div class='del'>-	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> 	if (buffer == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-</div><div class='del'>-	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='del'>-		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='del'>-			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='del'>-				buffer[count++] =</div><div class='del'>-					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='del'>-				buffer[count++] = cpu_to_le32(ext-&gt;reg_index - 0xa000);</div><div class='del'>-				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='del'>-					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='del'>-			} else {</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	count = amdgpu_gfx_csb_preamble_start(buffer);</div><div class='add'>+	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);</div><div class='ctx'> </div><div class='ctx'> 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.rb_config[0][0].raster_config);</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+	amdgpu_gfx_csb_preamble_end(buffer, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v6_0_init_pg(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3024,9 +3021,9 @@ static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {</div><div class='ctx'> 	.start = gfx_v6_0_rlc_start</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_early_init(void *handle)</div><div class='add'>+static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 	adev-&gt;gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;</div><div class='hunk'>@@ -3040,10 +3037,10 @@ static int gfx_v6_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_sw_init(void *handle)</div><div class='add'>+static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &amp;adev-&gt;gfx.eop_irq);</div><div class='hunk'>@@ -3105,13 +3102,18 @@ static int gfx_v6_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_sw_fini(void *handle)</div><div class='add'>+static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;gfx.gfx_ring[i]);</div><div class='hunk'>@@ -3123,10 +3125,10 @@ static int gfx_v6_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_hw_init(void *handle)</div><div class='add'>+static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v6_0_constants_init(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -3143,9 +3145,9 @@ static int gfx_v6_0_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_hw_fini(void *handle)</div><div class='add'>+static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v6_0_cp_enable(adev, false);</div><div class='ctx'> 	adev-&gt;gfx.rlc.funcs-&gt;stop(adev);</div><div class='hunk'>@@ -3154,23 +3156,19 @@ static int gfx_v6_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_suspend(void *handle)</div><div class='add'>+static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return gfx_v6_0_hw_fini(adev);</div><div class='add'>+	return gfx_v6_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_resume(void *handle)</div><div class='add'>+static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return gfx_v6_0_hw_init(adev);</div><div class='add'>+	return gfx_v6_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v6_0_is_idle(void *handle)</div><div class='add'>+static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (RREG32(mmGRBM_STATUS) &amp; GRBM_STATUS__GUI_ACTIVE_MASK)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -3178,24 +3176,19 @@ static bool gfx_v6_0_is_idle(void *handle)</div><div class='ctx'> 		return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (gfx_v6_0_is_idle(handle))</div><div class='add'>+		if (gfx_v6_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 						 enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='hunk'>@@ -3383,11 +3376,11 @@ static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_CG_STATE_GATE)</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -3405,11 +3398,11 @@ static int gfx_v6_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v6_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -3445,7 +3438,6 @@ static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)</div><div class='ctx'> static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {</div><div class='ctx'> 	.name = "gfx_v6_0",</div><div class='ctx'> 	.early_init = gfx_v6_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = gfx_v6_0_sw_init,</div><div class='ctx'> 	.sw_fini = gfx_v6_0_sw_fini,</div><div class='ctx'> 	.hw_init = gfx_v6_0_hw_init,</div><div class='hunk'>@@ -3454,7 +3446,6 @@ static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {</div><div class='ctx'> 	.resume = gfx_v6_0_resume,</div><div class='ctx'> 	.is_idle = gfx_v6_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = gfx_v6_0_wait_for_idle,</div><div class='del'>-	.soft_reset = gfx_v6_0_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = gfx_v6_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gfx_v6_0_set_powergating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br/>index 86a4865b1ae5..2b7aba22ecc1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c</a></div><div class='hunk'>@@ -55,6 +55,9 @@</div><div class='ctx'> #define GFX7_NUM_GFX_RINGS     1</div><div class='ctx'> #define GFX7_MEC_HPD_SIZE      2048</div><div class='ctx'> </div><div class='add'>+#define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001</div><div class='add'>+#define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003</div><div class='add'>+</div><div class='ctx'> static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);</div><div class='hunk'>@@ -880,7 +883,7 @@ static const u32 kalindi_rlc_save_restore_register_list[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);</div><div class='del'>-static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);</div><div class='add'>+static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer);</div><div class='ctx'> static void gfx_v7_0_init_pg(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -909,7 +912,6 @@ static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='hunk'>@@ -934,40 +936,44 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		BUG();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_pfp.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_me.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_ce.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mec.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;asic_type == CHIP_KAVERI) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_mec2.bin", chip_name);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='del'>-	if (err)</div><div class='del'>-		goto out;</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_rlc.bin", chip_name);</div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("gfx7: Failed to load firmware %s gfx firmware\n", chip_name);</div><div class='ctx'> 		gfx_v7_0_free_microcode(adev);</div><div class='ctx'> 	}</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -2117,6 +2123,8 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> {</div><div class='ctx'> 	bool write64bit = flags &amp; AMDGPU_FENCE_FLAG_64BIT;</div><div class='ctx'> 	bool int_sel = flags &amp; AMDGPU_FENCE_FLAG_INT;</div><div class='add'>+	bool exec = flags &amp; AMDGPU_FENCE_FLAG_EXEC;</div><div class='add'>+</div><div class='ctx'> 	/* Workaround for cache flush problems. First send a dummy EOP</div><div class='ctx'> 	 * event down the pipe with seq one below.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -2136,7 +2144,8 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> 	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |</div><div class='ctx'> 				 EOP_TC_ACTION_EN |</div><div class='ctx'> 				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |</div><div class='del'>-				 EVENT_INDEX(5)));</div><div class='add'>+				 EVENT_INDEX(5) |</div><div class='add'>+				 (exec ? EOP_EXEC : 0)));</div><div class='ctx'> 	amdgpu_ring_write(ring, addr &amp; 0xfffffffc);</div><div class='ctx'> 	amdgpu_ring_write(ring, (upper_32_bits(addr) &amp; 0xffff) |</div><div class='ctx'> 				DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));</div><div class='hunk'>@@ -2324,7 +2333,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> error:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -2559,7 +2568,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	ring-&gt;wptr = 0;</div><div class='ctx'> 	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> </div><div class='del'>-	/* set the wb address wether it's enabled or not */</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 	WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp; 0xFF);</div><div class='hunk'>@@ -2757,44 +2766,6 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct hqd_registers {</div><div class='del'>-	u32 cp_mqd_base_addr;</div><div class='del'>-	u32 cp_mqd_base_addr_hi;</div><div class='del'>-	u32 cp_hqd_active;</div><div class='del'>-	u32 cp_hqd_vmid;</div><div class='del'>-	u32 cp_hqd_persistent_state;</div><div class='del'>-	u32 cp_hqd_pipe_priority;</div><div class='del'>-	u32 cp_hqd_queue_priority;</div><div class='del'>-	u32 cp_hqd_quantum;</div><div class='del'>-	u32 cp_hqd_pq_base;</div><div class='del'>-	u32 cp_hqd_pq_base_hi;</div><div class='del'>-	u32 cp_hqd_pq_rptr;</div><div class='del'>-	u32 cp_hqd_pq_rptr_report_addr;</div><div class='del'>-	u32 cp_hqd_pq_rptr_report_addr_hi;</div><div class='del'>-	u32 cp_hqd_pq_wptr_poll_addr;</div><div class='del'>-	u32 cp_hqd_pq_wptr_poll_addr_hi;</div><div class='del'>-	u32 cp_hqd_pq_doorbell_control;</div><div class='del'>-	u32 cp_hqd_pq_wptr;</div><div class='del'>-	u32 cp_hqd_pq_control;</div><div class='del'>-	u32 cp_hqd_ib_base_addr;</div><div class='del'>-	u32 cp_hqd_ib_base_addr_hi;</div><div class='del'>-	u32 cp_hqd_ib_rptr;</div><div class='del'>-	u32 cp_hqd_ib_control;</div><div class='del'>-	u32 cp_hqd_iq_timer;</div><div class='del'>-	u32 cp_hqd_iq_rptr;</div><div class='del'>-	u32 cp_hqd_dequeue_request;</div><div class='del'>-	u32 cp_hqd_dma_offload;</div><div class='del'>-	u32 cp_hqd_sema_cmd;</div><div class='del'>-	u32 cp_hqd_msg_type;</div><div class='del'>-	u32 cp_hqd_atomic0_preop_lo;</div><div class='del'>-	u32 cp_hqd_atomic0_preop_hi;</div><div class='del'>-	u32 cp_hqd_atomic1_preop_lo;</div><div class='del'>-	u32 cp_hqd_atomic1_preop_hi;</div><div class='del'>-	u32 cp_hqd_hq_scheduler0;</div><div class='del'>-	u32 cp_hqd_hq_scheduler1;</div><div class='del'>-	u32 cp_mqd_control;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,</div><div class='ctx'> 				       int mec, int pipe)</div><div class='ctx'> {</div><div class='hunk'>@@ -2914,7 +2885,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='ctx'> </div><div class='del'>-	/* set the wb address wether it's enabled or not */</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	wb_gpu_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_rptr_report_addr_hi =</div><div class='hunk'>@@ -3911,70 +3882,24 @@ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='del'>-				    volatile u32 *buffer)</div><div class='add'>+static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='ctx'> {</div><div class='del'>-	u32 count = 0, i;</div><div class='del'>-	const struct cs_section_def *sect = NULL;</div><div class='del'>-	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> 	if (buffer == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-</div><div class='del'>-	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='del'>-		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='del'>-			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='del'>-				buffer[count++] =</div><div class='del'>-					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='del'>-				buffer[count++] = cpu_to_le32(ext-&gt;reg_index - PACKET3_SET_CONTEXT_REG_START);</div><div class='del'>-				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='del'>-					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='del'>-			} else {</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	count = amdgpu_gfx_csb_preamble_start(buffer);</div><div class='add'>+	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);</div><div class='ctx'> </div><div class='ctx'> 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);</div><div class='del'>-	switch (adev-&gt;asic_type) {</div><div class='del'>-	case CHIP_BONAIRE:</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x16000012);</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000);</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_KAVERI:</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000); /* XXX */</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000);</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_KABINI:</div><div class='del'>-	case CHIP_MULLINS:</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000); /* XXX */</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000);</div><div class='del'>-		break;</div><div class='del'>-	case CHIP_HAWAII:</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x3a00161a);</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x0000002e);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000);</div><div class='del'>-		buffer[count++] = cpu_to_le32(0x00000000);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='add'>+	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.rb_config[0][0].raster_config);</div><div class='add'>+	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.rb_config[0][0].raster_config_1);</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+	amdgpu_gfx_csb_preamble_end(buffer, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v7_0_init_pg(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4172,9 +4097,9 @@ static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {</div><div class='ctx'> 	.update_spm_vmid = gfx_v7_0_update_spm_vmid</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_early_init(void *handle)</div><div class='add'>+static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 	adev-&gt;gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;</div><div class='hunk'>@@ -4189,9 +4114,9 @@ static int gfx_v7_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_late_init(void *handle)</div><div class='add'>+static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='hunk'>@@ -4381,10 +4306,10 @@ static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_sw_init(void *handle)</div><div class='add'>+static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, j, k, r, ring_id;</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='hunk'>@@ -4474,12 +4399,17 @@ static int gfx_v7_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	gfx_v7_0_gpu_early_init(adev);</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_sw_fini(void *handle)</div><div class='add'>+static int gfx_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='hunk'>@@ -4503,10 +4433,10 @@ static int gfx_v7_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_hw_init(void *handle)</div><div class='add'>+static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v7_0_constants_init(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -4524,9 +4454,9 @@ static int gfx_v7_0_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_hw_fini(void *handle)</div><div class='add'>+static int gfx_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='hunk'>@@ -4537,23 +4467,19 @@ static int gfx_v7_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_suspend(void *handle)</div><div class='add'>+static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return gfx_v7_0_hw_fini(adev);</div><div class='add'>+	return gfx_v7_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_resume(void *handle)</div><div class='add'>+static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return gfx_v7_0_hw_init(adev);</div><div class='add'>+	return gfx_v7_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v7_0_is_idle(void *handle)</div><div class='add'>+static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (RREG32(mmGRBM_STATUS) &amp; GRBM_STATUS__GUI_ACTIVE_MASK)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -4561,11 +4487,11 @@ static bool gfx_v7_0_is_idle(void *handle)</div><div class='ctx'> 		return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -4578,11 +4504,11 @@ static int gfx_v7_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_soft_reset(void *handle)</div><div class='add'>+static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* GRBM_STATUS */</div><div class='ctx'> 	tmp = RREG32(mmGRBM_STATUS);</div><div class='hunk'>@@ -4888,11 +4814,11 @@ static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_CG_STATE_GATE)</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -4911,11 +4837,11 @@ static int gfx_v7_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v7_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -5041,6 +4967,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {</div><div class='ctx'> 	.insert_nop = amdgpu_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_wreg = gfx_v7_0_ring_emit_wreg,</div><div class='add'>+	.soft_recovery = gfx_v7_0_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v7_0_emit_mem_sync_compute,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br/>index 202ddda57f98..1c87375e1dd5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c</a></div><div class='hunk'>@@ -914,7 +914,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err2:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err1:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -939,7 +939,6 @@ static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	struct amdgpu_firmware_info *info = NULL;</div><div class='ctx'> 	const struct common_firmware_header *header = NULL;</div><div class='hunk'>@@ -982,15 +981,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;asic_type &gt;= CHIP_POLARIS10 &amp;&amp; adev-&gt;asic_type &lt;= CHIP_POLARIS12) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+					   AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+					   "amdgpu/%s_pfp_2.bin", chip_name);</div><div class='ctx'> 		if (err == -ENODEV) {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);</div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_pfp.bin", chip_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_pfp.bin", chip_name);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -999,15 +1001,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.pfp_feature_version = le32_to_cpu(cp_hdr-&gt;ucode_feature_version);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;asic_type &gt;= CHIP_POLARIS10 &amp;&amp; adev-&gt;asic_type &lt;= CHIP_POLARIS12) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+					   AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+					   "amdgpu/%s_me_2.bin", chip_name);</div><div class='ctx'> 		if (err == -ENODEV) {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);</div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_me.bin", chip_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_me.bin", chip_name);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -1017,15 +1022,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.me_feature_version = le32_to_cpu(cp_hdr-&gt;ucode_feature_version);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;asic_type &gt;= CHIP_POLARIS10 &amp;&amp; adev-&gt;asic_type &lt;= CHIP_POLARIS12) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+					   AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+					   "amdgpu/%s_ce_2.bin", chip_name);</div><div class='ctx'> 		if (err == -ENODEV) {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);</div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_ce.bin", chip_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_ce.bin", chip_name);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -1044,8 +1052,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	} else</div><div class='ctx'> 		adev-&gt;virt.chained_ib_support = false;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_rlc.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='hunk'>@@ -1093,15 +1102,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;asic_type &gt;= CHIP_POLARIS10 &amp;&amp; adev-&gt;asic_type &lt;= CHIP_POLARIS12) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+					   AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+					   "amdgpu/%s_mec_2.bin", chip_name);</div><div class='ctx'> 		if (err == -ENODEV) {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);</div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_mec.bin", chip_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_mec.bin", chip_name);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -1112,15 +1124,18 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	if ((adev-&gt;asic_type != CHIP_STONEY) &amp;&amp;</div><div class='ctx'> 	    (adev-&gt;asic_type != CHIP_TOPAZ)) {</div><div class='ctx'> 		if (adev-&gt;asic_type &gt;= CHIP_POLARIS10 &amp;&amp; adev-&gt;asic_type &lt;= CHIP_POLARIS12) {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);</div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+						   AMDGPU_UCODE_OPTIONAL,</div><div class='add'>+						   "amdgpu/%s_mec2_2.bin", chip_name);</div><div class='ctx'> 			if (err == -ENODEV) {</div><div class='del'>-				snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);</div><div class='del'>-				err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw, fw_name);</div><div class='add'>+				err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+							   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+							   "amdgpu/%s_mec2.bin", chip_name);</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);</div><div class='del'>-			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_mec2.bin", chip_name);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (!err) {</div><div class='ctx'> 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)</div><div class='hunk'>@@ -1194,9 +1209,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			"gfx8: Failed to load firmware \"%s\"\n",</div><div class='del'>-			fw_name);</div><div class='add'>+		dev_err(adev-&gt;dev, "gfx8: Failed to load firmware %s gfx firmware\n", chip_name);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.pfp_fw);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.me_fw);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.ce_fw);</div><div class='hunk'>@@ -1207,51 +1220,24 @@ out:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='del'>-				    volatile u32 *buffer)</div><div class='add'>+static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='ctx'> {</div><div class='del'>-	u32 count = 0, i;</div><div class='del'>-	const struct cs_section_def *sect = NULL;</div><div class='del'>-	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> 	if (buffer == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-</div><div class='del'>-	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='del'>-		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='del'>-			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='del'>-				buffer[count++] =</div><div class='del'>-					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='del'>-				buffer[count++] = cpu_to_le32(ext-&gt;reg_index -</div><div class='del'>-						PACKET3_SET_CONTEXT_REG_START);</div><div class='del'>-				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='del'>-					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='del'>-			} else {</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	count = amdgpu_gfx_csb_preamble_start(buffer);</div><div class='add'>+	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);</div><div class='ctx'> </div><div class='ctx'> 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));</div><div class='del'>-	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -</div><div class='del'>-			PACKET3_SET_CONTEXT_REG_START);</div><div class='add'>+	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.rb_config[0][0].raster_config);</div><div class='ctx'> 	buffer[count++] = cpu_to_le32(adev-&gt;gfx.config.rb_config[0][0].raster_config_1);</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+	amdgpu_gfx_csb_preamble_end(buffer, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1643,7 +1629,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)</div><div class='ctx'> 		RREG32(sec_ded_counter_registers[i]);</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1897,12 +1883,12 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> </div><div class='ctx'> static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_sw_init(void *handle)</div><div class='add'>+static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j, k, r, ring_id;</div><div class='ctx'> 	int xcc_id = 0;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> 	case CHIP_TONGA:</div><div class='hunk'>@@ -2037,12 +2023,17 @@ static int gfx_v8_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_sw_fini(void *handle)</div><div class='add'>+static int gfx_v8_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_gfx_rings; i++)</div><div class='hunk'>@@ -4263,7 +4254,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	ring-&gt;wptr = 0;</div><div class='ctx'> 	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> </div><div class='del'>-	/* set the wb address wether it's enabled or not */</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 	WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp; 0xFF);</div><div class='hunk'>@@ -4307,9 +4298,7 @@ static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='ctx'> 	tmp = RREG32(mmRLC_CP_SCHEDULERS);</div><div class='ctx'> 	tmp &amp;= 0xffffff00;</div><div class='ctx'> 	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-	WREG32(mmRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-	tmp |= 0x80;</div><div class='del'>-	WREG32(mmRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+	WREG32(mmRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4655,6 +4644,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> 			memcpy(mqd, adev-&gt;gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));</div><div class='ctx'> 		/* reset ring buffer */</div><div class='ctx'> 		ring-&gt;wptr = 0;</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr, 0);</div><div class='ctx'> 		amdgpu_ring_clear_ring(ring);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -4672,60 +4662,25 @@ static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(ring-&gt;mqd_obj, &amp;ring-&gt;mqd_ptr);</div><div class='del'>-	if (unlikely(r != 0)) {</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gfx_v8_0_kiq_init_queue(ring);</div><div class='del'>-	amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-	ring-&gt;mqd_ptr = NULL;</div><div class='del'>-	amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+	gfx_v8_0_kiq_init_queue(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = NULL;</div><div class='del'>-	int r = 0, i;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v8_0_cp_compute_enable(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			goto done;</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, &amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v8_0_kcq_init_queue(ring);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+		r = gfx_v8_0_kcq_init_queue(&amp;adev-&gt;gfx.compute_ring[i]);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	gfx_v8_0_set_mec_doorbell_range(adev);</div><div class='ctx'> </div><div class='del'>-	r = gfx_v8_0_kiq_kcq_enable(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		goto done;</div><div class='del'>-</div><div class='del'>-done:</div><div class='del'>-	return r;</div><div class='add'>+	return gfx_v8_0_kiq_kcq_enable(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4786,10 +4741,10 @@ static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 	gfx_v8_0_cp_compute_enable(adev, enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_hw_init(void *handle)</div><div class='add'>+static int gfx_v8_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v8_0_init_golden_registers(adev);</div><div class='ctx'> 	gfx_v8_0_constants_init(adev);</div><div class='hunk'>@@ -4826,6 +4781,13 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_ring_write(kiq_ring, 0);</div><div class='ctx'> 		amdgpu_ring_write(kiq_ring, 0);</div><div class='ctx'> 	}</div><div class='add'>+	/* Submit unmap queue packet */</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	/*</div><div class='add'>+	 * Ring test will do a basic scratch register change check. Just run</div><div class='add'>+	 * this to ensure that unmap queues that is submitted before got</div><div class='add'>+	 * processed successfully before returning.</div><div class='add'>+	 */</div><div class='ctx'> 	r = amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		DRM_ERROR("KCQ disable failed\n");</div><div class='hunk'>@@ -4833,9 +4795,9 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v8_0_is_idle(void *handle)</div><div class='add'>+static bool gfx_v8_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)</div><div class='ctx'> 		|| RREG32(mmGRBM_STATUS2) != 0x8)</div><div class='hunk'>@@ -4868,13 +4830,13 @@ static int gfx_v8_0_wait_for_rlc_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (gfx_v8_0_is_idle(handle))</div><div class='add'>+		if (gfx_v8_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> </div><div class='ctx'> 		udelay(1);</div><div class='hunk'>@@ -4882,9 +4844,9 @@ static int gfx_v8_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_hw_fini(void *handle)</div><div class='add'>+static int gfx_v8_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='hunk'>@@ -4900,8 +4862,9 @@ static int gfx_v8_0_hw_fini(void *handle)</div><div class='ctx'> 		pr_debug("For SRIOV client, shouldn't do anything.\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='del'>-	if (!gfx_v8_0_wait_for_idle(adev))</div><div class='add'>+	if (!gfx_v8_0_wait_for_idle(ip_block))</div><div class='ctx'> 		gfx_v8_0_cp_enable(adev, false);</div><div class='ctx'> 	else</div><div class='ctx'> 		pr_err("cp is busy, skip halt cp\n");</div><div class='hunk'>@@ -4914,19 +4877,19 @@ static int gfx_v8_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_suspend(void *handle)</div><div class='add'>+static int gfx_v8_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v8_0_hw_fini(handle);</div><div class='add'>+	return gfx_v8_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_resume(void *handle)</div><div class='add'>+static int gfx_v8_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v8_0_hw_init(handle);</div><div class='add'>+	return gfx_v8_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v8_0_check_soft_reset(void *handle)</div><div class='add'>+static bool gfx_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -4986,9 +4949,9 @@ static bool gfx_v8_0_check_soft_reset(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_pre_soft_reset(void *handle)</div><div class='add'>+static int gfx_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> </div><div class='ctx'> 	if ((!adev-&gt;gfx.grbm_soft_reset) &amp;&amp;</div><div class='hunk'>@@ -5027,9 +4990,9 @@ static int gfx_v8_0_pre_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_soft_reset(void *handle)</div><div class='add'>+static int gfx_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -5089,9 +5052,9 @@ static int gfx_v8_0_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_post_soft_reset(void *handle)</div><div class='add'>+static int gfx_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> </div><div class='ctx'> 	if ((!adev-&gt;gfx.grbm_soft_reset) &amp;&amp;</div><div class='hunk'>@@ -5257,9 +5220,9 @@ static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {</div><div class='ctx'> 	.select_me_pipe_q = &amp;gfx_v8_0_select_me_pipe_q</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_early_init(void *handle)</div><div class='add'>+static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.xcc_mask = 1;</div><div class='ctx'> 	adev-&gt;gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;</div><div class='hunk'>@@ -5274,9 +5237,9 @@ static int gfx_v8_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_late_init(void *handle)</div><div class='add'>+static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='hunk'>@@ -5316,7 +5279,7 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade</div><div class='ctx'> 	    (adev-&gt;asic_type == CHIP_POLARIS12) ||</div><div class='ctx'> 	    (adev-&gt;asic_type == CHIP_VEGAM))</div><div class='ctx'> 		/* Send msg to SMU via Powerplay */</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);</div><div class='ctx'> }</div><div class='hunk'>@@ -5362,10 +5325,10 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -5433,9 +5396,9 @@ static int gfx_v8_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v8_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gfx_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -5620,8 +5583,6 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t temp, data;</div><div class='ctx'> </div><div class='del'>-	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='del'>-</div><div class='ctx'> 	/* It is disabled by HW by default */</div><div class='ctx'> 	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_MGCG)) {</div><div class='ctx'> 		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_MGLS) {</div><div class='hunk'>@@ -5715,8 +5676,6 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> 		/* 7- wait for RLC_SERDES_CU_MASTER &amp; RLC_SERDES_NONCU_MASTER idle */</div><div class='ctx'> 		gfx_v8_0_wait_for_rlc_serdes(adev);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,</div><div class='hunk'>@@ -5726,8 +5685,6 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> </div><div class='ctx'> 	temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);</div><div class='ctx'> </div><div class='del'>-	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='del'>-</div><div class='ctx'> 	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGCG)) {</div><div class='ctx'> 		temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);</div><div class='ctx'> 		data1 &amp;= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;</div><div class='hunk'>@@ -5808,12 +5765,12 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	gfx_v8_0_wait_for_rlc_serdes(adev);</div><div class='del'>-</div><div class='del'>-	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 					    bool enable)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+</div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)</div><div class='ctx'> 		 * ===  MGCG + MGLS + TS(CG/LS) ===</div><div class='hunk'>@@ -5827,6 +5784,8 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 		gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);</div><div class='ctx'> 		gfx_v8_0_update_medium_grain_clock_gating(adev, enable);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5977,10 +5936,10 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v8_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -6152,6 +6111,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> {</div><div class='ctx'> 	bool write64bit = flags &amp; AMDGPU_FENCE_FLAG_64BIT;</div><div class='ctx'> 	bool int_sel = flags &amp; AMDGPU_FENCE_FLAG_INT;</div><div class='add'>+	bool exec = flags &amp; AMDGPU_FENCE_FLAG_EXEC;</div><div class='ctx'> </div><div class='ctx'> 	/* Workaround for cache flush problems. First send a dummy EOP</div><div class='ctx'> 	 * event down the pipe with seq one below.</div><div class='hunk'>@@ -6175,7 +6135,8 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,</div><div class='ctx'> 				 EOP_TC_ACTION_EN |</div><div class='ctx'> 				 EOP_TC_WB_ACTION_EN |</div><div class='ctx'> 				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |</div><div class='del'>-				 EVENT_INDEX(5)));</div><div class='add'>+				 EVENT_INDEX(5) |</div><div class='add'>+				 (exec ? EOP_EXEC : 0)));</div><div class='ctx'> 	amdgpu_ring_write(ring, addr &amp; 0xfffffffc);</div><div class='ctx'> 	amdgpu_ring_write(ring, (upper_32_bits(addr) &amp; 0xffff) |</div><div class='ctx'> 			  DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));</div><div class='hunk'>@@ -6956,6 +6917,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {</div><div class='ctx'> 	.insert_nop = amdgpu_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_wreg = gfx_v8_0_ring_emit_wreg,</div><div class='add'>+	.soft_recovery = gfx_v8_0_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,</div><div class='ctx'> 	.emit_wave_limit = gfx_v8_0_emit_wave_limit,</div><div class='ctx'> };</div><div class='hunk'>@@ -6982,6 +6944,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_rreg = gfx_v8_0_ring_emit_rreg,</div><div class='ctx'> 	.emit_wreg = gfx_v8_0_ring_emit_wreg,</div><div class='add'>+	.emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br/>index 6f97a6d0e6d0..0148d7ff34d9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</a></div><div class='hunk'>@@ -50,6 +50,7 @@</div><div class='ctx'> #include "amdgpu_ring_mux.h"</div><div class='ctx'> #include "gfx_v9_4.h"</div><div class='ctx'> #include "gfx_v9_0.h"</div><div class='add'>+#include "gfx_v9_0_cleaner_shader.h"</div><div class='ctx'> #include "gfx_v9_4_2.h"</div><div class='ctx'> </div><div class='ctx'> #include "asic_reg/pwr/pwr_10_0_offset.h"</div><div class='hunk'>@@ -149,6 +150,162 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");</div><div class='ctx'> #define mmGOLDEN_TSC_COUNT_LOWER_Renoir                0x0026</div><div class='ctx'> #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX       1</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_reg_list_9[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSQ_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),</div><div class='add'>+	/* SE status registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3),</div><div class='add'>+	/* packet headers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9[] = {</div><div class='add'>+	/* compute queue registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ACTIVE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GFX_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum ta_ras_gfx_subblock {</div><div class='ctx'> 	/*CPC*/</div><div class='ctx'> 	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,</div><div class='hunk'>@@ -764,10 +921,18 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,</div><div class='ctx'> static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev,</div><div class='ctx'> 					      unsigned int vmid);</div><div class='add'>+static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);</div><div class='add'>+static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 				uint64_t queue_mask)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	u64 shader_mc_addr;</div><div class='add'>+</div><div class='add'>+	/* Cleaner shader MC address */</div><div class='add'>+	shader_mc_addr = adev-&gt;gfx.cleaner_shader_gpu_addr &gt;&gt; 8;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring,</div><div class='ctx'> 		PACKET3_SET_RESOURCES_VMID_MASK(0) |</div><div class='hunk'>@@ -777,8 +942,8 @@ static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 			lower_32_bits(queue_mask));	/* queue mask lo */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring,</div><div class='ctx'> 			upper_32_bits(queue_mask));	/* queue mask hi */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */</div><div class='ctx'> }</div><div class='hunk'>@@ -875,12 +1040,47 @@ static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+static void gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,</div><div class='add'>+					uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+					uint32_t xcc_id, uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	unsigned i;</div><div class='add'>+</div><div class='add'>+	/* enter save mode */</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, 0);</div><div class='add'>+</div><div class='add'>+	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='add'>+		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+			dev_err(adev-&gt;dev, "fail to wait on hqd deactive\n");</div><div class='add'>+	} else {</div><div class='add'>+		dev_err(adev-&gt;dev, "reset queue_type(%d) not supported\n", queue_type);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	/* exit safe mode */</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {</div><div class='ctx'> 	.kiq_set_resources = gfx_v9_0_kiq_set_resources,</div><div class='ctx'> 	.kiq_map_queues = gfx_v9_0_kiq_map_queues,</div><div class='ctx'> 	.kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,</div><div class='ctx'> 	.kiq_query_status = gfx_v9_0_kiq_query_status,</div><div class='ctx'> 	.kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,</div><div class='add'>+	.kiq_reset_hw_queue = gfx_v9_0_kiq_reset_hw_queue,</div><div class='ctx'> 	.set_resources_size = 8,</div><div class='ctx'> 	.map_queues_size = 7,</div><div class='ctx'> 	.unmap_queues_size = 6,</div><div class='hunk'>@@ -1070,7 +1270,7 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err2:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err1:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -1096,6 +1296,7 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.mec_fw_write_wait = false;</div><div class='ctx'> </div><div class='ctx'> 	if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) &amp;&amp;</div><div class='add'>+	    (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) &amp;&amp;</div><div class='ctx'> 	    ((adev-&gt;gfx.mec_fw_version &lt; 0x000001a5) ||</div><div class='ctx'> 	     (adev-&gt;gfx.mec_feature_version &lt; 46) ||</div><div class='ctx'> 	     (adev-&gt;gfx.pfp_fw_version &lt; 0x000000b7) ||</div><div class='hunk'>@@ -1172,6 +1373,10 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {</div><div class='ctx'> 	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },</div><div class='ctx'> 	/* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */</div><div class='ctx'> 	{ 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 },</div><div class='add'>+	/* https://bbs.openkylin.top/t/topic/171497 */</div><div class='add'>+	{ 0x1002, 0x15d8, 0x19e5, 0x3e14, 0xc2 },</div><div class='add'>+	/* HP 705G4 DM with R5 2400G */</div><div class='add'>+	{ 0x1002, 0x15dd, 0x103c, 0x8464, 0xd6 },</div><div class='ctx'> 	{ 0, 0, 0, 0, 0 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1249,23 +1454,25 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)</div><div class='ctx'> static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 					  char *chip_name)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.pfp_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_pfp.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.me_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_me.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.ce_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_ce.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);</div><div class='hunk'>@@ -1282,7 +1489,6 @@ out:</div><div class='ctx'> static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 				       char *chip_name)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct rlc_firmware_header_v2_0 *rlc_hdr;</div><div class='ctx'> 	uint16_t version_major;</div><div class='hunk'>@@ -1300,20 +1506,25 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!strcmp(chip_name, "picasso") &amp;&amp;</div><div class='ctx'> 		(((adev-&gt;pdev-&gt;revision &gt;= 0xC8) &amp;&amp; (adev-&gt;pdev-&gt;revision &lt;= 0xCF)) ||</div><div class='ctx'> 		((adev-&gt;pdev-&gt;revision &gt;= 0xD8) &amp;&amp; (adev-&gt;pdev-&gt;revision &lt;= 0xDF))))</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_rlc_am4.bin", chip_name);</div><div class='ctx'> 	else if (!strcmp(chip_name, "raven") &amp;&amp; (amdgpu_pm_load_smu_firmware(adev, &amp;smu_version) == 0) &amp;&amp;</div><div class='ctx'> 		(smu_version &gt;= 0x41e2b))</div><div class='ctx'> 		/**</div><div class='ctx'> 		*SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.</div><div class='ctx'> 		*/</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_kicker_rlc.bin", chip_name);</div><div class='ctx'> 	else</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_rlc.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='del'>-	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='ctx'> </div><div class='add'>+	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='ctx'> 	version_major = le16_to_cpu(rlc_hdr-&gt;header.header_version_major);</div><div class='ctx'> 	version_minor = le16_to_cpu(rlc_hdr-&gt;header.header_version_minor);</div><div class='ctx'> 	err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);</div><div class='hunk'>@@ -1337,28 +1548,31 @@ static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)</div><div class='ctx'> static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 					      char *chip_name)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;asic_type == CHIP_ALDEBARAN))</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_sjt_mec.bin", chip_name);</div><div class='ctx'> 	else</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);</div><div class='del'>-</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_mec.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);</div><div class='ctx'> </div><div class='ctx'> 	if (gfx_v9_0_load_mec2_fw_bin_support(adev)) {</div><div class='ctx'> 		if (amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;asic_type == CHIP_ALDEBARAN))</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sjt_mec2.bin", chip_name);</div><div class='ctx'> 		else</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);</div><div class='del'>-</div><div class='del'>-		/* ignore failures to load */</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec2_fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_mec2.bin", chip_name);</div><div class='ctx'> 		if (!err) {</div><div class='ctx'> 			amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);</div><div class='ctx'> 			amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);</div><div class='hunk'>@@ -1434,45 +1648,18 @@ static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,</div><div class='del'>-				    volatile u32 *buffer)</div><div class='add'>+static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)</div><div class='ctx'> {</div><div class='del'>-	u32 count = 0, i;</div><div class='del'>-	const struct cs_section_def *sect = NULL;</div><div class='del'>-	const struct cs_extent_def *ext = NULL;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.rlc.cs_data == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> 	if (buffer == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-	buffer[count++] = cpu_to_le32(0x80000000);</div><div class='del'>-</div><div class='del'>-	for (sect = adev-&gt;gfx.rlc.cs_data; sect-&gt;section != NULL; ++sect) {</div><div class='del'>-		for (ext = sect-&gt;section; ext-&gt;extent != NULL; ++ext) {</div><div class='del'>-			if (sect-&gt;id == SECT_CONTEXT) {</div><div class='del'>-				buffer[count++] =</div><div class='del'>-					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext-&gt;reg_count));</div><div class='del'>-				buffer[count++] = cpu_to_le32(ext-&gt;reg_index -</div><div class='del'>-						PACKET3_SET_CONTEXT_REG_START);</div><div class='del'>-				for (i = 0; i &lt; ext-&gt;reg_count; i++)</div><div class='del'>-					buffer[count++] = cpu_to_le32(ext-&gt;extent[i]);</div><div class='del'>-			} else {</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);</div><div class='del'>-</div><div class='del'>-	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));</div><div class='del'>-	buffer[count++] = cpu_to_le32(0);</div><div class='add'>+	count = amdgpu_gfx_csb_preamble_start(buffer);</div><div class='add'>+	count = amdgpu_gfx_csb_data_parser(adev, buffer, count);</div><div class='add'>+	amdgpu_gfx_csb_preamble_end(buffer, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1994,12 +2181,40 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> 				hw_prio, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_sw_init(void *handle)</div><div class='add'>+static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);</div><div class='add'>+	uint32_t *ptr;</div><div class='add'>+	uint32_t inst;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for compute queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_9);</div><div class='add'>+	inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j, k, r, ring_id;</div><div class='ctx'> 	int xcc_id = 0;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	unsigned int hw_prio;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='hunk'>@@ -2018,6 +2233,43 @@ static int gfx_v9_0_sw_init(void *handle)</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(9, 0, 1):</div><div class='add'>+	case IP_VERSION(9, 2, 1):</div><div class='add'>+	case IP_VERSION(9, 4, 0):</div><div class='add'>+	case IP_VERSION(9, 2, 2):</div><div class='add'>+	case IP_VERSION(9, 1, 0):</div><div class='add'>+	case IP_VERSION(9, 3, 0):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.me_fw_version  &gt;= 167 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.pfp_fw_version &gt;= 196 &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.mec_fw_version &gt;= 474) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(9, 4, 2):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.mec_fw_version &gt;= 88) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='ctx'> 	adev-&gt;gfx.mec.num_queue_per_pipe = 8;</div><div class='ctx'> </div><div class='hunk'>@@ -2026,6 +2278,13 @@ static int gfx_v9_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	/* Bad opcode Event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR,</div><div class='add'>+			      &amp;adev-&gt;gfx.bad_op_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	/* Privileged reg */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,</div><div class='ctx'> 			      &amp;adev-&gt;gfx.priv_reg_irq);</div><div class='hunk'>@@ -2145,6 +2404,14 @@ static int gfx_v9_0_sw_init(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* TODO: Add queue reset mask when FW fully supports it */</div><div class='add'>+	adev-&gt;gfx.gfx_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.gfx_ring[0]);</div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+		adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("Failed to init KIQ BOs!\n");</div><div class='hunk'>@@ -2171,14 +2438,20 @@ static int gfx_v9_0_sw_init(void *handle)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gfx_v9_0_alloc_ip_dump(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gfx_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_sw_fini(void *handle)</div><div class='add'>+static int gfx_v9_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gfx.mcbp &amp;&amp; adev-&gt;gfx.num_gfx_rings) {</div><div class='ctx'> 		for (i = 0; i &lt; GFX9_NUM_SW_GFX_RINGS; i++)</div><div class='hunk'>@@ -2195,6 +2468,8 @@ static int gfx_v9_0_sw_fini(void *handle)</div><div class='ctx'> 	amdgpu_gfx_kiq_free_ring(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='ctx'> 	amdgpu_gfx_kiq_fini(adev, 0);</div><div class='ctx'> </div><div class='add'>+	amdgpu_gfx_cleaner_shader_sw_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	gfx_v9_0_mec_fini(adev);</div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.rlc.clear_state_obj,</div><div class='ctx'> 				&amp;adev-&gt;gfx.rlc.clear_state_gpu_addr,</div><div class='hunk'>@@ -2206,6 +2481,11 @@ static int gfx_v9_0_sw_fini(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> 	gfx_v9_0_free_microcode(adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_gfx_sysfs_fini(adev);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_core);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_compute_queues);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2369,6 +2649,9 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)</div><div class='ctx'> 				!READ_ONCE(adev-&gt;barrier_has_auto_waitcnt));</div><div class='ctx'> 		WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(9, 4, 2):</div><div class='add'>+		gfx_v9_4_2_init_sq(adev);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2379,7 +2662,10 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) {</div><div class='add'>+		WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	gfx_v9_0_tiling_mode_table_init(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2473,7 +2759,7 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);</div><div class='del'>-	if(adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings)</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);</div><div class='hunk'>@@ -2956,6 +3242,15 @@ static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);</div><div class='ctx'> </div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);</div><div class='hunk'>@@ -3037,8 +3332,8 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)</div><div class='ctx'> 	 * confirmed that the APU gfx10/gfx11 needn't such update.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU &amp;&amp;</div><div class='del'>-			adev-&gt;in_s3 &amp;&amp; !adev-&gt;suspend_complete) {</div><div class='del'>-		DRM_INFO(" Will skip the CSB packet resubmit\n");</div><div class='add'>+			adev-&gt;in_s3 &amp;&amp; !pm_resume_via_firmware()) {</div><div class='add'>+		DRM_INFO("Will skip the CSB packet resubmit\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);</div><div class='hunk'>@@ -3118,7 +3413,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring-&gt;wptr));</div><div class='ctx'> </div><div class='del'>-	/* set the wb address wether it's enabled or not */</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amp; CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);</div><div class='hunk'>@@ -3165,7 +3460,15 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,</div><div class='del'>-			(CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));</div><div class='add'>+				 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME1_HALT_MASK |</div><div class='add'>+				  CP_MEC_CNTL__MEC_ME2_HALT_MASK));</div><div class='ctx'> 		adev-&gt;gfx.kiq[0].ring.sched.ready = false;</div><div class='ctx'> 	}</div><div class='ctx'> 	udelay(50);</div><div class='hunk'>@@ -3223,9 +3526,7 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);</div><div class='ctx'> 	tmp &amp;= 0xffffff00;</div><div class='ctx'> 	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-	WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-	tmp |= 0x80;</div><div class='del'>-	WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+	WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)</div><div class='hunk'>@@ -3574,7 +3875,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='add'>+static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct v9_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='hunk'>@@ -3586,8 +3887,8 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> 	 */</div><div class='ctx'> 	tmp_mqd = (struct v9_mqd *)adev-&gt;gfx.mec.mqd_backup[mqd_idx];</div><div class='ctx'> </div><div class='del'>-	if (!tmp_mqd-&gt;cp_hqd_pq_control ||</div><div class='del'>-	    (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend)) {</div><div class='add'>+	if (!restore &amp;&amp; (!tmp_mqd-&gt;cp_hqd_pq_control ||</div><div class='add'>+	    (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend))) {</div><div class='ctx'> 		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));</div><div class='ctx'> 		((struct v9_mqd_allocation *)mqd)-&gt;dynamic_cu_mask = 0xFFFFFFFF;</div><div class='ctx'> 		((struct v9_mqd_allocation *)mqd)-&gt;dynamic_rb_mask = 0xFFFFFFFF;</div><div class='hunk'>@@ -3614,55 +3915,23 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-	if (unlikely(r != 0)) {</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gfx_v9_0_kiq_init_queue(ring);</div><div class='del'>-	amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-	ring-&gt;mqd_ptr = NULL;</div><div class='del'>-	amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+	gfx_v9_0_kiq_init_queue(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = NULL;</div><div class='del'>-	int r = 0, i;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v9_0_cp_compute_enable(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.compute_ring[i];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			goto done;</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v9_0_kcq_init_queue(ring);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+		r = gfx_v9_0_kcq_init_queue(&amp;adev-&gt;gfx.compute_ring[i], false);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_gfx_enable_kcq(adev, 0);</div><div class='del'>-done:</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_gfx_enable_kcq(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3686,6 +3955,10 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+		gfx_v9_0_cp_gfx_enable(adev, false);</div><div class='add'>+	gfx_v9_0_cp_compute_enable(adev, false);</div><div class='add'>+</div><div class='ctx'> 	r = gfx_v9_0_kiq_resume(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -3742,10 +4015,13 @@ static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 	gfx_v9_0_cp_compute_enable(adev, enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_hw_init(void *handle)</div><div class='add'>+static int gfx_v9_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_cleaner_shader_init(adev, adev-&gt;gfx.cleaner_shader_size,</div><div class='add'>+				       adev-&gt;gfx.cleaner_shader_ptr);</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 		gfx_v9_0_init_golden_registers(adev);</div><div class='hunk'>@@ -3762,20 +4038,22 @@ static int gfx_v9_0_hw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) &amp;&amp;</div><div class='add'>+	    !amdgpu_sriov_vf(adev))</div><div class='ctx'> 		gfx_v9_4_2_set_power_brake_sequence(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_hw_fini(void *handle)</div><div class='add'>+static int gfx_v9_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))</div><div class='ctx'> 		amdgpu_irq_put(adev, &amp;adev-&gt;gfx.cp_ecc_error_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* DF freeze and kcq disable will fail */</div><div class='ctx'> 	if (!amdgpu_ras_intr_triggered())</div><div class='hunk'>@@ -3819,19 +4097,19 @@ static int gfx_v9_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_suspend(void *handle)</div><div class='add'>+static int gfx_v9_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v9_0_hw_fini(handle);</div><div class='add'>+	return gfx_v9_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_resume(void *handle)</div><div class='add'>+static int gfx_v9_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v9_0_hw_init(handle);</div><div class='add'>+	return gfx_v9_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v9_0_is_idle(void *handle)</div><div class='add'>+static bool gfx_v9_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),</div><div class='ctx'> 				GRBM_STATUS, GUI_ACTIVE))</div><div class='hunk'>@@ -3840,24 +4118,24 @@ static bool gfx_v9_0_is_idle(void *handle)</div><div class='ctx'> 		return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (gfx_v9_0_is_idle(handle))</div><div class='add'>+		if (gfx_v9_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_soft_reset(void *handle)</div><div class='add'>+static int gfx_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* GRBM_STATUS */</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);</div><div class='hunk'>@@ -3896,19 +4174,17 @@ static int gfx_v9_0_soft_reset(void *handle)</div><div class='ctx'> 		/* Disable MEC parsing/prefetching */</div><div class='ctx'> 		gfx_v9_0_cp_compute_enable(adev, false);</div><div class='ctx'> </div><div class='del'>-		if (grbm_soft_reset) {</div><div class='del'>-			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='del'>-			tmp |= grbm_soft_reset;</div><div class='del'>-			dev_info(adev-&gt;dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='del'>-			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+		tmp |= grbm_soft_reset;</div><div class='add'>+		dev_info(adev-&gt;dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='del'>-			udelay(50);</div><div class='add'>+		udelay(50);</div><div class='ctx'> </div><div class='del'>-			tmp &amp;= ~grbm_soft_reset;</div><div class='del'>-			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='del'>-			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='del'>-		}</div><div class='add'>+		tmp &amp;= ~grbm_soft_reset;</div><div class='add'>+		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait a little for things to settle down */</div><div class='ctx'> 		udelay(50);</div><div class='hunk'>@@ -4507,15 +4783,15 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_early_init(void *handle)</div><div class='add'>+static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.funcs = &amp;gfx_v9_0_gfx_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -4539,9 +4815,9 @@ static int gfx_v9_0_early_init(void *handle)</div><div class='ctx'> 	return gfx_v9_0_init_microcode(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_ecc_late_init(void *handle)</div><div class='add'>+static int gfx_v9_0_ecc_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -4573,9 +4849,9 @@ static int gfx_v9_0_ecc_late_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_late_init(void *handle)</div><div class='add'>+static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='hunk'>@@ -4586,7 +4862,11 @@ static int gfx_v9_0_late_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = gfx_v9_0_ecc_late_init(handle);</div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = gfx_v9_0_ecc_late_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -4679,8 +4959,6 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t data, def;</div><div class='ctx'> </div><div class='del'>-	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='del'>-</div><div class='ctx'> 	/* It is disabled by HW by default */</div><div class='ctx'> 	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_MGCG)) {</div><div class='ctx'> 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */</div><div class='hunk'>@@ -4745,8 +5023,6 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,</div><div class='hunk'>@@ -4757,8 +5033,6 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!adev-&gt;gfx.num_gfx_rings)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='del'>-</div><div class='ctx'> 	/* Enable 3D CGCG/CGLS */</div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* write cmd to clear cgcg/cgls ov */</div><div class='hunk'>@@ -4800,8 +5074,6 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 		if (def != data)</div><div class='ctx'> 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,</div><div class='hunk'>@@ -4809,8 +5081,6 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t def, data;</div><div class='ctx'> </div><div class='del'>-	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='del'>-</div><div class='ctx'> 	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGCG)) {</div><div class='ctx'> 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);</div><div class='ctx'> 		/* unset CGCG override */</div><div class='hunk'>@@ -4852,13 +5122,12 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev</div><div class='ctx'> 		if (def != data)</div><div class='ctx'> 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 					    bool enable)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* CGCG/CGLS should be enabled after MGCG/MGLS</div><div class='ctx'> 		 * ===  MGCG + MGLS ===</div><div class='hunk'>@@ -4878,6 +5147,7 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 		/* ===  MGCG + MGLS === */</div><div class='ctx'> 		gfx_v9_0_update_medium_grain_clock_gating(adev, enable);</div><div class='ctx'> 	}</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4955,10 +5225,10 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {</div><div class='ctx'> 	.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='hunk'>@@ -4966,7 +5236,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,</div><div class='ctx'> 	case IP_VERSION(9, 1, 0):</div><div class='ctx'> 	case IP_VERSION(9, 3, 0):</div><div class='ctx'> 		if (!enable)</div><div class='del'>-			amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+			amdgpu_gfx_off_ctrl_immediate(adev, false);</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_RLC_SMU_HS) {</div><div class='ctx'> 			gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);</div><div class='hunk'>@@ -4988,10 +5258,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,</div><div class='ctx'> 		gfx_v9_0_update_gfx_mg_power_gating(adev, enable);</div><div class='ctx'> </div><div class='ctx'> 		if (enable)</div><div class='del'>-			amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+			amdgpu_gfx_off_ctrl_immediate(adev, true);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 2, 1):</div><div class='del'>-		amdgpu_gfx_off_ctrl(adev, enable);</div><div class='add'>+		amdgpu_gfx_off_ctrl_immediate(adev, enable);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -5000,10 +5270,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -5026,9 +5296,9 @@ static int gfx_v9_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gfx_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -5193,16 +5463,8 @@ static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 	payload_size = sizeof(struct v9_ce_ib_state);</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-					  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v9_gfx_meta_data, ce_payload);</div><div class='del'>-		ce_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);</div><div class='del'>-	} else {</div><div class='del'>-		payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload);</div><div class='del'>-		ce_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + payload_offset;</div><div class='del'>-	}</div><div class='add'>+	payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload);</div><div class='add'>+	ce_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + payload_offset;</div><div class='ctx'> </div><div class='ctx'> 	if (offset + (payload_size &gt;&gt; 2) &lt;= ring-&gt;buf_mask + 1) {</div><div class='ctx'> 		memcpy((void *)&amp;ring-&gt;ring[offset], ce_payload_cpu_addr, payload_size);</div><div class='hunk'>@@ -5225,16 +5487,8 @@ static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 	payload_size = sizeof(struct v9_de_ib_state);</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-					  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);</div><div class='del'>-	} else {</div><div class='del'>-		payload_offset = offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + payload_offset;</div><div class='del'>-	}</div><div class='add'>+	payload_offset = offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='add'>+	de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + payload_offset;</div><div class='ctx'> </div><div class='ctx'> 	((struct v9_de_ib_state *)de_payload_cpu_addr)-&gt;ib_completion_status =</div><div class='ctx'> 		IB_COMPLETION_STATUS_PREEMPTED;</div><div class='hunk'>@@ -5424,19 +5678,9 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)</div><div class='ctx'> </div><div class='ctx'> 	cnt = (sizeof(ce_payload) &gt;&gt; 2) + 4 - 2;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v9_gfx_meta_data, ce_payload);</div><div class='del'>-		ce_payload_gpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ce_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-	} else {</div><div class='del'>-		offset = offsetof(struct v9_gfx_meta_data, ce_payload);</div><div class='del'>-		ce_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='del'>-		ce_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='del'>-	}</div><div class='add'>+	offset = offsetof(struct v9_gfx_meta_data, ce_payload);</div><div class='add'>+	ce_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='add'>+	ce_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));</div><div class='ctx'> 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |</div><div class='hunk'>@@ -5522,28 +5766,13 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bo</div><div class='ctx'> 	void *de_payload_cpu_addr;</div><div class='ctx'> 	int cnt;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gfx_meta_data) +</div><div class='del'>-			offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_gpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		de_payload_cpu_addr =</div><div class='del'>-			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		offset = offsetof(struct amdgpu_mes_ctx_meta_data,</div><div class='del'>-				  gfx[0].gds_backup) +</div><div class='del'>-			offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='del'>-		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-	} else {</div><div class='del'>-		offset = offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='del'>-		de_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='del'>-		de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='add'>+	offset = offsetof(struct v9_gfx_meta_data, de_payload);</div><div class='add'>+	de_payload_gpu_addr = amdgpu_csa_vaddr(ring-&gt;adev) + offset;</div><div class='add'>+	de_payload_cpu_addr = adev-&gt;virt.csa_cpu_addr + offset;</div><div class='ctx'> </div><div class='del'>-		gds_addr = ALIGN(amdgpu_csa_vaddr(ring-&gt;adev) +</div><div class='del'>-				 AMDGPU_CSA_SIZE - adev-&gt;gds.gds_size,</div><div class='del'>-				 PAGE_SIZE);</div><div class='del'>-	}</div><div class='add'>+	gds_addr = ALIGN(amdgpu_csa_vaddr(ring-&gt;adev) +</div><div class='add'>+			 AMDGPU_CSA_SIZE - adev-&gt;gds.gds_size,</div><div class='add'>+			 PAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	if (usegds) {</div><div class='ctx'> 		de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);</div><div class='hunk'>@@ -5697,7 +5926,9 @@ static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)</div><div class='ctx'> 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);</div><div class='ctx'> 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);</div><div class='ctx'> 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='ctx'> 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='hunk'>@@ -5768,17 +5999,95 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 gfx_v9_0_get_cpc_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				     int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * amdgpu controls only the first MEC. That's why this function only</div><div class='add'>+	 * handles the setting of interrupts for this specific MEC. All other</div><div class='add'>+	 * pipes' interrupts are set by amdkfd.</div><div class='add'>+	 */</div><div class='add'>+	if (me != 1)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);</div><div class='add'>+	case 2:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);</div><div class='add'>+	case 3:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 					     struct amdgpu_irq_src *source,</div><div class='ctx'> 					     unsigned type,</div><div class='ctx'> 					     enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='ctx'> 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,</div><div class='ctx'> 			       PRIV_REG_INT_ENABLE,</div><div class='ctx'> 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    PRIV_REG_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					   struct amdgpu_irq_src *source,</div><div class='add'>+					   unsigned type,</div><div class='add'>+					   enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 cp_int_cntl_reg, cp_int_cntl;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,</div><div class='add'>+			       OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				/* MECs start at 1 */</div><div class='add'>+				cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j);</div><div class='add'>+</div><div class='add'>+				if (cp_int_cntl_reg) {</div><div class='add'>+					cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);</div><div class='add'>+					cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+								    OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+								    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -5960,6 +6269,15 @@ static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v9_0_bad_op_irq(struct amdgpu_device *adev,</div><div class='add'>+			       struct amdgpu_irq_src *source,</div><div class='add'>+			       struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal opcode in command stream\n");</div><div class='add'>+	gfx_v9_0_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				  struct amdgpu_irq_src *source,</div><div class='ctx'> 				  struct amdgpu_iv_entry *entry)</div><div class='hunk'>@@ -6840,6 +7158,230 @@ static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)</div><div class='add'>+{</div><div class='add'>+	/* Header itself is a NOP packet */</div><div class='add'>+	if (num_nop == 1) {</div><div class='add'>+		amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));</div><div class='add'>+</div><div class='add'>+	/* Header is at index 0, followed by num_nops - 1 NOP packet's */</div><div class='add'>+	amdgpu_ring_insert_nop(ring, num_nop - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,</div><div class='add'>+			      unsigned int vmid,</div><div class='add'>+			      struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;unmap_queues_size)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,</div><div class='add'>+				   0, 0);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* make sure dequeue is complete*/</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc15_grbm_select(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, 0, 0);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to wait on hqd deactive\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v9_0_kcq_init_queue(ring, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to init kcq\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size);</div><div class='add'>+	if (r) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, ring);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("fail to remap queue\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+			   gc_reg_list_9[i].reg_name,</div><div class='add'>+			   adev-&gt;gfx.ip_dump_core[i]);</div><div class='add'>+</div><div class='add'>+	/* print compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_9);</div><div class='add'>+	drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   adev-&gt;gfx.mec.num_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_pipe_per_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					if (i &amp;&amp; gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+						drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+							   "mmCP_MEC_ME2_HEADER_DUMP",</div><div class='add'>+							   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+					else</div><div class='add'>+						drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+							   gc_cp_reg_list_9[reg].reg_name,</div><div class='add'>+							   adev-&gt;gfx.ip_dump_compute_queues[index + reg]);</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k, reg, index = 0;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core || !adev-&gt;gfx.num_gfx_rings)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+		adev-&gt;gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i]));</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+	/* dump compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_9);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+			for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+				/* ME0 is for GFX so start from 1 for CP */</div><div class='add'>+				soc15_grbm_select(adev, 1 + i, j, k, 0, 0);</div><div class='add'>+</div><div class='add'>+				for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+					if (i &amp;&amp; gc_cp_reg_list_9[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+						adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+							RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));</div><div class='add'>+					else</div><div class='add'>+						adev-&gt;gfx.ip_dump_compute_queues[index + reg] =</div><div class='add'>+							RREG32(SOC15_REG_ENTRY_OFFSET(</div><div class='add'>+								       gc_cp_reg_list_9[reg]));</div><div class='add'>+				}</div><div class='add'>+				index += reg_count;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* Emit the cleaner shader */</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))</div><div class='add'>+		amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));</div><div class='add'>+	else</div><div class='add'>+		amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER_9_0, 0));</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_0_ring_begin_use_compute(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_ip_block *gfx_block =</div><div class='add'>+		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_begin_use(ring);</div><div class='add'>+</div><div class='add'>+	/* Raven and PCO APUs seem to have stability issues</div><div class='add'>+	 * with compute and gfxoff and gfx pg.  Disable gfx pg during</div><div class='add'>+	 * submission and allow again afterwards.</div><div class='add'>+	 */</div><div class='add'>+	if (gfx_block &amp;&amp; amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0))</div><div class='add'>+		gfx_v9_0_set_powergating_state(gfx_block, AMD_PG_STATE_UNGATE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_0_ring_end_use_compute(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_ip_block *gfx_block =</div><div class='add'>+		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);</div><div class='add'>+</div><div class='add'>+	/* Raven and PCO APUs seem to have stability issues</div><div class='add'>+	 * with compute and gfxoff and gfx pg.  Disable gfx pg during</div><div class='add'>+	 * submission and allow again afterwards.</div><div class='add'>+	 */</div><div class='add'>+	if (gfx_block &amp;&amp; amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0))</div><div class='add'>+		gfx_v9_0_set_powergating_state(gfx_block, AMD_PG_STATE_GATE);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_enforce_isolation_ring_end_use(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {</div><div class='ctx'> 	.name = "gfx_v9_0",</div><div class='ctx'> 	.early_init = gfx_v9_0_early_init,</div><div class='hunk'>@@ -6856,6 +7398,8 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = gfx_v9_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gfx_v9_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = gfx_v9_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = gfx_v9_ip_dump,</div><div class='add'>+	.print_ip_state = gfx_v9_ip_print,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {</div><div class='hunk'>@@ -6887,7 +7431,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {</div><div class='ctx'> 		5 + /* HDP_INVL */</div><div class='ctx'> 		8 + 8 + /* FENCE x2 */</div><div class='ctx'> 		2 + /* SWITCH_BUFFER */</div><div class='del'>-		7, /* gfx_v9_0_emit_mem_sync */</div><div class='add'>+		7 + /* gfx_v9_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v9_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_gfx */</div><div class='ctx'> 	.emit_ib = gfx_v9_0_ring_emit_ib_gfx,</div><div class='ctx'> 	.emit_fence = gfx_v9_0_ring_emit_fence,</div><div class='hunk'>@@ -6896,7 +7441,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,</div><div class='ctx'> 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v9_0_ring_test_ring,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v9_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_switch_buffer = gfx_v9_ring_emit_sb,</div><div class='ctx'> 	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,</div><div class='hunk'>@@ -6908,6 +7453,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,</div><div class='ctx'> 	.soft_recovery = gfx_v9_0_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,</div><div class='add'>+	.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,</div><div class='add'>+	.end_use = amdgpu_gfx_enforce_isolation_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {</div><div class='hunk'>@@ -6940,7 +7488,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {</div><div class='ctx'> 		5 + /* HDP_INVL */</div><div class='ctx'> 		8 + 8 + /* FENCE x2 */</div><div class='ctx'> 		2 + /* SWITCH_BUFFER */</div><div class='del'>-		7, /* gfx_v9_0_emit_mem_sync */</div><div class='add'>+		7 + /* gfx_v9_0_emit_mem_sync */</div><div class='add'>+		2, /* gfx_v9_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_gfx */</div><div class='ctx'> 	.emit_ib = gfx_v9_0_ring_emit_ib_gfx,</div><div class='ctx'> 	.emit_fence = gfx_v9_0_ring_emit_fence,</div><div class='hunk'>@@ -6950,7 +7499,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v9_0_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v9_0_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_sw_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v9_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_switch_buffer = gfx_v9_ring_emit_sb,</div><div class='ctx'> 	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,</div><div class='hunk'>@@ -6964,6 +7513,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {</div><div class='ctx'> 	.patch_cntl = gfx_v9_0_ring_patch_cntl,</div><div class='ctx'> 	.patch_de = gfx_v9_0_ring_patch_de_meta,</div><div class='ctx'> 	.patch_ce = gfx_v9_0_ring_patch_ce_meta,</div><div class='add'>+	.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,</div><div class='add'>+	.end_use = amdgpu_gfx_enforce_isolation_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {</div><div class='hunk'>@@ -6981,11 +7533,11 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {</div><div class='ctx'> 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='del'>-		2 + /* gfx_v9_0_ring_emit_vm_flush */</div><div class='ctx'> 		8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */</div><div class='ctx'> 		7 + /* gfx_v9_0_emit_mem_sync */</div><div class='ctx'> 		5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */</div><div class='del'>-		15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */</div><div class='add'>+		15 + /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */</div><div class='add'>+		2, /* gfx_v9_0_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v9_0_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,</div><div class='ctx'> 	.emit_fence = gfx_v9_0_ring_emit_fence,</div><div class='hunk'>@@ -6995,13 +7547,18 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v9_0_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v9_0_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v9_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_wreg = gfx_v9_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.soft_recovery = gfx_v9_0_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,</div><div class='ctx'> 	.emit_wave_limit = gfx_v9_0_emit_wave_limit,</div><div class='add'>+	.reset = gfx_v9_0_reset_kcq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = gfx_v9_0_ring_begin_use_compute,</div><div class='add'>+	.end_use = gfx_v9_0_ring_end_use_compute,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {</div><div class='hunk'>@@ -7019,7 +7576,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {</div><div class='ctx'> 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +</div><div class='del'>-		2 + /* gfx_v9_0_ring_emit_vm_flush */</div><div class='ctx'> 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v9_0_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_fence = gfx_v9_0_ring_emit_fence_kiq,</div><div class='hunk'>@@ -7030,6 +7586,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {</div><div class='ctx'> 	.emit_wreg = gfx_v9_0_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -7060,6 +7617,11 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {</div><div class='ctx'> 	.process = gfx_v9_0_priv_reg_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v9_0_bad_op_irq_funcs = {</div><div class='add'>+	.set = gfx_v9_0_set_bad_op_fault_state,</div><div class='add'>+	.process = gfx_v9_0_bad_op_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {</div><div class='ctx'> 	.set = gfx_v9_0_set_priv_inst_fault_state,</div><div class='ctx'> 	.process = gfx_v9_0_priv_inst_irq,</div><div class='hunk'>@@ -7079,6 +7641,9 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.funcs = &amp;gfx_v9_0_priv_reg_irq_funcs;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.bad_op_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.bad_op_irq.funcs = &amp;gfx_v9_0_bad_op_irq_funcs;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.funcs = &amp;gfx_v9_0_priv_inst_irq_funcs;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h<br/>new file mode 100644<br/>index 000000000000..0b6bd09b7529<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+/* Define the cleaner shader gfx_9_0 */</div><div class='add'>+static const u32 __maybe_unused gfx_9_0_cleaner_shader_hex[] = {</div><div class='add'>+	/* Add the cleaner shader code here */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Define the cleaner shader gfx_9_4_2 */</div><div class='add'>+static const u32 gfx_9_4_2_cleaner_shader_hex[] = {</div><div class='add'>+	0xbf068100, 0xbf84003b,</div><div class='add'>+	0xbf8a0000, 0xb07c0000,</div><div class='add'>+	0xbe8200ff, 0x00000078,</div><div class='add'>+	0xbf110802, 0x7e000280,</div><div class='add'>+	0x7e020280, 0x7e040280,</div><div class='add'>+	0x7e060280, 0x7e080280,</div><div class='add'>+	0x7e0a0280, 0x7e0c0280,</div><div class='add'>+	0x7e0e0280, 0x80828802,</div><div class='add'>+	0xbe803202, 0xbf84fff5,</div><div class='add'>+	0xbf9c0000, 0xbe8200ff,</div><div class='add'>+	0x80000000, 0x86020102,</div><div class='add'>+	0xbf840011, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xd28c0001,</div><div class='add'>+	0x0001007f, 0xd28d0001,</div><div class='add'>+	0x0002027e, 0x10020288,</div><div class='add'>+	0xbe8200bf, 0xbefc00c1,</div><div class='add'>+	0xd89c2000, 0x00020201,</div><div class='add'>+	0xd89c6040, 0x00040401,</div><div class='add'>+	0x320202ff, 0x00000400,</div><div class='add'>+	0x80828102, 0xbf84fff8,</div><div class='add'>+	0xbefc00ff, 0x0000005c,</div><div class='add'>+	0xbf800000, 0xbe802c80,</div><div class='add'>+	0xbe812c80, 0xbe822c80,</div><div class='add'>+	0xbe832c80, 0x80fc847c,</div><div class='add'>+	0xbf84fffa, 0xbee60080,</div><div class='add'>+	0xbee70080, 0xbeea0180,</div><div class='add'>+	0xbeec0180, 0xbeee0180,</div><div class='add'>+	0xbef00180, 0xbef20180,</div><div class='add'>+	0xbef40180, 0xbef60180,</div><div class='add'>+	0xbef80180, 0xbefa0180,</div><div class='add'>+	0xbf810000, 0xbf8d0001,</div><div class='add'>+	0xbefc00ff, 0x0000005c,</div><div class='add'>+	0xbf800000, 0xbe802c80,</div><div class='add'>+	0xbe812c80, 0xbe822c80,</div><div class='add'>+	0xbe832c80, 0x80fc847c,</div><div class='add'>+	0xbf84fffa, 0xbee60080,</div><div class='add'>+	0xbee70080, 0xbeea01ff,</div><div class='add'>+	0x000000ee, 0xbf810000,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c<br/>index f53b379d8971..6028afd81690 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c</a></div><div class='hunk'>@@ -27,7 +27,6 @@</div><div class='ctx'> #include "amdgpu_gfx.h"</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "soc15d.h"</div><div class='del'>-#include "amdgpu_atomfirmware.h"</div><div class='ctx'> #include "amdgpu_pm.h"</div><div class='ctx'> </div><div class='ctx'> #include "gc/gc_9_4_1_offset.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c<br/>index 065b2bd5f5a6..8058ea91ecaf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c</a></div><div class='hunk'>@@ -412,7 +412,7 @@ static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,</div><div class='ctx'> 	r = amdgpu_ib_schedule(ring, 1, ib, NULL, fence_ptr);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "ib submit failed (%d).\n", r);</div><div class='del'>-		amdgpu_ib_free(adev, ib, NULL);</div><div class='add'>+		amdgpu_ib_free(ib, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -611,16 +611,16 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> disp2_failed:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;disp_ibs[2], NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;disp_ibs[2], NULL);</div><div class='ctx'> 	dma_fence_put(fences[2]);</div><div class='ctx'> disp1_failed:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;disp_ibs[1], NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;disp_ibs[1], NULL);</div><div class='ctx'> 	dma_fence_put(fences[1]);</div><div class='ctx'> disp0_failed:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;disp_ibs[0], NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;disp_ibs[0], NULL);</div><div class='ctx'> 	dma_fence_put(fences[0]);</div><div class='ctx'> pro_end:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;wb_ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;wb_ib, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (r)</div><div class='ctx'> 		dev_info(adev-&gt;dev, "Init SGPRS Failed\n");</div><div class='hunk'>@@ -687,10 +687,10 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> disp_failed:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;disp_ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;disp_ib, NULL);</div><div class='ctx'> 	dma_fence_put(fence);</div><div class='ctx'> pro_end:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;wb_ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;wb_ib, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (r)</div><div class='ctx'> 		dev_info(adev-&gt;dev, "Init VGPRS Failed\n");</div><div class='hunk'>@@ -748,6 +748,18 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void gfx_v9_4_2_init_sq(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.mec_fw_version &gt;= 98) {</div><div class='add'>+		adev-&gt;gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN;</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regSQ_CONFIG1);</div><div class='add'>+		data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regSQ_CONFIG1, data);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,</div><div class='ctx'> 				uint32_t first_vmid,</div><div class='ctx'> 				uint32_t last_vmid)</div><div class='hunk'>@@ -1547,7 +1559,7 @@ static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t bank, way, mem;</div><div class='ctx'> 	static const char * const vml2_way_str[] = { "BIGK", "4K" };</div><div class='del'>-	static const char * const utcl2_rounter_str[] = { "VMC", "APT" };</div><div class='add'>+	static const char * const utcl2_router_str[] = { "VMC", "APT" };</div><div class='ctx'> </div><div class='ctx'> 	mem = instance % blk-&gt;num_mem_blocks;</div><div class='ctx'> 	way = (instance / blk-&gt;num_mem_blocks) % blk-&gt;num_ways;</div><div class='hunk'>@@ -1568,7 +1580,7 @@ static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev,</div><div class='ctx'> 		dev_info(</div><div class='ctx'> 			adev-&gt;dev,</div><div class='ctx'> 			"GFX SubBlock UTCL2_ROUTER_IFIF%d_GROUP0_%s, SED %d, DED %d\n",</div><div class='del'>-			bank, utcl2_rounter_str[mem], sec_cnt, ded_cnt);</div><div class='add'>+			bank, utcl2_router_str[mem], sec_cnt, ded_cnt);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ATC_L2_CACHE_2M:</div><div class='ctx'> 		dev_info(</div><div class='hunk'>@@ -1909,18 +1921,7 @@ static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev)</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v9_4_2_query_uctl2_poison_status(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	u32 status = 0;</div><div class='del'>-	struct amdgpu_vmhub *hub;</div><div class='del'>-</div><div class='del'>-	hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='del'>-	status = RREG32(hub-&gt;vm_l2_pro_fault_status);</div><div class='del'>-	/* reset page fault status */</div><div class='del'>-	WREG32_P(hub-&gt;vm_l2_pro_fault_cntl, 1, ~1);</div><div class='ctx'> </div><div class='del'>-	return REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_ras_block_hw_ops  gfx_v9_4_2_ras_ops = {</div><div class='ctx'> 		.query_ras_error_count = &amp;gfx_v9_4_2_query_ras_error_count,</div><div class='hunk'>@@ -1934,5 +1935,4 @@ struct amdgpu_gfx_ras gfx_v9_4_2_ras = {</div><div class='ctx'> 		.hw_ops = &amp;gfx_v9_4_2_ras_ops,</div><div class='ctx'> 	},</div><div class='ctx'> 	.enable_watchdog_timer = &amp;gfx_v9_4_2_enable_watchdog_timer,</div><div class='del'>-	.query_utcl2_poison_status = gfx_v9_4_2_query_uctl2_poison_status,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h<br/>index 7584624b641c..a603724c1dfc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h</a></div><div class='hunk'>@@ -28,6 +28,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,</div><div class='ctx'> 				uint32_t first_vmid, uint32_t last_vmid);</div><div class='ctx'> void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,</div><div class='ctx'> 				      uint32_t die_id);</div><div class='add'>+void gfx_v9_4_2_init_sq(struct amdgpu_device *adev);</div><div class='ctx'> void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);</div><div class='ctx'> int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm<br/>new file mode 100644<br/>index 000000000000..35b8cf9070bd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm</a></div><div class='hunk'>@@ -0,0 +1,153 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+// This shader is to clean LDS, SGPRs and VGPRs. It is  first 64 Dwords or 256 bytes of 192 Dwords cleaner shader.</div><div class='add'>+//To turn this shader program on for complitaion change this to main and lower shader main to main_1</div><div class='add'>+</div><div class='add'>+// MI200 : Clear SGPRs, VGPRs and LDS</div><div class='add'>+//   Uses two kernels launched separately:</div><div class='add'>+//   1. Clean VGPRs, LDS, and lower SGPRs</div><div class='add'>+//        Launches one workgroup per CU, each workgroup with 4x wave64 per SIMD in the CU</div><div class='add'>+//        Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs per SIMD</div><div class='add'>+//        Waves in the workgroup share the 64KB of LDS</div><div class='add'>+//        Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-383</div><div class='add'>+//        Each wave clears 128 VGPRs, so all 512 in the SIMD</div><div class='add'>+//        The first wave of the workgroup clears its 64KB of LDS</div><div class='add'>+//        The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup</div><div class='add'>+//          before any wave in the workgroup could end.  Without this, it is possible not all SGPRs get cleared.</div><div class='add'>+//    2. Clean remaining SGPRs</div><div class='add'>+//        Launches a workgroup with 24 waves per workgroup, yielding 6 waves per SIMD in each CU</div><div class='add'>+//        Waves are allocating 96 SGPRs</div><div class='add'>+//          CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves from allocating SGPRs 0-223.</div><div class='add'>+//          As such, these 6 waves per SIMD are allocated physical SGPRs 224-799</div><div class='add'>+//        Barriers do not work for &gt;16 waves per workgroup, so we cannot start with S_BARRIER</div><div class='add'>+//          Instead, the shader starts with an S_SETHALT 1. Once all waves are launched CP will send unhalt command</div><div class='add'>+//        The shader then clears all SGPRs allocated to it, cleaning out physical SGPRs 224-799</div><div class='add'>+</div><div class='add'>+shader main</div><div class='add'>+  asic(MI200)</div><div class='add'>+  type(CS)</div><div class='add'>+  wave_size(64)</div><div class='add'>+// Note: original source code from SQ team</div><div class='add'>+</div><div class='add'>+//   (theorhetical fastest = ~512clks vgpr + 1536 lds + ~128 sgpr  = 2176 clks)</div><div class='add'>+</div><div class='add'>+  s_cmp_eq_u32 s0, 1                                // Bit0 is set, sgpr0 is set then clear VGPRS and LDS as FW set COMPUTE_USER_DATA_3</div><div class='add'>+  s_cbranch_scc0  label_0023                        // Clean VGPRs and LDS if sgpr0 of wave is set, scc = (s3 == 1)</div><div class='add'>+  S_BARRIER</div><div class='add'>+</div><div class='add'>+  s_movk_i32    m0, 0x0000</div><div class='add'>+  s_mov_b32     s2, 0x00000078  // Loop 128/8=16 times  (loop unrolled for performance)</div><div class='add'>+  //</div><div class='add'>+  // CLEAR VGPRs</div><div class='add'>+  //</div><div class='add'>+  s_set_gpr_idx_on  s2, 0x8    // enable Dest VGPR indexing</div><div class='add'>+label_0005:</div><div class='add'>+  v_mov_b32     v0, 0</div><div class='add'>+  v_mov_b32     v1, 0</div><div class='add'>+  v_mov_b32     v2, 0</div><div class='add'>+  v_mov_b32     v3, 0</div><div class='add'>+  v_mov_b32     v4, 0</div><div class='add'>+  v_mov_b32     v5, 0</div><div class='add'>+  v_mov_b32     v6, 0</div><div class='add'>+  v_mov_b32     v7, 0</div><div class='add'>+  s_sub_u32     s2, s2, 8</div><div class='add'>+  s_set_gpr_idx_idx  s2</div><div class='add'>+  s_cbranch_scc0  label_0005</div><div class='add'>+  s_set_gpr_idx_off</div><div class='add'>+</div><div class='add'>+  //</div><div class='add'>+  //</div><div class='add'>+</div><div class='add'>+  s_mov_b32     s2, 0x80000000                      // Bit31 is first_wave</div><div class='add'>+  s_and_b32     s2, s2, s1                          // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set</div><div class='add'>+  s_cbranch_scc0  label_clean_sgpr_1                // Clean LDS if its first wave of ThreadGroup/WorkGroup</div><div class='add'>+  // CLEAR LDS</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32 exec_lo, 0xffffffff</div><div class='add'>+  s_mov_b32 exec_hi, 0xffffffff</div><div class='add'>+  v_mbcnt_lo_u32_b32  v1, exec_hi, 0          // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mbcnt_hi_u32_b32  v1, exec_lo, v1         // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mul_u32_u24  v1, 0x00000008, v1           // * 8, so each thread is a double-dword address (8byte)</div><div class='add'>+  s_mov_b32     s2, 0x00000003f               // 64 loop iterations</div><div class='add'>+  s_mov_b32     m0, 0xffffffff</div><div class='add'>+  // Clear all of LDS space</div><div class='add'>+  // Each FirstWave of WorkGroup clears 64kbyte block</div><div class='add'>+</div><div class='add'>+label_001F:</div><div class='add'>+  ds_write2_b64  v1, v[2:3], v[2:3] offset1:32</div><div class='add'>+  ds_write2_b64  v1, v[4:5], v[4:5] offset0:64 offset1:96</div><div class='add'>+  v_add_co_u32     v1, vcc, 0x00000400, v1</div><div class='add'>+  s_sub_u32     s2, s2, 1</div><div class='add'>+  s_cbranch_scc0  label_001F</div><div class='add'>+  //</div><div class='add'>+  // CLEAR SGPRs</div><div class='add'>+  //</div><div class='add'>+label_clean_sgpr_1:</div><div class='add'>+  s_mov_b32     m0, 0x0000005c   // Loop 96/4=24 times  (loop unrolled for performance)</div><div class='add'>+  s_nop 0</div><div class='add'>+label_sgpr_loop:</div><div class='add'>+  s_movreld_b32     s0, 0</div><div class='add'>+  s_movreld_b32     s1, 0</div><div class='add'>+  s_movreld_b32     s2, 0</div><div class='add'>+  s_movreld_b32     s3, 0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop</div><div class='add'>+</div><div class='add'>+  //clear vcc, flat scratch</div><div class='add'>+  s_mov_b32 flat_scratch_lo, 0   //clear  flat scratch lo SGPR</div><div class='add'>+  s_mov_b32 flat_scratch_hi, 0   //clear  flat scratch hi SGPR</div><div class='add'>+  s_mov_b64 vcc, 0               //clear vcc</div><div class='add'>+  s_mov_b64 ttmp0, 0             //Clear ttmp0 and ttmp1</div><div class='add'>+  s_mov_b64 ttmp2, 0             //Clear ttmp2 and ttmp3</div><div class='add'>+  s_mov_b64 ttmp4, 0             //Clear ttmp4 and ttmp5</div><div class='add'>+  s_mov_b64 ttmp6, 0             //Clear ttmp6 and ttmp7</div><div class='add'>+  s_mov_b64 ttmp8, 0             //Clear ttmp8 and ttmp9</div><div class='add'>+  s_mov_b64 ttmp10, 0            //Clear ttmp10 and ttmp11</div><div class='add'>+  s_mov_b64 ttmp12, 0            //Clear ttmp12 and ttmp13</div><div class='add'>+  s_mov_b64 ttmp14, 0            //Clear ttmp14 and ttmp15</div><div class='add'>+s_endpgm</div><div class='add'>+</div><div class='add'>+label_0023:</div><div class='add'>+</div><div class='add'>+  s_sethalt 1</div><div class='add'>+</div><div class='add'>+  s_mov_b32     m0, 0x0000005c   // Loop 96/4=24 times  (loop unrolled for performance)</div><div class='add'>+  s_nop 0</div><div class='add'>+label_sgpr_loop1:</div><div class='add'>+</div><div class='add'>+  s_movreld_b32     s0, 0</div><div class='add'>+  s_movreld_b32     s1, 0</div><div class='add'>+  s_movreld_b32     s2, 0</div><div class='add'>+  s_movreld_b32     s3, 0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop1</div><div class='add'>+</div><div class='add'>+  //clear vcc, flat scratch</div><div class='add'>+  s_mov_b32 flat_scratch_lo, 0   //clear  flat scratch lo SGPR</div><div class='add'>+  s_mov_b32 flat_scratch_hi, 0   //clear  flat scratch hi SGPR</div><div class='add'>+  s_mov_b64 vcc, 0xee            //clear vcc</div><div class='add'>+</div><div class='add'>+s_endpgm</div><div class='add'>+end</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c<br/>index b53c8fd4e8cf..cbb74ffc4792 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c</a></div><div class='hunk'>@@ -37,11 +37,18 @@</div><div class='ctx'> #include "gc/gc_9_4_3_sh_mask.h"</div><div class='ctx'> </div><div class='ctx'> #include "gfx_v9_4_3.h"</div><div class='add'>+#include "gfx_v9_4_3_cleaner_shader.h"</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='ctx'> #include "amdgpu_aca.h"</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin");</div><div class='ctx'> </div><div class='ctx'> #define GFX9_MEC_HPD_SIZE 4096</div><div class='ctx'> #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L</div><div class='hunk'>@@ -49,9 +56,110 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");</div><div class='ctx'> #define GOLDEN_GB_ADDR_CONFIG 0x2a114042</div><div class='ctx'> #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301</div><div class='ctx'> </div><div class='del'>-#define mmSMNAID_XCD0_MCA_SMU 0x36430400	/* SMN AID XCD0 */</div><div class='del'>-#define mmSMNAID_XCD1_MCA_SMU 0x38430400	/* SMN AID XCD1 */</div><div class='del'>-#define mmSMNXCD_XCD0_MCA_SMU 0x40430400	/* SMN XCD XCD0 */</div><div class='add'>+#define XCC_REG_RANGE_0_LOW  0x2000     /* XCC gfxdec0 lower Bound */</div><div class='add'>+#define XCC_REG_RANGE_0_HIGH 0x3400     /* XCC gfxdec0 upper Bound */</div><div class='add'>+#define XCC_REG_RANGE_1_LOW  0xA000     /* XCC gfxdec1 lower Bound */</div><div class='add'>+#define XCC_REG_RANGE_1_HIGH 0x10000    /* XCC gfxdec1 upper Bound */</div><div class='add'>+</div><div class='add'>+#define NORMALIZE_XCC_REG_OFFSET(offset) \</div><div class='add'>+	(offset &amp; 0xFFFF)</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6),</div><div class='add'>+	/* SE status registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = {</div><div class='add'>+	/* compute queue registers */</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_gfx_ras gfx_v9_4_3_ras;</div><div class='ctx'> </div><div class='hunk'>@@ -61,10 +169,18 @@ static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);</div><div class='ctx'> static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,</div><div class='ctx'> 				struct amdgpu_cu_info *cu_info);</div><div class='add'>+static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id);</div><div class='add'>+static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 				uint64_t queue_mask)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	u64 shader_mc_addr;</div><div class='add'>+</div><div class='add'>+	/* Cleaner shader MC address */</div><div class='add'>+	shader_mc_addr = adev-&gt;gfx.cleaner_shader_gpu_addr &gt;&gt; 8;</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring,</div><div class='ctx'> 		PACKET3_SET_RESOURCES_VMID_MASK(0) |</div><div class='hunk'>@@ -74,8 +190,8 @@ static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 			lower_32_bits(queue_mask));	/* queue mask lo */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring,</div><div class='ctx'> 			upper_32_bits(queue_mask));	/* queue mask hi */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */</div><div class='del'>-	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */</div><div class='add'>+	amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */</div><div class='ctx'> 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */</div><div class='ctx'> }</div><div class='hunk'>@@ -172,12 +288,46 @@ static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,</div><div class='ctx'> 			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,</div><div class='add'>+					  uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+					  uint32_t xcc_id, uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = kiq_ring-&gt;adev;</div><div class='add'>+	unsigned i;</div><div class='add'>+</div><div class='add'>+	/* enter save mode */</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id);</div><div class='add'>+</div><div class='add'>+	if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='add'>+		WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2);</div><div class='add'>+		WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+			dev_err(adev-&gt;dev, "fail to wait on hqd deactive\n");</div><div class='add'>+	} else {</div><div class='add'>+		dev_err(adev-&gt;dev, "reset queue_type(%d) not supported\n\n", queue_type);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	/* exit safe mode */</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {</div><div class='ctx'> 	.kiq_set_resources = gfx_v9_4_3_kiq_set_resources,</div><div class='ctx'> 	.kiq_map_queues = gfx_v9_4_3_kiq_map_queues,</div><div class='ctx'> 	.kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,</div><div class='ctx'> 	.kiq_query_status = gfx_v9_4_3_kiq_query_status,</div><div class='ctx'> 	.kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,</div><div class='add'>+	.kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue,</div><div class='ctx'> 	.set_resources_size = 8,</div><div class='ctx'> 	.map_queues_size = 7,</div><div class='ctx'> 	.unmap_queues_size = 6,</div><div class='hunk'>@@ -204,20 +354,28 @@ static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,</div><div class='ctx'> 			     GOLDEN_GB_ADDR_CONFIG);</div><div class='del'>-		/* Golden settings applied by driver for ASIC with rev_id 0 */</div><div class='del'>-		if (adev-&gt;rev_id == 0) {</div><div class='del'>-			WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,</div><div class='del'>-					      REDUCE_FIFO_DEPTH_BY_2, 2);</div><div class='del'>-		} else {</div><div class='del'>-			WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,</div><div class='del'>-						SPARE, 0x1);</div><div class='del'>-		}</div><div class='add'>+		WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg)</div><div class='add'>+{</div><div class='add'>+	uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);</div><div class='add'>+</div><div class='add'>+	/* If it is an XCC reg, normalize the reg to keep</div><div class='add'>+	   lower 16 bits in local xcc */</div><div class='add'>+</div><div class='add'>+	if (((normalized_reg &gt;= XCC_REG_RANGE_0_LOW) &amp;&amp; (normalized_reg &lt; XCC_REG_RANGE_0_HIGH)) ||</div><div class='add'>+		((normalized_reg &gt;= XCC_REG_RANGE_1_LOW) &amp;&amp; (normalized_reg &lt; XCC_REG_RANGE_1_HIGH)))</div><div class='add'>+		return normalized_reg;</div><div class='add'>+	else</div><div class='add'>+		return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,</div><div class='ctx'> 				       bool wc, uint32_t reg, uint32_t val)</div><div class='ctx'> {</div><div class='add'>+	reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg);</div><div class='ctx'> 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));</div><div class='ctx'> 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |</div><div class='ctx'> 				WRITE_DATA_DST_SEL(0) |</div><div class='hunk'>@@ -232,6 +390,12 @@ static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,</div><div class='ctx'> 				  uint32_t addr1, uint32_t ref, uint32_t mask,</div><div class='ctx'> 				  uint32_t inv)</div><div class='ctx'> {</div><div class='add'>+	/* Only do the normalization on regspace */</div><div class='add'>+	if (mem_space == 0) {</div><div class='add'>+		addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0);</div><div class='add'>+		addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));</div><div class='ctx'> 	amdgpu_ring_write(ring,</div><div class='ctx'> 				 /* memory (1) or register (0) */</div><div class='hunk'>@@ -333,7 +497,7 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err2:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err1:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -370,15 +534,15 @@ static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 					  const char *chip_name)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct rlc_firmware_header_v2_0 *rlc_hdr;</div><div class='ctx'> 	uint16_t version_major;</div><div class='ctx'> 	uint16_t version_minor;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);</div><div class='ctx'> </div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw,</div><div class='add'>+				   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_rlc.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='hunk'>@@ -393,26 +557,24 @@ out:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)</div><div class='del'>-{</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	if (gfx_v9_4_3_should_disable_gfxoff(adev-&gt;pdev))</div><div class='del'>-		adev-&gt;pm.pp_feature &amp;= ~PP_GFXOFF_MASK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 					  const char *chip_name)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);</div><div class='del'>-</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw, fw_name);</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_sjt_mec.bin", chip_name);</div><div class='add'>+</div><div class='add'>+		if (err)</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+							AMDGPU_UCODE_REQUIRED,</div><div class='add'>+							"amdgpu/%s_mec.bin", chip_name);</div><div class='add'>+	} else</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.mec_fw,</div><div class='add'>+					   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_mec.bin", chip_name);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);</div><div class='hunk'>@@ -421,8 +583,6 @@ static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 	adev-&gt;gfx.mec2_fw_version = adev-&gt;gfx.mec_fw_version;</div><div class='ctx'> 	adev-&gt;gfx.mec2_feature_version = adev-&gt;gfx.mec_feature_version;</div><div class='ctx'> </div><div class='del'>-	gfx_v9_4_3_check_if_need_gfxoff(adev);</div><div class='del'>-</div><div class='ctx'> out:</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.mec_fw);</div><div class='hunk'>@@ -431,16 +591,16 @@ out:</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	const char *chip_name;</div><div class='add'>+	char ucode_prefix[15];</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	chip_name = "gc_9_4_3";</div><div class='add'>+	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='ctx'> </div><div class='del'>-	r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);</div><div class='add'>+	r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);</div><div class='add'>+	r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -624,6 +784,15 @@ static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,</div><div class='ctx'> 	soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 xcp_ctl;</div><div class='add'>+</div><div class='add'>+	/* Value is expected to be the same on all, fetch from first instance */</div><div class='add'>+	xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL);</div><div class='add'>+</div><div class='add'>+	return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,</div><div class='ctx'> 						int num_xccs_per_xcp)</div><div class='hunk'>@@ -678,40 +847,48 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {</div><div class='ctx'> 	.select_me_pipe_q = &amp;gfx_v9_4_3_select_me_pipe_q,</div><div class='ctx'> 	.switch_partition_mode = &amp;gfx_v9_4_3_switch_compute_partition,</div><div class='ctx'> 	.ih_node_to_logical_xcc = &amp;gfx_v9_4_3_ih_to_xcc_inst,</div><div class='add'>+	.get_xccs_per_xcp = &amp;gfx_v9_4_3_get_xccs_per_xcp,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_aca_bank_generate_report(struct aca_handle *handle,</div><div class='del'>-					       struct aca_bank *bank, enum aca_error_type type,</div><div class='del'>-					       struct aca_bank_report *report, void *data)</div><div class='add'>+static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle,</div><div class='add'>+				      struct aca_bank *bank, enum aca_smu_type type,</div><div class='add'>+				      void *data)</div><div class='ctx'> {</div><div class='del'>-	u64 status, misc0;</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='ctx'> 	u32 instlo;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	status = bank-&gt;regs[ACA_REG_IDX_STATUS];</div><div class='del'>-	if ((type == ACA_ERROR_TYPE_UE &amp;&amp;</div><div class='del'>-	     ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) ||</div><div class='del'>-	    (type == ACA_ERROR_TYPE_CE &amp;&amp;</div><div class='del'>-	     ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-		ret = aca_bank_info_decode(bank, &amp;report-&gt;info);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+	/* NOTE: overwrite info.die_id with xcd id for gfx */</div><div class='add'>+	instlo = ACA_REG__IPID__INSTANCEIDLO(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='add'>+	info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1;</div><div class='ctx'> </div><div class='del'>-		/* NOTE: overwrite info.die_id with xcd id for gfx */</div><div class='del'>-		instlo = ACA_REG__IPID__INSTANCEIDLO(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='del'>-		instlo &amp;= GENMASK(31, 1);</div><div class='del'>-		report-&gt;info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1;</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='ctx'> </div><div class='del'>-		misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='del'>-		report-&gt;count[type] = ACA_REG__MISC0__ERRCNT(misc0);</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type, 1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='del'>-					 enum aca_error_type type, void *data)</div><div class='add'>+					 enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	u32 instlo;</div><div class='ctx'> </div><div class='hunk'>@@ -730,7 +907,7 @@ static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_b</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = {</div><div class='del'>-	.aca_bank_generate_report = gfx_v9_4_3_aca_bank_generate_report,</div><div class='add'>+	.aca_bank_parser = gfx_v9_4_3_aca_bank_parser,</div><div class='ctx'> 	.aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -742,26 +919,15 @@ static const struct aca_info gfx_v9_4_3_aca_info = {</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	u32 gb_addr_config;</div><div class='del'>-</div><div class='ctx'> 	adev-&gt;gfx.funcs = &amp;gfx_v9_4_3_gfx_funcs;</div><div class='ctx'> 	adev-&gt;gfx.ras = &amp;gfx_v9_4_3_ras;</div><div class='ctx'> </div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(9, 4, 3):</div><div class='del'>-		adev-&gt;gfx.config.max_hw_contexts = 8;</div><div class='del'>-		adev-&gt;gfx.config.sc_prim_fifo_size_frontend = 0x20;</div><div class='del'>-		adev-&gt;gfx.config.sc_prim_fifo_size_backend = 0x100;</div><div class='del'>-		adev-&gt;gfx.config.sc_hiz_tile_fifo_size = 0x30;</div><div class='del'>-		adev-&gt;gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;</div><div class='del'>-		gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BUG();</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	adev-&gt;gfx.config.gb_addr_config = gb_addr_config;</div><div class='add'>+	adev-&gt;gfx.config.max_hw_contexts = 8;</div><div class='add'>+	adev-&gt;gfx.config.sc_prim_fifo_size_frontend = 0x20;</div><div class='add'>+	adev-&gt;gfx.config.sc_prim_fifo_size_backend = 0x100;</div><div class='add'>+	adev-&gt;gfx.config.sc_hiz_tile_fifo_size = 0x30;</div><div class='add'>+	adev-&gt;gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;</div><div class='add'>+	adev-&gt;gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.config.gb_addr_config_fields.num_pipes = 1 &lt;&lt;</div><div class='ctx'> 			REG_GET_FIELD(</div><div class='hunk'>@@ -840,10 +1006,58 @@ static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,</div><div class='ctx'> 				hw_prio, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_sw_init(void *handle)</div><div class='add'>+static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);</div><div class='add'>+	uint32_t *ptr, num_xcc, inst;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_core = ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for compute queue registers for all the instances */</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);</div><div class='add'>+	inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;gfx.ip_dump_compute_queues = ptr;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j, k, r, ring_id, xcc_id, num_xcc;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex;</div><div class='add'>+		adev-&gt;gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex);</div><div class='add'>+		if (adev-&gt;gfx.mec_fw_version &gt;= 153) {</div><div class='add'>+			adev-&gt;gfx.enable_cleaner_shader = true;</div><div class='add'>+			r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev-&gt;gfx.cleaner_shader_size);</div><div class='add'>+			if (r) {</div><div class='add'>+				adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+				dev_err(adev-&gt;dev, "Failed to initialize cleaner shader\n");</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;gfx.enable_cleaner_shader = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.mec.num_mec = 2;</div><div class='ctx'> 	adev-&gt;gfx.mec.num_pipe_per_mec = 4;</div><div class='hunk'>@@ -856,6 +1070,13 @@ static int gfx_v9_4_3_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	/* Bad opcode Event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,</div><div class='add'>+			      GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR,</div><div class='add'>+			      &amp;adev-&gt;gfx.bad_op_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	/* Privileged reg */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,</div><div class='ctx'> 			      &amp;adev-&gt;gfx.priv_reg_irq);</div><div class='hunk'>@@ -922,6 +1143,29 @@ static int gfx_v9_4_3_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.compute_supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;gfx.compute_ring[0]);</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+		if ((adev-&gt;gfx.mec_fw_version &gt;= 155) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='add'>+		if ((adev-&gt;gfx.mec_fw_version &gt;= 21) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+			adev-&gt;gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> 	r = gfx_v9_4_3_gpu_early_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -930,17 +1174,19 @@ static int gfx_v9_4_3_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_gfx_sysfs_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_sriov_vf(adev))</div><div class='del'>-		r = amdgpu_gfx_sysfs_init(adev);</div><div class='add'>+	gfx_v9_4_3_alloc_ip_dump(adev);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_sw_fini(void *handle)</div><div class='add'>+static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, num_xcc;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings * num_xcc; i++)</div><div class='hunk'>@@ -952,11 +1198,15 @@ static int gfx_v9_4_3_sw_fini(void *handle)</div><div class='ctx'> 		amdgpu_gfx_kiq_fini(adev, i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_gfx_cleaner_shader_sw_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	gfx_v9_4_3_mec_fini(adev);</div><div class='ctx'> 	amdgpu_bo_unref(&amp;adev-&gt;gfx.rlc.clear_state_obj);</div><div class='ctx'> 	gfx_v9_4_3_free_microcode(adev);</div><div class='del'>-	if (!amdgpu_sriov_vf(adev))</div><div class='del'>-		amdgpu_gfx_sysfs_fini(adev);</div><div class='add'>+	amdgpu_gfx_sysfs_fini(adev);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_core);</div><div class='add'>+	kfree(adev-&gt;gfx.ip_dump_compute_queues);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -997,8 +1247,10 @@ static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,</div><div class='ctx'> 	soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='ctx'> </div><div class='del'>-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA</div><div class='del'>-	   acccess. These should be enabled by FW for target VMIDs. */</div><div class='add'>+	/*</div><div class='add'>+	 * Initialize all compute VMIDs to have no GDS, GWS, or OA</div><div class='add'>+	 * access. These should be enabled by FW for target VMIDs.</div><div class='add'>+	 */</div><div class='ctx'> 	for (i = adev-&gt;vm_manager.first_kfd_vmid; i &lt; AMDGPU_NUM_VMID; i++) {</div><div class='ctx'> 		WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);</div><div class='ctx'> 		WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);</div><div class='hunk'>@@ -1025,6 +1277,22 @@ static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1</div><div class='add'>+ * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain</div><div class='add'>+ * bit in SET_RESOURCES</div><div class='add'>+ */</div><div class='add'>+static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id)</div><div class='add'>+{</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;gmc.xnack_flags &amp; AMDGPU_GMC_XNACK_FLAG_CHAIN))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1);</div><div class='add'>+	data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);</div><div class='add'>+	WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,</div><div class='ctx'> 					  int xcc_id)</div><div class='ctx'> {</div><div class='hunk'>@@ -1069,6 +1337,7 @@ static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);</div><div class='ctx'> 	gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);</div><div class='add'>+	gfx_v9_4_3_xcc_init_sq(adev, xcc_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1081,6 +1350,22 @@ static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.config.db_debug2 =</div><div class='ctx'> 		RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	/* ToDo: GC 9.4.4 */</div><div class='add'>+	case IP_VERSION(9, 4, 3):</div><div class='add'>+		if (adev-&gt;gfx.mec_fw_version &gt;= 184 &amp;&amp;</div><div class='add'>+		    (amdgpu_sriov_reg_access_sq_config(adev) ||</div><div class='add'>+		     !amdgpu_sriov_vf(adev)))</div><div class='add'>+			adev-&gt;gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='add'>+		if (adev-&gt;gfx.mec_fw_version &gt;= 23)</div><div class='add'>+			adev-&gt;gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; num_xcc; i++)</div><div class='ctx'> 		gfx_v9_4_3_xcc_constants_init(adev, i);</div><div class='ctx'> }</div><div class='hunk'>@@ -1096,10 +1381,8 @@ static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Rlc save restore list is workable since v2_1.</div><div class='del'>-	 * And it's needed by gfxoff feature.</div><div class='ctx'> 	 */</div><div class='del'>-	if (adev-&gt;gfx.rlc.is_rlc_v2_1)</div><div class='del'>-		gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);</div><div class='add'>+	gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)</div><div class='hunk'>@@ -1386,21 +1669,23 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)</div><div class='ctx'> static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,</div><div class='ctx'> 				       unsigned vmid)</div><div class='ctx'> {</div><div class='del'>-	u32 reg, data;</div><div class='add'>+	u32 reg, pre_data, data;</div><div class='ctx'> </div><div class='ctx'> 	reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);</div><div class='del'>-	if (amdgpu_sriov_is_pp_one_vf(adev))</div><div class='del'>-		data = RREG32_NO_KIQ(reg);</div><div class='add'>+	if (amdgpu_sriov_is_pp_one_vf(adev) &amp;&amp; !amdgpu_sriov_runtime(adev))</div><div class='add'>+		pre_data = RREG32_NO_KIQ(reg);</div><div class='ctx'> 	else</div><div class='del'>-		data = RREG32(reg);</div><div class='add'>+		pre_data = RREG32(reg);</div><div class='ctx'> </div><div class='del'>-	data &amp;= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;</div><div class='add'>+	data =	pre_data &amp; (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);</div><div class='ctx'> 	data |= (vmid &amp; RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) &lt;&lt; RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_is_pp_one_vf(adev))</div><div class='del'>-		WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);</div><div class='del'>-	else</div><div class='del'>-		WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);</div><div class='add'>+	if (pre_data != data) {</div><div class='add'>+		if (amdgpu_sriov_is_pp_one_vf(adev) &amp;&amp; !amdgpu_sriov_runtime(adev)) {</div><div class='add'>+			WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);</div><div class='add'>+		} else</div><div class='add'>+			WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {</div><div class='hunk'>@@ -1449,7 +1734,15 @@ static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,</div><div class='del'>-			(CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));</div><div class='add'>+			(CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME1_HALT_MASK |</div><div class='add'>+			 CP_MEC_CNTL__MEC_ME2_HALT_MASK));</div><div class='ctx'> 		adev-&gt;gfx.kiq[xcc_id].ring.sched.ready = false;</div><div class='ctx'> 	}</div><div class='ctx'> 	udelay(50);</div><div class='hunk'>@@ -1513,9 +1806,7 @@ static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);</div><div class='ctx'> 	tmp &amp;= 0xffffff00;</div><div class='ctx'> 	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-	tmp |= 0x80;</div><div class='del'>-	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+	WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)</div><div class='hunk'>@@ -1576,6 +1867,9 @@ static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)</div><div class='ctx'> 				    DOORBELL_SOURCE, 0);</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='ctx'> 				    DOORBELL_HIT, 0);</div><div class='add'>+		if (amdgpu_sriov_multi_vf_mode(adev))</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+					    DOORBELL_MODE, 1);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='ctx'> 					 DOORBELL_EN, 0);</div><div class='hunk'>@@ -1860,7 +2154,8 @@ static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)</div><div class='add'>+static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id,</div><div class='add'>+					  bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct v9_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='hunk'>@@ -1872,8 +2167,8 @@ static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)</div><div class='ctx'> 	 */</div><div class='ctx'> 	tmp_mqd = (struct v9_mqd *)adev-&gt;gfx.mec.mqd_backup[mqd_idx];</div><div class='ctx'> </div><div class='del'>-	if (!tmp_mqd-&gt;cp_hqd_pq_control ||</div><div class='del'>-	    (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend)) {</div><div class='add'>+	if (!restore &amp;&amp; (!tmp_mqd-&gt;cp_hqd_pq_control ||</div><div class='add'>+	    (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_suspend))) {</div><div class='ctx'> 		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));</div><div class='ctx'> 		((struct v9_mqd_allocation *)mqd)-&gt;dynamic_cu_mask = 0xFFFFFFFF;</div><div class='ctx'> 		((struct v9_mqd_allocation *)mqd)-&gt;dynamic_rb_mask = 0xFFFFFFFF;</div><div class='hunk'>@@ -1894,8 +2189,6 @@ static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)</div><div class='ctx'> 		atomic64_set((atomic64_t *)&amp;adev-&gt;wb.wb[ring-&gt;wptr_offs], 0);</div><div class='ctx'> 		amdgpu_ring_clear_ring(ring);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)</div><div class='hunk'>@@ -1921,55 +2214,25 @@ static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;gfx.kiq[xcc_id].ring;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-	if (unlikely(r != 0))</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-	if (unlikely(r != 0)) {</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);</div><div class='del'>-	amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-	ring-&gt;mqd_ptr = NULL;</div><div class='del'>-	amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='add'>+	gfx_v9_4_3_xcc_kiq_init_queue(&amp;adev-&gt;gfx.kiq[xcc_id].ring, xcc_id);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = NULL;</div><div class='del'>-	int r = 0, i;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.num_compute_rings; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;gfx.compute_ring[i + xcc_id * adev-&gt;gfx.num_compute_rings];</div><div class='del'>-</div><div class='del'>-		r = amdgpu_bo_reserve(ring-&gt;mqd_obj, false);</div><div class='del'>-		if (unlikely(r != 0))</div><div class='del'>-			goto done;</div><div class='del'>-		r = amdgpu_bo_kmap(ring-&gt;mqd_obj, (void **)&amp;ring-&gt;mqd_ptr);</div><div class='del'>-		if (!r) {</div><div class='del'>-			r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);</div><div class='del'>-			amdgpu_bo_kunmap(ring-&gt;mqd_obj);</div><div class='del'>-			ring-&gt;mqd_ptr = NULL;</div><div class='del'>-		}</div><div class='del'>-		amdgpu_bo_unreserve(ring-&gt;mqd_obj);</div><div class='del'>-		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+		ring = &amp;adev-&gt;gfx.compute_ring[i + xcc_id *</div><div class='add'>+			adev-&gt;gfx.num_compute_rings];</div><div class='add'>+</div><div class='add'>+		gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_gfx_enable_kcq(adev, xcc_id);</div><div class='del'>-done:</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_gfx_enable_kcq(adev, xcc_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)</div><div class='hunk'>@@ -1985,6 +2248,8 @@ static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 		r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='add'>+	} else {</div><div class='add'>+		gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);</div><div class='hunk'>@@ -2010,18 +2275,33 @@ static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> </div><div class='ctx'> static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int r = 0, i, num_xcc;</div><div class='add'>+	int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		enum amdgpu_gfx_partition mode;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_xcp_query_partition_mode(adev-&gt;xcp_mgr,</div><div class='del'>-					    AMDGPU_XCP_FL_NONE) ==</div><div class='del'>-	    AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)</div><div class='del'>-		r = amdgpu_xcp_switch_partition_mode(adev-&gt;xcp_mgr,</div><div class='del'>-						     amdgpu_user_partt_mode);</div><div class='add'>+		mode = amdgpu_xcp_query_partition_mode(adev-&gt;xcp_mgr,</div><div class='add'>+						       AMDGPU_XCP_FL_NONE);</div><div class='add'>+		if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev);</div><div class='add'>+		adev-&gt;gfx.num_xcc_per_xcp = num_xcc_per_xcp;</div><div class='add'>+		num_xcp = num_xcc / num_xcc_per_xcp;</div><div class='add'>+		r = amdgpu_xcp_init(adev-&gt;xcp_mgr, num_xcp, mode);</div><div class='ctx'> </div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;in_suspend)</div><div class='add'>+			amdgpu_xcp_restore_partition_mode(adev-&gt;xcp_mgr);</div><div class='add'>+		else if (amdgpu_xcp_query_partition_mode(adev-&gt;xcp_mgr,</div><div class='add'>+						    AMDGPU_XCP_FL_NONE) ==</div><div class='add'>+		    AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)</div><div class='add'>+			r = amdgpu_xcp_switch_partition_mode(</div><div class='add'>+				adev-&gt;xcp_mgr, amdgpu_user_partt_mode);</div><div class='add'>+	}</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='ctx'> 	for (i = 0; i &lt; num_xcc; i++) {</div><div class='ctx'> 		r = gfx_v9_4_3_xcc_cp_resume(adev, i);</div><div class='ctx'> 		if (r)</div><div class='hunk'>@@ -2031,12 +2311,6 @@ static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,</div><div class='del'>-				     int xcc_id)</div><div class='del'>-{</div><div class='del'>-	gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_gfx_disable_kcq(adev, xcc_id))</div><div class='hunk'>@@ -2068,13 +2342,16 @@ static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);</div><div class='del'>-	gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);</div><div class='add'>+	gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_hw_init(void *handle)</div><div class='add'>+static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_cleaner_shader_init(adev, adev-&gt;gfx.cleaner_shader_size,</div><div class='add'>+				       adev-&gt;gfx.cleaner_shader_ptr);</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 		gfx_v9_4_3_init_golden_registers(adev);</div><div class='hunk'>@@ -2092,13 +2369,14 @@ static int gfx_v9_4_3_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_hw_fini(void *handle)</div><div class='add'>+static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, num_xcc;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.priv_inst_irq, 0);</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='ctx'> </div><div class='ctx'> 	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='ctx'> 	for (i = 0; i &lt; num_xcc; i++) {</div><div class='hunk'>@@ -2108,19 +2386,19 @@ static int gfx_v9_4_3_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_suspend(void *handle)</div><div class='add'>+static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v9_4_3_hw_fini(handle);</div><div class='add'>+	return gfx_v9_4_3_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_resume(void *handle)</div><div class='add'>+static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return gfx_v9_4_3_hw_init(handle);</div><div class='add'>+	return gfx_v9_4_3_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gfx_v9_4_3_is_idle(void *handle)</div><div class='add'>+static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, num_xcc;</div><div class='ctx'> </div><div class='ctx'> 	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='hunk'>@@ -2132,24 +2410,24 @@ static bool gfx_v9_4_3_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_wait_for_idle(void *handle)</div><div class='add'>+static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (gfx_v9_4_3_is_idle(handle))</div><div class='add'>+		if (gfx_v9_4_3_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_soft_reset(void *handle)</div><div class='add'>+static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* GRBM_STATUS */</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);</div><div class='hunk'>@@ -2184,19 +2462,17 @@ static int gfx_v9_4_3_soft_reset(void *handle)</div><div class='ctx'> 		/* Disable MEC parsing/prefetching */</div><div class='ctx'> 		gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);</div><div class='ctx'> </div><div class='del'>-		if (grbm_soft_reset) {</div><div class='del'>-			tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);</div><div class='del'>-			tmp |= grbm_soft_reset;</div><div class='del'>-			dev_info(adev-&gt;dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-			WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);</div><div class='del'>-			tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);</div><div class='add'>+		tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);</div><div class='add'>+		tmp |= grbm_soft_reset;</div><div class='add'>+		dev_info(adev-&gt;dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+		WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='del'>-			udelay(50);</div><div class='add'>+		udelay(50);</div><div class='ctx'> </div><div class='del'>-			tmp &amp;= ~grbm_soft_reset;</div><div class='del'>-			WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);</div><div class='del'>-			tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);</div><div class='del'>-		}</div><div class='add'>+		tmp &amp;= ~grbm_soft_reset;</div><div class='add'>+		WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait a little for things to settle down */</div><div class='ctx'> 		udelay(50);</div><div class='hunk'>@@ -2233,9 +2509,9 @@ static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,</div><div class='ctx'> 				   (1 &lt;&lt; (oa_size + oa_base)) - (1 &lt;&lt; oa_base));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_early_init(void *handle)</div><div class='add'>+static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),</div><div class='ctx'> 					  AMDGPU_MAX_COMPUTE_RINGS);</div><div class='hunk'>@@ -2251,9 +2527,9 @@ static int gfx_v9_4_3_early_init(void *handle)</div><div class='ctx'> 	return gfx_v9_4_3_init_microcode(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_late_init(void *handle)</div><div class='add'>+static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.priv_reg_irq, 0);</div><div class='hunk'>@@ -2264,6 +2540,10 @@ static int gfx_v9_4_3_late_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_irq_get(adev, &amp;adev-&gt;gfx.bad_op_irq, 0);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	if (adev-&gt;gfx.ras &amp;&amp;</div><div class='ctx'> 	    adev-&gt;gfx.ras-&gt;enable_watchdog_timer)</div><div class='ctx'> 		adev-&gt;gfx.ras-&gt;enable_watchdog_timer(adev);</div><div class='hunk'>@@ -2398,10 +2678,10 @@ gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 		if (def != data)</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);</div><div class='ctx'> </div><div class='del'>-		/* enable cgcg FSM(0x0000363F) */</div><div class='add'>+		/* CGCG Hysteresis: 400us */</div><div class='ctx'> 		def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);</div><div class='ctx'> </div><div class='del'>-		data = (0x36</div><div class='add'>+		data = (0x2710</div><div class='ctx'> 			&lt;&lt; RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |</div><div class='ctx'> 		       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;</div><div class='ctx'> 		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_GFX_CGLS)</div><div class='hunk'>@@ -2410,10 +2690,10 @@ gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 		if (def != data)</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);</div><div class='ctx'> </div><div class='del'>-		/* set IDLE_POLL_COUNT(0x00900100) */</div><div class='add'>+		/* set IDLE_POLL_COUNT(0x33450100)*/</div><div class='ctx'> 		def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);</div><div class='ctx'> 		data = (0x0100 &lt;&lt; CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |</div><div class='del'>-			(0x0090 &lt;&lt; CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);</div><div class='add'>+			(0x3345 &lt;&lt; CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);</div><div class='ctx'> 		if (def != data)</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -2478,37 +2758,32 @@ static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {</div><div class='ctx'> 	.is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_set_powergating_state(void *handle,</div><div class='add'>+static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfx_v9_4_3_set_clockgating_state(void *handle,</div><div class='add'>+static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, num_xcc;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(9, 4, 3):</div><div class='del'>-		for (i = 0; i &lt; num_xcc; i++)</div><div class='del'>-			gfx_v9_4_3_xcc_update_gfx_clock_gating(</div><div class='del'>-				adev, state == AMD_CG_STATE_GATE, i);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	for (i = 0; i &lt; num_xcc; i++)</div><div class='add'>+		gfx_v9_4_3_xcc_update_gfx_clock_gating(</div><div class='add'>+			adev, state == AMD_CG_STATE_GATE, i);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -2716,6 +2991,8 @@ static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='add'>+	reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0 |	/* src: register*/</div><div class='ctx'> 				(5 &lt;&lt; 8) |	/* dst: memory */</div><div class='hunk'>@@ -2733,6 +3010,8 @@ static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t cmd = 0;</div><div class='ctx'> </div><div class='add'>+	reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg);</div><div class='add'>+</div><div class='ctx'> 	switch (ring-&gt;funcs-&gt;type) {</div><div class='ctx'> 	case AMDGPU_RING_TYPE_GFX:</div><div class='ctx'> 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;</div><div class='hunk'>@@ -2765,6 +3044,21 @@ static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='ctx'> 						   ref, mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring,</div><div class='add'>+					  unsigned vmid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t value = 0;</div><div class='add'>+</div><div class='add'>+	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);</div><div class='add'>+	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);</div><div class='add'>+	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);</div><div class='add'>+	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, ring-&gt;xcc_id);</div><div class='add'>+	WREG32_SOC15(GC, GET_INST(GC, ring-&gt;xcc_id), regSQ_CMD, value);</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, ring-&gt;xcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(</div><div class='ctx'> 	struct amdgpu_device *adev, int me, int pipe,</div><div class='ctx'> 	enum amdgpu_interrupt_state state, int xcc_id)</div><div class='hunk'>@@ -2818,21 +3112,103 @@ static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev,</div><div class='add'>+				     int xcc_id, int me, int pipe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * amdgpu controls only the first MEC. That's why this function only</div><div class='add'>+	 * handles the setting of interrupts for this specific MEC. All other</div><div class='add'>+	 * pipes' interrupts are set by amdkfd.</div><div class='add'>+	 */</div><div class='add'>+	if (me != 1)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (pipe) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);</div><div class='add'>+	case 1:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);</div><div class='add'>+	case 2:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);</div><div class='add'>+	case 3:</div><div class='add'>+		return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,</div><div class='ctx'> 					     struct amdgpu_irq_src *source,</div><div class='ctx'> 					     unsigned type,</div><div class='ctx'> 					     enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='del'>-	int i, num_xcc;</div><div class='add'>+	u32 mec_int_cntl_reg, mec_int_cntl;</div><div class='add'>+	int i, j, k, num_xcc;</div><div class='ctx'> </div><div class='ctx'> 	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='ctx'> 	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-		for (i = 0; i &lt; num_xcc; i++)</div><div class='add'>+		for (i = 0; i &lt; num_xcc; i++) {</div><div class='ctx'> 			WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,</div><div class='del'>-				PRIV_REG_INT_ENABLE,</div><div class='del'>-				state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+					      PRIV_REG_INT_ENABLE,</div><div class='add'>+					      state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_mec; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.mec.num_pipe_per_mec; k++) {</div><div class='add'>+					/* MECs start at 1 */</div><div class='add'>+					mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);</div><div class='add'>+</div><div class='add'>+					if (mec_int_cntl_reg) {</div><div class='add'>+						mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);</div><div class='add'>+						mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+									     PRIV_REG_INT_ENABLE,</div><div class='add'>+									     state == AMDGPU_IRQ_STATE_ENABLE ?</div><div class='add'>+									     1 : 0);</div><div class='add'>+						WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev,</div><div class='add'>+					     struct amdgpu_irq_src *source,</div><div class='add'>+					     unsigned type,</div><div class='add'>+					     enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 mec_int_cntl_reg, mec_int_cntl;</div><div class='add'>+	int i, j, k, num_xcc;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		for (i = 0; i &lt; num_xcc; i++) {</div><div class='add'>+			WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,</div><div class='add'>+					      OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+					      state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_mec; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.mec.num_pipe_per_mec; k++) {</div><div class='add'>+					/* MECs start at 1 */</div><div class='add'>+					mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);</div><div class='add'>+</div><div class='add'>+					if (mec_int_cntl_reg) {</div><div class='add'>+						mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);</div><div class='add'>+						mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,</div><div class='add'>+									     OPCODE_ERROR_INT_ENABLE,</div><div class='add'>+									     state == AMDGPU_IRQ_STATE_ENABLE ?</div><div class='add'>+									     1 : 0);</div><div class='add'>+						WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -2993,6 +3369,15 @@ static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_irq_src *source,</div><div class='add'>+				 struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	DRM_ERROR("Illegal opcode in command stream\n");</div><div class='add'>+	gfx_v9_4_3_fault(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				  struct amdgpu_irq_src *source,</div><div class='ctx'> 				  struct amdgpu_iv_entry *entry)</div><div class='hunk'>@@ -3079,6 +3464,178 @@ static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me,</div><div class='add'>+				uint32_t pipe, uint32_t queue,</div><div class='add'>+				uint32_t xcc_id)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+	/* make sure dequeue is complete*/</div><div class='add'>+	gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id));</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+	else</div><div class='add'>+		r = 0;</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!!(adev-&gt;gfx.compute_supported_reset &amp; AMDGPU_RESET_TYPE_PER_PIPE))</div><div class='add'>+		return true;</div><div class='add'>+	else</div><div class='add'>+		dev_warn_once(adev-&gt;dev, "Please use the latest MEC version to see whether support pipe reset\n");</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t reset_pipe, clean_pipe;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!gfx_v9_4_3_pipe_reset_support(adev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	gfx_v9_4_3_xcc_set_safe_mode(adev, ring-&gt;xcc_id);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring-&gt;xcc_id), regCP_MEC_CNTL);</div><div class='add'>+	clean_pipe = reset_pipe;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me == 1) {</div><div class='add'>+		switch (ring-&gt;pipe) {</div><div class='add'>+		case 0:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+						   MEC_ME1_PIPE0_RESET, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+						   MEC_ME1_PIPE1_RESET, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+						   MEC_ME1_PIPE2_RESET, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+						   MEC_ME1_PIPE3_RESET, 1);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (ring-&gt;pipe)</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+						   MEC_ME2_PIPE1_RESET, 1);</div><div class='add'>+		else</div><div class='add'>+			reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,</div><div class='add'>+						   MEC_ME2_PIPE0_RESET, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, GET_INST(GC, ring-&gt;xcc_id), regCP_MEC_CNTL, reset_pipe);</div><div class='add'>+	WREG32_SOC15(GC, GET_INST(GC, ring-&gt;xcc_id), regCP_MEC_CNTL, clean_pipe);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	gfx_v9_4_3_xcc_unset_safe_mode(adev, ring-&gt;xcc_id);</div><div class='add'>+</div><div class='add'>+	r = gfx_v9_4_3_unmap_done(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, ring-&gt;xcc_id);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,</div><div class='add'>+				unsigned int vmid,</div><div class='add'>+				struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[ring-&gt;xcc_id];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;kiq-&gt;ring;</div><div class='add'>+	int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_unmap_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;unmap_queues_size)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,</div><div class='add'>+				   0, 0);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "kiq ring test failed after ring: %s queue reset\n",</div><div class='add'>+				ring-&gt;name);</div><div class='add'>+		goto pipe_reset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gfx_v9_4_3_unmap_done(adev, ring-&gt;me, ring-&gt;pipe, ring-&gt;queue, ring-&gt;xcc_id);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to wait on hqd deactive and will try pipe reset\n");</div><div class='add'>+</div><div class='add'>+pipe_reset:</div><div class='add'>+	if (r) {</div><div class='add'>+		if (!(adev-&gt;gfx.compute_supported_reset &amp; AMDGPU_RESET_TYPE_PER_PIPE))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		r = gfx_v9_4_3_reset_hw_pipe(ring);</div><div class='add'>+		reset_mode = AMDGPU_RESET_TYPE_PER_PIPE;</div><div class='add'>+		dev_info(adev-&gt;dev, "ring: %s pipe reset :%s\n", ring-&gt;name,</div><div class='add'>+				r ? "failed" : "successfully");</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gfx_v9_4_3_xcc_kcq_init_queue(ring, ring-&gt;xcc_id, true);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size);</div><div class='add'>+	if (r) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, ring);</div><div class='add'>+	amdgpu_ring_commit(kiq_ring);</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	spin_unlock_irqrestore(&amp;kiq-&gt;ring_lock, flags);</div><div class='add'>+	if (r) {</div><div class='add'>+		if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE)</div><div class='add'>+			goto pipe_reset;</div><div class='add'>+</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to remap queue\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) {</div><div class='add'>+		r = amdgpu_ring_test_ring(ring);</div><div class='add'>+		if (r)</div><div class='add'>+			goto pipe_reset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum amdgpu_gfx_cp_ras_mem_id {</div><div class='ctx'> 	AMDGPU_GFX_CP_MEM1 = 1,</div><div class='ctx'> 	AMDGPU_GFX_CP_MEM2,</div><div class='hunk'>@@ -3891,8 +4448,8 @@ static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,</div><div class='ctx'> 	/* the caller should make sure initialize value of</div><div class='ctx'> 	 * err_data-&gt;ue_count and err_data-&gt;ce_count</div><div class='ctx'> 	 */</div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='del'>-	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, ce_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, ce_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,</div><div class='hunk'>@@ -3994,6 +4551,161 @@ static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)</div><div class='add'>+{</div><div class='add'>+	/* Header itself is a NOP packet */</div><div class='add'>+	if (num_nop == 1) {</div><div class='add'>+		amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));</div><div class='add'>+</div><div class='add'>+	/* Header is at index 0, followed by num_nops - 1 NOP packet's */</div><div class='add'>+	amdgpu_ring_insert_nop(ring, num_nop - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k;</div><div class='add'>+	uint32_t xcc_id, xcc_offset, inst_offset;</div><div class='add'>+	uint32_t num_xcc, reg, num_inst;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+	drm_printf(p, "Number of Instances:%d\n", num_xcc);</div><div class='add'>+	for (xcc_id = 0; xcc_id &lt; num_xcc; xcc_id++) {</div><div class='add'>+		xcc_offset = xcc_id * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance id:%d\n", xcc_id);</div><div class='add'>+		for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n",</div><div class='add'>+				   gc_reg_list_9_4_3[i].reg_name,</div><div class='add'>+				   adev-&gt;gfx.ip_dump_core[xcc_offset + i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* print compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);</div><div class='add'>+	drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n",</div><div class='add'>+		   num_xcc,</div><div class='add'>+		   adev-&gt;gfx.mec.num_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_pipe_per_mec,</div><div class='add'>+		   adev-&gt;gfx.mec.num_queue_per_pipe);</div><div class='add'>+</div><div class='add'>+	for (xcc_id = 0; xcc_id &lt; num_xcc; xcc_id++) {</div><div class='add'>+		xcc_offset = xcc_id * reg_count * num_inst;</div><div class='add'>+		inst_offset = 0;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+					drm_printf(p,</div><div class='add'>+						   "\nxcc:%d mec:%d, pipe:%d, queue:%d\n",</div><div class='add'>+						    xcc_id, i, j, k);</div><div class='add'>+					for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+						if (i &amp;&amp; gc_cp_reg_list_9_4_3[reg].reg_offset ==</div><div class='add'>+						    regCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+							drm_printf(p,</div><div class='add'>+								   "%-50s \t 0x%08x\n",</div><div class='add'>+								   "regCP_MEC_ME2_HEADER_DUMP",</div><div class='add'>+								   adev-&gt;gfx.ip_dump_compute_queues</div><div class='add'>+								   [xcc_offset + inst_offset +</div><div class='add'>+								    reg]);</div><div class='add'>+						else</div><div class='add'>+							drm_printf(p,</div><div class='add'>+								   "%-50s \t 0x%08x\n",</div><div class='add'>+								   gc_cp_reg_list_9_4_3[reg].reg_name,</div><div class='add'>+								   adev-&gt;gfx.ip_dump_compute_queues</div><div class='add'>+								   [xcc_offset + inst_offset +</div><div class='add'>+								    reg]);</div><div class='add'>+					}</div><div class='add'>+					inst_offset += reg_count;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t i, j, k;</div><div class='add'>+	uint32_t num_xcc, reg, num_inst;</div><div class='add'>+	uint32_t xcc_id, xcc_offset, inst_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_core)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='add'>+</div><div class='add'>+	for (xcc_id = 0; xcc_id &lt; num_xcc; xcc_id++) {</div><div class='add'>+		xcc_offset = xcc_id * reg_count;</div><div class='add'>+		for (i = 0; i &lt; reg_count; i++)</div><div class='add'>+			adev-&gt;gfx.ip_dump_core[xcc_offset + i] =</div><div class='add'>+				RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i],</div><div class='add'>+								   GET_INST(GC, xcc_id)));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* dump compute queue registers for all instances */</div><div class='add'>+	if (!adev-&gt;gfx.ip_dump_compute_queues)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_inst = adev-&gt;gfx.mec.num_mec * adev-&gt;gfx.mec.num_pipe_per_mec *</div><div class='add'>+		adev-&gt;gfx.mec.num_queue_per_pipe;</div><div class='add'>+	reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (xcc_id = 0; xcc_id &lt; num_xcc; xcc_id++) {</div><div class='add'>+		xcc_offset = xcc_id * reg_count * num_inst;</div><div class='add'>+		inst_offset = 0;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;gfx.mec.num_mec; i++) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;gfx.mec.num_pipe_per_mec; j++) {</div><div class='add'>+				for (k = 0; k &lt; adev-&gt;gfx.mec.num_queue_per_pipe; k++) {</div><div class='add'>+					/* ME0 is for GFX so start from 1 for CP */</div><div class='add'>+					soc15_grbm_select(adev, 1 + i, j, k, 0,</div><div class='add'>+							  GET_INST(GC, xcc_id));</div><div class='add'>+</div><div class='add'>+					for (reg = 0; reg &lt; reg_count; reg++) {</div><div class='add'>+						if (i &amp;&amp; gc_cp_reg_list_9_4_3[reg].reg_offset ==</div><div class='add'>+						    regCP_MEC_ME1_HEADER_DUMP)</div><div class='add'>+							adev-&gt;gfx.ip_dump_compute_queues</div><div class='add'>+								[xcc_offset +</div><div class='add'>+								 inst_offset + reg] =</div><div class='add'>+								RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),</div><div class='add'>+											regCP_MEC_ME2_HEADER_DUMP));</div><div class='add'>+						else</div><div class='add'>+							adev-&gt;gfx.ip_dump_compute_queues</div><div class='add'>+								[xcc_offset +</div><div class='add'>+								 inst_offset + reg] =</div><div class='add'>+								RREG32(SOC15_REG_ENTRY_OFFSET_INST(</div><div class='add'>+									       gc_cp_reg_list_9_4_3[reg],</div><div class='add'>+									       GET_INST(GC, xcc_id)));</div><div class='add'>+					}</div><div class='add'>+					inst_offset += reg_count;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	soc15_grbm_select(adev, 0, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* Emit the cleaner shader */</div><div class='add'>+	amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));</div><div class='add'>+	amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {</div><div class='ctx'> 	.name = "gfx_v9_4_3",</div><div class='ctx'> 	.early_init = gfx_v9_4_3_early_init,</div><div class='hunk'>@@ -4010,6 +4722,8 @@ static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = gfx_v9_4_3_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gfx_v9_4_3_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = gfx_v9_4_3_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = gfx_v9_4_3_ip_dump,</div><div class='add'>+	.print_ip_state = gfx_v9_4_3_ip_print,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {</div><div class='hunk'>@@ -4031,7 +4745,8 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {</div><div class='ctx'> 		8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */</div><div class='ctx'> 		7 + /* gfx_v9_4_3_emit_mem_sync */</div><div class='ctx'> 		5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */</div><div class='del'>-		15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */</div><div class='add'>+		15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */</div><div class='add'>+		2, /* gfx_v9_4_3_ring_emit_cleaner_shader */</div><div class='ctx'> 	.emit_ib_size =	7, /* gfx_v9_4_3_ring_emit_ib_compute */</div><div class='ctx'> 	.emit_ib = gfx_v9_4_3_ring_emit_ib_compute,</div><div class='ctx'> 	.emit_fence = gfx_v9_4_3_ring_emit_fence,</div><div class='hunk'>@@ -4041,13 +4756,18 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {</div><div class='ctx'> 	.emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = gfx_v9_4_3_ring_test_ring,</div><div class='ctx'> 	.test_ib = gfx_v9_4_3_ring_test_ib,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_nop = gfx_v9_4_3_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.emit_wreg = gfx_v9_4_3_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.soft_recovery = gfx_v9_4_3_ring_soft_recovery,</div><div class='ctx'> 	.emit_mem_sync = gfx_v9_4_3_emit_mem_sync,</div><div class='ctx'> 	.emit_wave_limit = gfx_v9_4_3_emit_wave_limit,</div><div class='add'>+	.reset = gfx_v9_4_3_reset_kcq,</div><div class='add'>+	.emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader,</div><div class='add'>+	.begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,</div><div class='add'>+	.end_use = amdgpu_gfx_enforce_isolation_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {</div><div class='hunk'>@@ -4076,6 +4796,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {</div><div class='ctx'> 	.emit_wreg = gfx_v9_4_3_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -4102,6 +4823,11 @@ static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {</div><div class='ctx'> 	.process = gfx_v9_4_3_priv_reg_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = {</div><div class='add'>+	.set = gfx_v9_4_3_set_bad_op_fault_state,</div><div class='add'>+	.process = gfx_v9_4_3_bad_op_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {</div><div class='ctx'> 	.set = gfx_v9_4_3_set_priv_inst_fault_state,</div><div class='ctx'> 	.process = gfx_v9_4_3_priv_inst_irq,</div><div class='hunk'>@@ -4115,6 +4841,9 @@ static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_reg_irq.funcs = &amp;gfx_v9_4_3_priv_reg_irq_funcs;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;gfx.bad_op_irq.num_types = 1;</div><div class='add'>+	adev-&gt;gfx.bad_op_irq.funcs = &amp;gfx_v9_4_3_bad_op_irq_funcs;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.num_types = 1;</div><div class='ctx'> 	adev-&gt;gfx.priv_inst_irq.funcs = &amp;gfx_v9_4_3_priv_inst_irq_funcs;</div><div class='ctx'> }</div><div class='hunk'>@@ -4127,30 +4856,13 @@ static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	/* init asci gds info */</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(9, 4, 3):</div><div class='del'>-		/* 9.4.3 removed all the GDS internal memory,</div><div class='del'>-		 * only support GWS opcode in kernel, like barrier</div><div class='del'>-		 * semaphore.etc */</div><div class='del'>-		adev-&gt;gds.gds_size = 0;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		adev-&gt;gds.gds_size = 0x10000;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(9, 4, 3):</div><div class='del'>-		/* deprecated for 9.4.3, no usage at all */</div><div class='del'>-		adev-&gt;gds.gds_compute_max_wave_id = 0;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		/* this really depends on the chip */</div><div class='del'>-		adev-&gt;gds.gds_compute_max_wave_id = 0x7ff;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	/* 9.4.3 variants removed all the GDS internal memory,</div><div class='add'>+	 * only support GWS opcode in kernel, like barrier</div><div class='add'>+	 * semaphore.etc */</div><div class='ctx'> </div><div class='add'>+	/* init asic gds info */</div><div class='add'>+	adev-&gt;gds.gds_size = 0;</div><div class='add'>+	adev-&gt;gds.gds_compute_max_wave_id = 0;</div><div class='ctx'> 	adev-&gt;gds.gws_size = 64;</div><div class='ctx'> 	adev-&gt;gds.oa_size = 16;</div><div class='ctx'> }</div><div class='hunk'>@@ -4187,9 +4899,10 @@ static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_i</div><div class='ctx'> static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,</div><div class='ctx'> 				 struct amdgpu_cu_info *cu_info)</div><div class='ctx'> {</div><div class='del'>-	int i, j, k, counter, xcc_id, active_cu_number = 0;</div><div class='del'>-	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;</div><div class='add'>+	int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;</div><div class='add'>+	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;</div><div class='ctx'> 	unsigned disable_masks[4 * 4];</div><div class='add'>+	bool is_symmetric_cus;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev || !cu_info)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -4207,6 +4920,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> 	for (xcc_id = 0; xcc_id &lt; NUM_XCC(adev-&gt;gfx.xcc_mask); xcc_id++) {</div><div class='add'>+		is_symmetric_cus = true;</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;gfx.config.max_shader_engines; i++) {</div><div class='ctx'> 			for (j = 0; j &lt; adev-&gt;gfx.config.max_sh_per_se; j++) {</div><div class='ctx'> 				mask = 1;</div><div class='hunk'>@@ -4234,6 +4948,15 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,</div><div class='ctx'> 					ao_cu_mask |= (ao_bitmap &lt;&lt; (i * 16 + j * 8));</div><div class='ctx'> 				cu_info-&gt;ao_cu_bitmap[i][j] = ao_bitmap;</div><div class='ctx'> 			}</div><div class='add'>+			if (i &amp;&amp; is_symmetric_cus &amp;&amp; prev_counter != counter)</div><div class='add'>+				is_symmetric_cus = false;</div><div class='add'>+			prev_counter = counter;</div><div class='add'>+		}</div><div class='add'>+		if (is_symmetric_cus) {</div><div class='add'>+			tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);</div><div class='add'>+			WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);</div><div class='ctx'> 		}</div><div class='ctx'> 		gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,</div><div class='ctx'> 					    xcc_id);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm<br/>new file mode 100644<br/>index 000000000000..d5325ef80ab0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm</a></div><div class='hunk'>@@ -0,0 +1,153 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+// This shader is to clean LDS, SGPRs and VGPRs. It is  first 64 Dwords or 256 bytes of 192 Dwords cleaner shader.</div><div class='add'>+//To turn this shader program on for complitaion change this to main and lower shader main to main_1</div><div class='add'>+ </div><div class='add'>+// MI300 : Clear SGPRs, VGPRs and LDS</div><div class='add'>+//   Uses two kernels launched separately:</div><div class='add'>+//   1. Clean VGPRs, LDS, and lower SGPRs</div><div class='add'>+//        Launches one workgroup per CU, each workgroup with 4x wave64 per SIMD in the CU</div><div class='add'>+//        Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs per SIMD</div><div class='add'>+//        Waves in the workgroup share the 64KB of LDS</div><div class='add'>+//        Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-383</div><div class='add'>+//        Each wave clears 128 VGPRs, so all 512 in the SIMD</div><div class='add'>+//        The first wave of the workgroup clears its 64KB of LDS</div><div class='add'>+//        The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup</div><div class='add'>+//          before any wave in the workgroup could end.  Without this, it is possible not all SGPRs get cleared.</div><div class='add'>+//    2. Clean remaining SGPRs</div><div class='add'>+//        Launches a workgroup with 24 waves per workgroup, yielding 6 waves per SIMD in each CU</div><div class='add'>+//        Waves are allocating 96 SGPRs</div><div class='add'>+//          CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves from allocating SGPRs 0-223.</div><div class='add'>+//          As such, these 6 waves per SIMD are allocated physical SGPRs 224-799</div><div class='add'>+//        Barriers do not work for &gt;16 waves per workgroup, so we cannot start with S_BARRIER</div><div class='add'>+//          Instead, the shader starts with an S_SETHALT 1. Once all waves are launched CP will send unhalt command</div><div class='add'>+//        The shader then clears all SGPRs allocated to it, cleaning out physical SGPRs 224-799</div><div class='add'>+ </div><div class='add'>+shader main</div><div class='add'>+  asic(MI300)</div><div class='add'>+  type(CS)</div><div class='add'>+  wave_size(64)</div><div class='add'>+// Note: original source code from SQ team</div><div class='add'>+</div><div class='add'>+//   (theorhetical fastest = ~512clks vgpr + 1536 lds + ~128 sgpr  = 2176 clks)</div><div class='add'>+</div><div class='add'>+  s_cmp_eq_u32 s0, 1                                // Bit0 is set, sgpr0 is set then clear VGPRS and LDS as FW set COMPUTE_USER_DATA_3</div><div class='add'>+  s_cbranch_scc0  label_0023                        // Clean VGPRs and LDS if sgpr0 of wave is set, scc = (s3 == 1)</div><div class='add'>+  S_BARRIER</div><div class='add'>+</div><div class='add'>+  s_movk_i32    m0, 0x0000</div><div class='add'>+  s_mov_b32     s2, 0x00000078  // Loop 128/8=16 times  (loop unrolled for performance)</div><div class='add'>+  //</div><div class='add'>+  // CLEAR VGPRs</div><div class='add'>+  //</div><div class='add'>+  s_set_gpr_idx_on  s2, 0x8    // enable Dest VGPR indexing</div><div class='add'>+label_0005:</div><div class='add'>+  v_mov_b32     v0, 0</div><div class='add'>+  v_mov_b32     v1, 0</div><div class='add'>+  v_mov_b32     v2, 0</div><div class='add'>+  v_mov_b32     v3, 0</div><div class='add'>+  v_mov_b32     v4, 0</div><div class='add'>+  v_mov_b32     v5, 0</div><div class='add'>+  v_mov_b32     v6, 0</div><div class='add'>+  v_mov_b32     v7, 0</div><div class='add'>+  s_sub_u32     s2, s2, 8</div><div class='add'>+  s_set_gpr_idx_idx  s2</div><div class='add'>+  s_cbranch_scc0  label_0005</div><div class='add'>+  s_set_gpr_idx_off</div><div class='add'>+ </div><div class='add'>+  //</div><div class='add'>+  //</div><div class='add'>+ </div><div class='add'>+  s_mov_b32     s2, 0x80000000                      // Bit31 is first_wave</div><div class='add'>+  s_and_b32     s2, s2, s1                          // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set</div><div class='add'>+  s_cbranch_scc0  label_clean_sgpr_1                // Clean LDS if its first wave of ThreadGroup/WorkGroup</div><div class='add'>+  // CLEAR LDS</div><div class='add'>+  //</div><div class='add'>+  s_mov_b32 exec_lo, 0xffffffff</div><div class='add'>+  s_mov_b32 exec_hi, 0xffffffff</div><div class='add'>+  v_mbcnt_lo_u32_b32  v1, exec_hi, 0          // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mbcnt_hi_u32_b32  v1, exec_lo, v1         // Set V1 to thread-ID (0..63)</div><div class='add'>+  v_mul_u32_u24  v1, 0x00000008, v1           // * 8, so each thread is a double-dword address (8byte)</div><div class='add'>+  s_mov_b32     s2, 0x00000003f               // 64 loop iteraions</div><div class='add'>+  s_mov_b32     m0, 0xffffffff</div><div class='add'>+  // Clear all of LDS space</div><div class='add'>+  // Each FirstWave of WorkGroup clears 64kbyte block</div><div class='add'>+ </div><div class='add'>+label_001F:</div><div class='add'>+  ds_write2_b64  v1, v[2:3], v[2:3] offset1:32</div><div class='add'>+  ds_write2_b64  v1, v[4:5], v[4:5] offset0:64 offset1:96</div><div class='add'>+  v_add_co_u32     v1, vcc, 0x00000400, v1</div><div class='add'>+  s_sub_u32     s2, s2, 1</div><div class='add'>+  s_cbranch_scc0  label_001F</div><div class='add'>+  //</div><div class='add'>+  // CLEAR SGPRs</div><div class='add'>+  //</div><div class='add'>+label_clean_sgpr_1:</div><div class='add'>+  s_mov_b32     m0, 0x0000005c   // Loop 96/4=24 times  (loop unrolled for performance)</div><div class='add'>+  s_nop 0</div><div class='add'>+label_sgpr_loop:</div><div class='add'>+  s_movreld_b32     s0, 0</div><div class='add'>+  s_movreld_b32     s1, 0</div><div class='add'>+  s_movreld_b32     s2, 0</div><div class='add'>+  s_movreld_b32     s3, 0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop</div><div class='add'>+ </div><div class='add'>+  //clear vcc, flat scratch</div><div class='add'>+  s_mov_b32 flat_scratch_lo, 0   //clear  flat scratch lo SGPR </div><div class='add'>+  s_mov_b32 flat_scratch_hi, 0   //clear  flat scratch hi SGPR </div><div class='add'>+  s_mov_b64 vcc, 0               //clear vcc</div><div class='add'>+  s_mov_b64 ttmp0, 0             //Clear ttmp0 and ttmp1 </div><div class='add'>+  s_mov_b64 ttmp2, 0             //Clear ttmp2 and ttmp3 </div><div class='add'>+  s_mov_b64 ttmp4, 0             //Clear ttmp4 and ttmp5 </div><div class='add'>+  s_mov_b64 ttmp6, 0             //Clear ttmp6 and ttmp7 </div><div class='add'>+  s_mov_b64 ttmp8, 0             //Clear ttmp8 and ttmp9 </div><div class='add'>+  s_mov_b64 ttmp10, 0            //Clear ttmp10 and ttmp11 </div><div class='add'>+  s_mov_b64 ttmp12, 0            //Clear ttmp12 and ttmp13 </div><div class='add'>+  s_mov_b64 ttmp14, 0            //Clear ttmp14 and ttmp15 </div><div class='add'>+s_endpgm</div><div class='add'>+</div><div class='add'>+label_0023:</div><div class='add'>+</div><div class='add'>+  s_sethalt 1</div><div class='add'>+</div><div class='add'>+  s_mov_b32     m0, 0x0000005c   // Loop 96/4=24 times  (loop unrolled for performance)</div><div class='add'>+  s_nop 0</div><div class='add'>+label_sgpr_loop1:</div><div class='add'>+</div><div class='add'>+  s_movreld_b32     s0, 0</div><div class='add'>+  s_movreld_b32     s1, 0</div><div class='add'>+  s_movreld_b32     s2, 0</div><div class='add'>+  s_movreld_b32     s3, 0</div><div class='add'>+  s_sub_u32         m0, m0, 4</div><div class='add'>+  s_cbranch_scc0  label_sgpr_loop1</div><div class='add'>+ </div><div class='add'>+  //clear vcc, flat scratch</div><div class='add'>+  s_mov_b32 flat_scratch_lo, 0   //clear  flat scratch lo SGPR </div><div class='add'>+  s_mov_b32 flat_scratch_hi, 0   //clear  flat scratch hi SGPR </div><div class='add'>+  s_mov_b64 vcc, 0xee            //clear vcc</div><div class='add'>+</div><div class='add'>+s_endpgm</div><div class='add'>+end  </div><div class='add'>+  </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h<br/>new file mode 100644<br/>index 000000000000..69aa567c6c1d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h</a></div><div class='hunk'>@@ -0,0 +1,64 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Define the cleaner shader gfx_9_4_3 */</div><div class='add'>+static const u32 gfx_9_4_3_cleaner_shader_hex[] = {</div><div class='add'>+	0xbf068100, 0xbf84003b,</div><div class='add'>+	0xbf8a0000, 0xb07c0000,</div><div class='add'>+	0xbe8200ff, 0x00000078,</div><div class='add'>+	0xbf110802, 0x7e000280,</div><div class='add'>+	0x7e020280, 0x7e040280,</div><div class='add'>+	0x7e060280, 0x7e080280,</div><div class='add'>+	0x7e0a0280, 0x7e0c0280,</div><div class='add'>+	0x7e0e0280, 0x80828802,</div><div class='add'>+	0xbe803202, 0xbf84fff5,</div><div class='add'>+	0xbf9c0000, 0xbe8200ff,</div><div class='add'>+	0x80000000, 0x86020102,</div><div class='add'>+	0xbf840011, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xd28c0001,</div><div class='add'>+	0x0001007f, 0xd28d0001,</div><div class='add'>+	0x0002027e, 0x10020288,</div><div class='add'>+	0xbe8200bf, 0xbefc00c1,</div><div class='add'>+	0xd89c2000, 0x00020201,</div><div class='add'>+	0xd89c6040, 0x00040401,</div><div class='add'>+	0x320202ff, 0x00000400,</div><div class='add'>+	0x80828102, 0xbf84fff8,</div><div class='add'>+	0xbefc00ff, 0x0000005c,</div><div class='add'>+	0xbf800000, 0xbe802c80,</div><div class='add'>+	0xbe812c80, 0xbe822c80,</div><div class='add'>+	0xbe832c80, 0x80fc847c,</div><div class='add'>+	0xbf84fffa, 0xbee60080,</div><div class='add'>+	0xbee70080, 0xbeea0180,</div><div class='add'>+	0xbeec0180, 0xbeee0180,</div><div class='add'>+	0xbef00180, 0xbef20180,</div><div class='add'>+	0xbef40180, 0xbef60180,</div><div class='add'>+	0xbef80180, 0xbefa0180,</div><div class='add'>+	0xbf810000, 0xbf8d0001,</div><div class='add'>+	0xbefc00ff, 0x0000005c,</div><div class='add'>+	0xbf800000, 0xbe802c80,</div><div class='add'>+	0xbe812c80, 0xbe822c80,</div><div class='add'>+	0xbe832c80, 0x80fc847c,</div><div class='add'>+	0xbf84fffa, 0xbee60080,</div><div class='add'>+	0xbee70080, 0xbeea01ff,</div><div class='add'>+	0x000000ee, 0xbf810000,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c<br/>new file mode 100644<br/>index 000000000000..7609b9cecae8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c</a></div><div class='hunk'>@@ -0,0 +1,521 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "gfxhub_v12_0.h"</div><div class='add'>+</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "soc24_enum.h"</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+</div><div class='add'>+#define regGCVM_L2_CNTL3_DEFAULT	0x80120007</div><div class='add'>+#define regGCVM_L2_CNTL4_DEFAULT	0x000000c1</div><div class='add'>+#define regGCVM_L2_CNTL5_DEFAULT	0x00003fe0</div><div class='add'>+#define regGRBM_GFX_INDEX_DEFAULT	0xe0000000</div><div class='add'>+</div><div class='add'>+static const char *gfxhub_client_ids[] = {</div><div class='add'>+	"CB",</div><div class='add'>+	"DB",</div><div class='add'>+	"GE1",</div><div class='add'>+	"GE2",</div><div class='add'>+	"CPF",</div><div class='add'>+	"CPC",</div><div class='add'>+	"CPG",</div><div class='add'>+	"RLC",</div><div class='add'>+	"TCP",</div><div class='add'>+	"SQC (inst)",</div><div class='add'>+	"SQC (data)",</div><div class='add'>+	"SQG/PC/SC",</div><div class='add'>+	"Reserved",</div><div class='add'>+	"SDMA0",</div><div class='add'>+	"SDMA1",</div><div class='add'>+	"GCR",</div><div class='add'>+	"Reserved",</div><div class='add'>+	"Reserved",</div><div class='add'>+	"WGS",</div><div class='add'>+	"DSM",</div><div class='add'>+	"PA"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static uint32_t gfxhub_v12_0_get_invalidate_req(unsigned int vmid,</div><div class='add'>+					        uint32_t flush_type)</div><div class='add'>+{</div><div class='add'>+	u32 req = 0;</div><div class='add'>+</div><div class='add'>+	/* invalidate using legacy mode on vmid*/</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,</div><div class='add'>+			    PER_VMID_INVALIDATE_REQ, 1 &lt;&lt; vmid);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,</div><div class='add'>+			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);</div><div class='add'>+</div><div class='add'>+	return req;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gfxhub_v12_0_print_l2_protection_fault_status(struct amdgpu_device *adev,</div><div class='add'>+					      uint32_t status)</div><div class='add'>+{</div><div class='add'>+	u32 cid = REG_GET_FIELD(status,</div><div class='add'>+				GCVM_L2_PROTECTION_FAULT_STATUS_LO32, CID);</div><div class='add'>+</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",</div><div class='add'>+		status);</div><div class='add'>+	dev_err(adev-&gt;dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",</div><div class='add'>+		cid &gt;= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],</div><div class='add'>+		cid);</div><div class='add'>+	dev_err(adev-&gt;dev, "\t MORE_FAULTS: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t WALKER_ERROR: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		GCVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t PERMISSION_FAULTS: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		GCVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t MAPPING_ERROR: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t RW: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		GCVM_L2_PROTECTION_FAULT_STATUS_LO32, RW));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 gfxhub_v12_0_get_fb_location(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);</div><div class='add'>+</div><div class='add'>+	base &amp;= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;</div><div class='add'>+	base &lt;&lt;= 24;</div><div class='add'>+</div><div class='add'>+	return base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 gfxhub_v12_0_get_mc_fb_offset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) &lt;&lt; 24;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_setup_vm_pt_regs(struct amdgpu_device *adev,</div><div class='add'>+					  uint32_t vmid,</div><div class='add'>+					  uint64_t page_table_base)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,</div><div class='add'>+			    hub-&gt;ctx_addr_distance * vmid,</div><div class='add'>+			    lower_32_bits(page_table_base));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,</div><div class='add'>+			    hub-&gt;ctx_addr_distance * vmid,</div><div class='add'>+			    upper_32_bits(page_table_base));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_init_gart_aperture_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev-&gt;gart.bo);</div><div class='add'>+</div><div class='add'>+	gfxhub_v12_0_setup_vm_pt_regs(adev, 0, pt_base);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_start &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_start &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_end &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_end &gt;&gt; 44));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_init_system_aperture_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t value;</div><div class='add'>+</div><div class='add'>+	/* Program the AGP BAR */</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 24);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 24);</div><div class='add'>+</div><div class='add'>+	/* Program the system aperture low logical page number. */</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='add'>+		     min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,</div><div class='add'>+		     max(adev-&gt;gmc.fb_end, adev-&gt;gmc.agp_end) &gt;&gt; 18);</div><div class='add'>+</div><div class='add'>+	/* Set default page address. */</div><div class='add'>+	value = adev-&gt;mem_scratch.gpu_addr - adev-&gt;gmc.vram_start</div><div class='add'>+		+ adev-&gt;vm_manager.vram_base_offset;</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,</div><div class='add'>+		     (u32)(value &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,</div><div class='add'>+		     (u32)(value &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	/* Program "protection fault". */</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;dummy_page_addr &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,</div><div class='add'>+		     (u32)((u64)adev-&gt;dummy_page_addr &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,</div><div class='add'>+		       ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_init_tlb_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* Setup TLB control */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    MTYPE, MTYPE_UC); /* UC, uncached */</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_init_cache_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* These registers are not accessible to VF-SRIOV.</div><div class='add'>+	 * The PF will program them instead.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Setup L2 cache */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,</div><div class='add'>+			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);</div><div class='add'>+	/* XXX for emulation, Refer to closed source code.*/</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,</div><div class='add'>+			    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = regGCVM_L2_CNTL3_DEFAULT;</div><div class='add'>+	if (adev-&gt;gmc.translate_further) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,</div><div class='add'>+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);</div><div class='add'>+	} else {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,</div><div class='add'>+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = regGCVM_L2_CNTL4_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = regGCVM_L2_CNTL5_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_enable_system_domain(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,</div><div class='add'>+			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_disable_identity_aperture(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* These registers are not accessible to VF-SRIOV.</div><div class='add'>+	 * The PF will program them instead.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,</div><div class='add'>+		     0xFFFFFFFF);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,</div><div class='add'>+		     0x0000000F);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,</div><div class='add'>+		     0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,</div><div class='add'>+		     0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_setup_vmid_config(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt;= 14; i++) {</div><div class='add'>+		tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,</div><div class='add'>+				    adev-&gt;vm_manager.num_level);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				PAGE_TABLE_BLOCK_SIZE,</div><div class='add'>+				adev-&gt;vm_manager.block_size - 9);</div><div class='add'>+		/* Send no-retry XNACK on fault to suppress VM fault storm. */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,</div><div class='add'>+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,</div><div class='add'>+				    !amdgpu_noretry);</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,</div><div class='add'>+				    i * hub-&gt;ctx_distance, tmp);</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance, 0);</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance, 0);</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance,</div><div class='add'>+				    lower_32_bits(adev-&gt;vm_manager.max_pfn - 1));</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance,</div><div class='add'>+				    upper_32_bits(adev-&gt;vm_manager.max_pfn - 1));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hub-&gt;vm_cntx_cntl = tmp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_program_invalidation(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+	unsigned i;</div><div class='add'>+</div><div class='add'>+	for (i = 0 ; i &lt; 18; ++i) {</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,</div><div class='add'>+				    i * hub-&gt;eng_addr_distance, 0xffffffff);</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,</div><div class='add'>+				    i * hub-&gt;eng_addr_distance, 0x1f);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gfxhub_v12_0_gart_enable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/*</div><div class='add'>+		 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are</div><div class='add'>+		 * VF copy registers so vbios post doesn't program them, for</div><div class='add'>+		 * SRIOV driver need to program them</div><div class='add'>+		 */</div><div class='add'>+		WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE,</div><div class='add'>+			     adev-&gt;gmc.vram_start &gt;&gt; 24);</div><div class='add'>+		WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP,</div><div class='add'>+			     adev-&gt;gmc.vram_end &gt;&gt; 24);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* GART Enable. */</div><div class='add'>+	gfxhub_v12_0_init_gart_aperture_regs(adev);</div><div class='add'>+	gfxhub_v12_0_init_system_aperture_regs(adev);</div><div class='add'>+	gfxhub_v12_0_init_tlb_regs(adev);</div><div class='add'>+	gfxhub_v12_0_init_cache_regs(adev);</div><div class='add'>+</div><div class='add'>+	gfxhub_v12_0_enable_system_domain(adev);</div><div class='add'>+	gfxhub_v12_0_disable_identity_aperture(adev);</div><div class='add'>+	gfxhub_v12_0_setup_vmid_config(adev);</div><div class='add'>+	gfxhub_v12_0_program_invalidation(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_gart_disable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+	u32 tmp;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	/* Disable all tables */</div><div class='add'>+	for (i = 0; i &lt; 16; i++)</div><div class='add'>+		WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,</div><div class='add'>+				    i * hub-&gt;ctx_distance, 0);</div><div class='add'>+</div><div class='add'>+	/* Setup TLB control */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    ENABLE_ADVANCED_DRIVER_MODEL, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Setup L2 cache */</div><div class='add'>+	WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gfxhub_v12_0_set_fault_enable_default - update GART/VM fault handling</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @value: true redirects VM faults to the default page</div><div class='add'>+ */</div><div class='add'>+static void gfxhub_v12_0_set_fault_enable_default(struct amdgpu_device *adev,</div><div class='add'>+						  bool value)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	/* NO halt CP when page fault */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);</div><div class='add'>+</div><div class='add'>+	/* These registers are not accessible to VF-SRIOV.</div><div class='add'>+	 * The PF will program them instead.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,</div><div class='add'>+			    value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	if (!value) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+				CRASH_ON_NO_RETRY_FAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+				CRASH_ON_RETRY_FAULT, 1);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_vmhub_funcs gfxhub_v12_0_vmhub_funcs = {</div><div class='add'>+	.print_l2_protection_fault_status = gfxhub_v12_0_print_l2_protection_fault_status,</div><div class='add'>+	.get_invalidate_req = gfxhub_v12_0_get_invalidate_req,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gfxhub_v12_0_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+</div><div class='add'>+	hub-&gt;ctx0_ptb_addr_lo32 =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0,</div><div class='add'>+				 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);</div><div class='add'>+	hub-&gt;ctx0_ptb_addr_hi32 =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0,</div><div class='add'>+				 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);</div><div class='add'>+	hub-&gt;vm_inv_eng0_sem =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);</div><div class='add'>+	hub-&gt;vm_inv_eng0_req =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);</div><div class='add'>+	hub-&gt;vm_inv_eng0_ack =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);</div><div class='add'>+	hub-&gt;vm_context0_cntl =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);</div><div class='add'>+	hub-&gt;vm_l2_pro_fault_status =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32);</div><div class='add'>+	hub-&gt;vm_l2_pro_fault_cntl =</div><div class='add'>+		SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);</div><div class='add'>+</div><div class='add'>+	hub-&gt;ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;</div><div class='add'>+	hub-&gt;ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -</div><div class='add'>+		regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;</div><div class='add'>+	hub-&gt;eng_distance = regGCVM_INVALIDATE_ENG1_REQ -</div><div class='add'>+		regGCVM_INVALIDATE_ENG0_REQ;</div><div class='add'>+	hub-&gt;eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -</div><div class='add'>+		regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;</div><div class='add'>+</div><div class='add'>+	hub-&gt;vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;</div><div class='add'>+</div><div class='add'>+	hub-&gt;vmhub_funcs = &amp;gfxhub_v12_0_vmhub_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_gfxhub_funcs gfxhub_v12_0_funcs = {</div><div class='add'>+	.get_fb_location = gfxhub_v12_0_get_fb_location,</div><div class='add'>+	.get_mc_fb_offset = gfxhub_v12_0_get_mc_fb_offset,</div><div class='add'>+	.setup_vm_pt_regs = gfxhub_v12_0_setup_vm_pt_regs,</div><div class='add'>+	.gart_enable = gfxhub_v12_0_gart_enable,</div><div class='add'>+	.gart_disable = gfxhub_v12_0_gart_disable,</div><div class='add'>+	.set_fault_enable_default = gfxhub_v12_0_set_fault_enable_default,</div><div class='add'>+	.init = gfxhub_v12_0_init,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.h<br/>new file mode 100644<br/>index 000000000000..f1258265f802<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.h</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __GFXHUB_V12_0_H__</div><div class='add'>+#define __GFXHUB_V12_0_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_gfxhub_funcs gfxhub_v12_0_funcs;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c<br/>index 22175da0e16a..a7bfc9f41d0e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c</a></div><div class='hunk'>@@ -92,12 +92,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t value;</div><div class='ctx'> </div><div class='del'>-	/* Program the AGP BAR */</div><div class='del'>-	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);</div><div class='del'>-	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 24);</div><div class='del'>-	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 24);</div><div class='del'>-</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev) || adev-&gt;asic_type &lt;= CHIP_VEGA10) {</div><div class='add'>+		/* Program the AGP BAR */</div><div class='add'>+		WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);</div><div class='add'>+		WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 24);</div><div class='add'>+		WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 24);</div><div class='add'>+</div><div class='ctx'> 		/* Program the system aperture low logical page number. */</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='ctx'> 			min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18);</div><div class='hunk'>@@ -443,7 +443,6 @@ static void gfxhub_v1_0_init(struct amdgpu_device *adev)</div><div class='ctx'> 		mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {</div><div class='ctx'> 	.get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,</div><div class='ctx'> 	.setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c<br/>index 49aecdcee006..6c03bf9f1ae8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c</a></div><div class='hunk'>@@ -74,6 +74,8 @@ static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev,</div><div class='ctx'> static void gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,</div><div class='ctx'> 						    uint32_t xcc_mask)</div><div class='ctx'> {</div><div class='add'>+	uint64_t gart_start = amdgpu_virt_xgmi_migrate_enabled(adev) ?</div><div class='add'>+			adev-&gt;gmc.vram_start : adev-&gt;gmc.fb_start;</div><div class='ctx'> 	uint64_t pt_base;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -91,10 +93,10 @@ static void gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,</div><div class='ctx'> 		if (adev-&gt;gmc.pdb0_bo) {</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, i),</div><div class='ctx'> 				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,</div><div class='del'>-				     (u32)(adev-&gt;gmc.fb_start &gt;&gt; 12));</div><div class='add'>+				     (u32)(gart_start &gt;&gt; 12));</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, i),</div><div class='ctx'> 				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,</div><div class='del'>-				     (u32)(adev-&gt;gmc.fb_start &gt;&gt; 44));</div><div class='add'>+				     (u32)(gart_start &gt;&gt; 44));</div><div class='ctx'> </div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, i),</div><div class='ctx'> 				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,</div><div class='hunk'>@@ -180,7 +182,7 @@ gfxhub_v1_2_xcc_init_system_aperture_regs(struct amdgpu_device *adev,</div><div class='ctx'> 		/* In the case squeezing vram into GART aperture, we don't use</div><div class='ctx'> 		 * FB aperture and AGP aperture. Disable them.</div><div class='ctx'> 		 */</div><div class='del'>-		if (adev-&gt;gmc.pdb0_bo) {</div><div class='add'>+		if (adev-&gt;gmc.pdb0_bo &amp;&amp; adev-&gt;gmc.xgmi.connected_to_cpu) {</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);</div><div class='ctx'> 			WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);</div><div class='hunk'>@@ -313,6 +315,16 @@ gfxhub_v1_2_xcc_disable_identity_aperture(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool</div><div class='add'>+gfxhub_v1_2_per_process_xnack_support(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * TODO: Check if this function is really needed, so far only 9.4.3</div><div class='add'>+	 * variants use GFXHUB 1.2</div><div class='add'>+	 */</div><div class='add'>+	return !!adev-&gt;aid_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,</div><div class='ctx'> 					      uint32_t xcc_mask)</div><div class='ctx'> {</div><div class='hunk'>@@ -355,7 +367,7 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,</div><div class='ctx'> 					    PAGE_TABLE_BLOCK_SIZE,</div><div class='ctx'> 					    block_size);</div><div class='ctx'> 			/* Send no-retry XNACK on fault to suppress VM fault storm.</div><div class='del'>-			 * On 9.4.2 and 9.4.3, XNACK can be enabled in</div><div class='add'>+			 * On 9.4.3 variants, XNACK can be enabled in</div><div class='ctx'> 			 * the SQ per-process.</div><div class='ctx'> 			 * Retry faults need to be enabled for that to work.</div><div class='ctx'> 			 */</div><div class='hunk'>@@ -363,10 +375,8 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,</div><div class='ctx'> 				tmp, VM_CONTEXT1_CNTL,</div><div class='ctx'> 				RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,</div><div class='ctx'> 				!adev-&gt;gmc.noretry ||</div><div class='del'>-					amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='del'>-						IP_VERSION(9, 4, 2) ||</div><div class='del'>-					amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='del'>-						IP_VERSION(9, 4, 3));</div><div class='add'>+					gfxhub_v1_2_per_process_xnack_support(</div><div class='add'>+						adev));</div><div class='ctx'> 			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,</div><div class='ctx'> 					    i * hub-&gt;ctx_distance, tmp);</div><div class='ctx'> 			WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c<br/>index 17509f32f61a..deb95fab02df 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c</a></div><div class='hunk'>@@ -505,42 +505,6 @@ static void gfxhub_v2_1_init(struct amdgpu_device *adev)</div><div class='ctx'> 	hub-&gt;vmhub_funcs = &amp;gfxhub_v2_1_vmhub_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);</div><div class='del'>-	u32 max_region =</div><div class='del'>-		REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);</div><div class='del'>-	u32 max_num_physical_nodes   = 0;</div><div class='del'>-	u32 max_physical_node_id     = 0;</div><div class='del'>-</div><div class='del'>-	switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(4, 8, 0):</div><div class='del'>-		max_num_physical_nodes   = 4;</div><div class='del'>-		max_physical_node_id     = 3;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* PF_MAX_REGION=0 means xgmi is disabled */</div><div class='del'>-	if (max_region) {</div><div class='del'>-		adev-&gt;gmc.xgmi.num_physical_nodes = max_region + 1;</div><div class='del'>-		if (adev-&gt;gmc.xgmi.num_physical_nodes &gt; max_num_physical_nodes)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-</div><div class='del'>-		adev-&gt;gmc.xgmi.physical_node_id =</div><div class='del'>-			REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);</div><div class='del'>-		if (adev-&gt;gmc.xgmi.physical_node_id &gt; max_physical_node_id)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-</div><div class='del'>-		adev-&gt;gmc.xgmi.node_segment_size = REG_GET_FIELD(</div><div class='del'>-			RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),</div><div class='del'>-			GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) &lt;&lt; 24;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -696,7 +660,6 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {</div><div class='ctx'> 	.gart_disable = gfxhub_v2_1_gart_disable,</div><div class='ctx'> 	.set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,</div><div class='ctx'> 	.init = gfxhub_v2_1_init,</div><div class='del'>-	.get_xgmi_info = gfxhub_v2_1_get_xgmi_info,</div><div class='ctx'> 	.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,</div><div class='ctx'> 	.mode2_save_regs = gfxhub_v2_1_save_regs,</div><div class='ctx'> 	.mode2_restore_regs = gfxhub_v2_1_restore_regs,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br/>index d933e19e0cf5..ce6e04242c52 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c</a></div><div class='hunk'>@@ -103,8 +103,10 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	uint32_t vmhub_index = entry-&gt;client_id == SOC15_IH_CLIENTID_VMC ?</div><div class='ctx'> 			       AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);</div><div class='ctx'> 	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[vmhub_index];</div><div class='del'>-	bool retry_fault = !!(entry-&gt;src_data[1] &amp; 0x80);</div><div class='del'>-	bool write_fault = !!(entry-&gt;src_data[1] &amp; 0x20);</div><div class='add'>+	bool retry_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY);</div><div class='add'>+	bool write_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE);</div><div class='ctx'> 	struct amdgpu_task_info *task_info;</div><div class='ctx'> 	uint32_t status = 0;</div><div class='ctx'> 	u64 addr;</div><div class='hunk'>@@ -132,7 +134,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		/* Try to handle the recoverable page faults by filling page</div><div class='ctx'> 		 * tables</div><div class='ctx'> 		 */</div><div class='del'>-		if (amdgpu_vm_handle_fault(adev, entry-&gt;pasid, 0, 0, addr, write_fault))</div><div class='add'>+		if (amdgpu_vm_handle_fault(adev, entry-&gt;pasid, 0, 0, addr,</div><div class='add'>+					   entry-&gt;timestamp, write_fault))</div><div class='ctx'> 			return 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -163,10 +166,7 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		entry-&gt;src_id, entry-&gt;ring_id, entry-&gt;vmid, entry-&gt;pasid);</div><div class='ctx'> 	task_info = amdgpu_vm_get_task_info_pasid(adev, entry-&gt;pasid);</div><div class='ctx'> 	if (task_info) {</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			" in process %s pid %d thread %s pid %d\n",</div><div class='del'>-			task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='del'>-			task_info-&gt;task_name, task_info-&gt;pid);</div><div class='add'>+		amdgpu_vm_print_task_info(adev, task_info);</div><div class='ctx'> 		amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -174,7 +174,10 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 			addr, entry-&gt;client_id,</div><div class='ctx'> 			soc15_ih_clientid_name[entry-&gt;client_id]);</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+	/* Only print L2 fault status if the status register could be read and</div><div class='add'>+	 * contains useful information</div><div class='add'>+	 */</div><div class='add'>+	if (status != 0)</div><div class='ctx'> 		hub-&gt;vmhub_funcs-&gt;print_l2_protection_fault_status(adev,</div><div class='ctx'> 								   status);</div><div class='ctx'> </div><div class='hunk'>@@ -264,7 +267,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	ack = hub-&gt;vm_inv_eng0_ack + hub-&gt;eng_distance * eng;</div><div class='ctx'> </div><div class='ctx'> 	/* flush hdp cache */</div><div class='del'>-	adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	/* This is necessary for SRIOV as well as for GFXOFF to function</div><div class='ctx'> 	 * properly under bare metal</div><div class='hunk'>@@ -424,10 +427,6 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	uint32_t reg;</div><div class='ctx'> </div><div class='del'>-	/* MES fw manages IH_VMID_x_LUT updating */</div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	if (ring-&gt;vm_hub == AMDGPU_GFXHUB(0))</div><div class='ctx'> 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -469,24 +468,6 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int</div><div class='ctx'>  * 0 valid</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)</div><div class='del'>-{</div><div class='del'>-	switch (flags) {</div><div class='del'>-	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_NC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_WC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_CC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_UC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);</div><div class='del'>-	default:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> 				 uint64_t *addr, uint64_t *flags)</div><div class='ctx'> {</div><div class='hunk'>@@ -511,21 +492,39 @@ static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='del'>-				 struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				 struct amdgpu_vm *vm,</div><div class='add'>+				 struct amdgpu_bo *bo,</div><div class='add'>+				 uint32_t vm_flags,</div><div class='ctx'> 				 uint64_t *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *bo = mapping-&gt;bo_va-&gt;base.bo;</div><div class='del'>-</div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='del'>-	*flags |= mapping-&gt;flags &amp; AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_EXECUTABLE)</div><div class='add'>+		*flags |= AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> </div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_MTYPE_NV10_MASK;</div><div class='del'>-	*flags |= (mapping-&gt;flags &amp; AMDGPU_PTE_MTYPE_NV10_MASK);</div><div class='add'>+	switch (vm_flags &amp; AMDGPU_VM_MTYPE_MASK) {</div><div class='add'>+	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='add'>+	case AMDGPU_VM_MTYPE_NC:</div><div class='add'>+	default:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_WC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_CC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_UC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_NOALLOC;</div><div class='del'>-	*flags |= (mapping-&gt;flags &amp; AMDGPU_PTE_NOALLOC);</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_NOALLOC)</div><div class='add'>+		*flags |= AMDGPU_PTE_NOALLOC;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_NOALLOC;</div><div class='ctx'> </div><div class='del'>-	if (mapping-&gt;flags &amp; AMDGPU_PTE_PRT) {</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_PRT) {</div><div class='ctx'> 		*flags |= AMDGPU_PTE_PRT;</div><div class='ctx'> 		*flags |= AMDGPU_PTE_SNOOPED;</div><div class='ctx'> 		*flags |= AMDGPU_PTE_LOG;</div><div class='hunk'>@@ -536,8 +535,7 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='ctx'> 	if (bo &amp;&amp; bo-&gt;flags &amp; (AMDGPU_GEM_CREATE_COHERENT |</div><div class='ctx'> 			       AMDGPU_GEM_CREATE_EXT_COHERENT |</div><div class='ctx'> 			       AMDGPU_GEM_CREATE_UNCACHED))</div><div class='del'>-		*flags = (*flags &amp; ~AMDGPU_PTE_MTYPE_NV10_MASK) |</div><div class='del'>-			 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='hunk'>@@ -567,7 +565,6 @@ static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {</div><div class='ctx'> 	.flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,</div><div class='ctx'> 	.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,</div><div class='ctx'> 	.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,</div><div class='del'>-	.map_mtype = gmc_v10_0_map_mtype,</div><div class='ctx'> 	.get_vm_pde = gmc_v10_0_get_vm_pde,</div><div class='ctx'> 	.get_vm_pte = gmc_v10_0_get_vm_pte,</div><div class='ctx'> 	.get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,</div><div class='hunk'>@@ -630,9 +627,9 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_early_init(void *handle)</div><div class='add'>+static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v10_0_set_mmhub_funcs(adev);</div><div class='ctx'> 	gmc_v10_0_set_gfxhub_funcs(adev);</div><div class='hunk'>@@ -651,9 +648,9 @@ static int gmc_v10_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_late_init(void *handle)</div><div class='add'>+static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);</div><div class='hunk'>@@ -763,16 +760,16 @@ static int gmc_v10_0_gart_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gart.table_size = adev-&gt;gart.num_gpu_pages * 8;</div><div class='del'>-	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |</div><div class='add'>+	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) |</div><div class='ctx'> 				 AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_gart_table_vram_alloc(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_sw_init(void *handle)</div><div class='add'>+static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfxhub.funcs-&gt;init(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -920,9 +917,9 @@ static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_gart_table_vram_free(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_sw_fini(void *handle)</div><div class='add'>+static int gmc_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_vm_manager_fini(adev);</div><div class='ctx'> 	gmc_v10_0_gart_fini(adev);</div><div class='hunk'>@@ -966,10 +963,9 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;hdp.funcs-&gt;init_registers(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* Flush HDP after it is initialized */</div><div class='del'>-	adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='del'>-	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?</div><div class='del'>-		false : true;</div><div class='add'>+	value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;in_s0ix)</div><div class='ctx'> 		adev-&gt;gfxhub.funcs-&gt;set_fault_enable_default(adev, value);</div><div class='hunk'>@@ -985,9 +981,9 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_hw_init(void *handle)</div><div class='add'>+static int gmc_v10_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;</div><div class='hunk'>@@ -1032,9 +1028,9 @@ static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;gart_disable(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_hw_fini(void *handle)</div><div class='add'>+static int gmc_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v10_0_gart_disable(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1053,51 +1049,43 @@ static int gmc_v10_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_suspend(void *handle)</div><div class='add'>+static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	gmc_v10_0_hw_fini(adev);</div><div class='add'>+	gmc_v10_0_hw_fini(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_resume(void *handle)</div><div class='add'>+static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = gmc_v10_0_hw_init(adev);</div><div class='add'>+	r = gmc_v10_0_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vmid_reset_all(adev);</div><div class='add'>+	amdgpu_vmid_reset_all(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v10_0_is_idle(void *handle)</div><div class='add'>+static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* MC is always ready in GMC v10.*/</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_wait_for_idle(void *handle)</div><div class='add'>+static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* There is no need to wait for MC idle in GMC v10.*/</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int gmc_v10_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled</div><div class='hunk'>@@ -1120,9 +1108,9 @@ static int gmc_v10_0_set_clockgating_state(void *handle,</div><div class='ctx'> 		return athub_v2_0_set_clockgating(adev, state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gmc_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) ||</div><div class='ctx'> 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4))</div><div class='hunk'>@@ -1136,7 +1124,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		athub_v2_0_get_clockgating(adev, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v10_0_set_powergating_state(void *handle,</div><div class='add'>+static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1154,7 +1142,6 @@ const struct amd_ip_funcs gmc_v10_0_ip_funcs = {</div><div class='ctx'> 	.resume = gmc_v10_0_resume,</div><div class='ctx'> 	.is_idle = gmc_v10_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = gmc_v10_0_wait_for_idle,</div><div class='del'>-	.soft_reset = gmc_v10_0_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = gmc_v10_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gmc_v10_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = gmc_v10_0_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c<br/>index 527dc917e049..ba59ee8e398a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c</a></div><div class='hunk'>@@ -103,12 +103,41 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	uint32_t vmhub_index = entry-&gt;client_id == SOC21_IH_CLIENTID_VMC ?</div><div class='ctx'> 			       AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);</div><div class='ctx'> 	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[vmhub_index];</div><div class='add'>+	bool retry_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY);</div><div class='add'>+	bool write_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE);</div><div class='ctx'> 	uint32_t status = 0;</div><div class='ctx'> 	u64 addr;</div><div class='ctx'> </div><div class='ctx'> 	addr = (u64)entry-&gt;src_data[0] &lt;&lt; 12;</div><div class='ctx'> 	addr |= ((u64)entry-&gt;src_data[1] &amp; 0xf) &lt;&lt; 44;</div><div class='ctx'> </div><div class='add'>+	if (retry_fault) {</div><div class='add'>+		/* Returning 1 here also prevents sending the IV to the KFD */</div><div class='add'>+</div><div class='add'>+		/* Process it only if it's the first fault for this address */</div><div class='add'>+		if (entry-&gt;ih != &amp;adev-&gt;irq.ih_soft &amp;&amp;</div><div class='add'>+		    amdgpu_gmc_filter_faults(adev, entry-&gt;ih, addr, entry-&gt;pasid,</div><div class='add'>+					     entry-&gt;timestamp))</div><div class='add'>+			return 1;</div><div class='add'>+</div><div class='add'>+		/* Delegate it to a different ring if the hardware hasn't</div><div class='add'>+		 * already done it.</div><div class='add'>+		 */</div><div class='add'>+		if (entry-&gt;ih == &amp;adev-&gt;irq.ih) {</div><div class='add'>+			amdgpu_irq_delegate(adev, entry, 8);</div><div class='add'>+			return 1;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Try to handle the recoverable page faults by filling page</div><div class='add'>+		 * tables</div><div class='add'>+		 */</div><div class='add'>+		if (amdgpu_vm_handle_fault(adev, entry-&gt;pasid, 0, 0, addr,</div><div class='add'>+					   entry-&gt;timestamp, write_fault))</div><div class='add'>+			return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Issue a dummy read to wait for the status register to</div><div class='hunk'>@@ -134,17 +163,17 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 			entry-&gt;src_id, entry-&gt;ring_id, entry-&gt;vmid, entry-&gt;pasid);</div><div class='ctx'> 		task_info = amdgpu_vm_get_task_info_pasid(adev, entry-&gt;pasid);</div><div class='ctx'> 		if (task_info) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				" in process %s pid %d thread %s pid %d)\n",</div><div class='del'>-				task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='del'>-				task_info-&gt;task_name, task_info-&gt;pid);</div><div class='add'>+			amdgpu_vm_print_task_info(adev, task_info);</div><div class='ctx'> 			amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dev_err(adev-&gt;dev, "  in page starting at address 0x%016llx from client %d\n",</div><div class='ctx'> 				addr, entry-&gt;client_id);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		/* Only print L2 fault status if the status register could be read and</div><div class='add'>+		 * contains useful information</div><div class='add'>+		 */</div><div class='add'>+		if (status != 0)</div><div class='ctx'> 			hub-&gt;vmhub_funcs-&gt;print_l2_protection_fault_status(adev, status);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -226,12 +255,12 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	ack = hub-&gt;vm_inv_eng0_ack + hub-&gt;eng_distance * eng;</div><div class='ctx'> </div><div class='ctx'> 	/* flush hdp cache */</div><div class='del'>-	adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	/* This is necessary for SRIOV as well as for GFXOFF to function</div><div class='ctx'> 	 * properly under bare metal</div><div class='ctx'> 	 */</div><div class='del'>-	if ((adev-&gt;gfx.kiq[0].ring.sched.ready || adev-&gt;mes.ring.sched.ready) &amp;&amp;</div><div class='add'>+	if ((adev-&gt;gfx.kiq[0].ring.sched.ready || adev-&gt;mes.ring[0].sched.ready) &amp;&amp;</div><div class='ctx'> 	    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {</div><div class='ctx'> 		amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,</div><div class='ctx'> 						 1 &lt;&lt; vmid, GET_INST(GC, 0));</div><div class='hunk'>@@ -390,10 +419,6 @@ static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	uint32_t reg;</div><div class='ctx'> </div><div class='del'>-	/* MES fw manages IH_VMID_x_LUT updating */</div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	if (ring-&gt;vm_hub == AMDGPU_GFXHUB(0))</div><div class='ctx'> 		reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -434,24 +459,6 @@ static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int</div><div class='ctx'>  * 0 valid</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)</div><div class='del'>-{</div><div class='del'>-	switch (flags) {</div><div class='del'>-	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_NC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_WC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_CC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_UC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);</div><div class='del'>-	default:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> 				 uint64_t *addr, uint64_t *flags)</div><div class='ctx'> {</div><div class='hunk'>@@ -476,21 +483,39 @@ static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='del'>-				 struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				 struct amdgpu_vm *vm,</div><div class='add'>+				 struct amdgpu_bo *bo,</div><div class='add'>+				 uint32_t vm_flags,</div><div class='ctx'> 				 uint64_t *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *bo = mapping-&gt;bo_va-&gt;base.bo;</div><div class='del'>-</div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='del'>-	*flags |= mapping-&gt;flags &amp; AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_EXECUTABLE)</div><div class='add'>+		*flags |= AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> </div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_MTYPE_NV10_MASK;</div><div class='del'>-	*flags |= (mapping-&gt;flags &amp; AMDGPU_PTE_MTYPE_NV10_MASK);</div><div class='add'>+	switch (vm_flags &amp; AMDGPU_VM_MTYPE_MASK) {</div><div class='add'>+	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='add'>+	case AMDGPU_VM_MTYPE_NC:</div><div class='add'>+	default:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_WC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_CC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_UC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_NOALLOC;</div><div class='del'>-	*flags |= (mapping-&gt;flags &amp; AMDGPU_PTE_NOALLOC);</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_NOALLOC)</div><div class='add'>+		*flags |= AMDGPU_PTE_NOALLOC;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_NOALLOC;</div><div class='ctx'> </div><div class='del'>-	if (mapping-&gt;flags &amp; AMDGPU_PTE_PRT) {</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_PRT) {</div><div class='ctx'> 		*flags |= AMDGPU_PTE_PRT;</div><div class='ctx'> 		*flags |= AMDGPU_PTE_SNOOPED;</div><div class='ctx'> 		*flags |= AMDGPU_PTE_LOG;</div><div class='hunk'>@@ -501,8 +526,7 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='ctx'> 	if (bo &amp;&amp; bo-&gt;flags &amp; (AMDGPU_GEM_CREATE_COHERENT |</div><div class='ctx'> 			       AMDGPU_GEM_CREATE_EXT_COHERENT |</div><div class='ctx'> 			       AMDGPU_GEM_CREATE_UNCACHED))</div><div class='del'>-		*flags = (*flags &amp; ~AMDGPU_PTE_MTYPE_NV10_MASK) |</div><div class='del'>-			 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='hunk'>@@ -532,7 +556,6 @@ static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {</div><div class='ctx'> 	.flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,</div><div class='ctx'> 	.emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,</div><div class='ctx'> 	.emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,</div><div class='del'>-	.map_mtype = gmc_v11_0_map_mtype,</div><div class='ctx'> 	.get_vm_pde = gmc_v11_0_get_vm_pde,</div><div class='ctx'> 	.get_vm_pte = gmc_v11_0_get_vm_pte,</div><div class='ctx'> 	.get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,</div><div class='hunk'>@@ -577,6 +600,7 @@ static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(3, 3, 0):</div><div class='ctx'> 	case IP_VERSION(3, 3, 1):</div><div class='add'>+	case IP_VERSION(3, 3, 2):</div><div class='ctx'> 		adev-&gt;mmhub.funcs = &amp;mmhub_v3_3_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -593,6 +617,8 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		adev-&gt;gfxhub.funcs = &amp;gfxhub_v11_5_0_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -601,9 +627,9 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_early_init(void *handle)</div><div class='add'>+static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v11_0_set_gfxhub_funcs(adev);</div><div class='ctx'> 	gmc_v11_0_set_mmhub_funcs(adev);</div><div class='hunk'>@@ -622,9 +648,9 @@ static int gmc_v11_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_late_init(void *handle)</div><div class='add'>+static int gmc_v11_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);</div><div class='hunk'>@@ -723,16 +749,16 @@ static int gmc_v11_0_gart_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gart.table_size = adev-&gt;gart.num_gpu_pages * 8;</div><div class='del'>-	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |</div><div class='add'>+	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) |</div><div class='ctx'> 				 AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_gart_table_vram_alloc(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_sw_init(void *handle)</div><div class='add'>+static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;init(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -747,6 +773,18 @@ static int gmc_v11_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;gmc.vram_type = vram_type;</div><div class='ctx'> 	adev-&gt;gmc.vram_vendor = vram_vendor;</div><div class='ctx'> </div><div class='add'>+	/* The mall_size is already calculated as mall_size_per_umc * num_umc.</div><div class='add'>+	 * However, for gfx1151, which features a 2-to-1 UMC mapping,</div><div class='add'>+	 * the result must be multiplied by 2 to determine the actual mall size.</div><div class='add'>+	 */</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(11, 5, 1):</div><div class='add'>+		adev-&gt;gmc.mall_size *= 2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(11, 0, 0):</div><div class='ctx'> 	case IP_VERSION(11, 0, 1):</div><div class='hunk'>@@ -755,6 +793,8 @@ static int gmc_v11_0_sw_init(void *handle)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='ctx'> 		set_bit(AMDGPU_GFXHUB(0), adev-&gt;vmhubs_mask);</div><div class='ctx'> 		set_bit(AMDGPU_MMHUB0(0), adev-&gt;vmhubs_mask);</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -825,7 +865,7 @@ static int gmc_v11_0_sw_init(void *handle)</div><div class='ctx'> 	 * amdgpu graphics/compute will use VMIDs 1-7</div><div class='ctx'> 	 * amdkfd will use VMIDs 8-15</div><div class='ctx'> 	 */</div><div class='del'>-	adev-&gt;vm_manager.first_kfd_vmid = 8;</div><div class='add'>+	adev-&gt;vm_manager.first_kfd_vmid = adev-&gt;gfx.disable_kq ? 1 : 8;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_vm_manager_init(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -848,9 +888,9 @@ static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_gart_table_vram_free(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_sw_fini(void *handle)</div><div class='add'>+static int gmc_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_vm_manager_fini(adev);</div><div class='ctx'> 	gmc_v11_0_gart_fini(adev);</div><div class='hunk'>@@ -892,10 +932,9 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	/* Flush HDP after it is initialized */</div><div class='del'>-	adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='del'>-	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?</div><div class='del'>-		false : true;</div><div class='add'>+	value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;set_fault_enable_default(adev, value);</div><div class='ctx'> 	gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);</div><div class='hunk'>@@ -907,9 +946,9 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_hw_init(void *handle)</div><div class='add'>+static int gmc_v11_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;</div><div class='hunk'>@@ -939,9 +978,9 @@ static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;gart_disable(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_hw_fini(void *handle)</div><div class='add'>+static int gmc_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		/* full access mode, so don't touch any GMC register */</div><div class='hunk'>@@ -960,51 +999,43 @@ static int gmc_v11_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_suspend(void *handle)</div><div class='add'>+static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	gmc_v11_0_hw_fini(adev);</div><div class='add'>+	gmc_v11_0_hw_fini(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_resume(void *handle)</div><div class='add'>+static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = gmc_v11_0_hw_init(adev);</div><div class='add'>+	r = gmc_v11_0_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vmid_reset_all(adev);</div><div class='add'>+	amdgpu_vmid_reset_all(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v11_0_is_idle(void *handle)</div><div class='add'>+static bool gmc_v11_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* MC is always ready in GMC v11.*/</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_wait_for_idle(void *handle)</div><div class='add'>+static int gmc_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* There is no need to wait for MC idle in GMC v11.*/</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int gmc_v11_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gmc_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = adev-&gt;mmhub.funcs-&gt;set_clockgating(adev, state);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -1013,16 +1044,16 @@ static int gmc_v11_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return athub_v3_0_set_clockgating(adev, state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gmc_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;get_clockgating(adev, flags);</div><div class='ctx'> </div><div class='ctx'> 	athub_v3_0_get_clockgating(adev, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v11_0_set_powergating_state(void *handle,</div><div class='add'>+static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1040,7 +1071,6 @@ const struct amd_ip_funcs gmc_v11_0_ip_funcs = {</div><div class='ctx'> 	.resume = gmc_v11_0_resume,</div><div class='ctx'> 	.is_idle = gmc_v11_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = gmc_v11_0_wait_for_idle,</div><div class='del'>-	.soft_reset = gmc_v11_0_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = gmc_v11_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = gmc_v11_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = gmc_v11_0_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c<br/>new file mode 100644<br/>index 000000000000..7a9d6894e321<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c</a></div><div class='hunk'>@@ -0,0 +1,1070 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_cache.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_atomfirmware.h"</div><div class='add'>+#include "gmc_v12_0.h"</div><div class='add'>+#include "athub/athub_4_1_0_sh_mask.h"</div><div class='add'>+#include "athub/athub_4_1_0_offset.h"</div><div class='add'>+#include "oss/osssys_7_0_0_offset.h"</div><div class='add'>+#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"</div><div class='add'>+#include "soc24_enum.h"</div><div class='add'>+#include "soc24.h"</div><div class='add'>+#include "soc15d.h"</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "nbif_v6_3_1.h"</div><div class='add'>+#include "gfxhub_v12_0.h"</div><div class='add'>+#include "mmhub_v4_1_0.h"</div><div class='add'>+#include "athub_v4_1_0.h"</div><div class='add'>+#include "umc_v8_14.h"</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					 struct amdgpu_irq_src *src,</div><div class='add'>+					 unsigned type,</div><div class='add'>+					 enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					      struct amdgpu_irq_src *src, unsigned type,</div><div class='add'>+					      enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	switch (state) {</div><div class='add'>+	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='add'>+		/* MM HUB */</div><div class='add'>+		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);</div><div class='add'>+		/* GFX HUB */</div><div class='add'>+		/* This works because this interrupt is only</div><div class='add'>+		 * enabled at init/resume and disabled in</div><div class='add'>+		 * fini/suspend, so the overall state doesn't</div><div class='add'>+		 * change over the course of suspend/resume.</div><div class='add'>+		 */</div><div class='add'>+		if (!adev-&gt;in_s0ix)</div><div class='add'>+			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='add'>+		/* MM HUB */</div><div class='add'>+		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);</div><div class='add'>+		/* GFX HUB */</div><div class='add'>+		/* This works because this interrupt is only</div><div class='add'>+		 * enabled at init/resume and disabled in</div><div class='add'>+		 * fini/suspend, so the overall state doesn't</div><div class='add'>+		 * change over the course of suspend/resume.</div><div class='add'>+		 */</div><div class='add'>+		if (!adev-&gt;in_s0ix)</div><div class='add'>+			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev,</div><div class='add'>+				       struct amdgpu_irq_src *source,</div><div class='add'>+				       struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub;</div><div class='add'>+	bool retry_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY);</div><div class='add'>+	bool write_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE);</div><div class='add'>+	uint32_t status = 0;</div><div class='add'>+	u64 addr;</div><div class='add'>+</div><div class='add'>+	addr = (u64)entry-&gt;src_data[0] &lt;&lt; 12;</div><div class='add'>+	addr |= ((u64)entry-&gt;src_data[1] &amp; 0xf) &lt;&lt; 44;</div><div class='add'>+</div><div class='add'>+	if (entry-&gt;client_id == SOC21_IH_CLIENTID_VMC)</div><div class='add'>+		hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='add'>+	else</div><div class='add'>+		hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+</div><div class='add'>+	if (retry_fault) {</div><div class='add'>+		/* Returning 1 here also prevents sending the IV to the KFD */</div><div class='add'>+</div><div class='add'>+		/* Process it only if it's the first fault for this address */</div><div class='add'>+		if (entry-&gt;ih != &amp;adev-&gt;irq.ih_soft &amp;&amp;</div><div class='add'>+		    amdgpu_gmc_filter_faults(adev, entry-&gt;ih, addr, entry-&gt;pasid,</div><div class='add'>+					     entry-&gt;timestamp))</div><div class='add'>+			return 1;</div><div class='add'>+</div><div class='add'>+		/* Delegate it to a different ring if the hardware hasn't</div><div class='add'>+		 * already done it.</div><div class='add'>+		 */</div><div class='add'>+		if (entry-&gt;ih == &amp;adev-&gt;irq.ih) {</div><div class='add'>+			amdgpu_irq_delegate(adev, entry, 8);</div><div class='add'>+			return 1;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Try to handle the recoverable page faults by filling page</div><div class='add'>+		 * tables</div><div class='add'>+		 */</div><div class='add'>+		if (amdgpu_vm_handle_fault(adev, entry-&gt;pasid, 0, 0, addr,</div><div class='add'>+					   entry-&gt;timestamp, write_fault))</div><div class='add'>+			return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/*</div><div class='add'>+		 * Issue a dummy read to wait for the status register to</div><div class='add'>+		 * be updated to avoid reading an incorrect value due to</div><div class='add'>+		 * the new fast GRBM interface.</div><div class='add'>+		 */</div><div class='add'>+		if (entry-&gt;vmid_src == AMDGPU_GFXHUB(0))</div><div class='add'>+			RREG32(hub-&gt;vm_l2_pro_fault_status);</div><div class='add'>+</div><div class='add'>+		status = RREG32(hub-&gt;vm_l2_pro_fault_status);</div><div class='add'>+		WREG32_P(hub-&gt;vm_l2_pro_fault_cntl, 1, ~1);</div><div class='add'>+</div><div class='add'>+		amdgpu_vm_update_fault_cache(adev, entry-&gt;pasid, addr, status,</div><div class='add'>+					     entry-&gt;vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (printk_ratelimit()) {</div><div class='add'>+		struct amdgpu_task_info *task_info;</div><div class='add'>+</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",</div><div class='add'>+			entry-&gt;vmid_src ? "mmhub" : "gfxhub",</div><div class='add'>+			entry-&gt;src_id, entry-&gt;ring_id, entry-&gt;vmid, entry-&gt;pasid);</div><div class='add'>+		task_info = amdgpu_vm_get_task_info_pasid(adev, entry-&gt;pasid);</div><div class='add'>+		if (task_info) {</div><div class='add'>+			amdgpu_vm_print_task_info(adev, task_info);</div><div class='add'>+			amdgpu_vm_put_task_info(task_info);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dev_err(adev-&gt;dev, "  in page starting at address 0x%016llx from client %d\n",</div><div class='add'>+				addr, entry-&gt;client_id);</div><div class='add'>+</div><div class='add'>+		/* Only print L2 fault status if the status register could be read and</div><div class='add'>+		 * contains useful information</div><div class='add'>+		 */</div><div class='add'>+		if (status != 0)</div><div class='add'>+			hub-&gt;vmhub_funcs-&gt;print_l2_protection_fault_status(adev, status);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = {</div><div class='add'>+	.set = gmc_v12_0_vm_fault_interrupt_state,</div><div class='add'>+	.process = gmc_v12_0_process_interrupt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = {</div><div class='add'>+	.set = gmc_v12_0_ecc_interrupt_state,</div><div class='add'>+	.process = amdgpu_umc_process_ecc_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gmc.vm_fault.num_types = 1;</div><div class='add'>+	adev-&gt;gmc.vm_fault.funcs = &amp;gmc_v12_0_irq_funcs;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		adev-&gt;gmc.ecc_irq.num_types = 1;</div><div class='add'>+		adev-&gt;gmc.ecc_irq.funcs = &amp;gmc_v12_0_ecc_funcs;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @vmhub: vmhub type</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev,</div><div class='add'>+				       uint32_t vmhub)</div><div class='add'>+{</div><div class='add'>+	return ((vmhub == AMDGPU_MMHUB0(0)) &amp;&amp;</div><div class='add'>+		(!amdgpu_sriov_vf(adev)));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool gmc_v12_0_get_vmid_pasid_mapping_info(</div><div class='add'>+					struct amdgpu_device *adev,</div><div class='add'>+					uint8_t vmid, uint16_t *p_pasid)</div><div class='add'>+{</div><div class='add'>+	*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	return !!(*p_pasid);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GART</div><div class='add'>+ * VMID 0 is the physical GPU addresses as used by the kernel.</div><div class='add'>+ * VMIDs 1-15 are used for userspace clients and are handled</div><div class='add'>+ * by the amdgpu vm/hsa code.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,</div><div class='add'>+				   unsigned int vmhub, uint32_t flush_type)</div><div class='add'>+{</div><div class='add'>+	bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub);</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[vmhub];</div><div class='add'>+	u32 inv_req = hub-&gt;vmhub_funcs-&gt;get_invalidate_req(vmid, flush_type);</div><div class='add'>+	u32 tmp;</div><div class='add'>+	/* Use register 17 for GART */</div><div class='add'>+	const unsigned eng = 17;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned char hub_ip = 0;</div><div class='add'>+</div><div class='add'>+	hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ?</div><div class='add'>+		   GC_HWIP : MMHUB_HWIP;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;adev-&gt;gmc.invalidate_lock);</div><div class='add'>+	/*</div><div class='add'>+	 * It may lose gpuvm invalidate acknowldege state across power-gating</div><div class='add'>+	 * off cycle, add semaphore acquire before invalidation and semaphore</div><div class='add'>+	 * release after invalidation to avoid entering power gated state</div><div class='add'>+	 * to WA the Issue</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */</div><div class='add'>+	if (use_semaphore) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			/* a read return value of 1 means semaphore acuqire */</div><div class='add'>+			tmp = RREG32_RLC_NO_KIQ(hub-&gt;vm_inv_eng0_sem +</div><div class='add'>+					    hub-&gt;eng_distance * eng, hub_ip);</div><div class='add'>+			if (tmp &amp; 0x1)</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"Timeout waiting for sem acquire in VM flush!\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_RLC_NO_KIQ(hub-&gt;vm_inv_eng0_req + hub-&gt;eng_distance * eng, inv_req, hub_ip);</div><div class='add'>+</div><div class='add'>+	/* Wait for ACK with a delay.*/</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		tmp = RREG32_RLC_NO_KIQ(hub-&gt;vm_inv_eng0_ack +</div><div class='add'>+				    hub-&gt;eng_distance * eng, hub_ip);</div><div class='add'>+		tmp &amp;= 1 &lt;&lt; vmid;</div><div class='add'>+		if (tmp)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */</div><div class='add'>+	if (use_semaphore)</div><div class='add'>+		/*</div><div class='add'>+		 * add semaphore release after invalidation,</div><div class='add'>+		 * write with 0 means semaphore release</div><div class='add'>+		 */</div><div class='add'>+		WREG32_RLC_NO_KIQ(hub-&gt;vm_inv_eng0_sem +</div><div class='add'>+			      hub-&gt;eng_distance * eng, 0, hub_ip);</div><div class='add'>+</div><div class='add'>+	/* Issue additional private vm invalidation to MMHUB */</div><div class='add'>+	if ((vmhub != AMDGPU_GFXHUB(0)) &amp;&amp;</div><div class='add'>+	    (hub-&gt;vm_l2_bank_select_reserved_cid2) &amp;&amp;</div><div class='add'>+		!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		inv_req = RREG32_NO_KIQ(hub-&gt;vm_l2_bank_select_reserved_cid2);</div><div class='add'>+		/* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */</div><div class='add'>+		inv_req |= (1 &lt;&lt; 25);</div><div class='add'>+		/* Issue private invalidation */</div><div class='add'>+		WREG32_NO_KIQ(hub-&gt;vm_l2_bank_select_reserved_cid2, inv_req);</div><div class='add'>+		/* Read back to ensure invalidation is done*/</div><div class='add'>+		RREG32_NO_KIQ(hub-&gt;vm_l2_bank_select_reserved_cid2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;adev-&gt;gmc.invalidate_lock);</div><div class='add'>+</div><div class='add'>+	if (i &lt; adev-&gt;usec_timeout)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dev_err(adev-&gt;dev, "Timeout waiting for VM flush ACK!\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @vmid: vm instance to flush</div><div class='add'>+ * @vmhub: which hub to flush</div><div class='add'>+ * @flush_type: the flush type</div><div class='add'>+ *</div><div class='add'>+ * Flush the TLB for the requested page table.</div><div class='add'>+ */</div><div class='add'>+static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='add'>+					uint32_t vmhub, uint32_t flush_type)</div><div class='add'>+{</div><div class='add'>+	if ((vmhub == AMDGPU_GFXHUB(0)) &amp;&amp; !adev-&gt;gfx.is_poweron)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* flush hdp cache */</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+</div><div class='add'>+	/* This is necessary for SRIOV as well as for GFXOFF to function</div><div class='add'>+	 * properly under bare metal</div><div class='add'>+	 */</div><div class='add'>+	if ((adev-&gt;gfx.kiq[0].ring.sched.ready || adev-&gt;mes.ring[0].sched.ready) &amp;&amp;</div><div class='add'>+	    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {</div><div class='add'>+		struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[vmhub];</div><div class='add'>+		const unsigned eng = 17;</div><div class='add'>+		u32 inv_req = hub-&gt;vmhub_funcs-&gt;get_invalidate_req(vmid, flush_type);</div><div class='add'>+		u32 req = hub-&gt;vm_inv_eng0_req + hub-&gt;eng_distance * eng;</div><div class='add'>+		u32 ack = hub-&gt;vm_inv_eng0_ack + hub-&gt;eng_distance * eng;</div><div class='add'>+</div><div class='add'>+		amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,</div><div class='add'>+				1 &lt;&lt; vmid, GET_INST(GC, 0));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0);</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @pasid: pasid to be flush</div><div class='add'>+ * @flush_type: the flush type</div><div class='add'>+ * @all_hub: flush all hubs</div><div class='add'>+ * @inst: is used to select which instance of KIQ to use for the invalidation</div><div class='add'>+ *</div><div class='add'>+ * Flush the TLB for the requested pasid.</div><div class='add'>+ */</div><div class='add'>+static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,</div><div class='add'>+					  uint16_t pasid, uint32_t flush_type,</div><div class='add'>+					  bool all_hub, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	uint16_t queried;</div><div class='add'>+	int vmid, i;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_uni_mes &amp;&amp; adev-&gt;mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready &amp;&amp;</div><div class='add'>+	    (adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 0x84) {</div><div class='add'>+		struct mes_inv_tlbs_pasid_input input = {0};</div><div class='add'>+		input.pasid = pasid;</div><div class='add'>+		input.flush_type = flush_type;</div><div class='add'>+		input.hub_id = AMDGPU_GFXHUB(0);</div><div class='add'>+		/* MES will invalidate all gc_hub for the device from master */</div><div class='add'>+		adev-&gt;mes.funcs-&gt;invalidate_tlbs_pasid(&amp;adev-&gt;mes, &amp;input);</div><div class='add'>+		if (all_hub) {</div><div class='add'>+			/* Only need to invalidate mm_hub now, gfx12 only support one mmhub */</div><div class='add'>+			input.hub_id = AMDGPU_MMHUB0(0);</div><div class='add'>+			adev-&gt;mes.funcs-&gt;invalidate_tlbs_pasid(&amp;adev-&gt;mes, &amp;input);</div><div class='add'>+		}</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (vmid = 1; vmid &lt; 16; vmid++) {</div><div class='add'>+		bool valid;</div><div class='add'>+</div><div class='add'>+		valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid,</div><div class='add'>+							      &amp;queried);</div><div class='add'>+		if (!valid || queried != pasid)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (all_hub) {</div><div class='add'>+			for_each_set_bit(i, adev-&gt;vmhubs_mask,</div><div class='add'>+					 AMDGPU_MAX_VMHUBS)</div><div class='add'>+				gmc_v12_0_flush_gpu_tlb(adev, vmid, i,</div><div class='add'>+							flush_type);</div><div class='add'>+		} else {</div><div class='add'>+			gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),</div><div class='add'>+						flush_type);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,</div><div class='add'>+					     unsigned vmid, uint64_t pd_addr)</div><div class='add'>+{</div><div class='add'>+	bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring-&gt;adev, ring-&gt;vm_hub);</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;ring-&gt;adev-&gt;vmhub[ring-&gt;vm_hub];</div><div class='add'>+	uint32_t req = hub-&gt;vmhub_funcs-&gt;get_invalidate_req(vmid, 0);</div><div class='add'>+	unsigned eng = ring-&gt;vm_inv_eng;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * It may lose gpuvm invalidate acknowldege state across power-gating</div><div class='add'>+	 * off cycle, add semaphore acquire before invalidation and semaphore</div><div class='add'>+	 * release after invalidation to avoid entering power gated state</div><div class='add'>+	 * to WA the Issue</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */</div><div class='add'>+	if (use_semaphore)</div><div class='add'>+		/* a read return value of 1 means semaphore acuqire */</div><div class='add'>+		amdgpu_ring_emit_reg_wait(ring,</div><div class='add'>+					  hub-&gt;vm_inv_eng0_sem +</div><div class='add'>+					  hub-&gt;eng_distance * eng, 0x1, 0x1);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_emit_wreg(ring, hub-&gt;ctx0_ptb_addr_lo32 +</div><div class='add'>+			      (hub-&gt;ctx_addr_distance * vmid),</div><div class='add'>+			      lower_32_bits(pd_addr));</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_emit_wreg(ring, hub-&gt;ctx0_ptb_addr_hi32 +</div><div class='add'>+			      (hub-&gt;ctx_addr_distance * vmid),</div><div class='add'>+			      upper_32_bits(pd_addr));</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_emit_reg_write_reg_wait(ring, hub-&gt;vm_inv_eng0_req +</div><div class='add'>+					    hub-&gt;eng_distance * eng,</div><div class='add'>+					    hub-&gt;vm_inv_eng0_ack +</div><div class='add'>+					    hub-&gt;eng_distance * eng,</div><div class='add'>+					    req, 1 &lt;&lt; vmid);</div><div class='add'>+</div><div class='add'>+	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */</div><div class='add'>+	if (use_semaphore)</div><div class='add'>+		/*</div><div class='add'>+		 * add semaphore release after invalidation,</div><div class='add'>+		 * write with 0 means semaphore release</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_ring_emit_wreg(ring, hub-&gt;vm_inv_eng0_sem +</div><div class='add'>+				      hub-&gt;eng_distance * eng, 0);</div><div class='add'>+</div><div class='add'>+	return pd_addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,</div><div class='add'>+					 unsigned pasid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t reg;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;vm_hub == AMDGPU_GFXHUB(0))</div><div class='add'>+		reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;</div><div class='add'>+	else</div><div class='add'>+		reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_emit_wreg(ring, reg, pasid);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * PTE format:</div><div class='add'>+ * 63 P</div><div class='add'>+ * 62:59 reserved</div><div class='add'>+ * 58 D</div><div class='add'>+ * 57 G</div><div class='add'>+ * 56 T</div><div class='add'>+ * 55:54 M</div><div class='add'>+ * 53:52 SW</div><div class='add'>+ * 51:48 reserved for future</div><div class='add'>+ * 47:12 4k physical page base address</div><div class='add'>+ * 11:7 fragment</div><div class='add'>+ * 6 write</div><div class='add'>+ * 5 read</div><div class='add'>+ * 4 exe</div><div class='add'>+ * 3 Z</div><div class='add'>+ * 2 snooped</div><div class='add'>+ * 1 system</div><div class='add'>+ * 0 valid</div><div class='add'>+ *</div><div class='add'>+ * PDE format:</div><div class='add'>+ * 63 P</div><div class='add'>+ * 62:58 block fragment size</div><div class='add'>+ * 57 reserved</div><div class='add'>+ * 56 A</div><div class='add'>+ * 55:54 M</div><div class='add'>+ * 53:52 reserved</div><div class='add'>+ * 51:48 reserved for future</div><div class='add'>+ * 47:6 physical base address of PD or PTE</div><div class='add'>+ * 5:3 reserved</div><div class='add'>+ * 2 C</div><div class='add'>+ * 1 system</div><div class='add'>+ * 0 valid</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='add'>+				 uint64_t *addr, uint64_t *flags)</div><div class='add'>+{</div><div class='add'>+	if (!(*flags &amp; AMDGPU_PDE_PTE_GFX12) &amp;&amp; !(*flags &amp; AMDGPU_PTE_SYSTEM))</div><div class='add'>+		*addr = adev-&gt;vm_manager.vram_base_offset + *addr -</div><div class='add'>+			adev-&gt;gmc.vram_start;</div><div class='add'>+	BUG_ON(*addr &amp; 0xFFFF00000000003FULL);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gmc.translate_further)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (level == AMDGPU_VM_PDB1) {</div><div class='add'>+		/* Set the block fragment size */</div><div class='add'>+		if (!(*flags &amp; AMDGPU_PDE_PTE_GFX12))</div><div class='add'>+			*flags |= AMDGPU_PDE_BFS_GFX12(0x9);</div><div class='add'>+</div><div class='add'>+	} else if (level == AMDGPU_VM_PDB0) {</div><div class='add'>+		if (*flags &amp; AMDGPU_PDE_PTE_GFX12)</div><div class='add'>+			*flags &amp;= ~AMDGPU_PDE_PTE_GFX12;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='add'>+				 struct amdgpu_vm *vm,</div><div class='add'>+				 struct amdgpu_bo *bo,</div><div class='add'>+				 uint32_t vm_flags,</div><div class='add'>+				 uint64_t *flags)</div><div class='add'>+{</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_EXECUTABLE)</div><div class='add'>+		*flags |= AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+</div><div class='add'>+	switch (vm_flags &amp; AMDGPU_VM_MTYPE_MASK) {</div><div class='add'>+	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_NC:</div><div class='add'>+	default:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_UC:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_NOALLOC)</div><div class='add'>+		*flags |= AMDGPU_PTE_NOALLOC;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_NOALLOC;</div><div class='add'>+</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_PRT) {</div><div class='add'>+		*flags |= AMDGPU_PTE_PRT_GFX12;</div><div class='add'>+		*flags |= AMDGPU_PTE_SNOOPED;</div><div class='add'>+		*flags |= AMDGPU_PTE_SYSTEM;</div><div class='add'>+		*flags |= AMDGPU_PTE_IS_PTE;</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_VALID;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (bo &amp;&amp; bo-&gt;flags &amp; AMDGPU_GEM_CREATE_GFX12_DCC)</div><div class='add'>+		*flags |= AMDGPU_PTE_DCC;</div><div class='add'>+</div><div class='add'>+	if (bo &amp;&amp; bo-&gt;flags &amp; AMDGPU_GEM_CREATE_UNCACHED)</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	unsigned int max_tex_channel_caches, alignment;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	max_tex_channel_caches = adev-&gt;gfx.config.max_texture_channel_caches;</div><div class='add'>+	if (is_power_of_2(max_tex_channel_caches))</div><div class='add'>+		alignment = (unsigned int)(max_tex_channel_caches / SZ_4);</div><div class='add'>+	else</div><div class='add'>+		alignment = roundup_pow_of_two(max_tex_channel_caches);</div><div class='add'>+</div><div class='add'>+	return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = {</div><div class='add'>+	.flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb,</div><div class='add'>+	.flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid,</div><div class='add'>+	.emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb,</div><div class='add'>+	.emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping,</div><div class='add'>+	.get_vm_pde = gmc_v12_0_get_vm_pde,</div><div class='add'>+	.get_vm_pte = gmc_v12_0_get_vm_pte,</div><div class='add'>+	.get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size,</div><div class='add'>+	.get_dcc_alignment = gmc_v12_0_get_dcc_alignment,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;gmc.gmc_funcs = &amp;gmc_v12_0_gmc_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(8, 14, 0):</div><div class='add'>+		adev-&gt;umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM;</div><div class='add'>+		adev-&gt;umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev);</div><div class='add'>+		adev-&gt;umc.node_inst_num = 0;</div><div class='add'>+		adev-&gt;umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev);</div><div class='add'>+		adev-&gt;umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET;</div><div class='add'>+		adev-&gt;umc.ras = &amp;umc_v8_14_ras;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(4, 1, 0):</div><div class='add'>+		adev-&gt;mmhub.funcs = &amp;mmhub_v4_1_0_funcs;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		adev-&gt;gfxhub.funcs = &amp;gfxhub_v12_0_funcs;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	gmc_v12_0_set_gfxhub_funcs(adev);</div><div class='add'>+	gmc_v12_0_set_mmhub_funcs(adev);</div><div class='add'>+	gmc_v12_0_set_gmc_funcs(adev);</div><div class='add'>+	gmc_v12_0_set_irq_funcs(adev);</div><div class='add'>+	gmc_v12_0_set_umc_funcs(adev);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gmc.shared_aperture_start = 0x2000000000000000ULL;</div><div class='add'>+	adev-&gt;gmc.shared_aperture_end =</div><div class='add'>+		adev-&gt;gmc.shared_aperture_start + (4ULL &lt;&lt; 30) - 1;</div><div class='add'>+	adev-&gt;gmc.private_aperture_start = 0x1000000000000000ULL;</div><div class='add'>+	adev-&gt;gmc.private_aperture_end =</div><div class='add'>+		adev-&gt;gmc.private_aperture_start + (4ULL &lt;&lt; 30) - 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gmc_allocate_vm_inv_eng(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gmc_ras_late_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_irq_get(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_gmc *mc)</div><div class='add'>+{</div><div class='add'>+	u64 base = 0;</div><div class='add'>+</div><div class='add'>+	base = adev-&gt;mmhub.funcs-&gt;get_fb_location(adev);</div><div class='add'>+</div><div class='add'>+	amdgpu_gmc_set_agp_default(adev, mc);</div><div class='add'>+	amdgpu_gmc_vram_location(adev, &amp;adev-&gt;gmc, base);</div><div class='add'>+	amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (amdgpu_agp == 1))</div><div class='add'>+		amdgpu_gmc_agp_location(adev, mc);</div><div class='add'>+</div><div class='add'>+	/* base offset of vram pages */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vm_manager.vram_base_offset = 0;</div><div class='add'>+	else</div><div class='add'>+		adev-&gt;vm_manager.vram_base_offset = adev-&gt;mmhub.funcs-&gt;get_mc_fb_offset(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_mc_init - initialize the memory controller driver params</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Look up the amount of vram, vram width, and decide how to place</div><div class='add'>+ * vram and gart within the GPU's physical address space.</div><div class='add'>+ * Returns 0 for success.</div><div class='add'>+ */</div><div class='add'>+static int gmc_v12_0_mc_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/* size in MB on si */</div><div class='add'>+	adev-&gt;gmc.mc_vram_size =</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;get_memsize(adev) * 1024ULL * 1024ULL;</div><div class='add'>+	adev-&gt;gmc.real_vram_size = adev-&gt;gmc.mc_vram_size;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='add'>+		r = amdgpu_device_resize_fb_bar(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;gmc.aper_base = pci_resource_start(adev-&gt;pdev, 0);</div><div class='add'>+	adev-&gt;gmc.aper_size = pci_resource_len(adev-&gt;pdev, 0);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_X86_64</div><div class='add'>+	if ((adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; !amdgpu_passthrough(adev)) {</div><div class='add'>+		adev-&gt;gmc.aper_base = adev-&gt;mmhub.funcs-&gt;get_mc_fb_offset(adev);</div><div class='add'>+		adev-&gt;gmc.aper_size = adev-&gt;gmc.real_vram_size;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+	/* In case the PCI BAR is larger than the actual amount of vram */</div><div class='add'>+	adev-&gt;gmc.visible_vram_size = adev-&gt;gmc.aper_size;</div><div class='add'>+	if (adev-&gt;gmc.visible_vram_size &gt; adev-&gt;gmc.real_vram_size)</div><div class='add'>+		adev-&gt;gmc.visible_vram_size = adev-&gt;gmc.real_vram_size;</div><div class='add'>+</div><div class='add'>+	/* set the gart size */</div><div class='add'>+	if (amdgpu_gart_size == -1) {</div><div class='add'>+		adev-&gt;gmc.gart_size = 512ULL &lt;&lt; 20;</div><div class='add'>+	} else</div><div class='add'>+		adev-&gt;gmc.gart_size = (u64)amdgpu_gart_size &lt;&lt; 20;</div><div class='add'>+</div><div class='add'>+	gmc_v12_0_vram_gtt_location(adev, &amp;adev-&gt;gmc);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_gart_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gart.bo) {</div><div class='add'>+		WARN(1, "PCIE GART already initialized\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize common gart structure */</div><div class='add'>+	r = amdgpu_gart_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gart.table_size = adev-&gt;gart.num_gpu_pages * 8;</div><div class='add'>+	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) |</div><div class='add'>+				    AMDGPU_PTE_EXECUTABLE |</div><div class='add'>+				    AMDGPU_PTE_IS_PTE;</div><div class='add'>+</div><div class='add'>+	return amdgpu_gart_table_vram_alloc(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	adev-&gt;mmhub.funcs-&gt;init(adev);</div><div class='add'>+</div><div class='add'>+	adev-&gt;gfxhub.funcs-&gt;init(adev);</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;adev-&gt;gmc.invalidate_lock);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_atomfirmware_get_vram_info(adev,</div><div class='add'>+					      &amp;vram_width, &amp;vram_type, &amp;vram_vendor);</div><div class='add'>+	adev-&gt;gmc.vram_width = vram_width;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gmc.vram_type = vram_type;</div><div class='add'>+	adev-&gt;gmc.vram_vendor = vram_vendor;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		set_bit(AMDGPU_GFXHUB(0), adev-&gt;vmhubs_mask);</div><div class='add'>+		set_bit(AMDGPU_MMHUB0(0), adev-&gt;vmhubs_mask);</div><div class='add'>+		/*</div><div class='add'>+		 * To fulfill 4-level page support,</div><div class='add'>+		 * vm size is 256TB (48bit), maximum size,</div><div class='add'>+		 * block size 512 (9bit)</div><div class='add'>+		 */</div><div class='add'>+		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* This interrupt is VMC page fault.*/</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,</div><div class='add'>+			      VMC_1_0__SRCID__VM_FAULT,</div><div class='add'>+			      &amp;adev-&gt;gmc.vm_fault);</div><div class='add'>+</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,</div><div class='add'>+			      UTCL2_1_0__SRCID__FAULT,</div><div class='add'>+			      &amp;adev-&gt;gmc.vm_fault);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* interrupt sent to DF. */</div><div class='add'>+		r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,</div><div class='add'>+				      &amp;adev-&gt;gmc.ecc_irq);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set the internal MC address mask This is the max address of the GPU's</div><div class='add'>+	 * internal address space.</div><div class='add'>+	 */</div><div class='add'>+	adev-&gt;gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */</div><div class='add'>+</div><div class='add'>+	r = dma_set_mask_and_coherent(adev-&gt;dev, DMA_BIT_MASK(44));</div><div class='add'>+	if (r) {</div><div class='add'>+		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;need_swiotlb = drm_need_swiotlb(44);</div><div class='add'>+</div><div class='add'>+	r = gmc_v12_0_mc_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	amdgpu_gmc_get_vbios_allocations(adev);</div><div class='add'>+</div><div class='add'>+	/* Memory manager */</div><div class='add'>+	r = amdgpu_bo_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = gmc_v12_0_gart_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * number of VMs</div><div class='add'>+	 * VMID 0 is reserved for System</div><div class='add'>+	 * amdgpu graphics/compute will use VMIDs 1-7</div><div class='add'>+	 * amdkfd will use VMIDs 8-15</div><div class='add'>+	 */</div><div class='add'>+	adev-&gt;vm_manager.first_kfd_vmid = adev-&gt;gfx.disable_kq ? 1 : 8;</div><div class='add'>+</div><div class='add'>+	amdgpu_vm_manager_init(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_gmc_ras_sw_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_gart_fini - vm fini callback</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Tears down the driver GART/VM setup (CIK).</div><div class='add'>+ */</div><div class='add'>+static void gmc_v12_0_gart_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gart_table_vram_free(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	amdgpu_vm_manager_fini(adev);</div><div class='add'>+	gmc_v12_0_gart_fini(adev);</div><div class='add'>+	amdgpu_gem_force_release(adev);</div><div class='add'>+	amdgpu_bo_fini(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_gart_enable - gart enable</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ */</div><div class='add'>+static int gmc_v12_0_gart_enable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	bool value;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gart.bo == NULL) {</div><div class='add'>+		dev_err(adev-&gt;dev, "No VRAM object for PCIE GART.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_gtt_mgr_recover(&amp;adev-&gt;mman.gtt_mgr);</div><div class='add'>+</div><div class='add'>+	r = adev-&gt;mmhub.funcs-&gt;gart_enable(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* Flush HDP after it is initialized */</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='add'>+</div><div class='add'>+	value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS;</div><div class='add'>+</div><div class='add'>+	adev-&gt;mmhub.funcs-&gt;set_fault_enable_default(adev, value);</div><div class='add'>+	gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",</div><div class='add'>+		 (unsigned)(adev-&gt;gmc.gart_size &gt;&gt; 20),</div><div class='add'>+		 (unsigned long long)amdgpu_bo_gpu_offset(adev-&gt;gart.bo));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* The sequence of these two function calls matters.*/</div><div class='add'>+	gmc_v12_0_init_golden_registers(adev);</div><div class='add'>+</div><div class='add'>+	r = gmc_v12_0_gart_enable(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;umc.funcs &amp;&amp; adev-&gt;umc.funcs-&gt;init_registers)</div><div class='add'>+		adev-&gt;umc.funcs-&gt;init_registers(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gmc_v12_0_gart_disable - gart disable</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * This disables all VM page table.</div><div class='add'>+ */</div><div class='add'>+static void gmc_v12_0_gart_disable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;mmhub.funcs-&gt;gart_disable(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* full access mode, so don't touch any GMC register */</div><div class='add'>+		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.ecc_irq.funcs &amp;&amp;</div><div class='add'>+		amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='add'>+</div><div class='add'>+	gmc_v12_0_gart_disable(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	gmc_v12_0_hw_fini(ip_block);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = gmc_v12_0_hw_init(ip_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	amdgpu_vmid_reset_all(ip_block-&gt;adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	/* MC is always ready in GMC v11.*/</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	/* There is no need to wait for MC idle in GMC v11.*/</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					   enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	r = adev-&gt;mmhub.funcs-&gt;set_clockgating(adev, state);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return athub_v4_1_0_set_clockgating(adev, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	adev-&gt;mmhub.funcs-&gt;get_clockgating(adev, flags);</div><div class='add'>+</div><div class='add'>+	athub_v4_1_0_get_clockgating(adev, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					   enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amd_ip_funcs gmc_v12_0_ip_funcs = {</div><div class='add'>+	.name = "gmc_v12_0",</div><div class='add'>+	.early_init = gmc_v12_0_early_init,</div><div class='add'>+	.sw_init = gmc_v12_0_sw_init,</div><div class='add'>+	.hw_init = gmc_v12_0_hw_init,</div><div class='add'>+	.late_init = gmc_v12_0_late_init,</div><div class='add'>+	.sw_fini = gmc_v12_0_sw_fini,</div><div class='add'>+	.hw_fini = gmc_v12_0_hw_fini,</div><div class='add'>+	.suspend = gmc_v12_0_suspend,</div><div class='add'>+	.resume = gmc_v12_0_resume,</div><div class='add'>+	.is_idle = gmc_v12_0_is_idle,</div><div class='add'>+	.wait_for_idle = gmc_v12_0_wait_for_idle,</div><div class='add'>+	.set_clockgating_state = gmc_v12_0_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = gmc_v12_0_set_powergating_state,</div><div class='add'>+	.get_clockgating_state = gmc_v12_0_get_clockgating_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version gmc_v12_0_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_GMC,</div><div class='add'>+	.major = 12,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;gmc_v12_0_ip_funcs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.h<br/>new file mode 100644<br/>index 000000000000..deca93e4a156<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v12_0.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __GMC_V12_0_H__</div><div class='add'>+#define __GMC_V12_0_H__</div><div class='add'>+</div><div class='add'>+extern const struct amd_ip_funcs gmc_v12_0_ip_funcs;</div><div class='add'>+extern const struct amdgpu_ip_block_version gmc_v12_0_ip_block;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c<br/>index 23b478639921..a8ec95f42926 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c</a></div><div class='hunk'>@@ -43,7 +43,7 @@</div><div class='ctx'> </div><div class='ctx'> static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int gmc_v6_0_wait_for_idle(void *handle);</div><div class='add'>+static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");</div><div class='hunk'>@@ -64,8 +64,13 @@ MODULE_FIRMWARE("amdgpu/si58_mc.bin");</div><div class='ctx'> static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 blackout;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> </div><div class='del'>-	gmc_v6_0_wait_for_idle((void *)adev);</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	gmc_v6_0_wait_for_idle(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);</div><div class='ctx'> 	if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {</div><div class='hunk'>@@ -98,9 +103,7 @@ static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='del'>-	bool is_58_fw = false;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='ctx'> </div><div class='hunk'>@@ -126,17 +129,14 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	/* this memory configuration requires special firmware */</div><div class='ctx'> 	if (((RREG32(mmMC_SEQ_MISC0) &amp; 0xff000000) &gt;&gt; 24) == 0x58)</div><div class='del'>-		is_58_fw = true;</div><div class='add'>+		chip_name = "si58";</div><div class='ctx'> </div><div class='del'>-	if (is_58_fw)</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");</div><div class='del'>-	else</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gmc.fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gmc.fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mc.bin", chip_name);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='del'>-		       "si_mc: Failed to load firmware \"%s\"\n",</div><div class='del'>-		       fw_name);</div><div class='add'>+		       "si_mc: Failed to load firmware \"%s_mc.bin\"\n",</div><div class='add'>+		       chip_name);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gmc.fw);</div><div class='ctx'> 	}</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -213,12 +213,14 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gmc_set_agp_default(adev, mc);</div><div class='ctx'> 	amdgpu_gmc_vram_location(adev, mc, base);</div><div class='del'>-	amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);</div><div class='add'>+	amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v6_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize HDP */</div><div class='ctx'> 	for (i = 0, j = 0; i &lt; 32; i++, j += 0x6) {</div><div class='hunk'>@@ -230,7 +232,11 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);</div><div class='ctx'> </div><div class='del'>-	if (gmc_v6_0_wait_for_idle((void *)adev))</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (gmc_v6_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for MC idle timedout !\n");</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;mode_info.num_crtc) {</div><div class='hunk'>@@ -243,7 +249,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		/* disable VGA render */</div><div class='ctx'> 		tmp = RREG32(mmVGA_RENDER_CONTROL);</div><div class='del'>-		tmp &amp;= ~VGA_VSTATUS_CNTL;</div><div class='add'>+		tmp &amp;= VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK;</div><div class='ctx'> 		WREG32(mmVGA_RENDER_CONTROL, tmp);</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Update configuration */</div><div class='hunk'>@@ -257,7 +263,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 22);</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 22);</div><div class='ctx'> </div><div class='del'>-	if (gmc_v6_0_wait_for_idle((void *)adev))</div><div class='add'>+	if (gmc_v6_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for MC idle timedout !\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -376,7 +382,9 @@ static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				struct amdgpu_vm *vm,</div><div class='add'>+				struct amdgpu_bo *bo,</div><div class='add'>+				uint32_t vm_flags,</div><div class='ctx'> 				uint64_t *flags)</div><div class='ctx'> {</div><div class='ctx'> 	*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='hunk'>@@ -602,36 +610,33 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,</div><div class='del'>-				     u32 status, u32 addr, u32 mc_client)</div><div class='add'>+				     u32 status, u32 addr)</div><div class='ctx'> {</div><div class='ctx'> 	u32 mc_id;</div><div class='ctx'> 	u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);</div><div class='ctx'> 	u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='ctx'> 					PROTECTIONS);</div><div class='del'>-	char block[5] = { mc_client &gt;&gt; 24, (mc_client &gt;&gt; 16) &amp; 0xff,</div><div class='del'>-		(mc_client &gt;&gt; 8) &amp; 0xff, mc_client &amp; 0xff, 0 };</div><div class='ctx'> </div><div class='ctx'> 	mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='ctx'> 			      MEMORY_CLIENT_ID);</div><div class='ctx'> </div><div class='del'>-	dev_err(adev-&gt;dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",</div><div class='add'>+	dev_err(adev-&gt;dev, "VM fault (0x%02x, vmid %d) at page %u, %s from %d\n",</div><div class='ctx'> 	       protections, vmid, addr,</div><div class='ctx'> 	       REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='ctx'> 			     MEMORY_CLIENT_RW) ?</div><div class='del'>-	       "write" : "read", block, mc_client, mc_id);</div><div class='add'>+	       "write" : "read", mc_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='ctx'> static const u32 mc_cg_registers[] = {</div><div class='del'>-	MC_HUB_MISC_HUB_CG,</div><div class='del'>-	MC_HUB_MISC_SIP_CG,</div><div class='del'>-	MC_HUB_MISC_VM_CG,</div><div class='del'>-	MC_XPB_CLK_GAT,</div><div class='del'>-	ATC_MISC_CG,</div><div class='del'>-	MC_CITF_MISC_WR_CG,</div><div class='del'>-	MC_CITF_MISC_RD_CG,</div><div class='del'>-	MC_CITF_MISC_VM_CG,</div><div class='del'>-	VM_L2_CG,</div><div class='add'>+	mmMC_HUB_MISC_HUB_CG,</div><div class='add'>+	mmMC_HUB_MISC_SIP_CG,</div><div class='add'>+	mmMC_HUB_MISC_VM_CG,</div><div class='add'>+	mmMC_XPB_CLK_GAT,</div><div class='add'>+	mmATC_MISC_CG,</div><div class='add'>+	mmMC_CITF_MISC_WR_CG,</div><div class='add'>+	mmMC_CITF_MISC_RD_CG,</div><div class='add'>+	mmMC_CITF_MISC_VM_CG,</div><div class='add'>+	mmVM_L2_CG,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const u32 mc_cg_ls_en[] = {</div><div class='hunk'>@@ -666,7 +671,7 @@ static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(mc_cg_registers); i++) {</div><div class='ctx'> 		orig = data = RREG32(mc_cg_registers[i]);</div><div class='del'>-		if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMDGPU_CG_SUPPORT_MC_LS))</div><div class='add'>+		if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_MC_LS))</div><div class='ctx'> 			data |= mc_cg_ls_en[i];</div><div class='ctx'> 		else</div><div class='ctx'> 			data &amp;= ~mc_cg_ls_en[i];</div><div class='hunk'>@@ -683,7 +688,7 @@ static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(mc_cg_registers); i++) {</div><div class='ctx'> 		orig = data = RREG32(mc_cg_registers[i]);</div><div class='del'>-		if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMDGPU_CG_SUPPORT_MC_MGCG))</div><div class='add'>+		if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_MC_MGCG))</div><div class='ctx'> 			data |= mc_cg_en[i];</div><div class='ctx'> 		else</div><div class='ctx'> 			data &amp;= ~mc_cg_en[i];</div><div class='hunk'>@@ -699,7 +704,7 @@ static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	orig = data = RREG32_PCIE(ixPCIE_CNTL2);</div><div class='ctx'> </div><div class='del'>-	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMDGPU_CG_SUPPORT_BIF_LS)) {</div><div class='add'>+	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_BIF_LS)) {</div><div class='ctx'> 		data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);</div><div class='ctx'> 		data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);</div><div class='ctx'> 		data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);</div><div class='hunk'>@@ -722,7 +727,7 @@ static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);</div><div class='ctx'> </div><div class='del'>-	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMDGPU_CG_SUPPORT_HDP_MGCG))</div><div class='add'>+	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_HDP_MGCG))</div><div class='ctx'> 		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);</div><div class='ctx'> 	else</div><div class='ctx'> 		data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);</div><div class='hunk'>@@ -738,7 +743,7 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	orig = data = RREG32(mmHDP_MEM_POWER_LS);</div><div class='ctx'> </div><div class='del'>-	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMDGPU_CG_SUPPORT_HDP_LS))</div><div class='add'>+	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_HDP_LS))</div><div class='ctx'> 		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);</div><div class='ctx'> 	else</div><div class='ctx'> 		data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);</div><div class='hunk'>@@ -746,7 +751,6 @@ static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,</div><div class='ctx'> 	if (orig != data)</div><div class='ctx'> 		WREG32(mmHDP_MEM_POWER_LS, data);</div><div class='ctx'> }</div><div class='del'>-*/</div><div class='ctx'> </div><div class='ctx'> static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)</div><div class='ctx'> {</div><div class='hunk'>@@ -768,9 +772,9 @@ static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_early_init(void *handle)</div><div class='add'>+static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v6_0_set_gmc_funcs(adev);</div><div class='ctx'> 	gmc_v6_0_set_irq_funcs(adev);</div><div class='hunk'>@@ -778,9 +782,9 @@ static int gmc_v6_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_late_init(void *handle)</div><div class='add'>+static int gmc_v6_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)</div><div class='ctx'> 		return amdgpu_irq_get(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='hunk'>@@ -805,10 +809,10 @@ static unsigned int gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_sw_init(void *handle)</div><div class='add'>+static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	set_bit(AMDGPU_GFXHUB(0), adev-&gt;vmhubs_mask);</div><div class='ctx'> </div><div class='hunk'>@@ -882,9 +886,9 @@ static int gmc_v6_0_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_sw_fini(void *handle)</div><div class='add'>+static int gmc_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gem_force_release(adev);</div><div class='ctx'> 	amdgpu_vm_manager_fini(adev);</div><div class='hunk'>@@ -895,10 +899,10 @@ static int gmc_v6_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_hw_init(void *handle)</div><div class='add'>+static int gmc_v6_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v6_0_mc_program(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -920,9 +924,9 @@ static int gmc_v6_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_hw_fini(void *handle)</div><div class='add'>+static int gmc_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='ctx'> 	gmc_v6_0_gart_disable(adev);</div><div class='hunk'>@@ -930,21 +934,19 @@ static int gmc_v6_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_suspend(void *handle)</div><div class='add'>+static int gmc_v6_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	gmc_v6_0_hw_fini(adev);</div><div class='add'>+	gmc_v6_0_hw_fini(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_resume(void *handle)</div><div class='add'>+static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	r = gmc_v6_0_hw_init(adev);</div><div class='add'>+	r = gmc_v6_0_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -953,9 +955,10 @@ static int gmc_v6_0_resume(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v6_0_is_idle(void *handle)</div><div class='add'>+static bool gmc_v6_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |</div><div class='hunk'>@@ -965,13 +968,13 @@ static bool gmc_v6_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_wait_for_idle(void *handle)</div><div class='add'>+static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (gmc_v6_0_is_idle(handle))</div><div class='add'>+		if (gmc_v6_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -979,9 +982,10 @@ static int gmc_v6_0_wait_for_idle(void *handle)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_soft_reset(void *handle)</div><div class='add'>+static int gmc_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='hunk'>@@ -998,7 +1002,8 @@ static int gmc_v6_0_soft_reset(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	if (srbm_soft_reset) {</div><div class='ctx'> 		gmc_v6_0_mc_stop(adev);</div><div class='del'>-		if (gmc_v6_0_wait_for_idle(adev))</div><div class='add'>+</div><div class='add'>+		if (gmc_v6_0_wait_for_idle(ip_block))</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "Wait for GMC idle timed out !\n");</div><div class='ctx'> </div><div class='ctx'> 		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='hunk'>@@ -1065,6 +1070,12 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	u32 addr, status;</div><div class='ctx'> </div><div class='add'>+	/* Delegate to the soft IRQ handler ring */</div><div class='add'>+	if (adev-&gt;irq.ih_soft.enabled &amp;&amp; entry-&gt;ih != &amp;adev-&gt;irq.ih_soft) {</div><div class='add'>+		amdgpu_irq_delegate(adev, entry, 4);</div><div class='add'>+		return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);</div><div class='ctx'> 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);</div><div class='ctx'> 	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);</div><div class='hunk'>@@ -1072,6 +1083,10 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!addr &amp;&amp; !status)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	amdgpu_vm_update_fault_cache(adev, entry-&gt;pasid,</div><div class='add'>+				     ((u64)addr) &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='add'>+				     status, AMDGPU_GFXHUB(0));</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)</div><div class='ctx'> 		gmc_v6_0_set_fault_enable_default(adev, false);</div><div class='ctx'> </div><div class='hunk'>@@ -1082,19 +1097,33 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 			addr);</div><div class='ctx'> 		dev_err(adev-&gt;dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",</div><div class='ctx'> 			status);</div><div class='del'>-		gmc_v6_0_vm_decode_fault(adev, status, addr, 0);</div><div class='add'>+		gmc_v6_0_vm_decode_fault(adev, status, addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gmc_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool gate = false;</div><div class='add'>+</div><div class='add'>+	if (state == AMD_CG_STATE_GATE)</div><div class='add'>+		gate = true;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='add'>+		gmc_v6_0_enable_mc_mgcg(adev, gate);</div><div class='add'>+		gmc_v6_0_enable_mc_ls(adev, gate);</div><div class='add'>+	}</div><div class='add'>+	gmc_v6_0_enable_bif_mgls(adev, gate);</div><div class='add'>+	gmc_v6_0_enable_hdp_mgcg(adev, gate);</div><div class='add'>+	gmc_v6_0_enable_hdp_ls(adev, gate);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v6_0_set_powergating_state(void *handle,</div><div class='add'>+static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c<br/>index 3da7b6a2b00d..fbd0bf147f50 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c</a></div><div class='hunk'>@@ -52,7 +52,7 @@</div><div class='ctx'> </div><div class='ctx'> static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int gmc_v7_0_wait_for_idle(void *handle);</div><div class='add'>+static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");</div><div class='hunk'>@@ -87,9 +87,14 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> 	u32 blackout;</div><div class='ctx'> </div><div class='del'>-	gmc_v7_0_wait_for_idle((void *)adev);</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	gmc_v7_0_wait_for_idle(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);</div><div class='ctx'> 	if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {</div><div class='hunk'>@@ -130,7 +135,6 @@ static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='hunk'>@@ -153,11 +157,10 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);</div><div class='del'>-</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gmc.fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gmc.fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mc.bin", chip_name);</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("cik_mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gmc.fw);</div><div class='ctx'> 	}</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -254,9 +257,14 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,</div><div class='ctx'>  */</div><div class='ctx'> static void gmc_v7_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	/* Initialize HDP */</div><div class='ctx'> 	for (i = 0, j = 0; i &lt; 32; i++, j += 0x6) {</div><div class='ctx'> 		WREG32((0xb05 + j), 0x00000000);</div><div class='hunk'>@@ -267,7 +275,7 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);</div><div class='ctx'> </div><div class='del'>-	if (gmc_v7_0_wait_for_idle((void *)adev))</div><div class='add'>+	if (gmc_v7_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for MC idle timedout !\n");</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;mode_info.num_crtc) {</div><div class='hunk'>@@ -291,7 +299,7 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_BASE, 0);</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 22);</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 22);</div><div class='del'>-	if (gmc_v7_0_wait_for_idle((void *)adev))</div><div class='add'>+	if (gmc_v7_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for MC idle timedout !\n");</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);</div><div class='hunk'>@@ -496,7 +504,9 @@ static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				struct amdgpu_vm *vm,</div><div class='add'>+				struct amdgpu_bo *bo,</div><div class='add'>+				uint32_t vm_flags,</div><div class='ctx'> 				uint64_t *flags)</div><div class='ctx'> {</div><div class='ctx'> 	*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='hunk'>@@ -924,9 +934,9 @@ static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_early_init(void *handle)</div><div class='add'>+static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v7_0_set_gmc_funcs(adev);</div><div class='ctx'> 	gmc_v7_0_set_irq_funcs(adev);</div><div class='hunk'>@@ -943,9 +953,9 @@ static int gmc_v7_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_late_init(void *handle)</div><div class='add'>+static int gmc_v7_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)</div><div class='ctx'> 		return amdgpu_irq_get(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='hunk'>@@ -971,10 +981,10 @@ static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_sw_init(void *handle)</div><div class='add'>+static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	set_bit(AMDGPU_GFXHUB(0), adev-&gt;vmhubs_mask);</div><div class='ctx'> </div><div class='hunk'>@@ -1058,14 +1068,14 @@ static int gmc_v7_0_sw_init(void *handle)</div><div class='ctx'> 					GFP_KERNEL);</div><div class='ctx'> 	if (!adev-&gt;gmc.vm_fault_info)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	atomic_set(&amp;adev-&gt;gmc.vm_fault_info_updated, 0);</div><div class='add'>+	atomic_set_release(&amp;adev-&gt;gmc.vm_fault_info_updated, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_sw_fini(void *handle)</div><div class='add'>+static int gmc_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gem_force_release(adev);</div><div class='ctx'> 	amdgpu_vm_manager_fini(adev);</div><div class='hunk'>@@ -1077,10 +1087,10 @@ static int gmc_v7_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_hw_init(void *handle)</div><div class='add'>+static int gmc_v7_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v7_0_init_golden_registers(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1104,9 +1114,9 @@ static int gmc_v7_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_hw_fini(void *handle)</div><div class='add'>+static int gmc_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='ctx'> 	gmc_v7_0_gart_disable(adev);</div><div class='hunk'>@@ -1114,32 +1124,29 @@ static int gmc_v7_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_suspend(void *handle)</div><div class='add'>+static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	gmc_v7_0_hw_fini(adev);</div><div class='add'>+	gmc_v7_0_hw_fini(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_resume(void *handle)</div><div class='add'>+static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = gmc_v7_0_hw_init(adev);</div><div class='add'>+	r = gmc_v7_0_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vmid_reset_all(adev);</div><div class='add'>+	amdgpu_vmid_reset_all(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v7_0_is_idle(void *handle)</div><div class='add'>+static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |</div><div class='hunk'>@@ -1149,20 +1156,13 @@ static bool gmc_v7_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_wait_for_idle(void *handle)</div><div class='add'>+static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		/* read MC_STATUS */</div><div class='del'>-		tmp = RREG32(mmSRBM_STATUS) &amp; (SRBM_STATUS__MCB_BUSY_MASK |</div><div class='del'>-					       SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |</div><div class='del'>-					       SRBM_STATUS__MCC_BUSY_MASK |</div><div class='del'>-					       SRBM_STATUS__MCD_BUSY_MASK |</div><div class='del'>-					       SRBM_STATUS__VMC_BUSY_MASK);</div><div class='del'>-		if (!tmp)</div><div class='add'>+		if (gmc_v7_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1170,9 +1170,9 @@ static int gmc_v7_0_wait_for_idle(void *handle)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_soft_reset(void *handle)</div><div class='add'>+static int gmc_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='hunk'>@@ -1189,7 +1189,7 @@ static int gmc_v7_0_soft_reset(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	if (srbm_soft_reset) {</div><div class='ctx'> 		gmc_v7_0_mc_stop(adev);</div><div class='del'>-		if (gmc_v7_0_wait_for_idle((void *)adev))</div><div class='add'>+		if (gmc_v7_0_wait_for_idle(ip_block))</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "Wait for GMC idle timed out !\n");</div><div class='ctx'> </div><div class='ctx'> 		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='hunk'>@@ -1261,6 +1261,12 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	u32 addr, status, mc_client, vmid;</div><div class='ctx'> </div><div class='add'>+	/* Delegate to the soft IRQ handler ring */</div><div class='add'>+	if (adev-&gt;irq.ih_soft.enabled &amp;&amp; entry-&gt;ih != &amp;adev-&gt;irq.ih_soft) {</div><div class='add'>+		amdgpu_irq_delegate(adev, entry, 4);</div><div class='add'>+		return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);</div><div class='ctx'> 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);</div><div class='ctx'> 	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);</div><div class='hunk'>@@ -1290,7 +1296,7 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='ctx'> 			     VMID);</div><div class='ctx'> 	if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)</div><div class='del'>-		&amp;&amp; !atomic_read(&amp;adev-&gt;gmc.vm_fault_info_updated)) {</div><div class='add'>+		&amp;&amp; !atomic_read_acquire(&amp;adev-&gt;gmc.vm_fault_info_updated)) {</div><div class='ctx'> 		struct kfd_vm_fault_info *info = adev-&gt;gmc.vm_fault_info;</div><div class='ctx'> 		u32 protections = REG_GET_FIELD(status,</div><div class='ctx'> 					VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='hunk'>@@ -1306,18 +1312,17 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		info-&gt;prot_read = protections &amp; 0x8 ? true : false;</div><div class='ctx'> 		info-&gt;prot_write = protections &amp; 0x10 ? true : false;</div><div class='ctx'> 		info-&gt;prot_exec = protections &amp; 0x20 ? true : false;</div><div class='del'>-		mb();</div><div class='del'>-		atomic_set(&amp;adev-&gt;gmc.vm_fault_info_updated, 1);</div><div class='add'>+		atomic_set_release(&amp;adev-&gt;gmc.vm_fault_info_updated, 1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gmc_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_CG_STATE_GATE)</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -1333,7 +1338,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v7_0_set_powergating_state(void *handle,</div><div class='add'>+static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c<br/>index d20e5f20ee31..6551b60f2584 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c</a></div><div class='hunk'>@@ -53,7 +53,7 @@</div><div class='ctx'> </div><div class='ctx'> static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int gmc_v8_0_wait_for_idle(void *handle);</div><div class='add'>+static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/tonga_mc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");</div><div class='hunk'>@@ -170,8 +170,13 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='ctx'> static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 blackout;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> </div><div class='del'>-	gmc_v8_0_wait_for_idle(adev);</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	gmc_v8_0_wait_for_idle(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);</div><div class='ctx'> 	if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {</div><div class='hunk'>@@ -212,7 +217,6 @@ static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='hunk'>@@ -255,10 +259,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gmc.fw, fw_name);</div><div class='add'>+	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gmc.fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				   "amdgpu/%s_mc.bin", chip_name);</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gmc.fw);</div><div class='ctx'> 	}</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -428,6 +432,7 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,</div><div class='ctx'>  */</div><div class='ctx'> static void gmc_v8_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='hunk'>@@ -441,7 +446,11 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);</div><div class='ctx'> </div><div class='del'>-	if (gmc_v8_0_wait_for_idle((void *)adev))</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (gmc_v8_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for MC idle timedout !\n");</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;mode_info.num_crtc) {</div><div class='hunk'>@@ -476,7 +485,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_BASE, 0);</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 22);</div><div class='ctx'> 	WREG32(mmMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 22);</div><div class='del'>-	if (gmc_v8_0_wait_for_idle((void *)adev))</div><div class='add'>+	if (gmc_v8_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for MC idle timedout !\n");</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);</div><div class='hunk'>@@ -707,11 +716,15 @@ static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				struct amdgpu_vm *vm,</div><div class='add'>+				struct amdgpu_bo *bo,</div><div class='add'>+				uint32_t vm_flags,</div><div class='ctx'> 				uint64_t *flags)</div><div class='ctx'> {</div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='del'>-	*flags |= mapping-&gt;flags &amp; AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_EXECUTABLE)</div><div class='add'>+		*flags |= AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> 	*flags &amp;= ~AMDGPU_PTE_PRT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1029,9 +1042,9 @@ static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_early_init(void *handle)</div><div class='add'>+static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v8_0_set_gmc_funcs(adev);</div><div class='ctx'> 	gmc_v8_0_set_irq_funcs(adev);</div><div class='hunk'>@@ -1048,9 +1061,9 @@ static int gmc_v8_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_late_init(void *handle)</div><div class='add'>+static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)</div><div class='ctx'> 		return amdgpu_irq_get(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='hunk'>@@ -1078,10 +1091,10 @@ static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> #define mmMC_SEQ_MISC0_FIJI 0xA71</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_sw_init(void *handle)</div><div class='add'>+static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	set_bit(AMDGPU_GFXHUB(0), adev-&gt;vmhubs_mask);</div><div class='ctx'> </div><div class='hunk'>@@ -1170,14 +1183,14 @@ static int gmc_v8_0_sw_init(void *handle)</div><div class='ctx'> 					GFP_KERNEL);</div><div class='ctx'> 	if (!adev-&gt;gmc.vm_fault_info)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	atomic_set(&amp;adev-&gt;gmc.vm_fault_info_updated, 0);</div><div class='add'>+	atomic_set_release(&amp;adev-&gt;gmc.vm_fault_info_updated, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_sw_fini(void *handle)</div><div class='add'>+static int gmc_v8_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gem_force_release(adev);</div><div class='ctx'> 	amdgpu_vm_manager_fini(adev);</div><div class='hunk'>@@ -1189,10 +1202,10 @@ static int gmc_v8_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_hw_init(void *handle)</div><div class='add'>+static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v8_0_init_golden_registers(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1224,9 +1237,9 @@ static int gmc_v8_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_hw_fini(void *handle)</div><div class='add'>+static int gmc_v8_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='ctx'> 	gmc_v8_0_gart_disable(adev);</div><div class='hunk'>@@ -1234,32 +1247,29 @@ static int gmc_v8_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_suspend(void *handle)</div><div class='add'>+static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	gmc_v8_0_hw_fini(adev);</div><div class='add'>+	gmc_v8_0_hw_fini(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_resume(void *handle)</div><div class='add'>+static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = gmc_v8_0_hw_init(adev);</div><div class='add'>+	r = gmc_v8_0_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vmid_reset_all(adev);</div><div class='add'>+	amdgpu_vmid_reset_all(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v8_0_is_idle(void *handle)</div><div class='add'>+static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |</div><div class='hunk'>@@ -1269,11 +1279,11 @@ static bool gmc_v8_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_wait_for_idle(void *handle)</div><div class='add'>+static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -1291,10 +1301,10 @@ static int gmc_v8_0_wait_for_idle(void *handle)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v8_0_check_soft_reset(void *handle)</div><div class='add'>+static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS__VMC_BUSY_MASK)</div><div class='hunk'>@@ -1318,23 +1328,23 @@ static bool gmc_v8_0_check_soft_reset(void *handle)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_pre_soft_reset(void *handle)</div><div class='add'>+static int gmc_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;gmc.srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v8_0_mc_stop(adev);</div><div class='del'>-	if (gmc_v8_0_wait_for_idle(adev))</div><div class='add'>+	if (gmc_v8_0_wait_for_idle(ip_block))</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "Wait for GMC idle timed out !\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_soft_reset(void *handle)</div><div class='add'>+static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;gmc.srbm_soft_reset)</div><div class='hunk'>@@ -1363,9 +1373,9 @@ static int gmc_v8_0_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_post_soft_reset(void *handle)</div><div class='add'>+static int gmc_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;gmc.srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1429,6 +1439,12 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Delegate to the soft IRQ handler ring */</div><div class='add'>+	if (adev-&gt;irq.ih_soft.enabled &amp;&amp; entry-&gt;ih != &amp;adev-&gt;irq.ih_soft) {</div><div class='add'>+		amdgpu_irq_delegate(adev, entry, 4);</div><div class='add'>+		return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);</div><div class='ctx'> 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);</div><div class='ctx'> 	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);</div><div class='hunk'>@@ -1452,9 +1468,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 		task_info = amdgpu_vm_get_task_info_pasid(adev, entry-&gt;pasid);</div><div class='ctx'> 		if (task_info) {</div><div class='del'>-			dev_err(adev-&gt;dev, " for process %s pid %d thread %s pid %d\n",</div><div class='del'>-				task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='del'>-				task_info-&gt;task_name, task_info-&gt;pid);</div><div class='add'>+			amdgpu_vm_print_task_info(adev, task_info);</div><div class='ctx'> 			amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1470,7 +1484,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='ctx'> 			     VMID);</div><div class='ctx'> 	if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)</div><div class='del'>-		&amp;&amp; !atomic_read(&amp;adev-&gt;gmc.vm_fault_info_updated)) {</div><div class='add'>+		&amp;&amp; !atomic_read_acquire(&amp;adev-&gt;gmc.vm_fault_info_updated)) {</div><div class='ctx'> 		struct kfd_vm_fault_info *info = adev-&gt;gmc.vm_fault_info;</div><div class='ctx'> 		u32 protections = REG_GET_FIELD(status,</div><div class='ctx'> 					VM_CONTEXT1_PROTECTION_FAULT_STATUS,</div><div class='hunk'>@@ -1486,8 +1500,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		info-&gt;prot_read = protections &amp; 0x8 ? true : false;</div><div class='ctx'> 		info-&gt;prot_write = protections &amp; 0x10 ? true : false;</div><div class='ctx'> 		info-&gt;prot_exec = protections &amp; 0x20 ? true : false;</div><div class='del'>-		mb();</div><div class='del'>-		atomic_set(&amp;adev-&gt;gmc.vm_fault_info_updated, 1);</div><div class='add'>+		atomic_set_release(&amp;adev-&gt;gmc.vm_fault_info_updated, 1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1653,10 +1666,10 @@ static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1674,15 +1687,15 @@ static int gmc_v8_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v8_0_set_powergating_state(void *handle,</div><div class='add'>+static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gmc_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br/>index 47b63a4ce68b..8ad7519f7b58 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c</a></div><div class='hunk'>@@ -78,8 +78,6 @@</div><div class='ctx'> #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2                                                          0x05ea</div><div class='ctx'> #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX                                                 2</div><div class='ctx'> </div><div class='del'>-#define MAX_MEM_RANGES 8</div><div class='del'>-</div><div class='ctx'> static const char * const gfxhub_client_ids[] = {</div><div class='ctx'> 	"CB",</div><div class='ctx'> 	"DB",</div><div class='hunk'>@@ -546,9 +544,11 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 				      struct amdgpu_irq_src *source,</div><div class='ctx'> 				      struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	bool retry_fault = !!(entry-&gt;src_data[1] &amp; 0x80);</div><div class='del'>-	bool write_fault = !!(entry-&gt;src_data[1] &amp; 0x20);</div><div class='del'>-	uint32_t status = 0, cid = 0, rw = 0;</div><div class='add'>+	bool retry_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY);</div><div class='add'>+	bool write_fault = !!(entry-&gt;src_data[1] &amp;</div><div class='add'>+			      AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE);</div><div class='add'>+	uint32_t status = 0, cid = 0, rw = 0, fed = 0;</div><div class='ctx'> 	struct amdgpu_task_info *task_info;</div><div class='ctx'> 	struct amdgpu_vmhub *hub;</div><div class='ctx'> 	const char *mmhub_cid;</div><div class='hunk'>@@ -595,7 +595,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 			cam_index = entry-&gt;src_data[2] &amp; 0x3ff;</div><div class='ctx'> </div><div class='ctx'> 			ret = amdgpu_vm_handle_fault(adev, entry-&gt;pasid, entry-&gt;vmid, node_id,</div><div class='del'>-						     addr, write_fault);</div><div class='add'>+						     addr, entry-&gt;timestamp, write_fault);</div><div class='ctx'> 			WDOORBELL32(adev-&gt;irq.retry_cam_doorbell_index, cam_index);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return 1;</div><div class='hunk'>@@ -618,11 +618,14 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 			 * tables</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (amdgpu_vm_handle_fault(adev, entry-&gt;pasid, entry-&gt;vmid, node_id,</div><div class='del'>-						   addr, write_fault))</div><div class='add'>+						   addr, entry-&gt;timestamp, write_fault))</div><div class='ctx'> 				return 1;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault))</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='ctx'> 	if (!printk_ratelimit())</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -633,10 +636,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	task_info = amdgpu_vm_get_task_info_pasid(adev, entry-&gt;pasid);</div><div class='ctx'> 	if (task_info) {</div><div class='del'>-		dev_err(adev-&gt;dev,</div><div class='del'>-			" for process %s pid %d thread %s pid %d)\n",</div><div class='del'>-			task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='del'>-			task_info-&gt;task_name, task_info-&gt;pid);</div><div class='add'>+		amdgpu_vm_print_task_info(adev, task_info);</div><div class='ctx'> 		amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -644,7 +644,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 		addr, entry-&gt;client_id,</div><div class='ctx'> 		soc15_ih_clientid_name[entry-&gt;client_id]);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	if (amdgpu_is_multi_aid(adev))</div><div class='ctx'> 		dev_err(adev-&gt;dev, "  cookie node_id %d fault from die %s%d%s\n",</div><div class='ctx'> 			node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,</div><div class='ctx'> 			node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");</div><div class='hunk'>@@ -664,7 +664,21 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	status = RREG32(hub-&gt;vm_l2_pro_fault_status);</div><div class='ctx'> 	cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);</div><div class='ctx'> 	rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);</div><div class='del'>-	WREG32_P(hub-&gt;vm_l2_pro_fault_cntl, 1, ~1);</div><div class='add'>+	fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);</div><div class='add'>+</div><div class='add'>+	/* for fed error, kfd will handle it, return directly */</div><div class='add'>+	if (fed &amp;&amp; amdgpu_ras_is_poison_mode_supported(adev) &amp;&amp;</div><div class='add'>+	    (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(9, 4, 2)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Only print L2 fault status if the status register could be read and</div><div class='add'>+	 * contains useful information</div><div class='add'>+	 */</div><div class='add'>+	if (!status)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		WREG32_P(hub-&gt;vm_l2_pro_fault_cntl, 1, ~1);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_vm_update_fault_cache(adev, entry-&gt;pasid, addr, status, vmhub);</div><div class='ctx'> </div><div class='hunk'>@@ -779,7 +793,7 @@ static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,</div><div class='ctx'> 				       uint32_t vmhub)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||</div><div class='del'>-	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	    amdgpu_is_multi_aid(adev))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	return ((vmhub == AMDGPU_MMHUB0(0) ||</div><div class='hunk'>@@ -835,7 +849,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	ack = hub-&gt;vm_inv_eng0_ack + hub-&gt;eng_distance * eng;</div><div class='ctx'> </div><div class='ctx'> 	if (vmhub &gt;= AMDGPU_MMHUB0(0))</div><div class='del'>-		inst = GET_INST(GC, 0);</div><div class='add'>+		inst = 0;</div><div class='ctx'> 	else</div><div class='ctx'> 		inst = vmhub;</div><div class='ctx'> </div><div class='hunk'>@@ -867,9 +881,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='ctx'> 			/* a read return value of 1 means semaphore acquire */</div><div class='ctx'> 			if (vmhub &gt;= AMDGPU_MMHUB0(0))</div><div class='del'>-				tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst);</div><div class='add'>+				tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));</div><div class='ctx'> 			else</div><div class='del'>-				tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst);</div><div class='add'>+				tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));</div><div class='ctx'> 			if (tmp &amp; 0x1)</div><div class='ctx'> 				break;</div><div class='ctx'> 			udelay(1);</div><div class='hunk'>@@ -880,9 +894,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (vmhub &gt;= AMDGPU_MMHUB0(0))</div><div class='del'>-		WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst);</div><div class='add'>+		WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));</div><div class='ctx'> 	else</div><div class='del'>-		WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst);</div><div class='add'>+		WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Issue a dummy read to wait for the ACK register to</div><div class='hunk'>@@ -895,9 +909,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='ctx'> 		if (vmhub &gt;= AMDGPU_MMHUB0(0))</div><div class='del'>-			tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst);</div><div class='add'>+			tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));</div><div class='ctx'> 		else</div><div class='del'>-			tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst);</div><div class='add'>+			tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));</div><div class='ctx'> 		if (tmp &amp; (1 &lt;&lt; vmid))</div><div class='ctx'> 			break;</div><div class='ctx'> 		udelay(1);</div><div class='hunk'>@@ -910,9 +924,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 		 * write with 0 means semaphore release</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (vmhub &gt;= AMDGPU_MMHUB0(0))</div><div class='del'>-			WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst);</div><div class='add'>+			WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));</div><div class='ctx'> 		else</div><div class='del'>-			WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst);</div><div class='add'>+			WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock(&amp;adev-&gt;gmc.invalidate_lock);</div><div class='hunk'>@@ -1061,27 +1075,6 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int v</div><div class='ctx'>  * 0 valid</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)</div><div class='del'>-</div><div class='del'>-{</div><div class='del'>-	switch (flags) {</div><div class='del'>-	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_NC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_WC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_RW:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);</div><div class='del'>-	case AMDGPU_VM_MTYPE_CC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);</div><div class='del'>-	case AMDGPU_VM_MTYPE_UC:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);</div><div class='del'>-	default:</div><div class='del'>-		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> 				uint64_t *addr, uint64_t *flags)</div><div class='ctx'> {</div><div class='hunk'>@@ -1109,21 +1102,26 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,</div><div class='add'>+					 struct amdgpu_vm *vm,</div><div class='ctx'> 					 struct amdgpu_bo *bo,</div><div class='del'>-					 struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+					 uint32_t vm_flags,</div><div class='ctx'> 					 uint64_t *flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='del'>-	bool is_vram = bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM;</div><div class='del'>-	bool coherent = bo-&gt;flags &amp; (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT);</div><div class='add'>+	bool is_vram = bo-&gt;tbo.resource &amp;&amp;</div><div class='add'>+		bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_VRAM;</div><div class='add'>+	bool coherent = bo-&gt;flags &amp; (AMDGPU_GEM_CREATE_COHERENT |</div><div class='add'>+				     AMDGPU_GEM_CREATE_EXT_COHERENT);</div><div class='ctx'> 	bool ext_coherent = bo-&gt;flags &amp; AMDGPU_GEM_CREATE_EXT_COHERENT;</div><div class='ctx'> 	bool uncached = bo-&gt;flags &amp; AMDGPU_GEM_CREATE_UNCACHED;</div><div class='del'>-	struct amdgpu_vm *vm = mapping-&gt;bo_va-&gt;base.vm;</div><div class='ctx'> 	unsigned int mtype_local, mtype;</div><div class='add'>+	uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0);</div><div class='ctx'> 	bool snoop = false;</div><div class='ctx'> 	bool is_local;</div><div class='ctx'> </div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	dma_resv_assert_held(bo-&gt;tbo.base.resv);</div><div class='add'>+</div><div class='add'>+	switch (gc_ip_version) {</div><div class='ctx'> 	case IP_VERSION(9, 4, 1):</div><div class='ctx'> 	case IP_VERSION(9, 4, 2):</div><div class='ctx'> 		if (is_vram) {</div><div class='hunk'>@@ -1137,10 +1135,7 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,</div><div class='ctx'> 				/* FIXME: is this still needed? Or does</div><div class='ctx'> 				 * amdgpu_ttm_tt_pde_flags already handle this?</div><div class='ctx'> 				 */</div><div class='del'>-				if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='del'>-					     IP_VERSION(9, 4, 2) ||</div><div class='del'>-				     amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='del'>-					     IP_VERSION(9, 4, 3)) &amp;&amp;</div><div class='add'>+				if (gc_ip_version == IP_VERSION(9, 4, 2) &amp;&amp;</div><div class='ctx'> 				    adev-&gt;gmc.xgmi.connected_to_cpu)</div><div class='ctx'> 					snoop = true;</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -1148,7 +1143,7 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,</div><div class='ctx'> 					mtype = MTYPE_UC;</div><div class='ctx'> 				else</div><div class='ctx'> 					mtype = MTYPE_NC;</div><div class='del'>-				if (mapping-&gt;bo_va-&gt;is_xgmi)</div><div class='add'>+				if (amdgpu_xgmi_same_hive(adev, bo_adev))</div><div class='ctx'> 					snoop = true;</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -1163,6 +1158,8 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		/* Only local VRAM BOs or system memory on non-NUMA APUs</div><div class='ctx'> 		 * can be assumed to be local in their entirety. Choose</div><div class='ctx'> 		 * MTYPE_NC as safe fallback for all system memory BOs on</div><div class='hunk'>@@ -1187,20 +1184,17 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,</div><div class='ctx'> 		if (uncached) {</div><div class='ctx'> 			mtype = MTYPE_UC;</div><div class='ctx'> 		} else if (ext_coherent) {</div><div class='del'>-			if (adev-&gt;rev_id)</div><div class='del'>-				mtype = is_local ? MTYPE_CC : MTYPE_UC;</div><div class='del'>-			else</div><div class='del'>-				mtype = MTYPE_UC;</div><div class='add'>+			mtype = is_local ? MTYPE_CC : MTYPE_UC;</div><div class='ctx'> 		} else if (adev-&gt;flags &amp; AMD_IS_APU) {</div><div class='ctx'> 			mtype = is_local ? mtype_local : MTYPE_NC;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* dGPU */</div><div class='ctx'> 			if (is_local)</div><div class='ctx'> 				mtype = mtype_local;</div><div class='del'>-			else if (is_vram)</div><div class='del'>-				mtype = MTYPE_NC;</div><div class='del'>-			else</div><div class='add'>+			else if (gc_ip_version &lt; IP_VERSION(9, 5, 0) &amp;&amp; !is_vram)</div><div class='ctx'> 				mtype = MTYPE_UC;</div><div class='add'>+			else</div><div class='add'>+				mtype = MTYPE_NC;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1218,31 +1212,49 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (mtype != MTYPE_NC)</div><div class='del'>-		*flags = (*flags &amp; ~AMDGPU_PTE_MTYPE_VG10_MASK) |</div><div class='del'>-			 AMDGPU_PTE_MTYPE_VG10(mtype);</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype);</div><div class='add'>+</div><div class='ctx'> 	*flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_bo_va_mapping *mapping,</div><div class='add'>+				struct amdgpu_vm *vm,</div><div class='add'>+				struct amdgpu_bo *bo,</div><div class='add'>+				uint32_t vm_flags,</div><div class='ctx'> 				uint64_t *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_bo *bo = mapping-&gt;bo_va-&gt;base.bo;</div><div class='del'>-</div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='del'>-	*flags |= mapping-&gt;flags &amp; AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_EXECUTABLE)</div><div class='add'>+		*flags |= AMDGPU_PTE_EXECUTABLE;</div><div class='add'>+	else</div><div class='add'>+		*flags &amp;= ~AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> </div><div class='del'>-	*flags &amp;= ~AMDGPU_PTE_MTYPE_VG10_MASK;</div><div class='del'>-	*flags |= mapping-&gt;flags &amp; AMDGPU_PTE_MTYPE_VG10_MASK;</div><div class='add'>+	switch (vm_flags &amp; AMDGPU_VM_MTYPE_MASK) {</div><div class='add'>+	case AMDGPU_VM_MTYPE_DEFAULT:</div><div class='add'>+	case AMDGPU_VM_MTYPE_NC:</div><div class='add'>+	default:</div><div class='add'>+		*flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_NC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_WC:</div><div class='add'>+		*flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_WC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_RW:</div><div class='add'>+		*flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_RW);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_CC:</div><div class='add'>+		*flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VM_MTYPE_UC:</div><div class='add'>+		*flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_UC);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (mapping-&gt;flags &amp; AMDGPU_PTE_PRT) {</div><div class='add'>+	if (vm_flags &amp; AMDGPU_VM_PAGE_PRT) {</div><div class='ctx'> 		*flags |= AMDGPU_PTE_PRT;</div><div class='ctx'> 		*flags &amp;= ~AMDGPU_PTE_VALID;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (bo &amp;&amp; bo-&gt;tbo.resource)</div><div class='del'>-		gmc_v9_0_get_coherence_flags(adev, mapping-&gt;bo_va-&gt;base.bo,</div><div class='del'>-					     mapping, flags);</div><div class='add'>+	if ((*flags &amp; AMDGPU_PTE_VALID) &amp;&amp; bo)</div><div class='add'>+		gmc_v9_0_get_coherence_flags(adev, vm, bo, vm_flags, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,</div><div class='hunk'>@@ -1254,7 +1266,8 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,</div><div class='ctx'> 	/* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system</div><div class='ctx'> 	 * memory can use more efficient MTYPEs.</div><div class='ctx'> 	 */</div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU) ||</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* Only direct-mapped memory allows us to determine the NUMA node from</div><div class='hunk'>@@ -1270,9 +1283,9 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,</div><div class='ctx'> 	 * and can also be overridden.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if ((*flags &amp; AMDGPU_PTE_MTYPE_VG10_MASK) !=</div><div class='del'>-	    AMDGPU_PTE_MTYPE_VG10(MTYPE_NC) &amp;&amp;</div><div class='add'>+	    AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) &amp;&amp;</div><div class='ctx'> 	    (*flags &amp; AMDGPU_PTE_MTYPE_VG10_MASK) !=</div><div class='del'>-	    AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)) {</div><div class='add'>+	    AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) {</div><div class='ctx'> 		dev_dbg_ratelimited(adev-&gt;dev, "MTYPE is not NC or UC\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1301,7 +1314,7 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,</div><div class='ctx'> 	if (nid == local_node) {</div><div class='ctx'> 		uint64_t old_flags = *flags;</div><div class='ctx'> 		if ((*flags &amp; AMDGPU_PTE_MTYPE_VG10_MASK) ==</div><div class='del'>-			AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) {</div><div class='add'>+			AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) {</div><div class='ctx'> 			unsigned int mtype_local = MTYPE_RW;</div><div class='ctx'> </div><div class='ctx'> 			if (amdgpu_mtype_local == 1)</div><div class='hunk'>@@ -1309,12 +1322,10 @@ static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,</div><div class='ctx'> 			else if (amdgpu_mtype_local == 2)</div><div class='ctx'> 				mtype_local = MTYPE_CC;</div><div class='ctx'> </div><div class='del'>-			*flags = (*flags &amp; ~AMDGPU_PTE_MTYPE_VG10_MASK) |</div><div class='del'>-				 AMDGPU_PTE_MTYPE_VG10(mtype_local);</div><div class='del'>-		} else if (adev-&gt;rev_id) {</div><div class='add'>+			*flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local);</div><div class='add'>+		} else {</div><div class='ctx'> 			/* MTYPE_UC case */</div><div class='del'>-			*flags = (*flags &amp; ~AMDGPU_PTE_MTYPE_VG10_MASK) |</div><div class='del'>-				 AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);</div><div class='add'>+			*flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dev_dbg_ratelimited(adev-&gt;dev, "flags updated from %llx to %llx\n",</div><div class='hunk'>@@ -1364,25 +1375,15 @@ static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)</div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum amdgpu_memory_partition</div><div class='del'>-gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)</div><div class='add'>+static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;nbio.funcs-&gt;get_memory_partition_mode)</div><div class='del'>-		mode = adev-&gt;nbio.funcs-&gt;get_memory_partition_mode(adev,</div><div class='del'>-								   supp_modes);</div><div class='del'>-</div><div class='del'>-	return mode;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static enum amdgpu_memory_partition</div><div class='del'>-gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		return AMDGPU_NPS1_PARTITION_MODE;</div><div class='add'>+	if (adev-&gt;nbio.funcs &amp;&amp; adev-&gt;nbio.funcs-&gt;is_nps_switch_requested &amp;&amp;</div><div class='add'>+	    adev-&gt;nbio.funcs-&gt;is_nps_switch_requested(adev)) {</div><div class='add'>+		adev-&gt;gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return gmc_v9_0_get_memory_partition(adev, NULL);</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {</div><div class='hunk'>@@ -1390,12 +1391,13 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {</div><div class='ctx'> 	.flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,</div><div class='ctx'> 	.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,</div><div class='ctx'> 	.emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,</div><div class='del'>-	.map_mtype = gmc_v9_0_map_mtype,</div><div class='ctx'> 	.get_vm_pde = gmc_v9_0_get_vm_pde,</div><div class='ctx'> 	.get_vm_pte = gmc_v9_0_get_vm_pte,</div><div class='ctx'> 	.override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,</div><div class='ctx'> 	.get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,</div><div class='del'>-	.query_mem_partition_mode = &amp;gmc_v9_0_query_memory_partition,</div><div class='add'>+	.query_mem_partition_mode = &amp;amdgpu_gmc_query_memory_partition,</div><div class='add'>+	.request_mem_partition_mode = &amp;amdgpu_gmc_request_memory_partition,</div><div class='add'>+	.need_reset_on_init = &amp;gmc_v9_0_need_reset_on_init,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1442,15 +1444,13 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;umc.channel_idx_tbl = &amp;umc_v6_7_channel_idx_tbl_second[0][0];</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 5, 0):</div><div class='ctx'> 		adev-&gt;umc.max_ras_err_cnt_per_query =</div><div class='ctx'> 			UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;</div><div class='ctx'> 		adev-&gt;umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;</div><div class='ctx'> 		adev-&gt;umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;</div><div class='ctx'> 		adev-&gt;umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;</div><div class='ctx'> 		adev-&gt;umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;</div><div class='del'>-		adev-&gt;umc.active_mask = adev-&gt;aid_mask;</div><div class='del'>-		adev-&gt;umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;</div><div class='del'>-		adev-&gt;umc.channel_idx_tbl = &amp;umc_v12_0_channel_idx_tbl[0][0][0];</div><div class='ctx'> 		if (!adev-&gt;gmc.xgmi.connected_to_cpu &amp;&amp; !adev-&gt;gmc.is_app_apu)</div><div class='ctx'> 			adev-&gt;umc.ras = &amp;umc_v12_0_ras;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1469,6 +1469,7 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;mmhub.funcs = &amp;mmhub_v1_7_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(1, 8, 0):</div><div class='add'>+	case IP_VERSION(1, 8, 1):</div><div class='ctx'> 		adev-&gt;mmhub.funcs = &amp;mmhub_v1_8_funcs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1490,6 +1491,7 @@ static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;mmhub.ras = &amp;mmhub_v1_7_ras;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(1, 8, 0):</div><div class='add'>+	case IP_VERSION(1, 8, 1):</div><div class='ctx'> 		adev-&gt;mmhub.ras = &amp;mmhub_v1_8_ras;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1500,7 +1502,7 @@ static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	if (amdgpu_is_multi_aid(adev))</div><div class='ctx'> 		adev-&gt;gfxhub.funcs = &amp;gfxhub_v1_2_funcs;</div><div class='ctx'> 	else</div><div class='ctx'> 		adev-&gt;gfxhub.funcs = &amp;gfxhub_v1_0_funcs;</div><div class='hunk'>@@ -1535,9 +1537,46 @@ static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;gmc.xgmi.ras = &amp;xgmi_ras;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_early_init(void *handle)</div><div class='add'>+static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	enum amdgpu_memory_partition mode;</div><div class='add'>+	uint32_t supp_modes;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	adev-&gt;gmc.supported_nps_modes = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev) || (adev-&gt;flags &amp; AMD_IS_APU))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mode = amdgpu_gmc_get_memory_partition(adev, &amp;supp_modes);</div><div class='add'>+</div><div class='add'>+	/* Mode detected by hardware and supported modes available */</div><div class='add'>+	if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &amp;&amp; supp_modes) {</div><div class='add'>+		while ((i = ffs(supp_modes))) {</div><div class='add'>+			if (AMDGPU_ALL_NPS_MASK &amp; BIT(i))</div><div class='add'>+				adev-&gt;gmc.supported_nps_modes |= BIT(i);</div><div class='add'>+			supp_modes &amp;= supp_modes - 1;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/*TODO: Check PSP version also which supports NPS switch. Otherwise keep</div><div class='add'>+	 * supported modes as 0.</div><div class='add'>+	 */</div><div class='add'>+		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+		case IP_VERSION(9, 4, 3):</div><div class='add'>+		case IP_VERSION(9, 4, 4):</div><div class='add'>+			adev-&gt;gmc.supported_nps_modes =</div><div class='add'>+				BIT(AMDGPU_NPS1_PARTITION_MODE) |</div><div class='add'>+				BIT(AMDGPU_NPS4_PARTITION_MODE);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined</div><div class='hunk'>@@ -1545,7 +1584,7 @@ static int gmc_v9_0_early_init(void *handle)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||</div><div class='ctx'> 	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||</div><div class='del'>-	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	    amdgpu_is_multi_aid(adev))</div><div class='ctx'> 		adev-&gt;gmc.xgmi.supported = true;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {</div><div class='hunk'>@@ -1589,9 +1628,9 @@ static int gmc_v9_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_late_init(void *handle)</div><div class='add'>+static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);</div><div class='hunk'>@@ -1632,7 +1671,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	/* add the xgmi offset of the physical node */</div><div class='ctx'> 	base += adev-&gt;gmc.xgmi.physical_node_id * adev-&gt;gmc.xgmi.node_segment_size;</div><div class='del'>-	if (adev-&gt;gmc.xgmi.connected_to_cpu) {</div><div class='add'>+	if (amdgpu_gmc_is_pdb0_enabled(adev)) {</div><div class='ctx'> 		amdgpu_gmc_sysvm_location(adev, mc);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		amdgpu_gmc_vram_location(adev, mc, base);</div><div class='hunk'>@@ -1716,6 +1755,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)</div><div class='ctx'> 		case IP_VERSION(9, 4, 1):</div><div class='ctx'> 		case IP_VERSION(9, 4, 2):</div><div class='ctx'> 		case IP_VERSION(9, 4, 3):</div><div class='add'>+		case IP_VERSION(9, 4, 4):</div><div class='add'>+		case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		default:</div><div class='ctx'> 			adev-&gt;gmc.gart_size = 512ULL &lt;&lt; 20;</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -1745,7 +1786,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.xgmi.connected_to_cpu) {</div><div class='add'>+	if (amdgpu_gmc_is_pdb0_enabled(adev)) {</div><div class='ctx'> 		adev-&gt;gmc.vmid0_page_table_depth = 1;</div><div class='ctx'> 		adev-&gt;gmc.vmid0_page_table_block_size = 12;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1758,7 +1799,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	adev-&gt;gart.table_size = adev-&gt;gart.num_gpu_pages * 8;</div><div class='del'>-	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |</div><div class='add'>+	adev-&gt;gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) |</div><div class='ctx'> 				 AMDGPU_PTE_EXECUTABLE;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;gmc.real_vram_size) {</div><div class='hunk'>@@ -1771,7 +1812,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;gmc.xgmi.connected_to_cpu)</div><div class='add'>+		if (amdgpu_gmc_is_pdb0_enabled(adev))</div><div class='ctx'> 			r = amdgpu_gmc_pdb0_alloc(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1793,175 +1834,31 @@ static void gmc_v9_0_save_registers(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	enum amdgpu_memory_partition mode;</div><div class='del'>-	u32 supp_modes;</div><div class='del'>-	bool valid;</div><div class='del'>-</div><div class='del'>-	mode = gmc_v9_0_get_memory_partition(adev, &amp;supp_modes);</div><div class='del'>-</div><div class='del'>-	/* Mode detected by hardware not present in supported modes */</div><div class='del'>-	if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &amp;&amp;</div><div class='del'>-	    !(BIT(mode - 1) &amp; supp_modes))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	switch (mode) {</div><div class='del'>-	case UNKNOWN_MEMORY_PARTITION_MODE:</div><div class='del'>-	case AMDGPU_NPS1_PARTITION_MODE:</div><div class='del'>-		valid = (adev-&gt;gmc.num_mem_partitions == 1);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_NPS2_PARTITION_MODE:</div><div class='del'>-		valid = (adev-&gt;gmc.num_mem_partitions == 2);</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_NPS4_PARTITION_MODE:</div><div class='del'>-		valid = (adev-&gt;gmc.num_mem_partitions == 3 ||</div><div class='del'>-			 adev-&gt;gmc.num_mem_partitions == 4);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		valid = false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return valid;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	/* Check if node with id 'nid' is present in 'node_ids' array */</div><div class='del'>-	for (i = 0; i &lt; num_ids; ++i)</div><div class='del'>-		if (node_ids[i] == nid)</div><div class='del'>-			return true;</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,</div><div class='del'>-			      struct amdgpu_mem_partition_info *mem_ranges)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_numa_info numa_info;</div><div class='del'>-	int node_ids[MAX_MEM_RANGES];</div><div class='del'>-	int num_ranges = 0, ret;</div><div class='del'>-	int num_xcc, xcc_id;</div><div class='del'>-	uint32_t xcc_mask;</div><div class='del'>-</div><div class='del'>-	num_xcc = NUM_XCC(adev-&gt;gfx.xcc_mask);</div><div class='del'>-	xcc_mask = (1U &lt;&lt; num_xcc) - 1;</div><div class='del'>-</div><div class='del'>-	for_each_inst(xcc_id, xcc_mask)	{</div><div class='del'>-		ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &amp;numa_info);</div><div class='del'>-		if (ret)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (numa_info.nid == NUMA_NO_NODE) {</div><div class='del'>-			mem_ranges[0].size = numa_info.size;</div><div class='del'>-			mem_ranges[0].numa.node = numa_info.nid;</div><div class='del'>-			num_ranges = 1;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (gmc_v9_0_is_node_present(node_ids, num_ranges,</div><div class='del'>-					     numa_info.nid))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		node_ids[num_ranges] = numa_info.nid;</div><div class='del'>-		mem_ranges[num_ranges].numa.node = numa_info.nid;</div><div class='del'>-		mem_ranges[num_ranges].size = numa_info.size;</div><div class='del'>-		++num_ranges;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	adev-&gt;gmc.num_mem_partitions = num_ranges;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,</div><div class='del'>-			    struct amdgpu_mem_partition_info *mem_ranges)</div><div class='add'>+static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	enum amdgpu_memory_partition mode;</div><div class='del'>-	u32 start_addr = 0, size;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	mode = gmc_v9_0_query_memory_partition(adev);</div><div class='del'>-</div><div class='del'>-	switch (mode) {</div><div class='del'>-	case UNKNOWN_MEMORY_PARTITION_MODE:</div><div class='del'>-	case AMDGPU_NPS1_PARTITION_MODE:</div><div class='del'>-		adev-&gt;gmc.num_mem_partitions = 1;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_NPS2_PARTITION_MODE:</div><div class='del'>-		adev-&gt;gmc.num_mem_partitions = 2;</div><div class='del'>-		break;</div><div class='del'>-	case AMDGPU_NPS4_PARTITION_MODE:</div><div class='del'>-		if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='del'>-			adev-&gt;gmc.num_mem_partitions = 3;</div><div class='del'>-		else</div><div class='del'>-			adev-&gt;gmc.num_mem_partitions = 4;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		adev-&gt;gmc.num_mem_partitions = 1;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	size = adev-&gt;gmc.real_vram_size &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='del'>-	size /= adev-&gt;gmc.num_mem_partitions;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;gmc.num_mem_partitions; ++i) {</div><div class='del'>-		mem_ranges[i].range.fpfn = start_addr;</div><div class='del'>-		mem_ranges[i].size = ((u64)size &lt;&lt; AMDGPU_GPU_PAGE_SHIFT);</div><div class='del'>-		mem_ranges[i].range.lpfn = start_addr + size - 1;</div><div class='del'>-		start_addr += size;</div><div class='del'>-	}</div><div class='add'>+	static const u32 regBIF_BIOS_SCRATCH_4 = 0x50;</div><div class='add'>+	u32 vram_info;</div><div class='ctx'> </div><div class='del'>-	/* Adjust the last one */</div><div class='del'>-	mem_ranges[adev-&gt;gmc.num_mem_partitions - 1].range.lpfn =</div><div class='del'>-		(adev-&gt;gmc.real_vram_size &gt;&gt; AMDGPU_GPU_PAGE_SHIFT) - 1;</div><div class='del'>-	mem_ranges[adev-&gt;gmc.num_mem_partitions - 1].size =</div><div class='del'>-		adev-&gt;gmc.real_vram_size -</div><div class='del'>-		((u64)mem_ranges[adev-&gt;gmc.num_mem_partitions - 1].range.fpfn</div><div class='del'>-		 &lt;&lt; AMDGPU_GPU_PAGE_SHIFT);</div><div class='del'>-}</div><div class='add'>+	adev-&gt;gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;</div><div class='add'>+	adev-&gt;gmc.vram_width = 128 * 64;</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	bool valid;</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))</div><div class='add'>+		adev-&gt;gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;gmc.mem_partitions = kcalloc(MAX_MEM_RANGES,</div><div class='del'>-					   sizeof(struct amdgpu_mem_partition_info),</div><div class='del'>-					   GFP_KERNEL);</div><div class='del'>-	if (!adev-&gt;gmc.mem_partitions)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) &amp;&amp;</div><div class='add'>+		adev-&gt;rev_id == 0x3)</div><div class='add'>+		adev-&gt;gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;</div><div class='ctx'> </div><div class='del'>-	/* TODO : Get the range from PSP/Discovery for dGPU */</div><div class='del'>-	if (adev-&gt;gmc.is_app_apu)</div><div class='del'>-		gmc_v9_0_init_acpi_mem_ranges(adev, adev-&gt;gmc.mem_partitions);</div><div class='del'>-	else</div><div class='del'>-		gmc_v9_0_init_sw_mem_ranges(adev, adev-&gt;gmc.mem_partitions);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		valid = true;</div><div class='del'>-	else</div><div class='del'>-		valid = gmc_v9_0_validate_partition_info(adev);</div><div class='del'>-	if (!valid) {</div><div class='del'>-		/* TODO: handle invalid case */</div><div class='del'>-		dev_WARN(adev-&gt;dev,</div><div class='del'>-			 "Mem ranges not matching with hardware config");</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; !amdgpu_sriov_vf(adev)) {</div><div class='add'>+		vram_info = RREG32(regBIF_BIOS_SCRATCH_4);</div><div class='add'>+		adev-&gt;gmc.vram_vendor = vram_info &amp; 0xF;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	adev-&gt;gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;</div><div class='del'>-	adev-&gt;gmc.vram_width = 128 * 64;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int gmc_v9_0_sw_init(void *handle)</div><div class='add'>+static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	unsigned long inst_mask = adev-&gt;aid_mask;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;gfxhub.funcs-&gt;init(adev);</div><div class='hunk'>@@ -1970,7 +1867,7 @@ static int gmc_v9_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;adev-&gt;gmc.invalidate_lock);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {</div><div class='add'>+	if (amdgpu_is_multi_aid(adev)) {</div><div class='ctx'> 		gmc_v9_4_3_init_vram_info(adev);</div><div class='ctx'> 	} else if (!adev-&gt;bios) {</div><div class='ctx'> 		if (adev-&gt;flags &amp; AMD_IS_APU) {</div><div class='hunk'>@@ -2053,6 +1950,8 @@ static int gmc_v9_0_sw_init(void *handle)</div><div class='ctx'> 		adev-&gt;gmc.translate_further = adev-&gt;vm_manager.num_level &gt; 1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		bitmap_set(adev-&gt;vmhubs_mask, AMDGPU_GFXHUB(0),</div><div class='ctx'> 				  NUM_XCC(adev-&gt;gfx.xcc_mask));</div><div class='ctx'> </div><div class='hunk'>@@ -2118,8 +2017,8 @@ static int gmc_v9_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gmc_get_vbios_allocations(adev);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {</div><div class='del'>-		r = gmc_v9_0_init_mem_ranges(adev);</div><div class='add'>+	if (amdgpu_is_multi_aid(adev)) {</div><div class='add'>+		r = amdgpu_gmc_init_mem_ranges(adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2133,6 +2032,7 @@ static int gmc_v9_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	gmc_v9_0_init_nps_details(adev);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * number of VMs</div><div class='ctx'> 	 * VMID 0 is reserved for System</div><div class='hunk'>@@ -2146,7 +2046,7 @@ static int gmc_v9_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;vm_manager.first_kfd_vmid =</div><div class='ctx'> 		(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||</div><div class='ctx'> 		 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||</div><div class='del'>-		 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ?</div><div class='add'>+		 amdgpu_is_multi_aid(adev)) ?</div><div class='ctx'> 			3 :</div><div class='ctx'> 			8;</div><div class='ctx'> </div><div class='hunk'>@@ -2158,17 +2058,17 @@ static int gmc_v9_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	if (amdgpu_is_multi_aid(adev))</div><div class='ctx'> 		amdgpu_gmc_sysfs_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_sw_fini(void *handle)</div><div class='add'>+static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))</div><div class='add'>+	if (amdgpu_is_multi_aid(adev))</div><div class='ctx'> 		amdgpu_gmc_sysfs_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_gmc_ras_fini(adev);</div><div class='hunk'>@@ -2242,7 +2142,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.xgmi.connected_to_cpu)</div><div class='add'>+	if (amdgpu_gmc_is_pdb0_enabled(adev))</div><div class='ctx'> 		amdgpu_gmc_init_pdb0(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;gart.bo == NULL) {</div><div class='hunk'>@@ -2273,9 +2173,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_hw_init(void *handle)</div><div class='add'>+static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool value;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='hunk'>@@ -2289,13 +2189,6 @@ static int gmc_v9_0_hw_init(void *handle)</div><div class='ctx'> 	adev-&gt;gmc.flush_tlb_needs_extra_type_2 =</div><div class='ctx'> 		amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &amp;&amp;</div><div class='ctx'> 		adev-&gt;gmc.xgmi.num_physical_nodes;</div><div class='del'>-	/*</div><div class='del'>-	 * TODO: This workaround is badly documented and had a buggy</div><div class='del'>-	 * implementation. We should probably verify what we do here.</div><div class='del'>-	 */</div><div class='del'>-	adev-&gt;gmc.flush_tlb_needs_extra_type_0 =</div><div class='del'>-		amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='del'>-		adev-&gt;rev_id == 0;</div><div class='ctx'> </div><div class='ctx'> 	/* The sequence of these two function calls matters.*/</div><div class='ctx'> 	gmc_v9_0_init_golden_registers(adev);</div><div class='hunk'>@@ -2313,7 +2206,7 @@ static int gmc_v9_0_hw_init(void *handle)</div><div class='ctx'> 	adev-&gt;hdp.funcs-&gt;init_registers(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* After HDP is initialized, flush HDP.*/</div><div class='del'>-	adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+	amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)</div><div class='ctx'> 		value = false;</div><div class='hunk'>@@ -2358,9 +2251,9 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;gart_disable(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_hw_fini(void *handle)</div><div class='add'>+static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	gmc_v9_0_gart_disable(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2378,58 +2271,70 @@ static int gmc_v9_0_hw_fini(void *handle)</div><div class='ctx'> 	if (adev-&gt;mmhub.funcs-&gt;update_power_gating)</div><div class='ctx'> 		adev-&gt;mmhub.funcs-&gt;update_power_gating(adev, false);</div><div class='ctx'> </div><div class='del'>-	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='add'>+	/*</div><div class='add'>+	 * For minimal init, late_init is not called, hence VM fault/RAS irqs</div><div class='add'>+	 * are not enabled.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;init_lvl-&gt;level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.ecc_irq.funcs &amp;&amp;</div><div class='del'>-		amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='del'>-		amdgpu_irq_put(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='add'>+		if (adev-&gt;gmc.ecc_irq.funcs &amp;&amp;</div><div class='add'>+		    amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='add'>+			amdgpu_irq_put(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_suspend(void *handle)</div><div class='add'>+static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return gmc_v9_0_hw_fini(adev);</div><div class='add'>+	return gmc_v9_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_resume(void *handle)</div><div class='add'>+static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = gmc_v9_0_hw_init(adev);</div><div class='add'>+	/* If a reset is done for NPS mode switch, read the memory range</div><div class='add'>+	 * information again.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;gmc.reset_flags &amp; AMDGPU_GMC_INIT_RESET_NPS) {</div><div class='add'>+		amdgpu_gmc_init_sw_mem_ranges(adev, adev-&gt;gmc.mem_partitions);</div><div class='add'>+		adev-&gt;gmc.reset_flags &amp;= ~AMDGPU_GMC_INIT_RESET_NPS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = gmc_v9_0_hw_init(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vmid_reset_all(adev);</div><div class='add'>+	amdgpu_vmid_reset_all(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool gmc_v9_0_is_idle(void *handle)</div><div class='add'>+static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* MC is always ready in GMC v9.*/</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_wait_for_idle(void *handle)</div><div class='add'>+static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* There is no need to wait for MC idle in GMC v9.*/</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_soft_reset(void *handle)</div><div class='add'>+static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* XXX for emulation.*/</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_set_clockgating_state(void *handle,</div><div class='add'>+static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;set_clockgating(adev, state);</div><div class='ctx'> </div><div class='hunk'>@@ -2438,16 +2343,16 @@ static int gmc_v9_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mmhub.funcs-&gt;get_clockgating(adev, flags);</div><div class='ctx'> </div><div class='ctx'> 	athub_v1_0_get_clockgating(adev, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gmc_v9_0_set_powergating_state(void *handle,</div><div class='add'>+static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br/>index 4db6bb73ead4..e6c0d86d3486 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "hdp_v4_0.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> </div><div class='hunk'>@@ -37,27 +36,21 @@</div><div class='ctx'> #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK     0x00020000L</div><div class='ctx'> #define mmHDP_MEM_POWER_CTRL_BASE_IDX   0</div><div class='ctx'> </div><div class='del'>-static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	if (!ring || !ring-&gt;funcs-&gt;emit_wreg)</div><div class='del'>-		WREG32_NO_KIQ((adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_ring_emit_wreg(ring, (adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,</div><div class='ctx'> 				    struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) ||</div><div class='del'>-	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2))</div><div class='add'>+	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||</div><div class='add'>+	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (!ring || !ring-&gt;funcs-&gt;emit_wreg)</div><div class='add'>+	if (!ring || !ring-&gt;funcs-&gt;emit_wreg) {</div><div class='ctx'> 		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);</div><div class='del'>-	else</div><div class='add'>+		RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);</div><div class='add'>+	} else {</div><div class='ctx'> 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(</div><div class='ctx'> 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,</div><div class='hunk'>@@ -129,7 +122,8 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) ||</div><div class='add'>+	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5)) {</div><div class='ctx'> 		/* Default enabled */</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_HDP_MGCG;</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -175,7 +169,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {</div><div class='del'>-	.flush_hdp = hdp_v4_0_flush_hdp,</div><div class='add'>+	.flush_hdp = amdgpu_hdp_generic_flush,</div><div class='ctx'> 	.invalidate_hdp = hdp_v4_0_invalidate_hdp,</div><div class='ctx'> 	.update_clock_gating = hdp_v4_0_update_clock_gating,</div><div class='ctx'> 	.get_clock_gating_state = hdp_v4_0_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c<br/>index a9ea23fa0def..8bc001dc9f63 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c</a></div><div class='hunk'>@@ -21,27 +21,18 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "hdp_v5_0.h"</div><div class='ctx'> </div><div class='ctx'> #include "hdp/hdp_5_0_0_offset.h"</div><div class='ctx'> #include "hdp/hdp_5_0_0_sh_mask.h"</div><div class='ctx'> #include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='ctx'> </div><div class='del'>-static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	if (!ring || !ring-&gt;funcs-&gt;emit_wreg)</div><div class='del'>-		WREG32_NO_KIQ((adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_ring_emit_wreg(ring, (adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,</div><div class='ctx'> 				    struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	if (!ring || !ring-&gt;funcs-&gt;emit_wreg) {</div><div class='ctx'> 		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);</div><div class='add'>+		RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(</div><div class='ctx'> 					HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);</div><div class='hunk'>@@ -215,7 +206,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {</div><div class='del'>-	.flush_hdp = hdp_v5_0_flush_hdp,</div><div class='add'>+	.flush_hdp = amdgpu_hdp_generic_flush,</div><div class='ctx'> 	.invalidate_hdp = hdp_v5_0_invalidate_hdp,</div><div class='ctx'> 	.update_clock_gating = hdp_v5_0_update_clock_gating,</div><div class='ctx'> 	.get_clock_gating_state = hdp_v5_0_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c<br/>index 29c3484ae1f1..40940b4ab400 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "hdp_v5_2.h"</div><div class='ctx'> </div><div class='ctx'> #include "hdp/hdp_5_2_1_offset.h"</div><div class='hunk'>@@ -31,13 +30,25 @@</div><div class='ctx'> static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,</div><div class='ctx'> 				struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='del'>-	if (!ring || !ring-&gt;funcs-&gt;emit_wreg)</div><div class='add'>+	if (!ring || !ring-&gt;funcs-&gt;emit_wreg) {</div><div class='ctx'> 		WREG32_NO_KIQ((adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2,</div><div class='ctx'> 			0);</div><div class='del'>-	else</div><div class='add'>+		if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+			/* this is fine because SR_IOV doesn't remap the register */</div><div class='add'>+			RREG32_NO_KIQ((adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2);</div><div class='add'>+		} else {</div><div class='add'>+			/* We just need to read back a register to post the write.</div><div class='add'>+			 * Reading back the remapped register causes problems on</div><div class='add'>+			 * some platforms so just read back the memory size register.</div><div class='add'>+			 */</div><div class='add'>+			if (adev-&gt;nbio.funcs-&gt;get_memsize)</div><div class='add'>+				adev-&gt;nbio.funcs-&gt;get_memsize(adev);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='ctx'> 		amdgpu_ring_emit_wreg(ring,</div><div class='ctx'> 			(adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2,</div><div class='ctx'> 			0);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c<br/>index ab06c2b4b20b..ec20daf4272c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "hdp_v6_0.h"</div><div class='ctx'> </div><div class='ctx'> #include "hdp/hdp_6_0_0_offset.h"</div><div class='hunk'>@@ -31,15 +30,6 @@</div><div class='ctx'> #define regHDP_CLK_CNTL_V6_1	0xd5</div><div class='ctx'> #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0</div><div class='ctx'> </div><div class='del'>-static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	if (!ring || !ring-&gt;funcs-&gt;emit_wreg)</div><div class='del'>-		WREG32_NO_KIQ((adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_ring_emit_wreg(ring, (adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 					 bool enable)</div><div class='ctx'> {</div><div class='hunk'>@@ -148,7 +138,7 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {</div><div class='del'>-	.flush_hdp = hdp_v6_0_flush_hdp,</div><div class='add'>+	.flush_hdp = amdgpu_hdp_generic_flush,</div><div class='ctx'> 	.update_clock_gating = hdp_v6_0_update_clock_gating,</div><div class='ctx'> 	.get_clock_gating_state = hdp_v6_0_get_clockgating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c<br/>index 8d7d0813e331..ed1debc03507 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c</a></div><div class='hunk'>@@ -21,22 +21,12 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "hdp_v7_0.h"</div><div class='ctx'> </div><div class='ctx'> #include "hdp/hdp_7_0_0_offset.h"</div><div class='ctx'> #include "hdp/hdp_7_0_0_sh_mask.h"</div><div class='ctx'> #include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='ctx'> </div><div class='del'>-static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,</div><div class='del'>-				struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	if (!ring || !ring-&gt;funcs-&gt;emit_wreg)</div><div class='del'>-		WREG32_NO_KIQ((adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_ring_emit_wreg(ring, (adev-&gt;rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) &gt;&gt; 2, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,</div><div class='ctx'> 					 bool enable)</div><div class='ctx'> {</div><div class='hunk'>@@ -136,7 +126,7 @@ static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {</div><div class='del'>-	.flush_hdp = hdp_v7_0_flush_hdp,</div><div class='add'>+	.flush_hdp = amdgpu_hdp_generic_flush,</div><div class='ctx'> 	.update_clock_gating = hdp_v7_0_update_clock_gating,</div><div class='ctx'> 	.get_clock_gating_state = hdp_v7_0_get_clockgating_state,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c<br/>index 2c02ae69883d..01cadf898c00 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/iceland_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/iceland_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/iceland_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/iceland_ih.c</a></div><div class='hunk'>@@ -157,6 +157,9 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* enable interrupts */</div><div class='ctx'> 	iceland_ih_enable_interrupts(adev);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;irq.ih_soft.ring_size)</div><div class='add'>+		adev-&gt;irq.ih_soft.enabled = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -194,6 +197,9 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	wptr = le32_to_cpu(*ih-&gt;wptr_cpu);</div><div class='ctx'> </div><div class='add'>+	if (ih == &amp;adev-&gt;irq.ih_soft)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -273,9 +279,9 @@ static void iceland_ih_set_rptr(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32(mmIH_RB_RPTR, ih-&gt;rptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_early_init(void *handle)</div><div class='add'>+static int iceland_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_irq_add_domain(adev);</div><div class='hunk'>@@ -287,23 +293,27 @@ static int iceland_ih_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_sw_init(void *handle)</div><div class='add'>+static int iceland_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 64 * 1024, false);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih_soft, IH_SW_RING_SIZE, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_irq_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_sw_fini(void *handle)</div><div class='add'>+static int iceland_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> 	amdgpu_irq_remove_domain(adev);</div><div class='hunk'>@@ -311,39 +321,33 @@ static int iceland_ih_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_hw_init(void *handle)</div><div class='add'>+static int iceland_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return iceland_ih_irq_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_hw_fini(void *handle)</div><div class='add'>+static int iceland_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	iceland_ih_irq_disable(adev);</div><div class='add'>+	iceland_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_suspend(void *handle)</div><div class='add'>+static int iceland_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return iceland_ih_hw_fini(adev);</div><div class='add'>+	return iceland_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_resume(void *handle)</div><div class='add'>+static int iceland_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return iceland_ih_hw_init(adev);</div><div class='add'>+	return iceland_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool iceland_ih_is_idle(void *handle)</div><div class='add'>+static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))</div><div class='hunk'>@@ -352,11 +356,11 @@ static bool iceland_ih_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_wait_for_idle(void *handle)</div><div class='add'>+static int iceland_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -368,10 +372,10 @@ static int iceland_ih_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_soft_reset(void *handle)</div><div class='add'>+static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS__IH_BUSY_MASK)</div><div class='hunk'>@@ -398,13 +402,13 @@ static int iceland_ih_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int iceland_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int iceland_ih_set_powergating_state(void *handle,</div><div class='add'>+static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -413,7 +417,6 @@ static int iceland_ih_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs iceland_ih_ip_funcs = {</div><div class='ctx'> 	.name = "iceland_ih",</div><div class='ctx'> 	.early_init = iceland_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = iceland_ih_sw_init,</div><div class='ctx'> 	.sw_fini = iceland_ih_sw_fini,</div><div class='ctx'> 	.hw_init = iceland_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c<br/>index ad4ad39f128f..333e9c30c091 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ih_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/ih_v6_0.c</a></div><div class='hunk'>@@ -135,6 +135,34 @@ static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32(ih_regs-&gt;ih_rb_cntl);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		/* Unset the CLEAR_OVERFLOW bit to make sure the next step</div><div class='add'>+		 * is switching the bit from 0 to 1</div><div class='add'>+		 */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; amdgpu_sriov_reg_indirect_ih(adev)) {</div><div class='add'>+			if (psp_reg_program(&amp;adev-&gt;psp, ih_regs-&gt;psp_reg_id, tmp))</div><div class='add'>+				return -ETIMEDOUT;</div><div class='add'>+		} else {</div><div class='add'>+			WREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl, tmp);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Clear RB_OVERFLOW bit */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; amdgpu_sriov_reg_indirect_ih(adev)) {</div><div class='add'>+			if (psp_reg_program(&amp;adev-&gt;psp, ih_regs-&gt;psp_reg_id, tmp))</div><div class='add'>+				return -ETIMEDOUT;</div><div class='add'>+		} else {</div><div class='add'>+			WREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl, tmp);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows</div><div class='add'>+		 * can be detected.</div><div class='add'>+		 */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* enable_intr field is only valid in ring0 */</div><div class='ctx'> 	if (ih == &amp;adev-&gt;irq.ih)</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));</div><div class='hunk'>@@ -321,6 +349,7 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		}</div><div class='add'>+		ih[i]-&gt;overflow = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* update doorbell range for ih ring 0 */</div><div class='hunk'>@@ -346,6 +375,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 			    DELAY, 3);</div><div class='ctx'> 	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);</div><div class='ctx'> </div><div class='add'>+	/* Redirect the interrupts to IH RB1 for dGPU */</div><div class='add'>+	if (adev-&gt;irq.ih1.ring_size) {</div><div class='add'>+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);</div><div class='add'>+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,</div><div class='add'>+				    SOURCE_ID_MATCH_ENABLE, 0x1);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pci_set_master(adev-&gt;pdev);</div><div class='ctx'> </div><div class='ctx'> 	/* enable interrupts */</div><div class='hunk'>@@ -403,7 +447,10 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> 	wptr = RREG32_NO_KIQ(ih_regs-&gt;ih_rb_wptr);</div><div class='ctx'> 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))</div><div class='ctx'> 		goto out;</div><div class='del'>-	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);</div><div class='add'>+	else</div><div class='add'>+		ih-&gt;overflow = true;</div><div class='ctx'> </div><div class='ctx'> 	/* When a ring buffer overflow happen start parsing interrupt</div><div class='ctx'> 	 * from the last not overwritten vector (wptr + 32). Hopefully</div><div class='hunk'>@@ -516,19 +563,19 @@ static void ih_v6_0_set_self_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.self_irq.funcs = &amp;ih_v6_0_self_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_early_init(void *handle)</div><div class='add'>+static int ih_v6_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	ih_v6_0_set_interrupt_funcs(adev);</div><div class='ctx'> 	ih_v6_0_set_self_irq_funcs(adev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_sw_init(void *handle)</div><div class='add'>+static int ih_v6_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool use_bus_addr;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,</div><div class='hunk'>@@ -540,8 +587,7 @@ static int ih_v6_0_sw_init(void *handle)</div><div class='ctx'> 	/* use gpu virtual address for ih ring</div><div class='ctx'> 	 * until ih_checken is programmed to allow</div><div class='ctx'> 	 * use bus address for ih ring by psp bl */</div><div class='del'>-	use_bus_addr =</div><div class='del'>-		(adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;</div><div class='add'>+	use_bus_addr = adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP;</div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, IH_RING_SIZE, use_bus_addr);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -549,8 +595,15 @@ static int ih_v6_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;irq.ih.use_doorbell = true;</div><div class='ctx'> 	adev-&gt;irq.ih.doorbell_index = adev-&gt;doorbell_index.ih &lt;&lt; 1;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;irq.ih1.ring_size = 0;</div><div class='del'>-	adev-&gt;irq.ih2.ring_size = 0;</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='add'>+		r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih1, IH_RING_SIZE,</div><div class='add'>+					use_bus_addr);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		adev-&gt;irq.ih1.use_doorbell = true;</div><div class='add'>+		adev-&gt;irq.ih1.doorbell_index = (adev-&gt;doorbell_index.ih + 1) &lt;&lt; 1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* initialize ih control register offset */</div><div class='ctx'> 	ih_v6_0_init_register_offset(adev);</div><div class='hunk'>@@ -564,19 +617,19 @@ static int ih_v6_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_sw_fini(void *handle)</div><div class='add'>+static int ih_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_hw_init(void *handle)</div><div class='add'>+static int ih_v6_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = ih_v6_0_irq_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -585,42 +638,36 @@ static int ih_v6_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_hw_fini(void *handle)</div><div class='add'>+static int ih_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	ih_v6_0_irq_disable(adev);</div><div class='add'>+	ih_v6_0_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_suspend(void *handle)</div><div class='add'>+static int ih_v6_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return ih_v6_0_hw_fini(adev);</div><div class='add'>+	return ih_v6_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_resume(void *handle)</div><div class='add'>+static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return ih_v6_0_hw_init(adev);</div><div class='add'>+	return ih_v6_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool ih_v6_0_is_idle(void *handle)</div><div class='add'>+static bool ih_v6_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_wait_for_idle(void *handle)</div><div class='add'>+static int ih_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_soft_reset(void *handle)</div><div class='add'>+static int ih_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -649,10 +696,10 @@ static void ih_v6_0_update_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int ih_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	ih_v6_0_update_clockgating_state(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='hunk'>@@ -712,10 +759,10 @@ static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_0_set_powergating_state(void *handle,</div><div class='add'>+static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_IH_SRAM_PG)</div><div class='hunk'>@@ -724,9 +771,9 @@ static int ih_v6_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ih_v6_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void ih_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_IH_CG;</div><div class='hunk'>@@ -735,7 +782,6 @@ static void ih_v6_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> static const struct amd_ip_funcs ih_v6_0_ip_funcs = {</div><div class='ctx'> 	.name = "ih_v6_0",</div><div class='ctx'> 	.early_init = ih_v6_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = ih_v6_0_sw_init,</div><div class='ctx'> 	.sw_fini = ih_v6_0_sw_fini,</div><div class='ctx'> 	.hw_init = ih_v6_0_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c<br/>index b8da0fc29378..95b3f4e55ec3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ih_v6_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/ih_v6_1.c</a></div><div class='hunk'>@@ -346,6 +346,21 @@ static int ih_v6_1_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 			    DELAY, 3);</div><div class='ctx'> 	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);</div><div class='ctx'> </div><div class='add'>+	/* Redirect the interrupts to IH RB1 for dGPU */</div><div class='add'>+	if (adev-&gt;irq.ih1.ring_size) {</div><div class='add'>+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);</div><div class='add'>+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,</div><div class='add'>+				    SOURCE_ID_MATCH_ENABLE, 0x1);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pci_set_master(adev-&gt;pdev);</div><div class='ctx'> </div><div class='ctx'> 	/* enable interrupts */</div><div class='hunk'>@@ -517,19 +532,25 @@ static void ih_v6_1_set_self_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.self_irq.funcs = &amp;ih_v6_1_self_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_early_init(void *handle)</div><div class='add'>+static int ih_v6_1_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_irq_add_domain(adev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ih_v6_1_set_interrupt_funcs(adev);</div><div class='ctx'> 	ih_v6_1_set_self_irq_funcs(adev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_sw_init(void *handle)</div><div class='add'>+static int ih_v6_1_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool use_bus_addr;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,</div><div class='hunk'>@@ -541,8 +562,7 @@ static int ih_v6_1_sw_init(void *handle)</div><div class='ctx'> 	/* use gpu virtual address for ih ring</div><div class='ctx'> 	 * until ih_checken is programmed to allow</div><div class='ctx'> 	 * use bus address for ih ring by psp bl */</div><div class='del'>-	use_bus_addr =</div><div class='del'>-		(adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;</div><div class='add'>+	use_bus_addr = adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP;</div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 256 * 1024, use_bus_addr);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -550,8 +570,15 @@ static int ih_v6_1_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;irq.ih.use_doorbell = true;</div><div class='ctx'> 	adev-&gt;irq.ih.doorbell_index = adev-&gt;doorbell_index.ih &lt;&lt; 1;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;irq.ih1.ring_size = 0;</div><div class='del'>-	adev-&gt;irq.ih2.ring_size = 0;</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='add'>+		r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih1, IH_RING_SIZE,</div><div class='add'>+					use_bus_addr);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		adev-&gt;irq.ih1.use_doorbell = true;</div><div class='add'>+		adev-&gt;irq.ih1.doorbell_index = (adev-&gt;doorbell_index.ih + 1) &lt;&lt; 1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* initialize ih control register offset */</div><div class='ctx'> 	ih_v6_1_init_register_offset(adev);</div><div class='hunk'>@@ -565,19 +592,19 @@ static int ih_v6_1_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_sw_fini(void *handle)</div><div class='add'>+static int ih_v6_1_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_hw_init(void *handle)</div><div class='add'>+static int ih_v6_1_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = ih_v6_1_irq_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -586,42 +613,36 @@ static int ih_v6_1_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_hw_fini(void *handle)</div><div class='add'>+static int ih_v6_1_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	ih_v6_1_irq_disable(adev);</div><div class='add'>+	ih_v6_1_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_suspend(void *handle)</div><div class='add'>+static int ih_v6_1_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return ih_v6_1_hw_fini(adev);</div><div class='add'>+	return ih_v6_1_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_resume(void *handle)</div><div class='add'>+static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return ih_v6_1_hw_init(adev);</div><div class='add'>+	return ih_v6_1_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool ih_v6_1_is_idle(void *handle)</div><div class='add'>+static bool ih_v6_1_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_wait_for_idle(void *handle)</div><div class='add'>+static int ih_v6_1_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_soft_reset(void *handle)</div><div class='add'>+static int ih_v6_1_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -652,10 +673,10 @@ static void ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_set_clockgating_state(void *handle,</div><div class='add'>+static int ih_v6_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	ih_v6_1_update_clockgating_state(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='hunk'>@@ -715,10 +736,10 @@ static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v6_1_set_powergating_state(void *handle,</div><div class='add'>+static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_IH_SRAM_PG)</div><div class='hunk'>@@ -727,9 +748,9 @@ static int ih_v6_1_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ih_v6_1_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void ih_v6_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_IH_CG;</div><div class='hunk'>@@ -740,7 +761,6 @@ static void ih_v6_1_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> static const struct amd_ip_funcs ih_v6_1_ip_funcs = {</div><div class='ctx'> 	.name = "ih_v6_1",</div><div class='ctx'> 	.early_init = ih_v6_1_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = ih_v6_1_sw_init,</div><div class='ctx'> 	.sw_fini = ih_v6_1_sw_fini,</div><div class='ctx'> 	.hw_init = ih_v6_1_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c<br/>index 7aed96fa10a9..b32ea4129c61 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ih_v7_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/ih_v7_0.c</a></div><div class='hunk'>@@ -346,6 +346,21 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 			    DELAY, 3);</div><div class='ctx'> 	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);</div><div class='ctx'> </div><div class='add'>+	/* Redirect the interrupts to IH RB1 for dGPU */</div><div class='add'>+	if (adev-&gt;irq.ih1.ring_size) {</div><div class='add'>+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);</div><div class='add'>+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,</div><div class='add'>+				    SOURCE_ID_MATCH_ENABLE, 0x1);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pci_set_master(adev-&gt;pdev);</div><div class='ctx'> </div><div class='ctx'> 	/* enable interrupts */</div><div class='hunk'>@@ -513,19 +528,19 @@ static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.self_irq.funcs = &amp;ih_v7_0_self_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_early_init(void *handle)</div><div class='add'>+static int ih_v7_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	ih_v7_0_set_interrupt_funcs(adev);</div><div class='ctx'> 	ih_v7_0_set_self_irq_funcs(adev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_sw_init(void *handle)</div><div class='add'>+static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool use_bus_addr;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,</div><div class='hunk'>@@ -537,8 +552,7 @@ static int ih_v7_0_sw_init(void *handle)</div><div class='ctx'> 	/* use gpu virtual address for ih ring</div><div class='ctx'> 	 * until ih_checken is programmed to allow</div><div class='ctx'> 	 * use bus address for ih ring by psp bl */</div><div class='del'>-	use_bus_addr =</div><div class='del'>-		(adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;</div><div class='add'>+	use_bus_addr = adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP;</div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 256 * 1024, use_bus_addr);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -546,8 +560,15 @@ static int ih_v7_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;irq.ih.use_doorbell = true;</div><div class='ctx'> 	adev-&gt;irq.ih.doorbell_index = adev-&gt;doorbell_index.ih &lt;&lt; 1;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;irq.ih1.ring_size = 0;</div><div class='del'>-	adev-&gt;irq.ih2.ring_size = 0;</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='add'>+		r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih1, IH_RING_SIZE,</div><div class='add'>+					use_bus_addr);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		adev-&gt;irq.ih1.use_doorbell = true;</div><div class='add'>+		adev-&gt;irq.ih1.doorbell_index = (adev-&gt;doorbell_index.ih + 1) &lt;&lt; 1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* initialize ih control register offset */</div><div class='ctx'> 	ih_v7_0_init_register_offset(adev);</div><div class='hunk'>@@ -561,19 +582,19 @@ static int ih_v7_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_sw_fini(void *handle)</div><div class='add'>+static int ih_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_hw_init(void *handle)</div><div class='add'>+static int ih_v7_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = ih_v7_0_irq_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -582,42 +603,36 @@ static int ih_v7_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_hw_fini(void *handle)</div><div class='add'>+static int ih_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	ih_v7_0_irq_disable(adev);</div><div class='add'>+	ih_v7_0_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_suspend(void *handle)</div><div class='add'>+static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return ih_v7_0_hw_fini(adev);</div><div class='add'>+	return ih_v7_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_resume(void *handle)</div><div class='add'>+static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return ih_v7_0_hw_init(adev);</div><div class='add'>+	return ih_v7_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool ih_v7_0_is_idle(void *handle)</div><div class='add'>+static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_wait_for_idle(void *handle)</div><div class='add'>+static int ih_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_soft_reset(void *handle)</div><div class='add'>+static int ih_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -648,10 +663,10 @@ static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_set_clockgating_state(void *handle,</div><div class='add'>+static int ih_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	ih_v7_0_update_clockgating_state(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='hunk'>@@ -711,10 +726,10 @@ static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ih_v7_0_set_powergating_state(void *handle,</div><div class='add'>+static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_IH_SRAM_PG)</div><div class='hunk'>@@ -723,9 +738,9 @@ static int ih_v7_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ih_v7_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_IH_CG;</div><div class='hunk'>@@ -736,7 +751,6 @@ static void ih_v7_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> static const struct amd_ip_funcs ih_v7_0_ip_funcs = {</div><div class='ctx'> 	.name = "ih_v7_0",</div><div class='ctx'> 	.early_init = ih_v7_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = ih_v7_0_sw_init,</div><div class='ctx'> 	.sw_fini = ih_v7_0_sw_fini,</div><div class='ctx'> 	.hw_init = ih_v7_0_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c<br/>index 3e91a8e42c21..cc626036ed9c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/imu_v11_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/imu_v11_0.c</a></div><div class='hunk'>@@ -32,16 +32,18 @@</div><div class='ctx'> #include "gc/gc_11_0_0_sh_mask.h"</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu_kicker.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_4_imu.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_0_imu.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin");</div><div class='ctx'> </div><div class='ctx'> static int imu_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	char fw_name[45];</div><div class='ctx'> 	char ucode_prefix[30];</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct imu_firmware_header_v1_0 *imu_hdr;</div><div class='hunk'>@@ -50,11 +52,15 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	DRM_DEBUG("\n");</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='del'>-</div><div class='del'>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix);</div><div class='del'>-	err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.imu_fw, fw_name);</div><div class='add'>+	if (amdgpu_is_kicker_fw(adev))</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.imu_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_imu_kicker.bin", ucode_prefix);</div><div class='add'>+	else</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.imu_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_imu.bin", ucode_prefix);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='add'>+</div><div class='ctx'> 	imu_hdr = (const struct imu_firmware_header_v1_0 *)adev-&gt;gfx.imu_fw-&gt;data;</div><div class='ctx'> 	//adev-&gt;gfx.imu_feature_version = le32_to_cpu(imu_hdr-&gt;ucode_feature_version);</div><div class='ctx'> 	</div><div class='hunk'>@@ -75,8 +81,8 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(adev-&gt;dev,</div><div class='del'>-			"gfx11: Failed to load firmware \"%s\"\n",</div><div class='del'>-			fw_name);</div><div class='add'>+			"gfx11: Failed to load firmware \"%s_imu.bin\"\n",</div><div class='add'>+			ucode_prefix);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;gfx.imu_fw);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -154,7 +160,7 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)</div><div class='ctx'> 		WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	//disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB</div><div class='add'>+	//disable imu Rtavfs, SmsRepair, DfllBTC, and ClkB</div><div class='ctx'> 	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);</div><div class='ctx'> 	imu_reg_val |= 0x10007;</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c<br/>new file mode 100644<br/>index 000000000000..58cd87db8061<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/imu_v12_0.c</a></div><div class='hunk'>@@ -0,0 +1,406 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_imu.h"</div><div class='add'>+#include "amdgpu_dpm.h"</div><div class='add'>+</div><div class='add'>+#include "imu_v12_0.h"</div><div class='add'>+</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "mmhub/mmhub_4_1_0_offset.h"</div><div class='add'>+</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu_kicker.bin");</div><div class='add'>+</div><div class='add'>+#define TRANSFER_RAM_MASK	0x001c0000</div><div class='add'>+</div><div class='add'>+static int imu_v12_0_init_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	char ucode_prefix[30];</div><div class='add'>+	int err;</div><div class='add'>+	const struct imu_firmware_header_v1_0 *imu_hdr;</div><div class='add'>+	struct amdgpu_firmware_info *info = NULL;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG("\n");</div><div class='add'>+</div><div class='add'>+	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));</div><div class='add'>+	if (amdgpu_is_kicker_fw(adev))</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.imu_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_imu_kicker.bin", ucode_prefix);</div><div class='add'>+	else</div><div class='add'>+		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.imu_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+					   "amdgpu/%s_imu.bin", ucode_prefix);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	imu_hdr = (const struct imu_firmware_header_v1_0 *)adev-&gt;gfx.imu_fw-&gt;data;</div><div class='add'>+	adev-&gt;gfx.imu_fw_version = le32_to_cpu(imu_hdr-&gt;header.ucode_version);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+		info = &amp;adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_IMU_I];</div><div class='add'>+		info-&gt;ucode_id = AMDGPU_UCODE_ID_IMU_I;</div><div class='add'>+		info-&gt;fw = adev-&gt;gfx.imu_fw;</div><div class='add'>+		adev-&gt;firmware.fw_size +=</div><div class='add'>+			ALIGN(le32_to_cpu(imu_hdr-&gt;imu_iram_ucode_size_bytes), PAGE_SIZE);</div><div class='add'>+		info = &amp;adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_IMU_D];</div><div class='add'>+		info-&gt;ucode_id = AMDGPU_UCODE_ID_IMU_D;</div><div class='add'>+		info-&gt;fw = adev-&gt;gfx.imu_fw;</div><div class='add'>+		adev-&gt;firmware.fw_size +=</div><div class='add'>+			ALIGN(le32_to_cpu(imu_hdr-&gt;imu_dram_ucode_size_bytes), PAGE_SIZE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(adev-&gt;dev,</div><div class='add'>+			"gfx12: Failed to load firmware \"%s_imu.bin\"\n",</div><div class='add'>+			ucode_prefix);</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;gfx.imu_fw);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int imu_v12_0_load_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct imu_firmware_header_v1_0 *hdr;</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	unsigned i, fw_size;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;gfx.imu_fw)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct imu_firmware_header_v1_0 *)adev-&gt;gfx.imu_fw-&gt;data;</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.imu_fw-&gt;data +</div><div class='add'>+			le32_to_cpu(hdr-&gt;header.ucode_array_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(hdr-&gt;imu_iram_ucode_size_bytes) / 4;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; fw_size; i++)</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev-&gt;gfx.imu_fw_version);</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;gfx.imu_fw-&gt;data +</div><div class='add'>+			le32_to_cpu(hdr-&gt;header.ucode_array_offset_bytes) +</div><div class='add'>+			le32_to_cpu(hdr-&gt;imu_iram_ucode_size_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(hdr-&gt;imu_dram_ucode_size_bytes) / 4;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; fw_size; i++)</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev-&gt;gfx.imu_fw_version);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 imu_reg_val = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);</div><div class='add'>+		if ((imu_reg_val &amp; 0x1f) == 0x1f)</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "init imu: IMU start timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void imu_v12_0_setup(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 imu_reg_val;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.imu.mode == DEBUG_MODE) {</div><div class='add'>+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);</div><div class='add'>+		imu_reg_val |= 0x1;</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);</div><div class='add'>+</div><div class='add'>+		imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);</div><div class='add'>+		imu_reg_val |= 0x20010007;</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val);</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int imu_v12_0_start(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 imu_reg_val;</div><div class='add'>+</div><div class='add'>+	imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);</div><div class='add'>+	imu_reg_val &amp;= 0xfffffffe;</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+		amdgpu_dpm_set_gfx_power_up_by_imu(adev);</div><div class='add'>+</div><div class='add'>+	return imu_v12_0_wait_for_reset_status(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct imu_rlc_ram_golden imu_rlc_ram_golden_12_0_1[] = {</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCH_PIPE_STEER, 0x1e4, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1X_PIPE_STEER, 0x1e4, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1_PIPE_STEER, 0x1e4, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13571357, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x64206420, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x2460246, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x75317531, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xc0d41183, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_CHICKEN_BITS, 0x507d1c0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_CHICKEN_BITS, 0x507d1c0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_RB_WPTR_POLL_CNTL, 0x600100, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_CREDITS, 0x3f7fff, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_CREDITS, 0x3f7ebf, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE0, 0x2e00000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE1, 0x1a078, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE2, 0x0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE0, 0x0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE1, 0x12030, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE2, 0x0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE0, 0x19041000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE0, 0x1e080000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_PRIORITY, 0x880, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_PRIORITY, 0x8880, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ARB_FINAL, 0x17, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ARB_FINAL, 0x77, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ENABLE, 0x00000001, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ENABLE, 0x00000001, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x20000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0c, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xfffff, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_MISC, 0x0091, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_MISC, 0x0091, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x00008500, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0x00880007, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regTD_CNTL, 0x00000001, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x08200545, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBMH_CP_PERFMON_CNTL, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCB_PERFCOUNTER0_SELECT1, 0x000fffff, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_DEBUG_2, 0x00020000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_CPC_DEBUG, 0x00500010, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x0000000f, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x0000600f, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x0000ffff, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x0003d000, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x0003d7ff, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x1c0000),</div><div class='add'>+	IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0x1c0000)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void program_imu_rlc_ram_old(struct amdgpu_device *adev,</div><div class='add'>+				    const struct imu_rlc_ram_golden *regs,</div><div class='add'>+				    const u32 array_size)</div><div class='add'>+{</div><div class='add'>+	const struct imu_rlc_ram_golden *entry;</div><div class='add'>+	u32 reg, data;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; array_size; ++i) {</div><div class='add'>+		entry = &amp;regs[i];</div><div class='add'>+		reg =  adev-&gt;reg_offset[entry-&gt;hwip][entry-&gt;instance][entry-&gt;segment] + entry-&gt;reg;</div><div class='add'>+		reg |= entry-&gt;addr_mask;</div><div class='add'>+		data = entry-&gt;data;</div><div class='add'>+		if (entry-&gt;reg == regGCMC_VM_AGP_BASE)</div><div class='add'>+			data = 0x00ffffff;</div><div class='add'>+		else if (entry-&gt;reg == regGCMC_VM_AGP_TOP)</div><div class='add'>+			data = 0x0;</div><div class='add'>+		else if (entry-&gt;reg == regGCMC_VM_FB_LOCATION_BASE)</div><div class='add'>+			data = adev-&gt;gmc.vram_start &gt;&gt; 24;</div><div class='add'>+		else if (entry-&gt;reg == regGCMC_VM_FB_LOCATION_TOP)</div><div class='add'>+			data = adev-&gt;gmc.vram_end &gt;&gt; 24;</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);</div><div class='add'>+		WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 imu_v12_0_grbm_gfx_index_remap(struct amdgpu_device *adev,</div><div class='add'>+					  u32 data, bool high)</div><div class='add'>+{</div><div class='add'>+	u32 val, inst_index;</div><div class='add'>+</div><div class='add'>+	inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX);</div><div class='add'>+</div><div class='add'>+	if (high)</div><div class='add'>+		val = inst_index &gt;&gt; 5;</div><div class='add'>+	else</div><div class='add'>+		val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) &lt;&lt; 18 |</div><div class='add'>+		      REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) &lt;&lt; 19 |</div><div class='add'>+		      REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) &lt;&lt; 20 |</div><div class='add'>+		      REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) &lt;&lt; 21 |</div><div class='add'>+		      REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) &lt;&lt; 25 |</div><div class='add'>+		      (inst_index &amp; 0x1f);</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 imu_v12_init_gfxhub_settings(struct amdgpu_device *adev,</div><div class='add'>+					u32 reg, u32 data)</div><div class='add'>+{</div><div class='add'>+	if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_START);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_END);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB);</div><div class='add'>+	else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB))</div><div class='add'>+		return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB);</div><div class='add'>+	else</div><div class='add'>+		return data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void program_imu_rlc_ram(struct amdgpu_device *adev,</div><div class='add'>+				const u32 *regs,</div><div class='add'>+				const u32 array_size)</div><div class='add'>+{</div><div class='add'>+	u32 reg, data, val_h = 0, val_l = TRANSFER_RAM_MASK;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (array_size % 3)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; array_size; i += 3) {</div><div class='add'>+		reg = regs[i + 0];</div><div class='add'>+		data = regs[i + 2];</div><div class='add'>+		data = imu_v12_init_gfxhub_settings(adev, reg, data);</div><div class='add'>+		if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {</div><div class='add'>+			val_l = imu_v12_0_grbm_gfx_index_remap(adev, data, false);</div><div class='add'>+			val_h = imu_v12_0_grbm_gfx_index_remap(adev, data, true);</div><div class='add'>+		} else {</div><div class='add'>+			WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, val_h);</div><div class='add'>+			WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg | val_l);</div><div class='add'>+			WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 reg_data, size = 0;</div><div class='add'>+	const u32 *data = NULL;</div><div class='add'>+	int r = -EINVAL;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		if (!r)</div><div class='add'>+			program_imu_rlc_ram(adev, data, (const u32)size);</div><div class='add'>+		else</div><div class='add'>+			program_imu_rlc_ram_old(adev, imu_rlc_ram_golden_12_0_1,</div><div class='add'>+				(const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BUG();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//Indicate the latest entry</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);</div><div class='add'>+</div><div class='add'>+	reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);</div><div class='add'>+	reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK;</div><div class='add'>+	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs = {</div><div class='add'>+	.init_microcode = imu_v12_0_init_microcode,</div><div class='add'>+	.load_microcode = imu_v12_0_load_microcode,</div><div class='add'>+	.setup_imu = imu_v12_0_setup,</div><div class='add'>+	.start_imu = imu_v12_0_start,</div><div class='add'>+	.program_rlc_ram = imu_v12_0_program_rlc_ram,</div><div class='add'>+	.wait_for_reset_status = imu_v12_0_wait_for_reset_status,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.h b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.h<br/>index 9afd6ddb01e9..a1f50cb1aeab 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v10_1.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v10_1.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/imu_v12_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/imu_v12_0.h</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'>  * copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -21,9 +21,10 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#ifndef __MES_V10_1_H__</div><div class='del'>-#define __MES_V10_1_H__</div><div class='add'>+#ifndef __IMU_V12_0_H__</div><div class='add'>+#define __IMU_V12_0_H__</div><div class='ctx'> </div><div class='del'>-extern const struct amdgpu_ip_block_version mes_v10_1_ip_block;</div><div class='add'>+extern const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs;</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c<br/>new file mode 100644<br/>index 000000000000..0027a639c7e6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "isp_v4_1_0.h"</div><div class='add'>+</div><div class='add'>+static const unsigned int isp_4_1_0_int_srcid[MAX_ISP410_INT_SRC] = {</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int isp_v4_1_0_hw_init(struct amdgpu_isp *isp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+	int idx, int_idx, num_res, r;</div><div class='add'>+	u64 isp_base;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;rmmio_size == 0 || adev-&gt;rmmio_size &lt; 0x5289)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	isp_base = adev-&gt;rmmio_base;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell = kcalloc(3, sizeof(struct mfd_cell), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_cell) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"%s: isp mfd cell alloc failed\n", __func__);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_res = MAX_ISP410_MEM_RES + MAX_ISP410_INT_SRC;</div><div class='add'>+	isp-&gt;isp_res = kcalloc(num_res, sizeof(struct resource),</div><div class='add'>+			       GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_res) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"%s: isp mfd res alloc failed\n", __func__);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_pdata = kzalloc(sizeof(*isp-&gt;isp_pdata), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_pdata) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"%s: isp platform data alloc failed\n", __func__);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* initialize isp platform data */</div><div class='add'>+	isp-&gt;isp_pdata-&gt;adev = (void *)adev;</div><div class='add'>+	isp-&gt;isp_pdata-&gt;asic_type = adev-&gt;asic_type;</div><div class='add'>+	isp-&gt;isp_pdata-&gt;base_rmmio_size = adev-&gt;rmmio_size;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_res[0].name = "isp_4_1_0_reg";</div><div class='add'>+	isp-&gt;isp_res[0].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_res[0].start = isp_base;</div><div class='add'>+	isp-&gt;isp_res[0].end = isp_base + ISP_REGS_OFFSET_END;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_res[1].name = "isp_4_1_phy0_reg";</div><div class='add'>+	isp-&gt;isp_res[1].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_res[1].start = isp_base + ISP410_PHY0_OFFSET;</div><div class='add'>+	isp-&gt;isp_res[1].end = isp_base + ISP410_PHY0_OFFSET + ISP410_PHY0_SIZE;</div><div class='add'>+</div><div class='add'>+	for (idx = MAX_ISP410_MEM_RES, int_idx = 0; idx &lt; num_res; idx++, int_idx++) {</div><div class='add'>+		isp-&gt;isp_res[idx].name = "isp_4_1_0_irq";</div><div class='add'>+		isp-&gt;isp_res[idx].flags = IORESOURCE_IRQ;</div><div class='add'>+		isp-&gt;isp_res[idx].start =</div><div class='add'>+			amdgpu_irq_create_mapping(adev, isp_4_1_0_int_srcid[int_idx]);</div><div class='add'>+		isp-&gt;isp_res[idx].end =</div><div class='add'>+			isp-&gt;isp_res[idx].start;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell[0].name = "amd_isp_capture";</div><div class='add'>+	isp-&gt;isp_cell[0].num_resources = num_res;</div><div class='add'>+	isp-&gt;isp_cell[0].resources = &amp;isp-&gt;isp_res[0];</div><div class='add'>+	isp-&gt;isp_cell[0].platform_data = isp-&gt;isp_pdata;</div><div class='add'>+	isp-&gt;isp_cell[0].pdata_size = sizeof(struct isp_platform_data);</div><div class='add'>+</div><div class='add'>+	/* initialize isp i2c platform data */</div><div class='add'>+	isp-&gt;isp_i2c_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_i2c_res) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"%s: isp mfd res alloc failed\n", __func__);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_i2c_res[0].name = "isp_i2c0_reg";</div><div class='add'>+	isp-&gt;isp_i2c_res[0].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_i2c_res[0].start = isp_base + ISP410_I2C0_OFFSET;</div><div class='add'>+	isp-&gt;isp_i2c_res[0].end = isp_base + ISP410_I2C0_OFFSET + ISP410_I2C0_SIZE;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell[1].name = "amd_isp_i2c_designware";</div><div class='add'>+	isp-&gt;isp_cell[1].num_resources = 1;</div><div class='add'>+	isp-&gt;isp_cell[1].resources = &amp;isp-&gt;isp_i2c_res[0];</div><div class='add'>+	isp-&gt;isp_cell[1].platform_data = isp-&gt;isp_pdata;</div><div class='add'>+	isp-&gt;isp_cell[1].pdata_size = sizeof(struct isp_platform_data);</div><div class='add'>+</div><div class='add'>+	/* initialize isp gpiochip platform data */</div><div class='add'>+	isp-&gt;isp_gpio_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_gpio_res) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"%s: isp gpio res alloc failed\n", __func__);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_gpio_res[0].name = "isp_gpio_reg";</div><div class='add'>+	isp-&gt;isp_gpio_res[0].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_gpio_res[0].start = isp_base + ISP410_GPIO_SENSOR_OFFSET;</div><div class='add'>+	isp-&gt;isp_gpio_res[0].end = isp_base + ISP410_GPIO_SENSOR_OFFSET +</div><div class='add'>+				   ISP410_GPIO_SENSOR_SIZE;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell[2].name = "amdisp-pinctrl";</div><div class='add'>+	isp-&gt;isp_cell[2].num_resources = 1;</div><div class='add'>+	isp-&gt;isp_cell[2].resources = &amp;isp-&gt;isp_gpio_res[0];</div><div class='add'>+	isp-&gt;isp_cell[2].platform_data = isp-&gt;isp_pdata;</div><div class='add'>+	isp-&gt;isp_cell[2].pdata_size = sizeof(struct isp_platform_data);</div><div class='add'>+</div><div class='add'>+	r = mfd_add_hotplug_devices(isp-&gt;parent, isp-&gt;isp_cell, 3);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev,</div><div class='add'>+			"%s: add mfd hotplug device failed\n", __func__);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+failure:</div><div class='add'>+</div><div class='add'>+	kfree(isp-&gt;isp_pdata);</div><div class='add'>+	kfree(isp-&gt;isp_res);</div><div class='add'>+	kfree(isp-&gt;isp_cell);</div><div class='add'>+	kfree(isp-&gt;isp_i2c_res);</div><div class='add'>+	kfree(isp-&gt;isp_gpio_res);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_v4_1_0_hw_fini(struct amdgpu_isp *isp)</div><div class='add'>+{</div><div class='add'>+	mfd_remove_devices(isp-&gt;parent);</div><div class='add'>+</div><div class='add'>+	kfree(isp-&gt;isp_res);</div><div class='add'>+	kfree(isp-&gt;isp_cell);</div><div class='add'>+	kfree(isp-&gt;isp_pdata);</div><div class='add'>+	kfree(isp-&gt;isp_i2c_res);</div><div class='add'>+	kfree(isp-&gt;isp_gpio_res);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct isp_funcs isp_v4_1_0_funcs = {</div><div class='add'>+	.hw_init = isp_v4_1_0_hw_init,</div><div class='add'>+	.hw_fini = isp_v4_1_0_hw_fini,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp)</div><div class='add'>+{</div><div class='add'>+	isp-&gt;funcs = &amp;isp_v4_1_0_funcs;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h<br/>new file mode 100644<br/>index 000000000000..4d239198edd0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __ISP_V4_1_0_H__</div><div class='add'>+#define __ISP_V4_1_0_H__</div><div class='add'>+</div><div class='add'>+#include "amdgpu_isp.h"</div><div class='add'>+</div><div class='add'>+#include "ivsrcid/isp/irqsrcs_isp_4_1.h"</div><div class='add'>+</div><div class='add'>+#define MAX_ISP410_MEM_RES 2</div><div class='add'>+#define MAX_ISP410_SENSOR_RES 1</div><div class='add'>+#define MAX_ISP410_INT_SRC 8</div><div class='add'>+</div><div class='add'>+#define ISP410_PHY0_OFFSET 0x66700</div><div class='add'>+#define ISP410_PHY0_SIZE   0xD30</div><div class='add'>+</div><div class='add'>+#define ISP410_I2C0_OFFSET 0x66400</div><div class='add'>+#define ISP410_I2C0_SIZE 0x100</div><div class='add'>+</div><div class='add'>+#define ISP410_GPIO_SENSOR_OFFSET 0x6613C</div><div class='add'>+#define ISP410_GPIO_SENSOR_SIZE 0x54</div><div class='add'>+</div><div class='add'>+void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c<br/>new file mode 100644<br/>index 000000000000..4258d3e0b706<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c</a></div><div class='hunk'>@@ -0,0 +1,377 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/gpio/machine.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "isp_v4_1_1.h"</div><div class='add'>+</div><div class='add'>+MODULE_FIRMWARE("amdgpu/isp_4_1_1.bin");</div><div class='add'>+</div><div class='add'>+#define ISP_PERFORMANCE_STATE_LOW 0</div><div class='add'>+#define ISP_PERFORMANCE_STATE_HIGH 1</div><div class='add'>+</div><div class='add'>+#define ISP_HIGH_PERFORMANC_XCLK 788</div><div class='add'>+#define ISP_HIGH_PERFORMANC_ICLK 788</div><div class='add'>+</div><div class='add'>+static const unsigned int isp_4_1_1_int_srcid[MAX_ISP411_INT_SRC] = {</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15,</div><div class='add'>+	ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gpiod_lookup_table isp_gpio_table = {</div><div class='add'>+	.dev_id = "amd_isp_capture",</div><div class='add'>+	.table = {</div><div class='add'>+		GPIO_LOOKUP("AMDI0030:00", 85, "enable_isp", GPIO_ACTIVE_HIGH),</div><div class='add'>+		{ }</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gpiod_lookup_table isp_sensor_gpio_table = {</div><div class='add'>+	.dev_id = "i2c-ov05c10",</div><div class='add'>+	.table = {</div><div class='add'>+		GPIO_LOOKUP("amdisp-pinctrl", 0, "enable", GPIO_ACTIVE_HIGH),</div><div class='add'>+		{ }</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int isp_poweroff(struct generic_pm_domain *genpd)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_isp *isp = container_of(genpd, struct amdgpu_isp, ispgpd);</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+</div><div class='add'>+	return amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ISP, true, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_poweron(struct generic_pm_domain *genpd)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_isp *isp = container_of(genpd, struct amdgpu_isp, ispgpd);</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+</div><div class='add'>+	return amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ISP, false, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_set_performance_state(struct generic_pm_domain *genpd,</div><div class='add'>+				     unsigned int state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_isp *isp = container_of(genpd, struct amdgpu_isp, ispgpd);</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+	u32 iclk, xclk;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (state) {</div><div class='add'>+	case ISP_PERFORMANCE_STATE_HIGH:</div><div class='add'>+		xclk = ISP_HIGH_PERFORMANC_XCLK;</div><div class='add'>+		iclk = ISP_HIGH_PERFORMANC_ICLK;</div><div class='add'>+		break;</div><div class='add'>+	case ISP_PERFORMANCE_STATE_LOW:</div><div class='add'>+		/* isp runs at default lowest clock-rate on power-on, do nothing */</div><div class='add'>+		return 0;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dpm_set_soft_freq_range(adev, PP_ISPXCLK, xclk, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "failed to set xclk %u to %u: %d\n",</div><div class='add'>+			xclk, state, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dpm_set_soft_freq_range(adev, PP_ISPICLK, iclk, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "failed to set iclk %u to %u: %d\n",</div><div class='add'>+			iclk, state, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_genpd_add_device(struct device *dev, void *data)</div><div class='add'>+{</div><div class='add'>+	struct generic_pm_domain *gpd = data;</div><div class='add'>+	struct platform_device *pdev = container_of(dev, struct platform_device, dev);</div><div class='add'>+	struct amdgpu_isp *isp = container_of(gpd, struct amdgpu_isp, ispgpd);</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!pdev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!dev-&gt;type-&gt;name) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "Invalid device type to add\n");</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (strcmp(dev-&gt;type-&gt;name, "mfd_device")) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "Invalid isp mfd device %s to add\n", pdev-&gt;mfd_cell-&gt;name);</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pm_genpd_add_device(gpd, dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "Failed to add dev %s to genpd %d\n",</div><div class='add'>+			pdev-&gt;mfd_cell-&gt;name, ret);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+exit:</div><div class='add'>+	/* Continue to add */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_genpd_remove_device(struct device *dev, void *data)</div><div class='add'>+{</div><div class='add'>+	struct generic_pm_domain *gpd = data;</div><div class='add'>+	struct platform_device *pdev = container_of(dev, struct platform_device, dev);</div><div class='add'>+	struct amdgpu_isp *isp = container_of(gpd, struct amdgpu_isp, ispgpd);</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!pdev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!dev-&gt;type-&gt;name) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "Invalid device type to remove\n");</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (strcmp(dev-&gt;type-&gt;name, "mfd_device")) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "Invalid isp mfd device %s to remove\n",</div><div class='add'>+			pdev-&gt;mfd_cell-&gt;name);</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pm_genpd_remove_device(dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "Failed to remove dev from genpd %d\n", ret);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+exit:</div><div class='add'>+	/* Continue to remove */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)</div><div class='add'>+{</div><div class='add'>+	const struct software_node *amd_camera_node, *isp4_node;</div><div class='add'>+	struct amdgpu_device *adev = isp-&gt;adev;</div><div class='add'>+	struct acpi_device *acpi_dev;</div><div class='add'>+	int idx, int_idx, num_res, r;</div><div class='add'>+	u64 isp_base;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;rmmio_size == 0 || adev-&gt;rmmio_size &lt; 0x5289)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_acpi_get_isp4_dev(&amp;acpi_dev);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev, "Invalid isp platform detected (%d)", r);</div><div class='add'>+		/* allow GPU init to progress */</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* add GPIO resources required for OMNI5C10 sensor */</div><div class='add'>+	if (!strcmp("OMNI5C10", acpi_device_hid(acpi_dev))) {</div><div class='add'>+		gpiod_add_lookup_table(&amp;isp_gpio_table);</div><div class='add'>+		gpiod_add_lookup_table(&amp;isp_sensor_gpio_table);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp_base = adev-&gt;rmmio_base;</div><div class='add'>+</div><div class='add'>+	isp-&gt;ispgpd.name = "ISP_v_4_1_1";</div><div class='add'>+	isp-&gt;ispgpd.power_off = isp_poweroff;</div><div class='add'>+	isp-&gt;ispgpd.power_on = isp_poweron;</div><div class='add'>+	isp-&gt;ispgpd.set_performance_state = isp_set_performance_state;</div><div class='add'>+</div><div class='add'>+	r = pm_genpd_init(&amp;isp-&gt;ispgpd, NULL, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "failed to initialize genpd (%d)\n", r);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell = kcalloc(3, sizeof(struct mfd_cell), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_cell) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "isp mfd cell alloc failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_res = MAX_ISP411_MEM_RES + MAX_ISP411_INT_SRC;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_res = kcalloc(num_res, sizeof(struct resource),</div><div class='add'>+			       GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_res) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "isp mfd resource alloc failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_pdata = kzalloc(sizeof(*isp-&gt;isp_pdata), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_pdata) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "isp platform data alloc failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amd_camera_node = (const struct software_node *)acpi_dev-&gt;driver_data;</div><div class='add'>+	isp4_node = software_node_find_by_name(amd_camera_node, "isp4");</div><div class='add'>+</div><div class='add'>+	/* initialize isp platform data */</div><div class='add'>+	isp-&gt;isp_pdata-&gt;adev = (void *)adev;</div><div class='add'>+	isp-&gt;isp_pdata-&gt;asic_type = adev-&gt;asic_type;</div><div class='add'>+	isp-&gt;isp_pdata-&gt;base_rmmio_size = adev-&gt;rmmio_size;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_res[0].name = "isp_4_1_1_reg";</div><div class='add'>+	isp-&gt;isp_res[0].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_res[0].start = isp_base;</div><div class='add'>+	isp-&gt;isp_res[0].end = isp_base + ISP_REGS_OFFSET_END;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_res[1].name = "isp_4_1_1_phy0_reg";</div><div class='add'>+	isp-&gt;isp_res[1].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_res[1].start = isp_base + ISP411_PHY0_OFFSET;</div><div class='add'>+	isp-&gt;isp_res[1].end = isp_base + ISP411_PHY0_OFFSET + ISP411_PHY0_SIZE;</div><div class='add'>+</div><div class='add'>+	for (idx = MAX_ISP411_MEM_RES, int_idx = 0; idx &lt; num_res; idx++, int_idx++) {</div><div class='add'>+		isp-&gt;isp_res[idx].name = "isp_4_1_1_irq";</div><div class='add'>+		isp-&gt;isp_res[idx].flags = IORESOURCE_IRQ;</div><div class='add'>+		isp-&gt;isp_res[idx].start =</div><div class='add'>+			amdgpu_irq_create_mapping(adev, isp_4_1_1_int_srcid[int_idx]);</div><div class='add'>+		isp-&gt;isp_res[idx].end =</div><div class='add'>+			isp-&gt;isp_res[idx].start;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell[0].name = "amd_isp_capture";</div><div class='add'>+	isp-&gt;isp_cell[0].num_resources = num_res;</div><div class='add'>+	isp-&gt;isp_cell[0].resources = &amp;isp-&gt;isp_res[0];</div><div class='add'>+	isp-&gt;isp_cell[0].platform_data = isp-&gt;isp_pdata;</div><div class='add'>+	isp-&gt;isp_cell[0].swnode = isp4_node;</div><div class='add'>+	isp-&gt;isp_cell[0].pdata_size = sizeof(struct isp_platform_data);</div><div class='add'>+</div><div class='add'>+	/* initialize isp i2c platform data */</div><div class='add'>+	isp-&gt;isp_i2c_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_i2c_res) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "isp mfd res alloc failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_i2c_res[0].name = "isp_i2c0_reg";</div><div class='add'>+	isp-&gt;isp_i2c_res[0].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_i2c_res[0].start = isp_base + ISP411_I2C0_OFFSET;</div><div class='add'>+	isp-&gt;isp_i2c_res[0].end = isp_base + ISP411_I2C0_OFFSET + ISP411_I2C0_SIZE;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell[1].name = "amd_isp_i2c_designware";</div><div class='add'>+	isp-&gt;isp_cell[1].num_resources = 1;</div><div class='add'>+	isp-&gt;isp_cell[1].resources = &amp;isp-&gt;isp_i2c_res[0];</div><div class='add'>+	isp-&gt;isp_cell[1].platform_data = isp-&gt;isp_pdata;</div><div class='add'>+	isp-&gt;isp_cell[1].pdata_size = sizeof(struct isp_platform_data);</div><div class='add'>+</div><div class='add'>+	/* initialize isp gpiochip platform data */</div><div class='add'>+	isp-&gt;isp_gpio_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);</div><div class='add'>+	if (!isp-&gt;isp_gpio_res) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "isp gpio resource alloc failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_gpio_res[0].name = "isp_gpio_reg";</div><div class='add'>+	isp-&gt;isp_gpio_res[0].flags = IORESOURCE_MEM;</div><div class='add'>+	isp-&gt;isp_gpio_res[0].start = isp_base + ISP411_GPIO_SENSOR_OFFSET;</div><div class='add'>+	isp-&gt;isp_gpio_res[0].end = isp_base + ISP411_GPIO_SENSOR_OFFSET +</div><div class='add'>+				   ISP411_GPIO_SENSOR_SIZE;</div><div class='add'>+</div><div class='add'>+	isp-&gt;isp_cell[2].name = "amdisp-pinctrl";</div><div class='add'>+	isp-&gt;isp_cell[2].num_resources = 1;</div><div class='add'>+	isp-&gt;isp_cell[2].resources = &amp;isp-&gt;isp_gpio_res[0];</div><div class='add'>+	isp-&gt;isp_cell[2].platform_data = isp-&gt;isp_pdata;</div><div class='add'>+	isp-&gt;isp_cell[2].pdata_size = sizeof(struct isp_platform_data);</div><div class='add'>+</div><div class='add'>+	/* add only amd_isp_capture and amd_isp_i2c_designware to genpd */</div><div class='add'>+	r = mfd_add_hotplug_devices(isp-&gt;parent, isp-&gt;isp_cell, 2);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "add mfd hotplug device failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = device_for_each_child(isp-&gt;parent, &amp;isp-&gt;ispgpd,</div><div class='add'>+				  isp_genpd_add_device);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "failed to add devices to genpd (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = mfd_add_hotplug_devices(isp-&gt;parent, &amp;isp-&gt;isp_cell[2], 1);</div><div class='add'>+	if (r) {</div><div class='add'>+		drm_err(&amp;adev-&gt;ddev, "add pinctl hotplug device failed (%d)\n", r);</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+failure:</div><div class='add'>+</div><div class='add'>+	kfree(isp-&gt;isp_pdata);</div><div class='add'>+	kfree(isp-&gt;isp_res);</div><div class='add'>+	kfree(isp-&gt;isp_cell);</div><div class='add'>+	kfree(isp-&gt;isp_i2c_res);</div><div class='add'>+	kfree(isp-&gt;isp_gpio_res);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isp_v4_1_1_hw_fini(struct amdgpu_isp *isp)</div><div class='add'>+{</div><div class='add'>+	device_for_each_child(isp-&gt;parent, NULL,</div><div class='add'>+			      isp_genpd_remove_device);</div><div class='add'>+</div><div class='add'>+	mfd_remove_devices(isp-&gt;parent);</div><div class='add'>+</div><div class='add'>+	kfree(isp-&gt;isp_res);</div><div class='add'>+	kfree(isp-&gt;isp_cell);</div><div class='add'>+	kfree(isp-&gt;isp_pdata);</div><div class='add'>+	kfree(isp-&gt;isp_i2c_res);</div><div class='add'>+	kfree(isp-&gt;isp_gpio_res);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct isp_funcs isp_v4_1_1_funcs = {</div><div class='add'>+	.hw_init = isp_v4_1_1_hw_init,</div><div class='add'>+	.hw_fini = isp_v4_1_1_hw_fini,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp)</div><div class='add'>+{</div><div class='add'>+	isp-&gt;funcs = &amp;isp_v4_1_1_funcs;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h<br/>new file mode 100644<br/>index 000000000000..fe45d70d87f1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __ISP_V4_1_1_H__</div><div class='add'>+#define __ISP_V4_1_1_H__</div><div class='add'>+</div><div class='add'>+#include "amdgpu_isp.h"</div><div class='add'>+</div><div class='add'>+#include "ivsrcid/isp/irqsrcs_isp_4_1.h"</div><div class='add'>+</div><div class='add'>+#define MAX_ISP411_MEM_RES 2</div><div class='add'>+#define MAX_ISP411_INT_SRC 8</div><div class='add'>+</div><div class='add'>+#define ISP411_PHY0_OFFSET 0x66700</div><div class='add'>+#define ISP411_PHY0_SIZE   0xD30</div><div class='add'>+</div><div class='add'>+#define ISP411_I2C0_OFFSET 0x66400</div><div class='add'>+#define ISP411_I2C0_SIZE 0x100</div><div class='add'>+</div><div class='add'>+#define ISP411_GPIO_SENSOR_OFFSET 0x6613C</div><div class='add'>+#define ISP411_GPIO_SENSOR_SIZE 0x54</div><div class='add'>+</div><div class='add'>+void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c<br/>index 77595e9622da..b5bb7f4d607c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_jpeg.h"</div><div class='add'>+#include "amdgpu_cs.h"</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "soc15d.h"</div><div class='ctx'> #include "vcn_v1_0.h"</div><div class='hunk'>@@ -34,6 +35,9 @@</div><div class='ctx'> static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring);</div><div class='add'>+static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,</div><div class='add'>+				     struct amdgpu_job *job,</div><div class='add'>+				     struct amdgpu_ib *ib);</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)</div><div class='ctx'> {</div><div class='hunk'>@@ -300,7 +304,10 @@ static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring,</div><div class='ctx'> 		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4)));</div><div class='add'>+	if (ring-&gt;funcs-&gt;parse_cs)</div><div class='add'>+		amdgpu_ring_write(ring, 0);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4)));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring,</div><div class='ctx'> 		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));</div><div class='hunk'>@@ -451,13 +458,13 @@ static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v1_0_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-int jpeg_v1_0_early_init(void *handle)</div><div class='add'>+int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_inst = 1;</div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_rings = 1;</div><div class='hunk'>@@ -471,12 +478,12 @@ int jpeg_v1_0_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v1_0_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-int jpeg_v1_0_sw_init(void *handle)</div><div class='add'>+int jpeg_v1_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -502,13 +509,13 @@ int jpeg_v1_0_sw_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v1_0_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-void jpeg_v1_0_sw_fini(void *handle)</div><div class='add'>+void jpeg_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_fini(adev-&gt;jpeg.inst-&gt;ring_dec);</div><div class='ctx'> }</div><div class='hunk'>@@ -550,10 +557,11 @@ static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = {</div><div class='ctx'> 	.nop = PACKET0(0x81ff, 0),</div><div class='ctx'> 	.support_64bit_ptrs = false,</div><div class='ctx'> 	.no_user_fence = true,</div><div class='del'>-	.extra_dw = 64,</div><div class='add'>+	.extra_bytes = 256,</div><div class='ctx'> 	.get_rptr = jpeg_v1_0_decode_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v1_0_decode_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v1_0_decode_ring_set_wptr,</div><div class='add'>+	.parse_cs = jpeg_v1_dec_ring_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		6 + 6 + /* hdp invalidate / flush */</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='hunk'>@@ -581,7 +589,6 @@ static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = {</div><div class='ctx'> static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;ring_dec-&gt;funcs = &amp;jpeg_v1_0_decode_ring_vm_funcs;</div><div class='del'>-	DRM_INFO("JPEG decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs jpeg_v1_0_irq_funcs = {</div><div class='hunk'>@@ -597,18 +604,84 @@ static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct	amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	bool	set_clocks = !cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	bool	set_clocks = !cancel_delayed_work_sync(&amp;adev-&gt;vcn.inst[0].idle_work);</div><div class='ctx'> 	int		cnt = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;adev-&gt;vcn.vcn1_jpeg1_workaround);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;vcn.inst[0].vcn1_jpeg1_workaround);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_fence_wait_empty(&amp;adev-&gt;vcn.inst-&gt;ring_dec))</div><div class='ctx'> 		DRM_ERROR("JPEG dec: vcn dec ring may not be empty\n");</div><div class='ctx'> </div><div class='del'>-	for (cnt = 0; cnt &lt; adev-&gt;vcn.num_enc_rings; cnt++) {</div><div class='add'>+	for (cnt = 0; cnt &lt; adev-&gt;vcn.inst[0].num_enc_rings; cnt++) {</div><div class='ctx'> 		if (amdgpu_fence_wait_empty(&amp;adev-&gt;vcn.inst-&gt;ring_enc[cnt]))</div><div class='ctx'> 			DRM_ERROR("JPEG dec: vcn enc ring[%d] may not be empty\n", cnt);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v1_dec_ring_parse_cs - command submission parser</div><div class='add'>+ *</div><div class='add'>+ * @parser: Command submission parser context</div><div class='add'>+ * @job: the job to parse</div><div class='add'>+ * @ib: the IB to parse</div><div class='add'>+ *</div><div class='add'>+ * Parse the command stream, return -EINVAL for invalid packet,</div><div class='add'>+ * 0 otherwise</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,</div><div class='add'>+				     struct amdgpu_job *job,</div><div class='add'>+				     struct amdgpu_ib *ib)</div><div class='add'>+{</div><div class='add'>+	u32 i, reg, res, cond, type;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	struct amdgpu_device *adev = parser-&gt;adev;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ib-&gt;length_dw ; i += 2) {</div><div class='add'>+		reg  = CP_PACKETJ_GET_REG(ib-&gt;ptr[i]);</div><div class='add'>+		res  = CP_PACKETJ_GET_RES(ib-&gt;ptr[i]);</div><div class='add'>+		cond = CP_PACKETJ_GET_COND(ib-&gt;ptr[i]);</div><div class='add'>+		type = CP_PACKETJ_GET_TYPE(ib-&gt;ptr[i]);</div><div class='add'>+</div><div class='add'>+		if (res || cond != PACKETJ_CONDITION_CHECK0) /* only allow 0 for now */</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (reg &gt;= JPEG_V1_REG_RANGE_START &amp;&amp; reg &lt;= JPEG_V1_REG_RANGE_END)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		switch (type) {</div><div class='add'>+		case PACKETJ_TYPE0:</div><div class='add'>+			if (reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH &amp;&amp;</div><div class='add'>+			    reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW &amp;&amp;</div><div class='add'>+			    reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH &amp;&amp;</div><div class='add'>+			    reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW &amp;&amp;</div><div class='add'>+			    reg != JPEG_V1_REG_CTX_INDEX &amp;&amp;</div><div class='add'>+			    reg != JPEG_V1_REG_CTX_DATA) {</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case PACKETJ_TYPE1:</div><div class='add'>+			if (reg != JPEG_V1_REG_CTX_DATA)</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		case PACKETJ_TYPE3:</div><div class='add'>+			if (reg != JPEG_V1_REG_SOFT_RESET)</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		case PACKETJ_TYPE6:</div><div class='add'>+			if (ib-&gt;ptr[i] != CP_PACKETJ_NOP)</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Invalid packet [0x%08x]!\n", ib-&gt;ptr[i]);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h<br/>index bbf33a6a3972..097328635083 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h</a></div><div class='hunk'>@@ -24,9 +24,20 @@</div><div class='ctx'> #ifndef __JPEG_V1_0_H__</div><div class='ctx'> #define __JPEG_V1_0_H__</div><div class='ctx'> </div><div class='del'>-int jpeg_v1_0_early_init(void *handle);</div><div class='del'>-int jpeg_v1_0_sw_init(void *handle);</div><div class='del'>-void jpeg_v1_0_sw_fini(void *handle);</div><div class='add'>+int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block);</div><div class='add'>+int jpeg_v1_0_sw_init(struct amdgpu_ip_block *ip_block);</div><div class='add'>+void jpeg_v1_0_sw_fini(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> void jpeg_v1_0_start(struct amdgpu_device *adev, int mode);</div><div class='ctx'> </div><div class='add'>+#define JPEG_V1_REG_RANGE_START	0x8000</div><div class='add'>+#define JPEG_V1_REG_RANGE_END	0x803f</div><div class='add'>+</div><div class='add'>+#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH	0x8238</div><div class='add'>+#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW	0x8239</div><div class='add'>+#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH	0x825a</div><div class='add'>+#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW	0x825b</div><div class='add'>+#define JPEG_V1_REG_CTX_INDEX			0x8328</div><div class='add'>+#define JPEG_V1_REG_CTX_DATA			0x8329</div><div class='add'>+#define JPEG_V1_REG_SOFT_RESET			0x83a0</div><div class='add'>+</div><div class='ctx'> #endif /*__JPEG_V1_0_H__*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c<br/>index 1c8116d75f63..27c76bd424cf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c</a></div><div class='hunk'>@@ -32,21 +32,37 @@</div><div class='ctx'> #include "vcn/vcn_2_0_0_sh_mask.h"</div><div class='ctx'> #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v2_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_early_init(void *handle)</div><div class='add'>+static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_inst = 1;</div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_rings = 1;</div><div class='hunk'>@@ -60,13 +76,13 @@ static int jpeg_v2_0_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_sw_init(void *handle)</div><div class='add'>+static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -97,25 +113,37 @@ static int jpeg_v2_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(adev-&gt;jpeg.inst[0].ring_dec);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -124,41 +152,36 @@ static int jpeg_v2_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_hw_init(void *handle)</div><div class='add'>+static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;jpeg.inst-&gt;ring_dec;</div><div class='del'>-	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='ctx'> 		(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1), 0);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ring_test_helper(ring);</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("JPEG decode initialized successfully.\n");</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return amdgpu_ring_test_helper(ring);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))</div><div class='del'>-		jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+		jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -166,20 +189,19 @@ static int jpeg_v2_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_suspend(void *handle)</div><div class='add'>+static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v2_0_hw_fini(adev);</div><div class='add'>+	r = jpeg_v2_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -187,20 +209,19 @@ static int jpeg_v2_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_0_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_0_resume(void *handle)</div><div class='add'>+static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v2_0_hw_init(adev);</div><div class='add'>+	r = jpeg_v2_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -543,11 +564,15 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4)));</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;parse_cs)</div><div class='add'>+		amdgpu_ring_write(ring, 0);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4) | (vmid &lt;&lt; 8)));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4)));</div><div class='add'>+	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4) | (vmid &lt;&lt; 8)));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='hunk'>@@ -657,18 +682,18 @@ void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v2_0_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &amp;</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v2_0_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,</div><div class='hunk'>@@ -677,14 +702,14 @@ static int jpeg_v2_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v2_0_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='del'>-		if (!jpeg_v2_0_is_idle(handle))</div><div class='add'>+		if (!jpeg_v2_0_is_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 		jpeg_v2_0_enable_clock_gating(adev);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -694,10 +719,10 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v2_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (state == adev-&gt;jpeg.cur_state)</div><div class='hunk'>@@ -741,10 +766,25 @@ static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				unsigned int vmid,</div><div class='add'>+				struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = jpeg_v2_0_stop(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = jpeg_v2_0_start(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v2_0",</div><div class='ctx'> 	.early_init = jpeg_v2_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v2_0_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v2_0_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v2_0_hw_init,</div><div class='hunk'>@@ -753,12 +793,10 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v2_0_resume,</div><div class='ctx'> 	.is_idle = jpeg_v2_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v2_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v2_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v2_0_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -767,6 +805,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v2_0_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v2_0_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v2_0_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -788,12 +827,12 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v2_0_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;ring_dec-&gt;funcs = &amp;jpeg_v2_0_dec_ring_vm_funcs;</div><div class='del'>-	DRM_INFO("JPEG decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c<br/>index 99cd49ee8ef6..20983f126b49 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c</a></div><div class='hunk'>@@ -36,9 +36,25 @@</div><div class='ctx'> </div><div class='ctx'> #define JPEG25_MAX_HW_INSTANCES_ARCTURUS			2</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_5[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v2_5_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='ctx'> static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='hunk'>@@ -50,13 +66,13 @@ static int amdgpu_ih_clientid_jpeg[] = {</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_early_init(void *handle)</div><div class='add'>+static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 harvest;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -81,15 +97,15 @@ static int jpeg_v2_5_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_sw_init(void *handle)</div><div class='add'>+static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='hunk'>@@ -147,25 +163,37 @@ static int jpeg_v2_5_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_5, ARRAY_SIZE(jpeg_reg_list_2_5));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(adev-&gt;jpeg.inst[0].ring_dec);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -174,12 +202,12 @@ static int jpeg_v2_5_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_hw_init(void *handle)</div><div class='add'>+static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='hunk'>@@ -196,24 +224,22 @@ static int jpeg_v2_5_hw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("JPEG decode initialized successfully.\n");</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='hunk'>@@ -221,7 +247,7 @@ static int jpeg_v2_5_hw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 		      RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))</div><div class='del'>-			jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))</div><div class='ctx'> 			amdgpu_irq_put(adev, &amp;adev-&gt;jpeg.inst[i].ras_poison_irq, 0);</div><div class='hunk'>@@ -233,20 +259,19 @@ static int jpeg_v2_5_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_suspend(void *handle)</div><div class='add'>+static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v2_5_hw_fini(adev);</div><div class='add'>+	r = jpeg_v2_5_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -254,20 +279,19 @@ static int jpeg_v2_5_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v2_5_resume(void *handle)</div><div class='add'>+static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v2_5_hw_init(adev);</div><div class='add'>+	r = jpeg_v2_5_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -314,6 +338,44 @@ static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> 	WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void jpeg_v2_5_start_inst(struct amdgpu_device *adev, int i)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring = adev-&gt;jpeg.inst[i].ring_dec;</div><div class='add'>+	/* disable anti hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,</div><div class='add'>+		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+	/* JPEG disable CGC */</div><div class='add'>+	jpeg_v2_5_disable_clock_gating(adev, i);</div><div class='add'>+</div><div class='add'>+	/* MJPEG global tiling registers */</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,</div><div class='add'>+		adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='add'>+		adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* enable JMI channel */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,</div><div class='add'>+		~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+</div><div class='add'>+	/* enable System Interrupt for JRBC */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),</div><div class='add'>+		JPEG_SYS_INT_EN__DJRBC_MASK,</div><div class='add'>+		~JPEG_SYS_INT_EN__DJRBC_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='add'>+		lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,</div><div class='add'>+		upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);</div><div class='add'>+	WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_start - start JPEG block</div><div class='ctx'>  *</div><div class='hunk'>@@ -323,52 +385,33 @@ static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'>  */</div><div class='ctx'> static int jpeg_v2_5_start(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='add'>+		jpeg_v2_5_start_inst(adev, i);</div><div class='ctx'> </div><div class='del'>-		ring = adev-&gt;jpeg.inst[i].ring_dec;</div><div class='del'>-		/* disable anti hang mechanism */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,</div><div class='del'>-			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='del'>-</div><div class='del'>-		/* JPEG disable CGC */</div><div class='del'>-		jpeg_v2_5_disable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* MJPEG global tiling registers */</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,</div><div class='del'>-			adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='del'>-			adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* enable JMI channel */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,</div><div class='del'>-			~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='del'>-</div><div class='del'>-		/* enable System Interrupt for JRBC */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),</div><div class='del'>-			JPEG_SYS_INT_EN__DJRBC_MASK,</div><div class='del'>-			~JPEG_SYS_INT_EN__DJRBC_MASK);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='del'>-			lower_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,</div><div class='del'>-			upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);</div><div class='del'>-		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void jpeg_v2_5_stop_inst(struct amdgpu_device *adev, int i)</div><div class='add'>+{</div><div class='add'>+	/* reset JMI */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),</div><div class='add'>+		UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='add'>+		~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+</div><div class='add'>+	jpeg_v2_5_enable_clock_gating(adev, i);</div><div class='add'>+</div><div class='add'>+	/* enable anti hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),</div><div class='add'>+		UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,</div><div class='add'>+		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v2_5_stop - stop JPEG block</div><div class='ctx'>  *</div><div class='hunk'>@@ -383,18 +426,7 @@ static int jpeg_v2_5_stop(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='del'>-</div><div class='del'>-		/* reset JMI */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),</div><div class='del'>-			UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='del'>-			~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='del'>-</div><div class='del'>-		jpeg_v2_5_enable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* enable anti hang mechanism */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),</div><div class='del'>-			UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,</div><div class='del'>-			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+		jpeg_v2_5_stop_inst(adev, i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -486,9 +518,9 @@ static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_ring_write(ring, (1 &lt;&lt; (ring-&gt;me * 2 + 14)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v2_5_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='hunk'>@@ -503,9 +535,9 @@ static bool jpeg_v2_5_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v2_5_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='hunk'>@@ -522,10 +554,10 @@ static int jpeg_v2_5_wait_for_idle(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v2_5_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -534,7 +566,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (enable) {</div><div class='del'>-			if (!jpeg_v2_5_is_idle(handle))</div><div class='add'>+			if (!jpeg_v2_5_is_idle(ip_block))</div><div class='ctx'> 				return -EBUSY;</div><div class='ctx'> 			jpeg_v2_5_enable_clock_gating(adev, i);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -545,10 +577,10 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v2_5_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (state == adev-&gt;jpeg.cur_state)</div><div class='hunk'>@@ -614,10 +646,19 @@ static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v2_5_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				unsigned int vmid,</div><div class='add'>+				struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	jpeg_v2_5_stop_inst(ring-&gt;adev, ring-&gt;me);</div><div class='add'>+	jpeg_v2_5_start_inst(ring-&gt;adev, ring-&gt;me);</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v2_5",</div><div class='ctx'> 	.early_init = jpeg_v2_5_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v2_5_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v2_5_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v2_5_hw_init,</div><div class='hunk'>@@ -626,18 +667,15 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v2_5_resume,</div><div class='ctx'> 	.is_idle = jpeg_v2_5_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v2_5_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v2_5_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v2_5_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v2_6",</div><div class='ctx'> 	.early_init = jpeg_v2_5_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v2_5_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v2_5_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v2_5_hw_init,</div><div class='hunk'>@@ -646,12 +684,10 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v2_5_resume,</div><div class='ctx'> 	.is_idle = jpeg_v2_5_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v2_5_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v2_5_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v2_5_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -660,6 +696,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v2_5_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v2_5_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v2_5_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -681,6 +718,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v2_5_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -689,6 +727,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v2_5_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v2_5_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v2_5_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -710,6 +749,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v2_5_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -724,7 +764,6 @@ static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		else  /* CHIP_ALDEBARAN */</div><div class='ctx'> 			adev-&gt;jpeg.inst[i].ring_dec-&gt;funcs = &amp;jpeg_v2_6_dec_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;jpeg.inst[i].ring_dec-&gt;me = i;</div><div class='del'>-		DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c<br/>index a92481da60cd..d1a011c40ba2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c</a></div><div class='hunk'>@@ -34,21 +34,37 @@</div><div class='ctx'> </div><div class='ctx'> #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET	0x401f</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_3_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v3_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_early_init(void *handle)</div><div class='add'>+static int jpeg_v3_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	u32 harvest;</div><div class='ctx'> </div><div class='hunk'>@@ -75,13 +91,13 @@ static int jpeg_v3_0_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_sw_init(void *handle)</div><div class='add'>+static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -112,25 +128,37 @@ static int jpeg_v3_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_3_0, ARRAY_SIZE(jpeg_reg_list_3_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(adev-&gt;jpeg.inst[0].ring_dec);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -139,43 +167,36 @@ static int jpeg_v3_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_hw_init(void *handle)</div><div class='add'>+static int jpeg_v3_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;jpeg.inst-&gt;ring_dec;</div><div class='del'>-	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='ctx'> 		(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1), 0);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ring_test_helper(ring);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	DRM_INFO("JPEG decode initialized successfully.\n");</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return amdgpu_ring_test_helper(ring);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))</div><div class='del'>-		jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+		jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -183,20 +204,19 @@ static int jpeg_v3_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_suspend(void *handle)</div><div class='add'>+static int jpeg_v3_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v3_0_hw_fini(adev);</div><div class='add'>+	r = jpeg_v3_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -204,20 +224,19 @@ static int jpeg_v3_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v3_0_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v3_0_resume(void *handle)</div><div class='add'>+static int jpeg_v3_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v3_0_hw_init(adev);</div><div class='add'>+	r = jpeg_v3_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -454,9 +473,9 @@ static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v3_0_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v3_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	ret &amp;= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &amp;</div><div class='hunk'>@@ -466,23 +485,23 @@ static bool jpeg_v3_0_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v3_0_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v3_0_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='del'>-		if (!jpeg_v3_0_is_idle(handle))</div><div class='add'>+		if (!jpeg_v3_0_is_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 		jpeg_v3_0_enable_clock_gating(adev);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -492,10 +511,10 @@ static int jpeg_v3_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v3_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if(state == adev-&gt;jpeg.cur_state)</div><div class='hunk'>@@ -539,10 +558,25 @@ static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v3_0_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				unsigned int vmid,</div><div class='add'>+				struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = jpeg_v3_0_stop(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = jpeg_v3_0_start(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v3_0",</div><div class='ctx'> 	.early_init = jpeg_v3_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v3_0_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v3_0_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v3_0_hw_init,</div><div class='hunk'>@@ -551,12 +585,10 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v3_0_resume,</div><div class='ctx'> 	.is_idle = jpeg_v3_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v3_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v3_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v3_0_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -565,6 +597,7 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v3_0_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v3_0_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v3_0_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -586,12 +619,12 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v3_0_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;ring_dec-&gt;funcs = &amp;jpeg_v3_0_dec_ring_vm_funcs;</div><div class='del'>-	DRM_INFO("JPEG decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c<br/>index 88ea58d5c4ab..33db2c1ae6cc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c</a></div><div class='hunk'>@@ -36,25 +36,40 @@</div><div class='ctx'> </div><div class='ctx'> #define regUVD_JPEG_PITCH_INTERNAL_OFFSET                  0x401f</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v4_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='ctx'> static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);</div><div class='del'>-</div><div class='ctx'> static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_early_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_inst = 1;</div><div class='hunk'>@@ -70,13 +85,13 @@ static int jpeg_v4_0_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_sw_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -124,25 +139,36 @@ static int jpeg_v4_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(adev-&gt;jpeg.inst[0].ring_dec);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -151,12 +177,12 @@ static int jpeg_v4_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_hw_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;jpeg.inst-&gt;ring_dec;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -181,27 +207,25 @@ static int jpeg_v4_0_hw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "JPEG decode initialized successfully.\n");</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 			RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))</div><div class='del'>-			jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))</div><div class='ctx'> 		amdgpu_irq_put(adev, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq, 0);</div><div class='hunk'>@@ -212,20 +236,19 @@ static int jpeg_v4_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_suspend(void *handle)</div><div class='add'>+static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v4_0_hw_fini(adev);</div><div class='add'>+	r = jpeg_v4_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -233,20 +256,19 @@ static int jpeg_v4_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_resume(void *handle)</div><div class='add'>+static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v4_0_hw_init(adev);</div><div class='add'>+	r = jpeg_v4_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -611,9 +633,9 @@ static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v4_0_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	ret &amp;= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &amp;</div><div class='hunk'>@@ -623,23 +645,23 @@ static bool jpeg_v4_0_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='del'>-		if (!jpeg_v4_0_is_idle(handle))</div><div class='add'>+		if (!jpeg_v4_0_is_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 		jpeg_v4_0_enable_clock_gating(adev);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -649,10 +671,10 @@ static int jpeg_v4_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='hunk'>@@ -701,10 +723,25 @@ static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v4_0_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				unsigned int vmid,</div><div class='add'>+				struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = jpeg_v4_0_stop(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = jpeg_v4_0_start(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v4_0",</div><div class='ctx'> 	.early_init = jpeg_v4_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v4_0_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v4_0_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v4_0_hw_init,</div><div class='hunk'>@@ -713,12 +750,10 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v4_0_resume,</div><div class='ctx'> 	.is_idle = jpeg_v4_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v4_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v4_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v4_0_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -727,6 +762,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v4_0_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v4_0_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v4_0_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -748,12 +784,12 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v4_0_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;ring_dec-&gt;funcs = &amp;jpeg_v4_0_dec_ring_vm_funcs;</div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "JPEG decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h<br/>index 07d36c2abd6b..47638fd4d4e2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h</a></div><div class='hunk'>@@ -32,5 +32,4 @@ enum amdgpu_jpeg_v4_0_sub_block {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern const struct amdgpu_ip_block_version jpeg_v4_0_ip_block;</div><div class='del'>-</div><div class='ctx'> #endif /* __JPEG_V4_0_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c<br/>index 32caeb37cef9..aae7328973d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c</a></div><div class='hunk'>@@ -25,6 +25,7 @@</div><div class='ctx'> #include "amdgpu_jpeg.h"</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "soc15d.h"</div><div class='add'>+#include "jpeg_v2_0.h"</div><div class='ctx'> #include "jpeg_v4_0_3.h"</div><div class='ctx'> #include "mmsch_v4_0_3.h"</div><div class='ctx'> </div><div class='hunk'>@@ -32,6 +33,9 @@</div><div class='ctx'> #include "vcn/vcn_4_0_3_sh_mask.h"</div><div class='ctx'> #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"</div><div class='ctx'> </div><div class='add'>+#define NORMALIZE_JPEG_REG_OFFSET(offset) \</div><div class='add'>+		(offset &amp; 0x1FFFF)</div><div class='add'>+</div><div class='ctx'> enum jpeg_engin_status {</div><div class='ctx'> 	UVD_PGFSM_STATUS__UVDJ_PWR_ON  = 0,</div><div class='ctx'> 	UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2,</div><div class='hunk'>@@ -39,7 +43,7 @@ enum jpeg_engin_status {</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v4_0_3_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='ctx'> static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='hunk'>@@ -55,18 +59,67 @@ static int amdgpu_ih_srcid_jpeg[] = {</div><div class='ctx'> 	VCN_4_0__SRCID__JPEG7_DECODE</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_3[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return (adev-&gt;jpeg.caps &amp; AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int jpeg_v4_0_3_core_reg_offset(u32 pipe)</div><div class='add'>+{</div><div class='add'>+	if (pipe)</div><div class='add'>+		return ((0x40 * pipe) - 0xc80);</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_early_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;</div><div class='add'>+	adev-&gt;jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;</div><div class='ctx'> </div><div class='ctx'> 	jpeg_v4_0_3_set_dec_ring_funcs(adev);</div><div class='ctx'> 	jpeg_v4_0_3_set_irq_funcs(adev);</div><div class='hunk'>@@ -78,13 +131,13 @@ static int jpeg_v4_0_3_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_sw_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, j, r, jpeg_inst;</div><div class='ctx'> </div><div class='hunk'>@@ -96,6 +149,18 @@ static int jpeg_v4_0_3_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* JPEG DJPEG POISON EVENT */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+			VCN_4_0__SRCID_DJPEG0_POISON, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* JPEG EJPEG POISON EVENT */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+			VCN_4_0__SRCID_EJPEG0_POISON, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_jpeg_sw_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -134,10 +199,8 @@ static int jpeg_v4_0_3_sw_init(void *handle)</div><div class='ctx'> 			adev-&gt;jpeg.internal.jpeg_pitch[j] =</div><div class='ctx'> 				regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;</div><div class='ctx'> 			adev-&gt;jpeg.inst[i].external.jpeg_pitch[j] =</div><div class='del'>-				SOC15_REG_OFFSET1(</div><div class='del'>-					JPEG, jpeg_inst,</div><div class='del'>-					regUVD_JRBC0_UVD_JRBC_SCRATCH0,</div><div class='del'>-					(j ? (0x40 * j - 0xc80) : 0));</div><div class='add'>+				SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_SCRATCH0,</div><div class='add'>+						  jpeg_v4_0_3_core_reg_offset(j));</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -149,25 +212,37 @@ static int jpeg_v4_0_3_sw_init(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_3, ARRAY_SIZE(jpeg_reg_list_4_0_3));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(adev-&gt;jpeg.inst[0].ring_dec);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -289,12 +364,12 @@ static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_hw_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, j, r, jpeg_inst;</div><div class='ctx'> </div><div class='hunk'>@@ -303,7 +378,7 @@ static int jpeg_v4_0_3_hw_init(void *handle)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 			for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='ctx'> 				ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='ctx'> 				ring-&gt;wptr = 0;</div><div class='hunk'>@@ -313,6 +388,11 @@ static int jpeg_v4_0_3_hw_init(void *handle)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='add'>+		/* This flag is not set for VF, assumed to be disabled always */</div><div class='add'>+		if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &amp;</div><div class='add'>+		    0x100)</div><div class='add'>+			adev-&gt;jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED);</div><div class='add'>+</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 			jpeg_inst = GET_INST(JPEG, i);</div><div class='ctx'> </div><div class='hunk'>@@ -341,7 +421,6 @@ static int jpeg_v4_0_3_hw_init(void *handle)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "JPEG decode initialized successfully.\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -349,42 +428,44 @@ static int jpeg_v4_0_3_hw_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE)</div><div class='del'>-			ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) &amp;&amp; !amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_suspend(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v4_0_3_hw_fini(adev);</div><div class='add'>+	r = jpeg_v4_0_3_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -392,20 +473,19 @@ static int jpeg_v4_0_3_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_3_resume(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v4_0_3_hw_init(adev);</div><div class='add'>+	r = jpeg_v4_0_3_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -460,6 +540,75 @@ static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst</div><div class='ctx'> 	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void jpeg_v4_0_3_start_inst(struct amdgpu_device *adev, int inst)</div><div class='add'>+{</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, inst);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,</div><div class='add'>+		     1 &lt;&lt; UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);</div><div class='add'>+	SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS,</div><div class='add'>+			   UVD_PGFSM_STATUS__UVDJ_PWR_ON &lt;&lt;</div><div class='add'>+			   UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,</div><div class='add'>+			   UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable anti hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+		 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+	/* JPEG disable CGC */</div><div class='add'>+	jpeg_v4_0_3_disable_clock_gating(adev, inst);</div><div class='add'>+</div><div class='add'>+	/* MJPEG global tiling registers */</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* enable JMI channel */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,</div><div class='add'>+		 ~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void jpeg_v4_0_3_start_jrbc(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, ring-&gt;me);</div><div class='add'>+	int reg_offset = jpeg_v4_0_3_core_reg_offset(ring-&gt;pipe);</div><div class='add'>+</div><div class='add'>+	/* enable System Interrupt for JRBC */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN),</div><div class='add'>+		 JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; ring-&gt;pipe,</div><div class='add'>+		 ~(JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; ring-&gt;pipe));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_LMI_JRBC_RB_VMID,</div><div class='add'>+			    reg_offset, 0);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC0_UVD_JRBC_RB_CNTL,</div><div class='add'>+			    reg_offset,</div><div class='add'>+			    (0x00000001L | 0x00000002L));</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='add'>+			    reg_offset, lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,</div><div class='add'>+			    reg_offset, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC0_UVD_JRBC_RB_RPTR,</div><div class='add'>+			    reg_offset, 0);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='add'>+			    reg_offset, 0);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC0_UVD_JRBC_RB_CNTL,</div><div class='add'>+			    reg_offset, 0x00000002L);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC0_UVD_JRBC_RB_SIZE,</div><div class='add'>+			    reg_offset, ring-&gt;ring_size / 4);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='add'>+					 reg_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_start - start JPEG block</div><div class='ctx'>  *</div><div class='hunk'>@@ -470,84 +619,36 @@ static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst</div><div class='ctx'> static int jpeg_v4_0_3_start(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	int i, j, jpeg_inst;</div><div class='add'>+	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='del'>-		jpeg_inst = GET_INST(JPEG, i);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,</div><div class='del'>-			     1 &lt;&lt; UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);</div><div class='del'>-		SOC15_WAIT_ON_RREG(</div><div class='del'>-			JPEG, jpeg_inst, regUVD_PGFSM_STATUS,</div><div class='del'>-			UVD_PGFSM_STATUS__UVDJ_PWR_ON</div><div class='del'>-				&lt;&lt; UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,</div><div class='del'>-			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable anti hang mechanism */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					  regUVD_JPEG_POWER_STATUS),</div><div class='del'>-			 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='del'>-</div><div class='del'>-		/* JPEG disable CGC */</div><div class='del'>-		jpeg_v4_0_3_disable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* MJPEG global tiling registers */</div><div class='del'>-		WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG,</div><div class='del'>-			     adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-		WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='del'>-			     adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* enable JMI channel */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,</div><div class='del'>-			 ~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='del'>-</div><div class='add'>+		jpeg_v4_0_3_start_inst(adev, i);</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='del'>-			unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);</div><div class='del'>-</div><div class='ctx'> 			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='del'>-</div><div class='del'>-			/* enable System Interrupt for JRBC */</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-						  regJPEG_SYS_INT_EN),</div><div class='del'>-				 JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; j,</div><div class='del'>-				 ~(JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; j));</div><div class='del'>-</div><div class='del'>-			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					    regUVD_JMI0_UVD_LMI_JRBC_RB_VMID,</div><div class='del'>-					    reg_offset, 0);</div><div class='del'>-			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					    regUVD_JRBC0_UVD_JRBC_RB_CNTL,</div><div class='del'>-					    reg_offset,</div><div class='del'>-					    (0x00000001L | 0x00000002L));</div><div class='del'>-			WREG32_SOC15_OFFSET(</div><div class='del'>-				JPEG, jpeg_inst,</div><div class='del'>-				regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='del'>-				reg_offset, lower_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-			WREG32_SOC15_OFFSET(</div><div class='del'>-				JPEG, jpeg_inst,</div><div class='del'>-				regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH,</div><div class='del'>-				reg_offset, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					    regUVD_JRBC0_UVD_JRBC_RB_RPTR,</div><div class='del'>-					    reg_offset, 0);</div><div class='del'>-			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					    regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='del'>-					    reg_offset, 0);</div><div class='del'>-			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					    regUVD_JRBC0_UVD_JRBC_RB_CNTL,</div><div class='del'>-					    reg_offset, 0x00000002L);</div><div class='del'>-			WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					    regUVD_JRBC0_UVD_JRBC_RB_SIZE,</div><div class='del'>-					    reg_offset, ring-&gt;ring_size / 4);</div><div class='del'>-			ring-&gt;wptr = RREG32_SOC15_OFFSET(</div><div class='del'>-				JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='del'>-				reg_offset);</div><div class='add'>+			jpeg_v4_0_3_start_jrbc(ring);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void jpeg_v4_0_3_stop_inst(struct amdgpu_device *adev, int inst)</div><div class='add'>+{</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, inst);</div><div class='add'>+	/* reset JMI */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),</div><div class='add'>+		 UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='add'>+		 ~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+</div><div class='add'>+	jpeg_v4_0_3_enable_clock_gating(adev, inst);</div><div class='add'>+</div><div class='add'>+	/* enable anti hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+		 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,</div><div class='add'>+		 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_3_stop - stop JPEG block</div><div class='ctx'>  *</div><div class='hunk'>@@ -557,31 +658,10 @@ static int jpeg_v4_0_3_start(struct amdgpu_device *adev)</div><div class='ctx'>  */</div><div class='ctx'> static int jpeg_v4_0_3_stop(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	int i, jpeg_inst;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='del'>-		jpeg_inst = GET_INST(JPEG, i);</div><div class='del'>-		/* reset JMI */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),</div><div class='del'>-			 UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='del'>-			 ~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='del'>-</div><div class='del'>-		jpeg_v4_0_3_enable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* enable anti hang mechanism */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst,</div><div class='del'>-					  regUVD_JPEG_POWER_STATUS),</div><div class='del'>-			 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,</div><div class='del'>-			 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG,</div><div class='del'>-			     2 &lt;&lt; UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT);</div><div class='del'>-		SOC15_WAIT_ON_RREG(</div><div class='del'>-			JPEG, jpeg_inst, regUVD_PGFSM_STATUS,</div><div class='del'>-			UVD_PGFSM_STATUS__UVDJ_PWR_OFF</div><div class='del'>-				&lt;&lt; UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT,</div><div class='del'>-			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);</div><div class='del'>-	}</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i)</div><div class='add'>+		jpeg_v4_0_3_stop_inst(adev, i);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -597,9 +677,8 @@ static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	return RREG32_SOC15_OFFSET(</div><div class='del'>-		JPEG, GET_INST(JPEG, ring-&gt;me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,</div><div class='del'>-		ring-&gt;pipe ? (0x40 * ring-&gt;pipe - 0xc80) : 0);</div><div class='add'>+	return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me), regUVD_JRBC0_UVD_JRBC_RB_RPTR,</div><div class='add'>+				   jpeg_v4_0_3_core_reg_offset(ring-&gt;pipe));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -615,11 +694,16 @@ static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> </div><div class='ctx'> 	if (ring-&gt;use_doorbell)</div><div class='ctx'> 		return adev-&gt;wb.wb[ring-&gt;wptr_offs];</div><div class='del'>-	else</div><div class='del'>-		return RREG32_SOC15_OFFSET(</div><div class='del'>-			JPEG, GET_INST(JPEG, ring-&gt;me),</div><div class='del'>-			regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='del'>-			ring-&gt;pipe ? (0x40 * ring-&gt;pipe - 0xc80) : 0);</div><div class='add'>+</div><div class='add'>+	return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='add'>+				   jpeg_v4_0_3_core_reg_offset(ring-&gt;pipe));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* JPEG engine access for HDP flush doesn't work when RRMT is enabled.</div><div class='add'>+	 * This is a workaround to avoid any HDP flush through JPEG ring.</div><div class='add'>+	 */</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -637,10 +721,8 @@ static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 		adev-&gt;wb.wb[ring-&gt;wptr_offs] = lower_32_bits(ring-&gt;wptr);</div><div class='ctx'> 		WDOORBELL32(ring-&gt;doorbell_index, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 	} else {</div><div class='del'>-		WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me),</div><div class='del'>-				    regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='del'>-				    (ring-&gt;pipe ? (0x40 * ring-&gt;pipe - 0xc80) :</div><div class='del'>-						  0),</div><div class='add'>+		WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me), regUVD_JRBC0_UVD_JRBC_RB_WPTR,</div><div class='add'>+				    jpeg_v4_0_3_core_reg_offset(ring-&gt;pipe),</div><div class='ctx'> 				    lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -658,11 +740,12 @@ void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring)</div><div class='ctx'> 		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,</div><div class='ctx'> 			0, 0, PACKETJ_TYPE0));</div><div class='ctx'> 		amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,</div><div class='del'>-		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, 0x80004000);</div><div class='add'>+		amdgpu_ring_write(ring,</div><div class='add'>+				  PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,</div><div class='add'>+					  0, PACKETJ_TYPE0));</div><div class='add'>+		amdgpu_ring_write(ring, 0x80004000);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -678,11 +761,12 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring)</div><div class='ctx'> 		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,</div><div class='ctx'> 			0, 0, PACKETJ_TYPE0));</div><div class='ctx'> 		amdgpu_ring_write(ring, 0x62a04);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,</div><div class='del'>-		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, 0x00004000);</div><div class='add'>+		amdgpu_ring_write(ring,</div><div class='add'>+				  PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0,</div><div class='add'>+					  0, PACKETJ_TYPE0));</div><div class='add'>+		amdgpu_ring_write(ring, 0x00004000);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -724,31 +808,11 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq</div><div class='ctx'> 		0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0);</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;adev-&gt;jpeg.inst[ring-&gt;me].aid_id) {</div><div class='del'>-		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,</div><div class='del'>-			0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));</div><div class='del'>-		amdgpu_ring_write(ring, 0x4);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));</div><div class='del'>-		amdgpu_ring_write(ring, 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,</div><div class='del'>-		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, 0x3fbc);</div><div class='del'>-</div><div class='del'>-	if (ring-&gt;adev-&gt;jpeg.inst[ring-&gt;me].aid_id) {</div><div class='del'>-		amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,</div><div class='del'>-			0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));</div><div class='del'>-		amdgpu_ring_write(ring, 0x0);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));</div><div class='del'>-		amdgpu_ring_write(ring, 0);</div><div class='del'>-	}</div><div class='add'>+	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,</div><div class='del'>-		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, 0x1);</div><div class='add'>+	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0);</div><div class='hunk'>@@ -773,11 +837,15 @@ void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4)));</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;funcs-&gt;parse_cs)</div><div class='add'>+		amdgpu_ring_write(ring, 0);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4) | (vmid &lt;&lt; 8)));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='del'>-	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4)));</div><div class='add'>+	amdgpu_ring_write(ring, (vmid | (vmid &lt;&lt; 4) | (vmid &lt;&lt; 8)));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring,	PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='hunk'>@@ -818,7 +886,13 @@ void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='ctx'> void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,</div><div class='ctx'> 				uint32_t val, uint32_t mask)</div><div class='ctx'> {</div><div class='del'>-	uint32_t reg_offset = (reg &lt;&lt; 2);</div><div class='add'>+	uint32_t reg_offset;</div><div class='add'>+</div><div class='add'>+	/* Use normalized offsets if required */</div><div class='add'>+	if (jpeg_v4_0_3_normalizn_reqd(ring-&gt;adev))</div><div class='add'>+		reg = NORMALIZE_JPEG_REG_OFFSET(reg);</div><div class='add'>+</div><div class='add'>+	reg_offset = (reg &lt;&lt; 2);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='hunk'>@@ -859,7 +933,13 @@ void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> </div><div class='ctx'> void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)</div><div class='ctx'> {</div><div class='del'>-	uint32_t reg_offset = (reg &lt;&lt; 2);</div><div class='add'>+	uint32_t reg_offset;</div><div class='add'>+</div><div class='add'>+	/* Use normalized offsets if required */</div><div class='add'>+	if (jpeg_v4_0_3_normalizn_reqd(ring-&gt;adev))</div><div class='add'>+		reg = NORMALIZE_JPEG_REG_OFFSET(reg);</div><div class='add'>+</div><div class='add'>+	reg_offset = (reg &lt;&lt; 2);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring,	PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,</div><div class='ctx'> 		0, 0, PACKETJ_TYPE0));</div><div class='hunk'>@@ -887,21 +967,17 @@ void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v4_0_3_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='del'>-			unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);</div><div class='del'>-</div><div class='del'>-			ret &amp;= ((RREG32_SOC15_OFFSET(</div><div class='del'>-					 JPEG, GET_INST(JPEG, i),</div><div class='del'>-					 regUVD_JRBC0_UVD_JRBC_STATUS,</div><div class='del'>-					 reg_offset) &amp;</div><div class='del'>-				 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==</div><div class='add'>+			ret &amp;= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),</div><div class='add'>+				regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j)) &amp;</div><div class='add'>+				UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==</div><div class='ctx'> 				UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -909,36 +985,33 @@ static bool jpeg_v4_0_3_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_3_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='del'>-			unsigned int reg_offset = (j?(0x40 * j - 0xc80):0);</div><div class='del'>-</div><div class='del'>-			ret &amp;= SOC15_WAIT_ON_RREG_OFFSET(</div><div class='del'>-				JPEG, GET_INST(JPEG, i),</div><div class='del'>-				regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset,</div><div class='add'>+			ret &amp;= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),</div><div class='add'>+				regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j),</div><div class='ctx'> 				UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK,</div><div class='del'>-				UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='add'>+				UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK));</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_3_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		if (enable) {</div><div class='del'>-			if (!jpeg_v4_0_3_is_idle(handle))</div><div class='add'>+			if (!jpeg_v4_0_3_is_idle(ip_block))</div><div class='ctx'> 				return -EBUSY;</div><div class='ctx'> 			jpeg_v4_0_3_enable_clock_gating(adev, i);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -948,10 +1021,10 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_3_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='hunk'>@@ -981,6 +1054,14 @@ static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_irq_src *source,</div><div class='add'>+					unsigned int type,</div><div class='add'>+					enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 				      struct amdgpu_irq_src *source,</div><div class='ctx'> 				      struct amdgpu_iv_entry *entry)</div><div class='hunk'>@@ -1035,10 +1116,47 @@ static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void jpeg_v4_0_3_core_stall_reset(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, ring-&gt;me);</div><div class='add'>+	int reg_offset = jpeg_v4_0_3_core_reg_offset(ring-&gt;pipe);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_JMI_CLIENT_STALL,</div><div class='add'>+			    reg_offset, 0x1F);</div><div class='add'>+	SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+				  regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS,</div><div class='add'>+				  reg_offset, 0x1F, 0x1F);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_JPEG_LMI_DROP,</div><div class='add'>+			    reg_offset, 0x1F);</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 &lt;&lt; ring-&gt;pipe);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_JMI_CLIENT_STALL,</div><div class='add'>+			    reg_offset, 0x00);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_JPEG_LMI_DROP,</div><div class='add'>+			    reg_offset, 0x00);</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				  unsigned int vmid,</div><div class='add'>+				  struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_sriov_vf(ring-&gt;adev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	jpeg_v4_0_3_core_stall_reset(ring);</div><div class='add'>+	jpeg_v4_0_3_start_jrbc(ring);</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v4_0_3",</div><div class='ctx'> 	.early_init = jpeg_v4_0_3_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v4_0_3_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v4_0_3_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v4_0_3_hw_init,</div><div class='hunk'>@@ -1047,12 +1165,10 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v4_0_3_resume,</div><div class='ctx'> 	.is_idle = jpeg_v4_0_3_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v4_0_3_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v4_0_3_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -1061,16 +1177,18 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='ctx'> 		8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */</div><div class='del'>-		22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */</div><div class='add'>+		18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */</div><div class='ctx'> 		8 + 16,</div><div class='ctx'> 	.emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */</div><div class='ctx'> 	.emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,</div><div class='ctx'> 	.emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,</div><div class='ctx'> 	.emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = amdgpu_jpeg_dec_ring_test_ring,</div><div class='ctx'> 	.test_ib = amdgpu_jpeg_dec_ring_test_ib,</div><div class='ctx'> 	.insert_nop = jpeg_v4_0_3_dec_ring_nop,</div><div class='hunk'>@@ -1082,6 +1200,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v4_0_3_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1098,7 +1217,6 @@ static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;jpeg.inst[i].aid_id =</div><div class='ctx'> 			jpeg_inst / adev-&gt;jpeg.num_inst_per_aid;</div><div class='ctx'> 	}</div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "JPEG decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = {</div><div class='hunk'>@@ -1106,6 +1224,11 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = {</div><div class='ctx'> 	.process = jpeg_v4_0_3_process_interrupt,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_ras_irq_funcs = {</div><div class='add'>+	.set = jpeg_v4_0_3_set_ras_interrupt_state,</div><div class='add'>+	.process = amdgpu_jpeg_process_poison_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -1114,6 +1237,9 @@ static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;jpeg.inst-&gt;irq.num_types += adev-&gt;jpeg.num_jpeg_rings;</div><div class='ctx'> 	}</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;irq.funcs = &amp;jpeg_v4_0_3_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.inst-&gt;ras_poison_irq.num_types = 1;</div><div class='add'>+	adev-&gt;jpeg.inst-&gt;ras_poison_irq.funcs = &amp;jpeg_v4_0_3_ras_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = {</div><div class='hunk'>@@ -1210,14 +1336,147 @@ static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)</div><div class='ctx'> 		jpeg_v4_0_3_inst_reset_ras_error_count(adev, i);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev,</div><div class='add'>+		uint32_t instance, uint32_t sub_block)</div><div class='add'>+{</div><div class='add'>+	uint32_t poison_stat = 0, reg_value = 0;</div><div class='add'>+</div><div class='add'>+	switch (sub_block) {</div><div class='add'>+	case AMDGPU_JPEG_V4_0_3_JPEG0:</div><div class='add'>+		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);</div><div class='add'>+		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_JPEG_V4_0_3_JPEG1:</div><div class='add'>+		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);</div><div class='add'>+		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (poison_stat)</div><div class='add'>+		dev_info(adev-&gt;dev, "Poison detected in JPEG%d sub_block%d\n",</div><div class='add'>+			instance, sub_block);</div><div class='add'>+</div><div class='add'>+	return poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool jpeg_v4_0_3_query_ras_poison_status(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t inst = 0, sub = 0, poison_stat = 0;</div><div class='add'>+</div><div class='add'>+	for (inst = 0; inst &lt; adev-&gt;jpeg.num_jpeg_inst; inst++)</div><div class='add'>+		for (sub = 0; sub &lt; AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK; sub++)</div><div class='add'>+			poison_stat +=</div><div class='add'>+			jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub);</div><div class='add'>+</div><div class='add'>+	return !!poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = {</div><div class='ctx'> 	.query_ras_error_count = jpeg_v4_0_3_query_ras_error_count,</div><div class='ctx'> 	.reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count,</div><div class='add'>+	.query_poison_status = jpeg_v4_0_3_query_ras_poison_status,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				      enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE,</div><div class='add'>+						     1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* reference to smu driver if header file */</div><div class='add'>+static int jpeg_v4_0_3_err_codes[] = {</div><div class='add'>+	16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-7][S|D] */</div><div class='add'>+	24, 25, 26, 27, 28, 29, 30, 31</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+					 enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	u32 instlo;</div><div class='add'>+</div><div class='add'>+	instlo = ACA_REG__IPID__INSTANCEIDLO(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='add'>+</div><div class='add'>+	if (instlo != mmSMNAID_AID0_MCA_SMU)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (aca_bank_check_error_codes(handle-&gt;adev, bank,</div><div class='add'>+				       jpeg_v4_0_3_err_codes,</div><div class='add'>+				       ARRAY_SIZE(jpeg_v4_0_3_err_codes)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct aca_bank_ops jpeg_v4_0_3_aca_bank_ops = {</div><div class='add'>+	.aca_bank_parser = jpeg_v4_0_3_aca_bank_parser,</div><div class='add'>+	.aca_bank_is_valid = jpeg_v4_0_3_aca_bank_is_valid,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct aca_info jpeg_v4_0_3_aca_info = {</div><div class='add'>+	.hwip = ACA_HWIP_TYPE_SMU,</div><div class='add'>+	.mask = ACA_ERROR_UE_MASK,</div><div class='add'>+	.bank_ops = &amp;jpeg_v4_0_3_aca_bank_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_block_late_init(adev, ras_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, ras_block-&gt;block) &amp;&amp;</div><div class='add'>+		adev-&gt;jpeg.inst-&gt;ras_poison_irq.funcs) {</div><div class='add'>+		r = amdgpu_irq_get(adev, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+		if (r)</div><div class='add'>+			goto late_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG,</div><div class='add'>+				&amp;jpeg_v4_0_3_aca_info, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		goto late_fini;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+late_fini:</div><div class='add'>+	amdgpu_ras_block_late_fini(adev, ras_block);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = {</div><div class='ctx'> 	.ras_block = {</div><div class='ctx'> 		.hw_ops = &amp;jpeg_v4_0_3_ras_hw_ops,</div><div class='add'>+		.ras_late_init = jpeg_v4_0_3_ras_late_init,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h<br/>index 747a3e5f6856..2e110d04af84 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h</a></div><div class='hunk'>@@ -46,6 +46,13 @@</div><div class='ctx'> </div><div class='ctx'> #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000</div><div class='ctx'> </div><div class='add'>+enum amdgpu_jpeg_v4_0_3_sub_block {</div><div class='add'>+	AMDGPU_JPEG_V4_0_3_JPEG0 = 0,</div><div class='add'>+	AMDGPU_JPEG_V4_0_3_JPEG1,</div><div class='add'>+</div><div class='add'>+	AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;</div><div class='ctx'> </div><div class='ctx'> void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='hunk'>@@ -56,6 +63,7 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq</div><div class='ctx'> 				unsigned int flags);</div><div class='ctx'> void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> 					unsigned int vmid, uint64_t pd_addr);</div><div class='add'>+void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring);</div><div class='ctx'> void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);</div><div class='ctx'> void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring);</div><div class='ctx'> void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c<br/>index edf5bcdd2bc9..54fd9c800c40 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c</a></div><div class='hunk'>@@ -46,11 +46,26 @@</div><div class='ctx'> #define regJPEG_CGC_GATE_INTERNAL_OFFSET		0x4160</div><div class='ctx'> #define regUVD_NO_OP_INTERNAL_OFFSET			0x0029</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_5[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v4_0_5_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='del'>-</div><div class='ctx'> static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_ih_clientid_jpeg[] = {</div><div class='hunk'>@@ -58,16 +73,18 @@ static int amdgpu_ih_clientid_jpeg[] = {</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_early_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 0, 5):</div><div class='hunk'>@@ -94,13 +111,13 @@ static int jpeg_v4_0_5_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_sw_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='ctx'> </div><div class='hunk'>@@ -153,25 +170,38 @@ static int jpeg_v4_0_5_sw_init(void *handle)</div><div class='ctx'> 		adev-&gt;jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_5, ARRAY_SIZE(jpeg_reg_list_4_0_5));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;jpeg.inst[0].ring_dec[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -180,18 +210,17 @@ static int jpeg_v4_0_5_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_hw_init(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	int r, i;</div><div class='add'>+	int i, r = 0;</div><div class='ctx'> </div><div class='ctx'> 	// TODO: Enable ring test with DPG support</div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_JPEG_DPG) {</div><div class='del'>-		DRM_DEV_INFO(adev-&gt;dev, "JPEG decode initialized successfully under DPG Mode");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -205,25 +234,22 @@ static int jpeg_v4_0_5_hw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("JPEG decode initialized successfully under SPG Mode\n");</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;jpeg.harvest_config &amp; (1 &lt;&lt; i))</div><div class='hunk'>@@ -232,7 +258,7 @@ static int jpeg_v4_0_5_hw_fini(void *handle)</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 			    RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))</div><div class='del'>-				jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+				jpeg_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -241,20 +267,19 @@ static int jpeg_v4_0_5_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_suspend(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v4_0_5_hw_fini(adev);</div><div class='add'>+	r = jpeg_v4_0_5_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -262,20 +287,19 @@ static int jpeg_v4_0_5_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v4_0_5_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v4_0_5_resume(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v4_0_5_hw_init(adev);</div><div class='add'>+	r = jpeg_v4_0_5_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -625,9 +649,9 @@ static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v4_0_5_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='hunk'>@@ -641,9 +665,9 @@ static bool jpeg_v4_0_5_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_5_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='hunk'>@@ -658,11 +682,11 @@ static int jpeg_v4_0_5_wait_for_idle(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_5_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='hunk'>@@ -670,7 +694,7 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (enable) {</div><div class='del'>-			if (!jpeg_v4_0_5_is_idle(handle))</div><div class='add'>+			if (!jpeg_v4_0_5_is_idle(ip_block))</div><div class='ctx'> 				return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 			jpeg_v4_0_5_enable_clock_gating(adev, i);</div><div class='hunk'>@@ -682,10 +706,10 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v4_0_5_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='hunk'>@@ -744,10 +768,25 @@ static int jpeg_v4_0_5_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v4_0_5_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				  unsigned int vmid,</div><div class='add'>+				  struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = jpeg_v4_0_5_stop(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = jpeg_v4_0_5_start(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v4_0_5",</div><div class='ctx'> 	.early_init = jpeg_v4_0_5_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v4_0_5_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v4_0_5_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v4_0_5_hw_init,</div><div class='hunk'>@@ -756,12 +795,10 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v4_0_5_resume,</div><div class='ctx'> 	.is_idle = jpeg_v4_0_5_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v4_0_5_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v4_0_5_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -770,6 +807,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -791,6 +829,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v4_0_5_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -803,7 +842,6 @@ static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;jpeg.inst[i].ring_dec-&gt;funcs = &amp;jpeg_v4_0_5_dec_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;jpeg.inst[i].ring_dec-&gt;me = i;</div><div class='del'>-		DRM_DEV_INFO(adev-&gt;dev, "JPEG%d decode is enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c<br/>index e70200f97555..46bf15dce2bd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c</a></div><div class='hunk'>@@ -26,27 +26,45 @@</div><div class='ctx'> #include "amdgpu_pm.h"</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "soc15d.h"</div><div class='add'>+#include "jpeg_v2_0.h"</div><div class='ctx'> #include "jpeg_v4_0_3.h"</div><div class='ctx'> </div><div class='ctx'> #include "vcn/vcn_5_0_0_offset.h"</div><div class='ctx'> #include "vcn/vcn_5_0_0_sh_mask.h"</div><div class='del'>-#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"</div><div class='add'>+#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"</div><div class='add'>+#include "jpeg_v5_0_0.h"</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int jpeg_v5_0_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_powergating_state state);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_early_init(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_inst = 1;</div><div class='ctx'> 	adev-&gt;jpeg.num_jpeg_rings = 1;</div><div class='hunk'>@@ -60,19 +78,19 @@ static int jpeg_v5_0_0_early_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_sw_init - sw init for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_sw_init(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	/* JPEG TRAP */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='del'>-		VCN_4_0__SRCID__JPEG_DECODE, &amp;adev-&gt;jpeg.inst-&gt;irq);</div><div class='add'>+		VCN_5_0__SRCID__JPEG_DECODE, &amp;adev-&gt;jpeg.inst-&gt;irq);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -98,25 +116,36 @@ static int jpeg_v5_0_0_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0, ARRAY_SIZE(jpeg_reg_list_5_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;jpeg.inst[0].ring_dec[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_sw_fini - sw fini for JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * JPEG suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_sw_fini(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_jpeg_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	r = amdgpu_jpeg_sw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -125,47 +154,45 @@ static int jpeg_v5_0_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_hw_init - start and test JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_hw_init(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;jpeg.inst-&gt;ring_dec;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='ctx'> 			(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1), 0);</div><div class='ctx'> </div><div class='del'>-	WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,</div><div class='del'>-			ring-&gt;doorbell_index &lt;&lt; VCN_JPEG_DB_CTRL__OFFSET__SHIFT |</div><div class='del'>-			VCN_JPEG_DB_CTRL__EN_MASK);</div><div class='add'>+	/* Skip ring test because pause DPG is not implemented. */</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_JPEG_DPG)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "JPEG decode initialized successfully.\n");</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the JPEG block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_hw_fini(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 	      RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))</div><div class='del'>-		jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+		jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -173,20 +200,19 @@ static int jpeg_v5_0_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_suspend - suspend JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_suspend(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v5_0_0_hw_fini(adev);</div><div class='add'>+	r = jpeg_v5_0_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	r = amdgpu_jpeg_suspend(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -194,20 +220,19 @@ static int jpeg_v5_0_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_resume - resume JPEG block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init JPEG block</div><div class='ctx'>  */</div><div class='del'>-static int jpeg_v5_0_0_resume(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	r = amdgpu_jpeg_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v5_0_0_hw_init(adev);</div><div class='add'>+	r = jpeg_v5_0_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -241,7 +266,7 @@ static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev)</div><div class='add'>+static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -254,14 +279,10 @@ static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,</div><div class='ctx'> 		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='ctx'> </div><div class='del'>-	/* keep the JPEG in static PG mode */</div><div class='del'>-	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,</div><div class='del'>-		~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev)</div><div class='add'>+static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	/* enable anti hang mechanism */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),</div><div class='hunk'>@@ -279,6 +300,121 @@ static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev,</div><div class='add'>+	       int inst_idx, uint8_t indirect)</div><div class='add'>+{</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+</div><div class='add'>+	// JPEG disable CGC</div><div class='add'>+	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_JPEG_MGCG)</div><div class='add'>+		data = 1 &lt;&lt; JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='add'>+	else</div><div class='add'>+		data = 0 &lt;&lt; JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='add'>+</div><div class='add'>+	data |= 1 &lt;&lt; JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;</div><div class='add'>+	data |= 4 &lt;&lt; JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;</div><div class='add'>+</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);</div><div class='add'>+</div><div class='add'>+		// Turn on All JPEG clocks</div><div class='add'>+		data = 0;</div><div class='add'>+		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);</div><div class='add'>+</div><div class='add'>+		// Turn on All JPEG clocks</div><div class='add'>+		data = 0;</div><div class='add'>+		WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @inst_idx: instance number index</div><div class='add'>+ * @indirect: indirectly write sram</div><div class='add'>+ *</div><div class='add'>+ * Start JPEG block with dpg mode</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring = adev-&gt;jpeg.inst[inst_idx].ring_dec;</div><div class='add'>+	uint32_t reg_data = 0;</div><div class='add'>+</div><div class='add'>+	jpeg_v5_0_0_enable_power_gating(adev);</div><div class='add'>+</div><div class='add'>+	// enable dynamic power gating mode</div><div class='add'>+	reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);</div><div class='add'>+	reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);</div><div class='add'>+</div><div class='add'>+	if (indirect)</div><div class='add'>+		adev-&gt;jpeg.inst[inst_idx].dpg_sram_curr_addr =</div><div class='add'>+			(uint32_t *)adev-&gt;jpeg.inst[inst_idx].dpg_sram_cpu_addr;</div><div class='add'>+</div><div class='add'>+	jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect);</div><div class='add'>+</div><div class='add'>+	/* MJPEG global tiling registers */</div><div class='add'>+	if (indirect)</div><div class='add'>+		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='add'>+			adev-&gt;gfx.config.gb_addr_config, indirect);</div><div class='add'>+	else</div><div class='add'>+		WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='add'>+			adev-&gt;gfx.config.gb_addr_config, 1);</div><div class='add'>+</div><div class='add'>+	/* enable System Interrupt for JRBC */</div><div class='add'>+	if (indirect)</div><div class='add'>+		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN,</div><div class='add'>+			JPEG_SYS_INT_EN__DJRBC0_MASK, indirect);</div><div class='add'>+	else</div><div class='add'>+		WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN,</div><div class='add'>+			JPEG_SYS_INT_EN__DJRBC0_MASK, 1);</div><div class='add'>+</div><div class='add'>+	if (indirect) {</div><div class='add'>+		/* add nop to workaround PSP size check */</div><div class='add'>+		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect);</div><div class='add'>+</div><div class='add'>+		amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,</div><div class='add'>+		ring-&gt;doorbell_index &lt;&lt; VCN_JPEG_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		VCN_JPEG_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0);</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='add'>+		lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,</div><div class='add'>+		upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L);</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @inst_idx: instance number index</div><div class='add'>+ *</div><div class='add'>+ * Stop JPEG block with dpg mode</div><div class='add'>+ */</div><div class='add'>+static void jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_data = 0;</div><div class='add'>+</div><div class='add'>+	reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);</div><div class='add'>+	reg_data &amp;= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;</div><div class='add'>+	WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * jpeg_v5_0_0_start - start JPEG block</div><div class='ctx'>  *</div><div class='hunk'>@@ -294,8 +430,13 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='ctx'> 		amdgpu_dpm_enable_jpeg(adev, true);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_JPEG_DPG) {</div><div class='add'>+		r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev-&gt;jpeg.indirect_sram);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* disable power gating */</div><div class='del'>-	r = jpeg_v5_0_0_disable_static_power_gating(adev);</div><div class='add'>+	r = jpeg_v5_0_0_disable_power_gating(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -306,7 +447,6 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='ctx'> 		adev-&gt;gfx.config.gb_addr_config);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	/* enable JMI channel */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,</div><div class='ctx'> 		~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='hunk'>@@ -316,6 +456,10 @@ static int jpeg_v5_0_0_start(struct amdgpu_device *adev)</div><div class='ctx'> 		JPEG_SYS_INT_EN__DJRBC0_MASK,</div><div class='ctx'> 		~JPEG_SYS_INT_EN__DJRBC0_MASK);</div><div class='ctx'> </div><div class='add'>+	WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,</div><div class='add'>+		ring-&gt;doorbell_index &lt;&lt; VCN_JPEG_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		VCN_JPEG_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='ctx'> 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);</div><div class='ctx'> 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));</div><div class='ctx'> 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='hunk'>@@ -342,17 +486,22 @@ static int jpeg_v5_0_0_stop(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	/* reset JMI */</div><div class='del'>-	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),</div><div class='del'>-		UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='del'>-		~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_JPEG_DPG) {</div><div class='add'>+		jpeg_v5_0_0_stop_dpg_mode(adev, 0);</div><div class='add'>+	} else {</div><div class='ctx'> </div><div class='del'>-	jpeg_v5_0_0_enable_clock_gating(adev);</div><div class='add'>+		/* reset JMI */</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),</div><div class='add'>+			UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='add'>+			~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='ctx'> </div><div class='del'>-	/* enable power gating */</div><div class='del'>-	r = jpeg_v5_0_0_enable_static_power_gating(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+		jpeg_v5_0_0_enable_clock_gating(adev);</div><div class='add'>+</div><div class='add'>+		/* enable power gating */</div><div class='add'>+		r = jpeg_v5_0_0_enable_power_gating(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='ctx'> 		amdgpu_dpm_enable_jpeg(adev, false);</div><div class='hunk'>@@ -410,9 +559,9 @@ static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool jpeg_v5_0_0_is_idle(void *handle)</div><div class='add'>+static bool jpeg_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	ret &amp;= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &amp;</div><div class='hunk'>@@ -422,23 +571,23 @@ static bool jpeg_v5_0_0_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v5_0_0_wait_for_idle(void *handle)</div><div class='add'>+static int jpeg_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,</div><div class='ctx'> 		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v5_0_0_set_clockgating_state(void *handle,</div><div class='add'>+static int jpeg_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='del'>-		if (!jpeg_v5_0_0_is_idle(handle))</div><div class='add'>+		if (!jpeg_v5_0_0_is_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 		jpeg_v5_0_0_enable_clock_gating(adev);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -448,10 +597,10 @@ static int jpeg_v5_0_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jpeg_v5_0_0_set_powergating_state(void *handle,</div><div class='add'>+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (state == adev-&gt;jpeg.cur_state)</div><div class='hunk'>@@ -483,7 +632,7 @@ static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	DRM_DEBUG("IH: JPEG TRAP\n");</div><div class='ctx'> </div><div class='ctx'> 	switch (entry-&gt;src_id) {</div><div class='del'>-	case VCN_4_0__SRCID__JPEG_DECODE:</div><div class='add'>+	case VCN_5_0__SRCID__JPEG_DECODE:</div><div class='ctx'> 		amdgpu_fence_process(adev-&gt;jpeg.inst-&gt;ring_dec);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -495,10 +644,25 @@ static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int jpeg_v5_0_0_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				  unsigned int vmid,</div><div class='add'>+				  struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = jpeg_v5_0_0_stop(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = jpeg_v5_0_0_start(ring-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {</div><div class='ctx'> 	.name = "jpeg_v5_0_0",</div><div class='ctx'> 	.early_init = jpeg_v5_0_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = jpeg_v5_0_0_sw_init,</div><div class='ctx'> 	.sw_fini = jpeg_v5_0_0_sw_fini,</div><div class='ctx'> 	.hw_init = jpeg_v5_0_0_hw_init,</div><div class='hunk'>@@ -507,12 +671,10 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {</div><div class='ctx'> 	.resume = jpeg_v5_0_0_resume,</div><div class='ctx'> 	.is_idle = jpeg_v5_0_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = jpeg_v5_0_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = jpeg_v5_0_0_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -521,6 +683,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='hunk'>@@ -542,12 +705,12 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v5_0_0_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;jpeg.inst-&gt;ring_dec-&gt;funcs = &amp;jpeg_v5_0_0_dec_ring_vm_funcs;</div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "JPEG decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h<br/>index bd348336b215..5abb96159814 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h</a></div><div class='hunk'>@@ -24,6 +24,12 @@</div><div class='ctx'> #ifndef __JPEG_V5_0_0_H__</div><div class='ctx'> #define __JPEG_V5_0_0_H__</div><div class='ctx'> </div><div class='add'>+#define vcnipJPEG_CGC_GATE                                 0x4160</div><div class='add'>+#define vcnipJPEG_CGC_CTRL                                 0x4161</div><div class='add'>+#define vcnipJPEG_SYS_INT_EN                               0x4141</div><div class='add'>+#define vcnipUVD_NO_OP                                     0x0029</div><div class='add'>+#define vcnipJPEG_DEC_GFX10_ADDR_CONFIG                    0x404A</div><div class='add'>+</div><div class='ctx'> extern const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block;</div><div class='ctx'> </div><div class='ctx'> #endif /* __JPEG_V5_0_0_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c<br/>new file mode 100644<br/>index 000000000000..ab0bf880d3d8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c</a></div><div class='hunk'>@@ -0,0 +1,1101 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2014-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_jpeg.h"</div><div class='add'>+#include "amdgpu_pm.h"</div><div class='add'>+#include "soc15.h"</div><div class='add'>+#include "soc15d.h"</div><div class='add'>+#include "jpeg_v4_0_3.h"</div><div class='add'>+#include "jpeg_v5_0_1.h"</div><div class='add'>+#include "mmsch_v5_0.h"</div><div class='add'>+</div><div class='add'>+#include "vcn/vcn_5_0_0_offset.h"</div><div class='add'>+#include "vcn/vcn_5_0_0_sh_mask.h"</div><div class='add'>+#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_start_sriov(struct amdgpu_device *adev);</div><div class='add'>+static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					     enum amd_powergating_state state);</div><div class='add'>+static void jpeg_v5_0_1_set_ras_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='add'>+</div><div class='add'>+static int amdgpu_ih_srcid_jpeg[] = {</div><div class='add'>+	VCN_5_0__SRCID__JPEG_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG1_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG2_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG3_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG4_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG5_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG6_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG7_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG8_DECODE,</div><div class='add'>+	VCN_5_0__SRCID__JPEG9_DECODE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_core_reg_offset(u32 pipe)</div><div class='add'>+{</div><div class='add'>+	if (pipe &lt;= AMDGPU_MAX_JPEG_RINGS_4_0_3)</div><div class='add'>+		return ((0x40 * pipe) - 0xc80);</div><div class='add'>+	else</div><div class='add'>+		return ((0x40 * pipe) - 0x440);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_early_init - set function pointers</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Set ring and irq function pointers</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;jpeg.num_jpeg_inst || adev-&gt;jpeg.num_jpeg_inst &gt; AMDGPU_MAX_JPEG_INSTANCES)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS;</div><div class='add'>+	jpeg_v5_0_1_set_dec_ring_funcs(adev);</div><div class='add'>+	jpeg_v5_0_1_set_irq_funcs(adev);</div><div class='add'>+	jpeg_v5_0_1_set_ras_funcs(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_sw_init - sw init for JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Load firmware and sw initialization</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i, j, r, jpeg_inst;</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+		/* JPEG TRAP */</div><div class='add'>+		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+				      amdgpu_ih_srcid_jpeg[j], &amp;adev-&gt;jpeg.inst-&gt;irq);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+	/* JPEG DJPEG POISON EVENT */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+			VCN_5_0__SRCID_DJPEG0_POISON, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* JPEG EJPEG POISON EVENT */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+			VCN_5_0__SRCID_EJPEG0_POISON, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_sw_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		jpeg_inst = GET_INST(JPEG, i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+			ring-&gt;use_doorbell = true;</div><div class='add'>+			ring-&gt;vm_hub = AMDGPU_MMHUB0(adev-&gt;jpeg.inst[i].aid_id);</div><div class='add'>+			if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+				ring-&gt;doorbell_index =</div><div class='add'>+					(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='add'>+					1 + j + 11 * jpeg_inst;</div><div class='add'>+			} else {</div><div class='add'>+				ring-&gt;doorbell_index =</div><div class='add'>+					(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='add'>+					2 + j + 32 * jpeg_inst;</div><div class='add'>+			}</div><div class='add'>+			sprintf(ring-&gt;name, "jpeg_dec_%d.%d", adev-&gt;jpeg.inst[i].aid_id, j);</div><div class='add'>+			r = amdgpu_ring_init(adev, ring, 512, &amp;adev-&gt;jpeg.inst-&gt;irq, 0,</div><div class='add'>+					     AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+</div><div class='add'>+			adev-&gt;jpeg.internal.jpeg_pitch[j] =</div><div class='add'>+				regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;</div><div class='add'>+			adev-&gt;jpeg.inst[i].external.jpeg_pitch[j] =</div><div class='add'>+				SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0,</div><div class='add'>+						  (j ? jpeg_v5_0_1_core_reg_offset(j) : 0));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {</div><div class='add'>+		r = amdgpu_jpeg_ras_sw_init(adev);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to initialize jpeg ras block!\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;jpeg.inst[0].ring_dec[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+	r = amdgpu_jpeg_sysfs_reset_mask_init(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_sw_fini - sw fini for JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * JPEG suspend and free up sw allocation</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	amdgpu_jpeg_sysfs_reset_mask_fini(adev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_sw_fini(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_hw_init - start and test JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i, j, r, jpeg_inst;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		r = jpeg_v5_0_1_start_sriov(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+				ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+				ring-&gt;wptr = 0;</div><div class='add'>+				ring-&gt;wptr_old = 0;</div><div class='add'>+				jpeg_v5_0_1_dec_ring_set_wptr(ring);</div><div class='add'>+				ring-&gt;sched.ready = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &amp; 0x100)</div><div class='add'>+		adev-&gt;jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		jpeg_inst = GET_INST(JPEG, i);</div><div class='add'>+		ring = adev-&gt;jpeg.inst[i].ring_dec;</div><div class='add'>+		if (ring-&gt;use_doorbell)</div><div class='add'>+			adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='add'>+				 (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + 11 * jpeg_inst,</div><div class='add'>+				 adev-&gt;jpeg.inst[i].aid_id);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+			if (ring-&gt;use_doorbell)</div><div class='add'>+				WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL,</div><div class='add'>+						    ring-&gt;pipe,</div><div class='add'>+						    ring-&gt;doorbell_index &lt;&lt;</div><div class='add'>+						    VCN_JPEG_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+						    VCN_JPEG_DB_CTRL__EN_MASK);</div><div class='add'>+			r = amdgpu_ring_test_helper(ring);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_hw_fini - stop the hardware block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Stop the JPEG block, mark ring as not ready any more</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;jpeg.idle_work);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		if (adev-&gt;jpeg.cur_state != AMD_PG_STATE_GATE)</div><div class='add'>+			ret = jpeg_v5_0_1_set_powergating_state(ip_block, AMD_PG_STATE_GATE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) &amp;&amp; !amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_suspend - suspend JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * HW fini and suspend JPEG block</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = jpeg_v5_0_1_hw_fini(ip_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_suspend(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_resume - resume JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Resume firmware and hw init JPEG block</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_jpeg_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = jpeg_v5_0_1_hw_init(ip_block);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_init_inst(struct amdgpu_device *adev, int i)</div><div class='add'>+{</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, i);</div><div class='add'>+</div><div class='add'>+	/* disable anti hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,</div><div class='add'>+		 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+	/* keep the JPEG in static PG mode */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,</div><div class='add'>+		 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);</div><div class='add'>+</div><div class='add'>+	/* MJPEG global tiling registers */</div><div class='add'>+	WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* enable JMI channel */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,</div><div class='add'>+		 ~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_deinit_inst(struct amdgpu_device *adev, int i)</div><div class='add'>+{</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, i);</div><div class='add'>+	/* reset JMI */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),</div><div class='add'>+		 UVD_JMI_CNTL__SOFT_RESET_MASK,</div><div class='add'>+		 ~UVD_JMI_CNTL__SOFT_RESET_MASK);</div><div class='add'>+</div><div class='add'>+	/* enable anti hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),</div><div class='add'>+		 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,</div><div class='add'>+		 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_init_jrbc(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 reg, data, mask;</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, ring-&gt;me);</div><div class='add'>+	int reg_offset = ring-&gt;pipe ? jpeg_v5_0_1_core_reg_offset(ring-&gt;pipe) : 0;</div><div class='add'>+</div><div class='add'>+	/* enable System Interrupt for JRBC */</div><div class='add'>+	reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN);</div><div class='add'>+	if (ring-&gt;pipe &lt; AMDGPU_MAX_JPEG_RINGS_4_0_3) {</div><div class='add'>+		data = JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; ring-&gt;pipe;</div><div class='add'>+		mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; ring-&gt;pipe);</div><div class='add'>+		WREG32_P(reg, data, mask);</div><div class='add'>+	} else {</div><div class='add'>+		data = JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; (ring-&gt;pipe+12);</div><div class='add'>+		mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK &lt;&lt; (ring-&gt;pipe+12));</div><div class='add'>+		WREG32_P(reg, data, mask);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_LMI_JRBC_RB_VMID,</div><div class='add'>+			    reg_offset, 0);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC_RB_CNTL,</div><div class='add'>+			    reg_offset,</div><div class='add'>+			    (0x00000001L | 0x00000002L));</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,</div><div class='add'>+			    reg_offset, lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,</div><div class='add'>+			    reg_offset, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC_RB_RPTR,</div><div class='add'>+			    reg_offset, 0);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC_RB_WPTR,</div><div class='add'>+			    reg_offset, 0);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC_RB_CNTL,</div><div class='add'>+			    reg_offset, 0x00000002L);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JRBC_RB_SIZE,</div><div class='add'>+			    reg_offset, ring-&gt;ring_size / 4);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR,</div><div class='add'>+					 reg_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_start_sriov(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	uint64_t ctx_addr;</div><div class='add'>+	uint32_t param, resp, expected;</div><div class='add'>+	uint32_t tmp, timeout;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_mm_table *table = &amp;adev-&gt;virt.mm_table;</div><div class='add'>+	uint32_t *table_loc;</div><div class='add'>+	uint32_t table_size;</div><div class='add'>+	uint32_t size, size_dw, item_offset;</div><div class='add'>+	uint32_t init_status;</div><div class='add'>+	int i, j, jpeg_inst;</div><div class='add'>+</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_write</div><div class='add'>+		direct_wt = { {0} };</div><div class='add'>+	struct mmsch_v5_0_cmd_end end = { {0} };</div><div class='add'>+	struct mmsch_v5_0_init_header header;</div><div class='add'>+</div><div class='add'>+	direct_wt.cmd_header.command_type =</div><div class='add'>+		MMSCH_COMMAND__DIRECT_REG_WRITE;</div><div class='add'>+	end.cmd_header.command_type =</div><div class='add'>+		MMSCH_COMMAND__END;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; i++) {</div><div class='add'>+		jpeg_inst = GET_INST(JPEG, i);</div><div class='add'>+</div><div class='add'>+		memset(&amp;header, 0, sizeof(struct mmsch_v5_0_init_header));</div><div class='add'>+		header.version = MMSCH_VERSION;</div><div class='add'>+		header.total_size = sizeof(struct mmsch_v5_0_init_header) &gt;&gt; 2;</div><div class='add'>+</div><div class='add'>+		table_loc = (uint32_t *)table-&gt;cpu_addr;</div><div class='add'>+		table_loc += header.total_size;</div><div class='add'>+</div><div class='add'>+		item_offset = header.total_size;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; j++) {</div><div class='add'>+			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+			table_size = 0;</div><div class='add'>+</div><div class='add'>+			tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW);</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+			tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH);</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+			tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC_RB_SIZE);</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(tmp, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+			if (j &lt; 5) {</div><div class='add'>+				header.mjpegdec0[j].table_offset = item_offset;</div><div class='add'>+				header.mjpegdec0[j].init_status = 0;</div><div class='add'>+				header.mjpegdec0[j].table_size = table_size;</div><div class='add'>+			} else {</div><div class='add'>+				header.mjpegdec1[j - 5].table_offset = item_offset;</div><div class='add'>+				header.mjpegdec1[j - 5].init_status = 0;</div><div class='add'>+				header.mjpegdec1[j - 5].table_size = table_size;</div><div class='add'>+			}</div><div class='add'>+			header.total_size += table_size;</div><div class='add'>+			item_offset += table_size;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_END();</div><div class='add'>+</div><div class='add'>+		/* send init table to MMSCH */</div><div class='add'>+		size = sizeof(struct mmsch_v5_0_init_header);</div><div class='add'>+		table_loc = (uint32_t *)table-&gt;cpu_addr;</div><div class='add'>+		memcpy((void *)table_loc, &amp;header, size);</div><div class='add'>+</div><div class='add'>+		ctx_addr = table-&gt;gpu_addr;</div><div class='add'>+		WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));</div><div class='add'>+		WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);</div><div class='add'>+		tmp &amp;= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;</div><div class='add'>+		tmp |= (0 &lt;&lt; MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);</div><div class='add'>+		WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp);</div><div class='add'>+</div><div class='add'>+		size = header.total_size;</div><div class='add'>+		WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0);</div><div class='add'>+</div><div class='add'>+		param = 0x00000001;</div><div class='add'>+		WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param);</div><div class='add'>+		tmp = 0;</div><div class='add'>+		timeout = 1000;</div><div class='add'>+		resp = 0;</div><div class='add'>+		expected = MMSCH_VF_MAILBOX_RESP__OK;</div><div class='add'>+		init_status =</div><div class='add'>+			((struct mmsch_v5_0_init_header *)(table_loc))-&gt;mjpegdec0[i].init_status;</div><div class='add'>+		while (resp != expected) {</div><div class='add'>+			resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);</div><div class='add'>+</div><div class='add'>+			if (resp != 0)</div><div class='add'>+				break;</div><div class='add'>+			udelay(10);</div><div class='add'>+			tmp = tmp + 10;</div><div class='add'>+			if (tmp &gt;= timeout) {</div><div class='add'>+				DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\</div><div class='add'>+					" waiting for regMMSCH_VF_MAILBOX_RESP "\</div><div class='add'>+					"(expected=0x%08x, readback=0x%08x)\n",</div><div class='add'>+					tmp, expected, resp);</div><div class='add'>+				return -EBUSY;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (resp != expected &amp;&amp; resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE &amp;&amp;</div><div class='add'>+				init_status != MMSCH_VF_ENGINE_STATUS__PASS)</div><div class='add'>+			DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n",</div><div class='add'>+					resp, init_status);</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_start - start JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Setup and start the JPEG block</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_start(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		jpeg_v5_0_1_init_inst(adev, i);</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			ring = &amp;adev-&gt;jpeg.inst[i].ring_dec[j];</div><div class='add'>+			jpeg_v5_0_1_init_jrbc(ring);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_stop - stop JPEG block</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * stop the JPEG block</div><div class='add'>+ */</div><div class='add'>+static int jpeg_v5_0_1_stop(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i)</div><div class='add'>+		jpeg_v5_0_1_deinit_inst(adev, i);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_dec_ring_get_rptr - get read pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the current hardware read pointer</div><div class='add'>+ */</div><div class='add'>+static uint64_t jpeg_v5_0_1_dec_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me), regUVD_JRBC_RB_RPTR,</div><div class='add'>+				   ring-&gt;pipe ? jpeg_v5_0_1_core_reg_offset(ring-&gt;pipe) : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_dec_ring_get_wptr - get write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the current hardware write pointer</div><div class='add'>+ */</div><div class='add'>+static uint64_t jpeg_v5_0_1_dec_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell)</div><div class='add'>+		return adev-&gt;wb.wb[ring-&gt;wptr_offs];</div><div class='add'>+</div><div class='add'>+	return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me), regUVD_JRBC_RB_WPTR,</div><div class='add'>+				   ring-&gt;pipe ? jpeg_v5_0_1_core_reg_offset(ring-&gt;pipe) : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * jpeg_v5_0_1_dec_ring_set_wptr - set write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Commits the write pointer to the hardware</div><div class='add'>+ */</div><div class='add'>+static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		adev-&gt;wb.wb[ring-&gt;wptr_offs] = lower_32_bits(ring-&gt;wptr);</div><div class='add'>+		WDOORBELL32(ring-&gt;doorbell_index, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring-&gt;me),</div><div class='add'>+				    regUVD_JRBC_RB_WPTR,</div><div class='add'>+				    (ring-&gt;pipe ? jpeg_v5_0_1_core_reg_offset(ring-&gt;pipe) : 0),</div><div class='add'>+				    lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool jpeg_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool ret = false;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);</div><div class='add'>+</div><div class='add'>+			ret &amp;= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i),</div><div class='add'>+				regUVD_JRBC_STATUS, reg_offset) &amp;</div><div class='add'>+				UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==</div><div class='add'>+				UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);</div><div class='add'>+</div><div class='add'>+			ret &amp;= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i),</div><div class='add'>+							 regUVD_JRBC_STATUS, reg_offset,</div><div class='add'>+							 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,</div><div class='add'>+							 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					     enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = state == AMD_CG_STATE_GATE;</div><div class='add'>+</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!enable)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		if (!jpeg_v5_0_1_is_idle(ip_block))</div><div class='add'>+			return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					     enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		adev-&gt;jpeg.cur_state = AMD_PG_STATE_UNGATE;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (state == adev-&gt;jpeg.cur_state)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (state == AMD_PG_STATE_GATE)</div><div class='add'>+		ret = jpeg_v5_0_1_stop(adev);</div><div class='add'>+	else</div><div class='add'>+		ret = jpeg_v5_0_1_start(adev);</div><div class='add'>+</div><div class='add'>+	if (!ret)</div><div class='add'>+		adev-&gt;jpeg.cur_state = state;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_set_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					   struct amdgpu_irq_src *source,</div><div class='add'>+					   unsigned int type,</div><div class='add'>+					   enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_set_ras_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_irq_src *source,</div><div class='add'>+					unsigned int type,</div><div class='add'>+					enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_process_interrupt(struct amdgpu_device *adev,</div><div class='add'>+					 struct amdgpu_irq_src *source,</div><div class='add'>+					 struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 i, inst;</div><div class='add'>+</div><div class='add'>+	i = node_id_to_phys_map[entry-&gt;node_id];</div><div class='add'>+	DRM_DEV_DEBUG(adev-&gt;dev, "IH: JPEG TRAP\n");</div><div class='add'>+</div><div class='add'>+	for (inst = 0; inst &lt; adev-&gt;jpeg.num_jpeg_inst; ++inst)</div><div class='add'>+		if (adev-&gt;jpeg.inst[inst].aid_id == i)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+	if (inst &gt;= adev-&gt;jpeg.num_jpeg_inst) {</div><div class='add'>+		dev_WARN_ONCE(adev-&gt;dev, 1,</div><div class='add'>+			      "Interrupt received for unknown JPEG instance %d",</div><div class='add'>+			      entry-&gt;node_id);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (entry-&gt;src_id) {</div><div class='add'>+	case VCN_5_0__SRCID__JPEG_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[0]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG1_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[1]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG2_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[2]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG3_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[3]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG4_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[4]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG5_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[5]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG6_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[6]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG7_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[7]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG8_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[8]);</div><div class='add'>+		break;</div><div class='add'>+	case VCN_5_0__SRCID__JPEG9_DECODE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;jpeg.inst[inst].ring_dec[9]);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DRM_DEV_ERROR(adev-&gt;dev, "Unhandled interrupt: %d %d\n",</div><div class='add'>+			      entry-&gt;src_id, entry-&gt;src_data[0]);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_core_stall_reset(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int jpeg_inst = GET_INST(JPEG, ring-&gt;me);</div><div class='add'>+	int reg_offset = ring-&gt;pipe ? jpeg_v5_0_1_core_reg_offset(ring-&gt;pipe) : 0;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_JMI_CLIENT_STALL,</div><div class='add'>+			    reg_offset, 0x1F);</div><div class='add'>+	SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+				  regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS,</div><div class='add'>+				  reg_offset, 0x1F, 0x1F);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_JPEG_LMI_DROP,</div><div class='add'>+			    reg_offset, 0x1F);</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 &lt;&lt; ring-&gt;pipe);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_UVD_JMI_CLIENT_STALL,</div><div class='add'>+			    reg_offset, 0x00);</div><div class='add'>+	WREG32_SOC15_OFFSET(JPEG, jpeg_inst,</div><div class='add'>+			    regUVD_JMI0_JPEG_LMI_DROP,</div><div class='add'>+			    reg_offset, 0x00);</div><div class='add'>+	WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				  unsigned int vmid,</div><div class='add'>+				  struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	jpeg_v5_0_1_core_stall_reset(ring);</div><div class='add'>+	jpeg_v5_0_1_init_jrbc(ring);</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = {</div><div class='add'>+	.name = "jpeg_v5_0_1",</div><div class='add'>+	.early_init = jpeg_v5_0_1_early_init,</div><div class='add'>+	.late_init = NULL,</div><div class='add'>+	.sw_init = jpeg_v5_0_1_sw_init,</div><div class='add'>+	.sw_fini = jpeg_v5_0_1_sw_fini,</div><div class='add'>+	.hw_init = jpeg_v5_0_1_hw_init,</div><div class='add'>+	.hw_fini = jpeg_v5_0_1_hw_fini,</div><div class='add'>+	.suspend = jpeg_v5_0_1_suspend,</div><div class='add'>+	.resume = jpeg_v5_0_1_resume,</div><div class='add'>+	.is_idle = jpeg_v5_0_1_is_idle,</div><div class='add'>+	.wait_for_idle = jpeg_v5_0_1_wait_for_idle,</div><div class='add'>+	.check_soft_reset = NULL,</div><div class='add'>+	.pre_soft_reset = NULL,</div><div class='add'>+	.soft_reset = NULL,</div><div class='add'>+	.post_soft_reset = NULL,</div><div class='add'>+	.set_clockgating_state = jpeg_v5_0_1_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = jpeg_v5_0_1_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_jpeg_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_jpeg_print_ip_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_VCN_JPEG,</div><div class='add'>+	.align_mask = 0xf,</div><div class='add'>+	.get_rptr = jpeg_v5_0_1_dec_ring_get_rptr,</div><div class='add'>+	.get_wptr = jpeg_v5_0_1_dec_ring_get_wptr,</div><div class='add'>+	.set_wptr = jpeg_v5_0_1_dec_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_jpeg_dec_parse_cs,</div><div class='add'>+	.emit_frame_size =</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +</div><div class='add'>+		8 + /* jpeg_v5_0_1_dec_ring_emit_vm_flush */</div><div class='add'>+		22 + 22 + /* jpeg_v5_0_1_dec_ring_emit_fence x2 vm fence */</div><div class='add'>+		8 + 16,</div><div class='add'>+	.emit_ib_size = 22, /* jpeg_v5_0_1_dec_ring_emit_ib */</div><div class='add'>+	.emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,</div><div class='add'>+	.emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,</div><div class='add'>+	.emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush,</div><div class='add'>+	.test_ring = amdgpu_jpeg_dec_ring_test_ring,</div><div class='add'>+	.test_ib = amdgpu_jpeg_dec_ring_test_ib,</div><div class='add'>+	.insert_nop = jpeg_v4_0_3_dec_ring_nop,</div><div class='add'>+	.insert_start = jpeg_v4_0_3_dec_ring_insert_start,</div><div class='add'>+	.insert_end = jpeg_v4_0_3_dec_ring_insert_end,</div><div class='add'>+	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='add'>+	.begin_use = amdgpu_jpeg_ring_begin_use,</div><div class='add'>+	.end_use = amdgpu_jpeg_ring_end_use,</div><div class='add'>+	.emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,</div><div class='add'>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = jpeg_v5_0_1_ring_reset,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, j, jpeg_inst;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			adev-&gt;jpeg.inst[i].ring_dec[j].funcs = &amp;jpeg_v5_0_1_dec_ring_vm_funcs;</div><div class='add'>+			adev-&gt;jpeg.inst[i].ring_dec[j].me = i;</div><div class='add'>+			adev-&gt;jpeg.inst[i].ring_dec[j].pipe = j;</div><div class='add'>+		}</div><div class='add'>+		jpeg_inst = GET_INST(JPEG, i);</div><div class='add'>+		adev-&gt;jpeg.inst[i].aid_id =</div><div class='add'>+			jpeg_inst / adev-&gt;jpeg.num_inst_per_aid;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_irq_funcs = {</div><div class='add'>+	.set = jpeg_v5_0_1_set_interrupt_state,</div><div class='add'>+	.process = jpeg_v5_0_1_process_interrupt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_ras_irq_funcs = {</div><div class='add'>+	.set = jpeg_v5_0_1_set_ras_interrupt_state,</div><div class='add'>+	.process = amdgpu_jpeg_process_poison_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i)</div><div class='add'>+		adev-&gt;jpeg.inst-&gt;irq.num_types += adev-&gt;jpeg.num_jpeg_rings;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.inst-&gt;irq.funcs = &amp;jpeg_v5_0_1_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;jpeg.inst-&gt;ras_poison_irq.num_types = 1;</div><div class='add'>+	adev-&gt;jpeg.inst-&gt;ras_poison_irq.funcs = &amp;jpeg_v5_0_1_ras_irq_funcs;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_JPEG,</div><div class='add'>+	.major = 5,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 1,</div><div class='add'>+	.funcs = &amp;jpeg_v5_0_1_ip_funcs,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static uint32_t jpeg_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev,</div><div class='add'>+		uint32_t instance, uint32_t sub_block)</div><div class='add'>+{</div><div class='add'>+	uint32_t poison_stat = 0, reg_value = 0;</div><div class='add'>+</div><div class='add'>+	switch (sub_block) {</div><div class='add'>+	case AMDGPU_JPEG_V5_0_1_JPEG0:</div><div class='add'>+		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);</div><div class='add'>+		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_JPEG_V5_0_1_JPEG1:</div><div class='add'>+		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);</div><div class='add'>+		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (poison_stat)</div><div class='add'>+		dev_info(adev-&gt;dev, "Poison detected in JPEG%d sub_block%d\n",</div><div class='add'>+			instance, sub_block);</div><div class='add'>+</div><div class='add'>+	return poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool jpeg_v5_0_1_query_ras_poison_status(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t inst = 0, sub = 0, poison_stat = 0;</div><div class='add'>+</div><div class='add'>+	for (inst = 0; inst &lt; adev-&gt;jpeg.num_jpeg_inst; inst++)</div><div class='add'>+		for (sub = 0; sub &lt; AMDGPU_JPEG_V5_0_1_MAX_SUB_BLOCK; sub++)</div><div class='add'>+			poison_stat +=</div><div class='add'>+			jpeg_v5_0_1_query_poison_by_instance(adev, inst, sub);</div><div class='add'>+</div><div class='add'>+	return !!poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ras_block_hw_ops jpeg_v5_0_1_ras_hw_ops = {</div><div class='add'>+	.query_poison_status = jpeg_v5_0_1_query_ras_poison_status,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				      enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE,</div><div class='add'>+						     1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* reference to smu driver if header file */</div><div class='add'>+static int jpeg_v5_0_1_err_codes[] = {</div><div class='add'>+	16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-9][S|D] */</div><div class='add'>+	24, 25, 26, 27, 28, 29, 30, 31,</div><div class='add'>+	48, 49, 50, 51,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool jpeg_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+					 enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	u32 instlo;</div><div class='add'>+</div><div class='add'>+	instlo = ACA_REG__IPID__INSTANCEIDLO(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='add'>+</div><div class='add'>+	if (instlo != mmSMNAID_AID0_MCA_SMU)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (aca_bank_check_error_codes(handle-&gt;adev, bank,</div><div class='add'>+				       jpeg_v5_0_1_err_codes,</div><div class='add'>+				       ARRAY_SIZE(jpeg_v5_0_1_err_codes)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct aca_bank_ops jpeg_v5_0_1_aca_bank_ops = {</div><div class='add'>+	.aca_bank_parser = jpeg_v5_0_1_aca_bank_parser,</div><div class='add'>+	.aca_bank_is_valid = jpeg_v5_0_1_aca_bank_is_valid,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct aca_info jpeg_v5_0_1_aca_info = {</div><div class='add'>+	.hwip = ACA_HWIP_TYPE_SMU,</div><div class='add'>+	.mask = ACA_ERROR_UE_MASK,</div><div class='add'>+	.bank_ops = &amp;jpeg_v5_0_1_aca_bank_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_block_late_init(adev, ras_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG,</div><div class='add'>+				&amp;jpeg_v5_0_1_aca_info, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		goto late_fini;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, ras_block-&gt;block) &amp;&amp;</div><div class='add'>+		adev-&gt;jpeg.inst-&gt;ras_poison_irq.funcs) {</div><div class='add'>+		r = amdgpu_irq_get(adev, &amp;adev-&gt;jpeg.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+		if (r)</div><div class='add'>+			goto late_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+late_fini:</div><div class='add'>+	amdgpu_ras_block_late_fini(adev, ras_block);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct amdgpu_jpeg_ras jpeg_v5_0_1_ras = {</div><div class='add'>+	.ras_block = {</div><div class='add'>+		.hw_ops = &amp;jpeg_v5_0_1_ras_hw_ops,</div><div class='add'>+		.ras_late_init = jpeg_v5_0_1_ras_late_init,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void jpeg_v5_0_1_set_ras_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;jpeg.ras = &amp;jpeg_v5_0_1_ras;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h<br/>new file mode 100644<br/>index 000000000000..a7e58d5fb246<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __JPEG_V5_0_1_H__</div><div class='add'>+#define __JPEG_V5_0_1_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block;</div><div class='add'>+</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET			0x4094</div><div class='add'>+#define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET			0x1bffe</div><div class='add'>+</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_RB_WPTR                                                         0x0640</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX                                                1</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_STATUS                                                          0x0649</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX                                                 1</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_RB_RPTR                                                         0x064a</div><div class='add'>+#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX                                                1</div><div class='add'>+#define regUVD_JRBC1_UVD_JRBC_RB_WPTR                                                         0x0000</div><div class='add'>+#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC1_UVD_JRBC_STATUS                                                          0x0009</div><div class='add'>+#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC1_UVD_JRBC_RB_RPTR                                                         0x000a</div><div class='add'>+#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC2_UVD_JRBC_RB_WPTR                                                         0x0040</div><div class='add'>+#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC2_UVD_JRBC_STATUS                                                          0x0049</div><div class='add'>+#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC2_UVD_JRBC_RB_RPTR                                                         0x004a</div><div class='add'>+#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC3_UVD_JRBC_RB_WPTR                                                         0x0080</div><div class='add'>+#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC3_UVD_JRBC_STATUS                                                          0x0089</div><div class='add'>+#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC3_UVD_JRBC_RB_RPTR                                                         0x008a</div><div class='add'>+#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC4_UVD_JRBC_RB_WPTR                                                         0x00c0</div><div class='add'>+#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC4_UVD_JRBC_STATUS                                                          0x00c9</div><div class='add'>+#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC4_UVD_JRBC_RB_RPTR                                                         0x00ca</div><div class='add'>+#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC5_UVD_JRBC_RB_WPTR                                                         0x0100</div><div class='add'>+#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC5_UVD_JRBC_STATUS                                                          0x0109</div><div class='add'>+#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC5_UVD_JRBC_RB_RPTR                                                         0x010a</div><div class='add'>+#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC6_UVD_JRBC_RB_WPTR                                                         0x0140</div><div class='add'>+#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC6_UVD_JRBC_STATUS                                                          0x0149</div><div class='add'>+#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC6_UVD_JRBC_RB_RPTR                                                         0x014a</div><div class='add'>+#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC7_UVD_JRBC_RB_WPTR                                                         0x0180</div><div class='add'>+#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC7_UVD_JRBC_STATUS                                                          0x0189</div><div class='add'>+#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC7_UVD_JRBC_RB_RPTR                                                         0x018a</div><div class='add'>+#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC8_UVD_JRBC_RB_WPTR                                                         0x01c0</div><div class='add'>+#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC8_UVD_JRBC_STATUS                                                          0x01c9</div><div class='add'>+#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX                                                 0</div><div class='add'>+#define regUVD_JRBC8_UVD_JRBC_RB_RPTR                                                         0x01ca</div><div class='add'>+#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX                                                0</div><div class='add'>+#define regUVD_JRBC9_UVD_JRBC_RB_WPTR                                                         0x0440</div><div class='add'>+#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX                                                1</div><div class='add'>+#define regUVD_JRBC9_UVD_JRBC_STATUS                                                          0x0449</div><div class='add'>+#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX                                                 1</div><div class='add'>+#define regUVD_JRBC9_UVD_JRBC_RB_RPTR                                                         0x044a</div><div class='add'>+#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX                                                1</div><div class='add'>+#define regUVD_JMI0_JPEG_LMI_DROP                                                             0x0663</div><div class='add'>+#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX                                                    1</div><div class='add'>+#define regUVD_JMI0_UVD_JMI_CLIENT_STALL                                                      0x067a</div><div class='add'>+#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX                                             1</div><div class='add'>+#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS                                               0x067b</div><div class='add'>+#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX                                      1</div><div class='add'>+#define regJPEG_CORE_RST_CTRL                                                                 0x072e</div><div class='add'>+#define regJPEG_CORE_RST_CTRL_BASE_IDX                                                        1</div><div class='add'>+</div><div class='add'>+#define regVCN_RRMT_CNTL                          0x0940</div><div class='add'>+#define regVCN_RRMT_CNTL_BASE_IDX                 1</div><div class='add'>+</div><div class='add'>+enum amdgpu_jpeg_v5_0_1_sub_block {</div><div class='add'>+	AMDGPU_JPEG_V5_0_1_JPEG0 = 0,</div><div class='add'>+	AMDGPU_JPEG_V5_0_1_JPEG1,</div><div class='add'>+</div><div class='add'>+	AMDGPU_JPEG_V5_0_1_MAX_SUB_BLOCK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif /* __JPEG_V5_0_1_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c<br/>new file mode 100644<br/>index 000000000000..64cae89357b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mes_userqueue.c</a></div><div class='hunk'>@@ -0,0 +1,501 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_gfx.h"</div><div class='add'>+#include "mes_userqueue.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='add'>+</div><div class='add'>+#define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE</div><div class='add'>+#define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_reserve(bo, true);</div><div class='add'>+	if (ret) {</div><div class='add'>+		DRM_ERROR("Failed to reserve bo. ret %d\n", ret);</div><div class='add'>+		goto err_reserve_bo_failed;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_ttm_alloc_gart(&amp;bo-&gt;tbo);</div><div class='add'>+	if (ret) {</div><div class='add'>+		DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret);</div><div class='add'>+		goto err_map_bo_gart_failed;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(bo);</div><div class='add'>+	bo = amdgpu_bo_ref(bo);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_map_bo_gart_failed:</div><div class='add'>+	amdgpu_bo_unreserve(bo);</div><div class='add'>+err_reserve_bo_failed:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			      struct amdgpu_usermode_queue *queue,</div><div class='add'>+			      uint64_t wptr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo_va_mapping *wptr_mapping;</div><div class='add'>+	struct amdgpu_vm *wptr_vm;</div><div class='add'>+	struct amdgpu_userq_obj *wptr_obj = &amp;queue-&gt;wptr_obj;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	wptr_vm = queue-&gt;vm;</div><div class='add'>+	ret = amdgpu_bo_reserve(wptr_vm-&gt;root.bo, false);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	wptr &amp;= AMDGPU_GMC_HOLE_MASK;</div><div class='add'>+	wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr &gt;&gt; PAGE_SHIFT);</div><div class='add'>+	amdgpu_bo_unreserve(wptr_vm-&gt;root.bo);</div><div class='add'>+	if (!wptr_mapping) {</div><div class='add'>+		DRM_ERROR("Failed to lookup wptr bo\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wptr_obj-&gt;obj = wptr_mapping-&gt;bo_va-&gt;base.bo;</div><div class='add'>+	if (wptr_obj-&gt;obj-&gt;tbo.base.size &gt; PAGE_SIZE) {</div><div class='add'>+		DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mes_userq_map_gtt_bo_to_gart(wptr_obj-&gt;obj);</div><div class='add'>+	if (ret) {</div><div class='add'>+		DRM_ERROR("Failed to map wptr bo to GART\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue-&gt;wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj-&gt;obj);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int convert_to_mes_priority(int priority)</div><div class='add'>+{</div><div class='add'>+	switch (priority) {</div><div class='add'>+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW:</div><div class='add'>+	default:</div><div class='add'>+		return AMDGPU_MES_PRIORITY_LEVEL_NORMAL;</div><div class='add'>+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW:</div><div class='add'>+		return AMDGPU_MES_PRIORITY_LEVEL_LOW;</div><div class='add'>+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH:</div><div class='add'>+		return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM;</div><div class='add'>+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH:</div><div class='add'>+		return AMDGPU_MES_PRIORITY_LEVEL_HIGH;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			 struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct amdgpu_userq_obj *ctx = &amp;queue-&gt;fw_obj;</div><div class='add'>+	struct amdgpu_mqd_prop *userq_props = queue-&gt;userq_prop;</div><div class='add'>+	struct mes_add_queue_input queue_input;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	memset(&amp;queue_input, 0x0, sizeof(struct mes_add_queue_input));</div><div class='add'>+</div><div class='add'>+	queue_input.process_va_start = 0;</div><div class='add'>+	queue_input.process_va_end = adev-&gt;vm_manager.max_pfn - 1;</div><div class='add'>+</div><div class='add'>+	/* set process quantum to 10 ms and gang quantum to 1 ms as default */</div><div class='add'>+	queue_input.process_quantum = 100000;</div><div class='add'>+	queue_input.gang_quantum = 10000;</div><div class='add'>+	queue_input.paging = false;</div><div class='add'>+</div><div class='add'>+	queue_input.process_context_addr = ctx-&gt;gpu_addr;</div><div class='add'>+	queue_input.gang_context_addr = ctx-&gt;gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ;</div><div class='add'>+	queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;</div><div class='add'>+	queue_input.gang_global_priority_level = convert_to_mes_priority(queue-&gt;priority);</div><div class='add'>+</div><div class='add'>+	queue_input.process_id = queue-&gt;vm-&gt;pasid;</div><div class='add'>+	queue_input.queue_type = queue-&gt;queue_type;</div><div class='add'>+	queue_input.mqd_addr = queue-&gt;mqd.gpu_addr;</div><div class='add'>+	queue_input.wptr_addr = userq_props-&gt;wptr_gpu_addr;</div><div class='add'>+	queue_input.queue_size = userq_props-&gt;queue_size &gt;&gt; 2;</div><div class='add'>+	queue_input.doorbell_offset = userq_props-&gt;doorbell_index;</div><div class='add'>+	queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue-&gt;vm-&gt;root.bo);</div><div class='add'>+	queue_input.wptr_mc_addr = queue-&gt;wptr_obj.gpu_addr;</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;add_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to map queue in HW, err (%d)\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props-&gt;doorbell_index);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+			   struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct mes_remove_queue_input queue_input;</div><div class='add'>+	struct amdgpu_userq_obj *ctx = &amp;queue-&gt;fw_obj;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	memset(&amp;queue_input, 0x0, sizeof(struct mes_remove_queue_input));</div><div class='add'>+	queue_input.doorbell_offset = queue-&gt;doorbell_index;</div><div class='add'>+	queue_input.gang_context_addr = ctx-&gt;gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ;</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;remove_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r)</div><div class='add'>+		DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				      struct amdgpu_usermode_queue *queue,</div><div class='add'>+				      struct drm_amdgpu_userq_in *mqd_user)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_userq_obj *ctx = &amp;queue-&gt;fw_obj;</div><div class='add'>+	int r, size;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The FW expects at least one page space allocated for</div><div class='add'>+	 * process ctx and gang ctx each. Create an object</div><div class='add'>+	 * for the same.</div><div class='add'>+	 */</div><div class='add'>+	size = AMDGPU_USERQ_PROC_CTX_SZ + AMDGPU_USERQ_GANG_CTX_SZ;</div><div class='add'>+	r = amdgpu_userq_create_object(uq_mgr, ctx, size);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_detect_and_reset(struct amdgpu_device *adev,</div><div class='add'>+				      int queue_type)</div><div class='add'>+{</div><div class='add'>+	int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev);</div><div class='add'>+	struct mes_detect_and_reset_queue_input input;</div><div class='add'>+	struct amdgpu_usermode_queue *queue;</div><div class='add'>+	unsigned int hung_db_num = 0;</div><div class='add'>+	unsigned long queue_id;</div><div class='add'>+	u32 db_array[8];</div><div class='add'>+	bool found_hung_queue = false;</div><div class='add'>+	int r, i;</div><div class='add'>+</div><div class='add'>+	if (db_array_size &gt; 8) {</div><div class='add'>+		dev_err(adev-&gt;dev, "DB array size (%d vs 8) too small\n",</div><div class='add'>+			db_array_size);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(&amp;input, 0x0, sizeof(struct mes_detect_and_reset_queue_input));</div><div class='add'>+</div><div class='add'>+	input.queue_type = queue_type;</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false,</div><div class='add'>+						    &amp;hung_db_num, db_array);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to detect and reset queues, err (%d)\n", r);</div><div class='add'>+	} else if (hung_db_num) {</div><div class='add'>+		xa_for_each(&amp;adev-&gt;userq_doorbell_xa, queue_id, queue) {</div><div class='add'>+			if (queue-&gt;queue_type == queue_type) {</div><div class='add'>+				for (i = 0; i &lt; hung_db_num; i++) {</div><div class='add'>+					if (queue-&gt;doorbell_index == db_array[i]) {</div><div class='add'>+						queue-&gt;state = AMDGPU_USERQ_STATE_HUNG;</div><div class='add'>+						found_hung_queue = true;</div><div class='add'>+						atomic_inc(&amp;adev-&gt;gpu_reset_counter);</div><div class='add'>+						amdgpu_userq_fence_driver_force_completion(queue);</div><div class='add'>+						drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL);</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (found_hung_queue) {</div><div class='add'>+		/* Resume scheduling after hang recovery */</div><div class='add'>+		r = amdgpu_mes_resume(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				struct drm_amdgpu_userq_in *args_in,</div><div class='add'>+				struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct amdgpu_mqd *mqd_hw_default = &amp;adev-&gt;mqds[queue-&gt;queue_type];</div><div class='add'>+	struct drm_amdgpu_userq_in *mqd_user = args_in;</div><div class='add'>+	struct amdgpu_mqd_prop *userq_props;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/* Structure to initialize MQD for userqueue using generic MQD init function */</div><div class='add'>+	userq_props = kzalloc(sizeof(struct amdgpu_mqd_prop), GFP_KERNEL);</div><div class='add'>+	if (!userq_props) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for userq_props\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_userq_create_object(uq_mgr, &amp;queue-&gt;mqd, mqd_hw_default-&gt;mqd_size);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to create MQD object for userqueue\n");</div><div class='add'>+		goto free_props;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize the MQD BO with user given values */</div><div class='add'>+	userq_props-&gt;wptr_gpu_addr = mqd_user-&gt;wptr_va;</div><div class='add'>+	userq_props-&gt;rptr_gpu_addr = mqd_user-&gt;rptr_va;</div><div class='add'>+	userq_props-&gt;queue_size = mqd_user-&gt;queue_size;</div><div class='add'>+	userq_props-&gt;hqd_base_gpu_addr = mqd_user-&gt;queue_va;</div><div class='add'>+	userq_props-&gt;mqd_gpu_addr = queue-&gt;mqd.gpu_addr;</div><div class='add'>+	userq_props-&gt;use_doorbell = true;</div><div class='add'>+	userq_props-&gt;doorbell_index = queue-&gt;doorbell_index;</div><div class='add'>+	userq_props-&gt;fence_address = queue-&gt;fence_drv-&gt;gpu_addr;</div><div class='add'>+</div><div class='add'>+	if (queue-&gt;queue_type == AMDGPU_HW_IP_COMPUTE) {</div><div class='add'>+		struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd;</div><div class='add'>+</div><div class='add'>+		if (mqd_user-&gt;mqd_size != sizeof(*compute_mqd)) {</div><div class='add'>+			DRM_ERROR("Invalid compute IP MQD size\n");</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		compute_mqd = memdup_user(u64_to_user_ptr(mqd_user-&gt;mqd), mqd_user-&gt;mqd_size);</div><div class='add'>+		if (IS_ERR(compute_mqd)) {</div><div class='add'>+			DRM_ERROR("Failed to read user MQD\n");</div><div class='add'>+			r = -ENOMEM;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = amdgpu_userq_input_va_validate(queue, compute_mqd-&gt;eop_va,</div><div class='add'>+						   2048);</div><div class='add'>+		if (r)</div><div class='add'>+			goto free_mqd;</div><div class='add'>+</div><div class='add'>+		userq_props-&gt;eop_gpu_addr = compute_mqd-&gt;eop_va;</div><div class='add'>+		userq_props-&gt;hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;</div><div class='add'>+		userq_props-&gt;hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM;</div><div class='add'>+		userq_props-&gt;hqd_active = false;</div><div class='add'>+		userq_props-&gt;tmz_queue =</div><div class='add'>+			mqd_user-&gt;flags &amp; AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE;</div><div class='add'>+		kfree(compute_mqd);</div><div class='add'>+	} else if (queue-&gt;queue_type == AMDGPU_HW_IP_GFX) {</div><div class='add'>+		struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11;</div><div class='add'>+		struct amdgpu_gfx_shadow_info shadow_info;</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;gfx.funcs-&gt;get_gfx_shadow_info) {</div><div class='add'>+			adev-&gt;gfx.funcs-&gt;get_gfx_shadow_info(adev, &amp;shadow_info, true);</div><div class='add'>+		} else {</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (mqd_user-&gt;mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user-&gt;mqd) {</div><div class='add'>+			DRM_ERROR("Invalid GFX MQD\n");</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user-&gt;mqd), mqd_user-&gt;mqd_size);</div><div class='add'>+		if (IS_ERR(mqd_gfx_v11)) {</div><div class='add'>+			DRM_ERROR("Failed to read user MQD\n");</div><div class='add'>+			r = -ENOMEM;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		userq_props-&gt;shadow_addr = mqd_gfx_v11-&gt;shadow_va;</div><div class='add'>+		userq_props-&gt;csa_addr = mqd_gfx_v11-&gt;csa_va;</div><div class='add'>+		userq_props-&gt;tmz_queue =</div><div class='add'>+			mqd_user-&gt;flags &amp; AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11-&gt;shadow_va,</div><div class='add'>+						   shadow_info.shadow_size);</div><div class='add'>+		if (r)</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11-&gt;csa_va,</div><div class='add'>+						   shadow_info.csa_size);</div><div class='add'>+		if (r)</div><div class='add'>+			goto free_mqd;</div><div class='add'>+</div><div class='add'>+		kfree(mqd_gfx_v11);</div><div class='add'>+	} else if (queue-&gt;queue_type == AMDGPU_HW_IP_DMA) {</div><div class='add'>+		struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11;</div><div class='add'>+</div><div class='add'>+		if (mqd_user-&gt;mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user-&gt;mqd) {</div><div class='add'>+			DRM_ERROR("Invalid SDMA MQD\n");</div><div class='add'>+			r = -EINVAL;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user-&gt;mqd), mqd_user-&gt;mqd_size);</div><div class='add'>+		if (IS_ERR(mqd_sdma_v11)) {</div><div class='add'>+			DRM_ERROR("Failed to read sdma user MQD\n");</div><div class='add'>+			r = -ENOMEM;</div><div class='add'>+			goto free_mqd;</div><div class='add'>+		}</div><div class='add'>+		r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11-&gt;csa_va,</div><div class='add'>+						   32);</div><div class='add'>+		if (r)</div><div class='add'>+			goto free_mqd;</div><div class='add'>+</div><div class='add'>+		userq_props-&gt;csa_addr = mqd_sdma_v11-&gt;csa_va;</div><div class='add'>+		kfree(mqd_sdma_v11);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue-&gt;userq_prop = userq_props;</div><div class='add'>+</div><div class='add'>+	r = mqd_hw_default-&gt;init_mqd(adev, (void *)queue-&gt;mqd.cpu_ptr, userq_props);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to initialize MQD for userqueue\n");</div><div class='add'>+		goto free_mqd;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Create BO for FW operations */</div><div class='add'>+	r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to allocate BO for userqueue (%d)", r);</div><div class='add'>+		goto free_mqd;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* FW expects WPTR BOs to be mapped into GART */</div><div class='add'>+	r = mes_userq_create_wptr_mapping(uq_mgr, queue, userq_props-&gt;wptr_gpu_addr);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to create WPTR mapping\n");</div><div class='add'>+		goto free_ctx;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_ctx:</div><div class='add'>+	amdgpu_userq_destroy_object(uq_mgr, &amp;queue-&gt;fw_obj);</div><div class='add'>+</div><div class='add'>+free_mqd:</div><div class='add'>+	amdgpu_userq_destroy_object(uq_mgr, &amp;queue-&gt;mqd);</div><div class='add'>+</div><div class='add'>+free_props:</div><div class='add'>+	kfree(userq_props);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+		      struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	amdgpu_userq_destroy_object(uq_mgr, &amp;queue-&gt;fw_obj);</div><div class='add'>+	kfree(queue-&gt;userq_prop);</div><div class='add'>+	amdgpu_userq_destroy_object(uq_mgr, &amp;queue-&gt;mqd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_preempt(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct mes_suspend_gang_input queue_input;</div><div class='add'>+	struct amdgpu_userq_obj *ctx = &amp;queue-&gt;fw_obj;</div><div class='add'>+	signed long timeout = 2100000; /* 2100 ms */</div><div class='add'>+	u64 fence_gpu_addr;</div><div class='add'>+	u32 fence_offset;</div><div class='add'>+	u64 *fence_ptr;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (queue-&gt;state != AMDGPU_USERQ_STATE_MAPPED)</div><div class='add'>+		return 0;</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;fence_offset);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	fence_gpu_addr = adev-&gt;wb.gpu_addr + (fence_offset * 4);</div><div class='add'>+	fence_ptr = (u64 *)&amp;adev-&gt;wb.wb[fence_offset];</div><div class='add'>+	*fence_ptr = 0;</div><div class='add'>+</div><div class='add'>+	memset(&amp;queue_input, 0x0, sizeof(struct mes_suspend_gang_input));</div><div class='add'>+	queue_input.gang_context_addr = ctx-&gt;gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ;</div><div class='add'>+	queue_input.suspend_fence_addr = fence_gpu_addr;</div><div class='add'>+	queue_input.suspend_fence_value = 1;</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;suspend_gang(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to suspend gang: %d\n", r);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; timeout; i++) {</div><div class='add'>+		if (*fence_ptr == 1)</div><div class='add'>+			goto out;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+	r = -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	amdgpu_device_wb_free(adev, fence_offset);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_userq_restore(struct amdgpu_userq_mgr *uq_mgr,</div><div class='add'>+				struct amdgpu_usermode_queue *queue)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = uq_mgr-&gt;adev;</div><div class='add'>+	struct mes_resume_gang_input queue_input;</div><div class='add'>+	struct amdgpu_userq_obj *ctx = &amp;queue-&gt;fw_obj;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (queue-&gt;state == AMDGPU_USERQ_STATE_HUNG)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	if (queue-&gt;state != AMDGPU_USERQ_STATE_PREEMPTED)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	memset(&amp;queue_input, 0x0, sizeof(struct mes_resume_gang_input));</div><div class='add'>+	queue_input.gang_context_addr = ctx-&gt;gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ;</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;resume_gang(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	if (r)</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to resume queue, err (%d)\n", r);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_userq_funcs userq_mes_funcs = {</div><div class='add'>+	.mqd_create = mes_userq_mqd_create,</div><div class='add'>+	.mqd_destroy = mes_userq_mqd_destroy,</div><div class='add'>+	.unmap = mes_userq_unmap,</div><div class='add'>+	.map = mes_userq_map,</div><div class='add'>+	.detect_and_reset = mes_userq_detect_and_reset,</div><div class='add'>+	.preempt = mes_userq_preempt,</div><div class='add'>+	.restore = mes_userq_restore,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.h b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.h<br/>new file mode 100644<br/>index 000000000000..090ae8897770<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_userqueue.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mes_userqueue.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef MES_USERQ_H</div><div class='add'>+#define MES_USERQ_H</div><div class='add'>+#include "amdgpu_userq.h"</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_userq_funcs userq_mes_funcs;</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c<br/>deleted file mode 100644<br/>index 1e5ad1e08d2a..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v10_1.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,1187 +0,0 @@</div><div class='del'>-/*</div><div class='del'>- * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include &lt;linux/firmware.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include "amdgpu.h"</div><div class='del'>-#include "soc15_common.h"</div><div class='del'>-#include "nv.h"</div><div class='del'>-#include "gc/gc_10_1_0_offset.h"</div><div class='del'>-#include "gc/gc_10_1_0_sh_mask.h"</div><div class='del'>-#include "gc/gc_10_1_0_default.h"</div><div class='del'>-#include "v10_structs.h"</div><div class='del'>-#include "mes_api_def.h"</div><div class='del'>-</div><div class='del'>-#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid               0x2820</div><div class='del'>-#define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid_BASE_IDX      1</div><div class='del'>-#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1</div><div class='del'>-#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1</div><div class='del'>-</div><div class='del'>-MODULE_FIRMWARE("amdgpu/navi10_mes.bin");</div><div class='del'>-MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin");</div><div class='del'>-MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin");</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_hw_fini(void *handle);</div><div class='del'>-static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev);</div><div class='del'>-</div><div class='del'>-#define MES_EOP_SIZE   2048</div><div class='del'>-</div><div class='del'>-static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-</div><div class='del'>-	if (ring-&gt;use_doorbell) {</div><div class='del'>-		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='del'>-			     ring-&gt;wptr);</div><div class='del'>-		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='del'>-	} else {</div><div class='del'>-		BUG();</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	return *ring-&gt;rptr_cpu_addr;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	u64 wptr;</div><div class='del'>-</div><div class='del'>-	if (ring-&gt;use_doorbell)</div><div class='del'>-		wptr = atomic64_read((atomic64_t *)ring-&gt;wptr_cpu_addr);</div><div class='del'>-	else</div><div class='del'>-		BUG();</div><div class='del'>-	return wptr;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = {</div><div class='del'>-	.type = AMDGPU_RING_TYPE_MES,</div><div class='del'>-	.align_mask = 1,</div><div class='del'>-	.nop = 0,</div><div class='del'>-	.support_64bit_ptrs = true,</div><div class='del'>-	.get_rptr = mes_v10_1_ring_get_rptr,</div><div class='del'>-	.get_wptr = mes_v10_1_ring_get_wptr,</div><div class='del'>-	.set_wptr = mes_v10_1_ring_set_wptr,</div><div class='del'>-	.insert_nop = amdgpu_ring_insert_nop,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,</div><div class='del'>-						    void *pkt, int size,</div><div class='del'>-						    int api_status_off)</div><div class='del'>-{</div><div class='del'>-	int ndw = size / 4;</div><div class='del'>-	signed long r;</div><div class='del'>-	union MESAPI__ADD_QUEUE *x_pkt = pkt;</div><div class='del'>-	struct MES_API_STATUS *api_status;</div><div class='del'>-	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='del'>-	struct amdgpu_ring *ring = &amp;mes-&gt;ring;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	BUG_ON(size % 4 != 0);</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;mes-&gt;ring_lock, flags);</div><div class='del'>-	if (amdgpu_ring_alloc(ring, ndw)) {</div><div class='del'>-		spin_unlock_irqrestore(&amp;mes-&gt;ring_lock, flags);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);</div><div class='del'>-	api_status-&gt;api_completion_fence_addr = mes-&gt;ring.fence_drv.gpu_addr;</div><div class='del'>-	api_status-&gt;api_completion_fence_value = ++mes-&gt;ring.fence_drv.sync_seq;</div><div class='del'>-</div><div class='del'>-	amdgpu_ring_write_multiple(ring, pkt, ndw);</div><div class='del'>-	amdgpu_ring_commit(ring);</div><div class='del'>-	spin_unlock_irqrestore(&amp;mes-&gt;ring_lock, flags);</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG("MES msg=%d was emitted\n", x_pkt-&gt;header.opcode);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_fence_wait_polling(ring, ring-&gt;fence_drv.sync_seq,</div><div class='del'>-				      adev-&gt;usec_timeout);</div><div class='del'>-	if (r &lt; 1) {</div><div class='del'>-		DRM_ERROR("MES failed to response msg=%d\n",</div><div class='del'>-			  x_pkt-&gt;header.opcode);</div><div class='del'>-</div><div class='del'>-		while (halt_if_hws_hang)</div><div class='del'>-			schedule();</div><div class='del'>-</div><div class='del'>-		return -ETIMEDOUT;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int convert_to_mes_queue_type(int queue_type)</div><div class='del'>-{</div><div class='del'>-	if (queue_type == AMDGPU_RING_TYPE_GFX)</div><div class='del'>-		return MES_QUEUE_TYPE_GFX;</div><div class='del'>-	else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)</div><div class='del'>-		return MES_QUEUE_TYPE_COMPUTE;</div><div class='del'>-	else if (queue_type == AMDGPU_RING_TYPE_SDMA)</div><div class='del'>-		return MES_QUEUE_TYPE_SDMA;</div><div class='del'>-	else</div><div class='del'>-		BUG();</div><div class='del'>-	return -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,</div><div class='del'>-				  struct mes_add_queue_input *input)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='del'>-	union MESAPI__ADD_QUEUE mes_add_queue_pkt;</div><div class='del'>-	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='del'>-	uint32_t vm_cntx_cntl = hub-&gt;vm_cntx_cntl;</div><div class='del'>-</div><div class='del'>-	memset(&amp;mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));</div><div class='del'>-</div><div class='del'>-	mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='del'>-	mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;</div><div class='del'>-	mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='del'>-</div><div class='del'>-	mes_add_queue_pkt.process_id = input-&gt;process_id;</div><div class='del'>-	mes_add_queue_pkt.page_table_base_addr = input-&gt;page_table_base_addr;</div><div class='del'>-	mes_add_queue_pkt.process_va_start = input-&gt;process_va_start;</div><div class='del'>-	mes_add_queue_pkt.process_va_end = input-&gt;process_va_end;</div><div class='del'>-	mes_add_queue_pkt.process_quantum = input-&gt;process_quantum;</div><div class='del'>-	mes_add_queue_pkt.process_context_addr = input-&gt;process_context_addr;</div><div class='del'>-	mes_add_queue_pkt.gang_quantum = input-&gt;gang_quantum;</div><div class='del'>-	mes_add_queue_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='del'>-	mes_add_queue_pkt.inprocess_gang_priority =</div><div class='del'>-		input-&gt;inprocess_gang_priority;</div><div class='del'>-	mes_add_queue_pkt.gang_global_priority_level =</div><div class='del'>-		input-&gt;gang_global_priority_level;</div><div class='del'>-	mes_add_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='del'>-	mes_add_queue_pkt.mqd_addr = input-&gt;mqd_addr;</div><div class='del'>-	mes_add_queue_pkt.wptr_addr = input-&gt;wptr_addr;</div><div class='del'>-	mes_add_queue_pkt.queue_type =</div><div class='del'>-		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='del'>-	mes_add_queue_pkt.paging = input-&gt;paging;</div><div class='del'>-	mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;</div><div class='del'>-	mes_add_queue_pkt.gws_base = input-&gt;gws_base;</div><div class='del'>-	mes_add_queue_pkt.gws_size = input-&gt;gws_size;</div><div class='del'>-	mes_add_queue_pkt.trap_handler_addr = input-&gt;tba_addr;</div><div class='del'>-</div><div class='del'>-	return mes_v10_1_submit_pkt_and_poll_completion(mes,</div><div class='del'>-			&amp;mes_add_queue_pkt, sizeof(mes_add_queue_pkt),</div><div class='del'>-			offsetof(union MESAPI__ADD_QUEUE, api_status));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes,</div><div class='del'>-				     struct mes_remove_queue_input *input)</div><div class='del'>-{</div><div class='del'>-	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;</div><div class='del'>-</div><div class='del'>-	memset(&amp;mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));</div><div class='del'>-</div><div class='del'>-	mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='del'>-	mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;</div><div class='del'>-	mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='del'>-</div><div class='del'>-	mes_remove_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='del'>-	mes_remove_queue_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='del'>-</div><div class='del'>-	return mes_v10_1_submit_pkt_and_poll_completion(mes,</div><div class='del'>-			&amp;mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),</div><div class='del'>-			offsetof(union MESAPI__REMOVE_QUEUE, api_status));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_unmap_legacy_queue(struct amdgpu_mes *mes,</div><div class='del'>-				 struct mes_unmap_legacy_queue_input *input)</div><div class='del'>-{</div><div class='del'>-	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;</div><div class='del'>-</div><div class='del'>-	memset(&amp;mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));</div><div class='del'>-</div><div class='del'>-	mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='del'>-	mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;</div><div class='del'>-	mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='del'>-</div><div class='del'>-	mes_remove_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='del'>-	mes_remove_queue_pkt.gang_context_addr = 0;</div><div class='del'>-</div><div class='del'>-	mes_remove_queue_pkt.pipe_id = input-&gt;pipe_id;</div><div class='del'>-	mes_remove_queue_pkt.queue_id = input-&gt;queue_id;</div><div class='del'>-</div><div class='del'>-	if (input-&gt;action == PREEMPT_QUEUES_NO_UNMAP) {</div><div class='del'>-		mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;</div><div class='del'>-		mes_remove_queue_pkt.tf_addr = input-&gt;trail_fence_addr;</div><div class='del'>-		mes_remove_queue_pkt.tf_data =</div><div class='del'>-			lower_32_bits(input-&gt;trail_fence_data);</div><div class='del'>-	} else {</div><div class='del'>-		if (input-&gt;queue_type == AMDGPU_RING_TYPE_GFX)</div><div class='del'>-			mes_remove_queue_pkt.unmap_legacy_gfx_queue = 1;</div><div class='del'>-		else</div><div class='del'>-			mes_remove_queue_pkt.unmap_kiq_utility_queue = 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return mes_v10_1_submit_pkt_and_poll_completion(mes,</div><div class='del'>-			&amp;mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),</div><div class='del'>-			offsetof(union MESAPI__REMOVE_QUEUE, api_status));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes,</div><div class='del'>-				  struct mes_suspend_gang_input *input)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_resume_gang(struct amdgpu_mes *mes,</div><div class='del'>-				 struct mes_resume_gang_input *input)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes)</div><div class='del'>-{</div><div class='del'>-	union MESAPI__QUERY_MES_STATUS mes_status_pkt;</div><div class='del'>-</div><div class='del'>-	memset(&amp;mes_status_pkt, 0, sizeof(mes_status_pkt));</div><div class='del'>-</div><div class='del'>-	mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='del'>-	mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;</div><div class='del'>-	mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='del'>-</div><div class='del'>-	return mes_v10_1_submit_pkt_and_poll_completion(mes,</div><div class='del'>-			&amp;mes_status_pkt, sizeof(mes_status_pkt),</div><div class='del'>-			offsetof(union MESAPI__QUERY_MES_STATUS, api_status));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='del'>-	union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;</div><div class='del'>-</div><div class='del'>-	memset(&amp;mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));</div><div class='del'>-</div><div class='del'>-	mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='del'>-	mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;</div><div class='del'>-	mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='del'>-</div><div class='del'>-	mes_set_hw_res_pkt.vmid_mask_mmhub = mes-&gt;vmid_mask_mmhub;</div><div class='del'>-	mes_set_hw_res_pkt.vmid_mask_gfxhub = mes-&gt;vmid_mask_gfxhub;</div><div class='del'>-	mes_set_hw_res_pkt.gds_size = adev-&gt;gds.gds_size;</div><div class='del'>-	mes_set_hw_res_pkt.paging_vmid = 0;</div><div class='del'>-	mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes-&gt;sch_ctx_gpu_addr;</div><div class='del'>-	mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =</div><div class='del'>-		mes-&gt;query_status_fence_gpu_addr;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_COMPUTE_PIPES; i++)</div><div class='del'>-		mes_set_hw_res_pkt.compute_hqd_mask[i] =</div><div class='del'>-			mes-&gt;compute_hqd_mask[i];</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_GFX_PIPES; i++)</div><div class='del'>-		mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes-&gt;gfx_hqd_mask[i];</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_SDMA_PIPES; i++)</div><div class='del'>-		mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes-&gt;sdma_hqd_mask[i];</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; AMD_PRIORITY_NUM_LEVELS; i++)</div><div class='del'>-		mes_set_hw_res_pkt.aggregated_doorbells[i] =</div><div class='del'>-			mes-&gt;aggregated_doorbells[i];</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; 5; i++) {</div><div class='del'>-		mes_set_hw_res_pkt.gc_base[i] = adev-&gt;reg_offset[GC_HWIP][0][i];</div><div class='del'>-		mes_set_hw_res_pkt.mmhub_base[i] =</div><div class='del'>-			adev-&gt;reg_offset[MMHUB_HWIP][0][i];</div><div class='del'>-		mes_set_hw_res_pkt.osssys_base[i] =</div><div class='del'>-			adev-&gt;reg_offset[OSSSYS_HWIP][0][i];</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mes_set_hw_res_pkt.disable_reset = 1;</div><div class='del'>-	mes_set_hw_res_pkt.disable_mes_log = 1;</div><div class='del'>-	mes_set_hw_res_pkt.use_different_vmid_compute = 1;</div><div class='del'>-</div><div class='del'>-	return mes_v10_1_submit_pkt_and_poll_completion(mes,</div><div class='del'>-			&amp;mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),</div><div class='del'>-			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='del'>-	uint32_t data;</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1);</div><div class='del'>-	data &amp;= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);</div><div class='del'>-	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] &lt;&lt;</div><div class='del'>-		CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;</div><div class='del'>-	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1, data);</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2);</div><div class='del'>-	data &amp;= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);</div><div class='del'>-	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] &lt;&lt;</div><div class='del'>-		CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;</div><div class='del'>-	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2, data);</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3);</div><div class='del'>-	data &amp;= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);</div><div class='del'>-	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] &lt;&lt;</div><div class='del'>-		CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;</div><div class='del'>-	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3, data);</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4);</div><div class='del'>-	data &amp;= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);</div><div class='del'>-	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] &lt;&lt;</div><div class='del'>-		CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;</div><div class='del'>-	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4, data);</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5);</div><div class='del'>-	data &amp;= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |</div><div class='del'>-		  CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);</div><div class='del'>-	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] &lt;&lt;</div><div class='del'>-		CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;</div><div class='del'>-	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5, data);</div><div class='del'>-</div><div class='del'>-	data = 1 &lt;&lt; CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_GFX_CONTROL, data);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct amdgpu_mes_funcs mes_v10_1_funcs = {</div><div class='del'>-	.add_hw_queue = mes_v10_1_add_hw_queue,</div><div class='del'>-	.remove_hw_queue = mes_v10_1_remove_hw_queue,</div><div class='del'>-	.unmap_legacy_queue = mes_v10_1_unmap_legacy_queue,</div><div class='del'>-	.suspend_gang = mes_v10_1_suspend_gang,</div><div class='del'>-	.resume_gang = mes_v10_1_resume_gang,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev,</div><div class='del'>-					   enum admgpu_mes_pipe pipe)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='del'>-	const __le32 *fw_data;</div><div class='del'>-	unsigned fw_size;</div><div class='del'>-</div><div class='del'>-	mes_hdr = (const struct mes_firmware_header_v1_0 *)</div><div class='del'>-		adev-&gt;mes.fw[pipe]-&gt;data;</div><div class='del'>-</div><div class='del'>-	fw_data = (const __le32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='del'>-		   le32_to_cpu(mes_hdr-&gt;mes_ucode_offset_bytes));</div><div class='del'>-	fw_size = le32_to_cpu(mes_hdr-&gt;mes_ucode_size_bytes);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_reserved(adev, fw_size,</div><div class='del'>-				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				      &amp;adev-&gt;mes.ucode_fw_obj[pipe],</div><div class='del'>-				      &amp;adev-&gt;mes.ucode_fw_gpu_addr[pipe],</div><div class='del'>-				      (void **)&amp;adev-&gt;mes.ucode_fw_ptr[pipe]);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "(%d) failed to create mes fw bo\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	memcpy(adev-&gt;mes.ucode_fw_ptr[pipe], fw_data, fw_size);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_kunmap(adev-&gt;mes.ucode_fw_obj[pipe]);</div><div class='del'>-	amdgpu_bo_unreserve(adev-&gt;mes.ucode_fw_obj[pipe]);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev,</div><div class='del'>-						enum admgpu_mes_pipe pipe)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='del'>-	const __le32 *fw_data;</div><div class='del'>-	unsigned fw_size;</div><div class='del'>-</div><div class='del'>-	mes_hdr = (const struct mes_firmware_header_v1_0 *)</div><div class='del'>-		adev-&gt;mes.fw[pipe]-&gt;data;</div><div class='del'>-</div><div class='del'>-	fw_data = (const __le32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='del'>-		   le32_to_cpu(mes_hdr-&gt;mes_ucode_data_offset_bytes));</div><div class='del'>-	fw_size = le32_to_cpu(mes_hdr-&gt;mes_ucode_data_size_bytes);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_reserved(adev, fw_size,</div><div class='del'>-				      64 * 1024, AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-				      &amp;adev-&gt;mes.data_fw_obj[pipe],</div><div class='del'>-				      &amp;adev-&gt;mes.data_fw_gpu_addr[pipe],</div><div class='del'>-				      (void **)&amp;adev-&gt;mes.data_fw_ptr[pipe]);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "(%d) failed to create mes data fw bo\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	memcpy(adev-&gt;mes.data_fw_ptr[pipe], fw_data, fw_size);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_kunmap(adev-&gt;mes.data_fw_obj[pipe]);</div><div class='del'>-	amdgpu_bo_unreserve(adev-&gt;mes.data_fw_obj[pipe]);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mes_v10_1_free_ucode_buffers(struct amdgpu_device *adev,</div><div class='del'>-					 enum admgpu_mes_pipe pipe)</div><div class='del'>-{</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.data_fw_obj[pipe],</div><div class='del'>-			      &amp;adev-&gt;mes.data_fw_gpu_addr[pipe],</div><div class='del'>-			      (void **)&amp;adev-&gt;mes.data_fw_ptr[pipe]);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.ucode_fw_obj[pipe],</div><div class='del'>-			      &amp;adev-&gt;mes.ucode_fw_gpu_addr[pipe],</div><div class='del'>-			      (void **)&amp;adev-&gt;mes.ucode_fw_ptr[pipe]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable)</div><div class='del'>-{</div><div class='del'>-	uint32_t pipe, data = 0;</div><div class='del'>-</div><div class='del'>-	if (enable) {</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL,</div><div class='del'>-			     MES_PIPE1_RESET, adev-&gt;enable_mes_kiq ? 1 : 0);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);</div><div class='del'>-</div><div class='del'>-		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-		for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='del'>-			if (!adev-&gt;enable_mes_kiq &amp;&amp;</div><div class='del'>-			    pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			nv_grbm_select(adev, 3, pipe, 0, 0);</div><div class='del'>-			WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,</div><div class='del'>-			     (uint32_t)(adev-&gt;mes.uc_start_addr[pipe]) &gt;&gt; 2);</div><div class='del'>-		}</div><div class='del'>-		nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='del'>-		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-</div><div class='del'>-		/* clear BYPASS_UNCACHED to avoid hangs after interrupt. */</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_DC_OP_CNTL,</div><div class='del'>-				     BYPASS_UNCACHED, 0);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data);</div><div class='del'>-</div><div class='del'>-		/* unhalt MES and activate pipe0 */</div><div class='del'>-		data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,</div><div class='del'>-				     adev-&gt;enable_mes_kiq ? 1 : 0);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);</div><div class='del'>-		udelay(100);</div><div class='del'>-	} else {</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL,</div><div class='del'>-				     MES_INVALIDATE_ICACHE, 1);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,</div><div class='del'>-				     adev-&gt;enable_mes_kiq ? 1 : 0);</div><div class='del'>-		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* This function is for backdoor MES firmware */</div><div class='del'>-static int mes_v10_1_load_microcode(struct amdgpu_device *adev,</div><div class='del'>-				    enum admgpu_mes_pipe pipe)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	uint32_t data;</div><div class='del'>-</div><div class='del'>-	mes_v10_1_enable(adev, false);</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;mes.fw[pipe])</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_allocate_ucode_buffer(adev, pipe);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_allocate_ucode_data_buffer(adev, pipe);</div><div class='del'>-	if (r) {</div><div class='del'>-		mes_v10_1_free_ucode_buffers(adev, pipe);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0);</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-	/* me=3, pipe=0, queue=0 */</div><div class='del'>-	nv_grbm_select(adev, 3, pipe, 0, 0);</div><div class='del'>-</div><div class='del'>-	/* set ucode start address */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,</div><div class='del'>-		     (uint32_t)(adev-&gt;mes.uc_start_addr[pipe]) &gt;&gt; 2);</div><div class='del'>-</div><div class='del'>-	/* set ucode fimrware address */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO,</div><div class='del'>-		     lower_32_bits(adev-&gt;mes.ucode_fw_gpu_addr[pipe]));</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI,</div><div class='del'>-		     upper_32_bits(adev-&gt;mes.ucode_fw_gpu_addr[pipe]));</div><div class='del'>-</div><div class='del'>-	/* set ucode instruction cache boundary to 2M-1 */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF);</div><div class='del'>-</div><div class='del'>-	/* set ucode data firmware address */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO,</div><div class='del'>-		     lower_32_bits(adev-&gt;mes.data_fw_gpu_addr[pipe]));</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI,</div><div class='del'>-		     upper_32_bits(adev-&gt;mes.data_fw_gpu_addr[pipe]));</div><div class='del'>-</div><div class='del'>-	/* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);</div><div class='del'>-</div><div class='del'>-	/* invalidate ICACHE */</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(10, 3, 0):</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);</div><div class='del'>-	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(10, 3, 0):</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* prime the ICACHE. */</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(10, 3, 0):</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(10, 3, 0):</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev,</div><div class='del'>-				      enum admgpu_mes_pipe pipe)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	u32 *eop;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,</div><div class='del'>-			      AMDGPU_GEM_DOMAIN_GTT,</div><div class='del'>-			      &amp;adev-&gt;mes.eop_gpu_obj[pipe],</div><div class='del'>-			      &amp;adev-&gt;mes.eop_gpu_addr[pipe],</div><div class='del'>-			      (void **)&amp;eop);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "(%d) create EOP bo failed\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	memset(eop, 0, adev-&gt;mes.eop_gpu_obj[pipe]-&gt;tbo.base.size);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_kunmap(adev-&gt;mes.eop_gpu_obj[pipe]);</div><div class='del'>-	amdgpu_bo_unreserve(adev-&gt;mes.eop_gpu_obj[pipe]);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_mqd_init(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	struct v10_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='del'>-	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;</div><div class='del'>-	uint32_t tmp;</div><div class='del'>-</div><div class='del'>-	memset(mqd, 0, sizeof(*mqd));</div><div class='del'>-</div><div class='del'>-	mqd-&gt;header = 0xC0310800;</div><div class='del'>-	mqd-&gt;compute_pipelinestat_enable = 0x00000001;</div><div class='del'>-	mqd-&gt;compute_static_thread_mgmt_se0 = 0xffffffff;</div><div class='del'>-	mqd-&gt;compute_static_thread_mgmt_se1 = 0xffffffff;</div><div class='del'>-	mqd-&gt;compute_static_thread_mgmt_se2 = 0xffffffff;</div><div class='del'>-	mqd-&gt;compute_static_thread_mgmt_se3 = 0xffffffff;</div><div class='del'>-	mqd-&gt;compute_misc_reserved = 0x00000003;</div><div class='del'>-</div><div class='del'>-	eop_base_addr = ring-&gt;eop_gpu_addr &gt;&gt; 8;</div><div class='del'>-</div><div class='del'>-	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */</div><div class='del'>-	tmp = mmCP_HQD_EOP_CONTROL_DEFAULT;</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,</div><div class='del'>-			(order_base_2(MES_EOP_SIZE / 4) - 1));</div><div class='del'>-</div><div class='del'>-	mqd-&gt;cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);</div><div class='del'>-	mqd-&gt;cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);</div><div class='del'>-	mqd-&gt;cp_hqd_eop_control = tmp;</div><div class='del'>-</div><div class='del'>-	/* disable the queue if it's active */</div><div class='del'>-	ring-&gt;wptr = 0;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_rptr = 0;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_wptr_lo = 0;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_wptr_hi = 0;</div><div class='del'>-</div><div class='del'>-	/* set the pointer to the MQD */</div><div class='del'>-	mqd-&gt;cp_mqd_base_addr_lo = ring-&gt;mqd_gpu_addr &amp; 0xfffffffc;</div><div class='del'>-	mqd-&gt;cp_mqd_base_addr_hi = upper_32_bits(ring-&gt;mqd_gpu_addr);</div><div class='del'>-</div><div class='del'>-	/* set MQD vmid to 0 */</div><div class='del'>-	tmp = mmCP_MQD_CONTROL_DEFAULT;</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);</div><div class='del'>-	mqd-&gt;cp_mqd_control = tmp;</div><div class='del'>-</div><div class='del'>-	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */</div><div class='del'>-	hqd_gpu_addr = ring-&gt;gpu_addr &gt;&gt; 8;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);</div><div class='del'>-	mqd-&gt;cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);</div><div class='del'>-</div><div class='del'>-	/* set the wb address whether it's enabled or not */</div><div class='del'>-	wb_gpu_addr = ring-&gt;rptr_gpu_addr;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_rptr_report_addr_hi =</div><div class='del'>-		upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='del'>-</div><div class='del'>-	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */</div><div class='del'>-	wb_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr &amp; 0xfffffff8;</div><div class='del'>-	mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='del'>-</div><div class='del'>-	/* set up the HQD, this is similar to CP_RB0_CNTL */</div><div class='del'>-	tmp = mmCP_HQD_PQ_CONTROL_DEFAULT;</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,</div><div class='del'>-			    (order_base_2(ring-&gt;ring_size / 4) - 1));</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,</div><div class='del'>-			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) &lt;&lt; 8));</div><div class='del'>-#ifdef __BIG_ENDIAN</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);</div><div class='del'>-#endif</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);</div><div class='del'>-	mqd-&gt;cp_hqd_pq_control = tmp;</div><div class='del'>-</div><div class='del'>-	/* enable doorbell? */</div><div class='del'>-	tmp = 0;</div><div class='del'>-	if (ring-&gt;use_doorbell) {</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-				    DOORBELL_OFFSET, ring-&gt;doorbell_index);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-				    DOORBELL_EN, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-				    DOORBELL_SOURCE, 0);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-				    DOORBELL_HIT, 0);</div><div class='del'>-	}</div><div class='del'>-	else</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-				    DOORBELL_EN, 0);</div><div class='del'>-	mqd-&gt;cp_hqd_pq_doorbell_control = tmp;</div><div class='del'>-</div><div class='del'>-	mqd-&gt;cp_hqd_vmid = 0;</div><div class='del'>-	/* activate the queue */</div><div class='del'>-	mqd-&gt;cp_hqd_active = 1;</div><div class='del'>-	mqd-&gt;cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT;</div><div class='del'>-	mqd-&gt;cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT;</div><div class='del'>-	mqd-&gt;cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT;</div><div class='del'>-	mqd-&gt;cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT;</div><div class='del'>-</div><div class='del'>-	tmp = mmCP_HQD_GFX_CONTROL_DEFAULT;</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_GFX_CONTROL, DB_UPDATED_MSG_EN, 1);</div><div class='del'>-	/* offset: 184 - this is used for CP_HQD_GFX_CONTROL */</div><div class='del'>-	mqd-&gt;cp_hqd_suspend_cntl_stack_offset = tmp;</div><div class='del'>-</div><div class='del'>-	amdgpu_device_flush_hdp(ring-&gt;adev, NULL);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#if 0</div><div class='del'>-static void mes_v10_1_queue_init_register(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	struct v10_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='del'>-	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	uint32_t data = 0;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-	nv_grbm_select(adev, 3, ring-&gt;pipe, 0, 0);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_VMID.VMID = 0. */</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID);</div><div class='del'>-	data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);</div><div class='del'>-	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-			     DOORBELL_EN, 0);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);</div><div class='del'>-</div><div class='del'>-	/* set CP_MQD_BASE_ADDR/HI with the MQD base address */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd-&gt;cp_mqd_base_addr_lo);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd-&gt;cp_mqd_base_addr_hi);</div><div class='del'>-</div><div class='del'>-	/* set CP_MQD_CONTROL.VMID=0 */</div><div class='del'>-	data = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);</div><div class='del'>-	data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 0);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PQ_BASE/HI with the ring buffer base address */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd-&gt;cp_hqd_pq_base_lo);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd-&gt;cp_hqd_pq_base_hi);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,</div><div class='del'>-		     mqd-&gt;cp_hqd_pq_rptr_report_addr_lo);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,</div><div class='del'>-		     mqd-&gt;cp_hqd_pq_rptr_report_addr_hi);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PQ_CONTROL */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd-&gt;cp_hqd_pq_control);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,</div><div class='del'>-		     mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo);</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,</div><div class='del'>-		     mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PQ_DOORBELL_CONTROL */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,</div><div class='del'>-		     mqd-&gt;cp_hqd_pq_doorbell_control);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd-&gt;cp_hqd_persistent_state);</div><div class='del'>-</div><div class='del'>-	/* set CP_HQD_ACTIVE.ACTIVE=1 */</div><div class='del'>-	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd-&gt;cp_hqd_active);</div><div class='del'>-</div><div class='del'>-	nv_grbm_select(adev, 0, 0, 0, 0);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='del'>-	struct amdgpu_ring *kiq_ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_map_queues)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to lock KIQ (%d).\n", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, &amp;adev-&gt;mes.ring);</div><div class='del'>-</div><div class='del'>-	return amdgpu_ring_test_helper(kiq_ring);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_queue_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_mqd_init(&amp;adev-&gt;mes.ring);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_kiq_enable_queue(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_ring_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;mes.ring;</div><div class='del'>-</div><div class='del'>-	ring-&gt;funcs = &amp;mes_v10_1_ring_funcs;</div><div class='del'>-</div><div class='del'>-	ring-&gt;me = 3;</div><div class='del'>-	ring-&gt;pipe = 0;</div><div class='del'>-	ring-&gt;queue = 0;</div><div class='del'>-</div><div class='del'>-	ring-&gt;ring_obj = NULL;</div><div class='del'>-	ring-&gt;use_doorbell = true;</div><div class='del'>-	ring-&gt;doorbell_index = adev-&gt;doorbell_index.mes_ring0 &lt;&lt; 1;</div><div class='del'>-	ring-&gt;eop_gpu_addr = adev-&gt;mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];</div><div class='del'>-	ring-&gt;no_scheduler = true;</div><div class='del'>-	sprintf(ring-&gt;name, "mes_%d.%d.%d", ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='del'>-</div><div class='del'>-	return amdgpu_ring_init(adev, ring, 1024, NULL, 0,</div><div class='del'>-				AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_kiq_ring_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-</div><div class='del'>-	spin_lock_init(&amp;adev-&gt;gfx.kiq[0].ring_lock);</div><div class='del'>-</div><div class='del'>-	ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-</div><div class='del'>-	ring-&gt;me = 3;</div><div class='del'>-	ring-&gt;pipe = 1;</div><div class='del'>-	ring-&gt;queue = 0;</div><div class='del'>-</div><div class='del'>-	ring-&gt;adev = NULL;</div><div class='del'>-	ring-&gt;ring_obj = NULL;</div><div class='del'>-	ring-&gt;use_doorbell = true;</div><div class='del'>-	ring-&gt;doorbell_index = adev-&gt;doorbell_index.mes_ring1 &lt;&lt; 1;</div><div class='del'>-	ring-&gt;eop_gpu_addr = adev-&gt;mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];</div><div class='del'>-	ring-&gt;no_scheduler = true;</div><div class='del'>-	sprintf(ring-&gt;name, "mes_kiq_%d.%d.%d",</div><div class='del'>-		ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='del'>-</div><div class='del'>-	return amdgpu_ring_init(adev, ring, 1024, NULL, 0,</div><div class='del'>-				AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev,</div><div class='del'>-				 enum admgpu_mes_pipe pipe)</div><div class='del'>-{</div><div class='del'>-	int r, mqd_size = sizeof(struct v10_compute_mqd);</div><div class='del'>-	struct amdgpu_ring *ring;</div><div class='del'>-</div><div class='del'>-	if (pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='del'>-		ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='del'>-	else if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='del'>-		ring = &amp;adev-&gt;mes.ring;</div><div class='del'>-	else</div><div class='del'>-		BUG();</div><div class='del'>-</div><div class='del'>-	if (ring-&gt;mqd_obj)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_VRAM |</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_GTT, &amp;ring-&gt;mqd_obj,</div><div class='del'>-				    &amp;ring-&gt;mqd_gpu_addr, &amp;ring-&gt;mqd_ptr);</div><div class='del'>-	if (r) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "failed to create ring mqd bo (%d)", r);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-	memset(ring-&gt;mqd_ptr, 0, mqd_size);</div><div class='del'>-</div><div class='del'>-	/* prepare MQD backup */</div><div class='del'>-	adev-&gt;mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);</div><div class='del'>-	if (!adev-&gt;mes.mqd_backup[pipe]) {</div><div class='del'>-		dev_warn(adev-&gt;dev,</div><div class='del'>-			 "no memory to create MQD backup for ring %s\n",</div><div class='del'>-			 ring-&gt;name);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_sw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int pipe, r;</div><div class='del'>-</div><div class='del'>-	adev-&gt;mes.funcs = &amp;mes_v10_1_funcs;</div><div class='del'>-	adev-&gt;mes.kiq_hw_init = &amp;mes_v10_1_kiq_hw_init;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='del'>-		if (!adev-&gt;enable_mes_kiq &amp;&amp; pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r = mes_v10_1_allocate_eop_buf(adev, pipe);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-</div><div class='del'>-		r = mes_v10_1_mqd_sw_init(adev, pipe);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;enable_mes_kiq) {</div><div class='del'>-		r = mes_v10_1_kiq_ring_init(adev);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_ring_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_sw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int pipe;</div><div class='del'>-</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='del'>-</div><div class='del'>-	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='del'>-		kfree(adev-&gt;mes.mqd_backup[pipe]);</div><div class='del'>-</div><div class='del'>-		amdgpu_bo_free_kernel(&amp;adev-&gt;mes.eop_gpu_obj[pipe],</div><div class='del'>-				      &amp;adev-&gt;mes.eop_gpu_addr[pipe],</div><div class='del'>-				      NULL);</div><div class='del'>-		amdgpu_ucode_release(&amp;adev-&gt;mes.fw[pipe]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.kiq[0].ring.mqd_obj,</div><div class='del'>-			      &amp;adev-&gt;gfx.kiq[0].ring.mqd_gpu_addr,</div><div class='del'>-			      &amp;adev-&gt;gfx.kiq[0].ring.mqd_ptr);</div><div class='del'>-</div><div class='del'>-	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.ring.mqd_obj,</div><div class='del'>-			      &amp;adev-&gt;mes.ring.mqd_gpu_addr,</div><div class='del'>-			      &amp;adev-&gt;mes.ring.mqd_ptr);</div><div class='del'>-</div><div class='del'>-	amdgpu_ring_fini(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='del'>-	amdgpu_ring_fini(&amp;adev-&gt;mes.ring);</div><div class='del'>-</div><div class='del'>-	amdgpu_mes_fini(adev);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mes_v10_1_kiq_setting(struct amdgpu_ring *ring)</div><div class='del'>-{</div><div class='del'>-	uint32_t tmp;</div><div class='del'>-	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-</div><div class='del'>-	/* tell RLC which is KIQ queue */</div><div class='del'>-	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='del'>-	case IP_VERSION(10, 3, 0):</div><div class='del'>-	case IP_VERSION(10, 3, 2):</div><div class='del'>-	case IP_VERSION(10, 3, 1):</div><div class='del'>-	case IP_VERSION(10, 3, 4):</div><div class='del'>-		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);</div><div class='del'>-		tmp &amp;= 0xffffff00;</div><div class='del'>-		tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);</div><div class='del'>-		tmp |= 0x80;</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);</div><div class='del'>-		tmp &amp;= 0xffffff00;</div><div class='del'>-		tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-		tmp |= 0x80;</div><div class='del'>-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	int r = 0;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='del'>-		r = mes_v10_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		r = mes_v10_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("failed to load MES fw, r=%d\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mes_v10_1_enable(adev, true);</div><div class='del'>-</div><div class='del'>-	mes_v10_1_kiq_setting(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_queue_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		goto failure;</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-</div><div class='del'>-failure:</div><div class='del'>-	mes_v10_1_hw_fini(adev);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_hw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;enable_mes_kiq) {</div><div class='del'>-		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='del'>-			r = mes_v10_1_load_microcode(adev,</div><div class='del'>-					     AMDGPU_MES_SCHED_PIPE);</div><div class='del'>-			if (r) {</div><div class='del'>-				DRM_ERROR("failed to MES fw, r=%d\n", r);</div><div class='del'>-				return r;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		mes_v10_1_enable(adev, true);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_queue_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		goto failure;</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_set_hw_resources(&amp;adev-&gt;mes);</div><div class='del'>-	if (r)</div><div class='del'>-		goto failure;</div><div class='del'>-</div><div class='del'>-	mes_v10_1_init_aggregated_doorbell(&amp;adev-&gt;mes);</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_query_sched_status(&amp;adev-&gt;mes);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("MES is busy\n");</div><div class='del'>-		goto failure;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Disable KIQ ring usage from the driver once MES is enabled.</div><div class='del'>-	 * MES uses KIQ ring exclusively so driver cannot access KIQ ring</div><div class='del'>-	 * with MES enabled.</div><div class='del'>-	 */</div><div class='del'>-	adev-&gt;gfx.kiq[0].ring.sched.ready = false;</div><div class='del'>-	adev-&gt;mes.ring.sched.ready = true;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-failure:</div><div class='del'>-	mes_v10_1_hw_fini(adev);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_hw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	adev-&gt;mes.ring.sched.ready = false;</div><div class='del'>-</div><div class='del'>-	mes_v10_1_enable(adev, false);</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='del'>-		mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);</div><div class='del'>-		mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_suspend(void *handle)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return mes_v10_1_hw_fini(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_1_resume(void *handle)</div><div class='del'>-{</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	r = mes_v10_1_hw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return amdgpu_mes_resume(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_0_early_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int pipe, r;</div><div class='del'>-</div><div class='del'>-	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='del'>-		if (!adev-&gt;enable_mes_kiq &amp;&amp; pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='del'>-			continue;</div><div class='del'>-		r = amdgpu_mes_init_microcode(adev, pipe);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mes_v10_0_late_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_in_reset(adev))</div><div class='del'>-		amdgpu_mes_self_test(adev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct amd_ip_funcs mes_v10_1_ip_funcs = {</div><div class='del'>-	.name = "mes_v10_1",</div><div class='del'>-	.early_init = mes_v10_0_early_init,</div><div class='del'>-	.late_init = mes_v10_0_late_init,</div><div class='del'>-	.sw_init = mes_v10_1_sw_init,</div><div class='del'>-	.sw_fini = mes_v10_1_sw_fini,</div><div class='del'>-	.hw_init = mes_v10_1_hw_init,</div><div class='del'>-	.hw_fini = mes_v10_1_hw_fini,</div><div class='del'>-	.suspend = mes_v10_1_suspend,</div><div class='del'>-	.resume = mes_v10_1_resume,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-const struct amdgpu_ip_block_version mes_v10_1_ip_block = {</div><div class='del'>-	.type = AMD_IP_BLOCK_TYPE_MES,</div><div class='del'>-	.major = 10,</div><div class='del'>-	.minor = 1,</div><div class='del'>-	.rev = 0,</div><div class='del'>-	.funcs = &amp;mes_v10_1_ip_funcs,</div><div class='del'>-};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c<br/>index 072c478665ad..3a52754b5cad 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mes_v11_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mes_v11_0.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "soc15_common.h"</div><div class='ctx'> #include "soc21.h"</div><div class='add'>+#include "gfx_v11_0.h"</div><div class='ctx'> #include "gc/gc_11_0_0_offset.h"</div><div class='ctx'> #include "gc/gc_11_0_0_sh_mask.h"</div><div class='ctx'> #include "gc/gc_11_0_0_default.h"</div><div class='hunk'>@@ -51,14 +52,22 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin");</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-static int mes_v11_0_hw_fini(void *handle);</div><div class='add'>+static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block);</div><div class='add'>+static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);</div><div class='ctx'> static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #define MES_EOP_SIZE   2048</div><div class='ctx'> #define GFX_MES_DRAM_SIZE	0x80000</div><div class='add'>+#define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+#define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */</div><div class='add'>+#define MES11_HUNG_HQD_INFO_OFFSET	4</div><div class='ctx'> </div><div class='ctx'> static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='hunk'>@@ -100,18 +109,79 @@ static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {</div><div class='ctx'> 	.insert_nop = amdgpu_ring_insert_nop,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const char *mes_v11_0_opcodes[] = {</div><div class='add'>+	"SET_HW_RSRC",</div><div class='add'>+	"SET_SCHEDULING_CONFIG",</div><div class='add'>+	"ADD_QUEUE",</div><div class='add'>+	"REMOVE_QUEUE",</div><div class='add'>+	"PERFORM_YIELD",</div><div class='add'>+	"SET_GANG_PRIORITY_LEVEL",</div><div class='add'>+	"SUSPEND",</div><div class='add'>+	"RESUME",</div><div class='add'>+	"RESET",</div><div class='add'>+	"SET_LOG_BUFFER",</div><div class='add'>+	"CHANGE_GANG_PRORITY",</div><div class='add'>+	"QUERY_SCHEDULER_STATUS",</div><div class='add'>+	"PROGRAM_GDS",</div><div class='add'>+	"SET_DEBUG_VMID",</div><div class='add'>+	"MISC",</div><div class='add'>+	"UPDATE_ROOT_PAGE_TABLE",</div><div class='add'>+	"AMD_LOG",</div><div class='add'>+	"unused",</div><div class='add'>+	"unused",</div><div class='add'>+	"SET_HW_RSRC_1",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *mes_v11_0_misc_opcodes[] = {</div><div class='add'>+	"WRITE_REG",</div><div class='add'>+	"INV_GART",</div><div class='add'>+	"QUERY_STATUS",</div><div class='add'>+	"READ_REG",</div><div class='add'>+	"WAIT_REG_MEM",</div><div class='add'>+	"SET_SHADER_DEBUGGER",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt)</div><div class='add'>+{</div><div class='add'>+	const char *op_str = NULL;</div><div class='add'>+</div><div class='add'>+	if (x_pkt-&gt;header.opcode &lt; ARRAY_SIZE(mes_v11_0_opcodes))</div><div class='add'>+		op_str = mes_v11_0_opcodes[x_pkt-&gt;header.opcode];</div><div class='add'>+</div><div class='add'>+	return op_str;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt)</div><div class='add'>+{</div><div class='add'>+	const char *op_str = NULL;</div><div class='add'>+</div><div class='add'>+	if ((x_pkt-&gt;header.opcode == MES_SCH_API_MISC) &amp;&amp;</div><div class='add'>+	    (x_pkt-&gt;opcode &lt; ARRAY_SIZE(mes_v11_0_misc_opcodes)))</div><div class='add'>+		op_str = mes_v11_0_misc_opcodes[x_pkt-&gt;opcode];</div><div class='add'>+</div><div class='add'>+	return op_str;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,</div><div class='ctx'> 						    void *pkt, int size,</div><div class='ctx'> 						    int api_status_off)</div><div class='ctx'> {</div><div class='del'>-	int ndw = size / 4;</div><div class='del'>-	signed long r;</div><div class='del'>-	union MESAPI__ADD_QUEUE *x_pkt = pkt;</div><div class='del'>-	struct MES_API_STATUS *api_status;</div><div class='add'>+	union MESAPI__QUERY_MES_STATUS mes_status_pkt;</div><div class='add'>+	signed long timeout = 2100000; /* 2100 ms */</div><div class='ctx'> 	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='del'>-	struct amdgpu_ring *ring = &amp;mes-&gt;ring;</div><div class='add'>+	struct amdgpu_ring *ring = &amp;mes-&gt;ring[0];</div><div class='add'>+	struct MES_API_STATUS *api_status;</div><div class='add'>+	union MESAPI__MISC *x_pkt = pkt;</div><div class='add'>+	const char *op_str, *misc_op_str;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	signed long timeout = adev-&gt;usec_timeout;</div><div class='add'>+	u64 status_gpu_addr;</div><div class='add'>+	u32 seq, status_offset;</div><div class='add'>+	u64 *status_ptr;</div><div class='add'>+	signed long r;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (x_pkt-&gt;header.opcode &gt;= MES_SCH_API_MAX)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_emu_mode) {</div><div class='ctx'> 		timeout *= 100;</div><div class='hunk'>@@ -119,37 +189,92 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,</div><div class='ctx'> 		/* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */</div><div class='ctx'> 		timeout = 15 * 600 * 1000;</div><div class='ctx'> 	}</div><div class='del'>-	BUG_ON(size % 4 != 0);</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;mes-&gt;ring_lock, flags);</div><div class='del'>-	if (amdgpu_ring_alloc(ring, ndw)) {</div><div class='del'>-		spin_unlock_irqrestore(&amp;mes-&gt;ring_lock, flags);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='add'>+	ret = amdgpu_device_wb_get(adev, &amp;status_offset);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	status_gpu_addr = adev-&gt;wb.gpu_addr + (status_offset * 4);</div><div class='add'>+	status_ptr = (u64 *)&amp;adev-&gt;wb.wb[status_offset];</div><div class='add'>+	*status_ptr = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;mes-&gt;ring_lock[0], flags);</div><div class='add'>+	r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_unlock_free;</div><div class='add'>+</div><div class='add'>+	seq = ++ring-&gt;fence_drv.sync_seq;</div><div class='add'>+	r = amdgpu_fence_wait_polling(ring,</div><div class='add'>+				      seq - ring-&gt;fence_drv.num_fences_mask,</div><div class='add'>+				      timeout);</div><div class='add'>+	if (r &lt; 1)</div><div class='add'>+		goto error_undo;</div><div class='ctx'> </div><div class='ctx'> 	api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);</div><div class='del'>-	api_status-&gt;api_completion_fence_addr = mes-&gt;ring.fence_drv.gpu_addr;</div><div class='del'>-	api_status-&gt;api_completion_fence_value = ++mes-&gt;ring.fence_drv.sync_seq;</div><div class='add'>+	api_status-&gt;api_completion_fence_addr = status_gpu_addr;</div><div class='add'>+	api_status-&gt;api_completion_fence_value = 1;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write_multiple(ring, pkt, size / 4);</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_status_pkt, 0, sizeof(mes_status_pkt));</div><div class='add'>+	mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;</div><div class='add'>+	mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+	mes_status_pkt.api_status.api_completion_fence_addr =</div><div class='add'>+		ring-&gt;fence_drv.gpu_addr;</div><div class='add'>+	mes_status_pkt.api_status.api_completion_fence_value = seq;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write_multiple(ring, &amp;mes_status_pkt,</div><div class='add'>+				   sizeof(mes_status_pkt) / 4);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write_multiple(ring, pkt, ndw);</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='del'>-	spin_unlock_irqrestore(&amp;mes-&gt;ring_lock, flags);</div><div class='add'>+	spin_unlock_irqrestore(&amp;mes-&gt;ring_lock[0], flags);</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG("MES msg=%d was emitted\n", x_pkt-&gt;header.opcode);</div><div class='add'>+	op_str = mes_v11_0_get_op_string(x_pkt);</div><div class='add'>+	misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_fence_wait_polling(ring, ring-&gt;fence_drv.sync_seq,</div><div class='del'>-		      timeout);</div><div class='del'>-	if (r &lt; 1) {</div><div class='del'>-		DRM_ERROR("MES failed to response msg=%d\n",</div><div class='del'>-			  x_pkt-&gt;header.opcode);</div><div class='add'>+	if (misc_op_str)</div><div class='add'>+		dev_dbg(adev-&gt;dev, "MES msg=%s (%s) was emitted\n", op_str,</div><div class='add'>+			misc_op_str);</div><div class='add'>+	else if (op_str)</div><div class='add'>+		dev_dbg(adev-&gt;dev, "MES msg=%s was emitted\n", op_str);</div><div class='add'>+	else</div><div class='add'>+		dev_dbg(adev-&gt;dev, "MES msg=%d was emitted\n",</div><div class='add'>+			x_pkt-&gt;header.opcode);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_fence_wait_polling(ring, seq, timeout);</div><div class='add'>+	if (r &lt; 1 || !*status_ptr) {</div><div class='add'>+</div><div class='add'>+		if (misc_op_str)</div><div class='add'>+			dev_err(adev-&gt;dev, "MES failed to respond to msg=%s (%s)\n",</div><div class='add'>+				op_str, misc_op_str);</div><div class='add'>+		else if (op_str)</div><div class='add'>+			dev_err(adev-&gt;dev, "MES failed to respond to msg=%s\n",</div><div class='add'>+				op_str);</div><div class='add'>+		else</div><div class='add'>+			dev_err(adev-&gt;dev, "MES failed to respond to msg=%d\n",</div><div class='add'>+				x_pkt-&gt;header.opcode);</div><div class='ctx'> </div><div class='ctx'> 		while (halt_if_hws_hang)</div><div class='ctx'> 			schedule();</div><div class='ctx'> </div><div class='del'>-		return -ETIMEDOUT;</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+		goto error_wb_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_device_wb_free(adev, status_offset);</div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+error_undo:</div><div class='add'>+	dev_err(adev-&gt;dev, "MES ring buffer is full.\n");</div><div class='add'>+	amdgpu_ring_undo(ring);</div><div class='add'>+</div><div class='add'>+error_unlock_free:</div><div class='add'>+	spin_unlock_irqrestore(&amp;mes-&gt;ring_lock[0], flags);</div><div class='add'>+</div><div class='add'>+error_wb_free:</div><div class='add'>+	amdgpu_device_wb_free(adev, status_offset);</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int convert_to_mes_queue_type(int queue_type)</div><div class='hunk'>@@ -165,6 +290,23 @@ static int convert_to_mes_queue_type(int queue_type)</div><div class='ctx'> 	return -1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int convert_to_mes_priority_level(int priority_level)</div><div class='add'>+{</div><div class='add'>+	switch (priority_level) {</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_LOW:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_LOW;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_NORMAL:</div><div class='add'>+	default:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_NORMAL;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_MEDIUM;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_HIGH:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_HIGH;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_REALTIME:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_REALTIME;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,</div><div class='ctx'> 				  struct mes_add_queue_input *input)</div><div class='ctx'> {</div><div class='hunk'>@@ -188,9 +330,9 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,</div><div class='ctx'> 	mes_add_queue_pkt.gang_quantum = input-&gt;gang_quantum;</div><div class='ctx'> 	mes_add_queue_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='ctx'> 	mes_add_queue_pkt.inprocess_gang_priority =</div><div class='del'>-		input-&gt;inprocess_gang_priority;</div><div class='add'>+		convert_to_mes_priority_level(input-&gt;inprocess_gang_priority);</div><div class='ctx'> 	mes_add_queue_pkt.gang_global_priority_level =</div><div class='del'>-		input-&gt;gang_global_priority_level;</div><div class='add'>+		convert_to_mes_priority_level(input-&gt;gang_global_priority_level);</div><div class='ctx'> 	mes_add_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='ctx'> 	mes_add_queue_pkt.mqd_addr = input-&gt;mqd_addr;</div><div class='ctx'> </div><div class='hunk'>@@ -227,6 +369,7 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,</div><div class='ctx'> 				     struct mes_remove_queue_input *input)</div><div class='ctx'> {</div><div class='ctx'> 	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;</div><div class='add'>+	uint32_t mes_rev = mes-&gt;sched_version &amp; AMDGPU_MES_VERSION_MASK;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));</div><div class='ctx'> </div><div class='hunk'>@@ -237,11 +380,133 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,</div><div class='ctx'> 	mes_remove_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='ctx'> 	mes_remove_queue_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='ctx'> </div><div class='add'>+	if (mes_rev &gt;= 0x60)</div><div class='add'>+		mes_remove_queue_pkt.remove_queue_after_reset = input-&gt;remove_queue_after_reset;</div><div class='add'>+</div><div class='ctx'> 	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='ctx'> 			&amp;mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),</div><div class='ctx'> 			offsetof(union MESAPI__REMOVE_QUEUE, api_status));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,</div><div class='add'>+				      uint32_t me_id, uint32_t pipe_id,</div><div class='add'>+				      uint32_t queue_id, uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	uint32_t value, reg;</div><div class='add'>+	int i, r = 0;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	if (queue_type == AMDGPU_RING_TYPE_GFX) {</div><div class='add'>+		dev_info(adev-&gt;dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n",</div><div class='add'>+			 me_id, pipe_id, queue_id, vmid);</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='add'>+		gfx_v11_0_request_gfx_index_mutex(adev, true);</div><div class='add'>+		/* all se allow writes */</div><div class='add'>+		WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,</div><div class='add'>+			     (uint32_t)(0x1 &lt;&lt; GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));</div><div class='add'>+		value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 &lt;&lt; vmid);</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 &lt;&lt; queue_id);</div><div class='add'>+		else</div><div class='add'>+			value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 &lt;&lt; queue_id);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_VMID_RESET, value);</div><div class='add'>+		gfx_v11_0_request_gfx_index_mutex(adev, false);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on gfx hqd deactivate\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	} else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='add'>+		dev_info(adev-&gt;dev, "reset compute queue (%d:%d:%d)\n",</div><div class='add'>+			 me_id, pipe_id, queue_id);</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);</div><div class='add'>+		WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='add'>+</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on hqd deactivate\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	} else if (queue_type == AMDGPU_RING_TYPE_SDMA) {</div><div class='add'>+		dev_info(adev-&gt;dev, "reset sdma queue (%d:%d:%d)\n",</div><div class='add'>+			 me_id, pipe_id, queue_id);</div><div class='add'>+		switch (me_id) {</div><div class='add'>+		case 1:</div><div class='add'>+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);</div><div class='add'>+			break;</div><div class='add'>+		case 0:</div><div class='add'>+		default:</div><div class='add'>+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		value = 1 &lt;&lt; queue_id;</div><div class='add'>+		WREG32(reg, value);</div><div class='add'>+		/* wait for queue reset done */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32(reg) &amp; value))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on sdma queue reset done\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes,</div><div class='add'>+				      struct mes_map_legacy_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__ADD_QUEUE mes_add_queue_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;</div><div class='add'>+	mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.pipe_id = input-&gt;pipe_id;</div><div class='add'>+	mes_add_queue_pkt.queue_id = input-&gt;queue_id;</div><div class='add'>+	mes_add_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	mes_add_queue_pkt.mqd_addr = input-&gt;mqd_addr;</div><div class='add'>+	mes_add_queue_pkt.wptr_addr = input-&gt;wptr_addr;</div><div class='add'>+	mes_add_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+	mes_add_queue_pkt.map_legacy_kq = 1;</div><div class='add'>+</div><div class='add'>+	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			&amp;mes_add_queue_pkt, sizeof(mes_add_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__ADD_QUEUE, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,</div><div class='ctx'> 			struct mes_unmap_legacy_queue_input *input)</div><div class='ctx'> {</div><div class='hunk'>@@ -278,13 +543,41 @@ static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,</div><div class='ctx'> static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,</div><div class='ctx'> 				  struct mes_suspend_gang_input *input)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='add'>+	union MESAPI__SUSPEND mes_suspend_gang_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt));</div><div class='add'>+</div><div class='add'>+	mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND;</div><div class='add'>+	mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_suspend_gang_pkt.suspend_all_gangs = input-&gt;suspend_all_gangs;</div><div class='add'>+	mes_suspend_gang_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='add'>+	mes_suspend_gang_pkt.suspend_fence_addr = input-&gt;suspend_fence_addr;</div><div class='add'>+	mes_suspend_gang_pkt.suspend_fence_value = input-&gt;suspend_fence_value;</div><div class='add'>+</div><div class='add'>+	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			&amp;mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt),</div><div class='add'>+			offsetof(union MESAPI__SUSPEND, api_status));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,</div><div class='ctx'> 				 struct mes_resume_gang_input *input)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='add'>+	union MESAPI__RESUME mes_resume_gang_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt));</div><div class='add'>+</div><div class='add'>+	mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME;</div><div class='add'>+	mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_resume_gang_pkt.resume_all_gangs = input-&gt;resume_all_gangs;</div><div class='add'>+	mes_resume_gang_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='add'>+</div><div class='add'>+	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			&amp;mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt),</div><div class='add'>+			offsetof(union MESAPI__RESUME, api_status));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)</div><div class='hunk'>@@ -353,6 +646,19 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,</div><div class='ctx'> 				sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));</div><div class='ctx'> 		misc_pkt.set_shader_debugger.trap_en = input-&gt;set_shader_debugger.trap_en;</div><div class='ctx'> 		break;</div><div class='add'>+	case MES_MISC_OP_CHANGE_CONFIG:</div><div class='add'>+		if ((mes-&gt;adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &lt; 0x63) {</div><div class='add'>+			dev_warn_once(mes-&gt;adev-&gt;dev,</div><div class='add'>+				      "MES FW version must be larger than 0x63 to support limit single process feature.\n");</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;</div><div class='add'>+		misc_pkt.change_config.opcode =</div><div class='add'>+				MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;</div><div class='add'>+		misc_pkt.change_config.option.bits.limit_single_process =</div><div class='add'>+				input-&gt;change_config.option.limit_single_process;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='ctx'> 	default:</div><div class='ctx'> 		DRM_ERROR("unsupported misc op (%d) \n", input-&gt;op);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -379,16 +685,17 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)</div><div class='ctx'> 	mes_set_hw_res_pkt.vmid_mask_gfxhub = mes-&gt;vmid_mask_gfxhub;</div><div class='ctx'> 	mes_set_hw_res_pkt.gds_size = adev-&gt;gds.gds_size;</div><div class='ctx'> 	mes_set_hw_res_pkt.paging_vmid = 0;</div><div class='del'>-	mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes-&gt;sch_ctx_gpu_addr;</div><div class='add'>+	mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes-&gt;sch_ctx_gpu_addr[0];</div><div class='ctx'> 	mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =</div><div class='del'>-		mes-&gt;query_status_fence_gpu_addr;</div><div class='add'>+		mes-&gt;query_status_fence_gpu_addr[0];</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_COMPUTE_PIPES; i++)</div><div class='ctx'> 		mes_set_hw_res_pkt.compute_hqd_mask[i] =</div><div class='ctx'> 			mes-&gt;compute_hqd_mask[i];</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_GFX_PIPES; i++)</div><div class='del'>-		mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes-&gt;gfx_hqd_mask[i];</div><div class='add'>+		mes_set_hw_res_pkt.gfx_hqd_mask[i] =</div><div class='add'>+			mes-&gt;gfx_hqd_mask[i];</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_SDMA_PIPES; i++)</div><div class='ctx'> 		mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes-&gt;sdma_hqd_mask[i];</div><div class='hunk'>@@ -411,25 +718,125 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)</div><div class='ctx'> 	mes_set_hw_res_pkt.enable_reg_active_poll = 1;</div><div class='ctx'> 	mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;</div><div class='ctx'> 	mes_set_hw_res_pkt.oversubscription_timer = 50;</div><div class='del'>-	mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;</div><div class='del'>-	mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes-&gt;event_log_gpu_addr;</div><div class='add'>+	if ((mes-&gt;adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 0x7f)</div><div class='add'>+		mes_set_hw_res_pkt.enable_lr_compute_wa = 1;</div><div class='add'>+	else</div><div class='add'>+		dev_info_once(mes-&gt;adev-&gt;dev,</div><div class='add'>+			      "MES FW version must be &gt;= 0x7f to enable LR compute workaround.\n");</div><div class='add'>+</div><div class='add'>+	if (amdgpu_mes_log_enable) {</div><div class='add'>+		mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;</div><div class='add'>+		mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =</div><div class='add'>+					mes-&gt;event_log_gpu_addr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE)</div><div class='add'>+		mes_set_hw_res_pkt.limit_single_process = 1;</div><div class='ctx'> </div><div class='ctx'> 	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='ctx'> 			&amp;mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),</div><div class='ctx'> 			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)</div><div class='add'>+{</div><div class='add'>+	union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;</div><div class='add'>+	memset(&amp;mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));</div><div class='add'>+</div><div class='add'>+	mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;</div><div class='add'>+	mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+	mes_set_hw_res_pkt.enable_mes_info_ctx = 1;</div><div class='add'>+</div><div class='add'>+	mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes-&gt;resource_1_gpu_addr[0];</div><div class='add'>+	if (amdgpu_sriov_is_mes_info_enable(mes-&gt;adev)) {</div><div class='add'>+		mes_set_hw_res_pkt.mes_info_ctx_mc_addr =</div><div class='add'>+			mes-&gt;resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+		mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			&amp;mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),</div><div class='add'>+			offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,</div><div class='add'>+				    struct mes_reset_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__RESET mes_reset_queue_pkt;</div><div class='add'>+</div><div class='add'>+	if (input-&gt;use_mmio)</div><div class='add'>+		return mes_v11_0_reset_queue_mmio(mes, input-&gt;queue_type,</div><div class='add'>+						  input-&gt;me_id, input-&gt;pipe_id,</div><div class='add'>+						  input-&gt;queue_id, input-&gt;vmid);</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;</div><div class='add'>+	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+</div><div class='add'>+	if (input-&gt;legacy_gfx) {</div><div class='add'>+		mes_reset_queue_pkt.reset_legacy_gfx = 1;</div><div class='add'>+		mes_reset_queue_pkt.pipe_id_lp = input-&gt;pipe_id;</div><div class='add'>+		mes_reset_queue_pkt.queue_id_lp = input-&gt;queue_id;</div><div class='add'>+		mes_reset_queue_pkt.mqd_mc_addr_lp = input-&gt;mqd_addr;</div><div class='add'>+		mes_reset_queue_pkt.doorbell_offset_lp = input-&gt;doorbell_offset;</div><div class='add'>+		mes_reset_queue_pkt.wptr_addr_lp = input-&gt;wptr_addr;</div><div class='add'>+		mes_reset_queue_pkt.vmid_id_lp = input-&gt;vmid;</div><div class='add'>+	} else {</div><div class='add'>+		mes_reset_queue_pkt.reset_queue_only = 1;</div><div class='add'>+		mes_reset_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			&amp;mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__RESET, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes,</div><div class='add'>+						  struct mes_detect_and_reset_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__RESET mes_reset_queue_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;</div><div class='add'>+	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+	mes_reset_queue_pkt.doorbell_offset_addr =</div><div class='add'>+		mes-&gt;hung_queue_db_array_gpu_addr;</div><div class='add'>+</div><div class='add'>+	if (input-&gt;detect_only)</div><div class='add'>+		mes_reset_queue_pkt.hang_detect_only = 1;</div><div class='add'>+	else</div><div class='add'>+		mes_reset_queue_pkt.hang_detect_then_reset = 1;</div><div class='add'>+</div><div class='add'>+	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			&amp;mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__RESET, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_mes_funcs mes_v11_0_funcs = {</div><div class='ctx'> 	.add_hw_queue = mes_v11_0_add_hw_queue,</div><div class='ctx'> 	.remove_hw_queue = mes_v11_0_remove_hw_queue,</div><div class='add'>+	.map_legacy_queue = mes_v11_0_map_legacy_queue,</div><div class='ctx'> 	.unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,</div><div class='ctx'> 	.suspend_gang = mes_v11_0_suspend_gang,</div><div class='ctx'> 	.resume_gang = mes_v11_0_resume_gang,</div><div class='ctx'> 	.misc_op = mes_v11_0_misc_op,</div><div class='add'>+	.reset_hw_queue = mes_v11_0_reset_hw_queue,</div><div class='add'>+	.detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,</div><div class='del'>-					   enum admgpu_mes_pipe pipe)</div><div class='add'>+					   enum amdgpu_mes_pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='hunk'>@@ -464,7 +871,7 @@ static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,</div><div class='del'>-						enum admgpu_mes_pipe pipe)</div><div class='add'>+						enum amdgpu_mes_pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='hunk'>@@ -505,7 +912,7 @@ static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,</div><div class='del'>-					 enum admgpu_mes_pipe pipe)</div><div class='add'>+					 enum amdgpu_mes_pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.data_fw_obj[pipe],</div><div class='ctx'> 			      &amp;adev-&gt;mes.data_fw_gpu_addr[pipe],</div><div class='hunk'>@@ -516,12 +923,48 @@ static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,</div><div class='ctx'> 			      (void **)&amp;adev-&gt;mes.ucode_fw_ptr[pipe]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	/* return early if we have already fetched these */</div><div class='add'>+	if (adev-&gt;mes.sched_version &amp;&amp; adev-&gt;mes.kiq_version)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* get MES scheduler/KIQ versions */</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='add'>+		soc21_grbm_select(adev, 3, pipe, 0, 0);</div><div class='add'>+</div><div class='add'>+		if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='add'>+			adev-&gt;mes.sched_version =</div><div class='add'>+				RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);</div><div class='add'>+		else if (pipe == AMDGPU_MES_KIQ_PIPE &amp;&amp; adev-&gt;enable_mes_kiq)</div><div class='add'>+			adev-&gt;mes.kiq_version =</div><div class='add'>+				RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t ucode_addr;</div><div class='ctx'> 	uint32_t pipe, data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='add'>+		if (amdgpu_mes_log_enable) {</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,</div><div class='add'>+				lower_32_bits(adev-&gt;mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,</div><div class='add'>+				upper_32_bits(adev-&gt;mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));</div><div class='add'>+			dev_info(adev-&gt;dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",</div><div class='add'>+				RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),</div><div class='add'>+				RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);</div><div class='ctx'> 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);</div><div class='ctx'> 		data = REG_SET_FIELD(data, CP_MES_CNTL,</div><div class='hunk'>@@ -554,7 +997,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 		if (amdgpu_emu_mode)</div><div class='ctx'> 			msleep(100);</div><div class='ctx'> 		else</div><div class='del'>-			udelay(50);</div><div class='add'>+			udelay(500);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);</div><div class='ctx'> 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);</div><div class='hunk'>@@ -571,7 +1014,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> </div><div class='ctx'> /* This function is for backdoor MES firmware */</div><div class='ctx'> static int mes_v11_0_load_microcode(struct amdgpu_device *adev,</div><div class='del'>-				    enum admgpu_mes_pipe pipe, bool prime_icache)</div><div class='add'>+				    enum amdgpu_mes_pipe pipe, bool prime_icache)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	uint32_t data;</div><div class='hunk'>@@ -643,7 +1086,7 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,</div><div class='del'>-				      enum admgpu_mes_pipe pipe)</div><div class='add'>+				      enum amdgpu_mes_pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	u32 *eop;</div><div class='hunk'>@@ -848,13 +1291,13 @@ static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, &amp;adev-&gt;mes.ring);</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, &amp;adev-&gt;mes.ring[0]);</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_ring_test_helper(kiq_ring);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_queue_init(struct amdgpu_device *adev,</div><div class='del'>-				enum admgpu_mes_pipe pipe)</div><div class='add'>+				enum amdgpu_mes_pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r;</div><div class='hunk'>@@ -862,7 +1305,7 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev,</div><div class='ctx'> 	if (pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='ctx'> 		ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='ctx'> 	else if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='del'>-		ring = &amp;adev-&gt;mes.ring;</div><div class='add'>+		ring = &amp;adev-&gt;mes.ring[0];</div><div class='ctx'> 	else</div><div class='ctx'> 		BUG();</div><div class='ctx'> </div><div class='hunk'>@@ -885,18 +1328,6 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev,</div><div class='ctx'> 		mes_v11_0_queue_init_register(ring);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* get MES scheduler/KIQ versions */</div><div class='del'>-	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-	soc21_grbm_select(adev, 3, pipe, 0, 0);</div><div class='del'>-</div><div class='del'>-	if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='del'>-		adev-&gt;mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);</div><div class='del'>-	else if (pipe == AMDGPU_MES_KIQ_PIPE &amp;&amp; adev-&gt;enable_mes_kiq)</div><div class='del'>-		adev-&gt;mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);</div><div class='del'>-</div><div class='del'>-	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -904,7 +1335,7 @@ static int mes_v11_0_ring_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> </div><div class='del'>-	ring = &amp;adev-&gt;mes.ring;</div><div class='add'>+	ring = &amp;adev-&gt;mes.ring[0];</div><div class='ctx'> </div><div class='ctx'> 	ring-&gt;funcs = &amp;mes_v11_0_ring_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -949,7 +1380,7 @@ static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,</div><div class='del'>-				 enum admgpu_mes_pipe pipe)</div><div class='add'>+				 enum amdgpu_mes_pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	int r, mqd_size = sizeof(struct v11_compute_mqd);</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='hunk'>@@ -957,7 +1388,7 @@ static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,</div><div class='ctx'> 	if (pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='ctx'> 		ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='ctx'> 	else if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='del'>-		ring = &amp;adev-&gt;mes.ring;</div><div class='add'>+		ring = &amp;adev-&gt;mes.ring[0];</div><div class='ctx'> 	else</div><div class='ctx'> 		BUG();</div><div class='ctx'> </div><div class='hunk'>@@ -987,15 +1418,17 @@ static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_sw_init(void *handle)</div><div class='add'>+static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int pipe, r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int pipe, r, bo_size;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mes.funcs = &amp;mes_v11_0_funcs;</div><div class='ctx'> 	adev-&gt;mes.kiq_hw_init = &amp;mes_v11_0_kiq_hw_init;</div><div class='ctx'> 	adev-&gt;mes.kiq_hw_fini = &amp;mes_v11_0_kiq_hw_fini;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_mes_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -1023,16 +1456,33 @@ static int mes_v11_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	bo_size = AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	if (amdgpu_sriov_is_mes_info_enable(adev))</div><div class='add'>+		bo_size += MES11_HW_RESOURCE_1_SIZE;</div><div class='add'>+</div><div class='add'>+	/* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/</div><div class='add'>+	r = amdgpu_bo_create_kernel(adev,</div><div class='add'>+				    bo_size,</div><div class='add'>+				    PAGE_SIZE,</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				    &amp;adev-&gt;mes.resource_1[0],</div><div class='add'>+				    &amp;adev-&gt;mes.resource_1_gpu_addr[0],</div><div class='add'>+				    &amp;adev-&gt;mes.resource_1_addr[0]);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create mes resource_1 bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_sw_fini(void *handle)</div><div class='add'>+static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int pipe;</div><div class='ctx'> </div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='del'>-	amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.resource_1[0], &amp;adev-&gt;mes.resource_1_gpu_addr[0],</div><div class='add'>+			      &amp;adev-&gt;mes.resource_1_addr[0]);</div><div class='ctx'> </div><div class='ctx'> 	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='ctx'> 		kfree(adev-&gt;mes.mqd_backup[pipe]);</div><div class='hunk'>@@ -1047,12 +1497,12 @@ static int mes_v11_0_sw_fini(void *handle)</div><div class='ctx'> 			      &amp;adev-&gt;gfx.kiq[0].ring.mqd_gpu_addr,</div><div class='ctx'> 			      &amp;adev-&gt;gfx.kiq[0].ring.mqd_ptr);</div><div class='ctx'> </div><div class='del'>-	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.ring.mqd_obj,</div><div class='del'>-			      &amp;adev-&gt;mes.ring.mqd_gpu_addr,</div><div class='del'>-			      &amp;adev-&gt;mes.ring.mqd_ptr);</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.ring[0].mqd_obj,</div><div class='add'>+			      &amp;adev-&gt;mes.ring[0].mqd_gpu_addr,</div><div class='add'>+			      &amp;adev-&gt;mes.ring[0].mqd_ptr);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_fini(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='del'>-	amdgpu_ring_fini(&amp;adev-&gt;mes.ring);</div><div class='add'>+	amdgpu_ring_fini(&amp;adev-&gt;mes.ring[0]);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='ctx'> 		mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);</div><div class='hunk'>@@ -1107,9 +1557,7 @@ static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);</div><div class='ctx'> 	tmp &amp;= 0xffffff00;</div><div class='ctx'> 	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='del'>-	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);</div><div class='del'>-	tmp |= 0x80;</div><div class='del'>-	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1125,6 +1573,7 @@ static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)</div><div class='ctx'> static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r = 0;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='ctx'> </div><div class='hunk'>@@ -1144,24 +1593,43 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	mes_v11_0_enable(adev, true);</div><div class='ctx'> </div><div class='add'>+	mes_v11_0_get_fw_version(adev);</div><div class='add'>+</div><div class='ctx'> 	mes_v11_0_kiq_setting(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='ctx'> </div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);</div><div class='add'>+	if (unlikely(!ip_block)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to get MES handle\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto failure;</div><div class='ctx'> </div><div class='add'>+	if ((adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 0x47)</div><div class='add'>+		adev-&gt;mes.enable_legacy_queue_map = true;</div><div class='add'>+	else</div><div class='add'>+		adev-&gt;mes.enable_legacy_queue_map = false;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;mes.enable_legacy_queue_map) {</div><div class='add'>+		r = mes_v11_0_hw_init(ip_block);</div><div class='add'>+		if (r)</div><div class='add'>+			goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> </div><div class='ctx'> failure:</div><div class='del'>-	mes_v11_0_hw_fini(adev);</div><div class='add'>+	mes_v11_0_hw_fini(ip_block);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (adev-&gt;mes.ring.sched.ready) {</div><div class='del'>-		mes_v11_0_kiq_dequeue(&amp;adev-&gt;mes.ring);</div><div class='del'>-		adev-&gt;mes.ring.sched.ready = false;</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready) {</div><div class='add'>+		mes_v11_0_kiq_dequeue(&amp;adev-&gt;mes.ring[0]);</div><div class='add'>+		adev-&gt;mes.ring[0].sched.ready = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='hunk'>@@ -1174,10 +1642,13 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_hw_init(void *handle)</div><div class='add'>+static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready)</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;enable_mes_kiq) {</div><div class='ctx'> 		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='hunk'>@@ -1200,61 +1671,63 @@ static int mes_v11_0_hw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto failure;</div><div class='ctx'> </div><div class='add'>+	if ((adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 0x50) {</div><div class='add'>+		r = mes_v11_0_set_hw_resources_1(&amp;adev-&gt;mes);</div><div class='add'>+		if (r) {</div><div class='add'>+			DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);</div><div class='add'>+			goto failure;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	r = mes_v11_0_query_sched_status(&amp;adev-&gt;mes);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("MES is busy\n");</div><div class='ctx'> 		goto failure;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_mes_update_enforce_isolation(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failure;</div><div class='add'>+</div><div class='add'>+out:</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Disable KIQ ring usage from the driver once MES is enabled.</div><div class='ctx'> 	 * MES uses KIQ ring exclusively so driver cannot access KIQ ring</div><div class='ctx'> 	 * with MES enabled.</div><div class='ctx'> 	 */</div><div class='ctx'> 	adev-&gt;gfx.kiq[0].ring.sched.ready = false;</div><div class='del'>-	adev-&gt;mes.ring.sched.ready = true;</div><div class='add'>+	adev-&gt;mes.ring[0].sched.ready = true;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> failure:</div><div class='del'>-	mes_v11_0_hw_fini(adev);</div><div class='add'>+	mes_v11_0_hw_fini(ip_block);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_hw_fini(void *handle)</div><div class='add'>+static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_suspend(void *handle)</div><div class='add'>+static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_mes_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return mes_v11_0_hw_fini(adev);</div><div class='add'>+	return mes_v11_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_resume(void *handle)</div><div class='add'>+static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	r = mes_v11_0_hw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	return amdgpu_mes_resume(adev);</div><div class='add'>+	return mes_v11_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_early_init(void *handle)</div><div class='add'>+static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int pipe, r;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE;</div><div class='add'>+	adev-&gt;mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET;</div><div class='add'>+</div><div class='ctx'> 	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='ctx'> 		if (!adev-&gt;enable_mes_kiq &amp;&amp; pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -1266,22 +1739,10 @@ static int mes_v11_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mes_v11_0_late_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	/* it's only intended for use in mes_self_test case, not for s0ix and reset */</div><div class='del'>-	if (!amdgpu_in_reset(adev) &amp;&amp; !adev-&gt;in_s0ix &amp;&amp; !adev-&gt;in_suspend &amp;&amp;</div><div class='del'>-	    (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3)))</div><div class='del'>-		amdgpu_mes_self_test(adev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct amd_ip_funcs mes_v11_0_ip_funcs = {</div><div class='ctx'> 	.name = "mes_v11_0",</div><div class='ctx'> 	.early_init = mes_v11_0_early_init,</div><div class='del'>-	.late_init = mes_v11_0_late_init,</div><div class='add'>+	.late_init = NULL,</div><div class='ctx'> 	.sw_init = mes_v11_0_sw_init,</div><div class='ctx'> 	.sw_fini = mes_v11_0_sw_fini,</div><div class='ctx'> 	.hw_init = mes_v11_0_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c<br/>new file mode 100644<br/>index 000000000000..744e95d3984a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mes_v12_0.c</a></div><div class='hunk'>@@ -0,0 +1,1942 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "gfx_v12_0.h"</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "soc21.h"</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "gc/gc_11_0_0_default.h"</div><div class='add'>+#include "v12_structs.h"</div><div class='add'>+#include "mes_v12_api_def.h"</div><div class='add'>+</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block);</div><div class='add'>+static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block);</div><div class='add'>+static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);</div><div class='add'>+static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+#define MES_EOP_SIZE   2048</div><div class='add'>+</div><div class='add'>+#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */</div><div class='add'>+#define MES12_HUNG_HQD_INFO_OFFSET	4</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='add'>+			     ring-&gt;wptr);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr);</div><div class='add'>+	} else {</div><div class='add'>+		BUG();</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	return *ring-&gt;rptr_cpu_addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u64 wptr;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell)</div><div class='add'>+		wptr = atomic64_read((atomic64_t *)ring-&gt;wptr_cpu_addr);</div><div class='add'>+	else</div><div class='add'>+		BUG();</div><div class='add'>+	return wptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_MES,</div><div class='add'>+	.align_mask = 1,</div><div class='add'>+	.nop = 0,</div><div class='add'>+	.support_64bit_ptrs = true,</div><div class='add'>+	.get_rptr = mes_v12_0_ring_get_rptr,</div><div class='add'>+	.get_wptr = mes_v12_0_ring_get_wptr,</div><div class='add'>+	.set_wptr = mes_v12_0_ring_set_wptr,</div><div class='add'>+	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *mes_v12_0_opcodes[] = {</div><div class='add'>+	"SET_HW_RSRC",</div><div class='add'>+	"SET_SCHEDULING_CONFIG",</div><div class='add'>+	"ADD_QUEUE",</div><div class='add'>+	"REMOVE_QUEUE",</div><div class='add'>+	"PERFORM_YIELD",</div><div class='add'>+	"SET_GANG_PRIORITY_LEVEL",</div><div class='add'>+	"SUSPEND",</div><div class='add'>+	"RESUME",</div><div class='add'>+	"RESET",</div><div class='add'>+	"SET_LOG_BUFFER",</div><div class='add'>+	"CHANGE_GANG_PRORITY",</div><div class='add'>+	"QUERY_SCHEDULER_STATUS",</div><div class='add'>+	"unused",</div><div class='add'>+	"SET_DEBUG_VMID",</div><div class='add'>+	"MISC",</div><div class='add'>+	"UPDATE_ROOT_PAGE_TABLE",</div><div class='add'>+	"AMD_LOG",</div><div class='add'>+	"SET_SE_MODE",</div><div class='add'>+	"SET_GANG_SUBMIT",</div><div class='add'>+	"SET_HW_RSRC_1",</div><div class='add'>+	"INVALIDATE_TLBS",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *mes_v12_0_misc_opcodes[] = {</div><div class='add'>+	"WRITE_REG",</div><div class='add'>+	"INV_GART",</div><div class='add'>+	"QUERY_STATUS",</div><div class='add'>+	"READ_REG",</div><div class='add'>+	"WAIT_REG_MEM",</div><div class='add'>+	"SET_SHADER_DEBUGGER",</div><div class='add'>+	"NOTIFY_WORK_ON_UNMAPPED_QUEUE",</div><div class='add'>+	"NOTIFY_TO_UNMAP_PROCESSES",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)</div><div class='add'>+{</div><div class='add'>+	const char *op_str = NULL;</div><div class='add'>+</div><div class='add'>+	if (x_pkt-&gt;header.opcode &lt; ARRAY_SIZE(mes_v12_0_opcodes))</div><div class='add'>+		op_str = mes_v12_0_opcodes[x_pkt-&gt;header.opcode];</div><div class='add'>+</div><div class='add'>+	return op_str;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)</div><div class='add'>+{</div><div class='add'>+	const char *op_str = NULL;</div><div class='add'>+</div><div class='add'>+	if ((x_pkt-&gt;header.opcode == MES_SCH_API_MISC) &amp;&amp;</div><div class='add'>+	    (x_pkt-&gt;opcode &lt; ARRAY_SIZE(mes_v12_0_misc_opcodes)))</div><div class='add'>+		op_str = mes_v12_0_misc_opcodes[x_pkt-&gt;opcode];</div><div class='add'>+</div><div class='add'>+	return op_str;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,</div><div class='add'>+					    int pipe, void *pkt, int size,</div><div class='add'>+					    int api_status_off)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__QUERY_MES_STATUS mes_status_pkt;</div><div class='add'>+	signed long timeout = 2100000; /* 2100 ms */</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring = &amp;mes-&gt;ring[pipe];</div><div class='add'>+	spinlock_t *ring_lock = &amp;mes-&gt;ring_lock[pipe];</div><div class='add'>+	struct MES_API_STATUS *api_status;</div><div class='add'>+	union MESAPI__MISC *x_pkt = pkt;</div><div class='add'>+	const char *op_str, *misc_op_str;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u64 status_gpu_addr;</div><div class='add'>+	u32 seq, status_offset;</div><div class='add'>+	u64 *status_ptr;</div><div class='add'>+	signed long r;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (x_pkt-&gt;header.opcode &gt;= MES_SCH_API_MAX)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_emu_mode) {</div><div class='add'>+		timeout *= 100;</div><div class='add'>+	} else if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */</div><div class='add'>+		timeout = 15 * 600 * 1000;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_device_wb_get(adev, &amp;status_offset);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	status_gpu_addr = adev-&gt;wb.gpu_addr + (status_offset * 4);</div><div class='add'>+	status_ptr = (u64 *)&amp;adev-&gt;wb.wb[status_offset];</div><div class='add'>+	*status_ptr = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(ring_lock, flags);</div><div class='add'>+	r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_unlock_free;</div><div class='add'>+</div><div class='add'>+	seq = ++ring-&gt;fence_drv.sync_seq;</div><div class='add'>+	r = amdgpu_fence_wait_polling(ring,</div><div class='add'>+				      seq - ring-&gt;fence_drv.num_fences_mask,</div><div class='add'>+				      timeout);</div><div class='add'>+	if (r &lt; 1)</div><div class='add'>+		goto error_undo;</div><div class='add'>+</div><div class='add'>+	api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);</div><div class='add'>+	api_status-&gt;api_completion_fence_addr = status_gpu_addr;</div><div class='add'>+	api_status-&gt;api_completion_fence_value = 1;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write_multiple(ring, pkt, size / 4);</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_status_pkt, 0, sizeof(mes_status_pkt));</div><div class='add'>+	mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;</div><div class='add'>+	mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+	mes_status_pkt.api_status.api_completion_fence_addr =</div><div class='add'>+		ring-&gt;fence_drv.gpu_addr;</div><div class='add'>+	mes_status_pkt.api_status.api_completion_fence_value = seq;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write_multiple(ring, &amp;mes_status_pkt,</div><div class='add'>+				   sizeof(mes_status_pkt) / 4);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_commit(ring);</div><div class='add'>+	spin_unlock_irqrestore(ring_lock, flags);</div><div class='add'>+</div><div class='add'>+	op_str = mes_v12_0_get_op_string(x_pkt);</div><div class='add'>+	misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);</div><div class='add'>+</div><div class='add'>+	if (misc_op_str)</div><div class='add'>+		dev_dbg(adev-&gt;dev, "MES(%d) msg=%s (%s) was emitted\n",</div><div class='add'>+			pipe, op_str, misc_op_str);</div><div class='add'>+	else if (op_str)</div><div class='add'>+		dev_dbg(adev-&gt;dev, "MES(%d) msg=%s was emitted\n",</div><div class='add'>+			pipe, op_str);</div><div class='add'>+	else</div><div class='add'>+		dev_dbg(adev-&gt;dev, "MES(%d) msg=%d was emitted\n",</div><div class='add'>+			pipe, x_pkt-&gt;header.opcode);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_fence_wait_polling(ring, seq, timeout);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success).</div><div class='add'>+	 * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information.</div><div class='add'>+	 */</div><div class='add'>+	if (r &lt; 1 || !(lower_32_bits(*status_ptr))) {</div><div class='add'>+</div><div class='add'>+		if (misc_op_str)</div><div class='add'>+			dev_err(adev-&gt;dev, "MES(%d) failed to respond to msg=%s (%s)\n",</div><div class='add'>+				pipe, op_str, misc_op_str);</div><div class='add'>+		else if (op_str)</div><div class='add'>+			dev_err(adev-&gt;dev, "MES(%d) failed to respond to msg=%s\n",</div><div class='add'>+				pipe, op_str);</div><div class='add'>+		else</div><div class='add'>+			dev_err(adev-&gt;dev, "MES(%d) failed to respond to msg=%d\n",</div><div class='add'>+				pipe, x_pkt-&gt;header.opcode);</div><div class='add'>+</div><div class='add'>+		while (halt_if_hws_hang)</div><div class='add'>+			schedule();</div><div class='add'>+</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+		goto error_wb_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_device_wb_free(adev, status_offset);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_undo:</div><div class='add'>+	dev_err(adev-&gt;dev, "MES ring buffer is full.\n");</div><div class='add'>+	amdgpu_ring_undo(ring);</div><div class='add'>+</div><div class='add'>+error_unlock_free:</div><div class='add'>+	spin_unlock_irqrestore(ring_lock, flags);</div><div class='add'>+</div><div class='add'>+error_wb_free:</div><div class='add'>+	amdgpu_device_wb_free(adev, status_offset);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int convert_to_mes_queue_type(int queue_type)</div><div class='add'>+{</div><div class='add'>+	if (queue_type == AMDGPU_RING_TYPE_GFX)</div><div class='add'>+		return MES_QUEUE_TYPE_GFX;</div><div class='add'>+	else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)</div><div class='add'>+		return MES_QUEUE_TYPE_COMPUTE;</div><div class='add'>+	else if (queue_type == AMDGPU_RING_TYPE_SDMA)</div><div class='add'>+		return MES_QUEUE_TYPE_SDMA;</div><div class='add'>+	else if (queue_type == AMDGPU_RING_TYPE_MES)</div><div class='add'>+		return MES_QUEUE_TYPE_SCHQ;</div><div class='add'>+	else</div><div class='add'>+		BUG();</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int convert_to_mes_priority_level(int priority_level)</div><div class='add'>+{</div><div class='add'>+	switch (priority_level) {</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_LOW:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_LOW;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_NORMAL:</div><div class='add'>+	default:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_NORMAL;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_MEDIUM;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_HIGH:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_HIGH;</div><div class='add'>+	case AMDGPU_MES_PRIORITY_LEVEL_REALTIME:</div><div class='add'>+		return AMD_PRIORITY_LEVEL_REALTIME;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,</div><div class='add'>+				  struct mes_add_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	union MESAPI__ADD_QUEUE mes_add_queue_pkt;</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_GFXHUB(0)];</div><div class='add'>+	uint32_t vm_cntx_cntl = hub-&gt;vm_cntx_cntl;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;</div><div class='add'>+	mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.process_id = input-&gt;process_id;</div><div class='add'>+	mes_add_queue_pkt.page_table_base_addr = input-&gt;page_table_base_addr;</div><div class='add'>+	mes_add_queue_pkt.process_va_start = input-&gt;process_va_start;</div><div class='add'>+	mes_add_queue_pkt.process_va_end = input-&gt;process_va_end;</div><div class='add'>+	mes_add_queue_pkt.process_quantum = input-&gt;process_quantum;</div><div class='add'>+	mes_add_queue_pkt.process_context_addr = input-&gt;process_context_addr;</div><div class='add'>+	mes_add_queue_pkt.gang_quantum = input-&gt;gang_quantum;</div><div class='add'>+	mes_add_queue_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='add'>+	mes_add_queue_pkt.inprocess_gang_priority =</div><div class='add'>+		convert_to_mes_priority_level(input-&gt;inprocess_gang_priority);</div><div class='add'>+	mes_add_queue_pkt.gang_global_priority_level =</div><div class='add'>+		convert_to_mes_priority_level(input-&gt;gang_global_priority_level);</div><div class='add'>+	mes_add_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	mes_add_queue_pkt.mqd_addr = input-&gt;mqd_addr;</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.wptr_addr = input-&gt;wptr_mc_addr;</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+	mes_add_queue_pkt.paging = input-&gt;paging;</div><div class='add'>+	mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;</div><div class='add'>+	mes_add_queue_pkt.gws_base = input-&gt;gws_base;</div><div class='add'>+	mes_add_queue_pkt.gws_size = input-&gt;gws_size;</div><div class='add'>+	mes_add_queue_pkt.trap_handler_addr = input-&gt;tba_addr;</div><div class='add'>+	mes_add_queue_pkt.tma_addr = input-&gt;tma_addr;</div><div class='add'>+	mes_add_queue_pkt.trap_en = input-&gt;trap_en;</div><div class='add'>+	mes_add_queue_pkt.skip_process_ctx_clear = input-&gt;skip_process_ctx_clear;</div><div class='add'>+	mes_add_queue_pkt.is_kfd_process = input-&gt;is_kfd_process;</div><div class='add'>+</div><div class='add'>+	/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */</div><div class='add'>+	mes_add_queue_pkt.is_aql_queue = input-&gt;is_aql_queue;</div><div class='add'>+	mes_add_queue_pkt.gds_size = input-&gt;queue_size;</div><div class='add'>+</div><div class='add'>+	/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */</div><div class='add'>+	mes_add_queue_pkt.is_aql_queue = input-&gt;is_aql_queue;</div><div class='add'>+	mes_add_queue_pkt.gds_size = input-&gt;queue_size;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			AMDGPU_MES_SCHED_PIPE,</div><div class='add'>+			&amp;mes_add_queue_pkt, sizeof(mes_add_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__ADD_QUEUE, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,</div><div class='add'>+				     struct mes_remove_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;</div><div class='add'>+	uint32_t mes_rev = mes-&gt;sched_version &amp; AMDGPU_MES_VERSION_MASK;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;</div><div class='add'>+	mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_remove_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	mes_remove_queue_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='add'>+</div><div class='add'>+	if (mes_rev &gt;= 0x5a)</div><div class='add'>+		mes_remove_queue_pkt.remove_queue_after_reset = input-&gt;remove_queue_after_reset;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes,</div><div class='add'>+			AMDGPU_MES_SCHED_PIPE,</div><div class='add'>+			&amp;mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__REMOVE_QUEUE, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int gfx_v12_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='add'>+				      bool req)</div><div class='add'>+{</div><div class='add'>+	u32 i, tmp, val;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		/* Request with MeId=2, PipeId=0 */</div><div class='add'>+		tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);</div><div class='add'>+</div><div class='add'>+		val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);</div><div class='add'>+		if (req) {</div><div class='add'>+			if (val == tmp)</div><div class='add'>+				break;</div><div class='add'>+		} else {</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,</div><div class='add'>+					    REQUEST, 1);</div><div class='add'>+</div><div class='add'>+			/* unlocked or locked by firmware */</div><div class='add'>+			if (val != tmp)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,</div><div class='add'>+				      uint32_t me_id, uint32_t pipe_id,</div><div class='add'>+				      uint32_t queue_id, uint32_t vmid)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	uint32_t value, reg;</div><div class='add'>+	int i, r = 0;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	if (queue_type == AMDGPU_RING_TYPE_GFX) {</div><div class='add'>+		dev_info(adev-&gt;dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n",</div><div class='add'>+			 me_id, pipe_id, queue_id, vmid);</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='add'>+		gfx_v12_0_request_gfx_index_mutex(adev, true);</div><div class='add'>+		/* all se allow writes */</div><div class='add'>+		WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX,</div><div class='add'>+			     (uint32_t)(0x1 &lt;&lt; GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));</div><div class='add'>+		value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 &lt;&lt; vmid);</div><div class='add'>+		if (pipe_id == 0)</div><div class='add'>+			value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 &lt;&lt; queue_id);</div><div class='add'>+		else</div><div class='add'>+			value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 &lt;&lt; queue_id);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_VMID_RESET, value);</div><div class='add'>+		gfx_v12_0_request_gfx_index_mutex(adev, false);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;gfx.reset_sem_mutex);</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on gfx hqd deactivate\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	} else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {</div><div class='add'>+		dev_info(adev-&gt;dev, "reset compute queue (%d:%d:%d)\n",</div><div class='add'>+			 me_id, pipe_id, queue_id);</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);</div><div class='add'>+		WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);</div><div class='add'>+</div><div class='add'>+		/* wait till dequeue take effects */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on hqd deactivate\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	} else if (queue_type == AMDGPU_RING_TYPE_SDMA) {</div><div class='add'>+		dev_info(adev-&gt;dev, "reset sdma queue (%d:%d:%d)\n",</div><div class='add'>+			 me_id, pipe_id, queue_id);</div><div class='add'>+		switch (me_id) {</div><div class='add'>+		case 1:</div><div class='add'>+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);</div><div class='add'>+			break;</div><div class='add'>+		case 0:</div><div class='add'>+		default:</div><div class='add'>+			reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		value = 1 &lt;&lt; queue_id;</div><div class='add'>+		WREG32(reg, value);</div><div class='add'>+		/* wait for queue reset done */</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32(reg) &amp; value))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+		if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to wait on sdma queue reset done\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,</div><div class='add'>+				      struct mes_map_legacy_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__ADD_QUEUE mes_add_queue_pkt;</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;</div><div class='add'>+	mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_add_queue_pkt.pipe_id = input-&gt;pipe_id;</div><div class='add'>+	mes_add_queue_pkt.queue_id = input-&gt;queue_id;</div><div class='add'>+	mes_add_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	mes_add_queue_pkt.mqd_addr = input-&gt;mqd_addr;</div><div class='add'>+	mes_add_queue_pkt.wptr_addr = input-&gt;wptr_addr;</div><div class='add'>+	mes_add_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+	mes_add_queue_pkt.map_legacy_kq = 1;</div><div class='add'>+</div><div class='add'>+	if (mes-&gt;adev-&gt;enable_uni_mes)</div><div class='add'>+		pipe = AMDGPU_MES_KIQ_PIPE;</div><div class='add'>+	else</div><div class='add'>+		pipe = AMDGPU_MES_SCHED_PIPE;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;mes_add_queue_pkt, sizeof(mes_add_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__ADD_QUEUE, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,</div><div class='add'>+			struct mes_unmap_legacy_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;</div><div class='add'>+	mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_remove_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	mes_remove_queue_pkt.gang_context_addr = 0;</div><div class='add'>+</div><div class='add'>+	mes_remove_queue_pkt.pipe_id = input-&gt;pipe_id;</div><div class='add'>+	mes_remove_queue_pkt.queue_id = input-&gt;queue_id;</div><div class='add'>+</div><div class='add'>+	if (input-&gt;action == PREEMPT_QUEUES_NO_UNMAP) {</div><div class='add'>+		mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;</div><div class='add'>+		mes_remove_queue_pkt.tf_addr = input-&gt;trail_fence_addr;</div><div class='add'>+		mes_remove_queue_pkt.tf_data =</div><div class='add'>+			lower_32_bits(input-&gt;trail_fence_data);</div><div class='add'>+	} else {</div><div class='add'>+		mes_remove_queue_pkt.unmap_legacy_queue = 1;</div><div class='add'>+		mes_remove_queue_pkt.queue_type =</div><div class='add'>+			convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mes-&gt;adev-&gt;enable_uni_mes)</div><div class='add'>+		pipe = AMDGPU_MES_KIQ_PIPE;</div><div class='add'>+	else</div><div class='add'>+		pipe = AMDGPU_MES_SCHED_PIPE;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__REMOVE_QUEUE, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,</div><div class='add'>+				  struct mes_suspend_gang_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__SUSPEND mes_suspend_gang_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt));</div><div class='add'>+</div><div class='add'>+	mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND;</div><div class='add'>+	mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_suspend_gang_pkt.suspend_all_gangs = input-&gt;suspend_all_gangs;</div><div class='add'>+	mes_suspend_gang_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='add'>+	mes_suspend_gang_pkt.suspend_fence_addr = input-&gt;suspend_fence_addr;</div><div class='add'>+	mes_suspend_gang_pkt.suspend_fence_value = input-&gt;suspend_fence_value;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE,</div><div class='add'>+			&amp;mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt),</div><div class='add'>+			offsetof(union MESAPI__SUSPEND, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,</div><div class='add'>+				 struct mes_resume_gang_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__RESUME mes_resume_gang_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt));</div><div class='add'>+</div><div class='add'>+	mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME;</div><div class='add'>+	mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_resume_gang_pkt.resume_all_gangs = input-&gt;resume_all_gangs;</div><div class='add'>+	mes_resume_gang_pkt.gang_context_addr = input-&gt;gang_context_addr;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE,</div><div class='add'>+			&amp;mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt),</div><div class='add'>+			offsetof(union MESAPI__RESUME, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__QUERY_MES_STATUS mes_status_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_status_pkt, 0, sizeof(mes_status_pkt));</div><div class='add'>+</div><div class='add'>+	mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;</div><div class='add'>+	mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;mes_status_pkt, sizeof(mes_status_pkt),</div><div class='add'>+			offsetof(union MESAPI__QUERY_MES_STATUS, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_misc_op(struct amdgpu_mes *mes,</div><div class='add'>+			     struct mes_misc_op_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__MISC misc_pkt;</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	if (mes-&gt;adev-&gt;enable_uni_mes)</div><div class='add'>+		pipe = AMDGPU_MES_KIQ_PIPE;</div><div class='add'>+	else</div><div class='add'>+		pipe = AMDGPU_MES_SCHED_PIPE;</div><div class='add'>+</div><div class='add'>+	memset(&amp;misc_pkt, 0, sizeof(misc_pkt));</div><div class='add'>+</div><div class='add'>+	misc_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	misc_pkt.header.opcode = MES_SCH_API_MISC;</div><div class='add'>+	misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	switch (input-&gt;op) {</div><div class='add'>+	case MES_MISC_OP_READ_REG:</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__READ_REG;</div><div class='add'>+		misc_pkt.read_reg.reg_offset = input-&gt;read_reg.reg_offset;</div><div class='add'>+		misc_pkt.read_reg.buffer_addr = input-&gt;read_reg.buffer_addr;</div><div class='add'>+		break;</div><div class='add'>+	case MES_MISC_OP_WRITE_REG:</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__WRITE_REG;</div><div class='add'>+		misc_pkt.write_reg.reg_offset = input-&gt;write_reg.reg_offset;</div><div class='add'>+		misc_pkt.write_reg.reg_value = input-&gt;write_reg.reg_value;</div><div class='add'>+		break;</div><div class='add'>+	case MES_MISC_OP_WRM_REG_WAIT:</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;</div><div class='add'>+		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;</div><div class='add'>+		misc_pkt.wait_reg_mem.reference = input-&gt;wrm_reg.ref;</div><div class='add'>+		misc_pkt.wait_reg_mem.mask = input-&gt;wrm_reg.mask;</div><div class='add'>+		misc_pkt.wait_reg_mem.reg_offset1 = input-&gt;wrm_reg.reg0;</div><div class='add'>+		misc_pkt.wait_reg_mem.reg_offset2 = 0;</div><div class='add'>+		break;</div><div class='add'>+	case MES_MISC_OP_WRM_REG_WR_WAIT:</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;</div><div class='add'>+		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;</div><div class='add'>+		misc_pkt.wait_reg_mem.reference = input-&gt;wrm_reg.ref;</div><div class='add'>+		misc_pkt.wait_reg_mem.mask = input-&gt;wrm_reg.mask;</div><div class='add'>+		misc_pkt.wait_reg_mem.reg_offset1 = input-&gt;wrm_reg.reg0;</div><div class='add'>+		misc_pkt.wait_reg_mem.reg_offset2 = input-&gt;wrm_reg.reg1;</div><div class='add'>+		break;</div><div class='add'>+	case MES_MISC_OP_SET_SHADER_DEBUGGER:</div><div class='add'>+		pipe = AMDGPU_MES_SCHED_PIPE;</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;</div><div class='add'>+		misc_pkt.set_shader_debugger.process_context_addr =</div><div class='add'>+				input-&gt;set_shader_debugger.process_context_addr;</div><div class='add'>+		misc_pkt.set_shader_debugger.flags.u32all =</div><div class='add'>+				input-&gt;set_shader_debugger.flags.u32all;</div><div class='add'>+		misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =</div><div class='add'>+				input-&gt;set_shader_debugger.spi_gdbg_per_vmid_cntl;</div><div class='add'>+		memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,</div><div class='add'>+				input-&gt;set_shader_debugger.tcp_watch_cntl,</div><div class='add'>+				sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));</div><div class='add'>+		misc_pkt.set_shader_debugger.trap_en = input-&gt;set_shader_debugger.trap_en;</div><div class='add'>+		break;</div><div class='add'>+	case MES_MISC_OP_CHANGE_CONFIG:</div><div class='add'>+		misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;</div><div class='add'>+		misc_pkt.change_config.opcode =</div><div class='add'>+				MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;</div><div class='add'>+		misc_pkt.change_config.option.bits.limit_single_process =</div><div class='add'>+				input-&gt;change_config.option.limit_single_process;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		DRM_ERROR("unsupported misc op (%d) \n", input-&gt;op);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;misc_pkt, sizeof(misc_pkt),</div><div class='add'>+			offsetof(union MESAPI__MISC, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)</div><div class='add'>+{</div><div class='add'>+	union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));</div><div class='add'>+</div><div class='add'>+	mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;</div><div class='add'>+	mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;</div><div class='add'>+	mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr =</div><div class='add'>+		mes-&gt;resource_1_gpu_addr[pipe];</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),</div><div class='add'>+			offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));</div><div class='add'>+</div><div class='add'>+	mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;</div><div class='add'>+	mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	if (pipe == AMDGPU_MES_SCHED_PIPE) {</div><div class='add'>+		mes_set_hw_res_pkt.vmid_mask_mmhub = mes-&gt;vmid_mask_mmhub;</div><div class='add'>+		mes_set_hw_res_pkt.vmid_mask_gfxhub = mes-&gt;vmid_mask_gfxhub;</div><div class='add'>+		mes_set_hw_res_pkt.gds_size = adev-&gt;gds.gds_size;</div><div class='add'>+		mes_set_hw_res_pkt.paging_vmid = 0;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; MAX_COMPUTE_PIPES; i++)</div><div class='add'>+			mes_set_hw_res_pkt.compute_hqd_mask[i] =</div><div class='add'>+				mes-&gt;compute_hqd_mask[i];</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; MAX_GFX_PIPES; i++)</div><div class='add'>+			mes_set_hw_res_pkt.gfx_hqd_mask[i] =</div><div class='add'>+				mes-&gt;gfx_hqd_mask[i];</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; MAX_SDMA_PIPES; i++)</div><div class='add'>+			mes_set_hw_res_pkt.sdma_hqd_mask[i] =</div><div class='add'>+				mes-&gt;sdma_hqd_mask[i];</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; AMD_PRIORITY_NUM_LEVELS; i++)</div><div class='add'>+			mes_set_hw_res_pkt.aggregated_doorbells[i] =</div><div class='add'>+				mes-&gt;aggregated_doorbells[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =</div><div class='add'>+		mes-&gt;sch_ctx_gpu_addr[pipe];</div><div class='add'>+	mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =</div><div class='add'>+		mes-&gt;query_status_fence_gpu_addr[pipe];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 5; i++) {</div><div class='add'>+		mes_set_hw_res_pkt.gc_base[i] = adev-&gt;reg_offset[GC_HWIP][0][i];</div><div class='add'>+		mes_set_hw_res_pkt.mmhub_base[i] =</div><div class='add'>+				adev-&gt;reg_offset[MMHUB_HWIP][0][i];</div><div class='add'>+		mes_set_hw_res_pkt.osssys_base[i] =</div><div class='add'>+		adev-&gt;reg_offset[OSSSYS_HWIP][0][i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mes_set_hw_res_pkt.disable_reset = 1;</div><div class='add'>+	mes_set_hw_res_pkt.disable_mes_log = 1;</div><div class='add'>+	mes_set_hw_res_pkt.use_different_vmid_compute = 1;</div><div class='add'>+	mes_set_hw_res_pkt.enable_reg_active_poll = 1;</div><div class='add'>+	mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;</div><div class='add'>+	if ((mes-&gt;adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 0x82)</div><div class='add'>+		mes_set_hw_res_pkt.enable_lr_compute_wa = 1;</div><div class='add'>+	else</div><div class='add'>+		dev_info_once(adev-&gt;dev,</div><div class='add'>+			      "MES FW version must be &gt;= 0x82 to enable LR compute workaround.\n");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Keep oversubscribe timer for sdma . When we have unmapped doorbell</div><div class='add'>+	 * handling support, other queue will not use the oversubscribe timer.</div><div class='add'>+	 * handling  mode - 0: disabled; 1: basic version; 2: basic+ version</div><div class='add'>+	 */</div><div class='add'>+	mes_set_hw_res_pkt.oversubscription_timer = 50;</div><div class='add'>+	mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_mes_log_enable) {</div><div class='add'>+		mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;</div><div class='add'>+		mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes-&gt;event_log_gpu_addr +</div><div class='add'>+				pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE)</div><div class='add'>+		mes_set_hw_res_pkt.limit_single_process = 1;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),</div><div class='add'>+			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);</div><div class='add'>+	data &amp;= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);</div><div class='add'>+	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] &lt;&lt;</div><div class='add'>+		CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);</div><div class='add'>+	data &amp;= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);</div><div class='add'>+	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] &lt;&lt;</div><div class='add'>+		CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);</div><div class='add'>+	data &amp;= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);</div><div class='add'>+	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] &lt;&lt;</div><div class='add'>+		CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);</div><div class='add'>+	data &amp;= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);</div><div class='add'>+	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] &lt;&lt;</div><div class='add'>+		CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);</div><div class='add'>+	data &amp;= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |</div><div class='add'>+		  CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);</div><div class='add'>+	data |= mes-&gt;aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] &lt;&lt;</div><div class='add'>+		CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	data |= 1 &lt;&lt; CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);</div><div class='add'>+</div><div class='add'>+	data = 1 &lt;&lt; CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_enable_unmapped_doorbell_handling(</div><div class='add'>+		struct amdgpu_mes *mes, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = mes-&gt;adev;</div><div class='add'>+	uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The default PROC_LSB settng is 0xc which means doorbell</div><div class='add'>+	 * addr[16:12] gives the doorbell page number. For kfd, each</div><div class='add'>+	 * process will use 2 pages of doorbell, we need to change the</div><div class='add'>+	 * setting to 0xd</div><div class='add'>+	 */</div><div class='add'>+	data &amp;= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;</div><div class='add'>+	data |= 0xd &lt;&lt;  CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;</div><div class='add'>+</div><div class='add'>+	data |= (enable ? 1 : 0) &lt;&lt; CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,</div><div class='add'>+				    struct mes_reset_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__RESET mes_reset_queue_pkt;</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	if (input-&gt;use_mmio)</div><div class='add'>+		return mes_v12_0_reset_queue_mmio(mes, input-&gt;queue_type,</div><div class='add'>+						  input-&gt;me_id, input-&gt;pipe_id,</div><div class='add'>+						  input-&gt;queue_id, input-&gt;vmid);</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;</div><div class='add'>+	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+</div><div class='add'>+	if (input-&gt;legacy_gfx) {</div><div class='add'>+		mes_reset_queue_pkt.reset_legacy_gfx = 1;</div><div class='add'>+		mes_reset_queue_pkt.pipe_id_lp = input-&gt;pipe_id;</div><div class='add'>+		mes_reset_queue_pkt.queue_id_lp = input-&gt;queue_id;</div><div class='add'>+		mes_reset_queue_pkt.mqd_mc_addr_lp = input-&gt;mqd_addr;</div><div class='add'>+		mes_reset_queue_pkt.doorbell_offset_lp = input-&gt;doorbell_offset;</div><div class='add'>+		mes_reset_queue_pkt.wptr_addr_lp = input-&gt;wptr_addr;</div><div class='add'>+		mes_reset_queue_pkt.vmid_id_lp = input-&gt;vmid;</div><div class='add'>+	} else {</div><div class='add'>+		mes_reset_queue_pkt.reset_queue_only = 1;</div><div class='add'>+		mes_reset_queue_pkt.doorbell_offset = input-&gt;doorbell_offset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (input-&gt;is_kq)</div><div class='add'>+		pipe = AMDGPU_MES_KIQ_PIPE;</div><div class='add'>+	else</div><div class='add'>+		pipe = AMDGPU_MES_SCHED_PIPE;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,</div><div class='add'>+			&amp;mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__RESET, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes,</div><div class='add'>+						  struct mes_detect_and_reset_queue_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__RESET mes_reset_queue_pkt;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;</div><div class='add'>+	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_reset_queue_pkt.queue_type =</div><div class='add'>+		convert_to_mes_queue_type(input-&gt;queue_type);</div><div class='add'>+	mes_reset_queue_pkt.doorbell_offset_addr =</div><div class='add'>+		mes-&gt;hung_queue_db_array_gpu_addr;</div><div class='add'>+</div><div class='add'>+	if (input-&gt;detect_only)</div><div class='add'>+		mes_reset_queue_pkt.hang_detect_only = 1;</div><div class='add'>+	else</div><div class='add'>+		mes_reset_queue_pkt.hang_detect_then_reset = 1;</div><div class='add'>+</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE,</div><div class='add'>+			&amp;mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),</div><div class='add'>+			offsetof(union MESAPI__RESET, api_status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_inv_tlb_convert_hub_id(uint8_t id)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * MES doesn't support invalidate gc_hub on slave xcc individually</div><div class='add'>+	 * master xcc will invalidate all gc_hub for the partition</div><div class='add'>+	 */</div><div class='add'>+	if (AMDGPU_IS_GFXHUB(id))</div><div class='add'>+		return 0;</div><div class='add'>+	else if (AMDGPU_IS_MMHUB0(id))</div><div class='add'>+		return 1;</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes,</div><div class='add'>+				    struct mes_inv_tlbs_pasid_input *input)</div><div class='add'>+{</div><div class='add'>+	union MESAPI__INV_TLBS mes_inv_tlbs;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mes_inv_tlbs, 0, sizeof(mes_inv_tlbs));</div><div class='add'>+</div><div class='add'>+	mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER;</div><div class='add'>+	mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS;</div><div class='add'>+	mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS;</div><div class='add'>+</div><div class='add'>+	mes_inv_tlbs.invalidate_tlbs.inv_sel = 0;</div><div class='add'>+	mes_inv_tlbs.invalidate_tlbs.flush_type = input-&gt;flush_type;</div><div class='add'>+	mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input-&gt;pasid;</div><div class='add'>+</div><div class='add'>+	/*convert amdgpu_mes_hub_id to mes expected hub_id */</div><div class='add'>+	ret = mes_v12_inv_tlb_convert_hub_id(input-&gt;hub_id);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	mes_inv_tlbs.invalidate_tlbs.hub_id = ret;</div><div class='add'>+	return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE,</div><div class='add'>+			&amp;mes_inv_tlbs, sizeof(mes_inv_tlbs),</div><div class='add'>+			offsetof(union MESAPI__INV_TLBS, api_status));</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_mes_funcs mes_v12_0_funcs = {</div><div class='add'>+	.add_hw_queue = mes_v12_0_add_hw_queue,</div><div class='add'>+	.remove_hw_queue = mes_v12_0_remove_hw_queue,</div><div class='add'>+	.map_legacy_queue = mes_v12_0_map_legacy_queue,</div><div class='add'>+	.unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,</div><div class='add'>+	.suspend_gang = mes_v12_0_suspend_gang,</div><div class='add'>+	.resume_gang = mes_v12_0_resume_gang,</div><div class='add'>+	.misc_op = mes_v12_0_misc_op,</div><div class='add'>+	.reset_hw_queue = mes_v12_0_reset_hw_queue,</div><div class='add'>+	.invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid,</div><div class='add'>+	.detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,</div><div class='add'>+					   enum amdgpu_mes_pipe pipe)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	unsigned fw_size;</div><div class='add'>+</div><div class='add'>+	mes_hdr = (const struct mes_firmware_header_v1_0 *)</div><div class='add'>+		adev-&gt;mes.fw[pipe]-&gt;data;</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='add'>+		   le32_to_cpu(mes_hdr-&gt;mes_ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(mes_hdr-&gt;mes_ucode_size_bytes);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_size,</div><div class='add'>+				      PAGE_SIZE,</div><div class='add'>+				      AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;mes.ucode_fw_obj[pipe],</div><div class='add'>+				      &amp;adev-&gt;mes.ucode_fw_gpu_addr[pipe],</div><div class='add'>+				      (void **)&amp;adev-&gt;mes.ucode_fw_ptr[pipe]);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create mes fw bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(adev-&gt;mes.ucode_fw_ptr[pipe], fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;mes.ucode_fw_obj[pipe]);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;mes.ucode_fw_obj[pipe]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,</div><div class='add'>+						enum amdgpu_mes_pipe pipe)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	const struct mes_firmware_header_v1_0 *mes_hdr;</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	unsigned fw_size;</div><div class='add'>+</div><div class='add'>+	mes_hdr = (const struct mes_firmware_header_v1_0 *)</div><div class='add'>+		adev-&gt;mes.fw[pipe]-&gt;data;</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;mes.fw[pipe]-&gt;data +</div><div class='add'>+		   le32_to_cpu(mes_hdr-&gt;mes_ucode_data_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(mes_hdr-&gt;mes_ucode_data_size_bytes);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, fw_size,</div><div class='add'>+				      64 * 1024,</div><div class='add'>+				      AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+				      &amp;adev-&gt;mes.data_fw_obj[pipe],</div><div class='add'>+				      &amp;adev-&gt;mes.data_fw_gpu_addr[pipe],</div><div class='add'>+				      (void **)&amp;adev-&gt;mes.data_fw_ptr[pipe]);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to create mes data fw bo\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(adev-&gt;mes.data_fw_ptr[pipe], fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;mes.data_fw_obj[pipe]);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;mes.data_fw_obj[pipe]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,</div><div class='add'>+					 enum amdgpu_mes_pipe pipe)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.data_fw_obj[pipe],</div><div class='add'>+			      &amp;adev-&gt;mes.data_fw_gpu_addr[pipe],</div><div class='add'>+			      (void **)&amp;adev-&gt;mes.data_fw_ptr[pipe]);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.ucode_fw_obj[pipe],</div><div class='add'>+			      &amp;adev-&gt;mes.ucode_fw_gpu_addr[pipe],</div><div class='add'>+			      (void **)&amp;adev-&gt;mes.ucode_fw_ptr[pipe]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	uint64_t ucode_addr;</div><div class='add'>+	uint32_t pipe, data = 0;</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='add'>+			soc21_grbm_select(adev, 3, pipe, 0, 0);</div><div class='add'>+			if (amdgpu_mes_log_enable) {</div><div class='add'>+				u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;</div><div class='add'>+				/* In case uni mes is not enabled, only program for pipe 0 */</div><div class='add'>+				if (adev-&gt;mes.event_log_size &gt;= (pipe + 1) * log_size) {</div><div class='add'>+					WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,</div><div class='add'>+						     lower_32_bits(adev-&gt;mes.event_log_gpu_addr +</div><div class='add'>+						     pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));</div><div class='add'>+					WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,</div><div class='add'>+						     upper_32_bits(adev-&gt;mes.event_log_gpu_addr +</div><div class='add'>+						     pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));</div><div class='add'>+					dev_info(adev-&gt;dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",</div><div class='add'>+						 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),</div><div class='add'>+						 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);</div><div class='add'>+			if (pipe == 0)</div><div class='add'>+				data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);</div><div class='add'>+			else</div><div class='add'>+				data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);</div><div class='add'>+</div><div class='add'>+			ucode_addr = adev-&gt;mes.uc_start_addr[pipe] &gt;&gt; 2;</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,</div><div class='add'>+				     lower_32_bits(ucode_addr));</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,</div><div class='add'>+				     upper_32_bits(ucode_addr));</div><div class='add'>+</div><div class='add'>+			/* unhalt MES and activate one pipe each loop */</div><div class='add'>+			data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);</div><div class='add'>+			if (pipe)</div><div class='add'>+				data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);</div><div class='add'>+			dev_info(adev-&gt;dev, "program CP_MES_CNTL : 0x%x\n", data);</div><div class='add'>+</div><div class='add'>+			WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);</div><div class='add'>+</div><div class='add'>+		}</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode)</div><div class='add'>+			msleep(100);</div><div class='add'>+		else if (adev-&gt;enable_uni_mes)</div><div class='add'>+			udelay(500);</div><div class='add'>+		else</div><div class='add'>+			udelay(50);</div><div class='add'>+	} else {</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_CNTL,</div><div class='add'>+				     MES_INVALIDATE_ICACHE, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t ucode_addr;</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	mes_v12_0_enable(adev, false);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='add'>+		/* me=3, queue=0 */</div><div class='add'>+		soc21_grbm_select(adev, 3, pipe, 0, 0);</div><div class='add'>+</div><div class='add'>+		/* set ucode start address */</div><div class='add'>+		ucode_addr = adev-&gt;mes.uc_start_addr[pipe] &gt;&gt; 2;</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,</div><div class='add'>+				lower_32_bits(ucode_addr));</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,</div><div class='add'>+				upper_32_bits(ucode_addr));</div><div class='add'>+</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* This function is for backdoor MES firmware */</div><div class='add'>+static int mes_v12_0_load_microcode(struct amdgpu_device *adev,</div><div class='add'>+				    enum amdgpu_mes_pipe pipe, bool prime_icache)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	mes_v12_0_enable(adev, false);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;mes.fw[pipe])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_allocate_ucode_buffer(adev, pipe);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);</div><div class='add'>+	if (r) {</div><div class='add'>+		mes_v12_0_free_ucode_buffers(adev, pipe);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	/* me=3, pipe=0, queue=0 */</div><div class='add'>+	soc21_grbm_select(adev, 3, pipe, 0, 0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);</div><div class='add'>+</div><div class='add'>+	/* set ucode fimrware address */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,</div><div class='add'>+		     lower_32_bits(adev-&gt;mes.ucode_fw_gpu_addr[pipe]));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,</div><div class='add'>+		     upper_32_bits(adev-&gt;mes.ucode_fw_gpu_addr[pipe]));</div><div class='add'>+</div><div class='add'>+	/* set ucode instruction cache boundary to 2M-1 */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);</div><div class='add'>+</div><div class='add'>+	/* set ucode data firmware address */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,</div><div class='add'>+		     lower_32_bits(adev-&gt;mes.data_fw_gpu_addr[pipe]));</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,</div><div class='add'>+		     upper_32_bits(adev-&gt;mes.data_fw_gpu_addr[pipe]));</div><div class='add'>+</div><div class='add'>+	/* Set data cache boundary CP_MES_MDBOUND_LO */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);</div><div class='add'>+</div><div class='add'>+	if (prime_icache) {</div><div class='add'>+		/* invalidate ICACHE */</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);</div><div class='add'>+</div><div class='add'>+		/* prime the ICACHE. */</div><div class='add'>+		data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);</div><div class='add'>+		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,</div><div class='add'>+				      enum amdgpu_mes_pipe pipe)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	u32 *eop;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,</div><div class='add'>+			      AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+			      &amp;adev-&gt;mes.eop_gpu_obj[pipe],</div><div class='add'>+			      &amp;adev-&gt;mes.eop_gpu_addr[pipe],</div><div class='add'>+			      (void **)&amp;eop);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "(%d) create EOP bo failed\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(eop, 0,</div><div class='add'>+	       adev-&gt;mes.eop_gpu_obj[pipe]-&gt;tbo.base.size);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_kunmap(adev-&gt;mes.eop_gpu_obj[pipe]);</div><div class='add'>+	amdgpu_bo_unreserve(adev-&gt;mes.eop_gpu_obj[pipe]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='add'>+	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	mqd-&gt;header = 0xC0310800;</div><div class='add'>+	mqd-&gt;compute_pipelinestat_enable = 0x00000001;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se0 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se1 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se2 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_static_thread_mgmt_se3 = 0xffffffff;</div><div class='add'>+	mqd-&gt;compute_misc_reserved = 0x00000007;</div><div class='add'>+</div><div class='add'>+	eop_base_addr = ring-&gt;eop_gpu_addr &gt;&gt; 8;</div><div class='add'>+</div><div class='add'>+	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */</div><div class='add'>+	tmp = regCP_HQD_EOP_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,</div><div class='add'>+			(order_base_2(MES_EOP_SIZE / 4) - 1));</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);</div><div class='add'>+	mqd-&gt;cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);</div><div class='add'>+	mqd-&gt;cp_hqd_eop_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* disable the queue if it's active */</div><div class='add'>+	ring-&gt;wptr = 0;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr = 0;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_lo = 0;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_hi = 0;</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the MQD */</div><div class='add'>+	mqd-&gt;cp_mqd_base_addr_lo = ring-&gt;mqd_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_mqd_base_addr_hi = upper_32_bits(ring-&gt;mqd_gpu_addr);</div><div class='add'>+</div><div class='add'>+	/* set MQD vmid to 0 */</div><div class='add'>+	tmp = regCP_MQD_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);</div><div class='add'>+	mqd-&gt;cp_mqd_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */</div><div class='add'>+	hqd_gpu_addr = ring-&gt;gpu_addr &gt;&gt; 8;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);</div><div class='add'>+	mqd-&gt;cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	wb_gpu_addr = ring-&gt;rptr_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr &amp; 0xfffffffc;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_rptr_report_addr_hi =</div><div class='add'>+		upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */</div><div class='add'>+	wb_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr &amp; 0xfffffff8;</div><div class='add'>+	mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	/* set up the HQD, this is similar to CP_RB0_CNTL */</div><div class='add'>+	tmp = regCP_HQD_PQ_CONTROL_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,</div><div class='add'>+			    (order_base_2(ring-&gt;ring_size / 4) - 1));</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,</div><div class='add'>+			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) &lt;&lt; 8));</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);</div><div class='add'>+	mqd-&gt;cp_hqd_pq_control = tmp;</div><div class='add'>+</div><div class='add'>+	/* enable doorbell */</div><div class='add'>+	tmp = 0;</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_OFFSET, ring-&gt;doorbell_index);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_SOURCE, 0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_HIT, 0);</div><div class='add'>+	} else {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				    DOORBELL_EN, 0);</div><div class='add'>+	}</div><div class='add'>+	mqd-&gt;cp_hqd_pq_doorbell_control = tmp;</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_vmid = 0;</div><div class='add'>+	/* activate the queue */</div><div class='add'>+	mqd-&gt;cp_hqd_active = 1;</div><div class='add'>+</div><div class='add'>+	tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,</div><div class='add'>+			    PRELOAD_SIZE, 0x55);</div><div class='add'>+	mqd-&gt;cp_hqd_persistent_state = tmp;</div><div class='add'>+</div><div class='add'>+	mqd-&gt;cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;</div><div class='add'>+	mqd-&gt;cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;</div><div class='add'>+	mqd-&gt;cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped</div><div class='add'>+	 * doorbell handling. This is a reserved CP internal register can</div><div class='add'>+	 * not be accesss by others</div><div class='add'>+	 */</div><div class='add'>+	mqd-&gt;reserved_184 = BIT(15);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *mqd = ring-&gt;mqd_ptr;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	uint32_t data = 0;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc21_grbm_select(adev, 3, ring-&gt;pipe, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_VMID.VMID = 0. */</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+			     DOORBELL_EN, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);</div><div class='add'>+</div><div class='add'>+	/* set CP_MQD_BASE_ADDR/HI with the MQD base address */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd-&gt;cp_mqd_base_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd-&gt;cp_mqd_base_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* set CP_MQD_CONTROL.VMID=0 */</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PQ_BASE/HI with the ring buffer base address */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd-&gt;cp_hqd_pq_base_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd-&gt;cp_hqd_pq_base_hi);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,</div><div class='add'>+		     mqd-&gt;cp_hqd_pq_rptr_report_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,</div><div class='add'>+		     mqd-&gt;cp_hqd_pq_rptr_report_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PQ_CONTROL */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd-&gt;cp_hqd_pq_control);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,</div><div class='add'>+		     mqd-&gt;cp_hqd_pq_wptr_poll_addr_lo);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,</div><div class='add'>+		     mqd-&gt;cp_hqd_pq_wptr_poll_addr_hi);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PQ_DOORBELL_CONTROL */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+		     mqd-&gt;cp_hqd_pq_doorbell_control);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd-&gt;cp_hqd_persistent_state);</div><div class='add'>+</div><div class='add'>+	/* set CP_HQD_ACTIVE.ACTIVE=1 */</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd-&gt;cp_hqd_active);</div><div class='add'>+</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_kiq *kiq = &amp;adev-&gt;gfx.kiq[0];</div><div class='add'>+	struct amdgpu_ring *kiq_ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!kiq-&gt;pmf || !kiq-&gt;pmf-&gt;kiq_map_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ring_alloc(kiq_ring, kiq-&gt;pmf-&gt;map_queues_size);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kiq-&gt;pmf-&gt;kiq_map_queues(kiq_ring, &amp;adev-&gt;mes.ring[0]);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ring_test_ring(kiq_ring);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("kfq enable failed\n");</div><div class='add'>+		kiq_ring-&gt;sched.ready = false;</div><div class='add'>+	}</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_queue_init(struct amdgpu_device *adev,</div><div class='add'>+				enum amdgpu_mes_pipe pipe)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_uni_mes &amp;&amp; pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='add'>+		ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='add'>+	else</div><div class='add'>+		ring = &amp;adev-&gt;mes.ring[pipe];</div><div class='add'>+</div><div class='add'>+	if ((adev-&gt;enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &amp;&amp;</div><div class='add'>+	    (amdgpu_in_reset(adev) || adev-&gt;in_suspend)) {</div><div class='add'>+		*(ring-&gt;wptr_cpu_addr) = 0;</div><div class='add'>+		*(ring-&gt;rptr_cpu_addr) = 0;</div><div class='add'>+		amdgpu_ring_clear_ring(ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_mqd_init(ring);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (pipe == AMDGPU_MES_SCHED_PIPE) {</div><div class='add'>+		if (adev-&gt;enable_uni_mes)</div><div class='add'>+			r = amdgpu_mes_map_legacy_queue(adev, ring);</div><div class='add'>+		else</div><div class='add'>+			r = mes_v12_0_kiq_enable_queue(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	} else {</div><div class='add'>+		mes_v12_0_queue_init_register(ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (((pipe == AMDGPU_MES_SCHED_PIPE) &amp;&amp; !adev-&gt;mes.sched_version) ||</div><div class='add'>+	    ((pipe == AMDGPU_MES_KIQ_PIPE) &amp;&amp; !adev-&gt;mes.kiq_version)) {</div><div class='add'>+		/* get MES scheduler/KIQ versions */</div><div class='add'>+		mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+		soc21_grbm_select(adev, 3, pipe, 0, 0);</div><div class='add'>+</div><div class='add'>+		if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='add'>+			adev-&gt;mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);</div><div class='add'>+		else if (pipe == AMDGPU_MES_KIQ_PIPE &amp;&amp; adev-&gt;enable_mes_kiq)</div><div class='add'>+			adev-&gt;mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);</div><div class='add'>+</div><div class='add'>+		soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;mes.ring[pipe];</div><div class='add'>+</div><div class='add'>+	ring-&gt;funcs = &amp;mes_v12_0_ring_funcs;</div><div class='add'>+</div><div class='add'>+	ring-&gt;me = 3;</div><div class='add'>+	ring-&gt;pipe = pipe;</div><div class='add'>+	ring-&gt;queue = 0;</div><div class='add'>+</div><div class='add'>+	ring-&gt;ring_obj = NULL;</div><div class='add'>+	ring-&gt;use_doorbell = true;</div><div class='add'>+	ring-&gt;eop_gpu_addr = adev-&gt;mes.eop_gpu_addr[pipe];</div><div class='add'>+	ring-&gt;no_scheduler = true;</div><div class='add'>+	sprintf(ring-&gt;name, "mes_%d.%d.%d", ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='add'>+</div><div class='add'>+	if (pipe == AMDGPU_MES_SCHED_PIPE)</div><div class='add'>+		ring-&gt;doorbell_index = adev-&gt;doorbell_index.mes_ring0 &lt;&lt; 1;</div><div class='add'>+	else</div><div class='add'>+		ring-&gt;doorbell_index = adev-&gt;doorbell_index.mes_ring1 &lt;&lt; 1;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_init(adev, ring, 1024, NULL, 0,</div><div class='add'>+				AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;adev-&gt;gfx.kiq[0].ring_lock);</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='add'>+</div><div class='add'>+	ring-&gt;me = 3;</div><div class='add'>+	ring-&gt;pipe = 1;</div><div class='add'>+	ring-&gt;queue = 0;</div><div class='add'>+</div><div class='add'>+	ring-&gt;adev = NULL;</div><div class='add'>+	ring-&gt;ring_obj = NULL;</div><div class='add'>+	ring-&gt;use_doorbell = true;</div><div class='add'>+	ring-&gt;doorbell_index = adev-&gt;doorbell_index.mes_ring1 &lt;&lt; 1;</div><div class='add'>+	ring-&gt;eop_gpu_addr = adev-&gt;mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];</div><div class='add'>+	ring-&gt;no_scheduler = true;</div><div class='add'>+	sprintf(ring-&gt;name, "mes_kiq_%d.%d.%d",</div><div class='add'>+		ring-&gt;me, ring-&gt;pipe, ring-&gt;queue);</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_init(adev, ring, 1024, NULL, 0,</div><div class='add'>+				AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,</div><div class='add'>+				 enum amdgpu_mes_pipe pipe)</div><div class='add'>+{</div><div class='add'>+	int r, mqd_size = sizeof(struct v12_compute_mqd);</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_uni_mes &amp;&amp; pipe == AMDGPU_MES_KIQ_PIPE)</div><div class='add'>+		ring = &amp;adev-&gt;gfx.kiq[0].ring;</div><div class='add'>+	else</div><div class='add'>+		ring = &amp;adev-&gt;mes.ring[pipe];</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;mqd_obj)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_GTT, &amp;ring-&gt;mqd_obj,</div><div class='add'>+				    &amp;ring-&gt;mqd_gpu_addr, &amp;ring-&gt;mqd_ptr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed to create ring mqd bo (%d)", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(ring-&gt;mqd_ptr, 0, mqd_size);</div><div class='add'>+</div><div class='add'>+	/* prepare MQD backup */</div><div class='add'>+	adev-&gt;mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);</div><div class='add'>+	if (!adev-&gt;mes.mqd_backup[pipe])</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "no memory to create MQD backup for ring %s\n",</div><div class='add'>+			 ring-&gt;name);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int pipe, r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;mes.funcs = &amp;mes_v12_0_funcs;</div><div class='add'>+	adev-&gt;mes.kiq_hw_init = &amp;mes_v12_0_kiq_hw_init;</div><div class='add'>+	adev-&gt;mes.kiq_hw_fini = &amp;mes_v12_0_kiq_hw_fini;</div><div class='add'>+	adev-&gt;mes.enable_legacy_queue_map = true;</div><div class='add'>+</div><div class='add'>+	adev-&gt;mes.event_log_size = adev-&gt;enable_uni_mes ?</div><div class='add'>+		(AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) :</div><div class='add'>+		(AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);</div><div class='add'>+	r = amdgpu_mes_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='add'>+		r = mes_v12_0_allocate_eop_buf(adev, pipe);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		r = mes_v12_0_mqd_sw_init(adev, pipe);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		if (!adev-&gt;enable_uni_mes &amp;&amp; pipe == AMDGPU_MES_KIQ_PIPE) {</div><div class='add'>+			r = mes_v12_0_kiq_ring_init(adev);</div><div class='add'>+		}</div><div class='add'>+		else {</div><div class='add'>+			r = mes_v12_0_ring_init(adev, pipe);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+			r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,</div><div class='add'>+						    AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+						    &amp;adev-&gt;mes.resource_1[pipe],</div><div class='add'>+						    &amp;adev-&gt;mes.resource_1_gpu_addr[pipe],</div><div class='add'>+						    &amp;adev-&gt;mes.resource_1_addr[pipe]);</div><div class='add'>+			if (r) {</div><div class='add'>+				dev_err(adev-&gt;dev, "(%d) failed to create mes resource_1 bo pipe[%d]\n", r, pipe);</div><div class='add'>+				return r;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int pipe;</div><div class='add'>+</div><div class='add'>+	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;mes.resource_1[pipe],</div><div class='add'>+				      &amp;adev-&gt;mes.resource_1_gpu_addr[pipe],</div><div class='add'>+				      &amp;adev-&gt;mes.resource_1_addr[pipe]);</div><div class='add'>+</div><div class='add'>+		kfree(adev-&gt;mes.mqd_backup[pipe]);</div><div class='add'>+</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;mes.eop_gpu_obj[pipe],</div><div class='add'>+				      &amp;adev-&gt;mes.eop_gpu_addr[pipe],</div><div class='add'>+				      NULL);</div><div class='add'>+		amdgpu_ucode_release(&amp;adev-&gt;mes.fw[pipe]);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {</div><div class='add'>+			amdgpu_bo_free_kernel(&amp;adev-&gt;mes.ring[pipe].mqd_obj,</div><div class='add'>+					      &amp;adev-&gt;mes.ring[pipe].mqd_gpu_addr,</div><div class='add'>+					      &amp;adev-&gt;mes.ring[pipe].mqd_ptr);</div><div class='add'>+			amdgpu_ring_fini(&amp;adev-&gt;mes.ring[pipe]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_uni_mes) {</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;gfx.kiq[0].ring.mqd_obj,</div><div class='add'>+				      &amp;adev-&gt;gfx.kiq[0].ring.mqd_gpu_addr,</div><div class='add'>+				      &amp;adev-&gt;gfx.kiq[0].ring.mqd_ptr);</div><div class='add'>+		amdgpu_ring_fini(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+		mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);</div><div class='add'>+		mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_fini(adev);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t data;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+	soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* disable the queue if it's active */</div><div class='add'>+	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp; 1) {</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp; 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				DOORBELL_EN, 0);</div><div class='add'>+	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,</div><div class='add'>+				DOORBELL_HIT, 1);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);</div><div class='add'>+	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);</div><div class='add'>+</div><div class='add'>+	soc21_grbm_select(adev, 0, 0, 0, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;srbm_mutex);</div><div class='add'>+</div><div class='add'>+	adev-&gt;mes.ring[0].sched.ready = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* tell RLC which is KIQ queue */</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);</div><div class='add'>+	tmp &amp;= 0xffffff00;</div><div class='add'>+	tmp |= (ring-&gt;me &lt;&lt; 5) | (ring-&gt;pipe &lt;&lt; 3) | (ring-&gt;queue);</div><div class='add'>+	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_uni_mes)</div><div class='add'>+		mes_v12_0_kiq_setting(&amp;adev-&gt;mes.ring[AMDGPU_MES_KIQ_PIPE]);</div><div class='add'>+	else</div><div class='add'>+		mes_v12_0_kiq_setting(&amp;adev-&gt;gfx.kiq[0].ring);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+</div><div class='add'>+		r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);</div><div class='add'>+		if (r) {</div><div class='add'>+			DRM_ERROR("failed to load MES fw, r=%d\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);</div><div class='add'>+		if (r) {</div><div class='add'>+			DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mes_v12_0_set_ucode_start_addr(adev);</div><div class='add'>+</div><div class='add'>+	} else if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)</div><div class='add'>+		mes_v12_0_set_ucode_start_addr(adev);</div><div class='add'>+</div><div class='add'>+	mes_v12_0_enable(adev, true);</div><div class='add'>+</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);</div><div class='add'>+	if (unlikely(!ip_block)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to get MES handle\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failure;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_uni_mes) {</div><div class='add'>+		r = mes_v12_0_set_hw_resources(&amp;adev-&gt;mes, AMDGPU_MES_KIQ_PIPE);</div><div class='add'>+		if (r)</div><div class='add'>+			goto failure;</div><div class='add'>+</div><div class='add'>+		mes_v12_0_set_hw_resources_1(&amp;adev-&gt;mes, AMDGPU_MES_KIQ_PIPE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;mes.enable_legacy_queue_map) {</div><div class='add'>+		r = mes_v12_0_hw_init(ip_block);</div><div class='add'>+		if (r)</div><div class='add'>+			goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+</div><div class='add'>+failure:</div><div class='add'>+	mes_v12_0_hw_fini(ip_block);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready) {</div><div class='add'>+		if (adev-&gt;enable_uni_mes)</div><div class='add'>+			amdgpu_mes_unmap_legacy_queue(adev,</div><div class='add'>+				      &amp;adev-&gt;mes.ring[AMDGPU_MES_SCHED_PIPE],</div><div class='add'>+				      RESET_QUEUES, 0, 0);</div><div class='add'>+		else</div><div class='add'>+			mes_v12_0_kiq_dequeue_sched(adev);</div><div class='add'>+</div><div class='add'>+		adev-&gt;mes.ring[0].sched.ready = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mes_v12_0_enable(adev, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;mes.ring[0].sched.ready)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;enable_mes_kiq) {</div><div class='add'>+		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+			r = mes_v12_0_load_microcode(adev,</div><div class='add'>+					     AMDGPU_MES_SCHED_PIPE, true);</div><div class='add'>+			if (r) {</div><div class='add'>+				DRM_ERROR("failed to MES fw, r=%d\n", r);</div><div class='add'>+				return r;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			mes_v12_0_set_ucode_start_addr(adev);</div><div class='add'>+</div><div class='add'>+		} else if (adev-&gt;firmware.load_type ==</div><div class='add'>+			   AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {</div><div class='add'>+</div><div class='add'>+			mes_v12_0_set_ucode_start_addr(adev);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mes_v12_0_enable(adev, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Enable the MES to handle doorbell ring on unmapped queue */</div><div class='add'>+	mes_v12_0_enable_unmapped_doorbell_handling(&amp;adev-&gt;mes, true);</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failure;</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_set_hw_resources(&amp;adev-&gt;mes, AMDGPU_MES_SCHED_PIPE);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failure;</div><div class='add'>+</div><div class='add'>+	if ((adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 0x4b)</div><div class='add'>+		mes_v12_0_set_hw_resources_1(&amp;adev-&gt;mes, AMDGPU_MES_SCHED_PIPE);</div><div class='add'>+</div><div class='add'>+	mes_v12_0_init_aggregated_doorbell(&amp;adev-&gt;mes);</div><div class='add'>+</div><div class='add'>+	r = mes_v12_0_query_sched_status(&amp;adev-&gt;mes, AMDGPU_MES_SCHED_PIPE);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("MES is busy\n");</div><div class='add'>+		goto failure;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_update_enforce_isolation(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto failure;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	/*</div><div class='add'>+	 * Disable KIQ ring usage from the driver once MES is enabled.</div><div class='add'>+	 * MES uses KIQ ring exclusively so driver cannot access KIQ ring</div><div class='add'>+	 * with MES enabled.</div><div class='add'>+	 */</div><div class='add'>+	adev-&gt;gfx.kiq[0].ring.sched.ready = false;</div><div class='add'>+	adev-&gt;mes.ring[0].sched.ready = true;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+failure:</div><div class='add'>+	mes_v12_0_hw_fini(ip_block);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return mes_v12_0_hw_fini(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return mes_v12_0_hw_init(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int pipe, r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE;</div><div class='add'>+	adev-&gt;mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET;</div><div class='add'>+</div><div class='add'>+	for (pipe = 0; pipe &lt; AMDGPU_MAX_MES_PIPES; pipe++) {</div><div class='add'>+		r = amdgpu_mes_init_microcode(adev, pipe);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs mes_v12_0_ip_funcs = {</div><div class='add'>+	.name = "mes_v12_0",</div><div class='add'>+	.early_init = mes_v12_0_early_init,</div><div class='add'>+	.late_init = NULL,</div><div class='add'>+	.sw_init = mes_v12_0_sw_init,</div><div class='add'>+	.sw_fini = mes_v12_0_sw_fini,</div><div class='add'>+	.hw_init = mes_v12_0_hw_init,</div><div class='add'>+	.hw_fini = mes_v12_0_hw_fini,</div><div class='add'>+	.suspend = mes_v12_0_suspend,</div><div class='add'>+	.resume = mes_v12_0_resume,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version mes_v12_0_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_MES,</div><div class='add'>+	.major = 12,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;mes_v12_0_ip_funcs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.h b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.h<br/>new file mode 100644<br/>index 000000000000..ac3740f353aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v12_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mes_v12_0.h</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __MES_V12_0_H__</div><div class='add'>+#define __MES_V12_0_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_ip_block_version mes_v12_0_ip_block;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br/>index e3ddd22aa172..243eabda0607 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c</a></div><div class='hunk'>@@ -229,6 +229,52 @@ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)</div><div class='ctx'> 		     0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mmhub_v1_0_init_saw(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev-&gt;gart.bo);</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,</div><div class='add'>+			    lower_32_bits(pt_base &gt;&gt; 12));</div><div class='add'>+</div><div class='add'>+	/* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,</div><div class='add'>+			    upper_32_bits(pt_base &gt;&gt; 12));</div><div class='add'>+</div><div class='add'>+	/* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,</div><div class='add'>+			    (u32)(adev-&gt;gmc.gart_start &gt;&gt; 12));</div><div class='add'>+</div><div class='add'>+	/* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,</div><div class='add'>+			    (u32)(adev-&gt;gmc.gart_start &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	/* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,</div><div class='add'>+			    (u32)(adev-&gt;gmc.gart_end &gt;&gt; 12));</div><div class='add'>+</div><div class='add'>+	/* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,</div><div class='add'>+			    (u32)(adev-&gt;gmc.gart_end &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	/* Program SAW CONTEXT0 CNTL */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL);</div><div class='add'>+	tmp |= 1 &lt;&lt; CONTEXT0_CNTL_ENABLE_OFFSET;</div><div class='add'>+	tmp &amp;= ~(3 &lt;&lt; CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Disable all Contexts except Context0 */</div><div class='add'>+	tmp = 0xfffe;</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXTS_DISABLE, tmp);</div><div class='add'>+</div><div class='add'>+	/* Program SAW CNTL4 */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4);</div><div class='add'>+	tmp |= 1 &lt;&lt; VMC_TAP_PDE_REQUEST_SNOOP_OFFSET;</div><div class='add'>+	tmp |= 1 &lt;&lt; VMC_TAP_PTE_REQUEST_SNOOP_OFFSET;</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='hunk'>@@ -283,6 +329,9 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)</div><div class='ctx'> 				    i * hub-&gt;ctx_addr_distance,</div><div class='ctx'> 				    upper_32_bits(adev-&gt;vm_manager.max_pfn - 1));</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, ISP_HWIP, 0))</div><div class='add'>+		mmhub_v1_0_init_saw(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)</div><div class='hunk'>@@ -307,7 +356,7 @@ static void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,</div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_MMHUB)</div><div class='ctx'> 		amdgpu_dpm_set_powergating_by_smu(adev,</div><div class='ctx'> 						  AMD_IP_BLOCK_TYPE_GMC,</div><div class='del'>-						  enable);</div><div class='add'>+						  enable, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c<br/>index 92432cd2c0c7..2adee2b94c37 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c</a></div><div class='hunk'>@@ -172,6 +172,30 @@ static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */</div><div class='add'>+static void mmhub_v1_7_init_snoop_override_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -</div><div class='add'>+			    regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 5; i++) { /* DAGB instances */</div><div class='add'>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance);</div><div class='add'>+		tmp |= (1 &lt;&lt; 15); /* SDMA client is BIT15 */</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance);</div><div class='add'>+		tmp |= (1 &lt;&lt; 15);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance, tmp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t tmp;</div><div class='hunk'>@@ -337,6 +361,7 @@ static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	mmhub_v1_7_init_system_aperture_regs(adev);</div><div class='ctx'> 	mmhub_v1_7_init_tlb_regs(adev);</div><div class='ctx'> 	mmhub_v1_7_init_cache_regs(adev);</div><div class='add'>+	mmhub_v1_7_init_snoop_override_regs(adev);</div><div class='ctx'> </div><div class='ctx'> 	mmhub_v1_7_enable_system_domain(adev);</div><div class='ctx'> 	mmhub_v1_7_disable_identity_aperture(adev);</div><div class='hunk'>@@ -544,7 +569,7 @@ static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	int data, data1;</div><div class='add'>+	u32 data, data1;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		*flags = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c<br/>index c0fc44cdd658..cc688ae79e84 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c</a></div><div class='hunk'>@@ -30,10 +30,10 @@</div><div class='ctx'> #include "soc15_common.h"</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_psp.h"</div><div class='ctx'> </div><div class='ctx'> #define regVM_L2_CNTL3_DEFAULT	0x80100007</div><div class='ctx'> #define regVM_L2_CNTL4_DEFAULT	0x000000c1</div><div class='del'>-#define mmSMNAID_AID0_MCA_SMU 0x03b30400</div><div class='ctx'> </div><div class='ctx'> static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='hunk'>@@ -76,6 +76,8 @@ static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint64_t gart_start = amdgpu_virt_xgmi_migrate_enabled(adev) ?</div><div class='add'>+			adev-&gt;gmc.vram_start : adev-&gt;gmc.fb_start;</div><div class='ctx'> 	uint64_t pt_base;</div><div class='ctx'> 	u32 inst_mask;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -95,10 +97,10 @@ static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;gmc.pdb0_bo) {</div><div class='ctx'> 			WREG32_SOC15(MMHUB, i,</div><div class='ctx'> 				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,</div><div class='del'>-				     (u32)(adev-&gt;gmc.fb_start &gt;&gt; 12));</div><div class='add'>+				     (u32)(gart_start &gt;&gt; 12));</div><div class='ctx'> 			WREG32_SOC15(MMHUB, i,</div><div class='ctx'> 				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,</div><div class='del'>-				     (u32)(adev-&gt;gmc.fb_start &gt;&gt; 44));</div><div class='add'>+				     (u32)(gart_start &gt;&gt; 44));</div><div class='ctx'> </div><div class='ctx'> 			WREG32_SOC15(MMHUB, i,</div><div class='ctx'> 				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,</div><div class='hunk'>@@ -193,10 +195,8 @@ static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)</div><div class='ctx'> 	uint32_t tmp, inst_mask;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	/* Setup TLB control */</div><div class='del'>-	inst_mask = adev-&gt;aid_mask;</div><div class='del'>-	for_each_inst(i, inst_mask) {</div><div class='del'>-		tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+	if (amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev)) {</div><div class='add'>+		tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);</div><div class='ctx'> </div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,</div><div class='ctx'> 				    1);</div><div class='hunk'>@@ -210,7 +210,55 @@ static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)</div><div class='ctx'> 				    MTYPE, MTYPE_UC);/* XXX for emulation. */</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+		psp_reg_program_no_ring(&amp;adev-&gt;psp, tmp, PSP_REG_MMHUB_L1_TLB_CNTL);</div><div class='add'>+	} else {</div><div class='add'>+		inst_mask = adev-&gt;aid_mask;</div><div class='add'>+		for_each_inst(i, inst_mask) {</div><div class='add'>+			tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,</div><div class='add'>+					    1);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+					    SYSTEM_ACCESS_MODE, 3);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+					    ENABLE_ADVANCED_DRIVER_MODEL, 1);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+					    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+					    MTYPE, MTYPE_UC);/* XXX for emulation. */</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);</div><div class='add'>+</div><div class='add'>+			WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */</div><div class='add'>+static void mmhub_v1_8_init_snoop_override_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp, inst_mask;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -</div><div class='add'>+			    regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	inst_mask = adev-&gt;aid_mask;</div><div class='add'>+	for_each_inst(i, inst_mask) {</div><div class='add'>+		for (j = 0; j &lt; 5; j++) { /* DAGB instances */</div><div class='add'>+			tmp = RREG32_SOC15_OFFSET(MMHUB, i,</div><div class='add'>+				regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance);</div><div class='add'>+			tmp |= (1 &lt;&lt; 15); /* SDMA client is BIT15 */</div><div class='add'>+			WREG32_SOC15_OFFSET(MMHUB, i,</div><div class='add'>+				regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance, tmp);</div><div class='add'>+</div><div class='add'>+			tmp = RREG32_SOC15_OFFSET(MMHUB, i,</div><div class='add'>+				regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance);</div><div class='add'>+			tmp |= (1 &lt;&lt; 15);</div><div class='add'>+			WREG32_SOC15_OFFSET(MMHUB, i,</div><div class='add'>+				regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance, tmp);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -419,6 +467,7 @@ static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	mmhub_v1_8_init_system_aperture_regs(adev);</div><div class='ctx'> 	mmhub_v1_8_init_tlb_regs(adev);</div><div class='ctx'> 	mmhub_v1_8_init_cache_regs(adev);</div><div class='add'>+	mmhub_v1_8_init_snoop_override_regs(adev);</div><div class='ctx'> </div><div class='ctx'> 	mmhub_v1_8_enable_system_domain(adev);</div><div class='ctx'> 	mmhub_v1_8_disable_identity_aperture(adev);</div><div class='hunk'>@@ -428,6 +477,30 @@ static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mmhub_v1_8_disable_l1_tlb(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+	u32 i, inst_mask;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev)) {</div><div class='add'>+		tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+				    ENABLE_ADVANCED_DRIVER_MODEL, 0);</div><div class='add'>+		psp_reg_program_no_ring(&amp;adev-&gt;psp, tmp, PSP_REG_MMHUB_L1_TLB_CNTL);</div><div class='add'>+	} else {</div><div class='add'>+		inst_mask = adev-&gt;aid_mask;</div><div class='add'>+		for_each_inst(i, inst_mask) {</div><div class='add'>+			tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,</div><div class='add'>+					    0);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+					    ENABLE_ADVANCED_DRIVER_MODEL, 0);</div><div class='add'>+			WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vmhub *hub;</div><div class='hunk'>@@ -441,15 +514,6 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> 		for (i = 0; i &lt; 16; i++)</div><div class='ctx'> 			WREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT0_CNTL,</div><div class='ctx'> 					    i * hub-&gt;ctx_distance, 0);</div><div class='del'>-</div><div class='del'>-		/* Setup TLB control */</div><div class='del'>-		tmp = RREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,</div><div class='del'>-				    0);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,</div><div class='del'>-				    ENABLE_ADVANCED_DRIVER_MODEL, 0);</div><div class='del'>-		WREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='del'>-</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			/* Setup L2 cache */</div><div class='ctx'> 			tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);</div><div class='hunk'>@@ -459,6 +523,8 @@ static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)</div><div class='ctx'> 			WREG32_SOC15(MMHUB, j, regVM_L2_CNTL3, 0);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	mmhub_v1_8_disable_l1_tlb(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -653,8 +719,8 @@ static void mmhub_v1_8_inst_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 					AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,</div><div class='ctx'> 					&amp;ue_count);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, ce_count);</div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, ce_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v1_8_query_ras_error_count(struct amdgpu_device *adev,</div><div class='hunk'>@@ -706,28 +772,34 @@ static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = {</div><div class='ctx'> 	.reset_ras_error_count = mmhub_v1_8_reset_ras_error_count,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int mmhub_v1_8_aca_bank_generate_report(struct aca_handle *handle,</div><div class='del'>-					       struct aca_bank *bank, enum aca_error_type type,</div><div class='del'>-					       struct aca_bank_report *report, void *data)</div><div class='add'>+static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				      enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='del'>-	u64 status, misc0;</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	status = bank-&gt;regs[ACA_REG_IDX_STATUS];</div><div class='del'>-	if ((type == ACA_ERROR_TYPE_UE &amp;&amp;</div><div class='del'>-	     ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) ||</div><div class='del'>-	    (type == ACA_ERROR_TYPE_CE &amp;&amp;</div><div class='del'>-	     ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {</div><div class='del'>-</div><div class='del'>-		ret = aca_bank_info_decode(bank, &amp;report-&gt;info);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='del'>-		report-&gt;count[type] = ACA_REG__MISC0__ERRCNT(misc0);</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE,</div><div class='add'>+						     1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* reference to smu driver if header file */</div><div class='hunk'>@@ -741,7 +813,7 @@ static int mmhub_v1_8_err_codes[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='del'>-					 enum aca_error_type type, void *data)</div><div class='add'>+					 enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	u32 instlo;</div><div class='ctx'> </div><div class='hunk'>@@ -760,7 +832,7 @@ static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_b</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = {</div><div class='del'>-	.aca_bank_generate_report = mmhub_v1_8_aca_bank_generate_report,</div><div class='add'>+	.aca_bank_parser = mmhub_v1_8_aca_bank_parser,</div><div class='ctx'> 	.aca_bank_is_valid = mmhub_v1_8_aca_bank_is_valid,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c<br/>index 02fd45261399..a0cc8e218ca1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c</a></div><div class='hunk'>@@ -671,7 +671,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	int data, data1;</div><div class='add'>+	u32 data, data1;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		*flags = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c<br/>index 134c4ec10887..910337dc28d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c</a></div><div class='hunk'>@@ -36,40 +36,47 @@</div><div class='ctx'> </div><div class='ctx'> static const char *mmhub_client_ids_v3_0_1[][2] = {</div><div class='ctx'> 	[0][0] = "VMC",</div><div class='add'>+	[1][0] = "ISPXT",</div><div class='add'>+	[2][0] = "ISPIXT",</div><div class='ctx'> 	[4][0] = "DCEDMC",</div><div class='ctx'> 	[5][0] = "DCEVGA",</div><div class='ctx'> 	[6][0] = "MP0",</div><div class='ctx'> 	[7][0] = "MP1",</div><div class='del'>-	[8][0] = "MPIO",</div><div class='del'>-	[16][0] = "HDP",</div><div class='del'>-	[17][0] = "LSDMA",</div><div class='del'>-	[18][0] = "JPEG",</div><div class='del'>-	[19][0] = "VCNU0",</div><div class='del'>-	[21][0] = "VSCH",</div><div class='del'>-	[22][0] = "VCNU1",</div><div class='del'>-	[23][0] = "VCN1",</div><div class='del'>-	[32+20][0] = "VCN0",</div><div class='del'>-	[2][1] = "DBGUNBIO",</div><div class='add'>+	[8][0] = "MPM",</div><div class='add'>+	[12][0] = "ISPTNR",</div><div class='add'>+	[14][0] = "ISPCRD0",</div><div class='add'>+	[15][0] = "ISPCRD1",</div><div class='add'>+	[16][0] = "ISPCRD2",</div><div class='add'>+	[22][0] = "HDP",</div><div class='add'>+	[23][0] = "LSDMA",</div><div class='add'>+	[24][0] = "JPEG",</div><div class='add'>+	[27][0] = "VSCH",</div><div class='add'>+	[28][0] = "VCNU",</div><div class='add'>+	[29][0] = "VCN",</div><div class='add'>+	[1][1] = "ISPXT",</div><div class='add'>+	[2][1] = "ISPIXT",</div><div class='ctx'> 	[3][1] = "DCEDWB",</div><div class='ctx'> 	[4][1] = "DCEDMC",</div><div class='ctx'> 	[5][1] = "DCEVGA",</div><div class='ctx'> 	[6][1] = "MP0",</div><div class='ctx'> 	[7][1] = "MP1",</div><div class='del'>-	[8][1] = "MPIO",</div><div class='del'>-	[10][1] = "DBGU0",</div><div class='del'>-	[11][1] = "DBGU1",</div><div class='del'>-	[12][1] = "DBGU2",</div><div class='del'>-	[13][1] = "DBGU3",</div><div class='del'>-	[14][1] = "XDP",</div><div class='del'>-	[15][1] = "OSSSYS",</div><div class='del'>-	[16][1] = "HDP",</div><div class='del'>-	[17][1] = "LSDMA",</div><div class='del'>-	[18][1] = "JPEG",</div><div class='del'>-	[19][1] = "VCNU0",</div><div class='del'>-	[20][1] = "VCN0",</div><div class='del'>-	[21][1] = "VSCH",</div><div class='del'>-	[22][1] = "VCNU1",</div><div class='del'>-	[23][1] = "VCN1",</div><div class='add'>+	[8][1] = "MPM",</div><div class='add'>+	[10][1] = "ISPMWR0",</div><div class='add'>+	[11][1] = "ISPMWR1",</div><div class='add'>+	[12][1] = "ISPTNR",</div><div class='add'>+	[13][1] = "ISPSWR",</div><div class='add'>+	[14][1] = "ISPCWR0",</div><div class='add'>+	[15][1] = "ISPCWR1",</div><div class='add'>+	[16][1] = "ISPCWR2",</div><div class='add'>+	[17][1] = "ISPCWR3",</div><div class='add'>+	[18][1] = "XDP",</div><div class='add'>+	[21][1] = "OSSSYS",</div><div class='add'>+	[22][1] = "HDP",</div><div class='add'>+	[23][1] = "LSDMA",</div><div class='add'>+	[24][1] = "JPEG",</div><div class='add'>+	[27][1] = "VSCH",</div><div class='add'>+	[28][1] = "VCNU",</div><div class='add'>+	[29][1] = "VCN",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c<br/>index 238ea40c2450..f6fc9778bc30 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c</a></div><div class='hunk'>@@ -33,33 +33,136 @@</div><div class='ctx'> #define regMMVM_L2_CNTL3_DEFAULT				0x80100007</div><div class='ctx'> #define regMMVM_L2_CNTL4_DEFAULT				0x000000c1</div><div class='ctx'> #define regMMVM_L2_CNTL5_DEFAULT				0x00003fe0</div><div class='add'>+#define regDAGB0_L1TLB_REG_RW_3_3                   0x00a4</div><div class='add'>+#define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX          1</div><div class='add'>+#define regDAGB1_L1TLB_REG_RW_3_3                   0x0163</div><div class='add'>+#define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX          1</div><div class='ctx'> </div><div class='ctx'> static const char *mmhub_client_ids_v3_3[][2] = {</div><div class='ctx'> 	[0][0] = "VMC",</div><div class='add'>+	[1][0] = "ISPXT",</div><div class='add'>+	[2][0] = "ISPIXT",</div><div class='ctx'> 	[4][0] = "DCEDMC",</div><div class='ctx'> 	[6][0] = "MP0",</div><div class='ctx'> 	[7][0] = "MP1",</div><div class='ctx'> 	[8][0] = "MPM",</div><div class='add'>+	[9][0] = "ISPPDPRD",</div><div class='add'>+	[10][0] = "ISPCSTATRD",</div><div class='add'>+	[11][0] = "ISPBYRPRD",</div><div class='add'>+	[12][0] = "ISPRGBPRD",</div><div class='add'>+	[13][0] = "ISPMCFPRD",</div><div class='add'>+	[14][0] = "ISPMCFPRD1",</div><div class='add'>+	[15][0] = "ISPYUVPRD",</div><div class='add'>+	[16][0] = "ISPMCSCRD",</div><div class='add'>+	[17][0] = "ISPGDCRD",</div><div class='add'>+	[18][0] = "ISPLMERD",</div><div class='add'>+	[22][0] = "ISPXT1",</div><div class='add'>+	[23][0] = "ISPIXT1",</div><div class='ctx'> 	[24][0] = "HDP",</div><div class='ctx'> 	[25][0] = "LSDMA",</div><div class='ctx'> 	[26][0] = "JPEG",</div><div class='ctx'> 	[27][0] = "VPE",</div><div class='add'>+	[28][0] = "VSCH",</div><div class='ctx'> 	[29][0] = "VCNU",</div><div class='ctx'> 	[30][0] = "VCN",</div><div class='add'>+	[1][1] = "ISPXT",</div><div class='add'>+	[2][1] = "ISPIXT",</div><div class='ctx'> 	[3][1] = "DCEDWB",</div><div class='ctx'> 	[4][1] = "DCEDMC",</div><div class='add'>+	[5][1] = "ISPCSISWR",</div><div class='ctx'> 	[6][1] = "MP0",</div><div class='ctx'> 	[7][1] = "MP1",</div><div class='ctx'> 	[8][1] = "MPM",</div><div class='add'>+	[9][1] = "ISPPDPWR",</div><div class='add'>+	[10][1] = "ISPCSTATWR",</div><div class='add'>+	[11][1] = "ISPBYRPWR",</div><div class='add'>+	[12][1] = "ISPRGBPWR",</div><div class='add'>+	[13][1] = "ISPMCFPWR",</div><div class='add'>+	[14][1] = "ISPMWR0",</div><div class='add'>+	[15][1] = "ISPYUVPWR",</div><div class='add'>+	[16][1] = "ISPMCSCWR",</div><div class='add'>+	[17][1] = "ISPGDCWR",</div><div class='add'>+	[18][1] = "ISPLMEWR",</div><div class='add'>+	[20][1] = "ISPMWR2",</div><div class='ctx'> 	[21][1] = "OSSSYS",</div><div class='add'>+	[22][1] = "ISPXT1",</div><div class='add'>+	[23][1] = "ISPIXT1",</div><div class='ctx'> 	[24][1] = "HDP",</div><div class='ctx'> 	[25][1] = "LSDMA",</div><div class='ctx'> 	[26][1] = "JPEG",</div><div class='ctx'> 	[27][1] = "VPE",</div><div class='add'>+	[28][1] = "VSCH",</div><div class='ctx'> 	[29][1] = "VCNU",</div><div class='ctx'> 	[30][1] = "VCN",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const char *mmhub_client_ids_v3_3_1[][2] = {</div><div class='add'>+	[0][0] = "VMC",</div><div class='add'>+	[4][0] = "DCEDMC",</div><div class='add'>+	[6][0] = "MP0",</div><div class='add'>+	[7][0] = "MP1",</div><div class='add'>+	[8][0] = "MPM",</div><div class='add'>+	[24][0] = "HDP",</div><div class='add'>+	[25][0] = "LSDMA",</div><div class='add'>+	[26][0] = "JPEG0",</div><div class='add'>+	[27][0] = "VPE0",</div><div class='add'>+	[28][0] = "VSCH",</div><div class='add'>+	[29][0] = "VCNU0",</div><div class='add'>+	[30][0] = "VCN0",</div><div class='add'>+	[32+1][0] = "ISPXT",</div><div class='add'>+	[32+2][0] = "ISPIXT",</div><div class='add'>+	[32+9][0] = "ISPPDPRD",</div><div class='add'>+	[32+10][0] = "ISPCSTATRD",</div><div class='add'>+	[32+11][0] = "ISPBYRPRD",</div><div class='add'>+	[32+12][0] = "ISPRGBPRD",</div><div class='add'>+	[32+13][0] = "ISPMCFPRD",</div><div class='add'>+	[32+14][0] = "ISPMCFPRD1",</div><div class='add'>+	[32+15][0] = "ISPYUVPRD",</div><div class='add'>+	[32+16][0] = "ISPMCSCRD",</div><div class='add'>+	[32+17][0] = "ISPGDCRD",</div><div class='add'>+	[32+18][0] = "ISPLMERD",</div><div class='add'>+	[32+22][0] = "ISPXT1",</div><div class='add'>+	[32+23][0] = "ISPIXT1",</div><div class='add'>+	[32+26][0] = "JPEG1",</div><div class='add'>+	[32+27][0] = "VPE1",</div><div class='add'>+	[32+29][0] = "VCNU1",</div><div class='add'>+	[32+30][0] = "VCN1",</div><div class='add'>+	[3][1] = "DCEDWB",</div><div class='add'>+	[4][1] = "DCEDMC",</div><div class='add'>+	[6][1] = "MP0",</div><div class='add'>+	[7][1] = "MP1",</div><div class='add'>+	[8][1] = "MPM",</div><div class='add'>+	[21][1] = "OSSSYS",</div><div class='add'>+	[24][1] = "HDP",</div><div class='add'>+	[25][1] = "LSDMA",</div><div class='add'>+	[26][1] = "JPEG0",</div><div class='add'>+	[27][1] = "VPE0",</div><div class='add'>+	[28][1] = "VSCH",</div><div class='add'>+	[29][1] = "VCNU0",</div><div class='add'>+	[30][1] = "VCN0",</div><div class='add'>+	[32+1][1] = "ISPXT",</div><div class='add'>+	[32+2][1] = "ISPIXT",</div><div class='add'>+	[32+5][1] = "ISPCSISWR",</div><div class='add'>+	[32+9][1] = "ISPPDPWR",</div><div class='add'>+	[32+10][1] = "ISPCSTATWR",</div><div class='add'>+	[32+11][1] = "ISPBYRPWR",</div><div class='add'>+	[32+12][1] = "ISPRGBPWR",</div><div class='add'>+	[32+13][1] = "ISPMCFPWR",</div><div class='add'>+	[32+14][1] = "ISPMWR0",</div><div class='add'>+	[32+15][1] = "ISPYUVPWR",</div><div class='add'>+	[32+16][1] = "ISPMCSCWR",</div><div class='add'>+	[32+17][1] = "ISPGDCWR",</div><div class='add'>+	[32+18][1] = "ISPLMEWR",</div><div class='add'>+	[32+19][1] = "ISPMWR1",</div><div class='add'>+	[32+20][1] = "ISPMWR2",</div><div class='add'>+	[32+22][1] = "ISPXT1",</div><div class='add'>+	[32+23][1] = "ISPIXT1",</div><div class='add'>+	[32+26][1] = "JPEG1",</div><div class='add'>+	[32+27][1] = "VPE1",</div><div class='add'>+	[32+29][1] = "VCNU1",</div><div class='add'>+	[32+30][1] = "VCN1",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid,</div><div class='ctx'> 						uint32_t flush_type)</div><div class='ctx'> {</div><div class='hunk'>@@ -98,11 +201,16 @@ mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(3, 3, 0):</div><div class='del'>-	case IP_VERSION(3, 3, 1):</div><div class='add'>+	case IP_VERSION(3, 3, 2):</div><div class='ctx'> 		mmhub_cid = cid &lt; ARRAY_SIZE(mmhub_client_ids_v3_3) ?</div><div class='ctx'> 			    mmhub_client_ids_v3_3[cid][rw] :</div><div class='ctx'> 			    cid == 0x140 ? "UMSCH" : NULL;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(3, 3, 1):</div><div class='add'>+		mmhub_cid = cid &lt; ARRAY_SIZE(mmhub_client_ids_v3_3_1) ?</div><div class='add'>+			    mmhub_client_ids_v3_3_1[cid][rw] :</div><div class='add'>+			    cid == 0x140 ? "UMSCH" : NULL;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		mmhub_cid = NULL;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -359,6 +467,49 @@ static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev-&gt;gart.bo);</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* Program page table base, gart start, gart end */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,</div><div class='add'>+			lower_32_bits(pt_base &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,</div><div class='add'>+			upper_32_bits(pt_base &gt;&gt; 12));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_start &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_start &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_end &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_end &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Disable all contexts except context 0 */</div><div class='add'>+	tmp = 0xfffe;</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp);</div><div class='add'>+</div><div class='add'>+	/* Program saw cntl4 */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regDAGB0_L1TLB_REG_RW_3_3, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regDAGB1_L1TLB_REG_RW_3_3, 3);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	/* GART Enable. */</div><div class='hunk'>@@ -372,6 +523,12 @@ static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	mmhub_v3_3_setup_vmid_config(adev);</div><div class='ctx'> 	mmhub_v3_3_program_invalidation(adev);</div><div class='ctx'> </div><div class='add'>+	/* standalone alone walker init */</div><div class='add'>+	mmhub_v3_3_init_saw_regs(adev);</div><div class='add'>+</div><div class='add'>+	/* enable mmhub tls */</div><div class='add'>+	mmhub_v3_3_enable_tls(adev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -560,7 +717,7 @@ static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	int data;</div><div class='add'>+	u32 data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		*flags = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c<br/>new file mode 100644<br/>index 000000000000..951998454b25<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c</a></div><div class='hunk'>@@ -0,0 +1,647 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "mmhub_v4_1_0.h"</div><div class='add'>+</div><div class='add'>+#include "mmhub/mmhub_4_1_0_offset.h"</div><div class='add'>+#include "mmhub/mmhub_4_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "soc24_enum.h"</div><div class='add'>+</div><div class='add'>+#define regMMVM_L2_CNTL3_DEFAULT				0x80100007</div><div class='add'>+#define regMMVM_L2_CNTL4_DEFAULT				0x000000c1</div><div class='add'>+#define regMMVM_L2_CNTL5_DEFAULT				0x00003fe0</div><div class='add'>+</div><div class='add'>+static const char *mmhub_client_ids_v4_1_0[][2] = {</div><div class='add'>+	[0][0] = "VMC",</div><div class='add'>+	[4][0] = "DCEDMC",</div><div class='add'>+	[6][0] = "MP0",</div><div class='add'>+	[7][0] = "MP1",</div><div class='add'>+	[8][0] = "MPIO",</div><div class='add'>+	[16][0] = "LSDMA",</div><div class='add'>+	[17][0] = "JPEG",</div><div class='add'>+	[19][0] = "VCNU",</div><div class='add'>+	[22][0] = "VSCH",</div><div class='add'>+	[23][0] = "HDP",</div><div class='add'>+	[32+23][0] = "VCNRD",</div><div class='add'>+	[3][1] = "DCEDWB",</div><div class='add'>+	[4][1] = "DCEDMC",</div><div class='add'>+	[6][1] = "MP0",</div><div class='add'>+	[7][1] = "MP1",</div><div class='add'>+	[8][1] = "MPIO",</div><div class='add'>+	[10][1] = "DBGU0",</div><div class='add'>+	[11][1] = "DBGU1",</div><div class='add'>+	[12][1] = "DBGUNBIO",</div><div class='add'>+	[14][1] = "XDP",</div><div class='add'>+	[15][1] = "OSSSYS",</div><div class='add'>+	[16][1] = "LSDMA",</div><div class='add'>+	[17][1] = "JPEG",</div><div class='add'>+	[18][1] = "VCNWR",</div><div class='add'>+	[19][1] = "VCNU",</div><div class='add'>+	[22][1] = "VSCH",</div><div class='add'>+	[23][1] = "HDP",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid,</div><div class='add'>+						uint32_t flush_type)</div><div class='add'>+{</div><div class='add'>+	u32 req = 0;</div><div class='add'>+</div><div class='add'>+	/* invalidate using legacy mode on vmid*/</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,</div><div class='add'>+			    PER_VMID_INVALIDATE_REQ, 1 &lt;&lt; vmid);</div><div class='add'>+	/* Only use legacy inv on mmhub side */</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);</div><div class='add'>+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,</div><div class='add'>+			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);</div><div class='add'>+</div><div class='add'>+	return req;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev,</div><div class='add'>+					      uint32_t status)</div><div class='add'>+{</div><div class='add'>+	uint32_t cid, rw;</div><div class='add'>+	const char *mmhub_cid = NULL;</div><div class='add'>+</div><div class='add'>+	cid = REG_GET_FIELD(status,</div><div class='add'>+			    MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID);</div><div class='add'>+	rw = REG_GET_FIELD(status,</div><div class='add'>+			   MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW);</div><div class='add'>+</div><div class='add'>+	dev_err(adev-&gt;dev,</div><div class='add'>+		"MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n",</div><div class='add'>+		status);</div><div class='add'>+	switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(4, 1, 0):</div><div class='add'>+		mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw];</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		mmhub_cid = NULL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	dev_err(adev-&gt;dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",</div><div class='add'>+		mmhub_cid ? mmhub_cid : "unknown", cid);</div><div class='add'>+	dev_err(adev-&gt;dev, "\t MORE_FAULTS: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t WALKER_ERROR: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t PERMISSION_FAULTS: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t MAPPING_ERROR: 0x%lx\n",</div><div class='add'>+		REG_GET_FIELD(status,</div><div class='add'>+		MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR));</div><div class='add'>+	dev_err(adev-&gt;dev, "\t RW: 0x%x\n", rw);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_setup_vm_pt_regs(struct amdgpu_device *adev,</div><div class='add'>+					  uint32_t vmid, uint64_t page_table_base)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,</div><div class='add'>+			    hub-&gt;ctx_addr_distance * vmid,</div><div class='add'>+			    lower_32_bits(page_table_base));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,</div><div class='add'>+			    hub-&gt;ctx_addr_distance * vmid,</div><div class='add'>+			    upper_32_bits(page_table_base));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_init_gart_aperture_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev-&gt;gart.bo);</div><div class='add'>+</div><div class='add'>+	mmhub_v4_1_0_setup_vm_pt_regs(adev, 0, pt_base);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_start &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_start &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_end &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,</div><div class='add'>+		     (u32)(adev-&gt;gmc.gart_end &gt;&gt; 44));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_init_system_aperture_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint64_t value;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * the new L1 policy will block SRIOV guest from writing</div><div class='add'>+	 * these regs, and they will be programed at host.</div><div class='add'>+	 * so skip programing these regs.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Program the AGP BAR */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev-&gt;gmc.agp_start &gt;&gt; 24);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev-&gt;gmc.agp_end &gt;&gt; 24);</div><div class='add'>+</div><div class='add'>+	/* Program the system aperture low logical page number. */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='add'>+		     min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,</div><div class='add'>+		     max(adev-&gt;gmc.fb_end, adev-&gt;gmc.agp_end) &gt;&gt; 18);</div><div class='add'>+</div><div class='add'>+	/* Set default page address. */</div><div class='add'>+	value = adev-&gt;mem_scratch.gpu_addr - adev-&gt;gmc.vram_start +</div><div class='add'>+		adev-&gt;vm_manager.vram_base_offset;</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,</div><div class='add'>+		     (u32)(value &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,</div><div class='add'>+		     (u32)(value &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	/* Program "protection fault". */</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,</div><div class='add'>+		     (u32)(adev-&gt;dummy_page_addr &gt;&gt; 12));</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,</div><div class='add'>+		     (u32)((u64)adev-&gt;dummy_page_addr &gt;&gt; 44));</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,</div><div class='add'>+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_init_tlb_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* Setup TLB control */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    MTYPE, MTYPE_UC); /* UC, uncached */</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_init_cache_regs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	/* These registers are not accessible to VF-SRIOV.</div><div class='add'>+	 * The PF will program them instead.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Setup L2 cache */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,</div><div class='add'>+			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);</div><div class='add'>+	/* XXX for emulation, Refer to closed source code.*/</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,</div><div class='add'>+			    0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = regMMVM_L2_CNTL3_DEFAULT;</div><div class='add'>+	if (adev-&gt;gmc.translate_further) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,</div><div class='add'>+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);</div><div class='add'>+	} else {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,</div><div class='add'>+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = regMMVM_L2_CNTL4_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = regMMVM_L2_CNTL5_DEFAULT;</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_enable_system_domain(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,</div><div class='add'>+			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_disable_identity_aperture(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* These registers are not accessible to VF-SRIOV.</div><div class='add'>+	 * The PF will program them instead.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0,</div><div class='add'>+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,</div><div class='add'>+		     0xFFFFFFFF);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0,</div><div class='add'>+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,</div><div class='add'>+		     0x0000000F);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0,</div><div class='add'>+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0,</div><div class='add'>+		     regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,</div><div class='add'>+		     0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,</div><div class='add'>+		     0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_setup_vmid_config(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt;= 14; i++) {</div><div class='add'>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,</div><div class='add'>+				    adev-&gt;vm_manager.num_level);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,</div><div class='add'>+				    1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    PAGE_TABLE_BLOCK_SIZE,</div><div class='add'>+				    adev-&gt;vm_manager.block_size - 9);</div><div class='add'>+		/* Send no-retry XNACK on fault to suppress VM fault storm. */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,</div><div class='add'>+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,</div><div class='add'>+				    !amdgpu_noretry);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,</div><div class='add'>+				    i * hub-&gt;ctx_distance, tmp);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance, 0);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance, 0);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance,</div><div class='add'>+				    lower_32_bits(adev-&gt;vm_manager.max_pfn - 1));</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,</div><div class='add'>+				    i * hub-&gt;ctx_addr_distance,</div><div class='add'>+				    upper_32_bits(adev-&gt;vm_manager.max_pfn - 1));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hub-&gt;vm_cntx_cntl = tmp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_program_invalidation(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='add'>+	unsigned i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 18; ++i) {</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,</div><div class='add'>+				    i * hub-&gt;eng_addr_distance, 0xffffffff);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,</div><div class='add'>+				    i * hub-&gt;eng_addr_distance, 0x1f);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mmhub_v4_1_0_gart_enable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* GART Enable. */</div><div class='add'>+	mmhub_v4_1_0_init_gart_aperture_regs(adev);</div><div class='add'>+	mmhub_v4_1_0_init_system_aperture_regs(adev);</div><div class='add'>+	mmhub_v4_1_0_init_tlb_regs(adev);</div><div class='add'>+	mmhub_v4_1_0_init_cache_regs(adev);</div><div class='add'>+</div><div class='add'>+	mmhub_v4_1_0_enable_system_domain(adev);</div><div class='add'>+	mmhub_v4_1_0_disable_identity_aperture(adev);</div><div class='add'>+	mmhub_v4_1_0_setup_vmid_config(adev);</div><div class='add'>+	mmhub_v4_1_0_program_invalidation(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_gart_disable(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='add'>+	u32 tmp;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	/* Disable all tables */</div><div class='add'>+	for (i = 0; i &lt; 16; i++)</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,</div><div class='add'>+				    i * hub-&gt;ctx_distance, 0);</div><div class='add'>+</div><div class='add'>+	/* Setup TLB control */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,</div><div class='add'>+			    ENABLE_ADVANCED_DRIVER_MODEL, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* Setup L2 cache */</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * mmhub_v4_1_0_set_fault_enable_default - update GART/VM fault handling</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @value: true redirects VM faults to the default page</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	/* These registers are not accessible to VF-SRIOV.</div><div class='add'>+	 * The PF will program them instead.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,</div><div class='add'>+			    value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);</div><div class='add'>+	if (!value) {</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+				CRASH_ON_NO_RETRY_FAULT, 1);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,</div><div class='add'>+				CRASH_ON_RETRY_FAULT, 1);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_vmhub_funcs mmhub_v4_1_0_vmhub_funcs = {</div><div class='add'>+	.print_l2_protection_fault_status = mmhub_v4_1_0_print_l2_protection_fault_status,</div><div class='add'>+	.get_invalidate_req = mmhub_v4_1_0_get_invalidate_req,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;adev-&gt;vmhub[AMDGPU_MMHUB0(0)];</div><div class='add'>+</div><div class='add'>+	hub-&gt;ctx0_ptb_addr_lo32 =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0,</div><div class='add'>+				 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);</div><div class='add'>+	hub-&gt;ctx0_ptb_addr_hi32 =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0,</div><div class='add'>+				 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);</div><div class='add'>+	hub-&gt;vm_inv_eng0_sem =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);</div><div class='add'>+	hub-&gt;vm_inv_eng0_req =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);</div><div class='add'>+	hub-&gt;vm_inv_eng0_ack =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);</div><div class='add'>+	hub-&gt;vm_context0_cntl =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);</div><div class='add'>+	hub-&gt;vm_l2_pro_fault_status =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS_LO32);</div><div class='add'>+	hub-&gt;vm_l2_pro_fault_cntl =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);</div><div class='add'>+</div><div class='add'>+	hub-&gt;ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;</div><div class='add'>+	hub-&gt;ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -</div><div class='add'>+		regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;</div><div class='add'>+	hub-&gt;eng_distance = regMMVM_INVALIDATE_ENG1_REQ -</div><div class='add'>+		regMMVM_INVALIDATE_ENG0_REQ;</div><div class='add'>+	hub-&gt;eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -</div><div class='add'>+		regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;</div><div class='add'>+</div><div class='add'>+	hub-&gt;vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |</div><div class='add'>+		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;</div><div class='add'>+</div><div class='add'>+	hub-&gt;vm_l2_bank_select_reserved_cid2 =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);</div><div class='add'>+</div><div class='add'>+	hub-&gt;vm_contexts_disable =</div><div class='add'>+		SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE);</div><div class='add'>+</div><div class='add'>+	hub-&gt;vmhub_funcs = &amp;mmhub_v4_1_0_vmhub_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u64 base;</div><div class='add'>+</div><div class='add'>+	base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);</div><div class='add'>+</div><div class='add'>+	base &amp;= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;</div><div class='add'>+	base &lt;&lt;= 24;</div><div class='add'>+</div><div class='add'>+	return base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) &lt;&lt; 24;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+mmhub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,</div><div class='add'>+					      bool enable)</div><div class='add'>+{</div><div class='add'>+#if 0</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+#endif</div><div class='add'>+	uint32_t def1, data1, def2 = 0, data2 = 0;</div><div class='add'>+#if 0</div><div class='add'>+	def  = data  = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);</div><div class='add'>+#endif</div><div class='add'>+	def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);</div><div class='add'>+	def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+#if 0</div><div class='add'>+		data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;</div><div class='add'>+#endif</div><div class='add'>+		data1 &amp;= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |</div><div class='add'>+			   DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);</div><div class='add'>+</div><div class='add'>+		data2 &amp;= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |</div><div class='add'>+			   DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);</div><div class='add'>+	} else {</div><div class='add'>+#if 0</div><div class='add'>+		data &amp;= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;</div><div class='add'>+#endif</div><div class='add'>+		data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |</div><div class='add'>+			  DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);</div><div class='add'>+</div><div class='add'>+		data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK |</div><div class='add'>+			  DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#if 0</div><div class='add'>+	if (def != data)</div><div class='add'>+		WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);</div><div class='add'>+#endif</div><div class='add'>+	if (def1 != data1)</div><div class='add'>+		WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);</div><div class='add'>+</div><div class='add'>+	if (def2 != data2)</div><div class='add'>+		WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+mmhub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,</div><div class='add'>+					     bool enable)</div><div class='add'>+{</div><div class='add'>+#if 0</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+</div><div class='add'>+	def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;</div><div class='add'>+	else</div><div class='add'>+		data &amp;= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;</div><div class='add'>+</div><div class='add'>+	if (def != data)</div><div class='add'>+		WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mmhub_v4_1_0_set_clockgating(struct amdgpu_device *adev,</div><div class='add'>+					enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_MC_MGCG)</div><div class='add'>+		mmhub_v4_1_0_update_medium_grain_clock_gating(adev,</div><div class='add'>+				state == AMD_CG_STATE_GATE);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_MC_LS)</div><div class='add'>+		mmhub_v4_1_0_update_medium_grain_light_sleep(adev,</div><div class='add'>+				state == AMD_CG_STATE_GATE);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmhub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)</div><div class='add'>+{</div><div class='add'>+#if 0</div><div class='add'>+	int data;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		*flags = 0;</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_MC_MGCG */</div><div class='add'>+	if (data &amp; MM_ATC_L2_MISC_CG__ENABLE_MASK)</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_MC_MGCG;</div><div class='add'>+</div><div class='add'>+	/* AMD_CG_SUPPORT_MC_LS */</div><div class='add'>+	if (data &amp; MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_MC_LS;</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_mmhub_funcs mmhub_v4_1_0_funcs = {</div><div class='add'>+	.init = mmhub_v4_1_0_init,</div><div class='add'>+	.get_fb_location = mmhub_v4_1_0_get_fb_location,</div><div class='add'>+	.get_mc_fb_offset = mmhub_v4_1_0_get_mc_fb_offset,</div><div class='add'>+	.gart_enable = mmhub_v4_1_0_gart_enable,</div><div class='add'>+	.set_fault_enable_default = mmhub_v4_1_0_set_fault_enable_default,</div><div class='add'>+	.gart_disable = mmhub_v4_1_0_gart_disable,</div><div class='add'>+	.set_clockgating = mmhub_v4_1_0_set_clockgating,</div><div class='add'>+	.get_clockgating = mmhub_v4_1_0_get_clockgating,</div><div class='add'>+	.setup_vm_pt_regs = mmhub_v4_1_0_setup_vm_pt_regs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.h<br/>new file mode 100644<br/>index 000000000000..3902d653353c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#ifndef __MMHUB_V4_1_0_H__</div><div class='add'>+#define __MMHUB_V4_1_0_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_mmhub_funcs mmhub_v4_1_0_funcs;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c<br/>index 1b7da4aff2b8..fe0710b55c3a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c</a></div><div class='hunk'>@@ -198,6 +198,36 @@ static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)</div><div class='ctx'> 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */</div><div class='add'>+static void mmhub_v9_4_init_snoop_override_regs(struct amdgpu_device *adev, int hubid)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t distance = mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -</div><div class='add'>+			    mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;</div><div class='add'>+	uint32_t huboffset = hubid * MMHUB_INSTANCE_REGISTER_OFFSET;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 5 - (2 * hubid); i++) {</div><div class='add'>+		/* DAGB instances 0 to 4 are in hub0 and 5 to 7 are in hub1 */</div><div class='add'>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE,</div><div class='add'>+			huboffset + i * distance);</div><div class='add'>+		tmp |= (1 &lt;&lt; 15); /* SDMA client is BIT15 */</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE,</div><div class='add'>+			huboffset + i * distance, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE,</div><div class='add'>+			huboffset + i * distance);</div><div class='add'>+		tmp |= (1 &lt;&lt; 15);</div><div class='add'>+		WREG32_SOC15_OFFSET(MMHUB, 0,</div><div class='add'>+			mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE,</div><div class='add'>+			huboffset + i * distance, tmp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t tmp;</div><div class='hunk'>@@ -392,6 +422,7 @@ static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 			mmhub_v9_4_init_cache_regs(adev, i);</div><div class='ctx'> </div><div class='add'>+		mmhub_v9_4_init_snoop_override_regs(adev, i);</div><div class='ctx'> 		mmhub_v9_4_enable_system_domain(adev, i);</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 			mmhub_v9_4_disable_identity_aperture(adev, i);</div><div class='hunk'>@@ -657,7 +688,7 @@ static int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	int data, data1;</div><div class='add'>+	u32 data, data1;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		*flags = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h<br/>new file mode 100644<br/>index 000000000000..6f749814929f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h</a></div><div class='hunk'>@@ -0,0 +1,144 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __MMSCH_V5_0_H__</div><div class='add'>+#define __MMSCH_V5_0_H__</div><div class='add'>+</div><div class='add'>+#include "amdgpu_vcn.h"</div><div class='add'>+</div><div class='add'>+#define MMSCH_VERSION_MAJOR	5</div><div class='add'>+#define MMSCH_VERSION_MINOR	0</div><div class='add'>+#define MMSCH_VERSION	(MMSCH_VERSION_MAJOR &lt;&lt; 16 | MMSCH_VERSION_MINOR)</div><div class='add'>+</div><div class='add'>+#define RB_ENABLED (1 &lt;&lt; 0)</div><div class='add'>+#define RB4_ENABLED (1 &lt;&lt; 1)</div><div class='add'>+</div><div class='add'>+#define MMSCH_VF_ENGINE_STATUS__PASS 0x1</div><div class='add'>+</div><div class='add'>+#define MMSCH_VF_MAILBOX_RESP__OK                      0x1</div><div class='add'>+#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE              0x2</div><div class='add'>+#define MMSCH_VF_MAILBOX_RESP__FAILED                  0x3</div><div class='add'>+#define MMSCH_VF_MAILBOX_RESP__FAILED_SMALL_CTX_SIZE   0x4</div><div class='add'>+#define MMSCH_VF_MAILBOX_RESP__UNKNOWN_CMD             0x5</div><div class='add'>+</div><div class='add'>+enum mmsch_v5_0_command_type {</div><div class='add'>+	MMSCH_COMMAND__DIRECT_REG_WRITE = 0,</div><div class='add'>+	MMSCH_COMMAND__DIRECT_REG_POLLING = 2,</div><div class='add'>+	MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,</div><div class='add'>+	MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,</div><div class='add'>+	MMSCH_COMMAND__END = 0xf</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_table_info {</div><div class='add'>+	uint32_t init_status;</div><div class='add'>+	uint32_t table_offset;</div><div class='add'>+	uint32_t table_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_init_header {</div><div class='add'>+	uint32_t version;</div><div class='add'>+	uint32_t total_size;</div><div class='add'>+	struct mmsch_v5_0_table_info vcn0;</div><div class='add'>+	struct mmsch_v5_0_table_info mjpegdec0[5];</div><div class='add'>+	struct mmsch_v5_0_table_info mjpegdec1[5];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_direct_reg_header {</div><div class='add'>+	uint32_t reg_offset   : 28;</div><div class='add'>+	uint32_t command_type : 4;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_indirect_reg_header {</div><div class='add'>+	uint32_t reg_offset    : 20;</div><div class='add'>+	uint32_t reg_idx_space : 8;</div><div class='add'>+	uint32_t command_type  : 4;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_direct_write {</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_reg_header cmd_header;</div><div class='add'>+	uint32_t reg_value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_direct_read_modify_write {</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_reg_header cmd_header;</div><div class='add'>+	uint32_t write_data;</div><div class='add'>+	uint32_t mask_value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_direct_polling {</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_reg_header cmd_header;</div><div class='add'>+	uint32_t mask_value;</div><div class='add'>+	uint32_t wait_value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_end {</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_reg_header cmd_header;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mmsch_v5_0_cmd_indirect_write {</div><div class='add'>+	struct mmsch_v5_0_cmd_indirect_reg_header cmd_header;</div><div class='add'>+	uint32_t reg_value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \</div><div class='add'>+	size = sizeof(struct mmsch_v5_0_cmd_direct_read_modify_write); \</div><div class='add'>+	size_dw = size / 4; \</div><div class='add'>+	direct_rd_mod_wt.cmd_header.reg_offset = reg; \</div><div class='add'>+	direct_rd_mod_wt.mask_value = mask; \</div><div class='add'>+	direct_rd_mod_wt.write_data = data; \</div><div class='add'>+	memcpy((void *)table_loc, &amp;direct_rd_mod_wt, size); \</div><div class='add'>+	table_loc += size_dw; \</div><div class='add'>+	table_size += size_dw; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MMSCH_V5_0_INSERT_DIRECT_WT(reg, value) { \</div><div class='add'>+	size = sizeof(struct mmsch_v5_0_cmd_direct_write); \</div><div class='add'>+	size_dw = size / 4; \</div><div class='add'>+	direct_wt.cmd_header.reg_offset = reg; \</div><div class='add'>+	direct_wt.reg_value = value; \</div><div class='add'>+	memcpy((void *)table_loc, &amp;direct_wt, size); \</div><div class='add'>+	table_loc += size_dw; \</div><div class='add'>+	table_size += size_dw; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MMSCH_V5_0_INSERT_DIRECT_POLL(reg, mask, wait) { \</div><div class='add'>+	size = sizeof(struct mmsch_v5_0_cmd_direct_polling); \</div><div class='add'>+	size_dw = size / 4; \</div><div class='add'>+	direct_poll.cmd_header.reg_offset = reg; \</div><div class='add'>+	direct_poll.mask_value = mask; \</div><div class='add'>+	direct_poll.wait_value = wait; \</div><div class='add'>+	memcpy((void *)table_loc, &amp;direct_poll, size); \</div><div class='add'>+	table_loc += size_dw; \</div><div class='add'>+	table_size += size_dw; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MMSCH_V5_0_INSERT_END() { \</div><div class='add'>+	size = sizeof(struct mmsch_v5_0_cmd_end); \</div><div class='add'>+	size_dw = size / 4; \</div><div class='add'>+	memcpy((void *)table_loc, &amp;end, size); \</div><div class='add'>+	table_loc += size_dw; \</div><div class='add'>+	table_size += size_dw; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c<br/>index a2bd2c3b1ef9..9a40107a0869 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c</a></div><div class='hunk'>@@ -93,7 +93,7 @@ static int xgpu_ai_poll_ack(struct amdgpu_device *adev)</div><div class='ctx'> 		timeout -= 5;</div><div class='ctx'> 	} while (timeout &gt; 1);</div><div class='ctx'> </div><div class='del'>-	pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);</div><div class='add'>+	dev_err(adev-&gt;dev, "Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);</div><div class='ctx'> </div><div class='ctx'> 	return -ETIME;</div><div class='ctx'> }</div><div class='hunk'>@@ -111,7 +111,7 @@ static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)</div><div class='ctx'> 		timeout -= 10;</div><div class='ctx'> 	} while (timeout &gt; 1);</div><div class='ctx'> </div><div class='del'>-	pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);</div><div class='add'>+	dev_err(adev-&gt;dev, "Doesn't get msg:%d from pf, error=%d\n", event, r);</div><div class='ctx'> </div><div class='ctx'> 	return -ETIME;</div><div class='ctx'> }</div><div class='hunk'>@@ -132,7 +132,7 @@ static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,</div><div class='ctx'> 		xgpu_ai_mailbox_set_valid(adev, false);</div><div class='ctx'> 		trn = xgpu_ai_peek_ack(adev);</div><div class='ctx'> 		if (trn) {</div><div class='del'>-			pr_err("trn=%x ACK should not assert! wait again !\n", trn);</div><div class='add'>+			dev_err_ratelimited(adev-&gt;dev, "trn=%x ACK should not assert! wait again !\n", trn);</div><div class='ctx'> 			msleep(1);</div><div class='ctx'> 		}</div><div class='ctx'> 	} while(trn);</div><div class='hunk'>@@ -155,7 +155,7 @@ static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,</div><div class='ctx'> 	/* start to poll ack */</div><div class='ctx'> 	r = xgpu_ai_poll_ack(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		pr_err("Doesn't get ack from pf, continue\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Doesn't get ack from pf, continue\n");</div><div class='ctx'> </div><div class='ctx'> 	xgpu_ai_mailbox_set_valid(adev, false);</div><div class='ctx'> }</div><div class='hunk'>@@ -173,7 +173,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,</div><div class='ctx'> 		req == IDH_REQ_GPU_RESET_ACCESS) {</div><div class='ctx'> 		r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");</div><div class='add'>+			dev_err(adev-&gt;dev, "Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> 		/* Retrieve checksum from mailbox2 */</div><div class='hunk'>@@ -231,7 +231,7 @@ static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,</div><div class='ctx'> 					struct amdgpu_irq_src *source,</div><div class='ctx'> 					struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	DRM_DEBUG("get ack intr and do nothing.\n");</div><div class='add'>+	dev_dbg(adev-&gt;dev, "get ack intr and do nothing.\n");</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -249,52 +249,80 @@ static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void xgpu_ai_mailbox_flr_work(struct work_struct *work)</div><div class='add'>+static void xgpu_ai_ready_to_reset(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);</div><div class='del'>-	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='del'>-	int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT;</div><div class='del'>-</div><div class='del'>-	/* block amdgpu_gpu_recover till msg FLR COMPLETE received,</div><div class='del'>-	 * otherwise the mailbox msg will be ruined/reseted by</div><div class='del'>-	 * the VF FLR.</div><div class='del'>-	 */</div><div class='del'>-	if (atomic_cmpxchg(&amp;adev-&gt;reset_domain-&gt;in_gpu_reset, 0, 1) != 0)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	down_write(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-</div><div class='del'>-	amdgpu_virt_fini_data_exchange(adev);</div><div class='del'>-</div><div class='ctx'> 	xgpu_ai_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static int xgpu_ai_wait_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT;</div><div class='ctx'> 	do {</div><div class='del'>-		if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)</div><div class='del'>-			goto flr_done;</div><div class='del'>-</div><div class='add'>+		if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) {</div><div class='add'>+			dev_dbg(adev-&gt;dev, "Got AI IDH_FLR_NOTIFICATION_CMPL after %d ms\n", AI_MAILBOX_POLL_FLR_TIMEDOUT - timeout);</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='ctx'> 		msleep(10);</div><div class='ctx'> 		timeout -= 10;</div><div class='ctx'> 	} while (timeout &gt; 1);</div><div class='ctx'> </div><div class='del'>-flr_done:</div><div class='del'>-	atomic_set(&amp;adev-&gt;reset_domain-&gt;in_gpu_reset, 0);</div><div class='del'>-	up_write(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	dev_dbg(adev-&gt;dev, "waiting AI IDH_FLR_NOTIFICATION_CMPL timeout\n");</div><div class='add'>+	return -ETIME;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xgpu_ai_mailbox_flr_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);</div><div class='add'>+	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='add'>+	struct amdgpu_reset_context reset_context = { 0 };</div><div class='add'>+</div><div class='add'>+	amdgpu_virt_fini_data_exchange(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* Trigger recovery for world switch failure if no TDR */</div><div class='ctx'> 	if (amdgpu_device_should_recover_gpu(adev)</div><div class='ctx'> 		&amp;&amp; (!amdgpu_device_has_job_running(adev) ||</div><div class='ctx'> 			adev-&gt;sdma_timeout == MAX_SCHEDULE_TIMEOUT)) {</div><div class='del'>-		struct amdgpu_reset_context reset_context;</div><div class='del'>-		memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='ctx'> </div><div class='ctx'> 		reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 		reset_context.reset_req_dev = adev;</div><div class='ctx'> 		clear_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='add'>+		set_bit(AMDGPU_HOST_FLR, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void xgpu_ai_mailbox_req_bad_pages_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, req_bad_pages_work);</div><div class='add'>+	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='add'>+</div><div class='add'>+	if (down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_virt_fini_data_exchange(adev);</div><div class='add'>+		amdgpu_virt_request_bad_pages(adev);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xgpu_ai_mailbox_handle_bad_pages_work - Reinitialize the data exchange region to get fresh bad page information</div><div class='add'>+ * @work: pointer to the work_struct</div><div class='add'>+ *</div><div class='add'>+ * This work handler is triggered when bad pages are ready, and it reinitializes</div><div class='add'>+ * the data exchange region to retrieve updated bad page information from the host.</div><div class='add'>+ */</div><div class='add'>+static void xgpu_ai_mailbox_handle_bad_pages_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, handle_bad_pages_work);</div><div class='add'>+	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='add'>+</div><div class='add'>+	if (down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_virt_fini_data_exchange(adev);</div><div class='add'>+		amdgpu_virt_init_data_exchange(adev);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				       struct amdgpu_irq_src *src,</div><div class='ctx'> 				       unsigned type,</div><div class='hunk'>@@ -314,26 +342,47 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				   struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='ctx'> 	enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='ctx'> 	switch (event) {</div><div class='del'>-		case IDH_FLR_NOTIFICATION:</div><div class='del'>-		if (amdgpu_sriov_runtime(adev) &amp;&amp; !amdgpu_in_reset(adev))</div><div class='add'>+	case IDH_RAS_BAD_PAGES_READY:</div><div class='add'>+		xgpu_ai_mailbox_send_ack(adev);</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			schedule_work(&amp;adev-&gt;virt.handle_bad_pages_work);</div><div class='add'>+		break;</div><div class='add'>+	case IDH_RAS_BAD_PAGES_NOTIFICATION:</div><div class='add'>+		xgpu_ai_mailbox_send_ack(adev);</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			schedule_work(&amp;adev-&gt;virt.req_bad_pages_work);</div><div class='add'>+		break;</div><div class='add'>+	case IDH_UNRECOV_ERR_NOTIFICATION:</div><div class='add'>+		xgpu_ai_mailbox_send_ack(adev);</div><div class='add'>+		ras-&gt;is_rma = true;</div><div class='add'>+		dev_err(adev-&gt;dev, "VF is in an unrecoverable state. Runtime Services are halted.\n");</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='ctx'> 			WARN_ONCE(!amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='del'>-								&amp;adev-&gt;virt.flr_work),</div><div class='del'>-				  "Failed to queue work! at %s",</div><div class='del'>-				  __func__);</div><div class='add'>+					&amp;adev-&gt;virt.flr_work),</div><div class='add'>+					"Failed to queue work! at %s",</div><div class='add'>+					__func__);</div><div class='ctx'> 		break;</div><div class='del'>-		case IDH_QUERY_ALIVE:</div><div class='del'>-			xgpu_ai_mailbox_send_ack(adev);</div><div class='del'>-			break;</div><div class='del'>-		/* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore</div><div class='del'>-		 * it byfar since that polling thread will handle it,</div><div class='del'>-		 * other msg like flr complete is not handled here.</div><div class='del'>-		 */</div><div class='del'>-		case IDH_CLR_MSG_BUF:</div><div class='del'>-		case IDH_FLR_NOTIFICATION_CMPL:</div><div class='del'>-		case IDH_READY_TO_ACCESS_GPU:</div><div class='del'>-		default:</div><div class='add'>+	case IDH_FLR_NOTIFICATION:</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			WARN_ONCE(!amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='add'>+						&amp;adev-&gt;virt.flr_work),</div><div class='add'>+					"Failed to queue work! at %s",</div><div class='add'>+					__func__);</div><div class='add'>+		break;</div><div class='add'>+	case IDH_QUERY_ALIVE:</div><div class='add'>+		xgpu_ai_mailbox_send_ack(adev);</div><div class='add'>+		break;</div><div class='add'>+	/* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore</div><div class='add'>+	 * it byfar since that polling thread will handle it,</div><div class='add'>+	 * other msg like flr complete is not handled here.</div><div class='add'>+	 */</div><div class='add'>+	case IDH_CLR_MSG_BUF:</div><div class='add'>+	case IDH_FLR_NOTIFICATION_CMPL:</div><div class='add'>+	case IDH_READY_TO_ACCESS_GPU:</div><div class='add'>+	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -389,6 +438,8 @@ int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	INIT_WORK(&amp;adev-&gt;virt.flr_work, xgpu_ai_mailbox_flr_work);</div><div class='add'>+	INIT_WORK(&amp;adev-&gt;virt.req_bad_pages_work, xgpu_ai_mailbox_req_bad_pages_work);</div><div class='add'>+	INIT_WORK(&amp;adev-&gt;virt.handle_bad_pages_work, xgpu_ai_mailbox_handle_bad_pages_work);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -410,12 +461,21 @@ static void xgpu_ai_ras_poison_handler(struct amdgpu_device *adev,</div><div class='ctx'> 	xgpu_ai_send_access_requests(adev, IDH_RAS_POISON);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool xgpu_ai_rcvd_ras_intr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	enum idh_event msg = xgpu_ai_mailbox_peek_msg(adev);</div><div class='add'>+</div><div class='add'>+	return (msg == IDH_RAS_ERROR_DETECTED || msg == 0xFFFFFFFF);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_virt_ops xgpu_ai_virt_ops = {</div><div class='ctx'> 	.req_full_gpu	= xgpu_ai_request_full_gpu_access,</div><div class='ctx'> 	.rel_full_gpu	= xgpu_ai_release_full_gpu_access,</div><div class='ctx'> 	.reset_gpu = xgpu_ai_request_reset,</div><div class='del'>-	.wait_reset = NULL,</div><div class='add'>+	.ready_to_reset = xgpu_ai_ready_to_reset,</div><div class='add'>+	.wait_reset = xgpu_ai_wait_reset,</div><div class='ctx'> 	.trans_msg = xgpu_ai_mailbox_trans_msg,</div><div class='ctx'> 	.req_init_data  = xgpu_ai_request_init_data,</div><div class='ctx'> 	.ras_poison_handler = xgpu_ai_ras_poison_handler,</div><div class='add'>+	.rcvd_ras_intr = xgpu_ai_rcvd_ras_intr,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h<br/>index c520b2fabfb9..874b9f8f9804 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h</a></div><div class='hunk'>@@ -40,6 +40,7 @@ enum idh_request {</div><div class='ctx'> 	IDH_LOG_VF_ERROR       = 200,</div><div class='ctx'> 	IDH_READY_TO_RESET 	= 201,</div><div class='ctx'> 	IDH_RAS_POISON  = 202,</div><div class='add'>+	IDH_REQ_RAS_BAD_PAGES = 205,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum idh_event {</div><div class='hunk'>@@ -51,7 +52,12 @@ enum idh_event {</div><div class='ctx'> 	IDH_FAIL,</div><div class='ctx'> 	IDH_QUERY_ALIVE,</div><div class='ctx'> 	IDH_REQ_GPU_INIT_DATA_READY,</div><div class='del'>-</div><div class='add'>+	IDH_RAS_POISON_READY,</div><div class='add'>+	IDH_PF_SOFT_FLR_NOTIFICATION,</div><div class='add'>+	IDH_RAS_ERROR_DETECTED,</div><div class='add'>+	IDH_RAS_BAD_PAGES_READY = 15,</div><div class='add'>+	IDH_RAS_BAD_PAGES_NOTIFICATION = 16,</div><div class='add'>+	IDH_UNRECOV_ERR_NOTIFICATION = 17,</div><div class='ctx'> 	IDH_TEXT_MESSAGE = 255,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c<br/>index 77f5b55decf9..e7cd07383d56 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c</a></div><div class='hunk'>@@ -61,15 +61,20 @@ static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)</div><div class='ctx'> static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,</div><div class='ctx'> 				   enum idh_event event)</div><div class='ctx'> {</div><div class='add'>+	int r = 0;</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);</div><div class='del'>-	if (reg != event)</div><div class='add'>+	if (reg == IDH_FAIL)</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+	if (reg == IDH_UNRECOV_ERR_NOTIFICATION)</div><div class='add'>+		r = -ENODEV;</div><div class='add'>+	else if (reg != event)</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> </div><div class='ctx'> 	xgpu_nv_mailbox_send_ack(adev);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)</div><div class='hunk'>@@ -91,7 +96,7 @@ static int xgpu_nv_poll_ack(struct amdgpu_device *adev)</div><div class='ctx'> 		timeout -= 5;</div><div class='ctx'> 	} while (timeout &gt; 1);</div><div class='ctx'> </div><div class='del'>-	pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", NV_MAILBOX_POLL_ACK_TIMEDOUT);</div><div class='add'>+	dev_err(adev-&gt;dev, "Doesn't get TRN_MSG_ACK from pf in %d msec \n", NV_MAILBOX_POLL_ACK_TIMEDOUT);</div><div class='ctx'> </div><div class='ctx'> 	return -ETIME;</div><div class='ctx'> }</div><div class='hunk'>@@ -100,19 +105,31 @@ static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='ctx'> 	uint64_t timeout, now;</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='ctx'> 	now = (uint64_t)ktime_to_ms(ktime_get());</div><div class='ctx'> 	timeout = now + NV_MAILBOX_POLL_MSG_TIMEDOUT;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		r = xgpu_nv_mailbox_rcv_msg(adev, event);</div><div class='del'>-		if (!r)</div><div class='add'>+		if (!r) {</div><div class='add'>+			dev_dbg(adev-&gt;dev, "rcv_msg 0x%x after %llu ms\n",</div><div class='add'>+					event, NV_MAILBOX_POLL_MSG_TIMEDOUT - timeout + now);</div><div class='ctx'> 			return 0;</div><div class='add'>+		} else if (r == -ENODEV) {</div><div class='add'>+			if (!amdgpu_ras_is_rma(adev)) {</div><div class='add'>+				ras-&gt;is_rma = true;</div><div class='add'>+				dev_err(adev-&gt;dev, "VF is in an unrecoverable state. "</div><div class='add'>+						"Runtime Services are halted.\n");</div><div class='add'>+			}</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		msleep(10);</div><div class='ctx'> 		now = (uint64_t)ktime_to_ms(ktime_get());</div><div class='ctx'> 	} while (timeout &gt; now);</div><div class='ctx'> </div><div class='add'>+	dev_dbg(adev-&gt;dev, "nv_poll_msg timed out\n");</div><div class='ctx'> </div><div class='ctx'> 	return -ETIME;</div><div class='ctx'> }</div><div class='hunk'>@@ -133,11 +150,12 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,</div><div class='ctx'> 		xgpu_nv_mailbox_set_valid(adev, false);</div><div class='ctx'> 		trn = xgpu_nv_peek_ack(adev);</div><div class='ctx'> 		if (trn) {</div><div class='del'>-			pr_err("trn=%x ACK should not assert! wait again !\n", trn);</div><div class='add'>+			dev_err_ratelimited(adev-&gt;dev, "trn=%x ACK should not assert! wait again !\n", trn);</div><div class='ctx'> 			msleep(1);</div><div class='ctx'> 		}</div><div class='ctx'> 	} while (trn);</div><div class='ctx'> </div><div class='add'>+	dev_dbg(adev-&gt;dev, "trans_msg req = 0x%x, data1 = 0x%x\n", req, data1);</div><div class='ctx'> 	WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);</div><div class='ctx'> 	WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);</div><div class='ctx'> 	WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);</div><div class='hunk'>@@ -147,7 +165,7 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,</div><div class='ctx'> 	/* start to poll ack */</div><div class='ctx'> 	r = xgpu_nv_poll_ack(adev);</div><div class='ctx'> 	if (r)</div><div class='del'>-		pr_err("Doesn't get ack from pf, continue\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "Doesn't get ack from pf, continue\n");</div><div class='ctx'> </div><div class='ctx'> 	xgpu_nv_mailbox_set_valid(adev, false);</div><div class='ctx'> }</div><div class='hunk'>@@ -155,10 +173,18 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,</div><div class='ctx'> static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev,</div><div class='ctx'> 			enum idh_request req, u32 data1, u32 data2, u32 data3)</div><div class='ctx'> {</div><div class='del'>-	int r, retry = 1;</div><div class='add'>+	struct amdgpu_virt *virt = &amp;adev-&gt;virt;</div><div class='add'>+	int r = 0, retry = 1;</div><div class='ctx'> 	enum idh_event event = -1;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;virt-&gt;access_req_mutex);</div><div class='ctx'> send_request:</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_rma(adev)) {</div><div class='add'>+		r = -ENODEV;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3);</div><div class='ctx'> </div><div class='ctx'> 	switch (req) {</div><div class='hunk'>@@ -174,6 +200,15 @@ send_request:</div><div class='ctx'> 		if (data1 != 0)</div><div class='ctx'> 			event = IDH_RAS_POISON_READY;</div><div class='ctx'> 		break;</div><div class='add'>+	case IDH_REQ_RAS_ERROR_COUNT:</div><div class='add'>+		event = IDH_RAS_ERROR_COUNT_READY;</div><div class='add'>+		break;</div><div class='add'>+	case IDH_REQ_RAS_CPER_DUMP:</div><div class='add'>+		event = IDH_RAS_CPER_DUMP_READY;</div><div class='add'>+		break;</div><div class='add'>+	case IDH_REQ_RAS_CHK_CRITI:</div><div class='add'>+		event = IDH_REQ_RAS_CHK_CRITI_READY;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -181,22 +216,30 @@ send_request:</div><div class='ctx'> 	if (event != -1) {</div><div class='ctx'> 		r = xgpu_nv_poll_msg(adev, event);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			if (retry++ &lt; 2)</div><div class='add'>+			if (retry++ &lt; 5)</div><div class='ctx'> 				goto send_request;</div><div class='ctx'> </div><div class='ctx'> 			if (req != IDH_REQ_GPU_INIT_DATA) {</div><div class='del'>-				pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);</div><div class='del'>-				return r;</div><div class='add'>+				dev_err(adev-&gt;dev, "Doesn't get msg:%d from pf, error=%d\n", event, r);</div><div class='add'>+				goto out;</div><div class='ctx'> 			} else /* host doesn't support REQ_GPU_INIT_DATA handshake */</div><div class='ctx'> 				adev-&gt;virt.req_init_data_ver = 0;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			if (req == IDH_REQ_GPU_INIT_DATA) {</div><div class='del'>-				adev-&gt;virt.req_init_data_ver =</div><div class='del'>-					RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);</div><div class='del'>-</div><div class='del'>-				/* assume V1 in case host doesn't set version number */</div><div class='del'>-				if (adev-&gt;virt.req_init_data_ver &lt; 1)</div><div class='del'>-					adev-&gt;virt.req_init_data_ver = 1;</div><div class='add'>+				switch (RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1)) {</div><div class='add'>+				case GPU_CRIT_REGION_V2:</div><div class='add'>+					adev-&gt;virt.req_init_data_ver = GPU_CRIT_REGION_V2;</div><div class='add'>+					adev-&gt;virt.init_data_header.offset =</div><div class='add'>+						RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);</div><div class='add'>+					adev-&gt;virt.init_data_header.size_kb =</div><div class='add'>+						RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW3);</div><div class='add'>+					break;</div><div class='add'>+				default:</div><div class='add'>+					adev-&gt;virt.req_init_data_ver = GPU_CRIT_REGION_V1;</div><div class='add'>+					adev-&gt;virt.init_data_header.offset = -1;</div><div class='add'>+					adev-&gt;virt.init_data_header.size_kb = 0;</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -207,7 +250,10 @@ send_request:</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;virt-&gt;access_req_mutex);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,</div><div class='hunk'>@@ -254,14 +300,15 @@ static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> static int xgpu_nv_request_init_data(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);</div><div class='add'>+	return xgpu_nv_send_access_requests_with_param(adev, IDH_REQ_GPU_INIT_DATA,</div><div class='add'>+			0, GPU_CRIT_REGION_V2, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,</div><div class='ctx'> 					struct amdgpu_irq_src *source,</div><div class='ctx'> 					struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	DRM_DEBUG("get ack intr and do nothing.\n");</div><div class='add'>+	dev_dbg(adev-&gt;dev, "get ack intr and do nothing.\n");</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -282,36 +329,34 @@ static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void xgpu_nv_mailbox_flr_work(struct work_struct *work)</div><div class='add'>+static void xgpu_nv_ready_to_reset(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);</div><div class='del'>-	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='del'>-	int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;</div><div class='del'>-</div><div class='del'>-	/* block amdgpu_gpu_recover till msg FLR COMPLETE received,</div><div class='del'>-	 * otherwise the mailbox msg will be ruined/reseted by</div><div class='del'>-	 * the VF FLR.</div><div class='del'>-	 */</div><div class='del'>-	if (atomic_cmpxchg(&amp;adev-&gt;reset_domain-&gt;in_gpu_reset, 0, 1) != 0)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	down_write(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='del'>-</div><div class='del'>-	amdgpu_virt_fini_data_exchange(adev);</div><div class='del'>-</div><div class='ctx'> 	xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static int xgpu_nv_wait_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;</div><div class='ctx'> 	do {</div><div class='del'>-		if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)</div><div class='del'>-			goto flr_done;</div><div class='del'>-</div><div class='add'>+		if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) {</div><div class='add'>+			dev_dbg(adev-&gt;dev, "Got NV IDH_FLR_NOTIFICATION_CMPL after %d ms\n", NV_MAILBOX_POLL_FLR_TIMEDOUT - timeout);</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='ctx'> 		msleep(10);</div><div class='ctx'> 		timeout -= 10;</div><div class='ctx'> 	} while (timeout &gt; 1);</div><div class='ctx'> </div><div class='del'>-flr_done:</div><div class='del'>-	atomic_set(&amp;adev-&gt;reset_domain-&gt;in_gpu_reset, 0);</div><div class='del'>-	up_write(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	dev_dbg(adev-&gt;dev, "waiting NV IDH_FLR_NOTIFICATION_CMPL timeout\n");</div><div class='add'>+	return -ETIME;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xgpu_nv_mailbox_flr_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);</div><div class='add'>+	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='add'>+	struct amdgpu_reset_context reset_context = { 0 };</div><div class='add'>+</div><div class='add'>+	amdgpu_virt_fini_data_exchange(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* Trigger recovery for world switch failure if no TDR */</div><div class='ctx'> 	if (amdgpu_device_should_recover_gpu(adev)</div><div class='hunk'>@@ -320,17 +365,47 @@ flr_done:</div><div class='ctx'> 		adev-&gt;gfx_timeout == MAX_SCHEDULE_TIMEOUT ||</div><div class='ctx'> 		adev-&gt;compute_timeout == MAX_SCHEDULE_TIMEOUT ||</div><div class='ctx'> 		adev-&gt;video_timeout == MAX_SCHEDULE_TIMEOUT)) {</div><div class='del'>-		struct amdgpu_reset_context reset_context;</div><div class='del'>-		memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='ctx'> </div><div class='ctx'> 		reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 		reset_context.reset_req_dev = adev;</div><div class='ctx'> 		clear_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='add'>+		set_bit(AMDGPU_HOST_FLR, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void xgpu_nv_mailbox_req_bad_pages_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, req_bad_pages_work);</div><div class='add'>+	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='add'>+</div><div class='add'>+	if (down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_virt_fini_data_exchange(adev);</div><div class='add'>+		amdgpu_virt_request_bad_pages(adev);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xgpu_nv_mailbox_handle_bad_pages_work - Reinitialize the data exchange region to get fresh bad page information</div><div class='add'>+ * @work: pointer to the work_struct</div><div class='add'>+ *</div><div class='add'>+ * This work handler is triggered when bad pages are ready, and it reinitializes</div><div class='add'>+ * the data exchange region to retrieve updated bad page information from the host.</div><div class='add'>+ */</div><div class='add'>+static void xgpu_nv_mailbox_handle_bad_pages_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, handle_bad_pages_work);</div><div class='add'>+	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='add'>+</div><div class='add'>+	if (down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_virt_fini_data_exchange(adev);</div><div class='add'>+		amdgpu_virt_init_data_exchange(adev);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				       struct amdgpu_irq_src *src,</div><div class='ctx'> 				       unsigned type,</div><div class='hunk'>@@ -353,10 +428,34 @@ static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				   struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='ctx'> 	enum idh_event event = xgpu_nv_mailbox_peek_msg(adev);</div><div class='add'>+	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='ctx'> 	switch (event) {</div><div class='add'>+	case IDH_RAS_BAD_PAGES_READY:</div><div class='add'>+		xgpu_nv_mailbox_send_ack(adev);</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			schedule_work(&amp;adev-&gt;virt.handle_bad_pages_work);</div><div class='add'>+		break;</div><div class='add'>+	case IDH_RAS_BAD_PAGES_NOTIFICATION:</div><div class='add'>+		xgpu_nv_mailbox_send_ack(adev);</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			schedule_work(&amp;adev-&gt;virt.req_bad_pages_work);</div><div class='add'>+		break;</div><div class='add'>+	case IDH_UNRECOV_ERR_NOTIFICATION:</div><div class='add'>+		xgpu_nv_mailbox_send_ack(adev);</div><div class='add'>+		if (!amdgpu_ras_is_rma(adev)) {</div><div class='add'>+			ras-&gt;is_rma = true;</div><div class='add'>+			dev_err(adev-&gt;dev, "VF is in an unrecoverable state. Runtime Services are halted.\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='add'>+			WARN_ONCE(!amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='add'>+						&amp;adev-&gt;virt.flr_work),</div><div class='add'>+					"Failed to queue work! at %s",</div><div class='add'>+					__func__);</div><div class='add'>+		break;</div><div class='ctx'> 	case IDH_FLR_NOTIFICATION:</div><div class='del'>-		if (amdgpu_sriov_runtime(adev) &amp;&amp; !amdgpu_in_reset(adev))</div><div class='add'>+		if (amdgpu_sriov_runtime(adev))</div><div class='ctx'> 			WARN_ONCE(!amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='ctx'> 				   &amp;adev-&gt;virt.flr_work),</div><div class='ctx'> 				  "Failed to queue work! at %s",</div><div class='hunk'>@@ -425,6 +524,8 @@ int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	INIT_WORK(&amp;adev-&gt;virt.flr_work, xgpu_nv_mailbox_flr_work);</div><div class='add'>+	INIT_WORK(&amp;adev-&gt;virt.req_bad_pages_work, xgpu_nv_mailbox_req_bad_pages_work);</div><div class='add'>+	INIT_WORK(&amp;adev-&gt;virt.handle_bad_pages_work, xgpu_nv_mailbox_handle_bad_pages_work);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -444,16 +545,58 @@ static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev,</div><div class='ctx'> 		amdgpu_virt_fini_data_exchange(adev);</div><div class='ctx'> 		xgpu_nv_send_access_requests_with_param(adev,</div><div class='ctx'> 					IDH_RAS_POISON,	block, 0, 0);</div><div class='del'>-		amdgpu_virt_init_data_exchange(adev);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	enum idh_event msg = xgpu_nv_mailbox_peek_msg(adev);</div><div class='add'>+</div><div class='add'>+	return (msg == IDH_RAS_ERROR_DETECTED || msg == 0xFFFFFFFF);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xgpu_nv_req_ras_err_count(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return xgpu_nv_send_access_requests(adev, IDH_REQ_RAS_ERROR_COUNT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xgpu_nv_req_ras_cper_dump(struct amdgpu_device *adev, u64 vf_rptr)</div><div class='add'>+{</div><div class='add'>+	uint32_t vf_rptr_hi, vf_rptr_lo;</div><div class='add'>+</div><div class='add'>+	vf_rptr_hi = (uint32_t)(vf_rptr &gt;&gt; 32);</div><div class='add'>+	vf_rptr_lo = (uint32_t)(vf_rptr &amp; 0xFFFFFFFF);</div><div class='add'>+	return xgpu_nv_send_access_requests_with_param(</div><div class='add'>+		adev, IDH_REQ_RAS_CPER_DUMP, vf_rptr_hi, vf_rptr_lo, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xgpu_nv_req_ras_bad_pages(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return xgpu_nv_send_access_requests(adev, IDH_REQ_RAS_BAD_PAGES);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr)</div><div class='add'>+{</div><div class='add'>+	uint32_t addr_hi, addr_lo;</div><div class='add'>+</div><div class='add'>+	addr_hi = (uint32_t)(addr &gt;&gt; 32);</div><div class='add'>+	addr_lo = (uint32_t)(addr &amp; 0xFFFFFFFF);</div><div class='add'>+	return xgpu_nv_send_access_requests_with_param(</div><div class='add'>+		adev, IDH_REQ_RAS_CHK_CRITI, addr_hi, addr_lo, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_virt_ops xgpu_nv_virt_ops = {</div><div class='ctx'> 	.req_full_gpu	= xgpu_nv_request_full_gpu_access,</div><div class='ctx'> 	.rel_full_gpu	= xgpu_nv_release_full_gpu_access,</div><div class='ctx'> 	.req_init_data  = xgpu_nv_request_init_data,</div><div class='ctx'> 	.reset_gpu = xgpu_nv_request_reset,</div><div class='del'>-	.wait_reset = NULL,</div><div class='add'>+	.ready_to_reset = xgpu_nv_ready_to_reset,</div><div class='add'>+	.wait_reset = xgpu_nv_wait_reset,</div><div class='ctx'> 	.trans_msg = xgpu_nv_mailbox_trans_msg,</div><div class='ctx'> 	.ras_poison_handler = xgpu_nv_ras_poison_handler,</div><div class='add'>+	.rcvd_ras_intr = xgpu_nv_rcvd_ras_intr,</div><div class='add'>+	.req_ras_err_count = xgpu_nv_req_ras_err_count,</div><div class='add'>+	.req_ras_cper_dump = xgpu_nv_req_ras_cper_dump,</div><div class='add'>+	.req_bad_pages = xgpu_nv_req_ras_bad_pages,</div><div class='add'>+	.req_ras_chk_criti = xgpu_nv_check_vf_critical_region</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h<br/>index 1e8fd90cab43..c1083e5e41e0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h</a></div><div class='hunk'>@@ -25,8 +25,8 @@</div><div class='ctx'> #define __MXGPU_NV_H__</div><div class='ctx'> </div><div class='ctx'> #define NV_MAILBOX_POLL_ACK_TIMEDOUT	500</div><div class='del'>-#define NV_MAILBOX_POLL_MSG_TIMEDOUT	6000</div><div class='del'>-#define NV_MAILBOX_POLL_FLR_TIMEDOUT	5000</div><div class='add'>+#define NV_MAILBOX_POLL_MSG_TIMEDOUT	15000</div><div class='add'>+#define NV_MAILBOX_POLL_FLR_TIMEDOUT	10000</div><div class='ctx'> #define NV_MAILBOX_POLL_MSG_REP_MAX	11</div><div class='ctx'> </div><div class='ctx'> enum idh_request {</div><div class='hunk'>@@ -40,6 +40,10 @@ enum idh_request {</div><div class='ctx'> 	IDH_LOG_VF_ERROR	= 200,</div><div class='ctx'> 	IDH_READY_TO_RESET 	= 201,</div><div class='ctx'> 	IDH_RAS_POISON	= 202,</div><div class='add'>+	IDH_REQ_RAS_ERROR_COUNT = 203,</div><div class='add'>+	IDH_REQ_RAS_CPER_DUMP = 204,</div><div class='add'>+	IDH_REQ_RAS_BAD_PAGES = 205,</div><div class='add'>+	IDH_REQ_RAS_CHK_CRITI = 206</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum idh_event {</div><div class='hunk'>@@ -52,6 +56,14 @@ enum idh_event {</div><div class='ctx'> 	IDH_QUERY_ALIVE,</div><div class='ctx'> 	IDH_REQ_GPU_INIT_DATA_READY,</div><div class='ctx'> 	IDH_RAS_POISON_READY,</div><div class='add'>+	IDH_PF_SOFT_FLR_NOTIFICATION,</div><div class='add'>+	IDH_RAS_ERROR_DETECTED,</div><div class='add'>+	IDH_RAS_ERROR_COUNT_READY = 11,</div><div class='add'>+	IDH_RAS_CPER_DUMP_READY = 14,</div><div class='add'>+	IDH_RAS_BAD_PAGES_READY = 15,</div><div class='add'>+	IDH_RAS_BAD_PAGES_NOTIFICATION = 16,</div><div class='add'>+	IDH_UNRECOV_ERR_NOTIFICATION = 17,</div><div class='add'>+	IDH_REQ_RAS_CHK_CRITI_READY = 18,</div><div class='ctx'> </div><div class='ctx'> 	IDH_TEXT_MESSAGE = 255,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c<br/>index 59f53c743362..e1d63bed84bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c</a></div><div class='hunk'>@@ -515,12 +515,6 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)</div><div class='ctx'> 	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);</div><div class='ctx'> 	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);</div><div class='ctx'> </div><div class='del'>-	/* wait until RCV_MSG become 3 */</div><div class='del'>-	if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {</div><div class='del'>-		pr_err("failed to receive FLR_CMPL\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* Trigger recovery due to world switch failure */</div><div class='ctx'> 	if (amdgpu_device_should_recover_gpu(adev)) {</div><div class='ctx'> 		struct amdgpu_reset_context reset_context;</div><div class='hunk'>@@ -529,6 +523,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)</div><div class='ctx'> 		reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='ctx'> 		reset_context.reset_req_dev = adev;</div><div class='ctx'> 		clear_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='add'>+		set_bit(AMDGPU_HOST_FLR, &amp;reset_context.flags);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -560,7 +555,7 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev,</div><div class='ctx'> 		r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);</div><div class='ctx'> </div><div class='ctx'> 		/* only handle FLR_NOTIFY now */</div><div class='del'>-		if (!r &amp;&amp; !amdgpu_in_reset(adev))</div><div class='add'>+		if (!r)</div><div class='ctx'> 			WARN_ONCE(!amdgpu_reset_domain_schedule(adev-&gt;reset_domain,</div><div class='ctx'> 								&amp;adev-&gt;virt.flr_work),</div><div class='ctx'> 				  "Failed to queue work! at %s",</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c<br/>index 4178f4e5dad7..4cd325149b63 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/navi10_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/navi10_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/navi10_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/navi10_ih.c</a></div><div class='hunk'>@@ -434,9 +434,8 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> 	 * this should allow us to catch up.</div><div class='ctx'> 	 */</div><div class='ctx'> 	tmp = (wptr + 32) &amp; ih-&gt;ptr_mask;</div><div class='del'>-	dev_warn(adev-&gt;dev, "IH ring buffer overflow "</div><div class='del'>-		 "(0x%08X, 0x%08X, 0x%08X)\n",</div><div class='del'>-		 wptr, ih-&gt;rptr, tmp);</div><div class='add'>+	dev_warn(adev-&gt;dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",</div><div class='add'>+		 amdgpu_ih_ring_name(adev, ih), wptr, ih-&gt;rptr, tmp);</div><div class='ctx'> 	ih-&gt;rptr = tmp;</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl);</div><div class='hunk'>@@ -542,19 +541,19 @@ static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.self_irq.funcs = &amp;navi10_ih_self_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_early_init(void *handle)</div><div class='add'>+static int navi10_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	navi10_ih_set_interrupt_funcs(adev);</div><div class='ctx'> 	navi10_ih_set_self_irq_funcs(adev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_sw_init(void *handle)</div><div class='add'>+static int navi10_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool use_bus_addr;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,</div><div class='hunk'>@@ -593,58 +592,52 @@ static int navi10_ih_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_sw_fini(void *handle)</div><div class='add'>+static int navi10_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_hw_init(void *handle)</div><div class='add'>+static int navi10_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return navi10_ih_irq_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_hw_fini(void *handle)</div><div class='add'>+static int navi10_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	navi10_ih_irq_disable(adev);</div><div class='add'>+	navi10_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_suspend(void *handle)</div><div class='add'>+static int navi10_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return navi10_ih_hw_fini(adev);</div><div class='add'>+	return navi10_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_resume(void *handle)</div><div class='add'>+static int navi10_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return navi10_ih_hw_init(adev);</div><div class='add'>+	return navi10_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool navi10_ih_is_idle(void *handle)</div><div class='add'>+static bool navi10_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_wait_for_idle(void *handle)</div><div class='add'>+static int navi10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_soft_reset(void *handle)</div><div class='add'>+static int navi10_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -673,25 +666,25 @@ static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int navi10_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	navi10_ih_update_clockgating_state(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int navi10_ih_set_powergating_state(void *handle,</div><div class='add'>+static int navi10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void navi10_ih_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void navi10_ih_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_IH_CG;</div><div class='hunk'>@@ -700,7 +693,6 @@ static void navi10_ih_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> static const struct amd_ip_funcs navi10_ih_ip_funcs = {</div><div class='ctx'> 	.name = "navi10_ih",</div><div class='ctx'> 	.early_init = navi10_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = navi10_ih_sw_init,</div><div class='ctx'> 	.sw_fini = navi10_ih_sw_fini,</div><div class='ctx'> 	.hw_init = navi10_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h<br/>index a5b60c9a2418..c88284ff92d8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h</a></div><div class='hunk'>@@ -68,6 +68,7 @@</div><div class='ctx'> #define SDMA_SUBOP_POLL_REG_WRITE_MEM  1</div><div class='ctx'> #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM  2</div><div class='ctx'> #define SDMA_SUBOP_POLL_MEM_VERIFY  3</div><div class='add'>+#define SDMA_SUBOP_VM_INVALIDATION  4</div><div class='ctx'> #define HEADER_AGENT_DISPATCH  4</div><div class='ctx'> #define HEADER_BARRIER  5</div><div class='ctx'> #define SDMA_OP_AQL_COPY  0</div><div class='hunk'>@@ -4041,6 +4042,69 @@</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+** Definitions for SDMA_PKT_VM_INVALIDATION packet</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+/*define for HEADER word*/</div><div class='add'>+/*define for op field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask   0x000000FF</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift  0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_HEADER_op_shift)</div><div class='add'>+</div><div class='add'>+/*define for sub_op field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask   0x000000FF</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift  8</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift)</div><div class='add'>+</div><div class='add'>+/*define for gfx_eng_id field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask   0x0000001F</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift  16</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift)</div><div class='add'>+</div><div class='add'>+/*define for mm_eng_id field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask   0x0000001F</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift  24</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift)</div><div class='add'>+</div><div class='add'>+/*define for INVALIDATEREQ word*/</div><div class='add'>+/*define for invalidatereq field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask   0xFFFFFFFF</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift  0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift)</div><div class='add'>+</div><div class='add'>+/*define for ADDRESSRANGELO word*/</div><div class='add'>+/*define for addressrangelo field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask   0xFFFFFFFF</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift  0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift)</div><div class='add'>+</div><div class='add'>+/*define for ADDRESSRANGEHI word*/</div><div class='add'>+/*define for invalidateack field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask   0x0000FFFF</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift  0</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift)</div><div class='add'>+</div><div class='add'>+/*define for addressrangehi field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask   0x0000001F</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift  16</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift)</div><div class='add'>+</div><div class='add'>+/*define for reserved field*/</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask   0x000001FF</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift  23</div><div class='add'>+#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) &amp; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) &lt;&lt; SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'> ** Definitions for SDMA_PKT_ATOMIC packet</div><div class='ctx'> */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c<br/>index 96ed00ac81ac..9b4025c39e44 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c</a></div><div class='hunk'>@@ -21,13 +21,13 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbif_v6_3_1.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbif/nbif_6_3_1_offset.h"</div><div class='ctx'> #include "nbif/nbif_6_3_1_sh_mask.h"</div><div class='ctx'> #include "pcie/pcie_6_1_0_offset.h"</div><div class='ctx'> #include "pcie/pcie_6_1_0_sh_mask.h"</div><div class='add'>+#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"</div><div class='ctx'> #include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='ctx'> </div><div class='ctx'> static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)</div><div class='hunk'>@@ -315,6 +315,7 @@ static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev)</div><div class='ctx'> static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t def, data;</div><div class='add'>+	u16 devctl2;</div><div class='ctx'> </div><div class='ctx'> 	def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);</div><div class='ctx'> 	data = 0x35EB;</div><div class='hunk'>@@ -328,13 +329,15 @@ static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)</div><div class='ctx'> 	if (def != data)</div><div class='ctx'> 		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);</div><div class='ctx'> </div><div class='del'>-	def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);</div><div class='add'>+	pcie_capability_read_word(adev-&gt;pdev, PCI_EXP_DEVCTL2, &amp;devctl2);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;pdev-&gt;ltr_path == (devctl2 &amp; PCI_EXP_DEVCTL2_LTR_EN))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (adev-&gt;pdev-&gt;ltr_path)</div><div class='del'>-		data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;</div><div class='add'>+		pcie_capability_set_word(adev-&gt;pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);</div><div class='ctx'> 	else</div><div class='del'>-		data &amp;= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;</div><div class='del'>-	if (def != data)</div><div class='del'>-		WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);</div><div class='add'>+		pcie_capability_clear_word(adev-&gt;pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -342,6 +345,7 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> #ifdef CONFIG_PCIEASPM</div><div class='ctx'> 	uint32_t def, data;</div><div class='add'>+	u16 devctl2, ltr;</div><div class='ctx'> </div><div class='ctx'> 	def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);</div><div class='ctx'> 	data &amp;= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;</div><div class='hunk'>@@ -371,12 +375,17 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> 	if (def != data)</div><div class='ctx'> 		WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data);</div><div class='ctx'> </div><div class='del'>-	def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);</div><div class='del'>-	data &amp;= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;</div><div class='add'>+	pcie_capability_read_word(adev-&gt;pdev, PCI_EXP_DEVCTL2, &amp;devctl2);</div><div class='add'>+	data = def = devctl2;</div><div class='add'>+	data &amp;= ~PCI_EXP_DEVCTL2_LTR_EN;</div><div class='ctx'> 	if (def != data)</div><div class='del'>-		WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);</div><div class='add'>+		pcie_capability_set_word(adev-&gt;pdev, PCI_EXP_DEVCTL2, (u16)data);</div><div class='ctx'> </div><div class='del'>-	WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);</div><div class='add'>+	ltr = pci_find_ext_capability(adev-&gt;pdev, PCI_EXT_CAP_ID_LTR);</div><div class='add'>+</div><div class='add'>+	if (ltr) {</div><div class='add'>+		pci_write_config_dword(adev-&gt;pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> #if 0</div><div class='ctx'> 	/* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */</div><div class='hunk'>@@ -424,6 +433,20 @@ static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+			regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -446,50 +469,86 @@ const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = {</div><div class='ctx'> 	.remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers,</div><div class='ctx'> 	.get_rom_offset = nbif_v6_3_1_get_rom_offset,</div><div class='ctx'> 	.program_aspm = nbif_v6_3_1_program_aspm,</div><div class='add'>+	.set_reg_remap = nbif_v6_3_1_set_reg_remap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static void nbif_v6_3_1_sriov_ih_doorbell_range(struct amdgpu_device *adev,</div><div class='del'>-						bool use_doorbell, int doorbell_index)</div><div class='add'>+static int nbif_v6_3_1_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,</div><div class='add'>+						       struct amdgpu_irq_src *src,</div><div class='add'>+						       unsigned type,</div><div class='add'>+						       enum amdgpu_interrupt_state state)</div><div class='ctx'> {</div><div class='add'>+	/* The ras_controller_irq enablement should be done in psp bl when it</div><div class='add'>+	 * tries to enable ras feature. Driver only need to set the correct interrupt</div><div class='add'>+	 * vector for bare-metal and sriov use case respectively</div><div class='add'>+	 */</div><div class='add'>+	uint32_t bif_doorbell_int_cntl;</div><div class='add'>+</div><div class='add'>+	bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);</div><div class='add'>+	bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,</div><div class='add'>+					      BIF_BX0_BIF_DOORBELL_INT_CNTL,</div><div class='add'>+					      RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE,</div><div class='add'>+					      (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1);</div><div class='add'>+	WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void nbif_v6_3_1_sriov_sdma_doorbell_range(struct amdgpu_device *adev,</div><div class='del'>-						  int instance, bool use_doorbell,</div><div class='del'>-						  int doorbell_index,</div><div class='del'>-						  int doorbell_size)</div><div class='add'>+static int nbif_v6_3_1_process_err_event_athub_irq(struct amdgpu_device *adev,</div><div class='add'>+						 struct amdgpu_irq_src *source,</div><div class='add'>+						 struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='add'>+	/* By design, the ih cookie for err_event_athub_irq should be written</div><div class='add'>+	 * to bif ring. since bif ring is not enabled, just leave process callback</div><div class='add'>+	 * as a dummy one.</div><div class='add'>+	 */</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void nbif_v6_3_1_sriov_vcn_doorbell_range(struct amdgpu_device *adev,</div><div class='del'>-						 bool use_doorbell,</div><div class='del'>-						 int doorbell_index, int instance)</div><div class='add'>+static const struct amdgpu_irq_src_funcs nbif_v6_3_1_ras_err_event_athub_irq_funcs = {</div><div class='add'>+	.set = nbif_v6_3_1_set_ras_err_event_athub_irq_state,</div><div class='add'>+	.process = nbif_v6_3_1_process_err_event_athub_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	uint32_t bif_doorbell_int_cntl;</div><div class='add'>+</div><div class='add'>+	bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);</div><div class='add'>+	if (REG_GET_FIELD(bif_doorbell_int_cntl,</div><div class='add'>+			  BIF_BX0_BIF_DOORBELL_INT_CNTL,</div><div class='add'>+			  RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {</div><div class='add'>+		/* driver has to clear the interrupt status when bif ring is disabled */</div><div class='add'>+		bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,</div><div class='add'>+						BIF_BX0_BIF_DOORBELL_INT_CNTL,</div><div class='add'>+						RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);</div><div class='add'>+		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl);</div><div class='add'>+		amdgpu_ras_global_ras_isr(adev);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void nbif_v6_3_1_sriov_gc_doorbell_init(struct amdgpu_device *adev)</div><div class='add'>+static int nbif_v6_3_1_init_ras_err_event_athub_interrupt(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/* init the irq funcs */</div><div class='add'>+	adev-&gt;nbio.ras_err_event_athub_irq.funcs =</div><div class='add'>+		&amp;nbif_v6_3_1_ras_err_event_athub_irq_funcs;</div><div class='add'>+	adev-&gt;nbio.ras_err_event_athub_irq.num_types = 1;</div><div class='add'>+</div><div class='add'>+	/* register ras err event athub interrupt</div><div class='add'>+	 * nbif v6_3_1 uses the same irq source as nbio v7_4</div><div class='add'>+	 */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF,</div><div class='add'>+			      NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,</div><div class='add'>+			      &amp;adev-&gt;nbio.ras_err_event_athub_irq);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct amdgpu_nbio_funcs nbif_v6_3_1_sriov_funcs = {</div><div class='del'>-	.get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset,</div><div class='del'>-	.get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset,</div><div class='del'>-	.get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset,</div><div class='del'>-	.get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset,</div><div class='del'>-	.get_rev_id = nbif_v6_3_1_get_rev_id,</div><div class='del'>-	.mc_access_enable = nbif_v6_3_1_mc_access_enable,</div><div class='del'>-	.get_memsize = nbif_v6_3_1_get_memsize,</div><div class='del'>-	.sdma_doorbell_range = nbif_v6_3_1_sriov_sdma_doorbell_range,</div><div class='del'>-	.vcn_doorbell_range = nbif_v6_3_1_sriov_vcn_doorbell_range,</div><div class='del'>-	.gc_doorbell_init = nbif_v6_3_1_sriov_gc_doorbell_init,</div><div class='del'>-	.enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture,</div><div class='del'>-	.enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture,</div><div class='del'>-	.ih_doorbell_range = nbif_v6_3_1_sriov_ih_doorbell_range,</div><div class='del'>-	.update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating,</div><div class='del'>-	.update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep,</div><div class='del'>-	.get_clockgating_state = nbif_v6_3_1_get_clockgating_state,</div><div class='del'>-	.ih_control = nbif_v6_3_1_ih_control,</div><div class='del'>-	.init_registers = nbif_v6_3_1_init_registers,</div><div class='del'>-	.remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers,</div><div class='del'>-	.get_rom_offset = nbif_v6_3_1_get_rom_offset,</div><div class='add'>+struct amdgpu_nbio_ras nbif_v6_3_1_ras = {</div><div class='add'>+	.handle_ras_err_event_athub_intr_no_bifring =</div><div class='add'>+		nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring,</div><div class='add'>+	.init_ras_err_event_athub_interrupt =</div><div class='add'>+		nbif_v6_3_1_init_ras_err_event_athub_interrupt,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h<br/>index b7f2e0d88905..3afec715a9fe 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.h</a></div><div class='hunk'>@@ -28,6 +28,6 @@</div><div class='ctx'> </div><div class='ctx'> extern const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg;</div><div class='ctx'> extern const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs;</div><div class='del'>-extern const struct amdgpu_nbio_funcs nbif_v6_3_1_sriov_funcs;</div><div class='add'>+extern struct amdgpu_nbio_ras nbif_v6_3_1_ras;</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c<br/>index df218d5ca775..04041b398781 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v2_3.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_2_3_default.h"</div><div class='hunk'>@@ -339,10 +338,6 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (def != data)</div><div class='ctx'> 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='del'>-			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT		0x00000000 // off by default, no gains over L1</div><div class='hunk'>@@ -369,7 +364,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 		data &amp;= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;</div><div class='ctx'> 	} else {</div><div class='del'>-		/* Disbale ASPM L1 */</div><div class='add'>+		/* Disable ASPM L1 */</div><div class='ctx'> 		data &amp;= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;</div><div class='ctx'> 		/* Disable ASPM TxL0s */</div><div class='ctx'> 		data &amp;= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;</div><div class='hunk'>@@ -553,6 +548,20 @@ static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbio_v2_3_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -577,4 +586,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {</div><div class='ctx'> 	.apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,</div><div class='ctx'> 	.apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa,</div><div class='ctx'> 	.clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt,</div><div class='add'>+	.set_reg_remap = nbio_v2_3_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c<br/>index a3622897e3fe..f89e5f40e1a5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v4_3.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_4_3_0_offset.h"</div><div class='hunk'>@@ -345,9 +344,6 @@ static void nbio_v4_3_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> 		data &amp;= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;</div><div class='ctx'> 		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);</div><div class='ctx'> 	}</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='del'>-			regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)</div><div class='hunk'>@@ -475,6 +471,20 @@ static void nbio_v4_3_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbio_v4_3_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+			regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -497,6 +507,7 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {</div><div class='ctx'> 	.remap_hdp_registers = nbio_v4_3_remap_hdp_registers,</div><div class='ctx'> 	.get_rom_offset = nbio_v4_3_get_rom_offset,</div><div class='ctx'> 	.program_aspm = nbio_v4_3_program_aspm,</div><div class='add'>+	.set_reg_remap = nbio_v4_3_set_reg_remap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -541,6 +552,7 @@ const struct amdgpu_nbio_funcs nbio_v4_3_sriov_funcs = {</div><div class='ctx'> 	.init_registers = nbio_v4_3_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v4_3_remap_hdp_registers,</div><div class='ctx'> 	.get_rom_offset = nbio_v4_3_get_rom_offset,</div><div class='add'>+	.set_reg_remap = nbio_v4_3_set_reg_remap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int nbio_v4_3_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c<br/>index 37615a77287b..e911368c1aeb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v6_1.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_6_1_default.h"</div><div class='hunk'>@@ -276,10 +275,6 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (def != data)</div><div class='ctx'> 		WREG32_PCIE(smnPCIE_CI_CNTL, data);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='del'>-			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PCIEASPM</div><div class='hunk'>@@ -394,6 +389,21 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbio_v6_1_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset =</div><div class='add'>+			SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+					 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -412,5 +422,6 @@ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {</div><div class='ctx'> 	.ih_control = nbio_v6_1_ih_control,</div><div class='ctx'> 	.init_registers = nbio_v6_1_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v6_1_remap_hdp_registers,</div><div class='del'>-	.program_aspm =  nbio_v6_1_program_aspm,</div><div class='add'>+	.program_aspm = nbio_v6_1_program_aspm,</div><div class='add'>+	.set_reg_remap = nbio_v6_1_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c<br/>index aa0326d00c72..1569a1e934ec 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v7_0.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_7_0_default.h"</div><div class='hunk'>@@ -271,11 +270,33 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {</div><div class='ctx'> 	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define regRCC_DEV0_EPF6_STRAP4                                                                         0xd304</div><div class='add'>+#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX                                                                5</div><div class='add'>+</div><div class='ctx'> static void nbio_v7_0_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='add'>+	uint32_t data;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(2, 5, 0):</div><div class='add'>+		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4) &amp; ~BIT(23);</div><div class='add'>+		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4, data);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbio_v7_0_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='ctx'> 		adev-&gt;rmmio_remap.reg_offset =</div><div class='ctx'> 			SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {</div><div class='hunk'>@@ -297,4 +318,5 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {</div><div class='ctx'> 	.ih_control = nbio_v7_0_ih_control,</div><div class='ctx'> 	.init_registers = nbio_v7_0_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,</div><div class='add'>+	.set_reg_remap = nbio_v7_0_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c<br/>index 05020141c0ae..bed5ef4d8788 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v7_11.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_7_11_0_offset.h"</div><div class='hunk'>@@ -275,6 +274,15 @@ static void nbio_v7_11_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> 	if (def != data)</div><div class='ctx'> 		WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(7, 11, 0):</div><div class='add'>+	case IP_VERSION(7, 11, 1):</div><div class='add'>+	case IP_VERSION(7, 11, 2):</div><div class='add'>+	case IP_VERSION(7, 11, 3):</div><div class='add'>+		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) &amp; ~BIT(23);</div><div class='add'>+		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,</div><div class='hunk'>@@ -352,6 +360,20 @@ static void nbio_v7_11_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_BIF_LS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET 0x44000</div><div class='add'>+</div><div class='add'>+static void nbio_v7_11_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset =</div><div class='add'>+			SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -374,4 +396,5 @@ const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {</div><div class='ctx'> 	.ih_control = nbio_v7_11_ih_control,</div><div class='ctx'> 	.init_registers = nbio_v7_11_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v7_11_remap_hdp_registers,</div><div class='add'>+	.set_reg_remap = nbio_v7_11_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c<br/>index e962821ae6a1..acc5f363684a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v7_2.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_7_2_0_offset.h"</div><div class='hunk'>@@ -402,10 +401,21 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> 		WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='del'>-			regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+static void nbio_v7_2_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset =</div><div class='add'>+			SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+					 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {</div><div class='hunk'>@@ -429,4 +439,5 @@ const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {</div><div class='ctx'> 	.ih_control = nbio_v7_2_ih_control,</div><div class='ctx'> 	.init_registers = nbio_v7_2_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v7_2_remap_hdp_registers,</div><div class='add'>+	.set_reg_remap = nbio_v7_2_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c<br/>index 19986ff6a48d..860bc5cb03c8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v7_4.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> </div><div class='hunk'>@@ -152,9 +151,9 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan</div><div class='ctx'> 		 *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0</div><div class='ctx'> 		 *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4</div><div class='ctx'> 		 *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8</div><div class='del'>-+		 *   BIF_SDMA4_DOORBELL_RANGE:</div><div class='del'>-+		 *     ARCTURUS:  0x3be0</div><div class='del'>-+		 *     ALDEBARAN: 0x3be4</div><div class='add'>+		 *   BIF_SDMA4_DOORBELL_RANGE:</div><div class='add'>+		 *     ARCTURUS:  0x3be0</div><div class='add'>+		 *     ALDEBARAN: 0x3be4</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (adev-&gt;asic_type == CHIP_ALDEBARAN &amp;&amp; instance == 4)</div><div class='ctx'> 			reg = instance + 0x4 + 0x1 +</div><div class='hunk'>@@ -343,10 +342,6 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t baco_cntl;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,</div><div class='del'>-			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='del'>-</div><div class='ctx'> 	if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) &amp;&amp;</div><div class='ctx'> 	    !amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);</div><div class='hunk'>@@ -387,7 +382,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device</div><div class='ctx'> 		else</div><div class='ctx'> 			WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);</div><div class='ctx'> </div><div class='del'>-		if (!ras-&gt;disable_ras_err_cnt_harvest) {</div><div class='add'>+		if (ras &amp;&amp; !ras-&gt;disable_ras_err_cnt_harvest &amp;&amp; obj) {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * clear error status after ras_controller_intr</div><div class='ctx'> 			 * according to hw team and count ue number</div><div class='hunk'>@@ -418,7 +413,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device</div><div class='ctx'> 		/* ras_controller_int is dedicated for nbif ras error,</div><div class='ctx'> 		 * not the global interrupt for sync flood</div><div class='ctx'> 		 */</div><div class='del'>-		amdgpu_ras_reset_gpu(adev);</div><div class='add'>+		amdgpu_ras_global_ras_isr(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_error_data_fini(&amp;err_data);</div><div class='hunk'>@@ -792,6 +787,21 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbio_v7_4_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset =</div><div class='add'>+			SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+					 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -813,4 +823,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {</div><div class='ctx'> 	.init_registers = nbio_v7_4_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,</div><div class='ctx'> 	.program_aspm =  nbio_v7_4_program_aspm,</div><div class='add'>+	.set_reg_remap = nbio_v7_4_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c<br/>index 4df1055e640a..2ee60b8746a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v7_7.h"</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_7_7_0_offset.h"</div><div class='hunk'>@@ -247,6 +246,12 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> 	if (def != data)</div><div class='ctx'> 		WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(7, 7, 0):</div><div class='add'>+		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) &amp; ~BIT(23);</div><div class='add'>+		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,</div><div class='hunk'>@@ -324,6 +329,21 @@ static void nbio_v7_7_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_BIF_LS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void nbio_v7_7_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset =</div><div class='add'>+			SOC15_REG_OFFSET(NBIO, 0,</div><div class='add'>+					 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) &lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {</div><div class='ctx'> 	.get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,</div><div class='ctx'> 	.get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,</div><div class='hunk'>@@ -345,4 +365,5 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {</div><div class='ctx'> 	.ih_control = nbio_v7_7_ih_control,</div><div class='ctx'> 	.init_registers = nbio_v7_7_init_registers,</div><div class='ctx'> 	.remap_hdp_registers = nbio_v7_7_remap_hdp_registers,</div><div class='add'>+	.set_reg_remap = nbio_v7_7_set_reg_remap,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c<br/>index 40d1e209eab7..bdfd2917e3ca 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "nbio_v7_9.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> </div><div class='hunk'>@@ -32,9 +31,6 @@</div><div class='ctx'> </div><div class='ctx'> #define NPS_MODE_MASK 0x000000FFL</div><div class='ctx'> </div><div class='del'>-/* Core 0 Port 0 counter */</div><div class='del'>-#define smnPCIEP_NAK_COUNTER 0x1A340218</div><div class='del'>-</div><div class='ctx'> static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,</div><div class='hunk'>@@ -45,19 +41,21 @@ static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	u32 tmp;</div><div class='add'>+	u32 rev_id;</div><div class='ctx'> </div><div class='del'>-	tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));</div><div class='del'>-	/* If it is VF or subrevision holds a non-zero value, that should be used */</div><div class='del'>-	if (tmp || amdgpu_sriov_vf(adev))</div><div class='del'>-		return tmp;</div><div class='del'>-</div><div class='del'>-	/* If discovery subrev is not updated, use register version */</div><div class='del'>-	tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);</div><div class='del'>-	tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,</div><div class='del'>-			    STRAP_ATI_REV_ID_DEV0_F0);</div><div class='add'>+	/*</div><div class='add'>+	 * fetch the sub-revision field from the IP-discovery table</div><div class='add'>+	 * (returns zero if the table entry is not populated).</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		rev_id = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));</div><div class='add'>+	} else {</div><div class='add'>+		rev_id = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);</div><div class='add'>+		rev_id = REG_GET_FIELD(rev_id, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,</div><div class='add'>+				STRAP_ATI_REV_ID_DEV0_F0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return tmp;</div><div class='add'>+	return rev_id;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)</div><div class='hunk'>@@ -178,8 +176,12 @@ static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do</div><div class='ctx'> {</div><div class='ctx'> 	u32 doorbell_range = 0, doorbell_ctrl = 0;</div><div class='ctx'> 	u32 aid_id = instance;</div><div class='add'>+	u32 range_size;</div><div class='ctx'> </div><div class='ctx'> 	if (use_doorbell) {</div><div class='add'>+		range_size = (amdgpu_ip_version(adev, GC_HWIP, 0) ==</div><div class='add'>+						IP_VERSION(9, 5, 0)) ?</div><div class='add'>+						0xb : 0x9;</div><div class='ctx'> 		doorbell_range = REG_SET_FIELD(doorbell_range,</div><div class='ctx'> 				DOORBELL0_CTRL_ENTRY_0,</div><div class='ctx'> 				BIF_DOORBELL0_RANGE_OFFSET_ENTRY,</div><div class='hunk'>@@ -187,7 +189,7 @@ static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do</div><div class='ctx'> 		doorbell_range = REG_SET_FIELD(doorbell_range,</div><div class='ctx'> 				DOORBELL0_CTRL_ENTRY_0,</div><div class='ctx'> 				BIF_DOORBELL0_RANGE_SIZE_ENTRY,</div><div class='del'>-				0x9);</div><div class='add'>+				range_size);</div><div class='ctx'> 		if (aid_id)</div><div class='ctx'> 			doorbell_range = REG_SET_FIELD(doorbell_range,</div><div class='ctx'> 					DOORBELL0_CTRL_ENTRY_0,</div><div class='hunk'>@@ -205,7 +207,7 @@ static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do</div><div class='ctx'> 				S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);</div><div class='ctx'> 		doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,</div><div class='ctx'> 				S2A_DOORBELL_ENTRY_1_CTRL,</div><div class='del'>-				S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9);</div><div class='add'>+				S2A_DOORBELL_PORT1_RANGE_SIZE, range_size);</div><div class='ctx'> 		doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,</div><div class='ctx'> 				S2A_DOORBELL_ENTRY_1_CTRL,</div><div class='ctx'> 				S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);</div><div class='hunk'>@@ -401,6 +403,17 @@ static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	return px;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool nbio_v7_9_is_nps_switch_requested(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);</div><div class='add'>+	tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS,</div><div class='add'>+			    CHANGE_STATUE);</div><div class='add'>+</div><div class='add'>+	/* 0x8 - NPS switch requested */</div><div class='add'>+	return (tmp == 0x8);</div><div class='add'>+}</div><div class='ctx'> static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,</div><div class='ctx'> 					       u32 *supp_modes)</div><div class='ctx'> {</div><div class='hunk'>@@ -422,12 +435,6 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 inst_mask;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset =</div><div class='del'>-			SOC15_REG_OFFSET(</div><div class='del'>-				NBIO, 0,</div><div class='del'>-				regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)</div><div class='del'>-			&lt;&lt; 2;</div><div class='ctx'> 	WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,</div><div class='ctx'> 		0xff &amp; ~(adev-&gt;gfx.xcc_mask));</div><div class='ctx'> </div><div class='hunk'>@@ -459,20 +466,21 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	u32 val, nak_r, nak_g;</div><div class='add'>+#define MMIO_REG_HOLE_OFFSET 0x1A000</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* Get the number of NAKs received and generated */</div><div class='del'>-	val = RREG32_PCIE(smnPCIEP_NAK_COUNTER);</div><div class='del'>-	nak_r = val &amp; 0xFFFF;</div><div class='del'>-	nak_g = val &gt;&gt; 16;</div><div class='del'>-</div><div class='del'>-	/* Add the total number of NAKs, i.e the number of replays */</div><div class='del'>-	return (nak_r + nak_g);</div><div class='add'>+static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp; (PAGE_SIZE &lt;= 4096)) {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;rmmio_remap.reg_offset =</div><div class='add'>+			SOC15_REG_OFFSET(</div><div class='add'>+				NBIO, 0,</div><div class='add'>+				regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)</div><div class='add'>+			&lt;&lt; 2;</div><div class='add'>+		adev-&gt;rmmio_remap.bus_addr = 0;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {</div><div class='hunk'>@@ -497,8 +505,9 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {</div><div class='ctx'> 	.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,</div><div class='ctx'> 	.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,</div><div class='ctx'> 	.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,</div><div class='add'>+	.is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested,</div><div class='ctx'> 	.init_registers = nbio_v7_9_init_registers,</div><div class='del'>-	.get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,</div><div class='add'>+	.set_reg_remap = nbio_v7_9_set_reg_remap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c<br/>index 4d7976b77767..50e77d9b30af 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nv.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nv.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nv.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nv.c</a></div><div class='hunk'>@@ -59,7 +59,6 @@</div><div class='ctx'> #include "vcn_v3_0.h"</div><div class='ctx'> #include "jpeg_v3_0.h"</div><div class='ctx'> #include "amdgpu_vkms.h"</div><div class='del'>-#include "mes_v10_1.h"</div><div class='ctx'> #include "mxgpu_nv.h"</div><div class='ctx'> #include "smuio_v11_0.h"</div><div class='ctx'> #include "smuio_v11_0_6.h"</div><div class='hunk'>@@ -68,8 +67,8 @@ static const struct amd_ip_funcs nv_common_ip_funcs;</div><div class='ctx'> </div><div class='ctx'> /* Navi */</div><div class='ctx'> static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codecs nv_video_codecs_encode = {</div><div class='hunk'>@@ -79,12 +78,12 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = {</div><div class='ctx'> </div><div class='ctx'> /* Navi1x */</div><div class='ctx'> static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -95,8 +94,8 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = {</div><div class='ctx'> </div><div class='ctx'> /* Sienna Cichlid */</div><div class='ctx'> static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codecs sc_video_codecs_encode = {</div><div class='hunk'>@@ -105,23 +104,23 @@ static const struct amdgpu_video_codecs sc_video_codecs_encode = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -137,28 +136,28 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {</div><div class='ctx'> </div><div class='ctx'> /* SRIOV Sienna Cichlid, not const since data is controlled by host */</div><div class='ctx'> static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -199,7 +198,7 @@ static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -455,6 +454,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='ctx'> 	case IP_VERSION(13, 0, 1):</div><div class='ctx'> 	case IP_VERSION(13, 0, 3):</div><div class='ctx'> 	case IP_VERSION(13, 0, 5):</div><div class='hunk'>@@ -635,15 +635,11 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = {</div><div class='ctx'> 	.query_video_codecs = &amp;nv_query_video_codecs,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int nv_common_early_init(void *handle)</div><div class='add'>+static int nv_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='del'>-		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='del'>-	}</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;set_reg_remap(adev);</div><div class='ctx'> 	adev-&gt;smc_rreg = NULL;</div><div class='ctx'> 	adev-&gt;smc_wreg = NULL;</div><div class='ctx'> 	adev-&gt;pcie_rreg = &amp;amdgpu_device_indirect_rreg;</div><div class='hunk'>@@ -949,9 +945,9 @@ static int nv_common_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_late_init(void *handle)</div><div class='add'>+static int nv_common_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		xgpu_nv_mailbox_get_irq(adev);</div><div class='hunk'>@@ -978,9 +974,9 @@ static int nv_common_late_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_sw_init(void *handle)</div><div class='add'>+static int nv_common_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_nv_mailbox_add_irq_id(adev);</div><div class='hunk'>@@ -988,14 +984,9 @@ static int nv_common_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_sw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int nv_common_hw_init(void *handle)</div><div class='add'>+static int nv_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;nbio.funcs-&gt;apply_lc_spc_mode_wa)</div><div class='ctx'> 		adev-&gt;nbio.funcs-&gt;apply_lc_spc_mode_wa(adev);</div><div class='hunk'>@@ -1019,9 +1010,9 @@ static int nv_common_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_hw_fini(void *handle)</div><div class='add'>+static int nv_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable the doorbell aperture and selfring doorbell aperture</div><div class='ctx'> 	 * separately in hw_fini because nv_enable_doorbell_aperture</div><div class='hunk'>@@ -1034,39 +1025,25 @@ static int nv_common_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_suspend(void *handle)</div><div class='add'>+static int nv_common_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return nv_common_hw_fini(adev);</div><div class='add'>+	return nv_common_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_resume(void *handle)</div><div class='add'>+static int nv_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return nv_common_hw_init(adev);</div><div class='add'>+	return nv_common_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool nv_common_is_idle(void *handle)</div><div class='add'>+static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int nv_common_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int nv_common_set_clockgating_state(void *handle,</div><div class='add'>+static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1094,16 +1071,16 @@ static int nv_common_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nv_common_set_powergating_state(void *handle,</div><div class='add'>+static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* TODO */</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void nv_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void nv_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		*flags = 0;</div><div class='hunk'>@@ -1120,14 +1097,11 @@ static const struct amd_ip_funcs nv_common_ip_funcs = {</div><div class='ctx'> 	.early_init = nv_common_early_init,</div><div class='ctx'> 	.late_init = nv_common_late_init,</div><div class='ctx'> 	.sw_init = nv_common_sw_init,</div><div class='del'>-	.sw_fini = nv_common_sw_fini,</div><div class='ctx'> 	.hw_init = nv_common_hw_init,</div><div class='ctx'> 	.hw_fini = nv_common_hw_fini,</div><div class='ctx'> 	.suspend = nv_common_suspend,</div><div class='ctx'> 	.resume = nv_common_resume,</div><div class='ctx'> 	.is_idle = nv_common_is_idle,</div><div class='del'>-	.wait_for_idle = nv_common_wait_for_idle,</div><div class='del'>-	.soft_reset = nv_common_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = nv_common_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = nv_common_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = nv_common_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h<br/>index 83e9782aef39..8f4817404f10 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nv.h</a></div><div class='hunk'>@@ -31,5 +31,6 @@ extern const struct amdgpu_ip_block_version nv_common_ip_block;</div><div class='ctx'> void nv_grbm_select(struct amdgpu_device *adev,</div><div class='ctx'> 		    u32 me, u32 pipe, u32 queue, u32 vmid);</div><div class='ctx'> void nv_set_virt_ops(struct amdgpu_device *adev);</div><div class='add'>+int cyan_skillfish_reg_base_init(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h<br/>index 631dafb92299..56f1bfac0b20 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nvd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/nvd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/nvd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/nvd.h</a></div><div class='hunk'>@@ -64,6 +64,24 @@</div><div class='ctx'> #define	PACKET3_INDIRECT_BUFFER_CNST_END		0x19</div><div class='ctx'> #define	PACKET3_ATOMIC_GDS				0x1D</div><div class='ctx'> #define	PACKET3_ATOMIC_MEM				0x1E</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) &amp; 0x7F) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)))</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)))</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)))</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)))</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)))</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)))</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) &amp; 0x1FFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CACHE_POLICY__LRU 0</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CACHE_POLICY__STREAM 1</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CACHE_POLICY__NOA 2</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__CACHE_POLICY__BYPASS 3</div><div class='ctx'> #define	PACKET3_OCCLUSION_QUERY				0x1F</div><div class='ctx'> #define	PACKET3_SET_PREDICATION				0x20</div><div class='ctx'> #define	PACKET3_REG_RMW					0x21</div><div class='hunk'>@@ -105,6 +123,38 @@</div><div class='ctx'> 		 * 1 - pfp</div><div class='ctx'> 		 * 2 - ce</div><div class='ctx'> 		 */</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 16)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 20)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 21)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__AID_ID(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 22)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 24)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) &amp; 0xFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_SEL__TC_L2 2</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_SEL__GDS 3</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_SEL__MEMORY 5</div><div class='add'>+#define 	PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6</div><div class='add'>+#define 	PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0</div><div class='add'>+#define 	PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1</div><div class='add'>+#define 	PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0</div><div class='add'>+#define 	PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1</div><div class='add'>+#define 	PACKET3_WRITE_DATA__MODE__PF_VF_DISABLED 0</div><div class='add'>+#define 	PACKET3_WRITE_DATA__MODE__PF_VF_ENABLED 1</div><div class='add'>+#define 	PACKET3_WRITE_DATA__TEMPORAL__RT 0</div><div class='add'>+#define 	PACKET3_WRITE_DATA__TEMPORAL__NT 1</div><div class='add'>+#define 	PACKET3_WRITE_DATA__TEMPORAL__HT 2</div><div class='add'>+#define 	PACKET3_WRITE_DATA__TEMPORAL__LU 3</div><div class='add'>+#define 	PACKET3_WRITE_DATA__CACHE_POLICY__LRU 0</div><div class='add'>+#define 	PACKET3_WRITE_DATA__CACHE_POLICY__STREAM 1</div><div class='add'>+#define 	PACKET3_WRITE_DATA__CACHE_POLICY__NOA 2</div><div class='add'>+#define 	PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS 3</div><div class='ctx'> #define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38</div><div class='ctx'> #define	PACKET3_MEM_SEMAPHORE				0x39</div><div class='ctx'> #              define PACKET3_SEM_USE_MAILBOX       (0x1 &lt;&lt; 16)</div><div class='hunk'>@@ -135,6 +185,42 @@</div><div class='ctx'> 		/* 0 - me</div><div class='ctx'> 		 * 1 - pfp</div><div class='ctx'> 		 */</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) &amp; 0x7) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 4)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 6)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 22)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 24)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) &amp; 0X3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) &amp; 0X3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 31)</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__CACHE_POLICY__LRU 0</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__CACHE_POLICY__STREAM 1</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__CACHE_POLICY__NOA 2</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__CACHE_POLICY__BYPASS 3</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2</div><div class='add'>+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3</div><div class='ctx'> #define	PACKET3_INDIRECT_BUFFER				0x3F</div><div class='ctx'> #define		INDIRECT_BUFFER_VALID                   (1 &lt;&lt; 23)</div><div class='ctx'> #define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) &lt;&lt; 28)</div><div class='hunk'>@@ -144,8 +230,94 @@</div><div class='ctx'> 		 */</div><div class='ctx'> #define		INDIRECT_BUFFER_PRE_ENB(x)		((x) &lt;&lt; 21)</div><div class='ctx'> #define		INDIRECT_BUFFER_PRE_RESUME(x)           ((x) &lt;&lt; 30)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) &amp; 0xFFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 20)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 21)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 23)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 24)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 28)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 28)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 31)</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU 0</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM 1</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__CACHE_POLICY__NOA 2</div><div class='add'>+#define 	PACKET3_INDIRECT_BUFFER__CACHE_POLICY__BYPASS 3</div><div class='ctx'> #define	PACKET3_COND_INDIRECT_BUFFER			0x3F</div><div class='ctx'> #define	PACKET3_COPY_DATA				0x40</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 13)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 13)</div><div class='add'>+#define 	PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 16)</div><div class='add'>+#define 	PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 20)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define 	PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 29)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x1FFFFFFF) &lt;&lt; 3)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x1FFFFFFF) &lt;&lt; 3)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 21)</div><div class='add'>+#define 	PACKET3_COPY_DATA__AID_ID(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 23)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) &amp; 0xFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) &amp; 0xFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__TC_L2 2</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__GDS 3</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0 7</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1 8</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL__TC_L2 2</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL__GDS 3</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_CACHE_POLICY__NOA 2</div><div class='add'>+#define 	PACKET3_COPY_DATA__SRC_CACHE_POLICY__BYPASS 3</div><div class='add'>+#define 	PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__MODE__PF_VF_DISABLED 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__MODE__PF_VF_ENABLED 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__RT 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__NT 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__HT 2</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__LU 3</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM 1</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_CACHE_POLICY__NOA 2</div><div class='add'>+#define 	PACKET3_COPY_DATA__DST_CACHE_POLICY__BYPASS 3</div><div class='add'>+#define 	PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0</div><div class='add'>+#define 	PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1</div><div class='ctx'> #define	PACKET3_CP_DMA					0x41</div><div class='ctx'> #define	PACKET3_PFP_SYNC_ME				0x42</div><div class='ctx'> #define	PACKET3_SURFACE_SYNC				0x43</div><div class='hunk'>@@ -160,6 +332,23 @@</div><div class='ctx'> 		 * 3 - SAMPLE_STREAMOUTSTAT*</div><div class='ctx'> 		 * 4 - *S_PARTIAL_FLUSH</div><div class='ctx'> 		 */</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) &amp; 0x3F) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 29)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) &amp; 0x1FFFFFFF) &lt;&lt; 3)</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS 8</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS1 9</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS2 10</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_STREAMOUTSTATS3 11</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__LEGACY_MODE 0</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE1 1</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__NEW_MODE 2</div><div class='add'>+#define 	PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE__MIXED_MODE3 3</div><div class='ctx'> #define	PACKET3_EVENT_WRITE_EOP				0x47</div><div class='ctx'> #define	PACKET3_EVENT_WRITE_EOS				0x48</div><div class='ctx'> #define	PACKET3_RELEASE_MEM				0x49</div><div class='hunk'>@@ -304,6 +493,12 @@</div><div class='ctx'> 		 * 2: REVERSE</div><div class='ctx'> 		 */</div><div class='ctx'> #define 	PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA  (1 &lt;&lt; 18)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) &amp; 0xFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) &amp; 0xFFFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) &amp; 0x7FFFF) &lt;&lt; 0)</div><div class='ctx'> #define	PACKET3_REWIND					0x59</div><div class='ctx'> #define	PACKET3_INTERRUPT				0x5A</div><div class='ctx'> #define	PACKET3_GEN_PDEPTE				0x5B</div><div class='hunk'>@@ -330,11 +525,17 @@</div><div class='ctx'> #define	PACKET3_SET_SH_REG				0x76</div><div class='ctx'> #define		PACKET3_SET_SH_REG_START			0x00002c00</div><div class='ctx'> #define		PACKET3_SET_SH_REG_END				0x00003000</div><div class='add'>+#define 	PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) &amp; 0x1F) &lt;&lt; 23)</div><div class='add'>+#define 	PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 28)</div><div class='add'>+#define 	PACKET3_SET_SH_REG__INDEX__DEFAULT 0</div><div class='add'>+#define 	PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1</div><div class='ctx'> #define	PACKET3_SET_SH_REG_OFFSET			0x77</div><div class='ctx'> #define	PACKET3_SET_QUEUE_REG				0x78</div><div class='ctx'> #define	PACKET3_SET_UCONFIG_REG				0x79</div><div class='ctx'> #define		PACKET3_SET_UCONFIG_REG_START			0x0000c000</div><div class='ctx'> #define		PACKET3_SET_UCONFIG_REG_END			0x0000c400</div><div class='add'>+#define 	PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='ctx'> #define	PACKET3_SET_UCONFIG_REG_INDEX			0x7A</div><div class='ctx'> #define	PACKET3_FORWARD_HEADER				0x7C</div><div class='ctx'> #define	PACKET3_SCRATCH_RAM_WRITE			0x7D</div><div class='hunk'>@@ -369,6 +570,7 @@</div><div class='ctx'> #              define PACKET3_INVALIDATE_TLBS_DST_SEL(x)     ((x) &lt;&lt; 0)</div><div class='ctx'> #              define PACKET3_INVALIDATE_TLBS_ALL_HUB(x)     ((x) &lt;&lt; 4)</div><div class='ctx'> #              define PACKET3_INVALIDATE_TLBS_PASID(x)       ((x) &lt;&lt; 5)</div><div class='add'>+#              define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x)  ((x) &lt;&lt; 29)</div><div class='ctx'> #define	PACKET3_AQL_PACKET				0x99</div><div class='ctx'> #define	PACKET3_DMA_DATA_FILL_MULTI			0x9A</div><div class='ctx'> #define	PACKET3_SET_SH_REG_INDEX			0x9B</div><div class='hunk'>@@ -462,6 +664,12 @@</div><div class='ctx'> #              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) &lt;&lt; 25)</div><div class='ctx'> #define	PACKET3_RUN_LIST				0xA5</div><div class='ctx'> #define	PACKET3_MAP_PROCESS_VM				0xA6</div><div class='add'>+</div><div class='add'>+#define PACKET3_RUN_CLEANER_SHADER                      0xD2</div><div class='add'>+/* 1. header</div><div class='add'>+ * 2. RESERVED [31:0]</div><div class='add'>+ */</div><div class='add'>+</div><div class='ctx'> /* GFX11 */</div><div class='ctx'> #define	PACKET3_SET_Q_PREEMPTION_MODE			0xF0</div><div class='ctx'> #              define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x)  ((x) &lt;&lt; 0)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h<br/>index 7566973ed8f5..73f87131a7e9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h</a></div><div class='hunk'>@@ -103,6 +103,12 @@ enum psp_gfx_cmd_id</div><div class='ctx'>     GFX_CMD_ID_AUTOLOAD_RLC       = 0x00000021,   /* Indicates all graphics fw loaded, start RLC autoload */</div><div class='ctx'>     GFX_CMD_ID_BOOT_CFG           = 0x00000022,   /* Boot Config */</div><div class='ctx'>     GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027,   /* Configure spatial partitioning mode */</div><div class='add'>+    /*IDs of performance monitoring/profiling*/</div><div class='add'>+    GFX_CMD_ID_CONFIG_SQ_PERFMON  = 0x00000046,   /* Config CGTT_SQ_CLK_CTRL */</div><div class='add'>+    /* Dynamic memory partitioninig (NPS mode change)*/</div><div class='add'>+    GFX_CMD_ID_FB_NPS_MODE        = 0x00000048,  /* Configure memory partitioning mode */</div><div class='add'>+    GFX_CMD_ID_FB_FW_RESERV_ADDR  = 0x00000050,  /* Query FW reservation addr */</div><div class='add'>+    GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051,  /* Query FW reservation extended addr */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* PSP boot config sub-commands */</div><div class='hunk'>@@ -351,6 +357,20 @@ struct psp_gfx_cmd_sriov_spatial_part {</div><div class='ctx'> 	uint32_t override_this_aid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*Structure for sq performance monitoring/profiling enable/disable*/</div><div class='add'>+struct psp_gfx_cmd_config_sq_perfmon {</div><div class='add'>+	uint32_t        gfx_xcp_mask;</div><div class='add'>+	uint8_t         core_override;</div><div class='add'>+	uint8_t         reg_override;</div><div class='add'>+	uint8_t         perfmon_override;</div><div class='add'>+	uint8_t         reserved[5];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct psp_gfx_cmd_fb_memory_part {</div><div class='add'>+	uint32_t mode; /* requested NPS mode */</div><div class='add'>+	uint32_t resvd;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* All GFX ring buffer commands. */</div><div class='ctx'> union psp_gfx_commands</div><div class='ctx'> {</div><div class='hunk'>@@ -365,6 +385,8 @@ union psp_gfx_commands</div><div class='ctx'>     struct psp_gfx_cmd_load_toc         cmd_load_toc;</div><div class='ctx'>     struct psp_gfx_cmd_boot_cfg         boot_cfg;</div><div class='ctx'>     struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part;</div><div class='add'>+    struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon;</div><div class='add'>+    struct psp_gfx_cmd_fb_memory_part cmd_memory_part;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct psp_gfx_uresp_reserved</div><div class='hunk'>@@ -384,11 +406,19 @@ struct psp_gfx_uresp_bootcfg {</div><div class='ctx'> 	uint32_t boot_cfg;	/* boot config data */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* Command-specific response for fw reserve info */</div><div class='add'>+struct psp_gfx_uresp_fw_reserve_info {</div><div class='add'>+    uint32_t reserve_base_address_hi;</div><div class='add'>+    uint32_t reserve_base_address_lo;</div><div class='add'>+    uint32_t reserve_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Union of command-specific responses for GPCOM ring. */</div><div class='ctx'> union psp_gfx_uresp {</div><div class='ctx'> 	struct psp_gfx_uresp_reserved		reserved;</div><div class='ctx'> 	struct psp_gfx_uresp_bootcfg		boot_cfg;</div><div class='ctx'> 	struct psp_gfx_uresp_fwar_db_info	fwar_db_info;</div><div class='add'>+	struct psp_gfx_uresp_fw_reserve_info	fw_reserve_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Structure of GFX Response buffer.</div><div class='hunk'>@@ -464,8 +494,9 @@ struct psp_gfx_rb_frame</div><div class='ctx'> #define PSP_ERR_UNKNOWN_COMMAND 0x00000100</div><div class='ctx'> </div><div class='ctx'> enum tee_error_code {</div><div class='del'>-    TEE_SUCCESS                         = 0x00000000,</div><div class='del'>-    TEE_ERROR_NOT_SUPPORTED             = 0xFFFF000A,</div><div class='add'>+	TEE_SUCCESS			= 0x00000000,</div><div class='add'>+	TEE_ERROR_CANCEL		= 0xFFFF0002,</div><div class='add'>+	TEE_ERROR_NOT_SUPPORTED		= 0xFFFF000A,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif /* _PSP_TEE_GFX_IF_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c<br/>index 145186a1e48f..3584b8c18fd9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v10_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v10_0.c</a></div><div class='hunk'>@@ -94,7 +94,7 @@ static int psp_v10_0_ring_create(struct psp_context *psp,</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-			   0x80000000, 0x8000FFFF, false);</div><div class='add'>+			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -115,7 +115,7 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c<br/>index 2395f1856962..a9be7a505026 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v11_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v11_0.c</a></div><div class='hunk'>@@ -129,6 +129,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)</div><div class='ctx'> 		err = psp_init_ta_microcode(psp, ucode_prefix);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='ctx'> 		err = psp_init_asd_microcode(psp, ucode_prefix);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -141,21 +142,43 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)</div><div class='add'>+static int psp_v11_wait_for_tos_unload(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+	uint32_t sol_reg1, sol_reg2;</div><div class='add'>+	int retry_loop;</div><div class='add'>+</div><div class='add'>+	/* Wait for the TOS to be unloaded */</div><div class='add'>+	for (retry_loop = 0; retry_loop &lt; 20; retry_loop++) {</div><div class='add'>+		sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);</div><div class='add'>+		usleep_range(1000, 2000);</div><div class='add'>+		sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);</div><div class='add'>+		if (sol_reg1 == sol_reg2)</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='add'>+	dev_err(adev-&gt;dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x",</div><div class='add'>+		RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33),</div><div class='add'>+		RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81));</div><div class='ctx'> </div><div class='add'>+	return -ETIME;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int retry_loop;</div><div class='ctx'> </div><div class='del'>-	for (retry_loop = 0; retry_loop &lt; 10; retry_loop++) {</div><div class='add'>+	/* For a reset done at the end of S3, only wait for TOS to be unloaded */</div><div class='add'>+	if (adev-&gt;in_s3 &amp;&amp; !(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; amdgpu_in_reset(adev))</div><div class='add'>+		return psp_v11_wait_for_tos_unload(psp);</div><div class='add'>+</div><div class='add'>+	for (retry_loop = 0; retry_loop &lt; 20; retry_loop++) {</div><div class='ctx'> 		/* Wait for bootloader to signify that is</div><div class='ctx'> 		    ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='del'>-		ret = psp_wait_for(psp,</div><div class='del'>-				   SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-				   0x80000000,</div><div class='del'>-				   0x80000000,</div><div class='del'>-				   false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='add'>+			0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> </div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			return 0;</div><div class='hunk'>@@ -251,8 +274,8 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> 	/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),</div><div class='del'>-			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),</div><div class='del'>-			   0, true);</div><div class='add'>+			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,</div><div class='add'>+			   PSP_WAITREG_CHANGED);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -276,11 +299,13 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for response flag (bit 31) */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	else</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -316,13 +341,15 @@ static int psp_v11_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Wait for sOS ready for ring creation */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			DRM_ERROR("Failed to wait for sOS ready for ring creation\n");</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -346,8 +373,9 @@ static int psp_v11_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -380,7 +408,8 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);</div><div class='add'>+	ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,</div><div class='add'>+			   MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_INFO("psp is not working correctly before mode1 reset!\n");</div><div class='hunk'>@@ -392,17 +421,6 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	msleep(500);</div><div class='ctx'> </div><div class='del'>-	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);</div><div class='del'>-</div><div class='del'>-	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);</div><div class='del'>-</div><div class='del'>-	if (ret) {</div><div class='del'>-		DRM_INFO("psp mode 1 reset failed!\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	DRM_INFO("psp mode1 reset succeed \n");</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -420,8 +438,9 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)</div><div class='ctx'> </div><div class='ctx'> 	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev-&gt;usec_timeout;</div><div class='ctx'> 	for (i = 0; i &lt; max_wait; i++) {</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='add'>+			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -532,7 +551,7 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			memcpy_toio(adev-&gt;mman.aper_base_kaddr, buf, sz);</div><div class='del'>-			adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+			amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> 			vfree(buf);</div><div class='ctx'> 			drm_dev_exit(idx);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -600,7 +619,7 @@ static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr &gt;&gt; 20));</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			     0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -637,7 +656,7 @@ static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-				     0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		*fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);</div><div class='ctx'> </div><div class='hunk'>@@ -658,7 +677,8 @@ static const struct psp_funcs psp_v11_0_funcs = {</div><div class='ctx'> 	.ring_get_wptr = psp_v11_0_ring_get_wptr,</div><div class='ctx'> 	.ring_set_wptr = psp_v11_0_ring_set_wptr,</div><div class='ctx'> 	.load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,</div><div class='del'>-	.read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw</div><div class='add'>+	.read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw,</div><div class='add'>+	.wait_for_bootloader = psp_v11_0_wait_for_bootloader</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void psp_v11_0_set_psp_funcs(struct psp_context *psp)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c<br/>index 5697760a819b..93787a90d598 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c</a></div><div class='hunk'>@@ -41,8 +41,9 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Write the ring destroy command*/</div><div class='ctx'> 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,</div><div class='hunk'>@@ -50,8 +51,9 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -87,13 +89,15 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Wait for sOS ready for ring creation */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -117,8 +121,9 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c<br/>index fcd708eae75c..4c6450d62299 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v12_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v12_0.c</a></div><div class='hunk'>@@ -34,9 +34,6 @@</div><div class='ctx'> #include "sdma0/sdma0_4_0_offset.h"</div><div class='ctx'> #include "nbio/nbio_7_4_offset.h"</div><div class='ctx'> </div><div class='del'>-#include "oss/osssys_4_0_offset.h"</div><div class='del'>-#include "oss/osssys_4_0_sh_mask.h"</div><div class='del'>-</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/renoir_asd.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/renoir_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");</div><div class='hunk'>@@ -85,7 +82,7 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -99,11 +96,8 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,</div><div class='ctx'> 	       psp_gfxdrv_command_reg);</div><div class='ctx'> </div><div class='del'>-	/* there might be handshake issue with hardware which needs delay */</div><div class='del'>-	mdelay(20);</div><div class='del'>-</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -124,7 +118,7 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -138,46 +132,13 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,</div><div class='ctx'> 	       psp_gfxdrv_command_reg);</div><div class='ctx'> </div><div class='del'>-	/* there might be handshake issue with hardware which needs delay */</div><div class='del'>-	mdelay(20);</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),</div><div class='del'>-			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),</div><div class='del'>-			   0, true);</div><div class='add'>+			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,</div><div class='add'>+			   PSP_WAITREG_CHANGED);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void psp_v12_0_reroute_ih(struct psp_context *psp)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	uint32_t tmp;</div><div class='del'>-</div><div class='del'>-	/* Change IH ring for VMC */</div><div class='del'>-	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);</div><div class='del'>-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);</div><div class='del'>-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);</div><div class='del'>-</div><div class='del'>-	mdelay(20);</div><div class='del'>-	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-		     0x80000000, 0x8000FFFF, false);</div><div class='del'>-</div><div class='del'>-	/* Change IH ring for UMC */</div><div class='del'>-	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);</div><div class='del'>-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);</div><div class='del'>-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);</div><div class='del'>-</div><div class='del'>-	mdelay(20);</div><div class='del'>-	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-		     0x80000000, 0x8000FFFF, false);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int psp_v12_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 				enum psp_ring_type ring_type)</div><div class='ctx'> {</div><div class='hunk'>@@ -186,49 +147,23 @@ static int psp_v12_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 	struct psp_ring *ring = &amp;psp-&gt;km_ring;</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	psp_v12_0_reroute_ih(psp);</div><div class='del'>-</div><div class='del'>-	if (amdgpu_sriov_vf(psp-&gt;adev)) {</div><div class='del'>-		/* Write low address of the ring to C2PMSG_102 */</div><div class='del'>-		psp_ring_reg = lower_32_bits(ring-&gt;ring_mem_mc_addr);</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);</div><div class='del'>-		/* Write high address of the ring to C2PMSG_103 */</div><div class='del'>-		psp_ring_reg = upper_32_bits(ring-&gt;ring_mem_mc_addr);</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);</div><div class='del'>-</div><div class='del'>-		/* Write the ring initialization command to C2PMSG_101 */</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,</div><div class='del'>-					     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);</div><div class='del'>-</div><div class='del'>-		/* there might be handshake issue with hardware which needs delay */</div><div class='del'>-		mdelay(20);</div><div class='del'>-</div><div class='del'>-		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='del'>-</div><div class='del'>-	} else {</div><div class='del'>-		/* Write low address of the ring to C2PMSG_69 */</div><div class='del'>-		psp_ring_reg = lower_32_bits(ring-&gt;ring_mem_mc_addr);</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);</div><div class='del'>-		/* Write high address of the ring to C2PMSG_70 */</div><div class='del'>-		psp_ring_reg = upper_32_bits(ring-&gt;ring_mem_mc_addr);</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);</div><div class='del'>-		/* Write size of ring to C2PMSG_71 */</div><div class='del'>-		psp_ring_reg = ring-&gt;ring_size;</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);</div><div class='del'>-		/* Write the ring initialization command to C2PMSG_64 */</div><div class='del'>-		psp_ring_reg = ring_type;</div><div class='del'>-		psp_ring_reg = psp_ring_reg &lt;&lt; 16;</div><div class='del'>-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);</div><div class='del'>-</div><div class='del'>-		/* there might be handshake issue with hardware which needs delay */</div><div class='del'>-		mdelay(20);</div><div class='del'>-</div><div class='del'>-		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='del'>-	}</div><div class='add'>+	/* Write low address of the ring to C2PMSG_69 */</div><div class='add'>+	psp_ring_reg = lower_32_bits(ring-&gt;ring_mem_mc_addr);</div><div class='add'>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);</div><div class='add'>+	/* Write high address of the ring to C2PMSG_70 */</div><div class='add'>+	psp_ring_reg = upper_32_bits(ring-&gt;ring_mem_mc_addr);</div><div class='add'>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);</div><div class='add'>+	/* Write size of ring to C2PMSG_71 */</div><div class='add'>+	psp_ring_reg = ring-&gt;ring_size;</div><div class='add'>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);</div><div class='add'>+	/* Write the ring initialization command to C2PMSG_64 */</div><div class='add'>+	psp_ring_reg = ring_type;</div><div class='add'>+	psp_ring_reg = psp_ring_reg &lt;&lt; 16;</div><div class='add'>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);</div><div class='add'>+</div><div class='add'>+	/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='add'>+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			   MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -247,16 +182,15 @@ static int psp_v12_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,</div><div class='ctx'> 				     GFX_CTRL_CMD_ID_DESTROY_RINGS);</div><div class='ctx'> </div><div class='del'>-	/* there might be handshake issue with hardware which needs delay */</div><div class='del'>-	mdelay(20);</div><div class='del'>-</div><div class='ctx'> 	/* Wait for response flag (bit 31) */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	else</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -287,7 +221,8 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);</div><div class='add'>+	ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,</div><div class='add'>+			   MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_INFO("psp is not working correctly before mode1 reset!\n");</div><div class='hunk'>@@ -301,7 +236,8 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);</div><div class='add'>+	ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,</div><div class='add'>+			   0);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_INFO("psp mode 1 reset failed!\n");</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c<br/>index 0da50ea46eaf..af4a7d7c4abd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v13_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v13_0.c</a></div><div class='hunk'>@@ -42,7 +42,9 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");</div><div class='hunk'>@@ -51,10 +53,16 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");</div><div class='ctx'> </div><div class='ctx'> /* For large FW files the time to complete can be very long */</div><div class='ctx'> #define USBC_PD_POLLING_LIMIT_S 240</div><div class='hunk'>@@ -65,18 +73,13 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");</div><div class='ctx'> /* Retry times for vmbx ready wait */</div><div class='ctx'> #define PSP_VMBX_POLLING_LIMIT 3000</div><div class='ctx'> </div><div class='del'>-/* VBIOS gfl defines */</div><div class='del'>-#define MBOX_READY_MASK 0x80000000</div><div class='del'>-#define MBOX_STATUS_MASK 0x0000FFFF</div><div class='del'>-#define MBOX_COMMAND_MASK 0x00FF0000</div><div class='del'>-#define MBOX_READY_FLAG 0x80000000</div><div class='del'>-#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2</div><div class='del'>-#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3</div><div class='del'>-#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4</div><div class='del'>-</div><div class='ctx'> /* memory training timeout define */</div><div class='ctx'> #define MEM_TRAIN_SEND_MSG_TIMEOUT_US	3000000</div><div class='ctx'> </div><div class='add'>+#define regMP1_PUB_SCRATCH0	0x3b10090</div><div class='add'>+</div><div class='add'>+#define PSP13_BL_STATUS_SIZE 100</div><div class='add'>+</div><div class='ctx'> static int psp_v13_0_init_microcode(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='hunk'>@@ -104,6 +107,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)</div><div class='ctx'> 	case IP_VERSION(13, 0, 11):</div><div class='ctx'> 	case IP_VERSION(14, 0, 0):</div><div class='ctx'> 	case IP_VERSION(14, 0, 1):</div><div class='add'>+	case IP_VERSION(14, 0, 4):</div><div class='ctx'> 		err = psp_init_toc_microcode(psp, ucode_prefix);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -115,6 +119,8 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='ctx'> 	case IP_VERSION(13, 0, 7):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='ctx'> 		err = psp_init_sos_microcode(psp, ucode_prefix);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -140,6 +146,32 @@ static bool psp_v13_0_is_sos_alive(struct psp_context *psp)</div><div class='ctx'> 	return sol_reg != 0x0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void psp_v13_0_bootloader_print_status(struct psp_context *psp,</div><div class='add'>+					      const char *msg)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+	u32 bl_status_reg;</div><div class='add'>+	char bl_status_msg[PSP13_BL_STATUS_SIZE];</div><div class='add'>+	int i, at;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {</div><div class='add'>+		at = 0;</div><div class='add'>+		for_each_inst(i, adev-&gt;aid_mask) {</div><div class='add'>+			bl_status_reg =</div><div class='add'>+				(SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92)</div><div class='add'>+				 &lt;&lt; 2) +</div><div class='add'>+				adev-&gt;asic_funcs-&gt;encode_ext_smn_addressing(i);</div><div class='add'>+			at += snprintf(bl_status_msg + at,</div><div class='add'>+				       PSP13_BL_STATUS_SIZE - at,</div><div class='add'>+				       " status(%02i): 0x%08x", i,</div><div class='add'>+				       RREG32_PCIE_EXT(bl_status_reg));</div><div class='add'>+		}</div><div class='add'>+		dev_info(adev-&gt;dev, "%s - %s", msg, bl_status_msg);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='hunk'>@@ -150,7 +182,7 @@ static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)</div><div class='ctx'> 		   ready having bit 31 of C2PMSG_33 set to 1 */</div><div class='ctx'> 		ret = psp_wait_for(</div><div class='ctx'> 			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),</div><div class='del'>-			0x80000000, 0xffffffff, false);</div><div class='add'>+			0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> </div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -168,7 +200,9 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)</div><div class='ctx'> 	int retry_loop, retry_cnt, ret;</div><div class='ctx'> </div><div class='ctx'> 	retry_cnt =</div><div class='del'>-		(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?</div><div class='add'>+		((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+		  amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+		  amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?</div><div class='ctx'> 			PSP_VMBX_POLLING_LIMIT :</div><div class='ctx'> 			10;</div><div class='ctx'> 	/* Wait for bootloader to signify that it is ready having bit 31 of</div><div class='hunk'>@@ -179,10 +213,13 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)</div><div class='ctx'> 	for (retry_loop = 0; retry_loop &lt; retry_cnt; retry_loop++) {</div><div class='ctx'> 		ret = psp_wait_for(</div><div class='ctx'> 			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='del'>-			0x80000000, 0xffffffff, false);</div><div class='add'>+			0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> </div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			return 0;</div><div class='add'>+		if (retry_loop &amp;&amp; !(retry_loop % 10))</div><div class='add'>+			psp_v13_0_bootloader_print_status(</div><div class='add'>+				psp, "Waiting for bootloader completion");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -193,7 +230,9 @@ static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {</div><div class='ctx'> 		ret = psp_v13_0_wait_for_vmbx_ready(psp);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			amdgpu_ras_query_boot_status(adev, 4);</div><div class='hunk'>@@ -278,6 +317,11 @@ static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)</div><div class='ctx'> 	return psp_v13_0_bootloader_load_component(psp, &amp;psp-&gt;ras_drv, PSP_BL__LOAD_RASDRV);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	return psp_v13_0_bootloader_load_component(psp, &amp;psp-&gt;spdm_drv, PSP_BL__LOAD_SPDMDRV);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void psp_v13_0_init_sos_version(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='hunk'>@@ -318,8 +362,8 @@ static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> 	/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),</div><div class='del'>-			   RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),</div><div class='del'>-			   0, true);</div><div class='add'>+			   RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,</div><div class='add'>+			   PSP_WAITREG_CHANGED);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		psp_v13_0_init_sos_version(psp);</div><div class='hunk'>@@ -340,8 +384,9 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Write the ring destroy command*/</div><div class='ctx'> 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,</div><div class='hunk'>@@ -349,8 +394,9 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -386,13 +432,15 @@ static int psp_v13_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Wait for sOS ready for ring creation */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -416,8 +464,9 @@ static int psp_v13_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -480,8 +529,9 @@ static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)</div><div class='ctx'> </div><div class='ctx'> 	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev-&gt;usec_timeout;</div><div class='ctx'> 	for (i = 0; i &lt; max_wait; i++) {</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='add'>+			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -590,7 +640,7 @@ static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			memcpy_toio(adev-&gt;mman.aper_base_kaddr, buf, sz);</div><div class='del'>-			adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+			amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> 			vfree(buf);</div><div class='ctx'> 			drm_dev_exit(idx);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -633,7 +683,7 @@ static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr &gt;&gt; 20));</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='del'>-			     0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -670,7 +720,7 @@ static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='del'>-				     0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		*fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);</div><div class='ctx'> </div><div class='hunk'>@@ -690,12 +740,14 @@ static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)</div><div class='ctx'> 	/* Ring the doorbell */</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);</div><div class='ctx'> </div><div class='del'>-	if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)</div><div class='add'>+	if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE ||</div><div class='add'>+	    cmd == C2PMSG_CMD_SPI_GET_FLASH_IMAGE)</div><div class='ctx'> 		ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),</div><div class='ctx'> 						 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);</div><div class='ctx'> 	else</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),</div><div class='del'>-				   MBOX_READY_FLAG, MBOX_READY_MASK, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),</div><div class='add'>+			MBOX_READY_FLAG, MBOX_READY_MASK, 0);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "SPI cmd %x timed out, ret = %d", cmd, ret);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -719,7 +771,7 @@ static int psp_v13_0_update_spirom(struct psp_context *psp,</div><div class='ctx'> </div><div class='ctx'> 	/* Confirm PSP is ready to start */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),</div><div class='del'>-			   MBOX_READY_FLAG, MBOX_READY_MASK, false);</div><div class='add'>+			   MBOX_READY_FLAG, MBOX_READY_MASK, 0);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "PSP Not ready to start processing, ret = %d", ret);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -746,6 +798,37 @@ static int psp_v13_0_update_spirom(struct psp_context *psp,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int psp_v13_0_dump_spirom(struct psp_context *psp,</div><div class='add'>+				 uint64_t fw_pri_mc_addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Confirm PSP is ready to start */</div><div class='add'>+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),</div><div class='add'>+			   MBOX_READY_FLAG, MBOX_READY_MASK, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "PSP Not ready to start processing, ret = %d", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));</div><div class='add'>+</div><div class='add'>+	ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));</div><div class='add'>+</div><div class='add'>+	ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_FLASH_IMAGE);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int psp_v13_0_vbflash_status(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='hunk'>@@ -787,7 +870,9 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp)</div><div class='ctx'> 	if (!con)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) &amp;&amp;</div><div class='add'>+	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+	     amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+	     amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &amp;&amp;</div><div class='ctx'> 	    (!(adev-&gt;flags &amp; AMD_IS_APU))) {</div><div class='ctx'> 		reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);</div><div class='ctx'> 		adev-&gt;ras_hw_enabled = (reg_data &amp; GENMASK_ULL(23, 0));</div><div class='hunk'>@@ -798,6 +883,64 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+	u32 pmfw_ver;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* load 4e version of sos if pmfw version less than 85.115.0 */</div><div class='add'>+	pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);</div><div class='add'>+</div><div class='add'>+	return (pmfw_ver &lt; 0x557300);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool psp_v13_0_is_reload_needed(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	uint32_t ucode_ver;</div><div class='add'>+</div><div class='add'>+	if (!psp_v13_0_is_sos_alive(psp))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Restrict reload support only to specific IP versions */</div><div class='add'>+	switch (amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(13, 0, 2):</div><div class='add'>+	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='add'>+		/* TOS version read from microcode header */</div><div class='add'>+		ucode_ver = psp-&gt;sos.fw_version;</div><div class='add'>+		/* Read TOS version from hardware */</div><div class='add'>+		psp_v13_0_init_sos_version(psp);</div><div class='add'>+		return (ucode_ver != psp-&gt;sos.fw_version);</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,</div><div class='add'>+					 enum psp_reg_prog_id id)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='add'>+	int ret = -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	/* PSP will broadcast the value to all instances */</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET);</div><div class='add'>+		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id);</div><div class='add'>+		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val);</div><div class='add'>+</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='add'>+			0x80000000, 0x80000000, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct psp_funcs psp_v13_0_funcs = {</div><div class='ctx'> 	.init_microcode = psp_v13_0_init_microcode,</div><div class='ctx'> 	.wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,</div><div class='hunk'>@@ -808,6 +951,7 @@ static const struct psp_funcs psp_v13_0_funcs = {</div><div class='ctx'> 	.bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,</div><div class='ctx'> 	.bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,</div><div class='ctx'> 	.bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,</div><div class='add'>+	.bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv,</div><div class='ctx'> 	.bootloader_load_sos = psp_v13_0_bootloader_load_sos,</div><div class='ctx'> 	.ring_create = psp_v13_0_ring_create,</div><div class='ctx'> 	.ring_stop = psp_v13_0_ring_stop,</div><div class='hunk'>@@ -818,9 +962,13 @@ static const struct psp_funcs psp_v13_0_funcs = {</div><div class='ctx'> 	.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,</div><div class='ctx'> 	.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,</div><div class='ctx'> 	.update_spirom = psp_v13_0_update_spirom,</div><div class='add'>+	.dump_spirom = psp_v13_0_dump_spirom,</div><div class='ctx'> 	.vbflash_stat = psp_v13_0_vbflash_status,</div><div class='ctx'> 	.fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,</div><div class='ctx'> 	.get_ras_capability = psp_v13_0_get_ras_capability,</div><div class='add'>+	.is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required,</div><div class='add'>+	.is_reload_needed = psp_v13_0_is_reload_needed,</div><div class='add'>+	.reg_program_no_ring = psp_v13_0_reg_program_no_ring,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void psp_v13_0_set_psp_funcs(struct psp_context *psp)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c<br/>index eaa5512a21da..5f39a2edcc95 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c</a></div><div class='hunk'>@@ -76,11 +76,9 @@ static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)</div><div class='ctx'> 	for (retry_loop = 0; retry_loop &lt; 10; retry_loop++) {</div><div class='ctx'> 		/* Wait for bootloader to signify that is</div><div class='ctx'> 		    ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='del'>-		ret = psp_wait_for(psp,</div><div class='del'>-				   SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='del'>-				   0x80000000,</div><div class='del'>-				   0x80000000,</div><div class='del'>-				   false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='add'>+			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> </div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			return 0;</div><div class='hunk'>@@ -185,8 +183,8 @@ static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> 	/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),</div><div class='del'>-			   RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),</div><div class='del'>-			   0, true);</div><div class='add'>+			   RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,</div><div class='add'>+			   PSP_WAITREG_CHANGED);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -204,8 +202,9 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Write the ring destroy command*/</div><div class='ctx'> 		WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,</div><div class='hunk'>@@ -213,8 +212,9 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -250,13 +250,15 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Wait for sOS ready for ring creation */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -280,8 +282,9 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c<br/>index 78a95f8f370b..38dfc5c19f2a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v14_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v14_0.c</a></div><div class='hunk'>@@ -32,7 +32,13 @@</div><div class='ctx'> #include "mp/mp_14_0_2_sh_mask.h"</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos_kicker.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta_kicker.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin");</div><div class='ctx'> </div><div class='ctx'> /* For large FW files the time to complete can be very long */</div><div class='ctx'> #define USBC_PD_POLLING_LIMIT_S 240</div><div class='hunk'>@@ -66,6 +72,17 @@ static int psp_v14_0_init_microcode(struct psp_context *psp)</div><div class='ctx'> 		err = psp_init_sos_microcode(psp, ucode_prefix);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='add'>+		err = psp_init_ta_microcode(psp, ucode_prefix);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(14, 0, 5):</div><div class='add'>+		err = psp_init_toc_microcode(psp, ucode_prefix);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+		err = psp_init_ta_microcode(psp, ucode_prefix);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		BUG();</div><div class='hunk'>@@ -94,11 +111,9 @@ static int psp_v14_0_wait_for_bootloader(struct psp_context *psp)</div><div class='ctx'> 	for (retry_loop = 0; retry_loop &lt; 10; retry_loop++) {</div><div class='ctx'> 		/* Wait for bootloader to signify that is</div><div class='ctx'> 		    ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='del'>-		ret = psp_wait_for(psp,</div><div class='del'>-				   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='del'>-				   0x80000000,</div><div class='del'>-				   0x80000000,</div><div class='del'>-				   false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='add'>+			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> </div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			return 0;</div><div class='hunk'>@@ -149,7 +164,7 @@ static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> static int psp_v14_0_bootloader_load_spl(struct psp_context *psp)</div><div class='ctx'> {</div><div class='del'>-	return psp_v14_0_bootloader_load_component(psp, &amp;psp-&gt;kdb, PSP_BL__LOAD_TOS_SPL_TABLE);</div><div class='add'>+	return psp_v14_0_bootloader_load_component(psp, &amp;psp-&gt;spl, PSP_BL__LOAD_TOS_SPL_TABLE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp)</div><div class='hunk'>@@ -169,7 +184,8 @@ static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp)</div><div class='ctx'> {</div><div class='del'>-	return psp_v14_0_bootloader_load_component(psp, &amp;psp-&gt;dbg_drv, PSP_BL__LOAD_DBGDRV);</div><div class='add'>+	/* dbg_drv was renamed to had_drv in psp v14 */</div><div class='add'>+	return psp_v14_0_bootloader_load_component(psp, &amp;psp-&gt;dbg_drv, PSP_BL__LOAD_HADDRV);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)</div><div class='hunk'>@@ -177,6 +193,10 @@ static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)</div><div class='ctx'> 	return psp_v14_0_bootloader_load_component(psp, &amp;psp-&gt;ras_drv, PSP_BL__LOAD_RASDRV);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context *psp)</div><div class='add'>+{</div><div class='add'>+	return psp_v14_0_bootloader_load_component(psp, &amp;psp-&gt;ipkeymgr_drv, PSP_BL__LOAD_IPKEYMGRDRV);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> {</div><div class='hunk'>@@ -208,9 +228,10 @@ static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 	mdelay(20);</div><div class='del'>-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),</div><div class='del'>-			   RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81),</div><div class='del'>-			   0, true);</div><div class='add'>+	ret = psp_wait_for(psp,</div><div class='add'>+			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),</div><div class='add'>+			   RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0,</div><div class='add'>+			   PSP_WAITREG_CHANGED);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -228,8 +249,9 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Write the ring destroy command*/</div><div class='ctx'> 		WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,</div><div class='hunk'>@@ -237,8 +259,9 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,</div><div class='ctx'> 		/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> 		/* Wait for response flag (bit 31) */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -274,13 +297,15 @@ static int psp_v14_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Wait for sOS ready for ring creation */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -304,8 +329,9 @@ static int psp_v14_0_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),</div><div class='add'>+			MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -368,8 +394,9 @@ static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg)</div><div class='ctx'> </div><div class='ctx'> 	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev-&gt;usec_timeout;</div><div class='ctx'> 	for (i = 0; i &lt; max_wait; i++) {</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='add'>+			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);</div><div class='ctx'> 		if (ret == 0)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -478,7 +505,7 @@ static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			memcpy_toio(adev-&gt;mman.aper_base_kaddr, buf, sz);</div><div class='del'>-			adev-&gt;hdp.funcs-&gt;flush_hdp(adev, NULL);</div><div class='add'>+			amdgpu_device_flush_hdp(adev, NULL);</div><div class='ctx'> 			vfree(buf);</div><div class='ctx'> 			drm_dev_exit(idx);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -520,8 +547,9 @@ static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc</div><div class='ctx'> 	 */</div><div class='ctx'> 	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr &gt;&gt; 20));</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='del'>-			     0x80000000, 0x80000000, false);</div><div class='add'>+	ret = psp_wait_for(psp,</div><div class='add'>+			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -557,8 +585,9 @@ static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='del'>-				     0x80000000, 0x80000000, false);</div><div class='add'>+	ret = psp_wait_for(psp,</div><div class='add'>+			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		*fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);</div><div class='ctx'> </div><div class='hunk'>@@ -582,11 +611,13 @@ static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd)</div><div class='ctx'> 		ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='ctx'> 						 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);</div><div class='ctx'> 	else</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='del'>-				   MBOX_READY_FLAG, MBOX_READY_MASK, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='add'>+			MBOX_READY_FLAG, MBOX_READY_MASK, 0);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='del'>-				MBOX_READY_FLAG, MBOX_READY_MASK, false);</div><div class='add'>+	ret = psp_wait_for(psp,</div><div class='add'>+			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='add'>+			   MBOX_READY_FLAG, MBOX_READY_MASK, 0);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "SPI cmd %x timed out, ret = %d", cmd, ret);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -609,8 +640,9 @@ static int psp_v14_0_update_spirom(struct psp_context *psp,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Confirm PSP is ready to start */</div><div class='del'>-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='del'>-			   MBOX_READY_FLAG, MBOX_READY_MASK, false);</div><div class='add'>+	ret = psp_wait_for(psp,</div><div class='add'>+			   SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),</div><div class='add'>+			   MBOX_READY_FLAG, MBOX_READY_MASK, 0);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "PSP Not ready to start processing, ret = %d", ret);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -653,6 +685,7 @@ static const struct psp_funcs psp_v14_0_funcs = {</div><div class='ctx'> 	.bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv,</div><div class='ctx'> 	.bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv,</div><div class='ctx'> 	.bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv,</div><div class='add'>+	.bootloader_load_ipkeymgr_drv = psp_v14_0_bootloader_load_ipkeymgr_drv,</div><div class='ctx'> 	.bootloader_load_sos = psp_v14_0_bootloader_load_sos,</div><div class='ctx'> 	.ring_create = psp_v14_0_ring_create,</div><div class='ctx'> 	.ring_stop = psp_v14_0_ring_stop,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c<br/>index f6b75e3e47ff..833830bc3e2e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/psp_v3_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/psp_v3_1.c</a></div><div class='hunk'>@@ -91,7 +91,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -109,7 +109,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)</div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -130,7 +130,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),</div><div class='del'>-			   0x80000000, 0x80000000, false);</div><div class='add'>+			   0x80000000, 0x80000000, 0);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -147,8 +147,8 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)</div><div class='ctx'> 	/* there might be handshake issue with hardware which needs delay */</div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),</div><div class='del'>-			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),</div><div class='del'>-			   0, true);</div><div class='add'>+			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,</div><div class='add'>+			   PSP_WAITREG_CHANGED);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -168,7 +168,7 @@ static void psp_v3_1_reroute_ih(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-		     0x80000000, 0x8000FFFF, false);</div><div class='add'>+		     0x80000000, 0x8000FFFF, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* Change IH ring for UMC */</div><div class='ctx'> 	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);</div><div class='hunk'>@@ -180,7 +180,7 @@ static void psp_v3_1_reroute_ih(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	mdelay(20);</div><div class='ctx'> 	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-		     0x80000000, 0x8000FFFF, false);</div><div class='add'>+		     0x80000000, 0x8000FFFF, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int psp_v3_1_ring_create(struct psp_context *psp,</div><div class='hunk'>@@ -217,9 +217,9 @@ static int psp_v3_1_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_101 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,</div><div class='del'>-					mmMP0_SMN_C2PMSG_101), 0x80000000,</div><div class='del'>-					0x8000FFFF, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			0x80000000, 0x8000FFFF, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> </div><div class='ctx'> 		/* Write low address of the ring to C2PMSG_69 */</div><div class='hunk'>@@ -240,10 +240,9 @@ static int psp_v3_1_ring_create(struct psp_context *psp,</div><div class='ctx'> 		mdelay(20);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for response flag (bit 31) in C2PMSG_64 */</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,</div><div class='del'>-					mmMP0_SMN_C2PMSG_64), 0x80000000,</div><div class='del'>-					0x8000FFFF, false);</div><div class='del'>-</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			0x80000000, 0x8000FFFF, 0);</div><div class='ctx'> 	}</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -267,11 +266,13 @@ static int psp_v3_1_ring_stop(struct psp_context *psp,</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for response flag (bit 31) */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),</div><div class='add'>+			0x80000000, 0x80000000, 0);</div><div class='ctx'> 	else</div><div class='del'>-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='del'>-				   0x80000000, 0x80000000, false);</div><div class='add'>+		ret = psp_wait_for(</div><div class='add'>+			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),</div><div class='add'>+			0x80000000, 0x80000000, 0);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -311,7 +312,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);</div><div class='add'>+	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_INFO("psp is not working correctly before mode1 reset!\n");</div><div class='hunk'>@@ -325,7 +326,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)</div><div class='ctx'> </div><div class='ctx'> 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);</div><div class='ctx'> </div><div class='del'>-	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);</div><div class='add'>+	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_INFO("psp mode 1 reset failed!\n");</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c<br/>index 07e19caf2bc1..92ce580647cd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c</a></div><div class='hunk'>@@ -127,7 +127,6 @@ static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err = 0, i;</div><div class='ctx'> 	struct amdgpu_firmware_info *info = NULL;</div><div class='ctx'> 	const struct common_firmware_header *header = NULL;</div><div class='hunk'>@@ -145,10 +144,13 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='ctx'> 		if (i == 0)</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sdma.bin", chip_name);</div><div class='ctx'> 		else</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sdma1.bin", chip_name);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		hdr = (const struct sdma_firmware_header_v1_0 *)adev-&gt;sdma.instance[i].fw-&gt;data;</div><div class='hunk'>@@ -169,7 +171,8 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("sdma_v2_4: Failed to load firmware \"%s_sdma%s.bin\"\n",</div><div class='add'>+		       chip_name, i == 0 ? "" : "1");</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='ctx'> 			amdgpu_ucode_release(&amp;adev-&gt;sdma.instance[i].fw);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -630,7 +633,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -806,9 +809,9 @@ static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_write(ring, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_early_init(void *handle)</div><div class='add'>+static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;sdma.num_instances = SDMA_MAX_INSTANCE;</div><div class='hunk'>@@ -825,11 +828,11 @@ static int sdma_v2_4_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_sw_init(void *handle)</div><div class='add'>+static int sdma_v2_4_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,</div><div class='hunk'>@@ -865,9 +868,9 @@ static int sdma_v2_4_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_sw_fini(void *handle)</div><div class='add'>+static int sdma_v2_4_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='hunk'>@@ -877,10 +880,10 @@ static int sdma_v2_4_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_hw_init(void *handle)</div><div class='add'>+static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	sdma_v2_4_init_golden_registers(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -891,32 +894,26 @@ static int sdma_v2_4_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_hw_fini(void *handle)</div><div class='add'>+static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	sdma_v2_4_enable(adev, false);</div><div class='add'>+	sdma_v2_4_enable(ip_block-&gt;adev, false);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_suspend(void *handle)</div><div class='add'>+static int sdma_v2_4_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v2_4_hw_fini(adev);</div><div class='add'>+	return sdma_v2_4_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_resume(void *handle)</div><div class='add'>+static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v2_4_hw_init(adev);</div><div class='add'>+	return sdma_v2_4_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v2_4_is_idle(void *handle)</div><div class='add'>+static bool sdma_v2_4_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS2);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; (SRBM_STATUS2__SDMA_BUSY_MASK |</div><div class='hunk'>@@ -926,11 +923,11 @@ static bool sdma_v2_4_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v2_4_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		tmp = RREG32(mmSRBM_STATUS2) &amp; (SRBM_STATUS2__SDMA_BUSY_MASK |</div><div class='hunk'>@@ -943,10 +940,10 @@ static int sdma_v2_4_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_soft_reset(void *handle)</div><div class='add'>+static int sdma_v2_4_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS2);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS2__SDMA_BUSY_MASK) {</div><div class='hunk'>@@ -1085,14 +1082,14 @@ static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v2_4_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* XXX handled via the smc on VI */</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v2_4_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1101,7 +1098,6 @@ static int sdma_v2_4_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v2_4",</div><div class='ctx'> 	.early_init = sdma_v2_4_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = sdma_v2_4_sw_init,</div><div class='ctx'> 	.sw_fini = sdma_v2_4_sw_fini,</div><div class='ctx'> 	.hw_init = sdma_v2_4_hw_init,</div><div class='hunk'>@@ -1176,7 +1172,7 @@ static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: unused</div><div class='add'>+ * @copy_flags: unused</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine (VI).</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1186,7 +1182,7 @@ static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c<br/>index 2ad615be4bb3..1c076bd1cf73 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c</a></div><div class='hunk'>@@ -267,7 +267,6 @@ static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)</div><div class='ctx'> static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const char *chip_name;</div><div class='del'>-	char fw_name[30];</div><div class='ctx'> 	int err = 0, i;</div><div class='ctx'> 	struct amdgpu_firmware_info *info = NULL;</div><div class='ctx'> 	const struct common_firmware_header *header = NULL;</div><div class='hunk'>@@ -305,10 +304,13 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='ctx'> 		if (i == 0)</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sdma.bin", chip_name);</div><div class='ctx'> 		else</div><div class='del'>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw, fw_name);</div><div class='add'>+			err = amdgpu_ucode_request(adev, &amp;adev-&gt;sdma.instance[i].fw,</div><div class='add'>+						   AMDGPU_UCODE_REQUIRED,</div><div class='add'>+						   "amdgpu/%s_sdma1.bin", chip_name);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		hdr = (const struct sdma_firmware_header_v1_0 *)adev-&gt;sdma.instance[i].fw-&gt;data;</div><div class='hunk'>@@ -327,7 +329,8 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='ctx'> 	if (err) {</div><div class='del'>-		pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);</div><div class='add'>+		pr_err("sdma_v3_0: Failed to load firmware \"%s_sdma%s.bin\"\n",</div><div class='add'>+		       chip_name, i == 0 ? "" : "1");</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='ctx'> 			amdgpu_ucode_release(&amp;adev-&gt;sdma.instance[i].fw);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -709,7 +712,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 		       upper_32_bits(wptr_gpu_addr));</div><div class='ctx'> 		wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);</div><div class='ctx'> 		if (ring-&gt;use_pollmem) {</div><div class='del'>-			/*wptr polling is not enogh fast, directly clean the wptr register */</div><div class='add'>+			/*wptr polling is not enough fast, directly clean the wptr register */</div><div class='ctx'> 			WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);</div><div class='ctx'> 			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,</div><div class='ctx'> 						       SDMA0_GFX_RB_WPTR_POLL_CNTL,</div><div class='hunk'>@@ -903,7 +906,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	else</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -1079,9 +1082,9 @@ static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_write(ring, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_early_init(void *handle)</div><div class='add'>+static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='hunk'>@@ -1105,11 +1108,11 @@ static int sdma_v3_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_sw_init(void *handle)</div><div class='add'>+static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,</div><div class='hunk'>@@ -1151,9 +1154,9 @@ static int sdma_v3_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_sw_fini(void *handle)</div><div class='add'>+static int sdma_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='hunk'>@@ -1163,10 +1166,10 @@ static int sdma_v3_0_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_hw_init(void *handle)</div><div class='add'>+static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	sdma_v3_0_init_golden_registers(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1177,9 +1180,9 @@ static int sdma_v3_0_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_hw_fini(void *handle)</div><div class='add'>+static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	sdma_v3_0_ctx_switch_enable(adev, false);</div><div class='ctx'> 	sdma_v3_0_enable(adev, false);</div><div class='hunk'>@@ -1187,23 +1190,19 @@ static int sdma_v3_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_suspend(void *handle)</div><div class='add'>+static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v3_0_hw_fini(adev);</div><div class='add'>+	return sdma_v3_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_resume(void *handle)</div><div class='add'>+static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v3_0_hw_init(adev);</div><div class='add'>+	return sdma_v3_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v3_0_is_idle(void *handle)</div><div class='add'>+static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS2);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; (SRBM_STATUS2__SDMA_BUSY_MASK |</div><div class='hunk'>@@ -1213,11 +1212,11 @@ static bool sdma_v3_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		tmp = RREG32(mmSRBM_STATUS2) &amp; (SRBM_STATUS2__SDMA_BUSY_MASK |</div><div class='hunk'>@@ -1230,9 +1229,9 @@ static int sdma_v3_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v3_0_check_soft_reset(void *handle)</div><div class='add'>+static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS2);</div><div class='ctx'> </div><div class='hunk'>@@ -1251,9 +1250,9 @@ static bool sdma_v3_0_check_soft_reset(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_pre_soft_reset(void *handle)</div><div class='add'>+static int sdma_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;sdma.srbm_soft_reset)</div><div class='hunk'>@@ -1270,9 +1269,9 @@ static int sdma_v3_0_pre_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_post_soft_reset(void *handle)</div><div class='add'>+static int sdma_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;sdma.srbm_soft_reset)</div><div class='hunk'>@@ -1289,9 +1288,9 @@ static int sdma_v3_0_post_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_soft_reset(void *handle)</div><div class='add'>+static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -1486,10 +1485,10 @@ static void sdma_v3_0_update_sdma_medium_grain_light_sleep(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1509,15 +1508,15 @@ static int sdma_v3_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v3_0_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void sdma_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1537,7 +1536,6 @@ static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v3_0",</div><div class='ctx'> 	.early_init = sdma_v3_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = sdma_v3_0_sw_init,</div><div class='ctx'> 	.sw_fini = sdma_v3_0_sw_fini,</div><div class='ctx'> 	.hw_init = sdma_v3_0_hw_init,</div><div class='hunk'>@@ -1616,7 +1614,7 @@ static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: unused</div><div class='add'>+ * @copy_flags: unused</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine (VI).</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1626,7 +1624,7 @@ static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c<br/>index 43775cb67ff5..f38004e6064e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c</a></div><div class='hunk'>@@ -72,6 +72,53 @@ MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L</div><div class='ctx'> #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L</div><div class='ctx'> </div><div class='hunk'>@@ -1518,7 +1565,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -1704,9 +1751,9 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_early_init(void *handle)</div><div class='add'>+static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = sdma_v4_0_init_microcode(adev);</div><div class='hunk'>@@ -1733,9 +1780,9 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,</div><div class='ctx'> 		void *err_data,</div><div class='ctx'> 		struct amdgpu_iv_entry *entry);</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_late_init(void *handle)</div><div class='add'>+static int sdma_v4_0_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	sdma_v4_0_setup_ulv(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1745,11 +1792,13 @@ static int sdma_v4_0_late_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_sw_init(void *handle)</div><div class='add'>+static int sdma_v4_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1870,12 +1919,19 @@ static int sdma_v4_0_sw_init(void *handle)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Allocate memory for SDMA IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (ptr)</div><div class='add'>+		adev-&gt;sdma.ip_dump = ptr;</div><div class='add'>+	else</div><div class='add'>+		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_sw_fini(void *handle)</div><div class='add'>+static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1890,15 +1946,17 @@ static int sdma_v4_0_sw_fini(void *handle)</div><div class='ctx'> 	else</div><div class='ctx'> 		amdgpu_sdma_destroy_inst_ctx(adev, false);</div><div class='ctx'> </div><div class='add'>+	kfree(adev-&gt;sdma.ip_dump);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_hw_init(void *handle)</div><div class='add'>+static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 		sdma_v4_0_init_golden_registers(adev);</div><div class='hunk'>@@ -1906,9 +1964,9 @@ static int sdma_v4_0_hw_init(void *handle)</div><div class='ctx'> 	return sdma_v4_0_start(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_hw_fini(void *handle)</div><div class='add'>+static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1925,14 +1983,14 @@ static int sdma_v4_0_hw_fini(void *handle)</div><div class='ctx'> 	sdma_v4_0_enable(adev, false);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='del'>-		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);</div><div class='add'>+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_suspend(void *handle)</div><div class='add'>+static int sdma_v4_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* SMU saves SDMA state for us */</div><div class='ctx'> 	if (adev-&gt;in_s0ix) {</div><div class='hunk'>@@ -1940,12 +1998,12 @@ static int sdma_v4_0_suspend(void *handle)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return sdma_v4_0_hw_fini(adev);</div><div class='add'>+	return sdma_v4_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_resume(void *handle)</div><div class='add'>+static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* SMU restores SDMA state for us */</div><div class='ctx'> 	if (adev-&gt;in_s0ix) {</div><div class='hunk'>@@ -1954,12 +2012,12 @@ static int sdma_v4_0_resume(void *handle)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return sdma_v4_0_hw_init(adev);</div><div class='add'>+	return sdma_v4_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v4_0_is_idle(void *handle)</div><div class='add'>+static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1972,11 +2030,11 @@ static bool sdma_v4_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i, j;</div><div class='ctx'> 	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;sdma.num_instances; j++) {</div><div class='hunk'>@@ -1991,7 +2049,7 @@ static int sdma_v4_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_soft_reset(void *handle)</div><div class='add'>+static int sdma_v4_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> </div><div class='hunk'>@@ -2017,10 +2075,13 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				      struct amdgpu_irq_src *source,</div><div class='ctx'> 				      struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='del'>-	uint32_t instance;</div><div class='add'>+	int instance;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("IH: SDMA trap\n");</div><div class='ctx'> 	instance = sdma_v4_0_irq_id_to_seq(entry-&gt;client_id);</div><div class='add'>+	if (instance &lt; 0)</div><div class='add'>+		return instance;</div><div class='add'>+</div><div class='ctx'> 	switch (entry-&gt;ring_id) {</div><div class='ctx'> 	case 0:</div><div class='ctx'> 		amdgpu_fence_process(&amp;adev-&gt;sdma.instance[instance].ring);</div><div class='hunk'>@@ -2126,7 +2187,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,</div><div class='ctx'> 		dev_dbg_ratelimited(adev-&gt;dev,</div><div class='ctx'> 				    " for process %s pid %d thread %s pid %d\n",</div><div class='ctx'> 				    task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='del'>-				    task_info-&gt;task_name, task_info-&gt;pid);</div><div class='add'>+				    task_info-&gt;task.comm, task_info-&gt;task.pid);</div><div class='ctx'> 		amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2236,10 +2297,10 @@ static void sdma_v4_0_update_medium_grain_light_sleep(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -2251,10 +2312,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_0_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 1, 0):</div><div class='hunk'>@@ -2270,9 +2331,9 @@ static int sdma_v4_0_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void sdma_v4_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -2289,6 +2350,46 @@ static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_SDMA_LS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void sdma_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;sdma.num_instances);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance:%d\n", i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_0[j].reg_name,</div><div class='add'>+				   adev-&gt;sdma.ip_dump[instance_offset + j]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			adev-&gt;sdma.ip_dump[instance_offset + j] =</div><div class='add'>+				RREG32(sdma_v4_0_get_reg_offset(adev, i,</div><div class='add'>+				       sdma_reg_list_4_0[j].reg_offset));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amd_ip_funcs sdma_v4_0_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v4_0",</div><div class='ctx'> 	.early_init = sdma_v4_0_early_init,</div><div class='hunk'>@@ -2305,6 +2406,8 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = sdma_v4_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = sdma_v4_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = sdma_v4_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = sdma_v4_0_dump_ip_state,</div><div class='add'>+	.print_ip_state = sdma_v4_0_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {</div><div class='hunk'>@@ -2448,7 +2551,7 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: if a secure copy should be used</div><div class='add'>+ * @copy_flags: copy flags for the buffers</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine (VEGA10/12).</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -2458,11 +2561,11 @@ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='del'>-		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags &amp; AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src_offset);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c<br/>index 34237a1b1f2e..a1443990d5c6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c</a></div><div class='hunk'>@@ -30,6 +30,7 @@</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='ctx'> #include "amdgpu_ucode.h"</div><div class='ctx'> #include "amdgpu_trace.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> #include "sdma/sdma_4_4_2_offset.h"</div><div class='ctx'> #include "sdma/sdma_4_4_2_sh_mask.h"</div><div class='hunk'>@@ -44,6 +45,55 @@</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/sdma_4_4_4.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin");</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL)</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> #define mmSMNAID_AID0_MCA_SMU 0x03b30400</div><div class='ctx'> </div><div class='hunk'>@@ -57,6 +107,11 @@ static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev);</div><div class='add'>+static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring);</div><div class='add'>+static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring);</div><div class='add'>+static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev,</div><div class='add'>+					 u32 instance_id);</div><div class='ctx'> </div><div class='ctx'> static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,</div><div class='ctx'> 		u32 instance, u32 offset)</div><div class='hunk'>@@ -82,7 +137,7 @@ static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)</div><div class='add'>+static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id)</div><div class='ctx'> {</div><div class='ctx'> 	switch (client_id) {</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA0:</div><div class='hunk'>@@ -90,9 +145,15 @@ static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA1:</div><div class='ctx'> 		return 1;</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA2:</div><div class='del'>-		return 2;</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;gfx.xcc_mask == 0x1))</div><div class='add'>+			return 0;</div><div class='add'>+		else</div><div class='add'>+			return 2;</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA3:</div><div class='del'>-		return 3;</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;gfx.xcc_mask == 0x1))</div><div class='add'>+			return 1;</div><div class='add'>+		else</div><div class='add'>+			return 3;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -134,8 +195,9 @@ static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='del'>-		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==</div><div class='del'>-		    IP_VERSION(4, 4, 2)) {</div><div class='add'>+		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||</div><div class='add'>+		    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) ||</div><div class='add'>+		    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {</div><div class='ctx'> 			ret = amdgpu_sdma_init_microcode(adev, 0, true);</div><div class='ctx'> 			break;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -368,7 +430,8 @@ static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='ctx'> 	u32 ref_and_mask = 0;</div><div class='ctx'> 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev-&gt;nbio.hdp_flush_reg;</div><div class='ctx'> </div><div class='del'>-	ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_sdma0 &lt;&lt; ring-&gt;me;</div><div class='add'>+	ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_sdma0</div><div class='add'>+		       &lt;&lt; (ring-&gt;me % adev-&gt;sdma.num_inst_per_aid);</div><div class='ctx'> </div><div class='ctx'> 	sdma_v4_4_2_wait_reg_mem(ring, 0, 1,</div><div class='ctx'> 			       adev-&gt;nbio.funcs-&gt;get_hdp_flush_done_offset(adev),</div><div class='hunk'>@@ -430,7 +493,7 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];</div><div class='ctx'> 	u32 doorbell_offset, doorbell;</div><div class='del'>-	u32 rb_cntl, ib_cntl;</div><div class='add'>+	u32 rb_cntl, ib_cntl, sdma_cntl;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for_each_inst(i, inst_mask) {</div><div class='hunk'>@@ -442,6 +505,9 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,</div><div class='ctx'> 		ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);</div><div class='ctx'> 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);</div><div class='ctx'> 		WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);</div><div class='add'>+		sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL);</div><div class='add'>+		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl);</div><div class='ctx'> </div><div class='ctx'> 		if (sdma[i]-&gt;use_doorbell) {</div><div class='ctx'> 			doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);</div><div class='hunk'>@@ -612,11 +678,12 @@ static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @i: instance to resume</div><div class='add'>+ * @restore: used to restore wptr when restart</div><div class='ctx'>  *</div><div class='ctx'>  * Set up the gfx DMA ring buffers and enable them.</div><div class='ctx'>  * Returns 0 for success, error for failure.</div><div class='ctx'>  */</div><div class='del'>-static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='add'>+static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;</div><div class='hunk'>@@ -624,6 +691,7 @@ static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='ctx'> 	u32 doorbell;</div><div class='ctx'> 	u32 doorbell_offset;</div><div class='ctx'> 	u64 wptr_gpu_addr;</div><div class='add'>+	u64 rwptr;</div><div class='ctx'> </div><div class='ctx'> 	wb_offset = (ring-&gt;rptr_offs * 4);</div><div class='ctx'> </div><div class='hunk'>@@ -643,16 +711,32 @@ static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='ctx'> </div><div class='del'>-	ring-&gt;wptr = 0;</div><div class='add'>+	if (!restore)</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);</div><div class='ctx'> </div><div class='add'>+	/* For the guilty queue, set RPTR to the current wptr to skip bad commands,</div><div class='add'>+	 * It is not a guilty queue, restore cache_rptr and continue execution.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;sdma.instance[i].gfx_guilty)</div><div class='add'>+		rwptr = ring-&gt;wptr;</div><div class='add'>+	else</div><div class='add'>+		rwptr = ring-&gt;cached_rptr;</div><div class='add'>+</div><div class='ctx'> 	/* Initialize the ring buffer's read and write pointers */</div><div class='del'>-	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);</div><div class='del'>-	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);</div><div class='del'>-	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);</div><div class='del'>-	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);</div><div class='add'>+	if (restore) {</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);</div><div class='ctx'> 	doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);</div><div class='hunk'>@@ -700,11 +784,12 @@ static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @i: instance to resume</div><div class='add'>+ * @restore: boolean to say restore needed or not</div><div class='ctx'>  *</div><div class='ctx'>  * Set up the page DMA ring buffers and enable them.</div><div class='ctx'>  * Returns 0 for success, error for failure.</div><div class='ctx'>  */</div><div class='del'>-static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='add'>+static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;sdma.instance[i].page;</div><div class='ctx'> 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;</div><div class='hunk'>@@ -712,6 +797,7 @@ static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='ctx'> 	u32 doorbell;</div><div class='ctx'> 	u32 doorbell_offset;</div><div class='ctx'> 	u64 wptr_gpu_addr;</div><div class='add'>+	u64 rwptr;</div><div class='ctx'> </div><div class='ctx'> 	wb_offset = (ring-&gt;rptr_offs * 4);</div><div class='ctx'> </div><div class='hunk'>@@ -719,11 +805,26 @@ static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='ctx'> 	rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);</div><div class='ctx'> </div><div class='add'>+	/* For the guilty queue, set RPTR to the current wptr to skip bad commands,</div><div class='add'>+	 * It is not a guilty queue, restore cache_rptr and continue execution.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;sdma.instance[i].page_guilty)</div><div class='add'>+		rwptr = ring-&gt;wptr;</div><div class='add'>+	else</div><div class='add'>+		rwptr = ring-&gt;cached_rptr;</div><div class='add'>+</div><div class='ctx'> 	/* Initialize the ring buffer's read and write pointers */</div><div class='del'>-	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);</div><div class='del'>-	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);</div><div class='del'>-	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);</div><div class='del'>-	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);</div><div class='add'>+	if (restore) {</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr &lt;&lt; 2));</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);</div><div class='add'>+		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* set the wb address whether it's enabled or not */</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,</div><div class='hunk'>@@ -737,7 +838,8 @@ static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='ctx'> </div><div class='del'>-	ring-&gt;wptr = 0;</div><div class='add'>+	if (!restore)</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='ctx'> 	WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);</div><div class='hunk'>@@ -856,12 +958,13 @@ static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @inst_mask: mask of dma engine instances to be enabled</div><div class='add'>+ * @restore: boolean to say restore needed or not</div><div class='ctx'>  *</div><div class='ctx'>  * Set up the DMA engines and enable them.</div><div class='ctx'>  * Returns 0 for success, error for failure.</div><div class='ctx'>  */</div><div class='ctx'> static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,</div><div class='del'>-				  uint32_t inst_mask)</div><div class='add'>+				  uint32_t inst_mask, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp_mask;</div><div class='hunk'>@@ -872,7 +975,7 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,</div><div class='ctx'> 		sdma_v4_4_2_inst_enable(adev, false, inst_mask);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* bypass sdma microcode loading on Gopher */</div><div class='del'>-		if (adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP &amp;&amp;</div><div class='add'>+		if (!restore &amp;&amp; adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP &amp;&amp;</div><div class='ctx'> 		    adev-&gt;sdma.instance[0].fw) {</div><div class='ctx'> 			r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);</div><div class='ctx'> 			if (r)</div><div class='hunk'>@@ -891,17 +994,20 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,</div><div class='ctx'> 		uint32_t temp;</div><div class='ctx'> </div><div class='ctx'> 		WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);</div><div class='del'>-		sdma_v4_4_2_gfx_resume(adev, i);</div><div class='add'>+		sdma_v4_4_2_gfx_resume(adev, i, restore);</div><div class='ctx'> 		if (adev-&gt;sdma.has_page_queue)</div><div class='del'>-			sdma_v4_4_2_page_resume(adev, i);</div><div class='add'>+			sdma_v4_4_2_page_resume(adev, i, restore);</div><div class='ctx'> </div><div class='ctx'> 		/* set utc l1 enable flag always to 1 */</div><div class='ctx'> 		temp = RREG32_SDMA(i, regSDMA_CNTL);</div><div class='ctx'> 		temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);</div><div class='del'>-		/* enable context empty interrupt during initialization */</div><div class='del'>-		temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);</div><div class='ctx'> 		WREG32_SDMA(i, regSDMA_CNTL, temp);</div><div class='ctx'> </div><div class='add'>+		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) &lt; IP_VERSION(4, 4, 5)) {</div><div class='add'>+			/* enable context empty interrupt during initialization */</div><div class='add'>+			temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);</div><div class='add'>+			WREG32_SDMA(i, regSDMA_CNTL, temp);</div><div class='add'>+		}</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			if (adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 				/* unhalt engine */</div><div class='hunk'>@@ -1055,7 +1161,7 @@ static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -1228,15 +1334,22 @@ static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 4, 2):</div><div class='add'>+	case IP_VERSION(4, 4, 5):</div><div class='ctx'> 		return false;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_early_init(void *handle)</div><div class='add'>+static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = {</div><div class='add'>+	.stop_kernel_queue = &amp;sdma_v4_4_2_stop_queue,</div><div class='add'>+	.start_kernel_queue = &amp;sdma_v4_4_2_restore_queue,</div><div class='add'>+	.soft_reset_kernel_queue = &amp;sdma_v4_4_2_soft_reset_engine,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = sdma_v4_4_2_init_microcode(adev);</div><div class='hunk'>@@ -1252,7 +1365,6 @@ static int sdma_v4_4_2_early_init(void *handle)</div><div class='ctx'> 	sdma_v4_4_2_set_vm_pte_funcs(adev);</div><div class='ctx'> 	sdma_v4_4_2_set_irq_funcs(adev);</div><div class='ctx'> 	sdma_v4_4_2_set_ras_funcs(adev);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1262,9 +1374,9 @@ static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,</div><div class='ctx'> 		struct amdgpu_iv_entry *entry);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_late_init(void *handle)</div><div class='add'>+static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> #if 0</div><div class='ctx'> 	struct ras_ih_if ih_info = {</div><div class='ctx'> 		.cb = sdma_v4_4_2_process_ras_data_cb,</div><div class='hunk'>@@ -1273,15 +1385,23 @@ static int sdma_v4_4_2_late_init(void *handle)</div><div class='ctx'> 	if (!amdgpu_persistent_edc_harvesting_supported(adev))</div><div class='ctx'> 		amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);</div><div class='ctx'> </div><div class='add'>+	/* The initialization is done in the late_init stage to ensure that the SMU</div><div class='add'>+	 * initialization and capability setup are completed before we check the SDMA</div><div class='add'>+	 * reset capability</div><div class='add'>+	 */</div><div class='add'>+	sdma_v4_4_2_update_reset_mask(adev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_sw_init(void *handle)</div><div class='add'>+static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 aid_id;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);</div><div class='add'>+	uint32_t *ptr;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_inst_per_aid; i++) {</div><div class='hunk'>@@ -1326,9 +1446,21 @@ static int sdma_v4_4_2_sw_init(void *handle)</div><div class='ctx'> 				      &amp;adev-&gt;sdma.srbm_write_irq);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),</div><div class='add'>+				      SDMA0_4_0__SRCID__SDMA_CTXEMPTY,</div><div class='add'>+				      &amp;adev-&gt;sdma.ctxt_empty_irq);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		mutex_init(&amp;adev-&gt;sdma.instance[i].engine_reset_mutex);</div><div class='add'>+		/* Initialize guilty flags for GFX and PAGE queues */</div><div class='add'>+		adev-&gt;sdma.instance[i].gfx_guilty = false;</div><div class='add'>+		adev-&gt;sdma.instance[i].page_guilty = false;</div><div class='add'>+		adev-&gt;sdma.instance[i].funcs = &amp;sdma_v4_4_2_sdma_funcs;</div><div class='add'>+</div><div class='ctx'> 		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> 		ring-&gt;ring_obj = NULL;</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='hunk'>@@ -1372,17 +1504,31 @@ static int sdma_v4_4_2_sw_init(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;sdma.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;sdma.instance[0].ring);</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sdma_ras_sw_init(adev)) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "fail to initialize sdma ras block\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Allocate memory for SDMA IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (ptr)</div><div class='add'>+		adev-&gt;sdma.ip_dump = ptr;</div><div class='add'>+	else</div><div class='add'>+		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");</div><div class='add'>+</div><div class='add'>+	r = amdgpu_sdma_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_sw_fini(void *handle)</div><div class='add'>+static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1391,32 +1537,37 @@ static int sdma_v4_4_2_sw_fini(void *handle)</div><div class='ctx'> 			amdgpu_ring_fini(&amp;adev-&gt;sdma.instance[i].page);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2))</div><div class='add'>+	amdgpu_sdma_sysfs_reset_mask_fini(adev);</div><div class='add'>+	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||</div><div class='add'>+	    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) ||</div><div class='add'>+	    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5))</div><div class='ctx'> 		amdgpu_sdma_destroy_inst_ctx(adev, true);</div><div class='ctx'> 	else</div><div class='ctx'> 		amdgpu_sdma_destroy_inst_ctx(adev, false);</div><div class='ctx'> </div><div class='add'>+	kfree(adev-&gt;sdma.ip_dump);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_hw_init(void *handle)</div><div class='add'>+static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	uint32_t inst_mask;</div><div class='ctx'> </div><div class='ctx'> 	inst_mask = GENMASK(adev-&gt;sdma.num_instances - 1, 0);</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);</div><div class='ctx'> </div><div class='del'>-	r = sdma_v4_4_2_inst_start(adev, inst_mask);</div><div class='add'>+	r = sdma_v4_4_2_inst_start(adev, inst_mask, false);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_hw_fini(void *handle)</div><div class='add'>+static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	uint32_t inst_mask;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -1437,29 +1588,27 @@ static int sdma_v4_4_2_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					     enum amd_clockgating_state state);</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_suspend(void *handle)</div><div class='add'>+static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_in_reset(adev))</div><div class='del'>-		sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);</div><div class='add'>+		sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);</div><div class='ctx'> </div><div class='del'>-	return sdma_v4_4_2_hw_fini(adev);</div><div class='add'>+	return sdma_v4_4_2_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_resume(void *handle)</div><div class='add'>+static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v4_4_2_hw_init(adev);</div><div class='add'>+	return sdma_v4_4_2_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v4_4_2_is_idle(void *handle)</div><div class='add'>+static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1472,11 +1621,11 @@ static bool sdma_v4_4_2_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i, j;</div><div class='ctx'> 	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;sdma.num_instances; j++) {</div><div class='hunk'>@@ -1491,13 +1640,109 @@ static int sdma_v4_4_2_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_soft_reset(void *handle)</div><div class='add'>+static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;</div><div class='add'>+	uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));</div><div class='add'>+</div><div class='add'>+	/* Check if the SELECTED bit is set */</div><div class='add'>+	return (context_status &amp; SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,</div><div class='add'>+				   unsigned int vmid,</div><div class='add'>+				   struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 id = ring-&gt;me;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_amdkfd_suspend(adev, true);</div><div class='add'>+	r = amdgpu_sdma_reset_engine(adev, id, false);</div><div class='add'>+	amdgpu_amdkfd_resume(adev, true);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 instance_id = ring-&gt;me;</div><div class='add'>+	u32 inst_mask;</div><div class='add'>+	uint64_t rptr;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Check if this queue is the guilty one */</div><div class='add'>+	adev-&gt;sdma.instance[instance_id].gfx_guilty =</div><div class='add'>+		sdma_v4_4_2_is_queue_selected(adev, instance_id, false);</div><div class='add'>+	if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+		adev-&gt;sdma.instance[instance_id].page_guilty =</div><div class='add'>+			sdma_v4_4_2_is_queue_selected(adev, instance_id, true);</div><div class='add'>+</div><div class='add'>+	/* Cache the rptr before reset, after the reset,</div><div class='add'>+	* all of the registers will be reset to 0</div><div class='add'>+	*/</div><div class='add'>+	rptr = amdgpu_ring_get_rptr(ring);</div><div class='add'>+	ring-&gt;cached_rptr = rptr;</div><div class='add'>+	/* Cache the rptr for the page queue if it exists */</div><div class='add'>+	if (adev-&gt;sdma.has_page_queue) {</div><div class='add'>+		struct amdgpu_ring *page_ring = &amp;adev-&gt;sdma.instance[instance_id].page;</div><div class='add'>+		rptr = amdgpu_ring_get_rptr(page_ring);</div><div class='add'>+		page_ring-&gt;cached_rptr = rptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* stop queue */</div><div class='add'>+	inst_mask = 1 &lt;&lt; ring-&gt;me;</div><div class='add'>+	sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);</div><div class='add'>+	if (adev-&gt;sdma.has_page_queue)</div><div class='add'>+		sdma_v4_4_2_inst_page_stop(adev, inst_mask);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 inst_mask;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	inst_mask = 1 &lt;&lt; ring-&gt;me;</div><div class='add'>+	udelay(50);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (!REG_GET_FIELD(RREG32_SDMA(ring-&gt;me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i == adev-&gt;usec_timeout) {</div><div class='add'>+		dev_err(adev-&gt;dev, "timed out waiting for SDMA%d unhalt after reset\n",</div><div class='add'>+			ring-&gt;me);</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = sdma_v4_4_2_inst_start(adev, inst_mask, true);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev,</div><div class='add'>+					 u32 instance_id)</div><div class='add'>+{</div><div class='add'>+	/* For SDMA 4.x, use the existing DPM interface for backward compatibility</div><div class='add'>+	 * we need to convert the logical instance ID to physical instance ID before reset.</div><div class='add'>+	 */</div><div class='add'>+	return amdgpu_dpm_reset_sdma(adev, 1 &lt;&lt; GET_INST(SDMA0, instance_id));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 					struct amdgpu_irq_src *source,</div><div class='ctx'> 					unsigned type,</div><div class='hunk'>@@ -1520,7 +1765,7 @@ static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	uint32_t instance, i;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("IH: SDMA trap\n");</div><div class='del'>-	instance = sdma_v4_4_2_irq_id_to_seq(entry-&gt;client_id);</div><div class='add'>+	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry-&gt;client_id);</div><div class='ctx'> </div><div class='ctx'> 	/* Client id gives the SDMA instance in AID. To know the exact SDMA</div><div class='ctx'> 	 * instance, interrupt entry gives the node id which corresponds to the AID instance.</div><div class='hunk'>@@ -1543,6 +1788,9 @@ static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	case 0:</div><div class='ctx'> 		amdgpu_fence_process(&amp;adev-&gt;sdma.instance[i].ring);</div><div class='ctx'> 		break;</div><div class='add'>+	case 1:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;sdma.instance[i].page);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1563,7 +1811,7 @@ static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,</div><div class='ctx'> 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	instance = sdma_v4_4_2_irq_id_to_seq(entry-&gt;client_id);</div><div class='add'>+	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry-&gt;client_id);</div><div class='ctx'> 	if (instance &lt; 0)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -1582,7 +1830,7 @@ static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	DRM_ERROR("Illegal instruction in SDMA command stream\n");</div><div class='ctx'> </div><div class='del'>-	instance = sdma_v4_4_2_irq_id_to_seq(entry-&gt;client_id);</div><div class='add'>+	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry-&gt;client_id);</div><div class='ctx'> 	if (instance &lt; 0)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1602,19 +1850,9 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 	u32 sdma_cntl;</div><div class='ctx'> </div><div class='ctx'> 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);</div><div class='del'>-	switch (state) {</div><div class='del'>-	case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,</div><div class='del'>-					  DRAM_ECC_INT_ENABLE, 0);</div><div class='del'>-		WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);</div><div class='del'>-		break;</div><div class='del'>-	/* sdma ecc interrupt is enabled by default</div><div class='del'>-	 * driver doesn't need to do anything to</div><div class='del'>-	 * enable the interrupt */</div><div class='del'>-	case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,</div><div class='add'>+					state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1626,7 +1864,7 @@ static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,</div><div class='ctx'> 	struct amdgpu_task_info *task_info;</div><div class='ctx'> 	u64 addr;</div><div class='ctx'> </div><div class='del'>-	instance = sdma_v4_4_2_irq_id_to_seq(entry-&gt;client_id);</div><div class='add'>+	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry-&gt;client_id);</div><div class='ctx'> 	if (instance &lt; 0 || instance &gt;= adev-&gt;sdma.num_instances) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "sdma instance invalid %d\n", instance);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1644,7 +1882,7 @@ static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,</div><div class='ctx'> 	if (task_info) {</div><div class='ctx'> 		dev_dbg_ratelimited(adev-&gt;dev, " for process %s pid %d thread %s pid %d\n",</div><div class='ctx'> 				    task_info-&gt;process_name, task_info-&gt;tgid,</div><div class='del'>-				    task_info-&gt;task_name, task_info-&gt;pid);</div><div class='add'>+				    task_info-&gt;task.comm, task_info-&gt;task.pid);</div><div class='ctx'> 		amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1690,6 +1928,16 @@ static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev,</div><div class='add'>+					      struct amdgpu_irq_src *source,</div><div class='add'>+					      struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	/* There is nothing useful to be done here, only kept for debug */</div><div class='add'>+	dev_dbg_ratelimited(adev-&gt;dev, "SDMA context empty interrupt");</div><div class='add'>+	sdma_v4_4_2_print_iv_entry(adev, entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(</div><div class='ctx'> 	struct amdgpu_device *adev, bool enable, uint32_t inst_mask)</div><div class='ctx'> {</div><div class='hunk'>@@ -1756,10 +2004,10 @@ static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	uint32_t inst_mask;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1774,15 +2022,15 @@ static int sdma_v4_4_2_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1799,6 +2047,46 @@ static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_SDMA_LS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;sdma.num_instances);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance:%d\n", i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name,</div><div class='add'>+				   adev-&gt;sdma.ip_dump[instance_offset + j]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			adev-&gt;sdma.ip_dump[instance_offset + j] =</div><div class='add'>+				RREG32(sdma_v4_4_2_get_reg_offset(adev, i,</div><div class='add'>+				       sdma_reg_list_4_4_2[j].reg_offset));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v4_4_2",</div><div class='ctx'> 	.early_init = sdma_v4_4_2_early_init,</div><div class='hunk'>@@ -1815,6 +2103,8 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = sdma_v4_4_2_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = sdma_v4_4_2_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = sdma_v4_4_2_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = sdma_v4_4_2_dump_ip_state,</div><div class='add'>+	.print_ip_state = sdma_v4_4_2_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {</div><div class='hunk'>@@ -1846,6 +2136,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {</div><div class='ctx'> 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = sdma_v4_4_2_reset_queue,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {</div><div class='hunk'>@@ -1877,6 +2168,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {</div><div class='ctx'> 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = sdma_v4_4_2_reset_queue,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1929,6 +2221,10 @@ static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {</div><div class='ctx'> 	.process = sdma_v4_4_2_process_srbm_write_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = {</div><div class='add'>+	.process = sdma_v4_4_2_process_ctxt_empty_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;sdma.trap_irq.num_types = adev-&gt;sdma.num_instances;</div><div class='hunk'>@@ -1937,6 +2233,7 @@ static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;sdma.doorbell_invalid_irq.num_types = adev-&gt;sdma.num_instances;</div><div class='ctx'> 	adev-&gt;sdma.pool_timeout_irq.num_types = adev-&gt;sdma.num_instances;</div><div class='ctx'> 	adev-&gt;sdma.srbm_write_irq.num_types = adev-&gt;sdma.num_instances;</div><div class='add'>+	adev-&gt;sdma.ctxt_empty_irq.num_types = adev-&gt;sdma.num_instances;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;sdma.trap_irq.funcs = &amp;sdma_v4_4_2_trap_irq_funcs;</div><div class='ctx'> 	adev-&gt;sdma.illegal_inst_irq.funcs = &amp;sdma_v4_4_2_illegal_inst_irq_funcs;</div><div class='hunk'>@@ -1945,6 +2242,7 @@ static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;sdma.doorbell_invalid_irq.funcs = &amp;sdma_v4_4_2_doorbell_invalid_irq_funcs;</div><div class='ctx'> 	adev-&gt;sdma.pool_timeout_irq.funcs = &amp;sdma_v4_4_2_pool_timeout_irq_funcs;</div><div class='ctx'> 	adev-&gt;sdma.srbm_write_irq.funcs = &amp;sdma_v4_4_2_srbm_write_irq_funcs;</div><div class='add'>+	adev-&gt;sdma.ctxt_empty_irq.funcs = &amp;sdma_v4_4_2_ctxt_empty_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1954,7 +2252,7 @@ static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: if a secure copy should be used</div><div class='add'>+ * @copy_flags: copy flags for the buffers</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine.</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1964,11 +2262,11 @@ static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='del'>-		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags &amp; AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src_offset);</div><div class='hunk'>@@ -2042,6 +2340,44 @@ static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;vm_manager.vm_pte_num_scheds = adev-&gt;sdma.num_instances;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * sdma_v4_4_2_update_reset_mask - update  reset mask for SDMA</div><div class='add'>+ * @adev: Pointer to the AMDGPU device structure</div><div class='add'>+ *</div><div class='add'>+ * This function update reset mask for SDMA and sets the supported</div><div class='add'>+ * reset types based on the IP version and firmware versions.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* per queue reset not supported for SRIOV */</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * the user queue relies on MEC fw and pmfw when the sdma queue do reset.</div><div class='add'>+	 * it needs to check both of them at here to skip old mec and pmfw.</div><div class='add'>+	 */</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+		if ((adev-&gt;gfx.mec_fw_version &gt;= 0xb0) &amp;&amp;</div><div class='add'>+		    amdgpu_dpm_reset_sdma_is_supported(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+			adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='add'>+		if ((adev-&gt;gfx.mec_fw_version &gt;= 0xf) &amp;&amp;</div><div class='add'>+		    amdgpu_dpm_reset_sdma_is_supported(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+			adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {</div><div class='ctx'> 	.type = AMD_IP_BLOCK_TYPE_SDMA,</div><div class='ctx'> 	.major = 4,</div><div class='hunk'>@@ -2058,7 +2394,7 @@ static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='ctx'> 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);</div><div class='ctx'> </div><div class='del'>-	r = sdma_v4_4_2_inst_start(adev, inst_mask);</div><div class='add'>+	r = sdma_v4_4_2_inst_start(adev, inst_mask, false);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -2141,7 +2477,7 @@ static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 					AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,</div><div class='ctx'> 					&amp;ue_count);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,</div><div class='hunk'>@@ -2189,35 +2525,41 @@ static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {</div><div class='ctx'> 	.reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int sdma_v4_4_2_aca_bank_generate_report(struct aca_handle *handle,</div><div class='del'>-						struct aca_bank *bank, enum aca_error_type type,</div><div class='del'>-						struct aca_bank_report *report, void *data)</div><div class='add'>+static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				       enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='del'>-	u64 status, misc0;</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	status = bank-&gt;regs[ACA_REG_IDX_STATUS];</div><div class='del'>-	if ((type == ACA_ERROR_TYPE_UE &amp;&amp;</div><div class='del'>-	     ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) ||</div><div class='del'>-	    (type == ACA_ERROR_TYPE_CE &amp;&amp;</div><div class='del'>-	     ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {</div><div class='del'>-</div><div class='del'>-		ret = aca_bank_info_decode(bank, &amp;report-&gt;info);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-		misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='del'>-		report-&gt;count[type] = ACA_REG__MISC0__ERRCNT(misc0);</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE,</div><div class='add'>+						     1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */</div><div class='ctx'> static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };</div><div class='ctx'> </div><div class='ctx'> static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='del'>-					  enum aca_error_type type, void *data)</div><div class='add'>+					  enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	u32 instlo;</div><div class='ctx'> </div><div class='hunk'>@@ -2236,7 +2578,7 @@ static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {</div><div class='del'>-	.aca_bank_generate_report = sdma_v4_4_2_aca_bank_generate_report,</div><div class='add'>+	.aca_bank_parser = sdma_v4_4_2_aca_bank_parser,</div><div class='ctx'> 	.aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c<br/>index 883e8a1b8a40..8ddc4df06a1f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c</a></div><div class='hunk'>@@ -59,10 +59,61 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");</div><div class='ctx'> #define SDMA0_HYP_DEC_REG_END 0x5893</div><div class='ctx'> #define SDMA1_HYP_DEC_REG_OFFSET 0x20</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring);</div><div class='add'>+static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> static const struct soc15_reg_golden golden_settings_sdma_5[] = {</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),</div><div class='hunk'>@@ -320,67 +371,36 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	uint32_t *wptr_saved;</div><div class='del'>-	uint32_t *is_queue_unmap;</div><div class='del'>-	uint64_t aggregated_db_index;</div><div class='del'>-	uint32_t mqd_size = adev-&gt;mqds[AMDGPU_HW_IP_DMA].mqd_size;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("Setting write pointer\n");</div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		wptr_saved = (uint32_t *)(ring-&gt;mqd_ptr + mqd_size);</div><div class='del'>-		is_queue_unmap = (uint32_t *)(ring-&gt;mqd_ptr + mqd_size +</div><div class='del'>-					      sizeof(uint32_t));</div><div class='del'>-		aggregated_db_index =</div><div class='del'>-			amdgpu_mes_get_aggregated_doorbell_index(adev,</div><div class='del'>-			AMDGPU_MES_PRIORITY_LEVEL_NORMAL);</div><div class='del'>-</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		DRM_DEBUG("Using doorbell -- "</div><div class='add'>+			  "wptr_offs == 0x%08x "</div><div class='add'>+			  "lower_32_bits(ring-&gt;wptr) &lt;&lt; 2 == 0x%08x "</div><div class='add'>+			  "upper_32_bits(ring-&gt;wptr) &lt;&lt; 2 == 0x%08x\n",</div><div class='add'>+			  ring-&gt;wptr_offs,</div><div class='add'>+			  lower_32_bits(ring-&gt;wptr &lt;&lt; 2),</div><div class='add'>+			  upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		/* XXX check if swapping is necessary on BE */</div><div class='ctx'> 		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='ctx'> 			     ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-		*wptr_saved = ring-&gt;wptr &lt;&lt; 2;</div><div class='del'>-		if (*is_queue_unmap) {</div><div class='del'>-			WDOORBELL64(aggregated_db_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",</div><div class='del'>-					ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-		} else {</div><div class='del'>-			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",</div><div class='del'>-					ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-</div><div class='del'>-			if (*is_queue_unmap)</div><div class='del'>-				WDOORBELL64(aggregated_db_index,</div><div class='del'>-					    ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-		}</div><div class='add'>+		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",</div><div class='add'>+			  ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='ctx'> 	} else {</div><div class='del'>-		if (ring-&gt;use_doorbell) {</div><div class='del'>-			DRM_DEBUG("Using doorbell -- "</div><div class='del'>-				  "wptr_offs == 0x%08x "</div><div class='del'>-				  "lower_32_bits(ring-&gt;wptr) &lt;&lt; 2 == 0x%08x "</div><div class='del'>-				  "upper_32_bits(ring-&gt;wptr) &lt;&lt; 2 == 0x%08x\n",</div><div class='del'>-				  ring-&gt;wptr_offs,</div><div class='del'>-				  lower_32_bits(ring-&gt;wptr &lt;&lt; 2),</div><div class='del'>-				  upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-			/* XXX check if swapping is necessary on BE */</div><div class='del'>-			atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='del'>-				     ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",</div><div class='del'>-				  ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-			WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-		} else {</div><div class='del'>-			DRM_DEBUG("Not using doorbell -- "</div><div class='del'>-				  "mmSDMA%i_GFX_RB_WPTR == 0x%08x "</div><div class='del'>-				  "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",</div><div class='del'>-				  ring-&gt;me,</div><div class='del'>-				  lower_32_bits(ring-&gt;wptr &lt;&lt; 2),</div><div class='del'>-				  ring-&gt;me,</div><div class='del'>-				  upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,</div><div class='del'>-					     ring-&gt;me, mmSDMA0_GFX_RB_WPTR),</div><div class='del'>-					lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,</div><div class='del'>-					     ring-&gt;me, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='del'>-					upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-		}</div><div class='add'>+		DRM_DEBUG("Not using doorbell -- "</div><div class='add'>+			  "mmSDMA%i_GFX_RB_WPTR == 0x%08x "</div><div class='add'>+			  "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",</div><div class='add'>+			  ring-&gt;me,</div><div class='add'>+			  lower_32_bits(ring-&gt;wptr &lt;&lt; 2),</div><div class='add'>+			  ring-&gt;me,</div><div class='add'>+			  upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,</div><div class='add'>+							     ring-&gt;me, mmSDMA0_GFX_RB_WPTR),</div><div class='add'>+				lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,</div><div class='add'>+							     ring-&gt;me, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='add'>+				upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -526,11 +546,9 @@ static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (flags &amp; AMDGPU_FENCE_FLAG_INT) {</div><div class='del'>-		uint32_t ctx = ring-&gt;is_mes_queue ?</div><div class='del'>-			(ring-&gt;hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;</div><div class='ctx'> 		/* generate an interrupt */</div><div class='ctx'> 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));</div><div class='del'>-		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -539,15 +557,15 @@ static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se</div><div class='ctx'>  * sdma_v5_0_gfx_stop - stop the gfx async dma engines</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='add'>+ * @inst_mask: mask of dma engine instances to be disabled</div><div class='ctx'>  * Stop the gfx async dma ring buffers (NAVI10).</div><div class='ctx'>  */</div><div class='del'>-static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)</div><div class='add'>+static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask)</div><div class='ctx'> {</div><div class='ctx'> 	u32 rb_cntl, ib_cntl;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+	for_each_inst(i, inst_mask) {</div><div class='ctx'> 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));</div><div class='ctx'> 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='hunk'>@@ -639,9 +657,11 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 f32_cntl;</div><div class='ctx'> 	int i;</div><div class='add'>+	uint32_t inst_mask;</div><div class='ctx'> </div><div class='add'>+	inst_mask = GENMASK(adev-&gt;sdma.num_instances - 1, 0);</div><div class='ctx'> 	if (!enable) {</div><div class='del'>-		sdma_v5_0_gfx_stop(adev);</div><div class='add'>+		sdma_v5_0_gfx_stop(adev, 1 &lt;&lt; inst_mask);</div><div class='ctx'> 		sdma_v5_0_rlc_stop(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -656,14 +676,16 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * sdma_v5_0_gfx_resume - setup and start the async dma engines</div><div class='add'>+ * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='add'>+ * @i: instance</div><div class='add'>+ * @restore: used to restore wptr when restart</div><div class='ctx'>  *</div><div class='del'>- * Set up the gfx DMA ring buffers and enable them (NAVI10).</div><div class='del'>- * Returns 0 for success, error for failure.</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.</div><div class='add'>+ * Return 0 for success.</div><div class='ctx'>  */</div><div class='del'>-static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	u32 rb_cntl, ib_cntl;</div><div class='hunk'>@@ -673,142 +695,163 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 temp;</div><div class='ctx'> 	u32 wptr_poll_cntl;</div><div class='ctx'> 	u64 wptr_gpu_addr;</div><div class='del'>-	int i, r;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+	ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev))</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);</div><div class='ctx'> </div><div class='del'>-		/* Set ring buffer size in dwords */</div><div class='del'>-		rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='del'>-		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='add'>+	/* Set ring buffer size in dwords */</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='add'>+	rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,</div><div class='del'>-					RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,</div><div class='add'>+				RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='ctx'> #endif</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='del'>-</div><div class='del'>-		/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='add'>+</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	if (restore) {</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	} else {</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);</div><div class='del'>-</div><div class='del'>-		/* setup the wptr shadow polling */</div><div class='del'>-		wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),</div><div class='del'>-		       lower_32_bits(wptr_gpu_addr));</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),</div><div class='del'>-		       upper_32_bits(wptr_gpu_addr));</div><div class='del'>-		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,</div><div class='del'>-							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));</div><div class='del'>-		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,</div><div class='del'>-					       SDMA0_GFX_RB_WPTR_POLL_CNTL,</div><div class='del'>-					       F32_POLL_ENABLE, 1);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),</div><div class='del'>-		       wptr_poll_cntl);</div><div class='del'>-</div><div class='del'>-		/* set the wb address whether it's enabled or not */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),</div><div class='del'>-		       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),</div><div class='del'>-		       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='del'>-</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),</div><div class='del'>-		       ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),</div><div class='del'>-		       ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='del'>-</div><div class='add'>+	}</div><div class='add'>+	/* setup the wptr shadow polling */</div><div class='add'>+	wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	       lower_32_bits(wptr_gpu_addr));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	       upper_32_bits(wptr_gpu_addr));</div><div class='add'>+	wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,</div><div class='add'>+						 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));</div><div class='add'>+	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,</div><div class='add'>+				       SDMA0_GFX_RB_WPTR_POLL_CNTL,</div><div class='add'>+				       F32_POLL_ENABLE, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),</div><div class='add'>+	       wptr_poll_cntl);</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),</div><div class='add'>+	       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),</div><div class='add'>+	       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='add'>+</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),</div><div class='add'>+	       ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),</div><div class='add'>+	       ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='add'>+</div><div class='add'>+	if (!restore)</div><div class='ctx'> 		ring-&gt;wptr = 0;</div><div class='ctx'> </div><div class='del'>-		/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);</div><div class='add'>+	/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),</div><div class='del'>-			       lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='del'>-			       upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-		}</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),</div><div class='add'>+		       lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='add'>+		       upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));</div><div class='del'>-		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,</div><div class='del'>-						mmSDMA0_GFX_DOORBELL_OFFSET));</div><div class='add'>+	doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));</div><div class='add'>+	doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,</div><div class='add'>+					mmSDMA0_GFX_DOORBELL_OFFSET));</div><div class='ctx'> </div><div class='del'>-		if (ring-&gt;use_doorbell) {</div><div class='del'>-			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);</div><div class='del'>-			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,</div><div class='del'>-					OFFSET, ring-&gt;doorbell_index);</div><div class='del'>-		} else {</div><div class='del'>-			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),</div><div class='del'>-		       doorbell_offset);</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);</div><div class='add'>+		doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,</div><div class='add'>+				OFFSET, ring-&gt;doorbell_index);</div><div class='add'>+	} else {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),</div><div class='add'>+	       doorbell_offset);</div><div class='ctx'> </div><div class='del'>-		adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='del'>-						      ring-&gt;doorbell_index, 20);</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='add'>+					      ring-&gt;doorbell_index, 20);</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_sriov_vf(adev))</div><div class='del'>-			sdma_v5_0_ring_set_wptr(ring);</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		sdma_v5_0_ring_set_wptr(ring);</div><div class='ctx'> </div><div class='del'>-		/* set minor_ptr_update to 0 after wptr programed */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);</div><div class='add'>+	/* set minor_ptr_update to 0 after wptr programed */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-			/* set utc l1 enable flag always to 1 */</div><div class='del'>-			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);</div><div class='del'>-</div><div class='del'>-			/* enable MCBP */</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);</div><div class='del'>-</div><div class='del'>-			/* Set up RESP_MODE to non-copy addresses */</div><div class='del'>-			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);</div><div class='del'>-</div><div class='del'>-			/* program default cache read and write policy */</div><div class='del'>-			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));</div><div class='del'>-			/* clean read policy and write policy bits */</div><div class='del'>-			temp &amp;= 0xFF0FFF;</div><div class='del'>-			temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) | (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14));</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);</div><div class='del'>-		}</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* set utc l1 enable flag always to 1 */</div><div class='add'>+		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+		/* enable MCBP */</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);</div><div class='add'>+</div><div class='add'>+		/* Set up RESP_MODE to non-copy addresses */</div><div class='add'>+		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);</div><div class='add'>+</div><div class='add'>+		/* program default cache read and write policy */</div><div class='add'>+		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));</div><div class='add'>+		/* clean read policy and write policy bits */</div><div class='add'>+		temp &amp;= 0xFF0FFF;</div><div class='add'>+		temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) | (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14));</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-			/* unhalt engine */</div><div class='del'>-			temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);</div><div class='del'>-			WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);</div><div class='del'>-		}</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* unhalt engine */</div><div class='add'>+		temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);</div><div class='add'>+		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* enable DMA RB */</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='add'>+	/* enable DMA RB */</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='ctx'> </div><div class='del'>-		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));</div><div class='del'>-		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);</div><div class='add'>+	ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='ctx'> #endif</div><div class='del'>-		/* enable DMA IBs */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);</div><div class='add'>+	/* enable DMA IBs */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */</div><div class='del'>-			sdma_v5_0_ctx_switch_enable(adev, true);</div><div class='del'>-			sdma_v5_0_enable(adev, true);</div><div class='del'>-		}</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */</div><div class='add'>+		sdma_v5_0_ctx_switch_enable(adev, true);</div><div class='add'>+		sdma_v5_0_enable(adev, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_test_helper(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v5_0_gfx_resume - setup and start the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them (NAVI10).</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ring_test_helper(ring);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		r = sdma_v5_0_gfx_resume_instance(adev, i, false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -974,28 +1017,18 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	int r;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	u64 gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	tmp = 0xCAFEDEAD;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		*cpu_ptr = tmp;</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, 20);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring-&gt;idx, r);</div><div class='hunk'>@@ -1012,10 +1045,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (ring-&gt;is_mes_queue)</div><div class='del'>-			tmp = le32_to_cpu(*cpu_ptr);</div><div class='del'>-		else</div><div class='del'>-			tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='ctx'> 		if (tmp == 0xDEADBEEF)</div><div class='ctx'> 			break;</div><div class='ctx'> 		if (amdgpu_emu_mode == 1)</div><div class='hunk'>@@ -1027,8 +1057,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	if (i &gt;= adev-&gt;usec_timeout)</div><div class='ctx'> 		r = -ETIMEDOUT;</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -1051,38 +1080,24 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	long r;</div><div class='ctx'> 	u32 tmp = 0;</div><div class='ctx'> 	u64 gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	tmp = 0xCAFEDEAD;</div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);</div><div class='del'>-		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		*cpu_ptr = tmp;</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ib_get(adev, NULL, 256,</div><div class='del'>-					AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='del'>-			goto err0;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 256,</div><div class='add'>+			  AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |</div><div class='hunk'>@@ -1110,10 +1125,7 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		goto err1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		tmp = le32_to_cpu(*cpu_ptr);</div><div class='del'>-	else</div><div class='del'>-		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+	tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp == 0xDEADBEEF)</div><div class='ctx'> 		r = 0;</div><div class='hunk'>@@ -1121,11 +1133,10 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1316,9 +1327,39 @@ static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_early_init(void *handle)</div><div class='add'>+static int sdma_v5_0_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	u32 grbm_soft_reset;</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	grbm_soft_reset = REG_SET_FIELD(0,</div><div class='add'>+					GRBM_SOFT_RESET, SOFT_RESET_SDMA0,</div><div class='add'>+					1);</div><div class='add'>+	grbm_soft_reset &lt;&lt;= instance_id;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+	tmp |= grbm_soft_reset;</div><div class='add'>+	DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+	WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+</div><div class='add'>+	udelay(50);</div><div class='add'>+</div><div class='add'>+	tmp &amp;= ~grbm_soft_reset;</div><div class='add'>+	WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_sdma_funcs sdma_v5_0_sdma_funcs = {</div><div class='add'>+	.stop_kernel_queue = &amp;sdma_v5_0_stop_queue,</div><div class='add'>+	.start_kernel_queue = &amp;sdma_v5_0_restore_queue,</div><div class='add'>+	.soft_reset_kernel_queue = &amp;sdma_v5_0_soft_reset_engine,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = sdma_v5_0_init_microcode(adev);</div><div class='hunk'>@@ -1335,11 +1376,13 @@ static int sdma_v5_0_early_init(void *handle)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_sw_init(void *handle)</div><div class='add'>+static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,</div><div class='hunk'>@@ -1356,6 +1399,8 @@ static int sdma_v5_0_sw_init(void *handle)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		mutex_init(&amp;adev-&gt;sdma.instance[i].engine_reset_mutex);</div><div class='add'>+		adev-&gt;sdma.instance[i].funcs = &amp;sdma_v5_0_sdma_funcs;</div><div class='ctx'> 		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> 		ring-&gt;ring_obj = NULL;</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='hunk'>@@ -1377,26 +1422,55 @@ static int sdma_v5_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;sdma.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;sdma.instance[0].ring);</div><div class='add'>+	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(5, 0, 0):</div><div class='add'>+	case IP_VERSION(5, 0, 2):</div><div class='add'>+	case IP_VERSION(5, 0, 5):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 35) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+			adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for SDMA IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (ptr)</div><div class='add'>+		adev-&gt;sdma.ip_dump = ptr;</div><div class='add'>+	else</div><div class='add'>+		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");</div><div class='add'>+</div><div class='add'>+	r = amdgpu_sdma_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_sw_fini(void *handle)</div><div class='add'>+static int sdma_v5_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;sdma.instance[i].ring);</div><div class='ctx'> </div><div class='add'>+	amdgpu_sdma_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	amdgpu_sdma_destroy_inst_ctx(adev, false);</div><div class='ctx'> </div><div class='add'>+	kfree(adev-&gt;sdma.ip_dump);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_hw_init(void *handle)</div><div class='add'>+static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	sdma_v5_0_init_golden_registers(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1405,9 +1479,9 @@ static int sdma_v5_0_hw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_hw_fini(void *handle)</div><div class='add'>+static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1418,23 +1492,19 @@ static int sdma_v5_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_suspend(void *handle)</div><div class='add'>+static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v5_0_hw_fini(adev);</div><div class='add'>+	return sdma_v5_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_resume(void *handle)</div><div class='add'>+static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v5_0_hw_init(adev);</div><div class='add'>+	return sdma_v5_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v5_0_is_idle(void *handle)</div><div class='add'>+static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1447,11 +1517,11 @@ static bool sdma_v5_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 sdma0, sdma1;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));</div><div class='hunk'>@@ -1464,13 +1534,104 @@ static int sdma_v5_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_soft_reset(void *handle)</div><div class='add'>+static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me &gt;= adev-&gt;sdma.num_instances) {</div><div class='add'>+		dev_err(adev-&gt;dev, "sdma instance not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	amdgpu_amdkfd_suspend(adev, true);</div><div class='add'>+	r = amdgpu_sdma_reset_engine(adev, ring-&gt;me, true);</div><div class='add'>+	amdgpu_amdkfd_resume(adev, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u32 f32_cntl, freeze, cntl, stat1_reg;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int i, j, r = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	i = ring-&gt;me;</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	/* stop queue */</div><div class='add'>+	sdma_v5_0_gfx_stop(adev, 1 &lt;&lt; i);</div><div class='add'>+</div><div class='add'>+	/* engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */</div><div class='add'>+	freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));</div><div class='add'>+	freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);</div><div class='add'>+	WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='add'>+		freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));</div><div class='add'>+		if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) &amp; 1)</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* check sdma copy engine all idle if frozen not received*/</div><div class='add'>+	if (j == adev-&gt;usec_timeout) {</div><div class='add'>+		stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));</div><div class='add'>+		if ((stat1_reg &amp; 0x3FF) != 0x3FF) {</div><div class='add'>+			DRM_ERROR("cannot soft reset as sdma not idle\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+			goto err0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));</div><div class='add'>+	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);</div><div class='add'>+	WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);</div><div class='add'>+</div><div class='add'>+	cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));</div><div class='add'>+	cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);</div><div class='add'>+	WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);</div><div class='add'>+err0:</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 inst_id = ring-&gt;me;</div><div class='add'>+	u32 freeze;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+	/* unfreeze*/</div><div class='add'>+	freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));</div><div class='add'>+	freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);</div><div class='add'>+	WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);</div><div class='add'>+</div><div class='add'>+	r = sdma_v5_0_gfx_resume_instance(adev, inst_id, true);</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r = 0;</div><div class='hunk'>@@ -1668,10 +1829,10 @@ static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1692,15 +1853,15 @@ static int sdma_v5_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_0_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void sdma_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1717,10 +1878,51 @@ static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_SDMA_LS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct amd_ip_funcs sdma_v5_0_ip_funcs = {</div><div class='add'>+static void sdma_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;sdma.num_instances);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance:%d\n", i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_0[j].reg_name,</div><div class='add'>+				   adev-&gt;sdma.ip_dump[instance_offset + j]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			adev-&gt;sdma.ip_dump[instance_offset + j] =</div><div class='add'>+				RREG32(sdma_v5_0_get_reg_offset(adev, i,</div><div class='add'>+				       sdma_reg_list_5_0[j].reg_offset));</div><div class='add'>+	}</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs sdma_v5_0_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v5_0",</div><div class='ctx'> 	.early_init = sdma_v5_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = sdma_v5_0_sw_init,</div><div class='ctx'> 	.sw_fini = sdma_v5_0_sw_fini,</div><div class='ctx'> 	.hw_init = sdma_v5_0_hw_init,</div><div class='hunk'>@@ -1733,6 +1935,8 @@ const struct amd_ip_funcs sdma_v5_0_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = sdma_v5_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = sdma_v5_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = sdma_v5_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = sdma_v5_0_dump_ip_state,</div><div class='add'>+	.print_ip_state = sdma_v5_0_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {</div><div class='hunk'>@@ -1769,6 +1973,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {</div><div class='ctx'> 	.emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,</div><div class='ctx'> 	.init_cond_exec = sdma_v5_0_ring_init_cond_exec,</div><div class='ctx'> 	.preempt_ib = sdma_v5_0_ring_preempt_ib,</div><div class='add'>+	.reset = sdma_v5_0_reset_queue,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1805,7 +2010,7 @@ static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: if a secure copy should be used</div><div class='add'>+ * @copy_flags: copy flags for the buffers</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine (NAVI10).</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1815,11 +2020,11 @@ static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='del'>-		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags &amp; AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src_offset);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h<br/>index d4e3c2e696f6..2ab71f21755a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h</a></div><div class='hunk'>@@ -24,7 +24,6 @@</div><div class='ctx'> #ifndef __SDMA_V5_0_H__</div><div class='ctx'> #define __SDMA_V5_0_H__</div><div class='ctx'> </div><div class='del'>-extern const struct amd_ip_funcs sdma_v5_0_ip_funcs;</div><div class='ctx'> extern const struct amdgpu_ip_block_version sdma_v5_0_ip_block;</div><div class='ctx'> </div><div class='ctx'> #endif /* __SDMA_V5_0_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br/>index 42f4bd250def..51101b0aa2fa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c</a></div><div class='hunk'>@@ -60,10 +60,61 @@ MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");</div><div class='ctx'> #define SDMA0_HYP_DEC_REG_END 0x5893</div><div class='ctx'> #define SDMA1_HYP_DEC_REG_OFFSET 0x20</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring);</div><div class='add'>+static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)</div><div class='ctx'> {</div><div class='hunk'>@@ -176,6 +227,16 @@ static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",</div><div class='ctx'> 				ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='ctx'> 		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='add'>+		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) {</div><div class='add'>+			/* SDMA seems to miss doorbells sometimes when powergating kicks in.</div><div class='add'>+			 * Updating the wptr directly will wake it. This is only safe because</div><div class='add'>+			 * we disallow gfxoff in begin_use() and then allow it again in end_use().</div><div class='add'>+			 */</div><div class='add'>+			WREG32(sdma_v5_2_get_reg_offset(adev, ring-&gt;me, mmSDMA0_GFX_RB_WPTR),</div><div class='add'>+			       lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+			WREG32(sdma_v5_2_get_reg_offset(adev, ring-&gt;me, mmSDMA0_GFX_RB_WPTR_HI),</div><div class='add'>+			       upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		DRM_DEBUG("Not using doorbell -- "</div><div class='ctx'> 				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "</div><div class='hunk'>@@ -280,17 +341,21 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='ctx'> 	u32 ref_and_mask = 0;</div><div class='ctx'> 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev-&gt;nbio.hdp_flush_reg;</div><div class='ctx'> </div><div class='del'>-	ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_sdma0 &lt;&lt; ring-&gt;me;</div><div class='del'>-</div><div class='del'>-	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |</div><div class='del'>-			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |</div><div class='del'>-			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */</div><div class='del'>-	amdgpu_ring_write(ring, (adev-&gt;nbio.funcs-&gt;get_hdp_flush_done_offset(adev)) &lt;&lt; 2);</div><div class='del'>-	amdgpu_ring_write(ring, (adev-&gt;nbio.funcs-&gt;get_hdp_flush_req_offset(adev)) &lt;&lt; 2);</div><div class='del'>-	amdgpu_ring_write(ring, ref_and_mask); /* reference */</div><div class='del'>-	amdgpu_ring_write(ring, ref_and_mask); /* mask */</div><div class='del'>-	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |</div><div class='del'>-			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */</div><div class='add'>+	if (ring-&gt;me &gt; 1) {</div><div class='add'>+		amdgpu_hdp_flush(adev, ring);</div><div class='add'>+	} else {</div><div class='add'>+		ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_sdma0 &lt;&lt; ring-&gt;me;</div><div class='add'>+</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |</div><div class='add'>+				  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |</div><div class='add'>+				  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */</div><div class='add'>+		amdgpu_ring_write(ring, (adev-&gt;nbio.funcs-&gt;get_hdp_flush_done_offset(adev)) &lt;&lt; 2);</div><div class='add'>+		amdgpu_ring_write(ring, (adev-&gt;nbio.funcs-&gt;get_hdp_flush_req_offset(adev)) &lt;&lt; 2);</div><div class='add'>+		amdgpu_ring_write(ring, ref_and_mask); /* reference */</div><div class='add'>+		amdgpu_ring_write(ring, ref_and_mask); /* mask */</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |</div><div class='add'>+				  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -331,11 +396,9 @@ static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if ((flags &amp; AMDGPU_FENCE_FLAG_INT)) {</div><div class='del'>-		uint32_t ctx = ring-&gt;is_mes_queue ?</div><div class='del'>-			(ring-&gt;hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;</div><div class='ctx'> 		/* generate an interrupt */</div><div class='ctx'> 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));</div><div class='del'>-		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -344,15 +407,15 @@ static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se</div><div class='ctx'>  * sdma_v5_2_gfx_stop - stop the gfx async dma engines</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='del'>- *</div><div class='add'>+ * @inst_mask: mask of dma engine instances to be disabled</div><div class='ctx'>  * Stop the gfx async dma ring buffers.</div><div class='ctx'>  */</div><div class='del'>-static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)</div><div class='add'>+static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev,  uint32_t inst_mask)</div><div class='ctx'> {</div><div class='ctx'> 	u32 rb_cntl, ib_cntl;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+	for_each_inst(i, inst_mask) {</div><div class='ctx'> 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));</div><div class='ctx'> 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='hunk'>@@ -443,9 +506,11 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 f32_cntl;</div><div class='ctx'> 	int i;</div><div class='add'>+	uint32_t inst_mask;</div><div class='ctx'> </div><div class='add'>+	inst_mask = GENMASK(adev-&gt;sdma.num_instances - 1, 0);</div><div class='ctx'> 	if (!enable) {</div><div class='del'>-		sdma_v5_2_gfx_stop(adev);</div><div class='add'>+		sdma_v5_2_gfx_stop(adev, inst_mask);</div><div class='ctx'> 		sdma_v5_2_rlc_stop(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -459,14 +524,17 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * sdma_v5_2_gfx_resume - setup and start the async dma engines</div><div class='add'>+ * sdma_v5_2_gfx_resume_instance - start/restart a certain sdma engine</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='add'>+ * @i: instance</div><div class='add'>+ * @restore: used to restore wptr when restart</div><div class='ctx'>  *</div><div class='del'>- * Set up the gfx DMA ring buffers and enable them.</div><div class='del'>- * Returns 0 for success, error for failure.</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.</div><div class='add'>+ * Return 0 for success.</div><div class='ctx'>  */</div><div class='del'>-static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+</div><div class='add'>+static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	u32 rb_cntl, ib_cntl;</div><div class='hunk'>@@ -476,139 +544,161 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 temp;</div><div class='ctx'> 	u32 wptr_poll_cntl;</div><div class='ctx'> 	u64 wptr_gpu_addr;</div><div class='del'>-	int i, r;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+	ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev))</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);</div><div class='ctx'> </div><div class='del'>-		/* Set ring buffer size in dwords */</div><div class='del'>-		rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='del'>-		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='add'>+	/* Set ring buffer size in dwords */</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='add'>+	rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,</div><div class='del'>-					RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,</div><div class='add'>+				RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='ctx'> #endif</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='del'>-</div><div class='del'>-		/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='add'>+</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	if (restore) {</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	} else {</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* setup the wptr shadow polling */</div><div class='del'>-		wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),</div><div class='del'>-		       lower_32_bits(wptr_gpu_addr));</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),</div><div class='del'>-		       upper_32_bits(wptr_gpu_addr));</div><div class='del'>-		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,</div><div class='del'>-							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));</div><div class='del'>-		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,</div><div class='del'>-					       SDMA0_GFX_RB_WPTR_POLL_CNTL,</div><div class='del'>-					       F32_POLL_ENABLE, 1);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),</div><div class='del'>-		       wptr_poll_cntl);</div><div class='del'>-</div><div class='del'>-		/* set the wb address whether it's enabled or not */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),</div><div class='del'>-		       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),</div><div class='del'>-		       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='del'>-</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='del'>-</div><div class='add'>+	/* setup the wptr shadow polling */</div><div class='add'>+	wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	       lower_32_bits(wptr_gpu_addr));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	       upper_32_bits(wptr_gpu_addr));</div><div class='add'>+	wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,</div><div class='add'>+						 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));</div><div class='add'>+	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,</div><div class='add'>+				       SDMA0_GFX_RB_WPTR_POLL_CNTL,</div><div class='add'>+				       F32_POLL_ENABLE, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),</div><div class='add'>+	       wptr_poll_cntl);</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),</div><div class='add'>+	       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),</div><div class='add'>+	       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='add'>+</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='add'>+</div><div class='add'>+	if (!restore)</div><div class='ctx'> 		ring-&gt;wptr = 0;</div><div class='ctx'> </div><div class='del'>-		/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);</div><div class='add'>+	/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='del'>-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='del'>-		}</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='add'>+		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));</div><div class='del'>-		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));</div><div class='add'>+	doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));</div><div class='add'>+	doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));</div><div class='ctx'> </div><div class='del'>-		if (ring-&gt;use_doorbell) {</div><div class='del'>-			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);</div><div class='del'>-			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,</div><div class='del'>-					OFFSET, ring-&gt;doorbell_index);</div><div class='del'>-		} else {</div><div class='del'>-			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);</div><div class='add'>+		doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,</div><div class='add'>+				OFFSET, ring-&gt;doorbell_index);</div><div class='add'>+	} else {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);</div><div class='ctx'> </div><div class='del'>-		adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='del'>-						      ring-&gt;doorbell_index,</div><div class='del'>-						      adev-&gt;doorbell_index.sdma_doorbell_range);</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='add'>+					      ring-&gt;doorbell_index,</div><div class='add'>+					      adev-&gt;doorbell_index.sdma_doorbell_range);</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_sriov_vf(adev))</div><div class='del'>-			sdma_v5_2_ring_set_wptr(ring);</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		sdma_v5_2_ring_set_wptr(ring);</div><div class='ctx'> </div><div class='del'>-		/* set minor_ptr_update to 0 after wptr programed */</div><div class='add'>+	/* set minor_ptr_update to 0 after wptr programed */</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);</div><div class='ctx'> </div><div class='del'>-		/* SRIOV VF has no control of any of registers below */</div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-			/* set utc l1 enable flag always to 1 */</div><div class='del'>-			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);</div><div class='del'>-</div><div class='del'>-			/* enable MCBP */</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);</div><div class='del'>-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);</div><div class='del'>-</div><div class='del'>-			/* Set up RESP_MODE to non-copy addresses */</div><div class='del'>-			temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);</div><div class='del'>-</div><div class='del'>-			/* program default cache read and write policy */</div><div class='del'>-			temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));</div><div class='del'>-			/* clean read policy and write policy bits */</div><div class='del'>-			temp &amp;= 0xFF0FFF;</div><div class='del'>-			temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) |</div><div class='del'>-				 (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14) |</div><div class='del'>-				 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);</div><div class='del'>-</div><div class='del'>-			/* unhalt engine */</div><div class='del'>-			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);</div><div class='del'>-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);</div><div class='del'>-		}</div><div class='add'>+	/* SRIOV VF has no control of any of registers below */</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* set utc l1 enable flag always to 1 */</div><div class='add'>+		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+		/* enable MCBP */</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);</div><div class='add'>+		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);</div><div class='add'>+</div><div class='add'>+		/* Set up RESP_MODE to non-copy addresses */</div><div class='add'>+		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);</div><div class='add'>+</div><div class='add'>+		/* program default cache read and write policy */</div><div class='add'>+		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));</div><div class='add'>+		/* clean read policy and write policy bits */</div><div class='add'>+		temp &amp;= 0xFF0FFF;</div><div class='add'>+		temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) |</div><div class='add'>+			 (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14) |</div><div class='add'>+			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);</div><div class='add'>+</div><div class='add'>+		/* unhalt engine */</div><div class='add'>+		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);</div><div class='add'>+		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* enable DMA RB */</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='add'>+	/* enable DMA RB */</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);</div><div class='ctx'> </div><div class='del'>-		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));</div><div class='del'>-		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);</div><div class='add'>+	ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='ctx'> #endif</div><div class='del'>-		/* enable DMA IBs */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);</div><div class='add'>+	/* enable DMA IBs */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */</div><div class='del'>-			sdma_v5_2_ctx_switch_enable(adev, true);</div><div class='del'>-			sdma_v5_2_enable(adev, true);</div><div class='del'>-		}</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */</div><div class='add'>+		sdma_v5_2_ctx_switch_enable(adev, true);</div><div class='add'>+		sdma_v5_2_enable(adev, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_test_helper(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v5_2_gfx_resume - setup and start the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them.</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ring_test_helper(ring);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		r = sdma_v5_2_gfx_resume_instance(adev, i, false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -673,37 +763,49 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_soft_reset(void *handle)</div><div class='add'>+static int sdma_v5_2_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	u32 grbm_soft_reset;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='del'>-		grbm_soft_reset = REG_SET_FIELD(0,</div><div class='del'>-						GRBM_SOFT_RESET, SOFT_RESET_SDMA0,</div><div class='del'>-						1);</div><div class='del'>-		grbm_soft_reset &lt;&lt;= i;</div><div class='add'>+	grbm_soft_reset = REG_SET_FIELD(0,</div><div class='add'>+					GRBM_SOFT_RESET, SOFT_RESET_SDMA0,</div><div class='add'>+					1);</div><div class='add'>+	grbm_soft_reset &lt;&lt;= instance_id;</div><div class='ctx'> </div><div class='del'>-		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='del'>-		tmp |= grbm_soft_reset;</div><div class='del'>-		DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+	tmp |= grbm_soft_reset;</div><div class='add'>+	DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+	WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='del'>-		udelay(50);</div><div class='add'>+	udelay(50);</div><div class='ctx'> </div><div class='del'>-		tmp &amp;= ~grbm_soft_reset;</div><div class='del'>-		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~grbm_soft_reset;</div><div class='add'>+	WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		sdma_v5_2_soft_reset_engine(adev, i);</div><div class='ctx'> 		udelay(50);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_sdma_funcs sdma_v5_2_sdma_funcs = {</div><div class='add'>+	.stop_kernel_queue = &amp;sdma_v5_2_stop_queue,</div><div class='add'>+	.start_kernel_queue = &amp;sdma_v5_2_restore_queue,</div><div class='add'>+	.soft_reset_kernel_queue = &amp;sdma_v5_2_soft_reset_engine,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * sdma_v5_2_start - setup and start the async dma engines</div><div class='ctx'>  *</div><div class='hunk'>@@ -715,6 +817,7 @@ static int sdma_v5_2_soft_reset(void *handle)</div><div class='ctx'> static int sdma_v5_2_start(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int r = 0;</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		sdma_v5_2_ctx_switch_enable(adev, false);</div><div class='hunk'>@@ -735,7 +838,11 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)</div><div class='ctx'> 			msleep(1000);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sdma_v5_2_soft_reset(adev);</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	sdma_v5_2_soft_reset(ip_block);</div><div class='ctx'> 	/* unhalt the MEs */</div><div class='ctx'> 	sdma_v5_2_enable(adev, true);</div><div class='ctx'> 	/* enable sdma ring preemption */</div><div class='hunk'>@@ -810,28 +917,18 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	int r;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	u64 gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	tmp = 0xCAFEDEAD;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		*cpu_ptr = tmp;</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, 20);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring-&gt;idx, r);</div><div class='hunk'>@@ -848,10 +945,7 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (ring-&gt;is_mes_queue)</div><div class='del'>-			tmp = le32_to_cpu(*cpu_ptr);</div><div class='del'>-		else</div><div class='del'>-			tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='ctx'> 		if (tmp == 0xDEADBEEF)</div><div class='ctx'> 			break;</div><div class='ctx'> 		if (amdgpu_emu_mode == 1)</div><div class='hunk'>@@ -863,8 +957,7 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	if (i &gt;= adev-&gt;usec_timeout)</div><div class='ctx'> 		r = -ETIMEDOUT;</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -887,37 +980,23 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	long r;</div><div class='ctx'> 	u32 tmp = 0;</div><div class='ctx'> 	u64 gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	tmp = 0xCAFEDEAD;</div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);</div><div class='del'>-		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		*cpu_ptr = tmp;</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='del'>-			goto err0;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |</div><div class='hunk'>@@ -945,10 +1024,7 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		goto err1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		tmp = le32_to_cpu(*cpu_ptr);</div><div class='del'>-	else</div><div class='del'>-		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+	tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp == 0xDEADBEEF)</div><div class='ctx'> 		r = 0;</div><div class='hunk'>@@ -956,11 +1032,10 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1116,7 +1191,28 @@ static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)</div><div class='ctx'> static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> 					 unsigned vmid, uint64_t pd_addr)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;ring-&gt;adev-&gt;vmhub[ring-&gt;vm_hub];</div><div class='add'>+	uint32_t req = hub-&gt;vmhub_funcs-&gt;get_invalidate_req(vmid, 0);</div><div class='add'>+</div><div class='add'>+	/* Update the PD address for this VMID. */</div><div class='add'>+	amdgpu_ring_emit_wreg(ring, hub-&gt;ctx0_ptb_addr_lo32 +</div><div class='add'>+			      (hub-&gt;ctx_addr_distance * vmid),</div><div class='add'>+			      lower_32_bits(pd_addr));</div><div class='add'>+	amdgpu_ring_emit_wreg(ring, hub-&gt;ctx0_ptb_addr_hi32 +</div><div class='add'>+			      (hub-&gt;ctx_addr_distance * vmid),</div><div class='add'>+			      upper_32_bits(pd_addr));</div><div class='add'>+</div><div class='add'>+	/* Trigger invalidation. */</div><div class='add'>+	amdgpu_ring_write(ring,</div><div class='add'>+			  SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |</div><div class='add'>+			  SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |</div><div class='add'>+			  SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring-&gt;vm_inv_eng) |</div><div class='add'>+			  SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));</div><div class='add'>+	amdgpu_ring_write(ring, req);</div><div class='add'>+	amdgpu_ring_write(ring, 0xFFFFFFFF);</div><div class='add'>+	amdgpu_ring_write(ring,</div><div class='add'>+			  SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 &lt;&lt; vmid) |</div><div class='add'>+			  SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='hunk'>@@ -1152,9 +1248,9 @@ static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_early_init(void *handle)</div><div class='add'>+static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_sdma_init_microcode(adev, 0, true);</div><div class='hunk'>@@ -1204,11 +1300,13 @@ static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_sw_init(void *handle)</div><div class='add'>+static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);</div><div class='add'>+	uint32_t *ptr;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1220,6 +1318,8 @@ static int sdma_v5_2_sw_init(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		mutex_init(&amp;adev-&gt;sdma.instance[i].engine_reset_mutex);</div><div class='add'>+		adev-&gt;sdma.instance[i].funcs = &amp;sdma_v5_2_sdma_funcs;</div><div class='ctx'> 		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> 		ring-&gt;ring_obj = NULL;</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='hunk'>@@ -1240,32 +1340,68 @@ static int sdma_v5_2_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;sdma.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;sdma.instance[0].ring);</div><div class='add'>+	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(5, 2, 0):</div><div class='add'>+	case IP_VERSION(5, 2, 2):</div><div class='add'>+	case IP_VERSION(5, 2, 3):</div><div class='add'>+	case IP_VERSION(5, 2, 4):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 76) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+			adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(5, 2, 5):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 34) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+			adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for SDMA IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (ptr)</div><div class='add'>+		adev-&gt;sdma.ip_dump = ptr;</div><div class='add'>+	else</div><div class='add'>+		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");</div><div class='add'>+</div><div class='add'>+	r = amdgpu_sdma_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_sw_fini(void *handle)</div><div class='add'>+static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;sdma.instance[i].ring);</div><div class='ctx'> </div><div class='add'>+	amdgpu_sdma_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	amdgpu_sdma_destroy_inst_ctx(adev, true);</div><div class='ctx'> </div><div class='add'>+	kfree(adev-&gt;sdma.ip_dump);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_hw_init(void *handle)</div><div class='add'>+static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return sdma_v5_2_start(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_hw_fini(void *handle)</div><div class='add'>+static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1276,23 +1412,19 @@ static int sdma_v5_2_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_suspend(void *handle)</div><div class='add'>+static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v5_2_hw_fini(adev);</div><div class='add'>+	return sdma_v5_2_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_resume(void *handle)</div><div class='add'>+static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v5_2_hw_init(adev);</div><div class='add'>+	return sdma_v5_2_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v5_2_is_idle(void *handle)</div><div class='add'>+static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1305,11 +1437,11 @@ static bool sdma_v5_2_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 sdma0, sdma1, sdma2, sdma3;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));</div><div class='hunk'>@@ -1324,6 +1456,100 @@ static int sdma_v5_2_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me &gt;= adev-&gt;sdma.num_instances) {</div><div class='add'>+		dev_err(adev-&gt;dev, "sdma instance not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	amdgpu_amdkfd_suspend(adev, true);</div><div class='add'>+	r = amdgpu_sdma_reset_engine(adev, ring-&gt;me, true);</div><div class='add'>+	amdgpu_amdkfd_resume(adev, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u32 f32_cntl, freeze, cntl, stat1_reg;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int i, j, r = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	i = ring-&gt;me;</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	/* stop queue */</div><div class='add'>+	sdma_v5_2_gfx_stop(adev, 1 &lt;&lt; i);</div><div class='add'>+</div><div class='add'>+	/*engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */</div><div class='add'>+	freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));</div><div class='add'>+	freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);</div><div class='add'>+	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='add'>+		freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));</div><div class='add'>+</div><div class='add'>+		if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) &amp; 1)</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (j == adev-&gt;usec_timeout) {</div><div class='add'>+		stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));</div><div class='add'>+		if ((stat1_reg &amp; 0x3FF) != 0x3FF) {</div><div class='add'>+			DRM_ERROR("cannot soft reset as sdma not idle\n");</div><div class='add'>+			r = -ETIMEDOUT;</div><div class='add'>+			goto err0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));</div><div class='add'>+	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);</div><div class='add'>+	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);</div><div class='add'>+</div><div class='add'>+	cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));</div><div class='add'>+	cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);</div><div class='add'>+	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);</div><div class='add'>+</div><div class='add'>+err0:</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 inst_id = ring-&gt;me;</div><div class='add'>+	u32 freeze;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+	/* unfreeze and unhalt */</div><div class='add'>+	freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));</div><div class='add'>+	freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);</div><div class='add'>+	WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);</div><div class='add'>+</div><div class='add'>+	r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true);</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r = 0;</div><div class='hunk'>@@ -1577,10 +1803,10 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1606,15 +1832,15 @@ static int sdma_v5_2_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v5_2_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void sdma_v5_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1642,6 +1868,10 @@ static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)</div><div class='ctx'> 	 * but it shouldn't hurt for other parts since</div><div class='ctx'> 	 * this GFXOFF will be disallowed anyway when SDMA is</div><div class='ctx'> 	 * active, this just makes it explicit.</div><div class='add'>+	 * sdma_v5_2_ring_set_wptr() takes advantage of this</div><div class='add'>+	 * to update the wptr because sometimes SDMA seems to miss</div><div class='add'>+	 * doorbells when entering PG.  If you remove this, update</div><div class='add'>+	 * sdma_v5_2_ring_set_wptr() as well!</div><div class='ctx'> 	 */</div><div class='ctx'> 	amdgpu_gfx_off_ctrl(adev, false);</div><div class='ctx'> }</div><div class='hunk'>@@ -1657,10 +1887,51 @@ static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_gfx_off_ctrl(adev, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct amd_ip_funcs sdma_v5_2_ip_funcs = {</div><div class='add'>+static void sdma_v5_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;sdma.num_instances);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance:%d\n", i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name,</div><div class='add'>+				   adev-&gt;sdma.ip_dump[instance_offset + j]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v5_2_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			adev-&gt;sdma.ip_dump[instance_offset + j] =</div><div class='add'>+				RREG32(sdma_v5_2_get_reg_offset(adev, i,</div><div class='add'>+				       sdma_reg_list_5_2[j].reg_offset));</div><div class='add'>+	}</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs sdma_v5_2_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v5_2",</div><div class='ctx'> 	.early_init = sdma_v5_2_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = sdma_v5_2_sw_init,</div><div class='ctx'> 	.sw_fini = sdma_v5_2_sw_fini,</div><div class='ctx'> 	.hw_init = sdma_v5_2_hw_init,</div><div class='hunk'>@@ -1673,6 +1944,8 @@ const struct amd_ip_funcs sdma_v5_2_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = sdma_v5_2_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = sdma_v5_2_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = sdma_v5_2_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = sdma_v5_2_dump_ip_state,</div><div class='add'>+	.print_ip_state = sdma_v5_2_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {</div><div class='hunk'>@@ -1711,6 +1984,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {</div><div class='ctx'> 	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,</div><div class='ctx'> 	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,</div><div class='ctx'> 	.preempt_ib = sdma_v5_2_ring_preempt_ib,</div><div class='add'>+	.reset = sdma_v5_2_reset_queue,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1747,7 +2021,7 @@ static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: if a secure copy should be used</div><div class='add'>+ * @copy_flags: copy flags for the buffers</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine.</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1757,11 +2031,11 @@ static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='del'>-		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags &amp; AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src_offset);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h<br/>index b70414fef2a1..863145b3a77e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.h</a></div><div class='hunk'>@@ -24,7 +24,6 @@</div><div class='ctx'> #ifndef __SDMA_V5_2_H__</div><div class='ctx'> #define __SDMA_V5_2_H__</div><div class='ctx'> </div><div class='del'>-extern const struct amd_ip_funcs sdma_v5_2_ip_funcs;</div><div class='ctx'> extern const struct amdgpu_ip_block_version sdma_v5_2_ip_block;</div><div class='ctx'> </div><div class='ctx'> #endif /* __SDMA_V5_2_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c<br/>index 361835a61f2e..217040044987 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c</a></div><div class='hunk'>@@ -43,6 +43,8 @@</div><div class='ctx'> #include "sdma_common.h"</div><div class='ctx'> #include "sdma_v6_0.h"</div><div class='ctx'> #include "v11_structs.h"</div><div class='add'>+#include "mes_userqueue.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");</div><div class='hunk'>@@ -50,12 +52,71 @@ MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin");</div><div class='ctx'> </div><div class='ctx'> #define SDMA1_REG_OFFSET 0x600</div><div class='ctx'> #define SDMA0_HYP_DEC_REG_START 0x5880</div><div class='ctx'> #define SDMA0_HYP_DEC_REG_END 0x589a</div><div class='ctx'> #define SDMA1_HYP_DEC_REG_OFFSET 0x20</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='hunk'>@@ -317,11 +378,9 @@ static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (flags &amp; AMDGPU_FENCE_FLAG_INT) {</div><div class='del'>-		uint32_t ctx = ring-&gt;is_mes_queue ?</div><div class='del'>-			(ring-&gt;hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;</div><div class='ctx'> 		/* generate an interrupt */</div><div class='ctx'> 		amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));</div><div class='del'>-		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -411,14 +470,16 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * sdma_v6_0_gfx_resume - setup and start the async dma engines</div><div class='add'>+ * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='add'>+ * @i: instance</div><div class='add'>+ * @restore: used to restore wptr when restart</div><div class='ctx'>  *</div><div class='del'>- * Set up the gfx DMA ring buffers and enable them.</div><div class='del'>- * Returns 0 for success, error for failure.</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.</div><div class='add'>+ * Return 0 for success.</div><div class='ctx'>  */</div><div class='del'>-static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	u32 rb_cntl, ib_cntl;</div><div class='hunk'>@@ -427,125 +488,152 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 doorbell_offset;</div><div class='ctx'> 	u32 temp;</div><div class='ctx'> 	u64 wptr_gpu_addr;</div><div class='del'>-	int i, r;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='del'>-		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev))</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);</div><div class='add'>+	ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);</div><div class='ctx'> </div><div class='del'>-		/* Set ring buffer size in dwords */</div><div class='del'>-		rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='del'>-		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='add'>+	/* Set ring buffer size in dwords */</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='add'>+	rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,</div><div class='del'>-					RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,</div><div class='add'>+				RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='ctx'> #endif</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='del'>-</div><div class='del'>-		/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='add'>+</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	if (restore) {</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	} else {</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);</div><div class='ctx'> 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);</div><div class='add'>+	}</div><div class='add'>+	/* setup the wptr shadow polling */</div><div class='add'>+	wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	       lower_32_bits(wptr_gpu_addr));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	       upper_32_bits(wptr_gpu_addr));</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),</div><div class='add'>+	       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),</div><div class='add'>+	       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='add'>+</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='add'>+</div><div class='add'>+	if (!restore)</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='ctx'> </div><div class='del'>-		/* setup the wptr shadow polling */</div><div class='del'>-		wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),</div><div class='del'>-		       lower_32_bits(wptr_gpu_addr));</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),</div><div class='del'>-		       upper_32_bits(wptr_gpu_addr));</div><div class='del'>-</div><div class='del'>-		/* set the wb address whether it's enabled or not */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),</div><div class='del'>-		       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),</div><div class='del'>-		       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='add'>+	/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);</div><div class='ctx'> </div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring-&gt;wptr) &lt;&lt; 2);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr) &lt;&lt; 2);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='add'>+	doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));</div><div class='add'>+	doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));</div><div class='ctx'> </div><div class='del'>-		ring-&gt;wptr = 0;</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);</div><div class='add'>+		doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,</div><div class='add'>+				OFFSET, ring-&gt;doorbell_index);</div><div class='add'>+	} else {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);</div><div class='ctx'> </div><div class='del'>-		/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);</div><div class='add'>+	if (i == 0)</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='add'>+					      ring-&gt;doorbell_index,</div><div class='add'>+					      adev-&gt;doorbell_index.sdma_doorbell_range * adev-&gt;sdma.num_instances);</div><div class='ctx'> </div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring-&gt;wptr) &lt;&lt; 2);</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr) &lt;&lt; 2);</div><div class='del'>-		}</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		sdma_v6_0_ring_set_wptr(ring);</div><div class='add'>+</div><div class='add'>+	/* set minor_ptr_update to 0 after wptr programed */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);</div><div class='add'>+</div><div class='add'>+	/* Set up sdma hang watchdog */</div><div class='add'>+	temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));</div><div class='add'>+	/* 100ms per unit */</div><div class='add'>+	temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,</div><div class='add'>+			     max(adev-&gt;usec_timeout/100000, 1));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);</div><div class='add'>+</div><div class='add'>+	/* Set up RESP_MODE to non-copy addresses */</div><div class='add'>+	temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));</div><div class='add'>+	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='add'>+	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);</div><div class='add'>+</div><div class='add'>+	/* program default cache read and write policy */</div><div class='add'>+	temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));</div><div class='add'>+	/* clean read policy and write policy bits */</div><div class='add'>+	temp &amp;= 0xFF0FFF;</div><div class='add'>+	temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) |</div><div class='add'>+		 (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14) |</div><div class='add'>+		 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);</div><div class='ctx'> </div><div class='del'>-		doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));</div><div class='del'>-		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* unhalt engine */</div><div class='add'>+		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (ring-&gt;use_doorbell) {</div><div class='del'>-			doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);</div><div class='del'>-			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,</div><div class='del'>-					OFFSET, ring-&gt;doorbell_index);</div><div class='del'>-		} else {</div><div class='del'>-			doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);</div><div class='del'>-</div><div class='del'>-		if (i == 0)</div><div class='del'>-			adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='del'>-						      ring-&gt;doorbell_index,</div><div class='del'>-						      adev-&gt;doorbell_index.sdma_doorbell_range * adev-&gt;sdma.num_instances);</div><div class='del'>-</div><div class='del'>-		if (amdgpu_sriov_vf(adev))</div><div class='del'>-			sdma_v6_0_ring_set_wptr(ring);</div><div class='del'>-</div><div class='del'>-		/* set minor_ptr_update to 0 after wptr programed */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);</div><div class='del'>-</div><div class='del'>-		/* Set up RESP_MODE to non-copy addresses */</div><div class='del'>-		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));</div><div class='del'>-		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='del'>-		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);</div><div class='del'>-</div><div class='del'>-		/* program default cache read and write policy */</div><div class='del'>-		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));</div><div class='del'>-		/* clean read policy and write policy bits */</div><div class='del'>-		temp &amp;= 0xFF0FFF;</div><div class='del'>-		temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) |</div><div class='del'>-			 (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14) |</div><div class='del'>-			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);</div><div class='del'>-</div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-			/* unhalt engine */</div><div class='del'>-			temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);</div><div class='del'>-			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);</div><div class='del'>-			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);</div><div class='del'>-		}</div><div class='add'>+	/* enable DMA RB */</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='ctx'> </div><div class='del'>-		/* enable DMA RB */</div><div class='del'>-		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='del'>-</div><div class='del'>-		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));</div><div class='del'>-		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);</div><div class='add'>+	ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='ctx'> #endif</div><div class='del'>-		/* enable DMA IBs */</div><div class='del'>-		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);</div><div class='add'>+	/* enable DMA IBs */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		sdma_v6_0_enable(adev, true);</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_sriov_vf(adev))</div><div class='del'>-			sdma_v6_0_enable(adev, true);</div><div class='add'>+	return amdgpu_ring_test_helper(ring);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ring_test_helper(ring);</div><div class='add'>+/**</div><div class='add'>+ * sdma_v6_0_gfx_resume - setup and start the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them.</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		r = sdma_v6_0_gfx_resume_instance(adev, i, false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -668,9 +756,9 @@ static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_soft_reset(void *handle)</div><div class='add'>+static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -704,9 +792,9 @@ static int sdma_v6_0_soft_reset(void *handle)</div><div class='ctx'> 	return sdma_v6_0_start(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v6_0_check_soft_reset(void *handle)</div><div class='add'>+static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> 	long tmo = msecs_to_jiffies(1000);</div><div class='hunk'>@@ -803,6 +891,12 @@ static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,</div><div class='ctx'> 	m-&gt;sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;</div><div class='ctx'> 	m-&gt;sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;</div><div class='ctx'> </div><div class='add'>+	m-&gt;sdmax_rlcx_csa_addr_lo = lower_32_bits(prop-&gt;csa_addr);</div><div class='add'>+	m-&gt;sdmax_rlcx_csa_addr_hi = upper_32_bits(prop-&gt;csa_addr);</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_f32_dbg0 = lower_32_bits(prop-&gt;fence_address);</div><div class='add'>+	m-&gt;sdmax_rlcx_f32_dbg1 = upper_32_bits(prop-&gt;fence_address);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -829,28 +923,18 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	int r;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> 	u64 gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	tmp = 0xCAFEDEAD;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		*cpu_ptr = tmp;</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, 5);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring-&gt;idx, r);</div><div class='hunk'>@@ -867,10 +951,7 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (ring-&gt;is_mes_queue)</div><div class='del'>-			tmp = le32_to_cpu(*cpu_ptr);</div><div class='del'>-		else</div><div class='del'>-			tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='ctx'> 		if (tmp == 0xDEADBEEF)</div><div class='ctx'> 			break;</div><div class='ctx'> 		if (amdgpu_emu_mode == 1)</div><div class='hunk'>@@ -882,8 +963,7 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	if (i &gt;= adev-&gt;usec_timeout)</div><div class='ctx'> 		r = -ETIMEDOUT;</div><div class='ctx'> </div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -906,37 +986,23 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	long r;</div><div class='ctx'> 	u32 tmp = 0;</div><div class='ctx'> 	u64 gpu_addr;</div><div class='del'>-	volatile uint32_t *cpu_ptr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	tmp = 0xCAFEDEAD;</div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue) {</div><div class='del'>-		uint32_t offset = 0;</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);</div><div class='del'>-		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-</div><div class='del'>-		offset = amdgpu_mes_ctx_get_offs(ring,</div><div class='del'>-					 AMDGPU_MES_CTX_PADDING_OFFS);</div><div class='del'>-		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);</div><div class='del'>-		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);</div><div class='del'>-		*cpu_ptr = tmp;</div><div class='del'>-	} else {</div><div class='del'>-		r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='del'>-		adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='del'>-			goto err0;</div><div class='del'>-		}</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |</div><div class='hunk'>@@ -964,10 +1030,7 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		goto err1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;is_mes_queue)</div><div class='del'>-		tmp = le32_to_cpu(*cpu_ptr);</div><div class='del'>-	else</div><div class='del'>-		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+	tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp == 0xDEADBEEF)</div><div class='ctx'> 		r = 0;</div><div class='hunk'>@@ -975,11 +1038,10 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='del'>-	if (!ring-&gt;is_mes_queue)</div><div class='del'>-		amdgpu_device_wb_free(adev, index);</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1206,11 +1268,28 @@ static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_early_init(void *handle)</div><div class='add'>+static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_user_queue) {</div><div class='add'>+	case -1:</div><div class='add'>+	case 0:</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;sdma.no_user_submission = false;</div><div class='add'>+		adev-&gt;sdma.disable_uq = true;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		adev-&gt;sdma.no_user_submission = false;</div><div class='add'>+		adev-&gt;sdma.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		adev-&gt;sdma.no_user_submission = true;</div><div class='add'>+		adev-&gt;sdma.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_sdma_init_microcode(adev, 0, true);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -1225,11 +1304,13 @@ static int sdma_v6_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_sw_init(void *handle)</div><div class='add'>+static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='ctx'> </div><div class='ctx'> 	/* SDMA trap event */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,</div><div class='hunk'>@@ -1238,11 +1319,19 @@ static int sdma_v6_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	/* SDMA user fence event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,</div><div class='add'>+			      GFX_11_0_0__SRCID__SDMA_FENCE,</div><div class='add'>+			      &amp;adev-&gt;sdma.fence_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='ctx'> 		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> 		ring-&gt;ring_obj = NULL;</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='ctx'> 		ring-&gt;me = i;</div><div class='add'>+		ring-&gt;no_user_submission = adev-&gt;sdma.no_user_submission;</div><div class='ctx'> </div><div class='ctx'> 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,</div><div class='ctx'> 				ring-&gt;use_doorbell?"true":"false");</div><div class='hunk'>@@ -1260,64 +1349,155 @@ static int sdma_v6_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;sdma.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;sdma.instance[0].ring);</div><div class='add'>+	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 0, 0):</div><div class='add'>+	case IP_VERSION(6, 0, 2):</div><div class='add'>+	case IP_VERSION(6, 0, 3):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 21) &amp;&amp;</div><div class='add'>+		    !amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+		    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+			adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sdma_ras_sw_init(adev)) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Failed to initialize sdma ras block!\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Allocate memory for SDMA IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (ptr)</div><div class='add'>+		adev-&gt;sdma.ip_dump = ptr;</div><div class='add'>+	else</div><div class='add'>+		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 0, 0):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 27) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 0, 1):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 18) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 0, 2):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 23) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 0, 3):</div><div class='add'>+		if (adev-&gt;sdma.instance[0].fw_version &gt;= 29 &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 1, 0):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 14) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 1, 1):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 17) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 1, 2):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 15) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(6, 1, 3):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 10) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_sdma_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_sw_fini(void *handle)</div><div class='add'>+static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='ctx'> 		amdgpu_ring_fini(&amp;adev-&gt;sdma.instance[i].ring);</div><div class='ctx'> </div><div class='add'>+	amdgpu_sdma_sysfs_reset_mask_fini(adev);</div><div class='ctx'> 	amdgpu_sdma_destroy_inst_ctx(adev, true);</div><div class='ctx'> </div><div class='add'>+	kfree(adev-&gt;sdma.ip_dump);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_hw_init(void *handle)</div><div class='add'>+static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev,</div><div class='add'>+					       bool enable)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	unsigned int irq_type;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='del'>-	return sdma_v6_0_start(adev);</div><div class='add'>+	if (adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA]) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+			irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;</div><div class='add'>+			if (enable)</div><div class='add'>+				r = amdgpu_irq_get(adev, &amp;adev-&gt;sdma.trap_irq,</div><div class='add'>+						   irq_type);</div><div class='add'>+			else</div><div class='add'>+				r = amdgpu_irq_put(adev, &amp;adev-&gt;sdma.trap_irq,</div><div class='add'>+						   irq_type);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = sdma_v6_0_start(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return sdma_v6_0_set_userq_trap_interrupts(adev, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_hw_fini(void *handle)</div><div class='add'>+static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	sdma_v6_0_ctxempty_int_enable(adev, false);</div><div class='ctx'> 	sdma_v6_0_enable(adev, false);</div><div class='add'>+	sdma_v6_0_set_userq_trap_interrupts(adev, false);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_suspend(void *handle)</div><div class='add'>+static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v6_0_hw_fini(adev);</div><div class='add'>+	return sdma_v6_0_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_resume(void *handle)</div><div class='add'>+static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return sdma_v6_0_hw_init(adev);</div><div class='add'>+	return sdma_v6_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool sdma_v6_0_is_idle(void *handle)</div><div class='add'>+static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -1330,11 +1510,11 @@ static bool sdma_v6_0_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_wait_for_idle(void *handle)</div><div class='add'>+static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 sdma0, sdma1;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));</div><div class='hunk'>@@ -1392,6 +1572,31 @@ static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me &gt;= adev-&gt;sdma.num_instances) {</div><div class='add'>+		dev_err(adev-&gt;dev, "sdma instance not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = sdma_v6_0_gfx_resume_instance(adev, ring-&gt;me, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 					struct amdgpu_irq_src *source,</div><div class='ctx'> 					unsigned type,</div><div class='hunk'>@@ -1416,25 +1621,9 @@ static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,</div><div class='ctx'> 				      struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='ctx'> 	int instances, queue;</div><div class='del'>-	uint32_t mes_queue_id = entry-&gt;src_data[0];</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG("IH: SDMA trap\n");</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;enable_mes &amp;&amp; (mes_queue_id &amp; AMDGPU_FENCE_MES_QUEUE_FLAG)) {</div><div class='del'>-		struct amdgpu_mes_queue *queue;</div><div class='del'>-</div><div class='del'>-		mes_queue_id &amp;= AMDGPU_FENCE_MES_QUEUE_ID_MASK;</div><div class='del'>-</div><div class='del'>-		spin_lock(&amp;adev-&gt;mes.queue_id_lock);</div><div class='del'>-		queue = idr_find(&amp;adev-&gt;mes.queue_id_idr, mes_queue_id);</div><div class='del'>-		if (queue) {</div><div class='del'>-			DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);</div><div class='del'>-			amdgpu_fence_process(queue-&gt;ring);</div><div class='del'>-		}</div><div class='del'>-		spin_unlock(&amp;adev-&gt;mes.queue_id_lock);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	queue = entry-&gt;ring_id &amp; 0xf;</div><div class='ctx'> 	instances = (entry-&gt;ring_id &amp; 0xf0) &gt;&gt; 4;</div><div class='ctx'> 	if (instances &gt; 1) {</div><div class='hunk'>@@ -1456,6 +1645,29 @@ static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev,</div><div class='add'>+				       struct amdgpu_irq_src *source,</div><div class='add'>+				       struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 doorbell_offset = entry-&gt;src_data[0];</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; doorbell_offset) {</div><div class='add'>+		struct amdgpu_userq_fence_driver *fence_drv = NULL;</div><div class='add'>+		struct xarray *xa = &amp;adev-&gt;userq_xa;</div><div class='add'>+		unsigned long flags;</div><div class='add'>+</div><div class='add'>+		doorbell_offset &gt;&gt;= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;</div><div class='add'>+</div><div class='add'>+		xa_lock_irqsave(xa, flags);</div><div class='add'>+		fence_drv = xa_load(xa, doorbell_offset);</div><div class='add'>+		if (fence_drv)</div><div class='add'>+			amdgpu_userq_fence_driver_process(fence_drv);</div><div class='add'>+		xa_unlock_irqrestore(xa, flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 					      struct amdgpu_irq_src *source,</div><div class='ctx'> 					      struct amdgpu_iv_entry *entry)</div><div class='hunk'>@@ -1463,26 +1675,67 @@ static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sdma_v6_0_set_powergating_state(void *handle,</div><div class='add'>+static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;sdma.num_instances);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance:%d\n", i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name,</div><div class='add'>+				   adev-&gt;sdma.ip_dump[instance_offset + j]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			adev-&gt;sdma.ip_dump[instance_offset + j] =</div><div class='add'>+				RREG32(sdma_v6_0_get_reg_offset(adev, i,</div><div class='add'>+				       sdma_reg_list_6_0[j].reg_offset));</div><div class='add'>+	}</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct amd_ip_funcs sdma_v6_0_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v6_0",</div><div class='ctx'> 	.early_init = sdma_v6_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = sdma_v6_0_sw_init,</div><div class='ctx'> 	.sw_fini = sdma_v6_0_sw_fini,</div><div class='ctx'> 	.hw_init = sdma_v6_0_hw_init,</div><div class='hunk'>@@ -1496,6 +1749,8 @@ const struct amd_ip_funcs sdma_v6_0_ip_funcs = {</div><div class='ctx'> 	.set_clockgating_state = sdma_v6_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = sdma_v6_0_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = sdma_v6_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = sdma_v6_0_dump_ip_state,</div><div class='add'>+	.print_ip_state = sdma_v6_0_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {</div><div class='hunk'>@@ -1531,6 +1786,7 @@ static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {</div><div class='ctx'> 	.emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,</div><div class='ctx'> 	.init_cond_exec = sdma_v6_0_ring_init_cond_exec,</div><div class='ctx'> 	.preempt_ib = sdma_v6_0_ring_preempt_ib,</div><div class='add'>+	.reset = sdma_v6_0_reset_queue,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1548,6 +1804,10 @@ static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {</div><div class='ctx'> 	.process = sdma_v6_0_process_trap_irq,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs sdma_v6_0_fence_irq_funcs = {</div><div class='add'>+	.process = sdma_v6_0_process_fence_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {</div><div class='ctx'> 	.process = sdma_v6_0_process_illegal_inst_irq,</div><div class='ctx'> };</div><div class='hunk'>@@ -1557,6 +1817,7 @@ static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +</div><div class='ctx'> 					adev-&gt;sdma.num_instances;</div><div class='ctx'> 	adev-&gt;sdma.trap_irq.funcs = &amp;sdma_v6_0_trap_irq_funcs;</div><div class='add'>+	adev-&gt;sdma.fence_irq.funcs = &amp;sdma_v6_0_fence_irq_funcs;</div><div class='ctx'> 	adev-&gt;sdma.illegal_inst_irq.funcs = &amp;sdma_v6_0_illegal_inst_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1567,7 +1828,7 @@ static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: if a secure copy should be used</div><div class='add'>+ * @copy_flags: copy flags for the buffers</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine.</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -1577,11 +1838,11 @@ static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |</div><div class='ctx'> 		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='del'>-		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags &amp; AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src_offset);</div><div class='hunk'>@@ -1605,7 +1866,7 @@ static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count)</div><div class='ctx'> {</div><div class='del'>-	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(dst_offset);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(dst_offset);</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = src_data;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h<br/>index 6af23e7888ca..d8cf830916b9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v6_0_0_pkt_open.h</a></div><div class='hunk'>@@ -91,6 +91,14 @@</div><div class='ctx'> #define SDMA_GCR_GLM_WB			(1 &lt;&lt; 4)</div><div class='ctx'> #define SDMA_GCR_GL1_RANGE(x)		(((x) &amp; 0x3) &lt;&lt; 2)</div><div class='ctx'> #define SDMA_GCR_GLI_INV(x)		(((x) &amp; 0x3) &lt;&lt; 0)</div><div class='add'>+</div><div class='add'>+#define SDMA_DCC_DATA_FORMAT(x) ((x) &amp; 0x3f)</div><div class='add'>+#define SDMA_DCC_NUM_TYPE(x) (((x) &amp; 0x7) &lt;&lt; 9)</div><div class='add'>+#define SDMA_DCC_READ_CM(x) (((x) &amp; 0x3) &lt;&lt; 16)</div><div class='add'>+#define SDMA_DCC_WRITE_CM(x) (((x) &amp; 0x3) &lt;&lt; 18)</div><div class='add'>+#define SDMA_DCC_MAX_COM(x) (((x) &amp; 0x3) &lt;&lt; 24)</div><div class='add'>+#define SDMA_DCC_MAX_UCOM(x) (((x) &amp; 0x1) &lt;&lt; 26)</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'> ** Definitions for SDMA_PKT_COPY_LINEAR packet</div><div class='ctx'> */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c<br/>new file mode 100644<br/>index 000000000000..2b81344dcd66<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c</a></div><div class='hunk'>@@ -0,0 +1,1859 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_ucode.h"</div><div class='add'>+#include "amdgpu_trace.h"</div><div class='add'>+</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "hdp/hdp_6_0_0_offset.h"</div><div class='add'>+#include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h"</div><div class='add'>+</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "soc15.h"</div><div class='add'>+#include "sdma_v6_0_0_pkt_open.h"</div><div class='add'>+#include "nbio_v4_3.h"</div><div class='add'>+#include "sdma_common.h"</div><div class='add'>+#include "sdma_v7_0.h"</div><div class='add'>+#include "v12_structs.h"</div><div class='add'>+#include "mes_userqueue.h"</div><div class='add'>+#include "amdgpu_userq_fence.h"</div><div class='add'>+</div><div class='add'>+MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin");</div><div class='add'>+</div><div class='add'>+#define SDMA1_REG_OFFSET 0x600</div><div class='add'>+#define SDMA0_HYP_DEC_REG_START 0x5880</div><div class='add'>+#define SDMA0_HYP_DEC_REG_END 0x589a</div><div class='add'>+#define SDMA1_HYP_DEC_REG_OFFSET 0x20</div><div class='add'>+</div><div class='add'>+/*define for compression field for sdma7*/</div><div class='add'>+#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_offset 0</div><div class='add'>+#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask   0x00000001</div><div class='add'>+#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift  16</div><div class='add'>+#define SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(x) (((x) &amp; SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask) &lt;&lt; SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift)</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int sdma_v7_0_start(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)</div><div class='add'>+{</div><div class='add'>+	u32 base;</div><div class='add'>+</div><div class='add'>+	if (internal_offset &gt;= SDMA0_HYP_DEC_REG_START &amp;&amp;</div><div class='add'>+	    internal_offset &lt;= SDMA0_HYP_DEC_REG_END) {</div><div class='add'>+		base = adev-&gt;reg_offset[GC_HWIP][0][1];</div><div class='add'>+		if (instance != 0)</div><div class='add'>+			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;</div><div class='add'>+	} else {</div><div class='add'>+		base = adev-&gt;reg_offset[GC_HWIP][0][0];</div><div class='add'>+		if (instance == 1)</div><div class='add'>+			internal_offset += SDMA1_REG_OFFSET;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return base + internal_offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring,</div><div class='add'>+					      uint64_t addr)</div><div class='add'>+{</div><div class='add'>+	unsigned ret;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, 1);</div><div class='add'>+	/* this is the offset we need patch later */</div><div class='add'>+	ret = ring-&gt;wptr &amp; ring-&gt;buf_mask;</div><div class='add'>+	/* insert dummy here and patch it later */</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_get_rptr - get the current read pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Get the current rptr from the hardware.</div><div class='add'>+ */</div><div class='add'>+static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u64 *rptr;</div><div class='add'>+</div><div class='add'>+	/* XXX check if swapping is necessary on BE */</div><div class='add'>+	rptr = (u64 *)ring-&gt;rptr_cpu_addr;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);</div><div class='add'>+	return ((*rptr) &gt;&gt; 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_get_wptr - get the current write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Get the current wptr from the hardware.</div><div class='add'>+ */</div><div class='add'>+static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u64 wptr = 0;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		/* XXX check if swapping is necessary on BE */</div><div class='add'>+		wptr = READ_ONCE(*((u64 *)ring-&gt;wptr_cpu_addr));</div><div class='add'>+		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return wptr &gt;&gt; 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_set_wptr - commit the write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Write the wptr back to the hardware.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG("Setting write pointer\n");</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		DRM_DEBUG("Using doorbell -- "</div><div class='add'>+			  "wptr_offs == 0x%08x "</div><div class='add'>+			  "lower_32_bits(ring-&gt;wptr) &lt;&lt; 2 == 0x%08x "</div><div class='add'>+			  "upper_32_bits(ring-&gt;wptr) &lt;&lt; 2 == 0x%08x\n",</div><div class='add'>+			  ring-&gt;wptr_offs,</div><div class='add'>+			  lower_32_bits(ring-&gt;wptr &lt;&lt; 2),</div><div class='add'>+			  upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		/* XXX check if swapping is necessary on BE */</div><div class='add'>+		atomic64_set((atomic64_t *)ring-&gt;wptr_cpu_addr,</div><div class='add'>+			     ring-&gt;wptr &lt;&lt; 2);</div><div class='add'>+		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",</div><div class='add'>+			  ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='add'>+		WDOORBELL64(ring-&gt;doorbell_index, ring-&gt;wptr &lt;&lt; 2);</div><div class='add'>+	} else {</div><div class='add'>+		DRM_DEBUG("Not using doorbell -- "</div><div class='add'>+			  "regSDMA%i_GFX_RB_WPTR == 0x%08x "</div><div class='add'>+			  "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",</div><div class='add'>+			  ring-&gt;me,</div><div class='add'>+			  lower_32_bits(ring-&gt;wptr &lt;&lt; 2),</div><div class='add'>+			  ring-&gt;me,</div><div class='add'>+			  upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,</div><div class='add'>+							     ring-&gt;me,</div><div class='add'>+							     regSDMA0_QUEUE0_RB_WPTR),</div><div class='add'>+				lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,</div><div class='add'>+							     ring-&gt;me,</div><div class='add'>+							     regSDMA0_QUEUE0_RB_WPTR_HI),</div><div class='add'>+				upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		if (sdma &amp;&amp; sdma-&gt;burst_nop &amp;&amp; (i == 0))</div><div class='add'>+			amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop |</div><div class='add'>+				SDMA_PKT_NOP_HEADER_COUNT(count - 1));</div><div class='add'>+		else</div><div class='add'>+			amdgpu_ring_write(ring, ring-&gt;funcs-&gt;nop);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ * @job: job to retrieve vmid from</div><div class='add'>+ * @ib: IB object to schedule</div><div class='add'>+ * @flags: unused</div><div class='add'>+ *</div><div class='add'>+ * Schedule an IB in the DMA ring.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='add'>+				   struct amdgpu_job *job,</div><div class='add'>+				   struct amdgpu_ib *ib,</div><div class='add'>+				   uint32_t flags)</div><div class='add'>+{</div><div class='add'>+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='add'>+	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);</div><div class='add'>+</div><div class='add'>+	/* An IB packet must end on a 8 DW boundary--the next dword</div><div class='add'>+	 * must be on a 8-dword boundary. Our IB packet below is 6</div><div class='add'>+	 * dwords long, thus add x number of NOPs, such that, in</div><div class='add'>+	 * modular arithmetic,</div><div class='add'>+	 * wptr + 6 + x = 8k, k &gt;= 0, which in C is,</div><div class='add'>+	 * (wptr + 6 + x) % 8 = 0.</div><div class='add'>+	 * The expression below, is a solution of x.</div><div class='add'>+	 */</div><div class='add'>+	sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring-&gt;wptr)) &amp; 7);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |</div><div class='add'>+			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid &amp; 0xf));</div><div class='add'>+	/* base must be 32 byte aligned */</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(ib-&gt;gpu_addr) &amp; 0xffffffe0);</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(ib-&gt;gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, ib-&gt;length_dw);</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * flush the IB by graphics cache rinse.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |</div><div class='add'>+		SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |</div><div class='add'>+		SDMA_GCR_GLI_INV(1);</div><div class='add'>+</div><div class='add'>+	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |</div><div class='add'>+			  SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |</div><div class='add'>+			  SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl &gt;&gt; 16));</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |</div><div class='add'>+			  SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Emit an hdp flush packet on the requested DMA ring.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 ref_and_mask = 0;</div><div class='add'>+	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev-&gt;nbio.hdp_flush_reg;</div><div class='add'>+</div><div class='add'>+	ref_and_mask = nbio_hf_reg-&gt;ref_and_mask_sdma0 &lt;&lt; ring-&gt;me;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */</div><div class='add'>+	amdgpu_ring_write(ring, (adev-&gt;nbio.funcs-&gt;get_hdp_flush_done_offset(adev)) &lt;&lt; 2);</div><div class='add'>+	amdgpu_ring_write(ring, (adev-&gt;nbio.funcs-&gt;get_hdp_flush_req_offset(adev)) &lt;&lt; 2);</div><div class='add'>+	amdgpu_ring_write(ring, ref_and_mask); /* reference */</div><div class='add'>+	amdgpu_ring_write(ring, ref_and_mask); /* mask */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ * @addr: address</div><div class='add'>+ * @seq: fence seq number</div><div class='add'>+ * @flags: fence flags</div><div class='add'>+ *</div><div class='add'>+ * Add a DMA fence packet to the ring to write</div><div class='add'>+ * the fence seq number and DMA trap packet to generate</div><div class='add'>+ * an interrupt if needed.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,</div><div class='add'>+				      unsigned flags)</div><div class='add'>+{</div><div class='add'>+	bool write64bit = flags &amp; AMDGPU_FENCE_FLAG_64BIT;</div><div class='add'>+	/* write the fence */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |</div><div class='add'>+			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */</div><div class='add'>+	/* zero in first two bits */</div><div class='add'>+	BUG_ON(addr &amp; 0x3);</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(seq));</div><div class='add'>+</div><div class='add'>+	/* optionally write high bits as well */</div><div class='add'>+	if (write64bit) {</div><div class='add'>+		addr += 4;</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |</div><div class='add'>+				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));</div><div class='add'>+		/* zero in first two bits */</div><div class='add'>+		BUG_ON(addr &amp; 0x3);</div><div class='add'>+		amdgpu_ring_write(ring, lower_32_bits(addr));</div><div class='add'>+		amdgpu_ring_write(ring, upper_32_bits(addr));</div><div class='add'>+		amdgpu_ring_write(ring, upper_32_bits(seq));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (flags &amp; AMDGPU_FENCE_FLAG_INT) {</div><div class='add'>+		/* generate an interrupt */</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));</div><div class='add'>+		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_gfx_stop - stop the gfx async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Stop the gfx async dma ring buffers.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 rb_cntl, ib_cntl;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));</div><div class='add'>+		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='add'>+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));</div><div class='add'>+		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_rlc_stop - stop the compute async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Stop the compute async dma queues.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* XXX todo */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @enable: enable/disable the DMA MEs context switch.</div><div class='add'>+ *</div><div class='add'>+ * Halt or unhalt the async dma engines context switch.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_enable - stop the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @enable: enable/disable the DMA MEs.</div><div class='add'>+ *</div><div class='add'>+ * Halt or unhalt the async dma engines.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 mcu_cntl;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!enable) {</div><div class='add'>+		sdma_v7_0_gfx_stop(adev);</div><div class='add'>+		sdma_v7_0_rlc_stop(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));</div><div class='add'>+		mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @i: instance</div><div class='add'>+ * @restore: used to restore wptr when restart</div><div class='add'>+ *</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.</div><div class='add'>+ * Return 0 for success.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	u32 rb_cntl, ib_cntl;</div><div class='add'>+	u32 rb_bufsz;</div><div class='add'>+	u32 doorbell;</div><div class='add'>+	u32 doorbell_offset;</div><div class='add'>+	u32 temp;</div><div class='add'>+	u64 wptr_gpu_addr;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+</div><div class='add'>+	/* Set ring buffer size in dwords */</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='add'>+	rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);</div><div class='add'>+#ifdef __BIG_ENDIAN</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,</div><div class='add'>+				RPTR_WRITEBACK_SWAP_ENABLE, 1);</div><div class='add'>+#endif</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='add'>+</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	if (restore) {</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr &lt;&lt; 2));</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);</div><div class='add'>+	}</div><div class='add'>+	/* setup the wptr shadow polling */</div><div class='add'>+	wptr_gpu_addr = ring-&gt;wptr_gpu_addr;</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),</div><div class='add'>+	       lower_32_bits(wptr_gpu_addr));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),</div><div class='add'>+	       upper_32_bits(wptr_gpu_addr));</div><div class='add'>+</div><div class='add'>+	/* set the wb address whether it's enabled or not */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),</div><div class='add'>+	       upper_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFF);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),</div><div class='add'>+	       lower_32_bits(ring-&gt;rptr_gpu_addr) &amp; 0xFFFFFFFC);</div><div class='add'>+</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);</div><div class='add'>+	else</div><div class='add'>+		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);</div><div class='add'>+</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring-&gt;gpu_addr &gt;&gt; 40);</div><div class='add'>+</div><div class='add'>+	if (!restore)</div><div class='add'>+		ring-&gt;wptr = 0;</div><div class='add'>+</div><div class='add'>+	/* before programing wptr to a less value, need set minor_ptr_update first */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring-&gt;wptr) &lt;&lt; 2);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring-&gt;wptr) &lt;&lt; 2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));</div><div class='add'>+	doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);</div><div class='add'>+		doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,</div><div class='add'>+				OFFSET, ring-&gt;doorbell_index);</div><div class='add'>+	} else {</div><div class='add'>+		doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);</div><div class='add'>+</div><div class='add'>+	if (i == 0)</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;sdma_doorbell_range(adev, i, ring-&gt;use_doorbell,</div><div class='add'>+					      ring-&gt;doorbell_index,</div><div class='add'>+					      adev-&gt;doorbell_index.sdma_doorbell_range * adev-&gt;sdma.num_instances);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		sdma_v7_0_ring_set_wptr(ring);</div><div class='add'>+</div><div class='add'>+	/* set minor_ptr_update to 0 after wptr programed */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);</div><div class='add'>+</div><div class='add'>+	/* Set up sdma hang watchdog */</div><div class='add'>+	temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));</div><div class='add'>+	/* 100ms per unit */</div><div class='add'>+	temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,</div><div class='add'>+			     max(adev-&gt;usec_timeout/100000, 1));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);</div><div class='add'>+</div><div class='add'>+	/* Set up RESP_MODE to non-copy addresses */</div><div class='add'>+	temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));</div><div class='add'>+	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);</div><div class='add'>+	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);</div><div class='add'>+</div><div class='add'>+	/* program default cache read and write policy */</div><div class='add'>+	temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));</div><div class='add'>+	/* clean read policy and write policy bits */</div><div class='add'>+	temp &amp;= 0xFF0FFF;</div><div class='add'>+	temp |= ((CACHE_READ_POLICY_L2__DEFAULT &lt;&lt; 12) |</div><div class='add'>+		 (CACHE_WRITE_POLICY_L2__DEFAULT &lt;&lt; 14));</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+		/* unhalt engine */</div><div class='add'>+		temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0);</div><div class='add'>+		temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* enable DMA RB */</div><div class='add'>+	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);</div><div class='add'>+</div><div class='add'>+	ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);</div><div class='add'>+#ifdef __BIG_ENDIAN</div><div class='add'>+	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);</div><div class='add'>+#endif</div><div class='add'>+	/* enable DMA IBs */</div><div class='add'>+	WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);</div><div class='add'>+	ring-&gt;sched.ready = true;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */</div><div class='add'>+		sdma_v7_0_ctx_switch_enable(adev, true);</div><div class='add'>+		sdma_v7_0_enable(adev, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ring_test_helper(ring);</div><div class='add'>+	if (r)</div><div class='add'>+		ring-&gt;sched.ready = false;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_gfx_resume - setup and start the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set up the gfx DMA ring buffers and enable them.</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		r = sdma_v7_0_gfx_resume_instance(adev, i, false);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_rlc_resume - setup and start the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set up the compute DMA queues and enable them.</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		amdgpu_bo_free_kernel(&amp;adev-&gt;sdma.instance[i].sdma_fw_obj,</div><div class='add'>+				      &amp;adev-&gt;sdma.instance[i].sdma_fw_gpu_addr,</div><div class='add'>+				      (void **)&amp;adev-&gt;sdma.instance[i].sdma_fw_ptr);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_load_microcode - load the sDMA ME ucode</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Loads the sDMA0/1 ucode.</div><div class='add'>+ * Returns 0 for success, -EINVAL if the ucode is not available.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_load_microcode(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct sdma_firmware_header_v3_0 *hdr;</div><div class='add'>+	const __le32 *fw_data;</div><div class='add'>+	u32 fw_size;</div><div class='add'>+	uint32_t tmp, sdma_status, ic_op_cntl;</div><div class='add'>+	int i, r, j;</div><div class='add'>+</div><div class='add'>+	/* halt the MEs */</div><div class='add'>+	sdma_v7_0_enable(adev, false);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.instance[0].fw)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct sdma_firmware_header_v3_0 *)</div><div class='add'>+		adev-&gt;sdma.instance[0].fw-&gt;data;</div><div class='add'>+	amdgpu_ucode_print_sdma_hdr(&amp;hdr-&gt;header);</div><div class='add'>+</div><div class='add'>+	fw_data = (const __le32 *)(adev-&gt;sdma.instance[0].fw-&gt;data +</div><div class='add'>+			le32_to_cpu(hdr-&gt;ucode_offset_bytes));</div><div class='add'>+	fw_size = le32_to_cpu(hdr-&gt;ucode_size_bytes);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		r = amdgpu_bo_create_reserved(adev, fw_size,</div><div class='add'>+					      PAGE_SIZE,</div><div class='add'>+					      AMDGPU_GEM_DOMAIN_VRAM,</div><div class='add'>+					      &amp;adev-&gt;sdma.instance[i].sdma_fw_obj,</div><div class='add'>+					      &amp;adev-&gt;sdma.instance[i].sdma_fw_gpu_addr,</div><div class='add'>+					      (void **)&amp;adev-&gt;sdma.instance[i].sdma_fw_ptr);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "(%d) failed to create sdma ucode bo\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		memcpy(adev-&gt;sdma.instance[i].sdma_fw_ptr, fw_data, fw_size);</div><div class='add'>+</div><div class='add'>+		amdgpu_bo_kunmap(adev-&gt;sdma.instance[i].sdma_fw_obj);</div><div class='add'>+		amdgpu_bo_unreserve(adev-&gt;sdma.instance[i].sdma_fw_obj);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL));</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO),</div><div class='add'>+			lower_32_bits(adev-&gt;sdma.instance[i].sdma_fw_gpu_addr));</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI),</div><div class='add'>+			upper_32_bits(adev-&gt;sdma.instance[i].sdma_fw_gpu_addr));</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1);</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);</div><div class='add'>+</div><div class='add'>+		/* Wait for sdma ucode init complete */</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='add'>+			ic_op_cntl = RREG32_SOC15_IP(GC,</div><div class='add'>+					sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));</div><div class='add'>+			sdma_status = RREG32_SOC15_IP(GC,</div><div class='add'>+					sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));</div><div class='add'>+			if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) &amp;&amp;</div><div class='add'>+			    (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1))</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (j &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to init sdma ucode\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	u32 tmp;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	sdma_v7_0_gfx_stop(adev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		//tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE));</div><div class='add'>+		//tmp |= SDMA0_FREEZE__FREEZE_MASK;</div><div class='add'>+		//WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);</div><div class='add'>+		tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));</div><div class='add'>+		tmp |= SDMA0_MCU_CNTL__HALT_MASK;</div><div class='add'>+		tmp |= SDMA0_MCU_CNTL__RESET_MASK;</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);</div><div class='add'>+</div><div class='add'>+		udelay(100);</div><div class='add'>+</div><div class='add'>+		tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK &lt;&lt; i;</div><div class='add'>+		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);</div><div class='add'>+</div><div class='add'>+		udelay(100);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);</div><div class='add'>+		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);</div><div class='add'>+</div><div class='add'>+		udelay(100);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return sdma_v7_0_start(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i, r;</div><div class='add'>+	long tmo = msecs_to_jiffies(1000);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+		r = amdgpu_ring_test_ib(ring, tmo);</div><div class='add'>+		if (r)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me &gt;= adev-&gt;sdma.num_instances) {</div><div class='add'>+		dev_err(adev-&gt;dev, "sdma instance not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = sdma_v7_0_gfx_resume_instance(adev, ring-&gt;me, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_start - setup and start the async dma engines</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set up the DMA engines and enable them.</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_start(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		sdma_v7_0_ctx_switch_enable(adev, false);</div><div class='add'>+		sdma_v7_0_enable(adev, false);</div><div class='add'>+</div><div class='add'>+		/* set RB registers */</div><div class='add'>+		r = sdma_v7_0_gfx_resume(adev);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {</div><div class='add'>+		r = sdma_v7_0_load_microcode(adev);</div><div class='add'>+		if (r) {</div><div class='add'>+			sdma_v12_0_free_ucode_buffer(adev);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode == 1)</div><div class='add'>+			msleep(1000);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* unhalt the MEs */</div><div class='add'>+	sdma_v7_0_enable(adev, true);</div><div class='add'>+	/* enable sdma ring preemption */</div><div class='add'>+	sdma_v7_0_ctx_switch_enable(adev, true);</div><div class='add'>+</div><div class='add'>+	/* start the gfx rings and rlc compute queues */</div><div class='add'>+	r = sdma_v7_0_gfx_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = sdma_v7_0_rlc_resume(adev);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd,</div><div class='add'>+			      struct amdgpu_mqd_prop *prop)</div><div class='add'>+{</div><div class='add'>+	struct v12_sdma_mqd *m = mqd;</div><div class='add'>+	uint64_t wb_gpu_addr;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_cntl =</div><div class='add'>+		order_base_2(prop-&gt;queue_size / 4) &lt;&lt; SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |</div><div class='add'>+		1 &lt;&lt; SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |</div><div class='add'>+		4 &lt;&lt; SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |</div><div class='add'>+		1 &lt;&lt; SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_base = lower_32_bits(prop-&gt;hqd_base_gpu_addr &gt;&gt; 8);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_base_hi = upper_32_bits(prop-&gt;hqd_base_gpu_addr &gt;&gt; 8);</div><div class='add'>+</div><div class='add'>+	wb_gpu_addr = prop-&gt;wptr_gpu_addr;</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);</div><div class='add'>+</div><div class='add'>+	wb_gpu_addr = prop-&gt;rptr_gpu_addr;</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0,</div><div class='add'>+							regSDMA0_QUEUE0_IB_CNTL));</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_doorbell_offset =</div><div class='add'>+		prop-&gt;doorbell_index &lt;&lt; SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_doorbell_log = 0;</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_aql_cntl = 0x4000;	//regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;</div><div class='add'>+	m-&gt;sdmax_rlcx_dummy_reg = 0xf;	//regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_csa_addr_lo = lower_32_bits(prop-&gt;csa_addr);</div><div class='add'>+	m-&gt;sdmax_rlcx_csa_addr_hi = upper_32_bits(prop-&gt;csa_addr);</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_mcu_dbg0 = lower_32_bits(prop-&gt;fence_address);</div><div class='add'>+	m-&gt;sdmax_rlcx_mcu_dbg1 = upper_32_bits(prop-&gt;fence_address);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd);</div><div class='add'>+	adev-&gt;mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_test_ring - simple async dma engine test</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring structure holding ring information</div><div class='add'>+ *</div><div class='add'>+ * Test the DMA engine by writing using it to write an</div><div class='add'>+ * value to memory.</div><div class='add'>+ * Returns 0 for success, error for failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	unsigned i;</div><div class='add'>+	unsigned index;</div><div class='add'>+	int r;</div><div class='add'>+	u32 tmp;</div><div class='add'>+	u64 gpu_addr;</div><div class='add'>+</div><div class='add'>+	tmp = 0xCAFEDEAD;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%d) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ring_alloc(ring, 5);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring-&gt;idx, r);</div><div class='add'>+		amdgpu_device_wb_free(adev, index);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |</div><div class='add'>+			  SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));</div><div class='add'>+	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));</div><div class='add'>+	amdgpu_ring_write(ring, 0xDEADBEEF);</div><div class='add'>+	amdgpu_ring_commit(ring);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+		if (tmp == 0xDEADBEEF)</div><div class='add'>+			break;</div><div class='add'>+		if (amdgpu_emu_mode == 1)</div><div class='add'>+			msleep(1);</div><div class='add'>+		else</div><div class='add'>+			udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_test_ib - test an IB on the DMA engine</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring structure holding ring information</div><div class='add'>+ * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT</div><div class='add'>+ *</div><div class='add'>+ * Test a simple IB in the DMA ring.</div><div class='add'>+ * Returns 0 on success, error on failure.</div><div class='add'>+ */</div><div class='add'>+static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_ib ib;</div><div class='add'>+	struct dma_fence *f = NULL;</div><div class='add'>+	unsigned index;</div><div class='add'>+	long r;</div><div class='add'>+	u32 tmp = 0;</div><div class='add'>+	u64 gpu_addr;</div><div class='add'>+</div><div class='add'>+	tmp = 0xCAFEDEAD;</div><div class='add'>+	memset(&amp;ib, 0, sizeof(ib));</div><div class='add'>+</div><div class='add'>+	r = amdgpu_device_wb_get(adev, &amp;index);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "(%ld) failed to allocate wb slot\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='add'>+	adev-&gt;wb.wb[index] = cpu_to_le32(tmp);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='add'>+		goto err0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);</div><div class='add'>+	ib.ptr[1] = lower_32_bits(gpu_addr);</div><div class='add'>+	ib.ptr[2] = upper_32_bits(gpu_addr);</div><div class='add'>+	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);</div><div class='add'>+	ib.ptr[4] = 0xDEADBEEF;</div><div class='add'>+	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);</div><div class='add'>+	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);</div><div class='add'>+	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);</div><div class='add'>+	ib.length_dw = 8;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_schedule(ring, 1, &amp;ib, NULL, &amp;f);</div><div class='add'>+	if (r)</div><div class='add'>+		goto err1;</div><div class='add'>+</div><div class='add'>+	r = dma_fence_wait_timeout(f, false, timeout);</div><div class='add'>+	if (r == 0) {</div><div class='add'>+		DRM_ERROR("amdgpu: IB test timed out\n");</div><div class='add'>+		r = -ETIMEDOUT;</div><div class='add'>+		goto err1;</div><div class='add'>+	} else if (r &lt; 0) {</div><div class='add'>+		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);</div><div class='add'>+		goto err1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tmp = le32_to_cpu(adev-&gt;wb.wb[index]);</div><div class='add'>+</div><div class='add'>+	if (tmp == 0xDEADBEEF)</div><div class='add'>+		r = 0;</div><div class='add'>+	else</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+</div><div class='add'>+err1:</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='add'>+	dma_fence_put(f);</div><div class='add'>+err0:</div><div class='add'>+	amdgpu_device_wb_free(adev, index);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART</div><div class='add'>+ *</div><div class='add'>+ * @ib: indirect buffer to fill with commands</div><div class='add'>+ * @pe: addr of the page entry</div><div class='add'>+ * @src: src addr to copy from</div><div class='add'>+ * @count: number of page entries to update</div><div class='add'>+ *</div><div class='add'>+ * Update PTEs by copying them from the GART using sDMA.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib,</div><div class='add'>+				  uint64_t pe, uint64_t src,</div><div class='add'>+				  unsigned count)</div><div class='add'>+{</div><div class='add'>+	unsigned bytes = count * 8;</div><div class='add'>+</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_CPV(1);</div><div class='add'>+</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = bytes - 1;</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(src);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(pe);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(pe);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = 0;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_vm_write_pte - update PTEs by writing them manually</div><div class='add'>+ *</div><div class='add'>+ * @ib: indirect buffer to fill with commands</div><div class='add'>+ * @pe: addr of the page entry</div><div class='add'>+ * @value: dst addr to write into pe</div><div class='add'>+ * @count: number of page entries to update</div><div class='add'>+ * @incr: increase next addr by incr bytes</div><div class='add'>+ *</div><div class='add'>+ * Update PTEs by writing them manually using sDMA.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,</div><div class='add'>+				   uint64_t value, unsigned count,</div><div class='add'>+				   uint32_t incr)</div><div class='add'>+{</div><div class='add'>+	unsigned ndw = count * 2;</div><div class='add'>+</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(pe);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(pe);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = ndw - 1;</div><div class='add'>+	for (; ndw &gt; 0; ndw -= 2) {</div><div class='add'>+		ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(value);</div><div class='add'>+		ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(value);</div><div class='add'>+		value += incr;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA</div><div class='add'>+ *</div><div class='add'>+ * @ib: indirect buffer to fill with commands</div><div class='add'>+ * @pe: addr of the page entry</div><div class='add'>+ * @addr: dst addr to write into pe</div><div class='add'>+ * @count: number of page entries to update</div><div class='add'>+ * @incr: increase next addr by incr bytes</div><div class='add'>+ * @flags: access flags</div><div class='add'>+ *</div><div class='add'>+ * Update the page tables using sDMA.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib,</div><div class='add'>+				     uint64_t pe,</div><div class='add'>+				     uint64_t addr, unsigned count,</div><div class='add'>+				     uint32_t incr, uint64_t flags)</div><div class='add'>+{</div><div class='add'>+	/* for physically contiguous pages (vram) */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(pe); /* dst addr */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(pe);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(flags); /* mask */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(flags);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(addr); /* value */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(addr);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = incr; /* increment size */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = 0;</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = count - 1; /* number of entries */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_pad_ib - pad the IB</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ * @ib: indirect buffer to fill with padding</div><div class='add'>+ *</div><div class='add'>+ * Pad the IB with NOPs to a boundary multiple of 8.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);</div><div class='add'>+	u32 pad_count;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	pad_count = (-ib-&gt;length_dw) &amp; 0x7;</div><div class='add'>+	for (i = 0; i &lt; pad_count; i++)</div><div class='add'>+		if (sdma &amp;&amp; sdma-&gt;burst_nop &amp;&amp; (i == 0))</div><div class='add'>+			ib-&gt;ptr[ib-&gt;length_dw++] =</div><div class='add'>+				SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |</div><div class='add'>+				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);</div><div class='add'>+		else</div><div class='add'>+			ib-&gt;ptr[ib-&gt;length_dw++] =</div><div class='add'>+				SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Make sure all previous operations are completed (CIK).</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	uint32_t seq = ring-&gt;fence_drv.sync_seq;</div><div class='add'>+	uint64_t addr = ring-&gt;fence_drv.gpu_addr;</div><div class='add'>+</div><div class='add'>+	/* wait for idle */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));</div><div class='add'>+	amdgpu_ring_write(ring, addr &amp; 0xfffffffc);</div><div class='add'>+	amdgpu_ring_write(ring, upper_32_bits(addr) &amp; 0xffffffff);</div><div class='add'>+	amdgpu_ring_write(ring, seq); /* reference */</div><div class='add'>+	amdgpu_ring_write(ring, 0xffffffff); /* mask */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ * @vmid: vmid number to use</div><div class='add'>+ * @pd_addr: address</div><div class='add'>+ *</div><div class='add'>+ * Update the page table base and flush the VM TLB</div><div class='add'>+ * using sDMA.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='add'>+					 unsigned vmid, uint64_t pd_addr)</div><div class='add'>+{</div><div class='add'>+	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='add'>+				     uint32_t reg, uint32_t val)</div><div class='add'>+{</div><div class='add'>+	/* SRBM WRITE command will not support on sdma v7.</div><div class='add'>+	 * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE));</div><div class='add'>+	amdgpu_ring_write(ring, reg &lt;&lt; 2);</div><div class='add'>+	amdgpu_ring_write(ring, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+					 uint32_t val, uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */</div><div class='add'>+	amdgpu_ring_write(ring, reg &lt;&lt; 2);</div><div class='add'>+	amdgpu_ring_write(ring, 0);</div><div class='add'>+	amdgpu_ring_write(ring, val); /* reference */</div><div class='add'>+	amdgpu_ring_write(ring, mask); /* mask */</div><div class='add'>+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |</div><div class='add'>+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,</div><div class='add'>+						   uint32_t reg0, uint32_t reg1,</div><div class='add'>+						   uint32_t ref, uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	amdgpu_ring_emit_wreg(ring, reg0, ref);</div><div class='add'>+	/* wait for a cycle to reset vm_inv_eng*_ack */</div><div class='add'>+	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);</div><div class='add'>+	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_user_queue) {</div><div class='add'>+	case -1:</div><div class='add'>+	case 0:</div><div class='add'>+	default:</div><div class='add'>+		adev-&gt;sdma.no_user_submission = false;</div><div class='add'>+		adev-&gt;sdma.disable_uq = true;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		adev-&gt;sdma.no_user_submission = false;</div><div class='add'>+		adev-&gt;sdma.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		adev-&gt;sdma.no_user_submission = true;</div><div class='add'>+		adev-&gt;sdma.disable_uq = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_sdma_init_microcode(adev, 0, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to init sdma firmware!\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sdma_v7_0_set_ring_funcs(adev);</div><div class='add'>+	sdma_v7_0_set_buffer_funcs(adev);</div><div class='add'>+	sdma_v7_0_set_vm_pte_funcs(adev);</div><div class='add'>+	sdma_v7_0_set_irq_funcs(adev);</div><div class='add'>+	sdma_v7_0_set_mqd_funcs(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int r, i;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='add'>+</div><div class='add'>+	/* SDMA trap event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,</div><div class='add'>+			      GFX_12_0_0__SRCID__SDMA_TRAP,</div><div class='add'>+			      &amp;adev-&gt;sdma.trap_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* SDMA user fence event */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,</div><div class='add'>+			      GFX_12_0_0__SRCID__SDMA_FENCE,</div><div class='add'>+			      &amp;adev-&gt;sdma.fence_irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='add'>+		ring-&gt;ring_obj = NULL;</div><div class='add'>+		ring-&gt;use_doorbell = true;</div><div class='add'>+		ring-&gt;me = i;</div><div class='add'>+		ring-&gt;no_user_submission = adev-&gt;sdma.no_user_submission;</div><div class='add'>+</div><div class='add'>+		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,</div><div class='add'>+				ring-&gt;use_doorbell?"true":"false");</div><div class='add'>+</div><div class='add'>+		ring-&gt;doorbell_index =</div><div class='add'>+			(adev-&gt;doorbell_index.sdma_engine[i] &lt;&lt; 1); // get DWORD offset</div><div class='add'>+</div><div class='add'>+		ring-&gt;vm_hub = AMDGPU_GFXHUB(0);</div><div class='add'>+		sprintf(ring-&gt;name, "sdma%d", i);</div><div class='add'>+		r = amdgpu_ring_init(adev, ring, 1024,</div><div class='add'>+				     &amp;adev-&gt;sdma.trap_irq,</div><div class='add'>+				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,</div><div class='add'>+				     AMDGPU_RING_PRIO_DEFAULT, NULL);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;sdma.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;sdma.instance[0].ring);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+	    !adev-&gt;debug_disable_gpu_ring_reset)</div><div class='add'>+		adev-&gt;sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_sdma_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	/* Allocate memory for SDMA IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (ptr)</div><div class='add'>+		adev-&gt;sdma.ip_dump = ptr;</div><div class='add'>+	else</div><div class='add'>+		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(7, 0, 0):</div><div class='add'>+	case IP_VERSION(7, 0, 1):</div><div class='add'>+		if ((adev-&gt;sdma.instance[0].fw_version &gt;= 7966358) &amp;&amp; !adev-&gt;sdma.disable_uq)</div><div class='add'>+			adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA] = &amp;userq_mes_funcs;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='add'>+		amdgpu_ring_fini(&amp;adev-&gt;sdma.instance[i].ring);</div><div class='add'>+</div><div class='add'>+	amdgpu_sdma_sysfs_reset_mask_fini(adev);</div><div class='add'>+	amdgpu_sdma_destroy_inst_ctx(adev, true);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_DIRECT)</div><div class='add'>+		sdma_v12_0_free_ucode_buffer(adev);</div><div class='add'>+</div><div class='add'>+	kfree(adev-&gt;sdma.ip_dump);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_set_userq_trap_interrupts(struct amdgpu_device *adev,</div><div class='add'>+					       bool enable)</div><div class='add'>+{</div><div class='add'>+	unsigned int irq_type;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;userq_funcs[AMDGPU_HW_IP_DMA]) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+			irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;</div><div class='add'>+			if (enable)</div><div class='add'>+				r = amdgpu_irq_get(adev, &amp;adev-&gt;sdma.trap_irq,</div><div class='add'>+						   irq_type);</div><div class='add'>+			else</div><div class='add'>+				r = amdgpu_irq_put(adev, &amp;adev-&gt;sdma.trap_irq,</div><div class='add'>+						   irq_type);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = sdma_v7_0_start(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return sdma_v7_0_set_userq_trap_interrupts(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	sdma_v7_0_ctx_switch_enable(adev, false);</div><div class='add'>+	sdma_v7_0_enable(adev, false);</div><div class='add'>+	sdma_v7_0_set_userq_trap_interrupts(adev, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return sdma_v7_0_hw_fini(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return sdma_v7_0_hw_init(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));</div><div class='add'>+</div><div class='add'>+		if (!(tmp &amp; SDMA0_STATUS_REG__IDLE_MASK))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	unsigned i;</div><div class='add'>+	u32 sdma0, sdma1;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));</div><div class='add'>+		sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));</div><div class='add'>+</div><div class='add'>+		if (sdma0 &amp; sdma1 &amp; SDMA0_STATUS_REG__IDLE_MASK)</div><div class='add'>+			return 0;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	int i, r = 0;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	u32 index = 0;</div><div class='add'>+	u64 sdma_gfx_preempt;</div><div class='add'>+</div><div class='add'>+	amdgpu_sdma_get_index_from_ring(ring, &amp;index);</div><div class='add'>+	sdma_gfx_preempt =</div><div class='add'>+		sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);</div><div class='add'>+</div><div class='add'>+	/* assert preemption condition */</div><div class='add'>+	amdgpu_ring_set_preempt_cond_exec(ring, false);</div><div class='add'>+</div><div class='add'>+	/* emit the trailing fence */</div><div class='add'>+	ring-&gt;trail_seq += 1;</div><div class='add'>+	r = amdgpu_ring_alloc(ring, 10);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("ring %d failed to be allocated \n", ring-&gt;idx);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	sdma_v7_0_ring_emit_fence(ring, ring-&gt;trail_fence_gpu_addr,</div><div class='add'>+				  ring-&gt;trail_seq, 0);</div><div class='add'>+	amdgpu_ring_commit(ring);</div><div class='add'>+</div><div class='add'>+	/* assert IB preemption */</div><div class='add'>+	WREG32(sdma_gfx_preempt, 1);</div><div class='add'>+</div><div class='add'>+	/* poll the trailing fence */</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		if (ring-&gt;trail_seq ==</div><div class='add'>+		    le32_to_cpu(*(ring-&gt;trail_fence_cpu_addr)))</div><div class='add'>+			break;</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout) {</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		DRM_ERROR("ring %d failed to be preempted\n", ring-&gt;idx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* deassert IB preemption */</div><div class='add'>+	WREG32(sdma_gfx_preempt, 0);</div><div class='add'>+</div><div class='add'>+	/* deassert the preemption condition */</div><div class='add'>+	amdgpu_ring_set_preempt_cond_exec(ring, true);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_irq_src *source,</div><div class='add'>+					unsigned type,</div><div class='add'>+					enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	u32 sdma_cntl;</div><div class='add'>+</div><div class='add'>+	u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);</div><div class='add'>+</div><div class='add'>+	sdma_cntl = RREG32(reg_offset);</div><div class='add'>+	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,</div><div class='add'>+		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);</div><div class='add'>+	WREG32(reg_offset, sdma_cntl);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev,</div><div class='add'>+				      struct amdgpu_irq_src *source,</div><div class='add'>+				      struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	int instances, queue;</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG("IH: SDMA trap\n");</div><div class='add'>+</div><div class='add'>+	queue = entry-&gt;ring_id &amp; 0xf;</div><div class='add'>+	instances = (entry-&gt;ring_id &amp; 0xf0) &gt;&gt; 4;</div><div class='add'>+	if (instances &gt; 1) {</div><div class='add'>+		DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (entry-&gt;client_id) {</div><div class='add'>+	case SOC21_IH_CLIENTID_GFX:</div><div class='add'>+		switch (queue) {</div><div class='add'>+		case 0:</div><div class='add'>+			amdgpu_fence_process(&amp;adev-&gt;sdma.instance[instances].ring);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev,</div><div class='add'>+				       struct amdgpu_irq_src *source,</div><div class='add'>+				       struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 doorbell_offset = entry-&gt;src_data[0];</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;enable_mes &amp;&amp; doorbell_offset) {</div><div class='add'>+		struct amdgpu_userq_fence_driver *fence_drv = NULL;</div><div class='add'>+		struct xarray *xa = &amp;adev-&gt;userq_xa;</div><div class='add'>+		unsigned long flags;</div><div class='add'>+</div><div class='add'>+		doorbell_offset &gt;&gt;= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;</div><div class='add'>+</div><div class='add'>+		xa_lock_irqsave(xa, flags);</div><div class='add'>+		fence_drv = xa_load(xa, doorbell_offset);</div><div class='add'>+		if (fence_drv)</div><div class='add'>+			amdgpu_userq_fence_driver_process(fence_drv);</div><div class='add'>+		xa_unlock_irqrestore(xa, flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev,</div><div class='add'>+					      struct amdgpu_irq_src *source,</div><div class='add'>+					      struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					   enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					  enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;sdma.num_instances);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		drm_printf(p, "\nInstance:%d\n", i);</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name,</div><div class='add'>+				   adev-&gt;sdma.ip_dump[instance_offset + j]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t instance_offset;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;sdma.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		instance_offset = i * reg_count;</div><div class='add'>+		for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+			adev-&gt;sdma.ip_dump[instance_offset + j] =</div><div class='add'>+				RREG32(sdma_v7_0_get_reg_offset(adev, i,</div><div class='add'>+				       sdma_reg_list_7_0[j].reg_offset));</div><div class='add'>+	}</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amd_ip_funcs sdma_v7_0_ip_funcs = {</div><div class='add'>+	.name = "sdma_v7_0",</div><div class='add'>+	.early_init = sdma_v7_0_early_init,</div><div class='add'>+	.late_init = NULL,</div><div class='add'>+	.sw_init = sdma_v7_0_sw_init,</div><div class='add'>+	.sw_fini = sdma_v7_0_sw_fini,</div><div class='add'>+	.hw_init = sdma_v7_0_hw_init,</div><div class='add'>+	.hw_fini = sdma_v7_0_hw_fini,</div><div class='add'>+	.suspend = sdma_v7_0_suspend,</div><div class='add'>+	.resume = sdma_v7_0_resume,</div><div class='add'>+	.is_idle = sdma_v7_0_is_idle,</div><div class='add'>+	.wait_for_idle = sdma_v7_0_wait_for_idle,</div><div class='add'>+	.soft_reset = sdma_v7_0_soft_reset,</div><div class='add'>+	.check_soft_reset = sdma_v7_0_check_soft_reset,</div><div class='add'>+	.set_clockgating_state = sdma_v7_0_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = sdma_v7_0_set_powergating_state,</div><div class='add'>+	.get_clockgating_state = sdma_v7_0_get_clockgating_state,</div><div class='add'>+	.dump_ip_state = sdma_v7_0_dump_ip_state,</div><div class='add'>+	.print_ip_state = sdma_v7_0_print_ip_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_SDMA,</div><div class='add'>+	.align_mask = 0xf,</div><div class='add'>+	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),</div><div class='add'>+	.support_64bit_ptrs = true,</div><div class='add'>+	.secure_submission_supported = true,</div><div class='add'>+	.get_rptr = sdma_v7_0_ring_get_rptr,</div><div class='add'>+	.get_wptr = sdma_v7_0_ring_get_wptr,</div><div class='add'>+	.set_wptr = sdma_v7_0_ring_set_wptr,</div><div class='add'>+	.emit_frame_size =</div><div class='add'>+		5 + /* sdma_v7_0_ring_init_cond_exec */</div><div class='add'>+		6 + /* sdma_v7_0_ring_emit_hdp_flush */</div><div class='add'>+		6 + /* sdma_v7_0_ring_emit_pipeline_sync */</div><div class='add'>+		/* sdma_v7_0_ring_emit_vm_flush */</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +</div><div class='add'>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +</div><div class='add'>+		10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */</div><div class='add'>+	.emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */</div><div class='add'>+	.emit_ib = sdma_v7_0_ring_emit_ib,</div><div class='add'>+	.emit_mem_sync = sdma_v7_0_ring_emit_mem_sync,</div><div class='add'>+	.emit_fence = sdma_v7_0_ring_emit_fence,</div><div class='add'>+	.emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync,</div><div class='add'>+	.emit_vm_flush = sdma_v7_0_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush,</div><div class='add'>+	.test_ring = sdma_v7_0_ring_test_ring,</div><div class='add'>+	.test_ib = sdma_v7_0_ring_test_ib,</div><div class='add'>+	.insert_nop = sdma_v7_0_ring_insert_nop,</div><div class='add'>+	.pad_ib = sdma_v7_0_ring_pad_ib,</div><div class='add'>+	.emit_wreg = sdma_v7_0_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = sdma_v7_0_ring_emit_reg_wait,</div><div class='add'>+	.emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait,</div><div class='add'>+	.init_cond_exec = sdma_v7_0_ring_init_cond_exec,</div><div class='add'>+	.preempt_ib = sdma_v7_0_ring_preempt_ib,</div><div class='add'>+	.reset = sdma_v7_0_reset_queue,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		adev-&gt;sdma.instance[i].ring.funcs = &amp;sdma_v7_0_ring_funcs;</div><div class='add'>+		adev-&gt;sdma.instance[i].ring.me = i;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = {</div><div class='add'>+	.set = sdma_v7_0_set_trap_irq_state,</div><div class='add'>+	.process = sdma_v7_0_process_trap_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs sdma_v7_0_fence_irq_funcs = {</div><div class='add'>+	.process = sdma_v7_0_process_fence_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = {</div><div class='add'>+	.process = sdma_v7_0_process_illegal_inst_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +</div><div class='add'>+					adev-&gt;sdma.num_instances;</div><div class='add'>+	adev-&gt;sdma.trap_irq.funcs = &amp;sdma_v7_0_trap_irq_funcs;</div><div class='add'>+	adev-&gt;sdma.fence_irq.funcs = &amp;sdma_v7_0_fence_irq_funcs;</div><div class='add'>+	adev-&gt;sdma.illegal_inst_irq.funcs = &amp;sdma_v7_0_illegal_inst_irq_funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine</div><div class='add'>+ *</div><div class='add'>+ * @ib: indirect buffer to fill with commands</div><div class='add'>+ * @src_offset: src GPU address</div><div class='add'>+ * @dst_offset: dst GPU address</div><div class='add'>+ * @byte_count: number of bytes to xfer</div><div class='add'>+ * @copy_flags: copy flags for the buffers</div><div class='add'>+ *</div><div class='add'>+ * Copy GPU buffers using the DMA engine.</div><div class='add'>+ * Used by the amdgpu ttm implementation to move pages if</div><div class='add'>+ * registered as the asic copy callback.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='add'>+				       uint64_t src_offset,</div><div class='add'>+				       uint64_t dst_offset,</div><div class='add'>+				       uint32_t byte_count,</div><div class='add'>+				       uint32_t copy_flags)</div><div class='add'>+{</div><div class='add'>+	uint32_t num_type, data_format, max_com, write_cm;</div><div class='add'>+</div><div class='add'>+	max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);</div><div class='add'>+	data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);</div><div class='add'>+	num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);</div><div class='add'>+	write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;</div><div class='add'>+</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags &amp; AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) |</div><div class='add'>+		SDMA_PKT_COPY_LINEAR_HEADER_CPV(1);</div><div class='add'>+</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = 0; /* src/dst endian swap */</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(src_offset);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(src_offset);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(dst_offset);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(dst_offset);</div><div class='add'>+</div><div class='add'>+	if ((copy_flags &amp; (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))</div><div class='add'>+		ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |</div><div class='add'>+			((copy_flags &amp; AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |</div><div class='add'>+			((copy_flags &amp; AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |</div><div class='add'>+			SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);</div><div class='add'>+	else</div><div class='add'>+		ib-&gt;ptr[ib-&gt;length_dw++] = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine</div><div class='add'>+ *</div><div class='add'>+ * @ib: indirect buffer to fill</div><div class='add'>+ * @src_data: value to write to buffer</div><div class='add'>+ * @dst_offset: dst GPU address</div><div class='add'>+ * @byte_count: number of bytes to xfer</div><div class='add'>+ *</div><div class='add'>+ * Fill GPU buffers using the DMA engine.</div><div class='add'>+ */</div><div class='add'>+static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib,</div><div class='add'>+				       uint32_t src_data,</div><div class='add'>+				       uint64_t dst_offset,</div><div class='add'>+				       uint32_t byte_count)</div><div class='add'>+{</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL) |</div><div class='add'>+		SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(1);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = lower_32_bits(dst_offset);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = upper_32_bits(dst_offset);</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = src_data;</div><div class='add'>+	ib-&gt;ptr[ib-&gt;length_dw++] = byte_count - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {</div><div class='add'>+	.copy_max_bytes = 0x400000,</div><div class='add'>+	.copy_num_dw = 8,</div><div class='add'>+	.emit_copy_buffer = sdma_v7_0_emit_copy_buffer,</div><div class='add'>+	.fill_max_bytes = 0x400000,</div><div class='add'>+	.fill_num_dw = 5,</div><div class='add'>+	.emit_fill_buffer = sdma_v7_0_emit_fill_buffer,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;mman.buffer_funcs = &amp;sdma_v7_0_buffer_funcs;</div><div class='add'>+	adev-&gt;mman.buffer_funcs_ring = &amp;adev-&gt;sdma.instance[0].ring;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = {</div><div class='add'>+	.copy_pte_num_dw = 8,</div><div class='add'>+	.copy_pte = sdma_v7_0_vm_copy_pte,</div><div class='add'>+	.write_pte = sdma_v7_0_vm_write_pte,</div><div class='add'>+	.set_pte_pde = sdma_v7_0_vm_set_pte_pde,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	unsigned i;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vm_manager.vm_pte_funcs = &amp;sdma_v7_0_vm_pte_funcs;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='add'>+		adev-&gt;vm_manager.vm_pte_scheds[i] =</div><div class='add'>+			&amp;adev-&gt;sdma.instance[i].ring.sched;</div><div class='add'>+	}</div><div class='add'>+	adev-&gt;vm_manager.vm_pte_num_scheds = adev-&gt;sdma.num_instances;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_SDMA,</div><div class='add'>+	.major = 7,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;sdma_v7_0_ip_funcs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.h b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.h<br/>new file mode 100644<br/>index 000000000000..5af863bb39c4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sdma_v7_0.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __SDMA_V7_0_H__</div><div class='add'>+#define __SDMA_V7_0_H__</div><div class='add'>+</div><div class='add'>+extern const struct amd_ip_funcs sdma_v7_0_ip_funcs;</div><div class='add'>+extern const struct amdgpu_ip_block_version sdma_v7_0_ip_block;</div><div class='add'>+</div><div class='add'>+#endif /* __SDMA_V7_0_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c<br/>index 23e4ef4fff7c..f7288372ee61 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/si.c</a></div><div class='hunk'>@@ -35,6 +35,7 @@</div><div class='ctx'> #include "amdgpu_vce.h"</div><div class='ctx'> #include "atom.h"</div><div class='ctx'> #include "amd_pcie.h"</div><div class='add'>+</div><div class='ctx'> #include "si_dpm.h"</div><div class='ctx'> #include "sid.h"</div><div class='ctx'> #include "si_ih.h"</div><div class='hunk'>@@ -44,17 +45,31 @@</div><div class='ctx'> #include "dce_v6_0.h"</div><div class='ctx'> #include "si.h"</div><div class='ctx'> #include "uvd_v3_1.h"</div><div class='del'>-#include "amdgpu_vkms.h"</div><div class='add'>+#include "vce_v1_0.h"</div><div class='add'>+</div><div class='add'>+#include "uvd/uvd_4_0_d.h"</div><div class='add'>+</div><div class='add'>+#include "smu/smu_6_0_d.h"</div><div class='add'>+#include "smu/smu_6_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "gca/gfx_6_0_d.h"</div><div class='add'>+#include "gca/gfx_6_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "oss/oss_1_0_d.h"</div><div class='ctx'> #include "oss/oss_1_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "gmc/gmc_6_0_d.h"</div><div class='add'>+#include"gmc/gmc_6_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "dce/dce_6_0_d.h"</div><div class='del'>-#include "uvd/uvd_4_0_d.h"</div><div class='add'>+#include "dce/dce_6_0_sh_mask.h"</div><div class='add'>+</div><div class='ctx'> #include "bif/bif_3_0_d.h"</div><div class='ctx'> #include "bif/bif_3_0_sh_mask.h"</div><div class='add'>+#include "si_enums.h"</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='add'>+#include "amdgpu_vkms.h"</div><div class='ctx'> </div><div class='ctx'> static const u32 tahiti_golden_registers[] =</div><div class='ctx'> {</div><div class='hunk'>@@ -907,9 +922,7 @@ static const u32 hainan_mgcg_cgcg_init[] =</div><div class='ctx'> 	0x3630, 0xfffffff0, 0x00000100,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* XXX: update when we support VCE */</div><div class='del'>-#if 0</div><div class='del'>-/* tahiti, pitcarin, verde */</div><div class='add'>+/* tahiti, pitcairn, verde */</div><div class='ctx'> static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] =</div><div class='ctx'> {</div><div class='ctx'> 	{</div><div class='hunk'>@@ -926,13 +939,7 @@ static const struct amdgpu_video_codecs tahiti_video_codecs_encode =</div><div class='ctx'> 	.codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array),</div><div class='ctx'> 	.codec_array = tahiti_video_codecs_encode_array,</div><div class='ctx'> };</div><div class='del'>-#else</div><div class='del'>-static const struct amdgpu_video_codecs tahiti_video_codecs_encode =</div><div class='del'>-{</div><div class='del'>-	.codec_count = 0,</div><div class='del'>-	.codec_array = NULL,</div><div class='del'>-};</div><div class='del'>-#endif</div><div class='add'>+</div><div class='ctx'> /* oland and hainan don't support encode */</div><div class='ctx'> static const struct amdgpu_video_codecs hainan_video_codecs_encode =</div><div class='ctx'> {</div><div class='hunk'>@@ -940,7 +947,7 @@ static const struct amdgpu_video_codecs hainan_video_codecs_encode =</div><div class='ctx'> 	.codec_array = NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* tahiti, pitcarin, verde, oland */</div><div class='add'>+/* tahiti, pitcairn, verde, oland */</div><div class='ctx'> static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] =</div><div class='ctx'> {</div><div class='ctx'> 	{</div><div class='hunk'>@@ -1071,8 +1078,8 @@ static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)</div><div class='ctx'> 	u32 r;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;adev-&gt;smc_idx_lock, flags);</div><div class='del'>-	WREG32(SMC_IND_INDEX_0, (reg));</div><div class='del'>-	r = RREG32(SMC_IND_DATA_0);</div><div class='add'>+	WREG32(mmSMC_IND_INDEX_0, (reg));</div><div class='add'>+	r = RREG32(mmSMC_IND_DATA_0);</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;adev-&gt;smc_idx_lock, flags);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -1082,8 +1089,8 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;adev-&gt;smc_idx_lock, flags);</div><div class='del'>-	WREG32(SMC_IND_INDEX_0, (reg));</div><div class='del'>-	WREG32(SMC_IND_DATA_0, (v));</div><div class='add'>+	WREG32(mmSMC_IND_INDEX_0, (reg));</div><div class='add'>+	WREG32(mmSMC_IND_DATA_0, (v));</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;adev-&gt;smc_idx_lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1110,55 +1117,55 @@ static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {</div><div class='del'>-	{GRBM_STATUS},</div><div class='add'>+	{mmGRBM_STATUS},</div><div class='ctx'> 	{mmGRBM_STATUS2},</div><div class='ctx'> 	{mmGRBM_STATUS_SE0},</div><div class='ctx'> 	{mmGRBM_STATUS_SE1},</div><div class='ctx'> 	{mmSRBM_STATUS},</div><div class='ctx'> 	{mmSRBM_STATUS2},</div><div class='del'>-	{DMA_STATUS_REG + DMA0_REGISTER_OFFSET},</div><div class='del'>-	{DMA_STATUS_REG + DMA1_REGISTER_OFFSET},</div><div class='add'>+	{mmDMA_STATUS_REG + DMA0_REGISTER_OFFSET},</div><div class='add'>+	{mmDMA_STATUS_REG + DMA1_REGISTER_OFFSET},</div><div class='ctx'> 	{mmCP_STAT},</div><div class='ctx'> 	{mmCP_STALLED_STAT1},</div><div class='ctx'> 	{mmCP_STALLED_STAT2},</div><div class='ctx'> 	{mmCP_STALLED_STAT3},</div><div class='del'>-	{GB_ADDR_CONFIG},</div><div class='del'>-	{MC_ARB_RAMCFG},</div><div class='del'>-	{GB_TILE_MODE0},</div><div class='del'>-	{GB_TILE_MODE1},</div><div class='del'>-	{GB_TILE_MODE2},</div><div class='del'>-	{GB_TILE_MODE3},</div><div class='del'>-	{GB_TILE_MODE4},</div><div class='del'>-	{GB_TILE_MODE5},</div><div class='del'>-	{GB_TILE_MODE6},</div><div class='del'>-	{GB_TILE_MODE7},</div><div class='del'>-	{GB_TILE_MODE8},</div><div class='del'>-	{GB_TILE_MODE9},</div><div class='del'>-	{GB_TILE_MODE10},</div><div class='del'>-	{GB_TILE_MODE11},</div><div class='del'>-	{GB_TILE_MODE12},</div><div class='del'>-	{GB_TILE_MODE13},</div><div class='del'>-	{GB_TILE_MODE14},</div><div class='del'>-	{GB_TILE_MODE15},</div><div class='del'>-	{GB_TILE_MODE16},</div><div class='del'>-	{GB_TILE_MODE17},</div><div class='del'>-	{GB_TILE_MODE18},</div><div class='del'>-	{GB_TILE_MODE19},</div><div class='del'>-	{GB_TILE_MODE20},</div><div class='del'>-	{GB_TILE_MODE21},</div><div class='del'>-	{GB_TILE_MODE22},</div><div class='del'>-	{GB_TILE_MODE23},</div><div class='del'>-	{GB_TILE_MODE24},</div><div class='del'>-	{GB_TILE_MODE25},</div><div class='del'>-	{GB_TILE_MODE26},</div><div class='del'>-	{GB_TILE_MODE27},</div><div class='del'>-	{GB_TILE_MODE28},</div><div class='del'>-	{GB_TILE_MODE29},</div><div class='del'>-	{GB_TILE_MODE30},</div><div class='del'>-	{GB_TILE_MODE31},</div><div class='del'>-	{CC_RB_BACKEND_DISABLE, true},</div><div class='del'>-	{GC_USER_RB_BACKEND_DISABLE, true},</div><div class='del'>-	{PA_SC_RASTER_CONFIG, true},</div><div class='add'>+	{mmGB_ADDR_CONFIG},</div><div class='add'>+	{mmMC_ARB_RAMCFG},</div><div class='add'>+	{mmGB_TILE_MODE0},</div><div class='add'>+	{mmGB_TILE_MODE1},</div><div class='add'>+	{mmGB_TILE_MODE2},</div><div class='add'>+	{mmGB_TILE_MODE3},</div><div class='add'>+	{mmGB_TILE_MODE4},</div><div class='add'>+	{mmGB_TILE_MODE5},</div><div class='add'>+	{mmGB_TILE_MODE6},</div><div class='add'>+	{mmGB_TILE_MODE7},</div><div class='add'>+	{mmGB_TILE_MODE8},</div><div class='add'>+	{mmGB_TILE_MODE9},</div><div class='add'>+	{mmGB_TILE_MODE10},</div><div class='add'>+	{mmGB_TILE_MODE11},</div><div class='add'>+	{mmGB_TILE_MODE12},</div><div class='add'>+	{mmGB_TILE_MODE13},</div><div class='add'>+	{mmGB_TILE_MODE14},</div><div class='add'>+	{mmGB_TILE_MODE15},</div><div class='add'>+	{mmGB_TILE_MODE16},</div><div class='add'>+	{mmGB_TILE_MODE17},</div><div class='add'>+	{mmGB_TILE_MODE18},</div><div class='add'>+	{mmGB_TILE_MODE19},</div><div class='add'>+	{mmGB_TILE_MODE20},</div><div class='add'>+	{mmGB_TILE_MODE21},</div><div class='add'>+	{mmGB_TILE_MODE22},</div><div class='add'>+	{mmGB_TILE_MODE23},</div><div class='add'>+	{mmGB_TILE_MODE24},</div><div class='add'>+	{mmGB_TILE_MODE25},</div><div class='add'>+	{mmGB_TILE_MODE26},</div><div class='add'>+	{mmGB_TILE_MODE27},</div><div class='add'>+	{mmGB_TILE_MODE28},</div><div class='add'>+	{mmGB_TILE_MODE29},</div><div class='add'>+	{mmGB_TILE_MODE30},</div><div class='add'>+	{mmGB_TILE_MODE31},</div><div class='add'>+	{mmCC_RB_BACKEND_DISABLE, true},</div><div class='add'>+	{mmGC_USER_RB_BACKEND_DISABLE, true},</div><div class='add'>+	{mmPA_SC_RASTER_CONFIG, true},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t si_get_register_value(struct amdgpu_device *adev,</div><div class='hunk'>@@ -1264,37 +1271,37 @@ static bool si_read_disabled_bios(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 rom_cntl;</div><div class='ctx'> 	bool r;</div><div class='ctx'> </div><div class='del'>-	bus_cntl = RREG32(R600_BUS_CNTL);</div><div class='add'>+	bus_cntl = RREG32(mmBUS_CNTL);</div><div class='ctx'> 	if (adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);</div><div class='del'>-		d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);</div><div class='del'>-		vga_render_control = RREG32(VGA_RENDER_CONTROL);</div><div class='add'>+		d1vga_control = RREG32(mmD1VGA_CONTROL);</div><div class='add'>+		d2vga_control = RREG32(mmD2VGA_CONTROL);</div><div class='add'>+		vga_render_control = RREG32(mmVGA_RENDER_CONTROL);</div><div class='ctx'> 	}</div><div class='ctx'> 	rom_cntl = RREG32(R600_ROM_CNTL);</div><div class='ctx'> </div><div class='ctx'> 	/* enable the rom */</div><div class='del'>-	WREG32(R600_BUS_CNTL, (bus_cntl &amp; ~R600_BIOS_ROM_DIS));</div><div class='add'>+	WREG32(mmBUS_CNTL, (bus_cntl &amp; ~BUS_CNTL__BIOS_ROM_DIS_MASK));</div><div class='ctx'> 	if (adev-&gt;mode_info.num_crtc) {</div><div class='ctx'> 		/* Disable VGA mode */</div><div class='del'>-		WREG32(AVIVO_D1VGA_CONTROL,</div><div class='del'>-		       (d1vga_control &amp; ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |</div><div class='del'>-					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));</div><div class='del'>-		WREG32(AVIVO_D2VGA_CONTROL,</div><div class='del'>-		       (d2vga_control &amp; ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |</div><div class='del'>-					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));</div><div class='del'>-		WREG32(VGA_RENDER_CONTROL,</div><div class='del'>-		       (vga_render_control &amp; C_000300_VGA_VSTATUS_CNTL));</div><div class='add'>+		WREG32(mmD1VGA_CONTROL,</div><div class='add'>+		       (d1vga_control &amp; ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |</div><div class='add'>+					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));</div><div class='add'>+		WREG32(mmD2VGA_CONTROL,</div><div class='add'>+		       (d2vga_control &amp; ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |</div><div class='add'>+					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));</div><div class='add'>+		WREG32(mmVGA_RENDER_CONTROL,</div><div class='add'>+		       (vga_render_control &amp; ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));</div><div class='ctx'> 	}</div><div class='ctx'> 	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_read_bios(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* restore regs */</div><div class='del'>-	WREG32(R600_BUS_CNTL, bus_cntl);</div><div class='add'>+	WREG32(mmBUS_CNTL, bus_cntl);</div><div class='ctx'> 	if (adev-&gt;mode_info.num_crtc) {</div><div class='del'>-		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);</div><div class='del'>-		WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);</div><div class='del'>-		WREG32(VGA_RENDER_CONTROL, vga_render_control);</div><div class='add'>+		WREG32(mmD1VGA_CONTROL, d1vga_control);</div><div class='add'>+		WREG32(mmD2VGA_CONTROL, d2vga_control);</div><div class='add'>+		WREG32(mmVGA_RENDER_CONTROL, vga_render_control);</div><div class='ctx'> 	}</div><div class='ctx'> 	WREG32(R600_ROM_CNTL, rom_cntl);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1331,23 +1338,24 @@ static void si_set_clk_bypass_mode(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 tmp, i;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_SPLL_FUNC_CNTL);</div><div class='del'>-	tmp |= SPLL_BYPASS_EN;</div><div class='del'>-	WREG32(CG_SPLL_FUNC_CNTL, tmp);</div><div class='add'>+	tmp = RREG32(mmCG_SPLL_FUNC_CNTL);</div><div class='add'>+	tmp |= CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;</div><div class='add'>+	WREG32(mmCG_SPLL_FUNC_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_SPLL_FUNC_CNTL_2);</div><div class='del'>-	tmp |= SPLL_CTLREQ_CHG;</div><div class='del'>-	WREG32(CG_SPLL_FUNC_CNTL_2, tmp);</div><div class='add'>+	tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);</div><div class='add'>+	tmp |= CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK;</div><div class='add'>+	WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (RREG32(SPLL_STATUS) &amp; SPLL_CHG_STATUS)</div><div class='add'>+		if (RREG32(mmCG_SPLL_STATUS) &amp; CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK)</div><div class='ctx'> 			break;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_SPLL_FUNC_CNTL_2);</div><div class='del'>-	tmp &amp;= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);</div><div class='del'>-	WREG32(CG_SPLL_FUNC_CNTL_2, tmp);</div><div class='add'>+	tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);</div><div class='add'>+	tmp &amp;= ~(CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK |</div><div class='add'>+		CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK);</div><div class='add'>+	WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32(MPLL_CNTL_MODE);</div><div class='ctx'> 	tmp &amp;= ~MPLL_MCLK_SEL;</div><div class='hunk'>@@ -1358,21 +1366,21 @@ static void si_spll_powerdown(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(SPLL_CNTL_MODE);</div><div class='del'>-	tmp |= SPLL_SW_DIR_CONTROL;</div><div class='del'>-	WREG32(SPLL_CNTL_MODE, tmp);</div><div class='add'>+	tmp = RREG32(mmSPLL_CNTL_MODE);</div><div class='add'>+	tmp |= SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK;</div><div class='add'>+	WREG32(mmSPLL_CNTL_MODE, tmp);</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_SPLL_FUNC_CNTL);</div><div class='del'>-	tmp |= SPLL_RESET;</div><div class='del'>-	WREG32(CG_SPLL_FUNC_CNTL, tmp);</div><div class='add'>+	tmp = RREG32(mmCG_SPLL_FUNC_CNTL);</div><div class='add'>+	tmp |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;</div><div class='add'>+	WREG32(mmCG_SPLL_FUNC_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_SPLL_FUNC_CNTL);</div><div class='del'>-	tmp |= SPLL_SLEEP;</div><div class='del'>-	WREG32(CG_SPLL_FUNC_CNTL, tmp);</div><div class='add'>+	tmp = RREG32(mmCG_SPLL_FUNC_CNTL);</div><div class='add'>+	tmp |= CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK;</div><div class='add'>+	WREG32(mmCG_SPLL_FUNC_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(SPLL_CNTL_MODE);</div><div class='del'>-	tmp &amp;= ~SPLL_SW_DIR_CONTROL;</div><div class='del'>-	WREG32(SPLL_CNTL_MODE, tmp);</div><div class='add'>+	tmp = RREG32(mmSPLL_CNTL_MODE);</div><div class='add'>+	tmp &amp;= ~SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK;</div><div class='add'>+	WREG32(mmSPLL_CNTL_MODE, tmp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int si_gpu_pci_config_reset(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1409,9 +1417,9 @@ static int si_gpu_pci_config_reset(struct amdgpu_device *adev)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool si_asic_supports_baco(struct amdgpu_device *adev)</div><div class='add'>+static int si_asic_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return false;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum amd_reset_method</div><div class='hunk'>@@ -1454,14 +1462,14 @@ static void si_vga_set_state(struct amdgpu_device *adev, bool state)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t temp;</div><div class='ctx'> </div><div class='del'>-	temp = RREG32(CONFIG_CNTL);</div><div class='add'>+	temp = RREG32(mmCONFIG_CNTL);</div><div class='ctx'> 	if (!state) {</div><div class='ctx'> 		temp &amp;= ~(1&lt;&lt;0);</div><div class='ctx'> 		temp |= (1&lt;&lt;1);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		temp &amp;= ~(1&lt;&lt;1);</div><div class='ctx'> 	}</div><div class='del'>-	WREG32(CONFIG_CNTL, temp);</div><div class='add'>+	WREG32(mmCONFIG_CNTL, temp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 si_get_xclk(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1469,12 +1477,12 @@ static u32 si_get_xclk(struct amdgpu_device *adev)</div><div class='ctx'> 	u32 reference_clock = adev-&gt;clock.spll.reference_freq;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_CLKPIN_CNTL_2);</div><div class='del'>-	if (tmp &amp; MUX_TCLK_TO_XCLK)</div><div class='add'>+	tmp = RREG32(mmCG_CLKPIN_CNTL_2);</div><div class='add'>+	if (tmp &amp; CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK)</div><div class='ctx'> 		return TCLK;</div><div class='ctx'> </div><div class='del'>-	tmp = RREG32(CG_CLKPIN_CNTL);</div><div class='del'>-	if (tmp &amp; XTALIN_DIVIDE)</div><div class='add'>+	tmp = RREG32(mmCG_CLKPIN_CNTL);</div><div class='add'>+	if (tmp &amp; CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)</div><div class='ctx'> 		return reference_clock / 4;</div><div class='ctx'> </div><div class='ctx'> 	return reference_clock;</div><div class='hunk'>@@ -1519,9 +1527,9 @@ static int si_get_pcie_lanes(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);</div><div class='add'>+	link_width_cntl = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);</div><div class='ctx'> </div><div class='del'>-	switch ((link_width_cntl &amp; LC_LINK_WIDTH_RD_MASK) &gt;&gt; LC_LINK_WIDTH_RD_SHIFT) {</div><div class='add'>+	switch ((link_width_cntl &amp; PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) &gt;&gt; PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT) {</div><div class='ctx'> 	case LC_LINK_WIDTH_X1:</div><div class='ctx'> 		return 1;</div><div class='ctx'> 	case LC_LINK_WIDTH_X2:</div><div class='hunk'>@@ -1568,13 +1576,13 @@ static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);</div><div class='del'>-	link_width_cntl &amp;= ~LC_LINK_WIDTH_MASK;</div><div class='del'>-	link_width_cntl |= mask &lt;&lt; LC_LINK_WIDTH_SHIFT;</div><div class='del'>-	link_width_cntl |= (LC_RECONFIG_NOW |</div><div class='del'>-			    LC_RECONFIG_ARC_MISSING_ESCAPE);</div><div class='add'>+	link_width_cntl = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);</div><div class='add'>+	link_width_cntl &amp;= ~PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK;</div><div class='add'>+	link_width_cntl |= mask &lt;&lt; PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT;</div><div class='add'>+	link_width_cntl |= (PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK |</div><div class='add'>+		PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK);</div><div class='ctx'> </div><div class='del'>-	WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);</div><div class='add'>+	WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,</div><div class='hunk'>@@ -1888,7 +1896,7 @@ static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);</div><div class='ctx'> </div><div class='ctx'> 	if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) {</div><div class='del'>-		DRM_ERROR("Timeout setting UVD clocks!\n");</div><div class='add'>+		DRM_ERROR("Timeout setting VCE clocks!\n");</div><div class='ctx'> 		return -ETIMEDOUT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1910,6 +1918,14 @@ static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)</div><div class='ctx'> 		     ~VCEPLL_BYPASS_EN_MASK);</div><div class='ctx'> </div><div class='ctx'> 	if (!evclk || !ecclk) {</div><div class='add'>+		/*</div><div class='add'>+		 * On some chips, the PLL takes way too long to get out of</div><div class='add'>+		 * sleep mode, causing a timeout waiting on CTLACK/CTLACK2.</div><div class='add'>+		 * Leave the PLL running in bypass mode.</div><div class='add'>+		 */</div><div class='add'>+		if (adev-&gt;pdev-&gt;device == 0x6780)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='ctx'> 		/* Keep the Bypass mode, put PLL to sleep */</div><div class='ctx'> 		WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,</div><div class='ctx'> 			     ~VCEPLL_SLEEP_MASK);</div><div class='hunk'>@@ -2018,13 +2034,13 @@ static const struct amdgpu_asic_funcs si_asic_funcs =</div><div class='ctx'> </div><div class='ctx'> static uint32_t si_get_rev_id(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	return (RREG32(CC_DRM_ID_STRAPS) &amp; CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)</div><div class='add'>+	return (RREG32(mmCC_DRM_ID_STRAPS) &amp; CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)</div><div class='ctx'> 		&gt;&gt; CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_early_init(void *handle)</div><div class='add'>+static int si_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;smc_rreg = &amp;si_smc_rreg;</div><div class='ctx'> 	adev-&gt;smc_wreg = &amp;si_smc_wreg;</div><div class='hunk'>@@ -2148,17 +2164,6 @@ static int si_common_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_sw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int si_common_sw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> static void si_init_golden_registers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='hunk'>@@ -2250,9 +2255,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)</div><div class='ctx'> 					CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);</div><div class='del'>-	current_data_rate = (speed_cntl &amp; LC_CURRENT_DATA_RATE_MASK) &gt;&gt;</div><div class='del'>-		LC_CURRENT_DATA_RATE_SHIFT;</div><div class='add'>+	speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL);</div><div class='add'>+	current_data_rate = (speed_cntl &amp; PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) &gt;&gt;</div><div class='add'>+		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;</div><div class='ctx'> 	if (adev-&gt;pm.pcie_gen_mask &amp; CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {</div><div class='ctx'> 		if (current_data_rate == 2) {</div><div class='ctx'> 			DRM_INFO("PCIE gen 3 link speeds already enabled\n");</div><div class='hunk'>@@ -2279,17 +2284,17 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)</div><div class='ctx'> 			pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);</div><div class='ctx'> 			pcie_capability_set_word(adev-&gt;pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);</div><div class='ctx'> </div><div class='del'>-			tmp = RREG32_PCIE(PCIE_LC_STATUS1);</div><div class='del'>-			max_lw = (tmp &amp; LC_DETECTED_LINK_WIDTH_MASK) &gt;&gt; LC_DETECTED_LINK_WIDTH_SHIFT;</div><div class='del'>-			current_lw = (tmp &amp; LC_OPERATING_LINK_WIDTH_MASK) &gt;&gt; LC_OPERATING_LINK_WIDTH_SHIFT;</div><div class='add'>+			tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);</div><div class='add'>+			max_lw = (tmp &amp; PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) &gt;&gt; PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;</div><div class='add'>+			current_lw = (tmp &amp; PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) &gt;&gt; PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;</div><div class='ctx'> </div><div class='ctx'> 			if (current_lw &lt; max_lw) {</div><div class='del'>-				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);</div><div class='del'>-				if (tmp &amp; LC_RENEGOTIATION_SUPPORT) {</div><div class='del'>-					tmp &amp;= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);</div><div class='del'>-					tmp |= (max_lw &lt;&lt; LC_LINK_WIDTH_SHIFT);</div><div class='del'>-					tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;</div><div class='del'>-					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);</div><div class='add'>+				tmp = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);</div><div class='add'>+				if (tmp &amp; PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {</div><div class='add'>+					tmp &amp;= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);</div><div class='add'>+					tmp |= (max_lw &lt;&lt; PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);</div><div class='add'>+					tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;</div><div class='add'>+					WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -2312,13 +2317,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)</div><div class='ctx'> 							  PCI_EXP_LNKCTL2,</div><div class='ctx'> 							  &amp;gpu_cfg2);</div><div class='ctx'> </div><div class='del'>-				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);</div><div class='del'>-				tmp |= LC_SET_QUIESCE;</div><div class='del'>-				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);</div><div class='add'>+				tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);</div><div class='add'>+				tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;</div><div class='add'>+				WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);</div><div class='ctx'> </div><div class='del'>-				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);</div><div class='del'>-				tmp |= LC_REDO_EQ;</div><div class='del'>-				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);</div><div class='add'>+				tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);</div><div class='add'>+				tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;</div><div class='add'>+				WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);</div><div class='ctx'> </div><div class='ctx'> 				mdelay(100);</div><div class='ctx'> </div><div class='hunk'>@@ -2344,16 +2349,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)</div><div class='ctx'> 								   (PCI_EXP_LNKCTL2_ENTER_COMP |</div><div class='ctx'> 								    PCI_EXP_LNKCTL2_TX_MARGIN));</div><div class='ctx'> </div><div class='del'>-				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);</div><div class='del'>-				tmp &amp;= ~LC_SET_QUIESCE;</div><div class='del'>-				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);</div><div class='add'>+				tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);</div><div class='add'>+				tmp &amp;= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;</div><div class='add'>+				WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;</div><div class='del'>-	speed_cntl &amp;= ~LC_FORCE_DIS_SW_SPEED_CHANGE;</div><div class='del'>-	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);</div><div class='add'>+	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK;</div><div class='add'>+	speed_cntl &amp;= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;</div><div class='add'>+	WREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL, speed_cntl);</div><div class='ctx'> </div><div class='ctx'> 	tmp16 = 0;</div><div class='ctx'> 	if (adev-&gt;pm.pcie_gen_mask &amp; CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)</div><div class='hunk'>@@ -2365,13 +2370,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)</div><div class='ctx'> 	pcie_capability_clear_and_set_word(adev-&gt;pdev, PCI_EXP_LNKCTL2,</div><div class='ctx'> 					   PCI_EXP_LNKCTL2_TLS, tmp16);</div><div class='ctx'> </div><div class='del'>-	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);</div><div class='del'>-	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;</div><div class='del'>-	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);</div><div class='add'>+	speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL);</div><div class='add'>+	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;</div><div class='add'>+	WREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL, speed_cntl);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);</div><div class='del'>-		if ((speed_cntl &amp; LC_INITIATE_LINK_SPEED_CHANGE) == 0)</div><div class='add'>+		speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL);</div><div class='add'>+		if ((speed_cntl &amp; PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)</div><div class='ctx'> 			break;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2429,121 +2434,121 @@ static void si_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!amdgpu_device_should_use_aspm(adev))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);</div><div class='del'>-	data &amp;= ~LC_XMIT_N_FTS_MASK;</div><div class='del'>-	data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;</div><div class='add'>+	orig = data = RREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL);</div><div class='add'>+	data &amp;= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;</div><div class='add'>+	data |= (0x24 &lt;&lt; PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;</div><div class='ctx'> 	if (orig != data)</div><div class='del'>-		WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);</div><div class='add'>+		WREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL, data);</div><div class='ctx'> </div><div class='del'>-	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);</div><div class='del'>-	data |= LC_GO_TO_RECOVERY;</div><div class='add'>+	orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL3);</div><div class='add'>+	data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;</div><div class='ctx'> 	if (orig != data)</div><div class='del'>-		WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);</div><div class='add'>+		WREG32_PCIE_PORT(ixPCIE_LC_CNTL3, data);</div><div class='ctx'> </div><div class='del'>-	orig = data = RREG32_PCIE(PCIE_P_CNTL);</div><div class='del'>-	data |= P_IGNORE_EDB_ERR;</div><div class='add'>+	orig = data = RREG32_PCIE(ixPCIE_P_CNTL);</div><div class='add'>+	data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;</div><div class='ctx'> 	if (orig != data)</div><div class='del'>-		WREG32_PCIE(PCIE_P_CNTL, data);</div><div class='add'>+		WREG32_PCIE(ixPCIE_P_CNTL, data);</div><div class='ctx'> </div><div class='del'>-	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);</div><div class='del'>-	data &amp;= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);</div><div class='del'>-	data |= LC_PMI_TO_L1_DIS;</div><div class='add'>+	orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL);</div><div class='add'>+	data &amp;= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);</div><div class='add'>+	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;</div><div class='ctx'> 	if (!disable_l0s)</div><div class='del'>-		data |= LC_L0S_INACTIVITY(7);</div><div class='add'>+		data |= (7 &lt;&lt; PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);</div><div class='ctx'> </div><div class='ctx'> 	if (!disable_l1) {</div><div class='del'>-		data |= LC_L1_INACTIVITY(7);</div><div class='del'>-		data &amp;= ~LC_PMI_TO_L1_DIS;</div><div class='add'>+		data |= (7 &lt;&lt; PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);</div><div class='add'>+		data &amp;= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;</div><div class='ctx'> 		if (orig != data)</div><div class='del'>-			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);</div><div class='add'>+			WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data);</div><div class='ctx'> </div><div class='ctx'> 		if (!disable_plloff_in_l1) {</div><div class='ctx'> 			bool clk_req_support;</div><div class='ctx'> </div><div class='del'>-			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);</div><div class='del'>-			data &amp;= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);</div><div class='del'>-			data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);</div><div class='add'>+			orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_0);</div><div class='add'>+			data &amp;= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);</div><div class='add'>+			data |= (7 &lt;&lt; PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | (7 &lt;&lt; PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);</div><div class='add'>+				si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_0, data);</div><div class='ctx'> </div><div class='del'>-			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);</div><div class='del'>-			data &amp;= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);</div><div class='del'>-			data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);</div><div class='add'>+			orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_1);</div><div class='add'>+			data &amp;= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);</div><div class='add'>+			data |= (7 &lt;&lt; PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | (7 &lt;&lt; PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);</div><div class='add'>+				si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_1, data);</div><div class='ctx'> </div><div class='del'>-			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);</div><div class='del'>-			data &amp;= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);</div><div class='del'>-			data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);</div><div class='add'>+			orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_0);</div><div class='add'>+			data &amp;= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);</div><div class='add'>+			data |= (7 &lt;&lt; PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | (7 &lt;&lt; PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);</div><div class='add'>+				si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_0, data);</div><div class='ctx'> </div><div class='del'>-			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);</div><div class='del'>-			data &amp;= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);</div><div class='del'>-			data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);</div><div class='add'>+			orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_1);</div><div class='add'>+			data &amp;= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);</div><div class='add'>+			data |= (7 &lt;&lt; PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | (7 &lt;&lt; PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);</div><div class='add'>+				si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_1, data);</div><div class='ctx'> </div><div class='ctx'> 			if ((adev-&gt;asic_type != CHIP_OLAND) &amp;&amp; (adev-&gt;asic_type != CHIP_HAINAN)) {</div><div class='del'>-				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_0_MASK;</div><div class='add'>+				orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_0);</div><div class='add'>+				data &amp;= ~PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);</div><div class='add'>+					si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_0, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_1_MASK;</div><div class='add'>+				orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_1);</div><div class='add'>+				data &amp;= ~PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);</div><div class='add'>+					si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_1, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_2_MASK;</div><div class='add'>+				orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_2);</div><div class='add'>+				data &amp;= ~PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);</div><div class='add'>+					si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_2, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_3_MASK;</div><div class='add'>+				orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_3);</div><div class='add'>+				data &amp;= ~PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);</div><div class='add'>+					si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_3, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_0_MASK;</div><div class='add'>+				orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_0);</div><div class='add'>+				data &amp;= ~PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);</div><div class='add'>+					si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_0, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_1_MASK;</div><div class='add'>+				orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_1);</div><div class='add'>+				data &amp;= ~PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);</div><div class='add'>+					si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_1, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_2_MASK;</div><div class='add'>+				orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_2);</div><div class='add'>+				data &amp;= ~PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);</div><div class='add'>+					si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_2, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);</div><div class='del'>-				data &amp;= ~PLL_RAMP_UP_TIME_3_MASK;</div><div class='add'>+				orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_3);</div><div class='add'>+				data &amp;= ~PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);</div><div class='add'>+					si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_3, data);</div><div class='ctx'> 			}</div><div class='del'>-			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);</div><div class='del'>-			data &amp;= ~LC_DYN_LANES_PWR_STATE_MASK;</div><div class='del'>-			data |= LC_DYN_LANES_PWR_STATE(3);</div><div class='add'>+			orig = data = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);</div><div class='add'>+			data &amp;= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;</div><div class='add'>+			data |= (3 &lt;&lt; PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);</div><div class='add'>+				WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, data);</div><div class='ctx'> </div><div class='del'>-			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);</div><div class='del'>-			data &amp;= ~LS2_EXIT_TIME_MASK;</div><div class='add'>+			orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_CNTL);</div><div class='add'>+			data &amp;= ~PB0_PIF_CNTL__LS2_EXIT_TIME_MASK;</div><div class='ctx'> 			if ((adev-&gt;asic_type == CHIP_OLAND) || (adev-&gt;asic_type == CHIP_HAINAN))</div><div class='del'>-				data |= LS2_EXIT_TIME(5);</div><div class='add'>+				data |= (5 &lt;&lt; PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);</div><div class='add'>+				si_pif_phy0_wreg(adev,ixPB0_PIF_CNTL, data);</div><div class='ctx'> </div><div class='del'>-			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);</div><div class='del'>-			data &amp;= ~LS2_EXIT_TIME_MASK;</div><div class='add'>+			orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_CNTL);</div><div class='add'>+			data &amp;= ~PB1_PIF_CNTL__LS2_EXIT_TIME_MASK;</div><div class='ctx'> 			if ((adev-&gt;asic_type == CHIP_OLAND) || (adev-&gt;asic_type == CHIP_HAINAN))</div><div class='del'>-				data |= LS2_EXIT_TIME(5);</div><div class='add'>+				data |= (5 &lt;&lt; PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT);</div><div class='ctx'> 			if (orig != data)</div><div class='del'>-				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);</div><div class='add'>+				si_pif_phy1_wreg(adev,ixPB1_PIF_CNTL, data);</div><div class='ctx'> </div><div class='ctx'> 			if (!disable_clkreq &amp;&amp;</div><div class='ctx'> 			    !pci_is_root_bus(adev-&gt;pdev-&gt;bus)) {</div><div class='hunk'>@@ -2559,64 +2564,64 @@ static void si_program_aspm(struct amdgpu_device *adev)</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			if (clk_req_support) {</div><div class='del'>-				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);</div><div class='del'>-				data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;</div><div class='add'>+				orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL2);</div><div class='add'>+				data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);</div><div class='add'>+					WREG32_PCIE_PORT(ixPCIE_LC_CNTL2, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = RREG32(THM_CLK_CNTL);</div><div class='del'>-				data &amp;= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);</div><div class='del'>-				data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);</div><div class='add'>+				orig = data = RREG32(mmTHM_CLK_CNTL);</div><div class='add'>+				data &amp;= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK);</div><div class='add'>+				data |= (1 &lt;&lt; THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | (1 &lt;&lt; THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32(THM_CLK_CNTL, data);</div><div class='add'>+					WREG32(mmTHM_CLK_CNTL, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = RREG32(MISC_CLK_CNTL);</div><div class='del'>-				data &amp;= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);</div><div class='del'>-				data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);</div><div class='add'>+				orig = data = RREG32(mmMISC_CLK_CNTL);</div><div class='add'>+				data &amp;= ~(MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK | MISC_CLK_CNTL__ZCLK_SEL_MASK);</div><div class='add'>+				data |= (1 &lt;&lt; MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT) | (1 &lt;&lt; MISC_CLK_CNTL__ZCLK_SEL__SHIFT);</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32(MISC_CLK_CNTL, data);</div><div class='add'>+					WREG32(mmMISC_CLK_CNTL, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = RREG32(CG_CLKPIN_CNTL);</div><div class='del'>-				data &amp;= ~BCLK_AS_XCLK;</div><div class='add'>+				orig = data = RREG32(mmCG_CLKPIN_CNTL);</div><div class='add'>+				data &amp;= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32(CG_CLKPIN_CNTL, data);</div><div class='add'>+					WREG32(mmCG_CLKPIN_CNTL, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = RREG32(CG_CLKPIN_CNTL_2);</div><div class='del'>-				data &amp;= ~FORCE_BIF_REFCLK_EN;</div><div class='add'>+				orig = data = RREG32(mmCG_CLKPIN_CNTL_2);</div><div class='add'>+				data &amp;= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32(CG_CLKPIN_CNTL_2, data);</div><div class='add'>+					WREG32(mmCG_CLKPIN_CNTL_2, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = RREG32(MPLL_BYPASSCLK_SEL);</div><div class='del'>-				data &amp;= ~MPLL_CLKOUT_SEL_MASK;</div><div class='del'>-				data |= MPLL_CLKOUT_SEL(4);</div><div class='add'>+				orig = data = RREG32(mmMPLL_BYPASSCLK_SEL);</div><div class='add'>+				data &amp;= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;</div><div class='add'>+				data |= 4 &lt;&lt; MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32(MPLL_BYPASSCLK_SEL, data);</div><div class='add'>+					WREG32(mmMPLL_BYPASSCLK_SEL, data);</div><div class='ctx'> </div><div class='del'>-				orig = data = RREG32(SPLL_CNTL_MODE);</div><div class='del'>-				data &amp;= ~SPLL_REFCLK_SEL_MASK;</div><div class='add'>+				orig = data = RREG32(mmSPLL_CNTL_MODE);</div><div class='add'>+				data &amp;= ~SPLL_CNTL_MODE__SPLL_REFCLK_SEL_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32(SPLL_CNTL_MODE, data);</div><div class='add'>+					WREG32(mmSPLL_CNTL_MODE, data);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (orig != data)</div><div class='del'>-			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);</div><div class='add'>+			WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	orig = data = RREG32_PCIE(PCIE_CNTL2);</div><div class='del'>-	data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;</div><div class='add'>+	orig = data = RREG32_PCIE(ixPCIE_CNTL2);</div><div class='add'>+	data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | PCIE_CNTL2__MST_MEM_LS_EN_MASK | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;</div><div class='ctx'> 	if (orig != data)</div><div class='del'>-		WREG32_PCIE(PCIE_CNTL2, data);</div><div class='add'>+		WREG32_PCIE(ixPCIE_CNTL2, data);</div><div class='ctx'> </div><div class='ctx'> 	if (!disable_l0s) {</div><div class='del'>-		data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);</div><div class='del'>-		if((data &amp; LC_N_FTS_MASK) == LC_N_FTS_MASK) {</div><div class='del'>-			data = RREG32_PCIE(PCIE_LC_STATUS1);</div><div class='del'>-			if ((data &amp; LC_REVERSE_XMIT) &amp;&amp; (data &amp; LC_REVERSE_RCVR)) {</div><div class='del'>-				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);</div><div class='del'>-				data &amp;= ~LC_L0S_INACTIVITY_MASK;</div><div class='add'>+		data = RREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL);</div><div class='add'>+		if((data &amp; PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) {</div><div class='add'>+			data = RREG32_PCIE(ixPCIE_LC_STATUS1);</div><div class='add'>+			if ((data &amp; PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) &amp;&amp; (data &amp; PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {</div><div class='add'>+				orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL);</div><div class='add'>+				data &amp;= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;</div><div class='ctx'> 				if (orig != data)</div><div class='del'>-					WREG32_PCIE_PORT(PCIE_LC_CNTL, data);</div><div class='add'>+					WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2633,9 +2638,9 @@ static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)</div><div class='ctx'> 		pcie_set_readrq(adev-&gt;pdev, 512);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_hw_init(void *handle)</div><div class='add'>+static int si_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	si_fix_pci_max_read_req_size(adev);</div><div class='ctx'> 	si_init_golden_registers(adev);</div><div class='hunk'>@@ -2645,47 +2650,28 @@ static int si_common_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_hw_fini(void *handle)</div><div class='add'>+static int si_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_suspend(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return si_common_hw_fini(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int si_common_resume(void *handle)</div><div class='add'>+static int si_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return si_common_hw_init(adev);</div><div class='add'>+	return si_common_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool si_common_is_idle(void *handle)</div><div class='add'>+static bool si_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int si_common_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int si_common_set_clockgating_state(void *handle,</div><div class='add'>+static int si_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_common_set_powergating_state(void *handle,</div><div class='add'>+static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2694,16 +2680,10 @@ static int si_common_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs si_common_ip_funcs = {</div><div class='ctx'> 	.name = "si_common",</div><div class='ctx'> 	.early_init = si_common_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='del'>-	.sw_init = si_common_sw_init,</div><div class='del'>-	.sw_fini = si_common_sw_fini,</div><div class='ctx'> 	.hw_init = si_common_hw_init,</div><div class='ctx'> 	.hw_fini = si_common_hw_fini,</div><div class='del'>-	.suspend = si_common_suspend,</div><div class='ctx'> 	.resume = si_common_resume,</div><div class='ctx'> 	.is_idle = si_common_is_idle,</div><div class='del'>-	.wait_for_idle = si_common_wait_for_idle,</div><div class='del'>-	.soft_reset = si_common_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = si_common_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = si_common_set_powergating_state,</div><div class='ctx'> };</div><div class='hunk'>@@ -2738,7 +2718,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		else</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;dce_v6_0_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;uvd_v3_1_ip_block);</div><div class='del'>-		/* amdgpu_device_ip_block_add(adev, &amp;vce_v1_0_ip_block); */</div><div class='add'>+		amdgpu_device_ip_block_add(adev, &amp;vce_v1_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_OLAND:</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;si_common_ip_block);</div><div class='hunk'>@@ -2756,7 +2736,6 @@ int si_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		else</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;dce_v6_4_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;uvd_v3_1_ip_block);</div><div class='del'>-		/* amdgpu_device_ip_block_add(adev, &amp;vce_v1_0_ip_block); */</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CHIP_HAINAN:</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;si_common_ip_block);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c<br/>index 9aa0e11ee673..7f18e4875287 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si_dma.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si_dma.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si_dma.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/si_dma.c</a></div><div class='hunk'>@@ -27,6 +27,8 @@</div><div class='ctx'> #include "si.h"</div><div class='ctx'> #include "sid.h"</div><div class='ctx'> </div><div class='add'>+#include "oss/oss_1_0_d.h"</div><div class='add'>+#include "oss/oss_1_0_sh_mask.h"</div><div class='ctx'> const u32 sdma_offsets[SDMA_MAX_INSTANCE] =</div><div class='ctx'> {</div><div class='ctx'> 	DMA0_REGISTER_OFFSET,</div><div class='hunk'>@@ -38,17 +40,31 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void si_dma_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * si_dma_ring_get_rptr - get the current read pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Get the current rptr from the hardware (SI).</div><div class='add'>+ */</div><div class='ctx'> static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	return *ring-&gt;rptr_cpu_addr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * si_dma_ring_get_wptr - get the current write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Get the current wptr from the hardware (SI).</div><div class='add'>+ */</div><div class='ctx'> static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	u32 me = (ring == &amp;adev-&gt;sdma.instance[0].ring) ? 0 : 1;</div><div class='ctx'> </div><div class='del'>-	return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) &amp; 0x3fffc) &gt;&gt; 2;</div><div class='add'>+	return (RREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[me]) &amp; 0x3fffc) &gt;&gt; 2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='hunk'>@@ -56,7 +72,7 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	u32 me = (ring == &amp;adev-&gt;sdma.instance[0].ring) ? 0 : 1;</div><div class='ctx'> </div><div class='del'>-	WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring-&gt;wptr &lt;&lt; 2) &amp; 0x3fffc);</div><div class='add'>+	WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[me], (ring-&gt;wptr &lt;&lt; 2) &amp; 0x3fffc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='hunk'>@@ -117,9 +133,9 @@ static void si_dma_stop(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='ctx'> 		/* dma0 */</div><div class='del'>-		rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);</div><div class='del'>-		rb_cntl &amp;= ~DMA_RB_ENABLE;</div><div class='del'>-		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);</div><div class='add'>+		rb_cntl = RREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i]);</div><div class='add'>+		rb_cntl &amp;= ~DMA_GFX_RB_CNTL__RB_ENABLE_MASK;</div><div class='add'>+		WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -133,44 +149,44 @@ static int si_dma_start(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='ctx'> 		ring = &amp;adev-&gt;sdma.instance[i].ring;</div><div class='ctx'> </div><div class='del'>-		WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);</div><div class='del'>-		WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);</div><div class='add'>+		WREG32(mmDMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);</div><div class='add'>+		WREG32(mmDMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);</div><div class='ctx'> </div><div class='ctx'> 		/* Set ring buffer size in dwords */</div><div class='ctx'> 		rb_bufsz = order_base_2(ring-&gt;ring_size / 4);</div><div class='ctx'> 		rb_cntl = rb_bufsz &lt;&lt; 1;</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;</div><div class='add'>+		rb_cntl |= DMA_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | DMA_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;</div><div class='ctx'> #endif</div><div class='del'>-		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);</div><div class='ctx'> </div><div class='ctx'> 		/* Initialize the ring buffer's read and write pointers */</div><div class='del'>-		WREG32(DMA_RB_RPTR + sdma_offsets[i], 0);</div><div class='del'>-		WREG32(DMA_RB_WPTR + sdma_offsets[i], 0);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_RPTR + sdma_offsets[i], 0);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[i], 0);</div><div class='ctx'> </div><div class='ctx'> 		rptr_addr = ring-&gt;rptr_gpu_addr;</div><div class='ctx'> </div><div class='del'>-		WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));</div><div class='del'>-		WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) &amp; 0xFF);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));</div><div class='add'>+		WREG32(mmDMA_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) &amp; 0xFF);</div><div class='ctx'> </div><div class='del'>-		rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;</div><div class='add'>+		rb_cntl |= DMA_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;</div><div class='ctx'> </div><div class='del'>-		WREG32(DMA_RB_BASE + sdma_offsets[i], ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_BASE + sdma_offsets[i], ring-&gt;gpu_addr &gt;&gt; 8);</div><div class='ctx'> </div><div class='ctx'> 		/* enable DMA IBs */</div><div class='del'>-		ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;</div><div class='add'>+		ib_cntl = DMA_GFX_IB_CNTL__IB_ENABLE_MASK | DMA_GFX_IB_CNTL__CMD_VMID_FORCE_MASK;</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='del'>-		ib_cntl |= DMA_IB_SWAP_ENABLE;</div><div class='add'>+		ib_cntl |= DMA_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;</div><div class='ctx'> #endif</div><div class='del'>-		WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl);</div><div class='add'>+		WREG32(mmDMA_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);</div><div class='ctx'> </div><div class='del'>-		dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]);</div><div class='del'>-		dma_cntl &amp;= ~CTXEMPTY_INT_ENABLE;</div><div class='del'>-		WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl);</div><div class='add'>+		dma_cntl = RREG32(mmDMA_CNTL + sdma_offsets[i]);</div><div class='add'>+		dma_cntl &amp;= ~DMA_CNTL__CTXEMPTY_INT_ENABLE_MASK;</div><div class='add'>+		WREG32(mmDMA_CNTL + sdma_offsets[i], dma_cntl);</div><div class='ctx'> </div><div class='ctx'> 		ring-&gt;wptr = 0;</div><div class='del'>-		WREG32(DMA_RB_WPTR + sdma_offsets[i], ring-&gt;wptr &lt;&lt; 2);</div><div class='del'>-		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[i], ring-&gt;wptr &lt;&lt; 2);</div><div class='add'>+		WREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_GFX_RB_CNTL__RB_ENABLE_MASK);</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 		if (r)</div><div class='hunk'>@@ -286,7 +302,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		r = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> err1:</div><div class='del'>-	amdgpu_ib_free(adev, &amp;ib, NULL);</div><div class='add'>+	amdgpu_ib_free(&amp;ib, NULL);</div><div class='ctx'> 	dma_fence_put(f);</div><div class='ctx'> err0:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, index);</div><div class='hunk'>@@ -457,11 +473,11 @@ static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_write(ring, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_early_init(void *handle)</div><div class='add'>+static int si_dma_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;sdma.num_instances = 2;</div><div class='add'>+	adev-&gt;sdma.num_instances = SDMA_MAX_INSTANCE;</div><div class='ctx'> </div><div class='ctx'> 	si_dma_set_ring_funcs(adev);</div><div class='ctx'> 	si_dma_set_buffer_funcs(adev);</div><div class='hunk'>@@ -471,11 +487,11 @@ static int si_dma_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_sw_init(void *handle)</div><div class='add'>+static int si_dma_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* DMA0 trap event */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,</div><div class='hunk'>@@ -506,9 +522,9 @@ static int si_dma_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_sw_fini(void *handle)</div><div class='add'>+static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++)</div><div class='hunk'>@@ -517,61 +533,56 @@ static int si_dma_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_hw_init(void *handle)</div><div class='add'>+static int si_dma_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return si_dma_start(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_hw_fini(void *handle)</div><div class='add'>+static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	si_dma_stop(adev);</div><div class='add'>+	si_dma_stop(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_suspend(void *handle)</div><div class='add'>+static int si_dma_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return si_dma_hw_fini(adev);</div><div class='add'>+	return si_dma_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_resume(void *handle)</div><div class='add'>+static int si_dma_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return si_dma_hw_init(adev);</div><div class='add'>+	return si_dma_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool si_dma_is_idle(void *handle)</div><div class='add'>+static bool si_dma_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 tmp = RREG32(SRBM_STATUS2);</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	u32 tmp = RREG32(mmSRBM_STATUS2);</div><div class='ctx'> </div><div class='del'>-	if (tmp &amp; (DMA_BUSY_MASK | DMA1_BUSY_MASK))</div><div class='add'>+	if (tmp &amp; (SRBM_STATUS2__DMA_BUSY_MASK | SRBM_STATUS2__DMA1_BUSY_MASK))</div><div class='ctx'> 	    return false;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_wait_for_idle(void *handle)</div><div class='add'>+static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (si_dma_is_idle(handle))</div><div class='add'>+		if (si_dma_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_soft_reset(void *handle)</div><div class='add'>+static int si_dma_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n");</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -588,14 +599,14 @@ static int si_dma_set_trap_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 	case AMDGPU_SDMA_IRQ_INSTANCE0:</div><div class='ctx'> 		switch (state) {</div><div class='ctx'> 		case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-			sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);</div><div class='del'>-			sdma_cntl &amp;= ~TRAP_ENABLE;</div><div class='del'>-			WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);</div><div class='add'>+			sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);</div><div class='add'>+			sdma_cntl &amp;= ~DMA_CNTL__TRAP_ENABLE_MASK;</div><div class='add'>+			WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-			sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);</div><div class='del'>-			sdma_cntl |= TRAP_ENABLE;</div><div class='del'>-			WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);</div><div class='add'>+			sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);</div><div class='add'>+			sdma_cntl |= DMA_CNTL__TRAP_ENABLE_MASK;</div><div class='add'>+			WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -604,14 +615,14 @@ static int si_dma_set_trap_irq_state(struct amdgpu_device *adev,</div><div class='ctx'> 	case AMDGPU_SDMA_IRQ_INSTANCE1:</div><div class='ctx'> 		switch (state) {</div><div class='ctx'> 		case AMDGPU_IRQ_STATE_DISABLE:</div><div class='del'>-			sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);</div><div class='del'>-			sdma_cntl &amp;= ~TRAP_ENABLE;</div><div class='del'>-			WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);</div><div class='add'>+			sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);</div><div class='add'>+			sdma_cntl &amp;= ~DMA_CNTL__TRAP_ENABLE_MASK;</div><div class='add'>+			WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case AMDGPU_IRQ_STATE_ENABLE:</div><div class='del'>-			sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);</div><div class='del'>-			sdma_cntl |= TRAP_ENABLE;</div><div class='del'>-			WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);</div><div class='add'>+			sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);</div><div class='add'>+			sdma_cntl |= DMA_CNTL__TRAP_ENABLE_MASK;</div><div class='add'>+			WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -634,13 +645,13 @@ static int si_dma_process_trap_irq(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_set_clockgating_state(void *handle,</div><div class='add'>+static int si_dma_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	u32 orig, data, offset;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	bool enable;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> </div><div class='hunk'>@@ -650,11 +661,11 @@ static int si_dma_set_clockgating_state(void *handle,</div><div class='ctx'> 				offset = DMA0_REGISTER_OFFSET;</div><div class='ctx'> 			else</div><div class='ctx'> 				offset = DMA1_REGISTER_OFFSET;</div><div class='del'>-			orig = data = RREG32(DMA_POWER_CNTL + offset);</div><div class='del'>-			data &amp;= ~MEM_POWER_OVERRIDE;</div><div class='add'>+			orig = data = RREG32(mmDMA_POWER_CNTL + offset);</div><div class='add'>+			data &amp;= ~DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;</div><div class='ctx'> 			if (data != orig)</div><div class='del'>-				WREG32(DMA_POWER_CNTL + offset, data);</div><div class='del'>-			WREG32(DMA_CLK_CTRL + offset, 0x00000100);</div><div class='add'>+				WREG32(mmDMA_POWER_CNTL + offset, data);</div><div class='add'>+			WREG32(mmDMA_CLK_CTRL + offset, 0x00000100);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;sdma.num_instances; i++) {</div><div class='hunk'>@@ -662,33 +673,33 @@ static int si_dma_set_clockgating_state(void *handle,</div><div class='ctx'> 				offset = DMA0_REGISTER_OFFSET;</div><div class='ctx'> 			else</div><div class='ctx'> 				offset = DMA1_REGISTER_OFFSET;</div><div class='del'>-			orig = data = RREG32(DMA_POWER_CNTL + offset);</div><div class='del'>-			data |= MEM_POWER_OVERRIDE;</div><div class='add'>+			orig = data = RREG32(mmDMA_POWER_CNTL + offset);</div><div class='add'>+			data |= DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;</div><div class='ctx'> 			if (data != orig)</div><div class='del'>-				WREG32(DMA_POWER_CNTL + offset, data);</div><div class='add'>+				WREG32(mmDMA_POWER_CNTL + offset, data);</div><div class='ctx'> </div><div class='del'>-			orig = data = RREG32(DMA_CLK_CTRL + offset);</div><div class='add'>+			orig = data = RREG32(mmDMA_CLK_CTRL + offset);</div><div class='ctx'> 			data = 0xff000000;</div><div class='ctx'> 			if (data != orig)</div><div class='del'>-				WREG32(DMA_CLK_CTRL + offset, data);</div><div class='add'>+				WREG32(mmDMA_CLK_CTRL + offset, data);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_dma_set_powergating_state(void *handle,</div><div class='add'>+static int si_dma_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	WREG32(DMA_PGFSM_WRITE,  0x00002000);</div><div class='del'>-	WREG32(DMA_PGFSM_CONFIG, 0x100010ff);</div><div class='add'>+	WREG32(mmDMA_PGFSM_WRITE,  0x00002000);</div><div class='add'>+	WREG32(mmDMA_PGFSM_CONFIG, 0x100010ff);</div><div class='ctx'> </div><div class='ctx'> 	for (tmp = 0; tmp &lt; 5; tmp++)</div><div class='del'>-		WREG32(DMA_PGFSM_WRITE, 0);</div><div class='add'>+		WREG32(mmDMA_PGFSM_WRITE, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -696,7 +707,6 @@ static int si_dma_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs si_dma_ip_funcs = {</div><div class='ctx'> 	.name = "si_dma",</div><div class='ctx'> 	.early_init = si_dma_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = si_dma_sw_init,</div><div class='ctx'> 	.sw_fini = si_dma_sw_fini,</div><div class='ctx'> 	.hw_init = si_dma_hw_init,</div><div class='hunk'>@@ -761,7 +771,7 @@ static void si_dma_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'>  * @src_offset: src GPU address</div><div class='ctx'>  * @dst_offset: dst GPU address</div><div class='ctx'>  * @byte_count: number of bytes to xfer</div><div class='del'>- * @tmz: is this a secure operation</div><div class='add'>+ * @copy_flags: unused</div><div class='ctx'>  *</div><div class='ctx'>  * Copy GPU buffers using the DMA engine (VI).</div><div class='ctx'>  * Used by the amdgpu ttm implementation to move pages if</div><div class='hunk'>@@ -771,7 +781,7 @@ static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib,</div><div class='ctx'> 				       uint64_t src_offset,</div><div class='ctx'> 				       uint64_t dst_offset,</div><div class='ctx'> 				       uint32_t byte_count,</div><div class='del'>-				       bool tmz)</div><div class='add'>+				       uint32_t copy_flags)</div><div class='ctx'> {</div><div class='ctx'> 	ib-&gt;ptr[ib-&gt;length_dw++] = DMA_PACKET(DMA_PACKET_COPY,</div><div class='ctx'> 					      1, 0, 0, byte_count);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h<br/>index 4e935baa7b91..6da65778292b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si_enums.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si_enums.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si_enums.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/si_enums.h</a></div><div class='hunk'>@@ -23,123 +23,15 @@</div><div class='ctx'> #ifndef SI_ENUMS_H</div><div class='ctx'> #define SI_ENUMS_H</div><div class='ctx'> </div><div class='del'>-#define VBLANK_INT_MASK                (1 &lt;&lt; 0)</div><div class='del'>-#define DC_HPDx_INT_EN                 (1 &lt;&lt; 16)</div><div class='del'>-#define VBLANK_ACK                     (1 &lt;&lt; 4)</div><div class='del'>-#define VLINE_ACK                      (1 &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define CURSOR_WIDTH 64</div><div class='del'>-#define CURSOR_HEIGHT 64</div><div class='del'>-</div><div class='del'>-#define VGA_VSTATUS_CNTL               0xFFFCFFFF</div><div class='ctx'> #define PRIORITY_MARK_MASK             0x7fff</div><div class='ctx'> #define PRIORITY_OFF                   (1 &lt;&lt; 16)</div><div class='ctx'> #define PRIORITY_ALWAYS_ON             (1 &lt;&lt; 20)</div><div class='del'>-#define INTERLEAVE_EN                  (1 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-#define LATENCY_WATERMARK_MASK(x)      ((x) &lt;&lt; 16)</div><div class='del'>-#define DC_LB_MEMORY_CONFIG(x)         ((x) &lt;&lt; 20)</div><div class='del'>-#define ICON_DEGAMMA_MODE(x)           (((x) &amp; 0x3) &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define GRPH_ENDIAN_SWAP(x)            (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#define GRPH_ENDIAN_NONE               0</div><div class='del'>-#define GRPH_ENDIAN_8IN16              1</div><div class='del'>-#define GRPH_ENDIAN_8IN32              2</div><div class='del'>-#define GRPH_ENDIAN_8IN64              3</div><div class='del'>-#define GRPH_RED_CROSSBAR(x)           (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-#define GRPH_RED_SEL_R                 0</div><div class='del'>-#define GRPH_RED_SEL_G                 1</div><div class='del'>-#define GRPH_RED_SEL_B                 2</div><div class='del'>-#define GRPH_RED_SEL_A                 3</div><div class='del'>-#define GRPH_GREEN_CROSSBAR(x)         (((x) &amp; 0x3) &lt;&lt; 6)</div><div class='del'>-#define GRPH_GREEN_SEL_G               0</div><div class='del'>-#define GRPH_GREEN_SEL_B               1</div><div class='del'>-#define GRPH_GREEN_SEL_A               2</div><div class='del'>-#define GRPH_GREEN_SEL_R               3</div><div class='del'>-#define GRPH_BLUE_CROSSBAR(x)          (((x) &amp; 0x3) &lt;&lt; 8)</div><div class='del'>-#define GRPH_BLUE_SEL_B                0</div><div class='del'>-#define GRPH_BLUE_SEL_A                1</div><div class='del'>-#define GRPH_BLUE_SEL_R                2</div><div class='del'>-#define GRPH_BLUE_SEL_G                3</div><div class='del'>-#define GRPH_ALPHA_CROSSBAR(x)         (((x) &amp; 0x3) &lt;&lt; 10)</div><div class='del'>-#define GRPH_ALPHA_SEL_A               0</div><div class='del'>-#define GRPH_ALPHA_SEL_R               1</div><div class='del'>-#define GRPH_ALPHA_SEL_G               2</div><div class='del'>-#define GRPH_ALPHA_SEL_B               3</div><div class='del'>-</div><div class='del'>-#define GRPH_DEPTH(x)                  (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#define GRPH_DEPTH_8BPP                0</div><div class='del'>-#define GRPH_DEPTH_16BPP               1</div><div class='del'>-#define GRPH_DEPTH_32BPP               2</div><div class='del'>-</div><div class='del'>-#define GRPH_FORMAT(x)                 (((x) &amp; 0x7) &lt;&lt; 8)</div><div class='del'>-#define GRPH_FORMAT_INDEXED            0</div><div class='del'>-#define GRPH_FORMAT_ARGB1555           0</div><div class='del'>-#define GRPH_FORMAT_ARGB565            1</div><div class='del'>-#define GRPH_FORMAT_ARGB4444           2</div><div class='del'>-#define GRPH_FORMAT_AI88               3</div><div class='del'>-#define GRPH_FORMAT_MONO16             4</div><div class='del'>-#define GRPH_FORMAT_BGRA5551           5</div><div class='del'>-#define GRPH_FORMAT_ARGB8888           0</div><div class='del'>-#define GRPH_FORMAT_ARGB2101010        1</div><div class='del'>-#define GRPH_FORMAT_32BPP_DIG          2</div><div class='del'>-#define GRPH_FORMAT_8B_ARGB2101010     3</div><div class='del'>-#define GRPH_FORMAT_BGRA1010102        4</div><div class='del'>-#define GRPH_FORMAT_8B_BGRA1010102     5</div><div class='del'>-#define GRPH_FORMAT_RGB111110          6</div><div class='del'>-#define GRPH_FORMAT_BGR101111          7</div><div class='del'>-</div><div class='del'>-#define GRPH_NUM_BANKS(x)              (((x) &amp; 0x3) &lt;&lt; 2)</div><div class='del'>-#define GRPH_ARRAY_MODE(x)             (((x) &amp; 0x7) &lt;&lt; 20)</div><div class='del'>-#define GRPH_ARRAY_LINEAR_GENERAL      0</div><div class='del'>-#define GRPH_ARRAY_LINEAR_ALIGNED      1</div><div class='del'>-#define GRPH_ARRAY_1D_TILED_THIN1      2</div><div class='del'>-#define GRPH_ARRAY_2D_TILED_THIN1      4</div><div class='del'>-#define GRPH_TILE_SPLIT(x)             (((x) &amp; 0x7) &lt;&lt; 13)</div><div class='del'>-#define GRPH_BANK_WIDTH(x)             (((x) &amp; 0x3) &lt;&lt; 6)</div><div class='del'>-#define GRPH_BANK_HEIGHT(x)            (((x) &amp; 0x3) &lt;&lt; 11)</div><div class='del'>-#define GRPH_MACRO_TILE_ASPECT(x)      (((x) &amp; 0x3) &lt;&lt; 18)</div><div class='del'>-#define GRPH_ARRAY_MODE(x)             (((x) &amp; 0x7) &lt;&lt; 20)</div><div class='del'>-#define GRPH_PIPE_CONFIG(x)                   (((x) &amp; 0x1f) &lt;&lt; 24)</div><div class='del'>-</div><div class='del'>-#define CURSOR_EN                      (1 &lt;&lt; 0)</div><div class='del'>-#define CURSOR_MODE(x)                 (((x) &amp; 0x3) &lt;&lt; 8)</div><div class='del'>-#define CURSOR_MONO                    0</div><div class='del'>-#define CURSOR_24_1                    1</div><div class='del'>-#define CURSOR_24_8_PRE_MULT           2</div><div class='del'>-#define CURSOR_24_8_UNPRE_MULT         3</div><div class='del'>-#define CURSOR_2X_MAGNIFY              (1 &lt;&lt; 16)</div><div class='del'>-#define CURSOR_FORCE_MC_ON             (1 &lt;&lt; 20)</div><div class='del'>-#define CURSOR_URGENT_CONTROL(x)       (((x) &amp; 0x7) &lt;&lt; 24)</div><div class='del'>-#define CURSOR_URGENT_ALWAYS           0</div><div class='del'>-#define CURSOR_URGENT_1_8              1</div><div class='del'>-#define CURSOR_URGENT_1_4              2</div><div class='del'>-#define CURSOR_URGENT_3_8              3</div><div class='del'>-#define CURSOR_URGENT_1_2              4</div><div class='del'>-#define CURSOR_UPDATE_PENDING          (1 &lt;&lt; 0)</div><div class='del'>-#define CURSOR_UPDATE_TAKEN            (1 &lt;&lt; 1)</div><div class='del'>-#define CURSOR_UPDATE_LOCK             (1 &lt;&lt; 16)</div><div class='del'>-#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 &lt;&lt; 24)</div><div class='del'>-</div><div class='del'>-#define SI_CRTC0_REGISTER_OFFSET                0</div><div class='del'>-#define SI_CRTC1_REGISTER_OFFSET                0x300</div><div class='del'>-#define SI_CRTC2_REGISTER_OFFSET                0x2600</div><div class='del'>-#define SI_CRTC3_REGISTER_OFFSET                0x2900</div><div class='del'>-#define SI_CRTC4_REGISTER_OFFSET                0x2c00</div><div class='del'>-#define SI_CRTC5_REGISTER_OFFSET                0x2f00</div><div class='del'>-</div><div class='del'>-#define DMA0_REGISTER_OFFSET 0x000</div><div class='del'>-#define DMA1_REGISTER_OFFSET 0x200</div><div class='del'>-#define ES_AND_GS_AUTO       3</div><div class='del'>-#define RADEON_PACKET_TYPE3  3</div><div class='del'>-#define CE_PARTITION_BASE    3</div><div class='del'>-#define BUF_SWAP_32BIT       (2 &lt;&lt; 16)</div><div class='ctx'> </div><div class='ctx'> #define GFX_POWER_STATUS                           (1 &lt;&lt; 1)</div><div class='ctx'> #define GFX_CLOCK_STATUS                           (1 &lt;&lt; 2)</div><div class='ctx'> #define GFX_LS_STATUS                              (1 &lt;&lt; 3)</div><div class='del'>-#define RLC_BUSY_STATUS                            (1 &lt;&lt; 0)</div><div class='ctx'> </div><div class='add'>+#define RLC_BUSY_STATUS                            (1 &lt;&lt; 0)</div><div class='ctx'> #define RLC_PUD(x)                               ((x) &lt;&lt; 0)</div><div class='ctx'> #define RLC_PUD_MASK                             (0xff &lt;&lt; 0)</div><div class='ctx'> #define RLC_PDD(x)                               ((x) &lt;&lt; 8)</div><div class='hunk'>@@ -148,144 +40,8 @@</div><div class='ctx'> #define RLC_TTPD_MASK                            (0xff &lt;&lt; 16)</div><div class='ctx'> #define RLC_MSD(x)                               ((x) &lt;&lt; 24)</div><div class='ctx'> #define RLC_MSD_MASK                             (0xff &lt;&lt; 24)</div><div class='del'>-#define WRITE_DATA_ENGINE_SEL(x) ((x) &lt;&lt; 30)</div><div class='del'>-#define WRITE_DATA_DST_SEL(x) ((x) &lt;&lt; 8)</div><div class='del'>-#define EVENT_TYPE(x) ((x) &lt;&lt; 0)</div><div class='del'>-#define EVENT_INDEX(x) ((x) &lt;&lt; 8)</div><div class='del'>-#define WAIT_REG_MEM_MEM_SPACE(x)               ((x) &lt;&lt; 4)</div><div class='del'>-#define WAIT_REG_MEM_FUNCTION(x)                ((x) &lt;&lt; 0)</div><div class='del'>-#define WAIT_REG_MEM_ENGINE(x)                  ((x) &lt;&lt; 8)</div><div class='ctx'> </div><div class='del'>-#define GFX6_NUM_GFX_RINGS     1</div><div class='del'>-#define GFX6_NUM_COMPUTE_RINGS 2</div><div class='ctx'> #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90</div><div class='ctx'> #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D</div><div class='ctx'> </div><div class='del'>-#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003</div><div class='del'>-#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x02010002</div><div class='del'>-#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02011003</div><div class='del'>-</div><div class='del'>-#define PACKET3(op, n)  ((RADEON_PACKET_TYPE3 &lt;&lt; 30) |                  \</div><div class='del'>-                         (((op) &amp; 0xFF) &lt;&lt; 8) |                         \</div><div class='del'>-                         ((n) &amp; 0x3FFF) &lt;&lt; 16)</div><div class='del'>-#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 &lt;&lt; 1)</div><div class='del'>-#define	PACKET3_NOP					0x10</div><div class='del'>-#define	PACKET3_SET_BASE				0x11</div><div class='del'>-#define		PACKET3_BASE_INDEX(x)                  ((x) &lt;&lt; 0)</div><div class='del'>-#define	PACKET3_CLEAR_STATE				0x12</div><div class='del'>-#define	PACKET3_INDEX_BUFFER_SIZE			0x13</div><div class='del'>-#define	PACKET3_DISPATCH_DIRECT				0x15</div><div class='del'>-#define	PACKET3_DISPATCH_INDIRECT			0x16</div><div class='del'>-#define	PACKET3_ALLOC_GDS				0x1B</div><div class='del'>-#define	PACKET3_WRITE_GDS_RAM				0x1C</div><div class='del'>-#define	PACKET3_ATOMIC_GDS				0x1D</div><div class='del'>-#define	PACKET3_ATOMIC					0x1E</div><div class='del'>-#define	PACKET3_OCCLUSION_QUERY				0x1F</div><div class='del'>-#define	PACKET3_SET_PREDICATION				0x20</div><div class='del'>-#define	PACKET3_REG_RMW					0x21</div><div class='del'>-#define	PACKET3_COND_EXEC				0x22</div><div class='del'>-#define	PACKET3_PRED_EXEC				0x23</div><div class='del'>-#define	PACKET3_DRAW_INDIRECT				0x24</div><div class='del'>-#define	PACKET3_DRAW_INDEX_INDIRECT			0x25</div><div class='del'>-#define	PACKET3_INDEX_BASE				0x26</div><div class='del'>-#define	PACKET3_DRAW_INDEX_2				0x27</div><div class='del'>-#define	PACKET3_CONTEXT_CONTROL				0x28</div><div class='del'>-#define	PACKET3_INDEX_TYPE				0x2A</div><div class='del'>-#define	PACKET3_DRAW_INDIRECT_MULTI			0x2C</div><div class='del'>-#define	PACKET3_DRAW_INDEX_AUTO				0x2D</div><div class='del'>-#define	PACKET3_DRAW_INDEX_IMMD				0x2E</div><div class='del'>-#define	PACKET3_NUM_INSTANCES				0x2F</div><div class='del'>-#define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30</div><div class='del'>-#define	PACKET3_INDIRECT_BUFFER_CONST			0x31</div><div class='del'>-#define	PACKET3_INDIRECT_BUFFER				0x3F</div><div class='del'>-#define	PACKET3_STRMOUT_BUFFER_UPDATE			0x34</div><div class='del'>-#define	PACKET3_DRAW_INDEX_OFFSET_2			0x35</div><div class='del'>-#define	PACKET3_DRAW_INDEX_MULTI_ELEMENT		0x36</div><div class='del'>-#define	PACKET3_WRITE_DATA				0x37</div><div class='del'>-#define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38</div><div class='del'>-#define	PACKET3_MEM_SEMAPHORE				0x39</div><div class='del'>-#define	PACKET3_MPEG_INDEX				0x3A</div><div class='del'>-#define	PACKET3_COPY_DW					0x3B</div><div class='del'>-#define	PACKET3_WAIT_REG_MEM				0x3C</div><div class='del'>-#define	PACKET3_MEM_WRITE				0x3D</div><div class='del'>-#define	PACKET3_COPY_DATA				0x40</div><div class='del'>-#define	PACKET3_CP_DMA					0x41</div><div class='del'>-#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) &lt;&lt; 20)</div><div class='del'>-#              define PACKET3_CP_DMA_ENGINE(x)     ((x) &lt;&lt; 27)</div><div class='del'>-#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) &lt;&lt; 29)</div><div class='del'>-#              define PACKET3_CP_DMA_CP_SYNC       (1 &lt;&lt; 31)</div><div class='del'>-#              define PACKET3_CP_DMA_DIS_WC        (1 &lt;&lt; 21)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) &lt;&lt; 22)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) &lt;&lt; 24)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_SAS       (1 &lt;&lt; 26)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_DAS       (1 &lt;&lt; 27)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_SAIC      (1 &lt;&lt; 28)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_DAIC      (1 &lt;&lt; 29)</div><div class='del'>-#              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 &lt;&lt; 30)</div><div class='del'>-#define	PACKET3_PFP_SYNC_ME				0x42</div><div class='del'>-#define	PACKET3_SURFACE_SYNC				0x43</div><div class='del'>-#              define PACKET3_DEST_BASE_0_ENA      (1 &lt;&lt; 0)</div><div class='del'>-#              define PACKET3_DEST_BASE_1_ENA      (1 &lt;&lt; 1)</div><div class='del'>-#              define PACKET3_CB0_DEST_BASE_ENA    (1 &lt;&lt; 6)</div><div class='del'>-#              define PACKET3_CB1_DEST_BASE_ENA    (1 &lt;&lt; 7)</div><div class='del'>-#              define PACKET3_CB2_DEST_BASE_ENA    (1 &lt;&lt; 8)</div><div class='del'>-#              define PACKET3_CB3_DEST_BASE_ENA    (1 &lt;&lt; 9)</div><div class='del'>-#              define PACKET3_CB4_DEST_BASE_ENA    (1 &lt;&lt; 10)</div><div class='del'>-#              define PACKET3_CB5_DEST_BASE_ENA    (1 &lt;&lt; 11)</div><div class='del'>-#              define PACKET3_CB6_DEST_BASE_ENA    (1 &lt;&lt; 12)</div><div class='del'>-#              define PACKET3_CB7_DEST_BASE_ENA    (1 &lt;&lt; 13)</div><div class='del'>-#              define PACKET3_DB_DEST_BASE_ENA     (1 &lt;&lt; 14)</div><div class='del'>-#              define PACKET3_DEST_BASE_2_ENA      (1 &lt;&lt; 19)</div><div class='del'>-#              define PACKET3_DEST_BASE_3_ENA      (1 &lt;&lt; 21)</div><div class='del'>-#              define PACKET3_TCL1_ACTION_ENA      (1 &lt;&lt; 22)</div><div class='del'>-#              define PACKET3_TC_ACTION_ENA        (1 &lt;&lt; 23)</div><div class='del'>-#              define PACKET3_CB_ACTION_ENA        (1 &lt;&lt; 25)</div><div class='del'>-#              define PACKET3_DB_ACTION_ENA        (1 &lt;&lt; 26)</div><div class='del'>-#              define PACKET3_SH_KCACHE_ACTION_ENA (1 &lt;&lt; 27)</div><div class='del'>-#              define PACKET3_SH_ICACHE_ACTION_ENA (1 &lt;&lt; 29)</div><div class='del'>-#define	PACKET3_ME_INITIALIZE				0x44</div><div class='del'>-#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) &lt;&lt; 16)</div><div class='del'>-#define	PACKET3_COND_WRITE				0x45</div><div class='del'>-#define	PACKET3_EVENT_WRITE				0x46</div><div class='del'>-#define	PACKET3_EVENT_WRITE_EOP				0x47</div><div class='del'>-#define	PACKET3_EVENT_WRITE_EOS				0x48</div><div class='del'>-#define	PACKET3_PREAMBLE_CNTL				0x4A</div><div class='del'>-#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 &lt;&lt; 28)</div><div class='del'>-#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 &lt;&lt; 28)</div><div class='del'>-#define	PACKET3_ONE_REG_WRITE				0x57</div><div class='del'>-#define	PACKET3_LOAD_CONFIG_REG				0x5F</div><div class='del'>-#define	PACKET3_LOAD_CONTEXT_REG			0x60</div><div class='del'>-#define	PACKET3_LOAD_SH_REG				0x61</div><div class='del'>-#define	PACKET3_SET_CONFIG_REG				0x68</div><div class='del'>-#define		PACKET3_SET_CONFIG_REG_START			0x00002000</div><div class='del'>-#define		PACKET3_SET_CONFIG_REG_END			0x00002c00</div><div class='del'>-#define	PACKET3_SET_CONTEXT_REG				0x69</div><div class='del'>-#define		PACKET3_SET_CONTEXT_REG_START			0x000a000</div><div class='del'>-#define		PACKET3_SET_CONTEXT_REG_END			0x000a400</div><div class='del'>-#define	PACKET3_SET_CONTEXT_REG_INDIRECT		0x73</div><div class='del'>-#define	PACKET3_SET_RESOURCE_INDIRECT			0x74</div><div class='del'>-#define	PACKET3_SET_SH_REG				0x76</div><div class='del'>-#define		PACKET3_SET_SH_REG_START			0x00002c00</div><div class='del'>-#define		PACKET3_SET_SH_REG_END				0x00003000</div><div class='del'>-#define	PACKET3_SET_SH_REG_OFFSET			0x77</div><div class='del'>-#define	PACKET3_ME_WRITE				0x7A</div><div class='del'>-#define	PACKET3_SCRATCH_RAM_WRITE			0x7D</div><div class='del'>-#define	PACKET3_SCRATCH_RAM_READ			0x7E</div><div class='del'>-#define	PACKET3_CE_WRITE				0x7F</div><div class='del'>-#define	PACKET3_LOAD_CONST_RAM				0x80</div><div class='del'>-#define	PACKET3_WRITE_CONST_RAM				0x81</div><div class='del'>-#define	PACKET3_WRITE_CONST_RAM_OFFSET			0x82</div><div class='del'>-#define	PACKET3_DUMP_CONST_RAM				0x83</div><div class='del'>-#define	PACKET3_INCREMENT_CE_COUNTER			0x84</div><div class='del'>-#define	PACKET3_INCREMENT_DE_COUNTER			0x85</div><div class='del'>-#define	PACKET3_WAIT_ON_CE_COUNTER			0x86</div><div class='del'>-#define	PACKET3_WAIT_ON_DE_COUNTER			0x87</div><div class='del'>-#define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88</div><div class='del'>-#define	PACKET3_SET_CE_DE_COUNTERS			0x89</div><div class='del'>-#define	PACKET3_WAIT_ON_AVAIL_BUFFER			0x8A</div><div class='del'>-#define	PACKET3_SWITCH_BUFFER				0x8B</div><div class='del'>-#define PACKET3_SEM_WAIT_ON_SIGNAL    (0x1 &lt;&lt; 12)</div><div class='del'>-#define PACKET3_SEM_SEL_SIGNAL	    (0x6 &lt;&lt; 29)</div><div class='del'>-#define PACKET3_SEM_SEL_WAIT	    (0x7 &lt;&lt; 29)</div><div class='del'>-</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c<br/>index cada9f300a7f..66f650f87243 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/si_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/si_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/si_ih.c</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> #include "amdgpu_ih.h"</div><div class='ctx'> #include "sid.h"</div><div class='ctx'> #include "si_ih.h"</div><div class='add'>+</div><div class='ctx'> #include "oss/oss_1_0_d.h"</div><div class='ctx'> #include "oss/oss_1_0_sh_mask.h"</div><div class='ctx'> </div><div class='hunk'>@@ -95,6 +96,9 @@ static int si_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	pci_set_master(adev-&gt;pdev);</div><div class='ctx'> 	si_ih_enable_interrupts(adev);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;irq.ih_soft.ring_size)</div><div class='add'>+		adev-&gt;irq.ih_soft.enabled = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -111,6 +115,9 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	wptr = le32_to_cpu(*ih-&gt;wptr_cpu);</div><div class='ctx'> </div><div class='add'>+	if (ih == &amp;adev-&gt;irq.ih_soft)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	if (wptr &amp; IH_RB_WPTR__RB_OVERFLOW_MASK) {</div><div class='ctx'> 		wptr &amp;= ~IH_RB_WPTR__RB_OVERFLOW_MASK;</div><div class='ctx'> 		dev_warn(adev-&gt;dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",</div><div class='hunk'>@@ -126,6 +133,8 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> 		tmp &amp;= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;</div><div class='ctx'> 		WREG32(IH_RB_CNTL, tmp);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='ctx'> 	return (wptr &amp; ih-&gt;ptr_mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -156,70 +165,68 @@ static void si_ih_set_rptr(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32(IH_RB_RPTR, ih-&gt;rptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_early_init(void *handle)</div><div class='add'>+static int si_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	si_ih_set_interrupt_funcs(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_sw_init(void *handle)</div><div class='add'>+static int si_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 64 * 1024, false);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih_soft, IH_SW_RING_SIZE, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return amdgpu_irq_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_sw_fini(void *handle)</div><div class='add'>+static int si_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_hw_init(void *handle)</div><div class='add'>+static int si_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return si_ih_irq_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_hw_fini(void *handle)</div><div class='add'>+static int si_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	si_ih_irq_disable(adev);</div><div class='add'>+	si_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_suspend(void *handle)</div><div class='add'>+static int si_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return si_ih_hw_fini(adev);</div><div class='add'>+	return si_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_resume(void *handle)</div><div class='add'>+static int si_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return si_ih_hw_init(adev);</div><div class='add'>+	return si_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool si_ih_is_idle(void *handle)</div><div class='add'>+static bool si_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 tmp = RREG32(SRBM_STATUS);</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS__IH_BUSY_MASK)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -227,41 +234,41 @@ static bool si_ih_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_wait_for_idle(void *handle)</div><div class='add'>+static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (si_ih_is_idle(handle))</div><div class='add'>+		if (si_ih_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_soft_reset(void *handle)</div><div class='add'>+static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='del'>-	u32 tmp = RREG32(SRBM_STATUS);</div><div class='add'>+	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (tmp &amp; SRBM_STATUS__IH_BUSY_MASK)</div><div class='ctx'> 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;</div><div class='ctx'> </div><div class='ctx'> 	if (srbm_soft_reset) {</div><div class='del'>-		tmp = RREG32(SRBM_SOFT_RESET);</div><div class='add'>+		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='ctx'> 		tmp |= srbm_soft_reset;</div><div class='del'>-		dev_info(adev-&gt;dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-		WREG32(SRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(SRBM_SOFT_RESET);</div><div class='add'>+		dev_info(adev-&gt;dev, "mmSRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='add'>+		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='ctx'> 		udelay(50);</div><div class='ctx'> </div><div class='ctx'> 		tmp &amp;= ~srbm_soft_reset;</div><div class='del'>-		WREG32(SRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(SRBM_SOFT_RESET);</div><div class='add'>+		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='add'>+		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='ctx'> </div><div class='ctx'> 		udelay(50);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -269,13 +276,13 @@ static int si_ih_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int si_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int si_ih_set_powergating_state(void *handle,</div><div class='add'>+static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -284,7 +291,6 @@ static int si_ih_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs si_ih_ip_funcs = {</div><div class='ctx'> 	.name = "si_ih",</div><div class='ctx'> 	.early_init = si_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = si_ih_sw_init,</div><div class='ctx'> 	.sw_fini = si_ih_sw_fini,</div><div class='ctx'> 	.hw_init = si_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h<br/>index 9a39cbfe6db9..561462a8332e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sid.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sid.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sid.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sid.h</a></div><div class='hunk'>@@ -24,47 +24,12 @@</div><div class='ctx'> #ifndef SI_H</div><div class='ctx'> #define SI_H</div><div class='ctx'> </div><div class='del'>-#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2</div><div class='del'>-</div><div class='del'>-#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003</div><div class='del'>-#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002</div><div class='del'>-#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001</div><div class='del'>-</div><div class='del'>-#define SI_MAX_SH_GPRS		 	256</div><div class='del'>-#define SI_MAX_TEMP_GPRS         	16</div><div class='del'>-#define SI_MAX_SH_THREADS        	256</div><div class='del'>-#define SI_MAX_SH_STACK_ENTRIES  	4096</div><div class='del'>-#define SI_MAX_FRC_EOV_CNT       	16384</div><div class='del'>-#define SI_MAX_BACKENDS          	8</div><div class='del'>-#define SI_MAX_BACKENDS_MASK     	0xFF</div><div class='del'>-#define SI_MAX_BACKENDS_PER_SE_MASK     0x0F</div><div class='del'>-#define SI_MAX_SIMDS             	12</div><div class='del'>-#define SI_MAX_SIMDS_MASK        	0x0FFF</div><div class='del'>-#define SI_MAX_SIMDS_PER_SE_MASK        0x00FF</div><div class='del'>-#define SI_MAX_PIPES            	8</div><div class='del'>-#define SI_MAX_PIPES_MASK        	0xFF</div><div class='del'>-#define SI_MAX_PIPES_PER_SIMD_MASK      0x3F</div><div class='del'>-#define SI_MAX_LDS_NUM           	0xFFFF</div><div class='del'>-#define SI_MAX_TCC               	16</div><div class='del'>-#define SI_MAX_TCC_MASK          	0xFFFF</div><div class='ctx'> #define SI_MAX_CTLACKS_ASSERTION_WAIT   100</div><div class='ctx'> </div><div class='del'>-/* SMC IND accessor regs */</div><div class='del'>-#define SMC_IND_INDEX_0                              0x80</div><div class='del'>-#define SMC_IND_DATA_0                               0x81</div><div class='del'>-</div><div class='del'>-#define SMC_IND_ACCESS_CNTL                          0x8A</div><div class='del'>-#       define AUTO_INCREMENT_IND_0                  (1 &lt;&lt; 0)</div><div class='del'>-#define SMC_MESSAGE_0                                0x8B</div><div class='del'>-#define SMC_RESP_0                                   0x8C</div><div class='del'>-</div><div class='ctx'> /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */</div><div class='ctx'> #define SMC_CG_IND_START                    0xc0030000</div><div class='ctx'> #define SMC_CG_IND_END                      0xc0040000</div><div class='ctx'> </div><div class='del'>-#define	CG_CGTT_LOCAL_0				0x400</div><div class='del'>-#define	CG_CGTT_LOCAL_1				0x401</div><div class='del'>-</div><div class='ctx'> /* SMC IND registers */</div><div class='ctx'> #define	SMC_SYSCON_RESET_CNTL				0x80000000</div><div class='ctx'> #       define RST_REG                                  (1 &lt;&lt; 0)</div><div class='hunk'>@@ -72,9 +37,6 @@</div><div class='ctx'> #       define CK_DISABLE                               (1 &lt;&lt; 0)</div><div class='ctx'> #       define CKEN                                     (1 &lt;&lt; 24)</div><div class='ctx'> </div><div class='del'>-#define VGA_HDP_CONTROL  				0xCA</div><div class='del'>-#define		VGA_MEMORY_DISABLE				(1 &lt;&lt; 4)</div><div class='del'>-</div><div class='ctx'> #define DCCG_DISP_SLOW_SELECT_REG                       0x13F</div><div class='ctx'> #define		DCCG_DISP1_SLOW_SELECT(x)		((x) &lt;&lt; 0)</div><div class='ctx'> #define		DCCG_DISP1_SLOW_SELECT_MASK		(7 &lt;&lt; 0)</div><div class='hunk'>@@ -83,47 +45,6 @@</div><div class='ctx'> #define		DCCG_DISP2_SLOW_SELECT_MASK		(7 &lt;&lt; 4)</div><div class='ctx'> #define		DCCG_DISP2_SLOW_SELECT_SHIFT		4</div><div class='ctx'> </div><div class='del'>-#define	CG_SPLL_FUNC_CNTL				0x180</div><div class='del'>-#define		SPLL_RESET				(1 &lt;&lt; 0)</div><div class='del'>-#define		SPLL_SLEEP				(1 &lt;&lt; 1)</div><div class='del'>-#define		SPLL_BYPASS_EN				(1 &lt;&lt; 3)</div><div class='del'>-#define		SPLL_REF_DIV(x)				((x) &lt;&lt; 4)</div><div class='del'>-#define		SPLL_REF_DIV_MASK			(0x3f &lt;&lt; 4)</div><div class='del'>-#define		SPLL_PDIV_A(x)				((x) &lt;&lt; 20)</div><div class='del'>-#define		SPLL_PDIV_A_MASK			(0x7f &lt;&lt; 20)</div><div class='del'>-#define		SPLL_PDIV_A_SHIFT			20</div><div class='del'>-#define	CG_SPLL_FUNC_CNTL_2				0x181</div><div class='del'>-#define		SCLK_MUX_SEL(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		SCLK_MUX_SEL_MASK			(0x1ff &lt;&lt; 0)</div><div class='del'>-#define		SPLL_CTLREQ_CHG				(1 &lt;&lt; 23)</div><div class='del'>-#define		SCLK_MUX_UPDATE				(1 &lt;&lt; 26)</div><div class='del'>-#define	CG_SPLL_FUNC_CNTL_3				0x182</div><div class='del'>-#define		SPLL_FB_DIV(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		SPLL_FB_DIV_MASK			(0x3ffffff &lt;&lt; 0)</div><div class='del'>-#define		SPLL_FB_DIV_SHIFT			0</div><div class='del'>-#define		SPLL_DITHEN				(1 &lt;&lt; 28)</div><div class='del'>-#define	CG_SPLL_FUNC_CNTL_4				0x183</div><div class='del'>-</div><div class='del'>-#define	SPLL_STATUS					0x185</div><div class='del'>-#define		SPLL_CHG_STATUS				(1 &lt;&lt; 1)</div><div class='del'>-#define	SPLL_CNTL_MODE					0x186</div><div class='del'>-#define		SPLL_SW_DIR_CONTROL			(1 &lt;&lt; 0)</div><div class='del'>-#	define SPLL_REFCLK_SEL(x)			((x) &lt;&lt; 26)</div><div class='del'>-#	define SPLL_REFCLK_SEL_MASK			(3 &lt;&lt; 26)</div><div class='del'>-</div><div class='del'>-#define	CG_SPLL_SPREAD_SPECTRUM				0x188</div><div class='del'>-#define		SSEN					(1 &lt;&lt; 0)</div><div class='del'>-#define		CLK_S(x)				((x) &lt;&lt; 4)</div><div class='del'>-#define		CLK_S_MASK				(0xfff &lt;&lt; 4)</div><div class='del'>-#define		CLK_S_SHIFT				4</div><div class='del'>-#define	CG_SPLL_SPREAD_SPECTRUM_2			0x189</div><div class='del'>-#define		CLK_V(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		CLK_V_MASK				(0x3ffffff &lt;&lt; 0)</div><div class='del'>-#define		CLK_V_SHIFT				0</div><div class='del'>-</div><div class='del'>-#define	CG_SPLL_AUTOSCALE_CNTL				0x18b</div><div class='del'>-#       define AUTOSCALE_ON_SS_CLEAR                    (1 &lt;&lt; 9)</div><div class='del'>-</div><div class='ctx'> /* discrete uvd clocks */</div><div class='ctx'> #define	CG_UPLL_FUNC_CNTL				0x18d</div><div class='ctx'> #	define UPLL_RESET_MASK				0x00000001</div><div class='hunk'>@@ -153,317 +74,13 @@</div><div class='ctx'> #define	CG_UPLL_SPREAD_SPECTRUM				0x194</div><div class='ctx'> #	define SSEN_MASK				0x00000001</div><div class='ctx'> </div><div class='del'>-#define	MPLL_BYPASSCLK_SEL				0x197</div><div class='del'>-#	define MPLL_CLKOUT_SEL(x)			((x) &lt;&lt; 8)</div><div class='del'>-#	define MPLL_CLKOUT_SEL_MASK			0xFF00</div><div class='del'>-</div><div class='del'>-#define CG_CLKPIN_CNTL                                    0x198</div><div class='del'>-#       define XTALIN_DIVIDE                              (1 &lt;&lt; 1)</div><div class='del'>-#       define BCLK_AS_XCLK                               (1 &lt;&lt; 2)</div><div class='del'>-#define CG_CLKPIN_CNTL_2                                  0x199</div><div class='del'>-#       define FORCE_BIF_REFCLK_EN                        (1 &lt;&lt; 3)</div><div class='del'>-#       define MUX_TCLK_TO_XCLK                           (1 &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define	THM_CLK_CNTL					0x19b</div><div class='del'>-#	define CMON_CLK_SEL(x)				((x) &lt;&lt; 0)</div><div class='del'>-#	define CMON_CLK_SEL_MASK			0xFF</div><div class='del'>-#	define TMON_CLK_SEL(x)				((x) &lt;&lt; 8)</div><div class='del'>-#	define TMON_CLK_SEL_MASK			0xFF00</div><div class='del'>-#define	MISC_CLK_CNTL					0x19c</div><div class='del'>-#	define DEEP_SLEEP_CLK_SEL(x)			((x) &lt;&lt; 0)</div><div class='del'>-#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF</div><div class='del'>-#	define ZCLK_SEL(x)				((x) &lt;&lt; 8)</div><div class='del'>-#	define ZCLK_SEL_MASK				0xFF00</div><div class='del'>-</div><div class='del'>-#define	CG_THERMAL_CTRL					0x1c0</div><div class='del'>-#define 	DPM_EVENT_SRC(x)			((x) &lt;&lt; 0)</div><div class='del'>-#define 	DPM_EVENT_SRC_MASK			(7 &lt;&lt; 0)</div><div class='del'>-#define		DIG_THERM_DPM(x)			((x) &lt;&lt; 14)</div><div class='del'>-#define		DIG_THERM_DPM_MASK			0x003FC000</div><div class='del'>-#define		DIG_THERM_DPM_SHIFT			14</div><div class='del'>-#define	CG_THERMAL_STATUS				0x1c1</div><div class='del'>-#define		FDO_PWM_DUTY(x)				((x) &lt;&lt; 9)</div><div class='del'>-#define		FDO_PWM_DUTY_MASK			(0xff &lt;&lt; 9)</div><div class='del'>-#define		FDO_PWM_DUTY_SHIFT			9</div><div class='del'>-#define	CG_THERMAL_INT					0x1c2</div><div class='del'>-#define		DIG_THERM_INTH(x)			((x) &lt;&lt; 8)</div><div class='del'>-#define		DIG_THERM_INTH_MASK			0x0000FF00</div><div class='del'>-#define		DIG_THERM_INTH_SHIFT			8</div><div class='del'>-#define		DIG_THERM_INTL(x)			((x) &lt;&lt; 16)</div><div class='del'>-#define		DIG_THERM_INTL_MASK			0x00FF0000</div><div class='del'>-#define		DIG_THERM_INTL_SHIFT			16</div><div class='del'>-#define 	THERM_INT_MASK_HIGH			(1 &lt;&lt; 24)</div><div class='del'>-#define 	THERM_INT_MASK_LOW			(1 &lt;&lt; 25)</div><div class='del'>-</div><div class='del'>-#define	CG_MULT_THERMAL_CTRL					0x1c4</div><div class='del'>-#define		TEMP_SEL(x)					((x) &lt;&lt; 20)</div><div class='del'>-#define		TEMP_SEL_MASK					(0xff &lt;&lt; 20)</div><div class='del'>-#define		TEMP_SEL_SHIFT					20</div><div class='del'>-#define	CG_MULT_THERMAL_STATUS					0x1c5</div><div class='del'>-#define		ASIC_MAX_TEMP(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		ASIC_MAX_TEMP_MASK				0x000001ff</div><div class='del'>-#define		ASIC_MAX_TEMP_SHIFT				0</div><div class='del'>-#define		CTF_TEMP(x)					((x) &lt;&lt; 9)</div><div class='del'>-#define		CTF_TEMP_MASK					0x0003fe00</div><div class='del'>-#define		CTF_TEMP_SHIFT					9</div><div class='del'>-</div><div class='del'>-#define	CG_FDO_CTRL0					0x1d5</div><div class='del'>-#define		FDO_STATIC_DUTY(x)			((x) &lt;&lt; 0)</div><div class='del'>-#define		FDO_STATIC_DUTY_MASK			0x000000FF</div><div class='del'>-#define		FDO_STATIC_DUTY_SHIFT			0</div><div class='del'>-#define	CG_FDO_CTRL1					0x1d6</div><div class='del'>-#define		FMAX_DUTY100(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		FMAX_DUTY100_MASK			0x000000FF</div><div class='del'>-#define		FMAX_DUTY100_SHIFT			0</div><div class='del'>-#define	CG_FDO_CTRL2					0x1d7</div><div class='del'>-#define		TMIN(x)					((x) &lt;&lt; 0)</div><div class='del'>-#define		TMIN_MASK				0x000000FF</div><div class='del'>-#define		TMIN_SHIFT				0</div><div class='del'>-#define		FDO_PWM_MODE(x)				((x) &lt;&lt; 11)</div><div class='del'>-#define		FDO_PWM_MODE_MASK			(7 &lt;&lt; 11)</div><div class='del'>-#define		FDO_PWM_MODE_SHIFT			11</div><div class='del'>-#define		TACH_PWM_RESP_RATE(x)			((x) &lt;&lt; 25)</div><div class='del'>-#define		TACH_PWM_RESP_RATE_MASK			(0x7f &lt;&lt; 25)</div><div class='del'>-#define		TACH_PWM_RESP_RATE_SHIFT		25</div><div class='del'>-</div><div class='del'>-#define CG_TACH_CTRL                                    0x1dc</div><div class='del'>-#       define EDGE_PER_REV(x)                          ((x) &lt;&lt; 0)</div><div class='del'>-#       define EDGE_PER_REV_MASK                        (0x7 &lt;&lt; 0)</div><div class='del'>-#       define EDGE_PER_REV_SHIFT                       0</div><div class='del'>-#       define TARGET_PERIOD(x)                         ((x) &lt;&lt; 3)</div><div class='del'>-#       define TARGET_PERIOD_MASK                       0xfffffff8</div><div class='del'>-#       define TARGET_PERIOD_SHIFT                      3</div><div class='del'>-#define CG_TACH_STATUS                                  0x1dd</div><div class='del'>-#       define TACH_PERIOD(x)                           ((x) &lt;&lt; 0)</div><div class='del'>-#       define TACH_PERIOD_MASK                         0xffffffff</div><div class='del'>-#       define TACH_PERIOD_SHIFT                        0</div><div class='del'>-</div><div class='del'>-#define GENERAL_PWRMGT                                  0x1e0</div><div class='del'>-#       define GLOBAL_PWRMGT_EN                         (1 &lt;&lt; 0)</div><div class='del'>-#       define STATIC_PM_EN                             (1 &lt;&lt; 1)</div><div class='del'>-#       define THERMAL_PROTECTION_DIS                   (1 &lt;&lt; 2)</div><div class='del'>-#       define THERMAL_PROTECTION_TYPE                  (1 &lt;&lt; 3)</div><div class='del'>-#       define SW_SMIO_INDEX(x)                         ((x) &lt;&lt; 6)</div><div class='del'>-#       define SW_SMIO_INDEX_MASK                       (1 &lt;&lt; 6)</div><div class='del'>-#       define SW_SMIO_INDEX_SHIFT                      6</div><div class='del'>-#       define VOLT_PWRMGT_EN                           (1 &lt;&lt; 10)</div><div class='del'>-#       define DYN_SPREAD_SPECTRUM_EN                   (1 &lt;&lt; 23)</div><div class='del'>-#define CG_TPC                                            0x1e1</div><div class='del'>-#define SCLK_PWRMGT_CNTL                                  0x1e2</div><div class='del'>-#       define SCLK_PWRMGT_OFF                            (1 &lt;&lt; 0)</div><div class='del'>-#       define SCLK_LOW_D1                                (1 &lt;&lt; 1)</div><div class='del'>-#       define FIR_RESET                                  (1 &lt;&lt; 4)</div><div class='del'>-#       define FIR_FORCE_TREND_SEL                        (1 &lt;&lt; 5)</div><div class='del'>-#       define FIR_TREND_MODE                             (1 &lt;&lt; 6)</div><div class='del'>-#       define DYN_GFX_CLK_OFF_EN                         (1 &lt;&lt; 7)</div><div class='del'>-#       define GFX_CLK_FORCE_ON                           (1 &lt;&lt; 8)</div><div class='del'>-#       define GFX_CLK_REQUEST_OFF                        (1 &lt;&lt; 9)</div><div class='del'>-#       define GFX_CLK_FORCE_OFF                          (1 &lt;&lt; 10)</div><div class='del'>-#       define GFX_CLK_OFF_ACPI_D1                        (1 &lt;&lt; 11)</div><div class='del'>-#       define GFX_CLK_OFF_ACPI_D2                        (1 &lt;&lt; 12)</div><div class='del'>-#       define GFX_CLK_OFF_ACPI_D3                        (1 &lt;&lt; 13)</div><div class='del'>-#       define DYN_LIGHT_SLEEP_EN                         (1 &lt;&lt; 14)</div><div class='del'>-</div><div class='del'>-#define TARGET_AND_CURRENT_PROFILE_INDEX                  0x1e6</div><div class='del'>-#       define CURRENT_STATE_INDEX_MASK                   (0xf &lt;&lt; 4)</div><div class='del'>-#       define CURRENT_STATE_INDEX_SHIFT                  4</div><div class='del'>-</div><div class='del'>-#define CG_FTV                                            0x1ef</div><div class='del'>-</div><div class='del'>-#define CG_FFCT_0                                         0x1f0</div><div class='del'>-#       define UTC_0(x)                                   ((x) &lt;&lt; 0)</div><div class='del'>-#       define UTC_0_MASK                                 (0x3ff &lt;&lt; 0)</div><div class='del'>-#       define DTC_0(x)                                   ((x) &lt;&lt; 10)</div><div class='del'>-#       define DTC_0_MASK                                 (0x3ff &lt;&lt; 10)</div><div class='del'>-</div><div class='del'>-#define CG_BSP                                          0x1ff</div><div class='del'>-#       define BSP(x)					((x) &lt;&lt; 0)</div><div class='del'>-#       define BSP_MASK					(0xffff &lt;&lt; 0)</div><div class='del'>-#       define BSU(x)					((x) &lt;&lt; 16)</div><div class='del'>-#       define BSU_MASK					(0xf &lt;&lt; 16)</div><div class='del'>-#define CG_AT                                           0x200</div><div class='del'>-#       define CG_R(x)					((x) &lt;&lt; 0)</div><div class='del'>-#       define CG_R_MASK				(0xffff &lt;&lt; 0)</div><div class='del'>-#       define CG_L(x)					((x) &lt;&lt; 16)</div><div class='del'>-#       define CG_L_MASK				(0xffff &lt;&lt; 16)</div><div class='del'>-</div><div class='del'>-#define CG_GIT                                          0x201</div><div class='del'>-#       define CG_GICST(x)                              ((x) &lt;&lt; 0)</div><div class='del'>-#       define CG_GICST_MASK                            (0xffff &lt;&lt; 0)</div><div class='del'>-#       define CG_GIPOT(x)                              ((x) &lt;&lt; 16)</div><div class='del'>-#       define CG_GIPOT_MASK                            (0xffff &lt;&lt; 16)</div><div class='del'>-</div><div class='del'>-#define CG_SSP                                            0x203</div><div class='del'>-#       define SST(x)                                     ((x) &lt;&lt; 0)</div><div class='del'>-#       define SST_MASK                                   (0xffff &lt;&lt; 0)</div><div class='del'>-#       define SSTU(x)                                    ((x) &lt;&lt; 16)</div><div class='del'>-#       define SSTU_MASK                                  (0xf &lt;&lt; 16)</div><div class='del'>-</div><div class='del'>-#define CG_DISPLAY_GAP_CNTL                               0x20a</div><div class='del'>-#       define DISP1_GAP(x)                               ((x) &lt;&lt; 0)</div><div class='del'>-#       define DISP1_GAP_MASK                             (3 &lt;&lt; 0)</div><div class='del'>-#       define DISP2_GAP(x)                               ((x) &lt;&lt; 2)</div><div class='del'>-#       define DISP2_GAP_MASK                             (3 &lt;&lt; 2)</div><div class='del'>-#       define VBI_TIMER_COUNT(x)                         ((x) &lt;&lt; 4)</div><div class='del'>-#       define VBI_TIMER_COUNT_MASK                       (0x3fff &lt;&lt; 4)</div><div class='del'>-#       define VBI_TIMER_UNIT(x)                          ((x) &lt;&lt; 20)</div><div class='del'>-#       define VBI_TIMER_UNIT_MASK                        (7 &lt;&lt; 20)</div><div class='del'>-#       define DISP1_GAP_MCHG(x)                          ((x) &lt;&lt; 24)</div><div class='del'>-#       define DISP1_GAP_MCHG_MASK                        (3 &lt;&lt; 24)</div><div class='del'>-#       define DISP2_GAP_MCHG(x)                          ((x) &lt;&lt; 26)</div><div class='del'>-#       define DISP2_GAP_MCHG_MASK                        (3 &lt;&lt; 26)</div><div class='del'>-</div><div class='del'>-#define	CG_ULV_CONTROL					0x21e</div><div class='del'>-#define	CG_ULV_PARAMETER				0x21f</div><div class='del'>-</div><div class='del'>-#define	SMC_SCRATCH0					0x221</div><div class='del'>-</div><div class='del'>-#define	CG_CAC_CTRL					0x22e</div><div class='del'>-#	define CAC_WINDOW(x)				((x) &lt;&lt; 0)</div><div class='del'>-#	define CAC_WINDOW_MASK				0x00ffffff</div><div class='del'>-</div><div class='del'>-#define DMIF_ADDR_CONFIG  				0x2F5</div><div class='del'>-</div><div class='del'>-#define DMIF_ADDR_CALC  				0x300</div><div class='del'>-</div><div class='del'>-#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0328</div><div class='del'>-#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) &lt;&lt; 0)</div><div class='del'>-#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define	SRBM_STATUS				        0x394</div><div class='del'>-#define		GRBM_RQ_PENDING 			(1 &lt;&lt; 5)</div><div class='del'>-#define		VMC_BUSY 				(1 &lt;&lt; 8)</div><div class='del'>-#define		MCB_BUSY 				(1 &lt;&lt; 9)</div><div class='del'>-#define		MCB_NON_DISPLAY_BUSY 			(1 &lt;&lt; 10)</div><div class='del'>-#define		MCC_BUSY 				(1 &lt;&lt; 11)</div><div class='del'>-#define		MCD_BUSY 				(1 &lt;&lt; 12)</div><div class='del'>-#define		SEM_BUSY 				(1 &lt;&lt; 14)</div><div class='del'>-#define		IH_BUSY 				(1 &lt;&lt; 17)</div><div class='del'>-</div><div class='del'>-#define	SRBM_SOFT_RESET				        0x398</div><div class='del'>-#define		SOFT_RESET_BIF				(1 &lt;&lt; 1)</div><div class='del'>-#define		SOFT_RESET_DC				(1 &lt;&lt; 5)</div><div class='del'>-#define		SOFT_RESET_DMA1				(1 &lt;&lt; 6)</div><div class='del'>-#define		SOFT_RESET_GRBM				(1 &lt;&lt; 8)</div><div class='del'>-#define		SOFT_RESET_HDP				(1 &lt;&lt; 9)</div><div class='del'>-#define		SOFT_RESET_IH				(1 &lt;&lt; 10)</div><div class='del'>-#define		SOFT_RESET_MC				(1 &lt;&lt; 11)</div><div class='del'>-#define		SOFT_RESET_ROM				(1 &lt;&lt; 14)</div><div class='del'>-#define		SOFT_RESET_SEM				(1 &lt;&lt; 15)</div><div class='del'>-#define		SOFT_RESET_VMC				(1 &lt;&lt; 17)</div><div class='del'>-#define		SOFT_RESET_DMA				(1 &lt;&lt; 20)</div><div class='del'>-#define		SOFT_RESET_TST				(1 &lt;&lt; 21)</div><div class='del'>-#define		SOFT_RESET_REGBB			(1 &lt;&lt; 22)</div><div class='del'>-#define		SOFT_RESET_ORB				(1 &lt;&lt; 23)</div><div class='del'>-</div><div class='del'>-#define	CC_SYS_RB_BACKEND_DISABLE			0x3A0</div><div class='del'>-#define	GC_USER_SYS_RB_BACKEND_DISABLE			0x3A1</div><div class='del'>-</div><div class='del'>-#define SRBM_READ_ERROR					0x3A6</div><div class='del'>-#define SRBM_INT_CNTL					0x3A8</div><div class='del'>-#define SRBM_INT_ACK					0x3AA</div><div class='del'>-</div><div class='del'>-#define	SRBM_STATUS2				        0x3B1</div><div class='del'>-#define		DMA_BUSY 				(1 &lt;&lt; 5)</div><div class='del'>-#define		DMA1_BUSY 				(1 &lt;&lt; 6)</div><div class='del'>-</div><div class='del'>-#define VM_L2_CNTL					0x500</div><div class='del'>-#define		ENABLE_L2_CACHE					(1 &lt;&lt; 0)</div><div class='del'>-#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 &lt;&lt; 1)</div><div class='del'>-#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) &lt;&lt; 2)</div><div class='del'>-#define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) &lt;&lt; 4)</div><div class='del'>-#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 &lt;&lt; 9)</div><div class='del'>-#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 &lt;&lt; 10)</div><div class='del'>-#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) &amp; 7) &lt;&lt; 15)</div><div class='del'>-#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) &amp; 3) &lt;&lt; 19)</div><div class='del'>-#define VM_L2_CNTL2					0x501</div><div class='del'>-#define		INVALIDATE_ALL_L1_TLBS				(1 &lt;&lt; 0)</div><div class='del'>-#define		INVALIDATE_L2_CACHE				(1 &lt;&lt; 1)</div><div class='del'>-#define		INVALIDATE_CACHE_MODE(x)			((x) &lt;&lt; 26)</div><div class='del'>-#define			INVALIDATE_PTE_AND_PDE_CACHES		0</div><div class='del'>-#define			INVALIDATE_ONLY_PTE_CACHES		1</div><div class='del'>-#define			INVALIDATE_ONLY_PDE_CACHES		2</div><div class='del'>-#define VM_L2_CNTL3					0x502</div><div class='del'>-#define		BANK_SELECT(x)					((x) &lt;&lt; 0)</div><div class='del'>-#define		L2_CACHE_UPDATE_MODE(x)				((x) &lt;&lt; 6)</div><div class='del'>-#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) &lt;&lt; 15)</div><div class='del'>-#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 &lt;&lt; 20)</div><div class='del'>-#define	VM_L2_STATUS					0x503</div><div class='del'>-#define		L2_BUSY						(1 &lt;&lt; 0)</div><div class='del'>-#define VM_CONTEXT0_CNTL				0x504</div><div class='del'>-#define		ENABLE_CONTEXT					(1 &lt;&lt; 0)</div><div class='del'>-#define		PAGE_TABLE_DEPTH(x)				(((x) &amp; 3) &lt;&lt; 1)</div><div class='del'>-#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 &lt;&lt; 3)</div><div class='del'>-#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 &lt;&lt; 4)</div><div class='del'>-#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 &lt;&lt; 6)</div><div class='del'>-#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 &lt;&lt; 7)</div><div class='del'>-#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 &lt;&lt; 9)</div><div class='del'>-#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 &lt;&lt; 10)</div><div class='del'>-#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 &lt;&lt; 12)</div><div class='del'>-#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 &lt;&lt; 13)</div><div class='del'>-#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 &lt;&lt; 15)</div><div class='del'>-#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 &lt;&lt; 16)</div><div class='del'>-#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 &lt;&lt; 18)</div><div class='del'>-#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 &lt;&lt; 19)</div><div class='del'>-#define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) &amp; 0xF) &lt;&lt; 24)</div><div class='del'>-#define VM_CONTEXT1_CNTL				0x505</div><div class='del'>-#define VM_CONTEXT0_CNTL2				0x50C</div><div class='del'>-#define VM_CONTEXT1_CNTL2				0x50D</div><div class='del'>-#define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x50E</div><div class='del'>-#define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x50F</div><div class='del'>-#define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x510</div><div class='del'>-#define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x511</div><div class='del'>-#define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x512</div><div class='del'>-#define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x513</div><div class='del'>-#define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x514</div><div class='del'>-#define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x515</div><div class='del'>-</div><div class='del'>-#define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x53f</div><div class='del'>-#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x537</div><div class='del'>-#define		PROTECTIONS_MASK			(0xf &lt;&lt; 0)</div><div class='del'>-#define		PROTECTIONS_SHIFT			0</div><div class='del'>-		/* bit 0: range</div><div class='del'>-		 * bit 1: pde0</div><div class='del'>-		 * bit 2: valid</div><div class='del'>-		 * bit 3: read</div><div class='del'>-		 * bit 4: write</div><div class='del'>-		 */</div><div class='del'>-#define		MEMORY_CLIENT_ID_MASK			(0xff &lt;&lt; 12)</div><div class='del'>-#define		MEMORY_CLIENT_ID_SHIFT			12</div><div class='del'>-#define		MEMORY_CLIENT_RW_MASK			(1 &lt;&lt; 24)</div><div class='del'>-#define		MEMORY_CLIENT_RW_SHIFT			24</div><div class='del'>-#define		FAULT_VMID_MASK				(0xf &lt;&lt; 25)</div><div class='del'>-#define		FAULT_VMID_SHIFT			25</div><div class='del'>-</div><div class='ctx'> #define VM_INVALIDATE_REQUEST				0x51E</div><div class='ctx'> #define VM_INVALIDATE_RESPONSE				0x51F</div><div class='ctx'> </div><div class='del'>-#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x546</div><div class='del'>-#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x547</div><div class='del'>-</div><div class='del'>-#define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x54F</div><div class='del'>-#define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x550</div><div class='del'>-#define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x551</div><div class='del'>-#define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x552</div><div class='del'>-#define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x553</div><div class='del'>-#define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x554</div><div class='del'>-#define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x555</div><div class='del'>-#define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x556</div><div class='del'>-#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x557</div><div class='del'>-#define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x558</div><div class='del'>-</div><div class='del'>-#define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x55F</div><div class='del'>-#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x560</div><div class='del'>-</div><div class='ctx'> #define VM_L2_CG           				0x570</div><div class='ctx'> #define		MC_CG_ENABLE				(1 &lt;&lt; 18)</div><div class='ctx'> #define		MC_LS_ENABLE				(1 &lt;&lt; 19)</div><div class='ctx'> </div><div class='del'>-#define MC_SHARED_CHMAP						0x801</div><div class='del'>-#define		NOOFCHAN_SHIFT					12</div><div class='del'>-#define		NOOFCHAN_MASK					0x0000f000</div><div class='del'>-#define MC_SHARED_CHREMAP					0x802</div><div class='del'>-</div><div class='ctx'> #define	MC_VM_FB_LOCATION				0x809</div><div class='ctx'> #define	MC_VM_AGP_TOP					0x80A</div><div class='ctx'> #define	MC_VM_AGP_BOT					0x80B</div><div class='hunk'>@@ -495,21 +112,6 @@</div><div class='ctx'> #define MC_CITF_MISC_WR_CG           			0x993</div><div class='ctx'> #define MC_CITF_MISC_VM_CG           			0x994</div><div class='ctx'> </div><div class='del'>-#define	MC_ARB_RAMCFG					0x9D8</div><div class='del'>-#define		NOOFBANK_SHIFT					0</div><div class='del'>-#define		NOOFBANK_MASK					0x00000003</div><div class='del'>-#define		NOOFRANK_SHIFT					2</div><div class='del'>-#define		NOOFRANK_MASK					0x00000004</div><div class='del'>-#define		NOOFROWS_SHIFT					3</div><div class='del'>-#define		NOOFROWS_MASK					0x00000038</div><div class='del'>-#define		NOOFCOLS_SHIFT					6</div><div class='del'>-#define		NOOFCOLS_MASK					0x000000C0</div><div class='del'>-#define		CHANSIZE_SHIFT					8</div><div class='del'>-#define		CHANSIZE_MASK					0x00000100</div><div class='del'>-#define		CHANSIZE_OVERRIDE				(1 &lt;&lt; 11)</div><div class='del'>-#define		NOOFGROUPS_SHIFT				12</div><div class='del'>-#define		NOOFGROUPS_MASK					0x00001000</div><div class='del'>-</div><div class='ctx'> #define	MC_ARB_DRAM_TIMING				0x9DD</div><div class='ctx'> #define	MC_ARB_DRAM_TIMING2				0x9DE</div><div class='ctx'> </div><div class='hunk'>@@ -635,20 +237,6 @@</div><div class='ctx'> #define		CLKS(x)					((x) &lt;&lt; 0)</div><div class='ctx'> #define		CLKS_MASK				(0xfff &lt;&lt; 0)</div><div class='ctx'> </div><div class='del'>-#define	HDP_HOST_PATH_CNTL				0xB00</div><div class='del'>-#define 	CLOCK_GATING_DIS			(1 &lt;&lt; 23)</div><div class='del'>-#define	HDP_NONSURFACE_BASE				0xB01</div><div class='del'>-#define	HDP_NONSURFACE_INFO				0xB02</div><div class='del'>-#define	HDP_NONSURFACE_SIZE				0xB03</div><div class='del'>-</div><div class='del'>-#define HDP_DEBUG0  					0xBCC</div><div class='del'>-</div><div class='del'>-#define HDP_ADDR_CONFIG  				0xBD2</div><div class='del'>-#define HDP_MISC_CNTL					0xBD3</div><div class='del'>-#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 &lt;&lt; 0)</div><div class='del'>-#define HDP_MEM_POWER_LS				0xBD4</div><div class='del'>-#define 	HDP_LS_ENABLE				(1 &lt;&lt; 0)</div><div class='del'>-</div><div class='ctx'> #define ATC_MISC_CG           				0xCD4</div><div class='ctx'> </div><div class='ctx'> #define IH_RB_CNTL                                        0xF80</div><div class='hunk'>@@ -678,8 +266,6 @@</div><div class='ctx'> #       define MC_WR_CLEAN_CNT(x)                         ((x) &lt;&lt; 20)</div><div class='ctx'> #       define MC_VMID(x)                                 ((x) &lt;&lt; 25)</div><div class='ctx'> </div><div class='del'>-#define	CONFIG_MEMSIZE					0x150A</div><div class='del'>-</div><div class='ctx'> #define INTERRUPT_CNTL                                    0x151A</div><div class='ctx'> #       define IH_DUMMY_RD_OVERRIDE                       (1 &lt;&lt; 0)</div><div class='ctx'> #       define IH_DUMMY_RD_EN                             (1 &lt;&lt; 1)</div><div class='hunk'>@@ -687,734 +273,28 @@</div><div class='ctx'> #       define GEN_IH_INT_EN                              (1 &lt;&lt; 8)</div><div class='ctx'> #define INTERRUPT_CNTL2                                   0x151B</div><div class='ctx'> </div><div class='del'>-#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x1520</div><div class='del'>-</div><div class='del'>-#define	BIF_FB_EN						0x1524</div><div class='del'>-#define		FB_READ_EN					(1 &lt;&lt; 0)</div><div class='del'>-#define		FB_WRITE_EN					(1 &lt;&lt; 1)</div><div class='del'>-</div><div class='del'>-#define HDP_REG_COHERENCY_FLUSH_CNTL			0x1528</div><div class='del'>-</div><div class='del'>-/* DCE6 ELD audio interface */</div><div class='del'>-#define AZ_F0_CODEC_ENDPOINT_INDEX                       0x1780</div><div class='del'>-#       define AZ_ENDPOINT_REG_INDEX(x)                  (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define AZ_ENDPOINT_REG_WRITE_EN                  (1 &lt;&lt; 8)</div><div class='del'>-#define AZ_F0_CODEC_ENDPOINT_DATA                        0x1781</div><div class='del'>-</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER          0x25</div><div class='del'>-#define		SPEAKER_ALLOCATION(x)			(((x) &amp; 0x7f) &lt;&lt; 0)</div><div class='del'>-#define		SPEAKER_ALLOCATION_MASK			(0x7f &lt;&lt; 0)</div><div class='del'>-#define		SPEAKER_ALLOCATION_SHIFT		0</div><div class='del'>-#define		HDMI_CONNECTION				(1 &lt;&lt; 16)</div><div class='del'>-#define		DP_CONNECTION				(1 &lt;&lt; 17)</div><div class='del'>-</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0        0x28 /* LPCM */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1        0x29 /* AC3 */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2        0x2A /* MPEG1 */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3        0x2B /* MP3 */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4        0x2C /* MPEG2 */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5        0x2D /* AAC */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6        0x2E /* DTS */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7        0x2F /* ATRAC */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8        0x30 /* one bit audio - leave at 0 (default) */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9        0x31 /* Dolby Digital */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10       0x32 /* DTS-HD */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11       0x33 /* MAT-MLP */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12       0x34 /* DTS */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13       0x35 /* WMA Pro */</div><div class='del'>-#       define MAX_CHANNELS(x)                            (((x) &amp; 0x7) &lt;&lt; 0)</div><div class='del'>-/* max channels minus one.  7 = 8 channels */</div><div class='del'>-#       define SUPPORTED_FREQUENCIES(x)                   (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-#       define DESCRIPTOR_BYTE_2(x)                       (((x) &amp; 0xff) &lt;&lt; 16)</div><div class='del'>-#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) &amp; 0xff) &lt;&lt; 24) /* LPCM only */</div><div class='del'>-/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO</div><div class='del'>- * bit0 = 32 kHz</div><div class='del'>- * bit1 = 44.1 kHz</div><div class='del'>- * bit2 = 48 kHz</div><div class='del'>- * bit3 = 88.2 kHz</div><div class='del'>- * bit4 = 96 kHz</div><div class='del'>- * bit5 = 176.4 kHz</div><div class='del'>- * bit6 = 192 kHz</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC         0x37</div><div class='del'>-#       define VIDEO_LIPSYNC(x)                           (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define AUDIO_LIPSYNC(x)                           (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-/* VIDEO_LIPSYNC, AUDIO_LIPSYNC</div><div class='del'>- * 0   = invalid</div><div class='del'>- * x   = legal delay value</div><div class='del'>- * 255 = sync not supported</div><div class='del'>- */</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR             0x38</div><div class='del'>-#       define HBR_CAPABLE                                (1 &lt;&lt; 0) /* enabled by default */</div><div class='del'>-</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0               0x3a</div><div class='del'>-#       define MANUFACTURER_ID(x)                        (((x) &amp; 0xffff) &lt;&lt; 0)</div><div class='del'>-#       define PRODUCT_ID(x)                             (((x) &amp; 0xffff) &lt;&lt; 16)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1               0x3b</div><div class='del'>-#       define SINK_DESCRIPTION_LEN(x)                   (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2               0x3c</div><div class='del'>-#       define PORT_ID0(x)                               (((x) &amp; 0xffffffff) &lt;&lt; 0)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3               0x3d</div><div class='del'>-#       define PORT_ID1(x)                               (((x) &amp; 0xffffffff) &lt;&lt; 0)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4               0x3e</div><div class='del'>-#       define DESCRIPTION0(x)                           (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define DESCRIPTION1(x)                           (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-#       define DESCRIPTION2(x)                           (((x) &amp; 0xff) &lt;&lt; 16)</div><div class='del'>-#       define DESCRIPTION3(x)                           (((x) &amp; 0xff) &lt;&lt; 24)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5               0x3f</div><div class='del'>-#       define DESCRIPTION4(x)                           (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define DESCRIPTION5(x)                           (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-#       define DESCRIPTION6(x)                           (((x) &amp; 0xff) &lt;&lt; 16)</div><div class='del'>-#       define DESCRIPTION7(x)                           (((x) &amp; 0xff) &lt;&lt; 24)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6               0x40</div><div class='del'>-#       define DESCRIPTION8(x)                           (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define DESCRIPTION9(x)                           (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-#       define DESCRIPTION10(x)                          (((x) &amp; 0xff) &lt;&lt; 16)</div><div class='del'>-#       define DESCRIPTION11(x)                          (((x) &amp; 0xff) &lt;&lt; 24)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7               0x41</div><div class='del'>-#       define DESCRIPTION12(x)                          (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define DESCRIPTION13(x)                          (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-#       define DESCRIPTION14(x)                          (((x) &amp; 0xff) &lt;&lt; 16)</div><div class='del'>-#       define DESCRIPTION15(x)                          (((x) &amp; 0xff) &lt;&lt; 24)</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8               0x42</div><div class='del'>-#       define DESCRIPTION16(x)                          (((x) &amp; 0xff) &lt;&lt; 0)</div><div class='del'>-#       define DESCRIPTION17(x)                          (((x) &amp; 0xff) &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL         0x54</div><div class='del'>-#       define AUDIO_ENABLED                             (1 &lt;&lt; 31)</div><div class='del'>-</div><div class='del'>-#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT  0x56</div><div class='del'>-#define		PORT_CONNECTIVITY_MASK				(3 &lt;&lt; 30)</div><div class='del'>-#define		PORT_CONNECTIVITY_SHIFT				30</div><div class='del'>-</div><div class='del'>-#define	DC_LB_MEMORY_SPLIT					0x1AC3</div><div class='del'>-#define		DC_LB_MEMORY_CONFIG(x)				((x) &lt;&lt; 20)</div><div class='del'>-</div><div class='del'>-#define	PRIORITY_A_CNT						0x1AC6</div><div class='del'>-#define		PRIORITY_MARK_MASK				0x7fff</div><div class='del'>-#define		PRIORITY_OFF					(1 &lt;&lt; 16)</div><div class='del'>-#define		PRIORITY_ALWAYS_ON				(1 &lt;&lt; 20)</div><div class='del'>-#define	PRIORITY_B_CNT						0x1AC7</div><div class='del'>-</div><div class='del'>-#define	DPG_PIPE_ARBITRATION_CONTROL3				0x1B32</div><div class='del'>-#       define LATENCY_WATERMARK_MASK(x)			((x) &lt;&lt; 16)</div><div class='del'>-#define	DPG_PIPE_LATENCY_CONTROL				0x1B33</div><div class='del'>-#       define LATENCY_LOW_WATERMARK(x)				((x) &lt;&lt; 0)</div><div class='del'>-#       define LATENCY_HIGH_WATERMARK(x)			((x) &lt;&lt; 16)</div><div class='del'>-</div><div class='del'>-/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */</div><div class='del'>-#define VLINE_STATUS                                    0x1AEE</div><div class='del'>-#       define VLINE_OCCURRED                           (1 &lt;&lt; 0)</div><div class='del'>-#       define VLINE_ACK                                (1 &lt;&lt; 4)</div><div class='del'>-#       define VLINE_STAT                               (1 &lt;&lt; 12)</div><div class='del'>-#       define VLINE_INTERRUPT                          (1 &lt;&lt; 16)</div><div class='del'>-#       define VLINE_INTERRUPT_TYPE                     (1 &lt;&lt; 17)</div><div class='del'>-/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */</div><div class='del'>-#define VBLANK_STATUS                                   0x1AEF</div><div class='del'>-#       define VBLANK_OCCURRED                          (1 &lt;&lt; 0)</div><div class='del'>-#       define VBLANK_ACK                               (1 &lt;&lt; 4)</div><div class='del'>-#       define VBLANK_STAT                              (1 &lt;&lt; 12)</div><div class='del'>-#       define VBLANK_INTERRUPT                         (1 &lt;&lt; 16)</div><div class='del'>-#       define VBLANK_INTERRUPT_TYPE                    (1 &lt;&lt; 17)</div><div class='del'>-</div><div class='del'>-/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */</div><div class='del'>-#define INT_MASK                                        0x1AD0</div><div class='del'>-#       define VBLANK_INT_MASK                          (1 &lt;&lt; 0)</div><div class='del'>-#       define VLINE_INT_MASK                           (1 &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define DISP_INTERRUPT_STATUS                           0x183D</div><div class='del'>-#       define LB_D1_VLINE_INTERRUPT                    (1 &lt;&lt; 2)</div><div class='del'>-#       define LB_D1_VBLANK_INTERRUPT                   (1 &lt;&lt; 3)</div><div class='del'>-#       define DC_HPD1_INTERRUPT                        (1 &lt;&lt; 17)</div><div class='del'>-#       define DC_HPD1_RX_INTERRUPT                     (1 &lt;&lt; 18)</div><div class='del'>-#       define DACA_AUTODETECT_INTERRUPT                (1 &lt;&lt; 22)</div><div class='del'>-#       define DACB_AUTODETECT_INTERRUPT                (1 &lt;&lt; 23)</div><div class='del'>-#       define DC_I2C_SW_DONE_INTERRUPT                 (1 &lt;&lt; 24)</div><div class='del'>-#       define DC_I2C_HW_DONE_INTERRUPT                 (1 &lt;&lt; 25)</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE                  0x183E</div><div class='del'>-#       define LB_D2_VLINE_INTERRUPT                    (1 &lt;&lt; 2)</div><div class='del'>-#       define LB_D2_VBLANK_INTERRUPT                   (1 &lt;&lt; 3)</div><div class='del'>-#       define DC_HPD2_INTERRUPT                        (1 &lt;&lt; 17)</div><div class='del'>-#       define DC_HPD2_RX_INTERRUPT                     (1 &lt;&lt; 18)</div><div class='del'>-#       define DISP_TIMER_INTERRUPT                     (1 &lt;&lt; 24)</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x183F</div><div class='del'>-#       define LB_D3_VLINE_INTERRUPT                    (1 &lt;&lt; 2)</div><div class='del'>-#       define LB_D3_VBLANK_INTERRUPT                   (1 &lt;&lt; 3)</div><div class='del'>-#       define DC_HPD3_INTERRUPT                        (1 &lt;&lt; 17)</div><div class='del'>-#       define DC_HPD3_RX_INTERRUPT                     (1 &lt;&lt; 18)</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x1840</div><div class='del'>-#       define LB_D4_VLINE_INTERRUPT                    (1 &lt;&lt; 2)</div><div class='del'>-#       define LB_D4_VBLANK_INTERRUPT                   (1 &lt;&lt; 3)</div><div class='del'>-#       define DC_HPD4_INTERRUPT                        (1 &lt;&lt; 17)</div><div class='del'>-#       define DC_HPD4_RX_INTERRUPT                     (1 &lt;&lt; 18)</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x1853</div><div class='del'>-#       define LB_D5_VLINE_INTERRUPT                    (1 &lt;&lt; 2)</div><div class='del'>-#       define LB_D5_VBLANK_INTERRUPT                   (1 &lt;&lt; 3)</div><div class='del'>-#       define DC_HPD5_INTERRUPT                        (1 &lt;&lt; 17)</div><div class='del'>-#       define DC_HPD5_RX_INTERRUPT                     (1 &lt;&lt; 18)</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x1854</div><div class='del'>-#       define LB_D6_VLINE_INTERRUPT                    (1 &lt;&lt; 2)</div><div class='del'>-#       define LB_D6_VBLANK_INTERRUPT                   (1 &lt;&lt; 3)</div><div class='del'>-#       define DC_HPD6_INTERRUPT                        (1 &lt;&lt; 17)</div><div class='del'>-#       define DC_HPD6_RX_INTERRUPT                     (1 &lt;&lt; 18)</div><div class='del'>-</div><div class='del'>-/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */</div><div class='del'>-#define GRPH_INT_STATUS                                 0x1A16</div><div class='del'>-#       define GRPH_PFLIP_INT_OCCURRED                  (1 &lt;&lt; 0)</div><div class='del'>-#       define GRPH_PFLIP_INT_CLEAR                     (1 &lt;&lt; 8)</div><div class='del'>-/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */</div><div class='del'>-#define	GRPH_INT_CONTROL			        0x1A17</div><div class='del'>-#       define GRPH_PFLIP_INT_MASK                      (1 &lt;&lt; 0)</div><div class='del'>-#       define GRPH_PFLIP_INT_TYPE                      (1 &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define	DAC_AUTODETECT_INT_CONTROL			0x19F2</div><div class='del'>-</div><div class='del'>-#define DC_HPD1_INT_STATUS                              0x1807</div><div class='del'>-#define DC_HPD2_INT_STATUS                              0x180A</div><div class='del'>-#define DC_HPD3_INT_STATUS                              0x180D</div><div class='del'>-#define DC_HPD4_INT_STATUS                              0x1810</div><div class='del'>-#define DC_HPD5_INT_STATUS                              0x1813</div><div class='del'>-#define DC_HPD6_INT_STATUS                              0x1816</div><div class='del'>-#       define DC_HPDx_INT_STATUS                       (1 &lt;&lt; 0)</div><div class='del'>-#       define DC_HPDx_SENSE                            (1 &lt;&lt; 1)</div><div class='del'>-#       define DC_HPDx_RX_INT_STATUS                    (1 &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define DC_HPD1_INT_CONTROL                             0x1808</div><div class='del'>-#define DC_HPD2_INT_CONTROL                             0x180B</div><div class='del'>-#define DC_HPD3_INT_CONTROL                             0x180E</div><div class='del'>-#define DC_HPD4_INT_CONTROL                             0x1811</div><div class='del'>-#define DC_HPD5_INT_CONTROL                             0x1814</div><div class='del'>-#define DC_HPD6_INT_CONTROL                             0x1817</div><div class='del'>-#       define DC_HPDx_INT_ACK                          (1 &lt;&lt; 0)</div><div class='del'>-#       define DC_HPDx_INT_POLARITY                     (1 &lt;&lt; 8)</div><div class='del'>-#       define DC_HPDx_INT_EN                           (1 &lt;&lt; 16)</div><div class='del'>-#       define DC_HPDx_RX_INT_ACK                       (1 &lt;&lt; 20)</div><div class='del'>-#       define DC_HPDx_RX_INT_EN                        (1 &lt;&lt; 24)</div><div class='del'>-</div><div class='del'>-#define DC_HPD1_CONTROL                                   0x1809</div><div class='del'>-#define DC_HPD2_CONTROL                                   0x180C</div><div class='del'>-#define DC_HPD3_CONTROL                                   0x180F</div><div class='del'>-#define DC_HPD4_CONTROL                                   0x1812</div><div class='del'>-#define DC_HPD5_CONTROL                                   0x1815</div><div class='del'>-#define DC_HPD6_CONTROL                                   0x1818</div><div class='del'>-#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) &lt;&lt; 0)</div><div class='del'>-#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) &lt;&lt; 16)</div><div class='del'>-#       define DC_HPDx_EN                                 (1 &lt;&lt; 28)</div><div class='del'>-</div><div class='del'>-#define DPG_PIPE_STUTTER_CONTROL                          0x1B35</div><div class='del'>-#       define STUTTER_ENABLE                             (1 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */</div><div class='del'>-#define CRTC_STATUS_FRAME_COUNT                         0x1BA6</div><div class='del'>-</div><div class='del'>-/* Audio clocks */</div><div class='del'>-#define DCCG_AUDIO_DTO_SOURCE                           0x05ac</div><div class='del'>-#       define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) &lt;&lt; 0) /* crtc0 - crtc5 */</div><div class='del'>-#       define DCCG_AUDIO_DTO_SEL            (1 &lt;&lt; 4)   /* 0=dto0 1=dto1 */</div><div class='del'>-</div><div class='del'>-#define DCCG_AUDIO_DTO0_PHASE                           0x05b0</div><div class='del'>-#define DCCG_AUDIO_DTO0_MODULE                          0x05b4</div><div class='del'>-#define DCCG_AUDIO_DTO1_PHASE                           0x05c0</div><div class='del'>-#define DCCG_AUDIO_DTO1_MODULE                          0x05c4</div><div class='del'>-</div><div class='del'>-#define AFMT_AUDIO_SRC_CONTROL                          0x1c4f</div><div class='del'>-#define		AFMT_AUDIO_SRC_SELECT(x)		(((x) &amp; 7) &lt;&lt; 0)</div><div class='del'>-/* AFMT_AUDIO_SRC_SELECT</div><div class='del'>- * 0 = stream0</div><div class='del'>- * 1 = stream1</div><div class='del'>- * 2 = stream2</div><div class='del'>- * 3 = stream3</div><div class='del'>- * 4 = stream4</div><div class='del'>- * 5 = stream5</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#define	GRBM_CNTL					0x2000</div><div class='del'>-#define		GRBM_READ_TIMEOUT(x)				((x) &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-#define	GRBM_STATUS2					0x2002</div><div class='del'>-#define		RLC_RQ_PENDING 					(1 &lt;&lt; 0)</div><div class='del'>-#define		RLC_BUSY 					(1 &lt;&lt; 8)</div><div class='del'>-#define		TC_BUSY 					(1 &lt;&lt; 9)</div><div class='del'>-</div><div class='del'>-#define	GRBM_STATUS					0x2004</div><div class='del'>-#define		CMDFIFO_AVAIL_MASK				0x0000000F</div><div class='del'>-#define		RING2_RQ_PENDING				(1 &lt;&lt; 4)</div><div class='del'>-#define		SRBM_RQ_PENDING					(1 &lt;&lt; 5)</div><div class='del'>-#define		RING1_RQ_PENDING				(1 &lt;&lt; 6)</div><div class='del'>-#define		CF_RQ_PENDING					(1 &lt;&lt; 7)</div><div class='del'>-#define		PF_RQ_PENDING					(1 &lt;&lt; 8)</div><div class='del'>-#define		GDS_DMA_RQ_PENDING				(1 &lt;&lt; 9)</div><div class='del'>-#define		GRBM_EE_BUSY					(1 &lt;&lt; 10)</div><div class='del'>-#define		DB_CLEAN					(1 &lt;&lt; 12)</div><div class='del'>-#define		CB_CLEAN					(1 &lt;&lt; 13)</div><div class='del'>-#define		TA_BUSY 					(1 &lt;&lt; 14)</div><div class='del'>-#define		GDS_BUSY 					(1 &lt;&lt; 15)</div><div class='del'>-#define		VGT_BUSY					(1 &lt;&lt; 17)</div><div class='del'>-#define		IA_BUSY_NO_DMA					(1 &lt;&lt; 18)</div><div class='del'>-#define		IA_BUSY						(1 &lt;&lt; 19)</div><div class='del'>-#define		SX_BUSY 					(1 &lt;&lt; 20)</div><div class='del'>-#define		SPI_BUSY					(1 &lt;&lt; 22)</div><div class='del'>-#define		BCI_BUSY					(1 &lt;&lt; 23)</div><div class='del'>-#define		SC_BUSY 					(1 &lt;&lt; 24)</div><div class='del'>-#define		PA_BUSY 					(1 &lt;&lt; 25)</div><div class='del'>-#define		DB_BUSY 					(1 &lt;&lt; 26)</div><div class='del'>-#define		CP_COHERENCY_BUSY      				(1 &lt;&lt; 28)</div><div class='del'>-#define		CP_BUSY 					(1 &lt;&lt; 29)</div><div class='del'>-#define		CB_BUSY 					(1 &lt;&lt; 30)</div><div class='del'>-#define		GUI_ACTIVE					(1 &lt;&lt; 31)</div><div class='del'>-#define	GRBM_STATUS_SE0					0x2005</div><div class='del'>-#define	GRBM_STATUS_SE1					0x2006</div><div class='del'>-#define		SE_DB_CLEAN					(1 &lt;&lt; 1)</div><div class='del'>-#define		SE_CB_CLEAN					(1 &lt;&lt; 2)</div><div class='del'>-#define		SE_BCI_BUSY					(1 &lt;&lt; 22)</div><div class='del'>-#define		SE_VGT_BUSY					(1 &lt;&lt; 23)</div><div class='del'>-#define		SE_PA_BUSY					(1 &lt;&lt; 24)</div><div class='del'>-#define		SE_TA_BUSY					(1 &lt;&lt; 25)</div><div class='del'>-#define		SE_SX_BUSY					(1 &lt;&lt; 26)</div><div class='del'>-#define		SE_SPI_BUSY					(1 &lt;&lt; 27)</div><div class='del'>-#define		SE_SC_BUSY					(1 &lt;&lt; 29)</div><div class='del'>-#define		SE_DB_BUSY					(1 &lt;&lt; 30)</div><div class='del'>-#define		SE_CB_BUSY					(1 &lt;&lt; 31)</div><div class='del'>-</div><div class='del'>-#define	GRBM_SOFT_RESET					0x2008</div><div class='del'>-#define		SOFT_RESET_CP					(1 &lt;&lt; 0)</div><div class='del'>-#define		SOFT_RESET_CB					(1 &lt;&lt; 1)</div><div class='del'>-#define		SOFT_RESET_RLC					(1 &lt;&lt; 2)</div><div class='del'>-#define		SOFT_RESET_DB					(1 &lt;&lt; 3)</div><div class='del'>-#define		SOFT_RESET_GDS					(1 &lt;&lt; 4)</div><div class='del'>-#define		SOFT_RESET_PA					(1 &lt;&lt; 5)</div><div class='del'>-#define		SOFT_RESET_SC					(1 &lt;&lt; 6)</div><div class='del'>-#define		SOFT_RESET_BCI					(1 &lt;&lt; 7)</div><div class='del'>-#define		SOFT_RESET_SPI					(1 &lt;&lt; 8)</div><div class='del'>-#define		SOFT_RESET_SX					(1 &lt;&lt; 10)</div><div class='del'>-#define		SOFT_RESET_TC					(1 &lt;&lt; 11)</div><div class='del'>-#define		SOFT_RESET_TA					(1 &lt;&lt; 12)</div><div class='del'>-#define		SOFT_RESET_VGT					(1 &lt;&lt; 14)</div><div class='del'>-#define		SOFT_RESET_IA					(1 &lt;&lt; 15)</div><div class='del'>-</div><div class='del'>-#define GRBM_GFX_INDEX          			0x200B</div><div class='del'>-#define		INSTANCE_INDEX(x)			((x) &lt;&lt; 0)</div><div class='del'>-#define		SH_INDEX(x)     			((x) &lt;&lt; 8)</div><div class='del'>-#define		SE_INDEX(x)     			((x) &lt;&lt; 16)</div><div class='del'>-#define		SH_BROADCAST_WRITES      		(1 &lt;&lt; 29)</div><div class='del'>-#define		INSTANCE_BROADCAST_WRITES      		(1 &lt;&lt; 30)</div><div class='del'>-#define		SE_BROADCAST_WRITES      		(1 &lt;&lt; 31)</div><div class='del'>-</div><div class='del'>-#define GRBM_INT_CNTL                                   0x2018</div><div class='del'>-#       define RDERR_INT_ENABLE                         (1 &lt;&lt; 0)</div><div class='del'>-#       define GUI_IDLE_INT_ENABLE                      (1 &lt;&lt; 19)</div><div class='del'>-</div><div class='del'>-#define	CP_STRMOUT_CNTL					0x213F</div><div class='del'>-#define	SCRATCH_REG0					0x2140</div><div class='del'>-#define	SCRATCH_REG1					0x2141</div><div class='del'>-#define	SCRATCH_REG2					0x2142</div><div class='del'>-#define	SCRATCH_REG3					0x2143</div><div class='del'>-#define	SCRATCH_REG4					0x2144</div><div class='del'>-#define	SCRATCH_REG5					0x2145</div><div class='del'>-#define	SCRATCH_REG6					0x2146</div><div class='del'>-#define	SCRATCH_REG7					0x2147</div><div class='del'>-</div><div class='del'>-#define	SCRATCH_UMSK					0x2150</div><div class='del'>-#define	SCRATCH_ADDR					0x2151</div><div class='del'>-</div><div class='del'>-#define	CP_SEM_WAIT_TIMER				0x216F</div><div class='del'>-</div><div class='del'>-#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x2172</div><div class='del'>-</div><div class='del'>-#define CP_ME_CNTL					0x21B6</div><div class='del'>-#define		CP_CE_HALT					(1 &lt;&lt; 24)</div><div class='del'>-#define		CP_PFP_HALT					(1 &lt;&lt; 26)</div><div class='del'>-#define		CP_ME_HALT					(1 &lt;&lt; 28)</div><div class='del'>-</div><div class='del'>-#define	CP_COHER_CNTL2					0x217A</div><div class='del'>-</div><div class='del'>-#define	CP_RB2_RPTR					0x21BE</div><div class='del'>-#define	CP_RB1_RPTR					0x21BF</div><div class='del'>-#define	CP_RB0_RPTR					0x21C0</div><div class='del'>-#define	CP_RB_WPTR_DELAY				0x21C1</div><div class='del'>-</div><div class='del'>-#define	CP_QUEUE_THRESHOLDS				0x21D8</div><div class='del'>-#define		ROQ_IB1_START(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		ROQ_IB2_START(x)				((x) &lt;&lt; 8)</div><div class='del'>-#define CP_MEQ_THRESHOLDS				0x21D9</div><div class='del'>-#define		MEQ1_START(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		MEQ2_START(x)				((x) &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define	CP_PERFMON_CNTL					0x21FF</div><div class='del'>-</div><div class='ctx'> #define	VGT_VTX_VECT_EJECT_REG				0x222C</div><div class='del'>-</div><div class='del'>-#define	VGT_CACHE_INVALIDATION				0x2231</div><div class='del'>-#define		CACHE_INVALIDATION(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define			VC_ONLY						0</div><div class='del'>-#define			TC_ONLY						1</div><div class='del'>-#define			VC_AND_TC					2</div><div class='del'>-#define		AUTO_INVLD_EN(x)				((x) &lt;&lt; 6)</div><div class='del'>-#define			NO_AUTO						0</div><div class='del'>-#define			ES_AUTO						1</div><div class='del'>-#define			GS_AUTO						2</div><div class='del'>-#define			ES_AND_GS_AUTO					3</div><div class='ctx'> #define	VGT_ESGS_RING_SIZE				0x2232</div><div class='ctx'> #define	VGT_GSVS_RING_SIZE				0x2233</div><div class='del'>-</div><div class='ctx'> #define	VGT_GS_VERTEX_REUSE				0x2235</div><div class='del'>-</div><div class='ctx'> #define	VGT_PRIMITIVE_TYPE				0x2256</div><div class='ctx'> #define	VGT_INDEX_TYPE					0x2257</div><div class='del'>-</div><div class='ctx'> #define	VGT_NUM_INDICES					0x225C</div><div class='ctx'> #define	VGT_NUM_INSTANCES				0x225D</div><div class='del'>-</div><div class='ctx'> #define	VGT_TF_RING_SIZE				0x2262</div><div class='del'>-</div><div class='ctx'> #define	VGT_HS_OFFCHIP_PARAM				0x226C</div><div class='del'>-</div><div class='ctx'> #define	VGT_TF_MEMORY_BASE				0x226E</div><div class='ctx'> </div><div class='del'>-#define CC_GC_SHADER_ARRAY_CONFIG			0x226F</div><div class='del'>-#define		INACTIVE_CUS_MASK			0xFFFF0000</div><div class='del'>-#define		INACTIVE_CUS_SHIFT			16</div><div class='del'>-#define GC_USER_SHADER_ARRAY_CONFIG			0x2270</div><div class='del'>-</div><div class='del'>-#define	PA_CL_ENHANCE					0x2285</div><div class='del'>-#define		CLIP_VTX_REORDER_ENA				(1 &lt;&lt; 0)</div><div class='del'>-#define		NUM_CLIP_SEQ(x)					((x) &lt;&lt; 1)</div><div class='del'>-</div><div class='del'>-#define	PA_SU_LINE_STIPPLE_VALUE			0x2298</div><div class='del'>-</div><div class='del'>-#define	PA_SC_LINE_STIPPLE_STATE			0x22C4</div><div class='del'>-</div><div class='del'>-#define	PA_SC_FORCE_EOV_MAX_CNTS			0x22C9</div><div class='del'>-#define		FORCE_EOV_MAX_CLK_CNT(x)			((x) &lt;&lt; 0)</div><div class='del'>-#define		FORCE_EOV_MAX_REZ_CNT(x)			((x) &lt;&lt; 16)</div><div class='del'>-</div><div class='del'>-#define	PA_SC_FIFO_SIZE					0x22F3</div><div class='del'>-#define		SC_FRONTEND_PRIM_FIFO_SIZE(x)			((x) &lt;&lt; 0)</div><div class='del'>-#define		SC_BACKEND_PRIM_FIFO_SIZE(x)			((x) &lt;&lt; 6)</div><div class='del'>-#define		SC_HIZ_TILE_FIFO_SIZE(x)			((x) &lt;&lt; 15)</div><div class='del'>-#define		SC_EARLYZ_TILE_FIFO_SIZE(x)			((x) &lt;&lt; 23)</div><div class='del'>-</div><div class='ctx'> #define	PA_SC_ENHANCE					0x22FC</div><div class='ctx'> </div><div class='del'>-#define	SQ_CONFIG					0x2300</div><div class='del'>-</div><div class='del'>-#define	SQC_CACHES					0x2302</div><div class='del'>-</div><div class='del'>-#define SQ_POWER_THROTTLE                               0x2396</div><div class='del'>-#define		MIN_POWER(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		MIN_POWER_MASK				(0x3fff &lt;&lt; 0)</div><div class='del'>-#define		MIN_POWER_SHIFT				0</div><div class='del'>-#define		MAX_POWER(x)				((x) &lt;&lt; 16)</div><div class='del'>-#define		MAX_POWER_MASK				(0x3fff &lt;&lt; 16)</div><div class='del'>-#define		MAX_POWER_SHIFT				0</div><div class='del'>-#define SQ_POWER_THROTTLE2                              0x2397</div><div class='del'>-#define		MAX_POWER_DELTA(x)			((x) &lt;&lt; 0)</div><div class='del'>-#define		MAX_POWER_DELTA_MASK			(0x3fff &lt;&lt; 0)</div><div class='del'>-#define		MAX_POWER_DELTA_SHIFT			0</div><div class='del'>-#define		STI_SIZE(x)				((x) &lt;&lt; 16)</div><div class='del'>-#define		STI_SIZE_MASK				(0x3ff &lt;&lt; 16)</div><div class='del'>-#define		STI_SIZE_SHIFT				16</div><div class='del'>-#define		LTI_RATIO(x)				((x) &lt;&lt; 27)</div><div class='del'>-#define		LTI_RATIO_MASK				(0xf &lt;&lt; 27)</div><div class='del'>-#define		LTI_RATIO_SHIFT				27</div><div class='del'>-</div><div class='del'>-#define	SX_DEBUG_1					0x2418</div><div class='del'>-</div><div class='del'>-#define	SPI_STATIC_THREAD_MGMT_1			0x2438</div><div class='del'>-#define	SPI_STATIC_THREAD_MGMT_2			0x2439</div><div class='del'>-#define	SPI_STATIC_THREAD_MGMT_3			0x243A</div><div class='del'>-#define	SPI_PS_MAX_WAVE_ID				0x243B</div><div class='del'>-</div><div class='del'>-#define	SPI_CONFIG_CNTL					0x2440</div><div class='del'>-</div><div class='del'>-#define	SPI_CONFIG_CNTL_1				0x244F</div><div class='del'>-#define		VTX_DONE_DELAY(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		INTERP_ONE_PRIM_PER_ROW				(1 &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define	CGTS_TCC_DISABLE				0x2452</div><div class='del'>-#define	CGTS_USER_TCC_DISABLE				0x2453</div><div class='del'>-#define		TCC_DISABLE_MASK				0xFFFF0000</div><div class='del'>-#define		TCC_DISABLE_SHIFT				16</div><div class='del'>-#define	CGTS_SM_CTRL_REG				0x2454</div><div class='del'>-#define		OVERRIDE				(1 &lt;&lt; 21)</div><div class='del'>-#define		LS_OVERRIDE				(1 &lt;&lt; 22)</div><div class='del'>-</div><div class='del'>-#define	SPI_LB_CU_MASK					0x24D5</div><div class='del'>-</div><div class='ctx'> #define	TA_CNTL_AUX					0x2542</div><div class='ctx'> </div><div class='del'>-#define CC_RB_BACKEND_DISABLE				0x263D</div><div class='del'>-#define		BACKEND_DISABLE(x)     			((x) &lt;&lt; 16)</div><div class='del'>-#define GB_ADDR_CONFIG  				0x263E</div><div class='del'>-#define		NUM_PIPES(x)				((x) &lt;&lt; 0)</div><div class='del'>-#define		NUM_PIPES_MASK				0x00000007</div><div class='del'>-#define		NUM_PIPES_SHIFT				0</div><div class='del'>-#define		PIPE_INTERLEAVE_SIZE(x)			((x) &lt;&lt; 4)</div><div class='del'>-#define		PIPE_INTERLEAVE_SIZE_MASK		0x00000070</div><div class='del'>-#define		PIPE_INTERLEAVE_SIZE_SHIFT		4</div><div class='del'>-#define		NUM_SHADER_ENGINES(x)			((x) &lt;&lt; 12)</div><div class='del'>-#define		NUM_SHADER_ENGINES_MASK			0x00003000</div><div class='del'>-#define		NUM_SHADER_ENGINES_SHIFT		12</div><div class='del'>-#define		SHADER_ENGINE_TILE_SIZE(x)     		((x) &lt;&lt; 16)</div><div class='del'>-#define		SHADER_ENGINE_TILE_SIZE_MASK		0x00070000</div><div class='del'>-#define		SHADER_ENGINE_TILE_SIZE_SHIFT		16</div><div class='del'>-#define		NUM_GPUS(x)     			((x) &lt;&lt; 20)</div><div class='del'>-#define		NUM_GPUS_MASK				0x00700000</div><div class='del'>-#define		NUM_GPUS_SHIFT				20</div><div class='del'>-#define		MULTI_GPU_TILE_SIZE(x)     		((x) &lt;&lt; 24)</div><div class='del'>-#define		MULTI_GPU_TILE_SIZE_MASK		0x03000000</div><div class='del'>-#define		MULTI_GPU_TILE_SIZE_SHIFT		24</div><div class='del'>-#define		ROW_SIZE(x)             		((x) &lt;&lt; 28)</div><div class='del'>-#define		ROW_SIZE_MASK				0x30000000</div><div class='del'>-#define		ROW_SIZE_SHIFT				28</div><div class='del'>-</div><div class='del'>-#define	GB_TILE_MODE0					0x2644</div><div class='del'>-#       define MICRO_TILE_MODE(x)				((x) &lt;&lt; 0)</div><div class='del'>-#              define	ADDR_SURF_DISPLAY_MICRO_TILING		0</div><div class='del'>-#              define	ADDR_SURF_THIN_MICRO_TILING		1</div><div class='del'>-#              define	ADDR_SURF_DEPTH_MICRO_TILING		2</div><div class='del'>-#       define ARRAY_MODE(x)					((x) &lt;&lt; 2)</div><div class='del'>-#              define	ARRAY_LINEAR_GENERAL			0</div><div class='del'>-#              define	ARRAY_LINEAR_ALIGNED			1</div><div class='del'>-#              define	ARRAY_1D_TILED_THIN1			2</div><div class='del'>-#              define	ARRAY_2D_TILED_THIN1			4</div><div class='del'>-#       define PIPE_CONFIG(x)					((x) &lt;&lt; 6)</div><div class='del'>-#              define	ADDR_SURF_P2				0</div><div class='del'>-#              define	ADDR_SURF_P4_8x16			4</div><div class='del'>-#              define	ADDR_SURF_P4_16x16			5</div><div class='del'>-#              define	ADDR_SURF_P4_16x32			6</div><div class='del'>-#              define	ADDR_SURF_P4_32x32			7</div><div class='del'>-#              define	ADDR_SURF_P8_16x16_8x16			8</div><div class='del'>-#              define	ADDR_SURF_P8_16x32_8x16			9</div><div class='del'>-#              define	ADDR_SURF_P8_32x32_8x16			10</div><div class='del'>-#              define	ADDR_SURF_P8_16x32_16x16		11</div><div class='del'>-#              define	ADDR_SURF_P8_32x32_16x16		12</div><div class='del'>-#              define	ADDR_SURF_P8_32x32_16x32		13</div><div class='del'>-#              define	ADDR_SURF_P8_32x64_32x32		14</div><div class='del'>-#       define TILE_SPLIT(x)					((x) &lt;&lt; 11)</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_64B		0</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_128B		1</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_256B		2</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_512B		3</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_1KB		4</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_2KB		5</div><div class='del'>-#              define	ADDR_SURF_TILE_SPLIT_4KB		6</div><div class='del'>-#       define BANK_WIDTH(x)					((x) &lt;&lt; 14)</div><div class='del'>-#              define	ADDR_SURF_BANK_WIDTH_1			0</div><div class='del'>-#              define	ADDR_SURF_BANK_WIDTH_2			1</div><div class='del'>-#              define	ADDR_SURF_BANK_WIDTH_4			2</div><div class='del'>-#              define	ADDR_SURF_BANK_WIDTH_8			3</div><div class='del'>-#       define BANK_HEIGHT(x)					((x) &lt;&lt; 16)</div><div class='del'>-#              define	ADDR_SURF_BANK_HEIGHT_1			0</div><div class='del'>-#              define	ADDR_SURF_BANK_HEIGHT_2			1</div><div class='del'>-#              define	ADDR_SURF_BANK_HEIGHT_4			2</div><div class='del'>-#              define	ADDR_SURF_BANK_HEIGHT_8			3</div><div class='del'>-#       define MACRO_TILE_ASPECT(x)				((x) &lt;&lt; 18)</div><div class='del'>-#              define	ADDR_SURF_MACRO_ASPECT_1		0</div><div class='del'>-#              define	ADDR_SURF_MACRO_ASPECT_2		1</div><div class='del'>-#              define	ADDR_SURF_MACRO_ASPECT_4		2</div><div class='del'>-#              define	ADDR_SURF_MACRO_ASPECT_8		3</div><div class='del'>-#       define NUM_BANKS(x)					((x) &lt;&lt; 20)</div><div class='del'>-#              define	ADDR_SURF_2_BANK			0</div><div class='del'>-#              define	ADDR_SURF_4_BANK			1</div><div class='del'>-#              define	ADDR_SURF_8_BANK			2</div><div class='del'>-#              define	ADDR_SURF_16_BANK			3</div><div class='del'>-#define	GB_TILE_MODE1					0x2645</div><div class='del'>-#define	GB_TILE_MODE2					0x2646</div><div class='del'>-#define	GB_TILE_MODE3					0x2647</div><div class='del'>-#define	GB_TILE_MODE4					0x2648</div><div class='del'>-#define	GB_TILE_MODE5					0x2649</div><div class='del'>-#define	GB_TILE_MODE6					0x264a</div><div class='del'>-#define	GB_TILE_MODE7					0x264b</div><div class='del'>-#define	GB_TILE_MODE8					0x264c</div><div class='del'>-#define	GB_TILE_MODE9					0x264d</div><div class='del'>-#define	GB_TILE_MODE10					0x264e</div><div class='del'>-#define	GB_TILE_MODE11					0x264f</div><div class='del'>-#define	GB_TILE_MODE12					0x2650</div><div class='del'>-#define	GB_TILE_MODE13					0x2651</div><div class='del'>-#define	GB_TILE_MODE14					0x2652</div><div class='del'>-#define	GB_TILE_MODE15					0x2653</div><div class='del'>-#define	GB_TILE_MODE16					0x2654</div><div class='del'>-#define	GB_TILE_MODE17					0x2655</div><div class='del'>-#define	GB_TILE_MODE18					0x2656</div><div class='del'>-#define	GB_TILE_MODE19					0x2657</div><div class='del'>-#define	GB_TILE_MODE20					0x2658</div><div class='del'>-#define	GB_TILE_MODE21					0x2659</div><div class='del'>-#define	GB_TILE_MODE22					0x265a</div><div class='del'>-#define	GB_TILE_MODE23					0x265b</div><div class='del'>-#define	GB_TILE_MODE24					0x265c</div><div class='del'>-#define	GB_TILE_MODE25					0x265d</div><div class='del'>-#define	GB_TILE_MODE26					0x265e</div><div class='del'>-#define	GB_TILE_MODE27					0x265f</div><div class='del'>-#define	GB_TILE_MODE28					0x2660</div><div class='del'>-#define	GB_TILE_MODE29					0x2661</div><div class='del'>-#define	GB_TILE_MODE30					0x2662</div><div class='del'>-#define	GB_TILE_MODE31					0x2663</div><div class='del'>-</div><div class='del'>-#define	CB_PERFCOUNTER0_SELECT0				0x2688</div><div class='del'>-#define	CB_PERFCOUNTER0_SELECT1				0x2689</div><div class='del'>-#define	CB_PERFCOUNTER1_SELECT0				0x268A</div><div class='del'>-#define	CB_PERFCOUNTER1_SELECT1				0x268B</div><div class='del'>-#define	CB_PERFCOUNTER2_SELECT0				0x268C</div><div class='del'>-#define	CB_PERFCOUNTER2_SELECT1				0x268D</div><div class='del'>-#define	CB_PERFCOUNTER3_SELECT0				0x268E</div><div class='del'>-#define	CB_PERFCOUNTER3_SELECT1				0x268F</div><div class='del'>-</div><div class='del'>-#define	CB_CGTT_SCLK_CTRL				0x2698</div><div class='del'>-</div><div class='del'>-#define	GC_USER_RB_BACKEND_DISABLE			0x26DF</div><div class='del'>-#define		BACKEND_DISABLE_MASK			0x00FF0000</div><div class='del'>-#define		BACKEND_DISABLE_SHIFT			16</div><div class='del'>-</div><div class='del'>-#define	TCP_CHAN_STEER_LO				0x2B03</div><div class='del'>-#define	TCP_CHAN_STEER_HI				0x2B94</div><div class='del'>-</div><div class='del'>-#define	CP_RB0_BASE					0x3040</div><div class='del'>-#define	CP_RB0_CNTL					0x3041</div><div class='del'>-#define		RB_BUFSZ(x)					((x) &lt;&lt; 0)</div><div class='del'>-#define		RB_BLKSZ(x)					((x) &lt;&lt; 8)</div><div class='del'>-#define		BUF_SWAP_32BIT					(2 &lt;&lt; 16)</div><div class='del'>-#define		RB_NO_UPDATE					(1 &lt;&lt; 27)</div><div class='del'>-#define		RB_RPTR_WR_ENA					(1 &lt;&lt; 31)</div><div class='del'>-</div><div class='del'>-#define	CP_RB0_RPTR_ADDR				0x3043</div><div class='del'>-#define	CP_RB0_RPTR_ADDR_HI				0x3044</div><div class='del'>-#define	CP_RB0_WPTR					0x3045</div><div class='del'>-</div><div class='del'>-#define	CP_PFP_UCODE_ADDR				0x3054</div><div class='del'>-#define	CP_PFP_UCODE_DATA				0x3055</div><div class='del'>-#define	CP_ME_RAM_RADDR					0x3056</div><div class='del'>-#define	CP_ME_RAM_WADDR					0x3057</div><div class='del'>-#define	CP_ME_RAM_DATA					0x3058</div><div class='del'>-</div><div class='del'>-#define	CP_CE_UCODE_ADDR				0x305A</div><div class='del'>-#define	CP_CE_UCODE_DATA				0x305B</div><div class='del'>-</div><div class='del'>-#define	CP_RB1_BASE					0x3060</div><div class='del'>-#define	CP_RB1_CNTL					0x3061</div><div class='del'>-#define	CP_RB1_RPTR_ADDR				0x3062</div><div class='del'>-#define	CP_RB1_RPTR_ADDR_HI				0x3063</div><div class='del'>-#define	CP_RB1_WPTR					0x3064</div><div class='del'>-#define	CP_RB2_BASE					0x3065</div><div class='del'>-#define	CP_RB2_CNTL					0x3066</div><div class='del'>-#define	CP_RB2_RPTR_ADDR				0x3067</div><div class='del'>-#define	CP_RB2_RPTR_ADDR_HI				0x3068</div><div class='del'>-#define	CP_RB2_WPTR					0x3069</div><div class='del'>-#define CP_INT_CNTL_RING0                               0x306A</div><div class='del'>-#define CP_INT_CNTL_RING1                               0x306B</div><div class='del'>-#define CP_INT_CNTL_RING2                               0x306C</div><div class='del'>-#       define CNTX_BUSY_INT_ENABLE                     (1 &lt;&lt; 19)</div><div class='del'>-#       define CNTX_EMPTY_INT_ENABLE                    (1 &lt;&lt; 20)</div><div class='del'>-#       define WAIT_MEM_SEM_INT_ENABLE                  (1 &lt;&lt; 21)</div><div class='del'>-#       define TIME_STAMP_INT_ENABLE                    (1 &lt;&lt; 26)</div><div class='del'>-#       define CP_RINGID2_INT_ENABLE                    (1 &lt;&lt; 29)</div><div class='del'>-#       define CP_RINGID1_INT_ENABLE                    (1 &lt;&lt; 30)</div><div class='del'>-#       define CP_RINGID0_INT_ENABLE                    (1 &lt;&lt; 31)</div><div class='del'>-#define CP_INT_STATUS_RING0                             0x306D</div><div class='del'>-#define CP_INT_STATUS_RING1                             0x306E</div><div class='del'>-#define CP_INT_STATUS_RING2                             0x306F</div><div class='del'>-#       define WAIT_MEM_SEM_INT_STAT                    (1 &lt;&lt; 21)</div><div class='del'>-#       define TIME_STAMP_INT_STAT                      (1 &lt;&lt; 26)</div><div class='del'>-#       define CP_RINGID2_INT_STAT                      (1 &lt;&lt; 29)</div><div class='del'>-#       define CP_RINGID1_INT_STAT                      (1 &lt;&lt; 30)</div><div class='del'>-#       define CP_RINGID0_INT_STAT                      (1 &lt;&lt; 31)</div><div class='del'>-</div><div class='del'>-#define	CP_MEM_SLP_CNTL					0x3079</div><div class='del'>-#       define CP_MEM_LS_EN                             (1 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-#define	CP_DEBUG					0x307F</div><div class='del'>-</div><div class='del'>-#define RLC_CNTL                                          0x30C0</div><div class='del'>-#       define RLC_ENABLE                                 (1 &lt;&lt; 0)</div><div class='del'>-#define RLC_RL_BASE                                       0x30C1</div><div class='del'>-#define RLC_RL_SIZE                                       0x30C2</div><div class='del'>-#define RLC_LB_CNTL                                       0x30C3</div><div class='del'>-#       define LOAD_BALANCE_ENABLE                        (1 &lt;&lt; 0)</div><div class='del'>-#define RLC_SAVE_AND_RESTORE_BASE                         0x30C4</div><div class='del'>-#define RLC_LB_CNTR_MAX                                   0x30C5</div><div class='del'>-#define RLC_LB_CNTR_INIT                                  0x30C6</div><div class='del'>-</div><div class='del'>-#define RLC_CLEAR_STATE_RESTORE_BASE                      0x30C8</div><div class='del'>-</div><div class='del'>-#define RLC_UCODE_ADDR                                    0x30CB</div><div class='del'>-#define RLC_UCODE_DATA                                    0x30CC</div><div class='del'>-</div><div class='del'>-#define RLC_GPU_CLOCK_COUNT_LSB                           0x30CE</div><div class='del'>-#define RLC_GPU_CLOCK_COUNT_MSB                           0x30CF</div><div class='del'>-#define RLC_CAPTURE_GPU_CLOCK_COUNT                       0x30D0</div><div class='del'>-#define RLC_MC_CNTL                                       0x30D1</div><div class='del'>-#define RLC_UCODE_CNTL                                    0x30D2</div><div class='del'>-#define RLC_STAT                                          0x30D3</div><div class='del'>-#       define RLC_BUSY_STATUS                            (1 &lt;&lt; 0)</div><div class='del'>-#       define GFX_POWER_STATUS                           (1 &lt;&lt; 1)</div><div class='del'>-#       define GFX_CLOCK_STATUS                           (1 &lt;&lt; 2)</div><div class='del'>-#       define GFX_LS_STATUS                              (1 &lt;&lt; 3)</div><div class='del'>-</div><div class='del'>-#define	RLC_PG_CNTL					0x30D7</div><div class='del'>-#	define GFX_PG_ENABLE				(1 &lt;&lt; 0)</div><div class='del'>-#	define GFX_PG_SRC				(1 &lt;&lt; 1)</div><div class='del'>-</div><div class='del'>-#define	RLC_CGTT_MGCG_OVERRIDE				0x3100</div><div class='del'>-#define	RLC_CGCG_CGLS_CTRL				0x3101</div><div class='del'>-#	define CGCG_EN					(1 &lt;&lt; 0)</div><div class='del'>-#	define CGLS_EN					(1 &lt;&lt; 1)</div><div class='del'>-</div><div class='del'>-#define	RLC_TTOP_D					0x3105</div><div class='del'>-#	define RLC_PUD(x)				((x) &lt;&lt; 0)</div><div class='del'>-#	define RLC_PUD_MASK				(0xff &lt;&lt; 0)</div><div class='del'>-#	define RLC_PDD(x)				((x) &lt;&lt; 8)</div><div class='del'>-#	define RLC_PDD_MASK				(0xff &lt;&lt; 8)</div><div class='del'>-#	define RLC_TTPD(x)				((x) &lt;&lt; 16)</div><div class='del'>-#	define RLC_TTPD_MASK				(0xff &lt;&lt; 16)</div><div class='del'>-#	define RLC_MSD(x)				((x) &lt;&lt; 24)</div><div class='del'>-#	define RLC_MSD_MASK				(0xff &lt;&lt; 24)</div><div class='del'>-</div><div class='del'>-#define RLC_LB_INIT_CU_MASK                               0x3107</div><div class='del'>-</div><div class='del'>-#define	RLC_PG_AO_CU_MASK				0x310B</div><div class='del'>-#define	RLC_MAX_PG_CU					0x310C</div><div class='del'>-#	define MAX_PU_CU(x)				((x) &lt;&lt; 0)</div><div class='del'>-#	define MAX_PU_CU_MASK				(0xff &lt;&lt; 0)</div><div class='del'>-#define	RLC_AUTO_PG_CTRL				0x310C</div><div class='del'>-#	define AUTO_PG_EN				(1 &lt;&lt; 0)</div><div class='del'>-#	define GRBM_REG_SGIT(x)				((x) &lt;&lt; 3)</div><div class='del'>-#	define GRBM_REG_SGIT_MASK			(0xffff &lt;&lt; 3)</div><div class='del'>-#	define PG_AFTER_GRBM_REG_ST(x)			((x) &lt;&lt; 19)</div><div class='del'>-#	define PG_AFTER_GRBM_REG_ST_MASK		(0x1fff &lt;&lt; 19)</div><div class='del'>-</div><div class='del'>-#define RLC_SERDES_WR_MASTER_MASK_0                       0x3115</div><div class='del'>-#define RLC_SERDES_WR_MASTER_MASK_1                       0x3116</div><div class='del'>-#define RLC_SERDES_WR_CTRL                                0x3117</div><div class='del'>-</div><div class='del'>-#define RLC_SERDES_MASTER_BUSY_0                          0x3119</div><div class='del'>-#define RLC_SERDES_MASTER_BUSY_1                          0x311A</div><div class='del'>-</div><div class='del'>-#define RLC_GCPM_GENERAL_3                                0x311E</div><div class='del'>-</div><div class='del'>-#define	DB_RENDER_CONTROL				0xA000</div><div class='del'>-</div><div class='del'>-#define DB_DEPTH_INFO                                   0xA00F</div><div class='del'>-</div><div class='del'>-#define PA_SC_RASTER_CONFIG                             0xA0D4</div><div class='del'>-#	define RB_MAP_PKR0(x)				((x) &lt;&lt; 0)</div><div class='del'>-#	define RB_MAP_PKR0_MASK				(0x3 &lt;&lt; 0)</div><div class='del'>-#	define RB_MAP_PKR1(x)				((x) &lt;&lt; 2)</div><div class='del'>-#	define RB_MAP_PKR1_MASK				(0x3 &lt;&lt; 2)</div><div class='del'>-#       define RASTER_CONFIG_RB_MAP_0                   0</div><div class='del'>-#       define RASTER_CONFIG_RB_MAP_1                   1</div><div class='del'>-#       define RASTER_CONFIG_RB_MAP_2                   2</div><div class='del'>-#       define RASTER_CONFIG_RB_MAP_3                   3</div><div class='add'>+// #define PA_SC_RASTER_CONFIG                             0xA0D4</div><div class='ctx'> #	define RB_XSEL2(x)				((x) &lt;&lt; 4)</div><div class='ctx'> #	define RB_XSEL2_MASK				(0x3 &lt;&lt; 4)</div><div class='ctx'> #	define RB_XSEL					(1 &lt;&lt; 6)</div><div class='ctx'> #	define RB_YSEL					(1 &lt;&lt; 7)</div><div class='ctx'> #	define PKR_MAP(x)				((x) &lt;&lt; 8)</div><div class='del'>-#	define PKR_MAP_MASK				(0x3 &lt;&lt; 8)</div><div class='del'>-#       define RASTER_CONFIG_PKR_MAP_0			0</div><div class='del'>-#       define RASTER_CONFIG_PKR_MAP_1			1</div><div class='del'>-#       define RASTER_CONFIG_PKR_MAP_2			2</div><div class='del'>-#       define RASTER_CONFIG_PKR_MAP_3			3</div><div class='ctx'> #	define PKR_XSEL(x)				((x) &lt;&lt; 10)</div><div class='ctx'> #	define PKR_XSEL_MASK				(0x3 &lt;&lt; 10)</div><div class='ctx'> #	define PKR_YSEL(x)				((x) &lt;&lt; 12)</div><div class='hunk'>@@ -1426,221 +306,19 @@</div><div class='ctx'> #	define SC_YSEL(x)				((x) &lt;&lt; 20)</div><div class='ctx'> #	define SC_YSEL_MASK				(0x3 &lt;&lt; 20)</div><div class='ctx'> #	define SE_MAP(x)				((x) &lt;&lt; 24)</div><div class='del'>-#	define SE_MAP_MASK				(0x3 &lt;&lt; 24)</div><div class='del'>-#       define RASTER_CONFIG_SE_MAP_0			0</div><div class='del'>-#       define RASTER_CONFIG_SE_MAP_1			1</div><div class='del'>-#       define RASTER_CONFIG_SE_MAP_2			2</div><div class='del'>-#       define RASTER_CONFIG_SE_MAP_3			3</div><div class='ctx'> #	define SE_XSEL(x)				((x) &lt;&lt; 26)</div><div class='ctx'> #	define SE_XSEL_MASK				(0x3 &lt;&lt; 26)</div><div class='ctx'> #	define SE_YSEL(x)				((x) &lt;&lt; 28)</div><div class='ctx'> #	define SE_YSEL_MASK				(0x3 &lt;&lt; 28)</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-#define VGT_EVENT_INITIATOR                             0xA2A4</div><div class='del'>-#       define SAMPLE_STREAMOUTSTATS1                   (1 &lt;&lt; 0)</div><div class='del'>-#       define SAMPLE_STREAMOUTSTATS2                   (2 &lt;&lt; 0)</div><div class='del'>-#       define SAMPLE_STREAMOUTSTATS3                   (3 &lt;&lt; 0)</div><div class='del'>-#       define CACHE_FLUSH_TS                           (4 &lt;&lt; 0)</div><div class='del'>-#       define CACHE_FLUSH                              (6 &lt;&lt; 0)</div><div class='del'>-#       define CS_PARTIAL_FLUSH                         (7 &lt;&lt; 0)</div><div class='del'>-#       define VGT_STREAMOUT_RESET                      (10 &lt;&lt; 0)</div><div class='del'>-#       define END_OF_PIPE_INCR_DE                      (11 &lt;&lt; 0)</div><div class='del'>-#       define END_OF_PIPE_IB_END                       (12 &lt;&lt; 0)</div><div class='del'>-#       define RST_PIX_CNT                              (13 &lt;&lt; 0)</div><div class='del'>-#       define VS_PARTIAL_FLUSH                         (15 &lt;&lt; 0)</div><div class='del'>-#       define PS_PARTIAL_FLUSH                         (16 &lt;&lt; 0)</div><div class='del'>-#       define CACHE_FLUSH_AND_INV_TS_EVENT             (20 &lt;&lt; 0)</div><div class='del'>-#       define ZPASS_DONE                               (21 &lt;&lt; 0)</div><div class='del'>-#       define CACHE_FLUSH_AND_INV_EVENT                (22 &lt;&lt; 0)</div><div class='del'>-#       define PERFCOUNTER_START                        (23 &lt;&lt; 0)</div><div class='del'>-#       define PERFCOUNTER_STOP                         (24 &lt;&lt; 0)</div><div class='del'>-#       define PIPELINESTAT_START                       (25 &lt;&lt; 0)</div><div class='del'>-#       define PIPELINESTAT_STOP                        (26 &lt;&lt; 0)</div><div class='del'>-#       define PERFCOUNTER_SAMPLE                       (27 &lt;&lt; 0)</div><div class='del'>-#       define SAMPLE_PIPELINESTAT                      (30 &lt;&lt; 0)</div><div class='del'>-#       define SAMPLE_STREAMOUTSTATS                    (32 &lt;&lt; 0)</div><div class='del'>-#       define RESET_VTX_CNT                            (33 &lt;&lt; 0)</div><div class='del'>-#       define VGT_FLUSH                                (36 &lt;&lt; 0)</div><div class='del'>-#       define BOTTOM_OF_PIPE_TS                        (40 &lt;&lt; 0)</div><div class='del'>-#       define DB_CACHE_FLUSH_AND_INV                   (42 &lt;&lt; 0)</div><div class='del'>-#       define FLUSH_AND_INV_DB_DATA_TS                 (43 &lt;&lt; 0)</div><div class='del'>-#       define FLUSH_AND_INV_DB_META                    (44 &lt;&lt; 0)</div><div class='del'>-#       define FLUSH_AND_INV_CB_DATA_TS                 (45 &lt;&lt; 0)</div><div class='del'>-#       define FLUSH_AND_INV_CB_META                    (46 &lt;&lt; 0)</div><div class='del'>-#       define CS_DONE                                  (47 &lt;&lt; 0)</div><div class='del'>-#       define PS_DONE                                  (48 &lt;&lt; 0)</div><div class='del'>-#       define FLUSH_AND_INV_CB_PIXEL_DATA              (49 &lt;&lt; 0)</div><div class='del'>-#       define THREAD_TRACE_START                       (51 &lt;&lt; 0)</div><div class='del'>-#       define THREAD_TRACE_STOP                        (52 &lt;&lt; 0)</div><div class='del'>-#       define THREAD_TRACE_FLUSH                       (54 &lt;&lt; 0)</div><div class='del'>-#       define THREAD_TRACE_FINISH                      (55 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-/* PIF PHY0 registers idx/data 0x8/0xc */</div><div class='del'>-#define PB0_PIF_CNTL                                      0x10</div><div class='del'>-#       define LS2_EXIT_TIME(x)                           ((x) &lt;&lt; 17)</div><div class='del'>-#       define LS2_EXIT_TIME_MASK                         (0x7 &lt;&lt; 17)</div><div class='del'>-#       define LS2_EXIT_TIME_SHIFT                        17</div><div class='del'>-#define PB0_PIF_PAIRING                                   0x11</div><div class='del'>-#       define MULTI_PIF                                  (1 &lt;&lt; 25)</div><div class='del'>-#define PB0_PIF_PWRDOWN_0                                 0x12</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_0_MASK             (0x7 &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_0_SHIFT            7</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_0(x)                ((x) &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_0_MASK              (0x7 &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_0_SHIFT             10</div><div class='del'>-#       define PLL_RAMP_UP_TIME_0(x)                      ((x) &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_0_MASK                    (0x7 &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_0_SHIFT                   24</div><div class='del'>-#define PB0_PIF_PWRDOWN_1                                 0x13</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_1(x)               ((x) &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_1_MASK             (0x7 &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_1_SHIFT            7</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_1(x)                ((x) &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_1_MASK              (0x7 &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_1_SHIFT             10</div><div class='del'>-#       define PLL_RAMP_UP_TIME_1(x)                      ((x) &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_1_MASK                    (0x7 &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_1_SHIFT                   24</div><div class='del'>-</div><div class='del'>-#define PB0_PIF_PWRDOWN_2                                 0x17</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_2(x)               ((x) &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_2_MASK             (0x7 &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_2_SHIFT            7</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_2(x)                ((x) &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_2_MASK              (0x7 &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_2_SHIFT             10</div><div class='del'>-#       define PLL_RAMP_UP_TIME_2(x)                      ((x) &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_2_MASK                    (0x7 &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_2_SHIFT                   24</div><div class='del'>-#define PB0_PIF_PWRDOWN_3                                 0x18</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_3(x)               ((x) &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_3_MASK             (0x7 &lt;&lt; 7)</div><div class='del'>-#       define PLL_POWER_STATE_IN_TXS2_3_SHIFT            7</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_3(x)                ((x) &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_3_MASK              (0x7 &lt;&lt; 10)</div><div class='del'>-#       define PLL_POWER_STATE_IN_OFF_3_SHIFT             10</div><div class='del'>-#       define PLL_RAMP_UP_TIME_3(x)                      ((x) &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_3_MASK                    (0x7 &lt;&lt; 24)</div><div class='del'>-#       define PLL_RAMP_UP_TIME_3_SHIFT                   24</div><div class='del'>-/* PIF PHY1 registers idx/data 0x10/0x14 */</div><div class='del'>-#define PB1_PIF_CNTL                                      0x10</div><div class='del'>-#define PB1_PIF_PAIRING                                   0x11</div><div class='del'>-#define PB1_PIF_PWRDOWN_0                                 0x12</div><div class='del'>-#define PB1_PIF_PWRDOWN_1                                 0x13</div><div class='del'>-</div><div class='del'>-#define PB1_PIF_PWRDOWN_2                                 0x17</div><div class='del'>-#define PB1_PIF_PWRDOWN_3                                 0x18</div><div class='del'>-/* PCIE registers idx/data 0x30/0x34 */</div><div class='del'>-#define PCIE_CNTL2                                        0x1c /* PCIE */</div><div class='del'>-#       define SLV_MEM_LS_EN                              (1 &lt;&lt; 16)</div><div class='del'>-#       define SLV_MEM_AGGRESSIVE_LS_EN                   (1 &lt;&lt; 17)</div><div class='del'>-#       define MST_MEM_LS_EN                              (1 &lt;&lt; 18)</div><div class='del'>-#       define REPLAY_MEM_LS_EN                           (1 &lt;&lt; 19)</div><div class='del'>-#define PCIE_LC_STATUS1                                   0x28 /* PCIE */</div><div class='del'>-#       define LC_REVERSE_RCVR                            (1 &lt;&lt; 0)</div><div class='del'>-#       define LC_REVERSE_XMIT                            (1 &lt;&lt; 1)</div><div class='del'>-#       define LC_OPERATING_LINK_WIDTH_MASK               (0x7 &lt;&lt; 2)</div><div class='del'>-#       define LC_OPERATING_LINK_WIDTH_SHIFT              2</div><div class='del'>-#       define LC_DETECTED_LINK_WIDTH_MASK                (0x7 &lt;&lt; 5)</div><div class='del'>-#       define LC_DETECTED_LINK_WIDTH_SHIFT               5</div><div class='del'>-</div><div class='del'>-#define PCIE_P_CNTL                                       0x40 /* PCIE */</div><div class='del'>-#       define P_IGNORE_EDB_ERR                           (1 &lt;&lt; 6)</div><div class='del'>-</div><div class='ctx'> /* PCIE PORT registers idx/data 0x38/0x3c */</div><div class='del'>-#define PCIE_LC_CNTL                                      0xa0</div><div class='del'>-#       define LC_L0S_INACTIVITY(x)                       ((x) &lt;&lt; 8)</div><div class='del'>-#       define LC_L0S_INACTIVITY_MASK                     (0xf &lt;&lt; 8)</div><div class='del'>-#       define LC_L0S_INACTIVITY_SHIFT                    8</div><div class='del'>-#       define LC_L1_INACTIVITY(x)                        ((x) &lt;&lt; 12)</div><div class='del'>-#       define LC_L1_INACTIVITY_MASK                      (0xf &lt;&lt; 12)</div><div class='del'>-#       define LC_L1_INACTIVITY_SHIFT                     12</div><div class='del'>-#       define LC_PMI_TO_L1_DIS                           (1 &lt;&lt; 16)</div><div class='del'>-#       define LC_ASPM_TO_L1_DIS                          (1 &lt;&lt; 24)</div><div class='del'>-#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */</div><div class='del'>-#       define LC_LINK_WIDTH_SHIFT                        0</div><div class='del'>-#       define LC_LINK_WIDTH_MASK                         0x7</div><div class='add'>+// #define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */</div><div class='ctx'> #       define LC_LINK_WIDTH_X0                           0</div><div class='ctx'> #       define LC_LINK_WIDTH_X1                           1</div><div class='ctx'> #       define LC_LINK_WIDTH_X2                           2</div><div class='ctx'> #       define LC_LINK_WIDTH_X4                           3</div><div class='ctx'> #       define LC_LINK_WIDTH_X8                           4</div><div class='ctx'> #       define LC_LINK_WIDTH_X16                          6</div><div class='del'>-#       define LC_LINK_WIDTH_RD_SHIFT                     4</div><div class='del'>-#       define LC_LINK_WIDTH_RD_MASK                      0x70</div><div class='del'>-#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 &lt;&lt; 7)</div><div class='del'>-#       define LC_RECONFIG_NOW                            (1 &lt;&lt; 8)</div><div class='del'>-#       define LC_RENEGOTIATION_SUPPORT                   (1 &lt;&lt; 9)</div><div class='del'>-#       define LC_RENEGOTIATE_EN                          (1 &lt;&lt; 10)</div><div class='del'>-#       define LC_SHORT_RECONFIG_EN                       (1 &lt;&lt; 11)</div><div class='del'>-#       define LC_UPCONFIGURE_SUPPORT                     (1 &lt;&lt; 12)</div><div class='del'>-#       define LC_UPCONFIGURE_DIS                         (1 &lt;&lt; 13)</div><div class='del'>-#       define LC_DYN_LANES_PWR_STATE(x)                  ((x) &lt;&lt; 21)</div><div class='del'>-#       define LC_DYN_LANES_PWR_STATE_MASK                (0x3 &lt;&lt; 21)</div><div class='del'>-#       define LC_DYN_LANES_PWR_STATE_SHIFT               21</div><div class='del'>-#define PCIE_LC_N_FTS_CNTL                                0xa3 /* PCIE_P */</div><div class='del'>-#       define LC_XMIT_N_FTS(x)                           ((x) &lt;&lt; 0)</div><div class='del'>-#       define LC_XMIT_N_FTS_MASK                         (0xff &lt;&lt; 0)</div><div class='del'>-#       define LC_XMIT_N_FTS_SHIFT                        0</div><div class='del'>-#       define LC_XMIT_N_FTS_OVERRIDE_EN                  (1 &lt;&lt; 8)</div><div class='del'>-#       define LC_N_FTS_MASK                              (0xff &lt;&lt; 24)</div><div class='del'>-#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */</div><div class='del'>-#       define LC_GEN2_EN_STRAP                           (1 &lt;&lt; 0)</div><div class='del'>-#       define LC_GEN3_EN_STRAP                           (1 &lt;&lt; 1)</div><div class='del'>-#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 &lt;&lt; 2)</div><div class='del'>-#       define LC_TARGET_LINK_SPEED_OVERRIDE_MASK         (0x3 &lt;&lt; 3)</div><div class='del'>-#       define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT        3</div><div class='del'>-#       define LC_FORCE_EN_SW_SPEED_CHANGE                (1 &lt;&lt; 5)</div><div class='del'>-#       define LC_FORCE_DIS_SW_SPEED_CHANGE               (1 &lt;&lt; 6)</div><div class='del'>-#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 &lt;&lt; 7)</div><div class='del'>-#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 &lt;&lt; 8)</div><div class='del'>-#       define LC_INITIATE_LINK_SPEED_CHANGE              (1 &lt;&lt; 9)</div><div class='del'>-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 &lt;&lt; 10)</div><div class='del'>-#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     10</div><div class='del'>-#       define LC_CURRENT_DATA_RATE_MASK                  (0x3 &lt;&lt; 13) /* 0/1/2 = gen1/2/3 */</div><div class='del'>-#       define LC_CURRENT_DATA_RATE_SHIFT                 13</div><div class='del'>-#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 &lt;&lt; 16)</div><div class='del'>-#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 &lt;&lt; 18)</div><div class='del'>-#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 &lt;&lt; 19)</div><div class='del'>-#       define LC_OTHER_SIDE_EVER_SENT_GEN3               (1 &lt;&lt; 20)</div><div class='del'>-#       define LC_OTHER_SIDE_SUPPORTS_GEN3                (1 &lt;&lt; 21)</div><div class='del'>-</div><div class='del'>-#define PCIE_LC_CNTL2                                     0xb1</div><div class='del'>-#       define LC_ALLOW_PDWN_IN_L1                        (1 &lt;&lt; 17)</div><div class='del'>-#       define LC_ALLOW_PDWN_IN_L23                       (1 &lt;&lt; 18)</div><div class='del'>-</div><div class='del'>-#define PCIE_LC_CNTL3                                     0xb5 /* PCIE_P */</div><div class='del'>-#       define LC_GO_TO_RECOVERY                          (1 &lt;&lt; 30)</div><div class='del'>-#define PCIE_LC_CNTL4                                     0xb6 /* PCIE_P */</div><div class='del'>-#       define LC_REDO_EQ                                 (1 &lt;&lt; 5)</div><div class='del'>-#       define LC_SET_QUIESCE                             (1 &lt;&lt; 13)</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * UVD</div><div class='del'>- */</div><div class='del'>-#define UVD_UDEC_ADDR_CONFIG				0x3bd3</div><div class='del'>-#define UVD_UDEC_DB_ADDR_CONFIG				0x3bd4</div><div class='del'>-#define UVD_UDEC_DBW_ADDR_CONFIG			0x3bd5</div><div class='del'>-#define UVD_RBC_RB_RPTR					0x3da4</div><div class='del'>-#define UVD_RBC_RB_WPTR					0x3da5</div><div class='del'>-#define UVD_STATUS					0x3daf</div><div class='del'>-</div><div class='del'>-#define	UVD_CGC_CTRL					0x3dc2</div><div class='del'>-#	define DCM					(1 &lt;&lt; 0)</div><div class='del'>-#	define CG_DT(x)					((x) &lt;&lt; 2)</div><div class='del'>-#	define CG_DT_MASK				(0xf &lt;&lt; 2)</div><div class='del'>-#	define CLK_OD(x)				((x) &lt;&lt; 6)</div><div class='del'>-#	define CLK_OD_MASK				(0x1f &lt;&lt; 6)</div><div class='del'>-</div><div class='del'>- /* UVD CTX indirect */</div><div class='del'>-#define	UVD_CGC_MEM_CTRL				0xC0</div><div class='del'>-#define	UVD_CGC_CTRL2					0xC1</div><div class='del'>-#	define DYN_OR_EN				(1 &lt;&lt; 0)</div><div class='del'>-#	define DYN_RR_EN				(1 &lt;&lt; 1)</div><div class='del'>-#	define G_DIV_ID(x)				((x) &lt;&lt; 2)</div><div class='del'>-#	define G_DIV_ID_MASK				(0x7 &lt;&lt; 2)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * PM4</div><div class='hunk'>@@ -1874,45 +552,7 @@</div><div class='ctx'> /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */</div><div class='ctx'> #define DMA0_REGISTER_OFFSET                              0x0 /* not a register */</div><div class='ctx'> #define DMA1_REGISTER_OFFSET                              0x200 /* not a register */</div><div class='del'>-</div><div class='del'>-#define DMA_RB_CNTL                                       0x3400</div><div class='del'>-#       define DMA_RB_ENABLE                              (1 &lt;&lt; 0)</div><div class='del'>-#       define DMA_RB_SIZE(x)                             ((x) &lt;&lt; 1) /* log2 */</div><div class='del'>-#       define DMA_RB_SWAP_ENABLE                         (1 &lt;&lt; 9) /* 8IN32 */</div><div class='del'>-#       define DMA_RPTR_WRITEBACK_ENABLE                  (1 &lt;&lt; 12)</div><div class='del'>-#       define DMA_RPTR_WRITEBACK_SWAP_ENABLE             (1 &lt;&lt; 13)  /* 8IN32 */</div><div class='del'>-#       define DMA_RPTR_WRITEBACK_TIMER(x)                ((x) &lt;&lt; 16) /* log2 */</div><div class='del'>-#define DMA_RB_BASE                                       0x3401</div><div class='del'>-#define DMA_RB_RPTR                                       0x3402</div><div class='del'>-#define DMA_RB_WPTR                                       0x3403</div><div class='del'>-</div><div class='del'>-#define DMA_RB_RPTR_ADDR_HI                               0x3407</div><div class='del'>-#define DMA_RB_RPTR_ADDR_LO                               0x3408</div><div class='del'>-</div><div class='del'>-#define DMA_IB_CNTL                                       0x3409</div><div class='del'>-#       define DMA_IB_ENABLE                              (1 &lt;&lt; 0)</div><div class='del'>-#       define DMA_IB_SWAP_ENABLE                         (1 &lt;&lt; 4)</div><div class='del'>-#       define CMD_VMID_FORCE                             (1 &lt;&lt; 31)</div><div class='del'>-#define DMA_IB_RPTR                                       0x340a</div><div class='del'>-#define DMA_CNTL                                          0x340b</div><div class='del'>-#       define TRAP_ENABLE                                (1 &lt;&lt; 0)</div><div class='del'>-#       define SEM_INCOMPLETE_INT_ENABLE                  (1 &lt;&lt; 1)</div><div class='del'>-#       define SEM_WAIT_INT_ENABLE                        (1 &lt;&lt; 2)</div><div class='del'>-#       define DATA_SWAP_ENABLE                           (1 &lt;&lt; 3)</div><div class='del'>-#       define FENCE_SWAP_ENABLE                          (1 &lt;&lt; 4)</div><div class='del'>-#       define CTXEMPTY_INT_ENABLE                        (1 &lt;&lt; 28)</div><div class='del'>-#define DMA_STATUS_REG                                    0x340d</div><div class='del'>-#       define DMA_IDLE                                   (1 &lt;&lt; 0)</div><div class='del'>-#define DMA_TILING_CONFIG  				  0x342e</div><div class='del'>-</div><div class='del'>-#define	DMA_POWER_CNTL					0x342f</div><div class='del'>-#       define MEM_POWER_OVERRIDE                       (1 &lt;&lt; 8)</div><div class='del'>-#define	DMA_CLK_CTRL					0x3430</div><div class='del'>-</div><div class='del'>-#define	DMA_PG						0x3435</div><div class='del'>-#	define PG_CNTL_ENABLE				(1 &lt;&lt; 0)</div><div class='del'>-#define	DMA_PGFSM_CONFIG				0x3436</div><div class='del'>-#define	DMA_PGFSM_WRITE					0x3437</div><div class='add'>+#define SDMA_MAX_INSTANCE 2</div><div class='ctx'> </div><div class='ctx'> #define DMA_PACKET(cmd, b, t, s, n)	((((cmd) &amp; 0xF) &lt;&lt; 28) |	\</div><div class='ctx'> 					 (((b) &amp; 0x1) &lt;&lt; 26) |		\</div><div class='hunk'>@@ -1941,45 +581,7 @@</div><div class='ctx'> #define	DMA_PACKET_POLL_REG_MEM				  0xe</div><div class='ctx'> #define	DMA_PACKET_NOP					  0xf</div><div class='ctx'> </div><div class='del'>-#define VCE_STATUS					0x20004</div><div class='del'>-#define VCE_VCPU_CNTL					0x20014</div><div class='del'>-#define		VCE_CLK_EN				(1 &lt;&lt; 0)</div><div class='del'>-#define VCE_VCPU_CACHE_OFFSET0				0x20024</div><div class='del'>-#define VCE_VCPU_CACHE_SIZE0				0x20028</div><div class='del'>-#define VCE_VCPU_CACHE_OFFSET1				0x2002c</div><div class='del'>-#define VCE_VCPU_CACHE_SIZE1				0x20030</div><div class='del'>-#define VCE_VCPU_CACHE_OFFSET2				0x20034</div><div class='del'>-#define VCE_VCPU_CACHE_SIZE2				0x20038</div><div class='del'>-#define VCE_SOFT_RESET					0x20120</div><div class='del'>-#define 	VCE_ECPU_SOFT_RESET			(1 &lt;&lt; 0)</div><div class='del'>-#define 	VCE_FME_SOFT_RESET			(1 &lt;&lt; 2)</div><div class='del'>-#define VCE_RB_BASE_LO2					0x2016c</div><div class='del'>-#define VCE_RB_BASE_HI2					0x20170</div><div class='del'>-#define VCE_RB_SIZE2					0x20174</div><div class='del'>-#define VCE_RB_RPTR2					0x20178</div><div class='del'>-#define VCE_RB_WPTR2					0x2017c</div><div class='del'>-#define VCE_RB_BASE_LO					0x20180</div><div class='del'>-#define VCE_RB_BASE_HI					0x20184</div><div class='del'>-#define VCE_RB_SIZE					0x20188</div><div class='del'>-#define VCE_RB_RPTR					0x2018c</div><div class='del'>-#define VCE_RB_WPTR					0x20190</div><div class='del'>-#define VCE_CLOCK_GATING_A				0x202f8</div><div class='del'>-#define VCE_CLOCK_GATING_B				0x202fc</div><div class='del'>-#define VCE_UENC_CLOCK_GATING				0x205bc</div><div class='del'>-#define VCE_UENC_REG_CLOCK_GATING			0x205c0</div><div class='del'>-#define VCE_FW_REG_STATUS				0x20e10</div><div class='del'>-#	define VCE_FW_REG_STATUS_BUSY			(1 &lt;&lt; 0)</div><div class='del'>-#	define VCE_FW_REG_STATUS_PASS			(1 &lt;&lt; 3)</div><div class='del'>-#	define VCE_FW_REG_STATUS_DONE			(1 &lt;&lt; 11)</div><div class='del'>-#define VCE_LMI_FW_START_KEYSEL				0x20e18</div><div class='del'>-#define VCE_LMI_FW_PERIODIC_CTRL			0x20e20</div><div class='del'>-#define VCE_LMI_CTRL2					0x20e74</div><div class='del'>-#define VCE_LMI_CTRL					0x20e98</div><div class='del'>-#define VCE_LMI_VM_CTRL					0x20ea0</div><div class='del'>-#define VCE_LMI_SWAP_CNTL				0x20eb4</div><div class='del'>-#define VCE_LMI_SWAP_CNTL1				0x20eb8</div><div class='del'>-#define VCE_LMI_CACHE_CTRL				0x20ef4</div><div class='del'>-</div><div class='add'>+/* VCE */</div><div class='ctx'> #define VCE_CMD_NO_OP					0x00000000</div><div class='ctx'> #define VCE_CMD_END					0x00000001</div><div class='ctx'> #define VCE_CMD_IB					0x00000002</div><div class='hunk'>@@ -1988,434 +590,146 @@</div><div class='ctx'> #define VCE_CMD_IB_AUTO					0x00000005</div><div class='ctx'> #define VCE_CMD_SEMAPHORE				0x00000006</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> //#dce stupp</div><div class='ctx'> /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */</div><div class='del'>-#define SI_CRTC0_REGISTER_OFFSET                0 //(0x6df0 - 0x6df0)/4</div><div class='del'>-#define SI_CRTC1_REGISTER_OFFSET                0x300 //(0x79f0 - 0x6df0)/4</div><div class='del'>-#define SI_CRTC2_REGISTER_OFFSET                0x2600 //(0x105f0 - 0x6df0)/4</div><div class='del'>-#define SI_CRTC3_REGISTER_OFFSET                0x2900 //(0x111f0 - 0x6df0)/4</div><div class='del'>-#define SI_CRTC4_REGISTER_OFFSET                0x2c00 //(0x11df0 - 0x6df0)/4</div><div class='del'>-#define SI_CRTC5_REGISTER_OFFSET                0x2f00 //(0x129f0 - 0x6df0)/4</div><div class='add'>+#define CRTC0_REGISTER_OFFSET                 (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4</div><div class='add'>+#define CRTC1_REGISTER_OFFSET                 (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4</div><div class='add'>+#define CRTC2_REGISTER_OFFSET                 (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4</div><div class='add'>+#define CRTC3_REGISTER_OFFSET                 (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4</div><div class='add'>+#define CRTC4_REGISTER_OFFSET                 (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4</div><div class='add'>+#define CRTC5_REGISTER_OFFSET                 (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4</div><div class='add'>+</div><div class='add'>+/* hpd instance offsets */</div><div class='add'>+#define HPD0_REGISTER_OFFSET                 (0x1807 - 0x1807)</div><div class='add'>+#define HPD1_REGISTER_OFFSET                 (0x180a - 0x1807)</div><div class='add'>+#define HPD2_REGISTER_OFFSET                 (0x180d - 0x1807)</div><div class='add'>+#define HPD3_REGISTER_OFFSET                 (0x1810 - 0x1807)</div><div class='add'>+#define HPD4_REGISTER_OFFSET                 (0x1813 - 0x1807)</div><div class='add'>+#define HPD5_REGISTER_OFFSET                 (0x1816 - 0x1807)</div><div class='add'>+</div><div class='add'>+/* audio endpt instance offsets */</div><div class='add'>+#define AUD0_REGISTER_OFFSET                 (0x1780 - 0x1780)</div><div class='add'>+#define AUD1_REGISTER_OFFSET                 (0x1786 - 0x1780)</div><div class='add'>+#define AUD2_REGISTER_OFFSET                 (0x178c - 0x1780)</div><div class='add'>+#define AUD3_REGISTER_OFFSET                 (0x1792 - 0x1780)</div><div class='add'>+#define AUD4_REGISTER_OFFSET                 (0x1798 - 0x1780)</div><div class='add'>+#define AUD5_REGISTER_OFFSET                 (0x179d - 0x1780)</div><div class='add'>+#define AUD6_REGISTER_OFFSET                 (0x17a4 - 0x1780)</div><div class='ctx'> </div><div class='ctx'> #define CURSOR_WIDTH 64</div><div class='ctx'> #define CURSOR_HEIGHT 64</div><div class='del'>-#define AMDGPU_MM_INDEX		        0x0000</div><div class='del'>-#define AMDGPU_MM_DATA		        0x0001</div><div class='del'>-</div><div class='del'>-#define VERDE_NUM_CRTC 6</div><div class='del'>-#define	BLACKOUT_MODE_MASK			0x00000007</div><div class='del'>-#define	VGA_RENDER_CONTROL			0xC0</div><div class='del'>-#define R_000300_VGA_RENDER_CONTROL             0xC0</div><div class='del'>-#define C_000300_VGA_VSTATUS_CNTL               0xFFFCFFFF</div><div class='del'>-#define EVERGREEN_CRTC_STATUS                   0x1BA3</div><div class='del'>-#define EVERGREEN_CRTC_V_BLANK                  (1 &lt;&lt; 0)</div><div class='del'>-#define EVERGREEN_CRTC_STATUS_POSITION          0x1BA4</div><div class='del'>-/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */</div><div class='del'>-#define EVERGREEN_CRTC_V_BLANK_START_END                0x1b8d</div><div class='del'>-#define EVERGREEN_CRTC_CONTROL                          0x1b9c</div><div class='del'>-#define EVERGREEN_CRTC_MASTER_EN                 (1 &lt;&lt; 0)</div><div class='del'>-#define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 &lt;&lt; 24)</div><div class='del'>-#define EVERGREEN_CRTC_BLANK_CONTROL                    0x1b9d</div><div class='del'>-#define EVERGREEN_CRTC_BLANK_DATA_EN             (1 &lt;&lt; 8)</div><div class='del'>-#define EVERGREEN_CRTC_V_BLANK                   (1 &lt;&lt; 0)</div><div class='del'>-#define EVERGREEN_CRTC_STATUS_HV_COUNT                  0x1ba8</div><div class='del'>-#define EVERGREEN_CRTC_UPDATE_LOCK                      0x1bb5</div><div class='del'>-#define EVERGREEN_MASTER_UPDATE_LOCK                    0x1bbd</div><div class='del'>-#define EVERGREEN_MASTER_UPDATE_MODE                    0x1bbe</div><div class='del'>-#define EVERGREEN_GRPH_UPDATE_LOCK               (1 &lt;&lt; 16)</div><div class='del'>-#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x1a07</div><div class='del'>-#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x1a08</div><div class='del'>-#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS          0x1a04</div><div class='del'>-#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS        0x1a05</div><div class='del'>-#define EVERGREEN_GRPH_UPDATE                           0x1a11</div><div class='del'>-#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS               0xc4</div><div class='del'>-#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH          0xc9</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING    (1 &lt;&lt; 2)</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_DATA_FORMAT                           0x1ac0</div><div class='del'>-#       define EVERGREEN_INTERLEAVE_EN                  (1 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000</div><div class='del'>-#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc</div><div class='del'>-</div><div class='del'>-#define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL            (0 &lt;&lt; 20)</div><div class='del'>-#define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED            (1 &lt;&lt; 20)</div><div class='del'>-#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 &lt;&lt; 20)</div><div class='del'>-#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 &lt;&lt; 20)</div><div class='del'>-</div><div class='del'>-#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1a45</div><div class='del'>-#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1845</div><div class='del'>-</div><div class='del'>-#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1847</div><div class='del'>-#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH              0x1a47</div><div class='del'>-</div><div class='del'>-#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8</div><div class='del'>-</div><div class='del'>-#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4</div><div class='del'>-</div><div class='del'>-#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000</div><div class='del'>-#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000</div><div class='del'>-</div><div class='del'>-#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1</div><div class='del'>-#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100</div><div class='del'>-</div><div class='del'>-#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1</div><div class='del'>-</div><div class='del'>-#define R600_D1GRPH_SWAP_CONTROL                               0x1843</div><div class='del'>-#define R600_D1GRPH_SWAP_ENDIAN_NONE                    (0 &lt;&lt; 0)</div><div class='del'>-#define R600_D1GRPH_SWAP_ENDIAN_16BIT                   (1 &lt;&lt; 0)</div><div class='del'>-#define R600_D1GRPH_SWAP_ENDIAN_32BIT                   (2 &lt;&lt; 0)</div><div class='del'>-#define R600_D1GRPH_SWAP_ENDIAN_64BIT                   (3 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-#define AVIVO_D1VGA_CONTROL					0x00cc</div><div class='del'>-#       define AVIVO_DVGA_CONTROL_MODE_ENABLE            (1 &lt;&lt; 0)</div><div class='del'>-#       define AVIVO_DVGA_CONTROL_TIMING_SELECT          (1 &lt;&lt; 8)</div><div class='del'>-#       define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT   (1 &lt;&lt; 9)</div><div class='del'>-#       define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 &lt;&lt; 10)</div><div class='del'>-#       define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN      (1 &lt;&lt; 16)</div><div class='del'>-#       define AVIVO_DVGA_CONTROL_ROTATE                 (1 &lt;&lt; 24)</div><div class='del'>-#define AVIVO_D2VGA_CONTROL					0x00ce</div><div class='del'>-</div><div class='del'>-#define R600_BUS_CNTL                                           0x1508</div><div class='del'>-#       define R600_BIOS_ROM_DIS                                (1 &lt;&lt; 1)</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> #define R600_ROM_CNTL                              0x580</div><div class='ctx'> #       define R600_SCK_OVERWRITE                  (1 &lt;&lt; 1)</div><div class='ctx'> #       define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28</div><div class='ctx'> #       define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK  (0xf &lt;&lt; 28)</div><div class='ctx'> </div><div class='del'>-#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1</div><div class='del'>-</div><div class='del'>-#define FMT_BIT_DEPTH_CONTROL                0x1bf2</div><div class='del'>-#define FMT_TRUNCATE_EN               (1 &lt;&lt; 0)</div><div class='del'>-#define FMT_TRUNCATE_DEPTH            (1 &lt;&lt; 4)</div><div class='del'>-#define FMT_SPATIAL_DITHER_EN         (1 &lt;&lt; 8)</div><div class='del'>-#define FMT_SPATIAL_DITHER_MODE(x)    ((x) &lt;&lt; 9)</div><div class='del'>-#define FMT_SPATIAL_DITHER_DEPTH      (1 &lt;&lt; 12)</div><div class='del'>-#define FMT_FRAME_RANDOM_ENABLE       (1 &lt;&lt; 13)</div><div class='del'>-#define FMT_RGB_RANDOM_ENABLE         (1 &lt;&lt; 14)</div><div class='del'>-#define FMT_HIGHPASS_RANDOM_ENABLE    (1 &lt;&lt; 15)</div><div class='del'>-#define FMT_TEMPORAL_DITHER_EN        (1 &lt;&lt; 16)</div><div class='del'>-#define FMT_TEMPORAL_DITHER_DEPTH     (1 &lt;&lt; 20)</div><div class='del'>-#define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) &lt;&lt; 21)</div><div class='del'>-#define FMT_TEMPORAL_LEVEL            (1 &lt;&lt; 24)</div><div class='del'>-#define FMT_TEMPORAL_DITHER_RESET     (1 &lt;&lt; 25)</div><div class='del'>-#define FMT_25FRC_SEL(x)              ((x) &lt;&lt; 26)</div><div class='del'>-#define FMT_50FRC_SEL(x)              ((x) &lt;&lt; 28)</div><div class='del'>-#define FMT_75FRC_SEL(x)              ((x) &lt;&lt; 30)</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_DC_LUT_CONTROL                        0x1a80</div><div class='del'>-#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE              0x1a81</div><div class='del'>-#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN             0x1a82</div><div class='del'>-#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED               0x1a83</div><div class='del'>-#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE              0x1a84</div><div class='del'>-#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN             0x1a85</div><div class='del'>-#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED               0x1a86</div><div class='del'>-#define EVERGREEN_DC_LUT_30_COLOR                       0x1a7c</div><div class='del'>-#define EVERGREEN_DC_LUT_RW_INDEX                       0x1a79</div><div class='del'>-#define EVERGREEN_DC_LUT_WRITE_EN_MASK                  0x1a7e</div><div class='del'>-#define EVERGREEN_DC_LUT_RW_MODE                        0x1a78</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_GRPH_ENABLE                           0x1a00</div><div class='del'>-#define EVERGREEN_GRPH_CONTROL                          0x1a01</div><div class='del'>-#define EVERGREEN_GRPH_DEPTH(x)                  (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#define EVERGREEN_GRPH_DEPTH_8BPP                0</div><div class='del'>-#define EVERGREEN_GRPH_DEPTH_16BPP               1</div><div class='del'>-#define EVERGREEN_GRPH_DEPTH_32BPP               2</div><div class='del'>-#define EVERGREEN_GRPH_NUM_BANKS(x)              (((x) &amp; 0x3) &lt;&lt; 2)</div><div class='del'>-#define EVERGREEN_ADDR_SURF_2_BANK               0</div><div class='del'>-#define EVERGREEN_ADDR_SURF_4_BANK               1</div><div class='del'>-#define EVERGREEN_ADDR_SURF_8_BANK               2</div><div class='del'>-#define EVERGREEN_ADDR_SURF_16_BANK              3</div><div class='del'>-#define EVERGREEN_GRPH_Z(x)                      (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-#define EVERGREEN_GRPH_BANK_WIDTH(x)             (((x) &amp; 0x3) &lt;&lt; 6)</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_WIDTH_1         0</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_WIDTH_2         1</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_WIDTH_4         2</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_WIDTH_8         3</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT(x)                 (((x) &amp; 0x7) &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_INDEXED            0</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_ARGB1555           0</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_ARGB565            1</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_ARGB4444           2</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_AI88               3</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_MONO16             4</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_BGRA5551           5</div><div class='add'>+#define GRPH_ARRAY_LINEAR_GENERAL      0</div><div class='add'>+#define GRPH_ARRAY_LINEAR_ALIGNED      1</div><div class='add'>+#define GRPH_ARRAY_1D_TILED_THIN1      2</div><div class='add'>+#define GRPH_ARRAY_2D_TILED_THIN1      4</div><div class='add'>+</div><div class='add'>+#define ES_AND_GS_AUTO       3</div><div class='add'>+#define BUF_SWAP_32BIT       (2 &lt;&lt; 16)</div><div class='add'>+</div><div class='add'>+#define GRPH_DEPTH_8BPP                0</div><div class='add'>+#define GRPH_DEPTH_16BPP               1</div><div class='add'>+#define GRPH_DEPTH_32BPP               2</div><div class='add'>+</div><div class='add'>+/* 8 BPP */</div><div class='add'>+#define GRPH_FORMAT_INDEXED            0</div><div class='add'>+</div><div class='add'>+/* 16 BPP */</div><div class='add'>+#define GRPH_FORMAT_ARGB1555           0</div><div class='add'>+#define GRPH_FORMAT_ARGB565            1</div><div class='add'>+#define GRPH_FORMAT_ARGB4444           2</div><div class='add'>+#define GRPH_FORMAT_AI88               3</div><div class='add'>+#define GRPH_FORMAT_MONO16             4</div><div class='add'>+#define GRPH_FORMAT_BGRA5551           5</div><div class='ctx'> </div><div class='ctx'> /* 32 BPP */</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_ARGB8888           0</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_ARGB2101010        1</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_32BPP_DIG          2</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010     3</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_BGRA1010102        4</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102     5</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_RGB111110          6</div><div class='del'>-#define EVERGREEN_GRPH_FORMAT_BGR101111          7</div><div class='del'>-#define EVERGREEN_GRPH_BANK_HEIGHT(x)            (((x) &amp; 0x3) &lt;&lt; 11)</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1        0</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2        1</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4        2</div><div class='del'>-#define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8        3</div><div class='del'>-#define EVERGREEN_GRPH_TILE_SPLIT(x)             (((x) &amp; 0x7) &lt;&lt; 13)</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B       0</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B      1</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B      2</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B      3</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB       4</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB       5</div><div class='del'>-#define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB       6</div><div class='del'>-#define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x)      (((x) &amp; 0x3) &lt;&lt; 18)</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1  0</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2  1</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4  2</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8  3</div><div class='del'>-#define EVERGREEN_GRPH_ARRAY_MODE(x)             (((x) &amp; 0x7) &lt;&lt; 20)</div><div class='del'>-#define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL      0</div><div class='del'>-#define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED      1</div><div class='del'>-#define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1      2</div><div class='del'>-#define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1      4</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1  0</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2  1</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4  2</div><div class='del'>-#define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8  3</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_GRPH_SWAP_CONTROL                     0x1a03</div><div class='del'>-#define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#       define EVERGREEN_GRPH_ENDIAN_NONE               0</div><div class='del'>-#       define EVERGREEN_GRPH_ENDIAN_8IN16              1</div><div class='del'>-#       define EVERGREEN_GRPH_ENDIAN_8IN32              2</div><div class='del'>-#       define EVERGREEN_GRPH_ENDIAN_8IN64              3</div><div class='del'>-#define EVERGREEN_GRPH_RED_CROSSBAR(x)           (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-#       define EVERGREEN_GRPH_RED_SEL_R                 0</div><div class='del'>-#       define EVERGREEN_GRPH_RED_SEL_G                 1</div><div class='del'>-#       define EVERGREEN_GRPH_RED_SEL_B                 2</div><div class='del'>-#       define EVERGREEN_GRPH_RED_SEL_A                 3</div><div class='del'>-#define EVERGREEN_GRPH_GREEN_CROSSBAR(x)         (((x) &amp; 0x3) &lt;&lt; 6)</div><div class='del'>-#       define EVERGREEN_GRPH_GREEN_SEL_G               0</div><div class='del'>-#       define EVERGREEN_GRPH_GREEN_SEL_B               1</div><div class='del'>-#       define EVERGREEN_GRPH_GREEN_SEL_A               2</div><div class='del'>-#       define EVERGREEN_GRPH_GREEN_SEL_R               3</div><div class='del'>-#define EVERGREEN_GRPH_BLUE_CROSSBAR(x)          (((x) &amp; 0x3) &lt;&lt; 8)</div><div class='del'>-#       define EVERGREEN_GRPH_BLUE_SEL_B                0</div><div class='del'>-#       define EVERGREEN_GRPH_BLUE_SEL_A                1</div><div class='del'>-#       define EVERGREEN_GRPH_BLUE_SEL_R                2</div><div class='del'>-#       define EVERGREEN_GRPH_BLUE_SEL_G                3</div><div class='del'>-#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x)         (((x) &amp; 0x3) &lt;&lt; 10)</div><div class='del'>-#       define EVERGREEN_GRPH_ALPHA_SEL_A               0</div><div class='del'>-#       define EVERGREEN_GRPH_ALPHA_SEL_R               1</div><div class='del'>-#       define EVERGREEN_GRPH_ALPHA_SEL_G               2</div><div class='del'>-#       define EVERGREEN_GRPH_ALPHA_SEL_B               3</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_D3VGA_CONTROL                         0xf8</div><div class='del'>-#define EVERGREEN_D4VGA_CONTROL                         0xf9</div><div class='del'>-#define EVERGREEN_D5VGA_CONTROL                         0xfa</div><div class='del'>-#define EVERGREEN_D6VGA_CONTROL                         0xfb</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK      0xffffff00</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL         0x1a02</div><div class='del'>-#define EVERGREEN_LUT_10BIT_BYPASS_EN            (1 &lt;&lt; 8)</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_GRPH_PITCH                            0x1a06</div><div class='del'>-#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x1a07</div><div class='del'>-#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x1a08</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_OFFSET_X                 0x1a09</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_OFFSET_Y                 0x1a0a</div><div class='del'>-#define EVERGREEN_GRPH_X_START                          0x1a0b</div><div class='del'>-#define EVERGREEN_GRPH_Y_START                          0x1a0c</div><div class='del'>-#define EVERGREEN_GRPH_X_END                            0x1a0d</div><div class='del'>-#define EVERGREEN_GRPH_Y_END                            0x1a0e</div><div class='del'>-#define EVERGREEN_GRPH_UPDATE                           0x1a11</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING    (1 &lt;&lt; 2)</div><div class='del'>-#define EVERGREEN_GRPH_UPDATE_LOCK               (1 &lt;&lt; 16)</div><div class='del'>-#define EVERGREEN_GRPH_FLIP_CONTROL                     0x1a12</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 &lt;&lt; 0)</div><div class='del'>-</div><div class='del'>-#define EVERGREEN_VIEWPORT_START                        0x1b5c</div><div class='del'>-#define EVERGREEN_VIEWPORT_SIZE                         0x1b5d</div><div class='del'>-#define EVERGREEN_DESKTOP_HEIGHT                        0x1ac1</div><div class='del'>-</div><div class='del'>-/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */</div><div class='del'>-#define EVERGREEN_CUR_CONTROL                           0x1a66</div><div class='del'>-#       define EVERGREEN_CURSOR_EN                      (1 &lt;&lt; 0)</div><div class='del'>-#       define EVERGREEN_CURSOR_MODE(x)                 (((x) &amp; 0x3) &lt;&lt; 8)</div><div class='del'>-#       define EVERGREEN_CURSOR_MONO                    0</div><div class='del'>-#       define EVERGREEN_CURSOR_24_1                    1</div><div class='del'>-#       define EVERGREEN_CURSOR_24_8_PRE_MULT           2</div><div class='del'>-#       define EVERGREEN_CURSOR_24_8_UNPRE_MULT         3</div><div class='del'>-#       define EVERGREEN_CURSOR_2X_MAGNIFY              (1 &lt;&lt; 16)</div><div class='del'>-#       define EVERGREEN_CURSOR_FORCE_MC_ON             (1 &lt;&lt; 20)</div><div class='del'>-#       define EVERGREEN_CURSOR_URGENT_CONTROL(x)       (((x) &amp; 0x7) &lt;&lt; 24)</div><div class='del'>-#       define EVERGREEN_CURSOR_URGENT_ALWAYS           0</div><div class='del'>-#       define EVERGREEN_CURSOR_URGENT_1_8              1</div><div class='del'>-#       define EVERGREEN_CURSOR_URGENT_1_4              2</div><div class='del'>-#       define EVERGREEN_CURSOR_URGENT_3_8              3</div><div class='del'>-#       define EVERGREEN_CURSOR_URGENT_1_2              4</div><div class='del'>-#define EVERGREEN_CUR_SURFACE_ADDRESS                   0x1a67</div><div class='del'>-#       define EVERGREEN_CUR_SURFACE_ADDRESS_MASK       0xfffff000</div><div class='del'>-#define EVERGREEN_CUR_SIZE                              0x1a68</div><div class='del'>-#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH              0x1a69</div><div class='del'>-#define EVERGREEN_CUR_POSITION                          0x1a6a</div><div class='del'>-#define EVERGREEN_CUR_HOT_SPOT                          0x1a6b</div><div class='del'>-#define EVERGREEN_CUR_COLOR1                            0x1a6c</div><div class='del'>-#define EVERGREEN_CUR_COLOR2                            0x1a6d</div><div class='del'>-#define EVERGREEN_CUR_UPDATE                            0x1a6e</div><div class='del'>-#       define EVERGREEN_CURSOR_UPDATE_PENDING          (1 &lt;&lt; 0)</div><div class='del'>-#       define EVERGREEN_CURSOR_UPDATE_TAKEN            (1 &lt;&lt; 1)</div><div class='del'>-#       define EVERGREEN_CURSOR_UPDATE_LOCK             (1 &lt;&lt; 16)</div><div class='del'>-#       define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 &lt;&lt; 24)</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-#define NI_INPUT_CSC_CONTROL                           0x1a35</div><div class='del'>-#       define NI_INPUT_CSC_GRPH_MODE(x)               (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#       define NI_INPUT_CSC_BYPASS                     0</div><div class='del'>-#       define NI_INPUT_CSC_PROG_COEFF                 1</div><div class='del'>-#       define NI_INPUT_CSC_PROG_SHARED_MATRIXA        2</div><div class='del'>-#       define NI_INPUT_CSC_OVL_MODE(x)                (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define NI_OUTPUT_CSC_CONTROL                          0x1a3c</div><div class='del'>-#       define NI_OUTPUT_CSC_GRPH_MODE(x)              (((x) &amp; 0x7) &lt;&lt; 0)</div><div class='del'>-#       define NI_OUTPUT_CSC_BYPASS                    0</div><div class='del'>-#       define NI_OUTPUT_CSC_TV_RGB                    1</div><div class='del'>-#       define NI_OUTPUT_CSC_YCBCR_601                 2</div><div class='del'>-#       define NI_OUTPUT_CSC_YCBCR_709                 3</div><div class='del'>-#       define NI_OUTPUT_CSC_PROG_COEFF                4</div><div class='del'>-#       define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB       5</div><div class='del'>-#       define NI_OUTPUT_CSC_OVL_MODE(x)               (((x) &amp; 0x7) &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define NI_DEGAMMA_CONTROL                             0x1a58</div><div class='del'>-#       define NI_GRPH_DEGAMMA_MODE(x)                 (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#       define NI_DEGAMMA_BYPASS                       0</div><div class='del'>-#       define NI_DEGAMMA_SRGB_24                      1</div><div class='del'>-#       define NI_DEGAMMA_XVYCC_222                    2</div><div class='del'>-#       define NI_OVL_DEGAMMA_MODE(x)                  (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-#       define NI_ICON_DEGAMMA_MODE(x)                 (((x) &amp; 0x3) &lt;&lt; 8)</div><div class='del'>-#       define NI_CURSOR_DEGAMMA_MODE(x)               (((x) &amp; 0x3) &lt;&lt; 12)</div><div class='del'>-</div><div class='del'>-#define NI_GAMUT_REMAP_CONTROL                         0x1a59</div><div class='del'>-#       define NI_GRPH_GAMUT_REMAP_MODE(x)             (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#       define NI_GAMUT_REMAP_BYPASS                   0</div><div class='del'>-#       define NI_GAMUT_REMAP_PROG_COEFF               1</div><div class='del'>-#       define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA      2</div><div class='del'>-#       define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB      3</div><div class='del'>-#       define NI_OVL_GAMUT_REMAP_MODE(x)              (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define NI_REGAMMA_CONTROL                             0x1aa0</div><div class='del'>-#       define NI_GRPH_REGAMMA_MODE(x)                 (((x) &amp; 0x7) &lt;&lt; 0)</div><div class='del'>-#       define NI_REGAMMA_BYPASS                       0</div><div class='del'>-#       define NI_REGAMMA_SRGB_24                      1</div><div class='del'>-#       define NI_REGAMMA_XVYCC_222                    2</div><div class='del'>-#       define NI_REGAMMA_PROG_A                       3</div><div class='del'>-#       define NI_REGAMMA_PROG_B                       4</div><div class='del'>-#       define NI_OVL_REGAMMA_MODE(x)                  (((x) &amp; 0x7) &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-#define NI_PRESCALE_GRPH_CONTROL                       0x1a2d</div><div class='del'>-#       define NI_GRPH_PRESCALE_BYPASS                 (1 &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define NI_PRESCALE_OVL_CONTROL                        0x1a31</div><div class='del'>-#       define NI_OVL_PRESCALE_BYPASS                  (1 &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define NI_INPUT_GAMMA_CONTROL                         0x1a10</div><div class='del'>-#       define NI_GRPH_INPUT_GAMMA_MODE(x)             (((x) &amp; 0x3) &lt;&lt; 0)</div><div class='del'>-#       define NI_INPUT_GAMMA_USE_LUT                  0</div><div class='del'>-#       define NI_INPUT_GAMMA_BYPASS                   1</div><div class='del'>-#       define NI_INPUT_GAMMA_SRGB_24                  2</div><div class='del'>-#       define NI_INPUT_GAMMA_XVYCC_222                3</div><div class='del'>-#       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) &amp; 0x3) &lt;&lt; 4)</div><div class='del'>-</div><div class='del'>-#define	BLACKOUT_MODE_MASK			0x00000007</div><div class='del'>-#define	VGA_RENDER_CONTROL			0xC0</div><div class='del'>-#define R_000300_VGA_RENDER_CONTROL             0xC0</div><div class='del'>-#define C_000300_VGA_VSTATUS_CNTL               0xFFFCFFFF</div><div class='del'>-#define EVERGREEN_CRTC_STATUS                   0x1BA3</div><div class='del'>-#define EVERGREEN_CRTC_V_BLANK                  (1 &lt;&lt; 0)</div><div class='del'>-#define EVERGREEN_CRTC_STATUS_POSITION          0x1BA4</div><div class='del'>-/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */</div><div class='del'>-#define EVERGREEN_CRTC_V_BLANK_START_END                0x1b8d</div><div class='del'>-#define EVERGREEN_CRTC_CONTROL                          0x1b9c</div><div class='del'>-#       define EVERGREEN_CRTC_MASTER_EN                 (1 &lt;&lt; 0)</div><div class='del'>-#       define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 &lt;&lt; 24)</div><div class='del'>-#define EVERGREEN_CRTC_BLANK_CONTROL                    0x1b9d</div><div class='del'>-#       define EVERGREEN_CRTC_BLANK_DATA_EN             (1 &lt;&lt; 8)</div><div class='del'>-#       define EVERGREEN_CRTC_V_BLANK                   (1 &lt;&lt; 0)</div><div class='del'>-#define EVERGREEN_CRTC_STATUS_HV_COUNT                  0x1ba8</div><div class='del'>-#define EVERGREEN_CRTC_UPDATE_LOCK                      0x1bb5</div><div class='del'>-#define EVERGREEN_MASTER_UPDATE_LOCK                    0x1bbd</div><div class='del'>-#define EVERGREEN_MASTER_UPDATE_MODE                    0x1bbe</div><div class='del'>-#define EVERGREEN_GRPH_UPDATE_LOCK               (1 &lt;&lt; 16)</div><div class='del'>-#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH     0x1a07</div><div class='del'>-#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH   0x1a08</div><div class='del'>-#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS          0x1a04</div><div class='del'>-#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS        0x1a05</div><div class='del'>-#define EVERGREEN_GRPH_UPDATE                           0x1a11</div><div class='del'>-#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS               0xc4</div><div class='del'>-#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH          0xc9</div><div class='del'>-#define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING    (1 &lt;&lt; 2)</div><div class='del'>-</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000</div><div class='del'>-#define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13</div><div class='del'>-</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000</div><div class='del'>-#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18</div><div class='del'>-</div><div class='del'>-#define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7</div><div class='del'>-#define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0</div><div class='del'>-</div><div class='del'>-#define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1</div><div class='del'>-#define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0</div><div class='del'>-#define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2</div><div class='del'>-#define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1</div><div class='del'>-</div><div class='del'>-#define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000</div><div class='del'>-#define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11</div><div class='del'>-#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800</div><div class='del'>-#define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb</div><div class='del'>-</div><div class='del'>-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8</div><div class='del'>-#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3</div><div class='del'>-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40</div><div class='del'>-#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6</div><div class='del'>-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200</div><div class='del'>-#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9</div><div class='del'>-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000</div><div class='del'>-#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc</div><div class='del'>-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000</div><div class='del'>-#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf</div><div class='del'>-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000</div><div class='del'>-#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12</div><div class='add'>+#define GRPH_FORMAT_ARGB8888           0</div><div class='add'>+#define GRPH_FORMAT_ARGB2101010        1</div><div class='add'>+#define GRPH_FORMAT_32BPP_DIG          2</div><div class='add'>+#define GRPH_FORMAT_8B_ARGB2101010     3</div><div class='add'>+#define GRPH_FORMAT_BGRA1010102        4</div><div class='add'>+#define GRPH_FORMAT_8B_BGRA1010102     5</div><div class='add'>+#define GRPH_FORMAT_RGB111110          6</div><div class='add'>+#define GRPH_FORMAT_BGR101111          7</div><div class='add'>+</div><div class='add'>+#define GRPH_ENDIAN_NONE               0</div><div class='add'>+#define GRPH_ENDIAN_8IN16              1</div><div class='add'>+#define GRPH_ENDIAN_8IN32              2</div><div class='add'>+#define GRPH_ENDIAN_8IN64              3</div><div class='add'>+#define GRPH_RED_SEL_R                 0</div><div class='add'>+#define GRPH_RED_SEL_G                 1</div><div class='add'>+#define GRPH_RED_SEL_B                 2</div><div class='add'>+#define GRPH_RED_SEL_A                 3</div><div class='add'>+</div><div class='add'>+#define GRPH_GREEN_SEL_G               0</div><div class='add'>+#define GRPH_GREEN_SEL_B               1</div><div class='add'>+#define GRPH_GREEN_SEL_A               2</div><div class='add'>+#define GRPH_GREEN_SEL_R               3</div><div class='add'>+</div><div class='add'>+#define GRPH_BLUE_SEL_B                0</div><div class='add'>+#define GRPH_BLUE_SEL_A                1</div><div class='add'>+#define GRPH_BLUE_SEL_R                2</div><div class='add'>+#define GRPH_BLUE_SEL_G                3</div><div class='add'>+</div><div class='add'>+#define GRPH_ALPHA_SEL_A               0</div><div class='add'>+#define GRPH_ALPHA_SEL_R               1</div><div class='add'>+#define GRPH_ALPHA_SEL_G               2</div><div class='add'>+#define GRPH_ALPHA_SEL_B               3</div><div class='add'>+</div><div class='add'>+/* CUR_CONTROL */</div><div class='add'>+	#define CURSOR_MONO                    0</div><div class='add'>+	#define CURSOR_24_1                    1</div><div class='add'>+	#define CURSOR_24_8_PRE_MULT           2</div><div class='add'>+	#define CURSOR_24_8_UNPRE_MULT         3</div><div class='add'>+	#define CURSOR_URGENT_ALWAYS           0</div><div class='add'>+	#define CURSOR_URGENT_1_8              1</div><div class='add'>+	#define CURSOR_URGENT_1_4              2</div><div class='add'>+	#define CURSOR_URGENT_3_8              3</div><div class='add'>+	#define CURSOR_URGENT_1_2              4</div><div class='add'>+</div><div class='add'>+/* INPUT_CSC_CONTROL */</div><div class='add'>+#       define INPUT_CSC_BYPASS                     0</div><div class='add'>+#       define INPUT_CSC_PROG_COEFF                 1</div><div class='add'>+#       define INPUT_CSC_PROG_SHARED_MATRIXA        2</div><div class='add'>+</div><div class='add'>+/* OUTPUT_CSC_CONTROL */</div><div class='add'>+#       define OUTPUT_CSC_BYPASS                    0</div><div class='add'>+#       define OUTPUT_CSC_TV_RGB                    1</div><div class='add'>+#       define OUTPUT_CSC_YCBCR_601                 2</div><div class='add'>+#       define OUTPUT_CSC_YCBCR_709                 3</div><div class='add'>+#       define OUTPUT_CSC_PROG_COEFF                4</div><div class='add'>+#       define OUTPUT_CSC_PROG_SHARED_MATRIXB       5</div><div class='add'>+</div><div class='add'>+/* DEGAMMA_CONTROL */</div><div class='add'>+#       define DEGAMMA_BYPASS                       0</div><div class='add'>+#       define DEGAMMA_SRGB_24                      1</div><div class='add'>+#       define DEGAMMA_XVYCC_222                    2</div><div class='add'>+</div><div class='add'>+/* GAMUT_REMAP_CONTROL */</div><div class='add'>+#       define GAMUT_REMAP_BYPASS                   0</div><div class='add'>+#       define GAMUT_REMAP_PROG_COEFF               1</div><div class='add'>+#       define GAMUT_REMAP_PROG_SHARED_MATRIXA      2</div><div class='add'>+#       define GAMUT_REMAP_PROG_SHARED_MATRIXB      3</div><div class='add'>+</div><div class='add'>+/* REGAMMA_CONTROL */</div><div class='add'>+#       define REGAMMA_BYPASS                       0</div><div class='add'>+#       define REGAMMA_SRGB_24                      1</div><div class='add'>+#       define REGAMMA_XVYCC_222                    2</div><div class='add'>+#       define REGAMMA_PROG_A                       3</div><div class='add'>+#       define REGAMMA_PROG_B                       4</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* INPUT_GAMMA_CONTROL */</div><div class='add'>+#       define INPUT_GAMMA_USE_LUT                  0</div><div class='add'>+#       define INPUT_GAMMA_BYPASS                   1</div><div class='add'>+#       define INPUT_GAMMA_SRGB_24                  2</div><div class='add'>+#       define INPUT_GAMMA_XVYCC_222                3</div><div class='ctx'> </div><div class='ctx'> #define MC_SEQ_MISC0__MT__MASK	0xf0000000</div><div class='ctx'> #define MC_SEQ_MISC0__MT__GDDR1  0x10000000</div><div class='hunk'>@@ -2426,28 +740,14 @@</div><div class='ctx'> #define MC_SEQ_MISC0__MT__HBM    0x60000000</div><div class='ctx'> #define MC_SEQ_MISC0__MT__DDR3   0xB0000000</div><div class='ctx'> </div><div class='del'>-#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000</div><div class='ctx'> #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000</div><div class='del'>-#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000</div><div class='del'>-#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000</div><div class='ctx'> #define PACKET3_SEM_WAIT_ON_SIGNAL    (0x1 &lt;&lt; 12)</div><div class='ctx'> #define PACKET3_SEM_SEL_SIGNAL	    (0x6 &lt;&lt; 29)</div><div class='ctx'> #define PACKET3_SEM_SEL_WAIT	    (0x7 &lt;&lt; 29)</div><div class='ctx'> </div><div class='del'>-#define CONFIG_CNTL	0x1509</div><div class='del'>-#define CC_DRM_ID_STRAPS	0X1559</div><div class='ctx'> #define AMDGPU_PCIE_INDEX	0xc</div><div class='ctx'> #define AMDGPU_PCIE_DATA	0xd</div><div class='ctx'> </div><div class='del'>-#define DMA_SEM_INCOMPLETE_TIMER_CNTL                     0x3411</div><div class='del'>-#define DMA_SEM_WAIT_FAIL_TIMER_CNTL                      0x3412</div><div class='del'>-#define DMA_MODE                                          0x342f</div><div class='del'>-#define DMA_RB_RPTR_ADDR_HI                               0x3407</div><div class='del'>-#define DMA_RB_RPTR_ADDR_LO                               0x3408</div><div class='del'>-#define DMA_BUSY_MASK 0x20</div><div class='del'>-#define DMA1_BUSY_MASK 0X40</div><div class='del'>-#define SDMA_MAX_INSTANCE 2</div><div class='del'>-</div><div class='ctx'> #define PCIE_BUS_CLK    10000</div><div class='ctx'> #define TCLK            (PCIE_BUS_CLK / 10)</div><div class='ctx'> #define	PCIE_PORT_INDEX					0xe</div><div class='hunk'>@@ -2457,8 +757,6 @@</div><div class='ctx'> #define EVERGREEN_PIF_PHY1_INDEX                        0x10</div><div class='ctx'> #define EVERGREEN_PIF_PHY1_DATA				0x14</div><div class='ctx'> </div><div class='del'>-#define	MC_VM_FB_OFFSET					0x81a</div><div class='del'>-</div><div class='ctx'> /* Discrete VCE clocks */</div><div class='ctx'> #define CG_VCEPLL_FUNC_CNTL                             0xc0030600</div><div class='ctx'> #define    VCEPLL_RESET_MASK                            0x00000001</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c<br/>index 93f6772d1b24..2594467bdd87 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c</a></div><div class='hunk'>@@ -81,18 +81,12 @@ static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev)</div><div class='ctx'> 			      AMD_IP_BLOCK_TYPE_SDMA))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;suspend(adev);</div><div class='del'>-</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"suspend of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		r = amdgpu_ip_block_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-		}</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='hunk'>@@ -175,15 +169,9 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;type == AMD_IP_BLOCK_TYPE_IH) {</div><div class='del'>-			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-			if (r) {</div><div class='del'>-				dev_err(adev-&gt;dev,</div><div class='del'>-					"resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-					adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+			r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+			if (r)</div><div class='ctx'> 				return r;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -193,15 +181,9 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> 		      adev-&gt;ip_blocks[i].version-&gt;type ==</div><div class='ctx'> 			      AMD_IP_BLOCK_TYPE_SDMA))</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='hunk'>@@ -213,7 +195,7 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init) {</div><div class='ctx'> 			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init(</div><div class='del'>-				(void *)adev);</div><div class='add'>+				&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				dev_err(adev-&gt;dev,</div><div class='ctx'> 					"late_init of IP block &lt;%s&gt; failed %d after reset\n",</div><div class='hunk'>@@ -238,6 +220,7 @@ sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> 	int r;</div><div class='ctx'> 	struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl-&gt;handle;</div><div class='ctx'> </div><div class='add'>+	amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_RESET_RECOVERY);</div><div class='ctx'> 	dev_info(tmp_adev-&gt;dev,</div><div class='ctx'> 			"GPU reset succeeded, trying to resume\n");</div><div class='ctx'> 	r = sienna_cichlid_mode2_restore_ip(tmp_adev);</div><div class='hunk'>@@ -255,6 +238,7 @@ sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_gpu_reset_resume_helper(tmp_adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT);</div><div class='ctx'> 	r = amdgpu_ib_ring_tests(tmp_adev);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(tmp_adev-&gt;dev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c<br/>index dd2d66090d23..68aef47254a9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c</a></div><div class='hunk'>@@ -743,7 +743,7 @@ int smu_v11_0_i2c_control_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;pm.ras_eeprom_i2c_bus = &amp;adev-&gt;pm.smu_i2c[0].adapter;</div><div class='ctx'> 	adev-&gt;pm.fru_eeprom_i2c_bus = &amp;adev-&gt;pm.smu_i2c[0].adapter;</div><div class='ctx'> </div><div class='del'>-	res = i2c_add_adapter(control);</div><div class='add'>+	res = devm_i2c_add_adapter(adev-&gt;dev, control);</div><div class='ctx'> 	if (res)</div><div class='ctx'> 		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);</div><div class='ctx'> </div><div class='hunk'>@@ -752,9 +752,6 @@ int smu_v11_0_i2c_control_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct i2c_adapter *control = adev-&gt;pm.ras_eeprom_i2c_bus;</div><div class='del'>-</div><div class='del'>-	i2c_del_adapter(control);</div><div class='ctx'> 	adev-&gt;pm.ras_eeprom_i2c_bus = NULL;</div><div class='ctx'> 	adev-&gt;pm.fru_eeprom_i2c_bus = NULL;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c<br/>index 04c797d54511..70569ea906bc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c</a></div><div class='hunk'>@@ -80,18 +80,12 @@ static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)</div><div class='ctx'> 			      AMD_IP_BLOCK_TYPE_MES))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;suspend(adev);</div><div class='del'>-</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"suspend of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		r = amdgpu_ip_block_suspend(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-		}</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='hunk'>@@ -186,15 +180,9 @@ static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> 		      adev-&gt;ip_blocks[i].version-&gt;type ==</div><div class='ctx'> 			      AMD_IP_BLOCK_TYPE_SDMA))</div><div class='ctx'> 			continue;</div><div class='del'>-		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;resume(adev);</div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"resume of IP block &lt;%s&gt; failed %d\n",</div><div class='del'>-				adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;name, r);</div><div class='add'>+		r = amdgpu_ip_block_resume(&amp;adev-&gt;ip_blocks[i]);</div><div class='add'>+		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		adev-&gt;ip_blocks[i].status.hw = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;num_ip_blocks; i++) {</div><div class='hunk'>@@ -208,7 +196,7 @@ static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init) {</div><div class='ctx'> 			r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;late_init(</div><div class='del'>-				(void *)adev);</div><div class='add'>+				&amp;adev-&gt;ip_blocks[i]);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				dev_err(adev-&gt;dev,</div><div class='ctx'> 					"late_init of IP block &lt;%s&gt; failed %d after reset\n",</div><div class='hunk'>@@ -233,6 +221,7 @@ smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> 	int r;</div><div class='ctx'> 	struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl-&gt;handle;</div><div class='ctx'> </div><div class='add'>+	amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_RESET_RECOVERY);</div><div class='ctx'> 	dev_info(tmp_adev-&gt;dev,</div><div class='ctx'> 			"GPU reset succeeded, trying to resume\n");</div><div class='ctx'> 	r = smu_v13_0_10_mode2_restore_ip(tmp_adev);</div><div class='hunk'>@@ -246,6 +235,7 @@ smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_gpu_reset_resume_helper(tmp_adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT);</div><div class='ctx'> 	r = amdgpu_ib_ring_tests(tmp_adev);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(tmp_adev-&gt;dev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c b/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c<br/>new file mode 100644<br/>index 000000000000..2a51a70d4846<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c</a></div><div class='hunk'>@@ -0,0 +1,62 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "smuio_v14_0_2.h"</div><div class='add'>+#include "smuio/smuio_14_0_2_offset.h"</div><div class='add'>+#include "smuio/smuio_14_0_2_sh_mask.h"</div><div class='add'>+#include &lt;linux/preempt.h&gt;</div><div class='add'>+</div><div class='add'>+static u32 smuio_v14_0_2_get_rom_index_offset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 smuio_v14_0_2_get_rom_data_offset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 smuio_v14_0_2_get_gpu_clock_counter(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u64 clock;</div><div class='add'>+	u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;</div><div class='add'>+</div><div class='add'>+	preempt_disable();</div><div class='add'>+	clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);</div><div class='add'>+	clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);</div><div class='add'>+	/* the clock counter may be udpated during polling the counters */</div><div class='add'>+	clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);</div><div class='add'>+	if (clock_counter_hi_pre != clock_counter_hi_after)</div><div class='add'>+		clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);</div><div class='add'>+	preempt_enable();</div><div class='add'>+</div><div class='add'>+	clock = clock_counter_lo | (clock_counter_hi_after &lt;&lt; 32ULL);</div><div class='add'>+</div><div class='add'>+	return clock;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_smuio_funcs smuio_v14_0_2_funcs = {</div><div class='add'>+	.get_rom_index_offset = smuio_v14_0_2_get_rom_index_offset,</div><div class='add'>+	.get_rom_data_offset = smuio_v14_0_2_get_rom_data_offset,</div><div class='add'>+	.get_gpu_clock_counter = smuio_v14_0_2_get_gpu_clock_counter,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.h b/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.h<br/>new file mode 100644<br/>index 000000000000..6e617f832d90<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#ifndef __SMUIO_V14_0_2_H__</div><div class='add'>+#define __SMUIO_V14_0_2_H__</div><div class='add'>+</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_smuio_funcs smuio_v14_0_2_funcs;</div><div class='add'>+</div><div class='add'>+#endif /* __SMUIO_V14_0_2_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c<br/>index e4e30b9d481b..c04fdd2d5b38 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c</a></div><div class='hunk'>@@ -60,7 +60,7 @@ static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *f</div><div class='ctx'> {</div><div class='ctx'> 	u32 data;</div><div class='ctx'> </div><div class='del'>-	/* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */</div><div class='add'>+	/* CGTT_ROM_CLK_CTRL0 is not available for APUs */</div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c<br/>index dec81ccf6240..42f5d9c0e3af 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc15.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/soc15.c</a></div><div class='hunk'>@@ -28,7 +28,6 @@</div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='del'>-#include "amdgpu_atombios.h"</div><div class='ctx'> #include "amdgpu_ih.h"</div><div class='ctx'> #include "amdgpu_uvd.h"</div><div class='ctx'> #include "amdgpu_vce.h"</div><div class='hunk'>@@ -90,8 +89,8 @@ static const struct amd_ip_funcs soc15_common_ip_funcs;</div><div class='ctx'> /* Vega, Raven, Arcturus */</div><div class='ctx'> static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =</div><div class='ctx'> {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codecs vega_video_codecs_encode =</div><div class='hunk'>@@ -103,12 +102,11 @@ static const struct amdgpu_video_codecs vega_video_codecs_encode =</div><div class='ctx'> /* Vega */</div><div class='ctx'> static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =</div><div class='ctx'> {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codecs vega_video_codecs_decode =</div><div class='hunk'>@@ -120,12 +118,12 @@ static const struct amdgpu_video_codecs vega_video_codecs_decode =</div><div class='ctx'> /* Raven */</div><div class='ctx'> static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =</div><div class='ctx'> {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -138,12 +136,12 @@ static const struct amdgpu_video_codecs rv_video_codecs_decode =</div><div class='ctx'> /* Renoir, Arcturus */</div><div class='ctx'> static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =</div><div class='ctx'> {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -156,7 +154,7 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =</div><div class='ctx'> static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='hunk'>@@ -171,6 +169,24 @@ static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {</div><div class='ctx'> 	.codec_array = NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = {</div><div class='add'>+	.codec_count = 0,</div><div class='add'>+	.codec_array = NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = {</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = {</div><div class='add'>+	.codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0),</div><div class='add'>+	.codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,</div><div class='ctx'> 				    const struct amdgpu_video_codecs **codecs)</div><div class='ctx'> {</div><div class='hunk'>@@ -209,6 +225,12 @@ static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,</div><div class='ctx'> 			else</div><div class='ctx'> 				*codecs = &amp;vcn_4_0_3_video_codecs_decode;</div><div class='ctx'> 			return 0;</div><div class='add'>+		case IP_VERSION(5, 0, 1):</div><div class='add'>+			if (encode)</div><div class='add'>+				*codecs = &amp;vcn_5_0_1_video_codecs_encode_vcn0;</div><div class='add'>+			else</div><div class='add'>+				*codecs = &amp;vcn_5_0_1_video_codecs_decode_vcn0;</div><div class='add'>+			return 0;</div><div class='ctx'> 		default:</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -326,7 +348,9 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) ||</div><div class='ctx'> 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) ||</div><div class='del'>-	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6))</div><div class='add'>+	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) ||</div><div class='add'>+	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14))</div><div class='ctx'> 		return 10000;</div><div class='ctx'> 	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) ||</div><div class='ctx'> 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1))</div><div class='hunk'>@@ -502,7 +526,7 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)</div><div class='ctx'> static enum amd_reset_method</div><div class='ctx'> soc15_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	bool baco_reset = false;</div><div class='add'>+	int baco_reset = 0;</div><div class='ctx'> 	bool connected_to_cpu = false;</div><div class='ctx'> 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -540,7 +564,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (ras &amp;&amp; adev-&gt;ras_enabled &amp;&amp;</div><div class='ctx'> 			    adev-&gt;pm.fw_version &lt;= 0x283400)</div><div class='del'>-				baco_reset = false;</div><div class='add'>+				baco_reset = 0;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			baco_reset = amdgpu_dpm_is_baco_supported(adev);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -554,10 +578,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> 			return AMD_RESET_METHOD_MODE2;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='add'>+	case IP_VERSION(13, 0, 14):</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='ctx'> 		/* Use gpu_recovery param to target a reset method.</div><div class='ctx'> 		 * Enable triggering of GPU reset only if specified</div><div class='ctx'> 		 * by module parameter.</div><div class='ctx'> 		 */</div><div class='add'>+		if (adev-&gt;pcie_reset_ctx.in_link_reset)</div><div class='add'>+			return AMD_RESET_METHOD_LINK;</div><div class='ctx'> 		if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)</div><div class='ctx'> 			return AMD_RESET_METHOD_MODE2;</div><div class='ctx'> 		else if (!(adev-&gt;flags &amp; AMD_IS_APU))</div><div class='hunk'>@@ -576,20 +604,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	u32 sol_reg;</div><div class='del'>-</div><div class='del'>-	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);</div><div class='del'>-</div><div class='ctx'> 	/* Will reset for the following suspend abort cases.</div><div class='del'>-	 * 1) Only reset limit on APU side, dGPU hasn't checked yet.</div><div class='del'>-	 * 2) S3 suspend abort and TOS already launched.</div><div class='add'>+	 * 1) S3 suspend aborted in the normal S3 suspend</div><div class='add'>+	 * 2) S3 suspend aborted in performing pm core test.</div><div class='ctx'> 	 */</div><div class='del'>-	if (adev-&gt;flags &amp; AMD_IS_APU &amp;&amp; adev-&gt;in_s3 &amp;&amp;</div><div class='del'>-			!adev-&gt;suspend_complete &amp;&amp;</div><div class='del'>-			sol_reg)</div><div class='add'>+	if (adev-&gt;in_s3 &amp;&amp; !pm_resume_via_firmware())</div><div class='ctx'> 		return true;</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int soc15_asic_reset(struct amdgpu_device *adev)</div><div class='hunk'>@@ -599,11 +621,17 @@ static int soc15_asic_reset(struct amdgpu_device *adev)</div><div class='ctx'> 	 * successfully. So now, temporarily enable it for the</div><div class='ctx'> 	 * S3 suspend abort case.</div><div class='ctx'> 	 */</div><div class='del'>-	if (((adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN) ||</div><div class='del'>-	    (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)) &amp;&amp;</div><div class='del'>-		!soc15_need_reset_on_resume(adev))</div><div class='add'>+</div><div class='add'>+	if ((adev-&gt;apu_flags &amp; AMD_APU_IS_PICASSO ||</div><div class='add'>+			!(adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN)) &amp;&amp;</div><div class='add'>+			soc15_need_reset_on_resume(adev))</div><div class='add'>+		goto asic_reset;</div><div class='add'>+</div><div class='add'>+	if ((adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN) ||</div><div class='add'>+			(adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+asic_reset:</div><div class='ctx'> 	switch (soc15_asic_reset_method(adev)) {</div><div class='ctx'> 	case AMD_RESET_METHOD_PCI:</div><div class='ctx'> 		dev_info(adev-&gt;dev, "PCI reset\n");</div><div class='hunk'>@@ -614,13 +642,16 @@ static int soc15_asic_reset(struct amdgpu_device *adev)</div><div class='ctx'> 	case AMD_RESET_METHOD_MODE2:</div><div class='ctx'> 		dev_info(adev-&gt;dev, "MODE2 reset\n");</div><div class='ctx'> 		return amdgpu_dpm_mode2_reset(adev);</div><div class='add'>+	case AMD_RESET_METHOD_LINK:</div><div class='add'>+		dev_info(adev-&gt;dev, "Link reset\n");</div><div class='add'>+		return amdgpu_device_link_reset(adev);</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_info(adev-&gt;dev, "MODE1 reset\n");</div><div class='ctx'> 		return amdgpu_device_mode1_reset(adev);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool soc15_supports_baco(struct amdgpu_device *adev)</div><div class='add'>+static int soc15_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(9, 0, 0):</div><div class='hunk'>@@ -628,13 +659,13 @@ static bool soc15_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;asic_type == CHIP_VEGA20) {</div><div class='ctx'> 			if (adev-&gt;psp.sos.fw_version &gt;= 0x80067)</div><div class='ctx'> 				return amdgpu_dpm_is_baco_supported(adev);</div><div class='del'>-			return false;</div><div class='add'>+			return 0;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			return amdgpu_dpm_is_baco_supported(adev);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		return false;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -710,7 +741,6 @@ static void soc15_reg_base_init(struct amdgpu_device *adev)</div><div class='ctx'> void soc15_set_virt_ops(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;virt.ops = &amp;xgpu_ai_virt_ops;</div><div class='del'>-</div><div class='ctx'> 	/* init soc15 reg base early enough so we can</div><div class='ctx'> 	 * request request full access for sriov before</div><div class='ctx'> 	 * set_ip_blocks. */</div><div class='hunk'>@@ -823,10 +853,10 @@ static bool soc15_need_reset_on_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 sol_reg;</div><div class='ctx'> </div><div class='del'>-	/* CP hangs in IGT reloading test on RN, reset to WA */</div><div class='del'>-	if (adev-&gt;asic_type == CHIP_RENOIR)</div><div class='add'>+	if (amdgpu_gmc_need_reset_on_init(adev))</div><div class='add'>+		return true;</div><div class='add'>+	if (amdgpu_psp_tos_reload_needed(adev))</div><div class='ctx'> 		return true;</div><div class='del'>-</div><div class='ctx'> 	/* Just return false for soc15 GPUs.  Reset does not seem to</div><div class='ctx'> 	 * be necessary.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -927,15 +957,11 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =</div><div class='ctx'> 	.get_reg_state = &amp;aqua_vanjaram_get_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int soc15_common_early_init(void *handle)</div><div class='add'>+static int soc15_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-		adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='del'>-		adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='del'>-	}</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;set_reg_remap(adev);</div><div class='ctx'> 	adev-&gt;smc_rreg = NULL;</div><div class='ctx'> 	adev-&gt;smc_wreg = NULL;</div><div class='ctx'> 	adev-&gt;pcie_rreg = &amp;amdgpu_device_indirect_rreg;</div><div class='hunk'>@@ -1172,6 +1198,8 @@ static int soc15_common_early_init(void *handle)</div><div class='ctx'> 		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x3c;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		adev-&gt;asic_funcs = &amp;aqua_vanjaram_asic_funcs;</div><div class='ctx'> 		adev-&gt;cg_flags =</div><div class='ctx'> 			AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |</div><div class='hunk'>@@ -1183,12 +1211,10 @@ static int soc15_common_early_init(void *handle)</div><div class='ctx'> 			AMD_PG_SUPPORT_VCN |</div><div class='ctx'> 			AMD_PG_SUPPORT_VCN_DPG |</div><div class='ctx'> 			AMD_PG_SUPPORT_JPEG;</div><div class='add'>+		/*TODO: need a new external_rev_id for GC 9.4.4? */</div><div class='ctx'> 		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x46;</div><div class='del'>-		/* GC 9.4.3 uses MMIO register region hole at a different offset */</div><div class='del'>-		if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-			adev-&gt;rmmio_remap.reg_offset = 0x1A000;</div><div class='del'>-			adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + 0x1A000;</div><div class='del'>-		}</div><div class='add'>+		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))</div><div class='add'>+			adev-&gt;external_rev_id = adev-&gt;rev_id + 0x50;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* FIXME: not supported yet */</div><div class='hunk'>@@ -1203,9 +1229,9 @@ static int soc15_common_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_late_init(void *handle)</div><div class='add'>+static int soc15_common_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_ai_mailbox_get_irq(adev);</div><div class='hunk'>@@ -1218,9 +1244,9 @@ static int soc15_common_late_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_sw_init(void *handle)</div><div class='add'>+static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_ai_mailbox_add_irq_id(adev);</div><div class='hunk'>@@ -1232,9 +1258,9 @@ static int soc15_common_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_sw_fini(void *handle)</div><div class='add'>+static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;df.funcs &amp;&amp;</div><div class='ctx'> 	    adev-&gt;df.funcs-&gt;sw_fini)</div><div class='hunk'>@@ -1256,9 +1282,9 @@ static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_hw_init(void *handle)</div><div class='add'>+static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* enable aspm */</div><div class='ctx'> 	soc15_program_aspm(adev);</div><div class='hunk'>@@ -1285,9 +1311,9 @@ static int soc15_common_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_hw_fini(void *handle)</div><div class='add'>+static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable the doorbell aperture and selfring doorbell aperture</div><div class='ctx'> 	 * separately in hw_fini because soc15_enable_doorbell_aperture</div><div class='hunk'>@@ -1300,7 +1326,12 @@ static int soc15_common_hw_fini(void *handle)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_ai_mailbox_put_irq(adev);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * For minimal init, late_init is not called, hence RAS irqs are not</div><div class='add'>+	 * enabled.</div><div class='add'>+	 */</div><div class='ctx'> 	if ((!amdgpu_sriov_vf(adev)) &amp;&amp;</div><div class='add'>+	    (adev-&gt;init_lvl-&gt;level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) &amp;&amp;</div><div class='ctx'> 	    adev-&gt;nbio.ras_if &amp;&amp;</div><div class='ctx'> 	    amdgpu_ras_is_supported(adev, adev-&gt;nbio.ras_if-&gt;block)) {</div><div class='ctx'> 		if (adev-&gt;nbio.ras &amp;&amp;</div><div class='hunk'>@@ -1314,39 +1345,27 @@ static int soc15_common_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_suspend(void *handle)</div><div class='add'>+static int soc15_common_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return soc15_common_hw_fini(adev);</div><div class='add'>+	return soc15_common_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_resume(void *handle)</div><div class='add'>+static int soc15_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (soc15_need_reset_on_resume(adev)) {</div><div class='ctx'> 		dev_info(adev-&gt;dev, "S3 suspend abort case, let's reset ASIC.\n");</div><div class='ctx'> 		soc15_asic_reset(adev);</div><div class='ctx'> 	}</div><div class='del'>-	return soc15_common_hw_init(adev);</div><div class='add'>+	return soc15_common_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool soc15_common_is_idle(void *handle)</div><div class='add'>+static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int soc15_common_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t def, data;</div><div class='hunk'>@@ -1391,10 +1410,10 @@ static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable</div><div class='ctx'> 		WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_set_clockgating_state(void *handle,</div><div class='add'>+static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1443,9 +1462,9 @@ static int soc15_common_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void soc15_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1458,7 +1477,9 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		adev-&gt;hdp.funcs-&gt;get_clock_gating_state(adev, flags);</div><div class='ctx'> </div><div class='ctx'> 	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &amp;&amp;</div><div class='del'>-	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {</div><div class='add'>+	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &amp;&amp;</div><div class='add'>+	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) &amp;&amp;</div><div class='add'>+	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {</div><div class='ctx'> 		/* AMD_CG_SUPPORT_DRM_MGCG */</div><div class='ctx'> 		data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));</div><div class='ctx'> 		if (!(data &amp; 0x01000000))</div><div class='hunk'>@@ -1478,7 +1499,7 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		adev-&gt;df.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc15_common_set_powergating_state(void *handle,</div><div class='add'>+static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='hunk'>@@ -1496,8 +1517,6 @@ static const struct amd_ip_funcs soc15_common_ip_funcs = {</div><div class='ctx'> 	.suspend = soc15_common_suspend,</div><div class='ctx'> 	.resume = soc15_common_resume,</div><div class='ctx'> 	.is_idle = soc15_common_is_idle,</div><div class='del'>-	.wait_for_idle = soc15_common_wait_for_idle,</div><div class='del'>-	.soft_reset = soc15_common_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = soc15_common_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = soc15_common_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state= soc15_common_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h<br/>index 1444b7765e4b..c8ac11a9cdef 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc15.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/soc15.h</a></div><div class='hunk'>@@ -88,9 +88,15 @@ struct soc15_ras_field_entry {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg</div><div class='add'>+#define SOC15_REG_ENTRY_STR(ip, inst, reg) \</div><div class='add'>+	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }</div><div class='ctx'> </div><div class='ctx'> #define SOC15_REG_ENTRY_OFFSET(entry)	(adev-&gt;reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)</div><div class='ctx'> </div><div class='add'>+/* Over ride the instance id */</div><div class='add'>+#define SOC15_REG_ENTRY_OFFSET_INST(entry, inst) \</div><div class='add'>+	(adev-&gt;reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)</div><div class='add'>+</div><div class='ctx'> #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \</div><div class='ctx'> 	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }</div><div class='ctx'> </div><div class='hunk'>@@ -112,7 +118,6 @@ int vega10_reg_base_init(struct amdgpu_device *adev);</div><div class='ctx'> int vega20_reg_base_init(struct amdgpu_device *adev);</div><div class='ctx'> int arct_reg_base_init(struct amdgpu_device *adev);</div><div class='ctx'> int aldebaran_reg_base_init(struct amdgpu_device *adev);</div><div class='del'>-void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);</div><div class='ctx'> u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);</div><div class='ctx'> int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);</div><div class='ctx'> ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h<br/>index 2357ff39323f..cf93fa477674 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc15d.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc15d.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc15d.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/soc15d.h</a></div><div class='hunk'>@@ -76,6 +76,12 @@</div><div class='ctx'> 			 ((cond &amp; 0xF) &lt;&lt; 24) |				\</div><div class='ctx'> 			 ((type &amp; 0xF) &lt;&lt; 28))</div><div class='ctx'> </div><div class='add'>+#define CP_PACKETJ_NOP		0x60000000</div><div class='add'>+#define CP_PACKETJ_GET_REG(x)  ((x) &amp; 0x3FFFF)</div><div class='add'>+#define CP_PACKETJ_GET_RES(x)  (((x) &gt;&gt; 18) &amp; 0x3F)</div><div class='add'>+#define CP_PACKETJ_GET_COND(x) (((x) &gt;&gt; 24) &amp; 0xF)</div><div class='add'>+#define CP_PACKETJ_GET_TYPE(x) (((x) &gt;&gt; 28) &amp; 0xF)</div><div class='add'>+</div><div class='ctx'> /* Packet 3 types */</div><div class='ctx'> #define	PACKET3_NOP					0x10</div><div class='ctx'> #define	PACKET3_SET_BASE				0x11</div><div class='hunk'>@@ -87,11 +93,25 @@</div><div class='ctx'> #define	PACKET3_DISPATCH_INDIRECT			0x16</div><div class='ctx'> #define	PACKET3_ATOMIC_GDS				0x1D</div><div class='ctx'> #define	PACKET3_ATOMIC_MEM				0x1E</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) &amp; 0x3F) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) &amp; 0x1FFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC	0</div><div class='add'>+#define 	PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1</div><div class='ctx'> #define	PACKET3_OCCLUSION_QUERY				0x1F</div><div class='ctx'> #define	PACKET3_SET_PREDICATION				0x20</div><div class='ctx'> #define	PACKET3_REG_RMW					0x21</div><div class='ctx'> #define	PACKET3_COND_EXEC				0x22</div><div class='ctx'> #define	PACKET3_PRED_EXEC				0x23</div><div class='add'>+#define		PACKET3_PRED_EXEC__EXEC_COUNT(x)	((((unsigned)(x)) &amp; 0x3FFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_PRED_EXEC__VIRTUAL_XCC_ID_SELECT(x)	((((unsigned)(x)) &amp; 0xFF) &lt;&lt; 24)</div><div class='ctx'> #define	PACKET3_DRAW_INDIRECT				0x24</div><div class='ctx'> #define	PACKET3_DRAW_INDEX_INDIRECT			0x25</div><div class='ctx'> #define	PACKET3_INDEX_BASE				0x26</div><div class='hunk'>@@ -126,6 +146,28 @@</div><div class='ctx'> 		 * 1 - pfp</div><div class='ctx'> 		 * 2 - ce</div><div class='ctx'> 		 */</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define		PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 16)</div><div class='add'>+#define		PACKET3_WRITE_DATA__RESUME_VF_MI300(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 19)</div><div class='add'>+#define		PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 20)</div><div class='add'>+#define		PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER	0</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_SEL__TC_L2	2</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_SEL__GDS	3</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_SEL__MEMORY	5</div><div class='add'>+#define		PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE	6</div><div class='add'>+#define		PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS	0</div><div class='add'>+#define		PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS	1</div><div class='add'>+#define		PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION	0</div><div class='add'>+#define		PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION	1</div><div class='add'>+#define		PACKET3_WRITE_DATA__CACHE_POLICY__LRU	0</div><div class='add'>+#define		PACKET3_WRITE_DATA__CACHE_POLICY__STREAM	1</div><div class='add'>+#define		PACKET3_WRITE_DATA__CACHE_POLICY__NOA	2</div><div class='add'>+#define		PACKET3_WRITE_DATA__CACHE_POLICY__BYPASS	3</div><div class='ctx'> #define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38</div><div class='ctx'> #define	PACKET3_MEM_SEMAPHORE				0x39</div><div class='ctx'> #              define PACKET3_SEM_USE_MAILBOX       (0x1 &lt;&lt; 16)</div><div class='hunk'>@@ -154,6 +196,33 @@</div><div class='ctx'> 		/* 0 - me</div><div class='ctx'> 		 * 1 - pfp</div><div class='ctx'> 		 */</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) &amp; 0x7) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 4)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 6)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 22)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 24)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 31)</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS	0</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE	1</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE	2</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE	3</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE	4</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE	5</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE	6</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE	0</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE	1</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM	0</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG	1</div><div class='add'>+#define		PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE	3</div><div class='ctx'> #define	PACKET3_INDIRECT_BUFFER				0x3F</div><div class='ctx'> #define		INDIRECT_BUFFER_VALID                   (1 &lt;&lt; 23)</div><div class='ctx'> #define		INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) &lt;&lt; 28)</div><div class='hunk'>@@ -163,7 +232,63 @@</div><div class='ctx'> 		 */</div><div class='ctx'> #define     INDIRECT_BUFFER_PRE_ENB(x)		 ((x) &lt;&lt; 21)</div><div class='ctx'> #define     INDIRECT_BUFFER_PRE_RESUME(x)               ((x) &lt;&lt; 30)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) &amp; 0xFFFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 20)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 21)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 23)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 24)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 28)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 31)</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__CACHE_POLICY__LRU	0</div><div class='add'>+#define		PACKET3_INDIRECT_BUFFER__CACHE_POLICY__STREAM	1</div><div class='ctx'> #define	PACKET3_COPY_DATA				0x40</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 13)</div><div class='add'>+#define		PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 16)</div><div class='add'>+#define		PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 20)</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 25)</div><div class='add'>+#define		PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 29)</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x1FFFFFFF) &lt;&lt; 3)</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) &amp; 0x3FFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x3FFFFFFF) &lt;&lt; 2)</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) &amp; 0x1FFFFFFF) &lt;&lt; 3)</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER	0</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__MEMORY	1</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__TC_L2	2</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__GDS	3</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS	4</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA	5</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA	6</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA0	7</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__GDS_ATOMIC_RETURN_DATA1	8</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT	9</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER	0</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL__TC_L2	2</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL__GDS	3</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS	4</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL__MEMORY	5</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC	6</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_CACHE_POLICY__LRU	0</div><div class='add'>+#define		PACKET3_COPY_DATA__SRC_CACHE_POLICY__STREAM 1</div><div class='add'>+#define		PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA	0</div><div class='add'>+#define		PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA	1</div><div class='add'>+#define		PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION	0</div><div class='add'>+#define		PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION	1</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_CACHE_POLICY__LRU	0</div><div class='add'>+#define		PACKET3_COPY_DATA__DST_CACHE_POLICY__STREAM	1</div><div class='add'>+#define		PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT	0</div><div class='add'>+#define		PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE	1</div><div class='ctx'> #define	PACKET3_PFP_SYNC_ME				0x42</div><div class='ctx'> #define	PACKET3_COND_WRITE				0x45</div><div class='ctx'> #define	PACKET3_EVENT_WRITE				0x46</div><div class='hunk'>@@ -175,6 +300,15 @@</div><div class='ctx'> 		 * 3 - SAMPLE_STREAMOUTSTAT*</div><div class='ctx'> 		 * 4 - *S_PARTIAL_FLUSH</div><div class='ctx'> 		 */</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) &amp; 0x3F) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 8)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) &amp; 0x1) &lt;&lt; 31)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) &amp; 0x3) &lt;&lt; 29)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) &amp; 0x1FFFFFFF) &lt;&lt; 3)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__ADDRESS_HI(x) (((unsigned)(x)) &lt;&lt; 0)</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER	0</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTATS	2</div><div class='add'>+#define		PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH	4</div><div class='ctx'> #define	PACKET3_RELEASE_MEM				0x49</div><div class='ctx'> #define		EVENT_TYPE(x)                           ((x) &lt;&lt; 0)</div><div class='ctx'> #define		EVENT_INDEX(x)                          ((x) &lt;&lt; 8)</div><div class='hunk'>@@ -280,6 +414,13 @@</div><div class='ctx'> #define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) &lt;&lt; 29)</div><div class='ctx'> #define 	PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) &lt;&lt; 30)</div><div class='ctx'> #define	PACKET3_REWIND					0x59</div><div class='add'>+#define		PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) &amp; 0xFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_SIZE_HI_VG10(x) ((((unsigned)(x)) &amp; 0xFFFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) &amp; 0xFFFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) &amp; 0x7FF) &lt;&lt; 0)</div><div class='ctx'> #define	PACKET3_LOAD_UCONFIG_REG			0x5E</div><div class='ctx'> #define	PACKET3_LOAD_SH_REG				0x5F</div><div class='ctx'> #define	PACKET3_LOAD_CONFIG_REG				0x60</div><div class='hunk'>@@ -294,12 +435,16 @@</div><div class='ctx'> #define	PACKET3_SET_SH_REG				0x76</div><div class='ctx'> #define		PACKET3_SET_SH_REG_START			0x00002c00</div><div class='ctx'> #define		PACKET3_SET_SH_REG_END				0x00003000</div><div class='add'>+#define 	PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='add'>+#define 	PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) &amp; 0x1F) &lt;&lt; 23)</div><div class='add'>+#define 	PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) &amp; 0xF) &lt;&lt; 28)</div><div class='ctx'> #define	PACKET3_SET_SH_REG_OFFSET			0x77</div><div class='ctx'> #define	PACKET3_SET_QUEUE_REG				0x78</div><div class='ctx'> #define	PACKET3_SET_UCONFIG_REG				0x79</div><div class='ctx'> #define		PACKET3_SET_UCONFIG_REG_START			0x0000c000</div><div class='ctx'> #define		PACKET3_SET_UCONFIG_REG_END			0x0000c400</div><div class='ctx'> #define		PACKET3_SET_UCONFIG_REG_INDEX_TYPE		(2 &lt;&lt; 28)</div><div class='add'>+#define 	PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) &amp; 0xFFFF) &lt;&lt; 0)</div><div class='ctx'> #define	PACKET3_SCRATCH_RAM_WRITE			0x7D</div><div class='ctx'> #define	PACKET3_SCRATCH_RAM_READ			0x7E</div><div class='ctx'> #define	PACKET3_LOAD_CONST_RAM				0x80</div><div class='hunk'>@@ -407,6 +552,15 @@</div><div class='ctx'> #              define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x)  ((x) &lt;&lt; 2)</div><div class='ctx'> #              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) &lt;&lt; 25)</div><div class='ctx'> </div><div class='add'>+#define PACKET3_RUN_CLEANER_SHADER_9_0                      0xD7</div><div class='add'>+/* 1. header</div><div class='add'>+ * 2. RESERVED [31:0]</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define PACKET3_RUN_CLEANER_SHADER                      0xD2</div><div class='add'>+/* 1. header</div><div class='add'>+ * 2. RESERVED [31:0]</div><div class='add'>+ */</div><div class='ctx'> </div><div class='ctx'> #define VCE_CMD_NO_OP		0x00000000</div><div class='ctx'> #define VCE_CMD_END		0x00000001</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c<br/>index 581a3bd11481..ad36c96478a8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc21.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/soc21.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc21.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/soc21.c</a></div><div class='hunk'>@@ -49,13 +49,13 @@ static const struct amd_ip_funcs soc21_common_ip_funcs;</div><div class='ctx'> </div><div class='ctx'> /* SOC21 */</div><div class='ctx'> static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -72,7 +72,7 @@ static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {</div><div class='ctx'> static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='hunk'>@@ -80,7 +80,7 @@ static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_</div><div class='ctx'> static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -96,14 +96,14 @@ static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {</div><div class='ctx'> </div><div class='ctx'> /* SRIOV SOC21, not const since data is controlled by host */</div><div class='ctx'> static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {</div><div class='hunk'>@@ -117,23 +117,17 @@ static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='del'>-	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='ctx'> 	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -389,6 +383,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(13, 0, 11):</div><div class='ctx'> 	case IP_VERSION(14, 0, 0):</div><div class='ctx'> 	case IP_VERSION(14, 0, 1):</div><div class='add'>+	case IP_VERSION(14, 0, 4):</div><div class='add'>+	case IP_VERSION(14, 0, 5):</div><div class='ctx'> 		return AMD_RESET_METHOD_MODE2;</div><div class='ctx'> 	default:</div><div class='ctx'> 		if (amdgpu_dpm_is_baco_supported(adev))</div><div class='hunk'>@@ -457,10 +453,8 @@ static bool soc21_need_full_reset(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(11, 0, 0):</div><div class='del'>-		return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);</div><div class='ctx'> 	case IP_VERSION(11, 0, 2):</div><div class='ctx'> 	case IP_VERSION(11, 0, 3):</div><div class='del'>-		return false;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -557,13 +551,11 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs = {</div><div class='ctx'> 	.update_umd_stable_pstate = &amp;soc21_update_umd_stable_pstate,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int soc21_common_early_init(void *handle)</div><div class='add'>+static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;</div><div class='del'>-	adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + MMIO_REG_HOLE_OFFSET;</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;set_reg_remap(adev);</div><div class='ctx'> 	adev-&gt;smc_rreg = NULL;</div><div class='ctx'> 	adev-&gt;smc_wreg = NULL;</div><div class='ctx'> 	adev-&gt;pcie_rreg = &amp;amdgpu_device_indirect_rreg;</div><div class='hunk'>@@ -722,7 +714,10 @@ static int soc21_common_early_init(void *handle)</div><div class='ctx'> 			AMD_PG_SUPPORT_VCN |</div><div class='ctx'> 			AMD_PG_SUPPORT_JPEG |</div><div class='ctx'> 			AMD_PG_SUPPORT_GFX_PG;</div><div class='del'>-		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x1;</div><div class='add'>+		if (adev-&gt;rev_id == 0)</div><div class='add'>+			adev-&gt;external_rev_id = 0x1;</div><div class='add'>+		else</div><div class='add'>+			adev-&gt;external_rev_id = adev-&gt;rev_id + 0x10;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='ctx'> 		adev-&gt;cg_flags =</div><div class='hunk'>@@ -753,6 +748,62 @@ static int soc21_common_early_init(void *handle)</div><div class='ctx'> 			AMD_PG_SUPPORT_JPEG;</div><div class='ctx'> 		adev-&gt;external_rev_id = adev-&gt;rev_id + 0xc1;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+		adev-&gt;cg_flags = AMD_CG_SUPPORT_VCN_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_JPEG_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_REPEATER_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_PERF_CLK	|</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGLS	|</div><div class='add'>+			AMD_CG_SUPPORT_MC_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_MC_LS |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_LS |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_DS |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_SD |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_LS |</div><div class='add'>+			AMD_CG_SUPPORT_IH_CG |</div><div class='add'>+			AMD_CG_SUPPORT_BIF_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_BIF_LS;</div><div class='add'>+		adev-&gt;pg_flags = AMD_PG_SUPPORT_VCN_DPG |</div><div class='add'>+			AMD_PG_SUPPORT_VCN |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG_DPG |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG |</div><div class='add'>+			AMD_PG_SUPPORT_GFX_PG;</div><div class='add'>+		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x40;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='add'>+		adev-&gt;cg_flags = AMD_CG_SUPPORT_VCN_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_JPEG_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_REPEATER_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_PERF_CLK |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_MC_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_MC_LS |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_LS |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_DS |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_SD |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_LS |</div><div class='add'>+			AMD_CG_SUPPORT_IH_CG |</div><div class='add'>+			AMD_CG_SUPPORT_BIF_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_BIF_LS;</div><div class='add'>+		adev-&gt;pg_flags = AMD_PG_SUPPORT_VCN_DPG |</div><div class='add'>+			AMD_PG_SUPPORT_VCN |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG_DPG |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG |</div><div class='add'>+			AMD_PG_SUPPORT_GFX_PG;</div><div class='add'>+		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x50;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* FIXME: not supported yet */</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -766,9 +817,9 @@ static int soc21_common_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_late_init(void *handle)</div><div class='add'>+static int soc21_common_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		xgpu_nv_mailbox_get_irq(adev);</div><div class='hunk'>@@ -804,9 +855,9 @@ static int soc21_common_late_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_sw_init(void *handle)</div><div class='add'>+static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_nv_mailbox_add_irq_id(adev);</div><div class='hunk'>@@ -814,14 +865,9 @@ static int soc21_common_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_sw_fini(void *handle)</div><div class='add'>+static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int soc21_common_hw_init(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* enable aspm */</div><div class='ctx'> 	soc21_program_aspm(adev);</div><div class='hunk'>@@ -839,9 +885,9 @@ static int soc21_common_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_hw_fini(void *handle)</div><div class='add'>+static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable the doorbell aperture and selfring doorbell aperture</div><div class='ctx'> 	 * separately in hw_fini because soc21_enable_doorbell_aperture</div><div class='hunk'>@@ -862,39 +908,53 @@ static int soc21_common_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_suspend(void *handle)</div><div class='add'>+static int soc21_common_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return soc21_common_hw_fini(adev);</div><div class='add'>+	return soc21_common_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_resume(void *handle)</div><div class='add'>+static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	u32 sol_reg1, sol_reg2;</div><div class='ctx'> </div><div class='del'>-	return soc21_common_hw_init(adev);</div><div class='del'>-}</div><div class='add'>+	/* Will reset for the following suspend abort cases.</div><div class='add'>+	 * 1) Only reset dGPU side.</div><div class='add'>+	 * 2) S3 suspend got aborted and TOS is active.</div><div class='add'>+	 *    As for dGPU suspend abort cases the SOL value</div><div class='add'>+	 *    will be kept as zero at this resume point.</div><div class='add'>+	 */</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; adev-&gt;in_s3) {</div><div class='add'>+		sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);</div><div class='add'>+		msleep(100);</div><div class='add'>+		sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);</div><div class='ctx'> </div><div class='del'>-static bool soc21_common_is_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return true;</div><div class='add'>+		return (sol_reg1 != sol_reg2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_wait_for_idle(void *handle)</div><div class='add'>+static int soc21_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (soc21_need_reset_on_resume(adev)) {</div><div class='add'>+		dev_info(adev-&gt;dev, "S3 suspend aborted, resetting...");</div><div class='add'>+		soc21_asic_reset(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return soc21_common_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_soft_reset(void *handle)</div><div class='add'>+static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	return 0;</div><div class='add'>+	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_set_clockgating_state(void *handle,</div><div class='add'>+static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(4, 3, 0):</div><div class='hunk'>@@ -903,6 +963,8 @@ static int soc21_common_set_clockgating_state(void *handle,</div><div class='ctx'> 	case IP_VERSION(7, 7, 1):</div><div class='ctx'> 	case IP_VERSION(7, 11, 0):</div><div class='ctx'> 	case IP_VERSION(7, 11, 1):</div><div class='add'>+	case IP_VERSION(7, 11, 2):</div><div class='add'>+	case IP_VERSION(7, 11, 3):</div><div class='ctx'> 		adev-&gt;nbio.funcs-&gt;update_medium_grain_clock_gating(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='ctx'> 		adev-&gt;nbio.funcs-&gt;update_medium_grain_light_sleep(adev,</div><div class='hunk'>@@ -916,10 +978,10 @@ static int soc21_common_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int soc21_common_set_powergating_state(void *handle,</div><div class='add'>+static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(6, 0, 0):</div><div class='hunk'>@@ -934,9 +996,9 @@ static int soc21_common_set_powergating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void soc21_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;nbio.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='ctx'> </div><div class='hunk'>@@ -948,14 +1010,11 @@ static const struct amd_ip_funcs soc21_common_ip_funcs = {</div><div class='ctx'> 	.early_init = soc21_common_early_init,</div><div class='ctx'> 	.late_init = soc21_common_late_init,</div><div class='ctx'> 	.sw_init = soc21_common_sw_init,</div><div class='del'>-	.sw_fini = soc21_common_sw_fini,</div><div class='ctx'> 	.hw_init = soc21_common_hw_init,</div><div class='ctx'> 	.hw_fini = soc21_common_hw_fini,</div><div class='ctx'> 	.suspend = soc21_common_suspend,</div><div class='ctx'> 	.resume = soc21_common_resume,</div><div class='ctx'> 	.is_idle = soc21_common_is_idle,</div><div class='del'>-	.wait_for_idle = soc21_common_wait_for_idle,</div><div class='del'>-	.soft_reset = soc21_common_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = soc21_common_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = soc21_common_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = soc21_common_get_clockgating_state,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c<br/>new file mode 100644<br/>index 000000000000..972b449ab89f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc24.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/soc24.c</a></div><div class='hunk'>@@ -0,0 +1,601 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_ih.h"</div><div class='add'>+#include "amdgpu_uvd.h"</div><div class='add'>+#include "amdgpu_vce.h"</div><div class='add'>+#include "amdgpu_ucode.h"</div><div class='add'>+#include "amdgpu_psp.h"</div><div class='add'>+#include "amdgpu_smu.h"</div><div class='add'>+#include "atom.h"</div><div class='add'>+#include "amd_pcie.h"</div><div class='add'>+</div><div class='add'>+#include "gc/gc_12_0_0_offset.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "mp/mp_14_0_2_offset.h"</div><div class='add'>+</div><div class='add'>+#include "soc15.h"</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "soc24.h"</div><div class='add'>+#include "mxgpu_nv.h"</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs soc24_common_ip_funcs;</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = {</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_encode_vcn0 = {</div><div class='add'>+	.codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_encode_array_vcn0),</div><div class='add'>+	.codec_array = vcn_5_0_0_video_codecs_encode_array_vcn0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_decode_array_vcn0[] = {</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},</div><div class='add'>+	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_decode_vcn0 = {</div><div class='add'>+	.codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_decode_array_vcn0),</div><div class='add'>+	.codec_array = vcn_5_0_0_video_codecs_decode_array_vcn0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode,</div><div class='add'>+				 const struct amdgpu_video_codecs **codecs)</div><div class='add'>+{</div><div class='add'>+	if (adev-&gt;vcn.num_vcn_inst == hweight8(adev-&gt;vcn.harvest_config))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(5, 0, 0):</div><div class='add'>+		if (encode)</div><div class='add'>+			*codecs = &amp;vcn_5_0_0_video_codecs_encode_vcn0;</div><div class='add'>+		else</div><div class='add'>+			*codecs = &amp;vcn_5_0_0_video_codecs_decode_vcn0;</div><div class='add'>+		return 0;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 soc24_get_config_memsize(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return adev-&gt;nbio.funcs-&gt;get_memsize(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 soc24_get_xclk(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return adev-&gt;clock.spll.reference_freq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void soc24_grbm_select(struct amdgpu_device *adev,</div><div class='add'>+		       u32 me, u32 pipe, u32 queue, u32 vmid)</div><div class='add'>+{</div><div class='add'>+	u32 grbm_gfx_cntl = 0;</div><div class='add'>+	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);</div><div class='add'>+	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);</div><div class='add'>+	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);</div><div class='add'>+	grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},</div><div class='add'>+	{ SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},</div><div class='add'>+	{ SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_STAT)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},</div><div class='add'>+	{ SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,</div><div class='add'>+					    u32 se_num,</div><div class='add'>+					    u32 sh_num,</div><div class='add'>+					    u32 reg_offset)</div><div class='add'>+{</div><div class='add'>+	uint32_t val;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='add'>+	if (se_num != 0xffffffff || sh_num != 0xffffffff)</div><div class='add'>+		amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);</div><div class='add'>+</div><div class='add'>+	val = RREG32(reg_offset);</div><div class='add'>+</div><div class='add'>+	if (se_num != 0xffffffff || sh_num != 0xffffffff)</div><div class='add'>+		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t soc24_get_register_value(struct amdgpu_device *adev,</div><div class='add'>+					 bool indexed, u32 se_num,</div><div class='add'>+					 u32 sh_num, u32 reg_offset)</div><div class='add'>+{</div><div class='add'>+	if (indexed) {</div><div class='add'>+		return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset);</div><div class='add'>+	} else {</div><div class='add'>+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &amp;&amp;</div><div class='add'>+		    adev-&gt;gfx.config.gb_addr_config)</div><div class='add'>+			return adev-&gt;gfx.config.gb_addr_config;</div><div class='add'>+		return RREG32(reg_offset);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_read_register(struct amdgpu_device *adev, u32 se_num,</div><div class='add'>+			       u32 sh_num, u32 reg_offset, u32 *value)</div><div class='add'>+{</div><div class='add'>+	uint32_t i;</div><div class='add'>+	struct soc15_allowed_register_entry  *en;</div><div class='add'>+</div><div class='add'>+	*value = 0;</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(soc24_allowed_read_registers); i++) {</div><div class='add'>+		en = &amp;soc24_allowed_read_registers[i];</div><div class='add'>+		if (!adev-&gt;reg_offset[en-&gt;hwip][en-&gt;inst])</div><div class='add'>+			continue;</div><div class='add'>+		else if (reg_offset != (adev-&gt;reg_offset[en-&gt;hwip][en-&gt;inst][en-&gt;seg]</div><div class='add'>+					+ en-&gt;reg_offset))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		*value = soc24_get_register_value(adev,</div><div class='add'>+				soc24_allowed_read_registers[i].grbm_indexed,</div><div class='add'>+				se_num, sh_num, reg_offset);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum amd_reset_method</div><div class='add'>+soc24_asic_reset_method(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||</div><div class='add'>+	    amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||</div><div class='add'>+	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)</div><div class='add'>+		return amdgpu_reset_method;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_reset_method != -1)</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			 "Specified reset method:%d isn't supported, using AUTO instead.\n",</div><div class='add'>+			 amdgpu_reset_method);</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(14, 0, 2):</div><div class='add'>+	case IP_VERSION(14, 0, 3):</div><div class='add'>+		return AMD_RESET_METHOD_MODE1;</div><div class='add'>+	default:</div><div class='add'>+		if (amdgpu_dpm_is_baco_supported(adev))</div><div class='add'>+			return AMD_RESET_METHOD_BACO;</div><div class='add'>+		else</div><div class='add'>+			return AMD_RESET_METHOD_MODE1;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_asic_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	switch (soc24_asic_reset_method(adev)) {</div><div class='add'>+	case AMD_RESET_METHOD_PCI:</div><div class='add'>+		dev_info(adev-&gt;dev, "PCI reset\n");</div><div class='add'>+		ret = amdgpu_device_pci_reset(adev);</div><div class='add'>+		break;</div><div class='add'>+	case AMD_RESET_METHOD_BACO:</div><div class='add'>+		dev_info(adev-&gt;dev, "BACO reset\n");</div><div class='add'>+		ret = amdgpu_dpm_baco_reset(adev);</div><div class='add'>+		break;</div><div class='add'>+	case AMD_RESET_METHOD_MODE2:</div><div class='add'>+		dev_info(adev-&gt;dev, "MODE2 reset\n");</div><div class='add'>+		ret = amdgpu_dpm_mode2_reset(adev);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_info(adev-&gt;dev, "MODE1 reset\n");</div><div class='add'>+		ret = amdgpu_device_mode1_reset(adev);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void soc24_program_aspm(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_device_should_use_aspm(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp;</div><div class='add'>+	    (adev-&gt;nbio.funcs-&gt;program_aspm))</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;program_aspm(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version soc24_common_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_COMMON,</div><div class='add'>+	.major = 1,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;soc24_common_ip_funcs,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool soc24_need_full_reset(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+	default:</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool soc24_need_reset_on_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 sol_reg;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Check sOS sign of life register to confirm sys driver and sOS</div><div class='add'>+	 * are already been loaded.</div><div class='add'>+	 */</div><div class='add'>+	sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);</div><div class='add'>+	if (sol_reg)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	/* TODO</div><div class='add'>+	 * dummy implement for pcie_replay_count sysfs interface</div><div class='add'>+	 * */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void soc24_init_doorbell_index(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;</div><div class='add'>+	adev-&gt;doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;</div><div class='add'>+	adev-&gt;doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;</div><div class='add'>+	adev-&gt;doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;</div><div class='add'>+	adev-&gt;doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;</div><div class='add'>+	adev-&gt;doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;</div><div class='add'>+	adev-&gt;doorbell_index.gfx_userqueue_start =</div><div class='add'>+		AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;</div><div class='add'>+	adev-&gt;doorbell_index.gfx_userqueue_end =</div><div class='add'>+		AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;</div><div class='add'>+	adev-&gt;doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;</div><div class='add'>+	adev-&gt;doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;</div><div class='add'>+	adev-&gt;doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;</div><div class='add'>+	adev-&gt;doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;</div><div class='add'>+	adev-&gt;doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;</div><div class='add'>+	adev-&gt;doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;</div><div class='add'>+	adev-&gt;doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;</div><div class='add'>+	adev-&gt;doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;</div><div class='add'>+	adev-&gt;doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;</div><div class='add'>+	adev-&gt;doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;</div><div class='add'>+	adev-&gt;doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;</div><div class='add'>+</div><div class='add'>+	adev-&gt;doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT &lt;&lt; 1;</div><div class='add'>+	adev-&gt;doorbell_index.sdma_doorbell_range = 20;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void soc24_pre_asic_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev,</div><div class='add'>+					  bool enter)</div><div class='add'>+{</div><div class='add'>+	if (enter)</div><div class='add'>+		amdgpu_gfx_rlc_enter_safe_mode(adev, 0);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_gfx_rlc_exit_safe_mode(adev, 0);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gfx.funcs-&gt;update_perfmon_mgcg)</div><div class='add'>+		adev-&gt;gfx.funcs-&gt;update_perfmon_mgcg(adev, !enter);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_asic_funcs soc24_asic_funcs = {</div><div class='add'>+	.read_bios_from_rom = &amp;amdgpu_soc15_read_bios_from_rom,</div><div class='add'>+	.read_register = &amp;soc24_read_register,</div><div class='add'>+	.reset = &amp;soc24_asic_reset,</div><div class='add'>+	.reset_method = &amp;soc24_asic_reset_method,</div><div class='add'>+	.get_xclk = &amp;soc24_get_xclk,</div><div class='add'>+	.get_config_memsize = &amp;soc24_get_config_memsize,</div><div class='add'>+	.init_doorbell_index = &amp;soc24_init_doorbell_index,</div><div class='add'>+	.need_full_reset = &amp;soc24_need_full_reset,</div><div class='add'>+	.need_reset_on_init = &amp;soc24_need_reset_on_init,</div><div class='add'>+	.get_pcie_replay_count = &amp;soc24_get_pcie_replay_count,</div><div class='add'>+	.supports_baco = &amp;amdgpu_dpm_is_baco_supported,</div><div class='add'>+	.pre_asic_init = &amp;soc24_pre_asic_init,</div><div class='add'>+	.query_video_codecs = &amp;soc24_query_video_codecs,</div><div class='add'>+	.update_umd_stable_pstate = &amp;soc24_update_umd_stable_pstate,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int soc24_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;set_reg_remap(adev);</div><div class='add'>+	adev-&gt;smc_rreg = NULL;</div><div class='add'>+	adev-&gt;smc_wreg = NULL;</div><div class='add'>+	adev-&gt;pcie_rreg = &amp;amdgpu_device_indirect_rreg;</div><div class='add'>+	adev-&gt;pcie_wreg = &amp;amdgpu_device_indirect_wreg;</div><div class='add'>+	adev-&gt;pcie_rreg64 = &amp;amdgpu_device_indirect_rreg64;</div><div class='add'>+	adev-&gt;pcie_wreg64 = &amp;amdgpu_device_indirect_wreg64;</div><div class='add'>+	adev-&gt;pciep_rreg = amdgpu_device_pcie_port_rreg;</div><div class='add'>+	adev-&gt;pciep_wreg = amdgpu_device_pcie_port_wreg;</div><div class='add'>+	adev-&gt;uvd_ctx_rreg = NULL;</div><div class='add'>+	adev-&gt;uvd_ctx_wreg = NULL;</div><div class='add'>+	adev-&gt;didt_rreg = NULL;</div><div class='add'>+	adev-&gt;didt_wreg = NULL;</div><div class='add'>+</div><div class='add'>+	adev-&gt;asic_funcs = &amp;soc24_asic_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;rev_id = amdgpu_device_get_rev_id(adev);</div><div class='add'>+	adev-&gt;external_rev_id = 0xff;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+		adev-&gt;cg_flags = AMD_CG_SUPPORT_GFX_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_REPEATER_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_PERF_CLK |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_LS |</div><div class='add'>+			AMD_CG_SUPPORT_MC_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_SD |</div><div class='add'>+			AMD_CG_SUPPORT_MC_LS;</div><div class='add'>+		adev-&gt;pg_flags = AMD_PG_SUPPORT_VCN |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG |</div><div class='add'>+			AMD_PG_SUPPORT_VCN_DPG;</div><div class='add'>+		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x40;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		adev-&gt;cg_flags = AMD_CG_SUPPORT_GFX_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_3D_CGLS |</div><div class='add'>+			AMD_CG_SUPPORT_REPEATER_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_FGCG |</div><div class='add'>+			AMD_CG_SUPPORT_GFX_PERF_CLK |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_ATHUB_LS |</div><div class='add'>+			AMD_CG_SUPPORT_MC_MGCG |</div><div class='add'>+			AMD_CG_SUPPORT_HDP_SD |</div><div class='add'>+			AMD_CG_SUPPORT_MC_LS;</div><div class='add'>+</div><div class='add'>+		adev-&gt;pg_flags = AMD_PG_SUPPORT_VCN |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG |</div><div class='add'>+			AMD_PG_SUPPORT_JPEG_DPG |</div><div class='add'>+			AMD_PG_SUPPORT_VCN_DPG;</div><div class='add'>+		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x50;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		/* FIXME: not supported yet */</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		amdgpu_virt_init_setting(adev);</div><div class='add'>+		xgpu_nv_mailbox_set_irq_funcs(adev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_late_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		xgpu_nv_mailbox_get_irq(adev);</div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;nbio.ras &amp;&amp;</div><div class='add'>+		    adev-&gt;nbio.ras_err_event_athub_irq.funcs)</div><div class='add'>+			/* don't need to fail gpu late init</div><div class='add'>+			 * if enabling athub_err_event interrupt failed</div><div class='add'>+			 * nbif v6_3_1 only support fatal error hanlding</div><div class='add'>+			 * just enable the interrupt directly</div><div class='add'>+			 */</div><div class='add'>+			amdgpu_irq_get(adev, &amp;adev-&gt;nbio.ras_err_event_athub_irq, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Enable selfring doorbell aperture late because doorbell BAR</div><div class='add'>+	 * aperture will change if resize BAR successfully in gmc sw_init.</div><div class='add'>+	 */</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;enable_doorbell_selfring_aperture(adev, true);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		xgpu_nv_mailbox_add_irq_id(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* enable aspm */</div><div class='add'>+	soc24_program_aspm(adev);</div><div class='add'>+	/* setup nbio registers */</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;init_registers(adev);</div><div class='add'>+	/* remap HDP registers to a hole in mmio space,</div><div class='add'>+	 * for the purpose of expose those registers</div><div class='add'>+	 * to process space</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;nbio.funcs-&gt;remap_hdp_registers)</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;remap_hdp_registers(adev);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;df.funcs-&gt;hw_init)</div><div class='add'>+		adev-&gt;df.funcs-&gt;hw_init(adev);</div><div class='add'>+</div><div class='add'>+	/* enable the doorbell aperture */</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;enable_doorbell_aperture(adev, true);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* Disable the doorbell aperture and selfring doorbell aperture</div><div class='add'>+	 * separately in hw_fini because soc21_enable_doorbell_aperture</div><div class='add'>+	 * has been removed and there is no need to delay disabling</div><div class='add'>+	 * selfring doorbell.</div><div class='add'>+	 */</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;enable_doorbell_aperture(adev, false);</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;enable_doorbell_selfring_aperture(adev, false);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		xgpu_nv_mailbox_put_irq(adev);</div><div class='add'>+	} else {</div><div class='add'>+		if (adev-&gt;nbio.ras &amp;&amp;</div><div class='add'>+		    adev-&gt;nbio.ras_err_event_athub_irq.funcs)</div><div class='add'>+			amdgpu_irq_put(adev, &amp;adev-&gt;nbio.ras_err_event_athub_irq, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return soc24_common_hw_fini(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return soc24_common_hw_init(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					      enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(6, 3, 1):</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;update_medium_grain_clock_gating(adev,</div><div class='add'>+				state == AMD_CG_STATE_GATE);</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;update_medium_grain_light_sleep(adev,</div><div class='add'>+				state == AMD_CG_STATE_GATE);</div><div class='add'>+		adev-&gt;hdp.funcs-&gt;update_clock_gating(adev,</div><div class='add'>+				state == AMD_CG_STATE_GATE);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					      enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(7, 0, 0):</div><div class='add'>+	case IP_VERSION(7, 0, 1):</div><div class='add'>+		adev-&gt;lsdma.funcs-&gt;update_memory_power_gating(adev,</div><div class='add'>+				state == AMD_PG_STATE_GATE);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void soc24_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='add'>+</div><div class='add'>+	adev-&gt;hdp.funcs-&gt;get_clock_gating_state(adev, flags);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs soc24_common_ip_funcs = {</div><div class='add'>+	.name = "soc24_common",</div><div class='add'>+	.early_init = soc24_common_early_init,</div><div class='add'>+	.late_init = soc24_common_late_init,</div><div class='add'>+	.sw_init = soc24_common_sw_init,</div><div class='add'>+	.hw_init = soc24_common_hw_init,</div><div class='add'>+	.hw_fini = soc24_common_hw_fini,</div><div class='add'>+	.suspend = soc24_common_suspend,</div><div class='add'>+	.resume = soc24_common_resume,</div><div class='add'>+	.is_idle = soc24_common_is_idle,</div><div class='add'>+	.set_clockgating_state = soc24_common_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = soc24_common_set_powergating_state,</div><div class='add'>+	.get_clockgating_state = soc24_common_get_clockgating_state,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.h b/drivers/gpu/drm/amd/amdgpu/soc24.h<br/>new file mode 100644<br/>index 000000000000..fa7e442e0b62<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/soc24.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/soc24.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#ifndef __SOC24_H__</div><div class='add'>+#define __SOC24_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_ip_block_version soc24_common_ip_block;</div><div class='add'>+</div><div class='add'>+void soc24_grbm_select(struct amdgpu_device *adev,</div><div class='add'>+		       u32 me, u32 pipe, u32 queue, u32 vmid);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h<br/>index 056d4df8fa1f..8a3f326474e5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ta_ras_if.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/ta_ras_if.h</a></div><div class='hunk'>@@ -30,6 +30,9 @@</div><div class='ctx'> #define RSP_ID_MASK (1U &lt;&lt; 31)</div><div class='ctx'> #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)</div><div class='ctx'> </div><div class='add'>+/* invalid node instance value */</div><div class='add'>+#define TA_RAS_INV_NODE 0xffff</div><div class='add'>+</div><div class='ctx'> /* RAS related enumerations */</div><div class='ctx'> /**********************************************************/</div><div class='ctx'> enum ras_command {</div><div class='hunk'>@@ -89,6 +92,9 @@ enum ta_ras_block {</div><div class='ctx'> 	TA_RAS_BLOCK__MCA,</div><div class='ctx'> 	TA_RAS_BLOCK__VCN,</div><div class='ctx'> 	TA_RAS_BLOCK__JPEG,</div><div class='add'>+	TA_RAS_BLOCK__IH,</div><div class='add'>+	TA_RAS_BLOCK__MPIO,</div><div class='add'>+	TA_RAS_BLOCK__MMSCH,</div><div class='ctx'> 	TA_NUM_BLOCK_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -113,6 +119,14 @@ enum ta_ras_address_type {</div><div class='ctx'> 	TA_RAS_PA_TO_MCA,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum ta_ras_nps_mode {</div><div class='add'>+	TA_RAS_UNKNOWN_MODE = 0,</div><div class='add'>+	TA_RAS_NPS1_MODE = 1,</div><div class='add'>+	TA_RAS_NPS2_MODE = 2,</div><div class='add'>+	TA_RAS_NPS4_MODE = 4,</div><div class='add'>+	TA_RAS_NPS8_MODE = 8,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Input/output structures for RAS commands */</div><div class='ctx'> /**********************************************************/</div><div class='ctx'> </div><div class='hunk'>@@ -139,6 +153,8 @@ struct ta_ras_init_flags {</div><div class='ctx'> 	uint8_t dgpu_mode;</div><div class='ctx'> 	uint16_t xcc_mask;</div><div class='ctx'> 	uint8_t channel_dis_num;</div><div class='add'>+	uint8_t nps_mode;</div><div class='add'>+	uint32_t active_umc_mask;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ta_ras_mca_addr {</div><div class='hunk'>@@ -146,6 +162,7 @@ struct ta_ras_mca_addr {</div><div class='ctx'> 	uint32_t ch_inst;</div><div class='ctx'> 	uint32_t umc_inst;</div><div class='ctx'> 	uint32_t node_inst;</div><div class='add'>+	uint32_t socket_id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ta_ras_phy_addr {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h b/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h<br/>index 00d8bdb8254f..9ec2e03d41c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h</a></div><div class='hunk'>@@ -31,10 +31,12 @@</div><div class='ctx'>  *    Secure Display Command ID</div><div class='ctx'>  */</div><div class='ctx'> enum ta_securedisplay_command {</div><div class='del'>-	/* Query whether TA is responding used only for validation purpose */</div><div class='add'>+	/* Query whether TA is responding. It is used only for validation purpose */</div><div class='ctx'> 	TA_SECUREDISPLAY_COMMAND__QUERY_TA              = 1,</div><div class='ctx'> 	/* Send region of Interest and CRC value to I2C */</div><div class='ctx'> 	TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC          = 2,</div><div class='add'>+	/* V2 to send multiple regions of Interest and CRC value to I2C */</div><div class='add'>+	TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2       = 3,</div><div class='ctx'> 	/* Maximum Command ID */</div><div class='ctx'> 	TA_SECUREDISPLAY_COMMAND__MAX_ID                = 0x7FFFFFFF,</div><div class='ctx'> };</div><div class='hunk'>@@ -83,6 +85,8 @@ enum ta_securedisplay_ta_query_cmd_ret {</div><div class='ctx'> enum ta_securedisplay_buffer_size {</div><div class='ctx'> 	/* 15 bytes = 8 byte (ROI) + 6 byte(CRC) + 1 byte(phy_id) */</div><div class='ctx'> 	TA_SECUREDISPLAY_I2C_BUFFER_SIZE                = 15,</div><div class='add'>+	/* 16 bytes = 8 byte (ROI) + 6 byte(CRC) + 1 byte(phy_id) + 1 byte(roi_idx) */</div><div class='add'>+	TA_SECUREDISPLAY_V2_I2C_BUFFER_SIZE             = 16,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /** Input/output structures for Secure Display commands */</div><div class='hunk'>@@ -95,7 +99,15 @@ enum ta_securedisplay_buffer_size {</div><div class='ctx'>  *    Physical ID to determine which DIO scratch register should be used to get ROI</div><div class='ctx'>  */</div><div class='ctx'> struct ta_securedisplay_send_roi_crc_input {</div><div class='del'>-	uint32_t  phy_id;  /* Physical ID */</div><div class='add'>+	/* Physical ID */</div><div class='add'>+	uint32_t  phy_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ta_securedisplay_send_roi_crc_v2_input {</div><div class='add'>+	/* Physical ID */</div><div class='add'>+	uint32_t phy_id;</div><div class='add'>+	/* Region of interest index */</div><div class='add'>+	uint8_t  roi_idx;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /** @union ta_securedisplay_cmd_input</div><div class='hunk'>@@ -104,6 +116,8 @@ struct ta_securedisplay_send_roi_crc_input {</div><div class='ctx'> union ta_securedisplay_cmd_input {</div><div class='ctx'> 	/* send ROI and CRC input buffer format */</div><div class='ctx'> 	struct ta_securedisplay_send_roi_crc_input        send_roi_crc;</div><div class='add'>+	/* send ROI and CRC input buffer format, v2 adds a ROI index */</div><div class='add'>+	struct ta_securedisplay_send_roi_crc_v2_input     send_roi_crc_v2;</div><div class='ctx'> 	uint32_t                                          reserved[4];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -128,6 +142,10 @@ struct ta_securedisplay_send_roi_crc_output {</div><div class='ctx'> 	uint8_t  reserved;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct ta_securedisplay_send_roi_crc_v2_output {</div><div class='add'>+	uint8_t  i2c_buf[TA_SECUREDISPLAY_V2_I2C_BUFFER_SIZE];  /* I2C buffer */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /** @union ta_securedisplay_cmd_output</div><div class='ctx'>  *    Output buffer</div><div class='ctx'>  */</div><div class='hunk'>@@ -136,6 +154,8 @@ union ta_securedisplay_cmd_output {</div><div class='ctx'> 	struct ta_securedisplay_query_ta_output            query_ta;</div><div class='ctx'> 	/* Send ROI CRC output buffer format used only for validation purpose */</div><div class='ctx'> 	struct ta_securedisplay_send_roi_crc_output        send_roi_crc;</div><div class='add'>+	/* Send ROI CRC output buffer format used only for validation purpose */</div><div class='add'>+	struct ta_securedisplay_send_roi_crc_v2_output     send_roi_crc_v2;</div><div class='ctx'> 	uint32_t                                           reserved[4];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c<br/>index 450b6e831509..ee8038df17e3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/tonga_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/tonga_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/tonga_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/tonga_ih.c</a></div><div class='hunk'>@@ -159,6 +159,9 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* enable interrupts */</div><div class='ctx'> 	tonga_ih_enable_interrupts(adev);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;irq.ih_soft.ring_size)</div><div class='add'>+		adev-&gt;irq.ih_soft.enabled = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -196,6 +199,9 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	wptr = le32_to_cpu(*ih-&gt;wptr_cpu);</div><div class='ctx'> </div><div class='add'>+	if (ih == &amp;adev-&gt;irq.ih_soft)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -283,9 +289,9 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_early_init(void *handle)</div><div class='add'>+static int tonga_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_irq_add_domain(adev);</div><div class='hunk'>@@ -297,15 +303,19 @@ static int tonga_ih_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_sw_init(void *handle)</div><div class='add'>+static int tonga_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih, 64 * 1024, true);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih_soft, IH_SW_RING_SIZE, true);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;irq.ih.use_doorbell = true;</div><div class='ctx'> 	adev-&gt;irq.ih.doorbell_index = adev-&gt;doorbell_index.ih;</div><div class='ctx'> </div><div class='hunk'>@@ -314,9 +324,9 @@ static int tonga_ih_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_sw_fini(void *handle)</div><div class='add'>+static int tonga_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> 	amdgpu_irq_remove_domain(adev);</div><div class='hunk'>@@ -324,10 +334,10 @@ static int tonga_ih_sw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_hw_init(void *handle)</div><div class='add'>+static int tonga_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = tonga_ih_irq_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -336,32 +346,26 @@ static int tonga_ih_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_hw_fini(void *handle)</div><div class='add'>+static int tonga_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	tonga_ih_irq_disable(adev);</div><div class='add'>+	tonga_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_suspend(void *handle)</div><div class='add'>+static int tonga_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return tonga_ih_hw_fini(adev);</div><div class='add'>+	return tonga_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_resume(void *handle)</div><div class='add'>+static int tonga_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return tonga_ih_hw_init(adev);</div><div class='add'>+	return tonga_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool tonga_ih_is_idle(void *handle)</div><div class='add'>+static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))</div><div class='hunk'>@@ -370,11 +374,11 @@ static bool tonga_ih_is_idle(void *handle)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_wait_for_idle(void *handle)</div><div class='add'>+static int tonga_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		/* read MC_STATUS */</div><div class='hunk'>@@ -386,9 +390,9 @@ static int tonga_ih_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool tonga_ih_check_soft_reset(void *handle)</div><div class='add'>+static bool tonga_ih_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='hunk'>@@ -405,29 +409,27 @@ static bool tonga_ih_check_soft_reset(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_pre_soft_reset(void *handle)</div><div class='add'>+static int tonga_ih_pre_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;irq.srbm_soft_reset)</div><div class='add'>+	if (!ip_block-&gt;adev-&gt;irq.srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return tonga_ih_hw_fini(adev);</div><div class='add'>+	return tonga_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_post_soft_reset(void *handle)</div><div class='add'>+static int tonga_ih_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;irq.srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return tonga_ih_hw_init(adev);</div><div class='add'>+	return tonga_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_soft_reset(void *handle)</div><div class='add'>+static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;irq.srbm_soft_reset)</div><div class='hunk'>@@ -456,13 +458,13 @@ static int tonga_ih_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int tonga_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tonga_ih_set_powergating_state(void *handle,</div><div class='add'>+static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -471,7 +473,6 @@ static int tonga_ih_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs tonga_ih_ip_funcs = {</div><div class='ctx'> 	.name = "tonga_ih",</div><div class='ctx'> 	.early_init = tonga_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = tonga_ih_sw_init,</div><div class='ctx'> 	.sw_fini = tonga_ih_sw_fini,</div><div class='ctx'> 	.hw_init = tonga_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c<br/>index 77af4e25ff46..0f5b1719fda5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.c</a></div><div class='hunk'>@@ -28,27 +28,8 @@</div><div class='ctx'> #include "umc/umc_12_0_0_sh_mask.h"</div><div class='ctx'> #include "mp/mp_13_0_6_sh_mask.h"</div><div class='ctx'> </div><div class='del'>-const uint32_t</div><div class='del'>-	umc_v12_0_channel_idx_tbl[]</div><div class='del'>-			[UMC_V12_0_UMC_INSTANCE_NUM]</div><div class='del'>-			[UMC_V12_0_CHANNEL_INSTANCE_NUM] = {</div><div class='del'>-		{{3,   7,   11,  15,  2,   6,   10,  14},  {1,   5,   9,   13,  0,   4,   8,   12},</div><div class='del'>-		 {19,  23,  27,  31,  18,  22,  26,  30},  {17,  21,  25,  29,  16,  20,  24,  28}},</div><div class='del'>-		{{47,  43,  39,  35,  46,  42,  38,  34},  {45,  41,  37,  33,  44,  40,  36,  32},</div><div class='del'>-		 {63,  59,  55,  51,  62,  58,  54,  50},  {61,  57,  53,  49,  60,  56,  52,  48}},</div><div class='del'>-		{{79,  75,  71,  67,  78,  74,  70,  66},  {77,  73,  69,  65,  76,  72,  68,  64},</div><div class='del'>-		 {95,  91,  87,  83,  94,  90,  86,  82},  {93,  89,  85,  81,  92,  88,  84,  80}},</div><div class='del'>-		{{99,  103, 107, 111, 98,  102, 106, 110}, {97,  101, 105, 109, 96,  100, 104, 108},</div><div class='del'>-		 {115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 112, 116, 120, 124}}</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-/* mapping of MCA error address to normalized address */</div><div class='del'>-static const uint32_t umc_v12_0_ma2na_mapping[] = {</div><div class='del'>-	0,  5,  6,  8,  9,  14, 12, 13,</div><div class='del'>-	10, 11, 15, 16, 17, 18, 19, 20,</div><div class='del'>-	21, 22, 23, 24, 25, 26, 27, 28,</div><div class='del'>-	24, 7,  29, 30,</div><div class='del'>-};</div><div class='add'>+#define MAX_ECC_NUM_PER_RETIREMENT  32</div><div class='add'>+#define DELAYED_TIME_FOR_GPU_RESET  1000  //ms</div><div class='ctx'> </div><div class='ctx'> static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev,</div><div class='ctx'> 					    uint32_t node_inst,</div><div class='hunk'>@@ -91,7 +72,7 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status)</div><div class='ctx'> {</div><div class='del'>-	dev_info(adev-&gt;dev,</div><div class='add'>+	dev_dbg(adev-&gt;dev,</div><div class='ctx'> 		"MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n",</div><div class='ctx'> 		mc_umc_status,</div><div class='ctx'> 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val),</div><div class='hunk'>@@ -104,7 +85,8 @@ bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_sta</div><div class='ctx'> </div><div class='ctx'> 	return (amdgpu_ras_is_poison_mode_supported(adev) &amp;&amp;</div><div class='ctx'> 		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &amp;&amp;</div><div class='del'>-		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1));</div><div class='add'>+		((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) ||</div><div class='add'>+		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)</div><div class='hunk'>@@ -176,9 +158,9 @@ static int umc_v12_0_query_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 	umc_v12_0_query_error_count_per_type(adev, umc_reg_offset,</div><div class='ctx'> 					    &amp;de_count, umc_v12_0_is_deferred_error);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='del'>-	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, ce_count);</div><div class='del'>-	amdgpu_ras_error_statistic_de_count(err_data, &amp;mcm_info, NULL, de_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, ce_count);</div><div class='add'>+	amdgpu_ras_error_statistic_de_count(err_data, &amp;mcm_info, de_count);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -192,143 +174,164 @@ static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 	umc_v12_0_reset_error_count(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool umc_v12_0_bit_wise_xor(uint32_t val)</div><div class='add'>+static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	bool result = 0;</div><div class='del'>-	int i;</div><div class='add'>+	enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE;</div><div class='add'>+	uint32_t vram_type = adev-&gt;gmc.vram_type;</div><div class='add'>+	struct amdgpu_umc_flip_bits *flip_bits = &amp;(adev-&gt;umc.flip_bits);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode)</div><div class='add'>+		nps = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='add'>+</div><div class='add'>+	/* default setting */</div><div class='add'>+	flip_bits-&gt;flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT;</div><div class='add'>+	flip_bits-&gt;flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;</div><div class='add'>+	flip_bits-&gt;flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;</div><div class='add'>+	flip_bits-&gt;flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;</div><div class='add'>+	flip_bits-&gt;flip_row_bit = 13;</div><div class='add'>+	flip_bits-&gt;bit_num = 4;</div><div class='add'>+	flip_bits-&gt;r13_in_pa = UMC_V12_0_PA_R13_BIT;</div><div class='add'>+</div><div class='add'>+	if (nps == AMDGPU_NPS2_PARTITION_MODE) {</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;</div><div class='add'>+		flip_bits-&gt;r13_in_pa = UMC_V12_0_PA_R12_BIT;</div><div class='add'>+	} else if (nps == AMDGPU_NPS4_PARTITION_MODE) {</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;</div><div class='add'>+		flip_bits-&gt;r13_in_pa = UMC_V12_0_PA_R11_BIT;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; 32; i++)</div><div class='del'>-		result = result ^ ((val &gt;&gt; i) &amp; 0x1);</div><div class='add'>+	switch (vram_type) {</div><div class='add'>+	case AMDGPU_VRAM_TYPE_HBM:</div><div class='add'>+		/* other nps modes are taken as nps1 */</div><div class='add'>+		if (nps == AMDGPU_NPS2_PARTITION_MODE)</div><div class='add'>+			flip_bits-&gt;flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;</div><div class='add'>+		else if (nps == AMDGPU_NPS4_PARTITION_MODE)</div><div class='add'>+			flip_bits-&gt;flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;</div><div class='ctx'> </div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_VRAM_TYPE_HBM3E:</div><div class='add'>+		flip_bits-&gt;flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;</div><div class='add'>+		flip_bits-&gt;flip_row_bit = 12;</div><div class='ctx'> </div><div class='del'>-static void umc_v12_0_mca_addr_to_pa(struct amdgpu_device *adev,</div><div class='del'>-					uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst,</div><div class='del'>-					uint32_t node_inst,</div><div class='del'>-					struct ta_ras_query_address_output *addr_out)</div><div class='del'>-{</div><div class='del'>-	uint32_t channel_index, i;</div><div class='del'>-	uint64_t na, soc_pa;</div><div class='del'>-	uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row;</div><div class='del'>-	uint32_t bank0, bank1, bank2, bank3, bank;</div><div class='del'>-</div><div class='del'>-	bank_hash0 = (err_addr &gt;&gt; UMC_V12_0_MCA_B0_BIT) &amp; 0x1ULL;</div><div class='del'>-	bank_hash1 = (err_addr &gt;&gt; UMC_V12_0_MCA_B1_BIT) &amp; 0x1ULL;</div><div class='del'>-	bank_hash2 = (err_addr &gt;&gt; UMC_V12_0_MCA_B2_BIT) &amp; 0x1ULL;</div><div class='del'>-	bank_hash3 = (err_addr &gt;&gt; UMC_V12_0_MCA_B3_BIT) &amp; 0x1ULL;</div><div class='del'>-	col = (err_addr &gt;&gt; 1) &amp; 0x1fULL;</div><div class='del'>-	row = (err_addr &gt;&gt; 10) &amp; 0x3fffULL;</div><div class='del'>-</div><div class='del'>-	/* apply bank hash algorithm */</div><div class='del'>-	bank0 =</div><div class='del'>-		bank_hash0 ^ (UMC_V12_0_XOR_EN0 &amp;</div><div class='del'>-		(umc_v12_0_bit_wise_xor(col &amp; UMC_V12_0_COL_XOR0) ^</div><div class='del'>-		(umc_v12_0_bit_wise_xor(row &amp; UMC_V12_0_ROW_XOR0))));</div><div class='del'>-	bank1 =</div><div class='del'>-		bank_hash1 ^ (UMC_V12_0_XOR_EN1 &amp;</div><div class='del'>-		(umc_v12_0_bit_wise_xor(col &amp; UMC_V12_0_COL_XOR1) ^</div><div class='del'>-		(umc_v12_0_bit_wise_xor(row &amp; UMC_V12_0_ROW_XOR1))));</div><div class='del'>-	bank2 =</div><div class='del'>-		bank_hash2 ^ (UMC_V12_0_XOR_EN2 &amp;</div><div class='del'>-		(umc_v12_0_bit_wise_xor(col &amp; UMC_V12_0_COL_XOR2) ^</div><div class='del'>-		(umc_v12_0_bit_wise_xor(row &amp; UMC_V12_0_ROW_XOR2))));</div><div class='del'>-	bank3 =</div><div class='del'>-		bank_hash3 ^ (UMC_V12_0_XOR_EN3 &amp;</div><div class='del'>-		(umc_v12_0_bit_wise_xor(col &amp; UMC_V12_0_COL_XOR3) ^</div><div class='del'>-		(umc_v12_0_bit_wise_xor(row &amp; UMC_V12_0_ROW_XOR3))));</div><div class='del'>-</div><div class='del'>-	bank = bank0 | (bank1 &lt;&lt; 1) | (bank2 &lt;&lt; 2) | (bank3 &lt;&lt; 3);</div><div class='del'>-	err_addr &amp;= ~0x3c0ULL;</div><div class='del'>-	err_addr |= (bank &lt;&lt; UMC_V12_0_MCA_B0_BIT);</div><div class='del'>-</div><div class='del'>-	na = 0x0;</div><div class='del'>-	/* convert mca error address to normalized address */</div><div class='del'>-	for (i = 1; i &lt; ARRAY_SIZE(umc_v12_0_ma2na_mapping); i++)</div><div class='del'>-		na |= ((err_addr &gt;&gt; i) &amp; 0x1ULL) &lt;&lt; umc_v12_0_ma2na_mapping[i];</div><div class='del'>-</div><div class='del'>-	channel_index =</div><div class='del'>-		adev-&gt;umc.channel_idx_tbl[node_inst * adev-&gt;umc.umc_inst_num *</div><div class='del'>-			adev-&gt;umc.channel_inst_num +</div><div class='del'>-			umc_inst * adev-&gt;umc.channel_inst_num +</div><div class='del'>-			ch_inst];</div><div class='del'>-	/* translate umc channel address to soc pa, 3 parts are included */</div><div class='del'>-	soc_pa = ADDR_OF_32KB_BLOCK(na) |</div><div class='del'>-		ADDR_OF_256B_BLOCK(channel_index) |</div><div class='del'>-		OFFSET_IN_256B_BLOCK(na);</div><div class='del'>-</div><div class='del'>-	/* the umc channel bits are not original values, they are hashed */</div><div class='del'>-	UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa);</div><div class='del'>-</div><div class='del'>-	addr_out-&gt;pa.pa = soc_pa;</div><div class='del'>-	addr_out-&gt;pa.bank = bank;</div><div class='del'>-	addr_out-&gt;pa.channel_idx = channel_index;</div><div class='add'>+		if (nps == AMDGPU_NPS2_PARTITION_MODE)</div><div class='add'>+			flip_bits-&gt;flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;</div><div class='add'>+		else if (nps == AMDGPU_NPS4_PARTITION_MODE)</div><div class='add'>+			flip_bits-&gt;flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_warn(adev-&gt;dev,</div><div class='add'>+			"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;umc.retire_unit = 0x1 &lt;&lt; flip_bits-&gt;bit_num;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void umc_v12_0_convert_error_address(struct amdgpu_device *adev,</div><div class='del'>-					    struct ras_err_data *err_data, uint64_t err_addr,</div><div class='del'>-					    uint32_t ch_inst, uint32_t umc_inst,</div><div class='del'>-					    uint32_t node_inst)</div><div class='add'>+static int umc_v12_0_convert_error_address(struct amdgpu_device *adev,</div><div class='add'>+					struct ras_err_data *err_data,</div><div class='add'>+					struct ta_ras_query_address_input *addr_in,</div><div class='add'>+					struct ta_ras_query_address_output *addr_out,</div><div class='add'>+					bool dump_addr)</div><div class='ctx'> {</div><div class='del'>-	uint32_t col, row, row_xor, bank, channel_index;</div><div class='del'>-	uint64_t soc_pa, retired_page, column;</div><div class='del'>-	struct ta_ras_query_address_input addr_in;</div><div class='del'>-	struct ta_ras_query_address_output addr_out;</div><div class='add'>+	uint32_t col, col_lower, row, row_lower, row_high, bank;</div><div class='add'>+	uint32_t channel_index = 0, umc_inst = 0;</div><div class='add'>+	uint32_t i, bit_num, retire_unit, *flip_bits;</div><div class='add'>+	uint64_t soc_pa, column, err_addr;</div><div class='add'>+	struct ta_ras_query_address_output addr_out_tmp;</div><div class='add'>+	struct ta_ras_query_address_output *paddr_out;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!addr_out)</div><div class='add'>+		paddr_out = &amp;addr_out_tmp;</div><div class='add'>+	else</div><div class='add'>+		paddr_out = addr_out;</div><div class='add'>+</div><div class='add'>+	err_addr = bank = 0;</div><div class='add'>+	if (addr_in) {</div><div class='add'>+		err_addr = addr_in-&gt;ma.err_addr;</div><div class='add'>+		addr_in-&gt;addr_type = TA_RAS_MCA_TO_PA;</div><div class='add'>+		ret = psp_ras_query_address(&amp;adev-&gt;psp, addr_in, paddr_out);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_warn(adev-&gt;dev, "Failed to query RAS physical address for 0x%llx",</div><div class='add'>+				err_addr);</div><div class='add'>+</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		bank = paddr_out-&gt;pa.bank;</div><div class='add'>+		/* no need to care about umc inst if addr_in is NULL */</div><div class='add'>+		umc_inst = addr_in-&gt;ma.umc_inst;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	addr_in.addr_type = TA_RAS_MCA_TO_PA;</div><div class='del'>-	addr_in.ma.err_addr = err_addr;</div><div class='del'>-	addr_in.ma.ch_inst = ch_inst;</div><div class='del'>-	addr_in.ma.umc_inst = umc_inst;</div><div class='del'>-	addr_in.ma.node_inst = node_inst;</div><div class='del'>-</div><div class='del'>-	if (psp_ras_query_address(&amp;adev-&gt;psp, &amp;addr_in, &amp;addr_out))</div><div class='del'>-		/* fallback to old path if fail to get pa from psp */</div><div class='del'>-		umc_v12_0_mca_addr_to_pa(adev, err_addr, ch_inst, umc_inst,</div><div class='del'>-				node_inst, &amp;addr_out);</div><div class='del'>-</div><div class='del'>-	soc_pa = addr_out.pa.pa;</div><div class='del'>-	bank = addr_out.pa.bank;</div><div class='del'>-	channel_index = addr_out.pa.channel_idx;</div><div class='del'>-</div><div class='del'>-	col = (err_addr &gt;&gt; 1) &amp; 0x1fULL;</div><div class='del'>-	row = (err_addr &gt;&gt; 10) &amp; 0x3fffULL;</div><div class='del'>-	row_xor = row ^ (0x1ULL &lt;&lt; 13);</div><div class='del'>-	/* clear [C3 C2] in soc physical address */</div><div class='del'>-	soc_pa &amp;= ~(0x3ULL &lt;&lt; UMC_V12_0_PA_C2_BIT);</div><div class='del'>-	/* clear [C4] in soc physical address */</div><div class='del'>-	soc_pa &amp;= ~(0x1ULL &lt;&lt; UMC_V12_0_PA_C4_BIT);</div><div class='del'>-</div><div class='del'>-	/* loop for all possibilities of [C4 C3 C2] */</div><div class='del'>-	for (column = 0; column &lt; UMC_V12_0_NA_MAP_PA_NUM; column++) {</div><div class='del'>-		retired_page = soc_pa | ((column &amp; 0x3) &lt;&lt; UMC_V12_0_PA_C2_BIT);</div><div class='del'>-		retired_page |= (((column &amp; 0x4) &gt;&gt; 2) &lt;&lt; UMC_V12_0_PA_C4_BIT);</div><div class='del'>-		/* include column bit 0 and 1 */</div><div class='del'>-		col &amp;= 0x3;</div><div class='del'>-		col |= (column &lt;&lt; 2);</div><div class='del'>-		dev_info(adev-&gt;dev,</div><div class='del'>-			"Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n",</div><div class='del'>-			retired_page, row, col, bank, channel_index);</div><div class='del'>-		amdgpu_umc_fill_error_record(err_data, err_addr,</div><div class='del'>-			retired_page, channel_index, umc_inst);</div><div class='del'>-</div><div class='del'>-		/* shift R13 bit */</div><div class='del'>-		retired_page ^= (0x1ULL &lt;&lt; UMC_V12_0_PA_R13_BIT);</div><div class='del'>-		dev_info(adev-&gt;dev,</div><div class='del'>-			"Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n",</div><div class='del'>-			retired_page, row_xor, col, bank, channel_index);</div><div class='del'>-		amdgpu_umc_fill_error_record(err_data, err_addr,</div><div class='del'>-			retired_page, channel_index, umc_inst);</div><div class='add'>+	flip_bits = adev-&gt;umc.flip_bits.flip_bits_in_pa;</div><div class='add'>+	bit_num = adev-&gt;umc.flip_bits.bit_num;</div><div class='add'>+	retire_unit = adev-&gt;umc.retire_unit;</div><div class='add'>+</div><div class='add'>+	soc_pa = paddr_out-&gt;pa.pa;</div><div class='add'>+	channel_index = paddr_out-&gt;pa.channel_idx;</div><div class='add'>+	/* clear loop bits in soc physical address */</div><div class='add'>+	for (i = 0; i &lt; bit_num; i++)</div><div class='add'>+		soc_pa &amp;= ~BIT_ULL(flip_bits[i]);</div><div class='add'>+</div><div class='add'>+	paddr_out-&gt;pa.pa = soc_pa;</div><div class='add'>+	/* get column bit 0 and 1 in mca address */</div><div class='add'>+	col_lower = (err_addr &gt;&gt; 1) &amp; 0x3ULL;</div><div class='add'>+	/* extra row bit will be handled later */</div><div class='add'>+	row_lower = (err_addr &gt;&gt; UMC_V12_0_MA_R0_BIT) &amp; 0x1fffULL;</div><div class='add'>+	row_lower &amp;= ~BIT_ULL(adev-&gt;umc.flip_bits.flip_row_bit);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(9, 5, 0)) {</div><div class='add'>+		row_high = (soc_pa &gt;&gt; adev-&gt;umc.flip_bits.r13_in_pa) &amp; 0x3ULL;</div><div class='add'>+		/* it's 2.25GB in each channel, from MCA address to PA</div><div class='add'>+		 * [R14 R13] is converted if the two bits value are 0x3,</div><div class='add'>+		 * get them from PA instead of MCA address.</div><div class='add'>+		 */</div><div class='add'>+		row_lower |= (row_high &lt;&lt; 13);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (!err_data &amp;&amp; !dump_addr)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* loop for all possibilities of retired bits */</div><div class='add'>+	for (column = 0; column &lt; retire_unit; column++) {</div><div class='add'>+		soc_pa = paddr_out-&gt;pa.pa;</div><div class='add'>+		for (i = 0; i &lt; bit_num; i++)</div><div class='add'>+			soc_pa |= (((column &gt;&gt; i) &amp; 0x1ULL) &lt;&lt; flip_bits[i]);</div><div class='add'>+</div><div class='add'>+		col = ((column &amp; 0x7) &lt;&lt; 2) | col_lower;</div><div class='add'>+		/* handle extra row bit */</div><div class='add'>+		if (bit_num == RETIRE_FLIP_BITS_NUM)</div><div class='add'>+			row = ((column &gt;&gt; 3) &lt;&lt; adev-&gt;umc.flip_bits.flip_row_bit) |</div><div class='add'>+					row_lower;</div><div class='add'>+</div><div class='add'>+		if (dump_addr)</div><div class='add'>+			dev_info(adev-&gt;dev,</div><div class='add'>+				"Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n",</div><div class='add'>+				soc_pa, row, col, bank, channel_index);</div><div class='add'>+</div><div class='add'>+		if (err_data)</div><div class='add'>+			amdgpu_umc_fill_error_record(err_data, err_addr,</div><div class='add'>+				soc_pa, channel_index, umc_inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int umc_v12_0_query_error_address(struct amdgpu_device *adev,</div><div class='ctx'> 					uint32_t node_inst, uint32_t umc_inst,</div><div class='ctx'> 					uint32_t ch_inst, void *data)</div><div class='ctx'> {</div><div class='add'>+	struct ras_err_data *err_data = (struct ras_err_data *)data;</div><div class='add'>+	struct ta_ras_query_address_input addr_in;</div><div class='ctx'> 	uint64_t mc_umc_status_addr;</div><div class='ctx'> 	uint64_t mc_umc_status, err_addr;</div><div class='ctx'> 	uint64_t mc_umc_addrt0;</div><div class='del'>-	struct ras_err_data *err_data = (struct ras_err_data *)data;</div><div class='ctx'> 	uint64_t umc_reg_offset =</div><div class='ctx'> 		get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);</div><div class='ctx'> </div><div class='hunk'>@@ -357,8 +360,19 @@ static int umc_v12_0_query_error_address(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);</div><div class='ctx'> </div><div class='del'>-		umc_v12_0_convert_error_address(adev, err_data, err_addr,</div><div class='del'>-					ch_inst, umc_inst, node_inst);</div><div class='add'>+		if (!adev-&gt;aid_mask &amp;&amp;</div><div class='add'>+		    adev-&gt;smuio.funcs &amp;&amp;</div><div class='add'>+		    adev-&gt;smuio.funcs-&gt;get_socket_id)</div><div class='add'>+			addr_in.ma.socket_id = adev-&gt;smuio.funcs-&gt;get_socket_id(adev);</div><div class='add'>+		else</div><div class='add'>+			addr_in.ma.socket_id = 0;</div><div class='add'>+</div><div class='add'>+		addr_in.ma.err_addr = err_addr;</div><div class='add'>+		addr_in.ma.ch_inst = ch_inst;</div><div class='add'>+		addr_in.ma.umc_inst = umc_inst;</div><div class='add'>+		addr_in.ma.node_inst = node_inst;</div><div class='add'>+</div><div class='add'>+		umc_v12_0_convert_error_address(adev, err_data, &amp;addr_in, NULL, true);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* clear umc status */</div><div class='hunk'>@@ -401,64 +415,6 @@ static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void umc_v12_0_ecc_info_query_ras_error_count(struct amdgpu_device *adev,</div><div class='del'>-					void *ras_error_status)</div><div class='del'>-{</div><div class='del'>-	amdgpu_mca_smu_log_ras_error(adev,</div><div class='del'>-		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_CE, ras_error_status);</div><div class='del'>-	amdgpu_mca_smu_log_ras_error(adev,</div><div class='del'>-		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_UE, ras_error_status);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void umc_v12_0_ecc_info_query_ras_error_address(struct amdgpu_device *adev,</div><div class='del'>-					void *ras_error_status)</div><div class='del'>-{</div><div class='del'>-	struct ras_err_node *err_node;</div><div class='del'>-	uint64_t mc_umc_status;</div><div class='del'>-	struct ras_err_info *err_info;</div><div class='del'>-	struct ras_err_addr *mca_err_addr, *tmp;</div><div class='del'>-	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;</div><div class='del'>-</div><div class='del'>-	for_each_ras_error(err_node, err_data) {</div><div class='del'>-		err_info = &amp;err_node-&gt;err_info;</div><div class='del'>-		if (list_empty(&amp;err_info-&gt;err_addr_list))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		list_for_each_entry_safe(mca_err_addr, tmp, &amp;err_info-&gt;err_addr_list, node) {</div><div class='del'>-			mc_umc_status = mca_err_addr-&gt;err_status;</div><div class='del'>-			if (mc_umc_status &amp;&amp;</div><div class='del'>-				(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) ||</div><div class='del'>-				 umc_v12_0_is_deferred_error(adev, mc_umc_status))) {</div><div class='del'>-				uint64_t mca_addr, err_addr, mca_ipid;</div><div class='del'>-				uint32_t InstanceIdLo;</div><div class='del'>-</div><div class='del'>-				mca_addr = mca_err_addr-&gt;err_addr;</div><div class='del'>-				mca_ipid = mca_err_addr-&gt;err_ipid;</div><div class='del'>-</div><div class='del'>-				err_addr = REG_GET_FIELD(mca_addr,</div><div class='del'>-							MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);</div><div class='del'>-				InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo);</div><div class='del'>-</div><div class='del'>-				dev_info(adev-&gt;dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n",</div><div class='del'>-					mca_ipid,</div><div class='del'>-					err_info-&gt;mcm_info.die_id,</div><div class='del'>-					MCA_IPID_LO_2_UMC_INST(InstanceIdLo),</div><div class='del'>-					MCA_IPID_LO_2_UMC_CH(InstanceIdLo),</div><div class='del'>-					err_addr);</div><div class='del'>-</div><div class='del'>-				umc_v12_0_convert_error_address(adev,</div><div class='del'>-					err_data, err_addr,</div><div class='del'>-					MCA_IPID_LO_2_UMC_CH(InstanceIdLo),</div><div class='del'>-					MCA_IPID_LO_2_UMC_INST(InstanceIdLo),</div><div class='del'>-					err_info-&gt;mcm_info.die_id);</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			/* Delete error address node from list and free memory */</div><div class='del'>-			amdgpu_ras_del_mca_err_addr(err_info, mca_err_addr);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev,</div><div class='ctx'> 			enum amdgpu_mca_error_type type, void *ras_error_status)</div><div class='ctx'> {</div><div class='hunk'>@@ -498,43 +454,54 @@ const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = {</div><div class='ctx'> 	.query_ras_error_address = umc_v12_0_query_ras_error_address,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int umc_v12_0_aca_bank_generate_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,</div><div class='del'>-					      struct aca_bank_report *report, void *data)</div><div class='add'>+static int umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				     enum aca_smu_type type, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = handle-&gt;adev;</div><div class='del'>-	u64 status;</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	enum aca_error_type err_type;</div><div class='add'>+	u64 status, count;</div><div class='add'>+	u32 ext_error_code;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = aca_bank_info_decode(bank, &amp;report-&gt;info);</div><div class='add'>+	status = bank-&gt;regs[ACA_REG_IDX_STATUS];</div><div class='add'>+	if (umc_v12_0_is_deferred_error(adev, status))</div><div class='add'>+		err_type = ACA_ERROR_TYPE_DEFERRED;</div><div class='add'>+	else if (umc_v12_0_is_uncorrectable_error(adev, status))</div><div class='add'>+		err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+	else if (umc_v12_0_is_correctable_error(adev, status))</div><div class='add'>+		err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+	bank-&gt;aca_err_type = err_type;</div><div class='add'>+</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	status = bank-&gt;regs[ACA_REG_IDX_STATUS];</div><div class='del'>-	switch (type) {</div><div class='del'>-	case ACA_ERROR_TYPE_UE:</div><div class='del'>-		if (umc_v12_0_is_uncorrectable_error(adev, status)) {</div><div class='del'>-			report-&gt;count[type] = 1;</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case ACA_ERROR_TYPE_CE:</div><div class='del'>-		if (umc_v12_0_is_correctable_error(adev, status)) {</div><div class='del'>-			report-&gt;count[type] = 1;</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='add'>+	amdgpu_umc_update_ecc_status(adev,</div><div class='add'>+		bank-&gt;regs[ACA_REG_IDX_STATUS],</div><div class='add'>+		bank-&gt;regs[ACA_REG_IDX_IPID],</div><div class='add'>+		bank-&gt;regs[ACA_REG_IDX_ADDR]);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status);</div><div class='add'>+	if (umc_v12_0_is_deferred_error(adev, status))</div><div class='add'>+		count = ext_error_code == 0 ?</div><div class='add'>+			adev-&gt;umc.err_addr_cnt / adev-&gt;umc.retire_unit : 1ULL;</div><div class='add'>+	else</div><div class='add'>+		count = ext_error_code == 0 ?</div><div class='add'>+			ACA_REG__MISC0__ERRCNT(bank-&gt;regs[ACA_REG_IDX_MISC0]) : 1ULL;</div><div class='add'>+</div><div class='add'>+	return aca_error_cache_log_bank_error(handle, &amp;info, err_type, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct aca_bank_ops umc_v12_0_aca_bank_ops = {</div><div class='del'>-	.aca_bank_generate_report = umc_v12_0_aca_bank_generate_report,</div><div class='add'>+	.aca_bank_parser = umc_v12_0_aca_bank_parser,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct aca_info umc_v12_0_aca_info = {</div><div class='ctx'> 	.hwip = ACA_HWIP_TYPE_UMC,</div><div class='del'>-	.mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,</div><div class='add'>+	.mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK | ACA_ERROR_DEFERRED_MASK,</div><div class='ctx'> 	.bank_ops = &amp;umc_v12_0_aca_bank_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -554,6 +521,209 @@ static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev,</div><div class='add'>+			uint64_t status, uint64_t ipid, uint64_t addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	uint16_t hwid, mcatype;</div><div class='add'>+	uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL];</div><div class='add'>+	uint64_t err_addr, pa_addr = 0;</div><div class='add'>+	struct ras_ecc_err *ecc_err;</div><div class='add'>+	struct ta_ras_query_address_output addr_out;</div><div class='add'>+	uint32_t shift_bit = adev-&gt;umc.flip_bits.flip_bits_in_pa[2];</div><div class='add'>+	int count, ret, i;</div><div class='add'>+</div><div class='add'>+	hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);</div><div class='add'>+	mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);</div><div class='add'>+</div><div class='add'>+	/* The IP block decode of consumption is SMU */</div><div class='add'>+	if (hwid != MCA_UMC_HWID_V12_0 || mcatype != MCA_UMC_MCATYPE_V12_0) {</div><div class='add'>+		con-&gt;umc_ecc_log.consumption_q_count++;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!status)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!umc_v12_0_is_deferred_error(adev, status))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err_addr = REG_GET_FIELD(addr,</div><div class='add'>+				MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);</div><div class='add'>+</div><div class='add'>+	dev_dbg(adev-&gt;dev,</div><div class='add'>+		"UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, err_addr:0x%llx\n",</div><div class='add'>+		ipid,</div><div class='add'>+		MCA_IPID_2_SOCKET_ID(ipid),</div><div class='add'>+		MCA_IPID_2_DIE_ID(ipid),</div><div class='add'>+		MCA_IPID_2_UMC_INST(ipid),</div><div class='add'>+		MCA_IPID_2_UMC_CH(ipid),</div><div class='add'>+		err_addr);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_umc_mca_to_addr(adev,</div><div class='add'>+			err_addr, MCA_IPID_2_UMC_CH(ipid),</div><div class='add'>+			MCA_IPID_2_UMC_INST(ipid), MCA_IPID_2_DIE_ID(ipid),</div><div class='add'>+			MCA_IPID_2_SOCKET_ID(ipid), &amp;addr_out, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ecc_err = kzalloc(sizeof(*ecc_err), GFP_KERNEL);</div><div class='add'>+	if (!ecc_err)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	pa_addr = addr_out.pa.pa;</div><div class='add'>+	ecc_err-&gt;status = status;</div><div class='add'>+	ecc_err-&gt;ipid = ipid;</div><div class='add'>+	ecc_err-&gt;addr = addr;</div><div class='add'>+	ecc_err-&gt;pa_pfn = pa_addr &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+	ecc_err-&gt;channel_idx = addr_out.pa.channel_idx;</div><div class='add'>+</div><div class='add'>+	/* If converted pa_pfn is 0, use pa C4 pfn. */</div><div class='add'>+	if (!ecc_err-&gt;pa_pfn)</div><div class='add'>+		ecc_err-&gt;pa_pfn = BIT_ULL(shift_bit) &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_umc_logs_ecc_err(adev, &amp;con-&gt;umc_ecc_log.de_page_tree, ecc_err);</div><div class='add'>+	if (ret) {</div><div class='add'>+		if (ret == -EEXIST)</div><div class='add'>+			con-&gt;umc_ecc_log.de_queried_count++;</div><div class='add'>+		else</div><div class='add'>+			dev_err(adev-&gt;dev, "Fail to log ecc error! ret:%d\n", ret);</div><div class='add'>+</div><div class='add'>+		kfree(ecc_err);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	con-&gt;umc_ecc_log.de_queried_count++;</div><div class='add'>+</div><div class='add'>+	memset(page_pfn, 0, sizeof(page_pfn));</div><div class='add'>+	count = amdgpu_umc_lookup_bad_pages_in_a_row(adev,</div><div class='add'>+				pa_addr,</div><div class='add'>+				page_pfn, ARRAY_SIZE(page_pfn));</div><div class='add'>+	if (count &lt;= 0) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "Fail to convert error address! count:%d\n", count);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Reserve memory */</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		amdgpu_ras_reserve_page(adev, page_pfn[i]);</div><div class='add'>+</div><div class='add'>+	/* The problem case is as follows:</div><div class='add'>+	 * 1. GPU A triggers a gpu ras reset, and GPU A drives</div><div class='add'>+	 *    GPU B to also perform a gpu ras reset.</div><div class='add'>+	 * 2. After gpu B ras reset started, gpu B queried a DE</div><div class='add'>+	 *    data. Since the DE data was queried in the ras reset</div><div class='add'>+	 *    thread instead of the page retirement thread, bad</div><div class='add'>+	 *    page retirement work would not be triggered. Then</div><div class='add'>+	 *    even if all gpu resets are completed, the bad pages</div><div class='add'>+	 *    will be cached in RAM until GPU B's bad page retirement</div><div class='add'>+	 *    work is triggered again and then saved to eeprom.</div><div class='add'>+	 * Trigger delayed work to save the bad pages to eeprom in time</div><div class='add'>+	 * after gpu ras reset is completed.</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_ras_in_recovery(adev))</div><div class='add'>+		schedule_delayed_work(&amp;con-&gt;page_retirement_dwork,</div><div class='add'>+			msecs_to_jiffies(DELAYED_TIME_FOR_GPU_RESET));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int umc_v12_0_fill_error_record(struct amdgpu_device *adev,</div><div class='add'>+				struct ras_ecc_err *ecc_err, void *ras_error_status)</div><div class='add'>+{</div><div class='add'>+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;</div><div class='add'>+	uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL];</div><div class='add'>+	int ret, i, count;</div><div class='add'>+</div><div class='add'>+	if (!err_data || !ecc_err)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	memset(page_pfn, 0, sizeof(page_pfn));</div><div class='add'>+	count = amdgpu_umc_lookup_bad_pages_in_a_row(adev,</div><div class='add'>+				ecc_err-&gt;pa_pfn &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='add'>+				page_pfn, ARRAY_SIZE(page_pfn));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		ret = amdgpu_umc_fill_error_record(err_data,</div><div class='add'>+				ecc_err-&gt;addr,</div><div class='add'>+				page_pfn[i] &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='add'>+				ecc_err-&gt;channel_idx,</div><div class='add'>+				MCA_IPID_2_UMC_INST(ecc_err-&gt;ipid));</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err_data-&gt;de_count++;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v12_0_query_ras_ecc_err_addr(struct amdgpu_device *adev,</div><div class='add'>+					void *ras_error_status)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	struct ras_ecc_err *entries[MAX_ECC_NUM_PER_RETIREMENT];</div><div class='add'>+	struct radix_tree_root *ecc_tree;</div><div class='add'>+	int new_detected, ret, i;</div><div class='add'>+</div><div class='add'>+	ecc_tree = &amp;con-&gt;umc_ecc_log.de_page_tree;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;con-&gt;umc_ecc_log.lock);</div><div class='add'>+	new_detected = radix_tree_gang_lookup_tag(ecc_tree, (void **)entries,</div><div class='add'>+			0, ARRAY_SIZE(entries), UMC_ECC_NEW_DETECTED_TAG);</div><div class='add'>+	for (i = 0; i &lt; new_detected; i++) {</div><div class='add'>+		if (!entries[i])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		ret = umc_v12_0_fill_error_record(adev, entries[i], ras_error_status);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Fail to fill umc error record, ret:%d\n", ret);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		radix_tree_tag_clear(ecc_tree,</div><div class='add'>+				entries[i]-&gt;pa_pfn, UMC_ECC_NEW_DETECTED_TAG);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;con-&gt;umc_ecc_log.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev,</div><div class='add'>+		uint64_t mca_addr, uint64_t retired_page)</div><div class='add'>+{</div><div class='add'>+	uint32_t die = 0;</div><div class='add'>+</div><div class='add'>+	/* we only calculate die id for nps1 mode right now */</div><div class='add'>+	die += ((((retired_page &gt;&gt; 12) &amp; 0x1ULL)^</div><div class='add'>+	    ((retired_page &gt;&gt; 20) &amp; 0x1ULL) ^</div><div class='add'>+	    ((retired_page &gt;&gt; 27) &amp; 0x1ULL) ^</div><div class='add'>+	    ((retired_page &gt;&gt; 34) &amp; 0x1ULL) ^</div><div class='add'>+	    ((retired_page &gt;&gt; 41) &amp; 0x1ULL)) &lt;&lt; 0);</div><div class='add'>+</div><div class='add'>+	/* the original PA_C4 and PA_R13 may be cleared in retired_page, so</div><div class='add'>+	 * get them from mca_addr.</div><div class='add'>+	 */</div><div class='add'>+	die += ((((retired_page &gt;&gt; 13) &amp; 0x1ULL) ^</div><div class='add'>+	    ((mca_addr &gt;&gt; 5) &amp; 0x1ULL) ^</div><div class='add'>+	    ((retired_page &gt;&gt; 28) &amp; 0x1ULL) ^</div><div class='add'>+	    ((mca_addr &gt;&gt; 23) &amp; 0x1ULL) ^</div><div class='add'>+	    ((retired_page &gt;&gt; 42) &amp; 0x1ULL)) &lt;&lt; 1);</div><div class='add'>+	die &amp;= 3;</div><div class='add'>+</div><div class='add'>+	return die;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v12_0_mca_ipid_parse(struct amdgpu_device *adev, uint64_t ipid,</div><div class='add'>+		uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid)</div><div class='add'>+{</div><div class='add'>+	if (did)</div><div class='add'>+		*did = MCA_IPID_2_DIE_ID(ipid);</div><div class='add'>+	if (ch)</div><div class='add'>+		*ch = MCA_IPID_2_UMC_CH(ipid);</div><div class='add'>+	if (umc_inst)</div><div class='add'>+		*umc_inst = MCA_IPID_2_UMC_INST(ipid);</div><div class='add'>+	if (sid)</div><div class='add'>+		*sid = MCA_IPID_2_SOCKET_ID(ipid);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct amdgpu_umc_ras umc_v12_0_ras = {</div><div class='ctx'> 	.ras_block = {</div><div class='ctx'> 		.hw_ops = &amp;umc_v12_0_ras_hw_ops,</div><div class='hunk'>@@ -561,8 +731,12 @@ struct amdgpu_umc_ras umc_v12_0_ras = {</div><div class='ctx'> 	},</div><div class='ctx'> 	.err_cnt_init = umc_v12_0_err_cnt_init,</div><div class='ctx'> 	.query_ras_poison_mode = umc_v12_0_query_ras_poison_mode,</div><div class='del'>-	.ecc_info_query_ras_error_count = umc_v12_0_ecc_info_query_ras_error_count,</div><div class='del'>-	.ecc_info_query_ras_error_address = umc_v12_0_ecc_info_query_ras_error_address,</div><div class='add'>+	.ecc_info_query_ras_error_address = umc_v12_0_query_ras_ecc_err_addr,</div><div class='ctx'> 	.check_ecc_err_status = umc_v12_0_check_ecc_err_status,</div><div class='add'>+	.update_ecc_status = umc_v12_0_update_ecc_status,</div><div class='add'>+	.convert_ras_err_addr = umc_v12_0_convert_error_address,</div><div class='add'>+	.get_die_id_from_pa = umc_v12_0_get_die_id,</div><div class='add'>+	.get_retire_flip_bits = umc_v12_0_get_retire_flip_bits,</div><div class='add'>+	.mca_ipid_parse = umc_v12_0_mca_ipid_parse,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h<br/>index 5973bfb14fce..63b7e7254526 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.h</a></div><div class='hunk'>@@ -55,83 +55,51 @@</div><div class='ctx'> #define UMC_V12_0_NA_MAP_PA_NUM        8</div><div class='ctx'> /* R13 bit shift should be considered, double the number */</div><div class='ctx'> #define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2)</div><div class='del'>-/* bank bits in MCA error address */</div><div class='del'>-#define UMC_V12_0_MCA_B0_BIT 6</div><div class='del'>-#define UMC_V12_0_MCA_B1_BIT 7</div><div class='del'>-#define UMC_V12_0_MCA_B2_BIT 8</div><div class='del'>-#define UMC_V12_0_MCA_B3_BIT 9</div><div class='add'>+</div><div class='ctx'> /* column bits in SOC physical address */</div><div class='ctx'> #define UMC_V12_0_PA_C2_BIT 15</div><div class='add'>+#define UMC_V12_0_PA_C3_BIT 16</div><div class='ctx'> #define UMC_V12_0_PA_C4_BIT 21</div><div class='ctx'> /* row bits in SOC physical address */</div><div class='add'>+#define UMC_V12_0_PA_R0_BIT 22</div><div class='add'>+#define UMC_V12_0_PA_R10_BIT 32</div><div class='add'>+#define UMC_V12_0_PA_R11_BIT 33</div><div class='add'>+#define UMC_V12_0_PA_R12_BIT 34</div><div class='ctx'> #define UMC_V12_0_PA_R13_BIT 35</div><div class='del'>-/* channel index bits in SOC physical address */</div><div class='add'>+/* channel bit in SOC physical address */</div><div class='ctx'> #define UMC_V12_0_PA_CH4_BIT 12</div><div class='ctx'> #define UMC_V12_0_PA_CH5_BIT 13</div><div class='del'>-#define UMC_V12_0_PA_CH6_BIT 14</div><div class='del'>-</div><div class='del'>-/* bank hash settings */</div><div class='del'>-#define UMC_V12_0_XOR_EN0 1</div><div class='del'>-#define UMC_V12_0_XOR_EN1 1</div><div class='del'>-#define UMC_V12_0_XOR_EN2 1</div><div class='del'>-#define UMC_V12_0_XOR_EN3 1</div><div class='del'>-#define UMC_V12_0_COL_XOR0 0x0</div><div class='del'>-#define UMC_V12_0_COL_XOR1 0x0</div><div class='del'>-#define UMC_V12_0_COL_XOR2 0x800</div><div class='del'>-#define UMC_V12_0_COL_XOR3 0x1000</div><div class='del'>-#define UMC_V12_0_ROW_XOR0 0x11111</div><div class='del'>-#define UMC_V12_0_ROW_XOR1 0x22222</div><div class='del'>-#define UMC_V12_0_ROW_XOR2 0x4444</div><div class='del'>-#define UMC_V12_0_ROW_XOR3 0x8888</div><div class='del'>-</div><div class='del'>-/* channel hash settings */</div><div class='del'>-#define UMC_V12_0_HASH_4K 0</div><div class='del'>-#define UMC_V12_0_HASH_64K 1</div><div class='del'>-#define UMC_V12_0_HASH_2M 1</div><div class='del'>-#define UMC_V12_0_HASH_1G 1</div><div class='del'>-#define UMC_V12_0_HASH_1T 1</div><div class='del'>-</div><div class='del'>-/* XOR some bits of PA into CH4~CH6 bits (bits 12~14 of PA),</div><div class='del'>- * hash bit is only effective when related setting is enabled</div><div class='del'>- */</div><div class='del'>-#define UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) ((((channel_idx) &gt;&gt; 5) &amp; 0x1) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 20) &amp; 0x1ULL &amp; UMC_V12_0_HASH_64K) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 27) &amp; 0x1ULL &amp; UMC_V12_0_HASH_2M) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 34) &amp; 0x1ULL &amp; UMC_V12_0_HASH_1G) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 41) &amp; 0x1ULL &amp; UMC_V12_0_HASH_1T))</div><div class='del'>-#define UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) ((((channel_idx) &gt;&gt; 6) &amp; 0x1) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 21) &amp; 0x1ULL &amp; UMC_V12_0_HASH_64K) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 28) &amp; 0x1ULL &amp; UMC_V12_0_HASH_2M) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 35) &amp; 0x1ULL &amp; UMC_V12_0_HASH_1G) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 42) &amp; 0x1ULL &amp; UMC_V12_0_HASH_1T))</div><div class='del'>-#define UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) ((((channel_idx) &gt;&gt; 4) &amp; 0x1) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 19) &amp; 0x1ULL &amp; UMC_V12_0_HASH_64K) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 26) &amp; 0x1ULL &amp; UMC_V12_0_HASH_2M) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 33) &amp; 0x1ULL &amp; UMC_V12_0_HASH_1G) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 40) &amp; 0x1ULL &amp; UMC_V12_0_HASH_1T) ^ \</div><div class='del'>-				(((pa)  &gt;&gt; 47) &amp; 0x1ULL &amp; UMC_V12_0_HASH_4K))</div><div class='del'>-#define UMC_V12_0_SET_CHANNEL_HASH(channel_idx, pa) do { \</div><div class='del'>-		(pa) &amp;= ~(0x7ULL &lt;&lt; UMC_V12_0_PA_CH4_BIT); \</div><div class='del'>-		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) &lt;&lt; UMC_V12_0_PA_CH4_BIT); \</div><div class='del'>-		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) &lt;&lt; UMC_V12_0_PA_CH5_BIT); \</div><div class='del'>-		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) &lt;&lt; UMC_V12_0_PA_CH6_BIT); \</div><div class='del'>-	} while (0)</div><div class='add'>+/* bank bit in SOC physical address */</div><div class='add'>+#define UMC_V12_0_PA_B0_BIT 19</div><div class='add'>+#define UMC_V12_0_PA_B1_BIT 20</div><div class='add'>+/* row bits in MCA address */</div><div class='add'>+#define UMC_V12_0_MA_R0_BIT 10</div><div class='add'>+</div><div class='add'>+#define MCA_UMC_HWID_V12_0     0x96</div><div class='add'>+#define MCA_UMC_MCATYPE_V12_0  0x0</div><div class='ctx'> </div><div class='ctx'> #define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) &gt;&gt; 20) &amp; 0x1) * 4) + \</div><div class='ctx'> 			(((_ipid_lo) &gt;&gt; 12) &amp; 0xF))</div><div class='ctx'> #define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) &gt;&gt; 21) &amp; 0x7)</div><div class='ctx'> </div><div class='add'>+#define MCA_IPID_2_DIE_ID(ipid)  ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) &gt;&gt; 2) &amp; 0x03)</div><div class='add'>+</div><div class='add'>+#define MCA_IPID_2_UMC_CH(ipid) \</div><div class='add'>+	(MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))</div><div class='add'>+</div><div class='add'>+#define MCA_IPID_2_UMC_INST(ipid) \</div><div class='add'>+	(MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))</div><div class='add'>+</div><div class='add'>+#define MCA_IPID_2_SOCKET_ID(ipid) \</div><div class='add'>+	(((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) &amp; 0x1) &lt;&lt; 2) | \</div><div class='add'>+	 (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) &amp; 0x03))</div><div class='add'>+</div><div class='ctx'> bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status);</div><div class='ctx'> bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);</div><div class='ctx'> bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);</div><div class='ctx'> </div><div class='ctx'> typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status);</div><div class='ctx'> </div><div class='del'>-extern const uint32_t</div><div class='del'>-	umc_v12_0_channel_idx_tbl[]</div><div class='del'>-			[UMC_V12_0_UMC_INSTANCE_NUM]</div><div class='del'>-			[UMC_V12_0_CHANNEL_INSTANCE_NUM];</div><div class='del'>-</div><div class='ctx'> extern struct amdgpu_umc_ras umc_v12_0_ras;</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c<br/>index c4c77257710c..a32f87992f20 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umc_v8_10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/umc_v8_10.c</a></div><div class='hunk'>@@ -442,11 +442,6 @@ static void umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *ade</div><div class='ctx'> 		umc_v8_10_ecc_info_query_error_address, ras_error_status);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void umc_v8_10_set_eeprom_table_version(struct amdgpu_ras_eeprom_table_header *hdr)</div><div class='del'>-{</div><div class='del'>-	hdr-&gt;version = RAS_TABLE_VER_V2_1;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {</div><div class='ctx'> 	.query_ras_error_count = umc_v8_10_query_ras_error_count,</div><div class='ctx'> 	.query_ras_error_address = umc_v8_10_query_ras_error_address,</div><div class='hunk'>@@ -460,5 +455,4 @@ struct amdgpu_umc_ras umc_v8_10_ras = {</div><div class='ctx'> 	.query_ras_poison_mode = umc_v8_10_query_ras_poison_mode,</div><div class='ctx'> 	.ecc_info_query_ras_error_count = umc_v8_10_ecc_info_query_ras_error_count,</div><div class='ctx'> 	.ecc_info_query_ras_error_address = umc_v8_10_ecc_info_query_ras_error_address,</div><div class='del'>-	.set_eeprom_table_version = umc_v8_10_set_eeprom_table_version,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_14.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_14.c<br/>new file mode 100644<br/>index 000000000000..eaca10a3c4a9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v8_14.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/umc_v8_14.c</a></div><div class='hunk'>@@ -0,0 +1,160 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include "umc_v8_14.h"</div><div class='add'>+#include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_umc.h"</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "umc/umc_8_14_0_offset.h"</div><div class='add'>+#include "umc/umc_8_14_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+static inline uint32_t get_umc_v8_14_reg_offset(struct amdgpu_device *adev,</div><div class='add'>+					    uint32_t umc_inst,</div><div class='add'>+					    uint32_t ch_inst)</div><div class='add'>+{</div><div class='add'>+	return adev-&gt;umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int umc_v8_14_clear_error_count_per_channel(struct amdgpu_device *adev,</div><div class='add'>+					uint32_t node_inst, uint32_t umc_inst,</div><div class='add'>+					uint32_t ch_inst, void *data)</div><div class='add'>+{</div><div class='add'>+	uint32_t ecc_err_cnt_addr;</div><div class='add'>+	uint32_t umc_reg_offset =</div><div class='add'>+		get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst);</div><div class='add'>+</div><div class='add'>+	ecc_err_cnt_addr =</div><div class='add'>+		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);</div><div class='add'>+</div><div class='add'>+	/* clear error count */</div><div class='add'>+	WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,</div><div class='add'>+			UMC_V8_14_CE_CNT_INIT);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v8_14_clear_error_count(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_umc_loop_channels(adev,</div><div class='add'>+		umc_v8_14_clear_error_count_per_channel, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v8_14_query_correctable_error_count(struct amdgpu_device *adev,</div><div class='add'>+						   uint32_t umc_reg_offset,</div><div class='add'>+						   unsigned long *error_count)</div><div class='add'>+{</div><div class='add'>+	uint32_t ecc_err_cnt, ecc_err_cnt_addr;</div><div class='add'>+</div><div class='add'>+	/* UMC 8_14 registers */</div><div class='add'>+	ecc_err_cnt_addr =</div><div class='add'>+		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);</div><div class='add'>+</div><div class='add'>+	ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);</div><div class='add'>+	*error_count +=</div><div class='add'>+		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccErrCnt) -</div><div class='add'>+		 UMC_V8_14_CE_CNT_INIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v8_14_query_uncorrectable_error_count(struct amdgpu_device *adev,</div><div class='add'>+						      uint32_t umc_reg_offset,</div><div class='add'>+						      unsigned long *error_count)</div><div class='add'>+{</div><div class='add'>+	uint32_t ecc_err_cnt, ecc_err_cnt_addr;</div><div class='add'>+	/* UMC 8_14 registers */</div><div class='add'>+	ecc_err_cnt_addr =</div><div class='add'>+		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);</div><div class='add'>+</div><div class='add'>+	ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);</div><div class='add'>+	*error_count +=</div><div class='add'>+		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccUnCorrErrCnt) -</div><div class='add'>+		 UMC_V8_14_CE_CNT_INIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int umc_v8_14_query_error_count_per_channel(struct amdgpu_device *adev,</div><div class='add'>+					uint32_t node_inst, uint32_t umc_inst,</div><div class='add'>+					uint32_t ch_inst, void *data)</div><div class='add'>+{</div><div class='add'>+	struct ras_err_data *err_data = (struct ras_err_data *)data;</div><div class='add'>+	uint32_t umc_reg_offset =</div><div class='add'>+		get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst);</div><div class='add'>+</div><div class='add'>+	umc_v8_14_query_correctable_error_count(adev,</div><div class='add'>+					umc_reg_offset,</div><div class='add'>+					&amp;(err_data-&gt;ce_count));</div><div class='add'>+	umc_v8_14_query_uncorrectable_error_count(adev,</div><div class='add'>+					umc_reg_offset,</div><div class='add'>+					&amp;(err_data-&gt;ue_count));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v8_14_query_ras_error_count(struct amdgpu_device *adev,</div><div class='add'>+					   void *ras_error_status)</div><div class='add'>+{</div><div class='add'>+	amdgpu_umc_loop_channels(adev,</div><div class='add'>+		umc_v8_14_query_error_count_per_channel, ras_error_status);</div><div class='add'>+</div><div class='add'>+	umc_v8_14_clear_error_count(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int umc_v8_14_err_cnt_init_per_channel(struct amdgpu_device *adev,</div><div class='add'>+					uint32_t node_inst, uint32_t umc_inst,</div><div class='add'>+					uint32_t ch_inst, void *data)</div><div class='add'>+{</div><div class='add'>+	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;</div><div class='add'>+	uint32_t ecc_err_cnt_addr;</div><div class='add'>+	uint32_t umc_reg_offset =</div><div class='add'>+		get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst);</div><div class='add'>+</div><div class='add'>+	ecc_err_cnt_sel_addr =</div><div class='add'>+		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCntSel);</div><div class='add'>+	ecc_err_cnt_addr =</div><div class='add'>+		SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);</div><div class='add'>+</div><div class='add'>+	ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);</div><div class='add'>+</div><div class='add'>+	/* set ce error interrupt type to APIC based interrupt */</div><div class='add'>+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_GeccErrCntSel,</div><div class='add'>+					GeccErrInt, 0x1);</div><div class='add'>+	WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);</div><div class='add'>+	/* set error count to initial value */</div><div class='add'>+	WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_14_CE_CNT_INIT);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v8_14_err_cnt_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_umc_loop_channels(adev,</div><div class='add'>+		umc_v8_14_err_cnt_init_per_channel, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ras_block_hw_ops umc_v8_14_ras_hw_ops = {</div><div class='add'>+	.query_ras_error_count = umc_v8_14_query_ras_error_count,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_umc_ras umc_v8_14_ras = {</div><div class='add'>+	.ras_block = {</div><div class='add'>+		.hw_ops = &amp;umc_v8_14_ras_hw_ops,</div><div class='add'>+	},</div><div class='add'>+	.err_cnt_init = umc_v8_14_err_cnt_init,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_14.h b/drivers/gpu/drm/amd/amdgpu/umc_v8_14.h<br/>new file mode 100644<br/>index 000000000000..20a258f0017a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v8_14.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/umc_v8_14.h</a></div><div class='hunk'>@@ -0,0 +1,51 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#ifndef __UMC_V8_14_H__</div><div class='add'>+#define __UMC_V8_14_H__</div><div class='add'>+</div><div class='add'>+#include "soc15_common.h"</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+</div><div class='add'>+/* number of umc channel instance with memory map register access */</div><div class='add'>+#define UMC_V8_14_CHANNEL_INSTANCE_NUM		2</div><div class='add'>+/* number of umc instance with memory map register access */</div><div class='add'>+#define UMC_V8_14_UMC_INSTANCE_NUM(adev)		((adev)-&gt;umc.node_inst_num)</div><div class='add'>+</div><div class='add'>+/* Total channel instances for all available umc nodes */</div><div class='add'>+#define UMC_V8_14_TOTAL_CHANNEL_NUM(adev) \</div><div class='add'>+	(UMC_V8_14_CHANNEL_INSTANCE_NUM * (adev)-&gt;gmc.num_umc)</div><div class='add'>+</div><div class='add'>+/* UMC register per channel offset */</div><div class='add'>+#define UMC_V8_14_PER_CHANNEL_OFFSET		0x400</div><div class='add'>+</div><div class='add'>+#define UMC_V8_14_INST_DIST		0x40000</div><div class='add'>+</div><div class='add'>+/* EccErrCnt max value */</div><div class='add'>+#define UMC_V8_14_CE_CNT_MAX		0xffff</div><div class='add'>+/* umc ce interrupt threshold */</div><div class='add'>+#define UMC_V8_14_CE_INT_THRESHOLD		0xffff</div><div class='add'>+/* umc ce count initial value */</div><div class='add'>+#define UMC_V8_14_CE_CNT_INIT	(UMC_V8_14_CE_CNT_MAX - UMC_V8_14_CE_INT_THRESHOLD)</div><div class='add'>+</div><div class='add'>+extern struct amdgpu_umc_ras umc_v8_14_ras;</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c<br/>index 8e7b763cfdb7..ce3bb12e3572 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/firmware.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "soc15_common.h"</div><div class='ctx'> #include "soc21.h"</div><div class='hunk'>@@ -60,7 +61,7 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> </div><div class='ctx'> 	umsch-&gt;cmd_buf_curr_ptr = umsch-&gt;cmd_buf_ptr;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, VCN_HWIP, 0) &gt;= IP_VERSION(4, 0, 5)) {</div><div class='ctx'> 		WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,</div><div class='ctx'> 			1 &lt;&lt; UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);</div><div class='ctx'> 		SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,</div><div class='hunk'>@@ -115,9 +116,8 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> 		upper_32_bits(adev-&gt;umsch_mm.data_start_addr));</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_LO,</div><div class='del'>-		lower_32_bits(adev-&gt;umsch_mm.data_size - 1));</div><div class='del'>-	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI,</div><div class='del'>-		upper_32_bits(adev-&gt;umsch_mm.data_size - 1));</div><div class='add'>+		adev-&gt;umsch_mm.data_size - 1);</div><div class='add'>+	WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI, 0);</div><div class='ctx'> </div><div class='ctx'> 	data = adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP ?</div><div class='ctx'> 	       0 : adev-&gt;umsch_mm.data_fw_gpu_addr;</div><div class='hunk'>@@ -143,6 +143,11 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> 	WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, 0);</div><div class='ctx'> 	WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, 0);</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, lower_32_bits(umsch-&gt;log_gpu_addr));</div><div class='add'>+	WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, upper_32_bits(umsch-&gt;log_gpu_addr));</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	WREG32_SOC15_UMSCH(regVCN_MES_GP1_LO, 0);</div><div class='ctx'> 	WREG32_SOC15_UMSCH(regVCN_MES_GP1_HI, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -225,6 +230,8 @@ static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_SIZE, ring-&gt;ring_size);</div><div class='ctx'> </div><div class='add'>+	ring-&gt;wptr = 0;</div><div class='add'>+</div><div class='ctx'> 	data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);</div><div class='ctx'> 	data &amp;= ~(VCN_RB_ENABLE__AUDIO_RB_EN_MASK);</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data);</div><div class='hunk'>@@ -248,7 +255,7 @@ static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> 	data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, VCN_HWIP, 0) &gt;= IP_VERSION(4, 0, 5)) {</div><div class='ctx'> 		WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,</div><div class='ctx'> 			2 &lt;&lt; UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);</div><div class='ctx'> 		SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,</div><div class='hunk'>@@ -271,6 +278,8 @@ static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch)</div><div class='ctx'> </div><div class='ctx'> 	set_hw_resources.vmid_mask_mm_vcn = umsch-&gt;vmid_mask_mm_vcn;</div><div class='ctx'> 	set_hw_resources.vmid_mask_mm_vpe = umsch-&gt;vmid_mask_mm_vpe;</div><div class='add'>+	set_hw_resources.collaboration_mask_vpe =</div><div class='add'>+		adev-&gt;vpe.collaborate_mode ? 0x3 : 0x0;</div><div class='ctx'> 	set_hw_resources.engine_mask = umsch-&gt;engine_mask;</div><div class='ctx'> </div><div class='ctx'> 	set_hw_resources.vcn0_hqd_mask[0] = umsch-&gt;vcn0_hqd_mask;</div><div class='hunk'>@@ -346,6 +355,7 @@ static int umsch_mm_v4_0_add_queue(struct amdgpu_umsch_mm *umsch,</div><div class='ctx'> 	add_queue.h_queue = input_ptr-&gt;h_queue;</div><div class='ctx'> 	add_queue.vm_context_cntl = input_ptr-&gt;vm_context_cntl;</div><div class='ctx'> 	add_queue.is_context_suspended = input_ptr-&gt;is_context_suspended;</div><div class='add'>+	add_queue.collaboration_mode = adev-&gt;vpe.collaborate_mode ? 1 : 0;</div><div class='ctx'> </div><div class='ctx'> 	add_queue.api_status.api_completion_fence_addr = umsch-&gt;ring.fence_drv.gpu_addr;</div><div class='ctx'> 	add_queue.api_status.api_completion_fence_value = ++umsch-&gt;ring.fence_drv.sync_seq;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c<br/>index a6006f231c65..2e79a3afc774 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c</a></div><div class='hunk'>@@ -98,7 +98,7 @@ static void uvd_v3_1_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * uvd_v3_1_ring_emit_fence - emit an fence &amp; trap command</div><div class='add'>+ * uvd_v3_1_ring_emit_fence - emit a fence &amp; trap command</div><div class='ctx'>  *</div><div class='ctx'>  * @ring: amdgpu_ring pointer</div><div class='ctx'>  * @addr: address</div><div class='hunk'>@@ -242,7 +242,7 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	uint64_t addr;</div><div class='ctx'> 	uint32_t size;</div><div class='ctx'> </div><div class='del'>-	/* programm the VCPU memory controller bits 0-27 */</div><div class='add'>+	/* program the VCPU memory controller bits 0-27 */</div><div class='ctx'> 	addr = (adev-&gt;uvd.inst-&gt;gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) &gt;&gt; 3;</div><div class='ctx'> 	size = AMDGPU_UVD_FIRMWARE_SIZE(adev) &gt;&gt; 3;</div><div class='ctx'> 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);</div><div class='hunk'>@@ -416,7 +416,7 @@ static int uvd_v3_1_start(struct amdgpu_device *adev)</div><div class='ctx'> 	/* Set the write pointer delay */</div><div class='ctx'> 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);</div><div class='ctx'> </div><div class='del'>-	/* programm the 4GB memory segment for rptr and ring buffer */</div><div class='add'>+	/* Program the 4GB memory segment for rptr and ring buffer */</div><div class='ctx'> 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring-&gt;gpu_addr) |</div><div class='ctx'> 		   (0x7 &lt;&lt; 16) | (0x1 &lt;&lt; 31));</div><div class='ctx'> </div><div class='hunk'>@@ -531,9 +531,9 @@ static void uvd_v3_1_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_early_init(void *handle)</div><div class='add'>+static int uvd_v3_1_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	adev-&gt;uvd.num_uvd_inst = 1;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v3_1_set_ring_funcs(adev);</div><div class='hunk'>@@ -542,10 +542,10 @@ static int uvd_v3_1_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_sw_init(void *handle)</div><div class='add'>+static int uvd_v3_1_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> 	void *ptr;</div><div class='ctx'> 	uint32_t ucode_len;</div><div class='hunk'>@@ -580,10 +580,10 @@ static int uvd_v3_1_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_sw_fini(void *handle)</div><div class='add'>+static int uvd_v3_1_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_uvd_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -621,18 +621,42 @@ static void uvd_v3_1_enable_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v3_1_hw_init - start and test UVD block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='del'>- * Initialize the hardware, boot up the VCPU and do some testing</div><div class='add'>+ * Initialize the hardware, boot up the VCPU and do some testing.</div><div class='add'>+ *</div><div class='add'>+ * On SI, the UVD is meant to be used in a specific power state,</div><div class='add'>+ * or alternatively the driver can manually enable its clock.</div><div class='add'>+ * In amdgpu we use the dedicated UVD power state when DPM is enabled.</div><div class='add'>+ * Calling amdgpu_dpm_enable_uvd makes DPM select the UVD power state</div><div class='add'>+ * for the SMU and afterwards enables the UVD clock.</div><div class='add'>+ * This is automatically done by amdgpu_uvd_ring_begin_use when work</div><div class='add'>+ * is submitted to the UVD ring. Here, we have to call it manually</div><div class='add'>+ * in order to power up UVD before firmware validation.</div><div class='add'>+ *</div><div class='add'>+ * Note that we must not disable the UVD clock here, as that would</div><div class='add'>+ * cause the ring test to fail. However, UVD is powered off</div><div class='add'>+ * automatically after the ring test: amdgpu_uvd_ring_end_use calls</div><div class='add'>+ * the UVD idle work handler which will disable the UVD clock when</div><div class='add'>+ * all fences are signalled.</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v3_1_hw_init(void *handle)</div><div class='add'>+static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;uvd.inst-&gt;ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v3_1_mc_resume(adev);</div><div class='add'>+	uvd_v3_1_enable_mgcg(adev, true);</div><div class='add'>+</div><div class='add'>+	/* Make sure UVD is powered during FW validation.</div><div class='add'>+	 * It's going to be automatically powered off after the ring test.</div><div class='add'>+	 */</div><div class='add'>+	if (adev-&gt;pm.dpm_enabled)</div><div class='add'>+		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);</div><div class='ctx'> </div><div class='ctx'> 	r = uvd_v3_1_fw_validate(adev);</div><div class='ctx'> 	if (r) {</div><div class='hunk'>@@ -640,9 +664,6 @@ static int uvd_v3_1_hw_init(void *handle)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	uvd_v3_1_enable_mgcg(adev, true);</div><div class='del'>-	amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);</div><div class='del'>-</div><div class='ctx'> 	uvd_v3_1_start(adev);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='hunk'>@@ -688,13 +709,13 @@ done:</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v3_1_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the UVD block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v3_1_hw_fini(void *handle)</div><div class='add'>+static int uvd_v3_1_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;uvd.idle_work);</div><div class='ctx'> </div><div class='hunk'>@@ -704,17 +725,17 @@ static int uvd_v3_1_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_prepare_suspend(void *handle)</div><div class='add'>+static int uvd_v3_1_prepare_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_prepare_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_suspend(void *handle)</div><div class='add'>+static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Proper cleanups before halting the HW engine:</div><div class='hunk'>@@ -740,36 +761,35 @@ static int uvd_v3_1_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = uvd_v3_1_hw_fini(adev);</div><div class='add'>+	r = uvd_v3_1_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_resume(void *handle)</div><div class='add'>+static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_uvd_resume(adev);</div><div class='add'>+	r = amdgpu_uvd_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return uvd_v3_1_hw_init(adev);</div><div class='add'>+	return uvd_v3_1_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool uvd_v3_1_is_idle(void *handle)</div><div class='add'>+static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return !(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_wait_for_idle(void *handle)</div><div class='add'>+static int uvd_v3_1_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		if (!(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK))</div><div class='hunk'>@@ -778,9 +798,9 @@ static int uvd_v3_1_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_soft_reset(void *handle)</div><div class='add'>+static int uvd_v3_1_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v3_1_stop(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -791,13 +811,13 @@ static int uvd_v3_1_soft_reset(void *handle)</div><div class='ctx'> 	return uvd_v3_1_start(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v3_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v3_1_set_powergating_state(void *handle,</div><div class='add'>+static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -806,7 +826,6 @@ static int uvd_v3_1_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {</div><div class='ctx'> 	.name = "uvd_v3_1",</div><div class='ctx'> 	.early_init = uvd_v3_1_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = uvd_v3_1_sw_init,</div><div class='ctx'> 	.sw_fini = uvd_v3_1_sw_fini,</div><div class='ctx'> 	.hw_init = uvd_v3_1_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c<br/>index 1aa09ad7bbe3..4b96fd583772 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c</a></div><div class='hunk'>@@ -44,7 +44,7 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static int uvd_v4_2_start(struct amdgpu_device *adev);</div><div class='ctx'> static void uvd_v4_2_stop(struct amdgpu_device *adev);</div><div class='del'>-static int uvd_v4_2_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				enum amd_clockgating_state state);</div><div class='ctx'> static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,</div><div class='ctx'> 			     bool sw_mode);</div><div class='hunk'>@@ -90,9 +90,9 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_early_init(void *handle)</div><div class='add'>+static int uvd_v4_2_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	adev-&gt;uvd.num_uvd_inst = 1;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v4_2_set_ring_funcs(adev);</div><div class='hunk'>@@ -101,10 +101,10 @@ static int uvd_v4_2_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_sw_init(void *handle)</div><div class='add'>+static int uvd_v4_2_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	/* UVD TRAP */</div><div class='hunk'>@@ -130,10 +130,10 @@ static int uvd_v4_2_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_sw_fini(void *handle)</div><div class='add'>+static int uvd_v4_2_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_uvd_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -147,13 +147,13 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v4_2_hw_init - start and test UVD block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v4_2_hw_init(void *handle)</div><div class='add'>+static int uvd_v4_2_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;uvd.inst-&gt;ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int r;</div><div class='hunk'>@@ -202,13 +202,13 @@ done:</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v4_2_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the UVD block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v4_2_hw_fini(void *handle)</div><div class='add'>+static int uvd_v4_2_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;uvd.idle_work);</div><div class='ctx'> </div><div class='hunk'>@@ -218,17 +218,17 @@ static int uvd_v4_2_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_prepare_suspend(void *handle)</div><div class='add'>+static int uvd_v4_2_prepare_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_prepare_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_suspend(void *handle)</div><div class='add'>+static int uvd_v4_2_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Proper cleanups before halting the HW engine:</div><div class='hunk'>@@ -254,23 +254,22 @@ static int uvd_v4_2_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = uvd_v4_2_hw_fini(adev);</div><div class='add'>+	r = uvd_v4_2_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_resume(void *handle)</div><div class='add'>+static int uvd_v4_2_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_uvd_resume(adev);</div><div class='add'>+	r = amdgpu_uvd_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return uvd_v4_2_hw_init(adev);</div><div class='add'>+	return uvd_v4_2_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -303,7 +302,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)</div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	WREG32(mmUVD_VCPU_CNTL,  1 &lt;&lt; 9);</div><div class='ctx'> </div><div class='del'>-	/* disable interupt */</div><div class='add'>+	/* disable interrupt */</div><div class='ctx'> 	WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 &lt;&lt; 1));</div><div class='ctx'> </div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='hunk'>@@ -313,6 +312,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)</div><div class='ctx'> #endif</div><div class='ctx'> 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);</div><div class='ctx'> 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);</div><div class='add'>+</div><div class='ctx'> 	/* initialize UVD memory controller */</div><div class='ctx'> 	WREG32(mmUVD_LMI_CTRL, 0x203108);</div><div class='ctx'> </div><div class='hunk'>@@ -659,17 +659,17 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,</div><div class='ctx'> 	WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool uvd_v4_2_is_idle(void *handle)</div><div class='add'>+static bool uvd_v4_2_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return !(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_wait_for_idle(void *handle)</div><div class='add'>+static int uvd_v4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		if (!(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK))</div><div class='hunk'>@@ -678,9 +678,9 @@ static int uvd_v4_2_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_soft_reset(void *handle)</div><div class='add'>+static int uvd_v4_2_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v4_2_stop(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -709,13 +709,13 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v4_2_set_powergating_state(void *handle,</div><div class='add'>+static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the UVD block.</div><div class='hunk'>@@ -725,7 +725,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,</div><div class='ctx'> 	 * revisit this when there is a cleaner line between</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE) {</div><div class='ctx'> 		uvd_v4_2_stop(adev);</div><div class='hunk'>@@ -756,7 +756,6 @@ static int uvd_v4_2_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {</div><div class='ctx'> 	.name = "uvd_v4_2",</div><div class='ctx'> 	.early_init = uvd_v4_2_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = uvd_v4_2_sw_init,</div><div class='ctx'> 	.sw_fini = uvd_v4_2_sw_fini,</div><div class='ctx'> 	.hw_init = uvd_v4_2_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c<br/>index f8b229b75435..71409ad8b7ed 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c</a></div><div class='hunk'>@@ -42,7 +42,7 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static int uvd_v5_0_start(struct amdgpu_device *adev);</div><div class='ctx'> static void uvd_v5_0_stop(struct amdgpu_device *adev);</div><div class='del'>-static int uvd_v5_0_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state);</div><div class='ctx'> static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> 				 bool enable);</div><div class='hunk'>@@ -88,9 +88,9 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_early_init(void *handle)</div><div class='add'>+static int uvd_v5_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	adev-&gt;uvd.num_uvd_inst = 1;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v5_0_set_ring_funcs(adev);</div><div class='hunk'>@@ -99,10 +99,10 @@ static int uvd_v5_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_sw_init(void *handle)</div><div class='add'>+static int uvd_v5_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	/* UVD TRAP */</div><div class='hunk'>@@ -128,10 +128,10 @@ static int uvd_v5_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_sw_fini(void *handle)</div><div class='add'>+static int uvd_v5_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_uvd_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -143,19 +143,19 @@ static int uvd_v5_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v5_0_hw_init - start and test UVD block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v5_0_hw_init(void *handle)</div><div class='add'>+static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;uvd.inst-&gt;ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);</div><div class='del'>-	uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);</div><div class='add'>+	uvd_v5_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);</div><div class='ctx'> 	uvd_v5_0_enable_mgcg(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='hunk'>@@ -200,13 +200,13 @@ done:</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v5_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the UVD block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v5_0_hw_fini(void *handle)</div><div class='add'>+static int uvd_v5_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;uvd.idle_work);</div><div class='ctx'> </div><div class='hunk'>@@ -216,17 +216,17 @@ static int uvd_v5_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_prepare_suspend(void *handle)</div><div class='add'>+static int uvd_v5_0_prepare_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_prepare_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_suspend(void *handle)</div><div class='add'>+static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Proper cleanups before halting the HW engine:</div><div class='hunk'>@@ -252,23 +252,22 @@ static int uvd_v5_0_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = uvd_v5_0_hw_fini(adev);</div><div class='add'>+	r = uvd_v5_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_resume(void *handle)</div><div class='add'>+static int uvd_v5_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_uvd_resume(adev);</div><div class='add'>+	r = amdgpu_uvd_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return uvd_v5_0_hw_init(adev);</div><div class='add'>+	return uvd_v5_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -581,17 +580,17 @@ static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool uvd_v5_0_is_idle(void *handle)</div><div class='add'>+static bool uvd_v5_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return !(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_wait_for_idle(void *handle)</div><div class='add'>+static int uvd_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		if (!(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK))</div><div class='hunk'>@@ -600,9 +599,9 @@ static int uvd_v5_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_soft_reset(void *handle)</div><div class='add'>+static int uvd_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	uvd_v5_0_stop(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -791,15 +790,15 @@ static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* wait for STATUS to clear */</div><div class='del'>-		if (uvd_v5_0_wait_for_idle(handle))</div><div class='add'>+		if (uvd_v5_0_wait_for_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 		uvd_v5_0_enable_clock_gating(adev, true);</div><div class='ctx'> </div><div class='hunk'>@@ -813,7 +812,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v5_0_set_powergating_state(void *handle,</div><div class='add'>+static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the UVD block.</div><div class='hunk'>@@ -823,7 +822,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * revisit this when there is a cleaner line between</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE) {</div><div class='hunk'>@@ -838,9 +837,9 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void uvd_v5_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void uvd_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;pm.mutex);</div><div class='hunk'>@@ -863,7 +862,6 @@ out:</div><div class='ctx'> static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {</div><div class='ctx'> 	.name = "uvd_v5_0",</div><div class='ctx'> 	.early_init = uvd_v5_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = uvd_v5_0_sw_init,</div><div class='ctx'> 	.sw_fini = uvd_v5_0_sw_fini,</div><div class='ctx'> 	.hw_init = uvd_v5_0_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br/>index a9a6880f44e3..ceb94bbb03a4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c</a></div><div class='hunk'>@@ -48,7 +48,7 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static int uvd_v6_0_start(struct amdgpu_device *adev);</div><div class='ctx'> static void uvd_v6_0_stop(struct amdgpu_device *adev);</div><div class='ctx'> static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);</div><div class='del'>-static int uvd_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state);</div><div class='ctx'> static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> 				 bool enable);</div><div class='hunk'>@@ -217,7 +217,8 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL, ib_size_dw * 4,</div><div class='del'>-				     AMDGPU_IB_POOL_DIRECT, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DIRECT, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -281,7 +282,8 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL, ib_size_dw * 4,</div><div class='del'>-				     AMDGPU_IB_POOL_DIRECT, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DIRECT, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -354,9 +356,9 @@ error:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_early_init(void *handle)</div><div class='add'>+static int uvd_v6_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	adev-&gt;uvd.num_uvd_inst = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp;</div><div class='hunk'>@@ -375,11 +377,11 @@ static int uvd_v6_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_sw_init(void *handle)</div><div class='add'>+static int uvd_v6_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* UVD TRAP */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &amp;adev-&gt;uvd.inst-&gt;irq);</div><div class='hunk'>@@ -435,10 +437,10 @@ static int uvd_v6_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_sw_fini(void *handle)</div><div class='add'>+static int uvd_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_uvd_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -455,19 +457,19 @@ static int uvd_v6_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v6_0_hw_init - start and test UVD block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v6_0_hw_init(void *handle)</div><div class='add'>+static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;uvd.inst-&gt;ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);</div><div class='del'>-	uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);</div><div class='add'>+	uvd_v6_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);</div><div class='ctx'> 	uvd_v6_0_enable_mgcg(adev, true);</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='hunk'>@@ -524,13 +526,13 @@ done:</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v6_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the UVD block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v6_0_hw_fini(void *handle)</div><div class='add'>+static int uvd_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;uvd.idle_work);</div><div class='ctx'> </div><div class='hunk'>@@ -540,17 +542,17 @@ static int uvd_v6_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_prepare_suspend(void *handle)</div><div class='add'>+static int uvd_v6_0_prepare_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_prepare_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_suspend(void *handle)</div><div class='add'>+static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Proper cleanups before halting the HW engine:</div><div class='hunk'>@@ -576,23 +578,22 @@ static int uvd_v6_0_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = uvd_v6_0_hw_fini(adev);</div><div class='add'>+	r = uvd_v6_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_resume(void *handle)</div><div class='add'>+static int uvd_v6_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_uvd_resume(adev);</div><div class='add'>+	r = amdgpu_uvd_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return uvd_v6_0_hw_init(adev);</div><div class='add'>+	return uvd_v6_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1144,29 +1145,29 @@ static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_write(ring, vmid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool uvd_v6_0_is_idle(void *handle)</div><div class='add'>+static bool uvd_v6_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return !(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_wait_for_idle(void *handle)</div><div class='add'>+static int uvd_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (uvd_v6_0_is_idle(handle))</div><div class='add'>+		if (uvd_v6_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd</div><div class='del'>-static bool uvd_v6_0_check_soft_reset(void *handle)</div><div class='add'>+static bool uvd_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='ctx'> </div><div class='hunk'>@@ -1184,9 +1185,9 @@ static bool uvd_v6_0_check_soft_reset(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_pre_soft_reset(void *handle)</div><div class='add'>+static int uvd_v6_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;uvd.inst-&gt;srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1195,9 +1196,9 @@ static int uvd_v6_0_pre_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_soft_reset(void *handle)</div><div class='add'>+static int uvd_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;uvd.inst-&gt;srbm_soft_reset)</div><div class='hunk'>@@ -1226,9 +1227,9 @@ static int uvd_v6_0_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_post_soft_reset(void *handle)</div><div class='add'>+static int uvd_v6_0_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;uvd.inst-&gt;srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1451,15 +1452,15 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* wait for STATUS to clear */</div><div class='del'>-		if (uvd_v6_0_wait_for_idle(handle))</div><div class='add'>+		if (uvd_v6_0_wait_for_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 		uvd_v6_0_enable_clock_gating(adev, true);</div><div class='ctx'> 		/* enable HW gates because UVD is idle */</div><div class='hunk'>@@ -1472,7 +1473,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v6_0_set_powergating_state(void *handle,</div><div class='add'>+static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the UVD block.</div><div class='hunk'>@@ -1482,7 +1483,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * revisit this when there is a cleaner line between</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);</div><div class='hunk'>@@ -1499,9 +1500,9 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void uvd_v6_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void uvd_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;pm.mutex);</div><div class='hunk'>@@ -1528,7 +1529,6 @@ out:</div><div class='ctx'> static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {</div><div class='ctx'> 	.name = "uvd_v6_0",</div><div class='ctx'> 	.early_init = uvd_v6_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = uvd_v6_0_sw_init,</div><div class='ctx'> 	.sw_fini = uvd_v6_0_sw_fini,</div><div class='ctx'> 	.hw_init = uvd_v6_0_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c<br/>index 6068b784dc69..1f8866f3f63c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c</a></div><div class='hunk'>@@ -225,7 +225,8 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle,</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL, ib_size_dw * 4,</div><div class='del'>-				     AMDGPU_IB_POOL_DIRECT, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DIRECT, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -288,7 +289,8 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle,</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_job_alloc_with_ib(ring-&gt;adev, NULL, NULL, ib_size_dw * 4,</div><div class='del'>-				     AMDGPU_IB_POOL_DIRECT, &amp;job);</div><div class='add'>+				     AMDGPU_IB_POOL_DIRECT, &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -361,9 +363,9 @@ error:</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v7_0_early_init(void *handle)</div><div class='add'>+static int uvd_v7_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;asic_type == CHIP_VEGA20) {</div><div class='ctx'> 		u32 harvest;</div><div class='hunk'>@@ -395,12 +397,12 @@ static int uvd_v7_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v7_0_sw_init(void *handle)</div><div class='add'>+static int uvd_v7_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> </div><div class='ctx'> 	int i, j, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; adev-&gt;uvd.num_uvd_inst; j++) {</div><div class='ctx'> 		if (adev-&gt;uvd.harvest_config &amp; (1 &lt;&lt; j))</div><div class='hunk'>@@ -487,10 +489,10 @@ static int uvd_v7_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v7_0_sw_fini(void *handle)</div><div class='add'>+static int uvd_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -510,13 +512,13 @@ static int uvd_v7_0_sw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v7_0_hw_init - start and test UVD block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v7_0_hw_init(void *handle)</div><div class='add'>+static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int i, j, r;</div><div class='hunk'>@@ -588,13 +590,13 @@ done:</div><div class='ctx'> /**</div><div class='ctx'>  * uvd_v7_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: handle used to pass amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the UVD block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int uvd_v7_0_hw_fini(void *handle)</div><div class='add'>+static int uvd_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;uvd.idle_work);</div><div class='ctx'> </div><div class='hunk'>@@ -608,17 +610,17 @@ static int uvd_v7_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v7_0_prepare_suspend(void *handle)</div><div class='add'>+static int uvd_v7_0_prepare_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_prepare_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v7_0_suspend(void *handle)</div><div class='add'>+static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Proper cleanups before halting the HW engine:</div><div class='hunk'>@@ -644,23 +646,22 @@ static int uvd_v7_0_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = uvd_v7_0_hw_fini(adev);</div><div class='add'>+	r = uvd_v7_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_uvd_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uvd_v7_0_resume(void *handle)</div><div class='add'>+static int uvd_v7_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_uvd_resume(adev);</div><div class='add'>+	r = amdgpu_uvd_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return uvd_v7_0_hw_init(adev);</div><div class='add'>+	return uvd_v7_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1289,7 +1290,7 @@ static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,</div><div class='ctx'> 					   struct amdgpu_job *job,</div><div class='ctx'> 					   struct amdgpu_ib *ib)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_ring *ring = to_amdgpu_ring(job-&gt;base.sched);</div><div class='add'>+	struct amdgpu_ring *ring = amdgpu_job_ring(job);</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> </div><div class='ctx'> 	/* No patching necessary for the first instance */</div><div class='hunk'>@@ -1463,104 +1464,6 @@ static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='ctx'> 	amdgpu_ring_write(ring, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#if 0</div><div class='del'>-static bool uvd_v7_0_is_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return !(RREG32(mmSRBM_STATUS) &amp; SRBM_STATUS__UVD_BUSY_MASK);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (uvd_v7_0_is_idle(handle))</div><div class='del'>-			return 0;</div><div class='del'>-	}</div><div class='del'>-	return -ETIMEDOUT;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd</div><div class='del'>-static bool uvd_v7_0_check_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 srbm_soft_reset = 0;</div><div class='del'>-	u32 tmp = RREG32(mmSRBM_STATUS);</div><div class='del'>-</div><div class='del'>-	if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||</div><div class='del'>-	    REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||</div><div class='del'>-	    (RREG32_SOC15(UVD, ring-&gt;me, mmUVD_STATUS) &amp;</div><div class='del'>-		    AMDGPU_UVD_STATUS_BUSY_MASK))</div><div class='del'>-		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,</div><div class='del'>-				SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);</div><div class='del'>-</div><div class='del'>-	if (srbm_soft_reset) {</div><div class='del'>-		adev-&gt;uvd.inst[ring-&gt;me].srbm_soft_reset = srbm_soft_reset;</div><div class='del'>-		return true;</div><div class='del'>-	} else {</div><div class='del'>-		adev-&gt;uvd.inst[ring-&gt;me].srbm_soft_reset = 0;</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_pre_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;uvd.inst[ring-&gt;me].srbm_soft_reset)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	uvd_v7_0_stop(adev);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 srbm_soft_reset;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;uvd.inst[ring-&gt;me].srbm_soft_reset)</div><div class='del'>-		return 0;</div><div class='del'>-	srbm_soft_reset = adev-&gt;uvd.inst[ring-&gt;me].srbm_soft_reset;</div><div class='del'>-</div><div class='del'>-	if (srbm_soft_reset) {</div><div class='del'>-		u32 tmp;</div><div class='del'>-</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-		tmp |= srbm_soft_reset;</div><div class='del'>-		dev_info(adev-&gt;dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-</div><div class='del'>-		udelay(50);</div><div class='del'>-</div><div class='del'>-		tmp &amp;= ~srbm_soft_reset;</div><div class='del'>-		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-</div><div class='del'>-		/* Wait a little for things to settle down */</div><div class='del'>-		udelay(50);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_post_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;uvd.inst[ring-&gt;me].srbm_soft_reset)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	mdelay(5);</div><div class='del'>-</div><div class='del'>-	return uvd_v7_0_start(adev);</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,</div><div class='ctx'> 					struct amdgpu_irq_src *source,</div><div class='ctx'> 					unsigned type,</div><div class='hunk'>@@ -1610,172 +1513,7 @@ static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#if 0</div><div class='del'>-static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	uint32_t data, data1, data2, suvd_flags;</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(UVD, ring-&gt;me, mmUVD_CGC_CTRL);</div><div class='del'>-	data1 = RREG32_SOC15(UVD, ring-&gt;me, mmUVD_SUVD_CGC_GATE);</div><div class='del'>-	data2 = RREG32_SOC15(UVD, ring-&gt;me, mmUVD_SUVD_CGC_CTRL);</div><div class='del'>-</div><div class='del'>-	data &amp;= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |</div><div class='del'>-		  UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);</div><div class='del'>-</div><div class='del'>-	suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |</div><div class='del'>-		     UVD_SUVD_CGC_GATE__SIT_MASK |</div><div class='del'>-		     UVD_SUVD_CGC_GATE__SMP_MASK |</div><div class='del'>-		     UVD_SUVD_CGC_GATE__SCM_MASK |</div><div class='del'>-		     UVD_SUVD_CGC_GATE__SDB_MASK;</div><div class='del'>-</div><div class='del'>-	data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |</div><div class='del'>-		(1 &lt;&lt; REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |</div><div class='del'>-		(4 &lt;&lt; REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));</div><div class='del'>-</div><div class='del'>-	data &amp;= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__UDEC_CM_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__UDEC_IT_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__UDEC_DB_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__UDEC_MP_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__SYS_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__UDEC_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__MPEG2_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__REGS_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__RBC_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__LMI_MC_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__LMI_UMC_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__IDCT_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__MPRD_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__MPC_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__LBSI_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__LRBBM_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__WCB_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__VCPU_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__JPEG_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__JPEG2_MODE_MASK |</div><div class='del'>-			UVD_CGC_CTRL__SCPU_MODE_MASK);</div><div class='del'>-	data2 &amp;= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |</div><div class='del'>-			UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |</div><div class='del'>-			UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |</div><div class='del'>-			UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |</div><div class='del'>-			UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);</div><div class='del'>-	data1 |= suvd_flags;</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_CGC_CTRL, data);</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_CGC_GATE, 0);</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_SUVD_CGC_GATE, data1);</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_SUVD_CGC_CTRL, data2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	uint32_t data, data1, cgc_flags, suvd_flags;</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(UVD, ring-&gt;me, mmUVD_CGC_GATE);</div><div class='del'>-	data1 = RREG32_SOC15(UVD, ring-&gt;me, mmUVD_SUVD_CGC_GATE);</div><div class='del'>-</div><div class='del'>-	cgc_flags = UVD_CGC_GATE__SYS_MASK |</div><div class='del'>-		UVD_CGC_GATE__UDEC_MASK |</div><div class='del'>-		UVD_CGC_GATE__MPEG2_MASK |</div><div class='del'>-		UVD_CGC_GATE__RBC_MASK |</div><div class='del'>-		UVD_CGC_GATE__LMI_MC_MASK |</div><div class='del'>-		UVD_CGC_GATE__IDCT_MASK |</div><div class='del'>-		UVD_CGC_GATE__MPRD_MASK |</div><div class='del'>-		UVD_CGC_GATE__MPC_MASK |</div><div class='del'>-		UVD_CGC_GATE__LBSI_MASK |</div><div class='del'>-		UVD_CGC_GATE__LRBBM_MASK |</div><div class='del'>-		UVD_CGC_GATE__UDEC_RE_MASK |</div><div class='del'>-		UVD_CGC_GATE__UDEC_CM_MASK |</div><div class='del'>-		UVD_CGC_GATE__UDEC_IT_MASK |</div><div class='del'>-		UVD_CGC_GATE__UDEC_DB_MASK |</div><div class='del'>-		UVD_CGC_GATE__UDEC_MP_MASK |</div><div class='del'>-		UVD_CGC_GATE__WCB_MASK |</div><div class='del'>-		UVD_CGC_GATE__VCPU_MASK |</div><div class='del'>-		UVD_CGC_GATE__SCPU_MASK |</div><div class='del'>-		UVD_CGC_GATE__JPEG_MASK |</div><div class='del'>-		UVD_CGC_GATE__JPEG2_MASK;</div><div class='del'>-</div><div class='del'>-	suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |</div><div class='del'>-				UVD_SUVD_CGC_GATE__SIT_MASK |</div><div class='del'>-				UVD_SUVD_CGC_GATE__SMP_MASK |</div><div class='del'>-				UVD_SUVD_CGC_GATE__SCM_MASK |</div><div class='del'>-				UVD_SUVD_CGC_GATE__SDB_MASK;</div><div class='del'>-</div><div class='del'>-	data |= cgc_flags;</div><div class='del'>-	data1 |= suvd_flags;</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_CGC_GATE, data);</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_SUVD_CGC_GATE, data1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)</div><div class='del'>-{</div><div class='del'>-	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);</div><div class='del'>-</div><div class='del'>-	if (enable)</div><div class='del'>-		tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |</div><div class='del'>-			GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);</div><div class='del'>-	else</div><div class='del'>-		tmp &amp;= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |</div><div class='del'>-			 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);</div><div class='del'>-</div><div class='del'>-	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_set_clockgating_state(void *handle,</div><div class='del'>-					  enum amd_clockgating_state state)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='del'>-</div><div class='del'>-	uvd_v7_0_set_bypass_mode(adev, enable);</div><div class='del'>-</div><div class='del'>-	if (!(adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_UVD_MGCG))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (enable) {</div><div class='del'>-		/* disable HW gating and enable Sw gating */</div><div class='del'>-		uvd_v7_0_set_sw_clock_gating(adev);</div><div class='del'>-	} else {</div><div class='del'>-		/* wait for STATUS to clear */</div><div class='del'>-		if (uvd_v7_0_wait_for_idle(handle))</div><div class='del'>-			return -EBUSY;</div><div class='del'>-</div><div class='del'>-		/* enable HW gates because UVD is idle */</div><div class='del'>-		/* uvd_v7_0_set_hw_clock_gating(adev); */</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='del'>-{</div><div class='del'>-	/* This doesn't actually powergate the UVD block.</div><div class='del'>-	 * That's done in the dpm code via the SMC.  This</div><div class='del'>-	 * just re-inits the block as necessary.  The actual</div><div class='del'>-	 * gating still happens in the dpm code.  We should</div><div class='del'>-	 * revisit this when there is a cleaner line between</div><div class='del'>-	 * the smc and the hw blocks</div><div class='del'>-	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_UVD))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(UVD, ring-&gt;me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);</div><div class='del'>-</div><div class='del'>-	if (state == AMD_PG_STATE_GATE) {</div><div class='del'>-		uvd_v7_0_stop(adev);</div><div class='del'>-		return 0;</div><div class='del'>-	} else {</div><div class='del'>-		return uvd_v7_0_start(adev);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-static int uvd_v7_0_set_clockgating_state(void *handle,</div><div class='add'>+static int uvd_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* needed for driver unload*/</div><div class='hunk'>@@ -1785,7 +1523,6 @@ static int uvd_v7_0_set_clockgating_state(void *handle,</div><div class='ctx'> const struct amd_ip_funcs uvd_v7_0_ip_funcs = {</div><div class='ctx'> 	.name = "uvd_v7_0",</div><div class='ctx'> 	.early_init = uvd_v7_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = uvd_v7_0_sw_init,</div><div class='ctx'> 	.sw_fini = uvd_v7_0_sw_fini,</div><div class='ctx'> 	.hw_init = uvd_v7_0_hw_init,</div><div class='hunk'>@@ -1793,12 +1530,6 @@ const struct amd_ip_funcs uvd_v7_0_ip_funcs = {</div><div class='ctx'> 	.prepare_suspend = uvd_v7_0_prepare_suspend,</div><div class='ctx'> 	.suspend = uvd_v7_0_suspend,</div><div class='ctx'> 	.resume = uvd_v7_0_resume,</div><div class='del'>-	.is_idle = NULL /* uvd_v7_0_is_idle */,</div><div class='del'>-	.wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,</div><div class='del'>-	.check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,</div><div class='del'>-	.pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,</div><div class='del'>-	.soft_reset = NULL /* uvd_v7_0_soft_reset */,</div><div class='del'>-	.post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,</div><div class='ctx'> 	.set_clockgating_state = uvd_v7_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c<br/>new file mode 100644<br/>index 000000000000..9ae424618556<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vce_v1_0.c</a></div><div class='hunk'>@@ -0,0 +1,839 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2013 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2025 Valve Corporation</div><div class='add'>+ * Copyright 2025 Alexandre Demers</div><div class='add'>+ * All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the</div><div class='add'>+ * "Software"), to deal in the Software without restriction, including</div><div class='add'>+ * without limitation the rights to use, copy, modify, merge, publish,</div><div class='add'>+ * distribute, sub license, and/or sell copies of the Software, and to</div><div class='add'>+ * permit persons to whom the Software is furnished to do so, subject to</div><div class='add'>+ * the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,</div><div class='add'>+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR</div><div class='add'>+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE</div><div class='add'>+ * USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice (including the</div><div class='add'>+ * next paragraph) shall be included in all copies or substantial portions</div><div class='add'>+ * of the Software.</div><div class='add'>+ *</div><div class='add'>+ * Authors: Christian König &lt;christian.koenig@amd.com&gt;</div><div class='add'>+ *          Timur Kristóf &lt;timur.kristof@gmail.com&gt;</div><div class='add'>+ *          Alexandre Demers &lt;alexandre.f.demers@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_vce.h"</div><div class='add'>+#include "amdgpu_gart.h"</div><div class='add'>+#include "sid.h"</div><div class='add'>+#include "vce_v1_0.h"</div><div class='add'>+#include "vce/vce_1_0_d.h"</div><div class='add'>+#include "vce/vce_1_0_sh_mask.h"</div><div class='add'>+#include "oss/oss_1_0_d.h"</div><div class='add'>+#include "oss/oss_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#define VCE_V1_0_FW_SIZE	(256 * 1024)</div><div class='add'>+#define VCE_V1_0_STACK_SIZE	(64 * 1024)</div><div class='add'>+#define VCE_V1_0_DATA_SIZE	(7808 * (AMDGPU_MAX_VCE_HANDLES + 1))</div><div class='add'>+#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK	0x02</div><div class='add'>+</div><div class='add'>+#define VCE_V1_0_GART_PAGE_START \</div><div class='add'>+	(AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS)</div><div class='add'>+#define VCE_V1_0_GART_ADDR_START \</div><div class='add'>+	(VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE)</div><div class='add'>+</div><div class='add'>+static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+struct vce_v1_0_fw_signature {</div><div class='add'>+	int32_t offset;</div><div class='add'>+	uint32_t length;</div><div class='add'>+	int32_t number;</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t chip_id;</div><div class='add'>+		uint32_t keyselect;</div><div class='add'>+		uint32_t nonce[4];</div><div class='add'>+		uint32_t sigval[4];</div><div class='add'>+	} val[8];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_ring_get_rptr - get read pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the current hardware read pointer</div><div class='add'>+ */</div><div class='add'>+static uint64_t vce_v1_0_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me == 0)</div><div class='add'>+		return RREG32(mmVCE_RB_RPTR);</div><div class='add'>+	else</div><div class='add'>+		return RREG32(mmVCE_RB_RPTR2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_ring_get_wptr - get write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the current hardware write pointer</div><div class='add'>+ */</div><div class='add'>+static uint64_t vce_v1_0_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me == 0)</div><div class='add'>+		return RREG32(mmVCE_RB_WPTR);</div><div class='add'>+	else</div><div class='add'>+		return RREG32(mmVCE_RB_WPTR2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_ring_set_wptr - set write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Commits the write pointer to the hardware</div><div class='add'>+ */</div><div class='add'>+static void vce_v1_0_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;me == 0)</div><div class='add'>+		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	else</div><div class='add'>+		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_lmi_clean(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 10; ++i) {</div><div class='add'>+		for (j = 0; j &lt; 100; ++j) {</div><div class='add'>+			if (RREG32(mmVCE_LMI_STATUS) &amp; 0x337f)</div><div class='add'>+				return 0;</div><div class='add'>+</div><div class='add'>+			mdelay(10);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_firmware_loaded(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 10; ++i) {</div><div class='add'>+		for (j = 0; j &lt; 100; ++j) {</div><div class='add'>+			if (RREG32(mmVCE_STATUS) &amp; VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)</div><div class='add'>+				return 0;</div><div class='add'>+			mdelay(10);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dev_err(adev-&gt;dev, "VCE not responding, trying to reset the ECPU\n");</div><div class='add'>+</div><div class='add'>+		WREG32_P(mmVCE_SOFT_RESET,</div><div class='add'>+			VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,</div><div class='add'>+			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+		WREG32_P(mmVCE_SOFT_RESET, 0,</div><div class='add'>+			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vce_v1_0_init_cg(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	tmp = RREG32(mmVCE_CLOCK_GATING_A);</div><div class='add'>+	tmp |= VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK;</div><div class='add'>+	WREG32(mmVCE_CLOCK_GATING_A, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32(mmVCE_CLOCK_GATING_B);</div><div class='add'>+	tmp |= 0x1e;</div><div class='add'>+	tmp &amp;= ~0xe100e1;</div><div class='add'>+	WREG32(mmVCE_CLOCK_GATING_B, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);</div><div class='add'>+	tmp &amp;= ~0xff9ff000;</div><div class='add'>+	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);</div><div class='add'>+	tmp &amp;= ~0x3ff;</div><div class='add'>+	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_load_fw_signature - load firmware signature into VCPU BO</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * The VCE1 firmware validation mechanism needs a firmware signature.</div><div class='add'>+ * This function finds the signature appropriate for the current</div><div class='add'>+ * ASIC and writes that into the VCPU BO.</div><div class='add'>+ */</div><div class='add'>+static int vce_v1_0_load_fw_signature(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	const struct common_firmware_header *hdr;</div><div class='add'>+	struct vce_v1_0_fw_signature *sign;</div><div class='add'>+	unsigned int ucode_offset;</div><div class='add'>+	uint32_t chip_id;</div><div class='add'>+	u32 *cpu_addr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vce.fw-&gt;data;</div><div class='add'>+	ucode_offset = le32_to_cpu(hdr-&gt;ucode_array_offset_bytes);</div><div class='add'>+	cpu_addr = adev-&gt;vce.cpu_addr;</div><div class='add'>+</div><div class='add'>+	sign = (void *)adev-&gt;vce.fw-&gt;data + ucode_offset;</div><div class='add'>+</div><div class='add'>+	switch (adev-&gt;asic_type) {</div><div class='add'>+	case CHIP_TAHITI:</div><div class='add'>+		chip_id = 0x01000014;</div><div class='add'>+		break;</div><div class='add'>+	case CHIP_VERDE:</div><div class='add'>+		chip_id = 0x01000015;</div><div class='add'>+		break;</div><div class='add'>+	case CHIP_PITCAIRN:</div><div class='add'>+		chip_id = 0x01000016;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "asic_type %#010x was not found!", adev-&gt;asic_type);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; le32_to_cpu(sign-&gt;number); ++i) {</div><div class='add'>+		if (le32_to_cpu(sign-&gt;val[i].chip_id) == chip_id)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i == le32_to_cpu(sign-&gt;number)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "chip_id 0x%x for %s was not found in VCE firmware",</div><div class='add'>+			chip_id, amdgpu_asic_name[adev-&gt;asic_type]);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cpu_addr += (256 - 64) / 4;</div><div class='add'>+	memcpy_toio(&amp;cpu_addr[0], &amp;sign-&gt;val[i].nonce[0], 16);</div><div class='add'>+	cpu_addr[4] = cpu_to_le32(le32_to_cpu(sign-&gt;length) + 64);</div><div class='add'>+</div><div class='add'>+	memset_io(&amp;cpu_addr[5], 0, 44);</div><div class='add'>+	memcpy_toio(&amp;cpu_addr[16], &amp;sign[1], hdr-&gt;ucode_size_bytes - sizeof(*sign));</div><div class='add'>+</div><div class='add'>+	cpu_addr += (le32_to_cpu(sign-&gt;length) + 64) / 4;</div><div class='add'>+	memcpy_toio(&amp;cpu_addr[0], &amp;sign-&gt;val[i].sigval[0], 16);</div><div class='add'>+</div><div class='add'>+	adev-&gt;vce.keyselect = le32_to_cpu(sign-&gt;val[i].keyselect);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_wait_for_fw_validation(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	dev_dbg(adev-&gt;dev, "VCE keyselect: %d", adev-&gt;vce.keyselect);</div><div class='add'>+	WREG32(mmVCE_LMI_FW_START_KEYSEL, adev-&gt;vce.keyselect);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 10; ++i) {</div><div class='add'>+		mdelay(10);</div><div class='add'>+		if (RREG32(mmVCE_FW_REG_STATUS) &amp; VCE_FW_REG_STATUS__DONE_MASK)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!(RREG32(mmVCE_FW_REG_STATUS) &amp; VCE_FW_REG_STATUS__DONE_MASK)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCE FW validation timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!(RREG32(mmVCE_FW_REG_STATUS) &amp; VCE_FW_REG_STATUS__PASS_MASK)) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCE FW validation failed\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 10; ++i) {</div><div class='add'>+		mdelay(10);</div><div class='add'>+		if (!(RREG32(mmVCE_FW_REG_STATUS) &amp; VCE_FW_REG_STATUS__BUSY_MASK))</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (RREG32(mmVCE_FW_REG_STATUS) &amp; VCE_FW_REG_STATUS__BUSY_MASK) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCE FW busy timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_mc_resume(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t offset;</div><div class='add'>+	uint32_t size;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * When the keyselect is already set, don't perturb VCE FW.</div><div class='add'>+	 * Validation seems to always fail the second time.</div><div class='add'>+	 */</div><div class='add'>+	if (RREG32(mmVCE_LMI_FW_START_KEYSEL)) {</div><div class='add'>+		dev_dbg(adev-&gt;dev, "keyselect already set: 0x%x (on CPU: 0x%x)\n",</div><div class='add'>+			RREG32(mmVCE_LMI_FW_START_KEYSEL), adev-&gt;vce.keyselect);</div><div class='add'>+</div><div class='add'>+		WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 &lt;&lt; 16));</div><div class='add'>+	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);</div><div class='add'>+	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);</div><div class='add'>+	WREG32(mmVCE_CLOCK_GATING_B, 0);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);</div><div class='add'>+</div><div class='add'>+	WREG32(mmVCE_LMI_CTRL, 0x00398000);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);</div><div class='add'>+	WREG32(mmVCE_LMI_SWAP_CNTL, 0);</div><div class='add'>+	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);</div><div class='add'>+	WREG32(mmVCE_LMI_VM_CTRL, 0);</div><div class='add'>+</div><div class='add'>+	WREG32(mmVCE_VCPU_SCRATCH7, AMDGPU_MAX_VCE_HANDLES);</div><div class='add'>+</div><div class='add'>+	offset =  adev-&gt;vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET;</div><div class='add'>+	size = VCE_V1_0_FW_SIZE;</div><div class='add'>+	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset &amp; 0x7fffffff);</div><div class='add'>+	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);</div><div class='add'>+</div><div class='add'>+	offset += size;</div><div class='add'>+	size = VCE_V1_0_STACK_SIZE;</div><div class='add'>+	WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset &amp; 0x7fffffff);</div><div class='add'>+	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);</div><div class='add'>+</div><div class='add'>+	offset += size;</div><div class='add'>+	size = VCE_V1_0_DATA_SIZE;</div><div class='add'>+	WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset &amp; 0x7fffffff);</div><div class='add'>+	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);</div><div class='add'>+</div><div class='add'>+	return vce_v1_0_wait_for_fw_validation(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_is_idle() - Check idle status of VCE1 IP block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: amdgpu_ip_block pointer</div><div class='add'>+ *</div><div class='add'>+ * Check whether VCE is busy according to VCE_STATUS.</div><div class='add'>+ * Also check whether the SRBM thinks VCE is busy, although</div><div class='add'>+ * SRBM_STATUS.VCE_BUSY seems to be bogus because it</div><div class='add'>+ * appears to mirror the VCE_STATUS.VCPU_REPORT_FW_LOADED bit.</div><div class='add'>+ */</div><div class='add'>+static bool vce_v1_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool busy =</div><div class='add'>+		(RREG32(mmVCE_STATUS) &amp; (VCE_STATUS__JOB_BUSY_MASK | VCE_STATUS__UENC_BUSY_MASK)) ||</div><div class='add'>+		(RREG32(mmSRBM_STATUS2) &amp; SRBM_STATUS2__VCE_BUSY_MASK);</div><div class='add'>+</div><div class='add'>+	return !busy;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		udelay(1);</div><div class='add'>+		if (vce_v1_0_is_idle(ip_block))</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_start - start VCE block</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Setup and start the VCE block</div><div class='add'>+ */</div><div class='add'>+static int vce_v1_0_start(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_STATUS, 1, ~1);</div><div class='add'>+</div><div class='add'>+	r = vce_v1_0_mc_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;vce.ring[0];</div><div class='add'>+	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32(mmVCE_RB_BASE_LO, lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32(mmVCE_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;vce.ring[1];</div><div class='add'>+	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32(mmVCE_RB_BASE_LO2, lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32(mmVCE_RB_SIZE2, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,</div><div class='add'>+		 ~VCE_VCPU_CNTL__CLK_EN_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_SOFT_RESET,</div><div class='add'>+		VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |</div><div class='add'>+		VCE_SOFT_RESET__FME_SOFT_RESET_MASK,</div><div class='add'>+		~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |</div><div class='add'>+		  VCE_SOFT_RESET__FME_SOFT_RESET_MASK));</div><div class='add'>+</div><div class='add'>+	mdelay(100);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_SOFT_RESET, 0,</div><div class='add'>+		~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |</div><div class='add'>+		  VCE_SOFT_RESET__FME_SOFT_RESET_MASK));</div><div class='add'>+</div><div class='add'>+	r = vce_v1_0_firmware_loaded(adev);</div><div class='add'>+</div><div class='add'>+	/* Clear VCE_STATUS, otherwise SRBM thinks VCE1 is busy. */</div><div class='add'>+	WREG32(mmVCE_STATUS, 0);</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCE not responding, giving up\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_stop(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='add'>+	int status;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (vce_v1_0_lmi_clean(adev))</div><div class='add'>+		dev_warn(adev-&gt;dev, "VCE not idle\n");</div><div class='add'>+</div><div class='add'>+	if (vce_v1_0_wait_for_idle(ip_block))</div><div class='add'>+		dev_warn(adev-&gt;dev, "VCE busy: VCE_STATUS=0x%x, SRBM_STATUS2=0x%x\n",</div><div class='add'>+			RREG32(mmVCE_STATUS), RREG32(mmSRBM_STATUS2));</div><div class='add'>+</div><div class='add'>+	/* Stall UMC and register bus before resetting VCPU */</div><div class='add'>+	WREG32_P(mmVCE_LMI_CTRL2, 1 &lt;&lt; 8, ~(1 &lt;&lt; 8));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 100; ++i) {</div><div class='add'>+		status = RREG32(mmVCE_LMI_STATUS);</div><div class='add'>+		if (status &amp; 0x240)</div><div class='add'>+			break;</div><div class='add'>+		mdelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_SOFT_RESET,</div><div class='add'>+		VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |</div><div class='add'>+		VCE_SOFT_RESET__FME_SOFT_RESET_MASK,</div><div class='add'>+		~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |</div><div class='add'>+		  VCE_SOFT_RESET__FME_SOFT_RESET_MASK));</div><div class='add'>+</div><div class='add'>+	WREG32(mmVCE_STATUS, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 tmp;</div><div class='add'>+</div><div class='add'>+	if (enable &amp;&amp; (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCE_MGCG)) {</div><div class='add'>+		tmp = RREG32(mmVCE_CLOCK_GATING_A);</div><div class='add'>+		tmp |= VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK;</div><div class='add'>+		WREG32(mmVCE_CLOCK_GATING_A, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);</div><div class='add'>+		tmp &amp;= ~0x1ff000;</div><div class='add'>+		tmp |= 0xff800000;</div><div class='add'>+		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);</div><div class='add'>+		tmp &amp;= ~0x3ff;</div><div class='add'>+		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);</div><div class='add'>+	} else {</div><div class='add'>+		tmp = RREG32(mmVCE_CLOCK_GATING_A);</div><div class='add'>+		tmp &amp;= ~VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK;</div><div class='add'>+		WREG32(mmVCE_CLOCK_GATING_A, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);</div><div class='add'>+		tmp |= 0x1ff000;</div><div class='add'>+		tmp &amp;= ~0xff800000;</div><div class='add'>+		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);</div><div class='add'>+</div><div class='add'>+		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);</div><div class='add'>+		tmp |= 0x3ff;</div><div class='add'>+		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_early_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vce.num_rings = 2;</div><div class='add'>+</div><div class='add'>+	vce_v1_0_set_ring_funcs(adev);</div><div class='add'>+	vce_v1_0_set_irq_funcs(adev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_ensure_vcpu_bo_32bit_addr() - ensure the VCPU BO has a 32-bit address</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Due to various hardware limitations, the VCE1 requires</div><div class='add'>+ * the VCPU BO to be in the low 32 bit address range.</div><div class='add'>+ * Ensure that the VCPU BO has a 32-bit GPU address,</div><div class='add'>+ * or return an error code when that isn't possible.</div><div class='add'>+ *</div><div class='add'>+ * To accomodate that, we put GART to the LOW address range</div><div class='add'>+ * and reserve some GART pages where we map the VCPU BO,</div><div class='add'>+ * so that it gets a 32-bit address.</div><div class='add'>+ */</div><div class='add'>+static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	u64 gpu_addr = amdgpu_bo_gpu_offset(adev-&gt;vce.vcpu_bo);</div><div class='add'>+	u64 bo_size = amdgpu_bo_size(adev-&gt;vce.vcpu_bo);</div><div class='add'>+	u64 max_vcpu_bo_addr = 0xffffffff - bo_size;</div><div class='add'>+	u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE;</div><div class='add'>+	u64 pa = amdgpu_gmc_vram_pa(adev, adev-&gt;vce.vcpu_bo);</div><div class='add'>+	u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check if the VCPU BO already has a 32-bit address.</div><div class='add'>+	 * Eg. if MC is configured to put VRAM in the low address range.</div><div class='add'>+	 */</div><div class='add'>+	if (gpu_addr &lt;= max_vcpu_bo_addr)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Check if we can map the VCPU BO in GART to a 32-bit address. */</div><div class='add'>+	if (adev-&gt;gmc.gart_start + VCE_V1_0_GART_ADDR_START &gt; max_vcpu_bo_addr)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START,</div><div class='add'>+				   num_pages, flags, adev-&gt;gart.ptr);</div><div class='add'>+	adev-&gt;vce.gpu_addr = adev-&gt;gmc.gart_start + VCE_V1_0_GART_ADDR_START;</div><div class='add'>+	if (adev-&gt;vce.gpu_addr &gt; max_vcpu_bo_addr)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int r, i;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &amp;adev-&gt;vce.irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_sw_init(adev, VCE_V1_0_FW_SIZE +</div><div class='add'>+		VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = vce_v1_0_load_fw_signature(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vce.num_rings; i++) {</div><div class='add'>+		enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i);</div><div class='add'>+</div><div class='add'>+		ring = &amp;adev-&gt;vce.ring[i];</div><div class='add'>+		sprintf(ring-&gt;name, "vce%d", i);</div><div class='add'>+		r = amdgpu_ring_init(adev, ring, 512, &amp;adev-&gt;vce.irq, 0,</div><div class='add'>+				     hw_prio, NULL);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_suspend(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_vce_sw_fini(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vce_v1_0_hw_init - start and test VCE block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Initialize the hardware, boot up the VCPU and do some testing</div><div class='add'>+ */</div><div class='add'>+static int vce_v1_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;pm.dpm_enabled)</div><div class='add'>+		amdgpu_dpm_enable_vce(adev, true);</div><div class='add'>+	else</div><div class='add'>+		amdgpu_asic_set_vce_clocks(adev, 10000, 10000);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vce.num_rings; i++) {</div><div class='add'>+		r = amdgpu_ring_test_helper(&amp;adev-&gt;vce.ring[i]);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_info(adev-&gt;dev, "VCE initialized successfully.\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = vce_v1_0_stop(ip_block-&gt;adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;ip_block-&gt;adev-&gt;vce.idle_work);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Proper cleanups before halting the HW engine:</div><div class='add'>+	 *   - cancel the delayed idle work</div><div class='add'>+	 *   - enable powergating</div><div class='add'>+	 *   - enable clockgating</div><div class='add'>+	 *   - disable dpm</div><div class='add'>+	 *</div><div class='add'>+	 * TODO: to align with the VCN implementation, move the</div><div class='add'>+	 * jobs for clockgating/powergating/dpm setting to</div><div class='add'>+	 * -&gt;set_powergating_state().</div><div class='add'>+	 */</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;vce.idle_work);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;pm.dpm_enabled) {</div><div class='add'>+		amdgpu_dpm_enable_vce(adev, false);</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_asic_set_vce_clocks(adev, 0, 0);</div><div class='add'>+		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,</div><div class='add'>+						       AMD_PG_STATE_GATE);</div><div class='add'>+		amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,</div><div class='add'>+						       AMD_CG_STATE_GATE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = vce_v1_0_hw_fini(ip_block);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "vce_v1_0_hw_fini() failed with error %i", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_vce_suspend(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_resume(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = vce_v1_0_load_fw_signature(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return vce_v1_0_hw_init(ip_block);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_set_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_irq_src *source,</div><div class='add'>+					unsigned int type,</div><div class='add'>+					enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	uint32_t val = 0;</div><div class='add'>+</div><div class='add'>+	if (state == AMDGPU_IRQ_STATE_ENABLE)</div><div class='add'>+		val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;</div><div class='add'>+</div><div class='add'>+	WREG32_P(mmVCE_SYS_INT_EN, val,</div><div class='add'>+		 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_process_interrupt(struct amdgpu_device *adev,</div><div class='add'>+				      struct amdgpu_irq_src *source,</div><div class='add'>+				      struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	dev_dbg(adev-&gt;dev, "IH: VCE\n");</div><div class='add'>+	switch (entry-&gt;src_data[0]) {</div><div class='add'>+	case 0:</div><div class='add'>+	case 1:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;vce.ring[entry-&gt;src_data[0]]);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(adev-&gt;dev, "Unhandled interrupt: %d %d\n",</div><div class='add'>+			  entry-&gt;src_id, entry-&gt;src_data[0]);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					  enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	vce_v1_0_init_cg(adev);</div><div class='add'>+	vce_v1_0_enable_mgcg(adev, state == AMD_CG_STATE_GATE);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vce_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					  enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This doesn't actually powergate the VCE block.</div><div class='add'>+	 * That's done in the dpm code via the SMC.  This</div><div class='add'>+	 * just re-inits the block as necessary.  The actual</div><div class='add'>+	 * gating still happens in the dpm code.  We should</div><div class='add'>+	 * revisit this when there is a cleaner line between</div><div class='add'>+	 * the smc and the hw blocks</div><div class='add'>+	 */</div><div class='add'>+	if (state == AMD_PG_STATE_GATE)</div><div class='add'>+		return vce_v1_0_stop(adev);</div><div class='add'>+	else</div><div class='add'>+		return vce_v1_0_start(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs vce_v1_0_ip_funcs = {</div><div class='add'>+	.name = "vce_v1_0",</div><div class='add'>+	.early_init = vce_v1_0_early_init,</div><div class='add'>+	.sw_init = vce_v1_0_sw_init,</div><div class='add'>+	.sw_fini = vce_v1_0_sw_fini,</div><div class='add'>+	.hw_init = vce_v1_0_hw_init,</div><div class='add'>+	.hw_fini = vce_v1_0_hw_fini,</div><div class='add'>+	.suspend = vce_v1_0_suspend,</div><div class='add'>+	.resume = vce_v1_0_resume,</div><div class='add'>+	.is_idle = vce_v1_0_is_idle,</div><div class='add'>+	.wait_for_idle = vce_v1_0_wait_for_idle,</div><div class='add'>+	.set_clockgating_state = vce_v1_0_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = vce_v1_0_set_powergating_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs vce_v1_0_ring_funcs = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_VCE,</div><div class='add'>+	.align_mask = 0xf,</div><div class='add'>+	.nop = VCE_CMD_NO_OP,</div><div class='add'>+	.support_64bit_ptrs = false,</div><div class='add'>+	.no_user_fence = true,</div><div class='add'>+	.get_rptr = vce_v1_0_ring_get_rptr,</div><div class='add'>+	.get_wptr = vce_v1_0_ring_get_wptr,</div><div class='add'>+	.set_wptr = vce_v1_0_ring_set_wptr,</div><div class='add'>+	.parse_cs = amdgpu_vce_ring_parse_cs,</div><div class='add'>+	.emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence  x1 no user fence */</div><div class='add'>+	.emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */</div><div class='add'>+	.emit_ib = amdgpu_vce_ring_emit_ib,</div><div class='add'>+	.emit_fence = amdgpu_vce_ring_emit_fence,</div><div class='add'>+	.test_ring = amdgpu_vce_ring_test_ring,</div><div class='add'>+	.test_ib = amdgpu_vce_ring_test_ib,</div><div class='add'>+	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='add'>+	.begin_use = amdgpu_vce_ring_begin_use,</div><div class='add'>+	.end_use = amdgpu_vce_ring_end_use,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vce.num_rings; i++) {</div><div class='add'>+		adev-&gt;vce.ring[i].funcs = &amp;vce_v1_0_ring_funcs;</div><div class='add'>+		adev-&gt;vce.ring[i].me = i;</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs vce_v1_0_irq_funcs = {</div><div class='add'>+	.set = vce_v1_0_set_interrupt_state,</div><div class='add'>+	.process = vce_v1_0_process_interrupt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;vce.irq.num_types = 1;</div><div class='add'>+	adev-&gt;vce.irq.funcs = &amp;vce_v1_0_irq_funcs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version vce_v1_0_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_VCE,</div><div class='add'>+	.major = 1,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 0,</div><div class='add'>+	.funcs = &amp;vce_v1_0_ip_funcs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h<br/>new file mode 100644<br/>index 000000000000..206e7bec897f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vce_v1_0.h</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2025 Valve Corporation</div><div class='add'>+ * Copyright 2025 Alexandre Demers</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __VCE_V1_0_H__</div><div class='add'>+#define __VCE_V1_0_H__</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_ip_block_version vce_v1_0_ip_block;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c<br/>index a08e7abca423..8ea8a6193492 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v2_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vce_v2_0.c</a></div><div class='hunk'>@@ -201,20 +201,20 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vce_v2_0_is_idle(void *handle)</div><div class='add'>+static bool vce_v2_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return !(RREG32(mmSRBM_STATUS2) &amp; SRBM_STATUS2__VCE_BUSY_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_wait_for_idle(void *handle)</div><div class='add'>+static int vce_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='del'>-		if (vce_v2_0_is_idle(handle))</div><div class='add'>+		if (vce_v2_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='hunk'>@@ -274,15 +274,21 @@ static int vce_v2_0_start(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static int vce_v2_0_stop(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> 	if (vce_v2_0_lmi_clean(adev)) {</div><div class='del'>-		DRM_INFO("vce is not idle \n");</div><div class='add'>+		DRM_INFO("VCE is not idle \n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vce_v2_0_wait_for_idle(adev)) {</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (vce_v2_0_wait_for_idle(ip_block)) {</div><div class='ctx'> 		DRM_INFO("VCE is busy, Can't set clock gating");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -398,9 +404,14 @@ static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_early_init(void *handle)</div><div class='add'>+static int vce_v2_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_early_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;vce.num_rings = 2;</div><div class='ctx'> </div><div class='hunk'>@@ -410,11 +421,11 @@ static int vce_v2_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_sw_init(void *handle)</div><div class='add'>+static int vce_v2_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* VCE */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &amp;adev-&gt;vce.irq);</div><div class='hunk'>@@ -444,10 +455,10 @@ static int vce_v2_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_sw_fini(void *handle)</div><div class='add'>+static int vce_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_vce_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -456,10 +467,10 @@ static int vce_v2_0_sw_fini(void *handle)</div><div class='ctx'> 	return amdgpu_vce_sw_fini(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_hw_init(void *handle)</div><div class='add'>+static int vce_v2_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);</div><div class='ctx'> 	vce_v2_0_enable_mgcg(adev, true, false);</div><div class='hunk'>@@ -475,19 +486,17 @@ static int vce_v2_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_hw_fini(void *handle)</div><div class='add'>+static int vce_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vce.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;ip_block-&gt;adev-&gt;vce.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_suspend(void *handle)</div><div class='add'>+static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -513,28 +522,27 @@ static int vce_v2_0_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = vce_v2_0_hw_fini(adev);</div><div class='add'>+	r = vce_v2_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_vce_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_resume(void *handle)</div><div class='add'>+static int vce_v2_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vce_resume(adev);</div><div class='add'>+	r = amdgpu_vce_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return vce_v2_0_hw_init(adev);</div><div class='add'>+	return vce_v2_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_soft_reset(void *handle)</div><div class='add'>+static int vce_v2_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);</div><div class='ctx'> 	mdelay(5);</div><div class='hunk'>@@ -575,13 +583,13 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vce_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	bool gate = false;</div><div class='ctx'> 	bool sw_cg = false;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_CG_STATE_GATE) {</div><div class='ctx'> 		gate = true;</div><div class='hunk'>@@ -593,7 +601,7 @@ static int vce_v2_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v2_0_set_powergating_state(void *handle,</div><div class='add'>+static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the VCE block.</div><div class='hunk'>@@ -603,7 +611,7 @@ static int vce_v2_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * revisit this when there is a cleaner line between</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='ctx'> 		return vce_v2_0_stop(adev);</div><div class='hunk'>@@ -614,7 +622,6 @@ static int vce_v2_0_set_powergating_state(void *handle,</div><div class='ctx'> static const struct amd_ip_funcs vce_v2_0_ip_funcs = {</div><div class='ctx'> 	.name = "vce_v2_0",</div><div class='ctx'> 	.early_init = vce_v2_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vce_v2_0_sw_init,</div><div class='ctx'> 	.sw_fini = vce_v2_0_sw_fini,</div><div class='ctx'> 	.hw_init = vce_v2_0_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br/>index f4760748d349..719e9643c43d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v3_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vce_v3_0.c</a></div><div class='hunk'>@@ -64,8 +64,8 @@</div><div class='ctx'> static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);</div><div class='ctx'> static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vce_v3_0_wait_for_idle(void *handle);</div><div class='del'>-static int vce_v3_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block);</div><div class='add'>+static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state);</div><div class='ctx'> /**</div><div class='ctx'>  * vce_v3_0_ring_get_rptr - get read pointer</div><div class='hunk'>@@ -396,9 +396,10 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_early_init(void *handle)</div><div class='add'>+static int vce_v3_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;vce.harvest_config = vce_v3_0_get_harvest_config(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -407,6 +408,10 @@ static int vce_v3_0_early_init(void *handle)</div><div class='ctx'> 	    (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_vce_early_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;vce.num_rings = 3;</div><div class='ctx'> </div><div class='ctx'> 	vce_v3_0_set_ring_funcs(adev);</div><div class='hunk'>@@ -415,9 +420,9 @@ static int vce_v3_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_sw_init(void *handle)</div><div class='add'>+static int vce_v3_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int r, i;</div><div class='ctx'> </div><div class='hunk'>@@ -453,10 +458,10 @@ static int vce_v3_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_sw_fini(void *handle)</div><div class='add'>+static int vce_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_vce_suspend(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -465,10 +470,10 @@ static int vce_v3_0_sw_fini(void *handle)</div><div class='ctx'> 	return amdgpu_vce_sw_fini(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_hw_init(void *handle)</div><div class='add'>+static int vce_v3_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	vce_v3_0_override_vce_clock_gating(adev, true);</div><div class='ctx'> </div><div class='hunk'>@@ -485,25 +490,25 @@ static int vce_v3_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_hw_fini(void *handle)</div><div class='add'>+static int vce_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;vce.idle_work);</div><div class='ctx'> </div><div class='del'>-	r = vce_v3_0_wait_for_idle(handle);</div><div class='add'>+	r = vce_v3_0_wait_for_idle(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	vce_v3_0_stop(adev);</div><div class='del'>-	return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);</div><div class='add'>+	return vce_v3_0_set_clockgating_state(ip_block, AMD_CG_STATE_GATE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_suspend(void *handle)</div><div class='add'>+static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Proper cleanups before halting the HW engine:</div><div class='hunk'>@@ -528,23 +533,22 @@ static int vce_v3_0_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = vce_v3_0_hw_fini(adev);</div><div class='add'>+	r = vce_v3_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_vce_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_resume(void *handle)</div><div class='add'>+static int vce_v3_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vce_resume(adev);</div><div class='add'>+	r = amdgpu_vce_resume(ip_block-&gt;adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	return vce_v3_0_hw_init(adev);</div><div class='add'>+	return vce_v3_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)</div><div class='hunk'>@@ -598,9 +602,9 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)</div><div class='ctx'> 	WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vce_v3_0_is_idle(void *handle)</div><div class='add'>+static bool vce_v3_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 mask = 0;</div><div class='ctx'> </div><div class='ctx'> 	mask |= (adev-&gt;vce.harvest_config &amp; AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;</div><div class='hunk'>@@ -609,13 +613,13 @@ static bool vce_v3_0_is_idle(void *handle)</div><div class='ctx'> 	return !(RREG32(mmSRBM_STATUS2) &amp; mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_wait_for_idle(void *handle)</div><div class='add'>+static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++)</div><div class='del'>-		if (vce_v3_0_is_idle(handle))</div><div class='add'>+		if (vce_v3_0_is_idle(ip_block))</div><div class='ctx'> 			return 0;</div><div class='ctx'> </div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='hunk'>@@ -627,9 +631,9 @@ static int vce_v3_0_wait_for_idle(void *handle)</div><div class='ctx'> #define  AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \</div><div class='ctx'> 				      VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)</div><div class='ctx'> </div><div class='del'>-static bool vce_v3_0_check_soft_reset(void *handle)</div><div class='add'>+static bool vce_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* According to VCE team , we should use VCE_STATUS instead</div><div class='hunk'>@@ -668,9 +672,9 @@ static bool vce_v3_0_check_soft_reset(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_soft_reset(void *handle)</div><div class='add'>+static int vce_v3_0_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	u32 srbm_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;vce.srbm_soft_reset)</div><div class='hunk'>@@ -699,29 +703,29 @@ static int vce_v3_0_soft_reset(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_pre_soft_reset(void *handle)</div><div class='add'>+static int vce_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;vce.srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	mdelay(5);</div><div class='ctx'> </div><div class='del'>-	return vce_v3_0_suspend(adev);</div><div class='add'>+	return vce_v3_0_suspend(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_post_soft_reset(void *handle)</div><div class='add'>+static int vce_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;vce.srbm_soft_reset)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	mdelay(5);</div><div class='ctx'> </div><div class='del'>-	return vce_v3_0_resume(adev);</div><div class='add'>+	return vce_v3_0_resume(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,</div><div class='hunk'>@@ -761,10 +765,10 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -802,7 +806,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v3_0_set_powergating_state(void *handle,</div><div class='add'>+static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the VCE block.</div><div class='hunk'>@@ -812,7 +816,7 @@ static int vce_v3_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * revisit this when there is a cleaner line between</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE) {</div><div class='hunk'>@@ -829,9 +833,9 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vce_v3_0_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void vce_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;pm.mutex);</div><div class='hunk'>@@ -897,7 +901,6 @@ static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)</div><div class='ctx'> static const struct amd_ip_funcs vce_v3_0_ip_funcs = {</div><div class='ctx'> 	.name = "vce_v3_0",</div><div class='ctx'> 	.early_init = vce_v3_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vce_v3_0_sw_init,</div><div class='ctx'> 	.sw_fini = vce_v3_0_sw_fini,</div><div class='ctx'> 	.hw_init = vce_v3_0_hw_init,</div><div class='hunk'>@@ -948,7 +951,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = vce_v3_0_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = vce_v3_0_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = vce_v3_0_ring_set_wptr,</div><div class='del'>-	.parse_cs = amdgpu_vce_ring_parse_cs_vm,</div><div class='add'>+	.patch_cs_in_place = amdgpu_vce_ring_parse_cs_vm,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		6 + /* vce_v3_0_emit_vm_flush */</div><div class='ctx'> 		4 + /* vce_v3_0_emit_pipeline_sync */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c<br/>index 06d787385ad4..2d64002bed61 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vce_v4_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vce_v4_0.c</a></div><div class='hunk'>@@ -407,9 +407,14 @@ static int vce_v4_0_stop(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_early_init(void *handle)</div><div class='add'>+static int vce_v4_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vce_early_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) /* currently only VCN0 support SRIOV */</div><div class='ctx'> 		adev-&gt;vce.num_rings = 1;</div><div class='hunk'>@@ -422,9 +427,9 @@ static int vce_v4_0_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_sw_init(void *handle)</div><div class='add'>+static int vce_v4_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> </div><div class='ctx'> 	unsigned size;</div><div class='hunk'>@@ -493,10 +498,10 @@ static int vce_v4_0_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_sw_fini(void *handle)</div><div class='add'>+static int vce_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* free MM table */</div><div class='ctx'> 	amdgpu_virt_free_mm_table(adev);</div><div class='hunk'>@@ -513,10 +518,10 @@ static int vce_v4_0_sw_fini(void *handle)</div><div class='ctx'> 	return amdgpu_vce_sw_fini(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_hw_init(void *handle)</div><div class='add'>+static int vce_v4_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		r = vce_v4_0_sriov_start(adev);</div><div class='hunk'>@@ -536,14 +541,14 @@ static int vce_v4_0_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_hw_fini(void *handle)</div><div class='add'>+static int vce_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;adev-&gt;vce.idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-		/* vce_v4_0_wait_for_idle(handle); */</div><div class='add'>+		/* vce_v4_0_wait_for_idle(ip_block); */</div><div class='ctx'> 		vce_v4_0_stop(adev);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* full access mode, so don't touch any VCE register */</div><div class='hunk'>@@ -553,9 +558,9 @@ static int vce_v4_0_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_suspend(void *handle)</div><div class='add'>+static int vce_v4_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;vce.vcpu_bo == NULL)</div><div class='hunk'>@@ -594,16 +599,16 @@ static int vce_v4_0_suspend(void *handle)</div><div class='ctx'> 						       AMD_CG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = vce_v4_0_hw_fini(adev);</div><div class='add'>+	r = vce_v4_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_vce_suspend(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_resume(void *handle)</div><div class='add'>+static int vce_v4_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;vce.vcpu_bo == NULL)</div><div class='hunk'>@@ -624,7 +629,7 @@ static int vce_v4_0_resume(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return vce_v4_0_hw_init(adev);</div><div class='add'>+	return vce_v4_0_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vce_v4_0_mc_resume(struct amdgpu_device *adev)</div><div class='hunk'>@@ -684,281 +689,14 @@ static void vce_v4_0_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> 			~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vce_v4_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* needed for driver unload*/</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#if 0</div><div class='del'>-static bool vce_v4_0_is_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 mask = 0;</div><div class='del'>-</div><div class='del'>-	mask |= (adev-&gt;vce.harvest_config &amp; AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;</div><div class='del'>-	mask |= (adev-&gt;vce.harvest_config &amp; AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;</div><div class='del'>-</div><div class='del'>-	return !(RREG32(mmSRBM_STATUS2) &amp; mask);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vce_v4_0_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	unsigned i;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;usec_timeout; i++)</div><div class='del'>-		if (vce_v4_0_is_idle(handle))</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='del'>-	return -ETIMEDOUT;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#define  VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK  0x00000008L   /* AUTO_BUSY */</div><div class='del'>-#define  VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK   0x00000010L   /* RB0_BUSY */</div><div class='del'>-#define  VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK   0x00000020L   /* RB1_BUSY */</div><div class='del'>-#define  AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \</div><div class='del'>-				      VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)</div><div class='del'>-</div><div class='del'>-static bool vce_v4_0_check_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 srbm_soft_reset = 0;</div><div class='del'>-</div><div class='del'>-	/* According to VCE team , we should use VCE_STATUS instead</div><div class='del'>-	 * SRBM_STATUS.VCE_BUSY bit for busy status checking.</div><div class='del'>-	 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE</div><div class='del'>-	 * instance's registers are accessed</div><div class='del'>-	 * (0 for 1st instance, 10 for 2nd instance).</div><div class='del'>-	 *</div><div class='del'>-	 *VCE_STATUS</div><div class='del'>-	 *|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 |          |FW_LOADED|JOB |</div><div class='del'>-	 *|----+----+-----------+----+----+----+----------+---------+----|</div><div class='del'>-	 *|bit8|bit7|    bit6   |bit5|bit4|bit3|   bit2   |  bit1   |bit0|</div><div class='del'>-	 *</div><div class='del'>-	 * VCE team suggest use bit 3--bit 6 for busy status check</div><div class='del'>-	 */</div><div class='del'>-	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-	WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);</div><div class='del'>-	if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) &amp; AMDGPU_VCE_STATUS_BUSY_MASK) {</div><div class='del'>-		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);</div><div class='del'>-		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);</div><div class='del'>-	}</div><div class='del'>-	WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);</div><div class='del'>-	if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) &amp; AMDGPU_VCE_STATUS_BUSY_MASK) {</div><div class='del'>-		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);</div><div class='del'>-		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);</div><div class='del'>-	}</div><div class='del'>-	WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-</div><div class='del'>-	if (srbm_soft_reset) {</div><div class='del'>-		adev-&gt;vce.srbm_soft_reset = srbm_soft_reset;</div><div class='del'>-		return true;</div><div class='del'>-	} else {</div><div class='del'>-		adev-&gt;vce.srbm_soft_reset = 0;</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vce_v4_0_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	u32 srbm_soft_reset;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;vce.srbm_soft_reset)</div><div class='del'>-		return 0;</div><div class='del'>-	srbm_soft_reset = adev-&gt;vce.srbm_soft_reset;</div><div class='del'>-</div><div class='del'>-	if (srbm_soft_reset) {</div><div class='del'>-		u32 tmp;</div><div class='del'>-</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-		tmp |= srbm_soft_reset;</div><div class='del'>-		dev_info(adev-&gt;dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);</div><div class='del'>-		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-</div><div class='del'>-		udelay(50);</div><div class='del'>-</div><div class='del'>-		tmp &amp;= ~srbm_soft_reset;</div><div class='del'>-		WREG32(mmSRBM_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32(mmSRBM_SOFT_RESET);</div><div class='del'>-</div><div class='del'>-		/* Wait a little for things to settle down */</div><div class='del'>-		udelay(50);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vce_v4_0_pre_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;vce.srbm_soft_reset)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	mdelay(5);</div><div class='del'>-</div><div class='del'>-	return vce_v4_0_suspend(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static int vce_v4_0_post_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;vce.srbm_soft_reset)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	mdelay(5);</div><div class='del'>-</div><div class='del'>-	return vce_v4_0_resume(adev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void vce_v4_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)</div><div class='del'>-{</div><div class='del'>-	u32 tmp, data;</div><div class='del'>-</div><div class='del'>-	tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL));</div><div class='del'>-	if (override)</div><div class='del'>-		data |= VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK;</div><div class='del'>-	else</div><div class='del'>-		data &amp;= ~VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK;</div><div class='del'>-</div><div class='del'>-	if (tmp != data)</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void vce_v4_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,</div><div class='del'>-					     bool gated)</div><div class='del'>-{</div><div class='del'>-	u32 data;</div><div class='del'>-</div><div class='del'>-	/* Set Override to disable Clock Gating */</div><div class='del'>-	vce_v4_0_override_vce_clock_gating(adev, true);</div><div class='del'>-</div><div class='del'>-	/* This function enables MGCG which is controlled by firmware.</div><div class='del'>-	   With the clocks in the gated state the core is still</div><div class='del'>-	   accessible but the firmware will throttle the clocks on the</div><div class='del'>-	   fly as necessary.</div><div class='del'>-	*/</div><div class='del'>-	if (gated) {</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));</div><div class='del'>-		data |= 0x1ff;</div><div class='del'>-		data &amp;= ~0xef0000;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));</div><div class='del'>-		data |= 0x3ff000;</div><div class='del'>-		data &amp;= ~0xffc00000;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));</div><div class='del'>-		data |= 0x2;</div><div class='del'>-		data &amp;= ~0x00010000;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));</div><div class='del'>-		data |= 0x37f;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));</div><div class='del'>-		data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |</div><div class='del'>-			VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |</div><div class='del'>-			VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |</div><div class='del'>-			0x8;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);</div><div class='del'>-	} else {</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));</div><div class='del'>-		data &amp;= ~0x80010;</div><div class='del'>-		data |= 0xe70008;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));</div><div class='del'>-		data |= 0xffc00000;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));</div><div class='del'>-		data |= 0x10000;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));</div><div class='del'>-		data &amp;= ~0xffc00000;</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);</div><div class='del'>-</div><div class='del'>-		data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));</div><div class='del'>-		data &amp;= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |</div><div class='del'>-			  VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |</div><div class='del'>-			  VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK  |</div><div class='del'>-			  0x8);</div><div class='del'>-		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);</div><div class='del'>-	}</div><div class='del'>-	vce_v4_0_override_vce_clock_gating(adev, false);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void vce_v4_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)</div><div class='del'>-{</div><div class='del'>-	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);</div><div class='del'>-</div><div class='del'>-	if (enable)</div><div class='del'>-		tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;</div><div class='del'>-	else</div><div class='del'>-		tmp &amp;= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;</div><div class='del'>-</div><div class='del'>-	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vce_v4_0_set_clockgating_state(void *handle,</div><div class='del'>-					  enum amd_clockgating_state state)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if ((adev-&gt;asic_type == CHIP_POLARIS10) ||</div><div class='del'>-		(adev-&gt;asic_type == CHIP_TONGA) ||</div><div class='del'>-		(adev-&gt;asic_type == CHIP_FIJI))</div><div class='del'>-		vce_v4_0_set_bypass_mode(adev, enable);</div><div class='del'>-</div><div class='del'>-	if (!(adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCE_MGCG))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-	for (i = 0; i &lt; 2; i++) {</div><div class='del'>-		/* Program VCE Instance 0 or 1 if not harvested */</div><div class='del'>-		if (adev-&gt;vce.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);</div><div class='del'>-</div><div class='del'>-		if (enable) {</div><div class='del'>-			/* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */</div><div class='del'>-			uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A);</div><div class='del'>-			data &amp;= ~(0xf | 0xff0);</div><div class='del'>-			data |= ((0x0 &lt;&lt; 0) | (0x04 &lt;&lt; 4));</div><div class='del'>-			WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data);</div><div class='del'>-</div><div class='del'>-			/* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */</div><div class='del'>-			data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING);</div><div class='del'>-			data &amp;= ~(0xf | 0xff0);</div><div class='del'>-			data |= ((0x0 &lt;&lt; 0) | (0x04 &lt;&lt; 4));</div><div class='del'>-			WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		vce_v4_0_set_vce_sw_clock_gating(adev, enable);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-static int vce_v4_0_set_powergating_state(void *handle,</div><div class='add'>+static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the VCE block.</div><div class='hunk'>@@ -968,7 +706,7 @@ static int vce_v4_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * revisit this when there is a cleaner line between</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='ctx'> 		return vce_v4_0_stop(adev);</div><div class='hunk'>@@ -1076,19 +814,12 @@ static int vce_v4_0_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> const struct amd_ip_funcs vce_v4_0_ip_funcs = {</div><div class='ctx'> 	.name = "vce_v4_0",</div><div class='ctx'> 	.early_init = vce_v4_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vce_v4_0_sw_init,</div><div class='ctx'> 	.sw_fini = vce_v4_0_sw_fini,</div><div class='ctx'> 	.hw_init = vce_v4_0_hw_init,</div><div class='ctx'> 	.hw_fini = vce_v4_0_hw_fini,</div><div class='ctx'> 	.suspend = vce_v4_0_suspend,</div><div class='ctx'> 	.resume = vce_v4_0_resume,</div><div class='del'>-	.is_idle = NULL /* vce_v4_0_is_idle */,</div><div class='del'>-	.wait_for_idle = NULL /* vce_v4_0_wait_for_idle */,</div><div class='del'>-	.check_soft_reset = NULL /* vce_v4_0_check_soft_reset */,</div><div class='del'>-	.pre_soft_reset = NULL /* vce_v4_0_pre_soft_reset */,</div><div class='del'>-	.soft_reset = NULL /* vce_v4_0_soft_reset */,</div><div class='del'>-	.post_soft_reset = NULL /* vce_v4_0_post_soft_reset */,</div><div class='ctx'> 	.set_clockgating_state = vce_v4_0_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = vce_v4_0_set_powergating_state,</div><div class='ctx'> };</div><div class='hunk'>@@ -1102,7 +833,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {</div><div class='ctx'> 	.get_rptr = vce_v4_0_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = vce_v4_0_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = vce_v4_0_ring_set_wptr,</div><div class='del'>-	.parse_cs = amdgpu_vce_ring_parse_cs_vm,</div><div class='add'>+	.patch_cs_in_place = amdgpu_vce_ring_parse_cs_vm,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br/>index aaceecd558cf..a316797875a8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c</a></div><div class='hunk'>@@ -45,13 +45,50 @@</div><div class='ctx'> #define mmUVD_REG_XX_MASK_1_0			0x05ac</div><div class='ctx'> #define mmUVD_REG_XX_MASK_1_0_BASE_IDX		1</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_stop(struct amdgpu_device *adev);</div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst);</div><div class='ctx'> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);</div><div class='del'>-static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-				int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v1_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state);</div><div class='add'>+static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state);</div><div class='ctx'> </div><div class='ctx'> static void vcn_v1_0_idle_work_handler(struct work_struct *work);</div><div class='ctx'> static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);</div><div class='hunk'>@@ -59,38 +96,41 @@ static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_early_init(void *handle)</div><div class='add'>+static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vcn.num_enc_rings = 2;</div><div class='add'>+	adev-&gt;vcn.inst[0].num_enc_rings = 2;</div><div class='add'>+	adev-&gt;vcn.inst[0].set_pg_state = vcn_v1_0_set_pg_state;</div><div class='ctx'> </div><div class='ctx'> 	vcn_v1_0_set_dec_ring_funcs(adev);</div><div class='ctx'> 	vcn_v1_0_set_enc_ring_funcs(adev);</div><div class='ctx'> 	vcn_v1_0_set_irq_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	jpeg_v1_0_early_init(handle);</div><div class='add'>+	jpeg_v1_0_early_init(ip_block);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	return amdgpu_vcn_early_init(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_sw_init(void *handle)</div><div class='add'>+static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);</div><div class='add'>+	uint32_t *ptr;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* VCN DEC TRAP */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='hunk'>@@ -99,23 +139,23 @@ static int vcn_v1_0_sw_init(void *handle)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	/* VCN ENC TRAP */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,</div><div class='ctx'> 					&amp;adev-&gt;vcn.inst-&gt;irq);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='add'>+	r = amdgpu_vcn_sw_init(adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	/* Override the work func */</div><div class='del'>-	adev-&gt;vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;</div><div class='add'>+	adev-&gt;vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='add'>+	amdgpu_vcn_setup_ucode(adev, 0);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='add'>+	r = amdgpu_vcn_resume(adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -127,18 +167,18 @@ static int vcn_v1_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vcn.internal.scratch9 = adev-&gt;vcn.inst-&gt;external.scratch9 =</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.scratch9 = adev-&gt;vcn.inst-&gt;external.scratch9 =</div><div class='ctx'> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);</div><div class='del'>-	adev-&gt;vcn.internal.data0 = adev-&gt;vcn.inst-&gt;external.data0 =</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.data0 = adev-&gt;vcn.inst-&gt;external.data0 =</div><div class='ctx'> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);</div><div class='del'>-	adev-&gt;vcn.internal.data1 = adev-&gt;vcn.inst-&gt;external.data1 =</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.data1 = adev-&gt;vcn.inst-&gt;external.data1 =</div><div class='ctx'> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);</div><div class='del'>-	adev-&gt;vcn.internal.cmd = adev-&gt;vcn.inst-&gt;external.cmd =</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.cmd = adev-&gt;vcn.inst-&gt;external.cmd =</div><div class='ctx'> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);</div><div class='del'>-	adev-&gt;vcn.internal.nop = adev-&gt;vcn.inst-&gt;external.nop =</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.nop = adev-&gt;vcn.inst-&gt;external.nop =</div><div class='ctx'> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);</div><div class='ctx'> </div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst-&gt;ring_enc[i];</div><div class='hunk'>@@ -150,76 +190,79 @@ static int vcn_v1_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;</div><div class='add'>+	adev-&gt;vcn.inst[0].pause_dpg_mode = vcn_v1_0_pause_dpg_mode;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_vcnfw_log) {</div><div class='del'>-		volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='add'>+		struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 		fw_shared-&gt;present_flag_0 = 0;</div><div class='ctx'> 		amdgpu_vcn_fwlog_init(adev-&gt;vcn.inst);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = jpeg_v1_0_sw_init(handle);</div><div class='add'>+	r = jpeg_v1_0_sw_init(ip_block);</div><div class='ctx'> </div><div class='add'>+	/* Allocate memory for VCN IP Dump buffer */</div><div class='add'>+	ptr = kcalloc(adev-&gt;vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	if (!ptr) {</div><div class='add'>+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");</div><div class='add'>+		adev-&gt;vcn.ip_dump = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		adev-&gt;vcn.ip_dump = ptr;</div><div class='add'>+	}</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_sw_fini(void *handle)</div><div class='add'>+static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	r = amdgpu_vcn_suspend(adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	jpeg_v1_0_sw_fini(handle);</div><div class='add'>+	jpeg_v1_0_sw_fini(ip_block);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	amdgpu_vcn_sw_fini(adev, 0);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	kfree(adev-&gt;vcn.ip_dump);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_hw_init(void *handle)</div><div class='add'>+static int vcn_v1_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto done;</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst-&gt;ring_enc[i];</div><div class='ctx'> 		r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ring = adev-&gt;jpeg.inst-&gt;ring_dec;</div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='del'>-	if (r)</div><div class='del'>-		goto done;</div><div class='del'>-</div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -227,20 +270,21 @@ done:</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_hw_fini(void *handle)</div><div class='add'>+static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = adev-&gt;vcn.inst;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='del'>-		(adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='del'>-		 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {</div><div class='del'>-		vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+	    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+	     RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {</div><div class='add'>+		vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -249,27 +293,27 @@ static int vcn_v1_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_suspend(void *handle)</div><div class='add'>+static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool idle_work_unexecuted;</div><div class='ctx'> </div><div class='del'>-	idle_work_unexecuted = cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	idle_work_unexecuted = cancel_delayed_work_sync(&amp;adev-&gt;vcn.inst[0].idle_work);</div><div class='ctx'> 	if (idle_work_unexecuted) {</div><div class='ctx'> 		if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-			amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+			amdgpu_dpm_enable_vcn(adev, false, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v1_0_hw_fini(adev);</div><div class='add'>+	r = vcn_v1_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	r = amdgpu_vcn_suspend(adev, 0);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -277,20 +321,19 @@ static int vcn_v1_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_resume(void *handle)</div><div class='add'>+static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='add'>+	r = amdgpu_vcn_resume(ip_block-&gt;adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v1_0_hw_init(adev);</div><div class='add'>+	r = vcn_v1_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -298,13 +341,14 @@ static int vcn_v1_0_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_mc_resume_spg_mode - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[0]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[0].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -369,9 +413,10 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 			adev-&gt;gfx.config.gb_addr_config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[0]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[0].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -444,12 +489,13 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v1_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	/* JPEG disable CGC */</div><div class='hunk'>@@ -570,12 +616,13 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: Pointer to the VCN instance structure</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v1_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* enable JPEG CGC */</div><div class='hunk'>@@ -639,8 +686,10 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)</div><div class='add'>+static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					   uint8_t sram_sel)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* disable JPEG CGC */</div><div class='hunk'>@@ -693,8 +742,9 @@ static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t s</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_1_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -738,8 +788,9 @@ static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_1_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -782,12 +833,13 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_start_spg_mode - start VCN block</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Setup and start the VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v1_0_start_spg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='ctx'> 	uint32_t lmi_swap_cntl;</div><div class='hunk'>@@ -796,13 +848,13 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	/* disable byte swapping */</div><div class='ctx'> 	lmi_swap_cntl = 0;</div><div class='ctx'> </div><div class='del'>-	vcn_1_0_disable_static_power_gating(adev);</div><div class='add'>+	vcn_1_0_disable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);</div><div class='ctx'> </div><div class='ctx'> 	/* disable clock gating */</div><div class='del'>-	vcn_v1_0_disable_clock_gating(adev);</div><div class='add'>+	vcn_v1_0_disable_clock_gating(vinst);</div><div class='ctx'> </div><div class='ctx'> 	/* disable interupt */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,</div><div class='hunk'>@@ -844,7 +896,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 		(0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		(0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='ctx'> </div><div class='del'>-	vcn_v1_0_mc_resume_spg_mode(adev);</div><div class='add'>+	vcn_v1_0_mc_resume_spg_mode(vinst);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);</div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,</div><div class='hunk'>@@ -957,11 +1009,17 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	jpeg_v1_0_start(adev, 0);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v1_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='ctx'> 	uint32_t lmi_swap_cntl;</div><div class='hunk'>@@ -969,7 +1027,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	/* disable byte swapping */</div><div class='ctx'> 	lmi_swap_cntl = 0;</div><div class='ctx'> </div><div class='del'>-	vcn_1_0_enable_static_power_gating(adev);</div><div class='add'>+	vcn_1_0_enable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='ctx'> 	/* enable dynamic power gating mode */</div><div class='ctx'> 	tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);</div><div class='hunk'>@@ -978,7 +1036,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v1_0_clock_gating_dpg_mode(adev, 0);</div><div class='add'>+	vcn_v1_0_clock_gating_dpg_mode(vinst, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -1027,7 +1085,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);</div><div class='ctx'> </div><div class='del'>-	vcn_v1_0_mc_resume_dpg_mode(adev);</div><div class='add'>+	vcn_v1_0_mc_resume_dpg_mode(vinst);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);</div><div class='hunk'>@@ -1044,7 +1102,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,</div><div class='ctx'> 			UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);</div><div class='ctx'> </div><div class='del'>-	vcn_v1_0_clock_gating_dpg_mode(adev, 1);</div><div class='add'>+	vcn_v1_0_clock_gating_dpg_mode(vinst, 1);</div><div class='ctx'> 	/* setup mmUVD_LMI_CTRL */</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,</div><div class='ctx'> 		(8 &lt;&lt; UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |</div><div class='hunk'>@@ -1101,24 +1159,32 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	jpeg_v1_0_start(adev, 1);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v1_0_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+</div><div class='ctx'> 	return (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ?</div><div class='del'>-		vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev);</div><div class='add'>+		vcn_v1_0_start_dpg_mode(vinst) : vcn_v1_0_start_spg_mode(vinst);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v1_0_stop_spg_mode - stop VCN block</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * stop the VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v1_0_stop_spg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	int tmp;</div><div class='ctx'> </div><div class='ctx'> 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='hunk'>@@ -1158,13 +1224,20 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-	vcn_v1_0_enable_clock_gating(adev);</div><div class='del'>-	vcn_1_0_enable_static_power_gating(adev);</div><div class='add'>+	vcn_v1_0_enable_clock_gating(vinst);</div><div class='add'>+	vcn_1_0_enable_static_power_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v1_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */</div><div class='hunk'>@@ -1193,24 +1266,32 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,</div><div class='ctx'> 			~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		r = vcn_v1_0_stop_dpg_mode(adev);</div><div class='add'>+		r = vcn_v1_0_stop_dpg_mode(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		r = vcn_v1_0_stop_spg_mode(adev);</div><div class='add'>+		r = vcn_v1_0_stop_spg_mode(vinst);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-				int inst_idx, struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	int ret_code;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	uint32_t reg_data2 = 0;</div><div class='hunk'>@@ -1257,7 +1338,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='ctx'> </div><div class='del'>-				ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,</div><div class='ctx'> 						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) &amp; 0x7FFFFFFF);</div><div class='ctx'> 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,</div><div class='hunk'>@@ -1318,7 +1398,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,</div><div class='ctx'> 							UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);</div><div class='ctx'> </div><div class='del'>-				ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,</div><div class='ctx'> 						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) &amp; 0x7FFFFFFF);</div><div class='ctx'> 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,</div><div class='hunk'>@@ -1336,16 +1415,16 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vcn_v1_0_is_idle(void *handle)</div><div class='add'>+static bool vcn_v1_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,</div><div class='hunk'>@@ -1354,20 +1433,21 @@ static int vcn_v1_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = adev-&gt;vcn.inst;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* wait for STATUS to clear */</div><div class='del'>-		if (!vcn_v1_0_is_idle(handle))</div><div class='add'>+		if (!vcn_v1_0_is_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='del'>-		vcn_v1_0_enable_clock_gating(adev);</div><div class='add'>+		vcn_v1_0_enable_clock_gating(vinst);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* disable HW gating and enable Sw gating */</div><div class='del'>-		vcn_v1_0_disable_clock_gating(adev);</div><div class='add'>+		vcn_v1_0_disable_clock_gating(vinst);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1759,8 +1839,8 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v1_0_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='add'>+static int vcn_v1_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the VCN block.</div><div class='ctx'> 	 * That's done in the dpm code via the SMC.  This</div><div class='hunk'>@@ -1770,28 +1850,29 @@ static int vcn_v1_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='ctx'> 	int ret;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v1_0_stop(adev);</div><div class='add'>+		ret = vcn_v1_0_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v1_0_start(adev);</div><div class='add'>+		ret = vcn_v1_0_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vcn_v1_0_idle_work_handler(struct work_struct *work)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev =</div><div class='del'>-		container_of(work, struct amdgpu_device, vcn.idle_work.work);</div><div class='add'>+	struct amdgpu_vcn_inst *vcn_inst =</div><div class='add'>+		container_of(work, struct amdgpu_vcn_inst, idle_work.work);</div><div class='add'>+	struct amdgpu_device *adev = vcn_inst-&gt;adev;</div><div class='ctx'> 	unsigned int fences = 0, i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i)</div><div class='ctx'> 		fences += amdgpu_fence_count_emitted(&amp;adev-&gt;vcn.inst-&gt;ring_enc[i]);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='hunk'>@@ -1807,7 +1888,7 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)</div><div class='ctx'> 		else</div><div class='ctx'> 			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode(adev, 0, &amp;new_state);</div><div class='add'>+		adev-&gt;vcn.inst-&gt;pause_dpg_mode(vcn_inst, &amp;new_state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	fences += amdgpu_fence_count_emitted(adev-&gt;jpeg.inst-&gt;ring_dec);</div><div class='hunk'>@@ -1816,21 +1897,21 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)</div><div class='ctx'> 	if (fences == 0) {</div><div class='ctx'> 		amdgpu_gfx_off_ctrl(adev, true);</div><div class='ctx'> 		if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-			amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+			amdgpu_dpm_enable_vcn(adev, false, 0);</div><div class='ctx'> 		else</div><div class='ctx'> 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,</div><div class='ctx'> 			       AMD_PG_STATE_GATE);</div><div class='ctx'> 	} else {</div><div class='del'>-		schedule_delayed_work(&amp;adev-&gt;vcn.idle_work, VCN_IDLE_TIMEOUT);</div><div class='add'>+		schedule_delayed_work(&amp;adev-&gt;vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct	amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	bool set_clocks = !cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	bool set_clocks = !cancel_delayed_work_sync(&amp;adev-&gt;vcn.inst[0].idle_work);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;adev-&gt;vcn.vcn1_jpeg1_workaround);</div><div class='add'>+	mutex_lock(&amp;adev-&gt;vcn.inst[0].vcn1_jpeg1_workaround);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_fence_wait_empty(ring-&gt;adev-&gt;jpeg.inst-&gt;ring_dec))</div><div class='ctx'> 		DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");</div><div class='hunk'>@@ -1846,7 +1927,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)</div><div class='ctx'> 	if (set_clocks) {</div><div class='ctx'> 		amdgpu_gfx_off_ctrl(adev, false);</div><div class='ctx'> 		if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-			amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+			amdgpu_dpm_enable_vcn(adev, true, 0);</div><div class='ctx'> 		else</div><div class='ctx'> 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,</div><div class='ctx'> 			       AMD_PG_STATE_UNGATE);</div><div class='hunk'>@@ -1856,7 +1937,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)</div><div class='ctx'> 		struct dpg_pause_state new_state;</div><div class='ctx'> 		unsigned int fences = 0, i;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i)</div><div class='ctx'> 			fences += amdgpu_fence_count_emitted(&amp;adev-&gt;vcn.inst-&gt;ring_enc[i]);</div><div class='ctx'> </div><div class='ctx'> 		if (fences)</div><div class='hunk'>@@ -1874,20 +1955,79 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)</div><div class='ctx'> 		else if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_JPEG)</div><div class='ctx'> 			new_state.jpeg = VCN_DPG_STATE__PAUSE;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode(adev, 0, &amp;new_state);</div><div class='add'>+		adev-&gt;vcn.inst-&gt;pause_dpg_mode(adev-&gt;vcn.inst, &amp;new_state);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='del'>-	schedule_delayed_work(&amp;ring-&gt;adev-&gt;vcn.idle_work, VCN_IDLE_TIMEOUT);</div><div class='del'>-	mutex_unlock(&amp;ring-&gt;adev-&gt;vcn.vcn1_jpeg1_workaround);</div><div class='add'>+	schedule_delayed_work(&amp;ring-&gt;adev-&gt;vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);</div><div class='add'>+	mutex_unlock(&amp;ring-&gt;adev-&gt;vcn.inst[0].vcn1_jpeg1_workaround);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);</div><div class='add'>+	uint32_t inst_off, is_powered;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;vcn.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "num_instances:%d\n", adev-&gt;vcn.num_vcn_inst);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i)) {</div><div class='add'>+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		inst_off = i * reg_count;</div><div class='add'>+		is_powered = (adev-&gt;vcn.ip_dump[inst_off] &amp;</div><div class='add'>+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;</div><div class='add'>+</div><div class='add'>+		if (is_powered) {</div><div class='add'>+			drm_printf(p, "\nActive Instance:VCN%d\n", i);</div><div class='add'>+			for (j = 0; j &lt; reg_count; j++)</div><div class='add'>+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,</div><div class='add'>+					   adev-&gt;vcn.ip_dump[inst_off + j]);</div><div class='add'>+		} else {</div><div class='add'>+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, j;</div><div class='add'>+	bool is_powered;</div><div class='add'>+	uint32_t inst_off;</div><div class='add'>+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;vcn.ip_dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		inst_off = i * reg_count;</div><div class='add'>+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */</div><div class='add'>+		adev-&gt;vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);</div><div class='add'>+		is_powered = (adev-&gt;vcn.ip_dump[inst_off] &amp;</div><div class='add'>+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;</div><div class='add'>+</div><div class='add'>+		if (is_powered)</div><div class='add'>+			for (j = 1; j &lt; reg_count; j++)</div><div class='add'>+				adev-&gt;vcn.ip_dump[inst_off + j] =</div><div class='add'>+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v1_0",</div><div class='ctx'> 	.early_init = vcn_v1_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v1_0_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v1_0_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v1_0_hw_init,</div><div class='hunk'>@@ -1896,12 +2036,10 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v1_0_resume,</div><div class='ctx'> 	.is_idle = vcn_v1_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v1_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,</div><div class='del'>-	.pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,</div><div class='del'>-	.soft_reset = NULL /* vcn_v1_0_soft_reset */,</div><div class='del'>-	.post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,</div><div class='ctx'> 	.set_clockgating_state = vcn_v1_0_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v1_0_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = vcn_v1_0_dump_ip_state,</div><div class='add'>+	.print_ip_state = vcn_v1_0_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -1958,11 +2096,11 @@ static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		uint32_t reg = amdgpu_ib_get_value(ib, i);</div><div class='ctx'> 		uint32_t val = amdgpu_ib_get_value(ib, i + 1);</div><div class='ctx'> </div><div class='del'>-		if (reg == PACKET0(p-&gt;adev-&gt;vcn.internal.data0, 0)) {</div><div class='add'>+		if (reg == PACKET0(p-&gt;adev-&gt;vcn.inst[0].internal.data0, 0)) {</div><div class='ctx'> 			msg_lo = val;</div><div class='del'>-		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.internal.data1, 0)) {</div><div class='add'>+		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.inst[0].internal.data1, 0)) {</div><div class='ctx'> 			msg_hi = val;</div><div class='del'>-		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.internal.cmd, 0)) {</div><div class='add'>+		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.inst[0].internal.cmd, 0)) {</div><div class='ctx'> 			r = vcn_v1_0_validate_bo(p, job,</div><div class='ctx'> 						 ((u64)msg_hi) &lt;&lt; 32 | msg_lo);</div><div class='ctx'> 			if (r)</div><div class='hunk'>@@ -2041,17 +2179,14 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {</div><div class='ctx'> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;ring_dec.funcs = &amp;vcn_v1_0_dec_ring_vm_funcs;</div><div class='del'>-	DRM_INFO("VCN decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i)</div><div class='ctx'> 		adev-&gt;vcn.inst-&gt;ring_enc[i].funcs = &amp;vcn_v1_0_enc_ring_vm_funcs;</div><div class='del'>-</div><div class='del'>-	DRM_INFO("VCN encode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {</div><div class='hunk'>@@ -2061,7 +2196,7 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {</div><div class='ctx'> </div><div class='ctx'> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	adev-&gt;vcn.inst-&gt;irq.num_types = adev-&gt;vcn.num_enc_rings + 2;</div><div class='add'>+	adev-&gt;vcn.inst-&gt;irq.num_types = adev-&gt;vcn.inst[0].num_enc_rings + 2;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;irq.funcs = &amp;vcn_v1_0_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c<br/>index e357d8cf0c01..8897dcc9c1a0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c</a></div><div class='hunk'>@@ -39,6 +39,7 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN_VID_SOC_ADDRESS_2_0					0x1fa00</div><div class='ctx'> #define VCN1_VID_SOC_ADDRESS_3_0				0x48200</div><div class='add'>+#define VCN1_AON_SOC_ADDRESS_3_0				0x48000</div><div class='ctx'> </div><div class='ctx'> #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x1fd</div><div class='ctx'> #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x503</div><div class='hunk'>@@ -53,51 +54,90 @@</div><div class='ctx'> #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x5a7</div><div class='ctx'> #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x1e2</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v2_0_set_powergating_state(void *handle,</div><div class='del'>-				enum amd_powergating_state state);</div><div class='del'>-static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-				int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state);</div><div class='add'>+static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state);</div><div class='ctx'> static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);</div><div class='add'>+static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_early_init(void *handle)</div><div class='add'>+static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='del'>-		adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+		adev-&gt;vcn.inst[0].num_enc_rings = 1;</div><div class='ctx'> 	else</div><div class='del'>-		adev-&gt;vcn.num_enc_rings = 2;</div><div class='add'>+		adev-&gt;vcn.inst[0].num_enc_rings = 2;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;vcn.inst-&gt;set_pg_state = vcn_v2_0_set_pg_state;</div><div class='ctx'> 	vcn_v2_0_set_dec_ring_funcs(adev);</div><div class='ctx'> 	vcn_v2_0_set_enc_ring_funcs(adev);</div><div class='ctx'> 	vcn_v2_0_set_irq_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	return amdgpu_vcn_early_init(adev, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_sw_init(void *handle)</div><div class='add'>+static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 	/* VCN DEC TRAP */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='hunk'>@@ -107,7 +147,7 @@ static int vcn_v2_0_sw_init(void *handle)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	/* VCN ENC TRAP */</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 				      i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,</div><div class='ctx'> 				      &amp;adev-&gt;vcn.inst-&gt;irq);</div><div class='hunk'>@@ -115,13 +155,13 @@ static int vcn_v2_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='add'>+	r = amdgpu_vcn_sw_init(adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='add'>+	amdgpu_vcn_setup_ucode(adev, 0);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='add'>+	r = amdgpu_vcn_resume(adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -137,25 +177,25 @@ static int vcn_v2_0_sw_init(void *handle)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;</div><div class='del'>-	adev-&gt;vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;</div><div class='del'>-	adev-&gt;vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;</div><div class='del'>-	adev-&gt;vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;</div><div class='del'>-	adev-&gt;vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;</div><div class='del'>-	adev-&gt;vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);</div><div class='del'>-	adev-&gt;vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);</div><div class='del'>-	adev-&gt;vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);</div><div class='del'>-	adev-&gt;vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);</div><div class='del'>-	adev-&gt;vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;</div><div class='add'>+	adev-&gt;vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);</div><div class='ctx'> </div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst-&gt;ring_enc[i];</div><div class='hunk'>@@ -172,7 +212,13 @@ static int vcn_v2_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	adev-&gt;vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;</div><div class='add'>+	adev-&gt;vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;</div><div class='add'>+	adev-&gt;vcn.inst[0].reset = vcn_v2_0_reset;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_virt_alloc_mm_table(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -184,21 +230,29 @@ static int vcn_v2_0_sw_init(void *handle)</div><div class='ctx'> 	if (amdgpu_vcnfw_log)</div><div class='ctx'> 		amdgpu_vcn_fwlog_init(adev-&gt;vcn.inst);</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_2_0, ARRAY_SIZE(vcn_reg_list_2_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_sw_fini(void *handle)</div><div class='add'>+static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r, idx;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='ctx'> 		fw_shared-&gt;present_flag_0 = 0;</div><div class='hunk'>@@ -207,25 +261,27 @@ static int vcn_v2_0_sw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	r = amdgpu_vcn_suspend(adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	amdgpu_vcn_sw_fini(adev, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_hw_init(void *handle)</div><div class='add'>+static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='hunk'>@@ -237,44 +293,40 @@ static int vcn_v2_0_hw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 	if (r)</div><div class='del'>-		goto done;</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	//Disable vcn decode for sriov</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		ring-&gt;sched.ready = false;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst-&gt;ring_enc[i];</div><div class='ctx'> 		r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_hw_fini(void *handle)</div><div class='add'>+static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = adev-&gt;vcn.inst;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='ctx'> </div><div class='ctx'> 	if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='del'>-	    (adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='del'>-	      RREG32_SOC15(VCN, 0, mmUVD_STATUS)))</div><div class='del'>-		vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+	    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+	     RREG32_SOC15(VCN, 0, mmUVD_STATUS)))</div><div class='add'>+		vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -282,20 +334,19 @@ static int vcn_v2_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_suspend(void *handle)</div><div class='add'>+static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v2_0_hw_fini(adev);</div><div class='add'>+	r = vcn_v2_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	r = amdgpu_vcn_suspend(ip_block-&gt;adev, 0);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -303,20 +354,19 @@ static int vcn_v2_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_0_resume(void *handle)</div><div class='add'>+static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='add'>+	r = amdgpu_vcn_resume(ip_block-&gt;adev, 0);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v2_0_hw_init(adev);</div><div class='add'>+	r = vcn_v2_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -324,13 +374,14 @@ static int vcn_v2_0_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: Pointer to the VCN instance structure</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[0]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[0].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -384,9 +435,11 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev-&gt;gfx.config.gb_addr_config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)</div><div class='add'>+static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					bool indirect)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[0]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[0].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -483,12 +536,13 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -592,9 +646,10 @@ static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='add'>+static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='ctx'> 		uint8_t sram_sel, uint8_t indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* enable sw clock gating control */</div><div class='hunk'>@@ -643,12 +698,13 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_0_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -701,8 +757,9 @@ static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -750,8 +807,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -792,13 +850,15 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)</div><div class='add'>+static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	vcn_v2_0_enable_static_power_gating(adev);</div><div class='add'>+	vcn_v2_0_enable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='ctx'> 	/* enable dynamic power gating mode */</div><div class='ctx'> 	tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);</div><div class='hunk'>@@ -810,7 +870,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)</div><div class='ctx'> 		adev-&gt;vcn.inst-&gt;dpg_sram_curr_addr = (uint32_t *)adev-&gt;vcn.inst-&gt;dpg_sram_cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);</div><div class='add'>+	vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -859,7 +919,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v2_0_mc_resume_dpg_mode(adev, indirect);</div><div class='add'>+	vcn_v2_0_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(</div><div class='ctx'> 		UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);</div><div class='hunk'>@@ -880,8 +940,13 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)</div><div class='ctx'> 		UVD, 0, mmUVD_MASTINT_EN),</div><div class='ctx'> 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, 0, 0);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, 0, 0);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* force RBC into idle state */</div><div class='ctx'> 	rb_bufsz = order_base_2(ring-&gt;ring_size);</div><div class='hunk'>@@ -924,31 +989,38 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)</div><div class='ctx'> 	/* Unstall DPG */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),</div><div class='ctx'> 		0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring = &amp;adev-&gt;vcn.inst-&gt;ring_dec;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='ctx'> 	uint32_t lmi_swap_cntl;</div><div class='ctx'> 	int i, j, r;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, true, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		return vcn_v2_0_start_dpg_mode(adev, adev-&gt;vcn.indirect_sram);</div><div class='add'>+		return vcn_v2_0_start_dpg_mode(vinst, adev-&gt;vcn.inst-&gt;indirect_sram);</div><div class='ctx'> </div><div class='del'>-	vcn_v2_0_disable_static_power_gating(adev);</div><div class='add'>+	vcn_v2_0_disable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='ctx'> 	/* set uvd status busy */</div><div class='ctx'> 	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);</div><div class='ctx'> </div><div class='ctx'> 	/*SW clock gating */</div><div class='del'>-	vcn_v2_0_disable_clock_gating(adev);</div><div class='add'>+	vcn_v2_0_disable_clock_gating(vinst);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),</div><div class='hunk'>@@ -992,7 +1064,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)</div><div class='ctx'> 		(0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		(0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='ctx'> </div><div class='del'>-	vcn_v2_0_mc_resume(adev);</div><div class='add'>+	vcn_v2_0_mc_resume(vinst);</div><div class='ctx'> </div><div class='ctx'> 	/* release VCPU reset to boot */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,</div><div class='hunk'>@@ -1097,15 +1169,21 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring-&gt;ring_size / 4);</div><div class='ctx'> 	fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='del'>-	vcn_v2_0_pause_dpg_mode(adev, 0, &amp;state);</div><div class='add'>+	vcn_v2_0_pause_dpg_mode(vinst, &amp;state);</div><div class='ctx'> 	/* Wait for power status to be 1 */</div><div class='ctx'> 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,</div><div class='ctx'> 		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='hunk'>@@ -1127,16 +1205,22 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,</div><div class='ctx'> 			~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(UVD, 0, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-		r = vcn_v2_0_stop_dpg_mode(adev);</div><div class='add'>+		r = vcn_v2_0_stop_dpg_mode(vinst);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 		goto power_off;</div><div class='hunk'>@@ -1188,19 +1272,26 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)</div><div class='ctx'> 	/* clear status */</div><div class='ctx'> 	WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-	vcn_v2_0_enable_clock_gating(adev);</div><div class='del'>-	vcn_v2_0_enable_static_power_gating(adev);</div><div class='add'>+	vcn_v2_0_enable_clock_gating(vinst);</div><div class='add'>+	vcn_v2_0_enable_static_power_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, 0, mmUVD_STATUS);</div><div class='ctx'> </div><div class='ctx'> power_off:</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, false, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-				int inst_idx, struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	int ret_code;</div><div class='hunk'>@@ -1217,7 +1308,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='ctx'> </div><div class='ctx'> 			if (!ret_code) {</div><div class='del'>-				volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='add'>+				struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst-&gt;fw_shared.cpu_addr;</div><div class='ctx'> 				/* pause DPG */</div><div class='ctx'> 				reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;</div><div class='ctx'> 				WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);</div><div class='hunk'>@@ -1275,16 +1366,26 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vcn_v2_0_is_idle(void *handle)</div><div class='add'>+static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = vcn_v2_0_stop(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return vcn_v2_0_start(vinst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,</div><div class='hunk'>@@ -1293,10 +1394,10 @@ static int vcn_v2_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -1304,12 +1405,12 @@ static int vcn_v2_0_set_clockgating_state(void *handle,</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* wait for STATUS to clear */</div><div class='del'>-		if (!vcn_v2_0_is_idle(handle))</div><div class='add'>+		if (!vcn_v2_0_is_idle(ip_block))</div><div class='ctx'> 			return -EBUSY;</div><div class='del'>-		vcn_v2_0_enable_clock_gating(adev);</div><div class='add'>+		vcn_v2_0_enable_clock_gating(&amp;adev-&gt;vcn.inst[0]);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* disable HW gating and enable Sw gating */</div><div class='del'>-		vcn_v2_0_disable_clock_gating(adev);</div><div class='add'>+		vcn_v2_0_disable_clock_gating(&amp;adev-&gt;vcn.inst[0]);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1379,9 +1480,9 @@ void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data0, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0);</div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START &lt;&lt; 1));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1396,7 +1497,7 @@ void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[0].internal.cmd, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END &lt;&lt; 1));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1416,7 +1517,7 @@ void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)</div><div class='ctx'> 	WARN_ON(ring-&gt;wptr % 2 || count % 2);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; count / 2; i++) {</div><div class='del'>-		amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.nop, 0));</div><div class='add'>+		amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.nop, 0));</div><div class='ctx'> 		amdgpu_ring_write(ring, 0);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1437,25 +1538,25 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	WARN_ON(flags &amp; AMDGPU_FENCE_FLAG_64BIT);</div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.context_id, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.context_id, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, seq);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data0, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, addr &amp; 0xffffffff);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data1, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data1, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, upper_32_bits(addr) &amp; 0xff);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE &lt;&lt; 1));</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data0, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data1, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data1, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP &lt;&lt; 1));</div><div class='ctx'> }</div><div class='hunk'>@@ -1478,14 +1579,14 @@ void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.ib_vmid, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.ib_vmid, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, vmid);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring,	PACKET0(adev-&gt;vcn.internal.ib_bar_low, 0));</div><div class='add'>+	amdgpu_ring_write(ring,	PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.ib_bar_low, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, lower_32_bits(ib-&gt;gpu_addr));</div><div class='del'>-	amdgpu_ring_write(ring,	PACKET0(adev-&gt;vcn.internal.ib_bar_high, 0));</div><div class='add'>+	amdgpu_ring_write(ring,	PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.ib_bar_high, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, upper_32_bits(ib-&gt;gpu_addr));</div><div class='del'>-	amdgpu_ring_write(ring,	PACKET0(adev-&gt;vcn.internal.ib_size, 0));</div><div class='add'>+	amdgpu_ring_write(ring,	PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.ib_size, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, ib-&gt;length_dw);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1494,16 +1595,16 @@ void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data0, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, reg &lt;&lt; 2);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data1, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data1, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, val);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.gp_scratch8, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.gp_scratch8, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, mask);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT &lt;&lt; 1));</div><div class='ctx'> }</div><div class='hunk'>@@ -1528,13 +1629,13 @@ void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data0, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, reg &lt;&lt; 2);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.data1, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.data1, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, val);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0));</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG &lt;&lt; 1));</div><div class='ctx'> }</div><div class='hunk'>@@ -1735,9 +1836,9 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> 	r = amdgpu_ring_alloc(ring, 4);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.cmd, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START &lt;&lt; 1));</div><div class='del'>-	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.internal.scratch9, 0));</div><div class='add'>+	amdgpu_ring_write(ring, PACKET0(adev-&gt;vcn.inst[ring-&gt;me].internal.scratch9, 0));</div><div class='ctx'> 	amdgpu_ring_write(ring, 0xDEADBEEF);</div><div class='ctx'> 	amdgpu_ring_commit(ring);</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='hunk'>@@ -1754,8 +1855,8 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int vcn_v2_0_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='add'>+static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	/* This doesn't actually powergate the VCN block.</div><div class='ctx'> 	 * That's done in the dpm code via the SMC.  This</div><div class='hunk'>@@ -1765,23 +1866,24 @@ static int vcn_v2_0_set_powergating_state(void *handle,</div><div class='ctx'> 	 * the smc and the hw blocks</div><div class='ctx'> 	 */</div><div class='ctx'> 	int ret;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-		adev-&gt;vcn.cur_state = AMD_PG_STATE_UNGATE;</div><div class='add'>+		vinst-&gt;cur_state = AMD_PG_STATE_UNGATE;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v2_0_stop(adev);</div><div class='add'>+		ret = vcn_v2_0_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v2_0_start(adev);</div><div class='add'>+		ret = vcn_v2_0_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1820,7 +1922,7 @@ static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;ring_dec.wptr_old = 0;</div><div class='ctx'> 	vcn_v2_0_dec_ring_set_wptr(&amp;adev-&gt;vcn.inst-&gt;ring_dec);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i) {</div><div class='ctx'> 		adev-&gt;vcn.inst-&gt;ring_enc[i].wptr = 0;</div><div class='ctx'> 		adev-&gt;vcn.inst-&gt;ring_enc[i].wptr_old = 0;</div><div class='ctx'> 		vcn_v2_0_enc_ring_set_wptr(&amp;adev-&gt;vcn.inst-&gt;ring_enc[i]);</div><div class='hunk'>@@ -1878,7 +1980,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		init_table += header-&gt;vcn_table_offset;</div><div class='ctx'> </div><div class='del'>-		size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[0]-&gt;size + 4);</div><div class='add'>+		size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[0].fw-&gt;size + 4);</div><div class='ctx'> </div><div class='ctx'> 		MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(</div><div class='ctx'> 			SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),</div><div class='hunk'>@@ -1946,7 +2048,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),</div><div class='ctx'> 			AMDGPU_VCN_CONTEXT_SIZE);</div><div class='ctx'> </div><div class='del'>-		for (r = 0; r &lt; adev-&gt;vcn.num_enc_rings; ++r) {</div><div class='add'>+		for (r = 0; r &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++r) {</div><div class='ctx'> 			ring = &amp;adev-&gt;vcn.inst-&gt;ring_enc[r];</div><div class='ctx'> 			ring-&gt;wptr = 0;</div><div class='ctx'> 			MMSCH_V2_0_INSERT_DIRECT_WT(</div><div class='hunk'>@@ -1993,7 +2095,6 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v2_0",</div><div class='ctx'> 	.early_init = vcn_v2_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v2_0_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v2_0_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v2_0_hw_init,</div><div class='hunk'>@@ -2002,12 +2103,10 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v2_0_resume,</div><div class='ctx'> 	.is_idle = vcn_v2_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v2_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v2_0_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v2_0_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {</div><div class='hunk'>@@ -2038,6 +2137,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = amdgpu_vcn_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {</div><div class='hunk'>@@ -2067,22 +2167,20 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = amdgpu_vcn_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;ring_dec.funcs = &amp;vcn_v2_0_dec_ring_vm_funcs;</div><div class='del'>-	DRM_INFO("VCN decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i)</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.inst[0].num_enc_rings; ++i)</div><div class='ctx'> 		adev-&gt;vcn.inst-&gt;ring_enc[i].funcs = &amp;vcn_v2_0_enc_ring_vm_funcs;</div><div class='del'>-</div><div class='del'>-	DRM_INFO("VCN encode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {</div><div class='hunk'>@@ -2092,7 +2190,7 @@ static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {</div><div class='ctx'> </div><div class='ctx'> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	adev-&gt;vcn.inst-&gt;irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+	adev-&gt;vcn.inst-&gt;irq.num_types = adev-&gt;vcn.inst[0].num_enc_rings + 1;</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;irq.funcs = &amp;vcn_v2_0_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c<br/>index 1cd8a94b0fbc..cebee453871c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c</a></div><div class='hunk'>@@ -39,6 +39,7 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN_VID_SOC_ADDRESS_2_0					0x1fa00</div><div class='ctx'> #define VCN1_VID_SOC_ADDRESS_3_0				0x48200</div><div class='add'>+#define VCN1_AON_SOC_ADDRESS_3_0				0x48000</div><div class='ctx'> </div><div class='ctx'> #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27</div><div class='ctx'> #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f</div><div class='hunk'>@@ -55,37 +56,181 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN25_MAX_HW_INSTANCES_ARCTURUS			2</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v2_5_set_powergating_state(void *handle,</div><div class='del'>-				enum amd_powergating_state state);</div><div class='del'>-static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-				int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v2_5_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state);</div><div class='add'>+static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state);</div><div class='ctx'> static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst);</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void vcn_v2_5_idle_work_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vcn_inst *vcn_inst =</div><div class='add'>+		container_of(work, struct amdgpu_vcn_inst, idle_work.work);</div><div class='add'>+	struct amdgpu_device *adev = vcn_inst-&gt;adev;</div><div class='add'>+	unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *v = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; v-&gt;num_enc_rings; ++j)</div><div class='add'>+			fence[i] += amdgpu_fence_count_emitted(&amp;v-&gt;ring_enc[j]);</div><div class='add'>+</div><div class='add'>+		/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG &amp;&amp;</div><div class='add'>+		    !v-&gt;using_unified_queue) {</div><div class='add'>+			struct dpg_pause_state new_state;</div><div class='add'>+</div><div class='add'>+			if (fence[i] ||</div><div class='add'>+			    unlikely(atomic_read(&amp;v-&gt;dpg_enc_submission_cnt)))</div><div class='add'>+				new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='add'>+			else</div><div class='add'>+				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;</div><div class='add'>+</div><div class='add'>+			v-&gt;pause_dpg_mode(v, &amp;new_state);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		fence[i] += amdgpu_fence_count_emitted(&amp;v-&gt;ring_dec);</div><div class='add'>+		fences += fence[i];</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!fences &amp;&amp; !atomic_read(&amp;adev-&gt;vcn.inst[0].total_submission_cnt)) {</div><div class='add'>+		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,</div><div class='add'>+						       AMD_PG_STATE_GATE);</div><div class='add'>+		amdgpu_vcn_put_profile(adev);</div><div class='add'>+	} else {</div><div class='add'>+		schedule_delayed_work(&amp;adev-&gt;vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *v = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='add'>+</div><div class='add'>+	atomic_inc(&amp;adev-&gt;vcn.inst[0].total_submission_cnt);</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;vcn.inst[0].idle_work);</div><div class='add'>+</div><div class='add'>+	/* We can safely return early here because we've cancelled the</div><div class='add'>+	 * the delayed work so there is no one else to set it to false</div><div class='add'>+	 * and we don't care if someone else sets it to true.</div><div class='add'>+	 */</div><div class='add'>+	mutex_lock(&amp;adev-&gt;vcn.inst[0].vcn_pg_lock);</div><div class='add'>+	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,</div><div class='add'>+					       AMD_PG_STATE_UNGATE);</div><div class='add'>+</div><div class='add'>+	/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG &amp;&amp;</div><div class='add'>+	    !v-&gt;using_unified_queue) {</div><div class='add'>+		struct dpg_pause_state new_state;</div><div class='add'>+</div><div class='add'>+		if (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC) {</div><div class='add'>+			atomic_inc(&amp;v-&gt;dpg_enc_submission_cnt);</div><div class='add'>+			new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='add'>+		} else {</div><div class='add'>+			unsigned int fences = 0;</div><div class='add'>+			unsigned int i;</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; v-&gt;num_enc_rings; ++i)</div><div class='add'>+				fences += amdgpu_fence_count_emitted(&amp;v-&gt;ring_enc[i]);</div><div class='add'>+</div><div class='add'>+			if (fences || atomic_read(&amp;v-&gt;dpg_enc_submission_cnt))</div><div class='add'>+				new_state.fw_based = VCN_DPG_STATE__PAUSE;</div><div class='add'>+			else</div><div class='add'>+				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;</div><div class='add'>+		}</div><div class='add'>+		v-&gt;pause_dpg_mode(v, &amp;new_state);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;vcn.inst[0].vcn_pg_lock);</div><div class='add'>+	amdgpu_vcn_get_profile(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vcn_v2_5_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */</div><div class='add'>+	if (ring-&gt;adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG &amp;&amp;</div><div class='add'>+	    ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_VCN_ENC &amp;&amp;</div><div class='add'>+	    !adev-&gt;vcn.inst[ring-&gt;me].using_unified_queue)</div><div class='add'>+		atomic_dec(&amp;adev-&gt;vcn.inst[ring-&gt;me].dpg_enc_submission_cnt);</div><div class='add'>+</div><div class='add'>+	atomic_dec(&amp;adev-&gt;vcn.inst[0].total_submission_cnt);</div><div class='add'>+</div><div class='add'>+	schedule_delayed_work(&amp;adev-&gt;vcn.inst[0].idle_work,</div><div class='add'>+			      VCN_IDLE_TIMEOUT);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_early_init(void *handle)</div><div class='add'>+static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		adev-&gt;vcn.num_vcn_inst = 2;</div><div class='ctx'> 		adev-&gt;vcn.harvest_config = 0;</div><div class='del'>-		adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='add'>+			adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		u32 harvest;</div><div class='ctx'> 		int i;</div><div class='hunk'>@@ -94,13 +239,12 @@ static int vcn_v2_5_early_init(void *handle)</div><div class='ctx'> 			harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);</div><div class='ctx'> 			if (harvest &amp; CC_UVD_HARVESTING__UVD_DISABLE_MASK)</div><div class='ctx'> 				adev-&gt;vcn.harvest_config |= 1 &lt;&lt; i;</div><div class='add'>+			adev-&gt;vcn.inst[i].num_enc_rings = 2;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |</div><div class='del'>-					AMDGPU_VCN_HARVEST_VCN1))</div><div class='add'>+						 AMDGPU_VCN_HARVEST_VCN1))</div><div class='ctx'> 			/* both instances are harvested, disable the block */</div><div class='ctx'> 			return -ENOENT;</div><div class='del'>-</div><div class='del'>-		adev-&gt;vcn.num_enc_rings = 2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vcn_v2_5_set_dec_ring_funcs(adev);</div><div class='hunk'>@@ -108,23 +252,33 @@ static int vcn_v2_5_early_init(void *handle)</div><div class='ctx'> 	vcn_v2_5_set_irq_funcs(adev);</div><div class='ctx'> 	vcn_v2_5_set_ras_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v2_5_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_sw_init(void *handle)</div><div class='add'>+static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, j, r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; adev-&gt;vcn.num_vcn_inst; j++) {</div><div class='add'>+		struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; j))</div><div class='ctx'> 			continue;</div><div class='ctx'> 		/* VCN DEC TRAP */</div><div class='hunk'>@@ -134,7 +288,7 @@ static int vcn_v2_5_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='ctx'> 		/* VCN ENC TRAP */</div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.inst[j].num_enc_rings; ++i) {</div><div class='ctx'> 			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],</div><div class='ctx'> 				i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &amp;adev-&gt;vcn.inst[j].irq);</div><div class='ctx'> 			if (r)</div><div class='hunk'>@@ -146,39 +300,36 @@ static int vcn_v2_5_sw_init(void *handle)</div><div class='ctx'> 			VCN_2_6__SRCID_UVD_POISON, &amp;adev-&gt;vcn.inst[j].ras_poison_irq);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, j);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='add'>+		/* Override the work func */</div><div class='add'>+		adev-&gt;vcn.inst[j].idle_work.work.func = vcn_v2_5_idle_work_handler;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, j);</div><div class='ctx'> </div><div class='del'>-	for (j = 0; j &lt; adev-&gt;vcn.num_vcn_inst; j++) {</div><div class='del'>-		volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+		r = amdgpu_vcn_resume(adev, j);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; j))</div><div class='del'>-			continue;</div><div class='del'>-		adev-&gt;vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;</div><div class='del'>-</div><div class='del'>-		adev-&gt;vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;</div><div class='add'>+</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);</div><div class='del'>-		adev-&gt;vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);</div><div class='del'>-		adev-&gt;vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);</div><div class='del'>-		adev-&gt;vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);</div><div class='del'>-		adev-&gt;vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[j].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);</div><div class='ctx'> </div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst[j].ring_dec;</div><div class='hunk'>@@ -198,7 +349,7 @@ static int vcn_v2_5_sw_init(void *handle)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.inst[j].num_enc_rings; ++i) {</div><div class='ctx'> 			enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);</div><div class='ctx'> </div><div class='ctx'> 			ring = &amp;adev-&gt;vcn.inst[j].ring_enc[i];</div><div class='hunk'>@@ -226,36 +377,50 @@ static int vcn_v2_5_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_vcnfw_log)</div><div class='ctx'> 			amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[i]);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+			adev-&gt;vcn.inst[j].pause_dpg_mode = vcn_v2_5_pause_dpg_mode;</div><div class='add'>+		adev-&gt;vcn.inst[j].reset = vcn_v2_5_reset;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = amdgpu_virt_alloc_mm_table(adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;</div><div class='del'>-</div><div class='ctx'> 	r = amdgpu_vcn_ras_sw_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_2_5, ARRAY_SIZE(vcn_reg_list_2_5));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_sw_fini(void *handle)</div><div class='add'>+static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int i, r, idx;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='hunk'>@@ -271,25 +436,28 @@ static int vcn_v2_5_sw_fini(void *handle)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_hw_init(void *handle)</div><div class='add'>+static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, j, r = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -314,50 +482,47 @@ static int vcn_v2_5_hw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 			if (r)</div><div class='del'>-				goto done;</div><div class='add'>+				return r;</div><div class='ctx'> </div><div class='del'>-			for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+			for (i = 0; i &lt; adev-&gt;vcn.inst[j].num_enc_rings; ++i) {</div><div class='ctx'> 				ring = &amp;adev-&gt;vcn.inst[j].ring_enc[i];</div><div class='ctx'> 				r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 				if (r)</div><div class='del'>-					goto done;</div><div class='add'>+					return r;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_hw_fini(void *handle)</div><div class='add'>+static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='add'>+</div><div class='ctx'> 		if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='del'>-		    (adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+		    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='ctx'> 		     RREG32_SOC15(VCN, i, mmUVD_STATUS)))</div><div class='del'>-			vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))</div><div class='del'>-			amdgpu_irq_put(adev, &amp;adev-&gt;vcn.inst[i].ras_poison_irq, 0);</div><div class='add'>+			amdgpu_irq_put(adev, &amp;vinst-&gt;ras_poison_irq, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -366,41 +531,47 @@ static int vcn_v2_5_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_suspend(void *handle)</div><div class='add'>+static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v2_5_hw_fini(adev);</div><div class='add'>+	r = vcn_v2_5_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v2_5_resume(void *handle)</div><div class='add'>+static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v2_5_hw_init(adev);</div><div class='add'>+	r = vcn_v2_5_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -408,70 +579,72 @@ static int vcn_v2_5_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_5_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t size;</div><div class='ctx'> 	uint32_t offset;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='ctx'> </div><div class='del'>-		size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[i]-&gt;size + 4);</div><div class='del'>-		/* cache window 0: fw */</div><div class='del'>-		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,</div><div class='del'>-				(adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,</div><div class='del'>-				(adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);</div><div class='del'>-			offset = 0;</div><div class='del'>-		} else {</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,</div><div class='del'>-				lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,</div><div class='del'>-				upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr));</div><div class='del'>-			offset = size;</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,</div><div class='del'>-				AMDGPU_UVD_FIRMWARE_OFFSET &gt;&gt; 3);</div><div class='del'>-		}</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-		/* cache window 1: stack */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,</div><div class='del'>-			lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,</div><div class='del'>-			upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);</div><div class='del'>-</div><div class='del'>-		/* cache window 2: context */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,</div><div class='del'>-			lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,</div><div class='del'>-			upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);</div><div class='del'>-</div><div class='del'>-		/* non-cache window */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,</div><div class='del'>-			lower_32_bits(adev-&gt;vcn.inst[i].fw_shared.gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,</div><div class='del'>-			upper_32_bits(adev-&gt;vcn.inst[i].fw_shared.gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,</div><div class='del'>-			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));</div><div class='add'>+	size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[i].fw-&gt;size + 4);</div><div class='add'>+	/* cache window 0: fw */</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,</div><div class='add'>+			     (adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,</div><div class='add'>+			     (adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);</div><div class='add'>+		offset = 0;</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,</div><div class='add'>+			     lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,</div><div class='add'>+			     upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr));</div><div class='add'>+		offset = size;</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,</div><div class='add'>+			     AMDGPU_UVD_FIRMWARE_OFFSET &gt;&gt; 3);</div><div class='ctx'> 	}</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);</div><div class='add'>+</div><div class='add'>+	/* cache window 1: stack */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,</div><div class='add'>+		     lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,</div><div class='add'>+		     upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);</div><div class='add'>+</div><div class='add'>+	/* cache window 2: context */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,</div><div class='add'>+		     lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,</div><div class='add'>+		     upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);</div><div class='add'>+</div><div class='add'>+	/* non-cache window */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,</div><div class='add'>+		     lower_32_bits(adev-&gt;vcn.inst[i].fw_shared.gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,</div><div class='add'>+		     upper_32_bits(adev-&gt;vcn.inst[i].fw_shared.gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,</div><div class='add'>+		     AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					bool indirect)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[inst_idx]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[inst_idx].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -568,123 +741,124 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		/* UVD disable CGC */</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='del'>-		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='del'>-			data |= 1 &lt;&lt; UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='del'>-		else</div><div class='del'>-			data &amp;= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;</div><div class='del'>-		data |= 1 &lt;&lt; UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;</div><div class='del'>-		data |= 4 &lt;&lt; UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='del'>-</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);</div><div class='del'>-		data &amp;= ~(UVD_CGC_GATE__SYS_MASK</div><div class='del'>-			| UVD_CGC_GATE__UDEC_MASK</div><div class='del'>-			| UVD_CGC_GATE__MPEG2_MASK</div><div class='del'>-			| UVD_CGC_GATE__REGS_MASK</div><div class='del'>-			| UVD_CGC_GATE__RBC_MASK</div><div class='del'>-			| UVD_CGC_GATE__LMI_MC_MASK</div><div class='del'>-			| UVD_CGC_GATE__LMI_UMC_MASK</div><div class='del'>-			| UVD_CGC_GATE__IDCT_MASK</div><div class='del'>-			| UVD_CGC_GATE__MPRD_MASK</div><div class='del'>-			| UVD_CGC_GATE__MPC_MASK</div><div class='del'>-			| UVD_CGC_GATE__LBSI_MASK</div><div class='del'>-			| UVD_CGC_GATE__LRBBM_MASK</div><div class='del'>-			| UVD_CGC_GATE__UDEC_RE_MASK</div><div class='del'>-			| UVD_CGC_GATE__UDEC_CM_MASK</div><div class='del'>-			| UVD_CGC_GATE__UDEC_IT_MASK</div><div class='del'>-			| UVD_CGC_GATE__UDEC_DB_MASK</div><div class='del'>-			| UVD_CGC_GATE__UDEC_MP_MASK</div><div class='del'>-			| UVD_CGC_GATE__WCB_MASK</div><div class='del'>-			| UVD_CGC_GATE__VCPU_MASK</div><div class='del'>-			| UVD_CGC_GATE__MMSCH_MASK);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);</div><div class='del'>-</div><div class='del'>-		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);</div><div class='del'>-</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='del'>-		data &amp;= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_CM_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_IT_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_DB_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_MP_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__SYS_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MPEG2_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__REGS_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__RBC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LMI_MC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LMI_UMC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__IDCT_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MPRD_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MPC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LBSI_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LRBBM_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__WCB_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__VCPU_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MMSCH_MODE_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='del'>-</div><div class='del'>-		/* turn on */</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);</div><div class='del'>-		data |= (UVD_SUVD_CGC_GATE__SRE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SIT_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SMP_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SCM_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SDB_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SRE_H264_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SIT_H264_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SCM_H264_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SDB_H264_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SCLR_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__UVD_SC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__ENT_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SITE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SRE_VP9_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SCM_VP9_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__SDB_VP9_MASK</div><div class='del'>-			| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);</div><div class='del'>-</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);</div><div class='del'>-		data &amp;= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return;</div><div class='add'>+	/* UVD disable CGC */</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='add'>+	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='add'>+		data |= 1 &lt;&lt; UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='add'>+	else</div><div class='add'>+		data &amp;= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;</div><div class='add'>+	data |= 1 &lt;&lt; UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;</div><div class='add'>+	data |= 4 &lt;&lt; UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);</div><div class='add'>+	data &amp;= ~(UVD_CGC_GATE__SYS_MASK</div><div class='add'>+		  | UVD_CGC_GATE__UDEC_MASK</div><div class='add'>+		  | UVD_CGC_GATE__MPEG2_MASK</div><div class='add'>+		  | UVD_CGC_GATE__REGS_MASK</div><div class='add'>+		  | UVD_CGC_GATE__RBC_MASK</div><div class='add'>+		  | UVD_CGC_GATE__LMI_MC_MASK</div><div class='add'>+		  | UVD_CGC_GATE__LMI_UMC_MASK</div><div class='add'>+		  | UVD_CGC_GATE__IDCT_MASK</div><div class='add'>+		  | UVD_CGC_GATE__MPRD_MASK</div><div class='add'>+		  | UVD_CGC_GATE__MPC_MASK</div><div class='add'>+		  | UVD_CGC_GATE__LBSI_MASK</div><div class='add'>+		  | UVD_CGC_GATE__LRBBM_MASK</div><div class='add'>+		  | UVD_CGC_GATE__UDEC_RE_MASK</div><div class='add'>+		  | UVD_CGC_GATE__UDEC_CM_MASK</div><div class='add'>+		  | UVD_CGC_GATE__UDEC_IT_MASK</div><div class='add'>+		  | UVD_CGC_GATE__UDEC_DB_MASK</div><div class='add'>+		  | UVD_CGC_GATE__UDEC_MP_MASK</div><div class='add'>+		  | UVD_CGC_GATE__WCB_MASK</div><div class='add'>+		  | UVD_CGC_GATE__VCPU_MASK</div><div class='add'>+		  | UVD_CGC_GATE__MMSCH_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);</div><div class='add'>+</div><div class='add'>+	SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='add'>+	data &amp;= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__UDEC_CM_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__UDEC_IT_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__UDEC_DB_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__UDEC_MP_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__SYS_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__UDEC_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__MPEG2_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__REGS_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__RBC_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__LMI_MC_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__LMI_UMC_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__IDCT_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__MPRD_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__MPC_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__LBSI_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__LRBBM_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__WCB_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__VCPU_MODE_MASK</div><div class='add'>+		  | UVD_CGC_CTRL__MMSCH_MODE_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='add'>+</div><div class='add'>+	/* turn on */</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);</div><div class='add'>+	data |= (UVD_SUVD_CGC_GATE__SRE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SIT_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SMP_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SCM_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SDB_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SRE_H264_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SIT_H264_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SCM_H264_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SDB_H264_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SCLR_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__UVD_SC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__ENT_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SITE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);</div><div class='add'>+	data &amp;= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK</div><div class='ctx'> 			| UVD_SUVD_CGC_CTRL__IME_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);</div><div class='del'>-	}</div><div class='add'>+		  | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-		uint8_t sram_sel, int inst_idx, uint8_t indirect)</div><div class='add'>+static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+		uint8_t sram_sel, uint8_t indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* enable sw clock gating control */</div><div class='hunk'>@@ -733,68 +907,69 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v2_5_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)</div><div class='add'>+static void vcn_v2_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		/* enable UVD CGC */</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='del'>-		if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='del'>-			data |= 1 &lt;&lt; UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='del'>-		else</div><div class='del'>-			data |= 0 &lt;&lt; UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='del'>-		data |= 1 &lt;&lt; UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;</div><div class='del'>-		data |= 4 &lt;&lt; UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='del'>-</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='del'>-		data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_CM_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_IT_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_DB_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_MP_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__SYS_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__UDEC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MPEG2_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__REGS_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__RBC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LMI_MC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LMI_UMC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__IDCT_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MPRD_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__MPC_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LBSI_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__LRBBM_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__WCB_MODE_MASK</div><div class='del'>-			| UVD_CGC_CTRL__VCPU_MODE_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='del'>-</div><div class='del'>-		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);</div><div class='del'>-		data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__IME_MODE_MASK</div><div class='del'>-			| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);</div><div class='del'>-	}</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return;</div><div class='add'>+	/* enable UVD CGC */</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='add'>+	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='add'>+		data |= 1 &lt;&lt; UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='add'>+	else</div><div class='add'>+		data |= 0 &lt;&lt; UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;</div><div class='add'>+	data |= 1 &lt;&lt; UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;</div><div class='add'>+	data |= 4 &lt;&lt; UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);</div><div class='add'>+	data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__SYS_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__UDEC_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__MPEG2_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__REGS_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__RBC_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__LMI_MC_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__IDCT_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__MPRD_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__MPC_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__LBSI_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__LRBBM_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__WCB_MODE_MASK</div><div class='add'>+		 | UVD_CGC_CTRL__VCPU_MODE_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);</div><div class='add'>+</div><div class='add'>+	data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);</div><div class='add'>+	data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK</div><div class='add'>+		 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,</div><div class='add'>+static void vcn_v2_6_enable_ras(struct amdgpu_vcn_inst *vinst,</div><div class='ctx'> 				bool indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(2, 6, 0))</div><div class='hunk'>@@ -819,11 +994,14 @@ static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,</div><div class='ctx'> 			      tmp, 0, indirect);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* disable register anti-hang mechanism */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,</div><div class='hunk'>@@ -838,7 +1016,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		adev-&gt;vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev-&gt;vcn.inst[inst_idx].dpg_sram_cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);</div><div class='add'>+	vcn_v2_5_clock_gating_dpg_mode(vinst, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -887,7 +1065,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v2_5_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);</div><div class='hunk'>@@ -898,7 +1076,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v2_6_enable_ras(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v2_6_enable_ras(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* unblock VCPU register access */</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='hunk'>@@ -914,8 +1092,13 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		VCN, 0, mmUVD_MASTINT_EN),</div><div class='ctx'> 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_dec;</div><div class='ctx'> 	/* force RBC into idle state */</div><div class='hunk'>@@ -960,198 +1143,200 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),</div><div class='ctx'> 		0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v2_5_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared =</div><div class='add'>+		adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='del'>-	int i, j, k, r;</div><div class='add'>+	int j, k, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, true, i);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v2_5_start_dpg_mode(adev, i, adev-&gt;vcn.indirect_sram);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v2_5_start_dpg_mode(vinst, adev-&gt;vcn.inst[i].indirect_sram);</div><div class='ctx'> </div><div class='del'>-		/* disable register anti-hang mechanism */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,</div><div class='del'>-			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='add'>+	/* disable register anti-hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,</div><div class='add'>+		 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='ctx'> </div><div class='del'>-		/* set uvd status busy */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);</div><div class='del'>-	}</div><div class='add'>+	/* set uvd status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	/*SW clock gating */</div><div class='del'>-	vcn_v2_5_disable_clock_gating(adev);</div><div class='add'>+	/* SW clock gating */</div><div class='add'>+	vcn_v2_5_disable_clock_gating(vinst);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		/* enable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='del'>-			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,</div><div class='del'>-			~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* setup mmUVD_LMI_CTRL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);</div><div class='del'>-		tmp &amp;= ~0xff;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|</div><div class='del'>-			UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|</div><div class='del'>-			UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='del'>-			UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='del'>-			UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* setup mmUVD_MPC_CNTL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);</div><div class='del'>-		tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='del'>-		tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXA0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,</div><div class='del'>-			((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='del'>-			(0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='del'>-			(0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='del'>-			(0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXB0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,</div><div class='del'>-			((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='del'>-			(0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='del'>-			(0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='del'>-			(0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup mmUVD_MPC_SET_MUX */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,</div><div class='del'>-			((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='del'>-			(0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='del'>-			(0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='del'>-	}</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='ctx'> </div><div class='del'>-	vcn_v2_5_mc_resume(adev);</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		/* VCN global tiling registers */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,</div><div class='del'>-			adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,</div><div class='del'>-			adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+	/* setup mmUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);</div><div class='add'>+	tmp &amp;= ~0xff;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|</div><div class='add'>+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* setup mmUVD_MPC_CNTL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);</div><div class='add'>+	tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='add'>+	tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXA0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXB0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup mmUVD_MPC_SET_MUX */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,</div><div class='add'>+		     ((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='add'>+		      (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='add'>+</div><div class='add'>+	vcn_v2_5_mc_resume(vinst);</div><div class='ctx'> </div><div class='del'>-		/* enable LMI MC and UMC channels */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,</div><div class='del'>-			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='ctx'> </div><div class='del'>-		/* unblock VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,</div><div class='del'>-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='ctx'> </div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='del'>-			~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-		for (k = 0; k &lt; 10; ++k) {</div><div class='del'>-			uint32_t status;</div><div class='del'>-</div><div class='del'>-			for (j = 0; j &lt; 100; ++j) {</div><div class='del'>-				status = RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-				if (amdgpu_emu_mode == 1)</div><div class='del'>-					msleep(500);</div><div class='del'>-				else</div><div class='del'>-					mdelay(10);</div><div class='del'>-			}</div><div class='del'>-			r = 0;</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; 10; ++k) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; 100; ++j) {</div><div class='add'>+			status = RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='ctx'> 			if (status &amp; 2)</div><div class='ctx'> 				break;</div><div class='add'>+			if (amdgpu_emu_mode == 1)</div><div class='add'>+				msleep(500);</div><div class='add'>+			else</div><div class='add'>+				mdelay(10);</div><div class='add'>+		}</div><div class='add'>+		r = 0;</div><div class='add'>+		if (status &amp; 2)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-			DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='del'>-				UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-			mdelay(10);</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+		DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='add'>+			 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='add'>+			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-			mdelay(10);</div><div class='del'>-			r = -1;</div><div class='del'>-		}</div><div class='add'>+		mdelay(10);</div><div class='add'>+		r = -1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("VCN decode not responding, giving up!!!\n");</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("VCN decode not responding, giving up!!!\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* enable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),</div><div class='del'>-			UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='del'>-			~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		/* clear the busy bit of VCN_STATUS */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,</div><div class='del'>-			~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);</div><div class='ctx'> </div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_dec;</div><div class='del'>-		/* force RBC into idle state */</div><div class='del'>-		rb_bufsz = order_base_2(ring-&gt;ring_size);</div><div class='del'>-		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_dec;</div><div class='add'>+	/* force RBC into idle state */</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size);</div><div class='add'>+	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-		fw_shared-&gt;multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;</div><div class='del'>-		/* program the RB_BASE for ring buffer */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,</div><div class='del'>-			lower_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,</div><div class='del'>-			upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	fw_shared-&gt;multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	/* program the RB_BASE for ring buffer */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,</div><div class='add'>+		     lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,</div><div class='add'>+		     upper_32_bits(ring-&gt;gpu_addr));</div><div class='ctx'> </div><div class='del'>-		/* Initialize the ring buffer's read and write pointers */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);</div><div class='ctx'> </div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,</div><div class='del'>-				lower_32_bits(ring-&gt;wptr));</div><div class='del'>-		fw_shared-&gt;multi_queue.decode_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,</div><div class='add'>+		     lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	fw_shared-&gt;multi_queue.decode_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='ctx'> </div><div class='del'>-		fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;</div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='del'>-		fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='del'>-</div><div class='del'>-		fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;</div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[1];</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring-&gt;gpu_addr);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring-&gt;ring_size / 4);</div><div class='del'>-		fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='del'>-	}</div><div class='add'>+	fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+	fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='add'>+</div><div class='add'>+	fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[1];</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring-&gt;gpu_addr);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring-&gt;ring_size / 4);</div><div class='add'>+	fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode &amp;= ~FW_QUEUE_RING_RESET;</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1242,7 +1427,7 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)</div><div class='ctx'> 			SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),</div><div class='ctx'> 			~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);</div><div class='ctx'> </div><div class='del'>-		size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[i]-&gt;size + 4);</div><div class='add'>+		size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[i].fw-&gt;size + 4);</div><div class='ctx'> 		/* mc resume*/</div><div class='ctx'> 		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 			MMSCH_V1_0_INSERT_DIRECT_WT(</div><div class='hunk'>@@ -1352,8 +1537,10 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)</div><div class='ctx'> 	return vcn_v2_5_mmsch_start(adev, &amp;adev-&gt;virt.mm_table);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static int vcn_v2_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for power status to be 1 */</div><div class='hunk'>@@ -1377,80 +1564,93 @@ static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,</div><div class='ctx'> 			~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v2_5_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, r = 0;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v2_5_stop_dpg_mode(adev, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-		/* wait for vcn idle */</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		r = vcn_v2_5_stop_dpg_mode(vinst);</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* block LMI UMC channel */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);</div><div class='del'>-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|</div><div class='del'>-			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* block LMI UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);</div><div class='ctx'> </div><div class='del'>-		/* block VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),</div><div class='del'>-			UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='del'>-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* reset VCPU */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='del'>-			UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-			~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* block VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='ctx'> </div><div class='del'>-		/* disable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='del'>-			~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+	/* reset VCPU */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* clear status */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='ctx'> </div><div class='del'>-		vcn_v2_5_enable_clock_gating(adev);</div><div class='add'>+	/* clear status */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-		/* enable register anti-hang mechanism */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),</div><div class='del'>-			UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,</div><div class='del'>-			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='del'>-	}</div><div class='add'>+	vcn_v2_5_enable_clock_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* enable register anti-hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),</div><div class='add'>+		 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,</div><div class='add'>+		 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='add'>+done:</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, false, i);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-				int inst_idx, struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	int ret_code = 0;</div><div class='hunk'>@@ -1467,7 +1667,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='ctx'> </div><div class='ctx'> 			if (!ret_code) {</div><div class='del'>-				volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+				struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 				/* pause DPG */</div><div class='ctx'> 				reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;</div><div class='hunk'>@@ -1596,11 +1796,12 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {</div><div class='ctx'> 	.insert_start = vcn_v2_0_dec_ring_insert_start,</div><div class='ctx'> 	.insert_end = vcn_v2_0_dec_ring_insert_end,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='del'>-	.begin_use = amdgpu_vcn_ring_begin_use,</div><div class='del'>-	.end_use = amdgpu_vcn_ring_end_use,</div><div class='add'>+	.begin_use = vcn_v2_5_ring_begin_use,</div><div class='add'>+	.end_use = vcn_v2_5_ring_end_use,</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = amdgpu_vcn_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1694,11 +1895,12 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {</div><div class='ctx'> 	.insert_nop = amdgpu_ring_insert_nop,</div><div class='ctx'> 	.insert_end = vcn_v2_0_enc_ring_insert_end,</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='del'>-	.begin_use = amdgpu_vcn_ring_begin_use,</div><div class='del'>-	.end_use = amdgpu_vcn_ring_end_use,</div><div class='add'>+	.begin_use = vcn_v2_5_ring_begin_use,</div><div class='add'>+	.end_use = vcn_v2_5_ring_end_use,</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = amdgpu_vcn_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1710,7 +1912,6 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_dec.funcs = &amp;vcn_v2_5_dec_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_dec.me = i;</div><div class='del'>-		DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1721,31 +1922,41 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	for (j = 0; j &lt; adev-&gt;vcn.num_vcn_inst; ++j) {</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; j))</div><div class='ctx'> 			continue;</div><div class='del'>-		for (i = 0; i &lt; adev-&gt;vcn.num_enc_rings; ++i) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.inst[j].num_enc_rings; ++i) {</div><div class='ctx'> 			adev-&gt;vcn.inst[j].ring_enc[i].funcs = &amp;vcn_v2_5_enc_ring_vm_funcs;</div><div class='ctx'> 			adev-&gt;vcn.inst[j].ring_enc[i].me = j;</div><div class='ctx'> 		}</div><div class='del'>-		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vcn_v2_5_is_idle(void *handle)</div><div class='add'>+static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = vcn_v2_5_stop(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return vcn_v2_5_start(vinst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='add'>+</div><div class='ctx'> 		ret &amp;= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1760,45 +1971,50 @@ static int vcn_v2_5_wait_for_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_set_clockgating_state(void *handle,</div><div class='add'>+static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = (state == AMD_CG_STATE_GATE);</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (enable) {</div><div class='del'>-		if (!vcn_v2_5_is_idle(handle))</div><div class='del'>-			return -EBUSY;</div><div class='del'>-		vcn_v2_5_enable_clock_gating(adev);</div><div class='del'>-	} else {</div><div class='del'>-		vcn_v2_5_disable_clock_gating(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='add'>+		if (enable) {</div><div class='add'>+			if (!vcn_v2_5_is_idle(ip_block))</div><div class='add'>+				return -EBUSY;</div><div class='add'>+			vcn_v2_5_enable_clock_gating(vinst);</div><div class='add'>+		} else {</div><div class='add'>+			vcn_v2_5_disable_clock_gating(vinst);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v2_5_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='add'>+static int vcn_v2_5_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if(state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v2_5_stop(adev);</div><div class='add'>+		ret = vcn_v2_5_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v2_5_start(adev);</div><div class='add'>+		ret = vcn_v2_5_start(vinst);</div><div class='ctx'> </div><div class='del'>-	if(!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+	if (!ret)</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1875,10 +2091,10 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='del'>-		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].irq.funcs = &amp;vcn_v2_5_irq_funcs;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].ras_poison_irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].ras_poison_irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ras_poison_irq.funcs = &amp;vcn_v2_6_ras_irq_funcs;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1886,7 +2102,6 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v2_5",</div><div class='ctx'> 	.early_init = vcn_v2_5_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v2_5_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v2_5_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v2_5_hw_init,</div><div class='hunk'>@@ -1895,18 +2110,15 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v2_5_resume,</div><div class='ctx'> 	.is_idle = vcn_v2_5_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v2_5_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v2_5_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v2_5_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {</div><div class='ctx'>         .name = "vcn_v2_6",</div><div class='ctx'>         .early_init = vcn_v2_5_early_init,</div><div class='del'>-        .late_init = NULL,</div><div class='ctx'>         .sw_init = vcn_v2_5_sw_init,</div><div class='ctx'>         .sw_fini = vcn_v2_5_sw_fini,</div><div class='ctx'>         .hw_init = vcn_v2_5_hw_init,</div><div class='hunk'>@@ -1915,12 +2127,10 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {</div><div class='ctx'>         .resume = vcn_v2_5_resume,</div><div class='ctx'>         .is_idle = vcn_v2_5_is_idle,</div><div class='ctx'>         .wait_for_idle = vcn_v2_5_wait_for_idle,</div><div class='del'>-        .check_soft_reset = NULL,</div><div class='del'>-        .pre_soft_reset = NULL,</div><div class='del'>-        .soft_reset = NULL,</div><div class='del'>-        .post_soft_reset = NULL,</div><div class='ctx'>         .set_clockgating_state = vcn_v2_5_set_clockgating_state,</div><div class='del'>-        .set_powergating_state = vcn_v2_5_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version vcn_v2_5_ip_block =</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br/>index 8f82fb887e9c..d9cf8f0feeb3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c</a></div><div class='hunk'>@@ -40,6 +40,7 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN_VID_SOC_ADDRESS_2_0					0x1fa00</div><div class='ctx'> #define VCN1_VID_SOC_ADDRESS_3_0				0x48200</div><div class='add'>+#define VCN1_AON_SOC_ADDRESS_3_0				0x48000</div><div class='ctx'> </div><div class='ctx'> #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27</div><div class='ctx'> #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f</div><div class='hunk'>@@ -60,6 +61,42 @@</div><div class='ctx'> #define RDECODE_MSG_CREATE					0x00000000</div><div class='ctx'> #define RDECODE_MESSAGE_CREATE					0x00000001</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN1</div><div class='hunk'>@@ -69,10 +106,11 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v3_0_set_powergating_state(void *handle,</div><div class='del'>-			enum amd_powergating_state state);</div><div class='del'>-static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-			int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state);</div><div class='add'>+static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst);</div><div class='ctx'> </div><div class='ctx'> static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='hunk'>@@ -80,19 +118,21 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_early_init(void *handle)</div><div class='add'>+static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		adev-&gt;vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;</div><div class='ctx'> 		adev-&gt;vcn.harvest_config = 0;</div><div class='del'>-		adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='add'>+			adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |</div><div class='hunk'>@@ -100,43 +140,42 @@ static int vcn_v3_0_early_init(void *handle)</div><div class='ctx'> 			/* both instances are harvested, disable the block */</div><div class='ctx'> 			return -ENOENT;</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==</div><div class='del'>-		    IP_VERSION(3, 0, 33))</div><div class='del'>-			adev-&gt;vcn.num_enc_rings = 0;</div><div class='del'>-		else</div><div class='del'>-			adev-&gt;vcn.num_enc_rings = 2;</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+			if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==</div><div class='add'>+			    IP_VERSION(3, 0, 33))</div><div class='add'>+				adev-&gt;vcn.inst[i].num_enc_rings = 0;</div><div class='add'>+			else</div><div class='add'>+				adev-&gt;vcn.inst[i].num_enc_rings = 2;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vcn_v3_0_set_dec_ring_funcs(adev);</div><div class='ctx'> 	vcn_v3_0_set_enc_ring_funcs(adev);</div><div class='ctx'> 	vcn_v3_0_set_irq_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v3_0_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_sw_init(void *handle)</div><div class='add'>+static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, j, r;</div><div class='ctx'> 	int vcn_doorbell_index = 0;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines</div><div class='hunk'>@@ -152,27 +191,37 @@ static int vcn_v3_0_sw_init(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+		struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;</div><div class='del'>-		adev-&gt;vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;</div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);</div><div class='del'>-		adev-&gt;vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);</div><div class='del'>-		adev-&gt;vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);</div><div class='del'>-		adev-&gt;vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);</div><div class='del'>-		adev-&gt;vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;</div><div class='add'>+		adev-&gt;vcn.inst[i].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);</div><div class='ctx'> </div><div class='ctx'> 		/* VCN DEC TRAP */</div><div class='hunk'>@@ -186,7 +235,7 @@ static int vcn_v3_0_sw_init(void *handle)</div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst[i].ring_dec;</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='ctx'> 		if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-			ring-&gt;doorbell_index = vcn_doorbell_index + i * (adev-&gt;vcn.num_enc_rings + 1);</div><div class='add'>+			ring-&gt;doorbell_index = vcn_doorbell_index + i * (adev-&gt;vcn.inst[i].num_enc_rings + 1);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + 8 * i;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -198,7 +247,7 @@ static int vcn_v3_0_sw_init(void *handle)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; adev-&gt;vcn.num_enc_rings; ++j) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j) {</div><div class='ctx'> 			enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);</div><div class='ctx'> </div><div class='ctx'> 			/* VCN ENC TRAP */</div><div class='hunk'>@@ -210,7 +259,7 @@ static int vcn_v3_0_sw_init(void *handle)</div><div class='ctx'> 			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[j];</div><div class='ctx'> 			ring-&gt;use_doorbell = true;</div><div class='ctx'> 			if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-				ring-&gt;doorbell_index = vcn_doorbell_index + i * (adev-&gt;vcn.num_enc_rings + 1) + 1 + j;</div><div class='add'>+				ring-&gt;doorbell_index = vcn_doorbell_index + i * (adev-&gt;vcn.inst[i].num_enc_rings + 1) + 1 + j;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + 2 + j + 8 * i;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -236,15 +285,30 @@ static int vcn_v3_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_vcnfw_log)</div><div class='ctx'> 			amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[i]);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+			adev-&gt;vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode;</div><div class='add'>+		adev-&gt;vcn.inst[i].reset = vcn_v3_0_reset;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = amdgpu_virt_alloc_mm_table(adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_3_0, ARRAY_SIZE(vcn_reg_list_3_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -252,18 +316,18 @@ static int vcn_v3_0_sw_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_sw_fini(void *handle)</div><div class='add'>+static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-			volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+			struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='hunk'>@@ -278,32 +342,36 @@ static int vcn_v3_0_sw_fini(void *handle)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_hw_init(void *handle)</div><div class='add'>+static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, j, r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = vcn_v3_0_start_sriov(adev);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='ctx'> 		/* initialize VCN dec and enc ring buffers */</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -322,7 +390,7 @@ static int vcn_v3_0_hw_init(void *handle)</div><div class='ctx'> 				ring-&gt;sched.ready = true;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			for (j = 0; j &lt; adev-&gt;vcn.num_enc_rings; ++j) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j) {</div><div class='ctx'> 				ring = &amp;adev-&gt;vcn.inst[i].ring_enc[j];</div><div class='ctx'> 				if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {</div><div class='ctx'> 					ring-&gt;sched.ready = false;</div><div class='hunk'>@@ -348,48 +416,45 @@ static int vcn_v3_0_hw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 			if (r)</div><div class='del'>-				goto done;</div><div class='add'>+				return r;</div><div class='ctx'> </div><div class='del'>-			for (j = 0; j &lt; adev-&gt;vcn.num_enc_rings; ++j) {</div><div class='add'>+			for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j) {</div><div class='ctx'> 				ring = &amp;adev-&gt;vcn.inst[i].ring_enc[j];</div><div class='ctx'> 				r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 				if (r)</div><div class='del'>-					goto done;</div><div class='add'>+					return r;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_hw_fini(void *handle)</div><div class='add'>+static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='add'>+</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='del'>-					(adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='del'>-					 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {</div><div class='del'>-				vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+			     RREG32_SOC15(VCN, i, mmUVD_STATUS))) {</div><div class='add'>+				vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -400,41 +465,47 @@ static int vcn_v3_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_suspend(void *handle)</div><div class='add'>+static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v3_0_hw_fini(adev);</div><div class='add'>+	r = vcn_v3_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v3_0_resume(void *handle)</div><div class='add'>+static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v3_0_hw_init(adev);</div><div class='add'>+	r = vcn_v3_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -442,14 +513,15 @@ static int vcn_v3_0_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v3_0_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[inst]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[inst].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -497,9 +569,12 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='ctx'> 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					bool indirect)</div><div class='ctx'> {</div><div class='del'>-	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[inst_idx]-&gt;size + 4);</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[inst_idx].fw-&gt;size + 4);</div><div class='ctx'> 	uint32_t offset;</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -593,8 +668,10 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx</div><div class='ctx'> 		UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev-&gt;gfx.config.gb_addr_config, 0, indirect);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v3_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -644,8 +721,10 @@ static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int</div><div class='ctx'> 	WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v3_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -692,13 +771,14 @@ static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: Pointer to the VCN instance structure</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v3_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	/* VCN disable CGC */</div><div class='hunk'>@@ -825,9 +905,12 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-		uint8_t sram_sel, int inst_idx, uint8_t indirect)</div><div class='add'>+static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					   uint8_t sram_sel,</div><div class='add'>+					   uint8_t indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* enable sw clock gating control */</div><div class='hunk'>@@ -876,13 +959,14 @@ static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v3_0_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: Pointer to the VCN instance structure</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v3_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCN CGC */</div><div class='hunk'>@@ -941,11 +1025,14 @@ static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> 	WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* disable register anti-hang mechanism */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,</div><div class='hunk'>@@ -960,7 +1047,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		adev-&gt;vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev-&gt;vcn.inst[inst_idx].dpg_sram_cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);</div><div class='add'>+	vcn_v3_0_clock_gating_dpg_mode(vinst, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -1009,7 +1096,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v3_0_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);</div><div class='hunk'>@@ -1038,8 +1125,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_dec;</div><div class='ctx'> 	/* force RBC into idle state */</div><div class='hunk'>@@ -1090,195 +1182,203 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),</div><div class='ctx'> 		0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v3_0_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t rb_bufsz, tmp;</div><div class='del'>-	int i, j, k, r;</div><div class='add'>+	int j, k, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, true, i);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v3_0_start_dpg_mode(vinst, vinst-&gt;indirect_sram);</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v3_0_start_dpg_mode(adev, i, adev-&gt;vcn.indirect_sram);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	/* disable VCN power gating */</div><div class='add'>+	vcn_v3_0_disable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		/* disable VCN power gating */</div><div class='del'>-		vcn_v3_0_disable_static_power_gating(adev, i);</div><div class='add'>+	/* set VCN status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);</div><div class='ctx'> </div><div class='del'>-		/* set VCN status busy */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);</div><div class='add'>+	/* SW clock gating */</div><div class='add'>+	vcn_v3_0_disable_clock_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		/*SW clock gating */</div><div class='del'>-		vcn_v3_0_disable_clock_gating(adev, i);</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		/* enable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='del'>-			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,</div><div class='del'>-			~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* enable LMI MC and UMC channels */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,</div><div class='del'>-			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup mmUVD_LMI_CTRL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |</div><div class='del'>-			UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|</div><div class='del'>-			UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='del'>-			UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='del'>-			UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* setup mmUVD_MPC_CNTL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);</div><div class='del'>-		tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='del'>-		tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXA0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,</div><div class='del'>-			((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='del'>-			(0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='del'>-			(0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='del'>-			(0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXB0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,</div><div class='del'>-			((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='del'>-			(0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='del'>-			(0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='del'>-			(0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup mmUVD_MPC_SET_MUX */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,</div><div class='del'>-			((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='del'>-			(0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='del'>-			(0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='del'>-</div><div class='del'>-		vcn_v3_0_mc_resume(adev, i);</div><div class='del'>-</div><div class='del'>-		/* VCN global tiling registers */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,</div><div class='del'>-			adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* unblock VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,</div><div class='del'>-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='del'>-</div><div class='del'>-		/* release VCPU reset to boot */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='del'>-			~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; 10; ++j) {</div><div class='del'>-			uint32_t status;</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='ctx'> </div><div class='del'>-			for (k = 0; k &lt; 100; ++k) {</div><div class='del'>-				status = RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-				mdelay(10);</div><div class='del'>-			}</div><div class='del'>-			r = 0;</div><div class='del'>-			if (status &amp; 2)</div><div class='del'>-				break;</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);</div><div class='ctx'> </div><div class='del'>-			DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='del'>-				UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-			mdelay(10);</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* setup mmUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |</div><div class='add'>+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* setup mmUVD_MPC_CNTL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);</div><div class='add'>+	tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='add'>+	tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXA0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXB0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup mmUVD_MPC_SET_MUX */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,</div><div class='add'>+		     ((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='add'>+		      (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='add'>+</div><div class='add'>+	vcn_v3_0_mc_resume(vinst);</div><div class='ctx'> </div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; 10; ++j) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; 100; ++k) {</div><div class='add'>+			status = RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='ctx'> 			mdelay(10);</div><div class='del'>-			r = -1;</div><div class='ctx'> 		}</div><div class='add'>+		r = 0;</div><div class='add'>+		if (status &amp; 2)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+		DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='add'>+			 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='add'>+			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* enable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),</div><div class='del'>-			UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='del'>-			~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+		r = -1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* clear the busy bit of VCN_STATUS */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,</div><div class='del'>-			~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_dec;</div><div class='del'>-		/* force RBC into idle state */</div><div class='del'>-		rb_bufsz = order_base_2(ring-&gt;ring_size);</div><div class='del'>-		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='ctx'> </div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);</div><div class='ctx'> </div><div class='del'>-		/* programm the RB_BASE for ring buffer */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,</div><div class='del'>-			lower_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,</div><div class='del'>-			upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_dec;</div><div class='add'>+	/* force RBC into idle state */</div><div class='add'>+	rb_bufsz = order_base_2(ring-&gt;ring_size);</div><div class='add'>+	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);</div><div class='ctx'> </div><div class='del'>-		/* Initialize the ring buffer's read and write pointers */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);</div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,</div><div class='del'>-			lower_32_bits(ring-&gt;wptr));</div><div class='del'>-		fw_shared-&gt;rb.wptr = lower_32_bits(ring-&gt;wptr);</div><div class='del'>-		fw_shared-&gt;multi_queue.decode_queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='del'>-</div><div class='del'>-		if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=</div><div class='del'>-		    IP_VERSION(3, 0, 33)) {</div><div class='del'>-			fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);</div><div class='del'>-			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='del'>-			fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='del'>-</div><div class='del'>-			fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);</div><div class='del'>-			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[1];</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring-&gt;gpu_addr);</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-			WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring-&gt;ring_size / 4);</div><div class='del'>-			fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='del'>-		}</div><div class='add'>+	/* programm the RB_BASE for ring buffer */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,</div><div class='add'>+		     lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,</div><div class='add'>+		     upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,</div><div class='add'>+		     lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	fw_shared-&gt;rb.wptr = lower_32_bits(ring-&gt;wptr);</div><div class='add'>+	fw_shared-&gt;multi_queue.decode_queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=</div><div class='add'>+	    IP_VERSION(3, 0, 33)) {</div><div class='add'>+		fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);</div><div class='add'>+		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+		fw_shared-&gt;multi_queue.encode_generalpurpose_queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='add'>+</div><div class='add'>+		fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);</div><div class='add'>+		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[1];</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring-&gt;gpu_addr);</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring-&gt;ring_size / 4);</div><div class='add'>+		fw_shared-&gt;multi_queue.encode_lowlatency_queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1332,7 +1432,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 			mmUVD_STATUS),</div><div class='ctx'> 			~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);</div><div class='ctx'> </div><div class='del'>-		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[i]-&gt;size + 4);</div><div class='add'>+		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[i].fw-&gt;size + 4);</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,</div><div class='hunk'>@@ -1391,7 +1491,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 			mmUVD_VCPU_CACHE_SIZE2),</div><div class='ctx'> 			AMDGPU_VCN_CONTEXT_SIZE);</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; adev-&gt;vcn.num_enc_rings; ++j) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j) {</div><div class='ctx'> 			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[j];</div><div class='ctx'> 			ring-&gt;wptr = 0;</div><div class='ctx'> 			rb_addr = ring-&gt;gpu_addr;</div><div class='hunk'>@@ -1491,12 +1591,14 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static int vcn_v3_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='del'>-	vcn_v3_0_pause_dpg_mode(adev, inst_idx, &amp;state);</div><div class='add'>+	vcn_v3_0_pause_dpg_mode(vinst, &amp;state);</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for power status to be 1 */</div><div class='ctx'> 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,</div><div class='hunk'>@@ -1519,88 +1621,101 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,</div><div class='ctx'> 		~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v3_0_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, r = 0;</div><div class='add'>+	int r = 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='del'>-			continue;</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v3_0_stop_dpg_mode(adev, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		r = vcn_v3_0_stop_dpg_mode(vinst);</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* wait for vcn idle */</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='add'>+</div><div class='add'>+	/* disable LMI UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* disable LMI UMC channel */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);</div><div class='del'>-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);</div><div class='del'>-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|</div><div class='del'>-			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* block VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='ctx'> </div><div class='del'>-		/* block VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),</div><div class='del'>-			UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='del'>-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+	/* reset VCPU */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* reset VCPU */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),</div><div class='del'>-			UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-			~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='ctx'> </div><div class='del'>-		/* disable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,</div><div class='del'>-			~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+	/* apply soft reset */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);</div><div class='ctx'> </div><div class='del'>-		/* apply soft reset */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);</div><div class='add'>+	/* clear status */</div><div class='add'>+	WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-		/* clear status */</div><div class='del'>-		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);</div><div class='add'>+	/* apply HW clock gating */</div><div class='add'>+	vcn_v3_0_enable_clock_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		/* apply HW clock gating */</div><div class='del'>-		vcn_v3_0_enable_clock_gating(adev, i);</div><div class='add'>+	/* enable VCN power gating */</div><div class='add'>+	vcn_v3_0_enable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		/* enable VCN power gating */</div><div class='del'>-		vcn_v3_0_enable_static_power_gating(adev, i);</div><div class='del'>-	}</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, mmUVD_STATUS);</div><div class='ctx'> </div><div class='add'>+done:</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, false, i);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-		   int inst_idx, struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	int ret_code;</div><div class='hunk'>@@ -1719,7 +1834,7 @@ static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='del'>-	volatile struct amdgpu_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='ctx'> 		/*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */</div><div class='hunk'>@@ -1769,15 +1884,19 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,</div><div class='ctx'> 				struct amdgpu_job *job)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_gpu_scheduler **scheds;</div><div class='del'>-</div><div class='del'>-	/* The create msg must be in the first IB submitted */</div><div class='del'>-	if (atomic_read(&amp;job-&gt;base.entity-&gt;fence_seq))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='ctx'> </div><div class='ctx'> 	/* if VCN0 is harvested, we can't support AV1 */</div><div class='ctx'> 	if (p-&gt;adev-&gt;vcn.harvest_config &amp; AMDGPU_VCN_HARVEST_VCN0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	/* wait for all jobs to finish before switching to instance 0 */</div><div class='add'>+	fence = amdgpu_ctx_get_fence(p-&gt;ctx, job-&gt;base.entity, ~0ull);</div><div class='add'>+	if (fence) {</div><div class='add'>+		dma_fence_wait(fence, false);</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	scheds = p-&gt;adev-&gt;gpu_sched[AMDGPU_HW_IP_VCN_DEC]</div><div class='ctx'> 		[AMDGPU_RING_PRIO_DEFAULT].sched;</div><div class='ctx'> 	drm_sched_entity_modify_sched(job-&gt;base.entity, scheds, 1);</div><div class='hunk'>@@ -1883,11 +2002,11 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		uint32_t reg = amdgpu_ib_get_value(ib, i);</div><div class='ctx'> 		uint32_t val = amdgpu_ib_get_value(ib, i + 1);</div><div class='ctx'> </div><div class='del'>-		if (reg == PACKET0(p-&gt;adev-&gt;vcn.internal.data0, 0)) {</div><div class='add'>+		if (reg == PACKET0(p-&gt;adev-&gt;vcn.inst[ring-&gt;me].internal.data0, 0)) {</div><div class='ctx'> 			msg_lo = val;</div><div class='del'>-		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.internal.data1, 0)) {</div><div class='add'>+		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.inst[ring-&gt;me].internal.data1, 0)) {</div><div class='ctx'> 			msg_hi = val;</div><div class='del'>-		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.internal.cmd, 0) &amp;&amp;</div><div class='add'>+		} else if (reg == PACKET0(p-&gt;adev-&gt;vcn.inst[ring-&gt;me].internal.cmd, 0) &amp;&amp;</div><div class='ctx'> 			   val == 0) {</div><div class='ctx'> 			r = vcn_v3_0_dec_msg(p, job,</div><div class='ctx'> 					     ((u64)msg_hi) &lt;&lt; 32 | msg_lo);</div><div class='hunk'>@@ -1927,6 +2046,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = amdgpu_vcn_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2025,6 +2145,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = amdgpu_vcn_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='hunk'>@@ -2040,8 +2161,6 @@ static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		else</div><div class='ctx'> 			adev-&gt;vcn.inst[i].ring_dec.funcs = &amp;vcn_v3_0_dec_sw_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_dec.me = i;</div><div class='del'>-		DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,</div><div class='del'>-			  DEC_SW_RING_ENABLED?"(Software Ring)":"");</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2053,18 +2172,28 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; adev-&gt;vcn.num_enc_rings; ++j) {</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;vcn.inst[i].num_enc_rings; ++j) {</div><div class='ctx'> 			adev-&gt;vcn.inst[i].ring_enc[j].funcs = &amp;vcn_v3_0_enc_ring_vm_funcs;</div><div class='ctx'> 			adev-&gt;vcn.inst[i].ring_enc[j].me = i;</div><div class='ctx'> 		}</div><div class='del'>-		if (adev-&gt;vcn.num_enc_rings &gt; 0)</div><div class='del'>-			DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vcn_v3_0_is_idle(void *handle)</div><div class='add'>+static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = vcn_v3_0_stop(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	vcn_v3_0_enable_clock_gating(vinst);</div><div class='add'>+	vcn_v3_0_enable_static_power_gating(vinst);</div><div class='add'>+	return vcn_v3_0_start(vinst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -2077,9 +2206,9 @@ static bool vcn_v3_0_is_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -2095,54 +2224,55 @@ static int vcn_v3_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_set_clockgating_state(void *handle,</div><div class='add'>+static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (enable) {</div><div class='ctx'> 			if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)</div><div class='ctx'> 				return -EBUSY;</div><div class='del'>-			vcn_v3_0_enable_clock_gating(adev, i);</div><div class='add'>+			vcn_v3_0_enable_clock_gating(vinst);</div><div class='ctx'> 		} else {</div><div class='del'>-			vcn_v3_0_disable_clock_gating(adev, i);</div><div class='add'>+			vcn_v3_0_disable_clock_gating(vinst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v3_0_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='add'>+static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int ret;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* for SRIOV, guest should not control VCN Power-gating</div><div class='ctx'> 	 * MMSCH FW should control Power-gating and clock-gating</div><div class='ctx'> 	 * guest should avoid touching CGC and PG</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-		adev-&gt;vcn.cur_state = AMD_PG_STATE_UNGATE;</div><div class='add'>+		vinst-&gt;cur_state = AMD_PG_STATE_UNGATE;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v3_0_stop(adev);</div><div class='add'>+		ret = vcn_v3_0_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v3_0_start(adev);</div><div class='add'>+		ret = vcn_v3_0_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -2207,7 +2337,7 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].irq.funcs = &amp;vcn_v3_0_irq_funcs;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -2215,7 +2345,6 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v3_0",</div><div class='ctx'> 	.early_init = vcn_v3_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v3_0_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v3_0_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v3_0_hw_init,</div><div class='hunk'>@@ -2224,12 +2353,10 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v3_0_resume,</div><div class='ctx'> 	.is_idle = vcn_v3_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v3_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v3_0_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v3_0_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c<br/>index 832d15f7b5f6..3ae666522d57 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c</a></div><div class='hunk'>@@ -46,12 +46,49 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN_VID_SOC_ADDRESS_2_0							0x1fb00</div><div class='ctx'> #define VCN1_VID_SOC_ADDRESS_3_0						0x48300</div><div class='add'>+#define VCN1_AON_SOC_ADDRESS_3_0						0x48000</div><div class='ctx'> </div><div class='ctx'> #define VCN_HARVEST_MMSCH								0</div><div class='ctx'> </div><div class='ctx'> #define RDECODE_MSG_CREATE							0x00000000</div><div class='ctx'> #define RDECODE_MESSAGE_CREATE							0x00000001</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN1</div><div class='hunk'>@@ -60,25 +97,25 @@ static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v4_0_set_powergating_state(void *handle,</div><div class='del'>-        enum amd_powergating_state state);</div><div class='del'>-static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-        int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state);</div><div class='add'>+static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state);</div><div class='ctx'> static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_early_init(void *handle)</div><div class='add'>+static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int i;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		adev-&gt;vcn.harvest_config = VCN_HARVEST_MMSCH;</div><div class='hunk'>@@ -90,19 +127,28 @@ static int vcn_v4_0_early_init(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* re-use enc ring as unified ring */</div><div class='del'>-	adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		/* re-use enc ring as unified ring */</div><div class='add'>+		adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='ctx'> </div><div class='ctx'> 	vcn_v4_0_set_unified_ring_funcs(adev);</div><div class='ctx'> 	vcn_v4_0_set_irq_funcs(adev);</div><div class='ctx'> 	vcn_v4_0_set_ras_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v4_0_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 	fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	fw_shared-&gt;present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);</div><div class='hunk'>@@ -128,30 +174,30 @@ static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_sw_init(void *handle)</div><div class='add'>+static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='ctx'> 		/* Init instance 0 sched_score to 1, so it's scheduled after other instances */</div><div class='ctx'> 		if (i == 0)</div><div class='ctx'> 			atomic_set(&amp;adev-&gt;vcn.inst[i].sched_score, 1);</div><div class='hunk'>@@ -173,7 +219,8 @@ static int vcn_v4_0_sw_init(void *handle)</div><div class='ctx'> 		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='ctx'> 		if (amdgpu_sriov_vf(adev))</div><div class='del'>-			ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + i * (adev-&gt;vcn.num_enc_rings + 1) + 1;</div><div class='add'>+			ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + i *</div><div class='add'>+				(adev-&gt;vcn.inst[i].num_enc_rings + 1) + 1;</div><div class='ctx'> 		else</div><div class='ctx'> 			ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + 2 + 8 * i;</div><div class='ctx'> 		ring-&gt;vm_hub = AMDGPU_MMHUB0(0);</div><div class='hunk'>@@ -185,39 +232,53 @@ static int vcn_v4_0_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='ctx'> 		vcn_v4_0_fw_shared_init(adev, i);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+			adev-&gt;vcn.inst[i].pause_dpg_mode = vcn_v4_0_pause_dpg_mode;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = amdgpu_virt_alloc_mm_table(adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_vcn_ras_sw_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0, ARRAY_SIZE(vcn_reg_list_4_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_sw_fini(void *handle)</div><div class='add'>+static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-			volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+			struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='hunk'>@@ -233,32 +294,37 @@ static int vcn_v4_0_sw_fini(void *handle)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_hw_init(void *handle)</div><div class='add'>+static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = vcn_v4_0_start_sriov(adev);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='hunk'>@@ -269,7 +335,6 @@ static int vcn_v4_0_hw_init(void *handle)</div><div class='ctx'> 			ring-&gt;wptr_old = 0;</div><div class='ctx'> 			vcn_v4_0_unified_ring_set_wptr(ring);</div><div class='ctx'> 			ring-&gt;sched.ready = true;</div><div class='del'>-</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -283,45 +348,42 @@ static int vcn_v4_0_hw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 			if (r)</div><div class='del'>-				goto done;</div><div class='del'>-</div><div class='add'>+				return r;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_hw_fini(void *handle)</div><div class='add'>+static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='add'>+</div><div class='add'>+		cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='add'>+</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='del'>-                        (adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='del'>-                                RREG32_SOC15(VCN, i, regUVD_STATUS))) {</div><div class='del'>-                        vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+				 RREG32_SOC15(VCN, i, regUVD_STATUS))) {</div><div class='add'>+				vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))</div><div class='del'>-			amdgpu_irq_put(adev, &amp;adev-&gt;vcn.inst[i].ras_poison_irq, 0);</div><div class='add'>+			amdgpu_irq_put(adev, &amp;vinst-&gt;ras_poison_irq, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -330,41 +392,47 @@ static int vcn_v4_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_suspend(void *handle)</div><div class='add'>+static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v4_0_hw_fini(adev);</div><div class='add'>+	r = vcn_v4_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_resume(void *handle)</div><div class='add'>+static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v4_0_hw_init(adev);</div><div class='add'>+	r = vcn_v4_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -372,17 +440,18 @@ static int vcn_v4_0_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -432,17 +501,19 @@ static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					bool indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst_idx]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst_idx].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -533,19 +604,21 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx</div><div class='ctx'> </div><div class='ctx'> 	/* VCN global tiling registers */</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='del'>-		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev-&gt;gfx.config.gb_addr_config, 0, indirect);</div><div class='add'>+			VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),</div><div class='add'>+			adev-&gt;gfx.config.gb_addr_config, 0, indirect);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_disable_static_power_gating - disable VCN static power gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable static power gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -604,13 +677,14 @@ static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_enable_static_power_gating - enable VCN static power gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable static power gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -659,13 +733,14 @@ static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -770,16 +845,18 @@ static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @sram_sel: sram select</div><div class='del'>- * @inst_idx: instance number index</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,</div><div class='del'>-      int inst_idx, uint8_t indirect)</div><div class='add'>+static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+						   uint8_t sram_sel,</div><div class='add'>+						   uint8_t indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -827,13 +904,14 @@ static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, u</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -883,9 +961,11 @@ static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> 	WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,</div><div class='add'>+static void vcn_v4_0_enable_ras(struct amdgpu_vcn_inst *vinst,</div><div class='ctx'> 				bool indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))</div><div class='hunk'>@@ -908,17 +988,19 @@ static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* disable register anti-hang mechanism */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,</div><div class='hunk'>@@ -933,7 +1015,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		adev-&gt;vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev-&gt;vcn.inst[inst_idx].dpg_sram_cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -981,7 +1063,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='ctx'> 	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;</div><div class='hunk'>@@ -993,7 +1075,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v4_0_enable_ras(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_enable_ras(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable master interrupt */</div><div class='ctx'> 	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(</div><div class='hunk'>@@ -1001,8 +1083,13 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_enc[0];</div><div class='ctx'> </div><div class='hunk'>@@ -1030,6 +1117,11 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> 			ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='ctx'> 			VCN_RB1_DB_CTRL__EN_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1037,178 +1129,184 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_start - VCN start</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v4_0_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, j, k, r;</div><div class='add'>+	int j, k, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, true, i);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v4_0_start_dpg_mode(adev, i, adev-&gt;vcn.indirect_sram);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v4_0_start_dpg_mode(vinst, adev-&gt;vcn.inst[i].indirect_sram);</div><div class='ctx'> </div><div class='del'>-		/* disable VCN power gating */</div><div class='del'>-		vcn_v4_0_disable_static_power_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* set VCN status busy */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);</div><div class='del'>-</div><div class='del'>-		/*SW clock gating */</div><div class='del'>-		vcn_v4_0_disable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* enable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-				UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,</div><div class='del'>-				~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* enable LMI MC and UMC channels */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,</div><div class='del'>-				~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_LMI_CTRL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |</div><div class='del'>-				UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='del'>-				UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='del'>-				UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='del'>-				UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_MPC_CNTL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);</div><div class='del'>-		tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='del'>-		tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXA0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,</div><div class='del'>-				((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='del'>-				 (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='del'>-				 (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='del'>-				 (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXB0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,</div><div class='del'>-				((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='del'>-				 (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='del'>-				 (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='del'>-				 (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUX */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,</div><div class='del'>-				((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='del'>-				 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='del'>-				 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='del'>-</div><div class='del'>-		vcn_v4_0_mc_resume(adev, i);</div><div class='del'>-</div><div class='del'>-		/* VCN global tiling registers */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,</div><div class='del'>-				adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* unblock VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,</div><div class='del'>-				~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='del'>-</div><div class='del'>-		/* release VCPU reset to boot */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-		for (j = 0; j &lt; 10; ++j) {</div><div class='del'>-			uint32_t status;</div><div class='del'>-</div><div class='del'>-			for (k = 0; k &lt; 100; ++k) {</div><div class='del'>-				status = RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-				mdelay(10);</div><div class='del'>-				if (amdgpu_emu_mode == 1)</div><div class='del'>-					msleep(1);</div><div class='del'>-			}</div><div class='add'>+	/* disable VCN power gating */</div><div class='add'>+	vcn_v4_0_disable_static_power_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* set VCN status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);</div><div class='add'>+</div><div class='add'>+	/*SW clock gating */</div><div class='add'>+	vcn_v4_0_disable_clock_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |</div><div class='add'>+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_MPC_CNTL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);</div><div class='add'>+	tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='add'>+	tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXA0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXB0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUX */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,</div><div class='add'>+		     ((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='add'>+		      (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='add'>+</div><div class='add'>+	vcn_v4_0_mc_resume(vinst);</div><div class='ctx'> </div><div class='del'>-			if (amdgpu_emu_mode == 1) {</div><div class='del'>-				r = -1;</div><div class='del'>-				if (status &amp; 2) {</div><div class='del'>-					r = 0;</div><div class='del'>-					break;</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; 10; ++j) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; 100; ++k) {</div><div class='add'>+			status = RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+			mdelay(10);</div><div class='add'>+			if (amdgpu_emu_mode == 1)</div><div class='add'>+				msleep(1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode == 1) {</div><div class='add'>+			r = -1;</div><div class='add'>+			if (status &amp; 2) {</div><div class='ctx'> 				r = 0;</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-</div><div class='del'>-				dev_err(adev-&gt;dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);</div><div class='del'>-				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-							UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-							~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-				mdelay(10);</div><div class='del'>-				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-						~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-				mdelay(10);</div><div class='del'>-				r = -1;</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='add'>+		} else {</div><div class='add'>+			r = 0;</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			dev_err(adev-&gt;dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+				 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+			mdelay(10);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+			mdelay(10);</div><div class='add'>+			r = -1;</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* enable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),</div><div class='del'>-				UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='del'>-				~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		/* clear the busy bit of VCN_STATUS */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,</div><div class='del'>-				~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='ctx'> </div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,</div><div class='del'>-				ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='del'>-				VCN_RB1_DB_CTRL__EN_MASK);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='del'>-		tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);</div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='del'>-		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='del'>-	}</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,</div><div class='add'>+		     ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		     VCN_RB1_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='add'>+	tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='add'>+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1256,8 +1354,8 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 	struct mmsch_v4_0_cmd_end end = { {0} };</div><div class='ctx'> 	struct mmsch_v4_0_init_header header;</div><div class='ctx'> </div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='del'>-	volatile struct amdgpu_fw_shared_rb_setup *rb_setup;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_fw_shared_rb_setup *rb_setup;</div><div class='ctx'> </div><div class='ctx'> 	direct_wt.cmd_header.command_type =</div><div class='ctx'> 		MMSCH_COMMAND__DIRECT_REG_WRITE;</div><div class='hunk'>@@ -1289,7 +1387,7 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 			regUVD_STATUS),</div><div class='ctx'> 			~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);</div><div class='ctx'> </div><div class='del'>-		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[i]-&gt;size + 4);</div><div class='add'>+		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[i].fw-&gt;size + 4);</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,</div><div class='hunk'>@@ -1464,17 +1562,18 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static void vcn_v4_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='del'>-	vcn_v4_0_pause_dpg_mode(adev, inst_idx, &amp;state);</div><div class='add'>+	vcn_v4_0_pause_dpg_mode(vinst, &amp;state);</div><div class='ctx'> 	/* Wait for power status to be 1 */</div><div class='ctx'> 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,</div><div class='ctx'> 		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='hunk'>@@ -1489,87 +1588,101 @@ static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> 	/* disable dynamic power gating mode */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,</div><div class='ctx'> 		~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_stop - VCN stop</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v4_0_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, r = 0;</div><div class='add'>+	int r = 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			vcn_v4_0_stop_dpg_mode(adev, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='ctx'> </div><div class='del'>-		/* wait for vcn idle */</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		vcn_v4_0_stop_dpg_mode(vinst);</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* disable LMI UMC channel */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);</div><div class='del'>-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);</div><div class='del'>-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='del'>-			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='add'>+</div><div class='add'>+	/* disable LMI UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* block VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),</div><div class='del'>-				UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='del'>-				~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+	/* block VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='ctx'> </div><div class='del'>-		/* reset VCPU */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-				UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* reset VCPU */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* disable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-				~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='ctx'> </div><div class='del'>-		/* apply soft reset */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	/* apply soft reset */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='ctx'> </div><div class='del'>-		/* clear status */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_STATUS, 0);</div><div class='add'>+	/* clear status */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-		/* apply HW clock gating */</div><div class='del'>-		vcn_v4_0_enable_clock_gating(adev, i);</div><div class='add'>+	/* apply HW clock gating */</div><div class='add'>+	vcn_v4_0_enable_clock_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		/* enable VCN power gating */</div><div class='del'>-		vcn_v4_0_enable_static_power_gating(adev, i);</div><div class='del'>-	}</div><div class='add'>+	/* enable VCN power gating */</div><div class='add'>+	vcn_v4_0_enable_static_power_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='ctx'> </div><div class='add'>+done:</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, false, i);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1577,15 +1690,16 @@ static int vcn_v4_0_stop(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @new_state: pause state</div><div class='ctx'>  *</div><div class='ctx'>  * Pause dpg mode for VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,</div><div class='del'>-      struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	int ret_code;</div><div class='ctx'> </div><div class='hunk'>@@ -1687,15 +1801,19 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,</div><div class='ctx'> 				struct amdgpu_job *job)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_gpu_scheduler **scheds;</div><div class='del'>-</div><div class='del'>-	/* The create msg must be in the first IB submitted */</div><div class='del'>-	if (atomic_read(&amp;job-&gt;base.entity-&gt;fence_seq))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='ctx'> </div><div class='ctx'> 	/* if VCN0 is harvested, we can't support AV1 */</div><div class='ctx'> 	if (p-&gt;adev-&gt;vcn.harvest_config &amp; AMDGPU_VCN_HARVEST_VCN0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	/* wait for all jobs to finish before switching to instance 0 */</div><div class='add'>+	fence = amdgpu_ctx_get_fence(p-&gt;ctx, job-&gt;base.entity, ~0ull);</div><div class='add'>+	if (fence) {</div><div class='add'>+		dma_fence_wait(fence, false);</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	scheds = p-&gt;adev-&gt;gpu_sched[AMDGPU_HW_IP_VCN_ENC]</div><div class='ctx'> 		[AMDGPU_RING_PRIO_0].sched;</div><div class='ctx'> 	drm_sched_entity_modify_sched(job-&gt;base.entity, scheds, 1);</div><div class='hunk'>@@ -1786,22 +1904,16 @@ out:</div><div class='ctx'> </div><div class='ctx'> #define RADEON_VCN_ENGINE_TYPE_ENCODE			(0x00000002)</div><div class='ctx'> #define RADEON_VCN_ENGINE_TYPE_DECODE			(0x00000003)</div><div class='del'>-</div><div class='ctx'> #define RADEON_VCN_ENGINE_INFO				(0x30000001)</div><div class='del'>-#define RADEON_VCN_ENGINE_INFO_MAX_OFFSET		16</div><div class='del'>-</div><div class='ctx'> #define RENCODE_ENCODE_STANDARD_AV1			2</div><div class='ctx'> #define RENCODE_IB_PARAM_SESSION_INIT			0x00000003</div><div class='del'>-#define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET	64</div><div class='ctx'> </div><div class='del'>-/* return the offset in ib if id is found, -1 otherwise</div><div class='del'>- * to speed up the searching we only search upto max_offset</div><div class='del'>- */</div><div class='del'>-static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)</div><div class='add'>+/* return the offset in ib if id is found, -1 otherwise */</div><div class='add'>+static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int start)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ib-&gt;length_dw &amp;&amp; i &lt; max_offset &amp;&amp; ib-&gt;ptr[i] &gt;= 8; i += ib-&gt;ptr[i]/4) {</div><div class='add'>+	for (i = start; i &lt; ib-&gt;length_dw &amp;&amp; ib-&gt;ptr[i] &gt;= 8; i += ib-&gt;ptr[i] / 4) {</div><div class='ctx'> 		if (ib-&gt;ptr[i + 1] == id)</div><div class='ctx'> 			return i;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1816,42 +1928,56 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,</div><div class='ctx'> 	struct amdgpu_vcn_decode_buffer *decode_buffer;</div><div class='ctx'> 	uint64_t addr;</div><div class='ctx'> 	uint32_t val;</div><div class='del'>-	int idx;</div><div class='add'>+	int idx = 0, sidx;</div><div class='ctx'> </div><div class='ctx'> 	/* The first instance can decode anything */</div><div class='ctx'> 	if (!ring-&gt;me)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	/* RADEON_VCN_ENGINE_INFO is at the top of ib block */</div><div class='del'>-	idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,</div><div class='del'>-			RADEON_VCN_ENGINE_INFO_MAX_OFFSET);</div><div class='del'>-	if (idx &lt; 0) /* engine info is missing */</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */</div><div class='del'>-	if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {</div><div class='del'>-		decode_buffer = (struct amdgpu_vcn_decode_buffer *)&amp;ib-&gt;ptr[idx + 6];</div><div class='del'>-</div><div class='del'>-		if (!(decode_buffer-&gt;valid_buf_flag  &amp; 0x1))</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='del'>-		addr = ((u64)decode_buffer-&gt;msg_buffer_address_hi) &lt;&lt; 32 |</div><div class='del'>-			decode_buffer-&gt;msg_buffer_address_lo;</div><div class='del'>-		return vcn_v4_0_dec_msg(p, job, addr);</div><div class='del'>-	} else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {</div><div class='del'>-		idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,</div><div class='del'>-			RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);</div><div class='del'>-		if (idx &gt;= 0 &amp;&amp; ib-&gt;ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)</div><div class='del'>-			return vcn_v4_0_limit_sched(p, job);</div><div class='add'>+	while ((idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, idx)) &gt;= 0) {</div><div class='add'>+		val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */</div><div class='add'>+		if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {</div><div class='add'>+			decode_buffer = (struct amdgpu_vcn_decode_buffer *)&amp;ib-&gt;ptr[idx + 6];</div><div class='add'>+</div><div class='add'>+			if (!(decode_buffer-&gt;valid_buf_flag &amp; 0x1))</div><div class='add'>+				return 0;</div><div class='add'>+</div><div class='add'>+			addr = ((u64)decode_buffer-&gt;msg_buffer_address_hi) &lt;&lt; 32 |</div><div class='add'>+				decode_buffer-&gt;msg_buffer_address_lo;</div><div class='add'>+			return vcn_v4_0_dec_msg(p, job, addr);</div><div class='add'>+		} else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {</div><div class='add'>+			sidx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, idx);</div><div class='add'>+			if (sidx &gt;= 0 &amp;&amp; ib-&gt;ptr[sidx + 2] == RENCODE_ENCODE_STANDARD_AV1)</div><div class='add'>+				return vcn_v4_0_limit_sched(p, job);</div><div class='add'>+		}</div><div class='add'>+		idx += ib-&gt;ptr[idx] / 4;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vcn_v4_0_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+			       unsigned int vmid,</div><div class='add'>+			       struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = vcn_v4_0_stop(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = vcn_v4_0_start(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {</div><div class='ctx'> 	.type = AMDGPU_RING_TYPE_VCN_ENC,</div><div class='ctx'> 	.align_mask = 0x3f,</div><div class='ctx'> 	.nop = VCN_ENC_CMD_NO_OP,</div><div class='del'>-	.extra_dw = sizeof(struct amdgpu_vcn_rb_metadata),</div><div class='add'>+	.extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata),</div><div class='ctx'> 	.get_rptr = vcn_v4_0_unified_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = vcn_v4_0_unified_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = vcn_v4_0_unified_ring_set_wptr,</div><div class='hunk'>@@ -1876,6 +2002,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = vcn_v4_0_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1899,21 +2026,19 @@ static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_enc[0].funcs =</div><div class='ctx'> 		       (const struct amdgpu_ring_funcs *)&amp;vcn_v4_0_unified_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_enc[0].me = i;</div><div class='del'>-</div><div class='del'>-		DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_is_idle - check VCN block is idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block structure</div><div class='ctx'>  *</div><div class='ctx'>  * Check whether VCN block is idle</div><div class='ctx'>  */</div><div class='del'>-static bool vcn_v4_0_is_idle(void *handle)</div><div class='add'>+static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1929,13 +2054,13 @@ static bool vcn_v4_0_is_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_wait_for_idle - wait for VCN block idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Wait for VCN block idle</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1954,65 +2079,61 @@ static int vcn_v4_0_wait_for_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_set_clockgating_state - set VCN block clockgating state</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: amdgpu_ip_block pointer</div><div class='ctx'>  * @state: clock gating state</div><div class='ctx'>  *</div><div class='ctx'>  * Set VCN block clockgating state</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)</div><div class='add'>+static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (enable) {</div><div class='ctx'> 			if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)</div><div class='ctx'> 				return -EBUSY;</div><div class='del'>-			vcn_v4_0_enable_clock_gating(adev, i);</div><div class='add'>+			vcn_v4_0_enable_clock_gating(vinst);</div><div class='ctx'> 		} else {</div><div class='del'>-			vcn_v4_0_disable_clock_gating(adev, i);</div><div class='add'>+			vcn_v4_0_disable_clock_gating(vinst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * vcn_v4_0_set_powergating_state - set VCN block powergating state</div><div class='del'>- *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='del'>- * @state: power gating state</div><div class='del'>- *</div><div class='del'>- * Set VCN block powergating state</div><div class='del'>- */</div><div class='del'>-static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)</div><div class='add'>+static int vcn_v4_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				 enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int ret;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* for SRIOV, guest should not control VCN Power-gating</div><div class='ctx'> 	 * MMSCH FW should control Power-gating and clock-gating</div><div class='ctx'> 	 * guest should avoid touching CGC and PG</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-		adev-&gt;vcn.cur_state = AMD_PG_STATE_UNGATE;</div><div class='add'>+		vinst-&gt;cur_state = AMD_PG_STATE_UNGATE;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v4_0_stop(adev);</div><div class='add'>+		ret = vcn_v4_0_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v4_0_start(adev);</div><div class='add'>+		ret = vcn_v4_0_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -2104,10 +2225,10 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].irq.funcs = &amp;vcn_v4_0_irq_funcs;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].ras_poison_irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].ras_poison_irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ras_poison_irq.funcs = &amp;vcn_v4_0_ras_irq_funcs;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -2115,7 +2236,6 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v4_0",</div><div class='ctx'> 	.early_init = vcn_v4_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v4_0_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v4_0_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v4_0_hw_init,</div><div class='hunk'>@@ -2124,12 +2244,10 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v4_0_resume,</div><div class='ctx'> 	.is_idle = vcn_v4_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v4_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v4_0_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v4_0_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c<br/>index 203fa988322b..cb7123ec1a5d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #include "soc15d.h"</div><div class='ctx'> #include "soc15_hw_ip.h"</div><div class='ctx'> #include "vcn_v2_0.h"</div><div class='add'>+#include "vcn_v4_0_3.h"</div><div class='ctx'> #include "mmsch_v4_0_3.h"</div><div class='ctx'> </div><div class='ctx'> #include "vcn/vcn_4_0_3_offset.h"</div><div class='hunk'>@@ -44,70 +45,156 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN_VID_SOC_ADDRESS_2_0		0x1fb00</div><div class='ctx'> #define VCN1_VID_SOC_ADDRESS_3_0	0x48300</div><div class='add'>+#define VCN1_AON_SOC_ADDRESS_3_0	0x48000</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define NORMALIZE_VCN_REG_OFFSET(offset) \</div><div class='add'>+		(offset &amp; 0x1FFFF)</div><div class='ctx'> </div><div class='ctx'> static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v4_0_3_set_powergating_state(void *handle,</div><div class='del'>-		enum amd_powergating_state state);</div><div class='del'>-static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-		int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state);</div><div class='add'>+static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state);</div><div class='ctx'> static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,</div><div class='ctx'> 				  int inst_idx, bool indirect);</div><div class='add'>+</div><div class='add'>+static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	return (adev-&gt;vcn.caps &amp; AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_early_init - set function pointers</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_early_init(void *handle)</div><div class='add'>+static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='del'>-	/* re-use enc ring as unified ring */</div><div class='del'>-	adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		/* re-use enc ring as unified ring */</div><div class='add'>+		adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='ctx'> </div><div class='ctx'> 	vcn_v4_0_3_set_unified_ring_funcs(adev);</div><div class='ctx'> 	vcn_v4_0_3_set_irq_funcs(adev);</div><div class='ctx'> 	vcn_v4_0_3_set_ras_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dpm_reset_vcn_is_supported(adev) &amp;&amp; !amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);</div><div class='add'>+	fw_shared-&gt;sq.is_enabled = 1;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_vcnfw_log)</div><div class='add'>+		amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[inst_idx]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_sw_init(void *handle)</div><div class='add'>+static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r, vcn_inst;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='ctx'> 	/* VCN DEC TRAP */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 		VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &amp;adev-&gt;vcn.inst-&gt;irq);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	/* VCN POISON TRAP */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+		VCN_4_0__SRCID_UVD_POISON, &amp;adev-&gt;vcn.inst-&gt;ras_poison_irq);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='ctx'> 		vcn_inst = GET_INST(VCN, i);</div><div class='ctx'> </div><div class='hunk'>@@ -125,18 +212,20 @@ static int vcn_v4_0_3_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		ring-&gt;vm_hub = AMDGPU_MMHUB0(adev-&gt;vcn.inst[i].aid_id);</div><div class='ctx'> 		sprintf(ring-&gt;name, "vcn_unified_%d", adev-&gt;vcn.inst[i].aid_id);</div><div class='del'>-		r = amdgpu_ring_init(adev, ring, 512, &amp;adev-&gt;vcn.inst-&gt;irq, 0,</div><div class='add'>+</div><div class='add'>+		/* There are no per-instance irq source IDs on 4.0.3, the IH</div><div class='add'>+		 * packets use a separate field to differentiate instances.</div><div class='add'>+		 */</div><div class='add'>+		r = amdgpu_ring_init(adev, ring, 512, &amp;adev-&gt;vcn.inst[0].irq, 0,</div><div class='ctx'> 				     AMDGPU_RING_PRIO_DEFAULT,</div><div class='ctx'> 				     &amp;adev-&gt;vcn.inst[i].sched_score);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);</div><div class='del'>-		fw_shared-&gt;sq.is_enabled = true;</div><div class='add'>+		vcn_v4_0_3_fw_shared_init(adev, i);</div><div class='ctx'> </div><div class='del'>-		if (amdgpu_vcnfw_log)</div><div class='del'>-			amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[i]);</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+			adev-&gt;vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='hunk'>@@ -145,9 +234,6 @@ static int vcn_v4_0_3_sw_init(void *handle)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;</div><div class='del'>-</div><div class='ctx'> 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {</div><div class='ctx'> 		r = amdgpu_vcn_ras_sw_init(adev);</div><div class='ctx'> 		if (r) {</div><div class='hunk'>@@ -156,24 +242,28 @@ static int vcn_v4_0_3_sw_init(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_sw_fini(void *handle)</div><div class='add'>+static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(&amp;adev-&gt;ddev, &amp;idx)) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-			volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+			struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 			fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='ctx'> 			fw_shared-&gt;present_flag_0 = 0;</div><div class='hunk'>@@ -185,32 +275,63 @@ static int vcn_v4_0_3_sw_fini(void *handle)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	int vcn_inst;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, inst_idx);</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_enc[0];</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='add'>+			(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) + 9 * vcn_inst,</div><div class='add'>+			adev-&gt;vcn.inst[inst_idx].aid_id);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,</div><div class='add'>+			ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+			VCN_RB1_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='add'>+		/* Read DB_CTRL to flush the write DB_CTRL command. */</div><div class='add'>+		RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_hw_init(void *handle)</div><div class='add'>+static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	int i, r, vcn_inst;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = vcn_v4_0_3_start_sriov(adev);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='ctx'> 			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='hunk'>@@ -220,59 +341,55 @@ static int vcn_v4_0_3_hw_init(void *handle)</div><div class='ctx'> 			ring-&gt;sched.ready = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='add'>+		/* This flag is not set for VF, assumed to be disabled always */</div><div class='add'>+		if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &amp;</div><div class='add'>+		    0x100)</div><div class='add'>+			adev-&gt;vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);</div><div class='add'>+</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-			vcn_inst = GET_INST(VCN, i);</div><div class='add'>+			struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+</div><div class='ctx'> 			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+			vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+			vcn_v4_0_3_hw_init_inst(vinst);</div><div class='ctx'> </div><div class='del'>-			if (ring-&gt;use_doorbell) {</div><div class='del'>-				adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(</div><div class='del'>-					adev, ring-&gt;use_doorbell,</div><div class='del'>-					(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='del'>-						9 * vcn_inst,</div><div class='del'>-					adev-&gt;vcn.inst[i].aid_id);</div><div class='del'>-</div><div class='del'>-				WREG32_SOC15(</div><div class='del'>-					VCN, GET_INST(VCN, ring-&gt;me),</div><div class='del'>-					regVCN_RB1_DB_CTRL,</div><div class='del'>-					ring-&gt;doorbell_index</div><div class='del'>-							&lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='del'>-						VCN_RB1_DB_CTRL__EN_MASK);</div><div class='del'>-</div><div class='del'>-				/* Read DB_CTRL to flush the write DB_CTRL command. */</div><div class='del'>-				RREG32_SOC15(</div><div class='del'>-					VCN, GET_INST(VCN, ring-&gt;me),</div><div class='del'>-					regVCN_RB1_DB_CTRL);</div><div class='del'>-			}</div><div class='add'>+			/* Re-init fw_shared when RAS fatal error occurred */</div><div class='add'>+			fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+			if (!fw_shared-&gt;sq.is_enabled)</div><div class='add'>+				vcn_v4_0_3_fw_shared_init(adev, i);</div><div class='ctx'> </div><div class='ctx'> 			r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 			if (r)</div><div class='del'>-				goto done;</div><div class='add'>+				return r;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_DEV_INFO(adev-&gt;dev, "VCN decode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_hw_fini(void *handle)</div><div class='add'>+static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE)</div><div class='del'>-		vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+		cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='add'>+</div><div class='add'>+		if (vinst-&gt;cur_state != AMD_PG_STATE_GATE)</div><div class='add'>+			vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) &amp;&amp; !amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;vcn.inst-&gt;ras_poison_irq, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -280,41 +397,47 @@ static int vcn_v4_0_3_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_suspend(void *handle)</div><div class='add'>+static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v4_0_3_hw_fini(adev);</div><div class='add'>+	r = vcn_v4_0_3_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_resume(void *handle)</div><div class='add'>+static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int r;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v4_0_3_hw_init(adev);</div><div class='add'>+	r = vcn_v4_0_3_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -322,17 +445,18 @@ static int vcn_v4_0_3_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size, vcn_inst;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst_idx]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst_idx].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	vcn_inst = GET_INST(VCN, inst_idx);</div><div class='hunk'>@@ -396,18 +520,20 @@ static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					  bool indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst_idx]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst_idx].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -510,13 +636,14 @@ static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> 	int vcn_inst;</div><div class='ctx'> </div><div class='hunk'>@@ -603,16 +730,18 @@ static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @sram_sel: sram select</div><div class='del'>- * @inst_idx: instance number index</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,</div><div class='del'>-				int inst_idx, uint8_t indirect)</div><div class='add'>+static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+						     uint8_t sram_sel,</div><div class='add'>+						     uint8_t indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -654,13 +783,14 @@ static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> 	int vcn_inst;</div><div class='ctx'> </div><div class='hunk'>@@ -705,18 +835,20 @@ static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared =</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared =</div><div class='ctx'> 						adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	int vcn_inst;</div><div class='add'>+	int vcn_inst, ret;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='ctx'> 	vcn_inst = GET_INST(VCN, inst_idx);</div><div class='hunk'>@@ -740,7 +872,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -790,7 +922,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='ctx'> 	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;</div><div class='hunk'>@@ -809,8 +941,13 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 		VCN, 0, regUVD_MASTINT_EN),</div><div class='ctx'> 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_enc[0];</div><div class='ctx'> </div><div class='hunk'>@@ -842,6 +979,11 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 	/*resetting done, fw can check RB ring */</div><div class='ctx'> 	fw_shared-&gt;sq.queue_mode &amp;= cpu_to_le32(~FW_QUEUE_RING_RESET);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -870,8 +1012,8 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 	struct mmsch_v4_0_cmd_end end = { {0} };</div><div class='ctx'> 	struct mmsch_v4_0_3_init_header header;</div><div class='ctx'> </div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='del'>-	volatile struct amdgpu_fw_shared_rb_setup *rb_setup;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_fw_shared_rb_setup *rb_setup;</div><div class='ctx'> </div><div class='ctx'> 	direct_wt.cmd_header.command_type =</div><div class='ctx'> 		MMSCH_COMMAND__DIRECT_REG_WRITE;</div><div class='hunk'>@@ -882,6 +1024,8 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='ctx'> 		vcn_inst = GET_INST(VCN, i);</div><div class='ctx'> </div><div class='add'>+		vcn_v4_0_3_fw_shared_init(adev, vcn_inst);</div><div class='add'>+</div><div class='ctx'> 		memset(&amp;header, 0, sizeof(struct mmsch_v4_0_3_init_header));</div><div class='ctx'> 		header.version = MMSCH_VERSION;</div><div class='ctx'> 		header.total_size = sizeof(struct mmsch_v4_0_3_init_header) &gt;&gt; 2;</div><div class='hunk'>@@ -894,7 +1038,7 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 		MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),</div><div class='ctx'> 			~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);</div><div class='ctx'> </div><div class='del'>-		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.fw[i]-&gt;size + 4);</div><div class='add'>+		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[i].fw-&gt;size + 4);</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='ctx'> 			MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='hunk'>@@ -1035,189 +1179,185 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_start - VCN start</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	int i, j, k, r, vcn_inst;</div><div class='add'>+	int j, k, r, vcn_inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v4_0_3_start_dpg_mode(vinst, adev-&gt;vcn.inst[i].indirect_sram);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v4_0_3_start_dpg_mode(adev, i, adev-&gt;vcn.indirect_sram);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	vcn_inst = GET_INST(VCN, i);</div><div class='add'>+	/* set VCN status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |</div><div class='add'>+		UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);</div><div class='ctx'> </div><div class='del'>-		vcn_inst = GET_INST(VCN, i);</div><div class='del'>-		/* set VCN status busy */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |</div><div class='del'>-		      UVD_STATUS__UVD_BUSY;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);</div><div class='del'>-</div><div class='del'>-		/*SW clock gating */</div><div class='del'>-		vcn_v4_0_3_disable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* enable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='del'>-			 UVD_VCPU_CNTL__CLK_EN_MASK,</div><div class='del'>-			 ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,</div><div class='del'>-			 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* enable LMI MC and UMC channels */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,</div><div class='del'>-			 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_LMI_CTRL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,</div><div class='del'>-			     tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='del'>-				     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='del'>-				     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='del'>-				     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_MPC_CNTL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);</div><div class='del'>-		tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='del'>-		tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXA0 */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,</div><div class='del'>-			     ((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='del'>-			      (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='del'>-			      (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='del'>-			      (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXB0 */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,</div><div class='del'>-			     ((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='del'>-			      (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='del'>-			      (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='del'>-			      (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUX */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,</div><div class='del'>-			     ((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='del'>-			      (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='del'>-			      (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='del'>-</div><div class='del'>-		vcn_v4_0_3_mc_resume(adev, i);</div><div class='del'>-</div><div class='del'>-		/* VCN global tiling registers */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,</div><div class='del'>-			     adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,</div><div class='del'>-			     adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* unblock VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,</div><div class='del'>-			 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='del'>-</div><div class='del'>-		/* release VCPU reset to boot */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='del'>-			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* SW clock gating */</div><div class='add'>+	vcn_v4_0_3_disable_clock_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; 10; ++j) {</div><div class='del'>-			uint32_t status;</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='ctx'> </div><div class='del'>-			for (k = 0; k &lt; 100; ++k) {</div><div class='del'>-				status = RREG32_SOC15(VCN, vcn_inst,</div><div class='del'>-						      regUVD_STATUS);</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-				mdelay(10);</div><div class='del'>-			}</div><div class='del'>-			r = 0;</div><div class='del'>-			if (status &amp; 2)</div><div class='del'>-				break;</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-			DRM_DEV_ERROR(adev-&gt;dev,</div><div class='del'>-				"VCN decode not responding, trying to reset the VCPU!!!\n");</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,</div><div class='del'>-						  regUVD_VCPU_CNTL),</div><div class='del'>-				 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-			mdelay(10);</div><div class='del'>-			WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,</div><div class='del'>-						  regUVD_VCPU_CNTL),</div><div class='del'>-				 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,</div><div class='add'>+		     tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_MPC_CNTL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);</div><div class='add'>+	tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='add'>+	tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXA0 */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXB0 */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUX */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,</div><div class='add'>+		     ((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='add'>+		      (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='add'>+</div><div class='add'>+	vcn_v4_0_3_mc_resume(vinst);</div><div class='add'>+</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='add'>+	for (j = 0; j &lt; 10; ++j) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; 100; ++k) {</div><div class='add'>+			status = RREG32_SOC15(VCN, vcn_inst,</div><div class='add'>+					      regUVD_STATUS);</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='ctx'> 			mdelay(10);</div><div class='del'>-			r = -1;</div><div class='ctx'> 		}</div><div class='add'>+		r = 0;</div><div class='add'>+		if (status &amp; 2)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-		if (r) {</div><div class='del'>-			DRM_DEV_ERROR(adev-&gt;dev, "VCN decode not responding, giving up!!!\n");</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+		DRM_DEV_ERROR(adev-&gt;dev,</div><div class='add'>+			      "VCN decode not responding, trying to reset the VCPU!!!\n");</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,</div><div class='add'>+					  regUVD_VCPU_CNTL),</div><div class='add'>+			 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,</div><div class='add'>+					  regUVD_VCPU_CNTL),</div><div class='add'>+			 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* enable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),</div><div class='del'>-			 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='del'>-			 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+		mdelay(10);</div><div class='add'>+		r = -1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* clear the busy bit of VCN_STATUS */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,</div><div class='del'>-			 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_DEV_ERROR(adev-&gt;dev, "VCN decode not responding, giving up!!!\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		/* program the RB_BASE for ring buffer */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,</div><div class='del'>-			     lower_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,</div><div class='del'>-			     upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='ctx'> </div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,</div><div class='del'>-			     ring-&gt;ring_size / sizeof(uint32_t));</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='del'>-		/* resetting ring, fw should not check RB ring */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='del'>-		tmp &amp;= ~(VCN_RB_ENABLE__RB_EN_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	/* program the RB_BASE for ring buffer */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,</div><div class='add'>+		     lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,</div><div class='add'>+		     upper_32_bits(ring-&gt;gpu_addr));</div><div class='ctx'> </div><div class='del'>-		/* Initialize the ring buffer's read and write pointers */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,</div><div class='add'>+		     ring-&gt;ring_size / sizeof(uint32_t));</div><div class='ctx'> </div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='del'>-		tmp |= VCN_RB_ENABLE__RB_EN_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	/* resetting ring, fw should not check RB ring */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='add'>+	tmp &amp;= ~(VCN_RB_ENABLE__RB_EN_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='ctx'> </div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode &amp;=</div><div class='del'>-			cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));</div><div class='add'>+	/* Initialize the ring buffer's read and write pointers */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='add'>+	tmp |= VCN_RB_ENABLE__RB_EN_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode &amp;=</div><div class='add'>+		cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));</div><div class='ctx'> </div><div class='del'>-	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> 	int vcn_inst;</div><div class='ctx'> </div><div class='hunk'>@@ -1237,106 +1377,114 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> 	/* disable dynamic power gating mode */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,</div><div class='ctx'> 		 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_stop - VCN stop</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='del'>-	int i, r = 0, vcn_inst;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	int r = 0, vcn_inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		vcn_inst = GET_INST(VCN, i);</div><div class='add'>+	vcn_inst = GET_INST(VCN, i);</div><div class='ctx'> </div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			vcn_v4_0_3_stop_dpg_mode(adev, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		vcn_v4_0_3_stop_dpg_mode(vinst);</div><div class='add'>+		goto Done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* wait for vcn idle */</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,</div><div class='del'>-				       UVD_STATUS__IDLE, 0x7);</div><div class='del'>-		if (r)</div><div class='del'>-			goto Done;</div><div class='del'>-</div><div class='del'>-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,</div><div class='del'>-				       tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			goto Done;</div><div class='del'>-</div><div class='del'>-		/* stall UMC channel */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);</div><div class='del'>-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);</div><div class='del'>-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='del'>-			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,</div><div class='del'>-				       tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			goto Done;</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,</div><div class='add'>+			       UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		goto Done;</div><div class='add'>+</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,</div><div class='add'>+			       tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto Done;</div><div class='add'>+</div><div class='add'>+	/* stall UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,</div><div class='add'>+			       tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto Done;</div><div class='ctx'> </div><div class='del'>-		/* Unblock VCPU Register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),</div><div class='del'>-			 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='del'>-			 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+	/* Unblock VCPU Register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='ctx'> </div><div class='del'>-		/* release VCPU reset to boot */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='del'>-			 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-			 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* disable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='del'>-			 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='ctx'> </div><div class='del'>-		/* reset LMI UMC/LMI/VCPU */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	/* reset LMI UMC/LMI/VCPU */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='ctx'> </div><div class='del'>-		tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='ctx'> </div><div class='del'>-		/* clear VCN status */</div><div class='del'>-		WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);</div><div class='add'>+	/* clear VCN status */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-		/* apply HW clock gating */</div><div class='del'>-		vcn_v4_0_3_enable_clock_gating(adev, i);</div><div class='del'>-	}</div><div class='del'>-Done:</div><div class='del'>-	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+	/* apply HW clock gating */</div><div class='add'>+	vcn_v4_0_3_enable_clock_gating(vinst);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+</div><div class='add'>+Done:</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @new_state: pause state</div><div class='ctx'>  *</div><div class='ctx'>  * Pause dpg mode for VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,</div><div class='del'>-				struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1380,6 +1528,51 @@ static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 				    regUVD_RB_WPTR);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+				       uint32_t val, uint32_t mask)</div><div class='add'>+{</div><div class='add'>+	/* Use normalized offsets when required */</div><div class='add'>+	if (vcn_v4_0_3_normalizn_reqd(ring-&gt;adev))</div><div class='add'>+		reg = NORMALIZE_VCN_REG_OFFSET(reg);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);</div><div class='add'>+	amdgpu_ring_write(ring, reg &lt;&lt; 2);</div><div class='add'>+	amdgpu_ring_write(ring, mask);</div><div class='add'>+	amdgpu_ring_write(ring, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+				   uint32_t val)</div><div class='add'>+{</div><div class='add'>+	/* Use normalized offsets when required */</div><div class='add'>+	if (vcn_v4_0_3_normalizn_reqd(ring-&gt;adev))</div><div class='add'>+		reg = NORMALIZE_VCN_REG_OFFSET(reg);</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);</div><div class='add'>+	amdgpu_ring_write(ring,	reg &lt;&lt; 2);</div><div class='add'>+	amdgpu_ring_write(ring, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='add'>+				       unsigned int vmid, uint64_t pd_addr)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vmhub *hub = &amp;ring-&gt;adev-&gt;vmhub[ring-&gt;vm_hub];</div><div class='add'>+</div><div class='add'>+	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);</div><div class='add'>+</div><div class='add'>+	/* wait for reg writes */</div><div class='add'>+	vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub-&gt;ctx0_ptb_addr_lo32 +</div><div class='add'>+					vmid * hub-&gt;ctx_addr_distance,</div><div class='add'>+					lower_32_bits(pd_addr), 0xffffffff);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	/* VCN engine access for HDP flush doesn't work when RRMT is enabled.</div><div class='add'>+	 * This is a workaround to avoid any HDP flush through VCN ring.</div><div class='add'>+	 */</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer</div><div class='ctx'>  *</div><div class='hunk'>@@ -1403,6 +1596,34 @@ static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+	int vcn_inst;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, ring-&gt;me);</div><div class='add'>+	r = amdgpu_dpm_reset_vcn(adev, 1 &lt;&lt; vcn_inst);</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_DEV_ERROR(adev-&gt;dev, "VCN reset fail : %d\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* This flag is not set for VF, assumed to be disabled always */</div><div class='add'>+	if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &amp; 0x100)</div><div class='add'>+		adev-&gt;vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);</div><div class='add'>+	vcn_v4_0_3_hw_init_inst(vinst);</div><div class='add'>+	vcn_v4_0_3_start_dpg_mode(vinst, adev-&gt;vcn.inst[ring-&gt;me].indirect_sram);</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {</div><div class='ctx'> 	.type = AMDGPU_RING_TYPE_VCN_ENC,</div><div class='ctx'> 	.align_mask = 0x3f,</div><div class='hunk'>@@ -1419,7 +1640,8 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {</div><div class='ctx'> 	.emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */</div><div class='ctx'> 	.emit_ib = vcn_v2_0_enc_ring_emit_ib,</div><div class='ctx'> 	.emit_fence = vcn_v2_0_enc_ring_emit_fence,</div><div class='del'>-	.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,</div><div class='add'>+	.emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush,</div><div class='ctx'> 	.test_ring = amdgpu_vcn_enc_ring_test_ring,</div><div class='ctx'> 	.test_ib = amdgpu_vcn_unified_ring_test_ib,</div><div class='ctx'> 	.insert_nop = amdgpu_ring_insert_nop,</div><div class='hunk'>@@ -1427,9 +1649,10 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {</div><div class='ctx'> 	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='ctx'> 	.begin_use = amdgpu_vcn_ring_begin_use,</div><div class='ctx'> 	.end_use = amdgpu_vcn_ring_end_use,</div><div class='del'>-	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='del'>-	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='add'>+	.emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = vcn_v4_0_3_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1450,19 +1673,18 @@ static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;vcn.inst[i].aid_id =</div><div class='ctx'> 			vcn_inst / adev-&gt;vcn.num_inst_per_aid;</div><div class='ctx'> 	}</div><div class='del'>-	DRM_DEV_INFO(adev-&gt;dev, "VCN decode is enabled in VM mode\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_is_idle - check VCN block is idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block structure</div><div class='ctx'>  *</div><div class='ctx'>  * Check whether VCN block is idle</div><div class='ctx'>  */</div><div class='del'>-static bool vcn_v4_0_3_is_idle(void *handle)</div><div class='add'>+static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1476,13 +1698,13 @@ static bool vcn_v4_0_3_is_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_wait_for_idle - wait for VCN block idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Wait for VCN block idle</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1497,64 +1719,58 @@ static int vcn_v4_0_3_wait_for_idle(void *handle)</div><div class='ctx'> </div><div class='ctx'> /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: amdgpu_ip_block pointer</div><div class='ctx'>  * @state: clock gating state</div><div class='ctx'>  *</div><div class='ctx'>  * Set VCN block clockgating state</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_3_set_clockgating_state(void *handle,</div><div class='add'>+static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (enable) {</div><div class='ctx'> 			if (RREG32_SOC15(VCN, GET_INST(VCN, i),</div><div class='ctx'> 					 regUVD_STATUS) != UVD_STATUS__IDLE)</div><div class='ctx'> 				return -EBUSY;</div><div class='del'>-			vcn_v4_0_3_enable_clock_gating(adev, i);</div><div class='add'>+			vcn_v4_0_3_enable_clock_gating(vinst);</div><div class='ctx'> 		} else {</div><div class='del'>-			vcn_v4_0_3_disable_clock_gating(adev, i);</div><div class='add'>+			vcn_v4_0_3_disable_clock_gating(vinst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * vcn_v4_0_3_set_powergating_state - set VCN block powergating state</div><div class='del'>- *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='del'>- * @state: power gating state</div><div class='del'>- *</div><div class='del'>- * Set VCN block powergating state</div><div class='del'>- */</div><div class='del'>-static int vcn_v4_0_3_set_powergating_state(void *handle,</div><div class='del'>-					  enum amd_powergating_state state)</div><div class='add'>+static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int ret;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* for SRIOV, guest should not control VCN Power-gating</div><div class='ctx'> 	 * MMSCH FW should control Power-gating and clock-gating</div><div class='ctx'> 	 * guest should avoid touching CGC and PG</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='del'>-		adev-&gt;vcn.cur_state = AMD_PG_STATE_UNGATE;</div><div class='add'>+		vinst-&gt;cur_state = AMD_PG_STATE_UNGATE;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v4_0_3_stop(adev);</div><div class='add'>+		ret = vcn_v4_0_3_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v4_0_3_start(adev);</div><div class='add'>+		ret = vcn_v4_0_3_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1620,11 +1836,24 @@ static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vcn_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_irq_src *source,</div><div class='add'>+					unsigned int type,</div><div class='add'>+					enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = {</div><div class='ctx'> 	.set = vcn_v4_0_3_set_interrupt_state,</div><div class='ctx'> 	.process = vcn_v4_0_3_process_interrupt,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_irq_src_funcs vcn_v4_0_3_ras_irq_funcs = {</div><div class='add'>+	.set = vcn_v4_0_3_set_ras_interrupt_state,</div><div class='add'>+	.process = amdgpu_vcn_process_poison_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions</div><div class='ctx'>  *</div><div class='hunk'>@@ -1640,12 +1869,15 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;vcn.inst-&gt;irq.num_types++;</div><div class='ctx'> 	}</div><div class='ctx'> 	adev-&gt;vcn.inst-&gt;irq.funcs = &amp;vcn_v4_0_3_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.inst-&gt;ras_poison_irq.num_types = 1;</div><div class='add'>+	adev-&gt;vcn.inst-&gt;ras_poison_irq.funcs = &amp;vcn_v4_0_3_ras_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v4_0_3",</div><div class='ctx'> 	.early_init = vcn_v4_0_3_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='add'>+	.late_init = vcn_v4_0_3_late_init,</div><div class='ctx'> 	.sw_init = vcn_v4_0_3_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v4_0_3_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v4_0_3_hw_init,</div><div class='hunk'>@@ -1654,12 +1886,10 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v4_0_3_resume,</div><div class='ctx'> 	.is_idle = vcn_v4_0_3_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v4_0_3_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v4_0_3_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {</div><div class='hunk'>@@ -1728,14 +1958,143 @@ static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)</div><div class='ctx'> 		vcn_v4_0_3_inst_reset_ras_error_count(adev, i);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev,</div><div class='add'>+			uint32_t instance, uint32_t sub_block)</div><div class='add'>+{</div><div class='add'>+	uint32_t poison_stat = 0, reg_value = 0;</div><div class='add'>+</div><div class='add'>+	switch (sub_block) {</div><div class='add'>+	case AMDGPU_VCN_V4_0_3_VCPU_VCODEC:</div><div class='add'>+		reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);</div><div class='add'>+		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (poison_stat)</div><div class='add'>+		dev_info(adev-&gt;dev, "Poison detected in VCN%d, sub_block%d\n",</div><div class='add'>+			instance, sub_block);</div><div class='add'>+</div><div class='add'>+	return poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t inst, sub;</div><div class='add'>+	uint32_t poison_stat = 0;</div><div class='add'>+</div><div class='add'>+	for (inst = 0; inst &lt; adev-&gt;vcn.num_vcn_inst; inst++)</div><div class='add'>+		for (sub = 0; sub &lt; AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK; sub++)</div><div class='add'>+			poison_stat +=</div><div class='add'>+			vcn_v4_0_3_query_poison_by_instance(adev, inst, sub);</div><div class='add'>+</div><div class='add'>+	return !!poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = {</div><div class='ctx'> 	.query_ras_error_count = vcn_v4_0_3_query_ras_error_count,</div><div class='ctx'> 	.reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count,</div><div class='add'>+	.query_poison_status = vcn_v4_0_3_query_poison_status,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				      enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE,</div><div class='add'>+						     1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* reference to smu driver if header file */</div><div class='add'>+static int vcn_v4_0_3_err_codes[] = {</div><div class='add'>+	14, 15, /* VCN */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+					 enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	u32 instlo;</div><div class='add'>+</div><div class='add'>+	instlo = ACA_REG__IPID__INSTANCEIDLO(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='add'>+</div><div class='add'>+	if (instlo != mmSMNAID_AID0_MCA_SMU)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (aca_bank_check_error_codes(handle-&gt;adev, bank,</div><div class='add'>+				       vcn_v4_0_3_err_codes,</div><div class='add'>+				       ARRAY_SIZE(vcn_v4_0_3_err_codes)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = {</div><div class='add'>+	.aca_bank_parser = vcn_v4_0_3_aca_bank_parser,</div><div class='add'>+	.aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct aca_info vcn_v4_0_3_aca_info = {</div><div class='add'>+	.hwip = ACA_HWIP_TYPE_SMU,</div><div class='add'>+	.mask = ACA_ERROR_UE_MASK,</div><div class='add'>+	.bank_ops = &amp;vcn_v4_0_3_aca_bank_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_block_late_init(adev, ras_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, ras_block-&gt;block) &amp;&amp;</div><div class='add'>+		adev-&gt;vcn.inst-&gt;ras_poison_irq.funcs) {</div><div class='add'>+		r = amdgpu_irq_get(adev, &amp;adev-&gt;vcn.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+		if (r)</div><div class='add'>+			goto late_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN,</div><div class='add'>+				&amp;vcn_v4_0_3_aca_info, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		goto late_fini;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+late_fini:</div><div class='add'>+	amdgpu_ras_block_late_fini(adev, ras_block);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct amdgpu_vcn_ras vcn_v4_0_3_ras = {</div><div class='ctx'> 	.ras_block = {</div><div class='ctx'> 		.hw_ops = &amp;vcn_v4_0_3_ras_hw_ops,</div><div class='add'>+		.ras_late_init = vcn_v4_0_3_ras_late_init,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h<br/>index 0b046114373a..aeab89853a92 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h</a></div><div class='hunk'>@@ -24,6 +24,21 @@</div><div class='ctx'> #ifndef __VCN_V4_0_3_H__</div><div class='ctx'> #define __VCN_V4_0_3_H__</div><div class='ctx'> </div><div class='add'>+enum amdgpu_vcn_v4_0_3_sub_block {</div><div class='add'>+	AMDGPU_VCN_V4_0_3_VCPU_VCODEC = 0,</div><div class='add'>+</div><div class='add'>+	AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> extern const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block;</div><div class='ctx'> </div><div class='add'>+void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+				       uint32_t val, uint32_t mask);</div><div class='add'>+</div><div class='add'>+void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,</div><div class='add'>+				   uint32_t val);</div><div class='add'>+void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,</div><div class='add'>+				       unsigned int vmid, uint64_t pd_addr);</div><div class='add'>+void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring);</div><div class='add'>+</div><div class='ctx'> #endif /* __VCN_V4_0_3_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c<br/>index 501e53e69f2a..b107ee80e472 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c</a></div><div class='hunk'>@@ -46,12 +46,49 @@</div><div class='ctx'> </div><div class='ctx'> #define VCN_VID_SOC_ADDRESS_2_0						0x1fb00</div><div class='ctx'> #define VCN1_VID_SOC_ADDRESS_3_0					(0x48300 + 0x38000)</div><div class='add'>+#define VCN1_AON_SOC_ADDRESS_3_0					(0x48000 + 0x38000)</div><div class='ctx'> </div><div class='ctx'> #define VCN_HARVEST_MMSCH							0</div><div class='ctx'> </div><div class='ctx'> #define RDECODE_MSG_CREATE							0x00000000</div><div class='ctx'> #define RDECODE_MESSAGE_CREATE						0x00000001</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN1</div><div class='hunk'>@@ -59,61 +96,74 @@ static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> </div><div class='ctx'> static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v4_0_5_set_powergating_state(void *handle,</div><div class='del'>-		enum amd_powergating_state state);</div><div class='del'>-static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-		int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state);</div><div class='add'>+static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state);</div><div class='ctx'> static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_early_init(void *handle)</div><div class='add'>+static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))</div><div class='add'>+		adev-&gt;vcn.per_inst_fw = true;</div><div class='ctx'> </div><div class='del'>-	/* re-use enc ring as unified ring */</div><div class='del'>-	adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		/* re-use enc ring as unified ring */</div><div class='add'>+		adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='ctx'> 	vcn_v4_0_5_set_unified_ring_funcs(adev);</div><div class='ctx'> 	vcn_v4_0_5_set_irq_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v4_0_5_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_sw_init(void *handle)</div><div class='add'>+static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+		struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='ctx'> 		atomic_set(&amp;adev-&gt;vcn.inst[i].sched_score, 0);</div><div class='ctx'> </div><div class='ctx'> 		/* VCN UNIFIED TRAP */</div><div class='hunk'>@@ -132,7 +182,7 @@ static int vcn_v4_0_5_sw_init(void *handle)</div><div class='ctx'> 		ring-&gt;use_doorbell = true;</div><div class='ctx'> 		if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 			ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='del'>-						i * (adev-&gt;vcn.num_enc_rings + 1) + 1;</div><div class='add'>+						i * (adev-&gt;vcn.inst[i].num_enc_rings + 1) + 1;</div><div class='ctx'> 		else</div><div class='ctx'> 			ring-&gt;doorbell_index = (adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='ctx'> 						2 + 8 * i;</div><div class='hunk'>@@ -155,37 +205,51 @@ static int vcn_v4_0_5_sw_init(void *handle)</div><div class='ctx'> 		if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 			fw_shared-&gt;present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);</div><div class='ctx'> </div><div class='add'>+		fw_shared-&gt;present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;</div><div class='add'>+		fw_shared-&gt;drm_key_wa.method =</div><div class='add'>+			AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;</div><div class='add'>+</div><div class='ctx'> 		if (amdgpu_vcnfw_log)</div><div class='ctx'> 			amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[i]);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+			adev-&gt;vcn.inst[i].pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		r = amdgpu_virt_alloc_mm_table(adev);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;</div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_5, ARRAY_SIZE(vcn_reg_list_4_0_5));</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_sw_fini(void *handle)</div><div class='add'>+static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-			volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+			struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='hunk'>@@ -201,25 +265,27 @@ static int vcn_v4_0_5_sw_fini(void *handle)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_free_mm_table(adev);</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_hw_init(void *handle)</div><div class='add'>+static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='hunk'>@@ -234,39 +300,37 @@ static int vcn_v4_0_5_hw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_hw_fini(void *handle)</div><div class='add'>+static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='add'>+</div><div class='add'>+		cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='add'>+</div><div class='ctx'> 		if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 			if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='del'>-				(adev-&gt;vcn.cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='del'>-				RREG32_SOC15(VCN, i, regUVD_STATUS))) {</div><div class='del'>-				vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);</div><div class='add'>+			    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+			     RREG32_SOC15(VCN, i, regUVD_STATUS))) {</div><div class='add'>+				vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -277,20 +341,24 @@ static int vcn_v4_0_5_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_suspend(void *handle)</div><div class='add'>+static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v4_0_5_hw_fini(adev);</div><div class='add'>+	r = vcn_v4_0_5_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -298,20 +366,22 @@ static int vcn_v4_0_5_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_resume(void *handle)</div><div class='add'>+static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v4_0_5_hw_init(adev);</div><div class='add'>+	r = vcn_v4_0_5_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -319,17 +389,18 @@ static int vcn_v4_0_5_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_5_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -379,18 +450,20 @@ static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_mc_resume_dpg_mode - memory controller programming for dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					  bool indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst_idx]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst_idx].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -493,13 +566,14 @@ static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_disable_static_power_gating - disable VCN static power gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable static power gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -552,13 +626,14 @@ static void vcn_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, i</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_enable_static_power_gating - enable VCN static power gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable static power gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -594,13 +669,14 @@ static void vcn_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, in</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -705,16 +781,18 @@ static void vcn_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @sram_sel: sram select</div><div class='del'>- * @inst_idx: instance number index</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,</div><div class='del'>-		int inst_idx, uint8_t indirect)</div><div class='add'>+static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+						     uint8_t sram_sel,</div><div class='add'>+						     uint8_t indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -762,13 +840,14 @@ static void vcn_v4_0_5_disable_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;cg_flags &amp; AMD_CG_SUPPORT_VCN_MGCG)</div><div class='hunk'>@@ -821,17 +900,20 @@ static void vcn_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_start_dpg_mode - VCN start with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* disable register anti-hang mechanism */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,</div><div class='hunk'>@@ -847,7 +929,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 					(uint32_t *)adev-&gt;vcn.inst[inst_idx].dpg_sram_cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock gating */</div><div class='del'>-	vcn_v4_0_5_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* enable VCPU clock */</div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='hunk'>@@ -895,7 +977,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 		 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='ctx'> 		 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v4_0_5_mc_resume_dpg_mode(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='ctx'> 	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;</div><div class='hunk'>@@ -912,8 +994,13 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 		VCN, inst_idx, regUVD_MASTINT_EN),</div><div class='ctx'> 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_enc[0];</div><div class='ctx'> </div><div class='hunk'>@@ -941,6 +1028,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 			ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='ctx'> 			VCN_RB1_DB_CTRL__EN_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done, otherwise</div><div class='add'>+	 * it may introduce race conditions */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -948,179 +1039,184 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_start - VCN start</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, j, k, r;</div><div class='add'>+	int j, k, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, true, i);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v4_0_5_start_dpg_mode(adev, i, adev-&gt;vcn.indirect_sram);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v4_0_5_start_dpg_mode(vinst, adev-&gt;vcn.inst[i].indirect_sram);</div><div class='ctx'> </div><div class='del'>-		/* disable VCN power gating */</div><div class='del'>-		vcn_v4_0_5_disable_static_power_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* set VCN status busy */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);</div><div class='del'>-</div><div class='del'>-		/*SW clock gating */</div><div class='del'>-		vcn_v4_0_5_disable_clock_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* enable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-				UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,</div><div class='del'>-				~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* enable LMI MC and UMC channels */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,</div><div class='del'>-				~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_LMI_CTRL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |</div><div class='del'>-				UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='del'>-				UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='del'>-				UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='del'>-				UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_MPC_CNTL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);</div><div class='del'>-		tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='del'>-		tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXA0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,</div><div class='del'>-				((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='del'>-				 (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='del'>-				 (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='del'>-				 (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUXB0 */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,</div><div class='del'>-				((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='del'>-				 (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='del'>-				 (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='del'>-				 (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='del'>-</div><div class='del'>-		/* setup UVD_MPC_SET_MUX */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,</div><div class='del'>-				((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='del'>-				 (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='del'>-				 (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='del'>-</div><div class='del'>-		vcn_v4_0_5_mc_resume(adev, i);</div><div class='del'>-</div><div class='del'>-		/* VCN global tiling registers */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,</div><div class='del'>-				adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* unblock VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,</div><div class='del'>-				~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='del'>-</div><div class='del'>-		/* release VCPU reset to boot */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-		for (j = 0; j &lt; 10; ++j) {</div><div class='del'>-			uint32_t status;</div><div class='del'>-</div><div class='del'>-			for (k = 0; k &lt; 100; ++k) {</div><div class='del'>-				status = RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-				mdelay(10);</div><div class='del'>-				if (amdgpu_emu_mode == 1)</div><div class='del'>-					msleep(1);</div><div class='del'>-			}</div><div class='add'>+	/* disable VCN power gating */</div><div class='add'>+	vcn_v4_0_5_disable_static_power_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* set VCN status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);</div><div class='add'>+</div><div class='add'>+	/* SW clock gating */</div><div class='add'>+	vcn_v4_0_5_disable_clock_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-			if (amdgpu_emu_mode == 1) {</div><div class='del'>-				r = -1;</div><div class='del'>-				if (status &amp; 2) {</div><div class='del'>-					r = 0;</div><div class='del'>-					break;</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |</div><div class='add'>+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_MPC_CNTL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);</div><div class='add'>+	tmp &amp;= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;</div><div class='add'>+	tmp |= 0x2 &lt;&lt; UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXA0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUXB0 */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,</div><div class='add'>+		     ((0x1 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |</div><div class='add'>+		      (0x3 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |</div><div class='add'>+		      (0x4 &lt;&lt; UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));</div><div class='add'>+</div><div class='add'>+	/* setup UVD_MPC_SET_MUX */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,</div><div class='add'>+		     ((0x0 &lt;&lt; UVD_MPC_SET_MUX__SET_0__SHIFT) |</div><div class='add'>+		      (0x1 &lt;&lt; UVD_MPC_SET_MUX__SET_1__SHIFT) |</div><div class='add'>+		      (0x2 &lt;&lt; UVD_MPC_SET_MUX__SET_2__SHIFT)));</div><div class='add'>+</div><div class='add'>+	vcn_v4_0_5_mc_resume(vinst);</div><div class='add'>+</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; 10; ++j) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; 100; ++k) {</div><div class='add'>+			status = RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+			mdelay(10);</div><div class='add'>+			if (amdgpu_emu_mode == 1)</div><div class='add'>+				msleep(1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode == 1) {</div><div class='add'>+			r = -1;</div><div class='add'>+			if (status &amp; 2) {</div><div class='ctx'> 				r = 0;</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-</div><div class='del'>-				dev_err(adev-&gt;dev,</div><div class='del'>-					"VCN[%d] is not responding, trying to reset VCPU!!!\n", i);</div><div class='del'>-				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-							UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-							~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-				mdelay(10);</div><div class='del'>-				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-						~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-				mdelay(10);</div><div class='del'>-				r = -1;</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='add'>+		} else {</div><div class='add'>+			r = 0;</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"VCN[%d] is not responding, trying to reset VCPU!!!\n", i);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+				 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+			mdelay(10);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+			mdelay(10);</div><div class='add'>+			r = -1;</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* enable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),</div><div class='del'>-				UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='del'>-				~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		/* clear the busy bit of VCN_STATUS */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,</div><div class='del'>-				~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='ctx'> </div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,</div><div class='del'>-				ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='del'>-				VCN_RB1_DB_CTRL__EN_MASK);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='del'>-		tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);</div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='del'>-		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='del'>-	}</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,</div><div class='add'>+		     ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		     VCN_RB1_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='add'>+	tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='add'>+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done, otherwise</div><div class='add'>+	 * it may introduce race conditions */</div><div class='add'>+	RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1128,13 +1224,14 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_stop_dpg_mode - VCN stop with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for power status to be 1 */</div><div class='hunk'>@@ -1151,103 +1248,119 @@ static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> 	/* disable dynamic power gating mode */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,</div><div class='ctx'> 		~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_stop - VCN stop</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, r = 0;</div><div class='add'>+	int r = 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			vcn_v4_0_5_stop_dpg_mode(adev, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='ctx'> </div><div class='del'>-		/* wait for vcn idle */</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		vcn_v4_0_5_stop_dpg_mode(vinst);</div><div class='add'>+		r = 0;</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='del'>-			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* disable LMI UMC channel */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);</div><div class='del'>-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);</div><div class='del'>-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='del'>-			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='add'>+</div><div class='add'>+	/* disable LMI UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* block VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),</div><div class='del'>-				UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='del'>-				~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+	/* block VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='ctx'> </div><div class='del'>-		/* reset VCPU */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-				UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-				~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+	/* reset VCPU */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='ctx'> </div><div class='del'>-		/* disable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-				~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='ctx'> </div><div class='del'>-		/* apply soft reset */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	/* apply soft reset */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='ctx'> </div><div class='del'>-		/* clear status */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_STATUS, 0);</div><div class='add'>+	/* clear status */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_STATUS, 0);</div><div class='ctx'> </div><div class='del'>-		/* apply HW clock gating */</div><div class='del'>-		vcn_v4_0_5_enable_clock_gating(adev, i);</div><div class='add'>+	/* apply HW clock gating */</div><div class='add'>+	vcn_v4_0_5_enable_clock_gating(vinst);</div><div class='ctx'> </div><div class='del'>-		/* enable VCN power gating */</div><div class='del'>-		vcn_v4_0_5_enable_static_power_gating(adev, i);</div><div class='del'>-	}</div><div class='add'>+	/* enable VCN power gating */</div><div class='add'>+	vcn_v4_0_5_enable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='add'>+</div><div class='add'>+done:</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, false, i);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @new_state: pause state</div><div class='ctx'>  *</div><div class='ctx'>  * Pause dpg mode for VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,</div><div class='del'>-		struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	int ret_code;</div><div class='ctx'> </div><div class='hunk'>@@ -1346,178 +1459,31 @@ static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vcn_v4_0_5_limit_sched(struct amdgpu_cs_parser *p,</div><div class='del'>-				struct amdgpu_job *job)</div><div class='del'>-{</div><div class='del'>-	struct drm_gpu_scheduler **scheds;</div><div class='del'>-</div><div class='del'>-	/* The create msg must be in the first IB submitted */</div><div class='del'>-	if (atomic_read(&amp;job-&gt;base.entity-&gt;fence_seq))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	/* if VCN0 is harvested, we can't support AV1 */</div><div class='del'>-	if (p-&gt;adev-&gt;vcn.harvest_config &amp; AMDGPU_VCN_HARVEST_VCN0)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	scheds = p-&gt;adev-&gt;gpu_sched[AMDGPU_HW_IP_VCN_ENC]</div><div class='del'>-		[AMDGPU_RING_PRIO_0].sched;</div><div class='del'>-	drm_sched_entity_modify_sched(job-&gt;base.entity, scheds, 1);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vcn_v4_0_5_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,</div><div class='del'>-			    uint64_t addr)</div><div class='add'>+static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='ctx'> {</div><div class='del'>-	struct ttm_operation_ctx ctx = { false, false };</div><div class='del'>-	struct amdgpu_bo_va_mapping *map;</div><div class='del'>-	uint32_t *msg, num_buffers;</div><div class='del'>-	struct amdgpu_bo *bo;</div><div class='del'>-	uint64_t start, end;</div><div class='del'>-	unsigned int i;</div><div class='del'>-	void *ptr;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	addr &amp;= AMDGPU_GMC_HOLE_MASK;</div><div class='del'>-	r = amdgpu_cs_find_mapping(p, addr, &amp;bo, &amp;map);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);</div><div class='del'>-		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	start = map-&gt;start * AMDGPU_GPU_PAGE_SIZE;</div><div class='del'>-	end = (map-&gt;last + 1) * AMDGPU_GPU_PAGE_SIZE;</div><div class='del'>-	if (addr &amp; 0x7) {</div><div class='del'>-		DRM_ERROR("VCN messages must be 8 byte aligned!\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	bo-&gt;flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;</div><div class='del'>-	amdgpu_bo_placement_from_domain(bo, bo-&gt;allowed_domains);</div><div class='del'>-	r = ttm_bo_validate(&amp;bo-&gt;tbo, &amp;bo-&gt;placement, &amp;ctx);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = vcn_v4_0_5_stop(vinst);</div><div class='add'>+	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	r = amdgpu_bo_kmap(bo, &amp;ptr);</div><div class='del'>-	if (r) {</div><div class='del'>-		DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);</div><div class='add'>+	r = vcn_v4_0_5_start(vinst);</div><div class='add'>+	if (r)</div><div class='ctx'> 		return r;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	msg = ptr + addr - start;</div><div class='del'>-</div><div class='del'>-	/* Check length */</div><div class='del'>-	if (msg[1] &gt; end - addr) {</div><div class='del'>-		r = -EINVAL;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (msg[3] != RDECODE_MSG_CREATE)</div><div class='del'>-		goto out;</div><div class='del'>-</div><div class='del'>-	num_buffers = msg[2];</div><div class='del'>-	for (i = 0, msg = &amp;msg[6]; i &lt; num_buffers; ++i, msg += 4) {</div><div class='del'>-		uint32_t offset, size, *create;</div><div class='del'>-</div><div class='del'>-		if (msg[0] != RDECODE_MESSAGE_CREATE)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		offset = msg[1];</div><div class='del'>-		size = msg[2];</div><div class='del'>-</div><div class='del'>-		if (offset + size &gt; end) {</div><div class='del'>-			r = -EINVAL;</div><div class='del'>-			goto out;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		create = ptr + addr + offset - start;</div><div class='del'>-</div><div class='del'>-		/* H264, HEVC and VP9 can run on any instance */</div><div class='del'>-		if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r = vcn_v4_0_5_limit_sched(p, job);</div><div class='del'>-		if (r)</div><div class='del'>-			goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	amdgpu_bo_kunmap(bo);</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#define RADEON_VCN_ENGINE_TYPE_ENCODE			(0x00000002)</div><div class='del'>-#define RADEON_VCN_ENGINE_TYPE_DECODE			(0x00000003)</div><div class='del'>-</div><div class='del'>-#define RADEON_VCN_ENGINE_INFO				(0x30000001)</div><div class='del'>-#define RADEON_VCN_ENGINE_INFO_MAX_OFFSET		16</div><div class='del'>-</div><div class='del'>-#define RENCODE_ENCODE_STANDARD_AV1			2</div><div class='del'>-#define RENCODE_IB_PARAM_SESSION_INIT			0x00000003</div><div class='del'>-#define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET	64</div><div class='del'>-</div><div class='del'>-/* return the offset in ib if id is found, -1 otherwise</div><div class='del'>- * to speed up the searching we only search upto max_offset</div><div class='del'>- */</div><div class='del'>-static int vcn_v4_0_5_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ib-&gt;length_dw &amp;&amp; i &lt; max_offset &amp;&amp; ib-&gt;ptr[i] &gt;= 8; i += ib-&gt;ptr[i]/4) {</div><div class='del'>-		if (ib-&gt;ptr[i + 1] == id)</div><div class='del'>-			return i;</div><div class='del'>-	}</div><div class='del'>-	return -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vcn_v4_0_5_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,</div><div class='del'>-					   struct amdgpu_job *job,</div><div class='del'>-					   struct amdgpu_ib *ib)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_ring *ring = amdgpu_job_ring(job);</div><div class='del'>-	struct amdgpu_vcn_decode_buffer *decode_buffer;</div><div class='del'>-	uint64_t addr;</div><div class='del'>-	uint32_t val;</div><div class='del'>-	int idx;</div><div class='del'>-</div><div class='del'>-	/* The first instance can decode anything */</div><div class='del'>-	if (!ring-&gt;me)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* RADEON_VCN_ENGINE_INFO is at the top of ib block */</div><div class='del'>-	idx = vcn_v4_0_5_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,</div><div class='del'>-			RADEON_VCN_ENGINE_INFO_MAX_OFFSET);</div><div class='del'>-	if (idx &lt; 0) /* engine info is missing */</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */</div><div class='del'>-	if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {</div><div class='del'>-		decode_buffer = (struct amdgpu_vcn_decode_buffer *)&amp;ib-&gt;ptr[idx + 6];</div><div class='del'>-</div><div class='del'>-		if (!(decode_buffer-&gt;valid_buf_flag  &amp; 0x1))</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='del'>-		addr = ((u64)decode_buffer-&gt;msg_buffer_address_hi) &lt;&lt; 32 |</div><div class='del'>-			decode_buffer-&gt;msg_buffer_address_lo;</div><div class='del'>-		return vcn_v4_0_5_dec_msg(p, job, addr);</div><div class='del'>-	} else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {</div><div class='del'>-		idx = vcn_v4_0_5_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,</div><div class='del'>-			RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);</div><div class='del'>-		if (idx &gt;= 0 &amp;&amp; ib-&gt;ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)</div><div class='del'>-			return vcn_v4_0_5_limit_sched(p, job);</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {</div><div class='add'>+static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {</div><div class='ctx'> 	.type = AMDGPU_RING_TYPE_VCN_ENC,</div><div class='ctx'> 	.align_mask = 0x3f,</div><div class='ctx'> 	.nop = VCN_ENC_CMD_NO_OP,</div><div class='ctx'> 	.get_rptr = vcn_v4_0_5_unified_ring_get_rptr,</div><div class='ctx'> 	.get_wptr = vcn_v4_0_5_unified_ring_get_wptr,</div><div class='ctx'> 	.set_wptr = vcn_v4_0_5_unified_ring_set_wptr,</div><div class='del'>-	.patch_cs_in_place = vcn_v4_0_5_ring_patch_cs_in_place,</div><div class='ctx'> 	.emit_frame_size =</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +</div><div class='ctx'> 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +</div><div class='hunk'>@@ -1538,6 +1504,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = vcn_v4_0_5_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1555,23 +1522,24 @@ static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5))</div><div class='add'>+			vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true;</div><div class='add'>+</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_enc[0].funcs = &amp;vcn_v4_0_5_unified_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_enc[0].me = i;</div><div class='del'>-</div><div class='del'>-		DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_is_idle - check VCN block is idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block structure</div><div class='ctx'>  *</div><div class='ctx'>  * Check whether VCN block is idle</div><div class='ctx'>  */</div><div class='del'>-static bool vcn_v4_0_5_is_idle(void *handle)</div><div class='add'>+static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1587,13 +1555,13 @@ static bool vcn_v4_0_5_is_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_wait_for_idle - wait for VCN block idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Wait for VCN block idle</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1612,56 +1580,51 @@ static int vcn_v4_0_5_wait_for_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_5_set_clockgating_state - set VCN block clockgating state</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: amdgpu_ip_block pointer</div><div class='ctx'>  * @state: clock gating state</div><div class='ctx'>  *</div><div class='ctx'>  * Set VCN block clockgating state</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_state state)</div><div class='add'>+static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (enable) {</div><div class='ctx'> 			if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)</div><div class='ctx'> 				return -EBUSY;</div><div class='del'>-			vcn_v4_0_5_enable_clock_gating(adev, i);</div><div class='add'>+			vcn_v4_0_5_enable_clock_gating(vinst);</div><div class='ctx'> 		} else {</div><div class='del'>-			vcn_v4_0_5_disable_clock_gating(adev, i);</div><div class='add'>+			vcn_v4_0_5_disable_clock_gating(vinst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * vcn_v4_0_5_set_powergating_state - set VCN block powergating state</div><div class='del'>- *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='del'>- * @state: power gating state</div><div class='del'>- *</div><div class='del'>- * Set VCN block powergating state</div><div class='del'>- */</div><div class='del'>-static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)</div><div class='add'>+static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v4_0_5_stop(adev);</div><div class='add'>+		ret = vcn_v4_0_5_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v4_0_5_start(adev);</div><div class='add'>+		ret = vcn_v4_0_5_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1729,7 +1692,7 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].irq.funcs = &amp;vcn_v4_0_5_irq_funcs;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1737,7 +1700,6 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v4_0_5",</div><div class='ctx'> 	.early_init = vcn_v4_0_5_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v4_0_5_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v4_0_5_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v4_0_5_hw_init,</div><div class='hunk'>@@ -1746,12 +1708,10 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v4_0_5_resume,</div><div class='ctx'> 	.is_idle = vcn_v4_0_5_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v4_0_5_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v4_0_5_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v4_0_5_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c<br/>index bc60c554eb32..0202df5db1e1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c</a></div><div class='hunk'>@@ -32,11 +32,45 @@</div><div class='ctx'> </div><div class='ctx'> #include "vcn/vcn_5_0_0_offset.h"</div><div class='ctx'> #include "vcn/vcn_5_0_0_sh_mask.h"</div><div class='del'>-#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"</div><div class='add'>+#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"</div><div class='ctx'> #include "vcn_v5_0_0.h"</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN,</div><div class='ctx'> 	SOC15_IH_CLIENTID_VCN1</div><div class='hunk'>@@ -44,73 +78,83 @@ static int amdgpu_ih_clientid_vcns[] = {</div><div class='ctx'> </div><div class='ctx'> static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);</div><div class='del'>-static int vcn_v5_0_0_set_powergating_state(void *handle,</div><div class='del'>-		enum amd_powergating_state state);</div><div class='del'>-static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,</div><div class='del'>-		int inst_idx, struct dpg_pause_state *new_state);</div><div class='add'>+static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state);</div><div class='add'>+static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state);</div><div class='ctx'> static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_early_init - set function pointers and load microcode</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Set ring and irq function pointers</div><div class='ctx'>  * Load microcode from filesystem</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_early_init(void *handle)</div><div class='add'>+static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='ctx'> </div><div class='del'>-	/* re-use enc ring as unified ring */</div><div class='del'>-	adev-&gt;vcn.num_enc_rings = 1;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		/* re-use enc ring as unified ring */</div><div class='add'>+		adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='ctx'> </div><div class='ctx'> 	vcn_v5_0_0_set_unified_ring_funcs(adev);</div><div class='ctx'> 	vcn_v5_0_0_set_irq_funcs(adev);</div><div class='ctx'> </div><div class='del'>-	return amdgpu_vcn_early_init(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v5_0_0_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Load firmware and sw initialization</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_sw_init(void *handle)</div><div class='add'>+static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_init(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='del'>-	amdgpu_vcn_setup_ucode(adev);</div><div class='del'>-</div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+		struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='ctx'> 		atomic_set(&amp;adev-&gt;vcn.inst[i].sched_score, 0);</div><div class='ctx'> </div><div class='ctx'> 		/* VCN UNIFIED TRAP */</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],</div><div class='del'>-				VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &amp;adev-&gt;vcn.inst[i].irq);</div><div class='add'>+				VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &amp;adev-&gt;vcn.inst[i].irq);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='ctx'> 		/* VCN POISON TRAP */</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],</div><div class='del'>-				VCN_4_0__SRCID_UVD_POISON, &amp;adev-&gt;vcn.inst[i].irq);</div><div class='add'>+				VCN_5_0__SRCID_UVD_POISON, &amp;adev-&gt;vcn.inst[i].irq);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='hunk'>@@ -132,10 +176,23 @@ static int vcn_v5_0_0_sw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_vcnfw_log)</div><div class='ctx'> 			amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[i]);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+			adev-&gt;vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='del'>-		adev-&gt;vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;</div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0, ARRAY_SIZE(vcn_reg_list_5_0));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -143,18 +200,18 @@ static int vcn_v5_0_0_sw_init(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_sw_fini - sw fini for VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * VCN suspend and free up sw allocation</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_sw_fini(void *handle)</div><div class='add'>+static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, r, idx;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-			volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+			struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='ctx'> </div><div class='ctx'> 			if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 				continue;</div><div class='hunk'>@@ -167,25 +224,30 @@ static int vcn_v5_0_0_sw_fini(void *handle)</div><div class='ctx'> 		drm_dev_exit(idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_sw_fini(adev);</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_hw_init - start and test VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the hardware, boot up the VCPU and do some testing</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_hw_init(void *handle)</div><div class='add'>+static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	int i, r;</div><div class='ctx'> </div><div class='hunk'>@@ -200,36 +262,39 @@ static int vcn_v5_0_0_hw_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 		if (r)</div><div class='del'>-			goto done;</div><div class='add'>+			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-done:</div><div class='del'>-	if (!r)</div><div class='del'>-		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",</div><div class='del'>-			(adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_hw_fini - stop the hardware block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Stop the VCN block, mark ring as not ready any more</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_hw_fini(void *handle)</div><div class='add'>+static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;adev-&gt;vcn.idle_work);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		amdgpu_irq_put(adev, &amp;adev-&gt;vcn.inst[i].irq, 0);</div><div class='add'>+		cancel_delayed_work_sync(&amp;vinst-&gt;idle_work);</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+			if ((adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) ||</div><div class='add'>+			    (vinst-&gt;cur_state != AMD_PG_STATE_GATE &amp;&amp;</div><div class='add'>+			     RREG32_SOC15(VCN, i, regUVD_STATUS))) {</div><div class='add'>+				vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -238,20 +303,24 @@ static int vcn_v5_0_0_hw_fini(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_suspend - suspend VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * HW fini and suspend VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_suspend(void *handle)</div><div class='add'>+static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = vcn_v5_0_0_hw_fini(adev);</div><div class='add'>+	r = vcn_v5_0_0_hw_fini(ip_block);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_suspend(adev);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -259,20 +328,22 @@ static int vcn_v5_0_0_suspend(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_resume - resume VCN block</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Resume firmware and hw init VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_resume(void *handle)</div><div class='add'>+static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_vcn_resume(adev);</div><div class='del'>-	if (r)</div><div class='del'>-		return r;</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	r = vcn_v5_0_0_hw_init(adev);</div><div class='add'>+	r = vcn_v5_0_0_hw_init(ip_block);</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -280,17 +351,18 @@ static int vcn_v5_0_0_resume(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_mc_resume - memory controller programming</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v5_0_0_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -334,24 +406,26 @@ static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst)</div><div class='ctx'> 		upper_32_bits(adev-&gt;vcn.inst[inst].fw_shared.gpu_addr));</div><div class='ctx'> 	WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);</div><div class='ctx'> 	WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,</div><div class='del'>-		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));</div><div class='add'>+		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Let the VCN memory controller know it's offsets with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					  bool indirect)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t offset, size;</div><div class='ctx'> 	const struct common_firmware_header *hdr;</div><div class='ctx'> </div><div class='del'>-	hdr = (const struct common_firmware_header *)adev-&gt;vcn.fw[inst_idx]-&gt;data;</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst_idx].fw-&gt;data;</div><div class='ctx'> 	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='ctx'> </div><div class='ctx'> 	/* cache window 0: fw */</div><div class='hunk'>@@ -438,11 +512,12 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i</div><div class='ctx'> 		VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);</div><div class='ctx'> 	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),</div><div class='del'>-		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);</div><div class='add'>+		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	/* VCN global tiling registers */</div><div class='ctx'> 	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='del'>-		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev-&gt;gfx.config.gb_addr_config, 0, indirect);</div><div class='add'>+		VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),</div><div class='add'>+		adev-&gt;gfx.config.gb_addr_config, 0, indirect);</div><div class='ctx'> </div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='hunk'>@@ -450,13 +525,14 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable static power gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -517,13 +593,14 @@ static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, i</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable static power gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t data;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN) {</div><div class='hunk'>@@ -563,12 +640,11 @@ static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, in</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_disable_clock_gating - disable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='hunk'>@@ -577,15 +653,15 @@ static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @sram_sel: sram select</div><div class='del'>- * @inst_idx: instance number index</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Disable clock gating for VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,</div><div class='del'>-	int inst_idx, uint8_t indirect)</div><div class='add'>+static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+						     uint8_t sram_sel,</div><div class='add'>+						     uint8_t indirect)</div><div class='ctx'> {</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='hunk'>@@ -594,12 +670,11 @@ static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev,</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_enable_clock_gating - enable VCN clock gating</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst: instance number</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Enable clock gating for VCN block</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='add'>+static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='hunk'>@@ -607,17 +682,20 @@ static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @indirect: indirectly write sram</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)</div><div class='add'>+static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     bool indirect)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* disable register anti-hang mechanism */</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,</div><div class='hunk'>@@ -654,7 +732,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='ctx'> 		VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	vcn_v5_0_0_mc_resume_dpg_mode(adev, inst_idx, indirect);</div><div class='add'>+	vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect);</div><div class='ctx'> </div><div class='ctx'> 	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='ctx'> 	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;</div><div class='hunk'>@@ -671,8 +749,13 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 		VCN, inst_idx, regUVD_MASTINT_EN),</div><div class='ctx'> 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='ctx'> </div><div class='del'>-	if (indirect)</div><div class='del'>-		amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "%s: vcn sram load failed %d\n", __func__, ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_enc[0];</div><div class='ctx'> </div><div class='hunk'>@@ -700,156 +783,167 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b</div><div class='ctx'> 		ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='ctx'> 		VCN_RB1_DB_CTRL__EN_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_start - VCN start</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Start VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_start(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='ctx'> 	struct amdgpu_ring *ring;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, j, k, r;</div><div class='add'>+	int j, k, r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, true);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, true, i);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			r = vcn_v5_0_0_start_dpg_mode(adev, i, adev-&gt;vcn.indirect_sram);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v5_0_0_start_dpg_mode(vinst, adev-&gt;vcn.inst[i].indirect_sram);</div><div class='ctx'> </div><div class='del'>-		/* disable VCN power gating */</div><div class='del'>-		vcn_v5_0_0_disable_static_power_gating(adev, i);</div><div class='del'>-</div><div class='del'>-		/* set VCN status busy */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);</div><div class='del'>-</div><div class='del'>-		/* enable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,</div><div class='del'>-			~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='del'>-</div><div class='del'>-		/* enable LMI MC and UMC channels */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,</div><div class='del'>-			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-</div><div class='del'>-		/* setup regUVD_LMI_CTRL */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |</div><div class='del'>-			UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='del'>-			UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='del'>-			UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='del'>-			UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='del'>-</div><div class='del'>-		vcn_v5_0_0_mc_resume(adev, i);</div><div class='del'>-</div><div class='del'>-		/* VCN global tiling registers */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,</div><div class='del'>-			adev-&gt;gfx.config.gb_addr_config);</div><div class='del'>-</div><div class='del'>-		/* unblock VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,</div><div class='del'>-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='del'>-</div><div class='del'>-		/* release VCPU reset to boot */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-			~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-		for (j = 0; j &lt; 10; ++j) {</div><div class='del'>-			uint32_t status;</div><div class='del'>-</div><div class='del'>-			for (k = 0; k &lt; 100; ++k) {</div><div class='del'>-				status = RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-				mdelay(10);</div><div class='del'>-				if (amdgpu_emu_mode == 1)</div><div class='del'>-					msleep(1);</div><div class='del'>-			}</div><div class='add'>+	/* disable VCN power gating */</div><div class='add'>+	vcn_v5_0_0_disable_static_power_gating(vinst);</div><div class='add'>+</div><div class='add'>+	/* set VCN status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);</div><div class='ctx'> </div><div class='del'>-			if (amdgpu_emu_mode == 1) {</div><div class='del'>-				r = -1;</div><div class='del'>-				if (status &amp; 2) {</div><div class='del'>-					r = 0;</div><div class='del'>-					break;</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |</div><div class='add'>+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	vcn_v5_0_0_mc_resume(vinst);</div><div class='add'>+</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; 10; ++j) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; 100; ++k) {</div><div class='add'>+			status = RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+			mdelay(10);</div><div class='add'>+			if (amdgpu_emu_mode == 1)</div><div class='add'>+				msleep(1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode == 1) {</div><div class='add'>+			r = -1;</div><div class='add'>+			if (status &amp; 2) {</div><div class='ctx'> 				r = 0;</div><div class='del'>-				if (status &amp; 2)</div><div class='del'>-					break;</div><div class='del'>-</div><div class='del'>-				dev_err(adev-&gt;dev,</div><div class='del'>-					"VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);</div><div class='del'>-				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-							UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-							~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-				mdelay(10);</div><div class='del'>-				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-							~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-				mdelay(10);</div><div class='del'>-				r = -1;</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='add'>+		} else {</div><div class='add'>+			r = 0;</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+				 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+			mdelay(10);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+			mdelay(10);</div><div class='add'>+			r = -1;</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (r) {</div><div class='del'>-			dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='del'>-			return r;</div><div class='del'>-		}</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* enable master interrupt */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),</div><div class='del'>-				UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='del'>-				~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='ctx'> </div><div class='del'>-		/* clear the busy bit of VCN_STATUS */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,</div><div class='del'>-			~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='ctx'> </div><div class='del'>-		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,</div><div class='del'>-			ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='del'>-			VCN_RB1_DB_CTRL__EN_MASK);</div><div class='del'>-</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='del'>-		tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);</div><div class='del'>-		ring-&gt;wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);</div><div class='del'>-</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='del'>-		tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='del'>-		fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='del'>-	}</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,</div><div class='add'>+		     ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		     VCN_RB1_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='add'>+	tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);</div><div class='add'>+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -857,17 +951,18 @@ static int vcn_v5_0_0_start(struct amdgpu_device *adev)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block with dpg mode</div><div class='ctx'>  */</div><div class='del'>-static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};</div><div class='ctx'> 	uint32_t tmp;</div><div class='ctx'> </div><div class='del'>-	vcn_v5_0_0_pause_dpg_mode(adev, inst_idx, &amp;state);</div><div class='add'>+	vcn_v5_0_0_pause_dpg_mode(vinst, &amp;state);</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for power status to be 1 */</div><div class='ctx'> 	SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,</div><div class='hunk'>@@ -881,101 +976,117 @@ static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)</div><div class='ctx'> 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,</div><div class='ctx'> 		~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);</div><div class='add'>+</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_stop - VCN stop</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  *</div><div class='ctx'>  * Stop VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_stop(struct amdgpu_device *adev)</div><div class='add'>+static int vcn_v5_0_0_stop(struct amdgpu_vcn_inst *vinst)</div><div class='ctx'> {</div><div class='del'>-	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='ctx'> 	uint32_t tmp;</div><div class='del'>-	int i, r = 0;</div><div class='add'>+	int r = 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='add'>+	if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='del'>-			vcn_v5_0_0_stop_dpg_mode(adev, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='ctx'> </div><div class='del'>-		/* wait for vcn idle */</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		vcn_v5_0_0_stop_dpg_mode(vinst);</div><div class='add'>+		r = 0;</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='del'>-		      UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='del'>-		      UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='del'>-		      UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* disable LMI UMC channel */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);</div><div class='del'>-		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);</div><div class='del'>-		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='del'>-		      UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='del'>-		r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='add'>+</div><div class='add'>+	/* disable LMI UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		goto done;</div><div class='ctx'> </div><div class='del'>-		/* block VCPU register access */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),</div><div class='del'>-			UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='del'>-			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='del'>-</div><div class='del'>-		/* reset VCPU */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='del'>-			UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='del'>-			~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='del'>-</div><div class='del'>-		/* disable VCPU clock */</div><div class='del'>-		WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='del'>-			~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='del'>-</div><div class='del'>-		/* apply soft reset */</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-		tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='del'>-		tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='del'>-</div><div class='del'>-		/* clear status */</div><div class='del'>-		WREG32_SOC15(VCN, i, regUVD_STATUS, 0);</div><div class='del'>-</div><div class='del'>-		/* enable VCN power gating */</div><div class='del'>-		vcn_v5_0_0_enable_static_power_gating(adev, i);</div><div class='del'>-	}</div><div class='add'>+	/* block VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* reset VCPU */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+</div><div class='add'>+	/* apply soft reset */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* clear status */</div><div class='add'>+	WREG32_SOC15(VCN, i, regUVD_STATUS, 0);</div><div class='add'>+</div><div class='add'>+	/* enable VCN power gating */</div><div class='add'>+	vcn_v5_0_0_enable_static_power_gating(vinst);</div><div class='ctx'> </div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, i, regUVD_STATUS);</div><div class='add'>+</div><div class='add'>+done:</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='del'>-		amdgpu_dpm_enable_uvd(adev, false);</div><div class='add'>+		amdgpu_dpm_enable_vcn(adev, false, i);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode</div><div class='ctx'>  *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @inst_idx: instance number index</div><div class='add'>+ * @vinst: VCN instance</div><div class='ctx'>  * @new_state: pause state</div><div class='ctx'>  *</div><div class='ctx'>  * Pause dpg mode for VCN block</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,</div><div class='del'>-	struct dpg_pause_state *new_state)</div><div class='add'>+static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> 	int ret_code;</div><div class='ctx'> </div><div class='hunk'>@@ -1070,6 +1181,24 @@ static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+	r = vcn_v5_0_0_stop(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	r = vcn_v5_0_0_start(vinst);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = {</div><div class='ctx'> 	.type = AMDGPU_RING_TYPE_VCN_ENC,</div><div class='ctx'> 	.align_mask = 0x3f,</div><div class='hunk'>@@ -1097,6 +1226,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = {</div><div class='ctx'> 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = vcn_v5_0_0_ring_reset,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1116,21 +1246,19 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_enc[0].funcs = &amp;vcn_v5_0_0_unified_ring_vm_funcs;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].ring_enc[0].me = i;</div><div class='del'>-</div><div class='del'>-		DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_is_idle - check VCN block is idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block structure</div><div class='ctx'>  *</div><div class='ctx'>  * Check whether VCN block is idle</div><div class='ctx'>  */</div><div class='del'>-static bool vcn_v5_0_0_is_idle(void *handle)</div><div class='add'>+static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1146,13 +1274,13 @@ static bool vcn_v5_0_0_is_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_wait_for_idle - wait for VCN block idle</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Wait for VCN block idle</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_wait_for_idle(void *handle)</div><div class='add'>+static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='hunk'>@@ -1171,77 +1299,56 @@ static int vcn_v5_0_0_wait_for_idle(void *handle)</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v5_0_0_set_clockgating_state - set VCN block clockgating state</div><div class='ctx'>  *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='add'>+ * @ip_block: amdgpu_ip_block pointer</div><div class='ctx'>  * @state: clock gating state</div><div class='ctx'>  *</div><div class='ctx'>  * Set VCN block clockgating state</div><div class='ctx'>  */</div><div class='del'>-static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)</div><div class='add'>+static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = state == AMD_CG_STATE_GATE;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (enable) {</div><div class='ctx'> 			if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)</div><div class='ctx'> 				return -EBUSY;</div><div class='del'>-			vcn_v5_0_0_enable_clock_gating(adev, i);</div><div class='add'>+			vcn_v5_0_0_enable_clock_gating(vinst);</div><div class='ctx'> 		} else {</div><div class='del'>-			vcn_v5_0_0_disable_clock_gating(adev, i);</div><div class='add'>+			vcn_v5_0_0_disable_clock_gating(vinst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * vcn_v5_0_0_set_powergating_state - set VCN block powergating state</div><div class='del'>- *</div><div class='del'>- * @handle: amdgpu_device pointer</div><div class='del'>- * @state: power gating state</div><div class='del'>- *</div><div class='del'>- * Set VCN block powergating state</div><div class='del'>- */</div><div class='del'>-static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state)</div><div class='add'>+static int vcn_v5_0_0_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (state == adev-&gt;vcn.cur_state)</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (state == AMD_PG_STATE_GATE)</div><div class='del'>-		ret = vcn_v5_0_0_stop(adev);</div><div class='add'>+		ret = vcn_v5_0_0_stop(vinst);</div><div class='ctx'> 	else</div><div class='del'>-		ret = vcn_v5_0_0_start(adev);</div><div class='add'>+		ret = vcn_v5_0_0_start(vinst);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		adev-&gt;vcn.cur_state = state;</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * vcn_v5_0_0_set_interrupt_state - set VCN block interrupt state</div><div class='del'>- *</div><div class='del'>- * @adev: amdgpu_device pointer</div><div class='del'>- * @source: interrupt sources</div><div class='del'>- * @type: interrupt types</div><div class='del'>- * @state: interrupt states</div><div class='del'>- *</div><div class='del'>- * Set VCN block interrupt state</div><div class='del'>- */</div><div class='del'>-static int vcn_v5_0_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source,</div><div class='del'>-	unsigned type, enum amdgpu_interrupt_state state)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * vcn_v5_0_0_process_interrupt - process VCN block interrupt</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='hunk'>@@ -1270,10 +1377,10 @@ static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgp</div><div class='ctx'> 	DRM_DEBUG("IH: VCN TRAP\n");</div><div class='ctx'> </div><div class='ctx'> 	switch (entry-&gt;src_id) {</div><div class='del'>-	case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:</div><div class='add'>+	case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE:</div><div class='ctx'> 		amdgpu_fence_process(&amp;adev-&gt;vcn.inst[ip_instance].ring_enc[0]);</div><div class='ctx'> 		break;</div><div class='del'>-	case VCN_4_0__SRCID_UVD_POISON:</div><div class='add'>+	case VCN_5_0__SRCID_UVD_POISON:</div><div class='ctx'> 		amdgpu_vcn_process_poison_irq(adev, source, entry);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1286,7 +1393,6 @@ static int vcn_v5_0_0_process_interrupt(struct amdgpu_device *adev, struct amdgp</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = {</div><div class='del'>-	.set = vcn_v5_0_0_set_interrupt_state,</div><div class='ctx'> 	.process = vcn_v5_0_0_process_interrupt,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1305,7 +1411,7 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.num_enc_rings + 1;</div><div class='add'>+		adev-&gt;vcn.inst[i].irq.num_types = adev-&gt;vcn.inst[i].num_enc_rings + 1;</div><div class='ctx'> 		adev-&gt;vcn.inst[i].irq.funcs = &amp;vcn_v5_0_0_irq_funcs;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1313,7 +1419,6 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {</div><div class='ctx'> 	.name = "vcn_v5_0_0",</div><div class='ctx'> 	.early_init = vcn_v5_0_0_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vcn_v5_0_0_sw_init,</div><div class='ctx'> 	.sw_fini = vcn_v5_0_0_sw_fini,</div><div class='ctx'> 	.hw_init = vcn_v5_0_0_hw_init,</div><div class='hunk'>@@ -1322,12 +1427,10 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {</div><div class='ctx'> 	.resume = vcn_v5_0_0_resume,</div><div class='ctx'> 	.is_idle = vcn_v5_0_0_is_idle,</div><div class='ctx'> 	.wait_for_idle = vcn_v5_0_0_wait_for_idle,</div><div class='del'>-	.check_soft_reset = NULL,</div><div class='del'>-	.pre_soft_reset = NULL,</div><div class='del'>-	.soft_reset = NULL,</div><div class='del'>-	.post_soft_reset = NULL,</div><div class='ctx'> 	.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,</div><div class='del'>-	.set_powergating_state = vcn_v5_0_0_set_powergating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c<br/>new file mode 100644<br/>index 000000000000..8bd457dea4cf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c</a></div><div class='hunk'>@@ -0,0 +1,1729 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_vcn.h"</div><div class='add'>+#include "amdgpu_pm.h"</div><div class='add'>+#include "soc15.h"</div><div class='add'>+#include "soc15d.h"</div><div class='add'>+#include "soc15_hw_ip.h"</div><div class='add'>+#include "vcn_v2_0.h"</div><div class='add'>+#include "vcn_v4_0_3.h"</div><div class='add'>+#include "mmsch_v5_0.h"</div><div class='add'>+</div><div class='add'>+#include "vcn/vcn_5_0_0_offset.h"</div><div class='add'>+#include "vcn/vcn_5_0_0_sh_mask.h"</div><div class='add'>+#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"</div><div class='add'>+#include "vcn_v5_0_0.h"</div><div class='add'>+#include "vcn_v5_0_1.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0_1[] = {</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),</div><div class='add'>+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev);</div><div class='add'>+static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev);</div><div class='add'>+static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);</div><div class='add'>+static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state);</div><div class='add'>+static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring);</div><div class='add'>+static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev);</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_early_init - set function pointers and load microcode</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Set ring and irq function pointers</div><div class='add'>+ * Load microcode from filesystem</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		/* re-use enc ring as unified ring */</div><div class='add'>+		adev-&gt;vcn.inst[i].num_enc_rings = 1;</div><div class='add'>+</div><div class='add'>+	vcn_v5_0_1_set_unified_ring_funcs(adev);</div><div class='add'>+	vcn_v5_0_1_set_irq_funcs(adev);</div><div class='add'>+	vcn_v5_0_1_set_ras_funcs(adev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		adev-&gt;vcn.inst[i].set_pg_state = vcn_v5_0_1_set_pg_state;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_early_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_late_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.supported_reset =</div><div class='add'>+		amdgpu_get_soft_full_reset_mask(&amp;adev-&gt;vcn.inst[0].ring_enc[0]);</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(13, 0, 12):</div><div class='add'>+		if ((adev-&gt;psp.sos.fw_version &gt;= 0x00450025) &amp;&amp;</div><div class='add'>+			amdgpu_dpm_reset_vcn_is_supported(adev) &amp;&amp;</div><div class='add'>+			!amdgpu_sriov_vf(adev))</div><div class='add'>+			adev-&gt;vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='add'>+</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+</div><div class='add'>+	if (fw_shared-&gt;sq.is_enabled)</div><div class='add'>+		return;</div><div class='add'>+	fw_shared-&gt;present_flag_0 =</div><div class='add'>+		cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);</div><div class='add'>+	fw_shared-&gt;sq.is_enabled = 1;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_vcnfw_log)</div><div class='add'>+		amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[inst_idx]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_sw_init - sw init for VCN block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Load firmware and sw initialization</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i, r, vcn_inst;</div><div class='add'>+</div><div class='add'>+	/* VCN UNIFIED TRAP */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+		VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &amp;adev-&gt;vcn.inst-&gt;irq);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* VCN POISON TRAP */</div><div class='add'>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,</div><div class='add'>+		VCN_5_0__SRCID_UVD_POISON, &amp;adev-&gt;vcn.inst-&gt;ras_poison_irq);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		vcn_inst = GET_INST(VCN, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_sw_init(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		amdgpu_vcn_setup_ucode(adev, i);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+		ring-&gt;use_doorbell = true;</div><div class='add'>+		if (!amdgpu_sriov_vf(adev))</div><div class='add'>+			ring-&gt;doorbell_index =</div><div class='add'>+				(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='add'>+				11 * vcn_inst;</div><div class='add'>+		else</div><div class='add'>+			ring-&gt;doorbell_index =</div><div class='add'>+				(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='add'>+				32 * vcn_inst;</div><div class='add'>+</div><div class='add'>+		ring-&gt;vm_hub = AMDGPU_MMHUB0(adev-&gt;vcn.inst[i].aid_id);</div><div class='add'>+		sprintf(ring-&gt;name, "vcn_unified_%d", adev-&gt;vcn.inst[i].aid_id);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_ring_init(adev, ring, 512, &amp;adev-&gt;vcn.inst[i].irq, 0,</div><div class='add'>+					AMDGPU_RING_PRIO_DEFAULT, &amp;adev-&gt;vcn.inst[i].sched_score);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		vcn_v5_0_1_fw_shared_init(adev, i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		r = amdgpu_virt_alloc_mm_table(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {</div><div class='add'>+		r = amdgpu_vcn_ras_sw_init(adev);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to initialize vcn ras block!\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1));</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	return amdgpu_vcn_sysfs_reset_mask_init(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_sw_fini - sw fini for VCN block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * VCN suspend and free up sw allocation</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, r, idx;</div><div class='add'>+</div><div class='add'>+	if (drm_dev_enter(adev_to_drm(adev), &amp;idx)) {</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+			struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='add'>+</div><div class='add'>+			fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+			fw_shared-&gt;present_flag_0 = 0;</div><div class='add'>+			fw_shared-&gt;sq.is_enabled = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_dev_exit(idx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_virt_free_mm_table(adev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_vcn_sysfs_reset_mask_fini(adev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++)</div><div class='add'>+		amdgpu_vcn_sw_fini(adev, i);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_hw_init_inst(struct amdgpu_device *adev, int i)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int vcn_inst;</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, i);</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell)</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='add'>+			((adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1) +</div><div class='add'>+			11 * vcn_inst),</div><div class='add'>+			adev-&gt;vcn.inst[i].aid_id);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_hw_init - start and test VCN block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Initialize the hardware, boot up the VCPU and do some testing</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		r = vcn_v5_0_1_start_sriov(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+			ring-&gt;wptr = 0;</div><div class='add'>+			ring-&gt;wptr_old = 0;</div><div class='add'>+			vcn_v5_0_1_unified_ring_set_wptr(ring);</div><div class='add'>+			ring-&gt;sched.ready = true;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &amp; 0x100)</div><div class='add'>+			adev-&gt;vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);</div><div class='add'>+		for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+			ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+			vcn_v5_0_1_hw_init_inst(adev, i);</div><div class='add'>+</div><div class='add'>+			/* Re-init fw_shared, if required */</div><div class='add'>+			vcn_v5_0_1_fw_shared_init(adev, i);</div><div class='add'>+</div><div class='add'>+			r = amdgpu_ring_test_helper(ring);</div><div class='add'>+			if (r)</div><div class='add'>+				return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_hw_fini - stop the hardware block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Stop the VCN block, mark ring as not ready any more</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='add'>+		cancel_delayed_work_sync(&amp;adev-&gt;vcn.inst[i].idle_work);</div><div class='add'>+		if (vinst-&gt;cur_state != AMD_PG_STATE_GATE)</div><div class='add'>+			vinst-&gt;set_pg_state(vinst, AMD_PG_STATE_GATE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) &amp;&amp; !amdgpu_sriov_vf(adev))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;vcn.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_suspend - suspend VCN block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * HW fini and suspend VCN block</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='add'>+</div><div class='add'>+	r = vcn_v5_0_1_hw_fini(ip_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		r = amdgpu_vcn_suspend(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_resume - resume VCN block</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Resume firmware and hw init VCN block</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_resume(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r, i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='add'>+		if (amdgpu_in_reset(adev))</div><div class='add'>+			vinst-&gt;cur_state = AMD_PG_STATE_GATE;</div><div class='add'>+</div><div class='add'>+		r = amdgpu_vcn_resume(ip_block-&gt;adev, i);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = vcn_v5_0_1_hw_init(ip_block);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_mc_resume - memory controller programming</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ *</div><div class='add'>+ * Let the VCN memory controller know it's offsets</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_mc_resume(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst = vinst-&gt;inst;</div><div class='add'>+	uint32_t offset, size, vcn_inst;</div><div class='add'>+	const struct common_firmware_header *hdr;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst].fw-&gt;data;</div><div class='add'>+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, inst);</div><div class='add'>+	/* cache window 0: fw */</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,</div><div class='add'>+			(adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,</div><div class='add'>+			(adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0);</div><div class='add'>+		offset = 0;</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,</div><div class='add'>+			lower_32_bits(adev-&gt;vcn.inst[inst].gpu_addr));</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,</div><div class='add'>+			upper_32_bits(adev-&gt;vcn.inst[inst].gpu_addr));</div><div class='add'>+		offset = size;</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0,</div><div class='add'>+				AMDGPU_UVD_FIRMWARE_OFFSET &gt;&gt; 3);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size);</div><div class='add'>+</div><div class='add'>+	/* cache window 1: stack */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,</div><div class='add'>+		lower_32_bits(adev-&gt;vcn.inst[inst].gpu_addr + offset));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,</div><div class='add'>+		upper_32_bits(adev-&gt;vcn.inst[inst].gpu_addr + offset));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);</div><div class='add'>+</div><div class='add'>+	/* cache window 2: context */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,</div><div class='add'>+		lower_32_bits(adev-&gt;vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,</div><div class='add'>+		upper_32_bits(adev-&gt;vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);</div><div class='add'>+</div><div class='add'>+	/* non-cache window */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,</div><div class='add'>+		lower_32_bits(adev-&gt;vcn.inst[inst].fw_shared.gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,</div><div class='add'>+		upper_32_bits(adev-&gt;vcn.inst[inst].fw_shared.gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0,</div><div class='add'>+		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_mc_resume_dpg_mode - memory controller programming for dpg mode</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ * @indirect: indirectly write sram</div><div class='add'>+ *</div><div class='add'>+ * Let the VCN memory controller know it's offsets with dpg mode</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+					  bool indirect)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	uint32_t offset, size;</div><div class='add'>+	const struct common_firmware_header *hdr;</div><div class='add'>+</div><div class='add'>+	hdr = (const struct common_firmware_header *)adev-&gt;vcn.inst[inst_idx].fw-&gt;data;</div><div class='add'>+	size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr-&gt;ucode_size_bytes) + 8);</div><div class='add'>+</div><div class='add'>+	/* cache window 0: fw */</div><div class='add'>+	if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+		if (!indirect) {</div><div class='add'>+			WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),</div><div class='add'>+				(adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN +</div><div class='add'>+				 inst_idx].tmr_mc_addr_lo), 0, indirect);</div><div class='add'>+			WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),</div><div class='add'>+				(adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN +</div><div class='add'>+				 inst_idx].tmr_mc_addr_hi), 0, indirect);</div><div class='add'>+			WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+				VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);</div><div class='add'>+		} else {</div><div class='add'>+			WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);</div><div class='add'>+			WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);</div><div class='add'>+			WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+				VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);</div><div class='add'>+		}</div><div class='add'>+		offset = 0;</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),</div><div class='add'>+			lower_32_bits(adev-&gt;vcn.inst[inst_idx].gpu_addr), 0, indirect);</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),</div><div class='add'>+			upper_32_bits(adev-&gt;vcn.inst[inst_idx].gpu_addr), 0, indirect);</div><div class='add'>+		offset = size;</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_VCPU_CACHE_OFFSET0),</div><div class='add'>+			AMDGPU_UVD_FIRMWARE_OFFSET &gt;&gt; 3, 0, indirect);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!indirect)</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);</div><div class='add'>+	else</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* cache window 1: stack */</div><div class='add'>+	if (!indirect) {</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),</div><div class='add'>+			lower_32_bits(adev-&gt;vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),</div><div class='add'>+			upper_32_bits(adev-&gt;vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);</div><div class='add'>+	}</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+			VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* cache window 2: context */</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),</div><div class='add'>+		lower_32_bits(adev-&gt;vcn.inst[inst_idx].gpu_addr + offset +</div><div class='add'>+			AMDGPU_VCN_STACK_SIZE), 0, indirect);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),</div><div class='add'>+		upper_32_bits(adev-&gt;vcn.inst[inst_idx].gpu_addr + offset +</div><div class='add'>+			AMDGPU_VCN_STACK_SIZE), 0, indirect);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* non-cache window */</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),</div><div class='add'>+		lower_32_bits(adev-&gt;vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),</div><div class='add'>+		upper_32_bits(adev-&gt;vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_VCPU_NONCACHE_SIZE0),</div><div class='add'>+		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev-&gt;gfx.config.gb_addr_config, 0, indirect);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_disable_clock_gating - disable VCN clock gating</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ *</div><div class='add'>+ * Disable clock gating for VCN block</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_disable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_enable_clock_gating - enable VCN clock gating</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ *</div><div class='add'>+ * Enable clock gating for VCN block</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_enable_clock_gating(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_pause_dpg_mode - VCN pause with dpg mode</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ * @new_state: pause state</div><div class='add'>+ *</div><div class='add'>+ * Pause dpg mode for VCN block</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     struct dpg_pause_state *new_state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	uint32_t reg_data = 0;</div><div class='add'>+	int vcn_inst;</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, vinst-&gt;inst);</div><div class='add'>+</div><div class='add'>+	/* pause/unpause if state is changed */</div><div class='add'>+	if (vinst-&gt;pause_state.fw_based != new_state-&gt;fw_based) {</div><div class='add'>+		DRM_DEV_DEBUG(adev-&gt;dev, "dpg pause state changed %d -&gt; %d %s\n",</div><div class='add'>+			vinst-&gt;pause_state.fw_based, new_state-&gt;fw_based,</div><div class='add'>+			new_state-&gt;fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE");</div><div class='add'>+		reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) &amp;</div><div class='add'>+			(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);</div><div class='add'>+</div><div class='add'>+		if (new_state-&gt;fw_based == VCN_DPG_STATE__PAUSE) {</div><div class='add'>+			/* pause DPG */</div><div class='add'>+			reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;</div><div class='add'>+			WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data);</div><div class='add'>+</div><div class='add'>+			/* wait for ACK */</div><div class='add'>+			SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE,</div><div class='add'>+					UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,</div><div class='add'>+					UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);</div><div class='add'>+		} else {</div><div class='add'>+			/* unpause DPG, no need to wait */</div><div class='add'>+			reg_data &amp;= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;</div><div class='add'>+			WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data);</div><div class='add'>+		}</div><div class='add'>+		vinst-&gt;pause_state.fw_based = new_state-&gt;fw_based;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_start_dpg_mode - VCN start with dpg mode</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ * @indirect: indirectly write sram</div><div class='add'>+ *</div><div class='add'>+ * Start VCN block with dpg mode</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				     bool indirect)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared =</div><div class='add'>+		adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE};</div><div class='add'>+	int vcn_inst, ret;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, inst_idx);</div><div class='add'>+</div><div class='add'>+	/* disable register anti-hang mechanism */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,</div><div class='add'>+		~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+	/* enable dynamic power gating mode */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);</div><div class='add'>+	tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);</div><div class='add'>+</div><div class='add'>+	if (indirect) {</div><div class='add'>+		adev-&gt;vcn.inst[inst_idx].dpg_sram_curr_addr =</div><div class='add'>+			(uint32_t *)adev-&gt;vcn.inst[inst_idx].dpg_sram_cpu_addr;</div><div class='add'>+		/* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */</div><div class='add'>+		WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF,</div><div class='add'>+				adev-&gt;vcn.inst[inst_idx].aid_id, 0, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='add'>+	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_LMI_CTRL */</div><div class='add'>+	tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='add'>+		UVD_LMI_CTRL__REQ_MODE_MASK |</div><div class='add'>+		UVD_LMI_CTRL__CRC_RESET_MASK |</div><div class='add'>+		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |</div><div class='add'>+		(8 &lt;&lt; UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |</div><div class='add'>+		0x00100000L);</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);</div><div class='add'>+</div><div class='add'>+	vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect);</div><div class='add'>+</div><div class='add'>+	tmp = (0xFF &lt;&lt; UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);</div><div class='add'>+	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	tmp = 0x1f &lt;&lt; UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);</div><div class='add'>+</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(</div><div class='add'>+		VCN, 0, regUVD_MASTINT_EN),</div><div class='add'>+		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);</div><div class='add'>+</div><div class='add'>+	if (indirect) {</div><div class='add'>+		ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "vcn sram load failed %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* resetting ring, fw should not check RB ring */</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+</div><div class='add'>+	/* Pause dpg */</div><div class='add'>+	vcn_v5_0_1_pause_dpg_mode(vinst, &amp;state);</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[inst_idx].ring_enc[0];</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring-&gt;ring_size / sizeof(uint32_t));</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='add'>+	tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='add'>+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	/* resetting done, fw can check RB ring */</div><div class='add'>+	fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,</div><div class='add'>+		ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		VCN_RB1_DB_CTRL__EN_MASK);</div><div class='add'>+	/* Read DB_CTRL to flush the write DB_CTRL command. */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, vcn_inst;</div><div class='add'>+	struct amdgpu_ring *ring_enc;</div><div class='add'>+	uint64_t cache_addr;</div><div class='add'>+	uint64_t rb_enc_addr;</div><div class='add'>+	uint64_t ctx_addr;</div><div class='add'>+	uint32_t param, resp, expected;</div><div class='add'>+	uint32_t offset, cache_size;</div><div class='add'>+	uint32_t tmp, timeout;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_mm_table *table = &amp;adev-&gt;virt.mm_table;</div><div class='add'>+	uint32_t *table_loc;</div><div class='add'>+	uint32_t table_size;</div><div class='add'>+	uint32_t size, size_dw;</div><div class='add'>+	uint32_t init_status;</div><div class='add'>+	uint32_t enabled_vcn;</div><div class='add'>+</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_write</div><div class='add'>+		direct_wt = { {0} };</div><div class='add'>+	struct mmsch_v5_0_cmd_direct_read_modify_write</div><div class='add'>+		direct_rd_mod_wt = { {0} };</div><div class='add'>+	struct mmsch_v5_0_cmd_end end = { {0} };</div><div class='add'>+	struct mmsch_v5_0_init_header header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_fw_shared_rb_setup *rb_setup;</div><div class='add'>+</div><div class='add'>+	direct_wt.cmd_header.command_type =</div><div class='add'>+		MMSCH_COMMAND__DIRECT_REG_WRITE;</div><div class='add'>+	direct_rd_mod_wt.cmd_header.command_type =</div><div class='add'>+		MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;</div><div class='add'>+	end.cmd_header.command_type = MMSCH_COMMAND__END;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='add'>+		vcn_inst = GET_INST(VCN, i);</div><div class='add'>+</div><div class='add'>+		vcn_v5_0_1_fw_shared_init(adev, vcn_inst);</div><div class='add'>+</div><div class='add'>+		memset(&amp;header, 0, sizeof(struct mmsch_v5_0_init_header));</div><div class='add'>+		header.version = MMSCH_VERSION;</div><div class='add'>+		header.total_size = sizeof(struct mmsch_v5_0_init_header) &gt;&gt; 2;</div><div class='add'>+</div><div class='add'>+		table_loc = (uint32_t *)table-&gt;cpu_addr;</div><div class='add'>+		table_loc += header.total_size;</div><div class='add'>+</div><div class='add'>+		table_size = 0;</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),</div><div class='add'>+			~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);</div><div class='add'>+</div><div class='add'>+		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev-&gt;vcn.inst[i].fw-&gt;size + 4);</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;firmware.load_type == AMDGPU_FW_LOAD_PSP) {</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+				regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),</div><div class='add'>+				adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);</div><div class='add'>+</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+				regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),</div><div class='add'>+				adev-&gt;firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);</div><div class='add'>+</div><div class='add'>+			offset = 0;</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+				regUVD_VCPU_CACHE_OFFSET0), 0);</div><div class='add'>+		} else {</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+				regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),</div><div class='add'>+				lower_32_bits(adev-&gt;vcn.inst[i].gpu_addr));</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+				regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),</div><div class='add'>+				upper_32_bits(adev-&gt;vcn.inst[i].gpu_addr));</div><div class='add'>+			offset = cache_size;</div><div class='add'>+			MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+				regUVD_VCPU_CACHE_OFFSET0),</div><div class='add'>+				AMDGPU_UVD_FIRMWARE_OFFSET &gt;&gt; 3);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_VCPU_CACHE_SIZE0),</div><div class='add'>+			cache_size);</div><div class='add'>+</div><div class='add'>+		cache_addr = adev-&gt;vcn.inst[vcn_inst].gpu_addr + offset;</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_VCPU_CACHE_OFFSET1), 0);</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);</div><div class='add'>+</div><div class='add'>+		cache_addr = adev-&gt;vcn.inst[vcn_inst].gpu_addr + offset +</div><div class='add'>+			AMDGPU_VCN_STACK_SIZE;</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_VCPU_CACHE_OFFSET2), 0);</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE);</div><div class='add'>+</div><div class='add'>+		fw_shared = adev-&gt;vcn.inst[vcn_inst].fw_shared.cpu_addr;</div><div class='add'>+		rb_setup = &amp;fw_shared-&gt;rb_setup;</div><div class='add'>+</div><div class='add'>+		ring_enc = &amp;adev-&gt;vcn.inst[vcn_inst].ring_enc[0];</div><div class='add'>+		ring_enc-&gt;wptr = 0;</div><div class='add'>+		rb_enc_addr = ring_enc-&gt;gpu_addr;</div><div class='add'>+</div><div class='add'>+		rb_setup-&gt;is_rb_enabled_flags |= RB_ENABLED;</div><div class='add'>+		rb_setup-&gt;rb_addr_lo = lower_32_bits(rb_enc_addr);</div><div class='add'>+		rb_setup-&gt;rb_addr_hi = upper_32_bits(rb_enc_addr);</div><div class='add'>+		rb_setup-&gt;rb_size = ring_enc-&gt;ring_size / 4;</div><div class='add'>+		fw_shared-&gt;present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);</div><div class='add'>+</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),</div><div class='add'>+			lower_32_bits(adev-&gt;vcn.inst[vcn_inst].fw_shared.gpu_addr));</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),</div><div class='add'>+			upper_32_bits(adev-&gt;vcn.inst[vcn_inst].fw_shared.gpu_addr));</div><div class='add'>+		MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,</div><div class='add'>+			regUVD_VCPU_NONCACHE_SIZE0),</div><div class='add'>+			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));</div><div class='add'>+		MMSCH_V5_0_INSERT_END();</div><div class='add'>+</div><div class='add'>+		header.vcn0.init_status = 0;</div><div class='add'>+		header.vcn0.table_offset = header.total_size;</div><div class='add'>+		header.vcn0.table_size = table_size;</div><div class='add'>+		header.total_size += table_size;</div><div class='add'>+</div><div class='add'>+		/* Send init table to mmsch */</div><div class='add'>+		size = sizeof(struct mmsch_v5_0_init_header);</div><div class='add'>+		table_loc = (uint32_t *)table-&gt;cpu_addr;</div><div class='add'>+		memcpy((void *)table_loc, &amp;header, size);</div><div class='add'>+</div><div class='add'>+		ctx_addr = table-&gt;gpu_addr;</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));</div><div class='add'>+</div><div class='add'>+		tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);</div><div class='add'>+		tmp &amp;= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;</div><div class='add'>+		tmp |= (0 &lt;&lt; MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);</div><div class='add'>+</div><div class='add'>+		size = header.total_size;</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size);</div><div class='add'>+</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0);</div><div class='add'>+</div><div class='add'>+		param = 0x00000001;</div><div class='add'>+		WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param);</div><div class='add'>+		tmp = 0;</div><div class='add'>+		timeout = 1000;</div><div class='add'>+		resp = 0;</div><div class='add'>+		expected = MMSCH_VF_MAILBOX_RESP__OK;</div><div class='add'>+		while (resp != expected) {</div><div class='add'>+			resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);</div><div class='add'>+			if (resp != 0)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			udelay(10);</div><div class='add'>+			tmp = tmp + 10;</div><div class='add'>+			if (tmp &gt;= timeout) {</div><div class='add'>+				DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\</div><div class='add'>+					" waiting for regMMSCH_VF_MAILBOX_RESP "\</div><div class='add'>+					"(expected=0x%08x, readback=0x%08x)\n",</div><div class='add'>+					tmp, expected, resp);</div><div class='add'>+				return -EBUSY;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;</div><div class='add'>+		init_status = ((struct mmsch_v5_0_init_header *)(table_loc))-&gt;vcn0.init_status;</div><div class='add'>+		if (resp != expected &amp;&amp; resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE</div><div class='add'>+					&amp;&amp; init_status != MMSCH_VF_ENGINE_STATUS__PASS) {</div><div class='add'>+			DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\</div><div class='add'>+				"status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_start - VCN start</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ *</div><div class='add'>+ * Start VCN block</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='add'>+	struct amdgpu_ring *ring;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	int j, k, r, vcn_inst;</div><div class='add'>+</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG)</div><div class='add'>+		return vcn_v5_0_1_start_dpg_mode(vinst, adev-&gt;vcn.inst[i].indirect_sram);</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, i);</div><div class='add'>+</div><div class='add'>+	/* set VCN status busy */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);</div><div class='add'>+</div><div class='add'>+	/* enable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* enable LMI MC and UMC channels */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,</div><div class='add'>+		 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	tmp &amp;= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* setup regUVD_LMI_CTRL */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp |</div><div class='add'>+		     UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__MASK_MC_URGENT_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |</div><div class='add'>+		     UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);</div><div class='add'>+</div><div class='add'>+	vcn_v5_0_1_mc_resume(vinst);</div><div class='add'>+</div><div class='add'>+	/* VCN global tiling registers */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,</div><div class='add'>+		     adev-&gt;gfx.config.gb_addr_config);</div><div class='add'>+</div><div class='add'>+	/* unblock VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* release VCPU reset to boot */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; 10; ++j) {</div><div class='add'>+		uint32_t status;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; 100; ++k) {</div><div class='add'>+			status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+			mdelay(100);</div><div class='add'>+			if (amdgpu_emu_mode == 1)</div><div class='add'>+				msleep(20);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode == 1) {</div><div class='add'>+			r = -1;</div><div class='add'>+			if (status &amp; 2) {</div><div class='add'>+				r = 0;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			r = 0;</div><div class='add'>+			if (status &amp; 2)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+				"VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='add'>+				 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+			mdelay(10);</div><div class='add'>+			WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='add'>+				 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+			mdelay(10);</div><div class='add'>+			r = -1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "VCN[%d] is not responding, giving up!!!\n", i);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* enable master interrupt */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),</div><div class='add'>+		 UVD_MASTINT_EN__VCPU_EN_MASK,</div><div class='add'>+		 ~UVD_MASTINT_EN__VCPU_EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* clear the busy bit of VCN_STATUS */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,</div><div class='add'>+		 ~(2 &lt;&lt; UVD_STATUS__VCPU_REPORT__SHIFT));</div><div class='add'>+</div><div class='add'>+	ring = &amp;adev-&gt;vcn.inst[i].ring_enc[0];</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,</div><div class='add'>+		     ring-&gt;doorbell_index &lt;&lt; VCN_RB1_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		     VCN_RB1_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='add'>+	/* Read DB_CTRL to flush the write DB_CTRL command. */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring-&gt;gpu_addr);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring-&gt;gpu_addr));</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring-&gt;ring_size / 4);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='add'>+	tmp &amp;= ~(VCN_RB_ENABLE__RB1_EN_MASK);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_RING_RESET;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp);</div><div class='add'>+	ring-&gt;wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);</div><div class='add'>+</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);</div><div class='add'>+	tmp |= VCN_RB_ENABLE__RB1_EN_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);</div><div class='add'>+	fw_shared-&gt;sq.queue_mode &amp;= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_stop_dpg_mode - VCN stop with dpg mode</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ *</div><div class='add'>+ * Stop VCN block with dpg mode</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int inst_idx = vinst-&gt;inst;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	int vcn_inst;</div><div class='add'>+	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, inst_idx);</div><div class='add'>+</div><div class='add'>+	/* Unpause dpg */</div><div class='add'>+	vcn_v5_0_1_pause_dpg_mode(vinst, &amp;state);</div><div class='add'>+</div><div class='add'>+	/* Wait for power status to be 1 */</div><div class='add'>+	SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,</div><div class='add'>+		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);</div><div class='add'>+</div><div class='add'>+	/* wait for read ptr to be equal to write ptr */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);</div><div class='add'>+	SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);</div><div class='add'>+</div><div class='add'>+	/* disable dynamic power gating mode */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,</div><div class='add'>+		~UVD_POWER_STATUS__UVD_PG_MODE_MASK);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_stop - VCN stop</div><div class='add'>+ *</div><div class='add'>+ * @vinst: VCN instance</div><div class='add'>+ *</div><div class='add'>+ * Stop VCN block</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int i = vinst-&gt;inst;</div><div class='add'>+	struct amdgpu_vcn5_fw_shared *fw_shared;</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+	int r = 0, vcn_inst;</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, i);</div><div class='add'>+</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;pg_flags &amp; AMD_PG_SUPPORT_VCN_DPG) {</div><div class='add'>+		vcn_v5_0_1_stop_dpg_mode(vinst);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* wait for vcn idle */</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__READ_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_MASK |</div><div class='add'>+		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* disable LMI UMC channel */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);</div><div class='add'>+	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);</div><div class='add'>+	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |</div><div class='add'>+		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;</div><div class='add'>+	r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	/* block VCPU register access */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),</div><div class='add'>+		 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,</div><div class='add'>+		 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);</div><div class='add'>+</div><div class='add'>+	/* reset VCPU */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),</div><div class='add'>+		 UVD_VCPU_CNTL__BLK_RST_MASK,</div><div class='add'>+		 ~UVD_VCPU_CNTL__BLK_RST_MASK);</div><div class='add'>+</div><div class='add'>+	/* disable VCPU clock */</div><div class='add'>+	WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,</div><div class='add'>+		 ~(UVD_VCPU_CNTL__CLK_EN_MASK));</div><div class='add'>+</div><div class='add'>+	/* apply soft reset */</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='add'>+	tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);</div><div class='add'>+	tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);</div><div class='add'>+</div><div class='add'>+	/* clear status */</div><div class='add'>+	WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);</div><div class='add'>+</div><div class='add'>+	/* Keeping one read-back to ensure all register writes are done,</div><div class='add'>+	 * otherwise it may introduce race conditions.</div><div class='add'>+	 */</div><div class='add'>+	RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_unified_ring_get_rptr - get unified read pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the current hardware unified read pointer</div><div class='add'>+ */</div><div class='add'>+static uint64_t vcn_v5_0_1_unified_ring_get_rptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring != &amp;adev-&gt;vcn.inst[ring-&gt;me].ring_enc[0])</div><div class='add'>+		DRM_ERROR("wrong ring id is identified in %s", __func__);</div><div class='add'>+</div><div class='add'>+	return RREG32_SOC15(VCN, GET_INST(VCN, ring-&gt;me), regUVD_RB_RPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_unified_ring_get_wptr - get unified write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the current hardware unified write pointer</div><div class='add'>+ */</div><div class='add'>+static uint64_t vcn_v5_0_1_unified_ring_get_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring != &amp;adev-&gt;vcn.inst[ring-&gt;me].ring_enc[0])</div><div class='add'>+		DRM_ERROR("wrong ring id is identified in %s", __func__);</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell)</div><div class='add'>+		return *ring-&gt;wptr_cpu_addr;</div><div class='add'>+	else</div><div class='add'>+		return RREG32_SOC15(VCN, GET_INST(VCN, ring-&gt;me), regUVD_RB_WPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_unified_ring_set_wptr - set enc write pointer</div><div class='add'>+ *</div><div class='add'>+ * @ring: amdgpu_ring pointer</div><div class='add'>+ *</div><div class='add'>+ * Commits the enc write pointer to the hardware</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	if (ring != &amp;adev-&gt;vcn.inst[ring-&gt;me].ring_enc[0])</div><div class='add'>+		DRM_ERROR("wrong ring id is identified in %s", __func__);</div><div class='add'>+</div><div class='add'>+	if (ring-&gt;use_doorbell) {</div><div class='add'>+		*ring-&gt;wptr_cpu_addr = lower_32_bits(ring-&gt;wptr);</div><div class='add'>+		WDOORBELL32(ring-&gt;doorbell_index, lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	} else {</div><div class='add'>+		WREG32_SOC15(VCN, GET_INST(VCN, ring-&gt;me), regUVD_RB_WPTR,</div><div class='add'>+				lower_32_bits(ring-&gt;wptr));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring,</div><div class='add'>+				 unsigned int vmid,</div><div class='add'>+				 struct amdgpu_fence *timedout_fence)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+	int vcn_inst;</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[ring-&gt;me];</div><div class='add'>+</div><div class='add'>+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);</div><div class='add'>+</div><div class='add'>+	vcn_inst = GET_INST(VCN, ring-&gt;me);</div><div class='add'>+	r = amdgpu_dpm_reset_vcn(adev, 1 &lt;&lt; vcn_inst);</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_DEV_ERROR(adev-&gt;dev, "VCN reset fail : %d\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vcn_v5_0_1_hw_init_inst(adev, ring-&gt;me);</div><div class='add'>+	vcn_v5_0_1_start_dpg_mode(vinst, vinst-&gt;indirect_sram);</div><div class='add'>+</div><div class='add'>+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = {</div><div class='add'>+	.type = AMDGPU_RING_TYPE_VCN_ENC,</div><div class='add'>+	.align_mask = 0x3f,</div><div class='add'>+	.nop = VCN_ENC_CMD_NO_OP,</div><div class='add'>+	.get_rptr = vcn_v5_0_1_unified_ring_get_rptr,</div><div class='add'>+	.get_wptr = vcn_v5_0_1_unified_ring_get_wptr,</div><div class='add'>+	.set_wptr = vcn_v5_0_1_unified_ring_set_wptr,</div><div class='add'>+	.emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +</div><div class='add'>+			   SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +</div><div class='add'>+			   4 + /* vcn_v2_0_enc_ring_emit_vm_flush */</div><div class='add'>+			   5 +</div><div class='add'>+			   5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */</div><div class='add'>+			   1, /* vcn_v2_0_enc_ring_insert_end */</div><div class='add'>+	.emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */</div><div class='add'>+	.emit_ib = vcn_v2_0_enc_ring_emit_ib,</div><div class='add'>+	.emit_fence = vcn_v2_0_enc_ring_emit_fence,</div><div class='add'>+	.emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush,</div><div class='add'>+	.emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush,</div><div class='add'>+	.test_ring = amdgpu_vcn_enc_ring_test_ring,</div><div class='add'>+	.test_ib = amdgpu_vcn_unified_ring_test_ib,</div><div class='add'>+	.insert_nop = amdgpu_ring_insert_nop,</div><div class='add'>+	.insert_end = vcn_v2_0_enc_ring_insert_end,</div><div class='add'>+	.pad_ib = amdgpu_ring_generic_pad_ib,</div><div class='add'>+	.begin_use = amdgpu_vcn_ring_begin_use,</div><div class='add'>+	.end_use = amdgpu_vcn_ring_end_use,</div><div class='add'>+	.emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg,</div><div class='add'>+	.emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait,</div><div class='add'>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,</div><div class='add'>+	.reset = vcn_v5_0_1_ring_reset,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_set_unified_ring_funcs - set unified ring functions</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set unified ring functions</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i, vcn_inst;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		adev-&gt;vcn.inst[i].ring_enc[0].funcs = &amp;vcn_v5_0_1_unified_ring_vm_funcs;</div><div class='add'>+		adev-&gt;vcn.inst[i].ring_enc[0].me = i;</div><div class='add'>+		vcn_inst = GET_INST(VCN, i);</div><div class='add'>+		adev-&gt;vcn.inst[i].aid_id = vcn_inst / adev-&gt;vcn.num_inst_per_aid;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_is_idle - check VCN block is idle</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block structure</div><div class='add'>+ *</div><div class='add'>+ * Check whether VCN block is idle</div><div class='add'>+ */</div><div class='add'>+static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, ret = 1;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		ret &amp;= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_wait_for_idle - wait for VCN block idle</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ *</div><div class='add'>+ * Wait for VCN block idle</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int i, ret = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE,</div><div class='add'>+			UVD_STATUS__IDLE);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_set_clockgating_state - set VCN block clockgating state</div><div class='add'>+ *</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='add'>+ * @state: clock gating state</div><div class='add'>+ *</div><div class='add'>+ * Set VCN block clockgating state</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='add'>+					    enum amd_clockgating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	bool enable = state == AMD_CG_STATE_GATE;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		struct amdgpu_vcn_inst *vinst = &amp;adev-&gt;vcn.inst[i];</div><div class='add'>+</div><div class='add'>+		if (enable) {</div><div class='add'>+			if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)</div><div class='add'>+				return -EBUSY;</div><div class='add'>+			vcn_v5_0_1_enable_clock_gating(vinst);</div><div class='add'>+		} else {</div><div class='add'>+			vcn_v5_0_1_disable_clock_gating(vinst);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_set_pg_state(struct amdgpu_vcn_inst *vinst,</div><div class='add'>+				   enum amd_powergating_state state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vinst-&gt;adev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* for SRIOV, guest should not control VCN Power-gating</div><div class='add'>+	 * MMSCH FW should control Power-gating and clock-gating</div><div class='add'>+	 * guest should avoid touching CGC and PG</div><div class='add'>+	 */</div><div class='add'>+	if (amdgpu_sriov_vf(adev)) {</div><div class='add'>+		vinst-&gt;cur_state = AMD_PG_STATE_UNGATE;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (state == vinst-&gt;cur_state)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (state == AMD_PG_STATE_GATE)</div><div class='add'>+		ret = vcn_v5_0_1_stop(vinst);</div><div class='add'>+	else</div><div class='add'>+		ret = vcn_v5_0_1_start(vinst);</div><div class='add'>+</div><div class='add'>+	if (!ret)</div><div class='add'>+		vinst-&gt;cur_state = state;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_process_interrupt - process VCN block interrupt</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @source: interrupt sources</div><div class='add'>+ * @entry: interrupt entry from clients and sources</div><div class='add'>+ *</div><div class='add'>+ * Process VCN block interrupt</div><div class='add'>+ */</div><div class='add'>+static int vcn_v5_0_1_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,</div><div class='add'>+	struct amdgpu_iv_entry *entry)</div><div class='add'>+{</div><div class='add'>+	uint32_t i, inst;</div><div class='add'>+</div><div class='add'>+	i = node_id_to_phys_map[entry-&gt;node_id];</div><div class='add'>+</div><div class='add'>+	DRM_DEV_DEBUG(adev-&gt;dev, "IH: VCN TRAP\n");</div><div class='add'>+</div><div class='add'>+	for (inst = 0; inst &lt; adev-&gt;vcn.num_vcn_inst; ++inst)</div><div class='add'>+		if (adev-&gt;vcn.inst[inst].aid_id == i)</div><div class='add'>+			break;</div><div class='add'>+	if (inst &gt;= adev-&gt;vcn.num_vcn_inst) {</div><div class='add'>+		dev_WARN_ONCE(adev-&gt;dev, 1,</div><div class='add'>+				"Interrupt received for unknown VCN instance %d",</div><div class='add'>+				entry-&gt;node_id);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (entry-&gt;src_id) {</div><div class='add'>+	case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE:</div><div class='add'>+		amdgpu_fence_process(&amp;adev-&gt;vcn.inst[inst].ring_enc[0]);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DRM_DEV_ERROR(adev-&gt;dev, "Unhandled interrupt: %d %d\n",</div><div class='add'>+			  entry-&gt;src_id, entry-&gt;src_data[0]);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_set_ras_interrupt_state(struct amdgpu_device *adev,</div><div class='add'>+					struct amdgpu_irq_src *source,</div><div class='add'>+					unsigned int type,</div><div class='add'>+					enum amdgpu_interrupt_state state)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs vcn_v5_0_1_irq_funcs = {</div><div class='add'>+	.process = vcn_v5_0_1_process_interrupt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_irq_src_funcs vcn_v5_0_1_ras_irq_funcs = {</div><div class='add'>+	.set = vcn_v5_0_1_set_ras_interrupt_state,</div><div class='add'>+	.process = amdgpu_vcn_process_poison_irq,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vcn_v5_0_1_set_irq_funcs - set VCN block interrupt irq functions</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Set VCN block interrupt irq functions</div><div class='add'>+ */</div><div class='add'>+static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i)</div><div class='add'>+		adev-&gt;vcn.inst-&gt;irq.num_types++;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.inst-&gt;irq.funcs = &amp;vcn_v5_0_1_irq_funcs;</div><div class='add'>+</div><div class='add'>+	adev-&gt;vcn.inst-&gt;ras_poison_irq.num_types = 1;</div><div class='add'>+	adev-&gt;vcn.inst-&gt;ras_poison_irq.funcs = &amp;vcn_v5_0_1_ras_irq_funcs;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = {</div><div class='add'>+	.name = "vcn_v5_0_1",</div><div class='add'>+	.early_init = vcn_v5_0_1_early_init,</div><div class='add'>+	.late_init = vcn_v5_0_1_late_init,</div><div class='add'>+	.sw_init = vcn_v5_0_1_sw_init,</div><div class='add'>+	.sw_fini = vcn_v5_0_1_sw_fini,</div><div class='add'>+	.hw_init = vcn_v5_0_1_hw_init,</div><div class='add'>+	.hw_fini = vcn_v5_0_1_hw_fini,</div><div class='add'>+	.suspend = vcn_v5_0_1_suspend,</div><div class='add'>+	.resume = vcn_v5_0_1_resume,</div><div class='add'>+	.is_idle = vcn_v5_0_1_is_idle,</div><div class='add'>+	.wait_for_idle = vcn_v5_0_1_wait_for_idle,</div><div class='add'>+	.check_soft_reset = NULL,</div><div class='add'>+	.pre_soft_reset = NULL,</div><div class='add'>+	.soft_reset = NULL,</div><div class='add'>+	.post_soft_reset = NULL,</div><div class='add'>+	.set_clockgating_state = vcn_v5_0_1_set_clockgating_state,</div><div class='add'>+	.set_powergating_state = vcn_set_powergating_state,</div><div class='add'>+	.dump_ip_state = amdgpu_vcn_dump_ip_state,</div><div class='add'>+	.print_ip_state = amdgpu_vcn_print_ip_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = {</div><div class='add'>+	.type = AMD_IP_BLOCK_TYPE_VCN,</div><div class='add'>+	.major = 5,</div><div class='add'>+	.minor = 0,</div><div class='add'>+	.rev = 1,</div><div class='add'>+	.funcs = &amp;vcn_v5_0_1_ip_funcs,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static uint32_t vcn_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev,</div><div class='add'>+			uint32_t instance, uint32_t sub_block)</div><div class='add'>+{</div><div class='add'>+	uint32_t poison_stat = 0, reg_value = 0;</div><div class='add'>+</div><div class='add'>+	switch (sub_block) {</div><div class='add'>+	case AMDGPU_VCN_V5_0_1_VCPU_VCODEC:</div><div class='add'>+		reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);</div><div class='add'>+		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (poison_stat)</div><div class='add'>+		dev_info(adev-&gt;dev, "Poison detected in VCN%d, sub_block%d\n",</div><div class='add'>+			instance, sub_block);</div><div class='add'>+</div><div class='add'>+	return poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vcn_v5_0_1_query_poison_status(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	uint32_t inst, sub;</div><div class='add'>+	uint32_t poison_stat = 0;</div><div class='add'>+</div><div class='add'>+	for (inst = 0; inst &lt; adev-&gt;vcn.num_vcn_inst; inst++)</div><div class='add'>+		for (sub = 0; sub &lt; AMDGPU_VCN_V5_0_1_MAX_SUB_BLOCK; sub++)</div><div class='add'>+			poison_stat +=</div><div class='add'>+			vcn_v5_0_1_query_poison_by_instance(adev, inst, sub);</div><div class='add'>+</div><div class='add'>+	return !!poison_stat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct amdgpu_ras_block_hw_ops vcn_v5_0_1_ras_hw_ops = {</div><div class='add'>+	.query_poison_status = vcn_v5_0_1_query_poison_status,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+				      enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	struct aca_bank_info info;</div><div class='add'>+	u64 misc0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = aca_bank_info_decode(bank, &amp;info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	misc0 = bank-&gt;regs[ACA_REG_IDX_MISC0];</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ACA_SMU_TYPE_UE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_UE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, ACA_ERROR_TYPE_UE,</div><div class='add'>+						     1ULL);</div><div class='add'>+		break;</div><div class='add'>+	case ACA_SMU_TYPE_CE:</div><div class='add'>+		bank-&gt;aca_err_type = ACA_ERROR_TYPE_CE;</div><div class='add'>+		ret = aca_error_cache_log_bank_error(handle, &amp;info, bank-&gt;aca_err_type,</div><div class='add'>+						     ACA_REG__MISC0__ERRCNT(misc0));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* reference to smu driver if header file */</div><div class='add'>+static int vcn_v5_0_1_err_codes[] = {</div><div class='add'>+	14, 15, 47, /* VCN [D|V|S] */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,</div><div class='add'>+					 enum aca_smu_type type, void *data)</div><div class='add'>+{</div><div class='add'>+	u32 instlo;</div><div class='add'>+</div><div class='add'>+	instlo = ACA_REG__IPID__INSTANCEIDLO(bank-&gt;regs[ACA_REG_IDX_IPID]);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='add'>+</div><div class='add'>+	if (instlo != mmSMNAID_AID0_MCA_SMU)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (aca_bank_check_error_codes(handle-&gt;adev, bank,</div><div class='add'>+				       vcn_v5_0_1_err_codes,</div><div class='add'>+				       ARRAY_SIZE(vcn_v5_0_1_err_codes)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct aca_bank_ops vcn_v5_0_1_aca_bank_ops = {</div><div class='add'>+	.aca_bank_parser = vcn_v5_0_1_aca_bank_parser,</div><div class='add'>+	.aca_bank_is_valid = vcn_v5_0_1_aca_bank_is_valid,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct aca_info vcn_v5_0_1_aca_info = {</div><div class='add'>+	.hwip = ACA_HWIP_TYPE_SMU,</div><div class='add'>+	.mask = ACA_ERROR_UE_MASK,</div><div class='add'>+	.bank_ops = &amp;vcn_v5_0_1_aca_bank_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_block_late_init(adev, ras_block);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN,</div><div class='add'>+				&amp;vcn_v5_0_1_aca_info, NULL);</div><div class='add'>+	if (r)</div><div class='add'>+		goto late_fini;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ras_is_supported(adev, ras_block-&gt;block) &amp;&amp;</div><div class='add'>+		adev-&gt;vcn.inst-&gt;ras_poison_irq.funcs) {</div><div class='add'>+		r = amdgpu_irq_get(adev, &amp;adev-&gt;vcn.inst-&gt;ras_poison_irq, 0);</div><div class='add'>+		if (r)</div><div class='add'>+			goto late_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+late_fini:</div><div class='add'>+	amdgpu_ras_block_late_fini(adev, ras_block);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct amdgpu_vcn_ras vcn_v5_0_1_ras = {</div><div class='add'>+	.ras_block = {</div><div class='add'>+		.hw_ops = &amp;vcn_v5_0_1_ras_hw_ops,</div><div class='add'>+		.ras_late_init = vcn_v5_0_1_ras_late_init,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void vcn_v5_0_1_set_ras_funcs(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	adev-&gt;vcn.ras = &amp;vcn_v5_0_1_ras;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h<br/>new file mode 100644<br/>index 000000000000..b72e4da68317<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __VCN_v5_0_1_H__</div><div class='add'>+#define __VCN_v5_0_1_H__</div><div class='add'>+</div><div class='add'>+#define regVCN_RRMT_CNTL                          0x0940</div><div class='add'>+#define regVCN_RRMT_CNTL_BASE_IDX                 1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+enum amdgpu_vcn_v5_0_1_sub_block {</div><div class='add'>+	AMDGPU_VCN_V5_0_1_VCPU_VCODEC = 0,</div><div class='add'>+</div><div class='add'>+	AMDGPU_VCN_V5_0_1_MAX_SUB_BLOCK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block;</div><div class='add'>+</div><div class='add'>+#endif /* __VCN_v5_0_1_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c<br/>index bf68e18e3824..eb16916c6473 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vega10_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vega10_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vega10_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vega10_ih.c</a></div><div class='hunk'>@@ -364,9 +364,8 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> 	 * this should allow us to catchup.</div><div class='ctx'> 	 */</div><div class='ctx'> 	tmp = (wptr + 32) &amp; ih-&gt;ptr_mask;</div><div class='del'>-	dev_warn(adev-&gt;dev, "IH ring buffer overflow "</div><div class='del'>-		 "(0x%08X, 0x%08X, 0x%08X)\n",</div><div class='del'>-		 wptr, ih-&gt;rptr, tmp);</div><div class='add'>+	dev_warn_ratelimited(adev-&gt;dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",</div><div class='add'>+			     amdgpu_ih_ring_name(adev, ih), wptr, ih-&gt;rptr, tmp);</div><div class='ctx'> 	ih-&gt;rptr = tmp;</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl);</div><div class='hunk'>@@ -472,18 +471,18 @@ static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.self_irq.funcs = &amp;vega10_ih_self_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_early_init(void *handle)</div><div class='add'>+static int vega10_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	vega10_ih_set_interrupt_funcs(adev);</div><div class='ctx'> 	vega10_ih_set_self_irq_funcs(adev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_sw_init(void *handle)</div><div class='add'>+static int vega10_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,</div><div class='hunk'>@@ -525,58 +524,50 @@ static int vega10_ih_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_sw_fini(void *handle)</div><div class='add'>+static int vega10_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_hw_init(void *handle)</div><div class='add'>+static int vega10_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vega10_ih_irq_init(adev);</div><div class='add'>+	return vega10_ih_irq_init(ip_block-&gt;adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_hw_fini(void *handle)</div><div class='add'>+static int vega10_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	vega10_ih_irq_disable(adev);</div><div class='add'>+	vega10_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_suspend(void *handle)</div><div class='add'>+static int vega10_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vega10_ih_hw_fini(adev);</div><div class='add'>+	return vega10_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_resume(void *handle)</div><div class='add'>+static int vega10_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vega10_ih_hw_init(adev);</div><div class='add'>+	return vega10_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vega10_ih_is_idle(void *handle)</div><div class='add'>+static bool vega10_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_wait_for_idle(void *handle)</div><div class='add'>+static int vega10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_soft_reset(void *handle)</div><div class='add'>+static int vega10_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> </div><div class='hunk'>@@ -613,10 +604,10 @@ static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int vega10_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	vega10_ih_update_clockgating_state(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='hunk'>@@ -624,7 +615,7 @@ static int vega10_ih_set_clockgating_state(void *handle,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega10_ih_set_powergating_state(void *handle,</div><div class='add'>+static int vega10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -633,7 +624,6 @@ static int vega10_ih_set_powergating_state(void *handle,</div><div class='ctx'> const struct amd_ip_funcs vega10_ih_ip_funcs = {</div><div class='ctx'> 	.name = "vega10_ih",</div><div class='ctx'> 	.early_init = vega10_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vega10_ih_sw_init,</div><div class='ctx'> 	.sw_fini = vega10_ih_sw_fini,</div><div class='ctx'> 	.hw_init = vega10_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c<br/>index b9e785846637..85846fd08ce4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vega20_ih.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vega20_ih.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vega20_ih.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vega20_ih.c</a></div><div class='hunk'>@@ -114,6 +114,33 @@ static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);</div><div class='ctx'> </div><div class='add'>+	if (enable) {</div><div class='add'>+		/* Unset the CLEAR_OVERFLOW bit to make sure the next step</div><div class='add'>+		 * is switching the bit from 0 to 1</div><div class='add'>+		 */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; amdgpu_sriov_reg_indirect_ih(adev)) {</div><div class='add'>+			if (psp_reg_program(&amp;adev-&gt;psp, ih_regs-&gt;psp_reg_id, tmp))</div><div class='add'>+				return -ETIMEDOUT;</div><div class='add'>+		} else {</div><div class='add'>+			WREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl, tmp);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Clear RB_OVERFLOW bit */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp; amdgpu_sriov_reg_indirect_ih(adev)) {</div><div class='add'>+			if (psp_reg_program(&amp;adev-&gt;psp, ih_regs-&gt;psp_reg_id, tmp))</div><div class='add'>+				return -ETIMEDOUT;</div><div class='add'>+		} else {</div><div class='add'>+			WREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl, tmp);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows</div><div class='add'>+		 * can be detected.</div><div class='add'>+		 */</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* enable_intr field is only valid in ring0 */</div><div class='ctx'> 	if (ih == &amp;adev-&gt;irq.ih)</div><div class='ctx'> 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));</div><div class='hunk'>@@ -306,7 +333,8 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 		 * driver needs to program it properly according to</div><div class='ctx'> 		 * MC_SPACE type in IH_RB_CNTL */</div><div class='ctx'> 		if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) ||</div><div class='del'>-		    (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) {</div><div class='add'>+		    (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) ||</div><div class='add'>+		    (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) {</div><div class='ctx'> 			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);</div><div class='ctx'> 			if (adev-&gt;irq.ih.use_bus_addr) {</div><div class='ctx'> 				ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,</div><div class='hunk'>@@ -322,6 +350,7 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		}</div><div class='add'>+		ih[i]-&gt;overflow = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -337,7 +366,9 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	/* Enable IH Retry CAM */</div><div class='ctx'> 	if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) ||</div><div class='del'>-	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))</div><div class='add'>+	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) ||</div><div class='add'>+	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 4) ||</div><div class='add'>+	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))</div><div class='ctx'> 		WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,</div><div class='ctx'> 			       ENABLE, 1);</div><div class='ctx'> 	else</div><div class='hunk'>@@ -407,16 +438,18 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);</div><div class='add'>+	if (!amdgpu_sriov_vf(adev))</div><div class='add'>+		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);</div><div class='add'>+	else</div><div class='add'>+		ih-&gt;overflow = true;</div><div class='ctx'> </div><div class='ctx'> 	/* When a ring buffer overflow happen start parsing interrupt</div><div class='ctx'> 	 * from the last not overwritten vector (wptr + 32). Hopefully</div><div class='ctx'> 	 * this should allow us to catchup.</div><div class='ctx'> 	 */</div><div class='ctx'> 	tmp = (wptr + 32) &amp; ih-&gt;ptr_mask;</div><div class='del'>-	dev_warn(adev-&gt;dev, "IH ring buffer overflow "</div><div class='del'>-		 "(0x%08X, 0x%08X, 0x%08X)\n",</div><div class='del'>-		 wptr, ih-&gt;rptr, tmp);</div><div class='add'>+	dev_warn_ratelimited(adev-&gt;dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",</div><div class='add'>+			     amdgpu_ih_ring_name(adev, ih), wptr, ih-&gt;rptr, tmp);</div><div class='ctx'> 	ih-&gt;rptr = tmp;</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_NO_KIQ(ih_regs-&gt;ih_rb_cntl);</div><div class='hunk'>@@ -524,18 +557,18 @@ static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;irq.self_irq.funcs = &amp;vega20_ih_self_irq_funcs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_early_init(void *handle)</div><div class='add'>+static int vega20_ih_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	vega20_ih_set_interrupt_funcs(adev);</div><div class='ctx'> 	vega20_ih_set_self_irq_funcs(adev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_sw_init(void *handle)</div><div class='add'>+static int vega20_ih_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	bool use_bus_addr = true;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -562,7 +595,8 @@ static int vega20_ih_sw_init(void *handle)</div><div class='ctx'> 	adev-&gt;irq.ih1.use_doorbell = true;</div><div class='ctx'> 	adev-&gt;irq.ih1.doorbell_index = (adev-&gt;doorbell_index.ih + 1) &lt;&lt; 1;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2)) {</div><div class='add'>+	if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) {</div><div class='ctx'> 		r = amdgpu_ih_ring_init(adev, &amp;adev-&gt;irq.ih2, PAGE_SIZE, true);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='hunk'>@@ -583,19 +617,19 @@ static int vega20_ih_sw_init(void *handle)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_sw_fini(void *handle)</div><div class='add'>+static int vega20_ih_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_fini_sw(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_hw_init(void *handle)</div><div class='add'>+static int vega20_ih_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	r = vega20_ih_irq_init(adev);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -604,42 +638,36 @@ static int vega20_ih_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_hw_fini(void *handle)</div><div class='add'>+static int vega20_ih_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	vega20_ih_irq_disable(adev);</div><div class='add'>+	vega20_ih_irq_disable(ip_block-&gt;adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_suspend(void *handle)</div><div class='add'>+static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vega20_ih_hw_fini(adev);</div><div class='add'>+	return vega20_ih_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_resume(void *handle)</div><div class='add'>+static int vega20_ih_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vega20_ih_hw_init(adev);</div><div class='add'>+	return vega20_ih_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vega20_ih_is_idle(void *handle)</div><div class='add'>+static bool vega20_ih_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_wait_for_idle(void *handle)</div><div class='add'>+static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_soft_reset(void *handle)</div><div class='add'>+static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* todo */</div><div class='ctx'> </div><div class='hunk'>@@ -673,10 +701,10 @@ static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_set_clockgating_state(void *handle,</div><div class='add'>+static int vega20_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	vega20_ih_update_clockgating_state(adev,</div><div class='ctx'> 				state == AMD_CG_STATE_GATE);</div><div class='hunk'>@@ -684,7 +712,7 @@ static int vega20_ih_set_clockgating_state(void *handle,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vega20_ih_set_powergating_state(void *handle,</div><div class='add'>+static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -693,7 +721,6 @@ static int vega20_ih_set_powergating_state(void *handle,</div><div class='ctx'> const struct amd_ip_funcs vega20_ih_ip_funcs = {</div><div class='ctx'> 	.name = "vega20_ih",</div><div class='ctx'> 	.early_init = vega20_ih_early_init,</div><div class='del'>-	.late_init = NULL,</div><div class='ctx'> 	.sw_init = vega20_ih_sw_init,</div><div class='ctx'> 	.sw_fini = vega20_ih_sw_fini,</div><div class='ctx'> 	.hw_init = vega20_ih_hw_init,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c<br/>index 1a98812981f4..a611a7345125 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vi.c</a></div><div class='hunk'>@@ -67,7 +67,6 @@</div><div class='ctx'> #include "sdma_v2_4.h"</div><div class='ctx'> #include "sdma_v3_0.h"</div><div class='ctx'> #include "dce_v10_0.h"</div><div class='del'>-#include "dce_v11_0.h"</div><div class='ctx'> #include "iceland_ih.h"</div><div class='ctx'> #include "tonga_ih.h"</div><div class='ctx'> #include "cz_ih.h"</div><div class='hunk'>@@ -136,15 +135,15 @@ static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[]</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,</div><div class='ctx'> 		.max_width = 4096,</div><div class='del'>-		.max_height = 2304,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 2304,</div><div class='add'>+		.max_height = 4096,</div><div class='add'>+		.max_pixels_per_frame = 4096 * 4096,</div><div class='ctx'> 		.max_level = 0,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,</div><div class='ctx'> 		.max_width = 4096,</div><div class='del'>-		.max_height = 2304,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 2304,</div><div class='add'>+		.max_height = 4096,</div><div class='add'>+		.max_pixels_per_frame = 4096 * 4096,</div><div class='ctx'> 		.max_level = 0,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -167,16 +166,16 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =</div><div class='ctx'> {</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,</div><div class='del'>-		.max_width = 4096,</div><div class='del'>-		.max_height = 4096,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 4096,</div><div class='add'>+		.max_width = 1920,</div><div class='add'>+		.max_height = 1088,</div><div class='add'>+		.max_pixels_per_frame = 1920 * 1088,</div><div class='ctx'> 		.max_level = 3,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,</div><div class='del'>-		.max_width = 4096,</div><div class='del'>-		.max_height = 4096,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 4096,</div><div class='add'>+		.max_width = 1920,</div><div class='add'>+		.max_height = 1088,</div><div class='add'>+		.max_pixels_per_frame = 1920 * 1088,</div><div class='ctx'> 		.max_level = 5,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='hunk'>@@ -188,9 +187,9 @@ static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,</div><div class='del'>-		.max_width = 4096,</div><div class='del'>-		.max_height = 4096,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 4096,</div><div class='add'>+		.max_width = 1920,</div><div class='add'>+		.max_height = 1088,</div><div class='add'>+		.max_pixels_per_frame = 1920 * 1088,</div><div class='ctx'> 		.max_level = 4,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -206,16 +205,16 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =</div><div class='ctx'> {</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,</div><div class='del'>-		.max_width = 4096,</div><div class='del'>-		.max_height = 4096,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 4096,</div><div class='add'>+		.max_width = 1920,</div><div class='add'>+		.max_height = 1088,</div><div class='add'>+		.max_pixels_per_frame = 1920 * 1088,</div><div class='ctx'> 		.max_level = 3,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,</div><div class='del'>-		.max_width = 4096,</div><div class='del'>-		.max_height = 4096,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 4096,</div><div class='add'>+		.max_width = 1920,</div><div class='add'>+		.max_height = 1088,</div><div class='add'>+		.max_pixels_per_frame = 1920 * 1088,</div><div class='ctx'> 		.max_level = 5,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='hunk'>@@ -227,9 +226,9 @@ static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,</div><div class='del'>-		.max_width = 4096,</div><div class='del'>-		.max_height = 4096,</div><div class='del'>-		.max_pixels_per_frame = 4096 * 4096,</div><div class='add'>+		.max_width = 1920,</div><div class='add'>+		.max_height = 1088,</div><div class='add'>+		.max_pixels_per_frame = 1920 * 1088,</div><div class='ctx'> 		.max_level = 4,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='hunk'>@@ -897,7 +896,7 @@ static int vi_asic_pci_config_reset(struct amdgpu_device *adev)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vi_asic_supports_baco(struct amdgpu_device *adev)</div><div class='add'>+static int vi_asic_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> 	case CHIP_FIJI:</div><div class='hunk'>@@ -908,14 +907,14 @@ static bool vi_asic_supports_baco(struct amdgpu_device *adev)</div><div class='ctx'> 	case CHIP_TOPAZ:</div><div class='ctx'> 		return amdgpu_dpm_is_baco_supported(adev);</div><div class='ctx'> 	default:</div><div class='del'>-		return false;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum amd_reset_method</div><div class='ctx'> vi_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	bool baco_reset;</div><div class='add'>+	int baco_reset;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||</div><div class='ctx'> 	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)</div><div class='hunk'>@@ -935,7 +934,7 @@ vi_asic_reset_method(struct amdgpu_device *adev)</div><div class='ctx'> 		baco_reset = amdgpu_dpm_is_baco_supported(adev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		baco_reset = false;</div><div class='add'>+		baco_reset = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1455,9 +1454,9 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =</div><div class='ctx'> #define CZ_REV_BRISTOL(rev)	 \</div><div class='ctx'> 	((rev &gt;= 0xC8 &amp;&amp; rev &lt;= 0xCE) || (rev &gt;= 0xE1 &amp;&amp; rev &lt;= 0xE6))</div><div class='ctx'> </div><div class='del'>-static int vi_common_early_init(void *handle)</div><div class='add'>+static int vi_common_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;flags &amp; AMD_IS_APU) {</div><div class='ctx'> 		adev-&gt;smc_rreg = &amp;cz_smc_rreg;</div><div class='hunk'>@@ -1679,9 +1678,9 @@ static int vi_common_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_late_init(void *handle)</div><div class='add'>+static int vi_common_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_vi_mailbox_get_irq(adev);</div><div class='hunk'>@@ -1689,9 +1688,9 @@ static int vi_common_late_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_sw_init(void *handle)</div><div class='add'>+static int vi_common_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		xgpu_vi_mailbox_add_irq_id(adev);</div><div class='hunk'>@@ -1699,14 +1698,9 @@ static int vi_common_sw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_sw_fini(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vi_common_hw_init(void *handle)</div><div class='add'>+static int vi_common_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* move the golden regs per IP block */</div><div class='ctx'> 	vi_init_golden_registers(adev);</div><div class='hunk'>@@ -1718,9 +1712,9 @@ static int vi_common_hw_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_hw_fini(void *handle)</div><div class='add'>+static int vi_common_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* enable the doorbell aperture */</div><div class='ctx'> 	vi_enable_doorbell_aperture(adev, false);</div><div class='hunk'>@@ -1731,35 +1725,21 @@ static int vi_common_hw_fini(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_suspend(void *handle)</div><div class='add'>+static int vi_common_suspend(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vi_common_hw_fini(adev);</div><div class='add'>+	return vi_common_hw_fini(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_resume(void *handle)</div><div class='add'>+static int vi_common_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='del'>-</div><div class='del'>-	return vi_common_hw_init(adev);</div><div class='add'>+	return vi_common_hw_init(ip_block);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool vi_common_is_idle(void *handle)</div><div class='add'>+static bool vi_common_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_wait_for_idle(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int vi_common_soft_reset(void *handle)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,</div><div class='ctx'> 						   bool enable)</div><div class='ctx'> {</div><div class='hunk'>@@ -1964,10 +1944,10 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_set_clockgating_state(void *handle,</div><div class='add'>+static int vi_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					   enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -2007,15 +1987,15 @@ static int vi_common_set_clockgating_state(void *handle,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vi_common_set_powergating_state(void *handle,</div><div class='add'>+static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 					    enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vi_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='add'>+static void vi_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='hunk'>@@ -2047,14 +2027,11 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {</div><div class='ctx'> 	.early_init = vi_common_early_init,</div><div class='ctx'> 	.late_init = vi_common_late_init,</div><div class='ctx'> 	.sw_init = vi_common_sw_init,</div><div class='del'>-	.sw_fini = vi_common_sw_fini,</div><div class='ctx'> 	.hw_init = vi_common_hw_init,</div><div class='ctx'> 	.hw_fini = vi_common_hw_fini,</div><div class='ctx'> 	.suspend = vi_common_suspend,</div><div class='ctx'> 	.resume = vi_common_resume,</div><div class='ctx'> 	.is_idle = vi_common_is_idle,</div><div class='del'>-	.wait_for_idle = vi_common_wait_for_idle,</div><div class='del'>-	.soft_reset = vi_common_soft_reset,</div><div class='ctx'> 	.set_clockgating_state = vi_common_set_clockgating_state,</div><div class='ctx'> 	.set_powergating_state = vi_common_set_powergating_state,</div><div class='ctx'> 	.get_clockgating_state = vi_common_get_clockgating_state,</div><div class='hunk'>@@ -2146,8 +2123,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		else if (amdgpu_device_has_dc_support(adev))</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;dm_ip_block);</div><div class='ctx'> #endif</div><div class='del'>-		else</div><div class='del'>-			amdgpu_device_ip_block_add(adev, &amp;dce_v11_2_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;uvd_v6_3_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;vce_v3_4_ip_block);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -2164,8 +2139,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		else if (amdgpu_device_has_dc_support(adev))</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;dm_ip_block);</div><div class='ctx'> #endif</div><div class='del'>-		else</div><div class='del'>-			amdgpu_device_ip_block_add(adev, &amp;dce_v11_0_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;uvd_v6_0_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;vce_v3_1_ip_block);</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_ACP)</div><div class='hunk'>@@ -2185,8 +2158,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		else if (amdgpu_device_has_dc_support(adev))</div><div class='ctx'> 			amdgpu_device_ip_block_add(adev, &amp;dm_ip_block);</div><div class='ctx'> #endif</div><div class='del'>-		else</div><div class='del'>-			amdgpu_device_ip_block_add(adev, &amp;dce_v11_0_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;uvd_v6_2_ip_block);</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;vce_v3_4_ip_block);</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_ACP)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h<br/>index 80ce42aacc0c..b61f6b838ec2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vid.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vid.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vid.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vid.h</a></div><div class='hunk'>@@ -246,6 +246,7 @@</div><div class='ctx'> 		 * 1 - Stream</div><div class='ctx'> 		 * 2 - Bypass</div><div class='ctx'> 		 */</div><div class='add'>+#define		EOP_EXEC				(1 &lt;&lt; 28) /* For Trailing Fence */</div><div class='ctx'> #define		DATA_SEL(x)                             ((x) &lt;&lt; 29)</div><div class='ctx'> 		/* 0 - discard</div><div class='ctx'> 		 * 1 - send low 32bit data</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c<br/>index 769eb8f7bb3c..45876883bbf3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> </div><div class='ctx'> MODULE_FIRMWARE("amdgpu/vpe_6_1_0.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/vpe_6_1_1.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/vpe_6_1_3.bin");</div><div class='ctx'> </div><div class='ctx'> #define VPE_THREAD1_UCODE_OFFSET	0x8000</div><div class='ctx'> </div><div class='hunk'>@@ -144,6 +145,12 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)</div><div class='ctx'> 			WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* setup collaborate mode */</div><div class='add'>+	vpe_v6_1_set_collaborate_mode(vpe, true);</div><div class='add'>+	/* setup DPM */</div><div class='add'>+	if (amdgpu_vpe_configure_dpm(vpe))</div><div class='add'>+		dev_warn(adev-&gt;dev, "VPE failed to enable DPM\n");</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * For VPE 6.1.1, still only need to add master's offset, and psp will apply it to slave as well.</div><div class='ctx'> 	 * Here use instance 0 as master.</div><div class='hunk'>@@ -159,11 +166,7 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)</div><div class='ctx'> 		adev-&gt;vpe.cmdbuf_cpu_addr[0] = f32_offset;</div><div class='ctx'> 		adev-&gt;vpe.cmdbuf_cpu_addr[1] = f32_cntl;</div><div class='ctx'> </div><div class='del'>-		amdgpu_vpe_psp_update_sram(adev);</div><div class='del'>-		vpe_v6_1_set_collaborate_mode(vpe, true);</div><div class='del'>-		amdgpu_vpe_configure_dpm(vpe);</div><div class='del'>-</div><div class='del'>-		return 0;</div><div class='add'>+		return amdgpu_vpe_psp_update_sram(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev-&gt;vpe.fw-&gt;data;</div><div class='hunk'>@@ -196,8 +199,6 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vpe_v6_1_halt(vpe, false);</div><div class='del'>-	vpe_v6_1_set_collaborate_mode(vpe, true);</div><div class='del'>-	amdgpu_vpe_configure_dpm(vpe);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig<br/>index d3c3d3ab7225..16e12c9913f9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/Kconfig?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/Kconfig</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/Kconfig?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/Kconfig</a></div><div class='hunk'>@@ -5,7 +5,7 @@</div><div class='ctx'> </div><div class='ctx'> config HSA_AMD</div><div class='ctx'> 	bool "HSA kernel driver for AMD GPU devices"</div><div class='del'>-	depends on DRM_AMDGPU &amp;&amp; (X86_64 || ARM64 || PPC64)</div><div class='add'>+	depends on DRM_AMDGPU &amp;&amp; (X86_64 || ARM64 || PPC64 || (RISCV &amp;&amp; 64BIT) || (LOONGARCH &amp;&amp; 64BIT))</div><div class='ctx'> 	select HMM_MIRROR</div><div class='ctx'> 	select MMU_NOTIFIER</div><div class='ctx'> 	select DRM_AMDGPU_USERPTR</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile<br/>index a5ae7bcf44eb..0ce08113c9f0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/Makefile</a></div><div class='hunk'>@@ -27,7 +27,6 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_device.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_chardev.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_topology.o \</div><div class='del'>-		$(AMDKFD_PATH)/kfd_pasid.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_doorbell.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_flat_memory.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_process.o \</div><div class='hunk'>@@ -38,6 +37,7 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_mqd_manager_v9.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_mqd_manager_v10.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_mqd_manager_v11.o \</div><div class='add'>+		$(AMDKFD_PATH)/kfd_mqd_manager_v12.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_kernel_queue.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_packet_manager.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_packet_manager_vi.o \</div><div class='hunk'>@@ -49,6 +49,7 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_device_queue_manager_v9.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_device_queue_manager_v10.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_device_queue_manager_v11.o \</div><div class='add'>+		$(AMDKFD_PATH)/kfd_device_queue_manager_v12.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_interrupt.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/kfd_events.o \</div><div class='ctx'> 		$(AMDKFD_PATH)/cik_event_interrupt.o \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c<br/>index 795382b55e0a..73acbe0b7c21 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c</a></div><div class='hunk'>@@ -91,7 +91,6 @@ static void cik_event_interrupt_wq(struct kfd_node *dev,</div><div class='ctx'> 	const struct cik_ih_ring_entry *ihre =</div><div class='ctx'> 			(const struct cik_ih_ring_entry *)ih_ring_entry;</div><div class='ctx'> 	uint32_t context_id = ihre-&gt;data &amp; 0xfffffff;</div><div class='del'>-	unsigned int vmid  = (ihre-&gt;ring_id &amp; 0x0000ff00) &gt;&gt; 8;</div><div class='ctx'> 	u32 pasid = (ihre-&gt;ring_id &amp; 0xffff0000) &gt;&gt; 16;</div><div class='ctx'> </div><div class='ctx'> 	if (pasid == 0)</div><div class='hunk'>@@ -107,20 +106,26 @@ static void cik_event_interrupt_wq(struct kfd_node *dev,</div><div class='ctx'> 		kfd_signal_hw_exception_event(pasid);</div><div class='ctx'> 	else if (ihre-&gt;source_id == CIK_INTSRC_GFX_PAGE_INV_FAULT ||</div><div class='ctx'> 		ihre-&gt;source_id == CIK_INTSRC_GFX_MEM_PROT_FAULT) {</div><div class='add'>+		struct kfd_process_device *pdd = NULL;</div><div class='ctx'> 		struct kfd_vm_fault_info info;</div><div class='add'>+		struct kfd_process *p;</div><div class='ctx'> </div><div class='ctx'> 		kfd_smi_event_update_vmfault(dev, pasid);</div><div class='del'>-		kfd_dqm_evict_pasid(dev-&gt;dqm, pasid);</div><div class='add'>+		p = kfd_lookup_process_by_pasid(pasid, &amp;pdd);</div><div class='add'>+		if (!pdd)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		kfd_evict_process_device(pdd);</div><div class='ctx'> </div><div class='ctx'> 		memset(&amp;info, 0, sizeof(info));</div><div class='ctx'> 		amdgpu_amdkfd_gpuvm_get_vm_fault_info(dev-&gt;adev, &amp;info);</div><div class='del'>-		if (!info.page_addr &amp;&amp; !info.status)</div><div class='add'>+		if (!info.page_addr &amp;&amp; !info.status) {</div><div class='add'>+			kfd_unref_process(p);</div><div class='ctx'> 			return;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (info.vmid == vmid)</div><div class='del'>-			kfd_signal_vm_fault_event(dev, pasid, &amp;info, NULL);</div><div class='del'>-		else</div><div class='del'>-			kfd_signal_vm_fault_event(dev, pasid, NULL, NULL);</div><div class='add'>+		kfd_signal_vm_fault_event(pdd, &amp;info, NULL);</div><div class='add'>+		kfd_unref_process(p);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h<br/>index 5a0308d26b53..0320163b6e74 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h</a></div><div class='hunk'>@@ -274,7 +274,7 @@ static const uint32_t cwsr_trap_gfx8_hex[] = {</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_gfx9_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf820258,</div><div class='add'>+	0xbf820001, 0xbf820259,</div><div class='ctx'> 	0xb8f8f802, 0x8978ff78,</div><div class='ctx'> 	0x00020006, 0xb8fbf803,</div><div class='ctx'> 	0x866eff78, 0x00002000,</div><div class='hunk'>@@ -390,141 +390,98 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {</div><div class='ctx'> 	0xbefe007c, 0xbefc0070,</div><div class='ctx'> 	0xc0611c7a, 0x0000007c,</div><div class='ctx'> 	0xbf8cc07f, 0x80708470,</div><div class='del'>-	0xbefc007e, 0x867aff7f,</div><div class='del'>-	0x04000000, 0xbeef0080,</div><div class='del'>-	0x876f6f7a, 0xb8f02a05,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0xb8fb1605, 0x807b817b,</div><div class='del'>-	0x8e7b847b, 0x8e76827b,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbef20174, 0x80747074,</div><div class='del'>-	0x82758075, 0xbefc0080,</div><div class='del'>-	0xbf800000, 0xbe802b00,</div><div class='del'>-	0xbe822b02, 0xbe842b04,</div><div class='del'>-	0xbe862b06, 0xbe882b08,</div><div class='del'>-	0xbe8a2b0a, 0xbe8c2b0c,</div><div class='del'>-	0xbe8e2b0e, 0xc06b003a,</div><div class='del'>-	0x00000000, 0xbf8cc07f,</div><div class='del'>-	0xc06b013a, 0x00000010,</div><div class='del'>-	0xbf8cc07f, 0xc06b023a,</div><div class='del'>-	0x00000020, 0xbf8cc07f,</div><div class='del'>-	0xc06b033a, 0x00000030,</div><div class='del'>-	0xbf8cc07f, 0x8074c074,</div><div class='del'>-	0x82758075, 0x807c907c,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffe7,</div><div class='del'>-	0xbef40172, 0xbef00080,</div><div class='del'>-	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xbee80080, 0xbee90080,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0x867aff78, 0x00400000,</div><div class='del'>-	0xbf850003, 0xb8faf803,</div><div class='del'>-	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf85004d, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000900,</div><div class='del'>-	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000900,</div><div class='del'>-	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xc069003a, 0x00000070,</div><div class='del'>-	0xbf8cc07f, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbefc007e, 0xbf108080,</div><div class='add'>+	0x867aff7f, 0x04000000,</div><div class='add'>+	0xbeef0080, 0x876f6f7a,</div><div class='add'>+	0xb8f02a05, 0x80708170,</div><div class='add'>+	0x8e708a70, 0xb8fb1605,</div><div class='add'>+	0x807b817b, 0x8e7b847b,</div><div class='add'>+	0x8e76827b, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbef20174,</div><div class='add'>+	0x80747074, 0x82758075,</div><div class='add'>+	0xbefc0080, 0xbf800000,</div><div class='add'>+	0xbe802b00, 0xbe822b02,</div><div class='add'>+	0xbe842b04, 0xbe862b06,</div><div class='add'>+	0xbe882b08, 0xbe8a2b0a,</div><div class='add'>+	0xbe8c2b0c, 0xbe8e2b0e,</div><div class='add'>+	0xc06b003a, 0x00000000,</div><div class='add'>+	0xbf8cc07f, 0xc06b013a,</div><div class='add'>+	0x00000010, 0xbf8cc07f,</div><div class='add'>+	0xc06b023a, 0x00000020,</div><div class='add'>+	0xbf8cc07f, 0xc06b033a,</div><div class='add'>+	0x00000030, 0xbf8cc07f,</div><div class='add'>+	0x8074c074, 0x82758075,</div><div class='add'>+	0x807c907c, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffe7, 0xbef40172,</div><div class='add'>+	0xbef00080, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xbee80080,</div><div class='add'>+	0xbee90080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0x867aff78,</div><div class='add'>+	0x00400000, 0xbf850003,</div><div class='add'>+	0xb8faf803, 0x897a7aff,</div><div class='add'>+	0x10000000, 0xbf85004d,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000901,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000901,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000902,</div><div class='add'>+	0xd2890000, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000903,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000903,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbf820008,</div><div class='del'>-	0xe0724000, 0x701d0000,</div><div class='del'>-	0xe0724100, 0x701d0100,</div><div class='del'>-	0xe0724200, 0x701d0200,</div><div class='del'>-	0xe0724300, 0x701d0300,</div><div class='del'>-	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8fb4306, 0x867bc17b,</div><div class='del'>-	0xbf840063, 0xbf8a0000,</div><div class='del'>-	0x867aff6f, 0x04000000,</div><div class='del'>-	0xbf84005f, 0x8e7b867b,</div><div class='del'>-	0x8e7b827b, 0xbef6007b,</div><div class='del'>-	0xb8f02a05, 0x80708170,</div><div class='del'>-	0x8e708a70, 0xb8fa1605,</div><div class='del'>-	0x807a817a, 0x8e7a867a,</div><div class='del'>-	0x80707a70, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0080,</div><div class='del'>-	0xd28c0002, 0x000100c1,</div><div class='del'>-	0xd28d0003, 0x000204c1,</div><div class='del'>-	0x867aff78, 0x00400000,</div><div class='del'>-	0xbf850003, 0xb8faf803,</div><div class='del'>-	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf850030, 0x24040682,</div><div class='del'>-	0xd86e4000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000900,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000903,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000900,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000903,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000901,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000901,</div><div class='del'>-	0x80048104, 0xc069003a,</div><div class='del'>-	0x00000070, 0xbf8cc07f,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0x680404ff,</div><div class='del'>-	0x00000200, 0xd0c9006a,</div><div class='del'>-	0x0000f702, 0xbf87ffd2,</div><div class='del'>-	0xbf820015, 0xd1060002,</div><div class='del'>-	0x00011103, 0x7e0602ff,</div><div class='del'>-	0x00000200, 0xbefc00ff,</div><div class='del'>-	0x00010000, 0xbe800077,</div><div class='del'>-	0x8677ff77, 0xff7fffff,</div><div class='del'>-	0x8777ff77, 0x00058000,</div><div class='del'>-	0xd8ec0000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xe0765000,</div><div class='del'>-	0x701d0002, 0x68040702,</div><div class='del'>-	0xd0c9006a, 0x0000f702,</div><div class='del'>-	0xbf87fff7, 0xbef70000,</div><div class='del'>-	0xbef000ff, 0x00000400,</div><div class='del'>-	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8fb2a05, 0x807b817b,</div><div class='del'>-	0x8e7b827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0084,</div><div class='del'>-	0xbf0a7b7c, 0xbf84006d,</div><div class='del'>-	0xbf11017c, 0x807bff7b,</div><div class='del'>-	0x00001000, 0x867aff78,</div><div class='add'>+	0xbf820008, 0xe0724000,</div><div class='add'>+	0x701d0000, 0xe0724100,</div><div class='add'>+	0x701d0100, 0xe0724200,</div><div class='add'>+	0x701d0200, 0xe0724300,</div><div class='add'>+	0x701d0300, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8fb4306,</div><div class='add'>+	0x867bc17b, 0xbf840063,</div><div class='add'>+	0xbf8a0000, 0x867aff6f,</div><div class='add'>+	0x04000000, 0xbf84005f,</div><div class='add'>+	0x8e7b867b, 0x8e7b827b,</div><div class='add'>+	0xbef6007b, 0xb8f02a05,</div><div class='add'>+	0x80708170, 0x8e708a70,</div><div class='add'>+	0xb8fa1605, 0x807a817a,</div><div class='add'>+	0x8e7a867a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0080, 0xd28c0002,</div><div class='add'>+	0x000100c1, 0xd28d0003,</div><div class='add'>+	0x000204c1, 0x867aff78,</div><div class='ctx'> 	0x00400000, 0xbf850003,</div><div class='ctx'> 	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf850051,</div><div class='add'>+	0x10000000, 0xbf850030,</div><div class='add'>+	0x24040682, 0xd86e4000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='ctx'> 	0xd2890001, 0x00000900,</div><div class='hunk'>@@ -544,141 +501,185 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0x680404ff, 0x00000200,</div><div class='add'>+	0xd0c9006a, 0x0000f702,</div><div class='add'>+	0xbf87ffd2, 0xbf820015,</div><div class='add'>+	0xd1060002, 0x00011103,</div><div class='add'>+	0x7e0602ff, 0x00000200,</div><div class='add'>+	0xbefc00ff, 0x00010000,</div><div class='add'>+	0xbe800077, 0x8677ff77,</div><div class='add'>+	0xff7fffff, 0x8777ff77,</div><div class='add'>+	0x00058000, 0xd8ec0000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='add'>+	0xe0765000, 0x701d0002,</div><div class='add'>+	0x68040702, 0xd0c9006a,</div><div class='add'>+	0x0000f702, 0xbf87fff7,</div><div class='add'>+	0xbef70000, 0xbef000ff,</div><div class='add'>+	0x00000400, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8fb2a05,</div><div class='add'>+	0x807b817b, 0x8e7b827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0084, 0xbf0a7b7c,</div><div class='add'>+	0xbf84006d, 0xbf11017c,</div><div class='add'>+	0x807bff7b, 0x00001000,</div><div class='add'>+	0x867aff78, 0x00400000,</div><div class='add'>+	0xbf850003, 0xb8faf803,</div><div class='add'>+	0x897a7aff, 0x10000000,</div><div class='add'>+	0xbf850051, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0x807c847c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffb1, 0xbf9c0000,</div><div class='del'>-	0xbf820012, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000400,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xbf9c0000, 0xbf8200c7,</div><div class='del'>-	0xbef4007e, 0x8675ff7f,</div><div class='del'>-	0x0000ffff, 0x8775ff75,</div><div class='del'>-	0x00040000, 0xbef60080,</div><div class='del'>-	0xbef700ff, 0x00807fac,</div><div class='del'>-	0x866eff7f, 0x04000000,</div><div class='del'>-	0xbf84001e, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xb8ef4306,</div><div class='del'>-	0x866fc16f, 0xbf840019,</div><div class='del'>-	0x8e6f866f, 0x8e6f826f,</div><div class='del'>-	0xbef6006f, 0xb8f82a05,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0xb8ee1605, 0x806e816e,</div><div class='del'>-	0x8e6e866e, 0x80786e78,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc0080, 0xe0510000,</div><div class='del'>-	0x781d0000, 0xe0510100,</div><div class='del'>-	0x781d0000, 0x807cff7c,</div><div class='del'>-	0x00000200, 0x8078ff78,</div><div class='del'>-	0x00000200, 0xbf0a6f7c,</div><div class='del'>-	0xbf85fff6, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xb8ef2a05,</div><div class='del'>-	0x806f816f, 0x8e6f826f,</div><div class='del'>-	0x806fff6f, 0x00008000,</div><div class='del'>-	0xbef80080, 0xbeee0078,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbefc0084, 0xbf11087c,</div><div class='del'>-	0xe0524000, 0x781d0000,</div><div class='del'>-	0xe0524100, 0x781d0100,</div><div class='del'>-	0xe0524200, 0x781d0200,</div><div class='del'>-	0xe0524300, 0x781d0300,</div><div class='del'>-	0xbf8c0f70, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0x807c847c,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbf0a6f7c, 0xbf85ffee,</div><div class='del'>-	0xbf9c0000, 0xe0524000,</div><div class='del'>-	0x6e1d0000, 0xe0524100,</div><div class='del'>-	0x6e1d0100, 0xe0524200,</div><div class='del'>-	0x6e1d0200, 0xe0524300,</div><div class='del'>-	0x6e1d0300, 0xbf8c0f70,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0x807c847c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffb1,</div><div class='add'>+	0xbf9c0000, 0xbf820012,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000400, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffef, 0xbf9c0000,</div><div class='add'>+	0xbf8200c7, 0xbef4007e,</div><div class='add'>+	0x8675ff7f, 0x0000ffff,</div><div class='add'>+	0x8775ff75, 0x00040000,</div><div class='add'>+	0xbef60080, 0xbef700ff,</div><div class='add'>+	0x00807fac, 0x866eff7f,</div><div class='add'>+	0x04000000, 0xbf84001e,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xb8ef4306, 0x866fc16f,</div><div class='add'>+	0xbf840019, 0x8e6f866f,</div><div class='add'>+	0x8e6f826f, 0xbef6006f,</div><div class='ctx'> 	0xb8f82a05, 0x80788178,</div><div class='ctx'> 	0x8e788a78, 0xb8ee1605,</div><div class='ctx'> 	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0x80f8c078,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f846f, 0x8e76826f,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc0080,</div><div class='add'>+	0xe0510000, 0x781d0000,</div><div class='add'>+	0xe0510100, 0x781d0000,</div><div class='add'>+	0x807cff7c, 0x00000200,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0xbf0a6f7c, 0xbf85fff6,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc006f, 0xc031003a,</div><div class='del'>-	0x00000078, 0x80f8c078,</div><div class='del'>-	0xbf8cc07f, 0x80fc907c,</div><div class='del'>-	0xbf800000, 0xbe802d00,</div><div class='del'>-	0xbe822d02, 0xbe842d04,</div><div class='del'>-	0xbe862d06, 0xbe882d08,</div><div class='del'>-	0xbe8a2d0a, 0xbe8c2d0c,</div><div class='del'>-	0xbe8e2d0e, 0xbf06807c,</div><div class='del'>-	0xbf84fff0, 0xb8f82a05,</div><div class='add'>+	0xb8ef2a05, 0x806f816f,</div><div class='add'>+	0x8e6f826f, 0x806fff6f,</div><div class='add'>+	0x00008000, 0xbef80080,</div><div class='add'>+	0xbeee0078, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbefc0084,</div><div class='add'>+	0xbf11087c, 0xe0524000,</div><div class='add'>+	0x781d0000, 0xe0524100,</div><div class='add'>+	0x781d0100, 0xe0524200,</div><div class='add'>+	0x781d0200, 0xe0524300,</div><div class='add'>+	0x781d0300, 0xbf8c0f70,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='add'>+	0x807c847c, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbf0a6f7c,</div><div class='add'>+	0xbf85ffee, 0xbf9c0000,</div><div class='add'>+	0xe0524000, 0x6e1d0000,</div><div class='add'>+	0xe0524100, 0x6e1d0100,</div><div class='add'>+	0xe0524200, 0x6e1d0200,</div><div class='add'>+	0xe0524300, 0x6e1d0300,</div><div class='add'>+	0xbf8c0f70, 0xb8f82a05,</div><div class='ctx'> 	0x80788178, 0x8e788a78,</div><div class='ctx'> 	0xb8ee1605, 0x806e816e,</div><div class='ctx'> 	0x8e6e866e, 0x80786e78,</div><div class='del'>-	0xbef60084, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xc0211bfa,</div><div class='add'>+	0x80f8c078, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f846f,</div><div class='add'>+	0x8e76826f, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc006f,</div><div class='add'>+	0xc031003a, 0x00000078,</div><div class='add'>+	0x80f8c078, 0xbf8cc07f,</div><div class='add'>+	0x80fc907c, 0xbf800000,</div><div class='add'>+	0xbe802d00, 0xbe822d02,</div><div class='add'>+	0xbe842d04, 0xbe862d06,</div><div class='add'>+	0xbe882d08, 0xbe8a2d0a,</div><div class='add'>+	0xbe8c2d0c, 0xbe8e2d0e,</div><div class='add'>+	0xbf06807c, 0xbf84fff0,</div><div class='add'>+	0xb8f82a05, 0x80788178,</div><div class='add'>+	0x8e788a78, 0xb8ee1605,</div><div class='add'>+	0x806e816e, 0x8e6e866e,</div><div class='add'>+	0x80786e78, 0xbef60084,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xc0211bfa, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211b3a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211b3a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211b7a,</div><div class='add'>+	0xc0211b7a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211c3a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211c3a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211c7a,</div><div class='add'>+	0xc0211c7a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211eba,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211eba, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211efa,</div><div class='add'>+	0xc0211efa, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211a3a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211a3a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211a7a,</div><div class='add'>+	0xc0211a7a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211cfa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211cfa, 0x00000078,</div><div class='del'>-	0x80788478, 0xbf8cc07f,</div><div class='del'>-	0xbefc006f, 0xbefe0070,</div><div class='del'>-	0xbeff0071, 0x866f7bff,</div><div class='del'>-	0x000003ff, 0xb96f4803,</div><div class='del'>-	0x866f7bff, 0xfffff800,</div><div class='del'>-	0x8f6f8b6f, 0xb96fa2c3,</div><div class='del'>-	0xb973f801, 0xb8ee2a05,</div><div class='del'>-	0x806e816e, 0x8e6e8a6e,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f866f, 0x806e6f6e,</div><div class='del'>-	0x806e746e, 0x826f8075,</div><div class='del'>-	0x866fff6f, 0x0000ffff,</div><div class='del'>-	0xc00b1c37, 0x00000050,</div><div class='del'>-	0xc00b1d37, 0x00000060,</div><div class='del'>-	0xc0031e77, 0x00000074,</div><div class='del'>-	0xbf8cc07f, 0x8f6e8b77,</div><div class='del'>-	0x866eff6e, 0x001f8000,</div><div class='del'>-	0xb96ef807, 0x866dff6d,</div><div class='del'>-	0x0000ffff, 0x86fe7e7e,</div><div class='del'>-	0x86ea6a6a, 0x8f6e837a,</div><div class='del'>-	0xb96ee0c2, 0xbf800002,</div><div class='del'>-	0xb97a0002, 0xbf8a0000,</div><div class='del'>-	0xbe801f6c, 0xbf9b0000,</div><div class='add'>+	0xbf8cc07f, 0xbefc006f,</div><div class='add'>+	0xbefe0070, 0xbeff0071,</div><div class='add'>+	0x866f7bff, 0x000003ff,</div><div class='add'>+	0xb96f4803, 0x866f7bff,</div><div class='add'>+	0xfffff800, 0x8f6f8b6f,</div><div class='add'>+	0xb96fa2c3, 0xb973f801,</div><div class='add'>+	0xb8ee2a05, 0x806e816e,</div><div class='add'>+	0x8e6e8a6e, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f866f,</div><div class='add'>+	0x806e6f6e, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x866fff6f,</div><div class='add'>+	0x0000ffff, 0xc00b1c37,</div><div class='add'>+	0x00000050, 0xc00b1d37,</div><div class='add'>+	0x00000060, 0xc0031e77,</div><div class='add'>+	0x00000074, 0xbf8cc07f,</div><div class='add'>+	0x8f6e8b77, 0x866eff6e,</div><div class='add'>+	0x001f8000, 0xb96ef807,</div><div class='add'>+	0x866dff6d, 0x0000ffff,</div><div class='add'>+	0x86fe7e7e, 0x86ea6a6a,</div><div class='add'>+	0x8f6e837a, 0xb96ee0c2,</div><div class='add'>+	0xbf800002, 0xb97a0002,</div><div class='add'>+	0xbf8a0000, 0xbe801f6c,</div><div class='add'>+	0xbf9b0000, 0x00000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf820394,</div><div class='add'>+	0xbf820001, 0xbf820393,</div><div class='ctx'> 	0xb0804004, 0xb978f802,</div><div class='ctx'> 	0x8a78ff78, 0x00020006,</div><div class='ctx'> 	0xb97bf803, 0x876eff78,</div><div class='hunk'>@@ -711,19 +712,19 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0xbf0d8f7b, 0xbf840002,</div><div class='ctx'> 	0x887bff7b, 0xffff0000,</div><div class='ctx'> 	0xf4011bbd, 0xfa000010,</div><div class='del'>-	0xbf8cc07f, 0x8f6e976e,</div><div class='add'>+	0xbf8c0000, 0x8f6e976e,</div><div class='ctx'> 	0x8a77ff77, 0x00800000,</div><div class='ctx'> 	0x88776e77, 0xf4051bbd,</div><div class='del'>-	0xfa000000, 0xbf8cc07f,</div><div class='add'>+	0xfa000000, 0xbf8c0000,</div><div class='ctx'> 	0xf4051ebd, 0xfa000008,</div><div class='del'>-	0xbf8cc07f, 0x87ee6e6e,</div><div class='add'>+	0xbf8c0000, 0x87ee6e6e,</div><div class='ctx'> 	0xbf840001, 0xbe80206e,</div><div class='del'>-	0x876eff6d, 0x01ff0000,</div><div class='del'>-	0xbf850005, 0x8878ff78,</div><div class='del'>-	0x00002000, 0x80ec886c,</div><div class='del'>-	0x82ed806d, 0xbf820005,</div><div class='del'>-	0x876eff6d, 0x01000000,</div><div class='del'>-	0xbf850002, 0x806c846c,</div><div class='add'>+	0x876eff6d, 0x00ff0000,</div><div class='add'>+	0xbf850008, 0x876eff6d,</div><div class='add'>+	0x01000000, 0xbf850007,</div><div class='add'>+	0x8878ff78, 0x00002000,</div><div class='add'>+	0x80ec886c, 0x82ed806d,</div><div class='add'>+	0xbf820002, 0x806c846c,</div><div class='ctx'> 	0x826d806d, 0x876dff6d,</div><div class='ctx'> 	0x0000ffff, 0x907a8977,</div><div class='ctx'> 	0x877bff7a, 0x003f8000,</div><div class='hunk'>@@ -932,23 +933,48 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0xbf850002, 0xbeff0380,</div><div class='ctx'> 	0xbf820001, 0xbeff03c1,</div><div class='ctx'> 	0xb97b4306, 0x877bc17b,</div><div class='del'>-	0xbf840086, 0xbf8a0000,</div><div class='add'>+	0xbf840085, 0xbf8a0000,</div><div class='ctx'> 	0x877aff6d, 0x80000000,</div><div class='del'>-	0xbf840082, 0x8f7b867b,</div><div class='del'>-	0x8f7b827b, 0xbef6037b,</div><div class='del'>-	0xb9703a05, 0x80708170,</div><div class='del'>-	0xbf0d9973, 0xbf850002,</div><div class='del'>-	0x8f708970, 0xbf820001,</div><div class='del'>-	0x8f708a70, 0xb97a1e06,</div><div class='del'>-	0x8f7a8a7a, 0x80707a70,</div><div class='del'>-	0x8070ff70, 0x00000200,</div><div class='del'>-	0x8070ff70, 0x00000080,</div><div class='del'>-	0xbef603ff, 0x01000000,</div><div class='del'>-	0xd7650000, 0x000100c1,</div><div class='del'>-	0xd7660000, 0x000200c1,</div><div class='del'>-	0x16000084, 0x907c9973,</div><div class='del'>-	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbefc0380, 0xbf850033,</div><div class='add'>+	0xbf840081, 0x8f7b887b,</div><div class='add'>+	0xbef6037b, 0xb9703a05,</div><div class='add'>+	0x80708170, 0xbf0d9973,</div><div class='add'>+	0xbf850002, 0x8f708970,</div><div class='add'>+	0xbf820001, 0x8f708a70,</div><div class='add'>+	0xb97a1e06, 0x8f7a8a7a,</div><div class='add'>+	0x80707a70, 0x8070ff70,</div><div class='add'>+	0x00000200, 0x8070ff70,</div><div class='add'>+	0x00000080, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xd7650000,</div><div class='add'>+	0x000100c1, 0xd7660000,</div><div class='add'>+	0x000200c1, 0x16000084,</div><div class='add'>+	0x907c9973, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbefc0380,</div><div class='add'>+	0xbf850033, 0xb97af803,</div><div class='add'>+	0x8a7a7aff, 0x10000000,</div><div class='add'>+	0xbf85001d, 0xd8d80000,</div><div class='add'>+	0x01000000, 0xbf8c0000,</div><div class='add'>+	0xbe840380, 0xd7600000,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd7600001, 0x00000901,</div><div class='add'>+	0x80048104, 0xd7600002,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd7600003, 0x00000901,</div><div class='add'>+	0x80048104, 0xf469003a,</div><div class='add'>+	0xe0000000, 0x80709070,</div><div class='add'>+	0xbf06a004, 0xbf84ffef,</div><div class='add'>+	0x807cff7c, 0x00000080,</div><div class='add'>+	0xd5250000, 0x0001ff00,</div><div class='add'>+	0x00000080, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffe4, 0xbf820044,</div><div class='add'>+	0xbe8303ff, 0x00000080,</div><div class='add'>+	0xbf800000, 0xbf800000,</div><div class='add'>+	0xbf800000, 0xd8d80000,</div><div class='add'>+	0x01000000, 0xbf8c0000,</div><div class='add'>+	0xe0704000, 0x705d0100,</div><div class='add'>+	0x807c037c, 0x80700370,</div><div class='add'>+	0xd5250000, 0x0001ff00,</div><div class='add'>+	0x00000080, 0xbf0a7b7c,</div><div class='add'>+	0xbf85fff4, 0xbf820032,</div><div class='ctx'> 	0xb97af803, 0x8a7a7aff,</div><div class='ctx'> 	0x10000000, 0xbf85001d,</div><div class='ctx'> 	0xd8d80000, 0x01000000,</div><div class='hunk'>@@ -960,24 +986,45 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x80048104, 0xd7600003,</div><div class='ctx'> 	0x00000901, 0x80048104,</div><div class='ctx'> 	0xf469003a, 0xe0000000,</div><div class='del'>-	0x80709070, 0xbf06a004,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffef, 0x807cff7c,</div><div class='del'>-	0x00000080, 0xd5250000,</div><div class='del'>-	0x0001ff00, 0x00000080,</div><div class='add'>+	0x00000100, 0xd5250000,</div><div class='add'>+	0x0001ff00, 0x00000100,</div><div class='ctx'> 	0xbf0a7b7c, 0xbf85ffe4,</div><div class='del'>-	0xbf820044, 0xbe8303ff,</div><div class='del'>-	0x00000080, 0xbf800000,</div><div class='add'>+	0xbf820011, 0xbe8303ff,</div><div class='add'>+	0x00000100, 0xbf800000,</div><div class='ctx'> 	0xbf800000, 0xbf800000,</div><div class='ctx'> 	0xd8d80000, 0x01000000,</div><div class='ctx'> 	0xbf8c0000, 0xe0704000,</div><div class='ctx'> 	0x705d0100, 0x807c037c,</div><div class='ctx'> 	0x80700370, 0xd5250000,</div><div class='del'>-	0x0001ff00, 0x00000080,</div><div class='add'>+	0x0001ff00, 0x00000100,</div><div class='ctx'> 	0xbf0a7b7c, 0xbf85fff4,</div><div class='del'>-	0xbf820032, 0xb97af803,</div><div class='del'>-	0x8a7a7aff, 0x10000000,</div><div class='del'>-	0xbf85001d, 0xd8d80000,</div><div class='del'>-	0x01000000, 0xbf8c0000,</div><div class='add'>+	0xbefe03c1, 0x907c9973,</div><div class='add'>+	0x877c817c, 0xbf06817c,</div><div class='add'>+	0xbf850004, 0xbef003ff,</div><div class='add'>+	0x00000200, 0xbeff0380,</div><div class='add'>+	0xbf820003, 0xbef003ff,</div><div class='add'>+	0x00000400, 0xbeff03c1,</div><div class='add'>+	0xb97b3a05, 0x807b817b,</div><div class='add'>+	0x8f7b827b, 0x907c9973,</div><div class='add'>+	0x877c817c, 0xbf06817c,</div><div class='add'>+	0xbf85006b, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xbefc0384,</div><div class='add'>+	0xbf0a7b7c, 0xbf8400fa,</div><div class='add'>+	0xb97af803, 0x8a7a7aff,</div><div class='add'>+	0x10000000, 0xbf850050,</div><div class='add'>+	0x7e008700, 0x7e028701,</div><div class='add'>+	0x7e048702, 0x7e068703,</div><div class='add'>+	0xbe840380, 0xd7600000,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd7600001, 0x00000900,</div><div class='add'>+	0x80048104, 0xd7600002,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd7600003, 0x00000900,</div><div class='add'>+	0x80048104, 0xf469003a,</div><div class='add'>+	0xe0000000, 0x80709070,</div><div class='add'>+	0xbf06a004, 0xbf84ffef,</div><div class='ctx'> 	0xbe840380, 0xd7600000,</div><div class='ctx'> 	0x00000901, 0x80048104,</div><div class='ctx'> 	0xd7600001, 0x00000901,</div><div class='hunk'>@@ -986,32 +1033,39 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0xd7600003, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xf469003a,</div><div class='ctx'> 	0xe0000000, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffef,</div><div class='del'>-	0x807cff7c, 0x00000100,</div><div class='del'>-	0xd5250000, 0x0001ff00,</div><div class='del'>-	0x00000100, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffe4, 0xbf820011,</div><div class='del'>-	0xbe8303ff, 0x00000100,</div><div class='del'>-	0xbf800000, 0xbf800000,</div><div class='del'>-	0xbf800000, 0xd8d80000,</div><div class='del'>-	0x01000000, 0xbf8c0000,</div><div class='del'>-	0xe0704000, 0x705d0100,</div><div class='del'>-	0x807c037c, 0x80700370,</div><div class='del'>-	0xd5250000, 0x0001ff00,</div><div class='del'>-	0x00000100, 0xbf0a7b7c,</div><div class='del'>-	0xbf85fff4, 0xbefe03c1,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850004,</div><div class='del'>-	0xbef003ff, 0x00000200,</div><div class='del'>-	0xbeff0380, 0xbf820003,</div><div class='del'>-	0xbef003ff, 0x00000400,</div><div class='del'>-	0xbeff03c1, 0xb97b3a05,</div><div class='del'>-	0x807b817b, 0x8f7b827b,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf85006b,</div><div class='add'>+	0xbf06a004, 0xbf84ffef,</div><div class='add'>+	0xbe840380, 0xd7600000,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd7600001, 0x00000902,</div><div class='add'>+	0x80048104, 0xd7600002,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd7600003, 0x00000902,</div><div class='add'>+	0x80048104, 0xf469003a,</div><div class='add'>+	0xe0000000, 0x80709070,</div><div class='add'>+	0xbf06a004, 0xbf84ffef,</div><div class='add'>+	0xbe840380, 0xd7600000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd7600001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd7600002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd7600003, 0x00000903,</div><div class='add'>+	0x80048104, 0xf469003a,</div><div class='add'>+	0xe0000000, 0x80709070,</div><div class='add'>+	0xbf06a004, 0xbf84ffef,</div><div class='add'>+	0x807c847c, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffb1, 0xbf8200a6,</div><div class='add'>+	0x7e008700, 0x7e028701,</div><div class='add'>+	0x7e048702, 0x7e068703,</div><div class='add'>+	0xe0704000, 0x705d0000,</div><div class='add'>+	0xe0704080, 0x705d0100,</div><div class='add'>+	0xe0704100, 0x705d0200,</div><div class='add'>+	0xe0704180, 0x705d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000200, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffef, 0xbf820094,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='ctx'> 	0xbefc0384, 0xbf0a7b7c,</div><div class='del'>-	0xbf8400fa, 0xb97af803,</div><div class='add'>+	0xbf840065, 0xb97af803,</div><div class='ctx'> 	0x8a7a7aff, 0x10000000,</div><div class='ctx'> 	0xbf850050, 0x7e008700,</div><div class='ctx'> 	0x7e028701, 0x7e048702,</div><div class='hunk'>@@ -1023,7 +1077,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x80048104, 0xd7600003,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='ctx'> 	0xf469003a, 0xe0000000,</div><div class='del'>-	0x80709070, 0xbf06a004,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffef, 0xbe840380,</div><div class='ctx'> 	0xd7600000, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd7600001,</div><div class='hunk'>@@ -1032,7 +1086,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x80048104, 0xd7600003,</div><div class='ctx'> 	0x00000901, 0x80048104,</div><div class='ctx'> 	0xf469003a, 0xe0000000,</div><div class='del'>-	0x80709070, 0xbf06a004,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffef, 0xbe840380,</div><div class='ctx'> 	0xd7600000, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd7600001,</div><div class='hunk'>@@ -1041,7 +1095,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x80048104, 0xd7600003,</div><div class='ctx'> 	0x00000902, 0x80048104,</div><div class='ctx'> 	0xf469003a, 0xe0000000,</div><div class='del'>-	0x80709070, 0xbf06a004,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffef, 0xbe840380,</div><div class='ctx'> 	0xd7600000, 0x00000903,</div><div class='ctx'> 	0x80048104, 0xd7600001,</div><div class='hunk'>@@ -1050,25 +1104,24 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x80048104, 0xd7600003,</div><div class='ctx'> 	0x00000903, 0x80048104,</div><div class='ctx'> 	0xf469003a, 0xe0000000,</div><div class='del'>-	0x80709070, 0xbf06a004,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffef, 0x807c847c,</div><div class='ctx'> 	0xbf0a7b7c, 0xbf85ffb1,</div><div class='del'>-	0xbf8200a6, 0x7e008700,</div><div class='add'>+	0xbf82003b, 0x7e008700,</div><div class='ctx'> 	0x7e028701, 0x7e048702,</div><div class='ctx'> 	0x7e068703, 0xe0704000,</div><div class='del'>-	0x705d0000, 0xe0704080,</div><div class='del'>-	0x705d0100, 0xe0704100,</div><div class='del'>-	0x705d0200, 0xe0704180,</div><div class='add'>+	0x705d0000, 0xe0704100,</div><div class='add'>+	0x705d0100, 0xe0704200,</div><div class='add'>+	0x705d0200, 0xe0704300,</div><div class='ctx'> 	0x705d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000200,</div><div class='add'>+	0x8070ff70, 0x00000400,</div><div class='ctx'> 	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xbf820094, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xbefc0384,</div><div class='del'>-	0xbf0a7b7c, 0xbf840065,</div><div class='del'>-	0xb97af803, 0x8a7a7aff,</div><div class='del'>-	0x10000000, 0xbf850050,</div><div class='del'>-	0x7e008700, 0x7e028701,</div><div class='del'>-	0x7e048702, 0x7e068703,</div><div class='add'>+	0xb97b1e06, 0x877bc17b,</div><div class='add'>+	0xbf840027, 0x8f7b837b,</div><div class='add'>+	0x807b7c7b, 0xbefe03c1,</div><div class='add'>+	0xbeff0380, 0xb97af803,</div><div class='add'>+	0x8a7a7aff, 0x10000000,</div><div class='add'>+	0xbf850017, 0x7e008700,</div><div class='ctx'> 	0xbe840380, 0xd7600000,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='ctx'> 	0xd7600001, 0x00000900,</div><div class='hunk'>@@ -1078,78 +1131,25 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x80048104, 0xf469003a,</div><div class='ctx'> 	0xe0000000, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffef,</div><div class='del'>-	0xbe840380, 0xd7600000,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd7600001, 0x00000901,</div><div class='del'>-	0x80048104, 0xd7600002,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd7600003, 0x00000901,</div><div class='del'>-	0x80048104, 0xf469003a,</div><div class='del'>-	0xe0000000, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffef,</div><div class='del'>-	0xbe840380, 0xd7600000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd7600001, 0x00000902,</div><div class='del'>-	0x80048104, 0xd7600002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd7600003, 0x00000902,</div><div class='del'>-	0x80048104, 0xf469003a,</div><div class='del'>-	0xe0000000, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffef,</div><div class='del'>-	0xbe840380, 0xd7600000,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd7600001, 0x00000903,</div><div class='del'>-	0x80048104, 0xd7600002,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd7600003, 0x00000903,</div><div class='del'>-	0x80048104, 0xf469003a,</div><div class='del'>-	0xe0000000, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffef,</div><div class='del'>-	0x807c847c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffb1, 0xbf82003b,</div><div class='del'>-	0x7e008700, 0x7e028701,</div><div class='del'>-	0x7e048702, 0x7e068703,</div><div class='del'>-	0xe0704000, 0x705d0000,</div><div class='del'>-	0xe0704100, 0x705d0100,</div><div class='del'>-	0xe0704200, 0x705d0200,</div><div class='del'>-	0xe0704300, 0x705d0300,</div><div class='del'>-	0x807c847c, 0x8070ff70,</div><div class='del'>-	0x00000400, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffef, 0xb97b1e06,</div><div class='del'>-	0x877bc17b, 0xbf840027,</div><div class='del'>-	0x8f7b837b, 0x807b7c7b,</div><div class='del'>-	0xbefe03c1, 0xbeff0380,</div><div class='del'>-	0xb97af803, 0x8a7a7aff,</div><div class='del'>-	0x10000000, 0xbf850017,</div><div class='del'>-	0x7e008700, 0xbe840380,</div><div class='del'>-	0xd7600000, 0x00000900,</div><div class='del'>-	0x80048104, 0xd7600001,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd7600002, 0x00000900,</div><div class='del'>-	0x80048104, 0xd7600003,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xf469003a, 0xe0000000,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffef, 0x807c817c,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffea,</div><div class='del'>-	0xbf820008, 0x7e008700,</div><div class='del'>-	0xe0704000, 0x705d0000,</div><div class='del'>-	0x807c817c, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbf0a7b7c,</div><div class='del'>-	0xbf85fff8, 0xbf820144,</div><div class='del'>-	0xbef4037e, 0x8775ff7f,</div><div class='del'>-	0x0000ffff, 0x8875ff75,</div><div class='del'>-	0x00040000, 0xbef60380,</div><div class='del'>-	0xbef703ff, 0x10807fac,</div><div class='del'>-	0xb97202dc, 0x8f729972,</div><div class='del'>-	0x876eff7f, 0x04000000,</div><div class='del'>-	0xbf840034, 0xbefe03c1,</div><div class='del'>-	0x907c9972, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850002,</div><div class='del'>-	0xbeff0380, 0xbf820001,</div><div class='del'>-	0xbeff03c1, 0xb96f4306,</div><div class='del'>-	0x876fc16f, 0xbf840029,</div><div class='del'>-	0x8f6f866f, 0x8f6f826f,</div><div class='add'>+	0x807c817c, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffea, 0xbf820008,</div><div class='add'>+	0x7e008700, 0xe0704000,</div><div class='add'>+	0x705d0000, 0x807c817c,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbf0a7b7c, 0xbf85fff8,</div><div class='add'>+	0xbf82013f, 0xbef4037e,</div><div class='add'>+	0x8775ff7f, 0x0000ffff,</div><div class='add'>+	0x8875ff75, 0x00040000,</div><div class='add'>+	0xbef60380, 0xbef703ff,</div><div class='add'>+	0x10807fac, 0xb97202dc,</div><div class='add'>+	0x8f729972, 0x876eff7f,</div><div class='add'>+	0x04000000, 0xbf840033,</div><div class='add'>+	0xbefe03c1, 0x907c9972,</div><div class='add'>+	0x877c817c, 0xbf06817c,</div><div class='add'>+	0xbf850002, 0xbeff0380,</div><div class='add'>+	0xbf820001, 0xbeff03c1,</div><div class='add'>+	0xb96f4306, 0x876fc16f,</div><div class='add'>+	0xbf840028, 0x8f6f886f,</div><div class='ctx'> 	0xbef6036f, 0xb9783a05,</div><div class='ctx'> 	0x80788178, 0xbf0d9972,</div><div class='ctx'> 	0xbf850002, 0x8f788978,</div><div class='hunk'>@@ -1185,7 +1185,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x785d0000, 0xe0304080,</div><div class='ctx'> 	0x785d0100, 0xe0304100,</div><div class='ctx'> 	0x785d0200, 0xe0304180,</div><div class='del'>-	0x785d0300, 0xbf8c3f70,</div><div class='add'>+	0x785d0300, 0xbf8c0000,</div><div class='ctx'> 	0x7e008500, 0x7e028501,</div><div class='ctx'> 	0x7e048502, 0x7e068503,</div><div class='ctx'> 	0x807c847c, 0x8078ff78,</div><div class='hunk'>@@ -1194,7 +1194,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x6e5d0000, 0xe0304080,</div><div class='ctx'> 	0x6e5d0100, 0xe0304100,</div><div class='ctx'> 	0x6e5d0200, 0xe0304180,</div><div class='del'>-	0x6e5d0300, 0xbf8c3f70,</div><div class='add'>+	0x6e5d0300, 0xbf8c0000,</div><div class='ctx'> 	0xbf820034, 0xbef603ff,</div><div class='ctx'> 	0x01000000, 0xbeee0378,</div><div class='ctx'> 	0x8078ff78, 0x00000400,</div><div class='hunk'>@@ -1203,7 +1203,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x785d0000, 0xe0304100,</div><div class='ctx'> 	0x785d0100, 0xe0304200,</div><div class='ctx'> 	0x785d0200, 0xe0304300,</div><div class='del'>-	0x785d0300, 0xbf8c3f70,</div><div class='add'>+	0x785d0300, 0xbf8c0000,</div><div class='ctx'> 	0x7e008500, 0x7e028501,</div><div class='ctx'> 	0x7e048502, 0x7e068503,</div><div class='ctx'> 	0x807c847c, 0x8078ff78,</div><div class='hunk'>@@ -1213,7 +1213,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x8f6f836f, 0x806f7c6f,</div><div class='ctx'> 	0xbefe03c1, 0xbeff0380,</div><div class='ctx'> 	0xe0304000, 0x785d0000,</div><div class='del'>-	0xbf8c3f70, 0x7e008500,</div><div class='add'>+	0xbf8c0000, 0x7e008500,</div><div class='ctx'> 	0x807c817c, 0x8078ff78,</div><div class='ctx'> 	0x00000080, 0xbf0a6f7c,</div><div class='ctx'> 	0xbf85fff7, 0xbeff03c1,</div><div class='hunk'>@@ -1221,7 +1221,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0xe0304100, 0x6e5d0100,</div><div class='ctx'> 	0xe0304200, 0x6e5d0200,</div><div class='ctx'> 	0xe0304300, 0x6e5d0300,</div><div class='del'>-	0xbf8c3f70, 0xb9783a05,</div><div class='add'>+	0xbf8c0000, 0xb9783a05,</div><div class='ctx'> 	0x80788178, 0xbf0d9972,</div><div class='ctx'> 	0xbf850002, 0x8f788978,</div><div class='ctx'> 	0xbf820001, 0x8f788a78,</div><div class='hunk'>@@ -1232,16 +1232,16 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x01000000, 0xbefc03ff,</div><div class='ctx'> 	0x0000006c, 0x80f89078,</div><div class='ctx'> 	0xf429003a, 0xf0000000,</div><div class='del'>-	0xbf8cc07f, 0x80fc847c,</div><div class='add'>+	0xbf8c0000, 0x80fc847c,</div><div class='ctx'> 	0xbf800000, 0xbe803100,</div><div class='ctx'> 	0xbe823102, 0x80f8a078,</div><div class='ctx'> 	0xf42d003a, 0xf0000000,</div><div class='del'>-	0xbf8cc07f, 0x80fc887c,</div><div class='add'>+	0xbf8c0000, 0x80fc887c,</div><div class='ctx'> 	0xbf800000, 0xbe803100,</div><div class='ctx'> 	0xbe823102, 0xbe843104,</div><div class='ctx'> 	0xbe863106, 0x80f8c078,</div><div class='ctx'> 	0xf431003a, 0xf0000000,</div><div class='del'>-	0xbf8cc07f, 0x80fc907c,</div><div class='add'>+	0xbf8c0000, 0x80fc907c,</div><div class='ctx'> 	0xbf800000, 0xbe803100,</div><div class='ctx'> 	0xbe823102, 0xbe843104,</div><div class='ctx'> 	0xbe863106, 0xbe883108,</div><div class='hunk'>@@ -1271,15 +1271,13 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0xf4211cfa, 0xf0000000,</div><div class='ctx'> 	0x80788478, 0xf4211bba,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xbf8cc07f, 0xb9eef814,</div><div class='add'>+	0xbf8c0000, 0xb9eef814,</div><div class='ctx'> 	0xf4211bba, 0xf0000000,</div><div class='del'>-	0x80788478, 0xbf8cc07f,</div><div class='add'>+	0x80788478, 0xbf8c0000,</div><div class='ctx'> 	0xb9eef815, 0xbefc036f,</div><div class='ctx'> 	0xbefe0370, 0xbeff0371,</div><div class='del'>-	0x876f7bff, 0x000003ff,</div><div class='del'>-	0xb9ef4803, 0xb9f9f816,</div><div class='del'>-	0x876f7bff, 0xfffff800,</div><div class='del'>-	0x906f8b6f, 0xb9efa2c3,</div><div class='add'>+	0xb9f9f816, 0xb9fb4803,</div><div class='add'>+	0x907b8b7b, 0xb9fba2c3,</div><div class='ctx'> 	0xb9f3f801, 0xb96e3a05,</div><div class='ctx'> 	0x806e816e, 0xbf0d9972,</div><div class='ctx'> 	0xbf850002, 0x8f6e896e,</div><div class='hunk'>@@ -1291,7 +1289,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> 	0x0000ffff, 0xf4091c37,</div><div class='ctx'> 	0xfa000050, 0xf4091d37,</div><div class='ctx'> 	0xfa000060, 0xf4011e77,</div><div class='del'>-	0xfa000074, 0xbf8cc07f,</div><div class='add'>+	0xfa000074, 0xbf8c0000,</div><div class='ctx'> 	0x906e8977, 0x876fff6e,</div><div class='ctx'> 	0x003f8000, 0x906e8677,</div><div class='ctx'> 	0x876eff6e, 0x02000000,</div><div class='hunk'>@@ -1305,7 +1303,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_arcturus_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf8202d4,</div><div class='add'>+	0xbf820001, 0xbf8202d5,</div><div class='ctx'> 	0xb8f8f802, 0x8978ff78,</div><div class='ctx'> 	0x00020006, 0xb8fbf803,</div><div class='ctx'> 	0x866eff78, 0x00002000,</div><div class='hunk'>@@ -1422,99 +1420,37 @@ static const uint32_t cwsr_trap_arcturus_hex[] = {</div><div class='ctx'> 	0xbefe007c, 0xbefc0070,</div><div class='ctx'> 	0xc0611c7a, 0x0000007c,</div><div class='ctx'> 	0xbf8cc07f, 0x80708470,</div><div class='del'>-	0xbefc007e, 0x867aff7f,</div><div class='del'>-	0x04000000, 0xbeef0080,</div><div class='del'>-	0x876f6f7a, 0xb8f02a05,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0x8e708170, 0xb8fb1605,</div><div class='del'>-	0x807b817b, 0x8e7b847b,</div><div class='del'>-	0x8e76827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbef20174,</div><div class='del'>-	0x80747074, 0x82758075,</div><div class='del'>-	0xbefc0080, 0xbf800000,</div><div class='del'>-	0xbe802b00, 0xbe822b02,</div><div class='del'>-	0xbe842b04, 0xbe862b06,</div><div class='del'>-	0xbe882b08, 0xbe8a2b0a,</div><div class='del'>-	0xbe8c2b0c, 0xbe8e2b0e,</div><div class='del'>-	0xc06b003a, 0x00000000,</div><div class='del'>-	0xbf8cc07f, 0xc06b013a,</div><div class='del'>-	0x00000010, 0xbf8cc07f,</div><div class='del'>-	0xc06b023a, 0x00000020,</div><div class='del'>-	0xbf8cc07f, 0xc06b033a,</div><div class='del'>-	0x00000030, 0xbf8cc07f,</div><div class='del'>-	0x8074c074, 0x82758075,</div><div class='del'>-	0x807c907c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffe7, 0xbef40172,</div><div class='del'>-	0xbef00080, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xbee80080,</div><div class='del'>-	0xbee90080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0x867aff78,</div><div class='del'>-	0x00400000, 0xbf850003,</div><div class='del'>-	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf85004d,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000900,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000900,</div><div class='del'>-	0x80048104, 0xc069003a,</div><div class='del'>-	0x00000070, 0xbf8cc07f,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000901,</div><div class='del'>-	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000901,</div><div class='del'>-	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xc069003a, 0x00000070,</div><div class='del'>-	0xbf8cc07f, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='del'>-	0x80048104, 0xc069003a,</div><div class='del'>-	0x00000070, 0xbf8cc07f,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='del'>-	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='del'>-	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xc069003a, 0x00000070,</div><div class='del'>-	0xbf8cc07f, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbf820008, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xb8fb4306,</div><div class='del'>-	0x867bc17b, 0xbf840064,</div><div class='del'>-	0xbf8a0000, 0x867aff6f,</div><div class='del'>-	0x04000000, 0xbf840060,</div><div class='del'>-	0x8e7b867b, 0x8e7b827b,</div><div class='del'>-	0xbef6007b, 0xb8f02a05,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0x8e708170, 0xb8fa1605,</div><div class='del'>-	0x807a817a, 0x8e7a867a,</div><div class='del'>-	0x80707a70, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0080,</div><div class='del'>-	0xd28c0002, 0x000100c1,</div><div class='del'>-	0xd28d0003, 0x000204c1,</div><div class='add'>+	0xbefc007e, 0xbf108080,</div><div class='add'>+	0x867aff7f, 0x04000000,</div><div class='add'>+	0xbeef0080, 0x876f6f7a,</div><div class='add'>+	0xb8f02a05, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fb1605, 0x807b817b,</div><div class='add'>+	0x8e7b847b, 0x8e76827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbef20174, 0x80747074,</div><div class='add'>+	0x82758075, 0xbefc0080,</div><div class='add'>+	0xbf800000, 0xbe802b00,</div><div class='add'>+	0xbe822b02, 0xbe842b04,</div><div class='add'>+	0xbe862b06, 0xbe882b08,</div><div class='add'>+	0xbe8a2b0a, 0xbe8c2b0c,</div><div class='add'>+	0xbe8e2b0e, 0xc06b003a,</div><div class='add'>+	0x00000000, 0xbf8cc07f,</div><div class='add'>+	0xc06b013a, 0x00000010,</div><div class='add'>+	0xbf8cc07f, 0xc06b023a,</div><div class='add'>+	0x00000020, 0xbf8cc07f,</div><div class='add'>+	0xc06b033a, 0x00000030,</div><div class='add'>+	0xbf8cc07f, 0x8074c074,</div><div class='add'>+	0x82758075, 0x807c907c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffe7,</div><div class='add'>+	0xbef40172, 0xbef00080,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xbee80080, 0xbee90080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='ctx'> 	0x867aff78, 0x00400000,</div><div class='ctx'> 	0xbf850003, 0xb8faf803,</div><div class='ctx'> 	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf850030, 0x24040682,</div><div class='del'>-	0xd86e4000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xbe840080,</div><div class='add'>+	0xbf85004d, 0xbe840080,</div><div class='ctx'> 	0xd2890000, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='hunk'>@@ -1533,31 +1469,50 @@ static const uint32_t cwsr_trap_arcturus_hex[] = {</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0x680404ff,</div><div class='del'>-	0x00000200, 0xd0c9006a,</div><div class='del'>-	0x0000f702, 0xbf87ffd2,</div><div class='del'>-	0xbf820015, 0xd1060002,</div><div class='del'>-	0x00011103, 0x7e0602ff,</div><div class='del'>-	0x00000200, 0xbefc00ff,</div><div class='del'>-	0x00010000, 0xbe800077,</div><div class='del'>-	0x8677ff77, 0xff7fffff,</div><div class='del'>-	0x8777ff77, 0x00058000,</div><div class='del'>-	0xd8ec0000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xe0765000,</div><div class='del'>-	0x701d0002, 0x68040702,</div><div class='del'>-	0xd0c9006a, 0x0000f702,</div><div class='del'>-	0xbf87fff7, 0xbef70000,</div><div class='del'>-	0xbef000ff, 0x00000400,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbf820008,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='ctx'> 	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8fb2a05, 0x807b817b,</div><div class='del'>-	0x8e7b827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0084,</div><div class='del'>-	0xbf0a7b7c, 0xbf84006d,</div><div class='del'>-	0xbf11017c, 0x807bff7b,</div><div class='del'>-	0x00001000, 0x867aff78,</div><div class='add'>+	0xb8fb4306, 0x867bc17b,</div><div class='add'>+	0xbf840064, 0xbf8a0000,</div><div class='add'>+	0x867aff6f, 0x04000000,</div><div class='add'>+	0xbf840060, 0x8e7b867b,</div><div class='add'>+	0x8e7b827b, 0xbef6007b,</div><div class='add'>+	0xb8f02a05, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fa1605, 0x807a817a,</div><div class='add'>+	0x8e7a867a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0080, 0xd28c0002,</div><div class='add'>+	0x000100c1, 0xd28d0003,</div><div class='add'>+	0x000204c1, 0x867aff78,</div><div class='ctx'> 	0x00400000, 0xbf850003,</div><div class='ctx'> 	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf850051,</div><div class='add'>+	0x10000000, 0xbf850030,</div><div class='add'>+	0x24040682, 0xd86e4000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='ctx'> 	0xd2890001, 0x00000900,</div><div class='hunk'>@@ -1577,215 +1532,259 @@ static const uint32_t cwsr_trap_arcturus_hex[] = {</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0x680404ff, 0x00000200,</div><div class='add'>+	0xd0c9006a, 0x0000f702,</div><div class='add'>+	0xbf87ffd2, 0xbf820015,</div><div class='add'>+	0xd1060002, 0x00011103,</div><div class='add'>+	0x7e0602ff, 0x00000200,</div><div class='add'>+	0xbefc00ff, 0x00010000,</div><div class='add'>+	0xbe800077, 0x8677ff77,</div><div class='add'>+	0xff7fffff, 0x8777ff77,</div><div class='add'>+	0x00058000, 0xd8ec0000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='add'>+	0xe0765000, 0x701d0002,</div><div class='add'>+	0x68040702, 0xd0c9006a,</div><div class='add'>+	0x0000f702, 0xbf87fff7,</div><div class='add'>+	0xbef70000, 0xbef000ff,</div><div class='add'>+	0x00000400, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8fb2a05,</div><div class='add'>+	0x807b817b, 0x8e7b827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0084, 0xbf0a7b7c,</div><div class='add'>+	0xbf84006d, 0xbf11017c,</div><div class='add'>+	0x807bff7b, 0x00001000,</div><div class='add'>+	0x867aff78, 0x00400000,</div><div class='add'>+	0xbf850003, 0xb8faf803,</div><div class='add'>+	0x897a7aff, 0x10000000,</div><div class='add'>+	0xbf850051, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0x807c847c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffb1, 0xbf9c0000,</div><div class='del'>-	0xbf820012, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000400,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xbf9c0000, 0xbefc0080,</div><div class='del'>-	0xbf11017c, 0x867aff78,</div><div class='del'>-	0x00400000, 0xbf850003,</div><div class='del'>-	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf850059,</div><div class='del'>-	0xd3d84000, 0x18000100,</div><div class='del'>-	0xd3d84001, 0x18000101,</div><div class='del'>-	0xd3d84002, 0x18000102,</div><div class='del'>-	0xd3d84003, 0x18000103,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000900,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000900,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000901,</div><div class='add'>+	0xbf84ffee, 0x807c847c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffb1,</div><div class='add'>+	0xbf9c0000, 0xbf820012,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000400, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffef, 0xbf9c0000,</div><div class='add'>+	0xbefc0080, 0xbf11017c,</div><div class='add'>+	0x867aff78, 0x00400000,</div><div class='add'>+	0xbf850003, 0xb8faf803,</div><div class='add'>+	0x897a7aff, 0x10000000,</div><div class='add'>+	0xbf850059, 0xd3d84000,</div><div class='add'>+	0x18000100, 0xd3d84001,</div><div class='add'>+	0x18000101, 0xd3d84002,</div><div class='add'>+	0x18000102, 0xd3d84003,</div><div class='add'>+	0x18000103, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000901,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0x807c847c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffa9, 0xbf9c0000,</div><div class='del'>-	0xbf820016, 0xd3d84000,</div><div class='del'>-	0x18000100, 0xd3d84001,</div><div class='del'>-	0x18000101, 0xd3d84002,</div><div class='del'>-	0x18000102, 0xd3d84003,</div><div class='del'>-	0x18000103, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000400,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffeb,</div><div class='del'>-	0xbf9c0000, 0xbf8200e3,</div><div class='del'>-	0xbef4007e, 0x8675ff7f,</div><div class='del'>-	0x0000ffff, 0x8775ff75,</div><div class='del'>-	0x00040000, 0xbef60080,</div><div class='del'>-	0xbef700ff, 0x00807fac,</div><div class='del'>-	0x866eff7f, 0x04000000,</div><div class='del'>-	0xbf84001f, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xb8ef4306,</div><div class='del'>-	0x866fc16f, 0xbf84001a,</div><div class='del'>-	0x8e6f866f, 0x8e6f826f,</div><div class='del'>-	0xbef6006f, 0xb8f82a05,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0x8078ff78,</div><div class='del'>-	0x00000080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0080,</div><div class='del'>-	0xe0510000, 0x781d0000,</div><div class='del'>-	0xe0510100, 0x781d0000,</div><div class='del'>-	0x807cff7c, 0x00000200,</div><div class='del'>-	0x8078ff78, 0x00000200,</div><div class='del'>-	0xbf0a6f7c, 0xbf85fff6,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0x807c847c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffa9,</div><div class='add'>+	0xbf9c0000, 0xbf820016,</div><div class='add'>+	0xd3d84000, 0x18000100,</div><div class='add'>+	0xd3d84001, 0x18000101,</div><div class='add'>+	0xd3d84002, 0x18000102,</div><div class='add'>+	0xd3d84003, 0x18000103,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000400, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffeb, 0xbf9c0000,</div><div class='add'>+	0xbf8200e3, 0xbef4007e,</div><div class='add'>+	0x8675ff7f, 0x0000ffff,</div><div class='add'>+	0x8775ff75, 0x00040000,</div><div class='add'>+	0xbef60080, 0xbef700ff,</div><div class='add'>+	0x00807fac, 0x866eff7f,</div><div class='add'>+	0x04000000, 0xbf84001f,</div><div class='ctx'> 	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xb8ef4306, 0x866fc16f,</div><div class='add'>+	0xbf84001a, 0x8e6f866f,</div><div class='add'>+	0x8e6f826f, 0xbef6006f,</div><div class='add'>+	0xb8f82a05, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0x8078ff78, 0x00000080,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0xb8ef2a05, 0x806f816f,</div><div class='del'>-	0x8e6f826f, 0x806fff6f,</div><div class='del'>-	0x00008000, 0xbef80080,</div><div class='del'>-	0xbeee0078, 0x8078ff78,</div><div class='del'>-	0x00000400, 0xbefc0084,</div><div class='del'>-	0xbf11087c, 0xe0524000,</div><div class='del'>-	0x781d0000, 0xe0524100,</div><div class='del'>-	0x781d0100, 0xe0524200,</div><div class='del'>-	0x781d0200, 0xe0524300,</div><div class='del'>-	0x781d0300, 0xbf8c0f70,</div><div class='del'>-	0x7e000300, 0x7e020301,</div><div class='del'>-	0x7e040302, 0x7e060303,</div><div class='del'>-	0x807c847c, 0x8078ff78,</div><div class='del'>-	0x00000400, 0xbf0a6f7c,</div><div class='del'>-	0xbf85ffee, 0xbefc0080,</div><div class='del'>-	0xbf11087c, 0xe0524000,</div><div class='del'>-	0x781d0000, 0xe0524100,</div><div class='del'>-	0x781d0100, 0xe0524200,</div><div class='del'>-	0x781d0200, 0xe0524300,</div><div class='del'>-	0x781d0300, 0xbf8c0f70,</div><div class='del'>-	0xd3d94000, 0x18000100,</div><div class='del'>-	0xd3d94001, 0x18000101,</div><div class='del'>-	0xd3d94002, 0x18000102,</div><div class='del'>-	0xd3d94003, 0x18000103,</div><div class='del'>-	0x807c847c, 0x8078ff78,</div><div class='del'>-	0x00000400, 0xbf0a6f7c,</div><div class='del'>-	0xbf85ffea, 0xbf9c0000,</div><div class='del'>-	0xe0524000, 0x6e1d0000,</div><div class='del'>-	0xe0524100, 0x6e1d0100,</div><div class='del'>-	0xe0524200, 0x6e1d0200,</div><div class='del'>-	0xe0524300, 0x6e1d0300,</div><div class='del'>-	0xbf8c0f70, 0xb8f82a05,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0x80f8c078,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f846f, 0x8e76826f,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc006f, 0xc031003a,</div><div class='del'>-	0x00000078, 0x80f8c078,</div><div class='del'>-	0xbf8cc07f, 0x80fc907c,</div><div class='del'>-	0xbf800000, 0xbe802d00,</div><div class='del'>-	0xbe822d02, 0xbe842d04,</div><div class='del'>-	0xbe862d06, 0xbe882d08,</div><div class='del'>-	0xbe8a2d0a, 0xbe8c2d0c,</div><div class='del'>-	0xbe8e2d0e, 0xbf06807c,</div><div class='del'>-	0xbf84fff0, 0xb8f82a05,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0xbef60084,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xc0211bfa, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211b3a,</div><div class='add'>+	0xbefc0080, 0xe0510000,</div><div class='add'>+	0x781d0000, 0xe0510100,</div><div class='add'>+	0x781d0000, 0x807cff7c,</div><div class='add'>+	0x00000200, 0x8078ff78,</div><div class='add'>+	0x00000200, 0xbf0a6f7c,</div><div class='add'>+	0xbf85fff6, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xb8ef2a05,</div><div class='add'>+	0x806f816f, 0x8e6f826f,</div><div class='add'>+	0x806fff6f, 0x00008000,</div><div class='add'>+	0xbef80080, 0xbeee0078,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbefc0084, 0xbf11087c,</div><div class='add'>+	0xe0524000, 0x781d0000,</div><div class='add'>+	0xe0524100, 0x781d0100,</div><div class='add'>+	0xe0524200, 0x781d0200,</div><div class='add'>+	0xe0524300, 0x781d0300,</div><div class='add'>+	0xbf8c0f70, 0x7e000300,</div><div class='add'>+	0x7e020301, 0x7e040302,</div><div class='add'>+	0x7e060303, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffee,</div><div class='add'>+	0xbefc0080, 0xbf11087c,</div><div class='add'>+	0xe0524000, 0x781d0000,</div><div class='add'>+	0xe0524100, 0x781d0100,</div><div class='add'>+	0xe0524200, 0x781d0200,</div><div class='add'>+	0xe0524300, 0x781d0300,</div><div class='add'>+	0xbf8c0f70, 0xd3d94000,</div><div class='add'>+	0x18000100, 0xd3d94001,</div><div class='add'>+	0x18000101, 0xd3d94002,</div><div class='add'>+	0x18000102, 0xd3d94003,</div><div class='add'>+	0x18000103, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffea,</div><div class='add'>+	0xbf9c0000, 0xe0524000,</div><div class='add'>+	0x6e1d0000, 0xe0524100,</div><div class='add'>+	0x6e1d0100, 0xe0524200,</div><div class='add'>+	0x6e1d0200, 0xe0524300,</div><div class='add'>+	0x6e1d0300, 0xbf8c0f70,</div><div class='add'>+	0xb8f82a05, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0x80f8c078, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f846f,</div><div class='add'>+	0x8e76826f, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc006f,</div><div class='add'>+	0xc031003a, 0x00000078,</div><div class='add'>+	0x80f8c078, 0xbf8cc07f,</div><div class='add'>+	0x80fc907c, 0xbf800000,</div><div class='add'>+	0xbe802d00, 0xbe822d02,</div><div class='add'>+	0xbe842d04, 0xbe862d06,</div><div class='add'>+	0xbe882d08, 0xbe8a2d0a,</div><div class='add'>+	0xbe8c2d0c, 0xbe8e2d0e,</div><div class='add'>+	0xbf06807c, 0xbf84fff0,</div><div class='add'>+	0xb8f82a05, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0xbef60084, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xc0211bfa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211b7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211c3a,</div><div class='add'>+	0xc0211b3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211b7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211c7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211eba,</div><div class='add'>+	0xc0211c3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211c7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211efa, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211a3a,</div><div class='add'>+	0xc0211eba, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211efa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211a7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211cfa,</div><div class='add'>+	0xc0211a3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211a7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xbf8cc07f, 0xbefc006f,</div><div class='del'>-	0xbefe0070, 0xbeff0071,</div><div class='del'>-	0x866f7bff, 0x000003ff,</div><div class='del'>-	0xb96f4803, 0x866f7bff,</div><div class='del'>-	0xfffff800, 0x8f6f8b6f,</div><div class='del'>-	0xb96fa2c3, 0xb973f801,</div><div class='del'>-	0xb8ee2a05, 0x806e816e,</div><div class='del'>-	0x8e6e8a6e, 0x8e6e816e,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f866f, 0x806e6f6e,</div><div class='del'>-	0x806e746e, 0x826f8075,</div><div class='del'>-	0x866fff6f, 0x0000ffff,</div><div class='del'>-	0xc00b1c37, 0x00000050,</div><div class='del'>-	0xc00b1d37, 0x00000060,</div><div class='del'>-	0xc0031e77, 0x00000074,</div><div class='del'>-	0xbf8cc07f, 0x8f6e8b77,</div><div class='del'>-	0x866eff6e, 0x001f8000,</div><div class='del'>-	0xb96ef807, 0x866dff6d,</div><div class='del'>-	0x0000ffff, 0x86fe7e7e,</div><div class='del'>-	0x86ea6a6a, 0x8f6e837a,</div><div class='del'>-	0xb96ee0c2, 0xbf800002,</div><div class='del'>-	0xb97a0002, 0xbf8a0000,</div><div class='del'>-	0xbe801f6c, 0xbf9b0000,</div><div class='add'>+	0xc0211cfa, 0x00000078,</div><div class='add'>+	0x80788478, 0xbf8cc07f,</div><div class='add'>+	0xbefc006f, 0xbefe0070,</div><div class='add'>+	0xbeff0071, 0x866f7bff,</div><div class='add'>+	0x000003ff, 0xb96f4803,</div><div class='add'>+	0x866f7bff, 0xfffff800,</div><div class='add'>+	0x8f6f8b6f, 0xb96fa2c3,</div><div class='add'>+	0xb973f801, 0xb8ee2a05,</div><div class='add'>+	0x806e816e, 0x8e6e8a6e,</div><div class='add'>+	0x8e6e816e, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f866f,</div><div class='add'>+	0x806e6f6e, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x866fff6f,</div><div class='add'>+	0x0000ffff, 0xc00b1c37,</div><div class='add'>+	0x00000050, 0xc00b1d37,</div><div class='add'>+	0x00000060, 0xc0031e77,</div><div class='add'>+	0x00000074, 0xbf8cc07f,</div><div class='add'>+	0x8f6e8b77, 0x866eff6e,</div><div class='add'>+	0x001f8000, 0xb96ef807,</div><div class='add'>+	0x866dff6d, 0x0000ffff,</div><div class='add'>+	0x86fe7e7e, 0x86ea6a6a,</div><div class='add'>+	0x8f6e837a, 0xb96ee0c2,</div><div class='add'>+	0xbf800002, 0xb97a0002,</div><div class='add'>+	0xbf8a0000, 0xbe801f6c,</div><div class='add'>+	0xbf9b0000, 0x00000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_aldebaran_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf8202df,</div><div class='add'>+	0xbf820001, 0xbf8202e0,</div><div class='ctx'> 	0xb8f8f802, 0x8978ff78,</div><div class='ctx'> 	0x00020006, 0xb8fbf803,</div><div class='ctx'> 	0x866eff78, 0x00002000,</div><div class='hunk'>@@ -1902,99 +1901,37 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = {</div><div class='ctx'> 	0xbefe007c, 0xbefc0070,</div><div class='ctx'> 	0xc0611c7a, 0x0000007c,</div><div class='ctx'> 	0xbf8cc07f, 0x80708470,</div><div class='del'>-	0xbefc007e, 0x867aff7f,</div><div class='del'>-	0x04000000, 0xbeef0080,</div><div class='del'>-	0x876f6f7a, 0xb8f02985,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0x8e708170, 0xb8fb1605,</div><div class='del'>-	0x807b817b, 0x8e7b847b,</div><div class='del'>-	0x8e76827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbef20174,</div><div class='del'>-	0x80747074, 0x82758075,</div><div class='del'>-	0xbefc0080, 0xbf800000,</div><div class='del'>-	0xbe802b00, 0xbe822b02,</div><div class='del'>-	0xbe842b04, 0xbe862b06,</div><div class='del'>-	0xbe882b08, 0xbe8a2b0a,</div><div class='del'>-	0xbe8c2b0c, 0xbe8e2b0e,</div><div class='del'>-	0xc06b003a, 0x00000000,</div><div class='del'>-	0xbf8cc07f, 0xc06b013a,</div><div class='del'>-	0x00000010, 0xbf8cc07f,</div><div class='del'>-	0xc06b023a, 0x00000020,</div><div class='del'>-	0xbf8cc07f, 0xc06b033a,</div><div class='del'>-	0x00000030, 0xbf8cc07f,</div><div class='del'>-	0x8074c074, 0x82758075,</div><div class='del'>-	0x807c907c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffe7, 0xbef40172,</div><div class='del'>-	0xbef00080, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xbee80080,</div><div class='del'>-	0xbee90080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0x867aff78,</div><div class='del'>-	0x00400000, 0xbf850003,</div><div class='del'>-	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf85004d,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000900,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000900,</div><div class='del'>-	0x80048104, 0xc069003a,</div><div class='del'>-	0x00000070, 0xbf8cc07f,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000901,</div><div class='del'>-	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000901,</div><div class='del'>-	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xc069003a, 0x00000070,</div><div class='del'>-	0xbf8cc07f, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='del'>-	0x80048104, 0xc069003a,</div><div class='del'>-	0x00000070, 0xbf8cc07f,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='del'>-	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='del'>-	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xc069003a, 0x00000070,</div><div class='del'>-	0xbf8cc07f, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbf820008, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xb8fb4306,</div><div class='del'>-	0x867bc17b, 0xbf840064,</div><div class='del'>-	0xbf8a0000, 0x867aff6f,</div><div class='del'>-	0x04000000, 0xbf840060,</div><div class='del'>-	0x8e7b867b, 0x8e7b827b,</div><div class='del'>-	0xbef6007b, 0xb8f02985,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0x8e708170, 0xb8fa1605,</div><div class='del'>-	0x807a817a, 0x8e7a867a,</div><div class='del'>-	0x80707a70, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0080,</div><div class='del'>-	0xd28c0002, 0x000100c1,</div><div class='del'>-	0xd28d0003, 0x000204c1,</div><div class='add'>+	0xbefc007e, 0xbf108080,</div><div class='add'>+	0x867aff7f, 0x04000000,</div><div class='add'>+	0xbeef0080, 0x876f6f7a,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fb1605, 0x807b817b,</div><div class='add'>+	0x8e7b847b, 0x8e76827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbef20174, 0x80747074,</div><div class='add'>+	0x82758075, 0xbefc0080,</div><div class='add'>+	0xbf800000, 0xbe802b00,</div><div class='add'>+	0xbe822b02, 0xbe842b04,</div><div class='add'>+	0xbe862b06, 0xbe882b08,</div><div class='add'>+	0xbe8a2b0a, 0xbe8c2b0c,</div><div class='add'>+	0xbe8e2b0e, 0xc06b003a,</div><div class='add'>+	0x00000000, 0xbf8cc07f,</div><div class='add'>+	0xc06b013a, 0x00000010,</div><div class='add'>+	0xbf8cc07f, 0xc06b023a,</div><div class='add'>+	0x00000020, 0xbf8cc07f,</div><div class='add'>+	0xc06b033a, 0x00000030,</div><div class='add'>+	0xbf8cc07f, 0x8074c074,</div><div class='add'>+	0x82758075, 0x807c907c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffe7,</div><div class='add'>+	0xbef40172, 0xbef00080,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xbee80080, 0xbee90080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='ctx'> 	0x867aff78, 0x00400000,</div><div class='ctx'> 	0xbf850003, 0xb8faf803,</div><div class='ctx'> 	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf850030, 0x24040682,</div><div class='del'>-	0xd86e4000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xbe840080,</div><div class='add'>+	0xbf85004d, 0xbe840080,</div><div class='ctx'> 	0xd2890000, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='hunk'>@@ -2013,31 +1950,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = {</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0x680404ff,</div><div class='del'>-	0x00000200, 0xd0c9006a,</div><div class='del'>-	0x0000f702, 0xbf87ffd2,</div><div class='del'>-	0xbf820015, 0xd1060002,</div><div class='del'>-	0x00011103, 0x7e0602ff,</div><div class='del'>-	0x00000200, 0xbefc00ff,</div><div class='del'>-	0x00010000, 0xbe800077,</div><div class='del'>-	0x8677ff77, 0xff7fffff,</div><div class='del'>-	0x8777ff77, 0x00058000,</div><div class='del'>-	0xd8ec0000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xe0765000,</div><div class='del'>-	0x701d0002, 0x68040702,</div><div class='del'>-	0xd0c9006a, 0x0000f702,</div><div class='del'>-	0xbf87fff7, 0xbef70000,</div><div class='del'>-	0xbef000ff, 0x00000400,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbf820008,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='ctx'> 	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8fb2b05, 0x807b817b,</div><div class='del'>-	0x8e7b827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0084,</div><div class='del'>-	0xbf0a7b7c, 0xbf84006d,</div><div class='del'>-	0xbf11017c, 0x807bff7b,</div><div class='del'>-	0x00001000, 0x867aff78,</div><div class='add'>+	0xb8fb4306, 0x867bc17b,</div><div class='add'>+	0xbf840064, 0xbf8a0000,</div><div class='add'>+	0x867aff6f, 0x04000000,</div><div class='add'>+	0xbf840060, 0x8e7b867b,</div><div class='add'>+	0x8e7b827b, 0xbef6007b,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fa1605, 0x807a817a,</div><div class='add'>+	0x8e7a867a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0080, 0xd28c0002,</div><div class='add'>+	0x000100c1, 0xd28d0003,</div><div class='add'>+	0x000204c1, 0x867aff78,</div><div class='ctx'> 	0x00400000, 0xbf850003,</div><div class='ctx'> 	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf850051,</div><div class='add'>+	0x10000000, 0xbf850030,</div><div class='add'>+	0x24040682, 0xd86e4000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='ctx'> 	0xd2890001, 0x00000900,</div><div class='hunk'>@@ -2057,51 +2013,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = {</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='del'>-	0x80048104, 0xc069003a,</div><div class='del'>-	0x00000070, 0xbf8cc07f,</div><div class='del'>-	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='del'>-	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='del'>-	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xc069003a, 0x00000070,</div><div class='del'>-	0xbf8cc07f, 0x80709070,</div><div class='del'>-	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0x807c847c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffb1, 0xbf9c0000,</div><div class='del'>-	0xbf820012, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000400,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xbf9c0000, 0xb8fb2985,</div><div class='del'>-	0x807b817b, 0x8e7b837b,</div><div class='del'>-	0xb8fa2b05, 0x807a817a,</div><div class='del'>-	0x8e7a827a, 0x80fb7a7b,</div><div class='del'>-	0x867b7b7b, 0xbf84007a,</div><div class='add'>+	0x680404ff, 0x00000200,</div><div class='add'>+	0xd0c9006a, 0x0000f702,</div><div class='add'>+	0xbf87ffd2, 0xbf820015,</div><div class='add'>+	0xd1060002, 0x00011103,</div><div class='add'>+	0x7e0602ff, 0x00000200,</div><div class='add'>+	0xbefc00ff, 0x00010000,</div><div class='add'>+	0xbe800077, 0x8677ff77,</div><div class='add'>+	0xff7fffff, 0x8777ff77,</div><div class='add'>+	0x00058000, 0xd8ec0000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='add'>+	0xe0765000, 0x701d0002,</div><div class='add'>+	0x68040702, 0xd0c9006a,</div><div class='add'>+	0x0000f702, 0xbf87fff7,</div><div class='add'>+	0xbef70000, 0xbef000ff,</div><div class='add'>+	0x00000400, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8fb2b05,</div><div class='add'>+	0x807b817b, 0x8e7b827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0084, 0xbf0a7b7c,</div><div class='add'>+	0xbf84006d, 0xbf11017c,</div><div class='ctx'> 	0x807bff7b, 0x00001000,</div><div class='del'>-	0xbefc0080, 0xbf11017c,</div><div class='ctx'> 	0x867aff78, 0x00400000,</div><div class='ctx'> 	0xbf850003, 0xb8faf803,</div><div class='ctx'> 	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf850059, 0xd3d84000,</div><div class='del'>-	0x18000100, 0xd3d84001,</div><div class='del'>-	0x18000101, 0xd3d84002,</div><div class='del'>-	0x18000102, 0xd3d84003,</div><div class='del'>-	0x18000103, 0xbe840080,</div><div class='add'>+	0xbf850051, 0xbe840080,</div><div class='ctx'> 	0xd2890000, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='hunk'>@@ -2140,143 +2076,207 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = {</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0x807c847c,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffa9,</div><div class='del'>-	0xbf9c0000, 0xbf820016,</div><div class='del'>-	0xd3d84000, 0x18000100,</div><div class='del'>-	0xd3d84001, 0x18000101,</div><div class='del'>-	0xd3d84002, 0x18000102,</div><div class='del'>-	0xd3d84003, 0x18000103,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffb1,</div><div class='add'>+	0xbf9c0000, 0xbf820012,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='ctx'> 	0xe0724000, 0x701d0000,</div><div class='ctx'> 	0xe0724100, 0x701d0100,</div><div class='ctx'> 	0xe0724200, 0x701d0200,</div><div class='ctx'> 	0xe0724300, 0x701d0300,</div><div class='ctx'> 	0x807c847c, 0x8070ff70,</div><div class='ctx'> 	0x00000400, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffeb, 0xbf9c0000,</div><div class='del'>-	0xbf8200ee, 0xbef4007e,</div><div class='del'>-	0x8675ff7f, 0x0000ffff,</div><div class='del'>-	0x8775ff75, 0x00040000,</div><div class='del'>-	0xbef60080, 0xbef700ff,</div><div class='del'>-	0x00807fac, 0x866eff7f,</div><div class='del'>-	0x04000000, 0xbf84001f,</div><div class='add'>+	0xbf85ffef, 0xbf9c0000,</div><div class='add'>+	0xb8fb2985, 0x807b817b,</div><div class='add'>+	0x8e7b837b, 0xb8fa2b05,</div><div class='add'>+	0x807a817a, 0x8e7a827a,</div><div class='add'>+	0x80fb7a7b, 0x867b7b7b,</div><div class='add'>+	0xbf84007a, 0x807bff7b,</div><div class='add'>+	0x00001000, 0xbefc0080,</div><div class='add'>+	0xbf11017c, 0x867aff78,</div><div class='add'>+	0x00400000, 0xbf850003,</div><div class='add'>+	0xb8faf803, 0x897a7aff,</div><div class='add'>+	0x10000000, 0xbf850059,</div><div class='add'>+	0xd3d84000, 0x18000100,</div><div class='add'>+	0xd3d84001, 0x18000101,</div><div class='add'>+	0xd3d84002, 0x18000102,</div><div class='add'>+	0xd3d84003, 0x18000103,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000900,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000901,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000901,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000902,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0x807c847c, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffa9, 0xbf9c0000,</div><div class='add'>+	0xbf820016, 0xd3d84000,</div><div class='add'>+	0x18000100, 0xd3d84001,</div><div class='add'>+	0x18000101, 0xd3d84002,</div><div class='add'>+	0x18000102, 0xd3d84003,</div><div class='add'>+	0x18000103, 0xe0724000,</div><div class='add'>+	0x701d0000, 0xe0724100,</div><div class='add'>+	0x701d0100, 0xe0724200,</div><div class='add'>+	0x701d0200, 0xe0724300,</div><div class='add'>+	0x701d0300, 0x807c847c,</div><div class='add'>+	0x8070ff70, 0x00000400,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffeb,</div><div class='add'>+	0xbf9c0000, 0xbf8200ee,</div><div class='add'>+	0xbef4007e, 0x8675ff7f,</div><div class='add'>+	0x0000ffff, 0x8775ff75,</div><div class='add'>+	0x00040000, 0xbef60080,</div><div class='add'>+	0xbef700ff, 0x00807fac,</div><div class='add'>+	0x866eff7f, 0x04000000,</div><div class='add'>+	0xbf84001f, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8ef4306,</div><div class='add'>+	0x866fc16f, 0xbf84001a,</div><div class='add'>+	0x8e6f866f, 0x8e6f826f,</div><div class='add'>+	0xbef6006f, 0xb8f82985,</div><div class='add'>+	0x80788178, 0x8e788a78,</div><div class='add'>+	0x8e788178, 0xb8ee1605,</div><div class='add'>+	0x806e816e, 0x8e6e866e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc0080,</div><div class='add'>+	0xe0510000, 0x781d0000,</div><div class='add'>+	0xe0510100, 0x781d0000,</div><div class='add'>+	0x807cff7c, 0x00000200,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0xbf0a6f7c, 0xbf85fff6,</div><div class='ctx'> 	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8ef4306, 0x866fc16f,</div><div class='del'>-	0xbf84001a, 0x8e6f866f,</div><div class='del'>-	0x8e6f826f, 0xbef6006f,</div><div class='del'>-	0xb8f82985, 0x80788178,</div><div class='del'>-	0x8e788a78, 0x8e788178,</div><div class='del'>-	0xb8ee1605, 0x806e816e,</div><div class='del'>-	0x8e6e866e, 0x80786e78,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc0080, 0xe0510000,</div><div class='del'>-	0x781d0000, 0xe0510100,</div><div class='del'>-	0x781d0000, 0x807cff7c,</div><div class='del'>-	0x00000200, 0x8078ff78,</div><div class='del'>-	0x00000200, 0xbf0a6f7c,</div><div class='del'>-	0xbf85fff6, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xb8ef2b05,</div><div class='del'>-	0x806f816f, 0x8e6f826f,</div><div class='del'>-	0x806fff6f, 0x00008000,</div><div class='del'>-	0xbef80080, 0xbeee0078,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbefc0084, 0xbf11087c,</div><div class='del'>-	0xe0524000, 0x781d0000,</div><div class='del'>-	0xe0524100, 0x781d0100,</div><div class='del'>-	0xe0524200, 0x781d0200,</div><div class='del'>-	0xe0524300, 0x781d0300,</div><div class='del'>-	0xbf8c0f70, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0x807c847c,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbf0a6f7c, 0xbf85ffee,</div><div class='del'>-	0xb8ef2985, 0x806f816f,</div><div class='del'>-	0x8e6f836f, 0xb8f92b05,</div><div class='del'>-	0x80798179, 0x8e798279,</div><div class='del'>-	0x80ef796f, 0x866f6f6f,</div><div class='del'>-	0xbf84001a, 0x806fff6f,</div><div class='del'>-	0x00008000, 0xbefc0080,</div><div class='add'>+	0xb8ef2b05, 0x806f816f,</div><div class='add'>+	0x8e6f826f, 0x806fff6f,</div><div class='add'>+	0x00008000, 0xbef80080,</div><div class='add'>+	0xbeee0078, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbefc0084,</div><div class='ctx'> 	0xbf11087c, 0xe0524000,</div><div class='ctx'> 	0x781d0000, 0xe0524100,</div><div class='ctx'> 	0x781d0100, 0xe0524200,</div><div class='ctx'> 	0x781d0200, 0xe0524300,</div><div class='ctx'> 	0x781d0300, 0xbf8c0f70,</div><div class='del'>-	0xd3d94000, 0x18000100,</div><div class='del'>-	0xd3d94001, 0x18000101,</div><div class='del'>-	0xd3d94002, 0x18000102,</div><div class='del'>-	0xd3d94003, 0x18000103,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='ctx'> 	0x807c847c, 0x8078ff78,</div><div class='ctx'> 	0x00000400, 0xbf0a6f7c,</div><div class='del'>-	0xbf85ffea, 0xbf9c0000,</div><div class='del'>-	0xe0524000, 0x6e1d0000,</div><div class='del'>-	0xe0524100, 0x6e1d0100,</div><div class='del'>-	0xe0524200, 0x6e1d0200,</div><div class='del'>-	0xe0524300, 0x6e1d0300,</div><div class='del'>-	0xbf8c0f70, 0xb8f82985,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0x80f8c078,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f846f, 0x8e76826f,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc006f, 0xc031003a,</div><div class='del'>-	0x00000078, 0x80f8c078,</div><div class='del'>-	0xbf8cc07f, 0x80fc907c,</div><div class='del'>-	0xbf800000, 0xbe802d00,</div><div class='del'>-	0xbe822d02, 0xbe842d04,</div><div class='del'>-	0xbe862d06, 0xbe882d08,</div><div class='del'>-	0xbe8a2d0a, 0xbe8c2d0c,</div><div class='del'>-	0xbe8e2d0e, 0xbf06807c,</div><div class='del'>-	0xbf84fff0, 0xb8f82985,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0xbef60084,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xc0211bfa, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211b3a,</div><div class='add'>+	0xbf85ffee, 0xb8ef2985,</div><div class='add'>+	0x806f816f, 0x8e6f836f,</div><div class='add'>+	0xb8f92b05, 0x80798179,</div><div class='add'>+	0x8e798279, 0x80ef796f,</div><div class='add'>+	0x866f6f6f, 0xbf84001a,</div><div class='add'>+	0x806fff6f, 0x00008000,</div><div class='add'>+	0xbefc0080, 0xbf11087c,</div><div class='add'>+	0xe0524000, 0x781d0000,</div><div class='add'>+	0xe0524100, 0x781d0100,</div><div class='add'>+	0xe0524200, 0x781d0200,</div><div class='add'>+	0xe0524300, 0x781d0300,</div><div class='add'>+	0xbf8c0f70, 0xd3d94000,</div><div class='add'>+	0x18000100, 0xd3d94001,</div><div class='add'>+	0x18000101, 0xd3d94002,</div><div class='add'>+	0x18000102, 0xd3d94003,</div><div class='add'>+	0x18000103, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffea,</div><div class='add'>+	0xbf9c0000, 0xe0524000,</div><div class='add'>+	0x6e1d0000, 0xe0524100,</div><div class='add'>+	0x6e1d0100, 0xe0524200,</div><div class='add'>+	0x6e1d0200, 0xe0524300,</div><div class='add'>+	0x6e1d0300, 0xbf8c0f70,</div><div class='add'>+	0xb8f82985, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0x80f8c078, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f846f,</div><div class='add'>+	0x8e76826f, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc006f,</div><div class='add'>+	0xc031003a, 0x00000078,</div><div class='add'>+	0x80f8c078, 0xbf8cc07f,</div><div class='add'>+	0x80fc907c, 0xbf800000,</div><div class='add'>+	0xbe802d00, 0xbe822d02,</div><div class='add'>+	0xbe842d04, 0xbe862d06,</div><div class='add'>+	0xbe882d08, 0xbe8a2d0a,</div><div class='add'>+	0xbe8c2d0c, 0xbe8e2d0e,</div><div class='add'>+	0xbf06807c, 0xbf84fff0,</div><div class='add'>+	0xb8f82985, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0xbef60084, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xc0211bfa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211b7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211c3a,</div><div class='add'>+	0xc0211b3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211b7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211c7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211eba,</div><div class='add'>+	0xc0211c3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211c7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211efa, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211a3a,</div><div class='add'>+	0xc0211eba, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211efa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211a7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211cfa,</div><div class='add'>+	0xc0211a3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211a7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xbf8cc07f, 0xbefc006f,</div><div class='del'>-	0xbefe0070, 0xbeff0071,</div><div class='del'>-	0x866f7bff, 0x000003ff,</div><div class='del'>-	0xb96f4803, 0x866f7bff,</div><div class='del'>-	0xfffff800, 0x8f6f8b6f,</div><div class='del'>-	0xb96fa2c3, 0xb973f801,</div><div class='del'>-	0xb8ee2985, 0x806e816e,</div><div class='del'>-	0x8e6e8a6e, 0x8e6e816e,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f866f, 0x806e6f6e,</div><div class='del'>-	0x806e746e, 0x826f8075,</div><div class='del'>-	0x866fff6f, 0x0000ffff,</div><div class='del'>-	0xc00b1c37, 0x00000050,</div><div class='del'>-	0xc00b1d37, 0x00000060,</div><div class='del'>-	0xc0031e77, 0x00000074,</div><div class='del'>-	0xbf8cc07f, 0x8f6e8b77,</div><div class='del'>-	0x866eff6e, 0x001f8000,</div><div class='del'>-	0xb96ef807, 0x866dff6d,</div><div class='del'>-	0x0000ffff, 0x86fe7e7e,</div><div class='del'>-	0x86ea6a6a, 0x8f6e837a,</div><div class='del'>-	0xb96ee0c2, 0xbf800002,</div><div class='del'>-	0xb97a0002, 0xbf8a0000,</div><div class='del'>-	0xbe801f6c, 0xbf9b0000,</div><div class='add'>+	0xc0211cfa, 0x00000078,</div><div class='add'>+	0x80788478, 0xbf8cc07f,</div><div class='add'>+	0xbefc006f, 0xbefe0070,</div><div class='add'>+	0xbeff0071, 0x866f7bff,</div><div class='add'>+	0x000003ff, 0xb96f4803,</div><div class='add'>+	0x866f7bff, 0xfffff800,</div><div class='add'>+	0x8f6f8b6f, 0xb96fa2c3,</div><div class='add'>+	0xb973f801, 0xb8ee2985,</div><div class='add'>+	0x806e816e, 0x8e6e8a6e,</div><div class='add'>+	0x8e6e816e, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f866f,</div><div class='add'>+	0x806e6f6e, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x866fff6f,</div><div class='add'>+	0x0000ffff, 0xc00b1c37,</div><div class='add'>+	0x00000050, 0xc00b1d37,</div><div class='add'>+	0x00000060, 0xc0031e77,</div><div class='add'>+	0x00000074, 0xbf8cc07f,</div><div class='add'>+	0x8f6e8b77, 0x866eff6e,</div><div class='add'>+	0x001f8000, 0xb96ef807,</div><div class='add'>+	0x866dff6d, 0x0000ffff,</div><div class='add'>+	0x86fe7e7e, 0x86ea6a6a,</div><div class='add'>+	0x8f6e837a, 0xb96ee0c2,</div><div class='add'>+	0xbf800002, 0xb97a0002,</div><div class='add'>+	0xbf8a0000, 0xbe801f6c,</div><div class='add'>+	0xbf9b0000, 0x00000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf820221,</div><div class='add'>+	0xbf820001, 0xbf820220,</div><div class='ctx'> 	0xb0804004, 0xb978f802,</div><div class='ctx'> 	0x8a78ff78, 0x00020006,</div><div class='ctx'> 	0xb97bf803, 0x876eff78,</div><div class='hunk'>@@ -2302,19 +2302,19 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xbf0d8f7b, 0xbf840002,</div><div class='ctx'> 	0x887bff7b, 0xffff0000,</div><div class='ctx'> 	0xf4011bbd, 0xfa000010,</div><div class='del'>-	0xbf8cc07f, 0x8f6e976e,</div><div class='add'>+	0xbf8c0000, 0x8f6e976e,</div><div class='ctx'> 	0x8a77ff77, 0x00800000,</div><div class='ctx'> 	0x88776e77, 0xf4051bbd,</div><div class='del'>-	0xfa000000, 0xbf8cc07f,</div><div class='add'>+	0xfa000000, 0xbf8c0000,</div><div class='ctx'> 	0xf4051ebd, 0xfa000008,</div><div class='del'>-	0xbf8cc07f, 0x87ee6e6e,</div><div class='add'>+	0xbf8c0000, 0x87ee6e6e,</div><div class='ctx'> 	0xbf840001, 0xbe80206e,</div><div class='del'>-	0x876eff6d, 0x01ff0000,</div><div class='del'>-	0xbf850005, 0x8878ff78,</div><div class='del'>-	0x00002000, 0x80ec886c,</div><div class='del'>-	0x82ed806d, 0xbf820005,</div><div class='del'>-	0x876eff6d, 0x01000000,</div><div class='del'>-	0xbf850002, 0x806c846c,</div><div class='add'>+	0x876eff6d, 0x00ff0000,</div><div class='add'>+	0xbf850008, 0x876eff6d,</div><div class='add'>+	0x01000000, 0xbf850007,</div><div class='add'>+	0x8878ff78, 0x00002000,</div><div class='add'>+	0x80ec886c, 0x82ed806d,</div><div class='add'>+	0xbf820002, 0x806c846c,</div><div class='ctx'> 	0x826d806d, 0x876dff6d,</div><div class='ctx'> 	0x0000ffff, 0x87fe7e7e,</div><div class='ctx'> 	0x87ea6a6a, 0xb9f8f802,</div><div class='hunk'>@@ -2322,7 +2322,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0x0000ffff, 0xbefa0380,</div><div class='ctx'> 	0xb9fa0283, 0xbeee037e,</div><div class='ctx'> 	0xbeef037f, 0xbefe0480,</div><div class='del'>-	0xbf900004, 0xbf8cc07f,</div><div class='add'>+	0xbf900004, 0xbf8c0000,</div><div class='ctx'> 	0x877aff7f, 0x04000000,</div><div class='ctx'> 	0x8f7a857a, 0x886d7a6d,</div><div class='ctx'> 	0x7e008200, 0xbefa037e,</div><div class='hunk'>@@ -2475,94 +2475,93 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xbf850002, 0xbeff0380,</div><div class='ctx'> 	0xbf820001, 0xbeff03c1,</div><div class='ctx'> 	0xb97b4306, 0x877bc17b,</div><div class='del'>-	0xbf840044, 0xbf8a0000,</div><div class='add'>+	0xbf840043, 0xbf8a0000,</div><div class='ctx'> 	0x877aff6d, 0x80000000,</div><div class='del'>-	0xbf840040, 0x8f7b867b,</div><div class='del'>-	0x8f7b827b, 0xbef6037b,</div><div class='del'>-	0xb9703a05, 0x80708170,</div><div class='del'>-	0xbf0d9973, 0xbf850002,</div><div class='del'>-	0x8f708970, 0xbf820001,</div><div class='del'>-	0x8f708a70, 0xb97a1e06,</div><div class='del'>-	0x8f7a8a7a, 0x80707a70,</div><div class='del'>-	0x8070ff70, 0x00000200,</div><div class='del'>-	0x8070ff70, 0x00000080,</div><div class='del'>-	0xbef603ff, 0x01000000,</div><div class='del'>-	0xd7650000, 0x000100c1,</div><div class='del'>-	0xd7660000, 0x000200c1,</div><div class='del'>-	0x16000084, 0x907c9973,</div><div class='del'>-	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbefc0380, 0xbf850012,</div><div class='del'>-	0xbe8303ff, 0x00000080,</div><div class='add'>+	0xbf84003f, 0x8f7b887b,</div><div class='add'>+	0xbef6037b, 0xb9703a05,</div><div class='add'>+	0x80708170, 0xbf0d9973,</div><div class='add'>+	0xbf850002, 0x8f708970,</div><div class='add'>+	0xbf820001, 0x8f708a70,</div><div class='add'>+	0xb97a1e06, 0x8f7a8a7a,</div><div class='add'>+	0x80707a70, 0x8070ff70,</div><div class='add'>+	0x00000200, 0x8070ff70,</div><div class='add'>+	0x00000080, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xd7650000,</div><div class='add'>+	0x000100c1, 0xd7660000,</div><div class='add'>+	0x000200c1, 0x16000084,</div><div class='add'>+	0x907c9973, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbefc0380,</div><div class='add'>+	0xbf850012, 0xbe8303ff,</div><div class='add'>+	0x00000080, 0xbf800000,</div><div class='ctx'> 	0xbf800000, 0xbf800000,</div><div class='del'>-	0xbf800000, 0xd8d80000,</div><div class='del'>-	0x01000000, 0xbf8c0000,</div><div class='del'>-	0xe0704000, 0x705d0100,</div><div class='del'>-	0x807c037c, 0x80700370,</div><div class='del'>-	0xd5250000, 0x0001ff00,</div><div class='del'>-	0x00000080, 0xbf0a7b7c,</div><div class='del'>-	0xbf85fff4, 0xbf820011,</div><div class='del'>-	0xbe8303ff, 0x00000100,</div><div class='add'>+	0xd8d80000, 0x01000000,</div><div class='add'>+	0xbf8c0000, 0xe0704000,</div><div class='add'>+	0x705d0100, 0x807c037c,</div><div class='add'>+	0x80700370, 0xd5250000,</div><div class='add'>+	0x0001ff00, 0x00000080,</div><div class='add'>+	0xbf0a7b7c, 0xbf85fff4,</div><div class='add'>+	0xbf820011, 0xbe8303ff,</div><div class='add'>+	0x00000100, 0xbf800000,</div><div class='ctx'> 	0xbf800000, 0xbf800000,</div><div class='del'>-	0xbf800000, 0xd8d80000,</div><div class='del'>-	0x01000000, 0xbf8c0000,</div><div class='del'>-	0xe0704000, 0x705d0100,</div><div class='del'>-	0x807c037c, 0x80700370,</div><div class='del'>-	0xd5250000, 0x0001ff00,</div><div class='del'>-	0x00000100, 0xbf0a7b7c,</div><div class='del'>-	0xbf85fff4, 0xbefe03c1,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850004,</div><div class='del'>-	0xbef003ff, 0x00000200,</div><div class='del'>-	0xbeff0380, 0xbf820003,</div><div class='del'>-	0xbef003ff, 0x00000400,</div><div class='del'>-	0xbeff03c1, 0xb97b3a05,</div><div class='del'>-	0x807b817b, 0x8f7b827b,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850017,</div><div class='add'>+	0xd8d80000, 0x01000000,</div><div class='add'>+	0xbf8c0000, 0xe0704000,</div><div class='add'>+	0x705d0100, 0x807c037c,</div><div class='add'>+	0x80700370, 0xd5250000,</div><div class='add'>+	0x0001ff00, 0x00000100,</div><div class='add'>+	0xbf0a7b7c, 0xbf85fff4,</div><div class='add'>+	0xbefe03c1, 0x907c9973,</div><div class='add'>+	0x877c817c, 0xbf06817c,</div><div class='add'>+	0xbf850004, 0xbef003ff,</div><div class='add'>+	0x00000200, 0xbeff0380,</div><div class='add'>+	0xbf820003, 0xbef003ff,</div><div class='add'>+	0x00000400, 0xbeff03c1,</div><div class='add'>+	0xb97b3a05, 0x807b817b,</div><div class='add'>+	0x8f7b827b, 0x907c9973,</div><div class='add'>+	0x877c817c, 0xbf06817c,</div><div class='add'>+	0xbf850017, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xbefc0384,</div><div class='add'>+	0xbf0a7b7c, 0xbf840037,</div><div class='add'>+	0x7e008700, 0x7e028701,</div><div class='add'>+	0x7e048702, 0x7e068703,</div><div class='add'>+	0xe0704000, 0x705d0000,</div><div class='add'>+	0xe0704080, 0x705d0100,</div><div class='add'>+	0xe0704100, 0x705d0200,</div><div class='add'>+	0xe0704180, 0x705d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000200, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffef, 0xbf820025,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='ctx'> 	0xbefc0384, 0xbf0a7b7c,</div><div class='del'>-	0xbf840037, 0x7e008700,</div><div class='add'>+	0xbf840011, 0x7e008700,</div><div class='ctx'> 	0x7e028701, 0x7e048702,</div><div class='ctx'> 	0x7e068703, 0xe0704000,</div><div class='del'>-	0x705d0000, 0xe0704080,</div><div class='del'>-	0x705d0100, 0xe0704100,</div><div class='del'>-	0x705d0200, 0xe0704180,</div><div class='add'>+	0x705d0000, 0xe0704100,</div><div class='add'>+	0x705d0100, 0xe0704200,</div><div class='add'>+	0x705d0200, 0xe0704300,</div><div class='ctx'> 	0x705d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000200,</div><div class='add'>+	0x8070ff70, 0x00000400,</div><div class='ctx'> 	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xbf820025, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xbefc0384,</div><div class='del'>-	0xbf0a7b7c, 0xbf840011,</div><div class='del'>-	0x7e008700, 0x7e028701,</div><div class='del'>-	0x7e048702, 0x7e068703,</div><div class='add'>+	0xb97b1e06, 0x877bc17b,</div><div class='add'>+	0xbf84000c, 0x8f7b837b,</div><div class='add'>+	0x807b7c7b, 0xbefe03c1,</div><div class='add'>+	0xbeff0380, 0x7e008700,</div><div class='ctx'> 	0xe0704000, 0x705d0000,</div><div class='del'>-	0xe0704100, 0x705d0100,</div><div class='del'>-	0xe0704200, 0x705d0200,</div><div class='del'>-	0xe0704300, 0x705d0300,</div><div class='del'>-	0x807c847c, 0x8070ff70,</div><div class='del'>-	0x00000400, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffef, 0xb97b1e06,</div><div class='del'>-	0x877bc17b, 0xbf84000c,</div><div class='del'>-	0x8f7b837b, 0x807b7c7b,</div><div class='del'>-	0xbefe03c1, 0xbeff0380,</div><div class='del'>-	0x7e008700, 0xe0704000,</div><div class='del'>-	0x705d0000, 0x807c817c,</div><div class='del'>-	0x8070ff70, 0x00000080,</div><div class='del'>-	0xbf0a7b7c, 0xbf85fff8,</div><div class='del'>-	0xbf82013b, 0xbef4037e,</div><div class='del'>-	0x8775ff7f, 0x0000ffff,</div><div class='del'>-	0x8875ff75, 0x00040000,</div><div class='del'>-	0xbef60380, 0xbef703ff,</div><div class='del'>-	0x10807fac, 0xb97202dc,</div><div class='del'>-	0x8f729972, 0x876eff7f,</div><div class='del'>-	0x04000000, 0xbf840034,</div><div class='del'>-	0xbefe03c1, 0x907c9972,</div><div class='del'>-	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbf850002, 0xbeff0380,</div><div class='del'>-	0xbf820001, 0xbeff03c1,</div><div class='del'>-	0xb96f4306, 0x876fc16f,</div><div class='del'>-	0xbf840029, 0x8f6f866f,</div><div class='del'>-	0x8f6f826f, 0xbef6036f,</div><div class='add'>+	0x807c817c, 0x8070ff70,</div><div class='add'>+	0x00000080, 0xbf0a7b7c,</div><div class='add'>+	0xbf85fff8, 0xbf820136,</div><div class='add'>+	0xbef4037e, 0x8775ff7f,</div><div class='add'>+	0x0000ffff, 0x8875ff75,</div><div class='add'>+	0x00040000, 0xbef60380,</div><div class='add'>+	0xbef703ff, 0x10807fac,</div><div class='add'>+	0xb97202dc, 0x8f729972,</div><div class='add'>+	0x876eff7f, 0x04000000,</div><div class='add'>+	0xbf840033, 0xbefe03c1,</div><div class='add'>+	0x907c9972, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbf850002,</div><div class='add'>+	0xbeff0380, 0xbf820001,</div><div class='add'>+	0xbeff03c1, 0xb96f4306,</div><div class='add'>+	0x876fc16f, 0xbf840028,</div><div class='add'>+	0x8f6f886f, 0xbef6036f,</div><div class='ctx'> 	0xb9783a05, 0x80788178,</div><div class='ctx'> 	0xbf0d9972, 0xbf850002,</div><div class='ctx'> 	0x8f788978, 0xbf820001,</div><div class='hunk'>@@ -2598,7 +2597,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xe0304080, 0x785d0100,</div><div class='ctx'> 	0xe0304100, 0x785d0200,</div><div class='ctx'> 	0xe0304180, 0x785d0300,</div><div class='del'>-	0xbf8c3f70, 0x7e008500,</div><div class='add'>+	0xbf8c0000, 0x7e008500,</div><div class='ctx'> 	0x7e028501, 0x7e048502,</div><div class='ctx'> 	0x7e068503, 0x807c847c,</div><div class='ctx'> 	0x8078ff78, 0x00000200,</div><div class='hunk'>@@ -2607,7 +2606,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xe0304080, 0x6e5d0100,</div><div class='ctx'> 	0xe0304100, 0x6e5d0200,</div><div class='ctx'> 	0xe0304180, 0x6e5d0300,</div><div class='del'>-	0xbf8c3f70, 0xbf820034,</div><div class='add'>+	0xbf8c0000, 0xbf820034,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='ctx'> 	0xbeee0378, 0x8078ff78,</div><div class='ctx'> 	0x00000400, 0xbefc0384,</div><div class='hunk'>@@ -2616,7 +2615,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xe0304100, 0x785d0100,</div><div class='ctx'> 	0xe0304200, 0x785d0200,</div><div class='ctx'> 	0xe0304300, 0x785d0300,</div><div class='del'>-	0xbf8c3f70, 0x7e008500,</div><div class='add'>+	0xbf8c0000, 0x7e008500,</div><div class='ctx'> 	0x7e028501, 0x7e048502,</div><div class='ctx'> 	0x7e068503, 0x807c847c,</div><div class='ctx'> 	0x8078ff78, 0x00000400,</div><div class='hunk'>@@ -2625,7 +2624,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xbf84000e, 0x8f6f836f,</div><div class='ctx'> 	0x806f7c6f, 0xbefe03c1,</div><div class='ctx'> 	0xbeff0380, 0xe0304000,</div><div class='del'>-	0x785d0000, 0xbf8c3f70,</div><div class='add'>+	0x785d0000, 0xbf8c0000,</div><div class='ctx'> 	0x7e008500, 0x807c817c,</div><div class='ctx'> 	0x8078ff78, 0x00000080,</div><div class='ctx'> 	0xbf0a6f7c, 0xbf85fff7,</div><div class='hunk'>@@ -2633,7 +2632,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0x6e5d0000, 0xe0304100,</div><div class='ctx'> 	0x6e5d0100, 0xe0304200,</div><div class='ctx'> 	0x6e5d0200, 0xe0304300,</div><div class='del'>-	0x6e5d0300, 0xbf8c3f70,</div><div class='add'>+	0x6e5d0300, 0xbf8c0000,</div><div class='ctx'> 	0xb9783a05, 0x80788178,</div><div class='ctx'> 	0xbf0d9972, 0xbf850002,</div><div class='ctx'> 	0x8f788978, 0xbf820001,</div><div class='hunk'>@@ -2644,16 +2643,16 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='ctx'> 	0xbefc03ff, 0x0000006c,</div><div class='ctx'> 	0x80f89078, 0xf429003a,</div><div class='del'>-	0xf0000000, 0xbf8cc07f,</div><div class='add'>+	0xf0000000, 0xbf8c0000,</div><div class='ctx'> 	0x80fc847c, 0xbf800000,</div><div class='ctx'> 	0xbe803100, 0xbe823102,</div><div class='ctx'> 	0x80f8a078, 0xf42d003a,</div><div class='del'>-	0xf0000000, 0xbf8cc07f,</div><div class='add'>+	0xf0000000, 0xbf8c0000,</div><div class='ctx'> 	0x80fc887c, 0xbf800000,</div><div class='ctx'> 	0xbe803100, 0xbe823102,</div><div class='ctx'> 	0xbe843104, 0xbe863106,</div><div class='ctx'> 	0x80f8c078, 0xf431003a,</div><div class='del'>-	0xf0000000, 0xbf8cc07f,</div><div class='add'>+	0xf0000000, 0xbf8c0000,</div><div class='ctx'> 	0x80fc907c, 0xbf800000,</div><div class='ctx'> 	0xbe803100, 0xbe823102,</div><div class='ctx'> 	0xbe843104, 0xbe863106,</div><div class='hunk'>@@ -2683,15 +2682,13 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0x80788478, 0xf4211cfa,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='ctx'> 	0xf4211bba, 0xf0000000,</div><div class='del'>-	0x80788478, 0xbf8cc07f,</div><div class='add'>+	0x80788478, 0xbf8c0000,</div><div class='ctx'> 	0xb9eef814, 0xf4211bba,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xbf8cc07f, 0xb9eef815,</div><div class='add'>+	0xbf8c0000, 0xb9eef815,</div><div class='ctx'> 	0xbefc036f, 0xbefe0370,</div><div class='del'>-	0xbeff0371, 0x876f7bff,</div><div class='del'>-	0x000003ff, 0xb9ef4803,</div><div class='del'>-	0x876f7bff, 0xfffff800,</div><div class='del'>-	0x906f8b6f, 0xb9efa2c3,</div><div class='add'>+	0xbeff0371, 0xb9fb4803,</div><div class='add'>+	0x907b8b7b, 0xb9fba2c3,</div><div class='ctx'> 	0xb9f3f801, 0xb96e3a05,</div><div class='ctx'> 	0x806e816e, 0xbf0d9972,</div><div class='ctx'> 	0xbf850002, 0x8f6e896e,</div><div class='hunk'>@@ -2703,7 +2700,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0x0000ffff, 0xf4091c37,</div><div class='ctx'> 	0xfa000050, 0xf4091d37,</div><div class='ctx'> 	0xfa000060, 0xf4011e77,</div><div class='del'>-	0xfa000074, 0xbf8cc07f,</div><div class='add'>+	0xfa000074, 0xbf8c0000,</div><div class='ctx'> 	0x876dff6d, 0x0000ffff,</div><div class='ctx'> 	0x87fe7e7e, 0x87ea6a6a,</div><div class='ctx'> 	0xb9faf802, 0xbe80226c,</div><div class='hunk'>@@ -2713,7 +2710,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_gfx11_hex[] = {</div><div class='del'>-	0xbfa00001, 0xbfa00225,</div><div class='add'>+	0xbfa00001, 0xbfa00227,</div><div class='ctx'> 	0xb0804006, 0xb8f8f802,</div><div class='ctx'> 	0x9178ff78, 0x00020006,</div><div class='ctx'> 	0xb8fbf803, 0xbf0d9e6d,</div><div class='hunk'>@@ -2737,187 +2734,188 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {</div><div class='ctx'> 	0x8b6eff6e, 0x00000800,</div><div class='ctx'> 	0xbfa20003, 0x8b6eff7b,</div><div class='ctx'> 	0x00000400, 0xbfa2002a,</div><div class='del'>-	0xbefa4d82, 0xbf89fc07,</div><div class='add'>+	0xbefa4d82, 0xbf890000,</div><div class='ctx'> 	0x84fa887a, 0xbf0d8f7b,</div><div class='ctx'> 	0xbfa10002, 0x8c7bff7b,</div><div class='ctx'> 	0xffff0000, 0xf4005bbd,</div><div class='del'>-	0xf8000010, 0xbf89fc07,</div><div class='add'>+	0xf8000010, 0xbf890000,</div><div class='ctx'> 	0x846e976e, 0x9177ff77,</div><div class='ctx'> 	0x00800000, 0x8c776e77,</div><div class='ctx'> 	0xf4045bbd, 0xf8000000,</div><div class='del'>-	0xbf89fc07, 0xf4045ebd,</div><div class='del'>-	0xf8000008, 0xbf89fc07,</div><div class='add'>+	0xbf890000, 0xf4045ebd,</div><div class='add'>+	0xf8000008, 0xbf890000,</div><div class='ctx'> 	0x8bee6e6e, 0xbfa10001,</div><div class='ctx'> 	0xbe80486e, 0x8b6eff6d,</div><div class='del'>-	0x01ff0000, 0xbfa20005,</div><div class='del'>-	0x8c78ff78, 0x00002000,</div><div class='del'>-	0x80ec886c, 0x82ed806d,</div><div class='del'>-	0xbfa00005, 0x8b6eff6d,</div><div class='del'>-	0x01000000, 0xbfa20002,</div><div class='add'>+	0x00ff0000, 0xbfa20008,</div><div class='add'>+	0x8b6eff6d, 0x01000000,</div><div class='add'>+	0xbfa20007, 0x8c78ff78,</div><div class='add'>+	0x00002000, 0x80ec886c,</div><div class='add'>+	0x82ed806d, 0xbfa00002,</div><div class='ctx'> 	0x806c846c, 0x826d806d,</div><div class='ctx'> 	0x8b6dff6d, 0x0000ffff,</div><div class='ctx'> 	0x8bfe7e7e, 0x8bea6a6a,</div><div class='ctx'> 	0xb978f802, 0xbe804a6c,</div><div class='del'>-	0x8b6dff6d, 0x0000ffff,</div><div class='del'>-	0xbefa0080, 0xb97a0283,</div><div class='del'>-	0xbeee007e, 0xbeef007f,</div><div class='del'>-	0xbefe0180, 0xbefe4d84,</div><div class='del'>-	0xbf89fc07, 0x8b7aff7f,</div><div class='del'>-	0x04000000, 0x847a857a,</div><div class='del'>-	0x8c6d7a6d, 0xbefa007e,</div><div class='del'>-	0x8b7bff7f, 0x0000ffff,</div><div class='del'>-	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xdca6c000, 0x007a0000,</div><div class='del'>-	0x7e000280, 0xbefe007a,</div><div class='del'>-	0xbeff007b, 0xb8fb02dc,</div><div class='del'>-	0x847b997b, 0xb8fa3b05,</div><div class='del'>-	0x807a817a, 0xbf0d997b,</div><div class='del'>-	0xbfa20002, 0x847a897a,</div><div class='del'>-	0xbfa00001, 0x847a8a7a,</div><div class='del'>-	0xb8fb1e06, 0x847b8a7b,</div><div class='del'>-	0x807a7b7a, 0x8b7bff7f,</div><div class='del'>-	0x0000ffff, 0x807aff7a,</div><div class='del'>-	0x00000200, 0x807a7e7a,</div><div class='del'>-	0x827b807b, 0xd7610000,</div><div class='del'>-	0x00010870, 0xd7610000,</div><div class='del'>-	0x00010a71, 0xd7610000,</div><div class='del'>-	0x00010c72, 0xd7610000,</div><div class='del'>-	0x00010e73, 0xd7610000,</div><div class='del'>-	0x00011074, 0xd7610000,</div><div class='del'>-	0x00011275, 0xd7610000,</div><div class='del'>-	0x00011476, 0xd7610000,</div><div class='del'>-	0x00011677, 0xd7610000,</div><div class='del'>-	0x00011a79, 0xd7610000,</div><div class='del'>-	0x00011c7e, 0xd7610000,</div><div class='del'>-	0x00011e7f, 0xbefe00ff,</div><div class='del'>-	0x00003fff, 0xbeff0080,</div><div class='del'>-	0xdca6c040, 0x007a0000,</div><div class='del'>-	0xd760007a, 0x00011d00,</div><div class='del'>-	0xd760007b, 0x00011f00,</div><div class='add'>+	0xbf0d9878, 0xbfa10001,</div><div class='add'>+	0xbfb00000, 0x8b6dff6d,</div><div class='add'>+	0x0000ffff, 0xbefa0080,</div><div class='add'>+	0xb97a0283, 0xbeee007e,</div><div class='add'>+	0xbeef007f, 0xbefe0180,</div><div class='add'>+	0xbefe4d84, 0xbf890000,</div><div class='add'>+	0x8b7aff7f, 0x04000000,</div><div class='add'>+	0x847a857a, 0x8c6d7a6d,</div><div class='add'>+	0xbefa007e, 0x8b7bff7f,</div><div class='add'>+	0x0000ffff, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xdca6c000,</div><div class='add'>+	0x007a0000, 0x7e000280,</div><div class='ctx'> 	0xbefe007a, 0xbeff007b,</div><div class='del'>-	0xbef4007e, 0x8b75ff7f,</div><div class='del'>-	0x0000ffff, 0x8c75ff75,</div><div class='del'>-	0x00040000, 0xbef60080,</div><div class='del'>-	0xbef700ff, 0x10807fac,</div><div class='del'>-	0xbef1007d, 0xbef00080,</div><div class='del'>-	0xb8f302dc, 0x84739973,</div><div class='del'>-	0xbefe00c1, 0x857d9973,</div><div class='del'>-	0x8b7d817d, 0xbf06817d,</div><div class='del'>-	0xbfa20002, 0xbeff0080,</div><div class='del'>-	0xbfa00002, 0xbeff00c1,</div><div class='del'>-	0xbfa00009, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xe0685080,</div><div class='del'>-	0x701d0100, 0xe0685100,</div><div class='del'>-	0x701d0200, 0xe0685180,</div><div class='del'>-	0x701d0300, 0xbfa00008,</div><div class='add'>+	0xb8fb02dc, 0x847b997b,</div><div class='add'>+	0xb8fa3b05, 0x807a817a,</div><div class='add'>+	0xbf0d997b, 0xbfa20002,</div><div class='add'>+	0x847a897a, 0xbfa00001,</div><div class='add'>+	0x847a8a7a, 0xb8fb1e06,</div><div class='add'>+	0x847b8a7b, 0x807a7b7a,</div><div class='add'>+	0x8b7bff7f, 0x0000ffff,</div><div class='add'>+	0x807aff7a, 0x00000200,</div><div class='add'>+	0x807a7e7a, 0x827b807b,</div><div class='add'>+	0xd7610000, 0x00010870,</div><div class='add'>+	0xd7610000, 0x00010a71,</div><div class='add'>+	0xd7610000, 0x00010c72,</div><div class='add'>+	0xd7610000, 0x00010e73,</div><div class='add'>+	0xd7610000, 0x00011074,</div><div class='add'>+	0xd7610000, 0x00011275,</div><div class='add'>+	0xd7610000, 0x00011476,</div><div class='add'>+	0xd7610000, 0x00011677,</div><div class='add'>+	0xd7610000, 0x00011a79,</div><div class='add'>+	0xd7610000, 0x00011c7e,</div><div class='add'>+	0xd7610000, 0x00011e7f,</div><div class='add'>+	0xbefe00ff, 0x00003fff,</div><div class='add'>+	0xbeff0080, 0xdca6c040,</div><div class='add'>+	0x007a0000, 0xd760007a,</div><div class='add'>+	0x00011d00, 0xd760007b,</div><div class='add'>+	0x00011f00, 0xbefe007a,</div><div class='add'>+	0xbeff007b, 0xbef4007e,</div><div class='add'>+	0x8b75ff7f, 0x0000ffff,</div><div class='add'>+	0x8c75ff75, 0x00040000,</div><div class='add'>+	0xbef60080, 0xbef700ff,</div><div class='add'>+	0x10807fac, 0xbef1007d,</div><div class='add'>+	0xbef00080, 0xb8f302dc,</div><div class='add'>+	0x84739973, 0xbefe00c1,</div><div class='add'>+	0x857d9973, 0x8b7d817d,</div><div class='add'>+	0xbf06817d, 0xbfa20002,</div><div class='add'>+	0xbeff0080, 0xbfa00002,</div><div class='add'>+	0xbeff00c1, 0xbfa00009,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0xe0685100, 0x701d0100,</div><div class='del'>-	0xe0685200, 0x701d0200,</div><div class='del'>-	0xe0685300, 0x701d0300,</div><div class='add'>+	0xe0685080, 0x701d0100,</div><div class='add'>+	0xe0685100, 0x701d0200,</div><div class='add'>+	0xe0685180, 0x701d0300,</div><div class='add'>+	0xbfa00008, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xe0685100,</div><div class='add'>+	0x701d0100, 0xe0685200,</div><div class='add'>+	0x701d0200, 0xe0685300,</div><div class='add'>+	0x701d0300, 0xb8f03b05,</div><div class='add'>+	0x80708170, 0xbf0d9973,</div><div class='add'>+	0xbfa20002, 0x84708970,</div><div class='add'>+	0xbfa00001, 0x84708a70,</div><div class='add'>+	0xb8fa1e06, 0x847a8a7a,</div><div class='add'>+	0x80707a70, 0x8070ff70,</div><div class='add'>+	0x00000200, 0xbef600ff,</div><div class='add'>+	0x01000000, 0x7e000280,</div><div class='add'>+	0x7e020280, 0x7e040280,</div><div class='add'>+	0xbefd0080, 0xd7610002,</div><div class='add'>+	0x0000fa71, 0x807d817d,</div><div class='add'>+	0xd7610002, 0x0000fa6c,</div><div class='add'>+	0x807d817d, 0x917aff6d,</div><div class='add'>+	0x80000000, 0xd7610002,</div><div class='add'>+	0x0000fa7a, 0x807d817d,</div><div class='add'>+	0xd7610002, 0x0000fa6e,</div><div class='add'>+	0x807d817d, 0xd7610002,</div><div class='add'>+	0x0000fa6f, 0x807d817d,</div><div class='add'>+	0xd7610002, 0x0000fa78,</div><div class='add'>+	0x807d817d, 0xb8faf803,</div><div class='add'>+	0xd7610002, 0x0000fa7a,</div><div class='add'>+	0x807d817d, 0xd7610002,</div><div class='add'>+	0x0000fa7b, 0x807d817d,</div><div class='add'>+	0xb8f1f801, 0xd7610002,</div><div class='add'>+	0x0000fa71, 0x807d817d,</div><div class='add'>+	0xb8f1f814, 0xd7610002,</div><div class='add'>+	0x0000fa71, 0x807d817d,</div><div class='add'>+	0xb8f1f815, 0xd7610002,</div><div class='add'>+	0x0000fa71, 0x807d817d,</div><div class='add'>+	0xbefe00ff, 0x0000ffff,</div><div class='add'>+	0xbeff0080, 0xe0685000,</div><div class='add'>+	0x701d0200, 0xbefe00c1,</div><div class='ctx'> 	0xb8f03b05, 0x80708170,</div><div class='ctx'> 	0xbf0d9973, 0xbfa20002,</div><div class='ctx'> 	0x84708970, 0xbfa00001,</div><div class='ctx'> 	0x84708a70, 0xb8fa1e06,</div><div class='ctx'> 	0x847a8a7a, 0x80707a70,</div><div class='del'>-	0x8070ff70, 0x00000200,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0x7e000280, 0x7e020280,</div><div class='del'>-	0x7e040280, 0xbefd0080,</div><div class='del'>-	0xd7610002, 0x0000fa71,</div><div class='del'>-	0x807d817d, 0xd7610002,</div><div class='del'>-	0x0000fa6c, 0x807d817d,</div><div class='del'>-	0x917aff6d, 0x80000000,</div><div class='del'>-	0xd7610002, 0x0000fa7a,</div><div class='del'>-	0x807d817d, 0xd7610002,</div><div class='del'>-	0x0000fa6e, 0x807d817d,</div><div class='del'>-	0xd7610002, 0x0000fa6f,</div><div class='del'>-	0x807d817d, 0xd7610002,</div><div class='del'>-	0x0000fa78, 0x807d817d,</div><div class='del'>-	0xb8faf803, 0xd7610002,</div><div class='del'>-	0x0000fa7a, 0x807d817d,</div><div class='del'>-	0xd7610002, 0x0000fa7b,</div><div class='del'>-	0x807d817d, 0xb8f1f801,</div><div class='del'>-	0xd7610002, 0x0000fa71,</div><div class='del'>-	0x807d817d, 0xb8f1f814,</div><div class='del'>-	0xd7610002, 0x0000fa71,</div><div class='del'>-	0x807d817d, 0xb8f1f815,</div><div class='del'>-	0xd7610002, 0x0000fa71,</div><div class='del'>-	0x807d817d, 0xbefe00ff,</div><div class='del'>-	0x0000ffff, 0xbeff0080,</div><div class='del'>-	0xe0685000, 0x701d0200,</div><div class='del'>-	0xbefe00c1, 0xb8f03b05,</div><div class='del'>-	0x80708170, 0xbf0d9973,</div><div class='del'>-	0xbfa20002, 0x84708970,</div><div class='del'>-	0xbfa00001, 0x84708a70,</div><div class='del'>-	0xb8fa1e06, 0x847a8a7a,</div><div class='del'>-	0x80707a70, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbef90080,</div><div class='del'>-	0xbefd0080, 0xbf800000,</div><div class='del'>-	0xbe804100, 0xbe824102,</div><div class='del'>-	0xbe844104, 0xbe864106,</div><div class='del'>-	0xbe884108, 0xbe8a410a,</div><div class='del'>-	0xbe8c410c, 0xbe8e410e,</div><div class='del'>-	0xd7610002, 0x0000f200,</div><div class='add'>+	0xbef90080, 0xbefd0080,</div><div class='add'>+	0xbf800000, 0xbe804100,</div><div class='add'>+	0xbe824102, 0xbe844104,</div><div class='add'>+	0xbe864106, 0xbe884108,</div><div class='add'>+	0xbe8a410a, 0xbe8c410c,</div><div class='add'>+	0xbe8e410e, 0xd7610002,</div><div class='add'>+	0x0000f200, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f201,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f201, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f202,</div><div class='add'>+	0x0000f202, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f203,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f203, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f204,</div><div class='add'>+	0x0000f204, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f205,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f205, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f206,</div><div class='add'>+	0x0000f206, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f207,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f207, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f208,</div><div class='add'>+	0x0000f208, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f209,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f209, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20a,</div><div class='add'>+	0x0000f20a, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20b,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20b, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20c,</div><div class='add'>+	0x0000f20c, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20d,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20d, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20e,</div><div class='add'>+	0x0000f20e, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20f,</div><div class='add'>+	0x80798179, 0xbf06a079,</div><div class='add'>+	0xbfa10006, 0xe0685000,</div><div class='add'>+	0x701d0200, 0x8070ff70,</div><div class='add'>+	0x00000080, 0xbef90080,</div><div class='add'>+	0x7e040280, 0x807d907d,</div><div class='add'>+	0xbf0aff7d, 0x00000060,</div><div class='add'>+	0xbfa2ffbc, 0xbe804100,</div><div class='add'>+	0xbe824102, 0xbe844104,</div><div class='add'>+	0xbe864106, 0xbe884108,</div><div class='add'>+	0xbe8a410a, 0xd7610002,</div><div class='add'>+	0x0000f200, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f201,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20f, 0x80798179,</div><div class='del'>-	0xbf06a079, 0xbfa10006,</div><div class='del'>-	0xe0685000, 0x701d0200,</div><div class='del'>-	0x8070ff70, 0x00000080,</div><div class='del'>-	0xbef90080, 0x7e040280,</div><div class='del'>-	0x807d907d, 0xbf0aff7d,</div><div class='del'>-	0x00000060, 0xbfa2ffbc,</div><div class='del'>-	0xbe804100, 0xbe824102,</div><div class='del'>-	0xbe844104, 0xbe864106,</div><div class='del'>-	0xbe884108, 0xbe8a410a,</div><div class='del'>-	0xd7610002, 0x0000f200,</div><div class='add'>+	0x0000f202, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f203,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f201, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f202,</div><div class='add'>+	0x0000f204, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f205,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f203, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f204,</div><div class='add'>+	0x0000f206, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f207,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f205, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f206,</div><div class='add'>+	0x0000f208, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f209,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f207, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f208,</div><div class='del'>-	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f209, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20a,</div><div class='del'>-	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20b, 0x80798179,</div><div class='del'>-	0xe0685000, 0x701d0200,</div><div class='del'>-	0xbefe00c1, 0x857d9973,</div><div class='del'>-	0x8b7d817d, 0xbf06817d,</div><div class='del'>-	0xbfa20002, 0xbeff0080,</div><div class='del'>-	0xbfa00001, 0xbeff00c1,</div><div class='del'>-	0xb8fb4306, 0x8b7bc17b,</div><div class='del'>-	0xbfa10044, 0xbfbd0000,</div><div class='del'>-	0x8b7aff6d, 0x80000000,</div><div class='del'>-	0xbfa10040, 0x847b867b,</div><div class='del'>-	0x847b827b, 0xbef6007b,</div><div class='add'>+	0x0000f20a, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20b,</div><div class='add'>+	0x80798179, 0xe0685000,</div><div class='add'>+	0x701d0200, 0xbefe00c1,</div><div class='add'>+	0x857d9973, 0x8b7d817d,</div><div class='add'>+	0xbf06817d, 0xbfa20002,</div><div class='add'>+	0xbeff0080, 0xbfa00001,</div><div class='add'>+	0xbeff00c1, 0xb8fb4306,</div><div class='add'>+	0x8b7bc17b, 0xbfa10043,</div><div class='add'>+	0xbfbd0000, 0x8b7aff6d,</div><div class='add'>+	0x80000000, 0xbfa1003f,</div><div class='add'>+	0x847b887b, 0xbef6007b,</div><div class='ctx'> 	0xb8f03b05, 0x80708170,</div><div class='ctx'> 	0xbf0d9973, 0xbfa20002,</div><div class='ctx'> 	0x84708970, 0xbfa00001,</div><div class='hunk'>@@ -2988,177 +2986,175 @@ static const uint32_t cwsr_trap_gfx11_hex[] = {</div><div class='ctx'> 	0x701d0000, 0x807d817d,</div><div class='ctx'> 	0x8070ff70, 0x00000080,</div><div class='ctx'> 	0xbf0a7b7d, 0xbfa2fff8,</div><div class='del'>-	0xbfa00146, 0xbef4007e,</div><div class='add'>+	0xbfa00143, 0xbef4007e,</div><div class='ctx'> 	0x8b75ff7f, 0x0000ffff,</div><div class='ctx'> 	0x8c75ff75, 0x00040000,</div><div class='ctx'> 	0xbef60080, 0xbef700ff,</div><div class='ctx'> 	0x10807fac, 0xb8f202dc,</div><div class='ctx'> 	0x84729972, 0x8b6eff7f,</div><div class='del'>-	0x04000000, 0xbfa1003a,</div><div class='add'>+	0x04000000, 0xbfa10039,</div><div class='ctx'> 	0xbefe00c1, 0x857d9972,</div><div class='ctx'> 	0x8b7d817d, 0xbf06817d,</div><div class='ctx'> 	0xbfa20002, 0xbeff0080,</div><div class='ctx'> 	0xbfa00001, 0xbeff00c1,</div><div class='ctx'> 	0xb8ef4306, 0x8b6fc16f,</div><div class='del'>-	0xbfa1002f, 0x846f866f,</div><div class='del'>-	0x846f826f, 0xbef6006f,</div><div class='del'>-	0xb8f83b05, 0x80788178,</div><div class='del'>-	0xbf0d9972, 0xbfa20002,</div><div class='del'>-	0x84788978, 0xbfa00001,</div><div class='del'>-	0x84788a78, 0xb8ee1e06,</div><div class='del'>-	0x846e8a6e, 0x80786e78,</div><div class='add'>+	0xbfa1002e, 0x846f886f,</div><div class='add'>+	0xbef6006f, 0xb8f83b05,</div><div class='add'>+	0x80788178, 0xbf0d9972,</div><div class='add'>+	0xbfa20002, 0x84788978,</div><div class='add'>+	0xbfa00001, 0x84788a78,</div><div class='add'>+	0xb8ee1e06, 0x846e8a6e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000200, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbefd0080, 0xbfa2000c,</div><div class='add'>+	0xe0500000, 0x781d0000,</div><div class='add'>+	0xbf890000, 0xdac00000,</div><div class='add'>+	0x00000000, 0x807dff7d,</div><div class='add'>+	0x00000080, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2fff5, 0xbfa0000b,</div><div class='add'>+	0xe0500000, 0x781d0000,</div><div class='add'>+	0xbf890000, 0xdac00000,</div><div class='add'>+	0x00000000, 0x807dff7d,</div><div class='add'>+	0x00000100, 0x8078ff78,</div><div class='add'>+	0x00000100, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2fff5, 0xbef80080,</div><div class='add'>+	0xbefe00c1, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbfa20002, 0xbeff0080,</div><div class='add'>+	0xbfa00001, 0xbeff00c1,</div><div class='add'>+	0xb8ef3b05, 0x806f816f,</div><div class='add'>+	0x846f826f, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbfa20024, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbeee0078,</div><div class='ctx'> 	0x8078ff78, 0x00000200,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0x857d9972, 0x8b7d817d,</div><div class='del'>-	0xbf06817d, 0xbefd0080,</div><div class='del'>-	0xbfa2000c, 0xe0500000,</div><div class='del'>-	0x781d0000, 0xbf8903f7,</div><div class='del'>-	0xdac00000, 0x00000000,</div><div class='del'>-	0x807dff7d, 0x00000080,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='del'>-	0xbf0a6f7d, 0xbfa2fff5,</div><div class='del'>-	0xbfa0000b, 0xe0500000,</div><div class='del'>-	0x781d0000, 0xbf8903f7,</div><div class='del'>-	0xdac00000, 0x00000000,</div><div class='del'>-	0x807dff7d, 0x00000100,</div><div class='del'>-	0x8078ff78, 0x00000100,</div><div class='del'>-	0xbf0a6f7d, 0xbfa2fff5,</div><div class='del'>-	0xbef80080, 0xbefe00c1,</div><div class='del'>-	0x857d9972, 0x8b7d817d,</div><div class='del'>-	0xbf06817d, 0xbfa20002,</div><div class='del'>-	0xbeff0080, 0xbfa00001,</div><div class='del'>-	0xbeff00c1, 0xb8ef3b05,</div><div class='del'>-	0x806f816f, 0x846f826f,</div><div class='del'>-	0x857d9972, 0x8b7d817d,</div><div class='del'>-	0xbf06817d, 0xbfa20024,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbeee0078, 0x8078ff78,</div><div class='del'>-	0x00000200, 0xbefd0084,</div><div class='del'>-	0xbf0a6f7d, 0xbfa10050,</div><div class='add'>+	0xbefd0084, 0xbf0a6f7d,</div><div class='add'>+	0xbfa10050, 0xe0505000,</div><div class='add'>+	0x781d0000, 0xe0505080,</div><div class='add'>+	0x781d0100, 0xe0505100,</div><div class='add'>+	0x781d0200, 0xe0505180,</div><div class='add'>+	0x781d0300, 0xbf890000,</div><div class='add'>+	0x7e008500, 0x7e028501,</div><div class='add'>+	0x7e048502, 0x7e068503,</div><div class='add'>+	0x807d847d, 0x8078ff78,</div><div class='add'>+	0x00000200, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2ffee, 0xe0505000,</div><div class='add'>+	0x6e1d0000, 0xe0505080,</div><div class='add'>+	0x6e1d0100, 0xe0505100,</div><div class='add'>+	0x6e1d0200, 0xe0505180,</div><div class='add'>+	0x6e1d0300, 0xbf890000,</div><div class='add'>+	0xbfa00034, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbeee0078,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbefd0084, 0xbf0a6f7d,</div><div class='add'>+	0xbfa10012, 0xe0505000,</div><div class='add'>+	0x781d0000, 0xe0505100,</div><div class='add'>+	0x781d0100, 0xe0505200,</div><div class='add'>+	0x781d0200, 0xe0505300,</div><div class='add'>+	0x781d0300, 0xbf890000,</div><div class='add'>+	0x7e008500, 0x7e028501,</div><div class='add'>+	0x7e048502, 0x7e068503,</div><div class='add'>+	0x807d847d, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2ffee, 0xb8ef1e06,</div><div class='add'>+	0x8b6fc16f, 0xbfa1000e,</div><div class='add'>+	0x846f836f, 0x806f7d6f,</div><div class='add'>+	0xbefe00c1, 0xbeff0080,</div><div class='ctx'> 	0xe0505000, 0x781d0000,</div><div class='del'>-	0xe0505080, 0x781d0100,</div><div class='del'>-	0xe0505100, 0x781d0200,</div><div class='del'>-	0xe0505180, 0x781d0300,</div><div class='del'>-	0xbf8903f7, 0x7e008500,</div><div class='del'>-	0x7e028501, 0x7e048502,</div><div class='del'>-	0x7e068503, 0x807d847d,</div><div class='del'>-	0x8078ff78, 0x00000200,</div><div class='del'>-	0xbf0a6f7d, 0xbfa2ffee,</div><div class='add'>+	0xbf890000, 0x7e008500,</div><div class='add'>+	0x807d817d, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2fff7, 0xbeff00c1,</div><div class='ctx'> 	0xe0505000, 0x6e1d0000,</div><div class='del'>-	0xe0505080, 0x6e1d0100,</div><div class='del'>-	0xe0505100, 0x6e1d0200,</div><div class='del'>-	0xe0505180, 0x6e1d0300,</div><div class='del'>-	0xbf8903f7, 0xbfa00034,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbeee0078, 0x8078ff78,</div><div class='del'>-	0x00000400, 0xbefd0084,</div><div class='del'>-	0xbf0a6f7d, 0xbfa10012,</div><div class='del'>-	0xe0505000, 0x781d0000,</div><div class='del'>-	0xe0505100, 0x781d0100,</div><div class='del'>-	0xe0505200, 0x781d0200,</div><div class='del'>-	0xe0505300, 0x781d0300,</div><div class='del'>-	0xbf8903f7, 0x7e008500,</div><div class='del'>-	0x7e028501, 0x7e048502,</div><div class='del'>-	0x7e068503, 0x807d847d,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbf0a6f7d, 0xbfa2ffee,</div><div class='del'>-	0xb8ef1e06, 0x8b6fc16f,</div><div class='del'>-	0xbfa1000e, 0x846f836f,</div><div class='del'>-	0x806f7d6f, 0xbefe00c1,</div><div class='del'>-	0xbeff0080, 0xe0505000,</div><div class='del'>-	0x781d0000, 0xbf8903f7,</div><div class='del'>-	0x7e008500, 0x807d817d,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='del'>-	0xbf0a6f7d, 0xbfa2fff7,</div><div class='del'>-	0xbeff00c1, 0xe0505000,</div><div class='del'>-	0x6e1d0000, 0xe0505100,</div><div class='del'>-	0x6e1d0100, 0xe0505200,</div><div class='del'>-	0x6e1d0200, 0xe0505300,</div><div class='del'>-	0x6e1d0300, 0xbf8903f7,</div><div class='add'>+	0xe0505100, 0x6e1d0100,</div><div class='add'>+	0xe0505200, 0x6e1d0200,</div><div class='add'>+	0xe0505300, 0x6e1d0300,</div><div class='add'>+	0xbf890000, 0xb8f83b05,</div><div class='add'>+	0x80788178, 0xbf0d9972,</div><div class='add'>+	0xbfa20002, 0x84788978,</div><div class='add'>+	0xbfa00001, 0x84788a78,</div><div class='add'>+	0xb8ee1e06, 0x846e8a6e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000200, 0x80f8ff78,</div><div class='add'>+	0x00000050, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefd00ff,</div><div class='add'>+	0x0000006c, 0x80f89078,</div><div class='add'>+	0xf428403a, 0xf0000000,</div><div class='add'>+	0xbf890000, 0x80fd847d,</div><div class='add'>+	0xbf800000, 0xbe804300,</div><div class='add'>+	0xbe824302, 0x80f8a078,</div><div class='add'>+	0xf42c403a, 0xf0000000,</div><div class='add'>+	0xbf890000, 0x80fd887d,</div><div class='add'>+	0xbf800000, 0xbe804300,</div><div class='add'>+	0xbe824302, 0xbe844304,</div><div class='add'>+	0xbe864306, 0x80f8c078,</div><div class='add'>+	0xf430403a, 0xf0000000,</div><div class='add'>+	0xbf890000, 0x80fd907d,</div><div class='add'>+	0xbf800000, 0xbe804300,</div><div class='add'>+	0xbe824302, 0xbe844304,</div><div class='add'>+	0xbe864306, 0xbe884308,</div><div class='add'>+	0xbe8a430a, 0xbe8c430c,</div><div class='add'>+	0xbe8e430e, 0xbf06807d,</div><div class='add'>+	0xbfa1fff0, 0xb980f801,</div><div class='add'>+	0x00000000, 0xbfbd0000,</div><div class='ctx'> 	0xb8f83b05, 0x80788178,</div><div class='ctx'> 	0xbf0d9972, 0xbfa20002,</div><div class='ctx'> 	0x84788978, 0xbfa00001,</div><div class='ctx'> 	0x84788a78, 0xb8ee1e06,</div><div class='ctx'> 	0x846e8a6e, 0x80786e78,</div><div class='ctx'> 	0x8078ff78, 0x00000200,</div><div class='del'>-	0x80f8ff78, 0x00000050,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefd00ff, 0x0000006c,</div><div class='del'>-	0x80f89078, 0xf428403a,</div><div class='del'>-	0xf0000000, 0xbf89fc07,</div><div class='del'>-	0x80fd847d, 0xbf800000,</div><div class='del'>-	0xbe804300, 0xbe824302,</div><div class='del'>-	0x80f8a078, 0xf42c403a,</div><div class='del'>-	0xf0000000, 0xbf89fc07,</div><div class='del'>-	0x80fd887d, 0xbf800000,</div><div class='del'>-	0xbe804300, 0xbe824302,</div><div class='del'>-	0xbe844304, 0xbe864306,</div><div class='del'>-	0x80f8c078, 0xf430403a,</div><div class='del'>-	0xf0000000, 0xbf89fc07,</div><div class='del'>-	0x80fd907d, 0xbf800000,</div><div class='del'>-	0xbe804300, 0xbe824302,</div><div class='del'>-	0xbe844304, 0xbe864306,</div><div class='del'>-	0xbe884308, 0xbe8a430a,</div><div class='del'>-	0xbe8c430c, 0xbe8e430e,</div><div class='del'>-	0xbf06807d, 0xbfa1fff0,</div><div class='del'>-	0xb980f801, 0x00000000,</div><div class='del'>-	0xbfbd0000, 0xb8f83b05,</div><div class='del'>-	0x80788178, 0xbf0d9972,</div><div class='del'>-	0xbfa20002, 0x84788978,</div><div class='del'>-	0xbfa00001, 0x84788a78,</div><div class='del'>-	0xb8ee1e06, 0x846e8a6e,</div><div class='del'>-	0x80786e78, 0x8078ff78,</div><div class='del'>-	0x00000200, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xf4205bfa,</div><div class='add'>+	0xf4205bfa, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4205b3a,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4205b3a, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4205b7a,</div><div class='add'>+	0xf4205b7a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4205c3a,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4205c3a, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4205c7a,</div><div class='add'>+	0xf4205c7a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4205eba,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4205eba, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4205efa,</div><div class='add'>+	0xf4205efa, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4205e7a,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4205e7a, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4205cfa,</div><div class='add'>+	0xf4205cfa, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4205bba,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='add'>+	0xbf890000, 0xb96ef814,</div><div class='ctx'> 	0xf4205bba, 0xf0000000,</div><div class='del'>-	0x80788478, 0xbf89fc07,</div><div class='del'>-	0xb96ef814, 0xf4205bba,</div><div class='del'>-	0xf0000000, 0x80788478,</div><div class='del'>-	0xbf89fc07, 0xb96ef815,</div><div class='del'>-	0xbefd006f, 0xbefe0070,</div><div class='del'>-	0xbeff0071, 0x8b6f7bff,</div><div class='del'>-	0x000003ff, 0xb96f4803,</div><div class='del'>-	0x8b6f7bff, 0xfffff800,</div><div class='del'>-	0x856f8b6f, 0xb96fa2c3,</div><div class='del'>-	0xb973f801, 0xb8ee3b05,</div><div class='del'>-	0x806e816e, 0xbf0d9972,</div><div class='del'>-	0xbfa20002, 0x846e896e,</div><div class='del'>-	0xbfa00001, 0x846e8a6e,</div><div class='del'>-	0xb8ef1e06, 0x846f8a6f,</div><div class='del'>-	0x806e6f6e, 0x806eff6e,</div><div class='del'>-	0x00000200, 0x806e746e,</div><div class='del'>-	0x826f8075, 0x8b6fff6f,</div><div class='del'>-	0x0000ffff, 0xf4085c37,</div><div class='del'>-	0xf8000050, 0xf4085d37,</div><div class='del'>-	0xf8000060, 0xf4005e77,</div><div class='del'>-	0xf8000074, 0xbf89fc07,</div><div class='del'>-	0x8b6dff6d, 0x0000ffff,</div><div class='del'>-	0x8bfe7e7e, 0x8bea6a6a,</div><div class='del'>-	0xb8eef802, 0xbf0d866e,</div><div class='del'>-	0xbfa20002, 0xb97af802,</div><div class='del'>-	0xbe80486c, 0xb97af802,</div><div class='del'>-	0xbe804a6c, 0xbfb10000,</div><div class='add'>+	0x80788478, 0xbf890000,</div><div class='add'>+	0xb96ef815, 0xbefd006f,</div><div class='add'>+	0xbefe0070, 0xbeff0071,</div><div class='add'>+	0xb97b4803, 0x857b8b7b,</div><div class='add'>+	0xb97b22c3, 0x857b867b,</div><div class='add'>+	0xb97b7443, 0xb973f801,</div><div class='add'>+	0xb8ee3b05, 0x806e816e,</div><div class='add'>+	0xbf0d9972, 0xbfa20002,</div><div class='add'>+	0x846e896e, 0xbfa00001,</div><div class='add'>+	0x846e8a6e, 0xb8ef1e06,</div><div class='add'>+	0x846f8a6f, 0x806e6f6e,</div><div class='add'>+	0x806eff6e, 0x00000200,</div><div class='add'>+	0x806e746e, 0x826f8075,</div><div class='add'>+	0x8b6fff6f, 0x0000ffff,</div><div class='add'>+	0xf4085c37, 0xf8000050,</div><div class='add'>+	0xf4085d37, 0xf8000060,</div><div class='add'>+	0xf4005e77, 0xf8000074,</div><div class='add'>+	0xbf890000, 0x8b6dff6d,</div><div class='add'>+	0x0000ffff, 0x8bfe7e7e,</div><div class='add'>+	0x8bea6a6a, 0xb8eef802,</div><div class='add'>+	0xbf0d866e, 0xbfa20002,</div><div class='add'>+	0xb97af802, 0xbe80486c,</div><div class='add'>+	0xb97af802, 0xbe804a6c,</div><div class='add'>+	0xbfb10000, 0xbf9f0000,</div><div class='ctx'> 	0xbf9f0000, 0xbf9f0000,</div><div class='ctx'> 	0xbf9f0000, 0xbf9f0000,</div><div class='del'>-	0xbf9f0000, 0x00000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf8202db,</div><div class='add'>+	0xbf820001, 0xbf8202dc,</div><div class='ctx'> 	0xb8f8f802, 0x8978ff78,</div><div class='ctx'> 	0x00020006, 0xb8fbf803,</div><div class='ctx'> 	0x866eff78, 0x00002000,</div><div class='hunk'>@@ -3273,99 +3269,143 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {</div><div class='ctx'> 	0xbefe007c, 0xbefc0070,</div><div class='ctx'> 	0xc0611c7a, 0x0000007c,</div><div class='ctx'> 	0xbf8cc07f, 0x80708470,</div><div class='del'>-	0xbefc007e, 0x867aff7f,</div><div class='del'>-	0x04000000, 0xbeef0080,</div><div class='del'>-	0x876f6f7a, 0xb8f02985,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0x8e708170, 0xb8fb1605,</div><div class='del'>-	0x807b817b, 0x8e7b847b,</div><div class='del'>-	0x8e76827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbef20174,</div><div class='del'>-	0x80747074, 0x82758075,</div><div class='del'>-	0xbefc0080, 0xbf800000,</div><div class='del'>-	0xbe802b00, 0xbe822b02,</div><div class='del'>-	0xbe842b04, 0xbe862b06,</div><div class='del'>-	0xbe882b08, 0xbe8a2b0a,</div><div class='del'>-	0xbe8c2b0c, 0xbe8e2b0e,</div><div class='del'>-	0xc06b003a, 0x00000000,</div><div class='del'>-	0xbf8cc07f, 0xc06b013a,</div><div class='del'>-	0x00000010, 0xbf8cc07f,</div><div class='del'>-	0xc06b023a, 0x00000020,</div><div class='del'>-	0xbf8cc07f, 0xc06b033a,</div><div class='del'>-	0x00000030, 0xbf8cc07f,</div><div class='del'>-	0x8074c074, 0x82758075,</div><div class='del'>-	0x807c907c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffe7, 0xbef40172,</div><div class='del'>-	0xbef00080, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xbee80080,</div><div class='del'>-	0xbee90080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0x867aff78,</div><div class='del'>-	0x00400000, 0xbf850003,</div><div class='del'>-	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf85004d,</div><div class='del'>-	0xbe840080, 0xd2890000,</div><div class='add'>+	0xbefc007e, 0xbf108080,</div><div class='add'>+	0x867aff7f, 0x04000000,</div><div class='add'>+	0xbeef0080, 0x876f6f7a,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fb1605, 0x807b817b,</div><div class='add'>+	0x8e7b847b, 0x8e76827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbef20174, 0x80747074,</div><div class='add'>+	0x82758075, 0xbefc0080,</div><div class='add'>+	0xbf800000, 0xbe802b00,</div><div class='add'>+	0xbe822b02, 0xbe842b04,</div><div class='add'>+	0xbe862b06, 0xbe882b08,</div><div class='add'>+	0xbe8a2b0a, 0xbe8c2b0c,</div><div class='add'>+	0xbe8e2b0e, 0xc06b003a,</div><div class='add'>+	0x00000000, 0xbf8cc07f,</div><div class='add'>+	0xc06b013a, 0x00000010,</div><div class='add'>+	0xbf8cc07f, 0xc06b023a,</div><div class='add'>+	0x00000020, 0xbf8cc07f,</div><div class='add'>+	0xc06b033a, 0x00000030,</div><div class='add'>+	0xbf8cc07f, 0x8074c074,</div><div class='add'>+	0x82758075, 0x807c907c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffe7,</div><div class='add'>+	0xbef40172, 0xbef00080,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xbee80080, 0xbee90080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0x867aff78, 0x00400000,</div><div class='add'>+	0xbf850003, 0xb8faf803,</div><div class='add'>+	0x897a7aff, 0x10000000,</div><div class='add'>+	0xbf85004d, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000900,</div><div class='del'>-	0x80048104, 0xd2890002,</div><div class='add'>+	0xd2890002, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000900,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000901,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000901,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000901,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000901, 0x80048104,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890001, 0x00000902,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='ctx'> 	0x80048104, 0xd2890002,</div><div class='del'>-	0x00000902, 0x80048104,</div><div class='del'>-	0xd2890003, 0x00000902,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbf820008,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xb8fb4306, 0x867bc17b,</div><div class='add'>+	0xbf840064, 0xbf8a0000,</div><div class='add'>+	0x867aff6f, 0x04000000,</div><div class='add'>+	0xbf840060, 0x8e7b867b,</div><div class='add'>+	0x8e7b827b, 0xbef6007b,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fa1605, 0x807a817a,</div><div class='add'>+	0x8e7a867a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0080, 0xd28c0002,</div><div class='add'>+	0x000100c1, 0xd28d0003,</div><div class='add'>+	0x000204c1, 0x867aff78,</div><div class='add'>+	0x00400000, 0xbf850003,</div><div class='add'>+	0xb8faf803, 0x897a7aff,</div><div class='add'>+	0x10000000, 0xbf850030,</div><div class='add'>+	0x24040682, 0xd86e4000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0xbe840080,</div><div class='del'>-	0xd2890000, 0x00000903,</div><div class='add'>+	0xd2890000, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='del'>-	0xd2890002, 0x00000903,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000901,</div><div class='ctx'> 	0x80048104, 0xd2890003,</div><div class='del'>-	0x00000903, 0x80048104,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='ctx'> 	0xc069003a, 0x00000070,</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='del'>-	0xbf820008, 0xe0724000,</div><div class='del'>-	0x701d0000, 0xe0724100,</div><div class='del'>-	0x701d0100, 0xe0724200,</div><div class='del'>-	0x701d0200, 0xe0724300,</div><div class='del'>-	0x701d0300, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xb8fb4306,</div><div class='del'>-	0x867bc17b, 0xbf840064,</div><div class='del'>-	0xbf8a0000, 0x867aff6f,</div><div class='del'>-	0x04000000, 0xbf840060,</div><div class='del'>-	0x8e7b867b, 0x8e7b827b,</div><div class='del'>-	0xbef6007b, 0xb8f02985,</div><div class='del'>-	0x80708170, 0x8e708a70,</div><div class='del'>-	0x8e708170, 0xb8fa1605,</div><div class='del'>-	0x807a817a, 0x8e7a867a,</div><div class='del'>-	0x80707a70, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0080,</div><div class='del'>-	0xd28c0002, 0x000100c1,</div><div class='del'>-	0xd28d0003, 0x000204c1,</div><div class='add'>+	0x680404ff, 0x00000200,</div><div class='add'>+	0xd0c9006a, 0x0000f702,</div><div class='add'>+	0xbf87ffd2, 0xbf820015,</div><div class='add'>+	0xd1060002, 0x00011103,</div><div class='add'>+	0x7e0602ff, 0x00000200,</div><div class='add'>+	0xbefc00ff, 0x00010000,</div><div class='add'>+	0xbe800077, 0x8677ff77,</div><div class='add'>+	0xff7fffff, 0x8777ff77,</div><div class='add'>+	0x00058000, 0xd8ec0000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='add'>+	0xe0765000, 0x701d0002,</div><div class='add'>+	0x68040702, 0xd0c9006a,</div><div class='add'>+	0x0000f702, 0xbf87fff7,</div><div class='add'>+	0xbef70000, 0xbef000ff,</div><div class='add'>+	0x00000400, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8fb2b05,</div><div class='add'>+	0x807b817b, 0x8e7b827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0084, 0xbf0a7b7c,</div><div class='add'>+	0xbf84006d, 0xbf11017c,</div><div class='add'>+	0x807bff7b, 0x00001000,</div><div class='ctx'> 	0x867aff78, 0x00400000,</div><div class='ctx'> 	0xbf850003, 0xb8faf803,</div><div class='ctx'> 	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf850030, 0x24040682,</div><div class='del'>-	0xd86e4000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xbe840080,</div><div class='add'>+	0xbf850051, 0xbe840080,</div><div class='ctx'> 	0xd2890000, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='hunk'>@@ -3384,31 +3424,51 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {</div><div class='ctx'> 	0x80048104, 0xc069003a,</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='del'>-	0xbf84ffee, 0x680404ff,</div><div class='del'>-	0x00000200, 0xd0c9006a,</div><div class='del'>-	0x0000f702, 0xbf87ffd2,</div><div class='del'>-	0xbf820015, 0xd1060002,</div><div class='del'>-	0x00011103, 0x7e0602ff,</div><div class='del'>-	0x00000200, 0xbefc00ff,</div><div class='del'>-	0x00010000, 0xbe800077,</div><div class='del'>-	0x8677ff77, 0xff7fffff,</div><div class='del'>-	0x8777ff77, 0x00058000,</div><div class='del'>-	0xd8ec0000, 0x00000002,</div><div class='del'>-	0xbf8cc07f, 0xe0765000,</div><div class='del'>-	0x701d0002, 0x68040702,</div><div class='del'>-	0xd0c9006a, 0x0000f702,</div><div class='del'>-	0xbf87fff7, 0xbef70000,</div><div class='del'>-	0xbef000ff, 0x00000400,</div><div class='del'>-	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8fb2b05, 0x807b817b,</div><div class='del'>-	0x8e7b827b, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xbefc0084,</div><div class='del'>-	0xbf0a7b7c, 0xbf84006d,</div><div class='del'>-	0xbf11017c, 0x807bff7b,</div><div class='del'>-	0x00001000, 0x867aff78,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0x807c847c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffb1,</div><div class='add'>+	0xbf9c0000, 0xbf820012,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000400, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffef, 0xbf9c0000,</div><div class='add'>+	0xb8fb2985, 0x807b817b,</div><div class='add'>+	0x8e7b837b, 0xb8fa2b05,</div><div class='add'>+	0x807a817a, 0x8e7a827a,</div><div class='add'>+	0x80fb7a7b, 0x867b7b7b,</div><div class='add'>+	0xbf84007a, 0x807bff7b,</div><div class='add'>+	0x00001000, 0xbefc0080,</div><div class='add'>+	0xbf11017c, 0x867aff78,</div><div class='ctx'> 	0x00400000, 0xbf850003,</div><div class='ctx'> 	0xb8faf803, 0x897a7aff,</div><div class='del'>-	0x10000000, 0xbf850051,</div><div class='add'>+	0x10000000, 0xbf850059,</div><div class='add'>+	0xd3d84000, 0x18000100,</div><div class='add'>+	0xd3d84001, 0x18000101,</div><div class='add'>+	0xd3d84002, 0x18000102,</div><div class='add'>+	0xd3d84003, 0x18000103,</div><div class='ctx'> 	0xbe840080, 0xd2890000,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='ctx'> 	0xd2890001, 0x00000900,</div><div class='hunk'>@@ -3448,31 +3508,913 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {</div><div class='ctx'> 	0xbf8cc07f, 0x80709070,</div><div class='ctx'> 	0xbf06c004, 0xbf84ffee,</div><div class='ctx'> 	0x807c847c, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffb1, 0xbf9c0000,</div><div class='del'>-	0xbf820012, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0xe0724000,</div><div class='add'>+	0xbf85ffa9, 0xbf9c0000,</div><div class='add'>+	0xbf820016, 0xd3d84000,</div><div class='add'>+	0x18000100, 0xd3d84001,</div><div class='add'>+	0x18000101, 0xd3d84002,</div><div class='add'>+	0x18000102, 0xd3d84003,</div><div class='add'>+	0x18000103, 0xe0724000,</div><div class='ctx'> 	0x701d0000, 0xe0724100,</div><div class='ctx'> 	0x701d0100, 0xe0724200,</div><div class='ctx'> 	0x701d0200, 0xe0724300,</div><div class='ctx'> 	0x701d0300, 0x807c847c,</div><div class='ctx'> 	0x8070ff70, 0x00000400,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xbf9c0000, 0xb8fb2985,</div><div class='del'>-	0x807b817b, 0x8e7b837b,</div><div class='del'>-	0xb8fa2b05, 0x807a817a,</div><div class='del'>-	0x8e7a827a, 0x80fb7a7b,</div><div class='del'>-	0x867b7b7b, 0xbf84007a,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffeb,</div><div class='add'>+	0xbf9c0000, 0xbf8200ee,</div><div class='add'>+	0xbef4007e, 0x8675ff7f,</div><div class='add'>+	0x0000ffff, 0x8775ff75,</div><div class='add'>+	0x00040000, 0xbef60080,</div><div class='add'>+	0xbef700ff, 0x00807fac,</div><div class='add'>+	0x866eff7f, 0x04000000,</div><div class='add'>+	0xbf84001f, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8ef4306,</div><div class='add'>+	0x866fc16f, 0xbf84001a,</div><div class='add'>+	0x8e6f866f, 0x8e6f826f,</div><div class='add'>+	0xbef6006f, 0xb8f82985,</div><div class='add'>+	0x80788178, 0x8e788a78,</div><div class='add'>+	0x8e788178, 0xb8ee1605,</div><div class='add'>+	0x806e816e, 0x8e6e866e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc0080,</div><div class='add'>+	0xe0510000, 0x781d0000,</div><div class='add'>+	0xe0510100, 0x781d0000,</div><div class='add'>+	0x807cff7c, 0x00000200,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0xbf0a6f7c, 0xbf85fff6,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xb8ef2b05, 0x806f816f,</div><div class='add'>+	0x8e6f826f, 0x806fff6f,</div><div class='add'>+	0x00008000, 0xbef80080,</div><div class='add'>+	0xbeee0078, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbefc0084,</div><div class='add'>+	0xbf11087c, 0xe0524000,</div><div class='add'>+	0x781d0000, 0xe0524100,</div><div class='add'>+	0x781d0100, 0xe0524200,</div><div class='add'>+	0x781d0200, 0xe0524300,</div><div class='add'>+	0x781d0300, 0xbf8c0f70,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='add'>+	0x807c847c, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbf0a6f7c,</div><div class='add'>+	0xbf85ffee, 0xb8ef2985,</div><div class='add'>+	0x806f816f, 0x8e6f836f,</div><div class='add'>+	0xb8f92b05, 0x80798179,</div><div class='add'>+	0x8e798279, 0x80ef796f,</div><div class='add'>+	0x866f6f6f, 0xbf84001a,</div><div class='add'>+	0x806fff6f, 0x00008000,</div><div class='add'>+	0xbefc0080, 0xbf11087c,</div><div class='add'>+	0xe0524000, 0x781d0000,</div><div class='add'>+	0xe0524100, 0x781d0100,</div><div class='add'>+	0xe0524200, 0x781d0200,</div><div class='add'>+	0xe0524300, 0x781d0300,</div><div class='add'>+	0xbf8c0f70, 0xd3d94000,</div><div class='add'>+	0x18000100, 0xd3d94001,</div><div class='add'>+	0x18000101, 0xd3d94002,</div><div class='add'>+	0x18000102, 0xd3d94003,</div><div class='add'>+	0x18000103, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffea,</div><div class='add'>+	0xbf9c0000, 0xe0524000,</div><div class='add'>+	0x6e1d0000, 0xe0524100,</div><div class='add'>+	0x6e1d0100, 0xe0524200,</div><div class='add'>+	0x6e1d0200, 0xe0524300,</div><div class='add'>+	0x6e1d0300, 0xbf8c0f70,</div><div class='add'>+	0xb8f82985, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0x80f8c078, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f846f,</div><div class='add'>+	0x8e76826f, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc006f,</div><div class='add'>+	0xc031003a, 0x00000078,</div><div class='add'>+	0x80f8c078, 0xbf8cc07f,</div><div class='add'>+	0x80fc907c, 0xbf800000,</div><div class='add'>+	0xbe802d00, 0xbe822d02,</div><div class='add'>+	0xbe842d04, 0xbe862d06,</div><div class='add'>+	0xbe882d08, 0xbe8a2d0a,</div><div class='add'>+	0xbe8c2d0c, 0xbe8e2d0e,</div><div class='add'>+	0xbf06807c, 0xbf84fff0,</div><div class='add'>+	0xb8f82985, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0xbef60084, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xc0211bfa,</div><div class='add'>+	0x00000078, 0x80788478,</div><div class='add'>+	0xc0211b3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211b7a,</div><div class='add'>+	0x00000078, 0x80788478,</div><div class='add'>+	0xc0211c3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211c7a,</div><div class='add'>+	0x00000078, 0x80788478,</div><div class='add'>+	0xc0211eba, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211efa,</div><div class='add'>+	0x00000078, 0x80788478,</div><div class='add'>+	0xc0211a3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211a7a,</div><div class='add'>+	0x00000078, 0x80788478,</div><div class='add'>+	0xc0211cfa, 0x00000078,</div><div class='add'>+	0x80788478, 0xbf8cc07f,</div><div class='add'>+	0xbefc006f, 0xbefe0070,</div><div class='add'>+	0xbeff0071, 0x866f7bff,</div><div class='add'>+	0x000003ff, 0xb96f4803,</div><div class='add'>+	0x866f7bff, 0xfffff800,</div><div class='add'>+	0x8f6f8b6f, 0xb96fa2c3,</div><div class='add'>+	0xb973f801, 0xb8ee2985,</div><div class='add'>+	0x806e816e, 0x8e6e8a6e,</div><div class='add'>+	0x8e6e816e, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f866f,</div><div class='add'>+	0x806e6f6e, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x866fff6f,</div><div class='add'>+	0x0000ffff, 0xc00b1c37,</div><div class='add'>+	0x00000050, 0xc00b1d37,</div><div class='add'>+	0x00000060, 0xc0031e77,</div><div class='add'>+	0x00000074, 0xbf8cc07f,</div><div class='add'>+	0x8f6e8b79, 0x866eff6e,</div><div class='add'>+	0x001f8000, 0xb96ef807,</div><div class='add'>+	0x866dff6d, 0x0000ffff,</div><div class='add'>+	0x86fe7e7e, 0x86ea6a6a,</div><div class='add'>+	0x8f6e837a, 0xb96ee0c2,</div><div class='add'>+	0xbf800002, 0xb97a0002,</div><div class='add'>+	0xbf8a0000, 0xbe801f6c,</div><div class='add'>+	0xbf9b0000, 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint32_t cwsr_trap_gfx12_hex[] = {</div><div class='add'>+	0xbfa00001, 0xbfa002a2,</div><div class='add'>+	0xb0804009, 0xb8f8f804,</div><div class='add'>+	0x9178ff78, 0x00008c00,</div><div class='add'>+	0xb8fbf811, 0x8b6eff78,</div><div class='add'>+	0x00004000, 0xbfa10008,</div><div class='add'>+	0x8b6eff7b, 0x00000080,</div><div class='add'>+	0xbfa20018, 0x8b6ea07b,</div><div class='add'>+	0xbfa20042, 0xbf830010,</div><div class='add'>+	0xb8fbf811, 0xbfa0fffb,</div><div class='add'>+	0x8b6eff7b, 0x00000bd0,</div><div class='add'>+	0xbfa20010, 0xb8eef812,</div><div class='add'>+	0x8b6f8f7b, 0xbfa10002,</div><div class='add'>+	0x8c6eff6e, 0x00000080,</div><div class='add'>+	0xb8eff813, 0x8b6e6e6f,</div><div class='add'>+	0xbfa20008, 0x8b6eff6d,</div><div class='add'>+	0xf0000000, 0xbfa20005,</div><div class='add'>+	0x8b6fff6f, 0x00000200,</div><div class='add'>+	0xbfa20002, 0x8b6ea07b,</div><div class='add'>+	0xbfa2002c, 0xbefa4d82,</div><div class='add'>+	0xbf8a0000, 0x84fa887a,</div><div class='add'>+	0xbf0d8f7b, 0xbfa10002,</div><div class='add'>+	0x8c7bff7b, 0xffff0000,</div><div class='add'>+	0xf4601bbd, 0xf8000010,</div><div class='add'>+	0xbf8a0000, 0x846e976e,</div><div class='add'>+	0x9177ff77, 0x00800000,</div><div class='add'>+	0x8c776e77, 0xf4603bbd,</div><div class='add'>+	0xf8000000, 0xbf8a0000,</div><div class='add'>+	0xf4603ebd, 0xf8000008,</div><div class='add'>+	0xbf8a0000, 0x8bee6e6e,</div><div class='add'>+	0xbfa10001, 0xbe80486e,</div><div class='add'>+	0x8b6eff6d, 0xf0000000,</div><div class='add'>+	0xbfa20009, 0xb8eef811,</div><div class='add'>+	0x8b6eff6e, 0x00000080,</div><div class='add'>+	0xbfa20007, 0x8c78ff78,</div><div class='add'>+	0x00004000, 0x80ec886c,</div><div class='add'>+	0x82ed806d, 0xbfa00002,</div><div class='add'>+	0x806c846c, 0x826d806d,</div><div class='add'>+	0x8b6dff6d, 0x0000ffff,</div><div class='add'>+	0x8bfe7e7e, 0x8bea6a6a,</div><div class='add'>+	0x85788978, 0xb9783244,</div><div class='add'>+	0xbe804a6c, 0xb8faf802,</div><div class='add'>+	0xbf0d987a, 0xbfa10001,</div><div class='add'>+	0xbfb00000, 0x8b6dff6d,</div><div class='add'>+	0x0000ffff, 0xbefa0080,</div><div class='add'>+	0xb97a0151, 0xbeee007e,</div><div class='add'>+	0xbeef007f, 0xbefe0180,</div><div class='add'>+	0xbefe4d84, 0xbf8a0000,</div><div class='add'>+	0x8b7aff7f, 0x04000000,</div><div class='add'>+	0x847a857a, 0x8c6d7a6d,</div><div class='add'>+	0xbefa007e, 0x8b7bff7f,</div><div class='add'>+	0x0000ffff, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xee0a407a,</div><div class='add'>+	0x000c0000, 0x00000000,</div><div class='add'>+	0x7e000280, 0xbefe007a,</div><div class='add'>+	0xbeff007b, 0xb8fb0742,</div><div class='add'>+	0x847b997b, 0xb8fa3b05,</div><div class='add'>+	0x807a817a, 0xbf0d997b,</div><div class='add'>+	0xbfa20002, 0x847a897a,</div><div class='add'>+	0xbfa00001, 0x847a8a7a,</div><div class='add'>+	0xb8fb1e06, 0x847b8a7b,</div><div class='add'>+	0x807a7b7a, 0x8b7bff7f,</div><div class='add'>+	0x0000ffff, 0x807aff7a,</div><div class='add'>+	0x00000200, 0x807a7e7a,</div><div class='add'>+	0x827b807b, 0xd7610000,</div><div class='add'>+	0x00010870, 0xd7610000,</div><div class='add'>+	0x00010a71, 0xd7610000,</div><div class='add'>+	0x00010c72, 0xd7610000,</div><div class='add'>+	0x00010e73, 0xd7610000,</div><div class='add'>+	0x00011074, 0xd7610000,</div><div class='add'>+	0x00011275, 0xd7610000,</div><div class='add'>+	0x00011476, 0xd7610000,</div><div class='add'>+	0x00011677, 0xd7610000,</div><div class='add'>+	0x00011a79, 0xd7610000,</div><div class='add'>+	0x00011c7e, 0xd7610000,</div><div class='add'>+	0x00011e7f, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xbefe00ff,</div><div class='add'>+	0x00003fff, 0xbeff0080,</div><div class='add'>+	0xee0a407a, 0x000c0000,</div><div class='add'>+	0x00004000, 0xd760007a,</div><div class='add'>+	0x00011d00, 0xd760007b,</div><div class='add'>+	0x00011f00, 0xbefe007a,</div><div class='add'>+	0xbeff007b, 0xbef4007e,</div><div class='add'>+	0x8b75ff7f, 0x0000ffff,</div><div class='add'>+	0x8c75ff75, 0x00040000,</div><div class='add'>+	0xbef60080, 0xbef700ff,</div><div class='add'>+	0x10807fac, 0xbef1007d,</div><div class='add'>+	0xbef00080, 0xb8f30742,</div><div class='add'>+	0x84739973, 0xbefe00c1,</div><div class='add'>+	0x857d9973, 0x8b7d817d,</div><div class='add'>+	0xbf06817d, 0xbfa20002,</div><div class='add'>+	0xbeff0080, 0xbfa00002,</div><div class='add'>+	0xbeff00c1, 0xbfa0000c,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xc4068070, 0x008ce801,</div><div class='add'>+	0x00008000, 0xc4068070,</div><div class='add'>+	0x008ce802, 0x00010000,</div><div class='add'>+	0xc4068070, 0x008ce803,</div><div class='add'>+	0x00018000, 0xbfa0000b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xc4068070, 0x008ce801,</div><div class='add'>+	0x00010000, 0xc4068070,</div><div class='add'>+	0x008ce802, 0x00020000,</div><div class='add'>+	0xc4068070, 0x008ce803,</div><div class='add'>+	0x00030000, 0xb8f03b05,</div><div class='add'>+	0x80708170, 0xbf0d9973,</div><div class='add'>+	0xbfa20002, 0x84708970,</div><div class='add'>+	0xbfa00001, 0x84708a70,</div><div class='add'>+	0xb8fa1e06, 0x847a8a7a,</div><div class='add'>+	0x80707a70, 0x8070ff70,</div><div class='add'>+	0x00000200, 0xbef600ff,</div><div class='add'>+	0x01000000, 0x7e000280,</div><div class='add'>+	0x7e020280, 0x7e040280,</div><div class='add'>+	0xbe804ec2, 0xbf94fffe,</div><div class='add'>+	0xb8faf804, 0x8b7a847a,</div><div class='add'>+	0x91788478, 0x8c787a78,</div><div class='add'>+	0x917aff6d, 0x80000000,</div><div class='add'>+	0xd7610002, 0x00010071,</div><div class='add'>+	0xd7610002, 0x0001026c,</div><div class='add'>+	0xd7610002, 0x0001047a,</div><div class='add'>+	0xd7610002, 0x0001066e,</div><div class='add'>+	0xd7610002, 0x0001086f,</div><div class='add'>+	0xd7610002, 0x00010a78,</div><div class='add'>+	0xd7610002, 0x00010e7b,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xd8500000, 0x00000000,</div><div class='add'>+	0xb8faf811, 0xd7610002,</div><div class='add'>+	0x00010c7a, 0xb8faf801,</div><div class='add'>+	0xd7610002, 0x0001107a,</div><div class='add'>+	0xb8faf814, 0xd7610002,</div><div class='add'>+	0x0001127a, 0xb8faf815,</div><div class='add'>+	0xd7610002, 0x0001147a,</div><div class='add'>+	0xb8faf812, 0xd7610002,</div><div class='add'>+	0x0001167a, 0xb8faf813,</div><div class='add'>+	0xd7610002, 0x0001187a,</div><div class='add'>+	0xb8faf802, 0xd7610002,</div><div class='add'>+	0x00011a7a, 0xbefa50c1,</div><div class='add'>+	0xbfc70000, 0xd7610002,</div><div class='add'>+	0x00011c7a, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xbefe00ff,</div><div class='add'>+	0x0000ffff, 0xbeff0080,</div><div class='add'>+	0xc4068070, 0x008ce802,</div><div class='add'>+	0x00000000, 0xbefe00c1,</div><div class='add'>+	0xb8f03b05, 0x80708170,</div><div class='add'>+	0xbf0d9973, 0xbfa20002,</div><div class='add'>+	0x84708970, 0xbfa00001,</div><div class='add'>+	0x84708a70, 0xb8fa1e06,</div><div class='add'>+	0x847a8a7a, 0x80707a70,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbef90080, 0xbefd0080,</div><div class='add'>+	0xbf800000, 0xbe804100,</div><div class='add'>+	0xbe824102, 0xbe844104,</div><div class='add'>+	0xbe864106, 0xbe884108,</div><div class='add'>+	0xbe8a410a, 0xbe8c410c,</div><div class='add'>+	0xbe8e410e, 0xbf068079,</div><div class='add'>+	0xbfa10032, 0xd7610002,</div><div class='add'>+	0x00010000, 0xd7610002,</div><div class='add'>+	0x00010201, 0xd7610002,</div><div class='add'>+	0x00010402, 0xd7610002,</div><div class='add'>+	0x00010603, 0xd7610002,</div><div class='add'>+	0x00010804, 0xd7610002,</div><div class='add'>+	0x00010a05, 0xd7610002,</div><div class='add'>+	0x00010c06, 0xd7610002,</div><div class='add'>+	0x00010e07, 0xd7610002,</div><div class='add'>+	0x00011008, 0xd7610002,</div><div class='add'>+	0x00011209, 0xd7610002,</div><div class='add'>+	0x0001140a, 0xd7610002,</div><div class='add'>+	0x0001160b, 0xd7610002,</div><div class='add'>+	0x0001180c, 0xd7610002,</div><div class='add'>+	0x00011a0d, 0xd7610002,</div><div class='add'>+	0x00011c0e, 0xd7610002,</div><div class='add'>+	0x00011e0f, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0x80799079,</div><div class='add'>+	0xbfa00038, 0xd7610002,</div><div class='add'>+	0x00012000, 0xd7610002,</div><div class='add'>+	0x00012201, 0xd7610002,</div><div class='add'>+	0x00012402, 0xd7610002,</div><div class='add'>+	0x00012603, 0xd7610002,</div><div class='add'>+	0x00012804, 0xd7610002,</div><div class='add'>+	0x00012a05, 0xd7610002,</div><div class='add'>+	0x00012c06, 0xd7610002,</div><div class='add'>+	0x00012e07, 0xd7610002,</div><div class='add'>+	0x00013008, 0xd7610002,</div><div class='add'>+	0x00013209, 0xd7610002,</div><div class='add'>+	0x0001340a, 0xd7610002,</div><div class='add'>+	0x0001360b, 0xd7610002,</div><div class='add'>+	0x0001380c, 0xd7610002,</div><div class='add'>+	0x00013a0d, 0xd7610002,</div><div class='add'>+	0x00013c0e, 0xd7610002,</div><div class='add'>+	0x00013e0f, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0x80799079,</div><div class='add'>+	0xc4068070, 0x008ce802,</div><div class='add'>+	0x00000000, 0x8070ff70,</div><div class='add'>+	0x00000080, 0xbef90080,</div><div class='add'>+	0x7e040280, 0x807d907d,</div><div class='add'>+	0xbf0aff7d, 0x00000060,</div><div class='add'>+	0xbfa2ff88, 0xbe804100,</div><div class='add'>+	0xbe824102, 0xbe844104,</div><div class='add'>+	0xbe864106, 0xbe884108,</div><div class='add'>+	0xbe8a410a, 0xd7610002,</div><div class='add'>+	0x00010000, 0xd7610002,</div><div class='add'>+	0x00010201, 0xd7610002,</div><div class='add'>+	0x00010402, 0xd7610002,</div><div class='add'>+	0x00010603, 0xd7610002,</div><div class='add'>+	0x00010804, 0xd7610002,</div><div class='add'>+	0x00010a05, 0xd7610002,</div><div class='add'>+	0x00010c06, 0xd7610002,</div><div class='add'>+	0x00010e07, 0xd7610002,</div><div class='add'>+	0x00011008, 0xd7610002,</div><div class='add'>+	0x00011209, 0xd7610002,</div><div class='add'>+	0x0001140a, 0xd7610002,</div><div class='add'>+	0x0001160b, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xd8500000,</div><div class='add'>+	0x00000000, 0xc4068070,</div><div class='add'>+	0x008ce802, 0x00000000,</div><div class='add'>+	0xbefe00c1, 0x857d9973,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbfa20002, 0xbeff0080,</div><div class='add'>+	0xbfa00001, 0xbeff00c1,</div><div class='add'>+	0xb8fb4306, 0x8b7bc17b,</div><div class='add'>+	0xbfa10044, 0x8b7aff6d,</div><div class='add'>+	0x80000000, 0xbfa10041,</div><div class='add'>+	0x847b897b, 0xbef6007b,</div><div class='add'>+	0xb8f03b05, 0x80708170,</div><div class='add'>+	0xbf0d9973, 0xbfa20002,</div><div class='add'>+	0x84708970, 0xbfa00001,</div><div class='add'>+	0x84708a70, 0xb8fa1e06,</div><div class='add'>+	0x847a8a7a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000200,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xd71f0000, 0x000100c1,</div><div class='add'>+	0xd7200000, 0x000200c1,</div><div class='add'>+	0x16000084, 0x857d9973,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbefd0080, 0xbfa20013,</div><div class='add'>+	0xbe8300ff, 0x00000080,</div><div class='add'>+	0xbf800000, 0xbf800000,</div><div class='add'>+	0xbf800000, 0xd8d80000,</div><div class='add'>+	0x01000000, 0xbf8a0000,</div><div class='add'>+	0xc4068070, 0x008ce801,</div><div class='add'>+	0x00000000, 0x807d037d,</div><div class='add'>+	0x80700370, 0xd5250000,</div><div class='add'>+	0x0001ff00, 0x00000080,</div><div class='add'>+	0xbf0a7b7d, 0xbfa2fff3,</div><div class='add'>+	0xbfa00012, 0xbe8300ff,</div><div class='add'>+	0x00000100, 0xbf800000,</div><div class='add'>+	0xbf800000, 0xbf800000,</div><div class='add'>+	0xd8d80000, 0x01000000,</div><div class='add'>+	0xbf8a0000, 0xc4068070,</div><div class='add'>+	0x008ce801, 0x00000000,</div><div class='add'>+	0x807d037d, 0x80700370,</div><div class='add'>+	0xd5250000, 0x0001ff00,</div><div class='add'>+	0x00000100, 0xbf0a7b7d,</div><div class='add'>+	0xbfa2fff3, 0xbefe00c1,</div><div class='add'>+	0x857d9973, 0x8b7d817d,</div><div class='add'>+	0xbf06817d, 0xbfa20004,</div><div class='add'>+	0xbef000ff, 0x00000200,</div><div class='add'>+	0xbeff0080, 0xbfa00003,</div><div class='add'>+	0xbef000ff, 0x00000400,</div><div class='add'>+	0xbeff00c1, 0xb8fb3b05,</div><div class='add'>+	0x807b817b, 0x847b827b,</div><div class='add'>+	0x857d9973, 0x8b7d817d,</div><div class='add'>+	0xbf06817d, 0xbfa2001b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefd0084, 0xbf0a7b7d,</div><div class='add'>+	0xbfa10040, 0x7e008700,</div><div class='add'>+	0x7e028701, 0x7e048702,</div><div class='add'>+	0x7e068703, 0xc4068070,</div><div class='add'>+	0x008ce800, 0x00000000,</div><div class='add'>+	0xc4068070, 0x008ce801,</div><div class='add'>+	0x00008000, 0xc4068070,</div><div class='add'>+	0x008ce802, 0x00010000,</div><div class='add'>+	0xc4068070, 0x008ce803,</div><div class='add'>+	0x00018000, 0x807d847d,</div><div class='add'>+	0x8070ff70, 0x00000200,</div><div class='add'>+	0xbf0a7b7d, 0xbfa2ffeb,</div><div class='add'>+	0xbfa0002a, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefd0084,</div><div class='add'>+	0xbf0a7b7d, 0xbfa10015,</div><div class='add'>+	0x7e008700, 0x7e028701,</div><div class='add'>+	0x7e048702, 0x7e068703,</div><div class='add'>+	0xc4068070, 0x008ce800,</div><div class='add'>+	0x00000000, 0xc4068070,</div><div class='add'>+	0x008ce801, 0x00010000,</div><div class='add'>+	0xc4068070, 0x008ce802,</div><div class='add'>+	0x00020000, 0xc4068070,</div><div class='add'>+	0x008ce803, 0x00030000,</div><div class='add'>+	0x807d847d, 0x8070ff70,</div><div class='add'>+	0x00000400, 0xbf0a7b7d,</div><div class='add'>+	0xbfa2ffeb, 0xb8fb1e06,</div><div class='add'>+	0x8b7bc17b, 0xbfa1000d,</div><div class='add'>+	0x847b837b, 0x807b7d7b,</div><div class='add'>+	0xbefe00c1, 0xbeff0080,</div><div class='add'>+	0x7e008700, 0xc4068070,</div><div class='add'>+	0x008ce800, 0x00000000,</div><div class='add'>+	0x807d817d, 0x8070ff70,</div><div class='add'>+	0x00000080, 0xbf0a7b7d,</div><div class='add'>+	0xbfa2fff7, 0xbfa0016e,</div><div class='add'>+	0xbef4007e, 0x8b75ff7f,</div><div class='add'>+	0x0000ffff, 0x8c75ff75,</div><div class='add'>+	0x00040000, 0xbef60080,</div><div class='add'>+	0xbef700ff, 0x10807fac,</div><div class='add'>+	0xbef1007f, 0xb8f20742,</div><div class='add'>+	0x84729972, 0x8b6eff7f,</div><div class='add'>+	0x04000000, 0xbfa1003b,</div><div class='add'>+	0xbefe00c1, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbfa20002, 0xbeff0080,</div><div class='add'>+	0xbfa00001, 0xbeff00c1,</div><div class='add'>+	0xb8ef4306, 0x8b6fc16f,</div><div class='add'>+	0xbfa10030, 0x846f896f,</div><div class='add'>+	0xbef6006f, 0xb8f83b05,</div><div class='add'>+	0x80788178, 0xbf0d9972,</div><div class='add'>+	0xbfa20002, 0x84788978,</div><div class='add'>+	0xbfa00001, 0x84788a78,</div><div class='add'>+	0xb8ee1e06, 0x846e8a6e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000200, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbefd0080, 0xbfa2000d,</div><div class='add'>+	0xc4050078, 0x0080e800,</div><div class='add'>+	0x00000000, 0xbf8a0000,</div><div class='add'>+	0xdac00000, 0x00000000,</div><div class='add'>+	0x807dff7d, 0x00000080,</div><div class='add'>+	0x8078ff78, 0x00000080,</div><div class='add'>+	0xbf0a6f7d, 0xbfa2fff4,</div><div class='add'>+	0xbfa0000c, 0xc4050078,</div><div class='add'>+	0x0080e800, 0x00000000,</div><div class='add'>+	0xbf8a0000, 0xdac00000,</div><div class='add'>+	0x00000000, 0x807dff7d,</div><div class='add'>+	0x00000100, 0x8078ff78,</div><div class='add'>+	0x00000100, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2fff4, 0xbef80080,</div><div class='add'>+	0xbefe00c1, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbfa20002, 0xbeff0080,</div><div class='add'>+	0xbfa00001, 0xbeff00c1,</div><div class='add'>+	0xb8ef3b05, 0x806f816f,</div><div class='add'>+	0x846f826f, 0x857d9972,</div><div class='add'>+	0x8b7d817d, 0xbf06817d,</div><div class='add'>+	0xbfa2002c, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbeee0078,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0xbefd0084, 0xbf0a6f7d,</div><div class='add'>+	0xbfa10061, 0xc4050078,</div><div class='add'>+	0x008ce800, 0x00000000,</div><div class='add'>+	0xc4050078, 0x008ce801,</div><div class='add'>+	0x00008000, 0xc4050078,</div><div class='add'>+	0x008ce802, 0x00010000,</div><div class='add'>+	0xc4050078, 0x008ce803,</div><div class='add'>+	0x00018000, 0xbf8a0000,</div><div class='add'>+	0x7e008500, 0x7e028501,</div><div class='add'>+	0x7e048502, 0x7e068503,</div><div class='add'>+	0x807d847d, 0x8078ff78,</div><div class='add'>+	0x00000200, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2ffea, 0xc405006e,</div><div class='add'>+	0x008ce800, 0x00000000,</div><div class='add'>+	0xc405006e, 0x008ce801,</div><div class='add'>+	0x00008000, 0xc405006e,</div><div class='add'>+	0x008ce802, 0x00010000,</div><div class='add'>+	0xc405006e, 0x008ce803,</div><div class='add'>+	0x00018000, 0xbf8a0000,</div><div class='add'>+	0xbfa0003d, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbeee0078,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbefd0084, 0xbf0a6f7d,</div><div class='add'>+	0xbfa10016, 0xc4050078,</div><div class='add'>+	0x008ce800, 0x00000000,</div><div class='add'>+	0xc4050078, 0x008ce801,</div><div class='add'>+	0x00010000, 0xc4050078,</div><div class='add'>+	0x008ce802, 0x00020000,</div><div class='add'>+	0xc4050078, 0x008ce803,</div><div class='add'>+	0x00030000, 0xbf8a0000,</div><div class='add'>+	0x7e008500, 0x7e028501,</div><div class='add'>+	0x7e048502, 0x7e068503,</div><div class='add'>+	0x807d847d, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbf0a6f7d,</div><div class='add'>+	0xbfa2ffea, 0xb8ef1e06,</div><div class='add'>+	0x8b6fc16f, 0xbfa1000f,</div><div class='add'>+	0x846f836f, 0x806f7d6f,</div><div class='add'>+	0xbefe00c1, 0xbeff0080,</div><div class='add'>+	0xc4050078, 0x008ce800,</div><div class='add'>+	0x00000000, 0xbf8a0000,</div><div class='add'>+	0x7e008500, 0x807d817d,</div><div class='add'>+	0x8078ff78, 0x00000080,</div><div class='add'>+	0xbf0a6f7d, 0xbfa2fff6,</div><div class='add'>+	0xbeff00c1, 0xc405006e,</div><div class='add'>+	0x008ce800, 0x00000000,</div><div class='add'>+	0xc405006e, 0x008ce801,</div><div class='add'>+	0x00010000, 0xc405006e,</div><div class='add'>+	0x008ce802, 0x00020000,</div><div class='add'>+	0xc405006e, 0x008ce803,</div><div class='add'>+	0x00030000, 0xbf8a0000,</div><div class='add'>+	0xb8f83b05, 0x80788178,</div><div class='add'>+	0xbf0d9972, 0xbfa20002,</div><div class='add'>+	0x84788978, 0xbfa00001,</div><div class='add'>+	0x84788a78, 0xb8ee1e06,</div><div class='add'>+	0x846e8a6e, 0x80786e78,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0x80f8ff78, 0x00000050,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefd00ff, 0x0000006c,</div><div class='add'>+	0x80f89078, 0xf462403a,</div><div class='add'>+	0xf0000000, 0xbf8a0000,</div><div class='add'>+	0x80fd847d, 0xbf800000,</div><div class='add'>+	0xbe804300, 0xbe824302,</div><div class='add'>+	0x80f8a078, 0xf462603a,</div><div class='add'>+	0xf0000000, 0xbf8a0000,</div><div class='add'>+	0x80fd887d, 0xbf800000,</div><div class='add'>+	0xbe804300, 0xbe824302,</div><div class='add'>+	0xbe844304, 0xbe864306,</div><div class='add'>+	0x80f8c078, 0xf462803a,</div><div class='add'>+	0xf0000000, 0xbf8a0000,</div><div class='add'>+	0x80fd907d, 0xbf800000,</div><div class='add'>+	0xbe804300, 0xbe824302,</div><div class='add'>+	0xbe844304, 0xbe864306,</div><div class='add'>+	0xbe884308, 0xbe8a430a,</div><div class='add'>+	0xbe8c430c, 0xbe8e430e,</div><div class='add'>+	0xbf06807d, 0xbfa1fff0,</div><div class='add'>+	0xb980f801, 0x00000000,</div><div class='add'>+	0xb8f83b05, 0x80788178,</div><div class='add'>+	0xbf0d9972, 0xbfa20002,</div><div class='add'>+	0x84788978, 0xbfa00001,</div><div class='add'>+	0x84788a78, 0xb8ee1e06,</div><div class='add'>+	0x846e8a6e, 0x80786e78,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbeff0071, 0xf4621bfa,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xf4621b3a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4621b7a,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xf4621c3a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4621c7a,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xf4621eba, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4621efa,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xf4621e7a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4621cfa,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xf4621bba, 0xf0000000,</div><div class='add'>+	0x80788478, 0xbf8a0000,</div><div class='add'>+	0xb96ef814, 0xf4621bba,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xbf8a0000, 0xb96ef815,</div><div class='add'>+	0xf4621bba, 0xf0000000,</div><div class='add'>+	0x80788478, 0xbf8a0000,</div><div class='add'>+	0xb96ef812, 0xf4621bba,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xbf8a0000, 0xb96ef813,</div><div class='add'>+	0x8b6eff7f, 0x04000000,</div><div class='add'>+	0xbfa1000d, 0x80788478,</div><div class='add'>+	0xf4621bba, 0xf0000000,</div><div class='add'>+	0x80788478, 0xbf8a0000,</div><div class='add'>+	0xbf0d806e, 0xbfa10006,</div><div class='add'>+	0x856e906e, 0x8b6e6e6e,</div><div class='add'>+	0xbfa10003, 0xbe804ec1,</div><div class='add'>+	0x816ec16e, 0xbfa0fffb,</div><div class='add'>+	0xbefd006f, 0xbefe0070,</div><div class='add'>+	0xbeff0071, 0xb97b2011,</div><div class='add'>+	0x857b867b, 0xb97b0191,</div><div class='add'>+	0x857b827b, 0xb97bba11,</div><div class='add'>+	0xb973f801, 0xb8ee3b05,</div><div class='add'>+	0x806e816e, 0xbf0d9972,</div><div class='add'>+	0xbfa20002, 0x846e896e,</div><div class='add'>+	0xbfa00001, 0x846e8a6e,</div><div class='add'>+	0xb8ef1e06, 0x846f8a6f,</div><div class='add'>+	0x806e6f6e, 0x806eff6e,</div><div class='add'>+	0x00000200, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x8b6fff6f,</div><div class='add'>+	0x0000ffff, 0xf4605c37,</div><div class='add'>+	0xf8000050, 0xf4605d37,</div><div class='add'>+	0xf8000060, 0xf4601e77,</div><div class='add'>+	0xf8000074, 0xbf8a0000,</div><div class='add'>+	0x8b6dff6d, 0x0000ffff,</div><div class='add'>+	0x8bfe7e7e, 0x8bea6a6a,</div><div class='add'>+	0xb97af804, 0xbe804ec2,</div><div class='add'>+	0xbf94fffe, 0xbe804a6c,</div><div class='add'>+	0xbe804ec2, 0xbf94fffe,</div><div class='add'>+	0xbfb10000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+	0xbf9f0000, 0xbf9f0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint32_t cwsr_trap_gfx9_5_0_hex[] = {</div><div class='add'>+	0xbf820001, 0xbf8202ca,</div><div class='add'>+	0xb8f8f802, 0x8978ff78,</div><div class='add'>+	0x00020006, 0xb8fbf803,</div><div class='add'>+	0x866eff78, 0x00002000,</div><div class='add'>+	0xbf840009, 0x866eff6d,</div><div class='add'>+	0x00ff0000, 0xbf85001a,</div><div class='add'>+	0x866eff7b, 0x00000400,</div><div class='add'>+	0xbf850051, 0xbf8e0010,</div><div class='add'>+	0xb8fbf803, 0xbf82fffa,</div><div class='add'>+	0x866eff7b, 0x03c00900,</div><div class='add'>+	0xbf850011, 0x866eff7b,</div><div class='add'>+	0x000071ff, 0xbf840008,</div><div class='add'>+	0x866fff7b, 0x00007080,</div><div class='add'>+	0xbf840001, 0xbeee1a87,</div><div class='add'>+	0xb8eff801, 0x8e6e8c6e,</div><div class='add'>+	0x866e6f6e, 0xbf850006,</div><div class='add'>+	0x866eff6d, 0x00ff0000,</div><div class='add'>+	0xbf850003, 0x866eff7b,</div><div class='add'>+	0x00000400, 0xbf85003a,</div><div class='add'>+	0xb8faf807, 0x867aff7a,</div><div class='add'>+	0x001f8000, 0x8e7a8b7a,</div><div class='add'>+	0x8979ff79, 0xfc000000,</div><div class='add'>+	0x87797a79, 0xba7ff807,</div><div class='add'>+	0x00000000, 0xb8faf812,</div><div class='add'>+	0xb8fbf813, 0x8efa887a,</div><div class='add'>+	0xbf0d8f7b, 0xbf840002,</div><div class='add'>+	0x877bff7b, 0xffff0000,</div><div class='add'>+	0xc0031bbd, 0x00000010,</div><div class='add'>+	0xbf8cc07f, 0x8e6e976e,</div><div class='add'>+	0x8979ff79, 0x00800000,</div><div class='add'>+	0x87796e79, 0xc0071bbd,</div><div class='add'>+	0x00000000, 0xbf8cc07f,</div><div class='add'>+	0xc0071ebd, 0x00000008,</div><div class='add'>+	0xbf8cc07f, 0x86ee6e6e,</div><div class='add'>+	0xbf840001, 0xbe801d6e,</div><div class='add'>+	0x866eff6d, 0x01ff0000,</div><div class='add'>+	0xbf850005, 0x8778ff78,</div><div class='add'>+	0x00002000, 0x80ec886c,</div><div class='add'>+	0x82ed806d, 0xbf820005,</div><div class='add'>+	0x866eff6d, 0x01000000,</div><div class='add'>+	0xbf850002, 0x806c846c,</div><div class='add'>+	0x826d806d, 0x866dff6d,</div><div class='add'>+	0x0000ffff, 0x8f7a8b79,</div><div class='add'>+	0x867aff7a, 0x001f8000,</div><div class='add'>+	0xb97af807, 0x86fe7e7e,</div><div class='add'>+	0x86ea6a6a, 0x8f6e8378,</div><div class='add'>+	0xb96ee0c2, 0xbf800002,</div><div class='add'>+	0xb9780002, 0xbe801f6c,</div><div class='add'>+	0x866dff6d, 0x0000ffff,</div><div class='add'>+	0xbefa0080, 0xb97a0283,</div><div class='add'>+	0xb8faf807, 0x867aff7a,</div><div class='add'>+	0x001f8000, 0x8e7a8b7a,</div><div class='add'>+	0x8979ff79, 0xfc000000,</div><div class='add'>+	0x87797a79, 0xba7ff807,</div><div class='add'>+	0x00000000, 0xbeee007e,</div><div class='add'>+	0xbeef007f, 0xbefe0180,</div><div class='add'>+	0xbf900004, 0x877a8478,</div><div class='add'>+	0xb97af802, 0xbf8e0002,</div><div class='add'>+	0xbf88fffe, 0xb8fa2985,</div><div class='add'>+	0x807a817a, 0x8e7a8a7a,</div><div class='add'>+	0x8e7a817a, 0xb8fb1605,</div><div class='add'>+	0x807b817b, 0x8e7b867b,</div><div class='add'>+	0x807a7b7a, 0x807a7e7a,</div><div class='add'>+	0x827b807f, 0x867bff7b,</div><div class='add'>+	0x0000ffff, 0xc04b1c3d,</div><div class='add'>+	0x00000050, 0xbf8cc07f,</div><div class='add'>+	0xc04b1d3d, 0x00000060,</div><div class='add'>+	0xbf8cc07f, 0xc0431e7d,</div><div class='add'>+	0x00000074, 0xbf8cc07f,</div><div class='add'>+	0xbef4007e, 0x8675ff7f,</div><div class='add'>+	0x0000ffff, 0x8775ff75,</div><div class='add'>+	0x00040000, 0xbef60080,</div><div class='add'>+	0xbef700ff, 0x00807fac,</div><div class='add'>+	0xbef1007c, 0xbef00080,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fa1605, 0x807a817a,</div><div class='add'>+	0x8e7a867a, 0x80707a70,</div><div class='add'>+	0xbef60084, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefe007c,</div><div class='add'>+	0xbefc0070, 0xc0611c7a,</div><div class='add'>+	0x0000007c, 0xbf8cc07f,</div><div class='add'>+	0x80708470, 0xbefc007e,</div><div class='add'>+	0xbefe007c, 0xbefc0070,</div><div class='add'>+	0xc0611b3a, 0x0000007c,</div><div class='add'>+	0xbf8cc07f, 0x80708470,</div><div class='add'>+	0xbefc007e, 0xbefe007c,</div><div class='add'>+	0xbefc0070, 0xc0611b7a,</div><div class='add'>+	0x0000007c, 0xbf8cc07f,</div><div class='add'>+	0x80708470, 0xbefc007e,</div><div class='add'>+	0xbefe007c, 0xbefc0070,</div><div class='add'>+	0xc0611bba, 0x0000007c,</div><div class='add'>+	0xbf8cc07f, 0x80708470,</div><div class='add'>+	0xbefc007e, 0xbefe007c,</div><div class='add'>+	0xbefc0070, 0xc0611bfa,</div><div class='add'>+	0x0000007c, 0xbf8cc07f,</div><div class='add'>+	0x80708470, 0xbefc007e,</div><div class='add'>+	0xbefe007c, 0xbefc0070,</div><div class='add'>+	0xc0611e3a, 0x0000007c,</div><div class='add'>+	0xbf8cc07f, 0x80708470,</div><div class='add'>+	0xbefc007e, 0xb8fbf803,</div><div class='add'>+	0xbefe007c, 0xbefc0070,</div><div class='add'>+	0xc0611efa, 0x0000007c,</div><div class='add'>+	0xbf8cc07f, 0x80708470,</div><div class='add'>+	0xbefc007e, 0xbefe007c,</div><div class='add'>+	0xbefc0070, 0xc0611a3a,</div><div class='add'>+	0x0000007c, 0xbf8cc07f,</div><div class='add'>+	0x80708470, 0xbefc007e,</div><div class='add'>+	0xbefe007c, 0xbefc0070,</div><div class='add'>+	0xc0611a7a, 0x0000007c,</div><div class='add'>+	0xbf8cc07f, 0x80708470,</div><div class='add'>+	0xbefc007e, 0xb8f1f801,</div><div class='add'>+	0xbefe007c, 0xbefc0070,</div><div class='add'>+	0xc0611c7a, 0x0000007c,</div><div class='add'>+	0xbf8cc07f, 0x80708470,</div><div class='add'>+	0xbefc007e, 0xbf108080,</div><div class='add'>+	0x867aff7f, 0x04000000,</div><div class='add'>+	0xbeef0080, 0x876f6f7a,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fb1605, 0x807b817b,</div><div class='add'>+	0x8e7b847b, 0x8e76827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbef20174, 0x80747074,</div><div class='add'>+	0x82758075, 0xbefc0080,</div><div class='add'>+	0xbf800000, 0xbe802b00,</div><div class='add'>+	0xbe822b02, 0xbe842b04,</div><div class='add'>+	0xbe862b06, 0xbe882b08,</div><div class='add'>+	0xbe8a2b0a, 0xbe8c2b0c,</div><div class='add'>+	0xbe8e2b0e, 0xc06b003a,</div><div class='add'>+	0x00000000, 0xbf8cc07f,</div><div class='add'>+	0xc06b013a, 0x00000010,</div><div class='add'>+	0xbf8cc07f, 0xc06b023a,</div><div class='add'>+	0x00000020, 0xbf8cc07f,</div><div class='add'>+	0xc06b033a, 0x00000030,</div><div class='add'>+	0xbf8cc07f, 0x8074c074,</div><div class='add'>+	0x82758075, 0x807c907c,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffe7,</div><div class='add'>+	0xbef40172, 0xbef00080,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xbee80080, 0xbee90080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0x867aff78, 0x00400000,</div><div class='add'>+	0xbf850003, 0xb8faf803,</div><div class='add'>+	0x897a7aff, 0x10000000,</div><div class='add'>+	0xbf85004d, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000901,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000901,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000903,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbf820008,</div><div class='add'>+	0xe0724000, 0x701d0000,</div><div class='add'>+	0xe0724100, 0x701d0100,</div><div class='add'>+	0xe0724200, 0x701d0200,</div><div class='add'>+	0xe0724300, 0x701d0300,</div><div class='add'>+	0xbefe00c1, 0xbeff00c1,</div><div class='add'>+	0xb8fb5306, 0x867bc17b,</div><div class='add'>+	0xbf840052, 0xbf8a0000,</div><div class='add'>+	0x867aff6f, 0x04000000,</div><div class='add'>+	0xbf84004e, 0x8e7b867b,</div><div class='add'>+	0x8e7b827b, 0xbef6007b,</div><div class='add'>+	0xb8f02985, 0x80708170,</div><div class='add'>+	0x8e708a70, 0x8e708170,</div><div class='add'>+	0xb8fa1605, 0x807a817a,</div><div class='add'>+	0x8e7a867a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0080, 0xd28c0002,</div><div class='add'>+	0x000100c1, 0xd28d0003,</div><div class='add'>+	0x000204c1, 0x867aff78,</div><div class='add'>+	0x00400000, 0xbf850003,</div><div class='add'>+	0xb8faf803, 0x897a7aff,</div><div class='add'>+	0x10000000, 0xbf85001d,</div><div class='add'>+	0x24040682, 0xd86c0000,</div><div class='add'>+	0x00000002, 0xbf8cc07f,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000900,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0x680404ff,</div><div class='add'>+	0x00000100, 0xd0c9006a,</div><div class='add'>+	0x0000f702, 0xbf87ffe5,</div><div class='add'>+	0xbf820016, 0xd1060002,</div><div class='add'>+	0x00011103, 0x7e0602ff,</div><div class='add'>+	0x00000200, 0xbefc00ff,</div><div class='add'>+	0x00010000, 0xbe800077,</div><div class='add'>+	0x8677ff77, 0xff7fffff,</div><div class='add'>+	0x8777ff77, 0x00058000,</div><div class='add'>+	0xd8ec0000, 0x00000002,</div><div class='add'>+	0xbf8cc07f, 0xe0765000,</div><div class='add'>+	0x701d0002, 0x68040702,</div><div class='add'>+	0xd0c9006a, 0x0000f702,</div><div class='add'>+	0xbefe016a, 0xbf87fff6,</div><div class='add'>+	0xbef70000, 0xbef000ff,</div><div class='add'>+	0x00000400, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8fb2b05,</div><div class='add'>+	0x807b817b, 0x8e7b827b,</div><div class='add'>+	0xbef600ff, 0x01000000,</div><div class='add'>+	0xbefc0084, 0xbf0a7b7c,</div><div class='add'>+	0xbf84006d, 0xbf11017c,</div><div class='ctx'> 	0x807bff7b, 0x00001000,</div><div class='del'>-	0xbefc0080, 0xbf11017c,</div><div class='ctx'> 	0x867aff78, 0x00400000,</div><div class='ctx'> 	0xbf850003, 0xb8faf803,</div><div class='ctx'> 	0x897a7aff, 0x10000000,</div><div class='del'>-	0xbf850059, 0xd3d84000,</div><div class='del'>-	0x18000100, 0xd3d84001,</div><div class='del'>-	0x18000101, 0xd3d84002,</div><div class='del'>-	0x18000102, 0xd3d84003,</div><div class='del'>-	0x18000103, 0xbe840080,</div><div class='add'>+	0xbf850051, 0xbe840080,</div><div class='ctx'> 	0xd2890000, 0x00000900,</div><div class='ctx'> 	0x80048104, 0xd2890001,</div><div class='ctx'> 	0x00000900, 0x80048104,</div><div class='hunk'>@@ -3511,137 +4453,204 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {</div><div class='ctx'> 	0x00000070, 0xbf8cc07f,</div><div class='ctx'> 	0x80709070, 0xbf06c004,</div><div class='ctx'> 	0xbf84ffee, 0x807c847c,</div><div class='del'>-	0xbf0a7b7c, 0xbf85ffa9,</div><div class='del'>-	0xbf9c0000, 0xbf820016,</div><div class='del'>-	0xd3d84000, 0x18000100,</div><div class='del'>-	0xd3d84001, 0x18000101,</div><div class='del'>-	0xd3d84002, 0x18000102,</div><div class='del'>-	0xd3d84003, 0x18000103,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffb1,</div><div class='add'>+	0xbf9c0000, 0xbf820012,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='ctx'> 	0xe0724000, 0x701d0000,</div><div class='ctx'> 	0xe0724100, 0x701d0100,</div><div class='ctx'> 	0xe0724200, 0x701d0200,</div><div class='ctx'> 	0xe0724300, 0x701d0300,</div><div class='ctx'> 	0x807c847c, 0x8070ff70,</div><div class='ctx'> 	0x00000400, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffeb, 0xbf9c0000,</div><div class='del'>-	0xbf8200ee, 0xbef4007e,</div><div class='del'>-	0x8675ff7f, 0x0000ffff,</div><div class='del'>-	0x8775ff75, 0x00040000,</div><div class='del'>-	0xbef60080, 0xbef700ff,</div><div class='del'>-	0x00807fac, 0x866eff7f,</div><div class='del'>-	0x04000000, 0xbf84001f,</div><div class='add'>+	0xbf85ffef, 0xbf9c0000,</div><div class='add'>+	0xb8fb2985, 0x807b817b,</div><div class='add'>+	0x8e7b837b, 0xb8fa2b05,</div><div class='add'>+	0x807a817a, 0x8e7a827a,</div><div class='add'>+	0x80fb7a7b, 0x867b7b7b,</div><div class='add'>+	0xbf84007a, 0x807bff7b,</div><div class='add'>+	0x00001000, 0xbefc0080,</div><div class='add'>+	0xbf11017c, 0x867aff78,</div><div class='add'>+	0x00400000, 0xbf850003,</div><div class='add'>+	0xb8faf803, 0x897a7aff,</div><div class='add'>+	0x10000000, 0xbf850059,</div><div class='add'>+	0xd3d84000, 0x18000100,</div><div class='add'>+	0xd3d84001, 0x18000101,</div><div class='add'>+	0xd3d84002, 0x18000102,</div><div class='add'>+	0xd3d84003, 0x18000103,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000900,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000900, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000900,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000901,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000901,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000901, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0xbe840080, 0xd2890000,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890001, 0x00000902,</div><div class='add'>+	0x80048104, 0xd2890002,</div><div class='add'>+	0x00000902, 0x80048104,</div><div class='add'>+	0xd2890003, 0x00000902,</div><div class='add'>+	0x80048104, 0xc069003a,</div><div class='add'>+	0x00000070, 0xbf8cc07f,</div><div class='add'>+	0x80709070, 0xbf06c004,</div><div class='add'>+	0xbf84ffee, 0xbe840080,</div><div class='add'>+	0xd2890000, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890001,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xd2890002, 0x00000903,</div><div class='add'>+	0x80048104, 0xd2890003,</div><div class='add'>+	0x00000903, 0x80048104,</div><div class='add'>+	0xc069003a, 0x00000070,</div><div class='add'>+	0xbf8cc07f, 0x80709070,</div><div class='add'>+	0xbf06c004, 0xbf84ffee,</div><div class='add'>+	0x807c847c, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffa9, 0xbf9c0000,</div><div class='add'>+	0xbf820016, 0xd3d84000,</div><div class='add'>+	0x18000100, 0xd3d84001,</div><div class='add'>+	0x18000101, 0xd3d84002,</div><div class='add'>+	0x18000102, 0xd3d84003,</div><div class='add'>+	0x18000103, 0xe0724000,</div><div class='add'>+	0x701d0000, 0xe0724100,</div><div class='add'>+	0x701d0100, 0xe0724200,</div><div class='add'>+	0x701d0200, 0xe0724300,</div><div class='add'>+	0x701d0300, 0x807c847c,</div><div class='add'>+	0x8070ff70, 0x00000400,</div><div class='add'>+	0xbf0a7b7c, 0xbf85ffeb,</div><div class='add'>+	0xbf9c0000, 0xbf8200f4,</div><div class='add'>+	0xbef4007e, 0x8675ff7f,</div><div class='add'>+	0x0000ffff, 0x8775ff75,</div><div class='add'>+	0x00040000, 0xbef60080,</div><div class='add'>+	0xbef700ff, 0x00807fac,</div><div class='add'>+	0x866eff7f, 0x04000000,</div><div class='add'>+	0xbf840025, 0xbefe00c1,</div><div class='add'>+	0xbeff00c1, 0xb8ef5306,</div><div class='add'>+	0x866fc16f, 0xbf840020,</div><div class='add'>+	0x8e6f866f, 0x8e6f826f,</div><div class='add'>+	0xbef6006f, 0xb8f82985,</div><div class='add'>+	0x80788178, 0x8e788a78,</div><div class='add'>+	0x8e788178, 0xb8ee1605,</div><div class='add'>+	0x806e816e, 0x8e6e866e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc0080,</div><div class='add'>+	0xe0510000, 0x781d0000,</div><div class='add'>+	0xe0510100, 0x781d0000,</div><div class='add'>+	0xe0510200, 0x781d0000,</div><div class='add'>+	0xe0510300, 0x781d0000,</div><div class='add'>+	0xe0510400, 0x781d0000,</div><div class='add'>+	0x807cff7c, 0x00000500,</div><div class='add'>+	0x8078ff78, 0x00000500,</div><div class='add'>+	0xbf0a6f7c, 0xbf85fff0,</div><div class='ctx'> 	0xbefe00c1, 0xbeff00c1,</div><div class='del'>-	0xb8ef4306, 0x866fc16f,</div><div class='del'>-	0xbf84001a, 0x8e6f866f,</div><div class='del'>-	0x8e6f826f, 0xbef6006f,</div><div class='del'>-	0xb8f82985, 0x80788178,</div><div class='del'>-	0x8e788a78, 0x8e788178,</div><div class='del'>-	0xb8ee1605, 0x806e816e,</div><div class='del'>-	0x8e6e866e, 0x80786e78,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='ctx'> 	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc0080, 0xe0510000,</div><div class='del'>-	0x781d0000, 0xe0510100,</div><div class='del'>-	0x781d0000, 0x807cff7c,</div><div class='del'>-	0x00000200, 0x8078ff78,</div><div class='del'>-	0x00000200, 0xbf0a6f7c,</div><div class='del'>-	0xbf85fff6, 0xbefe00c1,</div><div class='del'>-	0xbeff00c1, 0xbef600ff,</div><div class='del'>-	0x01000000, 0xb8ef2b05,</div><div class='del'>-	0x806f816f, 0x8e6f826f,</div><div class='del'>-	0x806fff6f, 0x00008000,</div><div class='del'>-	0xbef80080, 0xbeee0078,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbefc0084, 0xbf11087c,</div><div class='del'>-	0xe0524000, 0x781d0000,</div><div class='del'>-	0xe0524100, 0x781d0100,</div><div class='del'>-	0xe0524200, 0x781d0200,</div><div class='del'>-	0xe0524300, 0x781d0300,</div><div class='del'>-	0xbf8c0f70, 0x7e000300,</div><div class='del'>-	0x7e020301, 0x7e040302,</div><div class='del'>-	0x7e060303, 0x807c847c,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbf0a6f7c, 0xbf85ffee,</div><div class='del'>-	0xb8ef2985, 0x806f816f,</div><div class='del'>-	0x8e6f836f, 0xb8f92b05,</div><div class='del'>-	0x80798179, 0x8e798279,</div><div class='del'>-	0x80ef796f, 0x866f6f6f,</div><div class='del'>-	0xbf84001a, 0x806fff6f,</div><div class='del'>-	0x00008000, 0xbefc0080,</div><div class='add'>+	0xb8ef2b05, 0x806f816f,</div><div class='add'>+	0x8e6f826f, 0x806fff6f,</div><div class='add'>+	0x00008000, 0xbef80080,</div><div class='add'>+	0xbeee0078, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbefc0084,</div><div class='ctx'> 	0xbf11087c, 0xe0524000,</div><div class='ctx'> 	0x781d0000, 0xe0524100,</div><div class='ctx'> 	0x781d0100, 0xe0524200,</div><div class='ctx'> 	0x781d0200, 0xe0524300,</div><div class='ctx'> 	0x781d0300, 0xbf8c0f70,</div><div class='del'>-	0xd3d94000, 0x18000100,</div><div class='del'>-	0xd3d94001, 0x18000101,</div><div class='del'>-	0xd3d94002, 0x18000102,</div><div class='del'>-	0xd3d94003, 0x18000103,</div><div class='add'>+	0x7e000300, 0x7e020301,</div><div class='add'>+	0x7e040302, 0x7e060303,</div><div class='ctx'> 	0x807c847c, 0x8078ff78,</div><div class='ctx'> 	0x00000400, 0xbf0a6f7c,</div><div class='del'>-	0xbf85ffea, 0xbf9c0000,</div><div class='del'>-	0xe0524000, 0x6e1d0000,</div><div class='del'>-	0xe0524100, 0x6e1d0100,</div><div class='del'>-	0xe0524200, 0x6e1d0200,</div><div class='del'>-	0xe0524300, 0x6e1d0300,</div><div class='del'>-	0xbf8c0f70, 0xb8f82985,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0x80f8c078,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f846f, 0x8e76826f,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xbefc006f, 0xc031003a,</div><div class='del'>-	0x00000078, 0x80f8c078,</div><div class='del'>-	0xbf8cc07f, 0x80fc907c,</div><div class='del'>-	0xbf800000, 0xbe802d00,</div><div class='del'>-	0xbe822d02, 0xbe842d04,</div><div class='del'>-	0xbe862d06, 0xbe882d08,</div><div class='del'>-	0xbe8a2d0a, 0xbe8c2d0c,</div><div class='del'>-	0xbe8e2d0e, 0xbf06807c,</div><div class='del'>-	0xbf84fff0, 0xb8f82985,</div><div class='del'>-	0x80788178, 0x8e788a78,</div><div class='del'>-	0x8e788178, 0xb8ee1605,</div><div class='del'>-	0x806e816e, 0x8e6e866e,</div><div class='del'>-	0x80786e78, 0xbef60084,</div><div class='del'>-	0xbef600ff, 0x01000000,</div><div class='del'>-	0xc0211bfa, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211b3a,</div><div class='add'>+	0xbf85ffee, 0xb8ef2985,</div><div class='add'>+	0x806f816f, 0x8e6f836f,</div><div class='add'>+	0xb8f92b05, 0x80798179,</div><div class='add'>+	0x8e798279, 0x80ef796f,</div><div class='add'>+	0x866f6f6f, 0xbf84001a,</div><div class='add'>+	0x806fff6f, 0x00008000,</div><div class='add'>+	0xbefc0080, 0xbf11087c,</div><div class='add'>+	0xe0524000, 0x781d0000,</div><div class='add'>+	0xe0524100, 0x781d0100,</div><div class='add'>+	0xe0524200, 0x781d0200,</div><div class='add'>+	0xe0524300, 0x781d0300,</div><div class='add'>+	0xbf8c0f70, 0xd3d94000,</div><div class='add'>+	0x18000100, 0xd3d94001,</div><div class='add'>+	0x18000101, 0xd3d94002,</div><div class='add'>+	0x18000102, 0xd3d94003,</div><div class='add'>+	0x18000103, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffea,</div><div class='add'>+	0xbf9c0000, 0xe0524000,</div><div class='add'>+	0x6e1d0000, 0xe0524100,</div><div class='add'>+	0x6e1d0100, 0xe0524200,</div><div class='add'>+	0x6e1d0200, 0xe0524300,</div><div class='add'>+	0x6e1d0300, 0xbf8c0f70,</div><div class='add'>+	0xb8f82985, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0x80f8c078, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f846f,</div><div class='add'>+	0x8e76826f, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xbefc006f,</div><div class='add'>+	0xc031003a, 0x00000078,</div><div class='add'>+	0x80f8c078, 0xbf8cc07f,</div><div class='add'>+	0x80fc907c, 0xbf800000,</div><div class='add'>+	0xbe802d00, 0xbe822d02,</div><div class='add'>+	0xbe842d04, 0xbe862d06,</div><div class='add'>+	0xbe882d08, 0xbe8a2d0a,</div><div class='add'>+	0xbe8c2d0c, 0xbe8e2d0e,</div><div class='add'>+	0xbf06807c, 0xbf84fff0,</div><div class='add'>+	0xb8f82985, 0x80788178,</div><div class='add'>+	0x8e788a78, 0x8e788178,</div><div class='add'>+	0xb8ee1605, 0x806e816e,</div><div class='add'>+	0x8e6e866e, 0x80786e78,</div><div class='add'>+	0xbef60084, 0xbef600ff,</div><div class='add'>+	0x01000000, 0xc0211bfa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211b7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211c3a,</div><div class='add'>+	0xc0211b3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211b7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211c7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211eba,</div><div class='add'>+	0xc0211c3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211c7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211efa, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211a3a,</div><div class='add'>+	0xc0211eba, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211efa,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xc0211a7a, 0x00000078,</div><div class='del'>-	0x80788478, 0xc0211cfa,</div><div class='add'>+	0xc0211a3a, 0x00000078,</div><div class='add'>+	0x80788478, 0xc0211a7a,</div><div class='ctx'> 	0x00000078, 0x80788478,</div><div class='del'>-	0xbf8cc07f, 0xbefc006f,</div><div class='del'>-	0xbefe0070, 0xbeff0071,</div><div class='del'>-	0x866f7bff, 0x000003ff,</div><div class='del'>-	0xb96f4803, 0x866f7bff,</div><div class='del'>-	0xfffff800, 0x8f6f8b6f,</div><div class='del'>-	0xb96fa2c3, 0xb973f801,</div><div class='del'>-	0xb8ee2985, 0x806e816e,</div><div class='del'>-	0x8e6e8a6e, 0x8e6e816e,</div><div class='del'>-	0xb8ef1605, 0x806f816f,</div><div class='del'>-	0x8e6f866f, 0x806e6f6e,</div><div class='del'>-	0x806e746e, 0x826f8075,</div><div class='del'>-	0x866fff6f, 0x0000ffff,</div><div class='del'>-	0xc00b1c37, 0x00000050,</div><div class='del'>-	0xc00b1d37, 0x00000060,</div><div class='del'>-	0xc0031e77, 0x00000074,</div><div class='del'>-	0xbf8cc07f, 0x8f6e8b79,</div><div class='del'>-	0x866eff6e, 0x001f8000,</div><div class='del'>-	0xb96ef807, 0x866dff6d,</div><div class='del'>-	0x0000ffff, 0x86fe7e7e,</div><div class='del'>-	0x86ea6a6a, 0x8f6e837a,</div><div class='del'>-	0xb96ee0c2, 0xbf800002,</div><div class='del'>-	0xb97a0002, 0xbf8a0000,</div><div class='del'>-	0xbe801f6c, 0xbf9b0000,</div><div class='add'>+	0xc0211cfa, 0x00000078,</div><div class='add'>+	0x80788478, 0xbf8cc07f,</div><div class='add'>+	0xbefc006f, 0xbefe0070,</div><div class='add'>+	0xbeff0071, 0x866f7bff,</div><div class='add'>+	0x000003ff, 0xb96f4803,</div><div class='add'>+	0x866f7bff, 0xfffff800,</div><div class='add'>+	0x8f6f8b6f, 0xb96fa2c3,</div><div class='add'>+	0xb973f801, 0xb8ee2985,</div><div class='add'>+	0x806e816e, 0x8e6e8a6e,</div><div class='add'>+	0x8e6e816e, 0xb8ef1605,</div><div class='add'>+	0x806f816f, 0x8e6f866f,</div><div class='add'>+	0x806e6f6e, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x866fff6f,</div><div class='add'>+	0x0000ffff, 0xc00b1c37,</div><div class='add'>+	0x00000050, 0xc00b1d37,</div><div class='add'>+	0x00000060, 0xc0031e77,</div><div class='add'>+	0x00000074, 0xbf8cc07f,</div><div class='add'>+	0x8f6e8b79, 0x866eff6e,</div><div class='add'>+	0x001f8000, 0xb96ef807,</div><div class='add'>+	0x866dff6d, 0x0000ffff,</div><div class='add'>+	0x86fe7e7e, 0x86ea6a6a,</div><div class='add'>+	0x8f6e837a, 0xb96ee0c2,</div><div class='add'>+	0xbf800002, 0xb97a0002,</div><div class='add'>+	0xbf8a0000, 0xbe801f6c,</div><div class='add'>+	0xbf9b0000, 0x00000000,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm<br/>index e1aaa5ce0784..96fbb16ceb21 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'>  * gfx11:</div><div class='ctx'>  *   cpp -DASIC_FAMILY=CHIP_PLUM_BONITO cwsr_trap_handler_gfx10.asm -P -o gfx11.sp3</div><div class='ctx'>  *   sp3 gfx11.sp3 -hex gfx11.hex</div><div class='add'>+ *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #define CHIP_NAVI10 26</div><div class='hunk'>@@ -43,23 +44,33 @@</div><div class='ctx'> #define HAVE_XNACK (ASIC_FAMILY &lt; CHIP_SIENNA_CICHLID)</div><div class='ctx'> #define HAVE_SENDMSG_RTN (ASIC_FAMILY &gt;= CHIP_PLUM_BONITO)</div><div class='ctx'> #define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY &lt; CHIP_PLUM_BONITO)</div><div class='del'>-#define SW_SA_TRAP (ASIC_FAMILY &gt;= CHIP_PLUM_BONITO)</div><div class='add'>+#define SW_SA_TRAP (ASIC_FAMILY == CHIP_PLUM_BONITO)</div><div class='ctx'> #define SAVE_AFTER_XNACK_ERROR (HAVE_XNACK &amp;&amp; !NO_SQC_STORE) // workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger</div><div class='add'>+#define SINGLE_STEP_MISSED_WORKAROUND 1	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised</div><div class='ctx'> </div><div class='del'>-var SINGLE_STEP_MISSED_WORKAROUND		= 1	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised</div><div class='add'>+#define S_COHERENCE glc:1</div><div class='add'>+#define V_COHERENCE slc:1 glc:1</div><div class='add'>+#define S_WAITCNT_0 s_waitcnt 0</div><div class='ctx'> </div><div class='ctx'> var SQ_WAVE_STATUS_SPI_PRIO_MASK		= 0x00000006</div><div class='ctx'> var SQ_WAVE_STATUS_HALT_MASK			= 0x2000</div><div class='ctx'> var SQ_WAVE_STATUS_ECC_ERR_MASK			= 0x20000</div><div class='ctx'> var SQ_WAVE_STATUS_TRAP_EN_SHIFT		= 6</div><div class='add'>+var SQ_WAVE_IB_STS2_WAVE64_SHIFT		= 11</div><div class='add'>+var SQ_WAVE_IB_STS2_WAVE64_SIZE			= 1</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_GRANULARITY		= 8</div><div class='add'>+var S_STATUS_HWREG				= HW_REG_STATUS</div><div class='add'>+var S_STATUS_ALWAYS_CLEAR_MASK			= SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK</div><div class='add'>+var S_STATUS_HALT_MASK				= SQ_WAVE_STATUS_HALT_MASK</div><div class='add'>+var S_SAVE_PC_HI_TRAP_ID_MASK			= 0x00FF0000</div><div class='add'>+var S_SAVE_PC_HI_HT_MASK			= 0x01000000</div><div class='ctx'> </div><div class='add'>+var SQ_WAVE_STATUS_NO_VGPRS_SHIFT		= 24</div><div class='ctx'> var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12</div><div class='ctx'> var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9</div><div class='ctx'> var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE		= 8</div><div class='ctx'> var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT	= 24</div><div class='ctx'> var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE	= 4</div><div class='del'>-var SQ_WAVE_IB_STS2_WAVE64_SHIFT		= 11</div><div class='del'>-var SQ_WAVE_IB_STS2_WAVE64_SIZE			= 1</div><div class='ctx'> </div><div class='ctx'> #if ASIC_FAMILY &lt; CHIP_PLUM_BONITO</div><div class='ctx'> var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 8</div><div class='hunk'>@@ -74,16 +85,13 @@ var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK		= 0x80</div><div class='ctx'> var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT		= 7</div><div class='ctx'> var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK		= 0x100</div><div class='ctx'> var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT		= 8</div><div class='del'>-var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK		= 0x3FF</div><div class='del'>-var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT		= 0x0</div><div class='del'>-var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE		= 10</div><div class='del'>-var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK		= 0xFFFFF800</div><div class='del'>-var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT		= 11</div><div class='del'>-var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE		= 21</div><div class='ctx'> var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK		= 0x800</div><div class='add'>+var SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT		= 11</div><div class='ctx'> var SQ_WAVE_TRAPSTS_EXCP_HI_MASK		= 0x7000</div><div class='ctx'> #if ASIC_FAMILY &gt;= CHIP_PLUM_BONITO</div><div class='add'>+var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT		= 16</div><div class='ctx'> var SQ_WAVE_TRAPSTS_WAVE_START_MASK		= 0x20000</div><div class='add'>+var SQ_WAVE_TRAPSTS_WAVE_START_SHIFT		= 17</div><div class='ctx'> var SQ_WAVE_TRAPSTS_WAVE_END_MASK		= 0x40000</div><div class='ctx'> var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK	= 0x100000</div><div class='ctx'> #endif</div><div class='hunk'>@@ -99,15 +107,27 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x003F8000</div><div class='ctx'> </div><div class='ctx'> var SQ_WAVE_MODE_DEBUG_EN_MASK			= 0x800</div><div class='ctx'> </div><div class='add'>+var S_TRAPSTS_RESTORE_PART_1_SIZE		= SQ_WAVE_TRAPSTS_SAVECTX_SHIFT</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_2_SHIFT		= SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT</div><div class='add'>+</div><div class='ctx'> #if ASIC_FAMILY &lt; CHIP_PLUM_BONITO</div><div class='ctx'> var S_TRAPSTS_NON_MASKABLE_EXCP_MASK		= SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_2_SIZE		= 32 - S_TRAPSTS_RESTORE_PART_2_SHIFT</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_3_SHIFT		= 0</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_3_SIZE		= 0</div><div class='ctx'> #else</div><div class='ctx'> var S_TRAPSTS_NON_MASKABLE_EXCP_MASK		= SQ_WAVE_TRAPSTS_MEM_VIOL_MASK		|\</div><div class='ctx'> 						  SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK	|\</div><div class='ctx'> 						  SQ_WAVE_TRAPSTS_WAVE_START_MASK	|\</div><div class='ctx'> 						  SQ_WAVE_TRAPSTS_WAVE_END_MASK		|\</div><div class='ctx'> 						  SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_2_SIZE		= SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT - SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_3_SHIFT		= SQ_WAVE_TRAPSTS_WAVE_START_SHIFT</div><div class='add'>+var S_TRAPSTS_RESTORE_PART_3_SIZE		= 32 - S_TRAPSTS_RESTORE_PART_3_SHIFT</div><div class='ctx'> #endif</div><div class='add'>+var S_TRAPSTS_HWREG				= HW_REG_TRAPSTS</div><div class='add'>+var S_TRAPSTS_SAVE_CONTEXT_MASK			= SQ_WAVE_TRAPSTS_SAVECTX_MASK</div><div class='add'>+var S_TRAPSTS_SAVE_CONTEXT_SHIFT		= SQ_WAVE_TRAPSTS_SAVECTX_SHIFT</div><div class='ctx'> </div><div class='ctx'> // bits [31:24] unused by SPI debug data</div><div class='ctx'> var TTMP11_SAVE_REPLAY_W64H_SHIFT		= 31</div><div class='hunk'>@@ -121,8 +141,6 @@ var TTMP11_DEBUG_TRAP_ENABLED_MASK		= 0x800000</div><div class='ctx'> // when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE</div><div class='ctx'> var S_SAVE_BUF_RSRC_WORD1_STRIDE		= 0x00040000</div><div class='ctx'> var S_SAVE_BUF_RSRC_WORD3_MISC			= 0x10807FAC</div><div class='del'>-var S_SAVE_PC_HI_TRAP_ID_MASK			= 0x00FF0000</div><div class='del'>-var S_SAVE_PC_HI_HT_MASK			= 0x01000000</div><div class='ctx'> var S_SAVE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000</div><div class='ctx'> var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT		= 26</div><div class='ctx'> </div><div class='hunk'>@@ -182,6 +200,7 @@ var s_restore_buf_rsrc3				= ttmp11</div><div class='ctx'> var s_restore_size				= ttmp6</div><div class='ctx'> var s_restore_ttmps_lo				= s_restore_tmp</div><div class='ctx'> var s_restore_ttmps_hi				= s_restore_alloc_size</div><div class='add'>+var s_restore_spi_init_hi_save			= s_restore_exec_hi</div><div class='ctx'> </div><div class='ctx'> shader main</div><div class='ctx'> 	asic(DEFAULT)</div><div class='hunk'>@@ -194,13 +213,13 @@ L_JUMP_TO_RESTORE:</div><div class='ctx'> 	s_branch	L_RESTORE</div><div class='ctx'> </div><div class='ctx'> L_SKIP_RESTORE:</div><div class='del'>-	s_getreg_b32	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC</div><div class='add'>+	s_getreg_b32	s_save_status, hwreg(S_STATUS_HWREG)			//save STATUS since we will change SCC</div><div class='ctx'> </div><div class='ctx'> 	// Clear SPI_PRIO: do not save with elevated priority.</div><div class='ctx'> 	// Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd.</div><div class='del'>-	s_andn2_b32	s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK</div><div class='add'>+	s_andn2_b32	s_save_status, s_save_status, S_STATUS_ALWAYS_CLEAR_MASK</div><div class='ctx'> </div><div class='del'>-	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)</div><div class='add'>+	s_getreg_b32	s_save_trapsts, hwreg(S_TRAPSTS_HWREG)</div><div class='ctx'> </div><div class='ctx'> #if SW_SA_TRAP</div><div class='ctx'> 	// If ttmp1[30] is set then issue s_barrier to unblock dependent waves.</div><div class='hunk'>@@ -215,7 +234,7 @@ L_TRAP_NO_BARRIER:</div><div class='ctx'> 	s_cbranch_scc1  L_CHECK_SAVE</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	s_and_b32       ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK</div><div class='add'>+	s_and_b32       ttmp2, s_save_status, S_STATUS_HALT_MASK</div><div class='ctx'> 	s_cbranch_scc0	L_NOT_HALTED</div><div class='ctx'> </div><div class='ctx'> L_HALTED:</div><div class='hunk'>@@ -224,14 +243,14 @@ L_HALTED:</div><div class='ctx'> 	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='ctx'> </div><div class='ctx'> L_CHECK_SAVE:</div><div class='del'>-	s_and_b32	ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK</div><div class='add'>+	s_and_b32	ttmp2, s_save_trapsts, S_TRAPSTS_SAVE_CONTEXT_MASK</div><div class='ctx'> 	s_cbranch_scc1	L_SAVE</div><div class='ctx'> </div><div class='ctx'> 	// Wave is halted but neither host trap nor SAVECTX is raised.</div><div class='ctx'> 	// Caused by instruction fetch memory violation.</div><div class='ctx'> 	// Spin wait until context saved to prevent interrupt storm.</div><div class='ctx'> 	s_sleep		0x10</div><div class='del'>-	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)</div><div class='add'>+	s_getreg_b32	s_save_trapsts, hwreg(S_TRAPSTS_HWREG)</div><div class='ctx'> 	s_branch	L_CHECK_SAVE</div><div class='ctx'> </div><div class='ctx'> L_NOT_HALTED:</div><div class='hunk'>@@ -265,15 +284,15 @@ L_CHECK_TRAP_ID:</div><div class='ctx'> 	s_and_b32	ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK</div><div class='ctx'> 	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='ctx'> </div><div class='del'>-if SINGLE_STEP_MISSED_WORKAROUND</div><div class='add'>+#if SINGLE_STEP_MISSED_WORKAROUND</div><div class='ctx'> 	// Prioritize single step exception over context save.</div><div class='ctx'> 	// Second-level trap will halt wave and RFE, re-entering for SAVECTX.</div><div class='ctx'> 	s_getreg_b32	ttmp2, hwreg(HW_REG_MODE)</div><div class='ctx'> 	s_and_b32	ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK</div><div class='ctx'> 	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='del'>-end</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='del'>-	s_and_b32	ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK</div><div class='add'>+	s_and_b32	ttmp2, s_save_trapsts, S_TRAPSTS_SAVE_CONTEXT_MASK</div><div class='ctx'> 	s_cbranch_scc1	L_SAVE</div><div class='ctx'> </div><div class='ctx'> L_FETCH_2ND_TRAP:</div><div class='hunk'>@@ -286,7 +305,7 @@ L_FETCH_2ND_TRAP:</div><div class='ctx'> 	// ttmp12 holds SQ_WAVE_STATUS</div><div class='ctx'> #if HAVE_SENDMSG_RTN</div><div class='ctx'> 	s_sendmsg_rtn_b64       [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA)</div><div class='del'>-	s_waitcnt       lgkmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> #else</div><div class='ctx'> 	s_getreg_b32	ttmp14, hwreg(HW_REG_SHADER_TMA_LO)</div><div class='ctx'> 	s_getreg_b32	ttmp15, hwreg(HW_REG_SHADER_TMA_HI)</div><div class='hunk'>@@ -298,16 +317,16 @@ L_FETCH_2ND_TRAP:</div><div class='ctx'> 	s_or_b32	ttmp15, ttmp15, 0xFFFF0000</div><div class='ctx'> L_NO_SIGN_EXTEND_TMA:</div><div class='ctx'> </div><div class='del'>-	s_load_dword    ttmp2, [ttmp14, ttmp15], 0x10 glc:1			// debug trap enabled flag</div><div class='del'>-	s_waitcnt       lgkmcnt(0)</div><div class='add'>+	s_load_dword    ttmp2, [ttmp14, ttmp15], 0x10 S_COHERENCE		// debug trap enabled flag</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> 	s_lshl_b32      ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT</div><div class='ctx'> 	s_andn2_b32     ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK</div><div class='ctx'> 	s_or_b32        ttmp11, ttmp11, ttmp2</div><div class='ctx'> </div><div class='del'>-	s_load_dwordx2	[ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1		// second-level TBA</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='del'>-	s_load_dwordx2	[ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1		// second-level TMA</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	s_load_dwordx2	[ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 S_COHERENCE	// second-level TBA</div><div class='add'>+	S_WAITCNT_0</div><div class='add'>+	s_load_dwordx2	[ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 S_COHERENCE	// second-level TMA</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_and_b64	[ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3]</div><div class='ctx'> 	s_cbranch_scc0	L_NO_NEXT_TRAP						// second-level trap handler not been set</div><div class='hunk'>@@ -315,9 +334,13 @@ L_NO_SIGN_EXTEND_TMA:</div><div class='ctx'> </div><div class='ctx'> L_NO_NEXT_TRAP:</div><div class='ctx'> 	// If not caused by trap then halt wave to prevent re-entry.</div><div class='del'>-	s_and_b32	ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK)</div><div class='add'>+	s_and_b32	ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK</div><div class='ctx'> 	s_cbranch_scc1	L_TRAP_CASE</div><div class='del'>-	s_or_b32	s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK</div><div class='add'>+</div><div class='add'>+	// Host trap will not cause trap re-entry.</div><div class='add'>+	s_and_b32	ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK</div><div class='add'>+	s_cbranch_scc1	L_EXIT_TRAP</div><div class='add'>+	s_or_b32	s_save_status, s_save_status, S_STATUS_HALT_MASK</div><div class='ctx'> </div><div class='ctx'> 	// If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set.</div><div class='ctx'> 	// Rewind the PC to prevent this from occurring.</div><div class='hunk'>@@ -327,10 +350,6 @@ L_NO_NEXT_TRAP:</div><div class='ctx'> 	s_branch	L_EXIT_TRAP</div><div class='ctx'> </div><div class='ctx'> L_TRAP_CASE:</div><div class='del'>-	// Host trap will not cause trap re-entry.</div><div class='del'>-	s_and_b32	ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK</div><div class='del'>-	s_cbranch_scc1	L_EXIT_TRAP</div><div class='del'>-</div><div class='ctx'> 	// Advance past trap instruction to prevent re-entry.</div><div class='ctx'> 	s_add_u32	ttmp0, ttmp0, 0x4</div><div class='ctx'> 	s_addc_u32	ttmp1, ttmp1, 0x0</div><div class='hunk'>@@ -345,14 +364,22 @@ L_EXIT_TRAP:</div><div class='ctx'> 	// Restore SQ_WAVE_STATUS.</div><div class='ctx'> 	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32</div><div class='ctx'> 	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32</div><div class='del'>-	s_setreg_b32	hwreg(HW_REG_STATUS), s_save_status</div><div class='ctx'> </div><div class='add'>+	s_setreg_b32	hwreg(S_STATUS_HWREG), s_save_status</div><div class='ctx'> 	s_rfe_b64	[ttmp0, ttmp1]</div><div class='ctx'> </div><div class='ctx'> L_SAVE:</div><div class='add'>+	// If VGPRs have been deallocated then terminate the wavefront.</div><div class='add'>+	// It has no remaining program to run and cannot save without VGPRs.</div><div class='add'>+#if ASIC_FAMILY == CHIP_PLUM_BONITO</div><div class='add'>+	s_bitcmp1_b32	s_save_status, SQ_WAVE_STATUS_NO_VGPRS_SHIFT</div><div class='add'>+	s_cbranch_scc0	L_HAVE_VGPRS</div><div class='add'>+	s_endpgm</div><div class='add'>+L_HAVE_VGPRS:</div><div class='add'>+#endif</div><div class='ctx'> 	s_and_b32	s_save_pc_hi, s_save_pc_hi, 0x0000ffff			//pc[47:32]</div><div class='ctx'> 	s_mov_b32	s_save_tmp, 0</div><div class='del'>-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp	//clear saveCtx bit</div><div class='add'>+	s_setreg_b32	hwreg(S_TRAPSTS_HWREG, S_TRAPSTS_SAVE_CONTEXT_SHIFT, 1), s_save_tmp	//clear saveCtx bit</div><div class='ctx'> </div><div class='ctx'> #if HAVE_XNACK</div><div class='ctx'> 	save_and_clear_ib_sts(s_save_tmp, s_save_trapsts)</div><div class='hunk'>@@ -377,7 +404,7 @@ L_SLEEP:</div><div class='ctx'> 	s_sleep		0x2</div><div class='ctx'> 	s_cbranch_execz	L_SLEEP</div><div class='ctx'> #else</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	// Save first_wave flag so we can clear high bits of save address.</div><div class='hunk'>@@ -399,7 +426,7 @@ L_SLEEP:</div><div class='ctx'> 	s_and_b32	s_save_ttmps_hi, exec_hi, 0xFFFF</div><div class='ctx'> 	s_mov_b32	exec_lo, 0xFFFFFFFF</div><div class='ctx'> 	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='del'>-	global_store_dword_addtid	v0, [s_save_ttmps_lo, s_save_ttmps_hi] slc:1 glc:1</div><div class='add'>+	global_store_dword_addtid	v0, [s_save_ttmps_lo, s_save_ttmps_hi] V_COHERENCE</div><div class='ctx'> 	v_mov_b32	v0, 0x0</div><div class='ctx'> 	s_mov_b32	exec_lo, s_save_ttmps_lo</div><div class='ctx'> 	s_mov_b32	exec_hi, s_save_ttmps_hi</div><div class='hunk'>@@ -407,7 +434,7 @@ L_SLEEP:</div><div class='ctx'> </div><div class='ctx'> 	// Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic</div><div class='ctx'> 	// ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40</div><div class='del'>-	get_wave_size(s_save_ttmps_hi)</div><div class='add'>+	get_wave_size2(s_save_ttmps_hi)</div><div class='ctx'> 	get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi)</div><div class='ctx'> 	get_svgpr_size_bytes(s_save_ttmps_hi)</div><div class='ctx'> 	s_add_u32	s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi</div><div class='hunk'>@@ -431,15 +458,15 @@ L_SLEEP:</div><div class='ctx'> </div><div class='ctx'> 	s_mov_b32	exec_lo, 0x3FFF</div><div class='ctx'> 	s_mov_b32	exec_hi, 0x0</div><div class='del'>-	global_store_dword_addtid	v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 slc:1 glc:1</div><div class='add'>+	global_store_dword_addtid	v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 V_COHERENCE</div><div class='ctx'> 	v_readlane_b32	ttmp14, v0, 0xE</div><div class='ctx'> 	v_readlane_b32	ttmp15, v0, 0xF</div><div class='ctx'> 	s_mov_b32	exec_lo, ttmp14</div><div class='ctx'> 	s_mov_b32	exec_hi, ttmp15</div><div class='ctx'> #else</div><div class='del'>-	s_store_dwordx4	[ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1</div><div class='del'>-	s_store_dwordx4	[ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1</div><div class='del'>-	s_store_dword   ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1</div><div class='add'>+	s_store_dwordx4	[ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 S_COHERENCE</div><div class='add'>+	s_store_dwordx4	[ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 S_COHERENCE</div><div class='add'>+	s_store_dword   ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 S_COHERENCE</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	/* setup Resource Contants */</div><div class='hunk'>@@ -453,7 +480,7 @@ L_SLEEP:</div><div class='ctx'> </div><div class='ctx'> 	/* global mem offset */</div><div class='ctx'> 	s_mov_b32	s_save_mem_offset, 0x0</div><div class='del'>-	get_wave_size(s_wave_size)</div><div class='add'>+	get_wave_size2(s_wave_size)</div><div class='ctx'> </div><div class='ctx'> #if HAVE_XNACK</div><div class='ctx'> 	// Save and clear vector XNACK state late to free up SGPRs.</div><div class='hunk'>@@ -488,11 +515,11 @@ L_SAVE_FIRST_VGPRS32_WITH_TCP:</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #if !NO_SQC_STORE</div><div class='del'>-	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> #endif</div><div class='del'>-	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128</div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2</div><div class='del'>-	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3</div><div class='ctx'> 	s_branch	L_SAVE_HWREG</div><div class='ctx'> </div><div class='ctx'> L_SAVE_4VGPR_WAVE64:</div><div class='hunk'>@@ -511,11 +538,11 @@ L_SAVE_FIRST_VGPRS64_WITH_TCP:</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #if !NO_SQC_STORE</div><div class='del'>-	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> #endif</div><div class='del'>-	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256</div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2</div><div class='del'>-	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3</div><div class='ctx'> </div><div class='ctx'> 	/* save HW registers */</div><div class='ctx'> </div><div class='hunk'>@@ -543,7 +570,7 @@ L_SAVE_HWREG:</div><div class='ctx'> 	write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> 	write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='del'>-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_TRAPSTS)</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(S_TRAPSTS_HWREG)</div><div class='ctx'> 	write_hwreg_to_mem(s_save_tmp, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='ctx'> 	// Not used on Sienna_Cichlid but keep layout same for debugger.</div><div class='hunk'>@@ -562,7 +589,7 @@ L_SAVE_HWREG:</div><div class='ctx'> 	// Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this.</div><div class='ctx'> 	s_mov_b32       exec_lo, 0xFFFF</div><div class='ctx'> 	s_mov_b32	exec_hi, 0x0</div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> </div><div class='ctx'> 	// Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode.</div><div class='ctx'> 	s_mov_b32       exec_lo, 0xFFFFFFFF</div><div class='hunk'>@@ -605,7 +632,7 @@ L_SAVE_SGPR_LOOP:</div><div class='ctx'> 	s_cmp_eq_u32	ttmp13, 0x20						//have 32 VGPR lanes filled?</div><div class='ctx'> 	s_cbranch_scc0	L_SAVE_SGPR_SKIP_TCP_STORE</div><div class='ctx'> </div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> 	s_add_u32	s_save_mem_offset, s_save_mem_offset, 0x80</div><div class='ctx'> 	s_mov_b32	ttmp13, 0x0</div><div class='ctx'> 	v_mov_b32	v2, 0x0</div><div class='hunk'>@@ -626,7 +653,7 @@ L_SAVE_SGPR_SKIP_TCP_STORE:</div><div class='ctx'> 	write_12sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='ctx'> #if NO_SQC_STORE</div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> #else</div><div class='ctx'> 	// restore s_save_buf_rsrc0,1</div><div class='ctx'> 	s_mov_b32	s_save_buf_rsrc0, s_save_xnack_mask</div><div class='hunk'>@@ -656,8 +683,7 @@ L_SAVE_LDS_NORMAL:</div><div class='ctx'> </div><div class='ctx'> 	// first wave do LDS save;</div><div class='ctx'> </div><div class='del'>-	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 6			//LDS size in dwords = lds_size * 64dw</div><div class='del'>-	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 2			//LDS size in bytes</div><div class='add'>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY</div><div class='ctx'> 	s_mov_b32	s_save_buf_rsrc2, s_save_alloc_size			//NUM_RECORDS in bytes</div><div class='ctx'> </div><div class='ctx'> 	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)</div><div class='hunk'>@@ -688,7 +714,7 @@ L_SAVE_LDS_W32:</div><div class='ctx'> </div><div class='ctx'> L_SAVE_LDS_LOOP_SQC_W32:</div><div class='ctx'> 	ds_read_b32	v1, v0</div><div class='del'>-	s_waitcnt	0</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	write_vgprs_to_mem_with_sqc_w32(v1, 1, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='hunk'>@@ -708,8 +734,8 @@ L_SAVE_LDS_WITH_TCP_W32:</div><div class='ctx'> 	s_nop		0</div><div class='ctx'> L_SAVE_LDS_LOOP_W32:</div><div class='ctx'> 	ds_read_b32	v1, v0</div><div class='del'>-	s_waitcnt	0</div><div class='del'>-	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	S_WAITCNT_0</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> </div><div class='ctx'> 	s_add_u32	m0, m0, s3						//every buffer_store_lds does 128 bytes</div><div class='ctx'> 	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3</div><div class='hunk'>@@ -726,7 +752,7 @@ L_SAVE_LDS_W64:</div><div class='ctx'> </div><div class='ctx'> L_SAVE_LDS_LOOP_SQC_W64:</div><div class='ctx'> 	ds_read_b32	v1, v0</div><div class='del'>-	s_waitcnt	0</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	write_vgprs_to_mem_with_sqc_w64(v1, 1, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='hunk'>@@ -746,8 +772,8 @@ L_SAVE_LDS_WITH_TCP_W64:</div><div class='ctx'> 	s_nop		0</div><div class='ctx'> L_SAVE_LDS_LOOP_W64:</div><div class='ctx'> 	ds_read_b32	v1, v0</div><div class='del'>-	s_waitcnt	0</div><div class='del'>-	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	S_WAITCNT_0</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> </div><div class='ctx'> 	s_add_u32	m0, m0, s3						//every buffer_store_lds does 256 bytes</div><div class='ctx'> 	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3</div><div class='hunk'>@@ -814,10 +840,10 @@ L_SAVE_VGPR_W32_LOOP:</div><div class='ctx'> 	v_movrels_b32	v2, v2							//v2 = v[2+m0]</div><div class='ctx'> 	v_movrels_b32	v3, v3							//v3 = v[3+m0]</div><div class='ctx'> </div><div class='del'>-	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='del'>-	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128</div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2</div><div class='del'>-	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3</div><div class='ctx'> </div><div class='ctx'> 	s_add_u32	m0, m0, 4						//next vgpr index</div><div class='ctx'> 	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128*4		//every buffer_store_dword does 128 bytes</div><div class='hunk'>@@ -859,10 +885,10 @@ L_SAVE_VGPR_W64_LOOP:</div><div class='ctx'> 	v_movrels_b32	v2, v2							//v2 = v[2+m0]</div><div class='ctx'> 	v_movrels_b32	v3, v3							//v3 = v[3+m0]</div><div class='ctx'> </div><div class='del'>-	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='del'>-	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256</div><div class='del'>-	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2</div><div class='del'>-	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3</div><div class='ctx'> </div><div class='ctx'> 	s_add_u32	m0, m0, 4						//next vgpr index</div><div class='ctx'> 	s_add_u32	s_save_mem_offset, s_save_mem_offset, 256*4		//every buffer_store_dword does 256 bytes</div><div class='hunk'>@@ -899,7 +925,7 @@ L_SAVE_SHARED_VGPR_WAVE64_LOOP_SQC:</div><div class='ctx'> </div><div class='ctx'> L_SAVE_SHARED_VGPR_WAVE64_LOOP:</div><div class='ctx'> 	v_movrels_b32	v0, v0							//v0 = v[0+m0]</div><div class='del'>-	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE</div><div class='ctx'> 	s_add_u32	m0, m0, 1						//next vgpr index</div><div class='ctx'> 	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128</div><div class='ctx'> 	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 &lt; s_save_alloc_size) ? 1 : 0</div><div class='hunk'>@@ -917,7 +943,7 @@ L_RESTORE:</div><div class='ctx'> 	s_mov_b32	s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC</div><div class='ctx'> </div><div class='ctx'> 	//determine it is wave32 or wave64</div><div class='del'>-	get_wave_size(s_restore_size)</div><div class='add'>+	get_wave_size2(s_restore_size)</div><div class='ctx'> </div><div class='ctx'> 	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK</div><div class='ctx'> 	s_cbranch_scc0	L_RESTORE_VGPR</div><div class='hunk'>@@ -937,8 +963,7 @@ L_RESTORE_LDS_NORMAL:</div><div class='ctx'> 	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)</div><div class='ctx'> 	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//lds_size is zero?</div><div class='ctx'> 	s_cbranch_scc0	L_RESTORE_VGPR						//no lds used? jump to L_RESTORE_VGPR</div><div class='del'>-	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 6		//LDS size in dwords = lds_size * 64dw</div><div class='del'>-	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 2		//LDS size in bytes</div><div class='add'>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY</div><div class='ctx'> 	s_mov_b32	s_restore_buf_rsrc2, s_restore_alloc_size		//NUM_RECORDS in bytes</div><div class='ctx'> </div><div class='ctx'> 	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)</div><div class='hunk'>@@ -962,7 +987,7 @@ L_RESTORE_LDS_LOOP_W32:</div><div class='ctx'> 	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1	// first 64DW</div><div class='ctx'> #else</div><div class='ctx'> 	buffer_load_dword       v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> 	ds_store_addtid_b32     v0</div><div class='ctx'> #endif</div><div class='ctx'> 	s_add_u32	m0, m0, 128						// 128 DW</div><div class='hunk'>@@ -976,7 +1001,7 @@ L_RESTORE_LDS_LOOP_W64:</div><div class='ctx'> 	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1	// first 64DW</div><div class='ctx'> #else</div><div class='ctx'> 	buffer_load_dword       v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> 	ds_store_addtid_b32     v0</div><div class='ctx'> #endif</div><div class='ctx'> 	s_add_u32	m0, m0, 256						// 256 DW</div><div class='hunk'>@@ -1017,11 +1042,11 @@ L_RESTORE_VGPR_NORMAL:</div><div class='ctx'> 	s_cbranch_scc0	L_RESTORE_SGPR</div><div class='ctx'> </div><div class='ctx'> L_RESTORE_VGPR_WAVE32_LOOP:</div><div class='del'>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1</div><div class='del'>-	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128</div><div class='del'>-	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*2</div><div class='del'>-	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*3</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> 	v_movreld_b32	v0, v0							//v[0+m0] = v0</div><div class='ctx'> 	v_movreld_b32	v1, v1</div><div class='ctx'> 	v_movreld_b32	v2, v2</div><div class='hunk'>@@ -1032,11 +1057,11 @@ L_RESTORE_VGPR_WAVE32_LOOP:</div><div class='ctx'> 	s_cbranch_scc1	L_RESTORE_VGPR_WAVE32_LOOP				//VGPR restore (except v0) is complete?</div><div class='ctx'> </div><div class='ctx'> 	/* VGPR restore on v0 */</div><div class='del'>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1</div><div class='del'>-	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128</div><div class='del'>-	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2</div><div class='del'>-	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128*3</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_branch	L_RESTORE_SGPR</div><div class='ctx'> </div><div class='hunk'>@@ -1051,11 +1076,11 @@ L_RESTORE_VGPR_WAVE64:</div><div class='ctx'> 	s_cbranch_scc0	L_RESTORE_SHARED_VGPR</div><div class='ctx'> </div><div class='ctx'> L_RESTORE_VGPR_WAVE64_LOOP:</div><div class='del'>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1</div><div class='del'>-	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256</div><div class='del'>-	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2</div><div class='del'>-	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256*3</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> 	v_movreld_b32	v0, v0							//v[0+m0] = v0</div><div class='ctx'> 	v_movreld_b32	v1, v1</div><div class='ctx'> 	v_movreld_b32	v2, v2</div><div class='hunk'>@@ -1077,8 +1102,8 @@ L_RESTORE_SHARED_VGPR:</div><div class='ctx'> 	s_mov_b32	exec_lo, 0xFFFFFFFF</div><div class='ctx'> 	s_mov_b32	exec_hi, 0x00000000</div><div class='ctx'> L_RESTORE_SHARED_VGPR_WAVE64_LOOP:</div><div class='del'>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> 	v_movreld_b32	v0, v0							//v[0+m0] = v0</div><div class='ctx'> 	s_add_u32	m0, m0, 1						//next vgpr index</div><div class='ctx'> 	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128</div><div class='hunk'>@@ -1089,11 +1114,11 @@ L_RESTORE_SHARED_VGPR_WAVE64_LOOP:</div><div class='ctx'> </div><div class='ctx'> 	/* VGPR restore on v0 */</div><div class='ctx'> L_RESTORE_V0:</div><div class='del'>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1</div><div class='del'>-	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256</div><div class='del'>-	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2</div><div class='del'>-	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3</div><div class='del'>-	s_waitcnt	vmcnt(0)</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256*3</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	/* restore SGPRs */</div><div class='ctx'> 	//will be 2+8+16*6</div><div class='hunk'>@@ -1110,7 +1135,7 @@ L_RESTORE_SGPR:</div><div class='ctx'> 	s_mov_b32	m0, s_sgpr_save_num</div><div class='ctx'> </div><div class='ctx'> 	read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_sub_u32	m0, m0, 4						// Restore from S[0] to S[104]</div><div class='ctx'> 	s_nop		0							// hazard SALU M0=&gt; S_MOVREL</div><div class='hunk'>@@ -1119,7 +1144,7 @@ L_RESTORE_SGPR:</div><div class='ctx'> 	s_movreld_b64	s2, s2</div><div class='ctx'> </div><div class='ctx'> 	read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_sub_u32	m0, m0, 8						// Restore from S[0] to S[96]</div><div class='ctx'> 	s_nop		0							// hazard SALU M0=&gt; S_MOVREL</div><div class='hunk'>@@ -1131,7 +1156,7 @@ L_RESTORE_SGPR:</div><div class='ctx'> </div><div class='ctx'>  L_RESTORE_SGPR_LOOP:</div><div class='ctx'> 	read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_sub_u32	m0, m0, 16						// Restore from S[n] to S[0]</div><div class='ctx'> 	s_nop		0							// hazard SALU M0=&gt; S_MOVREL</div><div class='hunk'>@@ -1173,12 +1198,12 @@ L_RESTORE_HWREG:</div><div class='ctx'> 	read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='ctx'> 	read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='ctx'> 	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_setreg_b32	hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO), s_restore_flat_scratch</div><div class='ctx'> </div><div class='ctx'> 	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='del'>-	s_waitcnt	lgkmcnt(0)						//from now on, it is safe to restore STATUS and IB_STS</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> 	s_setreg_b32	hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI), s_restore_flat_scratch</div><div class='ctx'> </div><div class='hunk'>@@ -1186,16 +1211,21 @@ L_RESTORE_HWREG:</div><div class='ctx'> 	s_mov_b32	exec_lo, s_restore_exec_lo</div><div class='ctx'> 	s_mov_b32	exec_hi, s_restore_exec_hi</div><div class='ctx'> </div><div class='del'>-	s_and_b32	s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts</div><div class='del'>-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0</div><div class='del'>-</div><div class='ctx'> #if HAVE_XNACK</div><div class='ctx'> 	s_setreg_b32	hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	s_and_b32	s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts</div><div class='del'>-	s_lshr_b32	s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT</div><div class='del'>-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0</div><div class='add'>+	// {TRAPSTS/EXCP_FLAG_PRIV}.SAVE_CONTEXT and HOST_TRAP may have changed.</div><div class='add'>+	// Only restore the other fields to avoid clobbering them.</div><div class='add'>+	s_setreg_b32	hwreg(S_TRAPSTS_HWREG, 0, S_TRAPSTS_RESTORE_PART_1_SIZE), s_restore_trapsts</div><div class='add'>+	s_lshr_b32	s_restore_trapsts, s_restore_trapsts, S_TRAPSTS_RESTORE_PART_2_SHIFT</div><div class='add'>+	s_setreg_b32	hwreg(S_TRAPSTS_HWREG, S_TRAPSTS_RESTORE_PART_2_SHIFT, S_TRAPSTS_RESTORE_PART_2_SIZE), s_restore_trapsts</div><div class='add'>+</div><div class='add'>+if S_TRAPSTS_RESTORE_PART_3_SIZE &gt; 0</div><div class='add'>+	s_lshr_b32	s_restore_trapsts, s_restore_trapsts, S_TRAPSTS_RESTORE_PART_3_SHIFT - S_TRAPSTS_RESTORE_PART_2_SHIFT</div><div class='add'>+	s_setreg_b32	hwreg(S_TRAPSTS_HWREG, S_TRAPSTS_RESTORE_PART_3_SHIFT, S_TRAPSTS_RESTORE_PART_3_SIZE), s_restore_trapsts</div><div class='add'>+end</div><div class='add'>+</div><div class='ctx'> 	s_setreg_b32	hwreg(HW_REG_MODE), s_restore_mode</div><div class='ctx'> </div><div class='ctx'> 	// Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic</div><div class='hunk'>@@ -1207,10 +1237,10 @@ L_RESTORE_HWREG:</div><div class='ctx'> 	s_add_u32	s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0</div><div class='ctx'> 	s_addc_u32	s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0</div><div class='ctx'> 	s_and_b32	s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF</div><div class='del'>-	s_load_dwordx4	[ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1</div><div class='del'>-	s_load_dwordx4	[ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1</div><div class='del'>-	s_load_dword	ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1</div><div class='del'>-	s_waitcnt	lgkmcnt(0)</div><div class='add'>+	s_load_dwordx4	[ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 S_COHERENCE</div><div class='add'>+	s_load_dwordx4	[ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 S_COHERENCE</div><div class='add'>+	s_load_dword	ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 S_COHERENCE</div><div class='add'>+	S_WAITCNT_0</div><div class='ctx'> </div><div class='ctx'> #if HAVE_XNACK</div><div class='ctx'> 	restore_ib_sts(s_restore_tmp, s_restore_m0)</div><div class='hunk'>@@ -1232,7 +1262,8 @@ L_RESTORE_HWREG:</div><div class='ctx'> L_RETURN_WITHOUT_PRIV:</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	s_setreg_b32	hwreg(HW_REG_STATUS), s_restore_status			// SCC is included, which is changed by previous salu</div><div class='add'>+	s_setreg_b32	hwreg(S_STATUS_HWREG), s_restore_status			// SCC is included, which is changed by previous salu</div><div class='add'>+</div><div class='ctx'> 	s_rfe_b64	s_restore_pc_lo						//Return to the main shader program and resume execution</div><div class='ctx'> </div><div class='ctx'> L_END_PGM:</div><div class='hunk'>@@ -1247,7 +1278,7 @@ function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)</div><div class='ctx'> #else</div><div class='ctx'> 	s_mov_b32	exec_lo, m0</div><div class='ctx'> 	s_mov_b32	m0, s_mem_offset</div><div class='del'>-	s_buffer_store_dword	s, s_rsrc, m0 glc:1</div><div class='add'>+	s_buffer_store_dword	s, s_rsrc, m0 S_COHERENCE</div><div class='ctx'> 	s_add_u32	s_mem_offset, s_mem_offset, 4</div><div class='ctx'> 	s_mov_b32	m0, exec_lo</div><div class='ctx'> #endif</div><div class='hunk'>@@ -1262,10 +1293,10 @@ function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)</div><div class='ctx'> 		s_add_u32	ttmp13, ttmp13, 0x1</div><div class='ctx'> 	end</div><div class='ctx'> #else</div><div class='del'>-	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1</div><div class='del'>-	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1</div><div class='del'>-	s_buffer_store_dwordx4	s[8], s_rsrc, 32 glc:1</div><div class='del'>-	s_buffer_store_dwordx4	s[12], s_rsrc, 48 glc:1</div><div class='add'>+	s_buffer_store_dwordx4	s[0], s_rsrc, 0 S_COHERENCE</div><div class='add'>+	s_buffer_store_dwordx4	s[4], s_rsrc, 16 S_COHERENCE</div><div class='add'>+	s_buffer_store_dwordx4	s[8], s_rsrc, 32 S_COHERENCE</div><div class='add'>+	s_buffer_store_dwordx4	s[12], s_rsrc, 48 S_COHERENCE</div><div class='ctx'> 	s_add_u32	s_rsrc[0], s_rsrc[0], 4*16</div><div class='ctx'> 	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0</div><div class='ctx'> #endif</div><div class='hunk'>@@ -1279,32 +1310,32 @@ function write_12sgpr_to_mem(s, s_rsrc, s_mem_offset)</div><div class='ctx'> 		s_add_u32	ttmp13, ttmp13, 0x1</div><div class='ctx'> 	end</div><div class='ctx'> #else</div><div class='del'>-	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1</div><div class='del'>-	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1</div><div class='del'>-	s_buffer_store_dwordx4	s[8], s_rsrc, 32 glc:1</div><div class='add'>+	s_buffer_store_dwordx4	s[0], s_rsrc, 0 S_COHERENCE</div><div class='add'>+	s_buffer_store_dwordx4	s[4], s_rsrc, 16 S_COHERENCE</div><div class='add'>+	s_buffer_store_dwordx4	s[8], s_rsrc, 32 S_COHERENCE</div><div class='ctx'> 	s_add_u32	s_rsrc[0], s_rsrc[0], 4*12</div><div class='ctx'> 	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0</div><div class='ctx'> #endif</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)</div><div class='del'>-	s_buffer_load_dword	s, s_rsrc, s_mem_offset glc:1</div><div class='add'>+	s_buffer_load_dword	s, s_rsrc, s_mem_offset S_COHERENCE</div><div class='ctx'> 	s_add_u32	s_mem_offset, s_mem_offset, 4</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)</div><div class='ctx'> 	s_sub_u32	s_mem_offset, s_mem_offset, 4*16</div><div class='del'>-	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset glc:1</div><div class='add'>+	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset S_COHERENCE</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset)</div><div class='ctx'> 	s_sub_u32	s_mem_offset, s_mem_offset, 4*8</div><div class='del'>-	s_buffer_load_dwordx8	s, s_rsrc, s_mem_offset glc:1</div><div class='add'>+	s_buffer_load_dwordx8	s, s_rsrc, s_mem_offset S_COHERENCE</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset)</div><div class='ctx'> 	s_sub_u32	s_mem_offset, s_mem_offset, 4*4</div><div class='del'>-	s_buffer_load_dwordx4	s, s_rsrc, s_mem_offset glc:1</div><div class='add'>+	s_buffer_load_dwordx4	s, s_rsrc, s_mem_offset S_COHERENCE</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> #if SAVE_AFTER_XNACK_ERROR</div><div class='hunk'>@@ -1345,11 +1376,6 @@ function write_vgprs_to_mem_with_sqc_w64(vgpr0, n_vgprs, s_rsrc, s_mem_offset)</div><div class='ctx'> end</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-function get_lds_size_bytes(s_lds_size_byte)</div><div class='del'>-	s_getreg_b32	s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)</div><div class='del'>-	s_lshl_b32	s_lds_size_byte, s_lds_size_byte, 8			//LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW</div><div class='del'>-end</div><div class='del'>-</div><div class='ctx'> function get_vgpr_size_bytes(s_vgpr_size_byte, s_size)</div><div class='ctx'> 	s_getreg_b32	s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)</div><div class='ctx'> 	s_add_u32	s_vgpr_size_byte, s_vgpr_size_byte, 1</div><div class='hunk'>@@ -1375,11 +1401,12 @@ function get_hwreg_size_bytes</div><div class='ctx'> 	return 128</div><div class='ctx'> end</div><div class='ctx'> </div><div class='del'>-function get_wave_size(s_reg)</div><div class='add'>+function get_wave_size2(s_reg)</div><div class='ctx'> 	s_getreg_b32	s_reg, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)</div><div class='ctx'> 	s_lshl_b32	s_reg, s_reg, S_WAVE_SIZE</div><div class='ctx'> end</div><div class='ctx'> </div><div class='add'>+#if HAVE_XNACK</div><div class='ctx'> function save_and_clear_ib_sts(tmp1, tmp2)</div><div class='ctx'> 	// Preserve and clear scalar XNACK state before issuing scalar loads.</div><div class='ctx'> 	// Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into</div><div class='hunk'>@@ -1404,3 +1431,4 @@ function restore_ib_sts(tmp1, tmp2)</div><div class='ctx'> 	s_or_b32	tmp1, tmp1, tmp2</div><div class='ctx'> 	s_setreg_b32	hwreg(HW_REG_IB_STS), tmp1</div><div class='ctx'> end</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm<br/>new file mode 100644<br/>index 000000000000..5a1a1b1f897f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm</a></div><div class='hunk'>@@ -0,0 +1,1136 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* To compile this assembly code:</div><div class='add'>+ *</div><div class='add'>+ * gfx12:</div><div class='add'>+ *   cpp -DASIC_FAMILY=CHIP_GFX12 cwsr_trap_handler_gfx12.asm -P -o gfx12.sp3</div><div class='add'>+ *   sp3 gfx12.sp3 -hex gfx12.hex</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CHIP_GFX12 37</div><div class='add'>+</div><div class='add'>+#define SINGLE_STEP_MISSED_WORKAROUND 1	//workaround for lost TRAP_AFTER_INST exception when SAVECTX raised</div><div class='add'>+#define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12)</div><div class='add'>+</div><div class='add'>+var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK	= 0x4</div><div class='add'>+var SQ_WAVE_STATE_PRIV_SCC_SHIFT		= 9</div><div class='add'>+var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK		= 0xC00</div><div class='add'>+var SQ_WAVE_STATE_PRIV_HALT_MASK		= 0x4000</div><div class='add'>+var SQ_WAVE_STATE_PRIV_POISON_ERR_MASK		= 0x8000</div><div class='add'>+var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT		= 15</div><div class='add'>+var SQ_WAVE_STATUS_WAVE64_SHIFT			= 29</div><div class='add'>+var SQ_WAVE_STATUS_WAVE64_SIZE			= 1</div><div class='add'>+var SQ_WAVE_STATUS_NO_VGPRS_SHIFT		= 24</div><div class='add'>+var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK	= SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK</div><div class='add'>+var S_SAVE_PC_HI_TRAP_ID_MASK			= 0xF0000000</div><div class='add'>+</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9</div><div class='add'>+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE		= 8</div><div class='add'>+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 12</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT	= 24</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE	= 4</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_GRANULARITY		= 9</div><div class='add'>+</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK	= 0xF</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK	= 0x10</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT	= 5</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK	= 0x20</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK	= 0x40</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT	= 6</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK	= 0x80</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT	= 7</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK	= 0x100</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT	= 8</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK	= 0x200</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK	= 0x800</div><div class='add'>+var SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK		= 0x80</div><div class='add'>+var SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK	= 0x200</div><div class='add'>+</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK= SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK		|\</div><div class='add'>+						  SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK	|\</div><div class='add'>+						  SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK		|\</div><div class='add'>+						  SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK	|\</div><div class='add'>+						  SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK		|\</div><div class='add'>+						  SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE	= SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT	= SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE	= SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT	= SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT</div><div class='add'>+var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE	= 32 - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT</div><div class='add'>+var BARRIER_STATE_SIGNAL_OFFSET			= 16</div><div class='add'>+var BARRIER_STATE_VALID_OFFSET			= 0</div><div class='add'>+</div><div class='add'>+var TTMP11_DEBUG_TRAP_ENABLED_SHIFT		= 23</div><div class='add'>+var TTMP11_DEBUG_TRAP_ENABLED_MASK		= 0x800000</div><div class='add'>+</div><div class='add'>+// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14]</div><div class='add'>+// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE</div><div class='add'>+var S_SAVE_BUF_RSRC_WORD1_STRIDE		= 0x00040000</div><div class='add'>+var S_SAVE_BUF_RSRC_WORD3_MISC			= 0x10807FAC</div><div class='add'>+var S_SAVE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000</div><div class='add'>+var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT		= 26</div><div class='add'>+</div><div class='add'>+var S_SAVE_PC_HI_FIRST_WAVE_MASK		= 0x80000000</div><div class='add'>+var S_SAVE_PC_HI_FIRST_WAVE_SHIFT		= 31</div><div class='add'>+</div><div class='add'>+var s_sgpr_save_num				= 108</div><div class='add'>+</div><div class='add'>+var s_save_spi_init_lo				= exec_lo</div><div class='add'>+var s_save_spi_init_hi				= exec_hi</div><div class='add'>+var s_save_pc_lo				= ttmp0</div><div class='add'>+var s_save_pc_hi				= ttmp1</div><div class='add'>+var s_save_exec_lo				= ttmp2</div><div class='add'>+var s_save_exec_hi				= ttmp3</div><div class='add'>+var s_save_state_priv				= ttmp12</div><div class='add'>+var s_save_excp_flag_priv			= ttmp15</div><div class='add'>+var s_save_xnack_mask				= s_save_excp_flag_priv</div><div class='add'>+var s_wave_size					= ttmp7</div><div class='add'>+var s_save_buf_rsrc0				= ttmp8</div><div class='add'>+var s_save_buf_rsrc1				= ttmp9</div><div class='add'>+var s_save_buf_rsrc2				= ttmp10</div><div class='add'>+var s_save_buf_rsrc3				= ttmp11</div><div class='add'>+var s_save_mem_offset				= ttmp4</div><div class='add'>+var s_save_alloc_size				= s_save_excp_flag_priv</div><div class='add'>+var s_save_tmp					= ttmp14</div><div class='add'>+var s_save_m0					= ttmp5</div><div class='add'>+var s_save_ttmps_lo				= s_save_tmp</div><div class='add'>+var s_save_ttmps_hi				= s_save_excp_flag_priv</div><div class='add'>+</div><div class='add'>+var S_RESTORE_BUF_RSRC_WORD1_STRIDE		= S_SAVE_BUF_RSRC_WORD1_STRIDE</div><div class='add'>+var S_RESTORE_BUF_RSRC_WORD3_MISC		= S_SAVE_BUF_RSRC_WORD3_MISC</div><div class='add'>+</div><div class='add'>+var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000</div><div class='add'>+var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT		= 26</div><div class='add'>+var S_WAVE_SIZE					= 25</div><div class='add'>+</div><div class='add'>+var s_restore_spi_init_lo			= exec_lo</div><div class='add'>+var s_restore_spi_init_hi			= exec_hi</div><div class='add'>+var s_restore_mem_offset			= ttmp12</div><div class='add'>+var s_restore_alloc_size			= ttmp3</div><div class='add'>+var s_restore_tmp				= ttmp2</div><div class='add'>+var s_restore_mem_offset_save			= s_restore_tmp</div><div class='add'>+var s_restore_m0				= s_restore_alloc_size</div><div class='add'>+var s_restore_mode				= ttmp7</div><div class='add'>+var s_restore_flat_scratch			= s_restore_tmp</div><div class='add'>+var s_restore_pc_lo				= ttmp0</div><div class='add'>+var s_restore_pc_hi				= ttmp1</div><div class='add'>+var s_restore_exec_lo				= ttmp4</div><div class='add'>+var s_restore_exec_hi				= ttmp5</div><div class='add'>+var s_restore_state_priv			= ttmp14</div><div class='add'>+var s_restore_excp_flag_priv			= ttmp15</div><div class='add'>+var s_restore_xnack_mask			= ttmp13</div><div class='add'>+var s_restore_buf_rsrc0				= ttmp8</div><div class='add'>+var s_restore_buf_rsrc1				= ttmp9</div><div class='add'>+var s_restore_buf_rsrc2				= ttmp10</div><div class='add'>+var s_restore_buf_rsrc3				= ttmp11</div><div class='add'>+var s_restore_size				= ttmp6</div><div class='add'>+var s_restore_ttmps_lo				= s_restore_tmp</div><div class='add'>+var s_restore_ttmps_hi				= s_restore_alloc_size</div><div class='add'>+var s_restore_spi_init_hi_save			= s_restore_exec_hi</div><div class='add'>+</div><div class='add'>+shader main</div><div class='add'>+	asic(DEFAULT)</div><div class='add'>+	type(CS)</div><div class='add'>+	wave_size(32)</div><div class='add'>+</div><div class='add'>+	s_branch	L_SKIP_RESTORE						//NOT restore. might be a regular trap or save</div><div class='add'>+</div><div class='add'>+L_JUMP_TO_RESTORE:</div><div class='add'>+	s_branch	L_RESTORE</div><div class='add'>+</div><div class='add'>+L_SKIP_RESTORE:</div><div class='add'>+	s_getreg_b32	s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV)	//save STATUS since we will change SCC</div><div class='add'>+</div><div class='add'>+	// Clear SPI_PRIO: do not save with elevated priority.</div><div class='add'>+	// Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd.</div><div class='add'>+	s_andn2_b32	s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)</div><div class='add'>+</div><div class='add'>+	s_and_b32       ttmp2, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK</div><div class='add'>+	s_cbranch_scc0	L_NOT_HALTED</div><div class='add'>+</div><div class='add'>+L_HALTED:</div><div class='add'>+	// Host trap may occur while wave is halted.</div><div class='add'>+	s_and_b32	ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK</div><div class='add'>+	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='add'>+</div><div class='add'>+L_CHECK_SAVE:</div><div class='add'>+	s_and_b32	ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK</div><div class='add'>+	s_cbranch_scc1	L_SAVE</div><div class='add'>+</div><div class='add'>+	// Wave is halted but neither host trap nor SAVECTX is raised.</div><div class='add'>+	// Caused by instruction fetch memory violation.</div><div class='add'>+	// Spin wait until context saved to prevent interrupt storm.</div><div class='add'>+	s_sleep		0x10</div><div class='add'>+	s_getreg_b32	s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)</div><div class='add'>+	s_branch	L_CHECK_SAVE</div><div class='add'>+</div><div class='add'>+L_NOT_HALTED:</div><div class='add'>+	// Let second-level handle non-SAVECTX exception or trap.</div><div class='add'>+	// Any concurrent SAVECTX will be handled upon re-entry once halted.</div><div class='add'>+</div><div class='add'>+	// Check non-maskable exceptions. memory_violation, illegal_instruction</div><div class='add'>+	// and xnack_error exceptions always cause the wave to enter the trap</div><div class='add'>+	// handler.</div><div class='add'>+	s_and_b32	ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK</div><div class='add'>+	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='add'>+</div><div class='add'>+	// Check for maskable exceptions in trapsts.excp and trapsts.excp_hi.</div><div class='add'>+	// Maskable exceptions only cause the wave to enter the trap handler if</div><div class='add'>+	// their respective bit in mode.excp_en is set.</div><div class='add'>+	s_getreg_b32	ttmp2, hwreg(HW_REG_WAVE_EXCP_FLAG_USER)</div><div class='add'>+	s_and_b32	ttmp3, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK</div><div class='add'>+	s_cbranch_scc0	L_NOT_ADDR_WATCH</div><div class='add'>+	s_or_b32	ttmp2, ttmp2, SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK</div><div class='add'>+</div><div class='add'>+L_NOT_ADDR_WATCH:</div><div class='add'>+	s_getreg_b32	ttmp3, hwreg(HW_REG_WAVE_TRAP_CTRL)</div><div class='add'>+	s_and_b32	ttmp2, ttmp3, ttmp2</div><div class='add'>+	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='add'>+</div><div class='add'>+L_CHECK_TRAP_ID:</div><div class='add'>+	// Check trap_id != 0</div><div class='add'>+	s_and_b32	ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK</div><div class='add'>+	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='add'>+</div><div class='add'>+#if SINGLE_STEP_MISSED_WORKAROUND</div><div class='add'>+	// Prioritize single step exception over context save.</div><div class='add'>+	// Second-level trap will halt wave and RFE, re-entering for SAVECTX.</div><div class='add'>+	// WAVE_TRAP_CTRL is already in ttmp3.</div><div class='add'>+	s_and_b32	ttmp3, ttmp3, SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK</div><div class='add'>+	s_cbranch_scc1	L_FETCH_2ND_TRAP</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	s_and_b32	ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK</div><div class='add'>+	s_cbranch_scc1	L_SAVE</div><div class='add'>+</div><div class='add'>+L_FETCH_2ND_TRAP:</div><div class='add'>+	// Read second-level TBA/TMA from first-level TMA and jump if available.</div><div class='add'>+	// ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data)</div><div class='add'>+	// ttmp12 holds SQ_WAVE_STATUS</div><div class='add'>+	s_sendmsg_rtn_b64       [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA)</div><div class='add'>+	s_wait_idle</div><div class='add'>+	s_lshl_b64	[ttmp14, ttmp15], [ttmp14, ttmp15], 0x8</div><div class='add'>+</div><div class='add'>+	s_bitcmp1_b32	ttmp15, 0xF</div><div class='add'>+	s_cbranch_scc0	L_NO_SIGN_EXTEND_TMA</div><div class='add'>+	s_or_b32	ttmp15, ttmp15, 0xFFFF0000</div><div class='add'>+L_NO_SIGN_EXTEND_TMA:</div><div class='add'>+</div><div class='add'>+	s_load_dword    ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS		// debug trap enabled flag</div><div class='add'>+	s_wait_idle</div><div class='add'>+	s_lshl_b32      ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT</div><div class='add'>+	s_andn2_b32     ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK</div><div class='add'>+	s_or_b32        ttmp11, ttmp11, ttmp2</div><div class='add'>+</div><div class='add'>+	s_load_dwordx2	[ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 scope:SCOPE_SYS	// second-level TBA</div><div class='add'>+	s_wait_idle</div><div class='add'>+	s_load_dwordx2	[ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 scope:SCOPE_SYS	// second-level TMA</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_and_b64	[ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3]</div><div class='add'>+	s_cbranch_scc0	L_NO_NEXT_TRAP						// second-level trap handler not been set</div><div class='add'>+	s_setpc_b64	[ttmp2, ttmp3]						// jump to second-level trap handler</div><div class='add'>+</div><div class='add'>+L_NO_NEXT_TRAP:</div><div class='add'>+	// If not caused by trap then halt wave to prevent re-entry.</div><div class='add'>+	s_and_b32	ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK</div><div class='add'>+	s_cbranch_scc1	L_TRAP_CASE</div><div class='add'>+</div><div class='add'>+	// Host trap will not cause trap re-entry.</div><div class='add'>+	s_getreg_b32	ttmp2, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)</div><div class='add'>+	s_and_b32	ttmp2, ttmp2, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK</div><div class='add'>+	s_cbranch_scc1	L_EXIT_TRAP</div><div class='add'>+	s_or_b32	s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK</div><div class='add'>+</div><div class='add'>+	// If the PC points to S_ENDPGM then context save will fail if STATE_PRIV.HALT is set.</div><div class='add'>+	// Rewind the PC to prevent this from occurring.</div><div class='add'>+	s_sub_u32	ttmp0, ttmp0, 0x8</div><div class='add'>+	s_subb_u32	ttmp1, ttmp1, 0x0</div><div class='add'>+</div><div class='add'>+	s_branch	L_EXIT_TRAP</div><div class='add'>+</div><div class='add'>+L_TRAP_CASE:</div><div class='add'>+	// Advance past trap instruction to prevent re-entry.</div><div class='add'>+	s_add_u32	ttmp0, ttmp0, 0x4</div><div class='add'>+	s_addc_u32	ttmp1, ttmp1, 0x0</div><div class='add'>+</div><div class='add'>+L_EXIT_TRAP:</div><div class='add'>+	s_and_b32	ttmp1, ttmp1, 0xFFFF</div><div class='add'>+</div><div class='add'>+	// Restore SQ_WAVE_STATUS.</div><div class='add'>+	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32</div><div class='add'>+	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32</div><div class='add'>+</div><div class='add'>+	// STATE_PRIV.BARRIER_COMPLETE may have changed since we read it.</div><div class='add'>+	// Only restore fields which the trap handler changes.</div><div class='add'>+	s_lshr_b32	s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \</div><div class='add'>+		SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT - SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_state_priv</div><div class='add'>+</div><div class='add'>+	s_rfe_b64	[ttmp0, ttmp1]</div><div class='add'>+</div><div class='add'>+L_SAVE:</div><div class='add'>+	// If VGPRs have been deallocated then terminate the wavefront.</div><div class='add'>+	// It has no remaining program to run and cannot save without VGPRs.</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_STATUS)</div><div class='add'>+	s_bitcmp1_b32	s_save_tmp, SQ_WAVE_STATUS_NO_VGPRS_SHIFT</div><div class='add'>+	s_cbranch_scc0	L_HAVE_VGPRS</div><div class='add'>+	s_endpgm</div><div class='add'>+L_HAVE_VGPRS:</div><div class='add'>+</div><div class='add'>+	s_and_b32	s_save_pc_hi, s_save_pc_hi, 0x0000ffff			//pc[47:32]</div><div class='add'>+	s_mov_b32	s_save_tmp, 0</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT, 1), s_save_tmp	//clear saveCtx bit</div><div class='add'>+</div><div class='add'>+	/* inform SPI the readiness and wait for SPI's go signal */</div><div class='add'>+	s_mov_b32	s_save_exec_lo, exec_lo					//save EXEC and use EXEC for the go signal from SPI</div><div class='add'>+	s_mov_b32	s_save_exec_hi, exec_hi</div><div class='add'>+	s_mov_b64	exec, 0x0						//clear EXEC to get ready to receive</div><div class='add'>+</div><div class='add'>+	s_sendmsg_rtn_b64       [exec_lo, exec_hi], sendmsg(MSG_RTN_SAVE_WAVE)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	// Save first_wave flag so we can clear high bits of save address.</div><div class='add'>+	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK</div><div class='add'>+	s_lshl_b32	s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT)</div><div class='add'>+	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp</div><div class='add'>+</div><div class='add'>+	// Trap temporaries must be saved via VGPR but all VGPRs are in use.</div><div class='add'>+	// There is no ttmp space to hold the resource constant for VGPR save.</div><div class='add'>+	// Save v0 by itself since it requires only two SGPRs.</div><div class='add'>+	s_mov_b32	s_save_ttmps_lo, exec_lo</div><div class='add'>+	s_and_b32	s_save_ttmps_hi, exec_hi, 0xFFFF</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='add'>+	global_store_dword_addtid	v0, [s_save_ttmps_lo, s_save_ttmps_hi] scope:SCOPE_SYS</div><div class='add'>+	v_mov_b32	v0, 0x0</div><div class='add'>+	s_mov_b32	exec_lo, s_save_ttmps_lo</div><div class='add'>+	s_mov_b32	exec_hi, s_save_ttmps_hi</div><div class='add'>+</div><div class='add'>+	// Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic</div><div class='add'>+	// ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40</div><div class='add'>+	get_wave_size2(s_save_ttmps_hi)</div><div class='add'>+	get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi)</div><div class='add'>+	get_svgpr_size_bytes(s_save_ttmps_hi)</div><div class='add'>+	s_add_u32	s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi</div><div class='add'>+	s_and_b32	s_save_ttmps_hi, s_save_spi_init_hi, 0xFFFF</div><div class='add'>+	s_add_u32	s_save_ttmps_lo, s_save_ttmps_lo, get_sgpr_size_bytes()</div><div class='add'>+	s_add_u32	s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo</div><div class='add'>+	s_addc_u32	s_save_ttmps_hi, s_save_ttmps_hi, 0x0</div><div class='add'>+</div><div class='add'>+	v_writelane_b32	v0, ttmp4, 0x4</div><div class='add'>+	v_writelane_b32	v0, ttmp5, 0x5</div><div class='add'>+	v_writelane_b32	v0, ttmp6, 0x6</div><div class='add'>+	v_writelane_b32	v0, ttmp7, 0x7</div><div class='add'>+	v_writelane_b32	v0, ttmp8, 0x8</div><div class='add'>+	v_writelane_b32	v0, ttmp9, 0x9</div><div class='add'>+	v_writelane_b32	v0, ttmp10, 0xA</div><div class='add'>+	v_writelane_b32	v0, ttmp11, 0xB</div><div class='add'>+	v_writelane_b32	v0, ttmp13, 0xD</div><div class='add'>+	v_writelane_b32	v0, exec_lo, 0xE</div><div class='add'>+	v_writelane_b32	v0, exec_hi, 0xF</div><div class='add'>+	valu_sgpr_hazard()</div><div class='add'>+</div><div class='add'>+	s_mov_b32	exec_lo, 0x3FFF</div><div class='add'>+	s_mov_b32	exec_hi, 0x0</div><div class='add'>+	global_store_dword_addtid	v0, [s_save_ttmps_lo, s_save_ttmps_hi] offset:0x40 scope:SCOPE_SYS</div><div class='add'>+	v_readlane_b32	ttmp14, v0, 0xE</div><div class='add'>+	v_readlane_b32	ttmp15, v0, 0xF</div><div class='add'>+	s_mov_b32	exec_lo, ttmp14</div><div class='add'>+	s_mov_b32	exec_hi, ttmp15</div><div class='add'>+</div><div class='add'>+	/* setup Resource Contants */</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc0, s_save_spi_init_lo			//base_addr_lo</div><div class='add'>+	s_and_b32	s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF	//base_addr_hi</div><div class='add'>+	s_or_b32	s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0					//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_save_m0, m0</div><div class='add'>+</div><div class='add'>+	/* global mem offset */</div><div class='add'>+	s_mov_b32	s_save_mem_offset, 0x0</div><div class='add'>+	get_wave_size2(s_wave_size)</div><div class='add'>+</div><div class='add'>+	/* save first 4 VGPRs, needed for SGPR save */</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on</div><div class='add'>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_ENABLE_SAVE_4VGPR_EXEC_HI</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+	s_branch	L_SAVE_4VGPR_WAVE32</div><div class='add'>+L_ENABLE_SAVE_4VGPR_EXEC_HI:</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='add'>+	s_branch	L_SAVE_4VGPR_WAVE64</div><div class='add'>+L_SAVE_4VGPR_WAVE32:</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// VGPR Allocated in 4-GPR granularity</div><div class='add'>+</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3</div><div class='add'>+	s_branch	L_SAVE_HWREG</div><div class='add'>+</div><div class='add'>+L_SAVE_4VGPR_WAVE64:</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// VGPR Allocated in 4-GPR granularity</div><div class='add'>+</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3</div><div class='add'>+</div><div class='add'>+	/* save HW registers */</div><div class='add'>+</div><div class='add'>+L_SAVE_HWREG:</div><div class='add'>+	// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)</div><div class='add'>+	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)</div><div class='add'>+	get_svgpr_size_bytes(s_save_tmp)</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes()</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	v_mov_b32	v0, 0x0							//Offset[31:0] from buffer resource</div><div class='add'>+	v_mov_b32	v1, 0x0							//Offset[63:32] from buffer resource</div><div class='add'>+	v_mov_b32	v2, 0x0							//Set of SGPRs for TCP store</div><div class='add'>+</div><div class='add'>+	// Ensure no further changes to barrier or LDS state.</div><div class='add'>+	// STATE_PRIV.BARRIER_COMPLETE may change up to this point.</div><div class='add'>+	s_barrier_signal	-2</div><div class='add'>+	s_barrier_wait	-2</div><div class='add'>+</div><div class='add'>+	// Re-read final state of BARRIER_COMPLETE field for save.</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_STATE_PRIV)</div><div class='add'>+	s_and_b32	s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK</div><div class='add'>+	s_andn2_b32	s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK</div><div class='add'>+	s_or_b32	s_save_state_priv, s_save_state_priv, s_save_tmp</div><div class='add'>+</div><div class='add'>+	s_andn2_b32	s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK</div><div class='add'>+	v_writelane_b32	v2, s_save_m0, 0x0</div><div class='add'>+	v_writelane_b32	v2, s_save_pc_lo, 0x1</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0x2</div><div class='add'>+	v_writelane_b32	v2, s_save_exec_lo, 0x3</div><div class='add'>+	v_writelane_b32	v2, s_save_exec_hi, 0x4</div><div class='add'>+	v_writelane_b32	v2, s_save_state_priv, 0x5</div><div class='add'>+	v_writelane_b32	v2, s_save_xnack_mask, 0x7</div><div class='add'>+	valu_sgpr_hazard()</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0x6</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_MODE)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0x8</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0x9</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0xA</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_USER)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0xB</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_TRAP_CTRL)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0xC</div><div class='add'>+</div><div class='add'>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_WAVE_STATUS)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0xD</div><div class='add'>+</div><div class='add'>+	s_get_barrier_state s_save_tmp, -1</div><div class='add'>+	s_wait_kmcnt (0)</div><div class='add'>+	v_writelane_b32	v2, s_save_tmp, 0xE</div><div class='add'>+	valu_sgpr_hazard()</div><div class='add'>+</div><div class='add'>+	// Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this.</div><div class='add'>+	s_mov_b32       exec_lo, 0xFFFF</div><div class='add'>+	s_mov_b32	exec_hi, 0x0</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+</div><div class='add'>+	// Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode.</div><div class='add'>+	s_mov_b32       exec_lo, 0xFFFFFFFF</div><div class='add'>+</div><div class='add'>+	/* save SGPRs */</div><div class='add'>+	// Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...</div><div class='add'>+</div><div class='add'>+	// SGPR SR memory offset : size(VGPR)+size(SVGPR)</div><div class='add'>+	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)</div><div class='add'>+	get_svgpr_size_bytes(s_save_tmp)</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	s_mov_b32	ttmp13, 0x0						//next VGPR lane to copy SGPR into</div><div class='add'>+</div><div class='add'>+	s_mov_b32	m0, 0x0							//SGPR initial index value =0</div><div class='add'>+	s_nop		0x0							//Manually inserted wait states</div><div class='add'>+L_SAVE_SGPR_LOOP:</div><div class='add'>+	// SGPR is allocated in 16 SGPR granularity</div><div class='add'>+	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]</div><div class='add'>+	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]</div><div class='add'>+	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]</div><div class='add'>+	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]</div><div class='add'>+	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]</div><div class='add'>+	s_movrels_b64	s10, s10						//s10 = s[10+m0], s11 = s[11+m0]</div><div class='add'>+	s_movrels_b64	s12, s12						//s12 = s[12+m0], s13 = s[13+m0]</div><div class='add'>+	s_movrels_b64	s14, s14						//s14 = s[14+m0], s15 = s[15+m0]</div><div class='add'>+</div><div class='add'>+	s_cmp_eq_u32	ttmp13, 0x0</div><div class='add'>+	s_cbranch_scc0	L_WRITE_V2_SECOND_HALF</div><div class='add'>+	write_16sgpr_to_v2(s0, 0x0)</div><div class='add'>+	s_branch	L_SAVE_SGPR_SKIP_TCP_STORE</div><div class='add'>+L_WRITE_V2_SECOND_HALF:</div><div class='add'>+	write_16sgpr_to_v2(s0, 0x10)</div><div class='add'>+</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 0x80</div><div class='add'>+	s_mov_b32	ttmp13, 0x0</div><div class='add'>+	v_mov_b32	v2, 0x0</div><div class='add'>+L_SAVE_SGPR_SKIP_TCP_STORE:</div><div class='add'>+</div><div class='add'>+	s_add_u32	m0, m0, 16						//next sgpr index</div><div class='add'>+	s_cmp_lt_u32	m0, 96							//scc = (m0 &lt; first 96 SGPR) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_SGPR_LOOP					//first 96 SGPR save is complete?</div><div class='add'>+</div><div class='add'>+	//save the rest 12 SGPR</div><div class='add'>+	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]</div><div class='add'>+	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]</div><div class='add'>+	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]</div><div class='add'>+	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]</div><div class='add'>+	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]</div><div class='add'>+	s_movrels_b64	s10, s10						//s10 = s[10+m0], s11 = s[11+m0]</div><div class='add'>+	write_12sgpr_to_v2(s0)</div><div class='add'>+</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+</div><div class='add'>+	/* save LDS */</div><div class='add'>+</div><div class='add'>+L_SAVE_LDS:</div><div class='add'>+	// Change EXEC to all threads...</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on</div><div class='add'>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_ENABLE_SAVE_LDS_EXEC_HI</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+	s_branch	L_SAVE_LDS_NORMAL</div><div class='add'>+L_ENABLE_SAVE_LDS_EXEC_HI:</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='add'>+L_SAVE_LDS_NORMAL:</div><div class='add'>+	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)</div><div class='add'>+	s_and_b32	s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF	//lds_size is zero?</div><div class='add'>+	s_cbranch_scc0	L_SAVE_LDS_DONE						//no lds used? jump to L_SAVE_DONE</div><div class='add'>+</div><div class='add'>+	s_and_b32	s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK</div><div class='add'>+	s_cbranch_scc0	L_SAVE_LDS_DONE</div><div class='add'>+</div><div class='add'>+	// first wave do LDS save;</div><div class='add'>+</div><div class='add'>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, s_save_alloc_size			//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)</div><div class='add'>+	//</div><div class='add'>+	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)</div><div class='add'>+	get_svgpr_size_bytes(s_save_tmp)</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes()</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	//load 0~63*4(byte address) to vgpr v0</div><div class='add'>+	v_mbcnt_lo_u32_b32	v0, -1, 0</div><div class='add'>+	v_mbcnt_hi_u32_b32	v0, -1, v0</div><div class='add'>+	v_mul_u32_u24	v0, 4, v0</div><div class='add'>+</div><div class='add'>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_mov_b32	m0, 0x0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_LDS_W64</div><div class='add'>+</div><div class='add'>+L_SAVE_LDS_W32:</div><div class='add'>+	s_mov_b32	s3, 128</div><div class='add'>+	s_nop		0</div><div class='add'>+	s_nop		0</div><div class='add'>+	s_nop		0</div><div class='add'>+L_SAVE_LDS_LOOP_W32:</div><div class='add'>+	ds_read_b32	v1, v0</div><div class='add'>+	s_wait_idle</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+</div><div class='add'>+	s_add_u32	m0, m0, s3						//every buffer_store_lds does 128 bytes</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3</div><div class='add'>+	v_add_nc_u32	v0, v0, 128						//mem offset increased by 128 bytes</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc=(m0 &lt; s_save_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_LDS_LOOP_W32					//LDS save is complete?</div><div class='add'>+</div><div class='add'>+	s_branch	L_SAVE_LDS_DONE</div><div class='add'>+</div><div class='add'>+L_SAVE_LDS_W64:</div><div class='add'>+	s_mov_b32	s3, 256</div><div class='add'>+	s_nop		0</div><div class='add'>+	s_nop		0</div><div class='add'>+	s_nop		0</div><div class='add'>+L_SAVE_LDS_LOOP_W64:</div><div class='add'>+	ds_read_b32	v1, v0</div><div class='add'>+	s_wait_idle</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+</div><div class='add'>+	s_add_u32	m0, m0, s3						//every buffer_store_lds does 256 bytes</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3</div><div class='add'>+	v_add_nc_u32	v0, v0, 256						//mem offset increased by 256 bytes</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc=(m0 &lt; s_save_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_LDS_LOOP_W64					//LDS save is complete?</div><div class='add'>+</div><div class='add'>+L_SAVE_LDS_DONE:</div><div class='add'>+	/* save VGPRs  - set the Rest VGPRs */</div><div class='add'>+L_SAVE_VGPR:</div><div class='add'>+	// VGPR SR memory offset: 0</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on</div><div class='add'>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_ENABLE_SAVE_VGPR_EXEC_HI</div><div class='add'>+	s_mov_b32	s_save_mem_offset, (0+128*4)				// for the rest VGPRs</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+	s_branch	L_SAVE_VGPR_NORMAL</div><div class='add'>+L_ENABLE_SAVE_VGPR_EXEC_HI:</div><div class='add'>+	s_mov_b32	s_save_mem_offset, (0+256*4)				// for the rest VGPRs</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='add'>+L_SAVE_VGPR_NORMAL:</div><div class='add'>+	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)</div><div class='add'>+	s_add_u32	s_save_alloc_size, s_save_alloc_size, 1</div><div class='add'>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 2			//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)</div><div class='add'>+	//determine it is wave32 or wave64</div><div class='add'>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_SAVE_VGPR_WAVE64</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// VGPR Allocated in 4-GPR granularity</div><div class='add'>+</div><div class='add'>+	// VGPR store using dw burst</div><div class='add'>+	s_mov_b32	m0, 0x4							//VGPR initial index value =4</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size</div><div class='add'>+	s_cbranch_scc0	L_SAVE_VGPR_END</div><div class='add'>+</div><div class='add'>+L_SAVE_VGPR_W32_LOOP:</div><div class='add'>+	v_movrels_b32	v0, v0							//v0 = v[0+m0]</div><div class='add'>+	v_movrels_b32	v1, v1							//v1 = v[1+m0]</div><div class='add'>+	v_movrels_b32	v2, v2							//v2 = v[2+m0]</div><div class='add'>+	v_movrels_b32	v3, v3							//v3 = v[3+m0]</div><div class='add'>+</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3</div><div class='add'>+</div><div class='add'>+	s_add_u32	m0, m0, 4						//next vgpr index</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128*4		//every buffer_store_dword does 128 bytes</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 &lt; s_save_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_VGPR_W32_LOOP					//VGPR save is complete?</div><div class='add'>+</div><div class='add'>+	s_branch	L_SAVE_VGPR_END</div><div class='add'>+</div><div class='add'>+L_SAVE_VGPR_WAVE64:</div><div class='add'>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// VGPR store using dw burst</div><div class='add'>+	s_mov_b32	m0, 0x4							//VGPR initial index value =4</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size</div><div class='add'>+	s_cbranch_scc0	L_SAVE_SHARED_VGPR</div><div class='add'>+</div><div class='add'>+L_SAVE_VGPR_W64_LOOP:</div><div class='add'>+	v_movrels_b32	v0, v0							//v0 = v[0+m0]</div><div class='add'>+	v_movrels_b32	v1, v1							//v1 = v[1+m0]</div><div class='add'>+	v_movrels_b32	v2, v2							//v2 = v[2+m0]</div><div class='add'>+	v_movrels_b32	v3, v3							//v3 = v[3+m0]</div><div class='add'>+</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256</div><div class='add'>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*2</div><div class='add'>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3</div><div class='add'>+</div><div class='add'>+	s_add_u32	m0, m0, 4						//next vgpr index</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 256*4		//every buffer_store_dword does 256 bytes</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 &lt; s_save_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_VGPR_W64_LOOP					//VGPR save is complete?</div><div class='add'>+</div><div class='add'>+L_SAVE_SHARED_VGPR:</div><div class='add'>+	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)</div><div class='add'>+	s_and_b32	s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF	//shared_vgpr_size is zero?</div><div class='add'>+	s_cbranch_scc0	L_SAVE_VGPR_END						//no shared_vgpr used? jump to L_SAVE_LDS</div><div class='add'>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 3			//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)</div><div class='add'>+	//m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.</div><div class='add'>+	//save shared_vgpr will start from the index of m0</div><div class='add'>+	s_add_u32	s_save_alloc_size, s_save_alloc_size, m0</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+</div><div class='add'>+L_SAVE_SHARED_VGPR_WAVE64_LOOP:</div><div class='add'>+	v_movrels_b32	v0, v0							//v0 = v[0+m0]</div><div class='add'>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS</div><div class='add'>+	s_add_u32	m0, m0, 1						//next vgpr index</div><div class='add'>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128</div><div class='add'>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 &lt; s_save_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_SAVE_SHARED_VGPR_WAVE64_LOOP				//SHARED_VGPR save is complete?</div><div class='add'>+</div><div class='add'>+L_SAVE_VGPR_END:</div><div class='add'>+	s_branch	L_END_PGM</div><div class='add'>+</div><div class='add'>+L_RESTORE:</div><div class='add'>+	/* Setup Resource Contants */</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc0, s_restore_spi_init_lo		//base_addr_lo</div><div class='add'>+	s_and_b32	s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF	//base_addr_hi</div><div class='add'>+	s_or_b32	s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, 0					//NUM_RECORDS initial value = 0 (in bytes)</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC</div><div class='add'>+</div><div class='add'>+	// Save s_restore_spi_init_hi for later use.</div><div class='add'>+	s_mov_b32 s_restore_spi_init_hi_save, s_restore_spi_init_hi</div><div class='add'>+</div><div class='add'>+	//determine it is wave32 or wave64</div><div class='add'>+	get_wave_size2(s_restore_size)</div><div class='add'>+</div><div class='add'>+	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK</div><div class='add'>+	s_cbranch_scc0	L_RESTORE_VGPR</div><div class='add'>+</div><div class='add'>+	/* restore LDS */</div><div class='add'>+L_RESTORE_LDS:</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on</div><div class='add'>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_ENABLE_RESTORE_LDS_EXEC_HI</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+	s_branch	L_RESTORE_LDS_NORMAL</div><div class='add'>+L_ENABLE_RESTORE_LDS_EXEC_HI:</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='add'>+L_RESTORE_LDS_NORMAL:</div><div class='add'>+	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)</div><div class='add'>+	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//lds_size is zero?</div><div class='add'>+	s_cbranch_scc0	L_RESTORE_VGPR						//no lds used? jump to L_RESTORE_VGPR</div><div class='add'>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, s_restore_alloc_size		//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)</div><div class='add'>+	//</div><div class='add'>+	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)</div><div class='add'>+	get_svgpr_size_bytes(s_restore_tmp)</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_mov_b32	m0, 0x0</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W64</div><div class='add'>+</div><div class='add'>+L_RESTORE_LDS_LOOP_W32:</div><div class='add'>+	buffer_load_dword       v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset</div><div class='add'>+	s_wait_idle</div><div class='add'>+	ds_store_addtid_b32     v0</div><div class='add'>+	s_add_u32	m0, m0, 128						// 128 DW</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128		//mem offset increased by 128DW</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc=(m0 &lt; s_restore_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W32					//LDS restore is complete?</div><div class='add'>+	s_branch	L_RESTORE_VGPR</div><div class='add'>+</div><div class='add'>+L_RESTORE_LDS_LOOP_W64:</div><div class='add'>+	buffer_load_dword       v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset</div><div class='add'>+	s_wait_idle</div><div class='add'>+	ds_store_addtid_b32     v0</div><div class='add'>+	s_add_u32	m0, m0, 256						// 256 DW</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256		//mem offset increased by 256DW</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc=(m0 &lt; s_restore_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W64					//LDS restore is complete?</div><div class='add'>+</div><div class='add'>+	/* restore VGPRs */</div><div class='add'>+L_RESTORE_VGPR:</div><div class='add'>+	// VGPR SR memory offset : 0</div><div class='add'>+	s_mov_b32	s_restore_mem_offset, 0x0</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on</div><div class='add'>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_ENABLE_RESTORE_VGPR_EXEC_HI</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+	s_branch	L_RESTORE_VGPR_NORMAL</div><div class='add'>+L_ENABLE_RESTORE_VGPR_EXEC_HI:</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF</div><div class='add'>+L_RESTORE_VGPR_NORMAL:</div><div class='add'>+	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)</div><div class='add'>+	s_add_u32	s_restore_alloc_size, s_restore_alloc_size, 1</div><div class='add'>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 2		//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)</div><div class='add'>+	//determine it is wave32 or wave64</div><div class='add'>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE</div><div class='add'>+	s_and_b32	m0, m0, 1</div><div class='add'>+	s_cmp_eq_u32	m0, 1</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_VGPR_WAVE64</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// VGPR load using dw burst</div><div class='add'>+	s_mov_b32	s_restore_mem_offset_save, s_restore_mem_offset		// restore start with v1, v0 will be the last</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128*4</div><div class='add'>+	s_mov_b32	m0, 4							//VGPR initial index value = 4</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size</div><div class='add'>+	s_cbranch_scc0	L_RESTORE_SGPR</div><div class='add'>+</div><div class='add'>+L_RESTORE_VGPR_WAVE32_LOOP:</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*3</div><div class='add'>+	s_wait_idle</div><div class='add'>+	v_movreld_b32	v0, v0							//v[0+m0] = v0</div><div class='add'>+	v_movreld_b32	v1, v1</div><div class='add'>+	v_movreld_b32	v2, v2</div><div class='add'>+	v_movreld_b32	v3, v3</div><div class='add'>+	s_add_u32	m0, m0, 4						//next vgpr index</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128*4	//every buffer_load_dword does 128 bytes</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 &lt; s_restore_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_VGPR_WAVE32_LOOP				//VGPR restore (except v0) is complete?</div><div class='add'>+</div><div class='add'>+	/* VGPR restore on v0 */</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128*3</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_branch	L_RESTORE_SGPR</div><div class='add'>+</div><div class='add'>+L_RESTORE_VGPR_WAVE64:</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// VGPR load using dw burst</div><div class='add'>+	s_mov_b32	s_restore_mem_offset_save, s_restore_mem_offset		// restore start with v4, v0 will be the last</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256*4</div><div class='add'>+	s_mov_b32	m0, 4							//VGPR initial index value = 4</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size</div><div class='add'>+	s_cbranch_scc0	L_RESTORE_SHARED_VGPR</div><div class='add'>+</div><div class='add'>+L_RESTORE_VGPR_WAVE64_LOOP:</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*3</div><div class='add'>+	s_wait_idle</div><div class='add'>+	v_movreld_b32	v0, v0							//v[0+m0] = v0</div><div class='add'>+	v_movreld_b32	v1, v1</div><div class='add'>+	v_movreld_b32	v2, v2</div><div class='add'>+	v_movreld_b32	v3, v3</div><div class='add'>+	s_add_u32	m0, m0, 4						//next vgpr index</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256*4	//every buffer_load_dword does 256 bytes</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 &lt; s_restore_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_VGPR_WAVE64_LOOP				//VGPR restore (except v0) is complete?</div><div class='add'>+</div><div class='add'>+L_RESTORE_SHARED_VGPR:</div><div class='add'>+	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)	//shared_vgpr_size</div><div class='add'>+	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//shared_vgpr_size is zero?</div><div class='add'>+	s_cbranch_scc0	L_RESTORE_V0						//no shared_vgpr used?</div><div class='add'>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 3		//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)</div><div class='add'>+	//m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.</div><div class='add'>+	//restore shared_vgpr will start from the index of m0</div><div class='add'>+	s_add_u32	s_restore_alloc_size, s_restore_alloc_size, m0</div><div class='add'>+	s_mov_b32	exec_lo, 0xFFFFFFFF</div><div class='add'>+	s_mov_b32	exec_hi, 0x00000000</div><div class='add'>+L_RESTORE_SHARED_VGPR_WAVE64_LOOP:</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS</div><div class='add'>+	s_wait_idle</div><div class='add'>+	v_movreld_b32	v0, v0							//v[0+m0] = v0</div><div class='add'>+	s_add_u32	m0, m0, 1						//next vgpr index</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128</div><div class='add'>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 &lt; s_restore_alloc_size) ? 1 : 0</div><div class='add'>+	s_cbranch_scc1	L_RESTORE_SHARED_VGPR_WAVE64_LOOP			//VGPR restore (except v0) is complete?</div><div class='add'>+</div><div class='add'>+	s_mov_b32	exec_hi, 0xFFFFFFFF					//restore back exec_hi before restoring V0!!</div><div class='add'>+</div><div class='add'>+	/* VGPR restore on v0 */</div><div class='add'>+L_RESTORE_V0:</div><div class='add'>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS</div><div class='add'>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256</div><div class='add'>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256*2</div><div class='add'>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256*3</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	/* restore SGPRs */</div><div class='add'>+	//will be 2+8+16*6</div><div class='add'>+	// SGPR SR memory offset : size(VGPR)+size(SVGPR)</div><div class='add'>+L_RESTORE_SGPR:</div><div class='add'>+	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)</div><div class='add'>+	get_svgpr_size_bytes(s_restore_tmp)</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()</div><div class='add'>+	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 20*4	//s108~s127 is not saved</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	s_mov_b32	m0, s_sgpr_save_num</div><div class='add'>+</div><div class='add'>+	read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_sub_u32	m0, m0, 4						// Restore from S[0] to S[104]</div><div class='add'>+	s_nop		0							// hazard SALU M0=&gt; S_MOVREL</div><div class='add'>+</div><div class='add'>+	s_movreld_b64	s0, s0							//s[0+m0] = s0</div><div class='add'>+	s_movreld_b64	s2, s2</div><div class='add'>+</div><div class='add'>+	read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_sub_u32	m0, m0, 8						// Restore from S[0] to S[96]</div><div class='add'>+	s_nop		0							// hazard SALU M0=&gt; S_MOVREL</div><div class='add'>+</div><div class='add'>+	s_movreld_b64	s0, s0							//s[0+m0] = s0</div><div class='add'>+	s_movreld_b64	s2, s2</div><div class='add'>+	s_movreld_b64	s4, s4</div><div class='add'>+	s_movreld_b64	s6, s6</div><div class='add'>+</div><div class='add'>+ L_RESTORE_SGPR_LOOP:</div><div class='add'>+	read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_sub_u32	m0, m0, 16						// Restore from S[n] to S[0]</div><div class='add'>+	s_nop		0							// hazard SALU M0=&gt; S_MOVREL</div><div class='add'>+</div><div class='add'>+	s_movreld_b64	s0, s0							//s[0+m0] = s0</div><div class='add'>+	s_movreld_b64	s2, s2</div><div class='add'>+	s_movreld_b64	s4, s4</div><div class='add'>+	s_movreld_b64	s6, s6</div><div class='add'>+	s_movreld_b64	s8, s8</div><div class='add'>+	s_movreld_b64	s10, s10</div><div class='add'>+	s_movreld_b64	s12, s12</div><div class='add'>+	s_movreld_b64	s14, s14</div><div class='add'>+</div><div class='add'>+	s_cmp_eq_u32	m0, 0							//scc = (m0 &lt; s_sgpr_save_num) ? 1 : 0</div><div class='add'>+	s_cbranch_scc0	L_RESTORE_SGPR_LOOP</div><div class='add'>+</div><div class='add'>+	// s_barrier with STATE_PRIV.TRAP_AFTER_INST=1, STATUS.PRIV=1 incorrectly asserts debug exception.</div><div class='add'>+	// Clear DEBUG_EN before and restore MODE after the barrier.</div><div class='add'>+	s_setreg_imm32_b32	hwreg(HW_REG_WAVE_MODE), 0</div><div class='add'>+</div><div class='add'>+	/* restore HW registers */</div><div class='add'>+L_RESTORE_HWREG:</div><div class='add'>+	// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)</div><div class='add'>+	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)</div><div class='add'>+	get_svgpr_size_bytes(s_restore_tmp)</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()</div><div class='add'>+</div><div class='add'>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes</div><div class='add'>+</div><div class='add'>+	// Restore s_restore_spi_init_hi before the saved value gets clobbered.</div><div class='add'>+	s_mov_b32 s_restore_spi_init_hi, s_restore_spi_init_hi_save</div><div class='add'>+</div><div class='add'>+	read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_state_priv, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_excp_flag_priv, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_SCRATCH_BASE_LO), s_restore_flat_scratch</div><div class='add'>+</div><div class='add'>+	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_SCRATCH_BASE_HI), s_restore_flat_scratch</div><div class='add'>+</div><div class='add'>+	read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_EXCP_FLAG_USER), s_restore_tmp</div><div class='add'>+</div><div class='add'>+	read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_TRAP_CTRL), s_restore_tmp</div><div class='add'>+</div><div class='add'>+	// Only the first wave needs to restore the workgroup barrier.</div><div class='add'>+	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK</div><div class='add'>+	s_cbranch_scc0	L_SKIP_BARRIER_RESTORE</div><div class='add'>+</div><div class='add'>+	// Skip over WAVE_STATUS, since there is no state to restore from it</div><div class='add'>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 4</div><div class='add'>+</div><div class='add'>+	read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset)</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_bitcmp1_b32	s_restore_tmp, BARRIER_STATE_VALID_OFFSET</div><div class='add'>+	s_cbranch_scc0	L_SKIP_BARRIER_RESTORE</div><div class='add'>+</div><div class='add'>+	// extract the saved signal count from s_restore_tmp</div><div class='add'>+	s_lshr_b32	s_restore_tmp, s_restore_tmp, BARRIER_STATE_SIGNAL_OFFSET</div><div class='add'>+</div><div class='add'>+	// We need to call s_barrier_signal repeatedly to restore the signal</div><div class='add'>+	// count of the work group barrier.  The member count is already</div><div class='add'>+	// initialized with the number of waves in the work group.</div><div class='add'>+L_BARRIER_RESTORE_LOOP:</div><div class='add'>+	s_and_b32	s_restore_tmp, s_restore_tmp, s_restore_tmp</div><div class='add'>+	s_cbranch_scc0	L_SKIP_BARRIER_RESTORE</div><div class='add'>+	s_barrier_signal	-1</div><div class='add'>+	s_add_i32	s_restore_tmp, s_restore_tmp, -1</div><div class='add'>+	s_branch	L_BARRIER_RESTORE_LOOP</div><div class='add'>+</div><div class='add'>+L_SKIP_BARRIER_RESTORE:</div><div class='add'>+</div><div class='add'>+	s_mov_b32	m0, s_restore_m0</div><div class='add'>+	s_mov_b32	exec_lo, s_restore_exec_lo</div><div class='add'>+	s_mov_b32	exec_hi, s_restore_exec_hi</div><div class='add'>+</div><div class='add'>+	// EXCP_FLAG_PRIV.SAVE_CONTEXT and HOST_TRAP may have changed.</div><div class='add'>+	// Only restore the other fields to avoid clobbering them.</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, 0, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE), s_restore_excp_flag_priv</div><div class='add'>+	s_lshr_b32	s_restore_excp_flag_priv, s_restore_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE), s_restore_excp_flag_priv</div><div class='add'>+	s_lshr_b32	s_restore_excp_flag_priv, s_restore_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE), s_restore_excp_flag_priv</div><div class='add'>+</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_MODE), s_restore_mode</div><div class='add'>+</div><div class='add'>+	// Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic</div><div class='add'>+	// ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40</div><div class='add'>+	get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size)</div><div class='add'>+	get_svgpr_size_bytes(s_restore_ttmps_hi)</div><div class='add'>+	s_add_u32	s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi</div><div class='add'>+	s_add_u32	s_restore_ttmps_lo, s_restore_ttmps_lo, get_sgpr_size_bytes()</div><div class='add'>+	s_add_u32	s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0</div><div class='add'>+	s_addc_u32	s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0</div><div class='add'>+	s_and_b32	s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF</div><div class='add'>+	s_load_dwordx4	[ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 scope:SCOPE_SYS</div><div class='add'>+	s_load_dwordx4	[ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 scope:SCOPE_SYS</div><div class='add'>+	s_load_dword	ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 scope:SCOPE_SYS</div><div class='add'>+	s_wait_idle</div><div class='add'>+</div><div class='add'>+	s_and_b32	s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff		//pc[47:32] //Do it here in order not to affect STATUS</div><div class='add'>+	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32</div><div class='add'>+	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32</div><div class='add'>+</div><div class='add'>+	s_setreg_b32	hwreg(HW_REG_WAVE_STATE_PRIV), s_restore_state_priv	// SCC is included, which is changed by previous salu</div><div class='add'>+</div><div class='add'>+	// Make barrier and LDS state visible to all waves in the group.</div><div class='add'>+	// STATE_PRIV.BARRIER_COMPLETE may change after this point.</div><div class='add'>+	s_barrier_signal	-2</div><div class='add'>+	s_barrier_wait	-2</div><div class='add'>+</div><div class='add'>+	s_rfe_b64	s_restore_pc_lo						//Return to the main shader program and resume execution</div><div class='add'>+</div><div class='add'>+L_END_PGM:</div><div class='add'>+	// Make sure that no wave of the workgroup can exit the trap handler</div><div class='add'>+	// before the workgroup barrier state is saved.</div><div class='add'>+	s_barrier_signal	-2</div><div class='add'>+	s_barrier_wait	-2</div><div class='add'>+	s_endpgm_saved</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function write_16sgpr_to_v2(s, lane_offset)</div><div class='add'>+	// Copy into VGPR for later TCP store.</div><div class='add'>+	for var sgpr_idx = 0; sgpr_idx &lt; 16; sgpr_idx ++</div><div class='add'>+		v_writelane_b32	v2, s[sgpr_idx], sgpr_idx + lane_offset</div><div class='add'>+	end</div><div class='add'>+	valu_sgpr_hazard()</div><div class='add'>+	s_add_u32	ttmp13, ttmp13, 0x10</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function write_12sgpr_to_v2(s)</div><div class='add'>+	// Copy into VGPR for later TCP store.</div><div class='add'>+	for var sgpr_idx = 0; sgpr_idx &lt; 12; sgpr_idx ++</div><div class='add'>+		v_writelane_b32	v2, s[sgpr_idx], sgpr_idx</div><div class='add'>+	end</div><div class='add'>+	valu_sgpr_hazard()</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)</div><div class='add'>+	s_buffer_load_dword	s, s_rsrc, s_mem_offset scope:SCOPE_SYS</div><div class='add'>+	s_add_u32	s_mem_offset, s_mem_offset, 4</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)</div><div class='add'>+	s_sub_u32	s_mem_offset, s_mem_offset, 4*16</div><div class='add'>+	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset scope:SCOPE_SYS</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset)</div><div class='add'>+	s_sub_u32	s_mem_offset, s_mem_offset, 4*8</div><div class='add'>+	s_buffer_load_dwordx8	s, s_rsrc, s_mem_offset scope:SCOPE_SYS</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset)</div><div class='add'>+	s_sub_u32	s_mem_offset, s_mem_offset, 4*4</div><div class='add'>+	s_buffer_load_dwordx4	s, s_rsrc, s_mem_offset scope:SCOPE_SYS</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function get_vgpr_size_bytes(s_vgpr_size_byte, s_size)</div><div class='add'>+	s_getreg_b32	s_vgpr_size_byte, hwreg(HW_REG_WAVE_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)</div><div class='add'>+	s_add_u32	s_vgpr_size_byte, s_vgpr_size_byte, 1</div><div class='add'>+	s_bitcmp1_b32	s_size, S_WAVE_SIZE</div><div class='add'>+	s_cbranch_scc1	L_ENABLE_SHIFT_W64</div><div class='add'>+	s_lshl_b32	s_vgpr_size_byte, s_vgpr_size_byte, (2+7)		//Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4   (non-zero value)</div><div class='add'>+	s_branch	L_SHIFT_DONE</div><div class='add'>+L_ENABLE_SHIFT_W64:</div><div class='add'>+	s_lshl_b32	s_vgpr_size_byte, s_vgpr_size_byte, (2+8)		//Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4   (non-zero value)</div><div class='add'>+L_SHIFT_DONE:</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function get_svgpr_size_bytes(s_svgpr_size_byte)</div><div class='add'>+	s_getreg_b32	s_svgpr_size_byte, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)</div><div class='add'>+	s_lshl_b32	s_svgpr_size_byte, s_svgpr_size_byte, (3+7)</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function get_sgpr_size_bytes</div><div class='add'>+	return 512</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function get_hwreg_size_bytes</div><div class='add'>+	return 128</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function get_wave_size2(s_reg)</div><div class='add'>+	s_getreg_b32	s_reg, hwreg(HW_REG_WAVE_STATUS,SQ_WAVE_STATUS_WAVE64_SHIFT,SQ_WAVE_STATUS_WAVE64_SIZE)</div><div class='add'>+	s_lshl_b32	s_reg, s_reg, S_WAVE_SIZE</div><div class='add'>+end</div><div class='add'>+</div><div class='add'>+function valu_sgpr_hazard</div><div class='add'>+#if HAVE_VALU_SGPR_HAZARD</div><div class='add'>+	for var rep = 0; rep &lt; 8; rep ++</div><div class='add'>+		ds_nop</div><div class='add'>+	end</div><div class='add'>+#endif</div><div class='add'>+end</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm<br/>index bb26338204f4..6869e07a2fff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm</a></div><div class='hunk'>@@ -37,17 +37,28 @@</div><div class='ctx'>  * gc_9_4_3:</div><div class='ctx'>  *   cpp -DASIC_FAMILY=GC_9_4_3 cwsr_trap_handler_gfx9.asm -P -o gc_9_4_3.sp3</div><div class='ctx'>  *   sp3 gc_9_4_3.sp3 -hex gc_9_4_3.hex</div><div class='add'>+ *</div><div class='add'>+ * gc_9_5_0:</div><div class='add'>+ *   cpp -DASIC_FAMILY=GC_9_5_0 cwsr_trap_handler_gfx9.asm -P -o gc_9_5_0.sp3</div><div class='add'>+ *   sp3 gc_9_5_0.sp3 -hex gc_9_5_0.hex</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #define CHIP_VEGAM 18</div><div class='ctx'> #define CHIP_ARCTURUS 23</div><div class='ctx'> #define CHIP_ALDEBARAN 25</div><div class='ctx'> #define CHIP_GC_9_4_3 26</div><div class='add'>+#define CHIP_GC_9_5_0 27</div><div class='ctx'> </div><div class='ctx'> var ACK_SQC_STORE		    =	1		    //workaround for suspected SQC store bug causing incorrect stores under concurrency</div><div class='ctx'> var SAVE_AFTER_XNACK_ERROR	    =	1		    //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger</div><div class='ctx'> var SINGLE_STEP_MISSED_WORKAROUND   =	(ASIC_FAMILY &lt;= CHIP_ALDEBARAN)	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised</div><div class='ctx'> </div><div class='add'>+#if ASIC_FAMILY &lt; CHIP_GC_9_4_3</div><div class='add'>+#define VMEM_MODIFIERS slc:1 glc:1</div><div class='add'>+#else</div><div class='add'>+#define VMEM_MODIFIERS sc0:1 nt:1</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /**************************************************************************/</div><div class='ctx'> /*			variables					  */</div><div class='ctx'> /**************************************************************************/</div><div class='hunk'>@@ -62,7 +73,13 @@ var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK    = 0x400000</div><div class='ctx'> var SQ_WAVE_STATUS_ECC_ERR_MASK         = 0x20000</div><div class='ctx'> </div><div class='ctx'> var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12</div><div class='add'>+#if ASIC_FAMILY &gt;= CHIP_GC_9_5_0</div><div class='add'>+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE	= 11</div><div class='add'>+var LDS_RESTORE_GRANULARITY_BYTES	= 1280</div><div class='add'>+#else</div><div class='ctx'> var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE	= 9</div><div class='add'>+var LDS_RESTORE_GRANULARITY_BYTES	= 512</div><div class='add'>+#endif</div><div class='ctx'> var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6</div><div class='ctx'> var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 3			//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits</div><div class='ctx'> var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24</div><div class='hunk'>@@ -430,7 +447,9 @@ L_SAVE:</div><div class='ctx'>     s_getreg_b32    s_save_m0, hwreg(HW_REG_MODE)						    //MODE</div><div class='ctx'>     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='del'>-</div><div class='add'>+    // Clear VSKIP state now that MODE.VSKIP has been saved.</div><div class='add'>+    // If user shader set it then vector instructions would be skipped.</div><div class='add'>+    s_setvskip	0,0</div><div class='ctx'> </div><div class='ctx'>     /*	    the first wave in the threadgroup	 */</div><div class='ctx'>     s_and_b32	    s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK	// extract fisrt wave bit</div><div class='hunk'>@@ -557,12 +576,21 @@ if SAVE_AFTER_XNACK_ERROR</div><div class='ctx'> </div><div class='ctx'> 	v_lshlrev_b32 v2, 2, v3</div><div class='ctx'> L_SAVE_LDS_LOOP_SQC:</div><div class='add'>+#if ASIC_FAMILY &lt; CHIP_GC_9_5_0</div><div class='ctx'> 	ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40</div><div class='ctx'> 	s_waitcnt lgkmcnt(0)</div><div class='del'>-</div><div class='ctx'> 	write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='ctx'> </div><div class='ctx'> 	v_add_u32 v2, 0x200, v2</div><div class='add'>+#else</div><div class='add'>+	// gfx950 needs to save in multiple of 256 bytes.</div><div class='add'>+	ds_read_b32 v0, v2</div><div class='add'>+	s_waitcnt lgkmcnt(0)</div><div class='add'>+	write_vgprs_to_mem_with_sqc(v0, 1, s_save_buf_rsrc0, s_save_mem_offset)</div><div class='add'>+</div><div class='add'>+	v_add_u32 v2, 0x100, v2</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size</div><div class='ctx'> 	s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC</div><div class='ctx'> </div><div class='hunk'>@@ -581,11 +609,14 @@ end</div><div class='ctx'> L_SAVE_LDS_LOOP_VECTOR:</div><div class='ctx'>       ds_read_b64 v[0:1], v2	//x =LDS[a], byte address</div><div class='ctx'>       s_waitcnt lgkmcnt(0)</div><div class='del'>-      buffer_store_dwordx2  v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1  glc:1  slc:1</div><div class='add'>+      buffer_store_dwordx2  v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset VMEM_MODIFIERS offen:1</div><div class='ctx'> //	s_waitcnt vmcnt(0)</div><div class='ctx'> //	v_add_u32 v2, vcc[0:1], v2, v3</div><div class='ctx'>       v_add_u32 v2, v2, v3</div><div class='ctx'>       v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size</div><div class='add'>+#if ASIC_FAMILY &gt;= CHIP_GC_9_5_0</div><div class='add'>+      s_mov_b64 exec, vcc</div><div class='add'>+#endif</div><div class='ctx'>       s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR</div><div class='ctx'> </div><div class='ctx'>       // restore rsrc3</div><div class='hunk'>@@ -748,8 +779,13 @@ L_RESTORE:</div><div class='ctx'>   L_RESTORE_LDS_LOOP:</div><div class='ctx'> 	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1		       // first 64DW</div><div class='ctx'> 	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256	       // second 64DW</div><div class='del'>-    s_add_u32	    m0, m0, 256*2						// 128 DW</div><div class='del'>-    s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*2		//mem offset increased by 128DW</div><div class='add'>+#if ASIC_FAMILY &gt;= CHIP_GC_9_5_0</div><div class='add'>+	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:512	// third 64DW</div><div class='add'>+	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:768	// forth 64DW</div><div class='add'>+	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:1024	// fifth 64DW</div><div class='add'>+#endif</div><div class='add'>+    s_add_u32	    m0, m0, LDS_RESTORE_GRANULARITY_BYTES					// 128/320 DW</div><div class='add'>+    s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, LDS_RESTORE_GRANULARITY_BYTES	//mem offset increased by 128/320 DW</div><div class='ctx'>     s_cmp_lt_u32    m0, s_restore_alloc_size					//scc=(m0 &lt; s_restore_alloc_size) ? 1 : 0</div><div class='ctx'>     s_cbranch_scc1  L_RESTORE_LDS_LOOP							    //LDS restore is complete?</div><div class='ctx'> </div><div class='hunk'>@@ -979,17 +1015,17 @@ L_TCP_STORE_CHECK_DONE:</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> function write_4vgprs_to_mem(s_rsrc, s_mem_offset)</div><div class='del'>-	buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1</div><div class='del'>-	buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256</div><div class='del'>-	buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256*2</div><div class='del'>-	buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256*3</div><div class='add'>+	buffer_store_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS</div><div class='add'>+	buffer_store_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256</div><div class='add'>+	buffer_store_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*2</div><div class='add'>+	buffer_store_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3</div><div class='ctx'> end</div><div class='ctx'> </div><div class='ctx'> function read_4vgprs_from_mem(s_rsrc, s_mem_offset)</div><div class='del'>-	buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1</div><div class='del'>-	buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256</div><div class='del'>-	buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2</div><div class='del'>-	buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3</div><div class='add'>+	buffer_load_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS</div><div class='add'>+	buffer_load_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256</div><div class='add'>+	buffer_load_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*2</div><div class='add'>+	buffer_load_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3</div><div class='ctx'> 	s_waitcnt vmcnt(0)</div><div class='ctx'> end</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c<br/>index dfa8c69532d4..22925df6a791 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_chardev.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_chardev.c</a></div><div class='hunk'>@@ -22,7 +22,6 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='del'>-#include &lt;linux/export.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/fs.h&gt;</div><div class='ctx'> #include &lt;linux/file.h&gt;</div><div class='hunk'>@@ -36,7 +35,6 @@</div><div class='ctx'> #include &lt;linux/mman.h&gt;</div><div class='ctx'> #include &lt;linux/ptrace.h&gt;</div><div class='ctx'> #include &lt;linux/dma-buf.h&gt;</div><div class='del'>-#include &lt;linux/fdtable.h&gt;</div><div class='ctx'> #include &lt;linux/processor.h&gt;</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> #include "kfd_device_queue_manager.h"</div><div class='hunk'>@@ -156,8 +154,8 @@ static int kfd_open(struct inode *inode, struct file *filep)</div><div class='ctx'> 	/* filep now owns the reference returned by kfd_create_process */</div><div class='ctx'> 	filep-&gt;private_data = process;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",</div><div class='del'>-		process-&gt;pasid, process-&gt;is_32bit_user_mode);</div><div class='add'>+	dev_dbg(kfd_device, "process pid %d opened kfd node, compat mode (32 bit) - %d\n",</div><div class='add'>+		process-&gt;lead_thread-&gt;pid, process-&gt;is_32bit_user_mode);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -213,6 +211,11 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (args-&gt;ring_size &lt; KFD_MIN_QUEUE_RING_SIZE) {</div><div class='add'>+		args-&gt;ring_size = KFD_MIN_QUEUE_RING_SIZE;</div><div class='add'>+		pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!access_ok((const void __user *) args-&gt;read_pointer_address,</div><div class='ctx'> 			sizeof(uint32_t))) {</div><div class='ctx'> 		pr_err("Can't access read pointer\n");</div><div class='hunk'>@@ -247,14 +250,15 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,</div><div class='ctx'> 	q_properties-&gt;priority = args-&gt;queue_priority;</div><div class='ctx'> 	q_properties-&gt;queue_address = args-&gt;ring_base_address;</div><div class='ctx'> 	q_properties-&gt;queue_size = args-&gt;ring_size;</div><div class='del'>-	q_properties-&gt;read_ptr = (uint32_t *) args-&gt;read_pointer_address;</div><div class='del'>-	q_properties-&gt;write_ptr = (uint32_t *) args-&gt;write_pointer_address;</div><div class='add'>+	q_properties-&gt;read_ptr = (void __user *)args-&gt;read_pointer_address;</div><div class='add'>+	q_properties-&gt;write_ptr = (void __user *)args-&gt;write_pointer_address;</div><div class='ctx'> 	q_properties-&gt;eop_ring_buffer_address = args-&gt;eop_buffer_address;</div><div class='ctx'> 	q_properties-&gt;eop_ring_buffer_size = args-&gt;eop_buffer_size;</div><div class='ctx'> 	q_properties-&gt;ctx_save_restore_area_address =</div><div class='ctx'> 			args-&gt;ctx_save_restore_address;</div><div class='ctx'> 	q_properties-&gt;ctx_save_restore_area_size = args-&gt;ctx_save_restore_size;</div><div class='ctx'> 	q_properties-&gt;ctl_stack_size = args-&gt;ctl_stack_size;</div><div class='add'>+	q_properties-&gt;sdma_engine_id = args-&gt;sdma_engine_id;</div><div class='ctx'> 	if (args-&gt;queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||</div><div class='ctx'> 		args-&gt;queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)</div><div class='ctx'> 		q_properties-&gt;type = KFD_QUEUE_TYPE_COMPUTE;</div><div class='hunk'>@@ -262,6 +266,8 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,</div><div class='ctx'> 		q_properties-&gt;type = KFD_QUEUE_TYPE_SDMA;</div><div class='ctx'> 	else if (args-&gt;queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)</div><div class='ctx'> 		q_properties-&gt;type = KFD_QUEUE_TYPE_SDMA_XGMI;</div><div class='add'>+	else if (args-&gt;queue_type == KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID)</div><div class='add'>+		q_properties-&gt;type = KFD_QUEUE_TYPE_SDMA_BY_ENG_ID;</div><div class='ctx'> 	else</div><div class='ctx'> 		return -ENOTSUPP;</div><div class='ctx'> </div><div class='hunk'>@@ -306,7 +312,6 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,</div><div class='ctx'> 	struct kfd_process_device *pdd;</div><div class='ctx'> 	struct queue_properties q_properties;</div><div class='ctx'> 	uint32_t doorbell_offset_in_process = 0;</div><div class='del'>-	struct amdgpu_bo *wptr_bo = NULL;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;q_properties, 0, sizeof(struct queue_properties));</div><div class='ctx'> </div><div class='hunk'>@@ -334,6 +339,18 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,</div><div class='ctx'> 		goto err_bind_process;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (q_properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) {</div><div class='add'>+		int max_sdma_eng_id = kfd_get_num_sdma_engines(dev) +</div><div class='add'>+				      kfd_get_num_xgmi_sdma_engines(dev) - 1;</div><div class='add'>+</div><div class='add'>+		if (q_properties.sdma_engine_id &gt; max_sdma_eng_id) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			pr_err("sdma_engine_id %i exceeds maximum id of %i\n",</div><div class='add'>+			       q_properties.sdma_engine_id, max_sdma_eng_id);</div><div class='add'>+			goto err_sdma_engine_id;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!pdd-&gt;qpd.proc_doorbells) {</div><div class='ctx'> 		err = kfd_alloc_process_doorbells(dev-&gt;kfd, pdd);</div><div class='ctx'> 		if (err) {</div><div class='hunk'>@@ -342,48 +359,17 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work</div><div class='del'>-	 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)</div><div class='del'>-	 */</div><div class='del'>-	if (dev-&gt;kfd-&gt;shared_resources.enable_mes &amp;&amp;</div><div class='del'>-			((dev-&gt;adev-&gt;mes.sched_version &amp; AMDGPU_MES_API_VERSION_MASK)</div><div class='del'>-			&gt;&gt; AMDGPU_MES_API_VERSION_SHIFT) &gt;= 2) {</div><div class='del'>-		struct amdgpu_bo_va_mapping *wptr_mapping;</div><div class='del'>-		struct amdgpu_vm *wptr_vm;</div><div class='del'>-</div><div class='del'>-		wptr_vm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='del'>-		err = amdgpu_bo_reserve(wptr_vm-&gt;root.bo, false);</div><div class='del'>-		if (err)</div><div class='del'>-			goto err_wptr_map_gart;</div><div class='del'>-</div><div class='del'>-		wptr_mapping = amdgpu_vm_bo_lookup_mapping(</div><div class='del'>-				wptr_vm, args-&gt;write_pointer_address &gt;&gt; PAGE_SHIFT);</div><div class='del'>-		amdgpu_bo_unreserve(wptr_vm-&gt;root.bo);</div><div class='del'>-		if (!wptr_mapping) {</div><div class='del'>-			pr_err("Failed to lookup wptr bo\n");</div><div class='del'>-			err = -EINVAL;</div><div class='del'>-			goto err_wptr_map_gart;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		wptr_bo = wptr_mapping-&gt;bo_va-&gt;base.bo;</div><div class='del'>-		if (wptr_bo-&gt;tbo.base.size &gt; PAGE_SIZE) {</div><div class='del'>-			pr_err("Requested GART mapping for wptr bo larger than one page\n");</div><div class='del'>-			err = -EINVAL;</div><div class='del'>-			goto err_wptr_map_gart;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		err = amdgpu_amdkfd_map_gtt_bo_to_gart(wptr_bo);</div><div class='del'>-		if (err) {</div><div class='del'>-			pr_err("Failed to map wptr bo to GART\n");</div><div class='del'>-			goto err_wptr_map_gart;</div><div class='del'>-		}</div><div class='add'>+	err = kfd_queue_acquire_buffers(pdd, &amp;q_properties);</div><div class='add'>+	if (err) {</div><div class='add'>+		pr_debug("failed to acquire user queue buffers\n");</div><div class='add'>+		goto err_acquire_queue_buf;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",</div><div class='del'>-			p-&gt;pasid,</div><div class='add'>+	pr_debug("Creating queue for process pid %d on gpu 0x%x\n",</div><div class='add'>+			p-&gt;lead_thread-&gt;pid,</div><div class='ctx'> 			dev-&gt;id);</div><div class='ctx'> </div><div class='del'>-	err = pqm_create_queue(&amp;p-&gt;pqm, dev, filep, &amp;q_properties, &amp;queue_id, wptr_bo,</div><div class='add'>+	err = pqm_create_queue(&amp;p-&gt;pqm, dev, &amp;q_properties, &amp;queue_id,</div><div class='ctx'> 			NULL, NULL, NULL, &amp;doorbell_offset_in_process);</div><div class='ctx'> 	if (err != 0)</div><div class='ctx'> 		goto err_create_queue;</div><div class='hunk'>@@ -417,9 +403,10 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_create_queue:</div><div class='del'>-	if (wptr_bo)</div><div class='del'>-		amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, wptr_bo);</div><div class='del'>-err_wptr_map_gart:</div><div class='add'>+	kfd_queue_unref_bo_vas(pdd, &amp;q_properties);</div><div class='add'>+	kfd_queue_release_buffers(pdd, &amp;q_properties);</div><div class='add'>+err_acquire_queue_buf:</div><div class='add'>+err_sdma_engine_id:</div><div class='ctx'> err_bind_process:</div><div class='ctx'> err_pdd:</div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;mutex);</div><div class='hunk'>@@ -432,9 +419,9 @@ static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,</div><div class='ctx'> 	int retval;</div><div class='ctx'> 	struct kfd_ioctl_destroy_queue_args *args = data;</div><div class='ctx'> </div><div class='del'>-	pr_debug("Destroying queue id %d for pasid 0x%x\n",</div><div class='add'>+	pr_debug("Destroying queue id %d for process pid %d\n",</div><div class='ctx'> 				args-&gt;queue_id,</div><div class='del'>-				p-&gt;pasid);</div><div class='add'>+				p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;p-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -478,6 +465,11 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (args-&gt;ring_size &lt; KFD_MIN_QUEUE_RING_SIZE) {</div><div class='add'>+		args-&gt;ring_size = KFD_MIN_QUEUE_RING_SIZE;</div><div class='add'>+		pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	properties.queue_address = args-&gt;ring_base_address;</div><div class='ctx'> 	properties.queue_size = args-&gt;ring_size;</div><div class='ctx'> 	properties.queue_percent = args-&gt;queue_percentage &amp; 0xFF;</div><div class='hunk'>@@ -485,8 +477,8 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,</div><div class='ctx'> 	properties.pm4_target_xcc = (args-&gt;queue_percentage &gt;&gt; 8) &amp; 0xFF;</div><div class='ctx'> 	properties.priority = args-&gt;queue_priority;</div><div class='ctx'> </div><div class='del'>-	pr_debug("Updating queue id %d for pasid 0x%x\n",</div><div class='del'>-			args-&gt;queue_id, p-&gt;pasid);</div><div class='add'>+	pr_debug("Updating queue id %d for process pid %d\n",</div><div class='add'>+			args-&gt;queue_id, p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;p-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -529,15 +521,10 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,</div><div class='ctx'> 		cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);</div><div class='del'>-	if (!minfo.cu_mask.ptr)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);</div><div class='del'>-	if (retval) {</div><div class='add'>+	minfo.cu_mask.ptr = memdup_user(cu_mask_ptr, cu_mask_size);</div><div class='add'>+	if (IS_ERR(minfo.cu_mask.ptr)) {</div><div class='ctx'> 		pr_debug("Could not copy CU mask from userspace");</div><div class='del'>-		retval = -EFAULT;</div><div class='del'>-		goto out;</div><div class='add'>+		return PTR_ERR(minfo.cu_mask.ptr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;p-&gt;mutex);</div><div class='hunk'>@@ -546,7 +533,6 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-out:</div><div class='ctx'> 	kfree(minfo.cu_mask.ptr);</div><div class='ctx'> 	return retval;</div><div class='ctx'> }</div><div class='hunk'>@@ -613,7 +599,8 @@ static int kfd_ioctl_set_memory_policy(struct file *filep,</div><div class='ctx'> 				default_policy,</div><div class='ctx'> 				alternate_policy,</div><div class='ctx'> 				(void __user *)args-&gt;alternate_aperture_base,</div><div class='del'>-				args-&gt;alternate_aperture_size))</div><div class='add'>+				args-&gt;alternate_aperture_size,</div><div class='add'>+				args-&gt;misc_process_flag))</div><div class='ctx'> 		err = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='hunk'>@@ -712,7 +699,7 @@ static int kfd_ioctl_get_process_apertures(struct file *filp,</div><div class='ctx'> 	struct kfd_process_device_apertures *pAperture;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(kfd_device, "get apertures for PASID 0x%x", p-&gt;pasid);</div><div class='add'>+	dev_dbg(kfd_device, "get apertures for process pid %d", p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	args-&gt;num_of_nodes = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -764,7 +751,8 @@ static int kfd_ioctl_get_process_apertures_new(struct file *filp,</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(kfd_device, "get apertures for PASID 0x%x", p-&gt;pasid);</div><div class='add'>+	dev_dbg(kfd_device, "get apertures for process pid %d",</div><div class='add'>+			p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	if (args-&gt;num_of_nodes == 0) {</div><div class='ctx'> 		/* Return number of nodes, so that user space can alloacate</div><div class='hunk'>@@ -779,8 +767,8 @@ static int kfd_ioctl_get_process_apertures_new(struct file *filp,</div><div class='ctx'> 	 * nodes, but not more than args-&gt;num_of_nodes as that is</div><div class='ctx'> 	 * the amount of memory allocated by user</div><div class='ctx'> 	 */</div><div class='del'>-	pa = kzalloc((sizeof(struct kfd_process_device_apertures) *</div><div class='del'>-				args-&gt;num_of_nodes), GFP_KERNEL);</div><div class='add'>+	pa = kcalloc(args-&gt;num_of_nodes, sizeof(struct kfd_process_device_apertures),</div><div class='add'>+		     GFP_KERNEL);</div><div class='ctx'> 	if (!pa)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -1076,7 +1064,12 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,</div><div class='ctx'> 	svm_range_list_lock_and_flush_work(&amp;p-&gt;svms, current-&gt;mm);</div><div class='ctx'> 	mutex_lock(&amp;p-&gt;svms.lock);</div><div class='ctx'> 	mmap_write_unlock(current-&gt;mm);</div><div class='del'>-	if (interval_tree_iter_first(&amp;p-&gt;svms.objects,</div><div class='add'>+</div><div class='add'>+	/* Skip a special case that allocates VRAM without VA,</div><div class='add'>+	 * VA will be invalid of 0.</div><div class='add'>+	 */</div><div class='add'>+	if (!(!args-&gt;va_addr &amp;&amp; (flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_VRAM)) &amp;&amp;</div><div class='add'>+	    interval_tree_iter_first(&amp;p-&gt;svms.objects,</div><div class='ctx'> 				     args-&gt;va_addr &gt;&gt; PAGE_SHIFT,</div><div class='ctx'> 				     (args-&gt;va_addr + args-&gt;size - 1) &gt;&gt; PAGE_SHIFT)) {</div><div class='ctx'> 		pr_err("Address: 0x%llx already allocated by SVM\n",</div><div class='hunk'>@@ -1139,7 +1132,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,</div><div class='ctx'> 			goto err_unlock;</div><div class='ctx'> 		}</div><div class='ctx'> 		offset = dev-&gt;adev-&gt;rmmio_remap.bus_addr;</div><div class='del'>-		if (!offset) {</div><div class='add'>+		if (!offset || (PAGE_SIZE &gt; 4096)) {</div><div class='ctx'> 			err = -ENOMEM;</div><div class='ctx'> 			goto err_unlock;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1165,7 +1158,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,</div><div class='ctx'> </div><div class='ctx'> 		if (flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)</div><div class='ctx'> 			size &gt;&gt;= 1;</div><div class='del'>-		WRITE_ONCE(pdd-&gt;vram_usage, pdd-&gt;vram_usage + PAGE_ALIGN(size));</div><div class='add'>+		atomic64_add(PAGE_ALIGN(size), &amp;pdd-&gt;vram_usage);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;mutex);</div><div class='hunk'>@@ -1236,7 +1229,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep,</div><div class='ctx'> 		kfd_process_device_remove_obj_handle(</div><div class='ctx'> 			pdd, GET_IDR_HANDLE(args-&gt;handle));</div><div class='ctx'> </div><div class='del'>-	WRITE_ONCE(pdd-&gt;vram_usage, pdd-&gt;vram_usage - size);</div><div class='add'>+	atomic64_sub(size, &amp;pdd-&gt;vram_usage);</div><div class='ctx'> </div><div class='ctx'> err_unlock:</div><div class='ctx'> err_pdd:</div><div class='hunk'>@@ -1417,8 +1410,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,</div><div class='ctx'> 		err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(</div><div class='ctx'> 			peer_pdd-&gt;dev-&gt;adev, (struct kgd_mem *)mem, peer_pdd-&gt;drm_priv);</div><div class='ctx'> 		if (err) {</div><div class='del'>-			pr_err("Failed to unmap from gpu %d/%d\n",</div><div class='del'>-			       i, args-&gt;n_devices);</div><div class='add'>+			pr_debug("Failed to unmap from gpu %d/%d\n", i, args-&gt;n_devices);</div><div class='ctx'> 			goto unmap_memory_from_gpu_failed;</div><div class='ctx'> 		}</div><div class='ctx'> 		args-&gt;n_success = i+1;</div><div class='hunk'>@@ -1523,7 +1515,7 @@ static int kfd_ioctl_get_dmabuf_info(struct file *filep,</div><div class='ctx'> </div><div class='ctx'> 	/* Find a KFD GPU device that supports the get_dmabuf_info query */</div><div class='ctx'> 	for (i = 0; kfd_topology_enum_kfd_devices(i, &amp;dev) == 0; i++)</div><div class='del'>-		if (dev)</div><div class='add'>+		if (dev &amp;&amp; !kfd_devcgroup_check_permission(dev))</div><div class='ctx'> 			break;</div><div class='ctx'> 	if (!dev)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1545,7 +1537,7 @@ static int kfd_ioctl_get_dmabuf_info(struct file *filep,</div><div class='ctx'> 	if (xcp_id &gt;= 0)</div><div class='ctx'> 		args-&gt;gpu_id = dmabuf_adev-&gt;kfd.dev-&gt;nodes[xcp_id]-&gt;id;</div><div class='ctx'> 	else</div><div class='del'>-		args-&gt;gpu_id = dmabuf_adev-&gt;kfd.dev-&gt;nodes[0]-&gt;id;</div><div class='add'>+		args-&gt;gpu_id = dev-&gt;id;</div><div class='ctx'> 	args-&gt;flags = flags;</div><div class='ctx'> </div><div class='ctx'> 	/* Copy metadata buffer to user mode */</div><div class='hunk'>@@ -1852,7 +1844,8 @@ static uint32_t get_process_num_bos(struct kfd_process *p)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int criu_get_prime_handle(struct kgd_mem *mem,</div><div class='del'>-				 int flags, u32 *shared_fd)</div><div class='add'>+				 int flags, u32 *shared_fd,</div><div class='add'>+				 struct file **file)</div><div class='ctx'> {</div><div class='ctx'> 	struct dma_buf *dmabuf;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1863,13 +1856,14 @@ static int criu_get_prime_handle(struct kgd_mem *mem,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = dma_buf_fd(dmabuf, flags);</div><div class='add'>+	ret = get_unused_fd_flags(flags);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		pr_err("dmabuf create fd failed, ret:%d\n", ret);</div><div class='ctx'> 		goto out_free_dmabuf;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	*shared_fd = ret;</div><div class='add'>+	*file = dmabuf-&gt;file;</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_free_dmabuf:</div><div class='hunk'>@@ -1877,6 +1871,25 @@ out_free_dmabuf:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void commit_files(struct file **files,</div><div class='add'>+			 struct kfd_criu_bo_bucket *bo_buckets,</div><div class='add'>+			 unsigned int count,</div><div class='add'>+			 int err)</div><div class='add'>+{</div><div class='add'>+	while (count--) {</div><div class='add'>+		struct file *file = files[count];</div><div class='add'>+</div><div class='add'>+		if (!file)</div><div class='add'>+			continue;</div><div class='add'>+		if (err) {</div><div class='add'>+			fput(file);</div><div class='add'>+			put_unused_fd(bo_buckets[count].dmabuf_fd);</div><div class='add'>+		} else {</div><div class='add'>+			fd_install(bo_buckets[count].dmabuf_fd, file);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> 			       uint32_t num_bos,</div><div class='ctx'> 			       uint8_t __user *user_bos,</div><div class='hunk'>@@ -1885,6 +1898,7 @@ static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_criu_bo_bucket *bo_buckets;</div><div class='ctx'> 	struct kfd_criu_bo_priv_data *bo_privs;</div><div class='add'>+	struct file **files = NULL;</div><div class='ctx'> 	int ret = 0, pdd_index, bo_index = 0, id;</div><div class='ctx'> 	void *mem;</div><div class='ctx'> </div><div class='hunk'>@@ -1898,6 +1912,12 @@ static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	files = kvzalloc(num_bos * sizeof(struct file *), GFP_KERNEL);</div><div class='add'>+	if (!files) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for (pdd_index = 0; pdd_index &lt; p-&gt;n_pdds; pdd_index++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = p-&gt;pdds[pdd_index];</div><div class='ctx'> 		struct amdgpu_bo *dumper_bo;</div><div class='hunk'>@@ -1908,11 +1928,6 @@ static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> 			struct kfd_criu_bo_priv_data *bo_priv;</div><div class='ctx'> 			int i, dev_idx = 0;</div><div class='ctx'> </div><div class='del'>-			if (!mem) {</div><div class='del'>-				ret = -ENOMEM;</div><div class='del'>-				goto exit;</div><div class='del'>-			}</div><div class='del'>-</div><div class='ctx'> 			kgd_mem = (struct kgd_mem *)mem;</div><div class='ctx'> 			dumper_bo = kgd_mem-&gt;bo;</div><div class='ctx'> </div><div class='hunk'>@@ -1945,7 +1960,7 @@ static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> 				ret = criu_get_prime_handle(kgd_mem,</div><div class='ctx'> 						bo_bucket-&gt;alloc_flags &amp;</div><div class='ctx'> 						KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,</div><div class='del'>-						&amp;bo_bucket-&gt;dmabuf_fd);</div><div class='add'>+						&amp;bo_bucket-&gt;dmabuf_fd, &amp;files[bo_index]);</div><div class='ctx'> 				if (ret)</div><div class='ctx'> 					goto exit;</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -1963,7 +1978,7 @@ static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> 				bo_bucket-&gt;offset = amdgpu_bo_mmap_offset(dumper_bo);</div><div class='ctx'> </div><div class='ctx'> 			for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='del'>-				if (amdgpu_amdkfd_bo_mapped_to_dev(p-&gt;pdds[i]-&gt;dev-&gt;adev, kgd_mem))</div><div class='add'>+				if (amdgpu_amdkfd_bo_mapped_to_dev(p-&gt;pdds[i]-&gt;drm_priv, kgd_mem))</div><div class='ctx'> 					bo_priv-&gt;mapped_gpuids[dev_idx++] = p-&gt;pdds[i]-&gt;user_gpu_id;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -1996,12 +2011,8 @@ static int criu_checkpoint_bos(struct kfd_process *p,</div><div class='ctx'> 	*priv_offset += num_bos * sizeof(*bo_privs);</div><div class='ctx'> </div><div class='ctx'> exit:</div><div class='del'>-	while (ret &amp;&amp; bo_index--) {</div><div class='del'>-		if (bo_buckets[bo_index].alloc_flags</div><div class='del'>-		    &amp; (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))</div><div class='del'>-			close_fd(bo_buckets[bo_index].dmabuf_fd);</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+	commit_files(files, bo_buckets, bo_index, ret);</div><div class='add'>+	kvfree(files);</div><div class='ctx'> 	kvfree(bo_buckets);</div><div class='ctx'> 	kvfree(bo_privs);</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -2026,9 +2037,7 @@ static int criu_get_process_object_info(struct kfd_process *p,</div><div class='ctx'> </div><div class='ctx'> 	num_events = kfd_get_num_events(p);</div><div class='ctx'> </div><div class='del'>-	ret = svm_range_get_info(p, &amp;num_svm_ranges, &amp;svm_priv_data_size);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+	svm_range_get_info(p, &amp;num_svm_ranges, &amp;svm_priv_data_size);</div><div class='ctx'> </div><div class='ctx'> 	*num_objects = num_queues + num_events + num_svm_ranges;</div><div class='ctx'> </div><div class='hunk'>@@ -2307,7 +2316,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> 		offset = pdd-&gt;dev-&gt;adev-&gt;rmmio_remap.bus_addr;</div><div class='del'>-		if (!offset) {</div><div class='add'>+		if (!offset || (PAGE_SIZE &gt; 4096)) {</div><div class='ctx'> 			pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2346,14 +2355,15 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,</div><div class='ctx'> 	} else if (bo_bucket-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {</div><div class='ctx'> 		bo_bucket-&gt;restored_offset = offset;</div><div class='ctx'> 		/* Update the VRAM usage count */</div><div class='del'>-		WRITE_ONCE(pdd-&gt;vram_usage, pdd-&gt;vram_usage + bo_bucket-&gt;size);</div><div class='add'>+		atomic64_add(bo_bucket-&gt;size, &amp;pdd-&gt;vram_usage);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int criu_restore_bo(struct kfd_process *p,</div><div class='ctx'> 			   struct kfd_criu_bo_bucket *bo_bucket,</div><div class='del'>-			   struct kfd_criu_bo_priv_data *bo_priv)</div><div class='add'>+			   struct kfd_criu_bo_priv_data *bo_priv,</div><div class='add'>+			   struct file **file)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process_device *pdd;</div><div class='ctx'> 	struct kgd_mem *kgd_mem;</div><div class='hunk'>@@ -2405,7 +2415,7 @@ static int criu_restore_bo(struct kfd_process *p,</div><div class='ctx'> 	if (bo_bucket-&gt;alloc_flags</div><div class='ctx'> 	    &amp; (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {</div><div class='ctx'> 		ret = criu_get_prime_handle(kgd_mem, DRM_RDWR,</div><div class='del'>-					    &amp;bo_bucket-&gt;dmabuf_fd);</div><div class='add'>+					    &amp;bo_bucket-&gt;dmabuf_fd, file);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -2422,6 +2432,7 @@ static int criu_restore_bos(struct kfd_process *p,</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_criu_bo_bucket *bo_buckets = NULL;</div><div class='ctx'> 	struct kfd_criu_bo_priv_data *bo_privs = NULL;</div><div class='add'>+	struct file **files = NULL;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	uint32_t i = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -2435,6 +2446,12 @@ static int criu_restore_bos(struct kfd_process *p,</div><div class='ctx'> 	if (!bo_buckets)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	files = kvzalloc(args-&gt;num_bos * sizeof(struct file *), GFP_KERNEL);</div><div class='add'>+	if (!files) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = copy_from_user(bo_buckets, (void __user *)args-&gt;bos,</div><div class='ctx'> 			     args-&gt;num_bos * sizeof(*bo_buckets));</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2460,7 +2477,7 @@ static int criu_restore_bos(struct kfd_process *p,</div><div class='ctx'> </div><div class='ctx'> 	/* Create and map new BOs */</div><div class='ctx'> 	for (; i &lt; args-&gt;num_bos; i++) {</div><div class='del'>-		ret = criu_restore_bo(p, &amp;bo_buckets[i], &amp;bo_privs[i]);</div><div class='add'>+		ret = criu_restore_bo(p, &amp;bo_buckets[i], &amp;bo_privs[i], &amp;files[i]);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);</div><div class='ctx'> 			goto exit;</div><div class='hunk'>@@ -2475,11 +2492,8 @@ static int criu_restore_bos(struct kfd_process *p,</div><div class='ctx'> 		ret = -EFAULT;</div><div class='ctx'> </div><div class='ctx'> exit:</div><div class='del'>-	while (ret &amp;&amp; i--) {</div><div class='del'>-		if (bo_buckets[i].alloc_flags</div><div class='del'>-		   &amp; (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))</div><div class='del'>-			close_fd(bo_buckets[i].dmabuf_fd);</div><div class='del'>-	}</div><div class='add'>+	commit_files(files, bo_buckets, i, ret);</div><div class='add'>+	kvfree(files);</div><div class='ctx'> 	kvfree(bo_buckets);</div><div class='ctx'> 	kvfree(bo_privs);</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -2551,8 +2565,8 @@ static int criu_restore(struct file *filep,</div><div class='ctx'> 	pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",</div><div class='ctx'> 		 args-&gt;num_devices, args-&gt;num_bos, args-&gt;num_objects, args-&gt;priv_data_size);</div><div class='ctx'> </div><div class='del'>-	if (!args-&gt;bos || !args-&gt;devices || !args-&gt;priv_data || !args-&gt;priv_data_size ||</div><div class='del'>-	    !args-&gt;num_devices || !args-&gt;num_bos)</div><div class='add'>+	if ((args-&gt;num_bos &gt; 0 &amp;&amp; !args-&gt;bos) || !args-&gt;devices || !args-&gt;priv_data ||</div><div class='add'>+	    !args-&gt;priv_data_size || !args-&gt;num_devices)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;p-&gt;mutex);</div><div class='hunk'>@@ -2812,7 +2826,7 @@ retry:</div><div class='ctx'> </div><div class='ctx'> static int runtime_disable(struct kfd_process *p)</div><div class='ctx'> {</div><div class='del'>-	int i = 0, ret;</div><div class='add'>+	int i = 0, ret = 0;</div><div class='ctx'> 	bool was_enabled = p-&gt;runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;</div><div class='ctx'> </div><div class='ctx'> 	p-&gt;runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED;</div><div class='hunk'>@@ -2849,6 +2863,7 @@ static int runtime_disable(struct kfd_process *p)</div><div class='ctx'> 	/* disable ttmp setup */</div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = p-&gt;pdds[i];</div><div class='add'>+		int last_err = 0;</div><div class='ctx'> </div><div class='ctx'> 		if (kfd_dbg_is_per_vmid_supported(pdd-&gt;dev)) {</div><div class='ctx'> 			pdd-&gt;spi_dbg_override =</div><div class='hunk'>@@ -2858,14 +2873,17 @@ static int runtime_disable(struct kfd_process *p)</div><div class='ctx'> 					pdd-&gt;dev-&gt;vm_info.last_vmid_kfd);</div><div class='ctx'> </div><div class='ctx'> 			if (!pdd-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-				debug_refresh_runlist(pdd-&gt;dev-&gt;dqm);</div><div class='add'>+				last_err = debug_refresh_runlist(pdd-&gt;dev-&gt;dqm);</div><div class='ctx'> 			else</div><div class='del'>-				kfd_dbg_set_mes_debug_mode(pdd,</div><div class='add'>+				last_err = kfd_dbg_set_mes_debug_mode(pdd,</div><div class='ctx'> 							   !kfd_dbg_has_cwsr_workaround(pdd-&gt;dev));</div><div class='add'>+</div><div class='add'>+			if (last_err)</div><div class='add'>+				ret = last_err;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)</div><div class='hunk'>@@ -3237,8 +3255,10 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)</div><div class='ctx'> 	int retcode = -EINVAL;</div><div class='ctx'> 	bool ptrace_attached = false;</div><div class='ctx'> </div><div class='del'>-	if (nr &gt;= AMDKFD_CORE_IOCTL_COUNT)</div><div class='add'>+	if (nr &gt;= AMDKFD_CORE_IOCTL_COUNT) {</div><div class='add'>+		retcode = -ENOTTY;</div><div class='ctx'> 		goto err_i1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if ((nr &gt;= AMDKFD_COMMAND_START) &amp;&amp; (nr &lt; AMDKFD_COMMAND_END)) {</div><div class='ctx'> 		u32 amdkfd_size;</div><div class='hunk'>@@ -3251,8 +3271,10 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)</div><div class='ctx'> 			asize = amdkfd_size;</div><div class='ctx'> </div><div class='ctx'> 		cmd = ioctl-&gt;cmd;</div><div class='del'>-	} else</div><div class='add'>+	} else {</div><div class='add'>+		retcode = -ENOTTY;</div><div class='ctx'> 		goto err_i1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);</div><div class='ctx'> </div><div class='hunk'>@@ -3349,6 +3371,9 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,</div><div class='ctx'> 	if (vma-&gt;vm_end - vma-&gt;vm_start != PAGE_SIZE)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (PAGE_SIZE &gt; 4096)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	address = dev-&gt;adev-&gt;rmmio_remap.bus_addr;</div><div class='ctx'> </div><div class='ctx'> 	vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |</div><div class='hunk'>@@ -3356,12 +3381,12 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,</div><div class='ctx'> </div><div class='ctx'> 	vma-&gt;vm_page_prot = pgprot_noncached(vma-&gt;vm_page_prot);</div><div class='ctx'> </div><div class='del'>-	pr_debug("pasid 0x%x mapping mmio page\n"</div><div class='add'>+	pr_debug("process pid %d mapping mmio page\n"</div><div class='ctx'> 		 "     target user address == 0x%08llX\n"</div><div class='ctx'> 		 "     physical address    == 0x%08llX\n"</div><div class='ctx'> 		 "     vm_flags            == 0x%04lX\n"</div><div class='ctx'> 		 "     size                == 0x%04lX\n",</div><div class='del'>-		 process-&gt;pasid, (unsigned long long) vma-&gt;vm_start,</div><div class='add'>+		 process-&gt;lead_thread-&gt;pid, (unsigned long long) vma-&gt;vm_start,</div><div class='ctx'> 		 address, vma-&gt;vm_flags, PAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return io_remap_pfn_range(vma,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c<br/>index 7f2ae0d15d4a..4a7180b46b71 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_crat.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_crat.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_crat.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_crat.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #include "kfd_topology.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_amdkfd.h"</div><div class='add'>+#include "amdgpu_xgmi.h"</div><div class='ctx'> </div><div class='ctx'> /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.</div><div class='ctx'>  * GPU processor ID are expressed with Bit[31]=1.</div><div class='hunk'>@@ -1422,6 +1423,7 @@ err:</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='add'>+						   bool cache_line_size_missing,</div><div class='ctx'> 						   struct kfd_gpu_cache_info *pcache_info)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = kdev-&gt;adev;</div><div class='hunk'>@@ -1434,7 +1436,10 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='ctx'> 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='del'>-		pcache_info[0].num_cu_shared = adev-&gt;gfx.config.gc_num_tcp_per_wpg / 2;</div><div class='add'>+		pcache_info[i].num_cu_shared = adev-&gt;gfx.config.gc_num_tcp_per_wpg / 2;</div><div class='add'>+		pcache_info[i].cache_line_size = adev-&gt;gfx.config.gc_tcp_cache_line_size;</div><div class='add'>+		if (cache_line_size_missing &amp;&amp; !pcache_info[i].cache_line_size)</div><div class='add'>+			pcache_info[i].cache_line_size = 128;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Scalar L1 Instruction Cache per SQC */</div><div class='hunk'>@@ -1446,6 +1451,9 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='ctx'> 					CRAT_CACHE_FLAGS_INST_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='ctx'> 		pcache_info[i].num_cu_shared = adev-&gt;gfx.config.gc_num_sqc_per_wgp * 2;</div><div class='add'>+		pcache_info[i].cache_line_size = adev-&gt;gfx.config.gc_instruction_cache_line_size;</div><div class='add'>+		if (cache_line_size_missing &amp;&amp; !pcache_info[i].cache_line_size)</div><div class='add'>+			pcache_info[i].cache_line_size = 128;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Scalar L1 Data Cache per SQC */</div><div class='hunk'>@@ -1456,6 +1464,9 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='ctx'> 		pcache_info[i].num_cu_shared = adev-&gt;gfx.config.gc_num_sqc_per_wgp * 2;</div><div class='add'>+		pcache_info[i].cache_line_size = adev-&gt;gfx.config.gc_scalar_data_cache_line_size;</div><div class='add'>+		if (cache_line_size_missing &amp;&amp; !pcache_info[i].cache_line_size)</div><div class='add'>+			pcache_info[i].cache_line_size = 64;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* GL1 Data Cache per SA */</div><div class='hunk'>@@ -1468,6 +1479,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='ctx'> 		pcache_info[i].num_cu_shared = adev-&gt;gfx.config.max_cu_per_sh;</div><div class='add'>+		if (cache_line_size_missing)</div><div class='add'>+			pcache_info[i].cache_line_size = 128;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* L2 Data Cache per GPU (Total Tex Cache) */</div><div class='hunk'>@@ -1478,6 +1491,9 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='ctx'> 		pcache_info[i].num_cu_shared = adev-&gt;gfx.config.max_cu_per_sh;</div><div class='add'>+		pcache_info[i].cache_line_size = adev-&gt;gfx.config.gc_tcc_cache_line_size;</div><div class='add'>+		if (cache_line_size_missing &amp;&amp; !pcache_info[i].cache_line_size)</div><div class='add'>+			pcache_info[i].cache_line_size = 128;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* L3 Data Cache per GPU */</div><div class='hunk'>@@ -1488,6 +1504,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='ctx'> 		pcache_info[i].num_cu_shared = adev-&gt;gfx.config.max_cu_per_sh;</div><div class='add'>+		pcache_info[i].cache_line_size = 64;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> 	return i;</div><div class='hunk'>@@ -1503,6 +1520,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,</div><div class='ctx'> 	if (adev-&gt;gfx.config.gc_tcp_size_per_cu) {</div><div class='ctx'> 		pcache_info[i].cache_size = adev-&gt;gfx.config.gc_tcp_size_per_cu;</div><div class='ctx'> 		pcache_info[i].cache_level = 1;</div><div class='add'>+		/* Cacheline size not available in IP discovery for gc943,gc944 */</div><div class='add'>+		pcache_info[i].cache_line_size = 128;</div><div class='ctx'> 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='hunk'>@@ -1514,6 +1533,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,</div><div class='ctx'> 		pcache_info[i].cache_size =</div><div class='ctx'> 			adev-&gt;gfx.config.gc_l1_instruction_cache_size_per_sqc;</div><div class='ctx'> 		pcache_info[i].cache_level = 1;</div><div class='add'>+		pcache_info[i].cache_line_size = 64;</div><div class='ctx'> 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_INST_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='hunk'>@@ -1524,6 +1544,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,</div><div class='ctx'> 	if (adev-&gt;gfx.config.gc_l1_data_cache_size_per_sqc) {</div><div class='ctx'> 		pcache_info[i].cache_size = adev-&gt;gfx.config.gc_l1_data_cache_size_per_sqc;</div><div class='ctx'> 		pcache_info[i].cache_level = 1;</div><div class='add'>+		pcache_info[i].cache_line_size = 64;</div><div class='ctx'> 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='hunk'>@@ -1534,6 +1555,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,</div><div class='ctx'> 	if (adev-&gt;gfx.config.gc_tcc_size) {</div><div class='ctx'> 		pcache_info[i].cache_size = adev-&gt;gfx.config.gc_tcc_size;</div><div class='ctx'> 		pcache_info[i].cache_level = 2;</div><div class='add'>+		pcache_info[i].cache_line_size = 128;</div><div class='ctx'> 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='hunk'>@@ -1544,6 +1566,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,</div><div class='ctx'> 	if (adev-&gt;gmc.mall_size) {</div><div class='ctx'> 		pcache_info[i].cache_size = adev-&gt;gmc.mall_size / 1024;</div><div class='ctx'> 		pcache_info[i].cache_level = 3;</div><div class='add'>+		pcache_info[i].cache_line_size = 64;</div><div class='ctx'> 		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_DATA_CACHE |</div><div class='ctx'> 					CRAT_CACHE_FLAGS_SIMD_CACHE);</div><div class='hunk'>@@ -1556,6 +1579,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,</div><div class='ctx'> int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info)</div><div class='ctx'> {</div><div class='ctx'> 	int num_of_cache_types = 0;</div><div class='add'>+	bool cache_line_size_missing = false;</div><div class='ctx'> </div><div class='ctx'> 	switch (kdev-&gt;adev-&gt;asic_type) {</div><div class='ctx'> 	case CHIP_KAVERI:</div><div class='hunk'>@@ -1614,6 +1638,8 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc</div><div class='ctx'> 			num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case IP_VERSION(9, 4, 3):</div><div class='add'>+		case IP_VERSION(9, 4, 4):</div><div class='add'>+		case IP_VERSION(9, 5, 0):</div><div class='ctx'> 			num_of_cache_types =</div><div class='ctx'> 				kfd_fill_gpu_cache_info_from_gfx_config_v2(kdev-&gt;kfd,</div><div class='ctx'> 									*pcache_info);</div><div class='hunk'>@@ -1677,8 +1703,19 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc</div><div class='ctx'> 		case IP_VERSION(11, 0, 4):</div><div class='ctx'> 		case IP_VERSION(11, 5, 0):</div><div class='ctx'> 		case IP_VERSION(11, 5, 1):</div><div class='add'>+		case IP_VERSION(11, 5, 2):</div><div class='add'>+		case IP_VERSION(11, 5, 3):</div><div class='add'>+			/* Cacheline size not available in IP discovery for gc11.</div><div class='add'>+			 * kfd_fill_gpu_cache_info_from_gfx_config to hard code it</div><div class='add'>+			 */</div><div class='add'>+			cache_line_size_missing = true;</div><div class='add'>+			fallthrough;</div><div class='add'>+		case IP_VERSION(12, 0, 0):</div><div class='add'>+		case IP_VERSION(12, 0, 1):</div><div class='ctx'> 			num_of_cache_types =</div><div class='del'>-				kfd_fill_gpu_cache_info_from_gfx_config(kdev-&gt;kfd, *pcache_info);</div><div class='add'>+				kfd_fill_gpu_cache_info_from_gfx_config(kdev-&gt;kfd,</div><div class='add'>+									cache_line_size_missing,</div><div class='add'>+									*pcache_info);</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			*pcache_info = dummy_cache_info;</div><div class='hunk'>@@ -2096,9 +2133,6 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,</div><div class='ctx'> 		bool ext_cpu = KFD_GC_VERSION(kdev) != IP_VERSION(9, 4, 3);</div><div class='ctx'> 		int mem_bw = 819200, weight = ext_cpu ? KFD_CRAT_XGMI_WEIGHT :</div><div class='ctx'> 							KFD_CRAT_INTRA_SOCKET_WEIGHT;</div><div class='del'>-		uint32_t bandwidth = ext_cpu ? amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(</div><div class='del'>-							kdev-&gt;adev, NULL, true) : mem_bw;</div><div class='del'>-</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * with host gpu xgmi link, host can access gpu memory whether</div><div class='ctx'> 		 * or not pcie bar type is large, so always create bidirectional</div><div class='hunk'>@@ -2107,8 +2141,16 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,</div><div class='ctx'> 		sub_type_hdr-&gt;flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;</div><div class='ctx'> 		sub_type_hdr-&gt;io_interface_type = CRAT_IOLINK_TYPE_XGMI;</div><div class='ctx'> 		sub_type_hdr-&gt;weight_xgmi = weight;</div><div class='del'>-		sub_type_hdr-&gt;minimum_bandwidth_mbs = bandwidth;</div><div class='del'>-		sub_type_hdr-&gt;maximum_bandwidth_mbs = bandwidth;</div><div class='add'>+		if (ext_cpu) {</div><div class='add'>+			amdgpu_xgmi_get_bandwidth(kdev-&gt;adev, NULL,</div><div class='add'>+						  AMDGPU_XGMI_BW_MODE_PER_LINK,</div><div class='add'>+						  AMDGPU_XGMI_BW_UNIT_MBYTES,</div><div class='add'>+						  &amp;sub_type_hdr-&gt;minimum_bandwidth_mbs,</div><div class='add'>+						  &amp;sub_type_hdr-&gt;maximum_bandwidth_mbs);</div><div class='add'>+		} else {</div><div class='add'>+			sub_type_hdr-&gt;minimum_bandwidth_mbs = mem_bw;</div><div class='add'>+			sub_type_hdr-&gt;maximum_bandwidth_mbs = mem_bw;</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		sub_type_hdr-&gt;io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;</div><div class='ctx'> 		sub_type_hdr-&gt;minimum_bandwidth_mbs =</div><div class='hunk'>@@ -2161,12 +2203,12 @@ static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size,</div><div class='ctx'> </div><div class='ctx'> 	if (use_ta_info) {</div><div class='ctx'> 		sub_type_hdr-&gt;weight_xgmi = KFD_CRAT_XGMI_WEIGHT *</div><div class='del'>-			amdgpu_amdkfd_get_xgmi_hops_count(kdev-&gt;adev, peer_kdev-&gt;adev);</div><div class='del'>-		sub_type_hdr-&gt;maximum_bandwidth_mbs =</div><div class='del'>-			amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev-&gt;adev,</div><div class='del'>-							peer_kdev-&gt;adev, false);</div><div class='del'>-		sub_type_hdr-&gt;minimum_bandwidth_mbs = sub_type_hdr-&gt;maximum_bandwidth_mbs ?</div><div class='del'>-			amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev-&gt;adev, NULL, true) : 0;</div><div class='add'>+			amdgpu_xgmi_get_hops_count(kdev-&gt;adev, peer_kdev-&gt;adev);</div><div class='add'>+		amdgpu_xgmi_get_bandwidth(kdev-&gt;adev, peer_kdev-&gt;adev,</div><div class='add'>+					  AMDGPU_XGMI_BW_MODE_PER_PEER,</div><div class='add'>+					  AMDGPU_XGMI_BW_UNIT_MBYTES,</div><div class='add'>+					  &amp;sub_type_hdr-&gt;minimum_bandwidth_mbs,</div><div class='add'>+					  &amp;sub_type_hdr-&gt;maximum_bandwidth_mbs);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		bool is_single_hop = kdev-&gt;kfd == peer_kdev-&gt;kfd;</div><div class='ctx'> 		int weight = is_single_hop ? KFD_CRAT_INTRA_SOCKET_WEIGHT :</div><div class='hunk'>@@ -2210,9 +2252,6 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image,</div><div class='ctx'> 	 * Modify length and total_entries as subunits are added.</div><div class='ctx'> 	 */</div><div class='ctx'> 	avail_size -= sizeof(struct crat_header);</div><div class='del'>-	if (avail_size &lt; 0)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='ctx'> 	memset(crat_table, 0, sizeof(struct crat_header));</div><div class='ctx'> </div><div class='ctx'> 	memcpy(&amp;crat_table-&gt;signature, CRAT_SIGNATURE,</div><div class='hunk'>@@ -2226,9 +2265,6 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image,</div><div class='ctx'> 	 * First fill in the sub type header and then sub type data</div><div class='ctx'> 	 */</div><div class='ctx'> 	avail_size -= sizeof(struct crat_subtype_computeunit);</div><div class='del'>-	if (avail_size &lt; 0)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='ctx'> 	sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);</div><div class='ctx'> 	memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));</div><div class='ctx'> </div><div class='hunk'>@@ -2325,6 +2361,8 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image,</div><div class='ctx'> 				continue;</div><div class='ctx'> 			if (peer_dev-&gt;gpu-&gt;kfd-&gt;hive_id != kdev-&gt;kfd-&gt;hive_id)</div><div class='ctx'> 				continue;</div><div class='add'>+			if (!amdgpu_xgmi_get_is_sharing_enabled(kdev-&gt;adev, peer_dev-&gt;gpu-&gt;adev))</div><div class='add'>+				continue;</div><div class='ctx'> 			sub_type_hdr = (typeof(sub_type_hdr))(</div><div class='ctx'> 				(char *)sub_type_hdr +</div><div class='ctx'> 				sizeof(struct crat_subtype_iolink));</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h<br/>index 300634b9f668..a8ca7ecb6d27 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_crat.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_crat.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_crat.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_crat.h</a></div><div class='hunk'>@@ -42,8 +42,6 @@</div><div class='ctx'> #define CRAT_OEMTABLEID_LENGTH	8</div><div class='ctx'> #define CRAT_RESERVED_LENGTH	6</div><div class='ctx'> </div><div class='del'>-#define CRAT_OEMID_64BIT_MASK ((1ULL &lt;&lt; (CRAT_OEMID_LENGTH * 8)) - 1)</div><div class='del'>-</div><div class='ctx'> /* Compute Unit flags */</div><div class='ctx'> #define COMPUTE_UNIT_CPU	(1 &lt;&lt; 0)  /* Create Virtual CRAT for CPU */</div><div class='ctx'> #define COMPUTE_UNIT_GPU	(1 &lt;&lt; 1)  /* Create Virtual CRAT for GPU */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c<br/>index d889e3545120..ba99e0f258ae 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_debug.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_debug.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_debug.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_debug.c</a></div><div class='hunk'>@@ -25,6 +25,7 @@</div><div class='ctx'> #include "kfd_topology.h"</div><div class='ctx'> #include &lt;linux/file.h&gt;</div><div class='ctx'> #include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='add'>+#include &lt;uapi/linux/kfd_sysfs.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define MAX_WATCH_ADDRESSES	4</div><div class='ctx'> </div><div class='hunk'>@@ -103,7 +104,8 @@ void debug_event_write_work_handler(struct work_struct *work)</div><div class='ctx'> 			struct kfd_process,</div><div class='ctx'> 			debug_event_workarea);</div><div class='ctx'> </div><div class='del'>-	kernel_write(process-&gt;dbg_ev_file, &amp;write_data, 1, &amp;pos);</div><div class='add'>+	if (process-&gt;debug_trap_enabled &amp;&amp; process-&gt;dbg_ev_file)</div><div class='add'>+		kernel_write(process-&gt;dbg_ev_file, &amp;write_data, 1, &amp;pos);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* update process/device/queue exception status, write to descriptor</div><div class='hunk'>@@ -202,11 +204,12 @@ bool kfd_set_dbg_ev_from_interrupt(struct kfd_node *dev,</div><div class='ctx'> 				   size_t exception_data_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process *p;</div><div class='add'>+	struct kfd_process_device *pdd = NULL;</div><div class='ctx'> 	bool signaled_to_debugger_or_runtime = false;</div><div class='ctx'> </div><div class='del'>-	p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	p = kfd_lookup_process_by_pasid(pasid, &amp;pdd);</div><div class='ctx'> </div><div class='del'>-	if (!p)</div><div class='add'>+	if (!pdd)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (!kfd_dbg_ev_raise(trap_mask, p, dev, doorbell_id, true,</div><div class='hunk'>@@ -236,9 +239,8 @@ bool kfd_set_dbg_ev_from_interrupt(struct kfd_node *dev,</div><div class='ctx'> </div><div class='ctx'> 			mutex_unlock(&amp;p-&gt;mutex);</div><div class='ctx'> 		} else if (trap_mask &amp; KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION)) {</div><div class='del'>-			kfd_dqm_evict_pasid(dev-&gt;dqm, p-&gt;pasid);</div><div class='del'>-			kfd_signal_vm_fault_event(dev, p-&gt;pasid, NULL,</div><div class='del'>-							exception_data);</div><div class='add'>+			kfd_evict_process_device(pdd);</div><div class='add'>+			kfd_signal_vm_fault_event(pdd, NULL, exception_data);</div><div class='ctx'> </div><div class='ctx'> 			signaled_to_debugger_or_runtime = true;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -274,8 +276,8 @@ int kfd_dbg_send_exception_to_runtime(struct kfd_process *p,</div><div class='ctx'> 		data = (struct kfd_hsa_memory_exception_data *)</div><div class='ctx'> 						pdd-&gt;vm_fault_exc_data;</div><div class='ctx'> </div><div class='del'>-		kfd_dqm_evict_pasid(pdd-&gt;dev-&gt;dqm, p-&gt;pasid);</div><div class='del'>-		kfd_signal_vm_fault_event(pdd-&gt;dev, p-&gt;pasid, NULL, data);</div><div class='add'>+		kfd_evict_process_device(pdd);</div><div class='add'>+		kfd_signal_vm_fault_event(pdd, NULL, data);</div><div class='ctx'> 		error_reason &amp;= ~KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -348,10 +350,27 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t spi_dbg_cntl = pdd-&gt;spi_dbg_override | pdd-&gt;spi_dbg_launch_mode;</div><div class='ctx'> 	uint32_t flags = pdd-&gt;process-&gt;dbg_flags;</div><div class='add'>+	struct amdgpu_device *adev = pdd-&gt;dev-&gt;adev;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!kfd_dbg_is_per_vmid_supported(pdd-&gt;dev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (!pdd-&gt;proc_ctx_cpu_ptr) {</div><div class='add'>+		r = amdgpu_amdkfd_alloc_gtt_mem(adev,</div><div class='add'>+			AMDGPU_MES_PROC_CTX_SIZE,</div><div class='add'>+			&amp;pdd-&gt;proc_ctx_bo,</div><div class='add'>+			&amp;pdd-&gt;proc_ctx_gpu_addr,</div><div class='add'>+			&amp;pdd-&gt;proc_ctx_cpu_ptr,</div><div class='add'>+			false);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(adev-&gt;dev,</div><div class='add'>+			"failed to allocate process context bo\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+		memset(pdd-&gt;proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return amdgpu_mes_set_shader_debugger(pdd-&gt;dev-&gt;adev, pdd-&gt;proc_ctx_gpu_addr, spi_dbg_cntl,</div><div class='ctx'> 						pdd-&gt;watch_points, flags, sq_trap_en);</div><div class='ctx'> }</div><div class='hunk'>@@ -363,47 +382,47 @@ static int kfd_dbg_get_dev_watch_id(struct kfd_process_device *pdd, int *watch_i</div><div class='ctx'> </div><div class='ctx'> 	*watch_id = KFD_DEBUGGER_INVALID_WATCH_POINT_ID;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+	spin_lock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_WATCH_ADDRESSES; i++) {</div><div class='ctx'> 		/* device watchpoint in use so skip */</div><div class='del'>-		if ((pdd-&gt;dev-&gt;kfd-&gt;alloc_watch_ids &gt;&gt; i) &amp; 0x1)</div><div class='add'>+		if ((pdd-&gt;dev-&gt;alloc_watch_ids &gt;&gt; i) &amp; 0x1)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		pdd-&gt;alloc_watch_ids |= 0x1 &lt;&lt; i;</div><div class='del'>-		pdd-&gt;dev-&gt;kfd-&gt;alloc_watch_ids |= 0x1 &lt;&lt; i;</div><div class='add'>+		pdd-&gt;dev-&gt;alloc_watch_ids |= 0x1 &lt;&lt; i;</div><div class='ctx'> 		*watch_id = i;</div><div class='del'>-		spin_unlock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+		spin_unlock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	spin_unlock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+	spin_unlock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> </div><div class='ctx'> 	return -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, int watch_id)</div><div class='ctx'> {</div><div class='del'>-	spin_lock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+	spin_lock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> </div><div class='ctx'> 	/* process owns device watch point so safe to clear */</div><div class='ctx'> 	if ((pdd-&gt;alloc_watch_ids &gt;&gt; watch_id) &amp; 0x1) {</div><div class='ctx'> 		pdd-&gt;alloc_watch_ids &amp;= ~(0x1 &lt;&lt; watch_id);</div><div class='del'>-		pdd-&gt;dev-&gt;kfd-&gt;alloc_watch_ids &amp;= ~(0x1 &lt;&lt; watch_id);</div><div class='add'>+		pdd-&gt;dev-&gt;alloc_watch_ids &amp;= ~(0x1 &lt;&lt; watch_id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	spin_unlock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+	spin_unlock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, int watch_id)</div><div class='ctx'> {</div><div class='ctx'> 	bool owns_watch_id = false;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+	spin_lock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> 	owns_watch_id = watch_id &lt; MAX_WATCH_ADDRESSES &amp;&amp;</div><div class='ctx'> 			((pdd-&gt;alloc_watch_ids &gt;&gt; watch_id) &amp; 0x1);</div><div class='ctx'> </div><div class='del'>-	spin_unlock(&amp;pdd-&gt;dev-&gt;kfd-&gt;watch_points_lock);</div><div class='add'>+	spin_unlock(&amp;pdd-&gt;dev-&gt;watch_points_lock);</div><div class='ctx'> </div><div class='ctx'> 	return owns_watch_id;</div><div class='ctx'> }</div><div class='hunk'>@@ -497,14 +516,24 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags)</div><div class='ctx'> 	int i, r = 0, rewind_count = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; target-&gt;n_pdds; i++) {</div><div class='del'>-		if (!kfd_dbg_is_per_vmid_supported(target-&gt;pdds[i]-&gt;dev) &amp;&amp;</div><div class='add'>+		struct kfd_topology_device *topo_dev =</div><div class='add'>+				kfd_topology_device_by_id(target-&gt;pdds[i]-&gt;dev-&gt;id);</div><div class='add'>+		uint32_t caps = topo_dev-&gt;node_props.capability;</div><div class='add'>+</div><div class='add'>+		if (!(caps &amp; HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED) &amp;&amp;</div><div class='ctx'> 			(*flags &amp; KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP)) {</div><div class='ctx'> 			*flags = prev_flags;</div><div class='ctx'> 			return -EACCES;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		if (!(caps &amp; HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED) &amp;&amp;</div><div class='add'>+		    (*flags &amp; KFD_DBG_TRAP_FLAG_SINGLE_ALU_OP)) {</div><div class='add'>+			*flags = prev_flags;</div><div class='add'>+			return -EACCES;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	target-&gt;dbg_flags = *flags &amp; KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP;</div><div class='add'>+	target-&gt;dbg_flags = *flags;</div><div class='ctx'> 	*flags = prev_flags;</div><div class='ctx'> 	for (i = 0; i &lt; target-&gt;n_pdds; i++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = target-&gt;pdds[i];</div><div class='hunk'>@@ -645,6 +674,7 @@ int kfd_dbg_trap_disable(struct kfd_process *target)</div><div class='ctx'> 	else if (target-&gt;runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)</div><div class='ctx'> 		target-&gt;runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;</div><div class='ctx'> </div><div class='add'>+	cancel_work_sync(&amp;target-&gt;debug_event_workarea);</div><div class='ctx'> 	fput(target-&gt;dbg_ev_file);</div><div class='ctx'> 	target-&gt;dbg_ev_file = NULL;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h<br/>index fd0ff64d4184..27aa1a5b120f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_debug.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_debug.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_debug.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_debug.h</a></div><div class='hunk'>@@ -78,6 +78,8 @@ static inline bool kfd_dbg_is_per_vmid_supported(struct kfd_node *dev)</div><div class='ctx'> {</div><div class='ctx'> 	return (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) ||</div><div class='ctx'> 		KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+		KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0) ||</div><div class='ctx'> 		KFD_GC_VERSION(dev) &gt;= IP_VERSION(11, 0, 0));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -134,6 +136,7 @@ static inline bool kfd_dbg_has_ttmps_always_setup(struct kfd_node *dev)</div><div class='ctx'> 			KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 2)) ||</div><div class='ctx'> 	       (KFD_GC_VERSION(dev) &gt;= IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='ctx'> 			KFD_GC_VERSION(dev) &lt; IP_VERSION(12, 0, 0) &amp;&amp;</div><div class='del'>-			(dev-&gt;adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 70);</div><div class='add'>+			(dev-&gt;adev-&gt;mes.sched_version &amp; AMDGPU_MES_VERSION_MASK) &gt;= 70) ||</div><div class='add'>+	       (KFD_GC_VERSION(dev) &gt;= IP_VERSION(12, 0, 0));</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c b/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c<br/>index 4a5a0a4e00f2..9bde2c64540f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c</a></div><div class='hunk'>@@ -27,6 +27,16 @@</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> </div><div class='ctx'> static struct dentry *debugfs_root;</div><div class='add'>+static struct dentry *debugfs_proc;</div><div class='add'>+static struct list_head procs;</div><div class='add'>+</div><div class='add'>+struct debugfs_proc_entry {</div><div class='add'>+	struct list_head list;</div><div class='add'>+	struct dentry *proc_dentry;</div><div class='add'>+	pid_t pid;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_DEBUGFS_FILENAME_LEN 32</div><div class='ctx'> </div><div class='ctx'> static int kfd_debugfs_open(struct inode *inode, struct file *file)</div><div class='ctx'> {</div><div class='hunk'>@@ -92,6 +102,8 @@ static const struct file_operations kfd_debugfs_hang_hws_fops = {</div><div class='ctx'> void kfd_debugfs_init(void)</div><div class='ctx'> {</div><div class='ctx'> 	debugfs_root = debugfs_create_dir("kfd", NULL);</div><div class='add'>+	debugfs_proc = debugfs_create_dir("proc", debugfs_root);</div><div class='add'>+	INIT_LIST_HEAD(&amp;procs);</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_file("mqds", S_IFREG | 0444, debugfs_root,</div><div class='ctx'> 			    kfd_debugfs_mqds_by_process, &amp;kfd_debugfs_fops);</div><div class='hunk'>@@ -107,5 +119,69 @@ void kfd_debugfs_init(void)</div><div class='ctx'> </div><div class='ctx'> void kfd_debugfs_fini(void)</div><div class='ctx'> {</div><div class='add'>+	debugfs_remove_recursive(debugfs_proc);</div><div class='ctx'> 	debugfs_remove_recursive(debugfs_root);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static ssize_t kfd_debugfs_pasid_read(struct file *file, char __user *buf,</div><div class='add'>+				      size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process_device *pdd = file_inode(file)-&gt;i_private;</div><div class='add'>+	char tmp[32];</div><div class='add'>+	int len;</div><div class='add'>+</div><div class='add'>+	len = snprintf(tmp, sizeof(tmp), "%u\n", pdd-&gt;pasid);</div><div class='add'>+</div><div class='add'>+	return simple_read_from_buffer(buf, count, ppos, tmp, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations kfd_debugfs_pasid_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.read = kfd_debugfs_pasid_read,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void kfd_debugfs_add_process(struct kfd_process *p)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	char name[MAX_DEBUGFS_FILENAME_LEN];</div><div class='add'>+	struct debugfs_proc_entry *entry;</div><div class='add'>+</div><div class='add'>+	entry = kzalloc(sizeof(*entry), GFP_KERNEL);</div><div class='add'>+	if (!entry)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	list_add(&amp;entry-&gt;list, &amp;procs);</div><div class='add'>+	entry-&gt;pid = p-&gt;lead_thread-&gt;pid;</div><div class='add'>+	snprintf(name, MAX_DEBUGFS_FILENAME_LEN, "%d",</div><div class='add'>+		 (int)entry-&gt;pid);</div><div class='add'>+	entry-&gt;proc_dentry = debugfs_create_dir(name, debugfs_proc);</div><div class='add'>+</div><div class='add'>+	/* Create debugfs files for each GPU:</div><div class='add'>+	 * - proc/&lt;pid&gt;/pasid_&lt;gpuid&gt;</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='add'>+		struct kfd_process_device *pdd = p-&gt;pdds[i];</div><div class='add'>+</div><div class='add'>+		snprintf(name, MAX_DEBUGFS_FILENAME_LEN, "pasid_%u",</div><div class='add'>+			 pdd-&gt;dev-&gt;id);</div><div class='add'>+		debugfs_create_file((const char *)name, S_IFREG | 0444,</div><div class='add'>+				    entry-&gt;proc_dentry, pdd,</div><div class='add'>+				    &amp;kfd_debugfs_pasid_fops);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void kfd_debugfs_remove_process(struct kfd_process *p)</div><div class='add'>+{</div><div class='add'>+	struct debugfs_proc_entry *entry, *next;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;kfd_processes_mutex);</div><div class='add'>+	list_for_each_entry_safe(entry, next, &amp;procs, list) {</div><div class='add'>+		if (entry-&gt;pid != p-&gt;lead_thread-&gt;pid)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		debugfs_remove_recursive(entry-&gt;proc_dentry);</div><div class='add'>+		list_del(&amp;entry-&gt;list);</div><div class='add'>+		kfree(entry);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;kfd_processes_mutex);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c<br/>index 041ec3de55e7..e9cfb80bd436 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device.c</a></div><div class='hunk'>@@ -56,6 +56,7 @@ extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;</div><div class='ctx'> extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;</div><div class='ctx'> extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;</div><div class='ctx'> extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;</div><div class='add'>+extern const struct kfd2kgd_calls gfx_v12_kfd2kgd;</div><div class='ctx'> </div><div class='ctx'> static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,</div><div class='ctx'> 				unsigned int chunk_size);</div><div class='hunk'>@@ -83,6 +84,8 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)</div><div class='ctx'> 	case IP_VERSION(4, 2, 2):/* ARCTURUS */</div><div class='ctx'> 	case IP_VERSION(4, 4, 0):/* ALDEBARAN */</div><div class='ctx'> 	case IP_VERSION(4, 4, 2):</div><div class='add'>+	case IP_VERSION(4, 4, 5):</div><div class='add'>+	case IP_VERSION(4, 4, 4):</div><div class='ctx'> 	case IP_VERSION(5, 0, 0):/* NAVI10 */</div><div class='ctx'> 	case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */</div><div class='ctx'> 	case IP_VERSION(5, 0, 2):/* NAVI14 */</div><div class='hunk'>@@ -97,6 +100,10 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)</div><div class='ctx'> 	case IP_VERSION(6, 0, 3):</div><div class='ctx'> 	case IP_VERSION(6, 1, 0):</div><div class='ctx'> 	case IP_VERSION(6, 1, 1):</div><div class='add'>+	case IP_VERSION(6, 1, 2):</div><div class='add'>+	case IP_VERSION(6, 1, 3):</div><div class='add'>+	case IP_VERSION(7, 0, 0):</div><div class='add'>+	case IP_VERSION(7, 0, 1):</div><div class='ctx'> 		kfd-&gt;device_info.num_sdma_queues_per_engine = 8;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -115,6 +122,10 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)</div><div class='ctx'> 	case IP_VERSION(6, 0, 3):</div><div class='ctx'> 	case IP_VERSION(6, 1, 0):</div><div class='ctx'> 	case IP_VERSION(6, 1, 1):</div><div class='add'>+	case IP_VERSION(6, 1, 2):</div><div class='add'>+	case IP_VERSION(6, 1, 3):</div><div class='add'>+	case IP_VERSION(7, 0, 0):</div><div class='add'>+	case IP_VERSION(7, 0, 1):</div><div class='ctx'> 		/* Reserve 1 for paging and 1 for gfx */</div><div class='ctx'> 		kfd-&gt;device_info.num_reserved_sdma_queues_per_engine = 2;</div><div class='ctx'> 		/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */</div><div class='hunk'>@@ -143,6 +154,8 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)</div><div class='ctx'> 		kfd-&gt;device_info.event_interrupt_class = &amp;event_interrupt_class_v9;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3): /* GC 9.4.3 */</div><div class='add'>+	case IP_VERSION(9, 4, 4): /* GC 9.4.4 */</div><div class='add'>+	case IP_VERSION(9, 5, 0): /* GC 9.5.0 */</div><div class='ctx'> 		kfd-&gt;device_info.event_interrupt_class =</div><div class='ctx'> 						&amp;event_interrupt_class_v9_4_3;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -168,6 +181,13 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='ctx'> 	case IP_VERSION(11, 5, 0):</div><div class='ctx'> 	case IP_VERSION(11, 5, 1):</div><div class='add'>+	case IP_VERSION(11, 5, 2):</div><div class='add'>+	case IP_VERSION(11, 5, 3):</div><div class='add'>+		kfd-&gt;device_info.event_interrupt_class = &amp;event_interrupt_class_v11;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		/* GFX12_TODO: Change to v12 version. */</div><div class='ctx'> 		kfd-&gt;device_info.event_interrupt_class = &amp;event_interrupt_class_v11;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -220,6 +240,11 @@ static void kfd_device_info_init(struct kfd_dev *kfd,</div><div class='ctx'> 			 */</div><div class='ctx'> 			kfd-&gt;device_info.needs_pci_atomics = true;</div><div class='ctx'> 			kfd-&gt;device_info.no_atomic_fw_version = kfd-&gt;adev-&gt;gfx.rs64_enable ? 509 : 0;</div><div class='add'>+		} else if (gc_version &lt; IP_VERSION(13, 0, 0)) {</div><div class='add'>+			kfd-&gt;device_info.needs_pci_atomics = true;</div><div class='add'>+			kfd-&gt;device_info.no_atomic_fw_version = 2090;</div><div class='add'>+		} else {</div><div class='add'>+			kfd-&gt;device_info.needs_pci_atomics = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		kfd-&gt;device_info.doorbell_size = 4;</div><div class='hunk'>@@ -327,9 +352,12 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)</div><div class='ctx'> 			f2g = &amp;aldebaran_kfd2kgd;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case IP_VERSION(9, 4, 3):</div><div class='del'>-			gfx_target_version = adev-&gt;rev_id &gt;= 1 ? 90402</div><div class='del'>-					   : adev-&gt;flags &amp; AMD_IS_APU ? 90400</div><div class='del'>-					   : 90401;</div><div class='add'>+		case IP_VERSION(9, 4, 4):</div><div class='add'>+			gfx_target_version = 90402;</div><div class='add'>+			f2g = &amp;gc_9_4_3_kfd2kgd;</div><div class='add'>+			break;</div><div class='add'>+		case IP_VERSION(9, 5, 0):</div><div class='add'>+			gfx_target_version = 90500;</div><div class='ctx'> 			f2g = &amp;gc_9_4_3_kfd2kgd;</div><div class='ctx'> 			break;</div><div class='ctx'> 		/* Navi10 */</div><div class='hunk'>@@ -408,15 +436,8 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)</div><div class='ctx'> 			f2g = &amp;gfx_v11_kfd2kgd;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case IP_VERSION(11, 0, 3):</div><div class='del'>-			if ((adev-&gt;pdev-&gt;device == 0x7460 &amp;&amp;</div><div class='del'>-			     adev-&gt;pdev-&gt;revision == 0x00) ||</div><div class='del'>-			    (adev-&gt;pdev-&gt;device == 0x7461 &amp;&amp;</div><div class='del'>-			     adev-&gt;pdev-&gt;revision == 0x00))</div><div class='del'>-				/* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */</div><div class='del'>-				gfx_target_version = 110005;</div><div class='del'>-			else</div><div class='del'>-				/* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */</div><div class='del'>-				gfx_target_version = 110001;</div><div class='add'>+			/* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */</div><div class='add'>+			gfx_target_version = 110001;</div><div class='ctx'> 			f2g = &amp;gfx_v11_kfd2kgd;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case IP_VERSION(11, 5, 0):</div><div class='hunk'>@@ -427,6 +448,22 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)</div><div class='ctx'> 			gfx_target_version = 110501;</div><div class='ctx'> 			f2g = &amp;gfx_v11_kfd2kgd;</div><div class='ctx'> 			break;</div><div class='add'>+		case IP_VERSION(11, 5, 2):</div><div class='add'>+			gfx_target_version = 110502;</div><div class='add'>+			f2g = &amp;gfx_v11_kfd2kgd;</div><div class='add'>+			break;</div><div class='add'>+		case IP_VERSION(11, 5, 3):</div><div class='add'>+			gfx_target_version = 110503;</div><div class='add'>+			f2g = &amp;gfx_v11_kfd2kgd;</div><div class='add'>+			break;</div><div class='add'>+		case IP_VERSION(12, 0, 0):</div><div class='add'>+			gfx_target_version = 120000;</div><div class='add'>+			f2g = &amp;gfx_v12_kfd2kgd;</div><div class='add'>+			break;</div><div class='add'>+		case IP_VERSION(12, 0, 1):</div><div class='add'>+			gfx_target_version = 120001;</div><div class='add'>+			f2g = &amp;gfx_v12_kfd2kgd;</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -435,12 +472,12 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)</div><div class='ctx'> </div><div class='ctx'> 	if (!f2g) {</div><div class='ctx'> 		if (amdgpu_ip_version(adev, GC_HWIP, 0))</div><div class='del'>-			dev_err(kfd_device,</div><div class='add'>+			dev_info(kfd_device,</div><div class='ctx'> 				"GC IP %06x %s not supported in kfd\n",</div><div class='ctx'> 				amdgpu_ip_version(adev, GC_HWIP, 0),</div><div class='ctx'> 				vf ? "VF" : "");</div><div class='ctx'> 		else</div><div class='del'>-			dev_err(kfd_device, "%s %s not supported in kfd\n",</div><div class='add'>+			dev_info(kfd_device, "%s %s not supported in kfd\n",</div><div class='ctx'> 				amdgpu_asic_name[adev-&gt;asic_type], vf ? "VF" : "");</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -458,6 +495,7 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)</div><div class='ctx'> 	mutex_init(&amp;kfd-&gt;doorbell_mutex);</div><div class='ctx'> </div><div class='ctx'> 	ida_init(&amp;kfd-&gt;doorbell_ida);</div><div class='add'>+	atomic_set(&amp;kfd-&gt;kfd_processes_count, 0);</div><div class='ctx'> </div><div class='ctx'> 	return kfd;</div><div class='ctx'> }</div><div class='hunk'>@@ -480,11 +518,16 @@ static void kfd_cwsr_init(struct kfd_dev *kfd)</div><div class='ctx'> 					     &gt; KFD_CWSR_TMA_OFFSET);</div><div class='ctx'> 			kfd-&gt;cwsr_isa = cwsr_trap_aldebaran_hex;</div><div class='ctx'> 			kfd-&gt;cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);</div><div class='del'>-		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) {</div><div class='add'>+		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+			   KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) {</div><div class='ctx'> 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex)</div><div class='ctx'> 					     &gt; KFD_CWSR_TMA_OFFSET);</div><div class='ctx'> 			kfd-&gt;cwsr_isa = cwsr_trap_gfx9_4_3_hex;</div><div class='ctx'> 			kfd-&gt;cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);</div><div class='add'>+		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) {</div><div class='add'>+			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) &gt; PAGE_SIZE);</div><div class='add'>+			kfd-&gt;cwsr_isa = cwsr_trap_gfx9_5_0_hex;</div><div class='add'>+			kfd-&gt;cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex);</div><div class='ctx'> 		} else if (KFD_GC_VERSION(kfd) &lt; IP_VERSION(10, 1, 1)) {</div><div class='ctx'> 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex)</div><div class='ctx'> 					     &gt; KFD_CWSR_TMA_OFFSET);</div><div class='hunk'>@@ -500,12 +543,17 @@ static void kfd_cwsr_init(struct kfd_dev *kfd)</div><div class='ctx'> 					     &gt; KFD_CWSR_TMA_OFFSET);</div><div class='ctx'> 			kfd-&gt;cwsr_isa = cwsr_trap_gfx10_hex;</div><div class='ctx'> 			kfd-&gt;cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);</div><div class='del'>-		} else {</div><div class='add'>+		} else if (KFD_GC_VERSION(kfd) &lt; IP_VERSION(12, 0, 0)) {</div><div class='ctx'> 			/* The gfx11 cwsr trap handler must fit inside a single</div><div class='ctx'> 			   page. */</div><div class='ctx'> 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) &gt; PAGE_SIZE);</div><div class='ctx'> 			kfd-&gt;cwsr_isa = cwsr_trap_gfx11_hex;</div><div class='ctx'> 			kfd-&gt;cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);</div><div class='add'>+		} else {</div><div class='add'>+			BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex)</div><div class='add'>+					     &gt; KFD_CWSR_TMA_OFFSET);</div><div class='add'>+			kfd-&gt;cwsr_isa = cwsr_trap_gfx12_hex;</div><div class='add'>+			kfd-&gt;cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		kfd-&gt;cwsr_enabled = true;</div><div class='hunk'>@@ -530,15 +578,21 @@ static int kfd_gws_init(struct kfd_node *node)</div><div class='ctx'> 			&amp;&amp; kfd-&gt;mec2_fw_version &gt;= 0x30)   ||</div><div class='ctx'> 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)</div><div class='ctx'> 			&amp;&amp; kfd-&gt;mec2_fw_version &gt;= 0x28) ||</div><div class='del'>-		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) ||</div><div class='add'>+		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) ||</div><div class='add'>+		(KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) ||</div><div class='ctx'> 		(KFD_GC_VERSION(node) &gt;= IP_VERSION(10, 3, 0)</div><div class='ctx'> 			&amp;&amp; KFD_GC_VERSION(node) &lt; IP_VERSION(11, 0, 0)</div><div class='ctx'> 			&amp;&amp; kfd-&gt;mec2_fw_version &gt;= 0x6b) ||</div><div class='ctx'> 		(KFD_GC_VERSION(node) &gt;= IP_VERSION(11, 0, 0)</div><div class='ctx'> 			&amp;&amp; KFD_GC_VERSION(node) &lt; IP_VERSION(12, 0, 0)</div><div class='del'>-			&amp;&amp; mes_rev &gt;= 68))))</div><div class='add'>+			&amp;&amp; mes_rev &gt;= 68) ||</div><div class='add'>+		(KFD_GC_VERSION(node) &gt;= IP_VERSION(12, 0, 0))))) {</div><div class='add'>+		if (KFD_GC_VERSION(node) &gt;= IP_VERSION(12, 0, 0))</div><div class='add'>+			node-&gt;adev-&gt;gds.gws_size = 64;</div><div class='ctx'> 		ret = amdgpu_amdkfd_alloc_gws(node-&gt;adev,</div><div class='ctx'> 				node-&gt;adev-&gt;gds.gws_size, &amp;node-&gt;gws);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -602,6 +656,14 @@ static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)</div><div class='ctx'> 	struct kfd_node *knode;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * flush_work ensures that there are no outstanding</div><div class='add'>+	 * work-queue items that will access interrupt_ring. New work items</div><div class='add'>+	 * can't be created because we stopped interrupt handling above.</div><div class='add'>+	 */</div><div class='add'>+	flush_workqueue(kfd-&gt;ih_wq);</div><div class='add'>+	destroy_workqueue(kfd-&gt;ih_wq);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; num_nodes; i++) {</div><div class='ctx'> 		knode = kfd-&gt;nodes[i];</div><div class='ctx'> 		device_queue_manager_uninit(knode-&gt;dqm);</div><div class='hunk'>@@ -697,14 +759,14 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,</div><div class='ctx'> 	last_vmid_kfd = fls(gpu_resources-&gt;compute_vmid_bitmap)-1;</div><div class='ctx'> 	vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;</div><div class='ctx'> </div><div class='del'>-	/* For GFX9.4.3, we need special handling for VMIDs depending on</div><div class='del'>-	 * partition mode.</div><div class='add'>+	/* For multi-partition capable GPUs, we need special handling for VMIDs</div><div class='add'>+	 * depending on partition mode.</div><div class='ctx'> 	 * In CPX mode, the VMID range needs to be shared between XCDs.</div><div class='ctx'> 	 * Additionally, there are 13 VMIDs (3-15) available for KFD. To</div><div class='ctx'> 	 * divide them equally, we change starting VMID to 4 and not use</div><div class='ctx'> 	 * VMID 3.</div><div class='del'>-	 * If the VMID range changes for GFX9.4.3, then this code MUST be</div><div class='del'>-	 * revisited.</div><div class='add'>+	 * If the VMID range changes for multi-partition capable GPUs, then</div><div class='add'>+	 * this code MUST be revisited.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (kfd-&gt;adev-&gt;xcp_mgr) {</div><div class='ctx'> 		partition_mode = amdgpu_xcp_query_partition_mode(kfd-&gt;adev-&gt;xcp_mgr,</div><div class='hunk'>@@ -769,11 +831,12 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,</div><div class='ctx'> 		kfd-&gt;hive_id = kfd-&gt;adev-&gt;gmc.xgmi.hive_id;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * For GFX9.4.3, the KFD abstracts all partitions within a socket as</div><div class='del'>-	 * xGMI connected in the topology so assign a unique hive id per</div><div class='del'>-	 * device based on the pci device location if device is in PCIe mode.</div><div class='add'>+	 * For multi-partition capable GPUs, the KFD abstracts all partitions</div><div class='add'>+	 * within a socket as xGMI connected in the topology so assign a unique</div><div class='add'>+	 * hive id per device based on the pci device location if device is in</div><div class='add'>+	 * PCIe mode.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!kfd-&gt;hive_id &amp;&amp; (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) &amp;&amp; kfd-&gt;num_nodes &gt; 1)</div><div class='add'>+	if (!kfd-&gt;hive_id &amp;&amp; kfd-&gt;num_nodes &gt; 1)</div><div class='ctx'> 		kfd-&gt;hive_id = pci_dev_id(kfd-&gt;adev-&gt;pdev);</div><div class='ctx'> </div><div class='ctx'> 	kfd-&gt;noretry = kfd-&gt;adev-&gt;gmc.noretry;</div><div class='hunk'>@@ -811,11 +874,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,</div><div class='ctx'> 				KFD_XCP_MEMORY_SIZE(node-&gt;adev, node-&gt;node_id) &gt;&gt; 20);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='del'>-		    partition_mode == AMDGPU_CPX_PARTITION_MODE &amp;&amp;</div><div class='add'>+		if (partition_mode == AMDGPU_CPX_PARTITION_MODE &amp;&amp;</div><div class='ctx'> 		    kfd-&gt;num_nodes != 1) {</div><div class='del'>-			/* For GFX9.4.3 and CPX mode, first XCD gets VMID range</div><div class='del'>-			 * 4-9 and second XCD gets VMID range 10-15.</div><div class='add'>+			/* For multi-partition capable GPUs and CPX mode, first</div><div class='add'>+			 * XCD gets VMID range 4-9 and second XCD gets VMID</div><div class='add'>+			 * range 10-15.</div><div class='ctx'> 			 */</div><div class='ctx'> </div><div class='ctx'> 			node-&gt;vm_info.first_vmid_kfd = (i%2 == 0) ?</div><div class='hunk'>@@ -839,7 +902,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,</div><div class='ctx'> 		amdgpu_amdkfd_get_local_mem_info(kfd-&gt;adev,</div><div class='ctx'> 					&amp;node-&gt;local_mem_info, node-&gt;xcp);</div><div class='ctx'> </div><div class='del'>-		if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3))</div><div class='add'>+		if (kfd-&gt;adev-&gt;xcp_mgr)</div><div class='ctx'> 			kfd_setup_interrupt_bitmap(node, i);</div><div class='ctx'> </div><div class='ctx'> 		/* Initialize the KFD node */</div><div class='hunk'>@@ -847,13 +910,14 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,</div><div class='ctx'> 			dev_err(kfd_device, "Error initializing KFD node\n");</div><div class='ctx'> 			goto node_init_error;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		spin_lock_init(&amp;node-&gt;watch_points_lock);</div><div class='add'>+</div><div class='ctx'> 		kfd-&gt;nodes[i] = node;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	svm_range_set_max_pages(kfd-&gt;adev);</div><div class='ctx'> </div><div class='del'>-	spin_lock_init(&amp;kfd-&gt;watch_points_lock);</div><div class='del'>-</div><div class='ctx'> 	kfd-&gt;init_complete = true;</div><div class='ctx'> 	dev_info(kfd_device, "added device %x:%x\n", kfd-&gt;adev-&gt;pdev-&gt;vendor,</div><div class='ctx'> 		 kfd-&gt;adev-&gt;pdev-&gt;device);</div><div class='hunk'>@@ -870,7 +934,7 @@ node_alloc_error:</div><div class='ctx'> kfd_doorbell_error:</div><div class='ctx'> 	kfd_gtt_sa_fini(kfd);</div><div class='ctx'> kfd_gtt_sa_init_error:</div><div class='del'>-	amdgpu_amdkfd_free_gtt_mem(kfd-&gt;adev, kfd-&gt;gtt_mem);</div><div class='add'>+	amdgpu_amdkfd_free_gtt_mem(kfd-&gt;adev, &amp;kfd-&gt;gtt_mem);</div><div class='ctx'> alloc_gtt_mem_failure:</div><div class='ctx'> 	dev_err(kfd_device,</div><div class='ctx'> 		"device %x:%x NOT added due to errors\n",</div><div class='hunk'>@@ -888,13 +952,14 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)</div><div class='ctx'> 		kfd_doorbell_fini(kfd);</div><div class='ctx'> 		ida_destroy(&amp;kfd-&gt;doorbell_ida);</div><div class='ctx'> 		kfd_gtt_sa_fini(kfd);</div><div class='del'>-		amdgpu_amdkfd_free_gtt_mem(kfd-&gt;adev, kfd-&gt;gtt_mem);</div><div class='add'>+		amdgpu_amdkfd_free_gtt_mem(kfd-&gt;adev, &amp;kfd-&gt;gtt_mem);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(kfd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int kgd2kfd_pre_reset(struct kfd_dev *kfd)</div><div class='add'>+int kgd2kfd_pre_reset(struct kfd_dev *kfd,</div><div class='add'>+		      struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_node *node;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -904,11 +969,10 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; kfd-&gt;num_nodes; i++) {</div><div class='ctx'> 		node = kfd-&gt;nodes[i];</div><div class='del'>-		kfd_smi_event_update_gpu_reset(node, false);</div><div class='del'>-		node-&gt;dqm-&gt;ops.pre_reset(node-&gt;dqm);</div><div class='add'>+		kfd_smi_event_update_gpu_reset(node, false, reset_context);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	kgd2kfd_suspend(kfd, false);</div><div class='add'>+	kgd2kfd_suspend(kfd, true);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; kfd-&gt;num_nodes; i++)</div><div class='ctx'> 		kfd_signal_reset_event(kfd-&gt;nodes[i]);</div><div class='hunk'>@@ -944,37 +1008,48 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)</div><div class='ctx'> 	for (i = 0; i &lt; kfd-&gt;num_nodes; i++) {</div><div class='ctx'> 		node = kfd-&gt;nodes[i];</div><div class='ctx'> 		atomic_set(&amp;node-&gt;sram_ecc_flag, 0);</div><div class='del'>-		kfd_smi_event_update_gpu_reset(node, true);</div><div class='add'>+		kfd_smi_event_update_gpu_reset(node, true, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool kfd_is_locked(void)</div><div class='add'>+bool kfd_is_locked(struct kfd_dev *kfd)</div><div class='ctx'> {</div><div class='add'>+	uint8_t id  = 0;</div><div class='add'>+	struct kfd_node *dev;</div><div class='add'>+</div><div class='ctx'> 	lockdep_assert_held(&amp;kfd_processes_mutex);</div><div class='del'>-	return  (kfd_locked &gt; 0);</div><div class='add'>+</div><div class='add'>+	/* check reset/suspend lock */</div><div class='add'>+	if (kfd_locked &gt; 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (kfd)</div><div class='add'>+		return kfd-&gt;kfd_dev_lock &gt; 0;</div><div class='add'>+</div><div class='add'>+	/* check lock on all cgroup accessible devices */</div><div class='add'>+	while (kfd_topology_enum_kfd_devices(id++, &amp;dev) == 0) {</div><div class='add'>+		if (!dev || kfd_devcgroup_check_permission(dev))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (dev-&gt;kfd-&gt;kfd_dev_lock &gt; 0)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)</div><div class='add'>+void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_node *node;</div><div class='ctx'> 	int i;</div><div class='del'>-	int count;</div><div class='ctx'> </div><div class='ctx'> 	if (!kfd-&gt;init_complete)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	/* for runtime suspend, skip locking kfd */</div><div class='del'>-	if (!run_pm) {</div><div class='del'>-		mutex_lock(&amp;kfd_processes_mutex);</div><div class='del'>-		count = ++kfd_locked;</div><div class='del'>-		mutex_unlock(&amp;kfd_processes_mutex);</div><div class='del'>-</div><div class='del'>-		/* For first KFD device suspend all the KFD processes */</div><div class='del'>-		if (count == 1)</div><div class='del'>-			kfd_suspend_all_processes();</div><div class='del'>-	}</div><div class='add'>+	if (suspend_proc)</div><div class='add'>+		kgd2kfd_suspend_process(kfd);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; kfd-&gt;num_nodes; i++) {</div><div class='ctx'> 		node = kfd-&gt;nodes[i];</div><div class='hunk'>@@ -982,9 +1057,9 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)</div><div class='add'>+int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc)</div><div class='ctx'> {</div><div class='del'>-	int ret, count, i;</div><div class='add'>+	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	if (!kfd-&gt;init_complete)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -995,16 +1070,36 @@ int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* for runtime resume, skip unlocking kfd */</div><div class='del'>-	if (!run_pm) {</div><div class='del'>-		mutex_lock(&amp;kfd_processes_mutex);</div><div class='del'>-		count = --kfd_locked;</div><div class='del'>-		mutex_unlock(&amp;kfd_processes_mutex);</div><div class='add'>+	if (resume_proc)</div><div class='add'>+		ret = kgd2kfd_resume_process(kfd);</div><div class='ctx'> </div><div class='del'>-		WARN_ONCE(count &lt; 0, "KFD suspend / resume ref. error");</div><div class='del'>-		if (count == 0)</div><div class='del'>-			ret = kfd_resume_all_processes();</div><div class='del'>-	}</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void kgd2kfd_suspend_process(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;kfd_processes_mutex);</div><div class='add'>+	/* For first KFD device suspend all the KFD processes */</div><div class='add'>+	if (++kfd_locked == 1)</div><div class='add'>+		kfd_suspend_all_processes();</div><div class='add'>+	mutex_unlock(&amp;kfd_processes_mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kgd2kfd_resume_process(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;kfd_processes_mutex);</div><div class='add'>+	if (--kfd_locked == 0)</div><div class='add'>+		ret = kfd_resume_all_processes();</div><div class='add'>+	WARN_ONCE(kfd_locked &lt; 0, "KFD suspend / resume ref. error");</div><div class='add'>+	mutex_unlock(&amp;kfd_processes_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1022,21 +1117,6 @@ static int kfd_resume(struct kfd_node *node)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void kfd_queue_work(struct workqueue_struct *wq,</div><div class='del'>-				  struct work_struct *work)</div><div class='del'>-{</div><div class='del'>-	int cpu, new_cpu;</div><div class='del'>-</div><div class='del'>-	cpu = new_cpu = smp_processor_id();</div><div class='del'>-	do {</div><div class='del'>-		new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;</div><div class='del'>-		if (cpu_to_node(new_cpu) == numa_node_id())</div><div class='del'>-			break;</div><div class='del'>-	} while (cpu != new_cpu);</div><div class='del'>-</div><div class='del'>-	queue_work_on(new_cpu, wq, work);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* This is called directly from KGD at ISR. */</div><div class='ctx'> void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)</div><div class='ctx'> {</div><div class='hunk'>@@ -1054,7 +1134,15 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; kfd-&gt;num_nodes; i++) {</div><div class='del'>-		node = kfd-&gt;nodes[i];</div><div class='add'>+		/* Race if another thread in b/w</div><div class='add'>+		 * kfd_cleanup_nodes and kfree(kfd),</div><div class='add'>+		 * when kfd-&gt;nodes[i] = NULL</div><div class='add'>+		 */</div><div class='add'>+		if (kfd-&gt;nodes[i])</div><div class='add'>+			node = kfd-&gt;nodes[i];</div><div class='add'>+		else</div><div class='add'>+			return;</div><div class='add'>+</div><div class='ctx'> 		spin_lock_irqsave(&amp;node-&gt;interrupt_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 		if (node-&gt;interrupts_active</div><div class='hunk'>@@ -1062,7 +1150,7 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)</div><div class='ctx'> 			    	patched_ihre, &amp;is_patched)</div><div class='ctx'> 		    &amp;&amp; enqueue_ih_ring_entry(node,</div><div class='ctx'> 			    	is_patched ? patched_ihre : ih_ring_entry)) {</div><div class='del'>-			kfd_queue_work(node-&gt;ih_wq, &amp;node-&gt;interrupt_work);</div><div class='add'>+			queue_work(node-&gt;kfd-&gt;ih_wq, &amp;node-&gt;interrupt_work);</div><div class='ctx'> 			spin_unlock_irqrestore(&amp;node-&gt;interrupt_lock, flags);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1359,6 +1447,13 @@ void kfd_dec_compute_active(struct kfd_node *node)</div><div class='ctx'> 	WARN_ONCE(count &lt; 0, "Compute profile ref. count error");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool kfd_compute_active(struct kfd_node *node)</div><div class='add'>+{</div><div class='add'>+	if (atomic_read(&amp;node-&gt;kfd-&gt;compute_profile))</div><div class='add'>+		return true;</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1392,27 +1487,225 @@ unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)</div><div class='ctx'> 		kfd_get_num_sdma_engines(node);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int kgd2kfd_check_and_lock_kfd(void)</div><div class='add'>+int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_process *p;</div><div class='add'>+	int r = 0, temp, idx;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;kfd_processes_mutex);</div><div class='del'>-	if (!hash_empty(kfd_processes_table) || kfd_is_locked()) {</div><div class='del'>-		mutex_unlock(&amp;kfd_processes_mutex);</div><div class='del'>-		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	/* kfd_processes_count is per kfd_dev, return -EBUSY without</div><div class='add'>+	 * further check</div><div class='add'>+	 */</div><div class='add'>+	if (!!atomic_read(&amp;kfd-&gt;kfd_processes_count)) {</div><div class='add'>+		pr_debug("process_wq_release not finished\n");</div><div class='add'>+		r = -EBUSY;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	++kfd_locked;</div><div class='add'>+	if (hash_empty(kfd_processes_table) &amp;&amp; !kfd_is_locked(kfd))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* fail under system reset/resume or kfd device is partition switching. */</div><div class='add'>+	if (kfd_is_locked(kfd)) {</div><div class='add'>+		r = -EBUSY;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * ensure all running processes are cgroup excluded from device before mode switch.</div><div class='add'>+	 * i.e. no pdd was created on the process socket.</div><div class='add'>+	 */</div><div class='add'>+	idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='add'>+	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='add'>+			if (p-&gt;pdds[i]-&gt;dev-&gt;kfd != kfd)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			r = -EBUSY;</div><div class='add'>+			goto proc_check_unlock;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+proc_check_unlock:</div><div class='add'>+	srcu_read_unlock(&amp;kfd_processes_srcu, idx);</div><div class='add'>+out:</div><div class='add'>+	if (!r)</div><div class='add'>+		++kfd-&gt;kfd_dev_lock;</div><div class='ctx'> 	mutex_unlock(&amp;kfd_processes_mutex);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kgd2kfd_unlock_kfd(void)</div><div class='add'>+void kgd2kfd_unlock_kfd(struct kfd_dev *kfd)</div><div class='ctx'> {</div><div class='ctx'> 	mutex_lock(&amp;kfd_processes_mutex);</div><div class='del'>-	--kfd_locked;</div><div class='add'>+	--kfd-&gt;kfd_dev_lock;</div><div class='ctx'> 	mutex_unlock(&amp;kfd_processes_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *node;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (node_id &gt;= kfd-&gt;num_nodes) {</div><div class='add'>+		dev_warn(kfd-&gt;adev-&gt;dev, "Invalid node ID: %u exceeds %u\n",</div><div class='add'>+			 node_id, kfd-&gt;num_nodes - 1);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	node = kfd-&gt;nodes[node_id];</div><div class='add'>+</div><div class='add'>+	ret = node-&gt;dqm-&gt;ops.unhalt(node-&gt;dqm);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(kfd_device, "Error in starting scheduler\n");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *node;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; kfd-&gt;num_nodes; i++) {</div><div class='add'>+		node = kfd-&gt;nodes[i];</div><div class='add'>+		r = node-&gt;dqm-&gt;ops.unhalt(node-&gt;dqm);</div><div class='add'>+		if (r) {</div><div class='add'>+			dev_err(kfd_device, "Error in starting scheduler\n");</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *node;</div><div class='add'>+</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (node_id &gt;= kfd-&gt;num_nodes) {</div><div class='add'>+		dev_warn(kfd-&gt;adev-&gt;dev, "Invalid node ID: %u exceeds %u\n",</div><div class='add'>+			 node_id, kfd-&gt;num_nodes - 1);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	node = kfd-&gt;nodes[node_id];</div><div class='add'>+	return node-&gt;dqm-&gt;ops.halt(node-&gt;dqm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *node;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; kfd-&gt;num_nodes; i++) {</div><div class='add'>+		node = kfd-&gt;nodes[i];</div><div class='add'>+		r = node-&gt;dqm-&gt;ops.halt(node-&gt;dqm);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *node;</div><div class='add'>+</div><div class='add'>+	if (!kfd-&gt;init_complete)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (node_id &gt;= kfd-&gt;num_nodes) {</div><div class='add'>+		dev_warn(kfd-&gt;adev-&gt;dev, "Invalid node ID: %u exceeds %u\n",</div><div class='add'>+			 node_id, kfd-&gt;num_nodes - 1);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	node = kfd-&gt;nodes[node_id];</div><div class='add'>+</div><div class='add'>+	return kfd_compute_active(node);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9</div><div class='add'>+ * @adev: amdgpu device</div><div class='add'>+ * @entry: vm fault interrupt vector</div><div class='add'>+ * @retry_fault: if this is retry fault</div><div class='add'>+ *</div><div class='add'>+ * retry fault -</div><div class='add'>+ *    with CAM enabled, adev primary ring</div><div class='add'>+ *                           |  gmc_v9_0_process_interrupt()</div><div class='add'>+ *                      adev soft_ring</div><div class='add'>+ *                           |  gmc_v9_0_process_interrupt() worker failed to recover page fault</div><div class='add'>+ *                      KFD node ih_fifo</div><div class='add'>+ *                           |  KFD interrupt_wq worker</div><div class='add'>+ *                      kfd_signal_vm_fault_event</div><div class='add'>+ *</div><div class='add'>+ *    without CAM,      adev primary ring1</div><div class='add'>+ *                           |  gmc_v9_0_process_interrupt worker failed to recvoer page fault</div><div class='add'>+ *                      KFD node ih_fifo</div><div class='add'>+ *                           |  KFD interrupt_wq worker</div><div class='add'>+ *                      kfd_signal_vm_fault_event</div><div class='add'>+ *</div><div class='add'>+ * no-retry fault -</div><div class='add'>+ *                      adev primary ring</div><div class='add'>+ *                           |  gmc_v9_0_process_interrupt()</div><div class='add'>+ *                      KFD node ih_fifo</div><div class='add'>+ *                           |  KFD interrupt_wq worker</div><div class='add'>+ *                      kfd_signal_vm_fault_event</div><div class='add'>+ *</div><div class='add'>+ * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault</div><div class='add'>+ *            of same process, don't copy interrupt to KFD node ih_fifo.</div><div class='add'>+ *            With gdb debugger enabled, need convert the retry fault to no-retry fault for</div><div class='add'>+ *            debugger, cannot use the fast path.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   true - use the fast path to handle this fault</div><div class='add'>+ *   false - use normal path to handle it</div><div class='add'>+ */</div><div class='add'>+bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,</div><div class='add'>+			       bool retry_fault)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process *p;</div><div class='add'>+	u32 cam_index;</div><div class='add'>+</div><div class='add'>+	if (entry-&gt;ih == &amp;adev-&gt;irq.ih_soft || entry-&gt;ih == &amp;adev-&gt;irq.ih1) {</div><div class='add'>+		p = kfd_lookup_process_by_pasid(entry-&gt;pasid, NULL);</div><div class='add'>+		if (!p)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;gpu_page_fault &amp;&amp; !p-&gt;debug_trap_enabled) {</div><div class='add'>+			if (retry_fault &amp;&amp; adev-&gt;irq.retry_cam_enabled) {</div><div class='add'>+				cam_index = entry-&gt;src_data[2] &amp; 0x3ff;</div><div class='add'>+				WDOORBELL32(adev-&gt;irq.retry_cam_doorbell_index, cam_index);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			kfd_unref_process(p);</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * This is the first page fault, set flag and then signal user space</div><div class='add'>+		 */</div><div class='add'>+		p-&gt;gpu_page_fault = true;</div><div class='add'>+		kfd_unref_process(p);</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> </div><div class='ctx'> /* This function will send a package to HIQ to hang the HWS</div><div class='hunk'>@@ -1425,6 +1718,11 @@ int kfd_debugfs_hang_hws(struct kfd_node *dev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Inducing MES hang is not supported\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return dqm_debugfs_hang_hws(dev-&gt;dqm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c<br/>index f4d395e38683..d7a2e7178ea9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c</a></div><div class='hunk'>@@ -35,12 +35,16 @@</div><div class='ctx'> #include "cik_regs.h"</div><div class='ctx'> #include "kfd_kernel_queue.h"</div><div class='ctx'> #include "amdgpu_amdkfd.h"</div><div class='del'>-#include "mes_api_def.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='add'>+#include "amdgpu_sdma.h"</div><div class='add'>+#include "mes_v11_api_def.h"</div><div class='ctx'> #include "kfd_debug.h"</div><div class='ctx'> </div><div class='ctx'> /* Size of the per-pipe EOP queue */</div><div class='ctx'> #define CIK_HPD_EOP_BYTES_LOG2 11</div><div class='ctx'> #define CIK_HPD_EOP_BYTES (1U &lt;&lt; CIK_HPD_EOP_BYTES_LOG2)</div><div class='add'>+/* See unmap_queues_cpsch() */</div><div class='add'>+#define USE_DEFAULT_GRACE_PERIOD 0xffffffff</div><div class='ctx'> </div><div class='ctx'> static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,</div><div class='ctx'> 				  u32 pasid, unsigned int vmid);</div><div class='hunk'>@@ -65,7 +69,8 @@ static inline void deallocate_hqd(struct device_queue_manager *dqm,</div><div class='ctx'> static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);</div><div class='ctx'> static int allocate_sdma_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 				struct queue *q, const uint32_t *restore_sdma_id);</div><div class='del'>-static void kfd_process_hw_exception(struct work_struct *work);</div><div class='add'>+</div><div class='add'>+static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma);</div><div class='ctx'> </div><div class='ctx'> static inline</div><div class='ctx'> enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)</div><div class='hunk'>@@ -152,17 +157,24 @@ void program_sh_mem_settings(struct device_queue_manager *dqm,</div><div class='ctx'> </div><div class='ctx'> static void kfd_hws_hang(struct device_queue_manager *dqm)</div><div class='ctx'> {</div><div class='add'>+	struct device_process_node *cur;</div><div class='add'>+	struct qcm_process_device *qpd;</div><div class='add'>+	struct queue *q;</div><div class='add'>+</div><div class='add'>+	/* Mark all device queues as reset. */</div><div class='add'>+	list_for_each_entry(cur, &amp;dqm-&gt;queues, list) {</div><div class='add'>+		qpd = cur-&gt;qpd;</div><div class='add'>+		list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+			struct kfd_process_device *pdd = qpd_to_pdd(qpd);</div><div class='add'>+</div><div class='add'>+			pdd-&gt;has_reset_queue = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Issue a GPU reset if HWS is unresponsive</div><div class='ctx'> 	 */</div><div class='del'>-	dqm-&gt;is_hws_hang = true;</div><div class='del'>-</div><div class='del'>-	/* It's possible we're detecting a HWS hang in the</div><div class='del'>-	 * middle of a GPU reset. No need to schedule another</div><div class='del'>-	 * reset in this case.</div><div class='del'>-	 */</div><div class='del'>-	if (!dqm-&gt;is_resetting)</div><div class='del'>-		schedule_work(&amp;dqm-&gt;hw_exception_work);</div><div class='add'>+	amdgpu_amdkfd_gpu_reset(dqm-&gt;dev-&gt;adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int convert_to_mes_queue_type(int queue_type)</div><div class='hunk'>@@ -194,11 +206,13 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	int r, queue_type;</div><div class='ctx'> 	uint64_t wptr_addr_off;</div><div class='ctx'> </div><div class='del'>-	if (dqm-&gt;is_hws_hang)</div><div class='add'>+	if (!dqm-&gt;sched_running || dqm-&gt;sched_halt)</div><div class='add'>+		return 0;</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;queue_input, 0x0, sizeof(struct mes_add_queue_input));</div><div class='del'>-	queue_input.process_id = qpd-&gt;pqm-&gt;process-&gt;pasid;</div><div class='add'>+	queue_input.process_id = pdd-&gt;pasid;</div><div class='ctx'> 	queue_input.page_table_base_addr =  qpd-&gt;page_table_base;</div><div class='ctx'> 	queue_input.process_va_start = 0;</div><div class='ctx'> 	queue_input.process_va_end = adev-&gt;vm_manager.max_pfn - 1;</div><div class='hunk'>@@ -214,10 +228,8 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	queue_input.mqd_addr = q-&gt;gart_mqd_addr;</div><div class='ctx'> 	queue_input.wptr_addr = (uint64_t)q-&gt;properties.write_ptr;</div><div class='ctx'> </div><div class='del'>-	if (q-&gt;wptr_bo) {</div><div class='del'>-		wptr_addr_off = (uint64_t)q-&gt;properties.write_ptr &amp; (PAGE_SIZE - 1);</div><div class='del'>-		queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q-&gt;wptr_bo) + wptr_addr_off;</div><div class='del'>-	}</div><div class='add'>+	wptr_addr_off = (uint64_t)q-&gt;properties.write_ptr &amp; (PAGE_SIZE - 1);</div><div class='add'>+	queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q-&gt;properties.wptr_bo) + wptr_addr_off;</div><div class='ctx'> </div><div class='ctx'> 	queue_input.is_kfd_process = 1;</div><div class='ctx'> 	queue_input.is_aql_queue = (q-&gt;properties.format == KFD_QUEUE_FORMAT_AQL);</div><div class='hunk'>@@ -236,6 +248,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	if (queue_type &lt; 0) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "Queue type not supported with MES, queue:%d\n",</div><div class='ctx'> 			q-&gt;properties.type);</div><div class='add'>+		up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> 	queue_input.queue_type = (uint32_t)queue_type;</div><div class='hunk'>@@ -245,6 +258,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;add_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "failed to add hardware queue to MES, doorbell=0x%x\n",</div><div class='ctx'> 			q-&gt;properties.doorbell_off);</div><div class='hunk'>@@ -262,7 +276,9 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	int r;</div><div class='ctx'> 	struct mes_remove_queue_input queue_input;</div><div class='ctx'> </div><div class='del'>-	if (dqm-&gt;is_hws_hang)</div><div class='add'>+	if (!dqm-&gt;sched_running || dqm-&gt;sched_halt)</div><div class='add'>+		return 0;</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;queue_input, 0x0, sizeof(struct mes_remove_queue_input));</div><div class='hunk'>@@ -272,6 +288,7 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='ctx'> 	r = adev-&gt;mes.funcs-&gt;remove_hw_queue(&amp;adev-&gt;mes, &amp;queue_input);</div><div class='ctx'> 	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> </div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_err(adev-&gt;dev, "failed to remove hardware queue from MES, doorbell=0x%x\n",</div><div class='hunk'>@@ -283,7 +300,7 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int remove_all_queues_mes(struct device_queue_manager *dqm)</div><div class='add'>+static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm)</div><div class='ctx'> {</div><div class='ctx'> 	struct device_process_node *cur;</div><div class='ctx'> 	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='hunk'>@@ -310,6 +327,73 @@ static int remove_all_queues_mes(struct device_queue_manager *dqm)</div><div class='ctx'> 	return retval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int add_all_kfd_queues_mes(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	struct device_process_node *cur;</div><div class='add'>+	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='add'>+	struct qcm_process_device *qpd;</div><div class='add'>+	struct queue *q;</div><div class='add'>+	int retval = 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(cur, &amp;dqm-&gt;queues, list) {</div><div class='add'>+		qpd = cur-&gt;qpd;</div><div class='add'>+		list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+			if (!q-&gt;properties.is_active)</div><div class='add'>+				continue;</div><div class='add'>+			retval = add_queue_mes(dqm, q, qpd);</div><div class='add'>+			if (retval) {</div><div class='add'>+				dev_err(dev, "%s: Failed to add queue %d for dev %d",</div><div class='add'>+					__func__,</div><div class='add'>+					q-&gt;properties.queue_id,</div><div class='add'>+					dqm-&gt;dev-&gt;id);</div><div class='add'>+				return retval;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return retval;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int suspend_all_queues_mes(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)dqm-&gt;dev-&gt;adev;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_suspend(adev);</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to suspend gangs from MES\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "MES might be in unrecoverable state, issue a GPU reset\n");</div><div class='add'>+		kfd_hws_hang(dqm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int resume_all_queues_mes(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)dqm-&gt;dev-&gt;adev;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!down_read_trylock(&amp;adev-&gt;reset_domain-&gt;sem))</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_mes_resume(adev);</div><div class='add'>+	up_read(&amp;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to resume gangs from MES\n");</div><div class='add'>+		dev_err(adev-&gt;dev, "MES might be in unrecoverable state, issue a GPU reset\n");</div><div class='add'>+		kfd_hws_hang(dqm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void increment_queue_count(struct device_queue_manager *dqm,</div><div class='ctx'> 				  struct qcm_process_device *qpd,</div><div class='ctx'> 				  struct queue *q)</div><div class='hunk'>@@ -447,6 +531,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,</div><div class='ctx'> 			struct qcm_process_device *qpd,</div><div class='ctx'> 			struct queue *q)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_process_device *pdd = qpd_to_pdd(qpd);</div><div class='ctx'> 	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='ctx'> 	int allocated_vmid = -1, i;</div><div class='ctx'> </div><div class='hunk'>@@ -465,9 +550,9 @@ static int allocate_vmid(struct device_queue_manager *dqm,</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("vmid allocated: %d\n", allocated_vmid);</div><div class='ctx'> </div><div class='del'>-	dqm-&gt;vmid_pasid[allocated_vmid] = q-&gt;process-&gt;pasid;</div><div class='add'>+	dqm-&gt;vmid_pasid[allocated_vmid] = pdd-&gt;pasid;</div><div class='ctx'> </div><div class='del'>-	set_pasid_vmid_mapping(dqm, q-&gt;process-&gt;pasid, allocated_vmid);</div><div class='add'>+	set_pasid_vmid_mapping(dqm, pdd-&gt;pasid, allocated_vmid);</div><div class='ctx'> </div><div class='ctx'> 	qpd-&gt;vmid = allocated_vmid;</div><div class='ctx'> 	q-&gt;properties.vmid = allocated_vmid;</div><div class='hunk'>@@ -719,6 +804,11 @@ static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* taking the VMID for that process on the safe way using PDD */</div><div class='add'>+	pdd = kfd_get_process_device_data(dev, p);</div><div class='add'>+	if (!pdd)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='ctx'> 	/* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..</div><div class='ctx'> 	 * ATC_VMID15_PASID_MAPPING</div><div class='ctx'> 	 * to check which VMID the current process is mapped to.</div><div class='hunk'>@@ -728,23 +818,19 @@ static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process</div><div class='ctx'> 		status = dev-&gt;kfd2kgd-&gt;get_atc_vmid_pasid_mapping_info</div><div class='ctx'> 				(dev-&gt;adev, vmid, &amp;queried_pasid);</div><div class='ctx'> </div><div class='del'>-		if (status &amp;&amp; queried_pasid == p-&gt;pasid) {</div><div class='del'>-			pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",</div><div class='del'>-					vmid, p-&gt;pasid);</div><div class='add'>+		if (status &amp;&amp; queried_pasid == pdd-&gt;pasid) {</div><div class='add'>+			pr_debug("Killing wave fronts of vmid %d and process pid %d\n",</div><div class='add'>+					vmid, p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (vmid &gt; last_vmid_to_scan) {</div><div class='del'>-		dev_err(dev-&gt;adev-&gt;dev, "Didn't find vmid for pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Didn't find vmid for process pid %d\n",</div><div class='add'>+				p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* taking the VMID for that process on the safe way using PDD */</div><div class='del'>-	pdd = kfd_get_process_device_data(dev, p);</div><div class='del'>-	if (!pdd)</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='ctx'> 	reg_gfx_index.bits.sh_broadcast_writes = 1;</div><div class='ctx'> 	reg_gfx_index.bits.se_broadcast_writes = 1;</div><div class='ctx'> 	reg_gfx_index.bits.instance_broadcast_writes = 1;</div><div class='hunk'>@@ -883,6 +969,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 		else if (prev_active)</div><div class='ctx'> 			retval = remove_queue_mes(dqm, q, &amp;pdd-&gt;qpd);</div><div class='ctx'> </div><div class='add'>+		/* queue is reset so inaccessable  */</div><div class='add'>+		if (pdd-&gt;has_reset_queue) {</div><div class='add'>+			retval = -EACCES;</div><div class='add'>+			goto out_unlock;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (retval) {</div><div class='ctx'> 			dev_err(dev, "unmap queue failed\n");</div><div class='ctx'> 			goto out_unlock;</div><div class='hunk'>@@ -974,8 +1066,8 @@ static int suspend_single_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 	if (q-&gt;properties.is_suspended)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	pr_debug("Suspending PASID %u queue [%i]\n",</div><div class='del'>-			pdd-&gt;process-&gt;pasid,</div><div class='add'>+	pr_debug("Suspending process pid %d queue [%i]\n",</div><div class='add'>+			pdd-&gt;process-&gt;lead_thread-&gt;pid,</div><div class='ctx'> 			q-&gt;properties.queue_id);</div><div class='ctx'> </div><div class='ctx'> 	is_new = q-&gt;properties.exception_status &amp; KFD_EC_MASK(EC_QUEUE_NEW);</div><div class='hunk'>@@ -1022,8 +1114,8 @@ static int resume_single_queue(struct device_queue_manager *dqm,</div><div class='ctx'> </div><div class='ctx'> 	pdd = qpd_to_pdd(qpd);</div><div class='ctx'> </div><div class='del'>-	pr_debug("Restoring from suspend PASID %u queue [%i]\n",</div><div class='del'>-			    pdd-&gt;process-&gt;pasid,</div><div class='add'>+	pr_debug("Restoring from suspend process pid %d queue [%i]\n",</div><div class='add'>+			    pdd-&gt;process-&gt;lead_thread-&gt;pid,</div><div class='ctx'> 			    q-&gt;properties.queue_id);</div><div class='ctx'> </div><div class='ctx'> 	q-&gt;properties.is_suspended = false;</div><div class='hunk'>@@ -1056,8 +1148,8 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	pdd = qpd_to_pdd(qpd);</div><div class='del'>-	pr_debug_ratelimited("Evicting PASID 0x%x queues\n",</div><div class='del'>-			    pdd-&gt;process-&gt;pasid);</div><div class='add'>+	pr_debug_ratelimited("Evicting process pid %d queues\n",</div><div class='add'>+			    pdd-&gt;process-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	pdd-&gt;last_evict_timestamp = get_jiffies_64();</div><div class='ctx'> 	/* Mark all queues as evicted. Deactivate all active queues on</div><div class='hunk'>@@ -1114,8 +1206,17 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 	if (!pdd-&gt;drm_priv)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	pr_debug_ratelimited("Evicting PASID 0x%x queues\n",</div><div class='del'>-			    pdd-&gt;process-&gt;pasid);</div><div class='add'>+	pr_debug_ratelimited("Evicting process pid %d queues\n",</div><div class='add'>+			    pdd-&gt;process-&gt;lead_thread-&gt;pid);</div><div class='add'>+</div><div class='add'>+	if (dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+		pdd-&gt;last_evict_timestamp = get_jiffies_64();</div><div class='add'>+		retval = suspend_all_queues_mes(dqm);</div><div class='add'>+		if (retval) {</div><div class='add'>+			dev_err(dev, "Suspending all queues failed");</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Mark all queues as evicted. Deactivate all active queues on</div><div class='ctx'> 	 * the qpd.</div><div class='hunk'>@@ -1137,13 +1238,19 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	pdd-&gt;last_evict_timestamp = get_jiffies_64();</div><div class='del'>-	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+</div><div class='add'>+	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+		pdd-&gt;last_evict_timestamp = get_jiffies_64();</div><div class='ctx'> 		retval = execute_queues_cpsch(dqm,</div><div class='ctx'> 					      qpd-&gt;is_debug ?</div><div class='ctx'> 					      KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :</div><div class='ctx'> 					      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,</div><div class='ctx'> 					      USE_DEFAULT_GRACE_PERIOD);</div><div class='add'>+	} else {</div><div class='add'>+		retval = resume_all_queues_mes(dqm);</div><div class='add'>+		if (retval)</div><div class='add'>+			dev_err(dev, "Resuming all queues failed");</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	dqm_unlock(dqm);</div><div class='hunk'>@@ -1173,8 +1280,8 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pr_debug_ratelimited("Restoring PASID 0x%x queues\n",</div><div class='del'>-			    pdd-&gt;process-&gt;pasid);</div><div class='add'>+	pr_debug_ratelimited("Restoring process pid %d queues\n",</div><div class='add'>+			    pdd-&gt;process-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	/* Update PD Base in QPD */</div><div class='ctx'> 	qpd-&gt;page_table_base = pd_base;</div><div class='hunk'>@@ -1257,8 +1364,8 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 	if (!pdd-&gt;drm_priv)</div><div class='ctx'> 		goto vm_not_acquired;</div><div class='ctx'> </div><div class='del'>-	pr_debug_ratelimited("Restoring PASID 0x%x queues\n",</div><div class='del'>-			    pdd-&gt;process-&gt;pasid);</div><div class='add'>+	pr_debug_ratelimited("Restoring process pid %d queues\n",</div><div class='add'>+			    pdd-&gt;process-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	/* Update PD Base in QPD */</div><div class='ctx'> 	qpd-&gt;page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd-&gt;drm_priv);</div><div class='hunk'>@@ -1468,20 +1575,13 @@ static int stop_nocpsch(struct device_queue_manager *dqm)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dqm-&gt;dev-&gt;adev-&gt;asic_type == CHIP_HAWAII)</div><div class='del'>-		pm_uninit(&amp;dqm-&gt;packet_mgr, false);</div><div class='add'>+		pm_uninit(&amp;dqm-&gt;packet_mgr);</div><div class='ctx'> 	dqm-&gt;sched_running = false;</div><div class='ctx'> 	dqm_unlock(dqm);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void pre_reset(struct device_queue_manager *dqm)</div><div class='del'>-{</div><div class='del'>-	dqm_lock(dqm);</div><div class='del'>-	dqm-&gt;is_resetting = true;</div><div class='del'>-	dqm_unlock(dqm);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int allocate_sdma_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 				struct queue *q, const uint32_t *restore_sdma_id)</div><div class='ctx'> {</div><div class='hunk'>@@ -1489,8 +1589,9 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 	int bit;</div><div class='ctx'> </div><div class='ctx'> 	if (q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA) {</div><div class='del'>-		if (bitmap_empty(dqm-&gt;sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {</div><div class='del'>-			dev_err(dev, "No more SDMA queue to allocate\n");</div><div class='add'>+		if (bitmap_empty(dqm-&gt;sdma_bitmap, get_num_sdma_queues(dqm))) {</div><div class='add'>+			dev_warn(dev, "No more SDMA queue to allocate (%d total queues)\n",</div><div class='add'>+				 get_num_sdma_queues(dqm));</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1515,8 +1616,9 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 		q-&gt;properties.sdma_queue_id = q-&gt;sdma_id /</div><div class='ctx'> 				kfd_get_num_sdma_engines(dqm-&gt;dev);</div><div class='ctx'> 	} else if (q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {</div><div class='del'>-		if (bitmap_empty(dqm-&gt;xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {</div><div class='del'>-			dev_err(dev, "No more XGMI SDMA queue to allocate\n");</div><div class='add'>+		if (bitmap_empty(dqm-&gt;xgmi_sdma_bitmap, get_num_xgmi_sdma_queues(dqm))) {</div><div class='add'>+			dev_warn(dev, "No more XGMI SDMA queue to allocate (%d total queues)\n",</div><div class='add'>+				 get_num_xgmi_sdma_queues(dqm));</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (restore_sdma_id) {</div><div class='hunk'>@@ -1544,6 +1646,41 @@ static int allocate_sdma_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 			q-&gt;sdma_id % kfd_get_num_xgmi_sdma_engines(dqm-&gt;dev);</div><div class='ctx'> 		q-&gt;properties.sdma_queue_id = q-&gt;sdma_id /</div><div class='ctx'> 			kfd_get_num_xgmi_sdma_engines(dqm-&gt;dev);</div><div class='add'>+	} else if (q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) {</div><div class='add'>+		int i, num_queues, num_engines, eng_offset = 0, start_engine;</div><div class='add'>+		bool free_bit_found = false, is_xgmi = false;</div><div class='add'>+</div><div class='add'>+		if (q-&gt;properties.sdma_engine_id &lt; kfd_get_num_sdma_engines(dqm-&gt;dev)) {</div><div class='add'>+			num_queues = get_num_sdma_queues(dqm);</div><div class='add'>+			num_engines = kfd_get_num_sdma_engines(dqm-&gt;dev);</div><div class='add'>+			q-&gt;properties.type = KFD_QUEUE_TYPE_SDMA;</div><div class='add'>+		} else {</div><div class='add'>+			num_queues = get_num_xgmi_sdma_queues(dqm);</div><div class='add'>+			num_engines = kfd_get_num_xgmi_sdma_engines(dqm-&gt;dev);</div><div class='add'>+			eng_offset = kfd_get_num_sdma_engines(dqm-&gt;dev);</div><div class='add'>+			q-&gt;properties.type = KFD_QUEUE_TYPE_SDMA_XGMI;</div><div class='add'>+			is_xgmi = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Scan available bit based on target engine ID. */</div><div class='add'>+		start_engine = q-&gt;properties.sdma_engine_id - eng_offset;</div><div class='add'>+		for (i = start_engine; i &lt; num_queues; i += num_engines) {</div><div class='add'>+</div><div class='add'>+			if (!test_bit(i, is_xgmi ? dqm-&gt;xgmi_sdma_bitmap : dqm-&gt;sdma_bitmap))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			clear_bit(i, is_xgmi ? dqm-&gt;xgmi_sdma_bitmap : dqm-&gt;sdma_bitmap);</div><div class='add'>+			q-&gt;sdma_id = i;</div><div class='add'>+			q-&gt;properties.sdma_queue_id = q-&gt;sdma_id / num_engines;</div><div class='add'>+			free_bit_found = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!free_bit_found) {</div><div class='add'>+			dev_warn(dev, "No more SDMA queue to allocate for target ID %i (%d total queues)\n",</div><div class='add'>+				 q-&gt;properties.sdma_engine_id, num_queues);</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("SDMA engine id: %d\n", q-&gt;properties.sdma_engine_id);</div><div class='hunk'>@@ -1624,22 +1761,75 @@ static int initialize_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> 	dqm-&gt;active_cp_queue_count = 0;</div><div class='ctx'> 	dqm-&gt;gws_queue_count = 0;</div><div class='ctx'> 	dqm-&gt;active_runlist = false;</div><div class='del'>-	INIT_WORK(&amp;dqm-&gt;hw_exception_work, kfd_process_hw_exception);</div><div class='ctx'> 	dqm-&gt;trap_debug_vmid = 0;</div><div class='ctx'> </div><div class='ctx'> 	init_sdma_bitmaps(dqm);</div><div class='ctx'> </div><div class='del'>-	if (dqm-&gt;dev-&gt;kfd2kgd-&gt;get_iq_wait_times)</div><div class='del'>-		dqm-&gt;dev-&gt;kfd2kgd-&gt;get_iq_wait_times(dqm-&gt;dev-&gt;adev,</div><div class='del'>-					&amp;dqm-&gt;wait_times,</div><div class='del'>-					ffs(dqm-&gt;dev-&gt;xcc_mask) - 1);</div><div class='add'>+	update_dqm_wait_times(dqm);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* halt_cpsch:</div><div class='add'>+ * Unmap queues so the schedule doesn't continue remaining jobs in the queue.</div><div class='add'>+ * Then set dqm-&gt;sched_halt so queues don't map to runlist until unhalt_cpsch</div><div class='add'>+ * is called.</div><div class='add'>+ */</div><div class='add'>+static int halt_cpsch(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	dqm_lock(dqm);</div><div class='add'>+	if (!dqm-&gt;sched_running) {</div><div class='add'>+		dqm_unlock(dqm);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WARN_ONCE(dqm-&gt;sched_halt, "Scheduling is already on halt\n");</div><div class='add'>+</div><div class='add'>+	if (!dqm-&gt;is_hws_hang) {</div><div class='add'>+		if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+			ret = unmap_queues_cpsch(dqm,</div><div class='add'>+						 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,</div><div class='add'>+				USE_DEFAULT_GRACE_PERIOD, false);</div><div class='add'>+		else</div><div class='add'>+			ret = remove_all_kfd_queues_mes(dqm);</div><div class='add'>+	}</div><div class='add'>+	dqm-&gt;sched_halt = true;</div><div class='add'>+	dqm_unlock(dqm);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* unhalt_cpsch</div><div class='add'>+ * Unset dqm-&gt;sched_halt and map queues back to runlist</div><div class='add'>+ */</div><div class='add'>+static int unhalt_cpsch(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	dqm_lock(dqm);</div><div class='add'>+	if (!dqm-&gt;sched_running || !dqm-&gt;sched_halt) {</div><div class='add'>+		WARN_ONCE(!dqm-&gt;sched_halt, "Scheduling is not on halt.\n");</div><div class='add'>+		dqm_unlock(dqm);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	dqm-&gt;sched_halt = false;</div><div class='add'>+	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+		ret = execute_queues_cpsch(dqm,</div><div class='add'>+					   KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,</div><div class='add'>+			0, USE_DEFAULT_GRACE_PERIOD);</div><div class='add'>+	else</div><div class='add'>+		ret = add_all_kfd_queues_mes(dqm);</div><div class='add'>+</div><div class='add'>+	dqm_unlock(dqm);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int start_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='del'>-	int retval;</div><div class='add'>+	int retval, num_hw_queue_slots;</div><div class='ctx'> </div><div class='ctx'> 	retval = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1669,38 +1859,37 @@ static int start_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> 	init_interrupts(dqm);</div><div class='ctx'> </div><div class='ctx'> 	/* clear hang status when driver try to start the hw scheduler */</div><div class='del'>-	dqm-&gt;is_hws_hang = false;</div><div class='del'>-	dqm-&gt;is_resetting = false;</div><div class='ctx'> 	dqm-&gt;sched_running = true;</div><div class='ctx'> </div><div class='del'>-	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+		if (pm_config_dequeue_wait_counts(&amp;dqm-&gt;packet_mgr,</div><div class='add'>+				KFD_DEQUEUE_WAIT_INIT, 0 /* unused */))</div><div class='add'>+			dev_err(dev, "Setting optimized dequeue wait failed. Using default values\n");</div><div class='ctx'> 		execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */</div><div class='del'>-	if (amdgpu_emu_mode == 0 &amp;&amp; dqm-&gt;dev-&gt;adev-&gt;gmc.is_app_apu &amp;&amp;</div><div class='del'>-	    (KFD_GC_VERSION(dqm-&gt;dev) == IP_VERSION(9, 4, 3))) {</div><div class='del'>-		uint32_t reg_offset = 0;</div><div class='del'>-		uint32_t grace_period = 1;</div><div class='add'>+	/* setup per-queue reset detection buffer  */</div><div class='add'>+	num_hw_queue_slots =  dqm-&gt;dev-&gt;kfd-&gt;shared_resources.num_queue_per_pipe *</div><div class='add'>+			      dqm-&gt;dev-&gt;kfd-&gt;shared_resources.num_pipe_per_mec *</div><div class='add'>+			      NUM_XCC(dqm-&gt;dev-&gt;xcc_mask);</div><div class='ctx'> </div><div class='del'>-		retval = pm_update_grace_period(&amp;dqm-&gt;packet_mgr,</div><div class='del'>-						grace_period);</div><div class='del'>-		if (retval)</div><div class='del'>-			dev_err(dev, "Setting grace timeout failed\n");</div><div class='del'>-		else if (dqm-&gt;dev-&gt;kfd2kgd-&gt;build_grace_period_packet_info)</div><div class='del'>-			/* Update dqm-&gt;wait_times maintained in software */</div><div class='del'>-			dqm-&gt;dev-&gt;kfd2kgd-&gt;build_grace_period_packet_info(</div><div class='del'>-					dqm-&gt;dev-&gt;adev,	dqm-&gt;wait_times,</div><div class='del'>-					grace_period, &amp;reg_offset,</div><div class='del'>-					&amp;dqm-&gt;wait_times);</div><div class='add'>+	dqm-&gt;detect_hang_info_size = num_hw_queue_slots * sizeof(struct dqm_detect_hang_info);</div><div class='add'>+	dqm-&gt;detect_hang_info = kzalloc(dqm-&gt;detect_hang_info_size, GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!dqm-&gt;detect_hang_info) {</div><div class='add'>+		retval = -ENOMEM;</div><div class='add'>+		goto fail_detect_hang_buffer;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dqm_unlock(dqm);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+fail_detect_hang_buffer:</div><div class='add'>+	kfd_gtt_sa_free(dqm-&gt;dev, dqm-&gt;fence_mem);</div><div class='ctx'> fail_allocate_vidmem:</div><div class='ctx'> fail_set_sched_resources:</div><div class='ctx'> 	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-		pm_uninit(&amp;dqm-&gt;packet_mgr, false);</div><div class='add'>+		pm_uninit(&amp;dqm-&gt;packet_mgr);</div><div class='ctx'> fail_packet_manager_init:</div><div class='ctx'> 	dqm_unlock(dqm);</div><div class='ctx'> 	return retval;</div><div class='hunk'>@@ -1708,7 +1897,7 @@ fail_packet_manager_init:</div><div class='ctx'> </div><div class='ctx'> static int stop_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> {</div><div class='del'>-	bool hanging;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	dqm_lock(dqm);</div><div class='ctx'> 	if (!dqm-&gt;sched_running) {</div><div class='hunk'>@@ -1716,14 +1905,12 @@ static int stop_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!dqm-&gt;is_hws_hang) {</div><div class='del'>-		if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-			unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);</div><div class='del'>-		else</div><div class='del'>-			remove_all_queues_mes(dqm);</div><div class='del'>-	}</div><div class='add'>+	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+		ret = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,</div><div class='add'>+								0, USE_DEFAULT_GRACE_PERIOD, false);</div><div class='add'>+	else</div><div class='add'>+		ret = remove_all_kfd_queues_mes(dqm);</div><div class='ctx'> </div><div class='del'>-	hanging = dqm-&gt;is_hws_hang || dqm-&gt;is_resetting;</div><div class='ctx'> 	dqm-&gt;sched_running = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='hunk'>@@ -1731,10 +1918,12 @@ static int stop_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> </div><div class='ctx'> 	kfd_gtt_sa_free(dqm-&gt;dev, dqm-&gt;fence_mem);</div><div class='ctx'> 	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-		pm_uninit(&amp;dqm-&gt;packet_mgr, hanging);</div><div class='add'>+		pm_uninit(&amp;dqm-&gt;packet_mgr);</div><div class='add'>+	kfree(dqm-&gt;detect_hang_info);</div><div class='add'>+	dqm-&gt;detect_hang_info = NULL;</div><div class='ctx'> 	dqm_unlock(dqm);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,</div><div class='hunk'>@@ -1803,7 +1992,8 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA ||</div><div class='del'>-		q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {</div><div class='add'>+		q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA_XGMI ||</div><div class='add'>+		q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) {</div><div class='ctx'> 		dqm_lock(dqm);</div><div class='ctx'> 		retval = allocate_sdma_queue(dqm, q, qd ? &amp;qd-&gt;sdma_id : NULL);</div><div class='ctx'> 		dqm_unlock(dqm);</div><div class='hunk'>@@ -1900,11 +2090,12 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm,</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;</div><div class='ctx'> 	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='del'>-	uint64_t *fence_addr =  dqm-&gt;fence_addr;</div><div class='add'>+	uint64_t *fence_addr = dqm-&gt;fence_addr;</div><div class='ctx'> </div><div class='ctx'> 	while (*fence_addr != fence_value) {</div><div class='ctx'> 		/* Fatal err detected, this response won't come */</div><div class='del'>-		if (amdgpu_amdkfd_is_fed(dqm-&gt;dev-&gt;adev))</div><div class='add'>+		if (amdgpu_amdkfd_is_fed(dqm-&gt;dev-&gt;adev) ||</div><div class='add'>+		    amdgpu_in_reset(dqm-&gt;dev-&gt;adev))</div><div class='ctx'> 			return -EIO;</div><div class='ctx'> </div><div class='ctx'> 		if (time_after(jiffies, end_jiffies)) {</div><div class='hunk'>@@ -1930,7 +2121,7 @@ static int map_queues_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> 	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='ctx'> 	int retval;</div><div class='ctx'> </div><div class='del'>-	if (!dqm-&gt;sched_running)</div><div class='add'>+	if (!dqm-&gt;sched_running || dqm-&gt;sched_halt)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	if (dqm-&gt;active_queue_count &lt;= 0 || dqm-&gt;processes_count &lt;= 0)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1948,7 +2139,249 @@ static int map_queues_cpsch(struct device_queue_manager *dqm)</div><div class='ctx'> 	return retval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* dqm-&gt;lock mutex has to be locked before calling this function */</div><div class='add'>+static void set_queue_as_reset(struct device_queue_manager *dqm, struct queue *q,</div><div class='add'>+			       struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process_device *pdd = qpd_to_pdd(qpd);</div><div class='add'>+</div><div class='add'>+	dev_err(dqm-&gt;dev-&gt;adev-&gt;dev, "queue id 0x%0x at pasid %d is reset\n",</div><div class='add'>+		q-&gt;properties.queue_id, pdd-&gt;process-&gt;lead_thread-&gt;pid);</div><div class='add'>+</div><div class='add'>+	pdd-&gt;has_reset_queue = true;</div><div class='add'>+	if (q-&gt;properties.is_active) {</div><div class='add'>+		q-&gt;properties.is_active = false;</div><div class='add'>+		decrement_queue_count(dqm, qpd, q);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int detect_queue_hang(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* detect should be used only in dqm locked queue reset */</div><div class='add'>+	if (WARN_ON(dqm-&gt;detect_hang_count &gt; 0))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	memset(dqm-&gt;detect_hang_info, 0, dqm-&gt;detect_hang_info_size);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_QUEUES; ++i) {</div><div class='add'>+		uint32_t mec, pipe, queue;</div><div class='add'>+		int xcc_id;</div><div class='add'>+</div><div class='add'>+		mec = (i / dqm-&gt;dev-&gt;kfd-&gt;shared_resources.num_queue_per_pipe)</div><div class='add'>+			/ dqm-&gt;dev-&gt;kfd-&gt;shared_resources.num_pipe_per_mec;</div><div class='add'>+</div><div class='add'>+		if (mec || !test_bit(i, dqm-&gt;dev-&gt;kfd-&gt;shared_resources.cp_queue_bitmap))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		amdgpu_queue_mask_bit_to_mec_queue(dqm-&gt;dev-&gt;adev, i, &amp;mec, &amp;pipe, &amp;queue);</div><div class='add'>+</div><div class='add'>+		for_each_inst(xcc_id, dqm-&gt;dev-&gt;xcc_mask) {</div><div class='add'>+			uint64_t queue_addr = dqm-&gt;dev-&gt;kfd2kgd-&gt;hqd_get_pq_addr(</div><div class='add'>+						dqm-&gt;dev-&gt;adev, pipe, queue, xcc_id);</div><div class='add'>+			struct dqm_detect_hang_info hang_info;</div><div class='add'>+</div><div class='add'>+			if (!queue_addr)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			hang_info.pipe_id = pipe;</div><div class='add'>+			hang_info.queue_id = queue;</div><div class='add'>+			hang_info.xcc_id = xcc_id;</div><div class='add'>+			hang_info.queue_address = queue_addr;</div><div class='add'>+</div><div class='add'>+			dqm-&gt;detect_hang_info[dqm-&gt;detect_hang_count] = hang_info;</div><div class='add'>+			dqm-&gt;detect_hang_count++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dqm-&gt;detect_hang_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct queue *find_queue_by_address(struct device_queue_manager *dqm, uint64_t queue_address)</div><div class='add'>+{</div><div class='add'>+	struct device_process_node *cur;</div><div class='add'>+	struct qcm_process_device *qpd;</div><div class='add'>+	struct queue *q;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(cur, &amp;dqm-&gt;queues, list) {</div><div class='add'>+		qpd = cur-&gt;qpd;</div><div class='add'>+		list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+			if (queue_address == q-&gt;properties.queue_address)</div><div class='add'>+				return q;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int reset_hung_queues(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	int r = 0, reset_count = 0, i;</div><div class='add'>+</div><div class='add'>+	if (!dqm-&gt;detect_hang_info || dqm-&gt;is_hws_hang)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	/* assume dqm locked. */</div><div class='add'>+	if (!detect_queue_hang(dqm))</div><div class='add'>+		return -ENOTRECOVERABLE;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dqm-&gt;detect_hang_count; i++) {</div><div class='add'>+		struct dqm_detect_hang_info hang_info = dqm-&gt;detect_hang_info[i];</div><div class='add'>+		struct queue *q = find_queue_by_address(dqm, hang_info.queue_address);</div><div class='add'>+		struct kfd_process_device *pdd;</div><div class='add'>+		uint64_t queue_addr = 0;</div><div class='add'>+</div><div class='add'>+		if (!q) {</div><div class='add'>+			r = -ENOTRECOVERABLE;</div><div class='add'>+			goto reset_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pdd = kfd_get_process_device_data(dqm-&gt;dev, q-&gt;process);</div><div class='add'>+		if (!pdd) {</div><div class='add'>+			r = -ENOTRECOVERABLE;</div><div class='add'>+			goto reset_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		queue_addr = dqm-&gt;dev-&gt;kfd2kgd-&gt;hqd_reset(dqm-&gt;dev-&gt;adev,</div><div class='add'>+				hang_info.pipe_id, hang_info.queue_id, hang_info.xcc_id,</div><div class='add'>+				KFD_UNMAP_LATENCY_MS);</div><div class='add'>+</div><div class='add'>+		/* either reset failed or we reset an unexpected queue. */</div><div class='add'>+		if (queue_addr != q-&gt;properties.queue_address) {</div><div class='add'>+			r = -ENOTRECOVERABLE;</div><div class='add'>+			goto reset_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		set_queue_as_reset(dqm, q, &amp;pdd-&gt;qpd);</div><div class='add'>+		reset_count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (reset_count == dqm-&gt;detect_hang_count)</div><div class='add'>+		kfd_signal_reset_event(dqm-&gt;dev);</div><div class='add'>+	else</div><div class='add'>+		r = -ENOTRECOVERABLE;</div><div class='add'>+</div><div class='add'>+reset_fail:</div><div class='add'>+	dqm-&gt;detect_hang_count = 0;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool sdma_has_hang(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	int engine_start = dqm-&gt;dev-&gt;node_id * get_num_all_sdma_engines(dqm);</div><div class='add'>+	int engine_end = engine_start + get_num_all_sdma_engines(dqm);</div><div class='add'>+	int num_queues_per_eng =  dqm-&gt;dev-&gt;kfd-&gt;device_info.num_sdma_queues_per_engine;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = engine_start; i &lt; engine_end; i++) {</div><div class='add'>+		for (j = 0; j &lt; num_queues_per_eng; j++) {</div><div class='add'>+			if (!dqm-&gt;dev-&gt;kfd2kgd-&gt;hqd_sdma_get_doorbell(dqm-&gt;dev-&gt;adev, i, j))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool set_sdma_queue_as_reset(struct device_queue_manager *dqm,</div><div class='add'>+				    uint32_t doorbell_off)</div><div class='add'>+{</div><div class='add'>+	struct device_process_node *cur;</div><div class='add'>+	struct qcm_process_device *qpd;</div><div class='add'>+	struct queue *q;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(cur, &amp;dqm-&gt;queues, list) {</div><div class='add'>+		qpd = cur-&gt;qpd;</div><div class='add'>+		list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+			if ((q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA ||</div><div class='add'>+			     q-&gt;properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) &amp;&amp;</div><div class='add'>+			     q-&gt;properties.doorbell_off == doorbell_off) {</div><div class='add'>+				set_queue_as_reset(dqm, q, qpd);</div><div class='add'>+				return true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int reset_hung_queues_sdma(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	int engine_start = dqm-&gt;dev-&gt;node_id * get_num_all_sdma_engines(dqm);</div><div class='add'>+	int engine_end = engine_start + get_num_all_sdma_engines(dqm);</div><div class='add'>+	int num_queues_per_eng =  dqm-&gt;dev-&gt;kfd-&gt;device_info.num_sdma_queues_per_engine;</div><div class='add'>+	int r = 0, i, j;</div><div class='add'>+</div><div class='add'>+	if (dqm-&gt;is_hws_hang)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	/* Scan for hung HW queues and reset engine. */</div><div class='add'>+	dqm-&gt;detect_hang_count = 0;</div><div class='add'>+	for (i = engine_start; i &lt; engine_end; i++) {</div><div class='add'>+		for (j = 0; j &lt; num_queues_per_eng; j++) {</div><div class='add'>+			uint32_t doorbell_off =</div><div class='add'>+				dqm-&gt;dev-&gt;kfd2kgd-&gt;hqd_sdma_get_doorbell(dqm-&gt;dev-&gt;adev, i, j);</div><div class='add'>+</div><div class='add'>+			if (!doorbell_off)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			/* Reset engine and check. */</div><div class='add'>+			if (amdgpu_sdma_reset_engine(dqm-&gt;dev-&gt;adev, i, false) ||</div><div class='add'>+			    dqm-&gt;dev-&gt;kfd2kgd-&gt;hqd_sdma_get_doorbell(dqm-&gt;dev-&gt;adev, i, j) ||</div><div class='add'>+			    !set_sdma_queue_as_reset(dqm, doorbell_off)) {</div><div class='add'>+				r = -ENOTRECOVERABLE;</div><div class='add'>+				goto reset_fail;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Should only expect one queue active per engine */</div><div class='add'>+			dqm-&gt;detect_hang_count++;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Signal process reset */</div><div class='add'>+	if (dqm-&gt;detect_hang_count)</div><div class='add'>+		kfd_signal_reset_event(dqm-&gt;dev);</div><div class='add'>+	else</div><div class='add'>+		r = -ENOTRECOVERABLE;</div><div class='add'>+</div><div class='add'>+reset_fail:</div><div class='add'>+	dqm-&gt;detect_hang_count = 0;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int reset_queues_on_hws_hang(struct device_queue_manager *dqm, bool is_sdma)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = dqm-&gt;dev-&gt;adev;</div><div class='add'>+</div><div class='add'>+	while (halt_if_hws_hang)</div><div class='add'>+		schedule();</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;debug_disable_gpu_ring_reset) {</div><div class='add'>+		dev_info_once(adev-&gt;dev,</div><div class='add'>+			      "%s queue hung, but ring reset disabled",</div><div class='add'>+			      is_sdma ? "sdma" : "compute");</div><div class='add'>+</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+	if (!amdgpu_gpu_recovery)</div><div class='add'>+		return -ENOTRECOVERABLE;</div><div class='add'>+</div><div class='add'>+	return is_sdma ? reset_hung_queues_sdma(dqm) : reset_hung_queues(dqm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* dqm-&gt;lock mutex has to be locked before calling this function</div><div class='add'>+ *</div><div class='add'>+ * @grace_period: If USE_DEFAULT_GRACE_PERIOD then default wait time</div><div class='add'>+ *   for context switch latency. Lower values are used by debugger</div><div class='add'>+ *   since context switching are triggered at high frequency.</div><div class='add'>+ *   This is configured by setting CP_IQ_WAIT_TIME2.SCH_WAVE</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='ctx'> static int unmap_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 				enum kfd_unmap_queues_filter filter,</div><div class='ctx'> 				uint32_t filter_param,</div><div class='hunk'>@@ -1957,26 +2390,28 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='ctx'> 	struct mqd_manager *mqd_mgr;</div><div class='del'>-	int retval = 0;</div><div class='add'>+	int retval;</div><div class='ctx'> </div><div class='ctx'> 	if (!dqm-&gt;sched_running)</div><div class='ctx'> 		return 0;</div><div class='del'>-	if (dqm-&gt;is_hws_hang || dqm-&gt;is_resetting)</div><div class='del'>-		return -EIO;</div><div class='ctx'> 	if (!dqm-&gt;active_runlist)</div><div class='del'>-		return retval;</div><div class='add'>+		return 0;</div><div class='add'>+	if (!down_read_trylock(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem))</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	if (grace_period != USE_DEFAULT_GRACE_PERIOD) {</div><div class='del'>-		retval = pm_update_grace_period(&amp;dqm-&gt;packet_mgr, grace_period);</div><div class='add'>+		retval = pm_config_dequeue_wait_counts(&amp;dqm-&gt;packet_mgr,</div><div class='add'>+				KFD_DEQUEUE_WAIT_SET_SCH_WAVE, grace_period);</div><div class='ctx'> 		if (retval)</div><div class='del'>-			return retval;</div><div class='add'>+			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	retval = pm_send_unmap_queue(&amp;dqm-&gt;packet_mgr, filter, filter_param, reset);</div><div class='ctx'> 	if (retval)</div><div class='del'>-		return retval;</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='ctx'> 	*dqm-&gt;fence_addr = KFD_FENCE_INIT;</div><div class='add'>+	mb();</div><div class='ctx'> 	pm_send_query_status(&amp;dqm-&gt;packet_mgr, dqm-&gt;fence_gpu_addr,</div><div class='ctx'> 				KFD_FENCE_COMPLETED);</div><div class='ctx'> 	/* should be timed out */</div><div class='hunk'>@@ -1985,7 +2420,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 	if (retval) {</div><div class='ctx'> 		dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");</div><div class='ctx'> 		kfd_hws_hang(dqm);</div><div class='del'>-		return retval;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* In the current MEC firmware implementation, if compute queue</div><div class='hunk'>@@ -1997,29 +2432,36 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 	 * check those fields</div><div class='ctx'> 	 */</div><div class='ctx'> 	mqd_mgr = dqm-&gt;mqd_mgrs[KFD_MQD_TYPE_HIQ];</div><div class='del'>-	if (mqd_mgr-&gt;read_doorbell_id(dqm-&gt;packet_mgr.priv_queue-&gt;queue-&gt;mqd)) {</div><div class='del'>-		dev_err(dev, "HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n");</div><div class='del'>-		while (halt_if_hws_hang)</div><div class='del'>-			schedule();</div><div class='del'>-		return -ETIME;</div><div class='del'>-	}</div><div class='add'>+	if (mqd_mgr-&gt;check_preemption_failed(mqd_mgr, dqm-&gt;packet_mgr.priv_queue-&gt;queue-&gt;mqd) &amp;&amp;</div><div class='add'>+	    reset_queues_on_hws_hang(dqm, false))</div><div class='add'>+		goto reset_fail;</div><div class='add'>+</div><div class='add'>+	/* Check for SDMA hang and attempt SDMA reset */</div><div class='add'>+	if (sdma_has_hang(dqm) &amp;&amp; reset_queues_on_hws_hang(dqm, true))</div><div class='add'>+		goto reset_fail;</div><div class='ctx'> </div><div class='ctx'> 	/* We need to reset the grace period value for this device */</div><div class='ctx'> 	if (grace_period != USE_DEFAULT_GRACE_PERIOD) {</div><div class='del'>-		if (pm_update_grace_period(&amp;dqm-&gt;packet_mgr,</div><div class='del'>-					USE_DEFAULT_GRACE_PERIOD))</div><div class='add'>+		if (pm_config_dequeue_wait_counts(&amp;dqm-&gt;packet_mgr,</div><div class='add'>+				KFD_DEQUEUE_WAIT_RESET, 0 /* unused */))</div><div class='ctx'> 			dev_err(dev, "Failed to reset grace period\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pm_release_ib(&amp;dqm-&gt;packet_mgr);</div><div class='ctx'> 	dqm-&gt;active_runlist = false;</div><div class='del'>-</div><div class='add'>+out:</div><div class='add'>+	up_read(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	return retval;</div><div class='add'>+</div><div class='add'>+reset_fail:</div><div class='add'>+	dqm-&gt;is_hws_hang = true;</div><div class='add'>+	kfd_hws_hang(dqm);</div><div class='add'>+	up_read(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	return -ETIME;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* only for compute queue */</div><div class='del'>-static int reset_queues_cpsch(struct device_queue_manager *dqm,</div><div class='del'>-			uint16_t pasid)</div><div class='add'>+static int reset_queues_cpsch(struct device_queue_manager *dqm, uint16_t pasid)</div><div class='ctx'> {</div><div class='ctx'> 	int retval;</div><div class='ctx'> </div><div class='hunk'>@@ -2040,13 +2482,13 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> {</div><div class='ctx'> 	int retval;</div><div class='ctx'> </div><div class='del'>-	if (dqm-&gt;is_hws_hang)</div><div class='add'>+	if (!down_read_trylock(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);</div><div class='del'>-	if (retval)</div><div class='del'>-		return retval;</div><div class='del'>-</div><div class='del'>-	return map_queues_cpsch(dqm);</div><div class='add'>+	if (!retval)</div><div class='add'>+		retval = map_queues_cpsch(dqm);</div><div class='add'>+	up_read(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	return retval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int wait_on_destroy_queue(struct device_queue_manager *dqm,</div><div class='hunk'>@@ -2056,6 +2498,9 @@ static int wait_on_destroy_queue(struct device_queue_manager *dqm,</div><div class='ctx'> 								q-&gt;process);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	if (WARN_ON(!pdd))</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	if (pdd-&gt;qpd.is_debug)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -2125,10 +2570,9 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 		pdd-&gt;sdma_past_activity_counter += sdma_val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	list_del(&amp;q-&gt;list);</div><div class='del'>-	qpd-&gt;queue_count--;</div><div class='ctx'> 	if (q-&gt;properties.is_active) {</div><div class='ctx'> 		decrement_queue_count(dqm, qpd, q);</div><div class='add'>+		q-&gt;properties.is_active = false;</div><div class='ctx'> 		if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='ctx'> 			retval = execute_queues_cpsch(dqm,</div><div class='ctx'> 						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,</div><div class='hunk'>@@ -2139,6 +2583,8 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 			retval = remove_queue_mes(dqm, q, qpd);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	list_del(&amp;q-&gt;list);</div><div class='add'>+	qpd-&gt;queue_count--;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Unconditionally decrement this counter, regardless of the queue's</div><div class='hunk'>@@ -2168,20 +2614,13 @@ failed_try_destroy_debugged_queue:</div><div class='ctx'> 	return retval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to</div><div class='del'>- * stay in user mode.</div><div class='del'>- */</div><div class='del'>-#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL</div><div class='del'>-/* APE1 limit is inclusive and 64K aligned. */</div><div class='del'>-#define APE1_LIMIT_ALIGNMENT 0xFFFF</div><div class='del'>-</div><div class='ctx'> static bool set_cache_memory_policy(struct device_queue_manager *dqm,</div><div class='ctx'> 				   struct qcm_process_device *qpd,</div><div class='ctx'> 				   enum cache_policy default_policy,</div><div class='ctx'> 				   enum cache_policy alternate_policy,</div><div class='ctx'> 				   void __user *alternate_aperture_base,</div><div class='del'>-				   uint64_t alternate_aperture_size)</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties)</div><div class='ctx'> {</div><div class='ctx'> 	bool retval = true;</div><div class='ctx'> </div><div class='hunk'>@@ -2190,41 +2629,17 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm,</div><div class='ctx'> </div><div class='ctx'> 	dqm_lock(dqm);</div><div class='ctx'> </div><div class='del'>-	if (alternate_aperture_size == 0) {</div><div class='del'>-		/* base &gt; limit disables APE1 */</div><div class='del'>-		qpd-&gt;sh_mem_ape1_base = 1;</div><div class='del'>-		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='del'>-	} else {</div><div class='del'>-		/*</div><div class='del'>-		 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},</div><div class='del'>-		 *			SH_MEM_APE1_BASE[31:0], 0x0000 }</div><div class='del'>-		 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},</div><div class='del'>-		 *			SH_MEM_APE1_LIMIT[31:0], 0xFFFF }</div><div class='del'>-		 * Verify that the base and size parameters can be</div><div class='del'>-		 * represented in this format and convert them.</div><div class='del'>-		 * Additionally restrict APE1 to user-mode addresses.</div><div class='del'>-		 */</div><div class='del'>-</div><div class='del'>-		uint64_t base = (uintptr_t)alternate_aperture_base;</div><div class='del'>-		uint64_t limit = base + alternate_aperture_size - 1;</div><div class='del'>-</div><div class='del'>-		if (limit &lt;= base || (base &amp; APE1_FIXED_BITS_MASK) != 0 ||</div><div class='del'>-		   (limit &amp; APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {</div><div class='del'>-			retval = false;</div><div class='del'>-			goto out;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		qpd-&gt;sh_mem_ape1_base = base &gt;&gt; 16;</div><div class='del'>-		qpd-&gt;sh_mem_ape1_limit = limit &gt;&gt; 16;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	retval = dqm-&gt;asic_ops.set_cache_memory_policy(</div><div class='ctx'> 			dqm,</div><div class='ctx'> 			qpd,</div><div class='ctx'> 			default_policy,</div><div class='ctx'> 			alternate_policy,</div><div class='ctx'> 			alternate_aperture_base,</div><div class='del'>-			alternate_aperture_size);</div><div class='add'>+			alternate_aperture_size,</div><div class='add'>+			misc_process_properties);</div><div class='add'>+</div><div class='add'>+	if (retval)</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if ((dqm-&gt;sched_policy == KFD_SCHED_POLICY_NO_HWS) &amp;&amp; (qpd-&gt;vmid != 0))</div><div class='ctx'> 		program_sh_mem_settings(dqm, qpd);</div><div class='hunk'>@@ -2327,7 +2742,7 @@ static void get_queue_checkpoint_info(struct device_queue_manager *dqm,</div><div class='ctx'> </div><div class='ctx'> 	dqm_lock(dqm);</div><div class='ctx'> 	mqd_mgr = dqm-&gt;mqd_mgrs[mqd_type];</div><div class='del'>-	*mqd_size = mqd_mgr-&gt;mqd_size;</div><div class='add'>+	*mqd_size = mqd_mgr-&gt;mqd_size * NUM_XCC(mqd_mgr-&gt;dev-&gt;xcc_mask);</div><div class='ctx'> 	*ctl_stack_size = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (q-&gt;properties.type == KFD_QUEUE_TYPE_COMPUTE &amp;&amp; mqd_mgr-&gt;get_checkpoint_info)</div><div class='hunk'>@@ -2427,10 +2842,12 @@ static int process_termination_cpsch(struct device_queue_manager *dqm,</div><div class='ctx'> 	if (!dqm-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='ctx'> 		retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD);</div><div class='ctx'> </div><div class='del'>-	if ((!dqm-&gt;is_hws_hang) &amp;&amp; (retval || qpd-&gt;reset_wavefronts)) {</div><div class='add'>+	if ((retval || qpd-&gt;reset_wavefronts) &amp;&amp;</div><div class='add'>+	    down_read_trylock(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem)) {</div><div class='ctx'> 		pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm-&gt;dev);</div><div class='ctx'> 		dbgdev_wave_reset_wavefronts(dqm-&gt;dev, qpd-&gt;pqm-&gt;process);</div><div class='ctx'> 		qpd-&gt;reset_wavefronts = false;</div><div class='add'>+		up_read(&amp;dqm-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Lastly, free mqd resources.</div><div class='hunk'>@@ -2537,7 +2954,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)</div><div class='ctx'> 		dqm-&gt;ops.initialize = initialize_cpsch;</div><div class='ctx'> 		dqm-&gt;ops.start = start_cpsch;</div><div class='ctx'> 		dqm-&gt;ops.stop = stop_cpsch;</div><div class='del'>-		dqm-&gt;ops.pre_reset = pre_reset;</div><div class='add'>+		dqm-&gt;ops.halt = halt_cpsch;</div><div class='add'>+		dqm-&gt;ops.unhalt = unhalt_cpsch;</div><div class='ctx'> 		dqm-&gt;ops.destroy_queue = destroy_queue_cpsch;</div><div class='ctx'> 		dqm-&gt;ops.update_queue = update_queue;</div><div class='ctx'> 		dqm-&gt;ops.register_process = register_process;</div><div class='hunk'>@@ -2558,7 +2976,6 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)</div><div class='ctx'> 		/* initialize dqm for no cp scheduling */</div><div class='ctx'> 		dqm-&gt;ops.start = start_nocpsch;</div><div class='ctx'> 		dqm-&gt;ops.stop = stop_nocpsch;</div><div class='del'>-		dqm-&gt;ops.pre_reset = pre_reset;</div><div class='ctx'> 		dqm-&gt;ops.create_queue = create_queue_nocpsch;</div><div class='ctx'> 		dqm-&gt;ops.destroy_queue = destroy_queue_nocpsch;</div><div class='ctx'> 		dqm-&gt;ops.update_queue = update_queue;</div><div class='hunk'>@@ -2597,7 +3014,9 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='del'>-		if (KFD_GC_VERSION(dev) &gt;= IP_VERSION(11, 0, 0))</div><div class='add'>+		if (KFD_GC_VERSION(dev) &gt;= IP_VERSION(12, 0, 0))</div><div class='add'>+			device_queue_manager_init_v12(&amp;dqm-&gt;asic_ops);</div><div class='add'>+		else if (KFD_GC_VERSION(dev) &gt;= IP_VERSION(11, 0, 0))</div><div class='ctx'> 			device_queue_manager_init_v11(&amp;dqm-&gt;asic_ops);</div><div class='ctx'> 		else if (KFD_GC_VERSION(dev) &gt;= IP_VERSION(10, 1, 1))</div><div class='ctx'> 			device_queue_manager_init_v10(&amp;dqm-&gt;asic_ops);</div><div class='hunk'>@@ -2633,7 +3052,7 @@ static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,</div><div class='ctx'> {</div><div class='ctx'> 	WARN(!mqd, "No hiq sdma mqd trunk to free");</div><div class='ctx'> </div><div class='del'>-	amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, mqd-&gt;gtt_mem);</div><div class='add'>+	amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, &amp;mqd-&gt;gtt_mem);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void device_queue_manager_uninit(struct device_queue_manager *dqm)</div><div class='hunk'>@@ -2645,28 +3064,68 @@ void device_queue_manager_uninit(struct device_queue_manager *dqm)</div><div class='ctx'> 	kfree(dqm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid)</div><div class='add'>+int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_process_device *pdd;</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	struct kfd_process_device *pdd = NULL;</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, &amp;pdd);</div><div class='add'>+	struct device_queue_manager *dqm = knode-&gt;dqm;</div><div class='add'>+	struct device *dev = dqm-&gt;dev-&gt;adev-&gt;dev;</div><div class='add'>+	struct qcm_process_device *qpd;</div><div class='add'>+	struct queue *q = NULL;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (!p)</div><div class='add'>+	if (!pdd)</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	WARN(debug_evictions, "Evicting pid %d", p-&gt;lead_thread-&gt;pid);</div><div class='del'>-	pdd = kfd_get_process_device_data(dqm-&gt;dev, p);</div><div class='del'>-	if (pdd)</div><div class='del'>-		ret = dqm-&gt;ops.evict_process_queues(dqm, &amp;pdd-&gt;qpd);</div><div class='del'>-	kfd_unref_process(p);</div><div class='ctx'> </div><div class='add'>+	dqm_lock(dqm);</div><div class='add'>+</div><div class='add'>+	if (pdd) {</div><div class='add'>+		qpd = &amp;pdd-&gt;qpd;</div><div class='add'>+</div><div class='add'>+		list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+			if (q-&gt;doorbell_id == doorbell_id &amp;&amp; q-&gt;properties.is_active) {</div><div class='add'>+				ret = suspend_all_queues_mes(dqm);</div><div class='add'>+				if (ret) {</div><div class='add'>+					dev_err(dev, "Suspending all queues failed");</div><div class='add'>+					goto out;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				q-&gt;properties.is_evicted = true;</div><div class='add'>+				q-&gt;properties.is_active = false;</div><div class='add'>+				decrement_queue_count(dqm, qpd, q);</div><div class='add'>+</div><div class='add'>+				ret = remove_queue_mes(dqm, q, qpd);</div><div class='add'>+				if (ret) {</div><div class='add'>+					dev_err(dev, "Removing bad queue failed");</div><div class='add'>+					goto out;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				ret = resume_all_queues_mes(dqm);</div><div class='add'>+				if (ret)</div><div class='add'>+					dev_err(dev, "Resuming all queues failed");</div><div class='add'>+</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	dqm_unlock(dqm);</div><div class='add'>+	kfd_unref_process(p);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void kfd_process_hw_exception(struct work_struct *work)</div><div class='add'>+int kfd_evict_process_device(struct kfd_process_device *pdd)</div><div class='ctx'> {</div><div class='del'>-	struct device_queue_manager *dqm = container_of(work,</div><div class='del'>-			struct device_queue_manager, hw_exception_work);</div><div class='del'>-	amdgpu_amdkfd_gpu_reset(dqm-&gt;dev-&gt;adev);</div><div class='add'>+	struct device_queue_manager *dqm;</div><div class='add'>+	struct kfd_process *p;</div><div class='add'>+</div><div class='add'>+	p = pdd-&gt;process;</div><div class='add'>+	dqm = pdd-&gt;dev-&gt;dqm;</div><div class='add'>+</div><div class='add'>+	WARN(debug_evictions, "Evicting pid %d", p-&gt;lead_thread-&gt;pid);</div><div class='add'>+</div><div class='add'>+	return dqm-&gt;ops.evict_process_queues(dqm, &amp;pdd-&gt;qpd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int reserve_debug_trap_vmid(struct device_queue_manager *dqm,</div><div class='hunk'>@@ -2792,7 +3251,7 @@ struct copy_context_work_handler_workarea {</div><div class='ctx'> 	struct kfd_process *p;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void copy_context_work_handler (struct work_struct *work)</div><div class='add'>+static void copy_context_work_handler(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct copy_context_work_handler_workarea *workarea;</div><div class='ctx'> 	struct mqd_manager *mqd_mgr;</div><div class='hunk'>@@ -2819,6 +3278,9 @@ static void copy_context_work_handler (struct work_struct *work)</div><div class='ctx'> 		struct qcm_process_device *qpd = &amp;pdd-&gt;qpd;</div><div class='ctx'> </div><div class='ctx'> 		list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+			if (q-&gt;properties.type != KFD_QUEUE_TYPE_COMPUTE)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='ctx'> 			mqd_mgr = dqm-&gt;mqd_mgrs[KFD_MQD_TYPE_CP];</div><div class='ctx'> </div><div class='ctx'> 			/* We ignore the return value from get_wave_state</div><div class='hunk'>@@ -3159,6 +3621,30 @@ int debug_refresh_runlist(struct device_queue_manager *dqm)</div><div class='ctx'> 	return debug_map_and_unlock(dqm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm,</div><div class='add'>+				 struct qcm_process_device *qpd,</div><div class='add'>+				 int doorbell_off, u32 *queue_format)</div><div class='add'>+{</div><div class='add'>+	struct queue *q;</div><div class='add'>+	bool r = false;</div><div class='add'>+</div><div class='add'>+	if (!queue_format)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='add'>+	dqm_lock(dqm);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;qpd-&gt;queues_list, list) {</div><div class='add'>+		if (q-&gt;properties.doorbell_off == doorbell_off) {</div><div class='add'>+			*queue_format = q-&gt;properties.format;</div><div class='add'>+			r = true;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	dqm_unlock(dqm);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> </div><div class='ctx'> static void seq_reg_dump(struct seq_file *m,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h<br/>index cf7e182588f8..74a61b5b2f0b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h</a></div><div class='hunk'>@@ -37,7 +37,6 @@</div><div class='ctx'> </div><div class='ctx'> #define KFD_MES_PROCESS_QUANTUM		100000</div><div class='ctx'> #define KFD_MES_GANG_QUANTUM		10000</div><div class='del'>-#define USE_DEFAULT_GRACE_PERIOD 0xffffffff</div><div class='ctx'> </div><div class='ctx'> struct device_process_node {</div><div class='ctx'> 	struct qcm_process_device *qpd;</div><div class='hunk'>@@ -106,6 +105,12 @@ union GRBM_GFX_INDEX_BITS {</div><div class='ctx'>  * @uninitialize: Destroys all the device queue manager resources allocated in</div><div class='ctx'>  * initialize routine.</div><div class='ctx'>  *</div><div class='add'>+ * @halt: This routine unmaps queues from runlist and set halt status to true</div><div class='add'>+ * so no more queues will be mapped to runlist until unhalt.</div><div class='add'>+ *</div><div class='add'>+ * @unhalt: This routine unset halt status to flase and maps queues back to</div><div class='add'>+ * runlist.</div><div class='add'>+ *</div><div class='ctx'>  * @create_kernel_queue: Creates kernel queue. Used for debug queue.</div><div class='ctx'>  *</div><div class='ctx'>  * @destroy_kernel_queue: Destroys kernel queue. Used for debug queue.</div><div class='hunk'>@@ -152,8 +157,9 @@ struct device_queue_manager_ops {</div><div class='ctx'> 	int	(*initialize)(struct device_queue_manager *dqm);</div><div class='ctx'> 	int	(*start)(struct device_queue_manager *dqm);</div><div class='ctx'> 	int	(*stop)(struct device_queue_manager *dqm);</div><div class='del'>-	void	(*pre_reset)(struct device_queue_manager *dqm);</div><div class='ctx'> 	void	(*uninitialize)(struct device_queue_manager *dqm);</div><div class='add'>+	int     (*halt)(struct device_queue_manager *dqm);</div><div class='add'>+	int     (*unhalt)(struct device_queue_manager *dqm);</div><div class='ctx'> 	int	(*create_kernel_queue)(struct device_queue_manager *dqm,</div><div class='ctx'> 					struct kernel_queue *kq,</div><div class='ctx'> 					struct qcm_process_device *qpd);</div><div class='hunk'>@@ -167,7 +173,8 @@ struct device_queue_manager_ops {</div><div class='ctx'> 					   enum cache_policy default_policy,</div><div class='ctx'> 					   enum cache_policy alternate_policy,</div><div class='ctx'> 					   void __user *alternate_aperture_base,</div><div class='del'>-					   uint64_t alternate_aperture_size);</div><div class='add'>+					   uint64_t alternate_aperture_size,</div><div class='add'>+					   u32 misc_process_properties);</div><div class='ctx'> </div><div class='ctx'> 	int (*process_termination)(struct device_queue_manager *dqm,</div><div class='ctx'> 			struct qcm_process_device *qpd);</div><div class='hunk'>@@ -203,7 +210,8 @@ struct device_queue_manager_asic_ops {</div><div class='ctx'> 					   enum cache_policy default_policy,</div><div class='ctx'> 					   enum cache_policy alternate_policy,</div><div class='ctx'> 					   void __user *alternate_aperture_base,</div><div class='del'>-					   uint64_t alternate_aperture_size);</div><div class='add'>+					   uint64_t alternate_aperture_size,</div><div class='add'>+					   u32 misc_process_properties);</div><div class='ctx'> 	void	(*init_sdma_vm)(struct device_queue_manager *dqm,</div><div class='ctx'> 				struct queue *q,</div><div class='ctx'> 				struct qcm_process_device *qpd);</div><div class='hunk'>@@ -211,6 +219,13 @@ struct device_queue_manager_asic_ops {</div><div class='ctx'> 				 struct kfd_node *dev);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dqm_detect_hang_info {</div><div class='add'>+	int pipe_id;</div><div class='add'>+	int queue_id;</div><div class='add'>+	int xcc_id;</div><div class='add'>+	uint64_t queue_address;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct device_queue_manager</div><div class='ctx'>  *</div><div class='hunk'>@@ -255,9 +270,9 @@ struct device_queue_manager {</div><div class='ctx'> 	/* hw exception  */</div><div class='ctx'> 	bool			is_hws_hang;</div><div class='ctx'> 	bool			is_resetting;</div><div class='del'>-	struct work_struct	hw_exception_work;</div><div class='ctx'> 	struct kfd_mem_obj	hiq_sdma_mqd;</div><div class='ctx'> 	bool			sched_running;</div><div class='add'>+	bool			sched_halt;</div><div class='ctx'> </div><div class='ctx'> 	/* used for GFX 9.4.3 only */</div><div class='ctx'> 	uint32_t		current_logical_xcc_start;</div><div class='hunk'>@@ -265,6 +280,11 @@ struct device_queue_manager {</div><div class='ctx'> 	uint32_t		wait_times;</div><div class='ctx'> </div><div class='ctx'> 	wait_queue_head_t	destroy_wait;</div><div class='add'>+</div><div class='add'>+	/* for per-queue reset support */</div><div class='add'>+	struct dqm_detect_hang_info *detect_hang_info;</div><div class='add'>+	size_t detect_hang_info_size;</div><div class='add'>+	int detect_hang_count;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void device_queue_manager_init_cik(</div><div class='hunk'>@@ -277,6 +297,8 @@ void device_queue_manager_init_v10(</div><div class='ctx'> 		struct device_queue_manager_asic_ops *asic_ops);</div><div class='ctx'> void device_queue_manager_init_v11(</div><div class='ctx'> 		struct device_queue_manager_asic_ops *asic_ops);</div><div class='add'>+void device_queue_manager_init_v12(</div><div class='add'>+		struct device_queue_manager_asic_ops *asic_ops);</div><div class='ctx'> void program_sh_mem_settings(struct device_queue_manager *dqm,</div><div class='ctx'> 					struct qcm_process_device *qpd);</div><div class='ctx'> unsigned int get_cp_queues_num(struct device_queue_manager *dqm);</div><div class='hunk'>@@ -302,6 +324,9 @@ void set_queue_snapshot_entry(struct queue *q,</div><div class='ctx'> int debug_lock_and_unmap(struct device_queue_manager *dqm);</div><div class='ctx'> int debug_map_and_unlock(struct device_queue_manager *dqm);</div><div class='ctx'> int debug_refresh_runlist(struct device_queue_manager *dqm);</div><div class='add'>+bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm,</div><div class='add'>+				 struct qcm_process_device *qpd,</div><div class='add'>+				 int doorbell_off, u32 *queue_format);</div><div class='ctx'> </div><div class='ctx'> static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)</div><div class='ctx'> {</div><div class='hunk'>@@ -334,4 +359,14 @@ static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val</div><div class='ctx'> 	/* SDMA activity counter is stored at queue's RPTR + 0x8 location. */</div><div class='ctx'> 	return get_user(*val, q_rptr + 1);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static inline void update_dqm_wait_times(struct device_queue_manager *dqm)</div><div class='add'>+{</div><div class='add'>+	if (dqm-&gt;dev-&gt;kfd2kgd-&gt;get_iq_wait_times)</div><div class='add'>+		dqm-&gt;dev-&gt;kfd2kgd-&gt;get_iq_wait_times(dqm-&gt;dev-&gt;adev,</div><div class='add'>+					&amp;dqm-&gt;wait_times,</div><div class='add'>+					ffs(dqm-&gt;dev-&gt;xcc_mask) - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> #endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c<br/>index d4d95c7f2e5d..0508ef5a41d7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c</a></div><div class='hunk'>@@ -27,12 +27,21 @@</div><div class='ctx'> #include "oss/oss_2_4_sh_mask.h"</div><div class='ctx'> #include "gca/gfx_7_2_sh_mask.h"</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to</div><div class='add'>+ * stay in user mode.</div><div class='add'>+ */</div><div class='add'>+#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL</div><div class='add'>+/* APE1 limit is inclusive and 64K aligned. */</div><div class='add'>+#define APE1_LIMIT_ALIGNMENT 0xFFFF</div><div class='add'>+</div><div class='ctx'> static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,</div><div class='ctx'> 				   struct qcm_process_device *qpd,</div><div class='ctx'> 				   enum cache_policy default_policy,</div><div class='ctx'> 				   enum cache_policy alternate_policy,</div><div class='ctx'> 				   void __user *alternate_aperture_base,</div><div class='del'>-				   uint64_t alternate_aperture_size);</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties);</div><div class='ctx'> static int update_qpd_cik(struct device_queue_manager *dqm,</div><div class='ctx'> 			  struct qcm_process_device *qpd);</div><div class='ctx'> static void init_sdma_vm(struct device_queue_manager *dqm,</div><div class='hunk'>@@ -80,10 +89,41 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,</div><div class='ctx'> 				   enum cache_policy default_policy,</div><div class='ctx'> 				   enum cache_policy alternate_policy,</div><div class='ctx'> 				   void __user *alternate_aperture_base,</div><div class='del'>-				   uint64_t alternate_aperture_size)</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t default_mtype;</div><div class='ctx'> 	uint32_t ape1_mtype;</div><div class='add'>+	unsigned int temp;</div><div class='add'>+	bool retval = true;</div><div class='add'>+</div><div class='add'>+	if (alternate_aperture_size == 0) {</div><div class='add'>+		/* base &gt; limit disables APE1 */</div><div class='add'>+		qpd-&gt;sh_mem_ape1_base = 1;</div><div class='add'>+		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},</div><div class='add'>+		 *			SH_MEM_APE1_BASE[31:0], 0x0000 }</div><div class='add'>+		 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},</div><div class='add'>+		 *			SH_MEM_APE1_LIMIT[31:0], 0xFFFF }</div><div class='add'>+		 * Verify that the base and size parameters can be</div><div class='add'>+		 * represented in this format and convert them.</div><div class='add'>+		 * Additionally restrict APE1 to user-mode addresses.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		uint64_t base = (uintptr_t)alternate_aperture_base;</div><div class='add'>+		uint64_t limit = base + alternate_aperture_size - 1;</div><div class='add'>+</div><div class='add'>+		if (limit &lt;= base || (base &amp; APE1_FIXED_BITS_MASK) != 0 ||</div><div class='add'>+		   (limit &amp; APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {</div><div class='add'>+			retval = false;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		qpd-&gt;sh_mem_ape1_base = base &gt;&gt; 16;</div><div class='add'>+		qpd-&gt;sh_mem_ape1_limit = limit &gt;&gt; 16;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	default_mtype = (default_policy == cache_policy_coherent) ?</div><div class='ctx'> 			MTYPE_NONCACHED :</div><div class='hunk'>@@ -97,37 +137,22 @@ static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm,</div><div class='ctx'> 			| ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)</div><div class='ctx'> 			| DEFAULT_MTYPE(default_mtype)</div><div class='ctx'> 			| APE1_MTYPE(ape1_mtype);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int update_qpd_cik(struct device_queue_manager *dqm,</div><div class='del'>-			  struct qcm_process_device *qpd)</div><div class='del'>-{</div><div class='del'>-	struct kfd_process_device *pdd;</div><div class='del'>-	unsigned int temp;</div><div class='del'>-</div><div class='del'>-	pdd = qpd_to_pdd(qpd);</div><div class='del'>-</div><div class='del'>-	/* check if sh_mem_config register already configured */</div><div class='del'>-	if (qpd-&gt;sh_mem_config == 0) {</div><div class='del'>-		qpd-&gt;sh_mem_config =</div><div class='del'>-			ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) |</div><div class='del'>-			DEFAULT_MTYPE(MTYPE_NONCACHED) |</div><div class='del'>-			APE1_MTYPE(MTYPE_NONCACHED);</div><div class='del'>-		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='del'>-		qpd-&gt;sh_mem_ape1_base = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* On dGPU we're always in GPUVM64 addressing mode with 64-bit</div><div class='ctx'> 	 * aperture addresses.</div><div class='ctx'> 	 */</div><div class='del'>-	temp = get_sh_mem_bases_nybble_64(pdd);</div><div class='add'>+	temp = get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd));</div><div class='ctx'> 	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(temp);</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n",</div><div class='ctx'> 		qpd-&gt;pqm-&gt;process-&gt;is_32bit_user_mode, temp, qpd-&gt;sh_mem_bases);</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+	return retval;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int update_qpd_cik(struct device_queue_manager *dqm,</div><div class='add'>+			  struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c<br/>index 245a90dfc2f6..ba6e3d747ccd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c</a></div><div class='hunk'>@@ -31,10 +31,18 @@ static int update_qpd_v10(struct device_queue_manager *dqm,</div><div class='ctx'> 			 struct qcm_process_device *qpd);</div><div class='ctx'> static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 			    struct qcm_process_device *qpd);</div><div class='add'>+static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties);</div><div class='ctx'> </div><div class='ctx'> void device_queue_manager_init_v10(</div><div class='ctx'> 	struct device_queue_manager_asic_ops *asic_ops)</div><div class='ctx'> {</div><div class='add'>+	asic_ops-&gt;set_cache_memory_policy = set_cache_memory_policy_v10;</div><div class='ctx'> 	asic_ops-&gt;update_qpd = update_qpd_v10;</div><div class='ctx'> 	asic_ops-&gt;init_sdma_vm = init_sdma_vm_v10;</div><div class='ctx'> 	asic_ops-&gt;mqd_manager_init = mqd_manager_init_v10;</div><div class='hunk'>@@ -49,27 +57,28 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)</div><div class='ctx'> 		private_base;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int update_qpd_v10(struct device_queue_manager *dqm,</div><div class='del'>-			 struct qcm_process_device *qpd)</div><div class='add'>+static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_process_device *pdd;</div><div class='del'>-</div><div class='del'>-	pdd = qpd_to_pdd(qpd);</div><div class='del'>-</div><div class='del'>-	/* check if sh_mem_config register already configured */</div><div class='del'>-	if (qpd-&gt;sh_mem_config == 0) {</div><div class='del'>-		qpd-&gt;sh_mem_config =</div><div class='del'>-			(SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='del'>-				SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |</div><div class='del'>-			(3 &lt;&lt; SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);</div><div class='del'>-		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='del'>-		qpd-&gt;sh_mem_ape1_base = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(pdd);</div><div class='add'>+	qpd-&gt;sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='add'>+			      SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |</div><div class='add'>+			      (3 &lt;&lt; SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);</div><div class='add'>+	qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='add'>+	qpd-&gt;sh_mem_ape1_base = 0;</div><div class='add'>+	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("sh_mem_bases 0x%X\n", qpd-&gt;sh_mem_bases);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static int update_qpd_v10(struct device_queue_manager *dqm,</div><div class='add'>+			 struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c<br/>index 2e129da7acb4..8b447d04558f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c</a></div><div class='hunk'>@@ -30,10 +30,18 @@ static int update_qpd_v11(struct device_queue_manager *dqm,</div><div class='ctx'> 			 struct qcm_process_device *qpd);</div><div class='ctx'> static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 			    struct qcm_process_device *qpd);</div><div class='add'>+static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties);</div><div class='ctx'> </div><div class='ctx'> void device_queue_manager_init_v11(</div><div class='ctx'> 	struct device_queue_manager_asic_ops *asic_ops)</div><div class='ctx'> {</div><div class='add'>+	asic_ops-&gt;set_cache_memory_policy = set_cache_memory_policy_v11;</div><div class='ctx'> 	asic_ops-&gt;update_qpd = update_qpd_v11;</div><div class='ctx'> 	asic_ops-&gt;init_sdma_vm = init_sdma_vm_v11;</div><div class='ctx'> 	asic_ops-&gt;mqd_manager_init = mqd_manager_init_v11;</div><div class='hunk'>@@ -48,28 +56,29 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)</div><div class='ctx'> 		private_base;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int update_qpd_v11(struct device_queue_manager *dqm,</div><div class='del'>-			 struct qcm_process_device *qpd)</div><div class='add'>+static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_process_device *pdd;</div><div class='del'>-</div><div class='del'>-	pdd = qpd_to_pdd(qpd);</div><div class='del'>-</div><div class='del'>-	/* check if sh_mem_config register already configured */</div><div class='del'>-	if (qpd-&gt;sh_mem_config == 0) {</div><div class='del'>-		qpd-&gt;sh_mem_config =</div><div class='del'>-			(SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='del'>-				SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |</div><div class='del'>-			(3 &lt;&lt; SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);</div><div class='del'>-</div><div class='del'>-		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='del'>-		qpd-&gt;sh_mem_ape1_base = 0;</div><div class='del'>-	}</div><div class='add'>+	qpd-&gt;sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='add'>+			      SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |</div><div class='add'>+			      (3 &lt;&lt; SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);</div><div class='ctx'> </div><div class='del'>-	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(pdd);</div><div class='add'>+	qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='add'>+	qpd-&gt;sh_mem_ape1_base = 0;</div><div class='add'>+	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("sh_mem_bases 0x%X\n", qpd-&gt;sh_mem_bases);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static int update_qpd_v11(struct device_queue_manager *dqm,</div><div class='add'>+			 struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c<br/>new file mode 100644<br/>index 000000000000..3550da3a46f9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c</a></div><div class='hunk'>@@ -0,0 +1,90 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "kfd_device_queue_manager.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "soc24_enum.h"</div><div class='add'>+</div><div class='add'>+static int update_qpd_v12(struct device_queue_manager *dqm,</div><div class='add'>+			 struct qcm_process_device *qpd);</div><div class='add'>+static void init_sdma_vm_v12(struct device_queue_manager *dqm, struct queue *q,</div><div class='add'>+			    struct qcm_process_device *qpd);</div><div class='add'>+static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties);</div><div class='add'>+</div><div class='add'>+void device_queue_manager_init_v12(</div><div class='add'>+	struct device_queue_manager_asic_ops *asic_ops)</div><div class='add'>+{</div><div class='add'>+	asic_ops-&gt;set_cache_memory_policy = set_cache_memory_policy_v12;</div><div class='add'>+	asic_ops-&gt;update_qpd = update_qpd_v12;</div><div class='add'>+	asic_ops-&gt;init_sdma_vm = init_sdma_vm_v12;</div><div class='add'>+	asic_ops-&gt;mqd_manager_init = mqd_manager_init_v12;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)</div><div class='add'>+{</div><div class='add'>+	uint32_t shared_base = pdd-&gt;lds_base &gt;&gt; 48;</div><div class='add'>+	uint32_t private_base = pdd-&gt;scratch_base &gt;&gt; 48;</div><div class='add'>+</div><div class='add'>+	return (shared_base &lt;&lt; SH_MEM_BASES__SHARED_BASE__SHIFT) |</div><div class='add'>+		private_base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties)</div><div class='add'>+{</div><div class='add'>+	qpd-&gt;sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='add'>+			      SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |</div><div class='add'>+			      (3 &lt;&lt; SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);</div><div class='add'>+</div><div class='add'>+	qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='add'>+	qpd-&gt;sh_mem_ape1_base = 0;</div><div class='add'>+	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));</div><div class='add'>+</div><div class='add'>+	pr_debug("sh_mem_bases 0x%X\n", qpd-&gt;sh_mem_bases);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int update_qpd_v12(struct device_queue_manager *dqm,</div><div class='add'>+			 struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_sdma_vm_v12(struct device_queue_manager *dqm, struct queue *q,</div><div class='add'>+			    struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='add'>+	/* Not needed on SDMAv4 onwards any more */</div><div class='add'>+	q-&gt;properties.sdma_vm_addr = 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c<br/>index 54eb1bff903c..9fcc8c6e57b7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c</a></div><div class='hunk'>@@ -30,10 +30,18 @@ static int update_qpd_v9(struct device_queue_manager *dqm,</div><div class='ctx'> 			 struct qcm_process_device *qpd);</div><div class='ctx'> static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,</div><div class='ctx'> 			    struct qcm_process_device *qpd);</div><div class='add'>+static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties);</div><div class='ctx'> </div><div class='ctx'> void device_queue_manager_init_v9(</div><div class='ctx'> 	struct device_queue_manager_asic_ops *asic_ops)</div><div class='ctx'> {</div><div class='add'>+	asic_ops-&gt;set_cache_memory_policy = set_cache_memory_policy_v9;</div><div class='ctx'> 	asic_ops-&gt;update_qpd = update_qpd_v9;</div><div class='ctx'> 	asic_ops-&gt;init_sdma_vm = init_sdma_vm_v9;</div><div class='ctx'> 	asic_ops-&gt;mqd_manager_init = mqd_manager_init_v9;</div><div class='hunk'>@@ -48,10 +56,42 @@ static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)</div><div class='ctx'> 		private_base;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,</div><div class='add'>+				   struct qcm_process_device *qpd,</div><div class='add'>+				   enum cache_policy default_policy,</div><div class='add'>+				   enum cache_policy alternate_policy,</div><div class='add'>+				   void __user *alternate_aperture_base,</div><div class='add'>+				   uint64_t alternate_aperture_size,</div><div class='add'>+				   u32 misc_process_properties)</div><div class='add'>+{</div><div class='add'>+	qpd-&gt;sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='add'>+				SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;</div><div class='add'>+</div><div class='add'>+	if (dqm-&gt;dev-&gt;kfd-&gt;noretry)</div><div class='add'>+		qpd-&gt;sh_mem_config |= 1 &lt;&lt; SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;</div><div class='add'>+</div><div class='add'>+	if (KFD_GC_VERSION(dqm-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		KFD_GC_VERSION(dqm-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 4))</div><div class='add'>+		qpd-&gt;sh_mem_config |= (1 &lt;&lt; SH_MEM_CONFIG__F8_MODE__SHIFT);</div><div class='add'>+</div><div class='add'>+	if (KFD_GC_VERSION(dqm-&gt;dev-&gt;kfd) == IP_VERSION(9, 5, 0)) {</div><div class='add'>+		if (misc_process_properties &amp; KFD_PROC_FLAG_MFMA_HIGH_PRECISION)</div><div class='add'>+			qpd-&gt;sh_mem_config |= 1 &lt;&lt; SH_MEM_CONFIG__PRECISION_MODE__SHIFT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='add'>+	qpd-&gt;sh_mem_ape1_base = 0;</div><div class='add'>+	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));</div><div class='add'>+</div><div class='add'>+	pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd-&gt;sh_mem_bases,</div><div class='add'>+		 qpd-&gt;sh_mem_config);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int update_qpd_v9(struct device_queue_manager *dqm,</div><div class='ctx'> 			 struct qcm_process_device *qpd)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_process_device *pdd;</div><div class='add'>+	struct kfd_process_device *pdd = qpd_to_pdd(qpd);</div><div class='ctx'> </div><div class='ctx'> 	pdd = qpd_to_pdd(qpd);</div><div class='ctx'> </div><div class='hunk'>@@ -63,7 +103,8 @@ static int update_qpd_v9(struct device_queue_manager *dqm,</div><div class='ctx'> 		if (dqm-&gt;dev-&gt;kfd-&gt;noretry)</div><div class='ctx'> 			qpd-&gt;sh_mem_config |= 1 &lt;&lt; SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;</div><div class='ctx'> </div><div class='del'>-		if (KFD_GC_VERSION(dqm-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 3))</div><div class='add'>+		if (KFD_GC_VERSION(dqm-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		    KFD_GC_VERSION(dqm-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 4))</div><div class='ctx'> 			qpd-&gt;sh_mem_config |=</div><div class='ctx'> 				(1 &lt;&lt; SH_MEM_CONFIG__F8_MODE__SHIFT);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c<br/>index b291ee0fab94..dad83356e976 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c</a></div><div class='hunk'>@@ -27,12 +27,21 @@</div><div class='ctx'> #include "gca/gfx_8_0_sh_mask.h"</div><div class='ctx'> #include "oss/oss_3_0_sh_mask.h"</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to</div><div class='add'>+ * stay in user mode.</div><div class='add'>+ */</div><div class='add'>+#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL</div><div class='add'>+/* APE1 limit is inclusive and 64K aligned. */</div><div class='add'>+#define APE1_LIMIT_ALIGNMENT 0xFFFF</div><div class='add'>+</div><div class='ctx'> static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,</div><div class='ctx'> 				       struct qcm_process_device *qpd,</div><div class='ctx'> 				       enum cache_policy default_policy,</div><div class='ctx'> 				       enum cache_policy alternate_policy,</div><div class='ctx'> 				       void __user *alternate_aperture_base,</div><div class='del'>-				       uint64_t alternate_aperture_size);</div><div class='add'>+				       uint64_t alternate_aperture_size,</div><div class='add'>+				       u32 misc_process_properties);</div><div class='ctx'> static int update_qpd_vi(struct device_queue_manager *dqm,</div><div class='ctx'> 			 struct qcm_process_device *qpd);</div><div class='ctx'> static void init_sdma_vm(struct device_queue_manager *dqm,</div><div class='hunk'>@@ -81,10 +90,41 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,</div><div class='ctx'> 		enum cache_policy default_policy,</div><div class='ctx'> 		enum cache_policy alternate_policy,</div><div class='ctx'> 		void __user *alternate_aperture_base,</div><div class='del'>-		uint64_t alternate_aperture_size)</div><div class='add'>+		uint64_t alternate_aperture_size,</div><div class='add'>+		u32 misc_process_properties)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t default_mtype;</div><div class='ctx'> 	uint32_t ape1_mtype;</div><div class='add'>+	unsigned int temp;</div><div class='add'>+	bool retval = true;</div><div class='add'>+</div><div class='add'>+	if (alternate_aperture_size == 0) {</div><div class='add'>+		/* base &gt; limit disables APE1 */</div><div class='add'>+		qpd-&gt;sh_mem_ape1_base = 1;</div><div class='add'>+		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},</div><div class='add'>+		 *			SH_MEM_APE1_BASE[31:0], 0x0000 }</div><div class='add'>+		 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},</div><div class='add'>+		 *			SH_MEM_APE1_LIMIT[31:0], 0xFFFF }</div><div class='add'>+		 * Verify that the base and size parameters can be</div><div class='add'>+		 * represented in this format and convert them.</div><div class='add'>+		 * Additionally restrict APE1 to user-mode addresses.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		uint64_t base = (uintptr_t)alternate_aperture_base;</div><div class='add'>+		uint64_t limit = base + alternate_aperture_size - 1;</div><div class='add'>+</div><div class='add'>+		if (limit &lt;= base || (base &amp; APE1_FIXED_BITS_MASK) != 0 ||</div><div class='add'>+		   (limit &amp; APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {</div><div class='add'>+			retval = false;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		qpd-&gt;sh_mem_ape1_base = base &gt;&gt; 16;</div><div class='add'>+		qpd-&gt;sh_mem_ape1_limit = limit &gt;&gt; 16;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	default_mtype = (default_policy == cache_policy_coherent) ?</div><div class='ctx'> 			MTYPE_UC :</div><div class='hunk'>@@ -100,40 +140,21 @@ static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,</div><div class='ctx'> 			default_mtype &lt;&lt; SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |</div><div class='ctx'> 			ape1_mtype &lt;&lt; SH_MEM_CONFIG__APE1_MTYPE__SHIFT;</div><div class='ctx'> </div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int update_qpd_vi(struct device_queue_manager *dqm,</div><div class='del'>-			 struct qcm_process_device *qpd)</div><div class='del'>-{</div><div class='del'>-	struct kfd_process_device *pdd;</div><div class='del'>-	unsigned int temp;</div><div class='del'>-</div><div class='del'>-	pdd = qpd_to_pdd(qpd);</div><div class='del'>-</div><div class='del'>-	/* check if sh_mem_config register already configured */</div><div class='del'>-	if (qpd-&gt;sh_mem_config == 0) {</div><div class='del'>-		qpd-&gt;sh_mem_config =</div><div class='del'>-				SH_MEM_ALIGNMENT_MODE_UNALIGNED &lt;&lt;</div><div class='del'>-					SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |</div><div class='del'>-				MTYPE_UC &lt;&lt;</div><div class='del'>-					SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |</div><div class='del'>-				MTYPE_UC &lt;&lt;</div><div class='del'>-					SH_MEM_CONFIG__APE1_MTYPE__SHIFT;</div><div class='del'>-</div><div class='del'>-		qpd-&gt;sh_mem_ape1_limit = 0;</div><div class='del'>-		qpd-&gt;sh_mem_ape1_base = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* On dGPU we're always in GPUVM64 addressing mode with 64-bit</div><div class='ctx'> 	 * aperture addresses.</div><div class='ctx'> 	 */</div><div class='del'>-	temp = get_sh_mem_bases_nybble_64(pdd);</div><div class='add'>+	temp = get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd));</div><div class='ctx'> 	qpd-&gt;sh_mem_bases = compute_sh_mem_bases_64bit(temp);</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n",</div><div class='ctx'> 		temp, qpd-&gt;sh_mem_bases);</div><div class='add'>+out:</div><div class='add'>+	return retval;</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static int update_qpd_vi(struct device_queue_manager *dqm,</div><div class='add'>+			 struct qcm_process_device *qpd)</div><div class='add'>+{</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c<br/>index 9b33d9d2c9ad..5a190dd6be4e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_events.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_events.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_events.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_events.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #include &lt;linux/memory.h&gt;</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> #include "kfd_events.h"</div><div class='add'>+#include "kfd_device_queue_manager.h"</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -726,7 +727,7 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,</div><div class='ctx'> 	 * to process context, kfd_process could attempt to exit while we are</div><div class='ctx'> 	 * running so the lookup function increments the process ref count.</div><div class='ctx'> 	 */</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (!p)</div><div class='ctx'> 		return; /* Presumably process exited. */</div><div class='hunk'>@@ -1127,8 +1128,8 @@ static void lookup_events_by_type_and_signal(struct kfd_process *p,</div><div class='ctx'> </div><div class='ctx'> 	if (type == KFD_EVENT_TYPE_MEMORY) {</div><div class='ctx'> 		dev_warn(kfd_device,</div><div class='del'>-			"Sending SIGSEGV to process %d (pasid 0x%x)",</div><div class='del'>-				p-&gt;lead_thread-&gt;pid, p-&gt;pasid);</div><div class='add'>+			"Sending SIGSEGV to process pid %d",</div><div class='add'>+				p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		send_sig(SIGSEGV, p-&gt;lead_thread, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1136,13 +1137,13 @@ static void lookup_events_by_type_and_signal(struct kfd_process *p,</div><div class='ctx'> 	if (send_signal) {</div><div class='ctx'> 		if (send_sigterm) {</div><div class='ctx'> 			dev_warn(kfd_device,</div><div class='del'>-				"Sending SIGTERM to process %d (pasid 0x%x)",</div><div class='del'>-					p-&gt;lead_thread-&gt;pid, p-&gt;pasid);</div><div class='add'>+				"Sending SIGTERM to process pid %d",</div><div class='add'>+					p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 			send_sig(SIGTERM, p-&gt;lead_thread, 0);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			dev_err(kfd_device,</div><div class='del'>-				"Process %d (pasid 0x%x) got unhandled exception",</div><div class='del'>-				p-&gt;lead_thread-&gt;pid, p-&gt;pasid);</div><div class='add'>+				"Process pid %d got unhandled exception",</div><div class='add'>+				p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1156,7 +1157,7 @@ void kfd_signal_hw_exception_event(u32 pasid)</div><div class='ctx'> 	 * to process context, kfd_process could attempt to exit while we are</div><div class='ctx'> 	 * running so the lookup function increments the process ref count.</div><div class='ctx'> 	 */</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (!p)</div><div class='ctx'> 		return; /* Presumably process exited. */</div><div class='hunk'>@@ -1165,22 +1166,39 @@ void kfd_signal_hw_exception_event(u32 pasid)</div><div class='ctx'> 	kfd_unref_process(p);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid,</div><div class='add'>+void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process_device *pdd;</div><div class='add'>+	struct kfd_hsa_memory_exception_data exception_data;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	memset(&amp;exception_data, 0, sizeof(exception_data));</div><div class='add'>+	exception_data.va = gpu_va;</div><div class='add'>+	exception_data.failure.NotPresent = 1;</div><div class='add'>+</div><div class='add'>+	// Send VM seg fault to all kfd process device</div><div class='add'>+	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='add'>+		pdd = p-&gt;pdds[i];</div><div class='add'>+		exception_data.gpu_id = pdd-&gt;user_gpu_id;</div><div class='add'>+		kfd_evict_process_device(pdd);</div><div class='add'>+		kfd_signal_vm_fault_event(pdd, NULL, &amp;exception_data);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void kfd_signal_vm_fault_event(struct kfd_process_device *pdd,</div><div class='ctx'> 				struct kfd_vm_fault_info *info,</div><div class='ctx'> 				struct kfd_hsa_memory_exception_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_event *ev;</div><div class='ctx'> 	uint32_t id;</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	struct kfd_process *p = pdd-&gt;process;</div><div class='ctx'> 	struct kfd_hsa_memory_exception_data memory_exception_data;</div><div class='ctx'> 	int user_gpu_id;</div><div class='ctx'> </div><div class='del'>-	if (!p)</div><div class='del'>-		return; /* Presumably process exited. */</div><div class='del'>-</div><div class='del'>-	user_gpu_id = kfd_process_get_user_gpu_id(p, dev-&gt;id);</div><div class='add'>+	user_gpu_id = kfd_process_get_user_gpu_id(p, pdd-&gt;dev-&gt;id);</div><div class='ctx'> 	if (unlikely(user_gpu_id == -EINVAL)) {</div><div class='del'>-		WARN_ONCE(1, "Could not get user_gpu_id from dev-&gt;id:%x\n", dev-&gt;id);</div><div class='add'>+		WARN_ONCE(1, "Could not get user_gpu_id from dev-&gt;id:%x\n",</div><div class='add'>+			  pdd-&gt;dev-&gt;id);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1217,7 +1235,6 @@ void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 	rcu_read_unlock();</div><div class='del'>-	kfd_unref_process(p);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_signal_reset_event(struct kfd_node *dev)</div><div class='hunk'>@@ -1244,12 +1261,41 @@ void kfd_signal_reset_event(struct kfd_node *dev)</div><div class='ctx'> 	idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='ctx'> 		int user_gpu_id = kfd_process_get_user_gpu_id(p, dev-&gt;id);</div><div class='add'>+		struct kfd_process_device *pdd = kfd_get_process_device_data(dev, p);</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(user_gpu_id == -EINVAL)) {</div><div class='ctx'> 			WARN_ONCE(1, "Could not get user_gpu_id from dev-&gt;id:%x\n", dev-&gt;id);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (unlikely(!pdd)) {</div><div class='add'>+			WARN_ONCE(1, "Could not get device data from process pid:%d\n",</div><div class='add'>+				  p-&gt;lead_thread-&gt;pid);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dev-&gt;dqm-&gt;detect_hang_count &amp;&amp; !pdd-&gt;has_reset_queue)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (dev-&gt;dqm-&gt;detect_hang_count) {</div><div class='add'>+			struct amdgpu_task_info *ti;</div><div class='add'>+			struct amdgpu_fpriv *drv_priv;</div><div class='add'>+</div><div class='add'>+			if (unlikely(amdgpu_file_to_fpriv(pdd-&gt;drm_file, &amp;drv_priv))) {</div><div class='add'>+				WARN_ONCE(1, "Could not get vm for device %x from pid:%d\n",</div><div class='add'>+					  dev-&gt;id, p-&gt;lead_thread-&gt;pid);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			ti = amdgpu_vm_get_task_info_vm(&amp;drv_priv-&gt;vm);</div><div class='add'>+			if (ti) {</div><div class='add'>+				dev_err(dev-&gt;adev-&gt;dev,</div><div class='add'>+					"Queues reset on process %s tid %d thread %s pid %d\n",</div><div class='add'>+					ti-&gt;process_name, ti-&gt;tgid, ti-&gt;task.comm, ti-&gt;task.pid);</div><div class='add'>+				amdgpu_vm_put_task_info(ti);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		rcu_read_lock();</div><div class='ctx'> </div><div class='ctx'> 		id = KFD_FIRST_NONSIGNAL_EVENT_ID;</div><div class='hunk'>@@ -1278,7 +1324,7 @@ void kfd_signal_reset_event(struct kfd_node *dev)</div><div class='ctx'> </div><div class='ctx'> void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='ctx'> 	struct kfd_hsa_memory_exception_data memory_exception_data;</div><div class='ctx'> 	struct kfd_hsa_hw_exception_data hw_exception_data;</div><div class='ctx'> 	struct kfd_event *ev;</div><div class='hunk'>@@ -1293,6 +1339,7 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid)</div><div class='ctx'> 	user_gpu_id = kfd_process_get_user_gpu_id(p, dev-&gt;id);</div><div class='ctx'> 	if (unlikely(user_gpu_id == -EINVAL)) {</div><div class='ctx'> 		WARN_ONCE(1, "Could not get user_gpu_id from dev-&gt;id:%x\n", dev-&gt;id);</div><div class='add'>+		kfd_unref_process(p);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c<br/>index 4a64307bc438..1d170dc50df3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c</a></div><div class='hunk'>@@ -23,7 +23,6 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='del'>-#include &lt;linux/export.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/fs.h&gt;</div><div class='ctx'> #include &lt;linux/sched.h&gt;</div><div class='hunk'>@@ -380,7 +379,8 @@ int kfd_init_apertures(struct kfd_process *process)</div><div class='ctx'> </div><div class='ctx'> 		pdd = kfd_create_process_device_data(dev, process);</div><div class='ctx'> 		if (!pdd) {</div><div class='del'>-			pr_err("Failed to create process device data\n");</div><div class='add'>+			dev_err(dev-&gt;adev-&gt;dev,</div><div class='add'>+				"Failed to create process device data\n");</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		}</div><div class='ctx'> 		/*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c<br/>index 9a06c6fb6605..3e1ad8974797 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c</a></div><div class='hunk'>@@ -129,60 +129,6 @@ enum SQ_INTERRUPT_ERROR_TYPE {</div><div class='ctx'> 				KFD_DEBUG_CP_BAD_OP_ECODE_MASK)		\</div><div class='ctx'> 				&gt;&gt; KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT)</div><div class='ctx'> </div><div class='del'>-static void event_interrupt_poison_consumption(struct kfd_node *dev,</div><div class='del'>-				uint16_t pasid, uint16_t client_id)</div><div class='del'>-{</div><div class='del'>-	enum amdgpu_ras_block block = 0;</div><div class='del'>-	int old_poison, ret = -EINVAL;</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='del'>-</div><div class='del'>-	if (!p)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* all queues of a process will be unmapped in one time */</div><div class='del'>-	old_poison = atomic_cmpxchg(&amp;p-&gt;poison, 0, 1);</div><div class='del'>-	kfd_unref_process(p);</div><div class='del'>-	if (old_poison)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (client_id) {</div><div class='del'>-	case SOC15_IH_CLIENTID_SE0SH:</div><div class='del'>-	case SOC15_IH_CLIENTID_SE1SH:</div><div class='del'>-	case SOC15_IH_CLIENTID_SE2SH:</div><div class='del'>-	case SOC15_IH_CLIENTID_SE3SH:</div><div class='del'>-	case SOC15_IH_CLIENTID_UTCL2:</div><div class='del'>-		ret = kfd_dqm_evict_pasid(dev-&gt;dqm, pasid);</div><div class='del'>-		block = AMDGPU_RAS_BLOCK__GFX;</div><div class='del'>-		break;</div><div class='del'>-	case SOC15_IH_CLIENTID_SDMA0:</div><div class='del'>-	case SOC15_IH_CLIENTID_SDMA1:</div><div class='del'>-	case SOC15_IH_CLIENTID_SDMA2:</div><div class='del'>-	case SOC15_IH_CLIENTID_SDMA3:</div><div class='del'>-	case SOC15_IH_CLIENTID_SDMA4:</div><div class='del'>-		block = AMDGPU_RAS_BLOCK__SDMA;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kfd_signal_poison_consumed_event(dev, pasid);</div><div class='del'>-</div><div class='del'>-	/* resetting queue passes, do page retirement without gpu reset</div><div class='del'>-	 * resetting queue fails, fallback to gpu reset solution</div><div class='del'>-	 */</div><div class='del'>-	if (!ret) {</div><div class='del'>-		dev_warn(dev-&gt;adev-&gt;dev,</div><div class='del'>-			"RAS poison consumption, unmap queue flow succeeded: client id %d\n",</div><div class='del'>-			client_id);</div><div class='del'>-		amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, false);</div><div class='del'>-	} else {</div><div class='del'>-		dev_warn(dev-&gt;adev-&gt;dev,</div><div class='del'>-			"RAS poison consumption, fall back to gpu reset flow: client id %d\n",</div><div class='del'>-			client_id);</div><div class='del'>-		amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, true);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool event_interrupt_isr_v10(struct kfd_node *dev,</div><div class='ctx'> 					const uint32_t *ih_ring_entry,</div><div class='ctx'> 					uint32_t *patched_ihre,</div><div class='hunk'>@@ -222,14 +168,14 @@ static bool event_interrupt_isr_v10(struct kfd_node *dev,</div><div class='ctx'> 	    client_id != SOC15_IH_CLIENTID_SE3SH)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",</div><div class='del'>-		 client_id, source_id, vmid, pasid);</div><div class='del'>-	pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",</div><div class='del'>-		 data[0], data[1], data[2], data[3],</div><div class='del'>-		 data[4], data[5], data[6], data[7]);</div><div class='add'>+	dev_dbg(dev-&gt;adev-&gt;dev,</div><div class='add'>+		"client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",</div><div class='add'>+		client_id, source_id, vmid, pasid);</div><div class='add'>+	dev_dbg(dev-&gt;adev-&gt;dev, "%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",</div><div class='add'>+		data[0], data[1], data[2], data[3], data[4], data[5], data[6],</div><div class='add'>+		data[7]);</div><div class='ctx'> </div><div class='del'>-	/* If there is no valid PASID, it's likely a bug */</div><div class='del'>-	if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))</div><div class='add'>+	if (pasid == 0)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Interrupt types we care about: various signals and faults.</div><div class='hunk'>@@ -271,37 +217,66 @@ static void event_interrupt_wq_v10(struct kfd_node *dev,</div><div class='ctx'> 						SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING);</div><div class='ctx'> 			switch (encoding) {</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_AUTO:</div><div class='del'>-				pr_debug_ratelimited(</div><div class='add'>+				dev_dbg_ratelimited(</div><div class='add'>+					dev-&gt;adev-&gt;dev,</div><div class='ctx'> 					"sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf0_full %d, ttrac_buf1_full %d, ttrace_utc_err %d\n",</div><div class='del'>-					REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_AUTO_CTXID1,</div><div class='del'>-							SE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='del'>-							THREAD_TRACE),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='del'>-							WLT),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='del'>-							THREAD_TRACE_BUF0_FULL),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='del'>-							THREAD_TRACE_BUF1_FULL),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='del'>-							THREAD_TRACE_UTC_ERROR));</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id1,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID1,</div><div class='add'>+						SE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+						THREAD_TRACE),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+						WLT),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+						THREAD_TRACE_BUF0_FULL),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+						THREAD_TRACE_BUF1_FULL),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+						THREAD_TRACE_UTC_ERROR));</div><div class='ctx'> 				break;</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_INST:</div><div class='del'>-				pr_debug_ratelimited("sq_intr: inst, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",</div><div class='del'>-					REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='del'>-							SE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							DATA),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							SA_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							PRIV),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							WAVE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							SIMD_ID),</div><div class='del'>-					REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='del'>-							WGP_ID));</div><div class='add'>+				dev_dbg_ratelimited(</div><div class='add'>+					dev-&gt;adev-&gt;dev,</div><div class='add'>+					"sq_intr: inst, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id1,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='add'>+						SE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						DATA),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						SA_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						PRIV),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						WAVE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						SIMD_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id1,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='add'>+						WGP_ID));</div><div class='ctx'> 				if (context_id0 &amp; SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK) {</div><div class='ctx'> 					if (kfd_set_dbg_ev_from_interrupt(dev, pasid,</div><div class='ctx'> 							KFD_DEBUG_DOORBELL_ID(context_id0),</div><div class='hunk'>@@ -313,33 +288,45 @@ static void event_interrupt_wq_v10(struct kfd_node *dev,</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_ERROR:</div><div class='ctx'> 				sq_intr_err_type = REG_GET_FIELD(context_id0, KFD_CTXID0,</div><div class='ctx'> 								ERR_TYPE);</div><div class='del'>-				pr_warn_ratelimited("sq_intr: error, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d, err_type %d\n",</div><div class='del'>-					REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='del'>-							SE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							DATA),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							SA_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							PRIV),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							WAVE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='del'>-							SIMD_ID),</div><div class='del'>-					REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='del'>-							WGP_ID),</div><div class='add'>+				dev_warn_ratelimited(</div><div class='add'>+					dev-&gt;adev-&gt;dev,</div><div class='add'>+					"sq_intr: error, se %d, data 0x%x, sa %d, priv %d, wave_id %d, simd_id %d, wgp_id %d, err_type %d\n",</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id1,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='add'>+						SE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						DATA),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						SA_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						PRIV),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						WAVE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+						SIMD_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id1,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='add'>+						WGP_ID),</div><div class='ctx'> 					sq_intr_err_type);</div><div class='del'>-				if (sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &amp;&amp;</div><div class='del'>-					sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {</div><div class='del'>-					event_interrupt_poison_consumption(dev, pasid, source_id);</div><div class='del'>-					return;</div><div class='del'>-				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 			kfd_signal_event_interrupt(pasid, context_id0 &amp; 0x7fffff, 23);</div><div class='del'>-		} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) {</div><div class='add'>+		} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &amp;&amp;</div><div class='add'>+			   KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) {</div><div class='ctx'> 			kfd_set_dbg_ev_from_interrupt(dev, pasid,</div><div class='ctx'> 				KFD_DEBUG_DOORBELL_ID(context_id0),</div><div class='ctx'> 				KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),</div><div class='hunk'>@@ -358,9 +345,6 @@ static void event_interrupt_wq_v10(struct kfd_node *dev,</div><div class='ctx'> 		   client_id == SOC15_IH_CLIENTID_SDMA7) {</div><div class='ctx'> 		if (source_id == SOC15_INTSRC_SDMA_TRAP) {</div><div class='ctx'> 			kfd_signal_event_interrupt(pasid, context_id0 &amp; 0xfffffff, 28);</div><div class='del'>-		} else if (source_id == SOC15_INTSRC_SDMA_ECC) {</div><div class='del'>-			event_interrupt_poison_consumption(dev, pasid, source_id);</div><div class='del'>-			return;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (client_id == SOC15_IH_CLIENTID_VMC ||</div><div class='ctx'> 		   client_id == SOC15_IH_CLIENTID_VMC1 ||</div><div class='hunk'>@@ -369,12 +353,6 @@ static void event_interrupt_wq_v10(struct kfd_node *dev,</div><div class='ctx'> 		uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);</div><div class='ctx'> 		struct kfd_hsa_memory_exception_data exception_data;</div><div class='ctx'> </div><div class='del'>-		if (client_id == SOC15_IH_CLIENTID_UTCL2 &amp;&amp;</div><div class='del'>-				amdgpu_amdkfd_ras_query_utcl2_poison_status(dev-&gt;adev)) {</div><div class='del'>-			event_interrupt_poison_consumption(dev, pasid, client_id);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 		info.vmid = vmid;</div><div class='ctx'> 		info.mc_id = client_id;</div><div class='ctx'> 		info.page_addr = ih_ring_entry[4] |</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c<br/>index 7e2859736a55..2788a52714d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c</a></div><div class='hunk'>@@ -148,44 +148,69 @@ enum SQ_INTERRUPT_ERROR_TYPE {</div><div class='ctx'> #define KFD_CTXID0_DOORBELL_ID(ctxid0)		((ctxid0) &amp; \</div><div class='ctx'> 				KFD_CTXID0_DOORBELL_ID_MASK)</div><div class='ctx'> </div><div class='del'>-static void print_sq_intr_info_auto(uint32_t context_id0, uint32_t context_id1)</div><div class='add'>+static void print_sq_intr_info_auto(struct kfd_node *dev, uint32_t context_id0,</div><div class='add'>+				    uint32_t context_id1)</div><div class='ctx'> {</div><div class='del'>-	pr_debug_ratelimited(</div><div class='add'>+	dev_dbg_ratelimited(</div><div class='add'>+		dev-&gt;adev-&gt;dev,</div><div class='ctx'> 		"sq_intr: auto, ttrace %d, wlt %d, ttrace_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n",</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      THREAD_TRACE),</div><div class='ctx'> 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_BUF_FULL),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, REG_TIMESTAMP),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, CMD_TIMESTAMP),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_CMD_OVERFLOW),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_REG_OVERFLOW),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, IMMED_OVERFLOW),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_UTC_ERROR));</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      THREAD_TRACE_BUF_FULL),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      REG_TIMESTAMP),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      CMD_TIMESTAMP),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      HOST_CMD_OVERFLOW),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      HOST_REG_OVERFLOW),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      IMMED_OVERFLOW),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0,</div><div class='add'>+			      THREAD_TRACE_UTC_ERROR));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void print_sq_intr_info_inst(uint32_t context_id0, uint32_t context_id1)</div><div class='add'>+static void print_sq_intr_info_inst(struct kfd_node *dev, uint32_t context_id0,</div><div class='add'>+				    uint32_t context_id1)</div><div class='ctx'> {</div><div class='del'>-	pr_debug_ratelimited(</div><div class='add'>+	dev_dbg_ratelimited(</div><div class='add'>+		dev-&gt;adev-&gt;dev,</div><div class='ctx'> 		"sq_intr: inst, data 0x%08x, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",</div><div class='ctx'> 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, SH_ID),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+			      SH_ID),</div><div class='ctx'> 		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, WAVE_ID),</div><div class='del'>-		REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, SIMD_ID),</div><div class='del'>-		REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, WGP_ID));</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0,</div><div class='add'>+			      WAVE_ID),</div><div class='add'>+		REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='add'>+			      SIMD_ID),</div><div class='add'>+		REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1,</div><div class='add'>+			      WGP_ID));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void print_sq_intr_info_error(uint32_t context_id0, uint32_t context_id1)</div><div class='add'>+static void print_sq_intr_info_error(struct kfd_node *dev, uint32_t context_id0,</div><div class='add'>+				     uint32_t context_id1)</div><div class='ctx'> {</div><div class='del'>-	pr_warn_ratelimited(</div><div class='add'>+	dev_warn_ratelimited(</div><div class='add'>+		dev-&gt;adev-&gt;dev,</div><div class='ctx'> 		"sq_intr: error, detail 0x%08x, type %d, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n",</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, DETAIL),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, SH_ID),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, PRIV),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, WAVE_ID),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, SIMD_ID),</div><div class='del'>-		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, WGP_ID));</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,</div><div class='add'>+			      DETAIL),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,</div><div class='add'>+			      TYPE),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,</div><div class='add'>+			      SH_ID),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,</div><div class='add'>+			      PRIV),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0,</div><div class='add'>+			      WAVE_ID),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1,</div><div class='add'>+			      SIMD_ID),</div><div class='add'>+		REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1,</div><div class='add'>+			      WGP_ID));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void event_interrupt_poison_consumption_v11(struct kfd_node *dev,</div><div class='hunk'>@@ -193,7 +218,8 @@ static void event_interrupt_poison_consumption_v11(struct kfd_node *dev,</div><div class='ctx'> {</div><div class='ctx'> 	enum amdgpu_ras_block block = 0;</div><div class='ctx'> 	int ret = -EINVAL;</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	uint32_t reset = 0;</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (!p)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -212,10 +238,13 @@ static void event_interrupt_poison_consumption_v11(struct kfd_node *dev,</div><div class='ctx'> 		if (dev-&gt;dqm-&gt;ops.reset_queues)</div><div class='ctx'> 			ret = dev-&gt;dqm-&gt;ops.reset_queues(dev-&gt;dqm, pasid);</div><div class='ctx'> 		block = AMDGPU_RAS_BLOCK__GFX;</div><div class='add'>+		if (ret)</div><div class='add'>+			reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SOC21_INTSRC_SDMA_ECC:</div><div class='ctx'> 	default:</div><div class='ctx'> 		block = AMDGPU_RAS_BLOCK__GFX;</div><div class='add'>+		reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -223,10 +252,7 @@ static void event_interrupt_poison_consumption_v11(struct kfd_node *dev,</div><div class='ctx'> </div><div class='ctx'> 	/* resetting queue passes, do page retirement without gpu reset</div><div class='ctx'> 	   resetting queue fails, fallback to gpu reset solution */</div><div class='del'>-	if (!ret)</div><div class='del'>-		amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, false);</div><div class='del'>-	else</div><div class='del'>-		amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, true);</div><div class='add'>+	amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, reset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool event_interrupt_isr_v11(struct kfd_node *dev,</div><div class='hunk'>@@ -254,14 +280,14 @@ static bool event_interrupt_isr_v11(struct kfd_node *dev,</div><div class='ctx'> 	    (context_id0 &amp; AMDGPU_FENCE_MES_QUEUE_FLAG))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",</div><div class='del'>-		 client_id, source_id, vmid, pasid);</div><div class='del'>-	pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",</div><div class='del'>-		 data[0], data[1], data[2], data[3],</div><div class='del'>-		 data[4], data[5], data[6], data[7]);</div><div class='add'>+	dev_dbg(dev-&gt;adev-&gt;dev,</div><div class='add'>+		"client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",</div><div class='add'>+		client_id, source_id, vmid, pasid);</div><div class='add'>+	dev_dbg(dev-&gt;adev-&gt;dev, "%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",</div><div class='add'>+		data[0], data[1], data[2], data[3], data[4], data[5], data[6],</div><div class='add'>+		data[7]);</div><div class='ctx'> </div><div class='del'>-	/* If there is no valid PASID, it's likely a bug */</div><div class='del'>-	if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))</div><div class='add'>+	if (pasid == 0)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	/* Interrupt types we care about: various signals and faults.</div><div class='hunk'>@@ -328,11 +354,15 @@ static void event_interrupt_wq_v11(struct kfd_node *dev,</div><div class='ctx'> 		/* CP */</div><div class='ctx'> 		if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)</div><div class='ctx'> 			kfd_signal_event_interrupt(pasid, context_id0, 32);</div><div class='del'>-		else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)</div><div class='del'>-			kfd_set_dbg_ev_from_interrupt(dev, pasid,</div><div class='del'>-				KFD_CTXID0_DOORBELL_ID(context_id0),</div><div class='add'>+		else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &amp;&amp;</div><div class='add'>+			 KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) {</div><div class='add'>+			u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0);</div><div class='add'>+</div><div class='add'>+			kfd_set_dbg_ev_from_interrupt(dev, pasid, doorbell_id,</div><div class='ctx'> 				KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)),</div><div class='ctx'> 				NULL, 0);</div><div class='add'>+			kfd_dqm_suspend_bad_queue_mes(dev, pasid, doorbell_id);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		/* SDMA */</div><div class='ctx'> 		else if (source_id == SOC21_INTSRC_SDMA_TRAP)</div><div class='hunk'>@@ -348,10 +378,10 @@ static void event_interrupt_wq_v11(struct kfd_node *dev,</div><div class='ctx'> 					SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING);</div><div class='ctx'> 			switch (sq_int_enc) {</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_AUTO:</div><div class='del'>-				print_sq_intr_info_auto(context_id0, context_id1);</div><div class='add'>+				print_sq_intr_info_auto(dev, context_id0, context_id1);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_INST:</div><div class='del'>-				print_sq_intr_info_inst(context_id0, context_id1);</div><div class='add'>+				print_sq_intr_info_inst(dev, context_id0, context_id1);</div><div class='ctx'> 				sq_int_priv = REG_GET_FIELD(context_id0,</div><div class='ctx'> 						SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV);</div><div class='ctx'> 				if (sq_int_priv &amp;&amp; (kfd_set_dbg_ev_from_interrupt(dev, pasid,</div><div class='hunk'>@@ -361,7 +391,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev,</div><div class='ctx'> 					return;</div><div class='ctx'> 				break;</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_ERROR:</div><div class='del'>-				print_sq_intr_info_error(context_id0, context_id1);</div><div class='add'>+				print_sq_intr_info_error(dev, context_id0, context_id1);</div><div class='ctx'> 				sq_int_errtype = REG_GET_FIELD(context_id0,</div><div class='ctx'> 						SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE);</div><div class='ctx'> 				if (sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &amp;&amp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c<br/>index 91dd5e045b51..d76fb61869c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c</a></div><div class='hunk'>@@ -27,6 +27,8 @@</div><div class='ctx'> #include "soc15_int.h"</div><div class='ctx'> #include "kfd_device_queue_manager.h"</div><div class='ctx'> #include "kfd_smi_events.h"</div><div class='add'>+#include "amdgpu_ras.h"</div><div class='add'>+#include "amdgpu_ras_mgr.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * GFX9 SQ Interrupts</div><div class='hunk'>@@ -144,8 +146,11 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev,</div><div class='ctx'> 				uint16_t pasid, uint16_t client_id)</div><div class='ctx'> {</div><div class='ctx'> 	enum amdgpu_ras_block block = 0;</div><div class='del'>-	int old_poison, ret = -EINVAL;</div><div class='del'>-	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	uint32_t reset = 0;</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='add'>+	enum ras_event_type type = RAS_EVENT_TYPE_POISON_CONSUMPTION;</div><div class='add'>+	u64 event_id;</div><div class='add'>+	int old_poison, ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!p)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -162,8 +167,30 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev,</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SE2SH:</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SE3SH:</div><div class='ctx'> 	case SOC15_IH_CLIENTID_UTCL2:</div><div class='del'>-		ret = kfd_dqm_evict_pasid(dev-&gt;dqm, pasid);</div><div class='ctx'> 		block = AMDGPU_RAS_BLOCK__GFX;</div><div class='add'>+		if (amdgpu_ip_version(dev-&gt;adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {</div><div class='add'>+			/* driver mode-2 for gfx poison is only supported by</div><div class='add'>+			 * pmfw 0x00557300 and onwards */</div><div class='add'>+			if (dev-&gt;adev-&gt;pm.fw_version &lt; 0x00557300)</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='add'>+			else</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		} else if (amdgpu_ip_version(dev-&gt;adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) {</div><div class='add'>+			/* driver mode-2 for gfx poison is only supported by</div><div class='add'>+			 * pmfw 0x05550C00 and onwards */</div><div class='add'>+			if (dev-&gt;adev-&gt;pm.fw_version &lt; 0x05550C00)</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='add'>+			else</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		} else {</div><div class='add'>+			reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		}</div><div class='add'>+		amdgpu_ras_set_err_poison(dev-&gt;adev, AMDGPU_RAS_BLOCK__GFX);</div><div class='add'>+		break;</div><div class='add'>+	case SOC15_IH_CLIENTID_VMC:</div><div class='add'>+	case SOC15_IH_CLIENTID_VMC1:</div><div class='add'>+		block = AMDGPU_RAS_BLOCK__MMHUB;</div><div class='add'>+		reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA0:</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA1:</div><div class='hunk'>@@ -171,27 +198,48 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev,</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA3:</div><div class='ctx'> 	case SOC15_IH_CLIENTID_SDMA4:</div><div class='ctx'> 		block = AMDGPU_RAS_BLOCK__SDMA;</div><div class='add'>+		if (amdgpu_ip_version(dev-&gt;adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) {</div><div class='add'>+			/* driver mode-2 for gfx poison is only supported by</div><div class='add'>+			 * pmfw 0x00557300 and onwards */</div><div class='add'>+			if (dev-&gt;adev-&gt;pm.fw_version &lt; 0x00557300)</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='add'>+			else</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		} else if (amdgpu_ip_version(dev-&gt;adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {</div><div class='add'>+			/* driver mode-2 for gfx poison is only supported by</div><div class='add'>+			 * pmfw 0x05550C00 and onwards */</div><div class='add'>+			if (dev-&gt;adev-&gt;pm.fw_version &lt; 0x05550C00)</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;</div><div class='add'>+			else</div><div class='add'>+				reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		} else {</div><div class='add'>+			reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;</div><div class='add'>+		}</div><div class='add'>+		amdgpu_ras_set_err_poison(dev-&gt;adev, AMDGPU_RAS_BLOCK__SDMA);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		break;</div><div class='add'>+		dev_warn(dev-&gt;adev-&gt;dev,</div><div class='add'>+			 "client %d does not support poison consumption\n", client_id);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = amdgpu_ras_mark_ras_event(dev-&gt;adev, type);</div><div class='add'>+	if (ret)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	kfd_signal_poison_consumed_event(dev, pasid);</div><div class='ctx'> </div><div class='del'>-	/* resetting queue passes, do page retirement without gpu reset</div><div class='del'>-	 * resetting queue fails, fallback to gpu reset solution</div><div class='del'>-	 */</div><div class='del'>-	if (!ret) {</div><div class='del'>-		dev_warn(dev-&gt;adev-&gt;dev,</div><div class='del'>-			"RAS poison consumption, unmap queue flow succeeded: client id %d\n",</div><div class='del'>-			client_id);</div><div class='del'>-		amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, false);</div><div class='del'>-	} else {</div><div class='del'>-		dev_warn(dev-&gt;adev-&gt;dev,</div><div class='del'>-			"RAS poison consumption, fall back to gpu reset flow: client id %d\n",</div><div class='del'>-			client_id);</div><div class='del'>-		amdgpu_amdkfd_ras_poison_consumption_handler(dev-&gt;adev, block, true);</div><div class='del'>-	}</div><div class='add'>+	if (amdgpu_uniras_enabled(dev-&gt;adev))</div><div class='add'>+		event_id = amdgpu_ras_mgr_gen_ras_event_seqno(dev-&gt;adev,</div><div class='add'>+					RAS_SEQNO_TYPE_POISON_CONSUMPTION);</div><div class='add'>+	else</div><div class='add'>+		event_id = amdgpu_ras_acquire_event_id(dev-&gt;adev, type);</div><div class='add'>+</div><div class='add'>+	RAS_EVENT_LOG(dev-&gt;adev, event_id,</div><div class='add'>+		      "poison is consumed by client %d, kick off gpu reset flow\n", client_id);</div><div class='add'>+</div><div class='add'>+	amdgpu_amdkfd_ras_pasid_poison_consumption_handler(dev-&gt;adev,</div><div class='add'>+		block, pasid, NULL, NULL, reset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool context_id_expected(struct kfd_dev *dev)</div><div class='hunk'>@@ -271,11 +319,12 @@ static bool event_interrupt_isr_v9(struct kfd_node *dev,</div><div class='ctx'> 					&amp; ~pasid_mask) | pasid);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",</div><div class='del'>-		 client_id, source_id, vmid, pasid);</div><div class='del'>-	pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",</div><div class='del'>-		 data[0], data[1], data[2], data[3],</div><div class='del'>-		 data[4], data[5], data[6], data[7]);</div><div class='add'>+	dev_dbg(dev-&gt;adev-&gt;dev,</div><div class='add'>+		"client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",</div><div class='add'>+		client_id, source_id, vmid, pasid);</div><div class='add'>+	dev_dbg(dev-&gt;adev-&gt;dev, "%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n",</div><div class='add'>+		data[0], data[1], data[2], data[3], data[4], data[5], data[6],</div><div class='add'>+		data[7]);</div><div class='ctx'> </div><div class='ctx'> 	/* If there is no valid PASID, it's likely a bug */</div><div class='ctx'> 	if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt"))</div><div class='hunk'>@@ -336,28 +385,82 @@ static void event_interrupt_wq_v9(struct kfd_node *dev,</div><div class='ctx'> 			encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING);</div><div class='ctx'> 			switch (encoding) {</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_AUTO:</div><div class='del'>-				pr_debug_ratelimited(</div><div class='add'>+				dev_dbg_ratelimited(</div><div class='add'>+					dev-&gt;adev-&gt;dev,</div><div class='ctx'> 					"sq_intr: auto, se %d, ttrace %d, wlt %d, ttrac_buf_full %d, reg_tms %d, cmd_tms %d, host_cmd_ovf %d, host_reg_ovf %d, immed_ovf %d, ttrace_utc_err %d\n",</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_UTC_ERROR));</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						SE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						THREAD_TRACE),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						WLT),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						THREAD_TRACE_BUF_FULL),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						REG_TIMESTAMP),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						CMD_TIMESTAMP),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						HOST_CMD_OVERFLOW),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						HOST_REG_OVERFLOW),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						IMMED_OVERFLOW),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_AUTO_CTXID,</div><div class='add'>+						THREAD_TRACE_UTC_ERROR));</div><div class='ctx'> 				break;</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_INST:</div><div class='del'>-				pr_debug_ratelimited("sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n",</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID),</div><div class='add'>+				dev_dbg_ratelimited(</div><div class='add'>+					dev-&gt;adev-&gt;dev,</div><div class='add'>+					"sq_intr: inst, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, intr_data 0x%x\n",</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						SE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						DATA),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						SH_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						PRIV),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						WAVE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						SIMD_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						CU_ID),</div><div class='ctx'> 					sq_int_data);</div><div class='ctx'> 				if (context_id0 &amp; SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK) {</div><div class='ctx'> 					if (kfd_set_dbg_ev_from_interrupt(dev, pasid,</div><div class='hunk'>@@ -369,14 +472,37 @@ static void event_interrupt_wq_v9(struct kfd_node *dev,</div><div class='ctx'> 				break;</div><div class='ctx'> 			case SQ_INTERRUPT_WORD_ENCODING_ERROR:</div><div class='ctx'> 				sq_intr_err = REG_GET_FIELD(sq_int_data, KFD_SQ_INT_DATA, ERR_TYPE);</div><div class='del'>-				pr_warn_ratelimited("sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n",</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, DATA),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SH_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, PRIV),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, WAVE_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, SIMD_ID),</div><div class='del'>-					REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, CU_ID),</div><div class='add'>+				dev_warn_ratelimited(</div><div class='add'>+					dev-&gt;adev-&gt;dev,</div><div class='add'>+					"sq_intr: error, se %d, data 0x%x, sh %d, priv %d, wave_id %d, simd_id %d, cu_id %d, err_type %d\n",</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						SE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						DATA),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						SH_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						PRIV),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						WAVE_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						SIMD_ID),</div><div class='add'>+					REG_GET_FIELD(</div><div class='add'>+						context_id0,</div><div class='add'>+						SQ_INTERRUPT_WORD_WAVE_CTXID,</div><div class='add'>+						CU_ID),</div><div class='ctx'> 					sq_intr_err);</div><div class='ctx'> 				if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &amp;&amp;</div><div class='ctx'> 					sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {</div><div class='hunk'>@@ -388,7 +514,8 @@ static void event_interrupt_wq_v9(struct kfd_node *dev,</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 			kfd_signal_event_interrupt(pasid, sq_int_data, 24);</div><div class='del'>-		} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) {</div><div class='add'>+		} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE &amp;&amp;</div><div class='add'>+			   KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) {</div><div class='ctx'> 			kfd_set_dbg_ev_from_interrupt(dev, pasid,</div><div class='ctx'> 				KFD_DEBUG_DOORBELL_ID(context_id0),</div><div class='ctx'> 				KFD_EC_MASK(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0)),</div><div class='hunk'>@@ -415,8 +542,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev,</div><div class='ctx'> 		uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);</div><div class='ctx'> 		struct kfd_hsa_memory_exception_data exception_data;</div><div class='ctx'> </div><div class='del'>-		if (client_id == SOC15_IH_CLIENTID_UTCL2 &amp;&amp;</div><div class='del'>-		    amdgpu_amdkfd_ras_query_utcl2_poison_status(dev-&gt;adev)) {</div><div class='add'>+		if (source_id == SOC15_INTSRC_VMC_UTCL2_POISON) {</div><div class='ctx'> 			event_interrupt_poison_consumption_v9(dev, pasid, client_id);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c<br/>index dd3c43c1ad70..783c2f5a04e4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c</a></div><div class='hunk'>@@ -46,7 +46,7 @@</div><div class='ctx'> #include &lt;linux/kfifo.h&gt;</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> </div><div class='del'>-#define KFD_IH_NUM_ENTRIES 8192</div><div class='add'>+#define KFD_IH_NUM_ENTRIES 16384</div><div class='ctx'> </div><div class='ctx'> static void interrupt_wq(struct work_struct *);</div><div class='ctx'> </div><div class='hunk'>@@ -62,11 +62,14 @@ int kfd_interrupt_init(struct kfd_node *node)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	node-&gt;ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI, 1);</div><div class='del'>-	if (unlikely(!node-&gt;ih_wq)) {</div><div class='del'>-		kfifo_free(&amp;node-&gt;ih_fifo);</div><div class='del'>-		dev_err(node-&gt;adev-&gt;dev, "Failed to allocate KFD IH workqueue\n");</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	if (!node-&gt;kfd-&gt;ih_wq) {</div><div class='add'>+		node-&gt;kfd-&gt;ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI | WQ_UNBOUND,</div><div class='add'>+						   node-&gt;kfd-&gt;num_nodes);</div><div class='add'>+		if (unlikely(!node-&gt;kfd-&gt;ih_wq)) {</div><div class='add'>+			kfifo_free(&amp;node-&gt;ih_fifo);</div><div class='add'>+			dev_err(node-&gt;adev-&gt;dev, "Failed to allocate KFD IH workqueue\n");</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_lock_init(&amp;node-&gt;interrupt_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -96,14 +99,6 @@ void kfd_interrupt_exit(struct kfd_node *node)</div><div class='ctx'> 	spin_lock_irqsave(&amp;node-&gt;interrupt_lock, flags);</div><div class='ctx'> 	node-&gt;interrupts_active = false;</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;node-&gt;interrupt_lock, flags);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * flush_work ensures that there are no outstanding</div><div class='del'>-	 * work-queue items that will access interrupt_ring. New work items</div><div class='del'>-	 * can't be created because we stopped interrupt handling above.</div><div class='del'>-	 */</div><div class='del'>-	flush_workqueue(node-&gt;ih_wq);</div><div class='del'>-</div><div class='ctx'> 	kfifo_free(&amp;node-&gt;ih_fifo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -112,55 +107,48 @@ void kfd_interrupt_exit(struct kfd_node *node)</div><div class='ctx'>  */</div><div class='ctx'> bool enqueue_ih_ring_entry(struct kfd_node *node, const void *ih_ring_entry)</div><div class='ctx'> {</div><div class='del'>-	int count;</div><div class='del'>-</div><div class='del'>-	count = kfifo_in(&amp;node-&gt;ih_fifo, ih_ring_entry,</div><div class='del'>-				node-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='del'>-	if (count != node-&gt;kfd-&gt;device_info.ih_ring_entry_size) {</div><div class='del'>-		dev_dbg_ratelimited(node-&gt;adev-&gt;dev,</div><div class='del'>-			"Interrupt ring overflow, dropping interrupt %d\n",</div><div class='del'>-			count);</div><div class='add'>+	if (kfifo_is_full(&amp;node-&gt;ih_fifo)) {</div><div class='add'>+		dev_warn_ratelimited(node-&gt;adev-&gt;dev, "KFD node %d ih_fifo overflow\n",</div><div class='add'>+				     node-&gt;node_id);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfifo_in(&amp;node-&gt;ih_fifo, ih_ring_entry, node-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Assumption: single reader/writer. This function is not re-entrant</div><div class='ctx'>  */</div><div class='del'>-static bool dequeue_ih_ring_entry(struct kfd_node *node, void *ih_ring_entry)</div><div class='add'>+static bool dequeue_ih_ring_entry(struct kfd_node *node, u32 **ih_ring_entry)</div><div class='ctx'> {</div><div class='ctx'> 	int count;</div><div class='ctx'> </div><div class='del'>-	count = kfifo_out(&amp;node-&gt;ih_fifo, ih_ring_entry,</div><div class='del'>-				node-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='del'>-</div><div class='del'>-	WARN_ON(count &amp;&amp; count != node-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='add'>+	if (kfifo_is_empty(&amp;node-&gt;ih_fifo))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='add'>+	count = kfifo_out_linear_ptr(&amp;node-&gt;ih_fifo, ih_ring_entry,</div><div class='add'>+				     node-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='add'>+	WARN_ON(count != node-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='ctx'> 	return count == node-&gt;kfd-&gt;device_info.ih_ring_entry_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void interrupt_wq(struct work_struct *work)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_node *dev = container_of(work, struct kfd_node,</div><div class='del'>-						interrupt_work);</div><div class='del'>-	uint32_t ih_ring_entry[KFD_MAX_RING_ENTRY_SIZE];</div><div class='add'>+	struct kfd_node *dev = container_of(work, struct kfd_node, interrupt_work);</div><div class='add'>+	uint32_t *ih_ring_entry;</div><div class='ctx'> 	unsigned long start_jiffies = jiffies;</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;kfd-&gt;device_info.ih_ring_entry_size &gt; sizeof(ih_ring_entry)) {</div><div class='del'>-		dev_err_once(dev-&gt;adev-&gt;dev, "Ring entry too small\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	while (dequeue_ih_ring_entry(dev, ih_ring_entry)) {</div><div class='add'>+	while (dequeue_ih_ring_entry(dev, &amp;ih_ring_entry)) {</div><div class='ctx'> 		dev-&gt;kfd-&gt;device_info.event_interrupt_class-&gt;interrupt_wq(dev,</div><div class='ctx'> 								ih_ring_entry);</div><div class='add'>+		kfifo_skip_count(&amp;dev-&gt;ih_fifo, dev-&gt;kfd-&gt;device_info.ih_ring_entry_size);</div><div class='add'>+</div><div class='ctx'> 		if (time_is_before_jiffies(start_jiffies + HZ)) {</div><div class='ctx'> 			/* If we spent more than a second processing signals,</div><div class='ctx'> 			 * reschedule the worker to avoid soft-lockup warnings</div><div class='ctx'> 			 */</div><div class='del'>-			queue_work(dev-&gt;ih_wq, &amp;dev-&gt;interrupt_work);</div><div class='add'>+			queue_work(dev-&gt;kfd-&gt;ih_wq, &amp;dev-&gt;interrupt_work);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c<br/>index 32c926986dbb..fb3129883a4c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include "kfd_device_queue_manager.h"</div><div class='ctx'> #include "kfd_pm4_headers.h"</div><div class='ctx'> #include "kfd_pm4_opcodes.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> #define PM4_COUNT_ZERO (((1 &lt;&lt; 15) - 1) &lt;&lt; 16)</div><div class='ctx'> </div><div class='hunk'>@@ -45,11 +46,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev,</div><div class='ctx'> 	int retval;</div><div class='ctx'> 	union PM4_MES_TYPE_3_HEADER nop;</div><div class='ctx'> </div><div class='del'>-	if (WARN_ON(type != KFD_QUEUE_TYPE_DIQ &amp;&amp; type != KFD_QUEUE_TYPE_HIQ))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	pr_debug("Initializing queue type %d size %d\n", KFD_QUEUE_TYPE_HIQ,</div><div class='del'>-			queue_size);</div><div class='add'>+	pr_debug("Initializing queue type %d size %d\n", type, queue_size);</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;prop, 0, sizeof(prop));</div><div class='ctx'> 	memset(&amp;nop, 0, sizeof(nop));</div><div class='hunk'>@@ -68,7 +65,8 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev,</div><div class='ctx'> 		kq-&gt;mqd_mgr = dev-&gt;dqm-&gt;mqd_mgrs[KFD_MQD_TYPE_HIQ];</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		pr_err("Invalid queue type %d\n", type);</div><div class='add'>+		WARN(1, "Invalid queue type %d\n", type);</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Invalid queue type %d\n", type);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -78,13 +76,14 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev,</div><div class='ctx'> 	prop.doorbell_ptr = kfd_get_kernel_doorbell(dev-&gt;kfd, &amp;prop.doorbell_off);</div><div class='ctx'> </div><div class='ctx'> 	if (!prop.doorbell_ptr) {</div><div class='del'>-		pr_err("Failed to initialize doorbell");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Failed to initialize doorbell");</div><div class='ctx'> 		goto err_get_kernel_doorbell;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	retval = kfd_gtt_sa_allocate(dev, queue_size, &amp;kq-&gt;pq);</div><div class='ctx'> 	if (retval != 0) {</div><div class='del'>-		pr_err("Failed to init pq queues size %d\n", queue_size);</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Failed to init pq queues size %d\n",</div><div class='add'>+			queue_size);</div><div class='ctx'> 		goto err_pq_allocate_vidmem;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -123,7 +122,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev,</div><div class='ctx'> </div><div class='ctx'> 	memset(kq-&gt;pq_kernel_addr, 0, queue_size);</div><div class='ctx'> 	memset(kq-&gt;rptr_kernel, 0, sizeof(*kq-&gt;rptr_kernel));</div><div class='del'>-	memset(kq-&gt;wptr_kernel, 0, sizeof(*kq-&gt;wptr_kernel));</div><div class='add'>+	memset(kq-&gt;wptr_kernel, 0, dev-&gt;kfd-&gt;device_info.doorbell_size);</div><div class='ctx'> </div><div class='ctx'> 	prop.queue_size = queue_size;</div><div class='ctx'> 	prop.is_interop = false;</div><div class='hunk'>@@ -196,15 +195,17 @@ err_get_kernel_doorbell:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Uninitialize a kernel queue and free all its memory usages. */</div><div class='del'>-static void kq_uninitialize(struct kernel_queue *kq, bool hanging)</div><div class='add'>+static void kq_uninitialize(struct kernel_queue *kq)</div><div class='ctx'> {</div><div class='del'>-	if (kq-&gt;queue-&gt;properties.type == KFD_QUEUE_TYPE_HIQ &amp;&amp; !hanging)</div><div class='add'>+	if (kq-&gt;queue-&gt;properties.type == KFD_QUEUE_TYPE_HIQ &amp;&amp; down_read_trylock(&amp;kq-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem)) {</div><div class='ctx'> 		kq-&gt;mqd_mgr-&gt;destroy_mqd(kq-&gt;mqd_mgr,</div><div class='ctx'> 					kq-&gt;queue-&gt;mqd,</div><div class='ctx'> 					KFD_PREEMPT_TYPE_WAVEFRONT_RESET,</div><div class='ctx'> 					KFD_UNMAP_LATENCY_MS,</div><div class='ctx'> 					kq-&gt;queue-&gt;pipe,</div><div class='ctx'> 					kq-&gt;queue-&gt;queue);</div><div class='add'>+		up_read(&amp;kq-&gt;dev-&gt;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='ctx'> 	else if (kq-&gt;queue-&gt;properties.type == KFD_QUEUE_TYPE_DIQ)</div><div class='ctx'> 		kfd_gtt_sa_free(kq-&gt;dev, kq-&gt;fence_mem_obj);</div><div class='ctx'> </div><div class='hunk'>@@ -302,12 +303,17 @@ int kq_submit_packet(struct kernel_queue *kq)</div><div class='ctx'> 	if (amdgpu_amdkfd_is_fed(kq-&gt;dev-&gt;adev))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='add'>+	/* Make sure ring buffer is updated before wptr updated */</div><div class='add'>+	mb();</div><div class='add'>+</div><div class='ctx'> 	if (kq-&gt;dev-&gt;kfd-&gt;device_info.doorbell_size == 8) {</div><div class='ctx'> 		*kq-&gt;wptr64_kernel = kq-&gt;pending_wptr64;</div><div class='add'>+		mb(); /* Make sure wptr updated before ring doorbell */</div><div class='ctx'> 		write_kernel_doorbell64(kq-&gt;queue-&gt;properties.doorbell_ptr,</div><div class='ctx'> 					kq-&gt;pending_wptr64);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		*kq-&gt;wptr_kernel = kq-&gt;pending_wptr;</div><div class='add'>+		mb(); /* Make sure wptr updated before ring doorbell */</div><div class='ctx'> 		write_kernel_doorbell(kq-&gt;queue-&gt;properties.doorbell_ptr,</div><div class='ctx'> 					kq-&gt;pending_wptr);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -338,15 +344,15 @@ struct kernel_queue *kernel_queue_init(struct kfd_node *dev,</div><div class='ctx'> 	if (kq_initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))</div><div class='ctx'> 		return kq;</div><div class='ctx'> </div><div class='del'>-	pr_err("Failed to init kernel queue\n");</div><div class='add'>+	dev_err(dev-&gt;adev-&gt;dev, "Failed to init kernel queue\n");</div><div class='ctx'> </div><div class='ctx'> 	kfree(kq);</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kernel_queue_uninit(struct kernel_queue *kq, bool hanging)</div><div class='add'>+void kernel_queue_uninit(struct kernel_queue *kq)</div><div class='ctx'> {</div><div class='del'>-	kq_uninitialize(kq, hanging);</div><div class='add'>+	kq_uninitialize(kq);</div><div class='ctx'> 	kfree(kq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -357,26 +363,26 @@ static __attribute__((unused)) void test_kq(struct kfd_node *dev)</div><div class='ctx'> 	uint32_t *buffer, i;</div><div class='ctx'> 	int retval;</div><div class='ctx'> </div><div class='del'>-	pr_err("Starting kernel queue test\n");</div><div class='add'>+	dev_err(dev-&gt;adev-&gt;dev, "Starting kernel queue test\n");</div><div class='ctx'> </div><div class='ctx'> 	kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ);</div><div class='ctx'> 	if (unlikely(!kq)) {</div><div class='del'>-		pr_err("  Failed to initialize HIQ\n");</div><div class='del'>-		pr_err("Kernel queue test failed\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "  Failed to initialize HIQ\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Kernel queue test failed\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	retval = kq_acquire_packet_buffer(kq, 5, &amp;buffer);</div><div class='ctx'> 	if (unlikely(retval != 0)) {</div><div class='del'>-		pr_err("  Failed to acquire packet buffer\n");</div><div class='del'>-		pr_err("Kernel queue test failed\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "  Failed to acquire packet buffer\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Kernel queue test failed\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	for (i = 0; i &lt; 5; i++)</div><div class='ctx'> 		buffer[i] = kq-&gt;nop_packet;</div><div class='ctx'> 	kq_submit_packet(kq);</div><div class='ctx'> </div><div class='del'>-	pr_err("Ending kernel queue test\n");</div><div class='add'>+	dev_err(dev-&gt;adev-&gt;dev, "Ending kernel queue test\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c<br/>index bdc01ca9609a..af53e796ea1b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  * OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='del'>-#include &lt;linux/hmm.h&gt;</div><div class='ctx'> #include &lt;linux/dma-direction.h&gt;</div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include &lt;linux/migrate.h&gt;</div><div class='hunk'>@@ -39,22 +38,22 @@</div><div class='ctx'> #endif</div><div class='ctx'> #define dev_fmt(fmt) "kfd_migrate: " fmt</div><div class='ctx'> </div><div class='del'>-static uint64_t</div><div class='del'>-svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, uint64_t addr)</div><div class='add'>+static u64</div><div class='add'>+svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, u64 addr)</div><div class='ctx'> {</div><div class='ctx'> 	return addr + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='del'>-svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages,</div><div class='del'>-		     dma_addr_t *addr, uint64_t *gart_addr, uint64_t flags)</div><div class='add'>+svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,</div><div class='add'>+		     dma_addr_t *addr, u64 *gart_addr, u64 flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='ctx'> 	struct amdgpu_job *job;</div><div class='ctx'> 	unsigned int num_dw, num_bytes;</div><div class='ctx'> 	struct dma_fence *fence;</div><div class='del'>-	uint64_t src_addr, dst_addr;</div><div class='del'>-	uint64_t pte_flags;</div><div class='add'>+	u64 src_addr, dst_addr;</div><div class='add'>+	u64 pte_flags;</div><div class='ctx'> 	void *cpu_addr;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -68,7 +67,8 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages,</div><div class='ctx'> 				     AMDGPU_FENCE_OWNER_UNDEFINED,</div><div class='ctx'> 				     num_dw * 4 + num_bytes,</div><div class='ctx'> 				     AMDGPU_IB_POOL_DELAYED,</div><div class='del'>-				     &amp;job);</div><div class='add'>+				     &amp;job,</div><div class='add'>+				     AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='hunk'>@@ -77,7 +77,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages,</div><div class='ctx'> </div><div class='ctx'> 	dst_addr = amdgpu_bo_gpu_offset(adev-&gt;gart.bo);</div><div class='ctx'> 	amdgpu_emit_copy_buffer(adev, &amp;job-&gt;ibs[0], src_addr,</div><div class='del'>-				dst_addr, num_bytes, false);</div><div class='add'>+				dst_addr, num_bytes, 0);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ring_pad_ib(ring, &amp;job-&gt;ibs[0]);</div><div class='ctx'> 	WARN_ON(job-&gt;ibs[0].length_dw &gt; num_dw);</div><div class='hunk'>@@ -122,15 +122,15 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages,</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='ctx'> svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,</div><div class='del'>-			     uint64_t *vram, uint64_t npages,</div><div class='add'>+			     u64 *vram, u64 npages,</div><div class='ctx'> 			     enum MIGRATION_COPY_DIR direction,</div><div class='ctx'> 			     struct dma_fence **mfence)</div><div class='ctx'> {</div><div class='del'>-	const uint64_t GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;</div><div class='add'>+	const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;mman.buffer_funcs_ring;</div><div class='del'>-	uint64_t gart_s, gart_d;</div><div class='add'>+	u64 gart_s, gart_d;</div><div class='ctx'> 	struct dma_fence *next;</div><div class='del'>-	uint64_t size;</div><div class='add'>+	u64 size;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;mman.gtt_window_lock);</div><div class='hunk'>@@ -153,7 +153,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE,</div><div class='del'>-				       NULL, &amp;next, false, true, false);</div><div class='add'>+				       NULL, &amp;next, false, true, 0);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "fail %d to copy memory\n", r);</div><div class='ctx'> 			goto out_unlock;</div><div class='hunk'>@@ -217,7 +217,7 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn)</div><div class='ctx'> 	page = pfn_to_page(pfn);</div><div class='ctx'> 	svm_range_bo_ref(prange-&gt;svm_bo);</div><div class='ctx'> 	page-&gt;zone_device_data = prange-&gt;svm_bo;</div><div class='del'>-	zone_device_page_init(page);</div><div class='add'>+	zone_device_page_init(page, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -260,53 +260,56 @@ static void svm_migrate_put_sys_page(unsigned long addr)</div><div class='ctx'> 	put_page(page);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned long svm_migrate_unsuccessful_pages(struct migrate_vma *migrate)</div><div class='add'>+static unsigned long svm_migrate_successful_pages(struct migrate_vma *migrate)</div><div class='ctx'> {</div><div class='del'>-	unsigned long upages = 0;</div><div class='add'>+	unsigned long mpages = 0;</div><div class='ctx'> 	unsigned long i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; migrate-&gt;npages; i++) {</div><div class='del'>-		if (migrate-&gt;src[i] &amp; MIGRATE_PFN_VALID &amp;&amp;</div><div class='del'>-		    !(migrate-&gt;src[i] &amp; MIGRATE_PFN_MIGRATE))</div><div class='del'>-			upages++;</div><div class='add'>+		if (migrate-&gt;dst[i] &amp; MIGRATE_PFN_VALID &amp;&amp;</div><div class='add'>+		    migrate-&gt;src[i] &amp; MIGRATE_PFN_MIGRATE)</div><div class='add'>+			mpages++;</div><div class='ctx'> 	}</div><div class='del'>-	return upages;</div><div class='add'>+	return mpages;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='ctx'> svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 			 struct migrate_vma *migrate, struct dma_fence **mfence,</div><div class='del'>-			 dma_addr_t *scratch, uint64_t ttm_res_offset)</div><div class='add'>+			 dma_addr_t *scratch, u64 ttm_res_offset)</div><div class='ctx'> {</div><div class='del'>-	uint64_t npages = migrate-&gt;cpages;</div><div class='add'>+	u64 npages = migrate-&gt;npages;</div><div class='ctx'> 	struct amdgpu_device *adev = node-&gt;adev;</div><div class='ctx'> 	struct device *dev = adev-&gt;dev;</div><div class='ctx'> 	struct amdgpu_res_cursor cursor;</div><div class='add'>+	u64 mpages = 0;</div><div class='ctx'> 	dma_addr_t *src;</div><div class='del'>-	uint64_t *dst;</div><div class='del'>-	uint64_t i, j;</div><div class='add'>+	u64 *dst;</div><div class='add'>+	u64 i, j;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("svms 0x%p [0x%lx 0x%lx 0x%llx]\n", prange-&gt;svms, prange-&gt;start,</div><div class='ctx'> 		 prange-&gt;last, ttm_res_offset);</div><div class='ctx'> </div><div class='ctx'> 	src = scratch;</div><div class='del'>-	dst = (uint64_t *)(scratch + npages);</div><div class='add'>+	dst = (u64 *)(scratch + npages);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_res_first(prange-&gt;ttm_res, ttm_res_offset,</div><div class='ctx'> 			 npages &lt;&lt; PAGE_SHIFT, &amp;cursor);</div><div class='del'>-	for (i = j = 0; i &lt; npages; i++) {</div><div class='add'>+	for (i = j = 0; (i &lt; npages) &amp;&amp; (mpages &lt; migrate-&gt;cpages); i++) {</div><div class='ctx'> 		struct page *spage;</div><div class='ctx'> </div><div class='del'>-		dst[i] = cursor.start + (j &lt;&lt; PAGE_SHIFT);</div><div class='del'>-		migrate-&gt;dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);</div><div class='del'>-		svm_migrate_get_vram_page(prange, migrate-&gt;dst[i]);</div><div class='del'>-		migrate-&gt;dst[i] = migrate_pfn(migrate-&gt;dst[i]);</div><div class='del'>-</div><div class='add'>+		if (migrate-&gt;src[i] &amp; MIGRATE_PFN_MIGRATE) {</div><div class='add'>+			dst[i] = cursor.start + (j &lt;&lt; PAGE_SHIFT);</div><div class='add'>+			migrate-&gt;dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]);</div><div class='add'>+			svm_migrate_get_vram_page(prange, migrate-&gt;dst[i]);</div><div class='add'>+			migrate-&gt;dst[i] = migrate_pfn(migrate-&gt;dst[i]);</div><div class='add'>+			mpages++;</div><div class='add'>+		}</div><div class='ctx'> 		spage = migrate_pfn_to_page(migrate-&gt;src[i]);</div><div class='ctx'> 		if (spage &amp;&amp; !is_zone_device_page(spage)) {</div><div class='ctx'> 			src[i] = dma_map_page(dev, spage, 0, PAGE_SIZE,</div><div class='del'>-					      DMA_TO_DEVICE);</div><div class='add'>+					      DMA_BIDIRECTIONAL);</div><div class='ctx'> 			r = dma_mapping_error(dev, src[i]);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				dev_err(dev, "%s: fail %d dma_map_page\n",</div><div class='hunk'>@@ -353,9 +356,12 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> out_free_vram_pages:</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		pr_debug("failed %d to copy memory to vram\n", r);</div><div class='del'>-		while (i--) {</div><div class='add'>+		for (i = 0; i &lt; npages &amp;&amp; mpages; i++) {</div><div class='add'>+			if (!dst[i])</div><div class='add'>+				continue;</div><div class='ctx'> 			svm_migrate_put_vram_page(adev, dst[i]);</div><div class='ctx'> 			migrate-&gt;dst[i] = 0;</div><div class='add'>+			mpages--;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -379,11 +385,11 @@ out_free_vram_pages:</div><div class='ctx'> </div><div class='ctx'> static long</div><div class='ctx'> svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='del'>-			struct vm_area_struct *vma, uint64_t start,</div><div class='del'>-			uint64_t end, uint32_t trigger, uint64_t ttm_res_offset)</div><div class='add'>+			struct vm_area_struct *vma, u64 start,</div><div class='add'>+			u64 end, uint32_t trigger, u64 ttm_res_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process *p = container_of(prange-&gt;svms, struct kfd_process, svms);</div><div class='del'>-	uint64_t npages = (end - start) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	u64 npages = (end - start) &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> 	struct amdgpu_device *adev = node-&gt;adev;</div><div class='ctx'> 	struct kfd_process_device *pdd;</div><div class='ctx'> 	struct dma_fence *mfence = NULL;</div><div class='hunk'>@@ -402,7 +408,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev);</div><div class='ctx'> </div><div class='ctx'> 	buf = kvcalloc(npages,</div><div class='del'>-		       2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t),</div><div class='add'>+		       2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t),</div><div class='ctx'> 		       GFP_KERNEL);</div><div class='ctx'> 	if (!buf)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -441,18 +447,17 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	svm_migrate_copy_done(adev, mfence);</div><div class='ctx'> 	migrate_vma_finalize(&amp;migrate);</div><div class='ctx'> </div><div class='del'>-	mpages = cpages - svm_migrate_unsuccessful_pages(&amp;migrate);</div><div class='del'>-	pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n",</div><div class='del'>-			 mpages, cpages, migrate.npages);</div><div class='del'>-</div><div class='del'>-	kfd_smi_event_migration_end(node, p-&gt;lead_thread-&gt;pid,</div><div class='del'>-				    start &gt;&gt; PAGE_SHIFT, end &gt;&gt; PAGE_SHIFT,</div><div class='del'>-				    0, node-&gt;id, trigger);</div><div class='add'>+	mpages = svm_migrate_successful_pages(&amp;migrate);</div><div class='add'>+	pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n",</div><div class='add'>+		 mpages, cpages, migrate.npages);</div><div class='ctx'> </div><div class='ctx'> 	svm_range_dma_unmap_dev(adev-&gt;dev, scratch, 0, npages);</div><div class='ctx'> </div><div class='ctx'> out_free:</div><div class='ctx'> 	kvfree(buf);</div><div class='add'>+	kfd_smi_event_migration_end(node, p-&gt;lead_thread-&gt;pid,</div><div class='add'>+				    start &gt;&gt; PAGE_SHIFT, end &gt;&gt; PAGE_SHIFT,</div><div class='add'>+				    0, node-&gt;id, trigger, r);</div><div class='ctx'> out:</div><div class='ctx'> 	if (!r &amp;&amp; mpages) {</div><div class='ctx'> 		pdd = svm_range_get_pdd_by_node(prange, node);</div><div class='hunk'>@@ -485,7 +490,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long addr, start, end;</div><div class='ctx'> 	struct vm_area_struct *vma;</div><div class='del'>-	uint64_t ttm_res_offset;</div><div class='add'>+	u64 ttm_res_offset;</div><div class='ctx'> 	struct kfd_node *node;</div><div class='ctx'> 	unsigned long mpages = 0;</div><div class='ctx'> 	long r = 0;</div><div class='hunk'>@@ -509,10 +514,19 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> 	start = start_mgr &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 	end = (last_mgr + 1) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_amdkfd_reserve_mem_limit(node-&gt;adev,</div><div class='add'>+					prange-&gt;npages * PAGE_SIZE,</div><div class='add'>+					KFD_IOC_ALLOC_MEM_FLAGS_VRAM,</div><div class='add'>+					node-&gt;xcp ? node-&gt;xcp-&gt;id : 0);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_dbg(node-&gt;adev-&gt;dev, "failed to reserve VRAM, r: %ld\n", r);</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	r = svm_range_vram_node_new(node, prange, true);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_dbg(node-&gt;adev-&gt;dev, "fail %ld to alloc vram\n", r);</div><div class='del'>-		return r;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> 	ttm_res_offset = (start_mgr - prange-&gt;start + prange-&gt;offset) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='hunk'>@@ -545,11 +559,17 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> 		svm_range_vram_node_free(prange);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+	amdgpu_amdkfd_unreserve_mem_limit(node-&gt;adev,</div><div class='add'>+					prange-&gt;npages * PAGE_SIZE,</div><div class='add'>+					KFD_IOC_ALLOC_MEM_FLAGS_VRAM,</div><div class='add'>+					node-&gt;xcp ? node-&gt;xcp-&gt;id : 0);</div><div class='ctx'> 	return r &lt; 0 ? r : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void svm_migrate_page_free(struct page *page)</div><div class='add'>+static void svm_migrate_folio_free(struct folio *folio)</div><div class='ctx'> {</div><div class='add'>+	struct page *page = &amp;folio-&gt;page;</div><div class='ctx'> 	struct svm_range_bo *svm_bo = page-&gt;zone_device_data;</div><div class='ctx'> </div><div class='ctx'> 	if (svm_bo) {</div><div class='hunk'>@@ -561,14 +581,14 @@ static void svm_migrate_page_free(struct page *page)</div><div class='ctx'> static int</div><div class='ctx'> svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,</div><div class='ctx'> 			struct migrate_vma *migrate, struct dma_fence **mfence,</div><div class='del'>-			dma_addr_t *scratch, uint64_t npages)</div><div class='add'>+			dma_addr_t *scratch, u64 npages)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = adev-&gt;dev;</div><div class='del'>-	uint64_t *src;</div><div class='add'>+	u64 *src;</div><div class='ctx'> 	dma_addr_t *dst;</div><div class='ctx'> 	struct page *dpage;</div><div class='del'>-	uint64_t i = 0, j;</div><div class='del'>-	uint64_t addr;</div><div class='add'>+	u64 i = 0, j;</div><div class='add'>+	u64 addr;</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange-&gt;svms, prange-&gt;start,</div><div class='hunk'>@@ -576,7 +596,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,</div><div class='ctx'> </div><div class='ctx'> 	addr = migrate-&gt;start;</div><div class='ctx'> </div><div class='del'>-	src = (uint64_t *)(scratch + npages);</div><div class='add'>+	src = (u64 *)(scratch + npages);</div><div class='ctx'> 	dst = scratch;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, j = 0; i &lt; npages; i++, addr += PAGE_SIZE) {</div><div class='hunk'>@@ -616,7 +636,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,</div><div class='ctx'> 			goto out_oom;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		dst[i] = dma_map_page(dev, dpage, 0, PAGE_SIZE, DMA_FROM_DEVICE);</div><div class='add'>+		dst[i] = dma_map_page(dev, dpage, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);</div><div class='ctx'> 		r = dma_mapping_error(dev, dst[i]);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dev_err(adev-&gt;dev, "%s: fail %d dma_map_page\n", __func__, r);</div><div class='hunk'>@@ -664,12 +684,11 @@ out_oom:</div><div class='ctx'>  */</div><div class='ctx'> static long</div><div class='ctx'> svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='del'>-		       struct vm_area_struct *vma, uint64_t start, uint64_t end,</div><div class='add'>+		       struct vm_area_struct *vma, u64 start, u64 end,</div><div class='ctx'> 		       uint32_t trigger, struct page *fault_page)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process *p = container_of(prange-&gt;svms, struct kfd_process, svms);</div><div class='del'>-	uint64_t npages = (end - start) &gt;&gt; PAGE_SHIFT;</div><div class='del'>-	unsigned long upages = npages;</div><div class='add'>+	u64 npages = (end - start) &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> 	unsigned long cpages = 0;</div><div class='ctx'> 	unsigned long mpages = 0;</div><div class='ctx'> 	struct amdgpu_device *adev = node-&gt;adev;</div><div class='hunk'>@@ -691,7 +710,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 		migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE;</div><div class='ctx'> </div><div class='ctx'> 	buf = kvcalloc(npages,</div><div class='del'>-		       2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t),</div><div class='add'>+		       2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t),</div><div class='ctx'> 		       GFP_KERNEL);</div><div class='ctx'> 	if (!buf)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -717,7 +736,6 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	if (!cpages) {</div><div class='ctx'> 		pr_debug("failed collect migrate device pages [0x%lx 0x%lx]\n",</div><div class='ctx'> 			 prange-&gt;start, prange-&gt;last);</div><div class='del'>-		upages = svm_migrate_unsuccessful_pages(&amp;migrate);</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (cpages != npages)</div><div class='hunk'>@@ -730,24 +748,22 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 				    scratch, npages);</div><div class='ctx'> 	migrate_vma_pages(&amp;migrate);</div><div class='ctx'> </div><div class='del'>-	upages = svm_migrate_unsuccessful_pages(&amp;migrate);</div><div class='del'>-	pr_debug("unsuccessful/cpages/npages 0x%lx/0x%lx/0x%lx\n",</div><div class='del'>-		 upages, cpages, migrate.npages);</div><div class='add'>+	mpages = svm_migrate_successful_pages(&amp;migrate);</div><div class='add'>+	pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n",</div><div class='add'>+		 mpages, cpages, migrate.npages);</div><div class='ctx'> </div><div class='ctx'> 	svm_migrate_copy_done(adev, mfence);</div><div class='ctx'> 	migrate_vma_finalize(&amp;migrate);</div><div class='ctx'> </div><div class='del'>-	kfd_smi_event_migration_end(node, p-&gt;lead_thread-&gt;pid,</div><div class='del'>-				    start &gt;&gt; PAGE_SHIFT, end &gt;&gt; PAGE_SHIFT,</div><div class='del'>-				    node-&gt;id, 0, trigger);</div><div class='del'>-</div><div class='ctx'> 	svm_range_dma_unmap_dev(adev-&gt;dev, scratch, 0, npages);</div><div class='ctx'> </div><div class='ctx'> out_free:</div><div class='ctx'> 	kvfree(buf);</div><div class='add'>+	kfd_smi_event_migration_end(node, p-&gt;lead_thread-&gt;pid,</div><div class='add'>+				    start &gt;&gt; PAGE_SHIFT, end &gt;&gt; PAGE_SHIFT,</div><div class='add'>+				    node-&gt;id, 0, trigger, r);</div><div class='ctx'> out:</div><div class='del'>-	if (!r &amp;&amp; cpages) {</div><div class='del'>-		mpages = cpages - upages;</div><div class='add'>+	if (!r &amp;&amp; mpages) {</div><div class='ctx'> 		pdd = svm_range_get_pdd_by_node(prange, node);</div><div class='ctx'> 		if (pdd)</div><div class='ctx'> 			WRITE_ONCE(pdd-&gt;page_out, pdd-&gt;page_out + mpages);</div><div class='hunk'>@@ -830,6 +846,9 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (r &gt;= 0) {</div><div class='add'>+		WARN_ONCE(prange-&gt;vram_pages &lt; mpages,</div><div class='add'>+			  "Recorded vram pages(0x%llx) should not be less than migration pages(0x%lx).",</div><div class='add'>+			  prange-&gt;vram_pages, mpages);</div><div class='ctx'> 		prange-&gt;vram_pages -= mpages;</div><div class='ctx'> </div><div class='ctx'> 		/* prange does not have vram page set its actual_loc to system</div><div class='hunk'>@@ -990,7 +1009,7 @@ out_mmput:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dev_pagemap_ops svm_migrate_pgmap_ops = {</div><div class='del'>-	.page_free		= svm_migrate_page_free,</div><div class='add'>+	.folio_free		= svm_migrate_folio_free,</div><div class='ctx'> 	.migrate_to_ram		= svm_migrate_to_ram,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1009,7 +1028,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(9, 0, 1))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;gmc.is_app_apu)</div><div class='add'>+	if (adev-&gt;apu_prefer_gtt)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	pgmap = &amp;kfddev-&gt;pgmap;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h<br/>index 2eebf67f9c2c..2b7fd442d29c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.h</a></div><div class='hunk'>@@ -31,7 +31,6 @@</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/sched/mm.h&gt;</div><div class='del'>-#include &lt;linux/hmm.h&gt;</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> #include "kfd_svm.h"</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c<br/>index aee2212e52f6..33aa23450b3f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_module.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_module.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_module.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_module.c</a></div><div class='hunk'>@@ -78,8 +78,8 @@ err_ioctl:</div><div class='ctx'> static void kfd_exit(void)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_cleanup_processes();</div><div class='del'>-	kfd_debugfs_fini();</div><div class='ctx'> 	kfd_process_destroy_wq();</div><div class='add'>+	kfd_debugfs_fini();</div><div class='ctx'> 	kfd_procfs_shutdown();</div><div class='ctx'> 	kfd_topology_shutdown();</div><div class='ctx'> 	kfd_chardev_exit();</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c<br/>index 050a6936ff84..d9ae854b6908 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c</a></div><div class='hunk'>@@ -118,18 +118,20 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,</div><div class='ctx'> 	 * attention grabbing.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (gfx_info-&gt;max_shader_engines &gt; KFD_MAX_NUM_SE) {</div><div class='del'>-		pr_err("Exceeded KFD_MAX_NUM_SE, chip reports %d\n",</div><div class='del'>-		       gfx_info-&gt;max_shader_engines);</div><div class='add'>+		dev_err(mm-&gt;dev-&gt;adev-&gt;dev,</div><div class='add'>+			"Exceeded KFD_MAX_NUM_SE, chip reports %d\n",</div><div class='add'>+			gfx_info-&gt;max_shader_engines);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (gfx_info-&gt;max_sh_per_se &gt; KFD_MAX_NUM_SH_PER_SE) {</div><div class='del'>-		pr_err("Exceeded KFD_MAX_NUM_SH, chip reports %d\n",</div><div class='add'>+		dev_err(mm-&gt;dev-&gt;adev-&gt;dev,</div><div class='add'>+			"Exceeded KFD_MAX_NUM_SH, chip reports %d\n",</div><div class='ctx'> 			gfx_info-&gt;max_sh_per_se * gfx_info-&gt;max_shader_engines);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cu_bitmap_sh_mul = (KFD_GC_VERSION(mm-&gt;dev) &gt;= IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='del'>-			    KFD_GC_VERSION(mm-&gt;dev) &lt; IP_VERSION(12, 0, 0)) ? 2 : 1;</div><div class='add'>+			    KFD_GC_VERSION(mm-&gt;dev) &lt; IP_VERSION(13, 0, 0)) ? 2 : 1;</div><div class='ctx'> </div><div class='ctx'> 	/* Count active CUs per SH.</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -223,7 +225,7 @@ void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	      struct kfd_mem_obj *mqd_mem_obj)</div><div class='ctx'> {</div><div class='ctx'> 	if (mqd_mem_obj-&gt;gtt_mem) {</div><div class='del'>-		amdgpu_amdkfd_free_gtt_mem(mm-&gt;dev-&gt;adev, mqd_mem_obj-&gt;gtt_mem);</div><div class='add'>+		amdgpu_amdkfd_free_gtt_mem(mm-&gt;dev-&gt;adev, &amp;mqd_mem_obj-&gt;gtt_mem);</div><div class='ctx'> 		kfree(mqd_mem_obj);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		kfd_gtt_sa_free(mm-&gt;dev, mqd_mem_obj);</div><div class='hunk'>@@ -290,3 +292,21 @@ uint64_t kfd_mqd_stride(struct mqd_manager *mm,</div><div class='ctx'> {</div><div class='ctx'> 	return mm-&gt;mqd_size;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id,</div><div class='add'>+				   uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	if (doorbell_id) {</div><div class='add'>+		struct device *dev = node-&gt;adev-&gt;dev;</div><div class='add'>+</div><div class='add'>+		if (node-&gt;adev-&gt;xcp_mgr &amp;&amp; node-&gt;adev-&gt;xcp_mgr-&gt;num_xcps &gt; 0)</div><div class='add'>+			dev_err(dev, "XCC %d: Queue preemption failed for queue with doorbell_id: %x\n",</div><div class='add'>+							inst, doorbell_id);</div><div class='add'>+		else</div><div class='add'>+			dev_err(dev, "Queue preemption failed for queue with doorbell_id: %x\n",</div><div class='add'>+							doorbell_id);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h<br/>index e5cc697a3ca8..17cc1f25c8d0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h</a></div><div class='hunk'>@@ -119,7 +119,7 @@ struct mqd_manager {</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 	int	(*debugfs_show_mqd)(struct seq_file *m, void *data);</div><div class='ctx'> #endif</div><div class='del'>-	uint32_t (*read_doorbell_id)(void *mqd);</div><div class='add'>+	bool (*check_preemption_failed)(struct mqd_manager *mm, void *mqd);</div><div class='ctx'> 	uint64_t (*mqd_stride)(struct mqd_manager *mm,</div><div class='ctx'> 				struct queue_properties *p);</div><div class='ctx'> </div><div class='hunk'>@@ -198,4 +198,6 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev,</div><div class='ctx'> uint64_t kfd_hiq_mqd_stride(struct kfd_node *dev);</div><div class='ctx'> uint64_t kfd_mqd_stride(struct mqd_manager *mm,</div><div class='ctx'> 			struct queue_properties *q);</div><div class='add'>+bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id,</div><div class='add'>+				   uint32_t inst);</div><div class='ctx'> #endif /* KFD_MQD_MANAGER_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c<br/>index 1a4a69943c71..05f3ac2eaef9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c</a></div><div class='hunk'>@@ -206,11 +206,11 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint32_t read_doorbell_id(void *mqd)</div><div class='add'>+static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)</div><div class='ctx'> {</div><div class='ctx'> 	struct cik_mqd *m = (struct cik_mqd *)mqd;</div><div class='ctx'> </div><div class='del'>-	return m-&gt;queue_doorbell_id0;</div><div class='add'>+	return kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev, m-&gt;queue_doorbell_id0, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='hunk'>@@ -423,7 +423,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='ctx'> #endif</div><div class='del'>-		mqd-&gt;read_doorbell_id = read_doorbell_id;</div><div class='add'>+		mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_MQD_TYPE_DIQ:</div><div class='ctx'> 		mqd-&gt;allocate_mqd = allocate_mqd;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c<br/>index 22cbfa1bdadd..1695dd78ede8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c</a></div><div class='hunk'>@@ -107,6 +107,8 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,</div><div class='ctx'> 	m-&gt;cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |</div><div class='ctx'> 			0x53 &lt;&lt; CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;</div><div class='ctx'> </div><div class='add'>+	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;</div><div class='ctx'> 	m-&gt;cp_mqd_control = 1 &lt;&lt; CP_MQD_CONTROL__PRIV_STATE__SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	m-&gt;cp_mqd_base_addr_lo        = lower_32_bits(addr);</div><div class='hunk'>@@ -167,10 +169,10 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> </div><div class='ctx'> 	m = get_mqd(mqd);</div><div class='ctx'> </div><div class='del'>-	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control &amp;= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;</div><div class='ctx'> 	m-&gt;cp_hqd_pq_control |=</div><div class='ctx'> 			ffs(q-&gt;queue_size / sizeof(unsigned int)) - 1 - 1;</div><div class='del'>-	m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;</div><div class='add'>+</div><div class='ctx'> 	pr_debug("cp_hqd_pq_control 0x%x\n", m-&gt;cp_hqd_pq_control);</div><div class='ctx'> </div><div class='ctx'> 	m-&gt;cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-&gt;queue_address &gt;&gt; 8);</div><div class='hunk'>@@ -224,11 +226,11 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint32_t read_doorbell_id(void *mqd)</div><div class='add'>+static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)</div><div class='ctx'> {</div><div class='ctx'> 	struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd;</div><div class='ctx'> </div><div class='del'>-	return m-&gt;queue_doorbell_id0;</div><div class='add'>+	return kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev, m-&gt;queue_doorbell_id0, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int get_wave_state(struct mqd_manager *mm, void *mqd,</div><div class='hunk'>@@ -488,7 +490,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='ctx'> #endif</div><div class='del'>-		mqd-&gt;read_doorbell_id = read_doorbell_id;</div><div class='add'>+		mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='ctx'> 		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_MQD_TYPE_DIQ:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c<br/>index 826bc4f6c8a7..3c0ae28c5923 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c</a></div><div class='hunk'>@@ -154,6 +154,8 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,</div><div class='ctx'> 	m-&gt;cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |</div><div class='ctx'> 			0x55 &lt;&lt; CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;</div><div class='ctx'> </div><div class='add'>+	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;</div><div class='ctx'> 	m-&gt;cp_mqd_control = 1 &lt;&lt; CP_MQD_CONTROL__PRIV_STATE__SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	m-&gt;cp_mqd_base_addr_lo        = lower_32_bits(addr);</div><div class='hunk'>@@ -221,10 +223,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> </div><div class='ctx'> 	m = get_mqd(mqd);</div><div class='ctx'> </div><div class='del'>-	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control &amp;= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;</div><div class='ctx'> 	m-&gt;cp_hqd_pq_control |=</div><div class='ctx'> 			ffs(q-&gt;queue_size / sizeof(unsigned int)) - 1 - 1;</div><div class='del'>-	m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;</div><div class='ctx'> 	pr_debug("cp_hqd_pq_control 0x%x\n", m-&gt;cp_hqd_pq_control);</div><div class='ctx'> </div><div class='ctx'> 	m-&gt;cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-&gt;queue_address &gt;&gt; 8);</div><div class='hunk'>@@ -278,11 +279,11 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint32_t read_doorbell_id(void *mqd)</div><div class='add'>+static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)</div><div class='ctx'> {</div><div class='ctx'> 	struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd;</div><div class='ctx'> </div><div class='del'>-	return m-&gt;queue_doorbell_id0;</div><div class='add'>+	return kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev, m-&gt;queue_doorbell_id0, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int get_wave_state(struct mqd_manager *mm, void *mqd,</div><div class='hunk'>@@ -517,7 +518,7 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='ctx'> #endif</div><div class='del'>-		mqd-&gt;read_doorbell_id = read_doorbell_id;</div><div class='add'>+		mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='ctx'> 		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_MQD_TYPE_DIQ:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c<br/>new file mode 100644<br/>index 000000000000..565858b9044d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c</a></div><div class='hunk'>@@ -0,0 +1,459 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/printk.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/uaccess.h&gt;</div><div class='add'>+#include "kfd_priv.h"</div><div class='add'>+#include "kfd_mqd_manager.h"</div><div class='add'>+#include "v12_structs.h"</div><div class='add'>+#include "gc/gc_12_0_0_sh_mask.h"</div><div class='add'>+#include "amdgpu_amdkfd.h"</div><div class='add'>+</div><div class='add'>+static inline struct v12_compute_mqd *get_mqd(void *mqd)</div><div class='add'>+{</div><div class='add'>+	return (struct v12_compute_mqd *)mqd;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct v12_sdma_mqd *get_sdma_mqd(void *mqd)</div><div class='add'>+{</div><div class='add'>+	return (struct v12_sdma_mqd *)mqd;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void update_cu_mask(struct mqd_manager *mm, void *mqd,</div><div class='add'>+			   struct mqd_update_info *minfo)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *m;</div><div class='add'>+	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};</div><div class='add'>+</div><div class='add'>+	if (!minfo || !minfo-&gt;cu_mask.ptr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mqd_symmetrically_map_cu_mask(mm,</div><div class='add'>+		minfo-&gt;cu_mask.ptr, minfo-&gt;cu_mask.count, se_mask, 0);</div><div class='add'>+</div><div class='add'>+	m = get_mqd(mqd);</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se0 = se_mask[0];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se1 = se_mask[1];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se2 = se_mask[2];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se3 = se_mask[3];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se4 = se_mask[4];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se5 = se_mask[5];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se6 = se_mask[6];</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se7 = se_mask[7];</div><div class='add'>+</div><div class='add'>+	pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se0,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se1,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se2,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se3,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se4,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se5,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se6,</div><div class='add'>+		m-&gt;compute_static_thread_mgmt_se7);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q)</div><div class='add'>+{</div><div class='add'>+	m-&gt;cp_hqd_pipe_priority = pipe_priority_map[q-&gt;priority];</div><div class='add'>+	m-&gt;cp_hqd_queue_priority = q-&gt;priority;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,</div><div class='add'>+		struct queue_properties *q)</div><div class='add'>+{</div><div class='add'>+	struct kfd_mem_obj *mqd_mem_obj;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond</div><div class='add'>+	 * struct MQD size.</div><div class='add'>+	 */</div><div class='add'>+	if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &amp;mqd_mem_obj))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return mqd_mem_obj;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_mqd(struct mqd_manager *mm, void **mqd,</div><div class='add'>+			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,</div><div class='add'>+			struct queue_properties *q)</div><div class='add'>+{</div><div class='add'>+	uint64_t addr;</div><div class='add'>+	struct v12_compute_mqd *m;</div><div class='add'>+</div><div class='add'>+	m = (struct v12_compute_mqd *) mqd_mem_obj-&gt;cpu_ptr;</div><div class='add'>+	addr = mqd_mem_obj-&gt;gpu_addr;</div><div class='add'>+</div><div class='add'>+	memset(m, 0, PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	m-&gt;header = 0xC0310800;</div><div class='add'>+	m-&gt;compute_pipelinestat_enable = 1;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se0 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se1 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se2 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se3 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se4 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se5 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se6 = 0xFFFFFFFF;</div><div class='add'>+	m-&gt;compute_static_thread_mgmt_se7 = 0xFFFFFFFF;</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |</div><div class='add'>+			0x55 &lt;&lt; CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;</div><div class='add'>+	m-&gt;cp_mqd_control = 1 &lt;&lt; CP_MQD_CONTROL__PRIV_STATE__SHIFT;</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_mqd_base_addr_lo        = lower_32_bits(addr);</div><div class='add'>+	m-&gt;cp_mqd_base_addr_hi        = upper_32_bits(addr);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_quantum = 1 &lt;&lt; CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |</div><div class='add'>+			1 &lt;&lt; CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |</div><div class='add'>+			1 &lt;&lt; CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;</div><div class='add'>+</div><div class='add'>+	/* Set cp_hqd_hq_status0.c_queue_debug_en to 1 to have the CP set up the</div><div class='add'>+	 * DISPATCH_PTR.  This is required for the kfd debugger</div><div class='add'>+	 */</div><div class='add'>+	m-&gt;cp_hqd_hq_status0 = 1 &lt;&lt; 14;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_amdkfd_have_atomics_support(mm-&gt;dev-&gt;adev))</div><div class='add'>+		m-&gt;cp_hqd_hq_status0 |= 1 &lt;&lt; 29;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;format == KFD_QUEUE_FORMAT_AQL) {</div><div class='add'>+		m-&gt;cp_hqd_aql_control =</div><div class='add'>+			1 &lt;&lt; CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mm-&gt;dev-&gt;kfd-&gt;cwsr_enabled) {</div><div class='add'>+		m-&gt;cp_hqd_persistent_state |=</div><div class='add'>+			(1 &lt;&lt; CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);</div><div class='add'>+		m-&gt;cp_hqd_ctx_save_base_addr_lo =</div><div class='add'>+			lower_32_bits(q-&gt;ctx_save_restore_area_address);</div><div class='add'>+		m-&gt;cp_hqd_ctx_save_base_addr_hi =</div><div class='add'>+			upper_32_bits(q-&gt;ctx_save_restore_area_address);</div><div class='add'>+		m-&gt;cp_hqd_ctx_save_size = q-&gt;ctx_save_restore_area_size;</div><div class='add'>+		m-&gt;cp_hqd_cntl_stack_size = q-&gt;ctl_stack_size;</div><div class='add'>+		m-&gt;cp_hqd_cntl_stack_offset = q-&gt;ctl_stack_size;</div><div class='add'>+		m-&gt;cp_hqd_wg_state_offset = q-&gt;ctl_stack_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*mqd = m;</div><div class='add'>+	if (gart_addr)</div><div class='add'>+		*gart_addr = addr;</div><div class='add'>+	mm-&gt;update_mqd(mm, m, q, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int load_mqd(struct mqd_manager *mm, void *mqd,</div><div class='add'>+			uint32_t pipe_id, uint32_t queue_id,</div><div class='add'>+			struct queue_properties *p, struct mm_struct *mms)</div><div class='add'>+{</div><div class='add'>+	int r = 0;</div><div class='add'>+	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */</div><div class='add'>+	uint32_t wptr_shift = (p-&gt;format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);</div><div class='add'>+</div><div class='add'>+	r = mm-&gt;dev-&gt;kfd2kgd-&gt;hqd_load(mm-&gt;dev-&gt;adev, mqd, pipe_id, queue_id,</div><div class='add'>+					  (uint32_t __user *)p-&gt;write_ptr,</div><div class='add'>+					  wptr_shift, 0, mms, 0);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='add'>+		       struct queue_properties *q,</div><div class='add'>+		       struct mqd_update_info *minfo)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *m;</div><div class='add'>+</div><div class='add'>+	m = get_mqd(mqd);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_pq_control &amp;= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;</div><div class='add'>+	m-&gt;cp_hqd_pq_control |=</div><div class='add'>+			ffs(q-&gt;queue_size / sizeof(unsigned int)) - 1 - 1;</div><div class='add'>+	pr_debug("cp_hqd_pq_control 0x%x\n", m-&gt;cp_hqd_pq_control);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-&gt;queue_address &gt;&gt; 8);</div><div class='add'>+	m-&gt;cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-&gt;queue_address &gt;&gt; 8);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-&gt;read_ptr);</div><div class='add'>+	m-&gt;cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q-&gt;read_ptr);</div><div class='add'>+	m-&gt;cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q-&gt;write_ptr);</div><div class='add'>+	m-&gt;cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q-&gt;write_ptr);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_pq_doorbell_control =</div><div class='add'>+		q-&gt;doorbell_off &lt;&lt;</div><div class='add'>+			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;</div><div class='add'>+	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",</div><div class='add'>+			m-&gt;cp_hqd_pq_doorbell_control);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_ib_control = 3 &lt;&lt; CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * HW does not clamp this field correctly. Maximum EOP queue size</div><div class='add'>+	 * is constrained by per-SE EOP done signal count, which is 8-bit.</div><div class='add'>+	 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit</div><div class='add'>+	 * more than (EOP entry count - 1) so a queue size of 0x800 dwords</div><div class='add'>+	 * is safe, giving a maximum field value of 0xA.</div><div class='add'>+	 */</div><div class='add'>+	m-&gt;cp_hqd_eop_control = min(0xA,</div><div class='add'>+		ffs(q-&gt;eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);</div><div class='add'>+	m-&gt;cp_hqd_eop_base_addr_lo =</div><div class='add'>+			lower_32_bits(q-&gt;eop_ring_buffer_address &gt;&gt; 8);</div><div class='add'>+	m-&gt;cp_hqd_eop_base_addr_hi =</div><div class='add'>+			upper_32_bits(q-&gt;eop_ring_buffer_address &gt;&gt; 8);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_iq_timer = 0;</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_vmid = q-&gt;vmid;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;format == KFD_QUEUE_FORMAT_AQL) {</div><div class='add'>+		/* GC 10 removed WPP_CLAMP from PQ Control */</div><div class='add'>+		m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |</div><div class='add'>+				2 &lt;&lt; CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |</div><div class='add'>+				1 &lt;&lt; CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT;</div><div class='add'>+		m-&gt;cp_hqd_pq_doorbell_control |=</div><div class='add'>+			1 &lt;&lt; CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;</div><div class='add'>+	}</div><div class='add'>+	if (mm-&gt;dev-&gt;kfd-&gt;cwsr_enabled)</div><div class='add'>+		m-&gt;cp_hqd_ctx_save_control = 0;</div><div class='add'>+</div><div class='add'>+	update_cu_mask(mm, mqd, minfo);</div><div class='add'>+	set_priority(m, q);</div><div class='add'>+</div><div class='add'>+	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *m = (struct v12_compute_mqd *)mqd;</div><div class='add'>+</div><div class='add'>+	return kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev, m-&gt;queue_doorbell_id0, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_wave_state(struct mqd_manager *mm, void *mqd,</div><div class='add'>+			  struct queue_properties *q,</div><div class='add'>+			  void __user *ctl_stack,</div><div class='add'>+			  u32 *ctl_stack_used_size,</div><div class='add'>+			  u32 *save_area_used_size)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *m;</div><div class='add'>+	struct mqd_user_context_save_area_header header;</div><div class='add'>+</div><div class='add'>+	m = get_mqd(mqd);</div><div class='add'>+</div><div class='add'>+	/* Control stack is written backwards, while workgroup context data</div><div class='add'>+	 * is written forwards. Both starts from m-&gt;cp_hqd_cntl_stack_size.</div><div class='add'>+	 * Current position is at m-&gt;cp_hqd_cntl_stack_offset and</div><div class='add'>+	 * m-&gt;cp_hqd_wg_state_offset, respectively.</div><div class='add'>+	 */</div><div class='add'>+	*ctl_stack_used_size = m-&gt;cp_hqd_cntl_stack_size -</div><div class='add'>+		m-&gt;cp_hqd_cntl_stack_offset;</div><div class='add'>+	*save_area_used_size = m-&gt;cp_hqd_wg_state_offset -</div><div class='add'>+		m-&gt;cp_hqd_cntl_stack_size;</div><div class='add'>+</div><div class='add'>+	/* Control stack is not copied to user mode for GFXv12 because</div><div class='add'>+	 * it's part of the context save area that is already</div><div class='add'>+	 * accessible to user mode</div><div class='add'>+	 */</div><div class='add'>+	header.control_stack_size = *ctl_stack_used_size;</div><div class='add'>+	header.wave_state_size = *save_area_used_size;</div><div class='add'>+</div><div class='add'>+	header.wave_state_offset = m-&gt;cp_hqd_wg_state_offset;</div><div class='add'>+	header.control_stack_offset = m-&gt;cp_hqd_cntl_stack_offset;</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(ctl_stack, &amp;header, sizeof(header)))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,</div><div class='add'>+			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,</div><div class='add'>+			struct queue_properties *q)</div><div class='add'>+{</div><div class='add'>+	struct v12_compute_mqd *m;</div><div class='add'>+</div><div class='add'>+	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);</div><div class='add'>+</div><div class='add'>+	m = get_mqd(*mqd);</div><div class='add'>+</div><div class='add'>+	m-&gt;cp_hqd_pq_control |= 1 &lt;&lt; CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |</div><div class='add'>+			1 &lt;&lt; CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,</div><div class='add'>+		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,</div><div class='add'>+		struct queue_properties *q)</div><div class='add'>+{</div><div class='add'>+	struct v12_sdma_mqd *m;</div><div class='add'>+</div><div class='add'>+	m = (struct v12_sdma_mqd *) mqd_mem_obj-&gt;cpu_ptr;</div><div class='add'>+</div><div class='add'>+	memset(m, 0, sizeof(struct v12_sdma_mqd));</div><div class='add'>+</div><div class='add'>+	*mqd = m;</div><div class='add'>+	if (gart_addr)</div><div class='add'>+		*gart_addr = mqd_mem_obj-&gt;gpu_addr;</div><div class='add'>+</div><div class='add'>+	mm-&gt;update_mqd(mm, m, q, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define SDMA_RLC_DUMMY_DEFAULT 0xf</div><div class='add'>+</div><div class='add'>+static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,</div><div class='add'>+		struct queue_properties *q,</div><div class='add'>+		struct mqd_update_info *minfo)</div><div class='add'>+{</div><div class='add'>+	struct v12_sdma_mqd *m;</div><div class='add'>+</div><div class='add'>+	m = get_sdma_mqd(mqd);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_cntl = (ffs(q-&gt;queue_size / sizeof(unsigned int)) - 1)</div><div class='add'>+		&lt;&lt; SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |</div><div class='add'>+		q-&gt;vmid &lt;&lt; SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT |</div><div class='add'>+		1 &lt;&lt; SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |</div><div class='add'>+		6 &lt;&lt; SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |</div><div class='add'>+		1 &lt;&lt; SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_base = lower_32_bits(q-&gt;queue_address &gt;&gt; 8);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_base_hi = upper_32_bits(q-&gt;queue_address &gt;&gt; 8);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q-&gt;read_ptr);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q-&gt;read_ptr);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q-&gt;write_ptr);</div><div class='add'>+	m-&gt;sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q-&gt;write_ptr);</div><div class='add'>+	m-&gt;sdmax_rlcx_doorbell_offset =</div><div class='add'>+		q-&gt;doorbell_off &lt;&lt; SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum</div><div class='add'>+		&lt;&lt; SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT)</div><div class='add'>+		 &amp; SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdma_engine_id = q-&gt;sdma_engine_id;</div><div class='add'>+	m-&gt;sdma_queue_id = q-&gt;sdma_queue_id;</div><div class='add'>+</div><div class='add'>+	m-&gt;sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;</div><div class='add'>+</div><div class='add'>+	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+</div><div class='add'>+static int debugfs_show_mqd(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,</div><div class='add'>+		     data, sizeof(struct v12_compute_mqd), false);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,</div><div class='add'>+		     data, sizeof(struct v12_sdma_mqd), false);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type,</div><div class='add'>+		struct kfd_node *dev)</div><div class='add'>+{</div><div class='add'>+	struct mqd_manager *mqd;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(type &gt;= KFD_MQD_TYPE_MAX))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);</div><div class='add'>+	if (!mqd)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	mqd-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case KFD_MQD_TYPE_CP:</div><div class='add'>+		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='add'>+		mqd-&gt;allocate_mqd = allocate_mqd;</div><div class='add'>+		mqd-&gt;init_mqd = init_mqd;</div><div class='add'>+		mqd-&gt;free_mqd = kfd_free_mqd_cp;</div><div class='add'>+		mqd-&gt;load_mqd = load_mqd;</div><div class='add'>+		mqd-&gt;update_mqd = update_mqd;</div><div class='add'>+		mqd-&gt;destroy_mqd = kfd_destroy_mqd_cp;</div><div class='add'>+		mqd-&gt;is_occupied = kfd_is_occupied_cp;</div><div class='add'>+		mqd-&gt;mqd_size = sizeof(struct v12_compute_mqd);</div><div class='add'>+		mqd-&gt;get_wave_state = get_wave_state;</div><div class='add'>+		mqd-&gt;mqd_stride = kfd_mqd_stride;</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='add'>+#endif</div><div class='add'>+		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='add'>+		break;</div><div class='add'>+	case KFD_MQD_TYPE_HIQ:</div><div class='add'>+		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='add'>+		mqd-&gt;allocate_mqd = allocate_hiq_mqd;</div><div class='add'>+		mqd-&gt;init_mqd = init_mqd_hiq;</div><div class='add'>+		mqd-&gt;free_mqd = free_mqd_hiq_sdma;</div><div class='add'>+		mqd-&gt;load_mqd = kfd_hiq_load_mqd_kiq;</div><div class='add'>+		mqd-&gt;update_mqd = update_mqd;</div><div class='add'>+		mqd-&gt;destroy_mqd = kfd_destroy_mqd_cp;</div><div class='add'>+		mqd-&gt;is_occupied = kfd_is_occupied_cp;</div><div class='add'>+		mqd-&gt;mqd_size = sizeof(struct v12_compute_mqd);</div><div class='add'>+		mqd-&gt;mqd_stride = kfd_mqd_stride;</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='add'>+#endif</div><div class='add'>+		mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='add'>+		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='add'>+		break;</div><div class='add'>+	case KFD_MQD_TYPE_DIQ:</div><div class='add'>+		mqd-&gt;allocate_mqd = allocate_mqd;</div><div class='add'>+		mqd-&gt;init_mqd = init_mqd_hiq;</div><div class='add'>+		mqd-&gt;free_mqd = kfd_free_mqd_cp;</div><div class='add'>+		mqd-&gt;load_mqd = load_mqd;</div><div class='add'>+		mqd-&gt;update_mqd = update_mqd;</div><div class='add'>+		mqd-&gt;destroy_mqd = kfd_destroy_mqd_cp;</div><div class='add'>+		mqd-&gt;is_occupied = kfd_is_occupied_cp;</div><div class='add'>+		mqd-&gt;mqd_size = sizeof(struct v12_compute_mqd);</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='add'>+#endif</div><div class='add'>+		break;</div><div class='add'>+	case KFD_MQD_TYPE_SDMA:</div><div class='add'>+		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='add'>+		mqd-&gt;allocate_mqd = allocate_mqd;</div><div class='add'>+		mqd-&gt;init_mqd = init_mqd_sdma;</div><div class='add'>+		mqd-&gt;free_mqd = kfd_free_mqd_cp;</div><div class='add'>+		mqd-&gt;load_mqd = kfd_load_mqd_sdma;</div><div class='add'>+		mqd-&gt;update_mqd = update_mqd_sdma;</div><div class='add'>+		mqd-&gt;destroy_mqd = kfd_destroy_mqd_sdma;</div><div class='add'>+		mqd-&gt;is_occupied = kfd_is_occupied_sdma;</div><div class='add'>+		mqd-&gt;mqd_size = sizeof(struct v12_sdma_mqd);</div><div class='add'>+		mqd-&gt;mqd_stride = kfd_mqd_stride;</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd_sdma;</div><div class='add'>+#endif</div><div class='add'>+		pr_debug("%s@%i\n", __func__, __LINE__);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		kfree(mqd);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return mqd;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c<br/>index 697b6d530d12..f2dee320fada 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c</a></div><div class='hunk'>@@ -77,7 +77,9 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	m-&gt;compute_static_thread_mgmt_se1 = se_mask[1];</div><div class='ctx'> 	m-&gt;compute_static_thread_mgmt_se2 = se_mask[2];</div><div class='ctx'> 	m-&gt;compute_static_thread_mgmt_se3 = se_mask[3];</div><div class='del'>-	if (KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 4, 3)) {</div><div class='add'>+	if (KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+	    KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 4, 4) &amp;&amp;</div><div class='add'>+	    KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 5, 0)) {</div><div class='ctx'> 		m-&gt;compute_static_thread_mgmt_se4 = se_mask[4];</div><div class='ctx'> 		m-&gt;compute_static_thread_mgmt_se5 = se_mask[5];</div><div class='ctx'> 		m-&gt;compute_static_thread_mgmt_se6 = se_mask[6];</div><div class='hunk'>@@ -181,6 +183,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,</div><div class='ctx'> 	m-&gt;cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |</div><div class='ctx'> 			0x53 &lt;&lt; CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;</div><div class='ctx'> </div><div class='add'>+	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;</div><div class='add'>+</div><div class='ctx'> 	m-&gt;cp_mqd_control = 1 &lt;&lt; CP_MQD_CONTROL__PRIV_STATE__SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	m-&gt;cp_mqd_base_addr_lo        = lower_32_bits(addr);</div><div class='hunk'>@@ -243,7 +248,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> </div><div class='ctx'> 	m = get_mqd(mqd);</div><div class='ctx'> </div><div class='del'>-	m-&gt;cp_hqd_pq_control = 5 &lt;&lt; CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;</div><div class='add'>+	m-&gt;cp_hqd_pq_control &amp;= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;</div><div class='ctx'> 	m-&gt;cp_hqd_pq_control |= order_base_2(q-&gt;queue_size / 4) - 1;</div><div class='ctx'> 	pr_debug("cp_hqd_pq_control 0x%x\n", m-&gt;cp_hqd_pq_control);</div><div class='ctx'> </div><div class='hunk'>@@ -299,7 +304,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	if (mm-&gt;dev-&gt;kfd-&gt;cwsr_enabled &amp;&amp; q-&gt;ctx_save_restore_area_address)</div><div class='ctx'> 		m-&gt;cp_hqd_ctx_save_control = 0;</div><div class='ctx'> </div><div class='del'>-	if (KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 4, 3))</div><div class='add'>+	if (KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+	    KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 4, 4) &amp;&amp;</div><div class='add'>+	    KFD_GC_VERSION(mm-&gt;dev) != IP_VERSION(9, 5, 0))</div><div class='ctx'> 		update_cu_mask(mm, mqd, minfo, 0);</div><div class='ctx'> 	set_priority(m, q);</div><div class='ctx'> </div><div class='hunk'>@@ -316,11 +323,14 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static uint32_t read_doorbell_id(void *mqd)</div><div class='add'>+static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)</div><div class='ctx'> {</div><div class='ctx'> 	struct v9_mqd *m = (struct v9_mqd *)mqd;</div><div class='add'>+	uint32_t doorbell_id = m-&gt;queue_doorbell_id0;</div><div class='ctx'> </div><div class='del'>-	return m-&gt;queue_doorbell_id0;</div><div class='add'>+	m-&gt;queue_doorbell_id0 = 0;</div><div class='add'>+</div><div class='add'>+	return kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev, doorbell_id, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int get_wave_state(struct mqd_manager *mm, void *mqd,</div><div class='hunk'>@@ -363,7 +373,7 @@ static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stac</div><div class='ctx'> {</div><div class='ctx'> 	struct v9_mqd *m = get_mqd(mqd);</div><div class='ctx'> </div><div class='del'>-	*ctl_stack_size = m-&gt;cp_hqd_cntl_stack_size;</div><div class='add'>+	*ctl_stack_size = m-&gt;cp_hqd_cntl_stack_size * NUM_XCC(mm-&gt;dev-&gt;xcc_mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)</div><div class='hunk'>@@ -378,6 +388,24 @@ static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, voi</div><div class='ctx'> 	memcpy(ctl_stack_dst, ctl_stack, m-&gt;cp_hqd_cntl_stack_size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void checkpoint_mqd_v9_4_3(struct mqd_manager *mm,</div><div class='add'>+								  void *mqd,</div><div class='add'>+								  void *mqd_dst,</div><div class='add'>+								  void *ctl_stack_dst)</div><div class='add'>+{</div><div class='add'>+	struct v9_mqd *m;</div><div class='add'>+	int xcc;</div><div class='add'>+	uint64_t size = get_mqd(mqd)-&gt;cp_mqd_stride_size;</div><div class='add'>+</div><div class='add'>+	for (xcc = 0; xcc &lt; NUM_XCC(mm-&gt;dev-&gt;xcc_mask); xcc++) {</div><div class='add'>+		m = get_mqd(mqd + size * xcc);</div><div class='add'>+</div><div class='add'>+		checkpoint_mqd(mm, m,</div><div class='add'>+				(uint8_t *)mqd_dst + sizeof(*m) * xcc,</div><div class='add'>+				(uint8_t *)ctl_stack_dst + m-&gt;cp_hqd_cntl_stack_size * xcc);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void restore_mqd(struct mqd_manager *mm, void **mqd,</div><div class='ctx'> 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,</div><div class='ctx'> 			struct queue_properties *qp,</div><div class='hunk'>@@ -485,6 +513,10 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	m-&gt;sdma_engine_id = q-&gt;sdma_engine_id;</div><div class='ctx'> 	m-&gt;sdma_queue_id = q-&gt;sdma_queue_id;</div><div class='ctx'> 	m-&gt;sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;</div><div class='add'>+	/* Allow context switch so we don't cross-process starve with a massive</div><div class='add'>+	 * command buffer of long-running SDMA commands</div><div class='add'>+	 */</div><div class='add'>+	m-&gt;sdmax_rlcx_ib_cntl |= SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK;</div><div class='ctx'> </div><div class='ctx'> 	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='ctx'> }</div><div class='hunk'>@@ -544,6 +576,9 @@ static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd,</div><div class='ctx'> 		m-&gt;cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |</div><div class='ctx'> 					1 &lt;&lt; CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |</div><div class='ctx'> 					1 &lt;&lt; CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;</div><div class='add'>+		if (amdgpu_sriov_multi_vf_mode(mm-&gt;dev-&gt;adev))</div><div class='add'>+			m-&gt;cp_hqd_pq_doorbell_control |= 1 &lt;&lt;</div><div class='add'>+				CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT;</div><div class='ctx'> 		m-&gt;cp_mqd_stride_size = kfd_hiq_mqd_stride(mm-&gt;dev);</div><div class='ctx'> 		if (xcc == 0) {</div><div class='ctx'> 			/* Set no_update_rptr = 0 in Master XCC */</div><div class='hunk'>@@ -607,6 +642,25 @@ static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool check_preemption_failed_v9_4_3(struct mqd_manager *mm, void *mqd)</div><div class='add'>+{</div><div class='add'>+	uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm-&gt;dev);</div><div class='add'>+	uint32_t xcc_mask = mm-&gt;dev-&gt;xcc_mask;</div><div class='add'>+	int inst = 0, xcc_id;</div><div class='add'>+	struct v9_mqd *m;</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	for_each_inst(xcc_id, xcc_mask) {</div><div class='add'>+		m = get_mqd(mqd + hiq_mqd_size * inst);</div><div class='add'>+		ret |= kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev,</div><div class='add'>+					m-&gt;queue_doorbell_id0, inst);</div><div class='add'>+		m-&gt;queue_doorbell_id0 = 0;</div><div class='add'>+		++inst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj,</div><div class='ctx'> 			       struct kfd_mem_obj *xcc_mqd_mem_obj,</div><div class='ctx'> 			       uint64_t offset)</div><div class='hunk'>@@ -635,7 +689,9 @@ static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,</div><div class='ctx'> 		get_xcc_mqd(mqd_mem_obj, &amp;xcc_mqd_mem_obj, offset*xcc);</div><div class='ctx'> </div><div class='ctx'> 		init_mqd(mm, (void **)&amp;m, &amp;xcc_mqd_mem_obj, &amp;xcc_gart_addr, q);</div><div class='del'>-</div><div class='add'>+		if (amdgpu_sriov_multi_vf_mode(mm-&gt;dev-&gt;adev))</div><div class='add'>+				m-&gt;cp_hqd_pq_doorbell_control |= 1 &lt;&lt;</div><div class='add'>+					CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT;</div><div class='ctx'> 		m-&gt;cp_mqd_stride_size = offset;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -695,7 +751,10 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 		m = get_mqd(mqd + size * xcc);</div><div class='ctx'> 		update_mqd(mm, m, q, minfo);</div><div class='ctx'> </div><div class='del'>-		update_cu_mask(mm, mqd, minfo, xcc);</div><div class='add'>+		if (amdgpu_sriov_multi_vf_mode(mm-&gt;dev-&gt;adev))</div><div class='add'>+				m-&gt;cp_hqd_pq_doorbell_control |= 1 &lt;&lt;</div><div class='add'>+					CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT;</div><div class='add'>+		update_cu_mask(mm, m, minfo, xcc);</div><div class='ctx'> </div><div class='ctx'> 		if (q-&gt;format == KFD_QUEUE_FORMAT_AQL) {</div><div class='ctx'> 			switch (xcc) {</div><div class='hunk'>@@ -717,6 +776,43 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,</div><div class='add'>+			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,</div><div class='add'>+			struct queue_properties *qp,</div><div class='add'>+			const void *mqd_src,</div><div class='add'>+			const void *ctl_stack_src, u32 ctl_stack_size)</div><div class='add'>+{</div><div class='add'>+	struct kfd_mem_obj xcc_mqd_mem_obj;</div><div class='add'>+	u32 mqd_ctl_stack_size;</div><div class='add'>+	struct v9_mqd *m;</div><div class='add'>+	u32 num_xcc;</div><div class='add'>+	int xcc;</div><div class='add'>+</div><div class='add'>+	uint64_t offset = mm-&gt;mqd_stride(mm, qp);</div><div class='add'>+</div><div class='add'>+	mm-&gt;dev-&gt;dqm-&gt;current_logical_xcc_start++;</div><div class='add'>+</div><div class='add'>+	num_xcc = NUM_XCC(mm-&gt;dev-&gt;xcc_mask);</div><div class='add'>+	mqd_ctl_stack_size = ctl_stack_size / num_xcc;</div><div class='add'>+</div><div class='add'>+	memset(&amp;xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj));</div><div class='add'>+</div><div class='add'>+	/* Set the MQD pointer and gart address to XCC0 MQD */</div><div class='add'>+	*mqd = mqd_mem_obj-&gt;cpu_ptr;</div><div class='add'>+	if (gart_addr)</div><div class='add'>+		*gart_addr = mqd_mem_obj-&gt;gpu_addr;</div><div class='add'>+</div><div class='add'>+	for (xcc = 0; xcc &lt; num_xcc; xcc++) {</div><div class='add'>+		get_xcc_mqd(mqd_mem_obj, &amp;xcc_mqd_mem_obj, offset * xcc);</div><div class='add'>+		restore_mqd(mm, (void **)&amp;m,</div><div class='add'>+					&amp;xcc_mqd_mem_obj,</div><div class='add'>+					NULL,</div><div class='add'>+					qp,</div><div class='add'>+					(uint8_t *)mqd_src + xcc * sizeof(*m),</div><div class='add'>+					(uint8_t *)ctl_stack_src + xcc *  mqd_ctl_stack_size,</div><div class='add'>+					mqd_ctl_stack_size);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 		   enum kfd_preempt_type type, unsigned int timeout,</div><div class='ctx'> 		   uint32_t pipe_id, uint32_t queue_id)</div><div class='hunk'>@@ -850,25 +946,29 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,</div><div class='ctx'> 		mqd-&gt;free_mqd = kfd_free_mqd_cp;</div><div class='ctx'> 		mqd-&gt;is_occupied = kfd_is_occupied_cp;</div><div class='ctx'> 		mqd-&gt;get_checkpoint_info = get_checkpoint_info;</div><div class='del'>-		mqd-&gt;checkpoint_mqd = checkpoint_mqd;</div><div class='del'>-		mqd-&gt;restore_mqd = restore_mqd;</div><div class='ctx'> 		mqd-&gt;mqd_size = sizeof(struct v9_mqd);</div><div class='ctx'> 		mqd-&gt;mqd_stride = mqd_stride_v9;</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='ctx'> #endif</div><div class='del'>-		if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) {</div><div class='add'>+		if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		    KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+		    KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) {</div><div class='ctx'> 			mqd-&gt;init_mqd = init_mqd_v9_4_3;</div><div class='ctx'> 			mqd-&gt;load_mqd = load_mqd_v9_4_3;</div><div class='ctx'> 			mqd-&gt;update_mqd = update_mqd_v9_4_3;</div><div class='ctx'> 			mqd-&gt;destroy_mqd = destroy_mqd_v9_4_3;</div><div class='ctx'> 			mqd-&gt;get_wave_state = get_wave_state_v9_4_3;</div><div class='add'>+			mqd-&gt;checkpoint_mqd = checkpoint_mqd_v9_4_3;</div><div class='add'>+			mqd-&gt;restore_mqd = restore_mqd_v9_4_3;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			mqd-&gt;init_mqd = init_mqd;</div><div class='ctx'> 			mqd-&gt;load_mqd = load_mqd;</div><div class='ctx'> 			mqd-&gt;update_mqd = update_mqd;</div><div class='ctx'> 			mqd-&gt;destroy_mqd = kfd_destroy_mqd_cp;</div><div class='ctx'> 			mqd-&gt;get_wave_state = get_wave_state;</div><div class='add'>+			mqd-&gt;checkpoint_mqd = checkpoint_mqd;</div><div class='add'>+			mqd-&gt;restore_mqd = restore_mqd;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_MQD_TYPE_HIQ:</div><div class='hunk'>@@ -881,15 +981,19 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='ctx'> #endif</div><div class='del'>-		mqd-&gt;read_doorbell_id = read_doorbell_id;</div><div class='del'>-		if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) {</div><div class='add'>+		mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='add'>+		if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		    KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+		    KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) {</div><div class='ctx'> 			mqd-&gt;init_mqd = init_mqd_hiq_v9_4_3;</div><div class='ctx'> 			mqd-&gt;load_mqd = hiq_load_mqd_kiq_v9_4_3;</div><div class='ctx'> 			mqd-&gt;destroy_mqd = destroy_hiq_mqd_v9_4_3;</div><div class='add'>+			mqd-&gt;check_preemption_failed = check_preemption_failed_v9_4_3;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			mqd-&gt;init_mqd = init_mqd_hiq;</div><div class='ctx'> 			mqd-&gt;load_mqd = kfd_hiq_load_mqd_kiq;</div><div class='ctx'> 			mqd-&gt;destroy_mqd = destroy_hiq_mqd;</div><div class='add'>+			mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_MQD_TYPE_DIQ:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c<br/>index 3e1a574d4ea6..c1fafc502515 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c</a></div><div class='hunk'>@@ -237,11 +237,11 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='ctx'> 	q-&gt;is_active = QUEUE_IS_ACTIVE(*q);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint32_t read_doorbell_id(void *mqd)</div><div class='add'>+static bool check_preemption_failed(struct mqd_manager *mm, void *mqd)</div><div class='ctx'> {</div><div class='ctx'> 	struct vi_mqd *m = (struct vi_mqd *)mqd;</div><div class='ctx'> </div><div class='del'>-	return m-&gt;queue_doorbell_id0;</div><div class='add'>+	return kfd_check_hiq_mqd_doorbell_id(mm-&gt;dev, m-&gt;queue_doorbell_id0, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void update_mqd(struct mqd_manager *mm, void *mqd,</div><div class='hunk'>@@ -482,7 +482,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 		mqd-&gt;debugfs_show_mqd = debugfs_show_mqd;</div><div class='ctx'> #endif</div><div class='del'>-		mqd-&gt;read_doorbell_id = read_doorbell_id;</div><div class='add'>+		mqd-&gt;check_preemption_failed = check_preemption_failed;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_MQD_TYPE_DIQ:</div><div class='ctx'> 		mqd-&gt;allocate_mqd = allocate_mqd;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c<br/>index d6f65f39072b..b1a6eb349bb3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c</a></div><div class='hunk'>@@ -28,6 +28,11 @@</div><div class='ctx'> #include "kfd_kernel_queue.h"</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> </div><div class='add'>+#define OVER_SUBSCRIPTION_PROCESS_COUNT (1 &lt;&lt; 0)</div><div class='add'>+#define OVER_SUBSCRIPTION_COMPUTE_QUEUE_COUNT (1 &lt;&lt; 1)</div><div class='add'>+#define OVER_SUBSCRIPTION_GWS_QUEUE_COUNT (1 &lt;&lt; 2)</div><div class='add'>+#define OVER_SUBSCRIPTION_XNACK_CONFLICT (1 &lt;&lt; 3)</div><div class='add'>+</div><div class='ctx'> static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes,</div><div class='ctx'> 				unsigned int buffer_size_bytes)</div><div class='ctx'> {</div><div class='hunk'>@@ -40,12 +45,14 @@ static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes,</div><div class='ctx'> </div><div class='ctx'> static void pm_calc_rlib_size(struct packet_manager *pm,</div><div class='ctx'> 				unsigned int *rlib_size,</div><div class='del'>-				bool *over_subscription)</div><div class='add'>+				int *over_subscription,</div><div class='add'>+				int xnack_conflict)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int process_count, queue_count, compute_queue_count, gws_queue_count;</div><div class='ctx'> 	unsigned int map_queue_size;</div><div class='ctx'> 	unsigned int max_proc_per_quantum = 1;</div><div class='del'>-	struct kfd_node *dev = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	process_count = pm-&gt;dqm-&gt;processes_count;</div><div class='ctx'> 	queue_count = pm-&gt;dqm-&gt;active_queue_count;</div><div class='hunk'>@@ -57,17 +64,22 @@ static void pm_calc_rlib_size(struct packet_manager *pm,</div><div class='ctx'> 	 * hws_max_conc_proc has been done in</div><div class='ctx'> 	 * kgd2kfd_device_init().</div><div class='ctx'> 	 */</div><div class='del'>-	*over_subscription = false;</div><div class='add'>+	*over_subscription = 0;</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;max_proc_per_quantum &gt; 1)</div><div class='del'>-		max_proc_per_quantum = dev-&gt;max_proc_per_quantum;</div><div class='add'>+	if (node-&gt;max_proc_per_quantum &gt; 1)</div><div class='add'>+		max_proc_per_quantum = node-&gt;max_proc_per_quantum;</div><div class='ctx'> </div><div class='del'>-	if ((process_count &gt; max_proc_per_quantum) ||</div><div class='del'>-	    compute_queue_count &gt; get_cp_queues_num(pm-&gt;dqm) ||</div><div class='del'>-	    gws_queue_count &gt; 1) {</div><div class='del'>-		*over_subscription = true;</div><div class='del'>-		pr_debug("Over subscribed runlist\n");</div><div class='del'>-	}</div><div class='add'>+	if (process_count &gt; max_proc_per_quantum)</div><div class='add'>+		*over_subscription |= OVER_SUBSCRIPTION_PROCESS_COUNT;</div><div class='add'>+	if (compute_queue_count &gt; get_cp_queues_num(pm-&gt;dqm))</div><div class='add'>+		*over_subscription |= OVER_SUBSCRIPTION_COMPUTE_QUEUE_COUNT;</div><div class='add'>+	if (gws_queue_count &gt; 1)</div><div class='add'>+		*over_subscription |= OVER_SUBSCRIPTION_GWS_QUEUE_COUNT;</div><div class='add'>+	if (xnack_conflict &amp;&amp; (node-&gt;adev-&gt;gmc.xnack_flags &amp; AMDGPU_GMC_XNACK_FLAG_CHAIN))</div><div class='add'>+		*over_subscription |= OVER_SUBSCRIPTION_XNACK_CONFLICT;</div><div class='add'>+</div><div class='add'>+	if (*over_subscription)</div><div class='add'>+		dev_dbg(dev, "Over subscribed runlist\n");</div><div class='ctx'> </div><div class='ctx'> 	map_queue_size = pm-&gt;pmf-&gt;map_queues_size;</div><div class='ctx'> 	/* calculate run list ib allocation size */</div><div class='hunk'>@@ -81,29 +93,32 @@ static void pm_calc_rlib_size(struct packet_manager *pm,</div><div class='ctx'> 	if (*over_subscription)</div><div class='ctx'> 		*rlib_size += pm-&gt;pmf-&gt;runlist_size;</div><div class='ctx'> </div><div class='del'>-	pr_debug("runlist ib size %d\n", *rlib_size);</div><div class='add'>+	dev_dbg(dev, "runlist ib size %d\n", *rlib_size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int pm_allocate_runlist_ib(struct packet_manager *pm,</div><div class='ctx'> 				unsigned int **rl_buffer,</div><div class='ctx'> 				uint64_t *rl_gpu_buffer,</div><div class='ctx'> 				unsigned int *rl_buffer_size,</div><div class='del'>-				bool *is_over_subscription)</div><div class='add'>+				int *is_over_subscription,</div><div class='add'>+				int xnack_conflict)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	int retval;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(pm-&gt;allocated))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	pm_calc_rlib_size(pm, rl_buffer_size, is_over_subscription);</div><div class='add'>+	pm_calc_rlib_size(pm, rl_buffer_size, is_over_subscription,</div><div class='add'>+				xnack_conflict);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;pm-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	retval = kfd_gtt_sa_allocate(pm-&gt;dqm-&gt;dev, *rl_buffer_size,</div><div class='del'>-					&amp;pm-&gt;ib_buffer_obj);</div><div class='add'>+	retval = kfd_gtt_sa_allocate(node, *rl_buffer_size, &amp;pm-&gt;ib_buffer_obj);</div><div class='ctx'> </div><div class='ctx'> 	if (retval) {</div><div class='del'>-		pr_err("Failed to allocate runlist IB\n");</div><div class='add'>+		dev_err(dev, "Failed to allocate runlist IB\n");</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -125,32 +140,54 @@ static int pm_create_runlist_ib(struct packet_manager *pm,</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int alloc_size_bytes;</div><div class='ctx'> 	unsigned int *rl_buffer, rl_wptr, i;</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	int retval, processes_mapped;</div><div class='ctx'> 	struct device_process_node *cur;</div><div class='ctx'> 	struct qcm_process_device *qpd;</div><div class='ctx'> 	struct queue *q;</div><div class='ctx'> 	struct kernel_queue *kq;</div><div class='del'>-	bool is_over_subscription;</div><div class='add'>+	int is_over_subscription;</div><div class='add'>+	int xnack_enabled = -1;</div><div class='add'>+	bool xnack_conflict = 0;</div><div class='ctx'> </div><div class='ctx'> 	rl_wptr = retval = processes_mapped = 0;</div><div class='ctx'> </div><div class='add'>+	/* Check if processes set different xnack modes */</div><div class='add'>+	list_for_each_entry(cur, queues, list) {</div><div class='add'>+		qpd = cur-&gt;qpd;</div><div class='add'>+		if (xnack_enabled &lt; 0)</div><div class='add'>+			/* First process */</div><div class='add'>+			xnack_enabled = qpd-&gt;pqm-&gt;process-&gt;xnack_enabled;</div><div class='add'>+		else if (qpd-&gt;pqm-&gt;process-&gt;xnack_enabled != xnack_enabled) {</div><div class='add'>+			/* Found a process with a different xnack mode */</div><div class='add'>+			xnack_conflict = 1;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	retval = pm_allocate_runlist_ib(pm, &amp;rl_buffer, rl_gpu_addr,</div><div class='del'>-				&amp;alloc_size_bytes, &amp;is_over_subscription);</div><div class='add'>+				&amp;alloc_size_bytes, &amp;is_over_subscription,</div><div class='add'>+				xnack_conflict);</div><div class='ctx'> 	if (retval)</div><div class='ctx'> 		return retval;</div><div class='ctx'> </div><div class='ctx'> 	*rl_size_bytes = alloc_size_bytes;</div><div class='ctx'> 	pm-&gt;ib_size_bytes = alloc_size_bytes;</div><div class='ctx'> </div><div class='del'>-	pr_debug("Building runlist ib process count: %d queues count %d\n",</div><div class='add'>+	dev_dbg(dev, "Building runlist ib process count: %d queues count %d\n",</div><div class='ctx'> 		pm-&gt;dqm-&gt;processes_count, pm-&gt;dqm-&gt;active_queue_count);</div><div class='ctx'> </div><div class='add'>+build_runlist_ib:</div><div class='ctx'> 	/* build the run list ib packet */</div><div class='ctx'> 	list_for_each_entry(cur, queues, list) {</div><div class='ctx'> 		qpd = cur-&gt;qpd;</div><div class='add'>+		/* group processes with the same xnack mode together */</div><div class='add'>+		if (qpd-&gt;pqm-&gt;process-&gt;xnack_enabled != xnack_enabled)</div><div class='add'>+			continue;</div><div class='ctx'> 		/* build map process packet */</div><div class='ctx'> 		if (processes_mapped &gt;= pm-&gt;dqm-&gt;processes_count) {</div><div class='del'>-			pr_debug("Not enough space left in runlist IB\n");</div><div class='add'>+			dev_dbg(dev, "Not enough space left in runlist IB\n");</div><div class='ctx'> 			pm_release_ib(pm);</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -167,7 +204,8 @@ static int pm_create_runlist_ib(struct packet_manager *pm,</div><div class='ctx'> 			if (!kq-&gt;queue-&gt;properties.is_active)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			pr_debug("static_queue, mapping kernel q %d, is debug status %d\n",</div><div class='add'>+			dev_dbg(dev,</div><div class='add'>+				"static_queue, mapping kernel q %d, is debug status %d\n",</div><div class='ctx'> 				kq-&gt;queue-&gt;queue, qpd-&gt;is_debug);</div><div class='ctx'> </div><div class='ctx'> 			retval = pm-&gt;pmf-&gt;map_queues(pm,</div><div class='hunk'>@@ -186,7 +224,8 @@ static int pm_create_runlist_ib(struct packet_manager *pm,</div><div class='ctx'> 			if (!q-&gt;properties.is_active)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			pr_debug("static_queue, mapping user queue %d, is debug status %d\n",</div><div class='add'>+			dev_dbg(dev,</div><div class='add'>+				"static_queue, mapping user queue %d, is debug status %d\n",</div><div class='ctx'> 				q-&gt;queue, qpd-&gt;is_debug);</div><div class='ctx'> </div><div class='ctx'> 			retval = pm-&gt;pmf-&gt;map_queues(pm,</div><div class='hunk'>@@ -202,18 +241,33 @@ static int pm_create_runlist_ib(struct packet_manager *pm,</div><div class='ctx'> 				alloc_size_bytes);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	if (xnack_conflict) {</div><div class='add'>+		/* pick up processes with the other xnack mode */</div><div class='add'>+		xnack_enabled = !xnack_enabled;</div><div class='add'>+		xnack_conflict = 0;</div><div class='add'>+		goto build_runlist_ib;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	pr_debug("Finished map process and queues to runlist\n");</div><div class='add'>+	dev_dbg(dev, "Finished map process and queues to runlist\n");</div><div class='ctx'> </div><div class='ctx'> 	if (is_over_subscription) {</div><div class='ctx'> 		if (!pm-&gt;is_over_subscription)</div><div class='del'>-			pr_warn("Runlist is getting oversubscribed. Expect reduced ROCm performance.\n");</div><div class='add'>+			dev_warn(dev, "Runlist is getting oversubscribed due to%s%s%s%s. Expect reduced ROCm performance.\n",</div><div class='add'>+				is_over_subscription &amp; OVER_SUBSCRIPTION_PROCESS_COUNT ?</div><div class='add'>+				" too many processes" : "",</div><div class='add'>+				is_over_subscription &amp; OVER_SUBSCRIPTION_COMPUTE_QUEUE_COUNT ?</div><div class='add'>+				" too many queues" : "",</div><div class='add'>+				is_over_subscription &amp; OVER_SUBSCRIPTION_GWS_QUEUE_COUNT ?</div><div class='add'>+				" multiple processes using cooperative launch" : "",</div><div class='add'>+				is_over_subscription &amp; OVER_SUBSCRIPTION_XNACK_CONFLICT ?</div><div class='add'>+				" xnack on/off processes mixed on gfx9" : "");</div><div class='add'>+</div><div class='ctx'> 		retval = pm-&gt;pmf-&gt;runlist(pm, &amp;rl_buffer[rl_wptr],</div><div class='ctx'> 					*rl_gpu_addr,</div><div class='ctx'> 					alloc_size_bytes / sizeof(uint32_t),</div><div class='ctx'> 					true);</div><div class='ctx'> 	}</div><div class='del'>-	pm-&gt;is_over_subscription = is_over_subscription;</div><div class='add'>+	pm-&gt;is_over_subscription = !!is_over_subscription;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; alloc_size_bytes / sizeof(uint32_t); i++)</div><div class='ctx'> 		pr_debug("0x%2X ", rl_buffer[i]);</div><div class='hunk'>@@ -239,7 +293,9 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		if (KFD_GC_VERSION(dqm-&gt;dev) == IP_VERSION(9, 4, 2) ||</div><div class='del'>-		    KFD_GC_VERSION(dqm-&gt;dev) == IP_VERSION(9, 4, 3))</div><div class='add'>+		    KFD_GC_VERSION(dqm-&gt;dev) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		    KFD_GC_VERSION(dqm-&gt;dev) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+		    KFD_GC_VERSION(dqm-&gt;dev) == IP_VERSION(9, 5, 0))</div><div class='ctx'> 			pm-&gt;pmf = &amp;kfd_aldebaran_pm_funcs;</div><div class='ctx'> 		else if (KFD_GC_VERSION(dqm-&gt;dev) &gt;= IP_VERSION(9, 0, 1))</div><div class='ctx'> 			pm-&gt;pmf = &amp;kfd_v9_pm_funcs;</div><div class='hunk'>@@ -262,16 +318,18 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void pm_uninit(struct packet_manager *pm, bool hanging)</div><div class='add'>+void pm_uninit(struct packet_manager *pm)</div><div class='ctx'> {</div><div class='ctx'> 	mutex_destroy(&amp;pm-&gt;lock);</div><div class='del'>-	kernel_queue_uninit(pm-&gt;priv_queue, hanging);</div><div class='add'>+	kernel_queue_uninit(pm-&gt;priv_queue);</div><div class='ctx'> 	pm-&gt;priv_queue = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int pm_send_set_resources(struct packet_manager *pm,</div><div class='ctx'> 				struct scheduling_resources *res)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	uint32_t *buffer, size;</div><div class='ctx'> 	int retval = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -281,7 +339,7 @@ int pm_send_set_resources(struct packet_manager *pm,</div><div class='ctx'> 					size / sizeof(uint32_t),</div><div class='ctx'> 					(unsigned int **)&amp;buffer);</div><div class='ctx'> 	if (!buffer) {</div><div class='del'>-		pr_err("Failed to allocate buffer on kernel queue\n");</div><div class='add'>+		dev_err(dev, "Failed to allocate buffer on kernel queue\n");</div><div class='ctx'> 		retval = -ENOMEM;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -343,6 +401,8 @@ fail_create_runlist_ib:</div><div class='ctx'> int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,</div><div class='ctx'> 			uint64_t fence_value)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	uint32_t *buffer, size;</div><div class='ctx'> 	int retval = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -354,7 +414,7 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,</div><div class='ctx'> 	kq_acquire_packet_buffer(pm-&gt;priv_queue,</div><div class='ctx'> 			size / sizeof(uint32_t), (unsigned int **)&amp;buffer);</div><div class='ctx'> 	if (!buffer) {</div><div class='del'>-		pr_err("Failed to allocate buffer on kernel queue\n");</div><div class='add'>+		dev_err(dev, "Failed to allocate buffer on kernel queue\n");</div><div class='ctx'> 		retval = -ENOMEM;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -370,12 +430,33 @@ out:</div><div class='ctx'> 	return retval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period)</div><div class='add'>+/* pm_config_dequeue_wait_counts: Configure dequeue timer Wait Counts</div><div class='add'>+ *  by writing to CP_IQ_WAIT_TIME2 registers.</div><div class='add'>+ *</div><div class='add'>+ *  @cmd: See emum kfd_config_dequeue_wait_counts_cmd definition</div><div class='add'>+ *  @value: Depends on the cmd. This parameter is unused for</div><div class='add'>+ *    KFD_DEQUEUE_WAIT_INIT and KFD_DEQUEUE_WAIT_RESET. For</div><div class='add'>+ *    KFD_DEQUEUE_WAIT_SET_SCH_WAVE it holds value to be set</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+int pm_config_dequeue_wait_counts(struct packet_manager *pm,</div><div class='add'>+		enum kfd_config_dequeue_wait_counts_cmd cmd,</div><div class='add'>+		uint32_t value)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	int retval = 0;</div><div class='ctx'> 	uint32_t *buffer, size;</div><div class='ctx'> </div><div class='del'>-	size = pm-&gt;pmf-&gt;set_grace_period_size;</div><div class='add'>+	if (!pm-&gt;pmf-&gt;config_dequeue_wait_counts ||</div><div class='add'>+	    !pm-&gt;pmf-&gt;config_dequeue_wait_counts_size)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (cmd == KFD_DEQUEUE_WAIT_INIT &amp;&amp; (KFD_GC_VERSION(pm-&gt;dqm-&gt;dev) &lt; IP_VERSION(9, 4, 1) ||</div><div class='add'>+	   KFD_GC_VERSION(pm-&gt;dqm-&gt;dev) &gt;= IP_VERSION(10, 0, 0)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	size = pm-&gt;pmf-&gt;config_dequeue_wait_counts_size;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;pm-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -385,18 +466,24 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period)</div><div class='ctx'> 			(unsigned int **)&amp;buffer);</div><div class='ctx'> </div><div class='ctx'> 		if (!buffer) {</div><div class='del'>-			pr_err("Failed to allocate buffer on kernel queue\n");</div><div class='add'>+			dev_err(dev,</div><div class='add'>+				"Failed to allocate buffer on kernel queue\n");</div><div class='ctx'> 			retval = -ENOMEM;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		retval = pm-&gt;pmf-&gt;set_grace_period(pm, buffer, grace_period);</div><div class='del'>-		if (!retval)</div><div class='add'>+		retval = pm-&gt;pmf-&gt;config_dequeue_wait_counts(pm, buffer,</div><div class='add'>+							     cmd, value);</div><div class='add'>+		if (!retval) {</div><div class='ctx'> 			retval = kq_submit_packet(pm-&gt;priv_queue);</div><div class='del'>-		else</div><div class='add'>+</div><div class='add'>+			/* If default value is modified, cache that in dqm-&gt;wait_times */</div><div class='add'>+			if (!retval &amp;&amp; cmd == KFD_DEQUEUE_WAIT_INIT)</div><div class='add'>+				update_dqm_wait_times(pm-&gt;dqm);</div><div class='add'>+		} else {</div><div class='ctx'> 			kq_rollback_packet(pm-&gt;priv_queue);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;pm-&gt;lock);</div><div class='ctx'> 	return retval;</div><div class='hunk'>@@ -406,6 +493,8 @@ int pm_send_unmap_queue(struct packet_manager *pm,</div><div class='ctx'> 			enum kfd_unmap_queues_filter filter,</div><div class='ctx'> 			uint32_t filter_param, bool reset)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	uint32_t *buffer, size;</div><div class='ctx'> 	int retval = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -414,7 +503,7 @@ int pm_send_unmap_queue(struct packet_manager *pm,</div><div class='ctx'> 	kq_acquire_packet_buffer(pm-&gt;priv_queue,</div><div class='ctx'> 			size / sizeof(uint32_t), (unsigned int **)&amp;buffer);</div><div class='ctx'> 	if (!buffer) {</div><div class='del'>-		pr_err("Failed to allocate buffer on kernel queue\n");</div><div class='add'>+		dev_err(dev, "Failed to allocate buffer on kernel queue\n");</div><div class='ctx'> 		retval = -ENOMEM;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -463,6 +552,8 @@ out:</div><div class='ctx'> </div><div class='ctx'> int pm_debugfs_hang_hws(struct packet_manager *pm)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_node *node = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct device *dev = node-&gt;adev-&gt;dev;</div><div class='ctx'> 	uint32_t *buffer, size;</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -474,16 +565,16 @@ int pm_debugfs_hang_hws(struct packet_manager *pm)</div><div class='ctx'> 	kq_acquire_packet_buffer(pm-&gt;priv_queue,</div><div class='ctx'> 			size / sizeof(uint32_t), (unsigned int **)&amp;buffer);</div><div class='ctx'> 	if (!buffer) {</div><div class='del'>-		pr_err("Failed to allocate buffer on kernel queue\n");</div><div class='add'>+		dev_err(dev, "Failed to allocate buffer on kernel queue\n");</div><div class='ctx'> 		r = -ENOMEM;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> 	memset(buffer, 0x55, size);</div><div class='ctx'> 	kq_submit_packet(pm-&gt;priv_queue);</div><div class='ctx'> </div><div class='del'>-	pr_info("Submitting %x %x %x %x %x %x %x to HIQ to hang the HWS.",</div><div class='del'>-		buffer[0], buffer[1], buffer[2], buffer[3],</div><div class='del'>-		buffer[4], buffer[5], buffer[6]);</div><div class='add'>+	dev_info(dev, "Submitting %x %x %x %x %x %x %x to HIQ to hang the HWS.",</div><div class='add'>+		 buffer[0], buffer[1], buffer[2], buffer[3], buffer[4],</div><div class='add'>+		 buffer[5], buffer[6]);</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;pm-&gt;lock);</div><div class='ctx'> 	return r;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c<br/>index 8ee2bedd301a..505036968a77 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c</a></div><div class='hunk'>@@ -37,14 +37,17 @@ static int pm_map_process_v9(struct packet_manager *pm,</div><div class='ctx'> 	struct kfd_node *kfd = pm-&gt;dqm-&gt;dev;</div><div class='ctx'> 	struct kfd_process_device *pdd =</div><div class='ctx'> 			container_of(qpd, struct kfd_process_device, qpd);</div><div class='add'>+	struct amdgpu_device *adev = kfd-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	packet = (struct pm4_mes_map_process *)buffer;</div><div class='ctx'> 	memset(buffer, 0, sizeof(struct pm4_mes_map_process));</div><div class='ctx'> 	packet-&gt;header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,</div><div class='ctx'> 					sizeof(struct pm4_mes_map_process));</div><div class='add'>+	if (adev-&gt;enforce_isolation[kfd-&gt;node_id] == AMDGPU_ENFORCE_ISOLATION_ENABLE)</div><div class='add'>+		packet-&gt;bitfields2.exec_cleaner_shader = 1;</div><div class='ctx'> 	packet-&gt;bitfields2.diq_enable = (qpd-&gt;is_debug) ? 1 : 0;</div><div class='ctx'> 	packet-&gt;bitfields2.process_quantum = 10;</div><div class='del'>-	packet-&gt;bitfields2.pasid = qpd-&gt;pqm-&gt;process-&gt;pasid;</div><div class='add'>+	packet-&gt;bitfields2.pasid = pdd-&gt;pasid;</div><div class='ctx'> 	packet-&gt;bitfields14.gds_size = qpd-&gt;gds_size &amp; 0x3F;</div><div class='ctx'> 	packet-&gt;bitfields14.gds_size_hi = (qpd-&gt;gds_size &gt;&gt; 6) &amp; 0xF;</div><div class='ctx'> 	packet-&gt;bitfields14.num_gws = (qpd-&gt;mapped_gws_queue) ? qpd-&gt;num_gws : 0;</div><div class='hunk'>@@ -89,17 +92,22 @@ static int pm_map_process_aldebaran(struct packet_manager *pm,</div><div class='ctx'> 	struct pm4_mes_map_process_aldebaran *packet;</div><div class='ctx'> 	uint64_t vm_page_table_base_addr = qpd-&gt;page_table_base;</div><div class='ctx'> 	struct kfd_dev *kfd = pm-&gt;dqm-&gt;dev-&gt;kfd;</div><div class='add'>+	struct kfd_node *knode = pm-&gt;dqm-&gt;dev;</div><div class='ctx'> 	struct kfd_process_device *pdd =</div><div class='ctx'> 			container_of(qpd, struct kfd_process_device, qpd);</div><div class='ctx'> 	int i;</div><div class='add'>+	struct amdgpu_device *adev = kfd-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	packet = (struct pm4_mes_map_process_aldebaran *)buffer;</div><div class='ctx'> 	memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran));</div><div class='ctx'> 	packet-&gt;header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,</div><div class='ctx'> 			sizeof(struct pm4_mes_map_process_aldebaran));</div><div class='add'>+	if (adev-&gt;enforce_isolation[knode-&gt;node_id] ==</div><div class='add'>+	    AMDGPU_ENFORCE_ISOLATION_ENABLE)</div><div class='add'>+		packet-&gt;bitfields2.exec_cleaner_shader = 1;</div><div class='ctx'> 	packet-&gt;bitfields2.diq_enable = (qpd-&gt;is_debug) ? 1 : 0;</div><div class='ctx'> 	packet-&gt;bitfields2.process_quantum = 10;</div><div class='del'>-	packet-&gt;bitfields2.pasid = qpd-&gt;pqm-&gt;process-&gt;pasid;</div><div class='add'>+	packet-&gt;bitfields2.pasid = pdd-&gt;pasid;</div><div class='ctx'> 	packet-&gt;bitfields14.gds_size = qpd-&gt;gds_size &amp; 0x3F;</div><div class='ctx'> 	packet-&gt;bitfields14.gds_size_hi = (qpd-&gt;gds_size &gt;&gt; 6) &amp; 0xF;</div><div class='ctx'> 	packet-&gt;bitfields14.num_gws = (qpd-&gt;mapped_gws_queue) ? qpd-&gt;num_gws : 0;</div><div class='hunk'>@@ -144,18 +152,23 @@ static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> </div><div class='ctx'> 	int concurrent_proc_cnt = 0;</div><div class='ctx'> 	struct kfd_node *kfd = pm-&gt;dqm-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = kfd-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* Determine the number of processes to map together to HW:</div><div class='ctx'> 	 * it can not exceed the number of VMIDs available to the</div><div class='ctx'> 	 * scheduler, and it is determined by the smaller of the number</div><div class='ctx'> 	 * of processes in the runlist and kfd module parameter</div><div class='ctx'> 	 * hws_max_conc_proc.</div><div class='add'>+	 * However, if enforce_isolation is set (toggle LDS/VGPRs/SGPRs</div><div class='add'>+	 * cleaner between process switch), enable single-process mode</div><div class='add'>+	 * in HWS.</div><div class='ctx'> 	 * Note: the arbitration between the number of VMIDs and</div><div class='ctx'> 	 * hws_max_conc_proc has been done in</div><div class='ctx'> 	 * kgd2kfd_device_init().</div><div class='ctx'> 	 */</div><div class='del'>-	concurrent_proc_cnt = min(pm-&gt;dqm-&gt;processes_count,</div><div class='del'>-			kfd-&gt;max_proc_per_quantum);</div><div class='add'>+	concurrent_proc_cnt = (adev-&gt;enforce_isolation[kfd-&gt;node_id] ==</div><div class='add'>+			       AMDGPU_ENFORCE_ISOLATION_ENABLE) ?</div><div class='add'>+		1 : min(pm-&gt;dqm-&gt;processes_count, kfd-&gt;max_proc_per_quantum);</div><div class='ctx'> </div><div class='ctx'> 	packet = (struct pm4_mes_runlist *)buffer;</div><div class='ctx'> </div><div class='hunk'>@@ -190,6 +203,8 @@ static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 			queue_type__mes_set_resources__hsa_interface_queue_hiq;</div><div class='ctx'> 	packet-&gt;bitfields2.vmid_mask = res-&gt;vmid_mask;</div><div class='ctx'> 	packet-&gt;bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;</div><div class='add'>+	if (pm-&gt;dqm-&gt;dev-&gt;adev-&gt;gmc.xnack_flags &amp; AMDGPU_GMC_XNACK_FLAG_CHAIN)</div><div class='add'>+		packet-&gt;bitfields2.enb_xnack_retry_disable_check = 1;</div><div class='ctx'> 	packet-&gt;bitfields7.oac_mask = res-&gt;oac_mask;</div><div class='ctx'> 	packet-&gt;bitfields8.gds_heap_base = res-&gt;gds_heap_base;</div><div class='ctx'> 	packet-&gt;bitfields8.gds_heap_size = res-&gt;gds_heap_size;</div><div class='hunk'>@@ -213,7 +228,6 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 		struct queue *q, bool is_static)</div><div class='ctx'> {</div><div class='ctx'> 	struct pm4_mes_map_queues *packet;</div><div class='del'>-	bool use_static = is_static;</div><div class='ctx'> </div><div class='ctx'> 	packet = (struct pm4_mes_map_queues *)buffer;</div><div class='ctx'> 	memset(buffer, 0, sizeof(struct pm4_mes_map_queues));</div><div class='hunk'>@@ -226,7 +240,7 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> </div><div class='ctx'> 	packet-&gt;bitfields2.engine_sel =</div><div class='ctx'> 		engine_sel__mes_map_queues__compute_vi;</div><div class='del'>-	packet-&gt;bitfields2.gws_control_queue = q-&gt;gws ? 1 : 0;</div><div class='add'>+	packet-&gt;bitfields2.gws_control_queue = q-&gt;properties.is_gws ? 1 : 0;</div><div class='ctx'> 	packet-&gt;bitfields2.extended_engine_sel =</div><div class='ctx'> 		extended_engine_sel__mes_map_queues__legacy_engine_sel;</div><div class='ctx'> 	packet-&gt;bitfields2.queue_type =</div><div class='hunk'>@@ -234,7 +248,7 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> </div><div class='ctx'> 	switch (q-&gt;properties.type) {</div><div class='ctx'> 	case KFD_QUEUE_TYPE_COMPUTE:</div><div class='del'>-		if (use_static)</div><div class='add'>+		if (is_static)</div><div class='ctx'> 			packet-&gt;bitfields2.queue_type =</div><div class='ctx'> 		queue_type__mes_map_queues__normal_latency_static_queue_vi;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -244,7 +258,6 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case KFD_QUEUE_TYPE_SDMA:</div><div class='ctx'> 	case KFD_QUEUE_TYPE_SDMA_XGMI:</div><div class='del'>-		use_static = false; /* no static queues under SDMA */</div><div class='ctx'> 		if (q-&gt;properties.sdma_engine_id &lt; 2 &amp;&amp;</div><div class='ctx'> 		    !pm_use_ext_eng(q-&gt;device-&gt;kfd))</div><div class='ctx'> 			packet-&gt;bitfields2.engine_sel = q-&gt;properties.sdma_engine_id +</div><div class='hunk'>@@ -287,23 +300,79 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pm_set_grace_period_v9(struct packet_manager *pm,</div><div class='add'>+static inline void pm_build_dequeue_wait_counts_packet_info(struct packet_manager *pm,</div><div class='add'>+			uint32_t sch_value, uint32_t que_sleep, uint32_t *reg_offset,</div><div class='add'>+			uint32_t *reg_data)</div><div class='add'>+{</div><div class='add'>+	pm-&gt;dqm-&gt;dev-&gt;kfd2kgd-&gt;build_dequeue_wait_counts_packet_info(</div><div class='add'>+		pm-&gt;dqm-&gt;dev-&gt;adev,</div><div class='add'>+		pm-&gt;dqm-&gt;wait_times,</div><div class='add'>+		sch_value,</div><div class='add'>+		que_sleep,</div><div class='add'>+		reg_offset,</div><div class='add'>+		reg_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* pm_config_dequeue_wait_counts_v9: Builds WRITE_DATA packet with</div><div class='add'>+ *    register/value for configuring dequeue wait counts</div><div class='add'>+ *</div><div class='add'>+ * @return: -ve for failure and 0 for success and buffer is</div><div class='add'>+ *  filled in with packet</div><div class='add'>+ *</div><div class='add'>+ **/</div><div class='add'>+static int pm_config_dequeue_wait_counts_v9(struct packet_manager *pm,</div><div class='ctx'> 		uint32_t *buffer,</div><div class='del'>-		uint32_t grace_period)</div><div class='add'>+		enum kfd_config_dequeue_wait_counts_cmd cmd,</div><div class='add'>+		uint32_t value)</div><div class='ctx'> {</div><div class='ctx'> 	struct pm4_mec_write_data_mmio *packet;</div><div class='ctx'> 	uint32_t reg_offset = 0;</div><div class='ctx'> 	uint32_t reg_data = 0;</div><div class='ctx'> </div><div class='del'>-	pm-&gt;dqm-&gt;dev-&gt;kfd2kgd-&gt;build_grace_period_packet_info(</div><div class='del'>-			pm-&gt;dqm-&gt;dev-&gt;adev,</div><div class='del'>-			pm-&gt;dqm-&gt;wait_times,</div><div class='del'>-			grace_period,</div><div class='del'>-			&amp;reg_offset,</div><div class='del'>-			&amp;reg_data);</div><div class='add'>+	switch (cmd) {</div><div class='add'>+	case KFD_DEQUEUE_WAIT_INIT: {</div><div class='add'>+		uint32_t sch_wave = 0, que_sleep = 1;</div><div class='add'>+</div><div class='add'>+		/* For all gfx9 ASICs &gt; gfx941,</div><div class='add'>+		 * Reduce CP_IQ_WAIT_TIME2.QUE_SLEEP to 0x1 from default 0x40.</div><div class='add'>+		 * On a 1GHz machine this is roughly 1 microsecond, which is</div><div class='add'>+		 * about how long it takes to load data out of memory during</div><div class='add'>+		 * queue connect</div><div class='add'>+		 * QUE_SLEEP: Wait Count for Dequeue Retry.</div><div class='add'>+		 *</div><div class='add'>+		 * Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU</div><div class='add'>+		 */</div><div class='add'>+		if (KFD_GC_VERSION(pm-&gt;dqm-&gt;dev) &lt; IP_VERSION(9, 4, 1) ||</div><div class='add'>+		    KFD_GC_VERSION(pm-&gt;dqm-&gt;dev) &gt;= IP_VERSION(10, 0, 0))</div><div class='add'>+			return -EPERM;</div><div class='add'>+</div><div class='add'>+		if (amdgpu_emu_mode == 0 &amp;&amp; pm-&gt;dqm-&gt;dev-&gt;adev-&gt;gmc.is_app_apu &amp;&amp;</div><div class='add'>+		    (KFD_GC_VERSION(pm-&gt;dqm-&gt;dev) == IP_VERSION(9, 4, 3)))</div><div class='add'>+			sch_wave = 1;</div><div class='ctx'> </div><div class='del'>-	if (grace_period == USE_DEFAULT_GRACE_PERIOD)</div><div class='del'>-		reg_data = pm-&gt;dqm-&gt;wait_times;</div><div class='add'>+		pm_build_dequeue_wait_counts_packet_info(pm, sch_wave, que_sleep,</div><div class='add'>+			&amp;reg_offset, &amp;reg_data);</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case KFD_DEQUEUE_WAIT_RESET:</div><div class='add'>+		/* reg_data would be set to dqm-&gt;wait_times */</div><div class='add'>+		pm_build_dequeue_wait_counts_packet_info(pm, 0, 0, &amp;reg_offset, &amp;reg_data);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case KFD_DEQUEUE_WAIT_SET_SCH_WAVE:</div><div class='add'>+		/* The CP cannot handle value 0 and it will result in</div><div class='add'>+		 * an infinite grace period being set so set to 1 to prevent this. Also</div><div class='add'>+		 * avoid debugger API breakage as it sets 0 and expects a low value.</div><div class='add'>+		 */</div><div class='add'>+		if (!value)</div><div class='add'>+			value = 1;</div><div class='add'>+		pm_build_dequeue_wait_counts_packet_info(pm, value, 0, &amp;reg_offset, &amp;reg_data);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		pr_err("Invalid dequeue wait cmd\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	packet = (struct pm4_mec_write_data_mmio *)buffer;</div><div class='ctx'> 	memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio));</div><div class='hunk'>@@ -405,7 +474,7 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {</div><div class='ctx'> 	.set_resources		= pm_set_resources_v9,</div><div class='ctx'> 	.map_queues		= pm_map_queues_v9,</div><div class='ctx'> 	.unmap_queues		= pm_unmap_queues_v9,</div><div class='del'>-	.set_grace_period       = pm_set_grace_period_v9,</div><div class='add'>+	.config_dequeue_wait_counts = pm_config_dequeue_wait_counts_v9,</div><div class='ctx'> 	.query_status		= pm_query_status_v9,</div><div class='ctx'> 	.release_mem		= NULL,</div><div class='ctx'> 	.map_process_size	= sizeof(struct pm4_mes_map_process),</div><div class='hunk'>@@ -413,7 +482,7 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {</div><div class='ctx'> 	.set_resources_size	= sizeof(struct pm4_mes_set_resources),</div><div class='ctx'> 	.map_queues_size	= sizeof(struct pm4_mes_map_queues),</div><div class='ctx'> 	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),</div><div class='del'>-	.set_grace_period_size  = sizeof(struct pm4_mec_write_data_mmio),</div><div class='add'>+	.config_dequeue_wait_counts_size  = sizeof(struct pm4_mec_write_data_mmio),</div><div class='ctx'> 	.query_status_size	= sizeof(struct pm4_mes_query_status),</div><div class='ctx'> 	.release_mem_size	= 0,</div><div class='ctx'> };</div><div class='hunk'>@@ -424,7 +493,7 @@ const struct packet_manager_funcs kfd_aldebaran_pm_funcs = {</div><div class='ctx'> 	.set_resources		= pm_set_resources_v9,</div><div class='ctx'> 	.map_queues		= pm_map_queues_v9,</div><div class='ctx'> 	.unmap_queues		= pm_unmap_queues_v9,</div><div class='del'>-	.set_grace_period       = pm_set_grace_period_v9,</div><div class='add'>+	.config_dequeue_wait_counts = pm_config_dequeue_wait_counts_v9,</div><div class='ctx'> 	.query_status		= pm_query_status_v9,</div><div class='ctx'> 	.release_mem		= NULL,</div><div class='ctx'> 	.map_process_size	= sizeof(struct pm4_mes_map_process_aldebaran),</div><div class='hunk'>@@ -432,7 +501,7 @@ const struct packet_manager_funcs kfd_aldebaran_pm_funcs = {</div><div class='ctx'> 	.set_resources_size	= sizeof(struct pm4_mes_set_resources),</div><div class='ctx'> 	.map_queues_size	= sizeof(struct pm4_mes_map_queues),</div><div class='ctx'> 	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),</div><div class='del'>-	.set_grace_period_size  = sizeof(struct pm4_mec_write_data_mmio),</div><div class='add'>+	.config_dequeue_wait_counts_size  = sizeof(struct pm4_mec_write_data_mmio),</div><div class='ctx'> 	.query_status_size	= sizeof(struct pm4_mes_query_status),</div><div class='ctx'> 	.release_mem_size	= 0,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c<br/>index c1199d06d131..a1de5d7e173a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c</a></div><div class='hunk'>@@ -42,6 +42,7 @@ unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size)</div><div class='ctx'> static int pm_map_process_vi(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 				struct qcm_process_device *qpd)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_process_device *pdd = qpd_to_pdd(qpd);</div><div class='ctx'> 	struct pm4_mes_map_process *packet;</div><div class='ctx'> </div><div class='ctx'> 	packet = (struct pm4_mes_map_process *)buffer;</div><div class='hunk'>@@ -52,7 +53,7 @@ static int pm_map_process_vi(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 					sizeof(struct pm4_mes_map_process));</div><div class='ctx'> 	packet-&gt;bitfields2.diq_enable = (qpd-&gt;is_debug) ? 1 : 0;</div><div class='ctx'> 	packet-&gt;bitfields2.process_quantum = 10;</div><div class='del'>-	packet-&gt;bitfields2.pasid = qpd-&gt;pqm-&gt;process-&gt;pasid;</div><div class='add'>+	packet-&gt;bitfields2.pasid = pdd-&gt;pasid;</div><div class='ctx'> 	packet-&gt;bitfields3.page_table_base = qpd-&gt;page_table_base;</div><div class='ctx'> 	packet-&gt;bitfields10.gds_size = qpd-&gt;gds_size;</div><div class='ctx'> 	packet-&gt;bitfields10.num_gws = qpd-&gt;num_gws;</div><div class='hunk'>@@ -303,7 +304,7 @@ const struct packet_manager_funcs kfd_vi_pm_funcs = {</div><div class='ctx'> 	.set_resources		= pm_set_resources_vi,</div><div class='ctx'> 	.map_queues		= pm_map_queues_vi,</div><div class='ctx'> 	.unmap_queues		= pm_unmap_queues_vi,</div><div class='del'>-	.set_grace_period	= NULL,</div><div class='add'>+	.config_dequeue_wait_counts	= NULL,</div><div class='ctx'> 	.query_status		= pm_query_status_vi,</div><div class='ctx'> 	.release_mem		= pm_release_mem_vi,</div><div class='ctx'> 	.map_process_size	= sizeof(struct pm4_mes_map_process),</div><div class='hunk'>@@ -311,7 +312,7 @@ const struct packet_manager_funcs kfd_vi_pm_funcs = {</div><div class='ctx'> 	.set_resources_size	= sizeof(struct pm4_mes_set_resources),</div><div class='ctx'> 	.map_queues_size	= sizeof(struct pm4_mes_map_queues),</div><div class='ctx'> 	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),</div><div class='del'>-	.set_grace_period_size	= 0,</div><div class='add'>+	.config_dequeue_wait_counts_size	= 0,</div><div class='ctx'> 	.query_status_size	= sizeof(struct pm4_mes_query_status),</div><div class='ctx'> 	.release_mem_size	= sizeof(struct pm4_mec_release_mem)</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h<br/>index 8b6b2bd5c148..e356a207d03c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h</a></div><div class='hunk'>@@ -63,7 +63,8 @@ struct pm4_mes_set_resources {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			uint32_t vmid_mask:16;</div><div class='ctx'> 			uint32_t unmap_latency:8;</div><div class='del'>-			uint32_t reserved1:5;</div><div class='add'>+			uint32_t reserved1:4;</div><div class='add'>+			uint32_t enb_xnack_retry_disable_check:1;</div><div class='ctx'> 			enum mes_set_resources_queue_type_enum queue_type:3;</div><div class='ctx'> 		} bitfields2;</div><div class='ctx'> 		uint32_t ordinal2;</div><div class='hunk'>@@ -145,8 +146,9 @@ struct pm4_mes_map_process {</div><div class='ctx'> </div><div class='ctx'> 	union {</div><div class='ctx'> 		struct {</div><div class='del'>-			uint32_t pasid:16;</div><div class='del'>-			uint32_t reserved1:2;</div><div class='add'>+			uint32_t pasid:16;		/* 0 - 15  */</div><div class='add'>+			uint32_t reserved1:1;		/* 16      */</div><div class='add'>+			uint32_t exec_cleaner_shader:1;	/* 17      */</div><div class='ctx'> 			uint32_t debug_vmid:4;</div><div class='ctx'> 			uint32_t new_debug:1;</div><div class='ctx'> 			uint32_t reserved2:1;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h<br/>index 38f5cb6a222a..e0ed62c4ade0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h</a></div><div class='hunk'>@@ -37,7 +37,7 @@ struct pm4_mes_map_process_aldebaran {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			uint32_t pasid:16;	    /* 0 - 15  */</div><div class='ctx'> 			uint32_t single_memops:1;   /* 16      */</div><div class='del'>-			uint32_t reserved1:1;	    /* 17      */</div><div class='add'>+			uint32_t exec_cleaner_shader:1;	    /* 17      */</div><div class='ctx'> 			uint32_t debug_vmid:4;	    /* 18 - 21 */</div><div class='ctx'> 			uint32_t new_debug:1;	    /* 22      */</div><div class='ctx'> 			uint32_t tmz:1;		    /* 23      */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h<br/>index 42d40560cd30..70ef051511bb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_priv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_priv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_priv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_priv.h</a></div><div class='hunk'>@@ -32,7 +32,7 @@</div><div class='ctx'> #include &lt;linux/atomic.h&gt;</div><div class='ctx'> #include &lt;linux/workqueue.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='del'>-#include &lt;linux/kfd_ioctl.h&gt;</div><div class='add'>+#include &lt;uapi/linux/kfd_ioctl.h&gt;</div><div class='ctx'> #include &lt;linux/idr.h&gt;</div><div class='ctx'> #include &lt;linux/kfifo.h&gt;</div><div class='ctx'> #include &lt;linux/seq_file.h&gt;</div><div class='hunk'>@@ -111,7 +111,14 @@</div><div class='ctx'> </div><div class='ctx'> #define KFD_KERNEL_QUEUE_SIZE 2048</div><div class='ctx'> </div><div class='del'>-#define KFD_UNMAP_LATENCY_MS	(4000)</div><div class='add'>+/*  KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC</div><div class='add'>+ *  can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time</div><div class='add'>+ *  driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is</div><div class='add'>+ *  queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload</div><div class='add'>+ *  The format here makes CP workload 10% of total timeout</div><div class='add'>+ */</div><div class='add'>+#define KFD_UNMAP_LATENCY_MS	\</div><div class='add'>+	((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) &gt;&gt; 1)</div><div class='ctx'> </div><div class='ctx'> #define KFD_MAX_SDMA_QUEUES	128</div><div class='ctx'> </div><div class='hunk'>@@ -206,7 +213,9 @@ enum cache_policy {</div><div class='ctx'> #define KFD_IS_SOC15(dev)   ((KFD_GC_VERSION(dev)) &gt;= (IP_VERSION(9, 0, 1)))</div><div class='ctx'> #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\</div><div class='ctx'> 	((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) ||	\</div><div class='del'>-	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)))</div><div class='add'>+	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) ||	\</div><div class='add'>+	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) ||	\</div><div class='add'>+	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)))</div><div class='ctx'> </div><div class='ctx'> struct kfd_node;</div><div class='ctx'> </div><div class='hunk'>@@ -272,7 +281,6 @@ struct kfd_node {</div><div class='ctx'> </div><div class='ctx'> 	/* Interrupts */</div><div class='ctx'> 	struct kfifo ih_fifo;</div><div class='del'>-	struct workqueue_struct *ih_wq;</div><div class='ctx'> 	struct work_struct interrupt_work;</div><div class='ctx'> 	spinlock_t interrupt_lock;</div><div class='ctx'> </div><div class='hunk'>@@ -288,7 +296,6 @@ struct kfd_node {</div><div class='ctx'> </div><div class='ctx'> 	/* Global GWS resource shared between processes */</div><div class='ctx'> 	void *gws;</div><div class='del'>-	bool gws_debug_workaround;</div><div class='ctx'> </div><div class='ctx'> 	/* Clients watching SMI events */</div><div class='ctx'> 	struct list_head smi_clients;</div><div class='hunk'>@@ -309,6 +316,10 @@ struct kfd_node {</div><div class='ctx'> 	struct kfd_local_mem_info local_mem_info;</div><div class='ctx'> </div><div class='ctx'> 	struct kfd_dev *kfd;</div><div class='add'>+</div><div class='add'>+	/* Track per device allocated watch points */</div><div class='add'>+	uint32_t alloc_watch_ids;</div><div class='add'>+	spinlock_t watch_points_lock;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct kfd_dev {</div><div class='hunk'>@@ -361,15 +372,18 @@ struct kfd_dev {</div><div class='ctx'> 	struct kfd_node *nodes[MAX_KFD_NODES];</div><div class='ctx'> 	unsigned int num_nodes;</div><div class='ctx'> </div><div class='del'>-	/* Track per device allocated watch points */</div><div class='del'>-	uint32_t alloc_watch_ids;</div><div class='del'>-	spinlock_t watch_points_lock;</div><div class='add'>+	struct workqueue_struct *ih_wq;</div><div class='ctx'> </div><div class='ctx'> 	/* Kernel doorbells for KFD device */</div><div class='ctx'> 	struct amdgpu_bo *doorbells;</div><div class='ctx'> </div><div class='ctx'> 	/* bitmap for dynamic doorbell allocation from doorbell object */</div><div class='ctx'> 	unsigned long *doorbell_bitmap;</div><div class='add'>+</div><div class='add'>+	/* for dynamic partitioning */</div><div class='add'>+	int kfd_dev_lock;</div><div class='add'>+</div><div class='add'>+	atomic_t kfd_processes_count;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum kfd_mempool {</div><div class='hunk'>@@ -413,13 +427,16 @@ enum kfd_unmap_queues_filter {</div><div class='ctx'>  * @KFD_QUEUE_TYPE_DIQ: DIQ queue type.</div><div class='ctx'>  *</div><div class='ctx'>  * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface.</div><div class='add'>+ *</div><div class='add'>+ * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID:  SDMA user mode queue with target SDMA engine ID.</div><div class='ctx'>  */</div><div class='ctx'> enum kfd_queue_type  {</div><div class='ctx'> 	KFD_QUEUE_TYPE_COMPUTE,</div><div class='ctx'> 	KFD_QUEUE_TYPE_SDMA,</div><div class='ctx'> 	KFD_QUEUE_TYPE_HIQ,</div><div class='ctx'> 	KFD_QUEUE_TYPE_DIQ,</div><div class='del'>-	KFD_QUEUE_TYPE_SDMA_XGMI</div><div class='add'>+	KFD_QUEUE_TYPE_SDMA_XGMI,</div><div class='add'>+	KFD_QUEUE_TYPE_SDMA_BY_ENG_ID</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum kfd_queue_format {</div><div class='hunk'>@@ -493,8 +510,8 @@ struct queue_properties {</div><div class='ctx'> 	uint64_t  queue_size;</div><div class='ctx'> 	uint32_t priority;</div><div class='ctx'> 	uint32_t queue_percent;</div><div class='del'>-	uint32_t *read_ptr;</div><div class='del'>-	uint32_t *write_ptr;</div><div class='add'>+	void __user *read_ptr;</div><div class='add'>+	void __user *write_ptr;</div><div class='ctx'> 	void __iomem *doorbell_ptr;</div><div class='ctx'> 	uint32_t doorbell_off;</div><div class='ctx'> 	bool is_interop;</div><div class='hunk'>@@ -521,6 +538,12 @@ struct queue_properties {</div><div class='ctx'> 	uint64_t tba_addr;</div><div class='ctx'> 	uint64_t tma_addr;</div><div class='ctx'> 	uint64_t exception_status;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_bo *wptr_bo;</div><div class='add'>+	struct amdgpu_bo *rptr_bo;</div><div class='add'>+	struct amdgpu_bo *ring_bo;</div><div class='add'>+	struct amdgpu_bo *eop_buf_bo;</div><div class='add'>+	struct amdgpu_bo *cwsr_bo;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define QUEUE_IS_ACTIVE(q) ((q).queue_size &gt; 0 &amp;&amp;	\</div><div class='hunk'>@@ -603,7 +626,7 @@ struct queue {</div><div class='ctx'> 	uint64_t gang_ctx_gpu_addr;</div><div class='ctx'> 	void *gang_ctx_cpu_ptr;</div><div class='ctx'> </div><div class='del'>-	struct amdgpu_bo *wptr_bo;</div><div class='add'>+	struct amdgpu_bo *wptr_bo_gart;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum KFD_MQD_TYPE {</div><div class='hunk'>@@ -765,7 +788,7 @@ struct kfd_process_device {</div><div class='ctx'> 	enum kfd_pdd_bound bound;</div><div class='ctx'> </div><div class='ctx'> 	/* VRAM usage */</div><div class='del'>-	uint64_t vram_usage;</div><div class='add'>+	atomic64_t vram_usage;</div><div class='ctx'> 	struct attribute attr_vram;</div><div class='ctx'> 	char vram_filename[MAX_SYSFS_FILENAME_LEN];</div><div class='ctx'> </div><div class='hunk'>@@ -836,6 +859,11 @@ struct kfd_process_device {</div><div class='ctx'> 	void *proc_ctx_bo;</div><div class='ctx'> 	uint64_t proc_ctx_gpu_addr;</div><div class='ctx'> 	void *proc_ctx_cpu_ptr;</div><div class='add'>+</div><div class='add'>+	/* Tracks queue reset status */</div><div class='add'>+	bool has_reset_queue;</div><div class='add'>+</div><div class='add'>+	u32 pasid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)</div><div class='hunk'>@@ -853,6 +881,14 @@ struct svm_range_list {</div><div class='ctx'> 	struct delayed_work		restore_work;</div><div class='ctx'> 	DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);</div><div class='ctx'> 	struct task_struct		*faulting_task;</div><div class='add'>+	/* check point ts decides if page fault recovery need be dropped */</div><div class='add'>+	uint64_t			checkpoint_ts[MAX_GPU_INSTANCE];</div><div class='add'>+</div><div class='add'>+	/* Default granularity to use in buffer migration</div><div class='add'>+	 * and restoration of backing memory while handling</div><div class='add'>+	 * recoverable page faults</div><div class='add'>+	 */</div><div class='add'>+	uint8_t default_granularity;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Process data */</div><div class='hunk'>@@ -887,8 +923,6 @@ struct kfd_process {</div><div class='ctx'> 	/* We want to receive a notification when the mm_struct is destroyed */</div><div class='ctx'> 	struct mmu_notifier mmu_notifier;</div><div class='ctx'> </div><div class='del'>-	u32 pasid;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Array of kfd_process_device pointers,</div><div class='ctx'> 	 * one for each device the process is using.</div><div class='hunk'>@@ -981,6 +1015,9 @@ struct kfd_process {</div><div class='ctx'> 	struct semaphore runtime_enable_sema;</div><div class='ctx'> 	bool is_runtime_retry;</div><div class='ctx'> 	struct kfd_runtime_info runtime_info;</div><div class='add'>+</div><div class='add'>+	/* if gpu page fault sent to KFD */</div><div class='add'>+	bool gpu_page_fault;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */</div><div class='hunk'>@@ -1013,7 +1050,8 @@ void kfd_process_destroy_wq(void);</div><div class='ctx'> void kfd_cleanup_processes(void);</div><div class='ctx'> struct kfd_process *kfd_create_process(struct task_struct *thread);</div><div class='ctx'> struct kfd_process *kfd_get_process(const struct task_struct *task);</div><div class='del'>-struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid);</div><div class='add'>+struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid,</div><div class='add'>+						 struct kfd_process_device **pdd);</div><div class='ctx'> struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);</div><div class='ctx'> </div><div class='ctx'> int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);</div><div class='hunk'>@@ -1065,8 +1103,6 @@ struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid);</div><div class='ctx'> /* PASIDs */</div><div class='ctx'> int kfd_pasid_init(void);</div><div class='ctx'> void kfd_pasid_exit(void);</div><div class='del'>-bool kfd_set_pasid_limit(unsigned int new_limit);</div><div class='del'>-unsigned int kfd_get_pasid_limit(void);</div><div class='ctx'> u32 kfd_pasid_alloc(void);</div><div class='ctx'> void kfd_pasid_free(u32 pasid);</div><div class='ctx'> </div><div class='hunk'>@@ -1116,7 +1152,6 @@ struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(</div><div class='ctx'> 						uint32_t proximity_domain);</div><div class='ctx'> struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);</div><div class='ctx'> struct kfd_node *kfd_device_by_id(uint32_t gpu_id);</div><div class='del'>-struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev);</div><div class='ctx'> static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id,</div><div class='ctx'> 					uint32_t vmid)</div><div class='ctx'> {</div><div class='hunk'>@@ -1128,7 +1163,9 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev,</div><div class='ctx'> 	struct kfd_dev *dev = adev-&gt;kfd.dev;</div><div class='ctx'> 	uint32_t i;</div><div class='ctx'> </div><div class='del'>-	if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3))</div><div class='add'>+	if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+	    KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) &amp;&amp;</div><div class='add'>+	    KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0))</div><div class='ctx'> 		return dev-&gt;nodes[0];</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dev-&gt;num_nodes; i++)</div><div class='hunk'>@@ -1282,6 +1319,15 @@ int init_queue(struct queue **q, const struct queue_properties *properties);</div><div class='ctx'> void uninit_queue(struct queue *q);</div><div class='ctx'> void print_queue_properties(struct queue_properties *q);</div><div class='ctx'> void print_queue(struct queue *q);</div><div class='add'>+int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo,</div><div class='add'>+			 u64 expected_size);</div><div class='add'>+void kfd_queue_buffer_put(struct amdgpu_bo **bo);</div><div class='add'>+int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);</div><div class='add'>+int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);</div><div class='add'>+void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo);</div><div class='add'>+int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd,</div><div class='add'>+			   struct queue_properties *properties);</div><div class='add'>+void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev);</div><div class='ctx'> </div><div class='ctx'> struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,</div><div class='ctx'> 		struct kfd_node *dev);</div><div class='hunk'>@@ -1293,12 +1339,15 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,</div><div class='ctx'> 		struct kfd_node *dev);</div><div class='ctx'> struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,</div><div class='ctx'> 		struct kfd_node *dev);</div><div class='add'>+struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type,</div><div class='add'>+		struct kfd_node *dev);</div><div class='ctx'> struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev);</div><div class='ctx'> void device_queue_manager_uninit(struct device_queue_manager *dqm);</div><div class='ctx'> struct kernel_queue *kernel_queue_init(struct kfd_node *dev,</div><div class='ctx'> 					enum kfd_queue_type type);</div><div class='del'>-void kernel_queue_uninit(struct kernel_queue *kq, bool hanging);</div><div class='del'>-int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid);</div><div class='add'>+void kernel_queue_uninit(struct kernel_queue *kq);</div><div class='add'>+int kfd_evict_process_device(struct kfd_process_device *pdd);</div><div class='add'>+int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id);</div><div class='ctx'> </div><div class='ctx'> /* Process Queue Manager */</div><div class='ctx'> struct process_queue_node {</div><div class='hunk'>@@ -1313,10 +1362,8 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p);</div><div class='ctx'> void pqm_uninit(struct process_queue_manager *pqm);</div><div class='ctx'> int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 			    struct kfd_node *dev,</div><div class='del'>-			    struct file *f,</div><div class='ctx'> 			    struct queue_properties *properties,</div><div class='ctx'> 			    unsigned int *qid,</div><div class='del'>-			    struct amdgpu_bo *wptr_bo,</div><div class='ctx'> 			    const struct kfd_criu_queue_priv_data *q_data,</div><div class='ctx'> 			    const void *restore_mqd,</div><div class='ctx'> 			    const void *restore_ctl_stack,</div><div class='hunk'>@@ -1328,8 +1375,6 @@ int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid,</div><div class='ctx'> 			struct mqd_update_info *minfo);</div><div class='ctx'> int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,</div><div class='ctx'> 			void *gws);</div><div class='del'>-struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm,</div><div class='del'>-						unsigned int qid);</div><div class='ctx'> struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 						unsigned int qid);</div><div class='ctx'> int pqm_get_wave_state(struct process_queue_manager *pqm,</div><div class='hunk'>@@ -1356,6 +1401,24 @@ int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,</div><div class='ctx'> #define KFD_FENCE_COMPLETED (100)</div><div class='ctx'> #define KFD_FENCE_INIT   (10)</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring</div><div class='add'>+ *  dequeue wait counts.</div><div class='add'>+ *</div><div class='add'>+ * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a</div><div class='add'>+ *	certain ASICs. For these ASICs, this is default value used by RESET</div><div class='add'>+ * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value</div><div class='add'>+ *	for certain ASICs. For others set it to default hardware reset value</div><div class='add'>+ * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+enum kfd_config_dequeue_wait_counts_cmd {</div><div class='add'>+	KFD_DEQUEUE_WAIT_INIT = 1,</div><div class='add'>+	KFD_DEQUEUE_WAIT_RESET = 2,</div><div class='add'>+	KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> struct packet_manager {</div><div class='ctx'> 	struct device_queue_manager *dqm;</div><div class='ctx'> 	struct kernel_queue *priv_queue;</div><div class='hunk'>@@ -1381,8 +1444,8 @@ struct packet_manager_funcs {</div><div class='ctx'> 	int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 			enum kfd_unmap_queues_filter mode,</div><div class='ctx'> 			uint32_t filter_param, bool reset);</div><div class='del'>-	int (*set_grace_period)(struct packet_manager *pm, uint32_t *buffer,</div><div class='del'>-			uint32_t grace_period);</div><div class='add'>+	int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer,</div><div class='add'>+			enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value);</div><div class='ctx'> 	int (*query_status)(struct packet_manager *pm, uint32_t *buffer,</div><div class='ctx'> 			uint64_t fence_address,	uint64_t fence_value);</div><div class='ctx'> 	int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);</div><div class='hunk'>@@ -1393,7 +1456,7 @@ struct packet_manager_funcs {</div><div class='ctx'> 	int set_resources_size;</div><div class='ctx'> 	int map_queues_size;</div><div class='ctx'> 	int unmap_queues_size;</div><div class='del'>-	int set_grace_period_size;</div><div class='add'>+	int config_dequeue_wait_counts_size;</div><div class='ctx'> 	int query_status_size;</div><div class='ctx'> 	int release_mem_size;</div><div class='ctx'> };</div><div class='hunk'>@@ -1403,7 +1466,7 @@ extern const struct packet_manager_funcs kfd_v9_pm_funcs;</div><div class='ctx'> extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs;</div><div class='ctx'> </div><div class='ctx'> int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);</div><div class='del'>-void pm_uninit(struct packet_manager *pm, bool hanging);</div><div class='add'>+void pm_uninit(struct packet_manager *pm);</div><div class='ctx'> int pm_send_set_resources(struct packet_manager *pm,</div><div class='ctx'> 				struct scheduling_resources *res);</div><div class='ctx'> int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues);</div><div class='hunk'>@@ -1416,7 +1479,9 @@ int pm_send_unmap_queue(struct packet_manager *pm,</div><div class='ctx'> </div><div class='ctx'> void pm_release_ib(struct packet_manager *pm);</div><div class='ctx'> </div><div class='del'>-int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period);</div><div class='add'>+int pm_config_dequeue_wait_counts(struct packet_manager *pm,</div><div class='add'>+			enum kfd_config_dequeue_wait_counts_cmd cmd,</div><div class='add'>+			uint32_t wait_counts_config);</div><div class='ctx'> </div><div class='ctx'> /* Following PM funcs can be shared among VI and AI */</div><div class='ctx'> unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);</div><div class='hunk'>@@ -1454,7 +1519,9 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p,</div><div class='ctx'> int kfd_get_num_events(struct kfd_process *p);</div><div class='ctx'> int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);</div><div class='ctx'> </div><div class='del'>-void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid,</div><div class='add'>+void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va);</div><div class='add'>+</div><div class='add'>+void kfd_signal_vm_fault_event(struct kfd_process_device *pdd,</div><div class='ctx'> 				struct kfd_vm_fault_info *info,</div><div class='ctx'> 				struct kfd_hsa_memory_exception_data *data);</div><div class='ctx'> </div><div class='hunk'>@@ -1473,7 +1540,7 @@ static inline void kfd_flush_tlb(struct kfd_process_device *pdd,</div><div class='ctx'> </div><div class='ctx'> static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)</div><div class='ctx'> {</div><div class='del'>-	return KFD_GC_VERSION(dev) &gt; IP_VERSION(9, 4, 2) ||</div><div class='add'>+	return KFD_GC_VERSION(dev) &gt;= IP_VERSION(9, 4, 2) ||</div><div class='ctx'> 	       (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) &amp;&amp; dev-&gt;sdma_fw_version &gt;= 18) ||</div><div class='ctx'> 	       KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);</div><div class='ctx'> }</div><div class='hunk'>@@ -1481,7 +1548,7 @@ static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)</div><div class='ctx'> int kfd_send_exception_to_runtime(struct kfd_process *p,</div><div class='ctx'> 				unsigned int queue_id,</div><div class='ctx'> 				uint64_t error_reason);</div><div class='del'>-bool kfd_is_locked(void);</div><div class='add'>+bool kfd_is_locked(struct kfd_dev *kfd);</div><div class='ctx'> </div><div class='ctx'> /* Compute profile */</div><div class='ctx'> void kfd_inc_compute_active(struct kfd_node *dev);</div><div class='hunk'>@@ -1528,10 +1595,15 @@ int kfd_debugfs_hang_hws(struct kfd_node *dev);</div><div class='ctx'> int pm_debugfs_hang_hws(struct packet_manager *pm);</div><div class='ctx'> int dqm_debugfs_hang_hws(struct device_queue_manager *dqm);</div><div class='ctx'> </div><div class='add'>+void kfd_debugfs_add_process(struct kfd_process *p);</div><div class='add'>+void kfd_debugfs_remove_process(struct kfd_process *p);</div><div class='add'>+</div><div class='ctx'> #else</div><div class='ctx'> </div><div class='ctx'> static inline void kfd_debugfs_init(void) {}</div><div class='ctx'> static inline void kfd_debugfs_fini(void) {}</div><div class='add'>+static inline void kfd_debugfs_add_process(struct kfd_process *p) {}</div><div class='add'>+static inline void kfd_debugfs_remove_process(struct kfd_process *p) {}</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c<br/>index 717a60d7a4ea..a085faac9fe1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_process.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_process.c</a></div><div class='hunk'>@@ -35,6 +35,7 @@</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include "amdgpu_amdkfd.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> struct mm_struct;</div><div class='ctx'> </div><div class='hunk'>@@ -270,6 +271,9 @@ static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer)</div><div class='ctx'> 	struct kfd_node *dev = NULL;</div><div class='ctx'> 	struct kfd_process *proc = NULL;</div><div class='ctx'> 	struct kfd_process_device *pdd = NULL;</div><div class='add'>+	int i;</div><div class='add'>+	struct kfd_cu_occupancy *cu_occupancy;</div><div class='add'>+	u32 queue_format;</div><div class='ctx'> </div><div class='ctx'> 	pdd = container_of(attr, struct kfd_process_device, attr_cu_occupancy);</div><div class='ctx'> 	dev = pdd-&gt;dev;</div><div class='hunk'>@@ -279,41 +283,64 @@ static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer)</div><div class='ctx'> 	cu_cnt = 0;</div><div class='ctx'> 	proc = pdd-&gt;process;</div><div class='ctx'> 	if (pdd-&gt;qpd.queue_count == 0) {</div><div class='del'>-		pr_debug("Gpu-Id: %d has no active queues for process %d\n",</div><div class='del'>-			 dev-&gt;id, proc-&gt;pasid);</div><div class='add'>+		pr_debug("Gpu-Id: %d has no active queues for process pid %d\n",</div><div class='add'>+			 dev-&gt;id, (int)proc-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Collect wave count from device if it supports */</div><div class='ctx'> 	wave_cnt = 0;</div><div class='ctx'> 	max_waves_per_cu = 0;</div><div class='del'>-	dev-&gt;kfd2kgd-&gt;get_cu_occupancy(dev-&gt;adev, proc-&gt;pasid, &amp;wave_cnt,</div><div class='del'>-			&amp;max_waves_per_cu, 0);</div><div class='add'>+</div><div class='add'>+	cu_occupancy = kcalloc(AMDGPU_MAX_QUEUES, sizeof(*cu_occupancy), GFP_KERNEL);</div><div class='add'>+	if (!cu_occupancy)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For GFX 9.4.3, fetch the CU occupancy from the first XCC in the partition.</div><div class='add'>+	 * For AQL queues, because of cooperative dispatch we multiply the wave count</div><div class='add'>+	 * by number of XCCs in the partition to get the total wave counts across all</div><div class='add'>+	 * XCCs in the partition.</div><div class='add'>+	 * For PM4 queues, there is no cooperative dispatch so wave_cnt stay as it is.</div><div class='add'>+	 */</div><div class='add'>+	dev-&gt;kfd2kgd-&gt;get_cu_occupancy(dev-&gt;adev, cu_occupancy,</div><div class='add'>+			&amp;max_waves_per_cu, ffs(dev-&gt;xcc_mask) - 1);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_MAX_QUEUES; i++) {</div><div class='add'>+		if (cu_occupancy[i].wave_cnt != 0 &amp;&amp;</div><div class='add'>+		    kfd_dqm_is_queue_in_process(dev-&gt;dqm, &amp;pdd-&gt;qpd,</div><div class='add'>+						cu_occupancy[i].doorbell_off,</div><div class='add'>+						&amp;queue_format)) {</div><div class='add'>+			if (unlikely(queue_format == KFD_QUEUE_FORMAT_PM4))</div><div class='add'>+				wave_cnt += cu_occupancy[i].wave_cnt;</div><div class='add'>+			else</div><div class='add'>+				wave_cnt += (NUM_XCC(dev-&gt;xcc_mask) *</div><div class='add'>+						cu_occupancy[i].wave_cnt);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Translate wave count to number of compute units */</div><div class='ctx'> 	cu_cnt = (wave_cnt + (max_waves_per_cu - 1)) / max_waves_per_cu;</div><div class='add'>+	kfree(cu_occupancy);</div><div class='ctx'> 	return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t kfd_procfs_show(struct kobject *kobj, struct attribute *attr,</div><div class='ctx'> 			       char *buffer)</div><div class='ctx'> {</div><div class='del'>-	if (strcmp(attr-&gt;name, "pasid") == 0) {</div><div class='del'>-		struct kfd_process *p = container_of(attr, struct kfd_process,</div><div class='del'>-						     attr_pasid);</div><div class='del'>-</div><div class='del'>-		return snprintf(buffer, PAGE_SIZE, "%d\n", p-&gt;pasid);</div><div class='del'>-	} else if (strncmp(attr-&gt;name, "vram_", 5) == 0) {</div><div class='add'>+	if (strcmp(attr-&gt;name, "pasid") == 0)</div><div class='add'>+		return snprintf(buffer, PAGE_SIZE, "%d\n", 0);</div><div class='add'>+	else if (strncmp(attr-&gt;name, "vram_", 5) == 0) {</div><div class='ctx'> 		struct kfd_process_device *pdd = container_of(attr, struct kfd_process_device,</div><div class='ctx'> 							      attr_vram);</div><div class='del'>-		return snprintf(buffer, PAGE_SIZE, "%llu\n", READ_ONCE(pdd-&gt;vram_usage));</div><div class='add'>+		return snprintf(buffer, PAGE_SIZE, "%llu\n", atomic64_read(&amp;pdd-&gt;vram_usage));</div><div class='ctx'> 	} else if (strncmp(attr-&gt;name, "sdma_", 5) == 0) {</div><div class='ctx'> 		struct kfd_process_device *pdd = container_of(attr, struct kfd_process_device,</div><div class='ctx'> 							      attr_sdma);</div><div class='ctx'> 		struct kfd_sdma_activity_handler_workarea sdma_activity_work_handler;</div><div class='ctx'> </div><div class='del'>-		INIT_WORK(&amp;sdma_activity_work_handler.sdma_activity_work,</div><div class='del'>-					kfd_sdma_activity_worker);</div><div class='add'>+		INIT_WORK_ONSTACK(&amp;sdma_activity_work_handler.sdma_activity_work,</div><div class='add'>+				  kfd_sdma_activity_worker);</div><div class='ctx'> </div><div class='ctx'> 		sdma_activity_work_handler.pdd = pdd;</div><div class='ctx'> 		sdma_activity_work_handler.sdma_activity_counter = 0;</div><div class='hunk'>@@ -321,6 +348,7 @@ static ssize_t kfd_procfs_show(struct kobject *kobj, struct attribute *attr,</div><div class='ctx'> 		schedule_work(&amp;sdma_activity_work_handler.sdma_activity_work);</div><div class='ctx'> </div><div class='ctx'> 		flush_work(&amp;sdma_activity_work_handler.sdma_activity_work);</div><div class='add'>+		destroy_work_on_stack(&amp;sdma_activity_work_handler.sdma_activity_work);</div><div class='ctx'> </div><div class='ctx'> 		return snprintf(buffer, PAGE_SIZE, "%llu\n",</div><div class='ctx'> 				(sdma_activity_work_handler.sdma_activity_counter)/</div><div class='hunk'>@@ -811,6 +839,14 @@ struct kfd_process *kfd_create_process(struct task_struct *thread)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* If the process just called exec(3), it is possible that the</div><div class='add'>+	 * cleanup of the kfd_process (following the release of the mm</div><div class='add'>+	 * of the old process image) is still in the cleanup work queue.</div><div class='add'>+	 * Make sure to drain any job before trying to recreate any</div><div class='add'>+	 * resource for this process.</div><div class='add'>+	 */</div><div class='add'>+	flush_workqueue(kfd_process_wq);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * take kfd processes mutex before starting of process creation</div><div class='ctx'> 	 * so there won't be a case where two threads of the same process</div><div class='hunk'>@@ -818,14 +854,16 @@ struct kfd_process *kfd_create_process(struct task_struct *thread)</div><div class='ctx'> 	 */</div><div class='ctx'> 	mutex_lock(&amp;kfd_processes_mutex);</div><div class='ctx'> </div><div class='del'>-	if (kfd_is_locked()) {</div><div class='del'>-		mutex_unlock(&amp;kfd_processes_mutex);</div><div class='add'>+	if (kfd_is_locked(NULL)) {</div><div class='ctx'> 		pr_debug("KFD is locked! Cannot create process");</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='add'>+		process = ERR_PTR(-EINVAL);</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* A prior open of /dev/kfd could have already created the process. */</div><div class='del'>-	process = find_process(thread, false);</div><div class='add'>+	/* A prior open of /dev/kfd could have already created the process.</div><div class='add'>+	 * find_process will increase process kref in this case</div><div class='add'>+	 */</div><div class='add'>+	process = find_process(thread, true);</div><div class='ctx'> 	if (process) {</div><div class='ctx'> 		pr_debug("Process already found\n");</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -862,11 +900,11 @@ struct kfd_process *kfd_create_process(struct task_struct *thread)</div><div class='ctx'> 		kfd_procfs_add_sysfs_files(process);</div><div class='ctx'> 		kfd_procfs_add_sysfs_counters(process);</div><div class='ctx'> </div><div class='add'>+		kfd_debugfs_add_process(process);</div><div class='add'>+</div><div class='ctx'> 		init_waitqueue_head(&amp;process-&gt;wait_irq_drain);</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='del'>-	if (!IS_ERR(process))</div><div class='del'>-		kref_get(&amp;process-&gt;ref);</div><div class='ctx'> 	mutex_unlock(&amp;kfd_processes_mutex);</div><div class='ctx'> 	mmput(thread-&gt;mm);</div><div class='ctx'> </div><div class='hunk'>@@ -1018,17 +1056,15 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)</div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = p-&gt;pdds[i];</div><div class='ctx'> </div><div class='del'>-		pr_debug("Releasing pdd (topology id %d) for process (pasid 0x%x)\n",</div><div class='del'>-				pdd-&gt;dev-&gt;id, p-&gt;pasid);</div><div class='add'>+		kfd_smi_event_process(pdd, false);</div><div class='ctx'> </div><div class='add'>+		pr_debug("Releasing pdd (topology id %d, for pid %d)\n",</div><div class='add'>+			pdd-&gt;dev-&gt;id, p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		kfd_process_device_destroy_cwsr_dgpu(pdd);</div><div class='ctx'> 		kfd_process_device_destroy_ib_mem(pdd);</div><div class='ctx'> </div><div class='del'>-		if (pdd-&gt;drm_file) {</div><div class='del'>-			amdgpu_amdkfd_gpuvm_release_process_vm(</div><div class='del'>-					pdd-&gt;dev-&gt;adev, pdd-&gt;drm_priv);</div><div class='add'>+		if (pdd-&gt;drm_file)</div><div class='ctx'> 			fput(pdd-&gt;drm_file);</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		if (pdd-&gt;qpd.cwsr_kaddr &amp;&amp; !pdd-&gt;qpd.cwsr_base)</div><div class='ctx'> 			free_pages((unsigned long)pdd-&gt;qpd.cwsr_kaddr,</div><div class='hunk'>@@ -1038,19 +1074,21 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)</div><div class='ctx'> </div><div class='ctx'> 		kfd_free_process_doorbells(pdd-&gt;dev-&gt;kfd, pdd);</div><div class='ctx'> </div><div class='del'>-		if (pdd-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+		if (pdd-&gt;dev-&gt;kfd-&gt;shared_resources.enable_mes &amp;&amp;</div><div class='add'>+			pdd-&gt;proc_ctx_cpu_ptr)</div><div class='ctx'> 			amdgpu_amdkfd_free_gtt_mem(pdd-&gt;dev-&gt;adev,</div><div class='del'>-						   pdd-&gt;proc_ctx_bo);</div><div class='add'>+						   &amp;pdd-&gt;proc_ctx_bo);</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * before destroying pdd, make sure to report availability</div><div class='ctx'> 		 * for auto suspend</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (pdd-&gt;runtime_inuse) {</div><div class='del'>-			pm_runtime_mark_last_busy(adev_to_drm(pdd-&gt;dev-&gt;adev)-&gt;dev);</div><div class='ctx'> 			pm_runtime_put_autosuspend(adev_to_drm(pdd-&gt;dev-&gt;adev)-&gt;dev);</div><div class='ctx'> 			pdd-&gt;runtime_inuse = false;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		atomic_dec(&amp;pdd-&gt;dev-&gt;kfd-&gt;kfd_processes_count);</div><div class='add'>+</div><div class='ctx'> 		kfree(pdd);</div><div class='ctx'> 		p-&gt;pdds[i] = NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1101,6 +1139,17 @@ static void kfd_process_remove_sysfs(struct kfd_process *p)</div><div class='ctx'> 	p-&gt;kobj = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * If any GPU is ongoing reset, wait for reset complete.</div><div class='add'>+ */</div><div class='add'>+static void kfd_process_wait_gpu_reset_complete(struct kfd_process *p)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; p-&gt;n_pdds; i++)</div><div class='add'>+		flush_workqueue(p-&gt;pdds[i]-&gt;dev-&gt;adev-&gt;reset_domain-&gt;wq);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* No process locking is needed in this function, because the process</div><div class='ctx'>  * is not findable any more. We must assume that no other thread is</div><div class='ctx'>  * using it any more, otherwise we couldn't safely free the process</div><div class='hunk'>@@ -1112,8 +1161,10 @@ static void kfd_process_wq_release(struct work_struct *work)</div><div class='ctx'> 					     release_work);</div><div class='ctx'> 	struct dma_fence *ef;</div><div class='ctx'> </div><div class='del'>-	kfd_process_dequeue_from_all_devices(p);</div><div class='del'>-	pqm_uninit(&amp;p-&gt;pqm);</div><div class='add'>+	/*</div><div class='add'>+	 * If GPU in reset, user queues may still running, wait for reset complete.</div><div class='add'>+	 */</div><div class='add'>+	kfd_process_wait_gpu_reset_complete(p);</div><div class='ctx'> </div><div class='ctx'> 	/* Signal the eviction fence after user mode queues are</div><div class='ctx'> 	 * destroyed. This allows any BOs to be freed without</div><div class='hunk'>@@ -1121,9 +1172,11 @@ static void kfd_process_wq_release(struct work_struct *work)</div><div class='ctx'> 	 */</div><div class='ctx'> 	synchronize_rcu();</div><div class='ctx'> 	ef = rcu_access_pointer(p-&gt;ef);</div><div class='del'>-	dma_fence_signal(ef);</div><div class='add'>+	if (ef)</div><div class='add'>+		dma_fence_signal(ef);</div><div class='ctx'> </div><div class='ctx'> 	kfd_process_remove_sysfs(p);</div><div class='add'>+	kfd_debugfs_remove_process(p);</div><div class='ctx'> </div><div class='ctx'> 	kfd_process_kunmap_signal_bo(p);</div><div class='ctx'> 	kfd_process_free_outstanding_kfd_bos(p);</div><div class='hunk'>@@ -1134,7 +1187,6 @@ static void kfd_process_wq_release(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	kfd_event_free_process(p);</div><div class='ctx'> </div><div class='del'>-	kfd_pasid_free(p-&gt;pasid);</div><div class='ctx'> 	mutex_destroy(&amp;p-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	put_task_struct(p-&gt;lead_thread);</div><div class='hunk'>@@ -1152,10 +1204,8 @@ static void kfd_process_ref_release(struct kref *ref)</div><div class='ctx'> </div><div class='ctx'> static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm)</div><div class='ctx'> {</div><div class='del'>-	int idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='del'>-	struct kfd_process *p = find_process_by_mm(mm);</div><div class='del'>-</div><div class='del'>-	srcu_read_unlock(&amp;kfd_processes_srcu, idx);</div><div class='add'>+	/* This increments p-&gt;ref counter if kfd process p exists */</div><div class='add'>+	struct kfd_process *p = kfd_lookup_process_by_mm(mm);</div><div class='ctx'> </div><div class='ctx'> 	return p ? &amp;p-&gt;mmu_notifier : ERR_PTR(-ESRCH);</div><div class='ctx'> }</div><div class='hunk'>@@ -1172,6 +1222,14 @@ static void kfd_process_notifier_release_internal(struct kfd_process *p)</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;p-&gt;eviction_work);</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;p-&gt;restore_work);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Dequeue and destroy user queues, it is not safe for GPU to access</div><div class='add'>+	 * system memory after mmu release notifier callback returns because</div><div class='add'>+	 * exit_mmap free process memory afterwards.</div><div class='add'>+	 */</div><div class='add'>+	kfd_process_dequeue_from_all_devices(p);</div><div class='add'>+	pqm_uninit(&amp;p-&gt;pqm);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = p-&gt;pdds[i];</div><div class='ctx'> </div><div class='hunk'>@@ -1303,7 +1361,8 @@ int kfd_process_init_cwsr_apu(struct kfd_process *p, struct file *filep)</div><div class='ctx'> 		if (IS_ERR_VALUE(qpd-&gt;tba_addr)) {</div><div class='ctx'> 			int err = qpd-&gt;tba_addr;</div><div class='ctx'> </div><div class='del'>-			pr_err("Failure to set tba address. error %d.\n", err);</div><div class='add'>+			dev_err(dev-&gt;adev-&gt;dev,</div><div class='add'>+				"Failure to set tba address. error %d.\n", err);</div><div class='ctx'> 			qpd-&gt;tba_addr = 0;</div><div class='ctx'> 			qpd-&gt;cwsr_kaddr = NULL;</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -1486,12 +1545,6 @@ static struct kfd_process *create_process(const struct task_struct *thread)</div><div class='ctx'> 	atomic_set(&amp;process-&gt;debugged_process_count, 0);</div><div class='ctx'> 	sema_init(&amp;process-&gt;runtime_enable_sema, 0);</div><div class='ctx'> </div><div class='del'>-	process-&gt;pasid = kfd_pasid_alloc();</div><div class='del'>-	if (process-&gt;pasid == 0) {</div><div class='del'>-		err = -ENOSPC;</div><div class='del'>-		goto err_alloc_pasid;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	err = pqm_init(&amp;process-&gt;pqm, process);</div><div class='ctx'> 	if (err != 0)</div><div class='ctx'> 		goto err_process_pqm_init;</div><div class='hunk'>@@ -1545,8 +1598,6 @@ err_init_svm_range_list:</div><div class='ctx'> err_init_apertures:</div><div class='ctx'> 	pqm_uninit(&amp;process-&gt;pqm);</div><div class='ctx'> err_process_pqm_init:</div><div class='del'>-	kfd_pasid_free(process-&gt;pasid);</div><div class='del'>-err_alloc_pasid:</div><div class='ctx'> 	kfd_event_free_process(process);</div><div class='ctx'> err_event_init:</div><div class='ctx'> 	mutex_destroy(&amp;process-&gt;mutex);</div><div class='hunk'>@@ -1571,7 +1622,6 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev,</div><div class='ctx'> 							struct kfd_process *p)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process_device *pdd = NULL;</div><div class='del'>-	int retval = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON_ONCE(p-&gt;n_pdds &gt;= MAX_GPU_INSTANCE))</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -1590,25 +1640,11 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev,</div><div class='ctx'> 	pdd-&gt;bound = PDD_UNBOUND;</div><div class='ctx'> 	pdd-&gt;already_dequeued = false;</div><div class='ctx'> 	pdd-&gt;runtime_inuse = false;</div><div class='del'>-	pdd-&gt;vram_usage = 0;</div><div class='add'>+	atomic64_set(&amp;pdd-&gt;vram_usage, 0);</div><div class='ctx'> 	pdd-&gt;sdma_past_activity_counter = 0;</div><div class='ctx'> 	pdd-&gt;user_gpu_id = dev-&gt;id;</div><div class='ctx'> 	atomic64_set(&amp;pdd-&gt;evict_duration_counter, 0);</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='del'>-		retval = amdgpu_amdkfd_alloc_gtt_mem(dev-&gt;adev,</div><div class='del'>-						AMDGPU_MES_PROC_CTX_SIZE,</div><div class='del'>-						&amp;pdd-&gt;proc_ctx_bo,</div><div class='del'>-						&amp;pdd-&gt;proc_ctx_gpu_addr,</div><div class='del'>-						&amp;pdd-&gt;proc_ctx_cpu_ptr,</div><div class='del'>-						false);</div><div class='del'>-		if (retval) {</div><div class='del'>-			pr_err("failed to allocate process context bo\n");</div><div class='del'>-			goto err_free_pdd;</div><div class='del'>-		}</div><div class='del'>-		memset(pdd-&gt;proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	p-&gt;pdds[p-&gt;n_pdds++] = pdd;</div><div class='ctx'> 	if (kfd_dbg_is_per_vmid_supported(pdd-&gt;dev))</div><div class='ctx'> 		pdd-&gt;spi_dbg_override = pdd-&gt;dev-&gt;kfd2kgd-&gt;disable_debug_trap(</div><div class='hunk'>@@ -1619,11 +1655,9 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev,</div><div class='ctx'> 	/* Init idr used for memory handle translation */</div><div class='ctx'> 	idr_init(&amp;pdd-&gt;alloc_idr);</div><div class='ctx'> </div><div class='del'>-	return pdd;</div><div class='add'>+	atomic_inc(&amp;dev-&gt;kfd-&gt;kfd_processes_count);</div><div class='ctx'> </div><div class='del'>-err_free_pdd:</div><div class='del'>-	kfree(pdd);</div><div class='del'>-	return NULL;</div><div class='add'>+	return pdd;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1666,12 +1700,15 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_amdkfd_gpuvm_acquire_process_vm(dev-&gt;adev, avm,</div><div class='ctx'> 						     &amp;p-&gt;kgd_process_info,</div><div class='del'>-						     &amp;ef);</div><div class='add'>+						     p-&gt;ef ? NULL : &amp;ef);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		pr_err("Failed to create process VM object\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Failed to create process VM object\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='del'>-	RCU_INIT_POINTER(p-&gt;ef, ef);</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;ef)</div><div class='add'>+		RCU_INIT_POINTER(p-&gt;ef, ef);</div><div class='add'>+</div><div class='ctx'> 	pdd-&gt;drm_priv = drm_file-&gt;private_data;</div><div class='ctx'> </div><div class='ctx'> 	ret = kfd_process_device_reserve_ib_mem(pdd);</div><div class='hunk'>@@ -1681,15 +1718,21 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_init_cwsr;</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_amdkfd_gpuvm_set_vm_pasid(dev-&gt;adev, avm, p-&gt;pasid);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err_set_pasid;</div><div class='add'>+	if (unlikely(!avm-&gt;pasid)) {</div><div class='add'>+		dev_warn(pdd-&gt;dev-&gt;adev-&gt;dev, "WARN: vm %p has no pasid associated",</div><div class='add'>+				 avm);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_get_pasid;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	pdd-&gt;pasid = avm-&gt;pasid;</div><div class='ctx'> 	pdd-&gt;drm_file = drm_file;</div><div class='ctx'> </div><div class='add'>+	kfd_smi_event_process(pdd, true);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-err_set_pasid:</div><div class='add'>+err_get_pasid:</div><div class='ctx'> 	kfd_process_device_destroy_cwsr_dgpu(pdd);</div><div class='ctx'> err_init_cwsr:</div><div class='ctx'> 	kfd_process_device_destroy_ib_mem(pdd);</div><div class='hunk'>@@ -1715,7 +1758,7 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev,</div><div class='ctx'> </div><div class='ctx'> 	pdd = kfd_get_process_device_data(dev, p);</div><div class='ctx'> 	if (!pdd) {</div><div class='del'>-		pr_err("Process device data doesn't exist\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Process device data doesn't exist\n");</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1775,25 +1818,50 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,</div><div class='ctx'> 		idr_remove(&amp;pdd-&gt;alloc_idr, handle);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* This increments the process-&gt;ref counter. */</div><div class='del'>-struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid)</div><div class='add'>+static struct kfd_process_device *kfd_lookup_process_device_by_pasid(u32 pasid)</div><div class='ctx'> {</div><div class='del'>-	struct kfd_process *p, *ret_p = NULL;</div><div class='add'>+	struct kfd_process_device *ret_p = NULL;</div><div class='add'>+	struct kfd_process *p;</div><div class='ctx'> 	unsigned int temp;</div><div class='del'>-</div><div class='del'>-	int idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='del'>-		if (p-&gt;pasid == pasid) {</div><div class='del'>-			kref_get(&amp;p-&gt;ref);</div><div class='del'>-			ret_p = p;</div><div class='del'>-			break;</div><div class='add'>+		for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='add'>+			if (p-&gt;pdds[i]-&gt;pasid == pasid) {</div><div class='add'>+				ret_p = p-&gt;pdds[i];</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='add'>+		if (ret_p)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	return ret_p;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* This increments the process-&gt;ref counter. */</div><div class='add'>+struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid,</div><div class='add'>+						struct kfd_process_device **pdd)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process_device *ret_p;</div><div class='add'>+</div><div class='add'>+	int idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='add'>+</div><div class='add'>+	ret_p = kfd_lookup_process_device_by_pasid(pasid);</div><div class='add'>+	if (ret_p) {</div><div class='add'>+		if (pdd)</div><div class='add'>+			*pdd = ret_p;</div><div class='add'>+		kref_get(&amp;ret_p-&gt;process-&gt;ref);</div><div class='add'>+</div><div class='add'>+		srcu_read_unlock(&amp;kfd_processes_srcu, idx);</div><div class='add'>+		return ret_p-&gt;process;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	srcu_read_unlock(&amp;kfd_processes_srcu, idx);</div><div class='ctx'> </div><div class='del'>-	return ret_p;</div><div class='add'>+	if (pdd)</div><div class='add'>+		*pdd = NULL;</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* This increments the process-&gt;ref counter. */</div><div class='hunk'>@@ -1825,6 +1893,7 @@ int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = p-&gt;pdds[i];</div><div class='add'>+		struct device *dev = pdd-&gt;dev-&gt;adev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 		kfd_smi_event_queue_eviction(pdd-&gt;dev, p-&gt;lead_thread-&gt;pid,</div><div class='ctx'> 					     trigger);</div><div class='hunk'>@@ -1836,10 +1905,12 @@ int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger)</div><div class='ctx'> 		 * them been add back since they actually not be saved right now.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (r &amp;&amp; r != -EIO) {</div><div class='del'>-			pr_err("Failed to evict process queues\n");</div><div class='add'>+			dev_err(dev, "Failed to evict process queues\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 		n_evicted++;</div><div class='add'>+</div><div class='add'>+		pdd-&gt;dev-&gt;dqm-&gt;is_hws_hang = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -1858,7 +1929,8 @@ fail:</div><div class='ctx'> </div><div class='ctx'> 		if (pdd-&gt;dev-&gt;dqm-&gt;ops.restore_process_queues(pdd-&gt;dev-&gt;dqm,</div><div class='ctx'> 							      &amp;pdd-&gt;qpd))</div><div class='del'>-			pr_err("Failed to restore queues\n");</div><div class='add'>+			dev_err(pdd-&gt;dev-&gt;adev-&gt;dev,</div><div class='add'>+				"Failed to restore queues\n");</div><div class='ctx'> </div><div class='ctx'> 		n_evicted--;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1874,13 +1946,14 @@ int kfd_process_restore_queues(struct kfd_process *p)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; p-&gt;n_pdds; i++) {</div><div class='ctx'> 		struct kfd_process_device *pdd = p-&gt;pdds[i];</div><div class='add'>+		struct device *dev = pdd-&gt;dev-&gt;adev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 		kfd_smi_event_queue_restore(pdd-&gt;dev, p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 		r = pdd-&gt;dev-&gt;dqm-&gt;ops.restore_process_queues(pdd-&gt;dev-&gt;dqm,</div><div class='ctx'> 							      &amp;pdd-&gt;qpd);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			pr_err("Failed to restore process queues\n");</div><div class='add'>+			dev_err(dev, "Failed to restore process queues\n");</div><div class='ctx'> 			if (!ret)</div><div class='ctx'> 				ret = r;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1922,6 +1995,8 @@ static int signal_eviction_fence(struct kfd_process *p)</div><div class='ctx'> 	rcu_read_lock();</div><div class='ctx'> 	ef = dma_fence_get_rcu_safe(&amp;p-&gt;ef);</div><div class='ctx'> 	rcu_read_unlock();</div><div class='add'>+	if (!ef)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	ret = dma_fence_signal(ef);</div><div class='ctx'> 	dma_fence_put(ef);</div><div class='hunk'>@@ -1942,22 +2017,21 @@ static void evict_process_worker(struct work_struct *work)</div><div class='ctx'> 	 */</div><div class='ctx'> 	p = container_of(dwork, struct kfd_process, eviction_work);</div><div class='ctx'> </div><div class='del'>-	pr_debug("Started evicting pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+	pr_debug("Started evicting process pid %d\n", p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM);</div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		/* If another thread already signaled the eviction fence,</div><div class='ctx'> 		 * they are responsible stopping the queues and scheduling</div><div class='ctx'> 		 * the restore work.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!signal_eviction_fence(p))</div><div class='del'>-			queue_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='del'>-				msecs_to_jiffies(PROCESS_RESTORE_TIME_MS));</div><div class='del'>-		else</div><div class='add'>+		if (signal_eviction_fence(p) ||</div><div class='add'>+		    mod_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='add'>+				     msecs_to_jiffies(PROCESS_RESTORE_TIME_MS)))</div><div class='ctx'> 			kfd_process_restore_queues(p);</div><div class='ctx'> </div><div class='del'>-		pr_debug("Finished evicting pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+		pr_debug("Finished evicting process pid %d\n", p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 	} else</div><div class='del'>-		pr_err("Failed to evict queues of pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+		pr_err("Failed to evict queues of process pid %d\n", p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int restore_process_helper(struct kfd_process *p)</div><div class='hunk'>@@ -1974,9 +2048,11 @@ static int restore_process_helper(struct kfd_process *p)</div><div class='ctx'> </div><div class='ctx'> 	ret = kfd_process_restore_queues(p);</div><div class='ctx'> 	if (!ret)</div><div class='del'>-		pr_debug("Finished restoring pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+		pr_debug("Finished restoring process pid %d\n",</div><div class='add'>+			p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 	else</div><div class='del'>-		pr_err("Failed to restore queues of pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+		pr_err("Failed to restore queues of process pid %d\n",</div><div class='add'>+		      p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1993,7 +2069,7 @@ static void restore_process_worker(struct work_struct *work)</div><div class='ctx'> 	 * lifetime of this thread, kfd_process p will be valid</div><div class='ctx'> 	 */</div><div class='ctx'> 	p = container_of(dwork, struct kfd_process, restore_work);</div><div class='del'>-	pr_debug("Started restoring pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+	pr_debug("Started restoring process pasid %d\n", (int)p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 	/* Setting last_restore_timestamp before successful restoration.</div><div class='ctx'> 	 * Otherwise this would have to be set by KGD (restore_process_bos)</div><div class='hunk'>@@ -2009,11 +2085,11 @@ static void restore_process_worker(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	ret = restore_process_helper(p);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		pr_debug("Failed to restore BOs of pasid 0x%x, retry after %d ms\n",</div><div class='del'>-			 p-&gt;pasid, PROCESS_BACK_OFF_TIME_MS);</div><div class='del'>-		ret = queue_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='del'>-				msecs_to_jiffies(PROCESS_BACK_OFF_TIME_MS));</div><div class='del'>-		WARN(!ret, "reschedule restore work failed\n");</div><div class='add'>+		pr_debug("Failed to restore BOs of process pid %d, retry after %d ms\n",</div><div class='add'>+			 p-&gt;lead_thread-&gt;pid, PROCESS_BACK_OFF_TIME_MS);</div><div class='add'>+		if (mod_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='add'>+				     msecs_to_jiffies(PROCESS_RESTORE_TIME_MS)))</div><div class='add'>+			kfd_process_restore_queues(p);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2026,7 +2102,7 @@ void kfd_suspend_all_processes(void)</div><div class='ctx'> 	WARN(debug_evictions, "Evicting all processes");</div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='ctx'> 		if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND))</div><div class='del'>-			pr_err("Failed to suspend process 0x%x\n", p-&gt;pasid);</div><div class='add'>+			pr_err("Failed to suspend process pid %d\n", p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		signal_eviction_fence(p);</div><div class='ctx'> 	}</div><div class='ctx'> 	srcu_read_unlock(&amp;kfd_processes_srcu, idx);</div><div class='hunk'>@@ -2040,8 +2116,8 @@ int kfd_resume_all_processes(void)</div><div class='ctx'> </div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='ctx'> 		if (restore_process_helper(p)) {</div><div class='del'>-			pr_err("Restore process %d failed during resume\n",</div><div class='del'>-			       p-&gt;pasid);</div><div class='add'>+			pr_err("Restore process pid %d failed during resume\n",</div><div class='add'>+			      p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 			ret = -EFAULT;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2056,7 +2132,7 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process,</div><div class='ctx'> 	struct qcm_process_device *qpd;</div><div class='ctx'> </div><div class='ctx'> 	if ((vma-&gt;vm_end - vma-&gt;vm_start) != KFD_CWSR_TBA_TMA_SIZE) {</div><div class='del'>-		pr_err("Incorrect CWSR mapping size.\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev, "Incorrect CWSR mapping size.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2068,7 +2144,8 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process,</div><div class='ctx'> 	qpd-&gt;cwsr_kaddr = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,</div><div class='ctx'> 					get_order(KFD_CWSR_TBA_TMA_SIZE));</div><div class='ctx'> 	if (!qpd-&gt;cwsr_kaddr) {</div><div class='del'>-		pr_err("Error allocating per process CWSR buffer.\n");</div><div class='add'>+		dev_err(dev-&gt;adev-&gt;dev,</div><div class='add'>+			"Error allocating per process CWSR buffer.\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2095,12 +2172,14 @@ int kfd_process_drain_interrupts(struct kfd_process_device *pdd)</div><div class='ctx'> 	memset(irq_drain_fence, 0, sizeof(irq_drain_fence));</div><div class='ctx'> 	irq_drain_fence[0] = (KFD_IRQ_FENCE_SOURCEID &lt;&lt; 8) |</div><div class='ctx'> 							KFD_IRQ_FENCE_CLIENTID;</div><div class='del'>-	irq_drain_fence[3] = pdd-&gt;process-&gt;pasid;</div><div class='add'>+	irq_drain_fence[3] = pdd-&gt;pasid;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * For GFX 9.4.3, send the NodeId also in IH cookie DW[3]</div><div class='add'>+	 * For GFX 9.4.3/9.5.0, send the NodeId also in IH cookie DW[3]</div><div class='ctx'> 	 */</div><div class='del'>-	if (KFD_GC_VERSION(pdd-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 3)) {</div><div class='add'>+	if (KFD_GC_VERSION(pdd-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+	    KFD_GC_VERSION(pdd-&gt;dev-&gt;kfd) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+	    KFD_GC_VERSION(pdd-&gt;dev-&gt;kfd) == IP_VERSION(9, 5, 0)) {</div><div class='ctx'> 		node_id = ffs(pdd-&gt;dev-&gt;interrupt_bitmap) - 1;</div><div class='ctx'> 		irq_drain_fence[3] |= node_id &lt;&lt; 16;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2124,7 +2203,7 @@ void kfd_process_close_interrupt_drain(unsigned int pasid)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process *p;</div><div class='ctx'> </div><div class='del'>-	p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (!p)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -2245,8 +2324,8 @@ int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data)</div><div class='ctx'> 	int idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='ctx'> </div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='del'>-		seq_printf(m, "Process %d PASID 0x%x:\n",</div><div class='del'>-			   p-&gt;lead_thread-&gt;tgid, p-&gt;pasid);</div><div class='add'>+		seq_printf(m, "Process %d PASID %d:\n",</div><div class='add'>+			   p-&gt;lead_thread-&gt;tgid, p-&gt;lead_thread-&gt;pid);</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;p-&gt;mutex);</div><div class='ctx'> 		r = pqm_debugfs_mqds(m, &amp;p-&gt;pqm);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c<br/>index 4858112f9a53..7fbb5c274ccc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> #include "kfd_kernel_queue.h"</div><div class='ctx'> #include "amdgpu_amdkfd.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> static inline struct process_queue_node *get_queue_by_qid(</div><div class='ctx'> 			struct process_queue_manager *pqm, unsigned int qid)</div><div class='hunk'>@@ -68,8 +69,8 @@ static int find_available_queue_slot(struct process_queue_manager *pqm,</div><div class='ctx'> 	pr_debug("The new slot id %lu\n", found);</div><div class='ctx'> </div><div class='ctx'> 	if (found &gt;= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {</div><div class='del'>-		pr_info("Cannot open more queues for process with pasid 0x%x\n",</div><div class='del'>-				pqm-&gt;process-&gt;pasid);</div><div class='add'>+		pr_info("Cannot open more queues for process with pid %d\n",</div><div class='add'>+			pqm-&gt;process-&gt;lead_thread-&gt;pid);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -85,10 +86,17 @@ void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)</div><div class='ctx'> </div><div class='ctx'> 	if (pdd-&gt;already_dequeued)</div><div class='ctx'> 		return;</div><div class='del'>-</div><div class='add'>+	/* The MES context flush needs to filter out the case which the</div><div class='add'>+	 * KFD process is created without setting up the MES context and</div><div class='add'>+	 * queue for creating a compute queue.</div><div class='add'>+	 */</div><div class='ctx'> 	dev-&gt;dqm-&gt;ops.process_termination(dev-&gt;dqm, &amp;pdd-&gt;qpd);</div><div class='del'>-	if (dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-		amdgpu_mes_flush_shader_debugger(dev-&gt;adev, pdd-&gt;proc_ctx_gpu_addr);</div><div class='add'>+	if (dev-&gt;kfd-&gt;shared_resources.enable_mes &amp;&amp; !!pdd-&gt;proc_ctx_gpu_addr &amp;&amp;</div><div class='add'>+	    down_read_trylock(&amp;dev-&gt;adev-&gt;reset_domain-&gt;sem)) {</div><div class='add'>+		amdgpu_mes_flush_shader_debugger(dev-&gt;adev,</div><div class='add'>+						 pdd-&gt;proc_ctx_gpu_addr);</div><div class='add'>+		up_read(&amp;dev-&gt;adev-&gt;reset_domain-&gt;sem);</div><div class='add'>+	}</div><div class='ctx'> 	pdd-&gt;already_dequeued = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -126,7 +134,10 @@ int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,</div><div class='ctx'> 	if (!gws &amp;&amp; pdd-&gt;qpd.num_gws == 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &amp;&amp; !dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+	if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+	     KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) &amp;&amp;</div><div class='add'>+	     KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) &amp;&amp;</div><div class='add'>+	    !dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='ctx'> 		if (gws)</div><div class='ctx'> 			ret = amdgpu_amdkfd_add_gws_to_process(pdd-&gt;process-&gt;kgd_process_info,</div><div class='ctx'> 				gws, &amp;mem);</div><div class='hunk'>@@ -189,6 +200,8 @@ static void pqm_clean_queue_resource(struct process_queue_manager *pqm,</div><div class='ctx'> </div><div class='ctx'> 	if (pqn-&gt;q-&gt;gws) {</div><div class='ctx'> 		if (KFD_GC_VERSION(pqn-&gt;q-&gt;device) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+		    KFD_GC_VERSION(pqn-&gt;q-&gt;device) != IP_VERSION(9, 4, 4) &amp;&amp;</div><div class='add'>+		    KFD_GC_VERSION(pqn-&gt;q-&gt;device) != IP_VERSION(9, 5, 0) &amp;&amp;</div><div class='ctx'> 		    !dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='ctx'> 			amdgpu_amdkfd_remove_gws_from_process(</div><div class='ctx'> 				pqm-&gt;process-&gt;kgd_process_info, pqn-&gt;q-&gt;gws);</div><div class='hunk'>@@ -196,9 +209,8 @@ static void pqm_clean_queue_resource(struct process_queue_manager *pqm,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='del'>-		amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, pqn-&gt;q-&gt;gang_ctx_bo);</div><div class='del'>-		if (pqn-&gt;q-&gt;wptr_bo)</div><div class='del'>-			amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, pqn-&gt;q-&gt;wptr_bo);</div><div class='add'>+		amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, &amp;pqn-&gt;q-&gt;gang_ctx_bo);</div><div class='add'>+		amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, (void **)&amp;pqn-&gt;q-&gt;wptr_bo_gart);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -207,8 +219,17 @@ void pqm_uninit(struct process_queue_manager *pqm)</div><div class='ctx'> 	struct process_queue_node *pqn, *next;</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(pqn, next, &amp;pqm-&gt;queues, process_queue_list) {</div><div class='del'>-		if (pqn-&gt;q)</div><div class='add'>+		if (pqn-&gt;q) {</div><div class='add'>+			struct kfd_process_device *pdd = kfd_get_process_device_data(pqn-&gt;q-&gt;device,</div><div class='add'>+										     pqm-&gt;process);</div><div class='add'>+			if (pdd) {</div><div class='add'>+				kfd_queue_unref_bo_vas(pdd, &amp;pqn-&gt;q-&gt;properties);</div><div class='add'>+				kfd_queue_release_buffers(pdd, &amp;pqn-&gt;q-&gt;properties);</div><div class='add'>+			} else {</div><div class='add'>+				WARN_ON(!pdd);</div><div class='add'>+			}</div><div class='ctx'> 			pqm_clean_queue_resource(pqm, pqn);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		kfd_procfs_del_queue(pqn-&gt;q);</div><div class='ctx'> 		uninit_queue(pqn-&gt;q);</div><div class='hunk'>@@ -223,7 +244,6 @@ void pqm_uninit(struct process_queue_manager *pqm)</div><div class='ctx'> static int init_user_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 				struct kfd_node *dev, struct queue **q,</div><div class='ctx'> 				struct queue_properties *q_properties,</div><div class='del'>-				struct file *f, struct amdgpu_bo *wptr_bo,</div><div class='ctx'> 				unsigned int qid)</div><div class='ctx'> {</div><div class='ctx'> 	int retval;</div><div class='hunk'>@@ -255,12 +275,29 @@ static int init_user_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 			goto cleanup;</div><div class='ctx'> 		}</div><div class='ctx'> 		memset((*q)-&gt;gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);</div><div class='del'>-		(*q)-&gt;wptr_bo = wptr_bo;</div><div class='add'>+</div><div class='add'>+		/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work</div><div class='add'>+		 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)</div><div class='add'>+		 */</div><div class='add'>+		if (dev-&gt;adev != amdgpu_ttm_adev(q_properties-&gt;wptr_bo-&gt;tbo.bdev)) {</div><div class='add'>+			pr_err("Queue memory allocated to wrong device\n");</div><div class='add'>+			retval = -EINVAL;</div><div class='add'>+			goto free_gang_ctx_bo;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties-&gt;wptr_bo,</div><div class='add'>+							  &amp;(*q)-&gt;wptr_bo_gart);</div><div class='add'>+		if (retval) {</div><div class='add'>+			pr_err("Failed to map wptr bo to GART\n");</div><div class='add'>+			goto free_gang_ctx_bo;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("PQM After init queue");</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+free_gang_ctx_bo:</div><div class='add'>+	amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, &amp;(*q)-&gt;gang_ctx_bo);</div><div class='ctx'> cleanup:</div><div class='ctx'> 	uninit_queue(*q);</div><div class='ctx'> 	*q = NULL;</div><div class='hunk'>@@ -269,10 +306,8 @@ cleanup:</div><div class='ctx'> </div><div class='ctx'> int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 			    struct kfd_node *dev,</div><div class='del'>-			    struct file *f,</div><div class='ctx'> 			    struct queue_properties *properties,</div><div class='ctx'> 			    unsigned int *qid,</div><div class='del'>-			    struct amdgpu_bo *wptr_bo,</div><div class='ctx'> 			    const struct kfd_criu_queue_priv_data *q_data,</div><div class='ctx'> 			    const void *restore_mqd,</div><div class='ctx'> 			    const void *restore_ctl_stack,</div><div class='hunk'>@@ -287,10 +322,12 @@ int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 	unsigned int max_queues = 127; /* HWS limit */</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * On GFX 9.4.3, increase the number of queues that</div><div class='del'>-	 * can be created to 255. No HWS limit on GFX 9.4.3.</div><div class='add'>+	 * On GFX 9.4.3/9.5.0, increase the number of queues that</div><div class='add'>+	 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0.</div><div class='ctx'> 	 */</div><div class='del'>-	if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3))</div><div class='add'>+	if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+	    KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+	    KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))</div><div class='ctx'> 		max_queues = 255;</div><div class='ctx'> </div><div class='ctx'> 	q = NULL;</div><div class='hunk'>@@ -323,10 +360,26 @@ int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 	if (retval != 0)</div><div class='ctx'> 		return retval;</div><div class='ctx'> </div><div class='add'>+	/* Register process if this is the first queue */</div><div class='ctx'> 	if (list_empty(&amp;pdd-&gt;qpd.queues_list) &amp;&amp;</div><div class='ctx'> 	    list_empty(&amp;pdd-&gt;qpd.priv_queue_list))</div><div class='ctx'> 		dev-&gt;dqm-&gt;ops.register_process(dev-&gt;dqm, &amp;pdd-&gt;qpd);</div><div class='ctx'> </div><div class='add'>+	/* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */</div><div class='add'>+	if (!pdd-&gt;proc_ctx_cpu_ptr &amp;&amp; dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+		retval = amdgpu_amdkfd_alloc_gtt_mem(dev-&gt;adev,</div><div class='add'>+						     AMDGPU_MES_PROC_CTX_SIZE,</div><div class='add'>+						     &amp;pdd-&gt;proc_ctx_bo,</div><div class='add'>+						     &amp;pdd-&gt;proc_ctx_gpu_addr,</div><div class='add'>+						     &amp;pdd-&gt;proc_ctx_cpu_ptr,</div><div class='add'>+						     false);</div><div class='add'>+		if (retval) {</div><div class='add'>+			dev_err(dev-&gt;adev-&gt;dev, "failed to allocate process context bo\n");</div><div class='add'>+			return retval;</div><div class='add'>+		}</div><div class='add'>+		memset(pdd-&gt;proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pqn = kzalloc(sizeof(*pqn), GFP_KERNEL);</div><div class='ctx'> 	if (!pqn) {</div><div class='ctx'> 		retval = -ENOMEM;</div><div class='hunk'>@@ -336,13 +389,14 @@ int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 	switch (type) {</div><div class='ctx'> 	case KFD_QUEUE_TYPE_SDMA:</div><div class='ctx'> 	case KFD_QUEUE_TYPE_SDMA_XGMI:</div><div class='add'>+	case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID:</div><div class='ctx'> 		/* SDMA queues are always allocated statically no matter</div><div class='ctx'> 		 * which scheduler mode is used. We also do not need to</div><div class='ctx'> 		 * check whether a SDMA queue can be allocated here, because</div><div class='ctx'> 		 * allocate_sdma_queue() in create_queue() has the</div><div class='ctx'> 		 * corresponding check logic.</div><div class='ctx'> 		 */</div><div class='del'>-		retval = init_user_queue(pqm, dev, &amp;q, properties, f, wptr_bo, *qid);</div><div class='add'>+		retval = init_user_queue(pqm, dev, &amp;q, properties, *qid);</div><div class='ctx'> 		if (retval != 0)</div><div class='ctx'> 			goto err_create_queue;</div><div class='ctx'> 		pqn-&gt;q = q;</div><div class='hunk'>@@ -363,7 +417,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 			goto err_create_queue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		retval = init_user_queue(pqm, dev, &amp;q, properties, f, wptr_bo, *qid);</div><div class='add'>+		retval = init_user_queue(pqm, dev, &amp;q, properties, *qid);</div><div class='ctx'> 		if (retval != 0)</div><div class='ctx'> 			goto err_create_queue;</div><div class='ctx'> 		pqn-&gt;q = q;</div><div class='hunk'>@@ -394,8 +448,15 @@ int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (retval != 0) {</div><div class='del'>-		pr_err("Pasid 0x%x DQM create queue type %d failed. ret %d\n",</div><div class='del'>-			pqm-&gt;process-&gt;pasid, type, retval);</div><div class='add'>+		if ((type == KFD_QUEUE_TYPE_SDMA ||</div><div class='add'>+		    type == KFD_QUEUE_TYPE_SDMA_XGMI ||</div><div class='add'>+		    type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) &amp;&amp;</div><div class='add'>+		    retval == -ENOMEM)</div><div class='add'>+			pr_warn("process pid %d DQM create queue type %d failed. ret %d\n",</div><div class='add'>+				pqm-&gt;process-&gt;lead_thread-&gt;pid, type, retval);</div><div class='add'>+		else</div><div class='add'>+			pr_err("process pid %d DQM create queue type %d failed. ret %d\n",</div><div class='add'>+				pqm-&gt;process-&gt;lead_thread-&gt;pid, type, retval);</div><div class='ctx'> 		goto err_create_queue;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -430,7 +491,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,</div><div class='ctx'> err_create_queue:</div><div class='ctx'> 	uninit_queue(q);</div><div class='ctx'> 	if (kq)</div><div class='del'>-		kernel_queue_uninit(kq, false);</div><div class='add'>+		kernel_queue_uninit(kq);</div><div class='ctx'> 	kfree(pqn);</div><div class='ctx'> err_allocate_pqn:</div><div class='ctx'> 	/* check if queues list is empty unregister process from device */</div><div class='hunk'>@@ -477,21 +538,25 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)</div><div class='ctx'> 		/* destroy kernel queue (DIQ) */</div><div class='ctx'> 		dqm = pqn-&gt;kq-&gt;dev-&gt;dqm;</div><div class='ctx'> 		dqm-&gt;ops.destroy_kernel_queue(dqm, pqn-&gt;kq, &amp;pdd-&gt;qpd);</div><div class='del'>-		kernel_queue_uninit(pqn-&gt;kq, false);</div><div class='add'>+		kernel_queue_uninit(pqn-&gt;kq);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pqn-&gt;q) {</div><div class='del'>-		kfd_procfs_del_queue(pqn-&gt;q);</div><div class='add'>+		retval = kfd_queue_unref_bo_vas(pdd, &amp;pqn-&gt;q-&gt;properties);</div><div class='add'>+		if (retval)</div><div class='add'>+			goto err_destroy_queue;</div><div class='add'>+</div><div class='ctx'> 		dqm = pqn-&gt;q-&gt;device-&gt;dqm;</div><div class='ctx'> 		retval = dqm-&gt;ops.destroy_queue(dqm, &amp;pdd-&gt;qpd, pqn-&gt;q);</div><div class='ctx'> 		if (retval) {</div><div class='ctx'> 			pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n",</div><div class='del'>-				pqm-&gt;process-&gt;pasid,</div><div class='add'>+				pdd-&gt;pasid,</div><div class='ctx'> 				pqn-&gt;q-&gt;properties.queue_id, retval);</div><div class='del'>-			if (retval != -ETIME)</div><div class='add'>+			if (retval != -ETIME &amp;&amp; retval != -EIO)</div><div class='ctx'> 				goto err_destroy_queue;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='add'>+		kfd_procfs_del_queue(pqn-&gt;q);</div><div class='add'>+		kfd_queue_release_buffers(pdd, &amp;pqn-&gt;q-&gt;properties);</div><div class='ctx'> 		pqm_clean_queue_resource(pqm, pqn);</div><div class='ctx'> 		uninit_queue(pqn-&gt;q);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -515,11 +580,42 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm,</div><div class='ctx'> 	struct process_queue_node *pqn;</div><div class='ctx'> </div><div class='ctx'> 	pqn = get_queue_by_qid(pqm, qid);</div><div class='del'>-	if (!pqn) {</div><div class='add'>+	if (!pqn || !pqn-&gt;q) {</div><div class='ctx'> 		pr_debug("No queue %d exists for update operation\n", qid);</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Update with NULL ring address is used to disable the queue</div><div class='add'>+	 */</div><div class='add'>+	if (p-&gt;queue_address &amp;&amp; p-&gt;queue_size) {</div><div class='add'>+		struct kfd_process_device *pdd;</div><div class='add'>+		struct amdgpu_vm *vm;</div><div class='add'>+		struct queue *q = pqn-&gt;q;</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		pdd = kfd_get_process_device_data(q-&gt;device, q-&gt;process);</div><div class='add'>+		if (!pdd)</div><div class='add'>+			return -ENODEV;</div><div class='add'>+		vm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='add'>+		err = amdgpu_bo_reserve(vm-&gt;root.bo, false);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		if (kfd_queue_buffer_get(vm, (void *)p-&gt;queue_address, &amp;p-&gt;ring_bo,</div><div class='add'>+					 p-&gt;queue_size)) {</div><div class='add'>+			pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n",</div><div class='add'>+				 p-&gt;queue_address, p-&gt;queue_size);</div><div class='add'>+			return -EFAULT;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		kfd_queue_unref_bo_va(vm, &amp;pqn-&gt;q-&gt;properties.ring_bo);</div><div class='add'>+		kfd_queue_buffer_put(&amp;pqn-&gt;q-&gt;properties.ring_bo);</div><div class='add'>+		amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+</div><div class='add'>+		pqn-&gt;q-&gt;properties.ring_bo = p-&gt;ring_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pqn-&gt;q-&gt;properties.queue_address = p-&gt;queue_address;</div><div class='ctx'> 	pqn-&gt;q-&gt;properties.queue_size = p-&gt;queue_size;</div><div class='ctx'> 	pqn-&gt;q-&gt;properties.queue_percent = p-&gt;queue_percent;</div><div class='hunk'>@@ -576,19 +672,6 @@ int pqm_update_mqd(struct process_queue_manager *pqm,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct kernel_queue *pqm_get_kernel_queue(</div><div class='del'>-					struct process_queue_manager *pqm,</div><div class='del'>-					unsigned int qid)</div><div class='del'>-{</div><div class='del'>-	struct process_queue_node *pqn;</div><div class='del'>-</div><div class='del'>-	pqn = get_queue_by_qid(pqm, qid);</div><div class='del'>-	if (pqn &amp;&amp; pqn-&gt;kq)</div><div class='del'>-		return pqn-&gt;kq;</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,</div><div class='ctx'> 					unsigned int qid)</div><div class='ctx'> {</div><div class='hunk'>@@ -831,7 +914,10 @@ static int criu_checkpoint_queues_device(struct kfd_process_device *pdd,</div><div class='ctx'> </div><div class='ctx'> 		q_data = (struct kfd_criu_queue_priv_data *)q_private_data;</div><div class='ctx'> </div><div class='del'>-		/* data stored in this order: priv_data, mqd, ctl_stack */</div><div class='add'>+		/*</div><div class='add'>+		 * data stored in this order:</div><div class='add'>+		 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...</div><div class='add'>+		 */</div><div class='ctx'> 		q_data-&gt;mqd_size = mqd_size;</div><div class='ctx'> 		q_data-&gt;ctl_stack_size = ctl_stack_size;</div><div class='ctx'> </div><div class='hunk'>@@ -880,7 +966,7 @@ int kfd_criu_checkpoint_queues(struct kfd_process *p,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void set_queue_properties_from_criu(struct queue_properties *qp,</div><div class='del'>-					  struct kfd_criu_queue_priv_data *q_data)</div><div class='add'>+					  struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc)</div><div class='ctx'> {</div><div class='ctx'> 	qp-&gt;is_interop = false;</div><div class='ctx'> 	qp-&gt;queue_percent = q_data-&gt;q_percent;</div><div class='hunk'>@@ -893,7 +979,11 @@ static void set_queue_properties_from_criu(struct queue_properties *qp,</div><div class='ctx'> 	qp-&gt;eop_ring_buffer_size = q_data-&gt;eop_ring_buffer_size;</div><div class='ctx'> 	qp-&gt;ctx_save_restore_area_address = q_data-&gt;ctx_save_restore_area_address;</div><div class='ctx'> 	qp-&gt;ctx_save_restore_area_size = q_data-&gt;ctx_save_restore_area_size;</div><div class='del'>-	qp-&gt;ctl_stack_size = q_data-&gt;ctl_stack_size;</div><div class='add'>+	if (q_data-&gt;type == KFD_QUEUE_TYPE_COMPUTE)</div><div class='add'>+		qp-&gt;ctl_stack_size = q_data-&gt;ctl_stack_size / num_xcc;</div><div class='add'>+	else</div><div class='add'>+		qp-&gt;ctl_stack_size = q_data-&gt;ctl_stack_size;</div><div class='add'>+</div><div class='ctx'> 	qp-&gt;type = q_data-&gt;type;</div><div class='ctx'> 	qp-&gt;format = q_data-&gt;format;</div><div class='ctx'> }</div><div class='hunk'>@@ -953,17 +1043,19 @@ int kfd_criu_restore_queue(struct kfd_process *p,</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* data stored in this order: mqd, ctl_stack */</div><div class='add'>+	/*</div><div class='add'>+	 * data stored in this order:</div><div class='add'>+	 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]...</div><div class='add'>+	 */</div><div class='ctx'> 	mqd = q_extra_data;</div><div class='ctx'> 	ctl_stack = mqd + q_data-&gt;mqd_size;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;qp, 0, sizeof(qp));</div><div class='del'>-	set_queue_properties_from_criu(&amp;qp, q_data);</div><div class='add'>+	set_queue_properties_from_criu(&amp;qp, q_data, NUM_XCC(pdd-&gt;dev-&gt;adev-&gt;gfx.xcc_mask));</div><div class='ctx'> </div><div class='ctx'> 	print_queue_properties(&amp;qp);</div><div class='ctx'> </div><div class='del'>-	ret = pqm_create_queue(&amp;p-&gt;pqm, pdd-&gt;dev, NULL, &amp;qp, &amp;queue_id, NULL, q_data, mqd, ctl_stack,</div><div class='del'>-				NULL);</div><div class='add'>+	ret = pqm_create_queue(&amp;p-&gt;pqm, pdd-&gt;dev, &amp;qp, &amp;queue_id, q_data, mqd, ctl_stack, NULL);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pr_err("Failed to create new queue err:%d\n", ret);</div><div class='ctx'> 		goto exit;</div><div class='hunk'>@@ -979,6 +1071,7 @@ exit:</div><div class='ctx'> 		pr_debug("Queue id %d was restored successfully\n", queue_id);</div><div class='ctx'> </div><div class='ctx'> 	kfree(q_data);</div><div class='add'>+	kfree(q_extra_data);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c<br/>index 0f6992b1895c..f1e7583650c4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_queue.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_queue.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_queue.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_queue.c</a></div><div class='hunk'>@@ -24,6 +24,8 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include "kfd_priv.h"</div><div class='add'>+#include "kfd_topology.h"</div><div class='add'>+#include "kfd_svm.h"</div><div class='ctx'> </div><div class='ctx'> void print_queue_properties(struct queue_properties *q)</div><div class='ctx'> {</div><div class='hunk'>@@ -82,3 +84,386 @@ void uninit_queue(struct queue *q)</div><div class='ctx'> {</div><div class='ctx'> 	kfree(q);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_HSA_AMD_SVM)</div><div class='add'>+</div><div class='add'>+static int kfd_queue_buffer_svm_get(struct kfd_process_device *pdd, u64 addr, u64 size)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process *p = pdd-&gt;process;</div><div class='add'>+	struct list_head update_list;</div><div class='add'>+	struct svm_range *prange;</div><div class='add'>+	int ret = -EINVAL;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;update_list);</div><div class='add'>+	addr &gt;&gt;= PAGE_SHIFT;</div><div class='add'>+	size &gt;&gt;= PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;p-&gt;svms.lock);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * range may split to multiple svm pranges aligned to granularity boundaery.</div><div class='add'>+	 */</div><div class='add'>+	while (size) {</div><div class='add'>+		uint32_t gpuid, gpuidx;</div><div class='add'>+		int r;</div><div class='add'>+</div><div class='add'>+		prange = svm_range_from_addr(&amp;p-&gt;svms, addr, NULL);</div><div class='add'>+		if (!prange)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (!prange-&gt;mapped_to_gpu)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		r = kfd_process_gpuid_from_node(p, pdd-&gt;dev, &amp;gpuid, &amp;gpuidx);</div><div class='add'>+		if (r &lt; 0)</div><div class='add'>+			break;</div><div class='add'>+		if (!test_bit(gpuidx, prange-&gt;bitmap_access) &amp;&amp;</div><div class='add'>+		    !test_bit(gpuidx, prange-&gt;bitmap_aip))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (!(prange-&gt;flags &amp; KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		list_add(&amp;prange-&gt;update_list, &amp;update_list);</div><div class='add'>+</div><div class='add'>+		if (prange-&gt;last - prange-&gt;start + 1 &gt;= size) {</div><div class='add'>+			size = 0;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		size -= prange-&gt;last - prange-&gt;start + 1;</div><div class='add'>+		addr += prange-&gt;last - prange-&gt;start + 1;</div><div class='add'>+	}</div><div class='add'>+	if (size) {</div><div class='add'>+		pr_debug("[0x%llx 0x%llx] not registered\n", addr, addr + size - 1);</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(prange, &amp;update_list, update_list)</div><div class='add'>+		atomic_inc(&amp;prange-&gt;queue_refcount);</div><div class='add'>+	ret = 0;</div><div class='add'>+</div><div class='add'>+out_unlock:</div><div class='add'>+	mutex_unlock(&amp;p-&gt;svms.lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void kfd_queue_buffer_svm_put(struct kfd_process_device *pdd, u64 addr, u64 size)</div><div class='add'>+{</div><div class='add'>+	struct kfd_process *p = pdd-&gt;process;</div><div class='add'>+	struct svm_range *prange, *pchild;</div><div class='add'>+	struct interval_tree_node *node;</div><div class='add'>+	unsigned long last;</div><div class='add'>+</div><div class='add'>+	addr &gt;&gt;= PAGE_SHIFT;</div><div class='add'>+	last = addr + (size &gt;&gt; PAGE_SHIFT) - 1;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;p-&gt;svms.lock);</div><div class='add'>+</div><div class='add'>+	node = interval_tree_iter_first(&amp;p-&gt;svms.objects, addr, last);</div><div class='add'>+	while (node) {</div><div class='add'>+		struct interval_tree_node *next_node;</div><div class='add'>+		unsigned long next_start;</div><div class='add'>+</div><div class='add'>+		prange = container_of(node, struct svm_range, it_node);</div><div class='add'>+		next_node = interval_tree_iter_next(node, addr, last);</div><div class='add'>+		next_start = min(node-&gt;last, last) + 1;</div><div class='add'>+</div><div class='add'>+		if (atomic_add_unless(&amp;prange-&gt;queue_refcount, -1, 0)) {</div><div class='add'>+			list_for_each_entry(pchild, &amp;prange-&gt;child_list, child_list)</div><div class='add'>+				atomic_add_unless(&amp;pchild-&gt;queue_refcount, -1, 0);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		node = next_node;</div><div class='add'>+		addr = next_start;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;p-&gt;svms.lock);</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+</div><div class='add'>+static int kfd_queue_buffer_svm_get(struct kfd_process_device *pdd, u64 addr, u64 size)</div><div class='add'>+{</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void kfd_queue_buffer_svm_put(struct kfd_process_device *pdd, u64 addr, u64 size)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo,</div><div class='add'>+			 u64 expected_size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo_va_mapping *mapping;</div><div class='add'>+	u64 user_addr;</div><div class='add'>+	u64 size;</div><div class='add'>+</div><div class='add'>+	user_addr = (u64)addr &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+	size = expected_size &gt;&gt; AMDGPU_GPU_PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	mapping = amdgpu_vm_bo_lookup_mapping(vm, user_addr);</div><div class='add'>+	if (!mapping)</div><div class='add'>+		goto out_err;</div><div class='add'>+</div><div class='add'>+	if (user_addr != mapping-&gt;start ||</div><div class='add'>+	    (size != 0 &amp;&amp; user_addr + size - 1 != mapping-&gt;last)) {</div><div class='add'>+		pr_debug("expected size 0x%llx not equal to mapping addr 0x%llx size 0x%llx\n",</div><div class='add'>+			expected_size, mapping-&gt;start &lt;&lt; AMDGPU_GPU_PAGE_SHIFT,</div><div class='add'>+			(mapping-&gt;last - mapping-&gt;start + 1) &lt;&lt; AMDGPU_GPU_PAGE_SHIFT);</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*pbo = amdgpu_bo_ref(mapping-&gt;bo_va-&gt;base.bo);</div><div class='add'>+	mapping-&gt;bo_va-&gt;queue_refcount++;</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out_err:</div><div class='add'>+	*pbo = NULL;</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* FIXME: remove this function, just call amdgpu_bo_unref directly */</div><div class='add'>+void kfd_queue_buffer_put(struct amdgpu_bo **bo)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_unref(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties)</div><div class='add'>+{</div><div class='add'>+	struct kfd_topology_device *topo_dev;</div><div class='add'>+	u64 expected_queue_size;</div><div class='add'>+	struct amdgpu_vm *vm;</div><div class='add'>+	u32 total_cwsr_size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	topo_dev = kfd_topology_device_by_id(pdd-&gt;dev-&gt;id);</div><div class='add'>+	if (!topo_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* AQL queues on GFX7 and GFX8 appear twice their actual size */</div><div class='add'>+	if (properties-&gt;type == KFD_QUEUE_TYPE_COMPUTE &amp;&amp;</div><div class='add'>+	    properties-&gt;format == KFD_QUEUE_FORMAT_AQL &amp;&amp;</div><div class='add'>+	    topo_dev-&gt;node_props.gfx_target_version &gt;= 70000 &amp;&amp;</div><div class='add'>+	    topo_dev-&gt;node_props.gfx_target_version &lt; 90000)</div><div class='add'>+		expected_queue_size = properties-&gt;queue_size / 2;</div><div class='add'>+	else</div><div class='add'>+		expected_queue_size = properties-&gt;queue_size;</div><div class='add'>+</div><div class='add'>+	vm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='add'>+	err = amdgpu_bo_reserve(vm-&gt;root.bo, false);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = kfd_queue_buffer_get(vm, properties-&gt;write_ptr, &amp;properties-&gt;wptr_bo, PAGE_SIZE);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_err_unreserve;</div><div class='add'>+</div><div class='add'>+	err = kfd_queue_buffer_get(vm, properties-&gt;read_ptr, &amp;properties-&gt;rptr_bo, PAGE_SIZE);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_err_unreserve;</div><div class='add'>+</div><div class='add'>+	err = kfd_queue_buffer_get(vm, (void *)properties-&gt;queue_address,</div><div class='add'>+				   &amp;properties-&gt;ring_bo, expected_queue_size);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_err_unreserve;</div><div class='add'>+</div><div class='add'>+	/* only compute queue requires EOP buffer and CWSR area */</div><div class='add'>+	if (properties-&gt;type != KFD_QUEUE_TYPE_COMPUTE)</div><div class='add'>+		goto out_unreserve;</div><div class='add'>+</div><div class='add'>+	/* EOP buffer is not required for all ASICs */</div><div class='add'>+	if (properties-&gt;eop_ring_buffer_address) {</div><div class='add'>+		if (properties-&gt;eop_ring_buffer_size != topo_dev-&gt;node_props.eop_buffer_size) {</div><div class='add'>+			pr_debug("queue eop bo size 0x%x not equal to node eop buf size 0x%x\n",</div><div class='add'>+				properties-&gt;eop_ring_buffer_size,</div><div class='add'>+				topo_dev-&gt;node_props.eop_buffer_size);</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto out_err_unreserve;</div><div class='add'>+		}</div><div class='add'>+		err = kfd_queue_buffer_get(vm, (void *)properties-&gt;eop_ring_buffer_address,</div><div class='add'>+					   &amp;properties-&gt;eop_buf_bo,</div><div class='add'>+					   properties-&gt;eop_ring_buffer_size);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out_err_unreserve;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (properties-&gt;ctl_stack_size != topo_dev-&gt;node_props.ctl_stack_size) {</div><div class='add'>+		pr_debug("queue ctl stack size 0x%x not equal to node ctl stack size 0x%x\n",</div><div class='add'>+			properties-&gt;ctl_stack_size,</div><div class='add'>+			topo_dev-&gt;node_props.ctl_stack_size);</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto out_err_unreserve;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (properties-&gt;ctx_save_restore_area_size &lt; topo_dev-&gt;node_props.cwsr_size) {</div><div class='add'>+		pr_debug("queue cwsr size 0x%x not sufficient for node cwsr size 0x%x\n",</div><div class='add'>+			properties-&gt;ctx_save_restore_area_size,</div><div class='add'>+			topo_dev-&gt;node_props.cwsr_size);</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto out_err_unreserve;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	total_cwsr_size = (properties-&gt;ctx_save_restore_area_size +</div><div class='add'>+			   topo_dev-&gt;node_props.debug_memory_size) * NUM_XCC(pdd-&gt;dev-&gt;xcc_mask);</div><div class='add'>+	total_cwsr_size = ALIGN(total_cwsr_size, PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	err = kfd_queue_buffer_get(vm, (void *)properties-&gt;ctx_save_restore_area_address,</div><div class='add'>+				   &amp;properties-&gt;cwsr_bo, total_cwsr_size);</div><div class='add'>+	if (!err)</div><div class='add'>+		goto out_unreserve;</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+</div><div class='add'>+	err = kfd_queue_buffer_svm_get(pdd, properties-&gt;ctx_save_restore_area_address,</div><div class='add'>+				       total_cwsr_size);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_err_release;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out_unreserve:</div><div class='add'>+	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out_err_unreserve:</div><div class='add'>+	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+out_err_release:</div><div class='add'>+	/* FIXME: make a _locked version of this that can be called before</div><div class='add'>+	 * dropping the VM reservation.</div><div class='add'>+	 */</div><div class='add'>+	kfd_queue_unref_bo_vas(pdd, properties);</div><div class='add'>+	kfd_queue_release_buffers(pdd, properties);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties)</div><div class='add'>+{</div><div class='add'>+	struct kfd_topology_device *topo_dev;</div><div class='add'>+	u32 total_cwsr_size;</div><div class='add'>+</div><div class='add'>+	kfd_queue_buffer_put(&amp;properties-&gt;wptr_bo);</div><div class='add'>+	kfd_queue_buffer_put(&amp;properties-&gt;rptr_bo);</div><div class='add'>+	kfd_queue_buffer_put(&amp;properties-&gt;ring_bo);</div><div class='add'>+	kfd_queue_buffer_put(&amp;properties-&gt;eop_buf_bo);</div><div class='add'>+	kfd_queue_buffer_put(&amp;properties-&gt;cwsr_bo);</div><div class='add'>+</div><div class='add'>+	topo_dev = kfd_topology_device_by_id(pdd-&gt;dev-&gt;id);</div><div class='add'>+	if (!topo_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	total_cwsr_size = (properties-&gt;ctx_save_restore_area_size +</div><div class='add'>+			   topo_dev-&gt;node_props.debug_memory_size) * NUM_XCC(pdd-&gt;dev-&gt;xcc_mask);</div><div class='add'>+	total_cwsr_size = ALIGN(total_cwsr_size, PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	kfd_queue_buffer_svm_put(pdd, properties-&gt;ctx_save_restore_area_address, total_cwsr_size);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo)</div><div class='add'>+{</div><div class='add'>+	if (*bo) {</div><div class='add'>+		struct amdgpu_bo_va *bo_va;</div><div class='add'>+</div><div class='add'>+		bo_va = amdgpu_vm_bo_find(vm, *bo);</div><div class='add'>+		if (bo_va &amp;&amp; bo_va-&gt;queue_refcount)</div><div class='add'>+			bo_va-&gt;queue_refcount--;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd,</div><div class='add'>+			   struct queue_properties *properties)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm *vm;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	vm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='add'>+	err = amdgpu_bo_reserve(vm-&gt;root.bo, false);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	kfd_queue_unref_bo_va(vm, &amp;properties-&gt;wptr_bo);</div><div class='add'>+	kfd_queue_unref_bo_va(vm, &amp;properties-&gt;rptr_bo);</div><div class='add'>+	kfd_queue_unref_bo_va(vm, &amp;properties-&gt;ring_bo);</div><div class='add'>+	kfd_queue_unref_bo_va(vm, &amp;properties-&gt;eop_buf_bo);</div><div class='add'>+	kfd_queue_unref_bo_va(vm, &amp;properties-&gt;cwsr_bo);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(vm-&gt;root.bo);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define SGPR_SIZE_PER_CU	0x4000</div><div class='add'>+#define LDS_SIZE_PER_CU		0x10000</div><div class='add'>+#define HWREG_SIZE_PER_CU	0x1000</div><div class='add'>+#define DEBUGGER_BYTES_ALIGN	64</div><div class='add'>+#define DEBUGGER_BYTES_PER_WAVE	32</div><div class='add'>+</div><div class='add'>+static u32 kfd_get_vgpr_size_per_cu(u32 gfxv)</div><div class='add'>+{</div><div class='add'>+	u32 vgpr_size = 0x40000;</div><div class='add'>+</div><div class='add'>+	if (gfxv == 90402 ||			/* GFX_VERSION_AQUA_VANJARAM */</div><div class='add'>+	    gfxv == 90010 ||			/* GFX_VERSION_ALDEBARAN */</div><div class='add'>+	    gfxv == 90008 ||			/* GFX_VERSION_ARCTURUS */</div><div class='add'>+	    gfxv == 90500)</div><div class='add'>+		vgpr_size = 0x80000;</div><div class='add'>+	else if (gfxv == 110000 ||		/* GFX_VERSION_PLUM_BONITO */</div><div class='add'>+		 gfxv == 110001 ||		/* GFX_VERSION_WHEAT_NAS */</div><div class='add'>+		 gfxv == 120000 ||		/* GFX_VERSION_GFX1200 */</div><div class='add'>+		 gfxv == 120001)		/* GFX_VERSION_GFX1201 */</div><div class='add'>+		vgpr_size = 0x60000;</div><div class='add'>+</div><div class='add'>+	return vgpr_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define WG_CONTEXT_DATA_SIZE_PER_CU(gfxv, props)	\</div><div class='add'>+	(kfd_get_vgpr_size_per_cu(gfxv) + SGPR_SIZE_PER_CU +\</div><div class='add'>+	 (((gfxv) == 90500) ? (props-&gt;lds_size_in_kb &lt;&lt; 10) : LDS_SIZE_PER_CU) +\</div><div class='add'>+	 HWREG_SIZE_PER_CU)</div><div class='add'>+</div><div class='add'>+#define CNTL_STACK_BYTES_PER_WAVE(gfxv)	\</div><div class='add'>+	((gfxv) &gt;= 100100 ? 12 : 8)	/* GFX_VERSION_NAVI10*/</div><div class='add'>+</div><div class='add'>+#define SIZEOF_HSA_USER_CONTEXT_SAVE_AREA_HEADER 40</div><div class='add'>+</div><div class='add'>+void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node_properties *props = &amp;dev-&gt;node_props;</div><div class='add'>+	u32 gfxv = props-&gt;gfx_target_version;</div><div class='add'>+	u32 ctl_stack_size;</div><div class='add'>+	u32 wg_data_size;</div><div class='add'>+	u32 wave_num;</div><div class='add'>+	u32 cu_num;</div><div class='add'>+</div><div class='add'>+	if (gfxv &lt; 80001)	/* GFX_VERSION_CARRIZO */</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cu_num = props-&gt;simd_count / props-&gt;simd_per_cu / NUM_XCC(dev-&gt;gpu-&gt;xcc_mask);</div><div class='add'>+	wave_num = (gfxv &lt; 100100) ?	/* GFX_VERSION_NAVI10 */</div><div class='add'>+		    min(cu_num * 40, props-&gt;array_count / props-&gt;simd_arrays_per_engine * 512)</div><div class='add'>+		    : cu_num * 32;</div><div class='add'>+</div><div class='add'>+	wg_data_size = ALIGN(cu_num * WG_CONTEXT_DATA_SIZE_PER_CU(gfxv, props), PAGE_SIZE);</div><div class='add'>+	ctl_stack_size = wave_num * CNTL_STACK_BYTES_PER_WAVE(gfxv) + 8;</div><div class='add'>+	ctl_stack_size = ALIGN(SIZEOF_HSA_USER_CONTEXT_SAVE_AREA_HEADER + ctl_stack_size,</div><div class='add'>+			       PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	if ((gfxv / 10000 * 10000) == 100000) {</div><div class='add'>+		/* HW design limits control stack size to 0x7000.</div><div class='add'>+		 * This is insufficient for theoretical PM4 cases</div><div class='add'>+		 * but sufficient for AQL, limited by SPI events.</div><div class='add'>+		 */</div><div class='add'>+		ctl_stack_size = min(ctl_stack_size, 0x7000);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	props-&gt;ctl_stack_size = ctl_stack_size;</div><div class='add'>+	props-&gt;debug_memory_size = ALIGN(wave_num * DEBUGGER_BYTES_PER_WAVE, DEBUGGER_BYTES_ALIGN);</div><div class='add'>+	props-&gt;cwsr_size = ctl_stack_size + wg_data_size;</div><div class='add'>+</div><div class='add'>+	if (gfxv == 80002)	/* GFX_VERSION_TONGA */</div><div class='add'>+		props-&gt;eop_buffer_size = 0x8000;</div><div class='add'>+	else if (gfxv == 90402)	/* GFX_VERSION_AQUA_VANJARAM */</div><div class='add'>+		props-&gt;eop_buffer_size = 4096;</div><div class='add'>+	else if (gfxv &gt;= 80000)</div><div class='add'>+		props-&gt;eop_buffer_size = 4096;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c<br/>index 06ac835190f9..a499449fcb06 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "amdgpu_vm.h"</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> #include "kfd_smi_events.h"</div><div class='add'>+#include "amdgpu_reset.h"</div><div class='ctx'> </div><div class='ctx'> struct kfd_smi_client {</div><div class='ctx'> 	struct list_head list;</div><div class='hunk'>@@ -43,7 +44,7 @@ struct kfd_smi_client {</div><div class='ctx'> 	bool suser;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define MAX_KFIFO_SIZE	1024</div><div class='add'>+#define KFD_MAX_KFIFO_SIZE	8192</div><div class='ctx'> </div><div class='ctx'> static __poll_t kfd_smi_ev_poll(struct file *, struct poll_table_struct *);</div><div class='ctx'> static ssize_t kfd_smi_ev_read(struct file *, char __user *, size_t, loff_t *);</div><div class='hunk'>@@ -85,7 +86,7 @@ static ssize_t kfd_smi_ev_read(struct file *filep, char __user *user,</div><div class='ctx'> 	struct kfd_smi_client *client = filep-&gt;private_data;</div><div class='ctx'> 	unsigned char *buf;</div><div class='ctx'> </div><div class='del'>-	size = min_t(size_t, size, MAX_KFIFO_SIZE);</div><div class='add'>+	size = min_t(size_t, size, KFD_MAX_KFIFO_SIZE);</div><div class='ctx'> 	buf = kmalloc(size, GFP_KERNEL);</div><div class='ctx'> 	if (!buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -162,10 +163,9 @@ static int kfd_smi_ev_release(struct inode *inode, struct file *filep)</div><div class='ctx'> static bool kfd_smi_ev_enabled(pid_t pid, struct kfd_smi_client *client,</div><div class='ctx'> 			       unsigned int event)</div><div class='ctx'> {</div><div class='del'>-	uint64_t all = KFD_SMI_EVENT_MASK_FROM_INDEX(KFD_SMI_EVENT_ALL_PROCESS);</div><div class='ctx'> 	uint64_t events = READ_ONCE(client-&gt;events);</div><div class='ctx'> </div><div class='del'>-	if (pid &amp;&amp; client-&gt;pid != pid &amp;&amp; !(client-&gt;suser &amp;&amp; (events &amp; all)))</div><div class='add'>+	if (pid &amp;&amp; client-&gt;pid != pid &amp;&amp; !client-&gt;suser)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	return events &amp; KFD_SMI_EVENT_MASK_FROM_INDEX(event);</div><div class='hunk'>@@ -215,9 +215,11 @@ static void kfd_smi_event_add(pid_t pid, struct kfd_node *dev,</div><div class='ctx'> 	add_event_to_kfifo(pid, dev, event, fifo_in, len);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset)</div><div class='add'>+void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset,</div><div class='add'>+				    struct amdgpu_reset_context *reset_context)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int event;</div><div class='add'>+	char reset_cause[64];</div><div class='ctx'> </div><div class='ctx'> 	if (post_reset) {</div><div class='ctx'> 		event = KFD_SMI_EVENT_GPU_POST_RESET;</div><div class='hunk'>@@ -225,15 +227,23 @@ void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset)</div><div class='ctx'> 		event = KFD_SMI_EVENT_GPU_PRE_RESET;</div><div class='ctx'> 		++(dev-&gt;reset_seq_num);</div><div class='ctx'> 	}</div><div class='del'>-	kfd_smi_event_add(0, dev, event, "%x\n", dev-&gt;reset_seq_num);</div><div class='add'>+</div><div class='add'>+	memset(reset_cause, 0, sizeof(reset_cause));</div><div class='add'>+</div><div class='add'>+	if (reset_context)</div><div class='add'>+		amdgpu_reset_get_desc(reset_context, reset_cause,</div><div class='add'>+				      sizeof(reset_cause));</div><div class='add'>+</div><div class='add'>+	kfd_smi_event_add(0, dev, event, KFD_EVENT_FMT_UPDATE_GPU_RESET(</div><div class='add'>+			  dev-&gt;reset_seq_num, reset_cause));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_update_thermal_throttling(struct kfd_node *dev,</div><div class='ctx'> 					     uint64_t throttle_bitmask)</div><div class='ctx'> {</div><div class='del'>-	kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n",</div><div class='add'>+	kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, KFD_EVENT_FMT_THERMAL_THROTTLING(</div><div class='ctx'> 			  throttle_bitmask,</div><div class='del'>-			  amdgpu_dpm_get_thermal_throttling_counter(dev-&gt;adev));</div><div class='add'>+			  amdgpu_dpm_get_thermal_throttling_counter(dev-&gt;adev)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid)</div><div class='hunk'>@@ -243,9 +253,9 @@ void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid)</div><div class='ctx'> 	task_info = amdgpu_vm_get_task_info_pasid(dev-&gt;adev, pasid);</div><div class='ctx'> 	if (task_info) {</div><div class='ctx'> 		/* Report VM faults from user applications, not retry from kernel */</div><div class='del'>-		if (task_info-&gt;pid)</div><div class='del'>-			kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n",</div><div class='del'>-					 task_info-&gt;pid, task_info-&gt;task_name);</div><div class='add'>+		if (task_info-&gt;task.pid)</div><div class='add'>+			kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, KFD_EVENT_FMT_VMFAULT(</div><div class='add'>+					  task_info-&gt;task.pid, task_info-&gt;task.comm));</div><div class='ctx'> 		amdgpu_vm_put_task_info(task_info);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -255,16 +265,16 @@ void kfd_smi_event_page_fault_start(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				    ktime_t ts)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_PAGE_FAULT_START,</div><div class='del'>-			  "%lld -%d @%lx(%x) %c\n", ktime_to_ns(ts), pid,</div><div class='del'>-			  address, node-&gt;id, write_fault ? 'W' : 'R');</div><div class='add'>+			  KFD_EVENT_FMT_PAGEFAULT_START(ktime_to_ns(ts), pid,</div><div class='add'>+			  address, node-&gt;id, write_fault ? 'W' : 'R'));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_page_fault_end(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				  unsigned long address, bool migration)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_PAGE_FAULT_END,</div><div class='del'>-			  "%lld -%d @%lx(%x) %c\n", ktime_get_boottime_ns(),</div><div class='del'>-			  pid, address, node-&gt;id, migration ? 'M' : 'U');</div><div class='add'>+			  KFD_EVENT_FMT_PAGEFAULT_END(ktime_get_boottime_ns(),</div><div class='add'>+			  pid, address, node-&gt;id, migration ? 'M' : 'U'));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_migration_start(struct kfd_node *node, pid_t pid,</div><div class='hunk'>@@ -274,34 +284,35 @@ void kfd_smi_event_migration_start(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				   uint32_t trigger)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_MIGRATE_START,</div><div class='del'>-			  "%lld -%d @%lx(%lx) %x-&gt;%x %x:%x %d\n",</div><div class='add'>+			  KFD_EVENT_FMT_MIGRATE_START(</div><div class='ctx'> 			  ktime_get_boottime_ns(), pid, start, end - start,</div><div class='del'>-			  from, to, prefetch_loc, preferred_loc, trigger);</div><div class='add'>+			  from, to, prefetch_loc, preferred_loc, trigger));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_migration_end(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				 unsigned long start, unsigned long end,</div><div class='del'>-				 uint32_t from, uint32_t to, uint32_t trigger)</div><div class='add'>+				 uint32_t from, uint32_t to, uint32_t trigger,</div><div class='add'>+				 int error_code)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_MIGRATE_END,</div><div class='del'>-			  "%lld -%d @%lx(%lx) %x-&gt;%x %d\n",</div><div class='add'>+			  KFD_EVENT_FMT_MIGRATE_END(</div><div class='ctx'> 			  ktime_get_boottime_ns(), pid, start, end - start,</div><div class='del'>-			  from, to, trigger);</div><div class='add'>+			  from, to, trigger, error_code));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_queue_eviction(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				  uint32_t trigger)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_EVICTION,</div><div class='del'>-			  "%lld -%d %x %d\n", ktime_get_boottime_ns(), pid,</div><div class='del'>-			  node-&gt;id, trigger);</div><div class='add'>+			  KFD_EVENT_FMT_QUEUE_EVICTION(ktime_get_boottime_ns(), pid,</div><div class='add'>+			  node-&gt;id, trigger));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_queue_restore(struct kfd_node *node, pid_t pid)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_RESTORE,</div><div class='del'>-			  "%lld -%d %x\n", ktime_get_boottime_ns(), pid,</div><div class='del'>-			  node-&gt;id);</div><div class='add'>+			  KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(), pid,</div><div class='add'>+			  node-&gt;id, 0));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm)</div><div class='hunk'>@@ -318,8 +329,8 @@ void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm)</div><div class='ctx'> </div><div class='ctx'> 		kfd_smi_event_add(p-&gt;lead_thread-&gt;pid, pdd-&gt;dev,</div><div class='ctx'> 				  KFD_SMI_EVENT_QUEUE_RESTORE,</div><div class='del'>-				  "%lld -%d %x %c\n", ktime_get_boottime_ns(),</div><div class='del'>-				  p-&gt;lead_thread-&gt;pid, pdd-&gt;dev-&gt;id, 'R');</div><div class='add'>+				  KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(),</div><div class='add'>+				  p-&gt;lead_thread-&gt;pid, pdd-&gt;dev-&gt;id, 'R'));</div><div class='ctx'> 	}</div><div class='ctx'> 	kfd_unref_process(p);</div><div class='ctx'> }</div><div class='hunk'>@@ -329,8 +340,29 @@ void kfd_smi_event_unmap_from_gpu(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				  uint32_t trigger)</div><div class='ctx'> {</div><div class='ctx'> 	kfd_smi_event_add(pid, node, KFD_SMI_EVENT_UNMAP_FROM_GPU,</div><div class='del'>-			  "%lld -%d @%lx(%lx) %x %d\n", ktime_get_boottime_ns(),</div><div class='del'>-			  pid, address, last - address + 1, node-&gt;id, trigger);</div><div class='add'>+			  KFD_EVENT_FMT_UNMAP_FROM_GPU(ktime_get_boottime_ns(),</div><div class='add'>+			  pid, address, last - address + 1, node-&gt;id, trigger));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void kfd_smi_event_process(struct kfd_process_device *pdd, bool start)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_task_info *task_info;</div><div class='add'>+	struct amdgpu_vm *avm;</div><div class='add'>+</div><div class='add'>+	if (!pdd-&gt;drm_priv)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	avm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='add'>+	task_info = amdgpu_vm_get_task_info_vm(avm);</div><div class='add'>+</div><div class='add'>+	if (task_info) {</div><div class='add'>+		kfd_smi_event_add(0, pdd-&gt;dev,</div><div class='add'>+				  start ? KFD_SMI_EVENT_PROCESS_START :</div><div class='add'>+				  KFD_SMI_EVENT_PROCESS_END,</div><div class='add'>+				  KFD_EVENT_FMT_PROCESS(task_info-&gt;task.pid,</div><div class='add'>+				  task_info-&gt;task.comm));</div><div class='add'>+		amdgpu_vm_put_task_info(task_info);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd)</div><div class='hunk'>@@ -343,7 +375,7 @@ int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;client-&gt;list);</div><div class='ctx'> </div><div class='del'>-	ret = kfifo_alloc(&amp;client-&gt;fifo, MAX_KFIFO_SIZE, GFP_KERNEL);</div><div class='add'>+	ret = kfifo_alloc(&amp;client-&gt;fifo, KFD_MAX_KFIFO_SIZE, GFP_KERNEL);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		kfree(client);</div><div class='ctx'> 		return ret;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h<br/>index fa95c2dfd587..bb4d72b57387 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h</a></div><div class='hunk'>@@ -24,11 +24,14 @@</div><div class='ctx'> #ifndef KFD_SMI_EVENTS_H_INCLUDED</div><div class='ctx'> #define KFD_SMI_EVENTS_H_INCLUDED</div><div class='ctx'> </div><div class='add'>+struct amdgpu_reset_context;</div><div class='add'>+</div><div class='ctx'> int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd);</div><div class='ctx'> void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid);</div><div class='ctx'> void kfd_smi_event_update_thermal_throttling(struct kfd_node *dev,</div><div class='ctx'> 					     uint64_t throttle_bitmask);</div><div class='del'>-void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset);</div><div class='add'>+void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset,</div><div class='add'>+				    struct amdgpu_reset_context *reset_context);</div><div class='ctx'> void kfd_smi_event_page_fault_start(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				    unsigned long address, bool write_fault,</div><div class='ctx'> 				    ktime_t ts);</div><div class='hunk'>@@ -41,7 +44,8 @@ void kfd_smi_event_migration_start(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 			     uint32_t trigger);</div><div class='ctx'> void kfd_smi_event_migration_end(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 			     unsigned long start, unsigned long end,</div><div class='del'>-			     uint32_t from, uint32_t to, uint32_t trigger);</div><div class='add'>+			     uint32_t from, uint32_t to, uint32_t trigger,</div><div class='add'>+			     int error_code);</div><div class='ctx'> void kfd_smi_event_queue_eviction(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				  uint32_t trigger);</div><div class='ctx'> void kfd_smi_event_queue_restore(struct kfd_node *node, pid_t pid);</div><div class='hunk'>@@ -49,4 +53,5 @@ void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm);</div><div class='ctx'> void kfd_smi_event_unmap_from_gpu(struct kfd_node *node, pid_t pid,</div><div class='ctx'> 				  unsigned long address, unsigned long last,</div><div class='ctx'> 				  uint32_t trigger);</div><div class='add'>+void kfd_smi_event_process(struct kfd_process_device *pdd, bool start);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c<br/>index f0f7f48af413..97c2270f278f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_svm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_svm.c</a></div><div class='hunk'>@@ -309,12 +309,13 @@ static void svm_range_free(struct svm_range *prange, bool do_unmap)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='del'>-svm_range_set_default_attributes(int32_t *location, int32_t *prefetch_loc,</div><div class='del'>-				 uint8_t *granularity, uint32_t *flags)</div><div class='add'>+svm_range_set_default_attributes(struct svm_range_list *svms, int32_t *location,</div><div class='add'>+				 int32_t *prefetch_loc, uint8_t *granularity,</div><div class='add'>+				 uint32_t *flags)</div><div class='ctx'> {</div><div class='ctx'> 	*location = KFD_IOCTL_SVM_LOCATION_UNDEFINED;</div><div class='ctx'> 	*prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED;</div><div class='del'>-	*granularity = 9;</div><div class='add'>+	*granularity = svms-&gt;default_granularity;</div><div class='ctx'> 	*flags =</div><div class='ctx'> 		KFD_IOCTL_SVM_FLAG_HOST_ACCESS | KFD_IOCTL_SVM_FLAG_COHERENT;</div><div class='ctx'> }</div><div class='hunk'>@@ -358,7 +359,7 @@ svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start,</div><div class='ctx'> 		bitmap_copy(prange-&gt;bitmap_access, svms-&gt;bitmap_supported,</div><div class='ctx'> 			    MAX_GPU_INSTANCE);</div><div class='ctx'> </div><div class='del'>-	svm_range_set_default_attributes(&amp;prange-&gt;preferred_loc,</div><div class='add'>+	svm_range_set_default_attributes(svms, &amp;prange-&gt;preferred_loc,</div><div class='ctx'> 					 &amp;prange-&gt;prefetch_loc,</div><div class='ctx'> 					 &amp;prange-&gt;granularity, &amp;prange-&gt;flags);</div><div class='ctx'> </div><div class='hunk'>@@ -404,6 +405,27 @@ static void svm_range_bo_release(struct kref *kref)</div><div class='ctx'> 		spin_lock(&amp;svm_bo-&gt;list_lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock(&amp;svm_bo-&gt;list_lock);</div><div class='add'>+</div><div class='add'>+	if (mmget_not_zero(svm_bo-&gt;eviction_fence-&gt;mm)) {</div><div class='add'>+		struct kfd_process_device *pdd;</div><div class='add'>+		struct kfd_process *p;</div><div class='add'>+		struct mm_struct *mm;</div><div class='add'>+</div><div class='add'>+		mm = svm_bo-&gt;eviction_fence-&gt;mm;</div><div class='add'>+		/*</div><div class='add'>+		 * The forked child process takes svm_bo device pages ref, svm_bo could be</div><div class='add'>+		 * released after parent process is gone.</div><div class='add'>+		 */</div><div class='add'>+		p = kfd_lookup_process_by_mm(mm);</div><div class='add'>+		if (p) {</div><div class='add'>+			pdd = kfd_get_process_device_data(svm_bo-&gt;node, p);</div><div class='add'>+			if (pdd)</div><div class='add'>+				atomic64_sub(amdgpu_bo_size(svm_bo-&gt;bo), &amp;pdd-&gt;vram_usage);</div><div class='add'>+			kfd_unref_process(p);</div><div class='add'>+		}</div><div class='add'>+		mmput(mm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!dma_fence_is_signaled(&amp;svm_bo-&gt;eviction_fence-&gt;base))</div><div class='ctx'> 		/* We're not in the eviction worker. Signal the fence. */</div><div class='ctx'> 		dma_fence_signal(&amp;svm_bo-&gt;eviction_fence-&gt;base);</div><div class='hunk'>@@ -531,6 +553,7 @@ int</div><div class='ctx'> svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 			bool clear)</div><div class='ctx'> {</div><div class='add'>+	struct kfd_process_device *pdd;</div><div class='ctx'> 	struct amdgpu_bo_param bp;</div><div class='ctx'> 	struct svm_range_bo *svm_bo;</div><div class='ctx'> 	struct amdgpu_bo_user *ubo;</div><div class='hunk'>@@ -540,7 +563,8 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	p = container_of(prange-&gt;svms, struct kfd_process, svms);</div><div class='del'>-	pr_debug("pasid: %x svms 0x%p [0x%lx 0x%lx]\n", p-&gt;pasid, prange-&gt;svms,</div><div class='add'>+	pr_debug("process pid: %d svms 0x%p [0x%lx 0x%lx]\n",</div><div class='add'>+		 p-&gt;lead_thread-&gt;pid, prange-&gt;svms,</div><div class='ctx'> 		 prange-&gt;start, prange-&gt;last);</div><div class='ctx'> </div><div class='ctx'> 	if (svm_range_validate_svm_bo(node, prange))</div><div class='hunk'>@@ -622,6 +646,10 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	list_add(&amp;prange-&gt;svm_bo_list, &amp;svm_bo-&gt;range_list);</div><div class='ctx'> 	spin_unlock(&amp;svm_bo-&gt;list_lock);</div><div class='ctx'> </div><div class='add'>+	pdd = svm_range_get_pdd_by_node(prange, node);</div><div class='add'>+	if (pdd)</div><div class='add'>+		atomic64_add(amdgpu_bo_size(bo), &amp;pdd-&gt;vram_usage);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> reserve_bo_failed:</div><div class='hunk'>@@ -1051,6 +1079,7 @@ svm_range_split_adjust(struct svm_range *new, struct svm_range *old,</div><div class='ctx'> 	new-&gt;mapped_to_gpu = old-&gt;mapped_to_gpu;</div><div class='ctx'> 	bitmap_copy(new-&gt;bitmap_access, old-&gt;bitmap_access, MAX_GPU_INSTANCE);</div><div class='ctx'> 	bitmap_copy(new-&gt;bitmap_aip, old-&gt;bitmap_aip, MAX_GPU_INSTANCE);</div><div class='add'>+	atomic_set(&amp;new-&gt;queue_refcount, atomic_read(&amp;old-&gt;queue_refcount));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1142,13 +1171,12 @@ svm_range_split_head(struct svm_range *prange, uint64_t new_start,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='del'>-svm_range_add_child(struct svm_range *prange, struct mm_struct *mm,</div><div class='del'>-		    struct svm_range *pchild, enum svm_work_list_ops op)</div><div class='add'>+svm_range_add_child(struct svm_range *prange, struct svm_range *pchild, enum svm_work_list_ops op)</div><div class='ctx'> {</div><div class='ctx'> 	pr_debug("add child 0x%p [0x%lx 0x%lx] to prange 0x%p child list %d\n",</div><div class='ctx'> 		 pchild, pchild-&gt;start, pchild-&gt;last, prange, op);</div><div class='ctx'> </div><div class='del'>-	pchild-&gt;work_item.mm = mm;</div><div class='add'>+	pchild-&gt;work_item.mm = NULL;</div><div class='ctx'> 	pchild-&gt;work_item.op = op;</div><div class='ctx'> 	list_add_tail(&amp;pchild-&gt;child_list, &amp;prange-&gt;child_list);</div><div class='ctx'> }</div><div class='hunk'>@@ -1161,23 +1189,23 @@ svm_nodes_in_same_hive(struct kfd_node *node_a, struct kfd_node *node_b)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint64_t</div><div class='del'>-svm_range_get_pte_flags(struct kfd_node *node,</div><div class='add'>+svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm,</div><div class='ctx'> 			struct svm_range *prange, int domain)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_node *bo_node;</div><div class='ctx'> 	uint32_t flags = prange-&gt;flags;</div><div class='ctx'> 	uint32_t mapping_flags = 0;</div><div class='add'>+	uint32_t gc_ip_version = KFD_GC_VERSION(node);</div><div class='ctx'> 	uint64_t pte_flags;</div><div class='ctx'> 	bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN);</div><div class='ctx'> 	bool coherent = flags &amp; (KFD_IOCTL_SVM_FLAG_COHERENT | KFD_IOCTL_SVM_FLAG_EXT_COHERENT);</div><div class='ctx'> 	bool ext_coherent = flags &amp; KFD_IOCTL_SVM_FLAG_EXT_COHERENT;</div><div class='del'>-	bool uncached = false; /*flags &amp; KFD_IOCTL_SVM_FLAG_UNCACHED;*/</div><div class='ctx'> 	unsigned int mtype_local;</div><div class='ctx'> </div><div class='ctx'> 	if (domain == SVM_RANGE_VRAM_DOMAIN)</div><div class='ctx'> 		bo_node = prange-&gt;svm_bo-&gt;node;</div><div class='ctx'> </div><div class='del'>-	switch (amdgpu_ip_version(node-&gt;adev, GC_HWIP, 0)) {</div><div class='add'>+	switch (gc_ip_version) {</div><div class='ctx'> 	case IP_VERSION(9, 4, 1):</div><div class='ctx'> 		if (domain == SVM_RANGE_VRAM_DOMAIN) {</div><div class='ctx'> 			if (bo_node == node) {</div><div class='hunk'>@@ -1213,15 +1241,15 @@ svm_range_get_pte_flags(struct kfd_node *node,</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='add'>+	case IP_VERSION(9, 4, 4):</div><div class='add'>+	case IP_VERSION(9, 5, 0):</div><div class='ctx'> 		if (ext_coherent)</div><div class='del'>-			mtype_local = node-&gt;adev-&gt;rev_id ? AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_UC;</div><div class='add'>+			mtype_local = AMDGPU_VM_MTYPE_CC;</div><div class='ctx'> 		else</div><div class='ctx'> 			mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC :</div><div class='ctx'> 				amdgpu_mtype_local == 2 ? AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;</div><div class='ctx'> 		snoop = true;</div><div class='del'>-		if (uncached) {</div><div class='del'>-			mapping_flags |= AMDGPU_VM_MTYPE_UC;</div><div class='del'>-		} else if (domain == SVM_RANGE_VRAM_DOMAIN) {</div><div class='add'>+		if (domain == SVM_RANGE_VRAM_DOMAIN) {</div><div class='ctx'> 			/* local HBM region close to partition */</div><div class='ctx'> 			if (bo_node-&gt;adev == node-&gt;adev &amp;&amp;</div><div class='ctx'> 			    (!bo_node-&gt;xcp || !node-&gt;xcp || bo_node-&gt;xcp-&gt;mem_id == node-&gt;xcp-&gt;mem_id))</div><div class='hunk'>@@ -1231,9 +1259,13 @@ svm_range_get_pte_flags(struct kfd_node *node,</div><div class='ctx'> 			 */</div><div class='ctx'> 			else if (svm_nodes_in_same_hive(bo_node, node) &amp;&amp; !ext_coherent)</div><div class='ctx'> 				mapping_flags |= AMDGPU_VM_MTYPE_NC;</div><div class='del'>-			/* PCIe P2P or extended system scope coherence */</div><div class='del'>-			else</div><div class='add'>+			/* PCIe P2P on GPUs pre-9.5.0 */</div><div class='add'>+			else if (gc_ip_version &lt; IP_VERSION(9, 5, 0) &amp;&amp;</div><div class='add'>+				 !svm_nodes_in_same_hive(bo_node, node))</div><div class='ctx'> 				mapping_flags |= AMDGPU_VM_MTYPE_UC;</div><div class='add'>+			/* Other remote memory */</div><div class='add'>+			else</div><div class='add'>+				mapping_flags |= ext_coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;</div><div class='ctx'> 		/* system memory accessed by the APU */</div><div class='ctx'> 		} else if (node-&gt;adev-&gt;flags &amp; AMD_IS_APU) {</div><div class='ctx'> 			/* On NUMA systems, locality is determined per-page</div><div class='hunk'>@@ -1245,26 +1277,34 @@ svm_range_get_pte_flags(struct kfd_node *node,</div><div class='ctx'> 				mapping_flags |= ext_coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;</div><div class='ctx'> 		/* system memory accessed by the dGPU */</div><div class='ctx'> 		} else {</div><div class='del'>-			mapping_flags |= AMDGPU_VM_MTYPE_UC;</div><div class='add'>+			if (gc_ip_version &lt; IP_VERSION(9, 5, 0) || ext_coherent)</div><div class='add'>+				mapping_flags |= AMDGPU_VM_MTYPE_UC;</div><div class='add'>+			else</div><div class='add'>+				mapping_flags |= AMDGPU_VM_MTYPE_NC;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(12, 0, 0):</div><div class='add'>+	case IP_VERSION(12, 0, 1):</div><div class='add'>+		mapping_flags |= AMDGPU_VM_MTYPE_NC;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		mapping_flags |= coherent ?</div><div class='ctx'> 			AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mapping_flags |= AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE;</div><div class='del'>-</div><div class='del'>-	if (flags &amp; KFD_IOCTL_SVM_FLAG_GPU_RO)</div><div class='del'>-		mapping_flags &amp;= ~AMDGPU_VM_PAGE_WRITEABLE;</div><div class='ctx'> 	if (flags &amp; KFD_IOCTL_SVM_FLAG_GPU_EXEC)</div><div class='ctx'> 		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;</div><div class='ctx'> </div><div class='ctx'> 	pte_flags = AMDGPU_PTE_VALID;</div><div class='ctx'> 	pte_flags |= (domain == SVM_RANGE_VRAM_DOMAIN) ? 0 : AMDGPU_PTE_SYSTEM;</div><div class='ctx'> 	pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;</div><div class='add'>+	if (gc_ip_version &gt;= IP_VERSION(12, 0, 0))</div><div class='add'>+		pte_flags |= AMDGPU_PTE_IS_PTE;</div><div class='ctx'> </div><div class='del'>-	pte_flags |= amdgpu_gem_va_map_flags(node-&gt;adev, mapping_flags);</div><div class='add'>+	amdgpu_gmc_get_vm_pte(node-&gt;adev, vm, NULL, mapping_flags, &amp;pte_flags);</div><div class='add'>+	pte_flags |= AMDGPU_PTE_READABLE;</div><div class='add'>+	if (!(flags &amp; KFD_IOCTL_SVM_FLAG_GPU_RO))</div><div class='add'>+		pte_flags |= AMDGPU_PTE_WRITEABLE;</div><div class='ctx'> 	return pte_flags;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1371,7 +1411,7 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange,</div><div class='ctx'> 		pr_debug("Mapping range [0x%lx 0x%llx] on domain: %s\n",</div><div class='ctx'> 			 last_start, prange-&gt;start + i, last_domain ? "GPU" : "CPU");</div><div class='ctx'> </div><div class='del'>-		pte_flags = svm_range_get_pte_flags(pdd-&gt;dev, prange, last_domain);</div><div class='add'>+		pte_flags = svm_range_get_pte_flags(pdd-&gt;dev, vm, prange, last_domain);</div><div class='ctx'> 		if (readonly)</div><div class='ctx'> 			pte_flags &amp;= ~AMDGPU_PTE_WRITEABLE;</div><div class='ctx'> </div><div class='hunk'>@@ -1658,7 +1698,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> 	start = map_start &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 	end = (map_last + 1) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 	for (addr = start; !r &amp;&amp; addr &lt; end; ) {</div><div class='del'>-		struct hmm_range *hmm_range;</div><div class='add'>+		struct amdgpu_hmm_range *range = NULL;</div><div class='ctx'> 		unsigned long map_start_vma;</div><div class='ctx'> 		unsigned long map_last_vma;</div><div class='ctx'> 		struct vm_area_struct *vma;</div><div class='hunk'>@@ -1673,16 +1713,39 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> </div><div class='ctx'> 			next = min(vma-&gt;vm_end, end);</div><div class='ctx'> 			npages = (next - addr) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+			/* HMM requires at least READ permissions. If provided with PROT_NONE,</div><div class='add'>+			 * unmap the memory. If it's not already mapped, this is a no-op</div><div class='add'>+			 * If PROT_WRITE is provided without READ, warn first then unmap</div><div class='add'>+			 */</div><div class='add'>+			if (!(vma-&gt;vm_flags &amp; VM_READ)) {</div><div class='add'>+				unsigned long e, s;</div><div class='add'>+</div><div class='add'>+				svm_range_lock(prange);</div><div class='add'>+				if (vma-&gt;vm_flags &amp; VM_WRITE)</div><div class='add'>+					pr_debug("VM_WRITE without VM_READ is not supported");</div><div class='add'>+				s = max(start, prange-&gt;start);</div><div class='add'>+				e = min(end, prange-&gt;last);</div><div class='add'>+				if (e &gt;= s)</div><div class='add'>+					r = svm_range_unmap_from_gpus(prange, s, e,</div><div class='add'>+						       KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU);</div><div class='add'>+				svm_range_unlock(prange);</div><div class='add'>+				/* If unmap returns non-zero, we'll bail on the next for loop</div><div class='add'>+				 * iteration, so just leave r and continue</div><div class='add'>+				 */</div><div class='add'>+				addr = next;</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			WRITE_ONCE(p-&gt;svms.faulting_task, current);</div><div class='del'>-			r = amdgpu_hmm_range_get_pages(&amp;prange-&gt;notifier, addr, npages,</div><div class='del'>-						       readonly, owner, NULL,</div><div class='del'>-						       &amp;hmm_range);</div><div class='add'>+			range = amdgpu_hmm_range_alloc(NULL);</div><div class='add'>+			if (likely(range))</div><div class='add'>+				r = amdgpu_hmm_range_get_pages(&amp;prange-&gt;notifier, addr, npages,</div><div class='add'>+							       readonly, owner, range);</div><div class='add'>+			else</div><div class='add'>+				r = -ENOMEM;</div><div class='ctx'> 			WRITE_ONCE(p-&gt;svms.faulting_task, NULL);</div><div class='del'>-			if (r) {</div><div class='add'>+			if (r)</div><div class='ctx'> 				pr_debug("failed %d to get svm range pages\n", r);</div><div class='del'>-				if (r == -EBUSY)</div><div class='del'>-					r = -EAGAIN;</div><div class='del'>-			}</div><div class='ctx'> 		} else {</div><div class='ctx'> 			r = -EFAULT;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1690,17 +1753,25 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> 		if (!r) {</div><div class='ctx'> 			offset = (addr &gt;&gt; PAGE_SHIFT) - prange-&gt;start;</div><div class='ctx'> 			r = svm_range_dma_map(prange, ctx-&gt;bitmap, offset, npages,</div><div class='del'>-					      hmm_range-&gt;hmm_pfns);</div><div class='add'>+					      range-&gt;hmm_range.hmm_pfns);</div><div class='ctx'> 			if (r)</div><div class='ctx'> 				pr_debug("failed %d to dma map range\n", r);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		svm_range_lock(prange);</div><div class='del'>-		if (!r &amp;&amp; amdgpu_hmm_range_get_pages_done(hmm_range)) {</div><div class='add'>+</div><div class='add'>+		/* Free backing memory of hmm_range if it was initialized</div><div class='add'>+		 * Override return value to TRY AGAIN only if prior returns</div><div class='add'>+		 * were successful</div><div class='add'>+		 */</div><div class='add'>+		if (range &amp;&amp; !amdgpu_hmm_range_valid(range) &amp;&amp; !r) {</div><div class='ctx'> 			pr_debug("hmm update the range, need validate again\n");</div><div class='ctx'> 			r = -EAGAIN;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/* Free the hmm range */</div><div class='add'>+		amdgpu_hmm_range_free(range);</div><div class='add'>+</div><div class='ctx'> 		if (!r &amp;&amp; !list_empty(&amp;prange-&gt;child_list)) {</div><div class='ctx'> 			pr_debug("range split by unmap in parallel, validate again\n");</div><div class='ctx'> 			r = -EAGAIN;</div><div class='hunk'>@@ -1980,6 +2051,7 @@ static struct svm_range *svm_range_clone(struct svm_range *old)</div><div class='ctx'> 	new-&gt;vram_pages = old-&gt;vram_pages;</div><div class='ctx'> 	bitmap_copy(new-&gt;bitmap_access, old-&gt;bitmap_access, MAX_GPU_INSTANCE);</div><div class='ctx'> 	bitmap_copy(new-&gt;bitmap_aip, old-&gt;bitmap_aip, MAX_GPU_INSTANCE);</div><div class='add'>+	atomic_set(&amp;new-&gt;queue_refcount, atomic_read(&amp;old-&gt;queue_refcount));</div><div class='ctx'> </div><div class='ctx'> 	return new;</div><div class='ctx'> }</div><div class='hunk'>@@ -2248,16 +2320,10 @@ static void svm_range_drain_retry_fault(struct svm_range_list *svms)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process_device *pdd;</div><div class='ctx'> 	struct kfd_process *p;</div><div class='del'>-	int drain;</div><div class='ctx'> 	uint32_t i;</div><div class='ctx'> </div><div class='ctx'> 	p = container_of(svms, struct kfd_process, svms);</div><div class='ctx'> </div><div class='del'>-restart:</div><div class='del'>-	drain = atomic_read(&amp;svms-&gt;drain_pagefaults);</div><div class='del'>-	if (!drain)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	for_each_set_bit(i, svms-&gt;bitmap_supported, p-&gt;n_pdds) {</div><div class='ctx'> 		pdd = p-&gt;pdds[i];</div><div class='ctx'> 		if (!pdd)</div><div class='hunk'>@@ -2277,8 +2343,6 @@ restart:</div><div class='ctx'> </div><div class='ctx'> 		pr_debug("drain retry fault gpu %d svms 0x%p done\n", i, svms);</div><div class='ctx'> 	}</div><div class='del'>-	if (atomic_cmpxchg(&amp;svms-&gt;drain_pagefaults, drain, 0) != drain)</div><div class='del'>-		goto restart;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void svm_range_deferred_list_work(struct work_struct *work)</div><div class='hunk'>@@ -2300,17 +2364,8 @@ static void svm_range_deferred_list_work(struct work_struct *work)</div><div class='ctx'> 			 prange-&gt;start, prange-&gt;last, prange-&gt;work_item.op);</div><div class='ctx'> </div><div class='ctx'> 		mm = prange-&gt;work_item.mm;</div><div class='del'>-retry:</div><div class='del'>-		mmap_write_lock(mm);</div><div class='ctx'> </div><div class='del'>-		/* Checking for the need to drain retry faults must be inside</div><div class='del'>-		 * mmap write lock to serialize with munmap notifiers.</div><div class='del'>-		 */</div><div class='del'>-		if (unlikely(atomic_read(&amp;svms-&gt;drain_pagefaults))) {</div><div class='del'>-			mmap_write_unlock(mm);</div><div class='del'>-			svm_range_drain_retry_fault(svms);</div><div class='del'>-			goto retry;</div><div class='del'>-		}</div><div class='add'>+		mmap_write_lock(mm);</div><div class='ctx'> </div><div class='ctx'> 		/* Remove from deferred_list must be inside mmap write lock, for</div><div class='ctx'> 		 * two race cases:</div><div class='hunk'>@@ -2366,15 +2421,17 @@ svm_range_add_list_work(struct svm_range_list *svms, struct svm_range *prange,</div><div class='ctx'> 		    prange-&gt;work_item.op != SVM_OP_UNMAP_RANGE)</div><div class='ctx'> 			prange-&gt;work_item.op = op;</div><div class='ctx'> 	} else {</div><div class='del'>-		prange-&gt;work_item.op = op;</div><div class='del'>-</div><div class='del'>-		/* Pairs with mmput in deferred_list_work */</div><div class='del'>-		mmget(mm);</div><div class='del'>-		prange-&gt;work_item.mm = mm;</div><div class='del'>-		list_add_tail(&amp;prange-&gt;deferred_list,</div><div class='del'>-			      &amp;prange-&gt;svms-&gt;deferred_range_list);</div><div class='del'>-		pr_debug("add prange 0x%p [0x%lx 0x%lx] to work list op %d\n",</div><div class='del'>-			 prange, prange-&gt;start, prange-&gt;last, op);</div><div class='add'>+		/* Pairs with mmput in deferred_list_work.</div><div class='add'>+		 * If process is exiting and mm is gone, don't update mmu notifier.</div><div class='add'>+		 */</div><div class='add'>+		if (mmget_not_zero(mm)) {</div><div class='add'>+			prange-&gt;work_item.mm = mm;</div><div class='add'>+			prange-&gt;work_item.op = op;</div><div class='add'>+			list_add_tail(&amp;prange-&gt;deferred_list,</div><div class='add'>+				      &amp;prange-&gt;svms-&gt;deferred_range_list);</div><div class='add'>+			pr_debug("add prange 0x%p [0x%lx 0x%lx] to work list op %d\n",</div><div class='add'>+				 prange, prange-&gt;start, prange-&gt;last, op);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock(&amp;svms-&gt;deferred_list_lock);</div><div class='ctx'> }</div><div class='hunk'>@@ -2388,8 +2445,7 @@ void schedule_deferred_list_work(struct svm_range_list *svms)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='del'>-svm_range_unmap_split(struct mm_struct *mm, struct svm_range *parent,</div><div class='del'>-		      struct svm_range *prange, unsigned long start,</div><div class='add'>+svm_range_unmap_split(struct svm_range *parent, struct svm_range *prange, unsigned long start,</div><div class='ctx'> 		      unsigned long last)</div><div class='ctx'> {</div><div class='ctx'> 	struct svm_range *head;</div><div class='hunk'>@@ -2410,12 +2466,12 @@ svm_range_unmap_split(struct mm_struct *mm, struct svm_range *parent,</div><div class='ctx'> 		svm_range_split(tail, last + 1, tail-&gt;last, &amp;head);</div><div class='ctx'> </div><div class='ctx'> 	if (head != prange &amp;&amp; tail != prange) {</div><div class='del'>-		svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE);</div><div class='del'>-		svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE);</div><div class='add'>+		svm_range_add_child(parent, head, SVM_OP_UNMAP_RANGE);</div><div class='add'>+		svm_range_add_child(parent, tail, SVM_OP_ADD_RANGE);</div><div class='ctx'> 	} else if (tail != prange) {</div><div class='del'>-		svm_range_add_child(parent, mm, tail, SVM_OP_UNMAP_RANGE);</div><div class='add'>+		svm_range_add_child(parent, tail, SVM_OP_UNMAP_RANGE);</div><div class='ctx'> 	} else if (head != prange) {</div><div class='del'>-		svm_range_add_child(parent, mm, head, SVM_OP_UNMAP_RANGE);</div><div class='add'>+		svm_range_add_child(parent, head, SVM_OP_UNMAP_RANGE);</div><div class='ctx'> 	} else if (parent != prange) {</div><div class='ctx'> 		prange-&gt;work_item.op = SVM_OP_UNMAP_RANGE;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2431,6 +2487,17 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange,</div><div class='ctx'> 	struct kfd_process *p;</div><div class='ctx'> 	unsigned long s, l;</div><div class='ctx'> 	bool unmap_parent;</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	if (atomic_read(&amp;prange-&gt;queue_refcount)) {</div><div class='add'>+		int r;</div><div class='add'>+</div><div class='add'>+		pr_warn("Freeing queue vital buffer 0x%lx, queue evicted\n",</div><div class='add'>+			prange-&gt;start &lt;&lt; PAGE_SHIFT);</div><div class='add'>+		r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_SVM);</div><div class='add'>+		if (r)</div><div class='add'>+			pr_debug("failed %d to quiesce KFD queues\n", r);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	p = kfd_lookup_process_by_mm(mm);</div><div class='ctx'> 	if (!p)</div><div class='hunk'>@@ -2440,11 +2507,38 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange,</div><div class='ctx'> 	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] [0x%lx 0x%lx]\n", svms,</div><div class='ctx'> 		 prange, prange-&gt;start, prange-&gt;last, start, last);</div><div class='ctx'> </div><div class='del'>-	/* Make sure pending page faults are drained in the deferred worker</div><div class='del'>-	 * before the range is freed to avoid straggler interrupts on</div><div class='del'>-	 * unmapped memory causing "phantom faults".</div><div class='add'>+	/* calculate time stamps that are used to decide which page faults need be</div><div class='add'>+	 * dropped or handled before unmap pages from gpu vm</div><div class='ctx'> 	 */</div><div class='del'>-	atomic_inc(&amp;svms-&gt;drain_pagefaults);</div><div class='add'>+	for_each_set_bit(i, svms-&gt;bitmap_supported, p-&gt;n_pdds) {</div><div class='add'>+		struct kfd_process_device *pdd;</div><div class='add'>+		struct amdgpu_device *adev;</div><div class='add'>+		struct amdgpu_ih_ring *ih;</div><div class='add'>+		uint32_t checkpoint_wptr;</div><div class='add'>+</div><div class='add'>+		pdd = p-&gt;pdds[i];</div><div class='add'>+		if (!pdd)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		adev = pdd-&gt;dev-&gt;adev;</div><div class='add'>+</div><div class='add'>+		/* Check and drain ih1 ring if cam not available */</div><div class='add'>+		if (adev-&gt;irq.ih1.ring_size) {</div><div class='add'>+			ih = &amp;adev-&gt;irq.ih1;</div><div class='add'>+			checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);</div><div class='add'>+			if (ih-&gt;rptr != checkpoint_wptr) {</div><div class='add'>+				svms-&gt;checkpoint_ts[i] =</div><div class='add'>+					amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* check if dev-&gt;irq.ih_soft is not empty */</div><div class='add'>+		ih = &amp;adev-&gt;irq.ih_soft;</div><div class='add'>+		checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih);</div><div class='add'>+		if (ih-&gt;rptr != checkpoint_wptr)</div><div class='add'>+			svms-&gt;checkpoint_ts[i] = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	unmap_parent = start &lt;= prange-&gt;start &amp;&amp; last &gt;= prange-&gt;last;</div><div class='ctx'> </div><div class='hunk'>@@ -2454,14 +2548,14 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange,</div><div class='ctx'> 		l = min(last, pchild-&gt;last);</div><div class='ctx'> 		if (l &gt;= s)</div><div class='ctx'> 			svm_range_unmap_from_gpus(pchild, s, l, trigger);</div><div class='del'>-		svm_range_unmap_split(mm, prange, pchild, start, last);</div><div class='add'>+		svm_range_unmap_split(prange, pchild, start, last);</div><div class='ctx'> 		mutex_unlock(&amp;pchild-&gt;lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	s = max(start, prange-&gt;start);</div><div class='ctx'> 	l = min(last, prange-&gt;last);</div><div class='ctx'> 	if (l &gt;= s)</div><div class='ctx'> 		svm_range_unmap_from_gpus(prange, s, l, trigger);</div><div class='del'>-	svm_range_unmap_split(mm, prange, prange, start, last);</div><div class='add'>+	svm_range_unmap_split(prange, prange, start, last);</div><div class='ctx'> </div><div class='ctx'> 	if (unmap_parent)</div><div class='ctx'> 		svm_range_add_list_work(svms, prange, mm, SVM_OP_UNMAP_RANGE);</div><div class='hunk'>@@ -2504,8 +2598,6 @@ svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni,</div><div class='ctx'> </div><div class='ctx'> 	if (range-&gt;event == MMU_NOTIFY_RELEASE)</div><div class='ctx'> 		return true;</div><div class='del'>-	if (!mmget_not_zero(mni-&gt;mm))</div><div class='del'>-		return true;</div><div class='ctx'> </div><div class='ctx'> 	start = mni-&gt;interval_tree.start;</div><div class='ctx'> 	last = mni-&gt;interval_tree.last;</div><div class='hunk'>@@ -2532,7 +2624,6 @@ svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	svm_range_unlock(prange);</div><div class='del'>-	mmput(mni-&gt;mm);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -2619,7 +2710,7 @@ svm_range_best_restore_location(struct svm_range *prange,</div><div class='ctx'> 		return -1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (node-&gt;adev-&gt;gmc.is_app_apu)</div><div class='add'>+	if (node-&gt;adev-&gt;apu_prefer_gtt)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (prange-&gt;preferred_loc == gpuid ||</div><div class='hunk'>@@ -2668,9 +2759,10 @@ svm_range_get_range_boundaries(struct kfd_process *p, int64_t addr,</div><div class='ctx'> 	*is_heap_stack = vma_is_initial_heap(vma) || vma_is_initial_stack(vma);</div><div class='ctx'> </div><div class='ctx'> 	start_limit = max(vma-&gt;vm_start &gt;&gt; PAGE_SHIFT,</div><div class='del'>-		      (unsigned long)ALIGN_DOWN(addr, 2UL &lt;&lt; 8));</div><div class='add'>+		      (unsigned long)ALIGN_DOWN(addr, 1UL &lt;&lt; p-&gt;svms.default_granularity));</div><div class='ctx'> 	end_limit = min(vma-&gt;vm_end &gt;&gt; PAGE_SHIFT,</div><div class='del'>-		    (unsigned long)ALIGN(addr + 1, 2UL &lt;&lt; 8));</div><div class='add'>+		    (unsigned long)ALIGN(addr + 1, 1UL &lt;&lt; p-&gt;svms.default_granularity));</div><div class='add'>+</div><div class='ctx'> 	/* First range that starts after the fault address */</div><div class='ctx'> 	node = interval_tree_iter_first(&amp;p-&gt;svms.objects, addr + 1, ULONG_MAX);</div><div class='ctx'> 	if (node) {</div><div class='hunk'>@@ -2885,7 +2977,7 @@ svm_fault_allowed(struct vm_area_struct *vma, bool write_fault)</div><div class='ctx'> int</div><div class='ctx'> svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 			uint32_t vmid, uint32_t node_id,</div><div class='del'>-			uint64_t addr, bool write_fault)</div><div class='add'>+			uint64_t addr, uint64_t ts, bool write_fault)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long start, last, size;</div><div class='ctx'> 	struct mm_struct *mm = NULL;</div><div class='hunk'>@@ -2895,7 +2987,7 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 	ktime_t timestamp = ktime_get_boottime();</div><div class='ctx'> 	struct kfd_node *node;</div><div class='ctx'> 	int32_t best_loc;</div><div class='del'>-	int32_t gpuidx = MAX_GPU_INSTANCE;</div><div class='add'>+	int32_t gpuid, gpuidx = MAX_GPU_INSTANCE;</div><div class='ctx'> 	bool write_locked = false;</div><div class='ctx'> 	struct vm_area_struct *vma;</div><div class='ctx'> 	bool migration = false;</div><div class='hunk'>@@ -2906,7 +2998,7 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	p = kfd_lookup_process_by_pasid(pasid);</div><div class='add'>+	p = kfd_lookup_process_by_pasid(pasid, NULL);</div><div class='ctx'> 	if (!p) {</div><div class='ctx'> 		pr_debug("kfd process not founded pasid 0x%x\n", pasid);</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -2916,11 +3008,25 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 	pr_debug("restoring svms 0x%p fault address 0x%llx\n", svms, addr);</div><div class='ctx'> </div><div class='ctx'> 	if (atomic_read(&amp;svms-&gt;drain_pagefaults)) {</div><div class='del'>-		pr_debug("draining retry fault, drop fault 0x%llx\n", addr);</div><div class='add'>+		pr_debug("page fault handling disabled, drop fault 0x%llx\n", addr);</div><div class='ctx'> 		r = 0;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	node = kfd_node_by_irq_ids(adev, node_id, vmid);</div><div class='add'>+	if (!node) {</div><div class='add'>+		pr_debug("kfd node does not exist node_id: %d, vmid: %d\n", node_id,</div><div class='add'>+			 vmid);</div><div class='add'>+		r = -EFAULT;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (kfd_process_gpuid_from_node(p, node, &amp;gpuid, &amp;gpuidx)) {</div><div class='add'>+		pr_debug("failed to get gpuid/gpuidex for node_id: %d\n", node_id);</div><div class='add'>+		r = -EFAULT;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!p-&gt;xnack_enabled) {</div><div class='ctx'> 		pr_debug("XNACK not enabled for pasid 0x%x\n", pasid);</div><div class='ctx'> 		r = -EFAULT;</div><div class='hunk'>@@ -2937,16 +3043,26 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	node = kfd_node_by_irq_ids(adev, node_id, vmid);</div><div class='del'>-	if (!node) {</div><div class='del'>-		pr_debug("kfd node does not exist node_id: %d, vmid: %d\n", node_id,</div><div class='del'>-			 vmid);</div><div class='del'>-		r = -EFAULT;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='ctx'> 	mmap_read_lock(mm);</div><div class='ctx'> retry_write_locked:</div><div class='ctx'> 	mutex_lock(&amp;svms-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* check if this page fault time stamp is before svms-&gt;checkpoint_ts */</div><div class='add'>+	if (svms-&gt;checkpoint_ts[gpuidx] != 0) {</div><div class='add'>+		if (amdgpu_ih_ts_after_or_equal(ts,  svms-&gt;checkpoint_ts[gpuidx])) {</div><div class='add'>+			pr_debug("draining retry fault, drop fault 0x%llx\n", addr);</div><div class='add'>+			if (write_locked)</div><div class='add'>+				mmap_write_downgrade(mm);</div><div class='add'>+			r = -EAGAIN;</div><div class='add'>+			goto out_unlock_svms;</div><div class='add'>+		} else {</div><div class='add'>+			/* ts is after svms-&gt;checkpoint_ts now, reset svms-&gt;checkpoint_ts</div><div class='add'>+			 * to zero to avoid following ts wrap around give wrong comparing</div><div class='add'>+			 */</div><div class='add'>+			svms-&gt;checkpoint_ts[gpuidx] = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	prange = svm_range_from_addr(svms, addr, NULL);</div><div class='ctx'> 	if (!prange) {</div><div class='ctx'> 		pr_debug("failed to find prange svms 0x%p address [0x%llx]\n",</div><div class='hunk'>@@ -3028,8 +3144,6 @@ retry_write_locked:</div><div class='ctx'> 	start = max_t(unsigned long, ALIGN_DOWN(addr, size), prange-&gt;start);</div><div class='ctx'> 	last = min_t(unsigned long, ALIGN(addr + 1, size) - 1, prange-&gt;last);</div><div class='ctx'> 	if (prange-&gt;actual_loc != 0 || best_loc != 0) {</div><div class='del'>-		migration = true;</div><div class='del'>-</div><div class='ctx'> 		if (best_loc) {</div><div class='ctx'> 			r = svm_migrate_to_vram(prange, best_loc, start, last,</div><div class='ctx'> 					mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU);</div><div class='hunk'>@@ -3052,7 +3166,9 @@ retry_write_locked:</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			pr_debug("failed %d to migrate svms %p [0x%lx 0x%lx]\n",</div><div class='ctx'> 				 r, svms, start, last);</div><div class='del'>-			goto out_unlock_range;</div><div class='add'>+			goto out_migrate_fail;</div><div class='add'>+		} else {</div><div class='add'>+			migration = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3062,6 +3178,7 @@ retry_write_locked:</div><div class='ctx'> 		pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",</div><div class='ctx'> 			 r, svms, start, last);</div><div class='ctx'> </div><div class='add'>+out_migrate_fail:</div><div class='ctx'> 	kfd_smi_event_page_fault_end(node, p-&gt;lead_thread-&gt;pid, addr,</div><div class='ctx'> 				     migration);</div><div class='ctx'> </div><div class='hunk'>@@ -3071,7 +3188,8 @@ out_unlock_svms:</div><div class='ctx'> 	mutex_unlock(&amp;svms-&gt;lock);</div><div class='ctx'> 	mmap_read_unlock(mm);</div><div class='ctx'> </div><div class='del'>-	svm_range_count_fault(node, p, gpuidx);</div><div class='add'>+	if (r != -EAGAIN)</div><div class='add'>+		svm_range_count_fault(node, p, gpuidx);</div><div class='ctx'> </div><div class='ctx'> 	mmput(mm);</div><div class='ctx'> out:</div><div class='hunk'>@@ -3148,7 +3266,8 @@ void svm_range_list_fini(struct kfd_process *p)</div><div class='ctx'> 	struct svm_range *prange;</div><div class='ctx'> 	struct svm_range *next;</div><div class='ctx'> </div><div class='del'>-	pr_debug("pasid 0x%x svms 0x%p\n", p-&gt;pasid, &amp;p-&gt;svms);</div><div class='add'>+	pr_debug("process pid %d svms 0x%p\n", p-&gt;lead_thread-&gt;pid,</div><div class='add'>+		 &amp;p-&gt;svms);</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;p-&gt;svms.restore_work);</div><div class='ctx'> </div><div class='hunk'>@@ -3158,8 +3277,9 @@ void svm_range_list_fini(struct kfd_process *p)</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Ensure no retry fault comes in afterwards, as page fault handler will</div><div class='ctx'> 	 * not find kfd process and take mm lock to recover fault.</div><div class='add'>+	 * stop kfd page fault handing, then wait pending page faults got drained</div><div class='ctx'> 	 */</div><div class='del'>-	atomic_inc(&amp;p-&gt;svms.drain_pagefaults);</div><div class='add'>+	atomic_set(&amp;p-&gt;svms.drain_pagefaults, 1);</div><div class='ctx'> 	svm_range_drain_retry_fault(&amp;p-&gt;svms);</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(prange, next, &amp;p-&gt;svms.list, list) {</div><div class='hunk'>@@ -3170,7 +3290,8 @@ void svm_range_list_fini(struct kfd_process *p)</div><div class='ctx'> </div><div class='ctx'> 	mutex_destroy(&amp;p-&gt;svms.lock);</div><div class='ctx'> </div><div class='del'>-	pr_debug("pasid 0x%x svms 0x%p done\n", p-&gt;pasid, &amp;p-&gt;svms);</div><div class='add'>+	pr_debug("process pid %d svms 0x%p done\n",</div><div class='add'>+		p-&gt;lead_thread-&gt;pid, &amp;p-&gt;svms);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int svm_range_list_init(struct kfd_process *p)</div><div class='hunk'>@@ -3193,6 +3314,12 @@ int svm_range_list_init(struct kfd_process *p)</div><div class='ctx'> 		if (KFD_IS_SVM_API_SUPPORTED(p-&gt;pdds[i]-&gt;dev-&gt;adev))</div><div class='ctx'> 			bitmap_set(svms-&gt;bitmap_supported, i, 1);</div><div class='ctx'> </div><div class='add'>+	 /* Value of default granularity cannot exceed 0x1B, the</div><div class='add'>+	  * number of pages supported by a 4-level paging table</div><div class='add'>+	  */</div><div class='add'>+	svms-&gt;default_granularity = min_t(u8, amdgpu_svm_default_granularity, 0x1B);</div><div class='add'>+	pr_debug("Default SVM Granularity to use: %d\n", svms-&gt;default_granularity);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3337,7 +3464,7 @@ svm_range_best_prefetch_location(struct svm_range *prange)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (bo_node-&gt;adev-&gt;gmc.is_app_apu) {</div><div class='add'>+	if (bo_node-&gt;adev-&gt;apu_prefer_gtt) {</div><div class='ctx'> 		best_loc = 0;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3426,7 +3553,7 @@ svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange,</div><div class='ctx'> 				mm, KFD_MIGRATE_TRIGGER_PREFETCH);</div><div class='ctx'> 	*migrated = !r;</div><div class='ctx'> </div><div class='del'>-	return r;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence)</div><div class='hunk'>@@ -3527,8 +3654,8 @@ svm_range_set_attr(struct kfd_process *p, struct mm_struct *mm,</div><div class='ctx'> 	bool flush_tlb;</div><div class='ctx'> 	int r, ret = 0;</div><div class='ctx'> </div><div class='del'>-	pr_debug("pasid 0x%x svms 0x%p [0x%llx 0x%llx] pages 0x%llx\n",</div><div class='del'>-		 p-&gt;pasid, &amp;p-&gt;svms, start, start + size - 1, size);</div><div class='add'>+	pr_debug("process pid %d svms 0x%p [0x%llx 0x%llx] pages 0x%llx\n",</div><div class='add'>+		 p-&gt;lead_thread-&gt;pid, &amp;p-&gt;svms, start, start + size - 1, size);</div><div class='ctx'> </div><div class='ctx'> 	r = svm_range_check_attr(p, nattr, attrs);</div><div class='ctx'> 	if (r)</div><div class='hunk'>@@ -3566,6 +3693,8 @@ svm_range_set_attr(struct kfd_process *p, struct mm_struct *mm,</div><div class='ctx'> 		svm_range_apply_attrs(p, prange, nattr, attrs, &amp;update_mapping);</div><div class='ctx'> 		/* TODO: unmap ranges from GPU that lost access */</div><div class='ctx'> 	}</div><div class='add'>+	update_mapping |= !p-&gt;xnack_enabled &amp;&amp; !list_empty(&amp;remap_list);</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(prange, next, &amp;remove_list, update_list) {</div><div class='ctx'> 		pr_debug("unlink old 0x%p prange 0x%p [0x%lx 0x%lx]\n",</div><div class='ctx'> 			 prange-&gt;svms, prange, prange-&gt;start,</div><div class='hunk'>@@ -3636,8 +3765,8 @@ out_unlock_range:</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;process_info-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	pr_debug("pasid 0x%x svms 0x%p [0x%llx 0x%llx] done, r=%d\n", p-&gt;pasid,</div><div class='del'>-		 &amp;p-&gt;svms, start, start + size - 1, r);</div><div class='add'>+	pr_debug("process pid %d svms 0x%p [0x%llx 0x%llx] done, r=%d\n",</div><div class='add'>+		 p-&gt;lead_thread-&gt;pid, &amp;p-&gt;svms, start, start + size - 1, r);</div><div class='ctx'> </div><div class='ctx'> 	return ret ? ret : r;</div><div class='ctx'> }</div><div class='hunk'>@@ -3720,7 +3849,7 @@ svm_range_get_attr(struct kfd_process *p, struct mm_struct *mm,</div><div class='ctx'> 	node = interval_tree_iter_first(&amp;svms-&gt;objects, start, last);</div><div class='ctx'> 	if (!node) {</div><div class='ctx'> 		pr_debug("range attrs not found return default values\n");</div><div class='del'>-		svm_range_set_default_attributes(&amp;location, &amp;prefetch_loc,</div><div class='add'>+		svm_range_set_default_attributes(svms, &amp;location, &amp;prefetch_loc,</div><div class='ctx'> 						 &amp;granularity, &amp;flags_and);</div><div class='ctx'> 		flags_or = flags_and;</div><div class='ctx'> 		if (p-&gt;xnack_enabled)</div><div class='hunk'>@@ -3975,8 +4104,8 @@ exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,</div><div class='del'>-		       uint64_t *svm_priv_data_size)</div><div class='add'>+void svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,</div><div class='add'>+			uint64_t *svm_priv_data_size)</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t total_size, accessibility_size, common_attr_size;</div><div class='ctx'> 	int nattr_common = 4, nattr_accessibility = 1;</div><div class='hunk'>@@ -3988,8 +4117,6 @@ int svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,</div><div class='ctx'> 	*svm_priv_data_size = 0;</div><div class='ctx'> </div><div class='ctx'> 	svms = &amp;p-&gt;svms;</div><div class='del'>-	if (!svms)</div><div class='del'>-		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;svms-&gt;lock);</div><div class='ctx'> 	list_for_each_entry(prange, &amp;svms-&gt;list, list) {</div><div class='hunk'>@@ -4031,7 +4158,6 @@ int svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("num_svm_ranges %u total_priv_size %llu\n", *num_svm_ranges,</div><div class='ctx'> 		 *svm_priv_data_size);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int kfd_criu_checkpoint_svm(struct kfd_process *p,</div><div class='hunk'>@@ -4048,8 +4174,6 @@ int kfd_criu_checkpoint_svm(struct kfd_process *p,</div><div class='ctx'> 	struct mm_struct *mm;</div><div class='ctx'> </div><div class='ctx'> 	svms = &amp;p-&gt;svms;</div><div class='del'>-	if (!svms)</div><div class='del'>-		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mm = get_task_mm(p-&gt;lead_thread);</div><div class='ctx'> 	if (!mm) {</div><div class='hunk'>@@ -4147,7 +4271,7 @@ svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start,</div><div class='ctx'> 		r = svm_range_get_attr(p, mm, start, size, nattrs, attrs);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		r = EINVAL;</div><div class='add'>+		r = -EINVAL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h<br/>index 026863a0abcd..a63dfc95b602 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_svm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_svm.h</a></div><div class='hunk'>@@ -31,7 +31,6 @@</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/sched/mm.h&gt;</div><div class='del'>-#include &lt;linux/hmm.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> </div><div class='hunk'>@@ -137,6 +136,7 @@ struct svm_range {</div><div class='ctx'> 	DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE);</div><div class='ctx'> 	DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE);</div><div class='ctx'> 	bool				mapped_to_gpu;</div><div class='add'>+	atomic_t			queue_refcount;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline void svm_range_lock(struct svm_range *prange)</div><div class='hunk'>@@ -173,7 +173,7 @@ int svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 			    bool clear);</div><div class='ctx'> void svm_range_vram_node_free(struct svm_range *prange);</div><div class='ctx'> int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='del'>-			    uint32_t vmid, uint32_t node_id, uint64_t addr,</div><div class='add'>+			    uint32_t vmid, uint32_t node_id, uint64_t addr, uint64_t ts,</div><div class='ctx'> 			    bool write_fault);</div><div class='ctx'> int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence);</div><div class='ctx'> void svm_range_add_list_work(struct svm_range_list *svms,</div><div class='hunk'>@@ -183,8 +183,8 @@ void schedule_deferred_list_work(struct svm_range_list *svms);</div><div class='ctx'> void svm_range_dma_unmap_dev(struct device *dev, dma_addr_t *dma_addr,</div><div class='ctx'> 			 unsigned long offset, unsigned long npages);</div><div class='ctx'> void svm_range_dma_unmap(struct svm_range *prange);</div><div class='del'>-int svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,</div><div class='del'>-		       uint64_t *svm_priv_data_size);</div><div class='add'>+void svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges,</div><div class='add'>+			uint64_t *svm_priv_data_size);</div><div class='ctx'> int kfd_criu_checkpoint_svm(struct kfd_process *p,</div><div class='ctx'> 			    uint8_t __user *user_priv_data,</div><div class='ctx'> 			    uint64_t *priv_offset);</div><div class='hunk'>@@ -201,7 +201,7 @@ void svm_range_list_lock_and_flush_work(struct svm_range_list *svms, struct mm_s</div><div class='ctx'>  * is initialized to not 0 when page migration register device memory.</div><div class='ctx'>  */</div><div class='ctx'> #define KFD_IS_SVM_API_SUPPORTED(adev) ((adev)-&gt;kfd.pgmap.type != 0 ||\</div><div class='del'>-					(adev)-&gt;gmc.is_app_apu)</div><div class='add'>+					((adev)-&gt;apu_prefer_gtt))</div><div class='ctx'> </div><div class='ctx'> void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);</div><div class='ctx'> </div><div class='hunk'>@@ -224,7 +224,7 @@ static inline void svm_range_list_fini(struct kfd_process *p)</div><div class='ctx'> static inline int svm_range_restore_pages(struct amdgpu_device *adev,</div><div class='ctx'> 					  unsigned int pasid,</div><div class='ctx'> 					  uint32_t client_id, uint32_t node_id,</div><div class='del'>-					  uint64_t addr, bool write_fault)</div><div class='add'>+					  uint64_t addr, uint64_t ts, bool write_fault)</div><div class='ctx'> {</div><div class='ctx'> 	return -EFAULT;</div><div class='ctx'> }</div><div class='hunk'>@@ -236,13 +236,12 @@ static inline int svm_range_schedule_evict_svm_bo(</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int svm_range_get_info(struct kfd_process *p,</div><div class='del'>-				     uint32_t *num_svm_ranges,</div><div class='del'>-				     uint64_t *svm_priv_data_size)</div><div class='add'>+static inline void svm_range_get_info(struct kfd_process *p,</div><div class='add'>+				      uint32_t *num_svm_ranges,</div><div class='add'>+				      uint64_t *svm_priv_data_size)</div><div class='ctx'> {</div><div class='ctx'> 	*num_svm_ranges = 0;</div><div class='ctx'> 	*svm_priv_data_size = 0;</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int kfd_criu_checkpoint_svm(struct kfd_process *p,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c<br/>index c51f131eaa2f..811636af14ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_topology.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_topology.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_topology.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_topology.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #include &lt;linux/log2.h&gt;</div><div class='ctx'> #include &lt;linux/dmi.h&gt;</div><div class='ctx'> #include &lt;linux/atomic.h&gt;</div><div class='add'>+#include &lt;linux/crc16.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "kfd_priv.h"</div><div class='ctx'> #include "kfd_crat.h"</div><div class='hunk'>@@ -107,24 +108,6 @@ struct kfd_node *kfd_device_by_id(uint32_t gpu_id)</div><div class='ctx'> 	return top_dev-&gt;gpu;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev)</div><div class='del'>-{</div><div class='del'>-	struct kfd_topology_device *top_dev;</div><div class='del'>-	struct kfd_node *device = NULL;</div><div class='del'>-</div><div class='del'>-	down_read(&amp;topology_lock);</div><div class='del'>-</div><div class='del'>-	list_for_each_entry(top_dev, &amp;topology_device_list, list)</div><div class='del'>-		if (top_dev-&gt;gpu &amp;&amp; top_dev-&gt;gpu-&gt;adev-&gt;pdev == pdev) {</div><div class='del'>-			device = top_dev-&gt;gpu;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	up_read(&amp;topology_lock);</div><div class='del'>-</div><div class='del'>-	return device;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* Called with write topology_lock acquired */</div><div class='ctx'> static void kfd_release_topology_device(struct kfd_topology_device *dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -291,6 +274,8 @@ static ssize_t iolink_show(struct kobject *kobj, struct attribute *attr,</div><div class='ctx'> 			      iolink-&gt;max_bandwidth);</div><div class='ctx'> 	sysfs_show_32bit_prop(buffer, offs, "recommended_transfer_size",</div><div class='ctx'> 			      iolink-&gt;rec_transfer_size);</div><div class='add'>+	sysfs_show_32bit_prop(buffer, offs, "recommended_sdma_engine_id_mask",</div><div class='add'>+			      iolink-&gt;rec_sdma_eng_id_mask);</div><div class='ctx'> 	sysfs_show_32bit_prop(buffer, offs, "flags", iolink-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	return offs;</div><div class='hunk'>@@ -525,6 +510,10 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,</div><div class='ctx'> 			dev-&gt;node_props.capability |=</div><div class='ctx'> 					HSA_CAP_AQL_QUEUE_DOUBLE_MAP;</div><div class='ctx'> </div><div class='add'>+		if (KFD_GC_VERSION(dev-&gt;gpu) &lt; IP_VERSION(10, 0, 0) &amp;&amp;</div><div class='add'>+			(dev-&gt;gpu-&gt;adev-&gt;sdma.supported_reset &amp; AMDGPU_RESET_TYPE_PER_QUEUE))</div><div class='add'>+				dev-&gt;node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;</div><div class='add'>+</div><div class='ctx'> 		sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",</div><div class='ctx'> 			dev-&gt;node_props.max_engine_clk_fcompute);</div><div class='ctx'> </div><div class='hunk'>@@ -534,11 +523,17 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,</div><div class='ctx'> 				      dev-&gt;gpu-&gt;kfd-&gt;mec_fw_version);</div><div class='ctx'> 		sysfs_show_32bit_prop(buffer, offs, "capability",</div><div class='ctx'> 				      dev-&gt;node_props.capability);</div><div class='add'>+		sysfs_show_32bit_prop(buffer, offs, "capability2",</div><div class='add'>+				      dev-&gt;node_props.capability2);</div><div class='ctx'> 		sysfs_show_64bit_prop(buffer, offs, "debug_prop",</div><div class='ctx'> 				      dev-&gt;node_props.debug_prop);</div><div class='ctx'> 		sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version",</div><div class='ctx'> 				      dev-&gt;gpu-&gt;kfd-&gt;sdma_fw_version);</div><div class='ctx'> 		sysfs_show_64bit_prop(buffer, offs, "unique_id",</div><div class='add'>+				      dev-&gt;gpu-&gt;xcp &amp;&amp;</div><div class='add'>+				      (dev-&gt;gpu-&gt;xcp-&gt;xcp_mgr-&gt;mode !=</div><div class='add'>+				       AMDGPU_SPX_PARTITION_MODE) ?</div><div class='add'>+				      dev-&gt;gpu-&gt;xcp-&gt;unique_id :</div><div class='ctx'> 				      dev-&gt;gpu-&gt;adev-&gt;unique_id);</div><div class='ctx'> 		sysfs_show_32bit_prop(buffer, offs, "num_xcc",</div><div class='ctx'> 				      NUM_XCC(dev-&gt;gpu-&gt;xcc_mask));</div><div class='hunk'>@@ -958,32 +953,30 @@ static void kfd_update_system_properties(void)</div><div class='ctx'> 	dev = list_last_entry(&amp;topology_device_list,</div><div class='ctx'> 			struct kfd_topology_device, list);</div><div class='ctx'> 	if (dev) {</div><div class='del'>-		sys_props.platform_id =</div><div class='del'>-			(*((uint64_t *)dev-&gt;oem_id)) &amp; CRAT_OEMID_64BIT_MASK;</div><div class='add'>+		sys_props.platform_id = dev-&gt;oem_id64;</div><div class='ctx'> 		sys_props.platform_oem = *((uint64_t *)dev-&gt;oem_table_id);</div><div class='ctx'> 		sys_props.platform_rev = dev-&gt;oem_revision;</div><div class='ctx'> 	}</div><div class='ctx'> 	up_read(&amp;topology_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void find_system_memory(const struct dmi_header *dm,</div><div class='del'>-	void *private)</div><div class='add'>+static void find_system_memory(const struct dmi_header *dm, void *private)</div><div class='ctx'> {</div><div class='add'>+	struct dmi_mem_device *memdev = container_of(dm, struct dmi_mem_device, header);</div><div class='ctx'> 	struct kfd_mem_properties *mem;</div><div class='del'>-	u16 mem_width, mem_clock;</div><div class='ctx'> 	struct kfd_topology_device *kdev =</div><div class='ctx'> 		(struct kfd_topology_device *)private;</div><div class='del'>-	const u8 *dmi_data = (const u8 *)(dm + 1);</div><div class='del'>-</div><div class='del'>-	if (dm-&gt;type == DMI_ENTRY_MEM_DEVICE &amp;&amp; dm-&gt;length &gt;= 0x15) {</div><div class='del'>-		mem_width = (u16)(*(const u16 *)(dmi_data + 0x6));</div><div class='del'>-		mem_clock = (u16)(*(const u16 *)(dmi_data + 0x11));</div><div class='del'>-		list_for_each_entry(mem, &amp;kdev-&gt;mem_props, list) {</div><div class='del'>-			if (mem_width != 0xFFFF &amp;&amp; mem_width != 0)</div><div class='del'>-				mem-&gt;width = mem_width;</div><div class='del'>-			if (mem_clock != 0)</div><div class='del'>-				mem-&gt;mem_clk_max = mem_clock;</div><div class='del'>-		}</div><div class='add'>+</div><div class='add'>+	if (memdev-&gt;header.type != DMI_ENTRY_MEM_DEVICE)</div><div class='add'>+		return;</div><div class='add'>+	if (memdev-&gt;header.length &lt; sizeof(struct dmi_mem_device))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(mem, &amp;kdev-&gt;mem_props, list) {</div><div class='add'>+		if (memdev-&gt;total_width != 0xFFFF &amp;&amp; memdev-&gt;total_width != 0)</div><div class='add'>+			mem-&gt;width = memdev-&gt;total_width;</div><div class='add'>+		if (memdev-&gt;speed != 0)</div><div class='add'>+			mem-&gt;mem_clk_max = memdev-&gt;speed;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1092,14 +1085,17 @@ void kfd_topology_shutdown(void)</div><div class='ctx'> </div><div class='ctx'> static uint32_t kfd_generate_gpu_id(struct kfd_node *gpu)</div><div class='ctx'> {</div><div class='del'>-	uint32_t hashout;</div><div class='add'>+	uint32_t gpu_id;</div><div class='ctx'> 	uint32_t buf[8];</div><div class='ctx'> 	uint64_t local_mem_size;</div><div class='del'>-	int i;</div><div class='add'>+	struct kfd_topology_device *dev;</div><div class='add'>+	bool is_unique;</div><div class='add'>+	uint8_t *crc_buf;</div><div class='ctx'> </div><div class='ctx'> 	if (!gpu)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	crc_buf = (uint8_t *)&amp;buf;</div><div class='ctx'> 	local_mem_size = gpu-&gt;local_mem_info.local_mem_size_private +</div><div class='ctx'> 			gpu-&gt;local_mem_info.local_mem_size_public;</div><div class='ctx'> 	buf[0] = gpu-&gt;adev-&gt;pdev-&gt;devfn;</div><div class='hunk'>@@ -1112,10 +1108,34 @@ static uint32_t kfd_generate_gpu_id(struct kfd_node *gpu)</div><div class='ctx'> 	buf[6] = upper_32_bits(local_mem_size);</div><div class='ctx'> 	buf[7] = (ffs(gpu-&gt;xcc_mask) - 1) | (NUM_XCC(gpu-&gt;xcc_mask) &lt;&lt; 16);</div><div class='ctx'> </div><div class='del'>-	for (i = 0, hashout = 0; i &lt; 8; i++)</div><div class='del'>-		hashout ^= hash_32(buf[i], KFD_GPU_ID_HASH_WIDTH);</div><div class='add'>+	gpu_id = crc16(0, crc_buf, sizeof(buf)) &amp;</div><div class='add'>+		 ((1 &lt;&lt; KFD_GPU_ID_HASH_WIDTH) - 1);</div><div class='ctx'> </div><div class='del'>-	return hashout;</div><div class='add'>+	/* There is a very small possibility when generating a</div><div class='add'>+	 * 16 (KFD_GPU_ID_HASH_WIDTH) bit value from 8 word buffer</div><div class='add'>+	 * that the value could be 0 or non-unique. So, check if</div><div class='add'>+	 * it is unique and non-zero. If not unique increment till</div><div class='add'>+	 * unique one is found. In case of overflow, restart from 1</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	down_read(&amp;topology_lock);</div><div class='add'>+	do {</div><div class='add'>+		is_unique = true;</div><div class='add'>+		if (!gpu_id)</div><div class='add'>+			gpu_id = 1;</div><div class='add'>+		list_for_each_entry(dev, &amp;topology_device_list, list) {</div><div class='add'>+			if (dev-&gt;gpu &amp;&amp; dev-&gt;gpu_id == gpu_id) {</div><div class='add'>+				is_unique = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (unlikely(!is_unique))</div><div class='add'>+			gpu_id = (gpu_id + 1) &amp;</div><div class='add'>+				  ((1 &lt;&lt; KFD_GPU_ID_HASH_WIDTH) - 1);</div><div class='add'>+	} while (!is_unique);</div><div class='add'>+	up_read(&amp;topology_lock);</div><div class='add'>+</div><div class='add'>+	return gpu_id;</div><div class='ctx'> }</div><div class='ctx'> /* kfd_assign_gpu - Attach @gpu to the correct kfd topology device. If</div><div class='ctx'>  *		the GPU device is not already present in the topology device</div><div class='hunk'>@@ -1238,6 +1258,61 @@ static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define REC_SDMA_NUM_GPU	8</div><div class='add'>+static const int rec_sdma_eng_map[REC_SDMA_NUM_GPU][REC_SDMA_NUM_GPU] = {</div><div class='add'>+							{ -1, 14, 12, 2, 4, 8, 10, 6 },</div><div class='add'>+							{ 14, -1, 2, 10, 8, 4, 6, 12 },</div><div class='add'>+							{ 10, 2, -1, 12, 14, 6, 4, 8 },</div><div class='add'>+							{ 2, 12, 10, -1, 6, 14, 8, 4 },</div><div class='add'>+							{ 4, 8, 14, 6, -1, 10, 12, 2 },</div><div class='add'>+							{ 8, 4, 6, 14, 12, -1, 2, 10 },</div><div class='add'>+							{ 10, 6, 4, 8, 12, 2, -1, 14 },</div><div class='add'>+							{ 6, 12, 8, 4, 2, 10, 14, -1 }};</div><div class='add'>+</div><div class='add'>+static void kfd_set_recommended_sdma_engines(struct kfd_topology_device *to_dev,</div><div class='add'>+					     struct kfd_iolink_properties *outbound_link,</div><div class='add'>+					     struct kfd_iolink_properties *inbound_link)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *gpu = outbound_link-&gt;gpu;</div><div class='add'>+	struct amdgpu_device *adev = gpu-&gt;adev;</div><div class='add'>+	unsigned int num_xgmi_nodes = adev-&gt;gmc.xgmi.num_physical_nodes;</div><div class='add'>+	unsigned int num_xgmi_sdma_engines = kfd_get_num_xgmi_sdma_engines(gpu);</div><div class='add'>+	unsigned int num_sdma_engines = kfd_get_num_sdma_engines(gpu);</div><div class='add'>+	uint32_t sdma_eng_id_mask = (1 &lt;&lt; num_sdma_engines) - 1;</div><div class='add'>+	uint32_t xgmi_sdma_eng_id_mask =</div><div class='add'>+			((1 &lt;&lt; num_xgmi_sdma_engines) - 1) &lt;&lt; num_sdma_engines;</div><div class='add'>+</div><div class='add'>+	bool support_rec_eng = !amdgpu_sriov_vf(adev) &amp;&amp; to_dev-&gt;gpu &amp;&amp;</div><div class='add'>+		adev-&gt;aid_mask &amp;&amp; num_xgmi_nodes &amp;&amp; gpu-&gt;kfd-&gt;num_nodes == 1 &amp;&amp;</div><div class='add'>+		num_xgmi_sdma_engines &gt;= 6 &amp;&amp; (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp;</div><div class='add'>+		num_xgmi_nodes == 8);</div><div class='add'>+</div><div class='add'>+	if (support_rec_eng) {</div><div class='add'>+		int src_socket_id = adev-&gt;gmc.xgmi.physical_node_id;</div><div class='add'>+		int dst_socket_id = to_dev-&gt;gpu-&gt;adev-&gt;gmc.xgmi.physical_node_id;</div><div class='add'>+		unsigned int reshift = num_xgmi_sdma_engines == 6 ? 1 : 0;</div><div class='add'>+</div><div class='add'>+		outbound_link-&gt;rec_sdma_eng_id_mask =</div><div class='add'>+			1 &lt;&lt; (rec_sdma_eng_map[src_socket_id][dst_socket_id] &gt;&gt; reshift);</div><div class='add'>+		inbound_link-&gt;rec_sdma_eng_id_mask =</div><div class='add'>+			1 &lt;&lt; (rec_sdma_eng_map[dst_socket_id][src_socket_id] &gt;&gt; reshift);</div><div class='add'>+</div><div class='add'>+		/* If recommended engine is out of range, need to reset the mask */</div><div class='add'>+		if (outbound_link-&gt;rec_sdma_eng_id_mask &amp; sdma_eng_id_mask)</div><div class='add'>+			outbound_link-&gt;rec_sdma_eng_id_mask = xgmi_sdma_eng_id_mask;</div><div class='add'>+		if (inbound_link-&gt;rec_sdma_eng_id_mask &amp; sdma_eng_id_mask)</div><div class='add'>+			inbound_link-&gt;rec_sdma_eng_id_mask = xgmi_sdma_eng_id_mask;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		uint32_t engine_mask = (outbound_link-&gt;iolink_type == CRAT_IOLINK_TYPE_XGMI &amp;&amp;</div><div class='add'>+				num_xgmi_sdma_engines &amp;&amp; to_dev-&gt;gpu) ? xgmi_sdma_eng_id_mask :</div><div class='add'>+				sdma_eng_id_mask;</div><div class='add'>+</div><div class='add'>+		outbound_link-&gt;rec_sdma_eng_id_mask = engine_mask;</div><div class='add'>+		inbound_link-&gt;rec_sdma_eng_id_mask = engine_mask;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_iolink_properties *link, *inbound_link;</div><div class='hunk'>@@ -1276,6 +1351,7 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)</div><div class='ctx'> 			inbound_link-&gt;flags = CRAT_IOLINK_FLAGS_ENABLED;</div><div class='ctx'> 			kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);</div><div class='ctx'> 			kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);</div><div class='add'>+			kfd_set_recommended_sdma_engines(peer_dev, link, inbound_link);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1515,7 +1591,8 @@ static int kfd_dev_create_p2p_links(void)</div><div class='ctx'> 			break;</div><div class='ctx'> 		if (!dev-&gt;gpu || !dev-&gt;gpu-&gt;adev ||</div><div class='ctx'> 		    (dev-&gt;gpu-&gt;kfd-&gt;hive_id &amp;&amp;</div><div class='del'>-		     dev-&gt;gpu-&gt;kfd-&gt;hive_id == new_dev-&gt;gpu-&gt;kfd-&gt;hive_id))</div><div class='add'>+		     dev-&gt;gpu-&gt;kfd-&gt;hive_id == new_dev-&gt;gpu-&gt;kfd-&gt;hive_id &amp;&amp;</div><div class='add'>+		     amdgpu_xgmi_get_is_sharing_enabled(dev-&gt;gpu-&gt;adev, new_dev-&gt;gpu-&gt;adev)))</div><div class='ctx'> 			goto next;</div><div class='ctx'> </div><div class='ctx'> 		/* check if node(s) is/are peer accessible in one direction or bi-direction */</div><div class='hunk'>@@ -1605,17 +1682,32 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext,</div><div class='ctx'> 				int cache_type, unsigned int cu_processor_id,</div><div class='ctx'> 				struct kfd_node *knode)</div><div class='ctx'> {</div><div class='del'>-	unsigned int cu_sibling_map_mask;</div><div class='add'>+	unsigned int cu_sibling_map_mask = 0;</div><div class='ctx'> 	int first_active_cu;</div><div class='ctx'> 	int i, j, k, xcc, start, end;</div><div class='ctx'> 	int num_xcc = NUM_XCC(knode-&gt;xcc_mask);</div><div class='ctx'> 	struct kfd_cache_properties *pcache = NULL;</div><div class='ctx'> 	enum amdgpu_memory_partition mode;</div><div class='ctx'> 	struct amdgpu_device *adev = knode-&gt;adev;</div><div class='add'>+	bool found = false;</div><div class='ctx'> </div><div class='ctx'> 	start = ffs(knode-&gt;xcc_mask) - 1;</div><div class='ctx'> 	end = start + num_xcc;</div><div class='del'>-	cu_sibling_map_mask = cu_info-&gt;bitmap[start][0][0];</div><div class='add'>+</div><div class='add'>+	/* To find the bitmap in the first active cu in the first</div><div class='add'>+	 * xcc, it is based on the assumption that evrey xcc must</div><div class='add'>+	 * have at least one active cu.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; gfx_info-&gt;max_shader_engines &amp;&amp; !found; i++) {</div><div class='add'>+		for (j = 0; j &lt; gfx_info-&gt;max_sh_per_se &amp;&amp; !found; j++) {</div><div class='add'>+			if (cu_info-&gt;bitmap[start][i % 4][j % 4]) {</div><div class='add'>+				cu_sibling_map_mask =</div><div class='add'>+					cu_info-&gt;bitmap[start][i % 4][j % 4];</div><div class='add'>+				found = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	cu_sibling_map_mask &amp;=</div><div class='ctx'> 		((1 &lt;&lt; pcache_info[cache_type].num_cu_shared) - 1);</div><div class='ctx'> 	first_active_cu = ffs(cu_sibling_map_mask);</div><div class='hunk'>@@ -1635,7 +1727,9 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext,</div><div class='ctx'> 		pcache-&gt;cache_level = pcache_info[cache_type].cache_level;</div><div class='ctx'> 		pcache-&gt;cacheline_size = pcache_info[cache_type].cache_line_size;</div><div class='ctx'> </div><div class='del'>-		if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3))</div><div class='add'>+		if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		    KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 4) ||</div><div class='add'>+		    KFD_GC_VERSION(knode) == IP_VERSION(9, 5, 0))</div><div class='ctx'> 			mode = adev-&gt;gmc.gmc_funcs-&gt;query_mem_partition_mode(adev);</div><div class='ctx'> 		else</div><div class='ctx'> 			mode = UNKNOWN_MEMORY_PARTITION_MODE;</div><div class='hunk'>@@ -1697,7 +1791,7 @@ static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct</div><div class='ctx'> 	struct amdgpu_cu_info *cu_info = &amp;kdev-&gt;adev-&gt;gfx.cu_info;</div><div class='ctx'> 	struct amdgpu_gfx_config *gfx_info = &amp;kdev-&gt;adev-&gt;gfx.config;</div><div class='ctx'> 	int gpu_processor_id;</div><div class='del'>-	struct kfd_cache_properties *props_ext;</div><div class='add'>+	struct kfd_cache_properties *props_ext = NULL;</div><div class='ctx'> 	int num_of_entries = 0;</div><div class='ctx'> 	int num_of_cache_types = 0;</div><div class='ctx'> 	struct kfd_gpu_cache_info cache_info[KFD_MAX_CACHE_TYPES];</div><div class='hunk'>@@ -1772,7 +1866,7 @@ static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct</div><div class='ctx'> 	pr_debug("Added [%d] GPU cache entries\n", num_of_entries);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,</div><div class='add'>+static int kfd_topology_add_device_locked(struct kfd_node *gpu,</div><div class='ctx'> 					  struct kfd_topology_device **dev)</div><div class='ctx'> {</div><div class='ctx'> 	int proximity_domain = ++topology_crat_proximity_domain;</div><div class='hunk'>@@ -1785,8 +1879,7 @@ static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,</div><div class='ctx'> 					    COMPUTE_UNIT_GPU, gpu,</div><div class='ctx'> 					    proximity_domain);</div><div class='ctx'> 	if (res) {</div><div class='del'>-		pr_err("Error creating VCRAT for GPU (ID: 0x%x)\n",</div><div class='del'>-		       gpu_id);</div><div class='add'>+		dev_err(gpu-&gt;adev-&gt;dev, "Error creating VCRAT\n");</div><div class='ctx'> 		topology_crat_proximity_domain--;</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1797,8 +1890,7 @@ static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,</div><div class='ctx'> 				   &amp;temp_topology_device_list,</div><div class='ctx'> 				   proximity_domain);</div><div class='ctx'> 	if (res) {</div><div class='del'>-		pr_err("Error parsing VCRAT for GPU (ID: 0x%x)\n",</div><div class='del'>-		       gpu_id);</div><div class='add'>+		dev_err(gpu-&gt;adev-&gt;dev, "Error parsing VCRAT\n");</div><div class='ctx'> 		topology_crat_proximity_domain--;</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1824,8 +1916,8 @@ static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,</div><div class='ctx'> 	if (!res)</div><div class='ctx'> 		sys_props.generation_count++;</div><div class='ctx'> 	else</div><div class='del'>-		pr_err("Failed to update GPU (ID: 0x%x) to sysfs topology. res=%d\n",</div><div class='del'>-		       gpu_id, res);</div><div class='add'>+		dev_err(gpu-&gt;adev-&gt;dev, "Failed to update GPU to sysfs topology. res=%d\n",</div><div class='add'>+			res);</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='ctx'> 	kfd_destroy_crat_image(crat_image);</div><div class='hunk'>@@ -1908,7 +2000,8 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)</div><div class='ctx'> 		dev-&gt;node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;</div><div class='ctx'> </div><div class='ctx'> 	if (KFD_GC_VERSION(dev-&gt;gpu) &lt; IP_VERSION(10, 0, 0)) {</div><div class='del'>-		if (KFD_GC_VERSION(dev-&gt;gpu) == IP_VERSION(9, 4, 3))</div><div class='add'>+		if (KFD_GC_VERSION(dev-&gt;gpu) == IP_VERSION(9, 4, 3) ||</div><div class='add'>+		    KFD_GC_VERSION(dev-&gt;gpu) == IP_VERSION(9, 4, 4))</div><div class='ctx'> 			dev-&gt;node_props.debug_prop |=</div><div class='ctx'> 				HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 |</div><div class='ctx'> 				HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3;</div><div class='hunk'>@@ -1920,13 +2013,17 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)</div><div class='ctx'> 		if (KFD_GC_VERSION(dev-&gt;gpu) &gt;= IP_VERSION(9, 4, 2))</div><div class='ctx'> 			dev-&gt;node_props.capability |=</div><div class='ctx'> 				HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_sriov_vf(dev-&gt;gpu-&gt;adev))</div><div class='add'>+			dev-&gt;node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dev-&gt;node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |</div><div class='ctx'> 					HSA_DBG_WATCH_ADDR_MASK_HI_BIT;</div><div class='ctx'> </div><div class='del'>-		if (KFD_GC_VERSION(dev-&gt;gpu) &gt;= IP_VERSION(11, 0, 0))</div><div class='add'>+		if (KFD_GC_VERSION(dev-&gt;gpu) &gt;= IP_VERSION(12, 0, 0))</div><div class='ctx'> 			dev-&gt;node_props.capability |=</div><div class='del'>-				HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;</div><div class='add'>+				HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	kfd_topology_set_dbg_firmware_support(dev);</div><div class='hunk'>@@ -1942,14 +2039,12 @@ int kfd_topology_add_device(struct kfd_node *gpu)</div><div class='ctx'> 	struct amdgpu_gfx_config *gfx_info = &amp;gpu-&gt;adev-&gt;gfx.config;</div><div class='ctx'> 	struct amdgpu_cu_info *cu_info = &amp;gpu-&gt;adev-&gt;gfx.cu_info;</div><div class='ctx'> </div><div class='del'>-	gpu_id = kfd_generate_gpu_id(gpu);</div><div class='ctx'> 	if (gpu-&gt;xcp &amp;&amp; !gpu-&gt;xcp-&gt;ddev) {</div><div class='ctx'> 		dev_warn(gpu-&gt;adev-&gt;dev,</div><div class='del'>-		"Won't add GPU (ID: 0x%x) to topology since it has no drm node assigned.",</div><div class='del'>-		gpu_id);</div><div class='add'>+			 "Won't add GPU to topology since it has no drm node assigned.");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	} else {</div><div class='del'>-		pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id);</div><div class='add'>+		dev_dbg(gpu-&gt;adev-&gt;dev, "Adding new GPU to topology\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check to see if this gpu device exists in the topology_device_list.</div><div class='hunk'>@@ -1961,11 +2056,12 @@ int kfd_topology_add_device(struct kfd_node *gpu)</div><div class='ctx'> 	down_write(&amp;topology_lock);</div><div class='ctx'> 	dev = kfd_assign_gpu(gpu);</div><div class='ctx'> 	if (!dev)</div><div class='del'>-		res = kfd_topology_add_device_locked(gpu, gpu_id, &amp;dev);</div><div class='add'>+		res = kfd_topology_add_device_locked(gpu, &amp;dev);</div><div class='ctx'> 	up_write(&amp;topology_lock);</div><div class='ctx'> 	if (res)</div><div class='ctx'> 		return res;</div><div class='ctx'> </div><div class='add'>+	gpu_id = kfd_generate_gpu_id(gpu);</div><div class='ctx'> 	dev-&gt;gpu_id = gpu_id;</div><div class='ctx'> 	gpu-&gt;id = gpu_id;</div><div class='ctx'> </div><div class='hunk'>@@ -1997,9 +2093,8 @@ int kfd_topology_add_device(struct kfd_node *gpu)</div><div class='ctx'> 			HSA_CAP_ASIC_REVISION_MASK);</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;node_props.location_id = pci_dev_id(gpu-&gt;adev-&gt;pdev);</div><div class='del'>-	/* On multi-partition nodes, node id = location_id[31:28] */</div><div class='ctx'> 	if (gpu-&gt;kfd-&gt;num_nodes &gt; 1)</div><div class='del'>-		dev-&gt;node_props.location_id |= (dev-&gt;gpu-&gt;node_id &lt;&lt; 28);</div><div class='add'>+		dev-&gt;node_props.location_id |= dev-&gt;gpu-&gt;node_id;</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;node_props.domain = pci_domain_nr(gpu-&gt;adev-&gt;pdev-&gt;bus);</div><div class='ctx'> 	dev-&gt;node_props.max_engine_clk_fcompute =</div><div class='hunk'>@@ -2091,6 +2186,8 @@ int kfd_topology_add_device(struct kfd_node *gpu)</div><div class='ctx'> 		dev-&gt;gpu-&gt;adev-&gt;gmc.xgmi.connected_to_cpu)</div><div class='ctx'> 		dev-&gt;node_props.capability |= HSA_CAP_FLAGS_COHERENTHOSTACCESS;</div><div class='ctx'> </div><div class='add'>+	kfd_queue_ctx_save_restore_size(dev);</div><div class='add'>+</div><div class='ctx'> 	kfd_debug_print_topology();</div><div class='ctx'> </div><div class='ctx'> 	kfd_notify_gpu_change(gpu_id, 1);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h<br/>index 27386ce9a021..3de8ec0043bb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_topology.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/kfd_topology.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_topology.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/kfd_topology.h</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'> #ifndef __KFD_TOPOLOGY_H__</div><div class='ctx'> #define __KFD_TOPOLOGY_H__</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/dmi.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/kfd_sysfs.h&gt;</div><div class='hunk'>@@ -50,6 +51,7 @@ struct kfd_node_properties {</div><div class='ctx'> 	uint32_t cpu_core_id_base;</div><div class='ctx'> 	uint32_t simd_id_base;</div><div class='ctx'> 	uint32_t capability;</div><div class='add'>+	uint32_t capability2;</div><div class='ctx'> 	uint64_t debug_prop;</div><div class='ctx'> 	uint32_t max_waves_per_simd;</div><div class='ctx'> 	uint32_t lds_size_in_kb;</div><div class='hunk'>@@ -74,6 +76,10 @@ struct kfd_node_properties {</div><div class='ctx'> 	uint32_t num_sdma_xgmi_engines;</div><div class='ctx'> 	uint32_t num_sdma_queues_per_engine;</div><div class='ctx'> 	uint32_t num_cp_queues;</div><div class='add'>+	uint32_t cwsr_size;</div><div class='add'>+	uint32_t ctl_stack_size;</div><div class='add'>+	uint32_t eop_buffer_size;</div><div class='add'>+	uint32_t debug_memory_size;</div><div class='ctx'> 	char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -121,6 +127,7 @@ struct kfd_iolink_properties {</div><div class='ctx'> 	uint32_t		min_bandwidth;</div><div class='ctx'> 	uint32_t		max_bandwidth;</div><div class='ctx'> 	uint32_t		rec_transfer_size;</div><div class='add'>+	uint32_t		rec_sdma_eng_id_mask;</div><div class='ctx'> 	uint32_t		flags;</div><div class='ctx'> 	struct kfd_node		*gpu;</div><div class='ctx'> 	struct kobject		*kobj;</div><div class='hunk'>@@ -154,7 +161,10 @@ struct kfd_topology_device {</div><div class='ctx'> 	struct attribute		attr_gpuid;</div><div class='ctx'> 	struct attribute		attr_name;</div><div class='ctx'> 	struct attribute		attr_props;</div><div class='del'>-	uint8_t				oem_id[CRAT_OEMID_LENGTH];</div><div class='add'>+	union {</div><div class='add'>+		uint8_t				oem_id[CRAT_OEMID_LENGTH];</div><div class='add'>+		uint64_t			oem_id64;</div><div class='add'>+	};</div><div class='ctx'> 	uint8_t				oem_table_id[CRAT_OEMTABLEID_LENGTH];</div><div class='ctx'> 	uint32_t			oem_revision;</div><div class='ctx'> };</div><div class='hunk'>@@ -171,6 +181,22 @@ struct kfd_system_properties {</div><div class='ctx'> 	struct attribute	attr_props;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dmi_mem_device {</div><div class='add'>+	struct dmi_header header;</div><div class='add'>+	u16 physical_handle;</div><div class='add'>+	u16 error_handle;</div><div class='add'>+	u16 total_width;</div><div class='add'>+	u16 data_width;</div><div class='add'>+	u16 size;</div><div class='add'>+	u8 form_factor;</div><div class='add'>+	u8 device_set;</div><div class='add'>+	u8 device_locator;</div><div class='add'>+	u8 bank_locator;</div><div class='add'>+	u8 memory_type;</div><div class='add'>+	u16 type_detail;</div><div class='add'>+	u16 speed;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='ctx'> struct kfd_topology_device *kfd_create_topology_device(</div><div class='ctx'> 		struct list_head *device_list);</div><div class='ctx'> void kfd_release_topology_device_list(struct list_head *device_list);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/soc15_int.h b/drivers/gpu/drm/amd/amdkfd/soc15_int.h<br/>index 10138676f27f..e5c0205f2618 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/soc15_int.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdkfd/soc15_int.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdkfd/soc15_int.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdkfd/soc15_int.h</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #define SOC15_INTSRC_CP_BAD_OPCODE	183</div><div class='ctx'> #define SOC15_INTSRC_SQ_INTERRUPT_MSG	239</div><div class='ctx'> #define SOC15_INTSRC_VMC_FAULT		0</div><div class='add'>+#define SOC15_INTSRC_VMC_UTCL2_POISON	1</div><div class='ctx'> #define SOC15_INTSRC_SDMA_TRAP		224</div><div class='ctx'> #define SOC15_INTSRC_SDMA_ECC		220</div><div class='ctx'> #define SOC21_INTSRC_SDMA_TRAP		49</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c<br/>index 90ddd8371176..44009aa8216e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/export.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='hunk'>@@ -43,19 +44,32 @@ static const struct drm_driver amdgpu_xcp_driver = {</div><div class='ctx'> 	.minor = 0,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int pdev_num;</div><div class='add'>+static int8_t pdev_num;</div><div class='ctx'> static struct xcp_device *xcp_dev[MAX_XCP_PLATFORM_DEVICE];</div><div class='add'>+static DEFINE_MUTEX(xcp_mutex);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev)</div><div class='ctx'> {</div><div class='ctx'> 	struct platform_device *pdev;</div><div class='ctx'> 	struct xcp_device *pxcp_dev;</div><div class='del'>-	int ret;</div><div class='add'>+	char dev_name[20];</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;xcp_mutex);</div><div class='ctx'> </div><div class='ctx'> 	if (pdev_num &gt;= MAX_XCP_PLATFORM_DEVICE)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	pdev = platform_device_register_simple("amdgpu_xcp", pdev_num, NULL, 0);</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP_PLATFORM_DEVICE; i++) {</div><div class='add'>+		if (!xcp_dev[i])</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= MAX_XCP_PLATFORM_DEVICE)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", i);</div><div class='add'>+	pdev = platform_device_register_simple(dev_name, -1, NULL, 0);</div><div class='ctx'> 	if (IS_ERR(pdev))</div><div class='ctx'> 		return PTR_ERR(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -70,8 +84,8 @@ int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev)</div><div class='ctx'> 		goto out_devres;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	xcp_dev[pdev_num] = pxcp_dev;</div><div class='del'>-	xcp_dev[pdev_num]-&gt;pdev = pdev;</div><div class='add'>+	xcp_dev[i] = pxcp_dev;</div><div class='add'>+	xcp_dev[i]-&gt;pdev = pdev;</div><div class='ctx'> 	*ddev = &amp;pxcp_dev-&gt;drm;</div><div class='ctx'> 	pdev_num++;</div><div class='ctx'> </div><div class='hunk'>@@ -86,16 +100,43 @@ out_unregister:</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(amdgpu_xcp_drm_dev_alloc);</div><div class='ctx'> </div><div class='del'>-void amdgpu_xcp_drv_release(void)</div><div class='add'>+static void free_xcp_dev(int8_t index)</div><div class='ctx'> {</div><div class='del'>-	for (--pdev_num; pdev_num &gt;= 0; --pdev_num) {</div><div class='del'>-		struct platform_device *pdev = xcp_dev[pdev_num]-&gt;pdev;</div><div class='add'>+	if ((index &lt; MAX_XCP_PLATFORM_DEVICE) &amp;&amp; (xcp_dev[index])) {</div><div class='add'>+		struct platform_device *pdev = xcp_dev[index]-&gt;pdev;</div><div class='ctx'> </div><div class='ctx'> 		devres_release_group(&amp;pdev-&gt;dev, NULL);</div><div class='ctx'> 		platform_device_unregister(pdev);</div><div class='del'>-		xcp_dev[pdev_num] = NULL;</div><div class='add'>+</div><div class='add'>+		xcp_dev[index] = NULL;</div><div class='add'>+		pdev_num--;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_xcp_drm_dev_free(struct drm_device *ddev)</div><div class='add'>+{</div><div class='add'>+	int8_t i;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;xcp_mutex);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_XCP_PLATFORM_DEVICE; i++) {</div><div class='add'>+		if ((xcp_dev[i]) &amp;&amp; (&amp;xcp_dev[i]-&gt;drm == ddev)) {</div><div class='add'>+			free_xcp_dev(i);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(amdgpu_xcp_drm_dev_free);</div><div class='add'>+</div><div class='add'>+void amdgpu_xcp_drv_release(void)</div><div class='add'>+{</div><div class='add'>+	int8_t i;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;xcp_mutex);</div><div class='add'>+</div><div class='add'>+	for (i = 0; pdev_num &amp;&amp; i &lt; MAX_XCP_PLATFORM_DEVICE; i++) {</div><div class='add'>+		free_xcp_dev(i);</div><div class='ctx'> 	}</div><div class='del'>-	pdev_num = 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(amdgpu_xcp_drv_release);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h<br/>index c1c4b679bf95..580a1602c8e3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h</a></div><div class='hunk'>@@ -25,5 +25,6 @@</div><div class='ctx'> #define _AMDGPU_XCP_DRV_H_</div><div class='ctx'> </div><div class='ctx'> int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev);</div><div class='add'>+void amdgpu_xcp_drm_dev_free(struct drm_device *ddev);</div><div class='ctx'> void amdgpu_xcp_drv_release(void);</div><div class='ctx'> #endif /* _AMDGPU_XCP_DRV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig<br/>index 901d1961b739..abd3b6564373 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/Kconfig?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/Kconfig</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/Kconfig?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/Kconfig</a></div><div class='hunk'>@@ -1,24 +1,29 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='add'>+# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+</div><div class='ctx'> menu "Display Engine Configuration"</div><div class='ctx'> 	depends on DRM &amp;&amp; DRM_AMDGPU</div><div class='ctx'> </div><div class='ctx'> config DRM_AMD_DC</div><div class='ctx'> 	bool "AMD DC - Enable new display engine"</div><div class='ctx'> 	default y</div><div class='del'>-	depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64</div><div class='add'>+	depends on BROKEN || !CC_IS_CLANG || ARM64 || LOONGARCH || RISCV || SPARC64 || X86_64</div><div class='add'>+	select CEC_CORE</div><div class='add'>+	select CEC_NOTIFIER</div><div class='ctx'> 	select SND_HDA_COMPONENT if SND_HDA_CORE</div><div class='ctx'> 	# !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752</div><div class='del'>-	select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 &amp;&amp; ALTIVEC) || (ARM64 &amp;&amp; KERNEL_MODE_NEON &amp;&amp; !CC_IS_CLANG))</div><div class='add'>+	select DRM_AMD_DC_FP if ARCH_HAS_KERNEL_FPU_SUPPORT &amp;&amp; !(CC_IS_CLANG &amp;&amp; (ARM64 || LOONGARCH || RISCV))</div><div class='ctx'> 	help</div><div class='ctx'> 	  Choose this option if you want to use the new display engine</div><div class='ctx'> 	  support for AMDGPU. This adds required support for Vega and</div><div class='ctx'> 	  Raven ASICs.</div><div class='ctx'> </div><div class='del'>-	  calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64)</div><div class='del'>-	  architectures built with Clang (all released versions), whereby the stack</div><div class='del'>-	  frame gets blown up to well over 5k.  This would cause an immediate kernel</div><div class='del'>-	  panic on most architectures.  We'll revert this when the following bug report</div><div class='del'>-	  has been resolved: https://github.com/llvm/llvm-project/issues/41896.</div><div class='add'>+	  calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 ||</div><div class='add'>+	  ARM64 || LOONGARCH || RISCV) architectures built with Clang (all released</div><div class='add'>+	  versions), whereby the stack frame gets blown up to well over 5k.  This</div><div class='add'>+	  would cause an immediate kernel panic on most architectures.  We'll revert</div><div class='add'>+	  this when the following bug report has been resolved:</div><div class='add'>+	  https://github.com/llvm/llvm-project/issues/41896.</div><div class='ctx'> </div><div class='ctx'> config DRM_AMD_DC_FP</div><div class='ctx'> 	def_bool n</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile<br/>index 92a5c5efcf92..0084a8d55254 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/Makefile</a></div><div class='hunk'>@@ -33,6 +33,18 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hwss</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/resource</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dsc</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/optc</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dpp</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hubbub</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dccg</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hubp</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dio</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dwb</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hpo</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/mmhubbub</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/mpc</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/opp</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/pg</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/soc_and_ip_translator</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile<br/>index ab2a97e354da..8e949fe77312 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/Makefile</a></div><div class='hunk'>@@ -38,7 +38,9 @@ AMDGPUDM = \</div><div class='ctx'> 	amdgpu_dm_pp_smu.o \</div><div class='ctx'> 	amdgpu_dm_psr.o \</div><div class='ctx'> 	amdgpu_dm_replay.o \</div><div class='del'>-	amdgpu_dm_wb.o</div><div class='add'>+	amdgpu_dm_quirks.o \</div><div class='add'>+	amdgpu_dm_wb.o \</div><div class='add'>+	amdgpu_dm_colorop.o</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> AMDGPUDM += dc_fpu.o</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br/>index 2851719d7121..740711ac1037 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -39,13 +40,11 @@</div><div class='ctx'> #include "dc/dc_stat.h"</div><div class='ctx'> #include "dc/dc_state.h"</div><div class='ctx'> #include "amdgpu_dm_trace.h"</div><div class='del'>-#include "dpcd_defs.h"</div><div class='ctx'> #include "link/protocols/link_dpcd.h"</div><div class='ctx'> #include "link_service_types.h"</div><div class='ctx'> #include "link/protocols/link_dp_capability.h"</div><div class='ctx'> #include "link/protocols/link_ddc.h"</div><div class='ctx'> </div><div class='del'>-#include "vid.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_display.h"</div><div class='ctx'> #include "amdgpu_ucode.h"</div><div class='hunk'>@@ -56,7 +55,6 @@</div><div class='ctx'> #include "amdgpu_dm_hdcp.h"</div><div class='ctx'> #include &lt;drm/display/drm_hdcp_helper.h&gt;</div><div class='ctx'> #include "amdgpu_dm_wb.h"</div><div class='del'>-#include "amdgpu_pm.h"</div><div class='ctx'> #include "amdgpu_atombios.h"</div><div class='ctx'> </div><div class='ctx'> #include "amd_shared.h"</div><div class='hunk'>@@ -77,10 +75,12 @@</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/power_supply.h&gt;</div><div class='ctx'> #include &lt;linux/firmware.h&gt;</div><div class='ctx'> #include &lt;linux/component.h&gt;</div><div class='del'>-#include &lt;linux/dmi.h&gt;</div><div class='add'>+#include &lt;linux/sort.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_privacy_screen_consumer.h&gt;</div><div class='ctx'> #include &lt;drm/display/drm_dp_mst_helper.h&gt;</div><div class='ctx'> #include &lt;drm/display/drm_hdmi_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_atomic.h&gt;</div><div class='hunk'>@@ -91,26 +91,21 @@</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_eld.h&gt;</div><div class='add'>+#include &lt;drm/drm_utils.h&gt;</div><div class='ctx'> #include &lt;drm/drm_vblank.h&gt;</div><div class='ctx'> #include &lt;drm/drm_audio_component.h&gt;</div><div class='ctx'> #include &lt;drm/drm_gem_atomic_helper.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;media/cec-notifier.h&gt;</div><div class='ctx'> #include &lt;acpi/video.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn/dcn_1_0_offset.h"</div><div class='del'>-#include "dcn/dcn_1_0_sh_mask.h"</div><div class='del'>-#include "soc15_hw_ip.h"</div><div class='del'>-#include "soc15_common.h"</div><div class='del'>-#include "vega10_ip_offset.h"</div><div class='del'>-</div><div class='del'>-#include "gc/gc_11_0_0_offset.h"</div><div class='del'>-#include "gc/gc_11_0_0_sh_mask.h"</div><div class='del'>-</div><div class='ctx'> #include "modules/inc/mod_freesync.h"</div><div class='ctx'> #include "modules/power/power_helpers.h"</div><div class='ctx'> </div><div class='add'>+static_assert(AMDGPU_DMUB_NOTIFICATION_MAX == DMUB_NOTIFICATION_MAX, "AMDGPU_DMUB_NOTIFICATION_MAX mismatch");</div><div class='add'>+</div><div class='ctx'> #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);</div><div class='ctx'> #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"</div><div class='hunk'>@@ -148,6 +143,15 @@ MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);</div><div class='ctx'> #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"</div><div class='ctx'> MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);</div><div class='ctx'> </div><div class='add'>+#define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin"</div><div class='add'>+MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB);</div><div class='add'>+</div><div class='add'>+#define FIRMWARE_DCN_36_DMUB "amdgpu/dcn_3_6_dmcub.bin"</div><div class='add'>+MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB);</div><div class='add'>+</div><div class='add'>+#define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin"</div><div class='add'>+MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB);</div><div class='add'>+</div><div class='ctx'> /* Number of bytes in PSP header for firmware. */</div><div class='ctx'> #define PSP_HEADER_BYTES 0x100</div><div class='ctx'> </div><div class='hunk'>@@ -168,6 +172,9 @@ MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);</div><div class='ctx'> static int amdgpu_dm_init(struct amdgpu_device *adev);</div><div class='ctx'> static void amdgpu_dm_fini(struct amdgpu_device *adev);</div><div class='ctx'> static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);</div><div class='add'>+static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state);</div><div class='add'>+static struct amdgpu_i2c_adapter *</div><div class='add'>+create_i2c(struct ddc_service *ddc_service, bool oem);</div><div class='ctx'> </div><div class='ctx'> static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)</div><div class='ctx'> {</div><div class='hunk'>@@ -226,6 +233,7 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);</div><div class='ctx'> </div><div class='add'>+static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state);</div><div class='ctx'> static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='hunk'>@@ -234,6 +242,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);</div><div class='ctx'> static void handle_hpd_rx_irq(void *param);</div><div class='ctx'> </div><div class='add'>+static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,</div><div class='add'>+					 int bl_idx,</div><div class='add'>+					 u32 user_brightness);</div><div class='add'>+</div><div class='ctx'> static bool</div><div class='ctx'> is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,</div><div class='ctx'> 				 struct drm_crtc_state *new_crtc_state);</div><div class='hunk'>@@ -260,7 +272,7 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)</div><div class='ctx'> 	acrtc = adev-&gt;mode_info.crtcs[crtc];</div><div class='ctx'> </div><div class='ctx'> 	if (!acrtc-&gt;dm_irq_params.stream) {</div><div class='del'>-		DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",</div><div class='add'>+		drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n",</div><div class='ctx'> 			  crtc);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -271,7 +283,7 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)</div><div class='ctx'> static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,</div><div class='ctx'> 				  u32 *vbl, u32 *position)</div><div class='ctx'> {</div><div class='del'>-	u32 v_blank_start, v_blank_end, h_position, v_position;</div><div class='add'>+	u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0;</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = NULL;</div><div class='ctx'> 	struct dc *dc = adev-&gt;dm.dc;</div><div class='ctx'> </div><div class='hunk'>@@ -281,7 +293,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,</div><div class='ctx'> 	acrtc = adev-&gt;mode_info.crtcs[crtc];</div><div class='ctx'> </div><div class='ctx'> 	if (!acrtc-&gt;dm_irq_params.stream) {</div><div class='del'>-		DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",</div><div class='add'>+		drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n",</div><div class='ctx'> 			  crtc);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -305,24 +317,24 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dm_is_idle(void *handle)</div><div class='add'>+static bool dm_is_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* XXX todo */</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_wait_for_idle(void *handle)</div><div class='add'>+static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* XXX todo */</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dm_check_soft_reset(void *handle)</div><div class='add'>+static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_soft_reset(void *handle)</div><div class='add'>+static int dm_soft_reset(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='ctx'> 	/* XXX todo */</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -352,6 +364,8 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev,</div><div class='ctx'> static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,</div><div class='ctx'> 					      struct dm_crtc_state *new_state)</div><div class='ctx'> {</div><div class='add'>+	if (new_state-&gt;stream-&gt;adjust.timing_adjust_pending)</div><div class='add'>+		return true;</div><div class='ctx'> 	if (new_state-&gt;freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)</div><div class='ctx'> 		return true;</div><div class='ctx'> 	else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))</div><div class='hunk'>@@ -360,13 +374,18 @@ static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,</div><div class='ctx'> 		return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,</div><div class='del'>-					int planes_count)</div><div class='add'>+/*</div><div class='add'>+ * DC will program planes with their z-order determined by their ordering</div><div class='add'>+ * in the dc_surface_updates array. This comparator is used to sort them</div><div class='add'>+ * by descending zpos.</div><div class='add'>+ */</div><div class='add'>+static int dm_plane_layer_index_cmp(const void *a, const void *b)</div><div class='ctx'> {</div><div class='del'>-	int i, j;</div><div class='add'>+	const struct dc_surface_update *sa = (struct dc_surface_update *)a;</div><div class='add'>+	const struct dc_surface_update *sb = (struct dc_surface_update *)b;</div><div class='ctx'> </div><div class='del'>-	for (i = 0, j = planes_count - 1; i &lt; j; i++, j--)</div><div class='del'>-		swap(array_of_surface_update[i], array_of_surface_update[j]);</div><div class='add'>+	/* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */</div><div class='add'>+	return sb-&gt;surface-&gt;layer_index - sa-&gt;surface-&gt;layer_index;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -393,13 +412,13 @@ static inline bool update_planes_and_stream_adapter(struct dc *dc,</div><div class='ctx'> 						    struct dc_stream_update *stream_update,</div><div class='ctx'> 						    struct dc_surface_update *array_of_surface_update)</div><div class='ctx'> {</div><div class='del'>-	reverse_planes_order(array_of_surface_update, planes_count);</div><div class='add'>+	sort(array_of_surface_update, planes_count,</div><div class='add'>+	     sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Previous frame finished and HW is ready for optimization.</div><div class='ctx'> 	 */</div><div class='del'>-	if (update_type == UPDATE_TYPE_FAST)</div><div class='del'>-		dc_post_update_surfaces_to_stream(dc);</div><div class='add'>+	dc_post_update_surfaces_to_stream(dc);</div><div class='ctx'> </div><div class='ctx'> 	return dc_update_planes_and_stream(dc,</div><div class='ctx'> 					   array_of_surface_update,</div><div class='hunk'>@@ -512,6 +531,50 @@ static void dm_pflip_high_irq(void *interrupt_params)</div><div class='ctx'> 		      amdgpu_crtc-&gt;crtc_id, amdgpu_crtc, vrr_active, (int)!e);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dm_handle_vmin_vmax_update(struct work_struct *offload_work)</div><div class='add'>+{</div><div class='add'>+	struct vupdate_offload_work *work = container_of(offload_work, struct vupdate_offload_work, work);</div><div class='add'>+	struct amdgpu_device *adev = work-&gt;adev;</div><div class='add'>+	struct dc_stream_state *stream = work-&gt;stream;</div><div class='add'>+	struct dc_crtc_timing_adjust *adjust = work-&gt;adjust;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='add'>+	dc_stream_adjust_vmin_vmax(adev-&gt;dm.dc, stream, adjust);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='add'>+</div><div class='add'>+	dc_stream_release(stream);</div><div class='add'>+	kfree(work-&gt;adjust);</div><div class='add'>+	kfree(work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void schedule_dc_vmin_vmax(struct amdgpu_device *adev,</div><div class='add'>+	struct dc_stream_state *stream,</div><div class='add'>+	struct dc_crtc_timing_adjust *adjust)</div><div class='add'>+{</div><div class='add'>+	struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_NOWAIT);</div><div class='add'>+	if (!offload_work) {</div><div class='add'>+		drm_dbg_driver(adev_to_drm(adev), "Failed to allocate vupdate_offload_work\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_NOWAIT);</div><div class='add'>+	if (!adjust_copy) {</div><div class='add'>+		drm_dbg_driver(adev_to_drm(adev), "Failed to allocate adjust_copy\n");</div><div class='add'>+		kfree(offload_work);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_stream_retain(stream);</div><div class='add'>+	memcpy(adjust_copy, adjust, sizeof(*adjust_copy));</div><div class='add'>+</div><div class='add'>+	INIT_WORK(&amp;offload_work-&gt;work, dm_handle_vmin_vmax_update);</div><div class='add'>+	offload_work-&gt;adev = adev;</div><div class='add'>+	offload_work-&gt;stream = stream;</div><div class='add'>+	offload_work-&gt;adjust = adjust_copy;</div><div class='add'>+</div><div class='add'>+	queue_work(system_wq, &amp;offload_work-&gt;work);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dm_vupdate_high_irq(void *interrupt_params)</div><div class='ctx'> {</div><div class='ctx'> 	struct common_irq_params *irq_params = interrupt_params;</div><div class='hunk'>@@ -528,7 +591,7 @@ static void dm_vupdate_high_irq(void *interrupt_params)</div><div class='ctx'> 	if (acrtc) {</div><div class='ctx'> 		vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);</div><div class='ctx'> 		drm_dev = acrtc-&gt;base.dev;</div><div class='del'>-		vblank = &amp;drm_dev-&gt;vblank[acrtc-&gt;base.index];</div><div class='add'>+		vblank = drm_crtc_vblank_crtc(&amp;acrtc-&gt;base);</div><div class='ctx'> 		previous_timestamp = atomic64_read(&amp;irq_params-&gt;previous_timestamp);</div><div class='ctx'> 		frame_duration_ns = vblank-&gt;time - previous_timestamp;</div><div class='ctx'> </div><div class='hunk'>@@ -549,22 +612,27 @@ static void dm_vupdate_high_irq(void *interrupt_params)</div><div class='ctx'> 		 * page-flip completion events that have been queued to us</div><div class='ctx'> 		 * if a pageflip happened inside front-porch.</div><div class='ctx'> 		 */</div><div class='del'>-		if (vrr_active) {</div><div class='add'>+		if (vrr_active &amp;&amp; acrtc-&gt;dm_irq_params.stream) {</div><div class='add'>+			bool replay_en = acrtc-&gt;dm_irq_params.stream-&gt;link-&gt;replay_settings.replay_feature_enabled;</div><div class='add'>+			bool psr_en = acrtc-&gt;dm_irq_params.stream-&gt;link-&gt;psr_settings.psr_feature_enabled;</div><div class='add'>+			bool fs_active_var_en = acrtc-&gt;dm_irq_params.freesync_config.state</div><div class='add'>+				== VRR_STATE_ACTIVE_VARIABLE;</div><div class='add'>+</div><div class='ctx'> 			amdgpu_dm_crtc_handle_vblank(acrtc);</div><div class='ctx'> </div><div class='ctx'> 			/* BTR processing for pre-DCE12 ASICs */</div><div class='del'>-			if (acrtc-&gt;dm_irq_params.stream &amp;&amp;</div><div class='del'>-			    adev-&gt;family &lt; AMDGPU_FAMILY_AI) {</div><div class='add'>+			if (adev-&gt;family &lt; AMDGPU_FAMILY_AI) {</div><div class='ctx'> 				spin_lock_irqsave(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='ctx'> 				mod_freesync_handle_v_update(</div><div class='ctx'> 				    adev-&gt;dm.freesync_module,</div><div class='ctx'> 				    acrtc-&gt;dm_irq_params.stream,</div><div class='ctx'> 				    &amp;acrtc-&gt;dm_irq_params.vrr_params);</div><div class='ctx'> </div><div class='del'>-				dc_stream_adjust_vmin_vmax(</div><div class='del'>-				    adev-&gt;dm.dc,</div><div class='del'>-				    acrtc-&gt;dm_irq_params.stream,</div><div class='del'>-				    &amp;acrtc-&gt;dm_irq_params.vrr_params.adjust);</div><div class='add'>+				if (fs_active_var_en || (!fs_active_var_en &amp;&amp; !replay_en &amp;&amp; !psr_en)) {</div><div class='add'>+					schedule_dc_vmin_vmax(adev,</div><div class='add'>+						acrtc-&gt;dm_irq_params.stream,</div><div class='add'>+						&amp;acrtc-&gt;dm_irq_params.vrr_params.adjust);</div><div class='add'>+				}</div><div class='ctx'> 				spin_unlock_irqrestore(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -591,12 +659,14 @@ static void dm_crtc_high_irq(void *interrupt_params)</div><div class='ctx'> 	if (!acrtc)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (acrtc-&gt;wb_pending) {</div><div class='del'>-		if (acrtc-&gt;wb_conn) {</div><div class='del'>-			spin_lock_irqsave(&amp;acrtc-&gt;wb_conn-&gt;job_lock, flags);</div><div class='add'>+	if (acrtc-&gt;wb_conn) {</div><div class='add'>+		spin_lock_irqsave(&amp;acrtc-&gt;wb_conn-&gt;job_lock, flags);</div><div class='add'>+</div><div class='add'>+		if (acrtc-&gt;wb_pending) {</div><div class='ctx'> 			job = list_first_entry_or_null(&amp;acrtc-&gt;wb_conn-&gt;job_queue,</div><div class='ctx'> 						       struct drm_writeback_job,</div><div class='ctx'> 						       list_entry);</div><div class='add'>+			acrtc-&gt;wb_pending = false;</div><div class='ctx'> 			spin_unlock_irqrestore(&amp;acrtc-&gt;wb_conn-&gt;job_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 			if (job) {</div><div class='hunk'>@@ -614,8 +684,7 @@ static void dm_crtc_high_irq(void *interrupt_params)</div><div class='ctx'> 							       acrtc-&gt;dm_irq_params.stream, 0);</div><div class='ctx'> 			}</div><div class='ctx'> 		} else</div><div class='del'>-			DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);</div><div class='del'>-		acrtc-&gt;wb_pending = false;</div><div class='add'>+			spin_unlock_irqrestore(&amp;acrtc-&gt;wb_conn-&gt;job_lock, flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);</div><div class='hunk'>@@ -646,15 +715,20 @@ static void dm_crtc_high_irq(void *interrupt_params)</div><div class='ctx'> 	spin_lock_irqsave(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	if (acrtc-&gt;dm_irq_params.stream &amp;&amp;</div><div class='del'>-	    acrtc-&gt;dm_irq_params.vrr_params.supported &amp;&amp;</div><div class='del'>-	    acrtc-&gt;dm_irq_params.freesync_config.state ==</div><div class='del'>-		    VRR_STATE_ACTIVE_VARIABLE) {</div><div class='add'>+		acrtc-&gt;dm_irq_params.vrr_params.supported) {</div><div class='add'>+		bool replay_en = acrtc-&gt;dm_irq_params.stream-&gt;link-&gt;replay_settings.replay_feature_enabled;</div><div class='add'>+		bool psr_en = acrtc-&gt;dm_irq_params.stream-&gt;link-&gt;psr_settings.psr_feature_enabled;</div><div class='add'>+		bool fs_active_var_en = acrtc-&gt;dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;</div><div class='add'>+</div><div class='ctx'> 		mod_freesync_handle_v_update(adev-&gt;dm.freesync_module,</div><div class='ctx'> 					     acrtc-&gt;dm_irq_params.stream,</div><div class='ctx'> 					     &amp;acrtc-&gt;dm_irq_params.vrr_params);</div><div class='ctx'> </div><div class='del'>-		dc_stream_adjust_vmin_vmax(adev-&gt;dm.dc, acrtc-&gt;dm_irq_params.stream,</div><div class='del'>-					   &amp;acrtc-&gt;dm_irq_params.vrr_params.adjust);</div><div class='add'>+		/* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */</div><div class='add'>+		if (fs_active_var_en || (!fs_active_var_en &amp;&amp; !replay_en &amp;&amp; !psr_en)) {</div><div class='add'>+			schedule_dc_vmin_vmax(adev, acrtc-&gt;dm_irq_params.stream,</div><div class='add'>+					&amp;acrtc-&gt;dm_irq_params.vrr_params.adjust);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -722,6 +796,29 @@ static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,</div><div class='ctx'> 		complete(&amp;adev-&gt;dm.dmub_aux_transfer_done);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dmub_aux_fused_io_callback(struct amdgpu_device *adev,</div><div class='add'>+					struct dmub_notification *notify)</div><div class='add'>+{</div><div class='add'>+	if (!adev || !notify) {</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	const struct dmub_cmd_fused_request *req = &amp;notify-&gt;fused_request;</div><div class='add'>+	const uint8_t ddc_line = req-&gt;u.aux.ddc_line;</div><div class='add'>+</div><div class='add'>+	if (ddc_line &gt;= ARRAY_SIZE(adev-&gt;dm.fused_io)) {</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	struct fused_io_sync *sync = &amp;adev-&gt;dm.fused_io[ddc_line];</div><div class='add'>+</div><div class='add'>+	static_assert(sizeof(*req) &lt;= sizeof(sync-&gt;reply_data), "Size mismatch");</div><div class='add'>+	memcpy(sync-&gt;reply_data, req, sizeof(*req));</div><div class='add'>+	complete(&amp;sync-&gt;replied);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * dmub_hpd_callback - DMUB HPD interrupt processing callback.</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='hunk'>@@ -745,12 +842,18 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (notify == NULL) {</div><div class='del'>-		DRM_ERROR("DMUB HPD callback notification was NULL");</div><div class='add'>+		drm_err(adev_to_drm(adev), "DMUB HPD callback notification was NULL");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (notify-&gt;link_index &gt; adev-&gt;dm.dc-&gt;link_count) {</div><div class='del'>-		DRM_ERROR("DMUB HPD index (%u)is abnormal", notify-&gt;link_index);</div><div class='add'>+		drm_err(adev_to_drm(adev), "DMUB HPD index (%u)is abnormal", notify-&gt;link_index);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */</div><div class='add'>+	if (notify-&gt;type == DMUB_NOTIFICATION_HPD &amp;&amp; adev-&gt;in_suspend) {</div><div class='add'>+		drm_info(adev_to_drm(adev), "Skip DMUB HPD IRQ callback in suspend/resume\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -767,11 +870,11 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (link &amp;&amp; aconnector-&gt;dc_link == link) {</div><div class='ctx'> 			if (notify-&gt;type == DMUB_NOTIFICATION_HPD)</div><div class='del'>-				DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);</div><div class='add'>+				drm_info(adev_to_drm(adev), "DMUB HPD IRQ callback: link_index=%u\n", link_index);</div><div class='ctx'> 			else if (notify-&gt;type == DMUB_NOTIFICATION_HPD_IRQ)</div><div class='del'>-				DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);</div><div class='add'>+				drm_info(adev_to_drm(adev), "DMUB HPD RX IRQ callback: link_index=%u\n", link_index);</div><div class='ctx'> 			else</div><div class='del'>-				DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",</div><div class='add'>+				drm_warn(adev_to_drm(adev), "DMUB Unknown HPD callback type %d, link_index=%u\n",</div><div class='ctx'> 						notify-&gt;type, link_index);</div><div class='ctx'> </div><div class='ctx'> 			hpd_aconnector = aconnector;</div><div class='hunk'>@@ -781,14 +884,31 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,</div><div class='ctx'> 	drm_connector_list_iter_end(&amp;iter);</div><div class='ctx'> </div><div class='ctx'> 	if (hpd_aconnector) {</div><div class='del'>-		if (notify-&gt;type == DMUB_NOTIFICATION_HPD)</div><div class='add'>+		if (notify-&gt;type == DMUB_NOTIFICATION_HPD) {</div><div class='add'>+			if (hpd_aconnector-&gt;dc_link-&gt;hpd_status == (notify-&gt;hpd_status == DP_HPD_PLUG))</div><div class='add'>+				drm_warn(adev_to_drm(adev), "DMUB reported hpd status unchanged. link_index=%u\n", link_index);</div><div class='ctx'> 			handle_hpd_irq_helper(hpd_aconnector);</div><div class='del'>-		else if (notify-&gt;type == DMUB_NOTIFICATION_HPD_IRQ)</div><div class='add'>+		} else if (notify-&gt;type == DMUB_NOTIFICATION_HPD_IRQ) {</div><div class='ctx'> 			handle_hpd_rx_irq(hpd_aconnector);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * dmub_hpd_sense_callback - DMUB HPD sense processing callback.</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @notify: dmub notification structure</div><div class='add'>+ *</div><div class='add'>+ * HPD sense changes can occur during low power states and need to be</div><div class='add'>+ * notified from firmware to driver.</div><div class='add'>+ */</div><div class='add'>+static void dmub_hpd_sense_callback(struct amdgpu_device *adev,</div><div class='add'>+			      struct dmub_notification *notify)</div><div class='add'>+{</div><div class='add'>+	drm_dbg_driver(adev_to_drm(adev), "DMUB HPD SENSE callback.\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * register_dmub_notify_callback - Sets callback for DMUB notify</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='ctx'>  * @type: Type of dmub notification</div><div class='hunk'>@@ -821,7 +941,7 @@ static void dm_handle_hpd_work(struct work_struct *work)</div><div class='ctx'> 	dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);</div><div class='ctx'> </div><div class='ctx'> 	if (!dmub_hpd_wrk-&gt;dmub_notify) {</div><div class='del'>-		DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");</div><div class='add'>+		drm_err(adev_to_drm(dmub_hpd_wrk-&gt;adev), "dmub_hpd_wrk dmub_notify is NULL");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -835,6 +955,30 @@ static void dm_handle_hpd_work(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const char *dmub_notification_type_str(enum dmub_notification_type e)</div><div class='add'>+{</div><div class='add'>+	switch (e) {</div><div class='add'>+	case DMUB_NOTIFICATION_NO_DATA:</div><div class='add'>+		return "NO_DATA";</div><div class='add'>+	case DMUB_NOTIFICATION_AUX_REPLY:</div><div class='add'>+		return "AUX_REPLY";</div><div class='add'>+	case DMUB_NOTIFICATION_HPD:</div><div class='add'>+		return "HPD";</div><div class='add'>+	case DMUB_NOTIFICATION_HPD_IRQ:</div><div class='add'>+		return "HPD_IRQ";</div><div class='add'>+	case DMUB_NOTIFICATION_SET_CONFIG_REPLY:</div><div class='add'>+		return "SET_CONFIG_REPLY";</div><div class='add'>+	case DMUB_NOTIFICATION_DPIA_NOTIFICATION:</div><div class='add'>+		return "DPIA_NOTIFICATION";</div><div class='add'>+	case DMUB_NOTIFICATION_HPD_SENSE_NOTIFY:</div><div class='add'>+		return "HPD_SENSE_NOTIFY";</div><div class='add'>+	case DMUB_NOTIFICATION_FUSED_IO:</div><div class='add'>+		return "FUSED_IO";</div><div class='add'>+	default:</div><div class='add'>+		return "&lt;unknown&gt;";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #define DMUB_TRACE_MAX_READ 64</div><div class='ctx'> /**</div><div class='ctx'>  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt</div><div class='hunk'>@@ -845,14 +989,30 @@ static void dm_handle_hpd_work(struct work_struct *work)</div><div class='ctx'>  */</div><div class='ctx'> static void dm_dmub_outbox1_low_irq(void *interrupt_params)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_notification notify;</div><div class='add'>+	struct dmub_notification notify = {0};</div><div class='ctx'> 	struct common_irq_params *irq_params = interrupt_params;</div><div class='ctx'> 	struct amdgpu_device *adev = irq_params-&gt;adev;</div><div class='ctx'> 	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='ctx'> 	struct dmcub_trace_buf_entry entry = { 0 };</div><div class='ctx'> 	u32 count = 0;</div><div class='ctx'> 	struct dmub_hpd_work *dmub_hpd_wrk;</div><div class='del'>-	struct dc_link *plink = NULL;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		if (dc_dmub_srv_get_dmub_outbox0_msg(dm-&gt;dc, &amp;entry)) {</div><div class='add'>+			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,</div><div class='add'>+							entry.param0, entry.param1);</div><div class='add'>+</div><div class='add'>+			drm_dbg_driver(adev_to_drm(adev), "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",</div><div class='add'>+				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);</div><div class='add'>+		} else</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		count++;</div><div class='add'>+</div><div class='add'>+	} while (count &lt;= DMUB_TRACE_MAX_READ);</div><div class='add'>+</div><div class='add'>+	if (count &gt; DMUB_TRACE_MAX_READ)</div><div class='add'>+		drm_dbg_driver(adev_to_drm(adev), "Warning : count &gt; DMUB_TRACE_MAX_READ");</div><div class='ctx'> </div><div class='ctx'> 	if (dc_enable_dmub_notifications(adev-&gt;dm.dc) &amp;&amp;</div><div class='ctx'> 		irq_params-&gt;irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {</div><div class='hunk'>@@ -860,75 +1020,51 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)</div><div class='ctx'> 		do {</div><div class='ctx'> 			dc_stat_get_dmub_notification(adev-&gt;dm.dc, &amp;notify);</div><div class='ctx'> 			if (notify.type &gt;= ARRAY_SIZE(dm-&gt;dmub_thread_offload)) {</div><div class='del'>-				DRM_ERROR("DM: notify type %d invalid!", notify.type);</div><div class='add'>+				drm_err(adev_to_drm(adev), "DM: notify type %d invalid!", notify.type);</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> 			if (!dm-&gt;dmub_callback[notify.type]) {</div><div class='del'>-				DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);</div><div class='add'>+				drm_warn(adev_to_drm(adev), "DMUB notification skipped due to no handler: type=%s\n",</div><div class='add'>+					dmub_notification_type_str(notify.type));</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> 			if (dm-&gt;dmub_thread_offload[notify.type] == true) {</div><div class='ctx'> 				dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);</div><div class='ctx'> 				if (!dmub_hpd_wrk) {</div><div class='del'>-					DRM_ERROR("Failed to allocate dmub_hpd_wrk");</div><div class='add'>+					drm_err(adev_to_drm(adev), "Failed to allocate dmub_hpd_wrk");</div><div class='ctx'> 					return;</div><div class='ctx'> 				}</div><div class='ctx'> 				dmub_hpd_wrk-&gt;dmub_notify = kmemdup(&amp;notify, sizeof(struct dmub_notification),</div><div class='ctx'> 								    GFP_ATOMIC);</div><div class='ctx'> 				if (!dmub_hpd_wrk-&gt;dmub_notify) {</div><div class='ctx'> 					kfree(dmub_hpd_wrk);</div><div class='del'>-					DRM_ERROR("Failed to allocate dmub_hpd_wrk-&gt;dmub_notify");</div><div class='add'>+					drm_err(adev_to_drm(adev), "Failed to allocate dmub_hpd_wrk-&gt;dmub_notify");</div><div class='ctx'> 					return;</div><div class='ctx'> 				}</div><div class='ctx'> 				INIT_WORK(&amp;dmub_hpd_wrk-&gt;handle_hpd_work, dm_handle_hpd_work);</div><div class='ctx'> 				dmub_hpd_wrk-&gt;adev = adev;</div><div class='del'>-				if (notify.type == DMUB_NOTIFICATION_HPD) {</div><div class='del'>-					plink = adev-&gt;dm.dc-&gt;links[notify.link_index];</div><div class='del'>-					if (plink) {</div><div class='del'>-						plink-&gt;hpd_status =</div><div class='del'>-							notify.hpd_status == DP_HPD_PLUG;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='ctx'> 				queue_work(adev-&gt;dm.delayed_hpd_wq, &amp;dmub_hpd_wrk-&gt;handle_hpd_work);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				dm-&gt;dmub_callback[notify.type](adev, &amp;notify);</div><div class='ctx'> 			}</div><div class='ctx'> 		} while (notify.pending_notification);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-		if (dc_dmub_srv_get_dmub_outbox0_msg(dm-&gt;dc, &amp;entry)) {</div><div class='del'>-			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,</div><div class='del'>-							entry.param0, entry.param1);</div><div class='del'>-</div><div class='del'>-			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",</div><div class='del'>-				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);</div><div class='del'>-		} else</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		count++;</div><div class='del'>-</div><div class='del'>-	} while (count &lt;= DMUB_TRACE_MAX_READ);</div><div class='del'>-</div><div class='del'>-	if (count &gt; DMUB_TRACE_MAX_READ)</div><div class='del'>-		DRM_DEBUG_DRIVER("Warning : count &gt; DMUB_TRACE_MAX_READ");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_set_clockgating_state(void *handle,</div><div class='add'>+static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 		  enum amd_clockgating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_set_powergating_state(void *handle,</div><div class='add'>+static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 		  enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Prototypes of private functions */</div><div class='del'>-static int dm_early_init(void *handle);</div><div class='add'>+static int dm_early_init(struct amdgpu_ip_block *ip_block);</div><div class='ctx'> </div><div class='ctx'> /* Allocate memory for FBC compressed data  */</div><div class='ctx'> static void amdgpu_dm_fbc_init(struct drm_connector *connector)</div><div class='hunk'>@@ -950,8 +1086,8 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(mode, &amp;connector-&gt;modes, head) {</div><div class='del'>-		if (max_size &lt; mode-&gt;htotal * mode-&gt;vtotal)</div><div class='del'>-			max_size = mode-&gt;htotal * mode-&gt;vtotal;</div><div class='add'>+		if (max_size &lt; (unsigned long) mode-&gt;htotal * mode-&gt;vtotal)</div><div class='add'>+			max_size = (unsigned long) mode-&gt;htotal * mode-&gt;vtotal;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (max_size) {</div><div class='hunk'>@@ -960,10 +1096,10 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)</div><div class='ctx'> 			    &amp;compressor-&gt;gpu_addr, &amp;compressor-&gt;cpu_addr);</div><div class='ctx'> </div><div class='ctx'> 		if (r)</div><div class='del'>-			DRM_ERROR("DM: Failed to initialize FBC\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "DM: Failed to initialize FBC\n");</div><div class='ctx'> 		else {</div><div class='ctx'> 			adev-&gt;dm.dc-&gt;ctx-&gt;fbc_gpu_addr = compressor-&gt;gpu_addr;</div><div class='del'>-			DRM_INFO("DM: FBC alloc %lu\n", max_size*4);</div><div class='add'>+			drm_info(adev_to_drm(adev), "DM: FBC alloc %lu\n", max_size*4);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='hunk'>@@ -996,8 +1132,10 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		*enabled = true;</div><div class='add'>+		mutex_lock(&amp;connector-&gt;eld_mutex);</div><div class='ctx'> 		ret = drm_eld_size(connector-&gt;eld);</div><div class='ctx'> 		memcpy(buf, connector-&gt;eld, min(max_bytes, ret));</div><div class='add'>+		mutex_unlock(&amp;connector-&gt;eld_mutex);</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1126,13 +1264,13 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!fb_info) {</div><div class='del'>-		DRM_ERROR("No framebuffer info for DMUB service.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "No framebuffer info for DMUB service.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!dmub_fw) {</div><div class='ctx'> 		/* Firmware required for DMUB support. */</div><div class='del'>-		DRM_ERROR("No firmware provided for DMUB.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "No firmware provided for DMUB.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1142,19 +1280,19 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	status = dmub_srv_has_hw_support(dmub_srv, &amp;has_hw_support);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DRM_ERROR("Error checking HW support for DMUB: %d\n", status);</div><div class='add'>+		drm_err(adev_to_drm(adev), "Error checking HW support for DMUB: %d\n", status);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!has_hw_support) {</div><div class='del'>-		DRM_INFO("DMUB unsupported on ASIC\n");</div><div class='add'>+		drm_info(adev_to_drm(adev), "DMUB unsupported on ASIC\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Reset DMCUB if it was previously running - before we overwrite its memory. */</div><div class='ctx'> 	status = dmub_srv_hw_reset(dmub_srv);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK)</div><div class='del'>-		DRM_WARN("Error resetting DMUB HW: %d\n", status);</div><div class='add'>+		drm_warn(adev_to_drm(adev), "Error resetting DMUB HW: %d\n", status);</div><div class='ctx'> </div><div class='ctx'> 	hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw-&gt;data;</div><div class='ctx'> </div><div class='hunk'>@@ -1200,6 +1338,9 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	memset(fb_info-&gt;fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,</div><div class='ctx'> 	       fb_info-&gt;fb[DMUB_WINDOW_6_FW_STATE].size);</div><div class='ctx'> </div><div class='add'>+	memset(fb_info-&gt;fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0,</div><div class='add'>+	       fb_info-&gt;fb[DMUB_WINDOW_SHARED_STATE].size);</div><div class='add'>+</div><div class='ctx'> 	/* Initialize hardware. */</div><div class='ctx'> 	memset(&amp;hw_params, 0, sizeof(hw_params));</div><div class='ctx'> 	hw_params.fb_base = adev-&gt;gmc.fb_start;</div><div class='hunk'>@@ -1220,6 +1361,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(3, 1, 4):</div><div class='ctx'> 	case IP_VERSION(3, 5, 0):</div><div class='ctx'> 	case IP_VERSION(3, 5, 1):</div><div class='add'>+	case IP_VERSION(3, 6, 0):</div><div class='add'>+	case IP_VERSION(4, 0, 1):</div><div class='ctx'> 		hw_params.dpia_supported = true;</div><div class='ctx'> 		hw_params.disable_dpia = adev-&gt;dm.dc-&gt;debug.dpia_debug.bits.disable_dpia;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1227,16 +1370,27 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(3, 5, 0):</div><div class='add'>+	case IP_VERSION(3, 5, 1):</div><div class='add'>+	case IP_VERSION(3, 6, 0):</div><div class='add'>+		hw_params.ips_sequential_ono = adev-&gt;external_rev_id &gt; 0x10;</div><div class='add'>+		hw_params.lower_hbr3_phy_ssc = true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	status = dmub_srv_hw_init(dmub_srv, &amp;hw_params);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DRM_ERROR("Error initializing DMUB HW: %d\n", status);</div><div class='add'>+		drm_err(adev_to_drm(adev), "Error initializing DMUB HW: %d\n", status);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for firmware load to finish. */</div><div class='ctx'> 	status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK)</div><div class='del'>-		DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);</div><div class='add'>+		drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status);</div><div class='ctx'> </div><div class='ctx'> 	/* Init DMCU and ABM if available. */</div><div class='ctx'> 	if (dmcu &amp;&amp; abm) {</div><div class='hunk'>@@ -1247,13 +1401,36 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!adev-&gt;dm.dc-&gt;ctx-&gt;dmub_srv)</div><div class='ctx'> 		adev-&gt;dm.dc-&gt;ctx-&gt;dmub_srv = dc_dmub_srv_create(adev-&gt;dm.dc, dmub_srv);</div><div class='ctx'> 	if (!adev-&gt;dm.dc-&gt;ctx-&gt;dmub_srv) {</div><div class='del'>-		DRM_ERROR("Couldn't allocate DC DMUB server!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Couldn't allocate DC DMUB server!\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",</div><div class='add'>+	drm_info(adev_to_drm(adev), "DMUB hardware initialized: version=0x%08X\n",</div><div class='ctx'> 		 adev-&gt;dm.dmcub_fw_version);</div><div class='ctx'> </div><div class='add'>+	/* Keeping sanity checks off if</div><div class='add'>+	 * DCN31 &gt;= 4.0.59.0</div><div class='add'>+	 * DCN314 &gt;= 8.0.16.0</div><div class='add'>+	 * Otherwise, turn on sanity checks</div><div class='add'>+	 */</div><div class='add'>+	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(3, 1, 2):</div><div class='add'>+	case IP_VERSION(3, 1, 3):</div><div class='add'>+		if (adev-&gt;dm.dmcub_fw_version &amp;&amp;</div><div class='add'>+			adev-&gt;dm.dmcub_fw_version &gt;= DMUB_FW_VERSION(4, 0, 0) &amp;&amp;</div><div class='add'>+			adev-&gt;dm.dmcub_fw_version &lt; DMUB_FW_VERSION(4, 0, 59))</div><div class='add'>+				adev-&gt;dm.dc-&gt;debug.sanity_checks = true;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(3, 1, 4):</div><div class='add'>+		if (adev-&gt;dm.dmcub_fw_version &amp;&amp;</div><div class='add'>+			adev-&gt;dm.dmcub_fw_version &gt;= DMUB_FW_VERSION(4, 0, 0) &amp;&amp;</div><div class='add'>+			adev-&gt;dm.dmcub_fw_version &lt; DMUB_FW_VERSION(8, 0, 16))</div><div class='add'>+				adev-&gt;dm.dc-&gt;debug.sanity_checks = true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1262,6 +1439,7 @@ static void dm_dmub_hw_resume(struct amdgpu_device *adev)</div><div class='ctx'> 	struct dmub_srv *dmub_srv = adev-&gt;dm.dmub_srv;</div><div class='ctx'> 	enum dmub_status status;</div><div class='ctx'> 	bool init;</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!dmub_srv) {</div><div class='ctx'> 		/* DMUB isn't supported on the ASIC. */</div><div class='hunk'>@@ -1270,16 +1448,18 @@ static void dm_dmub_hw_resume(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	status = dmub_srv_is_hw_init(dmub_srv, &amp;init);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK)</div><div class='del'>-		DRM_WARN("DMUB hardware init check failed: %d\n", status);</div><div class='add'>+		drm_warn(adev_to_drm(adev), "DMUB hardware init check failed: %d\n", status);</div><div class='ctx'> </div><div class='ctx'> 	if (status == DMUB_STATUS_OK &amp;&amp; init) {</div><div class='ctx'> 		/* Wait for firmware load to finish. */</div><div class='ctx'> 		status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);</div><div class='ctx'> 		if (status != DMUB_STATUS_OK)</div><div class='del'>-			DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);</div><div class='add'>+			drm_warn(adev_to_drm(adev), "Wait for DMUB auto-load failed: %d\n", status);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Perform the full hardware initialization. */</div><div class='del'>-		dm_dmub_hw_init(adev);</div><div class='add'>+		r = dm_dmub_hw_init(adev);</div><div class='add'>+		if (r)</div><div class='add'>+			drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1389,18 +1569,18 @@ static void dm_handle_hpd_rx_offload_work(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);</div><div class='ctx'> 	aconnector = offload_work-&gt;offload_wq-&gt;aconnector;</div><div class='add'>+	adev = offload_work-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	if (!aconnector) {</div><div class='del'>-		DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Can't retrieve aconnector in hpd_rx_irq_offload_work");</div><div class='ctx'> 		goto skip;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	adev = drm_to_adev(aconnector-&gt;base.dev);</div><div class='ctx'> 	dc_link = aconnector-&gt;dc_link;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> 	if (!dc_link_detect_connection_type(dc_link, &amp;new_connection_type))</div><div class='del'>-		DRM_ERROR("KMS: Failed to detect connector\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");</div><div class='ctx'> 	mutex_unlock(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (new_connection_type == dc_connection_none)</div><div class='hunk'>@@ -1469,8 +1649,9 @@ skip:</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)</div><div class='add'>+static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct dc *dc = adev-&gt;dm.dc;</div><div class='ctx'> 	int max_caps = dc-&gt;caps.max_links;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;</div><div class='hunk'>@@ -1486,7 +1667,7 @@ static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct</div><div class='ctx'> 				    create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");</div><div class='ctx'> </div><div class='ctx'> 		if (hpd_rx_offload_wq[i].wq == NULL) {</div><div class='del'>-			DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");</div><div class='add'>+			drm_err(adev_to_drm(adev), "create amdgpu_dm_hpd_rx_offload_wq fail!");</div><div class='ctx'> 			goto out_err;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1535,76 +1716,163 @@ static bool dm_should_disable_stutter(struct pci_dev *pdev)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct dmi_system_id hpd_disconnect_quirk_table[] = {</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{}</div><div class='del'>-	/* TODO: refactor this from a fixed table to a dynamic option */</div><div class='del'>-};</div><div class='ctx'> </div><div class='del'>-static void retrieve_dmi_info(struct amdgpu_display_manager *dm)</div><div class='add'>+void*</div><div class='add'>+dm_allocate_gpu_mem(</div><div class='add'>+		struct amdgpu_device *adev,</div><div class='add'>+		enum dc_gpu_mem_alloc_type type,</div><div class='add'>+		size_t size,</div><div class='add'>+		long long *addr)</div><div class='add'>+{</div><div class='add'>+	struct dal_allocation *da;</div><div class='add'>+	u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?</div><div class='add'>+		AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);</div><div class='add'>+	if (!da)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,</div><div class='add'>+				      domain, &amp;da-&gt;bo,</div><div class='add'>+				      &amp;da-&gt;gpu_addr, &amp;da-&gt;cpu_ptr);</div><div class='add'>+</div><div class='add'>+	*addr = da-&gt;gpu_addr;</div><div class='add'>+</div><div class='add'>+	if (ret) {</div><div class='add'>+		kfree(da);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* add da to list in dm */</div><div class='add'>+	list_add(&amp;da-&gt;list, &amp;adev-&gt;dm.da_list);</div><div class='add'>+</div><div class='add'>+	return da-&gt;cpu_ptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+dm_free_gpu_mem(</div><div class='add'>+		struct amdgpu_device *adev,</div><div class='add'>+		enum dc_gpu_mem_alloc_type type,</div><div class='add'>+		void *pvMem)</div><div class='add'>+{</div><div class='add'>+	struct dal_allocation *da;</div><div class='add'>+</div><div class='add'>+	/* walk the da list in DM */</div><div class='add'>+	list_for_each_entry(da, &amp;adev-&gt;dm.da_list, list) {</div><div class='add'>+		if (pvMem == da-&gt;cpu_ptr) {</div><div class='add'>+			amdgpu_bo_free_kernel(&amp;da-&gt;bo, &amp;da-&gt;gpu_addr, &amp;da-&gt;cpu_ptr);</div><div class='add'>+			list_del(&amp;da-&gt;list);</div><div class='add'>+			kfree(da);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dmub_status</div><div class='add'>+dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev,</div><div class='add'>+				 enum dmub_gpint_command command_code,</div><div class='add'>+				 uint16_t param,</div><div class='add'>+				 uint32_t timeout_us)</div><div class='add'>+{</div><div class='add'>+	union dmub_gpint_data_register reg, test;</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	/* Assume that VBIOS DMUB is ready to take commands */</div><div class='add'>+</div><div class='add'>+	reg.bits.status = 1;</div><div class='add'>+	reg.bits.command_code = command_code;</div><div class='add'>+	reg.bits.param = param;</div><div class='add'>+</div><div class='add'>+	cgs_write_register(adev-&gt;dm.cgs_device, 0x34c0 + 0x01f8, reg.all);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; timeout_us; ++i) {</div><div class='add'>+		udelay(1);</div><div class='add'>+</div><div class='add'>+		/* Check if our GPINT got acked */</div><div class='add'>+		reg.bits.status = 0;</div><div class='add'>+		test = (union dmub_gpint_data_register)</div><div class='add'>+			cgs_read_register(adev-&gt;dm.cgs_device, 0x34c0 + 0x01f8);</div><div class='add'>+</div><div class='add'>+		if (test.all == reg.all)</div><div class='add'>+			return DMUB_STATUS_OK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_TIMEOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	const struct dmi_system_id *dmi_id;</div><div class='add'>+	void *bb;</div><div class='add'>+	long long addr;</div><div class='add'>+	unsigned int bb_size;</div><div class='add'>+	int i = 0;</div><div class='add'>+	uint16_t chunk;</div><div class='add'>+	enum dmub_gpint_command send_addrs[] = {</div><div class='add'>+		DMUB_GPINT__SET_BB_ADDR_WORD0,</div><div class='add'>+		DMUB_GPINT__SET_BB_ADDR_WORD1,</div><div class='add'>+		DMUB_GPINT__SET_BB_ADDR_WORD2,</div><div class='add'>+		DMUB_GPINT__SET_BB_ADDR_WORD3,</div><div class='add'>+	};</div><div class='add'>+	enum dmub_status ret;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(4, 0, 1):</div><div class='add'>+		bb_size = sizeof(struct dml2_soc_bb);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	dm-&gt;aux_hpd_discon_quirk = false;</div><div class='add'>+	bb =  dm_allocate_gpu_mem(adev,</div><div class='add'>+				  DC_MEM_ALLOC_TYPE_GART,</div><div class='add'>+				  bb_size,</div><div class='add'>+				  &amp;addr);</div><div class='add'>+	if (!bb)</div><div class='add'>+		return NULL;</div><div class='ctx'> </div><div class='del'>-	dmi_id = dmi_first_match(hpd_disconnect_quirk_table);</div><div class='del'>-	if (dmi_id) {</div><div class='del'>-		dm-&gt;aux_hpd_discon_quirk = true;</div><div class='del'>-		DRM_INFO("aux_hpd_discon_quirk attached\n");</div><div class='add'>+	for (i = 0; i &lt; 4; i++) {</div><div class='add'>+		/* Extract 16-bit chunk */</div><div class='add'>+		chunk = ((uint64_t) addr &gt;&gt; (i * 16)) &amp; 0xFFFF;</div><div class='add'>+		/* Send the chunk */</div><div class='add'>+		ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000);</div><div class='add'>+		if (ret != DMUB_STATUS_OK)</div><div class='add'>+			goto free_bb;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/* Now ask DMUB to copy the bb */</div><div class='add'>+	ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000);</div><div class='add'>+	if (ret != DMUB_STATUS_OK)</div><div class='add'>+		goto free_bb;</div><div class='add'>+</div><div class='add'>+	return bb;</div><div class='add'>+</div><div class='add'>+free_bb:</div><div class='add'>+	dm_free_gpu_mem(adev, DC_MEM_ALLOC_TYPE_GART, (void *) bb);</div><div class='add'>+	return NULL;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dmub_ips_disable_type dm_get_default_ips_mode(</div><div class='add'>+	struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;</div><div class='add'>+</div><div class='add'>+	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='add'>+	case IP_VERSION(3, 5, 0):</div><div class='add'>+	case IP_VERSION(3, 6, 0):</div><div class='add'>+	case IP_VERSION(3, 5, 1):</div><div class='add'>+		ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		/* ASICs older than DCN35 do not have IPSs */</div><div class='add'>+		if (amdgpu_ip_version(adev, DCE_HWIP, 0) &lt; IP_VERSION(3, 5, 0))</div><div class='add'>+			ret = DMUB_IPS_DISABLE_ALL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='hunk'>@@ -1625,7 +1893,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	mutex_init(&amp;adev-&gt;dm.audio_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_dm_irq_init(adev)) {</div><div class='del'>-		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n");</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1642,13 +1910,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	init_data.driver = adev;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;dm.cgs_device = amdgpu_cgs_create_device(adev);</div><div class='del'>-</div><div class='del'>-	if (!adev-&gt;dm.cgs_device) {</div><div class='del'>-		DRM_ERROR("amdgpu: failed to create cgs device.\n");</div><div class='del'>-		goto error;</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+	/* cgs_device was created in dm_sw_init() */</div><div class='ctx'> 	init_data.cgs_device = adev-&gt;dm.cgs_device;</div><div class='ctx'> </div><div class='ctx'> 	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;</div><div class='hunk'>@@ -1685,7 +1947,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		else</div><div class='ctx'> 			init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);</div><div class='ctx'> 	} else {</div><div class='del'>-		init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) &amp;&amp; (adev-&gt;flags &amp; AMD_IS_APU);</div><div class='add'>+		if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3))</div><div class='add'>+			init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1);</div><div class='add'>+		else</div><div class='add'>+			init_data.flags.gpu_vm_support =</div><div class='add'>+				(amdgpu_sg_display != 0) &amp;&amp; (adev-&gt;flags &amp; AMD_IS_APU);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;</div><div class='hunk'>@@ -1712,7 +1978,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_device_seamless_boot_supported(adev)) {</div><div class='ctx'> 		init_data.flags.seamless_boot_edp_requested = true;</div><div class='ctx'> 		init_data.flags.allow_seamless_boot_optimization = true;</div><div class='del'>-		DRM_INFO("Seamless boot condition check passed\n");</div><div class='add'>+		drm_dbg(adev-&gt;dm.ddev, "Seamless boot requested\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	init_data.flags.enable_mipi_converter_optimization = true;</div><div class='hunk'>@@ -1723,25 +1989,42 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_IPS)</div><div class='ctx'> 		init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;</div><div class='add'>+	else if (amdgpu_dc_debug_mask &amp; DC_DISABLE_IPS_DYNAMIC)</div><div class='add'>+		init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC;</div><div class='add'>+	else if (amdgpu_dc_debug_mask &amp; DC_DISABLE_IPS2_DYNAMIC)</div><div class='add'>+		init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;</div><div class='add'>+	else if (amdgpu_dc_debug_mask &amp; DC_FORCE_IPS_ENABLE)</div><div class='add'>+		init_data.flags.disable_ips = DMUB_IPS_ENABLE;</div><div class='add'>+	else</div><div class='add'>+		init_data.flags.disable_ips = dm_get_default_ips_mode(adev);</div><div class='add'>+</div><div class='add'>+	init_data.flags.disable_ips_in_vpb = 0;</div><div class='ctx'> </div><div class='del'>-	init_data.flags.disable_ips_in_vpb = 1;</div><div class='add'>+	/* DCN35 and above supports dynamic DTBCLK switch */</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &gt;= IP_VERSION(3, 5, 0))</div><div class='add'>+		init_data.flags.allow_0_dtb_clk = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Enable DWB for tested platforms only */</div><div class='ctx'> 	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &gt;= IP_VERSION(3, 0, 0))</div><div class='ctx'> 		init_data.num_virtual_links = 1;</div><div class='ctx'> </div><div class='del'>-	INIT_LIST_HEAD(&amp;adev-&gt;dm.da_list);</div><div class='del'>-</div><div class='ctx'> 	retrieve_dmi_info(&amp;adev-&gt;dm);</div><div class='add'>+	if (adev-&gt;dm.edp0_on_dp1_quirk)</div><div class='add'>+		init_data.flags.support_edp0_on_dp1 = true;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dm.bb_from_dmub)</div><div class='add'>+		init_data.bb_from_dmub = adev-&gt;dm.bb_from_dmub;</div><div class='add'>+	else</div><div class='add'>+		init_data.bb_from_dmub = NULL;</div><div class='ctx'> </div><div class='ctx'> 	/* Display Core create. */</div><div class='ctx'> 	adev-&gt;dm.dc = dc_create(&amp;init_data);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;dm.dc) {</div><div class='del'>-		DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,</div><div class='add'>+		drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER,</div><div class='ctx'> 			 dce_version_to_string(adev-&gt;dm.dc-&gt;ctx-&gt;dce_version));</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);</div><div class='add'>+		drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER);</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1767,8 +2050,24 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_dc_debug_mask &amp; DC_FORCE_SUBVP_MCLK_SWITCH)</div><div class='ctx'> 		adev-&gt;dm.dc-&gt;debug.force_subvp_mclk_switch = true;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_dc_debug_mask &amp; DC_ENABLE_DML2)</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_SUBVP_FAMS) {</div><div class='add'>+		adev-&gt;dm.dc-&gt;debug.force_disable_subvp = true;</div><div class='add'>+		adev-&gt;dm.dc-&gt;debug.fams2_config.bits.enable = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_ENABLE_DML2) {</div><div class='ctx'> 		adev-&gt;dm.dc-&gt;debug.using_dml2 = true;</div><div class='add'>+		adev-&gt;dm.dc-&gt;debug.using_dml21 = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_HDCP_LC_FORCE_FW_ENABLE)</div><div class='add'>+		adev-&gt;dm.dc-&gt;debug.hdcp_lc_force_fw_enable = true;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_HDCP_LC_ENABLE_SW_FALLBACK)</div><div class='add'>+		adev-&gt;dm.dc-&gt;debug.hdcp_lc_enable_sw_fallback = true;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_SKIP_DETECTION_LT)</div><div class='add'>+		adev-&gt;dm.dc-&gt;debug.skip_detection_link_training = true;</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;dm.dc-&gt;debug.visual_confirm = amdgpu_dc_visual_confirm;</div><div class='ctx'> </div><div class='hunk'>@@ -1776,19 +2075,19 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev-&gt;dm.dc-&gt;debug.ignore_cable_id = true;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;dm.dc-&gt;caps.dp_hdmi21_pcon_support)</div><div class='del'>-		DRM_INFO("DP-HDMI FRL PCON supported\n");</div><div class='add'>+		drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n");</div><div class='ctx'> </div><div class='ctx'> 	r = dm_dmub_hw_init(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);</div><div class='add'>+		drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dc_hardware_init(adev-&gt;dm.dc);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev-&gt;dm.dc);</div><div class='add'>+	adev-&gt;dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev);</div><div class='ctx'> 	if (!adev-&gt;dm.hpd_rx_offload_wq) {</div><div class='del'>-		DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n");</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1803,10 +2102,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;dm.freesync_module = mod_freesync_create(adev-&gt;dm.dc);</div><div class='ctx'> 	if (!adev-&gt;dm.freesync_module) {</div><div class='del'>-		DRM_ERROR(</div><div class='del'>-		"amdgpu: failed to initialize freesync_module.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev),</div><div class='add'>+		"failed to initialize freesync_module.\n");</div><div class='ctx'> 	} else</div><div class='del'>-		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",</div><div class='add'>+		drm_dbg_driver(adev_to_drm(adev), "amdgpu: freesync_module init done %p.\n",</div><div class='ctx'> 				adev-&gt;dm.freesync_module);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_init_color_mod();</div><div class='hunk'>@@ -1815,16 +2114,20 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;dm.vblank_control_workqueue =</div><div class='ctx'> 			create_singlethread_workqueue("dm_vblank_control_workqueue");</div><div class='ctx'> 		if (!adev-&gt;dm.vblank_control_workqueue)</div><div class='del'>-			DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;dm.dc-&gt;caps.ips_support &amp;&amp;</div><div class='add'>+	    adev-&gt;dm.dc-&gt;config.disable_ips != DMUB_IPS_DISABLE_ALL)</div><div class='add'>+		adev-&gt;dm.idle_workqueue = idle_create_workqueue(adev);</div><div class='add'>+</div><div class='ctx'> 	if (adev-&gt;dm.dc-&gt;caps.max_links &gt; 0 &amp;&amp; adev-&gt;family &gt;= AMDGPU_FAMILY_RV) {</div><div class='ctx'> 		adev-&gt;dm.hdcp_workqueue = hdcp_create_workqueue(adev, &amp;init_params.cp_psp, adev-&gt;dm.dc);</div><div class='ctx'> </div><div class='ctx'> 		if (!adev-&gt;dm.hdcp_workqueue)</div><div class='del'>-			DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n");</div><div class='ctx'> 		else</div><div class='del'>-			DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev-&gt;dm.hdcp_workqueue);</div><div class='add'>+			drm_dbg_driver(adev_to_drm(adev), "amdgpu: hdcp_workqueue init done %p.\n", adev-&gt;dm.hdcp_workqueue);</div><div class='ctx'> </div><div class='ctx'> 		dc_init_callbacks(adev-&gt;dm.dc, &amp;init_params);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1832,20 +2135,29 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		init_completion(&amp;adev-&gt;dm.dmub_aux_transfer_done);</div><div class='ctx'> 		adev-&gt;dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);</div><div class='ctx'> 		if (!adev-&gt;dm.dmub_notify) {</div><div class='del'>-			DRM_INFO("amdgpu: fail to allocate adev-&gt;dm.dmub_notify");</div><div class='add'>+			drm_info(adev_to_drm(adev), "fail to allocate adev-&gt;dm.dmub_notify");</div><div class='ctx'> 			goto error;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");</div><div class='ctx'> 		if (!adev-&gt;dm.delayed_hpd_wq) {</div><div class='del'>-			DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n");</div><div class='ctx'> 			goto error;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_outbox_init(adev);</div><div class='ctx'> 		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,</div><div class='ctx'> 			dmub_aux_setconfig_callback, false)) {</div><div class='del'>-			DRM_ERROR("amdgpu: fail to register dmub aux callback");</div><div class='add'>+			drm_err(adev_to_drm(adev), "fail to register dmub aux callback");</div><div class='add'>+			goto error;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (size_t i = 0; i &lt; ARRAY_SIZE(adev-&gt;dm.fused_io); i++)</div><div class='add'>+			init_completion(&amp;adev-&gt;dm.fused_io[i].replied);</div><div class='add'>+</div><div class='add'>+		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO,</div><div class='add'>+			dmub_aux_fused_io_callback, false)) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "fail to register dmub fused io callback");</div><div class='ctx'> 			goto error;</div><div class='ctx'> 		}</div><div class='ctx'> 		/* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.</div><div class='hunk'>@@ -1862,8 +2174,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_dm_initialize_drm_device(adev)) {</div><div class='del'>-		DRM_ERROR(</div><div class='del'>-		"amdgpu: failed to initialize sw for display support.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev),</div><div class='add'>+		"failed to initialize sw for display support.\n");</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1877,18 +2189,22 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	adev_to_drm(adev)-&gt;mode_config.cursor_height = adev-&gt;dm.dc-&gt;caps.max_cursor_size;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_vblank_init(adev_to_drm(adev), adev-&gt;dm.display_indexes_num)) {</div><div class='del'>-		DRM_ERROR(</div><div class='del'>-		"amdgpu: failed to initialize sw for display support.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev),</div><div class='add'>+		"failed to initialize vblank for display support.\n");</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='del'>-	adev-&gt;dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);</div><div class='del'>-	if (!adev-&gt;dm.secure_display_ctxs)</div><div class='del'>-		DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");</div><div class='add'>+	amdgpu_dm_crtc_secure_display_create_contexts(adev);</div><div class='add'>+	if (!adev-&gt;dm.secure_display_ctx.crtc_ctx)</div><div class='add'>+		drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n");</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &gt;= IP_VERSION(4, 0, 1))</div><div class='add'>+		adev-&gt;dm.secure_display_ctx.support_mul_roi = true;</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG_DRIVER("KMS initialized.\n");</div><div class='add'>+	drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> error:</div><div class='hunk'>@@ -1897,9 +2213,9 @@ error:</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_dm_early_fini(void *handle)</div><div class='add'>+static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_audio_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -1915,18 +2231,28 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;dm.vblank_control_workqueue = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;dm.idle_workqueue) {</div><div class='add'>+		if (adev-&gt;dm.idle_workqueue-&gt;running) {</div><div class='add'>+			adev-&gt;dm.idle_workqueue-&gt;enable = false;</div><div class='add'>+			flush_work(&amp;adev-&gt;dm.idle_workqueue-&gt;work);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		kfree(adev-&gt;dm.idle_workqueue);</div><div class='add'>+		adev-&gt;dm.idle_workqueue = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	amdgpu_dm_destroy_drm_device(&amp;adev-&gt;dm);</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='del'>-	if (adev-&gt;dm.secure_display_ctxs) {</div><div class='add'>+	if (adev-&gt;dm.secure_display_ctx.crtc_ctx) {</div><div class='ctx'> 		for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-			if (adev-&gt;dm.secure_display_ctxs[i].crtc) {</div><div class='del'>-				flush_work(&amp;adev-&gt;dm.secure_display_ctxs[i].notify_ta_work);</div><div class='del'>-				flush_work(&amp;adev-&gt;dm.secure_display_ctxs[i].forward_roi_work);</div><div class='add'>+			if (adev-&gt;dm.secure_display_ctx.crtc_ctx[i].crtc) {</div><div class='add'>+				flush_work(&amp;adev-&gt;dm.secure_display_ctx.crtc_ctx[i].notify_ta_work);</div><div class='add'>+				flush_work(&amp;adev-&gt;dm.secure_display_ctx.crtc_ctx[i].forward_roi_work);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-		kfree(adev-&gt;dm.secure_display_ctxs);</div><div class='del'>-		adev-&gt;dm.secure_display_ctxs = NULL;</div><div class='add'>+		kfree(adev-&gt;dm.secure_display_ctx.crtc_ctx);</div><div class='add'>+		adev-&gt;dm.secure_display_ctx.crtc_ctx = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> 	if (adev-&gt;dm.hdcp_workqueue) {</div><div class='hunk'>@@ -2045,11 +2371,13 @@ static int load_dmcu_fw(struct amdgpu_device *adev)</div><div class='ctx'> 		case IP_VERSION(3, 2, 1):</div><div class='ctx'> 		case IP_VERSION(3, 5, 0):</div><div class='ctx'> 		case IP_VERSION(3, 5, 1):</div><div class='add'>+		case IP_VERSION(3, 6, 0):</div><div class='add'>+		case IP_VERSION(4, 0, 1):</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev-&gt;asic_type);</div><div class='add'>+		drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev-&gt;asic_type);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2058,7 +2386,8 @@ static int load_dmcu_fw(struct amdgpu_device *adev)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_ucode_request(adev, &amp;adev-&gt;dm.fw_dmcu, fw_name_dmcu);</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;dm.fw_dmcu, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				 "%s", fw_name_dmcu);</div><div class='ctx'> 	if (r == -ENODEV) {</div><div class='ctx'> 		/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */</div><div class='ctx'> 		DRM_DEBUG_KMS("dm: DMCU firmware not found\n");</div><div class='hunk'>@@ -2066,7 +2395,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",</div><div class='add'>+		drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n",</div><div class='ctx'> 			fw_name_dmcu);</div><div class='ctx'> 		amdgpu_ucode_release(&amp;adev-&gt;dm.fw_dmcu);</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -2125,6 +2454,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_5_TRACEBUFF</div><div class='ctx'> 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_6_FW_STATE</div><div class='ctx'> 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_7_SCRATCH_MEM</div><div class='add'>+		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_IB_MEM</div><div class='ctx'> 		DMUB_WINDOW_MEMORY_TYPE_FB,		//DMUB_WINDOW_SHARED_STATE</div><div class='ctx'> 	};</div><div class='ctx'> 	int r;</div><div class='hunk'>@@ -2168,6 +2498,13 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(3, 5, 1):</div><div class='ctx'> 		dmub_asic = DMUB_ASIC_DCN35;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(3, 6, 0):</div><div class='add'>+		dmub_asic = DMUB_ASIC_DCN36;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(4, 0, 1):</div><div class='add'>+		dmub_asic = DMUB_ASIC_DCN401;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* ASIC doesn't support DMUB. */</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -2184,7 +2521,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;firmware.fw_size +=</div><div class='ctx'> 			ALIGN(le32_to_cpu(hdr-&gt;inst_const_bytes), PAGE_SIZE);</div><div class='ctx'> </div><div class='del'>-		DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",</div><div class='add'>+		drm_info(adev_to_drm(adev), "Loading DMUB firmware via PSP: version=0x%08X\n",</div><div class='ctx'> 			 adev-&gt;dm.dmcub_fw_version);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2193,7 +2530,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	dmub_srv = adev-&gt;dm.dmub_srv;</div><div class='ctx'> </div><div class='ctx'> 	if (!dmub_srv) {</div><div class='del'>-		DRM_ERROR("Failed to allocate DMUB service!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to allocate DMUB service!\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2206,7 +2543,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* Create the DMUB service. */</div><div class='ctx'> 	status = dmub_srv_create(dmub_srv, &amp;create_params);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DRM_ERROR("Error creating DMUB service: %d\n", status);</div><div class='add'>+		drm_err(adev_to_drm(adev), "Error creating DMUB service: %d\n", status);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2231,7 +2568,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 					   &amp;region_info);</div><div class='ctx'> </div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DRM_ERROR("Error calculating DMUB region info: %d\n", status);</div><div class='add'>+		drm_err(adev_to_drm(adev), "Error calculating DMUB region info: %d\n", status);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2260,25 +2597,37 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)</div><div class='ctx'> 	fb_info = adev-&gt;dm.dmub_fb_info;</div><div class='ctx'> </div><div class='ctx'> 	if (!fb_info) {</div><div class='del'>-		DRM_ERROR(</div><div class='add'>+		drm_err(adev_to_drm(adev),</div><div class='ctx'> 			"Failed to allocate framebuffer info for DMUB service!\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = dmub_srv_calc_mem_info(dmub_srv, &amp;memory_params, fb_info);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DRM_ERROR("Error calculating DMUB FB info: %d\n", status);</div><div class='add'>+		drm_err(adev_to_drm(adev), "Error calculating DMUB FB info: %d\n", status);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adev-&gt;dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_sw_init(void *handle)</div><div class='add'>+static int dm_sw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;dm.cgs_device = amdgpu_cgs_create_device(adev);</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;dm.cgs_device) {</div><div class='add'>+		drm_err(adev_to_drm(adev), "failed to create cgs device.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Moved from dm init since we need to use allocations for storing bounding box data */</div><div class='add'>+	INIT_LIST_HEAD(&amp;adev-&gt;dm.da_list);</div><div class='add'>+</div><div class='ctx'> 	r = dm_dmub_sw_init(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -2286,9 +2635,21 @@ static int dm_sw_init(void *handle)</div><div class='ctx'> 	return load_dmcu_fw(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_sw_fini(void *handle)</div><div class='add'>+static int dm_sw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct dal_allocation *da;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(da, &amp;adev-&gt;dm.da_list, list) {</div><div class='add'>+		if (adev-&gt;dm.bb_from_dmub == (void *) da-&gt;cpu_ptr) {</div><div class='add'>+			amdgpu_bo_free_kernel(&amp;da-&gt;bo, &amp;da-&gt;gpu_addr, &amp;da-&gt;cpu_ptr);</div><div class='add'>+			list_del(&amp;da-&gt;list);</div><div class='add'>+			kfree(da);</div><div class='add'>+			adev-&gt;dm.bb_from_dmub = NULL;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 	kfree(adev-&gt;dm.dmub_fb_info);</div><div class='ctx'> 	adev-&gt;dm.dmub_fb_info = NULL;</div><div class='hunk'>@@ -2321,13 +2682,13 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (aconnector-&gt;dc_link-&gt;type == dc_connection_mst_branch &amp;&amp;</div><div class='ctx'> 		    aconnector-&gt;mst_mgr.aux) {</div><div class='del'>-			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",</div><div class='add'>+			drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n",</div><div class='ctx'> 					 aconnector,</div><div class='ctx'> 					 aconnector-&gt;base.base.id);</div><div class='ctx'> </div><div class='ctx'> 			ret = drm_dp_mst_topology_mgr_set_mst(&amp;aconnector-&gt;mst_mgr, true);</div><div class='ctx'> 			if (ret &lt; 0) {</div><div class='del'>-				DRM_ERROR("DM_MST: Failed to start MST\n");</div><div class='add'>+				drm_err(dev, "DM_MST: Failed to start MST\n");</div><div class='ctx'> 				aconnector-&gt;dc_link-&gt;type =</div><div class='ctx'> 					dc_connection_single;</div><div class='ctx'> 				ret = dm_helpers_dp_mst_stop_top_mgr(aconnector-&gt;dc_link-&gt;ctx,</div><div class='hunk'>@@ -2341,9 +2702,9 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_late_init(void *handle)</div><div class='add'>+static int dm_late_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	struct dmcu_iram_parameters params;</div><div class='ctx'> 	unsigned int linear_lut[16];</div><div class='hunk'>@@ -2389,9 +2750,9 @@ static int dm_late_init(void *handle)</div><div class='ctx'> </div><div class='ctx'> static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)</div><div class='ctx'> {</div><div class='add'>+	u8 buf[UUID_SIZE];</div><div class='add'>+	guid_t guid;</div><div class='ctx'> 	int ret;</div><div class='del'>-	u8 guid[16];</div><div class='del'>-	u64 tmp64;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;mgr-&gt;lock);</div><div class='ctx'> 	if (!mgr-&gt;mst_primary)</div><div class='hunk'>@@ -2412,31 +2773,74 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Some hubs forget their guids after they resume */</div><div class='del'>-	ret = drm_dp_dpcd_read(mgr-&gt;aux, DP_GUID, guid, 16);</div><div class='del'>-	if (ret != 16) {</div><div class='add'>+	ret = drm_dp_dpcd_read(mgr-&gt;aux, DP_GUID, buf, sizeof(buf));</div><div class='add'>+	if (ret != sizeof(buf)) {</div><div class='ctx'> 		drm_dbg_kms(mgr-&gt;dev, "dpcd read failed - undocked during suspend?\n");</div><div class='ctx'> 		goto out_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (memchr_inv(guid, 0, 16) == NULL) {</div><div class='del'>-		tmp64 = get_jiffies_64();</div><div class='del'>-		memcpy(&amp;guid[0], &amp;tmp64, sizeof(u64));</div><div class='del'>-		memcpy(&amp;guid[8], &amp;tmp64, sizeof(u64));</div><div class='add'>+	import_guid(&amp;guid, buf);</div><div class='ctx'> </div><div class='del'>-		ret = drm_dp_dpcd_write(mgr-&gt;aux, DP_GUID, guid, 16);</div><div class='add'>+	if (guid_is_null(&amp;guid)) {</div><div class='add'>+		guid_gen(&amp;guid);</div><div class='add'>+		export_guid(buf, &amp;guid);</div><div class='ctx'> </div><div class='del'>-		if (ret != 16) {</div><div class='add'>+		ret = drm_dp_dpcd_write(mgr-&gt;aux, DP_GUID, buf, sizeof(buf));</div><div class='add'>+</div><div class='add'>+		if (ret != sizeof(buf)) {</div><div class='ctx'> 			drm_dbg_kms(mgr-&gt;dev, "check mstb guid failed - undocked during suspend?\n");</div><div class='ctx'> 			goto out_fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	memcpy(mgr-&gt;mst_primary-&gt;guid, guid, 16);</div><div class='add'>+	guid_copy(&amp;mgr-&gt;mst_primary-&gt;guid, &amp;guid);</div><div class='ctx'> </div><div class='ctx'> out_fail:</div><div class='ctx'> 	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+{</div><div class='add'>+	struct cec_notifier *n = aconnector-&gt;notifier;</div><div class='add'>+</div><div class='add'>+	if (!n)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cec_notifier_phys_addr_invalidate(n);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct cec_notifier *n = aconnector-&gt;notifier;</div><div class='add'>+</div><div class='add'>+	if (!n)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cec_notifier_set_phys_addr(n,</div><div class='add'>+				   connector-&gt;display_info.source_physical_address);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='add'>+	struct drm_connector *connector;</div><div class='add'>+	struct drm_connector_list_iter conn_iter;</div><div class='add'>+</div><div class='add'>+	drm_connector_list_iter_begin(ddev, &amp;conn_iter);</div><div class='add'>+	drm_for_each_connector_iter(connector, &amp;conn_iter) {</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+		if (suspend)</div><div class='add'>+			hdmi_cec_unset_edid(aconnector);</div><div class='add'>+		else</div><div class='add'>+			hdmi_cec_set_edid(aconnector);</div><div class='add'>+	}</div><div class='add'>+	drm_connector_list_iter_end(&amp;conn_iter);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void s3_handle_mst(struct drm_device *dev, bool suspend)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='hunk'>@@ -2523,16 +2927,43 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_dpm_write_watermarks_table(adev);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		DRM_ERROR("Failed to update WMTABLE!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dm_oem_i2c_hw_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='add'>+	struct amdgpu_i2c_adapter *oem_i2c;</div><div class='add'>+	struct ddc_service *oem_ddc_service;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	oem_ddc_service = dc_get_oem_i2c_device(adev-&gt;dm.dc);</div><div class='add'>+	if (oem_ddc_service) {</div><div class='add'>+		oem_i2c = create_i2c(oem_ddc_service, true);</div><div class='add'>+		if (!oem_i2c) {</div><div class='add'>+			drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n");</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		r = devm_i2c_add_adapter(adev-&gt;dev, &amp;oem_i2c-&gt;base);</div><div class='add'>+		if (r) {</div><div class='add'>+			drm_info(adev_to_drm(adev), "Failed to register oem i2c\n");</div><div class='add'>+			kfree(oem_i2c);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='add'>+		dm-&gt;oem_i2c = oem_i2c;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * dm_hw_init() - Initialize DC device</div><div class='del'>- * @handle: The base driver device containing the amdgpu_dm device.</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the &amp;struct amdgpu_display_manager device. This involves calling</div><div class='ctx'>  * the initializers of each DM component, then populating the struct with them.</div><div class='hunk'>@@ -2550,27 +2981,35 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)</div><div class='ctx'>  * - Vblank support</div><div class='ctx'>  * - Debug FS entries, if enabled</div><div class='ctx'>  */</div><div class='del'>-static int dm_hw_init(void *handle)</div><div class='add'>+static int dm_hw_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='ctx'> 	/* Create DAL display manager */</div><div class='del'>-	amdgpu_dm_init(adev);</div><div class='add'>+	r = amdgpu_dm_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='ctx'> 	amdgpu_dm_hpd_init(adev);</div><div class='ctx'> </div><div class='add'>+	r = dm_oem_i2c_hw_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n");</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dm_hw_fini() - Teardown DC device</div><div class='del'>- * @handle: The base driver device containing the amdgpu_dm device.</div><div class='add'>+ * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.</div><div class='ctx'>  *</div><div class='ctx'>  * Teardown components within &amp;struct amdgpu_display_manager that require</div><div class='ctx'>  * cleanup. This involves cleaning up the DRM device, DC, and any modules that</div><div class='ctx'>  * were loaded. Also flush IRQ workqueues and disable them.</div><div class='ctx'>  */</div><div class='del'>-static int dm_hw_fini(void *handle)</div><div class='add'>+static int dm_hw_fini(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_hpd_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -2596,42 +3035,50 @@ static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,</div><div class='ctx'> 			irq_source = IRQ_TYPE_PFLIP + acrtc-&gt;otg_inst;</div><div class='ctx'> 			rc = dc_interrupt_set(adev-&gt;dm.dc, irq_source, enable) ? 0 : -EBUSY;</div><div class='ctx'> 			if (rc)</div><div class='del'>-				DRM_WARN("Failed to %s pflip interrupts\n",</div><div class='add'>+				drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n",</div><div class='ctx'> 					 enable ? "enable" : "disable");</div><div class='ctx'> </div><div class='del'>-			if (enable) {</div><div class='del'>-				if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc-&gt;base.state)))</div><div class='del'>-					rc = amdgpu_dm_crtc_set_vupdate_irq(&amp;acrtc-&gt;base, true);</div><div class='del'>-			} else</div><div class='del'>-				rc = amdgpu_dm_crtc_set_vupdate_irq(&amp;acrtc-&gt;base, false);</div><div class='del'>-</div><div class='del'>-			if (rc)</div><div class='del'>-				DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");</div><div class='add'>+			if (dc_supports_vrr(adev-&gt;dm.dc-&gt;ctx-&gt;dce_version)) {</div><div class='add'>+				if (enable) {</div><div class='add'>+					if (amdgpu_dm_crtc_vrr_active(</div><div class='add'>+							to_dm_crtc_state(acrtc-&gt;base.state)))</div><div class='add'>+						rc = amdgpu_dm_crtc_set_vupdate_irq(</div><div class='add'>+							&amp;acrtc-&gt;base, true);</div><div class='add'>+				} else</div><div class='add'>+					rc = amdgpu_dm_crtc_set_vupdate_irq(</div><div class='add'>+							&amp;acrtc-&gt;base, false);</div><div class='add'>+</div><div class='add'>+				if (rc)</div><div class='add'>+					drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n",</div><div class='add'>+						enable ? "en" : "dis");</div><div class='add'>+			}</div><div class='ctx'> </div><div class='ctx'> 			irq_source = IRQ_TYPE_VBLANK + acrtc-&gt;otg_inst;</div><div class='ctx'> 			/* During gpu-reset we disable and then enable vblank irq, so</div><div class='ctx'> 			 * don't use amdgpu_irq_get/put() to avoid refcount change.</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (!dc_interrupt_set(adev-&gt;dm.dc, irq_source, enable))</div><div class='del'>-				DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");</div><div class='add'>+				drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T))</div><div class='add'>+</div><div class='ctx'> static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)</div><div class='ctx'> {</div><div class='del'>-	struct dc_state *context = NULL;</div><div class='del'>-	enum dc_status res = DC_ERROR_UNEXPECTED;</div><div class='add'>+	struct dc_state *context __free(state_release) = NULL;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct dc_stream_state *del_streams[MAX_PIPES];</div><div class='ctx'> 	int del_streams_count = 0;</div><div class='add'>+	struct dc_commit_streams_params params = {};</div><div class='ctx'> </div><div class='ctx'> 	memset(del_streams, 0, sizeof(del_streams));</div><div class='ctx'> </div><div class='ctx'> 	context = dc_state_create_current_copy(dc);</div><div class='ctx'> 	if (context == NULL)</div><div class='del'>-		goto context_alloc_fail;</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='ctx'> </div><div class='ctx'> 	/* First remove from context all streams */</div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='hunk'>@@ -2642,23 +3089,20 @@ static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 	/* Remove all planes for removed streams and then remove the streams */</div><div class='ctx'> 	for (i = 0; i &lt; del_streams_count; i++) {</div><div class='del'>-		if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {</div><div class='del'>-			res = DC_FAIL_DETACH_SURFACES;</div><div class='del'>-			goto fail;</div><div class='del'>-		}</div><div class='add'>+		enum dc_status res;</div><div class='add'>+</div><div class='add'>+		if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context))</div><div class='add'>+			return DC_FAIL_DETACH_SURFACES;</div><div class='ctx'> </div><div class='ctx'> 		res = dc_state_remove_stream(dc, context, del_streams[i]);</div><div class='ctx'> 		if (res != DC_OK)</div><div class='del'>-			goto fail;</div><div class='add'>+			return res;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	res = dc_commit_streams(dc, context-&gt;streams, context-&gt;stream_count);</div><div class='add'>+	params.streams = context-&gt;streams;</div><div class='add'>+	params.stream_count = context-&gt;stream_count;</div><div class='ctx'> </div><div class='del'>-fail:</div><div class='del'>-	dc_state_release(context);</div><div class='del'>-</div><div class='del'>-context_alloc_fail:</div><div class='del'>-	return res;</div><div class='add'>+	return dc_commit_streams(dc, &amp;params);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)</div><div class='hunk'>@@ -2671,34 +3115,108 @@ static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_suspend(void *handle)</div><div class='add'>+static int dm_cache_state(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	adev-&gt;dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));</div><div class='add'>+	if (IS_ERR(adev-&gt;dm.cached_state)) {</div><div class='add'>+		r = PTR_ERR(adev-&gt;dm.cached_state);</div><div class='add'>+		adev-&gt;dm.cached_state = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return adev-&gt;dm.cached_state ? 0 : r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dm_destroy_cached_state(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = handle;</div><div class='ctx'> 	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='del'>-	int ret = 0;</div><div class='add'>+	struct drm_device *ddev = adev_to_drm(adev);</div><div class='add'>+	struct dm_plane_state *dm_new_plane_state;</div><div class='add'>+	struct drm_plane_state *new_plane_state;</div><div class='add'>+	struct dm_crtc_state *dm_new_crtc_state;</div><div class='add'>+	struct drm_crtc_state *new_crtc_state;</div><div class='add'>+	struct drm_plane *plane;</div><div class='add'>+	struct drm_crtc *crtc;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!dm-&gt;cached_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Force mode set in atomic commit */</div><div class='add'>+	for_each_new_crtc_in_state(dm-&gt;cached_state, crtc, new_crtc_state, i) {</div><div class='add'>+		new_crtc_state-&gt;active_changed = true;</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+		reset_freesync_config_for_crtc(dm_new_crtc_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * atomic_check is expected to create the dc states. We need to release</div><div class='add'>+	 * them here, since they were duplicated as part of the suspend</div><div class='add'>+	 * procedure.</div><div class='add'>+	 */</div><div class='add'>+	for_each_new_crtc_in_state(dm-&gt;cached_state, crtc, new_crtc_state, i) {</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+		if (dm_new_crtc_state-&gt;stream) {</div><div class='add'>+			WARN_ON(kref_read(&amp;dm_new_crtc_state-&gt;stream-&gt;refcount) &gt; 1);</div><div class='add'>+			dc_stream_release(dm_new_crtc_state-&gt;stream);</div><div class='add'>+			dm_new_crtc_state-&gt;stream = NULL;</div><div class='add'>+		}</div><div class='add'>+		dm_new_crtc_state-&gt;base.color_mgmt_changed = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_new_plane_in_state(dm-&gt;cached_state, plane, new_plane_state, i) {</div><div class='add'>+		dm_new_plane_state = to_dm_plane_state(new_plane_state);</div><div class='add'>+		if (dm_new_plane_state-&gt;dc_state) {</div><div class='add'>+			WARN_ON(kref_read(&amp;dm_new_plane_state-&gt;dc_state-&gt;refcount) &gt; 1);</div><div class='add'>+			dc_plane_state_release(dm_new_plane_state-&gt;dc_state);</div><div class='add'>+			dm_new_plane_state-&gt;dc_state = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_atomic_helper_resume(ddev, dm-&gt;cached_state);</div><div class='add'>+</div><div class='add'>+	dm-&gt;cached_state = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dm_suspend(struct amdgpu_ip_block *ip_block)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='add'>+	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_in_reset(adev)) {</div><div class='add'>+		enum dc_status res;</div><div class='add'>+</div><div class='ctx'> 		mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> </div><div class='ctx'> 		dc_allow_idle_optimizations(adev-&gt;dm.dc, false);</div><div class='ctx'> </div><div class='ctx'> 		dm-&gt;cached_dc_state = dc_state_create_copy(dm-&gt;dc-&gt;current_state);</div><div class='ctx'> </div><div class='del'>-		dm_gpureset_toggle_interrupts(adev, dm-&gt;cached_dc_state, false);</div><div class='add'>+		if (dm-&gt;cached_dc_state)</div><div class='add'>+			dm_gpureset_toggle_interrupts(adev, dm-&gt;cached_dc_state, false);</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_commit_zero_streams(dm-&gt;dc);</div><div class='add'>+		res = amdgpu_dm_commit_zero_streams(dm-&gt;dc);</div><div class='add'>+		if (res != DC_OK) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_irq_suspend(adev);</div><div class='ctx'> </div><div class='ctx'> 		hpd_rx_irq_work_suspend(dm);</div><div class='ctx'> </div><div class='del'>-		return ret;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	WARN_ON(adev-&gt;dm.cached_state);</div><div class='del'>-	adev-&gt;dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));</div><div class='del'>-	if (IS_ERR(adev-&gt;dm.cached_state))</div><div class='del'>-		return PTR_ERR(adev-&gt;dm.cached_state);</div><div class='add'>+	if (!adev-&gt;dm.cached_state) {</div><div class='add'>+		int r = dm_cache_state(adev);</div><div class='add'>+</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	s3_handle_hdmi_cec(adev_to_drm(adev), true);</div><div class='ctx'> </div><div class='ctx'> 	s3_handle_mst(adev_to_drm(adev), true);</div><div class='ctx'> </div><div class='hunk'>@@ -2707,6 +3225,10 @@ static int dm_suspend(void *handle)</div><div class='ctx'> 	hpd_rx_irq_work_suspend(dm);</div><div class='ctx'> </div><div class='ctx'> 	dc_set_power_state(dm-&gt;dc, DC_ACPI_CM_POWER_STATE_D3);</div><div class='add'>+</div><div class='add'>+	if (dm-&gt;dc-&gt;caps.ips_support &amp;&amp; adev-&gt;in_s0ix)</div><div class='add'>+		dc_allow_idle_optimizations(dm-&gt;dc, true);</div><div class='add'>+</div><div class='ctx'> 	dc_dmub_srv_set_power_state(dm-&gt;dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D3);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2823,57 +3345,127 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,</div><div class='ctx'> 		struct dc_scaling_info scaling_infos[MAX_SURFACES];</div><div class='ctx'> 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];</div><div class='ctx'> 		struct dc_stream_update stream_update;</div><div class='del'>-	} *bundle;</div><div class='add'>+	} *bundle __free(kfree);</div><div class='ctx'> 	int k, m;</div><div class='ctx'> </div><div class='ctx'> 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!bundle) {</div><div class='ctx'> 		drm_err(dm-&gt;ddev, "Failed to allocate update bundle\n");</div><div class='del'>-		goto cleanup;</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (k = 0; k &lt; dc_state-&gt;stream_count; k++) {</div><div class='ctx'> 		bundle-&gt;stream_update.stream = dc_state-&gt;streams[k];</div><div class='ctx'> </div><div class='del'>-		for (m = 0; m &lt; dc_state-&gt;stream_status-&gt;plane_count; m++) {</div><div class='add'>+		for (m = 0; m &lt; dc_state-&gt;stream_status[k].plane_count; m++) {</div><div class='ctx'> 			bundle-&gt;surface_updates[m].surface =</div><div class='del'>-				dc_state-&gt;stream_status-&gt;plane_states[m];</div><div class='add'>+				dc_state-&gt;stream_status[k].plane_states[m];</div><div class='ctx'> 			bundle-&gt;surface_updates[m].surface-&gt;force_full_update =</div><div class='ctx'> 				true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		update_planes_and_stream_adapter(dm-&gt;dc,</div><div class='ctx'> 					 UPDATE_TYPE_FULL,</div><div class='del'>-					 dc_state-&gt;stream_status-&gt;plane_count,</div><div class='add'>+					 dc_state-&gt;stream_status[k].plane_count,</div><div class='ctx'> 					 dc_state-&gt;streams[k],</div><div class='ctx'> 					 &amp;bundle-&gt;stream_update,</div><div class='ctx'> 					 bundle-&gt;surface_updates);</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-cleanup:</div><div class='del'>-	kfree(bundle);</div><div class='add'>+static void apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev,</div><div class='add'>+					    struct dc_sink *sink)</div><div class='add'>+{</div><div class='add'>+	struct dc_panel_patch *ppatch = NULL;</div><div class='add'>+</div><div class='add'>+	if (!sink)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ppatch = &amp;sink-&gt;edid_caps.panel_patch;</div><div class='add'>+	if (ppatch-&gt;wait_after_dpcd_poweroff_ms) {</div><div class='add'>+		msleep(ppatch-&gt;wait_after_dpcd_poweroff_ms);</div><div class='add'>+		drm_dbg_driver(adev_to_drm(adev),</div><div class='add'>+			       "%s: adding a %ds delay as w/a for panel\n",</div><div class='add'>+			       __func__,</div><div class='add'>+			       ppatch-&gt;wait_after_dpcd_poweroff_ms / 1000);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks</div><div class='add'>+ * @adev: amdgpu device pointer</div><div class='add'>+ *</div><div class='add'>+ * Iterates through all DC links and dumps information about local and remote</div><div class='add'>+ * (MST) sinks. Should be called after connector detection is complete to see</div><div class='add'>+ * the final state of all links.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = adev-&gt;dm.dc;</div><div class='add'>+	struct drm_device *dev = adev_to_drm(adev);</div><div class='add'>+	int li;</div><div class='add'>+</div><div class='add'>+	if (!dc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (li = 0; li &lt; dc-&gt;link_count; li++) {</div><div class='add'>+		struct dc_link *l = dc-&gt;links[li];</div><div class='add'>+		const char *name = NULL;</div><div class='add'>+		int rs;</div><div class='add'>+</div><div class='add'>+		if (!l)</div><div class='add'>+			continue;</div><div class='add'>+		if (l-&gt;local_sink &amp;&amp; l-&gt;local_sink-&gt;edid_caps.display_name[0])</div><div class='add'>+			name = l-&gt;local_sink-&gt;edid_caps.display_name;</div><div class='add'>+		else</div><div class='add'>+			name = "n/a";</div><div class='add'>+</div><div class='add'>+		drm_dbg_kms(dev,</div><div class='add'>+			"LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n",</div><div class='add'>+			li,</div><div class='add'>+			l-&gt;local_sink,</div><div class='add'>+			l-&gt;type,</div><div class='add'>+			l-&gt;local_sink ? l-&gt;local_sink-&gt;sink_signal : SIGNAL_TYPE_NONE,</div><div class='add'>+			l-&gt;sink_count,</div><div class='add'>+			name,</div><div class='add'>+			l-&gt;dpcd_caps.is_mst_capable,</div><div class='add'>+			l-&gt;mst_stream_alloc_table.stream_count);</div><div class='add'>+</div><div class='add'>+		/* Dump remote (MST) sinks if any */</div><div class='add'>+		for (rs = 0; rs &lt; l-&gt;sink_count; rs++) {</div><div class='add'>+			struct dc_sink *rsink = l-&gt;remote_sinks[rs];</div><div class='add'>+			const char *rname = NULL;</div><div class='add'>+</div><div class='add'>+			if (!rsink)</div><div class='add'>+				continue;</div><div class='add'>+			if (rsink-&gt;edid_caps.display_name[0])</div><div class='add'>+				rname = rsink-&gt;edid_caps.display_name;</div><div class='add'>+			else</div><div class='add'>+				rname = "n/a";</div><div class='add'>+			drm_dbg_kms(dev,</div><div class='add'>+				"  REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n",</div><div class='add'>+				li, rs,</div><div class='add'>+				rsink,</div><div class='add'>+				rsink-&gt;sink_signal,</div><div class='add'>+				rname);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_resume(void *handle)</div><div class='add'>+static int dm_resume(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct drm_device *ddev = adev_to_drm(adev);</div><div class='ctx'> 	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	struct drm_connector_list_iter iter;</div><div class='del'>-	struct drm_crtc *crtc;</div><div class='del'>-	struct drm_crtc_state *new_crtc_state;</div><div class='del'>-	struct dm_crtc_state *dm_new_crtc_state;</div><div class='del'>-	struct drm_plane *plane;</div><div class='del'>-	struct drm_plane_state *new_plane_state;</div><div class='del'>-	struct dm_plane_state *dm_new_plane_state;</div><div class='ctx'> 	struct dm_atomic_state *dm_state = to_dm_atomic_state(dm-&gt;atomic_obj.state);</div><div class='ctx'> 	enum dc_connection_type new_connection_type = dc_connection_none;</div><div class='ctx'> 	struct dc_state *dc_state;</div><div class='del'>-	int i, r, j, ret;</div><div class='del'>-	bool need_hotplug = false;</div><div class='add'>+	int i, r, j;</div><div class='add'>+	struct dc_commit_streams_params commit_params = {};</div><div class='ctx'> </div><div class='ctx'> 	if (dm-&gt;dc-&gt;caps.ips_support) {</div><div class='ctx'> 		dc_dmub_srv_apply_idle_power_optimizations(dm-&gt;dc, false);</div><div class='hunk'>@@ -2900,8 +3492,10 @@ static int dm_resume(void *handle)</div><div class='ctx'> 		link_enc_cfg_copy(adev-&gt;dm.dc-&gt;current_state, dc_state);</div><div class='ctx'> </div><div class='ctx'> 		r = dm_dmub_hw_init(adev);</div><div class='del'>-		if (r)</div><div class='del'>-			DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);</div><div class='add'>+		if (r) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		dc_dmub_srv_set_power_state(dm-&gt;dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D0);</div><div class='ctx'> 		dc_set_power_state(dm-&gt;dc, DC_ACPI_CM_POWER_STATE_D0);</div><div class='hunk'>@@ -2923,7 +3517,10 @@ static int dm_resume(void *handle)</div><div class='ctx'> 			dc_enable_dmub_outbox(adev-&gt;dm.dc);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		WARN_ON(!dc_commit_streams(dm-&gt;dc, dc_state-&gt;streams, dc_state-&gt;stream_count));</div><div class='add'>+		commit_params.streams = dc_state-&gt;streams;</div><div class='add'>+		commit_params.stream_count = dc_state-&gt;stream_count;</div><div class='add'>+		dc_exit_ips_for_hw_access(dm-&gt;dc);</div><div class='add'>+		WARN_ON(!dc_commit_streams(dm-&gt;dc, &amp;commit_params));</div><div class='ctx'> </div><div class='ctx'> 		dm_gpureset_commit_state(dm-&gt;cached_dc_state, dm);</div><div class='ctx'> </div><div class='hunk'>@@ -2936,11 +3533,17 @@ static int dm_resume(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> </div><div class='add'>+		/* set the backlight after a reset */</div><div class='add'>+		for (i = 0; i &lt; dm-&gt;num_of_edps; i++) {</div><div class='add'>+			if (dm-&gt;backlight_dev[i])</div><div class='add'>+				amdgpu_dm_backlight_set_level(dm, i, dm-&gt;brightness[i]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Recreate dc_state - DC invalidates it when setting power state to S3. */</div><div class='ctx'> 	dc_state_release(dm_state-&gt;context);</div><div class='del'>-	dm_state-&gt;context = dc_state_create(dm-&gt;dc);</div><div class='add'>+	dm_state-&gt;context = dc_state_create(dm-&gt;dc, NULL);</div><div class='ctx'> 	/* TODO: Remove dc_state-&gt;dccg, use dc-&gt;dccg directly. */</div><div class='ctx'> </div><div class='ctx'> 	/* Before powering on DC we need to re-initialize DMUB. */</div><div class='hunk'>@@ -2965,12 +3568,15 @@ static int dm_resume(void *handle)</div><div class='ctx'> 	 */</div><div class='ctx'> 	amdgpu_dm_irq_resume_early(adev);</div><div class='ctx'> </div><div class='add'>+	s3_handle_hdmi_cec(ddev, false);</div><div class='add'>+</div><div class='ctx'> 	/* On resume we need to rewrite the MSTM control bits to enable MST*/</div><div class='ctx'> 	s3_handle_mst(ddev, false);</div><div class='ctx'> </div><div class='ctx'> 	/* Do detection*/</div><div class='ctx'> 	drm_connector_list_iter_begin(ddev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+		bool ret;</div><div class='ctx'> </div><div class='ctx'> 		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -2984,19 +3590,23 @@ static int dm_resume(void *handle)</div><div class='ctx'> 		 * this is the case when traversing through already created end sink</div><div class='ctx'> 		 * MST connectors, should be skipped</div><div class='ctx'> 		 */</div><div class='del'>-		if (aconnector &amp;&amp; aconnector-&gt;mst_root)</div><div class='add'>+		if (aconnector-&gt;mst_root)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		mutex_lock(&amp;aconnector-&gt;hpd_lock);</div><div class='add'>+		guard(mutex)(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> 		if (!dc_link_detect_connection_type(aconnector-&gt;dc_link, &amp;new_connection_type))</div><div class='del'>-			DRM_ERROR("KMS: Failed to detect connector\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;base.force &amp;&amp; new_connection_type == dc_connection_none) {</div><div class='ctx'> 			emulated_link_detect(aconnector-&gt;dc_link);</div><div class='ctx'> 		} else {</div><div class='del'>-			mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='del'>-			dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_HPD);</div><div class='del'>-			mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='add'>+			guard(mutex)(&amp;dm-&gt;dc_lock);</div><div class='add'>+			dc_exit_ips_for_hw_access(dm-&gt;dc);</div><div class='add'>+			ret = dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_RESUMEFROMS3S4);</div><div class='add'>+			if (ret) {</div><div class='add'>+				/* w/a delay for certain panels */</div><div class='add'>+				apply_delay_after_dpcd_poweroff(adev, aconnector-&gt;dc_sink);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;fake_enable &amp;&amp; aconnector-&gt;dc_link-&gt;local_sink)</div><div class='hunk'>@@ -3006,66 +3616,47 @@ static int dm_resume(void *handle)</div><div class='ctx'> 			dc_sink_release(aconnector-&gt;dc_sink);</div><div class='ctx'> 		aconnector-&gt;dc_sink = NULL;</div><div class='ctx'> 		amdgpu_dm_update_connector_after_detect(aconnector);</div><div class='del'>-		mutex_unlock(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	drm_connector_list_iter_end(&amp;iter);</div><div class='ctx'> </div><div class='del'>-	/* Force mode set in atomic commit */</div><div class='del'>-	for_each_new_crtc_in_state(dm-&gt;cached_state, crtc, new_crtc_state, i)</div><div class='del'>-		new_crtc_state-&gt;active_changed = true;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * atomic_check is expected to create the dc states. We need to release</div><div class='del'>-	 * them here, since they were duplicated as part of the suspend</div><div class='del'>-	 * procedure.</div><div class='del'>-	 */</div><div class='del'>-	for_each_new_crtc_in_state(dm-&gt;cached_state, crtc, new_crtc_state, i) {</div><div class='del'>-		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='del'>-		if (dm_new_crtc_state-&gt;stream) {</div><div class='del'>-			WARN_ON(kref_read(&amp;dm_new_crtc_state-&gt;stream-&gt;refcount) &gt; 1);</div><div class='del'>-			dc_stream_release(dm_new_crtc_state-&gt;stream);</div><div class='del'>-			dm_new_crtc_state-&gt;stream = NULL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for_each_new_plane_in_state(dm-&gt;cached_state, plane, new_plane_state, i) {</div><div class='del'>-		dm_new_plane_state = to_dm_plane_state(new_plane_state);</div><div class='del'>-		if (dm_new_plane_state-&gt;dc_state) {</div><div class='del'>-			WARN_ON(kref_read(&amp;dm_new_plane_state-&gt;dc_state-&gt;refcount) &gt; 1);</div><div class='del'>-			dc_plane_state_release(dm_new_plane_state-&gt;dc_state);</div><div class='del'>-			dm_new_plane_state-&gt;dc_state = NULL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	drm_atomic_helper_resume(ddev, dm-&gt;cached_state);</div><div class='del'>-</div><div class='del'>-	dm-&gt;cached_state = NULL;</div><div class='add'>+	dm_destroy_cached_state(adev);</div><div class='ctx'> </div><div class='ctx'> 	/* Do mst topology probing after resuming cached state*/</div><div class='ctx'> 	drm_connector_list_iter_begin(ddev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+		bool init = false;</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (aconnector-&gt;dc_link-&gt;type != dc_connection_mst_branch ||</div><div class='ctx'> 		    aconnector-&gt;mst_root)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		ret = drm_dp_mst_topology_mgr_resume(&amp;aconnector-&gt;mst_mgr, true);</div><div class='del'>-</div><div class='del'>-		if (ret &lt; 0) {</div><div class='del'>-			dm_helpers_dp_mst_stop_top_mgr(aconnector-&gt;dc_link-&gt;ctx,</div><div class='del'>-					aconnector-&gt;dc_link);</div><div class='del'>-			need_hotplug = true;</div><div class='add'>+		scoped_guard(mutex, &amp;aconnector-&gt;mst_mgr.lock) {</div><div class='add'>+			init = !aconnector-&gt;mst_mgr.mst_primary;</div><div class='ctx'> 		}</div><div class='add'>+		if (init)</div><div class='add'>+			dm_helpers_dp_mst_start_top_mgr(aconnector-&gt;dc_link-&gt;ctx,</div><div class='add'>+				aconnector-&gt;dc_link, false);</div><div class='add'>+		else</div><div class='add'>+			drm_dp_mst_topology_queue_probe(&amp;aconnector-&gt;mst_mgr);</div><div class='ctx'> 	}</div><div class='ctx'> 	drm_connector_list_iter_end(&amp;iter);</div><div class='ctx'> </div><div class='del'>-	if (need_hotplug)</div><div class='del'>-		drm_kms_helper_hotplug_event(ddev);</div><div class='add'>+	/* Debug dump: list all DC links and their associated sinks after detection</div><div class='add'>+	 * is complete for all connectors. This provides a comprehensive view of the</div><div class='add'>+	 * final state without repeating the dump for each connector.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_dm_dump_links_and_sinks(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_irq_resume_late(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_smu_write_watermarks_table(adev);</div><div class='ctx'> </div><div class='add'>+	drm_kms_helper_hotplug_event(ddev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3122,22 +3713,25 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {</div><div class='ctx'> </div><div class='ctx'> static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {</div><div class='ctx'> 	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail,</div><div class='del'>-	.atomic_commit_setup = drm_dp_mst_atomic_setup_commit,</div><div class='add'>+	.atomic_commit_setup = amdgpu_dm_atomic_setup_commit,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> {</div><div class='add'>+	const struct drm_panel_backlight_quirk *panel_backlight_quirk;</div><div class='ctx'> 	struct amdgpu_dm_backlight_caps *caps;</div><div class='ctx'> 	struct drm_connector *conn_base;</div><div class='ctx'> 	struct amdgpu_device *adev;</div><div class='ctx'> 	struct drm_luminance_range_info *luminance_range;</div><div class='add'>+	struct drm_device *drm;</div><div class='ctx'> </div><div class='ctx'> 	if (aconnector-&gt;bl_idx == -1 ||</div><div class='ctx'> 	    aconnector-&gt;dc_link-&gt;connector_signal != SIGNAL_TYPE_EDP)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	conn_base = &amp;aconnector-&gt;base;</div><div class='del'>-	adev = drm_to_adev(conn_base-&gt;dev);</div><div class='add'>+	drm = conn_base-&gt;dev;</div><div class='add'>+	adev = drm_to_adev(drm);</div><div class='ctx'> </div><div class='ctx'> 	caps = &amp;adev-&gt;dm.backlight_caps[aconnector-&gt;bl_idx];</div><div class='ctx'> 	caps-&gt;ext_caps = &amp;aconnector-&gt;dc_link-&gt;dpcd_sink_ext_caps;</div><div class='hunk'>@@ -3155,24 +3749,49 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 		caps-&gt;aux_support = false;</div><div class='ctx'> 	else if (amdgpu_backlight == 1)</div><div class='ctx'> 		caps-&gt;aux_support = true;</div><div class='add'>+	if (caps-&gt;aux_support)</div><div class='add'>+		aconnector-&gt;dc_link-&gt;backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX;</div><div class='ctx'> </div><div class='ctx'> 	luminance_range = &amp;conn_base-&gt;display_info.luminance_range;</div><div class='ctx'> </div><div class='del'>-	if (luminance_range-&gt;max_luminance) {</div><div class='del'>-		caps-&gt;aux_min_input_signal = luminance_range-&gt;min_luminance;</div><div class='add'>+	if (luminance_range-&gt;max_luminance)</div><div class='ctx'> 		caps-&gt;aux_max_input_signal = luminance_range-&gt;max_luminance;</div><div class='del'>-	} else {</div><div class='del'>-		caps-&gt;aux_min_input_signal = 0;</div><div class='add'>+	else</div><div class='ctx'> 		caps-&gt;aux_max_input_signal = 512;</div><div class='add'>+</div><div class='add'>+	if (luminance_range-&gt;min_luminance)</div><div class='add'>+		caps-&gt;aux_min_input_signal = luminance_range-&gt;min_luminance;</div><div class='add'>+	else</div><div class='add'>+		caps-&gt;aux_min_input_signal = 1;</div><div class='add'>+</div><div class='add'>+	panel_backlight_quirk =</div><div class='add'>+		drm_get_panel_backlight_quirk(aconnector-&gt;drm_edid);</div><div class='add'>+	if (!IS_ERR_OR_NULL(panel_backlight_quirk)) {</div><div class='add'>+		if (panel_backlight_quirk-&gt;min_brightness) {</div><div class='add'>+			caps-&gt;min_input_signal =</div><div class='add'>+				panel_backlight_quirk-&gt;min_brightness - 1;</div><div class='add'>+			drm_info(drm,</div><div class='add'>+				 "Applying panel backlight quirk, min_brightness: %d\n",</div><div class='add'>+				 caps-&gt;min_input_signal);</div><div class='add'>+		}</div><div class='add'>+		if (panel_backlight_quirk-&gt;brightness_mask) {</div><div class='add'>+			drm_info(drm,</div><div class='add'>+				 "Applying panel backlight quirk, brightness_mask: 0x%X\n",</div><div class='add'>+				 panel_backlight_quirk-&gt;brightness_mask);</div><div class='add'>+			caps-&gt;brightness_mask =</div><div class='add'>+				panel_backlight_quirk-&gt;brightness_mask;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T))</div><div class='add'>+</div><div class='ctx'> void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 		struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct dc_sink *sink __free(sink_release) = NULL;</div><div class='ctx'> 	struct drm_device *dev = connector-&gt;dev;</div><div class='del'>-	struct dc_sink *sink;</div><div class='ctx'> </div><div class='ctx'> 	/* MST handled by drm_mst framework */</div><div class='ctx'> 	if (aconnector-&gt;mst_mgr.mst_state == true)</div><div class='hunk'>@@ -3194,7 +3813,7 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 		 * For S3 resume with headless use eml_sink to fake stream</div><div class='ctx'> 		 * because on resume connector-&gt;sink is set to NULL</div><div class='ctx'> 		 */</div><div class='del'>-		mutex_lock(&amp;dev-&gt;mode_config.mutex);</div><div class='add'>+		guard(mutex)(&amp;dev-&gt;mode_config.mutex);</div><div class='ctx'> </div><div class='ctx'> 		if (sink) {</div><div class='ctx'> 			if (aconnector-&gt;dc_sink) {</div><div class='hunk'>@@ -3210,7 +3829,7 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 			aconnector-&gt;dc_sink = sink;</div><div class='ctx'> 			dc_sink_retain(aconnector-&gt;dc_sink);</div><div class='ctx'> 			amdgpu_dm_update_freesync_caps(connector,</div><div class='del'>-					aconnector-&gt;edid);</div><div class='add'>+					aconnector-&gt;drm_edid);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			amdgpu_dm_update_freesync_caps(connector, NULL);</div><div class='ctx'> 			if (!aconnector-&gt;dc_sink) {</div><div class='hunk'>@@ -3219,10 +3838,6 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		mutex_unlock(&amp;dev-&gt;mode_config.mutex);</div><div class='del'>-</div><div class='del'>-		if (sink)</div><div class='del'>-			dc_sink_release(sink);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3230,27 +3845,25 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 	 * TODO: temporary guard to look for proper fix</div><div class='ctx'> 	 * if this sink is MST sink, we should not do anything</div><div class='ctx'> 	 */</div><div class='del'>-	if (sink &amp;&amp; sink-&gt;sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='del'>-		dc_sink_release(sink);</div><div class='add'>+	if (sink &amp;&amp; sink-&gt;sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 		return;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (aconnector-&gt;dc_sink == sink) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * We got a DP short pulse (Link Loss, DP CTS, etc...).</div><div class='ctx'> 		 * Do nothing!!</div><div class='ctx'> 		 */</div><div class='del'>-		DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",</div><div class='del'>-				aconnector-&gt;connector_id);</div><div class='del'>-		if (sink)</div><div class='del'>-			dc_sink_release(sink);</div><div class='add'>+		drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n",</div><div class='add'>+				 aconnector-&gt;connector_id);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",</div><div class='del'>-		aconnector-&gt;connector_id, aconnector-&gt;dc_sink, sink);</div><div class='add'>+	drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",</div><div class='add'>+		    aconnector-&gt;connector_id, aconnector-&gt;dc_sink, sink);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;dev-&gt;mode_config.mutex);</div><div class='add'>+	/* When polling, DRM has already locked the mutex for us. */</div><div class='add'>+	if (!drm_kms_helper_is_poll_worker())</div><div class='add'>+		mutex_lock(&amp;dev-&gt;mode_config.mutex);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * 1. Update status of the drm connector</div><div class='hunk'>@@ -3269,18 +3882,21 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 		aconnector-&gt;dc_sink = sink;</div><div class='ctx'> 		dc_sink_retain(aconnector-&gt;dc_sink);</div><div class='ctx'> 		if (sink-&gt;dc_edid.length == 0) {</div><div class='del'>-			aconnector-&gt;edid = NULL;</div><div class='add'>+			aconnector-&gt;drm_edid = NULL;</div><div class='add'>+			hdmi_cec_unset_edid(aconnector);</div><div class='ctx'> 			if (aconnector-&gt;dc_link-&gt;aux_mode) {</div><div class='del'>-				drm_dp_cec_unset_edid(</div><div class='del'>-					&amp;aconnector-&gt;dm_dp_aux.aux);</div><div class='add'>+				drm_dp_cec_unset_edid(&amp;aconnector-&gt;dm_dp_aux.aux);</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			aconnector-&gt;edid =</div><div class='del'>-				(struct edid *)sink-&gt;dc_edid.raw_edid;</div><div class='add'>+			const struct edid *edid = (const struct edid *)sink-&gt;dc_edid.raw_edid;</div><div class='add'>+</div><div class='add'>+			aconnector-&gt;drm_edid = drm_edid_alloc(edid, sink-&gt;dc_edid.length);</div><div class='add'>+			drm_edid_connector_update(connector, aconnector-&gt;drm_edid);</div><div class='ctx'> </div><div class='add'>+			hdmi_cec_set_edid(aconnector);</div><div class='ctx'> 			if (aconnector-&gt;dc_link-&gt;aux_mode)</div><div class='del'>-				drm_dp_cec_set_edid(&amp;aconnector-&gt;dm_dp_aux.aux,</div><div class='del'>-						    aconnector-&gt;edid);</div><div class='add'>+				drm_dp_cec_attach(&amp;aconnector-&gt;dm_dp_aux.aux,</div><div class='add'>+						  connector-&gt;display_info.source_physical_address);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (!aconnector-&gt;timing_requested) {</div><div class='hunk'>@@ -3291,17 +3907,17 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 					"failed to create aconnector-&gt;requested_timing\n");</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		drm_connector_update_edid_property(connector, aconnector-&gt;edid);</div><div class='del'>-		amdgpu_dm_update_freesync_caps(connector, aconnector-&gt;edid);</div><div class='add'>+		amdgpu_dm_update_freesync_caps(connector, aconnector-&gt;drm_edid);</div><div class='ctx'> 		update_connector_ext_caps(aconnector);</div><div class='ctx'> 	} else {</div><div class='add'>+		hdmi_cec_unset_edid(aconnector);</div><div class='ctx'> 		drm_dp_cec_unset_edid(&amp;aconnector-&gt;dm_dp_aux.aux);</div><div class='ctx'> 		amdgpu_dm_update_freesync_caps(connector, NULL);</div><div class='del'>-		drm_connector_update_edid_property(connector, NULL);</div><div class='ctx'> 		aconnector-&gt;num_modes = 0;</div><div class='ctx'> 		dc_sink_release(aconnector-&gt;dc_sink);</div><div class='ctx'> 		aconnector-&gt;dc_sink = NULL;</div><div class='del'>-		aconnector-&gt;edid = NULL;</div><div class='add'>+		drm_edid_free(aconnector-&gt;drm_edid);</div><div class='add'>+		aconnector-&gt;drm_edid = NULL;</div><div class='ctx'> 		kfree(aconnector-&gt;timing_requested);</div><div class='ctx'> 		aconnector-&gt;timing_requested = NULL;</div><div class='ctx'> 		/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */</div><div class='hunk'>@@ -3309,12 +3925,102 @@ void amdgpu_dm_update_connector_after_detect(</div><div class='ctx'> 			connector-&gt;state-&gt;content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;dev-&gt;mode_config.mutex);</div><div class='del'>-</div><div class='ctx'> 	update_subconnector_property(aconnector);</div><div class='ctx'> </div><div class='del'>-	if (sink)</div><div class='del'>-		dc_sink_release(sink);</div><div class='add'>+	/* When polling, the mutex will be unlocked for us by DRM. */</div><div class='add'>+	if (!drm_kms_helper_is_poll_worker())</div><div class='add'>+		mutex_unlock(&amp;dev-&gt;mode_config.mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool are_sinks_equal(const struct dc_sink *sink1, const struct dc_sink *sink2)</div><div class='add'>+{</div><div class='add'>+	if (!sink1 || !sink2)</div><div class='add'>+		return false;</div><div class='add'>+	if (sink1-&gt;sink_signal != sink2-&gt;sink_signal)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (sink1-&gt;dc_edid.length != sink2-&gt;dc_edid.length)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (memcmp(sink1-&gt;dc_edid.raw_edid, sink2-&gt;dc_edid.raw_edid,</div><div class='add'>+		   sink1-&gt;dc_edid.length) != 0)</div><div class='add'>+		return false;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: hdmi_hpd_debounce_work</div><div class='add'>+ *</div><div class='add'>+ * HDMI HPD debounce delay in milliseconds. When an HDMI display toggles HPD</div><div class='add'>+ * (such as during power save transitions), this delay determines how long to</div><div class='add'>+ * wait before processing the HPD event. This allows distinguishing between a</div><div class='add'>+ * physical unplug (&gt;hdmi_hpd_debounce_delay)</div><div class='add'>+ * and a spontaneous RX HPD toggle (&lt;hdmi_hpd_debounce_delay).</div><div class='add'>+ *</div><div class='add'>+ * If the toggle is less than this delay, the driver compares sink capabilities</div><div class='add'>+ * and permits a hotplug event if they changed.</div><div class='add'>+ *</div><div class='add'>+ * The default value of 1500ms was chosen based on experimental testing with</div><div class='add'>+ * various monitors that exhibit spontaneous HPD toggling behavior.</div><div class='add'>+ */</div><div class='add'>+static void hdmi_hpd_debounce_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *aconnector =</div><div class='add'>+		container_of(to_delayed_work(work), struct amdgpu_dm_connector,</div><div class='add'>+			     hdmi_hpd_debounce_work);</div><div class='add'>+	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct dc *dc = aconnector-&gt;dc_link-&gt;ctx-&gt;dc;</div><div class='add'>+	bool fake_reconnect = false;</div><div class='add'>+	bool reallow_idle = false;</div><div class='add'>+	bool ret = false;</div><div class='add'>+	guard(mutex)(&amp;aconnector-&gt;hpd_lock);</div><div class='add'>+</div><div class='add'>+	/* Re-detect the display */</div><div class='add'>+	scoped_guard(mutex, &amp;adev-&gt;dm.dc_lock) {</div><div class='add'>+		if (dc-&gt;caps.ips_support &amp;&amp; dc-&gt;ctx-&gt;dmub_srv-&gt;idle_allowed) {</div><div class='add'>+			dc_allow_idle_optimizations(dc, false);</div><div class='add'>+			reallow_idle = true;</div><div class='add'>+		}</div><div class='add'>+		ret = dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_HPD);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret) {</div><div class='add'>+		/* Apply workaround delay for certain panels */</div><div class='add'>+		apply_delay_after_dpcd_poweroff(adev, aconnector-&gt;dc_sink);</div><div class='add'>+		/* Compare sinks to determine if this was a spontaneous HPD toggle */</div><div class='add'>+		if (are_sinks_equal(aconnector-&gt;dc_link-&gt;local_sink, aconnector-&gt;hdmi_prev_sink)) {</div><div class='add'>+			/*</div><div class='add'>+			* Sinks match - this was a spontaneous HDMI HPD toggle.</div><div class='add'>+			*/</div><div class='add'>+			drm_dbg_kms(dev, "HDMI HPD: Sink unchanged after debounce, internal re-enable\n");</div><div class='add'>+			fake_reconnect = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Update connector state */</div><div class='add'>+		amdgpu_dm_update_connector_after_detect(aconnector);</div><div class='add'>+</div><div class='add'>+		drm_modeset_lock_all(dev);</div><div class='add'>+		dm_restore_drm_connector_state(dev, connector);</div><div class='add'>+		drm_modeset_unlock_all(dev);</div><div class='add'>+</div><div class='add'>+		/* Only notify OS if sink actually changed */</div><div class='add'>+		if (!fake_reconnect &amp;&amp; aconnector-&gt;base.force == DRM_FORCE_UNSPECIFIED)</div><div class='add'>+			drm_kms_helper_hotplug_event(dev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Release the cached sink reference */</div><div class='add'>+	if (aconnector-&gt;hdmi_prev_sink) {</div><div class='add'>+		dc_sink_release(aconnector-&gt;hdmi_prev_sink);</div><div class='add'>+		aconnector-&gt;hdmi_prev_sink = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;adev-&gt;dm.dc_lock) {</div><div class='add'>+		if (reallow_idle &amp;&amp; dc-&gt;caps.ips_support)</div><div class='add'>+			dc_allow_idle_optimizations(dc, true);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)</div><div class='hunk'>@@ -3324,7 +4030,9 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 	enum dc_connection_type new_connection_type = dc_connection_none;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='ctx'> 	struct dm_connector_state *dm_con_state = to_dm_connector_state(connector-&gt;state);</div><div class='add'>+	struct dc *dc = aconnector-&gt;dc_link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	bool ret = false;</div><div class='add'>+	bool debounce_required = false;</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;dm.disable_hpd_irq)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -3333,7 +4041,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 	 * In case of failure or MST no need to update connector status or notify the OS</div><div class='ctx'> 	 * since (for MST case) MST does this in its own context.</div><div class='ctx'> 	 */</div><div class='del'>-	mutex_lock(&amp;aconnector-&gt;hpd_lock);</div><div class='add'>+	guard(mutex)(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;dm.hdcp_workqueue) {</div><div class='ctx'> 		hdcp_reset_display(adev-&gt;dm.hdcp_workqueue, aconnector-&gt;dc_link-&gt;link_index);</div><div class='hunk'>@@ -3345,7 +4053,15 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 	aconnector-&gt;timing_changed = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_link_detect_connection_type(aconnector-&gt;dc_link, &amp;new_connection_type))</div><div class='del'>-		DRM_ERROR("KMS: Failed to detect connector\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check for HDMI disconnect with debounce enabled.</div><div class='add'>+	 */</div><div class='add'>+	debounce_required = (aconnector-&gt;hdmi_hpd_debounce_delay_ms &gt; 0 &amp;&amp;</div><div class='add'>+			      dc_is_hdmi_signal(aconnector-&gt;dc_link-&gt;connector_signal) &amp;&amp;</div><div class='add'>+			      new_connection_type == dc_connection_none &amp;&amp;</div><div class='add'>+			      aconnector-&gt;dc_link-&gt;local_sink != NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (aconnector-&gt;base.force &amp;&amp; new_connection_type == dc_connection_none) {</div><div class='ctx'> 		emulated_link_detect(aconnector-&gt;dc_link);</div><div class='hunk'>@@ -3356,11 +4072,41 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;base.force == DRM_FORCE_UNSPECIFIED)</div><div class='ctx'> 			drm_kms_helper_connector_hotplug_event(connector);</div><div class='add'>+	} else if (debounce_required) {</div><div class='add'>+		/*</div><div class='add'>+		 * HDMI disconnect detected - schedule delayed work instead of</div><div class='add'>+		 * processing immediately. This allows us to coalesce spurious</div><div class='add'>+		 * HDMI signals from physical unplugs.</div><div class='add'>+		 */</div><div class='add'>+		drm_dbg_kms(dev, "HDMI HPD: Disconnect detected, scheduling debounce work (%u ms)\n",</div><div class='add'>+			    aconnector-&gt;hdmi_hpd_debounce_delay_ms);</div><div class='add'>+</div><div class='add'>+		/* Cache the current sink for later comparison */</div><div class='add'>+		if (aconnector-&gt;hdmi_prev_sink)</div><div class='add'>+			dc_sink_release(aconnector-&gt;hdmi_prev_sink);</div><div class='add'>+		aconnector-&gt;hdmi_prev_sink = aconnector-&gt;dc_link-&gt;local_sink;</div><div class='add'>+		if (aconnector-&gt;hdmi_prev_sink)</div><div class='add'>+			dc_sink_retain(aconnector-&gt;hdmi_prev_sink);</div><div class='add'>+</div><div class='add'>+		/* Schedule delayed detection. */</div><div class='add'>+		if (mod_delayed_work(system_wq,</div><div class='add'>+				 &amp;aconnector-&gt;hdmi_hpd_debounce_work,</div><div class='add'>+				 msecs_to_jiffies(aconnector-&gt;hdmi_hpd_debounce_delay_ms)))</div><div class='add'>+			drm_dbg_kms(dev, "HDMI HPD: Re-scheduled debounce work\n");</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='del'>-		mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='del'>-		ret = dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_HPD);</div><div class='del'>-		mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='add'>+</div><div class='add'>+		/* If the aconnector-&gt;hdmi_hpd_debounce_work is scheduled, exit early */</div><div class='add'>+		if (delayed_work_pending(&amp;aconnector-&gt;hdmi_hpd_debounce_work))</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		scoped_guard(mutex, &amp;adev-&gt;dm.dc_lock) {</div><div class='add'>+			dc_exit_ips_for_hw_access(dc);</div><div class='add'>+			ret = dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_HPD);</div><div class='add'>+		}</div><div class='ctx'> 		if (ret) {</div><div class='add'>+			/* w/a delay for certain panels */</div><div class='add'>+			apply_delay_after_dpcd_poweroff(adev, aconnector-&gt;dc_sink);</div><div class='ctx'> 			amdgpu_dm_update_connector_after_detect(aconnector);</div><div class='ctx'> </div><div class='ctx'> 			drm_modeset_lock_all(dev);</div><div class='hunk'>@@ -3371,8 +4117,6 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 				drm_kms_helper_connector_hotplug_event(connector);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	mutex_unlock(&amp;aconnector-&gt;hpd_lock);</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void handle_hpd_irq(void *param)</div><div class='hunk'>@@ -3383,20 +4127,21 @@ static void handle_hpd_irq(void *param)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,</div><div class='add'>+static void schedule_hpd_rx_offload_work(struct amdgpu_device *adev, struct hpd_rx_irq_offload_work_queue *offload_wq,</div><div class='ctx'> 							union hpd_irq_data hpd_irq_data)</div><div class='ctx'> {</div><div class='ctx'> 	struct hpd_rx_irq_offload_work *offload_work =</div><div class='ctx'> 				kzalloc(sizeof(*offload_work), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!offload_work) {</div><div class='del'>-		DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to allocate hpd_rx_irq_offload_work.\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	INIT_WORK(&amp;offload_work-&gt;work, dm_handle_hpd_rx_offload_work);</div><div class='ctx'> 	offload_work-&gt;data = hpd_irq_data;</div><div class='ctx'> 	offload_work-&gt;offload_wq = offload_wq;</div><div class='add'>+	offload_work-&gt;adev = adev;</div><div class='ctx'> </div><div class='ctx'> 	queue_work(offload_wq-&gt;wq, &amp;offload_work-&gt;work);</div><div class='ctx'> 	DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");</div><div class='hunk'>@@ -3417,6 +4162,7 @@ static void handle_hpd_rx_irq(void *param)</div><div class='ctx'> 	bool has_left_work = false;</div><div class='ctx'> 	int idx = dc_link-&gt;link_index;</div><div class='ctx'> 	struct hpd_rx_irq_offload_work_queue *offload_wq = &amp;adev-&gt;dm.hpd_rx_offload_wq[idx];</div><div class='add'>+	struct dc *dc = aconnector-&gt;dc_link-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;hpd_irq_data, 0, sizeof(hpd_irq_data));</div><div class='ctx'> </div><div class='hunk'>@@ -3437,7 +4183,7 @@ static void handle_hpd_rx_irq(void *param)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {</div><div class='del'>-		schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);</div><div class='add'>+		schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data);</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3459,7 +4205,7 @@ static void handle_hpd_rx_irq(void *param)</div><div class='ctx'> 			spin_unlock(&amp;offload_wq-&gt;offload_lock);</div><div class='ctx'> </div><div class='ctx'> 			if (!skip)</div><div class='del'>-				schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);</div><div class='add'>+				schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data);</div><div class='ctx'> </div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3476,7 +4222,7 @@ static void handle_hpd_rx_irq(void *param)</div><div class='ctx'> 			spin_unlock(&amp;offload_wq-&gt;offload_lock);</div><div class='ctx'> </div><div class='ctx'> 			if (!skip)</div><div class='del'>-				schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);</div><div class='add'>+				schedule_hpd_rx_offload_work(adev, offload_wq, hpd_irq_data);</div><div class='ctx'> </div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3486,7 +4232,7 @@ out:</div><div class='ctx'> 	if (result &amp;&amp; !is_mst_root_connector) {</div><div class='ctx'> 		/* Downstream Port status changed. */</div><div class='ctx'> 		if (!dc_link_detect_connection_type(dc_link, &amp;new_connection_type))</div><div class='del'>-			DRM_ERROR("KMS: Failed to detect connector\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;base.force &amp;&amp; new_connection_type == dc_connection_none) {</div><div class='ctx'> 			emulated_link_detect(dc_link);</div><div class='hunk'>@@ -3506,6 +4252,7 @@ out:</div><div class='ctx'> 			bool ret = false;</div><div class='ctx'> </div><div class='ctx'> 			mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='add'>+			dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> 			ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);</div><div class='ctx'> 			mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -3534,7 +4281,7 @@ out:</div><div class='ctx'> 	mutex_unlock(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void register_hpd_handlers(struct amdgpu_device *adev)</div><div class='add'>+static int register_hpd_handlers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = adev_to_drm(adev);</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='hunk'>@@ -3546,11 +4293,23 @@ static void register_hpd_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;</div><div class='ctx'> </div><div class='ctx'> 	if (dc_is_dmub_outbox_supported(adev-&gt;dm.dc)) {</div><div class='del'>-		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true))</div><div class='del'>-			DRM_ERROR("amdgpu: fail to register dmub hpd callback");</div><div class='add'>+		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,</div><div class='add'>+			dmub_hpd_callback, true)) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "fail to register dmub hpd callback");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ,</div><div class='add'>+			dmub_hpd_callback, true)) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "fail to register dmub hpd callback");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true))</div><div class='del'>-			DRM_ERROR("amdgpu: fail to register dmub hpd callback");</div><div class='add'>+		if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY,</div><div class='add'>+			dmub_hpd_sense_callback, true)) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "fail to register dmub hpd sense callback");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(connector,</div><div class='hunk'>@@ -3566,9 +4325,16 @@ static void register_hpd_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;</div><div class='ctx'> 			int_params.irq_source = dc_link-&gt;irq_source_hpd;</div><div class='ctx'> </div><div class='del'>-			amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-					handle_hpd_irq,</div><div class='del'>-					(void *) aconnector);</div><div class='add'>+			if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+				int_params.irq_source  &lt; DC_IRQ_SOURCE_HPD1 ||</div><div class='add'>+				int_params.irq_source  &gt; DC_IRQ_SOURCE_HPD6) {</div><div class='add'>+				drm_err(adev_to_drm(adev), "Failed to register hpd irq!\n");</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+				handle_hpd_irq, (void *) aconnector))</div><div class='add'>+				return -ENOMEM;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {</div><div class='hunk'>@@ -3577,11 +4343,19 @@ static void register_hpd_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;</div><div class='ctx'> 			int_params.irq_source =	dc_link-&gt;irq_source_hpd_rx;</div><div class='ctx'> </div><div class='del'>-			amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-					handle_hpd_rx_irq,</div><div class='del'>-					(void *) aconnector);</div><div class='add'>+			if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+				int_params.irq_source  &lt; DC_IRQ_SOURCE_HPD1RX ||</div><div class='add'>+				int_params.irq_source  &gt; DC_IRQ_SOURCE_HPD6RX) {</div><div class='add'>+				drm_err(adev_to_drm(adev), "Failed to register hpd rx irq!\n");</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+				handle_hpd_rx_irq, (void *) aconnector))</div><div class='add'>+				return -ENOMEM;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_SI)</div><div class='hunk'>@@ -3614,7 +4388,7 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, client_id, i + 1, &amp;adev-&gt;crtc_irq);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add crtc irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3622,13 +4396,21 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i + 1, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_VBLANK1 ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_VBLANK6) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_crtc_high_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_crtc_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use GRPH_PFLIP interrupt */</div><div class='hunk'>@@ -3636,7 +4418,7 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 			i &lt;= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, client_id, i, &amp;adev-&gt;pageflip_irq);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add page flip irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3644,27 +4426,34 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_PFLIP_FIRST ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_PFLIP_LAST) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_pflip_high_irq, c_irq_params);</div><div class='del'>-</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_pflip_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* HPD */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, client_id,</div><div class='ctx'> 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &amp;adev-&gt;hpd_irq);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to add hpd irq id!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	register_hpd_handlers(adev);</div><div class='add'>+	r = register_hpd_handlers(adev);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -3700,7 +4489,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i &lt;= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, client_id, i, &amp;adev-&gt;crtc_irq);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add crtc irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3708,20 +4497,28 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_VBLANK1 ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_VBLANK6) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_crtc_high_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_crtc_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use VUPDATE interrupt */</div><div class='ctx'> 	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i &lt;= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, client_id, i, &amp;adev-&gt;vupdate_irq);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add vupdate irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3729,13 +4526,21 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_VUPDATE1 ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_VUPDATE6) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_vupdate_high_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_vupdate_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use GRPH_PFLIP interrupt */</div><div class='hunk'>@@ -3743,7 +4548,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 			i &lt;= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, client_id, i, &amp;adev-&gt;pageflip_irq);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add page flip irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3751,27 +4556,34 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_PFLIP_FIRST ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_PFLIP_LAST) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_pflip_high_irq, c_irq_params);</div><div class='del'>-</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_pflip_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* HPD */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, client_id,</div><div class='ctx'> 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &amp;adev-&gt;hpd_irq);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to add hpd irq id!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	register_hpd_handlers(adev);</div><div class='add'>+	r = register_hpd_handlers(adev);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Register IRQ sources and initialize IRQ callbacks */</div><div class='hunk'>@@ -3815,7 +4627,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &amp;adev-&gt;crtc_irq);</div><div class='ctx'> </div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add crtc irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3823,13 +4635,21 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_VBLANK1 ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_VBLANK6) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(</div><div class='del'>-			adev, &amp;int_params, dm_crtc_high_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_crtc_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use otg vertical line interrupt */</div><div class='hunk'>@@ -3839,7 +4659,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 				vrtl_int_srcid[i], &amp;adev-&gt;vline0_irq);</div><div class='ctx'> </div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add vline0 irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add vline0 irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3847,9 +4667,11 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);</div><div class='ctx'> </div><div class='del'>-		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {</div><div class='del'>-			DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);</div><div class='del'>-			break;</div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source &lt; DC_IRQ_SOURCE_DC1_VLINE0 ||</div><div class='add'>+			int_params.irq_source &gt; DC_IRQ_SOURCE_DC6_VLINE0) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register vline0 irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.vline0_params[int_params.irq_source</div><div class='hunk'>@@ -3858,8 +4680,10 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_dcn_vertical_interrupt0_high_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_dcn_vertical_interrupt0_high_irq,</div><div class='add'>+			c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -3874,7 +4698,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &amp;adev-&gt;vupdate_irq);</div><div class='ctx'> </div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add vupdate irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3882,13 +4706,21 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_VUPDATE1 ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_VUPDATE6) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_vupdate_high_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_vupdate_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use GRPH_PFLIP interrupt */</div><div class='hunk'>@@ -3897,7 +4729,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 			i++) {</div><div class='ctx'> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &amp;adev-&gt;pageflip_irq);</div><div class='ctx'> 		if (r) {</div><div class='del'>-			DRM_ERROR("Failed to add page flip irq id!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -3905,27 +4737,34 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		int_params.irq_source =</div><div class='ctx'> 			dc_interrupt_to_irq_source(dc, i, 0);</div><div class='ctx'> </div><div class='add'>+		if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||</div><div class='add'>+			int_params.irq_source  &lt; DC_IRQ_SOURCE_PFLIP_FIRST ||</div><div class='add'>+			int_params.irq_source  &gt; DC_IRQ_SOURCE_PFLIP_LAST) {</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		c_irq_params = &amp;adev-&gt;dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];</div><div class='ctx'> </div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_pflip_high_irq, c_irq_params);</div><div class='del'>-</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_pflip_high_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* HPD */</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,</div><div class='ctx'> 			&amp;adev-&gt;hpd_irq);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to add hpd irq id!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	register_hpd_handlers(adev);</div><div class='add'>+	r = register_hpd_handlers(adev);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return r;</div><div class='ctx'> }</div><div class='ctx'> /* Register Outbox IRQ sources and initialize IRQ callbacks */</div><div class='ctx'> static int register_outbox_irq_handlers(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3941,7 +4780,7 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,</div><div class='ctx'> 			&amp;adev-&gt;dmub_outbox_irq);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		DRM_ERROR("Failed to add outbox irq id!\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to add outbox irq id!\n");</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3956,8 +4795,9 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 		c_irq_params-&gt;adev = adev;</div><div class='ctx'> 		c_irq_params-&gt;irq_src = int_params.irq_source;</div><div class='ctx'> </div><div class='del'>-		amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='del'>-				dm_dmub_outbox1_low_irq, c_irq_params);</div><div class='add'>+		if (!amdgpu_dm_irq_register_interrupt(adev, &amp;int_params,</div><div class='add'>+			dm_dmub_outbox1_low_irq, c_irq_params))</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -4092,8 +4932,11 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> #ifdef AMD_PRIVATE_COLOR</div><div class='del'>-	if (amdgpu_dm_create_color_properties(adev))</div><div class='add'>+	if (amdgpu_dm_create_color_properties(adev)) {</div><div class='add'>+		dc_state_release(state-&gt;context);</div><div class='add'>+		kfree(state);</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_dm_audio_init(adev);</div><div class='hunk'>@@ -4108,38 +4951,46 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12</div><div class='ctx'> #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255</div><div class='add'>+#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)</div><div class='ctx'> #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,</div><div class='ctx'> 					    int bl_idx)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_dm_backlight_caps *caps = &amp;dm-&gt;backlight_caps[bl_idx];</div><div class='add'>+</div><div class='add'>+	if (caps-&gt;caps_valid)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_ACPI)</div><div class='del'>-	struct amdgpu_dm_backlight_caps caps;</div><div class='add'>+	amdgpu_acpi_get_backlight_caps(caps);</div><div class='ctx'> </div><div class='del'>-	memset(&amp;caps, 0, sizeof(caps));</div><div class='add'>+	/* validate the firmware value is sane */</div><div class='add'>+	if (caps-&gt;caps_valid) {</div><div class='add'>+		int spread = caps-&gt;max_input_signal - caps-&gt;min_input_signal;</div><div class='ctx'> </div><div class='del'>-	if (dm-&gt;backlight_caps[bl_idx].caps_valid)</div><div class='del'>-		return;</div><div class='add'>+		if (caps-&gt;max_input_signal &gt; AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||</div><div class='add'>+		    caps-&gt;min_input_signal &lt; 0 ||</div><div class='add'>+		    spread &gt; AMDGPU_DM_DEFAULT_MAX_BACKLIGHT ||</div><div class='add'>+		    spread &lt; AMDGPU_DM_MIN_SPREAD) {</div><div class='add'>+			DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n",</div><div class='add'>+				      caps-&gt;min_input_signal, caps-&gt;max_input_signal);</div><div class='add'>+			caps-&gt;caps_valid = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_acpi_get_backlight_caps(&amp;caps);</div><div class='del'>-	if (caps.caps_valid) {</div><div class='del'>-		dm-&gt;backlight_caps[bl_idx].caps_valid = true;</div><div class='del'>-		if (caps.aux_support)</div><div class='del'>-			return;</div><div class='del'>-		dm-&gt;backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;</div><div class='del'>-		dm-&gt;backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;</div><div class='del'>-	} else {</div><div class='del'>-		dm-&gt;backlight_caps[bl_idx].min_input_signal =</div><div class='del'>-				AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;</div><div class='del'>-		dm-&gt;backlight_caps[bl_idx].max_input_signal =</div><div class='del'>-				AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;</div><div class='add'>+	if (!caps-&gt;caps_valid) {</div><div class='add'>+		caps-&gt;min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;</div><div class='add'>+		caps-&gt;max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;</div><div class='add'>+		caps-&gt;caps_valid = true;</div><div class='ctx'> 	}</div><div class='ctx'> #else</div><div class='del'>-	if (dm-&gt;backlight_caps[bl_idx].aux_support)</div><div class='add'>+	if (caps-&gt;aux_support)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	dm-&gt;backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;</div><div class='del'>-	dm-&gt;backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;</div><div class='add'>+	caps-&gt;min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;</div><div class='add'>+	caps-&gt;max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;</div><div class='add'>+	caps-&gt;caps_valid = true;</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4161,6 +5012,82 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,</div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */</div><div class='add'>+static inline u32 scale_input_to_fw(int min, int max, u64 input)</div><div class='add'>+{</div><div class='add'>+	return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */</div><div class='add'>+static inline u32 scale_fw_to_input(int min, int max, u64 input)</div><div class='add'>+{</div><div class='add'>+	return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps,</div><div class='add'>+				      unsigned int min, unsigned int max,</div><div class='add'>+				      uint32_t *user_brightness)</div><div class='add'>+{</div><div class='add'>+	u32 brightness = scale_input_to_fw(min, max, *user_brightness);</div><div class='add'>+	u8 lower_signal, upper_signal, upper_lum, lower_lum, lum;</div><div class='add'>+	int left, right;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!caps-&gt;data_points)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Handle the case where brightness is below the first data point</div><div class='add'>+	 * Interpolate between (0,0) and (first_signal, first_lum)</div><div class='add'>+	 */</div><div class='add'>+	if (brightness &lt; caps-&gt;luminance_data[0].input_signal) {</div><div class='add'>+		lum = DIV_ROUND_CLOSEST(caps-&gt;luminance_data[0].luminance * brightness,</div><div class='add'>+					caps-&gt;luminance_data[0].input_signal);</div><div class='add'>+		goto scale;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	left = 0;</div><div class='add'>+	right = caps-&gt;data_points - 1;</div><div class='add'>+	while (left &lt;= right) {</div><div class='add'>+		int mid = left + (right - left) / 2;</div><div class='add'>+		u8 signal = caps-&gt;luminance_data[mid].input_signal;</div><div class='add'>+</div><div class='add'>+		/* Exact match found */</div><div class='add'>+		if (signal == brightness) {</div><div class='add'>+			lum = caps-&gt;luminance_data[mid].luminance;</div><div class='add'>+			goto scale;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (signal &lt; brightness)</div><div class='add'>+			left = mid + 1;</div><div class='add'>+		else</div><div class='add'>+			right = mid - 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* verify bound */</div><div class='add'>+	if (left &gt;= caps-&gt;data_points)</div><div class='add'>+		left = caps-&gt;data_points - 1;</div><div class='add'>+</div><div class='add'>+	/* At this point, left &gt; right */</div><div class='add'>+	lower_signal = caps-&gt;luminance_data[right].input_signal;</div><div class='add'>+	upper_signal = caps-&gt;luminance_data[left].input_signal;</div><div class='add'>+	lower_lum = caps-&gt;luminance_data[right].luminance;</div><div class='add'>+	upper_lum = caps-&gt;luminance_data[left].luminance;</div><div class='add'>+</div><div class='add'>+	/* interpolate */</div><div class='add'>+	if (right == left || !lower_lum)</div><div class='add'>+		lum = upper_lum;</div><div class='add'>+	else</div><div class='add'>+		lum = lower_lum + DIV_ROUND_CLOSEST((upper_lum - lower_lum) *</div><div class='add'>+						    (brightness - lower_signal),</div><div class='add'>+						    upper_signal - lower_signal);</div><div class='add'>+scale:</div><div class='add'>+	*user_brightness = scale_fw_to_input(min, max,</div><div class='add'>+					     DIV_ROUND_CLOSEST(lum * brightness, 101));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,</div><div class='ctx'> 					uint32_t brightness)</div><div class='ctx'> {</div><div class='hunk'>@@ -4169,9 +5096,10 @@ static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *c</div><div class='ctx'> 	if (!get_brightness_range(caps, &amp;min, &amp;max))</div><div class='ctx'> 		return brightness;</div><div class='ctx'> </div><div class='del'>-	// Rescale 0..255 to min..max</div><div class='del'>-	return min + DIV_ROUND_CLOSEST((max - min) * brightness,</div><div class='del'>-				       AMDGPU_MAX_BL_LEVEL);</div><div class='add'>+	convert_custom_brightness(caps, min, max, &amp;brightness);</div><div class='add'>+</div><div class='add'>+	// Rescale 0..max to min..max</div><div class='add'>+	return min + DIV_ROUND_CLOSEST_ULL((u64)(max - min) * brightness, max);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,</div><div class='hunk'>@@ -4184,8 +5112,8 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap</div><div class='ctx'> </div><div class='ctx'> 	if (brightness &lt; min)</div><div class='ctx'> 		return 0;</div><div class='del'>-	// Rescale min..max to 0..255</div><div class='del'>-	return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),</div><div class='add'>+	// Rescale min..max to 0..max</div><div class='add'>+	return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min),</div><div class='ctx'> 				 max - min);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4193,33 +5121,76 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,</div><div class='ctx'> 					 int bl_idx,</div><div class='ctx'> 					 u32 user_brightness)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_dm_backlight_caps caps;</div><div class='add'>+	struct amdgpu_dm_backlight_caps *caps;</div><div class='ctx'> 	struct dc_link *link;</div><div class='ctx'> 	u32 brightness;</div><div class='del'>-	bool rc;</div><div class='add'>+	bool rc, reallow_idle = false;</div><div class='add'>+	struct drm_connector *connector;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(connector, &amp;dm-&gt;ddev-&gt;mode_config.connector_list, head) {</div><div class='add'>+		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='add'>+		if (aconnector-&gt;bl_idx != bl_idx)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* if connector is off, save the brightness for next time it's on */</div><div class='add'>+		if (!aconnector-&gt;base.encoder) {</div><div class='add'>+			dm-&gt;brightness[bl_idx] = user_brightness;</div><div class='add'>+			dm-&gt;actual_brightness[bl_idx] = 0;</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_update_backlight_caps(dm, bl_idx);</div><div class='del'>-	caps = dm-&gt;backlight_caps[bl_idx];</div><div class='add'>+	caps = &amp;dm-&gt;backlight_caps[bl_idx];</div><div class='ctx'> </div><div class='ctx'> 	dm-&gt;brightness[bl_idx] = user_brightness;</div><div class='ctx'> 	/* update scratch register */</div><div class='ctx'> 	if (bl_idx == 0)</div><div class='ctx'> 		amdgpu_atombios_scratch_regs_set_backlight_level(dm-&gt;adev, dm-&gt;brightness[bl_idx]);</div><div class='del'>-	brightness = convert_brightness_from_user(&amp;caps, dm-&gt;brightness[bl_idx]);</div><div class='add'>+	brightness = convert_brightness_from_user(caps, dm-&gt;brightness[bl_idx]);</div><div class='ctx'> 	link = (struct dc_link *)dm-&gt;backlight_link[bl_idx];</div><div class='ctx'> </div><div class='add'>+	/* Apply brightness quirk */</div><div class='add'>+	if (caps-&gt;brightness_mask)</div><div class='add'>+		brightness |= caps-&gt;brightness_mask;</div><div class='add'>+</div><div class='ctx'> 	/* Change brightness based on AUX property */</div><div class='del'>-	if (caps.aux_support) {</div><div class='add'>+	mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='add'>+	if (dm-&gt;dc-&gt;caps.ips_support &amp;&amp; dm-&gt;dc-&gt;ctx-&gt;dmub_srv-&gt;idle_allowed) {</div><div class='add'>+		dc_allow_idle_optimizations(dm-&gt;dc, false);</div><div class='add'>+		reallow_idle = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (trace_amdgpu_dm_brightness_enabled()) {</div><div class='add'>+		trace_amdgpu_dm_brightness(__builtin_return_address(0),</div><div class='add'>+					   user_brightness,</div><div class='add'>+					   brightness,</div><div class='add'>+					   caps-&gt;aux_support,</div><div class='add'>+					   power_supply_is_system_supplied() &gt; 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (caps-&gt;aux_support) {</div><div class='ctx'> 		rc = dc_link_set_backlight_level_nits(link, true, brightness,</div><div class='ctx'> 						      AUX_BL_DEFAULT_TRANSITION_TIME_MS);</div><div class='ctx'> 		if (!rc)</div><div class='ctx'> 			DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);</div><div class='ctx'> 	} else {</div><div class='del'>-		rc = dc_link_set_backlight_level(link, brightness, 0);</div><div class='add'>+		struct set_backlight_level_params backlight_level_params = { 0 };</div><div class='add'>+</div><div class='add'>+		backlight_level_params.backlight_pwm_u16_16 = brightness;</div><div class='add'>+		backlight_level_params.transition_time_in_ms = 0;</div><div class='add'>+</div><div class='add'>+		rc = dc_link_set_backlight_level(link, &amp;backlight_level_params);</div><div class='ctx'> 		if (!rc)</div><div class='ctx'> 			DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dm-&gt;dc-&gt;caps.ips_support &amp;&amp; reallow_idle)</div><div class='add'>+		dc_allow_idle_optimizations(dm-&gt;dc, true);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='add'>+</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		dm-&gt;actual_brightness[bl_idx] = user_brightness;</div><div class='ctx'> }</div><div class='hunk'>@@ -4252,10 +5223,8 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	if (caps.aux_support) {</div><div class='ctx'> 		u32 avg, peak;</div><div class='del'>-		bool rc;</div><div class='ctx'> </div><div class='del'>-		rc = dc_link_get_backlight_level_nits(link, &amp;avg, &amp;peak);</div><div class='del'>-		if (!rc)</div><div class='add'>+		if (!dc_link_get_backlight_level_nits(link, &amp;avg, &amp;peak))</div><div class='ctx'> 			return dm-&gt;brightness[bl_idx];</div><div class='ctx'> 		return convert_brightness_to_user(&amp;caps, avg);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4294,7 +5263,9 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 	struct drm_device *drm = aconnector-&gt;base.dev;</div><div class='ctx'> 	struct amdgpu_display_manager *dm = &amp;drm_to_adev(drm)-&gt;dm;</div><div class='ctx'> 	struct backlight_properties props = { 0 };</div><div class='add'>+	struct amdgpu_dm_backlight_caps *caps;</div><div class='ctx'> 	char bl_name[16];</div><div class='add'>+	int min, max;</div><div class='ctx'> </div><div class='ctx'> 	if (aconnector-&gt;bl_idx == -1)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -4306,8 +5277,24 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	props.max_brightness = AMDGPU_MAX_BL_LEVEL;</div><div class='del'>-	props.brightness = AMDGPU_MAX_BL_LEVEL;</div><div class='add'>+	caps = &amp;dm-&gt;backlight_caps[aconnector-&gt;bl_idx];</div><div class='add'>+	if (get_brightness_range(caps, &amp;min, &amp;max)) {</div><div class='add'>+		if (power_supply_is_system_supplied() &gt; 0)</div><div class='add'>+			props.brightness = DIV_ROUND_CLOSEST((max - min) * caps-&gt;ac_level, 100);</div><div class='add'>+		else</div><div class='add'>+			props.brightness = DIV_ROUND_CLOSEST((max - min) * caps-&gt;dc_level, 100);</div><div class='add'>+		/* min is zero, so max needs to be adjusted */</div><div class='add'>+		props.max_brightness = max - min;</div><div class='add'>+		drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max,</div><div class='add'>+			caps-&gt;ac_level, caps-&gt;dc_level);</div><div class='add'>+	} else</div><div class='add'>+		props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+</div><div class='add'>+	if (caps-&gt;data_points &amp;&amp; !(amdgpu_dc_debug_mask &amp; DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) {</div><div class='add'>+		drm_info(drm, "Using custom brightness curve\n");</div><div class='add'>+		props.scale = BACKLIGHT_SCALE_NON_LINEAR;</div><div class='add'>+	} else</div><div class='add'>+		props.scale = BACKLIGHT_SCALE_LINEAR;</div><div class='ctx'> 	props.type = BACKLIGHT_RAW;</div><div class='ctx'> </div><div class='ctx'> 	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",</div><div class='hunk'>@@ -4316,12 +5303,13 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 	dm-&gt;backlight_dev[aconnector-&gt;bl_idx] =</div><div class='ctx'> 		backlight_device_register(bl_name, aconnector-&gt;base.kdev, dm,</div><div class='ctx'> 					  &amp;amdgpu_dm_backlight_ops, &amp;props);</div><div class='add'>+	dm-&gt;brightness[aconnector-&gt;bl_idx] = props.brightness;</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ERR(dm-&gt;backlight_dev[aconnector-&gt;bl_idx])) {</div><div class='del'>-		DRM_ERROR("DM: Backlight registration failed!\n");</div><div class='add'>+		drm_err(drm, "DM: Backlight registration failed!\n");</div><div class='ctx'> 		dm-&gt;backlight_dev[aconnector-&gt;bl_idx] = NULL;</div><div class='ctx'> 	} else</div><div class='del'>-		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);</div><div class='add'>+		drm_dbg_driver(drm, "DM: Registered Backlight device: %s\n", bl_name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int initialize_plane(struct amdgpu_display_manager *dm,</div><div class='hunk'>@@ -4335,7 +5323,7 @@ static int initialize_plane(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);</div><div class='ctx'> 	if (!plane) {</div><div class='del'>-		DRM_ERROR("KMS: Failed to allocate plane\n");</div><div class='add'>+		drm_err(adev_to_drm(dm-&gt;adev), "KMS: Failed to allocate plane\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> 	plane-&gt;type = plane_type;</div><div class='hunk'>@@ -4353,7 +5341,7 @@ static int initialize_plane(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='del'>-		DRM_ERROR("KMS: Failed to initialize plane\n");</div><div class='add'>+		drm_err(adev_to_drm(dm-&gt;adev), "KMS: Failed to initialize plane\n");</div><div class='ctx'> 		kfree(plane);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4368,6 +5356,7 @@ static int initialize_plane(struct amdgpu_display_manager *dm,</div><div class='ctx'> static void setup_backlight_device(struct amdgpu_display_manager *dm,</div><div class='ctx'> 				   struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_dm_backlight_caps *caps;</div><div class='ctx'> 	struct dc_link *link = aconnector-&gt;dc_link;</div><div class='ctx'> 	int bl_idx = dm-&gt;num_of_edps;</div><div class='ctx'> </div><div class='hunk'>@@ -4383,11 +5372,17 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	aconnector-&gt;bl_idx = bl_idx;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_update_backlight_caps(dm, bl_idx);</div><div class='del'>-	dm-&gt;brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;</div><div class='ctx'> 	dm-&gt;backlight_link[bl_idx] = link;</div><div class='ctx'> 	dm-&gt;num_of_edps++;</div><div class='ctx'> </div><div class='ctx'> 	update_connector_ext_caps(aconnector);</div><div class='add'>+	caps = &amp;dm-&gt;backlight_caps[aconnector-&gt;bl_idx];</div><div class='add'>+</div><div class='add'>+	/* Only offer ABM property when non-OLED and user didn't turn off by module parameter */</div><div class='add'>+	if (!caps-&gt;ext_caps-&gt;bits.oled &amp;&amp; amdgpu_dm_abm_level &lt; 0)</div><div class='add'>+		drm_object_attach_property(&amp;aconnector-&gt;base.base,</div><div class='add'>+					   dm-&gt;adev-&gt;mode_info.abm_level_property,</div><div class='add'>+					   ABM_SYSFS_CONTROL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_set_panel_orientation(struct drm_connector *connector);</div><div class='hunk'>@@ -4423,13 +5418,16 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	link_cnt = dm-&gt;dc-&gt;caps.max_links;</div><div class='ctx'> 	if (amdgpu_dm_mode_config_init(dm-&gt;adev)) {</div><div class='del'>-		DRM_ERROR("DM: Failed to initialize mode config\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* There is one primary plane per CRTC */</div><div class='ctx'> 	primary_planes = dm-&gt;dc-&gt;caps.max_streams;</div><div class='del'>-	ASSERT(primary_planes &lt;= AMDGPU_MAX_PLANES);</div><div class='add'>+	if (primary_planes &gt; AMDGPU_MAX_PLANES) {</div><div class='add'>+		drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Initialize primary planes, implicit planes for legacy IOCTLS.</div><div class='hunk'>@@ -4440,7 +5438,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		if (initialize_plane(dm, mode_info, i,</div><div class='ctx'> 				     DRM_PLANE_TYPE_PRIMARY, plane)) {</div><div class='del'>-			DRM_ERROR("KMS: Failed to initialize primary plane\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4472,14 +5470,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		if (initialize_plane(dm, NULL, primary_planes + i,</div><div class='ctx'> 				     DRM_PLANE_TYPE_OVERLAY, plane)) {</div><div class='del'>-			DRM_ERROR("KMS: Failed to initialize overlay plane\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dm-&gt;dc-&gt;caps.max_streams; i++)</div><div class='ctx'> 		if (amdgpu_dm_crtc_init(dm, mode_info-&gt;planes[i], i)) {</div><div class='del'>-			DRM_ERROR("KMS: Failed to initialize crtc\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -4496,8 +5494,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(2, 1, 0):</div><div class='ctx'> 	case IP_VERSION(3, 5, 0):</div><div class='ctx'> 	case IP_VERSION(3, 5, 1):</div><div class='add'>+	case IP_VERSION(3, 6, 0):</div><div class='add'>+	case IP_VERSION(4, 0, 1):</div><div class='ctx'> 		if (register_outbox_irq_handlers(dm-&gt;adev)) {</div><div class='del'>-			DRM_ERROR("DM: Failed to initialize IRQ\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -4518,6 +5518,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 		case IP_VERSION(3, 2, 1):</div><div class='ctx'> 		case IP_VERSION(3, 5, 0):</div><div class='ctx'> 		case IP_VERSION(3, 5, 1):</div><div class='add'>+		case IP_VERSION(3, 6, 0):</div><div class='add'>+		case IP_VERSION(4, 0, 1):</div><div class='ctx'> 			psr_feature_enabled = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='hunk'>@@ -4530,43 +5532,43 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!(amdgpu_dc_debug_mask &amp; DC_DISABLE_REPLAY)) {</div><div class='ctx'> 		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='ctx'> 		case IP_VERSION(3, 1, 4):</div><div class='del'>-		case IP_VERSION(3, 1, 5):</div><div class='del'>-		case IP_VERSION(3, 1, 6):</div><div class='ctx'> 		case IP_VERSION(3, 2, 0):</div><div class='ctx'> 		case IP_VERSION(3, 2, 1):</div><div class='ctx'> 		case IP_VERSION(3, 5, 0):</div><div class='ctx'> 		case IP_VERSION(3, 5, 1):</div><div class='add'>+		case IP_VERSION(3, 6, 0):</div><div class='ctx'> 			replay_feature_enabled = true;</div><div class='ctx'> 			break;</div><div class='add'>+</div><div class='ctx'> 		default:</div><div class='ctx'> 			replay_feature_enabled = amdgpu_dc_feature_mask &amp; DC_REPLAY_MASK;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (link_cnt &gt; MAX_LINKS) {</div><div class='add'>+		drm_err(adev_to_drm(adev),</div><div class='add'>+			"KMS: Cannot support more than %d display indexes\n",</div><div class='add'>+				MAX_LINKS);</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* loops over all connectors on the board */</div><div class='ctx'> 	for (i = 0; i &lt; link_cnt; i++) {</div><div class='ctx'> 		struct dc_link *link = NULL;</div><div class='ctx'> </div><div class='del'>-		if (i &gt; AMDGPU_DM_MAX_DISPLAY_INDEX) {</div><div class='del'>-			DRM_ERROR(</div><div class='del'>-				"KMS: Cannot support more than %d display indexes\n",</div><div class='del'>-					AMDGPU_DM_MAX_DISPLAY_INDEX);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 		link = dc_get_link_at_index(dm-&gt;dc, i);</div><div class='ctx'> </div><div class='ctx'> 		if (link-&gt;connector_signal == SIGNAL_TYPE_VIRTUAL) {</div><div class='ctx'> 			struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 			if (!wbcon) {</div><div class='del'>-				DRM_ERROR("KMS: Failed to allocate writeback connector\n");</div><div class='add'>+				drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n");</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {</div><div class='del'>-				DRM_ERROR("KMS: Failed to initialize writeback connector\n");</div><div class='add'>+				drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n");</div><div class='ctx'> 				kfree(wbcon);</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -4586,12 +5588,12 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_dm_encoder_init(dm-&gt;ddev, aencoder, i)) {</div><div class='del'>-			DRM_ERROR("KMS: Failed to initialize encoder\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {</div><div class='del'>-			DRM_ERROR("KMS: Failed to initialize connector\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -4600,7 +5602,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 				aconnector;</div><div class='ctx'> </div><div class='ctx'> 		if (!dc_link_detect_connection_type(link, &amp;new_connection_type))</div><div class='del'>-			DRM_ERROR("KMS: Failed to detect connector\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n");</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;base.force &amp;&amp; new_connection_type == dc_connection_none) {</div><div class='ctx'> 			emulated_link_detect(link);</div><div class='hunk'>@@ -4609,6 +5611,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 			bool ret = false;</div><div class='ctx'> </div><div class='ctx'> 			mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='add'>+			dc_exit_ips_for_hw_access(dm-&gt;dc);</div><div class='ctx'> 			ret = dc_link_detect(link, DETECT_REASON_BOOT);</div><div class='ctx'> 			mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -4621,19 +5624,26 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 					if (amdgpu_dm_set_replay_caps(link, aconnector))</div><div class='ctx'> 						psr_feature_enabled = false;</div><div class='ctx'> </div><div class='del'>-				if (psr_feature_enabled)</div><div class='add'>+				if (psr_feature_enabled) {</div><div class='ctx'> 					amdgpu_dm_set_psr_caps(link);</div><div class='del'>-</div><div class='del'>-				/* TODO: Fix vblank control helpers to delay PSR entry to allow this when</div><div class='del'>-				 * PSR is also supported.</div><div class='del'>-				 */</div><div class='del'>-				if (link-&gt;psr_settings.psr_feature_enabled)</div><div class='del'>-					adev_to_drm(adev)-&gt;vblank_disable_immediate = false;</div><div class='add'>+					drm_info(adev_to_drm(adev), "PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",</div><div class='add'>+						 link-&gt;psr_settings.psr_feature_enabled,</div><div class='add'>+						 link-&gt;psr_settings.psr_version,</div><div class='add'>+						 link-&gt;dpcd_caps.psr_info.psr_version,</div><div class='add'>+						 link-&gt;dpcd_caps.psr_info.psr_dpcd_caps.raw,</div><div class='add'>+						 link-&gt;dpcd_caps.psr_info.psr2_su_y_granularity_cap);</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		amdgpu_set_panel_orientation(&amp;aconnector-&gt;base);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Debug dump: list all DC links and their associated sinks after detection</div><div class='add'>+	 * is complete for all connectors. This provides a comprehensive view of the</div><div class='add'>+	 * final state without repeating the dump for each connector.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_dm_dump_links_and_sinks(adev);</div><div class='add'>+</div><div class='ctx'> 	/* Software is initialized. Now we can register interrupt handlers. */</div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_SI)</div><div class='hunk'>@@ -4642,7 +5652,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 	case CHIP_VERDE:</div><div class='ctx'> 	case CHIP_OLAND:</div><div class='ctx'> 		if (dce60_register_irq_handlers(dm-&gt;adev)) {</div><div class='del'>-			DRM_ERROR("DM: Failed to initialize IRQ\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -4664,7 +5674,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 	case CHIP_VEGA12:</div><div class='ctx'> 	case CHIP_VEGA20:</div><div class='ctx'> 		if (dce110_register_irq_handlers(dm-&gt;adev)) {</div><div class='del'>-			DRM_ERROR("DM: Failed to initialize IRQ\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -4689,13 +5699,15 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 		case IP_VERSION(3, 2, 1):</div><div class='ctx'> 		case IP_VERSION(3, 5, 0):</div><div class='ctx'> 		case IP_VERSION(3, 5, 1):</div><div class='add'>+		case IP_VERSION(3, 6, 0):</div><div class='add'>+		case IP_VERSION(4, 0, 1):</div><div class='ctx'> 			if (dcn10_register_irq_handlers(dm-&gt;adev)) {</div><div class='del'>-				DRM_ERROR("DM: Failed to initialize IRQ\n");</div><div class='add'>+				drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");</div><div class='ctx'> 				goto fail;</div><div class='ctx'> 			}</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='del'>-			DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",</div><div class='add'>+			drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n",</div><div class='ctx'> 					amdgpu_ip_version(adev, DCE_HWIP, 0));</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4712,7 +5724,8 @@ fail:</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)</div><div class='ctx'> {</div><div class='del'>-	drm_atomic_private_obj_fini(&amp;dm-&gt;atomic_obj);</div><div class='add'>+	if (dm-&gt;atomic_obj.state)</div><div class='add'>+		drm_atomic_private_obj_fini(&amp;dm-&gt;atomic_obj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /******************************************************************************</div><div class='hunk'>@@ -4756,15 +5769,20 @@ static ssize_t s3_debug_store(struct device *device,</div><div class='ctx'> 	int s3_state;</div><div class='ctx'> 	struct drm_device *drm_dev = dev_get_drvdata(device);</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='add'>+	struct amdgpu_ip_block *ip_block;</div><div class='add'>+</div><div class='add'>+	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE);</div><div class='add'>+	if (!ip_block)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	ret = kstrtoint(buf, 0, &amp;s3_state);</div><div class='ctx'> </div><div class='ctx'> 	if (ret == 0) {</div><div class='ctx'> 		if (s3_state) {</div><div class='del'>-			dm_resume(adev);</div><div class='add'>+			dm_resume(ip_block);</div><div class='ctx'> 			drm_kms_helper_hotplug_event(adev_to_drm(adev));</div><div class='ctx'> 		} else</div><div class='del'>-			dm_suspend(adev);</div><div class='add'>+			dm_suspend(ip_block);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret == 0 ? count : 0;</div><div class='hunk'>@@ -4820,20 +5838,29 @@ static int dm_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 		fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(3, 5, 0):</div><div class='del'>-	case IP_VERSION(3, 5, 1):</div><div class='ctx'> 		fw_name_dmub = FIRMWARE_DCN_35_DMUB;</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(3, 5, 1):</div><div class='add'>+		fw_name_dmub = FIRMWARE_DCN_351_DMUB;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(3, 6, 0):</div><div class='add'>+		fw_name_dmub = FIRMWARE_DCN_36_DMUB;</div><div class='add'>+		break;</div><div class='add'>+	case IP_VERSION(4, 0, 1):</div><div class='add'>+		fw_name_dmub = FIRMWARE_DCN_401_DMUB;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* ASIC doesn't support DMUB. */</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='del'>-	r = amdgpu_ucode_request(adev, &amp;adev-&gt;dm.dmub_fw, fw_name_dmub);</div><div class='add'>+	r = amdgpu_ucode_request(adev, &amp;adev-&gt;dm.dmub_fw, AMDGPU_UCODE_REQUIRED,</div><div class='add'>+				 "%s", fw_name_dmub);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_early_init(void *handle)</div><div class='add'>+static int dm_early_init(struct amdgpu_ip_block *ip_block)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_device *adev = ip_block-&gt;adev;</div><div class='ctx'> 	struct amdgpu_mode_info *mode_info = &amp;adev-&gt;mode_info;</div><div class='ctx'> 	struct atom_context *ctx = mode_info-&gt;atom_context;</div><div class='ctx'> 	int index = GetIndexIntoMasterTable(DATA, Object_Header);</div><div class='hunk'>@@ -4842,7 +5869,7 @@ static int dm_early_init(void *handle)</div><div class='ctx'> 	/* if there is no object header, skip DM */</div><div class='ctx'> 	if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &amp;data_offset)) {</div><div class='ctx'> 		adev-&gt;harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;</div><div class='del'>-		dev_info(adev-&gt;dev, "No object header, skipping DM\n");</div><div class='add'>+		drm_info(adev_to_drm(adev), "No object header, skipping DM\n");</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -4947,12 +5974,14 @@ static int dm_early_init(void *handle)</div><div class='ctx'> 		case IP_VERSION(3, 2, 1):</div><div class='ctx'> 		case IP_VERSION(3, 5, 0):</div><div class='ctx'> 		case IP_VERSION(3, 5, 1):</div><div class='add'>+		case IP_VERSION(3, 6, 0):</div><div class='add'>+		case IP_VERSION(4, 0, 1):</div><div class='ctx'> 			adev-&gt;mode_info.num_crtc = 4;</div><div class='ctx'> 			adev-&gt;mode_info.num_hpd = 4;</div><div class='ctx'> 			adev-&gt;mode_info.num_dig = 4;</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='del'>-			DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",</div><div class='add'>+			drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n",</div><div class='ctx'> 					amdgpu_ip_version(adev, DCE_HWIP, 0));</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -5001,6 +6030,10 @@ fill_plane_color_attributes(const struct drm_plane_state *plane_state,</div><div class='ctx'> </div><div class='ctx'> 	*color_space = COLOR_SPACE_SRGB;</div><div class='ctx'> </div><div class='add'>+	/* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */</div><div class='add'>+	if (plane_state-&gt;state &amp;&amp; plane_state-&gt;state-&gt;plane_color_pipeline)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	/* DRM color properties only affect non-RGB formats. */</div><div class='ctx'> 	if (format &lt; SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -5024,9 +6057,9 @@ fill_plane_color_attributes(const struct drm_plane_state *plane_state,</div><div class='ctx'> </div><div class='ctx'> 	case DRM_COLOR_YCBCR_BT2020:</div><div class='ctx'> 		if (full_range)</div><div class='del'>-			*color_space = COLOR_SPACE_2020_YCBCR;</div><div class='add'>+			*color_space = COLOR_SPACE_2020_YCBCR_FULL;</div><div class='ctx'> 		else</div><div class='del'>-			return -EINVAL;</div><div class='add'>+			*color_space = COLOR_SPACE_2020_YCBCR_LIMITED;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='hunk'>@@ -5042,8 +6075,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,</div><div class='ctx'> 			    const u64 tiling_flags,</div><div class='ctx'> 			    struct dc_plane_info *plane_info,</div><div class='ctx'> 			    struct dc_plane_address *address,</div><div class='del'>-			    bool tmz_surface,</div><div class='del'>-			    bool force_disable_dcc)</div><div class='add'>+			    bool tmz_surface)</div><div class='ctx'> {</div><div class='ctx'> 	const struct drm_framebuffer *fb = plane_state-&gt;fb;</div><div class='ctx'> 	const struct amdgpu_framebuffer *afb =</div><div class='hunk'>@@ -5102,7 +6134,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,</div><div class='ctx'> 		plane_info-&gt;format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		DRM_ERROR(</div><div class='add'>+		drm_err(adev_to_drm(adev),</div><div class='ctx'> 			"Unsupported screen format %p4cc\n",</div><div class='ctx'> 			&amp;fb-&gt;format-&gt;format);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -5142,7 +6174,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,</div><div class='ctx'> 					   &amp;plane_info-&gt;tiling_info,</div><div class='ctx'> 					   &amp;plane_info-&gt;plane_size,</div><div class='ctx'> 					   &amp;plane_info-&gt;dcc, address,</div><div class='del'>-					   tmz_surface, force_disable_dcc);</div><div class='add'>+					   tmz_surface);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -5163,7 +6195,6 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,</div><div class='ctx'> 	struct dc_scaling_info scaling_info;</div><div class='ctx'> 	struct dc_plane_info plane_info;</div><div class='ctx'> 	int ret;</div><div class='del'>-	bool force_disable_dcc = false;</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &amp;scaling_info);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -5174,13 +6205,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,</div><div class='ctx'> 	dc_plane_state-&gt;clip_rect = scaling_info.clip_rect;</div><div class='ctx'> 	dc_plane_state-&gt;scaling_quality = scaling_info.scaling_quality;</div><div class='ctx'> </div><div class='del'>-	force_disable_dcc = adev-&gt;asic_type == CHIP_RAVEN &amp;&amp; adev-&gt;in_suspend;</div><div class='ctx'> 	ret = fill_dc_plane_info_and_addr(adev, plane_state,</div><div class='ctx'> 					  afb-&gt;tiling_flags,</div><div class='ctx'> 					  &amp;plane_info,</div><div class='ctx'> 					  &amp;dc_plane_state-&gt;address,</div><div class='del'>-					  afb-&gt;tmz_surface,</div><div class='del'>-					  force_disable_dcc);</div><div class='add'>+					  afb-&gt;tmz_surface);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -5526,12 +6555,14 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,</div><div class='ctx'> 		if (dc_crtc_timing-&gt;pixel_encoding == PIXEL_ENCODING_RGB)</div><div class='ctx'> 			color_space = COLOR_SPACE_2020_RGB_FULLRANGE;</div><div class='ctx'> 		else</div><div class='del'>-			color_space = COLOR_SPACE_2020_YCBCR;</div><div class='add'>+			color_space = COLOR_SPACE_2020_YCBCR_LIMITED;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601</div><div class='ctx'> 	default:</div><div class='ctx'> 		if (dc_crtc_timing-&gt;pixel_encoding == PIXEL_ENCODING_RGB) {</div><div class='ctx'> 			color_space = COLOR_SPACE_SRGB;</div><div class='add'>+			if (connector_state-&gt;hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED)</div><div class='add'>+				color_space = COLOR_SPACE_SRGB_LIMITED;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * 27030khz is the separation point between HDTV and SDTV</div><div class='ctx'> 		 * according to HDMI spec, we use YCbCr709 and YCbCr601</div><div class='hunk'>@@ -5624,6 +6655,7 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='ctx'> 	struct hdmi_vendor_infoframe hv_frame;</div><div class='ctx'> 	struct hdmi_avi_infoframe avi_frame;</div><div class='add'>+	ssize_t err;</div><div class='ctx'> </div><div class='ctx'> 	if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='hunk'>@@ -5643,6 +6675,10 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> 			&amp;&amp; aconnector</div><div class='ctx'> 			&amp;&amp; aconnector-&gt;force_yuv420_output)</div><div class='ctx'> 		timing_out-&gt;pixel_encoding = PIXEL_ENCODING_YCBCR420;</div><div class='add'>+	else if ((connector-&gt;display_info.color_formats &amp; DRM_COLOR_FORMAT_YCBCR422)</div><div class='add'>+			&amp;&amp; aconnector</div><div class='add'>+			&amp;&amp; aconnector-&gt;force_yuv422_output)</div><div class='add'>+		timing_out-&gt;pixel_encoding = PIXEL_ENCODING_YCBCR422;</div><div class='ctx'> 	else if ((connector-&gt;display_info.color_formats &amp; DRM_COLOR_FORMAT_YCBCR444)</div><div class='ctx'> 			&amp;&amp; stream-&gt;signal == SIGNAL_TYPE_HDMI_TYPE_A)</div><div class='ctx'> 		timing_out-&gt;pixel_encoding = PIXEL_ENCODING_YCBCR444;</div><div class='hunk'>@@ -5670,9 +6706,19 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;signal == SIGNAL_TYPE_HDMI_TYPE_A) {</div><div class='del'>-		drm_hdmi_avi_infoframe_from_display_mode(&amp;avi_frame, (struct drm_connector *)connector, mode_in);</div><div class='add'>+		err = drm_hdmi_avi_infoframe_from_display_mode(&amp;avi_frame,</div><div class='add'>+							       (struct drm_connector *)connector,</div><div class='add'>+							       mode_in);</div><div class='add'>+		if (err &lt; 0)</div><div class='add'>+			drm_warn_once(connector-&gt;dev, "Failed to setup avi infoframe on connector %s: %zd\n",</div><div class='add'>+				      connector-&gt;name, err);</div><div class='ctx'> 		timing_out-&gt;vic = avi_frame.video_code;</div><div class='del'>-		drm_hdmi_vendor_infoframe_from_display_mode(&amp;hv_frame, (struct drm_connector *)connector, mode_in);</div><div class='add'>+		err = drm_hdmi_vendor_infoframe_from_display_mode(&amp;hv_frame,</div><div class='add'>+								  (struct drm_connector *)connector,</div><div class='add'>+								  mode_in);</div><div class='add'>+		if (err &lt; 0)</div><div class='add'>+			drm_warn_once(connector-&gt;dev, "Failed to setup vendor infoframe on connector %s: %zd\n",</div><div class='add'>+				      connector-&gt;name, err);</div><div class='ctx'> 		timing_out-&gt;hdmi_vic = hv_frame.vic;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -5700,8 +6746,8 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> </div><div class='ctx'> 	timing_out-&gt;aspect_ratio = get_aspect_ratio(mode_in);</div><div class='ctx'> </div><div class='del'>-	stream-&gt;out_transfer_func-&gt;type = TF_TYPE_PREDEFINED;</div><div class='del'>-	stream-&gt;out_transfer_func-&gt;tf = TRANSFER_FUNCTION_SRGB;</div><div class='add'>+	stream-&gt;out_transfer_func.type = TF_TYPE_PREDEFINED;</div><div class='add'>+	stream-&gt;out_transfer_func.tf = TRANSFER_FUNCTION_SRGB;</div><div class='ctx'> 	if (stream-&gt;signal == SIGNAL_TYPE_HDMI_TYPE_A) {</div><div class='ctx'> 		if (!adjust_colour_depth_from_display_info(timing_out, info) &amp;&amp;</div><div class='ctx'> 		    drm_mode_is_420_also(info, mode_in) &amp;&amp;</div><div class='hunk'>@@ -5785,19 +6831,19 @@ decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,</div><div class='ctx'> 					const struct drm_display_mode *native_mode,</div><div class='ctx'> 					bool scale_enabled)</div><div class='ctx'> {</div><div class='del'>-	if (scale_enabled) {</div><div class='del'>-		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);</div><div class='del'>-	} else if (native_mode-&gt;clock == drm_mode-&gt;clock &amp;&amp;</div><div class='del'>-			native_mode-&gt;htotal == drm_mode-&gt;htotal &amp;&amp;</div><div class='del'>-			native_mode-&gt;vtotal == drm_mode-&gt;vtotal) {</div><div class='del'>-		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);</div><div class='add'>+	if (scale_enabled || (</div><div class='add'>+	    native_mode-&gt;clock == drm_mode-&gt;clock &amp;&amp;</div><div class='add'>+	    native_mode-&gt;htotal == drm_mode-&gt;htotal &amp;&amp;</div><div class='add'>+	    native_mode-&gt;vtotal == drm_mode-&gt;vtotal)) {</div><div class='add'>+		if (native_mode-&gt;crtc_clock)</div><div class='add'>+			copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* no scaling nor amdgpu inserted, no need to patch */</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct dc_sink *</div><div class='del'>-create_fake_sink(struct dc_link *link)</div><div class='add'>+create_fake_sink(struct drm_device *dev, struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_sink_init_data sink_init_data = { 0 };</div><div class='ctx'> 	struct dc_sink *sink = NULL;</div><div class='hunk'>@@ -5807,7 +6853,7 @@ create_fake_sink(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	sink = dc_sink_create(&amp;sink_init_data);</div><div class='ctx'> 	if (!sink) {</div><div class='del'>-		DRM_ERROR("Failed to create sink!\n");</div><div class='add'>+		drm_err(dev, "Failed to create sink!\n");</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	sink-&gt;sink_signal = SIGNAL_TYPE_VIRTUAL;</div><div class='hunk'>@@ -5921,6 +6967,9 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 		&amp;aconnector-&gt;base.probed_modes :</div><div class='ctx'> 		&amp;aconnector-&gt;base.modes;</div><div class='ctx'> </div><div class='add'>+	if (aconnector-&gt;base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	if (aconnector-&gt;freesync_vid_base.clock != 0)</div><div class='ctx'> 		return &amp;aconnector-&gt;freesync_vid_base;</div><div class='ctx'> </div><div class='hunk'>@@ -5937,7 +6986,7 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 		m_pref = list_first_entry_or_null(</div><div class='ctx'> 				&amp;aconnector-&gt;base.modes, struct drm_display_mode, head);</div><div class='ctx'> 		if (!m_pref) {</div><div class='del'>-			DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");</div><div class='add'>+			drm_dbg_driver(aconnector-&gt;base.dev, "No preferred mode found in EDID\n");</div><div class='ctx'> 			return NULL;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -5991,6 +7040,7 @@ static bool is_freesync_video_mode(const struct drm_display_mode *mode,</div><div class='ctx'> 		return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 			    struct dc_sink *sink, struct dc_stream_state *stream,</div><div class='ctx'> 			    struct dsc_dec_dpcd_caps *dsc_caps)</div><div class='hunk'>@@ -6009,7 +7059,6 @@ static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 				    struct dc_sink *sink, struct dc_stream_state *stream,</div><div class='ctx'> 				    struct dsc_dec_dpcd_caps *dsc_caps,</div><div class='hunk'>@@ -6073,7 +7122,6 @@ static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 					struct dc_sink *sink, struct dc_stream_state *stream,</div><div class='ctx'> 					struct dsc_dec_dpcd_caps *dsc_caps)</div><div class='hunk'>@@ -6097,13 +7145,13 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	dc_dsc_policy_set_enable_dsc_when_not_needed(</div><div class='ctx'> 		aconnector-&gt;dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);</div><div class='ctx'> </div><div class='del'>-	if (aconnector-&gt;dc_link &amp;&amp; sink-&gt;sink_signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+	if (sink-&gt;sink_signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='ctx'> 	    !aconnector-&gt;dc_link-&gt;panel_config.dsc.disable_dsc_edp &amp;&amp;</div><div class='ctx'> 	    dc-&gt;caps.edp_dsc_support &amp;&amp; aconnector-&gt;dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {</div><div class='ctx'> </div><div class='ctx'> 		apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);</div><div class='ctx'> </div><div class='del'>-	} else if (aconnector-&gt;dc_link &amp;&amp; sink-&gt;sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {</div><div class='add'>+	} else if (sink-&gt;sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {</div><div class='ctx'> 		if (sink-&gt;link-&gt;dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {</div><div class='ctx'> 			if (dc_dsc_compute_config(aconnector-&gt;dc_link-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='ctx'> 						dsc_caps,</div><div class='hunk'>@@ -6113,7 +7161,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 						dc_link_get_highest_encoding_format(aconnector-&gt;dc_link),</div><div class='ctx'> 						&amp;stream-&gt;timing.dsc_cfg)) {</div><div class='ctx'> 				stream-&gt;timing.flags.DSC = 1;</div><div class='del'>-				DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector-&gt;name);</div><div class='add'>+				drm_dbg_driver(drm_connector-&gt;dev, "%s: SST_DSC [%s] DSC is selected from SST RX\n",</div><div class='add'>+							__func__, drm_connector-&gt;name);</div><div class='ctx'> 			}</div><div class='ctx'> 		} else if (sink-&gt;link-&gt;dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {</div><div class='ctx'> 			timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&amp;stream-&gt;timing,</div><div class='hunk'>@@ -6132,7 +7181,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 						dc_link_get_highest_encoding_format(aconnector-&gt;dc_link),</div><div class='ctx'> 						&amp;stream-&gt;timing.dsc_cfg)) {</div><div class='ctx'> 					stream-&gt;timing.flags.DSC = 1;</div><div class='del'>-					DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",</div><div class='add'>+					drm_dbg_driver(drm_connector-&gt;dev, "%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n",</div><div class='ctx'> 									 __func__, drm_connector-&gt;name);</div><div class='ctx'> 				}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -6151,6 +7200,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	if (stream-&gt;timing.flags.DSC &amp;&amp; aconnector-&gt;dsc_settings.dsc_bits_per_pixel)</div><div class='ctx'> 		stream-&gt;timing.dsc_cfg.bits_per_pixel = aconnector-&gt;dsc_settings.dsc_bits_per_pixel;</div><div class='ctx'> }</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> static struct dc_stream_state *</div><div class='ctx'> create_stream_for_sink(struct drm_connector *connector,</div><div class='hunk'>@@ -6159,6 +7209,7 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 		       const struct dc_stream_state *old_stream,</div><div class='ctx'> 		       int requested_bpc)</div><div class='ctx'> {</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='ctx'> 	struct drm_display_mode *preferred_mode = NULL;</div><div class='ctx'> 	const struct drm_connector_state *con_state = &amp;dm_state-&gt;base;</div><div class='hunk'>@@ -6172,19 +7223,15 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 	int mode_refresh;</div><div class='ctx'> 	int preferred_refresh = 0;</div><div class='ctx'> 	enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> 	struct dsc_dec_dpcd_caps dsc_caps;</div><div class='del'>-</div><div class='add'>+#endif</div><div class='ctx'> 	struct dc_link *link = NULL;</div><div class='ctx'> 	struct dc_sink *sink = NULL;</div><div class='ctx'> </div><div class='ctx'> 	drm_mode_init(&amp;mode, drm_mode);</div><div class='ctx'> 	memset(&amp;saved_mode, 0, sizeof(saved_mode));</div><div class='ctx'> </div><div class='del'>-	if (connector == NULL) {</div><div class='del'>-		DRM_ERROR("connector is NULL!\n");</div><div class='del'>-		return stream;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {</div><div class='ctx'> 		aconnector = NULL;</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='hunk'>@@ -6199,7 +7246,7 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!aconnector || !aconnector-&gt;dc_sink) {</div><div class='del'>-		sink = create_fake_sink(link);</div><div class='add'>+		sink = create_fake_sink(dev, link);</div><div class='ctx'> 		if (!sink)</div><div class='ctx'> 			return stream;</div><div class='ctx'> </div><div class='hunk'>@@ -6211,7 +7258,7 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 	stream = dc_create_stream_for_sink(sink);</div><div class='ctx'> </div><div class='ctx'> 	if (stream == NULL) {</div><div class='del'>-		DRM_ERROR("Failed to create stream for sink!\n");</div><div class='add'>+		drm_err(dev, "Failed to create stream for sink!\n");</div><div class='ctx'> 		goto finish;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -6243,7 +7290,7 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 		 * case, we call set mode ourselves to restore the previous mode</div><div class='ctx'> 		 * and the modelist may not be filled in time.</div><div class='ctx'> 		 */</div><div class='del'>-		DRM_DEBUG_DRIVER("No preferred mode found\n");</div><div class='add'>+		drm_dbg_driver(dev, "No preferred mode found\n");</div><div class='ctx'> 	} else if (aconnector) {</div><div class='ctx'> 		recalculate_timing = amdgpu_freesync_vid_mode &amp;&amp;</div><div class='ctx'> 				 is_freesync_video_mode(&amp;mode, aconnector);</div><div class='hunk'>@@ -6289,10 +7336,12 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 		stream-&gt;timing = *aconnector-&gt;timing_requested;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> 	/* SST DSC determination policy */</div><div class='ctx'> 	update_dsc_caps(aconnector, sink, stream, &amp;dsc_caps);</div><div class='ctx'> 	if (aconnector-&gt;dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE &amp;&amp; dsc_caps.is_dsc_supported)</div><div class='ctx'> 		apply_dsc_policy_for_stream(aconnector, sink, stream, &amp;dsc_caps);</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> 	update_stream_scaling_settings(&amp;mode, dm_state, stream);</div><div class='ctx'> </div><div class='hunk'>@@ -6305,27 +7354,31 @@ create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;signal == SIGNAL_TYPE_HDMI_TYPE_A)</div><div class='ctx'> 		mod_build_hf_vsif_infopacket(stream, &amp;stream-&gt;vsp_infopacket);</div><div class='del'>-	else if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT ||</div><div class='del'>-			 stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||</div><div class='del'>-			 stream-&gt;signal == SIGNAL_TYPE_EDP) {</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT ||</div><div class='add'>+	    stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||</div><div class='add'>+	    stream-&gt;signal == SIGNAL_TYPE_EDP) {</div><div class='add'>+		const struct dc_edid_caps *edid_caps;</div><div class='add'>+		unsigned int disable_colorimetry = 0;</div><div class='add'>+</div><div class='add'>+		if (aconnector-&gt;dc_sink) {</div><div class='add'>+			edid_caps = &amp;aconnector-&gt;dc_sink-&gt;edid_caps;</div><div class='add'>+			disable_colorimetry = edid_caps-&gt;panel_patch.disable_colorimetry;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		//</div><div class='ctx'> 		// should decide stream support vsc sdp colorimetry capability</div><div class='ctx'> 		// before building vsc info packet</div><div class='ctx'> 		//</div><div class='del'>-		stream-&gt;use_vsc_sdp_for_colorimetry = false;</div><div class='del'>-		if (aconnector-&gt;dc_sink-&gt;sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='del'>-			stream-&gt;use_vsc_sdp_for_colorimetry =</div><div class='del'>-				aconnector-&gt;dc_sink-&gt;is_vsc_sdp_colorimetry_supported;</div><div class='del'>-		} else {</div><div class='del'>-			if (stream-&gt;link-&gt;dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)</div><div class='del'>-				stream-&gt;use_vsc_sdp_for_colorimetry = true;</div><div class='del'>-		}</div><div class='del'>-		if (stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_GAMMA22)</div><div class='add'>+		stream-&gt;use_vsc_sdp_for_colorimetry = stream-&gt;link-&gt;dpcd_caps.dpcd_rev.raw &gt;= 0x14 &amp;&amp;</div><div class='add'>+						      stream-&gt;link-&gt;dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &amp;&amp;</div><div class='add'>+						      !disable_colorimetry;</div><div class='add'>+</div><div class='add'>+		if (stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)</div><div class='ctx'> 			tf = TRANSFER_FUNC_GAMMA_22;</div><div class='ctx'> 		mod_build_vsc_infopacket(stream, &amp;stream-&gt;vsc_infopacket, stream-&gt;output_color_space, tf);</div><div class='add'>+		aconnector-&gt;sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;</div><div class='ctx'> </div><div class='del'>-		if (stream-&gt;link-&gt;psr_settings.psr_feature_enabled)</div><div class='del'>-			aconnector-&gt;psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;</div><div class='ctx'> 	}</div><div class='ctx'> finish:</div><div class='ctx'> 	dc_sink_release(sink);</div><div class='hunk'>@@ -6333,29 +7386,117 @@ finish:</div><div class='ctx'> 	return stream;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_connector_poll - Poll a connector to see if it's connected to a display</div><div class='add'>+ * @aconnector: DM connector to poll (owns @base drm_connector and @dc_link)</div><div class='add'>+ * @force: if true, force polling even when DAC load detection was used</div><div class='add'>+ *</div><div class='add'>+ * Used for connectors that don't support HPD (hotplug detection) to</div><div class='add'>+ * periodically check whether the connector is connected to a display.</div><div class='add'>+ *</div><div class='add'>+ * When connection was determined via DAC load detection, we avoid</div><div class='add'>+ * re-running it on normal polls to prevent visible glitches, unless</div><div class='add'>+ * @force is set.</div><div class='add'>+ *</div><div class='add'>+ * Return: The probed connector status (connected/disconnected/unknown).</div><div class='add'>+ */</div><div class='ctx'> static enum drm_connector_status</div><div class='del'>-amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)</div><div class='add'>+amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force)</div><div class='ctx'> {</div><div class='del'>-	bool connected;</div><div class='del'>-	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct dc_link *link = aconnector-&gt;dc_link;</div><div class='add'>+	enum dc_connection_type conn_type = dc_connection_none;</div><div class='add'>+	enum drm_connector_status status = connector_status_disconnected;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Notes:</div><div class='del'>-	 * 1. This interface is NOT called in context of HPD irq.</div><div class='del'>-	 * 2. This interface *is called* in context of user-mode ioctl. Which</div><div class='del'>-	 * makes it a bad place for *any* MST-related activity.</div><div class='add'>+	/* When we determined the connection using DAC load detection,</div><div class='add'>+	 * do NOT poll the connector do detect disconnect because</div><div class='add'>+	 * that would run DAC load detection again which can cause</div><div class='add'>+	 * visible visual glitches.</div><div class='add'>+	 *</div><div class='add'>+	 * Only allow to poll such a connector again when forcing.</div><div class='ctx'> 	 */</div><div class='add'>+	if (!force &amp;&amp; link-&gt;local_sink &amp;&amp; link-&gt;type == dc_connection_dac_load)</div><div class='add'>+		return connector-&gt;status;</div><div class='ctx'> </div><div class='del'>-	if (aconnector-&gt;base.force == DRM_FORCE_UNSPECIFIED &amp;&amp;</div><div class='del'>-	    !aconnector-&gt;fake_enable)</div><div class='del'>-		connected = (aconnector-&gt;dc_sink != NULL);</div><div class='del'>-	else</div><div class='del'>-		connected = (aconnector-&gt;base.force == DRM_FORCE_ON ||</div><div class='del'>-				aconnector-&gt;base.force == DRM_FORCE_ON_DIGITAL);</div><div class='add'>+	mutex_lock(&amp;aconnector-&gt;hpd_lock);</div><div class='add'>+</div><div class='add'>+	if (dc_link_detect_connection_type(aconnector-&gt;dc_link, &amp;conn_type) &amp;&amp;</div><div class='add'>+	    conn_type != dc_connection_none) {</div><div class='add'>+		mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='add'>+</div><div class='add'>+		/* Only call full link detection when a sink isn't created yet,</div><div class='add'>+		 * ie. just when the display is plugged in, otherwise we risk flickering.</div><div class='add'>+		 */</div><div class='add'>+		if (link-&gt;local_sink ||</div><div class='add'>+			dc_link_detect(link, DETECT_REASON_HPD))</div><div class='add'>+			status = connector_status_connected;</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (connector-&gt;status != status) {</div><div class='add'>+		if (status == connector_status_disconnected) {</div><div class='add'>+			if (link-&gt;local_sink)</div><div class='add'>+				dc_sink_release(link-&gt;local_sink);</div><div class='add'>+</div><div class='add'>+			link-&gt;local_sink = NULL;</div><div class='add'>+			link-&gt;dpcd_sink_count = 0;</div><div class='add'>+			link-&gt;type = dc_connection_none;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		amdgpu_dm_update_connector_after_detect(aconnector);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;aconnector-&gt;hpd_lock);</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display</div><div class='add'>+ *</div><div class='add'>+ * A connector is considered connected when it has a sink that is not NULL.</div><div class='add'>+ * For connectors that support HPD (hotplug detection), the connection is</div><div class='add'>+ * handled in the HPD interrupt.</div><div class='add'>+ * For connectors that may not support HPD, such as analog connectors,</div><div class='add'>+ * DRM will call this function repeatedly to poll them.</div><div class='add'>+ *</div><div class='add'>+ * Notes:</div><div class='add'>+ * 1. This interface is NOT called in context of HPD irq.</div><div class='add'>+ * 2. This interface *is called* in context of user-mode ioctl. Which</div><div class='add'>+ *    makes it a bad place for *any* MST-related activity.</div><div class='add'>+ *</div><div class='add'>+ * @connector: The DRM connector we are checking. We convert it to</div><div class='add'>+ *             amdgpu_dm_connector so we can read the DC link and state.</div><div class='add'>+ * @force:     If true, do a full detect again. This is used even when</div><div class='add'>+ *             a lighter check would normally be used to avoid flicker.</div><div class='add'>+ *</div><div class='add'>+ * Return: The connector status (connected, disconnected, or unknown).</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static enum drm_connector_status</div><div class='add'>+amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 	update_subconnector_property(aconnector);</div><div class='ctx'> </div><div class='del'>-	return (connected ? connector_status_connected :</div><div class='add'>+	if (aconnector-&gt;base.force == DRM_FORCE_ON ||</div><div class='add'>+		aconnector-&gt;base.force == DRM_FORCE_ON_DIGITAL)</div><div class='add'>+		return connector_status_connected;</div><div class='add'>+	else if (aconnector-&gt;base.force == DRM_FORCE_OFF)</div><div class='add'>+		return connector_status_disconnected;</div><div class='add'>+</div><div class='add'>+	/* Poll analog connectors and only when either</div><div class='add'>+	 * disconnected or connected to an analog display.</div><div class='add'>+	 */</div><div class='add'>+	if (drm_kms_helper_is_poll_worker() &amp;&amp;</div><div class='add'>+		dc_connector_supports_analog(aconnector-&gt;dc_link-&gt;link_id.id) &amp;&amp;</div><div class='add'>+		(!aconnector-&gt;dc_sink || aconnector-&gt;dc_sink-&gt;edid_caps.analog))</div><div class='add'>+		return amdgpu_dm_connector_poll(aconnector, force);</div><div class='add'>+</div><div class='add'>+	return (aconnector-&gt;dc_sink ? connector_status_connected :</div><div class='ctx'> 			connector_status_disconnected);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6406,6 +7547,20 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,</div><div class='ctx'> 	} else if (property == adev-&gt;mode_info.underscan_property) {</div><div class='ctx'> 		dm_new_state-&gt;underscan_enable = val;</div><div class='ctx'> 		ret = 0;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.abm_level_property) {</div><div class='add'>+		switch (val) {</div><div class='add'>+		case ABM_SYSFS_CONTROL:</div><div class='add'>+			dm_new_state-&gt;abm_sysfs_forbidden = false;</div><div class='add'>+			break;</div><div class='add'>+		case ABM_LEVEL_OFF:</div><div class='add'>+			dm_new_state-&gt;abm_sysfs_forbidden = true;</div><div class='add'>+			dm_new_state-&gt;abm_level = ABM_LEVEL_IMMEDIATE_DISABLE;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			dm_new_state-&gt;abm_sysfs_forbidden = true;</div><div class='add'>+			dm_new_state-&gt;abm_level = val;</div><div class='add'>+		}</div><div class='add'>+		ret = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -6448,6 +7603,13 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,</div><div class='ctx'> 	} else if (property == adev-&gt;mode_info.underscan_property) {</div><div class='ctx'> 		*val = dm_state-&gt;underscan_enable;</div><div class='ctx'> 		ret = 0;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.abm_level_property) {</div><div class='add'>+		if (!dm_state-&gt;abm_sysfs_forbidden)</div><div class='add'>+			*val = ABM_SYSFS_CONTROL;</div><div class='add'>+		else</div><div class='add'>+			*val = (dm_state-&gt;abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?</div><div class='add'>+				dm_state-&gt;abm_level : 0;</div><div class='add'>+		ret = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -6500,10 +7662,16 @@ static ssize_t panel_power_savings_store(struct device *device,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	drm_modeset_lock(&amp;dev-&gt;mode_config.connection_mutex, NULL);</div><div class='del'>-	to_dm_connector_state(connector-&gt;state)-&gt;abm_level = val ?:</div><div class='del'>-		ABM_LEVEL_IMMEDIATE_DISABLE;</div><div class='add'>+	if (to_dm_connector_state(connector-&gt;state)-&gt;abm_sysfs_forbidden)</div><div class='add'>+		ret = -EBUSY;</div><div class='add'>+	else</div><div class='add'>+		to_dm_connector_state(connector-&gt;state)-&gt;abm_level = val ?:</div><div class='add'>+			ABM_LEVEL_IMMEDIATE_DISABLE;</div><div class='ctx'> 	drm_modeset_unlock(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='ctx'> </div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	drm_kms_helper_hotplug_event(dev);</div><div class='ctx'> </div><div class='ctx'> 	return count;</div><div class='hunk'>@@ -6521,14 +7689,37 @@ static const struct attribute_group amdgpu_group = {</div><div class='ctx'> 	.attrs = amdgpu_attrs</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static bool</div><div class='add'>+amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_dm_abm_level &gt;= 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dm_connector-&gt;base.connector_type != DRM_MODE_CONNECTOR_eDP)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* check for OLED panels */</div><div class='add'>+	if (amdgpu_dm_connector-&gt;bl_idx &gt;= 0) {</div><div class='add'>+		struct drm_device *drm = amdgpu_dm_connector-&gt;base.dev;</div><div class='add'>+		struct amdgpu_display_manager *dm = &amp;drm_to_adev(drm)-&gt;dm;</div><div class='add'>+		struct amdgpu_dm_backlight_caps *caps;</div><div class='add'>+</div><div class='add'>+		caps = &amp;dm-&gt;backlight_caps[amdgpu_dm_connector-&gt;bl_idx];</div><div class='add'>+		if (caps-&gt;aux_support)</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_connector_unregister(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP &amp;&amp;</div><div class='del'>-	    amdgpu_dm_abm_level &lt; 0)</div><div class='add'>+	if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector))</div><div class='ctx'> 		sysfs_remove_group(&amp;connector-&gt;kdev-&gt;kobj, &amp;amdgpu_group);</div><div class='ctx'> </div><div class='add'>+	cec_notifier_conn_unregister(amdgpu_dm_connector-&gt;notifier);</div><div class='ctx'> 	drm_dp_aux_unregister(&amp;amdgpu_dm_connector-&gt;dm_dp_aux.aux);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6545,6 +7736,13 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)</div><div class='ctx'> 	if (aconnector-&gt;mst_mgr.dev)</div><div class='ctx'> 		drm_dp_mst_topology_mgr_destroy(&amp;aconnector-&gt;mst_mgr);</div><div class='ctx'> </div><div class='add'>+	/* Cancel and flush any pending HDMI HPD debounce work */</div><div class='add'>+	cancel_delayed_work_sync(&amp;aconnector-&gt;hdmi_hpd_debounce_work);</div><div class='add'>+	if (aconnector-&gt;hdmi_prev_sink) {</div><div class='add'>+		dc_sink_release(aconnector-&gt;hdmi_prev_sink);</div><div class='add'>+		aconnector-&gt;hdmi_prev_sink = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (aconnector-&gt;bl_idx != -1) {</div><div class='ctx'> 		backlight_device_unregister(dm-&gt;backlight_dev[aconnector-&gt;bl_idx]);</div><div class='ctx'> 		dm-&gt;backlight_dev[aconnector-&gt;bl_idx] = NULL;</div><div class='hunk'>@@ -6560,10 +7758,6 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)</div><div class='ctx'> 	drm_dp_cec_unregister_connector(&amp;aconnector-&gt;dm_dp_aux.aux);</div><div class='ctx'> 	drm_connector_unregister(connector);</div><div class='ctx'> 	drm_connector_cleanup(connector);</div><div class='del'>-	if (aconnector-&gt;i2c) {</div><div class='del'>-		i2c_del_adapter(&amp;aconnector-&gt;i2c-&gt;base);</div><div class='del'>-		kfree(aconnector-&gt;i2c);</div><div class='del'>-	}</div><div class='ctx'> 	kfree(aconnector-&gt;dm_dp_aux.aux.name);</div><div class='ctx'> </div><div class='ctx'> 	kfree(connector);</div><div class='hunk'>@@ -6633,8 +7827,7 @@ amdgpu_dm_connector_late_register(struct drm_connector *connector)</div><div class='ctx'> 		to_amdgpu_dm_connector(connector);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP &amp;&amp;</div><div class='del'>-	    amdgpu_dm_abm_level &lt; 0) {</div><div class='add'>+	if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) {</div><div class='ctx'> 		r = sysfs_create_group(&amp;connector-&gt;kdev-&gt;kobj,</div><div class='ctx'> 				       &amp;amdgpu_group);</div><div class='ctx'> 		if (r)</div><div class='hunk'>@@ -6663,32 +7856,31 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 	struct dc_link *dc_link = aconnector-&gt;dc_link;</div><div class='ctx'> 	struct dc_sink *dc_em_sink = aconnector-&gt;dc_em_sink;</div><div class='del'>-	struct edid *edid;</div><div class='add'>+	const struct drm_edid *drm_edid;</div><div class='ctx'> 	struct i2c_adapter *ddc;</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	if (dc_link &amp;&amp; dc_link-&gt;aux_mode)</div><div class='ctx'> 		ddc = &amp;aconnector-&gt;dm_dp_aux.aux.ddc;</div><div class='ctx'> 	else</div><div class='ctx'> 		ddc = &amp;aconnector-&gt;i2c-&gt;base;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Note: drm_get_edid gets edid in the following order:</div><div class='del'>-	 * 1) override EDID if set via edid_override debugfs,</div><div class='del'>-	 * 2) firmware EDID if set via edid_firmware module parameter</div><div class='del'>-	 * 3) regular DDC read.</div><div class='del'>-	 */</div><div class='del'>-	edid = drm_get_edid(connector, ddc);</div><div class='del'>-	if (!edid) {</div><div class='del'>-		DRM_ERROR("No EDID found on connector: %s.\n", connector-&gt;name);</div><div class='add'>+	drm_edid = drm_edid_read_ddc(connector, ddc);</div><div class='add'>+	drm_edid_connector_update(connector, drm_edid);</div><div class='add'>+	if (!drm_edid) {</div><div class='add'>+		drm_err(dev, "No EDID found on connector: %s.\n", connector-&gt;name);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	aconnector-&gt;edid = edid;</div><div class='del'>-</div><div class='add'>+	aconnector-&gt;drm_edid = drm_edid;</div><div class='ctx'> 	/* Update emulated (virtual) sink's EDID */</div><div class='ctx'> 	if (dc_em_sink &amp;&amp; dc_link) {</div><div class='add'>+		// FIXME: Get rid of drm_edid_raw()</div><div class='add'>+		const struct edid *edid = drm_edid_raw(drm_edid);</div><div class='add'>+</div><div class='ctx'> 		memset(&amp;dc_em_sink-&gt;edid_caps, 0, sizeof(struct dc_edid_caps));</div><div class='del'>-		memmove(dc_em_sink-&gt;dc_edid.raw_edid, edid, (edid-&gt;extensions + 1) * EDID_LENGTH);</div><div class='add'>+		memmove(dc_em_sink-&gt;dc_edid.raw_edid, edid,</div><div class='add'>+			(edid-&gt;extensions + 1) * EDID_LENGTH);</div><div class='ctx'> 		dm_helpers_parse_edid_caps(</div><div class='ctx'> 			dc_link,</div><div class='ctx'> 			&amp;dc_em_sink-&gt;dc_edid,</div><div class='hunk'>@@ -6723,31 +7915,28 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 			.link = aconnector-&gt;dc_link,</div><div class='ctx'> 			.sink_signal = SIGNAL_TYPE_VIRTUAL</div><div class='ctx'> 	};</div><div class='del'>-	struct edid *edid;</div><div class='add'>+	const struct drm_edid *drm_edid;</div><div class='add'>+	const struct edid *edid;</div><div class='ctx'> 	struct i2c_adapter *ddc;</div><div class='ctx'> </div><div class='del'>-	if (dc_link-&gt;aux_mode)</div><div class='add'>+	if (dc_link &amp;&amp; dc_link-&gt;aux_mode)</div><div class='ctx'> 		ddc = &amp;aconnector-&gt;dm_dp_aux.aux.ddc;</div><div class='ctx'> 	else</div><div class='ctx'> 		ddc = &amp;aconnector-&gt;i2c-&gt;base;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Note: drm_get_edid gets edid in the following order:</div><div class='del'>-	 * 1) override EDID if set via edid_override debugfs,</div><div class='del'>-	 * 2) firmware EDID if set via edid_firmware module parameter</div><div class='del'>-	 * 3) regular DDC read.</div><div class='del'>-	 */</div><div class='del'>-	edid = drm_get_edid(connector, ddc);</div><div class='del'>-	if (!edid) {</div><div class='del'>-		DRM_ERROR("No EDID found on connector: %s.\n", connector-&gt;name);</div><div class='add'>+	drm_edid = drm_edid_read_ddc(connector, ddc);</div><div class='add'>+	drm_edid_connector_update(connector, drm_edid);</div><div class='add'>+	if (!drm_edid) {</div><div class='add'>+		drm_err(connector-&gt;dev, "No EDID found on connector: %s.\n", connector-&gt;name);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (drm_detect_hdmi_monitor(edid))</div><div class='add'>+	if (connector-&gt;display_info.is_hdmi)</div><div class='ctx'> 		init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='ctx'> </div><div class='del'>-	aconnector-&gt;edid = edid;</div><div class='add'>+	aconnector-&gt;drm_edid = drm_edid;</div><div class='ctx'> </div><div class='add'>+	edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()</div><div class='ctx'> 	aconnector-&gt;dc_em_sink = dc_link_add_remote_sink(</div><div class='ctx'> 		aconnector-&gt;dc_link,</div><div class='ctx'> 		(uint8_t *)edid,</div><div class='hunk'>@@ -6758,7 +7947,8 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> 		aconnector-&gt;dc_sink = aconnector-&gt;dc_link-&gt;local_sink ?</div><div class='ctx'> 		aconnector-&gt;dc_link-&gt;local_sink :</div><div class='ctx'> 		aconnector-&gt;dc_em_sink;</div><div class='del'>-		dc_sink_retain(aconnector-&gt;dc_sink);</div><div class='add'>+		if (aconnector-&gt;dc_sink)</div><div class='add'>+			dc_sink_retain(aconnector-&gt;dc_sink);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6792,7 +7982,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,</div><div class='ctx'> 	if (!dc_plane_state)</div><div class='ctx'> 		goto cleanup;</div><div class='ctx'> </div><div class='del'>-	dc_state = dc_state_create(dc);</div><div class='add'>+	dc_state = dc_state_create(dc, NULL);</div><div class='ctx'> 	if (!dc_state)</div><div class='ctx'> 		goto cleanup;</div><div class='ctx'> </div><div class='hunk'>@@ -6829,7 +8019,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,</div><div class='ctx'> 		dc_result = DC_FAIL_ATTACH_SURFACES;</div><div class='ctx'> </div><div class='ctx'> 	if (dc_result == DC_OK)</div><div class='del'>-		dc_result = dc_validate_global_state(dc, dc_state, true);</div><div class='add'>+		dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY);</div><div class='ctx'> </div><div class='ctx'> cleanup:</div><div class='ctx'> 	if (dc_state)</div><div class='hunk'>@@ -6842,31 +8032,45 @@ cleanup:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct dc_stream_state *</div><div class='del'>-create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='add'>+create_validate_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 				const struct drm_display_mode *drm_mode,</div><div class='ctx'> 				const struct dm_connector_state *dm_state,</div><div class='ctx'> 				const struct dc_stream_state *old_stream)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(connector-&gt;dev);</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='ctx'> 	const struct drm_connector_state *drm_state = dm_state ? &amp;dm_state-&gt;base : NULL;</div><div class='ctx'> 	int requested_bpc = drm_state ? drm_state-&gt;max_requested_bpc : 8;</div><div class='ctx'> 	enum dc_status dc_result = DC_OK;</div><div class='add'>+	uint8_t bpc_limit = 6;</div><div class='add'>+</div><div class='add'>+	if (!dm_state)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='add'>+	if (aconnector &amp;&amp;</div><div class='add'>+	    (aconnector-&gt;dc_link-&gt;connector_signal == SIGNAL_TYPE_HDMI_TYPE_A ||</div><div class='add'>+	     aconnector-&gt;dc_link-&gt;dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER))</div><div class='add'>+		bpc_limit = 8;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='add'>+		drm_dbg_kms(connector-&gt;dev, "Trying with %d bpc\n", requested_bpc);</div><div class='ctx'> 		stream = create_stream_for_sink(connector, drm_mode,</div><div class='ctx'> 						dm_state, old_stream,</div><div class='ctx'> 						requested_bpc);</div><div class='ctx'> 		if (stream == NULL) {</div><div class='del'>-			DRM_ERROR("Failed to create stream for sink!\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to create stream for sink!\n");</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (aconnector-&gt;base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		dc_result = dc_validate_stream(adev-&gt;dm.dc, stream);</div><div class='add'>+</div><div class='add'>+		if (!aconnector) /* writeback connector */</div><div class='ctx'> 			return stream;</div><div class='ctx'> </div><div class='del'>-		dc_result = dc_validate_stream(adev-&gt;dm.dc, stream);</div><div class='ctx'> 		if (dc_result == DC_OK &amp;&amp; stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 			dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);</div><div class='ctx'> </div><div class='hunk'>@@ -6874,11 +8078,12 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 			dc_result = dm_validate_stream_and_context(adev-&gt;dm.dc, stream);</div><div class='ctx'> </div><div class='ctx'> 		if (dc_result != DC_OK) {</div><div class='del'>-			DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",</div><div class='add'>+			DRM_DEBUG_KMS("Pruned mode %d x %d (clk %d) %s %s -- %s\n",</div><div class='ctx'> 				      drm_mode-&gt;hdisplay,</div><div class='ctx'> 				      drm_mode-&gt;vdisplay,</div><div class='ctx'> 				      drm_mode-&gt;clock,</div><div class='del'>-				      dc_result,</div><div class='add'>+				      dc_pixel_encoding_to_str(stream-&gt;timing.pixel_encoding),</div><div class='add'>+				      dc_color_depth_to_str(stream-&gt;timing.display_color_depth),</div><div class='ctx'> 				      dc_status_to_str(dc_result));</div><div class='ctx'> </div><div class='ctx'> 			dc_stream_release(stream);</div><div class='hunk'>@@ -6886,27 +8091,59 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 			requested_bpc -= 2; /* lower bpc to retry validation */</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-	} while (stream == NULL &amp;&amp; requested_bpc &gt;= 6);</div><div class='del'>-</div><div class='del'>-	if (dc_result == DC_FAIL_ENC_VALIDATE &amp;&amp; !aconnector-&gt;force_yuv420_output) {</div><div class='del'>-		DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");</div><div class='add'>+	} while (stream == NULL &amp;&amp; requested_bpc &gt;= bpc_limit);</div><div class='ctx'> </div><div class='del'>-		aconnector-&gt;force_yuv420_output = true;</div><div class='del'>-		stream = create_validate_stream_for_sink(aconnector, drm_mode,</div><div class='del'>-						dm_state, old_stream);</div><div class='add'>+	switch (dc_result) {</div><div class='add'>+	/*</div><div class='add'>+	 * If we failed to validate DP bandwidth stream with the requested RGB color depth,</div><div class='add'>+	 * we try to fallback and configure in order:</div><div class='add'>+	 * YUV422 (8bpc, 6bpc)</div><div class='add'>+	 * YUV420 (8bpc, 6bpc)</div><div class='add'>+	 */</div><div class='add'>+	case DC_FAIL_ENC_VALIDATE:</div><div class='add'>+	case DC_EXCEED_DONGLE_CAP:</div><div class='add'>+	case DC_NO_DP_LINK_BANDWIDTH:</div><div class='add'>+		/* recursively entered twice and already tried both YUV422 and YUV420 */</div><div class='add'>+		if (aconnector-&gt;force_yuv422_output &amp;&amp; aconnector-&gt;force_yuv420_output)</div><div class='add'>+			break;</div><div class='add'>+		/* first failure; try YUV422 */</div><div class='add'>+		if (!aconnector-&gt;force_yuv422_output) {</div><div class='add'>+			drm_dbg_kms(connector-&gt;dev, "%s:%d Validation failed with %d, retrying w/ YUV422\n",</div><div class='add'>+				    __func__, __LINE__, dc_result);</div><div class='add'>+			aconnector-&gt;force_yuv422_output = true;</div><div class='add'>+		/* recursively entered and YUV422 failed, try YUV420 */</div><div class='add'>+		} else if (!aconnector-&gt;force_yuv420_output) {</div><div class='add'>+			drm_dbg_kms(connector-&gt;dev, "%s:%d Validation failed with %d, retrying w/ YUV420\n",</div><div class='add'>+				    __func__, __LINE__, dc_result);</div><div class='add'>+			aconnector-&gt;force_yuv420_output = true;</div><div class='add'>+		}</div><div class='add'>+		stream = create_validate_stream_for_sink(connector, drm_mode,</div><div class='add'>+							 dm_state, old_stream);</div><div class='add'>+		aconnector-&gt;force_yuv422_output = false;</div><div class='ctx'> 		aconnector-&gt;force_yuv420_output = false;</div><div class='add'>+		break;</div><div class='add'>+	case DC_OK:</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_dbg_kms(connector-&gt;dev, "%s:%d Unhandled validation failure %d\n",</div><div class='add'>+			    __func__, __LINE__, dc_result);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return stream;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,</div><div class='del'>-				   struct drm_display_mode *mode)</div><div class='add'>+				   const struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	int result = MODE_ERROR;</div><div class='ctx'> 	struct dc_sink *dc_sink;</div><div class='add'>+	struct drm_display_mode *test_mode;</div><div class='ctx'> 	/* TODO: Unhardcode stream count */</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='add'>+	/* we always have an amdgpu_dm_connector here since we got</div><div class='add'>+	 * here via the amdgpu_dm_connector_helper_funcs</div><div class='add'>+	 */</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 	if ((mode-&gt;flags &amp; DRM_MODE_FLAG_INTERLACE) ||</div><div class='hunk'>@@ -6925,15 +8162,20 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec</div><div class='ctx'> </div><div class='ctx'> 	if (dc_sink == NULL &amp;&amp; aconnector-&gt;base.force != DRM_FORCE_ON_DIGITAL &amp;&amp;</div><div class='ctx'> 				aconnector-&gt;base.force != DRM_FORCE_ON) {</div><div class='del'>-		DRM_ERROR("dc_sink is NULL!\n");</div><div class='add'>+		drm_err(connector-&gt;dev, "dc_sink is NULL!\n");</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	drm_mode_set_crtcinfo(mode, 0);</div><div class='add'>+	test_mode = drm_mode_duplicate(connector-&gt;dev, mode);</div><div class='add'>+	if (!test_mode)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	drm_mode_set_crtcinfo(test_mode, 0);</div><div class='ctx'> </div><div class='del'>-	stream = create_validate_stream_for_sink(aconnector, mode,</div><div class='add'>+	stream = create_validate_stream_for_sink(connector, test_mode,</div><div class='ctx'> 						 to_dm_connector_state(connector-&gt;state),</div><div class='ctx'> 						 NULL);</div><div class='add'>+	drm_mode_destroy(connector-&gt;dev, test_mode);</div><div class='ctx'> 	if (stream) {</div><div class='ctx'> 		dc_stream_release(stream);</div><div class='ctx'> 		result = MODE_OK;</div><div class='hunk'>@@ -7016,6 +8258,9 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn,</div><div class='ctx'> 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (WARN_ON(unlikely(!old_con_state || !new_con_state)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	trace_amdgpu_dm_connector_atomic_check(new_con_state);</div><div class='ctx'> </div><div class='ctx'> 	if (conn-&gt;connector_type == DRM_MODE_CONNECTOR_DisplayPort) {</div><div class='hunk'>@@ -7027,6 +8272,14 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn,</div><div class='ctx'> 	if (!crtc)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (new_con_state-&gt;privacy_screen_sw_state != old_con_state-&gt;privacy_screen_sw_state) {</div><div class='add'>+		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);</div><div class='add'>+		if (IS_ERR(new_crtc_state))</div><div class='add'>+			return PTR_ERR(new_crtc_state);</div><div class='add'>+</div><div class='add'>+		new_crtc_state-&gt;mode_changed = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (new_con_state-&gt;colorspace != old_con_state-&gt;colorspace) {</div><div class='ctx'> 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);</div><div class='ctx'> 		if (IS_ERR(new_crtc_state))</div><div class='hunk'>@@ -7128,6 +8381,23 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,</div><div class='ctx'> 	int clock, bpp = 0;</div><div class='ctx'> 	bool is_y420 = false;</div><div class='ctx'> </div><div class='add'>+	if ((connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP) ||</div><div class='add'>+	    (connector-&gt;connector_type == DRM_MODE_CONNECTOR_LVDS)) {</div><div class='add'>+		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);</div><div class='add'>+		struct drm_display_mode *native_mode = &amp;amdgpu_encoder-&gt;native_mode;</div><div class='add'>+		enum drm_mode_status result;</div><div class='add'>+</div><div class='add'>+		result = drm_crtc_helper_mode_valid_fixed(encoder-&gt;crtc, adjusted_mode, native_mode);</div><div class='add'>+		if (result != MODE_OK &amp;&amp; dm_new_connector_state-&gt;scaling == RMX_OFF) {</div><div class='add'>+			drm_dbg_driver(encoder-&gt;dev,</div><div class='add'>+				       "mode %dx%d@%dHz is not native, enabling scaling\n",</div><div class='add'>+				       adjusted_mode-&gt;hdisplay, adjusted_mode-&gt;vdisplay,</div><div class='add'>+				       drm_mode_vrefresh(adjusted_mode));</div><div class='add'>+			dm_new_connector_state-&gt;scaling = RMX_ASPECT;</div><div class='add'>+		}</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!aconnector-&gt;mst_output_port)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -7141,7 +8411,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,</div><div class='ctx'> 	if (IS_ERR(mst_state))</div><div class='ctx'> 		return PTR_ERR(mst_state);</div><div class='ctx'> </div><div class='del'>-	mst_state-&gt;pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector-&gt;mst_root-&gt;dc_link));</div><div class='add'>+	mst_state-&gt;pbn_div.full = dm_mst_get_pbn_divider(aconnector-&gt;mst_root-&gt;dc_link);</div><div class='ctx'> </div><div class='ctx'> 	if (!state-&gt;duplicated) {</div><div class='ctx'> 		int max_bpc = conn_state-&gt;max_requested_bpc;</div><div class='hunk'>@@ -7181,7 +8451,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	struct dm_connector_state *dm_conn_state;</div><div class='ctx'> 	int i, j, ret;</div><div class='del'>-	int vcpi, pbn_div, pbn, slot_num = 0;</div><div class='add'>+	int vcpi, pbn_div, pbn = 0, slot_num = 0;</div><div class='ctx'> </div><div class='ctx'> 	for_each_new_connector_in_state(state, connector, new_con_state, i) {</div><div class='ctx'> </div><div class='hunk'>@@ -7221,7 +8491,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (j == dc_state-&gt;stream_count)</div><div class='add'>+		if (j == dc_state-&gt;stream_count || pbn_div == 0)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		slot_num = DIV_ROUND_UP(pbn, pbn_div);</div><div class='hunk'>@@ -7248,7 +8518,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int to_drm_connector_type(enum signal_type st)</div><div class='add'>+static int to_drm_connector_type(enum signal_type st, uint32_t connector_id)</div><div class='ctx'> {</div><div class='ctx'> 	switch (st) {</div><div class='ctx'> 	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='hunk'>@@ -7264,6 +8534,10 @@ static int to_drm_connector_type(enum signal_type st)</div><div class='ctx'> 		return DRM_MODE_CONNECTOR_DisplayPort;</div><div class='ctx'> 	case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='ctx'> 	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+		if (connector_id == CONNECTOR_ID_SINGLE_LINK_DVII ||</div><div class='add'>+			connector_id == CONNECTOR_ID_DUAL_LINK_DVII)</div><div class='add'>+			return DRM_MODE_CONNECTOR_DVII;</div><div class='add'>+</div><div class='ctx'> 		return DRM_MODE_CONNECTOR_DVID;</div><div class='ctx'> 	case SIGNAL_TYPE_VIRTUAL:</div><div class='ctx'> 		return DRM_MODE_CONNECTOR_VIRTUAL;</div><div class='hunk'>@@ -7315,7 +8589,7 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector)</div><div class='ctx'> </div><div class='ctx'> static struct drm_display_mode *</div><div class='ctx'> amdgpu_dm_create_common_mode(struct drm_encoder *encoder,</div><div class='del'>-			     char *name,</div><div class='add'>+			     const char *name,</div><div class='ctx'> 			     int hdisplay, int vdisplay)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = encoder-&gt;dev;</div><div class='hunk'>@@ -7337,6 +8611,24 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct amdgpu_dm_mode_size {</div><div class='add'>+	char name[DRM_DISPLAY_MODE_LEN];</div><div class='add'>+	int w;</div><div class='add'>+	int h;</div><div class='add'>+} common_modes[] = {</div><div class='add'>+	{  "640x480",  640,  480},</div><div class='add'>+	{  "800x600",  800,  600},</div><div class='add'>+	{ "1024x768", 1024,  768},</div><div class='add'>+	{ "1280x720", 1280,  720},</div><div class='add'>+	{ "1280x800", 1280,  800},</div><div class='add'>+	{"1280x1024", 1280, 1024},</div><div class='add'>+	{ "1440x900", 1440,  900},</div><div class='add'>+	{"1680x1050", 1680, 1050},</div><div class='add'>+	{"1600x1200", 1600, 1200},</div><div class='add'>+	{"1920x1080", 1920, 1080},</div><div class='add'>+	{"1920x1200", 1920, 1200}</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,</div><div class='ctx'> 						 struct drm_connector *connector)</div><div class='ctx'> {</div><div class='hunk'>@@ -7347,23 +8639,10 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,</div><div class='ctx'> 				to_amdgpu_dm_connector(connector);</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int n;</div><div class='del'>-	struct mode_size {</div><div class='del'>-		char name[DRM_DISPLAY_MODE_LEN];</div><div class='del'>-		int w;</div><div class='del'>-		int h;</div><div class='del'>-	} common_modes[] = {</div><div class='del'>-		{  "640x480",  640,  480},</div><div class='del'>-		{  "800x600",  800,  600},</div><div class='del'>-		{ "1024x768", 1024,  768},</div><div class='del'>-		{ "1280x720", 1280,  720},</div><div class='del'>-		{ "1280x800", 1280,  800},</div><div class='del'>-		{"1280x1024", 1280, 1024},</div><div class='del'>-		{ "1440x900", 1440,  900},</div><div class='del'>-		{"1680x1050", 1680, 1050},</div><div class='del'>-		{"1600x1200", 1600, 1200},</div><div class='del'>-		{"1920x1080", 1920, 1080},</div><div class='del'>-		{"1920x1200", 1920, 1200}</div><div class='del'>-	};</div><div class='add'>+</div><div class='add'>+	if ((connector-&gt;connector_type != DRM_MODE_CONNECTOR_eDP) &amp;&amp;</div><div class='add'>+	    (connector-&gt;connector_type != DRM_MODE_CONNECTOR_LVDS))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	n = ARRAY_SIZE(common_modes);</div><div class='ctx'> </div><div class='hunk'>@@ -7430,16 +8709,16 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,</div><div class='del'>-					      struct edid *edid)</div><div class='add'>+					      const struct drm_edid *drm_edid)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *amdgpu_dm_connector =</div><div class='ctx'> 			to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='del'>-	if (edid) {</div><div class='add'>+	if (drm_edid) {</div><div class='ctx'> 		/* empty probed_modes */</div><div class='ctx'> 		INIT_LIST_HEAD(&amp;connector-&gt;probed_modes);</div><div class='ctx'> 		amdgpu_dm_connector-&gt;num_modes =</div><div class='del'>-				drm_add_edid_modes(connector, edid);</div><div class='add'>+				drm_edid_connector_add_modes(connector);</div><div class='ctx'> </div><div class='ctx'> 		/* sorting the probed modes before calling function</div><div class='ctx'> 		 * amdgpu_dm_get_native_mode() since EDID can have</div><div class='hunk'>@@ -7453,10 +8732,10 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,</div><div class='ctx'> 		amdgpu_dm_get_native_mode(connector);</div><div class='ctx'> </div><div class='ctx'> 		/* Freesync capabilities are reset by calling</div><div class='del'>-		 * drm_add_edid_modes() and need to be</div><div class='add'>+		 * drm_edid_connector_add_modes() and need to be</div><div class='ctx'> 		 * restored here.</div><div class='ctx'> 		 */</div><div class='del'>-		amdgpu_dm_update_freesync_caps(connector, edid);</div><div class='add'>+		amdgpu_dm_update_freesync_caps(connector, drm_edid);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		amdgpu_dm_connector-&gt;num_modes = 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7552,12 +8831,22 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,</div><div class='del'>-						   struct edid *edid)</div><div class='add'>+						   const struct drm_edid *drm_edid)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *amdgpu_dm_connector =</div><div class='ctx'> 		to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='del'>-	if (!(amdgpu_freesync_vid_mode &amp;&amp; edid))</div><div class='add'>+	if (!(amdgpu_freesync_vid_mode &amp;&amp; drm_edid))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_dm_connector-&gt;dc_sink || !amdgpu_dm_connector-&gt;dc_link)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!dc_supports_vrr(amdgpu_dm_connector-&gt;dc_sink-&gt;ctx-&gt;dce_version))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (dc_connector_supports_analog(amdgpu_dm_connector-&gt;dc_link-&gt;link_id.id) &amp;&amp;</div><div class='add'>+	    amdgpu_dm_connector-&gt;dc_sink-&gt;edid_caps.analog)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_dm_connector-&gt;max_vfreq - amdgpu_dm_connector-&gt;min_vfreq &gt; 10)</div><div class='hunk'>@@ -7569,24 +8858,36 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *amdgpu_dm_connector =</div><div class='ctx'> 			to_amdgpu_dm_connector(connector);</div><div class='add'>+	struct dc_link *dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='ctx'> 	struct drm_encoder *encoder;</div><div class='del'>-	struct edid *edid = amdgpu_dm_connector-&gt;edid;</div><div class='del'>-	struct dc_link_settings *verified_link_cap =</div><div class='del'>-			&amp;amdgpu_dm_connector-&gt;dc_link-&gt;verified_link_cap;</div><div class='del'>-	const struct dc *dc = amdgpu_dm_connector-&gt;dc_link-&gt;dc;</div><div class='add'>+	const struct drm_edid *drm_edid = amdgpu_dm_connector-&gt;drm_edid;</div><div class='add'>+	struct dc_link_settings *verified_link_cap = &amp;dc_link-&gt;verified_link_cap;</div><div class='add'>+	const struct dc *dc = dc_link-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	encoder = amdgpu_dm_connector_to_encoder(connector);</div><div class='ctx'> </div><div class='del'>-	if (!drm_edid_is_valid(edid)) {</div><div class='add'>+	if (!drm_edid) {</div><div class='ctx'> 		amdgpu_dm_connector-&gt;num_modes =</div><div class='ctx'> 				drm_add_modes_noedid(connector, 640, 480);</div><div class='ctx'> 		if (dc-&gt;link_srv-&gt;dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)</div><div class='ctx'> 			amdgpu_dm_connector-&gt;num_modes +=</div><div class='ctx'> 				drm_add_modes_noedid(connector, 1920, 1080);</div><div class='add'>+</div><div class='add'>+		if (amdgpu_dm_connector-&gt;dc_sink &amp;&amp;</div><div class='add'>+		    amdgpu_dm_connector-&gt;dc_sink-&gt;edid_caps.analog &amp;&amp;</div><div class='add'>+		    dc_connector_supports_analog(dc_link-&gt;link_id.id)) {</div><div class='add'>+			/* Analog monitor connected by DAC load detection.</div><div class='add'>+			 * Add common modes. It will be up to the user to select one that works.</div><div class='add'>+			 */</div><div class='add'>+			for (int i = 0; i &lt; ARRAY_SIZE(common_modes); i++)</div><div class='add'>+				amdgpu_dm_connector-&gt;num_modes += drm_add_modes_noedid(</div><div class='add'>+					connector, common_modes[i].w, common_modes[i].h);</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='del'>-		amdgpu_dm_connector_ddc_get_modes(connector, edid);</div><div class='del'>-		amdgpu_dm_connector_add_common_modes(encoder, connector);</div><div class='del'>-		amdgpu_dm_connector_add_freesync_modes(connector, edid);</div><div class='add'>+		amdgpu_dm_connector_ddc_get_modes(connector, drm_edid);</div><div class='add'>+		if (encoder)</div><div class='add'>+			amdgpu_dm_connector_add_common_modes(encoder, connector);</div><div class='add'>+		amdgpu_dm_connector_add_freesync_modes(connector, drm_edid);</div><div class='ctx'> 	}</div><div class='ctx'> 	amdgpu_dm_fbc_init(connector);</div><div class='ctx'> </div><div class='hunk'>@@ -7629,6 +8930,10 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	mutex_init(&amp;aconnector-&gt;hpd_lock);</div><div class='ctx'> 	mutex_init(&amp;aconnector-&gt;handle_mst_msg_ready);</div><div class='ctx'> </div><div class='add'>+	aconnector-&gt;hdmi_hpd_debounce_delay_ms = AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS;</div><div class='add'>+	INIT_DELAYED_WORK(&amp;aconnector-&gt;hdmi_hpd_debounce_work, hdmi_hpd_debounce_work);</div><div class='add'>+	aconnector-&gt;hdmi_prev_sink = NULL;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * configure support HPD hot plug connector_&gt;polled default value is 0</div><div class='ctx'> 	 * which means HPD hot plug not supported</div><div class='hunk'>@@ -7650,6 +8955,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	case DRM_MODE_CONNECTOR_DVID:</div><div class='ctx'> 		aconnector-&gt;base.polled = DRM_CONNECTOR_POLL_HPD;</div><div class='ctx'> 		break;</div><div class='add'>+	case DRM_MODE_CONNECTOR_DVII:</div><div class='add'>+	case DRM_MODE_CONNECTOR_VGA:</div><div class='add'>+		aconnector-&gt;base.polled =</div><div class='add'>+			DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7658,6 +8968,10 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,</div><div class='ctx'> 				dm-&gt;ddev-&gt;mode_config.scaling_mode_property,</div><div class='ctx'> 				DRM_MODE_SCALE_NONE);</div><div class='ctx'> </div><div class='add'>+	if (connector_type == DRM_MODE_CONNECTOR_HDMIA</div><div class='add'>+		|| (connector_type == DRM_MODE_CONNECTOR_DisplayPort &amp;&amp; !aconnector-&gt;mst_root))</div><div class='add'>+		drm_connector_attach_broadcast_rgb_property(&amp;aconnector-&gt;base);</div><div class='add'>+</div><div class='ctx'> 	drm_object_attach_property(&amp;aconnector-&gt;base.base,</div><div class='ctx'> 				adev-&gt;mode_info.underscan_property,</div><div class='ctx'> 				UNDERSCAN_OFF);</div><div class='hunk'>@@ -7699,6 +9013,18 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		if (adev-&gt;dm.hdcp_workqueue)</div><div class='ctx'> 			drm_connector_attach_content_protection_property(&amp;aconnector-&gt;base, true);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (connector_type == DRM_MODE_CONNECTOR_eDP) {</div><div class='add'>+		struct drm_privacy_screen *privacy_screen;</div><div class='add'>+</div><div class='add'>+		privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)-&gt;dev, NULL);</div><div class='add'>+		if (!IS_ERR(privacy_screen)) {</div><div class='add'>+			drm_connector_attach_privacy_screen_provider(&amp;aconnector-&gt;base,</div><div class='add'>+								     privacy_screen);</div><div class='add'>+		} else if (PTR_ERR(privacy_screen) != -ENODEV) {</div><div class='add'>+			drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,</div><div class='hunk'>@@ -7710,7 +9036,7 @@ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int result = -EIO;</div><div class='ctx'> </div><div class='del'>-	if (!ddc_service-&gt;ddc_pin || !ddc_service-&gt;ddc_pin-&gt;hw_info.hw_supported)</div><div class='add'>+	if (!ddc_service-&gt;ddc_pin)</div><div class='ctx'> 		return result;</div><div class='ctx'> </div><div class='ctx'> 	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);</div><div class='hunk'>@@ -7729,11 +9055,18 @@ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,</div><div class='ctx'> 		cmd.payloads[i].data = msgs[i].buf;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc_submit_i2c(</div><div class='del'>-			ddc_service-&gt;ctx-&gt;dc,</div><div class='del'>-			ddc_service-&gt;link-&gt;link_index,</div><div class='del'>-			&amp;cmd))</div><div class='del'>-		result = num;</div><div class='add'>+	if (i2c-&gt;oem) {</div><div class='add'>+		if (dc_submit_i2c_oem(</div><div class='add'>+			    ddc_service-&gt;ctx-&gt;dc,</div><div class='add'>+			    &amp;cmd))</div><div class='add'>+			result = num;</div><div class='add'>+	} else {</div><div class='add'>+		if (dc_submit_i2c(</div><div class='add'>+			    ddc_service-&gt;ctx-&gt;dc,</div><div class='add'>+			    ddc_service-&gt;link-&gt;link_index,</div><div class='add'>+			    &amp;cmd))</div><div class='add'>+			result = num;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(cmd.payloads);</div><div class='ctx'> 	return result;</div><div class='hunk'>@@ -7750,9 +9083,7 @@ static const struct i2c_algorithm amdgpu_dm_i2c_algo = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct amdgpu_i2c_adapter *</div><div class='del'>-create_i2c(struct ddc_service *ddc_service,</div><div class='del'>-	   int link_index,</div><div class='del'>-	   int *res)</div><div class='add'>+create_i2c(struct ddc_service *ddc_service, bool oem)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ddc_service-&gt;ctx-&gt;driver_context;</div><div class='ctx'> 	struct amdgpu_i2c_adapter *i2c;</div><div class='hunk'>@@ -7763,13 +9094,39 @@ create_i2c(struct ddc_service *ddc_service,</div><div class='ctx'> 	i2c-&gt;base.owner = THIS_MODULE;</div><div class='ctx'> 	i2c-&gt;base.dev.parent = &amp;adev-&gt;pdev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;base.algo = &amp;amdgpu_dm_i2c_algo;</div><div class='del'>-	snprintf(i2c-&gt;base.name, sizeof(i2c-&gt;base.name), "AMDGPU DM i2c hw bus %d", link_index);</div><div class='add'>+	if (oem)</div><div class='add'>+		snprintf(i2c-&gt;base.name, sizeof(i2c-&gt;base.name), "AMDGPU DM i2c OEM bus");</div><div class='add'>+	else</div><div class='add'>+		snprintf(i2c-&gt;base.name, sizeof(i2c-&gt;base.name), "AMDGPU DM i2c hw bus %d",</div><div class='add'>+			 ddc_service-&gt;link-&gt;link_index);</div><div class='ctx'> 	i2c_set_adapdata(&amp;i2c-&gt;base, i2c);</div><div class='ctx'> 	i2c-&gt;ddc_service = ddc_service;</div><div class='add'>+	i2c-&gt;oem = oem;</div><div class='ctx'> </div><div class='ctx'> 	return i2c;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+{</div><div class='add'>+	struct cec_connector_info conn_info;</div><div class='add'>+	struct drm_device *ddev = aconnector-&gt;base.dev;</div><div class='add'>+	struct device *hdmi_dev = ddev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_HDMI_CEC) {</div><div class='add'>+		drm_info(ddev, "HDMI-CEC feature masked\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cec_fill_conn_info_from_drm(&amp;conn_info, &amp;aconnector-&gt;base);</div><div class='add'>+	aconnector-&gt;notifier =</div><div class='add'>+		cec_notifier_conn_register(hdmi_dev, NULL, &amp;conn_info);</div><div class='add'>+	if (!aconnector-&gt;notifier) {</div><div class='add'>+		drm_err(ddev, "Failed to create cec notifier\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Note: this function assumes that dc_link_detect() was called for the</div><div class='hunk'>@@ -7790,21 +9147,21 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	link-&gt;priv = aconnector;</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-	i2c = create_i2c(link-&gt;ddc, link-&gt;link_index, &amp;res);</div><div class='add'>+	i2c = create_i2c(link-&gt;ddc, false);</div><div class='ctx'> 	if (!i2c) {</div><div class='del'>-		DRM_ERROR("Failed to create i2c adapter data\n");</div><div class='add'>+		drm_err(adev_to_drm(dm-&gt;adev), "Failed to create i2c adapter data\n");</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	aconnector-&gt;i2c = i2c;</div><div class='del'>-	res = i2c_add_adapter(&amp;i2c-&gt;base);</div><div class='add'>+	res = devm_i2c_add_adapter(dm-&gt;adev-&gt;dev, &amp;i2c-&gt;base);</div><div class='ctx'> </div><div class='ctx'> 	if (res) {</div><div class='del'>-		DRM_ERROR("Failed to register hw i2c %d\n", link-&gt;link_index);</div><div class='add'>+		drm_err(adev_to_drm(dm-&gt;adev), "Failed to register hw i2c %d\n", link-&gt;link_index);</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	connector_type = to_drm_connector_type(link-&gt;connector_signal);</div><div class='add'>+	connector_type = to_drm_connector_type(link-&gt;connector_signal, link-&gt;link_id.id);</div><div class='ctx'> </div><div class='ctx'> 	res = drm_connector_init_with_ddc(</div><div class='ctx'> 			dm-&gt;ddev,</div><div class='hunk'>@@ -7814,7 +9171,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 			&amp;i2c-&gt;base);</div><div class='ctx'> </div><div class='ctx'> 	if (res) {</div><div class='del'>-		DRM_ERROR("connector_init failed\n");</div><div class='add'>+		drm_err(adev_to_drm(dm-&gt;adev), "connector_init failed\n");</div><div class='ctx'> 		aconnector-&gt;connector_id = -1;</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7833,6 +9190,10 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	drm_connector_attach_encoder(</div><div class='ctx'> 		&amp;aconnector-&gt;base, &amp;aencoder-&gt;base);</div><div class='ctx'> </div><div class='add'>+	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_HDMIB)</div><div class='add'>+		amdgpu_dm_initialize_hdmi_connector(aconnector);</div><div class='add'>+</div><div class='ctx'> 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort</div><div class='ctx'> 		|| connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='ctx'> 		amdgpu_dm_initialize_dp_connector(dm, aconnector, link-&gt;link_index);</div><div class='hunk'>@@ -7890,42 +9251,98 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> static void manage_dm_interrupts(struct amdgpu_device *adev,</div><div class='ctx'> 				 struct amdgpu_crtc *acrtc,</div><div class='del'>-				 bool enable)</div><div class='del'>-{</div><div class='del'>-	/*</div><div class='del'>-	 * We have no guarantee that the frontend index maps to the same</div><div class='add'>+				 struct dm_crtc_state *acrtc_state)</div><div class='add'>+{	/*</div><div class='add'>+	 * We cannot be sure that the frontend index maps to the same</div><div class='ctx'> 	 * backend index - some even map to more than one.</div><div class='del'>-	 *</div><div class='del'>-	 * TODO: Use a different interrupt or check DC itself for the mapping.</div><div class='add'>+	 * So we have to go through the CRTC to find the right IRQ.</div><div class='ctx'> 	 */</div><div class='del'>-	int irq_type =</div><div class='del'>-		amdgpu_display_crtc_idx_to_irq_type(</div><div class='add'>+	int irq_type = amdgpu_display_crtc_idx_to_irq_type(</div><div class='ctx'> 			adev,</div><div class='ctx'> 			acrtc-&gt;crtc_id);</div><div class='add'>+	struct drm_device *dev = adev_to_drm(adev);</div><div class='ctx'> </div><div class='del'>-	if (enable) {</div><div class='del'>-		drm_crtc_vblank_on(&amp;acrtc-&gt;base);</div><div class='del'>-		amdgpu_irq_get(</div><div class='del'>-			adev,</div><div class='del'>-			&amp;adev-&gt;pageflip_irq,</div><div class='del'>-			irq_type);</div><div class='add'>+	struct drm_vblank_crtc_config config = {0};</div><div class='add'>+	struct dc_crtc_timing *timing;</div><div class='add'>+	int offdelay;</div><div class='add'>+</div><div class='add'>+	if (acrtc_state) {</div><div class='add'>+		timing = &amp;acrtc_state-&gt;stream-&gt;timing;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Depending on when the HW latching event of double-buffered</div><div class='add'>+		 * registers happen relative to the PSR SDP deadline, and how</div><div class='add'>+		 * bad the Panel clock has drifted since the last ALPM off</div><div class='add'>+		 * event, there can be up to 3 frames of delay between sending</div><div class='add'>+		 * the PSR exit cmd to DMUB fw, and when the panel starts</div><div class='add'>+		 * displaying live frames.</div><div class='add'>+		 *</div><div class='add'>+		 * We can set:</div><div class='add'>+		 *</div><div class='add'>+		 * 20/100 * offdelay_ms = 3_frames_ms</div><div class='add'>+		 * =&gt; offdelay_ms = 5 * 3_frames_ms</div><div class='add'>+		 *</div><div class='add'>+		 * This ensures that `3_frames_ms` will only be experienced as a</div><div class='add'>+		 * 20% delay on top how long the display has been static, and</div><div class='add'>+		 * thus make the delay less perceivable.</div><div class='add'>+		 */</div><div class='add'>+		if (acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_version &lt;</div><div class='add'>+		    DC_PSR_VERSION_UNSUPPORTED) {</div><div class='add'>+			offdelay = DIV64_U64_ROUND_UP((u64)5 * 3 * 10 *</div><div class='add'>+						      timing-&gt;v_total *</div><div class='add'>+						      timing-&gt;h_total,</div><div class='add'>+						      timing-&gt;pix_clk_100hz);</div><div class='add'>+			config.offdelay_ms = offdelay ?: 30;</div><div class='add'>+		} else if (amdgpu_ip_version(adev, DCE_HWIP, 0) &lt;</div><div class='add'>+			   IP_VERSION(3, 5, 0) ||</div><div class='add'>+			   !(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='add'>+			/*</div><div class='add'>+			 * Older HW and DGPU have issues with instant off;</div><div class='add'>+			 * use a 2 frame offdelay.</div><div class='add'>+			 */</div><div class='add'>+			offdelay = DIV64_U64_ROUND_UP((u64)20 *</div><div class='add'>+						      timing-&gt;v_total *</div><div class='add'>+						      timing-&gt;h_total,</div><div class='add'>+						      timing-&gt;pix_clk_100hz);</div><div class='add'>+</div><div class='add'>+			config.offdelay_ms = offdelay ?: 30;</div><div class='add'>+		} else {</div><div class='add'>+			/* offdelay_ms = 0 will never disable vblank */</div><div class='add'>+			config.offdelay_ms = 1;</div><div class='add'>+			config.disable_immediate = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_crtc_vblank_on_config(&amp;acrtc-&gt;base,</div><div class='add'>+					  &amp;config);</div><div class='add'>+		/* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_get.*/</div><div class='add'>+		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='add'>+		case IP_VERSION(3, 0, 0):</div><div class='add'>+		case IP_VERSION(3, 0, 2):</div><div class='add'>+		case IP_VERSION(3, 0, 3):</div><div class='add'>+		case IP_VERSION(3, 2, 0):</div><div class='add'>+			if (amdgpu_irq_get(adev, &amp;adev-&gt;pageflip_irq, irq_type))</div><div class='add'>+				drm_err(dev, "DM_IRQ: Cannot get pageflip irq!\n");</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='del'>-		amdgpu_irq_get(</div><div class='del'>-			adev,</div><div class='del'>-			&amp;adev-&gt;vline0_irq,</div><div class='del'>-			irq_type);</div><div class='add'>+			if (amdgpu_irq_get(adev, &amp;adev-&gt;vline0_irq, irq_type))</div><div class='add'>+				drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n");</div><div class='ctx'> #endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='add'>+		/* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/</div><div class='add'>+		switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {</div><div class='add'>+		case IP_VERSION(3, 0, 0):</div><div class='add'>+		case IP_VERSION(3, 0, 2):</div><div class='add'>+		case IP_VERSION(3, 0, 3):</div><div class='add'>+		case IP_VERSION(3, 2, 0):</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='del'>-		amdgpu_irq_put(</div><div class='del'>-			adev,</div><div class='del'>-			&amp;adev-&gt;vline0_irq,</div><div class='del'>-			irq_type);</div><div class='add'>+			if (amdgpu_irq_put(adev, &amp;adev-&gt;vline0_irq, irq_type))</div><div class='add'>+				drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n");</div><div class='ctx'> #endif</div><div class='del'>-		amdgpu_irq_put(</div><div class='del'>-			adev,</div><div class='del'>-			&amp;adev-&gt;pageflip_irq,</div><div class='del'>-			irq_type);</div><div class='add'>+			if (amdgpu_irq_put(adev, &amp;adev-&gt;pageflip_irq, irq_type))</div><div class='add'>+				drm_err(dev, "DM_IRQ: Cannot put pageflip irq!\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		drm_crtc_vblank_off(&amp;acrtc-&gt;base);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -8281,7 +9698,7 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,</div><div class='ctx'> 		 */</div><div class='ctx'> 		WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state-&gt;base.crtc, true) != 0);</div><div class='ctx'> 		WARN_ON(drm_crtc_vblank_get(new_state-&gt;base.crtc) != 0);</div><div class='del'>-		DRM_DEBUG_DRIVER("%s: crtc=%u VRR off-&gt;on: Get vblank ref\n",</div><div class='add'>+		drm_dbg_driver(new_state-&gt;base.crtc-&gt;dev, "%s: crtc=%u VRR off-&gt;on: Get vblank ref\n",</div><div class='ctx'> 				 __func__, new_state-&gt;base.crtc-&gt;base.id);</div><div class='ctx'> 	} else if (old_vrr_active &amp;&amp; !new_vrr_active) {</div><div class='ctx'> 		/* Transition VRR active -&gt; inactive:</div><div class='hunk'>@@ -8289,7 +9706,7 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,</div><div class='ctx'> 		 */</div><div class='ctx'> 		WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state-&gt;base.crtc, false) != 0);</div><div class='ctx'> 		drm_crtc_vblank_put(new_state-&gt;base.crtc);</div><div class='del'>-		DRM_DEBUG_DRIVER("%s: crtc=%u VRR on-&gt;off: Drop vblank ref\n",</div><div class='add'>+		drm_dbg_driver(new_state-&gt;base.crtc-&gt;dev, "%s: crtc=%u VRR on-&gt;off: Drop vblank ref\n",</div><div class='ctx'> 				 __func__, new_state-&gt;base.crtc-&gt;base.id);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -8316,6 +9733,130 @@ static inline uint32_t get_mem_type(struct drm_framebuffer *fb)</div><div class='ctx'> 	return abo-&gt;tbo.resource ? abo-&gt;tbo.resource-&gt;mem_type : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_dm_update_cursor(struct drm_plane *plane,</div><div class='add'>+				    struct drm_plane_state *old_plane_state,</div><div class='add'>+				    struct dc_stream_update *update)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(plane-&gt;dev);</div><div class='add'>+	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane-&gt;state-&gt;fb);</div><div class='add'>+	struct drm_crtc *crtc = afb ? plane-&gt;state-&gt;crtc : old_plane_state-&gt;crtc;</div><div class='add'>+	struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc-&gt;state) : NULL;</div><div class='add'>+	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='add'>+	uint64_t address = afb ? afb-&gt;address : 0;</div><div class='add'>+	struct dc_cursor_position position = {0};</div><div class='add'>+	struct dc_cursor_attributes attributes;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!plane-&gt;state-&gt;fb &amp;&amp; !old_plane_state-&gt;fb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_dbg_atomic(plane-&gt;dev, "crtc_id=%d with size %d to %d\n",</div><div class='add'>+		       amdgpu_crtc-&gt;crtc_id, plane-&gt;state-&gt;crtc_w,</div><div class='add'>+		       plane-&gt;state-&gt;crtc_h);</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &amp;position);</div><div class='add'>+	if (ret)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!position.enable) {</div><div class='add'>+		/* turn off cursor */</div><div class='add'>+		if (crtc_state &amp;&amp; crtc_state-&gt;stream) {</div><div class='add'>+			dc_stream_set_cursor_position(crtc_state-&gt;stream,</div><div class='add'>+						      &amp;position);</div><div class='add'>+			update-&gt;cursor_position = &amp;crtc_state-&gt;stream-&gt;cursor_position;</div><div class='add'>+		}</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_crtc-&gt;cursor_width = plane-&gt;state-&gt;crtc_w;</div><div class='add'>+	amdgpu_crtc-&gt;cursor_height = plane-&gt;state-&gt;crtc_h;</div><div class='add'>+</div><div class='add'>+	memset(&amp;attributes, 0, sizeof(attributes));</div><div class='add'>+	attributes.address.high_part = upper_32_bits(address);</div><div class='add'>+	attributes.address.low_part  = lower_32_bits(address);</div><div class='add'>+	attributes.width             = plane-&gt;state-&gt;crtc_w;</div><div class='add'>+	attributes.height            = plane-&gt;state-&gt;crtc_h;</div><div class='add'>+	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;</div><div class='add'>+	attributes.rotation_angle    = 0;</div><div class='add'>+	attributes.attribute_flags.value = 0;</div><div class='add'>+</div><div class='add'>+	/* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM</div><div class='add'>+	 * legacy gamma setup.</div><div class='add'>+	 */</div><div class='add'>+	if (crtc_state-&gt;cm_is_degamma_srgb &amp;&amp;</div><div class='add'>+	    adev-&gt;dm.dc-&gt;caps.color.dpp.gamma_corr)</div><div class='add'>+		attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;</div><div class='add'>+</div><div class='add'>+	if (afb)</div><div class='add'>+		attributes.pitch = afb-&gt;base.pitches[0] / afb-&gt;base.format-&gt;cpp[0];</div><div class='add'>+</div><div class='add'>+	if (crtc_state-&gt;stream) {</div><div class='add'>+		if (!dc_stream_set_cursor_attributes(crtc_state-&gt;stream,</div><div class='add'>+						     &amp;attributes))</div><div class='add'>+			drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n");</div><div class='add'>+</div><div class='add'>+		update-&gt;cursor_attributes = &amp;crtc_state-&gt;stream-&gt;cursor_attributes;</div><div class='add'>+</div><div class='add'>+		if (!dc_stream_set_cursor_position(crtc_state-&gt;stream,</div><div class='add'>+						   &amp;position))</div><div class='add'>+			drm_err(adev_to_drm(adev), "DC failed to set cursor position\n");</div><div class='add'>+</div><div class='add'>+		update-&gt;cursor_position = &amp;crtc_state-&gt;stream-&gt;cursor_position;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,</div><div class='add'>+					  const struct dm_crtc_state *acrtc_state,</div><div class='add'>+					  const u64 current_ts)</div><div class='add'>+{</div><div class='add'>+	struct psr_settings *psr = &amp;acrtc_state-&gt;stream-&gt;link-&gt;psr_settings;</div><div class='add'>+	struct replay_settings *pr = &amp;acrtc_state-&gt;stream-&gt;link-&gt;replay_settings;</div><div class='add'>+	struct amdgpu_dm_connector *aconn =</div><div class='add'>+		(struct amdgpu_dm_connector *)acrtc_state-&gt;stream-&gt;dm_stream_context;</div><div class='add'>+	bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);</div><div class='add'>+</div><div class='add'>+	if (acrtc_state-&gt;update_type &gt; UPDATE_TYPE_FAST) {</div><div class='add'>+		if (pr-&gt;config.replay_supported &amp;&amp; !pr-&gt;replay_feature_enabled)</div><div class='add'>+			amdgpu_dm_link_setup_replay(acrtc_state-&gt;stream-&gt;link, aconn);</div><div class='add'>+		else if (psr-&gt;psr_version != DC_PSR_VERSION_UNSUPPORTED &amp;&amp;</div><div class='add'>+			     !psr-&gt;psr_feature_enabled)</div><div class='add'>+			if (!aconn-&gt;disallow_edp_enter_psr)</div><div class='add'>+				amdgpu_dm_link_setup_psr(acrtc_state-&gt;stream);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Decrement skip count when SR is enabled and we're doing fast updates. */</div><div class='add'>+	if (acrtc_state-&gt;update_type == UPDATE_TYPE_FAST &amp;&amp;</div><div class='add'>+	    (psr-&gt;psr_feature_enabled || pr-&gt;config.replay_supported)) {</div><div class='add'>+		if (aconn-&gt;sr_skip_count &gt; 0)</div><div class='add'>+			aconn-&gt;sr_skip_count--;</div><div class='add'>+</div><div class='add'>+		/* Allow SR when skip count is 0. */</div><div class='add'>+		acrtc_attach-&gt;dm_irq_params.allow_sr_entry = !aconn-&gt;sr_skip_count;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * If sink supports PSR SU/Panel Replay, there is no need to rely on</div><div class='add'>+		 * a vblank event disable request to enable PSR/RP. PSR SU/RP</div><div class='add'>+		 * can be enabled immediately once OS demonstrates an</div><div class='add'>+		 * adequate number of fast atomic commits to notify KMD</div><div class='add'>+		 * of update events. See `vblank_control_worker()`.</div><div class='add'>+		 */</div><div class='add'>+		if (!vrr_active &amp;&amp;</div><div class='add'>+		    acrtc_attach-&gt;dm_irq_params.allow_sr_entry &amp;&amp;</div><div class='add'>+#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='add'>+		    !amdgpu_dm_crc_window_is_activated(acrtc_state-&gt;base.crtc) &amp;&amp;</div><div class='add'>+#endif</div><div class='add'>+		    (current_ts - psr-&gt;psr_dirty_rects_change_timestamp_ns) &gt; 500000000) {</div><div class='add'>+			if (pr-&gt;replay_feature_enabled &amp;&amp; !pr-&gt;replay_allow_active)</div><div class='add'>+				amdgpu_dm_replay_enable(acrtc_state-&gt;stream, true);</div><div class='add'>+			if (psr-&gt;psr_version == DC_PSR_VERSION_SU_1 &amp;&amp;</div><div class='add'>+			    !psr-&gt;psr_allow_active &amp;&amp; !aconn-&gt;disallow_edp_enter_psr)</div><div class='add'>+				amdgpu_dm_psr_enable(acrtc_state-&gt;stream);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		acrtc_attach-&gt;dm_irq_params.allow_sr_entry = false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 				    struct drm_device *dev,</div><div class='ctx'> 				    struct amdgpu_display_manager *dm,</div><div class='hunk'>@@ -8339,6 +9880,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 	bool cursor_update = false;</div><div class='ctx'> 	bool pflip_present = false;</div><div class='ctx'> 	bool dirty_rects_changed = false;</div><div class='add'>+	bool updated_planes_and_streams = false;</div><div class='ctx'> 	struct {</div><div class='ctx'> 		struct dc_surface_update surface_updates[MAX_SURFACES];</div><div class='ctx'> 		struct dc_plane_info plane_infos[MAX_SURFACES];</div><div class='hunk'>@@ -8358,8 +9900,24 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 	 * Disable the cursor first if we're disabling all the planes.</div><div class='ctx'> 	 * It'll remain on the screen after the planes are re-enabled</div><div class='ctx'> 	 * if we don't.</div><div class='add'>+	 *</div><div class='add'>+	 * If the cursor is transitioning from native to overlay mode, the</div><div class='add'>+	 * native cursor needs to be disabled first.</div><div class='ctx'> 	 */</div><div class='del'>-	if (acrtc_state-&gt;active_planes == 0)</div><div class='add'>+	if (acrtc_state-&gt;cursor_mode == DM_CURSOR_OVERLAY_MODE &amp;&amp;</div><div class='add'>+	    dm_old_crtc_state-&gt;cursor_mode == DM_CURSOR_NATIVE_MODE) {</div><div class='add'>+		struct dc_cursor_position cursor_position = {0};</div><div class='add'>+</div><div class='add'>+		if (!dc_stream_set_cursor_position(acrtc_state-&gt;stream,</div><div class='add'>+						   &amp;cursor_position))</div><div class='add'>+			drm_err(dev, "DC failed to disable native cursor\n");</div><div class='add'>+</div><div class='add'>+		bundle-&gt;stream_update.cursor_position =</div><div class='add'>+				&amp;acrtc_state-&gt;stream-&gt;cursor_position;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (acrtc_state-&gt;active_planes == 0 &amp;&amp;</div><div class='add'>+	    dm_old_crtc_state-&gt;cursor_mode == DM_CURSOR_NATIVE_MODE)</div><div class='ctx'> 		amdgpu_dm_commit_cursors(state);</div><div class='ctx'> </div><div class='ctx'> 	/* update planes when needed */</div><div class='hunk'>@@ -8373,10 +9931,14 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);</div><div class='ctx'> </div><div class='ctx'> 		/* Cursor plane is handled after stream updates */</div><div class='del'>-		if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR) {</div><div class='add'>+		if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR &amp;&amp;</div><div class='add'>+		    acrtc_state-&gt;cursor_mode == DM_CURSOR_NATIVE_MODE) {</div><div class='ctx'> 			if ((fb &amp;&amp; crtc == pcrtc) ||</div><div class='del'>-			    (old_plane_state-&gt;fb &amp;&amp; old_plane_state-&gt;crtc == pcrtc))</div><div class='add'>+			    (old_plane_state-&gt;fb &amp;&amp; old_plane_state-&gt;crtc == pcrtc)) {</div><div class='ctx'> 				cursor_update = true;</div><div class='add'>+				if (amdgpu_ip_version(dm-&gt;adev, DCE_HWIP, 0) != 0)</div><div class='add'>+					amdgpu_dm_update_cursor(plane, old_plane_state, &amp;bundle-&gt;stream_update);</div><div class='add'>+			}</div><div class='ctx'> </div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -8394,13 +9956,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 		bundle-&gt;surface_updates[planes_count].surface = dc_plane;</div><div class='ctx'> 		if (new_pcrtc_state-&gt;color_mgmt_changed) {</div><div class='del'>-			bundle-&gt;surface_updates[planes_count].gamma = dc_plane-&gt;gamma_correction;</div><div class='del'>-			bundle-&gt;surface_updates[planes_count].in_transfer_func = dc_plane-&gt;in_transfer_func;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].gamma = &amp;dc_plane-&gt;gamma_correction;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].in_transfer_func = &amp;dc_plane-&gt;in_transfer_func;</div><div class='ctx'> 			bundle-&gt;surface_updates[planes_count].gamut_remap_matrix = &amp;dc_plane-&gt;gamut_remap_matrix;</div><div class='ctx'> 			bundle-&gt;surface_updates[planes_count].hdr_mult = dc_plane-&gt;hdr_mult;</div><div class='del'>-			bundle-&gt;surface_updates[planes_count].func_shaper = dc_plane-&gt;in_shaper_func;</div><div class='del'>-			bundle-&gt;surface_updates[planes_count].lut3d_func = dc_plane-&gt;lut3d_func;</div><div class='del'>-			bundle-&gt;surface_updates[planes_count].blend_tf = dc_plane-&gt;blend_tf;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].func_shaper = &amp;dc_plane-&gt;in_shaper_func;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].lut3d_func = &amp;dc_plane-&gt;lut3d_func;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].blend_tf = &amp;dc_plane-&gt;blend_tf;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_plane_fill_dc_scaling_info(dm-&gt;adev, new_plane_state,</div><div class='hunk'>@@ -8423,7 +9985,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 			afb-&gt;tiling_flags,</div><div class='ctx'> 			&amp;bundle-&gt;plane_infos[planes_count],</div><div class='ctx'> 			&amp;bundle-&gt;flip_addrs[planes_count].address,</div><div class='del'>-			afb-&gt;tmz_surface, false);</div><div class='add'>+			afb-&gt;tmz_surface);</div><div class='ctx'> </div><div class='ctx'> 		drm_dbg_state(state-&gt;dev, "plane: id=%d dcc_en=%d\n",</div><div class='ctx'> 				 new_plane_state-&gt;plane-&gt;index,</div><div class='hunk'>@@ -8448,7 +10010,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 			 * during the PSR-SU was disabled.</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_version &gt;= DC_PSR_VERSION_SU_1 &amp;&amp;</div><div class='del'>-			    acrtc_attach-&gt;dm_irq_params.allow_psr_entry &amp;&amp;</div><div class='add'>+			    acrtc_attach-&gt;dm_irq_params.allow_sr_entry &amp;&amp;</div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='ctx'> 			    !amdgpu_dm_crc_window_is_activated(acrtc_state-&gt;base.crtc) &amp;&amp;</div><div class='ctx'> #endif</div><div class='hunk'>@@ -8457,7 +10019,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 				acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_dirty_rects_change_timestamp_ns =</div><div class='ctx'> 				timestamp_ns;</div><div class='ctx'> 				if (acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_allow_active)</div><div class='del'>-					amdgpu_dm_psr_disable(acrtc_state-&gt;stream);</div><div class='add'>+					amdgpu_dm_psr_disable(acrtc_state-&gt;stream, true);</div><div class='ctx'> 				mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -8488,7 +10050,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 		bundle-&gt;surface_updates[planes_count].surface = dc_plane;</div><div class='ctx'> </div><div class='ctx'> 		if (!bundle-&gt;surface_updates[planes_count].surface) {</div><div class='del'>-			DRM_ERROR("No surface for CRTC: id=%d\n",</div><div class='add'>+			drm_err(dev, "No surface for CRTC: id=%d\n",</div><div class='ctx'> 					acrtc_attach-&gt;crtc_id);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -8575,15 +10137,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 				bundle-&gt;stream_update.vrr_infopacket =</div><div class='ctx'> 					&amp;acrtc_state-&gt;stream-&gt;vrr_infopacket;</div><div class='ctx'> 		}</div><div class='del'>-	} else if (cursor_update &amp;&amp; acrtc_state-&gt;active_planes &gt; 0 &amp;&amp;</div><div class='del'>-		   acrtc_attach-&gt;base.state-&gt;event) {</div><div class='del'>-		drm_crtc_vblank_get(pcrtc);</div><div class='del'>-</div><div class='add'>+	} else if (cursor_update &amp;&amp; acrtc_state-&gt;active_planes &gt; 0) {</div><div class='ctx'> 		spin_lock_irqsave(&amp;pcrtc-&gt;dev-&gt;event_lock, flags);</div><div class='del'>-</div><div class='del'>-		acrtc_attach-&gt;event = acrtc_attach-&gt;base.state-&gt;event;</div><div class='del'>-		acrtc_attach-&gt;base.state-&gt;event = NULL;</div><div class='del'>-</div><div class='add'>+		if (acrtc_attach-&gt;base.state-&gt;event) {</div><div class='add'>+			drm_crtc_vblank_get(pcrtc);</div><div class='add'>+			acrtc_attach-&gt;event = acrtc_attach-&gt;base.state-&gt;event;</div><div class='add'>+			acrtc_attach-&gt;base.state-&gt;event = NULL;</div><div class='add'>+		}</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;pcrtc-&gt;dev-&gt;event_lock, flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -8613,7 +10173,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 			bundle-&gt;stream_update.output_csc_transform =</div><div class='ctx'> 				&amp;acrtc_state-&gt;stream-&gt;csc_color_matrix;</div><div class='ctx'> 			bundle-&gt;stream_update.out_transfer_func =</div><div class='del'>-				acrtc_state-&gt;stream-&gt;out_transfer_func;</div><div class='add'>+				&amp;acrtc_state-&gt;stream-&gt;out_transfer_func;</div><div class='ctx'> 			bundle-&gt;stream_update.lut3d_func =</div><div class='ctx'> 				(struct dc_3dlut *) acrtc_state-&gt;stream-&gt;lut3d_func;</div><div class='ctx'> 			bundle-&gt;stream_update.func_shaper =</div><div class='hunk'>@@ -8625,9 +10185,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 			bundle-&gt;stream_update.abm_level = &amp;acrtc_state-&gt;abm_level;</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='del'>-		if ((acrtc_state-&gt;update_type &gt; UPDATE_TYPE_FAST) &amp;&amp;</div><div class='del'>-				acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_allow_active)</div><div class='del'>-			amdgpu_dm_psr_disable(acrtc_state-&gt;stream);</div><div class='add'>+		if ((acrtc_state-&gt;update_type &gt; UPDATE_TYPE_FAST) || vrr_active) {</div><div class='add'>+			if (acrtc_state-&gt;stream-&gt;link-&gt;replay_settings.replay_allow_active)</div><div class='add'>+				amdgpu_dm_replay_disable(acrtc_state-&gt;stream);</div><div class='add'>+			if (acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_allow_active)</div><div class='add'>+				amdgpu_dm_psr_disable(acrtc_state-&gt;stream, true);</div><div class='add'>+		}</div><div class='ctx'> 		mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -8649,6 +10212,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 					 acrtc_state-&gt;stream,</div><div class='ctx'> 					 &amp;bundle-&gt;stream_update,</div><div class='ctx'> 					 bundle-&gt;surface_updates);</div><div class='add'>+		updated_planes_and_streams = true;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='ctx'> 		 * Enable or disable the interrupts on the backend.</div><div class='hunk'>@@ -8667,57 +10231,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 			dm_update_pflip_irq_state(drm_to_adev(dev),</div><div class='ctx'> 						  acrtc_attach);</div><div class='ctx'> </div><div class='del'>-		if (acrtc_state-&gt;update_type &gt; UPDATE_TYPE_FAST) {</div><div class='del'>-			if (acrtc_state-&gt;stream-&gt;link-&gt;replay_settings.config.replay_supported &amp;&amp;</div><div class='del'>-					!acrtc_state-&gt;stream-&gt;link-&gt;replay_settings.replay_feature_enabled) {</div><div class='del'>-				struct amdgpu_dm_connector *aconn =</div><div class='del'>-					(struct amdgpu_dm_connector *)acrtc_state-&gt;stream-&gt;dm_stream_context;</div><div class='del'>-				amdgpu_dm_link_setup_replay(acrtc_state-&gt;stream-&gt;link, aconn);</div><div class='del'>-			} else if (acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &amp;&amp;</div><div class='del'>-					!acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_feature_enabled) {</div><div class='del'>-</div><div class='del'>-				struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)</div><div class='del'>-					acrtc_state-&gt;stream-&gt;dm_stream_context;</div><div class='del'>-</div><div class='del'>-				if (!aconn-&gt;disallow_edp_enter_psr)</div><div class='del'>-					amdgpu_dm_link_setup_psr(acrtc_state-&gt;stream);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Decrement skip count when PSR is enabled and we're doing fast updates. */</div><div class='del'>-		if (acrtc_state-&gt;update_type == UPDATE_TYPE_FAST &amp;&amp;</div><div class='del'>-		    acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_feature_enabled) {</div><div class='del'>-			struct amdgpu_dm_connector *aconn =</div><div class='del'>-				(struct amdgpu_dm_connector *)acrtc_state-&gt;stream-&gt;dm_stream_context;</div><div class='del'>-</div><div class='del'>-			if (aconn-&gt;psr_skip_count &gt; 0)</div><div class='del'>-				aconn-&gt;psr_skip_count--;</div><div class='del'>-</div><div class='del'>-			/* Allow PSR when skip count is 0. */</div><div class='del'>-			acrtc_attach-&gt;dm_irq_params.allow_psr_entry = !aconn-&gt;psr_skip_count;</div><div class='del'>-</div><div class='del'>-			/*</div><div class='del'>-			 * If sink supports PSR SU, there is no need to rely on</div><div class='del'>-			 * a vblank event disable request to enable PSR. PSR SU</div><div class='del'>-			 * can be enabled immediately once OS demonstrates an</div><div class='del'>-			 * adequate number of fast atomic commits to notify KMD</div><div class='del'>-			 * of update events. See `vblank_control_worker()`.</div><div class='del'>-			 */</div><div class='del'>-			if (acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_version &gt;= DC_PSR_VERSION_SU_1 &amp;&amp;</div><div class='del'>-			    acrtc_attach-&gt;dm_irq_params.allow_psr_entry &amp;&amp;</div><div class='del'>-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='del'>-			    !amdgpu_dm_crc_window_is_activated(acrtc_state-&gt;base.crtc) &amp;&amp;</div><div class='del'>-#endif</div><div class='del'>-			    !acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_allow_active &amp;&amp;</div><div class='del'>-			    !aconn-&gt;disallow_edp_enter_psr &amp;&amp;</div><div class='del'>-			    (timestamp_ns -</div><div class='del'>-			    acrtc_state-&gt;stream-&gt;link-&gt;psr_settings.psr_dirty_rects_change_timestamp_ns) &gt;</div><div class='del'>-			    500000000)</div><div class='del'>-				amdgpu_dm_psr_enable(acrtc_state-&gt;stream);</div><div class='del'>-		} else {</div><div class='del'>-			acrtc_attach-&gt;dm_irq_params.allow_psr_entry = false;</div><div class='del'>-		}</div><div class='del'>-</div><div class='add'>+		amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);</div><div class='ctx'> 		mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -8726,7 +10240,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 	 * This avoids redundant programming in the case where we're going</div><div class='ctx'> 	 * to be disabling a single plane - those pipes are being disabled.</div><div class='ctx'> 	 */</div><div class='del'>-	if (acrtc_state-&gt;active_planes)</div><div class='add'>+	if (acrtc_state-&gt;active_planes &amp;&amp;</div><div class='add'>+	    (!updated_planes_and_streams || amdgpu_ip_version(dm-&gt;adev, DCE_HWIP, 0) == 0) &amp;&amp;</div><div class='add'>+	    acrtc_state-&gt;cursor_mode == DM_CURSOR_NATIVE_MODE)</div><div class='ctx'> 		amdgpu_dm_commit_cursors(state);</div><div class='ctx'> </div><div class='ctx'> cleanup:</div><div class='hunk'>@@ -8764,10 +10280,10 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev,</div><div class='ctx'> 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+notify:</div><div class='ctx'> 		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-notify:</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;dm.audio_lock);</div><div class='hunk'>@@ -8847,6 +10363,8 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	bool mode_set_reset_required = false;</div><div class='ctx'> 	u32 i;</div><div class='add'>+	struct dc_commit_streams_params params = {dc_state-&gt;streams, dc_state-&gt;stream_count};</div><div class='add'>+	bool set_backlight_level = false;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable writeback */</div><div class='ctx'> 	for_each_old_connector_in_state(state, connector, old_con_state, i) {</div><div class='hunk'>@@ -8866,7 +10384,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 		if (acrtc)</div><div class='ctx'> 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &amp;acrtc-&gt;base);</div><div class='ctx'> </div><div class='del'>-		if (!acrtc-&gt;wb_enabled)</div><div class='add'>+		if (!acrtc || !acrtc-&gt;wb_enabled)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);</div><div class='hunk'>@@ -8884,7 +10402,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 		if (old_crtc_state-&gt;active &amp;&amp;</div><div class='ctx'> 		    (!new_crtc_state-&gt;active ||</div><div class='ctx'> 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {</div><div class='del'>-			manage_dm_interrupts(adev, acrtc, false);</div><div class='add'>+			manage_dm_interrupts(adev, acrtc, NULL);</div><div class='ctx'> 			dc_stream_release(dm_old_crtc_state-&gt;stream);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -8914,7 +10432,8 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 			memset(&amp;position, 0, sizeof(position));</div><div class='ctx'> 			mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='del'>-			dc_stream_set_cursor_position(dm_old_crtc_state-&gt;stream, &amp;position);</div><div class='add'>+			dc_exit_ips_for_hw_access(dm-&gt;dc);</div><div class='add'>+			dc_stream_program_cursor_position(dm_old_crtc_state-&gt;stream, &amp;position);</div><div class='ctx'> 			mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -8930,7 +10449,9 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 		if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state-&gt;stream, dm_old_crtc_state-&gt;stream)) {</div><div class='ctx'> </div><div class='del'>-			DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc-&gt;crtc_id, acrtc);</div><div class='add'>+			drm_dbg_atomic(dev,</div><div class='add'>+				       "Atomic commit: SET crtc id %d: [%p]\n",</div><div class='add'>+				       acrtc-&gt;crtc_id, acrtc);</div><div class='ctx'> </div><div class='ctx'> 			if (!dm_new_crtc_state-&gt;stream) {</div><div class='ctx'> 				/*</div><div class='hunk'>@@ -8948,8 +10469,9 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 				 * have a sink to keep the pipe running so that</div><div class='ctx'> 				 * hw state is consistent with the sw state</div><div class='ctx'> 				 */</div><div class='del'>-				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",</div><div class='del'>-						__func__, acrtc-&gt;base.base.id);</div><div class='add'>+				drm_dbg_atomic(dev,</div><div class='add'>+					       "Failed to create new stream for crtc %d\n",</div><div class='add'>+						acrtc-&gt;base.base.id);</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -8962,8 +10484,11 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 			acrtc-&gt;hw_mode = new_crtc_state-&gt;mode;</div><div class='ctx'> 			crtc-&gt;hwmode = new_crtc_state-&gt;mode;</div><div class='ctx'> 			mode_set_reset_required = true;</div><div class='add'>+			set_backlight_level = true;</div><div class='ctx'> 		} else if (modereset_required(new_crtc_state)) {</div><div class='del'>-			DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc-&gt;crtc_id, acrtc);</div><div class='add'>+			drm_dbg_atomic(dev,</div><div class='add'>+				       "Atomic commit: RESET. crtc id %d:[%p]\n",</div><div class='add'>+				       acrtc-&gt;crtc_id, acrtc);</div><div class='ctx'> 			/* i.e. reset mode */</div><div class='ctx'> 			if (dm_old_crtc_state-&gt;stream)</div><div class='ctx'> 				remove_stream(adev, acrtc, dm_old_crtc_state-&gt;stream);</div><div class='hunk'>@@ -8983,10 +10508,11 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 	dm_enable_per_frame_crtc_master_sync(dc_state);</div><div class='ctx'> 	mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='del'>-	WARN_ON(!dc_commit_streams(dm-&gt;dc, dc_state-&gt;streams, dc_state-&gt;stream_count));</div><div class='add'>+	dc_exit_ips_for_hw_access(dm-&gt;dc);</div><div class='add'>+	WARN_ON(!dc_commit_streams(dm-&gt;dc, &amp;params));</div><div class='ctx'> </div><div class='ctx'> 	/* Allow idle optimization when vblank count is 0 for display off */</div><div class='del'>-	if (dm-&gt;active_vblank_irq_count == 0)</div><div class='add'>+	if ((dm-&gt;active_vblank_irq_count == 0) &amp;&amp; amdgpu_dm_is_headless(dm-&gt;adev))</div><div class='ctx'> 		dc_allow_idle_optimizations(dm-&gt;dc, true);</div><div class='ctx'> 	mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -9010,6 +10536,19 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 				acrtc-&gt;otg_inst = status-&gt;primary_otg_inst;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/* During boot up and resume the DC layer will reset the panel brightness</div><div class='add'>+	 * to fix a flicker issue.</div><div class='add'>+	 * It will cause the dm-&gt;actual_brightness is not the current panel brightness</div><div class='add'>+	 * level. (the dm-&gt;brightness is the correct panel level)</div><div class='add'>+	 * So we set the backlight level with dm-&gt;brightness value after set mode</div><div class='add'>+	 */</div><div class='add'>+	if (set_backlight_level) {</div><div class='add'>+		for (i = 0; i &lt; dm-&gt;num_of_edps; i++) {</div><div class='add'>+			if (dm-&gt;backlight_dev[i])</div><div class='add'>+				amdgpu_dm_backlight_set_level(dm, i, dm-&gt;brightness[i]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dm_set_writeback(struct amdgpu_display_manager *dm,</div><div class='hunk'>@@ -9027,20 +10566,20 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);</div><div class='ctx'> 	if (!wb_info) {</div><div class='del'>-		DRM_ERROR("Failed to allocate wb_info\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	acrtc = to_amdgpu_crtc(wb_conn-&gt;encoder.crtc);</div><div class='ctx'> 	if (!acrtc) {</div><div class='del'>-		DRM_ERROR("no amdgpu_crtc found\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n");</div><div class='ctx'> 		kfree(wb_info);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	afb = to_amdgpu_framebuffer(new_con_state-&gt;writeback_job-&gt;fb);</div><div class='ctx'> 	if (!afb) {</div><div class='del'>-		DRM_ERROR("No amdgpu_framebuffer found\n");</div><div class='add'>+		drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n");</div><div class='ctx'> 		kfree(wb_info);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -9111,72 +10650,40 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	drm_writeback_queue_job(wb_conn, new_con_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.</div><div class='del'>- * @state: The atomic state to commit</div><div class='del'>- *</div><div class='del'>- * This will tell DC to commit the constructed DC state from atomic_check,</div><div class='del'>- * programming the hardware. Any failures here implies a hardware failure, since</div><div class='del'>- * atomic check should have filtered anything non-kosher.</div><div class='del'>- */</div><div class='del'>-static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='add'>+static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state)</div><div class='ctx'> {</div><div class='add'>+	struct drm_connector_state *old_con_state, *new_con_state;</div><div class='ctx'> 	struct drm_device *dev = state-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='del'>-	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='del'>-	struct dm_atomic_state *dm_state;</div><div class='del'>-	struct dc_state *dc_state = NULL;</div><div class='del'>-	u32 i, j;</div><div class='del'>-	struct drm_crtc *crtc;</div><div class='del'>-	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	bool wait_for_vblank = true;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_state *old_con_state, *new_con_state;</div><div class='del'>-	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='del'>-	int crtc_disable_count = 0;</div><div class='del'>-</div><div class='del'>-	trace_amdgpu_dm_atomic_commit_tail_begin(state);</div><div class='del'>-</div><div class='del'>-	if (dm-&gt;dc-&gt;caps.ips_support &amp;&amp; dm-&gt;dc-&gt;idle_optimizations_allowed)</div><div class='del'>-		dc_allow_idle_optimizations(dm-&gt;dc, false);</div><div class='del'>-</div><div class='del'>-	drm_atomic_helper_update_legacy_modeset_state(dev, state);</div><div class='del'>-	drm_dp_mst_atomic_wait_for_dependencies(state);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	dm_state = dm_atomic_get_new_state(state);</div><div class='del'>-	if (dm_state &amp;&amp; dm_state-&gt;context) {</div><div class='del'>-		dc_state = dm_state-&gt;context;</div><div class='del'>-		amdgpu_dm_commit_streams(state, dc_state);</div><div class='del'>-	}</div><div class='add'>+	if (!adev-&gt;dm.hdcp_workqueue)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {</div><div class='ctx'> 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);</div><div class='ctx'> 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state-&gt;base.crtc);</div><div class='add'>+		struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='add'>+		struct dm_crtc_state *dm_new_crtc_state;</div><div class='ctx'> 		struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> </div><div class='del'>-		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		if (!connector || connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='del'>-		if (!adev-&gt;dm.hdcp_workqueue)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);</div><div class='del'>-</div><div class='del'>-		if (!connector)</div><div class='del'>-			continue;</div><div class='add'>+		drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i);</div><div class='ctx'> </div><div class='del'>-		pr_debug("[HDCP_DM] connector-&gt;index: %x connect_status: %x dpms: %x\n",</div><div class='add'>+		drm_dbg(dev, "[HDCP_DM] connector-&gt;index: %x connect_status: %x dpms: %x\n",</div><div class='ctx'> 			connector-&gt;index, connector-&gt;status, connector-&gt;dpms);</div><div class='del'>-		pr_debug("[HDCP_DM] state protection old: %x new: %x\n",</div><div class='add'>+		drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n",</div><div class='ctx'> 			old_con_state-&gt;content_protection, new_con_state-&gt;content_protection);</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;dc_sink) {</div><div class='ctx'> 			if (aconnector-&gt;dc_sink-&gt;sink_signal != SIGNAL_TYPE_VIRTUAL &amp;&amp;</div><div class='ctx'> 				aconnector-&gt;dc_sink-&gt;sink_signal != SIGNAL_TYPE_NONE) {</div><div class='del'>-				pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",</div><div class='add'>+				drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n",</div><div class='ctx'> 				aconnector-&gt;dc_sink-&gt;edid_caps.display_name);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -9190,7 +10697,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (old_crtc_state)</div><div class='del'>-			pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",</div><div class='add'>+			drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",</div><div class='ctx'> 			old_crtc_state-&gt;enable,</div><div class='ctx'> 			old_crtc_state-&gt;active,</div><div class='ctx'> 			old_crtc_state-&gt;mode_changed,</div><div class='hunk'>@@ -9198,29 +10705,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 			old_crtc_state-&gt;connectors_changed);</div><div class='ctx'> </div><div class='ctx'> 		if (new_crtc_state)</div><div class='del'>-			pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",</div><div class='add'>+			drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",</div><div class='ctx'> 			new_crtc_state-&gt;enable,</div><div class='ctx'> 			new_crtc_state-&gt;active,</div><div class='ctx'> 			new_crtc_state-&gt;mode_changed,</div><div class='ctx'> 			new_crtc_state-&gt;active_changed,</div><div class='ctx'> 			new_crtc_state-&gt;connectors_changed);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {</div><div class='del'>-		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);</div><div class='del'>-		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state-&gt;base.crtc);</div><div class='del'>-		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='del'>-		if (!adev-&gt;dm.hdcp_workqueue)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		new_crtc_state = NULL;</div><div class='del'>-		old_crtc_state = NULL;</div><div class='del'>-</div><div class='del'>-		if (acrtc) {</div><div class='del'>-			new_crtc_state = drm_atomic_get_new_crtc_state(state, &amp;acrtc-&gt;base);</div><div class='del'>-			old_crtc_state = drm_atomic_get_old_crtc_state(state, &amp;acrtc-&gt;base);</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='ctx'> </div><div class='hunk'>@@ -9264,13 +10755,86 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 				new_con_state-&gt;content_protection &gt;= DRM_MODE_CONTENT_PROTECTION_DESIRED)</div><div class='ctx'> 				enable_encryption = true;</div><div class='ctx'> </div><div class='del'>-			DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);</div><div class='add'>+			drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);</div><div class='ctx'> </div><div class='del'>-			hdcp_update_display(</div><div class='del'>-				adev-&gt;dm.hdcp_workqueue, aconnector-&gt;dc_link-&gt;link_index, aconnector,</div><div class='del'>-				new_con_state-&gt;hdcp_content_type, enable_encryption);</div><div class='add'>+			if (aconnector-&gt;dc_link)</div><div class='add'>+				hdcp_update_display(</div><div class='add'>+					adev-&gt;dm.hdcp_workqueue, aconnector-&gt;dc_link-&gt;link_index, aconnector,</div><div class='add'>+					new_con_state-&gt;hdcp_content_type, enable_encryption);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state)</div><div class='add'>+{</div><div class='add'>+	struct drm_crtc *crtc;</div><div class='add'>+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='add'>+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	ret = drm_dp_mst_atomic_setup_commit(state);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {</div><div class='add'>+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+		/*</div><div class='add'>+		 * Color management settings. We also update color properties</div><div class='add'>+		 * when a modeset is needed, to ensure it gets reprogrammed.</div><div class='add'>+		 */</div><div class='add'>+		if (dm_new_crtc_state-&gt;base.active &amp;&amp; dm_new_crtc_state-&gt;stream &amp;&amp;</div><div class='add'>+		    (dm_new_crtc_state-&gt;base.color_mgmt_changed ||</div><div class='add'>+		     dm_old_crtc_state-&gt;regamma_tf != dm_new_crtc_state-&gt;regamma_tf ||</div><div class='add'>+		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {</div><div class='add'>+			ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);</div><div class='add'>+			if (ret) {</div><div class='add'>+				drm_dbg_atomic(state-&gt;dev, "Failed to update color state\n");</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.</div><div class='add'>+ * @state: The atomic state to commit</div><div class='add'>+ *</div><div class='add'>+ * This will tell DC to commit the constructed DC state from atomic_check,</div><div class='add'>+ * programming the hardware. Any failures here implies a hardware failure, since</div><div class='add'>+ * atomic check should have filtered anything non-kosher.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = state-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='add'>+	struct dm_atomic_state *dm_state;</div><div class='add'>+	struct dc_state *dc_state = NULL;</div><div class='add'>+	u32 i, j;</div><div class='add'>+	struct drm_crtc *crtc;</div><div class='add'>+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	bool wait_for_vblank = true;</div><div class='add'>+	struct drm_connector *connector;</div><div class='add'>+	struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL;</div><div class='add'>+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='add'>+	int crtc_disable_count = 0;</div><div class='add'>+</div><div class='add'>+	trace_amdgpu_dm_atomic_commit_tail_begin(state);</div><div class='add'>+</div><div class='add'>+	drm_atomic_helper_update_legacy_modeset_state(dev, state);</div><div class='add'>+	drm_dp_mst_atomic_wait_for_dependencies(state);</div><div class='add'>+</div><div class='add'>+	dm_state = dm_atomic_get_new_state(state);</div><div class='add'>+	if (dm_state &amp;&amp; dm_state-&gt;context) {</div><div class='add'>+		dc_state = dm_state-&gt;context;</div><div class='add'>+		amdgpu_dm_commit_streams(state, dc_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_dm_update_hdcp(state);</div><div class='ctx'> </div><div class='ctx'> 	/* Handle connector state changes */</div><div class='ctx'> 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {</div><div class='hunk'>@@ -9281,7 +10845,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 		struct dc_stream_update stream_update;</div><div class='ctx'> 		struct dc_info_packet hdr_packet;</div><div class='ctx'> 		struct dc_stream_status *status = NULL;</div><div class='del'>-		bool abm_changed, hdr_changed, scaling_changed;</div><div class='add'>+		bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false;</div><div class='ctx'> </div><div class='ctx'> 		memset(&amp;stream_update, 0, sizeof(stream_update));</div><div class='ctx'> </div><div class='hunk'>@@ -9300,13 +10864,18 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 		scaling_changed = is_scaling_state_different(dm_new_con_state,</div><div class='ctx'> 							     dm_old_con_state);</div><div class='ctx'> </div><div class='add'>+		if ((new_con_state-&gt;hdmi.broadcast_rgb != old_con_state-&gt;hdmi.broadcast_rgb) &amp;&amp;</div><div class='add'>+			(dm_old_crtc_state-&gt;stream-&gt;output_color_space !=</div><div class='add'>+				get_output_color_space(&amp;dm_new_crtc_state-&gt;stream-&gt;timing, new_con_state)))</div><div class='add'>+			output_color_space_changed = true;</div><div class='add'>+</div><div class='ctx'> 		abm_changed = dm_new_crtc_state-&gt;abm_level !=</div><div class='ctx'> 			      dm_old_crtc_state-&gt;abm_level;</div><div class='ctx'> </div><div class='ctx'> 		hdr_changed =</div><div class='ctx'> 			!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);</div><div class='ctx'> </div><div class='del'>-		if (!scaling_changed &amp;&amp; !abm_changed &amp;&amp; !hdr_changed)</div><div class='add'>+		if (!scaling_changed &amp;&amp; !abm_changed &amp;&amp; !hdr_changed &amp;&amp; !output_color_space_changed)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		stream_update.stream = dm_new_crtc_state-&gt;stream;</div><div class='hunk'>@@ -9318,6 +10887,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 			stream_update.dst = dm_new_crtc_state-&gt;stream-&gt;dst;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (output_color_space_changed) {</div><div class='add'>+			dm_new_crtc_state-&gt;stream-&gt;output_color_space</div><div class='add'>+				= get_output_color_space(&amp;dm_new_crtc_state-&gt;stream-&gt;timing, new_con_state);</div><div class='add'>+</div><div class='add'>+			stream_update.output_color_space = &amp;dm_new_crtc_state-&gt;stream-&gt;output_color_space;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (abm_changed) {</div><div class='ctx'> 			dm_new_crtc_state-&gt;stream-&gt;abm_level = dm_new_crtc_state-&gt;abm_level;</div><div class='ctx'> </div><div class='hunk'>@@ -9341,16 +10917,19 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 		 * Here we create an empty update on each plane.</div><div class='ctx'> 		 * To fix this, DC should permit updating only stream properties.</div><div class='ctx'> 		 */</div><div class='del'>-		dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);</div><div class='add'>+		dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL);</div><div class='ctx'> 		if (!dummy_updates) {</div><div class='del'>-			DRM_ERROR("Failed to allocate memory for dummy_updates.\n");</div><div class='add'>+			drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n");</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> 		for (j = 0; j &lt; status-&gt;plane_count; j++)</div><div class='ctx'> 			dummy_updates[j].surface = status-&gt;plane_states[0];</div><div class='ctx'> </div><div class='add'>+		sort(dummy_updates, status-&gt;plane_count,</div><div class='add'>+		     sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='add'>+		dc_exit_ips_for_hw_access(dm-&gt;dc);</div><div class='ctx'> 		dc_update_planes_and_stream(dm-&gt;dc,</div><div class='ctx'> 					    dummy_updates,</div><div class='ctx'> 					    status-&gt;plane_count,</div><div class='hunk'>@@ -9358,6 +10937,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 					    &amp;stream_update);</div><div class='ctx'> 		mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> 		kfree(dummy_updates);</div><div class='add'>+</div><div class='add'>+		drm_connector_update_privacy_screen(new_con_state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='hunk'>@@ -9392,7 +10973,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {</div><div class='ctx'> 			dc_stream_retain(dm_new_crtc_state-&gt;stream);</div><div class='ctx'> 			acrtc-&gt;dm_irq_params.stream = dm_new_crtc_state-&gt;stream;</div><div class='del'>-			manage_dm_interrupts(adev, acrtc, true);</div><div class='add'>+			manage_dm_interrupts(adev, acrtc, dm_new_crtc_state);</div><div class='ctx'> 		}</div><div class='ctx'> 		/* Handle vrr on-&gt;off / off-&gt;on transitions */</div><div class='ctx'> 		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);</div><div class='hunk'>@@ -9408,20 +10989,26 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 			if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='ctx'> 				if (amdgpu_dm_crc_window_is_activated(crtc)) {</div><div class='del'>-					spin_lock_irqsave(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='del'>-					acrtc-&gt;dm_irq_params.window_param.update_win = true;</div><div class='add'>+					uint8_t cnt;</div><div class='ctx'> </div><div class='del'>-					/**</div><div class='del'>-					 * It takes 2 frames for HW to stably generate CRC when</div><div class='del'>-					 * resuming from suspend, so we set skip_frame_cnt 2.</div><div class='del'>-					 */</div><div class='del'>-					acrtc-&gt;dm_irq_params.window_param.skip_frame_cnt = 2;</div><div class='add'>+					spin_lock_irqsave(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='add'>+					for (cnt = 0; cnt &lt; MAX_CRC_WINDOW_NUM; cnt++) {</div><div class='add'>+						if (acrtc-&gt;dm_irq_params.window_param[cnt].enable) {</div><div class='add'>+							acrtc-&gt;dm_irq_params.window_param[cnt].update_win = true;</div><div class='add'>+</div><div class='add'>+							/**</div><div class='add'>+							 * It takes 2 frames for HW to stably generate CRC when</div><div class='add'>+							 * resuming from suspend, so we set skip_frame_cnt 2.</div><div class='add'>+							 */</div><div class='add'>+							acrtc-&gt;dm_irq_params.window_param[cnt].skip_frame_cnt = 2;</div><div class='add'>+						}</div><div class='add'>+					}</div><div class='ctx'> 					spin_unlock_irqrestore(&amp;adev_to_drm(adev)-&gt;event_lock, flags);</div><div class='ctx'> 				}</div><div class='ctx'> #endif</div><div class='ctx'> 				if (amdgpu_dm_crtc_configure_crc_source(</div><div class='ctx'> 					crtc, dm_new_crtc_state, cur_crc_src))</div><div class='del'>-					DRM_DEBUG_DRIVER("Failed to configure crc source");</div><div class='add'>+					drm_dbg_atomic(dev, "Failed to configure crc source");</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> #endif</div><div class='hunk'>@@ -9516,6 +11103,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 	for (i = 0; i &lt; crtc_disable_count; i++)</div><div class='ctx'> 		pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> 	pm_runtime_mark_last_busy(dev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	trace_amdgpu_dm_atomic_commit_tail_finish(state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dm_force_atomic_commit(struct drm_connector *connector)</div><div class='hunk'>@@ -9541,16 +11130,20 @@ static int dm_force_atomic_commit(struct drm_connector *connector)</div><div class='ctx'> 	 */</div><div class='ctx'> 	conn_state = drm_atomic_get_connector_state(state, connector);</div><div class='ctx'> </div><div class='del'>-	ret = PTR_ERR_OR_ZERO(conn_state);</div><div class='del'>-	if (ret)</div><div class='add'>+	/* Check for error in getting connector state */</div><div class='add'>+	if (IS_ERR(conn_state)) {</div><div class='add'>+		ret = PTR_ERR(conn_state);</div><div class='ctx'> 		goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Attach crtc to drm_atomic_state*/</div><div class='ctx'> 	crtc_state = drm_atomic_get_crtc_state(state, &amp;disconnected_acrtc-&gt;base);</div><div class='ctx'> </div><div class='del'>-	ret = PTR_ERR_OR_ZERO(crtc_state);</div><div class='del'>-	if (ret)</div><div class='add'>+	/* Check for error in getting crtc state */</div><div class='add'>+	if (IS_ERR(crtc_state)) {</div><div class='add'>+		ret = PTR_ERR(crtc_state);</div><div class='ctx'> 		goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* force a restore */</div><div class='ctx'> 	crtc_state-&gt;mode_changed = true;</div><div class='hunk'>@@ -9558,9 +11151,11 @@ static int dm_force_atomic_commit(struct drm_connector *connector)</div><div class='ctx'> 	/* Attach plane to drm_atomic_state */</div><div class='ctx'> 	plane_state = drm_atomic_get_plane_state(state, plane);</div><div class='ctx'> </div><div class='del'>-	ret = PTR_ERR_OR_ZERO(plane_state);</div><div class='del'>-	if (ret)</div><div class='add'>+	/* Check for error in getting plane state */</div><div class='add'>+	if (IS_ERR(plane_state)) {</div><div class='add'>+		ret = PTR_ERR(plane_state);</div><div class='ctx'> 		goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Call commit internally with the state we just constructed */</div><div class='ctx'> 	ret = drm_atomic_commit(state);</div><div class='hunk'>@@ -9568,7 +11163,7 @@ static int dm_force_atomic_commit(struct drm_connector *connector)</div><div class='ctx'> out:</div><div class='ctx'> 	drm_atomic_state_put(state);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		DRM_ERROR("Restoring old state failed with %i\n", ret);</div><div class='add'>+		drm_err(ddev, "Restoring old state failed with %i\n", ret);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -9652,7 +11247,7 @@ static int do_aquire_global_lock(struct drm_device *dev,</div><div class='ctx'> 					&amp;commit-&gt;flip_done, 10*HZ);</div><div class='ctx'> </div><div class='ctx'> 		if (ret == 0)</div><div class='del'>-			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",</div><div class='add'>+			drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n",</div><div class='ctx'> 				  crtc-&gt;base.id, crtc-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 		drm_crtc_commit_put(commit);</div><div class='hunk'>@@ -9698,6 +11293,8 @@ static void get_freesync_config_for_crtc(</div><div class='ctx'> 		} else {</div><div class='ctx'> 			config.state = VRR_STATE_INACTIVE;</div><div class='ctx'> 		}</div><div class='add'>+	} else {</div><div class='add'>+		config.state = VRR_STATE_UNSUPPORTED;</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='ctx'> 	new_crtc_state-&gt;freesync_config = config;</div><div class='hunk'>@@ -9768,6 +11365,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	struct dm_atomic_state *dm_state = NULL;</div><div class='ctx'> 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='ctx'> 	struct dc_stream_state *new_stream;</div><div class='add'>+	struct amdgpu_device *adev = dm-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -9797,8 +11395,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		drm_old_conn_state = drm_atomic_get_old_connector_state(state,</div><div class='ctx'> 									connector);</div><div class='ctx'> </div><div class='del'>-		if (IS_ERR(drm_new_conn_state)) {</div><div class='del'>-			ret = PTR_ERR_OR_ZERO(drm_new_conn_state);</div><div class='add'>+		if (WARN_ON(!drm_new_conn_state)) {</div><div class='add'>+			ret = -EINVAL;</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -9808,7 +11406,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))</div><div class='ctx'> 			goto skip_modeset;</div><div class='ctx'> </div><div class='del'>-		new_stream = create_validate_stream_for_sink(aconnector,</div><div class='add'>+		new_stream = create_validate_stream_for_sink(connector,</div><div class='ctx'> 							     &amp;new_crtc_state-&gt;mode,</div><div class='ctx'> 							     dm_new_conn_state,</div><div class='ctx'> 							     dm_old_crtc_state-&gt;stream);</div><div class='hunk'>@@ -9821,7 +11419,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		 */</div><div class='ctx'> </div><div class='ctx'> 		if (!new_stream) {</div><div class='del'>-			DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",</div><div class='add'>+			drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n",</div><div class='ctx'> 					__func__, acrtc-&gt;base.base.id);</div><div class='ctx'> 			ret = -ENOMEM;</div><div class='ctx'> 			goto fail;</div><div class='hunk'>@@ -9859,7 +11457,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state-&gt;stream) &amp;&amp;</div><div class='ctx'> 		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state-&gt;stream)) {</div><div class='ctx'> 			new_crtc_state-&gt;mode_changed = false;</div><div class='del'>-			DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",</div><div class='add'>+			drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d",</div><div class='ctx'> 					 new_crtc_state-&gt;mode_changed);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -9897,7 +11495,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		    is_timing_unchanged_for_freesync(new_crtc_state,</div><div class='ctx'> 						     old_crtc_state)) {</div><div class='ctx'> 			new_crtc_state-&gt;mode_changed = false;</div><div class='del'>-			DRM_DEBUG_DRIVER(</div><div class='add'>+			drm_dbg_driver(adev_to_drm(adev),</div><div class='ctx'> 				"Mode change not required for front porch change, setting mode_changed to %d",</div><div class='ctx'> 				new_crtc_state-&gt;mode_changed);</div><div class='ctx'> </div><div class='hunk'>@@ -9918,7 +11516,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> </div><div class='del'>-		DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",</div><div class='add'>+		drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n",</div><div class='ctx'> 				crtc-&gt;base.id);</div><div class='ctx'> </div><div class='ctx'> 		/* i.e. reset mode */</div><div class='hunk'>@@ -10014,7 +11612,7 @@ skip_modeset:</div><div class='ctx'> 	if (dm_new_crtc_state-&gt;base.color_mgmt_changed ||</div><div class='ctx'> 	    dm_old_crtc_state-&gt;regamma_tf != dm_new_crtc_state-&gt;regamma_tf ||</div><div class='ctx'> 	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {</div><div class='del'>-		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);</div><div class='add'>+		ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -10038,7 +11636,8 @@ static bool should_reset_plane(struct drm_atomic_state *state,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_plane *other;</div><div class='ctx'> 	struct drm_plane_state *old_other_state, *new_other_state;</div><div class='del'>-	struct drm_crtc_state *new_crtc_state;</div><div class='add'>+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='add'>+	struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(plane-&gt;dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -10050,6 +11649,9 @@ static bool should_reset_plane(struct drm_atomic_state *state,</div><div class='ctx'> 	    state-&gt;allow_modeset)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_in_reset(adev) &amp;&amp; state-&gt;allow_modeset)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='ctx'> 	/* Exit early if we know that we're adding or removing the plane. */</div><div class='ctx'> 	if (old_plane_state-&gt;crtc != new_plane_state-&gt;crtc)</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -10060,14 +11662,38 @@ static bool should_reset_plane(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 	new_crtc_state =</div><div class='ctx'> 		drm_atomic_get_new_crtc_state(state, new_plane_state-&gt;crtc);</div><div class='add'>+	old_crtc_state =</div><div class='add'>+		drm_atomic_get_old_crtc_state(state, old_plane_state-&gt;crtc);</div><div class='ctx'> </div><div class='ctx'> 	if (!new_crtc_state)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * A change in cursor mode means a new dc pipe needs to be acquired or</div><div class='add'>+	 * released from the state</div><div class='add'>+	 */</div><div class='add'>+	old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);</div><div class='add'>+	new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+	if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR &amp;&amp;</div><div class='add'>+	    old_dm_crtc_state != NULL &amp;&amp;</div><div class='add'>+	    old_dm_crtc_state-&gt;cursor_mode != new_dm_crtc_state-&gt;cursor_mode) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* CRTC Degamma changes currently require us to recreate planes. */</div><div class='ctx'> 	if (new_crtc_state-&gt;color_mgmt_changed)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * On zpos change, planes need to be reordered by removing and re-adding</div><div class='add'>+	 * them one by one to the dc state, in order of descending zpos.</div><div class='add'>+	 *</div><div class='add'>+	 * TODO: We can likely skip bandwidth validation if the only thing that</div><div class='add'>+	 * changed about the plane was it'z z-ordering.</div><div class='add'>+	 */</div><div class='add'>+	if (old_plane_state-&gt;normalized_zpos != new_plane_state-&gt;normalized_zpos)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='ctx'> 	if (drm_atomic_crtc_needs_modeset(new_crtc_state))</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='hunk'>@@ -10199,12 +11825,14 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,</div><div class='ctx'> 	 * check tiling flags when the FB doesn't have a modifier.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!(fb-&gt;flags &amp; DRM_MODE_FB_MODIFIERS)) {</div><div class='del'>-		if (adev-&gt;family &lt; AMDGPU_FAMILY_AI) {</div><div class='add'>+		if (adev-&gt;family &gt;= AMDGPU_FAMILY_GC_12_0_0) {</div><div class='add'>+			linear = AMDGPU_TILING_GET(afb-&gt;tiling_flags, GFX12_SWIZZLE_MODE) == 0;</div><div class='add'>+		} else if (adev-&gt;family &gt;= AMDGPU_FAMILY_AI) {</div><div class='add'>+			linear = AMDGPU_TILING_GET(afb-&gt;tiling_flags, SWIZZLE_MODE) == 0;</div><div class='add'>+		} else {</div><div class='ctx'> 			linear = AMDGPU_TILING_GET(afb-&gt;tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &amp;&amp;</div><div class='ctx'> 				 AMDGPU_TILING_GET(afb-&gt;tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &amp;&amp;</div><div class='ctx'> 				 AMDGPU_TILING_GET(afb-&gt;tiling_flags, MICRO_TILE_MODE) == 0;</div><div class='del'>-		} else {</div><div class='del'>-			linear = AMDGPU_TILING_GET(afb-&gt;tiling_flags, SWIZZLE_MODE) == 0;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (!linear) {</div><div class='ctx'> 			DRM_DEBUG_ATOMIC("Cursor FB not linear");</div><div class='hunk'>@@ -10215,6 +11843,68 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Helper function for checking the cursor in native mode</div><div class='add'>+ */</div><div class='add'>+static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc,</div><div class='add'>+					struct drm_plane *plane,</div><div class='add'>+					struct drm_plane_state *new_plane_state,</div><div class='add'>+					bool enable)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct amdgpu_crtc *new_acrtc;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!enable || !new_plane_crtc ||</div><div class='add'>+	    drm_atomic_plane_disabling(plane-&gt;state, new_plane_state))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	new_acrtc = to_amdgpu_crtc(new_plane_crtc);</div><div class='add'>+</div><div class='add'>+	if (new_plane_state-&gt;src_x != 0 || new_plane_state-&gt;src_y != 0) {</div><div class='add'>+		DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (new_plane_state-&gt;fb) {</div><div class='add'>+		ret = dm_check_cursor_fb(new_acrtc, new_plane_state,</div><div class='add'>+						new_plane_state-&gt;fb);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dm_should_update_native_cursor(struct drm_atomic_state *state,</div><div class='add'>+					   struct drm_crtc *old_plane_crtc,</div><div class='add'>+					   struct drm_crtc *new_plane_crtc,</div><div class='add'>+					   bool enable)</div><div class='add'>+{</div><div class='add'>+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='add'>+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='add'>+</div><div class='add'>+	if (!enable) {</div><div class='add'>+		if (old_plane_crtc == NULL)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+		old_crtc_state = drm_atomic_get_old_crtc_state(</div><div class='add'>+			state, old_plane_crtc);</div><div class='add'>+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);</div><div class='add'>+</div><div class='add'>+		return dm_old_crtc_state-&gt;cursor_mode == DM_CURSOR_NATIVE_MODE;</div><div class='add'>+	} else {</div><div class='add'>+		if (new_plane_crtc == NULL)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+		new_crtc_state = drm_atomic_get_new_crtc_state(</div><div class='add'>+			state, new_plane_crtc);</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+</div><div class='add'>+		return dm_new_crtc_state-&gt;cursor_mode == DM_CURSOR_NATIVE_MODE;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 				 struct drm_atomic_state *state,</div><div class='ctx'> 				 struct drm_plane *plane,</div><div class='hunk'>@@ -10230,8 +11920,7 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='ctx'> 	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;</div><div class='ctx'> 	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;</div><div class='del'>-	struct amdgpu_crtc *new_acrtc;</div><div class='del'>-	bool needs_reset;</div><div class='add'>+	bool needs_reset, update_native_cursor;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -10240,24 +11929,16 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 	dm_new_plane_state = to_dm_plane_state(new_plane_state);</div><div class='ctx'> 	dm_old_plane_state = to_dm_plane_state(old_plane_state);</div><div class='ctx'> </div><div class='del'>-	if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR) {</div><div class='del'>-		if (!enable || !new_plane_crtc ||</div><div class='del'>-			drm_atomic_plane_disabling(plane-&gt;state, new_plane_state))</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='del'>-		new_acrtc = to_amdgpu_crtc(new_plane_crtc);</div><div class='del'>-</div><div class='del'>-		if (new_plane_state-&gt;src_x != 0 || new_plane_state-&gt;src_y != 0) {</div><div class='del'>-			DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='add'>+	update_native_cursor = dm_should_update_native_cursor(state,</div><div class='add'>+							      old_plane_crtc,</div><div class='add'>+							      new_plane_crtc,</div><div class='add'>+							      enable);</div><div class='ctx'> </div><div class='del'>-		if (new_plane_state-&gt;fb) {</div><div class='del'>-			ret = dm_check_cursor_fb(new_acrtc, new_plane_state,</div><div class='del'>-						 new_plane_state-&gt;fb);</div><div class='del'>-			if (ret)</div><div class='del'>-				return ret;</div><div class='del'>-		}</div><div class='add'>+	if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR &amp;&amp; update_native_cursor) {</div><div class='add'>+		ret = dm_check_native_cursor_state(new_plane_crtc, plane,</div><div class='add'>+						    new_plane_state, enable);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -10323,20 +12004,14 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 		ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='ctx'> 		WARN_ON(dm_new_plane_state-&gt;dc_state);</div><div class='ctx'> </div><div class='ctx'> 		dc_new_plane_state = dc_create_plane_state(dc);</div><div class='del'>-		if (!dc_new_plane_state)</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-</div><div class='del'>-		/* Block top most plane from being a video plane */</div><div class='del'>-		if (plane-&gt;type == DRM_PLANE_TYPE_OVERLAY) {</div><div class='del'>-			if (amdgpu_dm_plane_is_video_format(new_plane_state-&gt;fb-&gt;format-&gt;format) &amp;&amp; *is_top_most_overlay)</div><div class='del'>-				return -EINVAL;</div><div class='del'>-</div><div class='del'>-			*is_top_most_overlay = false;</div><div class='add'>+		if (!dc_new_plane_state) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",</div><div class='hunk'>@@ -10349,13 +12024,13 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 			new_crtc_state);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dc_plane_state_release(dc_new_plane_state);</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		ret = dm_atomic_get_state(state, &amp;dm_state);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dc_plane_state_release(dc_new_plane_state);</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -10372,7 +12047,8 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 				dm_state-&gt;context)) {</div><div class='ctx'> </div><div class='ctx'> 			dc_plane_state_release(dc_new_plane_state);</div><div class='del'>-			return -EINVAL;</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dm_new_plane_state-&gt;dc_state = dc_new_plane_state;</div><div class='hunk'>@@ -10387,6 +12063,16 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 		*lock_and_validation_needed = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+	/* If enabling cursor overlay failed, attempt fallback to native mode */</div><div class='add'>+	if (enable &amp;&amp; ret == -EINVAL &amp;&amp; plane-&gt;type == DRM_PLANE_TYPE_CURSOR) {</div><div class='add'>+		ret = dm_check_native_cursor_state(new_plane_crtc, plane,</div><div class='add'>+						    new_plane_state, enable);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		dm_new_crtc_state-&gt;cursor_mode = DM_CURSOR_NATIVE_MODE;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -10416,131 +12102,283 @@ dm_get_plane_scale(struct drm_plane_state *plane_state,</div><div class='ctx'> 	int plane_src_w, plane_src_h;</div><div class='ctx'> </div><div class='ctx'> 	dm_get_oriented_plane_size(plane_state, &amp;plane_src_w, &amp;plane_src_h);</div><div class='del'>-	*out_plane_scale_w = plane_state-&gt;crtc_w * 1000 / plane_src_w;</div><div class='del'>-	*out_plane_scale_h = plane_state-&gt;crtc_h * 1000 / plane_src_h;</div><div class='add'>+	*out_plane_scale_w = plane_src_w ? plane_state-&gt;crtc_w * 1000 / plane_src_w : 0;</div><div class='add'>+	*out_plane_scale_h = plane_src_h ? plane_state-&gt;crtc_h * 1000 / plane_src_h : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dm_check_crtc_cursor(struct drm_atomic_state *state,</div><div class='del'>-				struct drm_crtc *crtc,</div><div class='del'>-				struct drm_crtc_state *new_crtc_state)</div><div class='add'>+/*</div><div class='add'>+ * The normalized_zpos value cannot be used by this iterator directly. It's only</div><div class='add'>+ * calculated for enabled planes, potentially causing normalized_zpos collisions</div><div class='add'>+ * between enabled/disabled planes in the atomic state. We need a unique value</div><div class='add'>+ * so that the iterator will not generate the same object twice, or loop</div><div class='add'>+ * indefinitely.</div><div class='add'>+ */</div><div class='add'>+static inline struct __drm_planes_state *__get_next_zpos(</div><div class='add'>+	struct drm_atomic_state *state,</div><div class='add'>+	struct __drm_planes_state *prev)</div><div class='ctx'> {</div><div class='del'>-	struct drm_plane *cursor = crtc-&gt;cursor, *plane, *underlying;</div><div class='del'>-	struct drm_plane_state *old_plane_state, *new_plane_state;</div><div class='del'>-	struct drm_plane_state *new_cursor_state, *new_underlying_state;</div><div class='add'>+	unsigned int highest_zpos = 0, prev_zpos = 256;</div><div class='add'>+	uint32_t highest_id = 0, prev_id = UINT_MAX;</div><div class='add'>+	struct drm_plane_state *new_plane_state;</div><div class='add'>+	struct drm_plane *plane;</div><div class='add'>+	int i, highest_i = -1;</div><div class='add'>+</div><div class='add'>+	if (prev != NULL) {</div><div class='add'>+		prev_zpos = prev-&gt;new_state-&gt;zpos;</div><div class='add'>+		prev_id = prev-&gt;ptr-&gt;base.id;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_new_plane_in_state(state, plane, new_plane_state, i) {</div><div class='add'>+		/* Skip planes with higher zpos than the previously returned */</div><div class='add'>+		if (new_plane_state-&gt;zpos &gt; prev_zpos ||</div><div class='add'>+		    (new_plane_state-&gt;zpos == prev_zpos &amp;&amp;</div><div class='add'>+		     plane-&gt;base.id &gt;= prev_id))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Save the index of the plane with highest zpos */</div><div class='add'>+		if (new_plane_state-&gt;zpos &gt; highest_zpos ||</div><div class='add'>+		    (new_plane_state-&gt;zpos == highest_zpos &amp;&amp;</div><div class='add'>+		     plane-&gt;base.id &gt; highest_id)) {</div><div class='add'>+			highest_zpos = new_plane_state-&gt;zpos;</div><div class='add'>+			highest_id = plane-&gt;base.id;</div><div class='add'>+			highest_i = i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (highest_i &lt; 0)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return &amp;state-&gt;planes[highest_i];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate</div><div class='add'>+ * by descending zpos, as read from the new plane state. This is the same</div><div class='add'>+ * ordering as defined by drm_atomic_normalize_zpos().</div><div class='add'>+ */</div><div class='add'>+#define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \</div><div class='add'>+	for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \</div><div class='add'>+	     __i != NULL; __i = __get_next_zpos((__state), __i))		\</div><div class='add'>+		for_each_if(((plane) = __i-&gt;ptr,				\</div><div class='add'>+			     (void)(plane) /* Only to avoid unused-but-set-variable warning */, \</div><div class='add'>+			     (old_plane_state) = __i-&gt;old_state,		\</div><div class='add'>+			     (new_plane_state) = __i-&gt;new_state, 1))</div><div class='add'>+</div><div class='add'>+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector;</div><div class='add'>+	struct drm_connector_state *conn_state, *old_conn_state;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {</div><div class='add'>+		if (!conn_state-&gt;crtc)</div><div class='add'>+			conn_state = old_conn_state;</div><div class='add'>+</div><div class='add'>+		if (conn_state-&gt;crtc != crtc)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+		if (!aconnector-&gt;mst_output_port || !aconnector-&gt;mst_root)</div><div class='add'>+			aconnector = NULL;</div><div class='add'>+		else</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!aconnector)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return drm_dp_mst_add_affected_dsc_crtcs(state, &amp;aconnector-&gt;mst_root-&gt;mst_mgr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Cursor Modes - Native vs Overlay</div><div class='add'>+ *</div><div class='add'>+ * In native mode, the cursor uses a integrated cursor pipe within each DCN hw</div><div class='add'>+ * plane. It does not require a dedicated hw plane to enable, but it is</div><div class='add'>+ * subjected to the same z-order and scaling as the hw plane. It also has format</div><div class='add'>+ * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB</div><div class='add'>+ * hw plane.</div><div class='add'>+ *</div><div class='add'>+ * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its</div><div class='add'>+ * own scaling and z-pos. It also has no blending restrictions. It lends to a</div><div class='add'>+ * cursor behavior more akin to a DRM client's expectations. However, it does</div><div class='add'>+ * occupy an extra DCN plane, and therefore will only be used if a DCN plane is</div><div class='add'>+ * available.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc</div><div class='add'>+ * @adev: amdgpu device</div><div class='add'>+ * @state: DRM atomic state</div><div class='add'>+ * @dm_crtc_state: amdgpu state for the CRTC containing the cursor</div><div class='add'>+ * @cursor_mode: Returns the required cursor mode on dm_crtc_state</div><div class='add'>+ *</div><div class='add'>+ * Get whether the cursor should be enabled in native mode, or overlay mode, on</div><div class='add'>+ * the dm_crtc_state.</div><div class='add'>+ *</div><div class='add'>+ * The cursor should be enabled in overlay mode if there exists an underlying</div><div class='add'>+ * plane - on which the cursor may be blended - that is either YUV formatted, or</div><div class='add'>+ * scaled differently from the cursor.</div><div class='add'>+ *</div><div class='add'>+ * Since zpos info is required, drm_atomic_normalize_zpos must be called before</div><div class='add'>+ * calling this function.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, or an error code if getting the cursor plane state</div><div class='add'>+ * failed.</div><div class='add'>+ */</div><div class='add'>+static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,</div><div class='add'>+				   struct drm_atomic_state *state,</div><div class='add'>+				   struct dm_crtc_state *dm_crtc_state,</div><div class='add'>+				   enum amdgpu_dm_cursor_mode *cursor_mode)</div><div class='add'>+{</div><div class='add'>+	struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;</div><div class='add'>+	struct drm_crtc_state *crtc_state = &amp;dm_crtc_state-&gt;base;</div><div class='add'>+	struct drm_plane *plane;</div><div class='add'>+	bool consider_mode_change = false;</div><div class='add'>+	bool entire_crtc_covered = false;</div><div class='add'>+	bool cursor_changed = false;</div><div class='add'>+	int underlying_scale_w, underlying_scale_h;</div><div class='add'>+	int cursor_scale_w, cursor_scale_h;</div><div class='ctx'> 	int i;</div><div class='del'>-	int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;</div><div class='del'>-	bool any_relevant_change = false;</div><div class='ctx'> </div><div class='del'>-	/* On DCE and DCN there is no dedicated hardware cursor plane. We get a</div><div class='del'>-	 * cursor per pipe but it's going to inherit the scaling and</div><div class='del'>-	 * positioning from the underlying pipe. Check the cursor plane's</div><div class='del'>-	 * blending properties match the underlying planes'.</div><div class='add'>+	/* Overlay cursor not supported on HW before DCN</div><div class='add'>+	 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions</div><div class='add'>+	 * as previous DCN generations, so enable native mode on DCN401 in addition to DCE</div><div class='ctx'> 	 */</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 ||</div><div class='add'>+	    amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {</div><div class='add'>+		*cursor_mode = DM_CURSOR_NATIVE_MODE;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* If no plane was enabled or changed scaling, no need to check again */</div><div class='del'>-	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {</div><div class='add'>+	/* Init cursor_mode to be the same as current */</div><div class='add'>+	*cursor_mode = dm_crtc_state-&gt;cursor_mode;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Cursor mode can change if a plane's format changes, scale changes, is</div><div class='add'>+	 * enabled/disabled, or z-order changes.</div><div class='add'>+	 */</div><div class='add'>+	for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {</div><div class='ctx'> 		int new_scale_w, new_scale_h, old_scale_w, old_scale_h;</div><div class='ctx'> </div><div class='del'>-		if (!new_plane_state || !new_plane_state-&gt;fb || new_plane_state-&gt;crtc != crtc)</div><div class='add'>+		/* Only care about planes on this CRTC */</div><div class='add'>+		if ((drm_plane_mask(plane) &amp; crtc_state-&gt;plane_mask) == 0)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (!old_plane_state || !old_plane_state-&gt;fb || old_plane_state-&gt;crtc != crtc) {</div><div class='del'>-			any_relevant_change = true;</div><div class='add'>+		if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR)</div><div class='add'>+			cursor_changed = true;</div><div class='add'>+</div><div class='add'>+		if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||</div><div class='add'>+		    drm_atomic_plane_disabling(old_plane_state, plane_state) ||</div><div class='add'>+		    old_plane_state-&gt;fb-&gt;format != plane_state-&gt;fb-&gt;format) {</div><div class='add'>+			consider_mode_change = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (new_plane_state-&gt;fb == old_plane_state-&gt;fb &amp;&amp;</div><div class='del'>-		    new_plane_state-&gt;crtc_w == old_plane_state-&gt;crtc_w &amp;&amp;</div><div class='del'>-		    new_plane_state-&gt;crtc_h == old_plane_state-&gt;crtc_h)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		dm_get_plane_scale(new_plane_state, &amp;new_scale_w, &amp;new_scale_h);</div><div class='add'>+		dm_get_plane_scale(plane_state, &amp;new_scale_w, &amp;new_scale_h);</div><div class='ctx'> 		dm_get_plane_scale(old_plane_state, &amp;old_scale_w, &amp;old_scale_h);</div><div class='del'>-</div><div class='ctx'> 		if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {</div><div class='del'>-			any_relevant_change = true;</div><div class='add'>+			consider_mode_change = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!any_relevant_change)</div><div class='add'>+	if (!consider_mode_change &amp;&amp; !crtc_state-&gt;zpos_changed)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	new_cursor_state = drm_atomic_get_plane_state(state, cursor);</div><div class='del'>-	if (IS_ERR(new_cursor_state))</div><div class='del'>-		return PTR_ERR(new_cursor_state);</div><div class='del'>-</div><div class='del'>-	if (!new_cursor_state-&gt;fb)</div><div class='add'>+	/*</div><div class='add'>+	 * If no cursor change on this CRTC, and not enabled on this CRTC, then</div><div class='add'>+	 * no need to set cursor mode. This avoids needlessly locking the cursor</div><div class='add'>+	 * state.</div><div class='add'>+	 */</div><div class='add'>+	if (!cursor_changed &amp;&amp;</div><div class='add'>+	    !(drm_plane_mask(crtc_state-&gt;crtc-&gt;cursor) &amp; crtc_state-&gt;plane_mask)) {</div><div class='ctx'> 		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cursor_state = drm_atomic_get_plane_state(state,</div><div class='add'>+						  crtc_state-&gt;crtc-&gt;cursor);</div><div class='add'>+	if (IS_ERR(cursor_state))</div><div class='add'>+		return PTR_ERR(cursor_state);</div><div class='ctx'> </div><div class='del'>-	dm_get_plane_scale(new_cursor_state, &amp;cursor_scale_w, &amp;cursor_scale_h);</div><div class='add'>+	/* Cursor is disabled */</div><div class='add'>+	if (!cursor_state-&gt;fb)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	/* Need to check all enabled planes, even if this commit doesn't change</div><div class='del'>-	 * their state</div><div class='add'>+	/* For all planes in descending z-order (all of which are below cursor</div><div class='add'>+	 * as per zpos definitions), check their scaling and format</div><div class='ctx'> 	 */</div><div class='del'>-	i = drm_atomic_add_affected_planes(state, crtc);</div><div class='del'>-	if (i)</div><div class='del'>-		return i;</div><div class='add'>+	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {</div><div class='ctx'> </div><div class='del'>-	for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {</div><div class='del'>-		/* Narrow down to non-cursor planes on the same CRTC as the cursor */</div><div class='del'>-		if (new_underlying_state-&gt;crtc != crtc || underlying == crtc-&gt;cursor)</div><div class='add'>+		/* Only care about non-cursor planes on this CRTC */</div><div class='add'>+		if ((drm_plane_mask(plane) &amp; crtc_state-&gt;plane_mask) == 0 ||</div><div class='add'>+		    plane-&gt;type == DRM_PLANE_TYPE_CURSOR)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		/* Ignore disabled planes */</div><div class='del'>-		if (!new_underlying_state-&gt;fb)</div><div class='del'>-			continue;</div><div class='add'>+		/* Underlying plane is YUV format - use overlay cursor */</div><div class='add'>+		if (amdgpu_dm_plane_is_video_format(plane_state-&gt;fb-&gt;format-&gt;format)) {</div><div class='add'>+			*cursor_mode = DM_CURSOR_OVERLAY_MODE;</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		dm_get_plane_scale(new_underlying_state,</div><div class='add'>+		dm_get_plane_scale(plane_state,</div><div class='ctx'> 				   &amp;underlying_scale_w, &amp;underlying_scale_h);</div><div class='add'>+		dm_get_plane_scale(cursor_state,</div><div class='add'>+				   &amp;cursor_scale_w, &amp;cursor_scale_h);</div><div class='ctx'> </div><div class='del'>-		if (cursor_scale_w != underlying_scale_w ||</div><div class='add'>+		/* Underlying plane has different scale - use overlay cursor */</div><div class='add'>+		if (cursor_scale_w != underlying_scale_w &amp;&amp;</div><div class='ctx'> 		    cursor_scale_h != underlying_scale_h) {</div><div class='del'>-			drm_dbg_atomic(crtc-&gt;dev,</div><div class='del'>-				       "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",</div><div class='del'>-				       cursor-&gt;base.id, cursor-&gt;name, underlying-&gt;base.id, underlying-&gt;name);</div><div class='del'>-			return -EINVAL;</div><div class='add'>+			*cursor_mode = DM_CURSOR_OVERLAY_MODE;</div><div class='add'>+			return 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* If this plane covers the whole CRTC, no need to check planes underneath */</div><div class='del'>-		if (new_underlying_state-&gt;crtc_x &lt;= 0 &amp;&amp;</div><div class='del'>-		    new_underlying_state-&gt;crtc_y &lt;= 0 &amp;&amp;</div><div class='del'>-		    new_underlying_state-&gt;crtc_x + new_underlying_state-&gt;crtc_w &gt;= new_crtc_state-&gt;mode.hdisplay &amp;&amp;</div><div class='del'>-		    new_underlying_state-&gt;crtc_y + new_underlying_state-&gt;crtc_h &gt;= new_crtc_state-&gt;mode.vdisplay)</div><div class='add'>+		if (plane_state-&gt;crtc_x &lt;= 0 &amp;&amp; plane_state-&gt;crtc_y &lt;= 0 &amp;&amp;</div><div class='add'>+		    plane_state-&gt;crtc_x + plane_state-&gt;crtc_w &gt;= crtc_state-&gt;mode.hdisplay &amp;&amp;</div><div class='add'>+		    plane_state-&gt;crtc_y + plane_state-&gt;crtc_h &gt;= crtc_state-&gt;mode.vdisplay) {</div><div class='add'>+			entire_crtc_covered = true;</div><div class='ctx'> 			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* If planes do not cover the entire CRTC, use overlay mode to enable</div><div class='add'>+	 * cursor over holes</div><div class='add'>+	 */</div><div class='add'>+	if (entire_crtc_covered)</div><div class='add'>+		*cursor_mode = DM_CURSOR_NATIVE_MODE;</div><div class='add'>+	else</div><div class='add'>+		*cursor_mode = DM_CURSOR_OVERLAY_MODE;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)</div><div class='add'>+static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,</div><div class='add'>+					    struct drm_atomic_state *state,</div><div class='add'>+					    struct drm_crtc_state *crtc_state)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-	struct drm_connector_state *conn_state, *old_conn_state;</div><div class='del'>-	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {</div><div class='del'>-		if (!conn_state-&gt;crtc)</div><div class='del'>-			conn_state = old_conn_state;</div><div class='add'>+	struct drm_plane *plane;</div><div class='add'>+	struct drm_plane_state *new_plane_state, *old_plane_state;</div><div class='ctx'> </div><div class='del'>-		if (conn_state-&gt;crtc != crtc)</div><div class='del'>-			continue;</div><div class='add'>+	drm_for_each_plane_mask(plane, dev, crtc_state-&gt;plane_mask) {</div><div class='add'>+		new_plane_state = drm_atomic_get_plane_state(state, plane);</div><div class='add'>+		old_plane_state = drm_atomic_get_plane_state(state, plane);</div><div class='ctx'> </div><div class='del'>-		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='del'>-			continue;</div><div class='add'>+		if (IS_ERR(new_plane_state) || IS_ERR(old_plane_state)) {</div><div class='add'>+			drm_err(dev, "Failed to get plane state for plane %s\n", plane-&gt;name);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		aconnector = to_amdgpu_dm_connector(connector);</div><div class='del'>-		if (!aconnector-&gt;mst_output_port || !aconnector-&gt;mst_root)</div><div class='del'>-			aconnector = NULL;</div><div class='del'>-		else</div><div class='del'>-			break;</div><div class='add'>+		if (old_plane_state-&gt;fb &amp;&amp; new_plane_state-&gt;fb &amp;&amp;</div><div class='add'>+		    get_mem_type(old_plane_state-&gt;fb) != get_mem_type(new_plane_state-&gt;fb))</div><div class='add'>+			return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!aconnector)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	return drm_dp_mst_add_affected_dsc_crtcs(state, &amp;aconnector-&gt;mst_root-&gt;mst_mgr);</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -10579,7 +12417,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='ctx'> 	struct drm_plane *plane;</div><div class='del'>-	struct drm_plane_state *old_plane_state, *new_plane_state;</div><div class='add'>+	struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state;</div><div class='ctx'> 	enum dc_status status;</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> 	bool lock_and_validation_needed = false;</div><div class='hunk'>@@ -10587,13 +12425,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='ctx'> 	struct drm_dp_mst_topology_mgr *mgr;</div><div class='ctx'> 	struct drm_dp_mst_topology_state *mst_state;</div><div class='del'>-	struct dsc_mst_fairness_vars vars[MAX_PIPES];</div><div class='add'>+	struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};</div><div class='ctx'> </div><div class='ctx'> 	trace_amdgpu_dm_atomic_check_begin(state);</div><div class='ctx'> </div><div class='ctx'> 	ret = drm_atomic_helper_check_modeset(dev, state);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");</div><div class='add'>+		drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n");</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -10608,7 +12446,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 		new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state-&gt;crtc);</div><div class='ctx'> 		if (IS_ERR(new_crtc_state)) {</div><div class='del'>-			DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n");</div><div class='ctx'> 			ret = PTR_ERR(new_crtc_state);</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -10623,7 +12461,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {</div><div class='ctx'> 				ret = add_affected_mst_dsc_crtcs(state, crtc);</div><div class='ctx'> 				if (ret) {</div><div class='del'>-					DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");</div><div class='add'>+					drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n");</div><div class='ctx'> 					goto fail;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -10640,7 +12478,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 		ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -10649,13 +12487,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 		ret = drm_atomic_add_affected_connectors(state, crtc);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		ret = drm_atomic_add_affected_planes(state, crtc);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -10694,7 +12532,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 			if (IS_ERR(new_plane_state)) {</div><div class='ctx'> 				ret = PTR_ERR(new_plane_state);</div><div class='del'>-				DRM_DEBUG_DRIVER("new_plane_state is BAD\n");</div><div class='add'>+				drm_dbg_atomic(dev, "new_plane_state is BAD\n");</div><div class='ctx'> 				goto fail;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -10712,12 +12550,34 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Determine whether cursors on each CRTC should be enabled in native or</div><div class='add'>+	 * overlay mode.</div><div class='add'>+	 */</div><div class='add'>+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+</div><div class='add'>+		ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,</div><div class='add'>+					      &amp;dm_new_crtc_state-&gt;cursor_mode);</div><div class='add'>+		if (ret) {</div><div class='add'>+			drm_dbg(dev, "Failed to determine cursor mode\n");</div><div class='add'>+			goto fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * If overlay cursor is needed, DC cannot go through the</div><div class='add'>+		 * native cursor update path. All enabled planes on the CRTC</div><div class='add'>+		 * need to be added for DC to not disable a plane by mistake</div><div class='add'>+		 */</div><div class='add'>+		if (dm_new_crtc_state-&gt;cursor_mode == DM_CURSOR_OVERLAY_MODE) {</div><div class='add'>+			ret = drm_atomic_add_affected_planes(state, crtc);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Remove exiting planes if they are modified */</div><div class='del'>-	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {</div><div class='del'>-		if (old_plane_state-&gt;fb &amp;&amp; new_plane_state-&gt;fb &amp;&amp;</div><div class='del'>-		    get_mem_type(old_plane_state-&gt;fb) !=</div><div class='del'>-		    get_mem_type(new_plane_state-&gt;fb))</div><div class='del'>-			lock_and_validation_needed = true;</div><div class='add'>+	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {</div><div class='ctx'> </div><div class='ctx'> 		ret = dm_update_plane_state(dc, state, plane,</div><div class='ctx'> 					    old_plane_state,</div><div class='hunk'>@@ -10726,7 +12586,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 					    &amp;lock_and_validation_needed,</div><div class='ctx'> 					    &amp;is_top_most_overlay);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -10739,7 +12599,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 					   false,</div><div class='ctx'> 					   &amp;lock_and_validation_needed);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -10752,13 +12612,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 					   true,</div><div class='ctx'> 					   &amp;lock_and_validation_needed);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Add new/modified planes */</div><div class='del'>-	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {</div><div class='add'>+	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {</div><div class='ctx'> 		ret = dm_update_plane_state(dc, state, plane,</div><div class='ctx'> 					    old_plane_state,</div><div class='ctx'> 					    new_plane_state,</div><div class='hunk'>@@ -10766,35 +12626,75 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 					    &amp;lock_and_validation_needed,</div><div class='ctx'> 					    &amp;is_top_most_overlay);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "dm_update_plane_state() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> 	if (dc_resource_is_dsc_encoding_supported(dc)) {</div><div class='ctx'> 		ret = pre_validate_dsc(state, &amp;dm_state, vars);</div><div class='ctx'> 		if (ret != 0)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 	}</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> 	/* Run this here since we want to validate the streams we created */</div><div class='ctx'> 	ret = drm_atomic_helper_check_planes(dev, state);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");</div><div class='add'>+		drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n");</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {</div><div class='ctx'> 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='ctx'> 		if (dm_new_crtc_state-&gt;mpo_requested)</div><div class='del'>-			DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);</div><div class='add'>+			drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Check cursor planes scaling */</div><div class='add'>+	/* Check cursor restrictions */</div><div class='ctx'> 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {</div><div class='del'>-		ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);</div><div class='add'>+		enum amdgpu_dm_cursor_mode required_cursor_mode;</div><div class='add'>+		int is_rotated, is_scaled;</div><div class='add'>+</div><div class='add'>+		/* Overlay cusor not subject to native cursor restrictions */</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+		if (dm_new_crtc_state-&gt;cursor_mode == DM_CURSOR_OVERLAY_MODE)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Check if rotation or scaling is enabled on DCN401 */</div><div class='add'>+		if ((drm_plane_mask(crtc-&gt;cursor) &amp; new_crtc_state-&gt;plane_mask) &amp;&amp;</div><div class='add'>+		    amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) {</div><div class='add'>+			new_cursor_state = drm_atomic_get_new_plane_state(state, crtc-&gt;cursor);</div><div class='add'>+</div><div class='add'>+			is_rotated = new_cursor_state &amp;&amp;</div><div class='add'>+				((new_cursor_state-&gt;rotation &amp; DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0);</div><div class='add'>+			is_scaled = new_cursor_state &amp;&amp; ((new_cursor_state-&gt;src_w &gt;&gt; 16 != new_cursor_state-&gt;crtc_w) ||</div><div class='add'>+				(new_cursor_state-&gt;src_h &gt;&gt; 16 != new_cursor_state-&gt;crtc_h));</div><div class='add'>+</div><div class='add'>+			if (is_rotated || is_scaled) {</div><div class='add'>+				drm_dbg_driver(</div><div class='add'>+					crtc-&gt;dev,</div><div class='add'>+					"[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n",</div><div class='add'>+					crtc-&gt;base.id, crtc-&gt;name);</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+				goto fail;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* If HW can only do native cursor, check restrictions again */</div><div class='add'>+		ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,</div><div class='add'>+					      &amp;required_cursor_mode);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");</div><div class='add'>+			drm_dbg_driver(crtc-&gt;dev,</div><div class='add'>+				       "[CRTC:%d:%s] Checking cursor mode failed\n",</div><div class='add'>+				       crtc-&gt;base.id, crtc-&gt;name);</div><div class='add'>+			goto fail;</div><div class='add'>+		} else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) {</div><div class='add'>+			drm_dbg_driver(crtc-&gt;dev,</div><div class='add'>+				       "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n",</div><div class='add'>+				       crtc-&gt;base.id, crtc-&gt;name);</div><div class='add'>+			ret = -EINVAL;</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -10877,28 +12777,30 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 	if (lock_and_validation_needed) {</div><div class='ctx'> 		ret = dm_atomic_get_state(state, &amp;dm_state);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		ret = do_aquire_global_lock(dev, state);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> 		if (dc_resource_is_dsc_encoding_supported(dc)) {</div><div class='ctx'> 			ret = compute_mst_dsc_configs_for_state(state, dm_state-&gt;context, vars);</div><div class='ctx'> 			if (ret) {</div><div class='del'>-				DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");</div><div class='add'>+				drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n");</div><div class='ctx'> 				ret = -EINVAL;</div><div class='ctx'> 				goto fail;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> 		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-&gt;context, vars);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -10910,12 +12812,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 		 */</div><div class='ctx'> 		ret = drm_dp_mst_atomic_check(state);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");</div><div class='add'>+			drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n");</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='del'>-		status = dc_validate_global_state(dc, dm_state-&gt;context, true);</div><div class='add'>+		status = dc_validate_global_state(dc, dm_state-&gt;context, DC_VALIDATE_MODE_ONLY);</div><div class='ctx'> 		if (status != DC_OK) {</div><div class='del'>-			DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",</div><div class='add'>+			drm_dbg_atomic(dev, "DC global validation failure: %s (%d)",</div><div class='ctx'> 				       dc_status_to_str(status), status);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto fail;</div><div class='hunk'>@@ -10942,7 +12844,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 				int j = state-&gt;num_private_objs-1;</div><div class='ctx'> </div><div class='ctx'> 				dm_atomic_destroy_state(obj,</div><div class='del'>-						state-&gt;private_objs[i].state);</div><div class='add'>+						state-&gt;private_objs[i].state_to_destroy);</div><div class='ctx'> </div><div class='ctx'> 				/* If i is not at the end of the array then the</div><div class='ctx'> 				 * last element needs to be moved to where i was</div><div class='hunk'>@@ -10953,7 +12855,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> 						state-&gt;private_objs[j];</div><div class='ctx'> </div><div class='ctx'> 				state-&gt;private_objs[j].ptr = NULL;</div><div class='del'>-				state-&gt;private_objs[j].state = NULL;</div><div class='add'>+				state-&gt;private_objs[j].state_to_destroy = NULL;</div><div class='ctx'> 				state-&gt;private_objs[j].old_state = NULL;</div><div class='ctx'> 				state-&gt;private_objs[j].new_state = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -10970,9 +12872,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Only allow async flips for fast updates that don't change</div><div class='del'>-		 * the FB pitch, the DCC state, rotation, etc.</div><div class='add'>+		 * the FB pitch, the DCC state, rotation, mem_type, etc.</div><div class='ctx'> 		 */</div><div class='del'>-		if (new_crtc_state-&gt;async_flip &amp;&amp; lock_and_validation_needed) {</div><div class='add'>+		if (new_crtc_state-&gt;async_flip &amp;&amp;</div><div class='add'>+		    (lock_and_validation_needed ||</div><div class='add'>+		     amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) {</div><div class='ctx'> 			drm_dbg_atomic(crtc-&gt;dev,</div><div class='ctx'> 				       "[CRTC:%d:%s] async flips are only supported for fast updates\n",</div><div class='ctx'> 				       crtc-&gt;base.id, crtc-&gt;name);</div><div class='hunk'>@@ -10993,36 +12897,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='ctx'> 	if (ret == -EDEADLK)</div><div class='del'>-		DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");</div><div class='add'>+		drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n");</div><div class='ctx'> 	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)</div><div class='del'>-		DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");</div><div class='add'>+		drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n");</div><div class='ctx'> 	else</div><div class='del'>-		DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);</div><div class='add'>+		drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret);</div><div class='ctx'> </div><div class='ctx'> 	trace_amdgpu_dm_atomic_check_finish(state, ret);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool is_dp_capable_without_timing_msa(struct dc *dc,</div><div class='del'>-					     struct amdgpu_dm_connector *amdgpu_dm_connector)</div><div class='del'>-{</div><div class='del'>-	u8 dpcd_data;</div><div class='del'>-	bool capable = false;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_dm_connector-&gt;dc_link &amp;&amp;</div><div class='del'>-		dm_helpers_dp_read_dpcd(</div><div class='del'>-				NULL,</div><div class='del'>-				amdgpu_dm_connector-&gt;dc_link,</div><div class='del'>-				DP_DOWN_STREAM_PORT_COUNT,</div><div class='del'>-				&amp;dpcd_data,</div><div class='del'>-				sizeof(dpcd_data))) {</div><div class='del'>-		capable = (dpcd_data &amp; DP_MSA_TIMING_PAR_IGNORED) ? true:false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return capable;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		unsigned int offset,</div><div class='ctx'> 		unsigned int total_length,</div><div class='hunk'>@@ -11053,7 +12938,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	res = dc_wake_and_execute_dmub_cmd(dm-&gt;dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='ctx'> 	if (!res) {</div><div class='del'>-		DRM_ERROR("EDID CEA parser failed\n");</div><div class='add'>+		drm_err(adev_to_drm(dm-&gt;adev), "EDID CEA parser failed\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -11061,7 +12946,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	if (output-&gt;type == DMUB_CMD__EDID_CEA_ACK) {</div><div class='ctx'> 		if (!output-&gt;ack.success) {</div><div class='del'>-			DRM_ERROR("EDID CEA ack failed at offset %d\n",</div><div class='add'>+			drm_err(adev_to_drm(dm-&gt;adev), "EDID CEA ack failed at offset %d\n",</div><div class='ctx'> 					output-&gt;ack.offset);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (output-&gt;type == DMUB_CMD__EDID_CEA_AMD_VSDB) {</div><div class='hunk'>@@ -11073,7 +12958,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		vsdb-&gt;min_refresh_rate_hz = output-&gt;amd_vsdb.min_frame_rate;</div><div class='ctx'> 		vsdb-&gt;max_refresh_rate_hz = output-&gt;amd_vsdb.max_frame_rate;</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_WARN("Unknown EDID CEA parser results\n");</div><div class='add'>+		drm_warn(adev_to_drm(dm-&gt;adev), "Unknown EDID CEA parser results\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -11153,8 +13038,51 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void parse_edid_displayid_vrr(struct drm_connector *connector,</div><div class='add'>+				     const struct edid *edid)</div><div class='add'>+{</div><div class='add'>+	u8 *edid_ext = NULL;</div><div class='add'>+	int i;</div><div class='add'>+	int j = 0;</div><div class='add'>+	u16 min_vfreq;</div><div class='add'>+	u16 max_vfreq;</div><div class='add'>+</div><div class='add'>+	if (edid == NULL || edid-&gt;extensions == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Find DisplayID extension */</div><div class='add'>+	for (i = 0; i &lt; edid-&gt;extensions; i++) {</div><div class='add'>+		edid_ext = (void *)(edid + (i + 1));</div><div class='add'>+		if (edid_ext[0] == DISPLAYID_EXT)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (edid_ext == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	while (j &lt; EDID_LENGTH) {</div><div class='add'>+		/* Get dynamic video timing range from DisplayID if available */</div><div class='add'>+		if (EDID_LENGTH - j &gt; 13 &amp;&amp; edid_ext[j] == 0x25	&amp;&amp;</div><div class='add'>+		    (edid_ext[j+1] &amp; 0xFE) == 0 &amp;&amp; (edid_ext[j+2] == 9)) {</div><div class='add'>+			min_vfreq = edid_ext[j+9];</div><div class='add'>+			if (edid_ext[j+1] &amp; 7)</div><div class='add'>+				max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] &amp; 3) &lt;&lt; 8);</div><div class='add'>+			else</div><div class='add'>+				max_vfreq = edid_ext[j+10];</div><div class='add'>+</div><div class='add'>+			if (max_vfreq &amp;&amp; min_vfreq) {</div><div class='add'>+				connector-&gt;display_info.monitor_range.max_vfreq = max_vfreq;</div><div class='add'>+				connector-&gt;display_info.monitor_range.min_vfreq = min_vfreq;</div><div class='add'>+</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		j++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,</div><div class='del'>-			  struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)</div><div class='add'>+			  const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)</div><div class='ctx'> {</div><div class='ctx'> 	u8 *edid_ext = NULL;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -11170,7 +13098,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	while (j &lt; EDID_LENGTH) {</div><div class='add'>+	while (j &lt; EDID_LENGTH - sizeof(struct amd_vsdb_block)) {</div><div class='ctx'> 		struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&amp;edid_ext[j];</div><div class='ctx'> 		unsigned int ieeeId = (amd_vsdb-&gt;ieee_id[2] &lt;&lt; 16) | (amd_vsdb-&gt;ieee_id[1] &lt;&lt; 8) | (amd_vsdb-&gt;ieee_id[0]);</div><div class='ctx'> </div><div class='hunk'>@@ -11189,7 +13117,8 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,</div><div class='del'>-		struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)</div><div class='add'>+			       const struct edid *edid,</div><div class='add'>+			       struct amdgpu_hdmi_vsdb_info *vsdb_info)</div><div class='ctx'> {</div><div class='ctx'> 	u8 *edid_ext = NULL;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -11223,7 +13152,7 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'>  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities</div><div class='ctx'>  *</div><div class='ctx'>  * @connector: Connector to query.</div><div class='del'>- * @edid: EDID from monitor</div><div class='add'>+ * @drm_edid: DRM EDID from monitor</div><div class='ctx'>  *</div><div class='ctx'>  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep</div><div class='ctx'>  * track of some of the display information in the internal data struct used by</div><div class='hunk'>@@ -11231,24 +13160,21 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'>  * FreeSync parameters.</div><div class='ctx'>  */</div><div class='ctx'> void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='del'>-				    struct edid *edid)</div><div class='add'>+				    const struct drm_edid *drm_edid)</div><div class='ctx'> {</div><div class='ctx'> 	int i = 0;</div><div class='del'>-	struct detailed_timing *timing;</div><div class='del'>-	struct detailed_non_pixel *data;</div><div class='del'>-	struct detailed_data_monitor_range *range;</div><div class='ctx'> 	struct amdgpu_dm_connector *amdgpu_dm_connector =</div><div class='ctx'> 			to_amdgpu_dm_connector(connector);</div><div class='ctx'> 	struct dm_connector_state *dm_con_state = NULL;</div><div class='ctx'> 	struct dc_sink *sink;</div><div class='del'>-</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(connector-&gt;dev);</div><div class='ctx'> 	struct amdgpu_hdmi_vsdb_info vsdb_info = {0};</div><div class='add'>+	const struct edid *edid;</div><div class='ctx'> 	bool freesync_capable = false;</div><div class='ctx'> 	enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;</div><div class='ctx'> </div><div class='ctx'> 	if (!connector-&gt;state) {</div><div class='del'>-		DRM_ERROR("%s - Connector has no state", __func__);</div><div class='add'>+		drm_err(adev_to_drm(adev), "%s - Connector has no state", __func__);</div><div class='ctx'> 		goto update;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -11256,14 +13182,13 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='ctx'> 		amdgpu_dm_connector-&gt;dc_sink :</div><div class='ctx'> 		amdgpu_dm_connector-&gt;dc_em_sink;</div><div class='ctx'> </div><div class='del'>-	if (!edid || !sink) {</div><div class='add'>+	drm_edid_connector_update(connector, drm_edid);</div><div class='add'>+</div><div class='add'>+	if (!drm_edid || !sink) {</div><div class='ctx'> 		dm_con_state = to_dm_connector_state(connector-&gt;state);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_connector-&gt;min_vfreq = 0;</div><div class='ctx'> 		amdgpu_dm_connector-&gt;max_vfreq = 0;</div><div class='del'>-		amdgpu_dm_connector-&gt;pixel_clock_mhz = 0;</div><div class='del'>-		connector-&gt;display_info.monitor_range.min_vfreq = 0;</div><div class='del'>-		connector-&gt;display_info.monitor_range.max_vfreq = 0;</div><div class='ctx'> 		freesync_capable = false;</div><div class='ctx'> </div><div class='ctx'> 		goto update;</div><div class='hunk'>@@ -11271,72 +13196,26 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='ctx'> </div><div class='ctx'> 	dm_con_state = to_dm_connector_state(connector-&gt;state);</div><div class='ctx'> </div><div class='del'>-	if (!adev-&gt;dm.freesync_module)</div><div class='add'>+	if (!adev-&gt;dm.freesync_module || !dc_supports_vrr(sink-&gt;ctx-&gt;dce_version))</div><div class='ctx'> 		goto update;</div><div class='ctx'> </div><div class='add'>+	edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()</div><div class='add'>+</div><div class='add'>+	/* Some eDP panels only have the refresh rate range info in DisplayID */</div><div class='add'>+	if ((connector-&gt;display_info.monitor_range.min_vfreq == 0 ||</div><div class='add'>+	     connector-&gt;display_info.monitor_range.max_vfreq == 0))</div><div class='add'>+		parse_edid_displayid_vrr(connector, edid);</div><div class='add'>+</div><div class='ctx'> 	if (edid &amp;&amp; (sink-&gt;sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||</div><div class='ctx'> 		     sink-&gt;sink_signal == SIGNAL_TYPE_EDP)) {</div><div class='del'>-		bool edid_check_required = false;</div><div class='del'>-</div><div class='del'>-		if (is_dp_capable_without_timing_msa(adev-&gt;dm.dc,</div><div class='del'>-						     amdgpu_dm_connector)) {</div><div class='del'>-			if (edid-&gt;features &amp; DRM_EDID_FEATURE_CONTINUOUS_FREQ) {</div><div class='add'>+		if (amdgpu_dm_connector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    amdgpu_dm_connector-&gt;dc_link-&gt;dpcd_caps.allow_invalid_MSA_timing_param) {</div><div class='add'>+			amdgpu_dm_connector-&gt;min_vfreq = connector-&gt;display_info.monitor_range.min_vfreq;</div><div class='add'>+			amdgpu_dm_connector-&gt;max_vfreq = connector-&gt;display_info.monitor_range.max_vfreq;</div><div class='add'>+			if (amdgpu_dm_connector-&gt;max_vfreq - amdgpu_dm_connector-&gt;min_vfreq &gt; 10)</div><div class='ctx'> 				freesync_capable = true;</div><div class='del'>-				amdgpu_dm_connector-&gt;min_vfreq = connector-&gt;display_info.monitor_range.min_vfreq;</div><div class='del'>-				amdgpu_dm_connector-&gt;max_vfreq = connector-&gt;display_info.monitor_range.max_vfreq;</div><div class='del'>-			} else {</div><div class='del'>-				edid_check_required = edid-&gt;version &gt; 1 ||</div><div class='del'>-						      (edid-&gt;version == 1 &amp;&amp;</div><div class='del'>-						       edid-&gt;revision &gt; 1);</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (edid_check_required) {</div><div class='del'>-			for (i = 0; i &lt; 4; i++) {</div><div class='del'>-</div><div class='del'>-				timing	= &amp;edid-&gt;detailed_timings[i];</div><div class='del'>-				data	= &amp;timing-&gt;data.other_data;</div><div class='del'>-				range	= &amp;data-&gt;data.range;</div><div class='del'>-				/*</div><div class='del'>-				 * Check if monitor has continuous frequency mode</div><div class='del'>-				 */</div><div class='del'>-				if (data-&gt;type != EDID_DETAIL_MONITOR_RANGE)</div><div class='del'>-					continue;</div><div class='del'>-				/*</div><div class='del'>-				 * Check for flag range limits only. If flag == 1 then</div><div class='del'>-				 * no additional timing information provided.</div><div class='del'>-				 * Default GTF, GTF Secondary curve and CVT are not</div><div class='del'>-				 * supported</div><div class='del'>-				 */</div><div class='del'>-				if (range-&gt;flags != 1)</div><div class='del'>-					continue;</div><div class='del'>-</div><div class='del'>-				connector-&gt;display_info.monitor_range.min_vfreq = range-&gt;min_vfreq;</div><div class='del'>-				connector-&gt;display_info.monitor_range.max_vfreq = range-&gt;max_vfreq;</div><div class='del'>-</div><div class='del'>-				if (edid-&gt;revision &gt;= 4) {</div><div class='del'>-					if (data-&gt;pad2 &amp; DRM_EDID_RANGE_OFFSET_MIN_VFREQ)</div><div class='del'>-						connector-&gt;display_info.monitor_range.min_vfreq += 255;</div><div class='del'>-					if (data-&gt;pad2 &amp; DRM_EDID_RANGE_OFFSET_MAX_VFREQ)</div><div class='del'>-						connector-&gt;display_info.monitor_range.max_vfreq += 255;</div><div class='del'>-				}</div><div class='del'>-</div><div class='del'>-				amdgpu_dm_connector-&gt;min_vfreq =</div><div class='del'>-					connector-&gt;display_info.monitor_range.min_vfreq;</div><div class='del'>-				amdgpu_dm_connector-&gt;max_vfreq =</div><div class='del'>-					connector-&gt;display_info.monitor_range.max_vfreq;</div><div class='del'>-				amdgpu_dm_connector-&gt;pixel_clock_mhz =</div><div class='del'>-					range-&gt;pixel_clock_mhz * 10;</div><div class='del'>-</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (amdgpu_dm_connector-&gt;max_vfreq -</div><div class='del'>-			    amdgpu_dm_connector-&gt;min_vfreq &gt; 10) {</div><div class='del'>-</div><div class='del'>-				freesync_capable = true;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='ctx'> 		parse_amd_vsdb(amdgpu_dm_connector, edid, &amp;vsdb_info);</div><div class='ctx'> </div><div class='ctx'> 		if (vsdb_info.replay_mode) {</div><div class='hunk'>@@ -11345,12 +13224,9 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='ctx'> 			amdgpu_dm_connector-&gt;as_type = ADAPTIVE_SYNC_TYPE_EDP;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-	} else if (edid &amp;&amp; sink-&gt;sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {</div><div class='add'>+	} else if (drm_edid &amp;&amp; sink-&gt;sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {</div><div class='ctx'> 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &amp;vsdb_info);</div><div class='ctx'> 		if (i &gt;= 0 &amp;&amp; vsdb_info.freesync_supported) {</div><div class='del'>-			timing  = &amp;edid-&gt;detailed_timings[i];</div><div class='del'>-			data    = &amp;timing-&gt;data.other_data;</div><div class='del'>-</div><div class='ctx'> 			amdgpu_dm_connector-&gt;min_vfreq = vsdb_info.min_refresh_rate_hz;</div><div class='ctx'> 			amdgpu_dm_connector-&gt;max_vfreq = vsdb_info.max_refresh_rate_hz;</div><div class='ctx'> 			if (amdgpu_dm_connector-&gt;max_vfreq - amdgpu_dm_connector-&gt;min_vfreq &gt; 10)</div><div class='hunk'>@@ -11361,7 +13237,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector-&gt;dc_link);</div><div class='add'>+	if (amdgpu_dm_connector-&gt;dc_link)</div><div class='add'>+		as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector-&gt;dc_link);</div><div class='ctx'> </div><div class='ctx'> 	if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {</div><div class='ctx'> 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &amp;vsdb_info);</div><div class='hunk'>@@ -11385,6 +13262,12 @@ update:</div><div class='ctx'> 	if (dm_con_state)</div><div class='ctx'> 		dm_con_state-&gt;freesync_capable = freesync_capable;</div><div class='ctx'> </div><div class='add'>+	if (connector-&gt;state &amp;&amp; amdgpu_dm_connector-&gt;dc_link &amp;&amp; !freesync_capable &amp;&amp;</div><div class='add'>+	    amdgpu_dm_connector-&gt;dc_link-&gt;replay_settings.config.replay_supported) {</div><div class='add'>+		amdgpu_dm_connector-&gt;dc_link-&gt;replay_settings.config.replay_supported = false;</div><div class='add'>+		amdgpu_dm_connector-&gt;dc_link-&gt;replay_settings.replay_feature_enabled = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (connector-&gt;vrr_capable_property)</div><div class='ctx'> 		drm_connector_set_vrr_capable_property(connector,</div><div class='ctx'> 						       freesync_capable);</div><div class='hunk'>@@ -11409,6 +13292,12 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	if (dc-&gt;ctx-&gt;dmub_srv &amp;&amp; !dc-&gt;ctx-&gt;dmub_srv-&gt;idle_exit_counter)</div><div class='add'>+		dc_exit_ips_for_hw_access(dc);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,</div><div class='ctx'> 		       u32 value, const char *func_name)</div><div class='ctx'> {</div><div class='hunk'>@@ -11419,6 +13308,8 @@ void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='add'>+</div><div class='add'>+	amdgpu_dm_exit_ips_for_hw_access(ctx-&gt;dc);</div><div class='ctx'> 	cgs_write_register(ctx-&gt;cgs_device, address, value);</div><div class='ctx'> 	trace_amdgpu_dc_wreg(&amp;ctx-&gt;perf_trace-&gt;write_count, address, value);</div><div class='ctx'> }</div><div class='hunk'>@@ -11442,6 +13333,8 @@ uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_dm_exit_ips_for_hw_access(ctx-&gt;dc);</div><div class='add'>+</div><div class='ctx'> 	value = cgs_read_register(ctx-&gt;cgs_device, address);</div><div class='ctx'> </div><div class='ctx'> 	trace_amdgpu_dc_rreg(&amp;ctx-&gt;perf_trace-&gt;read_count, address, value);</div><div class='hunk'>@@ -11466,7 +13359,7 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!wait_for_completion_timeout(&amp;adev-&gt;dm.dmub_aux_transfer_done, 10 * HZ)) {</div><div class='del'>-		DRM_ERROR("wait_for_completion_timeout timeout!");</div><div class='add'>+		drm_err(adev_to_drm(adev), "wait_for_completion_timeout timeout!");</div><div class='ctx'> 		*operation_result = AUX_RET_ERROR_TIMEOUT;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -11476,31 +13369,24 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(</div><div class='ctx'> 		 * Transient states before tunneling is enabled could</div><div class='ctx'> 		 * lead to this error. We can ignore this for now.</div><div class='ctx'> 		 */</div><div class='del'>-		if (p_notify-&gt;result != AUX_RET_ERROR_PROTOCOL_ERROR) {</div><div class='del'>-			DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",</div><div class='add'>+		if (p_notify-&gt;result == AUX_RET_ERROR_PROTOCOL_ERROR) {</div><div class='add'>+			drm_warn(adev_to_drm(adev), "DPIA AUX failed on 0x%x(%d), error %d\n",</div><div class='ctx'> 					payload-&gt;address, payload-&gt;length,</div><div class='ctx'> 					p_notify-&gt;result);</div><div class='ctx'> 		}</div><div class='del'>-		*operation_result = AUX_RET_ERROR_INVALID_REPLY;</div><div class='add'>+		*operation_result = p_notify-&gt;result;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	payload-&gt;reply[0] = adev-&gt;dm.dmub_notify-&gt;aux_reply.command &amp; 0xF;</div><div class='add'>+	if (adev-&gt;dm.dmub_notify-&gt;aux_reply.command &amp; 0xF0)</div><div class='add'>+		/* The reply is stored in the top nibble of the command. */</div><div class='add'>+		payload-&gt;reply[0] = (adev-&gt;dm.dmub_notify-&gt;aux_reply.command &gt;&gt; 4) &amp; 0xF;</div><div class='ctx'> </div><div class='del'>-	payload-&gt;reply[0] = adev-&gt;dm.dmub_notify-&gt;aux_reply.command;</div><div class='del'>-	if (!payload-&gt;write &amp;&amp; p_notify-&gt;aux_reply.length &amp;&amp;</div><div class='del'>-			(payload-&gt;reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {</div><div class='del'>-</div><div class='del'>-		if (payload-&gt;length != p_notify-&gt;aux_reply.length) {</div><div class='del'>-			DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",</div><div class='del'>-				p_notify-&gt;aux_reply.length,</div><div class='del'>-					payload-&gt;address, payload-&gt;length);</div><div class='del'>-			*operation_result = AUX_RET_ERROR_INVALID_REPLY;</div><div class='del'>-			goto out;</div><div class='del'>-		}</div><div class='del'>-</div><div class='add'>+	/*write req may receive a byte indicating partially written number as well*/</div><div class='add'>+	if (p_notify-&gt;aux_reply.length)</div><div class='ctx'> 		memcpy(payload-&gt;data, p_notify-&gt;aux_reply.data,</div><div class='ctx'> 				p_notify-&gt;aux_reply.length);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/* success */</div><div class='ctx'> 	ret = p_notify-&gt;aux_reply.length;</div><div class='hunk'>@@ -11511,6 +13397,79 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void abort_fused_io(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		const struct dmub_cmd_fused_request *request</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd command = { 0 };</div><div class='add'>+	struct dmub_rb_cmd_fused_io *io = &amp;command.fused_io;</div><div class='add'>+</div><div class='add'>+	io-&gt;header.type = DMUB_CMD__FUSED_IO;</div><div class='add'>+	io-&gt;header.sub_type = DMUB_CMD__FUSED_IO_ABORT;</div><div class='add'>+	io-&gt;header.payload_bytes = sizeof(*io) - sizeof(io-&gt;header);</div><div class='add'>+	io-&gt;request = *request;</div><div class='add'>+	dm_execute_dmub_cmd(ctx, &amp;command, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool execute_fused_io(</div><div class='add'>+		struct amdgpu_device *dev,</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		union dmub_rb_cmd *commands,</div><div class='add'>+		uint8_t count,</div><div class='add'>+		uint32_t timeout_us</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	const uint8_t ddc_line = commands[0].fused_io.request.u.aux.ddc_line;</div><div class='add'>+</div><div class='add'>+	if (ddc_line &gt;= ARRAY_SIZE(dev-&gt;dm.fused_io))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	struct fused_io_sync *sync = &amp;dev-&gt;dm.fused_io[ddc_line];</div><div class='add'>+	struct dmub_rb_cmd_fused_io *first = &amp;commands[0].fused_io;</div><div class='add'>+	const bool result = dm_execute_dmub_cmd_list(ctx, count, commands, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)</div><div class='add'>+			&amp;&amp; first-&gt;header.ret_status</div><div class='add'>+			&amp;&amp; first-&gt;request.status == FUSED_REQUEST_STATUS_SUCCESS;</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	while (wait_for_completion_timeout(&amp;sync-&gt;replied, usecs_to_jiffies(timeout_us))) {</div><div class='add'>+		reinit_completion(&amp;sync-&gt;replied);</div><div class='add'>+</div><div class='add'>+		struct dmub_cmd_fused_request *reply = (struct dmub_cmd_fused_request *) sync-&gt;reply_data;</div><div class='add'>+</div><div class='add'>+		static_assert(sizeof(*reply) &lt;= sizeof(sync-&gt;reply_data), "Size mismatch");</div><div class='add'>+</div><div class='add'>+		if (reply-&gt;identifier == first-&gt;request.identifier) {</div><div class='add'>+			first-&gt;request = *reply;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reinit_completion(&amp;sync-&gt;replied);</div><div class='add'>+	first-&gt;request.status = FUSED_REQUEST_STATUS_TIMEOUT;</div><div class='add'>+	abort_fused_io(ctx, &amp;first-&gt;request);</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_dm_execute_fused_io(</div><div class='add'>+		struct amdgpu_device *dev,</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		union dmub_rb_cmd *commands,</div><div class='add'>+		uint8_t count,</div><div class='add'>+		uint32_t timeout_us)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_display_manager *dm = &amp;dev-&gt;dm;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;dm-&gt;dpia_aux_lock);</div><div class='add'>+</div><div class='add'>+	const bool result = execute_fused_io(dev, link-&gt;ctx, commands, count, timeout_us);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;dm-&gt;dpia_aux_lock);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_dm_process_dmub_set_config_sync(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		unsigned int link_index,</div><div class='hunk'>@@ -11529,7 +13488,7 @@ int amdgpu_dm_process_dmub_set_config_sync(</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 		*operation_result = adev-&gt;dm.dmub_notify-&gt;sc_status;</div><div class='ctx'> 	} else {</div><div class='del'>-		DRM_ERROR("wait_for_completion_timeout timeout!");</div><div class='add'>+		drm_err(adev_to_drm(adev), "wait_for_completion_timeout timeout!");</div><div class='ctx'> 		ret = -1;</div><div class='ctx'> 		*operation_result = SET_CONFIG_UNKNOWN_ERROR;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -11549,3 +13508,10 @@ bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,</div><div class='ctx'> {</div><div class='ctx'> 	return dc_dmub_srv_cmd_run_list(ctx-&gt;dmub_srv, count, cmd, wait_type);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dm_acpi_process_phy_transition_interlock(</div><div class='add'>+	const struct dc_context *ctx,</div><div class='add'>+	struct dm_process_phy_transition_init_params process_phy_transition_init_params)</div><div class='add'>+{</div><div class='add'>+	// Not yet implemented</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h<br/>index 09519b7abf67..ef97cede9926 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'>  *</div><div class='hunk'>@@ -50,7 +51,7 @@</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_DM_MAX_NUM_EDP 2</div><div class='ctx'> </div><div class='del'>-#define AMDGPU_DMUB_NOTIFICATION_MAX 5</div><div class='add'>+#define AMDGPU_DMUB_NOTIFICATION_MAX 8</div><div class='ctx'> </div><div class='ctx'> #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A</div><div class='ctx'> #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40</div><div class='hunk'>@@ -58,6 +59,7 @@</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS 1500</div><div class='ctx'> /*</div><div class='ctx'> #include "include/amdgpu_dal_power_if.h"</div><div class='ctx'> #include "amdgpu_dm_irq.h"</div><div class='hunk'>@@ -81,6 +83,7 @@ struct amdgpu_bo;</div><div class='ctx'> struct dmub_srv;</div><div class='ctx'> struct dc_plane_state;</div><div class='ctx'> struct dmub_notification;</div><div class='add'>+struct dmub_cmd_fused_request;</div><div class='ctx'> </div><div class='ctx'> struct amd_vsdb_block {</div><div class='ctx'> 	unsigned char ieee_id[3];</div><div class='hunk'>@@ -138,6 +141,46 @@ struct vblank_control_work {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * struct idle_workqueue - Work data for periodic action in idle</div><div class='add'>+ * @work: Kernel work data for the work event</div><div class='add'>+ * @dm: amdgpu display manager device</div><div class='add'>+ * @enable: true if idle worker is enabled</div><div class='add'>+ * @running: true if idle worker is running</div><div class='add'>+ */</div><div class='add'>+struct idle_workqueue {</div><div class='add'>+	struct work_struct work;</div><div class='add'>+	struct amdgpu_display_manager *dm;</div><div class='add'>+	bool enable;</div><div class='add'>+	bool running;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct vupdate_offload_work - Work data for offloading task from vupdate handler</div><div class='add'>+ * @work: Kernel work data for the work event</div><div class='add'>+ * @adev: amdgpu_device back pointer</div><div class='add'>+ * @stream: DC stream associated with the crtc</div><div class='add'>+ * @adjust: DC CRTC timing adjust to be applied to the crtc</div><div class='add'>+ */</div><div class='add'>+struct vupdate_offload_work {</div><div class='add'>+	struct work_struct work;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	struct dc_stream_state *stream;</div><div class='add'>+	struct dc_crtc_timing_adjust *adjust;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_LUMINANCE_DATA_POINTS 99</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct amdgpu_dm_luminance_data - Custom luminance data</div><div class='add'>+ * @luminance: Luminance in percent</div><div class='add'>+ * @input_signal: Input signal in range 0-255</div><div class='add'>+ */</div><div class='add'>+struct amdgpu_dm_luminance_data {</div><div class='add'>+	u8 luminance;</div><div class='add'>+	u8 input_signal;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * struct amdgpu_dm_backlight_caps - Information about backlight</div><div class='ctx'>  *</div><div class='ctx'>  * Describe the backlight support for ACPI or eDP AUX.</div><div class='hunk'>@@ -173,6 +216,27 @@ struct amdgpu_dm_backlight_caps {</div><div class='ctx'> 	 * @aux_support: Describes if the display supports AUX backlight.</div><div class='ctx'> 	 */</div><div class='ctx'> 	bool aux_support;</div><div class='add'>+	/**</div><div class='add'>+	 * @brightness_mask: After deriving brightness, OR it with this mask.</div><div class='add'>+	 * Workaround for panels with issues with certain brightness values.</div><div class='add'>+	 */</div><div class='add'>+	u32 brightness_mask;</div><div class='add'>+	/**</div><div class='add'>+	 * @ac_level: the default brightness if booted on AC</div><div class='add'>+	 */</div><div class='add'>+	u8 ac_level;</div><div class='add'>+	/**</div><div class='add'>+	 * @dc_level: the default brightness if booted on DC</div><div class='add'>+	 */</div><div class='add'>+	u8 dc_level;</div><div class='add'>+	/**</div><div class='add'>+	 * @data_points: the number of custom luminance data points</div><div class='add'>+	 */</div><div class='add'>+	u8 data_points;</div><div class='add'>+	/**</div><div class='add'>+	 * @luminance_data: custom luminance data</div><div class='add'>+	 */</div><div class='add'>+	struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -234,6 +298,10 @@ struct hpd_rx_irq_offload_work {</div><div class='ctx'> 	 * @offload_wq: offload work queue that this work is queued to</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct hpd_rx_irq_offload_work_queue *offload_wq;</div><div class='add'>+	/**</div><div class='add'>+	 * @adev: amdgpu_device pointer</div><div class='add'>+	 */</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -488,6 +556,13 @@ struct amdgpu_display_manager {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct workqueue_struct *vblank_control_workqueue;</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	 * @idle_workqueue:</div><div class='add'>+	 *</div><div class='add'>+	 * Periodic work for idle events.</div><div class='add'>+	 */</div><div class='add'>+	struct idle_workqueue *idle_workqueue;</div><div class='add'>+</div><div class='ctx'> 	struct drm_atomic_state *cached_state;</div><div class='ctx'> 	struct dc_state *cached_dc_state;</div><div class='ctx'> </div><div class='hunk'>@@ -512,12 +587,12 @@ struct amdgpu_display_manager {</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='ctx'> 	/**</div><div class='del'>-	 * @secure_display_ctxs:</div><div class='add'>+	 * @secure_display_ctx:</div><div class='ctx'> 	 *</div><div class='del'>-	 * Store the ROI information and the work_struct to command dmub and psp for</div><div class='del'>-	 * all crtcs.</div><div class='add'>+	 * Store secure display relevant info. e.g. the ROI information</div><div class='add'>+	 * , the work_struct to command dmub, etc.</div><div class='ctx'> 	 */</div><div class='del'>-	struct secure_display_context *secure_display_ctxs;</div><div class='add'>+	struct secure_display_context secure_display_ctx;</div><div class='ctx'> #endif</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * @hpd_rx_offload_wq:</div><div class='hunk'>@@ -565,11 +640,43 @@ struct amdgpu_display_manager {</div><div class='ctx'> 	bool aux_hpd_discon_quirk;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * @edp0_on_dp1_quirk:</div><div class='add'>+	 *</div><div class='add'>+	 * quirk for platforms that put edp0 on DP1.</div><div class='add'>+	 */</div><div class='add'>+	bool edp0_on_dp1_quirk;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * @dpia_aux_lock:</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * Guards access to DPIA AUX</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct mutex dpia_aux_lock;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @bb_from_dmub:</div><div class='add'>+	 *</div><div class='add'>+	 * Bounding box data read from dmub during early initialization for DCN4+</div><div class='add'>+	 * Data is stored as a byte array that should be casted to the appropriate bb struct</div><div class='add'>+	 */</div><div class='add'>+	void *bb_from_dmub;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @oem_i2c:</div><div class='add'>+	 *</div><div class='add'>+	 * OEM i2c bus</div><div class='add'>+	 */</div><div class='add'>+	struct amdgpu_i2c_adapter *oem_i2c;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @fused_io:</div><div class='add'>+	 *</div><div class='add'>+	 * dmub fused io interface</div><div class='add'>+	 */</div><div class='add'>+	struct fused_io_sync {</div><div class='add'>+		struct completion replied;</div><div class='add'>+		char reply_data[0x40];  // Cannot include dmub_cmd here</div><div class='add'>+	} fused_io[8];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum dsc_clock_force_state {</div><div class='hunk'>@@ -635,9 +742,11 @@ struct amdgpu_dm_connector {</div><div class='ctx'> 	uint32_t connector_id;</div><div class='ctx'> 	int bl_idx;</div><div class='ctx'> </div><div class='add'>+	struct cec_notifier *notifier;</div><div class='add'>+</div><div class='ctx'> 	/* we need to mind the EDID between detect</div><div class='ctx'> 	   and get modes due to analog/digital/tvencoder */</div><div class='del'>-	struct edid *edid;</div><div class='add'>+	const struct drm_edid *drm_edid;</div><div class='ctx'> </div><div class='ctx'> 	/* shared with amdgpu */</div><div class='ctx'> 	struct amdgpu_hpd hpd;</div><div class='hunk'>@@ -661,8 +770,13 @@ struct amdgpu_dm_connector {</div><div class='ctx'> 	struct drm_dp_mst_port *mst_output_port;</div><div class='ctx'> 	struct amdgpu_dm_connector *mst_root;</div><div class='ctx'> 	struct drm_dp_aux *dsc_aux;</div><div class='add'>+	uint32_t mst_local_bw;</div><div class='add'>+	uint16_t vc_full_pbn;</div><div class='ctx'> 	struct mutex handle_mst_msg_ready;</div><div class='ctx'> </div><div class='add'>+	/* branch device specific data */</div><div class='add'>+	uint32_t branch_ieee_oui;</div><div class='add'>+</div><div class='ctx'> 	/* TODO see if we can merge with ddc_bus or make a dm_connector */</div><div class='ctx'> 	struct amdgpu_i2c_adapter *i2c;</div><div class='ctx'> </div><div class='hunk'>@@ -678,7 +792,6 @@ struct amdgpu_dm_connector {</div><div class='ctx'> 	 * value is set to zero when there is no FreeSync support.</div><div class='ctx'> 	 */</div><div class='ctx'> 	int max_vfreq ;</div><div class='del'>-	int pixel_clock_mhz;</div><div class='ctx'> </div><div class='ctx'> 	/* Audio instance - protected by audio_lock. */</div><div class='ctx'> 	int audio_inst;</div><div class='hunk'>@@ -687,12 +800,13 @@ struct amdgpu_dm_connector {</div><div class='ctx'> </div><div class='ctx'> 	bool fake_enable;</div><div class='ctx'> 	bool force_yuv420_output;</div><div class='add'>+	bool force_yuv422_output;</div><div class='ctx'> 	struct dsc_preferred_settings dsc_settings;</div><div class='ctx'> 	union dp_downstream_port_present mst_downstream_port_present;</div><div class='ctx'> 	/* Cached display modes */</div><div class='ctx'> 	struct drm_display_mode freesync_vid_base;</div><div class='ctx'> </div><div class='del'>-	int psr_skip_count;</div><div class='add'>+	int sr_skip_count;</div><div class='ctx'> 	bool disallow_edp_enter_psr;</div><div class='ctx'> </div><div class='ctx'> 	/* Record progress status of mst*/</div><div class='hunk'>@@ -706,6 +820,11 @@ struct amdgpu_dm_connector {</div><div class='ctx'> 	bool pack_sdp_v1_3;</div><div class='ctx'> 	enum adaptive_sync_type as_type;</div><div class='ctx'> 	struct amdgpu_hdmi_vsdb_info vsdb_info;</div><div class='add'>+</div><div class='add'>+	/* HDMI HPD debounce support */</div><div class='add'>+	unsigned int hdmi_hpd_debounce_delay_ms;</div><div class='add'>+	struct delayed_work hdmi_hpd_debounce_work;</div><div class='add'>+	struct dc_sink *hdmi_prev_sink;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline void amdgpu_dm_set_mst_status(uint8_t *status,</div><div class='hunk'>@@ -822,6 +941,11 @@ struct dm_plane_state {</div><div class='ctx'> 	enum amdgpu_transfer_function blend_tf;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum amdgpu_dm_cursor_mode {</div><div class='add'>+	DM_CURSOR_NATIVE_MODE = 0,</div><div class='add'>+	DM_CURSOR_OVERLAY_MODE,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dm_crtc_state {</div><div class='ctx'> 	struct drm_crtc_state base;</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='hunk'>@@ -852,6 +976,8 @@ struct dm_crtc_state {</div><div class='ctx'> 	 * encoding.</div><div class='ctx'> 	 */</div><div class='ctx'> 	enum amdgpu_transfer_function regamma_tf;</div><div class='add'>+</div><div class='add'>+	enum amdgpu_dm_cursor_mode cursor_mode;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)</div><div class='hunk'>@@ -873,6 +999,7 @@ struct dm_connector_state {</div><div class='ctx'> 	bool underscan_enable;</div><div class='ctx'> 	bool freesync_capable;</div><div class='ctx'> 	bool update_hdcp;</div><div class='add'>+	bool abm_sysfs_forbidden;</div><div class='ctx'> 	uint8_t abm_level;</div><div class='ctx'> 	int vcpi_slots;</div><div class='ctx'> 	uint64_t pbn;</div><div class='hunk'>@@ -903,13 +1030,13 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,</div><div class='ctx'> 				     int link_index);</div><div class='ctx'> </div><div class='ctx'> enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,</div><div class='del'>-				   struct drm_display_mode *mode);</div><div class='add'>+				   const struct drm_display_mode *mode);</div><div class='ctx'> </div><div class='ctx'> void dm_restore_drm_connector_state(struct drm_device *dev,</div><div class='ctx'> 				    struct drm_connector *connector);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='del'>-					struct edid *edid);</div><div class='add'>+				    const struct drm_edid *drm_edid);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);</div><div class='ctx'> </div><div class='hunk'>@@ -927,6 +1054,8 @@ void amdgpu_dm_init_color_mod(void);</div><div class='ctx'> int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);</div><div class='ctx'> int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);</div><div class='add'>+int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc,</div><div class='add'>+				    bool check_only);</div><div class='ctx'> int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='ctx'> 				      struct drm_plane_state *plane_state,</div><div class='ctx'> 				      struct dc_plane_state *dc_plane_state);</div><div class='hunk'>@@ -939,11 +1068,19 @@ extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;</div><div class='ctx'> int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,</div><div class='ctx'> 					struct aux_payload *payload, enum aux_return_code_type *operation_result);</div><div class='ctx'> </div><div class='add'>+bool amdgpu_dm_execute_fused_io(</div><div class='add'>+		struct amdgpu_device *dev,</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		union dmub_rb_cmd *commands,</div><div class='add'>+		uint8_t count,</div><div class='add'>+		uint32_t timeout_us</div><div class='add'>+);</div><div class='add'>+</div><div class='ctx'> int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,</div><div class='ctx'> 					struct set_config_cmd_payload *payload, enum set_config_status *operation_result);</div><div class='ctx'> </div><div class='ctx'> struct dc_stream_state *</div><div class='del'>-	create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='add'>+	create_validate_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 					const struct drm_display_mode *drm_mode,</div><div class='ctx'> 					const struct dm_connector_state *dm_state,</div><div class='ctx'> 					const struct dc_stream_state *old_stream);</div><div class='hunk'>@@ -956,4 +1093,22 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,</div><div class='ctx'> 					     struct drm_crtc *crtc);</div><div class='ctx'> </div><div class='ctx'> int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);</div><div class='add'>+struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+void *dm_allocate_gpu_mem(struct amdgpu_device *adev,</div><div class='add'>+						  enum dc_gpu_mem_alloc_type type,</div><div class='add'>+						  size_t size,</div><div class='add'>+						  long long *addr);</div><div class='add'>+void dm_free_gpu_mem(struct amdgpu_device *adev,</div><div class='add'>+						  enum dc_gpu_mem_alloc_type type,</div><div class='add'>+						  void *addr);</div><div class='add'>+</div><div class='add'>+bool amdgpu_dm_is_headless(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector);</div><div class='add'>+void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector);</div><div class='add'>+int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector);</div><div class='add'>+</div><div class='add'>+void retrieve_dmi_info(struct amdgpu_display_manager *dm);</div><div class='add'>+</div><div class='ctx'> #endif /* __AMDGPU_DM_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c<br/>index c87b64e464ed..1dcc79b35225 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -25,13 +26,39 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_mode.h"</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='add'>+#include "amdgpu_dm_colorop.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "modules/color/color_gamma.h"</div><div class='del'>-#include "basics/conversion.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: overview</div><div class='ctx'>  *</div><div class='add'>+ * We have three types of color management in the AMD display driver.</div><div class='add'>+ * 1. the legacy &amp;drm_crtc DEGAMMA, CTM, and GAMMA properties</div><div class='add'>+ * 2. AMD driver private color management on &amp;drm_plane and &amp;drm_crtc</div><div class='add'>+ * 3. AMD plane color pipeline</div><div class='add'>+ *</div><div class='add'>+ * The CRTC properties are the original color management. When they were</div><div class='add'>+ * implemented per-plane color management was not a thing yet. Because</div><div class='add'>+ * of that we could get away with plumbing the DEGAMMA and CTM</div><div class='add'>+ * properties to pre-blending HW functions. This is incompatible with</div><div class='add'>+ * per-plane color management, such as via the AMD private properties or</div><div class='add'>+ * the new drm_plane color pipeline. The only compatible CRTC property</div><div class='add'>+ * with per-plane color management is the GAMMA property as it is</div><div class='add'>+ * applied post-blending.</div><div class='add'>+ *</div><div class='add'>+ * The AMD driver private color management properties are only exposed</div><div class='add'>+ * when the kernel is built explicitly with -DAMD_PRIVATE_COLOR. They</div><div class='add'>+ * are temporary building blocks on the path to full-fledged &amp;drm_plane</div><div class='add'>+ * and &amp;drm_crtc color pipelines and lay the driver's groundwork for the</div><div class='add'>+ * color pipelines.</div><div class='add'>+ *</div><div class='add'>+ * The AMD plane color pipeline describes AMD's &amp;drm_colorops via the</div><div class='add'>+ * &amp;drm_plane's COLOR_PIPELINE property.</div><div class='add'>+ *</div><div class='add'>+ * drm_crtc Properties</div><div class='add'>+ * -------------------</div><div class='add'>+ *</div><div class='ctx'>  * The DC interface to HW gives us the following color management blocks</div><div class='ctx'>  * per pipe (surface):</div><div class='ctx'>  *</div><div class='hunk'>@@ -42,36 +69,93 @@</div><div class='ctx'>  * - Surface regamma LUT (normalized)</div><div class='ctx'>  * - Output CSC (normalized)</div><div class='ctx'>  *</div><div class='del'>- * But these aren't a direct mapping to DRM color properties. The current DRM</div><div class='del'>- * interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware</div><div class='del'>- * is essentially giving:</div><div class='add'>+ * But these aren't a direct mapping to DRM color properties. The</div><div class='add'>+ * current DRM interface exposes CRTC degamma, CRTC CTM and CRTC regamma</div><div class='add'>+ * while our hardware is essentially giving:</div><div class='ctx'>  *</div><div class='ctx'>  * Plane CTM -&gt; Plane degamma -&gt; Plane CTM -&gt; Plane regamma -&gt; Plane CTM</div><div class='ctx'>  *</div><div class='del'>- * The input gamma LUT block isn't really applicable here since it operates</div><div class='del'>- * on the actual input data itself rather than the HW fp representation. The</div><div class='del'>- * input and output CSC blocks are technically available to use as part of</div><div class='del'>- * the DC interface but are typically used internally by DC for conversions</div><div class='del'>- * between color spaces. These could be blended together with user</div><div class='del'>- * adjustments in the future but for now these should remain untouched.</div><div class='add'>+ * The input gamma LUT block isn't really applicable here since it</div><div class='add'>+ * operates on the actual input data itself rather than the HW fp</div><div class='add'>+ * representation. The input and output CSC blocks are technically</div><div class='add'>+ * available to use as part of the DC interface but are typically used</div><div class='add'>+ * internally by DC for conversions between color spaces. These could be</div><div class='add'>+ * blended together with user adjustments in the future but for now</div><div class='add'>+ * these should remain untouched.</div><div class='add'>+ *</div><div class='add'>+ * The pipe blending also happens after these blocks so we don't</div><div class='add'>+ * actually support any CRTC props with correct blending with multiple</div><div class='add'>+ * planes - but we can still support CRTC color management properties in</div><div class='add'>+ * DM in most single plane cases correctly with clever management of the</div><div class='add'>+ * DC interface in DM.</div><div class='add'>+ *</div><div class='add'>+ * As per DRM documentation, blocks should be in hardware bypass when</div><div class='add'>+ * their respective property is set to NULL. A linear DGM/RGM LUT should</div><div class='add'>+ * also considered as putting the respective block into bypass mode.</div><div class='add'>+ *</div><div class='add'>+ * This means that the following configuration is assumed to be the</div><div class='add'>+ * default:</div><div class='add'>+ *</div><div class='add'>+ * Plane DGM Bypass -&gt; Plane CTM Bypass -&gt; Plane RGM Bypass -&gt; ... CRTC</div><div class='add'>+ * DGM Bypass -&gt; CRTC CTM Bypass -&gt; CRTC RGM Bypass</div><div class='add'>+ *</div><div class='add'>+ * AMD Private Color Management on drm_plane</div><div class='add'>+ * -----------------------------------------</div><div class='add'>+ *</div><div class='add'>+ * The AMD private color management properties on a &amp;drm_plane are:</div><div class='add'>+ *</div><div class='add'>+ * - AMD_PLANE_DEGAMMA_LUT</div><div class='add'>+ * - AMD_PLANE_DEGAMMA_LUT_SIZE</div><div class='add'>+ * - AMD_PLANE_DEGAMMA_TF</div><div class='add'>+ * - AMD_PLANE_HDR_MULT</div><div class='add'>+ * - AMD_PLANE_CTM</div><div class='add'>+ * - AMD_PLANE_SHAPER_LUT</div><div class='add'>+ * - AMD_PLANE_SHAPER_LUT_SIZE</div><div class='add'>+ * - AMD_PLANE_SHAPER_TF</div><div class='add'>+ * - AMD_PLANE_LUT3D</div><div class='add'>+ * - AMD_PLANE_LUT3D_SIZE</div><div class='add'>+ * - AMD_PLANE_BLEND_LUT</div><div class='add'>+ * - AMD_PLANE_BLEND_LUT_SIZE</div><div class='add'>+ * - AMD_PLANE_BLEND_TF</div><div class='add'>+ *</div><div class='add'>+ * The AMD private color management property on a &amp;drm_crtc is:</div><div class='ctx'>  *</div><div class='del'>- * The pipe blending also happens after these blocks so we don't actually</div><div class='del'>- * support any CRTC props with correct blending with multiple planes - but we</div><div class='del'>- * can still support CRTC color management properties in DM in most single</div><div class='del'>- * plane cases correctly with clever management of the DC interface in DM.</div><div class='add'>+ * - AMD_CRTC_REGAMMA_TF</div><div class='ctx'>  *</div><div class='del'>- * As per DRM documentation, blocks should be in hardware bypass when their</div><div class='del'>- * respective property is set to NULL. A linear DGM/RGM LUT should also</div><div class='del'>- * considered as putting the respective block into bypass mode.</div><div class='add'>+ * Use of these properties is discouraged.</div><div class='ctx'>  *</div><div class='del'>- * This means that the following</div><div class='del'>- * configuration is assumed to be the default:</div><div class='add'>+ * AMD plane color pipeline</div><div class='add'>+ * ------------------------</div><div class='add'>+ *</div><div class='add'>+ * The AMD &amp;drm_plane color pipeline is advertised for DCN generations</div><div class='add'>+ * 3.0 and newer. It exposes these elements in this order:</div><div class='add'>+ *</div><div class='add'>+ * 1. 1D curve colorop</div><div class='add'>+ * 2. Multiplier</div><div class='add'>+ * 3. 3x4 CTM</div><div class='add'>+ * 4. 1D curve colorop</div><div class='add'>+ * 5. 1D LUT</div><div class='add'>+ * 6. 3D LUT</div><div class='add'>+ * 7. 1D curve colorop</div><div class='add'>+ * 8. 1D LUT</div><div class='add'>+ *</div><div class='add'>+ * The multiplier (#2) is a simple multiplier that is applied to all</div><div class='add'>+ * channels.</div><div class='add'>+ *</div><div class='add'>+ * The 3x4 CTM (#3) is a simple 3x4 matrix.</div><div class='add'>+ *</div><div class='add'>+ * #1, and #7 are non-linear to linear curves. #4 is a linear to</div><div class='add'>+ * non-linear curve. They support sRGB, PQ, and BT.709/BT.2020 EOTFs or</div><div class='add'>+ * their inverse.</div><div class='add'>+ *</div><div class='add'>+ * The 1D LUTs (#5 and #8) are plain 4096 entry LUTs.</div><div class='add'>+ *</div><div class='add'>+ * The 3DLUT (#6) is a tetrahedrally interpolated 17 cube LUT.</div><div class='ctx'>  *</div><div class='del'>- * Plane DGM Bypass -&gt; Plane CTM Bypass -&gt; Plane RGM Bypass -&gt; ...</div><div class='del'>- * CRTC DGM Bypass -&gt; CRTC CTM Bypass -&gt; CRTC RGM Bypass</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #define MAX_DRM_LUT_VALUE 0xFFFF</div><div class='add'>+#define MAX_DRM_LUT32_VALUE 0xFFFFFFFF</div><div class='ctx'> #define SDR_WHITE_LEVEL_INIT_VALUE 80</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -342,6 +426,21 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * __extract_blob_lut32 - Extracts the DRM lut and lut size from a blob.</div><div class='add'>+ * @blob: DRM color mgmt property blob</div><div class='add'>+ * @size: lut size</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * DRM LUT or NULL</div><div class='add'>+ */</div><div class='add'>+static const struct drm_color_lut32 *</div><div class='add'>+__extract_blob_lut32(const struct drm_property_blob *blob, uint32_t *size)</div><div class='add'>+{</div><div class='add'>+	*size = blob ? drm_color_lut32_size(blob) : 0;</div><div class='add'>+	return blob ? (struct drm_color_lut32 *)blob-&gt;data : NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * __is_lut_linear - check if the given lut is a linear mapping of values</div><div class='ctx'>  * @lut: given lut to check values</div><div class='ctx'>  * @size: lut size</div><div class='hunk'>@@ -415,6 +514,24 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * __drm_lut32_to_dc_gamma - convert the drm_color_lut to dc_gamma.</div><div class='add'>+ * @lut: DRM lookup table for color conversion</div><div class='add'>+ * @gamma: DC gamma to set entries</div><div class='add'>+ *</div><div class='add'>+ * The conversion depends on the size of the lut - whether or not it's legacy.</div><div class='add'>+ */</div><div class='add'>+static void __drm_lut32_to_dc_gamma(const struct drm_color_lut32 *lut, struct dc_gamma *gamma)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_COLOR_LUT_ENTRIES; i++) {</div><div class='add'>+		gamma-&gt;entries.red[i] = dc_fixpt_from_fraction(lut[i].red, MAX_DRM_LUT32_VALUE);</div><div class='add'>+		gamma-&gt;entries.green[i] = dc_fixpt_from_fraction(lut[i].green, MAX_DRM_LUT32_VALUE);</div><div class='add'>+		gamma-&gt;entries.blue[i] = dc_fixpt_from_fraction(lut[i].blue, MAX_DRM_LUT32_VALUE);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix</div><div class='ctx'>  * @ctm: DRM color transformation matrix</div><div class='ctx'>  * @matrix: DC CSC float matrix</div><div class='hunk'>@@ -566,12 +683,68 @@ static int __set_output_tf(struct dc_transfer_func *func,</div><div class='ctx'> 	return res ? 0 : -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream,</div><div class='add'>+/**</div><div class='add'>+ * __set_output_tf_32 - calculates the output transfer function based on expected input space.</div><div class='add'>+ * @func: transfer function</div><div class='add'>+ * @lut: lookup table that defines the color space</div><div class='add'>+ * @lut_size: size of respective lut</div><div class='add'>+ * @has_rom: if ROM can be used for hardcoded curve</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 in case of success. -ENOMEM if fails.</div><div class='add'>+ */</div><div class='add'>+static int __set_output_tf_32(struct dc_transfer_func *func,</div><div class='add'>+			      const struct drm_color_lut32 *lut, uint32_t lut_size,</div><div class='add'>+			      bool has_rom)</div><div class='add'>+{</div><div class='add'>+	struct dc_gamma *gamma = NULL;</div><div class='add'>+	struct calculate_buffer cal_buffer = {0};</div><div class='add'>+	bool res;</div><div class='add'>+</div><div class='add'>+	cal_buffer.buffer_index = -1;</div><div class='add'>+</div><div class='add'>+	if (lut_size) {</div><div class='add'>+		gamma = dc_create_gamma();</div><div class='add'>+		if (!gamma)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		gamma-&gt;num_entries = lut_size;</div><div class='add'>+		__drm_lut32_to_dc_gamma(lut, gamma);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (func-&gt;tf == TRANSFER_FUNCTION_LINEAR) {</div><div class='add'>+		/*</div><div class='add'>+		 * Color module doesn't like calculating regamma params</div><div class='add'>+		 * on top of a linear input. But degamma params can be used</div><div class='add'>+		 * instead to simulate this.</div><div class='add'>+		 */</div><div class='add'>+		if (gamma)</div><div class='add'>+			gamma-&gt;type = GAMMA_CUSTOM;</div><div class='add'>+		res = mod_color_calculate_degamma_params(NULL, func,</div><div class='add'>+							 gamma, gamma != NULL);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * Assume sRGB. The actual mapping will depend on whether the</div><div class='add'>+		 * input was legacy or not.</div><div class='add'>+		 */</div><div class='add'>+		if (gamma)</div><div class='add'>+			gamma-&gt;type = GAMMA_CS_TFM_1D;</div><div class='add'>+		res = mod_color_calculate_regamma_params(func, gamma, gamma != NULL,</div><div class='add'>+							 has_rom, NULL, &amp;cal_buffer);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gamma)</div><div class='add'>+		dc_gamma_release(&amp;gamma);</div><div class='add'>+</div><div class='add'>+	return res ? 0 : -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_set_atomic_regamma(struct dc_transfer_func *out_tf,</div><div class='ctx'> 					const struct drm_color_lut *regamma_lut,</div><div class='ctx'> 					uint32_t regamma_size, bool has_rom,</div><div class='ctx'> 					enum dc_transfer_func_predefined tf)</div><div class='ctx'> {</div><div class='del'>-	struct dc_transfer_func *out_tf = stream-&gt;out_transfer_func;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (regamma_size || tf != TRANSFER_FUNCTION_LINEAR) {</div><div class='hunk'>@@ -639,6 +812,42 @@ static int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *f</div><div class='ctx'> 	return res ? 0 : -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * __set_input_tf_32 - calculates the input transfer function based on expected</div><div class='add'>+ * input space.</div><div class='add'>+ * @caps: dc color capabilities</div><div class='add'>+ * @func: transfer function</div><div class='add'>+ * @lut: lookup table that defines the color space</div><div class='add'>+ * @lut_size: size of respective lut.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 in case of success. -ENOMEM if fails.</div><div class='add'>+ */</div><div class='add'>+static int __set_input_tf_32(struct dc_color_caps *caps, struct dc_transfer_func *func,</div><div class='add'>+			     const struct drm_color_lut32 *lut, uint32_t lut_size)</div><div class='add'>+{</div><div class='add'>+	struct dc_gamma *gamma = NULL;</div><div class='add'>+	bool res;</div><div class='add'>+</div><div class='add'>+	if (lut_size) {</div><div class='add'>+		gamma = dc_create_gamma();</div><div class='add'>+		if (!gamma)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		gamma-&gt;type = GAMMA_CUSTOM;</div><div class='add'>+		gamma-&gt;num_entries = lut_size;</div><div class='add'>+</div><div class='add'>+		__drm_lut32_to_dc_gamma(lut, gamma);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL);</div><div class='add'>+</div><div class='add'>+	if (gamma)</div><div class='add'>+		dc_gamma_release(&amp;gamma);</div><div class='add'>+</div><div class='add'>+	return res ? 0 : -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum dc_transfer_func_predefined</div><div class='ctx'> amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf)</div><div class='ctx'> {</div><div class='hunk'>@@ -668,6 +877,27 @@ amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum dc_transfer_func_predefined</div><div class='add'>+amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf)</div><div class='add'>+{</div><div class='add'>+	switch (tf) {</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_SRGB_EOTF:</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_SRGB;</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_PQ_125_EOTF:</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_PQ;</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_BT2020_INV_OETF:</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_BT2020_OETF:</div><div class='add'>+		return TRANSFER_FUNCTION_BT709;</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_GAMMA22:</div><div class='add'>+	case DRM_COLOROP_1D_CURVE_GAMMA22_INV:</div><div class='add'>+		return TRANSFER_FUNCTION_GAMMA22;</div><div class='add'>+	default:</div><div class='add'>+		return TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void __to_dc_lut3d_color(struct dc_rgb *rgb,</div><div class='ctx'> 				const struct drm_color_lut lut,</div><div class='ctx'> 				int bit_precision)</div><div class='hunk'>@@ -721,6 +951,59 @@ static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut,</div><div class='ctx'> 	__to_dc_lut3d_color(&amp;lut0[lut_i], lut[i], bit_depth);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void __to_dc_lut3d_32_color(struct dc_rgb *rgb,</div><div class='add'>+				   const struct drm_color_lut32 lut,</div><div class='add'>+				   int bit_precision)</div><div class='add'>+{</div><div class='add'>+	rgb-&gt;red = drm_color_lut32_extract(lut.red, bit_precision);</div><div class='add'>+	rgb-&gt;green = drm_color_lut32_extract(lut.green, bit_precision);</div><div class='add'>+	rgb-&gt;blue  = drm_color_lut32_extract(lut.blue, bit_precision);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __drm_3dlut32_to_dc_3dlut(const struct drm_color_lut32 *lut,</div><div class='add'>+				       uint32_t lut3d_size,</div><div class='add'>+				       struct tetrahedral_params *params,</div><div class='add'>+				       bool use_tetrahedral_9,</div><div class='add'>+				       int bit_depth)</div><div class='add'>+{</div><div class='add'>+	struct dc_rgb *lut0;</div><div class='add'>+	struct dc_rgb *lut1;</div><div class='add'>+	struct dc_rgb *lut2;</div><div class='add'>+	struct dc_rgb *lut3;</div><div class='add'>+	int lut_i, i;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (use_tetrahedral_9) {</div><div class='add'>+		lut0 = params-&gt;tetrahedral_9.lut0;</div><div class='add'>+		lut1 = params-&gt;tetrahedral_9.lut1;</div><div class='add'>+		lut2 = params-&gt;tetrahedral_9.lut2;</div><div class='add'>+		lut3 = params-&gt;tetrahedral_9.lut3;</div><div class='add'>+	} else {</div><div class='add'>+		lut0 = params-&gt;tetrahedral_17.lut0;</div><div class='add'>+		lut1 = params-&gt;tetrahedral_17.lut1;</div><div class='add'>+		lut2 = params-&gt;tetrahedral_17.lut2;</div><div class='add'>+		lut3 = params-&gt;tetrahedral_17.lut3;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (lut_i = 0, i = 0; i &lt; lut3d_size - 4; lut_i++, i += 4) {</div><div class='add'>+		/*</div><div class='add'>+		 * We should consider the 3D LUT RGB values are distributed</div><div class='add'>+		 * along four arrays lut0-3 where the first sizes 1229 and the</div><div class='add'>+		 * other 1228. The bit depth supported for 3dlut channel is</div><div class='add'>+		 * 12-bit, but DC also supports 10-bit.</div><div class='add'>+		 *</div><div class='add'>+		 * TODO: improve color pipeline API to enable the userspace set</div><div class='add'>+		 * bit depth and 3D LUT size/stride, as specified by VA-API.</div><div class='add'>+		 */</div><div class='add'>+		__to_dc_lut3d_32_color(&amp;lut0[lut_i], lut[i], bit_depth);</div><div class='add'>+		__to_dc_lut3d_32_color(&amp;lut1[lut_i], lut[i + 1], bit_depth);</div><div class='add'>+		__to_dc_lut3d_32_color(&amp;lut2[lut_i], lut[i + 2], bit_depth);</div><div class='add'>+		__to_dc_lut3d_32_color(&amp;lut3[lut_i], lut[i + 3], bit_depth);</div><div class='add'>+	}</div><div class='add'>+	/* lut0 has 1229 points (lut_size/4 + 1) */</div><div class='add'>+	__to_dc_lut3d_32_color(&amp;lut0[lut_i], lut[i], bit_depth);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream</div><div class='ctx'>  * @drm_lut3d: user 3D LUT</div><div class='ctx'>  * @drm_lut3d_size: size of 3D LUT</div><div class='hunk'>@@ -821,7 +1104,7 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,</div><div class='ctx'> 	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);</div><div class='ctx'> 	const struct drm_color_lut *shaper = NULL, *lut3d = NULL;</div><div class='ctx'> 	uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;</div><div class='del'>-	bool has_3dlut = adev-&gt;dm.dc-&gt;caps.color.dpp.hw_3d_lut;</div><div class='add'>+	bool has_3dlut = adev-&gt;dm.dc-&gt;caps.color.dpp.hw_3d_lut || adev-&gt;dm.dc-&gt;caps.color.mpc.preblend;</div><div class='ctx'> </div><div class='ctx'> 	/* shaper LUT is only available if 3D LUT color caps */</div><div class='ctx'> 	exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;</div><div class='hunk'>@@ -885,33 +1168,33 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.</div><div class='add'>+ * amdgpu_dm_check_crtc_color_mgmt: Check if DRM color props are programmable by DC.</div><div class='ctx'>  * @crtc: amdgpu_dm crtc state</div><div class='add'>+ * @check_only: only check color state without update dc stream</div><div class='ctx'>  *</div><div class='del'>- * With no plane level color management properties we're free to use any</div><div class='del'>- * of the HW blocks as long as the CRTC CTM always comes before the</div><div class='del'>- * CRTC RGM and after the CRTC DGM.</div><div class='del'>- *</div><div class='del'>- * - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.</div><div class='del'>- * - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.</div><div class='del'>- * - The CRTC CTM will be placed in the gamut remap block if it is non-linear.</div><div class='add'>+ * This function just verifies CRTC LUT sizes, if there is enough space for</div><div class='add'>+ * output transfer function and if its parameters can be calculated by AMD</div><div class='add'>+ * color module. It also adjusts some settings for programming CRTC degamma at</div><div class='add'>+ * plane stage, using plane DGM block.</div><div class='ctx'>  *</div><div class='ctx'>  * The RGM block is typically more fully featured and accurate across</div><div class='ctx'>  * all ASICs - DCE can't support a custom non-linear CRTC DGM.</div><div class='ctx'>  *</div><div class='ctx'>  * For supporting both plane level color management and CRTC level color</div><div class='del'>- * management at once we have to either restrict the usage of CRTC properties</div><div class='del'>- * or blend adjustments together.</div><div class='add'>+ * management at once we have to either restrict the usage of some CRTC</div><div class='add'>+ * properties or blend adjustments together.</div><div class='ctx'>  *</div><div class='ctx'>  * Returns:</div><div class='del'>- * 0 on success. Error code if setup fails.</div><div class='add'>+ * 0 on success. Error code if validation fails.</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='add'>+</div><div class='add'>+int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc,</div><div class='add'>+				    bool check_only)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_stream_state *stream = crtc-&gt;stream;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;base.state-&gt;dev);</div><div class='ctx'> 	bool has_rom = adev-&gt;asic_type &lt;= CHIP_RAVEN;</div><div class='del'>-	struct drm_color_ctm *ctm = NULL;</div><div class='add'>+	struct dc_transfer_func *out_tf;</div><div class='ctx'> 	const struct drm_color_lut *degamma_lut, *regamma_lut;</div><div class='ctx'> 	uint32_t degamma_size, regamma_size;</div><div class='ctx'> 	bool has_regamma, has_degamma;</div><div class='hunk'>@@ -940,6 +1223,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 	crtc-&gt;cm_has_degamma = false;</div><div class='ctx'> 	crtc-&gt;cm_is_degamma_srgb = false;</div><div class='ctx'> </div><div class='add'>+	if (check_only) {</div><div class='add'>+		out_tf = kvzalloc(sizeof(*out_tf), GFP_KERNEL);</div><div class='add'>+		if (!out_tf)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	} else {</div><div class='add'>+		out_tf = &amp;stream-&gt;out_transfer_func;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Setup regamma and degamma. */</div><div class='ctx'> 	if (is_legacy) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -954,8 +1245,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 		 * inverse color ramp in legacy userspace.</div><div class='ctx'> 		 */</div><div class='ctx'> 		crtc-&gt;cm_is_degamma_srgb = true;</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;tf = TRANSFER_FUNCTION_SRGB;</div><div class='add'>+		out_tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		out_tf-&gt;tf = TRANSFER_FUNCTION_SRGB;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Note: although we pass has_rom as parameter here, we never</div><div class='ctx'> 		 * actually use ROM because the color module only takes the ROM</div><div class='hunk'>@@ -963,16 +1254,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * See more in mod_color_calculate_regamma_params()</div><div class='ctx'> 		 */</div><div class='del'>-		r = __set_legacy_tf(stream-&gt;out_transfer_func, regamma_lut,</div><div class='add'>+		r = __set_legacy_tf(out_tf, regamma_lut,</div><div class='ctx'> 				    regamma_size, has_rom);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		regamma_size = has_regamma ? regamma_size : 0;</div><div class='del'>-		r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut,</div><div class='add'>+		r = amdgpu_dm_set_atomic_regamma(out_tf, regamma_lut,</div><div class='ctx'> 						 regamma_size, has_rom, tf);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -981,6 +1268,43 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 	 * have to place the CTM in the OCSC in that case.</div><div class='ctx'> 	 */</div><div class='ctx'> 	crtc-&gt;cm_has_degamma = has_degamma;</div><div class='add'>+	if (check_only)</div><div class='add'>+		kvfree(out_tf);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.</div><div class='add'>+ * @crtc: amdgpu_dm crtc state</div><div class='add'>+ *</div><div class='add'>+ * With no plane level color management properties we're free to use any</div><div class='add'>+ * of the HW blocks as long as the CRTC CTM always comes before the</div><div class='add'>+ * CRTC RGM and after the CRTC DGM.</div><div class='add'>+ *</div><div class='add'>+ * - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.</div><div class='add'>+ * - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.</div><div class='add'>+ * - The CRTC CTM will be placed in the gamut remap block if it is non-linear.</div><div class='add'>+ *</div><div class='add'>+ * The RGM block is typically more fully featured and accurate across</div><div class='add'>+ * all ASICs - DCE can't support a custom non-linear CRTC DGM.</div><div class='add'>+ *</div><div class='add'>+ * For supporting both plane level color management and CRTC level color</div><div class='add'>+ * management at once we have to either restrict the usage of CRTC properties</div><div class='add'>+ * or blend adjustments together.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success. Error code if setup fails.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *stream = crtc-&gt;stream;</div><div class='add'>+	struct drm_color_ctm *ctm = NULL;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dm_check_crtc_color_mgmt(crtc, false);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Setup CRTC CTM. */</div><div class='ctx'> 	if (crtc-&gt;base.ctm) {</div><div class='hunk'>@@ -1034,7 +1358,7 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,</div><div class='ctx'> 						 &amp;degamma_size);</div><div class='ctx'> 		ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);</div><div class='ctx'> </div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func.type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * This case isn't fully correct, but also fairly</div><div class='hunk'>@@ -1061,12 +1385,12 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,</div><div class='ctx'> 		 * map these to the atomic one instead.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (crtc-&gt;cm_is_degamma_srgb)</div><div class='del'>-			dc_plane_state-&gt;in_transfer_func-&gt;tf = tf;</div><div class='add'>+			dc_plane_state-&gt;in_transfer_func.tf = tf;</div><div class='ctx'> 		else</div><div class='del'>-			dc_plane_state-&gt;in_transfer_func-&gt;tf =</div><div class='add'>+			dc_plane_state-&gt;in_transfer_func.tf =</div><div class='ctx'> 				TRANSFER_FUNCTION_LINEAR;</div><div class='ctx'> </div><div class='del'>-		r = __set_input_tf(caps, dc_plane_state-&gt;in_transfer_func,</div><div class='add'>+		r = __set_input_tf(caps, &amp;dc_plane_state-&gt;in_transfer_func,</div><div class='ctx'> 				   degamma_lut, degamma_size);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='hunk'>@@ -1075,12 +1399,12 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,</div><div class='ctx'> 		 * For legacy gamma support we need the regamma input</div><div class='ctx'> 		 * in linear space. Assume that the input is sRGB.</div><div class='ctx'> 		 */</div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_PREDEFINED;</div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;tf = tf;</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func.type = TF_TYPE_PREDEFINED;</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func.tf = tf;</div><div class='ctx'> </div><div class='ctx'> 		if (tf != TRANSFER_FUNCTION_SRGB &amp;&amp;</div><div class='ctx'> 		    !mod_color_calculate_degamma_params(caps,</div><div class='del'>-							dc_plane_state-&gt;in_transfer_func,</div><div class='add'>+							&amp;dc_plane_state-&gt;in_transfer_func,</div><div class='ctx'> 							NULL, false))</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1114,30 +1438,384 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state,</div><div class='ctx'> 	if (!has_degamma_lut &amp;&amp; tf == AMDGPU_TRANSFER_FUNCTION_DEFAULT)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	dc_plane_state-&gt;in_transfer_func-&gt;tf = amdgpu_tf_to_dc_tf(tf);</div><div class='add'>+	dc_plane_state-&gt;in_transfer_func.tf = amdgpu_tf_to_dc_tf(tf);</div><div class='ctx'> </div><div class='ctx'> 	if (has_degamma_lut) {</div><div class='ctx'> 		ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);</div><div class='ctx'> </div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;type =</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func.type =</div><div class='ctx'> 			TF_TYPE_DISTRIBUTED_POINTS;</div><div class='ctx'> </div><div class='del'>-		ret = __set_input_tf(color_caps, dc_plane_state-&gt;in_transfer_func,</div><div class='add'>+		ret = __set_input_tf(color_caps, &amp;dc_plane_state-&gt;in_transfer_func,</div><div class='ctx'> 				     degamma_lut, degamma_size);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'>        } else {</div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;type =</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func.type =</div><div class='ctx'> 			TF_TYPE_PREDEFINED;</div><div class='ctx'> </div><div class='ctx'> 		if (!mod_color_calculate_degamma_params(color_caps,</div><div class='del'>-		    dc_plane_state-&gt;in_transfer_func, NULL, false))</div><div class='add'>+		    &amp;dc_plane_state-&gt;in_transfer_func, NULL, false))</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='add'>+__set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state,</div><div class='add'>+			     struct drm_colorop_state *colorop_state)</div><div class='add'>+{</div><div class='add'>+	struct dc_transfer_func *tf = &amp;dc_plane_state-&gt;in_transfer_func;</div><div class='add'>+	struct drm_colorop *colorop = colorop_state-&gt;colorop;</div><div class='add'>+	struct drm_device *drm = colorop-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (colorop-&gt;type != DRM_COLOROP_1D_CURVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!(BIT(colorop_state-&gt;curve_1d_type) &amp; amdgpu_dm_supported_degam_tfs))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (colorop_state-&gt;bypass) {</div><div class='add'>+		tf-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+		tf-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_dbg(drm, "Degamma colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+</div><div class='add'>+	tf-&gt;type = TF_TYPE_PREDEFINED;</div><div class='add'>+	tf-&gt;tf = amdgpu_colorop_tf_to_dc_tf(colorop_state-&gt;curve_1d_type);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state,</div><div class='add'>+			       struct dc_plane_state *dc_plane_state,</div><div class='add'>+			       struct drm_colorop *colorop)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *old_colorop;</div><div class='add'>+	struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;</div><div class='add'>+	struct drm_atomic_state *state = plane_state-&gt;state;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+</div><div class='add'>+	/* 1st op: 1d curve - degamma */</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    (BIT(new_colorop_state-&gt;curve_1d_type) &amp; amdgpu_dm_supported_degam_tfs)) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!colorop_state)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return __set_colorop_in_tf_1d_curve(dc_plane_state, colorop_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_colorop_3x4_matrix(struct drm_plane_state *plane_state,</div><div class='add'>+				  struct dc_plane_state *dc_plane_state,</div><div class='add'>+				  struct drm_colorop *colorop)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *old_colorop;</div><div class='add'>+	struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;</div><div class='add'>+	struct drm_atomic_state *state = plane_state-&gt;state;</div><div class='add'>+	const struct drm_device *dev = colorop-&gt;dev;</div><div class='add'>+	const struct drm_property_blob *blob;</div><div class='add'>+	struct drm_color_ctm_3x4 *ctm = NULL;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	/* 3x4 matrix */</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    new_colorop_state-&gt;colorop-&gt;type == DRM_COLOROP_CTM_3X4) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_CTM_3X4) {</div><div class='add'>+		drm_dbg(dev, "3x4 matrix colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		blob = colorop_state-&gt;data;</div><div class='add'>+		if (blob-&gt;length == sizeof(struct drm_color_ctm_3x4)) {</div><div class='add'>+			ctm = (struct drm_color_ctm_3x4 *) blob-&gt;data;</div><div class='add'>+			__drm_ctm_3x4_to_dc_matrix(ctm, dc_plane_state-&gt;gamut_remap_matrix.matrix);</div><div class='add'>+			dc_plane_state-&gt;gamut_remap_matrix.enable_remap = true;</div><div class='add'>+			dc_plane_state-&gt;input_csc_color_matrix.enable_adjustment = false;</div><div class='add'>+		} else {</div><div class='add'>+			drm_warn(dev, "blob-&gt;length (%zu) isn't equal to drm_color_ctm_3x4 (%zu)\n",</div><div class='add'>+				 blob-&gt;length, sizeof(struct drm_color_ctm_3x4));</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_colorop_multiplier(struct drm_plane_state *plane_state,</div><div class='add'>+				  struct dc_plane_state *dc_plane_state,</div><div class='add'>+				  struct drm_colorop *colorop)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *old_colorop;</div><div class='add'>+	struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;</div><div class='add'>+	struct drm_atomic_state *state = plane_state-&gt;state;</div><div class='add'>+	const struct drm_device *dev = colorop-&gt;dev;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	/* Multiplier */</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    new_colorop_state-&gt;colorop-&gt;type == DRM_COLOROP_MULTIPLIER) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_MULTIPLIER) {</div><div class='add'>+		drm_dbg(dev, "Multiplier colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		dc_plane_state-&gt;hdr_mult = amdgpu_dm_fixpt_from_s3132(colorop_state-&gt;multiplier);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,</div><div class='add'>+			      struct dc_plane_state *dc_plane_state,</div><div class='add'>+			      struct drm_colorop *colorop)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *old_colorop;</div><div class='add'>+	struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;</div><div class='add'>+	struct drm_atomic_state *state = plane_state-&gt;state;</div><div class='add'>+	enum dc_transfer_func_predefined default_tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	struct dc_transfer_func *tf = &amp;dc_plane_state-&gt;in_shaper_func;</div><div class='add'>+	const struct drm_color_lut32 *shaper_lut;</div><div class='add'>+	struct drm_device *dev = colorop-&gt;dev;</div><div class='add'>+	bool enabled = false;</div><div class='add'>+	u32 shaper_size;</div><div class='add'>+	int i = 0, ret = 0;</div><div class='add'>+</div><div class='add'>+	/* 1D Curve - SHAPER TF */</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    (BIT(new_colorop_state-&gt;curve_1d_type) &amp; amdgpu_dm_supported_shaper_tfs)) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_1D_CURVE) {</div><div class='add'>+		drm_dbg(dev, "Shaper TF colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		tf-&gt;tf = default_tf = amdgpu_colorop_tf_to_dc_tf(colorop_state-&gt;curve_1d_type);</div><div class='add'>+		tf-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+		ret = __set_output_tf(tf, 0, 0, false);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		enabled = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 1D LUT - SHAPER LUT */</div><div class='add'>+	colorop = old_colorop-&gt;next;</div><div class='add'>+	if (!colorop) {</div><div class='add'>+		drm_dbg(dev, "no Shaper LUT colorop found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    new_colorop_state-&gt;colorop-&gt;type == DRM_COLOROP_1D_LUT) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_1D_LUT) {</div><div class='add'>+		drm_dbg(dev, "Shaper LUT colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		tf-&gt;tf = default_tf;</div><div class='add'>+		tf-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+		shaper_lut = __extract_blob_lut32(colorop_state-&gt;data, &amp;shaper_size);</div><div class='add'>+		shaper_size = shaper_lut != NULL ? shaper_size : 0;</div><div class='add'>+</div><div class='add'>+		/* Custom LUT size must be the same as supported size */</div><div class='add'>+		if (shaper_size == colorop-&gt;size) {</div><div class='add'>+			ret = __set_output_tf_32(tf, shaper_lut, shaper_size, false);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+			enabled = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!enabled)</div><div class='add'>+		tf-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* __set_colorop_3dlut - set DRM 3D LUT to DC stream</div><div class='add'>+ * @drm_lut3d: user 3D LUT</div><div class='add'>+ * @drm_lut3d_size: size of 3D LUT</div><div class='add'>+ * @lut3d: DC 3D LUT</div><div class='add'>+ *</div><div class='add'>+ * Map user 3D LUT data to DC 3D LUT and all necessary bits to program it</div><div class='add'>+ * on DCN accordingly.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success. -EINVAL if drm_lut3d_size is zero.</div><div class='add'>+ */</div><div class='add'>+static int __set_colorop_3dlut(const struct drm_color_lut32 *drm_lut3d,</div><div class='add'>+				uint32_t drm_lut3d_size,</div><div class='add'>+				struct dc_3dlut *lut)</div><div class='add'>+{</div><div class='add'>+	if (!drm_lut3d_size) {</div><div class='add'>+		lut-&gt;state.bits.initialized = 0;</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Only supports 17x17x17 3D LUT (12-bit) now */</div><div class='add'>+	lut-&gt;lut_3d.use_12bits = true;</div><div class='add'>+	lut-&gt;lut_3d.use_tetrahedral_9 = false;</div><div class='add'>+</div><div class='add'>+	lut-&gt;state.bits.initialized = 1;</div><div class='add'>+	__drm_3dlut32_to_dc_3dlut(drm_lut3d, drm_lut3d_size, &amp;lut-&gt;lut_3d,</div><div class='add'>+				   lut-&gt;lut_3d.use_tetrahedral_9, 12);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_colorop_3dlut(struct drm_plane_state *plane_state,</div><div class='add'>+			     struct dc_plane_state *dc_plane_state,</div><div class='add'>+			     struct drm_colorop *colorop)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *old_colorop;</div><div class='add'>+	struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;</div><div class='add'>+	struct dc_transfer_func *tf = &amp;dc_plane_state-&gt;in_shaper_func;</div><div class='add'>+	struct drm_atomic_state *state = plane_state-&gt;state;</div><div class='add'>+	const struct amdgpu_device *adev = drm_to_adev(colorop-&gt;dev);</div><div class='add'>+	const struct drm_device *dev = colorop-&gt;dev;</div><div class='add'>+	const struct drm_color_lut32 *lut3d;</div><div class='add'>+	uint32_t lut3d_size;</div><div class='add'>+	int i = 0, ret = 0;</div><div class='add'>+</div><div class='add'>+	/* 3D LUT */</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    new_colorop_state-&gt;colorop-&gt;type == DRM_COLOROP_3D_LUT) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_3D_LUT) {</div><div class='add'>+		if (!adev-&gt;dm.dc-&gt;caps.color.dpp.hw_3d_lut) {</div><div class='add'>+			drm_dbg(dev, "3D LUT is not supported by hardware\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_dbg(dev, "3D LUT colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		lut3d = __extract_blob_lut32(colorop_state-&gt;data, &amp;lut3d_size);</div><div class='add'>+		lut3d_size = lut3d != NULL ? lut3d_size : 0;</div><div class='add'>+		ret = __set_colorop_3dlut(lut3d, lut3d_size, &amp;dc_plane_state-&gt;lut3d_func);</div><div class='add'>+		if (ret) {</div><div class='add'>+			drm_dbg(dev, "3D LUT colorop with ID: %d has LUT size = %d\n",</div><div class='add'>+				colorop-&gt;base.id, lut3d_size);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* 3D LUT requires shaper. If shaper colorop is bypassed, enable shaper curve</div><div class='add'>+		 * with TRANSFER_FUNCTION_LINEAR</div><div class='add'>+		 */</div><div class='add'>+		if (tf-&gt;type == TF_TYPE_BYPASS) {</div><div class='add'>+			tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+			tf-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+			tf-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+			ret = __set_output_tf_32(tf, NULL, 0, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_colorop_blend(struct drm_plane_state *plane_state,</div><div class='add'>+			     struct dc_plane_state *dc_plane_state,</div><div class='add'>+			     struct drm_colorop *colorop)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *old_colorop;</div><div class='add'>+	struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;</div><div class='add'>+	struct drm_atomic_state *state = plane_state-&gt;state;</div><div class='add'>+	enum dc_transfer_func_predefined default_tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	struct dc_transfer_func *tf = &amp;dc_plane_state-&gt;blend_tf;</div><div class='add'>+	const struct drm_color_lut32 *blend_lut = NULL;</div><div class='add'>+	struct drm_device *dev = colorop-&gt;dev;</div><div class='add'>+	uint32_t blend_size = 0;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	/* 1D Curve - BLND TF */</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    (BIT(new_colorop_state-&gt;curve_1d_type) &amp; amdgpu_dm_supported_blnd_tfs)) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_1D_CURVE &amp;&amp;</div><div class='add'>+	    (BIT(colorop_state-&gt;curve_1d_type) &amp; amdgpu_dm_supported_blnd_tfs)) {</div><div class='add'>+		drm_dbg(dev, "Blend TF colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		tf-&gt;tf = default_tf = amdgpu_colorop_tf_to_dc_tf(colorop_state-&gt;curve_1d_type);</div><div class='add'>+		tf-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+		__set_input_tf_32(NULL, tf, blend_lut, blend_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 1D Curve - BLND LUT */</div><div class='add'>+	colorop = old_colorop-&gt;next;</div><div class='add'>+	if (!colorop) {</div><div class='add'>+		drm_dbg(dev, "no Blend LUT colorop found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	old_colorop = colorop;</div><div class='add'>+	for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {</div><div class='add'>+		if (new_colorop_state-&gt;colorop == old_colorop &amp;&amp;</div><div class='add'>+		    new_colorop_state-&gt;colorop-&gt;type == DRM_COLOROP_1D_LUT) {</div><div class='add'>+			colorop_state = new_colorop_state;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (colorop_state &amp;&amp; !colorop_state-&gt;bypass &amp;&amp; colorop-&gt;type == DRM_COLOROP_1D_LUT &amp;&amp;</div><div class='add'>+	    (BIT(colorop_state-&gt;curve_1d_type) &amp; amdgpu_dm_supported_blnd_tfs)) {</div><div class='add'>+		drm_dbg(dev, "Blend LUT colorop with ID: %d\n", colorop-&gt;base.id);</div><div class='add'>+		tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		tf-&gt;tf = default_tf;</div><div class='add'>+		tf-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+		blend_lut = __extract_blob_lut32(colorop_state-&gt;data, &amp;blend_size);</div><div class='add'>+		blend_size = blend_lut != NULL ? blend_size : 0;</div><div class='add'>+</div><div class='add'>+		/* Custom LUT size must be the same as supported size */</div><div class='add'>+		if (blend_size == colorop-&gt;size)</div><div class='add'>+			__set_input_tf_32(NULL, tf, blend_lut, blend_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='ctx'> amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,</div><div class='ctx'> 				     struct dc_plane_state *dc_plane_state)</div><div class='ctx'> {</div><div class='hunk'>@@ -1156,11 +1834,11 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,</div><div class='ctx'> 	lut3d = __extract_blob_lut(dm_plane_state-&gt;lut3d, &amp;lut3d_size);</div><div class='ctx'> 	lut3d_size = lut3d != NULL ? lut3d_size : 0;</div><div class='ctx'> </div><div class='del'>-	amdgpu_dm_atomic_lut3d(lut3d, lut3d_size, dc_plane_state-&gt;lut3d_func);</div><div class='add'>+	amdgpu_dm_atomic_lut3d(lut3d, lut3d_size, &amp;dc_plane_state-&gt;lut3d_func);</div><div class='ctx'> 	ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false,</div><div class='ctx'> 					  amdgpu_tf_to_dc_tf(shaper_tf),</div><div class='ctx'> 					  shaper_size,</div><div class='del'>-					  dc_plane_state-&gt;in_shaper_func);</div><div class='add'>+					  &amp;dc_plane_state-&gt;in_shaper_func);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		drm_dbg_kms(plane_state-&gt;plane-&gt;dev,</div><div class='ctx'> 			    "setting plane %d shaper LUT failed.\n",</div><div class='hunk'>@@ -1175,7 +1853,7 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_dm_atomic_blend_lut(blend_lut, false,</div><div class='ctx'> 					 amdgpu_tf_to_dc_tf(blend_tf),</div><div class='del'>-					 blend_size, dc_plane_state-&gt;blend_tf);</div><div class='add'>+					 blend_size, &amp;dc_plane_state-&gt;blend_tf);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		drm_dbg_kms(plane_state-&gt;plane-&gt;dev,</div><div class='ctx'> 			    "setting plane %d gamma lut failed.\n",</div><div class='hunk'>@@ -1187,6 +1865,93 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int</div><div class='add'>+amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,</div><div class='add'>+				       struct dc_plane_state *dc_plane_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *colorop = plane_state-&gt;color_pipeline;</div><div class='add'>+	struct drm_device *dev = plane_state-&gt;plane-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* 1D Curve - DEGAM TF */</div><div class='add'>+	if (!colorop)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = __set_dm_plane_colorop_degamma(plane_state, dc_plane_state, colorop);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Multiplier */</div><div class='add'>+	colorop = colorop-&gt;next;</div><div class='add'>+	if (!colorop) {</div><div class='add'>+		drm_dbg(dev, "no multiplier colorop found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = __set_dm_plane_colorop_multiplier(plane_state, dc_plane_state, colorop);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* 3x4 matrix */</div><div class='add'>+	colorop = colorop-&gt;next;</div><div class='add'>+	if (!colorop) {</div><div class='add'>+		drm_dbg(dev, "no 3x4 matrix colorop found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = __set_dm_plane_colorop_3x4_matrix(plane_state, dc_plane_state, colorop);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dm.dc-&gt;caps.color.dpp.hw_3d_lut) {</div><div class='add'>+		/* 1D Curve &amp; LUT - SHAPER TF &amp; LUT */</div><div class='add'>+		colorop = colorop-&gt;next;</div><div class='add'>+		if (!colorop) {</div><div class='add'>+			drm_dbg(dev, "no Shaper TF colorop found\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = __set_dm_plane_colorop_shaper(plane_state, dc_plane_state, colorop);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/* Shaper LUT colorop is already handled, just skip here */</div><div class='add'>+		colorop = colorop-&gt;next;</div><div class='add'>+		if (!colorop)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		/* 3D LUT */</div><div class='add'>+		colorop = colorop-&gt;next;</div><div class='add'>+		if (!colorop) {</div><div class='add'>+			drm_dbg(dev, "no 3D LUT colorop found\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = __set_dm_plane_colorop_3dlut(plane_state, dc_plane_state, colorop);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 1D Curve &amp; LUT - BLND TF &amp; LUT */</div><div class='add'>+	colorop = colorop-&gt;next;</div><div class='add'>+	if (!colorop) {</div><div class='add'>+		drm_dbg(dev, "no Blend TF colorop found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = __set_dm_plane_colorop_blend(plane_state, dc_plane_state, colorop);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* BLND LUT colorop is already handled, just skip here */</div><div class='add'>+	colorop = colorop-&gt;next;</div><div class='add'>+	if (!colorop)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.</div><div class='ctx'>  * @crtc: amdgpu_dm crtc state</div><div class='hunk'>@@ -1221,8 +1986,8 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='ctx'> 		color_caps = &amp;dc_plane_state-&gt;ctx-&gt;dc-&gt;caps.color;</div><div class='ctx'> </div><div class='ctx'> 	/* Initially, we can just bypass the DGM block. */</div><div class='del'>-	dc_plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='del'>-	dc_plane_state-&gt;in_transfer_func-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	dc_plane_state-&gt;in_transfer_func.type = TF_TYPE_BYPASS;</div><div class='add'>+	dc_plane_state-&gt;in_transfer_func.tf = TRANSFER_FUNCTION_LINEAR;</div><div class='ctx'> </div><div class='ctx'> 	/* After, we start to update values according to color props */</div><div class='ctx'> 	has_crtc_cm_degamma = (crtc-&gt;cm_has_degamma || crtc-&gt;cm_is_degamma_srgb);</div><div class='hunk'>@@ -1283,5 +2048,8 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='ctx'> 		dc_plane_state-&gt;input_csc_color_matrix.enable_adjustment = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c<br/>new file mode 100644<br/>index 000000000000..d585618b8064<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c</a></div><div class='hunk'>@@ -0,0 +1,209 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+#include &lt;drm/drm_plane.h&gt;</div><div class='add'>+#include &lt;drm/drm_property.h&gt;</div><div class='add'>+#include &lt;drm/drm_colorop.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_dm_colorop.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+</div><div class='add'>+const u64 amdgpu_dm_supported_degam_tfs =</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);</div><div class='add'>+</div><div class='add'>+const u64 amdgpu_dm_supported_shaper_tfs =</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_GAMMA22);</div><div class='add'>+</div><div class='add'>+const u64 amdgpu_dm_supported_blnd_tfs =</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |</div><div class='add'>+	BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);</div><div class='add'>+</div><div class='add'>+#define MAX_COLOR_PIPELINE_OPS 10</div><div class='add'>+</div><div class='add'>+#define LUT3D_SIZE		17</div><div class='add'>+</div><div class='add'>+int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list)</div><div class='add'>+{</div><div class='add'>+	struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS];</div><div class='add'>+	struct drm_device *dev = plane-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	int ret;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	memset(ops, 0, sizeof(ops));</div><div class='add'>+</div><div class='add'>+	/* 1D curve - DEGAM TF */</div><div class='add'>+	ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);</div><div class='add'>+	if (!ops[i]) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane,</div><div class='add'>+					      amdgpu_dm_supported_degam_tfs,</div><div class='add'>+					      DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	list-&gt;type = ops[i]-&gt;base.id;</div><div class='add'>+	list-&gt;name = kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[i]-&gt;base.id);</div><div class='add'>+</div><div class='add'>+	i++;</div><div class='add'>+</div><div class='add'>+	/* Multiplier */</div><div class='add'>+	ops[i] = kzalloc(sizeof(struct drm_colorop), GFP_KERNEL);</div><div class='add'>+	if (!ops[i]) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drm_plane_colorop_mult_init(dev, ops[i], plane, DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	drm_colorop_set_next_property(ops[i-1], ops[i]);</div><div class='add'>+</div><div class='add'>+	i++;</div><div class='add'>+</div><div class='add'>+	/* 3x4 matrix */</div><div class='add'>+	ops[i] = kzalloc(sizeof(struct drm_colorop), GFP_KERNEL);</div><div class='add'>+	if (!ops[i]) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drm_plane_colorop_ctm_3x4_init(dev, ops[i], plane, DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	drm_colorop_set_next_property(ops[i-1], ops[i]);</div><div class='add'>+</div><div class='add'>+	i++;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dm.dc-&gt;caps.color.dpp.hw_3d_lut) {</div><div class='add'>+		/* 1D curve - SHAPER TF */</div><div class='add'>+		ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);</div><div class='add'>+		if (!ops[i]) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto cleanup;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane,</div><div class='add'>+						amdgpu_dm_supported_shaper_tfs,</div><div class='add'>+						DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto cleanup;</div><div class='add'>+</div><div class='add'>+		drm_colorop_set_next_property(ops[i-1], ops[i]);</div><div class='add'>+</div><div class='add'>+		i++;</div><div class='add'>+</div><div class='add'>+		/* 1D LUT - SHAPER LUT */</div><div class='add'>+		ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);</div><div class='add'>+		if (!ops[i]) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto cleanup;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = drm_plane_colorop_curve_1d_lut_init(dev, ops[i], plane, MAX_COLOR_LUT_ENTRIES,</div><div class='add'>+							DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,</div><div class='add'>+							DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto cleanup;</div><div class='add'>+</div><div class='add'>+		drm_colorop_set_next_property(ops[i-1], ops[i]);</div><div class='add'>+</div><div class='add'>+		i++;</div><div class='add'>+</div><div class='add'>+		/* 3D LUT */</div><div class='add'>+		ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);</div><div class='add'>+		if (!ops[i]) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto cleanup;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = drm_plane_colorop_3dlut_init(dev, ops[i], plane, LUT3D_SIZE,</div><div class='add'>+					DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,</div><div class='add'>+					DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto cleanup;</div><div class='add'>+</div><div class='add'>+		drm_colorop_set_next_property(ops[i-1], ops[i]);</div><div class='add'>+</div><div class='add'>+		i++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 1D curve - BLND TF */</div><div class='add'>+	ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);</div><div class='add'>+	if (!ops[i]) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane,</div><div class='add'>+					      amdgpu_dm_supported_blnd_tfs,</div><div class='add'>+					      DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	drm_colorop_set_next_property(ops[i - 1], ops[i]);</div><div class='add'>+</div><div class='add'>+	i++;</div><div class='add'>+</div><div class='add'>+	/* 1D LUT - BLND LUT */</div><div class='add'>+	ops[i] = kzalloc(sizeof(struct drm_colorop), GFP_KERNEL);</div><div class='add'>+	if (!ops[i]) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drm_plane_colorop_curve_1d_lut_init(dev, ops[i], plane, MAX_COLOR_LUT_ENTRIES,</div><div class='add'>+						  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,</div><div class='add'>+						  DRM_COLOROP_FLAG_ALLOW_BYPASS);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	drm_colorop_set_next_property(ops[i-1], ops[i]);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+cleanup:</div><div class='add'>+	if (ret == -ENOMEM)</div><div class='add'>+		drm_err(plane-&gt;dev, "KMS: Failed to allocate colorop\n");</div><div class='add'>+</div><div class='add'>+	drm_colorop_pipeline_destroy(dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h<br/>index 3341ef71009b..2e1617ffc8ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.h</a></div><div class='hunk'>@@ -24,30 +24,13 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "core_types.h"</div><div class='del'>-#include "dcn35_dpp.h"</div><div class='del'>-#include "reg_helper.h"</div><div class='add'>+#ifndef __AMDGPU_DM_COLOROP_H__</div><div class='add'>+#define __AMDGPU_DM_COLOROP_H__</div><div class='ctx'> </div><div class='del'>-#define REG(reg) dpp-&gt;tf_regs-&gt;reg</div><div class='add'>+extern const u64 amdgpu_dm_supported_degam_tfs;</div><div class='add'>+extern const u64 amdgpu_dm_supported_shaper_tfs;</div><div class='add'>+extern const u64 amdgpu_dm_supported_blnd_tfs;</div><div class='ctx'> </div><div class='del'>-#define CTX dpp-&gt;base.ctx</div><div class='add'>+int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list);</div><div class='ctx'> </div><div class='del'>-#undef FN</div><div class='del'>-#define FN(reg_name, field_name)                                       \</div><div class='del'>-	((const struct dcn35_dpp_shift *)(dpp-&gt;tf_shift))-&gt;field_name, \</div><div class='del'>-	((const struct dcn35_dpp_mask *)(dpp-&gt;tf_mask))-&gt;field_name</div><div class='del'>-</div><div class='del'>-bool dpp35_construct(struct dcn3_dpp *dpp, struct dc_context *ctx,</div><div class='del'>-		     uint32_t inst, const struct dcn3_dpp_registers *tf_regs,</div><div class='del'>-		     const struct dcn35_dpp_shift *tf_shift,</div><div class='del'>-		     const struct dcn35_dpp_mask *tf_mask)</div><div class='del'>-{</div><div class='del'>-	return dpp32_construct(dpp, ctx, inst, tf_regs,</div><div class='del'>-			      (const struct dcn3_dpp_shift *)(tf_shift),</div><div class='del'>-			      (const struct dcn3_dpp_mask *)(tf_mask));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)</div><div class='del'>-{</div><div class='del'>-	REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);</div><div class='del'>-}</div><div class='add'>+#endif /* __AMDGPU_DM_COLOROP_H__*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c<br/>index f936a35fa9eb..e20aa7438066 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -30,6 +31,7 @@</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "amdgpu_securedisplay.h"</div><div class='add'>+#include "amdgpu_dm_psr.h"</div><div class='ctx'> </div><div class='ctx'> static const char *const pipe_crc_sources[] = {</div><div class='ctx'> 	"none",</div><div class='hunk'>@@ -83,45 +85,274 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='add'>+static void update_phy_id_mapping(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = adev_to_drm(adev);</div><div class='add'>+	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='add'>+	struct drm_connector *connector;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='add'>+	struct amdgpu_dm_connector *sort_connector[AMDGPU_DM_MAX_CRTC] = {NULL};</div><div class='add'>+	struct drm_connector_list_iter iter;</div><div class='add'>+	uint8_t idx = 0, idx_2 = 0, connector_cnt = 0;</div><div class='add'>+</div><div class='add'>+	dm-&gt;secure_display_ctx.phy_mapping_updated = false;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ddev-&gt;mode_config.mutex);</div><div class='add'>+	drm_connector_list_iter_begin(ddev, &amp;iter);</div><div class='add'>+	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;status != connector_status_connected)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (idx &gt;= AMDGPU_DM_MAX_CRTC) {</div><div class='add'>+			DRM_WARN("%s connected connectors exceed max crtc\n", __func__);</div><div class='add'>+			mutex_unlock(&amp;ddev-&gt;mode_config.mutex);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='add'>+		sort_connector[idx] = aconnector;</div><div class='add'>+		idx++;</div><div class='add'>+		connector_cnt++;</div><div class='add'>+	}</div><div class='add'>+	drm_connector_list_iter_end(&amp;iter);</div><div class='add'>+</div><div class='add'>+	/* sort connectors by link_enc_hw_instance first */</div><div class='add'>+	for (idx = connector_cnt; idx &gt; 1 ; idx--) {</div><div class='add'>+		for (idx_2 = 0; idx_2 &lt; (idx - 1); idx_2++) {</div><div class='add'>+			if (sort_connector[idx_2]-&gt;dc_link-&gt;link_enc_hw_inst &gt;</div><div class='add'>+			    sort_connector[idx_2 + 1]-&gt;dc_link-&gt;link_enc_hw_inst)</div><div class='add'>+				swap(sort_connector[idx_2], sort_connector[idx_2 + 1]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Sort mst connectors by RAD. mst connectors with the same enc_hw_instance are already</div><div class='add'>+	 * sorted together above.</div><div class='add'>+	 */</div><div class='add'>+	for (idx = 0; idx &lt; connector_cnt; /*Do nothing*/) {</div><div class='add'>+		if (sort_connector[idx]-&gt;mst_root) {</div><div class='add'>+			uint8_t i, j, k;</div><div class='add'>+			uint8_t mst_con_cnt = 1;</div><div class='add'>+</div><div class='add'>+			for (idx_2 = (idx + 1); idx_2 &lt; connector_cnt; idx_2++) {</div><div class='add'>+				if (sort_connector[idx_2]-&gt;mst_root == sort_connector[idx]-&gt;mst_root)</div><div class='add'>+					mst_con_cnt++;</div><div class='add'>+				else</div><div class='add'>+					break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			for (i = mst_con_cnt; i &gt; 1; i--) {</div><div class='add'>+				for (j = idx; j &lt; (idx + i - 2); j++) {</div><div class='add'>+					int mstb_lct = sort_connector[j]-&gt;mst_output_port-&gt;parent-&gt;lct;</div><div class='add'>+					int next_mstb_lct = sort_connector[j + 1]-&gt;mst_output_port-&gt;parent-&gt;lct;</div><div class='add'>+					u8 *rad;</div><div class='add'>+					u8 *next_rad;</div><div class='add'>+					bool swap = false;</div><div class='add'>+</div><div class='add'>+					/* Sort by mst tree depth first. Then compare RAD if depth is the same*/</div><div class='add'>+					if (mstb_lct &gt; next_mstb_lct) {</div><div class='add'>+						swap = true;</div><div class='add'>+					} else if (mstb_lct == next_mstb_lct) {</div><div class='add'>+						if (mstb_lct == 1) {</div><div class='add'>+							if (sort_connector[j]-&gt;mst_output_port-&gt;port_num &gt; sort_connector[j + 1]-&gt;mst_output_port-&gt;port_num)</div><div class='add'>+								swap = true;</div><div class='add'>+						} else if (mstb_lct &gt; 1) {</div><div class='add'>+							rad = sort_connector[j]-&gt;mst_output_port-&gt;parent-&gt;rad;</div><div class='add'>+							next_rad = sort_connector[j + 1]-&gt;mst_output_port-&gt;parent-&gt;rad;</div><div class='add'>+</div><div class='add'>+							for (k = 0; k &lt; mstb_lct - 1; k++) {</div><div class='add'>+								int shift = (k % 2) ? 0 : 4;</div><div class='add'>+								int port_num = (rad[k / 2] &gt;&gt; shift) &amp; 0xf;</div><div class='add'>+								int next_port_num = (next_rad[k / 2] &gt;&gt; shift) &amp; 0xf;</div><div class='add'>+</div><div class='add'>+								if (port_num &gt; next_port_num) {</div><div class='add'>+									swap = true;</div><div class='add'>+									break;</div><div class='add'>+								}</div><div class='add'>+							}</div><div class='add'>+						} else {</div><div class='add'>+							DRM_ERROR("MST LCT shouldn't be set as &lt; 1");</div><div class='add'>+							mutex_unlock(&amp;ddev-&gt;mode_config.mutex);</div><div class='add'>+							return;</div><div class='add'>+						}</div><div class='add'>+					}</div><div class='add'>+</div><div class='add'>+					if (swap)</div><div class='add'>+						swap(sort_connector[j], sort_connector[j + 1]);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			idx += mst_con_cnt;</div><div class='add'>+		} else {</div><div class='add'>+			idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Complete sorting. Assign relavant result to dm-&gt;secure_display_ctx.phy_id_mapping[]*/</div><div class='add'>+	memset(dm-&gt;secure_display_ctx.phy_id_mapping, 0, sizeof(dm-&gt;secure_display_ctx.phy_id_mapping));</div><div class='add'>+	for (idx = 0; idx &lt; connector_cnt; idx++) {</div><div class='add'>+		aconnector = sort_connector[idx];</div><div class='add'>+</div><div class='add'>+		dm-&gt;secure_display_ctx.phy_id_mapping[idx].assigned = true;</div><div class='add'>+		dm-&gt;secure_display_ctx.phy_id_mapping[idx].is_mst = false;</div><div class='add'>+		dm-&gt;secure_display_ctx.phy_id_mapping[idx].enc_hw_inst = aconnector-&gt;dc_link-&gt;link_enc_hw_inst;</div><div class='add'>+</div><div class='add'>+		if (sort_connector[idx]-&gt;mst_root) {</div><div class='add'>+			dm-&gt;secure_display_ctx.phy_id_mapping[idx].is_mst = true;</div><div class='add'>+			dm-&gt;secure_display_ctx.phy_id_mapping[idx].lct = aconnector-&gt;mst_output_port-&gt;parent-&gt;lct;</div><div class='add'>+			dm-&gt;secure_display_ctx.phy_id_mapping[idx].port_num = aconnector-&gt;mst_output_port-&gt;port_num;</div><div class='add'>+			memcpy(dm-&gt;secure_display_ctx.phy_id_mapping[idx].rad,</div><div class='add'>+				aconnector-&gt;mst_output_port-&gt;parent-&gt;rad, sizeof(aconnector-&gt;mst_output_port-&gt;parent-&gt;rad));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;ddev-&gt;mode_config.mutex);</div><div class='add'>+</div><div class='add'>+	dm-&gt;secure_display_ctx.phy_id_mapping_cnt = connector_cnt;</div><div class='add'>+	dm-&gt;secure_display_ctx.phy_mapping_updated = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool get_phy_id(struct amdgpu_display_manager *dm,</div><div class='add'>+			struct amdgpu_dm_connector *aconnector, uint8_t *phy_id)</div><div class='add'>+{</div><div class='add'>+	int idx, idx_2;</div><div class='add'>+	bool found = false;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Assume secure display start after all connectors are probed. The connection</div><div class='add'>+	 * config is static as well</div><div class='add'>+	 */</div><div class='add'>+	if (!dm-&gt;secure_display_ctx.phy_mapping_updated) {</div><div class='add'>+		DRM_WARN("%s Should update the phy id table before get it's value", __func__);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (idx = 0; idx &lt; dm-&gt;secure_display_ctx.phy_id_mapping_cnt; idx++) {</div><div class='add'>+		if (!dm-&gt;secure_display_ctx.phy_id_mapping[idx].assigned) {</div><div class='add'>+			DRM_ERROR("phy_id_mapping[%d] should be assigned", idx);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (aconnector-&gt;dc_link-&gt;link_enc_hw_inst ==</div><div class='add'>+				dm-&gt;secure_display_ctx.phy_id_mapping[idx].enc_hw_inst) {</div><div class='add'>+			if (!dm-&gt;secure_display_ctx.phy_id_mapping[idx].is_mst) {</div><div class='add'>+				found = true;</div><div class='add'>+				goto out;</div><div class='add'>+			} else {</div><div class='add'>+				/* Could caused by wrongly pass mst root connector */</div><div class='add'>+				if (!aconnector-&gt;mst_output_port) {</div><div class='add'>+					DRM_ERROR("%s Check mst case but connector without a port assigned", __func__);</div><div class='add'>+					return false;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if (aconnector-&gt;mst_root &amp;&amp;</div><div class='add'>+					aconnector-&gt;mst_root-&gt;mst_mgr.mst_primary == NULL) {</div><div class='add'>+					DRM_WARN("%s pass in a stale mst connector", __func__);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if (aconnector-&gt;mst_output_port-&gt;parent-&gt;lct == dm-&gt;secure_display_ctx.phy_id_mapping[idx].lct &amp;&amp;</div><div class='add'>+					aconnector-&gt;mst_output_port-&gt;port_num == dm-&gt;secure_display_ctx.phy_id_mapping[idx].port_num) {</div><div class='add'>+					if (aconnector-&gt;mst_output_port-&gt;parent-&gt;lct == 1) {</div><div class='add'>+						found = true;</div><div class='add'>+						goto out;</div><div class='add'>+					} else if (aconnector-&gt;mst_output_port-&gt;parent-&gt;lct &gt; 1) {</div><div class='add'>+						/* Check RAD */</div><div class='add'>+						for (idx_2 = 0; idx_2 &lt; aconnector-&gt;mst_output_port-&gt;parent-&gt;lct - 1; idx_2++) {</div><div class='add'>+							int shift = (idx_2 % 2) ? 0 : 4;</div><div class='add'>+							int port_num = (aconnector-&gt;mst_output_port-&gt;parent-&gt;rad[idx_2 / 2] &gt;&gt; shift) &amp; 0xf;</div><div class='add'>+							int port_num2 = (dm-&gt;secure_display_ctx.phy_id_mapping[idx].rad[idx_2 / 2] &gt;&gt; shift) &amp; 0xf;</div><div class='add'>+</div><div class='add'>+							if (port_num != port_num2)</div><div class='add'>+								break;</div><div class='add'>+						}</div><div class='add'>+</div><div class='add'>+						if (idx_2 == aconnector-&gt;mst_output_port-&gt;parent-&gt;lct - 1) {</div><div class='add'>+							found = true;</div><div class='add'>+							goto out;</div><div class='add'>+						}</div><div class='add'>+					} else {</div><div class='add'>+						DRM_ERROR("lCT should be &gt;= 1");</div><div class='add'>+						return false;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	if (found) {</div><div class='add'>+		DRM_DEBUG_DRIVER("Associated secure display PHY ID as %d", idx);</div><div class='add'>+		*phy_id = idx;</div><div class='add'>+	} else {</div><div class='add'>+		DRM_WARN("Can't find associated phy ID");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *drm_dev = crtc-&gt;dev;</div><div class='ctx'> 	struct amdgpu_display_manager *dm = &amp;drm_to_adev(drm_dev)-&gt;dm;</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	bool was_activated;</div><div class='add'>+	uint8_t phy_id;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	was_activated = acrtc-&gt;dm_irq_params.window_param.activated;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.x_start = 0;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.y_start = 0;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.x_end = 0;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.y_end = 0;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.activated = false;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.update_win = false;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.skip_frame_cnt = 0;</div><div class='del'>-	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='add'>+	spin_lock_irqsave(&amp;drm_dev-&gt;event_lock, flags);</div><div class='add'>+	was_activated = acrtc-&gt;dm_irq_params.crc_window_activated;</div><div class='add'>+	for (i = 0; i &lt; MAX_CRC_WINDOW_NUM; i++) {</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].x_start = 0;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].y_start = 0;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].x_end = 0;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].y_end = 0;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].enable = false;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].update_win = false;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[i].skip_frame_cnt = 0;</div><div class='add'>+	}</div><div class='add'>+	acrtc-&gt;dm_irq_params.crc_window_activated = false;</div><div class='add'>+	spin_unlock_irqrestore(&amp;drm_dev-&gt;event_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	/* Disable secure_display if it was enabled */</div><div class='del'>-	if (was_activated) {</div><div class='add'>+	if (was_activated &amp;&amp; dm-&gt;secure_display_ctx.op_mode == LEGACY_MODE) {</div><div class='ctx'> 		/* stop ROI update on this crtc */</div><div class='del'>-		flush_work(&amp;dm-&gt;secure_display_ctxs[crtc-&gt;index].notify_ta_work);</div><div class='del'>-		flush_work(&amp;dm-&gt;secure_display_ctxs[crtc-&gt;index].forward_roi_work);</div><div class='del'>-		dc_stream_forward_crc_window(stream, NULL, true);</div><div class='add'>+		flush_work(&amp;dm-&gt;secure_display_ctx.crtc_ctx[crtc-&gt;index].notify_ta_work);</div><div class='add'>+		flush_work(&amp;dm-&gt;secure_display_ctx.crtc_ctx[crtc-&gt;index].forward_roi_work);</div><div class='add'>+		aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='add'>+</div><div class='add'>+		if (aconnector &amp;&amp; get_phy_id(dm, aconnector, &amp;phy_id)) {</div><div class='add'>+			if (dm-&gt;secure_display_ctx.support_mul_roi)</div><div class='add'>+				dc_stream_forward_multiple_crc_window(stream, NULL, phy_id, true);</div><div class='add'>+			else</div><div class='add'>+				dc_stream_forward_crc_window(stream, NULL, phy_id, true);</div><div class='add'>+		} else {</div><div class='add'>+			DRM_DEBUG_DRIVER("%s Can't find matching phy id", __func__);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)</div><div class='ctx'> {</div><div class='del'>-	struct secure_display_context *secure_display_ctx;</div><div class='add'>+	struct secure_display_crtc_context *crtc_ctx;</div><div class='ctx'> 	struct psp_context *psp;</div><div class='ctx'> 	struct ta_securedisplay_cmd *securedisplay_cmd;</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	uint8_t phy_inst;</div><div class='add'>+	struct amdgpu_display_manager *dm;</div><div class='add'>+	struct crc_data crc_cpy[MAX_CRC_WINDOW_NUM];</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	uint8_t roi_idx = 0;</div><div class='ctx'> 	int ret;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work);</div><div class='del'>-	crtc = secure_display_ctx-&gt;crtc;</div><div class='add'>+	crtc_ctx = container_of(work, struct secure_display_crtc_context, notify_ta_work);</div><div class='add'>+	crtc = crtc_ctx-&gt;crtc;</div><div class='ctx'> </div><div class='ctx'> 	if (!crtc)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -133,21 +364,50 @@ static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	dm = &amp;drm_to_adev(crtc-&gt;dev)-&gt;dm;</div><div class='ctx'> 	stream = to_amdgpu_crtc(crtc)-&gt;dm_irq_params.stream;</div><div class='del'>-	phy_inst = stream-&gt;link-&gt;link_enc_hw_inst;</div><div class='del'>-</div><div class='del'>-	/* need lock for multiple crtcs to use the command buffer */</div><div class='del'>-	mutex_lock(&amp;psp-&gt;securedisplay_context.mutex);</div><div class='add'>+	aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='add'>+	if (!aconnector)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	psp_prep_securedisplay_cmd_buf(psp, &amp;securedisplay_cmd,</div><div class='del'>-						TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);</div><div class='add'>+	mutex_lock(&amp;crtc-&gt;dev-&gt;mode_config.mutex);</div><div class='add'>+	if (!get_phy_id(dm, aconnector, &amp;phy_inst)) {</div><div class='add'>+		DRM_WARN("%s Can't find mapping phy id!", __func__);</div><div class='add'>+		mutex_unlock(&amp;crtc-&gt;dev-&gt;mode_config.mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;crtc-&gt;dev-&gt;mode_config.mutex);</div><div class='ctx'> </div><div class='del'>-	securedisplay_cmd-&gt;securedisplay_in_message.send_roi_crc.phy_id = phy_inst;</div><div class='add'>+	spin_lock_irqsave(&amp;crtc-&gt;dev-&gt;event_lock, flags);</div><div class='add'>+	memcpy(crc_cpy, crtc_ctx-&gt;crc_info.crc, sizeof(struct crc_data) * MAX_CRC_WINDOW_NUM);</div><div class='add'>+	spin_unlock_irqrestore(&amp;crtc-&gt;dev-&gt;event_lock, flags);</div><div class='ctx'> </div><div class='add'>+	/* need lock for multiple crtcs to use the command buffer */</div><div class='add'>+	mutex_lock(&amp;psp-&gt;securedisplay_context.mutex);</div><div class='ctx'> 	/* PSP TA is expected to finish data transmission over I2C within current frame,</div><div class='ctx'> 	 * even there are up to 4 crtcs request to send in this frame.</div><div class='ctx'> 	 */</div><div class='del'>-	ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);</div><div class='add'>+	if (dm-&gt;secure_display_ctx.support_mul_roi) {</div><div class='add'>+		psp_prep_securedisplay_cmd_buf(psp, &amp;securedisplay_cmd,</div><div class='add'>+							TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2);</div><div class='add'>+</div><div class='add'>+		securedisplay_cmd-&gt;securedisplay_in_message.send_roi_crc_v2.phy_id = phy_inst;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; MAX_CRC_WINDOW_NUM; i++) {</div><div class='add'>+			if (crc_cpy[i].crc_ready)</div><div class='add'>+				roi_idx |= 1 &lt;&lt; i;</div><div class='add'>+		}</div><div class='add'>+		securedisplay_cmd-&gt;securedisplay_in_message.send_roi_crc_v2.roi_idx = roi_idx;</div><div class='add'>+</div><div class='add'>+		ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2);</div><div class='add'>+	} else {</div><div class='add'>+		psp_prep_securedisplay_cmd_buf(psp, &amp;securedisplay_cmd,</div><div class='add'>+							TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);</div><div class='add'>+</div><div class='add'>+		securedisplay_cmd-&gt;securedisplay_in_message.send_roi_crc.phy_id = phy_inst;</div><div class='add'>+</div><div class='add'>+		ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		if (securedisplay_cmd-&gt;status != TA_SECUREDISPLAY_STATUS__SUCCESS)</div><div class='hunk'>@@ -160,22 +420,47 @@ static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)</div><div class='ctx'> static void</div><div class='ctx'> amdgpu_dm_forward_crc_window(struct work_struct *work)</div><div class='ctx'> {</div><div class='del'>-	struct secure_display_context *secure_display_ctx;</div><div class='add'>+	struct secure_display_crtc_context *crtc_ctx;</div><div class='ctx'> 	struct amdgpu_display_manager *dm;</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='add'>+	struct crc_window roi_cpy[MAX_CRC_WINDOW_NUM];</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	uint8_t phy_id;</div><div class='ctx'> </div><div class='del'>-	secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work);</div><div class='del'>-	crtc = secure_display_ctx-&gt;crtc;</div><div class='add'>+	crtc_ctx = container_of(work, struct secure_display_crtc_context, forward_roi_work);</div><div class='add'>+	crtc = crtc_ctx-&gt;crtc;</div><div class='ctx'> </div><div class='ctx'> 	if (!crtc)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	dm = &amp;drm_to_adev(crtc-&gt;dev)-&gt;dm;</div><div class='ctx'> 	stream = to_amdgpu_crtc(crtc)-&gt;dm_irq_params.stream;</div><div class='add'>+	aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='add'>+</div><div class='add'>+	if (!aconnector)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;crtc-&gt;dev-&gt;mode_config.mutex);</div><div class='add'>+	if (!get_phy_id(dm, aconnector, &amp;phy_id)) {</div><div class='add'>+		DRM_WARN("%s Can't find mapping phy id!", __func__);</div><div class='add'>+		mutex_unlock(&amp;crtc-&gt;dev-&gt;mode_config.mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;crtc-&gt;dev-&gt;mode_config.mutex);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;crtc-&gt;dev-&gt;event_lock, flags);</div><div class='add'>+	memcpy(roi_cpy, crtc_ctx-&gt;roi, sizeof(struct crc_window) * MAX_CRC_WINDOW_NUM);</div><div class='add'>+	spin_unlock_irqrestore(&amp;crtc-&gt;dev-&gt;event_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='del'>-	dc_stream_forward_crc_window(stream, &amp;secure_display_ctx-&gt;rect, false);</div><div class='add'>+	if (dm-&gt;secure_display_ctx.support_mul_roi)</div><div class='add'>+		dc_stream_forward_multiple_crc_window(stream, roi_cpy,</div><div class='add'>+			phy_id, false);</div><div class='add'>+	else</div><div class='add'>+		dc_stream_forward_crc_window(stream, &amp;roi_cpy[0].rect,</div><div class='add'>+			phy_id, false);</div><div class='ctx'> 	mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -186,7 +471,7 @@ bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	ret = acrtc-&gt;dm_irq_params.window_param.activated;</div><div class='add'>+	ret = acrtc-&gt;dm_irq_params.crc_window_activated;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -224,10 +509,14 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='ctx'> </div><div class='add'>+	/* For PSR1, check that the panel has exited PSR */</div><div class='add'>+	if (stream_state-&gt;link-&gt;psr_settings.psr_version &lt; DC_PSR_VERSION_SU_1)</div><div class='add'>+		amdgpu_dm_psr_wait_disable(stream_state);</div><div class='add'>+</div><div class='ctx'> 	/* Enable or disable CRTC CRC generation */</div><div class='ctx'> 	if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {</div><div class='ctx'> 		if (!dc_stream_configure_crc(stream_state-&gt;ctx-&gt;dc,</div><div class='del'>-					     stream_state, NULL, enable, enable)) {</div><div class='add'>+					     stream_state, NULL, enable, enable, 0, true)) {</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto unlock;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -258,6 +547,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)</div><div class='ctx'> 	struct drm_crtc_commit *commit;</div><div class='ctx'> 	struct dm_crtc_state *crtc_state;</div><div class='ctx'> 	struct drm_device *drm_dev = crtc-&gt;dev;</div><div class='add'>+#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(drm_dev);</div><div class='add'>+	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='add'>+#endif</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> 	struct drm_dp_aux *aux = NULL;</div><div class='ctx'> 	bool enable = false;</div><div class='hunk'>@@ -357,6 +650,17 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Reading the CRC requires the vblank interrupt handler to be</div><div class='add'>+	 * enabled. Keep a reference until CRC capture stops.</div><div class='add'>+	 */</div><div class='add'>+	enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);</div><div class='add'>+	if (!enabled &amp;&amp; enable) {</div><div class='add'>+		ret = drm_crtc_vblank_get(crtc);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='ctx'> 	/* Reset secure_display when we change crc source from debugfs */</div><div class='ctx'> 	amdgpu_dm_set_crc_window_default(crtc, crtc_state-&gt;stream);</div><div class='hunk'>@@ -367,16 +671,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)</div><div class='ctx'> 		goto cleanup;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Reading the CRC requires the vblank interrupt handler to be</div><div class='del'>-	 * enabled. Keep a reference until CRC capture stops.</div><div class='del'>-	 */</div><div class='del'>-	enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);</div><div class='ctx'> 	if (!enabled &amp;&amp; enable) {</div><div class='del'>-		ret = drm_crtc_vblank_get(crtc);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto cleanup;</div><div class='del'>-</div><div class='ctx'> 		if (dm_is_crc_source_dprx(source)) {</div><div class='ctx'> 			if (drm_dp_start_crc(aux, crtc)) {</div><div class='ctx'> 				DRM_DEBUG_DRIVER("dp start crc failed\n");</div><div class='hunk'>@@ -402,6 +697,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)</div><div class='ctx'> 	/* Reset crc_skipped on dm state */</div><div class='ctx'> 	crtc_state-&gt;crc_skip_count = 0;</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='add'>+	/* Initialize phy id mapping table for secure display*/</div><div class='add'>+	if (dm-&gt;secure_display_ctx.op_mode == LEGACY_MODE &amp;&amp;</div><div class='add'>+		!dm-&gt;secure_display_ctx.phy_mapping_updated)</div><div class='add'>+		update_phy_id_mapping(adev);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> cleanup:</div><div class='ctx'> 	if (commit)</div><div class='ctx'> 		drm_crtc_commit_put(commit);</div><div class='hunk'>@@ -456,7 +758,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dm_is_crc_source_crtc(cur_crc_src)) {</div><div class='del'>-		if (!dc_stream_get_crc(stream_state-&gt;ctx-&gt;dc, stream_state,</div><div class='add'>+		if (!dc_stream_get_crc(stream_state-&gt;ctx-&gt;dc, stream_state, 0,</div><div class='ctx'> 				       &amp;crcs[0], &amp;crcs[1], &amp;crcs[2]))</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='hunk'>@@ -472,8 +774,17 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)</div><div class='ctx'> 	enum amdgpu_dm_pipe_crc_source cur_crc_src;</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = NULL;</div><div class='ctx'> 	struct amdgpu_device *adev = NULL;</div><div class='del'>-	struct secure_display_context *secure_display_ctx = NULL;</div><div class='add'>+	struct secure_display_crtc_context *crtc_ctx = NULL;</div><div class='add'>+	bool reset_crc_frame_count[MAX_CRC_WINDOW_NUM] = {false};</div><div class='add'>+	uint32_t crc_r[MAX_CRC_WINDOW_NUM] = {0};</div><div class='add'>+	uint32_t crc_g[MAX_CRC_WINDOW_NUM] = {0};</div><div class='add'>+	uint32_t crc_b[MAX_CRC_WINDOW_NUM] = {0};</div><div class='ctx'> 	unsigned long flags1;</div><div class='add'>+	bool forward_roi_change = false;</div><div class='add'>+	bool notify_ta = false;</div><div class='add'>+	bool all_crc_ready = true;</div><div class='add'>+	struct dc_stream_state *stream_state;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (crtc == NULL)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -481,78 +792,160 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)</div><div class='ctx'> 	acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> 	adev = drm_to_adev(crtc-&gt;dev);</div><div class='ctx'> 	drm_dev = crtc-&gt;dev;</div><div class='add'>+	stream_state = to_dm_crtc_state(crtc-&gt;state)-&gt;stream;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;drm_dev-&gt;event_lock, flags1);</div><div class='ctx'> 	cur_crc_src = acrtc-&gt;dm_irq_params.crc_src;</div><div class='ctx'> </div><div class='ctx'> 	/* Early return if CRC capture is not enabled. */</div><div class='ctx'> 	if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) ||</div><div class='del'>-		!dm_is_crc_source_crtc(cur_crc_src))</div><div class='del'>-		goto cleanup;</div><div class='del'>-</div><div class='del'>-	if (!acrtc-&gt;dm_irq_params.window_param.activated)</div><div class='del'>-		goto cleanup;</div><div class='add'>+	    !dm_is_crc_source_crtc(cur_crc_src)) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;drm_dev-&gt;event_lock, flags1);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (acrtc-&gt;dm_irq_params.window_param.skip_frame_cnt) {</div><div class='del'>-		acrtc-&gt;dm_irq_params.window_param.skip_frame_cnt -= 1;</div><div class='del'>-		goto cleanup;</div><div class='add'>+	if (!acrtc-&gt;dm_irq_params.crc_window_activated) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;drm_dev-&gt;event_lock, flags1);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	secure_display_ctx = &amp;adev-&gt;dm.secure_display_ctxs[acrtc-&gt;crtc_id];</div><div class='del'>-	if (WARN_ON(secure_display_ctx-&gt;crtc != crtc)) {</div><div class='del'>-		/* We have set the crtc when creating secure_display_context,</div><div class='add'>+	crtc_ctx = &amp;adev-&gt;dm.secure_display_ctx.crtc_ctx[acrtc-&gt;crtc_id];</div><div class='add'>+	if (WARN_ON(crtc_ctx-&gt;crtc != crtc)) {</div><div class='add'>+		/* We have set the crtc when creating secure_display_crtc_context,</div><div class='ctx'> 		 * don't expect it to be changed here.</div><div class='ctx'> 		 */</div><div class='del'>-		secure_display_ctx-&gt;crtc = crtc;</div><div class='add'>+		crtc_ctx-&gt;crtc = crtc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (acrtc-&gt;dm_irq_params.window_param.update_win) {</div><div class='del'>-		/* prepare work for dmub to update ROI */</div><div class='del'>-		secure_display_ctx-&gt;rect.x = acrtc-&gt;dm_irq_params.window_param.x_start;</div><div class='del'>-		secure_display_ctx-&gt;rect.y = acrtc-&gt;dm_irq_params.window_param.y_start;</div><div class='del'>-		secure_display_ctx-&gt;rect.width = acrtc-&gt;dm_irq_params.window_param.x_end -</div><div class='del'>-								acrtc-&gt;dm_irq_params.window_param.x_start;</div><div class='del'>-		secure_display_ctx-&gt;rect.height = acrtc-&gt;dm_irq_params.window_param.y_end -</div><div class='del'>-								acrtc-&gt;dm_irq_params.window_param.y_start;</div><div class='del'>-		schedule_work(&amp;secure_display_ctx-&gt;forward_roi_work);</div><div class='del'>-</div><div class='del'>-		acrtc-&gt;dm_irq_params.window_param.update_win = false;</div><div class='add'>+	for (i = 0; i &lt; MAX_CRC_WINDOW_NUM; i++) {</div><div class='add'>+		struct crc_params crc_window = {</div><div class='add'>+			.windowa_x_start = acrtc-&gt;dm_irq_params.window_param[i].x_start,</div><div class='add'>+			.windowa_y_start = acrtc-&gt;dm_irq_params.window_param[i].y_start,</div><div class='add'>+			.windowa_x_end = acrtc-&gt;dm_irq_params.window_param[i].x_end,</div><div class='add'>+			.windowa_y_end = acrtc-&gt;dm_irq_params.window_param[i].y_end,</div><div class='add'>+			.windowb_x_start = acrtc-&gt;dm_irq_params.window_param[i].x_start,</div><div class='add'>+			.windowb_y_start = acrtc-&gt;dm_irq_params.window_param[i].y_start,</div><div class='add'>+			.windowb_x_end = acrtc-&gt;dm_irq_params.window_param[i].x_end,</div><div class='add'>+			.windowb_y_end = acrtc-&gt;dm_irq_params.window_param[i].y_end,</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		crtc_ctx-&gt;roi[i].enable = acrtc-&gt;dm_irq_params.window_param[i].enable;</div><div class='add'>+</div><div class='add'>+		if (!acrtc-&gt;dm_irq_params.window_param[i].enable) {</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].crc_ready = false;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		/* Statically skip 1 frame, because we may need to wait below things</div><div class='del'>-		 * before sending ROI to dmub:</div><div class='del'>-		 * 1. We defer the work by using system workqueue.</div><div class='del'>-		 * 2. We may need to wait for dc_lock before accessing dmub.</div><div class='del'>-		 */</div><div class='del'>-		acrtc-&gt;dm_irq_params.window_param.skip_frame_cnt = 1;</div><div class='add'>+		if (acrtc-&gt;dm_irq_params.window_param[i].skip_frame_cnt) {</div><div class='add'>+			acrtc-&gt;dm_irq_params.window_param[i].skip_frame_cnt -= 1;</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].crc_ready = false;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	} else {</div><div class='del'>-		/* prepare work for psp to read ROI/CRC and send to I2C */</div><div class='del'>-		schedule_work(&amp;secure_display_ctx-&gt;notify_ta_work);</div><div class='add'>+		if (acrtc-&gt;dm_irq_params.window_param[i].update_win) {</div><div class='add'>+			crtc_ctx-&gt;roi[i].rect.x = crc_window.windowa_x_start;</div><div class='add'>+			crtc_ctx-&gt;roi[i].rect.y = crc_window.windowa_y_start;</div><div class='add'>+			crtc_ctx-&gt;roi[i].rect.width = crc_window.windowa_x_end -</div><div class='add'>+						crc_window.windowa_x_start;</div><div class='add'>+			crtc_ctx-&gt;roi[i].rect.height = crc_window.windowa_y_end -</div><div class='add'>+						crc_window.windowa_y_start;</div><div class='add'>+</div><div class='add'>+			if (adev-&gt;dm.secure_display_ctx.op_mode == LEGACY_MODE)</div><div class='add'>+				/* forward task to dmub to update ROI */</div><div class='add'>+				forward_roi_change = true;</div><div class='add'>+			else if (adev-&gt;dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE)</div><div class='add'>+				/* update ROI via dm*/</div><div class='add'>+				dc_stream_configure_crc(stream_state-&gt;ctx-&gt;dc, stream_state,</div><div class='add'>+					&amp;crc_window, true, true, i, false);</div><div class='add'>+</div><div class='add'>+			reset_crc_frame_count[i] = true;</div><div class='add'>+</div><div class='add'>+			acrtc-&gt;dm_irq_params.window_param[i].update_win = false;</div><div class='add'>+</div><div class='add'>+			/* Statically skip 1 frame, because we may need to wait below things</div><div class='add'>+			 * before sending ROI to dmub:</div><div class='add'>+			 * 1. We defer the work by using system workqueue.</div><div class='add'>+			 * 2. We may need to wait for dc_lock before accessing dmub.</div><div class='add'>+			 */</div><div class='add'>+			acrtc-&gt;dm_irq_params.window_param[i].skip_frame_cnt = 1;</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].crc_ready = false;</div><div class='add'>+		} else {</div><div class='add'>+			if (!dc_stream_get_crc(stream_state-&gt;ctx-&gt;dc, stream_state, i,</div><div class='add'>+						&amp;crc_r[i], &amp;crc_g[i], &amp;crc_b[i]))</div><div class='add'>+				DRM_ERROR("Secure Display: fail to get crc from engine %d\n", i);</div><div class='add'>+</div><div class='add'>+			if (adev-&gt;dm.secure_display_ctx.op_mode == LEGACY_MODE)</div><div class='add'>+				/* forward task to psp to read ROI/CRC and output via I2C */</div><div class='add'>+				notify_ta = true;</div><div class='add'>+			else if (adev-&gt;dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE)</div><div class='add'>+				/* Avoid ROI window get changed, keep overwriting. */</div><div class='add'>+				dc_stream_configure_crc(stream_state-&gt;ctx-&gt;dc, stream_state,</div><div class='add'>+						&amp;crc_window, true, true, i, false);</div><div class='add'>+</div><div class='add'>+			/* crc ready for psp to read out */</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].crc_ready = true;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-cleanup:</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;drm_dev-&gt;event_lock, flags1);</div><div class='add'>+</div><div class='add'>+	if (forward_roi_change)</div><div class='add'>+		schedule_work(&amp;crtc_ctx-&gt;forward_roi_work);</div><div class='add'>+</div><div class='add'>+	if (notify_ta)</div><div class='add'>+		schedule_work(&amp;crtc_ctx-&gt;notify_ta_work);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;crtc_ctx-&gt;crc_info.lock, flags1);</div><div class='add'>+	for (i = 0; i &lt; MAX_CRC_WINDOW_NUM; i++) {</div><div class='add'>+		crtc_ctx-&gt;crc_info.crc[i].crc_R = crc_r[i];</div><div class='add'>+		crtc_ctx-&gt;crc_info.crc[i].crc_G = crc_g[i];</div><div class='add'>+		crtc_ctx-&gt;crc_info.crc[i].crc_B = crc_b[i];</div><div class='add'>+</div><div class='add'>+		if (!crtc_ctx-&gt;roi[i].enable) {</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].frame_count = 0;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!crtc_ctx-&gt;crc_info.crc[i].crc_ready)</div><div class='add'>+			all_crc_ready = false;</div><div class='add'>+</div><div class='add'>+		if (reset_crc_frame_count[i] || crtc_ctx-&gt;crc_info.crc[i].frame_count == UINT_MAX)</div><div class='add'>+			/* Reset the reference frame count after user update the ROI</div><div class='add'>+			 * or it reaches the maximum value.</div><div class='add'>+			 */</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].frame_count = 0;</div><div class='add'>+		else</div><div class='add'>+			crtc_ctx-&gt;crc_info.crc[i].frame_count += 1;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;crtc_ctx-&gt;crc_info.lock, flags1);</div><div class='add'>+</div><div class='add'>+	if (all_crc_ready)</div><div class='add'>+		complete_all(&amp;crtc_ctx-&gt;crc_info.completion);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct secure_display_context *</div><div class='del'>-amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-	struct secure_display_context *secure_display_ctxs = NULL;</div><div class='add'>+	struct secure_display_crtc_context *crtc_ctx = NULL;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	secure_display_ctxs = kcalloc(adev-&gt;mode_info.num_crtc,</div><div class='del'>-				      sizeof(struct secure_display_context),</div><div class='add'>+	crtc_ctx = kcalloc(adev-&gt;mode_info.num_crtc,</div><div class='add'>+				      sizeof(struct secure_display_crtc_context),</div><div class='ctx'> 				      GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!secure_display_ctxs)</div><div class='del'>-		return NULL;</div><div class='add'>+	if (!crtc_ctx) {</div><div class='add'>+		adev-&gt;dm.secure_display_ctx.crtc_ctx = NULL;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;mode_info.num_crtc; i++) {</div><div class='del'>-		INIT_WORK(&amp;secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window);</div><div class='del'>-		INIT_WORK(&amp;secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);</div><div class='del'>-		secure_display_ctxs[i].crtc = &amp;adev-&gt;mode_info.crtcs[i]-&gt;base;</div><div class='add'>+		INIT_WORK(&amp;crtc_ctx[i].forward_roi_work, amdgpu_dm_forward_crc_window);</div><div class='add'>+		INIT_WORK(&amp;crtc_ctx[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);</div><div class='add'>+		crtc_ctx[i].crtc = &amp;adev-&gt;mode_info.crtcs[i]-&gt;base;</div><div class='add'>+		spin_lock_init(&amp;crtc_ctx[i].crc_info.lock);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return secure_display_ctxs;</div><div class='add'>+	adev-&gt;dm.secure_display_ctx.crtc_ctx = crtc_ctx;</div><div class='add'>+</div><div class='add'>+	adev-&gt;dm.secure_display_ctx.op_mode = DISPLAY_CRC_MODE;</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h<br/>index 748e80ef40d0..95bdb8699d7f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -40,20 +41,53 @@ enum amdgpu_dm_pipe_crc_source {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='add'>+#define MAX_CRTC 6</div><div class='add'>+</div><div class='add'>+enum secure_display_mode {</div><div class='add'>+	/* via dmub + psp */</div><div class='add'>+	LEGACY_MODE = 0,</div><div class='add'>+	/* driver directly */</div><div class='add'>+	DISPLAY_CRC_MODE,</div><div class='add'>+	SECURE_DISPLAY_MODE_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct phy_id_mapping {</div><div class='add'>+	bool assigned;</div><div class='add'>+	bool is_mst;</div><div class='add'>+	uint8_t enc_hw_inst;</div><div class='add'>+	u8 lct;</div><div class='add'>+	u8 port_num;</div><div class='add'>+	u8 rad[8];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct crc_data {</div><div class='add'>+	uint32_t crc_R;</div><div class='add'>+	uint32_t crc_G;</div><div class='add'>+	uint32_t crc_B;</div><div class='add'>+	uint32_t frame_count;</div><div class='add'>+	bool crc_ready;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct crc_info {</div><div class='add'>+	struct crc_data crc[MAX_CRC_WINDOW_NUM];</div><div class='add'>+	struct completion completion;</div><div class='add'>+	spinlock_t lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct crc_window_param {</div><div class='ctx'> 	uint16_t x_start;</div><div class='ctx'> 	uint16_t y_start;</div><div class='ctx'> 	uint16_t x_end;</div><div class='ctx'> 	uint16_t y_end;</div><div class='ctx'> 	/* CRC window is activated or not*/</div><div class='del'>-	bool activated;</div><div class='add'>+	bool enable;</div><div class='ctx'> 	/* Update crc window during vertical blank or not */</div><div class='ctx'> 	bool update_win;</div><div class='ctx'> 	/* skip reading/writing for few frames */</div><div class='ctx'> 	int skip_frame_cnt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct secure_display_context {</div><div class='add'>+struct secure_display_crtc_context {</div><div class='ctx'> 	/* work to notify PSP TA*/</div><div class='ctx'> 	struct work_struct notify_ta_work;</div><div class='ctx'> </div><div class='hunk'>@@ -63,7 +97,20 @@ struct secure_display_context {</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> </div><div class='ctx'> 	/* Region of Interest (ROI) */</div><div class='del'>-	struct rect rect;</div><div class='add'>+	struct crc_window roi[MAX_CRC_WINDOW_NUM];</div><div class='add'>+</div><div class='add'>+	struct crc_info crc_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct secure_display_context {</div><div class='add'>+</div><div class='add'>+	struct secure_display_crtc_context *crtc_ctx;</div><div class='add'>+    /* Whether dmub support multiple ROI setting */</div><div class='add'>+	bool support_mul_roi;</div><div class='add'>+	enum secure_display_mode op_mode;</div><div class='add'>+	bool phy_mapping_updated;</div><div class='add'>+	int phy_id_mapping_cnt;</div><div class='add'>+	struct phy_id_mapping phy_id_mapping[MAX_CRTC];</div><div class='ctx'> };</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -95,8 +142,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);</div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='ctx'> bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);</div><div class='ctx'> void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);</div><div class='del'>-struct secure_display_context *amdgpu_dm_crtc_secure_display_create_contexts(</div><div class='del'>-						struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev);</div><div class='ctx'> #else</div><div class='ctx'> #define amdgpu_dm_crc_window_is_activated(x)</div><div class='ctx'> #define amdgpu_dm_crtc_handle_crc_window_irq(x)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c<br/>index e23a0a276e33..697e232acebf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c</a></div><div class='hunk'>@@ -35,6 +35,9 @@</div><div class='ctx'> #include "amdgpu_dm_trace.h"</div><div class='ctx'> #include "amdgpu_dm_debugfs.h"</div><div class='ctx'> </div><div class='add'>+#define HPD_DETECTION_PERIOD_uS 2000000</div><div class='add'>+#define HPD_DETECTION_TIME_uS 100000</div><div class='add'>+</div><div class='ctx'> void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_crtc *crtc = &amp;acrtc-&gt;base;</div><div class='hunk'>@@ -90,7 +93,7 @@ int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)</div><div class='add'>+bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)</div><div class='ctx'> {</div><div class='ctx'> 	return dm_state-&gt;freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||</div><div class='ctx'> 	       dm_state-&gt;freesync_config.state == VRR_STATE_ACTIVE_FIXED;</div><div class='hunk'>@@ -110,6 +113,7 @@ bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)</div><div class='ctx'>  *</div><div class='ctx'>  * Panel Replay and PSR SU</div><div class='ctx'>  * - Enable when:</div><div class='add'>+ *      - VRR is disabled</div><div class='ctx'>  *      - vblank counter is disabled</div><div class='ctx'>  *      - entry is allowed: usermode demonstrates an adequate number of fast</div><div class='ctx'>  *        commits)</div><div class='hunk'>@@ -128,27 +132,115 @@ static void amdgpu_dm_crtc_set_panel_sr_feature(</div><div class='ctx'> 	bool is_sr_active = (link-&gt;replay_settings.replay_allow_active ||</div><div class='ctx'> 				 link-&gt;psr_settings.psr_allow_active);</div><div class='ctx'> 	bool is_crc_window_active = false;</div><div class='add'>+	bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work-&gt;acrtc);</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='ctx'> 	is_crc_window_active =</div><div class='ctx'> 		amdgpu_dm_crc_window_is_activated(&amp;vblank_work-&gt;acrtc-&gt;base);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;replay_settings.replay_feature_enabled &amp;&amp;</div><div class='add'>+	if (link-&gt;replay_settings.replay_feature_enabled &amp;&amp; !vrr_active &amp;&amp;</div><div class='ctx'> 		allow_sr_entry &amp;&amp; !is_sr_active &amp;&amp; !is_crc_window_active) {</div><div class='ctx'> 		amdgpu_dm_replay_enable(vblank_work-&gt;stream, true);</div><div class='ctx'> 	} else if (vblank_enabled) {</div><div class='ctx'> 		if (link-&gt;psr_settings.psr_version &lt; DC_PSR_VERSION_SU_1 &amp;&amp; is_sr_active)</div><div class='del'>-			amdgpu_dm_psr_disable(vblank_work-&gt;stream);</div><div class='del'>-	} else if (link-&gt;psr_settings.psr_feature_enabled &amp;&amp;</div><div class='add'>+			amdgpu_dm_psr_disable(vblank_work-&gt;stream, false);</div><div class='add'>+	} else if (link-&gt;psr_settings.psr_feature_enabled &amp;&amp; !vrr_active &amp;&amp;</div><div class='ctx'> 		allow_sr_entry &amp;&amp; !is_sr_active &amp;&amp; !is_crc_window_active) {</div><div class='ctx'> </div><div class='ctx'> 		struct amdgpu_dm_connector *aconn =</div><div class='ctx'> 			(struct amdgpu_dm_connector *) vblank_work-&gt;stream-&gt;dm_stream_context;</div><div class='ctx'> </div><div class='del'>-		if (!aconn-&gt;disallow_edp_enter_psr)</div><div class='add'>+		if (!aconn-&gt;disallow_edp_enter_psr) {</div><div class='add'>+			struct amdgpu_display_manager *dm = vblank_work-&gt;dm;</div><div class='add'>+</div><div class='ctx'> 			amdgpu_dm_psr_enable(vblank_work-&gt;stream);</div><div class='add'>+			if (dm-&gt;idle_workqueue &amp;&amp;</div><div class='add'>+			    (dm-&gt;dc-&gt;config.disable_ips == DMUB_IPS_ENABLE) &amp;&amp;</div><div class='add'>+			    dm-&gt;dc-&gt;idle_optimizations_allowed &amp;&amp;</div><div class='add'>+			    dm-&gt;idle_workqueue-&gt;enable &amp;&amp;</div><div class='add'>+			    !dm-&gt;idle_workqueue-&gt;running)</div><div class='add'>+				schedule_work(&amp;dm-&gt;idle_workqueue-&gt;work);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool amdgpu_dm_is_headless(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector;</div><div class='add'>+	struct drm_connector_list_iter iter;</div><div class='add'>+	struct drm_device *dev;</div><div class='add'>+	bool is_headless = true;</div><div class='add'>+</div><div class='add'>+	if (adev == NULL)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	dev = adev-&gt;dm.ddev;</div><div class='add'>+</div><div class='add'>+	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='add'>+	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;status == connector_status_connected) {</div><div class='add'>+			is_headless = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+	drm_connector_list_iter_end(&amp;iter);</div><div class='add'>+	return is_headless;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_dm_idle_worker(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct idle_workqueue *idle_work;</div><div class='add'>+</div><div class='add'>+	idle_work = container_of(work, struct idle_workqueue, work);</div><div class='add'>+	idle_work-&gt;dm-&gt;idle_workqueue-&gt;running = true;</div><div class='add'>+</div><div class='add'>+	while (idle_work-&gt;enable) {</div><div class='add'>+		fsleep(HPD_DETECTION_PERIOD_uS);</div><div class='add'>+		mutex_lock(&amp;idle_work-&gt;dm-&gt;dc_lock);</div><div class='add'>+		if (!idle_work-&gt;dm-&gt;dc-&gt;idle_optimizations_allowed) {</div><div class='add'>+			mutex_unlock(&amp;idle_work-&gt;dm-&gt;dc_lock);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		dc_allow_idle_optimizations(idle_work-&gt;dm-&gt;dc, false);</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;idle_work-&gt;dm-&gt;dc_lock);</div><div class='add'>+		fsleep(HPD_DETECTION_TIME_uS);</div><div class='add'>+		mutex_lock(&amp;idle_work-&gt;dm-&gt;dc_lock);</div><div class='add'>+</div><div class='add'>+		if (!amdgpu_dm_is_headless(idle_work-&gt;dm-&gt;adev) &amp;&amp;</div><div class='add'>+		    !amdgpu_dm_psr_is_active_allowed(idle_work-&gt;dm)) {</div><div class='add'>+			mutex_unlock(&amp;idle_work-&gt;dm-&gt;dc_lock);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (idle_work-&gt;enable) {</div><div class='add'>+			dc_post_update_surfaces_to_stream(idle_work-&gt;dm-&gt;dc);</div><div class='add'>+			dc_allow_idle_optimizations(idle_work-&gt;dm-&gt;dc, true);</div><div class='add'>+		}</div><div class='add'>+		mutex_unlock(&amp;idle_work-&gt;dm-&gt;dc_lock);</div><div class='add'>+	}</div><div class='add'>+	idle_work-&gt;dm-&gt;idle_workqueue-&gt;running = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct idle_workqueue *idle_work;</div><div class='add'>+</div><div class='add'>+	idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);</div><div class='add'>+	if (ZERO_OR_NULL_PTR(idle_work))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	idle_work-&gt;dm = &amp;adev-&gt;dm;</div><div class='add'>+	idle_work-&gt;enable = false;</div><div class='add'>+	idle_work-&gt;running = false;</div><div class='add'>+	INIT_WORK(&amp;idle_work-&gt;work, amdgpu_dm_idle_worker);</div><div class='add'>+</div><div class='add'>+	return idle_work;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)</div><div class='hunk'>@@ -156,6 +248,8 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)</div><div class='ctx'> 	struct vblank_control_work *vblank_work =</div><div class='ctx'> 		container_of(work, struct vblank_control_work, work);</div><div class='ctx'> 	struct amdgpu_display_manager *dm = vblank_work-&gt;dm;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dm-&gt;ddev);</div><div class='add'>+	int r;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;dm-&gt;dc_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -164,9 +258,8 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)</div><div class='ctx'> 	else if (dm-&gt;active_vblank_irq_count)</div><div class='ctx'> 		dm-&gt;active_vblank_irq_count--;</div><div class='ctx'> </div><div class='del'>-	dc_allow_idle_optimizations(dm-&gt;dc, dm-&gt;active_vblank_irq_count == 0);</div><div class='del'>-</div><div class='del'>-	DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm-&gt;active_vblank_irq_count == 0);</div><div class='add'>+	if (dm-&gt;active_vblank_irq_count &gt; 0)</div><div class='add'>+		dc_allow_idle_optimizations(dm-&gt;dc, false);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Control PSR based on vblank requirements from OS</div><div class='hunk'>@@ -178,11 +271,24 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)</div><div class='ctx'> 	 * where the SU region is the full hactive*vactive region. See</div><div class='ctx'> 	 * fill_dc_dirty_rects().</div><div class='ctx'> 	 */</div><div class='del'>-	if (vblank_work-&gt;stream &amp;&amp; vblank_work-&gt;stream-&gt;link) {</div><div class='add'>+	if (vblank_work-&gt;stream &amp;&amp; vblank_work-&gt;stream-&gt;link &amp;&amp; vblank_work-&gt;acrtc) {</div><div class='ctx'> 		amdgpu_dm_crtc_set_panel_sr_feature(</div><div class='ctx'> 			vblank_work, vblank_work-&gt;enable,</div><div class='del'>-			vblank_work-&gt;acrtc-&gt;dm_irq_params.allow_psr_entry ||</div><div class='del'>-			vblank_work-&gt;stream-&gt;link-&gt;replay_settings.replay_feature_enabled);</div><div class='add'>+			vblank_work-&gt;acrtc-&gt;dm_irq_params.allow_sr_entry);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dm-&gt;active_vblank_irq_count == 0) {</div><div class='add'>+		dc_post_update_surfaces_to_stream(dm-&gt;dc);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_dpm_pause_power_profile(adev, true);</div><div class='add'>+		if (r)</div><div class='add'>+			dev_warn(adev-&gt;dev, "failed to set default power profile mode\n");</div><div class='add'>+</div><div class='add'>+		dc_allow_idle_optimizations(dm-&gt;dc, true);</div><div class='add'>+</div><div class='add'>+		r = amdgpu_dpm_pause_power_profile(adev, false);</div><div class='add'>+		if (r)</div><div class='add'>+			dev_warn(adev-&gt;dev, "failed to restore the power profile mode\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;dm-&gt;dc_lock);</div><div class='hunk'>@@ -199,31 +305,100 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)</div><div class='ctx'> 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc-&gt;state);</div><div class='ctx'> 	struct amdgpu_display_manager *dm = &amp;adev-&gt;dm;</div><div class='ctx'> 	struct vblank_control_work *work;</div><div class='add'>+	int irq_type;</div><div class='ctx'> 	int rc = 0;</div><div class='ctx'> </div><div class='del'>-	if (acrtc-&gt;otg_inst == -1)</div><div class='del'>-		goto skip;</div><div class='add'>+	if (enable &amp;&amp; !acrtc-&gt;base.enabled) {</div><div class='add'>+		drm_dbg_vbl(crtc-&gt;dev,</div><div class='add'>+				"Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n",</div><div class='add'>+				acrtc-&gt;crtc_id, acrtc-&gt;base.enabled);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc-&gt;crtc_id);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		struct dc *dc = adev-&gt;dm.dc;</div><div class='add'>+		struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);</div><div class='add'>+		struct psr_settings *psr = &amp;acrtc_state-&gt;stream-&gt;link-&gt;psr_settings;</div><div class='add'>+		struct replay_settings *pr = &amp;acrtc_state-&gt;stream-&gt;link-&gt;replay_settings;</div><div class='add'>+		bool sr_supported = (psr-&gt;psr_version != DC_PSR_VERSION_UNSUPPORTED) ||</div><div class='add'>+								pr-&gt;config.replay_supported;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * IPS &amp; self-refresh feature can cause vblank counter resets between</div><div class='add'>+		 * vblank disable and enable.</div><div class='add'>+		 * It may cause system stuck due to waiting for the vblank counter.</div><div class='add'>+		 * Call this function to estimate missed vblanks by using timestamps and</div><div class='add'>+		 * update the vblank counter in DRM.</div><div class='add'>+		 */</div><div class='add'>+		if (dc-&gt;caps.ips_support &amp;&amp;</div><div class='add'>+			dc-&gt;config.disable_ips != DMUB_IPS_DISABLE_ALL &amp;&amp;</div><div class='add'>+			sr_supported &amp;&amp; vblank-&gt;config.disable_immediate)</div><div class='add'>+			drm_crtc_vblank_restore(crtc);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc_supports_vrr(dm-&gt;dc-&gt;ctx-&gt;dce_version)) {</div><div class='add'>+		if (enable) {</div><div class='add'>+			/* vblank irq on -&gt; Only need vupdate irq in vrr mode */</div><div class='add'>+			if (amdgpu_dm_crtc_vrr_active(acrtc_state))</div><div class='add'>+				rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);</div><div class='add'>+		} else {</div><div class='add'>+			/* vblank irq off -&gt; vupdate irq off */</div><div class='add'>+			rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> </div><div class='add'>+	/* crtc vblank or vstartup interrupt */</div><div class='ctx'> 	if (enable) {</div><div class='del'>-		/* vblank irq on -&gt; Only need vupdate irq in vrr mode */</div><div class='del'>-		if (amdgpu_dm_crtc_vrr_active(acrtc_state))</div><div class='del'>-			rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);</div><div class='add'>+		rc = amdgpu_irq_get(adev, &amp;adev-&gt;crtc_irq, irq_type);</div><div class='add'>+		drm_dbg_vbl(crtc-&gt;dev, "Get crtc_irq ret=%d\n", rc);</div><div class='ctx'> 	} else {</div><div class='del'>-		/* vblank irq off -&gt; vupdate irq off */</div><div class='del'>-		rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);</div><div class='add'>+		rc = amdgpu_irq_put(adev, &amp;adev-&gt;crtc_irq, irq_type);</div><div class='add'>+		drm_dbg_vbl(crtc-&gt;dev, "Put crtc_irq ret=%d\n", rc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	rc = (enable)</div><div class='del'>-		? amdgpu_irq_get(adev, &amp;adev-&gt;crtc_irq, acrtc-&gt;crtc_id)</div><div class='del'>-		: amdgpu_irq_put(adev, &amp;adev-&gt;crtc_irq, acrtc-&gt;crtc_id);</div><div class='add'>+	/*</div><div class='add'>+	 * hubp surface flip interrupt</div><div class='add'>+	 *</div><div class='add'>+	 * We have no guarantee that the frontend index maps to the same</div><div class='add'>+	 * backend index - some even map to more than one.</div><div class='add'>+	 *</div><div class='add'>+	 * TODO: Use a different interrupt or check DC itself for the mapping.</div><div class='add'>+	 */</div><div class='add'>+	if (enable) {</div><div class='add'>+		rc = amdgpu_irq_get(adev, &amp;adev-&gt;pageflip_irq, irq_type);</div><div class='add'>+		drm_dbg_vbl(crtc-&gt;dev, "Get pageflip_irq ret=%d\n", rc);</div><div class='add'>+	} else {</div><div class='add'>+		rc = amdgpu_irq_put(adev, &amp;adev-&gt;pageflip_irq, irq_type);</div><div class='add'>+		drm_dbg_vbl(crtc-&gt;dev, "Put pageflip_irq ret=%d\n", rc);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-skip:</div><div class='add'>+#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='add'>+	/* crtc vline0 interrupt, only available on DCN+ */</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {</div><div class='add'>+		if (enable) {</div><div class='add'>+			rc = amdgpu_irq_get(adev, &amp;adev-&gt;vline0_irq, irq_type);</div><div class='add'>+			drm_dbg_vbl(crtc-&gt;dev, "Get vline0_irq ret=%d\n", rc);</div><div class='add'>+		} else {</div><div class='add'>+			rc = amdgpu_irq_put(adev, &amp;adev-&gt;vline0_irq, irq_type);</div><div class='add'>+			drm_dbg_vbl(crtc-&gt;dev, "Put vline0_irq ret=%d\n", rc);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (rc)</div><div class='add'>+			return rc;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_in_reset(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -304,6 +479,7 @@ static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *cr</div><div class='ctx'> 	state-&gt;regamma_tf = cur-&gt;regamma_tf;</div><div class='ctx'> 	state-&gt;crc_skip_count = cur-&gt;crc_skip_count;</div><div class='ctx'> 	state-&gt;mpo_requested = cur-&gt;mpo_requested;</div><div class='add'>+	state-&gt;cursor_mode = cur-&gt;cursor_mode;</div><div class='ctx'> 	/* TODO Duplicate dc_stream after objects are stream object is flattened */</div><div class='ctx'> </div><div class='ctx'> 	return &amp;state-&gt;base;</div><div class='hunk'>@@ -527,6 +703,15 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!state-&gt;legacy_cursor_update &amp;&amp; amdgpu_dm_crtc_vrr_active(dm_crtc_state)) {</div><div class='add'>+		struct drm_plane_state *primary_state;</div><div class='add'>+</div><div class='add'>+		/* Pull in primary plane for correct VRR handling */</div><div class='add'>+		primary_state = drm_atomic_get_plane_state(state, crtc-&gt;primary);</div><div class='add'>+		if (IS_ERR(primary_state))</div><div class='add'>+			return PTR_ERR(primary_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* In some use cases, like reset, no stream is attached */</div><div class='ctx'> 	if (!dm_crtc_state-&gt;stream)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -551,7 +736,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = NULL;</div><div class='ctx'> 	struct drm_plane *cursor_plane;</div><div class='del'>-	bool is_dcn;</div><div class='add'>+	bool has_degamma;</div><div class='ctx'> 	int res = -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);</div><div class='hunk'>@@ -590,11 +775,18 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	dm-&gt;adev-&gt;mode_info.crtcs[crtc_index] = acrtc;</div><div class='ctx'> </div><div class='del'>-	/* Don't enable DRM CRTC degamma property for DCE since it doesn't</div><div class='del'>-	 * support programmable degamma anywhere.</div><div class='add'>+	/* Don't enable DRM CRTC degamma property for</div><div class='add'>+	 * 1. Degamma is replaced by color pipeline.</div><div class='add'>+	 * 2. DCE since it doesn't support programmable degamma anywhere.</div><div class='add'>+	 * 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor.</div><div class='ctx'> 	 */</div><div class='del'>-	is_dcn = dm-&gt;adev-&gt;dm.dc-&gt;caps.color.dpp.dcn_arch;</div><div class='del'>-	drm_crtc_enable_color_mgmt(&amp;acrtc-&gt;base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,</div><div class='add'>+	if (plane-&gt;color_pipeline_property)</div><div class='add'>+		has_degamma = false;</div><div class='add'>+	else</div><div class='add'>+		has_degamma = dm-&gt;adev-&gt;dm.dc-&gt;caps.color.dpp.dcn_arch &amp;&amp;</div><div class='add'>+			      dm-&gt;adev-&gt;dm.dc-&gt;ctx-&gt;dce_version != DCN_VERSION_4_01;</div><div class='add'>+</div><div class='add'>+	drm_crtc_enable_color_mgmt(&amp;acrtc-&gt;base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,</div><div class='ctx'> 				   true, MAX_COLOR_LUT_ENTRIES);</div><div class='ctx'> </div><div class='ctx'> 	drm_mode_crtc_set_gamma_size(&amp;acrtc-&gt;base, MAX_COLOR_LEGACY_LUT_ENTRIES);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h<br/>index 17e948753f59..c1212947a77b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h</a></div><div class='hunk'>@@ -37,7 +37,7 @@ int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable);</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc);</div><div class='ctx'> </div><div class='del'>-bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state);</div><div class='add'>+bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c<br/>index eee4945653e2..a9839485f2a2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -25,11 +26,13 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/string_helpers.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='add'>+#include &lt;media/cec-notifier.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='ctx'> #include "amdgpu_dm_debugfs.h"</div><div class='add'>+#include "amdgpu_dm_replay.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "dmub/dmub_srv.h"</div><div class='ctx'> #include "resource.h"</div><div class='hunk'>@@ -257,7 +260,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,</div><div class='ctx'> 	struct dc_link *link = connector-&gt;dc_link;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(connector-&gt;base.dev);</div><div class='ctx'> 	struct dc *dc = (struct dc *)link-&gt;dc;</div><div class='del'>-	struct dc_link_settings prefer_link_settings;</div><div class='add'>+	struct dc_link_settings prefer_link_settings = {0};</div><div class='ctx'> 	char *wr_buf = NULL;</div><div class='ctx'> 	const uint32_t wr_buf_size = 40;</div><div class='ctx'> 	/* 0: lane_count; 1: link_rate */</div><div class='hunk'>@@ -388,7 +391,7 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,</div><div class='ctx'> 	struct dc_link *link = aconnector-&gt;dc_link;</div><div class='ctx'> 	struct amdgpu_device *adev = drm_to_adev(aconnector-&gt;base.dev);</div><div class='ctx'> 	struct dc *dc = (struct dc *)link-&gt;dc;</div><div class='del'>-	struct dc_link_settings prefer_link_settings;</div><div class='add'>+	struct dc_link_settings prefer_link_settings = {0};</div><div class='ctx'> 	char *wr_buf = NULL;</div><div class='ctx'> 	const uint32_t wr_buf_size = 40;</div><div class='ctx'> 	/* 0: lane_count; 1: link_rate */</div><div class='hunk'>@@ -612,7 +615,7 @@ static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,</div><div class='ctx'> 	uint32_t wr_buf_size = 40;</div><div class='ctx'> 	long param[3];</div><div class='ctx'> 	bool use_prefer_link_setting;</div><div class='del'>-	struct link_training_settings link_lane_settings;</div><div class='add'>+	struct link_training_settings link_lane_settings = {0};</div><div class='ctx'> 	int max_param_num = 3;</div><div class='ctx'> 	uint8_t param_nums = 0;</div><div class='ctx'> 	int r = 0;</div><div class='hunk'>@@ -756,6 +759,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us</div><div class='ctx'> 	int max_param_num = 11;</div><div class='ctx'> 	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;</div><div class='ctx'> 	bool disable_hpd = false;</div><div class='add'>+	bool supports_hpd = link-&gt;irq_source_hpd != DC_IRQ_SOURCE_INVALID;</div><div class='ctx'> 	bool valid_test_pattern = false;</div><div class='ctx'> 	uint8_t param_nums = 0;</div><div class='ctx'> 	/* init with default 80bit custom pattern */</div><div class='hunk'>@@ -767,7 +771,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us</div><div class='ctx'> 			LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};</div><div class='ctx'> 	struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,</div><div class='ctx'> 			LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};</div><div class='del'>-	struct link_training_settings link_training_settings;</div><div class='add'>+	struct link_training_settings link_training_settings = {0};</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (size == 0)</div><div class='hunk'>@@ -847,7 +851,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us</div><div class='ctx'> 	 * because it might have been disabled after a test pattern was set.</div><div class='ctx'> 	 * AUX depends on HPD * sequence dependent, do not move!</div><div class='ctx'> 	 */</div><div class='del'>-	if (!disable_hpd)</div><div class='add'>+	if (supports_hpd &amp;&amp; !disable_hpd)</div><div class='ctx'> 		dc_link_enable_hpd(link);</div><div class='ctx'> </div><div class='ctx'> 	prefer_link_settings.lane_count = link-&gt;verified_link_cap.lane_count;</div><div class='hunk'>@@ -885,7 +889,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us</div><div class='ctx'> 	 * Need disable interrupt to avoid SW driver disable DP output. This is</div><div class='ctx'> 	 * done after the test pattern is set.</div><div class='ctx'> 	 */</div><div class='del'>-	if (valid_test_pattern &amp;&amp; disable_hpd)</div><div class='add'>+	if (valid_test_pattern &amp;&amp; supports_hpd &amp;&amp; disable_hpd)</div><div class='ctx'> 		dc_link_disable_hpd(link);</div><div class='ctx'> </div><div class='ctx'> 	kfree(wr_buf);</div><div class='hunk'>@@ -901,9 +905,10 @@ static int dmub_tracebuffer_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = m-&gt;private;</div><div class='ctx'> 	struct dmub_srv_fb_info *fb_info = adev-&gt;dm.dmub_fb_info;</div><div class='add'>+	struct dmub_fw_meta_info *fw_meta_info = NULL;</div><div class='ctx'> 	struct dmub_debugfs_trace_entry *entries;</div><div class='ctx'> 	uint8_t *tbuf_base;</div><div class='del'>-	uint32_t tbuf_size, max_entries, num_entries, i;</div><div class='add'>+	uint32_t tbuf_size, max_entries, num_entries, first_entry, i;</div><div class='ctx'> </div><div class='ctx'> 	if (!fb_info)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -912,20 +917,42 @@ static int dmub_tracebuffer_show(struct seq_file *m, void *data)</div><div class='ctx'> 	if (!tbuf_base)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	tbuf_size = fb_info-&gt;fb[DMUB_WINDOW_5_TRACEBUFF].size;</div><div class='add'>+	if (adev-&gt;dm.dmub_srv)</div><div class='add'>+		fw_meta_info = &amp;adev-&gt;dm.dmub_srv-&gt;meta_info;</div><div class='add'>+</div><div class='add'>+	tbuf_size = fw_meta_info ? fw_meta_info-&gt;trace_buffer_size :</div><div class='add'>+				   DMUB_TRACE_BUFFER_SIZE;</div><div class='ctx'> 	max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /</div><div class='ctx'> 		      sizeof(struct dmub_debugfs_trace_entry);</div><div class='ctx'> </div><div class='ctx'> 	num_entries =</div><div class='ctx'> 		((struct dmub_debugfs_trace_header *)tbuf_base)-&gt;entry_count;</div><div class='ctx'> </div><div class='add'>+	/* DMCUB tracebuffer is a ring. If it rolled over, print a hint that</div><div class='add'>+	 * entries are being overwritten.</div><div class='add'>+	 */</div><div class='add'>+	if (num_entries &gt; max_entries)</div><div class='add'>+		seq_printf(m, "...\n");</div><div class='add'>+</div><div class='add'>+	first_entry = num_entries % max_entries;</div><div class='ctx'> 	num_entries = min(num_entries, max_entries);</div><div class='ctx'> </div><div class='ctx'> 	entries = (struct dmub_debugfs_trace_entry</div><div class='ctx'> 			   *)(tbuf_base +</div><div class='ctx'> 			      sizeof(struct dmub_debugfs_trace_header));</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; num_entries; ++i) {</div><div class='add'>+	/* To print entries chronologically, start from the first entry till the</div><div class='add'>+	 * top of buffer, then from base of buffer to first entry.</div><div class='add'>+	 */</div><div class='add'>+	for (i = first_entry; i &lt; num_entries; ++i) {</div><div class='add'>+		struct dmub_debugfs_trace_entry *entry = &amp;entries[i];</div><div class='add'>+</div><div class='add'>+		seq_printf(m,</div><div class='add'>+			   "trace_code=%u tick_count=%u param0=%u param1=%u\n",</div><div class='add'>+			   entry-&gt;trace_code, entry-&gt;tick_count, entry-&gt;param0,</div><div class='add'>+			   entry-&gt;param1);</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; first_entry; ++i) {</div><div class='ctx'> 		struct dmub_debugfs_trace_entry *entry = &amp;entries[i];</div><div class='ctx'> </div><div class='ctx'> 		seq_printf(m,</div><div class='hunk'>@@ -960,6 +987,58 @@ static int dmub_fw_state_show(struct seq_file *m, void *data)</div><div class='ctx'> 	return seq_write(m, state_base, state_size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* replay_capability_show() - show eDP panel replay capability</div><div class='add'>+ *</div><div class='add'>+ * The read function: replay_capability_show</div><div class='add'>+ * Shows if sink and driver has Replay capability or not.</div><div class='add'>+ *</div><div class='add'>+ *	cat /sys/kernel/debug/dri/0/eDP-X/replay_capability</div><div class='add'>+ *</div><div class='add'>+ * Expected output:</div><div class='add'>+ * "Sink support: no\n" - if panel doesn't support Replay</div><div class='add'>+ * "Sink support: yes\n" - if panel supports Replay</div><div class='add'>+ * "Driver support: no\n" - if driver doesn't support Replay</div><div class='add'>+ * "Driver support: yes\n" - if driver supports Replay</div><div class='add'>+ */</div><div class='add'>+static int replay_capability_show(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector = m-&gt;private;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+	struct dc_link *link = aconnector-&gt;dc_link;</div><div class='add'>+	bool sink_support_replay = false;</div><div class='add'>+	bool driver_support_replay = false;</div><div class='add'>+</div><div class='add'>+	if (!link)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;type == dc_connection_none)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (!(link-&gt;connector_signal &amp; SIGNAL_TYPE_EDP))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	/* If Replay is already set to support, skip the checks */</div><div class='add'>+	if (link-&gt;replay_settings.config.replay_supported) {</div><div class='add'>+		sink_support_replay = true;</div><div class='add'>+		driver_support_replay = true;</div><div class='add'>+	} else if ((amdgpu_dc_debug_mask &amp; DC_DISABLE_REPLAY)) {</div><div class='add'>+		sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);</div><div class='add'>+	} else {</div><div class='add'>+		struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+		sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);</div><div class='add'>+		if (dc-&gt;ctx-&gt;dmub_srv &amp;&amp; dc-&gt;ctx-&gt;dmub_srv-&gt;dmub)</div><div class='add'>+			driver_support_replay =</div><div class='add'>+				(bool)dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.replay_supported;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));</div><div class='add'>+	seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));</div><div class='add'>+	seq_printf(m, "Config support: %s\n", str_yes_no(link-&gt;replay_settings.config.replay_supported));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* psr_capability_show() - show eDP panel PSR capability</div><div class='ctx'>  *</div><div class='ctx'>  * The read function: sink_psr_capability_show</div><div class='hunk'>@@ -1092,7 +1171,7 @@ static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_FULLRANGE:</div><div class='ctx'> 		seq_puts(m, "BT2020_RGB");</div><div class='ctx'> 		break;</div><div class='del'>-	case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='ctx'> 		seq_puts(m, "BT2020_YCC");</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1224,7 +1303,8 @@ static int odm_combine_segments_show(struct seq_file *m, void *unused)</div><div class='ctx'> 	if (connector-&gt;status != connector_status_connected)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx != NULL &amp;&amp; pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;get_odm_combine_segments)</div><div class='add'>+	if (pipe_ctx &amp;&amp; pipe_ctx-&gt;stream_res.tg &amp;&amp;</div><div class='add'>+	    pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;get_odm_combine_segments)</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;get_odm_combine_segments(pipe_ctx-&gt;stream_res.tg, &amp;segments);</div><div class='ctx'> </div><div class='ctx'> 	seq_printf(m, "%d\n", segments);</div><div class='hunk'>@@ -1249,7 +1329,7 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b</div><div class='ctx'> 				 size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	int r;</div><div class='del'>-	uint8_t data[36];</div><div class='add'>+	uint8_t data[36] = {0};</div><div class='ctx'> 	struct amdgpu_dm_connector *connector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct dm_crtc_state *acrtc_state;</div><div class='ctx'> 	uint32_t write_size = 36;</div><div class='hunk'>@@ -1367,7 +1447,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf,</div><div class='ctx'> 	uint8_t param_nums = 0;</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> </div><div class='del'>-	if (!aconnector || !aconnector-&gt;dc_link)</div><div class='add'>+	if (!aconnector-&gt;dc_link)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (size == 0)</div><div class='hunk'>@@ -1476,7 +1556,6 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -1490,12 +1569,12 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1503,10 +1582,9 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_clock_en);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -1596,7 +1674,9 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1662,7 +1742,6 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -1676,12 +1755,12 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1689,10 +1768,9 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_slice_width);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -1780,7 +1858,9 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1846,7 +1926,6 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -1860,12 +1939,12 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1873,10 +1952,9 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_slice_height);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -1964,7 +2042,9 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2026,7 +2106,6 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -2040,12 +2119,12 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2053,10 +2132,9 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_bits_per_pixel);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -2141,7 +2219,9 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2201,7 +2281,6 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -2215,12 +2294,12 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2228,10 +2307,9 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_pic_width);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -2257,7 +2335,6 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -2271,12 +2348,12 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2284,10 +2361,9 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_pic_height);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -2328,7 +2404,6 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -2342,12 +2417,12 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2355,10 +2430,9 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_chunk_size);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -2399,7 +2473,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,</div><div class='ctx'> 				    size_t size, loff_t *pos)</div><div class='ctx'> {</div><div class='ctx'> 	char *rd_buf = NULL;</div><div class='del'>-	char *rd_buf_ptr = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='ctx'> 	struct display_stream_compressor *dsc;</div><div class='ctx'> 	struct dcn_dsc_state dsc_state = {0};</div><div class='hunk'>@@ -2413,12 +2486,12 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (!rd_buf)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rd_buf_ptr = rd_buf;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		pipe_ctx = &amp;aconnector-&gt;dc_link-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (pipe_ctx-&gt;stream &amp;&amp;</div><div class='del'>-		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link)</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;link == aconnector-&gt;dc_link &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink &amp;&amp;</div><div class='add'>+		    pipe_ctx-&gt;stream-&gt;sink == aconnector-&gt;dc_sink)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2426,10 +2499,9 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (dsc)</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='ctx'> </div><div class='del'>-	snprintf(rd_buf_ptr, str_len,</div><div class='add'>+	snprintf(rd_buf, str_len,</div><div class='ctx'> 		"%d\n",</div><div class='ctx'> 		dsc_state.dsc_slice_bpg_offset);</div><div class='del'>-	rd_buf_ptr += str_len;</div><div class='ctx'> </div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		if (*pos &gt;= rd_buf_size)</div><div class='hunk'>@@ -2595,6 +2667,49 @@ unlock:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * IPS status.  Read only.</div><div class='add'>+ *</div><div class='add'>+ * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status</div><div class='add'>+ */</div><div class='add'>+static int ips_status_show(struct seq_file *m, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = m-&gt;private;</div><div class='add'>+	struct dc *dc = adev-&gt;dm.dc;</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv;</div><div class='add'>+</div><div class='add'>+	seq_printf(m, "IPS config: %d\n", dc-&gt;config.disable_ips);</div><div class='add'>+	seq_printf(m, "Idle optimization: %d\n", dc-&gt;idle_optimizations_allowed);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dm.idle_workqueue) {</div><div class='add'>+		seq_printf(m, "Idle workqueue - enabled: %d\n", adev-&gt;dm.idle_workqueue-&gt;enable);</div><div class='add'>+		seq_printf(m, "Idle workqueue - running: %d\n", adev-&gt;dm.idle_workqueue-&gt;running);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+	if (dc_dmub_srv &amp;&amp; dc_dmub_srv-&gt;dmub) {</div><div class='add'>+		uint32_t rcg_count, ips1_count, ips2_count;</div><div class='add'>+		volatile const struct dmub_shared_state_ips_fw *ips_fw =</div><div class='add'>+			&amp;dc_dmub_srv-&gt;dmub-&gt;shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;</div><div class='add'>+		rcg_count = ips_fw-&gt;rcg_entry_count;</div><div class='add'>+		ips1_count = ips_fw-&gt;ips1_entry_count;</div><div class='add'>+		ips2_count = ips_fw-&gt;ips2_entry_count;</div><div class='add'>+		seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",</div><div class='add'>+			   rcg_count,</div><div class='add'>+			   ips1_count,</div><div class='add'>+			   ips2_count);</div><div class='add'>+		rcg_count = ips_fw-&gt;rcg_exit_count;</div><div class='add'>+		ips1_count = ips_fw-&gt;ips1_exit_count;</div><div class='add'>+		ips2_count = ips_fw-&gt;ips2_exit_count;</div><div class='add'>+		seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u",</div><div class='add'>+			   rcg_count,</div><div class='add'>+			   ips1_count,</div><div class='add'>+			   ips2_count);</div><div class='add'>+		seq_puts(m, "\n");</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * Backlight at this moment.  Read only.</div><div class='ctx'>  * As written to display, taking ABM and backlight lut into account.</div><div class='ctx'>  * Ranges from 0x0 to 0x10000 (= 100% PWM)</div><div class='hunk'>@@ -2737,6 +2852,67 @@ static int is_dpia_link_show(struct seq_file *m, void *data)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * hdmi_cec_state_show - Read out the HDMI-CEC feature status</div><div class='add'>+ * @m: sequence file.</div><div class='add'>+ * @data: unused.</div><div class='add'>+ *</div><div class='add'>+ * Return 0 on success</div><div class='add'>+ */</div><div class='add'>+static int hdmi_cec_state_show(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector = m-&gt;private;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='add'>+	seq_printf(m, "%s:%d\n", connector-&gt;name, connector-&gt;base.id);</div><div class='add'>+	seq_printf(m, "HDMI-CEC status: %d\n", aconnector-&gt;notifier ? 1 : 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side</div><div class='add'>+ * @f: file structure.</div><div class='add'>+ * @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature.</div><div class='add'>+ * @size: size of buffer from userpsace.</div><div class='add'>+ * @pos: unused.</div><div class='add'>+ *</div><div class='add'>+ * Return size on success, error code on failure</div><div class='add'>+ */</div><div class='add'>+static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf,</div><div class='add'>+				    size_t size, loff_t *pos)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	bool enable;</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = file_inode(f)-&gt;i_private;</div><div class='add'>+	struct drm_device *ddev = aconnector-&gt;base.dev;</div><div class='add'>+</div><div class='add'>+	if (size == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = kstrtobool_from_user(buf, size, &amp;enable);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_dbg_driver(ddev, "invalid user data !\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (aconnector-&gt;notifier)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		ret = amdgpu_dm_initialize_hdmi_connector(aconnector);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		hdmi_cec_set_edid(aconnector);</div><div class='add'>+	} else {</div><div class='add'>+		if (!aconnector-&gt;notifier)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		cec_notifier_conn_unregister(aconnector-&gt;notifier);</div><div class='add'>+		aconnector-&gt;notifier = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);</div><div class='hunk'>@@ -2744,10 +2920,12 @@ DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(internal_display);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);</div><div class='add'>+DEFINE_SHOW_ATTRIBUTE(replay_capability);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(psr_capability);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(is_dpia_link);</div><div class='add'>+DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state);</div><div class='ctx'> </div><div class='ctx'> static const struct file_operations dp_dsc_clock_en_debugfs_fops = {</div><div class='ctx'> 	.owner = THIS_MODULE,</div><div class='hunk'>@@ -2883,7 +3061,8 @@ static const struct {</div><div class='ctx'> 	char *name;</div><div class='ctx'> 	const struct file_operations *fops;</div><div class='ctx'> } hdmi_debugfs_entries[] = {</div><div class='del'>-		{"hdcp_sink_capability", &amp;hdcp_sink_capability_fops}</div><div class='add'>+		{"hdcp_sink_capability", &amp;hdcp_sink_capability_fops},</div><div class='add'>+		{"hdmi_cec_state", &amp;hdmi_cec_state_fops}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -2914,6 +3093,51 @@ DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,</div><div class='ctx'> 			 force_yuv420_output_set, "%llu\n");</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ *  Read Replay state</div><div class='add'>+ */</div><div class='add'>+static int replay_get_state(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *connector = data;</div><div class='add'>+	struct dc_link *link = connector-&gt;dc_link;</div><div class='add'>+	uint64_t state = REPLAY_STATE_INVALID;</div><div class='add'>+</div><div class='add'>+	dc_link_get_replay_state(link, &amp;state);</div><div class='add'>+</div><div class='add'>+	*val = state;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ *  Start / Stop capture Replay residency</div><div class='add'>+ */</div><div class='add'>+static int replay_set_residency(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *connector = data;</div><div class='add'>+	struct dc_link *link = connector-&gt;dc_link;</div><div class='add'>+	bool is_start = (val != 0);</div><div class='add'>+	u32 residency = 0;</div><div class='add'>+</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;edp_replay_residency(link, &amp;residency, is_start, PR_RESIDENCY_MODE_PHY);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ *  Read Replay residency</div><div class='add'>+ */</div><div class='add'>+static int replay_get_residency(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *connector = data;</div><div class='add'>+	struct dc_link *link = connector-&gt;dc_link;</div><div class='add'>+	u32 residency = 0;</div><div class='add'>+</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;edp_replay_residency(link, &amp;residency, false, PR_RESIDENCY_MODE_PHY);</div><div class='add'>+	*val = (u64)residency;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  *  Read PSR state</div><div class='ctx'>  */</div><div class='ctx'> static int psr_get(void *data, u64 *val)</div><div class='hunk'>@@ -2936,9 +3160,9 @@ static int psr_read_residency(void *data, u64 *val)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *connector = data;</div><div class='ctx'> 	struct dc_link *link = connector-&gt;dc_link;</div><div class='del'>-	u32 residency;</div><div class='add'>+	u32 residency = 0;</div><div class='ctx'> </div><div class='del'>-	link-&gt;dc-&gt;link_srv-&gt;edp_get_psr_residency(link, &amp;residency);</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;edp_get_psr_residency(link, &amp;residency, PSR_RESIDENCY_MODE_PHY);</div><div class='ctx'> </div><div class='ctx'> 	*val = (u64)residency;</div><div class='ctx'> </div><div class='hunk'>@@ -3131,6 +3355,9 @@ static int dmcub_trace_event_state_get(void *data, u64 *val)</div><div class='ctx'> DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,</div><div class='ctx'> 			 dmcub_trace_event_state_set, "%llu\n");</div><div class='ctx'> </div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency,</div><div class='add'>+			 "%llu\n");</div><div class='ctx'> DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");</div><div class='ctx'> DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,</div><div class='ctx'> 			 "%llu\n");</div><div class='hunk'>@@ -3145,6 +3372,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,</div><div class='ctx'> </div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(current_backlight);</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(target_backlight);</div><div class='add'>+DEFINE_SHOW_ATTRIBUTE(ips_status);</div><div class='ctx'> </div><div class='ctx'> static const struct {</div><div class='ctx'> 	char *name;</div><div class='hunk'>@@ -3304,6 +3532,11 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (connector-&gt;base.connector_type == DRM_MODE_CONNECTOR_eDP) {</div><div class='add'>+		debugfs_create_file("replay_capability", 0444, dir, connector,</div><div class='add'>+					&amp;replay_capability_fops);</div><div class='add'>+		debugfs_create_file("replay_state", 0444, dir, connector, &amp;replay_state_fops);</div><div class='add'>+		debugfs_create_file_unsafe("replay_residency", 0444, dir,</div><div class='add'>+					   connector, &amp;replay_residency_fops);</div><div class='ctx'> 		debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &amp;psr_capability_fops);</div><div class='ctx'> 		debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &amp;psr_fops);</div><div class='ctx'> 		debugfs_create_file_unsafe("psr_residency", 0444, dir,</div><div class='hunk'>@@ -3346,8 +3579,8 @@ static int crc_win_x_start_set(void *data, u64 val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.x_start = (uint16_t) val;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.update_win = false;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].x_start = (uint16_t) val;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].update_win = false;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3363,7 +3596,7 @@ static int crc_win_x_start_get(void *data, u64 *val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	*val = acrtc-&gt;dm_irq_params.window_param.x_start;</div><div class='add'>+	*val = acrtc-&gt;dm_irq_params.window_param[0].x_start;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3383,8 +3616,8 @@ static int crc_win_y_start_set(void *data, u64 val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.y_start = (uint16_t) val;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.update_win = false;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].y_start = (uint16_t) val;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].update_win = false;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3400,7 +3633,7 @@ static int crc_win_y_start_get(void *data, u64 *val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	*val = acrtc-&gt;dm_irq_params.window_param.y_start;</div><div class='add'>+	*val = acrtc-&gt;dm_irq_params.window_param[0].y_start;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3419,8 +3652,8 @@ static int crc_win_x_end_set(void *data, u64 val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.x_end = (uint16_t) val;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.update_win = false;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].x_end = (uint16_t) val;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].update_win = false;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3436,7 +3669,7 @@ static int crc_win_x_end_get(void *data, u64 *val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	*val = acrtc-&gt;dm_irq_params.window_param.x_end;</div><div class='add'>+	*val = acrtc-&gt;dm_irq_params.window_param[0].x_end;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3455,8 +3688,8 @@ static int crc_win_y_end_set(void *data, u64 val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.y_end = (uint16_t) val;</div><div class='del'>-	acrtc-&gt;dm_irq_params.window_param.update_win = false;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].y_end = (uint16_t) val;</div><div class='add'>+	acrtc-&gt;dm_irq_params.window_param[0].update_win = false;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3472,7 +3705,7 @@ static int crc_win_y_end_get(void *data, u64 *val)</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='del'>-	*val = acrtc-&gt;dm_irq_params.window_param.y_end;</div><div class='add'>+	*val = acrtc-&gt;dm_irq_params.window_param[0].y_end;</div><div class='ctx'> 	spin_unlock_irq(&amp;drm_dev-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3495,13 +3728,14 @@ static int crc_win_update_set(void *data, u64 val)</div><div class='ctx'> 		/* PSR may write to OTG CRC window control register,</div><div class='ctx'> 		 * so close it before starting secure_display.</div><div class='ctx'> 		 */</div><div class='del'>-		amdgpu_dm_psr_disable(acrtc-&gt;dm_irq_params.stream);</div><div class='add'>+		amdgpu_dm_psr_disable(acrtc-&gt;dm_irq_params.stream, true);</div><div class='ctx'> </div><div class='ctx'> 		spin_lock_irq(&amp;adev_to_drm(adev)-&gt;event_lock);</div><div class='ctx'> </div><div class='del'>-		acrtc-&gt;dm_irq_params.window_param.activated = true;</div><div class='del'>-		acrtc-&gt;dm_irq_params.window_param.update_win = true;</div><div class='del'>-		acrtc-&gt;dm_irq_params.window_param.skip_frame_cnt = 0;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[0].enable = true;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[0].update_win = true;</div><div class='add'>+		acrtc-&gt;dm_irq_params.window_param[0].skip_frame_cnt = 0;</div><div class='add'>+		acrtc-&gt;dm_irq_params.crc_window_activated = true;</div><div class='ctx'> </div><div class='ctx'> 		spin_unlock_irq(&amp;adev_to_drm(adev)-&gt;event_lock);</div><div class='ctx'> 		mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='hunk'>@@ -3652,6 +3886,7 @@ static int trigger_hpd_mst_set(void *data, u64 val)</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	struct dc_link *link = NULL;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (val == 1) {</div><div class='ctx'> 		drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='hunk'>@@ -3660,10 +3895,15 @@ static int trigger_hpd_mst_set(void *data, u64 val)</div><div class='ctx'> 			if (aconnector-&gt;dc_link-&gt;type == dc_connection_mst_branch &amp;&amp;</div><div class='ctx'> 			    aconnector-&gt;mst_mgr.aux) {</div><div class='ctx'> 				mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='del'>-				dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_HPD);</div><div class='add'>+				ret = dc_link_detect(aconnector-&gt;dc_link, DETECT_REASON_HPD);</div><div class='ctx'> 				mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='ctx'> </div><div class='del'>-				drm_dp_mst_topology_mgr_set_mst(&amp;aconnector-&gt;mst_mgr, true);</div><div class='add'>+				if (!ret)</div><div class='add'>+					DRM_ERROR("DM_MST: Failed to detect dc link!");</div><div class='add'>+</div><div class='add'>+				ret = drm_dp_mst_topology_mgr_set_mst(&amp;aconnector-&gt;mst_mgr, true);</div><div class='add'>+				if (ret &lt; 0)</div><div class='add'>+					DRM_ERROR("DM_MST: Failed to set the device into MST mode!");</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (val == 0) {</div><div class='hunk'>@@ -3783,7 +4023,7 @@ static int capabilities_show(struct seq_file *m, void *unused)</div><div class='ctx'> </div><div class='ctx'> 	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='ctx'> </div><div class='del'>-	if (hubbub-&gt;funcs-&gt;get_mall_en)</div><div class='add'>+	if (hubbub &amp;&amp; hubbub-&gt;funcs-&gt;get_mall_en)</div><div class='ctx'> 		hubbub-&gt;funcs-&gt;get_mall_en(hubbub, &amp;mall_in_use);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;cap_funcs.get_subvp_en)</div><div class='hunk'>@@ -4031,4 +4271,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev)</div><div class='ctx'> 	debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,</div><div class='ctx'> 				   &amp;disable_hpd_ops);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;dm.dc-&gt;caps.ips_support)</div><div class='add'>+		debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,</div><div class='add'>+					   &amp;ips_status_fops);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h<br/>index 071200473c27..122cdc124b3b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c<br/>index e339c7a8d541..85ce558cefc5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -26,6 +27,7 @@</div><div class='ctx'> #include "amdgpu_dm_hdcp.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='add'>+#include "dc_fused_io.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include &lt;drm/display/drm_hdcp_helper.h&gt;</div><div class='ctx'> #include "hdcp_psp.h"</div><div class='hunk'>@@ -76,6 +78,34 @@ lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)</div><div class='ctx'> 	return dm_helpers_dp_read_dpcd(link-&gt;ctx, link, address, data, size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool lp_atomic_write_poll_read_i2c(</div><div class='add'>+		void *handle,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *write,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *poll,</div><div class='add'>+		struct mod_hdcp_atomic_op_i2c *read,</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = handle;</div><div class='add'>+</div><div class='add'>+	return dm_atomic_write_poll_read_i2c(link, write, poll, read, poll_timeout_us, poll_mask_msb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool lp_atomic_write_poll_read_aux(</div><div class='add'>+		void *handle,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *write,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *poll,</div><div class='add'>+		struct mod_hdcp_atomic_op_aux *read,</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = handle;</div><div class='add'>+</div><div class='add'>+	return dm_atomic_write_poll_read_aux(link, write, poll, read, poll_timeout_us, poll_mask_msb);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct ta_hdcp_shared_memory *hdcp_cmd;</div><div class='hunk'>@@ -171,8 +201,12 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,</div><div class='ctx'> 	struct mod_hdcp_link_adjustment link_adjust;</div><div class='ctx'> 	struct mod_hdcp_display_adjustment display_adjust;</div><div class='ctx'> 	unsigned int conn_index = aconnector-&gt;base.index;</div><div class='add'>+	const struct dc *dc = aconnector-&gt;dc_link-&gt;dc;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_w-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_w-&gt;mutex);</div><div class='add'>+	drm_connector_get(&amp;aconnector-&gt;base);</div><div class='add'>+	if (hdcp_w-&gt;aconnector[conn_index])</div><div class='add'>+		drm_connector_put(&amp;hdcp_w-&gt;aconnector[conn_index]-&gt;base);</div><div class='ctx'> 	hdcp_w-&gt;aconnector[conn_index] = aconnector;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;link_adjust, 0, sizeof(link_adjust));</div><div class='hunk'>@@ -190,6 +224,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,</div><div class='ctx'> 		display_adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE;</div><div class='ctx'> </div><div class='ctx'> 		link_adjust.auth_delay = 2;</div><div class='add'>+		link_adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;</div><div class='ctx'> </div><div class='ctx'> 		if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) {</div><div class='ctx'> 			link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;</div><div class='hunk'>@@ -197,6 +232,9 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,</div><div class='ctx'> 			link_adjust.hdcp1.disable = 1;</div><div class='ctx'> 			link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1;</div><div class='ctx'> 		}</div><div class='add'>+		link_adjust.hdcp2.use_fw_locality_check =</div><div class='add'>+				(dc-&gt;caps.fused_io_supported || dc-&gt;debug.hdcp_lc_force_fw_enable);</div><div class='add'>+		link_adjust.hdcp2.use_sw_locality_fallback = dc-&gt;debug.hdcp_lc_enable_sw_fallback;</div><div class='ctx'> </div><div class='ctx'> 		schedule_delayed_work(&amp;hdcp_w-&gt;property_validate_dwork,</div><div class='ctx'> 				      msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));</div><div class='hunk'>@@ -209,7 +247,6 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,</div><div class='ctx'> 	mod_hdcp_update_display(&amp;hdcp_w-&gt;hdcp, conn_index, &amp;link_adjust, &amp;display_adjust, &amp;hdcp_w-&gt;output);</div><div class='ctx'> </div><div class='ctx'> 	process_output(hdcp_w);</div><div class='del'>-	mutex_unlock(&amp;hdcp_w-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,</div><div class='hunk'>@@ -220,8 +257,7 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,</div><div class='ctx'> 	struct drm_connector_state *conn_state = aconnector-&gt;base.state;</div><div class='ctx'> 	unsigned int conn_index = aconnector-&gt;base.index;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_w-&gt;mutex);</div><div class='del'>-	hdcp_w-&gt;aconnector[conn_index] = aconnector;</div><div class='add'>+	guard(mutex)(&amp;hdcp_w-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	/* the removal of display will invoke auth reset -&gt; hdcp destroy and</div><div class='ctx'> 	 * we'd expect the Content Protection (CP) property changed back to</div><div class='hunk'>@@ -237,9 +273,11 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mod_hdcp_remove_display(&amp;hdcp_w-&gt;hdcp, aconnector-&gt;base.index, &amp;hdcp_w-&gt;output);</div><div class='del'>-</div><div class='add'>+	if (hdcp_w-&gt;aconnector[conn_index]) {</div><div class='add'>+		drm_connector_put(&amp;hdcp_w-&gt;aconnector[conn_index]-&gt;base);</div><div class='add'>+		hdcp_w-&gt;aconnector[conn_index] = NULL;</div><div class='add'>+	}</div><div class='ctx'> 	process_output(hdcp_w);</div><div class='del'>-	mutex_unlock(&amp;hdcp_w-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)</div><div class='hunk'>@@ -247,7 +285,7 @@ void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_inde</div><div class='ctx'> 	struct hdcp_workqueue *hdcp_w = &amp;hdcp_work[link_index];</div><div class='ctx'> 	unsigned int conn_index;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_w-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_w-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	mod_hdcp_reset_connection(&amp;hdcp_w-&gt;hdcp,  &amp;hdcp_w-&gt;output);</div><div class='ctx'> </div><div class='hunk'>@@ -256,11 +294,13 @@ void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_inde</div><div class='ctx'> 	for (conn_index = 0; conn_index &lt; AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) {</div><div class='ctx'> 		hdcp_w-&gt;encryption_status[conn_index] =</div><div class='ctx'> 			MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;</div><div class='add'>+		if (hdcp_w-&gt;aconnector[conn_index]) {</div><div class='add'>+			drm_connector_put(&amp;hdcp_w-&gt;aconnector[conn_index]-&gt;base);</div><div class='add'>+			hdcp_w-&gt;aconnector[conn_index] = NULL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	process_output(hdcp_w);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;hdcp_w-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index)</div><div class='hunk'>@@ -277,7 +317,7 @@ static void event_callback(struct work_struct *work)</div><div class='ctx'> 	hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue,</div><div class='ctx'> 				 callback_dwork);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_work-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work(&amp;hdcp_work-&gt;callback_dwork);</div><div class='ctx'> </div><div class='hunk'>@@ -285,8 +325,6 @@ static void event_callback(struct work_struct *work)</div><div class='ctx'> 			       &amp;hdcp_work-&gt;output);</div><div class='ctx'> </div><div class='ctx'> 	process_output(hdcp_work);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void event_property_update(struct work_struct *work)</div><div class='hunk'>@@ -323,7 +361,7 @@ static void event_property_update(struct work_struct *work)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		drm_modeset_lock(&amp;dev-&gt;mode_config.connection_mutex, NULL);</div><div class='del'>-		mutex_lock(&amp;hdcp_work-&gt;mutex);</div><div class='add'>+		guard(mutex)(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 		if (conn_state-&gt;commit) {</div><div class='ctx'> 			ret = wait_for_completion_interruptible_timeout(&amp;conn_state-&gt;commit-&gt;hw_done,</div><div class='hunk'>@@ -355,7 +393,6 @@ static void event_property_update(struct work_struct *work)</div><div class='ctx'> 			drm_hdcp_update_content_protection(connector,</div><div class='ctx'> 							   DRM_MODE_CONTENT_PROTECTION_DESIRED);</div><div class='ctx'> 		}</div><div class='del'>-		mutex_unlock(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> 		drm_modeset_unlock(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -368,7 +405,7 @@ static void event_property_validate(struct work_struct *work)</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	unsigned int conn_index;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_work-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	for (conn_index = 0; conn_index &lt; AMDGPU_DM_MAX_DISPLAY_INDEX;</div><div class='ctx'> 	     conn_index++) {</div><div class='hunk'>@@ -408,8 +445,6 @@ static void event_property_validate(struct work_struct *work)</div><div class='ctx'> 			schedule_work(&amp;hdcp_work-&gt;property_update_work);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void event_watchdog_timer(struct work_struct *work)</div><div class='hunk'>@@ -420,7 +455,7 @@ static void event_watchdog_timer(struct work_struct *work)</div><div class='ctx'> 				 struct hdcp_workqueue,</div><div class='ctx'> 				      watchdog_timer_dwork);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_work-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work(&amp;hdcp_work-&gt;watchdog_timer_dwork);</div><div class='ctx'> </div><div class='hunk'>@@ -429,8 +464,6 @@ static void event_watchdog_timer(struct work_struct *work)</div><div class='ctx'> 			       &amp;hdcp_work-&gt;output);</div><div class='ctx'> </div><div class='ctx'> 	process_output(hdcp_work);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void event_cpirq(struct work_struct *work)</div><div class='hunk'>@@ -439,13 +472,11 @@ static void event_cpirq(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_work-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	mod_hdcp_process_event(&amp;hdcp_work-&gt;hdcp, MOD_HDCP_EVENT_CPIRQ, &amp;hdcp_work-&gt;output);</div><div class='ctx'> </div><div class='ctx'> 	process_output(hdcp_work);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;hdcp_work-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work)</div><div class='hunk'>@@ -455,6 +486,7 @@ void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work)</div><div class='ctx'> 	for (i = 0; i &lt; hdcp_work-&gt;max_link; i++) {</div><div class='ctx'> 		cancel_delayed_work_sync(&amp;hdcp_work[i].callback_dwork);</div><div class='ctx'> 		cancel_delayed_work_sync(&amp;hdcp_work[i].watchdog_timer_dwork);</div><div class='add'>+		cancel_delayed_work_sync(&amp;hdcp_work[i].property_validate_dwork);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	sysfs_remove_bin_file(kobj, &amp;hdcp_work[0].attr);</div><div class='hunk'>@@ -469,7 +501,6 @@ static bool enable_assr(void *handle, struct dc_link *link)</div><div class='ctx'> 	struct mod_hdcp hdcp = hdcp_work-&gt;hdcp;</div><div class='ctx'> 	struct psp_context *psp = hdcp.config.psp.handle;</div><div class='ctx'> 	struct ta_dtm_shared_memory *dtm_cmd;</div><div class='del'>-	bool res = true;</div><div class='ctx'> </div><div class='ctx'> 	if (!psp-&gt;dtm_context.context.initialized) {</div><div class='ctx'> 		DRM_INFO("Failed to enable ASSR, DTM TA is not initialized.");</div><div class='hunk'>@@ -478,7 +509,7 @@ static bool enable_assr(void *handle, struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	dtm_cmd = (struct ta_dtm_shared_memory *)psp-&gt;dtm_context.context.mem_context.shared_buf;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;psp-&gt;dtm_context.mutex);</div><div class='add'>+	guard(mutex)(&amp;psp-&gt;dtm_context.mutex);</div><div class='ctx'> 	memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));</div><div class='ctx'> </div><div class='ctx'> 	dtm_cmd-&gt;cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE;</div><div class='hunk'>@@ -490,12 +521,10 @@ static bool enable_assr(void *handle, struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	if (dtm_cmd-&gt;dtm_status != TA_DTM_STATUS__SUCCESS) {</div><div class='ctx'> 		DRM_INFO("Failed to enable ASSR");</div><div class='del'>-		res = false;</div><div class='add'>+		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;psp-&gt;dtm_context.mutex);</div><div class='del'>-</div><div class='del'>-	return res;</div><div class='add'>+	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void update_config(void *handle, struct cp_psp_stream_config *config)</div><div class='hunk'>@@ -503,11 +532,13 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)</div><div class='ctx'> 	struct hdcp_workqueue *hdcp_work = handle;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = config-&gt;dm_stream_ctx;</div><div class='ctx'> 	int link_index = aconnector-&gt;dc_link-&gt;link_index;</div><div class='add'>+	unsigned int conn_index = aconnector-&gt;base.index;</div><div class='ctx'> 	struct mod_hdcp_display *display = &amp;hdcp_work[link_index].display;</div><div class='ctx'> 	struct mod_hdcp_link *link = &amp;hdcp_work[link_index].link;</div><div class='ctx'> 	struct hdcp_workqueue *hdcp_w = &amp;hdcp_work[link_index];</div><div class='ctx'> 	struct dc_sink *sink = NULL;</div><div class='ctx'> 	bool link_is_hdcp14 = false;</div><div class='add'>+	const struct dc *dc = aconnector-&gt;dc_link-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	if (config-&gt;dpms_off) {</div><div class='ctx'> 		hdcp_remove_display(hdcp_work, link_index, aconnector);</div><div class='hunk'>@@ -547,7 +578,10 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)</div><div class='ctx'> 	link-&gt;dp.usb4_enabled = config-&gt;usb4_enabled;</div><div class='ctx'> 	display-&gt;adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;</div><div class='ctx'> 	link-&gt;adjust.auth_delay = 2;</div><div class='add'>+	link-&gt;adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;</div><div class='ctx'> 	link-&gt;adjust.hdcp1.disable = 0;</div><div class='add'>+	link-&gt;adjust.hdcp2.use_fw_locality_check = (dc-&gt;caps.fused_io_supported || dc-&gt;debug.hdcp_lc_force_fw_enable);</div><div class='add'>+	link-&gt;adjust.hdcp2.use_sw_locality_fallback = dc-&gt;debug.hdcp_lc_enable_sw_fallback;</div><div class='ctx'> 	hdcp_w-&gt;encryption_status[display-&gt;index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector-&gt;base.index,</div><div class='hunk'>@@ -556,13 +590,14 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)</div><div class='ctx'> 			 (!!aconnector-&gt;base.state) ?</div><div class='ctx'> 			 aconnector-&gt;base.state-&gt;hdcp_content_type : -1);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;hdcp_w-&gt;mutex);</div><div class='add'>+	guard(mutex)(&amp;hdcp_w-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	mod_hdcp_add_display(&amp;hdcp_w-&gt;hdcp, link, display, &amp;hdcp_w-&gt;output);</div><div class='del'>-</div><div class='add'>+	drm_connector_get(&amp;aconnector-&gt;base);</div><div class='add'>+	if (hdcp_w-&gt;aconnector[conn_index])</div><div class='add'>+		drm_connector_put(&amp;hdcp_w-&gt;aconnector[conn_index]-&gt;base);</div><div class='add'>+	hdcp_w-&gt;aconnector[conn_index] = aconnector;</div><div class='ctx'> 	process_output(hdcp_w);</div><div class='del'>-	mutex_unlock(&amp;hdcp_w-&gt;mutex);</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -614,7 +649,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)</div><div class='ctx'>  *	incorrect/corrupted and we should correct our SRM by getting it from PSP</div><div class='ctx'>  */</div><div class='ctx'> static ssize_t srm_data_write(struct file *filp, struct kobject *kobj,</div><div class='del'>-			      struct bin_attribute *bin_attr, char *buffer,</div><div class='add'>+			      const struct bin_attribute *bin_attr, char *buffer,</div><div class='ctx'> 			      loff_t pos, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct hdcp_workqueue *work;</div><div class='hunk'>@@ -638,7 +673,7 @@ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t srm_data_read(struct file *filp, struct kobject *kobj,</div><div class='del'>-			     struct bin_attribute *bin_attr, char *buffer,</div><div class='add'>+			     const struct bin_attribute *bin_attr, char *buffer,</div><div class='ctx'> 			     loff_t pos, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct hdcp_workqueue *work;</div><div class='hunk'>@@ -736,19 +771,30 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,</div><div class='ctx'> 		INIT_DELAYED_WORK(&amp;hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);</div><div class='ctx'> 		INIT_DELAYED_WORK(&amp;hdcp_work[i].property_validate_dwork, event_property_validate);</div><div class='ctx'> </div><div class='del'>-		hdcp_work[i].hdcp.config.psp.handle = &amp;adev-&gt;psp;</div><div class='del'>-		if (dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_1 ||</div><div class='add'>+		struct mod_hdcp_config *config = &amp;hdcp_work[i].hdcp.config;</div><div class='add'>+		struct mod_hdcp_ddc_funcs *ddc_funcs = &amp;config-&gt;ddc.funcs;</div><div class='add'>+</div><div class='add'>+		config-&gt;psp.handle = &amp;adev-&gt;psp;</div><div class='add'>+		if (dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_1  ||</div><div class='ctx'> 		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_14 ||</div><div class='ctx'> 		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_15 ||</div><div class='del'>-		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_5 ||</div><div class='add'>+		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_16 ||</div><div class='add'>+		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_2  ||</div><div class='add'>+		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_21 ||</div><div class='add'>+		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_5  ||</div><div class='ctx'> 		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_51 ||</div><div class='del'>-		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_16)</div><div class='del'>-			hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;</div><div class='del'>-		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);</div><div class='del'>-		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;</div><div class='del'>-		hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;</div><div class='del'>-		hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd;</div><div class='del'>-		hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd;</div><div class='add'>+		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_6  ||</div><div class='add'>+		    dc-&gt;ctx-&gt;dce_version == DCN_VERSION_4_01)</div><div class='add'>+			config-&gt;psp.caps.dtm_v3_supported = 1;</div><div class='add'>+</div><div class='add'>+		config-&gt;ddc.handle = dc_get_link_at_index(dc, i);</div><div class='add'>+</div><div class='add'>+		ddc_funcs-&gt;write_i2c = lp_write_i2c;</div><div class='add'>+		ddc_funcs-&gt;read_i2c = lp_read_i2c;</div><div class='add'>+		ddc_funcs-&gt;write_dpcd = lp_write_dpcd;</div><div class='add'>+		ddc_funcs-&gt;read_dpcd = lp_read_dpcd;</div><div class='add'>+		ddc_funcs-&gt;atomic_write_poll_read_i2c = lp_atomic_write_poll_read_i2c;</div><div class='add'>+		ddc_funcs-&gt;atomic_write_poll_read_aux = lp_atomic_write_poll_read_aux;</div><div class='ctx'> </div><div class='ctx'> 		memset(hdcp_work[i].aconnector, 0,</div><div class='ctx'> 		       sizeof(struct amdgpu_dm_connector *) *</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h<br/>index 69b445b011c8..4faa344f196e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c<br/>index c27063305a13..ac98c746c3de 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -23,6 +24,8 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;acpi/video.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/string.h&gt;</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='hunk'>@@ -44,6 +47,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "ddc_service_types.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> static u32 edid_extract_panel_id(struct edid *edid)</div><div class='ctx'> {</div><div class='hunk'>@@ -52,16 +56,21 @@ static u32 edid_extract_panel_id(struct edid *edid)</div><div class='ctx'> 	       (u32)EDID_PRODUCT_ID(edid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)</div><div class='add'>+static void apply_edid_quirks(struct drm_device *dev, struct edid *edid, struct dc_edid_caps *edid_caps)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t panel_id = edid_extract_panel_id(edid);</div><div class='ctx'> </div><div class='ctx'> 	switch (panel_id) {</div><div class='add'>+	/* Workaround for monitors that need a delay after detecting the link */</div><div class='add'>+	case drm_edid_encode_panel_id('G', 'B', 'T', 0x3215):</div><div class='add'>+		drm_dbg_driver(dev, "Add 10s delay for link detection for panel id %X\n", panel_id);</div><div class='add'>+		edid_caps-&gt;panel_patch.wait_after_dpcd_poweroff_ms = 10000;</div><div class='add'>+		break;</div><div class='ctx'> 	/* Workaround for some monitors which does not work well with FAMS */</div><div class='ctx'> 	case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):</div><div class='ctx'> 	case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):</div><div class='ctx'> 	case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):</div><div class='del'>-		DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);</div><div class='add'>+		drm_dbg_driver(dev, "Disabling FAMS on monitor with panel id %X\n", panel_id);</div><div class='ctx'> 		edid_caps-&gt;panel_patch.disable_fams = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */</div><div class='hunk'>@@ -69,9 +78,15 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)</div><div class='ctx'> 	case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):</div><div class='ctx'> 	case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):</div><div class='ctx'> 	case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):</div><div class='del'>-		DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);</div><div class='add'>+	case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003):</div><div class='add'>+		drm_dbg_driver(dev, "Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);</div><div class='ctx'> 		edid_caps-&gt;panel_patch.remove_sink_ext_caps = true;</div><div class='ctx'> 		break;</div><div class='add'>+	case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154):</div><div class='add'>+	case drm_edid_encode_panel_id('S', 'D', 'C', 0x4171):</div><div class='add'>+		drm_dbg_driver(dev, "Disabling VSC on monitor with panel id %X\n", panel_id);</div><div class='add'>+		edid_caps-&gt;panel_patch.disable_colorimetry = true;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -93,6 +108,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = link-&gt;priv;</div><div class='ctx'> 	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='ctx'> 	struct edid *edid_buf = edid ? (struct edid *) edid-&gt;raw_edid : NULL;</div><div class='ctx'> 	struct cea_sad *sads;</div><div class='ctx'> 	int sad_count = -1;</div><div class='hunk'>@@ -115,6 +131,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(</div><div class='ctx'> 	edid_caps-&gt;serial_number = edid_buf-&gt;serial;</div><div class='ctx'> 	edid_caps-&gt;manufacture_week = edid_buf-&gt;mfg_week;</div><div class='ctx'> 	edid_caps-&gt;manufacture_year = edid_buf-&gt;mfg_year;</div><div class='add'>+	edid_caps-&gt;analog = !(edid_buf-&gt;input &amp; DRM_EDID_INPUT_DIGITAL);</div><div class='ctx'> </div><div class='ctx'> 	drm_edid_get_monitor_name(edid_buf,</div><div class='ctx'> 				  edid_caps-&gt;display_name,</div><div class='hunk'>@@ -122,7 +139,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps(</div><div class='ctx'> </div><div class='ctx'> 	edid_caps-&gt;edid_hdmi = connector-&gt;display_info.is_hdmi;</div><div class='ctx'> </div><div class='del'>-	apply_edid_quirks(edid_buf, edid_caps);</div><div class='add'>+	apply_edid_quirks(dev, edid_buf, edid_caps);</div><div class='ctx'> </div><div class='ctx'> 	sad_count = drm_edid_to_sad((struct edid *) edid-&gt;raw_edid, &amp;sads);</div><div class='ctx'> 	if (sad_count &lt;= 0)</div><div class='hunk'>@@ -363,7 +380,7 @@ void dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 	mst_state = to_drm_dp_mst_topology_state(mst_mgr-&gt;base.state);</div><div class='ctx'> 	new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector-&gt;mst_output_port);</div><div class='ctx'> </div><div class='del'>-	ret = drm_dp_add_payload_part2(mst_mgr, mst_state-&gt;base.state, new_payload);</div><div class='add'>+	ret = drm_dp_add_payload_part2(mst_mgr, new_payload);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='hunk'>@@ -574,10 +591,8 @@ bool dm_helpers_dp_write_dpcd(</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = link-&gt;priv;</div><div class='ctx'> </div><div class='del'>-	if (!aconnector) {</div><div class='del'>-		DRM_ERROR("Failed to find connector for link!");</div><div class='add'>+	if (!aconnector)</div><div class='ctx'> 		return false;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	return drm_dp_dpcd_write(&amp;aconnector-&gt;dm_dp_aux.aux,</div><div class='ctx'> 			address, (uint8_t *)data, size) &gt; 0;</div><div class='hunk'>@@ -618,6 +633,19 @@ bool dm_helpers_submit_i2c(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dm_helpers_execute_fused_io(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		union dmub_rb_cmd *commands,</div><div class='add'>+		uint8_t count,</div><div class='add'>+		uint32_t timeout_us</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *dev = ctx-&gt;driver_context;</div><div class='add'>+</div><div class='add'>+	return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,</div><div class='ctx'> 		bool is_write_cmd,</div><div class='ctx'> 		unsigned char cmd,</div><div class='hunk'>@@ -638,6 +666,8 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,</div><div class='ctx'> 		// write rc data</div><div class='ctx'> 		memmove(rc_data, data, length);</div><div class='ctx'> 		ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// write rc offset</div><div class='hunk'>@@ -646,20 +676,21 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,</div><div class='ctx'> 	rc_offset[2] = (unsigned char) (offset &gt;&gt; 16) &amp; 0xFF;</div><div class='ctx'> 	rc_offset[3] = (unsigned char) (offset &gt;&gt; 24) &amp; 0xFF;</div><div class='ctx'> 	ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err;</div><div class='ctx'> </div><div class='ctx'> 	// write rc length</div><div class='ctx'> 	rc_length[0] = (unsigned char) length &amp; 0xFF;</div><div class='ctx'> 	rc_length[1] = (unsigned char) (length &gt;&gt; 8) &amp; 0xFF;</div><div class='ctx'> 	ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err;</div><div class='ctx'> </div><div class='ctx'> 	// write rc cmd</div><div class='ctx'> 	rc_cmd = cmd | 0x80;</div><div class='ctx'> 	ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &amp;rc_cmd, sizeof(rc_cmd));</div><div class='del'>-</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err;</div><div class='ctx'> </div><div class='ctx'> 	// poll until active is 0</div><div class='ctx'> 	for (i = 0; i &lt; 10; i++) {</div><div class='hunk'>@@ -682,6 +713,10 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,</div><div class='ctx'> 	drm_dbg_dp(aux-&gt;drm_dev, "success = %d\n", success);</div><div class='ctx'> </div><div class='ctx'> 	return success;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)</div><div class='hunk'>@@ -760,7 +795,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(</div><div class='ctx'> 	uint8_t ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	drm_dbg_dp(aux-&gt;drm_dev,</div><div class='del'>-		   "Configure DSC to non-virtual dpcd synaptics\n");</div><div class='add'>+		   "MST_DSC Configure DSC to non-virtual dpcd synaptics\n");</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		/* When DSC is enabled on previous boot and reboot with the hub,</div><div class='hunk'>@@ -773,7 +808,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(</div><div class='ctx'> 			apply_synaptics_fifo_reset_wa(aux);</div><div class='ctx'> </div><div class='ctx'> 		ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &amp;enable, 1);</div><div class='del'>-		DRM_INFO("Send DSC enable to synaptics\n");</div><div class='add'>+		DRM_INFO("MST_DSC Send DSC enable to synaptics\n");</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Synaptics hub not support virtual dpcd,</div><div class='hunk'>@@ -782,7 +817,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (!stream-&gt;link-&gt;link_status.link_active) {</div><div class='ctx'> 			ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &amp;enable, 1);</div><div class='del'>-			DRM_INFO("Send DSC disable to synaptics\n");</div><div class='add'>+			DRM_INFO("MST_DSC Send DSC disable to synaptics\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -806,9 +841,6 @@ bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 	uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;</div><div class='ctx'> 	uint8_t ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (!stream)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='ctx'> 	if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='ctx'> 		if (!aconnector-&gt;dsc_aux)</div><div class='ctx'> 			return false;</div><div class='hunk'>@@ -827,14 +859,14 @@ bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 							DP_DSC_ENABLE,</div><div class='ctx'> 							&amp;enable_passthrough, 1);</div><div class='ctx'> 				drm_dbg_dp(dev,</div><div class='del'>-					   "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",</div><div class='add'>+					   "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",</div><div class='ctx'> 					   ret);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			ret = drm_dp_dpcd_write(aconnector-&gt;dsc_aux,</div><div class='ctx'> 						DP_DSC_ENABLE, &amp;enable_dsc, 1);</div><div class='ctx'> 			drm_dbg_dp(dev,</div><div class='del'>-				   "Sent DSC decoding enable to %s port, ret = %u\n",</div><div class='add'>+				   "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n",</div><div class='ctx'> 				   (port-&gt;passthrough_aux) ? "remote RX" :</div><div class='ctx'> 				   "virtual dpcd",</div><div class='ctx'> 				   ret);</div><div class='hunk'>@@ -842,7 +874,7 @@ bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 			ret = drm_dp_dpcd_write(aconnector-&gt;dsc_aux,</div><div class='ctx'> 						DP_DSC_ENABLE, &amp;enable_dsc, 1);</div><div class='ctx'> 			drm_dbg_dp(dev,</div><div class='del'>-				   "Sent DSC decoding disable to %s port, ret = %u\n",</div><div class='add'>+				   "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n",</div><div class='ctx'> 				   (port-&gt;passthrough_aux) ? "remote RX" :</div><div class='ctx'> 				   "virtual dpcd",</div><div class='ctx'> 				   ret);</div><div class='hunk'>@@ -852,7 +884,7 @@ bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 							DP_DSC_ENABLE,</div><div class='ctx'> 							&amp;enable_passthrough, 1);</div><div class='ctx'> 				drm_dbg_dp(dev,</div><div class='del'>-					   "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",</div><div class='add'>+					   "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",</div><div class='ctx'> 					   ret);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -862,12 +894,12 @@ bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 		if (stream-&gt;sink-&gt;link-&gt;dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {</div><div class='ctx'> 			ret = dm_helpers_dp_write_dpcd(ctx, stream-&gt;link, DP_DSC_ENABLE, &amp;enable_dsc, 1);</div><div class='ctx'> 			drm_dbg_dp(dev,</div><div class='del'>-				   "Send DSC %s to SST RX\n",</div><div class='add'>+				   "SST_DSC Send DSC %s to SST RX\n",</div><div class='ctx'> 				   enable_dsc ? "enable" : "disable");</div><div class='ctx'> 		} else if (stream-&gt;sink-&gt;link-&gt;dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {</div><div class='ctx'> 			ret = dm_helpers_dp_write_dpcd(ctx, stream-&gt;link, DP_DSC_ENABLE, &amp;enable_dsc, 1);</div><div class='ctx'> 			drm_dbg_dp(dev,</div><div class='del'>-				   "Send DSC %s to DP-HDMI PCON\n",</div><div class='add'>+				   "SST_DSC Send DSC %s to DP-HDMI PCON\n",</div><div class='ctx'> 				   enable_dsc ? "enable" : "disable");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -875,6 +907,12 @@ bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	// TODO</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dm_helpers_is_dp_sink_present(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	bool dp_sink_present;</div><div class='hunk'>@@ -891,6 +929,67 @@ bool dm_helpers_is_dp_sink_present(struct dc_link *link)</div><div class='ctx'> 	return dp_sink_present;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int</div><div class='add'>+dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector = data;</div><div class='add'>+	struct acpi_device *acpidev = ACPI_COMPANION(connector-&gt;dev-&gt;dev);</div><div class='add'>+	unsigned short start = block * EDID_LENGTH;</div><div class='add'>+	struct edid *edid;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!acpidev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	/* fetch the entire edid from BIOS */</div><div class='add'>+	r = acpi_video_get_edid(acpidev, ACPI_VIDEO_DISPLAY_LCD, -1, (void *)&amp;edid);</div><div class='add'>+	if (r &lt; 0) {</div><div class='add'>+		drm_dbg(connector-&gt;dev, "Failed to get EDID from ACPI: %d\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+	if (len &gt; r || start &gt; r || start + len &gt; r) {</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* sanity check */</div><div class='add'>+	if (edid-&gt;revision &lt; 4 || !(edid-&gt;input &amp; DRM_EDID_INPUT_DIGITAL) ||</div><div class='add'>+	    (edid-&gt;input &amp; DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_UNDEF) {</div><div class='add'>+		r = -EINVAL;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(buf, (void *)edid + start, len);</div><div class='add'>+	r = 0;</div><div class='add'>+</div><div class='add'>+cleanup:</div><div class='add'>+	kfree(edid);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_edid *</div><div class='add'>+dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_ACPI_EDID)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	switch (connector-&gt;connector_type) {</div><div class='add'>+	case DRM_MODE_CONNECTOR_LVDS:</div><div class='add'>+	case DRM_MODE_CONNECTOR_eDP:</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (connector-&gt;force == DRM_FORCE_OFF)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum dc_edid_status dm_helpers_read_local_edid(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct dc_link *link,</div><div class='hunk'>@@ -899,9 +998,10 @@ enum dc_edid_status dm_helpers_read_local_edid(</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = link-&gt;priv;</div><div class='ctx'> 	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='ctx'> 	struct i2c_adapter *ddc;</div><div class='del'>-	int retry = 3;</div><div class='del'>-	enum dc_edid_status edid_status;</div><div class='del'>-	struct edid *edid;</div><div class='add'>+	int retry = 25;</div><div class='add'>+	enum dc_edid_status edid_status = EDID_NO_RESPONSE;</div><div class='add'>+	const struct drm_edid *drm_edid;</div><div class='add'>+	const struct edid *edid;</div><div class='ctx'> </div><div class='ctx'> 	if (link-&gt;aux_mode)</div><div class='ctx'> 		ddc = &amp;aconnector-&gt;dm_dp_aux.aux.ddc;</div><div class='hunk'>@@ -912,33 +1012,42 @@ enum dc_edid_status dm_helpers_read_local_edid(</div><div class='ctx'> 	 * do check sum and retry to make sure read correct edid.</div><div class='ctx'> 	 */</div><div class='ctx'> 	do {</div><div class='del'>-</div><div class='del'>-		edid = drm_get_edid(&amp;aconnector-&gt;base, ddc);</div><div class='add'>+		drm_edid = dm_helpers_read_acpi_edid(aconnector);</div><div class='add'>+		if (drm_edid)</div><div class='add'>+			drm_info(connector-&gt;dev, "Using ACPI provided EDID for %s\n", connector-&gt;name);</div><div class='add'>+		else</div><div class='add'>+			drm_edid = drm_edid_read_ddc(connector, ddc);</div><div class='add'>+		drm_edid_connector_update(connector, drm_edid);</div><div class='ctx'> </div><div class='ctx'> 		/* DP Compliance Test 4.2.2.6 */</div><div class='ctx'> 		if (link-&gt;aux_mode &amp;&amp; connector-&gt;edid_corrupt)</div><div class='ctx'> 			drm_dp_send_real_edid_checksum(&amp;aconnector-&gt;dm_dp_aux.aux, connector-&gt;real_edid_checksum);</div><div class='ctx'> </div><div class='del'>-		if (!edid &amp;&amp; connector-&gt;edid_corrupt) {</div><div class='add'>+		if (!drm_edid &amp;&amp; connector-&gt;edid_corrupt) {</div><div class='ctx'> 			connector-&gt;edid_corrupt = false;</div><div class='ctx'> 			return EDID_BAD_CHECKSUM;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!edid)</div><div class='del'>-			return EDID_NO_RESPONSE;</div><div class='add'>+		if (!drm_edid)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()</div><div class='add'>+		if (!edid ||</div><div class='add'>+		    edid-&gt;extensions &gt;= sizeof(sink-&gt;dc_edid.raw_edid) / EDID_LENGTH)</div><div class='add'>+			return EDID_BAD_INPUT;</div><div class='ctx'> </div><div class='ctx'> 		sink-&gt;dc_edid.length = EDID_LENGTH * (edid-&gt;extensions + 1);</div><div class='ctx'> 		memmove(sink-&gt;dc_edid.raw_edid, (uint8_t *)edid, sink-&gt;dc_edid.length);</div><div class='ctx'> </div><div class='ctx'> 		/* We don't need the original edid anymore */</div><div class='del'>-		kfree(edid);</div><div class='add'>+		drm_edid_free(drm_edid);</div><div class='ctx'> </div><div class='ctx'> 		edid_status = dm_helpers_parse_edid_caps(</div><div class='ctx'> 						link,</div><div class='ctx'> 						&amp;sink-&gt;dc_edid,</div><div class='ctx'> 						&amp;sink-&gt;edid_caps);</div><div class='ctx'> </div><div class='del'>-	} while (edid_status == EDID_BAD_CHECKSUM &amp;&amp; --retry &gt; 0);</div><div class='add'>+	} while ((edid_status == EDID_BAD_CHECKSUM || edid_status == EDID_NO_RESPONSE) &amp;&amp; --retry &gt; 0);</div><div class='ctx'> </div><div class='ctx'> 	if (edid_status != EDID_OK)</div><div class='ctx'> 		DRM_ERROR("EDID err: %d, on connector: %s",</div><div class='hunk'>@@ -1044,30 +1153,8 @@ void *dm_helpers_allocate_gpu_mem(</div><div class='ctx'> 		long long *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ctx-&gt;driver_context;</div><div class='del'>-	struct dal_allocation *da;</div><div class='del'>-	u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?</div><div class='del'>-		AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='del'>-	da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);</div><div class='del'>-	if (!da)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,</div><div class='del'>-				      domain, &amp;da-&gt;bo,</div><div class='del'>-				      &amp;da-&gt;gpu_addr, &amp;da-&gt;cpu_ptr);</div><div class='del'>-</div><div class='del'>-	*addr = da-&gt;gpu_addr;</div><div class='del'>-</div><div class='del'>-	if (ret) {</div><div class='del'>-		kfree(da);</div><div class='del'>-		return NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* add da to list in dm */</div><div class='del'>-	list_add(&amp;da-&gt;list, &amp;adev-&gt;dm.da_list);</div><div class='del'>-</div><div class='del'>-	return da-&gt;cpu_ptr;</div><div class='add'>+	return dm_allocate_gpu_mem(adev, type, size, addr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dm_helpers_free_gpu_mem(</div><div class='hunk'>@@ -1076,17 +1163,8 @@ void dm_helpers_free_gpu_mem(</div><div class='ctx'> 		void *pvMem)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ctx-&gt;driver_context;</div><div class='del'>-	struct dal_allocation *da;</div><div class='del'>-</div><div class='del'>-	/* walk the da list in DM */</div><div class='del'>-	list_for_each_entry(da, &amp;adev-&gt;dm.da_list, list) {</div><div class='del'>-		if (pvMem == da-&gt;cpu_ptr) {</div><div class='del'>-			amdgpu_bo_free_kernel(&amp;da-&gt;bo, &amp;da-&gt;gpu_addr, &amp;da-&gt;cpu_ptr);</div><div class='del'>-			list_del(&amp;da-&gt;list);</div><div class='del'>-			kfree(da);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+</div><div class='add'>+	dm_free_gpu_mem(adev, type, pvMem);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)</div><div class='hunk'>@@ -1143,6 +1221,8 @@ bool dm_helpers_dp_handle_test_pattern_request(</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = link-&gt;priv;</div><div class='ctx'> 	struct drm_device *dev = aconnector-&gt;base.dev;</div><div class='add'>+	struct dc_state *dc_state = ctx-&gt;dc-&gt;current_state;</div><div class='add'>+	struct clk_mgr *clk_mgr = ctx-&gt;dc-&gt;clk_mgr;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='hunk'>@@ -1243,6 +1323,16 @@ bool dm_helpers_dp_handle_test_pattern_request(</div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;test_pattern.type = test_pattern;</div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;test_pattern.color_space = test_pattern_color_space;</div><div class='ctx'> </div><div class='add'>+	/* Temp W/A for compliance test failure */</div><div class='add'>+	dc_state-&gt;bw_ctx.bw.dcn.clk.p_state_change_support = false;</div><div class='add'>+	dc_state-&gt;bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr-&gt;dc_mode_softmax_enabled ?</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk : clk_mgr-&gt;bw_params-&gt;max_memclk_mhz;</div><div class='add'>+	dc_state-&gt;bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state-&gt;bw_ctx.bw.dcn.clk.dramclk_khz;</div><div class='add'>+	ctx-&gt;dc-&gt;clk_mgr-&gt;funcs-&gt;update_clocks(</div><div class='add'>+			ctx-&gt;dc-&gt;clk_mgr,</div><div class='add'>+			dc_state,</div><div class='add'>+			false);</div><div class='add'>+</div><div class='ctx'> 	dc_link_dp_set_test_pattern(</div><div class='ctx'> 		(struct dc_link *) link,</div><div class='ctx'> 		test_pattern,</div><div class='hunk'>@@ -1261,7 +1351,13 @@ void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)</div><div class='ctx'> </div><div class='ctx'> void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)</div><div class='ctx'> {</div><div class='del'>-	/* TODO: add periodic detection implementation */</div><div class='add'>+	struct amdgpu_device *adev = ctx-&gt;driver_context;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dm.idle_workqueue) {</div><div class='add'>+		adev-&gt;dm.idle_workqueue-&gt;enable = enable;</div><div class='add'>+		if (enable &amp;&amp; !adev-&gt;dm.idle_workqueue-&gt;running &amp;&amp; amdgpu_dm_is_headless(adev))</div><div class='add'>+			schedule_work(&amp;adev-&gt;dm.idle_workqueue-&gt;work);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dm_helpers_dp_mst_update_branch_bandwidth(</div><div class='hunk'>@@ -1306,3 +1402,15 @@ enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	return as_type;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	// TODO</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	// TODO</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c<br/>index 3390f0d8420a..0a2a3f233a0e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -473,8 +474,9 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	unregister_all_irq_handlers(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_dm_irq_suspend(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct drm_device *dev = adev_to_drm(adev);</div><div class='ctx'> 	int src;</div><div class='ctx'> 	struct list_head *hnd_list_h;</div><div class='ctx'> 	struct list_head *hnd_list_l;</div><div class='hunk'>@@ -511,10 +513,12 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);</div><div class='del'>-	return 0;</div><div class='add'>+</div><div class='add'>+	if (dev-&gt;mode_config.poll_enabled)</div><div class='add'>+		drm_kms_helper_poll_disable(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int src;</div><div class='ctx'> 	struct list_head *hnd_list_h, *hnd_list_l;</div><div class='hunk'>@@ -522,7 +526,7 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG_KMS("DM_IRQ: early resume\n");</div><div class='add'>+	drm_dbg(adev_to_drm(adev), "DM_IRQ: early resume\n");</div><div class='ctx'> </div><div class='ctx'> 	/* re-enable short pulse interrupts HW interrupt */</div><div class='ctx'> 	for (src = DC_IRQ_SOURCE_HPD1RX; src &lt;= DC_IRQ_SOURCE_HPD6RX; src++) {</div><div class='hunk'>@@ -533,19 +537,18 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)</div><div class='add'>+void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	struct drm_device *dev = adev_to_drm(adev);</div><div class='ctx'> 	int src;</div><div class='ctx'> 	struct list_head *hnd_list_h, *hnd_list_l;</div><div class='ctx'> 	unsigned long irq_table_flags;</div><div class='ctx'> </div><div class='ctx'> 	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG_KMS("DM_IRQ: resume\n");</div><div class='add'>+	drm_dbg(adev_to_drm(adev), "DM_IRQ: resume\n");</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Renable HW interrupt  for HPD and only since FLIP and VBLANK</div><div class='hunk'>@@ -559,7 +562,9 @@ int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);</div><div class='del'>-	return 0;</div><div class='add'>+</div><div class='add'>+	if (dev-&gt;mode_config.poll_enabled)</div><div class='add'>+		drm_kms_helper_poll_enable(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -894,12 +899,24 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)</div><div class='ctx'> 	struct drm_device *dev = adev_to_drm(adev);</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	struct drm_connector_list_iter iter;</div><div class='add'>+	int irq_type;</div><div class='add'>+	int i;</div><div class='add'>+	bool use_polling = false;</div><div class='add'>+</div><div class='add'>+	/* First, clear all hpd and hpdrx interrupts */</div><div class='add'>+	for (i = DC_IRQ_SOURCE_HPD1; i &lt;= DC_IRQ_SOURCE_HPD6RX; i++) {</div><div class='add'>+		if (!dc_interrupt_set(adev-&gt;dm.dc, i, false))</div><div class='add'>+			drm_err(dev, "Failed to clear hpd(rx) source=%d on init\n",</div><div class='add'>+				i);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='ctx'> 		struct amdgpu_dm_connector *amdgpu_dm_connector;</div><div class='ctx'> 		const struct dc_link *dc_link;</div><div class='ctx'> </div><div class='add'>+		use_polling |= connector-&gt;polled != DRM_CONNECTOR_POLL_HPD;</div><div class='add'>+</div><div class='ctx'> 		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -907,10 +924,31 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='ctx'> </div><div class='add'>+		/*</div><div class='add'>+		 * Get a base driver irq reference for hpd ints for the lifetime</div><div class='add'>+		 * of dm. Note that only hpd interrupt types are registered with</div><div class='add'>+		 * base driver; hpd_rx types aren't. IOW, amdgpu_irq_get/put on</div><div class='add'>+		 * hpd_rx isn't available. DM currently controls hpd_rx</div><div class='add'>+		 * explicitly with dc_interrupt_set()</div><div class='add'>+		 */</div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd != DC_IRQ_SOURCE_INVALID) {</div><div class='del'>-			dc_interrupt_set(adev-&gt;dm.dc,</div><div class='del'>-					dc_link-&gt;irq_source_hpd,</div><div class='del'>-					true);</div><div class='add'>+			irq_type = dc_link-&gt;irq_source_hpd - DC_IRQ_SOURCE_HPD1;</div><div class='add'>+			/*</div><div class='add'>+			 * TODO: There's a mismatch between mode_info.num_hpd</div><div class='add'>+			 * and what bios reports as the # of connectors with hpd</div><div class='add'>+			 * sources. Since the # of hpd source types registered</div><div class='add'>+			 * with base driver == mode_info.num_hpd, we have to</div><div class='add'>+			 * fallback to dc_interrupt_set for the remaining types.</div><div class='add'>+			 */</div><div class='add'>+			if (irq_type &lt; adev-&gt;mode_info.num_hpd) {</div><div class='add'>+				if (amdgpu_irq_get(adev, &amp;adev-&gt;hpd_irq, irq_type))</div><div class='add'>+					drm_err(dev, "DM_IRQ: Failed get HPD for source=%d)!\n",</div><div class='add'>+						dc_link-&gt;irq_source_hpd);</div><div class='add'>+			} else {</div><div class='add'>+				dc_interrupt_set(adev-&gt;dm.dc,</div><div class='add'>+						 dc_link-&gt;irq_source_hpd,</div><div class='add'>+						 true);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {</div><div class='hunk'>@@ -920,6 +958,9 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	drm_connector_list_iter_end(&amp;iter);</div><div class='add'>+</div><div class='add'>+	if (use_polling)</div><div class='add'>+		drm_kms_helper_poll_init(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -935,6 +976,7 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)</div><div class='ctx'> 	struct drm_device *dev = adev_to_drm(adev);</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	struct drm_connector_list_iter iter;</div><div class='add'>+	int irq_type;</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='hunk'>@@ -948,9 +990,18 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='ctx'> </div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd != DC_IRQ_SOURCE_INVALID) {</div><div class='del'>-			dc_interrupt_set(adev-&gt;dm.dc,</div><div class='del'>-					dc_link-&gt;irq_source_hpd,</div><div class='del'>-					false);</div><div class='add'>+			irq_type = dc_link-&gt;irq_source_hpd - DC_IRQ_SOURCE_HPD1;</div><div class='add'>+</div><div class='add'>+			/* TODO: See same TODO in amdgpu_dm_hpd_init() */</div><div class='add'>+			if (irq_type &lt; adev-&gt;mode_info.num_hpd) {</div><div class='add'>+				if (amdgpu_irq_put(adev, &amp;adev-&gt;hpd_irq, irq_type))</div><div class='add'>+					drm_err(dev, "DM_IRQ: Failed put HPD for source=%d!\n",</div><div class='add'>+						dc_link-&gt;irq_source_hpd);</div><div class='add'>+			} else {</div><div class='add'>+				dc_interrupt_set(adev-&gt;dm.dc,</div><div class='add'>+						 dc_link-&gt;irq_source_hpd,</div><div class='add'>+						 false);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {</div><div class='hunk'>@@ -960,4 +1011,7 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	drm_connector_list_iter_end(&amp;iter);</div><div class='add'>+</div><div class='add'>+	if (dev-&gt;mode_config.poll_enabled)</div><div class='add'>+		drm_kms_helper_poll_fini(dev);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h<br/>index 2349238a626b..4f6b58f4f90d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -90,14 +91,14 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);</div><div class='ctx'>  * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_dm_irq_suspend(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.</div><div class='ctx'>  * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> #endif /* __AMDGPU_DM_IRQ_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h<br/>index 5c9303241aeb..3c9995275cbd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2020 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -33,13 +34,15 @@ struct dm_irq_params {</div><div class='ctx'> 	struct mod_vrr_params vrr_params;</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='ctx'> 	int active_planes;</div><div class='del'>-	bool allow_psr_entry;</div><div class='add'>+	bool allow_sr_entry;</div><div class='ctx'> 	struct mod_freesync_config freesync_config;</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DEBUG_FS</div><div class='ctx'> 	enum amdgpu_dm_pipe_crc_source crc_src;</div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='del'>-	struct crc_window_param window_param;</div><div class='add'>+	struct crc_window_param window_param[MAX_CRC_WINDOW_NUM];</div><div class='add'>+	/* At least one CRC window is activated or not*/</div><div class='add'>+	bool crc_window_activated;</div><div class='ctx'> #endif</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c<br/>index 941e96f100f4..dbd1da4d85d3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2012-15 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -23,6 +24,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/vmalloc.h&gt;</div><div class='ctx'> #include &lt;drm/display/drm_dp_helper.h&gt;</div><div class='ctx'> #include &lt;drm/display/drm_dp_mst_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_atomic.h&gt;</div><div class='hunk'>@@ -50,6 +52,9 @@</div><div class='ctx'> </div><div class='ctx'> #define PEAK_FACTOR_X1000 1006</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * This function handles both native AUX and I2C-Over-AUX transactions.</div><div class='add'>+ */</div><div class='ctx'> static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 				  struct drm_dp_aux_msg *msg)</div><div class='ctx'> {</div><div class='hunk'>@@ -58,6 +63,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 	enum aux_return_code_type operation_result;</div><div class='ctx'> 	struct amdgpu_device *adev;</div><div class='ctx'> 	struct ddc_service *ddc;</div><div class='add'>+	uint8_t copy[16];</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(msg-&gt;size &gt; 16))</div><div class='ctx'> 		return -E2BIG;</div><div class='hunk'>@@ -73,6 +79,11 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 			(msg-&gt;request &amp; DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;</div><div class='ctx'> 	payload.defer_delay = 0;</div><div class='ctx'> </div><div class='add'>+	if (payload.write) {</div><div class='add'>+		memcpy(copy, msg-&gt;buffer, msg-&gt;size);</div><div class='add'>+		payload.data = copy;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)-&gt;ddc_service, &amp;payload,</div><div class='ctx'> 				      &amp;operation_result);</div><div class='ctx'> </div><div class='hunk'>@@ -86,15 +97,25 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 	if (adev-&gt;dm.aux_hpd_discon_quirk) {</div><div class='ctx'> 		if (msg-&gt;address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &amp;&amp;</div><div class='ctx'> 			operation_result == AUX_RET_ERROR_HPD_DISCON) {</div><div class='del'>-			result = 0;</div><div class='add'>+			result = msg-&gt;size;</div><div class='ctx'> 			operation_result = AUX_RET_SUCCESS;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (payload.write &amp;&amp; result &gt;= 0)</div><div class='del'>-		result = msg-&gt;size;</div><div class='add'>+	/*</div><div class='add'>+	 * result equals to 0 includes the cases of AUX_DEFER/I2C_DEFER</div><div class='add'>+	 */</div><div class='add'>+	if (payload.write &amp;&amp; result &gt;= 0) {</div><div class='add'>+		if (result) {</div><div class='add'>+			/*one byte indicating partially written bytes*/</div><div class='add'>+			drm_dbg_dp(adev_to_drm(adev), "AUX partially written\n");</div><div class='add'>+			result = payload.data[0];</div><div class='add'>+		} else if (!payload.reply[0])</div><div class='add'>+			/*I2C_ACK|AUX_ACK*/</div><div class='add'>+			result = msg-&gt;size;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (result &lt; 0)</div><div class='add'>+	if (result &lt; 0) {</div><div class='ctx'> 		switch (operation_result) {</div><div class='ctx'> 		case AUX_RET_SUCCESS:</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -113,6 +134,13 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		drm_dbg_dp(adev_to_drm(adev), "DP AUX transfer fail:%d\n", operation_result);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (payload.reply[0])</div><div class='add'>+		drm_dbg_dp(adev_to_drm(adev), "AUX reply command not ACK: 0x%02x.",</div><div class='add'>+			payload.reply[0]);</div><div class='add'>+</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -128,7 +156,7 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector)</div><div class='ctx'> 		dc_sink_release(aconnector-&gt;dc_sink);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	kfree(aconnector-&gt;edid);</div><div class='add'>+	drm_edid_free(aconnector-&gt;drm_edid);</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_cleanup(connector);</div><div class='ctx'> 	drm_dp_mst_put_port_malloc(aconnector-&gt;mst_output_port);</div><div class='hunk'>@@ -154,6 +182,17 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+{</div><div class='add'>+	aconnector-&gt;drm_edid = NULL;</div><div class='add'>+	aconnector-&gt;dsc_aux = NULL;</div><div class='add'>+	aconnector-&gt;mst_output_port-&gt;passthrough_aux = NULL;</div><div class='add'>+	aconnector-&gt;mst_local_bw = 0;</div><div class='add'>+	aconnector-&gt;vc_full_pbn = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='ctx'> amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='hunk'>@@ -181,7 +220,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)</div><div class='ctx'> </div><div class='ctx'> 		dc_sink_release(dc_sink);</div><div class='ctx'> 		aconnector-&gt;dc_sink = NULL;</div><div class='del'>-		aconnector-&gt;edid = NULL;</div><div class='add'>+		amdgpu_dm_mst_reset_mst_connector_setting(aconnector);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	aconnector-&gt;mst_status = MST_STATUS_DEFAULT;</div><div class='hunk'>@@ -210,6 +249,7 @@ bool needs_dsc_aux_workaround(struct dc_link *link)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)</div><div class='ctx'> {</div><div class='ctx'> 	u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F</div><div class='hunk'>@@ -249,7 +289,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto</div><div class='ctx'> 		aconnector-&gt;dsc_aux = &amp;aconnector-&gt;mst_root-&gt;dm_dp_aux.aux;</div><div class='ctx'> </div><div class='ctx'> 	/* synaptics cascaded MST hub case */</div><div class='del'>-	if (!aconnector-&gt;dsc_aux &amp;&amp; is_synaptics_cascaded_panamera(aconnector-&gt;dc_link, port))</div><div class='add'>+	if (is_synaptics_cascaded_panamera(aconnector-&gt;dc_link, port))</div><div class='ctx'> 		aconnector-&gt;dsc_aux = port-&gt;mgr-&gt;aux;</div><div class='ctx'> </div><div class='ctx'> 	if (!aconnector-&gt;dsc_aux)</div><div class='hunk'>@@ -269,6 +309,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> {</div><div class='hunk'>@@ -289,6 +330,34 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *connector = &amp;aconnector-&gt;base;</div><div class='add'>+	struct drm_dp_mst_port *port = aconnector-&gt;mst_output_port;</div><div class='add'>+	struct drm_dp_mst_port *port_parent;</div><div class='add'>+	struct drm_dp_aux *immediate_upstream_aux;</div><div class='add'>+	struct drm_dp_desc branch_desc;</div><div class='add'>+</div><div class='add'>+	if (!port-&gt;parent)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	port_parent = port-&gt;parent-&gt;port_parent;</div><div class='add'>+</div><div class='add'>+	immediate_upstream_aux = port_parent ? &amp;port_parent-&gt;aux : port-&gt;mgr-&gt;aux;</div><div class='add'>+</div><div class='add'>+	if (drm_dp_read_desc(immediate_upstream_aux, &amp;branch_desc, true))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	aconnector-&gt;branch_ieee_oui = (branch_desc.ident.oui[0] &lt;&lt; 16) +</div><div class='add'>+				      (branch_desc.ident.oui[1] &lt;&lt; 8) +</div><div class='add'>+				      (branch_desc.ident.oui[2]);</div><div class='add'>+</div><div class='add'>+	drm_dbg_dp(port-&gt;aux.drm_dev, "MST branch oui 0x%x detected at %s\n",</div><div class='add'>+		   aconnector-&gt;branch_ieee_oui, connector-&gt;name);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int dm_dp_mst_get_modes(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='hunk'>@@ -297,16 +366,18 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)</div><div class='ctx'> 	if (!aconnector)</div><div class='ctx'> 		return drm_add_edid_modes(connector, NULL);</div><div class='ctx'> </div><div class='del'>-	if (!aconnector-&gt;edid) {</div><div class='del'>-		struct edid *edid;</div><div class='add'>+	if (!aconnector-&gt;drm_edid) {</div><div class='add'>+		const struct drm_edid *drm_edid;</div><div class='ctx'> </div><div class='del'>-		edid = drm_dp_mst_get_edid(connector, &amp;aconnector-&gt;mst_root-&gt;mst_mgr, aconnector-&gt;mst_output_port);</div><div class='add'>+		drm_edid = drm_dp_mst_edid_read(connector,</div><div class='add'>+						&amp;aconnector-&gt;mst_root-&gt;mst_mgr,</div><div class='add'>+						aconnector-&gt;mst_output_port);</div><div class='ctx'> </div><div class='del'>-		if (!edid) {</div><div class='add'>+		if (!drm_edid) {</div><div class='ctx'> 			amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='ctx'> 			MST_REMOTE_EDID, false);</div><div class='ctx'> </div><div class='del'>-			drm_connector_update_edid_property(</div><div class='add'>+			drm_edid_connector_update(</div><div class='ctx'> 				&amp;aconnector-&gt;base,</div><div class='ctx'> 				NULL);</div><div class='ctx'> </div><div class='hunk'>@@ -340,7 +411,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		aconnector-&gt;edid = edid;</div><div class='add'>+		aconnector-&gt;drm_edid = drm_edid;</div><div class='ctx'> 		amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='ctx'> 			MST_REMOTE_EDID, true);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -355,10 +426,13 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)</div><div class='ctx'> 		struct dc_sink_init_data init_params = {</div><div class='ctx'> 				.link = aconnector-&gt;dc_link,</div><div class='ctx'> 				.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };</div><div class='add'>+		const struct edid *edid;</div><div class='add'>+</div><div class='add'>+		edid = drm_edid_raw(aconnector-&gt;drm_edid); // FIXME: Get rid of drm_edid_raw()</div><div class='ctx'> 		dc_sink = dc_link_add_remote_sink(</div><div class='ctx'> 			aconnector-&gt;dc_link,</div><div class='del'>-			(uint8_t *)aconnector-&gt;edid,</div><div class='del'>-			(aconnector-&gt;edid-&gt;extensions + 1) * EDID_LENGTH,</div><div class='add'>+			(uint8_t *)edid,</div><div class='add'>+			(edid-&gt;extensions + 1) * EDID_LENGTH,</div><div class='ctx'> 			&amp;init_params);</div><div class='ctx'> </div><div class='ctx'> 		if (!dc_sink) {</div><div class='hunk'>@@ -400,11 +474,13 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)</div><div class='ctx'> </div><div class='ctx'> 		if (aconnector-&gt;dc_sink) {</div><div class='ctx'> 			amdgpu_dm_update_freesync_caps(</div><div class='del'>-					connector, aconnector-&gt;edid);</div><div class='add'>+					connector, aconnector-&gt;drm_edid);</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> 			if (!validate_dsc_caps_on_connector(aconnector))</div><div class='ctx'> 				memset(&amp;aconnector-&gt;dc_sink-&gt;dsc_caps,</div><div class='ctx'> 				       0, sizeof(aconnector-&gt;dc_sink-&gt;dsc_caps));</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> 			if (!retrieve_downstream_port_device(aconnector))</div><div class='ctx'> 				memset(&amp;aconnector-&gt;mst_downstream_port_present,</div><div class='hunk'>@@ -412,10 +488,9 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	drm_connector_update_edid_property(</div><div class='del'>-					&amp;aconnector-&gt;base, aconnector-&gt;edid);</div><div class='add'>+	drm_edid_connector_update(&amp;aconnector-&gt;base, aconnector-&gt;drm_edid);</div><div class='ctx'> </div><div class='del'>-	ret = drm_add_edid_modes(connector, aconnector-&gt;edid);</div><div class='add'>+	ret = drm_edid_connector_add_modes(connector);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -493,7 +568,7 @@ dm_dp_mst_detect(struct drm_connector *connector,</div><div class='ctx'> </div><div class='ctx'> 		dc_sink_release(aconnector-&gt;dc_sink);</div><div class='ctx'> 		aconnector-&gt;dc_sink = NULL;</div><div class='del'>-		aconnector-&gt;edid = NULL;</div><div class='add'>+		amdgpu_dm_mst_reset_mst_connector_setting(aconnector);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='ctx'> 			MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,</div><div class='hunk'>@@ -569,17 +644,20 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,</div><div class='ctx'> 	if (!aconnector)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	DRM_DEBUG_DRIVER("%s: Create aconnector 0x%p for port 0x%p\n", __func__, aconnector, port);</div><div class='add'>+</div><div class='ctx'> 	connector = &amp;aconnector-&gt;base;</div><div class='ctx'> 	aconnector-&gt;mst_output_port = port;</div><div class='ctx'> 	aconnector-&gt;mst_root = master;</div><div class='ctx'> 	amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='ctx'> 			MST_PROBE, true);</div><div class='ctx'> </div><div class='del'>-	if (drm_connector_init(</div><div class='add'>+	if (drm_connector_dynamic_init(</div><div class='ctx'> 		dev,</div><div class='ctx'> 		connector,</div><div class='ctx'> 		&amp;dm_dp_mst_connector_funcs,</div><div class='del'>-		DRM_MODE_CONNECTOR_DisplayPort)) {</div><div class='add'>+		DRM_MODE_CONNECTOR_DisplayPort,</div><div class='add'>+		NULL)) {</div><div class='ctx'> 		kfree(aconnector);</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -613,9 +691,15 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,</div><div class='ctx'> 		&amp;connector-&gt;base,</div><div class='ctx'> 		dev-&gt;mode_config.tile_property,</div><div class='ctx'> 		0);</div><div class='add'>+	connector-&gt;colorspace_property = master-&gt;base.colorspace_property;</div><div class='add'>+	if (connector-&gt;colorspace_property)</div><div class='add'>+		drm_connector_attach_colorspace_property(connector);</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_set_path_property(connector, pathprop);</div><div class='ctx'> </div><div class='add'>+	if (!retrieve_branch_specific_data(aconnector))</div><div class='add'>+		aconnector-&gt;branch_ieee_oui = 0;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Initialize connector state before adding the connectror to drm and</div><div class='ctx'> 	 * framebuffer lists</div><div class='hunk'>@@ -757,6 +841,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	drm_dp_aux_init(&amp;aconnector-&gt;dm_dp_aux.aux);</div><div class='ctx'> 	drm_dp_cec_register_connector(&amp;aconnector-&gt;dm_dp_aux.aux,</div><div class='ctx'> 				      &amp;aconnector-&gt;base);</div><div class='add'>+	drm_dp_dpcd_set_probe(&amp;aconnector-&gt;dm_dp_aux.aux, false);</div><div class='ctx'> </div><div class='ctx'> 	if (aconnector-&gt;base.connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -769,13 +854,20 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	drm_connector_attach_dp_subconnector_property(&amp;aconnector-&gt;base);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int dm_mst_get_pbn_divider(struct dc_link *link)</div><div class='add'>+uint32_t dm_mst_get_pbn_divider(struct dc_link *link)</div><div class='ctx'> {</div><div class='add'>+	uint32_t pbn_div_x100;</div><div class='add'>+	uint64_t dividend, divisor;</div><div class='add'>+</div><div class='ctx'> 	if (!link)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return dc_link_bandwidth_kbps(link,</div><div class='del'>-			dc_link_get_link_cap(link)) / (8 * 1000 * 54);</div><div class='add'>+	dividend = (uint64_t)dc_link_bandwidth_kbps(link, dc_link_get_link_cap(link)) * 100;</div><div class='add'>+	divisor = 8 * 1000 * 54;</div><div class='add'>+</div><div class='add'>+	pbn_div_x100 = div64_u64(dividend, divisor);</div><div class='add'>+</div><div class='add'>+	return dfixed_const(pbn_div_x100) / 100;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct dsc_mst_fairness_params {</div><div class='hunk'>@@ -791,26 +883,29 @@ struct dsc_mst_fairness_params {</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+static uint64_t kbps_to_pbn(int kbps, bool is_peak_pbn)</div><div class='ctx'> {</div><div class='del'>-	u8 link_coding_cap;</div><div class='del'>-	uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;</div><div class='add'>+	uint64_t effective_kbps = (uint64_t)kbps;</div><div class='ctx'> </div><div class='del'>-	link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);</div><div class='del'>-	if (link_coding_cap == DP_128b_132b_ENCODING)</div><div class='del'>-		fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;</div><div class='add'>+	if (is_peak_pbn) {	// add 0.6% (1006/1000) overhead into effective kbps</div><div class='add'>+		effective_kbps *= 1006;</div><div class='add'>+		effective_kbps = div_u64(effective_kbps, 1000);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return fec_overhead_multiplier_x1000;</div><div class='add'>+	return (uint64_t) DIV64_U64_ROUND_UP(effective_kbps * 64, (54 * 8 * 1000));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)</div><div class='add'>+static uint32_t pbn_to_kbps(unsigned int pbn, bool with_margin)</div><div class='ctx'> {</div><div class='del'>-	u64 peak_kbps = kbps;</div><div class='add'>+	uint64_t pbn_effective = (uint64_t)pbn;</div><div class='add'>+</div><div class='add'>+	if (with_margin)	// deduct 0.6% (994/1000) overhead from effective pbn</div><div class='add'>+		pbn_effective *= (1000000 / PEAK_FACTOR_X1000);</div><div class='add'>+	else</div><div class='add'>+		pbn_effective *= 1000;</div><div class='ctx'> </div><div class='del'>-	peak_kbps *= 1006;</div><div class='del'>-	peak_kbps *= fec_overhead_multiplier_x1000;</div><div class='del'>-	peak_kbps = div_u64(peak_kbps, 1000 * 1000);</div><div class='del'>-	return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));</div><div class='add'>+	return DIV_U64_ROUND_UP(pbn_effective * 8 * 54, 64);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,</div><div class='hunk'>@@ -859,11 +954,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p</div><div class='ctx'> 		if (params[i].sink) {</div><div class='ctx'> 			if (params[i].sink-&gt;sink_signal != SIGNAL_TYPE_VIRTUAL &amp;&amp;</div><div class='ctx'> 				params[i].sink-&gt;sink_signal != SIGNAL_TYPE_NONE)</div><div class='del'>-				DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,</div><div class='add'>+				DRM_DEBUG_DRIVER("MST_DSC %s i=%d dispname=%s\n", __func__, i,</div><div class='ctx'> 					params[i].sink-&gt;edid_caps.display_name);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n",</div><div class='ctx'> 			params[i].timing-&gt;flags.DSC,</div><div class='ctx'> 			params[i].timing-&gt;dsc_cfg.bits_per_pixel,</div><div class='ctx'> 			vars[i + k].pbn);</div><div class='hunk'>@@ -881,7 +976,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)</div><div class='ctx'> 	dc_dsc_get_default_config_option(param.sink-&gt;ctx-&gt;dc, &amp;dsc_options);</div><div class='ctx'> 	dsc_options.max_target_bpp_limit_override_x16 = drm_connector-&gt;display_info.max_dsc_bpp * 16;</div><div class='ctx'> </div><div class='del'>-	kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);</div><div class='add'>+	kbps = pbn_to_kbps(pbn, false);</div><div class='ctx'> 	dc_dsc_compute_config(</div><div class='ctx'> 			param.sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='ctx'> 			&amp;param.sink-&gt;dsc_caps.dsc_dec_caps,</div><div class='hunk'>@@ -910,12 +1005,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state,</div><div class='ctx'> 	int link_timeslots_used;</div><div class='ctx'> 	int fair_pbn_alloc;</div><div class='ctx'> 	int ret = 0;</div><div class='del'>-	uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='ctx'> 		if (vars[i + k].dsc_enabled) {</div><div class='ctx'> 			initial_slack[i] =</div><div class='del'>-			kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;</div><div class='add'>+			kbps_to_pbn(params[i].bw_range.max_kbps, false) - vars[i + k].pbn;</div><div class='ctx'> 			bpp_increased[i] = false;</div><div class='ctx'> 			remaining_to_increase += 1;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -1011,7 +1105,7 @@ static int try_disable_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 	int next_index;</div><div class='ctx'> 	int remaining_to_try = 0;</div><div class='ctx'> 	int ret;</div><div class='del'>-	uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);</div><div class='add'>+	int var_pbn;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='ctx'> 		if (vars[i + k].dsc_enabled</div><div class='hunk'>@@ -1041,26 +1135,37 @@ static int try_disable_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 		if (next_index == -1)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='del'>-		vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index);</div><div class='add'>+		var_pbn = vars[next_index].pbn;</div><div class='add'>+		vars[next_index].pbn = kbps_to_pbn(params[next_index].bw_range.stream_kbps, true);</div><div class='ctx'> 		ret = drm_dp_atomic_find_time_slots(state,</div><div class='ctx'> 						    params[next_index].port-&gt;mgr,</div><div class='ctx'> 						    params[next_index].port,</div><div class='ctx'> 						    vars[next_index].pbn);</div><div class='del'>-		if (ret &lt; 0)</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",</div><div class='add'>+						__func__, __LINE__, next_index, ret);</div><div class='add'>+			vars[next_index].pbn = var_pbn;</div><div class='ctx'> 			return ret;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		ret = drm_dp_mst_atomic_check(state);</div><div class='ctx'> 		if (ret == 0) {</div><div class='add'>+			DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index);</div><div class='ctx'> 			vars[next_index].dsc_enabled = false;</div><div class='ctx'> 			vars[next_index].bpp_x16 = 0;</div><div class='ctx'> 		} else {</div><div class='del'>-			vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000);</div><div class='add'>+			DRM_DEBUG_DRIVER("MST_DSC index #%d, restore optimized pbn value\n", next_index);</div><div class='add'>+			vars[next_index].pbn = var_pbn;</div><div class='ctx'> 			ret = drm_dp_atomic_find_time_slots(state,</div><div class='ctx'> 							    params[next_index].port-&gt;mgr,</div><div class='ctx'> 							    params[next_index].port,</div><div class='ctx'> 							    vars[next_index].pbn);</div><div class='del'>-			if (ret &lt; 0)</div><div class='add'>+			if (ret &lt; 0) {</div><div class='add'>+				DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",</div><div class='add'>+							__func__, __LINE__, next_index, ret);</div><div class='ctx'> 				return ret;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		tried[next_index] = true;</div><div class='hunk'>@@ -1069,6 +1174,15 @@ static int try_disable_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n",</div><div class='add'>+				 i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 					    struct dc_state *dc_state,</div><div class='ctx'> 					    struct dc_link *dc_link,</div><div class='hunk'>@@ -1083,7 +1197,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 	int count = 0;</div><div class='ctx'> 	int i, k, ret;</div><div class='ctx'> 	bool debugfs_overwrite = false;</div><div class='del'>-	uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);</div><div class='add'>+	struct drm_connector_state *new_conn_state;</div><div class='ctx'> </div><div class='ctx'> 	memset(params, 0, sizeof(params));</div><div class='ctx'> </div><div class='hunk'>@@ -1091,6 +1205,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 		return PTR_ERR(mst_state);</div><div class='ctx'> </div><div class='ctx'> 	/* Set up params */</div><div class='add'>+	DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state-&gt;stream_count);</div><div class='ctx'> 	for (i = 0; i &lt; dc_state-&gt;stream_count; i++) {</div><div class='ctx'> 		struct dc_dsc_policy dsc_policy = {0};</div><div class='ctx'> </div><div class='hunk'>@@ -1106,6 +1221,14 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 		if (!aconnector-&gt;mst_output_port)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		new_conn_state = drm_atomic_get_new_connector_state(state, &amp;aconnector-&gt;base);</div><div class='add'>+</div><div class='add'>+		if (!new_conn_state) {</div><div class='add'>+			DRM_DEBUG_DRIVER("%s:%d MST_DSC Skip the stream 0x%p with invalid new_conn_state\n",</div><div class='add'>+					__func__, __LINE__, stream);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		stream-&gt;timing.flags.DSC = 0;</div><div class='ctx'> </div><div class='ctx'> 		params[count].timing = &amp;stream-&gt;timing;</div><div class='hunk'>@@ -1119,7 +1242,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 		params[count].num_slices_v = aconnector-&gt;dsc_settings.dsc_num_slices_v;</div><div class='ctx'> 		params[count].bpp_overwrite = aconnector-&gt;dsc_settings.dsc_bits_per_pixel;</div><div class='ctx'> 		params[count].compression_possible = stream-&gt;sink-&gt;dsc_caps.dsc_dec_caps.is_dsc_supported;</div><div class='del'>-		dc_dsc_get_policy_for_timing(params[count].timing, 0, &amp;dsc_policy);</div><div class='add'>+		dc_dsc_get_policy_for_timing(params[count].timing, 0, &amp;dsc_policy, dc_link_get_highest_encoding_format(stream-&gt;link));</div><div class='ctx'> 		if (!dc_dsc_compute_bandwidth_range(</div><div class='ctx'> 				stream-&gt;sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='ctx'> 				stream-&gt;sink-&gt;ctx-&gt;dc-&gt;debug.dsc_min_slice_height_override,</div><div class='hunk'>@@ -1132,9 +1255,14 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 			params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&amp;stream-&gt;timing,</div><div class='ctx'> 					dc_link_get_highest_encoding_format(dc_link));</div><div class='ctx'> </div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC #%d stream 0x%p - max_kbps = %u, min_kbps = %u, uncompressed_kbps = %u\n",</div><div class='add'>+			count, stream, params[count].bw_range.max_kbps, params[count].bw_range.min_kbps,</div><div class='add'>+			params[count].bw_range.stream_kbps);</div><div class='ctx'> 		count++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	DRM_DEBUG_DRIVER("%s: MST_DSC Params set up for %d streams\n", __func__, count);</div><div class='add'>+</div><div class='ctx'> 	if (count == 0) {</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1146,9 +1274,10 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 	*link_vars_start_index += count;</div><div class='ctx'> </div><div class='ctx'> 	/* Try no compression */</div><div class='add'>+	DRM_DEBUG_DRIVER("MST_DSC Try no compression\n");</div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='ctx'> 		vars[i + k].aconnector = params[i].aconnector;</div><div class='del'>-		vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);</div><div class='add'>+		vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.stream_kbps, false);</div><div class='ctx'> 		vars[i + k].dsc_enabled = false;</div><div class='ctx'> 		vars[i + k].bpp_x16 = 0;</div><div class='ctx'> 		ret = drm_dp_atomic_find_time_slots(state, params[i].port-&gt;mgr, params[i].port,</div><div class='hunk'>@@ -1164,10 +1293,13 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	log_dsc_params(count, vars, k);</div><div class='add'>+</div><div class='ctx'> 	/* Try max compression */</div><div class='add'>+	DRM_DEBUG_DRIVER("MST_DSC Try max compression\n");</div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='ctx'> 		if (params[i].compression_possible &amp;&amp; params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {</div><div class='del'>-			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);</div><div class='add'>+			vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.min_kbps, false);</div><div class='ctx'> 			vars[i + k].dsc_enabled = true;</div><div class='ctx'> 			vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;</div><div class='ctx'> 			ret = drm_dp_atomic_find_time_slots(state, params[i].port-&gt;mgr,</div><div class='hunk'>@@ -1175,7 +1307,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 			if (ret &lt; 0)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		} else {</div><div class='del'>-			vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);</div><div class='add'>+			vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.stream_kbps, false);</div><div class='ctx'> 			vars[i + k].dsc_enabled = false;</div><div class='ctx'> 			vars[i + k].bpp_x16 = 0;</div><div class='ctx'> 			ret = drm_dp_atomic_find_time_slots(state, params[i].port-&gt;mgr,</div><div class='hunk'>@@ -1188,14 +1320,26 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,</div><div class='ctx'> 	if (ret != 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	log_dsc_params(count, vars, k);</div><div class='add'>+</div><div class='ctx'> 	/* Optimize degree of compression */</div><div class='add'>+	DRM_DEBUG_DRIVER("MST_DSC Try optimize compression\n");</div><div class='ctx'> 	ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);</div><div class='del'>-	if (ret &lt; 0)</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC Failed to optimize compression\n");</div><div class='ctx'> 		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	log_dsc_params(count, vars, k);</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG_DRIVER("MST_DSC Try disable compression\n");</div><div class='ctx'> 	ret = try_disable_dsc(state, dc_link, params, vars, count, k);</div><div class='del'>-	if (ret &lt; 0)</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC Failed to disable compression\n");</div><div class='ctx'> 		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	log_dsc_params(count, vars, k);</div><div class='ctx'> </div><div class='ctx'> 	set_dsc_configs_from_fairness_vars(params, vars, count, k);</div><div class='ctx'> </div><div class='hunk'>@@ -1217,15 +1361,19 @@ static bool is_dsc_need_re_compute(</div><div class='ctx'> </div><div class='ctx'> 	/* only check phy used by dsc mst branch */</div><div class='ctx'> 	if (dc_link-&gt;type != dc_connection_mst_branch)</div><div class='del'>-		return false;</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='del'>-	if (!(dc_link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||</div><div class='del'>-		dc_link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))</div><div class='del'>-		return false;</div><div class='add'>+	/* add a check for older MST DSC with no virtual DPCDs */</div><div class='add'>+	if (needs_dsc_aux_workaround(dc_link)  &amp;&amp;</div><div class='add'>+		(!(dc_link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||</div><div class='add'>+		dc_link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++)</div><div class='ctx'> 		stream_on_link[i] = NULL;</div><div class='ctx'> </div><div class='add'>+	DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state-&gt;stream_count);</div><div class='add'>+</div><div class='ctx'> 	/* check if there is mode change in new request */</div><div class='ctx'> 	for (i = 0; i &lt; dc_state-&gt;stream_count; i++) {</div><div class='ctx'> 		struct drm_crtc_state *new_crtc_state;</div><div class='hunk'>@@ -1235,6 +1383,8 @@ static bool is_dsc_need_re_compute(</div><div class='ctx'> 		if (!stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		DRM_DEBUG_DRIVER("%s:%d MST_DSC checking #%d stream 0x%p\n", __func__, __LINE__, i, stream);</div><div class='add'>+</div><div class='ctx'> 		/* check if stream using the same link for mst */</div><div class='ctx'> 		if (stream-&gt;link != dc_link)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -1247,8 +1397,11 @@ static bool is_dsc_need_re_compute(</div><div class='ctx'> 		new_stream_on_link_num++;</div><div class='ctx'> </div><div class='ctx'> 		new_conn_state = drm_atomic_get_new_connector_state(state, &amp;aconnector-&gt;base);</div><div class='del'>-		if (!new_conn_state)</div><div class='add'>+		if (!new_conn_state) {</div><div class='add'>+			DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_conn_state for stream 0x%p, aconnector 0x%p\n",</div><div class='add'>+					 __func__, __LINE__, stream, aconnector);</div><div class='ctx'> 			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(new_conn_state))</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -1257,19 +1410,37 @@ static bool is_dsc_need_re_compute(</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state-&gt;crtc);</div><div class='del'>-		if (!new_crtc_state)</div><div class='add'>+		if (!new_crtc_state) {</div><div class='add'>+			DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_crtc_state for crtc of stream 0x%p, aconnector 0x%p\n",</div><div class='add'>+						__func__, __LINE__, stream, aconnector);</div><div class='ctx'> 			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(new_crtc_state))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (new_crtc_state-&gt;enable &amp;&amp; new_crtc_state-&gt;active) {</div><div class='ctx'> 			if (new_crtc_state-&gt;mode_changed || new_crtc_state-&gt;active_changed ||</div><div class='del'>-				new_crtc_state-&gt;connectors_changed)</div><div class='del'>-				return true;</div><div class='add'>+					new_crtc_state-&gt;connectors_changed) {</div><div class='add'>+				DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."</div><div class='add'>+						 "stream 0x%p in new dc_state\n",</div><div class='add'>+						 __func__, __LINE__, stream);</div><div class='add'>+				is_dsc_need_re_compute = true;</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (new_stream_on_link_num == 0) {</div><div class='add'>+		DRM_DEBUG_DRIVER("%s:%d MST_DSC no mode change request for streams in new dc_state\n",</div><div class='add'>+				 __func__, __LINE__);</div><div class='add'>+		is_dsc_need_re_compute = false;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",</div><div class='add'>+			 __func__, dc-&gt;current_state-&gt;stream_count);</div><div class='add'>+</div><div class='ctx'> 	/* check current_state if there stream on link but it is not in</div><div class='ctx'> 	 * new request state</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -1292,11 +1463,18 @@ static bool is_dsc_need_re_compute(</div><div class='ctx'> </div><div class='ctx'> 		if (j == new_stream_on_link_num) {</div><div class='ctx'> 			/* not in new state */</div><div class='add'>+			DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."</div><div class='add'>+					 "stream 0x%p in current dc_state but not in new dc_state\n",</div><div class='add'>+						__func__, __LINE__, stream);</div><div class='ctx'> 			is_dsc_need_re_compute = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+	DRM_DEBUG_DRIVER("%s: MST_DSC dsc recompute %s\n",</div><div class='add'>+			 __func__, is_dsc_need_re_compute ? "required" : "not required");</div><div class='add'>+</div><div class='ctx'> 	return is_dsc_need_re_compute;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1325,6 +1503,9 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 		aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='ctx'> </div><div class='add'>+		DRM_DEBUG_DRIVER("%s: MST_DSC compute mst dsc configs for stream 0x%p, aconnector 0x%p\n",</div><div class='add'>+				__func__, stream, aconnector);</div><div class='add'>+</div><div class='ctx'> 		if (!aconnector || !aconnector-&gt;dc_sink || !aconnector-&gt;mst_output_port)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -1357,8 +1538,11 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,</div><div class='ctx'> 		stream = dc_state-&gt;streams[i];</div><div class='ctx'> </div><div class='ctx'> 		if (stream-&gt;timing.flags.DSC == 1)</div><div class='del'>-			if (dc_stream_add_dsc_to_resource(stream-&gt;ctx-&gt;dc, dc_state, stream) != DC_OK)</div><div class='add'>+			if (dc_stream_add_dsc_to_resource(stream-&gt;ctx-&gt;dc, dc_state, stream) != DC_OK) {</div><div class='add'>+				DRM_DEBUG_DRIVER("%s:%d MST_DSC Failed to request dsc hw resource for stream 0x%p\n",</div><div class='add'>+							__func__, __LINE__, stream);</div><div class='ctx'> 				return -EINVAL;</div><div class='add'>+			}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -1387,6 +1571,9 @@ static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 		aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='ctx'> </div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC pre compute mst dsc configs for #%d stream 0x%p, aconnector 0x%p\n",</div><div class='add'>+					i, stream, aconnector);</div><div class='add'>+</div><div class='ctx'> 		if (!aconnector || !aconnector-&gt;dc_sink || !aconnector-&gt;mst_output_port)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -1476,12 +1663,12 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!is_dsc_precompute_needed(state)) {</div><div class='del'>-		DRM_INFO_ONCE("DSC precompute is not needed.\n");</div><div class='add'>+		DRM_INFO_ONCE("%s:%d MST_DSC dsc precompute is not needed\n", __func__, __LINE__);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	ret = dm_atomic_get_state(state, dm_state_ptr);</div><div class='ctx'> 	if (ret != 0) {</div><div class='del'>-		DRM_INFO_ONCE("dm_atomic_get_state() failed\n");</div><div class='add'>+		DRM_INFO_ONCE("%s:%d MST_DSC dm_atomic_get_state() failed\n", __func__, __LINE__);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	dm_state = *dm_state_ptr;</div><div class='hunk'>@@ -1492,9 +1679,10 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 	 * from dm_state-&gt;context.</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-	local_dc_state = kmemdup(dm_state-&gt;context, sizeof(struct dc_state), GFP_KERNEL);</div><div class='add'>+	local_dc_state = vmalloc(sizeof(struct dc_state));</div><div class='ctx'> 	if (!local_dc_state)</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	memcpy(local_dc_state, dm_state-&gt;context, sizeof(struct dc_state));</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; local_dc_state-&gt;stream_count; i++) {</div><div class='ctx'> 		struct dc_stream_state *stream = dm_state-&gt;context-&gt;streams[i];</div><div class='hunk'>@@ -1502,7 +1690,6 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 		if (ind &gt;= 0) {</div><div class='ctx'> 			struct drm_connector *connector;</div><div class='del'>-			struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 			struct drm_connector_state *drm_new_conn_state;</div><div class='ctx'> 			struct dm_connector_state *dm_new_conn_state;</div><div class='ctx'> 			struct dm_crtc_state *dm_old_crtc_state;</div><div class='hunk'>@@ -1510,15 +1697,17 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 			connector =</div><div class='ctx'> 				amdgpu_dm_find_first_crtc_matching_connector(state,</div><div class='ctx'> 									     state-&gt;crtcs[ind].ptr);</div><div class='del'>-			aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+			if (!connector)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='ctx'> 			drm_new_conn_state =</div><div class='ctx'> 				drm_atomic_get_new_connector_state(state,</div><div class='del'>-								   &amp;aconnector-&gt;base);</div><div class='add'>+								   connector);</div><div class='ctx'> 			dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);</div><div class='ctx'> 			dm_old_crtc_state = to_dm_crtc_state(state-&gt;crtcs[ind].old_state);</div><div class='ctx'> </div><div class='ctx'> 			local_dc_state-&gt;streams[i] =</div><div class='del'>-				create_validate_stream_for_sink(aconnector,</div><div class='add'>+				create_validate_stream_for_sink(connector,</div><div class='ctx'> 								&amp;state-&gt;crtcs[ind].new_state-&gt;mode,</div><div class='ctx'> 								dm_new_conn_state,</div><div class='ctx'> 								dm_old_crtc_state-&gt;stream);</div><div class='hunk'>@@ -1534,7 +1723,8 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 	ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);</div><div class='ctx'> 	if (ret != 0) {</div><div class='del'>-		DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");</div><div class='add'>+		DRM_INFO_ONCE("%s:%d MST_DSC dsc pre_compute_mst_dsc_configs_for_state() failed\n",</div><div class='add'>+				__func__, __LINE__);</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto clean_exit;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1548,12 +1738,15 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 		if (local_dc_state-&gt;streams[i] &amp;&amp;</div><div class='ctx'> 		    dc_is_timing_changed(stream, local_dc_state-&gt;streams[i])) {</div><div class='del'>-			DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i);</div><div class='add'>+			DRM_INFO_ONCE("%s:%d MST_DSC crtc[%d] needs mode_change\n", __func__, __LINE__, i);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			int ind = find_crtc_index_in_state_by_stream(state, stream);</div><div class='ctx'> </div><div class='del'>-			if (ind &gt;= 0)</div><div class='add'>+			if (ind &gt;= 0) {</div><div class='add'>+				DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n",</div><div class='add'>+						__func__, __LINE__, stream);</div><div class='ctx'> 				state-&gt;crtcs[ind].new_state-&gt;mode_changed = 0;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> clean_exit:</div><div class='hunk'>@@ -1564,119 +1757,218 @@ clean_exit:</div><div class='ctx'> 			dc_stream_release(local_dc_state-&gt;streams[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	kfree(local_dc_state);</div><div class='add'>+	vfree(local_dc_state);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned int kbps_from_pbn(unsigned int pbn)</div><div class='add'>+static bool is_dsc_common_config_possible(struct dc_stream_state *stream,</div><div class='add'>+					  struct dc_dsc_bw_range *bw_range)</div><div class='ctx'> {</div><div class='del'>-	unsigned int kbps = pbn;</div><div class='add'>+	struct dc_dsc_policy dsc_policy = {0};</div><div class='add'>+	bool is_dsc_possible;</div><div class='ctx'> </div><div class='del'>-	kbps *= (1000000 / PEAK_FACTOR_X1000);</div><div class='del'>-	kbps *= 8;</div><div class='del'>-	kbps *= 54;</div><div class='del'>-	kbps /= 64;</div><div class='add'>+	dc_dsc_get_policy_for_timing(&amp;stream-&gt;timing, 0, &amp;dsc_policy, dc_link_get_highest_encoding_format(stream-&gt;link));</div><div class='add'>+	is_dsc_possible = dc_dsc_compute_bandwidth_range(stream-&gt;sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='add'>+							 stream-&gt;sink-&gt;ctx-&gt;dc-&gt;debug.dsc_min_slice_height_override,</div><div class='add'>+							 dsc_policy.min_target_bpp * 16,</div><div class='add'>+							 dsc_policy.max_target_bpp * 16,</div><div class='add'>+							 &amp;stream-&gt;sink-&gt;dsc_caps.dsc_dec_caps,</div><div class='add'>+							 &amp;stream-&gt;timing, dc_link_get_highest_encoding_format(stream-&gt;link), bw_range);</div><div class='ctx'> </div><div class='del'>-	return kbps;</div><div class='add'>+	return is_dsc_possible;</div><div class='ctx'> }</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='del'>-static bool is_dsc_common_config_possible(struct dc_stream_state *stream,</div><div class='del'>-					  struct dc_dsc_bw_range *bw_range)</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)</div><div class='ctx'> {</div><div class='del'>-	struct dc_dsc_policy dsc_policy = {0};</div><div class='add'>+	uint32_t total_data_bw_efficiency_x10000 = 0;</div><div class='add'>+	uint32_t link_rate_per_lane_kbps = 0;</div><div class='add'>+	enum dc_link_rate link_rate;</div><div class='add'>+	union lane_count_set lane_count;</div><div class='add'>+	u8 dp_link_encoding;</div><div class='add'>+	u8 link_bw_set = 0;</div><div class='add'>+	u8 data[16] = {0};</div><div class='add'>+</div><div class='add'>+	*cur_link_bw = 0;</div><div class='add'>+</div><div class='add'>+	if (drm_dp_dpcd_read(aux, DP_LINK_BW_SET, data, 16) != 16)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET];</div><div class='add'>+	link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET];</div><div class='add'>+	lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET];</div><div class='add'>+</div><div class='add'>+	drm_dbg_dp(aux-&gt;drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n",</div><div class='add'>+		   dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET);</div><div class='add'>+</div><div class='add'>+	switch (dp_link_encoding) {</div><div class='add'>+	case DP_8b_10b_ENCODING:</div><div class='add'>+		link_rate = link_bw_set;</div><div class='add'>+		link_rate_per_lane_kbps = link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;</div><div class='add'>+		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;</div><div class='add'>+		total_data_bw_efficiency_x10000 /= 100;</div><div class='add'>+		total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;</div><div class='add'>+		break;</div><div class='add'>+	case DP_128b_132b_ENCODING:</div><div class='add'>+		switch (link_bw_set) {</div><div class='add'>+		case DP_LINK_BW_10:</div><div class='add'>+			link_rate = LINK_RATE_UHBR10;</div><div class='add'>+			break;</div><div class='add'>+		case DP_LINK_BW_13_5:</div><div class='add'>+			link_rate = LINK_RATE_UHBR13_5;</div><div class='add'>+			break;</div><div class='add'>+		case DP_LINK_BW_20:</div><div class='add'>+			link_rate = LINK_RATE_UHBR20;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	dc_dsc_get_policy_for_timing(&amp;stream-&gt;timing, 0, &amp;dsc_policy);</div><div class='del'>-	dc_dsc_compute_bandwidth_range(stream-&gt;sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='del'>-				       stream-&gt;sink-&gt;ctx-&gt;dc-&gt;debug.dsc_min_slice_height_override,</div><div class='del'>-				       dsc_policy.min_target_bpp * 16,</div><div class='del'>-				       dsc_policy.max_target_bpp * 16,</div><div class='del'>-				       &amp;stream-&gt;sink-&gt;dsc_caps.dsc_dec_caps,</div><div class='del'>-				       &amp;stream-&gt;timing, dc_link_get_highest_encoding_format(stream-&gt;link), bw_range);</div><div class='add'>+		link_rate_per_lane_kbps = link_rate * 10000;</div><div class='add'>+		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return bw_range-&gt;max_target_bpp_x16 &amp;&amp; bw_range-&gt;min_target_bpp_x16;</div><div class='add'>+	*cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;</div><div class='add'>+	return true;</div><div class='ctx'> }</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> enum dc_status dm_dp_mst_is_port_support_mode(</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='del'>-	int bpp, pbn, branch_max_throughput_mps = 0;</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+	int branch_max_throughput_mps = 0;</div><div class='ctx'> 	struct dc_link_settings cur_link_settings;</div><div class='del'>-	unsigned int end_to_end_bw_in_kbps = 0;</div><div class='del'>-	unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;</div><div class='add'>+	uint32_t end_to_end_bw_in_kbps = 0;</div><div class='add'>+	uint32_t root_link_bw_in_kbps = 0;</div><div class='add'>+	uint32_t virtual_channel_bw_in_kbps = 0;</div><div class='ctx'> 	struct dc_dsc_bw_range bw_range = {0};</div><div class='ctx'> 	struct dc_dsc_config_options dsc_options = {0};</div><div class='add'>+	uint32_t stream_kbps;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Consider the case with the depth of the mst topology tree is equal or less than 2</div><div class='del'>-	 * A. When dsc bitstream can be transmitted along the entire path</div><div class='del'>-	 *    1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND</div><div class='del'>-	 *    2. dsc passthrough supported at MST branch, or</div><div class='del'>-	 *    3. dsc decoding supported at leaf MST device</div><div class='del'>-	 *    Use maximum dsc compression as bw constraint</div><div class='del'>-	 * B. When dsc bitstream cannot be transmitted along the entire path</div><div class='del'>-	 *    Use native bw as bw constraint</div><div class='add'>+	/* DSC unnecessary case</div><div class='add'>+	 * Check if timing could be supported within end-to-end BW</div><div class='ctx'> 	 */</div><div class='del'>-	if (is_dsc_common_config_possible(stream, &amp;bw_range) &amp;&amp;</div><div class='del'>-	   (aconnector-&gt;mst_output_port-&gt;passthrough_aux ||</div><div class='del'>-	    aconnector-&gt;dsc_aux == &amp;aconnector-&gt;mst_output_port-&gt;aux)) {</div><div class='del'>-		cur_link_settings = stream-&gt;link-&gt;verified_link_cap;</div><div class='del'>-		upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector-&gt;dc_link, &amp;cur_link_settings);</div><div class='del'>-		down_link_bw_in_kbps = kbps_from_pbn(aconnector-&gt;mst_output_port-&gt;full_pbn);</div><div class='del'>-</div><div class='del'>-		/* pick the end to end bw bottleneck */</div><div class='del'>-		end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, down_link_bw_in_kbps);</div><div class='del'>-</div><div class='del'>-		if (end_to_end_bw_in_kbps &lt; bw_range.min_kbps) {</div><div class='del'>-			DRM_DEBUG_DRIVER("maximum dsc compression cannot fit into end-to-end bandwidth\n");</div><div class='del'>-			return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='del'>-		}</div><div class='add'>+	stream_kbps =</div><div class='add'>+		dc_bandwidth_in_kbps_from_timing(&amp;stream-&gt;timing,</div><div class='add'>+			dc_link_get_highest_encoding_format(stream-&gt;link));</div><div class='add'>+	cur_link_settings = stream-&gt;link-&gt;verified_link_cap;</div><div class='add'>+	root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector-&gt;dc_link, &amp;cur_link_settings);</div><div class='add'>+	virtual_channel_bw_in_kbps = pbn_to_kbps(aconnector-&gt;mst_output_port-&gt;full_pbn, true);</div><div class='add'>+</div><div class='add'>+	/* pick the end to end bw bottleneck */</div><div class='add'>+	end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);</div><div class='add'>+</div><div class='add'>+	if (stream_kbps &lt;= end_to_end_bw_in_kbps) {</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC no dsc required. End-to-end bw sufficient\n");</div><div class='add'>+		return DC_OK;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (end_to_end_bw_in_kbps &lt; bw_range.stream_kbps) {</div><div class='del'>-			dc_dsc_get_default_config_option(stream-&gt;link-&gt;dc, &amp;dsc_options);</div><div class='del'>-			dsc_options.max_target_bpp_limit_override_x16 = aconnector-&gt;base.display_info.max_dsc_bpp * 16;</div><div class='del'>-			if (dc_dsc_compute_config(stream-&gt;sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='del'>-					&amp;stream-&gt;sink-&gt;dsc_caps.dsc_dec_caps,</div><div class='del'>-					&amp;dsc_options,</div><div class='del'>-					end_to_end_bw_in_kbps,</div><div class='del'>-					&amp;stream-&gt;timing,</div><div class='del'>-					dc_link_get_highest_encoding_format(stream-&gt;link),</div><div class='del'>-					&amp;stream-&gt;timing.dsc_cfg)) {</div><div class='del'>-				stream-&gt;timing.flags.DSC = 1;</div><div class='del'>-				DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc and dsc config found\n");</div><div class='add'>+	/*DSC necessary case*/</div><div class='add'>+	if (!aconnector-&gt;dsc_aux)</div><div class='add'>+		return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+</div><div class='add'>+	if (is_dsc_common_config_possible(stream, &amp;bw_range)) {</div><div class='add'>+</div><div class='add'>+		/*capable of dsc passthough. dsc bitstream along the entire path*/</div><div class='add'>+		if (aconnector-&gt;mst_output_port-&gt;passthrough_aux) {</div><div class='add'>+			if (bw_range.min_kbps &gt; end_to_end_bw_in_kbps) {</div><div class='add'>+				DRM_DEBUG_DRIVER("MST_DSC dsc passthrough and decode at endpoint"</div><div class='add'>+						 "Max dsc compression bw can't fit into end-to-end bw\n");</div><div class='add'>+				return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/*dsc bitstream decoded at the dp last link*/</div><div class='add'>+			struct drm_dp_mst_port *immediate_upstream_port = NULL;</div><div class='add'>+			uint32_t end_link_bw = 0;</div><div class='add'>+</div><div class='add'>+			/*Get last DP link BW capability. Mode shall be supported by Legacy peer*/</div><div class='add'>+			if (aconnector-&gt;mst_output_port-&gt;pdt != DP_PEER_DEVICE_DP_LEGACY_CONV &amp;&amp;</div><div class='add'>+				aconnector-&gt;mst_output_port-&gt;pdt != DP_PEER_DEVICE_NONE) {</div><div class='add'>+				if (aconnector-&gt;vc_full_pbn != aconnector-&gt;mst_output_port-&gt;full_pbn) {</div><div class='add'>+					dp_get_link_current_set_bw(&amp;aconnector-&gt;mst_output_port-&gt;aux, &amp;end_link_bw);</div><div class='add'>+					aconnector-&gt;vc_full_pbn = aconnector-&gt;mst_output_port-&gt;full_pbn;</div><div class='add'>+					aconnector-&gt;mst_local_bw = end_link_bw;</div><div class='add'>+				} else {</div><div class='add'>+					end_link_bw = aconnector-&gt;mst_local_bw;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if (end_link_bw &gt; 0 &amp;&amp;</div><div class='add'>+				    stream_kbps &gt; end_link_bw &amp;&amp;</div><div class='add'>+				    aconnector-&gt;branch_ieee_oui != DP_BRANCH_DEVICE_ID_90CC24) {</div><div class='add'>+					DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link. "</div><div class='add'>+							 "Mode required bw can't fit into last link\n");</div><div class='add'>+					return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/*Get virtual channel bandwidth between source and the link before the last link*/</div><div class='add'>+			if (aconnector-&gt;mst_output_port-&gt;parent-&gt;port_parent)</div><div class='add'>+				immediate_upstream_port = aconnector-&gt;mst_output_port-&gt;parent-&gt;port_parent;</div><div class='add'>+</div><div class='add'>+			if (immediate_upstream_port) {</div><div class='add'>+				virtual_channel_bw_in_kbps = pbn_to_kbps(immediate_upstream_port-&gt;full_pbn, true);</div><div class='add'>+				virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);</div><div class='ctx'> 			} else {</div><div class='del'>-				DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc but dsc config not found\n");</div><div class='add'>+				/* For topology LCT 1 case - only one mstb*/</div><div class='add'>+				virtual_channel_bw_in_kbps = root_link_bw_in_kbps;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (bw_range.min_kbps &gt; virtual_channel_bw_in_kbps) {</div><div class='add'>+				DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."</div><div class='add'>+						 "Max dsc compression can't fit into MST available bw\n");</div><div class='ctx'> 				return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-	} else {</div><div class='del'>-		/* check if mode could be supported within full_pbn */</div><div class='del'>-		bpp = convert_dc_color_depth_into_bpc(stream-&gt;timing.display_color_depth) * 3;</div><div class='del'>-		pbn = drm_dp_calc_pbn_mode(stream-&gt;timing.pix_clk_100hz / 10, bpp &lt;&lt; 4);</div><div class='del'>-		if (pbn &gt; aconnector-&gt;mst_output_port-&gt;full_pbn)</div><div class='add'>+</div><div class='add'>+		/*Confirm if we can obtain dsc config*/</div><div class='add'>+		dc_dsc_get_default_config_option(stream-&gt;link-&gt;dc, &amp;dsc_options);</div><div class='add'>+		dsc_options.max_target_bpp_limit_override_x16 = aconnector-&gt;base.display_info.max_dsc_bpp * 16;</div><div class='add'>+		if (dc_dsc_compute_config(stream-&gt;sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='add'>+				&amp;stream-&gt;sink-&gt;dsc_caps.dsc_dec_caps,</div><div class='add'>+				&amp;dsc_options,</div><div class='add'>+				end_to_end_bw_in_kbps,</div><div class='add'>+				&amp;stream-&gt;timing,</div><div class='add'>+				dc_link_get_highest_encoding_format(stream-&gt;link),</div><div class='add'>+				&amp;stream-&gt;timing.dsc_cfg)) {</div><div class='add'>+			stream-&gt;timing.flags.DSC = 1;</div><div class='add'>+			DRM_DEBUG_DRIVER("MST_DSC require dsc and dsc config found\n");</div><div class='add'>+		} else {</div><div class='add'>+			DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find appropriate dsc config\n");</div><div class='ctx'> 			return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='del'>-	}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */</div><div class='del'>-	switch (stream-&gt;timing.pixel_encoding) {</div><div class='del'>-	case PIXEL_ENCODING_RGB:</div><div class='del'>-	case PIXEL_ENCODING_YCBCR444:</div><div class='del'>-		branch_max_throughput_mps =</div><div class='del'>-			aconnector-&gt;dc_sink-&gt;dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;</div><div class='del'>-		break;</div><div class='del'>-	case PIXEL_ENCODING_YCBCR422:</div><div class='del'>-	case PIXEL_ENCODING_YCBCR420:</div><div class='del'>-		branch_max_throughput_mps =</div><div class='del'>-			aconnector-&gt;dc_sink-&gt;dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+		/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */</div><div class='add'>+		switch (stream-&gt;timing.pixel_encoding) {</div><div class='add'>+		case PIXEL_ENCODING_RGB:</div><div class='add'>+		case PIXEL_ENCODING_YCBCR444:</div><div class='add'>+			branch_max_throughput_mps =</div><div class='add'>+				aconnector-&gt;dc_sink-&gt;dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;</div><div class='add'>+			break;</div><div class='add'>+		case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+		case PIXEL_ENCODING_YCBCR420:</div><div class='add'>+			branch_max_throughput_mps =</div><div class='add'>+				aconnector-&gt;dc_sink-&gt;dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (branch_max_throughput_mps != 0 &amp;&amp;</div><div class='del'>-		((stream-&gt;timing.pix_clk_100hz / 10) &gt;  branch_max_throughput_mps * 1000))</div><div class='add'>+		if (branch_max_throughput_mps != 0 &amp;&amp;</div><div class='add'>+			((stream-&gt;timing.pix_clk_100hz / 10) &gt;  branch_max_throughput_mps * 1000)) {</div><div class='add'>+			DRM_DEBUG_DRIVER("MST_DSC require dsc but max throughput mps fails\n");</div><div class='add'>+			return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n");</div><div class='ctx'> 		return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='del'>-</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h<br/>index 37c820ab0fdb..6f7ea684b555 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2012-15 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -46,8 +47,8 @@</div><div class='ctx'> #define SYNAPTICS_CASCADED_HUB_ID  0x5A</div><div class='ctx'> #define IS_SYNAPTICS_CASCADED_PANAMERA(devName, data) ((IS_SYNAPTICS_PANAMERA(devName) &amp;&amp; ((int)data[2] == SYNAPTICS_CASCADED_HUB_ID)) ? 1 : 0)</div><div class='ctx'> </div><div class='del'>-#define PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B	1031</div><div class='del'>-#define PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B	1000</div><div class='add'>+#define PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B     1031</div><div class='add'>+#define PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B  1000</div><div class='ctx'> </div><div class='ctx'> enum mst_msg_ready_type {</div><div class='ctx'> 	NONE_MSG_RDY_EVENT = 0,</div><div class='hunk'>@@ -59,7 +60,7 @@ enum mst_msg_ready_type {</div><div class='ctx'> struct amdgpu_display_manager;</div><div class='ctx'> struct amdgpu_dm_connector;</div><div class='ctx'> </div><div class='del'>-int dm_mst_get_pbn_divider(struct dc_link *link);</div><div class='add'>+uint32_t dm_mst_get_pbn_divider(struct dc_link *link);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,</div><div class='ctx'> 				       struct amdgpu_dm_connector *aconnector,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c<br/>index 8a4c40b4c27e..2e3ee78999d9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c</a></div><div class='hunk'>@@ -26,8 +26,10 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_blend.h&gt;</div><div class='add'>+#include "drm/drm_framebuffer.h"</div><div class='ctx'> #include &lt;drm/drm_gem_atomic_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_plane_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_gem_framebuffer_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='hunk'>@@ -35,6 +37,7 @@</div><div class='ctx'> #include "amdgpu_display.h"</div><div class='ctx'> #include "amdgpu_dm_trace.h"</div><div class='ctx'> #include "amdgpu_dm_plane.h"</div><div class='add'>+#include "amdgpu_dm_colorop.h"</div><div class='ctx'> #include "gc/gc_11_0_0_offset.h"</div><div class='ctx'> #include "gc/gc_11_0_0_sh_mask.h"</div><div class='ctx'> </div><div class='hunk'>@@ -90,9 +93,9 @@ enum dm_micro_swizzle {</div><div class='ctx'> 	MICRO_SWIZZLE_R = 3</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd)</div><div class='add'>+const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier)</div><div class='ctx'> {</div><div class='del'>-	return amdgpu_lookup_format_info(cmd-&gt;pixel_format, cmd-&gt;modifier[0]);</div><div class='add'>+	return amdgpu_lookup_format_info(pixel_format, modifier);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,</div><div class='hunk'>@@ -104,8 +107,6 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state</div><div class='ctx'> 	*global_alpha = false;</div><div class='ctx'> 	*global_alpha_value = 0xff;</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;plane-&gt;type != DRM_PLANE_TYPE_OVERLAY)</div><div class='del'>-		return;</div><div class='ctx'> </div><div class='ctx'> 	if (plane_state-&gt;pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||</div><div class='ctx'> 		plane_state-&gt;pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {</div><div class='hunk'>@@ -146,7 +147,7 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64</div><div class='ctx'> </div><div class='ctx'> 	if (*cap - *size &lt; 1) {</div><div class='ctx'> 		uint64_t new_cap = *cap * 2;</div><div class='del'>-		uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);</div><div class='add'>+		uint64_t *new_mods = kmalloc_array(new_cap, sizeof(uint64_t), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 		if (!new_mods) {</div><div class='ctx'> 			kfree(*mods);</div><div class='hunk'>@@ -177,7 +178,7 @@ static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier</div><div class='ctx'> 	return AMD_FMT_MOD_GET(TILE, modifier);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,</div><div class='add'>+static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(struct dc_tiling_info *tiling_info,</div><div class='ctx'> 							     uint64_t tiling_flags)</div><div class='ctx'> {</div><div class='ctx'> 	/* Fill GFX8 params */</div><div class='hunk'>@@ -190,6 +191,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_inf</div><div class='ctx'> 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);</div><div class='ctx'> 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);</div><div class='ctx'> </div><div class='add'>+		tiling_info-&gt;gfxversion = DcGfxVersion8;</div><div class='ctx'> 		/* XXX fix me for VI */</div><div class='ctx'> 		tiling_info-&gt;gfx8.num_banks = num_banks;</div><div class='ctx'> 		tiling_info-&gt;gfx8.array_mode =</div><div class='hunk'>@@ -210,7 +212,7 @@ static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_inf</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,</div><div class='del'>-							      union dc_tiling_info *tiling_info)</div><div class='add'>+							      struct dc_tiling_info *tiling_info)</div><div class='ctx'> {</div><div class='ctx'> 	/* Fill GFX9 params */</div><div class='ctx'> 	tiling_info-&gt;gfx9.num_pipes =</div><div class='hunk'>@@ -231,7 +233,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgp</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,</div><div class='del'>-								union dc_tiling_info *tiling_info,</div><div class='add'>+								struct dc_tiling_info *tiling_info,</div><div class='ctx'> 								uint64_t modifier)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);</div><div class='hunk'>@@ -261,7 +263,7 @@ static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amd</div><div class='ctx'> static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,</div><div class='ctx'> 					const enum surface_pixel_format format,</div><div class='ctx'> 					const enum dc_rotation_angle rotation,</div><div class='del'>-					const union dc_tiling_info *tiling_info,</div><div class='add'>+					const struct dc_tiling_info *tiling_info,</div><div class='ctx'> 					const struct dc_plane_dcc_param *dcc,</div><div class='ctx'> 					const struct dc_plane_address *address,</div><div class='ctx'> 					const struct plane_size *plane_size)</div><div class='hunk'>@@ -276,8 +278,11 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!dcc-&gt;enable)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (format &gt;= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||</div><div class='del'>-	    !dc-&gt;cap_funcs.get_dcc_compression_cap)</div><div class='add'>+	if (adev-&gt;family &lt; AMDGPU_FAMILY_GC_12_0_0 &amp;&amp;</div><div class='add'>+	    format &gt;= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;cap_funcs.get_dcc_compression_cap)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	input.format = format;</div><div class='hunk'>@@ -308,18 +313,18 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg</div><div class='ctx'> 								     const enum surface_pixel_format format,</div><div class='ctx'> 								     const enum dc_rotation_angle rotation,</div><div class='ctx'> 								     const struct plane_size *plane_size,</div><div class='del'>-								     union dc_tiling_info *tiling_info,</div><div class='add'>+								     struct dc_tiling_info *tiling_info,</div><div class='ctx'> 								     struct dc_plane_dcc_param *dcc,</div><div class='del'>-								     struct dc_plane_address *address,</div><div class='del'>-								     const bool force_disable_dcc)</div><div class='add'>+								     struct dc_plane_address *address)</div><div class='ctx'> {</div><div class='ctx'> 	const uint64_t modifier = afb-&gt;base.modifier;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);</div><div class='ctx'> 	tiling_info-&gt;gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);</div><div class='add'>+	tiling_info-&gt;gfxversion = DcGfxVersion9;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_dm_plane_modifier_has_dcc(modifier) &amp;&amp; !force_disable_dcc) {</div><div class='add'>+	if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {</div><div class='ctx'> 		uint64_t dcc_address = afb-&gt;address + afb-&gt;base.offsets[1];</div><div class='ctx'> 		bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);</div><div class='ctx'> 		bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);</div><div class='hunk'>@@ -354,6 +359,46 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev,</div><div class='add'>+								      const struct amdgpu_framebuffer *afb,</div><div class='add'>+								      const enum surface_pixel_format format,</div><div class='add'>+								      const enum dc_rotation_angle rotation,</div><div class='add'>+								      const struct plane_size *plane_size,</div><div class='add'>+								      struct dc_tiling_info *tiling_info,</div><div class='add'>+								      struct dc_plane_dcc_param *dcc,</div><div class='add'>+								      struct dc_plane_address *address)</div><div class='add'>+{</div><div class='add'>+	const uint64_t modifier = afb-&gt;base.modifier;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* TODO: Most of this function shouldn't be needed on GFX12. */</div><div class='add'>+	amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);</div><div class='add'>+</div><div class='add'>+	tiling_info-&gt;gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);</div><div class='add'>+	tiling_info-&gt;gfxversion = DcGfxAddr3;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {</div><div class='add'>+		int max_compressed_block = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);</div><div class='add'>+</div><div class='add'>+		dcc-&gt;enable = 1;</div><div class='add'>+		dcc-&gt;independent_64b_blks = max_compressed_block == 0;</div><div class='add'>+</div><div class='add'>+		if (max_compressed_block == 0)</div><div class='add'>+			dcc-&gt;dcc_ind_blk = hubp_ind_block_64b;</div><div class='add'>+		else if (max_compressed_block == 1)</div><div class='add'>+			dcc-&gt;dcc_ind_blk = hubp_ind_block_128b;</div><div class='add'>+		else</div><div class='add'>+			dcc-&gt;dcc_ind_blk = hubp_ind_block_unconstrained;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* TODO: This seems wrong because there is no DCC plane on GFX12. */</div><div class='add'>+	ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev,</div><div class='ctx'> 						  uint64_t **mods,</div><div class='ctx'> 						  uint64_t *size,</div><div class='hunk'>@@ -647,6 +692,38 @@ static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev,</div><div class='ctx'> 				     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev,</div><div class='add'>+		      uint64_t **mods, uint64_t *size, uint64_t *capacity)</div><div class='add'>+{</div><div class='add'>+	uint64_t ver = AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12);</div><div class='add'>+	uint64_t mod_256k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256K_2D);</div><div class='add'>+	uint64_t mod_64k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_64K_2D);</div><div class='add'>+	uint64_t mod_4k = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_4K_2D);</div><div class='add'>+	uint64_t mod_256b = ver | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX12_256B_2D);</div><div class='add'>+	uint64_t dcc = ver | AMD_FMT_MOD_SET(DCC, 1);</div><div class='add'>+	uint8_t max_comp_block[] = {2, 1, 0};</div><div class='add'>+	uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0};</div><div class='add'>+	uint8_t i = 0, j = 0;</div><div class='add'>+	uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b, DRM_FORMAT_MOD_LINEAR};</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(max_comp_block); i++)</div><div class='add'>+		max_comp_block_mod[i] = AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block[i]);</div><div class='add'>+</div><div class='add'>+	/* With DCC: Best choice should be kept first. Hence, add all 256k modifiers of different</div><div class='add'>+	 * max compressed blocks first and then move on to the next smaller sized layouts.</div><div class='add'>+	 * Do not add the linear modifier here, and hence the condition of size-1 for the loop</div><div class='add'>+	 */</div><div class='add'>+	for (j = 0; j &lt; ARRAY_SIZE(gfx12_modifiers) - 1; j++)</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(max_comp_block); i++)</div><div class='add'>+			amdgpu_dm_plane_add_modifier(mods, size, capacity,</div><div class='add'>+						     ver | dcc | max_comp_block_mod[i] | gfx12_modifiers[j]);</div><div class='add'>+</div><div class='add'>+	/* Without DCC. Add all modifiers including linear at the end */</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(gfx12_modifiers); i++)</div><div class='add'>+		amdgpu_dm_plane_add_modifier(mods, size, capacity, gfx12_modifiers[i]);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t size = 0, capacity = 128;</div><div class='hunk'>@@ -656,7 +733,7 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig</div><div class='ctx'> 	if (adev-&gt;family &lt; AMDGPU_FAMILY_AI)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	*mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);</div><div class='add'>+	*mods = kmalloc_array(capacity, sizeof(uint64_t), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (plane_type == DRM_PLANE_TYPE_CURSOR) {</div><div class='ctx'> 		amdgpu_dm_plane_add_modifier(mods, &amp;size, &amp;capacity, DRM_FORMAT_MOD_LINEAR);</div><div class='hunk'>@@ -684,6 +761,9 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig</div><div class='ctx'> 	case AMDGPU_FAMILY_GC_11_5_0:</div><div class='ctx'> 		amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &amp;size, &amp;capacity);</div><div class='ctx'> 		break;</div><div class='add'>+	case AMDGPU_FAMILY_GC_12_0_0:</div><div class='add'>+		amdgpu_dm_plane_add_gfx12_modifiers(adev, mods, &amp;size, &amp;capacity);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_dm_plane_add_modifier(mods, &amp;size, &amp;capacity, DRM_FORMAT_MOD_LINEAR);</div><div class='hunk'>@@ -761,12 +841,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,</div><div class='ctx'> 			     const enum surface_pixel_format format,</div><div class='ctx'> 			     const enum dc_rotation_angle rotation,</div><div class='ctx'> 			     const uint64_t tiling_flags,</div><div class='del'>-			     union dc_tiling_info *tiling_info,</div><div class='add'>+			     struct dc_tiling_info *tiling_info,</div><div class='ctx'> 			     struct plane_size *plane_size,</div><div class='ctx'> 			     struct dc_plane_dcc_param *dcc,</div><div class='ctx'> 			     struct dc_plane_address *address,</div><div class='del'>-			     bool tmz_surface,</div><div class='del'>-			     bool force_disable_dcc)</div><div class='add'>+			     bool tmz_surface)</div><div class='ctx'> {</div><div class='ctx'> 	const struct drm_framebuffer *fb = &amp;afb-&gt;base;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -822,12 +901,18 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,</div><div class='ctx'> 			upper_32_bits(chroma_addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;family &gt;= AMDGPU_FAMILY_AI) {</div><div class='add'>+	if (adev-&gt;family &gt;= AMDGPU_FAMILY_GC_12_0_0) {</div><div class='add'>+		ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format,</div><div class='add'>+										 rotation, plane_size,</div><div class='add'>+										 tiling_info, dcc,</div><div class='add'>+										 address);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	} else if (adev-&gt;family &gt;= AMDGPU_FAMILY_AI) {</div><div class='ctx'> 		ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,</div><div class='ctx'> 										rotation, plane_size,</div><div class='ctx'> 										tiling_info, dcc,</div><div class='del'>-										address,</div><div class='del'>-										force_disable_dcc);</div><div class='add'>+										address);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -854,19 +939,23 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	afb = to_amdgpu_framebuffer(new_state-&gt;fb);</div><div class='del'>-	obj = new_state-&gt;fb-&gt;obj[0];</div><div class='add'>+	obj = drm_gem_fb_get_obj(new_state-&gt;fb, 0);</div><div class='add'>+	if (!obj) {</div><div class='add'>+		DRM_ERROR("Failed to get obj from framebuffer\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rbo = gem_to_amdgpu_bo(obj);</div><div class='ctx'> 	adev = amdgpu_ttm_adev(rbo-&gt;tbo.bdev);</div><div class='del'>-</div><div class='ctx'> 	r = amdgpu_bo_reserve(rbo, true);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "fail to reserve bo (%d)\n", r);</div><div class='add'>+		drm_err(adev_to_drm(adev), "fail to reserve bo (%d)\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = dma_resv_reserve_fences(rbo-&gt;tbo.base.resv, 1);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "reserving fence slot failed (%d)\n", r);</div><div class='add'>+		drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r);</div><div class='ctx'> 		goto error_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -875,6 +964,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,</div><div class='ctx'> 	else</div><div class='ctx'> 		domain = AMDGPU_GEM_DOMAIN_VRAM;</div><div class='ctx'> </div><div class='add'>+	rbo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 	r = amdgpu_bo_pin(rbo, domain);</div><div class='ctx'> 	if (unlikely(r != 0)) {</div><div class='ctx'> 		if (r != -ERESTARTSYS)</div><div class='hunk'>@@ -913,14 +1003,13 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,</div><div class='ctx'> 	    dm_plane_state_old-&gt;dc_state != dm_plane_state_new-&gt;dc_state) {</div><div class='ctx'> 		struct dc_plane_state *plane_state =</div><div class='ctx'> 			dm_plane_state_new-&gt;dc_state;</div><div class='del'>-		bool force_disable_dcc = !plane_state-&gt;dcc.enable;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_plane_fill_plane_buffer_attributes(</div><div class='ctx'> 			adev, afb, plane_state-&gt;format, plane_state-&gt;rotation,</div><div class='ctx'> 			afb-&gt;tiling_flags,</div><div class='ctx'> 			&amp;plane_state-&gt;tiling_info, &amp;plane_state-&gt;plane_size,</div><div class='ctx'> 			&amp;plane_state-&gt;dcc, &amp;plane_state-&gt;address,</div><div class='del'>-			afb-&gt;tmz_surface, force_disable_dcc);</div><div class='add'>+			afb-&gt;tmz_surface);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1173,19 +1262,34 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane,</div><div class='del'>-					      struct drm_atomic_state *state)</div><div class='add'>+					      struct drm_atomic_state *state, bool flip)</div><div class='ctx'> {</div><div class='del'>-	/* Only support async updates on cursor planes. */</div><div class='del'>-	if (plane-&gt;type != DRM_PLANE_TYPE_CURSOR)</div><div class='add'>+	struct drm_crtc_state *new_crtc_state;</div><div class='add'>+	struct drm_plane_state *new_plane_state;</div><div class='add'>+	struct dm_crtc_state *dm_new_crtc_state;</div><div class='add'>+</div><div class='add'>+	if (flip) {</div><div class='add'>+		if (plane-&gt;type != DRM_PLANE_TYPE_OVERLAY)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	} else if (plane-&gt;type != DRM_PLANE_TYPE_CURSOR) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	new_plane_state = drm_atomic_get_new_plane_state(state, plane);</div><div class='add'>+	new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state-&gt;crtc);</div><div class='add'>+	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+	/* Reject overlay cursors for now*/</div><div class='add'>+	if (!flip &amp;&amp; dm_new_crtc_state-&gt;cursor_mode == DM_CURSOR_OVERLAY_MODE)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,</div><div class='del'>-					       struct dc_cursor_position *position)</div><div class='add'>+int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,</div><div class='add'>+					struct dc_cursor_position *position)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(plane-&gt;dev);</div><div class='ctx'> 	int x, y;</div><div class='ctx'> 	int xorigin = 0, yorigin = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1217,12 +1321,14 @@ static int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct d</div><div class='ctx'> 		y = 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	position-&gt;enable = true;</div><div class='del'>-	position-&gt;translate_by_source = true;</div><div class='ctx'> 	position-&gt;x = x;</div><div class='ctx'> 	position-&gt;y = y;</div><div class='ctx'> 	position-&gt;x_hotspot = xorigin;</div><div class='ctx'> 	position-&gt;y_hotspot = yorigin;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &lt; IP_VERSION(4, 0, 1))</div><div class='add'>+		position-&gt;translate_by_source = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1254,7 +1360,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,</div><div class='ctx'> 		/* turn off cursor */</div><div class='ctx'> 		if (crtc_state &amp;&amp; crtc_state-&gt;stream) {</div><div class='ctx'> 			mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='del'>-			dc_stream_set_cursor_position(crtc_state-&gt;stream,</div><div class='add'>+			dc_stream_program_cursor_position(crtc_state-&gt;stream,</div><div class='ctx'> 						      &amp;position);</div><div class='ctx'> 			mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1280,15 +1386,16 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,</div><div class='ctx'> 	    adev-&gt;dm.dc-&gt;caps.color.dpp.gamma_corr)</div><div class='ctx'> 		attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1;</div><div class='ctx'> </div><div class='del'>-	attributes.pitch = afb-&gt;base.pitches[0] / afb-&gt;base.format-&gt;cpp[0];</div><div class='add'>+	if (afb)</div><div class='add'>+		attributes.pitch = afb-&gt;base.pitches[0] / afb-&gt;base.format-&gt;cpp[0];</div><div class='ctx'> </div><div class='ctx'> 	if (crtc_state-&gt;stream) {</div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;dm.dc_lock);</div><div class='del'>-		if (!dc_stream_set_cursor_attributes(crtc_state-&gt;stream,</div><div class='add'>+		if (!dc_stream_program_cursor_attributes(crtc_state-&gt;stream,</div><div class='ctx'> 							 &amp;attributes))</div><div class='ctx'> 			DRM_ERROR("DC failed to set cursor attributes\n");</div><div class='ctx'> </div><div class='del'>-		if (!dc_stream_set_cursor_position(crtc_state-&gt;stream,</div><div class='add'>+		if (!dc_stream_program_cursor_position(crtc_state-&gt;stream,</div><div class='ctx'> 						   &amp;position))</div><div class='ctx'> 			DRM_ERROR("DC failed to set cursor position\n");</div><div class='ctx'> 		mutex_unlock(&amp;adev-&gt;dm.dc_lock);</div><div class='hunk'>@@ -1319,6 +1426,20 @@ static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane,</div><div class='ctx'> 	amdgpu_dm_plane_handle_cursor_update(plane, old_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane)</div><div class='add'>+{</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane-&gt;state);</div><div class='add'>+	struct drm_framebuffer *fb = plane-&gt;state-&gt;fb;</div><div class='add'>+	struct dc_plane_state *dc_plane_state;</div><div class='add'>+</div><div class='add'>+	if (!dm_plane_state || !dm_plane_state-&gt;dc_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dc_plane_state = dm_plane_state-&gt;dc_state;</div><div class='add'>+</div><div class='add'>+	dc_plane_force_dcc_and_tiling_disable(dc_plane_state, fb-&gt;modifier ? true : false);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {</div><div class='ctx'> 	.prepare_fb = amdgpu_dm_plane_helper_prepare_fb,</div><div class='ctx'> 	.cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb,</div><div class='hunk'>@@ -1327,6 +1448,16 @@ static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {</div><div class='ctx'> 	.atomic_async_update = amdgpu_dm_plane_atomic_async_update</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = {</div><div class='add'>+	.prepare_fb = amdgpu_dm_plane_helper_prepare_fb,</div><div class='add'>+	.cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb,</div><div class='add'>+	.atomic_check = amdgpu_dm_plane_atomic_check,</div><div class='add'>+	.atomic_async_check = amdgpu_dm_plane_atomic_async_check,</div><div class='add'>+	.atomic_async_update = amdgpu_dm_plane_atomic_async_update,</div><div class='add'>+	.get_scanout_buffer = amdgpu_display_get_scanout_buffer,</div><div class='add'>+	.panic_flush = amdgpu_dm_plane_panic_flush,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane)</div><div class='ctx'> {</div><div class='ctx'> 	struct dm_plane_state *amdgpu_state = NULL;</div><div class='hunk'>@@ -1395,8 +1526,6 @@ static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,</div><div class='ctx'> 	const struct drm_format_info *info = drm_format_info(format);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) &amp; 3;</div><div class='del'>-</div><div class='ctx'> 	if (!info)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='hunk'>@@ -1418,29 +1547,34 @@ static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,</div><div class='ctx'> 	if (i == plane-&gt;modifier_count)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * For D swizzle the canonical modifier depends on the bpp, so check</div><div class='del'>-	 * it here.</div><div class='del'>-	 */</div><div class='del'>-	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &amp;&amp;</div><div class='del'>-	    adev-&gt;family &gt;= AMDGPU_FAMILY_NV) {</div><div class='del'>-		if (microtile == MICRO_SWIZZLE_D &amp;&amp; info-&gt;cpp[0] == 4)</div><div class='del'>-			return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;family &gt;= AMDGPU_FAMILY_RV &amp;&amp; microtile == MICRO_SWIZZLE_D &amp;&amp;</div><div class='del'>-	    info-&gt;cpp[0] &lt; 8)</div><div class='del'>-		return false;</div><div class='add'>+	/* GFX12 doesn't have these limitations. */</div><div class='add'>+	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) &lt;= AMD_FMT_MOD_TILE_VER_GFX11) {</div><div class='add'>+		enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) &amp; 3;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {</div><div class='del'>-		/* Per radeonsi comments 16/64 bpp are more complicated. */</div><div class='del'>-		if (info-&gt;cpp[0] != 4)</div><div class='del'>-			return false;</div><div class='del'>-		/* We support multi-planar formats, but not when combined with</div><div class='del'>-		 * additional DCC metadata planes.</div><div class='add'>+		/*</div><div class='add'>+		 * For D swizzle the canonical modifier depends on the bpp, so check</div><div class='add'>+		 * it here.</div><div class='ctx'> 		 */</div><div class='del'>-		if (info-&gt;num_planes &gt; 1)</div><div class='add'>+		if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &amp;&amp;</div><div class='add'>+		    adev-&gt;family &gt;= AMDGPU_FAMILY_NV) {</div><div class='add'>+			if (microtile == MICRO_SWIZZLE_D &amp;&amp; info-&gt;cpp[0] == 4)</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (adev-&gt;family &gt;= AMDGPU_FAMILY_RV &amp;&amp; microtile == MICRO_SWIZZLE_D &amp;&amp;</div><div class='add'>+		    info-&gt;cpp[0] &lt; 8)</div><div class='ctx'> 			return false;</div><div class='add'>+</div><div class='add'>+		if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {</div><div class='add'>+			/* Per radeonsi comments 16/64 bpp are more complicated. */</div><div class='add'>+			if (info-&gt;cpp[0] != 4)</div><div class='add'>+				return false;</div><div class='add'>+			/* We support multi-planar formats, but not when combined with</div><div class='add'>+			 * additional DCC metadata planes.</div><div class='add'>+			 */</div><div class='add'>+			if (info-&gt;num_planes &gt; 1)</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -1500,7 +1634,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='ctx'> 					   dm-&gt;adev-&gt;mode_info.plane_ctm_property, 0);</div><div class='ctx'> </div><div class='del'>-	if (dpp_color_caps.hw_3d_lut) {</div><div class='add'>+	if (dpp_color_caps.hw_3d_lut || dm-&gt;dc-&gt;caps.color.mpc.preblend) {</div><div class='ctx'> 		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='ctx'> 					   mode_info.plane_shaper_lut_property, 0);</div><div class='ctx'> 		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='hunk'>@@ -1649,6 +1783,39 @@ dm_atomic_plane_get_property(struct drm_plane *plane,</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+#else</div><div class='add'>+</div><div class='add'>+#define MAX_COLOR_PIPELINES 5</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+dm_plane_init_colorops(struct drm_plane *plane)</div><div class='add'>+{</div><div class='add'>+	struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES];</div><div class='add'>+	struct drm_device *dev = plane-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct dc *dc = adev-&gt;dm.dc;</div><div class='add'>+	int len = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* initialize pipeline */</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_3_0) {</div><div class='add'>+		ret = amdgpu_dm_initialize_default_pipeline(plane, &amp;pipelines[len]);</div><div class='add'>+		if (ret) {</div><div class='add'>+			drm_err(plane-&gt;dev, "Failed to create color pipeline for plane %d: %d\n",</div><div class='add'>+				plane-&gt;base.id, ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+		len++;</div><div class='add'>+</div><div class='add'>+		/* Create COLOR_PIPELINE property and attach */</div><div class='add'>+		drm_plane_create_color_pipeline_property(plane, pipelines, len);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> static const struct drm_plane_funcs dm_plane_funcs = {</div><div class='hunk'>@@ -1675,6 +1842,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	int res = -EPERM;</div><div class='ctx'> 	unsigned int supported_rotations;</div><div class='ctx'> 	uint64_t *modifiers = NULL;</div><div class='add'>+	unsigned int primary_zpos = dm-&gt;dc-&gt;caps.max_slave_planes;</div><div class='ctx'> </div><div class='ctx'> 	num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,</div><div class='ctx'> 							ARRAY_SIZE(formats));</div><div class='hunk'>@@ -1704,10 +1872,19 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (plane-&gt;type == DRM_PLANE_TYPE_PRIMARY) {</div><div class='del'>-		drm_plane_create_zpos_immutable_property(plane, 0);</div><div class='add'>+		/*</div><div class='add'>+		 * Allow OVERLAY planes to be used as underlays by assigning an</div><div class='add'>+		 * immutable zpos = # of OVERLAY planes to the PRIMARY plane.</div><div class='add'>+		 */</div><div class='add'>+		drm_plane_create_zpos_immutable_property(plane, primary_zpos);</div><div class='ctx'> 	} else if (plane-&gt;type == DRM_PLANE_TYPE_OVERLAY) {</div><div class='del'>-		unsigned int zpos = 1 + drm_plane_index(plane);</div><div class='del'>-		drm_plane_create_zpos_property(plane, zpos, 1, 254);</div><div class='add'>+		/*</div><div class='add'>+		 * OVERLAY planes can be below or above the PRIMARY, but cannot</div><div class='add'>+		 * be above the CURSOR plane.</div><div class='add'>+		 */</div><div class='add'>+		unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane);</div><div class='add'>+</div><div class='add'>+		drm_plane_create_zpos_property(plane, zpos, 0, 254);</div><div class='ctx'> 	} else if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR) {</div><div class='ctx'> 		drm_plane_create_zpos_immutable_property(plane, 255);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1740,11 +1917,19 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	    plane-&gt;type != DRM_PLANE_TYPE_CURSOR)</div><div class='ctx'> 		drm_plane_enable_fb_damage_clips(plane);</div><div class='ctx'> </div><div class='del'>-	drm_plane_helper_add(plane, &amp;dm_plane_helper_funcs);</div><div class='add'>+	if (plane-&gt;type == DRM_PLANE_TYPE_PRIMARY)</div><div class='add'>+		drm_plane_helper_add(plane, &amp;dm_primary_plane_helper_funcs);</div><div class='add'>+	else</div><div class='add'>+		drm_plane_helper_add(plane, &amp;dm_plane_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> #ifdef AMD_PRIVATE_COLOR</div><div class='ctx'> 	dm_atomic_plane_attach_color_mgmt_properties(dm, plane);</div><div class='add'>+#else</div><div class='add'>+	res = dm_plane_init_colorops(plane);</div><div class='add'>+	if (res)</div><div class='add'>+		return res;</div><div class='ctx'> #endif</div><div class='add'>+</div><div class='ctx'> 	/* Create (reset) the plane state */</div><div class='ctx'> 	if (plane-&gt;funcs-&gt;reset)</div><div class='ctx'> 		plane-&gt;funcs-&gt;reset(plane);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h<br/>index b51a6b57bd9b..ea2619b507db 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h</a></div><div class='hunk'>@@ -29,6 +29,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='add'>+int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,</div><div class='add'>+					struct dc_cursor_position *position);</div><div class='add'>+</div><div class='ctx'> void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,</div><div class='ctx'> 			  struct drm_plane_state *old_plane_state);</div><div class='ctx'> </div><div class='hunk'>@@ -44,19 +47,18 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,</div><div class='ctx'> 				 const enum surface_pixel_format format,</div><div class='ctx'> 				 const enum dc_rotation_angle rotation,</div><div class='ctx'> 				 const uint64_t tiling_flags,</div><div class='del'>-				 union dc_tiling_info *tiling_info,</div><div class='add'>+				 struct dc_tiling_info *tiling_info,</div><div class='ctx'> 				 struct plane_size *plane_size,</div><div class='ctx'> 				 struct dc_plane_dcc_param *dcc,</div><div class='ctx'> 				 struct dc_plane_address *address,</div><div class='del'>-				 bool tmz_surface,</div><div class='del'>-				 bool force_disable_dcc);</div><div class='add'>+				 bool tmz_surface);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 			 struct drm_plane *plane,</div><div class='ctx'> 			 unsigned long possible_crtcs,</div><div class='ctx'> 			 const struct dc_plane_cap *plane_cap);</div><div class='ctx'> </div><div class='del'>-const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd);</div><div class='add'>+const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,</div><div class='ctx'> 				    bool *per_pixel_alpha, bool *pre_multiplied_alpha,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c<br/>index 848c5b4bb301..11b2ea6edf95 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -97,6 +98,7 @@ bool dm_pp_apply_display_requirements(</div><div class='ctx'> 			const struct dm_pp_single_disp_config *dc_cfg =</div><div class='ctx'> 						&amp;pp_display_cfg-&gt;disp_configs[i];</div><div class='ctx'> 			adev-&gt;pm.pm_display_cfg.displays[i].controller_id = dc_cfg-&gt;pipe_idx + 1;</div><div class='add'>+			adev-&gt;pm.pm_display_cfg.displays[i].pixel_clock = dc_cfg-&gt;pixel_clock;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dpm_display_configuration_change(adev, &amp;adev-&gt;pm.pm_display_cfg);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c<br/>index 1f08c6564c3b..fd491b7a3cd7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -26,7 +27,6 @@</div><div class='ctx'> #include "amdgpu_dm_psr.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "dc.h"</div><div class='del'>-#include "dm_helpers.h"</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='ctx'> #include "modules/power/power_helpers.h"</div><div class='ctx'> </div><div class='hunk'>@@ -54,7 +54,8 @@ static bool link_supports_psrsu(struct dc_link *link)</div><div class='ctx'> 	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_PSR_SU)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	return dc_dmub_check_min_version(dc-&gt;ctx-&gt;dmub_srv-&gt;dmub);</div><div class='add'>+	/* Temporarily disable PSR-SU to avoid glitches */</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -86,14 +87,6 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 		link-&gt;psr_settings.psr_feature_enabled = true;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",</div><div class='del'>-		link-&gt;psr_settings.psr_feature_enabled,</div><div class='del'>-		link-&gt;psr_settings.psr_version,</div><div class='del'>-		link-&gt;dpcd_caps.psr_info.psr_version,</div><div class='del'>-		link-&gt;dpcd_caps.psr_info.psr_dpcd_caps.raw,</div><div class='del'>-		link-&gt;dpcd_caps.psr_info.psr2_su_y_granularity_cap);</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -126,8 +119,10 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)</div><div class='ctx'> 		psr_config.allow_multi_disp_optimizations =</div><div class='ctx'> 			(amdgpu_dc_feature_mask &amp; DC_PSR_ALLOW_MULTI_DISP_OPT);</div><div class='ctx'> </div><div class='del'>-		if (!psr_su_set_dsc_slice_height(dc, link, stream, &amp;psr_config))</div><div class='del'>-			return false;</div><div class='add'>+		if (link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1) {</div><div class='add'>+			if (!psr_su_set_dsc_slice_height(dc, link, stream, &amp;psr_config))</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		ret = dc_link_setup_psr(link, stream, &amp;psr_config, &amp;psr_context);</div><div class='ctx'> </div><div class='hunk'>@@ -141,9 +136,8 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)</div><div class='ctx'>  * amdgpu_dm_psr_enable() - enable psr f/w</div><div class='ctx'>  * @stream: stream state</div><div class='ctx'>  *</div><div class='del'>- * Return: true if success</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)</div><div class='add'>+void amdgpu_dm_psr_enable(struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='ctx'> 	unsigned int vsync_rate_hz = 0;</div><div class='hunk'>@@ -159,7 +153,7 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)</div><div class='ctx'> 	DRM_DEBUG_DRIVER("Enabling psr...\n");</div><div class='ctx'> </div><div class='ctx'> 	vsync_rate_hz = div64_u64(div64_u64((</div><div class='del'>-			stream-&gt;timing.pix_clk_100hz * 100),</div><div class='add'>+			stream-&gt;timing.pix_clk_100hz * (uint64_t)100),</div><div class='ctx'> 			stream-&gt;timing.v_total),</div><div class='ctx'> 			stream-&gt;timing.h_total);</div><div class='ctx'> </div><div class='hunk'>@@ -190,7 +184,10 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)</div><div class='ctx'> 	if (link-&gt;psr_settings.psr_version &lt; DC_PSR_VERSION_SU_1)</div><div class='ctx'> 		power_opt |= psr_power_opt_z10_static_screen;</div><div class='ctx'> </div><div class='del'>-	return dc_link_set_psr_allow_active(link, &amp;psr_enable, false, false, &amp;power_opt);</div><div class='add'>+	dc_link_set_psr_allow_active(link, &amp;psr_enable, false, false, &amp;power_opt);</div><div class='add'>+</div><div class='add'>+	if (link-&gt;ctx-&gt;dc-&gt;caps.ips_support)</div><div class='add'>+		dc_allow_idle_optimizations(link-&gt;ctx-&gt;dc, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -199,18 +196,17 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)</div><div class='ctx'>  *</div><div class='ctx'>  * Return: true if success</div><div class='ctx'>  */</div><div class='del'>-bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)</div><div class='add'>+bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait)</div><div class='ctx'> {</div><div class='del'>-	unsigned int power_opt = 0;</div><div class='ctx'> 	bool psr_enable = false;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG_DRIVER("Disabling psr...\n");</div><div class='ctx'> </div><div class='del'>-	return dc_link_set_psr_allow_active(stream-&gt;link, &amp;psr_enable, true, false, &amp;power_opt);</div><div class='add'>+	return dc_link_set_psr_allow_active(stream-&gt;link, &amp;psr_enable, wait, false, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * amdgpu_dm_psr_disable() - disable psr f/w</div><div class='add'>+ * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams</div><div class='ctx'>  * if psr is enabled on any stream</div><div class='ctx'>  *</div><div class='ctx'>  * Return: true if success</div><div class='hunk'>@@ -221,3 +217,61 @@ bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)</div><div class='ctx'> 	return dc_set_psr_allow_active(dm-&gt;dc, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * amdgpu_dm_psr_is_active_allowed() - check if psr is allowed on any stream</div><div class='add'>+ * @dm:  pointer to amdgpu_display_manager</div><div class='add'>+ *</div><div class='add'>+ * Return: true if allowed</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool allow_active = false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dm-&gt;dc-&gt;current_state-&gt;stream_count ; i++) {</div><div class='add'>+		struct dc_link *link;</div><div class='add'>+		struct dc_stream_state *stream = dm-&gt;dc-&gt;current_state-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+		link = stream-&gt;link;</div><div class='add'>+		if (!link)</div><div class='add'>+			continue;</div><div class='add'>+		if (link-&gt;psr_settings.psr_feature_enabled &amp;&amp;</div><div class='add'>+		    link-&gt;psr_settings.psr_allow_active) {</div><div class='add'>+			allow_active = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return allow_active;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR</div><div class='add'>+ * @stream: stream state attached to the eDP link</div><div class='add'>+ *</div><div class='add'>+ * Waits for a max of 500ms for the eDP panel to exit PSR.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if panel exited PSR, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	enum dc_psr_state psr_state = PSR_STATE0;</div><div class='add'>+	struct dc_link *link = stream-&gt;link;</div><div class='add'>+	int retry_count;</div><div class='add'>+</div><div class='add'>+	if (link == NULL)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (retry_count = 0; retry_count &lt;= 1000; retry_count++) {</div><div class='add'>+		dc_link_get_psr_state(link, &amp;psr_state);</div><div class='add'>+		if (psr_state == PSR_STATE0)</div><div class='add'>+			break;</div><div class='add'>+		udelay(500);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (retry_count == 1000)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h<br/>index 6806b3c9c84b..4fb8626913cf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -32,9 +33,11 @@</div><div class='ctx'> #define AMDGPU_DM_PSR_ENTRY_DELAY 5</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_set_psr_caps(struct dc_link *link);</div><div class='del'>-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);</div><div class='add'>+void amdgpu_dm_psr_enable(struct dc_stream_state *stream);</div><div class='ctx'> bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);</div><div class='del'>-bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);</div><div class='add'>+bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait);</div><div class='ctx'> bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);</div><div class='add'>+bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm);</div><div class='add'>+bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> #endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c<br/>new file mode 100644<br/>index 000000000000..1da07ebf9217<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_quirks.c</a></div><div class='hunk'>@@ -0,0 +1,178 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dmi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_dm.h"</div><div class='add'>+</div><div class='add'>+struct amdgpu_dm_quirks {</div><div class='add'>+	bool aux_hpd_discon;</div><div class='add'>+	bool support_edp0_on_dp1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct amdgpu_dm_quirks quirk_entries = {</div><div class='add'>+	.aux_hpd_discon = false,</div><div class='add'>+	.support_edp0_on_dp1 = false</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int edp0_on_dp1_callback(const struct dmi_system_id *id)</div><div class='add'>+{</div><div class='add'>+	quirk_entries.support_edp0_on_dp1 = true;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aux_hpd_discon_callback(const struct dmi_system_id *id)</div><div class='add'>+{</div><div class='add'>+	quirk_entries.aux_hpd_discon = true;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dmi_system_id dmi_quirk_table[] = {</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = aux_hpd_discon_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = edp0_on_dp1_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite mt645 G8 Mobile Thin Client"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = edp0_on_dp1_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 645 14 inch G11 Notebook PC"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = edp0_on_dp1_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 665 16 inch G11 Notebook PC"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = edp0_on_dp1_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook 445 14 inch G11 Notebook PC"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.callback = edp0_on_dp1_callback,</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "HP"),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook 465 16 inch G11 Notebook PC"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{}</div><div class='add'>+	/* TODO: refactor this from a fixed table to a dynamic option */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void retrieve_dmi_info(struct amdgpu_display_manager *dm)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = dm-&gt;ddev;</div><div class='add'>+	int dmi_id;</div><div class='add'>+</div><div class='add'>+	dm-&gt;aux_hpd_discon_quirk = false;</div><div class='add'>+	dm-&gt;edp0_on_dp1_quirk = false;</div><div class='add'>+</div><div class='add'>+	dmi_id = dmi_check_system(dmi_quirk_table);</div><div class='add'>+</div><div class='add'>+	if (!dmi_id)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (quirk_entries.aux_hpd_discon) {</div><div class='add'>+		dm-&gt;aux_hpd_discon_quirk = true;</div><div class='add'>+		drm_info(dev, "aux_hpd_discon_quirk attached\n");</div><div class='add'>+	}</div><div class='add'>+	if (quirk_entries.support_edp0_on_dp1) {</div><div class='add'>+		dm-&gt;edp0_on_dp1_quirk = true;</div><div class='add'>+		drm_info(dev, "support_edp0_on_dp1 attached\n");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c<br/>index 738a58eebba7..da94e3544b65 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -24,20 +25,21 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu_dm_replay.h"</div><div class='add'>+#include "dc_dmub_srv.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='ctx'> #include "modules/power/power_helpers.h"</div><div class='ctx'> #include "dmub/inc/dmub_cmd.h"</div><div class='del'>-#include "dc/inc/link.h"</div><div class='add'>+#include "dc/inc/link_service.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * link_supports_replay() - check if the link supports replay</div><div class='add'>+ * amdgpu_dm_link_supports_replay() - check if the link supports replay</div><div class='ctx'>  * @link: link</div><div class='ctx'>  * @aconnector: aconnector</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-static bool link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)</div><div class='add'>+bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)</div><div class='ctx'> {</div><div class='ctx'> 	struct dm_connector_state *state = to_dm_connector_state(aconnector-&gt;base.state);</div><div class='ctx'> 	struct dpcd_caps *dpcd_caps = &amp;link-&gt;dpcd_caps;</div><div class='hunk'>@@ -78,6 +80,7 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector</div><div class='ctx'> {</div><div class='ctx'> 	struct replay_config pr_config = { 0 };</div><div class='ctx'> 	union replay_debug_flags *debug_flags = NULL;</div><div class='add'>+	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	// If Replay is already set to support, return true to skip checks</div><div class='ctx'> 	if (link-&gt;replay_settings.config.replay_supported)</div><div class='hunk'>@@ -89,7 +92,11 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector</div><div class='ctx'> 	if (link-&gt;panel_config.psr.disallow_replay)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (!link_supports_replay(link, aconnector))</div><div class='add'>+	if (!amdgpu_dm_link_supports_replay(link, aconnector))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;ctx-&gt;dmub_srv || !dc-&gt;ctx-&gt;dmub_srv-&gt;dmub ||</div><div class='add'>+		!dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.replay_supported)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	// Mark Replay is supported in pr_config</div><div class='hunk'>@@ -155,7 +162,7 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait)</div><div class='ctx'> </div><div class='ctx'> 	if (link) {</div><div class='ctx'> 		link-&gt;dc-&gt;link_srv-&gt;edp_setup_replay(link, stream);</div><div class='del'>-		link-&gt;dc-&gt;link_srv-&gt;edp_set_coasting_vtotal(link, stream-&gt;timing.v_total);</div><div class='add'>+		link-&gt;dc-&gt;link_srv-&gt;edp_set_coasting_vtotal(link, stream-&gt;timing.v_total, 0);</div><div class='ctx'> 		DRM_DEBUG_DRIVER("Enabling replay...\n");</div><div class='ctx'> 		link-&gt;dc-&gt;link_srv-&gt;edp_set_replay_allow_active(link, &amp;replay_active, wait, false, NULL);</div><div class='ctx'> 		return true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h<br/>index f0d30eb47312..73b6c67ae5e7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -38,7 +39,7 @@ enum replay_enable_option {</div><div class='ctx'> 	pr_enable_option_full_screen_video_coasting = 0x40000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-</div><div class='add'>+bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);</div><div class='ctx'> bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable);</div><div class='ctx'> bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector);</div><div class='ctx'> bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c<br/>index d9e33c6bccd9..8550d5e8b753 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+//SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2015 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -52,4 +53,12 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc</div><div class='ctx'> 				    func_name, line);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dm_trace_smu_enter(uint32_t msg_id, uint32_t param_in, unsigned int delay, struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**** power component interfaces ****/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h<br/>index 133af994a08c..aa56fd6d56c3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='add'>+//SPDX-License-Identifier: MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2018 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='hunk'>@@ -87,7 +88,7 @@ TRACE_EVENT(amdgpu_dc_performance,</div><div class='ctx'> 			__entry-&gt;writes = write_count;</div><div class='ctx'> 			__entry-&gt;read_delta = read_count - *last_read;</div><div class='ctx'> 			__entry-&gt;write_delta = write_count - *last_write;</div><div class='del'>-			__assign_str(func, func);</div><div class='add'>+			__assign_str(func);</div><div class='ctx'> 			__entry-&gt;line = line;</div><div class='ctx'> 			*last_read = read_count;</div><div class='ctx'> 			*last_write = write_count;</div><div class='hunk'>@@ -726,6 +727,32 @@ TRACE_EVENT(dcn_optc_lock_unlock_state,</div><div class='ctx'> 	    )</div><div class='ctx'> );</div><div class='ctx'> </div><div class='add'>+TRACE_EVENT(amdgpu_dm_brightness,</div><div class='add'>+	TP_PROTO(void *function, u32 user_brightness, u32 converted_brightness, bool aux, bool ac),</div><div class='add'>+	TP_ARGS(function, user_brightness, converted_brightness, aux, ac),</div><div class='add'>+	TP_STRUCT__entry(</div><div class='add'>+		__field(void *, function)</div><div class='add'>+		__field(u32, user_brightness)</div><div class='add'>+		__field(u32, converted_brightness)</div><div class='add'>+		__field(bool, aux)</div><div class='add'>+		__field(bool, ac)</div><div class='add'>+	),</div><div class='add'>+	TP_fast_assign(</div><div class='add'>+		__entry-&gt;function = function;</div><div class='add'>+		__entry-&gt;user_brightness = user_brightness;</div><div class='add'>+		__entry-&gt;converted_brightness = converted_brightness;</div><div class='add'>+		__entry-&gt;aux = aux;</div><div class='add'>+		__entry-&gt;ac = ac;</div><div class='add'>+	),</div><div class='add'>+	TP_printk("%ps: brightness requested=%u converted=%u aux=%s power=%s",</div><div class='add'>+		  (void *)__entry-&gt;function,</div><div class='add'>+		  (u32)__entry-&gt;user_brightness,</div><div class='add'>+		  (u32)__entry-&gt;converted_brightness,</div><div class='add'>+		  (__entry-&gt;aux) ? "true" : "false",</div><div class='add'>+		  (__entry-&gt;ac) ? "AC" : "DC"</div><div class='add'>+	)</div><div class='add'>+);</div><div class='add'>+</div><div class='ctx'> #endif /* _AMDGPU_DM_TRACE_H_ */</div><div class='ctx'> </div><div class='ctx'> #undef TRACE_INCLUDE_PATH</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c<br/>index 16e72d623630..d9527c05fc87 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c</a></div><div class='hunk'>@@ -76,10 +76,8 @@ static int amdgpu_dm_wb_encoder_atomic_check(struct drm_encoder *encoder,</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='del'>-</div><div class='del'>-	return drm_add_modes_noedid(connector, dev-&gt;mode_config.max_width,</div><div class='del'>-				    dev-&gt;mode_config.max_height);</div><div class='add'>+	/* Maximum resolution supported by DWB */</div><div class='add'>+	return drm_add_modes_noedid(connector, 3840, 2160);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector,</div><div class='hunk'>@@ -104,18 +102,19 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_bo_reserve(rbo, true);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "fail to reserve bo (%d)\n", r);</div><div class='add'>+		drm_err(adev_to_drm(adev), "fail to reserve bo (%d)\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	r = dma_resv_reserve_fences(rbo-&gt;tbo.base.resv, 1);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dev_err(adev-&gt;dev, "reserving fence slot failed (%d)\n", r);</div><div class='add'>+		drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r);</div><div class='ctx'> 		goto error_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	domain = amdgpu_display_supported_domains(adev, rbo-&gt;flags);</div><div class='ctx'> </div><div class='add'>+	rbo-&gt;flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;</div><div class='ctx'> 	r = amdgpu_bo_pin(rbo, domain);</div><div class='ctx'> 	if (unlikely(r != 0)) {</div><div class='ctx'> 		if (r != -ERESTARTSYS)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c<br/>index 4ae4720535a5..e46f8ce41d87 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c</a></div><div class='hunk'>@@ -26,16 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "dc_trace.h"</div><div class='ctx'> </div><div class='del'>-#if defined(CONFIG_X86)</div><div class='del'>-#include &lt;asm/fpu/api.h&gt;</div><div class='del'>-#elif defined(CONFIG_PPC64)</div><div class='del'>-#include &lt;asm/switch_to.h&gt;</div><div class='del'>-#include &lt;asm/cputable.h&gt;</div><div class='del'>-#elif defined(CONFIG_ARM64)</div><div class='del'>-#include &lt;asm/neon.h&gt;</div><div class='del'>-#elif defined(CONFIG_LOONGARCH)</div><div class='del'>-#include &lt;asm/fpu.h&gt;</div><div class='del'>-#endif</div><div class='add'>+#include &lt;linux/fpu.h&gt;</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * DOC: DC FPU manipulation overview</div><div class='hunk'>@@ -87,20 +78,9 @@ void dc_fpu_begin(const char *function_name, const int line)</div><div class='ctx'> 	WARN_ON_ONCE(!in_task());</div><div class='ctx'> 	preempt_disable();</div><div class='ctx'> 	depth = __this_cpu_inc_return(fpu_recursion_depth);</div><div class='del'>-</div><div class='ctx'> 	if (depth == 1) {</div><div class='del'>-#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH)</div><div class='add'>+		BUG_ON(!kernel_fpu_available());</div><div class='ctx'> 		kernel_fpu_begin();</div><div class='del'>-#elif defined(CONFIG_PPC64)</div><div class='del'>-		if (cpu_has_feature(CPU_FTR_VSX_COMP))</div><div class='del'>-			enable_kernel_vsx();</div><div class='del'>-		else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP))</div><div class='del'>-			enable_kernel_altivec();</div><div class='del'>-		else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE))</div><div class='del'>-			enable_kernel_fp();</div><div class='del'>-#elif defined(CONFIG_ARM64)</div><div class='del'>-		kernel_neon_begin();</div><div class='del'>-#endif</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	TRACE_DCN_FPU(true, function_name, line, depth);</div><div class='hunk'>@@ -122,18 +102,7 @@ void dc_fpu_end(const char *function_name, const int line)</div><div class='ctx'> </div><div class='ctx'> 	depth = __this_cpu_dec_return(fpu_recursion_depth);</div><div class='ctx'> 	if (depth == 0) {</div><div class='del'>-#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH)</div><div class='ctx'> 		kernel_fpu_end();</div><div class='del'>-#elif defined(CONFIG_PPC64)</div><div class='del'>-		if (cpu_has_feature(CPU_FTR_VSX_COMP))</div><div class='del'>-			disable_kernel_vsx();</div><div class='del'>-		else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP))</div><div class='del'>-			disable_kernel_altivec();</div><div class='del'>-		else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE))</div><div class='del'>-			disable_kernel_fp();</div><div class='del'>-#elif defined(CONFIG_ARM64)</div><div class='del'>-		kernel_neon_end();</div><div class='del'>-#endif</div><div class='ctx'> 	} else {</div><div class='ctx'> 		WARN_ON_ONCE(depth &lt; 0);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile<br/>index 7991ae468f75..7277ed21552f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/Makefile</a></div><div class='hunk'>@@ -22,7 +22,7 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for Display Core (dc) component.</div><div class='ctx'> </div><div class='del'>-DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc</div><div class='add'>+DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> </div><div class='hunk'>@@ -35,12 +35,9 @@ DC_LIBS += dcn201</div><div class='ctx'> DC_LIBS += dcn30</div><div class='ctx'> DC_LIBS += dcn301</div><div class='ctx'> DC_LIBS += dcn31</div><div class='del'>-DC_LIBS += dcn314</div><div class='del'>-DC_LIBS += dcn32</div><div class='del'>-DC_LIBS += dcn321</div><div class='del'>-DC_LIBS += dcn35</div><div class='ctx'> DC_LIBS += dml</div><div class='del'>-DC_LIBS += dml2</div><div class='add'>+DC_LIBS += dml2_0</div><div class='add'>+DC_LIBS += soc_and_ip_translator</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='ctx'> DC_LIBS += dce120</div><div class='hunk'>@@ -55,25 +52,32 @@ endif</div><div class='ctx'> </div><div class='ctx'> DC_LIBS += hdcp</div><div class='ctx'> </div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+DC_LIBS += sspl</div><div class='add'>+AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, dc_spl_translate.o)</div><div class='add'>+endif</div><div class='add'>+</div><div class='ctx'> AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))</div><div class='ctx'> </div><div class='ctx'> include $(AMD_DC)</div><div class='ctx'> </div><div class='del'>-DISPLAY_CORE = dc.o dc_stat.o dc_resource.o dc_hw_sequencer.o dc_sink.o \</div><div class='del'>-dc_surface.o dc_debug.o dc_stream.o dc_link_enc_cfg.o dc_link_exports.o dc_state.o</div><div class='del'>-</div><div class='del'>-DISPLAY_CORE += dc_vm_helper.o</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))</div><div class='del'>-</div><div class='del'>-AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)</div><div class='del'>-</div><div class='del'>-DC_DMUB += dc_dmub_srv.o</div><div class='del'>-DC_EDID += dc_edid_parser.o</div><div class='del'>-AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))</div><div class='del'>-AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID))</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB) $(AMD_DISPLAY_EDID)</div><div class='add'>+FILES =</div><div class='add'>+FILES += dc_dmub_srv.o</div><div class='add'>+FILES += dc_edid_parser.o</div><div class='add'>+FILES += dc_fused_io.o</div><div class='add'>+FILES += dc_helper.o</div><div class='add'>+FILES += core/dc.o</div><div class='add'>+FILES += core/dc_debug.o</div><div class='add'>+FILES += core/dc_hw_sequencer.o</div><div class='add'>+FILES += core/dc_link_enc_cfg.o</div><div class='add'>+FILES += core/dc_link_exports.o</div><div class='add'>+FILES += core/dc_resource.o</div><div class='add'>+FILES += core/dc_sink.o</div><div class='add'>+FILES += core/dc_stat.o</div><div class='add'>+FILES += core/dc_state.o</div><div class='add'>+FILES += core/dc_stream.o</div><div class='add'>+FILES += core/dc_surface.o</div><div class='add'>+FILES += core/dc_vm_helper.o</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/, $(FILES))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c<br/>index b2fc4f8e6482..a51c2701da24 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/dc_common.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/dc_common.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/dc_common.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/basics/dc_common.c</a></div><div class='hunk'>@@ -40,7 +40,8 @@ bool is_rgb_cspace(enum dc_color_space output_color_space)</div><div class='ctx'> 	case COLOR_SPACE_YCBCR709:</div><div class='ctx'> 	case COLOR_SPACE_YCBCR601_LIMITED:</div><div class='ctx'> 	case COLOR_SPACE_YCBCR709_LIMITED:</div><div class='del'>-	case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_FULL:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* Add a case to switch */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c<br/>index b30c2cdc1a61..4da5adab799c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c</a></div><div class='hunk'>@@ -569,7 +569,7 @@ static void calculate_bandwidth(</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 			data-&gt;lb_partitions[i] = bw_floor2(bw_div(data-&gt;lb_size_per_component[i], data-&gt;lb_line_pitch), bw_int_to_fixed(1));</div><div class='del'>-			/*clamp the partitions to the maxium number supported by the lb*/</div><div class='add'>+			/* clamp the partitions to the maximum number supported by the lb */</div><div class='ctx'> 			if ((surface_type[i] != bw_def_graphics || dceip-&gt;graphics_lb_nodownscaling_multi_line_prefetching == 1)) {</div><div class='ctx'> 				data-&gt;lb_partitions_max[i] = bw_int_to_fixed(10);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1136,7 +1136,7 @@ static void calculate_bandwidth(</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	data-&gt;total_dmifmc_urgent_trips = bw_ceil2(bw_div(data-&gt;total_requests_for_adjusted_dmif_size, (bw_add(dceip-&gt;dmif_request_buffer_size, bw_int_to_fixed(vbios-&gt;number_of_request_slots_gmc_reserves_for_dmif_per_channel * data-&gt;number_of_dram_channels)))), bw_int_to_fixed(1));</div><div class='add'>+	data-&gt;total_dmifmc_urgent_trips = bw_ceil2(bw_div(data-&gt;total_requests_for_adjusted_dmif_size, (bw_add(dceip-&gt;dmif_request_buffer_size, bw_int_to_fixed((uint64_t)vbios-&gt;number_of_request_slots_gmc_reserves_for_dmif_per_channel * data-&gt;number_of_dram_channels)))), bw_int_to_fixed(1));</div><div class='ctx'> 	data-&gt;total_dmifmc_urgent_latency = bw_mul(vbios-&gt;dmifmc_urgent_latency, data-&gt;total_dmifmc_urgent_trips);</div><div class='ctx'> 	data-&gt;total_display_reads_required_data = bw_int_to_fixed(0);</div><div class='ctx'> 	data-&gt;total_display_reads_required_dram_access_data = bw_int_to_fixed(0);</div><div class='hunk'>@@ -1393,7 +1393,7 @@ static void calculate_bandwidth(</div><div class='ctx'> 						if ((bw_mtn(data-&gt;dram_speed_change_margin, bw_int_to_fixed(0)) &amp;&amp; bw_ltn(data-&gt;dram_speed_change_margin, bw_int_to_fixed(9999)))) {</div><div class='ctx'> 							/*determine the minimum dram clock change margin for each set of clock frequencies*/</div><div class='ctx'> 							data-&gt;min_dram_speed_change_margin[i][j] = bw_min2(data-&gt;min_dram_speed_change_margin[i][j], data-&gt;dram_speed_change_margin);</div><div class='del'>-							/*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/</div><div class='add'>+							/*compute the maximum clock frequency required for the dram clock change at each set of clock frequencies*/</div><div class='ctx'> 							data-&gt;dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data-&gt;src_pixels_for_first_output_pixel[k], dceip-&gt;display_pipe_throughput_factor), dceip-&gt;lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data-&gt;maximum_latency_hiding_with_cursor[k], vbios-&gt;nbp_state_change_latency), data-&gt;dmif_burst_time[i][j]), data-&gt;dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data-&gt;src_pixels_for_last_output_pixel[k], dceip-&gt;display_pipe_throughput_factor), dceip-&gt;lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data-&gt;maximum_latency_hiding_with_cursor[k], vbios-&gt;nbp_state_change_latency), data-&gt;dmif_burst_time[i][j]), data-&gt;dram_speed_change_line_source_transfer_time[k][i][j]), data-&gt;active_time[k]))));</div><div class='ctx'> 							if ((bw_ltn(data-&gt;dispclk_required_for_dram_speed_change_pipe[i][j], vbios-&gt;high_voltage_max_dispclk))) {</div><div class='ctx'> 								data-&gt;display_pstate_change_enable[k] = 1;</div><div class='hunk'>@@ -1407,7 +1407,7 @@ static void calculate_bandwidth(</div><div class='ctx'> 						if ((bw_mtn(data-&gt;dram_speed_change_margin, bw_int_to_fixed(0)) &amp;&amp; bw_ltn(data-&gt;dram_speed_change_margin, bw_int_to_fixed(9999)))) {</div><div class='ctx'> 							/*determine the minimum dram clock change margin for each display pipe*/</div><div class='ctx'> 							data-&gt;min_dram_speed_change_margin[i][j] = bw_min2(data-&gt;min_dram_speed_change_margin[i][j], data-&gt;dram_speed_change_margin);</div><div class='del'>-							/*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/</div><div class='add'>+							/*compute the maximum clock frequency required for the dram clock change at each set of clock frequencies*/</div><div class='ctx'> 							data-&gt;dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data-&gt;src_pixels_for_first_output_pixel[k], dceip-&gt;display_pipe_throughput_factor), dceip-&gt;lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data-&gt;maximum_latency_hiding_with_cursor[k], vbios-&gt;nbp_state_change_latency), data-&gt;dmif_burst_time[i][j]), data-&gt;dram_speed_change_line_source_transfer_time[k][i][j]), data-&gt;mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data-&gt;src_pixels_for_last_output_pixel[k], dceip-&gt;display_pipe_throughput_factor), dceip-&gt;lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data-&gt;maximum_latency_hiding_with_cursor[k], vbios-&gt;nbp_state_change_latency), data-&gt;dmif_burst_time[i][j]), data-&gt;dram_speed_change_line_source_transfer_time[k][i][j]), data-&gt;mcifwr_burst_time[i][j]), data-&gt;active_time[k]))));</div><div class='ctx'> 							if ((bw_ltn(data-&gt;dispclk_required_for_dram_speed_change_pipe[i][j], vbios-&gt;high_voltage_max_dispclk))) {</div><div class='ctx'> 								data-&gt;display_pstate_change_enable[k] = 1;</div><div class='hunk'>@@ -1853,7 +1853,7 @@ static void calculate_bandwidth(</div><div class='ctx'> 	/*compute total time to request one chunk from each active display pipe*/</div><div class='ctx'> 	for (i = 0; i &lt;= maximum_number_of_surfaces - 1; i++) {</div><div class='ctx'> 		if (data-&gt;enable[i]) {</div><div class='del'>-			data-&gt;chunk_request_time = bw_add(data-&gt;chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data-&gt;bytes_per_pixel[i]), data-&gt;useful_bytes_per_request[i])), bw_min2(sclk[data-&gt;sclk_level], bw_div(data-&gt;dispclk, bw_int_to_fixed(2))))));</div><div class='add'>+			data-&gt;chunk_request_time = bw_add(data-&gt;chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * (int64_t)data-&gt;bytes_per_pixel[i]), data-&gt;useful_bytes_per_request[i])), bw_min2(sclk[data-&gt;sclk_level], bw_div(data-&gt;dispclk, bw_int_to_fixed(2))))));</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	/*compute total time to request cursor data*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c<br/>index 1726bdf89bae..6073cadde76c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c</a></div><div class='hunk'>@@ -51,8 +51,6 @@ static inline unsigned long long complete_integer_division_u64(</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long long result;</div><div class='ctx'> </div><div class='del'>-	ASSERT(divisor);</div><div class='del'>-</div><div class='ctx'> 	result = div64_u64_rem(dividend, divisor, remainder);</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='hunk'>@@ -140,8 +138,6 @@ struct fixed31_32 dc_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2)</div><div class='ctx'> </div><div class='ctx'> 	res.value = arg1_int * arg2_int;</div><div class='ctx'> </div><div class='del'>-	ASSERT(res.value &lt;= LONG_MAX);</div><div class='del'>-</div><div class='ctx'> 	res.value &lt;&lt;= FIXED31_32_BITS_PER_FRACTIONAL_PART;</div><div class='ctx'> </div><div class='ctx'> 	tmp = arg1_int * arg2_fra;</div><div class='hunk'>@@ -185,8 +181,6 @@ struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg)</div><div class='ctx'> </div><div class='ctx'> 	res.value = arg_int * arg_int;</div><div class='ctx'> </div><div class='del'>-	ASSERT(res.value &lt;= LONG_MAX);</div><div class='del'>-</div><div class='ctx'> 	res.value &lt;&lt;= FIXED31_32_BITS_PER_FRACTIONAL_PART;</div><div class='ctx'> </div><div class='ctx'> 	tmp = arg_int * arg_fra;</div><div class='hunk'>@@ -217,9 +211,6 @@ struct fixed31_32 dc_fixpt_recip(struct fixed31_32 arg)</div><div class='ctx'> 	 * @note</div><div class='ctx'> 	 * Good idea to use Newton's method</div><div class='ctx'> 	 */</div><div class='del'>-</div><div class='del'>-	ASSERT(arg.value);</div><div class='del'>-</div><div class='ctx'> 	return dc_fixpt_from_fraction(</div><div class='ctx'> 		dc_fixpt_one.value,</div><div class='ctx'> 		arg.value);</div><div class='hunk'>@@ -293,7 +284,7 @@ struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg)</div><div class='ctx'> 				dc_fixpt_mul(</div><div class='ctx'> 					square,</div><div class='ctx'> 					res),</div><div class='del'>-				n * (n - 1)));</div><div class='add'>+				(long long)n * (n - 1)));</div><div class='ctx'> </div><div class='ctx'> 		n -= 2;</div><div class='ctx'> 	} while (n != 0);</div><div class='hunk'>@@ -490,3 +481,30 @@ int dc_fixpt_s4d19(struct fixed31_32 arg)</div><div class='ctx'> 	else</div><div class='ctx'> 		return ux_dy(arg.value, 4, 19);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+struct fixed31_32 dc_fixpt_from_ux_dy(unsigned int value,</div><div class='add'>+	unsigned int integer_bits,</div><div class='add'>+	unsigned int fractional_bits)</div><div class='add'>+{</div><div class='add'>+	struct fixed31_32 fixpt_value = dc_fixpt_zero;</div><div class='add'>+	struct fixed31_32 fixpt_int_value = dc_fixpt_zero;</div><div class='add'>+	long long frac_mask = ((long long)1 &lt;&lt; (long long)integer_bits) - 1;</div><div class='add'>+</div><div class='add'>+	fixpt_value.value = (long long)value &lt;&lt; (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);</div><div class='add'>+	frac_mask = frac_mask &lt;&lt; fractional_bits;</div><div class='add'>+	fixpt_int_value.value = value &amp; frac_mask;</div><div class='add'>+	fixpt_int_value.value &lt;&lt;= (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);</div><div class='add'>+	fixpt_value.value |= fixpt_int_value.value;</div><div class='add'>+	return fixpt_value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct fixed31_32 dc_fixpt_from_int_dy(unsigned int int_value,</div><div class='add'>+	unsigned int frac_value,</div><div class='add'>+	unsigned int integer_bits,</div><div class='add'>+	unsigned int fractional_bits)</div><div class='add'>+{</div><div class='add'>+	struct fixed31_32 fixpt_value = dc_fixpt_from_int(int_value);</div><div class='add'>+</div><div class='add'>+	fixpt_value.value |= (long long)frac_value &lt;&lt; (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);</div><div class='add'>+	return fixpt_value;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/basics/vector.c b/drivers/gpu/drm/amd/display/dc/basics/vector.c<br/>index 6d2924114a3e..b413a672c2c0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/vector.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/basics/vector.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/basics/vector.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/basics/vector.c</a></div><div class='hunk'>@@ -170,7 +170,7 @@ bool dal_vector_remove_at_index(</div><div class='ctx'> 		memmove(</div><div class='ctx'> 			vector-&gt;container + (index * vector-&gt;struct_size),</div><div class='ctx'> 			vector-&gt;container + ((index + 1) * vector-&gt;struct_size),</div><div class='del'>-			(vector-&gt;count - index - 1) * vector-&gt;struct_size);</div><div class='add'>+			(size_t)(vector-&gt;count - index - 1) * vector-&gt;struct_size);</div><div class='ctx'> 	vector-&gt;count -= 1;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -219,7 +219,7 @@ bool dal_vector_insert_at(</div><div class='ctx'> 		memmove(</div><div class='ctx'> 			insert_address + vector-&gt;struct_size,</div><div class='ctx'> 			insert_address,</div><div class='del'>-			vector-&gt;struct_size * (vector-&gt;count - position));</div><div class='add'>+			(size_t)vector-&gt;struct_size * (vector-&gt;count - position));</div><div class='ctx'> </div><div class='ctx'> 	memmove(</div><div class='ctx'> 		insert_address,</div><div class='hunk'>@@ -271,7 +271,7 @@ struct vector *dal_vector_clone(</div><div class='ctx'> </div><div class='ctx'> 	/* copy vector's data */</div><div class='ctx'> 	memmove(vec_cloned-&gt;container, vector-&gt;container,</div><div class='del'>-			vec_cloned-&gt;struct_size * vec_cloned-&gt;capacity);</div><div class='add'>+			(size_t)vec_cloned-&gt;struct_size * vec_cloned-&gt;capacity);</div><div class='ctx'> </div><div class='ctx'> 	return vec_cloned;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c<br/>index 6450853fea94..d1471f34e419 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/bios_parser.c</a></div><div class='hunk'>@@ -44,8 +44,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "bios_parser_common.h"</div><div class='ctx'> </div><div class='del'>-#include "dc.h"</div><div class='del'>-</div><div class='ctx'> #define THREE_PERCENT_OF_10000 300</div><div class='ctx'> </div><div class='ctx'> #define LAST_RECORD_TYPE 0xff</div><div class='hunk'>@@ -69,7 +67,9 @@ static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,</div><div class='ctx'> 	ATOM_OBJECT *object);</div><div class='ctx'> static struct device_id device_type_from_device_id(uint16_t device_id);</div><div class='ctx'> static uint32_t signal_to_ss_id(enum as_signal_type signal);</div><div class='del'>-static uint32_t get_support_mask_for_device_id(struct device_id device_id);</div><div class='add'>+static uint32_t get_support_mask_for_device_id(</div><div class='add'>+	enum dal_device_type device_type,</div><div class='add'>+	uint32_t enum_id);</div><div class='ctx'> static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(</div><div class='ctx'> 	struct bios_parser *bp,</div><div class='ctx'> 	ATOM_OBJECT *object);</div><div class='hunk'>@@ -176,11 +176,8 @@ static struct graphics_object_id bios_parser_get_connector_id(</div><div class='ctx'> 		return object_id;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (tbl-&gt;ucNumberOfObjects &lt;= i) {</div><div class='del'>-		dm_error("Can't find connector id %d in connector table of size %d.\n",</div><div class='del'>-			 i, tbl-&gt;ucNumberOfObjects);</div><div class='add'>+	if (tbl-&gt;ucNumberOfObjects &lt;= i)</div><div class='ctx'> 		return object_id;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	id = le16_to_cpu(tbl-&gt;asObjects[i].usObjectID);</div><div class='ctx'> 	object_id = object_id_from_bios_object_id(id);</div><div class='hunk'>@@ -446,6 +443,7 @@ static enum bp_result get_firmware_info_v1_4(</div><div class='ctx'> 		le32_to_cpu(firmware_info-&gt;ulMinPixelClockPLL_Output) * 10;</div><div class='ctx'> 	info-&gt;pll_info.max_output_pxl_clk_pll_frequency =</div><div class='ctx'> 		le32_to_cpu(firmware_info-&gt;ulMaxPixelClockPLL_Output) * 10;</div><div class='add'>+	info-&gt;max_pixel_clock = le16_to_cpu(firmware_info-&gt;usMaxPixelClock) * 10;</div><div class='ctx'> </div><div class='ctx'> 	if (firmware_info-&gt;usFirmwareCapability.sbfAccess.MemoryClockSS_Support)</div><div class='ctx'> 		/* Since there is no information on the SS, report conservative</div><div class='hunk'>@@ -502,6 +500,7 @@ static enum bp_result get_firmware_info_v2_1(</div><div class='ctx'> 	info-&gt;external_clock_source_frequency_for_dp =</div><div class='ctx'> 		le16_to_cpu(firmwareInfo-&gt;usUniphyDPModeExtClkFreq) * 10;</div><div class='ctx'> 	info-&gt;min_allowed_bl_level = firmwareInfo-&gt;ucMinAllowedBL_Level;</div><div class='add'>+	info-&gt;max_pixel_clock = le16_to_cpu(firmwareInfo-&gt;usMaxPixelClock) * 10;</div><div class='ctx'> </div><div class='ctx'> 	/* There should be only one entry in the SS info table for Memory Clock</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -667,6 +666,9 @@ static enum bp_result get_ss_info_v3_1(</div><div class='ctx'> 	ss_table_header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) bios_get_image(&amp;bp-&gt;base,</div><div class='ctx'> 				DATA_TABLES(ASIC_InternalSS_Info),</div><div class='ctx'> 				struct_size(ss_table_header_include, asSpreadSpectrum, 1)));</div><div class='add'>+	if (!ss_table_header_include)</div><div class='add'>+		return BP_RESULT_UNSUPPORTED;</div><div class='add'>+</div><div class='ctx'> 	table_size =</div><div class='ctx'> 		(le16_to_cpu(ss_table_header_include-&gt;sHeader.usStructureSize)</div><div class='ctx'> 				- sizeof(ATOM_COMMON_TABLE_HEADER))</div><div class='hunk'>@@ -738,18 +740,94 @@ static enum bp_result bios_parser_transmitter_control(</div><div class='ctx'> 	return bp-&gt;cmd_tbl.transmitter_control(bp, cntl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum bp_result bios_parser_select_crtc_source(</div><div class='add'>+	struct dc_bios *dcb,</div><div class='add'>+	struct bp_crtc_source_select *bp_params)</div><div class='add'>+{</div><div class='add'>+	struct bios_parser *bp = BP_FROM_DCB(dcb);</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;cmd_tbl.select_crtc_source)</div><div class='add'>+		return BP_RESULT_FAILURE;</div><div class='add'>+</div><div class='add'>+	return bp-&gt;cmd_tbl.select_crtc_source(bp, bp_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum bp_result bios_parser_encoder_control(</div><div class='ctx'> 	struct dc_bios *dcb,</div><div class='ctx'> 	struct bp_encoder_control *cntl)</div><div class='ctx'> {</div><div class='ctx'> 	struct bios_parser *bp = BP_FROM_DCB(dcb);</div><div class='ctx'> </div><div class='add'>+	if (cntl-&gt;engine_id == ENGINE_ID_DACA) {</div><div class='add'>+		if (!bp-&gt;cmd_tbl.dac1_encoder_control)</div><div class='add'>+			return BP_RESULT_FAILURE;</div><div class='add'>+</div><div class='add'>+		return bp-&gt;cmd_tbl.dac1_encoder_control(</div><div class='add'>+			bp, cntl-&gt;action == ENCODER_CONTROL_ENABLE,</div><div class='add'>+			cntl-&gt;pixel_clock, ATOM_DAC1_PS2);</div><div class='add'>+	} else if (cntl-&gt;engine_id == ENGINE_ID_DACB) {</div><div class='add'>+		if (!bp-&gt;cmd_tbl.dac2_encoder_control)</div><div class='add'>+			return BP_RESULT_FAILURE;</div><div class='add'>+</div><div class='add'>+		return bp-&gt;cmd_tbl.dac2_encoder_control(</div><div class='add'>+			bp, cntl-&gt;action == ENCODER_CONTROL_ENABLE,</div><div class='add'>+			cntl-&gt;pixel_clock, ATOM_DAC1_PS2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!bp-&gt;cmd_tbl.dig_encoder_control)</div><div class='ctx'> 		return BP_RESULT_FAILURE;</div><div class='ctx'> </div><div class='ctx'> 	return bp-&gt;cmd_tbl.dig_encoder_control(bp, cntl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum bp_result bios_parser_dac_load_detection(</div><div class='add'>+	struct dc_bios *dcb,</div><div class='add'>+	enum engine_id engine_id,</div><div class='add'>+	enum dal_device_type device_type,</div><div class='add'>+	uint32_t enum_id)</div><div class='add'>+{</div><div class='add'>+	struct bios_parser *bp = BP_FROM_DCB(dcb);</div><div class='add'>+	struct dc_context *ctx = dcb-&gt;ctx;</div><div class='add'>+	struct bp_load_detection_parameters bp_params = {0};</div><div class='add'>+	enum bp_result bp_result;</div><div class='add'>+	uint32_t bios_0_scratch;</div><div class='add'>+	uint32_t device_id_mask = 0;</div><div class='add'>+</div><div class='add'>+	bp_params.engine_id = engine_id;</div><div class='add'>+	bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id);</div><div class='add'>+</div><div class='add'>+	if (engine_id != ENGINE_ID_DACA &amp;&amp;</div><div class='add'>+	    engine_id != ENGINE_ID_DACB)</div><div class='add'>+		return BP_RESULT_UNSUPPORTED;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;cmd_tbl.dac_load_detection)</div><div class='add'>+		return BP_RESULT_UNSUPPORTED;</div><div class='add'>+</div><div class='add'>+	if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT)</div><div class='add'>+		device_id_mask = ATOM_S0_CRT1_MASK;</div><div class='add'>+	else if (bp_params.device_id == ATOM_DEVICE_CRT2_SUPPORT)</div><div class='add'>+		device_id_mask = ATOM_S0_CRT2_MASK;</div><div class='add'>+	else</div><div class='add'>+		return BP_RESULT_UNSUPPORTED;</div><div class='add'>+</div><div class='add'>+	/* BIOS will write the detected devices to BIOS_SCRATCH_0, clear corresponding bit */</div><div class='add'>+	bios_0_scratch = dm_read_reg(ctx, bp-&gt;base.regs-&gt;BIOS_SCRATCH_0);</div><div class='add'>+	bios_0_scratch &amp;= ~device_id_mask;</div><div class='add'>+	dm_write_reg(ctx, bp-&gt;base.regs-&gt;BIOS_SCRATCH_0, bios_0_scratch);</div><div class='add'>+</div><div class='add'>+	bp_result = bp-&gt;cmd_tbl.dac_load_detection(bp, &amp;bp_params);</div><div class='add'>+</div><div class='add'>+	if (bp_result != BP_RESULT_OK)</div><div class='add'>+		return bp_result;</div><div class='add'>+</div><div class='add'>+	bios_0_scratch = dm_read_reg(ctx, bp-&gt;base.regs-&gt;BIOS_SCRATCH_0);</div><div class='add'>+</div><div class='add'>+	if (bios_0_scratch &amp; device_id_mask)</div><div class='add'>+		return BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	return BP_RESULT_FAILURE;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum bp_result bios_parser_adjust_pixel_clock(</div><div class='ctx'> 	struct dc_bios *dcb,</div><div class='ctx'> 	struct bp_adjust_pixel_clock_parameters *bp_params)</div><div class='hunk'>@@ -860,7 +938,7 @@ static bool bios_parser_is_device_id_supported(</div><div class='ctx'> {</div><div class='ctx'> 	struct bios_parser *bp = BP_FROM_DCB(dcb);</div><div class='ctx'> </div><div class='del'>-	uint32_t mask = get_support_mask_for_device_id(id);</div><div class='add'>+	uint32_t mask = get_support_mask_for_device_id(id.device_type, id.enum_id);</div><div class='ctx'> </div><div class='ctx'> 	return (le16_to_cpu(bp-&gt;object_info_tbl.v1_1-&gt;usDeviceSupport) &amp; mask) != 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1036,6 +1114,8 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(</div><div class='ctx'> 				&amp;bp-&gt;base,</div><div class='ctx'> 				DATA_TABLES(ASIC_InternalSS_Info),</div><div class='ctx'> 				struct_size(header, asSpreadSpectrum, 1)));</div><div class='add'>+	if (!header)</div><div class='add'>+		return result;</div><div class='ctx'> </div><div class='ctx'> 	memset(info, 0, sizeof(struct spread_spectrum_info));</div><div class='ctx'> </div><div class='hunk'>@@ -1109,6 +1189,8 @@ static enum bp_result get_ss_info_from_ss_info_table(</div><div class='ctx'> 	get_atom_data_table_revision(header, &amp;revision);</div><div class='ctx'> </div><div class='ctx'> 	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info));</div><div class='add'>+	if (!tbl)</div><div class='add'>+		return result;</div><div class='ctx'> </div><div class='ctx'> 	if (1 != revision.major || 2 &gt; revision.minor)</div><div class='ctx'> 		return result;</div><div class='hunk'>@@ -1636,6 +1718,8 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(</div><div class='ctx'> </div><div class='ctx'> 	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO,</div><div class='ctx'> 			DATA_TABLES(SS_Info));</div><div class='add'>+	if (!tbl)</div><div class='add'>+		return number;</div><div class='ctx'> </div><div class='ctx'> 	if (1 != revision.major || 2 &gt; revision.minor)</div><div class='ctx'> 		return number;</div><div class='hunk'>@@ -1718,6 +1802,8 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(</div><div class='ctx'> 				&amp;bp-&gt;base,</div><div class='ctx'> 				DATA_TABLES(ASIC_InternalSS_Info),</div><div class='ctx'> 				struct_size(header_include, asSpreadSpectrum, 1)));</div><div class='add'>+	if (!header_include)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	size = (le16_to_cpu(header_include-&gt;sHeader.usStructureSize)</div><div class='ctx'> 			- sizeof(ATOM_COMMON_TABLE_HEADER))</div><div class='hunk'>@@ -1731,6 +1817,7 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * get_ss_entry_number_from_internal_ss_info_tbl_V3_1</div><div class='ctx'>  * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of</div><div class='hunk'>@@ -1756,6 +1843,9 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(</div><div class='ctx'> 	header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) bios_get_image(&amp;bp-&gt;base,</div><div class='ctx'> 				DATA_TABLES(ASIC_InternalSS_Info),</div><div class='ctx'> 				struct_size(header_include, asSpreadSpectrum, 1)));</div><div class='add'>+	if (!header_include)</div><div class='add'>+		return number;</div><div class='add'>+</div><div class='ctx'> 	size = (le16_to_cpu(header_include-&gt;sHeader.usStructureSize) -</div><div class='ctx'> 			sizeof(ATOM_COMMON_TABLE_HEADER)) /</div><div class='ctx'> 					sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);</div><div class='hunk'>@@ -2139,11 +2229,10 @@ static uint32_t signal_to_ss_id(enum as_signal_type signal)</div><div class='ctx'> 	return clk_id_ss;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint32_t get_support_mask_for_device_id(struct device_id device_id)</div><div class='add'>+static uint32_t get_support_mask_for_device_id(</div><div class='add'>+	enum dal_device_type device_type,</div><div class='add'>+	uint32_t enum_id)</div><div class='ctx'> {</div><div class='del'>-	enum dal_device_type device_type = device_id.device_type;</div><div class='del'>-	uint32_t enum_id = device_id.enum_id;</div><div class='del'>-</div><div class='ctx'> 	switch (device_type) {</div><div class='ctx'> 	case DEVICE_TYPE_LCD:</div><div class='ctx'> 		switch (enum_id) {</div><div class='hunk'>@@ -2371,10 +2460,10 @@ static enum bp_result get_integrated_info_v8(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * get_integrated_info_v8</div><div class='add'>+ * get_integrated_info_v9</div><div class='ctx'>  *</div><div class='ctx'>  * @brief</div><div class='del'>- * Get V8 integrated BIOS information</div><div class='add'>+ * Get V9 integrated BIOS information</div><div class='ctx'>  *</div><div class='ctx'>  * @param</div><div class='ctx'>  * bios_parser *bp - [in]BIOS parser handler to get master data table</div><div class='hunk'>@@ -2552,8 +2641,8 @@ static enum bp_result construct_integrated_info(</div><div class='ctx'> </div><div class='ctx'> 	/* Sort voltage table from low to high*/</div><div class='ctx'> 	if (result == BP_RESULT_OK) {</div><div class='del'>-		uint32_t i;</div><div class='del'>-		uint32_t j;</div><div class='add'>+		int32_t i;</div><div class='add'>+		int32_t j;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 1; i &lt; NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {</div><div class='ctx'> 			for (j = i; j &gt; 0; --j) {</div><div class='hunk'>@@ -2819,8 +2908,12 @@ static const struct dc_vbios_funcs vbios_funcs = {</div><div class='ctx'> 	.is_device_id_supported = bios_parser_is_device_id_supported,</div><div class='ctx'> </div><div class='ctx'> 	/* COMMANDS */</div><div class='add'>+	.select_crtc_source = bios_parser_select_crtc_source,</div><div class='add'>+</div><div class='ctx'> 	.encoder_control = bios_parser_encoder_control,</div><div class='ctx'> </div><div class='add'>+	.dac_load_detection = bios_parser_dac_load_detection,</div><div class='add'>+</div><div class='ctx'> 	.transmitter_control = bios_parser_transmitter_control,</div><div class='ctx'> </div><div class='ctx'> 	.enable_crtc = bios_parser_enable_crtc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c<br/>index 05f392501c0a..550a9f1d03f8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c</a></div><div class='hunk'>@@ -75,6 +75,10 @@ static enum bp_result get_firmware_info_v3_4(</div><div class='ctx'> 	struct bios_parser *bp,</div><div class='ctx'> 	struct dc_firmware_info *info);</div><div class='ctx'> </div><div class='add'>+static enum bp_result get_firmware_info_v3_5(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct dc_firmware_info *info);</div><div class='add'>+</div><div class='ctx'> static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,</div><div class='ctx'> 		struct atom_display_object_path_v2 *object);</div><div class='ctx'> </div><div class='hunk'>@@ -1476,10 +1480,10 @@ static enum bp_result get_embedded_panel_info_v2_1(</div><div class='ctx'> 	/* not provided by VBIOS */</div><div class='ctx'> 	info-&gt;lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;</div><div class='ctx'> </div><div class='del'>-	info-&gt;lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds-&gt;lcd_timing.miscinfo</div><div class='del'>-			&amp; ATOM_HSYNC_POLARITY);</div><div class='del'>-	info-&gt;lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds-&gt;lcd_timing.miscinfo</div><div class='del'>-			&amp; ATOM_VSYNC_POLARITY);</div><div class='add'>+	info-&gt;lcd_timing.misc_info.H_SYNC_POLARITY = !(lvds-&gt;lcd_timing.miscinfo &amp;</div><div class='add'>+						       ATOM_HSYNC_POLARITY);</div><div class='add'>+	info-&gt;lcd_timing.misc_info.V_SYNC_POLARITY = !(lvds-&gt;lcd_timing.miscinfo &amp;</div><div class='add'>+						       ATOM_VSYNC_POLARITY);</div><div class='ctx'> </div><div class='ctx'> 	/* not provided by VBIOS */</div><div class='ctx'> 	info-&gt;lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;</div><div class='hunk'>@@ -1594,8 +1598,6 @@ static bool bios_parser_is_device_id_supported(</div><div class='ctx'> 		return (le16_to_cpu(bp-&gt;object_info_tbl.v1_5-&gt;supporteddevices) &amp; mask) != 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint32_t bios_parser_get_ss_entry_number(</div><div class='hunk'>@@ -1756,6 +1758,9 @@ static enum bp_result bios_parser_get_firmware_info(</div><div class='ctx'> 			case 4:</div><div class='ctx'> 				result = get_firmware_info_v3_4(bp, info);</div><div class='ctx'> 				break;</div><div class='add'>+			case 5:</div><div class='add'>+				result = get_firmware_info_v3_5(bp, info);</div><div class='add'>+				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1773,6 +1778,7 @@ static enum bp_result get_firmware_info_v3_1(</div><div class='ctx'> 	struct dc_firmware_info *info)</div><div class='ctx'> {</div><div class='ctx'> 	struct atom_firmware_info_v3_1 *firmware_info;</div><div class='add'>+	struct atom_firmware_info_v3_2 *firmware_info32;</div><div class='ctx'> 	struct atom_display_controller_info_v4_1 *dce_info = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (!info)</div><div class='hunk'>@@ -1780,11 +1786,13 @@ static enum bp_result get_firmware_info_v3_1(</div><div class='ctx'> </div><div class='ctx'> 	firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,</div><div class='ctx'> 			DATA_TABLES(firmwareinfo));</div><div class='add'>+	firmware_info32 = GET_IMAGE(struct atom_firmware_info_v3_2,</div><div class='add'>+			DATA_TABLES(firmwareinfo));</div><div class='ctx'> </div><div class='ctx'> 	dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,</div><div class='ctx'> 			DATA_TABLES(dce_info));</div><div class='ctx'> </div><div class='del'>-	if (!firmware_info || !dce_info)</div><div class='add'>+	if (!firmware_info || !firmware_info32 || !dce_info)</div><div class='ctx'> 		return BP_RESULT_BADBIOSTABLE;</div><div class='ctx'> </div><div class='ctx'> 	memset(info, 0, sizeof(*info));</div><div class='hunk'>@@ -1812,7 +1820,15 @@ static enum bp_result get_firmware_info_v3_1(</div><div class='ctx'> 				bp-&gt;cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	info-&gt;oem_i2c_present = false;</div><div class='add'>+	/* These fields are marked as reserved in v3_1, but they appear to be populated</div><div class='add'>+	 * properly.</div><div class='add'>+	 */</div><div class='add'>+	if (firmware_info32 &amp;&amp; firmware_info32-&gt;board_i2c_feature_id == 0x2) {</div><div class='add'>+		info-&gt;oem_i2c_present = true;</div><div class='add'>+		info-&gt;oem_i2c_obj_id = firmware_info32-&gt;board_i2c_feature_gpio_id;</div><div class='add'>+	} else {</div><div class='add'>+		info-&gt;oem_i2c_present = false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return BP_RESULT_OK;</div><div class='ctx'> }</div><div class='hunk'>@@ -2046,6 +2062,63 @@ static enum bp_result get_firmware_info_v3_4(</div><div class='ctx'> 	return BP_RESULT_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum bp_result get_firmware_info_v3_5(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct dc_firmware_info *info)</div><div class='add'>+{</div><div class='add'>+	struct atom_firmware_info_v3_5 *firmware_info;</div><div class='add'>+	struct atom_common_table_header *header;</div><div class='add'>+	struct atom_data_revision revision;</div><div class='add'>+	struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;</div><div class='add'>+</div><div class='add'>+	if (!info)</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+	firmware_info = GET_IMAGE(struct atom_firmware_info_v3_5,</div><div class='add'>+			DATA_TABLES(firmwareinfo));</div><div class='add'>+</div><div class='add'>+	if (!firmware_info)</div><div class='add'>+		return BP_RESULT_BADBIOSTABLE;</div><div class='add'>+</div><div class='add'>+	memset(info, 0, sizeof(*info));</div><div class='add'>+</div><div class='add'>+	if (firmware_info-&gt;board_i2c_feature_id == 0x2) {</div><div class='add'>+		info-&gt;oem_i2c_present = true;</div><div class='add'>+		info-&gt;oem_i2c_obj_id = firmware_info-&gt;board_i2c_feature_gpio_id;</div><div class='add'>+	} else {</div><div class='add'>+		info-&gt;oem_i2c_present = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	header = GET_IMAGE(struct atom_common_table_header,</div><div class='add'>+					DATA_TABLES(dce_info));</div><div class='add'>+</div><div class='add'>+	get_atom_data_table_revision(header, &amp;revision);</div><div class='add'>+</div><div class='add'>+	switch (revision.major) {</div><div class='add'>+	case 4:</div><div class='add'>+		switch (revision.minor) {</div><div class='add'>+		case 5:</div><div class='add'>+			dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,</div><div class='add'>+							DATA_TABLES(dce_info));</div><div class='add'>+</div><div class='add'>+			if (!dce_info_v4_5)</div><div class='add'>+				return BP_RESULT_BADBIOSTABLE;</div><div class='add'>+</div><div class='add'>+			 /* 100MHz expected */</div><div class='add'>+			info-&gt;pll_info.crystal_frequency = dce_info_v4_5-&gt;dce_refclk_10khz * 10;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	return BP_RESULT_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum bp_result bios_parser_get_encoder_cap_info(</div><div class='ctx'> 	struct dc_bios *dcb,</div><div class='ctx'> 	struct graphics_object_id object_id,</div><div class='hunk'>@@ -2400,6 +2473,25 @@ static enum bp_result get_vram_info_v30(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum bp_result get_vram_info_from_umc_info_v40(</div><div class='add'>+		struct bios_parser *bp,</div><div class='add'>+		struct dc_vram_info *info)</div><div class='add'>+{</div><div class='add'>+	struct atom_umc_info_v4_0 *info_v40;</div><div class='add'>+	enum bp_result result = BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	info_v40 = GET_IMAGE(struct atom_umc_info_v4_0,</div><div class='add'>+						DATA_TABLES(umc_info));</div><div class='add'>+</div><div class='add'>+	if (info_v40 == NULL)</div><div class='add'>+		return BP_RESULT_BADBIOSTABLE;</div><div class='add'>+</div><div class='add'>+	info-&gt;num_chans = info_v40-&gt;channel_num;</div><div class='add'>+	info-&gt;dram_channel_width_bytes = (1 &lt;&lt; info_v40-&gt;channel_width) / 8;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * get_integrated_info_v11</div><div class='ctx'>  *</div><div class='hunk'>@@ -2922,8 +3014,11 @@ static enum bp_result construct_integrated_info(</div><div class='ctx'> 	struct atom_common_table_header *header;</div><div class='ctx'> 	struct atom_data_revision revision;</div><div class='ctx'> </div><div class='del'>-	uint32_t i;</div><div class='del'>-	uint32_t j;</div><div class='add'>+	int32_t i;</div><div class='add'>+	int32_t j;</div><div class='add'>+</div><div class='add'>+	if (!info)</div><div class='add'>+		return result;</div><div class='ctx'> </div><div class='ctx'> 	if (info &amp;&amp; DATA_TABLES(integratedsysteminfo)) {</div><div class='ctx'> 		header = GET_IMAGE(struct atom_common_table_header,</div><div class='hunk'>@@ -2948,6 +3043,7 @@ static enum bp_result construct_integrated_info(</div><div class='ctx'> 				result = get_integrated_info_v2_1(bp, info);</div><div class='ctx'> 				break;</div><div class='ctx'> 			case 2:</div><div class='add'>+			case 3:</div><div class='ctx'> 				result = get_integrated_info_v2_2(bp, info);</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='hunk'>@@ -3003,11 +3099,12 @@ static enum bp_result construct_integrated_info(</div><div class='ctx'> 						info-&gt;ext_disp_conn_info.path[i].ext_encoder_obj_id.id,</div><div class='ctx'> 						info-&gt;ext_disp_conn_info.path[i].caps</div><div class='ctx'> 						);</div><div class='del'>-			if (info-&gt;ext_disp_conn_info.path[i].caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)</div><div class='del'>-				DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);</div><div class='add'>+			if ((info-&gt;ext_disp_conn_info.path[i].caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)</div><div class='add'>+				DC_LOG_BIOS("BIOS AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);</div><div class='ctx'> 			else if (bp-&gt;base.ctx-&gt;dc-&gt;config.force_bios_fixed_vs) {</div><div class='del'>-				info-&gt;ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;</div><div class='del'>-				DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);</div><div class='add'>+				info-&gt;ext_disp_conn_info.path[i].caps &amp;= ~AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;</div><div class='add'>+				info-&gt;ext_disp_conn_info.path[i].caps |= AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;</div><div class='add'>+				DC_LOG_BIOS("driver forced AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		// Log the Checksum and Voltage Swing</div><div class='hunk'>@@ -3037,11 +3134,33 @@ static enum bp_result bios_parser_get_vram_info(</div><div class='ctx'> 		struct dc_vram_info *info)</div><div class='ctx'> {</div><div class='ctx'> 	struct bios_parser *bp = BP_FROM_DCB(dcb);</div><div class='del'>-	static enum bp_result result = BP_RESULT_BADBIOSTABLE;</div><div class='add'>+	enum bp_result result = BP_RESULT_BADBIOSTABLE;</div><div class='ctx'> 	struct atom_common_table_header *header;</div><div class='ctx'> 	struct atom_data_revision revision;</div><div class='ctx'> </div><div class='del'>-	if (info &amp;&amp; DATA_TABLES(vram_info)) {</div><div class='add'>+	// vram info moved to umc_info for DCN4x</div><div class='add'>+	if (info &amp;&amp; DATA_TABLES(umc_info)) {</div><div class='add'>+		header = GET_IMAGE(struct atom_common_table_header,</div><div class='add'>+					DATA_TABLES(umc_info));</div><div class='add'>+</div><div class='add'>+		get_atom_data_table_revision(header, &amp;revision);</div><div class='add'>+</div><div class='add'>+		switch (revision.major) {</div><div class='add'>+		case 4:</div><div class='add'>+			switch (revision.minor) {</div><div class='add'>+			case 0:</div><div class='add'>+				result = get_vram_info_from_umc_info_v40(bp, info);</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result != BP_RESULT_OK &amp;&amp; info &amp;&amp; DATA_TABLES(vram_info)) {</div><div class='ctx'> 		header = GET_IMAGE(struct atom_common_table_header,</div><div class='ctx'> 					DATA_TABLES(vram_info));</div><div class='ctx'> </div><div class='hunk'>@@ -3664,7 +3783,7 @@ static bool bios_parser2_construct(</div><div class='ctx'> 	bp-&gt;base.integrated_info = bios_parser_create_integrated_info(&amp;bp-&gt;base);</div><div class='ctx'> 	bp-&gt;base.fw_info_valid = bios_parser_get_firmware_info(&amp;bp-&gt;base, &amp;bp-&gt;base.fw_info) == BP_RESULT_OK;</div><div class='ctx'> 	bios_parser_get_vram_info(&amp;bp-&gt;base, &amp;bp-&gt;base.vram_info);</div><div class='del'>-</div><div class='add'>+	bios_parser_get_soc_bb_info(&amp;bp-&gt;base, &amp;bp-&gt;base.bb_info);</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c<br/>index adc710fe4a45..8d2cf95ae739 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c</a></div><div class='hunk'>@@ -78,10 +78,3 @@ void bios_set_scratch_critical_state(</div><div class='ctx'> 	uint32_t critial_state = state ? 1 : 0;</div><div class='ctx'> 	REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-uint32_t bios_get_vga_enabled_displays(</div><div class='del'>-	struct dc_bios *bios)</div><div class='del'>-{</div><div class='del'>-	return REG_READ(BIOS_SCRATCH_3) &amp; 0XFFFF;</div><div class='del'>-}</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h<br/>index e1b4a40a353d..ab162f2fe577 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h</a></div><div class='hunk'>@@ -34,7 +34,6 @@ uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,</div><div class='ctx'> bool bios_is_accelerated_mode(struct dc_bios *bios);</div><div class='ctx'> void bios_set_scratch_acc_mode_change(struct dc_bios *bios, uint32_t state);</div><div class='ctx'> void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);</div><div class='del'>-uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios);</div><div class='ctx'> </div><div class='ctx'> #define GET_IMAGE(type, offset) ((type *) bios_get_image(&amp;bp-&gt;base, offset, sizeof(type)))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c<br/>index 86f9198e7501..22457f417e65 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/command_table.c</a></div><div class='hunk'>@@ -52,7 +52,9 @@ static void init_transmitter_control(struct bios_parser *bp);</div><div class='ctx'> static void init_set_pixel_clock(struct bios_parser *bp);</div><div class='ctx'> static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);</div><div class='ctx'> static void init_adjust_display_pll(struct bios_parser *bp);</div><div class='add'>+static void init_select_crtc_source(struct bios_parser *bp);</div><div class='ctx'> static void init_dac_encoder_control(struct bios_parser *bp);</div><div class='add'>+static void init_dac_load_detection(struct bios_parser *bp);</div><div class='ctx'> static void init_dac_output_control(struct bios_parser *bp);</div><div class='ctx'> static void init_set_crtc_timing(struct bios_parser *bp);</div><div class='ctx'> static void init_enable_crtc(struct bios_parser *bp);</div><div class='hunk'>@@ -69,7 +71,9 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)</div><div class='ctx'> 	init_set_pixel_clock(bp);</div><div class='ctx'> 	init_enable_spread_spectrum_on_ppll(bp);</div><div class='ctx'> 	init_adjust_display_pll(bp);</div><div class='add'>+	init_select_crtc_source(bp);</div><div class='ctx'> 	init_dac_encoder_control(bp);</div><div class='add'>+	init_dac_load_detection(bp);</div><div class='ctx'> 	init_dac_output_control(bp);</div><div class='ctx'> 	init_set_crtc_timing(bp);</div><div class='ctx'> 	init_enable_crtc(bp);</div><div class='hunk'>@@ -399,7 +403,7 @@ static enum bp_result transmitter_control_v1_6(</div><div class='ctx'> static void init_transmitter_control(struct bios_parser *bp)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t frev;</div><div class='del'>-	uint8_t crev;</div><div class='add'>+	uint8_t crev = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,</div><div class='ctx'> 			frev, crev) == false)</div><div class='hunk'>@@ -993,7 +997,7 @@ static enum bp_result set_pixel_clock_v3(</div><div class='ctx'> 	allocation.sPCLKInput.usFbDiv =</div><div class='ctx'> 			cpu_to_le16((uint16_t)bp_params-&gt;feedback_divider);</div><div class='ctx'> 	allocation.sPCLKInput.ucFracFbDiv =</div><div class='del'>-			(uint8_t)bp_params-&gt;fractional_feedback_divider;</div><div class='add'>+			(uint8_t)(bp_params-&gt;fractional_feedback_divider / 100000);</div><div class='ctx'> 	allocation.sPCLKInput.ucPostDiv =</div><div class='ctx'> 			(uint8_t)bp_params-&gt;pixel_clock_post_divider;</div><div class='ctx'> </div><div class='hunk'>@@ -1612,6 +1616,198 @@ static enum bp_result adjust_display_pll_v3(</div><div class='ctx'> /*******************************************************************************</div><div class='ctx'>  ********************************************************************************</div><div class='ctx'>  **</div><div class='add'>+ **                  SELECT CRTC SOURCE</div><div class='add'>+ **</div><div class='add'>+ ********************************************************************************</div><div class='add'>+ *******************************************************************************/</div><div class='add'>+</div><div class='add'>+static enum bp_result select_crtc_source_v1(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_crtc_source_select *bp_params);</div><div class='add'>+static enum bp_result select_crtc_source_v2(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_crtc_source_select *bp_params);</div><div class='add'>+static enum bp_result select_crtc_source_v3(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_crtc_source_select *bp_params);</div><div class='add'>+</div><div class='add'>+static void init_select_crtc_source(struct bios_parser *bp)</div><div class='add'>+{</div><div class='add'>+	switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {</div><div class='add'>+	case 1:</div><div class='add'>+		bp-&gt;cmd_tbl.select_crtc_source = select_crtc_source_v1;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		bp-&gt;cmd_tbl.select_crtc_source = select_crtc_source_v2;</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		bp-&gt;cmd_tbl.select_crtc_source = select_crtc_source_v3;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		bp-&gt;cmd_tbl.select_crtc_source = NULL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum bp_result select_crtc_source_v1(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_crtc_source_select *bp_params)</div><div class='add'>+{</div><div class='add'>+	enum bp_result result = BP_RESULT_FAILURE;</div><div class='add'>+	SELECT_CRTC_SOURCE_PS_ALLOCATION params;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;cmd_helper-&gt;controller_id_to_atom(bp_params-&gt;controller_id, &amp;params.ucCRTC))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+	switch (bp_params-&gt;engine_id) {</div><div class='add'>+	case ENGINE_ID_DACA:</div><div class='add'>+		params.ucDevice = ATOM_DEVICE_CRT1_INDEX;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DACB:</div><div class='add'>+		params.ucDevice = ATOM_DEVICE_CRT2_INDEX;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))</div><div class='add'>+		result = BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool select_crtc_source_v2_encoder_id(</div><div class='add'>+	enum engine_id engine_id, uint8_t *out_encoder_id)</div><div class='add'>+{</div><div class='add'>+	uint8_t encoder_id = 0;</div><div class='add'>+</div><div class='add'>+	switch (engine_id) {</div><div class='add'>+	case ENGINE_ID_DIGA:</div><div class='add'>+		encoder_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGB:</div><div class='add'>+		encoder_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGC:</div><div class='add'>+		encoder_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGD:</div><div class='add'>+		encoder_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGE:</div><div class='add'>+		encoder_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGF:</div><div class='add'>+		encoder_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGG:</div><div class='add'>+		encoder_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DACA:</div><div class='add'>+		encoder_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DACB:</div><div class='add'>+		encoder_id = ASIC_INT_DAC2_ENCODER_ID;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*out_encoder_id = encoder_id;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool select_crtc_source_v2_encoder_mode(</div><div class='add'>+	enum signal_type signal_type, uint8_t *out_encoder_mode)</div><div class='add'>+{</div><div class='add'>+	uint8_t encoder_mode = 0;</div><div class='add'>+</div><div class='add'>+	switch (signal_type) {</div><div class='add'>+	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+	case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_DVI;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_HDMI;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_LVDS:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_LVDS;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_RGB:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_CRT;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_DP;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT_MST:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_DP_MST;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_EDP:</div><div class='add'>+		encoder_mode = ATOM_ENCODER_MODE_DP;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*out_encoder_mode = encoder_mode;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum bp_result select_crtc_source_v2(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_crtc_source_select *bp_params)</div><div class='add'>+{</div><div class='add'>+	enum bp_result result = BP_RESULT_FAILURE;</div><div class='add'>+	SELECT_CRTC_SOURCE_PARAMETERS_V3 params;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;cmd_helper-&gt;controller_id_to_atom(bp_params-&gt;controller_id, &amp;params.ucCRTC))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+	if (!select_crtc_source_v2_encoder_id(</div><div class='add'>+		bp_params-&gt;engine_id,</div><div class='add'>+		&amp;params.ucEncoderID))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+	if (!select_crtc_source_v2_encoder_mode(</div><div class='add'>+		bp_params-&gt;sink_signal,</div><div class='add'>+		&amp;params.ucEncodeMode))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))</div><div class='add'>+		result = BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum bp_result select_crtc_source_v3(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_crtc_source_select *bp_params)</div><div class='add'>+{</div><div class='add'>+	enum bp_result result = BP_RESULT_FAILURE;</div><div class='add'>+	SELECT_CRTC_SOURCE_PARAMETERS_V3 params;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;cmd_helper-&gt;controller_id_to_atom(bp_params-&gt;controller_id, &amp;params.ucCRTC))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+	if (!select_crtc_source_v2_encoder_id(</div><div class='add'>+		bp_params-&gt;engine_id,</div><div class='add'>+		&amp;params.ucEncoderID))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+	if (!select_crtc_source_v2_encoder_mode(</div><div class='add'>+		bp_params-&gt;sink_signal,</div><div class='add'>+		&amp;params.ucEncodeMode))</div><div class='add'>+		return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+	params.ucDstBpc = bp_params-&gt;bit_depth;</div><div class='add'>+</div><div class='add'>+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))</div><div class='add'>+		result = BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*******************************************************************************</div><div class='add'>+ ********************************************************************************</div><div class='add'>+ **</div><div class='ctx'>  **                  DAC ENCODER CONTROL</div><div class='ctx'>  **</div><div class='ctx'>  ********************************************************************************</div><div class='hunk'>@@ -1711,6 +1907,96 @@ static enum bp_result dac2_encoder_control_v1(</div><div class='ctx'> /*******************************************************************************</div><div class='ctx'>  ********************************************************************************</div><div class='ctx'>  **</div><div class='add'>+ **                  DAC LOAD DETECTION</div><div class='add'>+ **</div><div class='add'>+ ********************************************************************************</div><div class='add'>+ *******************************************************************************/</div><div class='add'>+</div><div class='add'>+static enum bp_result dac_load_detection_v1(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_load_detection_parameters *bp_params);</div><div class='add'>+</div><div class='add'>+static enum bp_result dac_load_detection_v3(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_load_detection_parameters *bp_params);</div><div class='add'>+</div><div class='add'>+static void init_dac_load_detection(struct bios_parser *bp)</div><div class='add'>+{</div><div class='add'>+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC_LoadDetection)) {</div><div class='add'>+	case 1:</div><div class='add'>+	case 2:</div><div class='add'>+		bp-&gt;cmd_tbl.dac_load_detection = dac_load_detection_v1;</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+	default:</div><div class='add'>+		bp-&gt;cmd_tbl.dac_load_detection = dac_load_detection_v3;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dac_load_detect_prepare_params(</div><div class='add'>+	struct _DAC_LOAD_DETECTION_PS_ALLOCATION *params,</div><div class='add'>+	enum engine_id engine_id,</div><div class='add'>+	uint16_t device_id,</div><div class='add'>+	uint8_t misc)</div><div class='add'>+{</div><div class='add'>+	uint8_t dac_type = ENGINE_ID_DACA;</div><div class='add'>+</div><div class='add'>+	if (engine_id == ENGINE_ID_DACB)</div><div class='add'>+		dac_type = ATOM_DAC_B;</div><div class='add'>+</div><div class='add'>+	params-&gt;sDacload.usDeviceID = cpu_to_le16(device_id);</div><div class='add'>+	params-&gt;sDacload.ucDacType = dac_type;</div><div class='add'>+	params-&gt;sDacload.ucMisc = misc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum bp_result dac_load_detection_v1(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_load_detection_parameters *bp_params)</div><div class='add'>+{</div><div class='add'>+	enum bp_result result = BP_RESULT_FAILURE;</div><div class='add'>+	DAC_LOAD_DETECTION_PS_ALLOCATION params;</div><div class='add'>+</div><div class='add'>+	dac_load_detect_prepare_params(</div><div class='add'>+		&amp;params,</div><div class='add'>+		bp_params-&gt;engine_id,</div><div class='add'>+		bp_params-&gt;device_id,</div><div class='add'>+		0);</div><div class='add'>+</div><div class='add'>+	if (EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params))</div><div class='add'>+		result = BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum bp_result dac_load_detection_v3(</div><div class='add'>+	struct bios_parser *bp,</div><div class='add'>+	struct bp_load_detection_parameters *bp_params)</div><div class='add'>+{</div><div class='add'>+	enum bp_result result = BP_RESULT_FAILURE;</div><div class='add'>+	DAC_LOAD_DETECTION_PS_ALLOCATION params;</div><div class='add'>+</div><div class='add'>+	uint8_t misc = 0;</div><div class='add'>+</div><div class='add'>+	if (bp_params-&gt;device_id == ATOM_DEVICE_CV_SUPPORT ||</div><div class='add'>+	    bp_params-&gt;device_id == ATOM_DEVICE_TV1_SUPPORT)</div><div class='add'>+		misc = DAC_LOAD_MISC_YPrPb;</div><div class='add'>+</div><div class='add'>+	dac_load_detect_prepare_params(</div><div class='add'>+		&amp;params,</div><div class='add'>+		bp_params-&gt;engine_id,</div><div class='add'>+		bp_params-&gt;device_id,</div><div class='add'>+		misc);</div><div class='add'>+</div><div class='add'>+	if (EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params))</div><div class='add'>+		result = BP_RESULT_OK;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*******************************************************************************</div><div class='add'>+ ********************************************************************************</div><div class='add'>+ **</div><div class='ctx'>  **                  DAC OUTPUT CONTROL</div><div class='ctx'>  **</div><div class='ctx'>  ********************************************************************************</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h<br/>index ad533775e724..e89b1ba0048b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/command_table.h</a></div><div class='hunk'>@@ -52,6 +52,9 @@ struct cmd_tbl {</div><div class='ctx'> 	enum bp_result (*adjust_display_pll)(</div><div class='ctx'> 		struct bios_parser *bp,</div><div class='ctx'> 		struct bp_adjust_pixel_clock_parameters *bp_params);</div><div class='add'>+	enum bp_result (*select_crtc_source)(</div><div class='add'>+		struct bios_parser *bp,</div><div class='add'>+		struct bp_crtc_source_select *bp_params);</div><div class='ctx'> 	enum bp_result (*dac1_encoder_control)(</div><div class='ctx'> 		struct bios_parser *bp,</div><div class='ctx'> 		bool enable,</div><div class='hunk'>@@ -68,6 +71,9 @@ struct cmd_tbl {</div><div class='ctx'> 	enum bp_result (*dac2_output_control)(</div><div class='ctx'> 		struct bios_parser *bp,</div><div class='ctx'> 		bool enable);</div><div class='add'>+	enum bp_result (*dac_load_detection)(</div><div class='add'>+		struct bios_parser *bp,</div><div class='add'>+		struct bp_load_detection_parameters *bp_params);</div><div class='ctx'> 	enum bp_result (*set_crtc_timing)(</div><div class='ctx'> 		struct bios_parser *bp,</div><div class='ctx'> 		struct bp_hw_crtc_timing_parameters *bp_params);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c<br/>index cbae1be7b009..f2b1720a6a66 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/command_table2.c</a></div><div class='hunk'>@@ -101,7 +101,6 @@ static void init_dig_encoder_control(struct bios_parser *bp)</div><div class='ctx'> 		bp-&gt;cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dm_output_to_console("Don't have dig_encoder_control for v%d\n", version);</div><div class='ctx'> 		bp-&gt;cmd_tbl.dig_encoder_control = encoder_control_fallback;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -210,6 +209,7 @@ static enum bp_result encoder_control_fallback(</div><div class='ctx'>  ******************************************************************************</div><div class='ctx'>  *****************************************************************************/</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> static enum bp_result transmitter_control_v1_6(</div><div class='ctx'> 	struct bios_parser *bp,</div><div class='ctx'> 	struct bp_transmitter_control *cntl);</div><div class='hunk'>@@ -225,9 +225,10 @@ static enum bp_result transmitter_control_fallback(</div><div class='ctx'> static void init_transmitter_control(struct bios_parser *bp)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t frev;</div><div class='del'>-	uint8_t crev;</div><div class='add'>+	uint8_t crev = 0;</div><div class='ctx'> </div><div class='del'>-	BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev);</div><div class='add'>+	if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) &amp;&amp; (bp-&gt;base.ctx-&gt;dc-&gt;ctx-&gt;dce_version &lt;= DCN_VERSION_2_0))</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='ctx'> </div><div class='ctx'> 	switch (crev) {</div><div class='ctx'> 	case 6:</div><div class='hunk'>@@ -237,7 +238,6 @@ static void init_transmitter_control(struct bios_parser *bp)</div><div class='ctx'> 		bp-&gt;cmd_tbl.transmitter_control = transmitter_control_v1_7;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dm_output_to_console("Don't have transmitter_control for v%d\n", crev);</div><div class='ctx'> 		bp-&gt;cmd_tbl.transmitter_control = transmitter_control_fallback;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -324,6 +324,21 @@ static void transmitter_control_dmcub_v1_7(</div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct dc_link *get_link_by_phy_id(struct dc *p_dc, uint32_t phy_id)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = NULL;</div><div class='add'>+</div><div class='add'>+	// Get Transition Bitmask from dc_link structure associated with PHY</div><div class='add'>+	for (uint8_t link_id = 0; link_id &lt; MAX_LINKS; link_id++) {</div><div class='add'>+		if (phy_id == p_dc-&gt;links[link_id]-&gt;link_enc-&gt;transmitter) {</div><div class='add'>+			link = p_dc-&gt;links[link_id];</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return link;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum bp_result transmitter_control_v1_7(</div><div class='ctx'> 	struct bios_parser *bp,</div><div class='ctx'> 	struct bp_transmitter_control *cntl)</div><div class='hunk'>@@ -362,7 +377,38 @@ static enum bp_result transmitter_control_v1_7(</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;base.ctx-&gt;dc-&gt;ctx-&gt;dmub_srv &amp;&amp;</div><div class='ctx'> 		bp-&gt;base.ctx-&gt;dc-&gt;debug.dmub_command_table) {</div><div class='add'>+		struct dm_process_phy_transition_init_params process_phy_transition_init_params = {0};</div><div class='add'>+		struct dc_link *link = get_link_by_phy_id(bp-&gt;base.ctx-&gt;dc, dig_v1_7.phyid);</div><div class='add'>+		bool is_phy_transition_interlock_allowed = false;</div><div class='add'>+		uint8_t action = dig_v1_7.action;</div><div class='add'>+</div><div class='add'>+		if (link) {</div><div class='add'>+			if (link-&gt;phy_transition_bitmask &amp;&amp;</div><div class='add'>+				(action == TRANSMITTER_CONTROL_ENABLE || action == TRANSMITTER_CONTROL_DISABLE)) {</div><div class='add'>+				is_phy_transition_interlock_allowed = true;</div><div class='add'>+</div><div class='add'>+				// Prepare input parameters for processing ACPI retimers</div><div class='add'>+				process_phy_transition_init_params.action                   = action;</div><div class='add'>+				process_phy_transition_init_params.display_port_lanes_count = cntl-&gt;lanes_number;</div><div class='add'>+				process_phy_transition_init_params.phy_id                   = dig_v1_7.phyid;</div><div class='add'>+				process_phy_transition_init_params.signal                   = cntl-&gt;signal;</div><div class='add'>+				process_phy_transition_init_params.sym_clock_10khz          = dig_v1_7.symclk_units.symclk_10khz;</div><div class='add'>+				process_phy_transition_init_params.display_port_link_rate   = link-&gt;cur_link_settings.link_rate;</div><div class='add'>+				process_phy_transition_init_params.transition_bitmask       = link-&gt;phy_transition_bitmask;</div><div class='add'>+			}</div><div class='add'>+			dig_v1_7.skip_phy_ssc_reduction = link-&gt;wa_flags.skip_phy_ssc_reduction;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// Handle PRE_OFF_TO_ON: Process ACPI PHY Transition Interlock</div><div class='add'>+		if (is_phy_transition_interlock_allowed &amp;&amp; action == TRANSMITTER_CONTROL_ENABLE)</div><div class='add'>+			dm_acpi_process_phy_transition_interlock(bp-&gt;base.ctx, process_phy_transition_init_params);</div><div class='add'>+</div><div class='ctx'> 		transmitter_control_dmcub_v1_7(bp-&gt;base.ctx-&gt;dmub_srv, &amp;dig_v1_7);</div><div class='add'>+</div><div class='add'>+		// Handle POST_ON_TO_OFF: Process ACPI PHY Transition Interlock</div><div class='add'>+		if (is_phy_transition_interlock_allowed &amp;&amp; action == TRANSMITTER_CONTROL_DISABLE)</div><div class='add'>+			dm_acpi_process_phy_transition_interlock(bp-&gt;base.ctx, process_phy_transition_init_params);</div><div class='add'>+</div><div class='ctx'> 		return BP_RESULT_OK;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -407,8 +453,6 @@ static void init_set_pixel_clock(struct bios_parser *bp)</div><div class='ctx'> 		bp-&gt;cmd_tbl.set_pixel_clock = set_pixel_clock_v7;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dm_output_to_console("Don't have set_pixel_clock for v%d\n",</div><div class='del'>-			 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));</div><div class='ctx'> 		bp-&gt;cmd_tbl.set_pixel_clock = set_pixel_clock_fallback;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -553,7 +597,6 @@ static void init_set_crtc_timing(struct bios_parser *bp)</div><div class='ctx'> 			set_crtc_using_dtd_timing_v3;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dm_output_to_console("Don't have set_crtc_timing for v%d\n", dtd_version);</div><div class='ctx'> 		bp-&gt;cmd_tbl.set_crtc_timing = NULL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -670,8 +713,6 @@ static void init_enable_crtc(struct bios_parser *bp)</div><div class='ctx'> 		bp-&gt;cmd_tbl.enable_crtc = enable_crtc_v1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dm_output_to_console("Don't have enable_crtc for v%d\n",</div><div class='del'>-			 BIOS_CMD_TABLE_PARA_REVISION(enablecrtc));</div><div class='ctx'> 		bp-&gt;cmd_tbl.enable_crtc = NULL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -863,8 +904,6 @@ static void init_set_dce_clock(struct bios_parser *bp)</div><div class='ctx'> 		bp-&gt;cmd_tbl.set_dce_clock = set_dce_clock_v2_1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dm_output_to_console("Don't have set_dce_clock for v%d\n",</div><div class='del'>-			 BIOS_CMD_TABLE_PARA_REVISION(setdceclock));</div><div class='ctx'> 		bp-&gt;cmd_tbl.set_dce_clock = NULL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1045,3 +1084,4 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)</div><div class='ctx'> </div><div class='ctx'> 	init_enable_lvtma_control(bp);</div><div class='ctx'> }</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c<br/>index e317a3615147..91bc8a06e2cf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c</a></div><div class='hunk'>@@ -293,3 +293,107 @@ uint8_t dal_cmd_table_helper_encoder_id_to_atom(</div><div class='ctx'> 		return ENCODER_OBJECT_ID_NONE;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+uint8_t phy_id_to_atom(enum transmitter t)</div><div class='add'>+{</div><div class='add'>+	uint8_t atom_phy_id;</div><div class='add'>+</div><div class='add'>+	switch (t) {</div><div class='add'>+	case TRANSMITTER_UNIPHY_A:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='add'>+		break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_B:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;</div><div class='add'>+		break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_C:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;</div><div class='add'>+		break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_D:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;</div><div class='add'>+		break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_E:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;</div><div class='add'>+		break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_F:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;</div><div class='add'>+		break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_G:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return atom_phy_id;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='add'>+		enum clock_source_id id)</div><div class='add'>+{</div><div class='add'>+	uint8_t atom_phy_clk_src_id = 0;</div><div class='add'>+</div><div class='add'>+	switch (id) {</div><div class='add'>+	case CLOCK_SOURCE_ID_PLL0:</div><div class='add'>+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;</div><div class='add'>+		break;</div><div class='add'>+	case CLOCK_SOURCE_ID_PLL1:</div><div class='add'>+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='add'>+		break;</div><div class='add'>+	case CLOCK_SOURCE_ID_PLL2:</div><div class='add'>+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;</div><div class='add'>+		break;</div><div class='add'>+	case CLOCK_SOURCE_ID_EXTERNAL:</div><div class='add'>+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return atom_phy_clk_src_id &gt;&gt; 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (atom_engine_id != NULL)</div><div class='add'>+		switch (id) {</div><div class='add'>+		case ENGINE_ID_DIGA:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGB:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGC:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGD:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGE:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGF:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGG:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DACA:</div><div class='add'>+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h<br/>index dfd30aaf4032..547700e119a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h</a></div><div class='hunk'>@@ -59,4 +59,12 @@ uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(</div><div class='ctx'> </div><div class='ctx'> uint8_t dal_cmd_table_helper_encoder_id_to_atom(</div><div class='ctx'> 	enum encoder_id id);</div><div class='add'>+</div><div class='add'>+uint8_t phy_id_to_atom(enum transmitter t);</div><div class='add'>+</div><div class='add'>+uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='add'>+		enum clock_source_id id);</div><div class='add'>+</div><div class='add'>+bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c<br/>index 117fc6d4c1de..268e2414b34f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c</a></div><div class='hunk'>@@ -82,12 +82,13 @@ bool dal_bios_parser_init_cmd_tbl_helper2(</div><div class='ctx'> 	case DCN_VERSION_3_21:</div><div class='ctx'> 	case DCN_VERSION_3_5:</div><div class='ctx'> 	case DCN_VERSION_3_51:</div><div class='add'>+	case DCN_VERSION_3_6:</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='ctx'> 		*h = dal_cmd_tbl_helper_dce112_get_table2();</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='del'>-		/* Unsupported DCE */</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='add'>+		*h = dal_cmd_tbl_helper_dce112_get_table2();</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c<br/>index 11bf247bb180..3099128223df 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c</a></div><div class='hunk'>@@ -31,39 +31,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "../command_table_helper.h"</div><div class='ctx'> </div><div class='del'>-static uint8_t phy_id_to_atom(enum transmitter t)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_id;</div><div class='del'>-</div><div class='del'>-	switch (t) {</div><div class='del'>-	case TRANSMITTER_UNIPHY_A:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_B:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYB;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_C:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYC;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_D:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYD;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_E:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYE;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_F:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYF;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_G:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYG;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return atom_phy_id;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;</div><div class='hunk'>@@ -94,32 +61,6 @@ static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> 	return atom_dig_mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='del'>-		enum clock_source_id id)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_clk_src_id = 0;</div><div class='del'>-</div><div class='del'>-	switch (id) {</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL0:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL1:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL2:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_EXTERNAL:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return atom_phy_clk_src_id &gt;&gt; 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t hpd_sel_to_atom(enum hpd_source_id id)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_hpd_sel = 0;</div><div class='hunk'>@@ -207,51 +148,6 @@ static bool clock_source_id_to_atom(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)</div><div class='del'>-{</div><div class='del'>-	bool result = false;</div><div class='del'>-</div><div class='del'>-	if (atom_engine_id != NULL)</div><div class='del'>-		switch (id) {</div><div class='del'>-		case ENGINE_ID_DIGA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGB:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGC:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGD:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGE:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGF:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGG:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DACA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_action = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c<br/>index 755b6e33140a..349f0e5d5856 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c</a></div><div class='hunk'>@@ -29,40 +29,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "include/bios_parser_types.h"</div><div class='ctx'> </div><div class='del'>-#include "../command_table_helper2.h"</div><div class='del'>-</div><div class='del'>-static uint8_t phy_id_to_atom(enum transmitter t)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_id;</div><div class='add'>+#include "../command_table_helper.h"</div><div class='ctx'> </div><div class='del'>-	switch (t) {</div><div class='del'>-	case TRANSMITTER_UNIPHY_A:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_B:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYB;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_C:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYC;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_D:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYD;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_E:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYE;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_F:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYF;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_G:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYG;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return atom_phy_id;</div><div class='del'>-}</div><div class='add'>+#include "../command_table_helper2.h"</div><div class='ctx'> </div><div class='ctx'> static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> {</div><div class='hunk'>@@ -91,32 +60,6 @@ static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> 	return atom_dig_mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='del'>-		enum clock_source_id id)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_clk_src_id = 0;</div><div class='del'>-</div><div class='del'>-	switch (id) {</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL0:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL1:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL2:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_EXTERNAL:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return atom_phy_clk_src_id &gt;&gt; 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t hpd_sel_to_atom(enum hpd_source_id id)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_hpd_sel = 0;</div><div class='hunk'>@@ -209,51 +152,6 @@ static bool clock_source_id_to_atom(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)</div><div class='del'>-{</div><div class='del'>-	bool result = false;</div><div class='del'>-</div><div class='del'>-	if (atom_engine_id != NULL)</div><div class='del'>-		switch (id) {</div><div class='del'>-		case ENGINE_ID_DIGA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGB:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGC:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGD:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGE:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGF:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGG:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DACA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_action = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c<br/>index 06b4f7fa4a50..1a5fefcde8af 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c</a></div><div class='hunk'>@@ -31,39 +31,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "../command_table_helper.h"</div><div class='ctx'> </div><div class='del'>-static uint8_t phy_id_to_atom(enum transmitter t)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_id;</div><div class='del'>-</div><div class='del'>-	switch (t) {</div><div class='del'>-	case TRANSMITTER_UNIPHY_A:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_B:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYB;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_C:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYC;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_D:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYD;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_E:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYE;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_F:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYF;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_G:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYG;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return atom_phy_id;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;</div><div class='hunk'>@@ -91,32 +58,6 @@ static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> 	return atom_dig_mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='del'>-		enum clock_source_id id)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_clk_src_id = 0;</div><div class='del'>-</div><div class='del'>-	switch (id) {</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL0:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL1:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL2:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_EXTERNAL:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return atom_phy_clk_src_id &gt;&gt; 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t hpd_sel_to_atom(enum hpd_source_id id)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_hpd_sel = 0;</div><div class='hunk'>@@ -209,51 +150,6 @@ static bool clock_source_id_to_atom(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)</div><div class='del'>-{</div><div class='del'>-	bool result = false;</div><div class='del'>-</div><div class='del'>-	if (atom_engine_id != NULL)</div><div class='del'>-		switch (id) {</div><div class='del'>-		case ENGINE_ID_DIGA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGB:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGC:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGD:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGE:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGF:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGG:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DACA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_action = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c<br/>index 710221b4f5c5..01ccc803040c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c</a></div><div class='hunk'>@@ -58,51 +58,6 @@ static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)</div><div class='ctx'> 	return atom_action;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)</div><div class='del'>-{</div><div class='del'>-	bool result = false;</div><div class='del'>-</div><div class='del'>-	if (atom_engine_id != NULL)</div><div class='del'>-		switch (id) {</div><div class='del'>-		case ENGINE_ID_DIGA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGB:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGC:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGD:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGE:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGF:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGG:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DACA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool clock_source_id_to_atom(</div><div class='ctx'> 	enum clock_source_id id,</div><div class='ctx'> 	uint32_t *atom_pll_id)</div><div class='hunk'>@@ -149,32 +104,6 @@ static bool clock_source_id_to_atom(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='del'>-		enum clock_source_id id)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_clk_src_id = 0;</div><div class='del'>-</div><div class='del'>-	switch (id) {</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL0:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL1:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL2:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_EXTERNAL:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return atom_phy_clk_src_id &gt;&gt; 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;</div><div class='hunk'>@@ -270,39 +199,6 @@ static uint8_t dig_encoder_sel_to_atom(enum engine_id id)</div><div class='ctx'> 	return atom_dig_encoder_sel;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t phy_id_to_atom(enum transmitter t)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_id;</div><div class='del'>-</div><div class='del'>-	switch (t) {</div><div class='del'>-	case TRANSMITTER_UNIPHY_A:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_B:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYB;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_C:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYC;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_D:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYD;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_E:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYE;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_F:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYF;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_G:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYG;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return atom_phy_id;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t disp_power_gating_action_to_atom(</div><div class='ctx'> 	enum bp_pipe_control_action action)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c b/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c<br/>index 8b30b558cf1f..2ec5264536c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c</a></div><div class='hunk'>@@ -58,51 +58,6 @@ static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)</div><div class='ctx'> 	return atom_action;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)</div><div class='del'>-{</div><div class='del'>-	bool result = false;</div><div class='del'>-</div><div class='del'>-	if (atom_engine_id != NULL)</div><div class='del'>-		switch (id) {</div><div class='del'>-		case ENGINE_ID_DIGA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGB:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGC:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGD:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGE:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGF:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DIGG:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		case ENGINE_ID_DACA:</div><div class='del'>-			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;</div><div class='del'>-			result = true;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool clock_source_id_to_atom(</div><div class='ctx'> 	enum clock_source_id id,</div><div class='ctx'> 	uint32_t *atom_pll_id)</div><div class='hunk'>@@ -149,32 +104,6 @@ static bool clock_source_id_to_atom(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t clock_source_id_to_atom_phy_clk_src_id(</div><div class='del'>-		enum clock_source_id id)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_clk_src_id = 0;</div><div class='del'>-</div><div class='del'>-	switch (id) {</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL0:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL1:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_PLL2:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;</div><div class='del'>-		break;</div><div class='del'>-	case CLOCK_SOURCE_ID_EXTERNAL:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return atom_phy_clk_src_id &gt;&gt; 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;</div><div class='hunk'>@@ -270,39 +199,6 @@ static uint8_t dig_encoder_sel_to_atom(enum engine_id id)</div><div class='ctx'> 	return atom_dig_encoder_sel;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t phy_id_to_atom(enum transmitter t)</div><div class='del'>-{</div><div class='del'>-	uint8_t atom_phy_id;</div><div class='del'>-</div><div class='del'>-	switch (t) {</div><div class='del'>-	case TRANSMITTER_UNIPHY_A:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_B:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYB;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_C:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYC;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_D:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYD;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_E:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYE;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_F:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYF;</div><div class='del'>-		break;</div><div class='del'>-	case TRANSMITTER_UNIPHY_G:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYG;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		atom_phy_id = ATOM_PHY_ID_UNIPHYA;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return atom_phy_id;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint8_t disp_power_gating_action_to_atom(</div><div class='ctx'> 	enum bp_pipe_control_action action)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile<br/>index 1c443e549afa..60021671b386 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile</a></div><div class='hunk'>@@ -83,7 +83,6 @@ CLK_MGR_DCN10 = rv1_clk_mgr.o rv1_clk_mgr_vbios_smu.o rv2_clk_mgr.o</div><div class='ctx'> AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)</div><div class='del'>-</div><div class='ctx'> ###############################################################################</div><div class='ctx'> # DCN20</div><div class='ctx'> ###############################################################################</div><div class='hunk'>@@ -113,7 +112,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)</div><div class='ctx'> ###############################################################################</div><div class='ctx'> # DCN30</div><div class='ctx'> ###############################################################################</div><div class='del'>-CLK_MGR_DCN30 = dcn30_clk_mgr.o dcn30_clk_mgr_smu_msg.o</div><div class='add'>+CLK_MGR_DCN30 = dcn30_clk_mgr.o dcn30_clk_mgr_smu_msg.o dcn30m_clk_mgr.o dcn30m_clk_mgr_smu_msg.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))</div><div class='ctx'> </div><div class='hunk'>@@ -175,9 +174,18 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)</div><div class='ctx'> ###############################################################################</div><div class='ctx'> # DCN35</div><div class='ctx'> ###############################################################################</div><div class='del'>-CLK_MGR_DCN35 = dcn35_smu.o dcn35_clk_mgr.o</div><div class='add'>+CLK_MGR_DCN35 = dcn35_smu.o dcn351_clk_mgr.o dcn35_clk_mgr.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_CLK_MGR_DCN35 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn35/,$(CLK_MGR_DCN35))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN401</div><div class='add'>+###############################################################################</div><div class='add'>+CLK_MGR_DCN401 = dcn401_clk_mgr.o dcn401_clk_mgr_smu_msg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_CLK_MGR_DCN401 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn401/,$(CLK_MGR_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN401)</div><div class='ctx'> endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c<br/>index 9f0f25aee426..15cf13ec5302 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "dccg.h"</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce100/dce_clk_mgr.h"</div><div class='ctx'> #include "dce110/dce110_clk_mgr.h"</div><div class='hunk'>@@ -48,6 +48,7 @@</div><div class='ctx'> #include "dcn316/dcn316_clk_mgr.h"</div><div class='ctx'> #include "dcn32/dcn32_clk_mgr.h"</div><div class='ctx'> #include "dcn35/dcn35_clk_mgr.h"</div><div class='add'>+#include "dcn401/dcn401_clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> int clk_mgr_helper_get_active_display_cnt(</div><div class='ctx'> 		struct dc *dc,</div><div class='hunk'>@@ -58,6 +59,7 @@ int clk_mgr_helper_get_active_display_cnt(</div><div class='ctx'> 	display_count = 0;</div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		const struct dc_stream_state *stream = context-&gt;streams[i];</div><div class='add'>+		const struct dc_stream_status *stream_status = &amp;context-&gt;stream_status[i];</div><div class='ctx'> </div><div class='ctx'> 		/* Don't count SubVP phantom pipes as part of active</div><div class='ctx'> 		 * display count</div><div class='hunk'>@@ -65,13 +67,7 @@ int clk_mgr_helper_get_active_display_cnt(</div><div class='ctx'> 		if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		/*</div><div class='del'>-		 * Only notify active stream or virtual stream.</div><div class='del'>-		 * Need to notify virtual stream to work around</div><div class='del'>-		 * headless case. HPD does not fire when system is in</div><div class='del'>-		 * S0i2.</div><div class='del'>-		 */</div><div class='del'>-		if (!stream-&gt;dpms_off || stream-&gt;signal == SIGNAL_TYPE_VIRTUAL)</div><div class='add'>+		if (!stream-&gt;dpms_off || dc-&gt;is_switch_in_progress_dest || (stream_status &amp;&amp; stream_status-&gt;plane_count))</div><div class='ctx'> 			display_count++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -162,7 +158,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p</div><div class='ctx'> 			return NULL;</div><div class='ctx'> 		}</div><div class='ctx'> 		dce60_clk_mgr_construct(ctx, clk_mgr);</div><div class='del'>-		dce_clk_mgr_construct(ctx, clk_mgr);</div><div class='ctx'> 		return &amp;clk_mgr-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='hunk'>@@ -272,7 +267,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p</div><div class='ctx'> 			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='ctx'> 			return &amp;clk_mgr-&gt;base;</div><div class='ctx'> 		}</div><div class='del'>-		if (asic_id.chip_id == DEVICE_ID_NV_13FE) {</div><div class='add'>+		if (ctx-&gt;dce_version == DCN_VERSION_2_01) {</div><div class='ctx'> 			dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='ctx'> 			return &amp;clk_mgr-&gt;base;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -329,15 +324,14 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p</div><div class='ctx'> 	}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_FAMILY_GC_11_0_0: {</div><div class='del'>-	    struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);</div><div class='del'>-</div><div class='del'>-	    if (clk_mgr == NULL) {</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return NULL;</div><div class='del'>-	    }</div><div class='add'>+		struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	    dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='del'>-	    return &amp;clk_mgr-&gt;base;</div><div class='add'>+		if (clk_mgr == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+		dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='add'>+		return &amp;clk_mgr-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	case AMDGPU_FAMILY_GC_11_0_1: {</div><div class='hunk'>@@ -360,12 +354,26 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p</div><div class='ctx'> 			BREAK_TO_DEBUGGER();</div><div class='ctx'> 			return NULL;</div><div class='ctx'> 		}</div><div class='add'>+		if (ctx-&gt;dce_version == DCN_VERSION_3_51)</div><div class='add'>+			dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='add'>+		else</div><div class='add'>+			dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='ctx'> </div><div class='del'>-		dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);</div><div class='ctx'> 		return &amp;clk_mgr-&gt;base.base;</div><div class='ctx'> 	}</div><div class='ctx'> 	break;</div><div class='ctx'> </div><div class='add'>+	case AMDGPU_FAMILY_GC_12_0_0: {</div><div class='add'>+		struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);</div><div class='add'>+</div><div class='add'>+		if (clk_mgr == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return &amp;clk_mgr-&gt;base;</div><div class='add'>+	}</div><div class='add'>+	break;</div><div class='ctx'> #endif	/* CONFIG_DRM_AMD_DC_FP */</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT(0); /* Unknown Asic */</div><div class='hunk'>@@ -420,6 +428,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 	case AMDGPU_FAMILY_GC_11_5_0:</div><div class='ctx'> 		dcn35_clk_mgr_destroy(clk_mgr);</div><div class='ctx'> 		break;</div><div class='add'>+	case AMDGPU_FAMILY_GC_12_0_0:</div><div class='add'>+		dcn401_clk_mgr_destroy(clk_mgr);</div><div class='add'>+		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c<br/>index b77804cfde0f..6131ede2db7a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c</a></div><div class='hunk'>@@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = {</div><div class='ctx'> /* ClocksStateLow */</div><div class='ctx'> { .display_clk_khz = 352000, .pixel_clk_khz = 330000},</div><div class='ctx'> /* ClocksStateNominal */</div><div class='del'>-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },</div><div class='add'>+{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },</div><div class='ctx'> /* ClocksStatePerformance */</div><div class='del'>-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };</div><div class='add'>+{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };</div><div class='ctx'> </div><div class='ctx'> int dentist_get_divider_from_did(int did)</div><div class='ctx'> {</div><div class='hunk'>@@ -132,7 +132,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 	int dprefclk_wdivider;</div><div class='ctx'> 	int dprefclk_src_sel;</div><div class='ctx'> 	int dp_ref_clk_khz;</div><div class='del'>-	int target_div = 600000;</div><div class='add'>+	int target_div;</div><div class='ctx'> </div><div class='ctx'> 	/* ASSERT DP Reference Clock source is from DFS*/</div><div class='ctx'> 	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &amp;dprefclk_src_sel);</div><div class='hunk'>@@ -245,6 +245,11 @@ int dce_set_clock(</div><div class='ctx'> 	pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;</div><div class='ctx'> 	pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;</div><div class='ctx'> </div><div class='add'>+	/* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */</div><div class='add'>+	if (clk_mgr_base-&gt;ctx-&gt;dce_version == DCE_VERSION_6_0 ||</div><div class='add'>+	    clk_mgr_base-&gt;ctx-&gt;dce_version == DCE_VERSION_6_4)</div><div class='add'>+		pxl_clk_params.pll_id = CLOCK_SOURCE_ID_PLL0;</div><div class='add'>+</div><div class='ctx'> 	if (clk_mgr_dce-&gt;dfs_bypass_active)</div><div class='ctx'> 		pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;</div><div class='ctx'> </div><div class='hunk'>@@ -386,8 +391,6 @@ static void dce_pplib_apply_display_requirements(</div><div class='ctx'> {</div><div class='ctx'> 	struct dm_pp_display_configuration *pp_display_cfg = &amp;context-&gt;pp_display_cfg;</div><div class='ctx'> </div><div class='del'>-	pp_display_cfg-&gt;avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);</div><div class='del'>-</div><div class='ctx'> 	dce110_fill_display_configs(context, pp_display_cfg);</div><div class='ctx'> </div><div class='ctx'> 	if (memcmp(&amp;dc-&gt;current_state-&gt;pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)</div><div class='hunk'>@@ -400,11 +403,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> 	struct dm_pp_power_level_change_request level_change_req;</div><div class='del'>-	int patched_disp_clk = context-&gt;bw_ctx.bw.dce.dispclk_khz;</div><div class='del'>-</div><div class='del'>-	/*TODO: W/A for dal3 linux, investigate why this works */</div><div class='del'>-	if (!clk_mgr_dce-&gt;dfs_bypass_active)</div><div class='del'>-		patched_disp_clk = patched_disp_clk * 115 / 100;</div><div class='add'>+	const int max_disp_clk =</div><div class='add'>+		clk_mgr_dce-&gt;max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;</div><div class='add'>+	int patched_disp_clk = MIN(max_disp_clk, context-&gt;bw_ctx.bw.dce.dispclk_khz);</div><div class='ctx'> </div><div class='ctx'> 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);</div><div class='ctx'> 	/* get max clock state from PPLIB */</div><div class='hunk'>@@ -462,6 +463,9 @@ void dce_clk_mgr_construct(</div><div class='ctx'> 		clk_mgr-&gt;max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;</div><div class='ctx'> 	clk_mgr-&gt;cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;</div><div class='ctx'> </div><div class='add'>+	base-&gt;clks.max_supported_dispclk_khz =</div><div class='add'>+		clk_mgr-&gt;max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;</div><div class='add'>+</div><div class='ctx'> 	dce_clock_read_integrated_info(clk_mgr);</div><div class='ctx'> 	dce_clock_read_ss_info(clk_mgr);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c<br/>index 78df96882d6e..d50b9440210e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c</a></div><div class='hunk'>@@ -120,9 +120,15 @@ void dce110_fill_display_configs(</div><div class='ctx'> 	const struct dc_state *context,</div><div class='ctx'> 	struct dm_pp_display_configuration *pp_display_cfg)</div><div class='ctx'> {</div><div class='add'>+	struct dc *dc = context-&gt;clk_mgr-&gt;ctx-&gt;dc;</div><div class='ctx'> 	int j;</div><div class='ctx'> 	int num_cfgs = 0;</div><div class='ctx'> </div><div class='add'>+	pp_display_cfg-&gt;avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);</div><div class='add'>+	pp_display_cfg-&gt;disp_clk_khz = dc-&gt;clk_mgr-&gt;clks.dispclk_khz;</div><div class='add'>+	pp_display_cfg-&gt;avail_mclk_switch_time_in_disp_active_us = 0;</div><div class='add'>+	pp_display_cfg-&gt;crtc_index = dc-&gt;res_pool-&gt;res_cap-&gt;num_timing_generator;</div><div class='add'>+</div><div class='ctx'> 	for (j = 0; j &lt; context-&gt;stream_count; j++) {</div><div class='ctx'> 		int k;</div><div class='ctx'> </div><div class='hunk'>@@ -158,12 +164,29 @@ void dce110_fill_display_configs(</div><div class='ctx'> 			stream-&gt;link-&gt;cur_link_settings.link_rate;</div><div class='ctx'> 		cfg-&gt;link_settings.link_spread =</div><div class='ctx'> 			stream-&gt;link-&gt;cur_link_settings.link_spread;</div><div class='del'>-		cfg-&gt;sym_clock = stream-&gt;phy_pix_clk;</div><div class='add'>+		cfg-&gt;pixel_clock = stream-&gt;phy_pix_clk;</div><div class='ctx'> 		/* Round v_refresh*/</div><div class='ctx'> 		cfg-&gt;v_refresh = stream-&gt;timing.pix_clk_100hz * 100;</div><div class='ctx'> 		cfg-&gt;v_refresh /= stream-&gt;timing.h_total;</div><div class='ctx'> 		cfg-&gt;v_refresh = (cfg-&gt;v_refresh + stream-&gt;timing.v_total / 2)</div><div class='ctx'> 							/ stream-&gt;timing.v_total;</div><div class='add'>+</div><div class='add'>+		/* Find first CRTC index and calculate its line time.</div><div class='add'>+		 * This is necessary for DPM on SI GPUs.</div><div class='add'>+		 */</div><div class='add'>+		if (cfg-&gt;pipe_idx &lt; pp_display_cfg-&gt;crtc_index) {</div><div class='add'>+			const struct dc_crtc_timing *timing =</div><div class='add'>+				&amp;context-&gt;streams[0]-&gt;timing;</div><div class='add'>+</div><div class='add'>+			pp_display_cfg-&gt;crtc_index = cfg-&gt;pipe_idx;</div><div class='add'>+			pp_display_cfg-&gt;line_time_in_us =</div><div class='add'>+				timing-&gt;h_total * 10000 / timing-&gt;pix_clk_100hz;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!num_cfgs) {</div><div class='add'>+		pp_display_cfg-&gt;crtc_index = 0;</div><div class='add'>+		pp_display_cfg-&gt;line_time_in_us = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pp_display_cfg-&gt;display_count = num_cfgs;</div><div class='hunk'>@@ -195,7 +218,7 @@ void dce11_pplib_apply_display_requirements(</div><div class='ctx'> 	 * , then change minimum memory clock based on real-time bandwidth</div><div class='ctx'> 	 * limitation.</div><div class='ctx'> 	 */</div><div class='del'>-	if ((dc-&gt;ctx-&gt;asic_id.chip_family == FAMILY_AI) &amp;&amp;</div><div class='add'>+	if (dc-&gt;bw_vbios &amp;&amp; (dc-&gt;ctx-&gt;asic_id.chip_family == FAMILY_AI) &amp;&amp;</div><div class='ctx'> 	     ASICREV_IS_VEGA20_P(dc-&gt;ctx-&gt;asic_id.hw_internal_rev) &amp;&amp; (context-&gt;stream_count &gt;= 2)) {</div><div class='ctx'> 		pp_display_cfg-&gt;min_memory_clock_khz = max(pp_display_cfg-&gt;min_memory_clock_khz,</div><div class='ctx'> 							   (uint32_t) div64_s64(</div><div class='hunk'>@@ -223,25 +246,8 @@ void dce11_pplib_apply_display_requirements(</div><div class='ctx'> 	pp_display_cfg-&gt;min_engine_clock_deep_sleep_khz</div><div class='ctx'> 			= context-&gt;bw_ctx.bw.dce.sclk_deep_sleep_khz;</div><div class='ctx'> </div><div class='del'>-	pp_display_cfg-&gt;avail_mclk_switch_time_us =</div><div class='del'>-						dce110_get_min_vblank_time_us(context);</div><div class='del'>-	/* TODO: dce11.2*/</div><div class='del'>-	pp_display_cfg-&gt;avail_mclk_switch_time_in_disp_active_us = 0;</div><div class='del'>-</div><div class='del'>-	pp_display_cfg-&gt;disp_clk_khz = dc-&gt;clk_mgr-&gt;clks.dispclk_khz;</div><div class='del'>-</div><div class='ctx'> 	dce110_fill_display_configs(context, pp_display_cfg);</div><div class='ctx'> </div><div class='del'>-	/* TODO: is this still applicable?*/</div><div class='del'>-	if (pp_display_cfg-&gt;display_count == 1) {</div><div class='del'>-		const struct dc_crtc_timing *timing =</div><div class='del'>-			&amp;context-&gt;streams[0]-&gt;timing;</div><div class='del'>-</div><div class='del'>-		pp_display_cfg-&gt;crtc_index =</div><div class='del'>-			pp_display_cfg-&gt;disp_configs[0].pipe_idx;</div><div class='del'>-		pp_display_cfg-&gt;line_time_in_us = timing-&gt;h_total * 10000 / timing-&gt;pix_clk_100hz;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (memcmp(&amp;dc-&gt;current_state-&gt;pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)</div><div class='ctx'> 		dm_pp_apply_display_requirements(dc-&gt;ctx, pp_display_cfg);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c<br/>index 0267644717b2..69dd80d9f738 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c</a></div><div class='hunk'>@@ -83,22 +83,13 @@ static const struct state_dependent_clocks dce60_max_clks_by_state[] = {</div><div class='ctx'> static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='del'>-	int dprefclk_wdivider;</div><div class='del'>-	int dp_ref_clk_khz;</div><div class='del'>-	int target_div;</div><div class='add'>+	struct dc_context *ctx = clk_mgr_base-&gt;ctx;</div><div class='add'>+	int dp_ref_clk_khz = 0;</div><div class='ctx'> </div><div class='del'>-	/* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */</div><div class='del'>-</div><div class='del'>-	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently</div><div class='del'>-	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/</div><div class='del'>-	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &amp;dprefclk_wdivider);</div><div class='del'>-</div><div class='del'>-	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/</div><div class='del'>-	target_div = dentist_get_divider_from_did(dprefclk_wdivider);</div><div class='del'>-</div><div class='del'>-	/* Calculate the current DFS clock, in kHz.*/</div><div class='del'>-	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='del'>-		* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+	if (ASIC_REV_IS_TAHITI_P(ctx-&gt;asic_id.hw_internal_rev))</div><div class='add'>+		dp_ref_clk_khz = ctx-&gt;dc_bios-&gt;fw_info.default_display_engine_pll_frequency;</div><div class='add'>+	else</div><div class='add'>+		dp_ref_clk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='ctx'> </div><div class='ctx'> 	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);</div><div class='ctx'> }</div><div class='hunk'>@@ -109,8 +100,6 @@ static void dce60_pplib_apply_display_requirements(</div><div class='ctx'> {</div><div class='ctx'> 	struct dm_pp_display_configuration *pp_display_cfg = &amp;context-&gt;pp_display_cfg;</div><div class='ctx'> </div><div class='del'>-	pp_display_cfg-&gt;avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);</div><div class='del'>-</div><div class='ctx'> 	dce110_fill_display_configs(context, pp_display_cfg);</div><div class='ctx'> </div><div class='ctx'> 	if (memcmp(&amp;dc-&gt;current_state-&gt;pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)</div><div class='hunk'>@@ -123,11 +112,9 @@ static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> 	struct dm_pp_power_level_change_request level_change_req;</div><div class='del'>-	int patched_disp_clk = context-&gt;bw_ctx.bw.dce.dispclk_khz;</div><div class='del'>-</div><div class='del'>-	/*TODO: W/A for dal3 linux, investigate why this works */</div><div class='del'>-	if (!clk_mgr_dce-&gt;dfs_bypass_active)</div><div class='del'>-		patched_disp_clk = patched_disp_clk * 115 / 100;</div><div class='add'>+	const int max_disp_clk =</div><div class='add'>+		clk_mgr_dce-&gt;max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;</div><div class='add'>+	int patched_disp_clk = MIN(max_disp_clk, context-&gt;bw_ctx.bw.dce.dispclk_khz);</div><div class='ctx'> </div><div class='ctx'> 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);</div><div class='ctx'> 	/* get max clock state from PPLIB */</div><div class='hunk'>@@ -160,6 +147,8 @@ void dce60_clk_mgr_construct(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> {</div><div class='add'>+	struct clk_mgr *base = &amp;clk_mgr-&gt;base;</div><div class='add'>+</div><div class='ctx'> 	dce_clk_mgr_construct(ctx, clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	memcpy(clk_mgr-&gt;max_clks_by_state,</div><div class='hunk'>@@ -170,5 +159,8 @@ void dce60_clk_mgr_construct(</div><div class='ctx'> 	clk_mgr-&gt;clk_mgr_shift = &amp;disp_clk_shift;</div><div class='ctx'> 	clk_mgr-&gt;clk_mgr_mask = &amp;disp_clk_mask;</div><div class='ctx'> 	clk_mgr-&gt;base.funcs = &amp;dce60_funcs;</div><div class='add'>+</div><div class='add'>+	base-&gt;clks.max_supported_dispclk_khz =</div><div class='add'>+		clk_mgr-&gt;max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c<br/>index 2a74e2d74909..369421e46c52 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c</a></div><div class='hunk'>@@ -23,7 +23,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "reg_helper.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='ctx'> #include "rv1_clk_mgr.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c<br/>index 89b79dd39628..d82a52319088 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c</a></div><div class='hunk'>@@ -26,7 +26,6 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "rv1_clk_mgr_vbios_smu.h"</div><div class='ctx'> </div><div class='hunk'>@@ -143,17 +142,3 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di</div><div class='ctx'> </div><div class='ctx'> 	return actual_dispclk_set_mhz * 1000;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)</div><div class='del'>-{</div><div class='del'>-	int actual_dprefclk_set_mhz = -1;</div><div class='del'>-</div><div class='del'>-	actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(</div><div class='del'>-			clk_mgr,</div><div class='del'>-			VBIOSSMC_MSG_SetDprefclkFreq,</div><div class='del'>-			khz_to_mhz_ceil(clk_mgr-&gt;base.dprefclk_khz));</div><div class='del'>-</div><div class='del'>-	/* TODO: add code for programing DP DTO, currently this is down by command table */</div><div class='del'>-</div><div class='del'>-	return actual_dprefclk_set_mhz * 1000;</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h<br/>index 083cb3158859..81d7c912549c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h</a></div><div class='hunk'>@@ -27,6 +27,5 @@</div><div class='ctx'> #define DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_</div><div class='ctx'> </div><div class='ctx'> int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);</div><div class='del'>-int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> </div><div class='ctx'> #endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c<br/>index 5ee87965a078..bb4f3bd7532e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c</a></div><div class='hunk'>@@ -503,7 +503,7 @@ static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;cur_phyclk_req_table[link-&gt;link_index] = link-&gt;cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES * 2; i++) {</div><div class='add'>+	for (i = 0; i &lt; MAX_LINKS; i++) {</div><div class='ctx'> 		if (clk_mgr-&gt;cur_phyclk_req_table[i] &gt; max_phyclk_req)</div><div class='ctx'> 			max_phyclk_req = clk_mgr-&gt;cur_phyclk_req_table[i];</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c<br/>index 9c90090e7351..76c612ecfe3c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c</a></div><div class='hunk'>@@ -34,8 +34,8 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> </div><div class='ctx'> #include "cyan_skillfish_ip_offset.h"</div><div class='del'>-#include "dcn/dcn_2_0_3_offset.h"</div><div class='del'>-#include "dcn/dcn_2_0_3_sh_mask.h"</div><div class='add'>+#include "dcn/dcn_2_0_1_offset.h"</div><div class='add'>+#include "dcn/dcn_2_0_1_sh_mask.h"</div><div class='ctx'> #include "clk/clk_11_0_1_offset.h"</div><div class='ctx'> #include "clk/clk_11_0_1_sh_mask.h"</div><div class='ctx'> </div><div class='hunk'>@@ -100,13 +100,19 @@ static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> </div><div class='ctx'> 	if (clk_mgr_base-&gt;clks.dispclk_khz == 0 ||</div><div class='ctx'> 	    dc-&gt;debug.force_clock_mode &amp; 0x1) {</div><div class='add'>+		/* this is from resume or boot up, if forced_clock cfg option</div><div class='add'>+		 * used, we bypass program dispclk and DPPCLK, but need set them</div><div class='add'>+		 * for S3.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='ctx'> 		force_reset = true;</div><div class='add'>+		/* force_clock_mode 0x1:  force reset the clock even it is the</div><div class='add'>+		 * same clock as long as it is in Passive level.</div><div class='add'>+		 */</div><div class='ctx'> </div><div class='ctx'> 		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	clk_mgr_helper_get_active_display_cnt(dc, context);</div><div class='del'>-</div><div class='ctx'> 	if (should_set_clock(safe_to_lower, new_clocks-&gt;phyclk_khz, clk_mgr_base-&gt;clks.phyclk_khz))</div><div class='ctx'> 		clk_mgr_base-&gt;clks.phyclk_khz = new_clocks-&gt;phyclk_khz;</div><div class='ctx'> </div><div class='hunk'>@@ -150,11 +156,14 @@ static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;config.forced_clocks == false || (force_reset &amp;&amp; safe_to_lower)) {</div><div class='ctx'> 		if (dpp_clock_lowered) {</div><div class='add'>+			// if clock is being lowered, increase DTO before lowering refclk</div><div class='ctx'> 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);</div><div class='ctx'> 			dcn20_update_clocks_update_dentist(clk_mgr, context);</div><div class='ctx'> 		} else {</div><div class='add'>+			// if clock is being raised, increase refclk before lowering DTO</div><div class='ctx'> 			if (update_dppclk || update_dispclk)</div><div class='ctx'> 				dcn20_update_clocks_update_dentist(clk_mgr, context);</div><div class='add'>+			// always update dtos unless clock is lowered and not safe to lower</div><div class='ctx'> 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c<br/>index e3e1940198a9..e18097f82091 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c</a></div><div class='hunk'>@@ -320,16 +320,16 @@ static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_an</div><div class='ctx'> 	regs_and_bypass-&gt;dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;</div><div class='ctx'> </div><div class='ctx'> 	regs_and_bypass-&gt;dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dppclk_bypass &lt; 0 || regs_and_bypass-&gt;dppclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dppclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dppclk_bypass = 0;</div><div class='ctx'> 	regs_and_bypass-&gt;dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dcfclk_bypass &lt; 0 || regs_and_bypass-&gt;dcfclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dcfclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dcfclk_bypass = 0;</div><div class='ctx'> 	regs_and_bypass-&gt;dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dispclk_bypass &lt; 0 || regs_and_bypass-&gt;dispclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dispclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dispclk_bypass = 0;</div><div class='ctx'> 	regs_and_bypass-&gt;dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dprefclk_bypass &lt; 0 || regs_and_bypass-&gt;dprefclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dprefclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dprefclk_bypass = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (log_info-&gt;enabled) {</div><div class='hunk'>@@ -484,7 +484,8 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm</div><div class='ctx'> 			ranges-&gt;reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;</div><div class='ctx'> </div><div class='ctx'> 			/* Modify previous watermark range to cover up to max */</div><div class='del'>-			ranges-&gt;reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;</div><div class='add'>+			if (num_valid_sets &gt; 0)</div><div class='add'>+				ranges-&gt;reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;</div><div class='ctx'> 		}</div><div class='ctx'> 		num_valid_sets++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -548,7 +549,7 @@ static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_l</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;cur_phyclk_req_table[link-&gt;link_index] = link-&gt;cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES * 2; i++) {</div><div class='add'>+	for (i = 0; i &lt; MAX_LINKS; i++) {</div><div class='ctx'> 		if (clk_mgr-&gt;cur_phyclk_req_table[i] &gt; max_phyclk_req)</div><div class='ctx'> 			max_phyclk_req = clk_mgr-&gt;cur_phyclk_req_table[i];</div><div class='ctx'> 	}</div><div class='hunk'>@@ -642,7 +643,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params</div><div class='ctx'> </div><div class='ctx'> 	j = -1;</div><div class='ctx'> </div><div class='del'>-	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS &lt;= MAX_NUM_DPM_LVL);</div><div class='add'>+	static_assert(PP_SMU_NUM_FCLK_DPM_LEVELS &lt;= MAX_NUM_DPM_LVL,</div><div class='add'>+		"number of reported FCLK DPM levels exceed maximum");</div><div class='ctx'> </div><div class='ctx'> 	/* Find lowest DPM, FCLK is filled in reverse order*/</div><div class='ctx'> </div><div class='hunk'>@@ -770,7 +772,7 @@ void rn_clk_mgr_construct(</div><div class='ctx'> 		status = pp_smu-&gt;rn_funcs.get_dpm_clock_table(&amp;pp_smu-&gt;rn_funcs.pp_smu, &amp;clock_table);</div><div class='ctx'> </div><div class='ctx'> 		if (status == PP_SMU_RESULT_OK &amp;&amp;</div><div class='del'>-		    ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='add'>+		    ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='ctx'> 			rn_clk_mgr_helper_populate_bw_params (clk_mgr-&gt;base.bw_params, &amp;clock_table, ctx-&gt;dc_bios-&gt;integrated_info);</div><div class='ctx'> 			/* treat memory config as single channel if memory is asymmetrics. */</div><div class='ctx'> 			if (ctx-&gt;dc-&gt;config.is_asymmetric_memory)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c<br/>index 23b390245b5d..5a633333dbb5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c</a></div><div class='hunk'>@@ -164,20 +164,6 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis</div><div class='ctx'> 	return actual_dispclk_set_mhz * 1000;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)</div><div class='del'>-{</div><div class='del'>-	int actual_dprefclk_set_mhz = -1;</div><div class='del'>-</div><div class='del'>-	actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param(</div><div class='del'>-			clk_mgr,</div><div class='del'>-			VBIOSSMC_MSG_SetDprefclkFreq,</div><div class='del'>-			khz_to_mhz_ceil(clk_mgr-&gt;base.dprefclk_khz));</div><div class='del'>-</div><div class='del'>-	/* TODO: add code for programing DP DTO, currently this is down by command table */</div><div class='del'>-</div><div class='del'>-	return actual_dprefclk_set_mhz * 1000;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)</div><div class='ctx'> {</div><div class='ctx'> 	int actual_dcfclk_set_mhz = -1;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h<br/>index 1ce19d875358..f76fad87f0e1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h</a></div><div class='hunk'>@@ -30,7 +30,6 @@ enum dcn_pwr_state;</div><div class='ctx'> </div><div class='ctx'> int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);</div><div class='del'>-int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);</div><div class='ctx'> int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);</div><div class='ctx'> void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h<br/>index fa09c594fd36..06da34676965 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h</a></div><div class='hunk'>@@ -56,6 +56,7 @@</div><div class='ctx'> #define DALSMC_MSG_SetDisplayRefreshFromMall      0xF</div><div class='ctx'> #define DALSMC_MSG_SetExternalClientDfCstateAllow 0x10</div><div class='ctx'> #define DALSMC_MSG_BacoAudioD3PME                 0x11</div><div class='del'>-#define DALSMC_Message_Count                      0x12</div><div class='add'>+#define DALSMC_MSG_SmartAccess                    0x12</div><div class='add'>+#define DALSMC_Message_Count                      0x13</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c<br/>index 3271c8c7905d..ef77fcd164ed 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c</a></div><div class='hunk'>@@ -30,6 +30,7 @@</div><div class='ctx'> #include "dce100/dce_clk_mgr.h"</div><div class='ctx'> #include "dcn30/dcn30_clk_mgr.h"</div><div class='ctx'> #include "dml/dcn30/dcn30_fpu.h"</div><div class='add'>+#include "dcn30/dcn30m_clk_mgr.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='hunk'>@@ -474,7 +475,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;cur_phyclk_req_table[link-&gt;link_index] = link-&gt;cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES * 2; i++) {</div><div class='add'>+	for (i = 0; i &lt; MAX_LINKS; i++) {</div><div class='ctx'> 		if (clk_mgr-&gt;cur_phyclk_req_table[i] &gt; max_phyclk_req)</div><div class='ctx'> 			max_phyclk_req = clk_mgr-&gt;cur_phyclk_req_table[i];</div><div class='ctx'> 	}</div><div class='hunk'>@@ -498,7 +499,8 @@ static struct clk_mgr_funcs dcn3_funcs = {</div><div class='ctx'> 		.are_clock_states_equal = dcn3_are_clock_states_equal,</div><div class='ctx'> 		.enable_pme_wa = dcn3_enable_pme_wa,</div><div class='ctx'> 		.notify_link_rate_change = dcn30_notify_link_rate_change,</div><div class='del'>-		.is_smu_present = dcn3_is_smu_present</div><div class='add'>+		.is_smu_present = dcn3_is_smu_present,</div><div class='add'>+		.set_smartmux_switch = dcn30m_set_smartmux_switch</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)</div><div class='hunk'>@@ -560,11 +562,19 @@ void dcn3_clk_mgr_construct(</div><div class='ctx'> 	dce_clock_read_ss_info(clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;base.bw_params = kzalloc(sizeof(*clk_mgr-&gt;base.bw_params), GFP_KERNEL);</div><div class='add'>+	if (!clk_mgr-&gt;base.bw_params) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* need physical address of table to give to PMFW */</div><div class='ctx'> 	clk_mgr-&gt;wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr-&gt;base.ctx,</div><div class='ctx'> 			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),</div><div class='ctx'> 			&amp;clk_mgr-&gt;wm_range_table_addr);</div><div class='add'>+	if (!clk_mgr-&gt;wm_range_table) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c<br/>index bdbf18306698..827bc2431d5d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c</a></div><div class='hunk'>@@ -23,7 +23,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='ctx'> #include "dcn30_clk_mgr_smu_msg.h"</div><div class='ctx'> </div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='hunk'>@@ -54,6 +53,7 @@</div><div class='ctx'>  */</div><div class='ctx'> static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)</div><div class='ctx'> {</div><div class='add'>+	const uint32_t initial_max_retries = max_retries;</div><div class='ctx'> 	uint32_t reg = 0;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='hunk'>@@ -69,7 +69,7 @@ static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un</div><div class='ctx'> </div><div class='ctx'> 	/* handle DALSMC_Result_CmdRejectedBusy? */</div><div class='ctx'> </div><div class='del'>-	/* Log? */</div><div class='add'>+	TRACE_SMU_MSG_DELAY(0, 0, delay_us * (initial_max_retries - max_retries), clk_mgr-&gt;base.ctx);</div><div class='ctx'> </div><div class='ctx'> 	return reg;</div><div class='ctx'> }</div><div class='hunk'>@@ -89,6 +89,8 @@ static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint</div><div class='ctx'> 	/* Trigger the message transaction by writing the message ID */</div><div class='ctx'> 	REG_WRITE(DAL_MSG_REG, msg_id);</div><div class='ctx'> </div><div class='add'>+	TRACE_SMU_MSG(msg_id, param_in, clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='ctx'> 	result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000);</div><div class='ctx'> </div><div class='ctx'> 	if (IS_SMU_TIMEOUT(result)) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h<br/>index 61bb1d86182e..1bfd6f66f035 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> // SPDX-License-Identifier: MIT</div><div class='del'>-// This is a stripped-down version of the smu11_driver_if.h file for the relevant DAL interfaces.</div><div class='add'>+/* Copyright © 2022-2024 Advanced Micro Devices, Inc. All rights reserved. */</div><div class='ctx'> </div><div class='ctx'> #define SMU11_DRIVER_IF_VERSION 0x40</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c<br/>new file mode 100644<br/>index 000000000000..8e8a11c7437e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "clk_mgr_internal.h"</div><div class='add'>+#include "dcn30/dcn30m_clk_mgr.h"</div><div class='add'>+#include "dcn30m_clk_mgr_smu_msg.h"</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	return dcn30m_smu_set_smart_mux_switch(clk_mgr, pins_to_set);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h<br/>new file mode 100644<br/>index 000000000000..757985b2eadc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2019 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DCN30M_CLK_MGR_H__</div><div class='add'>+#define __DCN30M_CLK_MGR_H__</div><div class='add'>+</div><div class='add'>+uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set);</div><div class='add'>+</div><div class='add'>+#endif //__DCN30M_CLK_MGR_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c<br/>new file mode 100644<br/>index 000000000000..0dd0583ff21e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c</a></div><div class='hunk'>@@ -0,0 +1,118 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dcn30m_clk_mgr_smu_msg.h"</div><div class='add'>+</div><div class='add'>+#include "clk_mgr_internal.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dm_helpers.h"</div><div class='add'>+</div><div class='add'>+#include "dalsmc.h"</div><div class='add'>+</div><div class='add'>+#define mmDAL_MSG_REG  0x1628A</div><div class='add'>+#define mmDAL_ARG_REG  0x16273</div><div class='add'>+#define mmDAL_RESP_REG 0x16274</div><div class='add'>+</div><div class='add'>+#define REG(reg_name) \</div><div class='add'>+	mm ## reg_name</div><div class='add'>+</div><div class='add'>+#include "logger_types.h"</div><div class='add'>+#undef DC_LOGGER</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	CTX-&gt;logger</div><div class='add'>+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Function to be used instead of REG_WAIT macro because the wait ends when</div><div class='add'>+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h</div><div class='add'>+ * won't work with REG_WAIT.</div><div class='add'>+ */</div><div class='add'>+static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+	unsigned int delay_us, unsigned int max_retries)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg = 0;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		reg = REG_READ(DAL_RESP_REG);</div><div class='add'>+		if (reg)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (delay_us &gt;= 1000)</div><div class='add'>+			msleep(delay_us/1000);</div><div class='add'>+		else if (delay_us &gt; 0)</div><div class='add'>+			udelay(delay_us);</div><div class='add'>+	} while (max_retries--);</div><div class='add'>+</div><div class='add'>+	/* handle DALSMC_Result_CmdRejectedBusy? */</div><div class='add'>+</div><div class='add'>+	/* Log? */</div><div class='add'>+</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+	uint32_t msg_id, uint32_t param_in, uint32_t *param_out)</div><div class='add'>+{</div><div class='add'>+	uint32_t result;</div><div class='add'>+	/* Wait for response register to be ready */</div><div class='add'>+	dcn30m_smu_wait_for_response(clk_mgr, 10, 200000);</div><div class='add'>+</div><div class='add'>+	/* Clear response register */</div><div class='add'>+	REG_WRITE(DAL_RESP_REG, 0);</div><div class='add'>+</div><div class='add'>+	/* Set the parameter register for the SMU message */</div><div class='add'>+	REG_WRITE(DAL_ARG_REG, param_in);</div><div class='add'>+</div><div class='add'>+	/* Trigger the message transaction by writing the message ID */</div><div class='add'>+	REG_WRITE(DAL_MSG_REG, msg_id);</div><div class='add'>+</div><div class='add'>+	result = dcn30m_smu_wait_for_response(clk_mgr, 10, 200000);</div><div class='add'>+</div><div class='add'>+	if (IS_SMU_TIMEOUT(result))</div><div class='add'>+		dm_helpers_smu_timeout(CTX, msg_id, param_in, 10 * 200000);</div><div class='add'>+</div><div class='add'>+	/* Wait for response */</div><div class='add'>+	if (result == DALSMC_Result_OK) {</div><div class='add'>+		if (param_out)</div><div class='add'>+			*param_out = REG_READ(DAL_ARG_REG);</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Set SmartMux Switch: switch_dgpu = %d\n", pins_to_set);</div><div class='add'>+</div><div class='add'>+	dcn30m_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SmartAccess, pins_to_set, &amp;response);</div><div class='add'>+</div><div class='add'>+	return response;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h<br/>new file mode 100644<br/>index 000000000000..8a59a473fc5e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef DAL_DC_DCN30M_CLK_MGR_SMU_MSG_H_</div><div class='add'>+#define DAL_DC_DCN30M_CLK_MGR_SMU_MSG_H_</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+</div><div class='add'>+struct clk_mgr_internal;</div><div class='add'>+</div><div class='add'>+uint32_t     dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set);</div><div class='add'>+#endif /* DAL_DC_DCN30M_CLK_MGR_SMU_MSG_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c<br/>index aa9fd1dc550a..7aee02d56292 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c</a></div><div class='hunk'>@@ -252,16 +252,16 @@ static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_an</div><div class='ctx'> 	regs_and_bypass-&gt;dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;</div><div class='ctx'> </div><div class='ctx'> 	regs_and_bypass-&gt;dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dppclk_bypass &lt; 0 || regs_and_bypass-&gt;dppclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dppclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dppclk_bypass = 0;</div><div class='ctx'> 	regs_and_bypass-&gt;dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dcfclk_bypass &lt; 0 || regs_and_bypass-&gt;dcfclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dcfclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dcfclk_bypass = 0;</div><div class='ctx'> 	regs_and_bypass-&gt;dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dispclk_bypass &lt; 0 || regs_and_bypass-&gt;dispclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dispclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dispclk_bypass = 0;</div><div class='ctx'> 	regs_and_bypass-&gt;dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL &amp; 0x0007;</div><div class='del'>-	if (regs_and_bypass-&gt;dprefclk_bypass &lt; 0 || regs_and_bypass-&gt;dprefclk_bypass &gt; 4)</div><div class='add'>+	if (regs_and_bypass-&gt;dprefclk_bypass &gt; 4)</div><div class='ctx'> 		regs_and_bypass-&gt;dprefclk_bypass = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (log_info-&gt;enabled) {</div><div class='hunk'>@@ -563,10 +563,12 @@ static void vg_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> {</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	struct clk_bw_params *bw_params = clk_mgr-&gt;base.bw_params;</div><div class='add'>+	uint32_t max_dispclk = 0, max_dppclk = 0;</div><div class='ctx'> </div><div class='ctx'> 	j = -1;</div><div class='ctx'> </div><div class='del'>-	ASSERT(VG_NUM_FCLK_DPM_LEVELS &lt;= MAX_NUM_DPM_LVL);</div><div class='add'>+	static_assert(VG_NUM_FCLK_DPM_LEVELS &lt;= MAX_NUM_DPM_LVL,</div><div class='add'>+		"number of reported FCLK DPM levels exceeds maximum");</div><div class='ctx'> </div><div class='ctx'> 	/* Find lowest DPM, FCLK is filled in reverse order*/</div><div class='ctx'> </div><div class='hunk'>@@ -583,6 +585,15 @@ static void vg_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* dispclk and dppclk can be max at any voltage, same number of levels for both */</div><div class='add'>+	if (clock_table-&gt;NumDispClkLevelsEnabled &lt;= VG_NUM_DISPCLK_DPM_LEVELS &amp;&amp;</div><div class='add'>+	    clock_table-&gt;NumDispClkLevelsEnabled &lt;= VG_NUM_DPPCLK_DPM_LEVELS) {</div><div class='add'>+		max_dispclk = find_max_clk_value(clock_table-&gt;DispClocks, clock_table-&gt;NumDispClkLevelsEnabled);</div><div class='add'>+		max_dppclk = find_max_clk_value(clock_table-&gt;DppClocks, clock_table-&gt;NumDispClkLevelsEnabled);</div><div class='add'>+	} else {</div><div class='add'>+		ASSERT(0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	bw_params-&gt;clk_table.num_entries = j + 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; bw_params-&gt;clk_table.num_entries - 1; i++, j--) {</div><div class='hunk'>@@ -590,11 +601,17 @@ static void vg_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].memclk_mhz = clock_table-&gt;DfPstateTable[j].memclk;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].voltage = clock_table-&gt;DfPstateTable[j].voltage;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table-&gt;DfPstateTable[j].voltage);</div><div class='add'>+</div><div class='add'>+		/* Now update clocks we do read */</div><div class='add'>+		bw_params-&gt;clk_table.entries[i].dispclk_mhz = max_dispclk;</div><div class='add'>+		bw_params-&gt;clk_table.entries[i].dppclk_mhz = max_dppclk;</div><div class='ctx'> 	}</div><div class='ctx'> 	bw_params-&gt;clk_table.entries[i].fclk_mhz = clock_table-&gt;DfPstateTable[j].fclk;</div><div class='ctx'> 	bw_params-&gt;clk_table.entries[i].memclk_mhz = clock_table-&gt;DfPstateTable[j].memclk;</div><div class='ctx'> 	bw_params-&gt;clk_table.entries[i].voltage = clock_table-&gt;DfPstateTable[j].voltage;</div><div class='ctx'> 	bw_params-&gt;clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table-&gt;DcfClocks, VG_NUM_DCFCLK_DPM_LEVELS);</div><div class='add'>+	bw_params-&gt;clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table-&gt;DispClocks, VG_NUM_DISPCLK_DPM_LEVELS);</div><div class='add'>+	bw_params-&gt;clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table-&gt;DppClocks, VG_NUM_DPPCLK_DPM_LEVELS);</div><div class='ctx'> </div><div class='ctx'> 	bw_params-&gt;vram_type = bios_info-&gt;memory_type;</div><div class='ctx'> 	bw_params-&gt;num_channels = bios_info-&gt;ma_channel_number;</div><div class='hunk'>@@ -730,7 +747,7 @@ void vg_clk_mgr_construct(</div><div class='ctx'> 	clk_mgr-&gt;base.base.bw_params = &amp;vg_bw_params;</div><div class='ctx'> </div><div class='ctx'> 	vg_get_dpm_table_from_smu(&amp;clk_mgr-&gt;base, &amp;smu_dpm_clks);</div><div class='del'>-	if (ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='add'>+	if (ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='ctx'> 		vg_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 				&amp;clk_mgr-&gt;base,</div><div class='ctx'> 				ctx-&gt;dc_bios-&gt;integrated_info,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c<br/>index ce1386e22576..051052bd10c9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c</a></div><div class='hunk'>@@ -47,15 +47,16 @@</div><div class='ctx'> #include "dcn30/dcn30_clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #include "logger_types.h"</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "yellow_carp_offset.h"</div><div class='ctx'> #undef DC_LOGGER</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	clk_mgr-&gt;base.base.ctx-&gt;logger</div><div class='ctx'> </div><div class='del'>-#include "yellow_carp_offset.h"</div><div class='del'>-</div><div class='ctx'> #define regCLK1_CLK_PLL_REQ			0x0237</div><div class='ctx'> #define regCLK1_CLK_PLL_REQ_BASE_IDX		0</div><div class='ctx'> </div><div class='hunk'>@@ -562,7 +563,8 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk</div><div class='ctx'> </div><div class='ctx'> 	j = -1;</div><div class='ctx'> </div><div class='del'>-	ASSERT(NUM_DF_PSTATE_LEVELS &lt;= MAX_NUM_DPM_LVL);</div><div class='add'>+	static_assert(NUM_DF_PSTATE_LEVELS &lt;= MAX_NUM_DPM_LVL,</div><div class='add'>+		"number of reported pstate levels exceeds maximum");</div><div class='ctx'> </div><div class='ctx'> 	/* Find lowest DPM, FCLK is filled in reverse order*/</div><div class='ctx'> </div><div class='hunk'>@@ -784,7 +786,7 @@ void dcn31_clk_mgr_construct(</div><div class='ctx'> 					   i, smu_dpm_clks.dpm_clks-&gt;DfPstateTable[i].MemClk,</div><div class='ctx'> 					   i, smu_dpm_clks.dpm_clks-&gt;DfPstateTable[i].Voltage);</div><div class='ctx'> 		}</div><div class='del'>-		if (ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='ctx'> 			dcn31_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 					&amp;clk_mgr-&gt;base,</div><div class='ctx'> 					ctx-&gt;dc_bios-&gt;integrated_info,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c<br/>index 6904e95113c1..f201628e4e98 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c</a></div><div class='hunk'>@@ -23,7 +23,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c<br/>index a84f1e376dee..db687a13174d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c</a></div><div class='hunk'>@@ -48,14 +48,11 @@</div><div class='ctx'> #include "dcn31/dcn31_clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn314_smu.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #include "logger_types.h"</div><div class='del'>-#undef DC_LOGGER</div><div class='del'>-#define DC_LOGGER \</div><div class='del'>-	clk_mgr-&gt;base.base.ctx-&gt;logger</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #define MAX_INSTANCE                                        7</div><div class='hunk'>@@ -77,6 +74,10 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0,</div><div class='ctx'> 					{ { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } },</div><div class='ctx'> 					{ { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } };</div><div class='ctx'> </div><div class='add'>+#undef DC_LOGGER</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	clk_mgr-&gt;base.base.ctx-&gt;logger</div><div class='add'>+</div><div class='ctx'> #define regCLK1_CLK_PLL_REQ			0x0237</div><div class='ctx'> #define regCLK1_CLK_PLL_REQ_BASE_IDX		0</div><div class='ctx'> </div><div class='hunk'>@@ -87,8 +88,70 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0,</div><div class='ctx'> #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK	0x0000F000L</div><div class='ctx'> #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK	0xFFFF0000L</div><div class='ctx'> </div><div class='add'>+#define regCLK1_CLK0_DFS_CNTL				0x0269</div><div class='add'>+#define regCLK1_CLK0_DFS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK1_DFS_CNTL				0x026c</div><div class='add'>+#define regCLK1_CLK1_DFS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK2_DFS_CNTL				0x026f</div><div class='add'>+#define regCLK1_CLK2_DFS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK3_DFS_CNTL				0x0272</div><div class='add'>+#define regCLK1_CLK3_DFS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK4_DFS_CNTL				0x0275</div><div class='add'>+#define regCLK1_CLK4_DFS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK5_DFS_CNTL				0x0278</div><div class='add'>+#define regCLK1_CLK5_DFS_CNTL_BASE_IDX		0</div><div class='add'>+</div><div class='add'>+#define regCLK1_CLK0_CURRENT_CNT			0x02fb</div><div class='add'>+#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK1_CURRENT_CNT			0x02fc</div><div class='add'>+#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK2_CURRENT_CNT			0x02fd</div><div class='add'>+#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK3_CURRENT_CNT			0x02fe</div><div class='add'>+#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK4_CURRENT_CNT			0x02ff</div><div class='add'>+#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK5_CURRENT_CNT			0x0300</div><div class='add'>+#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+</div><div class='add'>+#define regCLK1_CLK0_BYPASS_CNTL			0x028a</div><div class='add'>+#define regCLK1_CLK0_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK1_BYPASS_CNTL			0x0293</div><div class='add'>+#define regCLK1_CLK1_BYPASS_CNTL_BASE_IDX	0</div><div class='ctx'> #define regCLK1_CLK2_BYPASS_CNTL			0x029c</div><div class='ctx'> #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK3_BYPASS_CNTL			0x02a5</div><div class='add'>+#define regCLK1_CLK3_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK4_BYPASS_CNTL			0x02ae</div><div class='add'>+#define regCLK1_CLK4_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK5_BYPASS_CNTL			0x02b7</div><div class='add'>+#define regCLK1_CLK5_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+</div><div class='add'>+#define regCLK1_CLK0_DS_CNTL				0x0283</div><div class='add'>+#define regCLK1_CLK0_DS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK1_DS_CNTL				0x028c</div><div class='add'>+#define regCLK1_CLK1_DS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK2_DS_CNTL				0x0295</div><div class='add'>+#define regCLK1_CLK2_DS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK3_DS_CNTL				0x029e</div><div class='add'>+#define regCLK1_CLK3_DS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK4_DS_CNTL				0x02a7</div><div class='add'>+#define regCLK1_CLK4_DS_CNTL_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK5_DS_CNTL				0x02b0</div><div class='add'>+#define regCLK1_CLK5_DS_CNTL_BASE_IDX		0</div><div class='add'>+</div><div class='add'>+#define regCLK1_CLK0_ALLOW_DS				0x0284</div><div class='add'>+#define regCLK1_CLK0_ALLOW_DS_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK1_ALLOW_DS				0x028d</div><div class='add'>+#define regCLK1_CLK1_ALLOW_DS_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK2_ALLOW_DS				0x0296</div><div class='add'>+#define regCLK1_CLK2_ALLOW_DS_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK3_ALLOW_DS				0x029f</div><div class='add'>+#define regCLK1_CLK3_ALLOW_DS_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK4_ALLOW_DS				0x02a8</div><div class='add'>+#define regCLK1_CLK4_ALLOW_DS_BASE_IDX		0</div><div class='add'>+#define regCLK1_CLK5_ALLOW_DS				0x02b1</div><div class='add'>+#define regCLK1_CLK5_ALLOW_DS_BASE_IDX		0</div><div class='ctx'> </div><div class='ctx'> #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT	0x0</div><div class='ctx'> #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT	0x10</div><div class='hunk'>@@ -185,6 +248,8 @@ void dcn314_init_clocks(struct clk_mgr *clk_mgr)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);</div><div class='ctx'> 	uint32_t ref_dtbclk = clk_mgr-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+	struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr_int);</div><div class='add'>+	struct clk_log_info log_info = {0};</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;(clk_mgr-&gt;clks), 0, sizeof(struct dc_clocks));</div><div class='ctx'> 	// Assumption is that boot state always supports pstate</div><div class='hunk'>@@ -200,6 +265,9 @@ void dcn314_init_clocks(struct clk_mgr *clk_mgr)</div><div class='ctx'> 			dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr-&gt;dprefclk_khz);</div><div class='ctx'> 	else</div><div class='ctx'> 		clk_mgr-&gt;dp_dto_source_clock_in_khz = clk_mgr-&gt;dprefclk_khz;</div><div class='add'>+</div><div class='add'>+	dcn314_dump_clk_registers(&amp;clk_mgr-&gt;boot_snapshot, &amp;clk_mgr_dcn314-&gt;base.base, &amp;log_info);</div><div class='add'>+	clk_mgr-&gt;clks.dispclk_khz =  clk_mgr-&gt;boot_snapshot.dispclk * 1000;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='hunk'>@@ -218,6 +286,8 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	if (dc-&gt;work_arounds.skip_clock_update)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	display_count = dcn314_get_active_display_cnt_wa(dc, context);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything</div><div class='ctx'> 	 * also if safe to lower is false, we just go in the higher state</div><div class='hunk'>@@ -236,7 +306,6 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		}</div><div class='ctx'> 		/* check that we're not already in lower */</div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {</div><div class='del'>-			display_count = dcn314_get_active_display_cnt_wa(dc, context);</div><div class='ctx'> 			/* if we can go lower, go lower */</div><div class='ctx'> 			if (display_count == 0) {</div><div class='ctx'> 				union display_idle_optimization_u idle_info = { 0 };</div><div class='hunk'>@@ -293,11 +362,19 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		update_dppclk = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz)) {</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz) &amp;&amp;</div><div class='add'>+	    (new_clocks-&gt;dispclk_khz &gt; 0 || (safe_to_lower &amp;&amp; display_count == 0))) {</div><div class='add'>+		int requested_dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='add'>+</div><div class='ctx'> 		dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);</div><div class='ctx'> </div><div class='add'>+		/* Clamp the requested clock to PMFW based on their limit. */</div><div class='add'>+		if (dc-&gt;debug.min_disp_clk_khz &gt; 0 &amp;&amp; requested_dispclk_khz &lt; dc-&gt;debug.min_disp_clk_khz)</div><div class='add'>+			requested_dispclk_khz = dc-&gt;debug.min_disp_clk_khz;</div><div class='add'>+</div><div class='add'>+		dcn314_smu_set_dispclk(clk_mgr, requested_dispclk_khz);</div><div class='ctx'> 		clk_mgr_base-&gt;clks.dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='del'>-		dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base-&gt;clks.dispclk_khz);</div><div class='add'>+</div><div class='ctx'> 		dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);</div><div class='ctx'> </div><div class='ctx'> 		update_dispclk = true;</div><div class='hunk'>@@ -385,10 +462,65 @@ bool dcn314_are_clock_states_equal(struct dc_clocks *a,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='add'>+</div><div class='add'>+static void dcn314_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	// read dtbclk</div><div class='add'>+	internal-&gt;CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dcfclk</div><div class='add'>+	internal-&gt;CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dcf deep sleep divider</div><div class='add'>+	internal-&gt;CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);</div><div class='add'>+	internal-&gt;CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);</div><div class='add'>+</div><div class='add'>+	// read dppclk</div><div class='add'>+	internal-&gt;CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dprefclk</div><div class='add'>+	internal-&gt;CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dispclk</div><div class='add'>+	internal-&gt;CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='ctx'> 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)</div><div class='ctx'> {</div><div class='del'>-	return;</div><div class='add'>+</div><div class='add'>+	struct dcn35_clk_internal internal = {0};</div><div class='add'>+</div><div class='add'>+	dcn314_dump_clk_registers_internal(&amp;internal, clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	regs_and_bypass-&gt;dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;</div><div class='add'>+	regs_and_bypass-&gt;dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;</div><div class='add'>+	regs_and_bypass-&gt;dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;</div><div class='add'>+</div><div class='add'>+	regs_and_bypass-&gt;dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dppclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dppclk_bypass = 0;</div><div class='add'>+	regs_and_bypass-&gt;dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dcfclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dcfclk_bypass = 0;</div><div class='add'>+	regs_and_bypass-&gt;dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dispclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dispclk_bypass = 0;</div><div class='add'>+	regs_and_bypass-&gt;dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dprefclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dprefclk_bypass = 0;</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct clk_bw_params dcn314_bw_params = {</div><div class='hunk'>@@ -896,7 +1028,7 @@ void dcn314_clk_mgr_construct(</div><div class='ctx'> 					   i, smu_dpm_clks.dpm_clks-&gt;DfPstateTable[i].Voltage);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info &amp;&amp; ctx-&gt;dc-&gt;config.use_default_clock_table == false) {</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;integrated_info &amp;&amp; ctx-&gt;dc-&gt;config.use_default_clock_table == false) {</div><div class='ctx'> 			dcn314_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 					&amp;clk_mgr-&gt;base,</div><div class='ctx'> 					ctx-&gt;dc_bios-&gt;integrated_info,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h<br/>index 002c28e80720..0577eb527bc3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h</a></div><div class='hunk'>@@ -65,4 +65,9 @@ void dcn314_clk_mgr_construct(struct dc_context *ctx,</div><div class='ctx'> </div><div class='ctx'> void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='add'>+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> #endif //__DCN314_CLK_MGR_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h<br/>index 047d19ea919c..78ca1e5c5e9e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h</a></div><div class='hunk'>@@ -37,34 +37,34 @@ typedef enum {</div><div class='ctx'> } WCK_RATIO_e;</div><div class='ctx'> </div><div class='ctx'> typedef struct {</div><div class='del'>-  uint32_t FClk;</div><div class='del'>-  uint32_t MemClk;</div><div class='del'>-  uint32_t Voltage;</div><div class='del'>-  uint8_t  WckRatio;</div><div class='del'>-  uint8_t  Spare[3];</div><div class='add'>+	uint32_t FClk;</div><div class='add'>+	uint32_t MemClk;</div><div class='add'>+	uint32_t Voltage;</div><div class='add'>+	uint8_t  WckRatio;</div><div class='add'>+	uint8_t  Spare[3];</div><div class='ctx'> } DfPstateTable314_t;</div><div class='ctx'> </div><div class='ctx'> //Freq in MHz</div><div class='ctx'> //Voltage in milli volts with 2 fractional bits</div><div class='ctx'> typedef struct {</div><div class='del'>-  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];</div><div class='del'>-  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];</div><div class='del'>-  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];</div><div class='del'>-  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];</div><div class='del'>-  uint32_t VClocks[NUM_VCN_DPM_LEVELS];</div><div class='del'>-  uint32_t DClocks[NUM_VCN_DPM_LEVELS];</div><div class='del'>-  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];</div><div class='del'>-  DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS];</div><div class='add'>+	uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t VClocks[NUM_VCN_DPM_LEVELS];</div><div class='add'>+	uint32_t DClocks[NUM_VCN_DPM_LEVELS];</div><div class='add'>+	uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];</div><div class='add'>+	DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS];</div><div class='ctx'> </div><div class='del'>-  uint8_t  NumDcfClkLevelsEnabled;</div><div class='del'>-  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk</div><div class='del'>-  uint8_t  NumSocClkLevelsEnabled;</div><div class='del'>-  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk</div><div class='del'>-  uint8_t  NumDfPstatesEnabled;</div><div class='del'>-  uint8_t  spare[3];</div><div class='add'>+	uint8_t  NumDcfClkLevelsEnabled;</div><div class='add'>+	uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk</div><div class='add'>+	uint8_t  NumSocClkLevelsEnabled;</div><div class='add'>+	uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk</div><div class='add'>+	uint8_t  NumDfPstatesEnabled;</div><div class='add'>+	uint8_t  spare[3];</div><div class='ctx'> </div><div class='del'>-  uint32_t MinGfxClk;</div><div class='del'>-  uint32_t MaxGfxClk;</div><div class='add'>+	uint32_t MinGfxClk;</div><div class='add'>+	uint32_t MaxGfxClk;</div><div class='ctx'> } DpmClocks314_t;</div><div class='ctx'> </div><div class='ctx'> struct dcn314_watermarks {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c<br/>index 644da4637320..3a881451e9da 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c</a></div><div class='hunk'>@@ -40,17 +40,51 @@</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> </div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='del'>-</div><div class='add'>+#include "reg_helper.h"</div><div class='ctx'> #include "logger_types.h"</div><div class='ctx'> #undef DC_LOGGER</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	clk_mgr-&gt;base.base.ctx-&gt;logger</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+</div><div class='add'>+#define MAX_INSTANCE                                        7</div><div class='add'>+#define MAX_SEGMENT                                         8</div><div class='add'>+</div><div class='add'>+struct IP_BASE_INSTANCE {</div><div class='add'>+	unsigned int segment[MAX_SEGMENT];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct IP_BASE {</div><div class='add'>+	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } },</div><div class='add'>+					{ { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } },</div><div class='add'>+					{ { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } },</div><div class='add'>+					{ { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } },</div><div class='add'>+					{ { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } },</div><div class='add'>+					{ { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } } } };</div><div class='add'>+</div><div class='add'>+#define regCLK1_CLK0_CURRENT_CNT			0x0314</div><div class='add'>+#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK1_CURRENT_CNT			0x0315</div><div class='add'>+#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK2_CURRENT_CNT			0x0316</div><div class='add'>+#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK3_CURRENT_CNT			0x0317</div><div class='add'>+#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK4_CURRENT_CNT			0x0318</div><div class='add'>+#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX	0</div><div class='add'>+#define regCLK1_CLK5_CURRENT_CNT			0x0319</div><div class='add'>+#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX	0</div><div class='ctx'> </div><div class='ctx'> #define TO_CLK_MGR_DCN315(clk_mgr)\</div><div class='ctx'> 	container_of(clk_mgr, struct clk_mgr_dcn315, base)</div><div class='ctx'> </div><div class='add'>+#define REG(reg_name) \</div><div class='add'>+	(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)</div><div class='add'>+</div><div class='ctx'> #define UNSUPPORTED_DCFCLK 10000000</div><div class='ctx'> #define MIN_DPP_DISP_CLK     100000</div><div class='ctx'> </div><div class='hunk'>@@ -130,7 +164,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> 	struct dc_clocks *new_clocks = &amp;context-&gt;bw_ctx.bw.dcn.clk;</div><div class='ctx'> 	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='del'>-	int display_count;</div><div class='add'>+	int display_count = 0;</div><div class='ctx'> 	bool update_dppclk = false;</div><div class='ctx'> 	bool update_dispclk = false;</div><div class='ctx'> 	bool dpp_clock_lowered = false;</div><div class='hunk'>@@ -145,6 +179,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	 */</div><div class='ctx'> 	clk_mgr_base-&gt;clks.zstate_support = new_clocks-&gt;zstate_support;</div><div class='ctx'> 	if (safe_to_lower) {</div><div class='add'>+		if (clk_mgr_base-&gt;clks.dtbclk_en &amp;&amp; !new_clocks-&gt;dtbclk_en) {</div><div class='add'>+			dcn315_smu_set_dtbclk(clk_mgr, false);</div><div class='add'>+			clk_mgr_base-&gt;clks.dtbclk_en = new_clocks-&gt;dtbclk_en;</div><div class='add'>+		}</div><div class='ctx'> 		/* check that we're not already in lower */</div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {</div><div class='ctx'> 			display_count = dcn315_get_active_display_cnt_wa(dc, context);</div><div class='hunk'>@@ -160,6 +198,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='add'>+		if (!clk_mgr_base-&gt;clks.dtbclk_en &amp;&amp; new_clocks-&gt;dtbclk_en) {</div><div class='add'>+			dcn315_smu_set_dtbclk(clk_mgr, true);</div><div class='add'>+			clk_mgr_base-&gt;clks.dtbclk_en = new_clocks-&gt;dtbclk_en;</div><div class='add'>+		}</div><div class='ctx'> 		/* check that we're not already in D0 */</div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {</div><div class='ctx'> 			union display_idle_optimization_u idle_info = { 0 };</div><div class='hunk'>@@ -186,8 +228,6 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.</div><div class='ctx'> 	if (new_clocks-&gt;dppclk_khz &lt; MIN_DPP_DISP_CLK)</div><div class='ctx'> 		new_clocks-&gt;dppclk_khz = MIN_DPP_DISP_CLK;</div><div class='del'>-	if (new_clocks-&gt;dispclk_khz &lt; MIN_DPP_DISP_CLK)</div><div class='del'>-		new_clocks-&gt;dispclk_khz = MIN_DPP_DISP_CLK;</div><div class='ctx'> </div><div class='ctx'> 	if (should_set_clock(safe_to_lower, new_clocks-&gt;dppclk_khz, clk_mgr-&gt;base.clks.dppclk_khz)) {</div><div class='ctx'> 		if (clk_mgr-&gt;base.clks.dppclk_khz &gt; new_clocks-&gt;dppclk_khz)</div><div class='hunk'>@@ -196,15 +236,19 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		update_dppclk = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz)) {</div><div class='del'>-		/* No need to apply the w/a if we haven't taken over from bios yet */</div><div class='del'>-		if (clk_mgr_base-&gt;clks.dispclk_khz)</div><div class='del'>-			dcn315_disable_otg_wa(clk_mgr_base, context, true);</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz) &amp;&amp;</div><div class='add'>+	    (new_clocks-&gt;dispclk_khz &gt; 0 || (safe_to_lower &amp;&amp; display_count == 0))) {</div><div class='add'>+		int requested_dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='add'>+</div><div class='add'>+		dcn315_disable_otg_wa(clk_mgr_base, context, true);</div><div class='add'>+</div><div class='add'>+		/* Clamp the requested clock to PMFW based on their limit. */</div><div class='add'>+		if (dc-&gt;debug.min_disp_clk_khz &gt; 0 &amp;&amp; requested_dispclk_khz &lt; dc-&gt;debug.min_disp_clk_khz)</div><div class='add'>+			requested_dispclk_khz = dc-&gt;debug.min_disp_clk_khz;</div><div class='ctx'> </div><div class='add'>+		dcn315_smu_set_dispclk(clk_mgr, requested_dispclk_khz);</div><div class='ctx'> 		clk_mgr_base-&gt;clks.dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='del'>-		dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base-&gt;clks.dispclk_khz);</div><div class='del'>-		if (clk_mgr_base-&gt;clks.dispclk_khz)</div><div class='del'>-			dcn315_disable_otg_wa(clk_mgr_base, context, false);</div><div class='add'>+		dcn315_disable_otg_wa(clk_mgr_base, context, false);</div><div class='ctx'> </div><div class='ctx'> 		update_dispclk = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -235,9 +279,38 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dcn315_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	// read dtbclk</div><div class='add'>+	internal-&gt;CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+	// read dcfclk</div><div class='add'>+	internal-&gt;CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+	// read dppclk</div><div class='add'>+	internal-&gt;CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+	// read dprefclk</div><div class='add'>+	internal-&gt;CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+	// read dispclk</div><div class='add'>+	internal-&gt;CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='ctx'> 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)</div><div class='ctx'> {</div><div class='add'>+	struct dcn35_clk_internal internal = {0};</div><div class='add'>+</div><div class='add'>+	dcn315_dump_clk_registers_internal(&amp;internal, clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	regs_and_bypass-&gt;dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;</div><div class='ctx'> 	return;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -584,13 +657,32 @@ static struct clk_mgr_funcs dcn315_funcs = {</div><div class='ctx'> 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,</div><div class='ctx'> 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,</div><div class='ctx'> 	.update_clocks = dcn315_update_clocks,</div><div class='del'>-	.init_clocks = dcn31_init_clocks,</div><div class='add'>+	.init_clocks = dcn315_init_clocks,</div><div class='ctx'> 	.enable_pme_wa = dcn315_enable_pme_wa,</div><div class='ctx'> 	.are_clock_states_equal = dcn31_are_clock_states_equal,</div><div class='ctx'> 	.notify_wm_ranges = dcn315_notify_wm_ranges</div><div class='ctx'> };</div><div class='ctx'> extern struct clk_mgr_funcs dcn3_fpga_funcs;</div><div class='ctx'> </div><div class='add'>+void dcn315_init_clocks(struct clk_mgr *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);</div><div class='add'>+	uint32_t ref_dtbclk = clk_mgr-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+	struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr_int);</div><div class='add'>+	struct clk_log_info log_info = {0};</div><div class='add'>+</div><div class='add'>+	memset(&amp;(clk_mgr-&gt;clks), 0, sizeof(struct dc_clocks));</div><div class='add'>+	// Assumption is that boot state always supports pstate</div><div class='add'>+	clk_mgr-&gt;clks.ref_dtbclk_khz = ref_dtbclk;	// restore ref_dtbclk</div><div class='add'>+	clk_mgr-&gt;clks.p_state_change_support = true;</div><div class='add'>+	clk_mgr-&gt;clks.prev_p_state_change_support = true;</div><div class='add'>+	clk_mgr-&gt;clks.pwr_state = DCN_PWR_STATE_UNKNOWN;</div><div class='add'>+	clk_mgr-&gt;clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	dcn315_dump_clk_registers(&amp;clk_mgr-&gt;boot_snapshot, &amp;clk_mgr_dcn315-&gt;base.base, &amp;log_info);</div><div class='add'>+	clk_mgr-&gt;clks.dispclk_khz =  clk_mgr-&gt;boot_snapshot.dispclk * 1000;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn315_clk_mgr_construct(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct clk_mgr_dcn315 *clk_mgr,</div><div class='hunk'>@@ -651,6 +743,7 @@ void dcn315_clk_mgr_construct(</div><div class='ctx'> 	/* Saved clocks configured at boot for debug purposes */</div><div class='ctx'> 	dcn315_dump_clk_registers(&amp;clk_mgr-&gt;base.base.boot_snapshot,</div><div class='ctx'> 				  &amp;clk_mgr-&gt;base.base, &amp;log_info);</div><div class='add'>+	clk_mgr-&gt;base.base.clks.dispclk_khz =  clk_mgr-&gt;base.base.boot_snapshot.dispclk * 1000;</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;base.base.dprefclk_khz = 600000;</div><div class='ctx'> 	clk_mgr-&gt;base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&amp;clk_mgr-&gt;base);</div><div class='hunk'>@@ -704,7 +797,7 @@ void dcn315_clk_mgr_construct(</div><div class='ctx'> 					   i, smu_dpm_clks.dpm_clks-&gt;DfPstateTable[i].Voltage);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='ctx'> 			dcn315_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 					&amp;clk_mgr-&gt;base,</div><div class='ctx'> 					ctx-&gt;dc_bios-&gt;integrated_info,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h<br/>index ac36ddf5dd1a..642ae3d4a790 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h</a></div><div class='hunk'>@@ -44,6 +44,7 @@ void dcn315_clk_mgr_construct(struct dc_context *ctx,</div><div class='ctx'> 		struct pp_smu_funcs *pp_smu,</div><div class='ctx'> 		struct dccg *dccg);</div><div class='ctx'> </div><div class='add'>+void dcn315_init_clocks(struct clk_mgr *clk_mgr);</div><div class='ctx'> void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);</div><div class='ctx'> </div><div class='ctx'> #endif //__DCN315_CLK_MGR_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c<br/>index 879f1494c4cd..478b4d6a3544 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "dcn315_smu.h"</div><div class='ctx'> #include "mp/mp_13_0_5_offset.h"</div><div class='add'>+#include "logger_types.h"</div><div class='ctx'> </div><div class='ctx'> #define MAX_INSTANCE                                        6</div><div class='ctx'> #define MAX_SEGMENT                                         6</div><div class='hunk'>@@ -48,12 +49,9 @@ static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E0000</div><div class='ctx'> 					{ { 0, 0, 0, 0, 0, 0 } },</div><div class='ctx'> 					{ { 0, 0, 0, 0, 0, 0 } },</div><div class='ctx'> 					{ { 0, 0, 0, 0, 0, 0 } } } };</div><div class='del'>-static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },</div><div class='del'>-					{ { 0, 0, 0, 0, 0, 0 } },</div><div class='del'>-					{ { 0, 0, 0, 0, 0, 0 } },</div><div class='del'>-					{ { 0, 0, 0, 0, 0, 0 } },</div><div class='del'>-					{ { 0, 0, 0, 0, 0, 0 } },</div><div class='del'>-					{ { 0, 0, 0, 0, 0, 0 } } } };</div><div class='add'>+</div><div class='add'>+#define CTX clk_mgr-&gt;base.ctx</div><div class='add'>+#define IND_REG(offset)	offset</div><div class='ctx'> </div><div class='ctx'> #define regBIF_BX_PF2_RSMU_INDEX                                                                        0x0000</div><div class='ctx'> #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX                                                               1</div><div class='hunk'>@@ -66,10 +64,6 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D</div><div class='ctx'> #define FN(reg_name, field) \</div><div class='ctx'> 	FD(reg_name##__##field)</div><div class='ctx'> </div><div class='del'>-#define REG_NBIO(reg_name) \</div><div class='del'>-	(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)</div><div class='del'>-</div><div class='del'>-#include "logger_types.h"</div><div class='ctx'> #undef DC_LOGGER</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	CTX-&gt;logger</div><div class='hunk'>@@ -77,6 +71,13 @@ static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D</div><div class='ctx'> </div><div class='ctx'> #define mmMP1_C2PMSG_3                            0x3B1050C</div><div class='ctx'> </div><div class='add'>+#define reg__MP1_C2PMSG_3_MASK					(0xFFFFFFFF)</div><div class='add'>+#define reg__MP1_C2PMSG_3__SHIFT					(0)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define data_reg_name__MP1_C2PMSG_3_MASK		(0xFFFFFFFF)</div><div class='add'>+#define data_reg_name__MP1_C2PMSG_3__SHIFT		(0)</div><div class='add'>+</div><div class='ctx'> #define VBIOSSMC_MSG_TestMessage                  0x01 ///&lt; To check if PMFW is alive and responding. Requirement specified by PMFW team</div><div class='ctx'> #define VBIOSSMC_MSG_GetPmfwVersion               0x02 ///&lt; Get PMFW version</div><div class='ctx'> #define VBIOSSMC_MSG_Spare0                       0x03 ///&lt; Spare0</div><div class='hunk'>@@ -153,12 +154,10 @@ static int dcn315_smu_send_msg_with_param(</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; SMU_REGISTER_WRITE_RETRY_COUNT; i++) {</div><div class='ctx'> 		/* Trigger the message transaction by writing the message ID */</div><div class='del'>-		generic_write_indirect_reg(CTX,</div><div class='del'>-			REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),</div><div class='del'>-			mmMP1_C2PMSG_3, msg_id);</div><div class='del'>-		read_back_data = generic_read_indirect_reg(CTX,</div><div class='del'>-			REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),</div><div class='del'>-			mmMP1_C2PMSG_3);</div><div class='add'>+		IX_REG_SET_SYNC(mmMP1_C2PMSG_3, 0,</div><div class='add'>+			MP1_C2PMSG_3, msg_id);</div><div class='add'>+		IX_REG_GET_SYNC(mmMP1_C2PMSG_3,</div><div class='add'>+			MP1_C2PMSG_3, &amp;read_back_data);</div><div class='ctx'> 		if (read_back_data == msg_id)</div><div class='ctx'> 			break;</div><div class='ctx'> 		udelay(2);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c<br/>index 12f3e8aa46d8..1769b1f26e75 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c</a></div><div class='hunk'>@@ -39,7 +39,7 @@</div><div class='ctx'> #include "dcn316_smu.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> // DCN316 this is CLK1 instance</div><div class='ctx'> #define MAX_INSTANCE                                        7</div><div class='hunk'>@@ -99,20 +99,25 @@ static int dcn316_get_active_display_cnt_wa(</div><div class='ctx'> 	return display_count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)</div><div class='add'>+static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,</div><div class='add'>+		bool safe_to_lower, bool disable)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; ++i) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *pipe = safe_to_lower</div><div class='add'>+			? &amp;context-&gt;res_ctx.pipe_ctx[i]</div><div class='add'>+			: &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;top_pipe || pipe-&gt;prev_odm_pipe)</div><div class='ctx'> 			continue;</div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || pipe-&gt;plane_state == NULL ||</div><div class='del'>-				     dc_is_virtual_signal(pipe-&gt;stream-&gt;signal))) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal) ||</div><div class='add'>+				     !pipe-&gt;stream-&gt;link_enc)) {</div><div class='ctx'> 			if (disable) {</div><div class='del'>-				pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc(pipe-&gt;stream_res.tg);</div><div class='add'>+				if (pipe-&gt;stream_res.tg &amp;&amp; pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc)</div><div class='add'>+					pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc(pipe-&gt;stream_res.tg);</div><div class='add'>+</div><div class='ctx'> 				reset_sync_context_for_pipe(dc, context, i);</div><div class='ctx'> 			} else</div><div class='ctx'> 				pipe-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipe-&gt;stream_res.tg);</div><div class='hunk'>@@ -135,7 +140,7 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> 	struct dc_clocks *new_clocks = &amp;context-&gt;bw_ctx.bw.dcn.clk;</div><div class='ctx'> 	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='del'>-	int display_count;</div><div class='add'>+	int display_count = 0;</div><div class='ctx'> 	bool update_dppclk = false;</div><div class='ctx'> 	bool update_dispclk = false;</div><div class='ctx'> 	bool dpp_clock_lowered = false;</div><div class='hunk'>@@ -196,8 +201,6 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.</div><div class='ctx'> 	if (new_clocks-&gt;dppclk_khz &lt; 100000)</div><div class='ctx'> 		new_clocks-&gt;dppclk_khz = 100000;</div><div class='del'>-	if (new_clocks-&gt;dispclk_khz &lt; 100000)</div><div class='del'>-		new_clocks-&gt;dispclk_khz = 100000;</div><div class='ctx'> </div><div class='ctx'> 	if (should_set_clock(safe_to_lower, new_clocks-&gt;dppclk_khz, clk_mgr-&gt;base.clks.dppclk_khz)) {</div><div class='ctx'> 		if (clk_mgr-&gt;base.clks.dppclk_khz &gt; new_clocks-&gt;dppclk_khz)</div><div class='hunk'>@@ -206,12 +209,19 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		update_dppclk = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz)) {</div><div class='del'>-		dcn316_disable_otg_wa(clk_mgr_base, context, true);</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz) &amp;&amp;</div><div class='add'>+	    (new_clocks-&gt;dispclk_khz &gt; 0 || (safe_to_lower &amp;&amp; display_count == 0))) {</div><div class='add'>+		int requested_dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='add'>+</div><div class='add'>+		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);</div><div class='add'>+</div><div class='add'>+		/* Clamp the requested clock to PMFW based on their limit. */</div><div class='add'>+		if (dc-&gt;debug.min_disp_clk_khz &gt; 0 &amp;&amp; requested_dispclk_khz &lt; dc-&gt;debug.min_disp_clk_khz)</div><div class='add'>+			requested_dispclk_khz = dc-&gt;debug.min_disp_clk_khz;</div><div class='ctx'> </div><div class='add'>+		dcn316_smu_set_dispclk(clk_mgr, requested_dispclk_khz);</div><div class='ctx'> 		clk_mgr_base-&gt;clks.dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='del'>-		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base-&gt;clks.dispclk_khz);</div><div class='del'>-		dcn316_disable_otg_wa(clk_mgr_base, context, false);</div><div class='add'>+		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);</div><div class='ctx'> </div><div class='ctx'> 		update_dispclk = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -480,7 +490,8 @@ static void dcn316_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> </div><div class='ctx'> 	j = -1;</div><div class='ctx'> </div><div class='del'>-	ASSERT(NUM_DF_PSTATE_LEVELS &lt;= MAX_NUM_DPM_LVL);</div><div class='add'>+	static_assert(NUM_DF_PSTATE_LEVELS &lt;= MAX_NUM_DPM_LVL,</div><div class='add'>+		"number of reported pstate levels exceeds maximum");</div><div class='ctx'> </div><div class='ctx'> 	/* Find lowest DPM, FCLK is filled in reverse order*/</div><div class='ctx'> </div><div class='hunk'>@@ -646,7 +657,7 @@ void dcn316_clk_mgr_construct(</div><div class='ctx'> 	if (clk_mgr-&gt;base.base.ctx-&gt;dc-&gt;debug.pstate_enabled) {</div><div class='ctx'> 		dcn316_get_dpm_table_from_smu(&amp;clk_mgr-&gt;base, &amp;smu_dpm_clks);</div><div class='ctx'> </div><div class='del'>-		if (ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;integrated_info) {</div><div class='ctx'> 			dcn316_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 					&amp;clk_mgr-&gt;base,</div><div class='ctx'> 					ctx-&gt;dc_bios-&gt;integrated_info,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c<br/>index bec252e1dd27..7da7b41bd092 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c</a></div><div class='hunk'>@@ -29,18 +29,18 @@</div><div class='ctx'> #include "dcn20/dcn20_clk_mgr.h"</div><div class='ctx'> #include "dce100/dce_clk_mgr.h"</div><div class='ctx'> #include "dcn31/dcn31_clk_mgr.h"</div><div class='add'>+#include "dcn32/dcn32_clk_mgr.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> #include "atomfirmware.h"</div><div class='del'>-#include "smu13_driver_if.h"</div><div class='add'>+#include "dcn32_smu13_driver_if.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn/dcn_3_2_0_offset.h"</div><div class='ctx'> #include "dcn/dcn_3_2_0_sh_mask.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn32/dcn32_clk_mgr.h"</div><div class='ctx'> #include "dml/dcn32/dcn32_fpu.h"</div><div class='ctx'> </div><div class='ctx'> #define DCN_BASE__INST0_SEG1                       0x000000C0</div><div class='hunk'>@@ -163,9 +163,14 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> 	unsigned int num_levels;</div><div class='del'>-	struct clk_limit_num_entries *num_entries_per_clk = &amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk;</div><div class='add'>+	struct clk_limit_num_entries *num_entries_per_clk;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='add'>+	if (!clk_mgr_base-&gt;bw_params)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_entries_per_clk = &amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk;</div><div class='add'>+</div><div class='ctx'> 	memset(&amp;(clk_mgr_base-&gt;clks), 0, sizeof(struct dc_clocks));</div><div class='ctx'> 	clk_mgr_base-&gt;clks.p_state_change_support = true;</div><div class='ctx'> 	clk_mgr_base-&gt;clks.prev_p_state_change_support = true;</div><div class='hunk'>@@ -173,9 +178,6 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 	clk_mgr-&gt;smu_present = false;</div><div class='ctx'> 	clk_mgr-&gt;dpm_present = false;</div><div class='ctx'> </div><div class='del'>-	if (!clk_mgr_base-&gt;bw_params)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	if (!clk_mgr_base-&gt;force_smu_not_present &amp;&amp; dcn30_smu_get_smu_version(clk_mgr, &amp;clk_mgr-&gt;smu_ver))</div><div class='ctx'> 		clk_mgr-&gt;smu_present = true;</div><div class='ctx'> </div><div class='hunk'>@@ -553,7 +555,7 @@ static void dcn32_auto_dpm_test_log(</div><div class='ctx'> 	//</div><div class='ctx'> 	//				AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"</div><div class='ctx'> 	////////////////////////////////////////////////////////////////////////////</div><div class='del'>-	if (new_clocks &amp;&amp; active_pipe_count &gt; 0 &amp;&amp;</div><div class='add'>+	if (active_pipe_count &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;dramclk_khz &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;fclk_khz &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;dcfclk_khz &gt; 0 &amp;&amp;</div><div class='hunk'>@@ -574,7 +576,7 @@ static void dcn32_auto_dpm_test_log(</div><div class='ctx'> 			p_state_list[i] = curr_pipe_ctx-&gt;p_state_type;</div><div class='ctx'> </div><div class='ctx'> 			refresh_rate = (curr_pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='del'>-				curr_pipe_ctx-&gt;stream-&gt;timing.v_total * curr_pipe_ctx-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+				curr_pipe_ctx-&gt;stream-&gt;timing.v_total * (uint64_t)curr_pipe_ctx-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> 			disp_src_refresh_list[i] = refresh_rate;</div><div class='hunk'>@@ -712,8 +714,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 					 * since we calculate mode support based on softmax being the max UCLK</div><div class='ctx'> 					 * frequency.</div><div class='ctx'> 					 */</div><div class='del'>-					dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,</div><div class='del'>-							dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk);</div><div class='add'>+					if (dc-&gt;debug.disable_dc_mode_overwrite) {</div><div class='add'>+						dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc-&gt;clk_mgr-&gt;bw_params-&gt;max_memclk_mhz);</div><div class='add'>+						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc-&gt;clk_mgr-&gt;bw_params-&gt;max_memclk_mhz);</div><div class='add'>+					} else</div><div class='add'>+						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,</div><div class='add'>+								dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk);</div><div class='ctx'> 				} else {</div><div class='ctx'> 					dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc-&gt;clk_mgr-&gt;bw_params-&gt;max_memclk_mhz);</div><div class='ctx'> 				}</div><div class='hunk'>@@ -746,8 +752,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */</div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.p_state_change_support &amp;&amp;</div><div class='ctx'> 				(update_uclk || !clk_mgr_base-&gt;clks.prev_p_state_change_support) &amp;&amp;</div><div class='del'>-				!dc-&gt;work_arounds.clock_update_disable_mask.uclk)</div><div class='add'>+				!dc-&gt;work_arounds.clock_update_disable_mask.uclk) {</div><div class='add'>+			if (dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled &amp;&amp; dc-&gt;debug.disable_dc_mode_overwrite)</div><div class='add'>+				dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,</div><div class='add'>+						max((int)dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base-&gt;clks.dramclk_khz)));</div><div class='add'>+</div><div class='ctx'> 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base-&gt;clks.dramclk_khz));</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.num_ways != new_clocks-&gt;num_ways &amp;&amp;</div><div class='ctx'> 				clk_mgr_base-&gt;clks.num_ways &gt; new_clocks-&gt;num_ways) {</div><div class='hunk'>@@ -829,7 +840,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		dmcu-&gt;funcs-&gt;set_psr_wait_loop(dmcu,</div><div class='ctx'> 				clk_mgr_base-&gt;clks.dispclk_khz / 1000 / 7);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;config.enable_auto_dpm_test_logs &amp;&amp; safe_to_lower) {</div><div class='add'>+	if (dc-&gt;config.enable_auto_dpm_test_logs) {</div><div class='ctx'> 	    dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1036,11 +1047,8 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 			&amp;num_entries_per_clk-&gt;num_fclk_levels);</div><div class='ctx'> 	clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);</div><div class='ctx'> </div><div class='del'>-	if (num_entries_per_clk-&gt;num_memclk_levels &gt;= num_entries_per_clk-&gt;num_fclk_levels) {</div><div class='del'>-		num_levels = num_entries_per_clk-&gt;num_memclk_levels;</div><div class='del'>-	} else {</div><div class='del'>-		num_levels = num_entries_per_clk-&gt;num_fclk_levels;</div><div class='del'>-	}</div><div class='add'>+	num_levels = max(num_entries_per_clk-&gt;num_memclk_levels, num_entries_per_clk-&gt;num_fclk_levels);</div><div class='add'>+</div><div class='ctx'> 	clk_mgr_base-&gt;bw_params-&gt;max_memclk_mhz =</div><div class='ctx'> 			clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_memclk_levels - 1].memclk_mhz;</div><div class='ctx'> 	clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries = num_levels ? num_levels : 1;</div><div class='hunk'>@@ -1199,11 +1207,19 @@ void dcn32_clk_mgr_construct(</div><div class='ctx'> 	clk_mgr-&gt;smu_present = false;</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;base.bw_params = kzalloc(sizeof(*clk_mgr-&gt;base.bw_params), GFP_KERNEL);</div><div class='add'>+	if (!clk_mgr-&gt;base.bw_params) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* need physical address of table to give to PMFW */</div><div class='ctx'> 	clk_mgr-&gt;wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr-&gt;base.ctx,</div><div class='ctx'> 			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),</div><div class='ctx'> 			&amp;clk_mgr-&gt;wm_range_table_addr);</div><div class='add'>+	if (!clk_mgr-&gt;wm_range_table) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c<br/>index df244b175fdb..5d80fdf63ffc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "dalsmc.h"</div><div class='del'>-#include "smu13_driver_if.h"</div><div class='add'>+#include "dcn32_smu13_driver_if.h"</div><div class='ctx'> </div><div class='ctx'> #define mmDAL_MSG_REG  0x1628A</div><div class='ctx'> #define mmDAL_ARG_REG  0x16273</div><div class='hunk'>@@ -49,6 +49,7 @@</div><div class='ctx'>  */</div><div class='ctx'> static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)</div><div class='ctx'> {</div><div class='add'>+	const uint32_t initial_max_retries = max_retries;</div><div class='ctx'> 	uint32_t reg = 0;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='hunk'>@@ -62,6 +63,9 @@ static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un</div><div class='ctx'> 			udelay(delay_us);</div><div class='ctx'> 	} while (max_retries--);</div><div class='ctx'> </div><div class='add'>+	TRACE_SMU_MSG_DELAY(0, 0, delay_us * (initial_max_retries - max_retries), clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> 	return reg;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -79,6 +83,8 @@ static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint</div><div class='ctx'> 	/* Trigger the message transaction by writing the message ID */</div><div class='ctx'> 	REG_WRITE(DAL_MSG_REG, msg_id);</div><div class='ctx'> </div><div class='add'>+	TRACE_SMU_MSG(msg_id, param_in, clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='ctx'> 	/* Wait for response */</div><div class='ctx'> 	if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {</div><div class='ctx'> 		if (param_out)</div><div class='hunk'>@@ -115,6 +121,8 @@ static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_m</div><div class='ctx'> 		*total_delay_us += delay_us;</div><div class='ctx'> 	} while (max_retries--);</div><div class='ctx'> </div><div class='add'>+	TRACE_SMU_MSG_DELAY(0, 0, *total_delay_us, clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='ctx'> 	return reg;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -135,6 +143,8 @@ static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr</div><div class='ctx'> 	/* Trigger the message transaction by writing the message ID */</div><div class='ctx'> 	REG_WRITE(DAL_MSG_REG, msg_id);</div><div class='ctx'> </div><div class='add'>+	TRACE_SMU_MSG(msg_id, param_in, clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='ctx'> 	/* Wait for response */</div><div class='ctx'> 	if (dcn32_smu_wait_for_response_delay(clk_mgr, 10, 200000, &amp;delay2_us) == DALSMC_Result_OK) {</div><div class='ctx'> 		if (param_out)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h<br/>index c76352a817de..5c44ab0e8667 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h</a></div><div class='hunk'>@@ -37,10 +37,9 @@</div><div class='ctx'> #define DALSMC_Result_OK				0x1</div><div class='ctx'> </div><div class='ctx'> void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);</div><div class='del'>-void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);</div><div class='del'>-void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);</div><div class='ctx'> void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);</div><div class='ctx'> void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h<br/>index d3d5a8caccf8..8d54865bbd5d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_smu13_driver_if.h</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> // SPDX-License-Identifier: MIT</div><div class='del'>-// This is a stripped-down version of the smu13_driver_if.h file for the relevant DAL interfaces.</div><div class='add'>+/* Copyright © 2022-2024 Advanced Micro Devices, Inc. All rights reserved. */</div><div class='ctx'> </div><div class='ctx'> #define SMU13_DRIVER_IF_VERSION  0x18</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h<br/>deleted file mode 100644<br/>index deeb85047e7b..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,108 +0,0 @@</div><div class='del'>-/*</div><div class='del'>- * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- * Authors: AMD</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-#ifndef SMU13_DRIVER_IF_DCN32_H</div><div class='del'>-#define SMU13_DRIVER_IF_DCN32_H</div><div class='del'>-</div><div class='del'>-// *** IMPORTANT ***</div><div class='del'>-// PMFW TEAM: Always increment the interface version on any change to this file</div><div class='del'>-#define SMU13_DRIVER_IF_VERSION  0x18</div><div class='del'>-</div><div class='del'>-//Only Clks that have DPM descriptors are listed here</div><div class='del'>-typedef enum {</div><div class='del'>-  PPCLK_GFXCLK = 0,</div><div class='del'>-  PPCLK_SOCCLK,</div><div class='del'>-  PPCLK_UCLK,</div><div class='del'>-  PPCLK_FCLK,</div><div class='del'>-  PPCLK_DCLK_0,</div><div class='del'>-  PPCLK_VCLK_0,</div><div class='del'>-  PPCLK_DCLK_1,</div><div class='del'>-  PPCLK_VCLK_1,</div><div class='del'>-  PPCLK_DISPCLK,</div><div class='del'>-  PPCLK_DPPCLK,</div><div class='del'>-  PPCLK_DPREFCLK,</div><div class='del'>-  PPCLK_DCFCLK,</div><div class='del'>-  PPCLK_DTBCLK,</div><div class='del'>-  PPCLK_COUNT,</div><div class='del'>-} PPCLK_e;</div><div class='del'>-</div><div class='del'>-typedef enum {</div><div class='del'>-  UCLK_DIV_BY_1 = 0,</div><div class='del'>-  UCLK_DIV_BY_2,</div><div class='del'>-  UCLK_DIV_BY_4,</div><div class='del'>-  UCLK_DIV_BY_8,</div><div class='del'>-} UCLK_DIV_e;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-  uint8_t  WmSetting;</div><div class='del'>-  uint8_t  Flags;</div><div class='del'>-  uint8_t  Padding[2];</div><div class='del'>-</div><div class='del'>-} WatermarkRowGeneric_t;</div><div class='del'>-</div><div class='del'>-#define NUM_WM_RANGES 4</div><div class='del'>-</div><div class='del'>-typedef enum {</div><div class='del'>-  WATERMARKS_CLOCK_RANGE = 0,</div><div class='del'>-  WATERMARKS_DUMMY_PSTATE,</div><div class='del'>-  WATERMARKS_MALL,</div><div class='del'>-  WATERMARKS_COUNT,</div><div class='del'>-} WATERMARKS_FLAGS_e;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-  // Watermarks</div><div class='del'>-  WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];</div><div class='del'>-} Watermarks_t;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-  Watermarks_t Watermarks;</div><div class='del'>-  uint32_t  Spare[16];</div><div class='del'>-</div><div class='del'>-  uint32_t     MmHubPadding[8]; // SMU internal use</div><div class='del'>-} WatermarksExternal_t;</div><div class='del'>-</div><div class='del'>-// These defines are used with the following messages:</div><div class='del'>-// SMC_MSG_TransferTableDram2Smu</div><div class='del'>-// SMC_MSG_TransferTableSmu2Dram</div><div class='del'>-</div><div class='del'>-// Table transfer status</div><div class='del'>-#define TABLE_TRANSFER_OK         0x0</div><div class='del'>-#define TABLE_TRANSFER_FAILED     0xFF</div><div class='del'>-#define TABLE_TRANSFER_PENDING    0xAB</div><div class='del'>-</div><div class='del'>-// Table types</div><div class='del'>-#define TABLE_PMFW_PPTABLE            0</div><div class='del'>-#define TABLE_COMBO_PPTABLE           1</div><div class='del'>-#define TABLE_WATERMARKS              2</div><div class='del'>-#define TABLE_AVFS_PSM_DEBUG          3</div><div class='del'>-#define TABLE_PMSTATUSLOG             4</div><div class='del'>-#define TABLE_SMU_METRICS             5</div><div class='del'>-#define TABLE_DRIVER_SMU_CONFIG       6</div><div class='del'>-#define TABLE_ACTIVITY_MONITOR_COEFF  7</div><div class='del'>-#define TABLE_OVERDRIVE               8</div><div class='del'>-#define TABLE_I2C_COMMANDS            9</div><div class='del'>-#define TABLE_DRIVER_INFO             10</div><div class='del'>-#define TABLE_COUNT                   11</div><div class='del'>-</div><div class='del'>-#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c<br/>new file mode 100644<br/>index 000000000000..4607eff07253<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c</a></div><div class='hunk'>@@ -0,0 +1,141 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dcn35_clk_mgr.h"</div><div class='add'>+</div><div class='add'>+#define DCN_BASE__INST0_SEG1 0x000000C0</div><div class='add'>+#define mmCLK1_CLK_PLL_REQ 0x16E37</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_DFS_CNTL 0x16E69</div><div class='add'>+#define mmCLK1_CLK1_DFS_CNTL 0x16E6C</div><div class='add'>+#define mmCLK1_CLK2_DFS_CNTL 0x16E6F</div><div class='add'>+#define mmCLK1_CLK3_DFS_CNTL 0x16E72</div><div class='add'>+#define mmCLK1_CLK4_DFS_CNTL 0x16E75</div><div class='add'>+#define mmCLK1_CLK5_DFS_CNTL 0x16E78</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_CURRENT_CNT 0x16EFC</div><div class='add'>+#define mmCLK1_CLK1_CURRENT_CNT 0x16EFD</div><div class='add'>+#define mmCLK1_CLK2_CURRENT_CNT 0x16EFE</div><div class='add'>+#define mmCLK1_CLK3_CURRENT_CNT 0x16EFF</div><div class='add'>+#define mmCLK1_CLK4_CURRENT_CNT 0x16F00</div><div class='add'>+#define mmCLK1_CLK5_CURRENT_CNT 0x16F01</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A</div><div class='add'>+#define mmCLK1_CLK1_BYPASS_CNTL 0x16E93</div><div class='add'>+#define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C</div><div class='add'>+#define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5</div><div class='add'>+#define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE</div><div class='add'>+#define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_DS_CNTL 0x16E83</div><div class='add'>+#define mmCLK1_CLK1_DS_CNTL 0x16E8C</div><div class='add'>+#define mmCLK1_CLK2_DS_CNTL 0x16E95</div><div class='add'>+#define mmCLK1_CLK3_DS_CNTL 0x16E9E</div><div class='add'>+#define mmCLK1_CLK4_DS_CNTL 0x16EA7</div><div class='add'>+#define mmCLK1_CLK5_DS_CNTL 0x16EB0</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_ALLOW_DS 0x16E84</div><div class='add'>+#define mmCLK1_CLK1_ALLOW_DS 0x16E8D</div><div class='add'>+#define mmCLK1_CLK2_ALLOW_DS 0x16E96</div><div class='add'>+#define mmCLK1_CLK3_ALLOW_DS 0x16E9F</div><div class='add'>+#define mmCLK1_CLK4_ALLOW_DS 0x16EA8</div><div class='add'>+#define mmCLK1_CLK5_ALLOW_DS 0x16EB1</div><div class='add'>+</div><div class='add'>+#define mmCLK5_spll_field_8 0x1B04B</div><div class='add'>+#define mmCLK6_spll_field_8 0x1B24B</div><div class='add'>+#define mmDENTIST_DISPCLK_CNTL 0x0124</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL 0x0064</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1</div><div class='add'>+</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0</div><div class='add'>+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL</div><div class='add'>+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L</div><div class='add'>+</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L</div><div class='add'>+</div><div class='add'>+// DENTIST_DISPCLK_CNTL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L</div><div class='add'>+</div><div class='add'>+#define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L</div><div class='add'>+</div><div class='add'>+#define REG(reg) \</div><div class='add'>+	(clk_mgr-&gt;regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SR(reg_name)\</div><div class='add'>+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \</div><div class='add'>+					reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define CLK_SR_DCN35(reg_name)\</div><div class='add'>+	.reg_name = mm ## reg_name</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_registers clk_mgr_regs_dcn351 = {</div><div class='add'>+	CLK_REG_LIST_DCN35()</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_shift clk_mgr_shift_dcn351 = {</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_mask clk_mgr_mask_dcn351 = {</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define TO_CLK_MGR_DCN35(clk_mgr)\</div><div class='add'>+	container_of(clk_mgr, struct clk_mgr_dcn35, base)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dcn351_clk_mgr_construct(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		struct clk_mgr_dcn35 *clk_mgr,</div><div class='add'>+		struct pp_smu_funcs *pp_smu,</div><div class='add'>+		struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	/*register offset changed*/</div><div class='add'>+	clk_mgr-&gt;base.regs = &amp;clk_mgr_regs_dcn351;</div><div class='add'>+	clk_mgr-&gt;base.clk_mgr_shift = &amp;clk_mgr_shift_dcn351;</div><div class='add'>+	clk_mgr-&gt;base.clk_mgr_mask = &amp;clk_mgr_mask_dcn351;</div><div class='add'>+</div><div class='add'>+	dcn35_clk_mgr_construct(ctx,  clk_mgr, pp_smu, dccg);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c<br/>index c378b879c76d..dfd0c9505af0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c</a></div><div class='hunk'>@@ -36,45 +36,119 @@</div><div class='ctx'> #include "dcn20/dcn20_clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dcn35_smu.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> </div><div class='del'>-/* TODO: remove this include once we ported over remaining clk mgr functions*/</div><div class='del'>-#include "dcn30/dcn30_clk_mgr.h"</div><div class='ctx'> #include "dcn31/dcn31_clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "logger_types.h"</div><div class='ctx'> </div><div class='ctx'> #undef DC_LOGGER</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	clk_mgr-&gt;base.base.ctx-&gt;logger</div><div class='ctx'> </div><div class='del'>-#define regCLK1_CLK_PLL_REQ			0x0237</div><div class='del'>-#define regCLK1_CLK_PLL_REQ_BASE_IDX		0</div><div class='del'>-</div><div class='del'>-#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT	0x0</div><div class='del'>-#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT	0xc</div><div class='del'>-#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT	0x10</div><div class='del'>-#define CLK1_CLK_PLL_REQ__FbMult_int_MASK	0x000001FFL</div><div class='del'>-#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK	0x0000F000L</div><div class='del'>-#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK	0xFFFF0000L</div><div class='del'>-</div><div class='del'>-#define regCLK1_CLK2_BYPASS_CNTL			0x029c</div><div class='del'>-#define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+#define DCN_BASE__INST0_SEG1 0x000000C0</div><div class='add'>+#define mmCLK1_CLK_PLL_REQ 0x16E37</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_DFS_CNTL 0x16E69</div><div class='add'>+#define mmCLK1_CLK1_DFS_CNTL 0x16E6C</div><div class='add'>+#define mmCLK1_CLK2_DFS_CNTL 0x16E6F</div><div class='add'>+#define mmCLK1_CLK3_DFS_CNTL 0x16E72</div><div class='add'>+#define mmCLK1_CLK4_DFS_CNTL 0x16E75</div><div class='add'>+#define mmCLK1_CLK5_DFS_CNTL 0x16E78</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_CURRENT_CNT 0x16EFB</div><div class='add'>+#define mmCLK1_CLK1_CURRENT_CNT 0x16EFC</div><div class='add'>+#define mmCLK1_CLK2_CURRENT_CNT 0x16EFD</div><div class='add'>+#define mmCLK1_CLK3_CURRENT_CNT 0x16EFE</div><div class='add'>+#define mmCLK1_CLK4_CURRENT_CNT 0x16EFF</div><div class='add'>+#define mmCLK1_CLK5_CURRENT_CNT 0x16F00</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A</div><div class='add'>+#define mmCLK1_CLK1_BYPASS_CNTL 0x16E93</div><div class='add'>+#define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C</div><div class='add'>+#define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5</div><div class='add'>+#define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE</div><div class='add'>+#define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_DS_CNTL 0x16E83</div><div class='add'>+#define mmCLK1_CLK1_DS_CNTL 0x16E8C</div><div class='add'>+#define mmCLK1_CLK2_DS_CNTL 0x16E95</div><div class='add'>+#define mmCLK1_CLK3_DS_CNTL 0x16E9E</div><div class='add'>+#define mmCLK1_CLK4_DS_CNTL 0x16EA7</div><div class='add'>+#define mmCLK1_CLK5_DS_CNTL 0x16EB0</div><div class='add'>+</div><div class='add'>+#define mmCLK1_CLK0_ALLOW_DS 0x16E84</div><div class='add'>+#define mmCLK1_CLK1_ALLOW_DS 0x16E8D</div><div class='add'>+#define mmCLK1_CLK2_ALLOW_DS 0x16E96</div><div class='add'>+#define mmCLK1_CLK3_ALLOW_DS 0x16E9F</div><div class='add'>+#define mmCLK1_CLK4_ALLOW_DS 0x16EA8</div><div class='add'>+#define mmCLK1_CLK5_ALLOW_DS 0x16EB1</div><div class='add'>+</div><div class='add'>+#define mmCLK5_spll_field_8 0x1B24B</div><div class='add'>+#define mmCLK6_spll_field_8 0x1B24B</div><div class='add'>+#define mmDENTIST_DISPCLK_CNTL 0x0124</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL 0x0064</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1</div><div class='add'>+</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0</div><div class='add'>+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL</div><div class='add'>+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L</div><div class='add'>+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L</div><div class='add'>+</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L</div><div class='add'>+// DENTIST_DISPCLK_CNTL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L</div><div class='add'>+</div><div class='add'>+#define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L</div><div class='add'>+#define CLK6_spll_field_8__spll_ssc_en_MASK 0x00002000L</div><div class='add'>+</div><div class='add'>+#define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	clk_mgr-&gt;clk_mgr_shift-&gt;field_name, clk_mgr-&gt;clk_mgr_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+#define REG(reg) \</div><div class='add'>+	(clk_mgr-&gt;regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SR(reg_name)\</div><div class='add'>+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \</div><div class='add'>+					reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define CLK_SR_DCN35(reg_name)\</div><div class='add'>+	.reg_name = mm ## reg_name</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_registers clk_mgr_regs_dcn35 = {</div><div class='add'>+	CLK_REG_LIST_DCN35()</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT	0x0</div><div class='del'>-#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT	0x10</div><div class='del'>-#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK		0x00000007L</div><div class='del'>-#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK		0x000F0000L</div><div class='add'>+static const struct clk_mgr_shift clk_mgr_shift_dcn35 = {</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-#define REG(reg_name) \</div><div class='del'>-	(ctx-&gt;clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)</div><div class='add'>+static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> #define TO_CLK_MGR_DCN35(clk_mgr)\</div><div class='ctx'> 	container_of(clk_mgr, struct clk_mgr_dcn35, base)</div><div class='hunk'>@@ -112,22 +186,59 @@ static int dcn35_get_active_display_cnt_wa(</div><div class='ctx'> </div><div class='ctx'> 	return display_count;</div><div class='ctx'> }</div><div class='del'>-</div><div class='ctx'> static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,</div><div class='ctx'> 		bool safe_to_lower, bool disable)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_DIAG)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; ++i) {</div><div class='add'>+		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+		struct dccg *dccg = clk_mgr_internal-&gt;dccg;</div><div class='ctx'> 		struct pipe_ctx *pipe = safe_to_lower</div><div class='ctx'> 			? &amp;context-&gt;res_ctx.pipe_ctx[i]</div><div class='ctx'> 			: &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct link_encoder *new_pipe_link_enc = new_pipe-&gt;link_res.dio_link_enc;</div><div class='add'>+		struct link_encoder *pipe_link_enc = pipe-&gt;link_res.dio_link_enc;</div><div class='add'>+		bool stream_changed_otg_dig_on = false;</div><div class='add'>+		bool has_active_hpo = false;</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;top_pipe || pipe-&gt;prev_odm_pipe)</div><div class='ctx'> 			continue;</div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal) ||</div><div class='del'>-				     !pipe-&gt;stream-&gt;link_enc)) {</div><div class='add'>+</div><div class='add'>+		if (!dc-&gt;config.unify_link_enc_assignment) {</div><div class='add'>+			if (new_pipe-&gt;stream)</div><div class='add'>+				new_pipe_link_enc = new_pipe-&gt;stream-&gt;link_enc;</div><div class='add'>+			if (pipe-&gt;stream)</div><div class='add'>+				pipe_link_enc = pipe-&gt;stream-&gt;link_enc;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		stream_changed_otg_dig_on = old_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream &amp;&amp;</div><div class='add'>+		old_pipe-&gt;stream != new_pipe-&gt;stream &amp;&amp;</div><div class='add'>+		old_pipe-&gt;stream_res.tg == new_pipe-&gt;stream_res.tg &amp;&amp;</div><div class='add'>+		new_pipe_link_enc &amp;&amp; !new_pipe-&gt;stream-&gt;dpms_off &amp;&amp;</div><div class='add'>+		new_pipe_link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='add'>+		new_pipe_link_enc-&gt;funcs-&gt;is_dig_enabled(</div><div class='add'>+		new_pipe_link_enc) &amp;&amp;</div><div class='add'>+		new_pipe-&gt;stream_res.stream_enc &amp;&amp;</div><div class='add'>+		new_pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;is_fifo_enabled &amp;&amp;</div><div class='add'>+		new_pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;is_fifo_enabled(new_pipe-&gt;stream_res.stream_enc);</div><div class='add'>+</div><div class='add'>+		if (old_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream &amp;&amp; old_pipe-&gt;stream == new_pipe-&gt;stream) {</div><div class='add'>+			has_active_hpo =  dccg-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(old_pipe) &amp;&amp;</div><div class='add'>+			dccg-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(new_pipe);</div><div class='add'>+</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!has_active_hpo &amp;&amp; !stream_changed_otg_dig_on &amp;&amp; pipe-&gt;stream &amp;&amp;</div><div class='add'>+		    (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal) || !pipe_link_enc) &amp;&amp;</div><div class='add'>+		    !dccg-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe)) {</div><div class='add'>+			/* This w/a should not trigger when we have a dig active */</div><div class='ctx'> 			if (disable) {</div><div class='ctx'> 				if (pipe-&gt;stream_res.tg &amp;&amp; pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc)</div><div class='ctx'> 					pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc(pipe-&gt;stream_res.tg);</div><div class='hunk'>@@ -210,6 +321,59 @@ static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,</div><div class='ctx'> 		}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint8_t get_lowest_dpia_index(const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	const struct dc *dc_struct = link-&gt;dc;</div><div class='add'>+	uint8_t idx = 0xFF;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES * 2; ++i) {</div><div class='add'>+		if (!dc_struct-&gt;links[i] || dc_struct-&gt;links[i]-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (idx &gt; dc_struct-&gt;links[i]-&gt;link_index)</div><div class='add'>+			idx = dc_struct-&gt;links[i]-&gt;link_index;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,</div><div class='add'>+					bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dc_clocks *new_clocks = &amp;context-&gt;bw_ctx.bw.dcn.clk;</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };</div><div class='add'>+	int i;</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; ++i) {</div><div class='add'>+		const struct dc_stream_state *stream = context-&gt;streams[i];</div><div class='add'>+		const struct dc_link *link = stream-&gt;link;</div><div class='add'>+		uint8_t lowest_dpia_index = 0;</div><div class='add'>+		unsigned int hr_index = 0;</div><div class='add'>+</div><div class='add'>+		if (!link)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		lowest_dpia_index = get_lowest_dpia_index(link);</div><div class='add'>+		if (link-&gt;link_index &lt; lowest_dpia_index)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		hr_index = (link-&gt;link_index - lowest_dpia_index) / 2;</div><div class='add'>+		if (hr_index &gt;= MAX_HOST_ROUTERS_NUM)</div><div class='add'>+			continue;</div><div class='add'>+		host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(</div><div class='add'>+			&amp;stream-&gt;timing, dc_link_get_highest_encoding_format(link));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_HOST_ROUTERS_NUM; ++i) {</div><div class='add'>+		new_clocks-&gt;host_router_bw_kbps[i] = host_router_bw_kbps[i];</div><div class='add'>+		if (should_set_clock(safe_to_lower, new_clocks-&gt;host_router_bw_kbps[i], clk_mgr_base-&gt;clks.host_router_bw_kbps[i])) {</div><div class='add'>+			clk_mgr_base-&gt;clks.host_router_bw_kbps[i] = new_clocks-&gt;host_router_bw_kbps[i];</div><div class='add'>+			dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks-&gt;host_router_bw_kbps[i]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 			struct dc_state *context,</div><div class='ctx'> 			bool safe_to_lower)</div><div class='hunk'>@@ -230,6 +394,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	display_count = dcn35_get_active_display_cnt_wa(dc, context, &amp;all_active_disps);</div><div class='ctx'> 	if (new_clocks-&gt;dtbclk_en &amp;&amp; !new_clocks-&gt;ref_dtbclk_khz)</div><div class='ctx'> 		new_clocks-&gt;ref_dtbclk_khz = 600000;</div><div class='add'>+	else if (!new_clocks-&gt;dtbclk_en &amp;&amp; new_clocks-&gt;ref_dtbclk_khz &gt; 590000)</div><div class='add'>+		new_clocks-&gt;ref_dtbclk_khz = 0;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything</div><div class='hunk'>@@ -244,7 +410,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.dtbclk_en &amp;&amp; !new_clocks-&gt;dtbclk_en) {</div><div class='del'>-			dcn35_smu_set_dtbclk(clk_mgr, false);</div><div class='add'>+			if (clk_mgr-&gt;base.ctx-&gt;dc-&gt;config.allow_0_dtb_clk)</div><div class='add'>+				dcn35_smu_set_dtbclk(clk_mgr, false);</div><div class='add'>+</div><div class='ctx'> 			clk_mgr_base-&gt;clks.dtbclk_en = new_clocks-&gt;dtbclk_en;</div><div class='ctx'> 		}</div><div class='ctx'> 		/* check that we're not already in lower */</div><div class='hunk'>@@ -262,11 +430,17 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (!clk_mgr_base-&gt;clks.dtbclk_en &amp;&amp; new_clocks-&gt;dtbclk_en) {</div><div class='del'>-			dcn35_smu_set_dtbclk(clk_mgr, true);</div><div class='del'>-			clk_mgr_base-&gt;clks.dtbclk_en = new_clocks-&gt;dtbclk_en;</div><div class='add'>+			int actual_dtbclk = 0;</div><div class='ctx'> </div><div class='ctx'> 			dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks-&gt;ref_dtbclk_khz);</div><div class='del'>-			clk_mgr_base-&gt;clks.ref_dtbclk_khz = new_clocks-&gt;ref_dtbclk_khz;</div><div class='add'>+			dcn35_smu_set_dtbclk(clk_mgr, true);</div><div class='add'>+</div><div class='add'>+			actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+			if (actual_dtbclk &gt; 590000) {</div><div class='add'>+				clk_mgr_base-&gt;clks.ref_dtbclk_khz = new_clocks-&gt;ref_dtbclk_khz;</div><div class='add'>+				clk_mgr_base-&gt;clks.dtbclk_en = new_clocks-&gt;dtbclk_en;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* check that we're not already in D0 */</div><div class='hunk'>@@ -304,11 +478,19 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		update_dppclk = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz)) {</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz) &amp;&amp;</div><div class='add'>+	    (new_clocks-&gt;dispclk_khz &gt; 0 || (safe_to_lower &amp;&amp; display_count == 0))) {</div><div class='add'>+		int requested_dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='add'>+</div><div class='ctx'> 		dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);</div><div class='ctx'> </div><div class='add'>+		/* Clamp the requested clock to PMFW based on their limit. */</div><div class='add'>+		if (dc-&gt;debug.min_disp_clk_khz &gt; 0 &amp;&amp; requested_dispclk_khz &lt; dc-&gt;debug.min_disp_clk_khz)</div><div class='add'>+			requested_dispclk_khz = dc-&gt;debug.min_disp_clk_khz;</div><div class='add'>+</div><div class='add'>+		dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);</div><div class='ctx'> 		clk_mgr_base-&gt;clks.dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='del'>-		dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base-&gt;clks.dispclk_khz);</div><div class='add'>+</div><div class='ctx'> 		dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);</div><div class='ctx'> </div><div class='ctx'> 		update_dispclk = true;</div><div class='hunk'>@@ -333,6 +515,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	// notify PMFW of bandwidth per DPIA tunnel</div><div class='add'>+	if (dc-&gt;debug.notify_dpia_hr_bw)</div><div class='add'>+		dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);</div><div class='add'>+</div><div class='ctx'> 	// notify DMCUB of latest clocks</div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> 	cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;</div><div class='hunk'>@@ -352,7 +538,6 @@ static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> 	struct fixed31_32 pll_req;</div><div class='ctx'> 	unsigned int fbmult_frac_val = 0;</div><div class='ctx'> 	unsigned int fbmult_int_val = 0;</div><div class='del'>-	struct dc_context *ctx = clk_mgr-&gt;base.ctx;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Register value of fbmult is in 8.16 format, we are converting to 314.32</div><div class='hunk'>@@ -404,14 +589,139 @@ bool dcn35_are_clock_states_equal(struct dc_clocks *a,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='add'>+static void dcn35_save_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	// read dtbclk</div><div class='add'>+	internal-&gt;CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dcfclk</div><div class='add'>+	internal-&gt;CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dcf deep sleep divider</div><div class='add'>+	internal-&gt;CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);</div><div class='add'>+	internal-&gt;CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);</div><div class='add'>+</div><div class='add'>+	// read dppclk</div><div class='add'>+	internal-&gt;CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dprefclk</div><div class='add'>+	internal-&gt;CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	// read dispclk</div><div class='add'>+	internal-&gt;CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);</div><div class='add'>+	internal-&gt;CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='ctx'> 		struct clk_mgr_dcn35 *clk_mgr)</div><div class='ctx'> {</div><div class='add'>+	struct dcn35_clk_internal internal = {0};</div><div class='add'>+	char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};</div><div class='add'>+</div><div class='add'>+	dcn35_save_clk_registers_internal(&amp;internal, &amp;clk_mgr-&gt;base.base);</div><div class='add'>+</div><div class='add'>+	regs_and_bypass-&gt;dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;</div><div class='add'>+	regs_and_bypass-&gt;dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;</div><div class='add'>+	regs_and_bypass-&gt;dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;</div><div class='add'>+	regs_and_bypass-&gt;dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;</div><div class='add'>+</div><div class='add'>+	regs_and_bypass-&gt;dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dppclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dppclk_bypass = 0;</div><div class='add'>+	regs_and_bypass-&gt;dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dcfclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dcfclk_bypass = 0;</div><div class='add'>+	regs_and_bypass-&gt;dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dispclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dispclk_bypass = 0;</div><div class='add'>+	regs_and_bypass-&gt;dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL &amp; 0x0007;</div><div class='add'>+	if (regs_and_bypass-&gt;dprefclk_bypass &gt; 4)</div><div class='add'>+		regs_and_bypass-&gt;dprefclk_bypass = 0;</div><div class='add'>+</div><div class='add'>+	if (clk_mgr-&gt;base.base.ctx-&gt;dc-&gt;debug.pstate_enabled) {</div><div class='add'>+		DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n",</div><div class='add'>+				   regs_and_bypass-&gt;dcfclk,</div><div class='add'>+				   regs_and_bypass-&gt;dcf_deep_sleep_divider,</div><div class='add'>+				   regs_and_bypass-&gt;dcf_deep_sleep_allow,</div><div class='add'>+				   bypass_clks[(int) regs_and_bypass-&gt;dcfclk_bypass]);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n",</div><div class='add'>+			regs_and_bypass-&gt;dprefclk,</div><div class='add'>+			bypass_clks[(int) regs_and_bypass-&gt;dprefclk_bypass]);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n",</div><div class='add'>+			regs_and_bypass-&gt;dispclk,</div><div class='add'>+			bypass_clks[(int) regs_and_bypass-&gt;dispclk_bypass]);</div><div class='add'>+</div><div class='add'>+		// REGISTER VALUES</div><div class='add'>+		DC_LOG_SMU("reg_name,value,clk_type");</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk",</div><div class='add'>+				internal.CLK1_CLK3_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk",</div><div class='add'>+					internal.CLK1_CLK4_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider",</div><div class='add'>+					internal.CLK1_CLK3_DS_CNTL);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow",</div><div class='add'>+					internal.CLK1_CLK3_ALLOW_DS);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk",</div><div class='add'>+					internal.CLK1_CLK2_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk",</div><div class='add'>+					internal.CLK1_CLK0_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk",</div><div class='add'>+					internal.CLK1_CLK1_CURRENT_CNT);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass",</div><div class='add'>+					internal.CLK1_CLK3_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass",</div><div class='add'>+					internal.CLK1_CLK2_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass",</div><div class='add'>+					internal.CLK1_CLK0_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+		DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass",</div><div class='add'>+					internal.CLK1_CLK1_BYPASS_CNTL);</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	uint32_t ssc_enable;</div><div class='add'>+</div><div class='add'>+	if (clk_mgr_base-&gt;ctx-&gt;dce_version == DCN_VERSION_3_51) {</div><div class='add'>+		ssc_enable = REG_READ(CLK6_spll_field_8) &amp; CLK6_spll_field_8__spll_ssc_en_MASK;</div><div class='add'>+	} else {</div><div class='add'>+		ssc_enable = REG_READ(CLK5_spll_field_8) &amp; CLK5_spll_field_8__spll_ssc_en_MASK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ssc_enable != 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void init_clk_states(struct clk_mgr *clk_mgr)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t ref_dtbclk = clk_mgr-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+</div><div class='ctx'> 	memset(&amp;(clk_mgr-&gt;clks), 0, sizeof(struct dc_clocks));</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;clks.ref_dtbclk_khz = ref_dtbclk;	// restore ref_dtbclk</div><div class='hunk'>@@ -423,7 +733,25 @@ static void init_clk_states(struct clk_mgr *clk_mgr)</div><div class='ctx'> </div><div class='ctx'> void dcn35_init_clocks(struct clk_mgr *clk_mgr)</div><div class='ctx'> {</div><div class='add'>+	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);</div><div class='add'>+	struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr_int);</div><div class='add'>+</div><div class='ctx'> 	init_clk_states(clk_mgr);</div><div class='add'>+</div><div class='add'>+	// to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk</div><div class='add'>+	if (dcn35_is_spll_ssc_enabled(clk_mgr))</div><div class='add'>+		clk_mgr-&gt;dp_dto_source_clock_in_khz =</div><div class='add'>+			dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr-&gt;dprefclk_khz);</div><div class='add'>+	else</div><div class='add'>+		clk_mgr-&gt;dp_dto_source_clock_in_khz = clk_mgr-&gt;dprefclk_khz;</div><div class='add'>+</div><div class='add'>+	dcn35_save_clk_registers(&amp;clk_mgr-&gt;boot_snapshot, clk_mgr_dcn35);</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;clks.ref_dtbclk_khz =  clk_mgr-&gt;boot_snapshot.dtbclk * 10;</div><div class='add'>+	if (clk_mgr-&gt;boot_snapshot.dtbclk &gt; 59000) {</div><div class='add'>+		/*dtbclk enabled based on */</div><div class='add'>+		clk_mgr-&gt;clks.dtbclk_en = true;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> static struct clk_bw_params dcn35_bw_params = {</div><div class='ctx'> 	.vram_type = Ddr4MemType,</div><div class='hunk'>@@ -509,9 +837,32 @@ static struct wm_table lpddr5_wm_table = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static DpmClocks_t_dcn35 dummy_clocks;</div><div class='add'>+static DpmClocks_t_dcn351 dummy_clocks_dcn351;</div><div class='ctx'> </div><div class='ctx'> static struct dcn35_watermarks dummy_wms = { 0 };</div><div class='ctx'> </div><div class='add'>+static struct dcn35_ss_info_table ss_info_table = {</div><div class='add'>+	.ss_divider = 1000,</div><div class='add'>+	.ss_percentage = {0, 0, 375, 375, 375}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	uint32_t clock_source = 0;</div><div class='add'>+</div><div class='add'>+	clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) &amp; CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;</div><div class='add'>+</div><div class='add'>+	// If it's DFS mode, clock_source is 0.</div><div class='add'>+	if (dcn35_is_spll_ssc_enabled(&amp;clk_mgr-&gt;base) &amp;&amp; (clock_source &lt; ARRAY_SIZE(ss_info_table.ss_percentage))) {</div><div class='add'>+		clk_mgr-&gt;dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];</div><div class='add'>+</div><div class='add'>+		if (clk_mgr-&gt;dprefclk_ss_percentage != 0) {</div><div class='add'>+			clk_mgr-&gt;ss_on_dprefclk = true;</div><div class='add'>+			clk_mgr-&gt;dprefclk_ss_divider = ss_info_table.ss_divider;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)</div><div class='ctx'> {</div><div class='ctx'> 	int i, num_valid_sets;</div><div class='hunk'>@@ -610,6 +961,22 @@ static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,</div><div class='ctx'> 	dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		struct dcn351_smu_dpm_clks *smu_dpm_clks)</div><div class='add'>+{</div><div class='add'>+	DpmClocks_t_dcn351 *table = smu_dpm_clks-&gt;dpm_clks;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr-&gt;smu_ver)</div><div class='add'>+		return;</div><div class='add'>+	if (!table || smu_dpm_clks-&gt;mc_address.quad_part == 0)</div><div class='add'>+		return;</div><div class='add'>+	memset(table, 0, sizeof(*table));</div><div class='add'>+	dcn35_smu_set_dram_addr_high(clk_mgr,</div><div class='add'>+			smu_dpm_clks-&gt;mc_address.high_part);</div><div class='add'>+	dcn35_smu_set_dram_addr_low(clk_mgr,</div><div class='add'>+			smu_dpm_clks-&gt;mc_address.low_part);</div><div class='add'>+	dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);</div><div class='add'>+}</div><div class='ctx'> static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t max = 0;</div><div class='hunk'>@@ -709,7 +1076,7 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk</div><div class='ctx'> 		clock_table-&gt;NumFclkLevelsEnabled;</div><div class='ctx'> 	max_fclk = find_max_clk_value(clock_table-&gt;FclkClocks_Freq, num_fclk);</div><div class='ctx'> </div><div class='del'>-	num_dcfclk = (clock_table-&gt;NumFclkLevelsEnabled &gt; NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :</div><div class='add'>+	num_dcfclk = (clock_table-&gt;NumDcfClkLevelsEnabled &gt; NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :</div><div class='ctx'> 		clock_table-&gt;NumDcfClkLevelsEnabled;</div><div class='ctx'> 	for (i = 0; i &lt; num_dcfclk; i++) {</div><div class='ctx'> 		int j;</div><div class='hunk'>@@ -836,35 +1203,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn35_set_ips_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)</div><div class='del'>-{</div><div class='del'>-	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='del'>-	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='del'>-	uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);</div><div class='del'>-</div><div class='del'>-	if (dc-&gt;config.disable_ips == DMUB_IPS_ENABLE ||</div><div class='del'>-		dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {</div><div class='del'>-		val = val &amp; ~DMUB_IPS1_ALLOW_MASK;</div><div class='del'>-		val = val &amp; ~DMUB_IPS2_ALLOW_MASK;</div><div class='del'>-	} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_IPS1) {</div><div class='del'>-		val |= DMUB_IPS1_ALLOW_MASK;</div><div class='del'>-		val |= DMUB_IPS2_ALLOW_MASK;</div><div class='del'>-	} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_IPS2) {</div><div class='del'>-		val = val &amp; ~DMUB_IPS1_ALLOW_MASK;</div><div class='del'>-		val |= DMUB_IPS2_ALLOW_MASK;</div><div class='del'>-	} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {</div><div class='del'>-		val = val &amp; ~DMUB_IPS1_ALLOW_MASK;</div><div class='del'>-		val = val &amp; ~DMUB_IPS2_ALLOW_MASK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!allow_idle) {</div><div class='del'>-		val |= DMUB_IPS1_ALLOW_MASK;</div><div class='del'>-		val |= DMUB_IPS2_ALLOW_MASK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dcn35_smu_write_ips_scratch(clk_mgr, val);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='hunk'>@@ -877,18 +1215,8 @@ static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='del'>-	bool ips_supported = true;</div><div class='del'>-</div><div class='del'>-	ips_supported = dcn35_smu_get_ips_supported(clk_mgr) ? true : false;</div><div class='del'>-</div><div class='del'>-	return ips_supported;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static uint32_t dcn35_get_ips_idle_state(struct clk_mgr *clk_mgr_base)</div><div class='del'>-{</div><div class='del'>-	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> </div><div class='del'>-	return dcn35_smu_read_ips_scratch(clk_mgr);</div><div class='add'>+	return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)</div><div class='hunk'>@@ -967,6 +1295,35 @@ static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,</div><div class='ctx'> 	dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr-&gt;clks.ref_dtbclk_khz);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	unsigned int num_clk_levels;</div><div class='add'>+</div><div class='add'>+	switch (clk_type) {</div><div class='add'>+	case CLK_TYPE_DISPCLK:</div><div class='add'>+		num_clk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dispclk_levels;</div><div class='add'>+		return num_clk_levels ?</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :</div><div class='add'>+				clk_mgr-&gt;base.boot_snapshot.dispclk;</div><div class='add'>+	case CLK_TYPE_DPPCLK:</div><div class='add'>+		num_clk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dppclk_levels;</div><div class='add'>+		return num_clk_levels ?</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :</div><div class='add'>+				clk_mgr-&gt;base.boot_snapshot.dppclk;</div><div class='add'>+	case CLK_TYPE_DSCCLK:</div><div class='add'>+		num_clk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dispclk_levels;</div><div class='add'>+		return num_clk_levels ?</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :</div><div class='add'>+				clk_mgr-&gt;base.boot_snapshot.dispclk / 3;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct clk_mgr_funcs dcn35_funcs = {</div><div class='ctx'> 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,</div><div class='ctx'> 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,</div><div class='hunk'>@@ -978,8 +1335,7 @@ static struct clk_mgr_funcs dcn35_funcs = {</div><div class='ctx'> 	.set_low_power_state = dcn35_set_low_power_state,</div><div class='ctx'> 	.exit_low_power_state = dcn35_exit_low_power_state,</div><div class='ctx'> 	.is_ips_supported = dcn35_is_ips_supported,</div><div class='del'>-	.set_idle_state = dcn35_set_ips_idle_state,</div><div class='del'>-	.get_idle_state = dcn35_get_ips_idle_state</div><div class='add'>+	.get_max_clock_khz = dcn35_get_max_clock_khz,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct clk_mgr_funcs dcn35_fpga_funcs = {</div><div class='hunk'>@@ -989,6 +1345,57 @@ struct clk_mgr_funcs dcn35_fpga_funcs = {</div><div class='ctx'> 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks *smu_dpm_clks_a,</div><div class='add'>+		struct dcn35_smu_dpm_clks *smu_dpm_clks_b)</div><div class='add'>+{</div><div class='add'>+	/*translate two structures and only take need clock tables*/</div><div class='add'>+	uint8_t i;</div><div class='add'>+</div><div class='add'>+	if (smu_dpm_clks_a == NULL || smu_dpm_clks_b == NULL ||</div><div class='add'>+		smu_dpm_clks_a-&gt;dpm_clks == NULL || smu_dpm_clks_b-&gt;dpm_clks == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_DCFCLK_DPM_LEVELS; i++)</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;DcfClocks[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;DcfClocks[i];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_DISPCLK_DPM_LEVELS; i++)</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;DispClocks[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;DispClocks[i];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_DPPCLK_DPM_LEVELS; i++)</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;DppClocks[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;DppClocks[i];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_FCLK_DPM_LEVELS; i++) {</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;FclkClocks_Freq[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;FclkClocks_Freq[i];</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;FclkClocks_Voltage[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;FclkClocks_Voltage[i];</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; NUM_MEM_PSTATE_LEVELS; i++) {</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;MemPstateTable[i].MemClk =</div><div class='add'>+			smu_dpm_clks_a-&gt;dpm_clks-&gt;MemPstateTable[i].MemClk;</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;MemPstateTable[i].UClk =</div><div class='add'>+			smu_dpm_clks_a-&gt;dpm_clks-&gt;MemPstateTable[i].UClk;</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;MemPstateTable[i].Voltage =</div><div class='add'>+			smu_dpm_clks_a-&gt;dpm_clks-&gt;MemPstateTable[i].Voltage;</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;MemPstateTable[i].WckRatio =</div><div class='add'>+			smu_dpm_clks_a-&gt;dpm_clks-&gt;MemPstateTable[i].WckRatio;</div><div class='add'>+	}</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;MaxGfxClk = smu_dpm_clks_a-&gt;dpm_clks-&gt;MaxGfxClk;</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;MinGfxClk = smu_dpm_clks_a-&gt;dpm_clks-&gt;MinGfxClk;</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;NumDcfClkLevelsEnabled =</div><div class='add'>+		smu_dpm_clks_a-&gt;dpm_clks-&gt;NumDcfClkLevelsEnabled;</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;NumDispClkLevelsEnabled =</div><div class='add'>+		smu_dpm_clks_a-&gt;dpm_clks-&gt;NumDispClkLevelsEnabled;</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;NumFclkLevelsEnabled =</div><div class='add'>+		smu_dpm_clks_a-&gt;dpm_clks-&gt;NumFclkLevelsEnabled;</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;NumMemPstatesEnabled =</div><div class='add'>+		smu_dpm_clks_a-&gt;dpm_clks-&gt;NumMemPstatesEnabled;</div><div class='add'>+	smu_dpm_clks_b-&gt;dpm_clks-&gt;NumSocClkLevelsEnabled =</div><div class='add'>+		smu_dpm_clks_a-&gt;dpm_clks-&gt;NumSocClkLevelsEnabled;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_SOC_VOLTAGE_LEVELS; i++) {</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;SocClocks[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;SocClocks[i];</div><div class='add'>+		smu_dpm_clks_b-&gt;dpm_clks-&gt;SocVoltage[i] = smu_dpm_clks_a-&gt;dpm_clks-&gt;SocVoltage[i];</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> void dcn35_clk_mgr_construct(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct clk_mgr_dcn35 *clk_mgr,</div><div class='hunk'>@@ -996,6 +1403,7 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 		struct dccg *dccg)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };</div><div class='add'>+	struct dcn351_smu_dpm_clks smu_dpm_clks_dcn351 = { 0 };</div><div class='ctx'> 	clk_mgr-&gt;base.base.ctx = ctx;</div><div class='ctx'> 	clk_mgr-&gt;base.base.funcs = &amp;dcn35_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -1008,10 +1416,16 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 	clk_mgr-&gt;base.dprefclk_ss_divider = 1000;</div><div class='ctx'> 	clk_mgr-&gt;base.ss_on_dprefclk = false;</div><div class='ctx'> 	clk_mgr-&gt;base.dfs_ref_freq_khz = 48000;</div><div class='add'>+	if (ctx-&gt;dce_version != DCN_VERSION_3_51) {</div><div class='add'>+		clk_mgr-&gt;base.regs = &amp;clk_mgr_regs_dcn35;</div><div class='add'>+		clk_mgr-&gt;base.clk_mgr_shift = &amp;clk_mgr_shift_dcn35;</div><div class='add'>+		clk_mgr-&gt;base.clk_mgr_mask = &amp;clk_mgr_mask_dcn35;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(</div><div class='ctx'> 				clk_mgr-&gt;base.base.ctx,</div><div class='del'>-				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,</div><div class='add'>+				DC_MEM_ALLOC_TYPE_GART,</div><div class='ctx'> 				sizeof(struct dcn35_watermarks),</div><div class='ctx'> 				&amp;clk_mgr-&gt;smu_wm_set.mc_address.quad_part);</div><div class='ctx'> </div><div class='hunk'>@@ -1023,17 +1437,27 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> </div><div class='ctx'> 	smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(</div><div class='ctx'> 				clk_mgr-&gt;base.base.ctx,</div><div class='del'>-				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,</div><div class='add'>+				DC_MEM_ALLOC_TYPE_GART,</div><div class='ctx'> 				sizeof(DpmClocks_t_dcn35),</div><div class='ctx'> 				&amp;smu_dpm_clks.mc_address.quad_part);</div><div class='del'>-</div><div class='ctx'> 	if (smu_dpm_clks.dpm_clks == NULL) {</div><div class='ctx'> 		smu_dpm_clks.dpm_clks = &amp;dummy_clocks;</div><div class='ctx'> 		smu_dpm_clks.mc_address.quad_part = 0;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> 	ASSERT(smu_dpm_clks.dpm_clks);</div><div class='ctx'> </div><div class='add'>+	if (ctx-&gt;dce_version == DCN_VERSION_3_51) {</div><div class='add'>+		smu_dpm_clks_dcn351.dpm_clks = (DpmClocks_t_dcn351 *)dm_helpers_allocate_gpu_mem(</div><div class='add'>+				clk_mgr-&gt;base.base.ctx,</div><div class='add'>+				DC_MEM_ALLOC_TYPE_GART,</div><div class='add'>+				sizeof(DpmClocks_t_dcn351),</div><div class='add'>+				&amp;smu_dpm_clks_dcn351.mc_address.quad_part);</div><div class='add'>+		if (smu_dpm_clks_dcn351.dpm_clks == NULL) {</div><div class='add'>+			smu_dpm_clks_dcn351.dpm_clks = &amp;dummy_clocks_dcn351;</div><div class='add'>+			smu_dpm_clks_dcn351.mc_address.quad_part = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	clk_mgr-&gt;base.smu_ver = dcn35_smu_get_smu_version(&amp;clk_mgr-&gt;base);</div><div class='ctx'> </div><div class='ctx'> 	if (clk_mgr-&gt;base.smu_ver)</div><div class='hunk'>@@ -1048,7 +1472,7 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 		dcn35_bw_params.wm_table = ddr5_wm_table;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Saved clocks configured at boot for debug purposes */</div><div class='del'>-	dcn35_dump_clk_registers(&amp;clk_mgr-&gt;base.base.boot_snapshot, clk_mgr);</div><div class='add'>+	dcn35_save_clk_registers(&amp;clk_mgr-&gt;base.base.boot_snapshot, clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&amp;clk_mgr-&gt;base);</div><div class='ctx'> 	clk_mgr-&gt;base.base.clks.ref_dtbclk_khz = 600000;</div><div class='hunk'>@@ -1056,11 +1480,17 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 	dce_clock_read_ss_info(&amp;clk_mgr-&gt;base);</div><div class='ctx'> 	/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/</div><div class='ctx'> </div><div class='add'>+	dcn35_read_ss_info_from_lut(&amp;clk_mgr-&gt;base);</div><div class='add'>+</div><div class='ctx'> 	clk_mgr-&gt;base.base.bw_params = &amp;dcn35_bw_params;</div><div class='ctx'> </div><div class='ctx'> 	if (clk_mgr-&gt;base.base.ctx-&gt;dc-&gt;debug.pstate_enabled) {</div><div class='ctx'> 		int i;</div><div class='del'>-		dcn35_get_dpm_table_from_smu(&amp;clk_mgr-&gt;base, &amp;smu_dpm_clks);</div><div class='add'>+		if (ctx-&gt;dce_version == DCN_VERSION_3_51) {</div><div class='add'>+			dcn351_get_dpm_table_from_smu(&amp;clk_mgr-&gt;base, &amp;smu_dpm_clks_dcn351);</div><div class='add'>+			translate_to_DpmClocks_t_dcn35(&amp;smu_dpm_clks_dcn351, &amp;smu_dpm_clks);</div><div class='add'>+		} else</div><div class='add'>+			dcn35_get_dpm_table_from_smu(&amp;clk_mgr-&gt;base, &amp;smu_dpm_clks);</div><div class='ctx'> 		DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"</div><div class='ctx'> 				   "NumDispClkLevelsEnabled: %d\n"</div><div class='ctx'> 				   "NumSocClkLevelsEnabled: %d\n"</div><div class='hunk'>@@ -1109,7 +1539,7 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 					   i, smu_dpm_clks.dpm_clks-&gt;MemPstateTable[i].Voltage);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (ctx-&gt;dc_bios &amp;&amp; ctx-&gt;dc_bios-&gt;integrated_info &amp;&amp; ctx-&gt;dc-&gt;config.use_default_clock_table == false) {</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;integrated_info &amp;&amp; ctx-&gt;dc-&gt;config.use_default_clock_table == false) {</div><div class='ctx'> 			dcn35_clk_mgr_helper_populate_bw_params(</div><div class='ctx'> 					&amp;clk_mgr-&gt;base,</div><div class='ctx'> 					ctx-&gt;dc_bios-&gt;integrated_info,</div><div class='hunk'>@@ -1118,9 +1548,13 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (smu_dpm_clks.dpm_clks &amp;&amp; smu_dpm_clks.mc_address.quad_part != 0)</div><div class='del'>-		dm_helpers_free_gpu_mem(clk_mgr-&gt;base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,</div><div class='add'>+		dm_helpers_free_gpu_mem(clk_mgr-&gt;base.base.ctx, DC_MEM_ALLOC_TYPE_GART,</div><div class='ctx'> 				smu_dpm_clks.dpm_clks);</div><div class='ctx'> </div><div class='add'>+	if (smu_dpm_clks_dcn351.dpm_clks &amp;&amp; smu_dpm_clks_dcn351.mc_address.quad_part != 0)</div><div class='add'>+		dm_helpers_free_gpu_mem(clk_mgr-&gt;base.base.ctx, DC_MEM_ALLOC_TYPE_GART,</div><div class='add'>+				smu_dpm_clks_dcn351.dpm_clks);</div><div class='add'>+</div><div class='ctx'> 	if (ctx-&gt;dc-&gt;config.disable_ips != DMUB_IPS_DISABLE_ALL) {</div><div class='ctx'> 		bool ips_support = false;</div><div class='ctx'> </div><div class='hunk'>@@ -1131,6 +1565,12 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 			ctx-&gt;dc-&gt;debug.disable_dpp_power_gate = false;</div><div class='ctx'> 			ctx-&gt;dc-&gt;debug.disable_hubp_power_gate = false;</div><div class='ctx'> 			ctx-&gt;dc-&gt;debug.disable_dsc_power_gate = false;</div><div class='add'>+</div><div class='add'>+			/* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */</div><div class='add'>+			if (ctx-&gt;dc-&gt;config.disable_ips == DMUB_IPS_ENABLE &amp;&amp;</div><div class='add'>+			    ctx-&gt;dce_version != DCN_VERSION_3_51 &amp;&amp;</div><div class='add'>+			    ((clk_mgr-&gt;base.smu_ver &amp; 0x00FFFFFF) &lt;= 0x005d0c00))</div><div class='add'>+				ctx-&gt;dc-&gt;config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/*let's reset the config control flag*/</div><div class='ctx'> 			ctx-&gt;dc-&gt;config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h<br/>index 1203dc605b12..a12a9bf90806 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h</a></div><div class='hunk'>@@ -60,4 +60,8 @@ void dcn35_clk_mgr_construct(struct dc_context *ctx,</div><div class='ctx'> </div><div class='ctx'> void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);</div><div class='ctx'> </div><div class='add'>+void dcn351_clk_mgr_construct(struct dc_context *ctx,</div><div class='add'>+		struct clk_mgr_dcn35 *clk_mgr,</div><div class='add'>+		struct pp_smu_funcs *pp_smu,</div><div class='add'>+		struct dccg *dccg);</div><div class='ctx'> #endif //__DCN35_CLK_MGR_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c<br/>index 9e588c56c570..604d256cb47a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c</a></div><div class='hunk'>@@ -84,12 +84,13 @@</div><div class='ctx'> #define VBIOSSMC_MSG_AllowZstatesEntry            0x15</div><div class='ctx'> #define VBIOSSMC_MSG_DisallowZstatesEntry     	  0x16</div><div class='ctx'> #define VBIOSSMC_MSG_SetDtbClk                    0x17</div><div class='del'>-#define VBIOSSMC_MSG_DispPsrEntry                 0x18 ///&lt; Display PSR entry, DMU</div><div class='del'>-#define VBIOSSMC_MSG_DispPsrExit                  0x19 ///&lt; Display PSR exit, DMU</div><div class='add'>+#define VBIOSSMC_MSG_DispIPS2Entry                0x18 ///&lt; Display IPS2 entry, DMU</div><div class='add'>+#define VBIOSSMC_MSG_DispIPS2Exit                 0x19 ///&lt; Display IPS2 exit, DMU</div><div class='ctx'> #define VBIOSSMC_MSG_DisableLSdma                 0x1A ///&lt; Disable LSDMA; only sent by VBIOS</div><div class='ctx'> #define VBIOSSMC_MSG_DpControllerPhyStatus        0x1B ///&lt; Inform PMFW about the pre conditions for turning SLDO2 on/off . bit[0]==1 precondition is met, bit[1-2] are for DPPHY number</div><div class='ctx'> #define VBIOSSMC_MSG_QueryIPS2Support             0x1C ///&lt; Return 1: support; else not supported</div><div class='del'>-#define VBIOSSMC_Message_Count                    0x1D</div><div class='add'>+#define VBIOSSMC_MSG_NotifyHostRouterBW           0x1D</div><div class='add'>+#define VBIOSSMC_Message_Count                    0x1E</div><div class='ctx'> </div><div class='ctx'> #define VBIOSSMC_Status_BUSY                      0x0</div><div class='ctx'> #define VBIOSSMC_Result_OK                        0x1</div><div class='hunk'>@@ -98,6 +99,14 @@</div><div class='ctx'> #define VBIOSSMC_Result_CmdRejectedPrereq         0xFD</div><div class='ctx'> #define VBIOSSMC_Result_CmdRejectedBusy           0xFC</div><div class='ctx'> </div><div class='add'>+union dcn35_dpia_host_router_bw {</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t hr_id : 16;</div><div class='add'>+		uint32_t bw_mbps : 16;</div><div class='add'>+	} bits;</div><div class='add'>+	uint32_t all;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Function to be used instead of REG_WAIT macro because the wait ends when</div><div class='ctx'>  * the register is NOT EQUAL to zero, and because `the translation in msg_if.h</div><div class='hunk'>@@ -466,7 +475,7 @@ int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> </div><div class='ctx'> 	retv = dcn35_smu_send_msg_with_param(</div><div class='ctx'> 		clk_mgr,</div><div class='del'>-		VBIOSSMC_MSG_DispPsrExit,</div><div class='add'>+		VBIOSSMC_MSG_DispIPS2Exit,</div><div class='ctx'> 		0);</div><div class='ctx'> 	smu_print("%s: smu_exit_low_power_state return = %d\n", __func__, retv);</div><div class='ctx'> 	return retv;</div><div class='hunk'>@@ -488,23 +497,12 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> 	return retv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)</div><div class='del'>-{</div><div class='del'>-	if (!clk_mgr-&gt;smu_present)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	REG_WRITE(MP1_SMN_C2PMSG_71, param);</div><div class='del'>-	//smu_print("%s: write_ips_scratch = %x\n", __func__, param);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps)</div><div class='ctx'> {</div><div class='del'>-	uint32_t retv;</div><div class='add'>+	union dcn35_dpia_host_router_bw msg_data = { 0 };</div><div class='ctx'> </div><div class='del'>-	if (!clk_mgr-&gt;smu_present)</div><div class='del'>-		return 0;</div><div class='add'>+	msg_data.bits.hr_id = hr_id;</div><div class='add'>+	msg_data.bits.bw_mbps = bw_kbps / 1000;</div><div class='ctx'> </div><div class='del'>-	retv = REG_READ(MP1_SMN_C2PMSG_71);</div><div class='del'>-	//smu_print("%s: dcn35_smu_read_ips_scratch = %x\n",  __func__, retv);</div><div class='del'>-	return retv;</div><div class='add'>+	dcn35_smu_send_msg_with_param(clk_mgr, VBIOSSMC_MSG_NotifyHostRouterBW, msg_data.all);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h<br/>index 2b8e6959a03d..ab9d21ba0c43 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h</a></div><div class='hunk'>@@ -126,18 +126,31 @@ typedef struct {</div><div class='ctx'>   uint32_t MaxGfxClk;</div><div class='ctx'> } DpmClocks_t_dcn35;</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-// Throttler Status Bitmask</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='add'>+typedef struct {</div><div class='add'>+	uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t VClocks0[NUM_VCN_DPM_LEVELS];</div><div class='add'>+	uint32_t VClocks1[NUM_VCN_DPM_LEVELS];</div><div class='add'>+	uint32_t DClocks0[NUM_VCN_DPM_LEVELS];</div><div class='add'>+	uint32_t DClocks1[NUM_VCN_DPM_LEVELS];</div><div class='add'>+	uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];</div><div class='add'>+	uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];</div><div class='add'>+	uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];</div><div class='add'>+	MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];</div><div class='add'>+	uint8_t NumDcfClkLevelsEnabled;</div><div class='add'>+	uint8_t NumDispClkLevelsEnabled; // Applies to both Dispclk and Dppclk</div><div class='add'>+	uint8_t NumSocClkLevelsEnabled;</div><div class='add'>+	uint8_t Vcn0ClkLevelsEnabled; // Applies to both Vclk0 and Dclk0</div><div class='add'>+	uint8_t Vcn1ClkLevelsEnabled; // Applies to both Vclk1 and Dclk1</div><div class='add'>+	uint8_t VpeClkLevelsEnabled;</div><div class='add'>+	uint8_t NumMemPstatesEnabled;</div><div class='add'>+	uint8_t NumFclkLevelsEnabled;</div><div class='add'>+	uint32_t MinGfxClk;</div><div class='add'>+	uint32_t MaxGfxClk;</div><div class='add'>+} DpmClocks_t_dcn351;</div><div class='ctx'> </div><div class='ctx'> #define TABLE_BIOS_IF            0 // Called by BIOS</div><div class='ctx'> #define TABLE_WATERMARKS         1 // Called by DAL through VBIOS</div><div class='hunk'>@@ -163,6 +176,10 @@ struct dcn35_smu_dpm_clks {</div><div class='ctx'> 	union large_integer mc_address;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn351_smu_dpm_clks {</div><div class='add'>+	DpmClocks_t_dcn351 *dpm_clks;</div><div class='add'>+	union large_integer mc_address;</div><div class='add'>+};</div><div class='ctx'> /* TODO: taken from vgh, may not be correct */</div><div class='ctx'> struct display_idle_optimization {</div><div class='ctx'> 	unsigned int df_request_disabled : 1;</div><div class='hunk'>@@ -198,6 +215,6 @@ int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);</div><div class='ctx'> int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);</div><div class='del'>-void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);</div><div class='del'>-uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps);</div><div class='add'>+</div><div class='ctx'> #endif /* DAL_DC_35_SMU_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h<br/>new file mode 100644<br/>index 000000000000..2e0d34fd7512<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef DALSMC_H</div><div class='add'>+#define DALSMC_H</div><div class='add'>+</div><div class='add'>+#define DALSMC_VERSION 0x1</div><div class='add'>+</div><div class='add'>+// SMU Response Codes:</div><div class='add'>+#define DALSMC_Result_OK                   0x1</div><div class='add'>+#define DALSMC_Result_Failed               0xFF</div><div class='add'>+#define DALSMC_Result_UnknownCmd           0xFE</div><div class='add'>+#define DALSMC_Result_CmdRejectedPrereq    0xFD</div><div class='add'>+#define DALSMC_Result_CmdRejectedBusy      0xFC</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// Message Definitions:</div><div class='add'>+#define DALSMC_MSG_TestMessage                    0x1</div><div class='add'>+#define DALSMC_MSG_GetSmuVersion                  0x2</div><div class='add'>+#define DALSMC_MSG_GetDriverIfVersion             0x3</div><div class='add'>+#define DALSMC_MSG_GetMsgHeaderVersion            0x4</div><div class='add'>+#define DALSMC_MSG_SetDalDramAddrHigh             0x5</div><div class='add'>+#define DALSMC_MSG_SetDalDramAddrLow              0x6</div><div class='add'>+#define DALSMC_MSG_TransferTableSmu2Dram          0x7</div><div class='add'>+#define DALSMC_MSG_TransferTableDram2Smu          0x8</div><div class='add'>+#define DALSMC_MSG_SetHardMinByFreq               0x9</div><div class='add'>+#define DALSMC_MSG_SetHardMaxByFreq               0xA</div><div class='add'>+#define DALSMC_MSG_GetDpmFreqByIndex              0xB</div><div class='add'>+#define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC</div><div class='add'>+#define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD</div><div class='add'>+#define DALSMC_MSG_NumOfDisplays                  0xE</div><div class='add'>+#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF</div><div class='add'>+#define DALSMC_MSG_BacoAudioD3PME                 0x10</div><div class='add'>+#define DALSMC_MSG_SetFclkSwitchAllow             0x11</div><div class='add'>+#define DALSMC_MSG_SetCabForUclkPstate            0x12</div><div class='add'>+#define DALSMC_MSG_SetWorstCaseUclkLatency        0x13</div><div class='add'>+#define DALSMC_MSG_DcnExitReset                   0x14</div><div class='add'>+#define DALSMC_MSG_ReturnHardMinStatus            0x15</div><div class='add'>+#define DALSMC_MSG_SetAlwaysWaitDmcubResp         0x16</div><div class='add'>+#define DALSMC_MSG_IndicateDrrStatus              0x17  // PMFW 15811</div><div class='add'>+#define DALSMC_MSG_ActiveUclkFclk                 0x18</div><div class='add'>+#define DALSMC_MSG_IdleUclkFclk                   0x19</div><div class='add'>+#define DALSMC_MSG_SetUclkPstateAllow             0x1A</div><div class='add'>+#define DALSMC_MSG_SubvpUclkFclk                  0x1B</div><div class='add'>+#define DALSMC_MSG_GetNumUmcChannels              0x1C</div><div class='add'>+#define DALSMC_Message_Count                      0x1D</div><div class='add'>+</div><div class='add'>+typedef enum {</div><div class='add'>+  FCLK_SWITCH_DISALLOW,</div><div class='add'>+  FCLK_SWITCH_ALLOW,</div><div class='add'>+} FclkSwitchAllow_e;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c<br/>new file mode 100644<br/>index 000000000000..306016c1f109<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c</a></div><div class='hunk'>@@ -0,0 +1,1631 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dccg.h"</div><div class='add'>+#include "clk_mgr_internal.h"</div><div class='add'>+#include "dcn401/dcn401_clk_mgr_smu_msg.h"</div><div class='add'>+#include "dcn20/dcn20_clk_mgr.h"</div><div class='add'>+#include "dce100/dce_clk_mgr.h"</div><div class='add'>+#include "dcn31/dcn31_clk_mgr.h"</div><div class='add'>+#include "dcn32/dcn32_clk_mgr.h"</div><div class='add'>+#include "dcn401/dcn401_clk_mgr.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dm_helpers.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+#include "atomfirmware.h"</div><div class='add'>+</div><div class='add'>+#include "dcn401_smu14_driver_if.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_4_1_0_offset.h"</div><div class='add'>+#include "dcn/dcn_4_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#define DCN_BASE__INST0_SEG1                       0x000000C0</div><div class='add'>+</div><div class='add'>+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E37</div><div class='add'>+#define mmCLK01_CLK0_CLK0_DFS_CNTL                      0x16E69</div><div class='add'>+#define mmCLK01_CLK0_CLK1_DFS_CNTL                      0x16E6C</div><div class='add'>+#define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E6F</div><div class='add'>+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E72</div><div class='add'>+#define mmCLK01_CLK0_CLK4_DFS_CNTL                      0x16E75</div><div class='add'>+#define mmCLK20_CLK2_CLK2_DFS_CNTL                      0x1B051</div><div class='add'>+</div><div class='add'>+#define CLK0_CLK_PLL_REQ__FbMult_int_MASK                  0x000001ffUL</div><div class='add'>+#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK                 0x0000f000UL</div><div class='add'>+#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK                 0xffff0000UL</div><div class='add'>+#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT                0x00000000</div><div class='add'>+#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT               0x0000000c</div><div class='add'>+#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT               0x00000010</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	clk_mgr-&gt;clk_mgr_shift-&gt;field_name, clk_mgr-&gt;clk_mgr_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+#define REG(reg) \</div><div class='add'>+	(clk_mgr-&gt;regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SR(reg_name)\</div><div class='add'>+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \</div><div class='add'>+					reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define CLK_SR_DCN401(reg_name, block, inst)\</div><div class='add'>+	.reg_name = mm ## block ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_registers clk_mgr_regs_dcn401 = {</div><div class='add'>+	CLK_REG_LIST_DCN401()</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_shift clk_mgr_shift_dcn401 = {</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define TO_DCN401_CLK_MGR(clk_mgr)\</div><div class='add'>+	container_of(clk_mgr, struct dcn401_clk_mgr, base)</div><div class='add'>+</div><div class='add'>+static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)</div><div class='add'>+{</div><div class='add'>+	bool ppclk_dpm_enabled = false;</div><div class='add'>+</div><div class='add'>+	switch (clk) {</div><div class='add'>+	case PPCLK_SOCCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_socclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_UCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_memclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_FCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_DISPCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dispclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_DPPCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dppclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_DPREFCLK:</div><div class='add'>+		ppclk_dpm_enabled = false;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_DCFCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dcfclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	case PPCLK_DTBCLK:</div><div class='add'>+		ppclk_dpm_enabled =</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dtbclk_levels &gt; 1;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ppclk_dpm_enabled = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ppclk_dpm_enabled &amp;= clk_mgr-&gt;smu_present;</div><div class='add'>+</div><div class='add'>+	return ppclk_dpm_enabled;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)</div><div class='add'>+{</div><div class='add'>+	bool ppclk_idle_dpm_enabled = false;</div><div class='add'>+</div><div class='add'>+	switch (clk) {</div><div class='add'>+	case PPCLK_UCLK:</div><div class='add'>+	case PPCLK_FCLK:</div><div class='add'>+		if (ASICREV_IS_GC_12_0_0_A0(clk_mgr-&gt;base.ctx-&gt;asic_id.hw_internal_rev) &amp;&amp;</div><div class='add'>+				clk_mgr-&gt;smu_ver &gt;= 0x681800) {</div><div class='add'>+			ppclk_idle_dpm_enabled = true;</div><div class='add'>+		} else if (ASICREV_IS_GC_12_0_1_A0(clk_mgr-&gt;base.ctx-&gt;asic_id.hw_internal_rev) &amp;&amp;</div><div class='add'>+				clk_mgr-&gt;smu_ver &gt;= 0x661300) {</div><div class='add'>+			ppclk_idle_dpm_enabled = true;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ppclk_idle_dpm_enabled = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ppclk_idle_dpm_enabled &amp;= clk_mgr-&gt;smu_present;</div><div class='add'>+</div><div class='add'>+	return ppclk_idle_dpm_enabled;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	bool is_df_throttle_opt_enabled = false;</div><div class='add'>+</div><div class='add'>+	if (ASICREV_IS_GC_12_0_1_A0(clk_mgr-&gt;base.ctx-&gt;asic_id.hw_internal_rev) &amp;&amp;</div><div class='add'>+			clk_mgr-&gt;smu_ver &gt;= 0x663500) {</div><div class='add'>+		is_df_throttle_opt_enabled = !clk_mgr-&gt;base.ctx-&gt;dc-&gt;debug.force_subvp_df_throttle;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	is_df_throttle_opt_enabled &amp;= clk_mgr-&gt;smu_present;</div><div class='add'>+</div><div class='add'>+	return is_df_throttle_opt_enabled;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Query SMU for all clock states for a particular clock */</div><div class='add'>+static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,</div><div class='add'>+		unsigned int *num_levels)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	char *entry_i = (char *)entry_0;</div><div class='add'>+</div><div class='add'>+	uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);</div><div class='add'>+</div><div class='add'>+	if (ret &amp; (1 &lt;&lt; 31))</div><div class='add'>+		/* fine-grained, only min and max */</div><div class='add'>+		*num_levels = 2;</div><div class='add'>+	else</div><div class='add'>+		/* discrete, a number of fixed states */</div><div class='add'>+		/* will set num_levels to 0 on failure */</div><div class='add'>+		*num_levels = ret &amp; 0xFF;</div><div class='add'>+</div><div class='add'>+	/* if the initial message failed, num_levels will be 0 */</div><div class='add'>+	for (i = 0; i &lt; *num_levels &amp;&amp; i &lt; ARRAY_SIZE(clk_mgr-&gt;base.bw_params-&gt;clk_table.entries); i++) {</div><div class='add'>+		*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) &amp; 0xFFFF);</div><div class='add'>+		entry_i += sizeof(clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[0]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	/* For min clocks use as reported by PM FW and report those as min */</div><div class='add'>+	uint16_t min_uclk_mhz = clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].memclk_mhz;</div><div class='add'>+	uint16_t min_dcfclk_mhz	= clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].dcfclk_mhz;</div><div class='add'>+</div><div class='add'>+	/* Set A - Normal - default values */</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].valid = true;</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;</div><div class='add'>+</div><div class='add'>+	/* Set B - Unused on dcn4 */</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_B].valid = false;</div><div class='add'>+</div><div class='add'>+	/* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */</div><div class='add'>+	/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */</div><div class='add'>+	if (clk_mgr-&gt;ctx-&gt;dc-&gt;bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].valid = true;</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;</div><div class='add'>+	} else {</div><div class='add'>+		clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1A].valid = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set 1B - Unused on dcn4 */</div><div class='add'>+	clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_1B].valid = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	struct clk_limit_num_entries *num_entries_per_clk;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr_base-&gt;bw_params)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_entries_per_clk = &amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk;</div><div class='add'>+</div><div class='add'>+	memset(&amp;(clk_mgr_base-&gt;clks), 0, sizeof(struct dc_clocks));</div><div class='add'>+	clk_mgr_base-&gt;clks.p_state_change_support = true;</div><div class='add'>+	clk_mgr_base-&gt;clks.prev_p_state_change_support = true;</div><div class='add'>+	clk_mgr_base-&gt;clks.fclk_prev_p_state_change_support = true;</div><div class='add'>+	clk_mgr-&gt;smu_present = false;</div><div class='add'>+	clk_mgr-&gt;dpm_present = false;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr_base-&gt;force_smu_not_present &amp;&amp; dcn401_smu_get_smu_version(clk_mgr, &amp;clk_mgr-&gt;smu_ver))</div><div class='add'>+		clk_mgr-&gt;smu_present = true;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr-&gt;smu_present)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dcn401_smu_check_driver_if_version(clk_mgr);</div><div class='add'>+	dcn401_smu_check_msg_header_version(clk_mgr);</div><div class='add'>+</div><div class='add'>+	/* DCFCLK */</div><div class='add'>+	dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,</div><div class='add'>+			&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].dcfclk_mhz,</div><div class='add'>+			&amp;num_entries_per_clk-&gt;num_dcfclk_levels);</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dcfclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);</div><div class='add'>+	if (num_entries_per_clk-&gt;num_dcfclk_levels &amp;&amp; clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dcfclk_mhz ==</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_dcfclk_levels - 1].dcfclk_mhz)</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dcfclk_mhz = 0;</div><div class='add'>+</div><div class='add'>+	/* SOCCLK */</div><div class='add'>+	dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,</div><div class='add'>+					&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].socclk_mhz,</div><div class='add'>+					&amp;num_entries_per_clk-&gt;num_socclk_levels);</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.socclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);</div><div class='add'>+	if (num_entries_per_clk-&gt;num_socclk_levels &amp;&amp; clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.socclk_mhz ==</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_socclk_levels - 1].socclk_mhz)</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.socclk_mhz = 0;</div><div class='add'>+</div><div class='add'>+	/* DTBCLK */</div><div class='add'>+	if (!clk_mgr-&gt;base.ctx-&gt;dc-&gt;debug.disable_dtb_ref_clk_switch) {</div><div class='add'>+		dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,</div><div class='add'>+				&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].dtbclk_mhz,</div><div class='add'>+				&amp;num_entries_per_clk-&gt;num_dtbclk_levels);</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dtbclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);</div><div class='add'>+		if (num_entries_per_clk-&gt;num_dtbclk_levels &amp;&amp; clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dtbclk_mhz ==</div><div class='add'>+				clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_dtbclk_levels - 1].dtbclk_mhz)</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dtbclk_mhz = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DISPCLK */</div><div class='add'>+	dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,</div><div class='add'>+			&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].dispclk_mhz,</div><div class='add'>+			&amp;num_entries_per_clk-&gt;num_dispclk_levels);</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dispclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);</div><div class='add'>+	if (num_entries_per_clk-&gt;num_dispclk_levels &amp;&amp; clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dispclk_mhz ==</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_dispclk_levels - 1].dispclk_mhz)</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dispclk_mhz = 0;</div><div class='add'>+</div><div class='add'>+	/* DPPCLK */</div><div class='add'>+	dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,</div><div class='add'>+			&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].dppclk_mhz,</div><div class='add'>+			&amp;num_entries_per_clk-&gt;num_dppclk_levels);</div><div class='add'>+</div><div class='add'>+	if (num_entries_per_clk-&gt;num_dcfclk_levels &amp;&amp;</div><div class='add'>+			num_entries_per_clk-&gt;num_dtbclk_levels &amp;&amp;</div><div class='add'>+			num_entries_per_clk-&gt;num_dispclk_levels)</div><div class='add'>+		clk_mgr-&gt;dpm_present = true;</div><div class='add'>+</div><div class='add'>+	if (clk_mgr_base-&gt;ctx-&gt;dc-&gt;debug.min_disp_clk_khz) {</div><div class='add'>+		for (i = 0; i &lt; num_entries_per_clk-&gt;num_dispclk_levels; i++)</div><div class='add'>+			if (clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[i].dispclk_mhz</div><div class='add'>+					&lt; khz_to_mhz_ceil(clk_mgr_base-&gt;ctx-&gt;dc-&gt;debug.min_disp_clk_khz))</div><div class='add'>+				clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[i].dispclk_mhz</div><div class='add'>+					= khz_to_mhz_ceil(clk_mgr_base-&gt;ctx-&gt;dc-&gt;debug.min_disp_clk_khz);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (clk_mgr_base-&gt;ctx-&gt;dc-&gt;debug.min_dpp_clk_khz) {</div><div class='add'>+		for (i = 0; i &lt; num_entries_per_clk-&gt;num_dppclk_levels; i++)</div><div class='add'>+			if (clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[i].dppclk_mhz</div><div class='add'>+					&lt; khz_to_mhz_ceil(clk_mgr_base-&gt;ctx-&gt;dc-&gt;debug.min_dpp_clk_khz))</div><div class='add'>+				clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[i].dppclk_mhz</div><div class='add'>+					= khz_to_mhz_ceil(clk_mgr_base-&gt;ctx-&gt;dc-&gt;debug.min_dpp_clk_khz);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Get UCLK, update bounding box */</div><div class='add'>+	clk_mgr_base-&gt;funcs-&gt;get_memclk_states_from_smu(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	/* WM range table */</div><div class='add'>+	dcn401_build_wm_range_table(clk_mgr_base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	return clk_mgr-&gt;smu_present &amp;&amp; clk_mgr-&gt;dpm_present &amp;&amp;</div><div class='add'>+			((clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_dcfclk_levels &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dcfclk_mhz) ||</div><div class='add'>+			(clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_dispclk_levels &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dispclk_mhz) ||</div><div class='add'>+			(clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_dtbclk_levels &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.dtbclk_mhz) ||</div><div class='add'>+			(clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.fclk_mhz) ||</div><div class='add'>+			(clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_memclk_levels &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.memclk_mhz) ||</div><div class='add'>+			(clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_socclk_levels &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.socclk_mhz));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='add'>+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)</div><div class='add'>+{</div><div class='add'>+		struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+		uint32_t dprefclk_did = 0;</div><div class='add'>+		uint32_t dcfclk_did = 0;</div><div class='add'>+		uint32_t dtbclk_did = 0;</div><div class='add'>+		uint32_t dispclk_did = 0;</div><div class='add'>+		uint32_t dppclk_did = 0;</div><div class='add'>+		uint32_t fclk_did = 0;</div><div class='add'>+		uint32_t target_div = 0;</div><div class='add'>+</div><div class='add'>+		/* DFS Slice 0 is used for DISPCLK */</div><div class='add'>+		dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);</div><div class='add'>+		/* DFS Slice 1 is used for DPPCLK */</div><div class='add'>+		dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);</div><div class='add'>+		/* DFS Slice 2 is used for DPREFCLK */</div><div class='add'>+		dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);</div><div class='add'>+		/* DFS Slice 3 is used for DCFCLK */</div><div class='add'>+		dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);</div><div class='add'>+		/* DFS Slice 4 is used for DTBCLK */</div><div class='add'>+		dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);</div><div class='add'>+		/* DFS Slice _ is used for FCLK */</div><div class='add'>+		fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);</div><div class='add'>+</div><div class='add'>+		/* Convert DISPCLK DFS Slice DID to divider*/</div><div class='add'>+		target_div = dentist_get_divider_from_did(dispclk_did);</div><div class='add'>+		//Get dispclk in khz</div><div class='add'>+		regs_and_bypass-&gt;dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+				* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+</div><div class='add'>+		/* Convert DISPCLK DFS Slice DID to divider*/</div><div class='add'>+		target_div = dentist_get_divider_from_did(dppclk_did);</div><div class='add'>+		//Get dppclk in khz</div><div class='add'>+		regs_and_bypass-&gt;dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+				* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+</div><div class='add'>+		/* Convert DPREFCLK DFS Slice DID to divider*/</div><div class='add'>+		target_div = dentist_get_divider_from_did(dprefclk_did);</div><div class='add'>+		//Get dprefclk in khz</div><div class='add'>+		regs_and_bypass-&gt;dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+				* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+</div><div class='add'>+		/* Convert DCFCLK DFS Slice DID to divider*/</div><div class='add'>+		target_div = dentist_get_divider_from_did(dcfclk_did);</div><div class='add'>+		//Get dcfclk in khz</div><div class='add'>+		regs_and_bypass-&gt;dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+				* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+</div><div class='add'>+		/* Convert DTBCLK DFS Slice DID to divider*/</div><div class='add'>+		target_div = dentist_get_divider_from_did(dtbclk_did);</div><div class='add'>+		//Get dtbclk in khz</div><div class='add'>+		regs_and_bypass-&gt;dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+				* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+</div><div class='add'>+		/* Convert DTBCLK DFS Slice DID to divider*/</div><div class='add'>+		target_div = dentist_get_divider_from_did(fclk_did);</div><div class='add'>+		//Get fclk in khz</div><div class='add'>+		regs_and_bypass-&gt;fclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+				* clk_mgr-&gt;base.dentist_vco_freq_khz) / target_div;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	bool is_native_scaling = false;</div><div class='add'>+	int width = pipe-&gt;plane_state-&gt;src_rect.width;</div><div class='add'>+	int height = pipe-&gt;plane_state-&gt;src_rect.height;</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;stream-&gt;timing.h_addressable == width &amp;&amp;</div><div class='add'>+			pipe-&gt;stream-&gt;timing.v_addressable == height &amp;&amp;</div><div class='add'>+			pipe-&gt;plane_state-&gt;dst_rect.width == width &amp;&amp;</div><div class='add'>+			pipe-&gt;plane_state-&gt;dst_rect.height == height)</div><div class='add'>+		is_native_scaling = true;</div><div class='add'>+</div><div class='add'>+	return is_native_scaling;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_auto_dpm_test_log(</div><div class='add'>+		struct dc_clocks *new_clocks,</div><div class='add'>+		struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	unsigned int mall_ss_size_bytes;</div><div class='add'>+	int dramclk_khz_override, fclk_khz_override, num_fclk_levels;</div><div class='add'>+</div><div class='add'>+	struct pipe_ctx *pipe_ctx_list[MAX_PIPES];</div><div class='add'>+	int active_pipe_count = 0;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {</div><div class='add'>+			pipe_ctx_list[active_pipe_count] = pipe_ctx;</div><div class='add'>+			active_pipe_count++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	msleep(5);</div><div class='add'>+</div><div class='add'>+	mall_ss_size_bytes = context-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes;</div><div class='add'>+</div><div class='add'>+	struct clk_log_info log_info = {0};</div><div class='add'>+	struct clk_state_registers_and_bypass clk_register_dump;</div><div class='add'>+</div><div class='add'>+	dcn401_dump_clk_registers(&amp;clk_register_dump, &amp;clk_mgr-&gt;base, &amp;log_info);</div><div class='add'>+</div><div class='add'>+	// Overrides for these clocks in case there is no p_state change support</div><div class='add'>+	dramclk_khz_override = new_clocks-&gt;dramclk_khz;</div><div class='add'>+	fclk_khz_override = new_clocks-&gt;fclk_khz;</div><div class='add'>+</div><div class='add'>+	num_fclk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels - 1;</div><div class='add'>+</div><div class='add'>+	if (!new_clocks-&gt;p_state_change_support)</div><div class='add'>+		dramclk_khz_override = clk_mgr-&gt;base.bw_params-&gt;max_memclk_mhz * 1000;</div><div class='add'>+</div><div class='add'>+	if (!new_clocks-&gt;fclk_p_state_change_support)</div><div class='add'>+		fclk_khz_override = clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_fclk_levels].fclk_mhz * 1000;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	////////////////////////////////////////////////////////////////////////////</div><div class='add'>+	//	IMPORTANT: 	When adding more clocks to these logs, do NOT put a newline</div><div class='add'>+	//	 			anywhere other than at the very end of the string.</div><div class='add'>+	//</div><div class='add'>+	//	Formatting example (make sure to have " - " between each entry):</div><div class='add'>+	//</div><div class='add'>+	//				AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"</div><div class='add'>+	////////////////////////////////////////////////////////////////////////////</div><div class='add'>+	if (active_pipe_count &gt; 0 &amp;&amp;</div><div class='add'>+		new_clocks-&gt;dramclk_khz &gt; 0 &amp;&amp;</div><div class='add'>+		new_clocks-&gt;fclk_khz &gt; 0 &amp;&amp;</div><div class='add'>+		new_clocks-&gt;dcfclk_khz &gt; 0 &amp;&amp;</div><div class='add'>+		new_clocks-&gt;dppclk_khz &gt; 0) {</div><div class='add'>+</div><div class='add'>+		uint32_t pix_clk_list[MAX_PIPES] = {0};</div><div class='add'>+		int p_state_list[MAX_PIPES] = {0};</div><div class='add'>+		int disp_src_width_list[MAX_PIPES] = {0};</div><div class='add'>+		int disp_src_height_list[MAX_PIPES] = {0};</div><div class='add'>+		uint64_t disp_src_refresh_list[MAX_PIPES] = {0};</div><div class='add'>+		bool is_scaled_list[MAX_PIPES] = {0};</div><div class='add'>+</div><div class='add'>+		for (int i = 0; i &lt; active_pipe_count; i++) {</div><div class='add'>+			struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];</div><div class='add'>+			uint64_t refresh_rate;</div><div class='add'>+</div><div class='add'>+			pix_clk_list[i] = curr_pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz;</div><div class='add'>+			p_state_list[i] = curr_pipe_ctx-&gt;p_state_type;</div><div class='add'>+</div><div class='add'>+			refresh_rate = (curr_pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='add'>+				curr_pipe_ctx-&gt;stream-&gt;timing.v_total</div><div class='add'>+				* (uint64_t) curr_pipe_ctx-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx-&gt;stream-&gt;timing.v_total);</div><div class='add'>+			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx-&gt;stream-&gt;timing.h_total);</div><div class='add'>+			disp_src_refresh_list[i] = refresh_rate;</div><div class='add'>+</div><div class='add'>+			if (curr_pipe_ctx-&gt;plane_state) {</div><div class='add'>+				is_scaled_list[i] = !(dcn401_check_native_scaling(curr_pipe_ctx));</div><div class='add'>+				disp_src_width_list[i] = curr_pipe_ctx-&gt;plane_state-&gt;src_rect.width;</div><div class='add'>+				disp_src_height_list[i] = curr_pipe_ctx-&gt;plane_state-&gt;src_rect.height;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "</div><div class='add'>+			"dcfclk:%d - dppclk:%d - dispclk_hw:%d - "</div><div class='add'>+			"dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "</div><div class='add'>+			"dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "</div><div class='add'>+			"pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "</div><div class='add'>+			"p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "</div><div class='add'>+			"pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "</div><div class='add'>+			"pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "</div><div class='add'>+			"pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "</div><div class='add'>+			"pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",</div><div class='add'>+			dramclk_khz_override,</div><div class='add'>+			fclk_khz_override,</div><div class='add'>+			new_clocks-&gt;dcfclk_khz,</div><div class='add'>+			new_clocks-&gt;dppclk_khz,</div><div class='add'>+			clk_register_dump.dispclk,</div><div class='add'>+			clk_register_dump.dppclk,</div><div class='add'>+			clk_register_dump.dprefclk,</div><div class='add'>+			clk_register_dump.dcfclk,</div><div class='add'>+			clk_register_dump.dtbclk,</div><div class='add'>+			clk_register_dump.fclk,</div><div class='add'>+			pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],</div><div class='add'>+			mall_ss_size_bytes,</div><div class='add'>+			p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],</div><div class='add'>+			disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],</div><div class='add'>+			disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],</div><div class='add'>+			disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],</div><div class='add'>+			disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			int ref_dtbclk_khz)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct dccg *dccg = clk_mgr-&gt;dccg;</div><div class='add'>+	struct pipe_ctx *otg_master;</div><div class='add'>+	bool use_hpo_encoder;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		otg_master = resource_get_otg_master_for_stream(</div><div class='add'>+				&amp;context-&gt;res_ctx, context-&gt;streams[i]);</div><div class='add'>+		ASSERT(otg_master);</div><div class='add'>+		ASSERT(otg_master-&gt;clock_source);</div><div class='add'>+		ASSERT(otg_master-&gt;clock_source-&gt;funcs-&gt;program_pix_clk);</div><div class='add'>+		ASSERT(otg_master-&gt;stream_res.pix_clk_params.controller_id &gt;= CONTROLLER_ID_D0);</div><div class='add'>+</div><div class='add'>+		use_hpo_encoder = dccg-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(otg_master);</div><div class='add'>+		if (!use_hpo_encoder)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (otg_master-&gt;stream_res.pix_clk_params.controller_id &gt; CONTROLLER_ID_UNDEFINED)</div><div class='add'>+			otg_master-&gt;clock_source-&gt;funcs-&gt;program_pix_clk(</div><div class='add'>+				otg_master-&gt;clock_source,</div><div class='add'>+				&amp;otg_master-&gt;stream_res.pix_clk_params,</div><div class='add'>+				dccg-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_get_encoding_format(</div><div class='add'>+					&amp;otg_master-&gt;link_config.dp_link_settings),</div><div class='add'>+				&amp;otg_master-&gt;pll_settings);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;dccg-&gt;ref_dppclk = ref_dppclk_khz;</div><div class='add'>+	for (i = 0; i &lt; clk_mgr-&gt;base.ctx-&gt;dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;</div><div class='add'>+</div><div class='add'>+		dppclk_khz = context-&gt;res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;</div><div class='add'>+</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].plane_res.dpp)</div><div class='add'>+			dpp_inst = context-&gt;res_ctx.pipe_ctx[i].plane_res.dpp-&gt;inst;</div><div class='add'>+		else if (!context-&gt;res_ctx.pipe_ctx[i].plane_res.dpp &amp;&amp; dppclk_khz == 0) {</div><div class='add'>+			/* dpp == NULL &amp;&amp; dppclk_khz == 0 is valid because of pipe harvesting.</div><div class='add'>+			 * In this case just continue in loop</div><div class='add'>+			 */</div><div class='add'>+			continue;</div><div class='add'>+		} else if (!context-&gt;res_ctx.pipe_ctx[i].plane_res.dpp &amp;&amp; dppclk_khz &gt; 0) {</div><div class='add'>+			/* The software state is not valid if dpp resource is NULL and</div><div class='add'>+			 * dppclk_khz &gt; 0.</div><div class='add'>+			 */</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		prev_dppclk_khz = clk_mgr-&gt;dccg-&gt;pipe_dppclk_khz[i];</div><div class='add'>+</div><div class='add'>+		if (safe_to_lower || prev_dppclk_khz &lt; dppclk_khz)</div><div class='add'>+			clk_mgr-&gt;dccg-&gt;funcs-&gt;update_dpp_dto(</div><div class='add'>+							clk_mgr-&gt;dccg, dpp_inst, dppclk_khz);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)</div><div class='add'>+{</div><div class='add'>+	if (!clk_mgr-&gt;smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * SMU set hard min interface takes requested clock in mhz and return</div><div class='add'>+	 * actual clock configured in khz. If we floor requested clk to mhz,</div><div class='add'>+	 * there is a chance that the actual clock configured in khz is less</div><div class='add'>+	 * than requested. If we ceil it to mhz, there is a chance that it</div><div class='add'>+	 * unnecessarily dumps up to a higher dpm level, which burns more power.</div><div class='add'>+	 * The solution is to set by flooring it to mhz first. If the actual</div><div class='add'>+	 * clock returned is less than requested, then we will ceil the</div><div class='add'>+	 * requested value to mhz and call it again.</div><div class='add'>+	 */</div><div class='add'>+	int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));</div><div class='add'>+</div><div class='add'>+	if (actual_clk_khz &lt; requested_clk_khz)</div><div class='add'>+		actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));</div><div class='add'>+</div><div class='add'>+	return actual_clk_khz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_update_clocks_update_dentist(</div><div class='add'>+		struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	uint32_t new_disp_divider = 0;</div><div class='add'>+	uint32_t new_dispclk_wdivider = 0;</div><div class='add'>+	uint32_t dentist_dispclk_wdivider_readback = 0;</div><div class='add'>+	struct dc *dc = clk_mgr-&gt;base.ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (clk_mgr-&gt;base.clks.dispclk_khz == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR</div><div class='add'>+			* clk_mgr-&gt;base.dentist_vco_freq_khz / clk_mgr-&gt;base.clks.dispclk_khz;</div><div class='add'>+</div><div class='add'>+	new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.override_dispclk_programming) {</div><div class='add'>+		REG_GET(DENTIST_DISPCLK_CNTL,</div><div class='add'>+				DENTIST_DISPCLK_WDIVIDER, &amp;dentist_dispclk_wdivider_readback);</div><div class='add'>+</div><div class='add'>+		if (dentist_dispclk_wdivider_readback &gt; new_dispclk_wdivider) {</div><div class='add'>+			REG_UPDATE(DENTIST_DISPCLK_CNTL,</div><div class='add'>+					DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);</div><div class='add'>+			REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+	union dcn401_clk_mgr_block_sequence_params *params;</div><div class='add'>+</div><div class='add'>+	/* execute sequence */</div><div class='add'>+	for (i = 0; i &lt; num_steps; i++) {</div><div class='add'>+		params = &amp;clk_mgr401-&gt;block_sequence[i].params;</div><div class='add'>+</div><div class='add'>+		switch (clk_mgr401-&gt;block_sequence[i].func) {</div><div class='add'>+		case CLK_MGR401_READ_CLOCKS_FROM_DENTIST:</div><div class='add'>+			dcn2_read_clocks_from_hw_dentist(clk_mgr_base);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_NUM_DISPLAYS:</div><div class='add'>+			dcn401_smu_set_num_of_displays(clk_mgr_internal,</div><div class='add'>+					params-&gt;update_num_displays_params.num_displays);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_HARDMIN_PPCLK:</div><div class='add'>+			if (params-&gt;update_hardmin_params.response)</div><div class='add'>+				*params-&gt;update_hardmin_params.response = dcn401_smu_set_hard_min_by_freq(</div><div class='add'>+						clk_mgr_internal,</div><div class='add'>+						params-&gt;update_hardmin_params.ppclk,</div><div class='add'>+						params-&gt;update_hardmin_params.freq_mhz);</div><div class='add'>+			else</div><div class='add'>+				dcn401_smu_set_hard_min_by_freq(clk_mgr_internal,</div><div class='add'>+						params-&gt;update_hardmin_params.ppclk,</div><div class='add'>+						params-&gt;update_hardmin_params.freq_mhz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED:</div><div class='add'>+			if (params-&gt;update_hardmin_optimized_params.response)</div><div class='add'>+				*params-&gt;update_hardmin_optimized_params.response = dcn401_set_hard_min_by_freq_optimized(</div><div class='add'>+						clk_mgr_internal,</div><div class='add'>+						params-&gt;update_hardmin_optimized_params.ppclk,</div><div class='add'>+						params-&gt;update_hardmin_optimized_params.freq_khz);</div><div class='add'>+			else</div><div class='add'>+				dcn401_set_hard_min_by_freq_optimized(clk_mgr_internal,</div><div class='add'>+						params-&gt;update_hardmin_optimized_params.ppclk,</div><div class='add'>+						params-&gt;update_hardmin_optimized_params.freq_khz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_ACTIVE_HARDMINS:</div><div class='add'>+			dcn401_smu_set_active_uclk_fclk_hardmin(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_idle_hardmin_params.uclk_mhz,</div><div class='add'>+					params-&gt;update_idle_hardmin_params.fclk_mhz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_IDLE_HARDMINS:</div><div class='add'>+			dcn401_smu_set_idle_uclk_fclk_hardmin(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_idle_hardmin_params.uclk_mhz,</div><div class='add'>+					params-&gt;update_idle_hardmin_params.fclk_mhz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_SUBVP_HARDMINS:</div><div class='add'>+			dcn401_smu_set_subvp_uclk_fclk_hardmin(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_idle_hardmin_params.uclk_mhz,</div><div class='add'>+					params-&gt;update_idle_hardmin_params.fclk_mhz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK:</div><div class='add'>+			dcn401_smu_set_min_deep_sleep_dcef_clk(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_deep_sleep_dcfclk_params.freq_mhz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT:</div><div class='add'>+			dcn401_smu_send_fclk_pstate_message(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_pstate_support_params.support);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT:</div><div class='add'>+			dcn401_smu_send_uclk_pstate_message(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_pstate_support_params.support);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_CAB_FOR_UCLK:</div><div class='add'>+			dcn401_smu_send_cab_for_uclk_message(</div><div class='add'>+				clk_mgr_internal,</div><div class='add'>+				params-&gt;update_cab_for_uclk_params.num_ways);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK:</div><div class='add'>+			dcn401_smu_wait_for_dmub_ack_mclk(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_wait_for_dmub_ack_params.enable);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_INDICATE_DRR_STATUS:</div><div class='add'>+			dcn401_smu_indicate_drr_status(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;indicate_drr_status_params.mod_drr_for_pstate);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_DPPCLK_DTO:</div><div class='add'>+			dcn401_update_clocks_update_dpp_dto(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_dppclk_dto_params.context,</div><div class='add'>+					params-&gt;update_dppclk_dto_params.safe_to_lower,</div><div class='add'>+					*params-&gt;update_dppclk_dto_params.ref_dppclk_khz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_DTBCLK_DTO:</div><div class='add'>+			dcn401_update_clocks_update_dtb_dto(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_dtbclk_dto_params.context,</div><div class='add'>+					*params-&gt;update_dtbclk_dto_params.ref_dtbclk_khz);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_DENTIST:</div><div class='add'>+			dcn401_update_clocks_update_dentist(</div><div class='add'>+					clk_mgr_internal,</div><div class='add'>+					params-&gt;update_dentist_params.context);</div><div class='add'>+			break;</div><div class='add'>+		case CLK_MGR401_UPDATE_PSR_WAIT_LOOP:</div><div class='add'>+			params-&gt;update_psr_wait_loop_params.dmcu-&gt;funcs-&gt;set_psr_wait_loop(</div><div class='add'>+					params-&gt;update_psr_wait_loop_params.dmcu,</div><div class='add'>+					params-&gt;update_psr_wait_loop_params.wait);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			/* this should never happen */</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dcn401_build_update_bandwidth_clocks_sequence(</div><div class='add'>+		struct clk_mgr *clk_mgr_base,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dc_clocks *new_clocks,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);</div><div class='add'>+	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401-&gt;block_sequence;</div><div class='add'>+	bool enter_display_off = false;</div><div class='add'>+	bool update_active_fclk = false;</div><div class='add'>+	bool update_active_uclk = false;</div><div class='add'>+	bool update_idle_fclk = false;</div><div class='add'>+	bool update_idle_uclk = false;</div><div class='add'>+	bool update_subvp_prefetch_dramclk = false;</div><div class='add'>+	bool update_subvp_prefetch_fclk = false;</div><div class='add'>+	bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &amp;&amp;</div><div class='add'>+			dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &amp;&amp;</div><div class='add'>+			dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &amp;&amp;</div><div class='add'>+			dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);</div><div class='add'>+	bool is_df_throttle_opt_enabled = is_idle_dpm_enabled &amp;&amp;</div><div class='add'>+		dcn401_is_df_throttle_opt_enabled(clk_mgr_internal);</div><div class='add'>+	int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);</div><div class='add'>+	int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.dramclk_khz);</div><div class='add'>+	int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.fclk_khz);</div><div class='add'>+	int idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.idle_dramclk_khz);</div><div class='add'>+	int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.idle_fclk_khz);</div><div class='add'>+	int subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.subvp_prefetch_dramclk_khz);</div><div class='add'>+	int subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.subvp_prefetch_fclk_khz);</div><div class='add'>+</div><div class='add'>+	unsigned int num_steps = 0;</div><div class='add'>+</div><div class='add'>+	int display_count;</div><div class='add'>+	bool fclk_p_state_change_support, uclk_p_state_change_support;</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_NUM_DISPLAYS */</div><div class='add'>+	if (clk_mgr_internal-&gt;smu_present) {</div><div class='add'>+		display_count = clk_mgr_helper_get_active_display_cnt(dc, context);</div><div class='add'>+</div><div class='add'>+		if (display_count == 0)</div><div class='add'>+			enter_display_off = true;</div><div class='add'>+</div><div class='add'>+		if (enter_display_off == safe_to_lower) {</div><div class='add'>+			block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT */</div><div class='add'>+	clk_mgr_base-&gt;clks.fclk_prev_p_state_change_support = clk_mgr_base-&gt;clks.fclk_p_state_change_support;</div><div class='add'>+	fclk_p_state_change_support = new_clocks-&gt;fclk_p_state_change_support || (total_plane_count == 0);</div><div class='add'>+	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base-&gt;clks.fclk_prev_p_state_change_support)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.fclk_p_state_change_support = fclk_p_state_change_support;</div><div class='add'>+		update_active_fclk = true;</div><div class='add'>+		update_idle_fclk = true;</div><div class='add'>+</div><div class='add'>+		/* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW (message not supported on DCN401)*/</div><div class='add'>+		// if (clk_mgr_base-&gt;clks.fclk_p_state_change_support) {</div><div class='add'>+		// 	/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */</div><div class='add'>+		// 	if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {</div><div class='add'>+		// 		block_sequence[num_steps].params.update_pstate_support_params.support = true;</div><div class='add'>+		// 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;</div><div class='add'>+		// 		num_steps++;</div><div class='add'>+		// 	}</div><div class='add'>+		// }</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr_base-&gt;clks.fclk_p_state_change_support &amp;&amp; dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {</div><div class='add'>+		/* when P-State switching disabled, set UCLK min = max */</div><div class='add'>+		idle_fclk_mhz =</div><div class='add'>+				clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;</div><div class='add'>+		active_fclk_mhz = idle_fclk_mhz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* UPDATE DCFCLK */</div><div class='add'>+	if (dc-&gt;debug.force_min_dcfclk_mhz &gt; 0)</div><div class='add'>+		new_clocks-&gt;dcfclk_khz = (new_clocks-&gt;dcfclk_khz &gt; (dc-&gt;debug.force_min_dcfclk_mhz * 1000)) ?</div><div class='add'>+				new_clocks-&gt;dcfclk_khz : (dc-&gt;debug.force_min_dcfclk_mhz * 1000);</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dcfclk_khz, clk_mgr_base-&gt;clks.dcfclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.dcfclk_khz = new_clocks-&gt;dcfclk_khz;</div><div class='add'>+		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {</div><div class='add'>+			block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;</div><div class='add'>+			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.dcfclk_khz);</div><div class='add'>+			block_sequence[num_steps].params.update_hardmin_params.response = NULL;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK */</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dcfclk_deep_sleep_khz, clk_mgr_base-&gt;clks.dcfclk_deep_sleep_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.dcfclk_deep_sleep_khz = new_clocks-&gt;dcfclk_deep_sleep_khz;</div><div class='add'>+		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {</div><div class='add'>+			block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.dcfclk_deep_sleep_khz);</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* SOCCLK */</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;socclk_khz, clk_mgr_base-&gt;clks.socclk_khz))</div><div class='add'>+		/* We don't actually care about socclk, don't notify SMU of hard min */</div><div class='add'>+		clk_mgr_base-&gt;clks.socclk_khz = new_clocks-&gt;socclk_khz;</div><div class='add'>+</div><div class='add'>+	/* UCLK */</div><div class='add'>+	if (new_clocks-&gt;fw_based_mclk_switching != clk_mgr_base-&gt;clks.fw_based_mclk_switching &amp;&amp;</div><div class='add'>+			new_clocks-&gt;fw_based_mclk_switching) {</div><div class='add'>+		/* enable FAMS features */</div><div class='add'>+		clk_mgr_base-&gt;clks.fw_based_mclk_switching = new_clocks-&gt;fw_based_mclk_switching;</div><div class='add'>+</div><div class='add'>+		block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base-&gt;clks.fw_based_mclk_switching;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;</div><div class='add'>+		num_steps++;</div><div class='add'>+</div><div class='add'>+		block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base-&gt;clks.fw_based_mclk_switching;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_CAB_FOR_UCLK */</div><div class='add'>+	clk_mgr_base-&gt;clks.prev_num_ways = clk_mgr_base-&gt;clks.num_ways;</div><div class='add'>+	if (clk_mgr_base-&gt;clks.num_ways != new_clocks-&gt;num_ways &amp;&amp;</div><div class='add'>+			clk_mgr_base-&gt;clks.num_ways &lt; new_clocks-&gt;num_ways) {</div><div class='add'>+		/* increase num ways for subvp */</div><div class='add'>+		clk_mgr_base-&gt;clks.num_ways = new_clocks-&gt;num_ways;</div><div class='add'>+		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {</div><div class='add'>+			block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base-&gt;clks.num_ways;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	clk_mgr_base-&gt;clks.prev_p_state_change_support = clk_mgr_base-&gt;clks.p_state_change_support;</div><div class='add'>+	uclk_p_state_change_support = new_clocks-&gt;p_state_change_support || (total_plane_count == 0);</div><div class='add'>+	if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base-&gt;clks.prev_p_state_change_support)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.p_state_change_support = uclk_p_state_change_support;</div><div class='add'>+		update_active_uclk = true;</div><div class='add'>+		update_idle_uclk = true;</div><div class='add'>+</div><div class='add'>+		if (clk_mgr_base-&gt;clks.p_state_change_support) {</div><div class='add'>+			/* enable UCLK switching  */</div><div class='add'>+			if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {</div><div class='add'>+				block_sequence[num_steps].params.update_pstate_support_params.support = true;</div><div class='add'>+				block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;</div><div class='add'>+				num_steps++;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr_base-&gt;clks.p_state_change_support &amp;&amp; dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {</div><div class='add'>+		/* when P-State switching disabled, set UCLK min = max */</div><div class='add'>+		if (dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled) {</div><div class='add'>+			/* will never have the functional UCLK min above the softmax</div><div class='add'>+			* since we calculate mode support based on softmax being the max UCLK</div><div class='add'>+			* frequency.</div><div class='add'>+			*/</div><div class='add'>+			active_uclk_mhz = clk_mgr_base-&gt;bw_params-&gt;dc_mode_softmax_memclk;</div><div class='add'>+		} else {</div><div class='add'>+			active_uclk_mhz = clk_mgr_base-&gt;bw_params-&gt;max_memclk_mhz;</div><div class='add'>+		}</div><div class='add'>+		idle_uclk_mhz = active_uclk_mhz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Always update saved value, even if new value not set due to P-State switching unsupported */</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dramclk_khz, clk_mgr_base-&gt;clks.dramclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.dramclk_khz = new_clocks-&gt;dramclk_khz;</div><div class='add'>+</div><div class='add'>+		if (clk_mgr_base-&gt;clks.p_state_change_support) {</div><div class='add'>+			update_active_uclk = true;</div><div class='add'>+			active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.dramclk_khz);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;idle_dramclk_khz, clk_mgr_base-&gt;clks.idle_dramclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.idle_dramclk_khz = new_clocks-&gt;idle_dramclk_khz;</div><div class='add'>+</div><div class='add'>+		if (clk_mgr_base-&gt;clks.p_state_change_support) {</div><div class='add'>+			update_idle_uclk = true;</div><div class='add'>+			idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.idle_dramclk_khz);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;subvp_prefetch_dramclk_khz, clk_mgr_base-&gt;clks.subvp_prefetch_dramclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.subvp_prefetch_dramclk_khz = new_clocks-&gt;subvp_prefetch_dramclk_khz;</div><div class='add'>+		update_subvp_prefetch_dramclk = true;</div><div class='add'>+		subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.subvp_prefetch_dramclk_khz);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* FCLK */</div><div class='add'>+	/* Always update saved value, even if new value not set due to P-State switching unsupported */</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;fclk_khz, clk_mgr_base-&gt;clks.fclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.fclk_khz = new_clocks-&gt;fclk_khz;</div><div class='add'>+</div><div class='add'>+		if (clk_mgr_base-&gt;clks.fclk_p_state_change_support) {</div><div class='add'>+			update_active_fclk = true;</div><div class='add'>+			active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.fclk_khz);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;idle_fclk_khz, clk_mgr_base-&gt;clks.idle_fclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.idle_fclk_khz = new_clocks-&gt;idle_fclk_khz;</div><div class='add'>+</div><div class='add'>+		if (clk_mgr_base-&gt;clks.fclk_p_state_change_support) {</div><div class='add'>+			update_idle_fclk = true;</div><div class='add'>+			idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.idle_fclk_khz);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;subvp_prefetch_fclk_khz, clk_mgr_base-&gt;clks.subvp_prefetch_fclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.subvp_prefetch_fclk_khz = new_clocks-&gt;subvp_prefetch_fclk_khz;</div><div class='add'>+		update_subvp_prefetch_fclk = true;</div><div class='add'>+		subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base-&gt;clks.subvp_prefetch_fclk_khz);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* When idle DPM is enabled, need to send active and idle hardmins separately */</div><div class='add'>+	/* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */</div><div class='add'>+	if ((update_active_uclk || update_active_fclk) &amp;&amp; is_idle_dpm_enabled) {</div><div class='add'>+		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;</div><div class='add'>+		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_IDLE_HARDMINS */</div><div class='add'>+	if ((update_idle_uclk || update_idle_fclk) &amp;&amp; is_idle_dpm_enabled) {</div><div class='add'>+		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;</div><div class='add'>+		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_SUBVP_HARDMINS */</div><div class='add'>+	if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) &amp;&amp; is_df_throttle_opt_enabled) {</div><div class='add'>+		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;</div><div class='add'>+		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */</div><div class='add'>+	if (update_active_uclk || update_idle_uclk) {</div><div class='add'>+		if (!is_idle_dpm_enabled) {</div><div class='add'>+			block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;</div><div class='add'>+			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;</div><div class='add'>+			block_sequence[num_steps].params.update_hardmin_params.response = NULL;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* disable UCLK P-State support if needed */</div><div class='add'>+		if (!uclk_p_state_change_support &amp;&amp;</div><div class='add'>+				should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base-&gt;clks.prev_p_state_change_support) &amp;&amp;</div><div class='add'>+				dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {</div><div class='add'>+			block_sequence[num_steps].params.update_pstate_support_params.support = false;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* set FCLK to requested value if P-State switching is supported, or to re-enable P-State switching */</div><div class='add'>+	if (update_active_fclk || update_idle_fclk) {</div><div class='add'>+		/* No need to send active FCLK hardmin, automatically set based on DCFCLK */</div><div class='add'>+		// if (!is_idle_dpm_enabled) {</div><div class='add'>+		// 	block_sequence[*num_steps].update_hardmin_params.clk_mgr = clk_mgr;</div><div class='add'>+		// 	block_sequence[*num_steps].update_hardmin_params.ppclk = PPCLK_FCLK;</div><div class='add'>+		// 	block_sequence[*num_steps].update_hardmin_params.freq_mhz = active_fclk_mhz;</div><div class='add'>+		// 	block_sequence[*num_steps].update_hardmin_params.response = NULL;</div><div class='add'>+		// 	block_sequence[*num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;</div><div class='add'>+		// 	(*num_steps)++;</div><div class='add'>+		// }</div><div class='add'>+</div><div class='add'>+		/* disable FCLK P-State support if needed (message not supported on DCN401)*/</div><div class='add'>+		// if (!fclk_p_state_change_support &amp;&amp;</div><div class='add'>+		// 		should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base-&gt;clks.fclk_prev_p_state_change_support) &amp;&amp;</div><div class='add'>+		// 		dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {</div><div class='add'>+		// 	block_sequence[num_steps].params.update_pstate_support_params.support = false;</div><div class='add'>+		// 	block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;</div><div class='add'>+		// 	num_steps++;</div><div class='add'>+		// }</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (new_clocks-&gt;fw_based_mclk_switching != clk_mgr_base-&gt;clks.fw_based_mclk_switching &amp;&amp;</div><div class='add'>+			safe_to_lower &amp;&amp; !new_clocks-&gt;fw_based_mclk_switching) {</div><div class='add'>+		/* disable FAMS features */</div><div class='add'>+		clk_mgr_base-&gt;clks.fw_based_mclk_switching = new_clocks-&gt;fw_based_mclk_switching;</div><div class='add'>+</div><div class='add'>+		block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base-&gt;clks.fw_based_mclk_switching;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;</div><div class='add'>+		num_steps++;</div><div class='add'>+</div><div class='add'>+		block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base-&gt;clks.fw_based_mclk_switching;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_UPDATE_CAB_FOR_UCLK */</div><div class='add'>+	if (clk_mgr_base-&gt;clks.num_ways != new_clocks-&gt;num_ways &amp;&amp;</div><div class='add'>+			safe_to_lower &amp;&amp; clk_mgr_base-&gt;clks.num_ways &gt; new_clocks-&gt;num_ways) {</div><div class='add'>+		/* decrease num ways for subvp */</div><div class='add'>+		clk_mgr_base-&gt;clks.num_ways = new_clocks-&gt;num_ways;</div><div class='add'>+		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {</div><div class='add'>+			block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base-&gt;clks.num_ways;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return num_steps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dcn401_build_update_display_clocks_sequence(</div><div class='add'>+		struct clk_mgr *clk_mgr_base,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dc_clocks *new_clocks,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);</div><div class='add'>+	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dmcu *dmcu = clk_mgr_base-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dmcu;</div><div class='add'>+	struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401-&gt;block_sequence;</div><div class='add'>+	bool force_reset = false;</div><div class='add'>+	bool update_dispclk = false;</div><div class='add'>+	bool update_dppclk = false;</div><div class='add'>+	bool dppclk_lowered = false;</div><div class='add'>+</div><div class='add'>+	unsigned int num_steps = 0;</div><div class='add'>+</div><div class='add'>+	/* CLK_MGR401_READ_CLOCKS_FROM_DENTIST */</div><div class='add'>+	if (clk_mgr_base-&gt;clks.dispclk_khz == 0 ||</div><div class='add'>+			(dc-&gt;debug.force_clock_mode &amp; 0x1)) {</div><div class='add'>+		/* This is from resume or boot up, if forced_clock cfg option used,</div><div class='add'>+		 * we bypass program dispclk and DPPCLK, but need set them for S3.</div><div class='add'>+		 * Force_clock_mode 0x1:  force reset the clock even it is the same clock</div><div class='add'>+		 * as long as it is in Passive level.</div><div class='add'>+		 */</div><div class='add'>+		force_reset = true;</div><div class='add'>+</div><div class='add'>+		clk_mgr_base-&gt;clks.dispclk_khz = clk_mgr_base-&gt;boot_snapshot.dispclk;</div><div class='add'>+		clk_mgr_base-&gt;clks.actual_dispclk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='add'>+</div><div class='add'>+		clk_mgr_base-&gt;clks.dppclk_khz = clk_mgr_base-&gt;boot_snapshot.dppclk;</div><div class='add'>+		clk_mgr_base-&gt;clks.actual_dppclk_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DTBCLK */</div><div class='add'>+	if (!new_clocks-&gt;dtbclk_en &amp;&amp; dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {</div><div class='add'>+		new_clocks-&gt;ref_dtbclk_khz = clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].dtbclk_mhz * 1000;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */</div><div class='add'>+	if (!dc-&gt;debug.disable_dtb_ref_clk_switch &amp;&amp;</div><div class='add'>+			should_set_clock(safe_to_lower, new_clocks-&gt;ref_dtbclk_khz / 1000, clk_mgr_base-&gt;clks.ref_dtbclk_khz / 1000) &amp;&amp; //TODO these should be ceiled</div><div class='add'>+			dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {</div><div class='add'>+		/* DCCG requires KHz precision for DTBCLK */</div><div class='add'>+		block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;</div><div class='add'>+		block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks-&gt;ref_dtbclk_khz);</div><div class='add'>+		block_sequence[num_steps].params.update_hardmin_params.response = &amp;clk_mgr_base-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;</div><div class='add'>+		num_steps++;</div><div class='add'>+</div><div class='add'>+		/* Update DTO in DCCG */</div><div class='add'>+		block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;</div><div class='add'>+		block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &amp;clk_mgr_base-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dppclk_khz, clk_mgr_base-&gt;clks.dppclk_khz)) {</div><div class='add'>+		if (clk_mgr_base-&gt;clks.dppclk_khz &gt; new_clocks-&gt;dppclk_khz)</div><div class='add'>+			dppclk_lowered = true;</div><div class='add'>+</div><div class='add'>+		clk_mgr_base-&gt;clks.dppclk_khz = new_clocks-&gt;dppclk_khz;</div><div class='add'>+		clk_mgr_base-&gt;clks.actual_dppclk_khz = new_clocks-&gt;dppclk_khz;</div><div class='add'>+</div><div class='add'>+		update_dppclk = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz)) {</div><div class='add'>+		clk_mgr_base-&gt;clks.dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='add'>+</div><div class='add'>+		block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;</div><div class='add'>+		block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='add'>+		block_sequence[num_steps].params.update_hardmin_optimized_params.response = &amp;clk_mgr_base-&gt;clks.actual_dispclk_khz;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;</div><div class='add'>+		num_steps++;</div><div class='add'>+</div><div class='add'>+		update_dispclk = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;config.forced_clocks == false || (force_reset &amp;&amp; safe_to_lower)) {</div><div class='add'>+		if (dppclk_lowered) {</div><div class='add'>+			/* if clock is being lowered, increase DTO before lowering refclk */</div><div class='add'>+			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;</div><div class='add'>+			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &amp;clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='add'>+			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;</div><div class='add'>+			num_steps++;</div><div class='add'>+</div><div class='add'>+			block_sequence[num_steps].params.update_dentist_params.context = context;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;</div><div class='add'>+			num_steps++;</div><div class='add'>+</div><div class='add'>+			if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {</div><div class='add'>+				block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;</div><div class='add'>+				block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='add'>+				block_sequence[num_steps].params.update_hardmin_optimized_params.response = &amp;clk_mgr_base-&gt;clks.actual_dppclk_khz;</div><div class='add'>+				block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;</div><div class='add'>+				num_steps++;</div><div class='add'>+</div><div class='add'>+				block_sequence[num_steps].params.update_dppclk_dto_params.context = context;</div><div class='add'>+				block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &amp;clk_mgr_base-&gt;clks.actual_dppclk_khz;</div><div class='add'>+				block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;</div><div class='add'>+				block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;</div><div class='add'>+				num_steps++;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* if clock is being raised, increase refclk before lowering DTO */</div><div class='add'>+			if (update_dppclk &amp;&amp; dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {</div><div class='add'>+				block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;</div><div class='add'>+				block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='add'>+				block_sequence[num_steps].params.update_hardmin_optimized_params.response = &amp;clk_mgr_base-&gt;clks.actual_dppclk_khz;</div><div class='add'>+				block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;</div><div class='add'>+				num_steps++;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (update_dppclk || update_dispclk) {</div><div class='add'>+				block_sequence[num_steps].params.update_dentist_params.context = context;</div><div class='add'>+				block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;</div><div class='add'>+				num_steps++;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;</div><div class='add'>+			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &amp;clk_mgr_base-&gt;clks.actual_dppclk_khz;</div><div class='add'>+			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;</div><div class='add'>+			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;</div><div class='add'>+			num_steps++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (update_dispclk &amp;&amp; dmcu &amp;&amp; dmcu-&gt;funcs-&gt;is_dmcu_initialized(dmcu)) {</div><div class='add'>+		/*update dmcu for wait_loop count*/</div><div class='add'>+		block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;</div><div class='add'>+		block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base-&gt;clks.dispclk_khz / 1000 / 7;</div><div class='add'>+		block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;</div><div class='add'>+		num_steps++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return num_steps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	unsigned int num_steps = 0;</div><div class='add'>+</div><div class='add'>+	/* build bandwidth related clocks update sequence */</div><div class='add'>+	num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,</div><div class='add'>+			context,</div><div class='add'>+			&amp;context-&gt;bw_ctx.bw.dcn.clk,</div><div class='add'>+			safe_to_lower);</div><div class='add'>+</div><div class='add'>+	/* execute sequence */</div><div class='add'>+	dcn401_execute_block_sequence(clk_mgr_base,	num_steps);</div><div class='add'>+</div><div class='add'>+	/* build display related clocks update sequence */</div><div class='add'>+	num_steps = dcn401_build_update_display_clocks_sequence(clk_mgr_base,</div><div class='add'>+			context,</div><div class='add'>+			&amp;context-&gt;bw_ctx.bw.dcn.clk,</div><div class='add'>+			safe_to_lower);</div><div class='add'>+</div><div class='add'>+	/* execute sequence */</div><div class='add'>+	dcn401_execute_block_sequence(clk_mgr_base,	num_steps);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;config.enable_auto_dpm_test_logs)</div><div class='add'>+		dcn401_auto_dpm_test_log(&amp;context-&gt;bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+		struct fixed31_32 pll_req;</div><div class='add'>+		uint32_t pll_req_reg = 0;</div><div class='add'>+</div><div class='add'>+		/* get FbMult value */</div><div class='add'>+		pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);</div><div class='add'>+</div><div class='add'>+		/* set up a fixed-point number</div><div class='add'>+		 * this works because the int part is on the right edge of the register</div><div class='add'>+		 * and the frac part is on the left edge</div><div class='add'>+		 */</div><div class='add'>+		pll_req = dc_fixpt_from_int(pll_req_reg &amp; clk_mgr-&gt;clk_mgr_mask-&gt;FbMult_int);</div><div class='add'>+		pll_req.value |= pll_req_reg &amp; clk_mgr-&gt;clk_mgr_mask-&gt;FbMult_frac;</div><div class='add'>+</div><div class='add'>+		/* multiply by REFCLK period */</div><div class='add'>+		pll_req = dc_fixpt_mul_int(pll_req, clk_mgr-&gt;dfs_ref_freq_khz);</div><div class='add'>+</div><div class='add'>+		return dc_fixpt_floor(pll_req);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	struct dc_bios *bp = clk_mgr-&gt;base.ctx-&gt;dc_bios;</div><div class='add'>+	int ss_info_num = bp-&gt;funcs-&gt;get_ss_entry_number(</div><div class='add'>+			bp, AS_SIGNAL_TYPE_GPU_PLL);</div><div class='add'>+</div><div class='add'>+	if (ss_info_num) {</div><div class='add'>+		struct spread_spectrum_info info = { { 0 } };</div><div class='add'>+		enum bp_result result = bp-&gt;funcs-&gt;get_spread_spectrum_info(</div><div class='add'>+				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &amp;info);</div><div class='add'>+</div><div class='add'>+		/* SSInfo.spreadSpectrumPercentage !=0 would be sign</div><div class='add'>+		 * that SS is enabled</div><div class='add'>+		 */</div><div class='add'>+		if (result == BP_RESULT_OK &amp;&amp;</div><div class='add'>+				info.spread_spectrum_percentage != 0) {</div><div class='add'>+			clk_mgr-&gt;ss_on_dprefclk = true;</div><div class='add'>+			clk_mgr-&gt;dprefclk_ss_divider = info.spread_percentage_divider;</div><div class='add'>+</div><div class='add'>+			if (info.type.CENTER_MODE == 0) {</div><div class='add'>+				/* Currently for DP Reference clock we</div><div class='add'>+				 * need only SS percentage for</div><div class='add'>+				 * downspread</div><div class='add'>+				 */</div><div class='add'>+				clk_mgr-&gt;dprefclk_ss_percentage =</div><div class='add'>+						info.spread_spectrum_percentage;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr-&gt;wm_range_table;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr-&gt;smu_present)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!table)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(table, 0, sizeof(*table));</div><div class='add'>+</div><div class='add'>+	/* collect valid ranges, place in pmfw table */</div><div class='add'>+	for (i = 0; i &lt; WM_SET_COUNT; i++)</div><div class='add'>+		if (clk_mgr-&gt;base.bw_params-&gt;wm_table.nv_entries[i].valid) {</div><div class='add'>+			table-&gt;Watermarks.WatermarkRow[i].WmSetting = i;</div><div class='add'>+			table-&gt;Watermarks.WatermarkRow[i].Flags = clk_mgr-&gt;base.bw_params-&gt;wm_table.nv_entries[i].pmfw_breakdown.wm_type;</div><div class='add'>+		}</div><div class='add'>+	dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr-&gt;wm_range_table_addr &gt;&gt; 32);</div><div class='add'>+	dcn401_smu_set_dram_addr_low(clk_mgr, clk_mgr-&gt;wm_range_table_addr &amp; 0xFFFFFFFF);</div><div class='add'>+	dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Set min memclk to minimum, either constrained by the current mode or DPM0 */</div><div class='add'>+static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	const struct dc *dc = clk_mgr-&gt;base.ctx-&gt;dc;</div><div class='add'>+	struct dc_state *context = dc-&gt;current_state;</div><div class='add'>+	struct dc_clocks new_clocks;</div><div class='add'>+	int num_steps;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr-&gt;smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* build clock update */</div><div class='add'>+	memcpy(&amp;new_clocks, &amp;clk_mgr_base-&gt;clks, sizeof(struct dc_clocks));</div><div class='add'>+</div><div class='add'>+	if (current_mode) {</div><div class='add'>+		new_clocks.dramclk_khz = context-&gt;bw_ctx.bw.dcn.clk.dramclk_khz;</div><div class='add'>+		new_clocks.idle_dramclk_khz = context-&gt;bw_ctx.bw.dcn.clk.idle_dramclk_khz;</div><div class='add'>+		new_clocks.p_state_change_support = context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='add'>+	} else {</div><div class='add'>+		new_clocks.dramclk_khz = clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].memclk_mhz * 1000;</div><div class='add'>+		new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz;</div><div class='add'>+		new_clocks.p_state_change_support = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,</div><div class='add'>+			context,</div><div class='add'>+			&amp;new_clocks,</div><div class='add'>+			true);</div><div class='add'>+</div><div class='add'>+	/* execute sequence */</div><div class='add'>+	dcn401_execute_block_sequence(clk_mgr_base,	num_steps);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcn401_get_hard_min_memclk(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	return clk_mgr-&gt;base.ctx-&gt;dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk.dramclk_khz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcn401_get_hard_min_fclk(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	return clk_mgr-&gt;base.ctx-&gt;dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk.fclk_khz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Get current memclk states, update bounding box */</div><div class='add'>+static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	struct clk_limit_num_entries *num_entries_per_clk = &amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries_per_clk;</div><div class='add'>+	unsigned int num_levels;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr-&gt;smu_present)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Refresh memclk and fclk states */</div><div class='add'>+	dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,</div><div class='add'>+			&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].memclk_mhz,</div><div class='add'>+			&amp;num_entries_per_clk-&gt;num_memclk_levels);</div><div class='add'>+	if (num_entries_per_clk-&gt;num_memclk_levels) {</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;max_memclk_mhz =</div><div class='add'>+				clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_memclk_levels - 1].memclk_mhz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.memclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);</div><div class='add'>+	if (num_entries_per_clk-&gt;num_memclk_levels &amp;&amp; clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.memclk_mhz ==</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_memclk_levels - 1].memclk_mhz)</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.memclk_mhz = 0;</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;dc_mode_softmax_memclk = clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.memclk_mhz;</div><div class='add'>+</div><div class='add'>+	dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,</div><div class='add'>+			&amp;clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[0].fclk_mhz,</div><div class='add'>+			&amp;num_entries_per_clk-&gt;num_fclk_levels);</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.fclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);</div><div class='add'>+	if (num_entries_per_clk-&gt;num_fclk_levels &amp;&amp; clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.fclk_mhz ==</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;clk_table.entries[num_entries_per_clk-&gt;num_fclk_levels - 1].fclk_mhz)</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dc_mode_limit.fclk_mhz = 0;</div><div class='add'>+</div><div class='add'>+	num_levels = max(num_entries_per_clk-&gt;num_memclk_levels, num_entries_per_clk-&gt;num_fclk_levels);</div><div class='add'>+</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;clk_table.num_entries = num_levels ? num_levels : 1;</div><div class='add'>+</div><div class='add'>+	if (clk_mgr-&gt;dpm_present &amp;&amp; !num_levels)</div><div class='add'>+		clk_mgr-&gt;dpm_present = false;</div><div class='add'>+</div><div class='add'>+	clk_mgr_base-&gt;bw_params-&gt;num_channels = dcn401_smu_get_num_of_umc_channels(clk_mgr);</div><div class='add'>+	if (clk_mgr_base-&gt;ctx-&gt;dc_bios) {</div><div class='add'>+		/* use BIOS values if none provided by PMFW */</div><div class='add'>+		if (clk_mgr_base-&gt;bw_params-&gt;num_channels == 0) {</div><div class='add'>+			clk_mgr_base-&gt;bw_params-&gt;num_channels = clk_mgr_base-&gt;ctx-&gt;dc_bios-&gt;vram_info.num_chans;</div><div class='add'>+		}</div><div class='add'>+		clk_mgr_base-&gt;bw_params-&gt;dram_channel_width_bytes = clk_mgr_base-&gt;ctx-&gt;dc_bios-&gt;vram_info.dram_channel_width_bytes;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Refresh bounding box */</div><div class='add'>+	clk_mgr_base-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;update_bw_bounding_box(</div><div class='add'>+			clk_mgr-&gt;base.ctx-&gt;dc, clk_mgr_base-&gt;bw_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_are_clock_states_equal(struct dc_clocks *a,</div><div class='add'>+					struct dc_clocks *b)</div><div class='add'>+{</div><div class='add'>+	if (a-&gt;dispclk_khz != b-&gt;dispclk_khz)</div><div class='add'>+		return false;</div><div class='add'>+	else if (a-&gt;dppclk_khz != b-&gt;dppclk_khz)</div><div class='add'>+		return false;</div><div class='add'>+	else if (a-&gt;dcfclk_khz != b-&gt;dcfclk_khz)</div><div class='add'>+		return false;</div><div class='add'>+	else if (a-&gt;dcfclk_deep_sleep_khz != b-&gt;dcfclk_deep_sleep_khz)</div><div class='add'>+		return false;</div><div class='add'>+	else if (a-&gt;dramclk_khz != b-&gt;dramclk_khz)</div><div class='add'>+		return false;</div><div class='add'>+	else if (a-&gt;p_state_change_support != b-&gt;p_state_change_support)</div><div class='add'>+		return false;</div><div class='add'>+	else if (a-&gt;fclk_p_state_change_support != b-&gt;fclk_p_state_change_support)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr-&gt;smu_present)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dcn401_smu_set_pme_workaround(clk_mgr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	return clk_mgr-&gt;smu_present;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	int dtb_ref_clk_khz = 0;</div><div class='add'>+</div><div class='add'>+	if (clk_mgr-&gt;smu_present &amp;&amp; dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {</div><div class='add'>+		/* DPM enabled, use currently set value */</div><div class='add'>+		dtb_ref_clk_khz = clk_mgr_base-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+	} else {</div><div class='add'>+		/* DPM disabled, so use boot snapshot */</div><div class='add'>+		dtb_ref_clk_khz = clk_mgr_base-&gt;boot_snapshot.dtbclk;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dtb_ref_clk_khz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	uint32_t dispclk_wdivider;</div><div class='add'>+	int disp_divider;</div><div class='add'>+</div><div class='add'>+	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &amp;dispclk_wdivider);</div><div class='add'>+	disp_divider = dentist_get_divider_from_did(dispclk_wdivider);</div><div class='add'>+</div><div class='add'>+	/* Return DISPCLK freq in Khz */</div><div class='add'>+	if (disp_divider)</div><div class='add'>+		return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr-&gt;base.dentist_vco_freq_khz) / disp_divider;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+</div><div class='add'>+	unsigned int num_clk_levels;</div><div class='add'>+</div><div class='add'>+	switch (clk_type) {</div><div class='add'>+	case CLK_TYPE_DISPCLK:</div><div class='add'>+		num_clk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dispclk_levels;</div><div class='add'>+		return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :</div><div class='add'>+				clk_mgr-&gt;base.boot_snapshot.dispclk;</div><div class='add'>+	case CLK_TYPE_DPPCLK:</div><div class='add'>+		num_clk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dppclk_levels;</div><div class='add'>+		return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK) ?</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :</div><div class='add'>+				clk_mgr-&gt;base.boot_snapshot.dppclk;</div><div class='add'>+	case CLK_TYPE_DSCCLK:</div><div class='add'>+		num_clk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_dispclk_levels;</div><div class='add'>+		return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?</div><div class='add'>+				clk_mgr-&gt;base.bw_params-&gt;clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :</div><div class='add'>+				clk_mgr-&gt;base.boot_snapshot.dispclk / 3;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct clk_mgr_funcs dcn401_funcs = {</div><div class='add'>+		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,</div><div class='add'>+		.get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,</div><div class='add'>+		.update_clocks = dcn401_update_clocks,</div><div class='add'>+		.dump_clk_registers = dcn401_dump_clk_registers,</div><div class='add'>+		.init_clocks = dcn401_init_clocks,</div><div class='add'>+		.notify_wm_ranges = dcn401_notify_wm_ranges,</div><div class='add'>+		.set_hard_min_memclk = dcn401_set_hard_min_memclk,</div><div class='add'>+		.get_memclk_states_from_smu = dcn401_get_memclk_states_from_smu,</div><div class='add'>+		.are_clock_states_equal = dcn401_are_clock_states_equal,</div><div class='add'>+		.enable_pme_wa = dcn401_enable_pme_wa,</div><div class='add'>+		.is_smu_present = dcn401_is_smu_present,</div><div class='add'>+		.get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,</div><div class='add'>+		.get_hard_min_memclk = dcn401_get_hard_min_memclk,</div><div class='add'>+		.get_hard_min_fclk = dcn401_get_hard_min_fclk,</div><div class='add'>+		.is_dc_mode_present = dcn401_is_dc_mode_present,</div><div class='add'>+		.get_max_clock_khz = dcn401_get_max_clock_khz,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct clk_mgr_internal *dcn401_clk_mgr_construct(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	struct clk_log_info log_info = {0};</div><div class='add'>+	struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct dcn401_clk_mgr), GFP_KERNEL);</div><div class='add'>+	struct clk_mgr_internal *clk_mgr;</div><div class='add'>+</div><div class='add'>+	if (!clk_mgr401)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	clk_mgr = &amp;clk_mgr401-&gt;base;</div><div class='add'>+	clk_mgr-&gt;base.ctx = ctx;</div><div class='add'>+	clk_mgr-&gt;base.funcs = &amp;dcn401_funcs;</div><div class='add'>+	clk_mgr-&gt;regs = &amp;clk_mgr_regs_dcn401;</div><div class='add'>+	clk_mgr-&gt;clk_mgr_shift = &amp;clk_mgr_shift_dcn401;</div><div class='add'>+	clk_mgr-&gt;clk_mgr_mask = &amp;clk_mgr_mask_dcn401;</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;dccg = dccg;</div><div class='add'>+	clk_mgr-&gt;dfs_bypass_disp_clk = 0;</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;dprefclk_ss_percentage = 0;</div><div class='add'>+	clk_mgr-&gt;dprefclk_ss_divider = 1000;</div><div class='add'>+	clk_mgr-&gt;ss_on_dprefclk = false;</div><div class='add'>+	clk_mgr-&gt;dfs_ref_freq_khz = 100000;</div><div class='add'>+</div><div class='add'>+	/* Changed from DCN3.2_clock_frequency doc to match</div><div class='add'>+	 * dcn401_dump_clk_registers from 4 * dentist_vco_freq_khz /</div><div class='add'>+	 * dprefclk DID divider</div><div class='add'>+	 */</div><div class='add'>+	clk_mgr-&gt;base.dprefclk_khz = 720000; //TODO update from VBIOS</div><div class='add'>+</div><div class='add'>+	/* integer part is now VCO frequency in kHz */</div><div class='add'>+	clk_mgr-&gt;base.dentist_vco_freq_khz = dcn401_get_vco_frequency_from_reg(clk_mgr);</div><div class='add'>+</div><div class='add'>+	/* in case we don't get a value from the register, use default */</div><div class='add'>+	if (clk_mgr-&gt;base.dentist_vco_freq_khz == 0)</div><div class='add'>+		clk_mgr-&gt;base.dentist_vco_freq_khz = 4500000; //TODO Update from VBIOS</div><div class='add'>+</div><div class='add'>+	dcn401_dump_clk_registers(&amp;clk_mgr-&gt;base.boot_snapshot, &amp;clk_mgr-&gt;base, &amp;log_info);</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;dc-&gt;debug.disable_dtb_ref_clk_switch &amp;&amp;</div><div class='add'>+			clk_mgr-&gt;base.clks.ref_dtbclk_khz != clk_mgr-&gt;base.boot_snapshot.dtbclk) {</div><div class='add'>+		clk_mgr-&gt;base.clks.ref_dtbclk_khz = clk_mgr-&gt;base.boot_snapshot.dtbclk;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (clk_mgr-&gt;base.boot_snapshot.dprefclk != 0) {</div><div class='add'>+		clk_mgr-&gt;base.dprefclk_khz = clk_mgr-&gt;base.boot_snapshot.dprefclk;</div><div class='add'>+	}</div><div class='add'>+	dcn401_clock_read_ss_info(clk_mgr);</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;dfs_bypass_enabled = false;</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;smu_present = false;</div><div class='add'>+</div><div class='add'>+	clk_mgr-&gt;base.bw_params = kzalloc(sizeof(*clk_mgr-&gt;base.bw_params), GFP_KERNEL);</div><div class='add'>+	if (!clk_mgr-&gt;base.bw_params) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		kfree(clk_mgr401);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* need physical address of table to give to PMFW */</div><div class='add'>+	clk_mgr-&gt;wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr-&gt;base.ctx,</div><div class='add'>+			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),</div><div class='add'>+			&amp;clk_mgr-&gt;wm_range_table_addr);</div><div class='add'>+	if (!clk_mgr-&gt;wm_range_table) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		kfree(clk_mgr-&gt;base.bw_params);</div><div class='add'>+		kfree(clk_mgr401);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;clk_mgr401-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	kfree(clk_mgr-&gt;base.bw_params);</div><div class='add'>+</div><div class='add'>+	if (clk_mgr-&gt;wm_range_table)</div><div class='add'>+		dm_helpers_free_gpu_mem(clk_mgr-&gt;base.ctx, DC_MEM_ALLOC_TYPE_GART,</div><div class='add'>+				clk_mgr-&gt;wm_range_table);</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h<br/>new file mode 100644<br/>index 000000000000..97a1ce1e8a9e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DCN401_CLK_MGR_H_</div><div class='add'>+#define __DCN401_CLK_MGR_H_</div><div class='add'>+</div><div class='add'>+#define DCN401_CLK_MGR_MAX_SEQUENCE_SIZE 30</div><div class='add'>+</div><div class='add'>+union dcn401_clk_mgr_block_sequence_params {</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		uint32_t num_displays;</div><div class='add'>+	} update_num_displays_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		uint32_t ppclk;</div><div class='add'>+		uint16_t freq_mhz;</div><div class='add'>+		/* outputs */</div><div class='add'>+		uint32_t *response;</div><div class='add'>+	} update_hardmin_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		uint32_t ppclk;</div><div class='add'>+		int freq_khz;</div><div class='add'>+		/* outputs */</div><div class='add'>+		uint32_t *response;</div><div class='add'>+	} update_hardmin_optimized_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		uint16_t uclk_mhz;</div><div class='add'>+		uint16_t fclk_mhz;</div><div class='add'>+	} update_idle_hardmin_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		uint16_t freq_mhz;</div><div class='add'>+	} update_deep_sleep_dcfclk_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		bool support;</div><div class='add'>+	} update_pstate_support_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		unsigned int num_ways;</div><div class='add'>+	} update_cab_for_uclk_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		bool enable;</div><div class='add'>+	} update_wait_for_dmub_ack_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		bool mod_drr_for_pstate;</div><div class='add'>+	} indicate_drr_status_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		struct dc_state *context;</div><div class='add'>+		int *ref_dppclk_khz;</div><div class='add'>+		bool safe_to_lower;</div><div class='add'>+	} update_dppclk_dto_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		struct dc_state *context;</div><div class='add'>+		int *ref_dtbclk_khz;</div><div class='add'>+	} update_dtbclk_dto_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		struct dc_state *context;</div><div class='add'>+	} update_dentist_params;</div><div class='add'>+	struct {</div><div class='add'>+		/* inputs */</div><div class='add'>+		struct dmcu *dmcu;</div><div class='add'>+		unsigned int wait;</div><div class='add'>+	} update_psr_wait_loop_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dcn401_clk_mgr_block_sequence_func {</div><div class='add'>+	CLK_MGR401_READ_CLOCKS_FROM_DENTIST,</div><div class='add'>+	CLK_MGR401_UPDATE_NUM_DISPLAYS,</div><div class='add'>+	CLK_MGR401_UPDATE_HARDMIN_PPCLK,</div><div class='add'>+	CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED,</div><div class='add'>+	CLK_MGR401_UPDATE_ACTIVE_HARDMINS,</div><div class='add'>+	CLK_MGR401_UPDATE_IDLE_HARDMINS,</div><div class='add'>+	CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK,</div><div class='add'>+	CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT,</div><div class='add'>+	CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT,</div><div class='add'>+	CLK_MGR401_UPDATE_CAB_FOR_UCLK,</div><div class='add'>+	CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK,</div><div class='add'>+	CLK_MGR401_INDICATE_DRR_STATUS,</div><div class='add'>+	CLK_MGR401_UPDATE_DPPCLK_DTO,</div><div class='add'>+	CLK_MGR401_UPDATE_DTBCLK_DTO,</div><div class='add'>+	CLK_MGR401_UPDATE_DENTIST,</div><div class='add'>+	CLK_MGR401_UPDATE_PSR_WAIT_LOOP,</div><div class='add'>+	CLK_MGR401_UPDATE_SUBVP_HARDMINS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_clk_mgr_block_sequence {</div><div class='add'>+	union dcn401_clk_mgr_block_sequence_params params;</div><div class='add'>+	enum dcn401_clk_mgr_block_sequence_func func;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_clk_mgr {</div><div class='add'>+	struct clk_mgr_internal base;</div><div class='add'>+</div><div class='add'>+	struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);</div><div class='add'>+bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);</div><div class='add'>+</div><div class='add'>+struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,</div><div class='add'>+		struct dccg *dccg);</div><div class='add'>+</div><div class='add'>+void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+</div><div class='add'>+unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);</div><div class='add'>+</div><div class='add'>+#endif /* __DCN401_CLK_MGR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c<br/>new file mode 100644<br/>index 000000000000..3a263840893e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c</a></div><div class='hunk'>@@ -0,0 +1,472 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dcn401_clk_mgr_smu_msg.h"</div><div class='add'>+</div><div class='add'>+#include "clk_mgr_internal.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+</div><div class='add'>+#include "dalsmc.h"</div><div class='add'>+#include "dcn401_smu14_driver_if.h"</div><div class='add'>+</div><div class='add'>+#define mmDAL_MSG_REG  0x1628A</div><div class='add'>+#define mmDAL_ARG_REG  0x16273</div><div class='add'>+#define mmDAL_RESP_REG 0x16274</div><div class='add'>+</div><div class='add'>+#define REG(reg_name) \</div><div class='add'>+	mm ## reg_name</div><div class='add'>+</div><div class='add'>+#include "logger_types.h"</div><div class='add'>+</div><div class='add'>+#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }</div><div class='add'>+</div><div class='add'>+/* temporary define */</div><div class='add'>+#ifndef DALSMC_MSG_SubvpUclkFclk</div><div class='add'>+#define DALSMC_MSG_SubvpUclkFclk 0x1B</div><div class='add'>+#endif</div><div class='add'>+#ifndef DALSMC_MSG_GetNumUmcChannels</div><div class='add'>+#define DALSMC_MSG_GetNumUmcChannels 0x1C</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Function to be used instead of REG_WAIT macro because the wait ends when</div><div class='add'>+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h</div><div class='add'>+ * won't work with REG_WAIT.</div><div class='add'>+ */</div><div class='add'>+static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg = 0;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		reg = REG_READ(DAL_RESP_REG);</div><div class='add'>+		if (reg)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (delay_us &gt;= 1000)</div><div class='add'>+			msleep(delay_us/1000);</div><div class='add'>+		else if (delay_us &gt; 0)</div><div class='add'>+			udelay(delay_us);</div><div class='add'>+	} while (max_retries--);</div><div class='add'>+</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)</div><div class='add'>+{</div><div class='add'>+	/* Wait for response register to be ready */</div><div class='add'>+	dcn401_smu_wait_for_response(clk_mgr, 10, 200000);</div><div class='add'>+</div><div class='add'>+	TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='add'>+	/* Clear response register */</div><div class='add'>+	REG_WRITE(DAL_RESP_REG, 0);</div><div class='add'>+</div><div class='add'>+	/* Set the parameter register for the SMU message */</div><div class='add'>+	REG_WRITE(DAL_ARG_REG, param_in);</div><div class='add'>+</div><div class='add'>+	/* Trigger the message transaction by writing the message ID */</div><div class='add'>+	REG_WRITE(DAL_MSG_REG, msg_id);</div><div class='add'>+</div><div class='add'>+	/* Wait for response */</div><div class='add'>+	if (dcn401_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {</div><div class='add'>+		if (param_out)</div><div class='add'>+			*param_out = REG_READ(DAL_ARG_REG);</div><div class='add'>+</div><div class='add'>+		TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr-&gt;base.ctx);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	TRACE_SMU_MSG_EXIT(false, 0, clk_mgr-&gt;base.ctx);</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Use these functions to return back delay information so we can aggregate the total</div><div class='add'>+ *  delay when requesting hardmin clk</div><div class='add'>+ *</div><div class='add'>+ * dcn401_smu_wait_for_response_delay</div><div class='add'>+ * dcn401_smu_send_msg_with_param_delay</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)</div><div class='add'>+{</div><div class='add'>+	uint32_t reg = 0;</div><div class='add'>+	*total_delay_us = 0;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		reg = REG_READ(DAL_RESP_REG);</div><div class='add'>+		if (reg)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (delay_us &gt;= 1000)</div><div class='add'>+			msleep(delay_us/1000);</div><div class='add'>+		else if (delay_us &gt; 0)</div><div class='add'>+			udelay(delay_us);</div><div class='add'>+		*total_delay_us += delay_us;</div><div class='add'>+	} while (max_retries--);</div><div class='add'>+</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)</div><div class='add'>+{</div><div class='add'>+	unsigned int delay1_us, delay2_us;</div><div class='add'>+	*total_delay_us = 0;</div><div class='add'>+</div><div class='add'>+	/* Wait for response register to be ready */</div><div class='add'>+	dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &amp;delay1_us);</div><div class='add'>+</div><div class='add'>+	TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr-&gt;base.ctx);</div><div class='add'>+</div><div class='add'>+	/* Clear response register */</div><div class='add'>+	REG_WRITE(DAL_RESP_REG, 0);</div><div class='add'>+</div><div class='add'>+	/* Set the parameter register for the SMU message */</div><div class='add'>+	REG_WRITE(DAL_ARG_REG, param_in);</div><div class='add'>+</div><div class='add'>+	/* Trigger the message transaction by writing the message ID */</div><div class='add'>+	REG_WRITE(DAL_MSG_REG, msg_id);</div><div class='add'>+</div><div class='add'>+	/* Wait for response */</div><div class='add'>+	if (dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &amp;delay2_us) == DALSMC_Result_OK) {</div><div class='add'>+		if (param_out)</div><div class='add'>+			*param_out = REG_READ(DAL_ARG_REG);</div><div class='add'>+</div><div class='add'>+		*total_delay_us = delay1_us + delay2_us;</div><div class='add'>+		TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr-&gt;base.ctx);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*total_delay_us = delay1_us + 2000000;</div><div class='add'>+	TRACE_SMU_MSG_EXIT(false, 0, clk_mgr-&gt;base.ctx);</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Get SMU version\n");</div><div class='add'>+</div><div class='add'>+	if (dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_GetSmuVersion, 0, version)) {</div><div class='add'>+</div><div class='add'>+		smu_print("SMU version: %d\n", *version);</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */</div><div class='add'>+bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Check driver if version\n");</div><div class='add'>+</div><div class='add'>+	if (dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_GetDriverIfVersion, 0, &amp;response)) {</div><div class='add'>+</div><div class='add'>+		smu_print("SMU driver if version: %d\n", response);</div><div class='add'>+</div><div class='add'>+		if (response == SMU14_DRIVER_IF_VERSION)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Message output should match DALSMC_VERSION in dalsmc.h */</div><div class='add'>+bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Check msg header version\n");</div><div class='add'>+</div><div class='add'>+	if (dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_GetMsgHeaderVersion, 0, &amp;response)) {</div><div class='add'>+</div><div class='add'>+		smu_print("SMU msg header version: %d\n", response);</div><div class='add'>+</div><div class='add'>+		if (response == DALSMC_VERSION)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)</div><div class='add'>+{</div><div class='add'>+	smu_print("FCLK P-state support value is : %d\n", support);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SetFclkSwitchAllow, support, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)</div><div class='add'>+{</div><div class='add'>+	smu_print("UCLK P-state support value is : %d\n", support);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SetUclkPstateAllow, support, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)</div><div class='add'>+{</div><div class='add'>+	uint32_t param = (num_ways &lt;&lt; 1) | (num_ways &gt; 0);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);</div><div class='add'>+	smu_print("Numways for SubVP : %d\n", num_ways);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Set DRAM addr high: %d\n", addr_high);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Set DRAM addr low: %d\n", addr_low);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Transfer WM table DRAM 2 SMU\n");</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Set PME workaround\n");</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+		DALSMC_MSG_BacoAudioD3PME, 0, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dcn401_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+</div><div class='add'>+	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */</div><div class='add'>+	uint32_t param = 0;</div><div class='add'>+</div><div class='add'>+	*no_timeout = dcn401_smu_send_msg_with_param_delay(clk_mgr,</div><div class='add'>+			DALSMC_MSG_ReturnHardMinStatus, param, &amp;response, total_delay_us);</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n",</div><div class='add'>+		*no_timeout, *total_delay_us, response);</div><div class='add'>+</div><div class='add'>+	return response;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)</div><div class='add'>+{</div><div class='add'>+	const unsigned int max_delay_us = 1000000;</div><div class='add'>+</div><div class='add'>+	unsigned int hardmin_status_mask = (1 &lt;&lt; ppclk);</div><div class='add'>+	unsigned int total_delay_us = 0;</div><div class='add'>+	bool hardmin_done = false;</div><div class='add'>+</div><div class='add'>+	while (!hardmin_done &amp;&amp; total_delay_us &lt; max_delay_us) {</div><div class='add'>+		unsigned int hardmin_status;</div><div class='add'>+		unsigned int read_total_delay_us;</div><div class='add'>+		bool no_timeout;</div><div class='add'>+</div><div class='add'>+		if (!hardmin_done &amp;&amp; total_delay_us &gt; 0) {</div><div class='add'>+			/* hardmin not yet fulfilled, wait 500us and retry*/</div><div class='add'>+			udelay(500);</div><div class='add'>+			total_delay_us += 500;</div><div class='add'>+</div><div class='add'>+			smu_print("SMU Wait hard min status for %d us\n", total_delay_us);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		hardmin_status = dcn401_smu_get_hard_min_status(clk_mgr, &amp;no_timeout, &amp;read_total_delay_us);</div><div class='add'>+		total_delay_us += read_total_delay_us;</div><div class='add'>+		hardmin_done = hardmin_status &amp; hardmin_status_mask;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return hardmin_done;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Returns the actual frequency that was set in MHz, 0 on failure */</div><div class='add'>+unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+	bool hard_min_done = false;</div><div class='add'>+</div><div class='add'>+	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */</div><div class='add'>+	uint32_t param = (clk &lt;&lt; 16) | freq_mhz;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SetHardMinByFreq, param, &amp;response);</div><div class='add'>+</div><div class='add'>+	/* wait until hardmin acknowledged */</div><div class='add'>+	hard_min_done = dcn401_smu_wait_hard_min_status(clk_mgr, clk);</div><div class='add'>+	smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done);</div><div class='add'>+</div><div class='add'>+	return response;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetAlwaysWaitDmcubResp, enable ? 1 : 0, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Set indicate drr status = %d\n", mod_drr_for_pstate);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_IndicateDrrStatus, mod_drr_for_pstate ? 1 : 0, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		uint16_t uclk_freq_mhz,</div><div class='add'>+		uint16_t fclk_freq_mhz)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	/* 15:0 for uclk, 32:16 for fclk */</div><div class='add'>+	uint32_t param = (fclk_freq_mhz &lt;&lt; 16) | uclk_freq_mhz;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Set idle hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);</div><div class='add'>+</div><div class='add'>+	success = dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_IdleUclkFclk, param, &amp;response);</div><div class='add'>+</div><div class='add'>+	/* wait until hardmin acknowledged */</div><div class='add'>+	success &amp;= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);</div><div class='add'>+	smu_print("SMU hard_min_done %d\n", success);</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		uint16_t uclk_freq_mhz,</div><div class='add'>+		uint16_t fclk_freq_mhz)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	/* 15:0 for uclk, 32:16 for fclk */</div><div class='add'>+	uint32_t param = (fclk_freq_mhz &lt;&lt; 16) | uclk_freq_mhz;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);</div><div class='add'>+</div><div class='add'>+	success = dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_ActiveUclkFclk, param, &amp;response);</div><div class='add'>+</div><div class='add'>+	/* wait until hardmin acknowledged */</div><div class='add'>+	success &amp;= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);</div><div class='add'>+	smu_print("SMU hard_min_done %d\n", success);</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		uint16_t uclk_freq_mhz,</div><div class='add'>+		uint16_t fclk_freq_mhz)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	/* 15:0 for uclk, 32:16 for fclk */</div><div class='add'>+	uint32_t param = (fclk_freq_mhz &lt;&lt; 16) | uclk_freq_mhz;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);</div><div class='add'>+</div><div class='add'>+	success = dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SubvpUclkFclk, param, &amp;response);</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_SetMinDeepSleepDcfclk, freq_mhz, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)</div><div class='add'>+{</div><div class='add'>+	smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_NumOfDisplays, num_displays, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	unsigned int response = 0;</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_GetNumUmcChannels, 0, &amp;response);</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Get Num UMC Channels: num_umc_channels = %d\n", response);</div><div class='add'>+</div><div class='add'>+	return response;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Frequency in MHz returned in lower 16 bits for valid DPM level</div><div class='add'>+ *</div><div class='add'>+ * Call with dpm_level = 0xFF to query features, return value will be:</div><div class='add'>+ *     Bits 7:0 - number of DPM levels</div><div class='add'>+ *     Bit   28 - 1 = auto DPM on</div><div class='add'>+ *     Bit   29 - 1 = sweep DPM on</div><div class='add'>+ *     Bit   30 - 1 = forced DPM on</div><div class='add'>+ *     Bit   31 - 0 = discrete, 1 = fine-grained</div><div class='add'>+ *</div><div class='add'>+ * With fine-grained DPM, only min and max frequencies will be reported</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 on failure</div><div class='add'>+ */</div><div class='add'>+unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+</div><div class='add'>+	/* bits 23:16 for clock type, lower 8 bits for DPM level */</div><div class='add'>+	uint32_t param = (clk &lt;&lt; 16) | dpm_level;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_GetDpmFreqByIndex, param, &amp;response);</div><div class='add'>+</div><div class='add'>+	smu_print("SMU dpm freq: %d MHz\n", response);</div><div class='add'>+</div><div class='add'>+	return response;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */</div><div class='add'>+unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)</div><div class='add'>+{</div><div class='add'>+	uint32_t response = 0;</div><div class='add'>+</div><div class='add'>+	/* bits 23:16 for clock type */</div><div class='add'>+	uint32_t param = clk &lt;&lt; 16;</div><div class='add'>+</div><div class='add'>+	smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);</div><div class='add'>+</div><div class='add'>+	dcn401_smu_send_msg_with_param(clk_mgr,</div><div class='add'>+			DALSMC_MSG_GetDcModeMaxDpmFreq, param, &amp;response);</div><div class='add'>+</div><div class='add'>+	smu_print("SMU DC mode max DMP freq: %d MHz\n", response);</div><div class='add'>+</div><div class='add'>+	return response;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h<br/>new file mode 100644<br/>index 000000000000..4f5ac603e822<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DCN401_CLK_MGR_SMU_MSG_H_</div><div class='add'>+#define __DCN401_CLK_MGR_SMU_MSG_H_</div><div class='add'>+</div><div class='add'>+#include "os_types.h"</div><div class='add'>+#include "core_types.h"</div><div class='add'>+</div><div class='add'>+struct clk_mgr_internal;</div><div class='add'>+</div><div class='add'>+bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);</div><div class='add'>+bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);</div><div class='add'>+void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);</div><div class='add'>+void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);</div><div class='add'>+void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);</div><div class='add'>+void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);</div><div class='add'>+void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);</div><div class='add'>+void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);</div><div class='add'>+void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate);</div><div class='add'>+bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		uint16_t uclk_freq_mhz,</div><div class='add'>+		uint16_t fclk_freq_mhz);</div><div class='add'>+bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		uint16_t uclk_freq_mhz,</div><div class='add'>+		uint16_t fclk_freq_mhz);</div><div class='add'>+bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		uint16_t uclk_freq_mhz,</div><div class='add'>+		uint16_t fclk_freq_mhz);</div><div class='add'>+void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);</div><div class='add'>+void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);</div><div class='add'>+unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr);</div><div class='add'>+unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);</div><div class='add'>+unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);</div><div class='add'>+</div><div class='add'>+#endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h<br/>new file mode 100644<br/>index 000000000000..36034b32870c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_smu14_driver_if.h</a></div><div class='hunk'>@@ -0,0 +1,66 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+//</div><div class='add'>+// This is a stripped-down version of the smu13_driver_if.h file for the relevant DAL interfaces.</div><div class='add'>+</div><div class='add'>+#define SMU14_DRIVER_IF_VERSION  0x1</div><div class='add'>+</div><div class='add'>+//Only Clks that have DPM descriptors are listed here</div><div class='add'>+typedef enum {</div><div class='add'>+  PPCLK_GFXCLK = 0,</div><div class='add'>+  PPCLK_SOCCLK,</div><div class='add'>+  PPCLK_UCLK,</div><div class='add'>+  PPCLK_FCLK,</div><div class='add'>+  PPCLK_DCLK_0,</div><div class='add'>+  PPCLK_VCLK_0,</div><div class='add'>+  PPCLK_DISPCLK,</div><div class='add'>+  PPCLK_DPPCLK,</div><div class='add'>+  PPCLK_DPREFCLK,</div><div class='add'>+  PPCLK_DCFCLK,</div><div class='add'>+  PPCLK_DTBCLK,</div><div class='add'>+  PPCLK_COUNT,</div><div class='add'>+} PPCLK_e;</div><div class='add'>+</div><div class='add'>+typedef struct {</div><div class='add'>+  uint8_t  WmSetting;</div><div class='add'>+  uint8_t  Flags;</div><div class='add'>+  uint8_t  Padding[2];</div><div class='add'>+</div><div class='add'>+} WatermarkRowGeneric_t;</div><div class='add'>+</div><div class='add'>+#define NUM_WM_RANGES 4</div><div class='add'>+</div><div class='add'>+typedef enum {</div><div class='add'>+  WATERMARKS_CLOCK_RANGE = 0,</div><div class='add'>+  WATERMARKS_DUMMY_PSTATE,</div><div class='add'>+  WATERMARKS_MALL,</div><div class='add'>+  WATERMARKS_COUNT,</div><div class='add'>+} WATERMARKS_FLAGS_e;</div><div class='add'>+</div><div class='add'>+typedef struct {</div><div class='add'>+  // Watermarks</div><div class='add'>+  WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];</div><div class='add'>+} Watermarks_t;</div><div class='add'>+</div><div class='add'>+typedef struct {</div><div class='add'>+  Watermarks_t Watermarks;</div><div class='add'>+  uint32_t  Spare[16];</div><div class='add'>+</div><div class='add'>+  uint32_t     MmHubPadding[8]; // SMU internal use</div><div class='add'>+} WatermarksExternal_t;</div><div class='add'>+</div><div class='add'>+// Table types</div><div class='add'>+#define TABLE_PMFW_PPTABLE            0</div><div class='add'>+#define TABLE_COMBO_PPTABLE           1</div><div class='add'>+#define TABLE_WATERMARKS              2</div><div class='add'>+#define TABLE_AVFS_PSM_DEBUG          3</div><div class='add'>+#define TABLE_PMSTATUSLOG             4</div><div class='add'>+#define TABLE_SMU_METRICS             5</div><div class='add'>+#define TABLE_DRIVER_SMU_CONFIG       6</div><div class='add'>+#define TABLE_ACTIVITY_MONITOR_COEFF  7</div><div class='add'>+#define TABLE_OVERDRIVE               8</div><div class='add'>+#define TABLE_I2C_COMMANDS            9</div><div class='add'>+#define TABLE_DRIVER_INFO             10</div><div class='add'>+#define TABLE_ECCINFO                 11</div><div class='add'>+#define TABLE_COUNT                   12</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c<br/>index e7dc128f6284..8be9cbd43e18 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc.c</a></div><div class='hunk'>@@ -36,6 +36,9 @@</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "dc_state.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='add'>+#include "dc_plane.h"</div><div class='add'>+#include "dc_plane_priv.h"</div><div class='add'>+#include "dc_stream_priv.h"</div><div class='ctx'> </div><div class='ctx'> #include "gpio_service_interface.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='hunk'>@@ -57,7 +60,7 @@</div><div class='ctx'> #include "link_encoder.h"</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "mem_input.h"</div><div class='ctx'> </div><div class='hunk'>@@ -79,7 +82,10 @@</div><div class='ctx'> </div><div class='ctx'> #include "hw_sequencer_private.h"</div><div class='ctx'> </div><div class='del'>-#include "dml2/dml2_internal_types.h"</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+#include "dml2_0/dml2_internal_types.h"</div><div class='add'>+#include "soc_and_ip_translator.h"</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> #include "dce/dmub_outbox.h"</div><div class='ctx'> </div><div class='hunk'>@@ -142,10 +148,16 @@ static const char DC_BUILD_ID[] = "production-build";</div><div class='ctx'> </div><div class='ctx'> /* Private functions */</div><div class='ctx'> </div><div class='del'>-static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)</div><div class='add'>+static inline void elevate_update_type(</div><div class='add'>+		struct surface_update_descriptor *descriptor,</div><div class='add'>+		enum surface_update_type new_type,</div><div class='add'>+		enum dc_lock_descriptor new_locks</div><div class='add'>+)</div><div class='ctx'> {</div><div class='del'>-	if (new &gt; *original)</div><div class='del'>-		*original = new;</div><div class='add'>+	if (new_type &gt; descriptor-&gt;update_type)</div><div class='add'>+		descriptor-&gt;update_type = new_type;</div><div class='add'>+</div><div class='add'>+	descriptor-&gt;lock_descriptor |= new_locks;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void destroy_links(struct dc *dc)</div><div class='hunk'>@@ -212,10 +224,24 @@ static bool create_links(</div><div class='ctx'> 		connectors_num,</div><div class='ctx'> 		num_virtual_links);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; connectors_num; i++) {</div><div class='add'>+	/* When getting the number of connectors, the VBIOS reports the number of valid indices,</div><div class='add'>+	 * but it doesn't say which indices are valid, and not every index has an actual connector.</div><div class='add'>+	 * So, if we don't find a connector on an index, that is not an error.</div><div class='add'>+	 *</div><div class='add'>+	 * - There is no guarantee that the first N indices will be valid</div><div class='add'>+	 * - VBIOS may report a higher amount of valid indices than there are actual connectors</div><div class='add'>+	 * - Some VBIOS have valid configurations for more connectors than there actually are</div><div class='add'>+	 *   on the card. This may be because the manufacturer used the same VBIOS for different</div><div class='add'>+	 *   variants of the same card.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; dc-&gt;link_count &lt; connectors_num &amp;&amp; i &lt; MAX_LINKS; i++) {</div><div class='add'>+		struct graphics_object_id connector_id = bios-&gt;funcs-&gt;get_connector_id(bios, i);</div><div class='ctx'> 		struct link_init_data link_init_params = {0};</div><div class='ctx'> 		struct dc_link *link;</div><div class='ctx'> </div><div class='add'>+		if (connector_id.id == CONNECTOR_ID_UNKNOWN)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc-&gt;link_count);</div><div class='ctx'> </div><div class='ctx'> 		link_init_params.ctx = dc-&gt;ctx;</div><div class='hunk'>@@ -235,6 +261,7 @@ static bool create_links(</div><div class='ctx'> 	DC_LOG_DC("BIOS object table - end");</div><div class='ctx'> </div><div class='ctx'> 	/* Create a link for each usb4 dpia port */</div><div class='add'>+	dc-&gt;lowest_dpia_link_index = MAX_LINKS;</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;usb4_dpia_count; i++) {</div><div class='ctx'> 		struct link_init_data link_init_params = {0};</div><div class='ctx'> 		struct dc_link *link;</div><div class='hunk'>@@ -247,6 +274,9 @@ static bool create_links(</div><div class='ctx'> </div><div class='ctx'> 		link = dc-&gt;link_srv-&gt;create_link(&amp;link_init_params);</div><div class='ctx'> 		if (link) {</div><div class='add'>+			if (dc-&gt;lowest_dpia_link_index &gt; dc-&gt;link_count)</div><div class='add'>+				dc-&gt;lowest_dpia_link_index = dc-&gt;link_count;</div><div class='add'>+</div><div class='ctx'> 			dc-&gt;links[dc-&gt;link_count] = link;</div><div class='ctx'> 			link-&gt;dc = dc;</div><div class='ctx'> 			++dc-&gt;link_count;</div><div class='hunk'>@@ -272,6 +302,8 @@ static bool create_links(</div><div class='ctx'> 		link-&gt;link_id.type = OBJECT_TYPE_CONNECTOR;</div><div class='ctx'> 		link-&gt;link_id.id = CONNECTOR_ID_VIRTUAL;</div><div class='ctx'> 		link-&gt;link_id.enum_id = ENUM_ID_1;</div><div class='add'>+		link-&gt;psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;</div><div class='add'>+		link-&gt;replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED;</div><div class='ctx'> 		link-&gt;link_enc = kzalloc(sizeof(*link-&gt;link_enc), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 		if (!link-&gt;link_enc) {</div><div class='hunk'>@@ -386,6 +418,30 @@ static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)</div><div class='ctx'> 	*perf_trace = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust)</div><div class='add'>+{</div><div class='add'>+	if (!dc || !stream || !adjust)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;current_state)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;stream == stream &amp;&amp; pipe-&gt;stream_res.tg) {</div><div class='add'>+			if (dc-&gt;hwss.set_long_vtotal)</div><div class='add'>+				dc-&gt;hwss.set_long_vtotal(&amp;pipe, 1, adjust-&gt;v_total_min, adjust-&gt;v_total_max);</div><div class='add'>+</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  *  dc_stream_adjust_vmin_vmax - look up pipe context &amp; update parts of DRR</div><div class='ctx'>  *  @dc:     dc reference</div><div class='hunk'>@@ -410,9 +466,14 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,</div><div class='ctx'> 	 * Don't adjust DRR while there's bandwidth optimizations pending to</div><div class='ctx'> 	 * avoid conflicting with firmware updates.</div><div class='ctx'> 	 */</div><div class='del'>-	if (dc-&gt;ctx-&gt;dce_version &gt; DCE_VERSION_MAX)</div><div class='del'>-		if (dc-&gt;optimized_required || dc-&gt;wm_optimized_required)</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_version &gt; DCE_VERSION_MAX) {</div><div class='add'>+		if (dc-&gt;optimized_required &amp;&amp;</div><div class='add'>+			(stream-&gt;adjust.v_total_max != adjust-&gt;v_total_max ||</div><div class='add'>+			stream-&gt;adjust.v_total_min != adjust-&gt;v_total_min)) {</div><div class='add'>+			stream-&gt;adjust.timing_adjust_pending = true;</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> </div><div class='hunk'>@@ -420,6 +481,16 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,</div><div class='ctx'> 	stream-&gt;adjust.v_total_mid = adjust-&gt;v_total_mid;</div><div class='ctx'> 	stream-&gt;adjust.v_total_mid_frame_num = adjust-&gt;v_total_mid_frame_num;</div><div class='ctx'> 	stream-&gt;adjust.v_total_min = adjust-&gt;v_total_min;</div><div class='add'>+	stream-&gt;adjust.allow_otg_v_count_halt = adjust-&gt;allow_otg_v_count_halt;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.max_v_total != 0 &amp;&amp;</div><div class='add'>+		(adjust-&gt;v_total_max &gt; dc-&gt;caps.max_v_total || adjust-&gt;v_total_min &gt; dc-&gt;caps.max_v_total)) {</div><div class='add'>+		stream-&gt;adjust.timing_adjust_pending = false;</div><div class='add'>+		if (adjust-&gt;allow_otg_v_count_halt)</div><div class='add'>+			return set_long_vtotal(dc, stream, adjust);</div><div class='add'>+		else</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -428,10 +499,15 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,</div><div class='ctx'> 			dc-&gt;hwss.set_drr(&amp;pipe,</div><div class='ctx'> 					1,</div><div class='ctx'> 					*adjust);</div><div class='add'>+			stream-&gt;adjust.timing_adjust_pending = false;</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;hwss.notify_cursor_offload_drr_update)</div><div class='add'>+				dc-&gt;hwss.notify_cursor_offload_drr_update(dc, dc-&gt;current_state, stream);</div><div class='ctx'> </div><div class='ctx'> 			return true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -478,33 +554,6 @@ bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_stream_get_crtc_position(struct dc *dc,</div><div class='del'>-		struct dc_stream_state **streams, int num_streams,</div><div class='del'>-		unsigned int *v_pos, unsigned int *nom_v_pos)</div><div class='del'>-{</div><div class='del'>-	/* TODO: Support multiple streams */</div><div class='del'>-	const struct dc_stream_state *stream = streams[0];</div><div class='del'>-	int i;</div><div class='del'>-	bool ret = false;</div><div class='del'>-	struct crtc_position position;</div><div class='del'>-</div><div class='del'>-	dc_exit_ips_for_hw_access(dc);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-		struct pipe_ctx *pipe =</div><div class='del'>-				&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (pipe-&gt;stream == stream &amp;&amp; pipe-&gt;stream_res.stream_enc) {</div><div class='del'>-			dc-&gt;hwss.get_position(&amp;pipe, 1, &amp;position);</div><div class='del'>-</div><div class='del'>-			*v_pos = position.vertical_count;</div><div class='del'>-			*nom_v_pos = position.nominal_vcount;</div><div class='del'>-			ret = true;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='ctx'> static inline void</div><div class='ctx'> dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,</div><div class='hunk'>@@ -542,7 +591,7 @@ dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,</div><div class='ctx'> </div><div class='ctx'> bool</div><div class='ctx'> dc_stream_forward_crc_window(struct dc_stream_state *stream,</div><div class='del'>-		struct rect *rect, bool is_stop)</div><div class='add'>+		struct rect *rect, uint8_t phy_id, bool is_stop)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmcu *dmcu;</div><div class='ctx'> 	struct dc_dmub_srv *dmub_srv;</div><div class='hunk'>@@ -561,7 +610,7 @@ dc_stream_forward_crc_window(struct dc_stream_state *stream,</div><div class='ctx'> 	if (i == MAX_PIPES)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	mux_mapping.phy_output_num = stream-&gt;link-&gt;link_enc_hw_inst;</div><div class='add'>+	mux_mapping.phy_output_num = phy_id;</div><div class='ctx'> 	mux_mapping.otg_output_num = pipe-&gt;stream_res.tg-&gt;inst;</div><div class='ctx'> </div><div class='ctx'> 	dmcu = dc-&gt;res_pool-&gt;dmcu;</div><div class='hunk'>@@ -578,25 +627,89 @@ dc_stream_forward_crc_window(struct dc_stream_state *stream,</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+dc_stream_forward_dmub_multiple_crc_window(struct dc_dmub_srv *dmub_srv,</div><div class='add'>+		struct crc_window *window, struct otg_phy_mux *mux_mapping, bool stop)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	union dmub_rb_cmd cmd = {0};</div><div class='add'>+</div><div class='add'>+	cmd.secure_display.mul_roi_ctl.phy_id = mux_mapping-&gt;phy_output_num;</div><div class='add'>+	cmd.secure_display.mul_roi_ctl.otg_id = mux_mapping-&gt;otg_output_num;</div><div class='add'>+</div><div class='add'>+	cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;</div><div class='add'>+</div><div class='add'>+	if (stop) {</div><div class='add'>+		cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE;</div><div class='add'>+	} else {</div><div class='add'>+		cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY;</div><div class='add'>+		for (i = 0; i &lt; MAX_CRC_WINDOW_NUM; i++) {</div><div class='add'>+			cmd.secure_display.mul_roi_ctl.roi_ctl[i].x_start = window[i].rect.x;</div><div class='add'>+			cmd.secure_display.mul_roi_ctl.roi_ctl[i].y_start = window[i].rect.y;</div><div class='add'>+			cmd.secure_display.mul_roi_ctl.roi_ctl[i].x_end = window[i].rect.x + window[i].rect.width;</div><div class='add'>+			cmd.secure_display.mul_roi_ctl.roi_ctl[i].y_end = window[i].rect.y + window[i].rect.height;</div><div class='add'>+			cmd.secure_display.mul_roi_ctl.roi_ctl[i].enable = window[i].enable;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool</div><div class='add'>+dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream,</div><div class='add'>+		struct crc_window *window, uint8_t phy_id, bool stop)</div><div class='add'>+{</div><div class='add'>+	struct dc_dmub_srv *dmub_srv;</div><div class='add'>+	struct otg_phy_mux mux_mapping;</div><div class='add'>+	struct pipe_ctx *pipe;</div><div class='add'>+	int i;</div><div class='add'>+	struct dc *dc = stream-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (pipe-&gt;stream == stream &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Stream not found */</div><div class='add'>+	if (i == MAX_PIPES)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	mux_mapping.phy_output_num = phy_id;</div><div class='add'>+	mux_mapping.otg_output_num = pipe-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+</div><div class='add'>+	dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+</div><div class='add'>+	/* forward to dmub only. no dmcu support*/</div><div class='add'>+	if (dmub_srv)</div><div class='add'>+		dc_stream_forward_dmub_multiple_crc_window(dmub_srv, window, &amp;mux_mapping, stop);</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='ctx'> #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dc_stream_configure_crc() - Configure CRC capture for the given stream.</div><div class='ctx'>  * @dc: DC Object</div><div class='ctx'>  * @stream: The stream to configure CRC on.</div><div class='del'>- * @enable: Enable CRC if true, disable otherwise.</div><div class='ctx'>  * @crc_window: CRC window (x/y start/end) information</div><div class='add'>+ * @enable: Enable CRC if true, disable otherwise.</div><div class='ctx'>  * @continuous: Capture CRC on every frame if true. Otherwise, only capture</div><div class='ctx'>  *              once.</div><div class='add'>+ * @idx: Capture CRC on which CRC engine instance</div><div class='add'>+ * @reset: Reset CRC engine before the configuration</div><div class='ctx'>  *</div><div class='del'>- * By default, only CRC0 is configured, and the entire frame is used to</div><div class='del'>- * calculate the CRC.</div><div class='add'>+ * By default, the entire frame is used to calculate the CRC.</div><div class='ctx'>  *</div><div class='ctx'>  * Return: %false if the stream is not found or CRC capture is not supported;</div><div class='ctx'>  *         %true if the stream has been configured.</div><div class='ctx'>  */</div><div class='ctx'> bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,</div><div class='del'>-			     struct crc_params *crc_window, bool enable, bool continuous)</div><div class='add'>+			     struct crc_params *crc_window, bool enable, bool continuous,</div><div class='add'>+			     uint8_t idx, bool reset)</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='ctx'> 	struct crc_params param;</div><div class='hunk'>@@ -640,6 +753,9 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,</div><div class='ctx'> 	param.continuous_mode = continuous;</div><div class='ctx'> 	param.enable = enable;</div><div class='ctx'> </div><div class='add'>+	param.crc_eng_inst = idx;</div><div class='add'>+	param.reset = reset;</div><div class='add'>+</div><div class='ctx'> 	tg = pipe-&gt;stream_res.tg;</div><div class='ctx'> </div><div class='ctx'> 	/* Only call if supported */</div><div class='hunk'>@@ -654,6 +770,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: DC object.</div><div class='ctx'>  * @stream: The DC stream state of the stream to get CRCs from.</div><div class='add'>+ * @idx: index of crc engine to get CRC from</div><div class='ctx'>  * @r_cr: CRC value for the red component.</div><div class='ctx'>  * @g_y:  CRC value for the green component.</div><div class='ctx'>  * @b_cb: CRC value for the blue component.</div><div class='hunk'>@@ -663,7 +780,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,</div><div class='ctx'>  * Return:</div><div class='ctx'>  * %false if stream is not found, or if CRCs are not enabled.</div><div class='ctx'>  */</div><div class='del'>-bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,</div><div class='add'>+bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t idx,</div><div class='ctx'> 		       uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -684,7 +801,7 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,</div><div class='ctx'> 	tg = pipe-&gt;stream_res.tg;</div><div class='ctx'> </div><div class='ctx'> 	if (tg-&gt;funcs-&gt;get_crc)</div><div class='del'>-		return tg-&gt;funcs-&gt;get_crc(tg, r_cr, g_y, b_cb);</div><div class='add'>+		return tg-&gt;funcs-&gt;get_crc(tg, idx, r_cr, g_y, b_cb);</div><div class='ctx'> 	DC_LOG_WARNING("CRC capture not supported.");</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -826,7 +943,8 @@ void dc_stream_set_static_screen_params(struct dc *dc,</div><div class='ctx'> static void dc_destruct(struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	// reset link encoder assignment table on destruct</div><div class='del'>-	if (dc-&gt;res_pool &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign)</div><div class='add'>+	if (dc-&gt;res_pool &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign &amp;&amp;</div><div class='add'>+			!dc-&gt;config.unify_link_enc_assignment)</div><div class='ctx'> 		link_enc_cfg_init(dc, dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;current_state) {</div><div class='hunk'>@@ -844,21 +962,24 @@ static void dc_destruct(struct dc *dc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dc_destroy_resource_pool(dc);</div><div class='del'>-</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	dc_destroy_soc_and_ip_translator(&amp;dc-&gt;soc_and_ip_translator);</div><div class='add'>+#endif</div><div class='ctx'> 	if (dc-&gt;link_srv)</div><div class='ctx'> 		link_destroy_link_service(&amp;dc-&gt;link_srv);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;ctx-&gt;gpio_service)</div><div class='del'>-		dal_gpio_service_destroy(&amp;dc-&gt;ctx-&gt;gpio_service);</div><div class='del'>-</div><div class='del'>-	if (dc-&gt;ctx-&gt;created_bios)</div><div class='del'>-		dal_bios_parser_destroy(&amp;dc-&gt;ctx-&gt;dc_bios);</div><div class='add'>+	if (dc-&gt;ctx) {</div><div class='add'>+		if (dc-&gt;ctx-&gt;gpio_service)</div><div class='add'>+			dal_gpio_service_destroy(&amp;dc-&gt;ctx-&gt;gpio_service);</div><div class='ctx'> </div><div class='del'>-	kfree(dc-&gt;ctx-&gt;logger);</div><div class='del'>-	dc_perf_trace_destroy(&amp;dc-&gt;ctx-&gt;perf_trace);</div><div class='add'>+		if (dc-&gt;ctx-&gt;created_bios)</div><div class='add'>+			dal_bios_parser_destroy(&amp;dc-&gt;ctx-&gt;dc_bios);</div><div class='add'>+		kfree(dc-&gt;ctx-&gt;logger);</div><div class='add'>+		dc_perf_trace_destroy(&amp;dc-&gt;ctx-&gt;perf_trace);</div><div class='ctx'> </div><div class='del'>-	kfree(dc-&gt;ctx);</div><div class='del'>-	dc-&gt;ctx = NULL;</div><div class='add'>+		kfree(dc-&gt;ctx);</div><div class='add'>+		dc-&gt;ctx = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(dc-&gt;bw_vbios);</div><div class='ctx'> 	dc-&gt;bw_vbios = NULL;</div><div class='hunk'>@@ -886,6 +1007,8 @@ static bool dc_construct_ctx(struct dc *dc,</div><div class='ctx'> 	if (!dc_ctx)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	dc_stream_init_rmcm_3dlut(dc);</div><div class='add'>+</div><div class='ctx'> 	dc_ctx-&gt;cgs_device = init_params-&gt;cgs_device;</div><div class='ctx'> 	dc_ctx-&gt;driver_context = init_params-&gt;driver;</div><div class='ctx'> 	dc_ctx-&gt;dc = dc;</div><div class='hunk'>@@ -977,12 +1100,17 @@ static bool dc_construct(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip = dcn_ip;</div><div class='ctx'> </div><div class='add'>+	if (init_params-&gt;bb_from_dmub)</div><div class='add'>+		dc-&gt;dml2_options.bb_from_dmub = init_params-&gt;bb_from_dmub;</div><div class='add'>+	else</div><div class='add'>+		dc-&gt;dml2_options.bb_from_dmub = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (!dc_construct_ctx(dc, init_params)) {</div><div class='ctx'> 		dm_error("%s: failed to create ctx\n", __func__);</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-        dc_ctx = dc-&gt;ctx;</div><div class='add'>+	dc_ctx = dc-&gt;ctx;</div><div class='ctx'> </div><div class='ctx'> 	/* Resource should construct all asic specific resources.</div><div class='ctx'> 	 * This should be the only place where we need to parse the asic id</div><div class='hunk'>@@ -1027,8 +1155,8 @@ static bool dc_construct(struct dc *dc,</div><div class='ctx'> 	/* set i2c speed if not done by the respective dcnxxx__resource.c */</div><div class='ctx'> 	if (dc-&gt;caps.i2c_speed_in_khz_hdcp == 0)</div><div class='ctx'> 		dc-&gt;caps.i2c_speed_in_khz_hdcp = dc-&gt;caps.i2c_speed_in_khz;</div><div class='del'>-	if (dc-&gt;caps.max_optimizable_video_width == 0)</div><div class='del'>-		dc-&gt;caps.max_optimizable_video_width = 5120;</div><div class='add'>+	if (dc-&gt;check_config.max_optimizable_video_width == 0)</div><div class='add'>+		dc-&gt;check_config.max_optimizable_video_width = 5120;</div><div class='ctx'> 	dc-&gt;clk_mgr = dc_clk_mgr_create(dc-&gt;ctx, dc-&gt;res_pool-&gt;pp_smu, dc-&gt;res_pool-&gt;dccg);</div><div class='ctx'> 	if (!dc-&gt;clk_mgr)</div><div class='ctx'> 		goto fail;</div><div class='hunk'>@@ -1040,6 +1168,9 @@ static bool dc_construct(struct dc *dc,</div><div class='ctx'> 		dc-&gt;res_pool-&gt;funcs-&gt;update_bw_bounding_box(dc, dc-&gt;clk_mgr-&gt;bw_params);</div><div class='ctx'> 		DC_FP_END();</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx-&gt;dce_version);</div><div class='add'>+	if (!dc-&gt;soc_and_ip_translator)</div><div class='add'>+		goto fail;</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	if (!create_links(dc, init_params-&gt;num_virtual_links))</div><div class='hunk'>@@ -1055,8 +1186,7 @@ static bool dc_construct(struct dc *dc,</div><div class='ctx'> 	 * is initialized in dc_create_resource_pool because</div><div class='ctx'> 	 * on creation it copies the contents of dc-&gt;dml</div><div class='ctx'> 	 */</div><div class='del'>-</div><div class='del'>-	dc-&gt;current_state = dc_state_create(dc);</div><div class='add'>+	dc-&gt;current_state = dc_state_create(dc, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (!dc-&gt;current_state) {</div><div class='ctx'> 		dm_error("%s: failed to create validate ctx\n", __func__);</div><div class='hunk'>@@ -1107,6 +1237,12 @@ static void apply_ctx_interdependent_lock(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='add'>+	if (dc-&gt;debug.visual_confirm &amp; VISUAL_CONFIRM_EXPLICIT) {</div><div class='add'>+		memcpy(&amp;pipe_ctx-&gt;visual_confirm_color, &amp;pipe_ctx-&gt;plane_state-&gt;visual_confirm_color,</div><div class='add'>+		sizeof(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_1_0) {</div><div class='ctx'> 		memset(&amp;pipe_ctx-&gt;visual_confirm_color, 0, sizeof(struct tg_color));</div><div class='ctx'> </div><div class='hunk'>@@ -1116,6 +1252,10 @@ static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *conte</div><div class='ctx'> 			get_surface_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='ctx'> 		else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)</div><div class='ctx'> 			get_surface_tile_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+		else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR)</div><div class='add'>+			get_cursor_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+		else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_DCC)</div><div class='add'>+			get_dcc_visual_confirm_color(dc, pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='ctx'> 		else {</div><div class='ctx'> 			if (dc-&gt;ctx-&gt;dce_version &lt; DCN_VERSION_2_0)</div><div class='ctx'> 				color_space_to_black_color(</div><div class='hunk'>@@ -1128,6 +1268,55 @@ static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *conte</div><div class='ctx'> 				get_subvp_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='ctx'> 			else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)</div><div class='ctx'> 				get_mclk_switch_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+			else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_FAMS2)</div><div class='add'>+				get_fams2_visual_confirm_color(dc, context, pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+			else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_VABC)</div><div class='add'>+				get_vabc_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_get_visual_confirm_for_stream(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_stream_state *stream_state,</div><div class='add'>+	struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_status *stream_status = dc_stream_get_status(stream_state);</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	int i;</div><div class='add'>+	struct dc_plane_state *plane_state = NULL;</div><div class='add'>+</div><div class='add'>+	if (!stream_status)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (dc-&gt;debug.visual_confirm) {</div><div class='add'>+	case VISUAL_CONFIRM_DISABLE:</div><div class='add'>+		return;</div><div class='add'>+	case VISUAL_CONFIRM_PSR:</div><div class='add'>+	case VISUAL_CONFIRM_FAMS:</div><div class='add'>+		pipe_ctx = dc_stream_get_pipe_ctx(stream_state);</div><div class='add'>+		if (!pipe_ctx)</div><div class='add'>+			return;</div><div class='add'>+		dc_dmub_srv_get_visual_confirm_color_cmd(dc, pipe_ctx);</div><div class='add'>+		memcpy(color, &amp;dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;visual_confirm_color, sizeof(struct tg_color));</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		/* find plane with highest layer_index */</div><div class='add'>+		for (i = 0; i &lt; stream_status-&gt;plane_count; i++) {</div><div class='add'>+			if (stream_status-&gt;plane_states[i]-&gt;visible)</div><div class='add'>+				plane_state = stream_status-&gt;plane_states[i];</div><div class='add'>+		}</div><div class='add'>+		if (!plane_state)</div><div class='add'>+			return;</div><div class='add'>+		/* find pipe that contains plane with highest layer index */</div><div class='add'>+		for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+			struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+			if (pipe-&gt;plane_state == plane_state) {</div><div class='add'>+				memcpy(color, &amp;pipe-&gt;visual_confirm_color, sizeof(struct tg_color));</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1190,13 +1379,8 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (is_phantom) {</div><div class='ctx'> 				if (tg-&gt;funcs-&gt;enable_crtc) {</div><div class='del'>-					int main_pipe_width, main_pipe_height;</div><div class='del'>-					struct dc_stream_state *old_paired_stream = dc_state_get_paired_subvp_stream(dc-&gt;current_state, old_stream);</div><div class='del'>-</div><div class='del'>-					main_pipe_width = old_paired_stream-&gt;dst.width;</div><div class='del'>-					main_pipe_height = old_paired_stream-&gt;dst.height;</div><div class='del'>-					if (dc-&gt;hwss.blank_phantom)</div><div class='del'>-						dc-&gt;hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);</div><div class='add'>+					if (dc-&gt;hwseq-&gt;funcs.blank_pixel_data)</div><div class='add'>+						dc-&gt;hwseq-&gt;funcs.blank_pixel_data(dc, pipe, true);</div><div class='ctx'> 					tg-&gt;funcs-&gt;enable_crtc(tg);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1208,7 +1392,8 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);</div><div class='ctx'> </div><div class='ctx'> 			if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='del'>-				set_p_state_switch_method(dc, context, pipe);</div><div class='add'>+				if (!dc-&gt;debug.using_dml2)</div><div class='add'>+					set_p_state_switch_method(dc, context, pipe);</div><div class='ctx'> 				dc_update_visual_confirm_color(dc, context, pipe);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -1218,6 +1403,9 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 				apply_ctx_interdependent_lock(dc, dc-&gt;current_state, old_stream, false);</div><div class='ctx'> 				dc-&gt;hwss.post_unlock_program_front_end(dc, dangling_context);</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;res_pool-&gt;funcs-&gt;prepare_mcache_programming)</div><div class='add'>+				dc-&gt;res_pool-&gt;funcs-&gt;prepare_mcache_programming(dc, dangling_context);</div><div class='ctx'> 			if (dc-&gt;hwss.program_front_end_for_ctx) {</div><div class='ctx'> 				dc-&gt;hwss.interdependent_update_lock(dc, dc-&gt;current_state, true);</div><div class='ctx'> 				dc-&gt;hwss.program_front_end_for_ctx(dc, dangling_context);</div><div class='hunk'>@@ -1272,7 +1460,7 @@ static void disable_vbios_mode_if_required(</div><div class='ctx'> </div><div class='ctx'> 		if (link != NULL &amp;&amp; link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc)) {</div><div class='ctx'> 			unsigned int enc_inst, tg_inst = 0;</div><div class='del'>-			unsigned int pix_clk_100hz;</div><div class='add'>+			unsigned int pix_clk_100hz = 0;</div><div class='ctx'> </div><div class='ctx'> 			enc_inst = link-&gt;link_enc-&gt;funcs-&gt;get_dig_frontend(link-&gt;link_enc);</div><div class='ctx'> 			if (enc_inst != ENGINE_ID_UNKNOWN) {</div><div class='hunk'>@@ -1302,80 +1490,6 @@ static void disable_vbios_mode_if_required(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * wait_for_blank_complete - wait for all active OPPs to finish pending blank</div><div class='del'>- * pattern updates</div><div class='del'>- *</div><div class='del'>- * @dc: [in] dc reference</div><div class='del'>- * @context: [in] hardware context in use</div><div class='del'>- */</div><div class='del'>-static void wait_for_blank_complete(struct dc *dc,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	struct pipe_ctx *opp_head;</div><div class='del'>-	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!hws-&gt;funcs.wait_for_blank_complete)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-		opp_head = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||</div><div class='del'>-				dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		hws-&gt;funcs.wait_for_blank_complete(opp_head-&gt;stream_res.opp);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	struct pipe_ctx *otg_master;</div><div class='del'>-	struct timing_generator *tg;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-		otg_master = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-		if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||</div><div class='del'>-				dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)</div><div class='del'>-			continue;</div><div class='del'>-		tg = otg_master-&gt;stream_res.tg;</div><div class='del'>-		if (tg-&gt;funcs-&gt;wait_odm_doublebuffer_pending_clear)</div><div class='del'>-			tg-&gt;funcs-&gt;wait_odm_doublebuffer_pending_clear(tg);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* ODM update may require to reprogram blank pattern for each OPP */</div><div class='del'>-	wait_for_blank_complete(dc, context);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	PERF_TRACE();</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-		int count = 0;</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (!pipe-&gt;plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		/* Timeout 100 ms */</div><div class='del'>-		while (count &lt; 100000) {</div><div class='del'>-			/* Must set to false to start with, due to OR in update function */</div><div class='del'>-			pipe-&gt;plane_state-&gt;status.is_flip_pending = false;</div><div class='del'>-			dc-&gt;hwss.update_pending_status(pipe);</div><div class='del'>-			if (!pipe-&gt;plane_state-&gt;status.is_flip_pending)</div><div class='del'>-				break;</div><div class='del'>-			udelay(1);</div><div class='del'>-			count++;</div><div class='del'>-		}</div><div class='del'>-		ASSERT(!pipe-&gt;plane_state-&gt;status.is_flip_pending);</div><div class='del'>-	}</div><div class='del'>-	PERF_TRACE();</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* Public functions */</div><div class='ctx'> </div><div class='ctx'> struct dc *dc_create(const struct dc_init_data *init_params)</div><div class='hunk'>@@ -1387,6 +1501,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (init_params-&gt;dce_environment == DCE_ENV_VIRTUAL_HW) {</div><div class='add'>+		dc-&gt;caps.linear_pitch_alignment = 64;</div><div class='ctx'> 		if (!dc_construct_ctx(dc, init_params))</div><div class='ctx'> 			goto destruct_dc;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1423,8 +1538,6 @@ struct dc *dc_create(const struct dc_init_data *init_params)</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_DC("Display Core initialized\n");</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> 	return dc;</div><div class='ctx'> </div><div class='ctx'> destruct_dc:</div><div class='hunk'>@@ -1462,6 +1575,7 @@ void dc_hardware_init(struct dc *dc)</div><div class='ctx'> 	detect_edp_presence(dc);</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment != DCE_ENV_VIRTUAL_HW)</div><div class='ctx'> 		dc-&gt;hwss.init_hw(dc);</div><div class='add'>+	dc_dmub_srv_notify_fw_dc_power_state(dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_init_callbacks(struct dc *dc,</div><div class='hunk'>@@ -1586,6 +1700,9 @@ static void program_timing_sync(</div><div class='ctx'> 		for (k = 0; k &lt; group_size; k++) {</div><div class='ctx'> 			struct dc_stream_status *status = dc_state_get_stream_status(ctx, pipe_set[k]-&gt;stream);</div><div class='ctx'> </div><div class='add'>+			if (!status)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='ctx'> 			status-&gt;timing_sync_info.group_id = num_group;</div><div class='ctx'> 			status-&gt;timing_sync_info.group_size = group_size;</div><div class='ctx'> 			if (k == 0)</div><div class='hunk'>@@ -1677,17 +1794,23 @@ bool dc_validate_boot_timing(const struct dc *dc,</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;debug.force_odm_combine)</div><div class='add'>+	if (dc-&gt;debug.force_odm_combine) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to force_odm_combine\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check for enabled DIG to identify enabled display */</div><div class='del'>-	if (!link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc))</div><div class='add'>+	if (!link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc)) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to disabled DIG\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	enc_inst = link-&gt;link_enc-&gt;funcs-&gt;get_dig_frontend(link-&gt;link_enc);</div><div class='ctx'> </div><div class='del'>-	if (enc_inst == ENGINE_ID_UNKNOWN)</div><div class='add'>+	if (enc_inst == ENGINE_ID_UNKNOWN) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to unknown DIG engine ID\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;stream_enc_count; i++) {</div><div class='ctx'> 		if (dc-&gt;res_pool-&gt;stream_enc[i]-&gt;id == enc_inst) {</div><div class='hunk'>@@ -1701,65 +1824,101 @@ bool dc_validate_boot_timing(const struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// tg_inst not found</div><div class='del'>-	if (i == dc-&gt;res_pool-&gt;stream_enc_count)</div><div class='add'>+	if (i == dc-&gt;res_pool-&gt;stream_enc_count) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to timing generator instance not found\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (tg_inst &gt;= dc-&gt;res_pool-&gt;timing_generator_count)</div><div class='add'>+	if (tg_inst &gt;= dc-&gt;res_pool-&gt;timing_generator_count) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to invalid timing generator count\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (tg_inst != link-&gt;link_enc-&gt;preferred_engine)</div><div class='add'>+	if (tg_inst != link-&gt;link_enc-&gt;preferred_engine) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to non-preferred timing generator\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	tg = dc-&gt;res_pool-&gt;timing_generators[tg_inst];</div><div class='ctx'> </div><div class='del'>-	if (!tg-&gt;funcs-&gt;get_hw_timing)</div><div class='add'>+	if (!tg-&gt;funcs-&gt;get_hw_timing) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to missing get_hw_timing callback\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (!tg-&gt;funcs-&gt;get_hw_timing(tg, &amp;hw_crtc_timing))</div><div class='add'>+	if (!tg-&gt;funcs-&gt;get_hw_timing(tg, &amp;hw_crtc_timing)) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to failed get_hw_timing return\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;h_total != hw_crtc_timing.h_total)</div><div class='add'>+	if (crtc_timing-&gt;h_total != hw_crtc_timing.h_total) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to h_total mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;h_border_left != hw_crtc_timing.h_border_left)</div><div class='add'>+	if (crtc_timing-&gt;h_border_left != hw_crtc_timing.h_border_left) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to h_border_left mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;h_addressable != hw_crtc_timing.h_addressable)</div><div class='add'>+	if (crtc_timing-&gt;h_addressable != hw_crtc_timing.h_addressable) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to h_addressable mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;h_border_right != hw_crtc_timing.h_border_right)</div><div class='add'>+	if (crtc_timing-&gt;h_border_right != hw_crtc_timing.h_border_right) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to h_border_right mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;h_front_porch != hw_crtc_timing.h_front_porch)</div><div class='add'>+	if (crtc_timing-&gt;h_front_porch != hw_crtc_timing.h_front_porch) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to h_front_porch mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;h_sync_width != hw_crtc_timing.h_sync_width)</div><div class='add'>+	if (crtc_timing-&gt;h_sync_width != hw_crtc_timing.h_sync_width) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to h_sync_width mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;v_total != hw_crtc_timing.v_total)</div><div class='add'>+	if (crtc_timing-&gt;v_total != hw_crtc_timing.v_total) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to v_total mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;v_border_top != hw_crtc_timing.v_border_top)</div><div class='add'>+	if (crtc_timing-&gt;v_border_top != hw_crtc_timing.v_border_top) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to v_border_top mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;v_addressable != hw_crtc_timing.v_addressable)</div><div class='add'>+	if (crtc_timing-&gt;v_addressable != hw_crtc_timing.v_addressable) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to v_addressable mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;v_border_bottom != hw_crtc_timing.v_border_bottom)</div><div class='add'>+	if (crtc_timing-&gt;v_border_bottom != hw_crtc_timing.v_border_bottom) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to v_border_bottom mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;v_front_porch != hw_crtc_timing.v_front_porch)</div><div class='add'>+	if (crtc_timing-&gt;v_front_porch != hw_crtc_timing.v_front_porch) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to v_front_porch mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (crtc_timing-&gt;v_sync_width != hw_crtc_timing.v_sync_width)</div><div class='add'>+	if (crtc_timing-&gt;v_sync_width != hw_crtc_timing.v_sync_width) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to v_sync_width mismatch\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* block DSC for now, as VBIOS does not currently support DSC timings */</div><div class='del'>-	if (crtc_timing-&gt;flags.DSC)</div><div class='add'>+	if (crtc_timing-&gt;flags.DSC) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to DSC\n");</div><div class='ctx'> 		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc_is_dp_signal(link-&gt;connector_signal)) {</div><div class='del'>-		unsigned int pix_clk_100hz;</div><div class='add'>+		unsigned int pix_clk_100hz = 0;</div><div class='ctx'> 		uint32_t numOdmPipes = 1;</div><div class='ctx'> 		uint32_t id_src[4] = {0};</div><div class='ctx'> </div><div class='hunk'>@@ -1771,33 +1930,60 @@ bool dc_validate_boot_timing(const struct dc *dc,</div><div class='ctx'> 			tg-&gt;funcs-&gt;get_optc_source(tg,</div><div class='ctx'> 						&amp;numOdmPipes, &amp;id_src[0], &amp;id_src[1]);</div><div class='ctx'> </div><div class='del'>-		if (numOdmPipes == 2)</div><div class='add'>+		if (numOdmPipes == 2) {</div><div class='ctx'> 			pix_clk_100hz *= 2;</div><div class='del'>-		if (numOdmPipes == 4)</div><div class='add'>+		} else if (numOdmPipes == 4) {</div><div class='ctx'> 			pix_clk_100hz *= 4;</div><div class='add'>+		} else if (se &amp;&amp; se-&gt;funcs-&gt;get_pixels_per_cycle) {</div><div class='add'>+			uint32_t pixels_per_cycle = se-&gt;funcs-&gt;get_pixels_per_cycle(se);</div><div class='add'>+</div><div class='add'>+			if (pixels_per_cycle != 1 &amp;&amp; !dc-&gt;debug.enable_dp_dig_pixel_rate_div_policy) {</div><div class='add'>+				DC_LOG_DEBUG("boot timing validation failed due to pixels_per_cycle\n");</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			pix_clk_100hz *= pixels_per_cycle;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		// Note: In rare cases, HW pixclk may differ from crtc's pixclk</div><div class='ctx'> 		// slightly due to rounding issues in 10 kHz units.</div><div class='del'>-		if (crtc_timing-&gt;pix_clk_100hz != pix_clk_100hz)</div><div class='add'>+		if (crtc_timing-&gt;pix_clk_100hz != pix_clk_100hz) {</div><div class='add'>+			DC_LOG_DEBUG("boot timing validation failed due to pix_clk_100hz mismatch\n");</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (!se-&gt;funcs-&gt;dp_get_pixel_format)</div><div class='add'>+		if (!se || !se-&gt;funcs-&gt;dp_get_pixel_format) {</div><div class='add'>+			DC_LOG_DEBUG("boot timing validation failed due to missing dp_get_pixel_format\n");</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!se-&gt;funcs-&gt;dp_get_pixel_format(</div><div class='ctx'> 			se,</div><div class='ctx'> 			&amp;hw_crtc_timing.pixel_encoding,</div><div class='del'>-			&amp;hw_crtc_timing.display_color_depth))</div><div class='add'>+			&amp;hw_crtc_timing.display_color_depth)) {</div><div class='add'>+			DC_LOG_DEBUG("boot timing validation failed due to dp_get_pixel_format failure\n");</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (hw_crtc_timing.display_color_depth != crtc_timing-&gt;display_color_depth)</div><div class='add'>+		if (hw_crtc_timing.display_color_depth != crtc_timing-&gt;display_color_depth) {</div><div class='add'>+			DC_LOG_DEBUG("boot timing validation failed due to display_color_depth mismatch\n");</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (hw_crtc_timing.pixel_encoding != crtc_timing-&gt;pixel_encoding)</div><div class='add'>+		if (hw_crtc_timing.pixel_encoding != crtc_timing-&gt;pixel_encoding) {</div><div class='add'>+			DC_LOG_DEBUG("boot timing validation failed due to pixel_encoding mismatch\n");</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to VSC SDP colorimetry\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {</div><div class='add'>+		DC_LOG_DEBUG("boot timing validation failed due to DP 128b/132b\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1887,6 +2073,41 @@ void dc_z10_save_init(struct dc *dc)</div><div class='ctx'> 		dc-&gt;hwss.z10_save_init(dc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Set a pipe unlock order based on the change in DET allocation and stores it in dc scratch memory</div><div class='add'>+ * Prevents over allocation of DET during unlock process</div><div class='add'>+ * e.g. 2 pipe config with different streams with a max of 20 DET segments</div><div class='add'>+ *	Before:								After:</div><div class='add'>+ *		- Pipe0: 10 DET segments			- Pipe0: 12 DET segments</div><div class='add'>+ *		- Pipe1: 10 DET segments			- Pipe1: 8 DET segments</div><div class='add'>+ * If Pipe0 gets updated first, 22 DET segments will be allocated</div><div class='add'>+ */</div><div class='add'>+static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+	struct timing_generator *tg = NULL;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;config.set_pipe_unlock_order)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(dc-&gt;scratch.pipes_to_unlock_first, 0, sizeof(dc-&gt;scratch.pipes_to_unlock_first));</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		tg = pipe-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+		if (!resource_is_pipe_type(pipe, OTG_MASTER) ||</div><div class='add'>+				!tg-&gt;funcs-&gt;is_tg_enabled(tg) ||</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (resource_calculate_det_for_stream(context, pipe) &lt;</div><div class='add'>+				resource_calculate_det_for_stream(dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i])) {</div><div class='add'>+			dc-&gt;scratch.pipes_to_unlock_first[i] = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * dc_commit_state_no_check - Apply context to the hardware</div><div class='ctx'>  *</div><div class='hunk'>@@ -1926,6 +2147,26 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 	if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb)) {</div><div class='ctx'> 		disable_vbios_mode_if_required(dc, context);</div><div class='ctx'> 		dc-&gt;hwss.enable_accelerated_mode(dc, context);</div><div class='add'>+	} else if (get_seamless_boot_stream_count(dc-&gt;current_state) &gt; 0) {</div><div class='add'>+		/* If the previous Stream still retains the apply seamless boot flag,</div><div class='add'>+		 * it means the OS has not actually performed a flip yet.</div><div class='add'>+		 * At this point, if we receive dc_commit_streams again, we should</div><div class='add'>+		 * once more check whether the actual HW timing matches what the OS</div><div class='add'>+		 * has provided</div><div class='add'>+		 */</div><div class='add'>+		disable_vbios_mode_if_required(dc, context);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwseq-&gt;funcs.wait_for_pipe_update_if_needed) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			//Only delay otg master for a given config</div><div class='add'>+			if (resource_is_pipe_type(pipe, OTG_MASTER)) {</div><div class='add'>+				//dc_commit_state_no_check is always a full update</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.wait_for_pipe_update_if_needed(dc, pipe, false);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (context-&gt;stream_count &gt; get_seamless_boot_stream_count(context) ||</div><div class='hunk'>@@ -1937,6 +2178,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='ctx'> 		dc-&gt;hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);</div><div class='add'>+	if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+		dc-&gt;hwss.dmub_hw_control_lock(dc, context, true);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;hwss.update_dsc_pg)</div><div class='ctx'> 		dc-&gt;hwss.update_dsc_pg(dc, context, false);</div><div class='hunk'>@@ -1965,8 +2208,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 		dc-&gt;hwss.wait_for_mpcc_disconnect(dc, dc-&gt;res_pool, pipe);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++)</div><div class='add'>+		dc_dmub_srv_control_cursor_offload(dc, dc-&gt;current_state, dc-&gt;current_state-&gt;streams[i], false);</div><div class='add'>+</div><div class='ctx'> 	result = dc-&gt;hwss.apply_ctx_to_hw(dc, context);</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='add'>+		dc_dmub_srv_control_cursor_offload(dc, context, context-&gt;streams[i], true);</div><div class='add'>+</div><div class='ctx'> 	if (result != DC_OK) {</div><div class='ctx'> 		/* Application of dc_state to hardware stopped. */</div><div class='ctx'> 		dc-&gt;current_state-&gt;res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;</div><div class='hunk'>@@ -1983,10 +2232,21 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 		context-&gt;streams[i]-&gt;update_flags.bits.dsc_changed = prev_dsc_changed;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	determine_pipe_unlock_order(dc, context);</div><div class='ctx'> 	/* Program all planes within new context*/</div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;prepare_mcache_programming)</div><div class='add'>+		dc-&gt;res_pool-&gt;funcs-&gt;prepare_mcache_programming(dc, context);</div><div class='ctx'> 	if (dc-&gt;hwss.program_front_end_for_ctx) {</div><div class='ctx'> 		dc-&gt;hwss.interdependent_update_lock(dc, context, true);</div><div class='ctx'> 		dc-&gt;hwss.program_front_end_for_ctx(dc, context);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;hwseq-&gt;funcs.set_wait_for_update_needed_for_pipe) {</div><div class='add'>+			for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+				pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.set_wait_for_update_needed_for_pipe(dc, pipe);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		dc-&gt;hwss.interdependent_update_lock(dc, context, false);</div><div class='ctx'> 		dc-&gt;hwss.post_unlock_program_front_end(dc, context);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1995,6 +2255,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 		dc-&gt;hwss.commit_subvp_config(dc, context);</div><div class='ctx'> 	if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='ctx'> 		dc-&gt;hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);</div><div class='add'>+	if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+		dc-&gt;hwss.dmub_hw_control_lock(dc, context, false);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		const struct dc_link *link = context-&gt;streams[i]-&gt;link;</div><div class='hunk'>@@ -2037,15 +2299,15 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> </div><div class='ctx'> 	dc_enable_stereo(dc, context, dc_streams, context-&gt;stream_count);</div><div class='ctx'> </div><div class='del'>-	if (context-&gt;stream_count &gt; get_seamless_boot_stream_count(context) ||</div><div class='add'>+	if (get_seamless_boot_stream_count(context) == 0 ||</div><div class='ctx'> 		context-&gt;stream_count == 0) {</div><div class='ctx'> 		/* Must wait for no flips to be pending before doing optimize bw */</div><div class='del'>-		wait_for_no_pipes_pending(dc, context);</div><div class='add'>+		hwss_wait_for_no_pipes_pending(dc, context);</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * optimized dispclk depends on ODM setup. Need to wait for ODM</div><div class='ctx'> 		 * update pending complete before optimizing bandwidth.</div><div class='ctx'> 		 */</div><div class='del'>-		wait_for_odm_update_pending_complete(dc, context);</div><div class='add'>+		hwss_wait_for_odm_update_pending_complete(dc, context);</div><div class='ctx'> 		/* pplib is notified if disp_num changed */</div><div class='ctx'> 		dc-&gt;hwss.optimize_bandwidth(dc, context);</div><div class='ctx'> 		/* Need to do otg sync again as otg could be out of sync due to otg</div><div class='hunk'>@@ -2085,15 +2347,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool commit_minimal_transition_state_legacy(struct dc *dc,</div><div class='add'>+static bool commit_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 		struct dc_state *transition_base_context);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dc_commit_streams - Commit current stream state</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: DC object with the commit state to be configured in the hardware</div><div class='del'>- * @streams: Array with a list of stream state</div><div class='del'>- * @stream_count: Total of streams</div><div class='add'>+ * @params: Parameters for the commit, including the streams to be committed</div><div class='ctx'>  *</div><div class='ctx'>  * Function responsible for commit streams change to the hardware.</div><div class='ctx'>  *</div><div class='hunk'>@@ -2101,9 +2362,7 @@ static bool commit_minimal_transition_state_legacy(struct dc *dc,</div><div class='ctx'>  * Return DC_OK if everything work as expected, otherwise, return a dc_status</div><div class='ctx'>  * code.</div><div class='ctx'>  */</div><div class='del'>-enum dc_status dc_commit_streams(struct dc *dc,</div><div class='del'>-				 struct dc_stream_state *streams[],</div><div class='del'>-				 uint8_t stream_count)</div><div class='add'>+enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	struct dc_state *context;</div><div class='hunk'>@@ -2112,19 +2371,32 @@ enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='ctx'> 	bool handle_exit_odm2to1 = false;</div><div class='ctx'> </div><div class='add'>+	if (!params)</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_VIRTUAL_HW)</div><div class='ctx'> 		return res;</div><div class='ctx'> </div><div class='del'>-	if (!streams_changed(dc, streams, stream_count))</div><div class='add'>+	if (!streams_changed(dc, params-&gt;streams, params-&gt;stream_count) &amp;&amp;</div><div class='add'>+			dc-&gt;current_state-&gt;power_source == params-&gt;power_source)</div><div class='ctx'> 		return res;</div><div class='ctx'> </div><div class='ctx'> 	dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> </div><div class='del'>-	DC_LOG_DC("%s: %d streams\n", __func__, stream_count);</div><div class='add'>+	DC_LOG_DC("%s: %d streams\n", __func__, params-&gt;stream_count);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; stream_count; i++) {</div><div class='del'>-		struct dc_stream_state *stream = streams[i];</div><div class='add'>+	for (i = 0; i &lt; params-&gt;stream_count; i++) {</div><div class='add'>+		struct dc_stream_state *stream = params-&gt;streams[i];</div><div class='ctx'> 		struct dc_stream_status *status = dc_stream_get_status(stream);</div><div class='add'>+		struct dc_sink *sink = stream-&gt;sink;</div><div class='add'>+</div><div class='add'>+		/* revalidate streams */</div><div class='add'>+		if (!dc_is_virtual_signal(sink-&gt;sink_signal)) {</div><div class='add'>+			res = dc_validate_stream(dc, stream);</div><div class='add'>+			if (res != DC_OK)</div><div class='add'>+				return res;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 		dc_stream_log(dc, stream);</div><div class='ctx'> </div><div class='hunk'>@@ -2141,7 +2413,7 @@ enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 	 * scenario, it uses extra pipes than needed to reduce power consumption</div><div class='ctx'> 	 * We need to switch off this feature to make room for new streams.</div><div class='ctx'> 	 */</div><div class='del'>-	if (stream_count &gt; dc-&gt;current_state-&gt;stream_count &amp;&amp;</div><div class='add'>+	if (params-&gt;stream_count &gt; dc-&gt;current_state-&gt;stream_count &amp;&amp;</div><div class='ctx'> 			dc-&gt;current_state-&gt;stream_count == 1) {</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -2151,30 +2423,55 @@ enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (handle_exit_odm2to1)</div><div class='del'>-		res = commit_minimal_transition_state_legacy(dc, dc-&gt;current_state);</div><div class='add'>+		res = commit_minimal_transition_state(dc, dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 	context = dc_state_create_current_copy(dc);</div><div class='ctx'> 	if (!context)</div><div class='ctx'> 		goto context_alloc_fail;</div><div class='ctx'> </div><div class='del'>-	res = dc_validate_with_context(dc, set, stream_count, context, false);</div><div class='add'>+	context-&gt;power_source = params-&gt;power_source;</div><div class='add'>+</div><div class='add'>+	res = dc_validate_with_context(dc, set, params-&gt;stream_count, context, DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Only update link encoder to stream assignment after bandwidth validation passed.</div><div class='add'>+	 */</div><div class='add'>+	if (res == DC_OK &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign &amp;&amp; !dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign(</div><div class='add'>+			dc, context, context-&gt;streams, context-&gt;stream_count);</div><div class='add'>+</div><div class='ctx'> 	if (res != DC_OK) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * If not already seamless, make transition seamless by inserting intermediate minimal transition</div><div class='add'>+	 */</div><div class='add'>+	if (dc-&gt;hwss.is_pipe_topology_transition_seamless &amp;&amp;</div><div class='add'>+			!dc-&gt;hwss.is_pipe_topology_transition_seamless(dc, dc-&gt;current_state, context)) {</div><div class='add'>+		res = commit_minimal_transition_state(dc, context);</div><div class='add'>+		if (res != DC_OK) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			goto fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	res = dc_commit_state_no_check(dc, context);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; stream_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; params-&gt;stream_count; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; context-&gt;stream_count; j++) {</div><div class='del'>-			if (streams[i]-&gt;stream_id == context-&gt;streams[j]-&gt;stream_id)</div><div class='del'>-				streams[i]-&gt;out.otg_offset = context-&gt;stream_status[j].primary_otg_inst;</div><div class='add'>+			if (params-&gt;streams[i]-&gt;stream_id == context-&gt;streams[j]-&gt;stream_id)</div><div class='add'>+				params-&gt;streams[i]-&gt;out.otg_offset = context-&gt;stream_status[j].primary_otg_inst;</div><div class='ctx'> </div><div class='del'>-			if (dc_is_embedded_signal(streams[i]-&gt;signal)) {</div><div class='del'>-				struct dc_stream_status *status = dc_state_get_stream_status(context, streams[i]);</div><div class='add'>+			if (dc_is_embedded_signal(params-&gt;streams[i]-&gt;signal)) {</div><div class='add'>+				struct dc_stream_status *status = dc_state_get_stream_status(context, params-&gt;streams[i]);</div><div class='add'>+</div><div class='add'>+				if (!status)</div><div class='add'>+					continue;</div><div class='ctx'> </div><div class='ctx'> 				if (dc-&gt;hwss.is_abm_supported)</div><div class='del'>-					status-&gt;is_abm_supported = dc-&gt;hwss.is_abm_supported(dc, context, streams[i]);</div><div class='add'>+					status-&gt;is_abm_supported = dc-&gt;hwss.is_abm_supported(dc, context, params-&gt;streams[i]);</div><div class='ctx'> 				else</div><div class='ctx'> 					status-&gt;is_abm_supported = true;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -2306,7 +2603,6 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;optimized_required = false;</div><div class='del'>-	dc-&gt;wm_optimized_required = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_set_generic_gpio_for_stereo(bool enable,</div><div class='hunk'>@@ -2375,47 +2671,50 @@ static bool is_surface_in_context(</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)</div><div class='add'>+static struct surface_update_descriptor get_plane_info_update_type(const struct dc_surface_update *u)</div><div class='ctx'> {</div><div class='ctx'> 	union surface_update_flags *update_flags = &amp;u-&gt;surface-&gt;update_flags;</div><div class='del'>-	enum surface_update_type update_type = UPDATE_TYPE_FAST;</div><div class='add'>+	struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };</div><div class='ctx'> </div><div class='ctx'> 	if (!u-&gt;plane_info)</div><div class='del'>-		return UPDATE_TYPE_FAST;</div><div class='add'>+		return update_type;</div><div class='add'>+</div><div class='add'>+	// `plane_info` present means at least `STREAM` lock is required</div><div class='add'>+	elevate_update_type(&amp;update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;color_space != u-&gt;surface-&gt;color_space) {</div><div class='ctx'> 		update_flags-&gt;bits.color_space_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;horizontal_mirror != u-&gt;surface-&gt;horizontal_mirror) {</div><div class='ctx'> 		update_flags-&gt;bits.horizontal_mirror_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;rotation != u-&gt;surface-&gt;rotation) {</div><div class='ctx'> 		update_flags-&gt;bits.rotation_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;format != u-&gt;surface-&gt;format) {</div><div class='ctx'> 		update_flags-&gt;bits.pixel_format_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;stereo_format != u-&gt;surface-&gt;stereo_format) {</div><div class='ctx'> 		update_flags-&gt;bits.stereo_format_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;per_pixel_alpha != u-&gt;surface-&gt;per_pixel_alpha) {</div><div class='ctx'> 		update_flags-&gt;bits.per_pixel_alpha_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;global_alpha_value != u-&gt;surface-&gt;global_alpha_value) {</div><div class='ctx'> 		update_flags-&gt;bits.global_alpha_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;dcc.enable != u-&gt;surface-&gt;dcc.enable</div><div class='hunk'>@@ -2427,7 +2726,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa</div><div class='ctx'> 		 * recalculate stutter period.</div><div class='ctx'> 		 */</div><div class='ctx'> 		update_flags-&gt;bits.dcc_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (resource_pixel_format_to_bpp(u-&gt;plane_info-&gt;format) !=</div><div class='hunk'>@@ -2436,30 +2735,41 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa</div><div class='ctx'> 		 * and DML calculation</div><div class='ctx'> 		 */</div><div class='ctx'> 		update_flags-&gt;bits.bpp_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;plane_info-&gt;plane_size.surface_pitch != u-&gt;surface-&gt;plane_size.surface_pitch</div><div class='ctx'> 			|| u-&gt;plane_info-&gt;plane_size.chroma_pitch != u-&gt;surface-&gt;plane_size.chroma_pitch) {</div><div class='ctx'> 		update_flags-&gt;bits.plane_size_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	const struct dc_tiling_info *tiling = &amp;u-&gt;plane_info-&gt;tiling_info;</div><div class='ctx'> </div><div class='del'>-	if (memcmp(&amp;u-&gt;plane_info-&gt;tiling_info, &amp;u-&gt;surface-&gt;tiling_info,</div><div class='del'>-			sizeof(union dc_tiling_info)) != 0) {</div><div class='add'>+	if (memcmp(tiling, &amp;u-&gt;surface-&gt;tiling_info, sizeof(*tiling)) != 0) {</div><div class='ctx'> 		update_flags-&gt;bits.swizzle_change = 1;</div><div class='del'>-		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED);</div><div class='del'>-</div><div class='del'>-		/* todo: below are HW dependent, we should add a hook to</div><div class='del'>-		 * DCE/N resource and validated there.</div><div class='del'>-		 */</div><div class='del'>-		if (u-&gt;plane_info-&gt;tiling_info.gfx9.swizzle != DC_SW_LINEAR) {</div><div class='del'>-			/* swizzled mode requires RQ to be setup properly,</div><div class='del'>-			 * thus need to run DML to calculate RQ settings</div><div class='del'>-			 */</div><div class='del'>-			update_flags-&gt;bits.bandwidth_change = 1;</div><div class='del'>-			elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL);</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+</div><div class='add'>+		switch (tiling-&gt;gfxversion) {</div><div class='add'>+		case DcGfxVersion9:</div><div class='add'>+		case DcGfxVersion10:</div><div class='add'>+		case DcGfxVersion11:</div><div class='add'>+			if (tiling-&gt;gfx9.swizzle != DC_SW_LINEAR) {</div><div class='add'>+				update_flags-&gt;bits.bandwidth_change = 1;</div><div class='add'>+				elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case DcGfxAddr3:</div><div class='add'>+			if (tiling-&gt;gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) {</div><div class='add'>+				update_flags-&gt;bits.bandwidth_change = 1;</div><div class='add'>+				elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case DcGfxVersion7:</div><div class='add'>+		case DcGfxVersion8:</div><div class='add'>+		case DcGfxVersionUnknown:</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2467,21 +2777,34 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa</div><div class='ctx'> 	return update_type;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum surface_update_type get_scaling_info_update_type(</div><div class='del'>-		const struct dc *dc,</div><div class='add'>+static struct surface_update_descriptor get_scaling_info_update_type(</div><div class='add'>+		const struct dc_check_config *check_config,</div><div class='ctx'> 		const struct dc_surface_update *u)</div><div class='ctx'> {</div><div class='ctx'> 	union surface_update_flags *update_flags = &amp;u-&gt;surface-&gt;update_flags;</div><div class='add'>+	struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };</div><div class='ctx'> </div><div class='ctx'> 	if (!u-&gt;scaling_info)</div><div class='del'>-		return UPDATE_TYPE_FAST;</div><div class='add'>+		return update_type;</div><div class='add'>+</div><div class='add'>+	// `scaling_info` present means at least `STREAM` lock is required</div><div class='add'>+	elevate_update_type(&amp;update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;scaling_info-&gt;dst_rect.width != u-&gt;surface-&gt;dst_rect.width</div><div class='add'>+	if (u-&gt;scaling_info-&gt;src_rect.width != u-&gt;surface-&gt;src_rect.width</div><div class='add'>+			|| u-&gt;scaling_info-&gt;src_rect.height != u-&gt;surface-&gt;src_rect.height</div><div class='add'>+			|| u-&gt;scaling_info-&gt;dst_rect.width != u-&gt;surface-&gt;dst_rect.width</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;dst_rect.height != u-&gt;surface-&gt;dst_rect.height</div><div class='add'>+			|| u-&gt;scaling_info-&gt;clip_rect.width != u-&gt;surface-&gt;clip_rect.width</div><div class='add'>+			|| u-&gt;scaling_info-&gt;clip_rect.height != u-&gt;surface-&gt;clip_rect.height</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;scaling_quality.integer_scaling !=</div><div class='del'>-				u-&gt;surface-&gt;scaling_quality.integer_scaling</div><div class='del'>-			) {</div><div class='add'>+					u-&gt;surface-&gt;scaling_quality.integer_scaling) {</div><div class='ctx'> 		update_flags-&gt;bits.scaling_change = 1;</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+</div><div class='add'>+		if (u-&gt;scaling_info-&gt;src_rect.width &gt; u-&gt;surface-&gt;src_rect.width</div><div class='add'>+				|| u-&gt;scaling_info-&gt;src_rect.height &gt; u-&gt;surface-&gt;src_rect.height)</div><div class='add'>+			/* Making src rect bigger requires a bandwidth change */</div><div class='add'>+			update_flags-&gt;bits.clock_change = 1;</div><div class='ctx'> </div><div class='ctx'> 		if ((u-&gt;scaling_info-&gt;dst_rect.width &lt; u-&gt;surface-&gt;dst_rect.width</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;dst_rect.height &lt; u-&gt;surface-&gt;dst_rect.height)</div><div class='hunk'>@@ -2489,155 +2812,169 @@ static enum surface_update_type get_scaling_info_update_type(</div><div class='ctx'> 					|| u-&gt;scaling_info-&gt;dst_rect.height &lt; u-&gt;surface-&gt;src_rect.height))</div><div class='ctx'> 			/* Making dst rect smaller requires a bandwidth change */</div><div class='ctx'> 			update_flags-&gt;bits.bandwidth_change = 1;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;scaling_info-&gt;src_rect.width != u-&gt;surface-&gt;src_rect.width</div><div class='del'>-		|| u-&gt;scaling_info-&gt;src_rect.height != u-&gt;surface-&gt;src_rect.height) {</div><div class='del'>-</div><div class='del'>-		update_flags-&gt;bits.scaling_change = 1;</div><div class='del'>-		if (u-&gt;scaling_info-&gt;src_rect.width &gt; u-&gt;surface-&gt;src_rect.width</div><div class='del'>-				|| u-&gt;scaling_info-&gt;src_rect.height &gt; u-&gt;surface-&gt;src_rect.height)</div><div class='del'>-			/* Making src rect bigger requires a bandwidth change */</div><div class='del'>-			update_flags-&gt;bits.clock_change = 1;</div><div class='add'>+		if (u-&gt;scaling_info-&gt;src_rect.width &gt; check_config-&gt;max_optimizable_video_width &amp;&amp;</div><div class='add'>+			(u-&gt;scaling_info-&gt;clip_rect.width &gt; u-&gt;surface-&gt;clip_rect.width ||</div><div class='add'>+			 u-&gt;scaling_info-&gt;clip_rect.height &gt; u-&gt;surface-&gt;clip_rect.height))</div><div class='add'>+			 /* Changing clip size of a large surface may result in MPC slice count change */</div><div class='add'>+			update_flags-&gt;bits.bandwidth_change = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;scaling_info-&gt;src_rect.width &gt; dc-&gt;caps.max_optimizable_video_width &amp;&amp;</div><div class='del'>-		(u-&gt;scaling_info-&gt;clip_rect.width &gt; u-&gt;surface-&gt;clip_rect.width ||</div><div class='del'>-		 u-&gt;scaling_info-&gt;clip_rect.height &gt; u-&gt;surface-&gt;clip_rect.height))</div><div class='del'>-		 /* Changing clip size of a large surface may result in MPC slice count change */</div><div class='del'>-		update_flags-&gt;bits.bandwidth_change = 1;</div><div class='del'>-</div><div class='del'>-	if (u-&gt;scaling_info-&gt;clip_rect.width != u-&gt;surface-&gt;clip_rect.width ||</div><div class='del'>-			u-&gt;scaling_info-&gt;clip_rect.height != u-&gt;surface-&gt;clip_rect.height)</div><div class='del'>-		update_flags-&gt;bits.clip_size_change = 1;</div><div class='del'>-</div><div class='ctx'> 	if (u-&gt;scaling_info-&gt;src_rect.x != u-&gt;surface-&gt;src_rect.x</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;src_rect.y != u-&gt;surface-&gt;src_rect.y</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;clip_rect.x != u-&gt;surface-&gt;clip_rect.x</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;clip_rect.y != u-&gt;surface-&gt;clip_rect.y</div><div class='ctx'> 			|| u-&gt;scaling_info-&gt;dst_rect.x != u-&gt;surface-&gt;dst_rect.x</div><div class='del'>-			|| u-&gt;scaling_info-&gt;dst_rect.y != u-&gt;surface-&gt;dst_rect.y)</div><div class='add'>+			|| u-&gt;scaling_info-&gt;dst_rect.y != u-&gt;surface-&gt;dst_rect.y) {</div><div class='add'>+		elevate_update_type(&amp;update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 		update_flags-&gt;bits.position_change = 1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (update_flags-&gt;bits.clock_change</div><div class='del'>-			|| update_flags-&gt;bits.bandwidth_change</div><div class='del'>-			|| update_flags-&gt;bits.scaling_change)</div><div class='del'>-		return UPDATE_TYPE_FULL;</div><div class='del'>-</div><div class='del'>-	if (update_flags-&gt;bits.position_change ||</div><div class='del'>-			update_flags-&gt;bits.clip_size_change)</div><div class='del'>-		return UPDATE_TYPE_MED;</div><div class='del'>-</div><div class='del'>-	return UPDATE_TYPE_FAST;</div><div class='add'>+	return update_type;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum surface_update_type det_surface_update(const struct dc *dc,</div><div class='del'>-		const struct dc_surface_update *u)</div><div class='add'>+static struct surface_update_descriptor det_surface_update(</div><div class='add'>+		const struct dc_check_config *check_config,</div><div class='add'>+		struct dc_surface_update *u)</div><div class='ctx'> {</div><div class='del'>-	const struct dc_state *context = dc-&gt;current_state;</div><div class='del'>-	enum surface_update_type type;</div><div class='del'>-	enum surface_update_type overall_type = UPDATE_TYPE_FAST;</div><div class='add'>+	struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };</div><div class='ctx'> 	union surface_update_flags *update_flags = &amp;u-&gt;surface-&gt;update_flags;</div><div class='ctx'> </div><div class='del'>-	if (!is_surface_in_context(context, u-&gt;surface) || u-&gt;surface-&gt;force_full_update) {</div><div class='add'>+	if (u-&gt;surface-&gt;force_full_update) {</div><div class='ctx'> 		update_flags-&gt;raw = 0xFFFFFFFF;</div><div class='del'>-		return UPDATE_TYPE_FULL;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+		return overall_type;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	update_flags-&gt;raw = 0; // Reset all flags</div><div class='ctx'> </div><div class='del'>-	type = get_plane_info_update_type(u);</div><div class='del'>-	elevate_update_type(&amp;overall_type, type);</div><div class='add'>+	struct surface_update_descriptor inner_type = get_plane_info_update_type(u);</div><div class='add'>+</div><div class='add'>+	elevate_update_type(&amp;overall_type, inner_type.update_type, inner_type.lock_descriptor);</div><div class='ctx'> </div><div class='del'>-	type = get_scaling_info_update_type(dc, u);</div><div class='del'>-	elevate_update_type(&amp;overall_type, type);</div><div class='add'>+	inner_type = get_scaling_info_update_type(check_config, u);</div><div class='add'>+	elevate_update_type(&amp;overall_type, inner_type.update_type, inner_type.lock_descriptor);</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;flip_addr) {</div><div class='ctx'> 		update_flags-&gt;bits.addr_update = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+</div><div class='ctx'> 		if (u-&gt;flip_addr-&gt;address.tmz_surface != u-&gt;surface-&gt;address.tmz_surface) {</div><div class='ctx'> 			update_flags-&gt;bits.tmz_changed = 1;</div><div class='del'>-			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL);</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	if (u-&gt;in_transfer_func)</div><div class='add'>+	if (u-&gt;in_transfer_func) {</div><div class='ctx'> 		update_flags-&gt;bits.in_transfer_func_change = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;input_csc_color_matrix)</div><div class='add'>+	if (u-&gt;input_csc_color_matrix) {</div><div class='ctx'> 		update_flags-&gt;bits.input_csc_change = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;coeff_reduction_factor)</div><div class='add'>+	if (u-&gt;coeff_reduction_factor) {</div><div class='ctx'> 		update_flags-&gt;bits.coeff_reduction_change = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;gamut_remap_matrix)</div><div class='add'>+	if (u-&gt;gamut_remap_matrix) {</div><div class='ctx'> 		update_flags-&gt;bits.gamut_remap_change = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;blend_tf)</div><div class='add'>+	if (u-&gt;blend_tf || (u-&gt;gamma &amp;&amp; dce_use_lut(u-&gt;plane_info ? u-&gt;plane_info-&gt;format : u-&gt;surface-&gt;format))) {</div><div class='ctx'> 		update_flags-&gt;bits.gamma_change = 1;</div><div class='del'>-</div><div class='del'>-	if (u-&gt;gamma) {</div><div class='del'>-		enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;</div><div class='del'>-</div><div class='del'>-		if (u-&gt;plane_info)</div><div class='del'>-			format = u-&gt;plane_info-&gt;format;</div><div class='del'>-		else if (u-&gt;surface)</div><div class='del'>-			format = u-&gt;surface-&gt;format;</div><div class='del'>-</div><div class='del'>-		if (dce_use_lut(format))</div><div class='del'>-			update_flags-&gt;bits.gamma_change = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (u-&gt;lut3d_func || u-&gt;func_shaper)</div><div class='add'>+	if (u-&gt;lut3d_func || u-&gt;func_shaper) {</div><div class='ctx'> 		update_flags-&gt;bits.lut_3d = 1;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (u-&gt;hdr_mult.value)</div><div class='ctx'> 		if (u-&gt;hdr_mult.value != u-&gt;surface-&gt;hdr_mult.value) {</div><div class='add'>+			// TODO: Should be fast?</div><div class='ctx'> 			update_flags-&gt;bits.hdr_mult = 1;</div><div class='del'>-			elevate_update_type(&amp;overall_type, UPDATE_TYPE_MED);</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-	if (update_flags-&gt;bits.in_transfer_func_change) {</div><div class='del'>-		type = UPDATE_TYPE_MED;</div><div class='del'>-		elevate_update_type(&amp;overall_type, type);</div><div class='add'>+	if (u-&gt;sdr_white_level_nits)</div><div class='add'>+		if (u-&gt;sdr_white_level_nits != u-&gt;surface-&gt;sdr_white_level_nits) {</div><div class='add'>+			// TODO: Should be fast?</div><div class='add'>+			update_flags-&gt;bits.sdr_white_level_nits = 1;</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	if (u-&gt;cm2_params) {</div><div class='add'>+		if (u-&gt;cm2_params-&gt;component_settings.shaper_3dlut_setting != u-&gt;surface-&gt;mcm_shaper_3dlut_setting</div><div class='add'>+				|| u-&gt;cm2_params-&gt;component_settings.lut1d_enable != u-&gt;surface-&gt;mcm_lut1d_enable</div><div class='add'>+				|| u-&gt;cm2_params-&gt;cm2_luts.lut3d_data.lut3d_src != u-&gt;surface-&gt;mcm_luts.lut3d_data.lut3d_src) {</div><div class='add'>+			update_flags-&gt;bits.mcm_transfer_function_enable_change = 1;</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (update_flags-&gt;bits.lut_3d) {</div><div class='del'>-		type = UPDATE_TYPE_FULL;</div><div class='del'>-		elevate_update_type(&amp;overall_type, type);</div><div class='add'>+	if (update_flags-&gt;bits.lut_3d &amp;&amp;</div><div class='add'>+			u-&gt;surface-&gt;mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;debug.enable_legacy_fast_update &amp;&amp;</div><div class='add'>+	if (check_config-&gt;enable_legacy_fast_update &amp;&amp;</div><div class='ctx'> 			(update_flags-&gt;bits.gamma_change ||</div><div class='ctx'> 			update_flags-&gt;bits.gamut_remap_change ||</div><div class='ctx'> 			update_flags-&gt;bits.input_csc_change ||</div><div class='ctx'> 			update_flags-&gt;bits.coeff_reduction_change)) {</div><div class='del'>-		type = UPDATE_TYPE_FULL;</div><div class='del'>-		elevate_update_type(&amp;overall_type, type);</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> 	return overall_type;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum surface_update_type check_update_surfaces_for_stream(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_surface_update *updates,</div><div class='del'>-		int surface_count,</div><div class='del'>-		struct dc_stream_update *stream_update,</div><div class='del'>-		const struct dc_stream_status *stream_status)</div><div class='add'>+/* May need to flip the desktop plane in cases where MPO plane receives a flip but desktop plane doesn't</div><div class='add'>+ * while both planes are flip_immediate</div><div class='add'>+ */</div><div class='add'>+static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count)</div><div class='ctx'> {</div><div class='add'>+	bool has_flip_immediate_plane = false;</div><div class='ctx'> 	int i;</div><div class='del'>-	enum surface_update_type overall_type = UPDATE_TYPE_FAST;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;idle_optimizations_allowed)</div><div class='del'>-		overall_type = UPDATE_TYPE_FULL;</div><div class='add'>+	for (i = 0; i &lt; surface_count; i++) {</div><div class='add'>+		if (updates[i].surface-&gt;flip_immediate) {</div><div class='add'>+			has_flip_immediate_plane = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (stream_status == NULL || stream_status-&gt;plane_count != surface_count)</div><div class='del'>-		overall_type = UPDATE_TYPE_FULL;</div><div class='add'>+	if (has_flip_immediate_plane &amp;&amp; surface_count &gt; 1) {</div><div class='add'>+		for (i = 0; i &lt; surface_count; i++) {</div><div class='add'>+			if (updates[i].surface-&gt;flip_immediate)</div><div class='add'>+				updates[i].surface-&gt;update_flags.bits.addr_update = 1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct surface_update_descriptor check_update_surfaces_for_stream(</div><div class='add'>+		const struct dc_check_config *check_config,</div><div class='add'>+		struct dc_surface_update *updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		struct dc_stream_update *stream_update)</div><div class='add'>+{</div><div class='add'>+	struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE };</div><div class='ctx'> </div><div class='ctx'> 	if (stream_update &amp;&amp; stream_update-&gt;pending_test_pattern) {</div><div class='del'>-		overall_type = UPDATE_TYPE_FULL;</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (stream_update &amp;&amp; stream_update-&gt;hw_cursor_req) {</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* some stream updates require passive update */</div><div class='ctx'> 	if (stream_update) {</div><div class='add'>+		elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+</div><div class='ctx'> 		union stream_update_flags *su_flags = &amp;stream_update-&gt;stream-&gt;update_flags;</div><div class='ctx'> </div><div class='ctx'> 		if ((stream_update-&gt;src.height != 0 &amp;&amp; stream_update-&gt;src.width != 0) ||</div><div class='hunk'>@@ -2645,14 +2982,16 @@ static enum surface_update_type check_update_surfaces_for_stream(</div><div class='ctx'> 			stream_update-&gt;integer_scaling_update)</div><div class='ctx'> 			su_flags-&gt;bits.scaling = 1;</div><div class='ctx'> </div><div class='del'>-		if (dc-&gt;debug.enable_legacy_fast_update &amp;&amp; stream_update-&gt;out_transfer_func)</div><div class='add'>+		if (check_config-&gt;enable_legacy_fast_update &amp;&amp; stream_update-&gt;out_transfer_func)</div><div class='ctx'> 			su_flags-&gt;bits.out_tf = 1;</div><div class='ctx'> </div><div class='ctx'> 		if (stream_update-&gt;abm_level)</div><div class='ctx'> 			su_flags-&gt;bits.abm_level = 1;</div><div class='ctx'> </div><div class='del'>-		if (stream_update-&gt;dpms_off)</div><div class='add'>+		if (stream_update-&gt;dpms_off) {</div><div class='ctx'> 			su_flags-&gt;bits.dpms_off = 1;</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL | LOCK_DESCRIPTOR_LINK);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (stream_update-&gt;gamut_remap)</div><div class='ctx'> 			su_flags-&gt;bits.gamut_remap = 1;</div><div class='hunk'>@@ -2666,29 +3005,41 @@ static enum surface_update_type check_update_surfaces_for_stream(</div><div class='ctx'> 		if (stream_update-&gt;mst_bw_update)</div><div class='ctx'> 			su_flags-&gt;bits.mst_bw = 1;</div><div class='ctx'> </div><div class='del'>-		if (stream_update-&gt;stream &amp;&amp; stream_update-&gt;stream-&gt;freesync_on_desktop &amp;&amp;</div><div class='add'>+		if (stream_update-&gt;stream-&gt;freesync_on_desktop &amp;&amp;</div><div class='ctx'> 			(stream_update-&gt;vrr_infopacket || stream_update-&gt;allow_freesync ||</div><div class='ctx'> 				stream_update-&gt;vrr_active_variable || stream_update-&gt;vrr_active_fixed))</div><div class='ctx'> 			su_flags-&gt;bits.fams_changed = 1;</div><div class='ctx'> </div><div class='del'>-		if (su_flags-&gt;raw != 0)</div><div class='del'>-			overall_type = UPDATE_TYPE_FULL;</div><div class='add'>+		if (stream_update-&gt;scaler_sharpener_update)</div><div class='add'>+			su_flags-&gt;bits.scaler_sharpener = 1;</div><div class='ctx'> </div><div class='del'>-		if (stream_update-&gt;output_csc_transform || stream_update-&gt;output_color_space)</div><div class='add'>+		if (stream_update-&gt;sharpening_required)</div><div class='add'>+			su_flags-&gt;bits.sharpening_required = 1;</div><div class='add'>+</div><div class='add'>+		if (stream_update-&gt;output_color_space)</div><div class='ctx'> 			su_flags-&gt;bits.out_csc = 1;</div><div class='ctx'> </div><div class='del'>-		/* Output transfer function changes do not require bandwidth recalculation,</div><div class='del'>-		 * so don't trigger a full update</div><div class='del'>-		 */</div><div class='del'>-		if (!dc-&gt;debug.enable_legacy_fast_update &amp;&amp; stream_update-&gt;out_transfer_func)</div><div class='add'>+		// TODO: Make each elevation explicit, as to not override fast stream in crct_timing_adjust</div><div class='add'>+		if (su_flags-&gt;raw)</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);</div><div class='add'>+</div><div class='add'>+		// Non-global cases</div><div class='add'>+		if (stream_update-&gt;output_csc_transform) {</div><div class='add'>+			su_flags-&gt;bits.out_csc = 1;</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!check_config-&gt;enable_legacy_fast_update &amp;&amp; stream_update-&gt;out_transfer_func) {</div><div class='ctx'> 			su_flags-&gt;bits.out_tf = 1;</div><div class='add'>+			elevate_update_type(&amp;overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0 ; i &lt; surface_count; i++) {</div><div class='del'>-		enum surface_update_type type =</div><div class='del'>-				det_surface_update(dc, &amp;updates[i]);</div><div class='add'>+	for (int i = 0 ; i &lt; surface_count; i++) {</div><div class='add'>+		struct surface_update_descriptor inner_type =</div><div class='add'>+				det_surface_update(check_config, &amp;updates[i]);</div><div class='ctx'> </div><div class='del'>-		elevate_update_type(&amp;overall_type, type);</div><div class='add'>+		elevate_update_type(&amp;overall_type, inner_type.update_type, inner_type.lock_descriptor);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return overall_type;</div><div class='hunk'>@@ -2699,46 +3050,18 @@ static enum surface_update_type check_update_surfaces_for_stream(</div><div class='ctx'>  *</div><div class='ctx'>  * See :c:type:`enum surface_update_type &lt;surface_update_type&gt;` for explanation of update types</div><div class='ctx'>  */</div><div class='del'>-enum surface_update_type dc_check_update_surfaces_for_stream(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+struct surface_update_descriptor dc_check_update_surfaces_for_stream(</div><div class='add'>+		const struct dc_check_config *check_config,</div><div class='ctx'> 		struct dc_surface_update *updates,</div><div class='ctx'> 		int surface_count,</div><div class='del'>-		struct dc_stream_update *stream_update,</div><div class='del'>-		const struct dc_stream_status *stream_status)</div><div class='add'>+		struct dc_stream_update *stream_update)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-	enum surface_update_type type;</div><div class='del'>-</div><div class='ctx'> 	if (stream_update)</div><div class='ctx'> 		stream_update-&gt;stream-&gt;update_flags.raw = 0;</div><div class='del'>-	for (i = 0; i &lt; surface_count; i++)</div><div class='add'>+	for (size_t i = 0; i &lt; surface_count; i++)</div><div class='ctx'> 		updates[i].surface-&gt;update_flags.raw = 0;</div><div class='ctx'> </div><div class='del'>-	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);</div><div class='del'>-	if (type == UPDATE_TYPE_FULL) {</div><div class='del'>-		if (stream_update) {</div><div class='del'>-			uint32_t dsc_changed = stream_update-&gt;stream-&gt;update_flags.bits.dsc_changed;</div><div class='del'>-			stream_update-&gt;stream-&gt;update_flags.raw = 0xFFFFFFFF;</div><div class='del'>-			stream_update-&gt;stream-&gt;update_flags.bits.dsc_changed = dsc_changed;</div><div class='del'>-		}</div><div class='del'>-		for (i = 0; i &lt; surface_count; i++)</div><div class='del'>-			updates[i].surface-&gt;update_flags.raw = 0xFFFFFFFF;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (type == UPDATE_TYPE_FAST) {</div><div class='del'>-		// If there's an available clock comparator, we use that.</div><div class='del'>-		if (dc-&gt;clk_mgr-&gt;funcs-&gt;are_clock_states_equal) {</div><div class='del'>-			if (!dc-&gt;clk_mgr-&gt;funcs-&gt;are_clock_states_equal(&amp;dc-&gt;clk_mgr-&gt;clks, &amp;dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk))</div><div class='del'>-				dc-&gt;optimized_required = true;</div><div class='del'>-		// Else we fallback to mem compare.</div><div class='del'>-		} else if (memcmp(&amp;dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk, &amp;dc-&gt;clk_mgr-&gt;clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {</div><div class='del'>-			dc-&gt;optimized_required = true;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		dc-&gt;optimized_required |= dc-&gt;wm_optimized_required;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return type;</div><div class='add'>+	return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct dc_stream_status *stream_get_status(</div><div class='hunk'>@@ -2818,55 +3141,66 @@ static void copy_surface_update_to_plane(</div><div class='ctx'> 				srf_update-&gt;plane_info-&gt;layer_index;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (srf_update-&gt;gamma &amp;&amp;</div><div class='del'>-			(surface-&gt;gamma_correction !=</div><div class='del'>-					srf_update-&gt;gamma)) {</div><div class='del'>-		memcpy(&amp;surface-&gt;gamma_correction-&gt;entries,</div><div class='add'>+	if (srf_update-&gt;gamma) {</div><div class='add'>+		memcpy(&amp;surface-&gt;gamma_correction.entries,</div><div class='ctx'> 			&amp;srf_update-&gt;gamma-&gt;entries,</div><div class='ctx'> 			sizeof(struct dc_gamma_entries));</div><div class='del'>-		surface-&gt;gamma_correction-&gt;is_identity =</div><div class='add'>+		surface-&gt;gamma_correction.is_identity =</div><div class='ctx'> 			srf_update-&gt;gamma-&gt;is_identity;</div><div class='del'>-		surface-&gt;gamma_correction-&gt;num_entries =</div><div class='add'>+		surface-&gt;gamma_correction.num_entries =</div><div class='ctx'> 			srf_update-&gt;gamma-&gt;num_entries;</div><div class='del'>-		surface-&gt;gamma_correction-&gt;type =</div><div class='add'>+		surface-&gt;gamma_correction.type =</div><div class='ctx'> 			srf_update-&gt;gamma-&gt;type;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (srf_update-&gt;in_transfer_func &amp;&amp;</div><div class='del'>-			(surface-&gt;in_transfer_func !=</div><div class='del'>-				srf_update-&gt;in_transfer_func)) {</div><div class='del'>-		surface-&gt;in_transfer_func-&gt;sdr_ref_white_level =</div><div class='add'>+	if (srf_update-&gt;in_transfer_func) {</div><div class='add'>+		surface-&gt;in_transfer_func.sdr_ref_white_level =</div><div class='ctx'> 			srf_update-&gt;in_transfer_func-&gt;sdr_ref_white_level;</div><div class='del'>-		surface-&gt;in_transfer_func-&gt;tf =</div><div class='add'>+		surface-&gt;in_transfer_func.tf =</div><div class='ctx'> 			srf_update-&gt;in_transfer_func-&gt;tf;</div><div class='del'>-		surface-&gt;in_transfer_func-&gt;type =</div><div class='add'>+		surface-&gt;in_transfer_func.type =</div><div class='ctx'> 			srf_update-&gt;in_transfer_func-&gt;type;</div><div class='del'>-		memcpy(&amp;surface-&gt;in_transfer_func-&gt;tf_pts,</div><div class='add'>+		memcpy(&amp;surface-&gt;in_transfer_func.tf_pts,</div><div class='ctx'> 			&amp;srf_update-&gt;in_transfer_func-&gt;tf_pts,</div><div class='ctx'> 			sizeof(struct dc_transfer_func_distributed_points));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (srf_update-&gt;func_shaper &amp;&amp;</div><div class='del'>-			(surface-&gt;in_shaper_func !=</div><div class='del'>-			srf_update-&gt;func_shaper))</div><div class='del'>-		memcpy(surface-&gt;in_shaper_func, srf_update-&gt;func_shaper,</div><div class='del'>-		sizeof(*surface-&gt;in_shaper_func));</div><div class='add'>+	if (srf_update-&gt;cm2_params) {</div><div class='add'>+		surface-&gt;mcm_shaper_3dlut_setting = srf_update-&gt;cm2_params-&gt;component_settings.shaper_3dlut_setting;</div><div class='add'>+		surface-&gt;mcm_lut1d_enable = srf_update-&gt;cm2_params-&gt;component_settings.lut1d_enable;</div><div class='add'>+		surface-&gt;mcm_luts = srf_update-&gt;cm2_params-&gt;cm2_luts;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (srf_update-&gt;func_shaper) {</div><div class='add'>+		memcpy(&amp;surface-&gt;in_shaper_func, srf_update-&gt;func_shaper,</div><div class='add'>+		sizeof(surface-&gt;in_shaper_func));</div><div class='add'>+</div><div class='add'>+		if (surface-&gt;mcm_shaper_3dlut_setting &gt;= DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER)</div><div class='add'>+			surface-&gt;mcm_luts.shaper = &amp;surface-&gt;in_shaper_func;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (srf_update-&gt;lut3d_func &amp;&amp;</div><div class='del'>-			(surface-&gt;lut3d_func !=</div><div class='del'>-			srf_update-&gt;lut3d_func))</div><div class='del'>-		memcpy(surface-&gt;lut3d_func, srf_update-&gt;lut3d_func,</div><div class='del'>-		sizeof(*surface-&gt;lut3d_func));</div><div class='add'>+	if (srf_update-&gt;lut3d_func)</div><div class='add'>+		memcpy(&amp;surface-&gt;lut3d_func, srf_update-&gt;lut3d_func,</div><div class='add'>+		sizeof(surface-&gt;lut3d_func));</div><div class='ctx'> </div><div class='ctx'> 	if (srf_update-&gt;hdr_mult.value)</div><div class='ctx'> 		surface-&gt;hdr_mult =</div><div class='ctx'> 				srf_update-&gt;hdr_mult;</div><div class='ctx'> </div><div class='del'>-	if (srf_update-&gt;blend_tf &amp;&amp;</div><div class='del'>-			(surface-&gt;blend_tf !=</div><div class='del'>-			srf_update-&gt;blend_tf))</div><div class='del'>-		memcpy(surface-&gt;blend_tf, srf_update-&gt;blend_tf,</div><div class='del'>-		sizeof(*surface-&gt;blend_tf));</div><div class='add'>+	if (srf_update-&gt;sdr_white_level_nits)</div><div class='add'>+		surface-&gt;sdr_white_level_nits =</div><div class='add'>+				srf_update-&gt;sdr_white_level_nits;</div><div class='add'>+</div><div class='add'>+	if (srf_update-&gt;blend_tf) {</div><div class='add'>+		memcpy(&amp;surface-&gt;blend_tf, srf_update-&gt;blend_tf,</div><div class='add'>+		sizeof(surface-&gt;blend_tf));</div><div class='add'>+</div><div class='add'>+		if (surface-&gt;mcm_lut1d_enable)</div><div class='add'>+			surface-&gt;mcm_luts.lut1d_func = &amp;surface-&gt;blend_tf;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (srf_update-&gt;cm2_params || srf_update-&gt;blend_tf)</div><div class='add'>+		surface-&gt;lut_bank_a = !surface-&gt;lut_bank_a;</div><div class='ctx'> </div><div class='ctx'> 	if (srf_update-&gt;input_csc_color_matrix)</div><div class='ctx'> 		surface-&gt;input_csc_color_matrix =</div><div class='hunk'>@@ -2879,6 +3213,14 @@ static void copy_surface_update_to_plane(</div><div class='ctx'> 	if (srf_update-&gt;gamut_remap_matrix)</div><div class='ctx'> 		surface-&gt;gamut_remap_matrix =</div><div class='ctx'> 			*srf_update-&gt;gamut_remap_matrix;</div><div class='add'>+</div><div class='add'>+	if (srf_update-&gt;cursor_csc_color_matrix)</div><div class='add'>+		surface-&gt;cursor_csc_color_matrix =</div><div class='add'>+			*srf_update-&gt;cursor_csc_color_matrix;</div><div class='add'>+</div><div class='add'>+	if (srf_update-&gt;bias_and_scale.bias_and_scale_valid)</div><div class='add'>+			surface-&gt;bias_and_scale =</div><div class='add'>+					srf_update-&gt;bias_and_scale;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void copy_stream_update_to_stream(struct dc *dc,</div><div class='hunk'>@@ -2897,14 +3239,13 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 	if (update-&gt;dst.height &amp;&amp; update-&gt;dst.width)</div><div class='ctx'> 		stream-&gt;dst = update-&gt;dst;</div><div class='ctx'> </div><div class='del'>-	if (update-&gt;out_transfer_func &amp;&amp;</div><div class='del'>-	    stream-&gt;out_transfer_func != update-&gt;out_transfer_func) {</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;sdr_ref_white_level =</div><div class='add'>+	if (update-&gt;out_transfer_func) {</div><div class='add'>+		stream-&gt;out_transfer_func.sdr_ref_white_level =</div><div class='ctx'> 			update-&gt;out_transfer_func-&gt;sdr_ref_white_level;</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;tf = update-&gt;out_transfer_func-&gt;tf;</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;type =</div><div class='add'>+		stream-&gt;out_transfer_func.tf = update-&gt;out_transfer_func-&gt;tf;</div><div class='add'>+		stream-&gt;out_transfer_func.type =</div><div class='ctx'> 			update-&gt;out_transfer_func-&gt;type;</div><div class='del'>-		memcpy(&amp;stream-&gt;out_transfer_func-&gt;tf_pts,</div><div class='add'>+		memcpy(&amp;stream-&gt;out_transfer_func.tf_pts,</div><div class='ctx'> 		       &amp;update-&gt;out_transfer_func-&gt;tf_pts,</div><div class='ctx'> 		       sizeof(struct dc_transfer_func_distributed_points));</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2934,6 +3275,9 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 	if (update-&gt;vrr_infopacket)</div><div class='ctx'> 		stream-&gt;vrr_infopacket = *update-&gt;vrr_infopacket;</div><div class='ctx'> </div><div class='add'>+	if (update-&gt;hw_cursor_req)</div><div class='add'>+		stream-&gt;hw_cursor_req = *update-&gt;hw_cursor_req;</div><div class='add'>+</div><div class='ctx'> 	if (update-&gt;allow_freesync)</div><div class='ctx'> 		stream-&gt;allow_freesync = *update-&gt;allow_freesync;</div><div class='ctx'> </div><div class='hunk'>@@ -2943,8 +3287,14 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 	if (update-&gt;vrr_active_fixed)</div><div class='ctx'> 		stream-&gt;vrr_active_fixed = *update-&gt;vrr_active_fixed;</div><div class='ctx'> </div><div class='del'>-	if (update-&gt;crtc_timing_adjust)</div><div class='add'>+	if (update-&gt;crtc_timing_adjust) {</div><div class='add'>+		if (stream-&gt;adjust.v_total_min != update-&gt;crtc_timing_adjust-&gt;v_total_min ||</div><div class='add'>+			stream-&gt;adjust.v_total_max != update-&gt;crtc_timing_adjust-&gt;v_total_max ||</div><div class='add'>+			stream-&gt;adjust.timing_adjust_pending)</div><div class='add'>+			update-&gt;crtc_timing_adjust-&gt;timing_adjust_pending = true;</div><div class='ctx'> 		stream-&gt;adjust = *update-&gt;crtc_timing_adjust;</div><div class='add'>+		update-&gt;crtc_timing_adjust-&gt;timing_adjust_pending = false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (update-&gt;dpms_off)</div><div class='ctx'> 		stream-&gt;dpms_off = *update-&gt;dpms_off;</div><div class='hunk'>@@ -2964,6 +3314,9 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 	if (update-&gt;adaptive_sync_infopacket)</div><div class='ctx'> 		stream-&gt;adaptive_sync_infopacket = *update-&gt;adaptive_sync_infopacket;</div><div class='ctx'> </div><div class='add'>+	if (update-&gt;avi_infopacket)</div><div class='add'>+		stream-&gt;avi_infopacket = *update-&gt;avi_infopacket;</div><div class='add'>+</div><div class='ctx'> 	if (update-&gt;dither_option)</div><div class='ctx'> 		stream-&gt;dither_option = *update-&gt;dither_option;</div><div class='ctx'> </div><div class='hunk'>@@ -2991,7 +3344,8 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 		if (dsc_validate_context) {</div><div class='ctx'> 			stream-&gt;timing.dsc_cfg = *update-&gt;dsc_config;</div><div class='ctx'> 			stream-&gt;timing.flags.DSC = enable_dsc;</div><div class='del'>-			if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, dsc_validate_context, true)) {</div><div class='add'>+			if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, dsc_validate_context,</div><div class='add'>+				DC_VALIDATE_MODE_ONLY) != DC_OK) {</div><div class='ctx'> 				stream-&gt;timing.dsc_cfg = old_dsc_cfg;</div><div class='ctx'> 				stream-&gt;timing.flags.DSC = old_dsc_enabled;</div><div class='ctx'> 				update-&gt;dsc_config = NULL;</div><div class='hunk'>@@ -3003,6 +3357,10 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 			update-&gt;dsc_config = NULL;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	if (update-&gt;scaler_sharpener_update)</div><div class='add'>+		stream-&gt;scaler_sharpener_update = *update-&gt;scaler_sharpener_update;</div><div class='add'>+	if (update-&gt;sharpening_required)</div><div class='add'>+		stream-&gt;sharpening_required = *update-&gt;sharpening_required;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void backup_planes_and_stream_state(</div><div class='hunk'>@@ -3016,15 +3374,9 @@ static void backup_planes_and_stream_state(</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; status-&gt;plane_count; i++) {</div><div class='del'>-		scratch-&gt;plane_states[i] = *status-&gt;plane_states[i];</div><div class='del'>-		scratch-&gt;gamma_correction[i] = *status-&gt;plane_states[i]-&gt;gamma_correction;</div><div class='del'>-		scratch-&gt;in_transfer_func[i] = *status-&gt;plane_states[i]-&gt;in_transfer_func;</div><div class='del'>-		scratch-&gt;lut3d_func[i] = *status-&gt;plane_states[i]-&gt;lut3d_func;</div><div class='del'>-		scratch-&gt;in_shaper_func[i] = *status-&gt;plane_states[i]-&gt;in_shaper_func;</div><div class='del'>-		scratch-&gt;blend_tf[i] = *status-&gt;plane_states[i]-&gt;blend_tf;</div><div class='add'>+		dc_plane_copy_config(&amp;scratch-&gt;plane_states[i], status-&gt;plane_states[i]);</div><div class='ctx'> 	}</div><div class='ctx'> 	scratch-&gt;stream_state = *stream;</div><div class='del'>-	scratch-&gt;out_transfer_func = *stream-&gt;out_transfer_func;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void restore_planes_and_stream_state(</div><div class='hunk'>@@ -3038,17 +3390,79 @@ static void restore_planes_and_stream_state(</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; status-&gt;plane_count; i++) {</div><div class='del'>-		*status-&gt;plane_states[i] = scratch-&gt;plane_states[i];</div><div class='del'>-		*status-&gt;plane_states[i]-&gt;gamma_correction = scratch-&gt;gamma_correction[i];</div><div class='del'>-		*status-&gt;plane_states[i]-&gt;in_transfer_func = scratch-&gt;in_transfer_func[i];</div><div class='del'>-		*status-&gt;plane_states[i]-&gt;lut3d_func = scratch-&gt;lut3d_func[i];</div><div class='del'>-		*status-&gt;plane_states[i]-&gt;in_shaper_func = scratch-&gt;in_shaper_func[i];</div><div class='del'>-		*status-&gt;plane_states[i]-&gt;blend_tf = scratch-&gt;blend_tf[i];</div><div class='add'>+		dc_plane_copy_config(status-&gt;plane_states[i], &amp;scratch-&gt;plane_states[i]);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	// refcount is persistent</div><div class='add'>+	struct kref temp_refcount = stream-&gt;refcount;</div><div class='ctx'> 	*stream = scratch-&gt;stream_state;</div><div class='del'>-	*stream-&gt;out_transfer_func = scratch-&gt;out_transfer_func;</div><div class='add'>+	stream-&gt;refcount = temp_refcount;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * update_seamless_boot_flags() - Helper function for updating seamless boot flags</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current DC state</div><div class='add'>+ * @context: New DC state to be programmed</div><div class='add'>+ * @surface_count: Number of surfaces that have an updated</div><div class='add'>+ * @stream: Corresponding stream to be updated in the current flip</div><div class='add'>+ *</div><div class='add'>+ * Updating seamless boot flags do not need to be part of the commit sequence. This</div><div class='add'>+ * helper function will update the seamless boot flags on each flip (if required)</div><div class='add'>+ * outside of the HW commit sequence (fast or slow).</div><div class='add'>+ *</div><div class='add'>+ * Return: void</div><div class='add'>+ */</div><div class='add'>+static void update_seamless_boot_flags(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		int surface_count,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	if (get_seamless_boot_stream_count(context) &gt; 0 &amp;&amp; (surface_count &gt; 0 || stream-&gt;dpms_off)) {</div><div class='add'>+		/* Optimize seamless boot flag keeps clocks and watermarks high until</div><div class='add'>+		 * first flip. After first flip, optimization is required to lower</div><div class='add'>+		 * bandwidth. Important to note that it is expected UEFI will</div><div class='add'>+		 * only light up a single display on POST, therefore we only expect</div><div class='add'>+		 * one stream with seamless boot flag set.</div><div class='add'>+		 */</div><div class='add'>+		if (stream-&gt;apply_seamless_boot_optimization) {</div><div class='add'>+			stream-&gt;apply_seamless_boot_optimization = false;</div><div class='add'>+</div><div class='add'>+			if (get_seamless_boot_stream_count(context) == 0)</div><div class='add'>+				dc-&gt;optimized_required = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool full_update_required_weak(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		const struct dc_stream_update *stream_update,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * update_planes_and_stream_state() - The function takes planes and stream</div><div class='add'>+ * updates as inputs and determines the appropriate update type. If update type</div><div class='add'>+ * is FULL, the function allocates a new context, populates and validates it.</div><div class='add'>+ * Otherwise, it updates current dc context. The function will return both</div><div class='add'>+ * new_context and new_update_type back to the caller. The function also backs</div><div class='add'>+ * up both current and new contexts into corresponding dc state scratch memory.</div><div class='add'>+ * TODO: The function does too many things, and even conditionally allocates dc</div><div class='add'>+ * context memory implicitly. We should consider to break it down.</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current DC state</div><div class='add'>+ * @srf_updates: an array of surface updates</div><div class='add'>+ * @surface_count: surface update count</div><div class='add'>+ * @stream: Corresponding stream to be updated</div><div class='add'>+ * @stream_update: stream update</div><div class='add'>+ * @new_update_type: [out] determined update type by the function</div><div class='add'>+ * @new_context: [out] new context allocated and validated if update type is</div><div class='add'>+ * FULL, reference to current context if update type is less than FULL.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if a valid update is populated into new_context, false</div><div class='add'>+ * otherwise.</div><div class='add'>+ */</div><div class='ctx'> static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 		struct dc_surface_update *srf_updates, int surface_count,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='hunk'>@@ -3072,9 +3486,18 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	context = dc-&gt;current_state;</div><div class='del'>-	backup_planes_and_stream_state(&amp;dc-&gt;current_state-&gt;scratch, stream);</div><div class='ctx'> 	update_type = dc_check_update_surfaces_for_stream(</div><div class='del'>-			dc, srf_updates, surface_count, stream_update, stream_status);</div><div class='add'>+			&amp;dc-&gt;check_config, srf_updates, surface_count, stream_update).update_type;</div><div class='add'>+	if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))</div><div class='add'>+		update_type = UPDATE_TYPE_FULL;</div><div class='add'>+</div><div class='add'>+	/* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream.</div><div class='add'>+	 * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip</div><div class='add'>+	 * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come.</div><div class='add'>+	 */</div><div class='add'>+	force_immediate_gsl_plane_flip(dc, srf_updates, surface_count);</div><div class='add'>+	if (update_type == UPDATE_TYPE_FULL)</div><div class='add'>+		backup_planes_and_stream_state(&amp;dc-&gt;scratch.current_state, stream);</div><div class='ctx'> </div><div class='ctx'> 	/* update current stream with the new updates */</div><div class='ctx'> 	copy_stream_update_to_stream(dc, context, stream, stream_update);</div><div class='hunk'>@@ -3099,6 +3522,16 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (update_type == UPDATE_TYPE_FULL) {</div><div class='add'>+		if (stream_update) {</div><div class='add'>+			uint32_t dsc_changed = stream_update-&gt;stream-&gt;update_flags.bits.dsc_changed;</div><div class='add'>+			stream_update-&gt;stream-&gt;update_flags.raw = 0xFFFFFFFF;</div><div class='add'>+			stream_update-&gt;stream-&gt;update_flags.bits.dsc_changed = dsc_changed;</div><div class='add'>+		}</div><div class='add'>+		for (i = 0; i &lt; surface_count; i++)</div><div class='add'>+			srf_updates[i].surface-&gt;update_flags.raw = 0xFFFFFFFF;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (update_type &gt;= update_surface_trace_level)</div><div class='ctx'> 		update_surface_trace(dc, srf_updates, surface_count);</div><div class='ctx'> </div><div class='hunk'>@@ -3143,7 +3576,9 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 	for (i = 0; i &lt; surface_count; i++) {</div><div class='ctx'> 		struct dc_plane_state *surface = srf_updates[i].surface;</div><div class='ctx'> </div><div class='del'>-		if (update_type &gt;= UPDATE_TYPE_MED) {</div><div class='add'>+		if (update_type != UPDATE_TYPE_MED)</div><div class='add'>+			continue;</div><div class='add'>+		if (surface-&gt;update_flags.bits.position_change) {</div><div class='ctx'> 			for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='ctx'> 				struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='ctx'> </div><div class='hunk'>@@ -3156,23 +3591,17 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (update_type == UPDATE_TYPE_FULL) {</div><div class='del'>-		if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, false)) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {</div><div class='ctx'> 			BREAK_TO_DEBUGGER();</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='del'>-			struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx,</div><div class='del'>-					context-&gt;streams[i]);</div><div class='del'>-</div><div class='del'>-			if (otg_master &amp;&amp; otg_master-&gt;stream-&gt;test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)</div><div class='del'>-				resource_build_test_pattern_params(&amp;context-&gt;res_ctx, otg_master);</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='add'>+	update_seamless_boot_flags(dc, context, surface_count, stream);</div><div class='ctx'> </div><div class='ctx'> 	*new_context = context;</div><div class='ctx'> 	*new_update_type = update_type;</div><div class='del'>-	backup_planes_and_stream_state(&amp;context-&gt;scratch, stream);</div><div class='add'>+	if (update_type == UPDATE_TYPE_FULL)</div><div class='add'>+		backup_planes_and_stream_state(&amp;dc-&gt;scratch.new_state, stream);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='hunk'>@@ -3206,7 +3635,8 @@ static void commit_planes_do_stream_update(struct dc *dc,</div><div class='ctx'> 					stream_update-&gt;vsp_infopacket ||</div><div class='ctx'> 					stream_update-&gt;hfvsif_infopacket ||</div><div class='ctx'> 					stream_update-&gt;adaptive_sync_infopacket ||</div><div class='del'>-					stream_update-&gt;vtem_infopacket) {</div><div class='add'>+					stream_update-&gt;vtem_infopacket ||</div><div class='add'>+					stream_update-&gt;avi_infopacket) {</div><div class='ctx'> 				resource_build_info_frame(pipe_ctx);</div><div class='ctx'> 				dc-&gt;hwss.update_info_frame(pipe_ctx);</div><div class='ctx'> </div><div class='hunk'>@@ -3243,6 +3673,11 @@ static void commit_planes_do_stream_update(struct dc *dc,</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='add'>+			if (stream_update-&gt;cursor_attributes)</div><div class='add'>+				program_cursor_attributes(dc, stream);</div><div class='add'>+</div><div class='add'>+			if (stream_update-&gt;cursor_position)</div><div class='add'>+				program_cursor_position(dc, stream);</div><div class='ctx'> </div><div class='ctx'> 			/* Full fe update*/</div><div class='ctx'> 			if (update_type == UPDATE_TYPE_FAST)</div><div class='hunk'>@@ -3255,18 +3690,32 @@ static void commit_planes_do_stream_update(struct dc *dc,</div><div class='ctx'> 				if (stream_update-&gt;mst_bw_update-&gt;is_increase)</div><div class='ctx'> 					dc-&gt;link_srv-&gt;increase_mst_payload(pipe_ctx,</div><div class='ctx'> 							stream_update-&gt;mst_bw_update-&gt;mst_stream_bw);</div><div class='del'>- 				else</div><div class='add'>+				else</div><div class='ctx'> 					dc-&gt;link_srv-&gt;reduce_mst_payload(pipe_ctx,</div><div class='ctx'> 							stream_update-&gt;mst_bw_update-&gt;mst_stream_bw);</div><div class='del'>- 			}</div><div class='add'>+			}</div><div class='ctx'> </div><div class='ctx'> 			if (stream_update-&gt;pending_test_pattern) {</div><div class='del'>-				dc_link_dp_set_test_pattern(stream-&gt;link,</div><div class='add'>+				/*</div><div class='add'>+				 * test pattern params depends on ODM topology</div><div class='add'>+				 * changes that we could be applying to front</div><div class='add'>+				 * end. Since at the current stage front end</div><div class='add'>+				 * changes are not yet applied. We can only</div><div class='add'>+				 * apply test pattern in hw based on current</div><div class='add'>+				 * state and populate the final test pattern</div><div class='add'>+				 * params in new state. If current and new test</div><div class='add'>+				 * pattern params are different as result of</div><div class='add'>+				 * different ODM topology being used, it will be</div><div class='add'>+				 * detected and handle during front end</div><div class='add'>+				 * programming update.</div><div class='add'>+				 */</div><div class='add'>+				dc-&gt;link_srv-&gt;dp_set_test_pattern(stream-&gt;link,</div><div class='ctx'> 					stream-&gt;test_pattern.type,</div><div class='ctx'> 					stream-&gt;test_pattern.color_space,</div><div class='ctx'> 					stream-&gt;test_pattern.p_link_settings,</div><div class='ctx'> 					stream-&gt;test_pattern.p_custom_pattern,</div><div class='ctx'> 					stream-&gt;test_pattern.cust_pattern_size);</div><div class='add'>+				resource_build_test_pattern_params(&amp;context-&gt;res_ctx, pipe_ctx);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			if (stream_update-&gt;dpms_off) {</div><div class='hunk'>@@ -3363,6 +3812,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,</div><div class='ctx'> 		if (srf_updates[i].surface-&gt;flip_immediate)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		update_dirty_rect-&gt;cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;</div><div class='ctx'> 		update_dirty_rect-&gt;dirty_rect_count = flip_addr-&gt;dirty_rect_count;</div><div class='ctx'> 		memcpy(update_dirty_rect-&gt;src_dirty_rects, flip_addr-&gt;dirty_rects,</div><div class='ctx'> 				sizeof(flip_addr-&gt;dirty_rects));</div><div class='hunk'>@@ -3437,6 +3887,15 @@ static void build_dmub_update_dirty_rect(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool check_address_only_update(union surface_update_flags update_flags)</div><div class='add'>+{</div><div class='add'>+	union surface_update_flags addr_only_update_flags;</div><div class='add'>+	addr_only_update_flags.raw = 0;</div><div class='add'>+	addr_only_update_flags.bits.addr_update = 1;</div><div class='add'>+</div><div class='add'>+	return update_flags.bits.addr_update &amp;&amp;</div><div class='add'>+			!(update_flags.raw &amp; ~addr_only_update_flags.raw);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB</div><div class='hunk'>@@ -3468,6 +3927,45 @@ static void build_dmub_cmd_list(struct dc *dc,</div><div class='ctx'> 	build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void commit_plane_for_stream_offload_fams2_flip(struct dc *dc,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	/* update dirty rect for PSR */</div><div class='add'>+	dc_dmub_update_dirty_rect(dc, surface_count, stream,</div><div class='add'>+			srf_updates, context);</div><div class='add'>+</div><div class='add'>+	/* Perform requested Updates */</div><div class='add'>+	for (i = 0; i &lt; surface_count; i++) {</div><div class='add'>+		struct dc_plane_state *plane_state = srf_updates[i].surface;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='add'>+			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='add'>+</div><div class='add'>+			if (!should_update_pipe_for_stream(context, pipe_ctx, stream))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			/* update pipe context for plane */</div><div class='add'>+			if (pipe_ctx-&gt;plane_state-&gt;update_flags.bits.addr_update)</div><div class='add'>+				dc-&gt;hwss.update_plane_addr(dc, pipe_ctx);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Send commands to DMCUB */</div><div class='add'>+	dc_dmub_srv_fams2_passthrough_flip(dc,</div><div class='add'>+				context,</div><div class='add'>+				stream,</div><div class='add'>+				srf_updates,</div><div class='add'>+				surface_count);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> 		struct dc_surface_update *srf_updates,</div><div class='ctx'> 		int surface_count,</div><div class='hunk'>@@ -3479,6 +3977,32 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	struct pipe_ctx *top_pipe_to_program = NULL;</div><div class='ctx'> 	struct dc_stream_status *stream_status = NULL;</div><div class='add'>+	bool should_offload_fams2_flip = false;</div><div class='add'>+	bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);</div><div class='add'>+</div><div class='add'>+	if (should_lock_all_pipes)</div><div class='add'>+		determine_pipe_unlock_order(dc, context);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.fams2_config.bits.enable &amp;&amp;</div><div class='add'>+			dc-&gt;debug.fams2_config.bits.enable_offload_flip &amp;&amp;</div><div class='add'>+			dc_state_is_fams2_in_use(dc, context)) {</div><div class='add'>+		/* if not offloading to HWFQ, offload to FAMS2 if needed */</div><div class='add'>+		should_offload_fams2_flip = true;</div><div class='add'>+		for (i = 0; i &lt; surface_count; i++) {</div><div class='add'>+			if (srf_updates[i].surface &amp;&amp;</div><div class='add'>+					srf_updates[i].surface-&gt;update_flags.raw &amp;&amp;</div><div class='add'>+					!check_address_only_update(srf_updates[i].surface-&gt;update_flags)) {</div><div class='add'>+				/* more than address update, need to acquire FAMS2 lock */</div><div class='add'>+				should_offload_fams2_flip = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (stream_update) {</div><div class='add'>+			/* more than address update, need to acquire FAMS2 lock */</div><div class='add'>+			should_offload_fams2_flip = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> </div><div class='ctx'> 	dc_z10_restore(dc);</div><div class='hunk'>@@ -3494,7 +4018,8 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='del'>-			set_p_state_switch_method(dc, context, pipe);</div><div class='add'>+			if (!dc-&gt;debug.using_dml2)</div><div class='add'>+				set_p_state_switch_method(dc, context, pipe);</div><div class='ctx'> </div><div class='ctx'> 			if (dc-&gt;debug.visual_confirm)</div><div class='ctx'> 				dc_update_visual_confirm_color(dc, context, pipe);</div><div class='hunk'>@@ -3509,13 +4034,14 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 			if (!pipe_ctx-&gt;plane_state)</div><div class='ctx'> 				continue;</div><div class='del'>-			if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))</div><div class='add'>+			if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))</div><div class='ctx'> 				continue;</div><div class='add'>+</div><div class='ctx'> 			pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips = false;</div><div class='ctx'> 			if (update_type == UPDATE_TYPE_FAST &amp;&amp;</div><div class='del'>-			    dc-&gt;hwss.program_triplebuffer &amp;&amp;</div><div class='del'>-			    !pipe_ctx-&gt;plane_state-&gt;flip_immediate &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='del'>-				/*triple buffer for VUpdate  only*/</div><div class='add'>+					dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp;</div><div class='add'>+					!pipe_ctx-&gt;plane_state-&gt;flip_immediate &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='add'>+				/*triple buffer for VUpdate only*/</div><div class='ctx'> 				pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips = true;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3523,23 +4049,33 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	stream_status = dc_state_get_stream_status(context, stream);</div><div class='ctx'> </div><div class='del'>-	build_dmub_cmd_list(dc,</div><div class='del'>-			srf_updates,</div><div class='del'>-			surface_count,</div><div class='del'>-			stream,</div><div class='del'>-			context,</div><div class='del'>-			context-&gt;dc_dmub_cmd,</div><div class='del'>-			&amp;(context-&gt;dmub_cmd_count));</div><div class='del'>-	hwss_build_fast_sequence(dc,</div><div class='del'>-			context-&gt;dc_dmub_cmd,</div><div class='del'>-			context-&gt;dmub_cmd_count,</div><div class='del'>-			context-&gt;block_sequence,</div><div class='del'>-			&amp;(context-&gt;block_sequence_steps),</div><div class='del'>-			top_pipe_to_program,</div><div class='del'>-			stream_status);</div><div class='del'>-	hwss_execute_sequence(dc,</div><div class='del'>-			context-&gt;block_sequence,</div><div class='del'>-			context-&gt;block_sequence_steps);</div><div class='add'>+	if (should_offload_fams2_flip) {</div><div class='add'>+		commit_plane_for_stream_offload_fams2_flip(dc,</div><div class='add'>+				srf_updates,</div><div class='add'>+				surface_count,</div><div class='add'>+				stream,</div><div class='add'>+				context);</div><div class='add'>+	} else if (stream_status) {</div><div class='add'>+		build_dmub_cmd_list(dc,</div><div class='add'>+				srf_updates,</div><div class='add'>+				surface_count,</div><div class='add'>+				stream,</div><div class='add'>+				context,</div><div class='add'>+				context-&gt;dc_dmub_cmd,</div><div class='add'>+				&amp;(context-&gt;dmub_cmd_count));</div><div class='add'>+		hwss_build_fast_sequence(dc,</div><div class='add'>+				context-&gt;dc_dmub_cmd,</div><div class='add'>+				context-&gt;dmub_cmd_count,</div><div class='add'>+				context-&gt;block_sequence,</div><div class='add'>+				&amp;(context-&gt;block_sequence_steps),</div><div class='add'>+				top_pipe_to_program,</div><div class='add'>+				stream_status,</div><div class='add'>+				context);</div><div class='add'>+		hwss_execute_sequence(dc,</div><div class='add'>+				context-&gt;block_sequence,</div><div class='add'>+				context-&gt;block_sequence_steps);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Clear update flags so next flip doesn't have redundant programming</div><div class='ctx'> 	 * (if there's no stream update, the update flags are not cleared).</div><div class='ctx'> 	 * Surface updates are cleared unconditionally at the beginning of each flip,</div><div class='hunk'>@@ -3549,47 +4085,6 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> 		top_pipe_to_program-&gt;stream-&gt;update_flags.raw = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)</div><div class='del'>-{</div><div class='del'>-/*</div><div class='del'>- * This function calls HWSS to wait for any potentially double buffered</div><div class='del'>- * operations to complete. It should be invoked as a pre-amble prior</div><div class='del'>- * to full update programming before asserting any HW locks.</div><div class='del'>- */</div><div class='del'>-	int pipe_idx;</div><div class='del'>-	int opp_inst;</div><div class='del'>-	int opp_count = dc-&gt;res_pool-&gt;res_cap-&gt;num_opp;</div><div class='del'>-	struct hubp *hubp;</div><div class='del'>-	int mpcc_inst;</div><div class='del'>-	const struct pipe_ctx *pipe_ctx;</div><div class='del'>-</div><div class='del'>-	for (pipe_idx = 0; pipe_idx &lt; dc-&gt;res_pool-&gt;pipe_count; pipe_idx++) {</div><div class='del'>-		pipe_ctx = &amp;dc_context-&gt;res_ctx.pipe_ctx[pipe_idx];</div><div class='del'>-</div><div class='del'>-		if (!pipe_ctx-&gt;stream)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_drr_doublebuffer_pending_clear)</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_drr_doublebuffer_pending_clear(pipe_ctx-&gt;stream_res.tg);</div><div class='del'>-</div><div class='del'>-		hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='del'>-		if (!hubp)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		mpcc_inst = hubp-&gt;inst;</div><div class='del'>-		// MPCC inst is equal to pipe index in practice</div><div class='del'>-		for (opp_inst = 0; opp_inst &lt; opp_count; opp_inst++) {</div><div class='del'>-			if ((dc-&gt;res_pool-&gt;opps[opp_inst] != NULL) &amp;&amp;</div><div class='del'>-				(dc-&gt;res_pool-&gt;opps[opp_inst]-&gt;mpcc_disconnect_pending[mpcc_inst])) {</div><div class='del'>-				dc-&gt;res_pool-&gt;mpc-&gt;funcs-&gt;wait_for_idle(dc-&gt;res_pool-&gt;mpc, mpcc_inst);</div><div class='del'>-				dc-&gt;res_pool-&gt;opps[opp_inst]-&gt;mpcc_disconnect_pending[mpcc_inst] = false;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	wait_for_odm_update_pending_complete(dc, dc_context);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 		struct dc_surface_update *srf_updates,</div><div class='ctx'> 		int surface_count,</div><div class='hunk'>@@ -3605,6 +4100,8 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	bool subvp_curr_use = false;</div><div class='ctx'> 	uint8_t current_stream_mask = 0;</div><div class='ctx'> </div><div class='add'>+	if (should_lock_all_pipes)</div><div class='add'>+		determine_pipe_unlock_order(dc, context);</div><div class='ctx'> 	// Once we apply the new subvp context to hardware it won't be in the</div><div class='ctx'> 	// dc-&gt;current_state anymore, so we have to cache it before we apply</div><div class='ctx'> 	// the new SubVP context</div><div class='hunk'>@@ -3612,14 +4109,18 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> </div><div class='ctx'> 	dc_z10_restore(dc);</div><div class='del'>-	if (update_type == UPDATE_TYPE_FULL)</div><div class='del'>-		wait_for_outstanding_hw_updates(dc, context);</div><div class='add'>+	if (update_type == UPDATE_TYPE_FULL &amp;&amp; dc-&gt;optimized_required)</div><div class='add'>+		hwss_process_outstanding_hw_updates(dc, dc-&gt;current_state);</div><div class='add'>+</div><div class='add'>+	if (update_type != UPDATE_TYPE_FAST &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;prepare_mcache_programming)</div><div class='add'>+		dc-&gt;res_pool-&gt;funcs-&gt;prepare_mcache_programming(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='del'>-			set_p_state_switch_method(dc, context, pipe);</div><div class='add'>+			if (!dc-&gt;debug.using_dml2)</div><div class='add'>+				set_p_state_switch_method(dc, context, pipe);</div><div class='ctx'> </div><div class='ctx'> 			if (dc-&gt;debug.visual_confirm)</div><div class='ctx'> 				dc_update_visual_confirm_color(dc, context, pipe);</div><div class='hunk'>@@ -3638,10 +4139,14 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 		context_clock_trace(dc, context);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (update_type == UPDATE_TYPE_FULL)</div><div class='add'>+		hwss_wait_for_outstanding_hw_updates(dc, dc-&gt;current_state);</div><div class='add'>+</div><div class='ctx'> 	top_pipe_to_program = resource_get_otg_master_for_stream(</div><div class='ctx'> 				&amp;context-&gt;res_ctx,</div><div class='ctx'> 				stream);</div><div class='ctx'> 	ASSERT(top_pipe_to_program != NULL);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='hunk'>@@ -3672,7 +4177,7 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	if ((update_type != UPDATE_TYPE_FAST) &amp;&amp; stream-&gt;update_flags.bits.dsc_changed)</div><div class='ctx'> 		if (top_pipe_to_program &amp;&amp;</div><div class='ctx'> 			top_pipe_to_program-&gt;stream_res.tg-&gt;funcs-&gt;lock_doublebuffer_enable) {</div><div class='del'>-			if (should_use_dmub_lock(stream-&gt;link)) {</div><div class='add'>+			if (should_use_dmub_inbox1_lock(dc, stream-&gt;link)) {</div><div class='ctx'> 				union dmub_hw_lock_flags hw_locks = { 0 };</div><div class='ctx'> 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -3688,14 +4193,28 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 						top_pipe_to_program-&gt;stream_res.tg);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;hwss.wait_for_dcc_meta_propagation) {</div><div class='add'>+		dc-&gt;hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwseq-&gt;funcs.wait_for_pipe_update_if_needed)</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type &lt; UPDATE_TYPE_FULL);</div><div class='add'>+</div><div class='ctx'> 	if (should_lock_all_pipes &amp;&amp; dc-&gt;hwss.interdependent_update_lock) {</div><div class='ctx'> 		if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='del'>-				dc-&gt;hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);</div><div class='del'>-		dc-&gt;hwss.interdependent_update_lock(dc, context, true);</div><div class='add'>+			dc-&gt;hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+			dc-&gt;hwss.dmub_hw_control_lock(dc, context, true);</div><div class='ctx'> </div><div class='add'>+		dc-&gt;hwss.interdependent_update_lock(dc, context, true);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='ctx'> 			dc-&gt;hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+			dc-&gt;hwss.dmub_hw_control_lock(dc, context, true);</div><div class='add'>+</div><div class='ctx'> 		/* Lock the top pipe while updating plane addrs, since freesync requires</div><div class='ctx'> 		 *  plane addr update event triggers to be synchronized.</div><div class='ctx'> 		 *  top_pipe_to_program is expected to never be NULL</div><div class='hunk'>@@ -3736,6 +4255,9 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 		if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='ctx'> 			dc-&gt;hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,</div><div class='ctx'> 							 NULL, subvp_prev_use);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+			dc-&gt;hwss.dmub_hw_control_lock(dc, context, false);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3758,24 +4280,26 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; surface_count; i++) {</div><div class='ctx'> 		struct dc_plane_state *plane_state = srf_updates[i].surface;</div><div class='add'>+</div><div class='ctx'> 		/*set logical flag for lock/unlock use*/</div><div class='ctx'> 		for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='ctx'> 			if (!pipe_ctx-&gt;plane_state)</div><div class='ctx'> 				continue;</div><div class='del'>-			if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))</div><div class='add'>+			if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))</div><div class='ctx'> 				continue;</div><div class='ctx'> 			pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips = false;</div><div class='ctx'> 			if (update_type == UPDATE_TYPE_FAST &amp;&amp;</div><div class='del'>-				dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp;</div><div class='del'>-				!pipe_ctx-&gt;plane_state-&gt;flip_immediate &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='del'>-					/*triple buffer for VUpdate  only*/</div><div class='del'>-					pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips = true;</div><div class='add'>+					dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp;</div><div class='add'>+					!pipe_ctx-&gt;plane_state-&gt;flip_immediate &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='add'>+				/*triple buffer for VUpdate only*/</div><div class='add'>+				pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips = true;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (update_type == UPDATE_TYPE_FULL) {</div><div class='ctx'> 			/* force vsync flip when reconfiguring pipes to prevent underflow */</div><div class='ctx'> 			plane_state-&gt;flip_immediate = false;</div><div class='add'>+			plane_state-&gt;triplebuffer_flips = false;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3795,23 +4319,45 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 			if (update_type == UPDATE_TYPE_FAST)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			ASSERT(!pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='del'>-</div><div class='del'>-			if (dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='del'>-				/*turn off triple buffer for full update*/</div><div class='del'>-				dc-&gt;hwss.program_triplebuffer(</div><div class='del'>-					dc, pipe_ctx, pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='del'>-			}</div><div class='ctx'> 			stream_status =</div><div class='ctx'> 				stream_get_status(context, pipe_ctx-&gt;stream);</div><div class='ctx'> </div><div class='del'>-			if (dc-&gt;hwss.apply_ctx_for_surface)</div><div class='add'>+			if (dc-&gt;hwss.apply_ctx_for_surface &amp;&amp; stream_status)</div><div class='ctx'> 				dc-&gt;hwss.apply_ctx_for_surface(</div><div class='ctx'> 					dc, pipe_ctx-&gt;stream, stream_status-&gt;plane_count, context);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx-&gt;plane_state)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Full fe update*/</div><div class='add'>+		if (update_type == UPDATE_TYPE_FAST)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		ASSERT(!pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='add'>+		if (dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='add'>+			/*turn off triple buffer for full update*/</div><div class='add'>+			dc-&gt;hwss.program_triplebuffer(</div><div class='add'>+				dc, pipe_ctx, pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;hwss.program_front_end_for_ctx &amp;&amp; update_type != UPDATE_TYPE_FAST) {</div><div class='ctx'> 		dc-&gt;hwss.program_front_end_for_ctx(dc, context);</div><div class='add'>+</div><div class='add'>+		//Pipe busy until some frame and line #</div><div class='add'>+		if (dc-&gt;hwseq-&gt;funcs.set_wait_for_update_needed_for_pipe &amp;&amp; update_type == UPDATE_TYPE_FULL) {</div><div class='add'>+			for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='add'>+				struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='add'>+</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.set_wait_for_update_needed_for_pipe(dc, pipe_ctx);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (dc-&gt;debug.validate_dml_output) {</div><div class='ctx'> 			for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 				struct pipe_ctx *cur_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -3861,9 +4407,17 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 				if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))</div><div class='ctx'> 					continue;</div><div class='ctx'> </div><div class='add'>+				if (srf_updates[i].cm2_params &amp;&amp;</div><div class='add'>+						srf_updates[i].cm2_params-&gt;cm2_luts.lut3d_data.lut3d_src ==</div><div class='add'>+								DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &amp;&amp;</div><div class='add'>+						srf_updates[i].cm2_params-&gt;component_settings.shaper_3dlut_setting ==</div><div class='add'>+								DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &amp;&amp;</div><div class='add'>+						dc-&gt;hwss.trigger_3dlut_dma_load)</div><div class='add'>+					dc-&gt;hwss.trigger_3dlut_dma_load(dc, pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 				/*program triple buffer after lock based on flip type*/</div><div class='ctx'> 				if (dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='del'>-					/*only enable triplebuffer for  fast_update*/</div><div class='add'>+					/*only enable triplebuffer for fast_update*/</div><div class='ctx'> 					dc-&gt;hwss.program_triplebuffer(</div><div class='ctx'> 						dc, pipe_ctx, pipe_ctx-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='ctx'> 				}</div><div class='hunk'>@@ -3880,7 +4434,8 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if ((update_type != UPDATE_TYPE_FAST) &amp;&amp; stream-&gt;update_flags.bits.dsc_changed)</div><div class='del'>-		if (top_pipe_to_program-&gt;stream_res.tg-&gt;funcs-&gt;lock_doublebuffer_enable) {</div><div class='add'>+		if (top_pipe_to_program &amp;&amp;</div><div class='add'>+		    top_pipe_to_program-&gt;stream_res.tg-&gt;funcs-&gt;lock_doublebuffer_enable) {</div><div class='ctx'> 			top_pipe_to_program-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(</div><div class='ctx'> 				top_pipe_to_program-&gt;stream_res.tg,</div><div class='ctx'> 				CRTC_STATE_VACTIVE);</div><div class='hunk'>@@ -3891,7 +4446,7 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 				top_pipe_to_program-&gt;stream_res.tg,</div><div class='ctx'> 				CRTC_STATE_VACTIVE);</div><div class='ctx'> </div><div class='del'>-			if (should_use_dmub_lock(stream-&gt;link)) {</div><div class='add'>+			if (should_use_dmub_inbox1_lock(dc, stream-&gt;link)) {</div><div class='ctx'> 				union dmub_hw_lock_flags hw_locks = { 0 };</div><div class='ctx'> 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -3939,9 +4494,13 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	if (should_lock_all_pipes &amp;&amp; dc-&gt;hwss.interdependent_update_lock) {</div><div class='ctx'> 		if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='ctx'> 			dc-&gt;hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);</div><div class='add'>+		if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+			dc-&gt;hwss.dmub_hw_control_lock(dc, context, false);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (dc-&gt;hwss.subvp_pipe_control_lock)</div><div class='ctx'> 			dc-&gt;hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);</div><div class='add'>+		if (dc-&gt;hwss.dmub_hw_control_lock)</div><div class='add'>+			dc-&gt;hwss.dmub_hw_control_lock(dc, context, false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// Fire manual trigger only when bottom plane is flipped</div><div class='hunk'>@@ -3957,6 +4516,8 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 				pipe_ctx-&gt;plane_state-&gt;skip_manual_trigger)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		if (dc-&gt;hwss.program_cursor_offload_now)</div><div class='add'>+			dc-&gt;hwss.program_cursor_offload_now(dc, pipe_ctx);</div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_manual_trigger)</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_manual_trigger(pipe_ctx-&gt;stream_res.tg);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4065,24 +4626,14 @@ struct pipe_split_policy_backup {</div><div class='ctx'> 	bool dynamic_odm_policy;</div><div class='ctx'> 	bool subvp_policy;</div><div class='ctx'> 	enum pipe_split_policy mpc_policy;</div><div class='add'>+	char force_odm[MAX_PIPES];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void release_minimal_transition_state(struct dc *dc,</div><div class='del'>-		struct dc_state *context, struct pipe_split_policy_backup *policy)</div><div class='del'>-{</div><div class='del'>-	dc_state_release(context);</div><div class='del'>-	/* restore previous pipe split and odm policy */</div><div class='del'>-	if (!dc-&gt;config.is_vmin_only_asic)</div><div class='del'>-		dc-&gt;debug.pipe_split_policy = policy-&gt;mpc_policy;</div><div class='del'>-	dc-&gt;debug.enable_single_display_2to1_odm_policy = policy-&gt;dynamic_odm_policy;</div><div class='del'>-	dc-&gt;debug.force_disable_subvp = policy-&gt;subvp_policy;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct dc_state *create_minimal_transition_state(struct dc *dc,</div><div class='del'>-		struct dc_state *base_context, struct pipe_split_policy_backup *policy)</div><div class='add'>+static void backup_and_set_minimal_pipe_split_policy(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_split_policy_backup *policy)</div><div class='ctx'> {</div><div class='del'>-	struct dc_state *minimal_transition_context = NULL;</div><div class='del'>-	unsigned int i, j;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc-&gt;config.is_vmin_only_asic) {</div><div class='ctx'> 		policy-&gt;mpc_policy = dc-&gt;debug.pipe_split_policy;</div><div class='hunk'>@@ -4092,97 +4643,259 @@ static struct dc_state *create_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 	dc-&gt;debug.enable_single_display_2to1_odm_policy = false;</div><div class='ctx'> 	policy-&gt;subvp_policy = dc-&gt;debug.force_disable_subvp;</div><div class='ctx'> 	dc-&gt;debug.force_disable_subvp = true;</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		policy-&gt;force_odm[i] = context-&gt;streams[i]-&gt;debug.force_odm_combine_segments;</div><div class='add'>+		if (context-&gt;streams[i]-&gt;debug.allow_transition_for_forced_odm)</div><div class='add'>+			context-&gt;streams[i]-&gt;debug.force_odm_combine_segments = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void restore_minimal_pipe_split_policy(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_split_policy_backup *policy)</div><div class='add'>+{</div><div class='add'>+	uint8_t i;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;config.is_vmin_only_asic)</div><div class='add'>+		dc-&gt;debug.pipe_split_policy = policy-&gt;mpc_policy;</div><div class='add'>+	dc-&gt;debug.enable_single_display_2to1_odm_policy =</div><div class='add'>+			policy-&gt;dynamic_odm_policy;</div><div class='add'>+	dc-&gt;debug.force_disable_subvp = policy-&gt;subvp_policy;</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='add'>+		context-&gt;streams[i]-&gt;debug.force_odm_combine_segments = policy-&gt;force_odm[i];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void release_minimal_transition_state(struct dc *dc,</div><div class='add'>+		struct dc_state *minimal_transition_context,</div><div class='add'>+		struct dc_state *base_context,</div><div class='add'>+		struct pipe_split_policy_backup *policy)</div><div class='add'>+{</div><div class='add'>+	restore_minimal_pipe_split_policy(dc, base_context, policy);</div><div class='add'>+	dc_state_release(minimal_transition_context);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void force_vsync_flip_in_minimal_transition_context(struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	uint8_t i;</div><div class='add'>+	int j;</div><div class='add'>+	struct dc_stream_status *stream_status;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		stream_status = &amp;context-&gt;stream_status[i];</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; stream_status-&gt;plane_count; j++)</div><div class='add'>+			stream_status-&gt;plane_states[j]-&gt;flip_immediate = false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dc_state *create_minimal_transition_state(struct dc *dc,</div><div class='add'>+		struct dc_state *base_context, struct pipe_split_policy_backup *policy)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *minimal_transition_context = NULL;</div><div class='ctx'> </div><div class='ctx'> 	minimal_transition_context = dc_state_create_copy(base_context);</div><div class='ctx'> 	if (!minimal_transition_context)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	backup_and_set_minimal_pipe_split_policy(dc, base_context, policy);</div><div class='ctx'> 	/* commit minimal state */</div><div class='del'>-	if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, minimal_transition_context, false)) {</div><div class='del'>-		for (i = 0; i &lt; minimal_transition_context-&gt;stream_count; i++) {</div><div class='del'>-			struct dc_stream_status *stream_status = &amp;minimal_transition_context-&gt;stream_status[i];</div><div class='del'>-</div><div class='del'>-			for (j = 0; j &lt; stream_status-&gt;plane_count; j++) {</div><div class='del'>-				struct dc_plane_state *plane_state = stream_status-&gt;plane_states[j];</div><div class='del'>-</div><div class='del'>-				/* force vsync flip when reconfiguring pipes to prevent underflow</div><div class='del'>-				 * and corruption</div><div class='del'>-				 */</div><div class='del'>-				plane_state-&gt;flip_immediate = false;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, minimal_transition_context,</div><div class='add'>+		DC_VALIDATE_MODE_AND_PROGRAMMING) == DC_OK) {</div><div class='add'>+		/* prevent underflow and corruption when reconfiguring pipes */</div><div class='add'>+		force_vsync_flip_in_minimal_transition_context(minimal_transition_context);</div><div class='ctx'> 	} else {</div><div class='del'>-		/* this should never happen */</div><div class='del'>-		release_minimal_transition_state(dc, minimal_transition_context, policy);</div><div class='add'>+		/*</div><div class='add'>+		 * This should never happen, minimal transition state should</div><div class='add'>+		 * always be validated first before adding pipe split features.</div><div class='add'>+		 */</div><div class='add'>+		release_minimal_transition_state(dc, minimal_transition_context, base_context, policy);</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='ctx'> 		minimal_transition_context = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	return minimal_transition_context;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool is_pipe_topology_transition_seamless_with_intermediate_step(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *initial_state,</div><div class='add'>+		struct dc_state *intermediate_state,</div><div class='add'>+		struct dc_state *final_state)</div><div class='add'>+{</div><div class='add'>+	return dc-&gt;hwss.is_pipe_topology_transition_seamless(dc, initial_state,</div><div class='add'>+			intermediate_state) &amp;&amp;</div><div class='add'>+			dc-&gt;hwss.is_pipe_topology_transition_seamless(dc,</div><div class='add'>+					intermediate_state, final_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void swap_and_release_current_context(struct dc *dc,</div><div class='add'>+		struct dc_state *new_context, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	int i;</div><div class='add'>+	struct dc_state *old = dc-&gt;current_state;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+</div><div class='add'>+	/* Since memory free requires elevated IRQ, an interrupt</div><div class='add'>+	 * request is generated by mem free. If this happens</div><div class='add'>+	 * between freeing and reassigning the context, our vsync</div><div class='add'>+	 * interrupt will call into dc and cause a memory</div><div class='add'>+	 * corruption. Hence, we first reassign the context,</div><div class='add'>+	 * then free the old context.</div><div class='add'>+	 */</div><div class='add'>+	dc-&gt;current_state = new_context;</div><div class='add'>+	dc_state_release(old);</div><div class='add'>+</div><div class='add'>+	// clear any forced full updates</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		pipe_ctx = &amp;new_context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;stream == stream)</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;force_full_update = false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int initialize_empty_surface_updates(</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_surface_update *srf_updates)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_status *status = dc_stream_get_status(stream);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!status)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; status-&gt;plane_count; i++)</div><div class='add'>+		srf_updates[i].surface = status-&gt;plane_states[i];</div><div class='add'>+</div><div class='add'>+	return status-&gt;plane_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool commit_minimal_transition_based_on_new_context(struct dc *dc,</div><div class='add'>+		struct dc_state *new_context,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count)</div><div class='add'>+{</div><div class='add'>+	bool success = false;</div><div class='add'>+	struct pipe_split_policy_backup policy;</div><div class='add'>+	struct dc_state *intermediate_context =</div><div class='add'>+			create_minimal_transition_state(dc, new_context,</div><div class='add'>+					&amp;policy);</div><div class='add'>+</div><div class='add'>+	if (intermediate_context) {</div><div class='add'>+		if (is_pipe_topology_transition_seamless_with_intermediate_step(</div><div class='add'>+				dc,</div><div class='add'>+				dc-&gt;current_state,</div><div class='add'>+				intermediate_context,</div><div class='add'>+				new_context)) {</div><div class='add'>+			DC_LOG_DC("commit minimal transition state: base = new state\n");</div><div class='add'>+			commit_planes_for_stream(dc, srf_updates,</div><div class='add'>+					surface_count, stream, NULL,</div><div class='add'>+					UPDATE_TYPE_FULL, intermediate_context);</div><div class='add'>+			swap_and_release_current_context(</div><div class='add'>+					dc, intermediate_context, stream);</div><div class='add'>+			dc_state_retain(dc-&gt;current_state);</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+		release_minimal_transition_state(</div><div class='add'>+				dc, intermediate_context, new_context, &amp;policy);</div><div class='add'>+	}</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool commit_minimal_transition_based_on_current_context(struct dc *dc,</div><div class='add'>+		struct dc_state *new_context, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	bool success = false;</div><div class='add'>+	struct pipe_split_policy_backup policy;</div><div class='add'>+	struct dc_state *intermediate_context;</div><div class='add'>+	struct dc_state *old_current_state = dc-&gt;current_state;</div><div class='add'>+	struct dc_surface_update srf_updates[MAX_SURFACES] = {0};</div><div class='add'>+	int surface_count;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Both current and new contexts share the same stream and plane state</div><div class='add'>+	 * pointers. When new context is validated, stream and planes get</div><div class='add'>+	 * populated with new updates such as new plane addresses. This makes</div><div class='add'>+	 * the current context no longer valid because stream and planes are</div><div class='add'>+	 * modified from the original. We backup current stream and plane states</div><div class='add'>+	 * into scratch space whenever we are populating new context. So we can</div><div class='add'>+	 * restore the original values back by calling the restore function now.</div><div class='add'>+	 * This restores back the original stream and plane states associated</div><div class='add'>+	 * with the current state.</div><div class='add'>+	 */</div><div class='add'>+	restore_planes_and_stream_state(&amp;dc-&gt;scratch.current_state, stream);</div><div class='add'>+	dc_state_retain(old_current_state);</div><div class='add'>+	intermediate_context = create_minimal_transition_state(dc,</div><div class='add'>+			old_current_state, &amp;policy);</div><div class='add'>+</div><div class='add'>+	if (intermediate_context) {</div><div class='add'>+		if (is_pipe_topology_transition_seamless_with_intermediate_step(</div><div class='add'>+				dc,</div><div class='add'>+				dc-&gt;current_state,</div><div class='add'>+				intermediate_context,</div><div class='add'>+				new_context)) {</div><div class='add'>+			DC_LOG_DC("commit minimal transition state: base = current state\n");</div><div class='add'>+			surface_count = initialize_empty_surface_updates(</div><div class='add'>+					stream, srf_updates);</div><div class='add'>+			commit_planes_for_stream(dc, srf_updates,</div><div class='add'>+					surface_count, stream, NULL,</div><div class='add'>+					UPDATE_TYPE_FULL, intermediate_context);</div><div class='add'>+			swap_and_release_current_context(</div><div class='add'>+					dc, intermediate_context, stream);</div><div class='add'>+			dc_state_retain(dc-&gt;current_state);</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+		release_minimal_transition_state(dc, intermediate_context,</div><div class='add'>+				old_current_state, &amp;policy);</div><div class='add'>+	}</div><div class='add'>+	dc_state_release(old_current_state);</div><div class='add'>+	/*</div><div class='add'>+	 * Restore stream and plane states back to the values associated with</div><div class='add'>+	 * new context.</div><div class='add'>+	 */</div><div class='add'>+	restore_planes_and_stream_state(&amp;dc-&gt;scratch.new_state, stream);</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * commit_minimal_transition_state - Commit a minimal state based on current or new context</div><div class='add'>+ * commit_minimal_transition_state_in_dc_update - Commit a minimal state based</div><div class='add'>+ * on current or new context</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: DC structure, used to get the current state</div><div class='del'>- * @context: New context</div><div class='add'>+ * @new_context: New context</div><div class='ctx'>  * @stream: Stream getting the update for the flip</div><div class='add'>+ * @srf_updates: Surface updates</div><div class='add'>+ * @surface_count: Number of surfaces</div><div class='ctx'>  *</div><div class='del'>- * The function takes in current state and new state and determine a minimal transition state</div><div class='del'>- * as the intermediate step which could make the transition between current and new states</div><div class='del'>- * seamless. If found, it will commit the minimal transition state and update current state to</div><div class='del'>- * this minimal transition state and return true, if not, it will return false.</div><div class='add'>+ * The function takes in current state and new state and determine a minimal</div><div class='add'>+ * transition state as the intermediate step which could make the transition</div><div class='add'>+ * between current and new states seamless. If found, it will commit the minimal</div><div class='add'>+ * transition state and update current state to this minimal transition state</div><div class='add'>+ * and return true, if not, it will return false.</div><div class='ctx'>  *</div><div class='ctx'>  * Return:</div><div class='ctx'>  * Return True if the minimal transition succeeded, false otherwise</div><div class='ctx'>  */</div><div class='del'>-static bool commit_minimal_transition_state(struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	bool success = false;</div><div class='del'>-	struct dc_state *minimal_transition_context;</div><div class='del'>-	struct pipe_split_policy_backup policy;</div><div class='del'>-</div><div class='del'>-	/* commit based on new context */</div><div class='del'>-	minimal_transition_context = create_minimal_transition_state(dc,</div><div class='del'>-			context, &amp;policy);</div><div class='del'>-	if (minimal_transition_context) {</div><div class='del'>-		if (dc-&gt;hwss.is_pipe_topology_transition_seamless(</div><div class='del'>-					dc, dc-&gt;current_state, minimal_transition_context) &amp;&amp;</div><div class='del'>-			dc-&gt;hwss.is_pipe_topology_transition_seamless(</div><div class='del'>-					dc, minimal_transition_context, context)) {</div><div class='del'>-			DC_LOG_DC("%s base = new state\n", __func__);</div><div class='del'>-</div><div class='del'>-			success = dc_commit_state_no_check(dc, minimal_transition_context) == DC_OK;</div><div class='del'>-		}</div><div class='del'>-		release_minimal_transition_state(dc, minimal_transition_context, &amp;policy);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!success) {</div><div class='del'>-		/* commit based on current context */</div><div class='del'>-		restore_planes_and_stream_state(&amp;dc-&gt;current_state-&gt;scratch, stream);</div><div class='del'>-		minimal_transition_context = create_minimal_transition_state(dc,</div><div class='del'>-				dc-&gt;current_state, &amp;policy);</div><div class='del'>-		if (minimal_transition_context) {</div><div class='del'>-			if (dc-&gt;hwss.is_pipe_topology_transition_seamless(</div><div class='del'>-					dc, dc-&gt;current_state, minimal_transition_context) &amp;&amp;</div><div class='del'>-				dc-&gt;hwss.is_pipe_topology_transition_seamless(</div><div class='del'>-						dc, minimal_transition_context, context)) {</div><div class='del'>-				DC_LOG_DC("%s base = current state\n", __func__);</div><div class='del'>-				success = dc_commit_state_no_check(dc, minimal_transition_context) == DC_OK;</div><div class='del'>-			}</div><div class='del'>-			release_minimal_transition_state(dc, minimal_transition_context, &amp;policy);</div><div class='del'>-		}</div><div class='del'>-		restore_planes_and_stream_state(&amp;context-&gt;scratch, stream);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ASSERT(success);</div><div class='add'>+static bool commit_minimal_transition_state_in_dc_update(struct dc *dc,</div><div class='add'>+		struct dc_state *new_context,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count)</div><div class='add'>+{</div><div class='add'>+	bool success = commit_minimal_transition_based_on_new_context(</div><div class='add'>+				dc, new_context, stream, srf_updates,</div><div class='add'>+				surface_count);</div><div class='add'>+	if (!success)</div><div class='add'>+		success = commit_minimal_transition_based_on_current_context(dc,</div><div class='add'>+				new_context, stream);</div><div class='add'>+	if (!success)</div><div class='add'>+		DC_LOG_ERROR("Fail to commit a seamless minimal transition state between current and new states.\nThis pipe topology update is non-seamless!\n");</div><div class='ctx'> 	return success;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * commit_minimal_transition_state_legacy - Create a transition pipe split state</div><div class='add'>+ * commit_minimal_transition_state - Create a transition pipe split state</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: Used to get the current state status</div><div class='ctx'>  * @transition_base_context: New transition state</div><div class='hunk'>@@ -4199,7 +4912,7 @@ static bool commit_minimal_transition_state(struct dc *dc,</div><div class='ctx'>  * Return:</div><div class='ctx'>  * Return false if something is wrong in the transition state.</div><div class='ctx'>  */</div><div class='del'>-static bool commit_minimal_transition_state_legacy(struct dc *dc,</div><div class='add'>+static bool commit_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 		struct dc_state *transition_base_context)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_state *transition_context;</div><div class='hunk'>@@ -4260,12 +4973,14 @@ static bool commit_minimal_transition_state_legacy(struct dc *dc,</div><div class='ctx'> 			dc-&gt;debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC in Use" :</div><div class='ctx'> 			"Unknown");</div><div class='ctx'> </div><div class='add'>+	dc_state_retain(transition_base_context);</div><div class='ctx'> 	transition_context = create_minimal_transition_state(dc,</div><div class='ctx'> 			transition_base_context, &amp;policy);</div><div class='ctx'> 	if (transition_context) {</div><div class='ctx'> 		ret = dc_commit_state_no_check(dc, transition_context);</div><div class='del'>-		release_minimal_transition_state(dc, transition_context, &amp;policy);</div><div class='add'>+		release_minimal_transition_state(dc, transition_context, transition_base_context, &amp;policy);</div><div class='ctx'> 	}</div><div class='add'>+	dc_state_release(transition_base_context);</div><div class='ctx'> </div><div class='ctx'> 	if (ret != DC_OK) {</div><div class='ctx'> 		/* this should never happen */</div><div class='hunk'>@@ -4283,42 +4998,7 @@ static bool commit_minimal_transition_state_legacy(struct dc *dc,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * update_seamless_boot_flags() - Helper function for updating seamless boot flags</div><div class='del'>- *</div><div class='del'>- * @dc: Current DC state</div><div class='del'>- * @context: New DC state to be programmed</div><div class='del'>- * @surface_count: Number of surfaces that have an updated</div><div class='del'>- * @stream: Corresponding stream to be updated in the current flip</div><div class='del'>- *</div><div class='del'>- * Updating seamless boot flags do not need to be part of the commit sequence. This</div><div class='del'>- * helper function will update the seamless boot flags on each flip (if required)</div><div class='del'>- * outside of the HW commit sequence (fast or slow).</div><div class='del'>- *</div><div class='del'>- * Return: void</div><div class='del'>- */</div><div class='del'>-static void update_seamless_boot_flags(struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		int surface_count,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	if (get_seamless_boot_stream_count(context) &gt; 0 &amp;&amp; surface_count &gt; 0) {</div><div class='del'>-		/* Optimize seamless boot flag keeps clocks and watermarks high until</div><div class='del'>-		 * first flip. After first flip, optimization is required to lower</div><div class='del'>-		 * bandwidth. Important to note that it is expected UEFI will</div><div class='del'>-		 * only light up a single display on POST, therefore we only expect</div><div class='del'>-		 * one stream with seamless boot flag set.</div><div class='del'>-		 */</div><div class='del'>-		if (stream-&gt;apply_seamless_boot_optimization) {</div><div class='del'>-			stream-&gt;apply_seamless_boot_optimization = false;</div><div class='del'>-</div><div class='del'>-			if (get_seamless_boot_stream_count(context) == 0)</div><div class='del'>-				dc-&gt;optimized_required = true;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void populate_fast_updates(struct dc_fast_update *fast_update,</div><div class='add'>+void populate_fast_updates(struct dc_fast_update *fast_update,</div><div class='ctx'> 		struct dc_surface_update *srf_updates,</div><div class='ctx'> 		int surface_count,</div><div class='ctx'> 		struct dc_stream_update *stream_update)</div><div class='hunk'>@@ -4328,6 +5008,9 @@ static void populate_fast_updates(struct dc_fast_update *fast_update,</div><div class='ctx'> 	if (stream_update) {</div><div class='ctx'> 		fast_update[0].out_transfer_func = stream_update-&gt;out_transfer_func;</div><div class='ctx'> 		fast_update[0].output_csc_transform = stream_update-&gt;output_csc_transform;</div><div class='add'>+	} else {</div><div class='add'>+		fast_update[0].out_transfer_func = NULL;</div><div class='add'>+		fast_update[0].output_csc_transform = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; surface_count; i++) {</div><div class='hunk'>@@ -4336,10 +5019,11 @@ static void populate_fast_updates(struct dc_fast_update *fast_update,</div><div class='ctx'> 		fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;</div><div class='ctx'> 		fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;</div><div class='ctx'> 		fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;</div><div class='add'>+		fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count)</div><div class='add'>+static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -4352,6 +5036,7 @@ static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_c</div><div class='ctx'> 				fast_update[i].gamma ||</div><div class='ctx'> 				fast_update[i].gamut_remap_matrix ||</div><div class='ctx'> 				fast_update[i].input_csc_color_matrix ||</div><div class='add'>+				fast_update[i].cursor_csc_color_matrix ||</div><div class='ctx'> 				fast_update[i].coeff_reduction_factor)</div><div class='ctx'> 			return true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4359,30 +5044,80 @@ static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_c</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool full_update_required(struct dc *dc,</div><div class='del'>-		struct dc_surface_update *srf_updates,</div><div class='del'>-		int surface_count,</div><div class='del'>-		struct dc_stream_update *stream_update,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='add'>+bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	int i;</div><div class='del'>-	struct dc_stream_status *stream_status;</div><div class='del'>-	const struct dc_state *context = dc-&gt;current_state;</div><div class='add'>+</div><div class='add'>+	if (fast_update[0].out_transfer_func ||</div><div class='add'>+		fast_update[0].output_csc_transform)</div><div class='add'>+		return true;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; surface_count; i++) {</div><div class='add'>+		if (fast_update[i].input_csc_color_matrix ||</div><div class='add'>+				fast_update[i].gamma ||</div><div class='add'>+				fast_update[i].gamut_remap_matrix ||</div><div class='add'>+				fast_update[i].coeff_reduction_factor ||</div><div class='add'>+				fast_update[i].cursor_csc_color_matrix)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool full_update_required_weak(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		const struct dc_stream_update *stream_update,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	const struct dc_state *context = dc-&gt;current_state;</div><div class='add'>+	if (srf_updates)</div><div class='add'>+		for (int i = 0; i &lt; surface_count; i++)</div><div class='add'>+			if (!is_surface_in_context(context, srf_updates[i].surface))</div><div class='add'>+				return true;</div><div class='add'>+</div><div class='add'>+	if (stream) {</div><div class='add'>+		const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream);</div><div class='add'>+		if (stream_status == NULL || stream_status-&gt;plane_count != surface_count)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+	if (dc-&gt;idle_optimizations_allowed)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (dc_can_clear_cursor_limit(dc))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool full_update_required(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		const struct dc_stream_update *stream_update,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; surface_count; i++) {</div><div class='ctx'> 		if (srf_updates &amp;&amp;</div><div class='ctx'> 				(srf_updates[i].plane_info ||</div><div class='ctx'> 				srf_updates[i].scaling_info ||</div><div class='ctx'> 				(srf_updates[i].hdr_mult.value &amp;&amp;</div><div class='ctx'> 				srf_updates[i].hdr_mult.value != srf_updates-&gt;surface-&gt;hdr_mult.value) ||</div><div class='add'>+				(srf_updates[i].sdr_white_level_nits &amp;&amp;</div><div class='add'>+				srf_updates[i].sdr_white_level_nits != srf_updates-&gt;surface-&gt;sdr_white_level_nits) ||</div><div class='ctx'> 				srf_updates[i].in_transfer_func ||</div><div class='ctx'> 				srf_updates[i].func_shaper ||</div><div class='ctx'> 				srf_updates[i].lut3d_func ||</div><div class='ctx'> 				srf_updates[i].surface-&gt;force_full_update ||</div><div class='ctx'> 				(srf_updates[i].flip_addr &amp;&amp;</div><div class='ctx'> 				srf_updates[i].flip_addr-&gt;address.tmz_surface != srf_updates[i].surface-&gt;address.tmz_surface) ||</div><div class='del'>-				!is_surface_in_context(context, srf_updates[i].surface)))</div><div class='add'>+				(srf_updates[i].cm2_params &amp;&amp;</div><div class='add'>+				 (srf_updates[i].cm2_params-&gt;component_settings.shaper_3dlut_setting != srf_updates[i].surface-&gt;mcm_shaper_3dlut_setting ||</div><div class='add'>+				  srf_updates[i].cm2_params-&gt;component_settings.lut1d_enable != srf_updates[i].surface-&gt;mcm_lut1d_enable))))</div><div class='ctx'> 			return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -4399,6 +5134,7 @@ static bool full_update_required(struct dc *dc,</div><div class='ctx'> 			stream_update-&gt;hfvsif_infopacket ||</div><div class='ctx'> 			stream_update-&gt;vtem_infopacket ||</div><div class='ctx'> 			stream_update-&gt;adaptive_sync_infopacket ||</div><div class='add'>+			stream_update-&gt;avi_infopacket ||</div><div class='ctx'> 			stream_update-&gt;dpms_off ||</div><div class='ctx'> 			stream_update-&gt;allow_freesync ||</div><div class='ctx'> 			stream_update-&gt;vrr_active_variable ||</div><div class='hunk'>@@ -4412,39 +5148,33 @@ static bool full_update_required(struct dc *dc,</div><div class='ctx'> 			stream_update-&gt;func_shaper ||</div><div class='ctx'> 			stream_update-&gt;lut3d_func ||</div><div class='ctx'> 			stream_update-&gt;pending_test_pattern ||</div><div class='del'>-			stream_update-&gt;crtc_timing_adjust))</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	if (stream) {</div><div class='del'>-		stream_status = dc_stream_get_status(stream);</div><div class='del'>-		if (stream_status == NULL || stream_status-&gt;plane_count != surface_count)</div><div class='del'>-			return true;</div><div class='del'>-	}</div><div class='del'>-	if (dc-&gt;idle_optimizations_allowed)</div><div class='add'>+			stream_update-&gt;crtc_timing_adjust ||</div><div class='add'>+			stream_update-&gt;scaler_sharpener_update ||</div><div class='add'>+			stream_update-&gt;hw_cursor_req))</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool fast_update_only(struct dc *dc,</div><div class='del'>-		struct dc_fast_update *fast_update,</div><div class='del'>-		struct dc_surface_update *srf_updates,</div><div class='add'>+static bool fast_update_only(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_fast_update *fast_update,</div><div class='add'>+		const struct dc_surface_update *srf_updates,</div><div class='ctx'> 		int surface_count,</div><div class='del'>-		struct dc_stream_update *stream_update,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='add'>+		const struct dc_stream_update *stream_update,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	return fast_updates_exist(fast_update, surface_count)</div><div class='ctx'> 			&amp;&amp; !full_update_required(dc, srf_updates, surface_count, stream_update, stream);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_update_planes_and_stream(struct dc *dc,</div><div class='add'>+static bool update_planes_and_stream_v2(struct dc *dc,</div><div class='ctx'> 		struct dc_surface_update *srf_updates, int surface_count,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_stream_update *stream_update)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_state *context;</div><div class='ctx'> 	enum surface_update_type update_type;</div><div class='del'>-	int i;</div><div class='ctx'> 	struct dc_fast_update fast_update[MAX_SURFACES] = {0};</div><div class='ctx'> </div><div class='ctx'> 	/* In cases where MPO and split or ODM are used transitions can</div><div class='hunk'>@@ -4455,8 +5185,6 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> 	bool is_plane_addition = 0;</div><div class='ctx'> 	bool is_fast_update_only;</div><div class='ctx'> </div><div class='del'>-	dc_exit_ips_for_hw_access(dc);</div><div class='del'>-</div><div class='ctx'> 	populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);</div><div class='ctx'> 	is_fast_update_only = fast_update_only(dc, fast_update, srf_updates,</div><div class='ctx'> 			surface_count, stream_update, stream);</div><div class='hunk'>@@ -4469,8 +5197,8 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	/* on plane addition, minimal state is the current one */</div><div class='ctx'> 	if (force_minimal_pipe_splitting &amp;&amp; is_plane_addition &amp;&amp;</div><div class='del'>-		!commit_minimal_transition_state_legacy(dc, dc-&gt;current_state))</div><div class='del'>-				return false;</div><div class='add'>+		!commit_minimal_transition_state(dc, dc-&gt;current_state))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (!update_planes_and_stream_state(</div><div class='ctx'> 			dc,</div><div class='hunk'>@@ -4484,7 +5212,7 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	/* on plane removal, minimal state is the new one */</div><div class='ctx'> 	if (force_minimal_pipe_splitting &amp;&amp; !is_plane_addition) {</div><div class='del'>-		if (!commit_minimal_transition_state_legacy(dc, context)) {</div><div class='add'>+		if (!commit_minimal_transition_state(dc, context)) {</div><div class='ctx'> 			dc_state_release(context);</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4493,12 +5221,11 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;hwss.is_pipe_topology_transition_seamless &amp;&amp;</div><div class='ctx'> 			!dc-&gt;hwss.is_pipe_topology_transition_seamless(</div><div class='del'>-					dc, dc-&gt;current_state, context)) {</div><div class='del'>-		commit_minimal_transition_state(dc,</div><div class='del'>-				context, stream);</div><div class='del'>-	}</div><div class='del'>-	update_seamless_boot_flags(dc, context, surface_count, stream);</div><div class='del'>-	if (is_fast_update_only &amp;&amp; !dc-&gt;debug.enable_legacy_fast_update) {</div><div class='add'>+					dc, dc-&gt;current_state, context))</div><div class='add'>+		commit_minimal_transition_state_in_dc_update(dc, context, stream,</div><div class='add'>+				srf_updates, surface_count);</div><div class='add'>+</div><div class='add'>+	if (is_fast_update_only &amp;&amp; !dc-&gt;check_config.enable_legacy_fast_update) {</div><div class='ctx'> 		commit_planes_for_stream_fast(dc,</div><div class='ctx'> 				srf_updates,</div><div class='ctx'> 				surface_count,</div><div class='hunk'>@@ -4523,143 +5250,33 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> 				update_type,</div><div class='ctx'> 				context);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	if (dc-&gt;current_state != context) {</div><div class='del'>-</div><div class='del'>-		/* Since memory free requires elevated IRQL, an interrupt</div><div class='del'>-		 * request is generated by mem free. If this happens</div><div class='del'>-		 * between freeing and reassigning the context, our vsync</div><div class='del'>-		 * interrupt will call into dc and cause a memory</div><div class='del'>-		 * corruption BSOD. Hence, we first reassign the context,</div><div class='del'>-		 * then free the old context.</div><div class='del'>-		 */</div><div class='del'>-</div><div class='del'>-		struct dc_state *old = dc-&gt;current_state;</div><div class='del'>-</div><div class='del'>-		dc-&gt;current_state = context;</div><div class='del'>-		dc_state_release(old);</div><div class='del'>-</div><div class='del'>-		// clear any forced full updates</div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-			if (pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;stream == stream)</div><div class='del'>-				pipe_ctx-&gt;plane_state-&gt;force_full_update = false;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	if (dc-&gt;current_state != context)</div><div class='add'>+		swap_and_release_current_context(dc, context, stream);</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_commit_updates_for_stream(struct dc *dc,</div><div class='del'>-		struct dc_surface_update *srf_updates,</div><div class='del'>-		int surface_count,</div><div class='add'>+static void commit_planes_and_stream_update_on_current_context(struct dc *dc,</div><div class='add'>+		struct dc_surface_update *srf_updates, int surface_count,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_stream_update *stream_update,</div><div class='del'>-		struct dc_state *state)</div><div class='add'>+		enum surface_update_type update_type)</div><div class='ctx'> {</div><div class='del'>-	const struct dc_stream_status *stream_status;</div><div class='del'>-	enum surface_update_type update_type;</div><div class='del'>-	struct dc_state *context;</div><div class='del'>-	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='del'>-	int i, j;</div><div class='ctx'> 	struct dc_fast_update fast_update[MAX_SURFACES] = {0};</div><div class='ctx'> </div><div class='del'>-	dc_exit_ips_for_hw_access(dc);</div><div class='del'>-</div><div class='del'>-	populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);</div><div class='del'>-	stream_status = dc_stream_get_status(stream);</div><div class='del'>-	context = dc-&gt;current_state;</div><div class='del'>-</div><div class='del'>-	update_type = dc_check_update_surfaces_for_stream(</div><div class='del'>-				dc, srf_updates, surface_count, stream_update, stream_status);</div><div class='del'>-</div><div class='del'>-	/* TODO: Since change commit sequence can have a huge impact,</div><div class='del'>-	 * we decided to only enable it for DCN3x. However, as soon as</div><div class='del'>-	 * we get more confident about this change we'll need to enable</div><div class='del'>-	 * the new sequence for all ASICs.</div><div class='del'>-	 */</div><div class='del'>-	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_3_2) {</div><div class='del'>-		/*</div><div class='del'>-		 * Previous frame finished and HW is ready for optimization.</div><div class='del'>-		 */</div><div class='del'>-		if (update_type == UPDATE_TYPE_FAST)</div><div class='del'>-			dc_post_update_surfaces_to_stream(dc);</div><div class='del'>-</div><div class='del'>-		dc_update_planes_and_stream(dc, srf_updates,</div><div class='del'>-					    surface_count, stream,</div><div class='del'>-					    stream_update);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (update_type &gt;= update_surface_trace_level)</div><div class='del'>-		update_surface_trace(dc, srf_updates, surface_count);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	if (update_type &gt;= UPDATE_TYPE_FULL) {</div><div class='del'>-</div><div class='del'>-		/* initialize scratch memory for building context */</div><div class='del'>-		context = dc_state_create_copy(state);</div><div class='del'>-		if (context == NULL) {</div><div class='del'>-			DC_ERROR("Failed to allocate new validate context!\n");</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			struct pipe_ctx *new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-			struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-			if (new_pipe-&gt;plane_state &amp;&amp; new_pipe-&gt;plane_state != old_pipe-&gt;plane_state)</div><div class='del'>-				new_pipe-&gt;plane_state-&gt;force_full_update = true;</div><div class='del'>-		}</div><div class='del'>-	} else if (update_type == UPDATE_TYPE_FAST) {</div><div class='del'>-		/*</div><div class='del'>-		 * Previous frame finished and HW is ready for optimization.</div><div class='del'>-		 */</div><div class='del'>-		dc_post_update_surfaces_to_stream(dc);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; surface_count; i++) {</div><div class='del'>-		struct dc_plane_state *surface = srf_updates[i].surface;</div><div class='del'>-</div><div class='del'>-		copy_surface_update_to_plane(surface, &amp;srf_updates[i]);</div><div class='del'>-</div><div class='del'>-		if (update_type &gt;= UPDATE_TYPE_MED) {</div><div class='del'>-			for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='del'>-				struct pipe_ctx *pipe_ctx =</div><div class='del'>-					&amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='del'>-</div><div class='del'>-				if (pipe_ctx-&gt;plane_state != surface)</div><div class='del'>-					continue;</div><div class='del'>-</div><div class='del'>-				resource_build_scaling_params(pipe_ctx);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	copy_stream_update_to_stream(dc, context, stream, stream_update);</div><div class='del'>-</div><div class='del'>-	if (update_type &gt;= UPDATE_TYPE_FULL) {</div><div class='del'>-		if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, false)) {</div><div class='del'>-			DC_ERROR("Mode validation failed for stream update!\n");</div><div class='del'>-			dc_state_release(context);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);</div><div class='del'>-</div><div class='del'>-	update_seamless_boot_flags(dc, context, surface_count, stream);</div><div class='del'>-	if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) &amp;&amp;</div><div class='del'>-			!dc-&gt;debug.enable_legacy_fast_update) {</div><div class='add'>+	ASSERT(update_type &lt; UPDATE_TYPE_FULL);</div><div class='add'>+	populate_fast_updates(fast_update, srf_updates, surface_count,</div><div class='add'>+			stream_update);</div><div class='add'>+	if (fast_update_only(dc, fast_update, srf_updates, surface_count,</div><div class='add'>+			stream_update, stream) &amp;&amp;</div><div class='add'>+			!dc-&gt;check_config.enable_legacy_fast_update)</div><div class='ctx'> 		commit_planes_for_stream_fast(dc,</div><div class='ctx'> 				srf_updates,</div><div class='ctx'> 				surface_count,</div><div class='ctx'> 				stream,</div><div class='ctx'> 				stream_update,</div><div class='ctx'> 				update_type,</div><div class='del'>-				context);</div><div class='del'>-	} else {</div><div class='add'>+				dc-&gt;current_state);</div><div class='add'>+	else</div><div class='ctx'> 		commit_planes_for_stream(</div><div class='ctx'> 				dc,</div><div class='ctx'> 				srf_updates,</div><div class='hunk'>@@ -4667,32 +5284,155 @@ void dc_commit_updates_for_stream(struct dc *dc,</div><div class='ctx'> 				stream,</div><div class='ctx'> 				stream_update,</div><div class='ctx'> 				update_type,</div><div class='del'>-				context);</div><div class='del'>-	}</div><div class='del'>-	/*update current_State*/</div><div class='del'>-	if (dc-&gt;current_state != context) {</div><div class='add'>+				dc-&gt;current_state);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		struct dc_state *old = dc-&gt;current_state;</div><div class='add'>+static void commit_planes_and_stream_update_with_new_context(struct dc *dc,</div><div class='add'>+		struct dc_surface_update *srf_updates, int surface_count,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_stream_update *stream_update,</div><div class='add'>+		enum surface_update_type update_type,</div><div class='add'>+		struct dc_state *new_context)</div><div class='add'>+{</div><div class='add'>+	ASSERT(update_type &gt;= UPDATE_TYPE_FULL);</div><div class='add'>+	if (!dc-&gt;hwss.is_pipe_topology_transition_seamless(dc,</div><div class='add'>+			dc-&gt;current_state, new_context))</div><div class='add'>+		/*</div><div class='add'>+		 * It is required by the feature design that all pipe topologies</div><div class='add'>+		 * using extra free pipes for power saving purposes such as</div><div class='add'>+		 * dynamic ODM or SubVp shall only be enabled when it can be</div><div class='add'>+		 * transitioned seamlessly to AND from its minimal transition</div><div class='add'>+		 * state. A minimal transition state is defined as the same dc</div><div class='add'>+		 * state but with all power saving features disabled. So it uses</div><div class='add'>+		 * the minimum pipe topology. When we can't seamlessly</div><div class='add'>+		 * transition from state A to state B, we will insert the</div><div class='add'>+		 * minimal transition state A' or B' in between so seamless</div><div class='add'>+		 * transition between A and B can be made possible.</div><div class='add'>+		 */</div><div class='add'>+		commit_minimal_transition_state_in_dc_update(dc, new_context,</div><div class='add'>+				stream, srf_updates, surface_count);</div><div class='add'>+</div><div class='add'>+	commit_planes_for_stream(</div><div class='add'>+			dc,</div><div class='add'>+			srf_updates,</div><div class='add'>+			surface_count,</div><div class='add'>+			stream,</div><div class='add'>+			stream_update,</div><div class='add'>+			update_type,</div><div class='add'>+			new_context);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		dc-&gt;current_state = context;</div><div class='del'>-		dc_state_release(old);</div><div class='add'>+static bool update_planes_and_stream_v3(struct dc *dc,</div><div class='add'>+		struct dc_surface_update *srf_updates, int surface_count,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_stream_update *stream_update)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *new_context;</div><div class='add'>+	enum surface_update_type update_type;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+	/*</div><div class='add'>+	 * When this function returns true and new_context is not equal to</div><div class='add'>+	 * current state, the function allocates and validates a new dc state</div><div class='add'>+	 * and assigns it to new_context. The function expects that the caller</div><div class='add'>+	 * is responsible to free this memory when new_context is no longer</div><div class='add'>+	 * used. We swap current with new context and free current instead. So</div><div class='add'>+	 * new_context's memory will live until the next full update after it is</div><div class='add'>+	 * replaced by a newer context. Refer to the use of</div><div class='add'>+	 * swap_and_free_current_context below.</div><div class='add'>+	 */</div><div class='add'>+	if (!update_planes_and_stream_state(dc, srf_updates, surface_count,</div><div class='add'>+				stream, stream_update, &amp;update_type,</div><div class='add'>+				&amp;new_context))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-			if (pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;stream == stream)</div><div class='del'>-				pipe_ctx-&gt;plane_state-&gt;force_full_update = false;</div><div class='del'>-		}</div><div class='add'>+	if (new_context == dc-&gt;current_state) {</div><div class='add'>+		commit_planes_and_stream_update_on_current_context(dc,</div><div class='add'>+				srf_updates, surface_count, stream,</div><div class='add'>+				stream_update, update_type);</div><div class='add'>+	} else {</div><div class='add'>+		commit_planes_and_stream_update_with_new_context(dc,</div><div class='add'>+				srf_updates, surface_count, stream,</div><div class='add'>+				stream_update, update_type, new_context);</div><div class='add'>+		swap_and_release_current_context(dc, new_context, stream);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Legacy optimization path for DCE. */</div><div class='del'>-	if (update_type &gt;= UPDATE_TYPE_FULL &amp;&amp; dc_ctx-&gt;dce_version &lt; DCE_VERSION_MAX) {</div><div class='del'>-		dc_post_update_surfaces_to_stream(dc);</div><div class='del'>-		TRACE_DCE_CLOCK_STATE(&amp;context-&gt;bw_ctx.bw.dce);</div><div class='del'>-	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_update_flags(struct dc_surface_update *srf_updates,</div><div class='add'>+	int surface_count, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (stream)</div><div class='add'>+		stream-&gt;update_flags.raw = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; surface_count; i++)</div><div class='add'>+		if (srf_updates[i].surface)</div><div class='add'>+			srf_updates[i].surface-&gt;update_flags.raw = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_update_planes_and_stream(struct dc *dc,</div><div class='add'>+		struct dc_surface_update *srf_updates, int surface_count,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_stream_update *stream_update)</div><div class='add'>+{</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	dc_exit_ips_for_hw_access(dc);</div><div class='add'>+	/*</div><div class='add'>+	 * update planes and stream version 3 separates FULL and FAST updates</div><div class='add'>+	 * to their own sequences. It aims to clean up frequent checks for</div><div class='add'>+	 * update type resulting unnecessary branching in logic flow. It also</div><div class='add'>+	 * adds a new commit minimal transition sequence, which detects the need</div><div class='add'>+	 * for minimal transition based on the actual comparison of current and</div><div class='add'>+	 * new states instead of "predicting" it based on per feature software</div><div class='add'>+	 * policy.i.e could_mpcc_tree_change_for_active_pipes. The new commit</div><div class='add'>+	 * minimal transition sequence is made universal to any power saving</div><div class='add'>+	 * features that would use extra free pipes such as Dynamic ODM/MPC</div><div class='add'>+	 * Combine, MPO or SubVp. Therefore there is no longer a need to</div><div class='add'>+	 * specially handle compatibility problems with transitions among those</div><div class='add'>+	 * features as they are now transparent to the new sequence.</div><div class='add'>+	 */</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_4_01 || dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_2 ||</div><div class='add'>+			dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_21)</div><div class='add'>+		ret = update_planes_and_stream_v3(dc, srf_updates,</div><div class='add'>+				surface_count, stream, stream_update);</div><div class='add'>+	else</div><div class='add'>+		ret = update_planes_and_stream_v2(dc, srf_updates,</div><div class='add'>+			surface_count, stream, stream_update);</div><div class='add'>+	if (ret &amp;&amp; (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_3_2 ||</div><div class='add'>+		dc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_01))</div><div class='add'>+		clear_update_flags(srf_updates, surface_count, stream);</div><div class='ctx'> </div><div class='del'>-	return;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_commit_updates_for_stream(struct dc *dc,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_stream_update *stream_update,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	bool ret = false;</div><div class='ctx'> </div><div class='add'>+	dc_exit_ips_for_hw_access(dc);</div><div class='add'>+	/* TODO: Since change commit sequence can have a huge impact,</div><div class='add'>+	 * we decided to only enable it for DCN3x. However, as soon as</div><div class='add'>+	 * we get more confident about this change we'll need to enable</div><div class='add'>+	 * the new sequence for all ASICs.</div><div class='add'>+	 */</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_4_01) {</div><div class='add'>+		ret = update_planes_and_stream_v3(dc, srf_updates, surface_count,</div><div class='add'>+				stream, stream_update);</div><div class='add'>+	} else {</div><div class='add'>+		ret = update_planes_and_stream_v2(dc, srf_updates, surface_count,</div><div class='add'>+				stream, stream_update);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret &amp;&amp; dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_3_2)</div><div class='add'>+		clear_update_flags(srf_updates, surface_count, stream);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> uint8_t dc_get_current_stream_count(struct dc *dc)</div><div class='hunk'>@@ -4735,13 +5475,14 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)</div><div class='ctx'> void dc_power_down_on_boot(struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment != DCE_ENV_VIRTUAL_HW &amp;&amp;</div><div class='del'>-			dc-&gt;hwss.power_down_on_boot)</div><div class='add'>+	    dc-&gt;hwss.power_down_on_boot) {</div><div class='add'>+		if (dc-&gt;caps.ips_support)</div><div class='add'>+			dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> 		dc-&gt;hwss.power_down_on_boot(dc);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_set_power_state(</div><div class='del'>-	struct dc *dc,</div><div class='del'>-	enum dc_acpi_cm_power_state power_state)</div><div class='add'>+void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)</div><div class='ctx'> {</div><div class='ctx'> 	if (!dc-&gt;current_state)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -4754,16 +5495,27 @@ void dc_set_power_state(</div><div class='ctx'> </div><div class='ctx'> 		dc_z10_restore(dc);</div><div class='ctx'> </div><div class='add'>+		dc_dmub_srv_notify_fw_dc_power_state(dc-&gt;ctx-&gt;dmub_srv, power_state);</div><div class='add'>+</div><div class='ctx'> 		dc-&gt;hwss.init_hw(dc);</div><div class='ctx'> </div><div class='ctx'> 		if (dc-&gt;hwss.init_sys_ctx != NULL &amp;&amp;</div><div class='ctx'> 			dc-&gt;vm_pa_config.valid) {</div><div class='ctx'> 			dc-&gt;hwss.init_sys_ctx(dc-&gt;hwseq, dc, &amp;dc-&gt;vm_pa_config);</div><div class='ctx'> 		}</div><div class='add'>+		break;</div><div class='add'>+	case DC_ACPI_CM_POWER_STATE_D3:</div><div class='add'>+		if (dc-&gt;caps.ips_support)</div><div class='add'>+			dc_dmub_srv_notify_fw_dc_power_state(dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D3);</div><div class='ctx'> </div><div class='add'>+		if (dc-&gt;caps.ips_v2_support) {</div><div class='add'>+			if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_low_power_state)</div><div class='add'>+				dc-&gt;clk_mgr-&gt;funcs-&gt;set_low_power_state(dc-&gt;clk_mgr);</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT(dc-&gt;current_state-&gt;stream_count == 0);</div><div class='add'>+		dc_dmub_srv_notify_fw_dc_power_state(dc-&gt;ctx-&gt;dmub_srv, power_state);</div><div class='ctx'> </div><div class='ctx'> 		dc_state_destruct(dc-&gt;current_state);</div><div class='ctx'> </div><div class='hunk'>@@ -4788,18 +5540,6 @@ bool dc_is_dmcu_initialized(struct dc *dc)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)</div><div class='del'>-{</div><div class='del'>-	info-&gt;displayClock				= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.dispclk_khz;</div><div class='del'>-	info-&gt;engineClock				= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.dcfclk_khz;</div><div class='del'>-	info-&gt;memoryClock				= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.dramclk_khz;</div><div class='del'>-	info-&gt;maxSupportedDppClock		= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;</div><div class='del'>-	info-&gt;dppClock					= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.dppclk_khz;</div><div class='del'>-	info-&gt;socClock					= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.socclk_khz;</div><div class='del'>-	info-&gt;dcfClockDeepSleep			= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;</div><div class='del'>-	info-&gt;fClock					= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.fclk_khz;</div><div class='del'>-	info-&gt;phyClock					= (unsigned int)state-&gt;bw_ctx.bw.dcn.clk.phyclk_khz;</div><div class='del'>-}</div><div class='ctx'> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc-&gt;hwss.set_clock)</div><div class='hunk'>@@ -4874,10 +5614,31 @@ bool dc_set_replay_allow_active(struct dc *dc, bool active)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_allow_idle_optimizations(struct dc *dc, bool allow)</div><div class='add'>+/* set IPS disable state */</div><div class='add'>+bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips)</div><div class='ctx'> {</div><div class='del'>-	if (dc-&gt;debug.disable_idle_power_optimizations)</div><div class='add'>+	dc_exit_ips_for_hw_access(dc);</div><div class='add'>+</div><div class='add'>+	dc-&gt;config.disable_ips = disable_ips;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name)</div><div class='add'>+{</div><div class='add'>+	int idle_fclk_khz = 0, idle_dramclk_khz = 0, i = 0;</div><div class='add'>+	enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0};</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+	struct dc_state *context = dc-&gt;current_state;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.disable_idle_power_optimizations) {</div><div class='add'>+		DC_LOG_DEBUG("%s: disabled\n", __func__);</div><div class='ctx'> 		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (allow != dc-&gt;idle_optimizations_allowed)</div><div class='add'>+		DC_LOG_IPS("%s: allow_idle old=%d new=%d (caller=%s)\n", __func__,</div><div class='add'>+			   dc-&gt;idle_optimizations_allowed, allow, caller_name);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;caps.ips_support &amp;&amp; (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_ALL))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -4889,14 +5650,36 @@ void dc_allow_idle_optimizations(struct dc *dc, bool allow)</div><div class='ctx'> 	if (allow == dc-&gt;idle_optimizations_allowed)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;hwss.apply_idle_power_optimizations &amp;&amp; dc-&gt;hwss.apply_idle_power_optimizations(dc, allow))</div><div class='add'>+	if (dc-&gt;hwss.apply_idle_power_optimizations &amp;&amp; dc-&gt;clk_mgr != NULL &amp;&amp;</div><div class='add'>+	    dc-&gt;hwss.apply_idle_power_optimizations(dc, allow)) {</div><div class='ctx'> 		dc-&gt;idle_optimizations_allowed = allow;</div><div class='add'>+		DC_LOG_DEBUG("%s: %s\n", __func__, allow ? "enabled" : "disabled");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// log idle clocks and sub vp pipe types at idle optimization time</div><div class='add'>+	if (dc-&gt;clk_mgr != NULL &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;get_hard_min_fclk)</div><div class='add'>+		idle_fclk_khz = dc-&gt;clk_mgr-&gt;funcs-&gt;get_hard_min_fclk(dc-&gt;clk_mgr);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;clk_mgr != NULL &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;get_hard_min_memclk)</div><div class='add'>+		idle_dramclk_khz = dc-&gt;clk_mgr-&gt;funcs-&gt;get_hard_min_memclk(dc-&gt;clk_mgr);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool &amp;&amp; context) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			subvp_pipe_type[i] = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	if (!dc-&gt;caps.is_apu)</div><div class='add'>+		DC_LOG_DC("%s: allow_idle=%d\n HardMinUClk_Khz=%d HardMinDramclk_Khz=%d\n Pipe_0=%d Pipe_1=%d Pipe_2=%d Pipe_3=%d Pipe_4=%d Pipe_5=%d (caller=%s)\n",</div><div class='add'>+			__func__, allow, idle_fclk_khz, idle_dramclk_khz, subvp_pipe_type[0], subvp_pipe_type[1], subvp_pipe_type[2],</div><div class='add'>+			subvp_pipe_type[3], subvp_pipe_type[4], subvp_pipe_type[5], caller_name);</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_exit_ips_for_hw_access(struct dc *dc)</div><div class='add'>+void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc-&gt;caps.ips_support)</div><div class='del'>-		dc_allow_idle_optimizations(dc, false);</div><div class='add'>+		dc_allow_idle_optimizations_internal(dc, false, caller_name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_is_ips_idle_state(struct dc *dc)</div><div class='hunk'>@@ -4958,9 +5741,10 @@ static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memcl</div><div class='ctx'> 			hubp-&gt;funcs-&gt;set_blank_regs(hubp, true);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk(dc-&gt;clk_mgr, memclk_mhz);</div><div class='del'>-	dc-&gt;clk_mgr-&gt;funcs-&gt;set_min_memclk(dc-&gt;clk_mgr, memclk_mhz);</div><div class='add'>+	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk)</div><div class='add'>+		dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk(dc-&gt;clk_mgr, memclk_mhz);</div><div class='add'>+	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_min_memclk)</div><div class='add'>+		dc-&gt;clk_mgr-&gt;funcs-&gt;set_min_memclk(dc-&gt;clk_mgr, memclk_mhz);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -5009,7 +5793,7 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)</div><div class='ctx'> </div><div class='ctx'> 	if (enable &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled) {</div><div class='ctx'> 		if (p_state_change_support) {</div><div class='del'>-			if (funcMin &lt;= softMax)</div><div class='add'>+			if (funcMin &lt;= softMax &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk)</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk(dc-&gt;clk_mgr, softMax);</div><div class='ctx'> 			// else: No-Op</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -5019,7 +5803,7 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (!enable &amp;&amp; dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled) {</div><div class='ctx'> 		if (p_state_change_support) {</div><div class='del'>-			if (funcMin &lt;= softMax)</div><div class='add'>+			if (funcMin &lt;= softMax &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk)</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk(dc-&gt;clk_mgr, maxDPM);</div><div class='ctx'> 			// else: No-Op</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -5030,10 +5814,13 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)</div><div class='ctx'> 	}</div><div class='ctx'> 	dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled = enable;</div><div class='ctx'> }</div><div class='del'>-bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,</div><div class='add'>+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,</div><div class='add'>+		unsigned int pitch,</div><div class='add'>+		unsigned int height,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='ctx'> 		struct dc_cursor_attributes *cursor_attr)</div><div class='ctx'> {</div><div class='del'>-	if (dc-&gt;hwss.does_plane_fit_in_mall &amp;&amp; dc-&gt;hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))</div><div class='add'>+	if (dc-&gt;hwss.does_plane_fit_in_mall &amp;&amp; dc-&gt;hwss.does_plane_fit_in_mall(dc, pitch, height, format, cursor_attr))</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -5067,6 +5854,9 @@ void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)</div><div class='ctx'>  */</div><div class='ctx'> bool dc_is_dmub_outbox_supported(struct dc *dc)</div><div class='ctx'> {</div><div class='add'>+	if (!dc-&gt;caps.dmcub_support)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	switch (dc-&gt;ctx-&gt;asic_id.chip_family) {</div><div class='ctx'> </div><div class='ctx'> 	case FAMILY_YELLOW_CARP:</div><div class='hunk'>@@ -5190,6 +5980,101 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits,</div><div class='add'>+			uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline)</div><div class='add'>+{</div><div class='add'>+	bool status = false;</div><div class='add'>+	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	uint8_t otg_inst = 0;</div><div class='add'>+	unsigned int panel_inst = 0;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = NULL;</div><div class='add'>+	struct resource_context *res_ctx = &amp;link-&gt;ctx-&gt;dc-&gt;current_state-&gt;res_ctx;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	// get panel_inst</div><div class='add'>+	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='add'>+	// get otg_inst</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (res_ctx &amp;&amp;</div><div class='add'>+			res_ctx-&gt;pipe_ctx[i].stream &amp;&amp;</div><div class='add'>+			res_ctx-&gt;pipe_ctx[i].stream-&gt;link &amp;&amp;</div><div class='add'>+			res_ctx-&gt;pipe_ctx[i].stream-&gt;link == link &amp;&amp;</div><div class='add'>+			res_ctx-&gt;pipe_ctx[i].stream-&gt;link-&gt;connector_signal == SIGNAL_TYPE_EDP) {</div><div class='add'>+			pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+			//TODO: refactor for multi edp support</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx)</div><div class='add'>+		otg_inst = pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+</div><div class='add'>+	// before enable smart power OLED, we need to call set pipe for DMUB to set ABM config</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (dc-&gt;hwss.set_pipe &amp;&amp; pipe_ctx)</div><div class='add'>+			dc-&gt;hwss.set_pipe(pipe_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// fill in cmd</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.smart_power_oled_enable.header.type = DMUB_CMD__SMART_POWER_OLED;</div><div class='add'>+	cmd.smart_power_oled_enable.header.sub_type = DMUB_CMD__SMART_POWER_OLED_ENABLE;</div><div class='add'>+	cmd.smart_power_oled_enable.header.payload_bytes =</div><div class='add'>+		sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header);</div><div class='add'>+	cmd.smart_power_oled_enable.header.ret_status = 1;</div><div class='add'>+	cmd.smart_power_oled_enable.data.enable = enable;</div><div class='add'>+	cmd.smart_power_oled_enable.data.panel_inst = panel_inst;</div><div class='add'>+	cmd.smart_power_oled_enable.data.peak_nits = peak_nits;</div><div class='add'>+	cmd.smart_power_oled_enable.data.otg_inst = otg_inst;</div><div class='add'>+	cmd.smart_power_oled_enable.data.digfe_inst = link-&gt;link_enc-&gt;preferred_engine;</div><div class='add'>+	cmd.smart_power_oled_enable.data.digbe_inst = link-&gt;link_enc-&gt;transmitter;</div><div class='add'>+</div><div class='add'>+	cmd.smart_power_oled_enable.data.debugcontrol = debug_control;</div><div class='add'>+	cmd.smart_power_oled_enable.data.triggerline = triggerline;</div><div class='add'>+	cmd.smart_power_oled_enable.data.fixed_max_cll = fixed_CLL;</div><div class='add'>+</div><div class='add'>+	// send cmd</div><div class='add'>+	status = dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	bool status = false;</div><div class='add'>+	unsigned int panel_inst = 0;</div><div class='add'>+</div><div class='add'>+	// get panel_inst</div><div class='add'>+	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='add'>+	// fill in cmd</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.smart_power_oled_getmaxcll.header.type = DMUB_CMD__SMART_POWER_OLED;</div><div class='add'>+	cmd.smart_power_oled_getmaxcll.header.sub_type = DMUB_CMD__SMART_POWER_OLED_GETMAXCLL;</div><div class='add'>+	cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data);</div><div class='add'>+	cmd.smart_power_oled_getmaxcll.header.ret_status = 1;</div><div class='add'>+</div><div class='add'>+	cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst;</div><div class='add'>+</div><div class='add'>+	// send cmd and wait for reply</div><div class='add'>+	status = dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='add'>+</div><div class='add'>+	if (status)</div><div class='add'>+		*pCurrent_MaxCLL = cmd.smart_power_oled_getmaxcll.data.output.current_max_cll;</div><div class='add'>+	else</div><div class='add'>+		*pCurrent_MaxCLL = 0;</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,</div><div class='ctx'> 					    uint8_t dpia_port_index)</div><div class='ctx'> {</div><div class='hunk'>@@ -5305,6 +6190,27 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * dc_process_dmub_dpia_set_tps_notification - Submits tps notification</div><div class='add'>+ *</div><div class='add'>+ * @dc: [in] dc structure</div><div class='add'>+ * @link_index: [in] link index</div><div class='add'>+ * @tps: [in] request tps</div><div class='add'>+ *</div><div class='add'>+ * Submits set_tps_notification command to dmub via inbox message</div><div class='add'>+ */</div><div class='add'>+void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd = {0};</div><div class='add'>+</div><div class='add'>+	cmd.set_tps_notification.header.type = DMUB_CMD__DPIA;</div><div class='add'>+	cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION;</div><div class='add'>+	cmd.set_tps_notification.tps_notification.instance = dc-&gt;links[link_index]-&gt;ddc_hw_inst;</div><div class='add'>+	cmd.set_tps_notification.tps_notification.tps = tps;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: [in] dc structure</div><div class='hunk'>@@ -5457,15 +6363,22 @@ bool dc_abm_save_restore(</div><div class='ctx'> void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-	bool subvp_sw_cursor_req = false;</div><div class='add'>+	unsigned int max_cursor_size = dc-&gt;caps.max_cursor_size;</div><div class='add'>+	unsigned int stream_cursor_size;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='del'>-		if (check_subvp_sw_cursor_fallback_req(dc, dc-&gt;current_state-&gt;streams[i])) {</div><div class='del'>-			subvp_sw_cursor_req = true;</div><div class='del'>-			break;</div><div class='add'>+	if (dc-&gt;debug.allow_sw_cursor_fallback &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;get_max_hw_cursor_size) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+			stream_cursor_size = dc-&gt;res_pool-&gt;funcs-&gt;get_max_hw_cursor_size(dc,</div><div class='add'>+					dc-&gt;current_state,</div><div class='add'>+					dc-&gt;current_state-&gt;streams[i]);</div><div class='add'>+</div><div class='add'>+			if (stream_cursor_size &lt; max_cursor_size) {</div><div class='add'>+				max_cursor_size = stream_cursor_size;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	properties-&gt;cursor_size_limit = subvp_sw_cursor_req ? 64 : dc-&gt;caps.max_cursor_size;</div><div class='add'>+</div><div class='add'>+	properties-&gt;cursor_size_limit = max_cursor_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -5492,20 +6405,689 @@ void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,</div><div class='ctx'> 	edp_link-&gt;dc-&gt;link_srv-&gt;edp_set_panel_power(edp_link, powerOn);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- *****************************************************************************</div><div class='add'>+/**</div><div class='ctx'>  * dc_get_power_profile_for_dc_state() - extracts power profile from dc state</div><div class='ctx'>  *</div><div class='ctx'>  * Called when DM wants to make power policy decisions based on dc_state</div><div class='ctx'>  *</div><div class='del'>- *****************************************************************************</div><div class='add'>+ * @context: Pointer to the dc_state from which the power profile is extracted.</div><div class='add'>+ *</div><div class='add'>+ * Return: The power profile structure containing the power level information.</div><div class='ctx'>  */</div><div class='ctx'> struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_power_profile profile = { 0 };</div><div class='ctx'> </div><div class='del'>-	profile.power_level += !context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='add'>+	profile.power_level = !context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='add'>+	if (!context-&gt;clk_mgr || !context-&gt;clk_mgr-&gt;ctx || !context-&gt;clk_mgr-&gt;ctx-&gt;dc)</div><div class='add'>+		return profile;</div><div class='add'>+	struct dc *dc = context-&gt;clk_mgr-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;get_power_profile)</div><div class='add'>+		profile.power_level = dc-&gt;res_pool-&gt;funcs-&gt;get_power_profile(context);</div><div class='ctx'> 	return profile;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * dc_get_det_buffer_size_from_state() - extracts detile buffer size from dc state</div><div class='add'>+ *</div><div class='add'>+ * This function is called to log the detile buffer size from the dc_state.</div><div class='add'>+ *</div><div class='add'>+ * @context: a pointer to the dc_state from which the detile buffer size is extracted.</div><div class='add'>+ *</div><div class='add'>+ * Return: the size of the detile buffer, or 0 if not available.</div><div class='add'>+ */</div><div class='add'>+unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = context-&gt;clk_mgr-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;get_det_buffer_size)</div><div class='add'>+		return dc-&gt;res_pool-&gt;funcs-&gt;get_det_buffer_size(context);</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_get_host_router_index: Get index of host router from a dpia link</div><div class='add'>+ *</div><div class='add'>+ * This function return a host router index of the target link. If the target link is dpia link.</div><div class='add'>+ *</div><div class='add'>+ * @link: Pointer to the target link (input)</div><div class='add'>+ * @host_router_index: Pointer to store the host router index of the target link (output).</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the host router index is found and valid.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc;</div><div class='add'>+</div><div class='add'>+	if (!link || !host_router_index || link-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;link_index &lt; dc-&gt;lowest_dpia_link_index)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	*host_router_index = (link-&gt;link_index - dc-&gt;lowest_dpia_link_index) / dc-&gt;caps.num_of_dpias_per_host_router;</div><div class='add'>+	if (*host_router_index &lt; dc-&gt;caps.num_of_host_routers)</div><div class='add'>+		return true;</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_is_cursor_limit_pending(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+		if (dc_stream_is_cursor_limit_pending(dc, dc-&gt;current_state-&gt;streams[i]))</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_can_clear_cursor_limit(const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+		if (dc_state_can_clear_stream_cursor_subvp_limit(dc-&gt;current_state-&gt;streams[i], dc-&gt;current_state))</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst,</div><div class='add'>+				struct dc_underflow_debug_data *out_data)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = NULL;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;timing_generators[i] &amp;&amp;</div><div class='add'>+			dc-&gt;res_pool-&gt;timing_generators[i]-&gt;inst == primary_otg_inst) {</div><div class='add'>+				tg = dc-&gt;res_pool-&gt;timing_generators[i];</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_exit_ips_for_hw_access(dc);</div><div class='add'>+	if (dc-&gt;hwss.get_underflow_debug_data)</div><div class='add'>+		dc-&gt;hwss.get_underflow_debug_data(dc, tg, out_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst,</div><div class='add'>+				struct power_features *out_data)</div><div class='add'>+{</div><div class='add'>+	out_data-&gt;uclk_p_state = dc-&gt;current_state-&gt;clk_mgr-&gt;clks.p_state_change_support;</div><div class='add'>+	out_data-&gt;fams = dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *context;</div><div class='add'>+	struct resource_context *res_ctx;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!dc || !dc-&gt;current_state || !state) {</div><div class='add'>+		if (state)</div><div class='add'>+			state-&gt;state_valid = false;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize the state structure */</div><div class='add'>+	memset(state, 0, sizeof(struct dc_register_software_state));</div><div class='add'>+</div><div class='add'>+	context = dc-&gt;current_state;</div><div class='add'>+	res_ctx = &amp;context-&gt;res_ctx;</div><div class='add'>+</div><div class='add'>+	/* Count active pipes and streams */</div><div class='add'>+	state-&gt;active_pipe_count = 0;</div><div class='add'>+	state-&gt;active_stream_count = context-&gt;stream_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (res_ctx-&gt;pipe_ctx[i].stream)</div><div class='add'>+			state-&gt;active_pipe_count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture HUBP programming state for each pipe */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		state-&gt;hubp[i].valid_stream = false;</div><div class='add'>+		if (!pipe_ctx-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		state-&gt;hubp[i].valid_stream = true;</div><div class='add'>+</div><div class='add'>+		/* HUBP register programming variables */</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg)</div><div class='add'>+			state-&gt;hubp[i].vtg_sel = pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+</div><div class='add'>+		state-&gt;hubp[i].hubp_clock_enable = (pipe_ctx-&gt;plane_res.hubp != NULL) ? 1 : 0;</div><div class='add'>+</div><div class='add'>+		state-&gt;hubp[i].valid_plane_state = false;</div><div class='add'>+		if (pipe_ctx-&gt;plane_state) {</div><div class='add'>+			state-&gt;hubp[i].valid_plane_state = true;</div><div class='add'>+			state-&gt;hubp[i].surface_pixel_format = pipe_ctx-&gt;plane_state-&gt;format;</div><div class='add'>+			state-&gt;hubp[i].rotation_angle = pipe_ctx-&gt;plane_state-&gt;rotation;</div><div class='add'>+			state-&gt;hubp[i].h_mirror_en = pipe_ctx-&gt;plane_state-&gt;horizontal_mirror ? 1 : 0;</div><div class='add'>+</div><div class='add'>+			/* Surface size */</div><div class='add'>+			if (pipe_ctx-&gt;plane_state-&gt;plane_size.surface_size.width &gt; 0) {</div><div class='add'>+				state-&gt;hubp[i].surface_size_width = pipe_ctx-&gt;plane_state-&gt;plane_size.surface_size.width;</div><div class='add'>+				state-&gt;hubp[i].surface_size_height = pipe_ctx-&gt;plane_state-&gt;plane_size.surface_size.height;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Viewport dimensions from scaler data */</div><div class='add'>+			if (pipe_ctx-&gt;plane_state-&gt;src_rect.width &gt; 0) {</div><div class='add'>+				state-&gt;hubp[i].pri_viewport_width = pipe_ctx-&gt;plane_state-&gt;src_rect.width;</div><div class='add'>+				state-&gt;hubp[i].pri_viewport_height = pipe_ctx-&gt;plane_state-&gt;src_rect.height;</div><div class='add'>+				state-&gt;hubp[i].pri_viewport_x_start = pipe_ctx-&gt;plane_state-&gt;src_rect.x;</div><div class='add'>+				state-&gt;hubp[i].pri_viewport_y_start = pipe_ctx-&gt;plane_state-&gt;src_rect.y;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* DCC settings */</div><div class='add'>+			state-&gt;hubp[i].surface_dcc_en = (pipe_ctx-&gt;plane_state-&gt;dcc.enable) ? 1 : 0;</div><div class='add'>+			state-&gt;hubp[i].surface_dcc_ind_64b_blk = pipe_ctx-&gt;plane_state-&gt;dcc.independent_64b_blks;</div><div class='add'>+			state-&gt;hubp[i].surface_dcc_ind_128b_blk = pipe_ctx-&gt;plane_state-&gt;dcc.dcc_ind_blk;</div><div class='add'>+</div><div class='add'>+			/* Surface pitch */</div><div class='add'>+			state-&gt;hubp[i].surface_pitch = pipe_ctx-&gt;plane_state-&gt;plane_size.surface_pitch;</div><div class='add'>+			state-&gt;hubp[i].meta_pitch = pipe_ctx-&gt;plane_state-&gt;dcc.meta_pitch;</div><div class='add'>+			state-&gt;hubp[i].chroma_pitch = pipe_ctx-&gt;plane_state-&gt;plane_size.chroma_pitch;</div><div class='add'>+			state-&gt;hubp[i].meta_pitch_c = pipe_ctx-&gt;plane_state-&gt;dcc.meta_pitch_c;</div><div class='add'>+</div><div class='add'>+			/* Surface addresses - primary */</div><div class='add'>+			state-&gt;hubp[i].primary_surface_address_low = pipe_ctx-&gt;plane_state-&gt;address.grph.addr.low_part;</div><div class='add'>+			state-&gt;hubp[i].primary_surface_address_high = pipe_ctx-&gt;plane_state-&gt;address.grph.addr.high_part;</div><div class='add'>+			state-&gt;hubp[i].primary_meta_surface_address_low = pipe_ctx-&gt;plane_state-&gt;address.grph.meta_addr.low_part;</div><div class='add'>+			state-&gt;hubp[i].primary_meta_surface_address_high = pipe_ctx-&gt;plane_state-&gt;address.grph.meta_addr.high_part;</div><div class='add'>+</div><div class='add'>+			/* TMZ settings */</div><div class='add'>+			state-&gt;hubp[i].primary_surface_tmz = pipe_ctx-&gt;plane_state-&gt;address.tmz_surface;</div><div class='add'>+			state-&gt;hubp[i].primary_meta_surface_tmz = pipe_ctx-&gt;plane_state-&gt;address.tmz_surface;</div><div class='add'>+</div><div class='add'>+			/* Tiling configuration */</div><div class='add'>+			state-&gt;hubp[i].min_dc_gfx_version9 = false;</div><div class='add'>+			if (pipe_ctx-&gt;plane_state-&gt;tiling_info.gfxversion &gt;= DcGfxVersion9) {</div><div class='add'>+				state-&gt;hubp[i].min_dc_gfx_version9 = true;</div><div class='add'>+				state-&gt;hubp[i].sw_mode = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.swizzle;</div><div class='add'>+				state-&gt;hubp[i].num_pipes = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.num_pipes;</div><div class='add'>+				state-&gt;hubp[i].num_banks = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.num_banks;</div><div class='add'>+				state-&gt;hubp[i].pipe_interleave = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.pipe_interleave;</div><div class='add'>+				state-&gt;hubp[i].num_shader_engines = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.num_shader_engines;</div><div class='add'>+				state-&gt;hubp[i].num_rb_per_se = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.num_rb_per_se;</div><div class='add'>+				state-&gt;hubp[i].num_pkrs = pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.num_pkrs;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* DML Request Size Configuration */</div><div class='add'>+		if (pipe_ctx-&gt;rq_regs.rq_regs_l.chunk_size &gt; 0) {</div><div class='add'>+			state-&gt;hubp[i].rq_chunk_size = pipe_ctx-&gt;rq_regs.rq_regs_l.chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_min_chunk_size = pipe_ctx-&gt;rq_regs.rq_regs_l.min_chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_meta_chunk_size = pipe_ctx-&gt;rq_regs.rq_regs_l.meta_chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_min_meta_chunk_size = pipe_ctx-&gt;rq_regs.rq_regs_l.min_meta_chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_dpte_group_size = pipe_ctx-&gt;rq_regs.rq_regs_l.dpte_group_size;</div><div class='add'>+			state-&gt;hubp[i].rq_mpte_group_size = pipe_ctx-&gt;rq_regs.rq_regs_l.mpte_group_size;</div><div class='add'>+			state-&gt;hubp[i].rq_swath_height_l = pipe_ctx-&gt;rq_regs.rq_regs_l.swath_height;</div><div class='add'>+			state-&gt;hubp[i].rq_pte_row_height_l = pipe_ctx-&gt;rq_regs.rq_regs_l.pte_row_height_linear;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Chroma request size configuration */</div><div class='add'>+		if (pipe_ctx-&gt;rq_regs.rq_regs_c.chunk_size &gt; 0) {</div><div class='add'>+			state-&gt;hubp[i].rq_chunk_size_c = pipe_ctx-&gt;rq_regs.rq_regs_c.chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_min_chunk_size_c = pipe_ctx-&gt;rq_regs.rq_regs_c.min_chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_meta_chunk_size_c = pipe_ctx-&gt;rq_regs.rq_regs_c.meta_chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_min_meta_chunk_size_c = pipe_ctx-&gt;rq_regs.rq_regs_c.min_meta_chunk_size;</div><div class='add'>+			state-&gt;hubp[i].rq_dpte_group_size_c = pipe_ctx-&gt;rq_regs.rq_regs_c.dpte_group_size;</div><div class='add'>+			state-&gt;hubp[i].rq_mpte_group_size_c = pipe_ctx-&gt;rq_regs.rq_regs_c.mpte_group_size;</div><div class='add'>+			state-&gt;hubp[i].rq_swath_height_c = pipe_ctx-&gt;rq_regs.rq_regs_c.swath_height;</div><div class='add'>+			state-&gt;hubp[i].rq_pte_row_height_c = pipe_ctx-&gt;rq_regs.rq_regs_c.pte_row_height_linear;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* DML expansion modes */</div><div class='add'>+		state-&gt;hubp[i].drq_expansion_mode = pipe_ctx-&gt;rq_regs.drq_expansion_mode;</div><div class='add'>+		state-&gt;hubp[i].prq_expansion_mode = pipe_ctx-&gt;rq_regs.prq_expansion_mode;</div><div class='add'>+		state-&gt;hubp[i].mrq_expansion_mode = pipe_ctx-&gt;rq_regs.mrq_expansion_mode;</div><div class='add'>+		state-&gt;hubp[i].crq_expansion_mode = pipe_ctx-&gt;rq_regs.crq_expansion_mode;</div><div class='add'>+</div><div class='add'>+		/* DML DLG parameters - nominal */</div><div class='add'>+		state-&gt;hubp[i].dst_y_per_vm_vblank = pipe_ctx-&gt;dlg_regs.dst_y_per_vm_vblank;</div><div class='add'>+		state-&gt;hubp[i].dst_y_per_row_vblank = pipe_ctx-&gt;dlg_regs.dst_y_per_row_vblank;</div><div class='add'>+		state-&gt;hubp[i].dst_y_per_vm_flip = pipe_ctx-&gt;dlg_regs.dst_y_per_vm_flip;</div><div class='add'>+		state-&gt;hubp[i].dst_y_per_row_flip = pipe_ctx-&gt;dlg_regs.dst_y_per_row_flip;</div><div class='add'>+</div><div class='add'>+		/* DML prefetch settings */</div><div class='add'>+		state-&gt;hubp[i].dst_y_prefetch = pipe_ctx-&gt;dlg_regs.dst_y_prefetch;</div><div class='add'>+		state-&gt;hubp[i].vratio_prefetch = pipe_ctx-&gt;dlg_regs.vratio_prefetch;</div><div class='add'>+		state-&gt;hubp[i].vratio_prefetch_c = pipe_ctx-&gt;dlg_regs.vratio_prefetch_c;</div><div class='add'>+</div><div class='add'>+		/* TTU parameters */</div><div class='add'>+		state-&gt;hubp[i].qos_level_low_wm = pipe_ctx-&gt;ttu_regs.qos_level_low_wm;</div><div class='add'>+		state-&gt;hubp[i].qos_level_high_wm = pipe_ctx-&gt;ttu_regs.qos_level_high_wm;</div><div class='add'>+		state-&gt;hubp[i].qos_level_flip = pipe_ctx-&gt;ttu_regs.qos_level_flip;</div><div class='add'>+		state-&gt;hubp[i].min_ttu_vblank = pipe_ctx-&gt;ttu_regs.min_ttu_vblank;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture HUBBUB programming state */</div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub) {</div><div class='add'>+		/* Individual DET buffer sizes - software state variables that program DET registers */</div><div class='add'>+		for (i = 0; i &lt; 4 &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			uint32_t det_size = res_ctx-&gt;pipe_ctx[i].det_buffer_size_kb;</div><div class='add'>+			switch (i) {</div><div class='add'>+			case 0:</div><div class='add'>+				state-&gt;hubbub.det0_size = det_size;</div><div class='add'>+				break;</div><div class='add'>+			case 1:</div><div class='add'>+				state-&gt;hubbub.det1_size = det_size;</div><div class='add'>+				break;</div><div class='add'>+			case 2:</div><div class='add'>+				state-&gt;hubbub.det2_size = det_size;</div><div class='add'>+				break;</div><div class='add'>+			case 3:</div><div class='add'>+				state-&gt;hubbub.det3_size = det_size;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Compression buffer configuration - software state that programs COMPBUF_SIZE register */</div><div class='add'>+		// TODO: Handle logic for legacy DCN pre-DCN401</div><div class='add'>+		state-&gt;hubbub.compbuf_size = context-&gt;bw_ctx.bw.dcn.arb_regs.compbuf_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture DPP programming state for each pipe */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		state-&gt;dpp[i].dpp_clock_enable = (pipe_ctx-&gt;plane_res.dpp != NULL) ? 1 : 0;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_res.scl_data.recout.width &gt; 0) {</div><div class='add'>+			/* Access dscl_prog_data directly - this contains the actual software state used for register programming */</div><div class='add'>+			struct dscl_prog_data *dscl_data = &amp;pipe_ctx-&gt;plane_res.scl_data.dscl_prog_data;</div><div class='add'>+</div><div class='add'>+			/* Recout (Rectangle of Interest) configuration - software state that programs RECOUT registers */</div><div class='add'>+			state-&gt;dpp[i].recout_start_x = dscl_data-&gt;recout.x;</div><div class='add'>+			state-&gt;dpp[i].recout_start_y = dscl_data-&gt;recout.y;</div><div class='add'>+			state-&gt;dpp[i].recout_width = dscl_data-&gt;recout.width;</div><div class='add'>+			state-&gt;dpp[i].recout_height = dscl_data-&gt;recout.height;</div><div class='add'>+</div><div class='add'>+			/* MPC (Multiple Pipe/Plane Combiner) size - software state that programs MPC_SIZE registers */</div><div class='add'>+			state-&gt;dpp[i].mpc_width = dscl_data-&gt;mpc_size.width;</div><div class='add'>+			state-&gt;dpp[i].mpc_height = dscl_data-&gt;mpc_size.height;</div><div class='add'>+</div><div class='add'>+			/* DSCL mode - software state that programs SCL_MODE registers */</div><div class='add'>+			state-&gt;dpp[i].dscl_mode = dscl_data-&gt;dscl_mode;</div><div class='add'>+</div><div class='add'>+			/* Scaler ratios - software state that programs scale ratio registers (use actual programmed ratios) */</div><div class='add'>+			state-&gt;dpp[i].horz_ratio_int = dscl_data-&gt;ratios.h_scale_ratio &gt;&gt; 19; // Extract integer part from programmed ratio</div><div class='add'>+			state-&gt;dpp[i].vert_ratio_int = dscl_data-&gt;ratios.v_scale_ratio &gt;&gt; 19; // Extract integer part from programmed ratio</div><div class='add'>+</div><div class='add'>+			/* Basic scaler taps - software state that programs tap control registers (use actual programmed taps) */</div><div class='add'>+			state-&gt;dpp[i].h_taps = dscl_data-&gt;taps.h_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back</div><div class='add'>+			state-&gt;dpp[i].v_taps = dscl_data-&gt;taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture essential clock state for underflow analysis */</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;clks.dispclk_khz &gt; 0) {</div><div class='add'>+		/* Core display clocks affecting bandwidth and timing */</div><div class='add'>+		state-&gt;dccg.dispclk_khz = dc-&gt;clk_mgr-&gt;clks.dispclk_khz;</div><div class='add'>+</div><div class='add'>+		/* Per-pipe clock configuration - only capture what's essential */</div><div class='add'>+		for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+			if (pipe_ctx-&gt;stream) {</div><div class='add'>+				/* Essential clocks that directly affect underflow risk */</div><div class='add'>+				state-&gt;dccg.dppclk_khz[i] = dc-&gt;clk_mgr-&gt;clks.dppclk_khz;</div><div class='add'>+				state-&gt;dccg.pixclk_khz[i] = pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz / 10;</div><div class='add'>+				state-&gt;dccg.dppclk_enable[i] = 1;</div><div class='add'>+</div><div class='add'>+				/* DP stream clock only for DP signals */</div><div class='add'>+				if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT ||</div><div class='add'>+						pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='add'>+					state-&gt;dccg.dpstreamclk_enable[i] = 1;</div><div class='add'>+				} else {</div><div class='add'>+					state-&gt;dccg.dpstreamclk_enable[i] = 0;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				/* Inactive pipe - no clocks */</div><div class='add'>+				state-&gt;dccg.dppclk_khz[i] = 0;</div><div class='add'>+				state-&gt;dccg.pixclk_khz[i] = 0;</div><div class='add'>+				state-&gt;dccg.dppclk_enable[i] = 0;</div><div class='add'>+				if (i &lt; 4) {</div><div class='add'>+					state-&gt;dccg.dpstreamclk_enable[i] = 0;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* DSC clock state - only when actually using DSC */</div><div class='add'>+		for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+			struct pipe_ctx *pipe_ctx = (i &lt; dc-&gt;res_pool-&gt;pipe_count) ? &amp;res_ctx-&gt;pipe_ctx[i] : NULL;</div><div class='add'>+			if (pipe_ctx &amp;&amp; pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;timing.dsc_cfg.num_slices_h &gt; 0) {</div><div class='add'>+				state-&gt;dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;dccg.dscclk_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* SYMCLK32 LE Control - only the essential HPO state for underflow analysis */</div><div class='add'>+		for (i = 0; i &lt; 2; i++) {</div><div class='add'>+			state-&gt;dccg.symclk32_le_enable[i] = 0; /* Default: disabled */</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture essential DSC configuration for underflow analysis */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;timing.dsc_cfg.num_slices_h &gt; 0) {</div><div class='add'>+			/* DSC is enabled - capture essential configuration */</div><div class='add'>+			state-&gt;dsc[i].dsc_clock_enable = 1;</div><div class='add'>+</div><div class='add'>+			/* DSC configuration affecting bandwidth and timing */</div><div class='add'>+			struct dc_dsc_config *dsc_cfg = &amp;pipe_ctx-&gt;stream-&gt;timing.dsc_cfg;</div><div class='add'>+			state-&gt;dsc[i].dsc_num_slices_h = dsc_cfg-&gt;num_slices_h;</div><div class='add'>+			state-&gt;dsc[i].dsc_num_slices_v = dsc_cfg-&gt;num_slices_v;</div><div class='add'>+			state-&gt;dsc[i].dsc_bits_per_pixel = dsc_cfg-&gt;bits_per_pixel;</div><div class='add'>+</div><div class='add'>+			/* OPP pipe source for DSC forwarding */</div><div class='add'>+			if (pipe_ctx-&gt;stream_res.opp) {</div><div class='add'>+				state-&gt;dsc[i].dscrm_dsc_forward_enable = 1;</div><div class='add'>+				state-&gt;dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;dsc[i].dscrm_dsc_forward_enable = 0;</div><div class='add'>+				state-&gt;dsc[i].dscrm_dsc_opp_pipe_source = 0;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* DSC not enabled - clear all fields */</div><div class='add'>+			memset(&amp;state-&gt;dsc[i], 0, sizeof(state-&gt;dsc[i]));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture MPC programming state - comprehensive register field coverage */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;stream) {</div><div class='add'>+			struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='add'>+</div><div class='add'>+			/* MPCC blending tree and mode control - capture actual blend configuration */</div><div class='add'>+			state-&gt;mpc.mpcc_mode[i] = (plane_state-&gt;blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0;</div><div class='add'>+			state-&gt;mpc.mpcc_alpha_blend_mode[i] = plane_state-&gt;per_pixel_alpha ? 1 : 0;</div><div class='add'>+			state-&gt;mpc.mpcc_alpha_multiplied_mode[i] = plane_state-&gt;pre_multiplied_alpha ? 1 : 0;</div><div class='add'>+			state-&gt;mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */</div><div class='add'>+			state-&gt;mpc.mpcc_global_alpha[i] = plane_state-&gt;global_alpha_value;</div><div class='add'>+			state-&gt;mpc.mpcc_global_gain[i] = plane_state-&gt;global_alpha ? 255 : 0;</div><div class='add'>+			state-&gt;mpc.mpcc_bg_bpc[i] = 8; /* Standard 8-bit background */</div><div class='add'>+			state-&gt;mpc.mpcc_bot_gain_mode[i] = 0; /* Standard gain mode */</div><div class='add'>+</div><div class='add'>+			/* MPCC blending tree connections - capture tree topology */</div><div class='add'>+			if (pipe_ctx-&gt;bottom_pipe) {</div><div class='add'>+				state-&gt;mpc.mpcc_bot_sel[i] = pipe_ctx-&gt;bottom_pipe-&gt;pipe_idx;</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */</div><div class='add'>+			}</div><div class='add'>+			state-&gt;mpc.mpcc_top_sel[i] = pipe_ctx-&gt;pipe_idx; /* This pipe's DPP ID */</div><div class='add'>+</div><div class='add'>+			/* MPCC output gamma control - capture gamma programming */</div><div class='add'>+			if (plane_state-&gt;gamma_correction.type != GAMMA_CS_TFM_1D &amp;&amp; plane_state-&gt;gamma_correction.num_entries &gt; 0) {</div><div class='add'>+				state-&gt;mpc.mpcc_ogam_mode[i] = 1; /* Gamma enabled */</div><div class='add'>+				state-&gt;mpc.mpcc_ogam_select[i] = 0; /* Bank A selection */</div><div class='add'>+				state-&gt;mpc.mpcc_ogam_pwl_disable[i] = 0; /* PWL enabled */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;mpc.mpcc_ogam_mode[i] = 0; /* Bypass mode */</div><div class='add'>+				state-&gt;mpc.mpcc_ogam_select[i] = 0;</div><div class='add'>+				state-&gt;mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* MPCC pipe assignment and operational status */</div><div class='add'>+			if (pipe_ctx-&gt;stream_res.opp) {</div><div class='add'>+				state-&gt;mpc.mpcc_opp_id[i] = pipe_ctx-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* MPCC status indicators - active pipe state */</div><div class='add'>+			state-&gt;mpc.mpcc_idle[i] = 0; /* Active pipe - not idle */</div><div class='add'>+			state-&gt;mpc.mpcc_busy[i] = 1; /* Active pipe - busy processing */</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			/* Pipe not active - set disabled/idle state for all fields */</div><div class='add'>+			state-&gt;mpc.mpcc_mode[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_alpha_blend_mode[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_alpha_multiplied_mode[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_blnd_active_overlap_only[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_global_alpha[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_global_gain[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_bg_bpc[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_bot_gain_mode[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */</div><div class='add'>+			state-&gt;mpc.mpcc_top_sel[i] = 0xF; /* No top connection */</div><div class='add'>+			state-&gt;mpc.mpcc_ogam_mode[i] = 0; /* Bypass */</div><div class='add'>+			state-&gt;mpc.mpcc_ogam_select[i] = 0;</div><div class='add'>+			state-&gt;mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */</div><div class='add'>+			state-&gt;mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */</div><div class='add'>+			state-&gt;mpc.mpcc_idle[i] = 1; /* Idle */</div><div class='add'>+			state-&gt;mpc.mpcc_busy[i] = 0; /* Not busy */</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture OPP programming state for each pipe - comprehensive register field coverage */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.opp) {</div><div class='add'>+			struct dc_crtc_timing *timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+</div><div class='add'>+			/* OPP Pipe Control */</div><div class='add'>+			state-&gt;opp[i].opp_pipe_clock_enable = 1; /* Active pipe has clock enabled */</div><div class='add'>+</div><div class='add'>+			/* Display Pattern Generator (DPG) Control - 19 fields */</div><div class='add'>+			if (pipe_ctx-&gt;stream-&gt;test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {</div><div class='add'>+				state-&gt;opp[i].dpg_enable = 1;</div><div class='add'>+			} else {</div><div class='add'>+				/* Video mode - DPG disabled */</div><div class='add'>+				state-&gt;opp[i].dpg_enable = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Format Control (FMT) - 18 fields */</div><div class='add'>+			state-&gt;opp[i].fmt_pixel_encoding = timing-&gt;pixel_encoding;</div><div class='add'>+</div><div class='add'>+			/* Chroma subsampling mode based on pixel encoding */</div><div class='add'>+			if (timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR420) {</div><div class='add'>+				state-&gt;opp[i].fmt_subsampling_mode = 1; /* 4:2:0 subsampling */</div><div class='add'>+			} else if (timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422) {</div><div class='add'>+				state-&gt;opp[i].fmt_subsampling_mode = 2; /* 4:2:2 subsampling */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].fmt_subsampling_mode = 0; /* No subsampling (4:4:4) */</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			state-&gt;opp[i].fmt_cbcr_bit_reduction_bypass = (timing-&gt;pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;</div><div class='add'>+			state-&gt;opp[i].fmt_stereosync_override = (timing-&gt;timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;</div><div class='add'>+</div><div class='add'>+			/* Dithering control based on bit depth */</div><div class='add'>+			if (timing-&gt;display_color_depth &lt; COLOR_DEPTH_121212) {</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_frame_counter_max = 15; /* Typical frame counter max */</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_frame_counter_bit_swap = 0; /* No bit swapping */</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_enable = 1;</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_mode = 0; /* Spatial dithering mode */</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_depth = timing-&gt;display_color_depth;</div><div class='add'>+				state-&gt;opp[i].fmt_temporal_dither_enable = 0; /* Spatial dithering preferred */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_frame_counter_max = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_frame_counter_bit_swap = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_enable = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_mode = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_spatial_dither_depth = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_temporal_dither_enable = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Truncation control for bit depth reduction */</div><div class='add'>+			if (timing-&gt;display_color_depth &lt; COLOR_DEPTH_121212) {</div><div class='add'>+				state-&gt;opp[i].fmt_truncate_enable = 1;</div><div class='add'>+				state-&gt;opp[i].fmt_truncate_depth = timing-&gt;display_color_depth;</div><div class='add'>+				state-&gt;opp[i].fmt_truncate_mode = 0; /* Round mode */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].fmt_truncate_enable = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_truncate_depth = 0;</div><div class='add'>+				state-&gt;opp[i].fmt_truncate_mode = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Data clamping control */</div><div class='add'>+			state-&gt;opp[i].fmt_clamp_data_enable = 1; /* Clamping typically enabled */</div><div class='add'>+			state-&gt;opp[i].fmt_clamp_color_format = timing-&gt;pixel_encoding;</div><div class='add'>+</div><div class='add'>+			/* Dynamic expansion for limited range content */</div><div class='add'>+			if (timing-&gt;pixel_encoding != PIXEL_ENCODING_RGB) {</div><div class='add'>+				state-&gt;opp[i].fmt_dynamic_exp_enable = 1; /* YCbCr typically needs expansion */</div><div class='add'>+				state-&gt;opp[i].fmt_dynamic_exp_mode = 0; /* Standard expansion */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].fmt_dynamic_exp_enable = 0; /* RGB typically full range */</div><div class='add'>+				state-&gt;opp[i].fmt_dynamic_exp_mode = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Legacy field for compatibility */</div><div class='add'>+			state-&gt;opp[i].fmt_bit_depth_control = timing-&gt;display_color_depth;</div><div class='add'>+</div><div class='add'>+			/* Output Buffer (OPPBUF) Control - 6 fields */</div><div class='add'>+			state-&gt;opp[i].oppbuf_active_width = timing-&gt;h_addressable;</div><div class='add'>+			state-&gt;opp[i].oppbuf_pixel_repetition = 0; /* No pixel repetition by default */</div><div class='add'>+</div><div class='add'>+			/* Multi-Stream Output (MSO) / ODM segmentation */</div><div class='add'>+			if (pipe_ctx-&gt;next_odm_pipe) {</div><div class='add'>+				state-&gt;opp[i].oppbuf_display_segmentation = 1; /* Segmented display */</div><div class='add'>+				state-&gt;opp[i].oppbuf_overlap_pixel_num = 0; /* ODM overlap pixels */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].oppbuf_display_segmentation = 0; /* Single segment */</div><div class='add'>+				state-&gt;opp[i].oppbuf_overlap_pixel_num = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* 3D/Stereo control */</div><div class='add'>+			if (timing-&gt;timing_3d_format != TIMING_3D_FORMAT_NONE) {</div><div class='add'>+				state-&gt;opp[i].oppbuf_3d_vact_space1_size = 30; /* Typical stereo blanking */</div><div class='add'>+				state-&gt;opp[i].oppbuf_3d_vact_space2_size = 30;</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].oppbuf_3d_vact_space1_size = 0;</div><div class='add'>+				state-&gt;opp[i].oppbuf_3d_vact_space2_size = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* DSC Forward Config - 3 fields */</div><div class='add'>+			if (timing-&gt;dsc_cfg.num_slices_h &gt; 0) {</div><div class='add'>+				state-&gt;opp[i].dscrm_dsc_forward_enable = 1;</div><div class='add'>+				state-&gt;opp[i].dscrm_dsc_opp_pipe_source = pipe_ctx-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+				state-&gt;opp[i].dscrm_dsc_forward_enable_status = 1; /* Status follows enable */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;opp[i].dscrm_dsc_forward_enable = 0;</div><div class='add'>+				state-&gt;opp[i].dscrm_dsc_opp_pipe_source = 0;</div><div class='add'>+				state-&gt;opp[i].dscrm_dsc_forward_enable_status = 0;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* No OPP resource - set all fields to disabled state */</div><div class='add'>+			memset(&amp;state-&gt;opp[i], 0, sizeof(state-&gt;opp[i]));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Capture OPTC programming state for each pipe - comprehensive register field coverage */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg) {</div><div class='add'>+			struct dc_crtc_timing *timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+</div><div class='add'>+			state-&gt;optc[i].otg_master_inst = pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+</div><div class='add'>+			/* OTG_CONTROL register - 5 fields */</div><div class='add'>+			state-&gt;optc[i].otg_master_enable = 1; /* Active stream */</div><div class='add'>+			state-&gt;optc[i].otg_disable_point_cntl = 0; /* Normal operation */</div><div class='add'>+			state-&gt;optc[i].otg_start_point_cntl = 0; /* Normal start */</div><div class='add'>+			state-&gt;optc[i].otg_field_number_cntl = (timing-&gt;flags.INTERLACE) ? 1 : 0;</div><div class='add'>+			state-&gt;optc[i].otg_out_mux = 0; /* Direct output */</div><div class='add'>+</div><div class='add'>+			/* OTG Horizontal Timing - 7 fields */</div><div class='add'>+			state-&gt;optc[i].otg_h_total = timing-&gt;h_total;</div><div class='add'>+			state-&gt;optc[i].otg_h_blank_start = timing-&gt;h_addressable;</div><div class='add'>+			state-&gt;optc[i].otg_h_blank_end = timing-&gt;h_total - timing-&gt;h_front_porch;</div><div class='add'>+			state-&gt;optc[i].otg_h_sync_start = timing-&gt;h_addressable + timing-&gt;h_front_porch;</div><div class='add'>+			state-&gt;optc[i].otg_h_sync_end = timing-&gt;h_addressable + timing-&gt;h_front_porch + timing-&gt;h_sync_width;</div><div class='add'>+			state-&gt;optc[i].otg_h_sync_polarity = timing-&gt;flags.HSYNC_POSITIVE_POLARITY ? 0 : 1;</div><div class='add'>+			state-&gt;optc[i].otg_h_timing_div_mode = (pipe_ctx-&gt;next_odm_pipe) ? 1 : 0; /* ODM divide mode */</div><div class='add'>+</div><div class='add'>+			/* OTG Vertical Timing - 7 fields */</div><div class='add'>+			state-&gt;optc[i].otg_v_total = timing-&gt;v_total;</div><div class='add'>+			state-&gt;optc[i].otg_v_blank_start = timing-&gt;v_addressable;</div><div class='add'>+			state-&gt;optc[i].otg_v_blank_end = timing-&gt;v_total - timing-&gt;v_front_porch;</div><div class='add'>+			state-&gt;optc[i].otg_v_sync_start = timing-&gt;v_addressable + timing-&gt;v_front_porch;</div><div class='add'>+			state-&gt;optc[i].otg_v_sync_end = timing-&gt;v_addressable + timing-&gt;v_front_porch + timing-&gt;v_sync_width;</div><div class='add'>+			state-&gt;optc[i].otg_v_sync_polarity = timing-&gt;flags.VSYNC_POSITIVE_POLARITY ? 0 : 1;</div><div class='add'>+			state-&gt;optc[i].otg_v_sync_mode = 0; /* Normal sync mode */</div><div class='add'>+</div><div class='add'>+			/* Initialize remaining core fields with appropriate defaults */</div><div class='add'>+			// TODO: Update logic for accurate vtotal min/max</div><div class='add'>+			state-&gt;optc[i].otg_v_total_max = timing-&gt;v_total + 100; /* Typical DRR range */</div><div class='add'>+			state-&gt;optc[i].otg_v_total_min = timing-&gt;v_total - 50;</div><div class='add'>+			state-&gt;optc[i].otg_v_total_mid = timing-&gt;v_total;</div><div class='add'>+</div><div class='add'>+			/* ODM configuration */</div><div class='add'>+			// TODO: Update logic to have complete ODM mappings (e.g. 3:1 and 4:1) stored in single pipe</div><div class='add'>+			if (pipe_ctx-&gt;next_odm_pipe) {</div><div class='add'>+				state-&gt;optc[i].optc_seg0_src_sel = pipe_ctx-&gt;stream_res.opp ? pipe_ctx-&gt;stream_res.opp-&gt;inst : 0;</div><div class='add'>+				state-&gt;optc[i].optc_seg1_src_sel = pipe_ctx-&gt;next_odm_pipe-&gt;stream_res.opp ? pipe_ctx-&gt;next_odm_pipe-&gt;stream_res.opp-&gt;inst : 0;</div><div class='add'>+				state-&gt;optc[i].optc_num_of_input_segment = 1; /* 2 segments - 1 */</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;optc[i].optc_seg0_src_sel = pipe_ctx-&gt;stream_res.opp ? pipe_ctx-&gt;stream_res.opp-&gt;inst : 0;</div><div class='add'>+				state-&gt;optc[i].optc_seg1_src_sel = 0;</div><div class='add'>+				state-&gt;optc[i].optc_num_of_input_segment = 0; /* Single segment */</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* DSC configuration */</div><div class='add'>+			if (timing-&gt;dsc_cfg.num_slices_h &gt; 0) {</div><div class='add'>+				state-&gt;optc[i].optc_dsc_mode = 1; /* DSC enabled */</div><div class='add'>+				state-&gt;optc[i].optc_dsc_bytes_per_pixel = timing-&gt;dsc_cfg.bits_per_pixel / 16; /* Convert to bytes */</div><div class='add'>+				state-&gt;optc[i].optc_dsc_slice_width = timing-&gt;h_addressable / timing-&gt;dsc_cfg.num_slices_h;</div><div class='add'>+			} else {</div><div class='add'>+				state-&gt;optc[i].optc_dsc_mode = 0;</div><div class='add'>+				state-&gt;optc[i].optc_dsc_bytes_per_pixel = 0;</div><div class='add'>+				state-&gt;optc[i].optc_dsc_slice_width = 0;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Essential control fields */</div><div class='add'>+			state-&gt;optc[i].otg_stereo_enable = (timing-&gt;timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0;</div><div class='add'>+			state-&gt;optc[i].otg_interlace_enable = timing-&gt;flags.INTERLACE ? 1 : 0;</div><div class='add'>+			state-&gt;optc[i].otg_clock_enable = 1; /* OTG clock enabled */</div><div class='add'>+			state-&gt;optc[i].vtg0_enable = 1; /* VTG enabled for timing generation */</div><div class='add'>+</div><div class='add'>+			/* Initialize other key fields to defaults */</div><div class='add'>+			state-&gt;optc[i].optc_input_pix_clk_en = 1;</div><div class='add'>+			state-&gt;optc[i].optc_segment_width = (pipe_ctx-&gt;next_odm_pipe) ? (timing-&gt;h_addressable / 2) : timing-&gt;h_addressable;</div><div class='add'>+			state-&gt;optc[i].otg_vready_offset = 1;</div><div class='add'>+			state-&gt;optc[i].otg_vstartup_start = timing-&gt;v_addressable + 10;</div><div class='add'>+			state-&gt;optc[i].otg_vupdate_offset = 0;</div><div class='add'>+			state-&gt;optc[i].otg_vupdate_width = 5;</div><div class='add'>+		} else {</div><div class='add'>+			/* No timing generator resource - initialize all fields to 0 */</div><div class='add'>+			memset(&amp;state-&gt;optc[i], 0, sizeof(state-&gt;optc[i]));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	state-&gt;state_valid = true;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_log_preos_dmcub_info(const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	dc_dmub_srv_log_preos_dmcub_info(dc-&gt;ctx-&gt;dmub_srv);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c<br/>index 801cdbc8117d..bbce751b485f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_debug.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_debug.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_debug.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_debug.c</a></div><div class='hunk'>@@ -46,136 +46,11 @@</div><div class='ctx'> 			DC_LOG_IF_TRACE(__VA_ARGS__); \</div><div class='ctx'> } while (0)</div><div class='ctx'> </div><div class='del'>-#define TIMING_TRACE(...) do {\</div><div class='del'>-	if (dc-&gt;debug.timing_trace) \</div><div class='del'>-		DC_LOG_SYNC(__VA_ARGS__); \</div><div class='del'>-} while (0)</div><div class='del'>-</div><div class='ctx'> #define CLOCK_TRACE(...) do {\</div><div class='ctx'> 	if (dc-&gt;debug.clock_trace) \</div><div class='ctx'> 		DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \</div><div class='ctx'> } while (0)</div><div class='ctx'> </div><div class='del'>-void pre_surface_trace(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		const struct dc_plane_state *const *plane_states,</div><div class='del'>-		int surface_count)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; surface_count; i++) {</div><div class='del'>-		const struct dc_plane_state *plane_state = plane_states[i];</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE("Planes %d:\n", i);</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE(</div><div class='del'>-				"plane_state-&gt;visible = %d;\n"</div><div class='del'>-				"plane_state-&gt;flip_immediate = %d;\n"</div><div class='del'>-				"plane_state-&gt;address.type = %d;\n"</div><div class='del'>-				"plane_state-&gt;address.grph.addr.quad_part = 0x%llX;\n"</div><div class='del'>-				"plane_state-&gt;address.grph.meta_addr.quad_part = 0x%llX;\n"</div><div class='del'>-				"plane_state-&gt;scaling_quality.h_taps = %d;\n"</div><div class='del'>-				"plane_state-&gt;scaling_quality.v_taps = %d;\n"</div><div class='del'>-				"plane_state-&gt;scaling_quality.h_taps_c = %d;\n"</div><div class='del'>-				"plane_state-&gt;scaling_quality.v_taps_c = %d;\n",</div><div class='del'>-				plane_state-&gt;visible,</div><div class='del'>-				plane_state-&gt;flip_immediate,</div><div class='del'>-				plane_state-&gt;address.type,</div><div class='del'>-				plane_state-&gt;address.grph.addr.quad_part,</div><div class='del'>-				plane_state-&gt;address.grph.meta_addr.quad_part,</div><div class='del'>-				plane_state-&gt;scaling_quality.h_taps,</div><div class='del'>-				plane_state-&gt;scaling_quality.v_taps,</div><div class='del'>-				plane_state-&gt;scaling_quality.h_taps_c,</div><div class='del'>-				plane_state-&gt;scaling_quality.v_taps_c);</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE(</div><div class='del'>-				"plane_state-&gt;src_rect.x = %d;\n"</div><div class='del'>-				"plane_state-&gt;src_rect.y = %d;\n"</div><div class='del'>-				"plane_state-&gt;src_rect.width = %d;\n"</div><div class='del'>-				"plane_state-&gt;src_rect.height = %d;\n"</div><div class='del'>-				"plane_state-&gt;dst_rect.x = %d;\n"</div><div class='del'>-				"plane_state-&gt;dst_rect.y = %d;\n"</div><div class='del'>-				"plane_state-&gt;dst_rect.width = %d;\n"</div><div class='del'>-				"plane_state-&gt;dst_rect.height = %d;\n"</div><div class='del'>-				"plane_state-&gt;clip_rect.x = %d;\n"</div><div class='del'>-				"plane_state-&gt;clip_rect.y = %d;\n"</div><div class='del'>-				"plane_state-&gt;clip_rect.width = %d;\n"</div><div class='del'>-				"plane_state-&gt;clip_rect.height = %d;\n",</div><div class='del'>-				plane_state-&gt;src_rect.x,</div><div class='del'>-				plane_state-&gt;src_rect.y,</div><div class='del'>-				plane_state-&gt;src_rect.width,</div><div class='del'>-				plane_state-&gt;src_rect.height,</div><div class='del'>-				plane_state-&gt;dst_rect.x,</div><div class='del'>-				plane_state-&gt;dst_rect.y,</div><div class='del'>-				plane_state-&gt;dst_rect.width,</div><div class='del'>-				plane_state-&gt;dst_rect.height,</div><div class='del'>-				plane_state-&gt;clip_rect.x,</div><div class='del'>-				plane_state-&gt;clip_rect.y,</div><div class='del'>-				plane_state-&gt;clip_rect.width,</div><div class='del'>-				plane_state-&gt;clip_rect.height);</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE(</div><div class='del'>-				"plane_state-&gt;plane_size.surface_size.x = %d;\n"</div><div class='del'>-				"plane_state-&gt;plane_size.surface_size.y = %d;\n"</div><div class='del'>-				"plane_state-&gt;plane_size.surface_size.width = %d;\n"</div><div class='del'>-				"plane_state-&gt;plane_size.surface_size.height = %d;\n"</div><div class='del'>-				"plane_state-&gt;plane_size.surface_pitch = %d;\n",</div><div class='del'>-				plane_state-&gt;plane_size.surface_size.x,</div><div class='del'>-				plane_state-&gt;plane_size.surface_size.y,</div><div class='del'>-				plane_state-&gt;plane_size.surface_size.width,</div><div class='del'>-				plane_state-&gt;plane_size.surface_size.height,</div><div class='del'>-				plane_state-&gt;plane_size.surface_pitch);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE(</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.num_banks = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.bank_width = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.bank_width_c = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.bank_height = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.bank_height_c = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.tile_aspect = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.tile_aspect_c = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.tile_split = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.tile_split_c = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.tile_mode = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.tile_mode_c = %d;\n",</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.num_banks,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.bank_width,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.bank_width_c,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.bank_height,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.bank_height_c,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.tile_aspect,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.tile_aspect_c,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.tile_split,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.tile_split_c,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.tile_mode,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.tile_mode_c);</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE(</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.pipe_config = %d;\n"</div><div class='del'>-				"plane_state-&gt;tiling_info.gfx8.array_mode = %d;\n"</div><div class='del'>-				"plane_state-&gt;color_space = %d;\n"</div><div class='del'>-				"plane_state-&gt;dcc.enable = %d;\n"</div><div class='del'>-				"plane_state-&gt;format = %d;\n"</div><div class='del'>-				"plane_state-&gt;rotation = %d;\n"</div><div class='del'>-				"plane_state-&gt;stereo_format = %d;\n",</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.pipe_config,</div><div class='del'>-				plane_state-&gt;tiling_info.gfx8.array_mode,</div><div class='del'>-				plane_state-&gt;color_space,</div><div class='del'>-				plane_state-&gt;dcc.enable,</div><div class='del'>-				plane_state-&gt;format,</div><div class='del'>-				plane_state-&gt;rotation,</div><div class='del'>-				plane_state-&gt;stereo_format);</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE("plane_state-&gt;tiling_info.gfx9.swizzle = %d;\n",</div><div class='del'>-				plane_state-&gt;tiling_info.gfx9.swizzle);</div><div class='del'>-</div><div class='del'>-		SURFACE_TRACE("\n");</div><div class='del'>-	}</div><div class='del'>-	SURFACE_TRACE("\n");</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void update_surface_trace(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		const struct dc_surface_update *updates,</div><div class='hunk'>@@ -306,43 +181,6 @@ void post_surface_trace(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void context_timing_trace(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct resource_context *res_ctx)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};</div><div class='del'>-	struct crtc_position position;</div><div class='del'>-	unsigned int underlay_idx = dc-&gt;res_pool-&gt;underlay_pipe_index;</div><div class='del'>-	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='del'>-		/* get_position() returns CRTC vertical/horizontal counter</div><div class='del'>-		 * hence not applicable for underlay pipe</div><div class='del'>-		 */</div><div class='del'>-		if (pipe_ctx-&gt;stream == NULL || pipe_ctx-&gt;pipe_idx == underlay_idx)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;get_position(pipe_ctx-&gt;stream_res.tg, &amp;position);</div><div class='del'>-		h_pos[i] = position.horizontal_count;</div><div class='del'>-		v_pos[i] = position.vertical_count;</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe_ctx = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (pipe_ctx-&gt;stream == NULL || pipe_ctx-&gt;pipe_idx == underlay_idx)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  V_pos:%d\n",</div><div class='del'>-				pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;timing.h_total,</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;timing.v_total,</div><div class='del'>-				h_pos[i], v_pos[i]);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void context_clock_trace(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context)</div><div class='hunk'>@@ -428,9 +266,53 @@ char *dc_status_to_str(enum dc_status status)</div><div class='ctx'> 		return "Fail dp payload allocation";</div><div class='ctx'> 	case DC_FAIL_DP_LINK_BANDWIDTH:</div><div class='ctx'> 		return "Insufficient DP link bandwidth";</div><div class='add'>+	case DC_FAIL_HW_CURSOR_SUPPORT:</div><div class='add'>+		return "HW Cursor not supported";</div><div class='add'>+	case DC_FAIL_DP_TUNNEL_BW_VALIDATE:</div><div class='add'>+		return "Fail DP Tunnel BW validation";</div><div class='ctx'> 	case DC_ERROR_UNEXPECTED:</div><div class='ctx'> 		return "Unexpected error";</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return "Unexpected status error";</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+char *dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding)</div><div class='add'>+{</div><div class='add'>+	switch (pixel_encoding) {</div><div class='add'>+	case PIXEL_ENCODING_RGB:</div><div class='add'>+		return "RGB";</div><div class='add'>+	case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+		return "YUV422";</div><div class='add'>+	case PIXEL_ENCODING_YCBCR444:</div><div class='add'>+		return "YUV444";</div><div class='add'>+	case PIXEL_ENCODING_YCBCR420:</div><div class='add'>+		return "YUV420";</div><div class='add'>+	default:</div><div class='add'>+		return "Unknown";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+char *dc_color_depth_to_str(enum dc_color_depth color_depth)</div><div class='add'>+{</div><div class='add'>+	switch (color_depth) {</div><div class='add'>+	case COLOR_DEPTH_666:</div><div class='add'>+		return "6-bpc";</div><div class='add'>+	case COLOR_DEPTH_888:</div><div class='add'>+		return "8-bpc";</div><div class='add'>+	case COLOR_DEPTH_101010:</div><div class='add'>+		return "10-bpc";</div><div class='add'>+	case COLOR_DEPTH_121212:</div><div class='add'>+		return "12-bpc";</div><div class='add'>+	case COLOR_DEPTH_141414:</div><div class='add'>+		return "14-bpc";</div><div class='add'>+	case COLOR_DEPTH_161616:</div><div class='add'>+		return "16-bpc";</div><div class='add'>+	case COLOR_DEPTH_999:</div><div class='add'>+		return "9-bpc";</div><div class='add'>+	case COLOR_DEPTH_111111:</div><div class='add'>+		return "11-bpc";</div><div class='add'>+	default:</div><div class='add'>+		return "Unknown";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c<br/>index 9c05b1a07142..e2763b60482a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c</a></div><div class='hunk'>@@ -32,8 +32,16 @@</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='add'>+#include "opp.h"</div><div class='add'>+#include "dsc.h"</div><div class='add'>+#include "dchubbub.h"</div><div class='add'>+#include "dccg.h"</div><div class='add'>+#include "abm.h"</div><div class='add'>+#include "dcn10/dcn10_hubbub.h"</div><div class='add'>+#include "dce/dmub_hw_lock_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))</div><div class='add'>+#define MAX_NUM_MCACHE 8</div><div class='ctx'> </div><div class='ctx'> /* used as index in array of black_color_format */</div><div class='ctx'> enum black_color_format {</div><div class='hunk'>@@ -176,7 +184,7 @@ static bool is_ycbcr2020_type(</div><div class='ctx'> {</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> </div><div class='del'>-	if (color_space == COLOR_SPACE_2020_YCBCR)</div><div class='add'>+	if (color_space == COLOR_SPACE_2020_YCBCR_LIMITED || color_space == COLOR_SPACE_2020_YCBCR_FULL)</div><div class='ctx'> 		ret = true;</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -247,7 +255,8 @@ void color_space_to_black_color(</div><div class='ctx'> 	case COLOR_SPACE_YCBCR709_BLACK:</div><div class='ctx'> 	case COLOR_SPACE_YCBCR601_LIMITED:</div><div class='ctx'> 	case COLOR_SPACE_YCBCR709_LIMITED:</div><div class='del'>-	case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_FULL:</div><div class='ctx'> 		*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='hunk'>@@ -256,7 +265,7 @@ void color_space_to_black_color(</div><div class='ctx'> 			black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='del'>-	/**</div><div class='add'>+	/*</div><div class='ctx'> 	 * Remove default and add case for all color space</div><div class='ctx'> 	 * so when we forget to add new color space</div><div class='ctx'> 	 * compiler will give a warning</div><div class='hunk'>@@ -312,11 +321,11 @@ void get_mpctree_visual_confirm_color(</div><div class='ctx'> {</div><div class='ctx'> 	const struct tg_color pipe_colors[6] = {</div><div class='ctx'> 			{MAX_TG_COLOR_VALUE, 0, 0}, /* red */</div><div class='del'>-			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */</div><div class='ctx'> 			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */</div><div class='ctx'> 			{0, MAX_TG_COLOR_VALUE, 0}, /* green */</div><div class='add'>+			{0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */</div><div class='ctx'> 			{0, 0, MAX_TG_COLOR_VALUE}, /* blue */</div><div class='del'>-			{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */</div><div class='add'>+			{MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	struct pipe_ctx *top_pipe = pipe_ctx;</div><div class='hunk'>@@ -392,10 +401,10 @@ void get_hdr_visual_confirm_color(</div><div class='ctx'> </div><div class='ctx'> 	switch (top_pipe_ctx-&gt;plane_res.scl_data.format) {</div><div class='ctx'> 	case PIXEL_FORMAT_ARGB2101010:</div><div class='del'>-		if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_PQ) {</div><div class='add'>+		if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {</div><div class='ctx'> 			/* HDR10, ARGB2101010 - set border color to red */</div><div class='ctx'> 			color-&gt;color_r_cr = color_value;</div><div class='del'>-		} else if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_GAMMA22) {</div><div class='add'>+		} else if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {</div><div class='ctx'> 			/* FreeSync 2 ARGB2101010 - set border color to pink */</div><div class='ctx'> 			color-&gt;color_r_cr = color_value;</div><div class='ctx'> 			color-&gt;color_b_cb = color_value;</div><div class='hunk'>@@ -403,10 +412,10 @@ void get_hdr_visual_confirm_color(</div><div class='ctx'> 			is_sdr = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case PIXEL_FORMAT_FP16:</div><div class='del'>-		if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_PQ) {</div><div class='add'>+		if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {</div><div class='ctx'> 			/* HDR10, FP16 - set border color to blue */</div><div class='ctx'> 			color-&gt;color_b_cb = color_value;</div><div class='del'>-		} else if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_GAMMA22) {</div><div class='add'>+		} else if (top_pipe_ctx-&gt;stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {</div><div class='ctx'> 			/* FreeSync 2 HDR - set border color to green */</div><div class='ctx'> 			color-&gt;color_g_y = color_value;</div><div class='ctx'> 		} else</div><div class='hunk'>@@ -425,6 +434,70 @@ void get_hdr_visual_confirm_color(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Visual Confirm color definition for Smart Mux */</div><div class='add'>+void get_smartmux_visual_confirm_color(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='add'>+</div><div class='add'>+	const struct tg_color sm_ver_colors[5] = {</div><div class='add'>+			{0, 0, 0},					/* SMUX_MUXCONTROL_UNSUPPORTED - Black */</div><div class='add'>+			{0, MAX_TG_COLOR_VALUE, 0},			/* SMUX_MUXCONTROL_v10 - Green */</div><div class='add'>+			{0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE},	/* SMUX_MUXCONTROL_v15 - Cyan */</div><div class='add'>+			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, 	/* SMUX_MUXCONTROL_MDM - Yellow */</div><div class='add'>+			{MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, 	/* SMUX_MUXCONTROL_vUNKNOWN - Magenta*/</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.is_apu) {</div><div class='add'>+		/* APU driving the eDP */</div><div class='add'>+		*color = sm_ver_colors[dc-&gt;config.smart_mux_version];</div><div class='add'>+	} else {</div><div class='add'>+		/* dGPU driving the eDP - red */</div><div class='add'>+		color-&gt;color_r_cr = color_value;</div><div class='add'>+		color-&gt;color_g_y = 0;</div><div class='add'>+		color-&gt;color_b_cb = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Visual Confirm color definition for VABC */</div><div class='add'>+void get_vabc_visual_confirm_color(</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='add'>+	struct dc_link *edp_link = NULL;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx &amp;&amp; pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;link) {</div><div class='add'>+		if (pipe_ctx-&gt;stream-&gt;link-&gt;connector_signal == SIGNAL_TYPE_EDP)</div><div class='add'>+			edp_link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (edp_link) {</div><div class='add'>+		switch (edp_link-&gt;backlight_control_type) {</div><div class='add'>+		case BACKLIGHT_CONTROL_PWM:</div><div class='add'>+			color-&gt;color_r_cr = color_value;</div><div class='add'>+			color-&gt;color_g_y = 0;</div><div class='add'>+			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case BACKLIGHT_CONTROL_AMD_AUX:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y = color_value;</div><div class='add'>+			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case BACKLIGHT_CONTROL_VESA_AUX:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y = 0;</div><div class='add'>+			color-&gt;color_b_cb = color_value;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		color-&gt;color_r_cr = 0;</div><div class='add'>+		color-&gt;color_g_y = 0;</div><div class='add'>+		color-&gt;color_b_cb = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void get_subvp_visual_confirm_color(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color)</div><div class='hunk'>@@ -497,6 +570,70 @@ void get_mclk_switch_visual_confirm_color(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void get_cursor_visual_confirm_color(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;cursor_position.enable) {</div><div class='add'>+		color-&gt;color_r_cr = color_value;</div><div class='add'>+		color-&gt;color_g_y = 0;</div><div class='add'>+		color-&gt;color_b_cb = 0;</div><div class='add'>+	} else {</div><div class='add'>+		color-&gt;color_r_cr = 0;</div><div class='add'>+		color-&gt;color_g_y = 0;</div><div class='add'>+		color-&gt;color_b_cb = color_value;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void get_dcc_visual_confirm_color(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	const uint32_t MCACHE_ID_UNASSIGNED = 0xF;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;plane_state-&gt;dcc.enable) {</div><div class='add'>+		color-&gt;color_r_cr = 0; /* black - DCC disabled */</div><div class='add'>+		color-&gt;color_g_y = 0;</div><div class='add'>+		color-&gt;color_b_cb = 0;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_version &lt; DCN_VERSION_4_01) {</div><div class='add'>+		color-&gt;color_r_cr = MAX_TG_COLOR_VALUE; /* red - DCC enabled */</div><div class='add'>+		color-&gt;color_g_y = 0;</div><div class='add'>+		color-&gt;color_b_cb = 0;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	uint32_t first_id = pipe_ctx-&gt;mcache_regs.main.p0.mcache_id_first;</div><div class='add'>+	uint32_t second_id = pipe_ctx-&gt;mcache_regs.main.p0.mcache_id_second;</div><div class='add'>+</div><div class='add'>+	if (first_id != MCACHE_ID_UNASSIGNED &amp;&amp; second_id != MCACHE_ID_UNASSIGNED &amp;&amp; first_id != second_id) {</div><div class='add'>+		color-&gt;color_r_cr = MAX_TG_COLOR_VALUE/2; /* grey - 2 mcache */</div><div class='add'>+		color-&gt;color_g_y = MAX_TG_COLOR_VALUE/2;</div><div class='add'>+		color-&gt;color_b_cb = MAX_TG_COLOR_VALUE/2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	else if (first_id != MCACHE_ID_UNASSIGNED || second_id != MCACHE_ID_UNASSIGNED) {</div><div class='add'>+		const struct tg_color id_colors[MAX_NUM_MCACHE] = {</div><div class='add'>+		{0, MAX_TG_COLOR_VALUE, 0}, /* green */</div><div class='add'>+		{0, 0, MAX_TG_COLOR_VALUE}, /* blue */</div><div class='add'>+		{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */</div><div class='add'>+		{MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */</div><div class='add'>+		{0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */</div><div class='add'>+		{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* white */</div><div class='add'>+		{MAX_TG_COLOR_VALUE/2, 0, 0}, /* dark red */</div><div class='add'>+		{0, MAX_TG_COLOR_VALUE/2, 0}, /* dark green */</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id;</div><div class='add'>+		*color = id_colors[assigned_id];</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void set_p_state_switch_method(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='hunk'>@@ -505,9 +642,10 @@ void set_p_state_switch_method(</div><div class='ctx'> 	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='ctx'> 	bool enable_subvp;</div><div class='ctx'> </div><div class='del'>-	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !pipe_ctx || !vba || !context)</div><div class='add'>+	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !pipe_ctx || !vba)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	pipe_ctx-&gt;p_state_type = P_STATE_UNKNOWN;</div><div class='ctx'> 	if (vba-&gt;DRAMClockChangeSupport[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb] !=</div><div class='ctx'> 			dm_dram_clock_change_unsupported) {</div><div class='ctx'> 		/* MCLK switching is supported */</div><div class='hunk'>@@ -554,13 +692,49 @@ void set_p_state_switch_method(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void set_drr_and_clear_adjust_pending(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct drr_params *params)</div><div class='add'>+{</div><div class='add'>+	/* params can be null.*/</div><div class='add'>+	if (pipe_ctx &amp;&amp; pipe_ctx-&gt;stream_res.tg &amp;&amp;</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg, params);</div><div class='add'>+</div><div class='add'>+	if (stream)</div><div class='add'>+		stream-&gt;adjust.timing_adjust_pending = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void get_fams2_visual_confirm_color(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !pipe_ctx || !context || !dc-&gt;debug.fams2_config.bits.enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* driver only handles visual confirm when FAMS2 is disabled */</div><div class='add'>+	if (!dc_state_is_fams2_in_use(dc, context)) {</div><div class='add'>+		/* when FAMS2 is disabled, all pipes are grey */</div><div class='add'>+		color-&gt;color_g_y = color_value / 2;</div><div class='add'>+		color-&gt;color_b_cb = color_value / 2;</div><div class='add'>+		color-&gt;color_r_cr = color_value / 2;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 		struct dc_dmub_cmd *dc_dmub_cmd,</div><div class='ctx'> 		unsigned int dmub_cmd_count,</div><div class='del'>-		struct block_sequence block_sequence[],</div><div class='del'>-		int *num_steps,</div><div class='add'>+		struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],</div><div class='add'>+		unsigned int *num_steps,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='del'>-		struct dc_stream_status *stream_status)</div><div class='add'>+		struct dc_stream_status *stream_status,</div><div class='add'>+		struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_plane_state *plane = pipe_ctx-&gt;plane_state;</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='hunk'>@@ -574,6 +748,12 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 	if (!plane || !stream)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;hwss.wait_for_dcc_meta_propagation) {</div><div class='add'>+		block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;</div><div class='add'>+		block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;</div><div class='add'>+		block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;</div><div class='add'>+		(*num_steps)++;</div><div class='add'>+	}</div><div class='ctx'> 	if (dc-&gt;hwss.subvp_pipe_control_lock_fast) {</div><div class='ctx'> 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;</div><div class='ctx'> 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;</div><div class='hunk'>@@ -582,6 +762,15 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 		block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;</div><div class='ctx'> 		(*num_steps)++;</div><div class='ctx'> 	}</div><div class='add'>+	if (dc-&gt;hwss.dmub_hw_control_lock_fast) {</div><div class='add'>+		block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;</div><div class='add'>+		block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;</div><div class='add'>+		block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required =</div><div class='add'>+			dc_state_is_fams2_in_use(dc, context) ||</div><div class='add'>+			dmub_hw_lock_mgr_does_link_require_lock(dc, stream-&gt;link);</div><div class='add'>+		block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;</div><div class='add'>+		(*num_steps)++;</div><div class='add'>+	}</div><div class='ctx'> 	if (dc-&gt;hwss.pipe_control_lock) {</div><div class='ctx'> 		block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;</div><div class='ctx'> 		block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;</div><div class='hunk'>@@ -602,57 +791,59 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 	while (current_pipe) {</div><div class='ctx'> 		current_mpc_pipe = current_pipe;</div><div class='ctx'> 		while (current_mpc_pipe) {</div><div class='del'>-			if (dc-&gt;hwss.set_flip_control_gsl &amp;&amp; current_mpc_pipe-&gt;plane_state &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.raw) {</div><div class='del'>-				block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe-&gt;plane_state-&gt;flip_immediate;</div><div class='del'>-				block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;</div><div class='del'>-				(*num_steps)++;</div><div class='del'>-			}</div><div class='del'>-			if (dc-&gt;hwss.program_triplebuffer &amp;&amp; dc-&gt;debug.enable_tri_buf &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.raw) {</div><div class='del'>-				block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;</div><div class='del'>-				block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe-&gt;plane_state-&gt;triplebuffer_flips;</div><div class='del'>-				block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;</div><div class='del'>-				(*num_steps)++;</div><div class='del'>-			}</div><div class='del'>-			if (dc-&gt;hwss.update_plane_addr &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.addr_update) {</div><div class='del'>-				if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &amp;&amp;</div><div class='del'>-						stream_status-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='del'>-					block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='del'>-					block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &amp;current_mpc_pipe-&gt;plane_state-&gt;address;</div><div class='del'>-					block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe-&gt;subvp_index;</div><div class='del'>-					block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;</div><div class='add'>+			if (current_mpc_pipe-&gt;plane_state) {</div><div class='add'>+				if (dc-&gt;hwss.set_flip_control_gsl &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.raw) {</div><div class='add'>+					block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe-&gt;plane_res.hubp;</div><div class='add'>+					block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe-&gt;plane_state-&gt;flip_immediate;</div><div class='add'>+					block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='add'>+				if (dc-&gt;hwss.program_triplebuffer &amp;&amp; dc-&gt;debug.enable_tri_buf &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.raw) {</div><div class='add'>+					block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;</div><div class='add'>+					block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe-&gt;plane_state-&gt;triplebuffer_flips;</div><div class='add'>+					block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='add'>+				if (dc-&gt;hwss.update_plane_addr &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.addr_update) {</div><div class='add'>+					if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &amp;&amp;</div><div class='add'>+							stream_status-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+						block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+						block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &amp;current_mpc_pipe-&gt;plane_state-&gt;address;</div><div class='add'>+						block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe-&gt;subvp_index;</div><div class='add'>+						block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;</div><div class='add'>+						(*num_steps)++;</div><div class='add'>+					}</div><div class='add'>+</div><div class='add'>+					block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;</div><div class='add'>+					block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;</div><div class='ctx'> 					(*num_steps)++;</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='del'>-				block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;</div><div class='del'>-				block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;</div><div class='del'>-				(*num_steps)++;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (hws-&gt;funcs.set_input_transfer_func &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.gamma_change) {</div><div class='del'>-				block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;</div><div class='del'>-				block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe-&gt;plane_state;</div><div class='del'>-				block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;</div><div class='del'>-				(*num_steps)++;</div><div class='del'>-			}</div><div class='add'>+				if (hws-&gt;funcs.set_input_transfer_func &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.gamma_change) {</div><div class='add'>+					block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;</div><div class='add'>+					block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe-&gt;plane_state;</div><div class='add'>+					block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='ctx'> </div><div class='del'>-			if (dc-&gt;hwss.program_gamut_remap &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.gamut_remap_change) {</div><div class='del'>-				block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;</div><div class='del'>-				(*num_steps)++;</div><div class='del'>-			}</div><div class='del'>-			if (current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.input_csc_change) {</div><div class='del'>-				block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].func = DPP_SETUP_DPP;</div><div class='del'>-				(*num_steps)++;</div><div class='del'>-			}</div><div class='del'>-			if (current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.coeff_reduction_change) {</div><div class='del'>-				block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;</div><div class='del'>-				block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;</div><div class='del'>-				(*num_steps)++;</div><div class='add'>+				if (dc-&gt;hwss.program_gamut_remap &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.gamut_remap_change) {</div><div class='add'>+					block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='add'>+				if (current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.input_csc_change) {</div><div class='add'>+					block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].func = DPP_SETUP_DPP;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='add'>+				if (current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.coeff_reduction_change) {</div><div class='add'>+					block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 			if (hws-&gt;funcs.set_output_transfer_func &amp;&amp; current_mpc_pipe-&gt;stream-&gt;update_flags.bits.out_tf) {</div><div class='ctx'> 				block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;</div><div class='hunk'>@@ -661,7 +852,14 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 				block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;</div><div class='ctx'> 				(*num_steps)++;</div><div class='ctx'> 			}</div><div class='del'>-</div><div class='add'>+			if (dc-&gt;debug.visual_confirm != VISUAL_CONFIRM_DISABLE &amp;&amp;</div><div class='add'>+				dc-&gt;hwss.update_visual_confirm_color) {</div><div class='add'>+				block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;</div><div class='add'>+				block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+				block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe-&gt;plane_res.hubp-&gt;inst;</div><div class='add'>+				block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;</div><div class='add'>+				(*num_steps)++;</div><div class='add'>+			}</div><div class='ctx'> 			if (current_mpc_pipe-&gt;stream-&gt;update_flags.bits.out_csc) {</div><div class='ctx'> 				block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> 				block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe-&gt;plane_res.hubp-&gt;inst;</div><div class='hunk'>@@ -705,6 +903,13 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 		block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;</div><div class='ctx'> 		(*num_steps)++;</div><div class='ctx'> 	}</div><div class='add'>+	if (dc-&gt;hwss.dmub_hw_control_lock_fast) {</div><div class='add'>+		block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;</div><div class='add'>+		block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false;</div><div class='add'>+		block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);</div><div class='add'>+		block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;</div><div class='add'>+		(*num_steps)++;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	current_pipe = pipe_ctx;</div><div class='ctx'> 	while (current_pipe) {</div><div class='hunk'>@@ -715,6 +920,13 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 					current_mpc_pipe-&gt;stream &amp;&amp; current_mpc_pipe-&gt;plane_state &amp;&amp;</div><div class='ctx'> 					current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.addr_update &amp;&amp;</div><div class='ctx'> 					!current_mpc_pipe-&gt;plane_state-&gt;skip_manual_trigger) {</div><div class='add'>+				if (dc-&gt;hwss.program_cursor_offload_now) {</div><div class='add'>+					block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc;</div><div class='add'>+					block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;</div><div class='add'>+					block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW;</div><div class='add'>+					(*num_steps)++;</div><div class='add'>+				}</div><div class='add'>+</div><div class='ctx'> 				block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;</div><div class='ctx'> 				block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;</div><div class='ctx'> 				(*num_steps)++;</div><div class='hunk'>@@ -726,7 +938,7 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hwss_execute_sequence(struct dc *dc,</div><div class='del'>-		struct block_sequence block_sequence[],</div><div class='add'>+		struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],</div><div class='ctx'> 		int num_steps)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -746,8 +958,9 @@ void hwss_execute_sequence(struct dc *dc,</div><div class='ctx'> 					params-&gt;pipe_control_lock_params.lock);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case HUBP_SET_FLIP_CONTROL_GSL:</div><div class='del'>-			dc-&gt;hwss.set_flip_control_gsl(params-&gt;set_flip_control_gsl_params.pipe_ctx,</div><div class='del'>-					params-&gt;set_flip_control_gsl_params.flip_immediate);</div><div class='add'>+			params-&gt;set_flip_control_gsl_params.hubp-&gt;funcs-&gt;hubp_set_flip_control_surface_gsl(</div><div class='add'>+				params-&gt;set_flip_control_gsl_params.hubp,</div><div class='add'>+				params-&gt;set_flip_control_gsl_params.flip_immediate);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case HUBP_PROGRAM_TRIPLEBUFFER:</div><div class='ctx'> 			dc-&gt;hwss.program_triplebuffer(params-&gt;program_triplebuffer_params.dc,</div><div class='hunk'>@@ -800,6 +1013,307 @@ void hwss_execute_sequence(struct dc *dc,</div><div class='ctx'> 		case DMUB_SUBVP_SAVE_SURF_ADDR:</div><div class='ctx'> 			hwss_subvp_save_surf_addr(params);</div><div class='ctx'> 			break;</div><div class='add'>+		case HUBP_WAIT_FOR_DCC_META_PROP:</div><div class='add'>+			dc-&gt;hwss.wait_for_dcc_meta_propagation(</div><div class='add'>+					params-&gt;wait_for_dcc_meta_propagation_params.dc,</div><div class='add'>+					params-&gt;wait_for_dcc_meta_propagation_params.top_pipe_to_program);</div><div class='add'>+			break;</div><div class='add'>+		case DMUB_HW_CONTROL_LOCK_FAST:</div><div class='add'>+			dc-&gt;hwss.dmub_hw_control_lock_fast(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_PROGRAM_SURFACE_CONFIG:</div><div class='add'>+			hwss_program_surface_config(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_PROGRAM_MCACHE_ID:</div><div class='add'>+			hwss_program_mcache_id_and_split_coordinate(params);</div><div class='add'>+			break;</div><div class='add'>+		case PROGRAM_CURSOR_UPDATE_NOW:</div><div class='add'>+			dc-&gt;hwss.program_cursor_offload_now(</div><div class='add'>+				params-&gt;program_cursor_update_now_params.dc,</div><div class='add'>+				params-&gt;program_cursor_update_now_params.pipe_ctx);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_WAIT_PIPE_READ_START:</div><div class='add'>+			params-&gt;hubp_wait_pipe_read_start_params.hubp-&gt;funcs-&gt;hubp_wait_pipe_read_start(</div><div class='add'>+				params-&gt;hubp_wait_pipe_read_start_params.hubp);</div><div class='add'>+			break;</div><div class='add'>+		case HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM:</div><div class='add'>+			dc-&gt;hwss.apply_update_flags_for_phantom(params-&gt;apply_update_flags_for_phantom_params.pipe_ctx);</div><div class='add'>+			break;</div><div class='add'>+		case HWS_UPDATE_PHANTOM_VP_POSITION:</div><div class='add'>+			dc-&gt;hwss.update_phantom_vp_position(params-&gt;update_phantom_vp_position_params.dc,</div><div class='add'>+				params-&gt;update_phantom_vp_position_params.context,</div><div class='add'>+				params-&gt;update_phantom_vp_position_params.pipe_ctx);</div><div class='add'>+			break;</div><div class='add'>+		case OPTC_SET_ODM_COMBINE:</div><div class='add'>+			hwss_set_odm_combine(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPTC_SET_ODM_BYPASS:</div><div class='add'>+			hwss_set_odm_bypass(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_PIPE_CLOCK_CONTROL:</div><div class='add'>+			hwss_opp_pipe_clock_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL:</div><div class='add'>+			hwss_opp_program_left_edge_extra_pixel(params);</div><div class='add'>+			break;</div><div class='add'>+		case DCCG_SET_DTO_DSCCLK:</div><div class='add'>+			hwss_dccg_set_dto_dscclk(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_SET_CONFIG:</div><div class='add'>+			hwss_dsc_set_config(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_ENABLE:</div><div class='add'>+			hwss_dsc_enable(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_SET_DSC_CONFIG:</div><div class='add'>+			hwss_tg_set_dsc_config(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_DISCONNECT:</div><div class='add'>+			hwss_dsc_disconnect(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_READ_STATE:</div><div class='add'>+			hwss_dsc_read_state(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_CALCULATE_AND_SET_CONFIG:</div><div class='add'>+			hwss_dsc_calculate_and_set_config(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_ENABLE_WITH_OPP:</div><div class='add'>+			hwss_dsc_enable_with_opp(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_PROGRAM_GLOBAL_SYNC:</div><div class='add'>+			hwss_tg_program_global_sync(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_WAIT_FOR_STATE:</div><div class='add'>+			hwss_tg_wait_for_state(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_SET_VTG_PARAMS:</div><div class='add'>+			hwss_tg_set_vtg_params(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_SETUP_VERTICAL_INTERRUPT2:</div><div class='add'>+			hwss_tg_setup_vertical_interrupt2(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_SET_HDR_MULTIPLIER:</div><div class='add'>+			hwss_dpp_set_hdr_multiplier(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_PROGRAM_DET_SIZE:</div><div class='add'>+			hwss_program_det_size(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_PROGRAM_DET_SEGMENTS:</div><div class='add'>+			hwss_program_det_segments(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_SET_DYN_EXPANSION:</div><div class='add'>+			hwss_opp_set_dyn_expansion(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_PROGRAM_FMT:</div><div class='add'>+			hwss_opp_program_fmt(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_PROGRAM_BIT_DEPTH_REDUCTION:</div><div class='add'>+			hwss_opp_program_bit_depth_reduction(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_SET_DISP_PATTERN_GENERATOR:</div><div class='add'>+			hwss_opp_set_disp_pattern_generator(params);</div><div class='add'>+			break;</div><div class='add'>+		case ABM_SET_PIPE:</div><div class='add'>+			hwss_set_abm_pipe(params);</div><div class='add'>+			break;</div><div class='add'>+		case ABM_SET_LEVEL:</div><div class='add'>+			hwss_set_abm_level(params);</div><div class='add'>+			break;</div><div class='add'>+		case ABM_SET_IMMEDIATE_DISABLE:</div><div class='add'>+			hwss_set_abm_immediate_disable(params);</div><div class='add'>+			break;</div><div class='add'>+		case MPC_REMOVE_MPCC:</div><div class='add'>+			hwss_mpc_remove_mpcc(params);</div><div class='add'>+			break;</div><div class='add'>+		case OPP_SET_MPCC_DISCONNECT_PENDING:</div><div class='add'>+			hwss_opp_set_mpcc_disconnect_pending(params);</div><div class='add'>+			break;</div><div class='add'>+		case DC_SET_OPTIMIZED_REQUIRED:</div><div class='add'>+			hwss_dc_set_optimized_required(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_DISCONNECT:</div><div class='add'>+			hwss_hubp_disconnect(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBBUB_FORCE_PSTATE_CHANGE_CONTROL:</div><div class='add'>+			hwss_hubbub_force_pstate_change_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_ENABLE_CRTC:</div><div class='add'>+			hwss_tg_enable_crtc(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_SET_GSL:</div><div class='add'>+			hwss_tg_set_gsl(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_SET_GSL_SOURCE_SELECT:</div><div class='add'>+			hwss_tg_set_gsl_source_select(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_WAIT_FLIP_PENDING:</div><div class='add'>+			hwss_hubp_wait_flip_pending(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_WAIT_DOUBLE_BUFFER_PENDING:</div><div class='add'>+			hwss_tg_wait_double_buffer_pending(params);</div><div class='add'>+			break;</div><div class='add'>+		case UPDATE_FORCE_PSTATE:</div><div class='add'>+			hwss_update_force_pstate(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBBUB_APPLY_DEDCN21_147_WA:</div><div class='add'>+			hwss_hubbub_apply_dedcn21_147_wa(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBBUB_ALLOW_SELF_REFRESH_CONTROL:</div><div class='add'>+			hwss_hubbub_allow_self_refresh_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case TG_GET_FRAME_COUNT:</div><div class='add'>+			hwss_tg_get_frame_count(params);</div><div class='add'>+			break;</div><div class='add'>+		case MPC_SET_DWB_MUX:</div><div class='add'>+			hwss_mpc_set_dwb_mux(params);</div><div class='add'>+			break;</div><div class='add'>+		case MPC_DISABLE_DWB_MUX:</div><div class='add'>+			hwss_mpc_disable_dwb_mux(params);</div><div class='add'>+			break;</div><div class='add'>+		case MCIF_WB_CONFIG_BUF:</div><div class='add'>+			hwss_mcif_wb_config_buf(params);</div><div class='add'>+			break;</div><div class='add'>+		case MCIF_WB_CONFIG_ARB:</div><div class='add'>+			hwss_mcif_wb_config_arb(params);</div><div class='add'>+			break;</div><div class='add'>+		case MCIF_WB_ENABLE:</div><div class='add'>+			hwss_mcif_wb_enable(params);</div><div class='add'>+			break;</div><div class='add'>+		case MCIF_WB_DISABLE:</div><div class='add'>+			hwss_mcif_wb_disable(params);</div><div class='add'>+			break;</div><div class='add'>+		case DWBC_ENABLE:</div><div class='add'>+			hwss_dwbc_enable(params);</div><div class='add'>+			break;</div><div class='add'>+		case DWBC_DISABLE:</div><div class='add'>+			hwss_dwbc_disable(params);</div><div class='add'>+			break;</div><div class='add'>+		case DWBC_UPDATE:</div><div class='add'>+			hwss_dwbc_update(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_UPDATE_MALL_SEL:</div><div class='add'>+			hwss_hubp_update_mall_sel(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_PREPARE_SUBVP_BUFFERING:</div><div class='add'>+			hwss_hubp_prepare_subvp_buffering(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SET_BLANK_EN:</div><div class='add'>+			hwss_hubp_set_blank_en(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_DISABLE_CONTROL:</div><div class='add'>+			hwss_hubp_disable_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBBUB_SOFT_RESET:</div><div class='add'>+			hwss_hubbub_soft_reset(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_CLK_CNTL:</div><div class='add'>+			hwss_hubp_clk_cntl(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_INIT:</div><div class='add'>+			hwss_hubp_init(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS:</div><div class='add'>+			hwss_hubp_set_vm_system_aperture_settings(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SET_FLIP_INT:</div><div class='add'>+			hwss_hubp_set_flip_int(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_DPPCLK_CONTROL:</div><div class='add'>+			hwss_dpp_dppclk_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case DISABLE_PHANTOM_CRTC:</div><div class='add'>+			hwss_disable_phantom_crtc(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_PG_STATUS:</div><div class='add'>+			hwss_dsc_pg_status(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_WAIT_DISCONNECT_PENDING_CLEAR:</div><div class='add'>+			hwss_dsc_wait_disconnect_pending_clear(params);</div><div class='add'>+			break;</div><div class='add'>+		case DSC_DISABLE:</div><div class='add'>+			hwss_dsc_disable(params);</div><div class='add'>+			break;</div><div class='add'>+		case DCCG_SET_REF_DSCCLK:</div><div class='add'>+			hwss_dccg_set_ref_dscclk(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_PG_CONTROL:</div><div class='add'>+			hwss_dpp_pg_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_PG_CONTROL:</div><div class='add'>+			hwss_hubp_pg_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_RESET:</div><div class='add'>+			hwss_hubp_reset(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_RESET:</div><div class='add'>+			hwss_dpp_reset(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_ROOT_CLOCK_CONTROL:</div><div class='add'>+			hwss_dpp_root_clock_control(params);</div><div class='add'>+			break;</div><div class='add'>+		case DC_IP_REQUEST_CNTL:</div><div class='add'>+			hwss_dc_ip_request_cntl(params);</div><div class='add'>+			break;</div><div class='add'>+		case DCCG_UPDATE_DPP_DTO:</div><div class='add'>+			hwss_dccg_update_dpp_dto(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_VTG_SEL:</div><div class='add'>+			hwss_hubp_vtg_sel(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SETUP2:</div><div class='add'>+			hwss_hubp_setup2(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SETUP:</div><div class='add'>+			hwss_hubp_setup(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SET_UNBOUNDED_REQUESTING:</div><div class='add'>+			hwss_hubp_set_unbounded_requesting(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SETUP_INTERDEPENDENT2:</div><div class='add'>+			hwss_hubp_setup_interdependent2(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SETUP_INTERDEPENDENT:</div><div class='add'>+			hwss_hubp_setup_interdependent(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_SET_CURSOR_MATRIX:</div><div class='add'>+			hwss_dpp_set_cursor_matrix(params);</div><div class='add'>+			break;</div><div class='add'>+		case MPC_UPDATE_BLENDING:</div><div class='add'>+			hwss_mpc_update_blending(params);</div><div class='add'>+			break;</div><div class='add'>+		case MPC_ASSERT_IDLE_MPCC:</div><div class='add'>+			hwss_mpc_assert_idle_mpcc(params);</div><div class='add'>+			break;</div><div class='add'>+		case MPC_INSERT_PLANE:</div><div class='add'>+			hwss_mpc_insert_plane(params);</div><div class='add'>+			break;</div><div class='add'>+		case DPP_SET_SCALER:</div><div class='add'>+			hwss_dpp_set_scaler(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_MEM_PROGRAM_VIEWPORT:</div><div class='add'>+			hwss_hubp_mem_program_viewport(params);</div><div class='add'>+			break;</div><div class='add'>+		case ABORT_CURSOR_OFFLOAD_UPDATE:</div><div class='add'>+			hwss_abort_cursor_offload_update(params);</div><div class='add'>+			break;</div><div class='add'>+		case SET_CURSOR_ATTRIBUTE:</div><div class='add'>+			hwss_set_cursor_attribute(params);</div><div class='add'>+			break;</div><div class='add'>+		case SET_CURSOR_POSITION:</div><div class='add'>+			hwss_set_cursor_position(params);</div><div class='add'>+			break;</div><div class='add'>+		case SET_CURSOR_SDR_WHITE_LEVEL:</div><div class='add'>+			hwss_set_cursor_sdr_white_level(params);</div><div class='add'>+			break;</div><div class='add'>+		case PROGRAM_OUTPUT_CSC:</div><div class='add'>+			hwss_program_output_csc(params);</div><div class='add'>+			break;</div><div class='add'>+		case HUBP_SET_BLANK:</div><div class='add'>+			hwss_hubp_set_blank(params);</div><div class='add'>+			break;</div><div class='add'>+		case PHANTOM_HUBP_POST_ENABLE:</div><div class='add'>+			hwss_phantom_hubp_post_enable(params);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			ASSERT(false);</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -807,6 +1321,338 @@ void hwss_execute_sequence(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Helper function to add OPTC pipe control lock to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		bool lock)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.pipe_control_lock_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.pipe_control_lock_params.lock = lock;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPTC_PIPE_CONTROL_LOCK;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP set flip control GSL to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool flip_immediate)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_flip_control_gsl_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP program triplebuffer to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		bool enableTripleBuffer)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_triplebuffer_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP update plane address to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_plane_addr_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_UPDATE_PLANE_ADDR;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DPP set input transfer function to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_input_transfer_func_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_input_transfer_func_params.plane_state = plane_state;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DPP program gamut remap to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_PROGRAM_GAMUT_REMAP;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DPP program bias and scale to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add OPTC program manual trigger to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DPP set output transfer function to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_transfer_func_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_transfer_func_params.stream = stream;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC update visual confirm to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_visual_confirm_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC power on MPC mem PWR to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int mpcc_id,</div><div class='add'>+		bool power_on)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC set output CSC to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int opp_id,</div><div class='add'>+		const uint16_t *regval,</div><div class='add'>+		enum mpc_output_csc_mode ocsc_mode)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_csc_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_csc_params.opp_id = opp_id;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_csc_params.regval = regval;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_SET_OUTPUT_CSC;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC set OCSC default to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int opp_id,</div><div class='add'>+		enum dc_color_space colorspace,</div><div class='add'>+		enum mpc_output_csc_mode ocsc_mode)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_ocsc_default_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_ocsc_default_params.opp_id = opp_id;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_ocsc_default_params.color_space = colorspace;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_SET_OCSC_DEFAULT;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DMUB send DMCUB command to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		union dmub_rb_cmd *cmd,</div><div class='add'>+		enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.send_dmcub_cmd_params.ctx = ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.send_dmcub_cmd_params.cmd = cmd;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.send_dmcub_cmd_params.wait_type = wait_type;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DMUB_SEND_DMCUB_CMD;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DMUB SubVP save surface address to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+		struct dc_plane_address *addr,</div><div class='add'>+		uint8_t subvp_index)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.subvp_save_surf_addr.addr = addr;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP wait for DCC meta propagation to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *top_pipe_to_program)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP wait pipe read start to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_WAIT_PIPE_READ_START;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HWS apply update flags for phantom to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HWS update phantom VP position to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_phantom_vp_position_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_phantom_vp_position_params.context = context;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add OPTC set ODM combine to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,</div><div class='add'>+		int odm_slice_width, int last_odm_slice_width)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_combine_params.tg = tg;</div><div class='add'>+		memcpy(seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES);</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPTC_SET_ODM_COMBINE;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add OPTC set ODM bypass to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_bypass_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_odm_bypass_params.timing = timing;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPTC_SET_ODM_BYPASS;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hwss_send_dmcub_cmd(union block_sequence_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *ctx = params-&gt;send_dmcub_cmd_params.ctx;</div><div class='hunk'>@@ -816,6 +1662,276 @@ void hwss_send_dmcub_cmd(union block_sequence_params *params)</div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Helper function to add TG program global sync to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		int vready_offset,</div><div class='add'>+		unsigned int vstartup_lines,</div><div class='add'>+		unsigned int vupdate_offset_pixels,</div><div class='add'>+		unsigned int vupdate_vupdate_width_pixels,</div><div class='add'>+		unsigned int pstate_keepout_start_lines)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_program_global_sync_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_PROGRAM_GLOBAL_SYNC;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add TG wait for state to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		enum crtc_state state)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_wait_for_state_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_wait_for_state_params.state = state;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_WAIT_FOR_STATE;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add TG set VTG params to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		struct dc_crtc_timing *dc_crtc_timing,</div><div class='add'>+		bool program_fp2)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_vtg_params_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_SET_VTG_PARAMS;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add TG setup vertical interrupt2 to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, int start_line)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add DPP set HDR multiplier to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp, uint32_t hw_mult)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_SET_HDR_MULTIPLIER;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP program DET size to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		unsigned int hubp_inst,</div><div class='add'>+		unsigned int det_buffer_size_kb)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_det_size_params.hubbub = hubbub;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_det_size_params.hubp_inst = hubp_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PROGRAM_DET_SIZE;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_hubp_pipe_mcache_regs *mcache_regs)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PROGRAM_MCACHE_ID;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		bool enable,</div><div class='add'>+		bool wait)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_force_pstate_change_control_params.enable = enable;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_force_pstate_change_control_params.wait = wait;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP program DET segments to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		unsigned int hubp_inst,</div><div class='add'>+		unsigned int det_size)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_det_segments_params.hubbub = hubbub;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_det_segments_params.hubp_inst = hubp_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_det_segments_params.det_size = det_size;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PROGRAM_DET_SEGMENTS;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add OPP set dynamic expansion to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		enum dc_color_space color_space,</div><div class='add'>+		enum dc_color_depth color_depth,</div><div class='add'>+		enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_dyn_expansion_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_dyn_expansion_params.color_space = color_space;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_dyn_expansion_params.signal = signal;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_SET_DYN_EXPANSION;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add OPP program FMT to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		struct bit_depth_reduction_params *fmt_bit_depth,</div><div class='add'>+		struct clamping_and_pixel_encoding_params *clamping)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_fmt_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_fmt_params.clamping = clamping;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_PROGRAM_FMT;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		enum dc_pixel_encoding pixel_encoding,</div><div class='add'>+		bool is_otg_master)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add ABM set pipe to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_abm_pipe_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = ABM_SET_PIPE;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add ABM set level to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_abm_set_level(struct block_sequence_state *seq_state,</div><div class='add'>+		struct abm *abm,</div><div class='add'>+		uint32_t abm_level)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_abm_level_params.abm = abm;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_abm_level_params.abm_level = abm_level;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = ABM_SET_LEVEL;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add TG enable CRTC to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_enable_crtc_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_ENABLE_CRTC;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP wait flip pending to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		unsigned int timeout_us,</div><div class='add'>+		unsigned int polling_interval_us)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_wait_flip_pending_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_WAIT_FLIP_PENDING;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add TG wait double buffer pending to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		unsigned int timeout_us,</div><div class='add'>+		unsigned int polling_interval_us)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_wait_double_buffer_pending_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hwss_program_manual_trigger(union block_sequence_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx = params-&gt;program_manual_trigger_params.pipe_ctx;</div><div class='hunk'>@@ -830,6 +1946,9 @@ void hwss_setup_dpp(union block_sequence_params *params)</div><div class='ctx'> 	struct dpp *dpp = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='ctx'> </div><div class='add'>+	if (!plane_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (dpp &amp;&amp; dpp-&gt;funcs-&gt;dpp_setup) {</div><div class='ctx'> 		// program the input csc</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_setup(dpp,</div><div class='hunk'>@@ -846,10 +1965,9 @@ void hwss_program_bias_and_scale(union block_sequence_params *params)</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx = params-&gt;program_bias_and_scale_params.pipe_ctx;</div><div class='ctx'> 	struct dpp *dpp = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='del'>-	struct dc_bias_and_scale bns_params = {0};</div><div class='add'>+	struct dc_bias_and_scale bns_params = plane_state-&gt;bias_and_scale;</div><div class='ctx'> </div><div class='ctx'> 	//TODO :for CNVC set scale and bias registers if necessary</div><div class='del'>-	build_prescale_params(&amp;bns_params, plane_state);</div><div class='ctx'> 	if (dpp-&gt;funcs-&gt;dpp_program_bias_and_scale)</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_program_bias_and_scale(dpp, &amp;bns_params);</div><div class='ctx'> }</div><div class='hunk'>@@ -901,6 +2019,39 @@ void hwss_subvp_save_surf_addr(union block_sequence_params *params)</div><div class='ctx'> 	dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hwss_program_surface_config(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;program_surface_config_params.hubp;</div><div class='add'>+	enum surface_pixel_format format = params-&gt;program_surface_config_params.format;</div><div class='add'>+	struct dc_tiling_info *tiling_info = params-&gt;program_surface_config_params.tiling_info;</div><div class='add'>+	struct plane_size size = params-&gt;program_surface_config_params.plane_size;</div><div class='add'>+	enum dc_rotation_angle rotation = params-&gt;program_surface_config_params.rotation;</div><div class='add'>+	struct dc_plane_dcc_param *dcc = params-&gt;program_surface_config_params.dcc;</div><div class='add'>+	bool horizontal_mirror = params-&gt;program_surface_config_params.horizontal_mirror;</div><div class='add'>+	int compat_level = params-&gt;program_surface_config_params.compat_level;</div><div class='add'>+</div><div class='add'>+	hubp-&gt;funcs-&gt;hubp_program_surface_config(</div><div class='add'>+		hubp,</div><div class='add'>+		format,</div><div class='add'>+		tiling_info,</div><div class='add'>+		&amp;size,</div><div class='add'>+		rotation,</div><div class='add'>+		dcc,</div><div class='add'>+		horizontal_mirror,</div><div class='add'>+		compat_level);</div><div class='add'>+</div><div class='add'>+	hubp-&gt;power_gated = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;program_mcache_id_and_split_coordinate.hubp;</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs *mcache_regs = params-&gt;program_mcache_id_and_split_coordinate.mcache_regs;</div><div class='add'>+</div><div class='add'>+	hubp-&gt;funcs-&gt;hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void get_surface_tile_visual_confirm_color(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color)</div><div class='hunk'>@@ -921,3 +2072,2000 @@ void get_surface_tile_visual_confirm_color(</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank</div><div class='add'>+ * pattern updates</div><div class='add'>+ *</div><div class='add'>+ * @dc: [in] dc reference</div><div class='add'>+ * @context: [in] hardware context in use</div><div class='add'>+ */</div><div class='add'>+void hwss_wait_for_all_blank_complete(struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *opp_head;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!hws-&gt;funcs.wait_for_blank_complete)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		opp_head = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		hws-&gt;funcs.wait_for_blank_complete(opp_head-&gt;stream_res.opp);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *otg_master;</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		otg_master = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)</div><div class='add'>+			continue;</div><div class='add'>+		tg = otg_master-&gt;stream_res.tg;</div><div class='add'>+		if (tg-&gt;funcs-&gt;wait_odm_doublebuffer_pending_clear)</div><div class='add'>+			tg-&gt;funcs-&gt;wait_odm_doublebuffer_pending_clear(tg);</div><div class='add'>+		if (tg-&gt;funcs-&gt;wait_otg_disable)</div><div class='add'>+			tg-&gt;funcs-&gt;wait_otg_disable(tg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* ODM update may require to reprogram blank pattern for each OPP */</div><div class='add'>+	hwss_wait_for_all_blank_complete(dc, context);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		int count = 0;</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe-&gt;plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Timeout 100 ms */</div><div class='add'>+		while (count &lt; 100000) {</div><div class='add'>+			/* Must set to false to start with, due to OR in update function */</div><div class='add'>+			pipe-&gt;plane_state-&gt;status.is_flip_pending = false;</div><div class='add'>+			dc-&gt;hwss.update_pending_status(pipe);</div><div class='add'>+			if (!pipe-&gt;plane_state-&gt;status.is_flip_pending)</div><div class='add'>+				break;</div><div class='add'>+			udelay(1);</div><div class='add'>+			count++;</div><div class='add'>+		}</div><div class='add'>+		ASSERT(!pipe-&gt;plane_state-&gt;status.is_flip_pending);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)</div><div class='add'>+{</div><div class='add'>+/*</div><div class='add'>+ * This function calls HWSS to wait for any potentially double buffered</div><div class='add'>+ * operations to complete. It should be invoked as a pre-amble prior</div><div class='add'>+ * to full update programming before asserting any HW locks.</div><div class='add'>+ */</div><div class='add'>+	int pipe_idx;</div><div class='add'>+	int opp_inst;</div><div class='add'>+	int opp_count = dc-&gt;res_pool-&gt;res_cap-&gt;num_opp;</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	int mpcc_inst;</div><div class='add'>+	const struct pipe_ctx *pipe_ctx;</div><div class='add'>+</div><div class='add'>+	for (pipe_idx = 0; pipe_idx &lt; dc-&gt;res_pool-&gt;pipe_count; pipe_idx++) {</div><div class='add'>+		pipe_ctx = &amp;dc_context-&gt;res_ctx.pipe_ctx[pipe_idx];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* For full update we must wait for all double buffer updates, not just DRR updates. This</div><div class='add'>+		 * is particularly important for minimal transitions. Only check for OTG_MASTER pipes,</div><div class='add'>+		 * as non-OTG Master pipes share the same OTG as</div><div class='add'>+		 */</div><div class='add'>+		if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &amp;&amp; dc-&gt;hwss.wait_for_all_pending_updates) {</div><div class='add'>+			dc-&gt;hwss.wait_for_all_pending_updates(pipe_ctx);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+		if (!hubp)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		mpcc_inst = hubp-&gt;inst;</div><div class='add'>+		// MPCC inst is equal to pipe index in practice</div><div class='add'>+		for (opp_inst = 0; opp_inst &lt; opp_count; opp_inst++) {</div><div class='add'>+			if ((dc-&gt;res_pool-&gt;opps[opp_inst] != NULL) &amp;&amp;</div><div class='add'>+				(dc-&gt;res_pool-&gt;opps[opp_inst]-&gt;mpcc_disconnect_pending[mpcc_inst])) {</div><div class='add'>+				dc-&gt;res_pool-&gt;mpc-&gt;funcs-&gt;wait_for_idle(dc-&gt;res_pool-&gt;mpc, mpcc_inst);</div><div class='add'>+				dc-&gt;res_pool-&gt;opps[opp_inst]-&gt;mpcc_disconnect_pending[mpcc_inst] = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	hwss_wait_for_odm_update_pending_complete(dc, dc_context);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)</div><div class='add'>+{</div><div class='add'>+	/* wait for outstanding updates */</div><div class='add'>+	hwss_wait_for_outstanding_hw_updates(dc, dc_context);</div><div class='add'>+</div><div class='add'>+	/* perform outstanding post update programming */</div><div class='add'>+	if (dc-&gt;hwss.program_outstanding_updates)</div><div class='add'>+		dc-&gt;hwss.program_outstanding_updates(dc, dc_context);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_odm_combine(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;set_odm_combine_params.tg;</div><div class='add'>+	int *opp_inst = params-&gt;set_odm_combine_params.opp_inst;</div><div class='add'>+	int opp_head_count = params-&gt;set_odm_combine_params.opp_head_count;</div><div class='add'>+	int odm_slice_width = params-&gt;set_odm_combine_params.odm_slice_width;</div><div class='add'>+	int last_odm_slice_width = params-&gt;set_odm_combine_params.last_odm_slice_width;</div><div class='add'>+</div><div class='add'>+	if (tg &amp;&amp; tg-&gt;funcs-&gt;set_odm_combine)</div><div class='add'>+		tg-&gt;funcs-&gt;set_odm_combine(tg, opp_inst, opp_head_count,</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_odm_bypass(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;set_odm_bypass_params.tg;</div><div class='add'>+	const struct dc_crtc_timing *timing = params-&gt;set_odm_bypass_params.timing;</div><div class='add'>+</div><div class='add'>+	if (tg &amp;&amp; tg-&gt;funcs-&gt;set_odm_bypass)</div><div class='add'>+		tg-&gt;funcs-&gt;set_odm_bypass(tg, timing);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_pipe_clock_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_pipe_clock_control_params.opp;</div><div class='add'>+	bool enable = params-&gt;opp_pipe_clock_control_params.enable;</div><div class='add'>+</div><div class='add'>+	if (opp &amp;&amp; opp-&gt;funcs-&gt;opp_pipe_clock_control)</div><div class='add'>+		opp-&gt;funcs-&gt;opp_pipe_clock_control(opp, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_program_left_edge_extra_pixel_params.opp;</div><div class='add'>+	enum dc_pixel_encoding pixel_encoding = params-&gt;opp_program_left_edge_extra_pixel_params.pixel_encoding;</div><div class='add'>+	bool is_otg_master = params-&gt;opp_program_left_edge_extra_pixel_params.is_otg_master;</div><div class='add'>+</div><div class='add'>+	if (opp &amp;&amp; opp-&gt;funcs-&gt;opp_program_left_edge_extra_pixel)</div><div class='add'>+		opp-&gt;funcs-&gt;opp_program_left_edge_extra_pixel(opp, pixel_encoding, is_otg_master);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dccg_set_dto_dscclk(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dccg *dccg = params-&gt;dccg_set_dto_dscclk_params.dccg;</div><div class='add'>+	int inst = params-&gt;dccg_set_dto_dscclk_params.inst;</div><div class='add'>+	int num_slices_h = params-&gt;dccg_set_dto_dscclk_params.num_slices_h;</div><div class='add'>+</div><div class='add'>+	if (dccg &amp;&amp; dccg-&gt;funcs-&gt;set_dto_dscclk)</div><div class='add'>+		dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, inst, num_slices_h);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_set_config(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = params-&gt;dsc_set_config_params.dsc;</div><div class='add'>+	struct dsc_config *dsc_cfg = params-&gt;dsc_set_config_params.dsc_cfg;</div><div class='add'>+	struct dsc_optc_config *dsc_optc_cfg = params-&gt;dsc_set_config_params.dsc_optc_cfg;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_set_config)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_enable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = params-&gt;dsc_enable_params.dsc;</div><div class='add'>+	int opp_inst = params-&gt;dsc_enable_params.opp_inst;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_enable)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_enable(dsc, opp_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_dsc_config(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_set_dsc_config_params.tg;</div><div class='add'>+	enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED;</div><div class='add'>+	uint32_t bytes_per_pixel = 0;</div><div class='add'>+	uint32_t slice_width = 0;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;tg_set_dsc_config_params.enable) {</div><div class='add'>+		struct dsc_optc_config *dsc_optc_cfg = params-&gt;tg_set_dsc_config_params.dsc_optc_cfg;</div><div class='add'>+</div><div class='add'>+		if (dsc_optc_cfg) {</div><div class='add'>+			bytes_per_pixel = dsc_optc_cfg-&gt;bytes_per_pixel;</div><div class='add'>+			slice_width = dsc_optc_cfg-&gt;slice_width;</div><div class='add'>+			optc_dsc_mode = dsc_optc_cfg-&gt;is_pixel_format_444 ?</div><div class='add'>+				OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (tg &amp;&amp; tg-&gt;funcs-&gt;set_dsc_config)</div><div class='add'>+		tg-&gt;funcs-&gt;set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_disconnect(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = params-&gt;dsc_disconnect_params.dsc;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_disconnect)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_disconnect(dsc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_read_state(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = params-&gt;dsc_read_state_params.dsc;</div><div class='add'>+	struct dcn_dsc_state *dsc_state = params-&gt;dsc_read_state_params.dsc_state;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_read_state)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_read_state(dsc, dsc_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_calculate_and_set_config(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;dsc_calculate_and_set_config_params.pipe_ctx;</div><div class='add'>+	struct pipe_ctx *top_pipe = pipe_ctx;</div><div class='add'>+	bool enable = params-&gt;dsc_calculate_and_set_config_params.enable;</div><div class='add'>+	int opp_cnt = params-&gt;dsc_calculate_and_set_config_params.opp_cnt;</div><div class='add'>+</div><div class='add'>+	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+</div><div class='add'>+	if (!dsc || !enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Calculate DSC configuration - extracted from dcn32_update_dsc_on_stream */</div><div class='add'>+	struct dsc_config dsc_cfg;</div><div class='add'>+</div><div class='add'>+	while (top_pipe-&gt;prev_odm_pipe)</div><div class='add'>+		top_pipe = top_pipe-&gt;prev_odm_pipe;</div><div class='add'>+</div><div class='add'>+	dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + top_pipe-&gt;dsc_padding_params.dsc_hactive_padding +</div><div class='add'>+			stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='add'>+	dsc_cfg.pic_height = stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_top + stream-&gt;timing.v_border_bottom;</div><div class='add'>+	dsc_cfg.pixel_encoding = stream-&gt;timing.pixel_encoding;</div><div class='add'>+	dsc_cfg.color_depth = stream-&gt;timing.display_color_depth;</div><div class='add'>+	dsc_cfg.is_odm = top_pipe-&gt;next_odm_pipe ? true : false;</div><div class='add'>+	dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='add'>+	dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;</div><div class='add'>+	dsc_cfg.dsc_padding = top_pipe-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='add'>+</div><div class='add'>+	/* Set DSC configuration */</div><div class='add'>+	if (dsc-&gt;funcs-&gt;dsc_set_config)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg,</div><div class='add'>+			&amp;params-&gt;dsc_calculate_and_set_config_params.dsc_optc_cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_enable_with_opp(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;dsc_enable_with_opp_params.pipe_ctx;</div><div class='add'>+	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_enable)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_program_global_sync(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_program_global_sync_params.tg;</div><div class='add'>+	int vready_offset = params-&gt;tg_program_global_sync_params.vready_offset;</div><div class='add'>+	unsigned int vstartup_lines = params-&gt;tg_program_global_sync_params.vstartup_lines;</div><div class='add'>+	unsigned int vupdate_offset_pixels = params-&gt;tg_program_global_sync_params.vupdate_offset_pixels;</div><div class='add'>+	unsigned int vupdate_vupdate_width_pixels = params-&gt;tg_program_global_sync_params.vupdate_vupdate_width_pixels;</div><div class='add'>+	unsigned int pstate_keepout_start_lines = params-&gt;tg_program_global_sync_params.pstate_keepout_start_lines;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;program_global_sync) {</div><div class='add'>+		tg-&gt;funcs-&gt;program_global_sync(tg, vready_offset, vstartup_lines,</div><div class='add'>+			vupdate_offset_pixels, vupdate_vupdate_width_pixels, pstate_keepout_start_lines);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_wait_for_state(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_wait_for_state_params.tg;</div><div class='add'>+	enum crtc_state state = params-&gt;tg_wait_for_state_params.state;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;wait_for_state)</div><div class='add'>+		tg-&gt;funcs-&gt;wait_for_state(tg, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_vtg_params(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_set_vtg_params_params.tg;</div><div class='add'>+	struct dc_crtc_timing *timing = params-&gt;tg_set_vtg_params_params.timing;</div><div class='add'>+	bool program_fp2 = params-&gt;tg_set_vtg_params_params.program_fp2;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;set_vtg_params)</div><div class='add'>+		tg-&gt;funcs-&gt;set_vtg_params(tg, timing, program_fp2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_setup_vertical_interrupt2_params.tg;</div><div class='add'>+	int start_line = params-&gt;tg_setup_vertical_interrupt2_params.start_line;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;setup_vertical_interrupt2)</div><div class='add'>+		tg-&gt;funcs-&gt;setup_vertical_interrupt2(tg, start_line);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp = params-&gt;dpp_set_hdr_multiplier_params.dpp;</div><div class='add'>+	uint32_t hw_mult = params-&gt;dpp_set_hdr_multiplier_params.hw_mult;</div><div class='add'>+</div><div class='add'>+	if (dpp-&gt;funcs-&gt;dpp_set_hdr_multiplier)</div><div class='add'>+		dpp-&gt;funcs-&gt;dpp_set_hdr_multiplier(dpp, hw_mult);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_program_det_size(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = params-&gt;program_det_size_params.hubbub;</div><div class='add'>+	unsigned int hubp_inst = params-&gt;program_det_size_params.hubp_inst;</div><div class='add'>+	unsigned int det_buffer_size_kb = params-&gt;program_det_size_params.det_buffer_size_kb;</div><div class='add'>+</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_det_size)</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_det_size(hubbub, hubp_inst, det_buffer_size_kb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_program_det_segments(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = params-&gt;program_det_segments_params.hubbub;</div><div class='add'>+	unsigned int hubp_inst = params-&gt;program_det_segments_params.hubp_inst;</div><div class='add'>+	unsigned int det_size = params-&gt;program_det_segments_params.det_size;</div><div class='add'>+</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_det_segments(hubbub, hubp_inst, det_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_set_dyn_expansion(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_set_dyn_expansion_params.opp;</div><div class='add'>+	enum dc_color_space color_space = params-&gt;opp_set_dyn_expansion_params.color_space;</div><div class='add'>+	enum dc_color_depth color_depth = params-&gt;opp_set_dyn_expansion_params.color_depth;</div><div class='add'>+	enum signal_type signal = params-&gt;opp_set_dyn_expansion_params.signal;</div><div class='add'>+</div><div class='add'>+	if (opp-&gt;funcs-&gt;opp_set_dyn_expansion)</div><div class='add'>+		opp-&gt;funcs-&gt;opp_set_dyn_expansion(opp, color_space, color_depth, signal);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_program_fmt(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_program_fmt_params.opp;</div><div class='add'>+	struct bit_depth_reduction_params *fmt_bit_depth = params-&gt;opp_program_fmt_params.fmt_bit_depth;</div><div class='add'>+	struct clamping_and_pixel_encoding_params *clamping = params-&gt;opp_program_fmt_params.clamping;</div><div class='add'>+</div><div class='add'>+	if (opp-&gt;funcs-&gt;opp_program_fmt)</div><div class='add'>+		opp-&gt;funcs-&gt;opp_program_fmt(opp, fmt_bit_depth, clamping);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_program_bit_depth_reduction_params.opp;</div><div class='add'>+	bool use_default_params = params-&gt;opp_program_bit_depth_reduction_params.use_default_params;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;opp_program_bit_depth_reduction_params.pipe_ctx;</div><div class='add'>+	struct bit_depth_reduction_params bit_depth_params;</div><div class='add'>+</div><div class='add'>+	if (use_default_params)</div><div class='add'>+		memset(&amp;bit_depth_params, 0, sizeof(bit_depth_params));</div><div class='add'>+	else</div><div class='add'>+		resource_build_bit_depth_reduction_params(pipe_ctx-&gt;stream, &amp;bit_depth_params);</div><div class='add'>+</div><div class='add'>+	if (opp-&gt;funcs-&gt;opp_program_bit_depth_reduction)</div><div class='add'>+		opp-&gt;funcs-&gt;opp_program_bit_depth_reduction(opp, &amp;bit_depth_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_set_disp_pattern_generator_params.opp;</div><div class='add'>+	enum controller_dp_test_pattern test_pattern = params-&gt;opp_set_disp_pattern_generator_params.test_pattern;</div><div class='add'>+	enum controller_dp_color_space color_space = params-&gt;opp_set_disp_pattern_generator_params.color_space;</div><div class='add'>+	enum dc_color_depth color_depth = params-&gt;opp_set_disp_pattern_generator_params.color_depth;</div><div class='add'>+	struct tg_color *solid_color = params-&gt;opp_set_disp_pattern_generator_params.use_solid_color ?</div><div class='add'>+		&amp;params-&gt;opp_set_disp_pattern_generator_params.solid_color : NULL;</div><div class='add'>+	int width = params-&gt;opp_set_disp_pattern_generator_params.width;</div><div class='add'>+	int height = params-&gt;opp_set_disp_pattern_generator_params.height;</div><div class='add'>+	int offset = params-&gt;opp_set_disp_pattern_generator_params.offset;</div><div class='add'>+</div><div class='add'>+	if (opp &amp;&amp; opp-&gt;funcs-&gt;opp_set_disp_pattern_generator) {</div><div class='add'>+		opp-&gt;funcs-&gt;opp_set_disp_pattern_generator(opp, test_pattern, color_space,</div><div class='add'>+			color_depth, solid_color, width, height, offset);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_abm_pipe(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;set_abm_pipe_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;set_abm_pipe_params.pipe_ctx;</div><div class='add'>+</div><div class='add'>+	dc-&gt;hwss.set_pipe(pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_abm_level(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct abm *abm = params-&gt;set_abm_level_params.abm;</div><div class='add'>+	unsigned int abm_level = params-&gt;set_abm_level_params.abm_level;</div><div class='add'>+</div><div class='add'>+	if (abm-&gt;funcs-&gt;set_abm_level)</div><div class='add'>+		abm-&gt;funcs-&gt;set_abm_level(abm, abm_level);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_abm_immediate_disable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;set_abm_immediate_disable_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;set_abm_immediate_disable_params.pipe_ctx;</div><div class='add'>+</div><div class='add'>+	if (dc &amp;&amp; dc-&gt;hwss.set_abm_immediate_disable)</div><div class='add'>+		dc-&gt;hwss.set_abm_immediate_disable(pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_remove_mpcc(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mpc *mpc = params-&gt;mpc_remove_mpcc_params.mpc;</div><div class='add'>+	struct mpc_tree *mpc_tree_params = params-&gt;mpc_remove_mpcc_params.mpc_tree_params;</div><div class='add'>+	struct mpcc *mpcc_to_remove = params-&gt;mpc_remove_mpcc_params.mpcc_to_remove;</div><div class='add'>+</div><div class='add'>+	mpc-&gt;funcs-&gt;remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct output_pixel_processor *opp = params-&gt;opp_set_mpcc_disconnect_pending_params.opp;</div><div class='add'>+	int mpcc_inst = params-&gt;opp_set_mpcc_disconnect_pending_params.mpcc_inst;</div><div class='add'>+	bool pending = params-&gt;opp_set_mpcc_disconnect_pending_params.pending;</div><div class='add'>+</div><div class='add'>+	opp-&gt;mpcc_disconnect_pending[mpcc_inst] = pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dc_set_optimized_required(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;dc_set_optimized_required_params.dc;</div><div class='add'>+	bool optimized_required = params-&gt;dc_set_optimized_required_params.optimized_required;</div><div class='add'>+</div><div class='add'>+	dc-&gt;optimized_required = optimized_required;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_disconnect(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_disconnect_params.hubp;</div><div class='add'>+</div><div class='add'>+	if (hubp-&gt;funcs-&gt;hubp_disconnect)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_disconnect(hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = params-&gt;hubbub_force_pstate_change_control_params.hubbub;</div><div class='add'>+	bool enable = params-&gt;hubbub_force_pstate_change_control_params.enable;</div><div class='add'>+	bool wait = params-&gt;hubbub_force_pstate_change_control_params.wait;</div><div class='add'>+</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;force_pstate_change_control) {</div><div class='add'>+		hubbub-&gt;funcs-&gt;force_pstate_change_control(hubbub, enable, wait);</div><div class='add'>+		/* Add delay when enabling pstate change control */</div><div class='add'>+		if (enable)</div><div class='add'>+			udelay(500);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_enable_crtc(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_enable_crtc_params.tg;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;enable_crtc)</div><div class='add'>+		tg-&gt;funcs-&gt;enable_crtc(tg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_gsl(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_set_gsl_params.tg;</div><div class='add'>+	struct gsl_params *gsl = &amp;params-&gt;tg_set_gsl_params.gsl;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;set_gsl)</div><div class='add'>+		tg-&gt;funcs-&gt;set_gsl(tg, gsl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_gsl_source_select(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_set_gsl_source_select_params.tg;</div><div class='add'>+	int group_idx = params-&gt;tg_set_gsl_source_select_params.group_idx;</div><div class='add'>+	uint32_t gsl_ready_signal = params-&gt;tg_set_gsl_source_select_params.gsl_ready_signal;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;set_gsl_source_select)</div><div class='add'>+		tg-&gt;funcs-&gt;set_gsl_source_select(tg, group_idx, gsl_ready_signal);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_wait_flip_pending(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_wait_flip_pending_params.hubp;</div><div class='add'>+	unsigned int timeout_us = params-&gt;hubp_wait_flip_pending_params.timeout_us;</div><div class='add'>+	unsigned int polling_interval_us = params-&gt;hubp_wait_flip_pending_params.polling_interval_us;</div><div class='add'>+	int j = 0;</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; timeout_us / polling_interval_us</div><div class='add'>+		&amp;&amp; hubp-&gt;funcs-&gt;hubp_is_flip_pending(hubp); j++)</div><div class='add'>+		udelay(polling_interval_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_wait_double_buffer_pending_params.tg;</div><div class='add'>+	unsigned int timeout_us = params-&gt;tg_wait_double_buffer_pending_params.timeout_us;</div><div class='add'>+	unsigned int polling_interval_us = params-&gt;tg_wait_double_buffer_pending_params.polling_interval_us;</div><div class='add'>+	int j = 0;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;get_optc_double_buffer_pending) {</div><div class='add'>+		for (j = 0; j &lt; timeout_us / polling_interval_us</div><div class='add'>+			&amp;&amp; tg-&gt;funcs-&gt;get_optc_double_buffer_pending(tg); j++)</div><div class='add'>+			udelay(polling_interval_us);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_update_force_pstate(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;update_force_pstate_params.dc;</div><div class='add'>+	struct dc_state *context = params-&gt;update_force_pstate_params.context;</div><div class='add'>+	struct dce_hwseq *hwseq = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	if (hwseq-&gt;funcs.update_force_pstate)</div><div class='add'>+		hwseq-&gt;funcs.update_force_pstate(dc, context);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = params-&gt;hubbub_apply_dedcn21_147_wa_params.hubbub;</div><div class='add'>+</div><div class='add'>+	hubbub-&gt;funcs-&gt;apply_DEDCN21_147_wa(hubbub);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = params-&gt;hubbub_allow_self_refresh_control_params.hubbub;</div><div class='add'>+	bool allow = params-&gt;hubbub_allow_self_refresh_control_params.allow;</div><div class='add'>+</div><div class='add'>+	hubbub-&gt;funcs-&gt;allow_self_refresh_control(hubbub, allow);</div><div class='add'>+</div><div class='add'>+	if (!allow &amp;&amp; params-&gt;hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied)</div><div class='add'>+		*params-&gt;hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_tg_get_frame_count(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;tg_get_frame_count_params.tg;</div><div class='add'>+	unsigned int *frame_count = params-&gt;tg_get_frame_count_params.frame_count;</div><div class='add'>+</div><div class='add'>+	*frame_count = tg-&gt;funcs-&gt;get_frame_count(tg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_set_dwb_mux(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mpc *mpc = params-&gt;mpc_set_dwb_mux_params.mpc;</div><div class='add'>+	int dwb_id = params-&gt;mpc_set_dwb_mux_params.dwb_id;</div><div class='add'>+	int mpcc_id = params-&gt;mpc_set_dwb_mux_params.mpcc_id;</div><div class='add'>+</div><div class='add'>+	if (mpc-&gt;funcs-&gt;set_dwb_mux)</div><div class='add'>+		mpc-&gt;funcs-&gt;set_dwb_mux(mpc, dwb_id, mpcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_disable_dwb_mux(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mpc *mpc = params-&gt;mpc_disable_dwb_mux_params.mpc;</div><div class='add'>+	unsigned int dwb_id = params-&gt;mpc_disable_dwb_mux_params.dwb_id;</div><div class='add'>+</div><div class='add'>+	if (mpc-&gt;funcs-&gt;disable_dwb_mux)</div><div class='add'>+		mpc-&gt;funcs-&gt;disable_dwb_mux(mpc, dwb_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_config_buf(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mcif_wb *mcif_wb = params-&gt;mcif_wb_config_buf_params.mcif_wb;</div><div class='add'>+	struct mcif_buf_params *mcif_buf_params = params-&gt;mcif_wb_config_buf_params.mcif_buf_params;</div><div class='add'>+	unsigned int dest_height = params-&gt;mcif_wb_config_buf_params.dest_height;</div><div class='add'>+</div><div class='add'>+	if (mcif_wb-&gt;funcs-&gt;config_mcif_buf)</div><div class='add'>+		mcif_wb-&gt;funcs-&gt;config_mcif_buf(mcif_wb, mcif_buf_params, dest_height);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_config_arb(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mcif_wb *mcif_wb = params-&gt;mcif_wb_config_arb_params.mcif_wb;</div><div class='add'>+	struct mcif_arb_params *mcif_arb_params = params-&gt;mcif_wb_config_arb_params.mcif_arb_params;</div><div class='add'>+</div><div class='add'>+	if (mcif_wb-&gt;funcs-&gt;config_mcif_arb)</div><div class='add'>+		mcif_wb-&gt;funcs-&gt;config_mcif_arb(mcif_wb, mcif_arb_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_enable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mcif_wb *mcif_wb = params-&gt;mcif_wb_enable_params.mcif_wb;</div><div class='add'>+</div><div class='add'>+	if (mcif_wb-&gt;funcs-&gt;enable_mcif)</div><div class='add'>+		mcif_wb-&gt;funcs-&gt;enable_mcif(mcif_wb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_disable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mcif_wb *mcif_wb = params-&gt;mcif_wb_disable_params.mcif_wb;</div><div class='add'>+</div><div class='add'>+	if (mcif_wb-&gt;funcs-&gt;disable_mcif)</div><div class='add'>+		mcif_wb-&gt;funcs-&gt;disable_mcif(mcif_wb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dwbc_enable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb = params-&gt;dwbc_enable_params.dwb;</div><div class='add'>+	struct dc_dwb_params *dwb_params = params-&gt;dwbc_enable_params.dwb_params;</div><div class='add'>+</div><div class='add'>+	if (dwb-&gt;funcs-&gt;enable)</div><div class='add'>+		dwb-&gt;funcs-&gt;enable(dwb, dwb_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dwbc_disable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb = params-&gt;dwbc_disable_params.dwb;</div><div class='add'>+</div><div class='add'>+	if (dwb-&gt;funcs-&gt;disable)</div><div class='add'>+		dwb-&gt;funcs-&gt;disable(dwb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dwbc_update(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb = params-&gt;dwbc_update_params.dwb;</div><div class='add'>+	struct dc_dwb_params *dwb_params = params-&gt;dwbc_update_params.dwb_params;</div><div class='add'>+</div><div class='add'>+	if (dwb-&gt;funcs-&gt;update)</div><div class='add'>+		dwb-&gt;funcs-&gt;update(dwb, dwb_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_update_mall_sel(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_update_mall_sel_params.hubp;</div><div class='add'>+	uint32_t mall_sel = params-&gt;hubp_update_mall_sel_params.mall_sel;</div><div class='add'>+	bool cache_cursor = params-&gt;hubp_update_mall_sel_params.cache_cursor;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_mall_sel)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_update_mall_sel(hubp, mall_sel, cache_cursor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_prepare_subvp_buffering_params.hubp;</div><div class='add'>+	bool enable = params-&gt;hubp_prepare_subvp_buffering_params.enable;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_prepare_subvp_buffering)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_prepare_subvp_buffering(hubp, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_blank_en(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_set_blank_en_params.hubp;</div><div class='add'>+	bool enable = params-&gt;hubp_set_blank_en_params.enable;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;set_hubp_blank_en)</div><div class='add'>+		hubp-&gt;funcs-&gt;set_hubp_blank_en(hubp, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_disable_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_disable_control_params.hubp;</div><div class='add'>+	bool disable = params-&gt;hubp_disable_control_params.disable;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_disable_control)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_disable_control(hubp, disable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_soft_reset(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = params-&gt;hubbub_soft_reset_params.hubbub;</div><div class='add'>+	bool reset = params-&gt;hubbub_soft_reset_params.reset;</div><div class='add'>+</div><div class='add'>+	if (hubbub)</div><div class='add'>+		params-&gt;hubbub_soft_reset_params.hubbub_soft_reset(hubbub, reset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_clk_cntl(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_clk_cntl_params.hubp;</div><div class='add'>+	bool enable = params-&gt;hubp_clk_cntl_params.enable;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_clk_cntl) {</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_clk_cntl(hubp, enable);</div><div class='add'>+		hubp-&gt;power_gated = !enable;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_init(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_init_params.hubp;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_init)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_init(hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_set_vm_system_aperture_settings_params.hubp;</div><div class='add'>+	struct vm_system_aperture_param apt;</div><div class='add'>+</div><div class='add'>+	apt.sys_default = params-&gt;hubp_set_vm_system_aperture_settings_params.sys_default;</div><div class='add'>+	apt.sys_high = params-&gt;hubp_set_vm_system_aperture_settings_params.sys_high;</div><div class='add'>+	apt.sys_low = params-&gt;hubp_set_vm_system_aperture_settings_params.sys_low;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_set_vm_system_aperture_settings)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_set_vm_system_aperture_settings(hubp, &amp;apt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_flip_int(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_set_flip_int_params.hubp;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_set_flip_int)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_set_flip_int(hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_dppclk_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp = params-&gt;dpp_dppclk_control_params.dpp;</div><div class='add'>+	bool dppclk_div = params-&gt;dpp_dppclk_control_params.dppclk_div;</div><div class='add'>+	bool enable = params-&gt;dpp_dppclk_control_params.enable;</div><div class='add'>+</div><div class='add'>+	if (dpp &amp;&amp; dpp-&gt;funcs-&gt;dpp_dppclk_control)</div><div class='add'>+		dpp-&gt;funcs-&gt;dpp_dppclk_control(dpp, dppclk_div, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_disable_phantom_crtc(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = params-&gt;disable_phantom_crtc_params.tg;</div><div class='add'>+</div><div class='add'>+	if (tg &amp;&amp; tg-&gt;funcs-&gt;disable_phantom_crtc)</div><div class='add'>+		tg-&gt;funcs-&gt;disable_phantom_crtc(tg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_pg_status(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = params-&gt;dsc_pg_status_params.hws;</div><div class='add'>+	int dsc_inst = params-&gt;dsc_pg_status_params.dsc_inst;</div><div class='add'>+</div><div class='add'>+	if (hws &amp;&amp; hws-&gt;funcs.dsc_pg_status)</div><div class='add'>+		params-&gt;dsc_pg_status_params.is_ungated = hws-&gt;funcs.dsc_pg_status(hws, dsc_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = params-&gt;dsc_wait_disconnect_pending_clear_params.dsc;</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;dsc_wait_disconnect_pending_clear_params.is_ungated)</div><div class='add'>+		return;</div><div class='add'>+	if (*params-&gt;dsc_wait_disconnect_pending_clear_params.is_ungated == false)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_wait_disconnect_pending_clear)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_wait_disconnect_pending_clear(dsc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dsc_disable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = params-&gt;dsc_disable_params.dsc;</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;dsc_disable_params.is_ungated)</div><div class='add'>+		return;</div><div class='add'>+	if (*params-&gt;dsc_disable_params.is_ungated == false)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;funcs-&gt;dsc_disable)</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_disable(dsc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dccg_set_ref_dscclk(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dccg *dccg = params-&gt;dccg_set_ref_dscclk_params.dccg;</div><div class='add'>+	int dsc_inst = params-&gt;dccg_set_ref_dscclk_params.dsc_inst;</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;dccg_set_ref_dscclk_params.is_ungated)</div><div class='add'>+		return;</div><div class='add'>+	if (*params-&gt;dccg_set_ref_dscclk_params.is_ungated == false)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (dccg &amp;&amp; dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+		dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, dsc_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_pg_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = params-&gt;dpp_pg_control_params.hws;</div><div class='add'>+	unsigned int dpp_inst = params-&gt;dpp_pg_control_params.dpp_inst;</div><div class='add'>+	bool power_on = params-&gt;dpp_pg_control_params.power_on;</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.dpp_pg_control)</div><div class='add'>+		hws-&gt;funcs.dpp_pg_control(hws, dpp_inst, power_on);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_pg_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = params-&gt;hubp_pg_control_params.hws;</div><div class='add'>+	unsigned int hubp_inst = params-&gt;hubp_pg_control_params.hubp_inst;</div><div class='add'>+	bool power_on = params-&gt;hubp_pg_control_params.power_on;</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.hubp_pg_control)</div><div class='add'>+		hws-&gt;funcs.hubp_pg_control(hws, hubp_inst, power_on);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_reset(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_reset_params.hubp;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_reset)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_reset(hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_reset(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp = params-&gt;dpp_reset_params.dpp;</div><div class='add'>+</div><div class='add'>+	if (dpp &amp;&amp; dpp-&gt;funcs-&gt;dpp_reset)</div><div class='add'>+		dpp-&gt;funcs-&gt;dpp_reset(dpp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_root_clock_control(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = params-&gt;dpp_root_clock_control_params.hws;</div><div class='add'>+	unsigned int dpp_inst = params-&gt;dpp_root_clock_control_params.dpp_inst;</div><div class='add'>+	bool clock_on = params-&gt;dpp_root_clock_control_params.clock_on;</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.dpp_root_clock_control)</div><div class='add'>+		hws-&gt;funcs.dpp_root_clock_control(hws, dpp_inst, clock_on);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dc_ip_request_cntl(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;dc_ip_request_cntl_params.dc;</div><div class='add'>+	bool enable = params-&gt;dc_ip_request_cntl_params.enable;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.dc_ip_request_cntl)</div><div class='add'>+		hws-&gt;funcs.dc_ip_request_cntl(dc, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dccg_update_dpp_dto(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dccg *dccg = params-&gt;dccg_update_dpp_dto_params.dccg;</div><div class='add'>+	int dpp_inst = params-&gt;dccg_update_dpp_dto_params.dpp_inst;</div><div class='add'>+	int dppclk_khz = params-&gt;dccg_update_dpp_dto_params.dppclk_khz;</div><div class='add'>+</div><div class='add'>+	if (dccg &amp;&amp; dccg-&gt;funcs-&gt;update_dpp_dto)</div><div class='add'>+		dccg-&gt;funcs-&gt;update_dpp_dto(dccg, dpp_inst, dppclk_khz);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_vtg_sel(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_vtg_sel_params.hubp;</div><div class='add'>+	uint32_t otg_inst = params-&gt;hubp_vtg_sel_params.otg_inst;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_vtg_sel)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_vtg_sel(hubp, otg_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup2(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_setup2_params.hubp;</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set *hubp_regs = params-&gt;hubp_setup2_params.hubp_regs;</div><div class='add'>+	union dml2_global_sync_programming *global_sync = params-&gt;hubp_setup2_params.global_sync;</div><div class='add'>+	struct dc_crtc_timing *timing = params-&gt;hubp_setup2_params.timing;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_setup2)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_setup2(hubp, hubp_regs, global_sync, timing);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_setup_params.hubp;</div><div class='add'>+	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params-&gt;hubp_setup_params.dlg_regs;</div><div class='add'>+	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params-&gt;hubp_setup_params.ttu_regs;</div><div class='add'>+	struct _vcs_dpi_display_rq_regs_st *rq_regs = params-&gt;hubp_setup_params.rq_regs;</div><div class='add'>+	struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest = params-&gt;hubp_setup_params.pipe_dest;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_setup)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_set_unbounded_requesting_params.hubp;</div><div class='add'>+	bool unbounded_req = params-&gt;hubp_set_unbounded_requesting_params.unbounded_req;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;set_unbounded_requesting)</div><div class='add'>+		hubp-&gt;funcs-&gt;set_unbounded_requesting(hubp, unbounded_req);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup_interdependent2(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_setup_interdependent2_params.hubp;</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set *hubp_regs = params-&gt;hubp_setup_interdependent2_params.hubp_regs;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_setup_interdependent2)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_setup_interdependent2(hubp, hubp_regs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup_interdependent(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_setup_interdependent_params.hubp;</div><div class='add'>+	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params-&gt;hubp_setup_interdependent_params.dlg_regs;</div><div class='add'>+	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params-&gt;hubp_setup_interdependent_params.ttu_regs;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_setup_interdependent)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_setup_interdependent(hubp, dlg_regs, ttu_regs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_set_cursor_matrix(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp = params-&gt;dpp_set_cursor_matrix_params.dpp;</div><div class='add'>+	enum dc_color_space color_space = params-&gt;dpp_set_cursor_matrix_params.color_space;</div><div class='add'>+	struct dc_csc_transform *cursor_csc_color_matrix = params-&gt;dpp_set_cursor_matrix_params.cursor_csc_color_matrix;</div><div class='add'>+</div><div class='add'>+	if (dpp &amp;&amp; dpp-&gt;funcs-&gt;set_cursor_matrix)</div><div class='add'>+		dpp-&gt;funcs-&gt;set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_update_mpcc(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;mpc_update_mpcc_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;mpc_update_mpcc_params.pipe_ctx;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.update_mpcc)</div><div class='add'>+		hws-&gt;funcs.update_mpcc(dc, pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_update_blending(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mpc *mpc = params-&gt;mpc_update_blending_params.mpc;</div><div class='add'>+	struct mpcc_blnd_cfg *blnd_cfg = &amp;params-&gt;mpc_update_blending_params.blnd_cfg;</div><div class='add'>+	int mpcc_id = params-&gt;mpc_update_blending_params.mpcc_id;</div><div class='add'>+</div><div class='add'>+	if (mpc &amp;&amp; mpc-&gt;funcs-&gt;update_blending)</div><div class='add'>+		mpc-&gt;funcs-&gt;update_blending(mpc, blnd_cfg, mpcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mpc *mpc = params-&gt;mpc_assert_idle_mpcc_params.mpc;</div><div class='add'>+	int mpcc_id = params-&gt;mpc_assert_idle_mpcc_params.mpcc_id;</div><div class='add'>+</div><div class='add'>+	if (mpc &amp;&amp; mpc-&gt;funcs-&gt;wait_for_idle)</div><div class='add'>+		mpc-&gt;funcs-&gt;wait_for_idle(mpc, mpcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_mpc_insert_plane(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct mpc *mpc = params-&gt;mpc_insert_plane_params.mpc;</div><div class='add'>+	struct mpc_tree *tree = params-&gt;mpc_insert_plane_params.mpc_tree_params;</div><div class='add'>+	struct mpcc_blnd_cfg *blnd_cfg = &amp;params-&gt;mpc_insert_plane_params.blnd_cfg;</div><div class='add'>+	struct mpcc_sm_cfg *sm_cfg = params-&gt;mpc_insert_plane_params.sm_cfg;</div><div class='add'>+	struct mpcc *insert_above_mpcc = params-&gt;mpc_insert_plane_params.insert_above_mpcc;</div><div class='add'>+	int mpcc_id = params-&gt;mpc_insert_plane_params.mpcc_id;</div><div class='add'>+	int dpp_id = params-&gt;mpc_insert_plane_params.dpp_id;</div><div class='add'>+</div><div class='add'>+	if (mpc &amp;&amp; mpc-&gt;funcs-&gt;insert_plane)</div><div class='add'>+		mpc-&gt;funcs-&gt;insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc,</div><div class='add'>+			dpp_id, mpcc_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_dpp_set_scaler(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp = params-&gt;dpp_set_scaler_params.dpp;</div><div class='add'>+	const struct scaler_data *scl_data = params-&gt;dpp_set_scaler_params.scl_data;</div><div class='add'>+</div><div class='add'>+	if (dpp &amp;&amp; dpp-&gt;funcs-&gt;dpp_set_scaler)</div><div class='add'>+		dpp-&gt;funcs-&gt;dpp_set_scaler(dpp, scl_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_mem_program_viewport(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_mem_program_viewport_params.hubp;</div><div class='add'>+	const struct rect *viewport = params-&gt;hubp_mem_program_viewport_params.viewport;</div><div class='add'>+	const struct rect *viewport_c = params-&gt;hubp_mem_program_viewport_params.viewport_c;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;mem_program_viewport)</div><div class='add'>+		hubp-&gt;funcs-&gt;mem_program_viewport(hubp, viewport, viewport_c);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_abort_cursor_offload_update(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;abort_cursor_offload_update_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;abort_cursor_offload_update_params.pipe_ctx;</div><div class='add'>+</div><div class='add'>+	if (dc &amp;&amp; dc-&gt;hwss.abort_cursor_offload_update)</div><div class='add'>+		dc-&gt;hwss.abort_cursor_offload_update(dc, pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_cursor_attribute(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;set_cursor_attribute_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;set_cursor_attribute_params.pipe_ctx;</div><div class='add'>+</div><div class='add'>+	if (dc &amp;&amp; dc-&gt;hwss.set_cursor_attribute)</div><div class='add'>+		dc-&gt;hwss.set_cursor_attribute(pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_cursor_position(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;set_cursor_position_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;set_cursor_position_params.pipe_ctx;</div><div class='add'>+</div><div class='add'>+	if (dc &amp;&amp; dc-&gt;hwss.set_cursor_position)</div><div class='add'>+		dc-&gt;hwss.set_cursor_position(pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_set_cursor_sdr_white_level(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;set_cursor_sdr_white_level_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;set_cursor_sdr_white_level_params.pipe_ctx;</div><div class='add'>+</div><div class='add'>+	if (dc &amp;&amp; dc-&gt;hwss.set_cursor_sdr_white_level)</div><div class='add'>+		dc-&gt;hwss.set_cursor_sdr_white_level(pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_program_output_csc(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;program_output_csc_params.dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = params-&gt;program_output_csc_params.pipe_ctx;</div><div class='add'>+	enum dc_color_space colorspace = params-&gt;program_output_csc_params.colorspace;</div><div class='add'>+	uint16_t *matrix = params-&gt;program_output_csc_params.matrix;</div><div class='add'>+	int opp_id = params-&gt;program_output_csc_params.opp_id;</div><div class='add'>+</div><div class='add'>+	if (dc &amp;&amp; dc-&gt;hwss.program_output_csc)</div><div class='add'>+		dc-&gt;hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_blank(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;hubp_set_blank_params.hubp;</div><div class='add'>+	bool blank = params-&gt;hubp_set_blank_params.blank;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;set_blank)</div><div class='add'>+		hubp-&gt;funcs-&gt;set_blank(hubp, blank);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_phantom_hubp_post_enable(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = params-&gt;phantom_hubp_post_enable_params.hubp;</div><div class='add'>+</div><div class='add'>+	if (hubp &amp;&amp; hubp-&gt;funcs-&gt;phantom_hubp_post_enable)</div><div class='add'>+		hubp-&gt;funcs-&gt;phantom_hubp_post_enable(hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dccg *dccg, int inst, int num_slices_h)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DCCG_SET_DTO_DSCCLK;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_set_dto_dscclk_params.inst = inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DSC_CALCULATE_AND_SET_CONFIG;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_calculate_and_set_config_params.enable = enable;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_REMOVE_MPCC;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_remove_mpcc_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp, int mpcc_inst, bool pending)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_DISCONNECT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_disconnect_params.hubp = hubp;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DSC_ENABLE_WITH_OPP;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, struct dsc_optc_config *dsc_optc_cfg, bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_SET_DSC_CONFIG;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_dsc_config_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_dsc_config_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state,</div><div class='add'>+		struct display_stream_compressor *dsc)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DSC_DISCONNECT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_disconnect_params.dsc = dsc;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, bool optimized_required)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DC_SET_OPTIMIZED_REQUIRED;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dc_set_optimized_required_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = ABM_SET_IMMEDIATE_DISABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_abm_immediate_disable_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		enum controller_dp_test_pattern test_pattern,</div><div class='add'>+		enum controller_dp_color_space color_space,</div><div class='add'>+		enum dc_color_depth color_depth,</div><div class='add'>+		struct tg_color solid_color,</div><div class='add'>+		bool use_solid_color,</div><div class='add'>+		int width,</div><div class='add'>+		int height,</div><div class='add'>+		int offset)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.width = width;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.height = height;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_set_disp_pattern_generator_params.offset = offset;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC update blending to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		struct mpcc_blnd_cfg blnd_cfg,</div><div class='add'>+		int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_UPDATE_BLENDING;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_update_blending_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC insert plane to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		struct mpc_tree *mpc_tree_params,</div><div class='add'>+		struct mpcc_blnd_cfg blnd_cfg,</div><div class='add'>+		struct mpcc_sm_cfg *sm_cfg,</div><div class='add'>+		struct mpcc *insert_above_mpcc,</div><div class='add'>+		int dpp_id,</div><div class='add'>+		int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_INSERT_PLANE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add MPC assert idle MPCC to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_ASSERT_IDLE_MPCC;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper function to add HUBP set blank to block sequence</div><div class='add'>+ */</div><div class='add'>+void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool blank)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SET_BLANK;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_blank_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_blank_params.blank = blank;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		bool use_default_params,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_bit_depth_reduction_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DC_IP_REQUEST_CNTL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dc_ip_request_cntl_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dc_ip_request_cntl_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dwbc_update(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dwbc *dwb,</div><div class='add'>+		struct dc_dwb_params *dwb_params)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DWBC_UPDATE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dwbc_update_params.dwb = dwb;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dwbc_update_params.dwb_params = dwb_params;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb,</div><div class='add'>+		struct mcif_buf_params *mcif_buf_params,</div><div class='add'>+		unsigned int dest_height)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MCIF_WB_CONFIG_BUF;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb,</div><div class='add'>+		struct mcif_arb_params *mcif_arb_params)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MCIF_WB_CONFIG_ARB;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MCIF_WB_ENABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MCIF_WB_DISABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int dwb_id,</div><div class='add'>+		int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_SET_DWB_MUX;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_set_dwb_mux_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		unsigned int dwb_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = MPC_DISABLE_DWB_MUX;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dwbc_enable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dwbc *dwb,</div><div class='add'>+		struct dc_dwb_params *dwb_params)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DWBC_ENABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dwbc_enable_params.dwb = dwb;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dwbc_enable_params.dwb_params = dwb_params;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dwbc_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dwbc *dwb)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DWBC_DISABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dwbc_disable_params.dwb = dwb;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		struct gsl_params gsl)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_SET_GSL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_gsl_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_gsl_params.gsl = gsl;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		int group_idx,</div><div class='add'>+		uint32_t gsl_ready_signal)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_SET_GSL_SOURCE_SELECT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_gsl_source_select_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		uint32_t mall_sel,</div><div class='add'>+		bool cache_cursor)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_UPDATE_MALL_SEL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_update_mall_sel_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SET_BLANK_EN;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_blank_en_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_blank_en_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool disable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_DISABLE_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_disable_control_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_disable_control_params.disable = disable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset),</div><div class='add'>+		bool reset)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBBUB_SOFT_RESET;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_soft_reset_params.hubbub = hubbub;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_soft_reset_params.reset = reset;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_CLK_CNTL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_clk_cntl_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_clk_cntl_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		bool dppclk_div,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_DPPCLK_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_dppclk_control_params.dpp = dpp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_dppclk_control_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DISABLE_PHANTOM_CRTC;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.disable_phantom_crtc_params.tg = tg;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		int dsc_inst,</div><div class='add'>+		bool is_ungated)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DSC_PG_STATUS;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_pg_status_params.hws = hws;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_pg_status_params.is_ungated = is_ungated;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state,</div><div class='add'>+		struct display_stream_compressor *dsc,</div><div class='add'>+		bool *is_ungated)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct display_stream_compressor *dsc,</div><div class='add'>+		bool *is_ungated)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DSC_DISABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_disable_params.dsc = dsc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dsc_disable_params.is_ungated = is_ungated;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int dsc_inst,</div><div class='add'>+		bool *is_ungated)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DCCG_SET_REF_DSCCLK;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int dpp_inst,</div><div class='add'>+		bool clock_on)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_ROOT_CLOCK_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_root_clock_control_params.hws = hws;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_root_clock_control_params.clock_on = clock_on;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int dpp_inst,</div><div class='add'>+		bool power_on)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_PG_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_pg_control_params.hws = hws;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_pg_control_params.power_on = power_on;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int hubp_inst,</div><div class='add'>+		bool power_on)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PG_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_pg_control_params.hws = hws;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_pg_control_params.power_on = power_on;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_init(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_INIT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_init_params.hubp = hubp;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_reset(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_RESET;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_reset_params.hubp = hubp;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_reset(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_RESET;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_reset_params.dpp = dpp;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = OPP_PIPE_CLOCK_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_pipe_clock_control_params.opp = opp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.opp_pipe_clock_control_params.enable = enable;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		uint64_t sys_default,</div><div class='add'>+		uint64_t sys_low,</div><div class='add'>+		uint64_t sys_high)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SET_FLIP_INT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_flip_int_params.hubp = hubp;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int dpp_inst,</div><div class='add'>+		int dppclk_khz)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DCCG_UPDATE_DPP_DTO;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_update_dpp_dto_params.dccg = dccg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		uint32_t otg_inst)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_VTG_SEL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_vtg_sel_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup2(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *hubp_regs,</div><div class='add'>+		union dml2_global_sync_programming *global_sync,</div><div class='add'>+		struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SETUP2;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup2_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup2_params.global_sync = global_sync;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup2_params.timing = timing;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,</div><div class='add'>+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs,</div><div class='add'>+		struct _vcs_dpi_display_rq_regs_st *rq_regs,</div><div class='add'>+		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SETUP;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_params.dlg_regs = dlg_regs;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_params.ttu_regs = ttu_regs;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_params.rq_regs = rq_regs;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_params.pipe_dest = pipe_dest;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool unbounded_req)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *hubp_regs)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SETUP_INTERDEPENDENT2;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_interdependent2_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,</div><div class='add'>+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_SETUP_INTERDEPENDENT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_interdependent_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='add'>+		struct plane_size plane_size,</div><div class='add'>+		enum dc_rotation_angle rotation,</div><div class='add'>+		struct dc_plane_dcc_param *dcc,</div><div class='add'>+		bool horizontal_mirror,</div><div class='add'>+		int compat_level)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.format = format;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.tiling_info = tiling_info;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.plane_size = plane_size;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.rotation = rotation;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.dcc = dcc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_surface_config_params.compat_level = compat_level;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_SETUP_DPP;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		enum dc_color_space color_space,</div><div class='add'>+		struct dc_csc_transform *cursor_csc_color_matrix)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_SET_CURSOR_MATRIX;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = DPP_SET_SCALER;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_scaler_params.dpp = dpp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.dpp_set_scaler_params.scl_data = scl_data;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		const struct rect *viewport,</div><div class='add'>+		const struct rect *viewport_c)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_mem_program_viewport_params.hubp = hubp;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_mem_program_viewport_params.viewport = viewport;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.abort_cursor_offload_update_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = SET_CURSOR_ATTRIBUTE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_cursor_attribute_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = SET_CURSOR_POSITION;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_cursor_position_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_cursor_sdr_white_level_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_program_output_csc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		enum dc_color_space colorspace,</div><div class='add'>+		uint16_t *matrix,</div><div class='add'>+		int opp_id)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = PROGRAM_OUTPUT_CSC;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_output_csc_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_output_csc_params.colorspace = colorspace;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_output_csc_params.matrix = matrix;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.program_output_csc_params.opp_id = opp_id;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = PHANTOM_HUBP_POST_ENABLE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.phantom_hubp_post_enable_params.hubp = hubp;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_update_force_pstate(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = UPDATE_FORCE_PSTATE;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_force_pstate_params.dc = dc;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.update_force_pstate_params.context = context;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		bool allow,</div><div class='add'>+		bool *disallow_self_refresh_applied)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		unsigned int *frame_count)</div><div class='add'>+{</div><div class='add'>+	if (*seq_state-&gt;num_steps &lt; MAX_HWSS_BLOCK_SEQUENCE_SIZE) {</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].func = TG_GET_FRAME_COUNT;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_get_frame_count_params.tg = tg;</div><div class='add'>+		seq_state-&gt;steps[*seq_state-&gt;num_steps].params.tg_get_frame_count_params.frame_count = frame_count;</div><div class='add'>+		(*seq_state-&gt;num_steps)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c<br/>index be5a6d008b29..deb23d20bca6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> #include "resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER dc-&gt;ctx-&gt;logger</div><div class='ctx'> </div><div class='hunk'>@@ -44,20 +44,8 @@ static bool is_dig_link_enc_stream(struct dc_stream_state *stream)</div><div class='ctx'> 			 * yet match.</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (link_enc &amp;&amp; ((uint32_t)stream-&gt;link-&gt;connector_signal &amp; link_enc-&gt;output_signals)) {</div><div class='del'>-				if (dc_is_dp_signal(stream-&gt;signal)) {</div><div class='del'>-					/* DIGs do not support DP2.0 streams with 128b/132b encoding. */</div><div class='del'>-					struct dc_link_settings link_settings = {0};</div><div class='del'>-</div><div class='del'>-					stream-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_decide_link_settings(stream, &amp;link_settings);</div><div class='del'>-					if ((link_settings.link_rate &gt;= LINK_RATE_LOW) &amp;&amp;</div><div class='del'>-							link_settings.link_rate &lt;= LINK_RATE_HIGH3) {</div><div class='del'>-						is_dig_stream = true;</div><div class='del'>-						break;</div><div class='del'>-					}</div><div class='del'>-				} else {</div><div class='del'>-					is_dig_stream = true;</div><div class='del'>-					break;</div><div class='del'>-				}</div><div class='add'>+				is_dig_stream = true;</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -248,6 +236,8 @@ static struct link_encoder *get_link_enc_used_by_link(</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		struct link_enc_assignment assignment = state-&gt;res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];</div><div class='add'>+		if (assignment.eng_id == ENGINE_ID_UNKNOWN)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (assignment.valid == true &amp;&amp; are_ep_ids_equal(&amp;assignment.ep_id, &amp;ep_id))</div><div class='ctx'> 			link_enc = link-&gt;dc-&gt;res_pool-&gt;link_encoders[assignment.eng_id - ENGINE_ID_DIGA];</div><div class='hunk'>@@ -517,6 +507,8 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		struct link_enc_assignment assignment = get_assignment(dc, i);</div><div class='add'>+		if (assignment.eng_id == ENGINE_ID_UNKNOWN)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (assignment.valid == true &amp;&amp; are_ep_ids_equal(&amp;assignment.ep_id, &amp;ep_id)) {</div><div class='ctx'> 			link_enc = link-&gt;dc-&gt;res_pool-&gt;link_encoders[assignment.eng_id - ENGINE_ID_DIGA];</div><div class='hunk'>@@ -530,17 +522,17 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(</div><div class='ctx'> struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct link_encoder *link_enc = NULL;</div><div class='del'>-	enum engine_id encs_assigned[MAX_DIG_LINK_ENCODERS];</div><div class='add'>+	enum engine_id encs_assigned[MAX_LINK_ENCODERS];</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; MAX_DIG_LINK_ENCODERS; i++)</div><div class='add'>+	for (i = 0; i &lt; MAX_LINK_ENCODERS; i++)</div><div class='ctx'> 		encs_assigned[i] = ENGINE_ID_UNKNOWN;</div><div class='ctx'> </div><div class='ctx'> 	/* Add assigned encoders to list. */</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='ctx'> 		struct link_enc_assignment assignment = get_assignment(dc, i);</div><div class='ctx'> </div><div class='del'>-		if (assignment.valid)</div><div class='add'>+		if (assignment.valid &amp;&amp; assignment.eng_id != ENGINE_ID_UNKNOWN)</div><div class='ctx'> 			encs_assigned[assignment.eng_id - ENGINE_ID_DIGA] = assignment.eng_id;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -555,17 +547,6 @@ struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc)</div><div class='ctx'> 	return link_enc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		const struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	struct link_encoder *link_enc;</div><div class='del'>-</div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc_used_by_link(dc, stream-&gt;link);</div><div class='del'>-</div><div class='del'>-	return link_enc;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct link_encoder *link_enc_cfg_get_link_enc(</div><div class='ctx'> 		const struct dc_link *link)</div><div class='ctx'> {</div><div class='hunk'>@@ -602,6 +583,9 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream_current(</div><div class='ctx'> 		struct link_enc_assignment assignment =</div><div class='ctx'> 			dc-&gt;current_state-&gt;res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];</div><div class='ctx'> </div><div class='add'>+		if (assignment.eng_id == ENGINE_ID_UNKNOWN)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		if (assignment.valid == true &amp;&amp; are_ep_ids_equal(&amp;assignment.ep_id, &amp;ep_id)) {</div><div class='ctx'> 			link_enc = stream-&gt;link-&gt;dc-&gt;res_pool-&gt;link_encoders[assignment.eng_id - ENGINE_ID_DIGA];</div><div class='ctx'> 			break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c<br/>index c6c35037bdb8..9acd30019717 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c</a></div><div class='hunk'>@@ -33,10 +33,14 @@</div><div class='ctx'>  * dc.h with detail interface documentation, then add function implementation</div><div class='ctx'>  * in this file which calls link functions.</div><div class='ctx'>  */</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='add'>+</div><div class='ctx'> struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)</div><div class='ctx'> {</div><div class='add'>+	if (link_index &gt;= MAX_LINKS)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	return dc-&gt;links[link_index];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -122,6 +126,14 @@ uint32_t dc_link_bandwidth_kbps(</div><div class='ctx'> 	return link-&gt;dc-&gt;link_srv-&gt;dp_link_bandwidth_kbps(link, link_settings);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+uint32_t dc_link_required_hblank_size_bytes(</div><div class='add'>+	const struct dc_link *link,</div><div class='add'>+	struct dp_audio_bandwidth_params *audio_params)</div><div class='add'>+{</div><div class='add'>+	return link-&gt;dc-&gt;link_srv-&gt;dp_required_hblank_size_bytes(link,</div><div class='add'>+			audio_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)</div><div class='ctx'> {</div><div class='ctx'> 	dc-&gt;link_srv-&gt;get_cur_res_map(dc, map);</div><div class='hunk'>@@ -139,6 +151,12 @@ bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	return link-&gt;dc-&gt;link_srv-&gt;update_dsc_config(pipe_ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+struct ddc_service *</div><div class='add'>+dc_get_oem_i2c_device(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	return dc-&gt;res_pool-&gt;oem_device;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dc_is_oem_i2c_device_present(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	size_t slave_address)</div><div class='hunk'>@@ -353,15 +371,10 @@ bool dc_link_should_enable_fec(const struct dc_link *link)</div><div class='ctx'> 	return link-&gt;dc-&gt;link_srv-&gt;dp_should_enable_fec(link);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(</div><div class='add'>+void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(</div><div class='ctx'> 		struct dc_link *link, int peak_bw)</div><div class='ctx'> {</div><div class='del'>-	return link-&gt;dc-&gt;link_srv-&gt;dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result)</div><div class='del'>-{</div><div class='del'>-	link-&gt;dc-&gt;link_srv-&gt;dpia_handle_bw_alloc_response(link, bw, result);</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_link_check_link_loss_status(</div><div class='hunk'>@@ -427,11 +440,10 @@ bool dc_link_get_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_link_set_backlight_level(const struct dc_link *link,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp)</div><div class='add'>+		struct set_backlight_level_params *backlight_level_params)</div><div class='ctx'> {</div><div class='ctx'> 	return link-&gt;dc-&gt;link_srv-&gt;edp_set_backlight_level(link,</div><div class='del'>-			backlight_pwm_u16_16, frame_ramp);</div><div class='add'>+			backlight_level_params);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_link_set_backlight_level_nits(struct dc_link *link,</div><div class='hunk'>@@ -504,7 +516,15 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)</div><div class='ctx'> 	link-&gt;dc-&gt;link_srv-&gt;enable_hpd_filter(link, enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count)</div><div class='add'>+enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)</div><div class='ctx'> {</div><div class='del'>-	return dc-&gt;link_srv-&gt;validate_dpia_bandwidth(streams, count);</div><div class='add'>+	return dc-&gt;link_srv-&gt;validate_dp_tunnel_bandwidth(dc, new_ctx);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dc_link_get_alpm_support(struct dc_link *link,</div><div class='add'>+	bool *auxless_support,</div><div class='add'>+	bool *auxwake_support)</div><div class='add'>+{</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;edp_get_alpm_support(link, auxless_support, auxwake_support);</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c<br/>index ec4bf9432bdb..848c267ef11e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_resource.c</a></div><div class='hunk'>@@ -40,9 +40,11 @@</div><div class='ctx'> #include "virtual/virtual_stream_encoder.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='add'>+#include "dc_stream_priv.h"</div><div class='add'>+</div><div class='ctx'> #include "virtual/virtual_link_hwss.h"</div><div class='ctx'> #include "link/hwss/link_hwss_dio.h"</div><div class='ctx'> #include "link/hwss/link_hwss_dpia.h"</div><div class='hunk'>@@ -74,6 +76,11 @@</div><div class='ctx'> #include "dcn321/dcn321_resource.h"</div><div class='ctx'> #include "dcn35/dcn35_resource.h"</div><div class='ctx'> #include "dcn351/dcn351_resource.h"</div><div class='add'>+#include "dcn36/dcn36_resource.h"</div><div class='add'>+#include "dcn401/dcn401_resource.h"</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+#include "dc_spl_translate.h"</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> #define VISUAL_CONFIRM_BASE_DEFAULT 3</div><div class='ctx'> #define VISUAL_CONFIRM_BASE_MIN 1</div><div class='hunk'>@@ -88,11 +95,44 @@</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dc-&gt;ctx-&gt;logger</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='del'>-</div><div class='del'>-#include "dml2/dml2_wrapper.h"</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> #define UNABLE_TO_SPLIT -1</div><div class='ctx'> </div><div class='add'>+static void capture_pipe_topology_data(struct dc *dc, int plane_idx, int slice_idx, int stream_idx,</div><div class='add'>+									   int dpp_inst, int opp_inst, int tg_inst, bool is_phantom_pipe)</div><div class='add'>+{</div><div class='add'>+	struct pipe_topology_snapshot *current_snapshot = &amp;dc-&gt;debug_data.topology_history.snapshots[dc-&gt;debug_data.topology_history.current_snapshot_index];</div><div class='add'>+</div><div class='add'>+	if (current_snapshot-&gt;line_count &gt;= MAX_PIPES)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].is_phantom_pipe = is_phantom_pipe;</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].plane_idx = plane_idx;</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].slice_idx = slice_idx;</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].stream_idx = stream_idx;</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].dpp_inst = dpp_inst;</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].opp_inst = opp_inst;</div><div class='add'>+	current_snapshot-&gt;pipe_log_lines[current_snapshot-&gt;line_count].tg_inst = tg_inst;</div><div class='add'>+</div><div class='add'>+	current_snapshot-&gt;line_count++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void start_new_topology_snapshot(struct dc *dc, struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	// Move to next snapshot slot (circular buffer)</div><div class='add'>+	dc-&gt;debug_data.topology_history.current_snapshot_index = (dc-&gt;debug_data.topology_history.current_snapshot_index + 1) % MAX_TOPOLOGY_SNAPSHOTS;</div><div class='add'>+</div><div class='add'>+	// Clear the new snapshot</div><div class='add'>+	struct pipe_topology_snapshot *current_snapshot = &amp;dc-&gt;debug_data.topology_history.snapshots[dc-&gt;debug_data.topology_history.current_snapshot_index];</div><div class='add'>+	memset(current_snapshot, 0, sizeof(*current_snapshot));</div><div class='add'>+</div><div class='add'>+	// Set metadata</div><div class='add'>+	current_snapshot-&gt;timestamp_us = dm_get_timestamp(dc-&gt;ctx);</div><div class='add'>+	current_snapshot-&gt;stream_count = state-&gt;stream_count;</div><div class='add'>+	current_snapshot-&gt;phantom_stream_count = state-&gt;phantom_stream_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)</div><div class='ctx'> {</div><div class='ctx'> 	enum dce_version dc_version = DCE_VERSION_UNKNOWN;</div><div class='hunk'>@@ -158,7 +198,13 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)</div><div class='ctx'> </div><div class='ctx'> 	case FAMILY_NV:</div><div class='ctx'> 		dc_version = DCN_VERSION_2_0;</div><div class='del'>-		if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {</div><div class='add'>+		if (asic_id.chip_id == DEVICE_ID_NV_13FE ||</div><div class='add'>+		    asic_id.chip_id == DEVICE_ID_NV_143F ||</div><div class='add'>+		    asic_id.chip_id == DEVICE_ID_NV_13F9 ||</div><div class='add'>+		    asic_id.chip_id == DEVICE_ID_NV_13FA ||</div><div class='add'>+		    asic_id.chip_id == DEVICE_ID_NV_13FB ||</div><div class='add'>+		    asic_id.chip_id == DEVICE_ID_NV_13FC ||</div><div class='add'>+		    asic_id.chip_id == DEVICE_ID_NV_13DB) {</div><div class='ctx'> 			dc_version = DCN_VERSION_2_01;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -198,6 +244,13 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)</div><div class='ctx'> 		dc_version = DCN_VERSION_3_5;</div><div class='ctx'> 		if (ASICREV_IS_GC_11_0_4(asic_id.hw_internal_rev))</div><div class='ctx'> 			dc_version = DCN_VERSION_3_51;</div><div class='add'>+		if (ASICREV_IS_DCN36(asic_id.hw_internal_rev))</div><div class='add'>+			dc_version = DCN_VERSION_3_6;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_FAMILY_GC_12_0_0:</div><div class='add'>+		if (ASICREV_IS_GC_12_0_1_A0(asic_id.hw_internal_rev) ||</div><div class='add'>+			ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev))</div><div class='add'>+			dc_version = DCN_VERSION_4_01;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dc_version = DCE_VERSION_UNKNOWN;</div><div class='hunk'>@@ -309,6 +362,12 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,</div><div class='ctx'> 	case DCN_VERSION_3_51:</div><div class='ctx'> 		res_pool = dcn351_create_resource_pool(init_data, dc);</div><div class='ctx'> 		break;</div><div class='add'>+	case DCN_VERSION_3_6:</div><div class='add'>+		res_pool = dcn36_create_resource_pool(init_data, dc);</div><div class='add'>+		break;</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		res_pool = dcn401_create_resource_pool(init_data, dc);</div><div class='add'>+		break;</div><div class='ctx'> #endif /* CONFIG_DRM_AMD_DC_FP */</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -328,11 +387,6 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,</div><div class='ctx'> 				res_pool-&gt;ref_clocks.xtalin_clock_inKhz;</div><div class='ctx'> 			res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz =</div><div class='ctx'> 				res_pool-&gt;ref_clocks.xtalin_clock_inKhz;</div><div class='del'>-			if (dc-&gt;debug.using_dml2)</div><div class='del'>-				if (res_pool-&gt;hubbub &amp;&amp; res_pool-&gt;hubbub-&gt;funcs-&gt;get_dchub_ref_freq)</div><div class='del'>-					res_pool-&gt;hubbub-&gt;funcs-&gt;get_dchub_ref_freq(res_pool-&gt;hubbub,</div><div class='del'>-										    res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz,</div><div class='del'>-										    &amp;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz);</div><div class='ctx'> 		} else</div><div class='ctx'> 			ASSERT_CRITICAL(false);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -340,7 +394,7 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,</div><div class='ctx'> 	return res_pool;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_destroy_resource_pool(struct dc  *dc)</div><div class='add'>+void dc_destroy_resource_pool(struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc) {</div><div class='ctx'> 		if (dc-&gt;res_pool)</div><div class='hunk'>@@ -426,6 +480,14 @@ bool resource_construct(</div><div class='ctx'> 				DC_ERR("DC: failed to create stream_encoder!\n");</div><div class='ctx'> 			pool-&gt;stream_enc_count++;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; caps-&gt;num_analog_stream_encoder; i++) {</div><div class='add'>+			pool-&gt;stream_enc[caps-&gt;num_stream_encoder + i] =</div><div class='add'>+				create_funcs-&gt;create_stream_encoder(ENGINE_ID_DACA + i, ctx);</div><div class='add'>+			if (pool-&gt;stream_enc[caps-&gt;num_stream_encoder + i] == NULL)</div><div class='add'>+				DC_ERR("DC: failed to create analog stream_encoder %d!\n", i);</div><div class='add'>+			pool-&gt;stream_enc_count++;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pool-&gt;hpo_dp_stream_enc_count = 0;</div><div class='hunk'>@@ -756,25 +818,6 @@ static inline void get_vp_scan_direction(</div><div class='ctx'> 		*flip_horz_scan_dir = !*flip_horz_scan_dir;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * This is a preliminary vp size calculation to allow us to check taps support.</div><div class='del'>- * The result is completely overridden afterwards.</div><div class='del'>- */</div><div class='del'>-static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)</div><div class='del'>-{</div><div class='del'>-	struct scaler_data *data = &amp;pipe_ctx-&gt;plane_res.scl_data;</div><div class='del'>-</div><div class='del'>-	data-&gt;viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data-&gt;ratios.horz, data-&gt;recout.width));</div><div class='del'>-	data-&gt;viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data-&gt;ratios.vert, data-&gt;recout.height));</div><div class='del'>-	data-&gt;viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data-&gt;ratios.horz_c, data-&gt;recout.width));</div><div class='del'>-	data-&gt;viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data-&gt;ratios.vert_c, data-&gt;recout.height));</div><div class='del'>-	if (pipe_ctx-&gt;plane_state-&gt;rotation == ROTATION_ANGLE_90 ||</div><div class='del'>-			pipe_ctx-&gt;plane_state-&gt;rotation == ROTATION_ANGLE_270) {</div><div class='del'>-		swap(data-&gt;viewport.width, data-&gt;viewport.height);</div><div class='del'>-		swap(data-&gt;viewport_c.width, data-&gt;viewport_c.height);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct rect intersect_rec(const struct rect *r0, const struct rect *r1)</div><div class='ctx'> {</div><div class='ctx'> 	struct rect rec;</div><div class='hunk'>@@ -805,32 +848,6 @@ static struct rect shift_rec(const struct rect *rec_in, int x, int y)</div><div class='ctx'> 	return rec_out;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ctx)</div><div class='del'>-{</div><div class='del'>-	const struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='del'>-	int odm_slice_count = resource_get_odm_slice_count(pipe_ctx);</div><div class='del'>-	int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);</div><div class='del'>-	bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;</div><div class='del'>-	int h_active = stream-&gt;timing.h_addressable +</div><div class='del'>-			stream-&gt;timing.h_border_left +</div><div class='del'>-			stream-&gt;timing.h_border_right;</div><div class='del'>-	int odm_slice_width = h_active / odm_slice_count;</div><div class='del'>-	struct rect odm_rec;</div><div class='del'>-</div><div class='del'>-	odm_rec.x = odm_slice_width * odm_slice_idx;</div><div class='del'>-	odm_rec.width = is_last_odm_slice ?</div><div class='del'>-			/* last slice width is the reminder of h_active */</div><div class='del'>-			h_active - odm_slice_width * (odm_slice_count - 1) :</div><div class='del'>-			/* odm slice width is the floor of h_active / count */</div><div class='del'>-			odm_slice_width;</div><div class='del'>-	odm_rec.y = 0;</div><div class='del'>-	odm_rec.height = stream-&gt;timing.v_addressable +</div><div class='del'>-			stream-&gt;timing.v_border_bottom +</div><div class='del'>-			stream-&gt;timing.v_border_top;</div><div class='del'>-</div><div class='del'>-	return odm_rec;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct rect calculate_plane_rec_in_timing_active(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		const struct rect *rec_in)</div><div class='hunk'>@@ -900,21 +917,21 @@ static struct rect calculate_plane_rec_in_timing_active(</div><div class='ctx'> 	struct rect rec_out = {0};</div><div class='ctx'> 	struct fixed31_32 temp;</div><div class='ctx'> </div><div class='del'>-	temp = dc_fixpt_from_fraction(rec_in-&gt;x * stream-&gt;dst.width,</div><div class='add'>+	temp = dc_fixpt_from_fraction(rec_in-&gt;x * (long long)stream-&gt;dst.width,</div><div class='ctx'> 			stream-&gt;src.width);</div><div class='ctx'> 	rec_out.x = stream-&gt;dst.x + dc_fixpt_round(temp);</div><div class='ctx'> </div><div class='ctx'> 	temp = dc_fixpt_from_fraction(</div><div class='del'>-			(rec_in-&gt;x + rec_in-&gt;width) * stream-&gt;dst.width,</div><div class='add'>+			(rec_in-&gt;x + rec_in-&gt;width) * (long long)stream-&gt;dst.width,</div><div class='ctx'> 			stream-&gt;src.width);</div><div class='ctx'> 	rec_out.width = stream-&gt;dst.x + dc_fixpt_round(temp) - rec_out.x;</div><div class='ctx'> </div><div class='del'>-	temp = dc_fixpt_from_fraction(rec_in-&gt;y * stream-&gt;dst.height,</div><div class='add'>+	temp = dc_fixpt_from_fraction(rec_in-&gt;y * (long long)stream-&gt;dst.height,</div><div class='ctx'> 			stream-&gt;src.height);</div><div class='ctx'> 	rec_out.y = stream-&gt;dst.y + dc_fixpt_round(temp);</div><div class='ctx'> </div><div class='ctx'> 	temp = dc_fixpt_from_fraction(</div><div class='del'>-			(rec_in-&gt;y + rec_in-&gt;height) * stream-&gt;dst.height,</div><div class='add'>+			(rec_in-&gt;y + rec_in-&gt;height) * (long long)stream-&gt;dst.height,</div><div class='ctx'> 			stream-&gt;src.height);</div><div class='ctx'> 	rec_out.height = stream-&gt;dst.y + dc_fixpt_round(temp) - rec_out.y;</div><div class='ctx'> </div><div class='hunk'>@@ -939,6 +956,9 @@ static struct rect calculate_mpc_slice_in_timing_active(</div><div class='ctx'> 			stream-&gt;view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE ||</div><div class='ctx'> 			mpc_rec.width % 2 == 0);</div><div class='ctx'> </div><div class='add'>+	if (stream-&gt;view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)</div><div class='add'>+		mpc_rec.x -= (mpc_rec.width * mpc_slice_idx);</div><div class='add'>+</div><div class='ctx'> 	/* extra pixels in the division remainder need to go to pipes after</div><div class='ctx'> 	 * the extra pixel index minus one(epimo) defined here as:</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -954,24 +974,44 @@ static struct rect calculate_mpc_slice_in_timing_active(</div><div class='ctx'> 	return mpc_rec;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void adjust_recout_for_visual_confirm(struct rect *recout,</div><div class='del'>-		struct pipe_ctx *pipe_ctx)</div><div class='add'>+static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx,</div><div class='add'>+	int *base_offset, int *dpp_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='del'>-	int dpp_offset, base_offset;</div><div class='add'>+	*base_offset = 0;</div><div class='add'>+	*dpp_offset = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx-&gt;plane_res.dpp)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	dpp_offset = pipe_ctx-&gt;stream-&gt;timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;</div><div class='del'>-	dpp_offset *= pipe_ctx-&gt;plane_res.dpp-&gt;inst;</div><div class='add'>+	*dpp_offset = pipe_ctx-&gt;stream-&gt;timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;</div><div class='add'>+	*dpp_offset *= pipe_ctx-&gt;plane_res.dpp-&gt;inst;</div><div class='ctx'> </div><div class='ctx'> 	if ((dc-&gt;debug.visual_confirm_rect_height &gt;= VISUAL_CONFIRM_BASE_MIN) &amp;&amp;</div><div class='ctx'> 			dc-&gt;debug.visual_confirm_rect_height &lt;= VISUAL_CONFIRM_BASE_MAX)</div><div class='del'>-		base_offset = dc-&gt;debug.visual_confirm_rect_height;</div><div class='add'>+		*base_offset = dc-&gt;debug.visual_confirm_rect_height;</div><div class='ctx'> 	else</div><div class='del'>-		base_offset = VISUAL_CONFIRM_BASE_DEFAULT;</div><div class='add'>+		*base_offset = VISUAL_CONFIRM_BASE_DEFAULT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reverse_adjust_recout_for_visual_confirm(struct rect *recout,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	int dpp_offset, base_offset;</div><div class='add'>+</div><div class='add'>+	calculate_adjust_recout_for_visual_confirm(pipe_ctx, &amp;base_offset,</div><div class='add'>+		&amp;dpp_offset);</div><div class='add'>+	recout-&gt;height += base_offset;</div><div class='add'>+	recout-&gt;height += dpp_offset;</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static void adjust_recout_for_visual_confirm(struct rect *recout,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	int dpp_offset, base_offset;</div><div class='add'>+</div><div class='add'>+	calculate_adjust_recout_for_visual_confirm(pipe_ctx, &amp;base_offset,</div><div class='add'>+		&amp;dpp_offset);</div><div class='ctx'> 	recout-&gt;height -= base_offset;</div><div class='ctx'> 	recout-&gt;height -= dpp_offset;</div><div class='ctx'> }</div><div class='hunk'>@@ -1106,7 +1146,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct rect plane_clip;</div><div class='ctx'> 	struct rect mpc_slice_of_plane_clip;</div><div class='del'>-	struct rect odm_slice;</div><div class='add'>+	struct rect odm_slice_src;</div><div class='ctx'> 	struct rect overlapping_area;</div><div class='ctx'> </div><div class='ctx'> 	plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,</div><div class='hunk'>@@ -1116,16 +1156,16 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 				&amp;pipe_ctx-&gt;stream-&gt;dst);</div><div class='ctx'> 	mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(</div><div class='ctx'> 			pipe_ctx, &amp;plane_clip);</div><div class='del'>-	odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);</div><div class='del'>-	overlapping_area = intersect_rec(&amp;mpc_slice_of_plane_clip, &amp;odm_slice);</div><div class='add'>+	odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);</div><div class='add'>+	overlapping_area = intersect_rec(&amp;mpc_slice_of_plane_clip, &amp;odm_slice_src);</div><div class='ctx'> 	if (overlapping_area.height &gt; 0 &amp;&amp;</div><div class='ctx'> 			overlapping_area.width &gt; 0) {</div><div class='ctx'> 		/* shift the overlapping area so it is with respect to current</div><div class='del'>-		 * ODM slice's position</div><div class='add'>+		 * ODM slice source's position</div><div class='ctx'> 		 */</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.scl_data.recout = shift_rec(</div><div class='ctx'> 				&amp;overlapping_area,</div><div class='del'>-				-odm_slice.x, -odm_slice.y);</div><div class='add'>+				-odm_slice_src.x, -odm_slice_src.y);</div><div class='ctx'> 		adjust_recout_for_visual_confirm(</div><div class='ctx'> 				&amp;pipe_ctx-&gt;plane_res.scl_data.recout,</div><div class='ctx'> 				pipe_ctx);</div><div class='hunk'>@@ -1262,13 +1302,13 @@ static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct rect recout_clip_in_active_timing;</div><div class='ctx'> 	struct rect recout_clip_in_recout_dst;</div><div class='ctx'> 	struct rect overlap_in_active_timing;</div><div class='del'>-	struct rect odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);</div><div class='add'>+	struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);</div><div class='ctx'> 	int vpc_div = (data-&gt;format == PIXEL_FORMAT_420BPP8</div><div class='ctx'> 				|| data-&gt;format == PIXEL_FORMAT_420BPP10) ? 2 : 1;</div><div class='ctx'> 	bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;</div><div class='ctx'> </div><div class='ctx'> 	recout_clip_in_active_timing = shift_rec(</div><div class='del'>-			&amp;data-&gt;recout, odm_slice.x, odm_slice.y);</div><div class='add'>+			&amp;data-&gt;recout, odm_slice_src.x, odm_slice_src.y);</div><div class='ctx'> 	recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(</div><div class='ctx'> 			pipe_ctx, &amp;plane_state-&gt;dst_rect);</div><div class='ctx'> 	overlap_in_active_timing = intersect_rec(&amp;recout_clip_in_active_timing,</div><div class='hunk'>@@ -1349,32 +1389,6 @@ static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	data-&gt;viewport_c.y += src.y / vpc_div;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool is_subvp_high_refresh_candidate(struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	uint32_t refresh_rate;</div><div class='del'>-	struct dc *dc = stream-&gt;ctx-&gt;dc;</div><div class='del'>-</div><div class='del'>-	refresh_rate = (stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='del'>-		stream-&gt;timing.v_total * stream-&gt;timing.h_total - (uint64_t)1);</div><div class='del'>-	refresh_rate = div_u64(refresh_rate, stream-&gt;timing.v_total);</div><div class='del'>-	refresh_rate = div_u64(refresh_rate, stream-&gt;timing.h_total);</div><div class='del'>-</div><div class='del'>-	/* If there's any stream that fits the SubVP high refresh criteria,</div><div class='del'>-	 * we must return true. This is because cursor updates are asynchronous</div><div class='del'>-	 * with full updates, so we could transition into a SubVP config and</div><div class='del'>-	 * remain in HW cursor mode if there's no cursor update which will</div><div class='del'>-	 * then cause corruption.</div><div class='del'>-	 */</div><div class='del'>-	if ((refresh_rate &gt;= 120 &amp;&amp; refresh_rate &lt;= 175 &amp;&amp;</div><div class='del'>-			stream-&gt;timing.v_addressable &gt;= 1080 &amp;&amp;</div><div class='del'>-			stream-&gt;timing.v_addressable &lt;= 2160) &amp;&amp;</div><div class='del'>-			(dc-&gt;current_state-&gt;stream_count &gt; 1 ||</div><div class='del'>-			(dc-&gt;current_state-&gt;stream_count == 1 &amp;&amp; !stream-&gt;allow_freesync)))</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static enum controller_dp_test_pattern convert_dp_to_controller_test_pattern(</div><div class='ctx'> 				enum dp_test_pattern test_pattern)</div><div class='ctx'> {</div><div class='hunk'>@@ -1437,19 +1451,13 @@ static enum controller_dp_color_space convert_dp_to_controller_color_space(</div><div class='ctx'> void resource_build_test_pattern_params(struct resource_context *res_ctx,</div><div class='ctx'> 				struct pipe_ctx *otg_master)</div><div class='ctx'> {</div><div class='del'>-	int odm_slice_width, last_odm_slice_width, offset = 0;</div><div class='ctx'> 	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='ctx'> 	struct test_pattern_params *params;</div><div class='del'>-	int odm_cnt = 1;</div><div class='add'>+	int odm_cnt;</div><div class='ctx'> 	enum controller_dp_test_pattern controller_test_pattern;</div><div class='ctx'> 	enum controller_dp_color_space controller_color_space;</div><div class='ctx'> 	enum dc_color_depth color_depth = otg_master-&gt;stream-&gt;timing.display_color_depth;</div><div class='del'>-	int h_active = otg_master-&gt;stream-&gt;timing.h_addressable +</div><div class='del'>-		otg_master-&gt;stream-&gt;timing.h_border_left +</div><div class='del'>-		otg_master-&gt;stream-&gt;timing.h_border_right;</div><div class='del'>-	int v_active = otg_master-&gt;stream-&gt;timing.v_addressable +</div><div class='del'>-		otg_master-&gt;stream-&gt;timing.v_border_bottom +</div><div class='del'>-		otg_master-&gt;stream-&gt;timing.v_border_top;</div><div class='add'>+	struct rect odm_slice_src;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	controller_test_pattern = convert_dp_to_controller_test_pattern(</div><div class='hunk'>@@ -1457,25 +1465,20 @@ void resource_build_test_pattern_params(struct resource_context *res_ctx,</div><div class='ctx'> 	controller_color_space = convert_dp_to_controller_color_space(</div><div class='ctx'> 			otg_master-&gt;stream-&gt;test_pattern.color_space);</div><div class='ctx'> </div><div class='del'>-	odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);</div><div class='add'>+	if (controller_test_pattern == CONTROLLER_DP_TEST_PATTERN_VIDEOMODE)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	odm_slice_width = h_active / odm_cnt;</div><div class='del'>-	last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1);</div><div class='add'>+	odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; odm_cnt; i++) {</div><div class='add'>+		odm_slice_src = resource_get_odm_slice_src_rect(opp_heads[i]);</div><div class='ctx'> 		params = &amp;opp_heads[i]-&gt;stream_res.test_pattern_params;</div><div class='ctx'> 		params-&gt;test_pattern = controller_test_pattern;</div><div class='ctx'> 		params-&gt;color_space = controller_color_space;</div><div class='ctx'> 		params-&gt;color_depth = color_depth;</div><div class='del'>-		params-&gt;height = v_active;</div><div class='del'>-		params-&gt;offset = offset;</div><div class='del'>-</div><div class='del'>-		if (i &lt; odm_cnt - 1)</div><div class='del'>-			params-&gt;width = odm_slice_width;</div><div class='del'>-		else</div><div class='del'>-			params-&gt;width = last_odm_slice_width;</div><div class='del'>-</div><div class='del'>-		offset += odm_slice_width;</div><div class='add'>+		params-&gt;height = odm_slice_src.height;</div><div class='add'>+		params-&gt;offset = odm_slice_src.x;</div><div class='add'>+		params-&gt;width = odm_slice_src.width;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1483,12 +1486,15 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	const struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='ctx'> 	struct dc_crtc_timing *timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='del'>-	const struct rect odm_slice_rec = calculate_odm_slice_in_timing_active(pipe_ctx);</div><div class='add'>+	const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);</div><div class='add'>+	struct scaling_taps temp = {0};</div><div class='ctx'> 	bool res = false;</div><div class='add'>+</div><div class='ctx'> 	DC_LOGGER_INIT(pipe_ctx-&gt;stream-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	/* Invalid input */</div><div class='del'>-	if (!plane_state-&gt;dst_rect.width ||</div><div class='add'>+	if (!plane_state ||</div><div class='add'>+			!plane_state-&gt;dst_rect.width ||</div><div class='ctx'> 			!plane_state-&gt;dst_rect.height ||</div><div class='ctx'> 			!plane_state-&gt;src_rect.width ||</div><div class='ctx'> 			!plane_state-&gt;src_rect.height) {</div><div class='hunk'>@@ -1496,9 +1502,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pipe_ctx-&gt;plane_res.scl_data.format = convert_pixel_format_to_dalsurface(</div><div class='del'>-			pipe_ctx-&gt;plane_state-&gt;format);</div><div class='del'>-</div><div class='ctx'> 	/* Timing borders are part of vactive that we are also supposed to skip in addition</div><div class='ctx'> 	 * to any stream dst offset. Since dm logic assumes dst is in addressable</div><div class='ctx'> 	 * space we need to add the left and top borders to dst offsets temporarily.</div><div class='hunk'>@@ -1508,15 +1511,45 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;dst.y += timing-&gt;v_border_top;</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate H and V active size */</div><div class='del'>-	pipe_ctx-&gt;plane_res.scl_data.h_active = odm_slice_rec.width;</div><div class='del'>-	pipe_ctx-&gt;plane_res.scl_data.v_active = odm_slice_rec.height;</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.h_active = odm_slice_src.width;</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.v_active = odm_slice_src.height;</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.format = convert_pixel_format_to_dalsurface(</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;format);</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+	if ((pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;config.use_spl)	&amp;&amp; (!pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.disable_spl)) {</div><div class='add'>+		struct spl_in *spl_in = &amp;pipe_ctx-&gt;plane_res.spl_in;</div><div class='add'>+		struct spl_out *spl_out = &amp;pipe_ctx-&gt;plane_res.spl_out;</div><div class='ctx'> </div><div class='add'>+		if (plane_state-&gt;ctx-&gt;dce_version &gt; DCE_VERSION_MAX)</div><div class='add'>+			pipe_ctx-&gt;plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;</div><div class='add'>+		else</div><div class='add'>+			pipe_ctx-&gt;plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;plane_res.scl_data.lb_params.alpha_en = plane_state-&gt;per_pixel_alpha;</div><div class='add'>+</div><div class='add'>+		// Convert pipe_ctx to respective input params for SPL</div><div class='add'>+		translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in);</div><div class='add'>+		/* Pass visual confirm debug information */</div><div class='add'>+		calculate_adjust_recout_for_visual_confirm(pipe_ctx,</div><div class='add'>+			&amp;spl_in-&gt;debug.visual_confirm_base_offset,</div><div class='add'>+			&amp;spl_in-&gt;debug.visual_confirm_dpp_offset);</div><div class='add'>+		// Set SPL output parameters to dscl_prog_data to be used for hw registers</div><div class='add'>+		spl_out-&gt;dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);</div><div class='add'>+		// Calculate scaler parameters from SPL</div><div class='add'>+		res = spl_calculate_scaler_params(spl_in, spl_out);</div><div class='add'>+		// Convert respective out params from SPL to scaler data</div><div class='add'>+		translate_SPL_out_params_to_pipe_ctx(pipe_ctx, spl_out);</div><div class='add'>+</div><div class='add'>+		/* Ignore scaler failure if pipe context plane is phantom plane */</div><div class='add'>+		if (!res &amp;&amp; plane_state-&gt;is_phantom)</div><div class='add'>+			res = true;</div><div class='add'>+	} else {</div><div class='add'>+#endif</div><div class='ctx'> 	/* depends on h_active */</div><div class='ctx'> 	calculate_recout(pipe_ctx);</div><div class='ctx'> 	/* depends on pixel format */</div><div class='ctx'> 	calculate_scaling_ratios(pipe_ctx);</div><div class='del'>-	/* depends on scaling ratios and recout, does not calculate offset yet */</div><div class='del'>-	calculate_viewport_size(pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * LB calculations depend on vp size, h/v_active and scaling ratios</div><div class='hunk'>@@ -1537,6 +1570,24 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> </div><div class='ctx'> 	pipe_ctx-&gt;plane_res.scl_data.lb_params.alpha_en = plane_state-&gt;per_pixel_alpha;</div><div class='ctx'> </div><div class='add'>+	// get TAP value with 100x100 dummy data for max scaling qualify, override</div><div class='add'>+	// if a new scaling quality required</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.viewport.width = 100;</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.viewport.height = 100;</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.viewport_c.width = 100;</div><div class='add'>+	pipe_ctx-&gt;plane_res.scl_data.viewport_c.height = 100;</div><div class='add'>+	if (pipe_ctx-&gt;plane_res.xfm != NULL)</div><div class='add'>+		res = pipe_ctx-&gt;plane_res.xfm-&gt;funcs-&gt;transform_get_optimal_number_of_taps(</div><div class='add'>+				pipe_ctx-&gt;plane_res.xfm, &amp;pipe_ctx-&gt;plane_res.scl_data, &amp;plane_state-&gt;scaling_quality);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_res.dpp != NULL)</div><div class='add'>+		res = pipe_ctx-&gt;plane_res.dpp-&gt;funcs-&gt;dpp_get_optimal_number_of_taps(</div><div class='add'>+				pipe_ctx-&gt;plane_res.dpp, &amp;pipe_ctx-&gt;plane_res.scl_data, &amp;plane_state-&gt;scaling_quality);</div><div class='add'>+</div><div class='add'>+	temp = pipe_ctx-&gt;plane_res.scl_data.taps;</div><div class='add'>+</div><div class='add'>+	calculate_inits_and_viewports(pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 	if (pipe_ctx-&gt;plane_res.xfm != NULL)</div><div class='ctx'> 		res = pipe_ctx-&gt;plane_res.xfm-&gt;funcs-&gt;transform_get_optimal_number_of_taps(</div><div class='ctx'> 				pipe_ctx-&gt;plane_res.xfm, &amp;pipe_ctx-&gt;plane_res.scl_data, &amp;plane_state-&gt;scaling_quality);</div><div class='hunk'>@@ -1563,11 +1614,14 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 					&amp;plane_state-&gt;scaling_quality);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Depends on recout, scaling ratios, h_active and taps</div><div class='del'>-	 * May need to re-check lb size after this in some obscure scenario</div><div class='del'>-	 */</div><div class='del'>-	if (res)</div><div class='add'>+	/* Ignore scaler failure if pipe context plane is phantom plane */</div><div class='add'>+	if (!res &amp;&amp; plane_state-&gt;is_phantom)</div><div class='add'>+		res = true;</div><div class='add'>+</div><div class='add'>+	if (res &amp;&amp; (pipe_ctx-&gt;plane_res.scl_data.taps.v_taps != temp.v_taps ||</div><div class='add'>+		pipe_ctx-&gt;plane_res.scl_data.taps.h_taps != temp.h_taps ||</div><div class='add'>+		pipe_ctx-&gt;plane_res.scl_data.taps.v_taps_c != temp.v_taps_c ||</div><div class='add'>+		pipe_ctx-&gt;plane_res.scl_data.taps.h_taps_c != temp.h_taps_c))</div><div class='ctx'> 		calculate_inits_and_viewports(pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1590,8 +1644,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;</div><div class='ctx'> 	if (pipe_ctx-&gt;plane_res.scl_data.viewport.width &lt; MIN_VIEWPORT_SIZE)</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;</div><div class='del'>-</div><div class='del'>-</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='ctx'> 	DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"</div><div class='ctx'> 			"src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",</div><div class='ctx'> 			__func__,</div><div class='hunk'>@@ -1625,6 +1680,62 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *test_pipe, *split_pipe;</div><div class='add'>+	struct rect r1 = pipe_ctx-&gt;plane_res.scl_data.recout;</div><div class='add'>+	int r1_right, r1_bottom;</div><div class='add'>+	int cur_layer = pipe_ctx-&gt;plane_state-&gt;layer_index;</div><div class='add'>+</div><div class='add'>+	reverse_adjust_recout_for_visual_confirm(&amp;r1, pipe_ctx);</div><div class='add'>+	r1_right = r1.x + r1.width;</div><div class='add'>+	r1_bottom = r1.y + r1.height;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Disable the cursor if there's another pipe above this with a</div><div class='add'>+	 * plane that contains this pipe's viewport to prevent double cursor</div><div class='add'>+	 * and incorrect scaling artifacts.</div><div class='add'>+	 */</div><div class='add'>+	for (test_pipe = pipe_ctx-&gt;top_pipe; test_pipe;</div><div class='add'>+	     test_pipe = test_pipe-&gt;top_pipe) {</div><div class='add'>+		struct rect r2;</div><div class='add'>+		int r2_right, r2_bottom;</div><div class='add'>+		// Skip invisible layer and pipe-split plane on same layer</div><div class='add'>+		if (!test_pipe-&gt;plane_state ||</div><div class='add'>+		    !test_pipe-&gt;plane_state-&gt;visible ||</div><div class='add'>+		    test_pipe-&gt;plane_state-&gt;layer_index == cur_layer)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		r2 = test_pipe-&gt;plane_res.scl_data.recout;</div><div class='add'>+		reverse_adjust_recout_for_visual_confirm(&amp;r2, test_pipe);</div><div class='add'>+		r2_right = r2.x + r2.width;</div><div class='add'>+		r2_bottom = r2.y + r2.height;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * There is another half plane on same layer because of</div><div class='add'>+		 * pipe-split, merge together per same height.</div><div class='add'>+		 */</div><div class='add'>+		for (split_pipe = pipe_ctx-&gt;top_pipe; split_pipe;</div><div class='add'>+		     split_pipe = split_pipe-&gt;top_pipe)</div><div class='add'>+			if (split_pipe-&gt;plane_state-&gt;layer_index == test_pipe-&gt;plane_state-&gt;layer_index) {</div><div class='add'>+				struct rect r2_half;</div><div class='add'>+</div><div class='add'>+				r2_half = split_pipe-&gt;plane_res.scl_data.recout;</div><div class='add'>+				reverse_adjust_recout_for_visual_confirm(&amp;r2_half, split_pipe);</div><div class='add'>+				r2.x = min(r2_half.x, r2.x);</div><div class='add'>+				r2.width = r2.width + r2_half.width;</div><div class='add'>+				r2_right = r2.x + r2.width;</div><div class='add'>+				r2_bottom = min(r2_bottom, r2_half.y + r2_half.height);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+		if (r1.x &gt;= r2.x &amp;&amp; r1.y &gt;= r2.y &amp;&amp; r1_right &lt;= r2_right &amp;&amp; r1_bottom &lt;= r2_bottom)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> enum dc_status resource_build_scaling_params_for_context(</div><div class='ctx'> 	const struct dc  *dc,</div><div class='hunk'>@@ -1794,6 +1905,30 @@ int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(</div><div class='ctx'> 	return free_pipe_idx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int resource_find_free_pipe_used_as_cur_sec_dpp(</div><div class='add'>+		const struct resource_context *cur_res_ctx,</div><div class='add'>+		struct resource_context *new_res_ctx,</div><div class='add'>+		const struct resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;</div><div class='add'>+	const struct pipe_ctx *new_pipe, *cur_pipe;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+		cur_pipe = &amp;cur_res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+		new_pipe = &amp;new_res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &amp;&amp;</div><div class='add'>+				!resource_is_pipe_type(cur_pipe, OPP_HEAD) &amp;&amp;</div><div class='add'>+				resource_is_pipe_type(new_pipe, FREE_PIPE)) {</div><div class='add'>+			free_pipe_idx = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return free_pipe_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(</div><div class='ctx'> 		const struct resource_context *cur_res_ctx,</div><div class='ctx'> 		struct resource_context *new_res_ctx,</div><div class='hunk'>@@ -1875,9 +2010,15 @@ int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master,</div><div class='ctx'> 		struct pipe_ctx *opp_heads[MAX_PIPES])</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *opp_head = &amp;res_ctx-&gt;pipe_ctx[otg_master-&gt;pipe_idx];</div><div class='add'>+	struct dc *dc = otg_master-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> </div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='ctx'> 	if (!resource_is_pipe_type(otg_master, OTG_MASTER)) {</div><div class='add'>+		DC_LOG_WARNING("%s called from a non OTG master, something "</div><div class='add'>+			       "is wrong in the pipe configuration",</div><div class='add'>+			       __func__);</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2032,6 +2173,88 @@ int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	return index;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,</div><div class='add'>+		bool is_last_segment)</div><div class='add'>+{</div><div class='add'>+	const struct dc_crtc_timing *timing;</div><div class='add'>+	int count;</div><div class='add'>+	int h_active;</div><div class='add'>+	int width;</div><div class='add'>+	bool two_pixel_alignment_required = false;</div><div class='add'>+</div><div class='add'>+	if (!otg_master || !otg_master-&gt;stream)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	timing = &amp;otg_master-&gt;stream-&gt;timing;</div><div class='add'>+	count = resource_get_odm_slice_count(otg_master);</div><div class='add'>+	h_active = timing-&gt;h_addressable +</div><div class='add'>+			timing-&gt;h_border_left +</div><div class='add'>+			timing-&gt;h_border_right +</div><div class='add'>+			otg_master-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='add'>+	width = h_active / count;</div><div class='add'>+</div><div class='add'>+	if (otg_master-&gt;stream_res.tg)</div><div class='add'>+		two_pixel_alignment_required =</div><div class='add'>+				otg_master-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(timing) ||</div><div class='add'>+				/*</div><div class='add'>+				 * 422 is sub-sampled horizontally. 1 set of chromas</div><div class='add'>+				 * (Cb/Cr) is shared for 2 lumas (i.e 2 Y values).</div><div class='add'>+				 * Therefore even if 422 is still 1 pixel per container,</div><div class='add'>+				 * ODM segment width still needs to be 2 pixel aligned.</div><div class='add'>+				 */</div><div class='add'>+				timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422;</div><div class='add'>+	if ((width % 2) &amp;&amp; two_pixel_alignment_required)</div><div class='add'>+		width++;</div><div class='add'>+</div><div class='add'>+	return is_last_segment ?</div><div class='add'>+			h_active - width * (count - 1) :</div><div class='add'>+			width;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	const struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	bool is_last_odm_slice = pipe_ctx-&gt;next_odm_pipe == NULL;</div><div class='add'>+	struct pipe_ctx *otg_master = resource_get_otg_master(pipe_ctx);</div><div class='add'>+	int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);</div><div class='add'>+	int odm_segment_offset = resource_get_odm_slice_dst_width(otg_master, false);</div><div class='add'>+	struct rect odm_slice_dst;</div><div class='add'>+</div><div class='add'>+	odm_slice_dst.x = odm_segment_offset * odm_slice_idx;</div><div class='add'>+	odm_slice_dst.width = resource_get_odm_slice_dst_width(otg_master, is_last_odm_slice);</div><div class='add'>+	odm_slice_dst.y = 0;</div><div class='add'>+	odm_slice_dst.height = stream-&gt;timing.v_addressable +</div><div class='add'>+			stream-&gt;timing.v_border_bottom +</div><div class='add'>+			stream-&gt;timing.v_border_top;</div><div class='add'>+</div><div class='add'>+	return odm_slice_dst;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct rect odm_slice_dst;</div><div class='add'>+	struct rect odm_slice_src;</div><div class='add'>+	struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);</div><div class='add'>+	struct output_pixel_processor *opp = opp_head-&gt;stream_res.opp;</div><div class='add'>+	uint32_t left_edge_extra_pixel_count;</div><div class='add'>+</div><div class='add'>+	odm_slice_dst = resource_get_odm_slice_dst_rect(opp_head);</div><div class='add'>+	odm_slice_src = odm_slice_dst;</div><div class='add'>+</div><div class='add'>+	if (opp &amp;&amp; opp-&gt;funcs-&gt;opp_get_left_edge_extra_pixel_count)</div><div class='add'>+		left_edge_extra_pixel_count =</div><div class='add'>+				opp-&gt;funcs-&gt;opp_get_left_edge_extra_pixel_count(</div><div class='add'>+						opp, pipe_ctx-&gt;stream-&gt;timing.pixel_encoding,</div><div class='add'>+						resource_is_pipe_type(opp_head, OTG_MASTER));</div><div class='add'>+	else</div><div class='add'>+		left_edge_extra_pixel_count = 0;</div><div class='add'>+</div><div class='add'>+	odm_slice_src.x -= left_edge_extra_pixel_count;</div><div class='add'>+	odm_slice_src.width += left_edge_extra_pixel_count;</div><div class='add'>+</div><div class='add'>+	return odm_slice_src;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool resource_is_pipe_topology_changed(const struct dc_state *state_a,</div><div class='ctx'> 		const struct dc_state *state_b)</div><div class='ctx'> {</div><div class='hunk'>@@ -2122,10 +2345,11 @@ bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a,</div><div class='ctx'> </div><div class='ctx'> static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,</div><div class='ctx'> 		int stream_idx, int slice_idx, int plane_idx, int slice_count,</div><div class='del'>-		bool is_primary)</div><div class='add'>+		bool is_primary, bool is_phantom_pipe)</div><div class='ctx'> {</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='add'>+	// new format for logging: bit storing code</div><div class='ctx'> 	if (slice_idx == 0 &amp;&amp; plane_idx == 0 &amp;&amp; is_primary) {</div><div class='ctx'> 		/* case 0 (OTG master pipe with plane) */</div><div class='ctx'> 		DC_LOG_DC(" | plane%d  slice%d  stream%d|",</div><div class='hunk'>@@ -2134,6 +2358,10 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,</div><div class='ctx'> 				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='ctx'> 				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='ctx'> 				pipe-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+		capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,</div><div class='add'>+				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;inst, is_phantom_pipe);</div><div class='ctx'> 	} else if (slice_idx == 0 &amp;&amp; plane_idx == -1) {</div><div class='ctx'> 		/* case 1 (OTG master pipe without plane) */</div><div class='ctx'> 		DC_LOG_DC(" |         slice%d  stream%d|",</div><div class='hunk'>@@ -2142,6 +2370,10 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,</div><div class='ctx'> 				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='ctx'> 				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='ctx'> 				pipe-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+		capture_pipe_topology_data(dc, 0xF, slice_idx, stream_idx,</div><div class='add'>+				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;inst, is_phantom_pipe);</div><div class='ctx'> 	} else if (slice_idx != 0 &amp;&amp; plane_idx == 0 &amp;&amp; is_primary) {</div><div class='ctx'> 		/* case 2 (OPP head pipe with plane) */</div><div class='ctx'> 		DC_LOG_DC(" | plane%d  slice%d |       |",</div><div class='hunk'>@@ -2149,69 +2381,138 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe,</div><div class='ctx'> 		DC_LOG_DC(" |DPP%d----OPP%d----|       |",</div><div class='ctx'> 				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='ctx'> 				pipe-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+		capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,</div><div class='add'>+				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;inst, is_phantom_pipe);</div><div class='ctx'> 	} else if (slice_idx != 0 &amp;&amp; plane_idx == -1) {</div><div class='ctx'> 		/* case 3 (OPP head pipe without plane) */</div><div class='ctx'> 		DC_LOG_DC(" |         slice%d |       |", slice_idx);</div><div class='ctx'> 		DC_LOG_DC(" |DPG%d----OPP%d----|       |",</div><div class='ctx'> 				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='ctx'> 				pipe-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+		capture_pipe_topology_data(dc, 0xF, slice_idx, stream_idx,</div><div class='add'>+				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;inst, is_phantom_pipe);</div><div class='ctx'> 	} else if (slice_idx == slice_count - 1) {</div><div class='ctx'> 		/* case 4 (DPP pipe in last slice) */</div><div class='ctx'> 		DC_LOG_DC(" | plane%d |               |", plane_idx);</div><div class='ctx'> 		DC_LOG_DC(" |DPP%d----|               |",</div><div class='ctx'> 				pipe-&gt;plane_res.dpp-&gt;inst);</div><div class='add'>+		capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,</div><div class='add'>+				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;inst, is_phantom_pipe);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* case 5 (DPP pipe not in last slice) */</div><div class='ctx'> 		DC_LOG_DC(" | plane%d |       |       |", plane_idx);</div><div class='ctx'> 		DC_LOG_DC(" |DPP%d----|       |       |",</div><div class='ctx'> 				pipe-&gt;plane_res.dpp-&gt;inst);</div><div class='add'>+		capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx,</div><div class='add'>+				pipe-&gt;plane_res.dpp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.opp-&gt;inst,</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;inst, is_phantom_pipe);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)</div><div class='add'>+static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *otg_master, int stream_idx, bool is_phantom_pipe)</div><div class='ctx'> {</div><div class='del'>-	struct pipe_ctx *otg_master;</div><div class='ctx'> 	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='ctx'> 	struct pipe_ctx *dpp_pipes[MAX_PIPES];</div><div class='ctx'> </div><div class='del'>-	int stream_idx, slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;</div><div class='add'>+	int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count;</div><div class='ctx'> 	bool is_primary;</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='add'>+	slice_count = resource_get_opp_heads_for_otg_master(otg_master,</div><div class='add'>+			&amp;state-&gt;res_ctx, opp_heads);</div><div class='add'>+	for (slice_idx = 0; slice_idx &lt; slice_count; slice_idx++) {</div><div class='add'>+		plane_idx = -1;</div><div class='add'>+		if (opp_heads[slice_idx]-&gt;plane_state) {</div><div class='add'>+			dpp_count = resource_get_dpp_pipes_for_opp_head(</div><div class='add'>+					opp_heads[slice_idx],</div><div class='add'>+					&amp;state-&gt;res_ctx,</div><div class='add'>+					dpp_pipes);</div><div class='add'>+			for (dpp_idx = 0; dpp_idx &lt; dpp_count; dpp_idx++) {</div><div class='add'>+				is_primary = !dpp_pipes[dpp_idx]-&gt;top_pipe ||</div><div class='add'>+						dpp_pipes[dpp_idx]-&gt;top_pipe-&gt;plane_state != dpp_pipes[dpp_idx]-&gt;plane_state;</div><div class='add'>+				if (is_primary)</div><div class='add'>+					plane_idx++;</div><div class='add'>+				resource_log_pipe(dc, dpp_pipes[dpp_idx],</div><div class='add'>+						stream_idx, slice_idx,</div><div class='add'>+						plane_idx, slice_count,</div><div class='add'>+						is_primary, is_phantom_pipe);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			resource_log_pipe(dc, opp_heads[slice_idx],</div><div class='add'>+					stream_idx, slice_idx, plane_idx,</div><div class='add'>+					slice_count, true, is_phantom_pipe);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int resource_stream_to_stream_idx(struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i, stream_idx = -1;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		if (state-&gt;streams[i] == stream) {</div><div class='add'>+			stream_idx = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	/* never return negative array index */</div><div class='add'>+	if (stream_idx == -1) {</div><div class='add'>+		ASSERT(0);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return stream_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *otg_master;</div><div class='add'>+	int stream_idx, phantom_stream_idx;</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+	bool is_phantom_pipe = false;</div><div class='add'>+</div><div class='add'>+	// Start a new snapshot for this topology update</div><div class='add'>+	start_new_topology_snapshot(dc, state);</div><div class='add'>+</div><div class='ctx'> 	DC_LOG_DC("    pipe topology update");</div><div class='ctx'> 	DC_LOG_DC("  ________________________");</div><div class='ctx'> 	for (stream_idx = 0; stream_idx &lt; state-&gt;stream_count; stream_idx++) {</div><div class='add'>+		if (state-&gt;streams[stream_idx]-&gt;is_phantom)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		otg_master = resource_get_otg_master_for_stream(</div><div class='ctx'> 				&amp;state-&gt;res_ctx, state-&gt;streams[stream_idx]);</div><div class='del'>-		if (!otg_master	|| otg_master-&gt;stream_res.tg == NULL) {</div><div class='del'>-			DC_LOG_DC("topology update: otg_master NULL stream_idx %d!\n", stream_idx);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-		slice_count = resource_get_opp_heads_for_otg_master(otg_master,</div><div class='del'>-				&amp;state-&gt;res_ctx, opp_heads);</div><div class='del'>-		for (slice_idx = 0; slice_idx &lt; slice_count; slice_idx++) {</div><div class='del'>-			plane_idx = -1;</div><div class='del'>-			if (opp_heads[slice_idx]-&gt;plane_state) {</div><div class='del'>-				dpp_count = resource_get_dpp_pipes_for_opp_head(</div><div class='del'>-						opp_heads[slice_idx],</div><div class='del'>-						&amp;state-&gt;res_ctx,</div><div class='del'>-						dpp_pipes);</div><div class='del'>-				for (dpp_idx = 0; dpp_idx &lt; dpp_count; dpp_idx++) {</div><div class='del'>-					is_primary = !dpp_pipes[dpp_idx]-&gt;top_pipe ||</div><div class='del'>-							dpp_pipes[dpp_idx]-&gt;top_pipe-&gt;plane_state != dpp_pipes[dpp_idx]-&gt;plane_state;</div><div class='del'>-					if (is_primary)</div><div class='del'>-						plane_idx++;</div><div class='del'>-					resource_log_pipe(dc, dpp_pipes[dpp_idx],</div><div class='del'>-							stream_idx, slice_idx,</div><div class='del'>-							plane_idx, slice_count,</div><div class='del'>-							is_primary);</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='del'>-				resource_log_pipe(dc, opp_heads[slice_idx],</div><div class='del'>-						stream_idx, slice_idx, plane_idx,</div><div class='del'>-						slice_count, true);</div><div class='del'>-			}</div><div class='ctx'> </div><div class='add'>+		if (!otg_master)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		resource_log_pipe_for_stream(dc, state, otg_master, stream_idx, is_phantom_pipe);</div><div class='add'>+	}</div><div class='add'>+	if (state-&gt;phantom_stream_count &gt; 0) {</div><div class='add'>+		is_phantom_pipe = true;</div><div class='add'>+		DC_LOG_DC(" |    (phantom pipes)     |");</div><div class='add'>+		for (stream_idx = 0; stream_idx &lt; state-&gt;stream_count; stream_idx++) {</div><div class='add'>+			if (state-&gt;stream_status[stream_idx].mall_stream_config.type != SUBVP_MAIN)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			phantom_stream_idx = resource_stream_to_stream_idx(state,</div><div class='add'>+					state-&gt;stream_status[stream_idx].mall_stream_config.paired_stream);</div><div class='add'>+			otg_master = resource_get_otg_master_for_stream(</div><div class='add'>+					&amp;state-&gt;res_ctx, state-&gt;streams[phantom_stream_idx]);</div><div class='add'>+			if (!otg_master)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			resource_log_pipe_for_stream(dc, state, otg_master, stream_idx, is_phantom_pipe);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	DC_LOG_DC(" |________________________|\n");</div><div class='hunk'>@@ -2266,6 +2567,9 @@ static bool update_pipe_params_after_odm_slice_count_change(</div><div class='ctx'> </div><div class='ctx'> 	if (pool-&gt;funcs-&gt;build_pipe_pix_clk_params)</div><div class='ctx'> 		pool-&gt;funcs-&gt;build_pipe_pix_clk_params(otg_master);</div><div class='add'>+</div><div class='add'>+	resource_build_test_pattern_params(&amp;context-&gt;res_ctx, otg_master);</div><div class='add'>+</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2437,6 +2741,196 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline int find_acquired_dio_link_enc_for_link(</div><div class='add'>+		const struct resource_context *res_ctx,</div><div class='add'>+		const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(res_ctx-&gt;dio_link_enc_ref_cnts); i++)</div><div class='add'>+		if (res_ctx-&gt;dio_link_enc_ref_cnts[i] &gt; 0 &amp;&amp;</div><div class='add'>+				res_ctx-&gt;dio_link_enc_to_link_idx[i] == link-&gt;link_index)</div><div class='add'>+			return i;</div><div class='add'>+</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int find_fixed_dio_link_enc(const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	/* the 8b10b dp phy can only use fixed link encoder */</div><div class='add'>+	return link-&gt;eng_id;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int find_free_dio_link_enc(const struct resource_context *res_ctx,</div><div class='add'>+		const struct dc_link *link, const struct resource_pool *pool, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i, j = -1;</div><div class='add'>+	int stream_enc_inst = -1;</div><div class='add'>+	int enc_count = pool-&gt;dig_link_enc_count;</div><div class='add'>+</div><div class='add'>+	/* Find stream encoder instance for the stream */</div><div class='add'>+	if (stream) {</div><div class='add'>+		for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+			if ((res_ctx-&gt;pipe_ctx[i].stream == stream) &amp;&amp;</div><div class='add'>+				(res_ctx-&gt;pipe_ctx[i].stream_res.stream_enc != NULL)) {</div><div class='add'>+				stream_enc_inst = res_ctx-&gt;pipe_ctx[i].stream_res.stream_enc-&gt;id;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Assign dpia preferred &gt; stream enc instance &gt; available */</div><div class='add'>+	for (i = 0; i &lt; enc_count; i++) {</div><div class='add'>+		if (res_ctx-&gt;dio_link_enc_ref_cnts[i] == 0) {</div><div class='add'>+			if (j == -1)</div><div class='add'>+				j = i;</div><div class='add'>+</div><div class='add'>+			if (link-&gt;dpia_preferred_eng_id == i) {</div><div class='add'>+				j = i;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (stream_enc_inst == i) {</div><div class='add'>+				j = stream_enc_inst;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return j;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void acquire_dio_link_enc(</div><div class='add'>+		struct resource_context *res_ctx,</div><div class='add'>+		unsigned int link_index,</div><div class='add'>+		int enc_index)</div><div class='add'>+{</div><div class='add'>+	res_ctx-&gt;dio_link_enc_to_link_idx[enc_index] = link_index;</div><div class='add'>+	res_ctx-&gt;dio_link_enc_ref_cnts[enc_index] = 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void retain_dio_link_enc(</div><div class='add'>+		struct resource_context *res_ctx,</div><div class='add'>+		int enc_index)</div><div class='add'>+{</div><div class='add'>+	res_ctx-&gt;dio_link_enc_ref_cnts[enc_index]++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void release_dio_link_enc(</div><div class='add'>+		struct resource_context *res_ctx,</div><div class='add'>+		int enc_index)</div><div class='add'>+{</div><div class='add'>+	ASSERT(res_ctx-&gt;dio_link_enc_ref_cnts[enc_index] &gt; 0);</div><div class='add'>+	res_ctx-&gt;dio_link_enc_ref_cnts[enc_index]--;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_dio_enc_acquired_by_other_link(const struct dc_link *link,</div><div class='add'>+		int enc_index,</div><div class='add'>+		int *link_index)</div><div class='add'>+{</div><div class='add'>+	const struct dc *dc  = link-&gt;dc;</div><div class='add'>+	const struct resource_context *res_ctx = &amp;dc-&gt;current_state-&gt;res_ctx;</div><div class='add'>+</div><div class='add'>+	/* pass the link_index that acquired the enc_index */</div><div class='add'>+	if (res_ctx-&gt;dio_link_enc_ref_cnts[enc_index] &gt; 0 &amp;&amp;</div><div class='add'>+			res_ctx-&gt;dio_link_enc_to_link_idx[enc_index] != link-&gt;link_index) {</div><div class='add'>+		*link_index = res_ctx-&gt;dio_link_enc_to_link_idx[enc_index];</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void swap_dio_link_enc_to_muxable_ctx(struct dc_state *context,</div><div class='add'>+		const struct resource_pool *pool,</div><div class='add'>+		int new_encoder,</div><div class='add'>+		int old_encoder)</div><div class='add'>+{</div><div class='add'>+	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='add'>+	int stream_count = context-&gt;stream_count;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	res_ctx-&gt;dio_link_enc_ref_cnts[new_encoder] = res_ctx-&gt;dio_link_enc_ref_cnts[old_encoder];</div><div class='add'>+	res_ctx-&gt;dio_link_enc_to_link_idx[new_encoder] = res_ctx-&gt;dio_link_enc_to_link_idx[old_encoder];</div><div class='add'>+	res_ctx-&gt;dio_link_enc_ref_cnts[old_encoder] = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; stream_count; i++) {</div><div class='add'>+		struct dc_stream_state *stream = context-&gt;streams[i];</div><div class='add'>+		struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, stream);</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx &amp;&amp; pipe_ctx-&gt;link_res.dio_link_enc == pool-&gt;link_encoders[old_encoder])</div><div class='add'>+			pipe_ctx-&gt;link_res.dio_link_enc = pool-&gt;link_encoders[new_encoder];</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool add_dio_link_enc_to_ctx(const struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		const struct resource_pool *pool,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='add'>+	int enc_index;</div><div class='add'>+</div><div class='add'>+	enc_index = find_acquired_dio_link_enc_for_link(res_ctx, stream-&gt;link);</div><div class='add'>+</div><div class='add'>+	if (enc_index &gt;= 0) {</div><div class='add'>+		retain_dio_link_enc(res_ctx, enc_index);</div><div class='add'>+	} else {</div><div class='add'>+		if (stream-&gt;link-&gt;is_dig_mapping_flexible)</div><div class='add'>+			enc_index = find_free_dio_link_enc(res_ctx, stream-&gt;link, pool, stream);</div><div class='add'>+		else {</div><div class='add'>+			int link_index = 0;</div><div class='add'>+</div><div class='add'>+			enc_index = find_fixed_dio_link_enc(stream-&gt;link);</div><div class='add'>+			/* Fixed mapping link can only use its fixed link encoder.</div><div class='add'>+			 * If the encoder is acquired by other link then get a new free encoder and swap the new</div><div class='add'>+			 * one into the acquiring link.</div><div class='add'>+			 */</div><div class='add'>+			if (enc_index &gt;= 0 &amp;&amp; is_dio_enc_acquired_by_other_link(stream-&gt;link, enc_index, &amp;link_index)) {</div><div class='add'>+				int new_enc_index = find_free_dio_link_enc(res_ctx, dc-&gt;links[link_index], pool, stream);</div><div class='add'>+</div><div class='add'>+				if (new_enc_index &gt;= 0)</div><div class='add'>+					swap_dio_link_enc_to_muxable_ctx(context, pool, new_enc_index, enc_index);</div><div class='add'>+				else</div><div class='add'>+					return false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (enc_index &gt;= 0)</div><div class='add'>+			acquire_dio_link_enc(res_ctx, stream-&gt;link-&gt;link_index, enc_index);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enc_index &gt;= 0)</div><div class='add'>+		pipe_ctx-&gt;link_res.dio_link_enc = pool-&gt;link_encoders[enc_index];</div><div class='add'>+</div><div class='add'>+	return pipe_ctx-&gt;link_res.dio_link_enc != NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void remove_dio_link_enc_from_ctx(struct resource_context *res_ctx,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int enc_index = -1;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;link)</div><div class='add'>+		enc_index = find_acquired_dio_link_enc_for_link(res_ctx, stream-&gt;link);</div><div class='add'>+</div><div class='add'>+	if (enc_index &gt;= 0) {</div><div class='add'>+		release_dio_link_enc(res_ctx, enc_index);</div><div class='add'>+		pipe_ctx-&gt;link_res.dio_link_enc = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	int count = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;pipe_count; i++)</div><div class='add'>+		if (resource_is_pipe_type(&amp;context-&gt;res_ctx.pipe_ctx[i], FREE_PIPE))</div><div class='add'>+			count++;</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,</div><div class='ctx'> 		const struct resource_pool *pool,</div><div class='ctx'> 		struct dc_stream_state *stream)</div><div class='hunk'>@@ -2473,6 +2967,10 @@ void resource_remove_otg_master_for_stream_output(struct dc_state *context,</div><div class='ctx'> 		remove_hpo_dp_link_enc_from_ctx(</div><div class='ctx'> 				&amp;context-&gt;res_ctx, otg_master, stream);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		remove_dio_link_enc_from_ctx(&amp;context-&gt;res_ctx, otg_master, stream);</div><div class='add'>+</div><div class='ctx'> 	if (otg_master-&gt;stream_res.audio)</div><div class='ctx'> 		update_audio_usage(</div><div class='ctx'> 			&amp;context-&gt;res_ctx,</div><div class='hunk'>@@ -2487,6 +2985,7 @@ void resource_remove_otg_master_for_stream_output(struct dc_state *context,</div><div class='ctx'> 	if (pool-&gt;funcs-&gt;remove_stream_from_ctx)</div><div class='ctx'> 		pool-&gt;funcs-&gt;remove_stream_from_ctx(</div><div class='ctx'> 				stream-&gt;ctx-&gt;dc, context, stream);</div><div class='add'>+</div><div class='ctx'> 	memset(otg_master, 0, sizeof(*otg_master));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2570,37 +3069,33 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(</div><div class='ctx'> 		struct dc_state *cur_ctx,</div><div class='ctx'> 		struct resource_pool *pool)</div><div class='ctx'> {</div><div class='del'>-	struct pipe_ctx *opp_head_pipe, *sec_pipe, *tail_pipe;</div><div class='add'>+	struct pipe_ctx *sec_pipe, *tail_pipe;</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='add'>+	int opp_head_count;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!pool-&gt;funcs-&gt;acquire_free_pipe_as_secondary_dpp_pipe) {</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	opp_head_pipe = otg_master_pipe;</div><div class='del'>-	while (opp_head_pipe) {</div><div class='add'>+	opp_head_count = resource_get_opp_heads_for_otg_master(otg_master_pipe,</div><div class='add'>+			&amp;new_ctx-&gt;res_ctx, opp_heads);</div><div class='add'>+	if (get_num_of_free_pipes(pool, new_ctx) &lt; opp_head_count)</div><div class='add'>+		/* not enough free pipes */</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; opp_head_count; i++) {</div><div class='ctx'> 		sec_pipe = pool-&gt;funcs-&gt;acquire_free_pipe_as_secondary_dpp_pipe(</div><div class='ctx'> 				cur_ctx,</div><div class='ctx'> 				new_ctx,</div><div class='ctx'> 				pool,</div><div class='del'>-				opp_head_pipe);</div><div class='del'>-		if (!sec_pipe) {</div><div class='del'>-			/* try tearing down MPCC combine */</div><div class='del'>-			int pipe_idx = acquire_first_split_pipe(</div><div class='del'>-					&amp;new_ctx-&gt;res_ctx, pool,</div><div class='del'>-					otg_master_pipe-&gt;stream);</div><div class='del'>-</div><div class='del'>-			if (pipe_idx &gt;= 0)</div><div class='del'>-				sec_pipe = &amp;new_ctx-&gt;res_ctx.pipe_ctx[pipe_idx];</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (!sec_pipe)</div><div class='del'>-			return false;</div><div class='del'>-</div><div class='add'>+				opp_heads[i]);</div><div class='add'>+		ASSERT(sec_pipe);</div><div class='ctx'> 		sec_pipe-&gt;plane_state = plane_state;</div><div class='ctx'> </div><div class='ctx'> 		/* establish pipe relationship */</div><div class='del'>-		tail_pipe = get_tail_pipe(opp_head_pipe);</div><div class='add'>+		tail_pipe = get_tail_pipe(opp_heads[i]);</div><div class='ctx'> 		tail_pipe-&gt;bottom_pipe = sec_pipe;</div><div class='ctx'> 		sec_pipe-&gt;top_pipe = tail_pipe;</div><div class='ctx'> 		sec_pipe-&gt;bottom_pipe = NULL;</div><div class='hunk'>@@ -2611,8 +3106,6 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(</div><div class='ctx'> 		} else {</div><div class='ctx'> 			sec_pipe-&gt;prev_odm_pipe = NULL;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		opp_head_pipe = opp_head_pipe-&gt;next_odm_pipe;</div><div class='ctx'> 	}</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -2624,13 +3117,25 @@ bool resource_append_dpp_pipes_for_plane_composition(</div><div class='ctx'> 		struct pipe_ctx *otg_master_pipe,</div><div class='ctx'> 		struct dc_plane_state *plane_state)</div><div class='ctx'> {</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='ctx'> 	if (otg_master_pipe-&gt;plane_state == NULL)</div><div class='del'>-		return add_plane_to_opp_head_pipes(otg_master_pipe,</div><div class='add'>+		success = add_plane_to_opp_head_pipes(otg_master_pipe,</div><div class='ctx'> 				plane_state, new_ctx);</div><div class='ctx'> 	else</div><div class='del'>-		return acquire_secondary_dpp_pipes_and_add_plane(</div><div class='add'>+		success = acquire_secondary_dpp_pipes_and_add_plane(</div><div class='ctx'> 				otg_master_pipe, plane_state, new_ctx,</div><div class='ctx'> 				cur_ctx, pool);</div><div class='add'>+	if (success) {</div><div class='add'>+		/* when appending a plane mpc slice count changes from 0 to 1 */</div><div class='add'>+		success = update_pipe_params_after_mpc_slice_count_change(</div><div class='add'>+				plane_state, new_ctx, pool);</div><div class='add'>+		if (!success)</div><div class='add'>+			resource_remove_dpp_pipes_for_plane_composition(new_ctx,</div><div class='add'>+					pool, plane_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void resource_remove_dpp_pipes_for_plane_composition(</div><div class='hunk'>@@ -2639,6 +3144,7 @@ void resource_remove_dpp_pipes_for_plane_composition(</div><div class='ctx'> 		const struct dc_plane_state *plane_state)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='add'>+</div><div class='ctx'> 	for (i = pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='hunk'>@@ -2935,9 +3441,14 @@ bool resource_update_pipes_for_stream_with_slice_count(</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(</div><div class='ctx'> 			&amp;new_ctx-&gt;res_ctx, stream);</div><div class='del'>-	int cur_slice_count = resource_get_odm_slice_count(otg_master);</div><div class='add'>+	int cur_slice_count;</div><div class='ctx'> 	bool result = true;</div><div class='ctx'> </div><div class='add'>+	if (!otg_master)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	cur_slice_count = resource_get_odm_slice_count(otg_master);</div><div class='add'>+</div><div class='ctx'> 	if (new_slice_count == cur_slice_count)</div><div class='ctx'> 		return result;</div><div class='ctx'> </div><div class='hunk'>@@ -2965,7 +3476,7 @@ bool resource_update_pipes_for_plane_with_slice_count(</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int dpp_pipe_count;</div><div class='ctx'> 	int cur_slice_count;</div><div class='del'>-	struct pipe_ctx *dpp_pipes[MAX_PIPES];</div><div class='add'>+	struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};</div><div class='ctx'> 	bool result = true;</div><div class='ctx'> </div><div class='ctx'> 	dpp_pipe_count = resource_get_dpp_pipes_for_plane(plane,</div><div class='hunk'>@@ -3038,6 +3549,8 @@ static bool are_stream_backends_same(</div><div class='ctx'> bool dc_is_stream_unchanged(</div><div class='ctx'> 	struct dc_stream_state *old_stream, struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='add'>+	if (!old_stream || !stream)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (!are_stream_backends_same(old_stream, stream))</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -3117,6 +3630,9 @@ static struct audio *find_first_free_audio(</div><div class='ctx'> {</div><div class='ctx'> 	int i, available_audio_count;</div><div class='ctx'> </div><div class='add'>+	if (id == ENGINE_ID_UNKNOWN)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	available_audio_count = pool-&gt;audio_count;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; available_audio_count; i++) {</div><div class='hunk'>@@ -3181,10 +3697,13 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing)</div><div class='ctx'> 			break;</div><div class='ctx'> 		case COLOR_DEPTH_121212:</div><div class='ctx'> 			normalized_pix_clk = (pix_clk * 36) / 24;</div><div class='del'>-		break;</div><div class='add'>+			break;</div><div class='add'>+		case COLOR_DEPTH_141414:</div><div class='add'>+			normalized_pix_clk = (pix_clk * 42) / 24;</div><div class='add'>+			break;</div><div class='ctx'> 		case COLOR_DEPTH_161616:</div><div class='ctx'> 			normalized_pix_clk = (pix_clk * 48) / 24;</div><div class='del'>-		break;</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			ASSERT(0);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -3318,16 +3837,22 @@ static int acquire_resource_from_hw_enabled_state(</div><div class='ctx'> 	return -1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mark_seamless_boot_stream(</div><div class='del'>-		const struct dc  *dc,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='add'>+static void mark_seamless_boot_stream(const struct dc  *dc,</div><div class='add'>+				      struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;config.allow_seamless_boot_optimization &amp;&amp;</div><div class='del'>-			!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb)) {</div><div class='del'>-		if (dc_validate_boot_timing(dc, stream-&gt;sink, &amp;stream-&gt;timing))</div><div class='del'>-			stream-&gt;apply_seamless_boot_optimization = true;</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;apply_seamless_boot_optimization)</div><div class='add'>+		return;</div><div class='add'>+	if (!dc-&gt;config.allow_seamless_boot_optimization)</div><div class='add'>+		return;</div><div class='add'>+	if (dcb-&gt;funcs-&gt;is_accelerated_mode(dcb))</div><div class='add'>+		return;</div><div class='add'>+	if (dc_validate_boot_timing(dc, stream-&gt;sink, &amp;stream-&gt;timing)) {</div><div class='add'>+		stream-&gt;apply_seamless_boot_optimization = true;</div><div class='add'>+		DC_LOG_DC("Marked stream for seamless boot optimization\n");</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3371,11 +3896,31 @@ static bool acquire_otg_master_pipe_for_stream(</div><div class='ctx'> 	 * any free pipes already used in current context as this could tear</div><div class='ctx'> 	 * down exiting ODM/MPC/MPO configuration unnecessarily.</div><div class='ctx'> 	 */</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Try to acquire the same OTG master already in use. This is not</div><div class='add'>+	 * optimal because resetting an enabled OTG master pipe for a new stream</div><div class='add'>+	 * requires an extra frame of wait. However there are test automation</div><div class='add'>+	 * and eDP assumptions that rely on reusing the same OTG master pipe</div><div class='add'>+	 * during mode change. We have to keep this logic as is for now.</div><div class='add'>+	 */</div><div class='ctx'> 	pipe_idx = recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(</div><div class='ctx'> 			&amp;cur_ctx-&gt;res_ctx, &amp;new_ctx-&gt;res_ctx, pool);</div><div class='add'>+	/*</div><div class='add'>+	 * Try to acquire a pipe not used in current resource context to avoid</div><div class='add'>+	 * pipe swapping.</div><div class='add'>+	 */</div><div class='ctx'> 	if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)</div><div class='ctx'> 		pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(</div><div class='ctx'> 				&amp;cur_ctx-&gt;res_ctx, &amp;new_ctx-&gt;res_ctx, pool);</div><div class='add'>+	/*</div><div class='add'>+	 * If pipe swapping is unavoidable, try to acquire pipe used as</div><div class='add'>+	 * secondary DPP pipe in current state as we prioritize to support more</div><div class='add'>+	 * streams over supporting MPO planes.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)</div><div class='add'>+		pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp(</div><div class='add'>+				&amp;cur_ctx-&gt;res_ctx, &amp;new_ctx-&gt;res_ctx, pool);</div><div class='ctx'> 	if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)</div><div class='ctx'> 		pipe_idx = resource_find_any_free_pipe(&amp;new_ctx-&gt;res_ctx, pool);</div><div class='ctx'> 	if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {</div><div class='hunk'>@@ -3392,7 +3937,7 @@ static bool acquire_otg_master_pipe_for_stream(</div><div class='ctx'> 		if (pool-&gt;dpps[pipe_idx])</div><div class='ctx'> 			pipe_ctx-&gt;plane_res.mpcc_inst = pool-&gt;dpps[pipe_idx]-&gt;inst;</div><div class='ctx'> </div><div class='del'>-		if (pipe_idx &gt;= pool-&gt;timing_generator_count) {</div><div class='add'>+		if (pipe_idx &gt;= pool-&gt;timing_generator_count &amp;&amp; pool-&gt;timing_generator_count != 0) {</div><div class='ctx'> 			int tg_inst = pool-&gt;timing_generator_count - 1;</div><div class='ctx'> </div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg = pool-&gt;timing_generators[tg_inst];</div><div class='hunk'>@@ -3418,6 +3963,7 @@ enum dc_status resource_map_pool_resources(</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx = NULL;</div><div class='ctx'> 	int pipe_idx = -1;</div><div class='ctx'> 	bool acquired = false;</div><div class='add'>+	bool is_dio_encoder = true;</div><div class='ctx'> </div><div class='ctx'> 	calculate_phy_pix_clks(stream);</div><div class='ctx'> </div><div class='hunk'>@@ -3460,9 +4006,15 @@ enum dc_status resource_map_pool_resources(</div><div class='ctx'> 	/* Allocate DP HPO Stream Encoder based on signal, hw capabilities</div><div class='ctx'> 	 * and link settings</div><div class='ctx'> 	 */</div><div class='del'>-	if (dc_is_dp_signal(stream-&gt;signal)) {</div><div class='del'>-		if (!dc-&gt;link_srv-&gt;dp_decide_link_settings(stream, &amp;pipe_ctx-&gt;link_config.dp_link_settings))</div><div class='add'>+	if (dc_is_dp_signal(stream-&gt;signal) ||</div><div class='add'>+			dc_is_virtual_signal(stream-&gt;signal)) {</div><div class='add'>+		if (!dc-&gt;link_srv-&gt;dp_decide_link_settings(stream,</div><div class='add'>+				&amp;pipe_ctx-&gt;link_config.dp_link_settings))</div><div class='ctx'> 			return DC_FAIL_DP_LINK_BANDWIDTH;</div><div class='add'>+</div><div class='add'>+		dc-&gt;link_srv-&gt;dp_decide_tunnel_settings(stream,</div><div class='add'>+				&amp;pipe_ctx-&gt;link_config.dp_tunnel_settings);</div><div class='add'>+</div><div class='ctx'> 		if (dc-&gt;link_srv-&gt;dp_get_encoding_format(</div><div class='ctx'> 				&amp;pipe_ctx-&gt;link_config.dp_link_settings) == DP_128b_132b_ENCODING) {</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.hpo_dp_stream_enc =</div><div class='hunk'>@@ -3481,10 +4033,16 @@ enum dc_status resource_map_pool_resources(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;config.unify_link_enc_assignment &amp;&amp; is_dio_encoder)</div><div class='add'>+		if (!add_dio_link_enc_to_ctx(dc, context, pool, pipe_ctx, stream))</div><div class='add'>+			return DC_NO_LINK_ENC_RESOURCE;</div><div class='add'>+</div><div class='ctx'> 	/* TODO: Add check if ASIC support and EDID audio */</div><div class='ctx'> 	if (!stream-&gt;converter_disable_audio &amp;&amp;</div><div class='ctx'> 	    dc_is_audio_capable_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp;</div><div class='del'>-	    stream-&gt;audio_info.mode_count &amp;&amp; stream-&gt;audio_info.flags.all) {</div><div class='add'>+	    stream-&gt;audio_info.mode_count &amp;&amp;</div><div class='add'>+		(stream-&gt;audio_info.flags.all ||</div><div class='add'>+		(stream-&gt;sink &amp;&amp; stream-&gt;sink-&gt;edid_caps.panel_patch.skip_audio_sab_check))) {</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.audio = find_first_free_audio(</div><div class='ctx'> 		&amp;context-&gt;res_ctx, pool, pipe_ctx-&gt;stream_res.stream_enc-&gt;id, dc_ctx-&gt;dce_version);</div><div class='ctx'> </div><div class='hunk'>@@ -3543,8 +4101,10 @@ static bool planes_changed_for_existing_stream(struct dc_state *context,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!stream_status)</div><div class='add'>+	if (!stream_status) {</div><div class='ctx'> 		ASSERT(0);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; set_count; i++)</div><div class='ctx'> 		if (set[i].stream == stream)</div><div class='hunk'>@@ -3595,7 +4155,7 @@ static bool add_all_planes_for_stream(</div><div class='ctx'>  * @set: An array of dc_validation_set with all the current streams reference</div><div class='ctx'>  * @set_count: Total of streams</div><div class='ctx'>  * @context: New context</div><div class='del'>- * @fast_validate: Enable or disable fast validation</div><div class='add'>+ * @validate_mode: identify the validation mode</div><div class='ctx'>  *</div><div class='ctx'>  * This function updates the potential new stream in the context object. It</div><div class='ctx'>  * creates multiple lists for the add, remove, and unchanged streams. In</div><div class='hunk'>@@ -3610,7 +4170,7 @@ enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='ctx'> 					const struct dc_validation_set set[],</div><div class='ctx'> 					int set_count,</div><div class='ctx'> 					struct dc_state *context,</div><div class='del'>-					bool fast_validate)</div><div class='add'>+					enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };</div><div class='ctx'> 	struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };</div><div class='hunk'>@@ -3779,7 +4339,18 @@ enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	res = dc_validate_global_state(dc, context, fast_validate);</div><div class='add'>+	/* clear subvp cursor limitations */</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		dc_state_set_stream_subvp_cursor_limit(context-&gt;streams[i], context, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	res = dc_validate_global_state(dc, context, validate_mode);</div><div class='add'>+</div><div class='add'>+	/* calculate pixel rate divider after deciding pxiel clock &amp; odm combine  */</div><div class='add'>+	if ((dc-&gt;hwss.calculate_pix_rate_divider) &amp;&amp; (res == DC_OK)) {</div><div class='add'>+		for (i = 0; i &lt; add_streams_count; i++)</div><div class='add'>+			dc-&gt;hwss.calculate_pix_rate_divider(dc, context, add_streams[i]);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='ctx'> 	if (res != DC_OK)</div><div class='hunk'>@@ -3790,12 +4361,41 @@ fail:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+#endif /* CONFIG_DRM_AMD_DC_FP */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * calculate_timing_params_for_dsc_with_padding - Calculates timing parameters for DSC with padding.</div><div class='add'>+ * @pipe_ctx: Pointer to the pipe context structure.</div><div class='add'>+ *</div><div class='add'>+ * This function calculates the timing parameters for a given pipe context based on the</div><div class='add'>+ * display stream compression (DSC) configuration. If the horizontal active pixels (hactive) are less</div><div class='add'>+ * than the total width of the DSC slices, it sets the dsc_hactive_padding value to the difference. If the</div><div class='add'>+ * total horizontal timing minus the dsc_hactive_padding value is less than 32, it resets the dsc_hactive_padding</div><div class='add'>+ * value to 0.</div><div class='add'>+ */</div><div class='add'>+static void calculate_timing_params_for_dsc_with_padding(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *stream = NULL;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	stream = pipe_ctx-&gt;stream;</div><div class='add'>+	pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding = 0;</div><div class='add'>+	pipe_ctx-&gt;dsc_padding_params.dsc_htotal_padding = 0;</div><div class='add'>+</div><div class='add'>+	if (stream)</div><div class='add'>+		pipe_ctx-&gt;dsc_padding_params.dsc_pix_clk_100hz = stream-&gt;timing.pix_clk_100hz;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * dc_validate_global_state() - Determine if hardware can support a given state</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: dc struct for this driver</div><div class='ctx'>  * @new_ctx: state to be validated</div><div class='del'>- * @fast_validate: set to true if only yes/no to support matters</div><div class='add'>+ * @validate_mode: identify the validation mode</div><div class='ctx'>  *</div><div class='ctx'>  * Checks hardware resource availability and bandwidth requirement.</div><div class='ctx'>  *</div><div class='hunk'>@@ -3805,7 +4405,7 @@ fail:</div><div class='ctx'> enum dc_status dc_validate_global_state(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *new_ctx,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_status result = DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	int i, j;</div><div class='hunk'>@@ -3828,6 +4428,10 @@ enum dc_status dc_validate_global_state(</div><div class='ctx'> 			if (pipe_ctx-&gt;stream != stream)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='add'>+			/* Decide whether hblank borrow is needed and save it in pipe_ctx */</div><div class='add'>+			if (dc-&gt;debug.enable_hblank_borrow)</div><div class='add'>+				calculate_timing_params_for_dsc_with_padding(pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 			if (dc-&gt;res_pool-&gt;funcs-&gt;patch_unknown_plane_state &amp;&amp;</div><div class='ctx'> 					pipe_ctx-&gt;plane_state &amp;&amp;</div><div class='ctx'> 					pipe_ctx-&gt;plane_state-&gt;tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {</div><div class='hunk'>@@ -3860,16 +4464,7 @@ enum dc_status dc_validate_global_state(</div><div class='ctx'> 	result = resource_build_scaling_params_for_context(dc, new_ctx);</div><div class='ctx'> </div><div class='ctx'> 	if (result == DC_OK)</div><div class='del'>-		if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, new_ctx, fast_validate))</div><div class='del'>-			result = DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Only update link encoder to stream assignment after bandwidth validation passed.</div><div class='del'>-	 * TODO: Split out assignment and validation.</div><div class='del'>-	 */</div><div class='del'>-	if (result == DC_OK &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign &amp;&amp; fast_validate == false)</div><div class='del'>-		dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign(</div><div class='del'>-			dc, new_ctx, new_ctx-&gt;streams, new_ctx-&gt;stream_count);</div><div class='add'>+		result = dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, new_ctx, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='hunk'>@@ -3910,8 +4505,14 @@ static void set_avi_info_frame(</div><div class='ctx'> 	unsigned int fr_ind = pipe_ctx-&gt;stream-&gt;timing.fr_index;</div><div class='ctx'> 	enum dc_timing_3d_format format;</div><div class='ctx'> </div><div class='add'>+	if (stream-&gt;avi_infopacket.valid) {</div><div class='add'>+		*info_packet = stream-&gt;avi_infopacket;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	memset(&amp;hdmi_info, 0, sizeof(union hdmi_info_packet));</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> 	color_space = pipe_ctx-&gt;stream-&gt;output_color_space;</div><div class='ctx'> 	if (color_space == COLOR_SPACE_UNKNOWN)</div><div class='ctx'> 		color_space = (stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_RGB) ?</div><div class='hunk'>@@ -3975,7 +4576,7 @@ static void set_avi_info_frame(</div><div class='ctx'> 		break;</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_FULLRANGE:</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:</div><div class='del'>-	case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='ctx'> 		hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;</div><div class='ctx'> 		hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -3989,8 +4590,8 @@ static void set_avi_info_frame(</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pixel_encoding &amp;&amp; color_space == COLOR_SPACE_2020_YCBCR &amp;&amp;</div><div class='del'>-			stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_GAMMA22) {</div><div class='add'>+	if (pixel_encoding &amp;&amp; color_space == COLOR_SPACE_2020_YCBCR_LIMITED &amp;&amp;</div><div class='add'>+			stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {</div><div class='ctx'> 		hdmi_info.bits.EC0_EC2 = 0;</div><div class='ctx'> 		hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4091,7 +4692,7 @@ static void set_avi_info_frame(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (rid != 0 &amp;&amp; fr_ind != 0) {</div><div class='del'>-		hdmi_info.bits.header.version = 5;</div><div class='add'>+		hdmi_info.bits.header.version = 4;</div><div class='ctx'> 		hdmi_info.bits.header.length = 15;</div><div class='ctx'> </div><div class='ctx'> 		hdmi_info.bits.FR0_FR3 = fr_ind &amp; 0xF;</div><div class='hunk'>@@ -4210,7 +4811,7 @@ static void set_hfvs_info_packet(</div><div class='ctx'> static void adaptive_sync_override_dp_info_packets_sdp_line_num(</div><div class='ctx'> 		const struct dc_crtc_timing *timing,</div><div class='ctx'> 		struct enc_sdp_line_num *sdp_line_num,</div><div class='del'>-		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)</div><div class='add'>+		unsigned int vstartup_start)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t asic_blank_start = 0;</div><div class='ctx'> 	uint32_t asic_blank_end   = 0;</div><div class='hunk'>@@ -4225,8 +4826,8 @@ static void adaptive_sync_override_dp_info_packets_sdp_line_num(</div><div class='ctx'> 	asic_blank_end = (asic_blank_start - tg-&gt;v_border_bottom -</div><div class='ctx'> 						tg-&gt;v_addressable - tg-&gt;v_border_top);</div><div class='ctx'> </div><div class='del'>-	if (pipe_dlg_param-&gt;vstartup_start &gt; asic_blank_end) {</div><div class='del'>-		v_update = (tg-&gt;v_total - (pipe_dlg_param-&gt;vstartup_start - asic_blank_end));</div><div class='add'>+	if (vstartup_start &gt; asic_blank_end) {</div><div class='add'>+		v_update = (tg-&gt;v_total - (vstartup_start - asic_blank_end));</div><div class='ctx'> 		sdp_line_num-&gt;adaptive_sync_line_num_valid = true;</div><div class='ctx'> 		sdp_line_num-&gt;adaptive_sync_line_num = (tg-&gt;v_total - v_update - 1);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -4239,7 +4840,7 @@ static void set_adaptive_sync_info_packet(</div><div class='ctx'> 		struct dc_info_packet *info_packet,</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		struct encoder_info_frame *info_frame,</div><div class='del'>-		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)</div><div class='add'>+		unsigned int vstartup_start)</div><div class='ctx'> {</div><div class='ctx'> 	if (!stream-&gt;adaptive_sync_infopacket.valid)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -4247,7 +4848,7 @@ static void set_adaptive_sync_info_packet(</div><div class='ctx'> 	adaptive_sync_override_dp_info_packets_sdp_line_num(</div><div class='ctx'> 			&amp;stream-&gt;timing,</div><div class='ctx'> 			&amp;info_frame-&gt;sdp_line_num,</div><div class='del'>-			pipe_dlg_param);</div><div class='add'>+			vstartup_start);</div><div class='ctx'> </div><div class='ctx'> 	*info_packet = stream-&gt;adaptive_sync_infopacket;</div><div class='ctx'> }</div><div class='hunk'>@@ -4280,6 +4881,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	enum signal_type signal = SIGNAL_TYPE_NONE;</div><div class='ctx'> 	struct encoder_info_frame *info = &amp;pipe_ctx-&gt;stream_res.encoder_info_frame;</div><div class='add'>+	unsigned int vstartup_start = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* default all packets to invalid */</div><div class='ctx'> 	info-&gt;avi.valid = false;</div><div class='hunk'>@@ -4293,6 +4895,9 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	info-&gt;adaptive_sync.valid = false;</div><div class='ctx'> 	signal = pipe_ctx-&gt;stream-&gt;signal;</div><div class='ctx'> </div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;get_vstartup_for_pipe)</div><div class='add'>+		vstartup_start = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;get_vstartup_for_pipe(pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 	/* HDMi and DP have different info packets*/</div><div class='ctx'> 	if (dc_is_hdmi_signal(signal)) {</div><div class='ctx'> 		set_avi_info_frame(&amp;info-&gt;avi, pipe_ctx);</div><div class='hunk'>@@ -4314,7 +4919,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		set_adaptive_sync_info_packet(&amp;info-&gt;adaptive_sync,</div><div class='ctx'> 										pipe_ctx-&gt;stream,</div><div class='ctx'> 										info,</div><div class='del'>-										&amp;pipe_ctx-&gt;pipe_dlg_param);</div><div class='add'>+										vstartup_start);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	patch_gamut_packet_checksum(&amp;info-&gt;gamut);</div><div class='hunk'>@@ -4408,7 +5013,10 @@ bool pipe_need_reprogram(</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/* DIG link encoder resource assignment for stream changed. */</div><div class='del'>-	if (pipe_ctx_old-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign) {</div><div class='add'>+	if (pipe_ctx_old-&gt;stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment) {</div><div class='add'>+		if (pipe_ctx_old-&gt;link_res.dio_link_enc != pipe_ctx-&gt;link_res.dio_link_enc)</div><div class='add'>+			return true;</div><div class='add'>+	} else if (pipe_ctx_old-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign) {</div><div class='ctx'> 		bool need_reprogram = false;</div><div class='ctx'> 		struct dc *dc = pipe_ctx_old-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 		struct link_encoder *link_enc_prev =</div><div class='hunk'>@@ -4553,6 +5161,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,</div><div class='ctx'> </div><div class='ctx'> enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='add'>+	if (dc == NULL || stream == NULL)</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='ctx'> 	struct timing_generator *tg = dc-&gt;res_pool-&gt;timing_generators[0];</div><div class='ctx'> 	enum dc_status res = DC_OK;</div><div class='hunk'>@@ -4671,6 +5282,28 @@ void get_audio_check(struct audio_info *aud_modes,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+struct link_encoder *get_temp_dio_link_enc(</div><div class='add'>+		const struct resource_context *res_ctx,</div><div class='add'>+		const struct resource_pool *const pool,</div><div class='add'>+		const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	struct link_encoder *link_enc = NULL;</div><div class='add'>+	int enc_index;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;is_dig_mapping_flexible)</div><div class='add'>+		enc_index = find_acquired_dio_link_enc_for_link(res_ctx, link);</div><div class='add'>+	else</div><div class='add'>+		enc_index = link-&gt;eng_id;</div><div class='add'>+</div><div class='add'>+	if (enc_index &lt; 0)</div><div class='add'>+		enc_index = find_free_dio_link_enc(res_ctx, link, pool, NULL);</div><div class='add'>+</div><div class='add'>+	if (enc_index &gt;= 0)</div><div class='add'>+		link_enc = pool-&gt;link_encoders[enc_index];</div><div class='add'>+</div><div class='add'>+	return link_enc;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(</div><div class='ctx'> 		const struct resource_context *res_ctx,</div><div class='ctx'> 		const struct resource_pool *const pool,</div><div class='hunk'>@@ -4700,11 +5333,17 @@ bool get_temp_dp_link_res(struct dc_link *link,</div><div class='ctx'> 	memset(link_res, 0, sizeof(*link_res));</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;link_srv-&gt;dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {</div><div class='del'>-		link_res-&gt;hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,</div><div class='del'>-				dc-&gt;res_pool, link);</div><div class='add'>+		link_res-&gt;hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx, dc-&gt;res_pool, link);</div><div class='ctx'> 		if (!link_res-&gt;hpo_dp_link_enc)</div><div class='ctx'> 			return false;</div><div class='add'>+	} else if (dc-&gt;link_srv-&gt;dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &amp;&amp;</div><div class='add'>+				dc-&gt;config.unify_link_enc_assignment) {</div><div class='add'>+		link_res-&gt;dio_link_enc = get_temp_dio_link_enc(res_ctx,</div><div class='add'>+				dc-&gt;res_pool, link);</div><div class='add'>+		if (!link_res-&gt;dio_link_enc)</div><div class='add'>+			return false;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4927,7 +5566,7 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(</div><div class='ctx'> 			sec_pipe-&gt;stream_res.opp = sec_pipe-&gt;top_pipe-&gt;stream_res.opp;</div><div class='ctx'> 		if (sec_pipe-&gt;stream-&gt;timing.flags.DSC == 1) {</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='del'>-			dcn20_acquire_dsc(dc, &amp;state-&gt;res_ctx, &amp;sec_pipe-&gt;stream_res.dsc, pipe_idx);</div><div class='add'>+			dcn20_acquire_dsc(dc, &amp;state-&gt;res_ctx, &amp;sec_pipe-&gt;stream_res.dsc, sec_pipe-&gt;stream_res.opp-&gt;inst);</div><div class='ctx'> #endif</div><div class='ctx'> 			ASSERT(sec_pipe-&gt;stream_res.dsc);</div><div class='ctx'> 			if (sec_pipe-&gt;stream_res.dsc == NULL)</div><div class='hunk'>@@ -4976,19 +5615,101 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,</div><div class='ctx'> 			remove_hpo_dp_link_enc_from_ctx(&amp;context-&gt;res_ctx, pipe_ctx, pipe_ctx-&gt;stream);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (pipe_ctx-&gt;link_res.dio_link_enc == NULL &amp;&amp; dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		if (!add_dio_link_enc_to_ctx(dc, context, dc-&gt;res_pool, pipe_ctx, pipe_ctx-&gt;stream))</div><div class='add'>+			return DC_NO_LINK_ENC_RESOURCE;</div><div class='add'>+</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream)</div><div class='add'>+struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='del'>-	if (!dc-&gt;debug.disable_subvp_high_refresh &amp;&amp; is_subvp_high_refresh_candidate(stream))</div><div class='del'>-		return true;</div><div class='del'>-	if (dc-&gt;current_state-&gt;stream_count == 1 &amp;&amp; stream-&gt;timing.v_addressable &gt;= 2880 &amp;&amp;</div><div class='del'>-			((stream-&gt;timing.pix_clk_100hz * 100) / stream-&gt;timing.v_total / stream-&gt;timing.h_total) &lt; 120)</div><div class='del'>-		return true;</div><div class='del'>-	else if (dc-&gt;current_state-&gt;stream_count &gt; 1 &amp;&amp; stream-&gt;timing.v_addressable &gt;= 1080 &amp;&amp;</div><div class='del'>-			((stream-&gt;timing.pix_clk_100hz * 100) / stream-&gt;timing.v_total / stream-&gt;timing.h_total) &lt; 120)</div><div class='del'>-		return true;</div><div class='add'>+	return &amp;pipe_ctx-&gt;plane_res.scl_data.dscl_prog_data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool resource_allocate_mcache(struct dc_state *context, const struct  dc_mcache_params *mcache_params)</div><div class='add'>+{</div><div class='add'>+	if (context-&gt;clk_mgr-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;program_mcache_pipe_config)</div><div class='add'>+		context-&gt;clk_mgr-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;program_mcache_pipe_config(context, mcache_params);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options)</div><div class='add'>+{</div><div class='add'>+	dml2_options-&gt;callbacks.dc = dc;</div><div class='add'>+	dml2_options-&gt;callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='add'>+	dml2_options-&gt;callbacks.build_test_pattern_params = &amp;resource_build_test_pattern_params;</div><div class='add'>+	dml2_options-&gt;callbacks.acquire_secondary_pipe_for_mpc_odm = &amp;dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;</div><div class='add'>+	dml2_options-&gt;callbacks.update_pipes_for_stream_with_slice_count = &amp;resource_update_pipes_for_stream_with_slice_count;</div><div class='add'>+	dml2_options-&gt;callbacks.update_pipes_for_plane_with_slice_count = &amp;resource_update_pipes_for_plane_with_slice_count;</div><div class='add'>+	dml2_options-&gt;callbacks.get_mpc_slice_index = &amp;resource_get_mpc_slice_index;</div><div class='add'>+	dml2_options-&gt;callbacks.get_mpc_slice_count = &amp;resource_get_mpc_slice_count;</div><div class='add'>+	dml2_options-&gt;callbacks.get_odm_slice_index = &amp;resource_get_odm_slice_index;</div><div class='add'>+	dml2_options-&gt;callbacks.get_odm_slice_count = &amp;resource_get_odm_slice_count;</div><div class='add'>+	dml2_options-&gt;callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='add'>+	dml2_options-&gt;callbacks.get_otg_master_for_stream = &amp;resource_get_otg_master_for_stream;</div><div class='add'>+	dml2_options-&gt;callbacks.get_opp_heads_for_otg_master = &amp;resource_get_opp_heads_for_otg_master;</div><div class='add'>+	dml2_options-&gt;callbacks.get_dpp_pipes_for_plane = &amp;resource_get_dpp_pipes_for_plane;</div><div class='add'>+	dml2_options-&gt;callbacks.get_stream_status = &amp;dc_state_get_stream_status;</div><div class='add'>+	dml2_options-&gt;callbacks.get_stream_from_id = &amp;dc_state_get_stream_from_id;</div><div class='add'>+	dml2_options-&gt;callbacks.get_max_flickerless_instant_vtotal_increase = &amp;dc_stream_get_max_flickerless_instant_vtotal_increase;</div><div class='add'>+	dml2_options-&gt;callbacks.allocate_mcache = &amp;resource_allocate_mcache;</div><div class='add'>+</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.dc = dc;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.add_phantom_plane = &amp;dc_state_add_phantom_plane;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.add_phantom_stream = &amp;dc_state_add_phantom_stream;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.create_phantom_plane = &amp;dc_state_create_phantom_plane;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.remove_phantom_plane = &amp;dc_state_remove_phantom_plane;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.remove_phantom_stream = &amp;dc_state_remove_phantom_stream;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.create_phantom_stream = &amp;dc_state_create_phantom_stream;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.release_phantom_plane = &amp;dc_state_release_phantom_plane;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.release_phantom_stream = &amp;dc_state_release_phantom_stream;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.get_pipe_subvp_type = &amp;dc_state_get_pipe_subvp_type;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.get_stream_subvp_type = &amp;dc_state_get_stream_subvp_type;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.get_paired_subvp_stream = &amp;dc_state_get_paired_subvp_stream;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.remove_phantom_streams_and_planes = &amp;dc_state_remove_phantom_streams_and_planes;</div><div class='add'>+	dml2_options-&gt;svp_pstate.callbacks.release_phantom_streams_and_planes = &amp;dc_state_release_phantom_streams_and_planes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Returns number of DET segments allocated for a given OTG_MASTER pipe */</div><div class='add'>+int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='add'>+	struct pipe_ctx *dpp_pipes[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	int dpp_count = 0;</div><div class='add'>+	int det_segments = 0;</div><div class='add'>+</div><div class='add'>+	if (!otg_master-&gt;stream)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	int slice_count = resource_get_opp_heads_for_otg_master(otg_master,</div><div class='add'>+			&amp;state-&gt;res_ctx, opp_heads);</div><div class='add'>+</div><div class='add'>+	for (int slice_idx = 0; slice_idx &lt; slice_count; slice_idx++) {</div><div class='add'>+		if (opp_heads[slice_idx]-&gt;plane_state) {</div><div class='add'>+			dpp_count = resource_get_dpp_pipes_for_opp_head(</div><div class='add'>+					opp_heads[slice_idx],</div><div class='add'>+					&amp;state-&gt;res_ctx,</div><div class='add'>+					dpp_pipes);</div><div class='add'>+			for (int dpp_idx = 0; dpp_idx &lt; dpp_count; dpp_idx++)</div><div class='add'>+				det_segments += dpp_pipes[dpp_idx]-&gt;hubp_regs.det_size;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return det_segments;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool resource_is_hpo_acquired(struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_HPO_DP2_ENCODERS; i++) {</div><div class='add'>+		if (context-&gt;res_ctx.is_hpo_dp_stream_enc_acquired[i]) {</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c<br/>index 5f6392ae31a6..f976ffd6d466 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_stat.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_stat.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_stat.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_stat.c</a></div><div class='hunk'>@@ -61,10 +61,11 @@ void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification</div><div class='ctx'> 	/* For HPD/HPD RX, convert dpia port index into link index */</div><div class='ctx'> 	if (notify-&gt;type == DMUB_NOTIFICATION_HPD ||</div><div class='ctx'> 	    notify-&gt;type == DMUB_NOTIFICATION_HPD_IRQ ||</div><div class='del'>-		notify-&gt;type == DMUB_NOTIFICATION_DPIA_NOTIFICATION ||</div><div class='add'>+	    notify-&gt;type == DMUB_NOTIFICATION_AUX_REPLY ||</div><div class='add'>+	    notify-&gt;type == DMUB_NOTIFICATION_DPIA_NOTIFICATION ||</div><div class='ctx'> 	    notify-&gt;type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) {</div><div class='ctx'> 		notify-&gt;link_index =</div><div class='del'>-			get_link_index_from_dpia_port_index(dc, notify-&gt;link_index);</div><div class='add'>+			get_link_index_from_dpia_port_index(dc, notify-&gt;instance);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c<br/>index 5cc7f8da209c..2de8ef4a58ec 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_state.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_state.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_state.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_state.c</a></div><div class='hunk'>@@ -22,6 +22,7 @@</div><div class='ctx'>  * Authors: AMD</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='add'>+#include "dc_types.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "core_status.h"</div><div class='ctx'> #include "dc_state.h"</div><div class='hunk'>@@ -33,8 +34,10 @@</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> </div><div class='del'>-#include "dml2/dml2_wrapper.h"</div><div class='del'>-#include "dml2/dml2_internal_types.h"</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='add'>+#include "dml2_0/dml2_internal_types.h"</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dc-&gt;ctx-&gt;logger</div><div class='hunk'>@@ -188,20 +191,31 @@ static void init_state(struct dc *dc, struct dc_state *state)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Public dc_state functions */</div><div class='del'>-struct dc_state *dc_state_create(struct dc *dc)</div><div class='add'>+struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params)</div><div class='ctx'> {</div><div class='del'>-	struct dc_state *state = kvzalloc(sizeof(struct dc_state),</div><div class='del'>-			GFP_KERNEL);</div><div class='add'>+	struct dc_state *state;</div><div class='add'>+</div><div class='add'>+	state = kvzalloc(sizeof(struct dc_state), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!state)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	init_state(dc, state);</div><div class='ctx'> 	dc_state_construct(dc, state);</div><div class='add'>+	state-&gt;power_source = params ? params-&gt;power_source : DC_POWER_SOURCE_AC;</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	if (dc-&gt;debug.using_dml2)</div><div class='del'>-		dml2_create(dc, &amp;dc-&gt;dml2_options, &amp;state-&gt;bw_ctx.dml2);</div><div class='add'>+	if (dc-&gt;debug.using_dml2) {</div><div class='add'>+		if (!dml2_create(dc, &amp;dc-&gt;dml2_options, &amp;state-&gt;bw_ctx.dml2)) {</div><div class='add'>+			dc_state_release(state);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;caps.dcmode_power_limits_present &amp;&amp; !dml2_create(dc, &amp;dc-&gt;dml2_dc_power_options, &amp;state-&gt;bw_ctx.dml2_dc_power_source)) {</div><div class='add'>+			dc_state_release(state);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	kref_init(&amp;state-&gt;refcount);</div><div class='hunk'>@@ -214,6 +228,7 @@ void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state)</div><div class='ctx'> 	struct kref refcount = dst_state-&gt;refcount;</div><div class='ctx'> #ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> 	struct dml2_context *dst_dml2 = dst_state-&gt;bw_ctx.dml2;</div><div class='add'>+	struct dml2_context *dst_dml2_dc_power_source = dst_state-&gt;bw_ctx.dml2_dc_power_source;</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	dc_state_copy_internal(dst_state, src_state);</div><div class='hunk'>@@ -222,6 +237,10 @@ void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state)</div><div class='ctx'> 	dst_state-&gt;bw_ctx.dml2 = dst_dml2;</div><div class='ctx'> 	if (src_state-&gt;bw_ctx.dml2)</div><div class='ctx'> 		dml2_copy(dst_state-&gt;bw_ctx.dml2, src_state-&gt;bw_ctx.dml2);</div><div class='add'>+</div><div class='add'>+	dst_state-&gt;bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source;</div><div class='add'>+	if (src_state-&gt;bw_ctx.dml2_dc_power_source)</div><div class='add'>+		dml2_copy(dst_state-&gt;bw_ctx.dml2_dc_power_source, src_state-&gt;bw_ctx.dml2_dc_power_source);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	/* context refcount should not be overridden */</div><div class='hunk'>@@ -240,11 +259,20 @@ struct dc_state *dc_state_create_copy(struct dc_state *src_state)</div><div class='ctx'> 	dc_state_copy_internal(new_state, src_state);</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	new_state-&gt;bw_ctx.dml2 = NULL;</div><div class='add'>+	new_state-&gt;bw_ctx.dml2_dc_power_source = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (src_state-&gt;bw_ctx.dml2 &amp;&amp;</div><div class='ctx'> 			!dml2_create_copy(&amp;new_state-&gt;bw_ctx.dml2, src_state-&gt;bw_ctx.dml2)) {</div><div class='ctx'> 		dc_state_release(new_state);</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (src_state-&gt;bw_ctx.dml2_dc_power_source &amp;&amp;</div><div class='add'>+			!dml2_create_copy(&amp;new_state-&gt;bw_ctx.dml2_dc_power_source, src_state-&gt;bw_ctx.dml2_dc_power_source)) {</div><div class='add'>+		dc_state_release(new_state);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	kref_init(&amp;new_state-&gt;refcount);</div><div class='hunk'>@@ -310,7 +338,6 @@ void dc_state_destruct(struct dc_state *state)</div><div class='ctx'> 	memset(state-&gt;dc_dmub_cmd, 0, sizeof(state-&gt;dc_dmub_cmd));</div><div class='ctx'> 	state-&gt;dmub_cmd_count = 0;</div><div class='ctx'> 	memset(&amp;state-&gt;perf_params, 0, sizeof(state-&gt;perf_params));</div><div class='del'>-	memset(&amp;state-&gt;scratch, 0, sizeof(state-&gt;scratch));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_state_retain(struct dc_state *state)</div><div class='hunk'>@@ -327,6 +354,9 @@ static void dc_state_free(struct kref *kref)</div><div class='ctx'> #ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> 	dml2_destroy(state-&gt;bw_ctx.dml2);</div><div class='ctx'> 	state-&gt;bw_ctx.dml2 = 0;</div><div class='add'>+</div><div class='add'>+	dml2_destroy(state-&gt;bw_ctx.dml2_dc_power_source);</div><div class='add'>+	state-&gt;bw_ctx.dml2_dc_power_source = 0;</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	kvfree(state);</div><div class='hunk'>@@ -341,7 +371,7 @@ void dc_state_release(struct dc_state *state)</div><div class='ctx'>  * dc_state_add_stream() - Add a new dc_stream_state to a dc_state.</div><div class='ctx'>  */</div><div class='ctx'> enum dc_status dc_state_add_stream(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+		const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='hunk'>@@ -370,7 +400,7 @@ enum dc_status dc_state_add_stream(</div><div class='ctx'>  * dc_state_remove_stream() - Remove a stream from a dc_state.</div><div class='ctx'>  */</div><div class='ctx'> enum dc_status dc_state_remove_stream(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+		const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='hunk'>@@ -397,6 +427,8 @@ enum dc_status dc_state_remove_stream(</div><div class='ctx'> 		return DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	dc_stream_release_3dlut_for_stream(dc, stream);</div><div class='add'>+</div><div class='ctx'> 	dc_stream_release(state-&gt;streams[i]);</div><div class='ctx'> 	state-&gt;stream_count--;</div><div class='ctx'> </div><div class='hunk'>@@ -415,6 +447,19 @@ enum dc_status dc_state_remove_stream(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void remove_mpc_combine_for_stream(const struct dc *dc,</div><div class='add'>+		struct dc_state *new_ctx,</div><div class='add'>+		const struct dc_state *cur_ctx,</div><div class='add'>+		struct dc_stream_status *status)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; status-&gt;plane_count; i++)</div><div class='add'>+		resource_update_pipes_for_plane_with_slice_count(</div><div class='add'>+				new_ctx, cur_ctx, dc-&gt;res_pool,</div><div class='add'>+				status-&gt;plane_states[i], 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dc_state_add_plane(</div><div class='ctx'> 		const struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='hunk'>@@ -425,22 +470,52 @@ bool dc_state_add_plane(</div><div class='ctx'> 	struct pipe_ctx *otg_master_pipe;</div><div class='ctx'> 	struct dc_stream_status *stream_status = NULL;</div><div class='ctx'> 	bool added = false;</div><div class='add'>+	int odm_slice_count;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+	otg_master_pipe = resource_get_otg_master_for_stream(</div><div class='add'>+			&amp;state-&gt;res_ctx, stream);</div><div class='ctx'> 	if (stream_status == NULL) {</div><div class='ctx'> 		dm_error("Existing stream not found; failed to attach surface!\n");</div><div class='ctx'> 		goto out;</div><div class='del'>-	} else if (stream_status-&gt;plane_count == MAX_SURFACE_NUM) {</div><div class='add'>+	} else if (stream_status-&gt;plane_count == MAX_SURFACES) {</div><div class='ctx'> 		dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",</div><div class='del'>-				plane_state, MAX_SURFACE_NUM);</div><div class='add'>+				plane_state, MAX_SURFACES);</div><div class='add'>+		goto out;</div><div class='add'>+	} else if (!otg_master_pipe) {</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	otg_master_pipe = resource_get_otg_master_for_stream(</div><div class='del'>-			&amp;state-&gt;res_ctx, stream);</div><div class='del'>-	if (otg_master_pipe)</div><div class='add'>+	added = resource_append_dpp_pipes_for_plane_composition(state,</div><div class='add'>+			dc-&gt;current_state, pool, otg_master_pipe, plane_state);</div><div class='add'>+</div><div class='add'>+	if (!added) {</div><div class='add'>+		/* try to remove MPC combine to free up pipes */</div><div class='add'>+		for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+			remove_mpc_combine_for_stream(dc, state,</div><div class='add'>+					dc-&gt;current_state,</div><div class='add'>+					&amp;state-&gt;stream_status[i]);</div><div class='ctx'> 		added = resource_append_dpp_pipes_for_plane_composition(state,</div><div class='del'>-				dc-&gt;current_state, pool, otg_master_pipe, plane_state);</div><div class='add'>+					dc-&gt;current_state, pool,</div><div class='add'>+					otg_master_pipe, plane_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!added) {</div><div class='add'>+		/* try to decrease ODM slice count gradually to free up pipes */</div><div class='add'>+		odm_slice_count = resource_get_odm_slice_count(otg_master_pipe);</div><div class='add'>+		for (i = odm_slice_count - 1; i &gt; 0; i--) {</div><div class='add'>+			resource_update_pipes_for_stream_with_slice_count(state,</div><div class='add'>+					dc-&gt;current_state, dc-&gt;res_pool, stream,</div><div class='add'>+					i);</div><div class='add'>+			added = resource_append_dpp_pipes_for_plane_composition(</div><div class='add'>+					state,</div><div class='add'>+					dc-&gt;current_state, pool,</div><div class='add'>+					otg_master_pipe, plane_state);</div><div class='add'>+			if (added)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (added) {</div><div class='ctx'> 		stream_status-&gt;plane_states[stream_status-&gt;plane_count] =</div><div class='hunk'>@@ -500,15 +575,6 @@ bool dc_state_remove_plane(</div><div class='ctx'> </div><div class='ctx'> 	stream_status-&gt;plane_states[stream_status-&gt;plane_count] = NULL;</div><div class='ctx'> </div><div class='del'>-	if (stream_status-&gt;plane_count == 0 &amp;&amp; dc-&gt;config.enable_windowed_mpo_odm)</div><div class='del'>-		/* ODM combine could prevent us from supporting more planes</div><div class='del'>-		 * we will reset ODM slice count back to 1 when all planes have</div><div class='del'>-		 * been removed to maximize the amount of planes supported when</div><div class='del'>-		 * new planes are added.</div><div class='del'>-		 */</div><div class='del'>-		resource_update_pipes_for_stream_with_slice_count(</div><div class='del'>-				state, dc-&gt;current_state, dc-&gt;res_pool, stream, 1);</div><div class='del'>-</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -530,7 +596,7 @@ bool dc_state_rem_all_planes_for_stream(</div><div class='ctx'> {</div><div class='ctx'> 	int i, old_plane_count;</div><div class='ctx'> 	struct dc_stream_status *stream_status = NULL;</div><div class='del'>-	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };</div><div class='add'>+	struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='ctx'> 		if (state-&gt;streams[i] == stream) {</div><div class='hunk'>@@ -586,7 +652,7 @@ bool dc_state_add_all_planes_for_stream(</div><div class='ctx'>  */</div><div class='ctx'> struct dc_stream_status *dc_state_get_stream_status(</div><div class='ctx'> 		struct dc_state *state,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t i;</div><div class='ctx'> </div><div class='hunk'>@@ -680,7 +746,7 @@ void dc_state_release_phantom_stream(const struct dc *dc,</div><div class='ctx'> 	dc_stream_release(phantom_stream);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dc_plane_state *dc_state_create_phantom_plane(struct dc *dc,</div><div class='add'>+struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_plane_state *main_plane)</div><div class='ctx'> {</div><div class='hunk'>@@ -716,7 +782,7 @@ void dc_state_release_phantom_plane(const struct dc *dc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* add phantom streams to context and generate correct meta inside dc_state */</div><div class='del'>-enum dc_status dc_state_add_phantom_stream(struct dc *dc,</div><div class='add'>+enum dc_status dc_state_add_phantom_stream(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *phantom_stream,</div><div class='ctx'> 		struct dc_stream_state *main_stream)</div><div class='hunk'>@@ -733,27 +799,39 @@ enum dc_status dc_state_add_phantom_stream(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	/* setup subvp meta */</div><div class='ctx'> 	main_stream_status = dc_state_get_stream_status(state, main_stream);</div><div class='add'>+	if (main_stream_status) {</div><div class='add'>+		main_stream_status-&gt;mall_stream_config.type = SUBVP_MAIN;</div><div class='add'>+		main_stream_status-&gt;mall_stream_config.paired_stream = phantom_stream;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	phantom_stream_status = dc_state_get_stream_status(state, phantom_stream);</div><div class='del'>-	phantom_stream_status-&gt;mall_stream_config.type = SUBVP_PHANTOM;</div><div class='del'>-	phantom_stream_status-&gt;mall_stream_config.paired_stream = main_stream;</div><div class='del'>-	main_stream_status-&gt;mall_stream_config.type = SUBVP_MAIN;</div><div class='del'>-	main_stream_status-&gt;mall_stream_config.paired_stream = phantom_stream;</div><div class='add'>+	if (phantom_stream_status) {</div><div class='add'>+		phantom_stream_status-&gt;mall_stream_config.type = SUBVP_PHANTOM;</div><div class='add'>+		phantom_stream_status-&gt;mall_stream_config.paired_stream = main_stream;</div><div class='add'>+		phantom_stream_status-&gt;mall_stream_config.subvp_limit_cursor_size = false;</div><div class='add'>+		phantom_stream_status-&gt;mall_stream_config.cursor_size_limit_subvp = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_state_set_stream_subvp_cursor_limit(main_stream, state, true);</div><div class='ctx'> </div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum dc_status dc_state_remove_phantom_stream(struct dc *dc,</div><div class='add'>+enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *phantom_stream)</div><div class='ctx'> {</div><div class='del'>-	struct dc_stream_status *main_stream_status;</div><div class='add'>+	struct dc_stream_status *main_stream_status = NULL;</div><div class='ctx'> 	struct dc_stream_status *phantom_stream_status;</div><div class='ctx'> </div><div class='ctx'> 	/* reset subvp meta */</div><div class='ctx'> 	phantom_stream_status = dc_state_get_stream_status(state, phantom_stream);</div><div class='del'>-	main_stream_status = dc_state_get_stream_status(state, phantom_stream_status-&gt;mall_stream_config.paired_stream);</div><div class='del'>-	phantom_stream_status-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='del'>-	phantom_stream_status-&gt;mall_stream_config.paired_stream = NULL;</div><div class='add'>+	if (phantom_stream_status) {</div><div class='add'>+		main_stream_status = dc_state_get_stream_status(state, phantom_stream_status-&gt;mall_stream_config.paired_stream);</div><div class='add'>+		phantom_stream_status-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='add'>+		phantom_stream_status-&gt;mall_stream_config.paired_stream = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (main_stream_status) {</div><div class='ctx'> 		main_stream_status-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='ctx'> 		main_stream_status-&gt;mall_stream_config.paired_stream = NULL;</div><div class='hunk'>@@ -797,7 +875,7 @@ bool dc_state_rem_all_phantom_planes_for_stream(</div><div class='ctx'> {</div><div class='ctx'> 	int i, old_plane_count;</div><div class='ctx'> 	struct dc_stream_status *stream_status = NULL;</div><div class='del'>-	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };</div><div class='add'>+	struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='ctx'> 		if (state-&gt;streams[i] == phantom_stream) {</div><div class='hunk'>@@ -836,7 +914,7 @@ bool dc_state_add_all_phantom_planes_for_stream(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_state_remove_phantom_streams_and_planes(</div><div class='del'>-	struct dc *dc,</div><div class='add'>+	const struct dc *dc,</div><div class='ctx'> 	struct dc_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -858,14 +936,142 @@ bool dc_state_remove_phantom_streams_and_planes(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_state_release_phantom_streams_and_planes(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+		const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state)</div><div class='ctx'> {</div><div class='add'>+	unsigned int phantom_count;</div><div class='add'>+	struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES];</div><div class='add'>+	struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES];</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; state-&gt;phantom_stream_count; i++)</div><div class='del'>-		dc_state_release_phantom_stream(dc, state, state-&gt;phantom_streams[i]);</div><div class='add'>+	phantom_count = state-&gt;phantom_stream_count;</div><div class='add'>+	memcpy(phantom_streams, state-&gt;phantom_streams, sizeof(struct dc_stream_state *) * MAX_PHANTOM_PIPES);</div><div class='add'>+	for (i = 0; i &lt; phantom_count; i++)</div><div class='add'>+		dc_state_release_phantom_stream(dc, state, phantom_streams[i]);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; state-&gt;phantom_plane_count; i++)</div><div class='del'>-		dc_state_release_phantom_plane(dc, state, state-&gt;phantom_planes[i]);</div><div class='add'>+	phantom_count = state-&gt;phantom_plane_count;</div><div class='add'>+	memcpy(phantom_planes, state-&gt;phantom_planes, sizeof(struct dc_plane_state *) * MAX_PHANTOM_PIPES);</div><div class='add'>+	for (i = 0; i &lt; phantom_count; i++)</div><div class='add'>+		dc_state_release_phantom_plane(dc, state, phantom_planes[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dc_stream_state *dc_state_get_stream_from_id(const struct dc_state *state, unsigned int id)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *stream = NULL;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		if (state-&gt;streams[i] &amp;&amp; state-&gt;streams[i]-&gt;stream_id == id) {</div><div class='add'>+			stream = state-&gt;streams[i];</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return stream;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_is_fams2_in_use(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	bool is_fams2_in_use = false;</div><div class='add'>+</div><div class='add'>+	if (state)</div><div class='add'>+		is_fams2_in_use |= state-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;current_state)</div><div class='add'>+		is_fams2_in_use |= dc-&gt;current_state-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;</div><div class='add'>+</div><div class='add'>+	return is_fams2_in_use;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_set_stream_subvp_cursor_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		bool limit)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_status *stream_status;</div><div class='add'>+</div><div class='add'>+	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+</div><div class='add'>+	if (stream_status) {</div><div class='add'>+		stream_status-&gt;mall_stream_config.subvp_limit_cursor_size = limit;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_get_stream_subvp_cursor_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	bool limit = false;</div><div class='add'>+</div><div class='add'>+	struct dc_stream_status *stream_status;</div><div class='add'>+</div><div class='add'>+	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+</div><div class='add'>+	if (stream_status) {</div><div class='add'>+		limit = stream_status-&gt;mall_stream_config.subvp_limit_cursor_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return limit;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_set_stream_cursor_subvp_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		bool limit)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_status *stream_status;</div><div class='add'>+</div><div class='add'>+	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+</div><div class='add'>+	if (stream_status) {</div><div class='add'>+		stream_status-&gt;mall_stream_config.cursor_size_limit_subvp = limit;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_get_stream_cursor_subvp_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	bool limit = false;</div><div class='add'>+</div><div class='add'>+	struct dc_stream_status *stream_status;</div><div class='add'>+</div><div class='add'>+	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+</div><div class='add'>+	if (stream_status) {</div><div class='add'>+		limit = stream_status-&gt;mall_stream_config.cursor_size_limit_subvp;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return limit;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_can_clear_stream_cursor_subvp_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	bool can_clear_limit = false;</div><div class='add'>+</div><div class='add'>+	struct dc_stream_status *stream_status;</div><div class='add'>+</div><div class='add'>+	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+</div><div class='add'>+	if (stream_status) {</div><div class='add'>+		can_clear_limit = dc_state_get_stream_cursor_subvp_limit(stream, state) &amp;&amp;</div><div class='add'>+				(stream_status-&gt;mall_stream_config.type == SUBVP_PHANTOM ||</div><div class='add'>+				stream-&gt;hw_cursor_req ||</div><div class='add'>+				!stream_status-&gt;mall_stream_config.subvp_limit_cursor_size ||</div><div class='add'>+				!stream-&gt;cursor_position.enable ||</div><div class='add'>+				dc_stream_check_cursor_attributes(stream, state, &amp;stream-&gt;cursor_attributes));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return can_clear_limit;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_is_subvp_in_use(struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		if (dc_state_get_stream_subvp_type(state, state-&gt;streams[i]) != SUBVP_NONE)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c<br/>index 51a970fcb5d0..129cd5f84983 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_stream.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_stream.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_stream.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_stream.c</a></div><div class='hunk'>@@ -35,6 +35,12 @@</div><div class='ctx'> #include "dc_stream_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER dc-&gt;ctx-&gt;logger</div><div class='add'>+#ifndef MIN</div><div class='add'>+#define MIN(X, Y) ((X) &lt; (Y) ? (X) : (Y))</div><div class='add'>+#endif</div><div class='add'>+#ifndef MAX</div><div class='add'>+#define MAX(x, y) ((x &gt; y) ? x : y)</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> /*******************************************************************************</div><div class='ctx'>  * Private functions</div><div class='hunk'>@@ -116,12 +122,7 @@ bool dc_stream_construct(struct dc_stream_state *stream,</div><div class='ctx'> </div><div class='ctx'> 	update_stream_signal(stream, dc_sink_data);</div><div class='ctx'> </div><div class='del'>-	stream-&gt;out_transfer_func = dc_create_transfer_func();</div><div class='del'>-	if (stream-&gt;out_transfer_func == NULL) {</div><div class='del'>-		dc_sink_release(dc_sink_data);</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-	stream-&gt;out_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+	stream-&gt;out_transfer_func.type = TF_TYPE_BYPASS;</div><div class='ctx'> </div><div class='ctx'> 	dc_stream_assign_stream_id(stream);</div><div class='ctx'> </div><div class='hunk'>@@ -131,10 +132,6 @@ bool dc_stream_construct(struct dc_stream_state *stream,</div><div class='ctx'> void dc_stream_destruct(struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	dc_sink_release(stream-&gt;sink);</div><div class='del'>-	if (stream-&gt;out_transfer_func != NULL) {</div><div class='del'>-		dc_transfer_func_release(stream-&gt;out_transfer_func);</div><div class='del'>-		stream-&gt;out_transfer_func = NULL;</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_stream_assign_stream_id(struct dc_stream_state *stream)</div><div class='hunk'>@@ -201,13 +198,11 @@ struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)</div><div class='ctx'> 	if (new_stream-&gt;sink)</div><div class='ctx'> 		dc_sink_retain(new_stream-&gt;sink);</div><div class='ctx'> </div><div class='del'>-	if (new_stream-&gt;out_transfer_func)</div><div class='del'>-		dc_transfer_func_retain(new_stream-&gt;out_transfer_func);</div><div class='del'>-</div><div class='ctx'> 	dc_stream_assign_stream_id(new_stream);</div><div class='ctx'> </div><div class='ctx'> 	/* If using dynamic encoder assignment, wait till stream committed to assign encoder. */</div><div class='del'>-	if (new_stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign)</div><div class='add'>+	if (new_stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign &amp;&amp;</div><div class='add'>+			!new_stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='ctx'> 		new_stream-&gt;link_enc = NULL;</div><div class='ctx'> </div><div class='ctx'> 	kref_init(&amp;new_stream-&gt;refcount);</div><div class='hunk'>@@ -229,14 +224,22 @@ struct dc_stream_status *dc_stream_get_status(</div><div class='ctx'> 	return dc_state_get_stream_status(dc-&gt;current_state, stream);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void program_cursor_attributes(</div><div class='add'>+const struct dc_stream_status *dc_stream_get_status_const(</div><div class='add'>+	const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = stream-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	return dc_state_get_stream_status(dc-&gt;current_state, stream);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void program_cursor_attributes(</div><div class='ctx'> 	struct dc *dc,</div><div class='del'>-	struct dc_stream_state *stream,</div><div class='del'>-	const struct dc_cursor_attributes *attributes)</div><div class='add'>+	struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct resource_context *res_ctx;</div><div class='ctx'> 	struct pipe_ctx *pipe_to_program = NULL;</div><div class='add'>+	bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);</div><div class='ctx'> </div><div class='ctx'> 	if (!stream)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -251,9 +254,14 @@ static void program_cursor_attributes(</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe_to_program) {</div><div class='ctx'> 			pipe_to_program = pipe_ctx;</div><div class='del'>-			dc-&gt;hwss.cursor_lock(dc, pipe_to_program, true);</div><div class='del'>-			if (pipe_to_program-&gt;next_odm_pipe)</div><div class='del'>-				dc-&gt;hwss.cursor_lock(dc, pipe_to_program-&gt;next_odm_pipe, true);</div><div class='add'>+</div><div class='add'>+			if (enable_cursor_offload &amp;&amp; dc-&gt;hwss.begin_cursor_offload_update) {</div><div class='add'>+				dc-&gt;hwss.begin_cursor_offload_update(dc, pipe_ctx);</div><div class='add'>+			} else {</div><div class='add'>+				dc-&gt;hwss.cursor_lock(dc, pipe_to_program, true);</div><div class='add'>+				if (pipe_to_program-&gt;next_odm_pipe)</div><div class='add'>+					dc-&gt;hwss.cursor_lock(dc, pipe_to_program-&gt;next_odm_pipe, true);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dc-&gt;hwss.set_cursor_attribute(pipe_ctx);</div><div class='hunk'>@@ -261,24 +269,32 @@ static void program_cursor_attributes(</div><div class='ctx'> 			dc_send_update_cursor_info_to_dmu(pipe_ctx, i);</div><div class='ctx'> 		if (dc-&gt;hwss.set_cursor_sdr_white_level)</div><div class='ctx'> 			dc-&gt;hwss.set_cursor_sdr_white_level(pipe_ctx);</div><div class='add'>+		if (enable_cursor_offload &amp;&amp; dc-&gt;hwss.update_cursor_offload_pipe)</div><div class='add'>+			dc-&gt;hwss.update_cursor_offload_pipe(dc, pipe_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_to_program) {</div><div class='del'>-		dc-&gt;hwss.cursor_lock(dc, pipe_to_program, false);</div><div class='del'>-		if (pipe_to_program-&gt;next_odm_pipe)</div><div class='del'>-			dc-&gt;hwss.cursor_lock(dc, pipe_to_program-&gt;next_odm_pipe, false);</div><div class='add'>+		if (enable_cursor_offload &amp;&amp; dc-&gt;hwss.commit_cursor_offload_update) {</div><div class='add'>+			dc-&gt;hwss.commit_cursor_offload_update(dc, pipe_to_program);</div><div class='add'>+		} else {</div><div class='add'>+			dc-&gt;hwss.cursor_lock(dc, pipe_to_program, false);</div><div class='add'>+			if (pipe_to_program-&gt;next_odm_pipe)</div><div class='add'>+				dc-&gt;hwss.cursor_lock(dc, pipe_to_program-&gt;next_odm_pipe, false);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address</div><div class='add'>+ * dc_stream_check_cursor_attributes() - Check validitity of cursor attributes and surface address</div><div class='ctx'>  */</div><div class='del'>-bool dc_stream_set_cursor_attributes(</div><div class='del'>-	struct dc_stream_state *stream,</div><div class='add'>+bool dc_stream_check_cursor_attributes(</div><div class='add'>+	const struct dc_stream_state *stream,</div><div class='add'>+	struct dc_state *state,</div><div class='ctx'> 	const struct dc_cursor_attributes *attributes)</div><div class='ctx'> {</div><div class='del'>-	struct dc  *dc;</div><div class='del'>-	bool reset_idle_optimizations = false;</div><div class='add'>+	const struct dc *dc;</div><div class='add'>+</div><div class='add'>+	unsigned int max_cursor_size;</div><div class='ctx'> </div><div class='ctx'> 	if (NULL == stream) {</div><div class='ctx'> 		dm_error("DC: dc_stream is NULL!\n");</div><div class='hunk'>@@ -296,43 +312,81 @@ bool dc_stream_set_cursor_attributes(</div><div class='ctx'> </div><div class='ctx'> 	dc = stream-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='del'>-	/* SubVP is not compatible with HW cursor larger than 64 x 64 x 4.</div><div class='del'>-	 * Therefore, if cursor is greater than 64 x 64 x 4, fallback to SW cursor in the following case:</div><div class='del'>-	 * 1. If the config is a candidate for SubVP high refresh (both single an dual display configs)</div><div class='del'>-	 * 2. If not subvp high refresh, for single display cases, if resolution is &gt;= 5K and refresh rate &lt; 120hz</div><div class='del'>-	 * 3. If not subvp high refresh, for multi display cases, if resolution is &gt;= 4K and refresh rate &lt; 120hz</div><div class='add'>+	/* SubVP is not compatible with HW cursor larger than what can fit in cursor SRAM.</div><div class='add'>+	 * Therefore, if cursor is greater than this, fallback to SW cursor.</div><div class='ctx'> 	 */</div><div class='del'>-	if (dc-&gt;debug.allow_sw_cursor_fallback &amp;&amp; attributes-&gt;height * attributes-&gt;width * 4 &gt; 16384) {</div><div class='del'>-		if (check_subvp_sw_cursor_fallback_req(dc, stream))</div><div class='add'>+	if (dc-&gt;debug.allow_sw_cursor_fallback &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;get_max_hw_cursor_size) {</div><div class='add'>+		max_cursor_size = dc-&gt;res_pool-&gt;funcs-&gt;get_max_hw_cursor_size(dc, state, stream);</div><div class='add'>+		max_cursor_size = max_cursor_size * max_cursor_size * 4;</div><div class='add'>+</div><div class='add'>+		if (attributes-&gt;height * attributes-&gt;width * 4 &gt; max_cursor_size) {</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	stream-&gt;cursor_attributes = *attributes;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address</div><div class='add'>+ */</div><div class='add'>+bool dc_stream_set_cursor_attributes(</div><div class='add'>+	struct dc_stream_state *stream,</div><div class='add'>+	const struct dc_cursor_attributes *attributes)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (!stream)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	dc_z10_restore(dc);</div><div class='del'>-	/* disable idle optimizations while updating cursor */</div><div class='del'>-	if (dc-&gt;idle_optimizations_allowed) {</div><div class='del'>-		dc_allow_idle_optimizations(dc, false);</div><div class='del'>-		reset_idle_optimizations = true;</div><div class='add'>+	if (dc_stream_check_cursor_attributes(stream, stream-&gt;ctx-&gt;dc-&gt;current_state, attributes)) {</div><div class='add'>+		stream-&gt;cursor_attributes = *attributes;</div><div class='add'>+		result = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	program_cursor_attributes(dc, stream, attributes);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	/* re-enable idle optimizations if necessary */</div><div class='del'>-	if (reset_idle_optimizations)</div><div class='del'>-		dc_allow_idle_optimizations(dc, true);</div><div class='add'>+bool dc_stream_program_cursor_attributes(</div><div class='add'>+	struct dc_stream_state *stream,</div><div class='add'>+	const struct dc_cursor_attributes *attributes)</div><div class='add'>+{</div><div class='add'>+	struct dc  *dc;</div><div class='add'>+	bool reset_idle_optimizations = false;</div><div class='ctx'> </div><div class='del'>-	return true;</div><div class='add'>+	if (!stream)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dc = stream-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (dc_stream_set_cursor_attributes(stream, attributes)) {</div><div class='add'>+		dc_z10_restore(dc);</div><div class='add'>+		/* disable idle optimizations while updating cursor */</div><div class='add'>+		if (dc-&gt;idle_optimizations_allowed) {</div><div class='add'>+			dc_allow_idle_optimizations(dc, false);</div><div class='add'>+			reset_idle_optimizations = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		program_cursor_attributes(dc, stream);</div><div class='add'>+</div><div class='add'>+		/* re-enable idle optimizations if necessary */</div><div class='add'>+		if (reset_idle_optimizations &amp;&amp; !dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='add'>+			dc_allow_idle_optimizations(dc, true);</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void program_cursor_position(</div><div class='add'>+void program_cursor_position(</div><div class='ctx'> 	struct dc *dc,</div><div class='del'>-	struct dc_stream_state *stream,</div><div class='del'>-	const struct dc_cursor_position *position)</div><div class='add'>+	struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct resource_context *res_ctx;</div><div class='ctx'> 	struct pipe_ctx *pipe_to_program = NULL;</div><div class='add'>+	bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);</div><div class='ctx'> </div><div class='ctx'> 	if (!stream)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -351,25 +405,33 @@ static void program_cursor_position(</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe_to_program) {</div><div class='ctx'> 			pipe_to_program = pipe_ctx;</div><div class='del'>-			dc-&gt;hwss.cursor_lock(dc, pipe_to_program, true);</div><div class='add'>+</div><div class='add'>+			if (enable_cursor_offload &amp;&amp; dc-&gt;hwss.begin_cursor_offload_update)</div><div class='add'>+				dc-&gt;hwss.begin_cursor_offload_update(dc, pipe_ctx);</div><div class='add'>+			else</div><div class='add'>+				dc-&gt;hwss.cursor_lock(dc, pipe_to_program, true);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dc-&gt;hwss.set_cursor_position(pipe_ctx);</div><div class='add'>+		if (enable_cursor_offload &amp;&amp; dc-&gt;hwss.update_cursor_offload_pipe)</div><div class='add'>+			dc-&gt;hwss.update_cursor_offload_pipe(dc, pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 		if (dc-&gt;ctx-&gt;dmub_srv)</div><div class='ctx'> 			dc_send_update_cursor_info_to_dmu(pipe_ctx, i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pipe_to_program)</div><div class='del'>-		dc-&gt;hwss.cursor_lock(dc, pipe_to_program, false);</div><div class='add'>+	if (pipe_to_program) {</div><div class='add'>+		if (enable_cursor_offload &amp;&amp; dc-&gt;hwss.commit_cursor_offload_update)</div><div class='add'>+			dc-&gt;hwss.commit_cursor_offload_update(dc, pipe_to_program);</div><div class='add'>+		else</div><div class='add'>+			dc-&gt;hwss.cursor_lock(dc, pipe_to_program, false);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_stream_set_cursor_position(</div><div class='ctx'> 	struct dc_stream_state *stream,</div><div class='ctx'> 	const struct dc_cursor_position *position)</div><div class='ctx'> {</div><div class='del'>-	struct dc *dc;</div><div class='del'>-	bool reset_idle_optimizations = false;</div><div class='del'>-</div><div class='ctx'> 	if (NULL == stream) {</div><div class='ctx'> 		dm_error("DC: dc_stream is NULL!\n");</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -380,24 +442,66 @@ bool dc_stream_set_cursor_position(</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	stream-&gt;cursor_position = *position;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_stream_program_cursor_position(</div><div class='add'>+	struct dc_stream_state *stream,</div><div class='add'>+	const struct dc_cursor_position *position)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	bool reset_idle_optimizations = false;</div><div class='add'>+	const struct dc_cursor_position *old_position;</div><div class='add'>+</div><div class='add'>+	if (!stream)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	old_position = &amp;stream-&gt;cursor_position;</div><div class='ctx'> 	dc = stream-&gt;ctx-&gt;dc;</div><div class='del'>-	dc_z10_restore(dc);</div><div class='ctx'> </div><div class='del'>-	/* disable idle optimizations if enabling cursor */</div><div class='del'>-	if (dc-&gt;idle_optimizations_allowed &amp;&amp; (!stream-&gt;cursor_position.enable || dc-&gt;debug.exit_idle_opt_for_cursor_updates)</div><div class='del'>-			&amp;&amp; position-&gt;enable) {</div><div class='del'>-		dc_allow_idle_optimizations(dc, false);</div><div class='del'>-		reset_idle_optimizations = true;</div><div class='del'>-	}</div><div class='add'>+	if (dc_stream_set_cursor_position(stream, position)) {</div><div class='add'>+		dc_z10_restore(dc);</div><div class='ctx'> </div><div class='del'>-	stream-&gt;cursor_position = *position;</div><div class='add'>+		/* disable idle optimizations if enabling cursor */</div><div class='add'>+		if (dc-&gt;idle_optimizations_allowed &amp;&amp;</div><div class='add'>+		    (!old_position-&gt;enable || dc-&gt;debug.exit_idle_opt_for_cursor_updates) &amp;&amp;</div><div class='add'>+		    position-&gt;enable) {</div><div class='add'>+			dc_allow_idle_optimizations(dc, false);</div><div class='add'>+			reset_idle_optimizations = true;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	program_cursor_position(dc, stream, position);</div><div class='del'>-	/* re-enable idle optimizations if necessary */</div><div class='del'>-	if (reset_idle_optimizations)</div><div class='del'>-		dc_allow_idle_optimizations(dc, true);</div><div class='add'>+		program_cursor_position(dc, stream);</div><div class='add'>+		/* re-enable idle optimizations if necessary */</div><div class='add'>+		if (reset_idle_optimizations &amp;&amp; !dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='add'>+			dc_allow_idle_optimizations(dc, true);</div><div class='ctx'> </div><div class='del'>-	return true;</div><div class='add'>+		/* apply/update visual confirm */</div><div class='add'>+		if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) {</div><div class='add'>+			/* update software state */</div><div class='add'>+			int i;</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+				struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+				/* adjust visual confirm color for all pipes with current stream */</div><div class='add'>+				if (stream == pipe_ctx-&gt;stream) {</div><div class='add'>+					get_cursor_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+</div><div class='add'>+					/* programming hardware */</div><div class='add'>+					if (pipe_ctx-&gt;plane_state)</div><div class='add'>+						dc-&gt;hwss.update_visual_confirm_color(dc, pipe_ctx,</div><div class='add'>+								pipe_ctx-&gt;plane_res.hubp-&gt;mpcc_id);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_stream_add_writeback(struct dc *dc,</div><div class='hunk'>@@ -425,7 +529,7 @@ bool dc_stream_add_writeback(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> </div><div class='del'>-	wb_info-&gt;dwb_params.out_transfer_func = stream-&gt;out_transfer_func;</div><div class='add'>+	wb_info-&gt;dwb_params.out_transfer_func = &amp;stream-&gt;out_transfer_func;</div><div class='ctx'> </div><div class='ctx'> 	dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='ctx'> 	dwb-&gt;dwb_is_drc = false;</div><div class='hunk'>@@ -503,11 +607,19 @@ bool dc_stream_fc_disable_writeback(struct dc *dc,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * dc_stream_remove_writeback() - Disables writeback and removes writeback info.</div><div class='add'>+ * @dc: Display core control structure.</div><div class='add'>+ * @stream: Display core stream state.</div><div class='add'>+ * @dwb_pipe_inst: Display writeback pipe.</div><div class='add'>+ *</div><div class='add'>+ * Return: returns true on success, false otherwise.</div><div class='add'>+ */</div><div class='ctx'> bool dc_stream_remove_writeback(struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		uint32_t dwb_pipe_inst)</div><div class='ctx'> {</div><div class='del'>-	int i = 0, j = 0;</div><div class='add'>+	unsigned int i, j;</div><div class='ctx'> 	if (stream == NULL) {</div><div class='ctx'> 		dm_error("DC: dc_stream is NULL!\n");</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -559,17 +671,6 @@ bool dc_stream_remove_writeback(struct dc *dc,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_stream_warmup_writeback(struct dc *dc,</div><div class='del'>-		int num_dwb,</div><div class='del'>-		struct dc_writeback_info *wb_info)</div><div class='del'>-{</div><div class='del'>-	dc_exit_ips_for_hw_access(dc);</div><div class='del'>-</div><div class='del'>-	if (dc-&gt;hwss.mmhubbub_warmup)</div><div class='del'>-		return dc-&gt;hwss.mmhubbub_warmup(dc, num_dwb, wb_info);</div><div class='del'>-	else</div><div class='del'>-		return false;</div><div class='del'>-}</div><div class='ctx'> uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t i;</div><div class='hunk'>@@ -636,9 +737,14 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t i;</div><div class='ctx'> 	bool ret = false;</div><div class='del'>-	struct dc  *dc = stream-&gt;ctx-&gt;dc;</div><div class='del'>-	struct resource_context *res_ctx =</div><div class='del'>-		&amp;dc-&gt;current_state-&gt;res_ctx;</div><div class='add'>+	struct dc  *dc;</div><div class='add'>+	struct resource_context *res_ctx;</div><div class='add'>+</div><div class='add'>+	if (!stream-&gt;ctx)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dc = stream-&gt;ctx-&gt;dc;</div><div class='add'>+	res_ctx = &amp;dc-&gt;current_state-&gt;res_ctx;</div><div class='ctx'> </div><div class='ctx'> 	dc_exit_ips_for_hw_access(dc);</div><div class='ctx'> </div><div class='hunk'>@@ -766,12 +872,12 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)</div><div class='ctx'> 			stream-&gt;dst.height,</div><div class='ctx'> 			stream-&gt;output_color_space);</div><div class='ctx'> 	DC_LOG_DC(</div><div class='del'>-			"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",</div><div class='add'>+			"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixel_encoding:%s, color_depth:%s\n",</div><div class='ctx'> 			stream-&gt;timing.pix_clk_100hz / 10,</div><div class='ctx'> 			stream-&gt;timing.h_total,</div><div class='ctx'> 			stream-&gt;timing.v_total,</div><div class='del'>-			stream-&gt;timing.pixel_encoding,</div><div class='del'>-			stream-&gt;timing.display_color_depth);</div><div class='add'>+			dc_pixel_encoding_to_str(stream-&gt;timing.pixel_encoding),</div><div class='add'>+			dc_color_depth_to_str(stream-&gt;timing.display_color_depth));</div><div class='ctx'> 	DC_LOG_DC(</div><div class='ctx'> 			"\tlink: %d\n",</div><div class='ctx'> 			stream-&gt;link-&gt;link_index);</div><div class='hunk'>@@ -786,10 +892,380 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)</div><div class='ctx'> 			stream-&gt;sink-&gt;sink_signal != SIGNAL_TYPE_NONE) {</div><div class='ctx'> </div><div class='ctx'> 			DC_LOG_DC(</div><div class='del'>-					"\tdispname: %s signal: %x\n",</div><div class='add'>+					"\tsignal: %x dispname: %s manufacturer_id: 0x%x product_id: 0x%x\n",</div><div class='add'>+					stream-&gt;signal,</div><div class='ctx'> 					stream-&gt;sink-&gt;edid_caps.display_name,</div><div class='del'>-					stream-&gt;signal);</div><div class='add'>+					stream-&gt;sink-&gt;edid_caps.manufacturer_id,</div><div class='add'>+					stream-&gt;sink-&gt;edid_caps.product_id);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+*	dc_stream_get_3dlut()</div><div class='add'>+*	Requirements:</div><div class='add'>+*	1. Is stream already owns an RMCM instance, return it.</div><div class='add'>+*	2. If it doesn't and we don't need to allocate, return NULL.</div><div class='add'>+*	3. If there's a free RMCM instance, assign to stream and return it.</div><div class='add'>+*	4. If no free RMCM instances, return NULL.</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream(</div><div class='add'>+	const struct dc *dc,</div><div class='add'>+	const struct dc_stream_state *stream,</div><div class='add'>+	bool allocate_one)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_rmcm = dc-&gt;caps.color.mpc.num_rmcm_3dluts;</div><div class='add'>+</div><div class='add'>+	// see if one is allocated for this stream</div><div class='add'>+	for (int i = 0; i &lt; num_rmcm; i++) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;rmcm_3dlut[i].isInUse &amp;&amp;</div><div class='add'>+			dc-&gt;res_pool-&gt;rmcm_3dlut[i].stream == stream)</div><div class='add'>+			return &amp;dc-&gt;res_pool-&gt;rmcm_3dlut[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//case: not found one, and dont need to allocate</div><div class='add'>+	if (!allocate_one)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	//see if there is an unused 3dlut, allocate</div><div class='add'>+	for (int i = 0; i &lt; num_rmcm; i++) {</div><div class='add'>+		if (!dc-&gt;res_pool-&gt;rmcm_3dlut[i].isInUse) {</div><div class='add'>+			dc-&gt;res_pool-&gt;rmcm_3dlut[i].isInUse = true;</div><div class='add'>+			dc-&gt;res_pool-&gt;rmcm_3dlut[i].stream = stream;</div><div class='add'>+			return &amp;dc-&gt;res_pool-&gt;rmcm_3dlut[i];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//dont have a 3dlut</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dc_stream_release_3dlut_for_stream(</div><div class='add'>+	const struct dc *dc,</div><div class='add'>+	const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	struct dc_rmcm_3dlut *rmcm_3dlut =</div><div class='add'>+		dc_stream_get_3dlut_for_stream(dc, stream, false);</div><div class='add'>+</div><div class='add'>+	if (rmcm_3dlut) {</div><div class='add'>+		rmcm_3dlut-&gt;isInUse = false;</div><div class='add'>+		rmcm_3dlut-&gt;stream  = NULL;</div><div class='add'>+		rmcm_3dlut-&gt;protection_bits = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dc_stream_init_rmcm_3dlut(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_rmcm = dc-&gt;caps.color.mpc.num_rmcm_3dluts;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; num_rmcm; i++) {</div><div class='add'>+		dc-&gt;res_pool-&gt;rmcm_3dlut[i].isInUse = false;</div><div class='add'>+		dc-&gt;res_pool-&gt;rmcm_3dlut[i].stream = NULL;</div><div class='add'>+		dc-&gt;res_pool-&gt;rmcm_3dlut[i].protection_bits = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds the greatest index in refresh_rate_hz that contains a value &lt;= refresh</div><div class='add'>+ */</div><div class='add'>+static int dc_stream_get_nearest_smallest_index(struct dc_stream_state *stream, int refresh)</div><div class='add'>+{</div><div class='add'>+	for (int i = 0; i &lt; (LUMINANCE_DATA_TABLE_SIZE - 1); ++i) {</div><div class='add'>+		if ((stream-&gt;lumin_data.refresh_rate_hz[i] &lt;= refresh) &amp;&amp; (refresh &lt; stream-&gt;lumin_data.refresh_rate_hz[i + 1])) {</div><div class='add'>+			return i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return 9;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds a corresponding brightness for a given refresh rate between 2 given indices, where index1 &lt; index2</div><div class='add'>+ */</div><div class='add'>+static int dc_stream_get_brightness_millinits_linear_interpolation (struct dc_stream_state *stream,</div><div class='add'>+								     int index1,</div><div class='add'>+								     int index2,</div><div class='add'>+								     int refresh_hz)</div><div class='add'>+{</div><div class='add'>+	long long slope = 0;</div><div class='add'>+	if (stream-&gt;lumin_data.refresh_rate_hz[index2] != stream-&gt;lumin_data.refresh_rate_hz[index1]) {</div><div class='add'>+		slope = (stream-&gt;lumin_data.luminance_millinits[index2] - stream-&gt;lumin_data.luminance_millinits[index1]) /</div><div class='add'>+			    (stream-&gt;lumin_data.refresh_rate_hz[index2] - stream-&gt;lumin_data.refresh_rate_hz[index1]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	int y_intercept = stream-&gt;lumin_data.luminance_millinits[index2] - slope * stream-&gt;lumin_data.refresh_rate_hz[index2];</div><div class='add'>+</div><div class='add'>+	return (y_intercept + refresh_hz * slope);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds a corresponding refresh rate for a given brightness between 2 given indices, where index1 &lt; index2</div><div class='add'>+ */</div><div class='add'>+static int dc_stream_get_refresh_hz_linear_interpolation (struct dc_stream_state *stream,</div><div class='add'>+							   int index1,</div><div class='add'>+							   int index2,</div><div class='add'>+							   int brightness_millinits)</div><div class='add'>+{</div><div class='add'>+	long long slope = 1;</div><div class='add'>+	if (stream-&gt;lumin_data.refresh_rate_hz[index2] != stream-&gt;lumin_data.refresh_rate_hz[index1]) {</div><div class='add'>+		slope = (stream-&gt;lumin_data.luminance_millinits[index2] - stream-&gt;lumin_data.luminance_millinits[index1]) /</div><div class='add'>+				(stream-&gt;lumin_data.refresh_rate_hz[index2] - stream-&gt;lumin_data.refresh_rate_hz[index1]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	int y_intercept = stream-&gt;lumin_data.luminance_millinits[index2] - slope * stream-&gt;lumin_data.refresh_rate_hz[index2];</div><div class='add'>+</div><div class='add'>+	return ((int)div64_s64((brightness_millinits - y_intercept), slope));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds the current brightness in millinits given a refresh rate</div><div class='add'>+ */</div><div class='add'>+static int dc_stream_get_brightness_millinits_from_refresh (struct dc_stream_state *stream, int refresh_hz)</div><div class='add'>+{</div><div class='add'>+	int nearest_smallest_index = dc_stream_get_nearest_smallest_index(stream, refresh_hz);</div><div class='add'>+	int nearest_smallest_value = stream-&gt;lumin_data.refresh_rate_hz[nearest_smallest_index];</div><div class='add'>+</div><div class='add'>+	if (nearest_smallest_value == refresh_hz)</div><div class='add'>+		return stream-&gt;lumin_data.luminance_millinits[nearest_smallest_index];</div><div class='add'>+</div><div class='add'>+	if (nearest_smallest_index &gt;= 9)</div><div class='add'>+		return dc_stream_get_brightness_millinits_linear_interpolation(stream, nearest_smallest_index - 1, nearest_smallest_index, refresh_hz);</div><div class='add'>+</div><div class='add'>+	if (nearest_smallest_value == stream-&gt;lumin_data.refresh_rate_hz[nearest_smallest_index + 1])</div><div class='add'>+		return stream-&gt;lumin_data.luminance_millinits[nearest_smallest_index];</div><div class='add'>+</div><div class='add'>+	return dc_stream_get_brightness_millinits_linear_interpolation(stream, nearest_smallest_index, nearest_smallest_index + 1, refresh_hz);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds the lowest/highest refresh rate (depending on search_for_max_increase)</div><div class='add'>+ * that can be achieved from starting_refresh_hz while staying</div><div class='add'>+ * within flicker criteria</div><div class='add'>+ */</div><div class='add'>+static int dc_stream_calculate_flickerless_refresh_rate(struct dc_stream_state *stream,</div><div class='add'>+							 int current_brightness,</div><div class='add'>+							 int starting_refresh_hz,</div><div class='add'>+							 bool is_gaming,</div><div class='add'>+							 bool search_for_max_increase)</div><div class='add'>+{</div><div class='add'>+	int nearest_smallest_index = dc_stream_get_nearest_smallest_index(stream, starting_refresh_hz);</div><div class='add'>+</div><div class='add'>+	int flicker_criteria_millinits = is_gaming ?</div><div class='add'>+					 stream-&gt;lumin_data.flicker_criteria_milli_nits_GAMING :</div><div class='add'>+					 stream-&gt;lumin_data.flicker_criteria_milli_nits_STATIC;</div><div class='add'>+</div><div class='add'>+	int safe_upper_bound = current_brightness + flicker_criteria_millinits;</div><div class='add'>+	int safe_lower_bound = current_brightness - flicker_criteria_millinits;</div><div class='add'>+	int lumin_millinits_temp = 0;</div><div class='add'>+</div><div class='add'>+	int offset = -1;</div><div class='add'>+	if (search_for_max_increase) {</div><div class='add'>+		offset = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Increments up or down by 1 depending on search_for_max_increase</div><div class='add'>+	 */</div><div class='add'>+	for (int i = nearest_smallest_index; (i &gt; 0 &amp;&amp; !search_for_max_increase) || (i &lt; (LUMINANCE_DATA_TABLE_SIZE - 1) &amp;&amp; search_for_max_increase); i += offset) {</div><div class='add'>+</div><div class='add'>+		lumin_millinits_temp = stream-&gt;lumin_data.luminance_millinits[i + offset];</div><div class='add'>+</div><div class='add'>+		if ((lumin_millinits_temp &gt;= safe_upper_bound) || (lumin_millinits_temp &lt;= safe_lower_bound)) {</div><div class='add'>+</div><div class='add'>+			if (stream-&gt;lumin_data.refresh_rate_hz[i + offset] == stream-&gt;lumin_data.refresh_rate_hz[i])</div><div class='add'>+				return stream-&gt;lumin_data.refresh_rate_hz[i];</div><div class='add'>+</div><div class='add'>+			int target_brightness = (stream-&gt;lumin_data.luminance_millinits[i + offset] &gt;= (current_brightness + flicker_criteria_millinits)) ?</div><div class='add'>+											current_brightness + flicker_criteria_millinits :</div><div class='add'>+											current_brightness - flicker_criteria_millinits;</div><div class='add'>+</div><div class='add'>+			int refresh = 0;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Need the second input to be &lt; third input for dc_stream_get_refresh_hz_linear_interpolation</div><div class='add'>+			 */</div><div class='add'>+			if (search_for_max_increase)</div><div class='add'>+				refresh = dc_stream_get_refresh_hz_linear_interpolation(stream, i, i + offset, target_brightness);</div><div class='add'>+			else</div><div class='add'>+				refresh = dc_stream_get_refresh_hz_linear_interpolation(stream, i + offset, i, target_brightness);</div><div class='add'>+</div><div class='add'>+			if (refresh == stream-&gt;lumin_data.refresh_rate_hz[i + offset])</div><div class='add'>+				return stream-&gt;lumin_data.refresh_rate_hz[i + offset];</div><div class='add'>+</div><div class='add'>+			return refresh;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (search_for_max_increase)</div><div class='add'>+		return (int)div64_s64((long long)stream-&gt;timing.pix_clk_100hz*100, stream-&gt;timing.v_total*(long long)stream-&gt;timing.h_total);</div><div class='add'>+	else</div><div class='add'>+		return stream-&gt;lumin_data.refresh_rate_hz[0];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Gets the max delta luminance within a specified refresh range</div><div class='add'>+ */</div><div class='add'>+static int dc_stream_get_max_delta_lumin_millinits(struct dc_stream_state *stream, int hz1, int hz2, bool isGaming)</div><div class='add'>+{</div><div class='add'>+	int lower_refresh_brightness = dc_stream_get_brightness_millinits_from_refresh (stream, hz1);</div><div class='add'>+	int higher_refresh_brightness = dc_stream_get_brightness_millinits_from_refresh (stream, hz2);</div><div class='add'>+</div><div class='add'>+	int min = lower_refresh_brightness;</div><div class='add'>+	int max = higher_refresh_brightness;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Static screen, therefore no need to scan through array</div><div class='add'>+	 */</div><div class='add'>+	if (!isGaming) {</div><div class='add'>+		if (lower_refresh_brightness &gt;= higher_refresh_brightness) {</div><div class='add'>+			return lower_refresh_brightness - higher_refresh_brightness;</div><div class='add'>+		}</div><div class='add'>+		return higher_refresh_brightness - lower_refresh_brightness;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min = MIN(lower_refresh_brightness, higher_refresh_brightness);</div><div class='add'>+	max = MAX(lower_refresh_brightness, higher_refresh_brightness);</div><div class='add'>+</div><div class='add'>+	int nearest_smallest_index = dc_stream_get_nearest_smallest_index(stream, hz1);</div><div class='add'>+</div><div class='add'>+	for (; nearest_smallest_index &lt; (LUMINANCE_DATA_TABLE_SIZE - 1) &amp;&amp;</div><div class='add'>+			stream-&gt;lumin_data.refresh_rate_hz[nearest_smallest_index + 1] &lt;= hz2 ; nearest_smallest_index++) {</div><div class='add'>+		min = MIN(min, stream-&gt;lumin_data.luminance_millinits[nearest_smallest_index + 1]);</div><div class='add'>+		max = MAX(max, stream-&gt;lumin_data.luminance_millinits[nearest_smallest_index + 1]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return (max - min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the max flickerless instant vtotal delta for a stream.</div><div class='add'>+ * Determines vtotal increase/decrease based on the bool "increase"</div><div class='add'>+ */</div><div class='add'>+static unsigned int dc_stream_get_max_flickerless_instant_vtotal_delta(struct dc_stream_state *stream, bool is_gaming, bool increase)</div><div class='add'>+{</div><div class='add'>+	if (stream-&gt;timing.v_total * stream-&gt;timing.h_total == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	int current_refresh_hz = (int)div64_s64((long long)stream-&gt;timing.pix_clk_100hz*100, stream-&gt;timing.v_total*(long long)stream-&gt;timing.h_total);</div><div class='add'>+</div><div class='add'>+	int safe_refresh_hz = dc_stream_calculate_flickerless_refresh_rate(stream,</div><div class='add'>+							 dc_stream_get_brightness_millinits_from_refresh(stream, current_refresh_hz),</div><div class='add'>+							 current_refresh_hz,</div><div class='add'>+							 is_gaming,</div><div class='add'>+							 increase);</div><div class='add'>+</div><div class='add'>+	int safe_refresh_v_total = (int)div64_s64((long long)stream-&gt;timing.pix_clk_100hz*100, safe_refresh_hz*(long long)stream-&gt;timing.h_total);</div><div class='add'>+</div><div class='add'>+	if (increase)</div><div class='add'>+		return (((int) stream-&gt;timing.v_total - safe_refresh_v_total) &gt;= 0) ? (stream-&gt;timing.v_total - safe_refresh_v_total) : 0;</div><div class='add'>+</div><div class='add'>+	return ((safe_refresh_v_total - (int) stream-&gt;timing.v_total) &gt;= 0) ? (safe_refresh_v_total - stream-&gt;timing.v_total) : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds the highest refresh rate that can be achieved</div><div class='add'>+ * from starting_refresh_hz while staying within flicker criteria</div><div class='add'>+ */</div><div class='add'>+int dc_stream_calculate_max_flickerless_refresh_rate(struct dc_stream_state *stream, int starting_refresh_hz, bool is_gaming)</div><div class='add'>+{</div><div class='add'>+	if (!stream-&gt;lumin_data.is_valid)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	int current_brightness = dc_stream_get_brightness_millinits_from_refresh(stream, starting_refresh_hz);</div><div class='add'>+</div><div class='add'>+	return dc_stream_calculate_flickerless_refresh_rate(stream,</div><div class='add'>+							    current_brightness,</div><div class='add'>+							    starting_refresh_hz,</div><div class='add'>+							    is_gaming,</div><div class='add'>+							    true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds the lowest refresh rate that can be achieved</div><div class='add'>+ * from starting_refresh_hz while staying within flicker criteria</div><div class='add'>+ */</div><div class='add'>+int dc_stream_calculate_min_flickerless_refresh_rate(struct dc_stream_state *stream, int starting_refresh_hz, bool is_gaming)</div><div class='add'>+{</div><div class='add'>+	if (!stream-&gt;lumin_data.is_valid)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+	int current_brightness = dc_stream_get_brightness_millinits_from_refresh(stream, starting_refresh_hz);</div><div class='add'>+</div><div class='add'>+	return dc_stream_calculate_flickerless_refresh_rate(stream,</div><div class='add'>+							    current_brightness,</div><div class='add'>+							    starting_refresh_hz,</div><div class='add'>+							    is_gaming,</div><div class='add'>+							    false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines if there will be a flicker when moving between 2 refresh rates</div><div class='add'>+ */</div><div class='add'>+bool dc_stream_is_refresh_rate_range_flickerless(struct dc_stream_state *stream, int hz1, int hz2, bool is_gaming)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Assume that we wont flicker if there is invalid data</div><div class='add'>+	 */</div><div class='add'>+	if (!stream-&gt;lumin_data.is_valid)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	int dl = dc_stream_get_max_delta_lumin_millinits(stream, hz1, hz2, is_gaming);</div><div class='add'>+</div><div class='add'>+	int flicker_criteria_millinits = (is_gaming) ?</div><div class='add'>+					  stream-&gt;lumin_data.flicker_criteria_milli_nits_GAMING :</div><div class='add'>+					  stream-&gt;lumin_data.flicker_criteria_milli_nits_STATIC;</div><div class='add'>+</div><div class='add'>+	return (dl &lt;= flicker_criteria_millinits);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the max instant vtotal delta increase that can be applied without</div><div class='add'>+ * flickering for a given stream</div><div class='add'>+ */</div><div class='add'>+unsigned int dc_stream_get_max_flickerless_instant_vtotal_decrease(struct dc_stream_state *stream,</div><div class='add'>+									  bool is_gaming)</div><div class='add'>+{</div><div class='add'>+	if (!stream-&gt;lumin_data.is_valid)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return dc_stream_get_max_flickerless_instant_vtotal_delta(stream, is_gaming, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the max instant vtotal delta decrease that can be applied without</div><div class='add'>+ * flickering for a given stream</div><div class='add'>+ */</div><div class='add'>+unsigned int dc_stream_get_max_flickerless_instant_vtotal_increase(struct dc_stream_state *stream,</div><div class='add'>+									  bool is_gaming)</div><div class='add'>+{</div><div class='add'>+	if (!stream-&gt;lumin_data.is_valid)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return dc_stream_get_max_flickerless_instant_vtotal_delta(stream, is_gaming, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	bool is_limit_pending = false;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;current_state)</div><div class='add'>+		is_limit_pending = dc_state_get_stream_cursor_subvp_limit(stream, dc-&gt;current_state);</div><div class='add'>+</div><div class='add'>+	return is_limit_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	bool can_clear_limit = false;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;current_state)</div><div class='add'>+		can_clear_limit = dc_state_get_stream_cursor_subvp_limit(stream, dc-&gt;current_state) &amp;&amp;</div><div class='add'>+				(stream-&gt;hw_cursor_req ||</div><div class='add'>+				!stream-&gt;cursor_position.enable ||</div><div class='add'>+				dc_stream_check_cursor_attributes(stream, dc-&gt;current_state, &amp;stream-&gt;cursor_attributes));</div><div class='add'>+</div><div class='add'>+	return can_clear_limit;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c<br/>index 19140fb65787..922f23557f5d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_surface.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_surface.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_surface.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_surface.c</a></div><div class='hunk'>@@ -41,25 +41,15 @@ void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_sta</div><div class='ctx'> {</div><div class='ctx'> 	plane_state-&gt;ctx = ctx;</div><div class='ctx'> </div><div class='del'>-	plane_state-&gt;gamma_correction = dc_create_gamma();</div><div class='del'>-	if (plane_state-&gt;gamma_correction != NULL)</div><div class='del'>-		plane_state-&gt;gamma_correction-&gt;is_identity = true;</div><div class='add'>+	plane_state-&gt;gamma_correction.is_identity = true;</div><div class='ctx'> </div><div class='del'>-	plane_state-&gt;in_transfer_func = dc_create_transfer_func();</div><div class='del'>-	if (plane_state-&gt;in_transfer_func != NULL) {</div><div class='del'>-		plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='del'>-	}</div><div class='del'>-	plane_state-&gt;in_shaper_func = dc_create_transfer_func();</div><div class='del'>-	if (plane_state-&gt;in_shaper_func != NULL) {</div><div class='del'>-		plane_state-&gt;in_shaper_func-&gt;type = TF_TYPE_BYPASS;</div><div class='del'>-	}</div><div class='add'>+	plane_state-&gt;in_transfer_func.type = TF_TYPE_BYPASS;</div><div class='ctx'> </div><div class='del'>-	plane_state-&gt;lut3d_func = dc_create_3dlut_func();</div><div class='add'>+	plane_state-&gt;in_shaper_func.type = TF_TYPE_BYPASS;</div><div class='ctx'> </div><div class='del'>-	plane_state-&gt;blend_tf = dc_create_transfer_func();</div><div class='del'>-	if (plane_state-&gt;blend_tf != NULL) {</div><div class='del'>-		plane_state-&gt;blend_tf-&gt;type = TF_TYPE_BYPASS;</div><div class='del'>-	}</div><div class='add'>+	plane_state-&gt;lut3d_func.state.raw = 0;</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;blend_tf.type = TF_TYPE_BYPASS;</div><div class='ctx'> </div><div class='ctx'> 	plane_state-&gt;pre_multiplied_alpha = true;</div><div class='ctx'> </div><div class='hunk'>@@ -67,43 +57,33 @@ void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_sta</div><div class='ctx'> </div><div class='ctx'> void dc_plane_destruct(struct dc_plane_state *plane_state)</div><div class='ctx'> {</div><div class='del'>-	if (plane_state-&gt;gamma_correction != NULL) {</div><div class='del'>-		dc_gamma_release(&amp;plane_state-&gt;gamma_correction);</div><div class='del'>-	}</div><div class='del'>-	if (plane_state-&gt;in_transfer_func != NULL) {</div><div class='del'>-		dc_transfer_func_release(</div><div class='del'>-				plane_state-&gt;in_transfer_func);</div><div class='del'>-		plane_state-&gt;in_transfer_func = NULL;</div><div class='del'>-	}</div><div class='del'>-	if (plane_state-&gt;in_shaper_func != NULL) {</div><div class='del'>-		dc_transfer_func_release(</div><div class='del'>-				plane_state-&gt;in_shaper_func);</div><div class='del'>-		plane_state-&gt;in_shaper_func = NULL;</div><div class='del'>-	}</div><div class='del'>-	if (plane_state-&gt;lut3d_func != NULL) {</div><div class='del'>-		dc_3dlut_func_release(</div><div class='del'>-				plane_state-&gt;lut3d_func);</div><div class='del'>-		plane_state-&gt;lut3d_func = NULL;</div><div class='del'>-	}</div><div class='del'>-	if (plane_state-&gt;blend_tf != NULL) {</div><div class='del'>-		dc_transfer_func_release(</div><div class='del'>-				plane_state-&gt;blend_tf);</div><div class='del'>-		plane_state-&gt;blend_tf = NULL;</div><div class='add'>+	// no more pointers to free within dc_plane_state</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* dc_state is passed in separately since it may differ from the current dc state accessible from plane_state e.g.</div><div class='add'>+ * if the driver is doing an update from an old context to a new one and the caller wants the pipe mask for the new</div><div class='add'>+ * context rather than the existing one</div><div class='add'>+ */</div><div class='add'>+uint8_t  dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	uint8_t pipe_mask = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; plane_state-&gt;ctx-&gt;dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;plane_state == plane_state &amp;&amp; pipe_ctx-&gt;plane_res.hubp)</div><div class='add'>+			pipe_mask |= 1 &lt;&lt; pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	return pipe_mask;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*******************************************************************************</div><div class='ctx'>  * Public functions</div><div class='ctx'>  ******************************************************************************/</div><div class='del'>-void enable_surface_flip_reporting(struct dc_plane_state *plane_state,</div><div class='del'>-		uint32_t controller_id)</div><div class='del'>-{</div><div class='del'>-	plane_state-&gt;irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;</div><div class='del'>-	/*register_flip_interrupt(surface);*/</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct dc_plane_state *dc_create_plane_state(struct dc *dc)</div><div class='add'>+struct dc_plane_state *dc_create_plane_state(const struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),</div><div class='ctx'> 							GFP_KERNEL);</div><div class='hunk'>@@ -129,7 +109,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)</div><div class='ctx'>  *****************************************************************************</div><div class='ctx'>  */</div><div class='ctx'> const struct dc_plane_status *dc_plane_get_status(</div><div class='del'>-		const struct dc_plane_state *plane_state)</div><div class='add'>+		const struct dc_plane_state *plane_state,</div><div class='add'>+		union dc_plane_status_update_flags flags)</div><div class='ctx'> {</div><div class='ctx'> 	const struct dc_plane_status *plane_status;</div><div class='ctx'> 	struct dc  *dc;</div><div class='hunk'>@@ -156,7 +137,8 @@ const struct dc_plane_status *dc_plane_get_status(</div><div class='ctx'> 		if (pipe_ctx-&gt;plane_state != plane_state)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		pipe_ctx-&gt;plane_state-&gt;status.is_flip_pending = false;</div><div class='add'>+		if (pipe_ctx-&gt;plane_state &amp;&amp; flags.bits.address)</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;status.is_flip_pending = false;</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -170,7 +152,8 @@ const struct dc_plane_status *dc_plane_get_status(</div><div class='ctx'> 		if (pipe_ctx-&gt;plane_state != plane_state)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		dc-&gt;hwss.update_pending_status(pipe_ctx);</div><div class='add'>+		if (flags.bits.address)</div><div class='add'>+			dc-&gt;hwss.update_pending_status(pipe_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return plane_status;</div><div class='hunk'>@@ -289,4 +272,41 @@ void dc_3dlut_func_retain(struct dc_3dlut *lut)</div><div class='ctx'> 	kref_get(&amp;lut-&gt;refcount);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,</div><div class='add'>+					   bool clear_tiling)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!plane_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dc = plane_state-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (!dc || !dc-&gt;current_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='add'>+		if (dc-&gt;hwss.clear_surface_dcc_and_tiling)</div><div class='add'>+			dc-&gt;hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_plane_copy_config(struct dc_plane_state *dst, const struct dc_plane_state *src)</div><div class='add'>+{</div><div class='add'>+	struct kref temp_refcount;</div><div class='add'>+</div><div class='add'>+	/* backup persistent info */</div><div class='add'>+	memcpy(&amp;temp_refcount, &amp;dst-&gt;refcount, sizeof(struct kref));</div><div class='add'>+</div><div class='add'>+	/* copy all configuration information */</div><div class='add'>+	memcpy(dst, src, sizeof(struct dc_plane_state));</div><div class='add'>+</div><div class='add'>+	/* restore persistent info */</div><div class='add'>+	memcpy(&amp;dst-&gt;refcount, &amp;temp_refcount, sizeof(struct kref));</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c<br/>index eda2152dcd1f..d1e68dc57a2a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c</a></div><div class='hunk'>@@ -47,6 +47,7 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c</div><div class='ctx'> 		 */</div><div class='ctx'> 		memcpy(&amp;dc-&gt;vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));</div><div class='ctx'> 		dc-&gt;vm_pa_config.valid = true;</div><div class='add'>+		dc-&gt;dml2_options.gpuvm_enable = true;</div><div class='ctx'> 		dc_z10_save_init(dc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h<br/>index ee8453bf958f..29edfa51ea2c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc.h</a></div><div class='hunk'>@@ -42,7 +42,11 @@</div><div class='ctx'> #include "inc/hw/dmcu.h"</div><div class='ctx'> #include "dml/display_mode_lib.h"</div><div class='ctx'> </div><div class='del'>-#include "dml2/dml2_wrapper.h"</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='add'>+</div><div class='add'>+#include "dmub/inc/dmub_cmd.h"</div><div class='add'>+</div><div class='add'>+#include "sspl/dc_spl_types.h"</div><div class='ctx'> </div><div class='ctx'> struct abm_save_restore;</div><div class='ctx'> </div><div class='hunk'>@@ -50,14 +54,33 @@ struct abm_save_restore;</div><div class='ctx'> struct aux_payload;</div><div class='ctx'> struct set_config_cmd_payload;</div><div class='ctx'> struct dmub_notification;</div><div class='add'>+struct dcn_hubbub_reg_state;</div><div class='add'>+struct dcn_hubp_reg_state;</div><div class='add'>+struct dcn_dpp_reg_state;</div><div class='add'>+struct dcn_mpc_reg_state;</div><div class='add'>+struct dcn_opp_reg_state;</div><div class='add'>+struct dcn_dsc_reg_state;</div><div class='add'>+struct dcn_optc_reg_state;</div><div class='add'>+struct dcn_dccg_reg_state;</div><div class='ctx'> </div><div class='del'>-#define DC_VER "3.2.273"</div><div class='add'>+#define DC_VER "3.2.359"</div><div class='ctx'> </div><div class='del'>-#define MAX_SURFACES 3</div><div class='add'>+/**</div><div class='add'>+ * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC</div><div class='add'>+ */</div><div class='add'>+#define MAX_SURFACES 4</div><div class='add'>+/**</div><div class='add'>+ * MAX_PLANES - representative of the upper bound of planes that are supported by the HW</div><div class='add'>+ */</div><div class='ctx'> #define MAX_PLANES 6</div><div class='ctx'> #define MAX_STREAMS 6</div><div class='ctx'> #define MIN_VIEWPORT_SIZE 12</div><div class='ctx'> #define MAX_NUM_EDP 2</div><div class='add'>+#define MAX_SUPPORTED_FORMATS 7</div><div class='add'>+</div><div class='add'>+#define MAX_HOST_ROUTERS_NUM 3</div><div class='add'>+#define MAX_DPIA_PER_HOST_ROUTER 3</div><div class='add'>+#define MAX_DPIA_NUM  (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER)</div><div class='ctx'> </div><div class='ctx'> /* Display Core Interfaces */</div><div class='ctx'> struct dc_versions {</div><div class='hunk'>@@ -183,6 +206,34 @@ struct dpp_color_caps {</div><div class='ctx'> 	struct rom_curve_caps ogam_rom_caps;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* Below structure is to describe the HW support for mem layout, extend support</div><div class='add'>+	range to match what OS could handle in the roadmap */</div><div class='add'>+struct lut3d_caps {</div><div class='add'>+	uint32_t dma_3d_lut : 1; /*&lt; DMA mode support for 3D LUT */</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t swizzle_3d_rgb : 1;</div><div class='add'>+		uint32_t swizzle_3d_bgr : 1;</div><div class='add'>+		uint32_t linear_1d : 1;</div><div class='add'>+	} mem_layout_support;</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t unorm_12msb : 1;</div><div class='add'>+		uint32_t unorm_12lsb : 1;</div><div class='add'>+		uint32_t float_fp1_5_10 : 1;</div><div class='add'>+	} mem_format_support;</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t order_rgba : 1;</div><div class='add'>+		uint32_t order_bgra : 1;</div><div class='add'>+	} mem_pixel_order_support;</div><div class='add'>+	/*&lt; size options are 9, 17, 33, 45, 65 */</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */</div><div class='add'>+		uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */</div><div class='add'>+		uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */</div><div class='add'>+		uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */</div><div class='add'>+		uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */</div><div class='add'>+	} lut_dim_caps;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct mpc_color_caps - color pipeline capabilities for multiple pipe and</div><div class='ctx'>  * plane combined blocks</div><div class='hunk'>@@ -191,17 +242,25 @@ struct dpp_color_caps {</div><div class='ctx'>  * @ogam_ram: programmable out gamma LUT</div><div class='ctx'>  * @ocsc: output color space conversion matrix</div><div class='ctx'>  * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT</div><div class='add'>+ * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT</div><div class='ctx'>  * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single</div><div class='ctx'>  * instance</div><div class='ctx'>  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT</div><div class='add'>+ * @mcm_3d_lut_caps: HW support cap for MCM LUT memory</div><div class='add'>+ * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory</div><div class='add'>+ * @preblend: whether color manager supports preblend with MPC</div><div class='ctx'>  */</div><div class='ctx'> struct mpc_color_caps {</div><div class='ctx'> 	uint16_t gamut_remap : 1;</div><div class='ctx'> 	uint16_t ogam_ram : 1;</div><div class='ctx'> 	uint16_t ocsc : 1;</div><div class='ctx'> 	uint16_t num_3dluts : 3;</div><div class='add'>+	uint16_t num_rmcm_3dluts : 3;</div><div class='ctx'> 	uint16_t shared_3d_lut:1;</div><div class='ctx'> 	struct rom_curve_caps ogam_rom_caps;</div><div class='add'>+	struct lut3d_caps mcm_3d_lut_caps;</div><div class='add'>+	struct lut3d_caps rmcm_3d_lut_caps;</div><div class='add'>+	bool preblend;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -219,6 +278,21 @@ struct dc_dmub_caps {</div><div class='ctx'> 	bool mclk_sw;</div><div class='ctx'> 	bool subvp_psr;</div><div class='ctx'> 	bool gecc_enable;</div><div class='add'>+	uint8_t fams_ver;</div><div class='add'>+	bool aux_backlight_support;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_scl_caps {</div><div class='add'>+	bool sharpener_support;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_check_config {</div><div class='add'>+	/**</div><div class='add'>+	 * max video plane width that can be safely assumed to be always</div><div class='add'>+	 * supported by single DPP pipe.</div><div class='add'>+	 */</div><div class='add'>+	unsigned int max_optimizable_video_width;</div><div class='add'>+	bool enable_legacy_fast_update;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_caps {</div><div class='hunk'>@@ -234,12 +308,8 @@ struct dc_caps {</div><div class='ctx'> 	uint32_t i2c_speed_in_khz_hdcp;</div><div class='ctx'> 	uint32_t dmdata_alloc_size;</div><div class='ctx'> 	unsigned int max_cursor_size;</div><div class='add'>+	unsigned int max_buffered_cursor_size;</div><div class='ctx'> 	unsigned int max_video_width;</div><div class='del'>-	/*</div><div class='del'>-	 * max video plane width that can be safely assumed to be always</div><div class='del'>-	 * supported by single DPP pipe.</div><div class='del'>-	 */</div><div class='del'>-	unsigned int max_optimizable_video_width;</div><div class='ctx'> 	unsigned int min_horizontal_blanking_period;</div><div class='ctx'> 	int linear_pitch_alignment;</div><div class='ctx'> 	bool dcc_const_color;</div><div class='hunk'>@@ -254,6 +324,7 @@ struct dc_caps {</div><div class='ctx'> 	bool dmcub_support;</div><div class='ctx'> 	bool zstate_support;</div><div class='ctx'> 	bool ips_support;</div><div class='add'>+	bool ips_v2_support;</div><div class='ctx'> 	uint32_t num_of_internal_disp;</div><div class='ctx'> 	enum dp_protocol_version max_dp_protocol_version;</div><div class='ctx'> 	unsigned int mall_size_per_mem_channel;</div><div class='hunk'>@@ -267,6 +338,7 @@ struct dc_caps {</div><div class='ctx'> 	bool edp_dsc_support;</div><div class='ctx'> 	bool vbios_lttpr_aware;</div><div class='ctx'> 	bool vbios_lttpr_enable;</div><div class='add'>+	bool fused_io_supported;</div><div class='ctx'> 	uint32_t max_otg_num;</div><div class='ctx'> 	uint32_t max_cab_allocation_bytes;</div><div class='ctx'> 	uint32_t cache_line_size;</div><div class='hunk'>@@ -279,8 +351,19 @@ struct dc_caps {</div><div class='ctx'> 	uint16_t subvp_vertical_int_margin_us;</div><div class='ctx'> 	bool seamless_odm;</div><div class='ctx'> 	uint32_t max_v_total;</div><div class='add'>+	bool vtotal_limited_by_fp2;</div><div class='ctx'> 	uint32_t max_disp_clock_khz_at_vmin;</div><div class='ctx'> 	uint8_t subvp_drr_vblank_start_margin_us;</div><div class='add'>+	bool cursor_not_scaled;</div><div class='add'>+	bool dcmode_power_limits_present;</div><div class='add'>+	bool sequential_ono;</div><div class='add'>+	/* Conservative limit for DCC cases which require ODM4:1 to support*/</div><div class='add'>+	uint32_t dcc_plane_width_limit;</div><div class='add'>+	struct dc_scl_caps scl_caps;</div><div class='add'>+	uint8_t num_of_host_routers;</div><div class='add'>+	uint8_t num_of_dpias_per_host_router;</div><div class='add'>+	/* limit of the ODM only, could be limited by other factors (like pipe count)*/</div><div class='add'>+	uint8_t max_odm_combine_factor;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_bug_wa {</div><div class='hunk'>@@ -294,11 +377,18 @@ struct dc_bug_wa {</div><div class='ctx'> 		uint8_t dcfclk : 1;</div><div class='ctx'> 		uint8_t dcfclk_ds: 1;</div><div class='ctx'> 	} clock_update_disable_mask;</div><div class='add'>+	bool skip_psr_ips_crtc_disable;</div><div class='ctx'> };</div><div class='ctx'> struct dc_dcc_surface_param {</div><div class='ctx'> 	struct dc_size surface_size;</div><div class='ctx'> 	enum surface_pixel_format format;</div><div class='del'>-	enum swizzle_mode_values swizzle_mode;</div><div class='add'>+	unsigned int plane0_pitch;</div><div class='add'>+	struct dc_size plane1_size;</div><div class='add'>+	unsigned int plane1_pitch;</div><div class='add'>+	union {</div><div class='add'>+		enum swizzle_mode_values swizzle_mode;</div><div class='add'>+		enum swizzle_mode_addr3_values swizzle_mode_addr3;</div><div class='add'>+	};</div><div class='ctx'> 	enum dc_scan_direction scan;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -306,12 +396,15 @@ struct dc_dcc_setting {</div><div class='ctx'> 	unsigned int max_compressed_blk_size;</div><div class='ctx'> 	unsigned int max_uncompressed_blk_size;</div><div class='ctx'> 	bool independent_64b_blks;</div><div class='del'>-	//These bitfields to be used starting with DCN</div><div class='add'>+	//These bitfields to be used starting with DCN 3.0</div><div class='ctx'> 	struct {</div><div class='del'>-		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)</div><div class='del'>-		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN</div><div class='del'>-		uint32_t dcc_256_128_128 : 1;		//available starting with DCN</div><div class='del'>-		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)</div><div class='add'>+		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)</div><div class='add'>+		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN 3.0</div><div class='add'>+		uint32_t dcc_256_128_128 : 1;		//available starting with DCN 3.0</div><div class='add'>+		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN 3.0 (the best compression case)</div><div class='add'>+		uint32_t dcc_256_256 : 1;  //available in ASICs starting with DCN 4.0x (the best compression case)</div><div class='add'>+		uint32_t dcc_256_128 : 1;  //available in ASICs starting with DCN 4.0x</div><div class='add'>+		uint32_t dcc_256_64 : 1;   //available in ASICs starting with DCN 4.0x (the worst compression case)</div><div class='ctx'> 	} dcc_controls;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -374,12 +467,23 @@ enum surface_update_type {</div><div class='ctx'> 	UPDATE_TYPE_FULL, /* may need to shuffle resources */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dc_lock_descriptor {</div><div class='add'>+	LOCK_DESCRIPTOR_NONE = 0x0,</div><div class='add'>+	LOCK_DESCRIPTOR_STREAM = 0x1,</div><div class='add'>+	LOCK_DESCRIPTOR_LINK = 0x2,</div><div class='add'>+	LOCK_DESCRIPTOR_GLOBAL = 0x4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct surface_update_descriptor {</div><div class='add'>+	enum surface_update_type update_type;</div><div class='add'>+	enum dc_lock_descriptor lock_descriptor;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Forward declaration*/</div><div class='ctx'> struct dc;</div><div class='ctx'> struct dc_plane_state;</div><div class='ctx'> struct dc_state;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> struct dc_cap_funcs {</div><div class='ctx'> 	bool (*get_dcc_compression_cap)(const struct dc *dc,</div><div class='ctx'> 			const struct dc_dcc_surface_param *input,</div><div class='hunk'>@@ -416,13 +520,17 @@ struct dc_config {</div><div class='ctx'> 	bool enable_windowed_mpo_odm;</div><div class='ctx'> 	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520</div><div class='ctx'> 	uint32_t allow_edp_hotplug_detection;</div><div class='add'>+	bool skip_riommu_prefetch_wa;</div><div class='ctx'> 	bool clamp_min_dcfclk;</div><div class='ctx'> 	uint64_t vblank_alignment_dto_params;</div><div class='ctx'> 	uint8_t  vblank_alignment_max_frame_time_diff;</div><div class='ctx'> 	bool is_asymmetric_memory;</div><div class='ctx'> 	bool is_single_rank_dimm;</div><div class='ctx'> 	bool is_vmin_only_asic;</div><div class='add'>+	bool use_spl;</div><div class='add'>+	bool prefer_easf;</div><div class='ctx'> 	bool use_pipe_ctx_sync_logic;</div><div class='add'>+	int smart_mux_version;</div><div class='ctx'> 	bool ignore_dpref_ss;</div><div class='ctx'> 	bool enable_mipi_converter_optimization;</div><div class='ctx'> 	bool use_default_clock_table;</div><div class='hunk'>@@ -433,8 +541,22 @@ struct dc_config {</div><div class='ctx'> 	bool EnableMinDispClkODM;</div><div class='ctx'> 	bool enable_auto_dpm_test_logs;</div><div class='ctx'> 	unsigned int disable_ips;</div><div class='add'>+	unsigned int disable_ips_rcg;</div><div class='ctx'> 	unsigned int disable_ips_in_vpb;</div><div class='add'>+	bool disable_ips_in_dpms_off;</div><div class='ctx'> 	bool usb4_bw_alloc_support;</div><div class='add'>+	bool allow_0_dtb_clk;</div><div class='add'>+	bool use_assr_psp_message;</div><div class='add'>+	bool support_edp0_on_dp1;</div><div class='add'>+	unsigned int enable_fpo_flicker_detection;</div><div class='add'>+	bool disable_hbr_audio_dp2;</div><div class='add'>+	bool consolidated_dpia_dp_lt;</div><div class='add'>+	bool set_pipe_unlock_order;</div><div class='add'>+	bool enable_dpia_pre_training;</div><div class='add'>+	bool unify_link_enc_assignment;</div><div class='add'>+	bool enable_cursor_offload;</div><div class='add'>+	struct spl_sharpness_range dcn_sharpness_range;</div><div class='add'>+	struct spl_sharpness_range dcn_override_sharpness_range;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum visual_confirm {</div><div class='hunk'>@@ -446,9 +568,15 @@ enum visual_confirm {</div><div class='ctx'> 	VISUAL_CONFIRM_SWAPCHAIN = 6,</div><div class='ctx'> 	VISUAL_CONFIRM_FAMS = 7,</div><div class='ctx'> 	VISUAL_CONFIRM_SWIZZLE = 9,</div><div class='add'>+	VISUAL_CONFIRM_SMARTMUX_DGPU = 10,</div><div class='ctx'> 	VISUAL_CONFIRM_REPLAY = 12,</div><div class='ctx'> 	VISUAL_CONFIRM_SUBVP = 14,</div><div class='ctx'> 	VISUAL_CONFIRM_MCLK_SWITCH = 16,</div><div class='add'>+	VISUAL_CONFIRM_FAMS2 = 19,</div><div class='add'>+	VISUAL_CONFIRM_HW_CURSOR = 20,</div><div class='add'>+	VISUAL_CONFIRM_VABC = 21,</div><div class='add'>+	VISUAL_CONFIRM_DCC = 22,</div><div class='add'>+	VISUAL_CONFIRM_EXPLICIT = 0x80000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum dc_psr_power_opts {</div><div class='hunk'>@@ -476,6 +604,13 @@ enum dcc_option {</div><div class='ctx'> 	DCC_HALF_REQ_DISALBE = 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum in_game_fams_config {</div><div class='add'>+	INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams</div><div class='add'>+	INGAME_FAMS_DISABLE, // disable in-game fams</div><div class='add'>+	INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display</div><div class='add'>+	INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * enum pipe_split_policy - Pipe split strategy supported by DCN</div><div class='ctx'>  *</div><div class='hunk'>@@ -562,6 +697,7 @@ struct dc_clocks {</div><div class='ctx'> 	bool prev_p_state_change_support;</div><div class='ctx'> 	bool fclk_prev_p_state_change_support;</div><div class='ctx'> 	int num_ways;</div><div class='add'>+	int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * @fw_based_mclk_switching</div><div class='hunk'>@@ -580,6 +716,19 @@ struct dc_clocks {</div><div class='ctx'> 	int max_supported_dispclk_khz;</div><div class='ctx'> 	int bw_dppclk_khz; /*a copy of dppclk_khz*/</div><div class='ctx'> 	int bw_dispclk_khz;</div><div class='add'>+	int idle_dramclk_khz;</div><div class='add'>+	int idle_fclk_khz;</div><div class='add'>+	int subvp_prefetch_dramclk_khz;</div><div class='add'>+	int subvp_prefetch_fclk_khz;</div><div class='add'>+</div><div class='add'>+	/* Stutter efficiency is technically not clock values</div><div class='add'>+	 * but stored here so the values are part of the update_clocks call similar to num_ways</div><div class='add'>+	 * Efficiencies are stored as percentage (0-100)</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t base_efficiency; //LP1</div><div class='add'>+		uint8_t low_power_efficiency; //LP2</div><div class='add'>+	} stutter_efficiency;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_bw_validation_profile {</div><div class='hunk'>@@ -693,6 +842,9 @@ enum pg_hw_pipe_resources {</div><div class='ctx'> 	PG_MPCC,</div><div class='ctx'> 	PG_OPP,</div><div class='ctx'> 	PG_OPTC,</div><div class='add'>+	PG_DPSTREAM,</div><div class='add'>+	PG_HDMISTREAM,</div><div class='add'>+	PG_PHYSYMCLK,</div><div class='ctx'> 	PG_HW_PIPE_RESOURCES_NUM_ELEMENT</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -704,6 +856,7 @@ enum pg_hw_resources {</div><div class='ctx'> 	PG_DCHVM,</div><div class='ctx'> 	PG_DWB,</div><div class='ctx'> 	PG_HPO,</div><div class='add'>+	PG_DCOH,</div><div class='ctx'> 	PG_HW_RESOURCES_NUM_ELEMENT</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -719,7 +872,9 @@ union dpia_debug_options {</div><div class='ctx'> 		uint32_t extend_aux_rd_interval:1; /* bit 2 */</div><div class='ctx'> 		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */</div><div class='ctx'> 		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */</div><div class='del'>-		uint32_t reserved:27;</div><div class='add'>+		uint32_t disable_usb4_pm_support:1; /* bit 5 */</div><div class='add'>+		uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */</div><div class='add'>+		uint32_t reserved:25;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint32_t raw;</div><div class='ctx'> };</div><div class='hunk'>@@ -744,6 +899,7 @@ struct dc_debug_data {</div><div class='ctx'> 	uint32_t ltFailCount;</div><div class='ctx'> 	uint32_t i2cErrorCount;</div><div class='ctx'> 	uint32_t auxErrorCount;</div><div class='add'>+	struct pipe_topology_history topology_history;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_phy_addr_space_config {</div><div class='hunk'>@@ -817,7 +973,6 @@ struct dc_debug_options {</div><div class='ctx'> 	bool sanity_checks;</div><div class='ctx'> 	bool max_disp_clk;</div><div class='ctx'> 	bool surface_trace;</div><div class='del'>-	bool timing_trace;</div><div class='ctx'> 	bool clock_trace;</div><div class='ctx'> 	bool validation_trace;</div><div class='ctx'> 	bool bandwidth_calcs_trace;</div><div class='hunk'>@@ -837,12 +992,18 @@ struct dc_debug_options {</div><div class='ctx'> 	bool voltage_align_fclk;</div><div class='ctx'> 	bool disable_min_fclk;</div><div class='ctx'> </div><div class='add'>+	bool hdcp_lc_force_fw_enable;</div><div class='add'>+	bool hdcp_lc_enable_sw_fallback;</div><div class='add'>+</div><div class='ctx'> 	bool disable_dfs_bypass;</div><div class='ctx'> 	bool disable_dpp_power_gate;</div><div class='ctx'> 	bool disable_hubp_power_gate;</div><div class='ctx'> 	bool disable_dsc_power_gate;</div><div class='ctx'> 	bool disable_optc_power_gate;</div><div class='ctx'> 	bool disable_hpo_power_gate;</div><div class='add'>+	bool disable_io_clk_power_gate;</div><div class='add'>+	bool disable_mem_power_gate;</div><div class='add'>+	bool disable_dio_power_gate;</div><div class='ctx'> 	int dsc_min_slice_height_override;</div><div class='ctx'> 	int dsc_bpp_increment_div;</div><div class='ctx'> 	bool disable_pplib_wm_range;</div><div class='hunk'>@@ -887,6 +1048,7 @@ struct dc_debug_options {</div><div class='ctx'> 	bool disable_z9_mpc;</div><div class='ctx'> 	unsigned int force_fclk_khz;</div><div class='ctx'> 	bool enable_tri_buf;</div><div class='add'>+	bool ips_disallow_entry;</div><div class='ctx'> 	bool dmub_offload_enabled;</div><div class='ctx'> 	bool dmcub_emulation;</div><div class='ctx'> 	bool disable_idle_power_optimizations;</div><div class='hunk'>@@ -926,7 +1088,7 @@ struct dc_debug_options {</div><div class='ctx'> 	/* Enable dmub aux for legacy ddc */</div><div class='ctx'> 	bool enable_dmub_aux_for_legacy_ddc;</div><div class='ctx'> 	bool disable_fams;</div><div class='del'>-	bool disable_fams_gaming;</div><div class='add'>+	enum in_game_fams_config disable_fams_gaming;</div><div class='ctx'> 	/* FEC/PSR1 sequence enable delay in 100us */</div><div class='ctx'> 	uint8_t fec_enable_delay_in100us;</div><div class='ctx'> 	bool enable_driver_sequence_debug;</div><div class='hunk'>@@ -935,6 +1097,7 @@ struct dc_debug_options {</div><div class='ctx'> 	bool disable_z10;</div><div class='ctx'> 	bool enable_z9_disable_interface;</div><div class='ctx'> 	bool psr_skip_crtc_disable;</div><div class='add'>+	uint32_t ips_skip_crtc_disable_mask;</div><div class='ctx'> 	union dpia_debug_options dpia_debug;</div><div class='ctx'> 	bool disable_fixed_vs_aux_timeout_wa;</div><div class='ctx'> 	uint32_t fixed_vs_aux_delay_config_wa;</div><div class='hunk'>@@ -945,6 +1108,7 @@ struct dc_debug_options {</div><div class='ctx'> 	unsigned int force_mall_ss_num_ways;</div><div class='ctx'> 	bool alloc_extra_way_for_cursor;</div><div class='ctx'> 	uint32_t subvp_extra_lines;</div><div class='add'>+	bool disable_force_pstate_allow_on_hw_release;</div><div class='ctx'> 	bool force_usr_allow;</div><div class='ctx'> 	/* uses value at boot and disables switch */</div><div class='ctx'> 	bool disable_dtb_ref_clk_switch;</div><div class='hunk'>@@ -960,6 +1124,7 @@ struct dc_debug_options {</div><div class='ctx'> 	bool enable_single_display_2to1_odm_policy;</div><div class='ctx'> 	bool enable_double_buffered_dsc_pg_support;</div><div class='ctx'> 	bool enable_dp_dig_pixel_rate_div_policy;</div><div class='add'>+	bool using_dml21;</div><div class='ctx'> 	enum lttpr_mode lttpr_mode_override;</div><div class='ctx'> 	unsigned int dsc_delay_factor_wa_x1000;</div><div class='ctx'> 	unsigned int min_prefetch_in_strobe_ns;</div><div class='hunk'>@@ -980,21 +1145,51 @@ struct dc_debug_options {</div><div class='ctx'> 	uint32_t fpo_vactive_min_active_margin_us;</div><div class='ctx'> 	uint32_t fpo_vactive_max_blank_us;</div><div class='ctx'> 	bool enable_hpo_pg_support;</div><div class='del'>-	bool enable_legacy_fast_update;</div><div class='ctx'> 	bool disable_dc_mode_overwrite;</div><div class='ctx'> 	bool replay_skip_crtc_disabled;</div><div class='ctx'> 	bool ignore_pg;/*do nothing, let pmfw control it*/</div><div class='ctx'> 	bool psp_disabled_wa;</div><div class='ctx'> 	unsigned int ips2_eval_delay_us;</div><div class='ctx'> 	unsigned int ips2_entry_delay_us;</div><div class='add'>+	bool optimize_ips_handshake;</div><div class='ctx'> 	bool disable_dmub_reallow_idle;</div><div class='ctx'> 	bool disable_timeout;</div><div class='ctx'> 	bool disable_extblankadj;</div><div class='add'>+	bool enable_idle_reg_checks;</div><div class='ctx'> 	unsigned int static_screen_wait_frames;</div><div class='add'>+	uint32_t pwm_freq;</div><div class='ctx'> 	bool force_chroma_subsampling_1tap;</div><div class='add'>+	unsigned int dcc_meta_propagation_delay_us;</div><div class='add'>+	bool disable_422_left_edge_pixel;</div><div class='add'>+	bool dml21_force_pstate_method;</div><div class='add'>+	uint32_t dml21_force_pstate_method_values[MAX_PIPES];</div><div class='add'>+	uint32_t dml21_disable_pstate_method_mask;</div><div class='add'>+	union fw_assisted_mclk_switch_version fams_version;</div><div class='add'>+	union dmub_fams2_global_feature_config fams2_config;</div><div class='add'>+	unsigned int force_cositing;</div><div class='add'>+	unsigned int disable_spl;</div><div class='add'>+	unsigned int force_easf;</div><div class='add'>+	unsigned int force_sharpness;</div><div class='add'>+	unsigned int force_sharpness_level;</div><div class='add'>+	unsigned int force_lls;</div><div class='add'>+	bool notify_dpia_hr_bw;</div><div class='add'>+	bool enable_ips_visual_confirm;</div><div class='add'>+	unsigned int sharpen_policy;</div><div class='add'>+	unsigned int scale_to_sharpness_policy;</div><div class='add'>+	unsigned int enable_oled_edp_power_up_opt;</div><div class='add'>+	bool enable_hblank_borrow;</div><div class='add'>+	bool force_subvp_df_throttle;</div><div class='add'>+	uint32_t acpi_transition_bitmasks[MAX_PIPES];</div><div class='add'>+	bool enable_pg_cntl_debug_logs;</div><div class='add'>+	unsigned int auxless_alpm_lfps_setup_ns;</div><div class='add'>+	unsigned int auxless_alpm_lfps_period_ns;</div><div class='add'>+	unsigned int auxless_alpm_lfps_silence_ns;</div><div class='add'>+	unsigned int auxless_alpm_lfps_t1t2_us;</div><div class='add'>+	short auxless_alpm_lfps_t1t2_offset_us;</div><div class='add'>+	bool disable_stutter_for_wm_program;</div><div class='add'>+	bool enable_block_sequence_programming;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct gpu_info_soc_bounding_box_v1_0;</div><div class='ctx'> </div><div class='ctx'> /* Generic structure that can be used to query properties of DC. More fields</div><div class='ctx'>  * can be added as required.</div><div class='hunk'>@@ -1003,76 +1198,6 @@ struct dc_current_properties {</div><div class='ctx'> 	unsigned int cursor_size_limit;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dc {</div><div class='del'>-	struct dc_debug_options debug;</div><div class='del'>-	struct dc_versions versions;</div><div class='del'>-	struct dc_caps caps;</div><div class='del'>-	struct dc_cap_funcs cap_funcs;</div><div class='del'>-	struct dc_config config;</div><div class='del'>-	struct dc_bounding_box_overrides bb_overrides;</div><div class='del'>-	struct dc_bug_wa work_arounds;</div><div class='del'>-	struct dc_context *ctx;</div><div class='del'>-	struct dc_phy_addr_space_config vm_pa_config;</div><div class='del'>-</div><div class='del'>-	uint8_t link_count;</div><div class='del'>-	struct dc_link *links[MAX_PIPES * 2];</div><div class='del'>-	struct link_service *link_srv;</div><div class='del'>-</div><div class='del'>-	struct dc_state *current_state;</div><div class='del'>-	struct resource_pool *res_pool;</div><div class='del'>-</div><div class='del'>-	struct clk_mgr *clk_mgr;</div><div class='del'>-</div><div class='del'>-	/* Display Engine Clock levels */</div><div class='del'>-	struct dm_pp_clock_levels sclk_lvls;</div><div class='del'>-</div><div class='del'>-	/* Inputs into BW and WM calculations. */</div><div class='del'>-	struct bw_calcs_dceip *bw_dceip;</div><div class='del'>-	struct bw_calcs_vbios *bw_vbios;</div><div class='del'>-	struct dcn_soc_bounding_box *dcn_soc;</div><div class='del'>-	struct dcn_ip_params *dcn_ip;</div><div class='del'>-	struct display_mode_lib dml;</div><div class='del'>-</div><div class='del'>-	/* HW functions */</div><div class='del'>-	struct hw_sequencer_funcs hwss;</div><div class='del'>-	struct dce_hwseq *hwseq;</div><div class='del'>-</div><div class='del'>-	/* Require to optimize clocks and bandwidth for added/removed planes */</div><div class='del'>-	bool optimized_required;</div><div class='del'>-	bool wm_optimized_required;</div><div class='del'>-	bool idle_optimizations_allowed;</div><div class='del'>-	bool enable_c20_dtm_b0;</div><div class='del'>-</div><div class='del'>-	/* Require to maintain clocks and bandwidth for UEFI enabled HW */</div><div class='del'>-</div><div class='del'>-	/* FBC compressor */</div><div class='del'>-	struct compressor *fbc_compressor;</div><div class='del'>-</div><div class='del'>-	struct dc_debug_data debug_data;</div><div class='del'>-	struct dpcd_vendor_signature vendor_signature;</div><div class='del'>-</div><div class='del'>-	const char *build_id;</div><div class='del'>-	struct vm_helper *vm_helper;</div><div class='del'>-</div><div class='del'>-	uint32_t *dcn_reg_offsets;</div><div class='del'>-	uint32_t *nbio_reg_offsets;</div><div class='del'>-	uint32_t *clk_reg_offsets;</div><div class='del'>-</div><div class='del'>-	/* Scratch memory */</div><div class='del'>-	struct {</div><div class='del'>-		struct {</div><div class='del'>-			/*</div><div class='del'>-			 * For matching clock_limits table in driver with table</div><div class='del'>-			 * from PMFW.</div><div class='del'>-			 */</div><div class='del'>-			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];</div><div class='del'>-		} update_bw_bounding_box;</div><div class='del'>-	} scratch;</div><div class='del'>-</div><div class='del'>-	struct dml2_configuration_options dml2_options;</div><div class='del'>-	enum dc_acpi_cm_power_state power_state;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> enum frame_buffer_mode {</div><div class='ctx'> 	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,</div><div class='ctx'> 	FRAME_BUFFER_MODE_ZFB_ONLY,</div><div class='hunk'>@@ -1088,6 +1213,8 @@ struct dchub_init_data {</div><div class='ctx'> 	bool dchub_info_valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dml2_soc_bb;</div><div class='add'>+</div><div class='ctx'> struct dc_init_data {</div><div class='ctx'> 	struct hw_asic_id asic_id;</div><div class='ctx'> 	void *driver; /* ctx */</div><div class='hunk'>@@ -1120,6 +1247,7 @@ struct dc_init_data {</div><div class='ctx'> 	uint32_t *dcn_reg_offsets;</div><div class='ctx'> 	uint32_t *nbio_reg_offsets;</div><div class='ctx'> 	uint32_t *clk_reg_offsets;</div><div class='add'>+	void *bb_from_dmub;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_callback_init {</div><div class='hunk'>@@ -1220,6 +1348,38 @@ union dc_3dlut_state {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='add'>+#define MATRIX_9C__DIM_128_ALIGNED_LEN   16 // 9+8 :  9 * 8 +  7 * 8 = 72  + 56  = 128 % 128 = 0</div><div class='add'>+#define MATRIX_17C__DIM_128_ALIGNED_LEN  32 //17+15:  17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0</div><div class='add'>+#define MATRIX_33C__DIM_128_ALIGNED_LEN  64 //17+47:  17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0</div><div class='add'>+</div><div class='add'>+struct lut_rgb {</div><div class='add'>+	uint16_t b;</div><div class='add'>+	uint16_t g;</div><div class='add'>+	uint16_t r;</div><div class='add'>+	uint16_t padding;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//this structure maps directly to how the lut will read it from memory</div><div class='add'>+struct lut_mem_mapping {</div><div class='add'>+	union {</div><div class='add'>+		//NATIVE MODE 1, 2</div><div class='add'>+		//RGB layout          [b][g][r]      //red  is 128 byte aligned</div><div class='add'>+		//BGR layout          [r][g][b]      //blue is 128 byte aligned</div><div class='add'>+		struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN];</div><div class='add'>+		struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN];</div><div class='add'>+</div><div class='add'>+		//TRANSFORMED</div><div class='add'>+		uint16_t linear_rgb[(33*33*33*4/128+1)*128];</div><div class='add'>+	};</div><div class='add'>+	uint16_t size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_rmcm_3dlut {</div><div class='add'>+	bool isInUse;</div><div class='add'>+	const struct dc_stream_state *stream;</div><div class='add'>+	uint8_t protection_bits;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dc_3dlut {</div><div class='ctx'> 	struct kref refcount;</div><div class='ctx'> 	struct tetrahedral_params lut_3d;</div><div class='hunk'>@@ -1252,12 +1412,10 @@ union surface_update_flags {</div><div class='ctx'> 		uint32_t rotation_change:1;</div><div class='ctx'> 		uint32_t swizzle_change:1;</div><div class='ctx'> 		uint32_t scaling_change:1;</div><div class='del'>-		uint32_t clip_size_change: 1;</div><div class='ctx'> 		uint32_t position_change:1;</div><div class='ctx'> 		uint32_t in_transfer_func_change:1;</div><div class='ctx'> 		uint32_t input_csc_change:1;</div><div class='ctx'> 		uint32_t coeff_reduction_change:1;</div><div class='del'>-		uint32_t output_tf_change:1;</div><div class='ctx'> 		uint32_t pixel_format_change:1;</div><div class='ctx'> 		uint32_t plane_size_change:1;</div><div class='ctx'> 		uint32_t gamut_remap_change:1;</div><div class='hunk'>@@ -1271,12 +1429,16 @@ union surface_update_flags {</div><div class='ctx'> 		uint32_t stereo_format_change:1;</div><div class='ctx'> 		uint32_t lut_3d:1;</div><div class='ctx'> 		uint32_t tmz_changed:1;</div><div class='add'>+		uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */</div><div class='ctx'> 		uint32_t full_update:1;</div><div class='add'>+		uint32_t sdr_white_level_nits:1;</div><div class='ctx'> 	} bits;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define DC_REMOVE_PLANE_POINTERS 1</div><div class='add'>+</div><div class='ctx'> struct dc_plane_state {</div><div class='ctx'> 	struct dc_plane_address address;</div><div class='ctx'> 	struct dc_plane_flip_time time;</div><div class='hunk'>@@ -1287,13 +1449,13 @@ struct dc_plane_state {</div><div class='ctx'> 	struct rect clip_rect;</div><div class='ctx'> </div><div class='ctx'> 	struct plane_size plane_size;</div><div class='del'>-	union dc_tiling_info tiling_info;</div><div class='add'>+	struct dc_tiling_info tiling_info;</div><div class='ctx'> </div><div class='ctx'> 	struct dc_plane_dcc_param dcc;</div><div class='ctx'> </div><div class='del'>-	struct dc_gamma *gamma_correction;</div><div class='del'>-	struct dc_transfer_func *in_transfer_func;</div><div class='del'>-	struct dc_bias_and_scale *bias_and_scale;</div><div class='add'>+	struct dc_gamma gamma_correction;</div><div class='add'>+	struct dc_transfer_func in_transfer_func;</div><div class='add'>+	struct dc_bias_and_scale bias_and_scale;</div><div class='ctx'> 	struct dc_csc_transform input_csc_color_matrix;</div><div class='ctx'> 	struct fixed31_32 coeff_reduction_factor;</div><div class='ctx'> 	struct fixed31_32 hdr_mult;</div><div class='hunk'>@@ -1304,9 +1466,9 @@ struct dc_plane_state {</div><div class='ctx'> </div><div class='ctx'> 	enum dc_color_space color_space;</div><div class='ctx'> </div><div class='del'>-	struct dc_3dlut *lut3d_func;</div><div class='del'>-	struct dc_transfer_func *in_shaper_func;</div><div class='del'>-	struct dc_transfer_func *blend_tf;</div><div class='add'>+	struct dc_3dlut lut3d_func;</div><div class='add'>+	struct dc_transfer_func in_shaper_func;</div><div class='add'>+	struct dc_transfer_func blend_tf;</div><div class='ctx'> </div><div class='ctx'> 	struct dc_transfer_func *gamcor_tf;</div><div class='ctx'> 	enum surface_pixel_format format;</div><div class='hunk'>@@ -1342,11 +1504,25 @@ struct dc_plane_state {</div><div class='ctx'> 	struct tg_color visual_confirm_color;</div><div class='ctx'> </div><div class='ctx'> 	bool is_statically_allocated;</div><div class='add'>+	enum chroma_cositing cositing;</div><div class='add'>+	enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting;</div><div class='add'>+	bool mcm_lut1d_enable;</div><div class='add'>+	struct dc_cm2_func_luts mcm_luts;</div><div class='add'>+	bool lut_bank_a;</div><div class='add'>+	enum mpcc_movable_cm_location mcm_location;</div><div class='add'>+	struct dc_csc_transform cursor_csc_color_matrix;</div><div class='add'>+	bool adaptive_sharpness_en;</div><div class='add'>+	int adaptive_sharpness_policy;</div><div class='add'>+	int sharpness_level;</div><div class='add'>+	enum linear_light_scaling linear_light_scaling;</div><div class='add'>+	unsigned int sdr_white_level_nits;</div><div class='add'>+	struct spl_sharpness_range sharpness_range;</div><div class='add'>+	enum sharpness_range_source sharpness_source;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_plane_info {</div><div class='ctx'> 	struct plane_size plane_size;</div><div class='del'>-	union dc_tiling_info tiling_info;</div><div class='add'>+	struct dc_tiling_info tiling_info;</div><div class='ctx'> 	struct dc_plane_dcc_param dcc;</div><div class='ctx'> 	enum surface_pixel_format format;</div><div class='ctx'> 	enum dc_rotation_angle rotation;</div><div class='hunk'>@@ -1360,150 +1536,29 @@ struct dc_plane_info {</div><div class='ctx'> 	int  global_alpha_value;</div><div class='ctx'> 	bool input_csc_enabled;</div><div class='ctx'> 	int layer_index;</div><div class='add'>+	enum chroma_cositing cositing;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dc_scaling_info {</div><div class='del'>-	struct rect src_rect;</div><div class='del'>-	struct rect dst_rect;</div><div class='del'>-	struct rect clip_rect;</div><div class='del'>-	struct scaling_taps scaling_quality;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct dc_fast_update {</div><div class='del'>-	const struct dc_flip_addrs *flip_addr;</div><div class='del'>-	const struct dc_gamma *gamma;</div><div class='del'>-	const struct colorspace_transform *gamut_remap_matrix;</div><div class='del'>-	const struct dc_csc_transform *input_csc_color_matrix;</div><div class='del'>-	const struct fixed31_32 *coeff_reduction_factor;</div><div class='del'>-	struct dc_transfer_func *out_transfer_func;</div><div class='del'>-	struct dc_csc_transform *output_csc_transform;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct dc_surface_update {</div><div class='del'>-	struct dc_plane_state *surface;</div><div class='del'>-</div><div class='del'>-	/* isr safe update parameters.  null means no updates */</div><div class='del'>-	const struct dc_flip_addrs *flip_addr;</div><div class='del'>-	const struct dc_plane_info *plane_info;</div><div class='del'>-	const struct dc_scaling_info *scaling_info;</div><div class='del'>-	struct fixed31_32 hdr_mult;</div><div class='del'>-	/* following updates require alloc/sleep/spin that is not isr safe,</div><div class='del'>-	 * null means no updates</div><div class='del'>-	 */</div><div class='del'>-	const struct dc_gamma *gamma;</div><div class='del'>-	const struct dc_transfer_func *in_transfer_func;</div><div class='del'>-</div><div class='del'>-	const struct dc_csc_transform *input_csc_color_matrix;</div><div class='del'>-	const struct fixed31_32 *coeff_reduction_factor;</div><div class='del'>-	const struct dc_transfer_func *func_shaper;</div><div class='del'>-	const struct dc_3dlut *lut3d_func;</div><div class='del'>-	const struct dc_transfer_func *blend_tf;</div><div class='del'>-	const struct colorspace_transform *gamut_remap_matrix;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Create a new surface with default parameters;</div><div class='del'>- */</div><div class='del'>-void dc_gamma_retain(struct dc_gamma *dc_gamma);</div><div class='del'>-void dc_gamma_release(struct dc_gamma **dc_gamma);</div><div class='del'>-struct dc_gamma *dc_create_gamma(void);</div><div class='del'>-</div><div class='del'>-void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);</div><div class='del'>-void dc_transfer_func_release(struct dc_transfer_func *dc_tf);</div><div class='del'>-struct dc_transfer_func *dc_create_transfer_func(void);</div><div class='del'>-</div><div class='del'>-struct dc_3dlut *dc_create_3dlut_func(void);</div><div class='del'>-void dc_3dlut_func_release(struct dc_3dlut *lut);</div><div class='del'>-void dc_3dlut_func_retain(struct dc_3dlut *lut);</div><div class='del'>-</div><div class='del'>-void dc_post_update_surfaces_to_stream(</div><div class='del'>-		struct dc *dc);</div><div class='del'>-</div><div class='ctx'> #include "dc_stream.h"</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * struct dc_validation_set - Struct to store surface/stream associations for validation</div><div class='del'>- */</div><div class='del'>-struct dc_validation_set {</div><div class='del'>-	/**</div><div class='del'>-	 * @stream: Stream state properties</div><div class='del'>-	 */</div><div class='del'>-	struct dc_stream_state *stream;</div><div class='del'>-</div><div class='del'>-	/**</div><div class='del'>-	 * @plane_states: Surface state</div><div class='add'>+struct dc_scratch_space {</div><div class='add'>+	/* used to temporarily backup plane states of a stream during</div><div class='add'>+	 * dc update. The reason is that plane states are overwritten</div><div class='add'>+	 * with surface updates in dc update. Once they are overwritten</div><div class='add'>+	 * current state is no longer valid. We want to temporarily</div><div class='add'>+	 * store current value in plane states so we can still recover</div><div class='add'>+	 * a valid current state during dc update.</div><div class='ctx'> 	 */</div><div class='del'>-	struct dc_plane_state *plane_states[MAX_SURFACES];</div><div class='add'>+	struct dc_plane_state plane_states[MAX_SURFACES];</div><div class='ctx'> </div><div class='del'>-	/**</div><div class='del'>-	 * @plane_count: Total of active planes</div><div class='del'>-	 */</div><div class='del'>-	uint8_t plane_count;</div><div class='add'>+	struct dc_stream_state stream_state;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-bool dc_validate_boot_timing(const struct dc *dc,</div><div class='del'>-				const struct dc_sink *sink,</div><div class='del'>-				struct dc_crtc_timing *crtc_timing);</div><div class='del'>-</div><div class='del'>-enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);</div><div class='del'>-</div><div class='del'>-void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);</div><div class='del'>-</div><div class='del'>-enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='del'>-					const struct dc_validation_set set[],</div><div class='del'>-					int set_count,</div><div class='del'>-					struct dc_state *context,</div><div class='del'>-					bool fast_validate);</div><div class='del'>-</div><div class='del'>-bool dc_set_generic_gpio_for_stereo(bool enable,</div><div class='del'>-		struct gpio_service *gpio_service);</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * fast_validate: we return after determining if we can support the new state,</div><div class='del'>- * but before we populate the programming info</div><div class='del'>- */</div><div class='del'>-enum dc_status dc_validate_global_state(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *new_ctx,</div><div class='del'>-		bool fast_validate);</div><div class='del'>-</div><div class='del'>-bool dc_acquire_release_mpc_3dlut(</div><div class='del'>-		struct dc *dc, bool acquire,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_3dlut **lut,</div><div class='del'>-		struct dc_transfer_func **shaper);</div><div class='del'>-</div><div class='del'>-bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);</div><div class='del'>-void get_audio_check(struct audio_info *aud_modes,</div><div class='del'>-	struct audio_check *aud_chk);</div><div class='del'>-</div><div class='del'>-enum dc_status dc_commit_streams(struct dc *dc,</div><div class='del'>-				 struct dc_stream_state *streams[],</div><div class='del'>-				 uint8_t stream_count);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		int mpcc_inst);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);</div><div class='del'>-</div><div class='del'>-void dc_set_disable_128b_132b_stream_overhead(bool disable);</div><div class='del'>-</div><div class='del'>-/* The function returns minimum bandwidth required to drive a given timing</div><div class='del'>- * return - minimum required timing bandwidth in kbps.</div><div class='del'>- */</div><div class='del'>-uint32_t dc_bandwidth_in_kbps_from_timing(</div><div class='del'>-		const struct dc_crtc_timing *timing,</div><div class='del'>-		const enum dc_link_encoding_format link_encoding);</div><div class='del'>-</div><div class='del'>-/* Link Interfaces */</div><div class='ctx'> /*</div><div class='ctx'>  * A link contains one or more sinks and their connected status.</div><div class='ctx'>  * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.</div><div class='ctx'>  */</div><div class='del'>-struct dc_link {</div><div class='add'>+ struct dc_link {</div><div class='ctx'> 	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];</div><div class='ctx'> 	unsigned int sink_count;</div><div class='ctx'> 	struct dc_sink *local_sink;</div><div class='hunk'>@@ -1512,6 +1567,7 @@ struct dc_link {</div><div class='ctx'> 	enum signal_type connector_signal;</div><div class='ctx'> 	enum dc_irq_source irq_source_hpd;</div><div class='ctx'> 	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */</div><div class='add'>+	enum dc_irq_source irq_source_read_request;/* Read Request */</div><div class='ctx'> </div><div class='ctx'> 	bool is_hpd_filter_disabled;</div><div class='ctx'> 	bool dp_ss_off;</div><div class='hunk'>@@ -1619,7 +1675,6 @@ struct dc_link {</div><div class='ctx'> 	union dpcd_sink_ext_caps dpcd_sink_ext_caps;</div><div class='ctx'> </div><div class='ctx'> 	struct psr_settings psr_settings;</div><div class='del'>-</div><div class='ctx'> 	struct replay_settings replay_settings;</div><div class='ctx'> </div><div class='ctx'> 	/* Drive settings read from integrated info table */</div><div class='hunk'>@@ -1643,7 +1698,10 @@ struct dc_link {</div><div class='ctx'> 		bool dongle_mode_timing_override;</div><div class='ctx'> 		bool blank_stream_on_ocs_change;</div><div class='ctx'> 		bool read_dpcd204h_on_irq_hpd;</div><div class='add'>+		bool force_dp_ffe_preset;</div><div class='add'>+		bool skip_phy_ssc_reduction;</div><div class='ctx'> 	} wa_flags;</div><div class='add'>+	union dc_dp_ffe_preset forced_dp_ffe_preset;</div><div class='ctx'> 	struct link_mst_stream_allocation_table mst_stream_alloc_table;</div><div class='ctx'> </div><div class='ctx'> 	struct dc_link_status link_status;</div><div class='hunk'>@@ -1651,15 +1709,275 @@ struct dc_link {</div><div class='ctx'> </div><div class='ctx'> 	struct gpio *hpd_gpio;</div><div class='ctx'> 	enum dc_link_fec_state fec_state;</div><div class='add'>+	bool is_dds;</div><div class='add'>+	bool is_display_mux_present;</div><div class='ctx'> 	bool link_powered_externally;	// Used to bypass hardware sequencing delays when panel is powered down forcibly</div><div class='ctx'> </div><div class='ctx'> 	struct dc_panel_config panel_config;</div><div class='ctx'> 	struct phy_state phy_state;</div><div class='add'>+	uint32_t phy_transition_bitmask;</div><div class='ctx'> 	// BW ALLOCATON USB4 ONLY</div><div class='ctx'> 	struct dc_dpia_bw_alloc dpia_bw_alloc_config;</div><div class='ctx'> 	bool skip_implict_edp_power_control;</div><div class='add'>+	enum backlight_control_type backlight_control_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc {</div><div class='add'>+	struct dc_debug_options debug;</div><div class='add'>+	struct dc_versions versions;</div><div class='add'>+	struct dc_caps caps;</div><div class='add'>+	struct dc_check_config check_config;</div><div class='add'>+	struct dc_cap_funcs cap_funcs;</div><div class='add'>+	struct dc_config config;</div><div class='add'>+	struct dc_bounding_box_overrides bb_overrides;</div><div class='add'>+	struct dc_bug_wa work_arounds;</div><div class='add'>+	struct dc_context *ctx;</div><div class='add'>+	struct dc_phy_addr_space_config vm_pa_config;</div><div class='add'>+</div><div class='add'>+	uint8_t link_count;</div><div class='add'>+	struct dc_link *links[MAX_LINKS];</div><div class='add'>+	uint8_t lowest_dpia_link_index;</div><div class='add'>+	struct link_service *link_srv;</div><div class='add'>+</div><div class='add'>+	struct dc_state *current_state;</div><div class='add'>+	struct resource_pool *res_pool;</div><div class='add'>+</div><div class='add'>+	struct clk_mgr *clk_mgr;</div><div class='add'>+</div><div class='add'>+	/* Display Engine Clock levels */</div><div class='add'>+	struct dm_pp_clock_levels sclk_lvls;</div><div class='add'>+</div><div class='add'>+	/* Inputs into BW and WM calculations. */</div><div class='add'>+	struct bw_calcs_dceip *bw_dceip;</div><div class='add'>+	struct bw_calcs_vbios *bw_vbios;</div><div class='add'>+	struct dcn_soc_bounding_box *dcn_soc;</div><div class='add'>+	struct dcn_ip_params *dcn_ip;</div><div class='add'>+	struct display_mode_lib dml;</div><div class='add'>+</div><div class='add'>+	/* HW functions */</div><div class='add'>+	struct hw_sequencer_funcs hwss;</div><div class='add'>+	struct dce_hwseq *hwseq;</div><div class='add'>+</div><div class='add'>+	/* Require to optimize clocks and bandwidth for added/removed planes */</div><div class='add'>+	bool optimized_required;</div><div class='add'>+	bool idle_optimizations_allowed;</div><div class='add'>+	bool enable_c20_dtm_b0;</div><div class='add'>+</div><div class='add'>+	/* Require to maintain clocks and bandwidth for UEFI enabled HW */</div><div class='add'>+</div><div class='add'>+	/* For eDP to know the switching state of SmartMux */</div><div class='add'>+	bool is_switch_in_progress_orig;</div><div class='add'>+	bool is_switch_in_progress_dest;</div><div class='add'>+</div><div class='add'>+	/* FBC compressor */</div><div class='add'>+	struct compressor *fbc_compressor;</div><div class='add'>+</div><div class='add'>+	struct dc_debug_data debug_data;</div><div class='add'>+	struct dpcd_vendor_signature vendor_signature;</div><div class='add'>+</div><div class='add'>+	const char *build_id;</div><div class='add'>+	struct vm_helper *vm_helper;</div><div class='add'>+</div><div class='add'>+	uint32_t *dcn_reg_offsets;</div><div class='add'>+	uint32_t *nbio_reg_offsets;</div><div class='add'>+	uint32_t *clk_reg_offsets;</div><div class='add'>+</div><div class='add'>+	/* Scratch memory */</div><div class='add'>+	struct {</div><div class='add'>+		struct {</div><div class='add'>+			/*</div><div class='add'>+			 * For matching clock_limits table in driver with table</div><div class='add'>+			 * from PMFW.</div><div class='add'>+			 */</div><div class='add'>+			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];</div><div class='add'>+		} update_bw_bounding_box;</div><div class='add'>+		struct dc_scratch_space current_state;</div><div class='add'>+		struct dc_scratch_space new_state;</div><div class='add'>+		struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack</div><div class='add'>+		struct dc_link temp_link;</div><div class='add'>+		bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */</div><div class='add'>+	} scratch;</div><div class='add'>+</div><div class='add'>+	struct dml2_configuration_options dml2_options;</div><div class='add'>+	struct dml2_configuration_options dml2_dc_power_options;</div><div class='add'>+	enum dc_acpi_cm_power_state power_state;</div><div class='add'>+	struct soc_and_ip_translator *soc_and_ip_translator;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_scaling_info {</div><div class='add'>+	struct rect src_rect;</div><div class='add'>+	struct rect dst_rect;</div><div class='add'>+	struct rect clip_rect;</div><div class='add'>+	struct scaling_taps scaling_quality;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_fast_update {</div><div class='add'>+	const struct dc_flip_addrs *flip_addr;</div><div class='add'>+	const struct dc_gamma *gamma;</div><div class='add'>+	const struct colorspace_transform *gamut_remap_matrix;</div><div class='add'>+	const struct dc_csc_transform *input_csc_color_matrix;</div><div class='add'>+	const struct fixed31_32 *coeff_reduction_factor;</div><div class='add'>+	struct dc_transfer_func *out_transfer_func;</div><div class='add'>+	struct dc_csc_transform *output_csc_transform;</div><div class='add'>+	const struct dc_csc_transform *cursor_csc_color_matrix;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_surface_update {</div><div class='add'>+	struct dc_plane_state *surface;</div><div class='add'>+</div><div class='add'>+	/* isr safe update parameters.  null means no updates */</div><div class='add'>+	const struct dc_flip_addrs *flip_addr;</div><div class='add'>+	const struct dc_plane_info *plane_info;</div><div class='add'>+	const struct dc_scaling_info *scaling_info;</div><div class='add'>+	struct fixed31_32 hdr_mult;</div><div class='add'>+	/* following updates require alloc/sleep/spin that is not isr safe,</div><div class='add'>+	 * null means no updates</div><div class='add'>+	 */</div><div class='add'>+	const struct dc_gamma *gamma;</div><div class='add'>+	const struct dc_transfer_func *in_transfer_func;</div><div class='add'>+</div><div class='add'>+	const struct dc_csc_transform *input_csc_color_matrix;</div><div class='add'>+	const struct fixed31_32 *coeff_reduction_factor;</div><div class='add'>+	const struct dc_transfer_func *func_shaper;</div><div class='add'>+	const struct dc_3dlut *lut3d_func;</div><div class='add'>+	const struct dc_transfer_func *blend_tf;</div><div class='add'>+	const struct colorspace_transform *gamut_remap_matrix;</div><div class='add'>+	/*</div><div class='add'>+	 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)</div><div class='add'>+	 *</div><div class='add'>+	 * change cm2_params.component_settings: Full update</div><div class='add'>+	 * change cm2_params.cm2_luts: Fast update</div><div class='add'>+	 */</div><div class='add'>+	const struct dc_cm2_parameters *cm2_params;</div><div class='add'>+	const struct dc_csc_transform *cursor_csc_color_matrix;</div><div class='add'>+	unsigned int sdr_white_level_nits;</div><div class='add'>+	struct dc_bias_and_scale bias_and_scale;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_underflow_debug_data {</div><div class='add'>+	struct dcn_hubbub_reg_state *hubbub_reg_state;</div><div class='add'>+	struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];</div><div class='add'>+	struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];</div><div class='add'>+	struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];</div><div class='add'>+	struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];</div><div class='add'>+	struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];</div><div class='add'>+	struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];</div><div class='add'>+	struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct power_features {</div><div class='add'>+	bool ips;</div><div class='add'>+	bool rcg;</div><div class='add'>+	bool replay;</div><div class='add'>+	bool dds;</div><div class='add'>+	bool sprs;</div><div class='add'>+	bool psr;</div><div class='add'>+	bool fams;</div><div class='add'>+	bool mpo;</div><div class='add'>+	bool uclk_p_state;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Create a new surface with default parameters;</div><div class='add'>+ */</div><div class='add'>+void dc_gamma_retain(struct dc_gamma *dc_gamma);</div><div class='add'>+void dc_gamma_release(struct dc_gamma **dc_gamma);</div><div class='add'>+struct dc_gamma *dc_create_gamma(void);</div><div class='add'>+</div><div class='add'>+void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);</div><div class='add'>+void dc_transfer_func_release(struct dc_transfer_func *dc_tf);</div><div class='add'>+struct dc_transfer_func *dc_create_transfer_func(void);</div><div class='add'>+</div><div class='add'>+struct dc_3dlut *dc_create_3dlut_func(void);</div><div class='add'>+void dc_3dlut_func_release(struct dc_3dlut *lut);</div><div class='add'>+void dc_3dlut_func_retain(struct dc_3dlut *lut);</div><div class='add'>+</div><div class='add'>+void dc_post_update_surfaces_to_stream(</div><div class='add'>+		struct dc *dc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dc_validation_set - Struct to store surface/stream associations for validation</div><div class='add'>+ */</div><div class='add'>+struct dc_validation_set {</div><div class='add'>+	/**</div><div class='add'>+	 * @stream: Stream state properties</div><div class='add'>+	 */</div><div class='add'>+	struct dc_stream_state *stream;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_states: Surface state</div><div class='add'>+	 */</div><div class='add'>+	struct dc_plane_state *plane_states[MAX_SURFACES];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_count: Total of active planes</div><div class='add'>+	 */</div><div class='add'>+	uint8_t plane_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dc_validate_boot_timing(const struct dc *dc,</div><div class='add'>+				const struct dc_sink *sink,</div><div class='add'>+				struct dc_crtc_timing *crtc_timing);</div><div class='add'>+</div><div class='add'>+enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);</div><div class='add'>+</div><div class='add'>+enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='add'>+					const struct dc_validation_set set[],</div><div class='add'>+					int set_count,</div><div class='add'>+					struct dc_state *context,</div><div class='add'>+					enum dc_validate_mode validate_mode);</div><div class='add'>+</div><div class='add'>+bool dc_set_generic_gpio_for_stereo(bool enable,</div><div class='add'>+		struct gpio_service *gpio_service);</div><div class='add'>+</div><div class='add'>+enum dc_status dc_validate_global_state(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *new_ctx,</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='add'>+</div><div class='add'>+bool dc_acquire_release_mpc_3dlut(</div><div class='add'>+		struct dc *dc, bool acquire,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_3dlut **lut,</div><div class='add'>+		struct dc_transfer_func **shaper);</div><div class='add'>+</div><div class='add'>+bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);</div><div class='add'>+void get_audio_check(struct audio_info *aud_modes,</div><div class='add'>+	struct audio_check *aud_chk);</div><div class='add'>+</div><div class='add'>+bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);</div><div class='add'>+void populate_fast_updates(struct dc_fast_update *fast_update,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count,</div><div class='add'>+		struct dc_stream_update *stream_update);</div><div class='add'>+/*</div><div class='add'>+ * Set up streams and links associated to drive sinks</div><div class='add'>+ * The streams parameter is an absolute set of all active streams.</div><div class='add'>+ *</div><div class='add'>+ * After this call:</div><div class='add'>+ *   Phy, Encoder, Timing Generator are programmed and enabled.</div><div class='add'>+ *   New streams are enabled with blank stream; no memory read.</div><div class='add'>+ */</div><div class='add'>+enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		int mpcc_inst);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);</div><div class='add'>+</div><div class='add'>+void dc_set_disable_128b_132b_stream_overhead(bool disable);</div><div class='add'>+</div><div class='add'>+/* The function returns minimum bandwidth required to drive a given timing</div><div class='add'>+ * return - minimum required timing bandwidth in kbps.</div><div class='add'>+ */</div><div class='add'>+uint32_t dc_bandwidth_in_kbps_from_timing(</div><div class='add'>+		const struct dc_crtc_timing *timing,</div><div class='add'>+		const enum dc_link_encoding_format link_encoding);</div><div class='add'>+</div><div class='add'>+/* Link Interfaces */</div><div class='ctx'> /* Return an enumerated dc_link.</div><div class='ctx'>  * dc_link order is constant and determined at</div><div class='ctx'>  * boot time.  They cannot be created or destroyed.</div><div class='hunk'>@@ -1801,6 +2119,9 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,</div><div class='ctx'> 		struct aux_payload *payload,</div><div class='ctx'> 		enum aux_return_code_type *operation_result);</div><div class='ctx'> </div><div class='add'>+struct ddc_service *</div><div class='add'>+dc_get_oem_i2c_device(struct dc *dc);</div><div class='add'>+</div><div class='ctx'> bool dc_is_oem_i2c_device_present(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	size_t slave_address</div><div class='hunk'>@@ -1881,6 +2202,24 @@ uint32_t dc_link_bandwidth_kbps(</div><div class='ctx'> 	const struct dc_link *link,</div><div class='ctx'> 	const struct dc_link_settings *link_setting);</div><div class='ctx'> </div><div class='add'>+struct dp_audio_bandwidth_params {</div><div class='add'>+	const struct dc_crtc_timing *crtc_timing;</div><div class='add'>+	enum dp_link_encoding link_encoding;</div><div class='add'>+	uint32_t channel_count;</div><div class='add'>+	uint32_t sample_rate_hz;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* The function calculates the minimum size of hblank (in bytes) needed to</div><div class='add'>+ * support the specified channel count and sample rate combination, given the</div><div class='add'>+ * link encoding and timing to be used. This calculation is not supported</div><div class='add'>+ * for 8b/10b SST.</div><div class='add'>+ *</div><div class='add'>+ * return - min hblank size in bytes, 0 if 8b/10b SST.</div><div class='add'>+ */</div><div class='add'>+uint32_t dc_link_required_hblank_size_bytes(</div><div class='add'>+	const struct dc_link *link,</div><div class='add'>+	struct dp_audio_bandwidth_params *audio_params);</div><div class='add'>+</div><div class='ctx'> /* The function takes a snapshot of current link resource allocation state</div><div class='ctx'>  * @dc: pointer to dc of the dm calling this</div><div class='ctx'>  * @map: a dc link resource snapshot defined internally to dc.</div><div class='hunk'>@@ -2075,8 +2414,7 @@ void dc_link_edp_panel_backlight_power_on(struct dc_link *link,</div><div class='ctx'>  * and 16 bit fractional, where 1.0 is max backlight value.</div><div class='ctx'>  */</div><div class='ctx'> bool dc_link_set_backlight_level(const struct dc_link *dc_link,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp);</div><div class='add'>+		struct set_backlight_level_params *backlight_level_params);</div><div class='ctx'> </div><div class='ctx'> /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */</div><div class='ctx'> bool dc_link_set_backlight_level_nits(struct dc_link *link,</div><div class='hunk'>@@ -2179,19 +2517,6 @@ unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);</div><div class='ctx'> void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Handle function for when the status of the Request above is complete.</div><div class='del'>- * We will find out the result of allocating on CM and update structs.</div><div class='del'>- *</div><div class='del'>- * @link: pointer to the dc_link struct instance</div><div class='del'>- * @bw: Allocated or Estimated BW depending on the result</div><div class='del'>- * @result: Response type</div><div class='del'>- *</div><div class='del'>- * return: none</div><div class='del'>- */</div><div class='del'>-void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,</div><div class='del'>-		uint8_t bw, uint8_t result);</div><div class='del'>-</div><div class='del'>-/*</div><div class='ctx'>  * Handle the USB4 BW Allocation related functionality here:</div><div class='ctx'>  * Plug =&gt; Try to allocate max bw from timing parameters supported by the sink</div><div class='ctx'>  * Unplug =&gt; de-allocate bw</div><div class='hunk'>@@ -2199,23 +2524,23 @@ void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,</div><div class='ctx'>  * @link: pointer to the dc_link struct instance</div><div class='ctx'>  * @peak_bw: Peak bw used by the link/sink</div><div class='ctx'>  *</div><div class='del'>- * return: allocated bw else return 0</div><div class='ctx'>  */</div><div class='del'>-int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(</div><div class='add'>+void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(</div><div class='ctx'> 		struct dc_link *link, int peak_bw);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Validate the BW of all the valid DPIA links to make sure it doesn't exceed</div><div class='del'>- * available BW for each host router</div><div class='del'>- *</div><div class='del'>- * @dc: pointer to dc struct</div><div class='del'>- * @stream: pointer to all possible streams</div><div class='del'>- * @count: number of valid DPIA streams</div><div class='add'>+ * Calculates the DP tunneling bandwidth required for the stream timing</div><div class='add'>+ * and aggregates the stream bandwidth for the respective DP tunneling link</div><div class='ctx'>  *</div><div class='del'>- * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE</div><div class='add'>+ * return: dc_status</div><div class='ctx'>  */</div><div class='del'>-bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,</div><div class='del'>-		const unsigned int count);</div><div class='add'>+enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Get if ALPM is supported by the link</div><div class='add'>+ */</div><div class='add'>+void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support,</div><div class='add'>+	bool *auxwake_support);</div><div class='ctx'> </div><div class='ctx'> /* Sink Interfaces - A sink corresponds to a display output device */</div><div class='ctx'> </div><div class='hunk'>@@ -2241,6 +2566,13 @@ struct dc_sink_dsc_caps {</div><div class='ctx'> 	struct dsc_dec_dpcd_caps dsc_dec_caps;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dc_sink_hblank_expansion_caps {</div><div class='add'>+	// 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology),</div><div class='add'>+	// 'false' if they are sink's HBlank expansion caps</div><div class='add'>+	bool is_virtual_dpcd_hblank_expansion;</div><div class='add'>+	struct hblank_expansion_dpcd_caps dpcd_caps;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dc_sink_fec_caps {</div><div class='ctx'> 	bool is_rx_fec_supported;</div><div class='ctx'> 	bool is_topology_fec_supported;</div><div class='hunk'>@@ -2267,6 +2599,7 @@ struct dc_sink {</div><div class='ctx'> 	struct scdc_caps scdc_caps;</div><div class='ctx'> 	struct dc_sink_dsc_caps dsc_caps;</div><div class='ctx'> 	struct dc_sink_fec_caps fec_caps;</div><div class='add'>+	struct dc_sink_hblank_expansion_caps hblank_expansion_caps;</div><div class='ctx'> </div><div class='ctx'> 	bool is_vsc_sdp_colorimetry_supported;</div><div class='ctx'> </div><div class='hunk'>@@ -2335,11 +2668,17 @@ bool dc_is_dmcu_initialized(struct dc *dc);</div><div class='ctx'> enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);</div><div class='ctx'> void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);</div><div class='ctx'> </div><div class='del'>-bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,</div><div class='del'>-				struct dc_cursor_attributes *cursor_attr);</div><div class='add'>+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,</div><div class='add'>+		unsigned int pitch,</div><div class='add'>+		unsigned int height,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		struct dc_cursor_attributes *cursor_attr);</div><div class='add'>+</div><div class='add'>+#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)</div><div class='add'>+#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)</div><div class='ctx'> </div><div class='del'>-void dc_allow_idle_optimizations(struct dc *dc, bool allow);</div><div class='del'>-void dc_exit_ips_for_hw_access(struct dc *dc);</div><div class='add'>+void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);</div><div class='add'>+void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);</div><div class='ctx'> bool dc_dmub_is_ips_idle_state(struct dc *dc);</div><div class='ctx'> </div><div class='ctx'> /* set min and max memory clock to lowest and highest DPM level, respectively */</div><div class='hunk'>@@ -2361,6 +2700,8 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable);</div><div class='ctx'> </div><div class='ctx'> bool dc_set_replay_allow_active(struct dc *dc, bool active);</div><div class='ctx'> </div><div class='add'>+bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);</div><div class='add'>+</div><div class='ctx'> void dc_z10_restore(const struct dc *dc);</div><div class='ctx'> void dc_z10_save_init(struct dc *dc);</div><div class='ctx'> </div><div class='hunk'>@@ -2378,6 +2719,13 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,</div><div class='ctx'> 				uint32_t link_index,</div><div class='ctx'> 				struct aux_payload *payload);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * smart power OLED Interfaces</div><div class='add'>+ */</div><div class='add'>+bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits,</div><div class='add'>+	uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline);</div><div class='add'>+bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL);</div><div class='add'>+</div><div class='ctx'> /* Get dc link index from dpia port index */</div><div class='ctx'> uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,</div><div class='ctx'> 				uint8_t dpia_port_index);</div><div class='hunk'>@@ -2392,6 +2740,8 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,</div><div class='ctx'> 				uint8_t mst_alloc_slots,</div><div class='ctx'> 				uint8_t *mst_slots_in_use);</div><div class='ctx'> </div><div class='add'>+void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);</div><div class='add'>+</div><div class='ctx'> void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,</div><div class='ctx'> 				uint32_t hpd_int_enable);</div><div class='ctx'> </div><div class='hunk'>@@ -2405,13 +2755,529 @@ struct dc_power_profile {</div><div class='ctx'> </div><div class='ctx'> struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);</div><div class='ctx'> </div><div class='add'>+unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);</div><div class='add'>+</div><div class='add'>+bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index);</div><div class='add'>+</div><div class='add'>+void dc_log_preos_dmcub_info(const struct dc *dc);</div><div class='add'>+</div><div class='ctx'> /* DSC Interfaces */</div><div class='ctx'> #include "dc_dsc.h"</div><div class='ctx'> </div><div class='add'>+void dc_get_visual_confirm_for_stream(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_stream_state *stream_state,</div><div class='add'>+	struct tg_color *color);</div><div class='add'>+</div><div class='ctx'> /* Disable acc mode Interfaces */</div><div class='ctx'> void dc_disable_accelerated_mode(struct dc *dc);</div><div class='ctx'> </div><div class='ctx'> bool dc_is_timing_changed(struct dc_stream_state *cur_stream,</div><div class='ctx'> 		       struct dc_stream_state *new_stream);</div><div class='ctx'> </div><div class='add'>+bool dc_is_cursor_limit_pending(struct dc *dc);</div><div class='add'>+bool dc_can_clear_cursor_limit(const struct dc *dc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data.</div><div class='add'>+ *</div><div class='add'>+ * @dc: Pointer to the display core context.</div><div class='add'>+ * @primary_otg_inst: Instance index of the primary OTG that underflowed.</div><div class='add'>+ * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information.</div><div class='add'>+ *</div><div class='add'>+ * This function collects and logs underflow-related HW states when underflow happens,</div><div class='add'>+ * including OTG underflow status, current read positions, frame count, and per-HUBP debug data.</div><div class='add'>+ * The results are stored in the provided out_data structure for further analysis or logging.</div><div class='add'>+ */</div><div class='add'>+void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data);</div><div class='add'>+</div><div class='add'>+void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Software state variables used to program register fields across the display pipeline</div><div class='add'>+ */</div><div class='add'>+struct dc_register_software_state {</div><div class='add'>+	/* HUBP register programming variables for each pipe */</div><div class='add'>+	struct {</div><div class='add'>+		bool valid_plane_state;</div><div class='add'>+		bool valid_stream;</div><div class='add'>+		bool min_dc_gfx_version9;</div><div class='add'>+		uint32_t vtg_sel;                        /* DCHUBP_CNTL-&gt;HUBP_VTG_SEL from pipe_ctx-&gt;stream_res.tg-&gt;inst */</div><div class='add'>+		uint32_t hubp_clock_enable;              /* HUBP_CLK_CNTL-&gt;HUBP_CLOCK_ENABLE from power management */</div><div class='add'>+		uint32_t surface_pixel_format;           /* DCSURF_SURFACE_CONFIG-&gt;SURFACE_PIXEL_FORMAT from plane_state-&gt;format */</div><div class='add'>+		uint32_t rotation_angle;                 /* DCSURF_SURFACE_CONFIG-&gt;ROTATION_ANGLE from plane_state-&gt;rotation */</div><div class='add'>+		uint32_t h_mirror_en;                    /* DCSURF_SURFACE_CONFIG-&gt;H_MIRROR_EN from plane_state-&gt;horizontal_mirror */</div><div class='add'>+		uint32_t surface_dcc_en;                 /* DCSURF_SURFACE_CONTROL-&gt;PRIMARY_SURFACE_DCC_EN from dcc-&gt;enable */</div><div class='add'>+		uint32_t surface_size_width;             /* HUBP_SIZE-&gt;SURFACE_SIZE_WIDTH from plane_size.surface_size.width */</div><div class='add'>+		uint32_t surface_size_height;            /* HUBP_SIZE-&gt;SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */</div><div class='add'>+		uint32_t pri_viewport_width;             /* DCSURF_PRI_VIEWPORT_DIMENSION-&gt;PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */</div><div class='add'>+		uint32_t pri_viewport_height;            /* DCSURF_PRI_VIEWPORT_DIMENSION-&gt;PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */</div><div class='add'>+		uint32_t pri_viewport_x_start;           /* DCSURF_PRI_VIEWPORT_START-&gt;PRI_VIEWPORT_X_START from scaler_data.viewport.x */</div><div class='add'>+		uint32_t pri_viewport_y_start;           /* DCSURF_PRI_VIEWPORT_START-&gt;PRI_VIEWPORT_Y_START from scaler_data.viewport.y */</div><div class='add'>+		uint32_t cursor_enable;                  /* CURSOR_CONTROL-&gt;CURSOR_ENABLE from cursor_attributes.enable */</div><div class='add'>+		uint32_t cursor_width;                   /* CURSOR_SETTINGS-&gt;CURSOR_WIDTH from cursor_position.width */</div><div class='add'>+		uint32_t cursor_height;                  /* CURSOR_SETTINGS-&gt;CURSOR_HEIGHT from cursor_position.height */</div><div class='add'>+</div><div class='add'>+		/* Additional DCC configuration */</div><div class='add'>+		uint32_t surface_dcc_ind_64b_blk;        /* DCSURF_SURFACE_CONTROL-&gt;PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */</div><div class='add'>+		uint32_t surface_dcc_ind_128b_blk;       /* DCSURF_SURFACE_CONTROL-&gt;PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */</div><div class='add'>+</div><div class='add'>+		/* Surface pitch configuration */</div><div class='add'>+		uint32_t surface_pitch;                  /* DCSURF_SURFACE_PITCH-&gt;PITCH from plane_size.surface_pitch */</div><div class='add'>+		uint32_t meta_pitch;                     /* DCSURF_SURFACE_PITCH-&gt;META_PITCH from dcc.meta_pitch */</div><div class='add'>+		uint32_t chroma_pitch;                   /* DCSURF_SURFACE_PITCH_C-&gt;PITCH_C from plane_size.chroma_pitch */</div><div class='add'>+		uint32_t meta_pitch_c;                   /* DCSURF_SURFACE_PITCH_C-&gt;META_PITCH_C from dcc.meta_pitch_c */</div><div class='add'>+</div><div class='add'>+		/* Surface addresses */</div><div class='add'>+		uint32_t primary_surface_address_low;    /* DCSURF_PRIMARY_SURFACE_ADDRESS-&gt;PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */</div><div class='add'>+		uint32_t primary_surface_address_high;   /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH-&gt;PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */</div><div class='add'>+		uint32_t primary_meta_surface_address_low;  /* DCSURF_PRIMARY_META_SURFACE_ADDRESS-&gt;PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */</div><div class='add'>+		uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH-&gt;PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */</div><div class='add'>+</div><div class='add'>+		/* TMZ configuration */</div><div class='add'>+		uint32_t primary_surface_tmz;            /* DCSURF_SURFACE_CONTROL-&gt;PRIMARY_SURFACE_TMZ from address.tmz_surface */</div><div class='add'>+		uint32_t primary_meta_surface_tmz;       /* DCSURF_SURFACE_CONTROL-&gt;PRIMARY_META_SURFACE_TMZ from address.tmz_surface */</div><div class='add'>+</div><div class='add'>+		/* Tiling configuration */</div><div class='add'>+		uint32_t sw_mode;                        /* DCSURF_TILING_CONFIG-&gt;SW_MODE from tiling_info.gfx9.swizzle */</div><div class='add'>+		uint32_t num_pipes;                      /* DCSURF_ADDR_CONFIG-&gt;NUM_PIPES from tiling_info.gfx9.num_pipes */</div><div class='add'>+		uint32_t num_banks;                      /* DCSURF_ADDR_CONFIG-&gt;NUM_BANKS from tiling_info.gfx9.num_banks */</div><div class='add'>+		uint32_t pipe_interleave;                /* DCSURF_ADDR_CONFIG-&gt;PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */</div><div class='add'>+		uint32_t num_shader_engines;             /* DCSURF_ADDR_CONFIG-&gt;NUM_SE from tiling_info.gfx9.num_shader_engines */</div><div class='add'>+		uint32_t num_rb_per_se;                  /* DCSURF_ADDR_CONFIG-&gt;NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */</div><div class='add'>+		uint32_t num_pkrs;                       /* DCSURF_ADDR_CONFIG-&gt;NUM_PKRS from tiling_info.gfx9.num_pkrs */</div><div class='add'>+</div><div class='add'>+		/* DML Request Size Configuration - Luma */</div><div class='add'>+		uint32_t rq_chunk_size;                  /* DCHUBP_REQ_SIZE_CONFIG-&gt;CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */</div><div class='add'>+		uint32_t rq_min_chunk_size;              /* DCHUBP_REQ_SIZE_CONFIG-&gt;MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */</div><div class='add'>+		uint32_t rq_meta_chunk_size;             /* DCHUBP_REQ_SIZE_CONFIG-&gt;META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */</div><div class='add'>+		uint32_t rq_min_meta_chunk_size;         /* DCHUBP_REQ_SIZE_CONFIG-&gt;MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */</div><div class='add'>+		uint32_t rq_dpte_group_size;             /* DCHUBP_REQ_SIZE_CONFIG-&gt;DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */</div><div class='add'>+		uint32_t rq_mpte_group_size;             /* DCHUBP_REQ_SIZE_CONFIG-&gt;MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */</div><div class='add'>+		uint32_t rq_swath_height_l;              /* DCHUBP_REQ_SIZE_CONFIG-&gt;SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */</div><div class='add'>+		uint32_t rq_pte_row_height_l;            /* DCHUBP_REQ_SIZE_CONFIG-&gt;PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */</div><div class='add'>+</div><div class='add'>+		/* DML Request Size Configuration - Chroma */</div><div class='add'>+		uint32_t rq_chunk_size_c;                /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */</div><div class='add'>+		uint32_t rq_min_chunk_size_c;            /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */</div><div class='add'>+		uint32_t rq_meta_chunk_size_c;           /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */</div><div class='add'>+		uint32_t rq_min_meta_chunk_size_c;       /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */</div><div class='add'>+		uint32_t rq_dpte_group_size_c;           /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */</div><div class='add'>+		uint32_t rq_mpte_group_size_c;           /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */</div><div class='add'>+		uint32_t rq_swath_height_c;              /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */</div><div class='add'>+		uint32_t rq_pte_row_height_c;            /* DCHUBP_REQ_SIZE_CONFIG_C-&gt;PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */</div><div class='add'>+</div><div class='add'>+		/* DML Expansion Modes */</div><div class='add'>+		uint32_t drq_expansion_mode;             /* DCN_EXPANSION_MODE-&gt;DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */</div><div class='add'>+		uint32_t prq_expansion_mode;             /* DCN_EXPANSION_MODE-&gt;PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */</div><div class='add'>+		uint32_t mrq_expansion_mode;             /* DCN_EXPANSION_MODE-&gt;MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */</div><div class='add'>+		uint32_t crq_expansion_mode;             /* DCN_EXPANSION_MODE-&gt;CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */</div><div class='add'>+</div><div class='add'>+		/* DML DLG parameters - nominal */</div><div class='add'>+		uint32_t dst_y_per_vm_vblank;            /* NOM_PARAMETERS_0-&gt;DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */</div><div class='add'>+		uint32_t dst_y_per_row_vblank;           /* NOM_PARAMETERS_0-&gt;DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */</div><div class='add'>+		uint32_t dst_y_per_vm_flip;              /* NOM_PARAMETERS_1-&gt;DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */</div><div class='add'>+		uint32_t dst_y_per_row_flip;             /* NOM_PARAMETERS_1-&gt;DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */</div><div class='add'>+</div><div class='add'>+		/* DML prefetch settings */</div><div class='add'>+		uint32_t dst_y_prefetch;                 /* PREFETCH_SETTINS-&gt;DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */</div><div class='add'>+		uint32_t vratio_prefetch;                /* PREFETCH_SETTINS-&gt;VRATIO_PREFETCH from dlg_regs.vratio_prefetch */</div><div class='add'>+		uint32_t vratio_prefetch_c;              /* PREFETCH_SETTINS_C-&gt;VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */</div><div class='add'>+</div><div class='add'>+		/* TTU parameters */</div><div class='add'>+		uint32_t qos_level_low_wm;               /* TTU_CNTL1-&gt;QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */</div><div class='add'>+		uint32_t qos_level_high_wm;              /* TTU_CNTL1-&gt;QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */</div><div class='add'>+		uint32_t qos_level_flip;                 /* TTU_CNTL2-&gt;QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */</div><div class='add'>+		uint32_t min_ttu_vblank;                 /* DCN_GLOBAL_TTU_CNTL-&gt;MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */</div><div class='add'>+	} hubp[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	/* HUBBUB register programming variables */</div><div class='add'>+	struct {</div><div class='add'>+		/* Individual DET buffer control per pipe - software state that programs DET registers */</div><div class='add'>+		uint32_t det0_size;                      /* DCHUBBUB_DET0_CTRL-&gt;DET0_SIZE from hubbub-&gt;funcs-&gt;program_det_size(hubbub, 0, det_buffer_size_kb) */</div><div class='add'>+		uint32_t det1_size;                      /* DCHUBBUB_DET1_CTRL-&gt;DET1_SIZE from hubbub-&gt;funcs-&gt;program_det_size(hubbub, 1, det_buffer_size_kb) */</div><div class='add'>+		uint32_t det2_size;                      /* DCHUBBUB_DET2_CTRL-&gt;DET2_SIZE from hubbub-&gt;funcs-&gt;program_det_size(hubbub, 2, det_buffer_size_kb) */</div><div class='add'>+		uint32_t det3_size;                      /* DCHUBBUB_DET3_CTRL-&gt;DET3_SIZE from hubbub-&gt;funcs-&gt;program_det_size(hubbub, 3, det_buffer_size_kb) */</div><div class='add'>+</div><div class='add'>+		/* Compression buffer control - software state that programs COMPBUF registers */</div><div class='add'>+		uint32_t compbuf_size;                   /* DCHUBBUB_COMPBUF_CTRL-&gt;COMPBUF_SIZE from hubbub-&gt;funcs-&gt;program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */</div><div class='add'>+		uint32_t compbuf_reserved_space_64b;     /* COMPBUF_RESERVED_SPACE-&gt;COMPBUF_RESERVED_SPACE_64B from hubbub2-&gt;pixel_chunk_size / 32 */</div><div class='add'>+		uint32_t compbuf_reserved_space_zs;      /* COMPBUF_RESERVED_SPACE-&gt;COMPBUF_RESERVED_SPACE_ZS from hubbub2-&gt;pixel_chunk_size / 128 */</div><div class='add'>+	} hubbub;</div><div class='add'>+</div><div class='add'>+	/* DPP register programming variables for each pipe (simplified for available fields) */</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t dpp_clock_enable;               /* DPP_CONTROL-&gt;DPP_CLOCK_ENABLE from dppclk_enable */</div><div class='add'>+</div><div class='add'>+		/* Recout (Rectangle of Interest) configuration */</div><div class='add'>+		uint32_t recout_start_x;                 /* RECOUT_START-&gt;RECOUT_START_X from pipe_ctx-&gt;plane_res.scl_data.recout.x */</div><div class='add'>+		uint32_t recout_start_y;                 /* RECOUT_START-&gt;RECOUT_START_Y from pipe_ctx-&gt;plane_res.scl_data.recout.y */</div><div class='add'>+		uint32_t recout_width;                   /* RECOUT_SIZE-&gt;RECOUT_WIDTH from pipe_ctx-&gt;plane_res.scl_data.recout.width */</div><div class='add'>+		uint32_t recout_height;                  /* RECOUT_SIZE-&gt;RECOUT_HEIGHT from pipe_ctx-&gt;plane_res.scl_data.recout.height */</div><div class='add'>+</div><div class='add'>+		/* MPC (Multiple Pipe/Plane Combiner) size configuration */</div><div class='add'>+		uint32_t mpc_width;                      /* MPC_SIZE-&gt;MPC_WIDTH from pipe_ctx-&gt;plane_res.scl_data.h_active */</div><div class='add'>+		uint32_t mpc_height;                     /* MPC_SIZE-&gt;MPC_HEIGHT from pipe_ctx-&gt;plane_res.scl_data.v_active */</div><div class='add'>+</div><div class='add'>+		/* DSCL mode configuration */</div><div class='add'>+		uint32_t dscl_mode;                      /* SCL_MODE-&gt;DSCL_MODE from pipe_ctx-&gt;plane_res.scl_data.dscl_prog_data.dscl_mode */</div><div class='add'>+</div><div class='add'>+		/* Scaler ratios (simplified to integer parts) */</div><div class='add'>+		uint32_t horz_ratio_int;                 /* SCL_HORZ_FILTER_SCALE_RATIO-&gt;SCL_H_SCALE_RATIO integer part from ratios.horz */</div><div class='add'>+		uint32_t vert_ratio_int;                 /* SCL_VERT_FILTER_SCALE_RATIO-&gt;SCL_V_SCALE_RATIO integer part from ratios.vert */</div><div class='add'>+</div><div class='add'>+		/* Basic scaler taps */</div><div class='add'>+		uint32_t h_taps;                         /* SCL_TAP_CONTROL-&gt;SCL_H_NUM_TAPS from taps.h_taps */</div><div class='add'>+		uint32_t v_taps;                         /* SCL_TAP_CONTROL-&gt;SCL_V_NUM_TAPS from taps.v_taps */</div><div class='add'>+	} dpp[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	/* DCCG register programming variables */</div><div class='add'>+	struct {</div><div class='add'>+		/* Core Display Clock Control */</div><div class='add'>+		uint32_t dispclk_khz;                    /* DENTIST_DISPCLK_CNTL-&gt;DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */</div><div class='add'>+		uint32_t dc_mem_global_pwr_req_dis;      /* DC_MEM_GLOBAL_PWR_REQ_CNTL-&gt;DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */</div><div class='add'>+</div><div class='add'>+		/* DPP Clock Control - 4 fields per pipe */</div><div class='add'>+		uint32_t dppclk_khz[MAX_PIPES];          /* DPPCLK_CTRL-&gt;DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */</div><div class='add'>+		uint32_t dppclk_enable[MAX_PIPES];       /* DPPCLK_CTRL-&gt;DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */</div><div class='add'>+		uint32_t dppclk_dto_enable[MAX_PIPES];   /* DPPCLK_DTO_CTRL-&gt;DPPCLK_DTO_ENABLE from dccg-&gt;dpp_clock_gated[dpp_inst] state */</div><div class='add'>+		uint32_t dppclk_dto_phase[MAX_PIPES];    /* DPPCLK0_DTO_PARAM-&gt;DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */</div><div class='add'>+		uint32_t dppclk_dto_modulo[MAX_PIPES];   /* DPPCLK0_DTO_PARAM-&gt;DPPCLK0_DTO_MODULO from modulo = 0xff */</div><div class='add'>+</div><div class='add'>+		/* DSC Clock Control - 4 fields per DSC resource */</div><div class='add'>+		uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL-&gt;DSCCLK_DTO_ENABLE from dsc_clocks */</div><div class='add'>+		uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL-&gt;DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */</div><div class='add'>+		uint32_t dscclk_dto_phase[MAX_PIPES];  /* DSCCLK0_DTO_PARAM-&gt;DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */</div><div class='add'>+		uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM-&gt;DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */</div><div class='add'>+</div><div class='add'>+		/* Pixel Clock Control - per pipe */</div><div class='add'>+		uint32_t pixclk_khz[MAX_PIPES];          /* PIXCLK_RESYNC_CNTL-&gt;PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */</div><div class='add'>+		uint32_t otg_pixel_rate_div[MAX_PIPES];  /* OTG_PIXEL_RATE_DIV-&gt;OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */</div><div class='add'>+		uint32_t dtbclk_dto_enable[MAX_PIPES];   /* OTG0_PIXEL_RATE_CNTL-&gt;DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */</div><div class='add'>+		uint32_t pipe_dto_src_sel[MAX_PIPES];    /* OTG0_PIXEL_RATE_CNTL-&gt;PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */</div><div class='add'>+		uint32_t dtbclk_dto_div[MAX_PIPES];      /* OTG0_PIXEL_RATE_CNTL-&gt;DTBCLK_DTO_DIV from dtbdto_div calculation */</div><div class='add'>+		uint32_t otg_add_pixel[MAX_PIPES];       /* OTG0_PIXEL_RATE_CNTL-&gt;OTG_ADD_PIXEL from dccg31_otg_add_pixel() */</div><div class='add'>+		uint32_t otg_drop_pixel[MAX_PIPES];      /* OTG0_PIXEL_RATE_CNTL-&gt;OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */</div><div class='add'>+</div><div class='add'>+		/* DTBCLK DTO Control - 4 DTOs */</div><div class='add'>+		uint32_t dtbclk_dto_modulo[4];           /* DTBCLK_DTO0_MODULO-&gt;DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */</div><div class='add'>+		uint32_t dtbclk_dto_phase[4];            /* DTBCLK_DTO0_PHASE-&gt;DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */</div><div class='add'>+		uint32_t dtbclk_dto_dbuf_en;             /* DTBCLK_DTO_DBUF_EN-&gt;DTBCLK DTO data buffer enable */</div><div class='add'>+</div><div class='add'>+		/* DP Stream Clock Control - 4 pipes */</div><div class='add'>+		uint32_t dpstreamclk_enable[MAX_PIPES];          /* DPSTREAMCLK_CNTL-&gt;DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */</div><div class='add'>+		uint32_t dp_dto_modulo[4];               /* DP_DTO0_MODULO-&gt;DP_DTO0_MODULO from DP stream DTO programming */</div><div class='add'>+		uint32_t dp_dto_phase[4];                /* DP_DTO0_PHASE-&gt;DP_DTO0_PHASE from DP stream DTO programming */</div><div class='add'>+		uint32_t dp_dto_dbuf_en;                 /* DP_DTO_DBUF_EN-&gt;DP DTO data buffer enable */</div><div class='add'>+</div><div class='add'>+		/* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */</div><div class='add'>+		uint32_t phy_symclk_force_en[5];         /* PHYASYMCLK_CLOCK_CNTL-&gt;PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */</div><div class='add'>+		uint32_t phy_symclk_force_src_sel[5];    /* PHYASYMCLK_CLOCK_CNTL-&gt;PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */</div><div class='add'>+		uint32_t phy_symclk_gate_disable[5];     /* DCCG_GATE_DISABLE_CNTL2-&gt;PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */</div><div class='add'>+</div><div class='add'>+		/* SYMCLK32 SE Control - 4 instances */</div><div class='add'>+		uint32_t symclk32_se_src_sel[4];         /* SYMCLK32_SE_CNTL-&gt;SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */</div><div class='add'>+		uint32_t symclk32_se_enable[4];          /* SYMCLK32_SE_CNTL-&gt;SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */</div><div class='add'>+		uint32_t symclk32_se_gate_disable[4];    /* DCCG_GATE_DISABLE_CNTL3-&gt;SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */</div><div class='add'>+</div><div class='add'>+		/* SYMCLK32 LE Control - 2 instances */</div><div class='add'>+		uint32_t symclk32_le_src_sel[2];         /* SYMCLK32_LE_CNTL-&gt;SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */</div><div class='add'>+		uint32_t symclk32_le_enable[2];          /* SYMCLK32_LE_CNTL-&gt;SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */</div><div class='add'>+		uint32_t symclk32_le_gate_disable[2];    /* DCCG_GATE_DISABLE_CNTL3-&gt;SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */</div><div class='add'>+</div><div class='add'>+		/* DPIA Clock Control */</div><div class='add'>+		uint32_t dpiaclk_540m_dto_modulo;        /* DPIACLK_540M_DTO_MODULO-&gt;DPIA 540MHz DTO modulo */</div><div class='add'>+		uint32_t dpiaclk_540m_dto_phase;         /* DPIACLK_540M_DTO_PHASE-&gt;DPIA 540MHz DTO phase */</div><div class='add'>+		uint32_t dpiaclk_810m_dto_modulo;        /* DPIACLK_810M_DTO_MODULO-&gt;DPIA 810MHz DTO modulo */</div><div class='add'>+		uint32_t dpiaclk_810m_dto_phase;         /* DPIACLK_810M_DTO_PHASE-&gt;DPIA 810MHz DTO phase */</div><div class='add'>+		uint32_t dpiaclk_dto_cntl;               /* DPIACLK_DTO_CNTL-&gt;DPIA clock DTO control */</div><div class='add'>+		uint32_t dpiasymclk_cntl;                /* DPIASYMCLK_CNTL-&gt;DPIA symbol clock control */</div><div class='add'>+</div><div class='add'>+		/* Clock Gating Control */</div><div class='add'>+		uint32_t dccg_gate_disable_cntl;         /* DCCG_GATE_DISABLE_CNTL-&gt;Clock gate disable control from dccg31_init() */</div><div class='add'>+		uint32_t dpstreamclk_gate_disable;       /* DCCG_GATE_DISABLE_CNTL3-&gt;DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */</div><div class='add'>+		uint32_t dpstreamclk_root_gate_disable;  /* DCCG_GATE_DISABLE_CNTL3-&gt;DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */</div><div class='add'>+</div><div class='add'>+		/* VSync Control */</div><div class='add'>+		uint32_t vsync_cnt_ctrl;                 /* DCCG_VSYNC_CNT_CTRL-&gt;VSync counter control */</div><div class='add'>+		uint32_t vsync_cnt_int_ctrl;             /* DCCG_VSYNC_CNT_INT_CTRL-&gt;VSync counter interrupt control */</div><div class='add'>+		uint32_t vsync_otg_latch_value[6];       /* DCCG_VSYNC_OTG0_LATCH_VALUE-&gt;OTG0 VSync latch value (for OTG0-5) */</div><div class='add'>+</div><div class='add'>+		/* Time Base Control */</div><div class='add'>+		uint32_t microsecond_time_base_div;      /* MICROSECOND_TIME_BASE_DIV-&gt;Microsecond time base divider */</div><div class='add'>+		uint32_t millisecond_time_base_div;      /* MILLISECOND_TIME_BASE_DIV-&gt;Millisecond time base divider */</div><div class='add'>+	} dccg;</div><div class='add'>+</div><div class='add'>+	/* DSC essential configuration for underflow analysis */</div><div class='add'>+	struct {</div><div class='add'>+		/* DSC active state - critical for bandwidth analysis */</div><div class='add'>+		uint32_t dsc_clock_enable;               /* DSC enabled - affects bandwidth requirements */</div><div class='add'>+</div><div class='add'>+		/* DSC configuration affecting bandwidth and timing */</div><div class='add'>+		uint32_t dsc_num_slices_h;              /* Horizontal slice count - affects throughput */</div><div class='add'>+		uint32_t dsc_num_slices_v;              /* Vertical slice count - affects throughput */</div><div class='add'>+		uint32_t dsc_bits_per_pixel;            /* Compression ratio - affects bandwidth */</div><div class='add'>+</div><div class='add'>+		/* OPP integration - affects pipeline flow */</div><div class='add'>+		uint32_t dscrm_dsc_forward_enable;      /* DSC forwarding to OPP enabled */</div><div class='add'>+		uint32_t dscrm_dsc_opp_pipe_source;    /* Which OPP receives DSC output */</div><div class='add'>+	} dsc[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	/* MPC register programming variables */</div><div class='add'>+	struct {</div><div class='add'>+		/* MPCC blending tree and mode control */</div><div class='add'>+		uint32_t mpcc_mode[MAX_PIPES];           /* MPCC_CONTROL-&gt;MPCC_MODE from blend_cfg.blend_mode */</div><div class='add'>+		uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL-&gt;MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */</div><div class='add'>+		uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL-&gt;MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */</div><div class='add'>+		uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL-&gt;MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */</div><div class='add'>+		uint32_t mpcc_global_alpha[MAX_PIPES];   /* MPCC_CONTROL-&gt;MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */</div><div class='add'>+		uint32_t mpcc_global_gain[MAX_PIPES];    /* MPCC_CONTROL-&gt;MPCC_GLOBAL_GAIN from blend_cfg.global_gain */</div><div class='add'>+		uint32_t mpcc_bg_bpc[MAX_PIPES];         /* MPCC_CONTROL-&gt;MPCC_BG_BPC from background color depth */</div><div class='add'>+		uint32_t mpcc_bot_gain_mode[MAX_PIPES];  /* MPCC_CONTROL-&gt;MPCC_BOT_GAIN_MODE from bottom layer gain control */</div><div class='add'>+</div><div class='add'>+		/* MPCC blending tree connections */</div><div class='add'>+		uint32_t mpcc_bot_sel[MAX_PIPES];        /* MPCC_BOT_SEL-&gt;MPCC_BOT_SEL from mpcc_state-&gt;bot_sel */</div><div class='add'>+		uint32_t mpcc_top_sel[MAX_PIPES];        /* MPCC_TOP_SEL-&gt;MPCC_TOP_SEL from mpcc_state-&gt;dpp_id */</div><div class='add'>+</div><div class='add'>+		/* MPCC output gamma control */</div><div class='add'>+		uint32_t mpcc_ogam_mode[MAX_PIPES];      /* MPCC_OGAM_CONTROL-&gt;MPCC_OGAM_MODE from output gamma mode */</div><div class='add'>+		uint32_t mpcc_ogam_select[MAX_PIPES];    /* MPCC_OGAM_CONTROL-&gt;MPCC_OGAM_SELECT from gamma LUT bank selection */</div><div class='add'>+		uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL-&gt;MPCC_OGAM_PWL_DISABLE from PWL control */</div><div class='add'>+</div><div class='add'>+		/* MPCC pipe assignment and status */</div><div class='add'>+		uint32_t mpcc_opp_id[MAX_PIPES];         /* MPCC_OPP_ID-&gt;MPCC_OPP_ID from mpcc_state-&gt;opp_id */</div><div class='add'>+		uint32_t mpcc_idle[MAX_PIPES];           /* MPCC_STATUS-&gt;MPCC_IDLE from mpcc idle status */</div><div class='add'>+		uint32_t mpcc_busy[MAX_PIPES];           /* MPCC_STATUS-&gt;MPCC_BUSY from mpcc busy status */</div><div class='add'>+</div><div class='add'>+		/* MPC output processing */</div><div class='add'>+		uint32_t mpc_out_csc_mode;               /* MPC_OUT_CSC_COEF-&gt;MPC_OUT_CSC_MODE from output_csc */</div><div class='add'>+		uint32_t mpc_out_gamma_mode;             /* MPC_OUT_GAMMA_LUT-&gt;MPC_OUT_GAMMA_MODE from output_gamma */</div><div class='add'>+	} mpc;</div><div class='add'>+</div><div class='add'>+	/* OPP register programming variables for each pipe */</div><div class='add'>+	struct {</div><div class='add'>+		/* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */</div><div class='add'>+		uint32_t dpg_enable;                     /* DPG_CONTROL-&gt;DPG_EN from test_pattern parameter (enable/disable) */</div><div class='add'>+</div><div class='add'>+		/* Format Control (FMT) - 18 fields from FMT_CONTROL register */</div><div class='add'>+		uint32_t fmt_pixel_encoding;             /* FMT_CONTROL-&gt;FMT_PIXEL_ENCODING from clamping-&gt;pixel_encoding */</div><div class='add'>+		uint32_t fmt_subsampling_mode;           /* FMT_CONTROL-&gt;FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */</div><div class='add'>+		uint32_t fmt_cbcr_bit_reduction_bypass;  /* FMT_CONTROL-&gt;FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */</div><div class='add'>+		uint32_t fmt_stereosync_override;        /* FMT_CONTROL-&gt;FMT_STEREOSYNC_OVERRIDE from stereo timing override */</div><div class='add'>+		uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL-&gt;FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth-&gt;flags */</div><div class='add'>+		uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL-&gt;FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */</div><div class='add'>+		uint32_t fmt_truncate_enable;            /* FMT_CONTROL-&gt;FMT_TRUNCATE_EN from fmt_bit_depth-&gt;flags.TRUNCATE_ENABLED */</div><div class='add'>+		uint32_t fmt_truncate_depth;             /* FMT_CONTROL-&gt;FMT_TRUNCATE_DEPTH from fmt_bit_depth-&gt;flags.TRUNCATE_DEPTH */</div><div class='add'>+		uint32_t fmt_truncate_mode;              /* FMT_CONTROL-&gt;FMT_TRUNCATE_MODE from fmt_bit_depth-&gt;flags.TRUNCATE_MODE */</div><div class='add'>+		uint32_t fmt_spatial_dither_enable;      /* FMT_CONTROL-&gt;FMT_SPATIAL_DITHER_EN from fmt_bit_depth-&gt;flags.SPATIAL_DITHER_ENABLED */</div><div class='add'>+		uint32_t fmt_spatial_dither_mode;        /* FMT_CONTROL-&gt;FMT_SPATIAL_DITHER_MODE from fmt_bit_depth-&gt;flags.SPATIAL_DITHER_MODE */</div><div class='add'>+		uint32_t fmt_spatial_dither_depth;       /* FMT_CONTROL-&gt;FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth-&gt;flags.SPATIAL_DITHER_DEPTH */</div><div class='add'>+		uint32_t fmt_temporal_dither_enable;     /* FMT_CONTROL-&gt;FMT_TEMPORAL_DITHER_EN from fmt_bit_depth-&gt;flags.TEMPORAL_DITHER_ENABLED */</div><div class='add'>+		uint32_t fmt_clamp_data_enable;          /* FMT_CONTROL-&gt;FMT_CLAMP_DATA_EN from clamping-&gt;clamping_range enable */</div><div class='add'>+		uint32_t fmt_clamp_color_format;         /* FMT_CONTROL-&gt;FMT_CLAMP_COLOR_FORMAT from clamping-&gt;color_format */</div><div class='add'>+		uint32_t fmt_dynamic_exp_enable;         /* FMT_CONTROL-&gt;FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */</div><div class='add'>+		uint32_t fmt_dynamic_exp_mode;           /* FMT_CONTROL-&gt;FMT_DYNAMIC_EXP_MODE from color space mode mapping */</div><div class='add'>+		uint32_t fmt_bit_depth_control;          /* Legacy field - kept for compatibility */</div><div class='add'>+</div><div class='add'>+		/* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */</div><div class='add'>+		uint32_t opp_pipe_clock_enable;          /* OPP_PIPE_CONTROL-&gt;OPP_PIPE_CLOCK_EN from enable parameter (bool) */</div><div class='add'>+</div><div class='add'>+		/* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */</div><div class='add'>+		uint32_t opp_crc_enable;                 /* OPP_PIPE_CRC_CONTROL-&gt;CRC_EN from CRC enable control */</div><div class='add'>+		uint32_t opp_crc_select_source;          /* OPP_PIPE_CRC_CONTROL-&gt;CRC_SELECT_SOURCE from CRC source selection */</div><div class='add'>+		uint32_t opp_crc_stereo_cont;            /* OPP_PIPE_CRC_CONTROL-&gt;CRC_STEREO_CONT from stereo continuous CRC */</div><div class='add'>+</div><div class='add'>+		/* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */</div><div class='add'>+		uint32_t oppbuf_active_width;            /* OPPBUF_CONTROL-&gt;OPPBUF_ACTIVE_WIDTH from oppbuf_params-&gt;active_width */</div><div class='add'>+		uint32_t oppbuf_pixel_repetition;        /* OPPBUF_CONTROL-&gt;OPPBUF_PIXEL_REPETITION from oppbuf_params-&gt;pixel_repetition */</div><div class='add'>+		uint32_t oppbuf_display_segmentation;    /* OPPBUF_CONTROL-&gt;OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params-&gt;mso_segmentation */</div><div class='add'>+		uint32_t oppbuf_overlap_pixel_num;       /* OPPBUF_CONTROL-&gt;OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params-&gt;mso_overlap_pixel_num */</div><div class='add'>+		uint32_t oppbuf_3d_vact_space1_size;     /* OPPBUF_CONTROL-&gt;OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */</div><div class='add'>+		uint32_t oppbuf_3d_vact_space2_size;     /* OPPBUF_CONTROL-&gt;OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */</div><div class='add'>+</div><div class='add'>+		/* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */</div><div class='add'>+		uint32_t dscrm_dsc_forward_enable;       /* DSCRM_DSC_FORWARD_CONFIG-&gt;DSCRM_DSC_FORWARD_EN from DSC forward enable control */</div><div class='add'>+		uint32_t dscrm_dsc_opp_pipe_source;      /* DSCRM_DSC_FORWARD_CONFIG-&gt;DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */</div><div class='add'>+		uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG-&gt;DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */</div><div class='add'>+	} opp[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	/* OPTC register programming variables for each pipe */</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t otg_master_inst;</div><div class='add'>+</div><div class='add'>+		/* OTG_CONTROL register - 5 fields for OTG control */</div><div class='add'>+		uint32_t otg_master_enable;              /* OTG_CONTROL-&gt;OTG_MASTER_EN from timing enable/disable control */</div><div class='add'>+		uint32_t otg_disable_point_cntl;         /* OTG_CONTROL-&gt;OTG_DISABLE_POINT_CNTL from disable timing control */</div><div class='add'>+		uint32_t otg_start_point_cntl;           /* OTG_CONTROL-&gt;OTG_START_POINT_CNTL from start timing control */</div><div class='add'>+		uint32_t otg_field_number_cntl;          /* OTG_CONTROL-&gt;OTG_FIELD_NUMBER_CNTL from interlace field control */</div><div class='add'>+		uint32_t otg_out_mux;                    /* OTG_CONTROL-&gt;OTG_OUT_MUX from output mux selection */</div><div class='add'>+</div><div class='add'>+		/* OTG Horizontal Timing - 7 fields */</div><div class='add'>+		uint32_t otg_h_total;                    /* OTG_H_TOTAL-&gt;OTG_H_TOTAL from dc_crtc_timing-&gt;h_total */</div><div class='add'>+		uint32_t otg_h_blank_start;              /* OTG_H_BLANK_START_END-&gt;OTG_H_BLANK_START from dc_crtc_timing-&gt;h_front_porch */</div><div class='add'>+		uint32_t otg_h_blank_end;                /* OTG_H_BLANK_START_END-&gt;OTG_H_BLANK_END from dc_crtc_timing-&gt;h_addressable_video_pixel_width */</div><div class='add'>+		uint32_t otg_h_sync_start;               /* OTG_H_SYNC_A-&gt;OTG_H_SYNC_A_START from dc_crtc_timing-&gt;h_sync_width */</div><div class='add'>+		uint32_t otg_h_sync_end;                 /* OTG_H_SYNC_A-&gt;OTG_H_SYNC_A_END from calculated sync end position */</div><div class='add'>+		uint32_t otg_h_sync_polarity;            /* OTG_H_SYNC_A_CNTL-&gt;OTG_H_SYNC_A_POL from dc_crtc_timing-&gt;flags.HSYNC_POSITIVE_POLARITY */</div><div class='add'>+		uint32_t otg_h_timing_div_mode;          /* OTG_H_TIMING_CNTL-&gt;OTG_H_TIMING_DIV_MODE from horizontal timing division mode */</div><div class='add'>+</div><div class='add'>+		/* OTG Vertical Timing - 7 fields */</div><div class='add'>+		uint32_t otg_v_total;                    /* OTG_V_TOTAL-&gt;OTG_V_TOTAL from dc_crtc_timing-&gt;v_total */</div><div class='add'>+		uint32_t otg_v_blank_start;              /* OTG_V_BLANK_START_END-&gt;OTG_V_BLANK_START from dc_crtc_timing-&gt;v_front_porch */</div><div class='add'>+		uint32_t otg_v_blank_end;                /* OTG_V_BLANK_START_END-&gt;OTG_V_BLANK_END from dc_crtc_timing-&gt;v_addressable_video_line_width */</div><div class='add'>+		uint32_t otg_v_sync_start;               /* OTG_V_SYNC_A-&gt;OTG_V_SYNC_A_START from dc_crtc_timing-&gt;v_sync_width */</div><div class='add'>+		uint32_t otg_v_sync_end;                 /* OTG_V_SYNC_A-&gt;OTG_V_SYNC_A_END from calculated sync end position */</div><div class='add'>+		uint32_t otg_v_sync_polarity;            /* OTG_V_SYNC_A_CNTL-&gt;OTG_V_SYNC_A_POL from dc_crtc_timing-&gt;flags.VSYNC_POSITIVE_POLARITY */</div><div class='add'>+		uint32_t otg_v_sync_mode;                /* OTG_V_SYNC_A_CNTL-&gt;OTG_V_SYNC_MODE from sync mode selection */</div><div class='add'>+</div><div class='add'>+		/* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */</div><div class='add'>+		uint32_t otg_v_total_max;                /* OTG_V_TOTAL_MAX-&gt;OTG_V_TOTAL_MAX from drr_params-&gt;vertical_total_max */</div><div class='add'>+		uint32_t otg_v_total_min;                /* OTG_V_TOTAL_MIN-&gt;OTG_V_TOTAL_MIN from drr_params-&gt;vertical_total_min */</div><div class='add'>+		uint32_t otg_v_total_mid;                /* OTG_V_TOTAL_MID-&gt;OTG_V_TOTAL_MID from drr_params-&gt;vertical_total_mid */</div><div class='add'>+		uint32_t otg_v_total_max_sel;            /* OTG_V_TOTAL_CONTROL-&gt;OTG_V_TOTAL_MAX_SEL from DRR max selection enable */</div><div class='add'>+		uint32_t otg_v_total_min_sel;            /* OTG_V_TOTAL_CONTROL-&gt;OTG_V_TOTAL_MIN_SEL from DRR min selection enable */</div><div class='add'>+		uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL-&gt;OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */</div><div class='add'>+		uint32_t otg_vtotal_mid_frame_num;       /* OTG_V_TOTAL_CONTROL-&gt;OTG_VTOTAL_MID_FRAME_NUM from drr_params-&gt;vertical_total_mid_frame_num */</div><div class='add'>+		uint32_t otg_set_v_total_min_mask;       /* OTG_V_TOTAL_CONTROL-&gt;OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */</div><div class='add'>+		uint32_t otg_force_lock_on_event;        /* OTG_V_TOTAL_CONTROL-&gt;OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */</div><div class='add'>+</div><div class='add'>+		/* OPTC Data Source and ODM - 6 fields */</div><div class='add'>+		uint32_t optc_seg0_src_sel;              /* OPTC_DATA_SOURCE_SELECT-&gt;OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */</div><div class='add'>+		uint32_t optc_seg1_src_sel;              /* OPTC_DATA_SOURCE_SELECT-&gt;OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */</div><div class='add'>+		uint32_t optc_seg2_src_sel;              /* OPTC_DATA_SOURCE_SELECT-&gt;OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */</div><div class='add'>+		uint32_t optc_seg3_src_sel;              /* OPTC_DATA_SOURCE_SELECT-&gt;OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */</div><div class='add'>+		uint32_t optc_num_of_input_segment;      /* OPTC_DATA_SOURCE_SELECT-&gt;OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */</div><div class='add'>+		uint32_t optc_mem_sel;                   /* OPTC_MEMORY_CONFIG-&gt;OPTC_MEM_SEL from memory_mask ODM memory selection */</div><div class='add'>+</div><div class='add'>+		/* OPTC Data Format and DSC - 4 fields */</div><div class='add'>+		uint32_t optc_data_format;               /* OPTC_DATA_FORMAT_CONTROL-&gt;OPTC_DATA_FORMAT from data format selection */</div><div class='add'>+		uint32_t optc_dsc_mode;                  /* OPTC_DATA_FORMAT_CONTROL-&gt;OPTC_DSC_MODE from dsc_mode parameter */</div><div class='add'>+		uint32_t optc_dsc_bytes_per_pixel;       /* OPTC_BYTES_PER_PIXEL-&gt;OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */</div><div class='add'>+		uint32_t optc_segment_width;             /* OPTC_WIDTH_CONTROL-&gt;OPTC_SEGMENT_WIDTH from segment_width parameter */</div><div class='add'>+		uint32_t optc_dsc_slice_width;           /* OPTC_WIDTH_CONTROL-&gt;OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */</div><div class='add'>+</div><div class='add'>+		/* OPTC Clock and Underflow Control - 4 fields */</div><div class='add'>+		uint32_t optc_input_pix_clk_en;          /* OPTC_INPUT_CLOCK_CONTROL-&gt;OPTC_INPUT_PIX_CLK_EN from pixel clock enable */</div><div class='add'>+		uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL-&gt;OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */</div><div class='add'>+		uint32_t optc_underflow_clear;           /* OPTC_INPUT_GLOBAL_CONTROL-&gt;OPTC_UNDERFLOW_CLEAR from underflow clear control */</div><div class='add'>+		uint32_t otg_clock_enable;               /* OTG_CLOCK_CONTROL-&gt;OTG_CLOCK_EN from OTG clock enable */</div><div class='add'>+		uint32_t otg_clock_gate_dis;             /* OTG_CLOCK_CONTROL-&gt;OTG_CLOCK_GATE_DIS from clock gate disable */</div><div class='add'>+</div><div class='add'>+		/* OTG Stereo and 3D Control - 6 fields */</div><div class='add'>+		uint32_t otg_stereo_enable;              /* OTG_STEREO_CONTROL-&gt;OTG_STEREO_EN from stereo enable control */</div><div class='add'>+		uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL-&gt;OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing-&gt;stereo_3d_format line num */</div><div class='add'>+		uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL-&gt;OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */</div><div class='add'>+		uint32_t otg_3d_structure_en;            /* OTG_3D_STRUCTURE_CONTROL-&gt;OTG_3D_STRUCTURE_EN from 3D structure enable */</div><div class='add'>+		uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL-&gt;OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */</div><div class='add'>+		uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL-&gt;OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */</div><div class='add'>+		uint32_t otg_interlace_enable;           /* OTG_INTERLACE_CONTROL-&gt;OTG_INTERLACE_ENABLE from dc_crtc_timing-&gt;flags.INTERLACE */</div><div class='add'>+</div><div class='add'>+		/* OTG GSL (Global Sync Lock) Control - 5 fields */</div><div class='add'>+		uint32_t otg_gsl0_en;                    /* OTG_GSL_CONTROL-&gt;OTG_GSL0_EN from GSL group 0 enable */</div><div class='add'>+		uint32_t otg_gsl1_en;                    /* OTG_GSL_CONTROL-&gt;OTG_GSL1_EN from GSL group 1 enable */</div><div class='add'>+		uint32_t otg_gsl2_en;                    /* OTG_GSL_CONTROL-&gt;OTG_GSL2_EN from GSL group 2 enable */</div><div class='add'>+		uint32_t otg_gsl_master_en;              /* OTG_GSL_CONTROL-&gt;OTG_GSL_MASTER_EN from GSL master enable */</div><div class='add'>+		uint32_t otg_gsl_master_mode;            /* OTG_GSL_CONTROL-&gt;OTG_GSL_MASTER_MODE from gsl_params-&gt;gsl_master mode */</div><div class='add'>+</div><div class='add'>+		/* OTG DRR Advanced Control - 4 fields */</div><div class='add'>+		uint32_t otg_v_total_last_used_by_drr;   /* OTG_DRR_CONTROL-&gt;OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */</div><div class='add'>+		uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW-&gt;OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */</div><div class='add'>+		uint32_t otg_drr_trigger_window_end_x;   /* OTG_DRR_TRIGGER_WINDOW-&gt;OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */</div><div class='add'>+		uint32_t otg_drr_v_total_change_limit;   /* OTG_DRR_V_TOTAL_CHANGE-&gt;OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */</div><div class='add'>+</div><div class='add'>+		/* OTG DSC Position Control - 2 fields */</div><div class='add'>+		uint32_t otg_dsc_start_position_x;       /* OTG_DSC_START_POSITION-&gt;OTG_DSC_START_POSITION_X from DSC start X position */</div><div class='add'>+		uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION-&gt;OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */</div><div class='add'>+</div><div class='add'>+		/* OTG Double Buffer Control - 2 fields */</div><div class='add'>+		uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL-&gt;OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */</div><div class='add'>+		uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL-&gt;OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */</div><div class='add'>+</div><div class='add'>+		/* OTG Vertical Interrupts - 6 fields */</div><div class='add'>+		uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL-&gt;OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */</div><div class='add'>+		uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION-&gt;OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */</div><div class='add'>+		uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL-&gt;OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */</div><div class='add'>+		uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION-&gt;OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */</div><div class='add'>+		uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL-&gt;OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */</div><div class='add'>+		uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION-&gt;OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */</div><div class='add'>+</div><div class='add'>+		/* OTG Global Sync Parameters - 6 fields */</div><div class='add'>+		uint32_t otg_vready_offset;              /* OTG_VREADY_PARAM-&gt;OTG_VREADY_OFFSET from vready_offset parameter */</div><div class='add'>+		uint32_t otg_vstartup_start;             /* OTG_VSTARTUP_PARAM-&gt;OTG_VSTARTUP_START from vstartup_start parameter */</div><div class='add'>+		uint32_t otg_vupdate_offset;             /* OTG_VUPDATE_PARAM-&gt;OTG_VUPDATE_OFFSET from vupdate_offset parameter */</div><div class='add'>+		uint32_t otg_vupdate_width;              /* OTG_VUPDATE_PARAM-&gt;OTG_VUPDATE_WIDTH from vupdate_width parameter */</div><div class='add'>+		uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT-&gt;MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */</div><div class='add'>+		uint32_t master_update_lock_vupdate_keepout_end_offset;   /* OTG_VUPDATE_KEEPOUT-&gt;MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */</div><div class='add'>+</div><div class='add'>+		/* OTG Manual Trigger Control - 11 fields */</div><div class='add'>+		uint32_t otg_triga_source_select;        /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_SOURCE_SELECT from trigger A source selection */</div><div class='add'>+		uint32_t otg_triga_source_pipe_select;   /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */</div><div class='add'>+		uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */</div><div class='add'>+		uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */</div><div class='add'>+		uint32_t otg_triga_polarity_select;      /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */</div><div class='add'>+		uint32_t otg_triga_frequency_select;     /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */</div><div class='add'>+		uint32_t otg_triga_delay;                /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_DELAY from trigger A delay */</div><div class='add'>+		uint32_t otg_triga_clear;                /* OTG_TRIGA_CNTL-&gt;OTG_TRIGA_CLEAR from trigger A clear */</div><div class='add'>+		uint32_t otg_triga_manual_trig;          /* OTG_TRIGA_MANUAL_TRIG-&gt;OTG_TRIGA_MANUAL_TRIG from manual trigger A */</div><div class='add'>+		uint32_t otg_trigb_source_select;        /* OTG_TRIGB_CNTL-&gt;OTG_TRIGB_SOURCE_SELECT from trigger B source selection */</div><div class='add'>+		uint32_t otg_trigb_polarity_select;      /* OTG_TRIGB_CNTL-&gt;OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */</div><div class='add'>+		uint32_t otg_trigb_manual_trig;          /* OTG_TRIGB_MANUAL_TRIG-&gt;OTG_TRIGB_MANUAL_TRIG from manual trigger B */</div><div class='add'>+</div><div class='add'>+		/* OTG Static Screen and Update Control - 6 fields */</div><div class='add'>+		uint32_t otg_static_screen_event_mask;   /* OTG_STATIC_SCREEN_CONTROL-&gt;OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */</div><div class='add'>+		uint32_t otg_static_screen_frame_count;  /* OTG_STATIC_SCREEN_CONTROL-&gt;OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */</div><div class='add'>+		uint32_t master_update_lock;             /* OTG_MASTER_UPDATE_LOCK-&gt;MASTER_UPDATE_LOCK from update lock control */</div><div class='add'>+		uint32_t master_update_mode;             /* OTG_MASTER_UPDATE_MODE-&gt;MASTER_UPDATE_MODE from update mode selection */</div><div class='add'>+		uint32_t otg_force_count_now_mode;       /* OTG_FORCE_COUNT_NOW_CNTL-&gt;OTG_FORCE_COUNT_NOW_MODE from force count mode */</div><div class='add'>+		uint32_t otg_force_count_now_clear;      /* OTG_FORCE_COUNT_NOW_CNTL-&gt;OTG_FORCE_COUNT_NOW_CLEAR from force count clear */</div><div class='add'>+</div><div class='add'>+		/* VTG Control - 3 fields */</div><div class='add'>+		uint32_t vtg0_enable;                    /* CONTROL-&gt;VTG0_ENABLE from VTG enable control */</div><div class='add'>+		uint32_t vtg0_fp2;                       /* CONTROL-&gt;VTG0_FP2 from VTG front porch 2 */</div><div class='add'>+		uint32_t vtg0_vcount_init;               /* CONTROL-&gt;VTG0_VCOUNT_INIT from VTG vertical count init */</div><div class='add'>+</div><div class='add'>+		/* OTG Status (Read-Only) - 12 fields */</div><div class='add'>+		uint32_t otg_v_blank;                    /* OTG_STATUS-&gt;OTG_V_BLANK from vertical blank status (read-only) */</div><div class='add'>+		uint32_t otg_v_active_disp;              /* OTG_STATUS-&gt;OTG_V_ACTIVE_DISP from vertical active display (read-only) */</div><div class='add'>+		uint32_t otg_frame_count;                /* OTG_STATUS_FRAME_COUNT-&gt;OTG_FRAME_COUNT from frame count (read-only) */</div><div class='add'>+		uint32_t otg_horz_count;                 /* OTG_STATUS_POSITION-&gt;OTG_HORZ_COUNT from horizontal position (read-only) */</div><div class='add'>+		uint32_t otg_vert_count;                 /* OTG_STATUS_POSITION-&gt;OTG_VERT_COUNT from vertical position (read-only) */</div><div class='add'>+		uint32_t otg_horz_count_hv;              /* OTG_STATUS_HV_COUNT-&gt;OTG_HORZ_COUNT from horizontal count (read-only) */</div><div class='add'>+		uint32_t otg_vert_count_nom;             /* OTG_STATUS_HV_COUNT-&gt;OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */</div><div class='add'>+		uint32_t otg_flip_pending;               /* OTG_PIPE_UPDATE_STATUS-&gt;OTG_FLIP_PENDING from flip pending status (read-only) */</div><div class='add'>+		uint32_t otg_dc_reg_update_pending;      /* OTG_PIPE_UPDATE_STATUS-&gt;OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */</div><div class='add'>+		uint32_t otg_cursor_update_pending;      /* OTG_PIPE_UPDATE_STATUS-&gt;OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */</div><div class='add'>+		uint32_t otg_vupdate_keepout_status;     /* OTG_PIPE_UPDATE_STATUS-&gt;OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */</div><div class='add'>+	} optc[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	/* Metadata */</div><div class='add'>+	uint32_t active_pipe_count;</div><div class='add'>+	uint32_t active_stream_count;</div><div class='add'>+	bool state_valid;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_capture_register_software_state() - Capture software state for register programming</div><div class='add'>+ * @dc: DC context containing current display configuration</div><div class='add'>+ * @state: Pointer to dc_register_software_state structure to populate</div><div class='add'>+ *</div><div class='add'>+ * Extracts all software state variables that are used to program hardware register</div><div class='add'>+ * fields across the display driver pipeline. This provides a complete snapshot</div><div class='add'>+ * of the software configuration that drives hardware register programming.</div><div class='add'>+ *</div><div class='add'>+ * The function traverses the DC context and extracts values from:</div><div class='add'>+ * - Stream configurations (timing, format, DSC settings)</div><div class='add'>+ * - Plane states (surface format, rotation, scaling, cursor)</div><div class='add'>+ * - Pipe contexts (resource allocation, blending, viewport)</div><div class='add'>+ * - Clock manager (display clocks, DPP clocks, pixel clocks)</div><div class='add'>+ * - Resource context (DET buffer allocation, ODM configuration)</div><div class='add'>+ *</div><div class='add'>+ * This is essential for underflow debugging as it captures the exact software</div><div class='add'>+ * state that determines how registers are programmed, allowing analysis of</div><div class='add'>+ * whether underflow is caused by incorrect register programming or timing issues.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if state was successfully captured, false on error</div><div class='add'>+ */</div><div class='add'>+bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state);</div><div class='add'>+</div><div class='ctx'> #endif /* DC_INTERFACE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h<br/>index 26940d94d8fb..40d7a7d83c40 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_bios_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_bios_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_bios_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_bios_types.h</a></div><div class='hunk'>@@ -91,9 +91,17 @@ struct dc_vbios_funcs {</div><div class='ctx'> 		struct device_id id);</div><div class='ctx'> 	/* COMMANDS */</div><div class='ctx'> </div><div class='add'>+	enum bp_result (*select_crtc_source)(</div><div class='add'>+		struct dc_bios *bios,</div><div class='add'>+		struct bp_crtc_source_select *bp_params);</div><div class='ctx'> 	enum bp_result (*encoder_control)(</div><div class='ctx'> 		struct dc_bios *bios,</div><div class='ctx'> 		struct bp_encoder_control *cntl);</div><div class='add'>+	enum bp_result (*dac_load_detection)(</div><div class='add'>+		struct dc_bios *bios,</div><div class='add'>+		enum engine_id engine_id,</div><div class='add'>+		enum dal_device_type device_type,</div><div class='add'>+		uint32_t enum_id);</div><div class='ctx'> 	enum bp_result (*transmitter_control)(</div><div class='ctx'> 		struct dc_bios *bios,</div><div class='ctx'> 		struct bp_transmitter_control *cntl);</div><div class='hunk'>@@ -165,6 +173,7 @@ struct dc_vbios_funcs {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct bios_registers {</div><div class='add'>+	uint32_t BIOS_SCRATCH_0;</div><div class='ctx'> 	uint32_t BIOS_SCRATCH_3;</div><div class='ctx'> 	uint32_t BIOS_SCRATCH_6;</div><div class='ctx'> };</div><div class='hunk'>@@ -183,6 +192,7 @@ struct dc_bios {</div><div class='ctx'> 	struct dc_firmware_info fw_info;</div><div class='ctx'> 	bool fw_info_valid;</div><div class='ctx'> 	struct dc_vram_info vram_info;</div><div class='add'>+	struct bp_soc_bb_info bb_info;</div><div class='ctx'> 	struct dc_golden_table golden_table;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c<br/>index 6083b1dcf050..7b09af1cb306 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "../dmub/dmub_srv.h"</div><div class='hunk'>@@ -34,9 +35,11 @@</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='add'>+#include "dc_plane_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define CTX dc_dmub_srv-&gt;ctx</div><div class='ctx'> #define DC_LOGGER CTX-&gt;logger</div><div class='add'>+#define GPINT_RETRY_NUM 20</div><div class='ctx'> </div><div class='ctx'> static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,</div><div class='ctx'> 				  struct dmub_srv *dmub)</div><div class='hunk'>@@ -68,20 +71,28 @@ void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)</div><div class='add'>+bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *dmub = dc_dmub_srv-&gt;dmub;</div><div class='del'>-	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	struct dmub_srv *dmub;</div><div class='add'>+	struct dc_context *dc_ctx;</div><div class='ctx'> 	enum dmub_status status;</div><div class='ctx'> </div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	dmub = dc_dmub_srv-&gt;dmub;</div><div class='add'>+</div><div class='ctx'> 	do {</div><div class='del'>-		status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='add'>+		status = dmub_srv_wait_for_pending(dmub, 100000);</div><div class='ctx'> 	} while (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout &amp;&amp; status != DMUB_STATUS_OK);</div><div class='ctx'> </div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='ctx'> 		DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);</div><div class='ctx'> 		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return status == DMUB_STATUS_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv)</div><div class='hunk'>@@ -124,13 +135,13 @@ void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> 		unsigned int count,</div><div class='ctx'> 		union dmub_rb_cmd *cmd_list)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *dc_ctx;</div><div class='ctx'> 	struct dmub_srv *dmub;</div><div class='del'>-	enum dmub_status status;</div><div class='add'>+	enum dmub_status status = DMUB_STATUS_OK;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='hunk'>@@ -140,33 +151,21 @@ bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> 	dmub = dc_dmub_srv-&gt;dmub;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0 ; i &lt; count; i++) {</div><div class='del'>-		// Queue command</div><div class='del'>-		status = dmub_srv_cmd_queue(dmub, &amp;cmd_list[i]);</div><div class='del'>-</div><div class='del'>-		if (status == DMUB_STATUS_QUEUE_FULL) {</div><div class='del'>-			/* Execute and wait for queue to become empty again. */</div><div class='del'>-			status = dmub_srv_cmd_execute(dmub);</div><div class='del'>-			if (status == DMUB_STATUS_POWER_STATE_D3)</div><div class='del'>-				return false;</div><div class='del'>-</div><div class='del'>-			do {</div><div class='del'>-				status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='del'>-			} while (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout &amp;&amp; status != DMUB_STATUS_OK);</div><div class='add'>+		/* confirm no messages pending */</div><div class='add'>+		do {</div><div class='add'>+			status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='add'>+		} while (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout &amp;&amp; status != DMUB_STATUS_OK);</div><div class='ctx'> </div><div class='del'>-			/* Requeue the command. */</div><div class='del'>-			status = dmub_srv_cmd_queue(dmub, &amp;cmd_list[i]);</div><div class='del'>-		}</div><div class='add'>+		/* queue command */</div><div class='add'>+		if (status == DMUB_STATUS_OK)</div><div class='add'>+			status = dmub_srv_reg_cmd_execute(dmub, &amp;cmd_list[i]);</div><div class='ctx'> </div><div class='add'>+		/* check for errors */</div><div class='ctx'> 		if (status != DMUB_STATUS_OK) {</div><div class='del'>-			if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='del'>-				DC_ERROR("Error queueing DMUB command: status=%d\n", status);</div><div class='del'>-				dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='del'>-			}</div><div class='del'>-			return false;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = dmub_srv_cmd_execute(dmub);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='ctx'> 		if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='ctx'> 			DC_ERROR("Error starting DMUB execution: status=%d\n", status);</div><div class='hunk'>@@ -178,45 +177,10 @@ bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,</div><div class='del'>-		enum dm_dmub_wait_type wait_type,</div><div class='add'>+static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+		unsigned int count,</div><div class='ctx'> 		union dmub_rb_cmd *cmd_list)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *dmub;</div><div class='del'>-	enum dmub_status status;</div><div class='del'>-</div><div class='del'>-	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	dmub = dc_dmub_srv-&gt;dmub;</div><div class='del'>-</div><div class='del'>-	// Wait for DMUB to process command</div><div class='del'>-	if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {</div><div class='del'>-		do {</div><div class='del'>-			status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='del'>-		} while (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout &amp;&amp; status != DMUB_STATUS_OK);</div><div class='del'>-</div><div class='del'>-		if (status != DMUB_STATUS_OK) {</div><div class='del'>-			DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);</div><div class='del'>-			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='del'>-			return false;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		// Copy data back from ring buffer into command</div><div class='del'>-		if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)</div><div class='del'>-			dmub_rb_get_return_data(&amp;dmub-&gt;inbox1_rb, cmd_list);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)</div><div class='del'>-{</div><div class='del'>-	return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)</div><div class='del'>-{</div><div class='ctx'> 	struct dc_context *dc_ctx;</div><div class='ctx'> 	struct dmub_srv *dmub;</div><div class='ctx'> 	enum dmub_status status;</div><div class='hunk'>@@ -230,18 +194,25 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int coun</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0 ; i &lt; count; i++) {</div><div class='ctx'> 		// Queue command</div><div class='del'>-		status = dmub_srv_cmd_queue(dmub, &amp;cmd_list[i]);</div><div class='add'>+		if (!cmd_list[i].cmd_common.header.multi_cmd_pending ||</div><div class='add'>+				dmub_rb_num_free(&amp;dmub-&gt;inbox1.rb) &gt;= count - i) {</div><div class='add'>+			status = dmub_srv_fb_cmd_queue(dmub, &amp;cmd_list[i]);</div><div class='add'>+		} else {</div><div class='add'>+			status = DMUB_STATUS_QUEUE_FULL;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (status == DMUB_STATUS_QUEUE_FULL) {</div><div class='ctx'> 			/* Execute and wait for queue to become empty again. */</div><div class='del'>-			status = dmub_srv_cmd_execute(dmub);</div><div class='add'>+			status = dmub_srv_fb_cmd_execute(dmub);</div><div class='ctx'> 			if (status == DMUB_STATUS_POWER_STATE_D3)</div><div class='ctx'> 				return false;</div><div class='ctx'> </div><div class='del'>-			dmub_srv_wait_for_idle(dmub, 100000);</div><div class='add'>+			do {</div><div class='add'>+					status = dmub_srv_wait_for_inbox_free(dmub, 100000, count - i);</div><div class='add'>+			} while (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout &amp;&amp; status != DMUB_STATUS_OK);</div><div class='ctx'> </div><div class='ctx'> 			/* Requeue the command. */</div><div class='del'>-			status = dmub_srv_cmd_queue(dmub, &amp;cmd_list[i]);</div><div class='add'>+			status = dmub_srv_fb_cmd_queue(dmub, &amp;cmd_list[i]);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (status != DMUB_STATUS_OK) {</div><div class='hunk'>@@ -253,7 +224,7 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int coun</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = dmub_srv_cmd_execute(dmub);</div><div class='add'>+	status = dmub_srv_fb_cmd_execute(dmub);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='ctx'> 		if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='ctx'> 			DC_ERROR("Error starting DMUB execution: status=%d\n", status);</div><div class='hunk'>@@ -262,29 +233,81 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int coun</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+		unsigned int count,</div><div class='add'>+		union dmub_rb_cmd *cmd_list)</div><div class='add'>+{</div><div class='add'>+	bool res = false;</div><div class='add'>+</div><div class='add'>+	if (dc_dmub_srv &amp;&amp; dc_dmub_srv-&gt;dmub) {</div><div class='add'>+		if (dc_dmub_srv-&gt;dmub-&gt;inbox_type == DMUB_CMD_INTERFACE_REG) {</div><div class='add'>+			res = dc_dmub_srv_reg_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list);</div><div class='add'>+		} else {</div><div class='add'>+			res = dc_dmub_srv_fb_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (res)</div><div class='add'>+			res = dmub_srv_update_inbox_status(dc_dmub_srv-&gt;dmub) == DMUB_STATUS_OK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+		enum dm_dmub_wait_type wait_type,</div><div class='add'>+		union dmub_rb_cmd *cmd_list)</div><div class='add'>+{</div><div class='add'>+	struct dmub_srv *dmub;</div><div class='add'>+	enum dmub_status status;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dmub = dc_dmub_srv-&gt;dmub;</div><div class='add'>+</div><div class='ctx'> 	// Wait for DMUB to process command</div><div class='ctx'> 	if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {</div><div class='del'>-		if (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout) {</div><div class='del'>-			do {</div><div class='del'>-				status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='del'>-			} while (status != DMUB_STATUS_OK);</div><div class='del'>-		} else</div><div class='add'>+		do {</div><div class='ctx'> 			status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='add'>+		} while (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout &amp;&amp; status != DMUB_STATUS_OK);</div><div class='ctx'> </div><div class='ctx'> 		if (status != DMUB_STATUS_OK) {</div><div class='ctx'> 			DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);</div><div class='add'>+			if (!dmub-&gt;debug.timeout_info.timeout_occured) {</div><div class='add'>+				dmub-&gt;debug.timeout_info.timeout_occured = true;</div><div class='add'>+				if (cmd_list)</div><div class='add'>+					dmub-&gt;debug.timeout_info.timeout_cmd = *cmd_list;</div><div class='add'>+				dmub-&gt;debug.timeout_info.timestamp = dm_get_timestamp(dc_dmub_srv-&gt;ctx);</div><div class='add'>+			}</div><div class='ctx'> 			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		// Copy data back from ring buffer into command</div><div class='del'>-		if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)</div><div class='del'>-			dmub_rb_get_return_data(&amp;dmub-&gt;inbox1_rb, cmd_list);</div><div class='add'>+		if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY &amp;&amp; cmd_list) {</div><div class='add'>+			dmub_srv_cmd_get_response(dc_dmub_srv-&gt;dmub, cmd_list);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	if (!dc_dmub_srv_cmd_list_queue_execute(dc_dmub_srv, count, cmd_list))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return dc_dmub_srv_wait_for_idle(dc_dmub_srv, wait_type, cmd_list);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmub_srv *dmub;</div><div class='hunk'>@@ -419,7 +442,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru</div><div class='ctx'> 	int i = 0, k = 0;</div><div class='ctx'> 	int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it.</div><div class='ctx'> 	uint8_t visual_confirm_enabled;</div><div class='del'>-	int pipe_idx = 0;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (dc == NULL)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -433,7 +456,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru</div><div class='ctx'> 	cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled;</div><div class='ctx'> </div><div class='ctx'> 	if (should_manage_pstate) {</div><div class='del'>-		for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 			if (!pipe-&gt;stream)</div><div class='hunk'>@@ -443,18 +466,22 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru</div><div class='ctx'> 			 * that does not use FAMS, we are in an FPO + VActive scenario.</div><div class='ctx'> 			 * Assign vactive stretch margin in this case.</div><div class='ctx'> 			 */</div><div class='del'>-			if (!pipe-&gt;stream-&gt;fpo_in_use) {</div><div class='add'>+			stream_status = dc_state_get_stream_status(context, pipe-&gt;stream);</div><div class='add'>+			if (stream_status &amp;&amp; !stream_status-&gt;fpo_in_use) {</div><div class='ctx'> 				cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc-&gt;debug.fpo_vactive_margin_us;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='del'>-			pipe_idx++;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, k = 0; context &amp;&amp; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp; pipe-&gt;stream-&gt;fpo_in_use) {</div><div class='add'>+		if (!resource_is_pipe_type(pipe, OTG_MASTER))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		stream_status = dc_state_get_stream_status(context, pipe-&gt;stream);</div><div class='add'>+		if (stream_status &amp;&amp; stream_status-&gt;fpo_in_use) {</div><div class='ctx'> 			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 			uint8_t min_refresh_in_hz = (pipe-&gt;stream-&gt;timing.min_refresh_in_uhz + 999999) / 1000000;</div><div class='ctx'> </div><div class='hunk'>@@ -504,7 +531,9 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi</div><div class='ctx'> 	union dmub_rb_cmd cmd = { 0 };</div><div class='ctx'> 	unsigned int panel_inst = 0;</div><div class='ctx'> </div><div class='del'>-	dc_get_edp_link_panel_inst(dc, pipe_ctx-&gt;stream-&gt;link, &amp;panel_inst);</div><div class='add'>+	if (!dc_get_edp_link_panel_inst(dc, pipe_ctx-&gt;stream-&gt;link, &amp;panel_inst) &amp;&amp;</div><div class='add'>+			dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_DISABLE)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> </div><div class='hunk'>@@ -549,7 +578,7 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='del'>-	struct dc_crtc_timing *phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='add'>+	struct dc_crtc_timing *phantom_timing;</div><div class='ctx'> 	struct dc_crtc_timing *drr_timing = &amp;vblank_pipe-&gt;stream-&gt;timing;</div><div class='ctx'> 	uint16_t drr_frame_us = 0;</div><div class='ctx'> 	uint16_t min_drr_supported_us = 0;</div><div class='hunk'>@@ -563,6 +592,11 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,</div><div class='ctx'> 	uint16_t min_vtotal_supported = 0;</div><div class='ctx'> 	uint16_t max_vtotal_supported = 0;</div><div class='ctx'> </div><div class='add'>+	if (!phantom_stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='add'>+</div><div class='ctx'> 	pipe_data-&gt;pipe_config.vblank_data.drr_info.drr_in_use = true;</div><div class='ctx'> 	pipe_data-&gt;pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping</div><div class='ctx'> 	pipe_data-&gt;pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now</div><div class='hunk'>@@ -686,7 +720,13 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,</div><div class='ctx'> 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;</div><div class='ctx'> </div><div class='ctx'> 	phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]-&gt;stream);</div><div class='add'>+	if (!phantom_stream0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]-&gt;stream);</div><div class='add'>+	if (!phantom_stream1)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	phantom_timing0 = &amp;phantom_stream0-&gt;timing;</div><div class='ctx'> 	phantom_timing1 = &amp;phantom_stream1-&gt;timing;</div><div class='ctx'> </div><div class='hunk'>@@ -741,9 +781,14 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,</div><div class='ctx'> 			&amp;cmd-&gt;fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];</div><div class='ctx'> 	struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='del'>-	struct dc_crtc_timing *phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='add'>+	struct dc_crtc_timing *phantom_timing;</div><div class='ctx'> 	uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;</div><div class='ctx'> </div><div class='add'>+	if (!phantom_stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='add'>+</div><div class='ctx'> 	pipe_data-&gt;mode = SUBVP;</div><div class='ctx'> 	pipe_data-&gt;pipe_config.subvp_data.pix_clk_100hz = subvp_pipe-&gt;stream-&gt;timing.pix_clk_100hz;</div><div class='ctx'> 	pipe_data-&gt;pipe_config.subvp_data.htotal = subvp_pipe-&gt;stream-&gt;timing.h_total;</div><div class='hunk'>@@ -825,7 +870,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 		bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t cmd_pipe_index = 0;</div><div class='del'>-	uint32_t i, pipe_idx;</div><div class='add'>+	uint32_t i;</div><div class='ctx'> 	uint8_t subvp_count = 0;</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct pipe_ctx *subvp_pipes[2];</div><div class='hunk'>@@ -852,7 +897,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		// For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd</div><div class='del'>-		for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 			pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='hunk'>@@ -875,7 +920,6 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 				populate_subvp_cmd_vblank_pipe_info(dc, context, &amp;cmd, pipe, cmd_pipe_index++);</div><div class='ctx'> </div><div class='ctx'> 			}</div><div class='del'>-			pipe_idx++;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (subvp_count == 2) {</div><div class='ctx'> 			update_subvp_prefetch_end_to_mall_start(dc, context, &amp;cmd, subvp_pipes);</div><div class='hunk'>@@ -894,115 +938,74 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)</div><div class='add'>+bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)</div><div class='ctx'> {</div><div class='del'>-	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub || !diag_data)</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='ctx'> 		return false;</div><div class='del'>-	return dmub_srv_get_diagnostic_data(dc_dmub_srv-&gt;dmub, diag_data);</div><div class='add'>+	return dmub_srv_get_diagnostic_data(dc_dmub_srv-&gt;dmub);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_diagnostic_data diag_data = {0};</div><div class='add'>+	uint32_t i;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub) {</div><div class='ctx'> 		DC_LOG_ERROR("%s: invalid parameters.", __func__);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &amp;diag_data)) {</div><div class='add'>+	DC_LOG_ERROR("%s: DMCUB error - collecting diagnostic data\n", __func__);</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv)) {</div><div class='ctx'> 		DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_DEBUG("DMCUB STATE:");</div><div class='del'>-	DC_LOG_DEBUG("    dmcub_version      : %08x", diag_data.dmcub_version);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [0]       : %08x", diag_data.scratch[0]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [1]       : %08x", diag_data.scratch[1]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [2]       : %08x", diag_data.scratch[2]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [3]       : %08x", diag_data.scratch[3]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [4]       : %08x", diag_data.scratch[4]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [5]       : %08x", diag_data.scratch[5]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [6]       : %08x", diag_data.scratch[6]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [7]       : %08x", diag_data.scratch[7]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [8]       : %08x", diag_data.scratch[8]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch  [9]       : %08x", diag_data.scratch[9]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch [10]       : %08x", diag_data.scratch[10]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch [11]       : %08x", diag_data.scratch[11]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch [12]       : %08x", diag_data.scratch[12]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch [13]       : %08x", diag_data.scratch[13]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch [14]       : %08x", diag_data.scratch[14]);</div><div class='del'>-	DC_LOG_DEBUG("    scratch [15]       : %08x", diag_data.scratch[15]);</div><div class='del'>-	DC_LOG_DEBUG("    pc                 : %08x", diag_data.pc);</div><div class='del'>-	DC_LOG_DEBUG("    unk_fault_addr     : %08x", diag_data.undefined_address_fault_addr);</div><div class='del'>-	DC_LOG_DEBUG("    inst_fault_addr    : %08x", diag_data.inst_fetch_fault_addr);</div><div class='del'>-	DC_LOG_DEBUG("    data_fault_addr    : %08x", diag_data.data_write_fault_addr);</div><div class='del'>-	DC_LOG_DEBUG("    inbox1_rptr        : %08x", diag_data.inbox1_rptr);</div><div class='del'>-	DC_LOG_DEBUG("    inbox1_wptr        : %08x", diag_data.inbox1_wptr);</div><div class='del'>-	DC_LOG_DEBUG("    inbox1_size        : %08x", diag_data.inbox1_size);</div><div class='del'>-	DC_LOG_DEBUG("    inbox0_rptr        : %08x", diag_data.inbox0_rptr);</div><div class='del'>-	DC_LOG_DEBUG("    inbox0_wptr        : %08x", diag_data.inbox0_wptr);</div><div class='del'>-	DC_LOG_DEBUG("    inbox0_size        : %08x", diag_data.inbox0_size);</div><div class='del'>-	DC_LOG_DEBUG("    is_enabled         : %d", diag_data.is_dmcub_enabled);</div><div class='del'>-	DC_LOG_DEBUG("    is_soft_reset      : %d", diag_data.is_dmcub_soft_reset);</div><div class='del'>-	DC_LOG_DEBUG("    is_secure_reset    : %d", diag_data.is_dmcub_secure_reset);</div><div class='del'>-	DC_LOG_DEBUG("    is_traceport_en    : %d", diag_data.is_traceport_en);</div><div class='del'>-	DC_LOG_DEBUG("    is_cw0_en          : %d", diag_data.is_cw0_enabled);</div><div class='del'>-	DC_LOG_DEBUG("    is_cw6_en          : %d", diag_data.is_cw6_enabled);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dc_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)</div><div class='del'>-{</div><div class='del'>-	struct pipe_ctx *test_pipe, *split_pipe;</div><div class='del'>-	const struct scaler_data *scl_data = &amp;pipe_ctx-&gt;plane_res.scl_data;</div><div class='del'>-	struct rect r1 = scl_data-&gt;recout, r2, r2_half;</div><div class='del'>-	int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;</div><div class='del'>-	int cur_layer = pipe_ctx-&gt;plane_state-&gt;layer_index;</div><div class='del'>-</div><div class='del'>-	/**</div><div class='del'>-	 * Disable the cursor if there's another pipe above this with a</div><div class='del'>-	 * plane that contains this pipe's viewport to prevent double cursor</div><div class='del'>-	 * and incorrect scaling artifacts.</div><div class='del'>-	 */</div><div class='del'>-	for (test_pipe = pipe_ctx-&gt;top_pipe; test_pipe;</div><div class='del'>-	     test_pipe = test_pipe-&gt;top_pipe) {</div><div class='del'>-		// Skip invisible layer and pipe-split plane on same layer</div><div class='del'>-		if (!test_pipe-&gt;plane_state-&gt;visible || test_pipe-&gt;plane_state-&gt;layer_index == cur_layer)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r2 = test_pipe-&gt;plane_res.scl_data.recout;</div><div class='del'>-		r2_r = r2.x + r2.width;</div><div class='del'>-		r2_b = r2.y + r2.height;</div><div class='del'>-		split_pipe = test_pipe;</div><div class='del'>-</div><div class='del'>-		/**</div><div class='del'>-		 * There is another half plane on same layer because of</div><div class='del'>-		 * pipe-split, merge together per same height.</div><div class='del'>-		 */</div><div class='del'>-		for (split_pipe = pipe_ctx-&gt;top_pipe; split_pipe;</div><div class='del'>-		     split_pipe = split_pipe-&gt;top_pipe)</div><div class='del'>-			if (split_pipe-&gt;plane_state-&gt;layer_index == test_pipe-&gt;plane_state-&gt;layer_index) {</div><div class='del'>-				r2_half = split_pipe-&gt;plane_res.scl_data.recout;</div><div class='del'>-				r2.x = (r2_half.x &lt; r2.x) ? r2_half.x : r2.x;</div><div class='del'>-				r2.width = r2.width + r2_half.width;</div><div class='del'>-				r2_r = r2.x + r2.width;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-		if (r1.x &gt;= r2.x &amp;&amp; r1.y &gt;= r2.y &amp;&amp; r1_r &lt;= r2_r &amp;&amp; r1_b &lt;= r2_b)</div><div class='del'>-			return true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='add'>+	DC_LOG_DEBUG("    dmcub_version      : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.dmcub_version);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [0]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[0]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [1]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[1]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [2]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[2]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [3]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[3]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [4]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[4]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [5]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[5]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [6]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[6]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [7]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[7]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [8]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[8]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch  [9]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[9]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch [10]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[10]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch [11]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[11]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch [12]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[12]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch [13]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[13]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch [14]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[14]);</div><div class='add'>+	DC_LOG_DEBUG("    scratch [15]       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.scratch[15]);</div><div class='add'>+	for (i = 0; i &lt; DMUB_PC_SNAPSHOT_COUNT; i++)</div><div class='add'>+		DC_LOG_DEBUG("    pc[%d]             : %08x", i, dc_dmub_srv-&gt;dmub-&gt;debug.pc[i]);</div><div class='add'>+	DC_LOG_DEBUG("    unk_fault_addr     : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.undefined_address_fault_addr);</div><div class='add'>+	DC_LOG_DEBUG("    inst_fault_addr    : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inst_fetch_fault_addr);</div><div class='add'>+	DC_LOG_DEBUG("    data_fault_addr    : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.data_write_fault_addr);</div><div class='add'>+	DC_LOG_DEBUG("    inbox1_rptr        : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inbox1_rptr);</div><div class='add'>+	DC_LOG_DEBUG("    inbox1_wptr        : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inbox1_wptr);</div><div class='add'>+	DC_LOG_DEBUG("    inbox1_size        : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inbox1_size);</div><div class='add'>+	DC_LOG_DEBUG("    inbox0_rptr        : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inbox0_rptr);</div><div class='add'>+	DC_LOG_DEBUG("    inbox0_wptr        : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inbox0_wptr);</div><div class='add'>+	DC_LOG_DEBUG("    inbox0_size        : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.inbox0_size);</div><div class='add'>+	DC_LOG_DEBUG("    outbox1_rptr       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.outbox1_rptr);</div><div class='add'>+	DC_LOG_DEBUG("    outbox1_wptr       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.outbox1_wptr);</div><div class='add'>+	DC_LOG_DEBUG("    outbox1_size       : %08x", dc_dmub_srv-&gt;dmub-&gt;debug.outbox1_size);</div><div class='add'>+	DC_LOG_DEBUG("    is_enabled         : %d", dc_dmub_srv-&gt;dmub-&gt;debug.is_dmcub_enabled);</div><div class='add'>+	DC_LOG_DEBUG("    is_soft_reset      : %d", dc_dmub_srv-&gt;dmub-&gt;debug.is_dmcub_soft_reset);</div><div class='add'>+	DC_LOG_DEBUG("    is_secure_reset    : %d", dc_dmub_srv-&gt;dmub-&gt;debug.is_dmcub_secure_reset);</div><div class='add'>+	DC_LOG_DEBUG("    is_traceport_en    : %d", dc_dmub_srv-&gt;dmub-&gt;debug.is_traceport_en);</div><div class='add'>+	DC_LOG_DEBUG("    is_cw0_en          : %d", dc_dmub_srv-&gt;dmub-&gt;debug.is_cw0_enabled);</div><div class='add'>+	DC_LOG_DEBUG("    is_cw6_en          : %d", dc_dmub_srv-&gt;dmub-&gt;debug.is_cw6_enabled);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	if (pipe_ctx-&gt;plane_state != NULL) {</div><div class='del'>-		if (pipe_ctx-&gt;plane_state-&gt;address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)</div><div class='del'>-			return false;</div><div class='del'>-</div><div class='del'>-		if (dc_can_pipe_disable_cursor(pipe_ctx))</div><div class='add'>+		if (pipe_ctx-&gt;plane_state-&gt;address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||</div><div class='add'>+			resource_can_pipe_disable_cursor(pipe_ctx))</div><div class='ctx'> 			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1168,6 +1171,100 @@ void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, con</div><div class='ctx'> 	dmub_srv_subvp_save_surf_addr(dc_dmub_srv-&gt;dmub, addr, subvp_index);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dc_dmub_srv_cursor_offload_init(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dmub_rb_cmd_cursor_offload_init *init;</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;config.enable_cursor_offload)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv-&gt;dmub-&gt;meta_info.feature_bits.bits.cursor_offload_v1_support)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv-&gt;dmub-&gt;cursor_offload_fb.gpu_addr || !dc_dmub_srv-&gt;dmub-&gt;cursor_offload_fb.cpu_addr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv-&gt;dmub-&gt;cursor_offload_v1)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv-&gt;dmub-&gt;shared_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	init = &amp;cmd.cursor_offload_init;</div><div class='add'>+	init-&gt;header.type = DMUB_CMD__CURSOR_OFFLOAD;</div><div class='add'>+	init-&gt;header.sub_type = DMUB_CMD__CURSOR_OFFLOAD_INIT;</div><div class='add'>+	init-&gt;header.payload_bytes = sizeof(init-&gt;init_data);</div><div class='add'>+	init-&gt;init_data.state_addr.quad_part = dc_dmub_srv-&gt;dmub-&gt;cursor_offload_fb.gpu_addr;</div><div class='add'>+	init-&gt;init_data.state_size = dc_dmub_srv-&gt;dmub-&gt;cursor_offload_fb.size;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+</div><div class='add'>+	dc_dmub_srv-&gt;cursor_offload_enabled = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,</div><div class='add'>+					const struct dc_stream_state *stream, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx const *pipe_ctx;</div><div class='add'>+	struct dmub_rb_cmd_cursor_offload_stream_cntl *cntl;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv_is_cursor_offload_enabled(dc))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pipe_ctx = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, stream);</div><div class='add'>+	if (!pipe_ctx || !pipe_ctx-&gt;stream_res.tg || pipe_ctx-&gt;stream != stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cntl = &amp;cmd.cursor_offload_stream_ctnl;</div><div class='add'>+	cntl-&gt;header.type = DMUB_CMD__CURSOR_OFFLOAD;</div><div class='add'>+	cntl-&gt;header.sub_type =</div><div class='add'>+		enable ? DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE : DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE;</div><div class='add'>+	cntl-&gt;header.payload_bytes = sizeof(cntl-&gt;data);</div><div class='add'>+</div><div class='add'>+	cntl-&gt;data.otg_inst = pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+	cntl-&gt;data.line_time_in_ns = 1u + (uint32_t)(div64_u64(stream-&gt;timing.h_total * 1000000ull,</div><div class='add'>+							       stream-&gt;timing.pix_clk_100hz / 10));</div><div class='add'>+</div><div class='add'>+	cntl-&gt;data.v_total_max = stream-&gt;adjust.v_total_max &gt; stream-&gt;timing.v_total ?</div><div class='add'>+					 stream-&gt;adjust.v_total_max :</div><div class='add'>+					 stream-&gt;timing.v_total;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd,</div><div class='add'>+				     enable ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	struct dmub_rb_cmd_cursor_offload_stream_cntl *cntl;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv_is_cursor_offload_enabled(dc))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!pipe || !pipe-&gt;stream || !pipe-&gt;stream_res.tg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cntl = &amp;cmd.cursor_offload_stream_ctnl;</div><div class='add'>+	cntl-&gt;header.type = DMUB_CMD__CURSOR_OFFLOAD;</div><div class='add'>+	cntl-&gt;header.sub_type = DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM;</div><div class='add'>+	cntl-&gt;header.payload_bytes = sizeof(cntl-&gt;data);</div><div class='add'>+	cntl-&gt;data.otg_inst = pipe-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *dc_ctx;</div><div class='hunk'>@@ -1199,8 +1296,23 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int count_active_streams(const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	int i, count = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; ++i) {</div><div class='add'>+		struct dc_stream_state *stream = dc-&gt;current_state-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+		if (stream &amp;&amp; (!stream-&gt;dpms_off || dc-&gt;config.disable_ips_in_dpms_off))</div><div class='add'>+			count += 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)</div><div class='ctx'> {</div><div class='add'>+	volatile const struct dmub_shared_state_ips_fw *ips_fw;</div><div class='ctx'> 	struct dc_dmub_srv *dc_dmub_srv;</div><div class='ctx'> 	union dmub_rb_cmd cmd = {0};</div><div class='ctx'> </div><div class='hunk'>@@ -1211,6 +1323,7 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+	ips_fw = &amp;dc_dmub_srv-&gt;dmub-&gt;shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> 	cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;</div><div class='hunk'>@@ -1221,43 +1334,108 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)</div><div class='ctx'> </div><div class='ctx'> 	cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;work_arounds.skip_psr_ips_crtc_disable)</div><div class='add'>+		cmd.idle_opt_notify_idle.cntl_data.skip_otg_disable = true;</div><div class='add'>+</div><div class='ctx'> 	if (allow_idle) {</div><div class='ctx'> 		volatile struct dmub_shared_state_ips_driver *ips_driver =</div><div class='ctx'> 			&amp;dc_dmub_srv-&gt;dmub-&gt;shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;</div><div class='ctx'> 		union dmub_shared_state_ips_driver_signals new_signals;</div><div class='ctx'> </div><div class='del'>-		dc_dmub_srv_wait_idle(dc-&gt;ctx-&gt;dmub_srv);</div><div class='add'>+		DC_LOG_IPS(</div><div class='add'>+			"%s wait idle (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+			__func__,</div><div class='add'>+			ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+			ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='add'>+		dc_dmub_srv_wait_for_idle(dc-&gt;ctx-&gt;dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);</div><div class='ctx'> </div><div class='ctx'> 		memset(&amp;new_signals, 0, sizeof(new_signals));</div><div class='ctx'> </div><div class='add'>+		new_signals.bits.allow_idle = 1; /* always set */</div><div class='add'>+</div><div class='ctx'> 		if (dc-&gt;config.disable_ips == DMUB_IPS_ENABLE ||</div><div class='ctx'> 		    dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {</div><div class='ctx'> 			new_signals.bits.allow_pg = 1;</div><div class='ctx'> 			new_signals.bits.allow_ips1 = 1;</div><div class='ctx'> 			new_signals.bits.allow_ips2 = 1;</div><div class='ctx'> 			new_signals.bits.allow_z10 = 1;</div><div class='add'>+			// New in IPSv2.0</div><div class='add'>+			new_signals.bits.allow_ips1z8 = 1;</div><div class='ctx'> 		} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_IPS1) {</div><div class='ctx'> 			new_signals.bits.allow_ips1 = 1;</div><div class='ctx'> 		} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_IPS2) {</div><div class='add'>+			// IPSv1.0 only</div><div class='ctx'> 			new_signals.bits.allow_pg = 1;</div><div class='ctx'> 			new_signals.bits.allow_ips1 = 1;</div><div class='ctx'> 		} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {</div><div class='add'>+			// IPSv1.0 only</div><div class='add'>+			new_signals.bits.allow_pg = 1;</div><div class='add'>+			new_signals.bits.allow_ips1 = 1;</div><div class='add'>+			new_signals.bits.allow_ips2 = 1;</div><div class='add'>+		} else if (dc-&gt;config.disable_ips == DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF) {</div><div class='add'>+			/* TODO: Move this logic out to hwseq */</div><div class='add'>+			if (count_active_streams(dc) == 0) {</div><div class='add'>+				/* IPS2 - Display off */</div><div class='add'>+				new_signals.bits.allow_pg = 1;</div><div class='add'>+				new_signals.bits.allow_ips1 = 1;</div><div class='add'>+				new_signals.bits.allow_ips2 = 1;</div><div class='add'>+				new_signals.bits.allow_z10 = 1;</div><div class='add'>+				// New in IPSv2.0</div><div class='add'>+				new_signals.bits.allow_ips1z8 = 1;</div><div class='add'>+			} else {</div><div class='add'>+				/* RCG only */</div><div class='add'>+				new_signals.bits.allow_pg = 0;</div><div class='add'>+				new_signals.bits.allow_ips1 = 1;</div><div class='add'>+				new_signals.bits.allow_ips2 = 0;</div><div class='add'>+				new_signals.bits.allow_z10 = 0;</div><div class='add'>+			}</div><div class='add'>+		} else if (dc-&gt;config.disable_ips == DMUB_IPS_DISABLE_Z8_RETENTION) {</div><div class='ctx'> 			new_signals.bits.allow_pg = 1;</div><div class='ctx'> 			new_signals.bits.allow_ips1 = 1;</div><div class='ctx'> 			new_signals.bits.allow_ips2 = 1;</div><div class='add'>+			new_signals.bits.allow_z10 = 1;</div><div class='add'>+		}</div><div class='add'>+		// Setting RCG allow bits (IPSv2.0)</div><div class='add'>+		if (dc-&gt;config.disable_ips_rcg == DMUB_IPS_RCG_ENABLE) {</div><div class='add'>+			new_signals.bits.allow_ips0_rcg = 1;</div><div class='add'>+			new_signals.bits.allow_ips1_rcg = 1;</div><div class='add'>+		} else if (dc-&gt;config.disable_ips_rcg == DMUB_IPS0_RCG_DISABLE) {</div><div class='add'>+			new_signals.bits.allow_ips1_rcg = 1;</div><div class='add'>+		} else if (dc-&gt;config.disable_ips_rcg == DMUB_IPS1_RCG_DISABLE) {</div><div class='add'>+			new_signals.bits.allow_ips0_rcg = 1;</div><div class='add'>+		}</div><div class='add'>+		// IPS dynamic allow bits (IPSv2 change, vpb use case)</div><div class='add'>+		if (dc-&gt;config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG) {</div><div class='add'>+			new_signals.bits.allow_dynamic_ips1 = 1;</div><div class='add'>+		} else if (dc-&gt;config.disable_ips_in_vpb == DMUB_IPS_VPB_ENABLE_ALL) {</div><div class='add'>+			new_signals.bits.allow_dynamic_ips1 = 1;</div><div class='add'>+			new_signals.bits.allow_dynamic_ips1_z8 = 1;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='ctx'> 		ips_driver-&gt;signals = new_signals;</div><div class='add'>+		dc_dmub_srv-&gt;driver_signals = ips_driver-&gt;signals;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	DC_LOG_IPS(</div><div class='add'>+		"%s send allow_idle=%d (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+		__func__,</div><div class='add'>+		allow_idle,</div><div class='add'>+		ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+		ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='ctx'> 	/* NOTE: This does not use the "wake" interface since this is part of the wake path. */</div><div class='ctx'> 	/* We also do not perform a wait since DMCUB could enter idle after the notification. */</div><div class='ctx'> 	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, allow_idle ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+</div><div class='add'>+	/* Register access should stop at this point. */</div><div class='add'>+	if (allow_idle)</div><div class='add'>+		dc_dmub_srv-&gt;needs_idle_wake = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_dmub_srv *dc_dmub_srv;</div><div class='add'>+	uint32_t rcg_exit_count = 0, ips1_exit_count = 0, ips2_exit_count = 0, ips1z8_exit_count = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;debug.dmcub_emulation)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1274,43 +1452,124 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> 			&amp;dc_dmub_srv-&gt;dmub-&gt;shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER].data.ips_driver;</div><div class='ctx'> 		union dmub_shared_state_ips_driver_signals prev_driver_signals = ips_driver-&gt;signals;</div><div class='ctx'> </div><div class='add'>+		rcg_exit_count = ips_fw-&gt;rcg_exit_count;</div><div class='add'>+		ips1_exit_count = ips_fw-&gt;ips1_exit_count;</div><div class='add'>+		ips2_exit_count = ips_fw-&gt;ips2_exit_count;</div><div class='add'>+		ips1z8_exit_count = ips_fw-&gt;ips1_z8ret_exit_count;</div><div class='add'>+</div><div class='ctx'> 		ips_driver-&gt;signals.all = 0;</div><div class='add'>+		dc_dmub_srv-&gt;driver_signals = ips_driver-&gt;signals;</div><div class='add'>+</div><div class='add'>+		DC_LOG_IPS(</div><div class='add'>+			"%s (allow ips1=%u ips2=%u) (commit ips1=%u ips2=%u ips1z8=%u) (count rcg=%u ips1=%u ips2=%u ips1_z8=%u)",</div><div class='add'>+			__func__,</div><div class='add'>+			ips_driver-&gt;signals.bits.allow_ips1,</div><div class='add'>+			ips_driver-&gt;signals.bits.allow_ips2,</div><div class='add'>+			ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+			ips_fw-&gt;signals.bits.ips2_commit,</div><div class='add'>+			ips_fw-&gt;signals.bits.ips1z8_commit,</div><div class='add'>+			ips_fw-&gt;rcg_entry_count,</div><div class='add'>+			ips_fw-&gt;ips1_entry_count,</div><div class='add'>+			ips_fw-&gt;ips2_entry_count,</div><div class='add'>+			ips_fw-&gt;ips1_z8ret_entry_count);</div><div class='add'>+</div><div class='add'>+		/* Note: register access has technically not resumed for DCN here, but we</div><div class='add'>+		 * need to be message PMFW through our standard register interface.</div><div class='add'>+		 */</div><div class='add'>+		dc_dmub_srv-&gt;needs_idle_wake = false;</div><div class='add'>+</div><div class='add'>+		if (!dc-&gt;caps.ips_v2_support &amp;&amp; ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) &amp;&amp;</div><div class='add'>+		    (!dc-&gt;debug.optimize_ips_handshake ||</div><div class='add'>+		     ips_fw-&gt;signals.bits.ips2_commit || !ips_fw-&gt;signals.bits.in_idle))) {</div><div class='add'>+			DC_LOG_IPS(</div><div class='add'>+				"wait IPS2 eval (ips1_commit=%u ips2_commit=%u )",</div><div class='add'>+				ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+				ips_fw-&gt;signals.bits.ips2_commit);</div><div class='ctx'> </div><div class='del'>-		if (prev_driver_signals.bits.allow_ips2) {</div><div class='del'>-			udelay(dc-&gt;debug.ips2_eval_delay_us);</div><div class='add'>+			if (!dc-&gt;debug.optimize_ips_handshake || !ips_fw-&gt;signals.bits.ips2_commit)</div><div class='add'>+				udelay(dc-&gt;debug.ips2_eval_delay_us);</div><div class='add'>+</div><div class='add'>+			DC_LOG_IPS(</div><div class='add'>+				"exit IPS2 #1 (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+				ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+				ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='add'>+			// Tell PMFW to exit low power state</div><div class='add'>+			dc-&gt;clk_mgr-&gt;funcs-&gt;exit_low_power_state(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 			if (ips_fw-&gt;signals.bits.ips2_commit) {</div><div class='del'>-				// Tell PMFW to exit low power state</div><div class='del'>-				dc-&gt;clk_mgr-&gt;funcs-&gt;exit_low_power_state(dc-&gt;clk_mgr);</div><div class='add'>+</div><div class='add'>+				DC_LOG_IPS(</div><div class='add'>+					"wait IPS2 entry delay (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+					ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+					ips_fw-&gt;signals.bits.ips2_commit);</div><div class='ctx'> </div><div class='ctx'> 				// Wait for IPS2 entry upper bound</div><div class='ctx'> 				udelay(dc-&gt;debug.ips2_entry_delay_us);</div><div class='ctx'> </div><div class='add'>+				DC_LOG_IPS(</div><div class='add'>+					"exit IPS2 #2 (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+					ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+					ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;funcs-&gt;exit_low_power_state(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='add'>+				DC_LOG_IPS(</div><div class='add'>+					"wait IPS2 commit clear (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+					ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+					ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='ctx'> 				while (ips_fw-&gt;signals.bits.ips2_commit)</div><div class='ctx'> 					udelay(1);</div><div class='ctx'> </div><div class='add'>+				DC_LOG_IPS(</div><div class='add'>+					"wait hw_pwr_up (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+					ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+					ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='ctx'> 				if (!dc_dmub_srv_is_hw_pwr_up(dc-&gt;ctx-&gt;dmub_srv, true))</div><div class='ctx'> 					ASSERT(0);</div><div class='ctx'> </div><div class='del'>-				dmub_srv_sync_inbox1(dc-&gt;ctx-&gt;dmub_srv-&gt;dmub);</div><div class='add'>+				DC_LOG_IPS(</div><div class='add'>+					"resync inbox1 (ips1_commit=%u ips2_commit=%u)",</div><div class='add'>+					ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+					ips_fw-&gt;signals.bits.ips2_commit);</div><div class='add'>+</div><div class='add'>+				dmub_srv_sync_inboxes(dc-&gt;ctx-&gt;dmub_srv-&gt;dmub);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dc_dmub_srv_notify_idle(dc, false);</div><div class='del'>-		if (prev_driver_signals.bits.allow_ips1) {</div><div class='add'>+		if (prev_driver_signals.bits.allow_ips1 || prev_driver_signals.all == 0) {</div><div class='add'>+			DC_LOG_IPS(</div><div class='add'>+				"wait for IPS1 commit clear (ips1_commit=%u ips2_commit=%u ips1z8=%u)",</div><div class='add'>+				ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+				ips_fw-&gt;signals.bits.ips2_commit,</div><div class='add'>+				ips_fw-&gt;signals.bits.ips1z8_commit);</div><div class='add'>+</div><div class='ctx'> 			while (ips_fw-&gt;signals.bits.ips1_commit)</div><div class='ctx'> 				udelay(1);</div><div class='ctx'> </div><div class='add'>+			DC_LOG_IPS(</div><div class='add'>+				"wait for IPS1 commit clear done (ips1_commit=%u ips2_commit=%u ips1z8=%u)",</div><div class='add'>+				ips_fw-&gt;signals.bits.ips1_commit,</div><div class='add'>+				ips_fw-&gt;signals.bits.ips2_commit,</div><div class='add'>+				ips_fw-&gt;signals.bits.ips1z8_commit);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_dmub_srv_is_hw_pwr_up(dc-&gt;ctx-&gt;dmub_srv, true))</div><div class='ctx'> 		ASSERT(0);</div><div class='add'>+</div><div class='add'>+	DC_LOG_IPS("%s exit (count rcg=%u ips1=%u ips2=%u ips1z8=%u)",</div><div class='add'>+		__func__,</div><div class='add'>+		rcg_exit_count,</div><div class='add'>+		ips1_exit_count,</div><div class='add'>+		ips2_exit_count,</div><div class='add'>+		ips1z8_exit_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState)</div><div class='add'>+void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmub_srv *dmub;</div><div class='ctx'> </div><div class='hunk'>@@ -1319,12 +1578,68 @@ void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_c</div><div class='ctx'> </div><div class='ctx'> 	dmub = dc_dmub_srv-&gt;dmub;</div><div class='ctx'> </div><div class='del'>-	if (powerState == DC_ACPI_CM_POWER_STATE_D0)</div><div class='add'>+	if (power_state == DC_ACPI_CM_POWER_STATE_D0)</div><div class='ctx'> 		dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0);</div><div class='ctx'> 	else</div><div class='ctx'> 		dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+					  enum dc_acpi_cm_power_state power_state)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.idle_opt_set_dc_power_state.header.type = DMUB_CMD__IDLE_OPT;</div><div class='add'>+	cmd.idle_opt_set_dc_power_state.header.sub_type = DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE;</div><div class='add'>+	cmd.idle_opt_set_dc_power_state.header.payload_bytes =</div><div class='add'>+		sizeof(cmd.idle_opt_set_dc_power_state) - sizeof(cmd.idle_opt_set_dc_power_state.header);</div><div class='add'>+</div><div class='add'>+	if (power_state == DC_ACPI_CM_POWER_STATE_D0) {</div><div class='add'>+		cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D0;</div><div class='add'>+	} else if (power_state == DC_ACPI_CM_POWER_STATE_D3) {</div><div class='add'>+		cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D3;</div><div class='add'>+	} else {</div><div class='add'>+		cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv)</div><div class='add'>+{</div><div class='add'>+	volatile const struct dmub_shared_state_ips_fw *ips_fw;</div><div class='add'>+	bool reallow_idle = false, should_detect = false;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (dc_dmub_srv-&gt;dmub-&gt;shared_state &amp;&amp;</div><div class='add'>+	    dc_dmub_srv-&gt;dmub-&gt;meta_info.feature_bits.bits.shared_state_link_detection) {</div><div class='add'>+		ips_fw = &amp;dc_dmub_srv-&gt;dmub-&gt;shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;</div><div class='add'>+		return ips_fw-&gt;signals.bits.detection_required;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Detection may require reading scratch 0 - exit out of idle prior to the read. */</div><div class='add'>+	if (dc_dmub_srv-&gt;idle_allowed) {</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv-&gt;ctx-&gt;dc, false);</div><div class='add'>+		reallow_idle = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	should_detect = dmub_srv_should_detect(dc_dmub_srv-&gt;dmub);</div><div class='add'>+</div><div class='add'>+	/* Re-enter idle if we're not about to immediately redetect links. */</div><div class='add'>+	if (!should_detect &amp;&amp; reallow_idle &amp;&amp; dc_dmub_srv-&gt;idle_exit_counter == 0 &amp;&amp;</div><div class='add'>+	    !dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(dc_dmub_srv-&gt;ctx-&gt;dc, true);</div><div class='add'>+</div><div class='add'>+	return should_detect;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_dmub_srv *dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='hunk'>@@ -1332,24 +1647,47 @@ void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_</div><div class='ctx'> 	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	allow_idle &amp;= (!dc-&gt;debug.ips_disallow_entry);</div><div class='add'>+</div><div class='ctx'> 	if (dc_dmub_srv-&gt;idle_allowed == allow_idle)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	DC_LOG_IPS("%s state change: old=%d new=%d", __func__, dc_dmub_srv-&gt;idle_allowed, allow_idle);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Entering a low power state requires a driver notification.</div><div class='ctx'> 	 * Powering up the hardware requires notifying PMFW and DMCUB.</div><div class='ctx'> 	 * Clearing the driver idle allow requires a DMCUB command.</div><div class='ctx'> 	 * DMCUB commands requires the DMCUB to be powered up and restored.</div><div class='del'>-	 *</div><div class='del'>-	 * Exit out early to prevent an infinite loop of DMCUB commands</div><div class='del'>-	 * triggering exit low power - use software state to track this.</div><div class='ctx'> 	 */</div><div class='del'>-	dc_dmub_srv-&gt;idle_allowed = allow_idle;</div><div class='ctx'> </div><div class='del'>-	if (!allow_idle)</div><div class='add'>+	if (!allow_idle) {</div><div class='add'>+		dc_dmub_srv-&gt;idle_exit_counter += 1;</div><div class='add'>+</div><div class='ctx'> 		dc_dmub_srv_exit_low_power_state(dc);</div><div class='del'>-	else</div><div class='add'>+		/*</div><div class='add'>+		 * Idle is considered fully exited only after the sequence above</div><div class='add'>+		 * fully completes. If we have a race of two threads exiting</div><div class='add'>+		 * at the same time then it's safe to perform the sequence</div><div class='add'>+		 * twice as long as we're not re-entering.</div><div class='add'>+		 *</div><div class='add'>+		 * Infinite command submission is avoided by using the</div><div class='add'>+		 * dm_execute_dmub_cmd submission instead of the "wake" helpers.</div><div class='add'>+		 */</div><div class='add'>+		dc_dmub_srv-&gt;idle_allowed = false;</div><div class='add'>+</div><div class='add'>+		dc_dmub_srv-&gt;idle_exit_counter -= 1;</div><div class='add'>+		if (dc_dmub_srv-&gt;idle_exit_counter &lt; 0) {</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			dc_dmub_srv-&gt;idle_exit_counter = 0;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* Consider idle as notified prior to the actual submission to</div><div class='add'>+		 * prevent multiple entries. */</div><div class='add'>+		dc_dmub_srv-&gt;idle_allowed = true;</div><div class='add'>+</div><div class='ctx'> 		dc_dmub_srv_notify_idle(dc, allow_idle);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,</div><div class='hunk'>@@ -1384,7 +1722,8 @@ bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned in</div><div class='ctx'> 	else</div><div class='ctx'> 		result = dm_execute_dmub_cmd(ctx, cmd, wait_type);</div><div class='ctx'> </div><div class='del'>-	if (result &amp;&amp; reallow_idle &amp;&amp; !ctx-&gt;dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='add'>+	if (result &amp;&amp; reallow_idle &amp;&amp; dc_dmub_srv-&gt;idle_exit_counter == 0 &amp;&amp;</div><div class='add'>+	    !ctx-&gt;dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='ctx'> 		dc_dmub_srv_apply_idle_power_optimizations(ctx-&gt;dc, true);</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='hunk'>@@ -1433,8 +1772,599 @@ bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_com</div><div class='ctx'> </div><div class='ctx'> 	result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type);</div><div class='ctx'> </div><div class='del'>-	if (result &amp;&amp; reallow_idle &amp;&amp; !ctx-&gt;dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='add'>+	if (result &amp;&amp; reallow_idle &amp;&amp; dc_dmub_srv-&gt;idle_exit_counter == 0 &amp;&amp;</div><div class='add'>+	    !ctx-&gt;dc-&gt;debug.disable_dmub_reallow_idle)</div><div class='ctx'> 		dc_dmub_srv_apply_idle_power_optimizations(ctx-&gt;dc, true);</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	uint8_t num_cmds = 1;</div><div class='add'>+	uint32_t i;</div><div class='add'>+	union dmub_rb_cmd cmd[2 * MAX_STREAMS + 1];</div><div class='add'>+	struct dmub_rb_cmd_fams2 *global_cmd = &amp;cmd[0].fams2_config;</div><div class='add'>+</div><div class='add'>+	memset(cmd, 0, sizeof(union dmub_rb_cmd) * (2 * MAX_STREAMS + 1));</div><div class='add'>+	/* fill in generic command header */</div><div class='add'>+	global_cmd-&gt;header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;</div><div class='add'>+	global_cmd-&gt;header.sub_type = DMUB_CMD__FAMS2_CONFIG;</div><div class='add'>+	global_cmd-&gt;header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		/* send global configuration parameters */</div><div class='add'>+		memcpy(&amp;global_cmd-&gt;config.global, &amp;context-&gt;bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub_cmd_fams2_global_config));</div><div class='add'>+</div><div class='add'>+		/* copy static feature configuration overrides */</div><div class='add'>+		global_cmd-&gt;config.global.features.bits.enable_stall_recovery = dc-&gt;debug.fams2_config.bits.enable_stall_recovery;</div><div class='add'>+		global_cmd-&gt;config.global.features.bits.enable_debug = dc-&gt;debug.fams2_config.bits.enable_debug;</div><div class='add'>+		global_cmd-&gt;config.global.features.bits.enable_offload_flip = dc-&gt;debug.fams2_config.bits.enable_offload_flip;</div><div class='add'>+</div><div class='add'>+		/* construct per-stream configs */</div><div class='add'>+		for (i = 0; i &lt; context-&gt;bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) {</div><div class='add'>+			struct dmub_rb_cmd_fams2 *stream_base_cmd = &amp;cmd[i+1].fams2_config;</div><div class='add'>+			struct dmub_rb_cmd_fams2 *stream_sub_state_cmd = &amp;cmd[i+1+context-&gt;bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config;</div><div class='add'>+</div><div class='add'>+			/* configure command header */</div><div class='add'>+			stream_base_cmd-&gt;header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;</div><div class='add'>+			stream_base_cmd-&gt;header.sub_type = DMUB_CMD__FAMS2_CONFIG;</div><div class='add'>+			stream_base_cmd-&gt;header.payload_bytes =</div><div class='add'>+					sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header);</div><div class='add'>+			stream_base_cmd-&gt;header.multi_cmd_pending = 1;</div><div class='add'>+			stream_sub_state_cmd-&gt;header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;</div><div class='add'>+			stream_sub_state_cmd-&gt;header.sub_type = DMUB_CMD__FAMS2_CONFIG;</div><div class='add'>+			stream_sub_state_cmd-&gt;header.payload_bytes =</div><div class='add'>+					sizeof(struct dmub_rb_cmd_fams2) - sizeof(struct dmub_cmd_header);</div><div class='add'>+			stream_sub_state_cmd-&gt;header.multi_cmd_pending = 1;</div><div class='add'>+			/* copy stream static base state */</div><div class='add'>+			memcpy(&amp;stream_base_cmd-&gt;config,</div><div class='add'>+					&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_base_params[i],</div><div class='add'>+					sizeof(union dmub_cmd_fams2_config));</div><div class='add'>+			/* copy stream static sub state */</div><div class='add'>+			memcpy(&amp;stream_sub_state_cmd-&gt;config,</div><div class='add'>+					&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_sub_params[i],</div><div class='add'>+					sizeof(union dmub_cmd_fams2_config));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* apply feature configuration based on current driver state */</div><div class='add'>+	global_cmd-&gt;config.global.features.bits.enable_visual_confirm = dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_FAMS2;</div><div class='add'>+	global_cmd-&gt;config.global.features.bits.enable = enable;</div><div class='add'>+</div><div class='add'>+	if (enable &amp;&amp; context-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {</div><div class='add'>+		/* set multi pending for global, and unset for last stream cmd */</div><div class='add'>+		global_cmd-&gt;header.multi_cmd_pending = 1;</div><div class='add'>+		cmd[2 * context-&gt;bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending = 0;</div><div class='add'>+		num_cmds += 2 * context-&gt;bw_ctx.bw.dcn.fams2_global_config.num_streams;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dm_execute_dmub_cmd_list(dc-&gt;ctx, num_cmds, cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;ib_mem_gart.cpu_addr;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='add'>+	memset(config, 0, sizeof(*config));</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.ib_fams2_config.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;</div><div class='add'>+	cmd.ib_fams2_config.header.sub_type = DMUB_CMD__FAMS2_IB_CONFIG;</div><div class='add'>+</div><div class='add'>+	cmd.ib_fams2_config.ib_data.src.quad_part = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;ib_mem_gart.gpu_addr;</div><div class='add'>+	cmd.ib_fams2_config.ib_data.size = sizeof(*config);</div><div class='add'>+</div><div class='add'>+	if (enable &amp;&amp; context-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) {</div><div class='add'>+		/* copy static feature configuration overrides */</div><div class='add'>+		config-&gt;global.features.bits.enable_stall_recovery = dc-&gt;debug.fams2_config.bits.enable_stall_recovery;</div><div class='add'>+		config-&gt;global.features.bits.enable_offload_flip = dc-&gt;debug.fams2_config.bits.enable_offload_flip;</div><div class='add'>+		config-&gt;global.features.bits.enable_debug = dc-&gt;debug.fams2_config.bits.enable_debug;</div><div class='add'>+</div><div class='add'>+		/* send global configuration parameters */</div><div class='add'>+		memcpy(&amp;config-&gt;global, &amp;context-&gt;bw_ctx.bw.dcn.fams2_global_config,</div><div class='add'>+			sizeof(struct dmub_cmd_fams2_global_config));</div><div class='add'>+</div><div class='add'>+		/* construct per-stream configs */</div><div class='add'>+		for (i = 0; i &lt; context-&gt;bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) {</div><div class='add'>+			/* copy stream static base state */</div><div class='add'>+			memcpy(&amp;config-&gt;stream_v1[i].base,</div><div class='add'>+				&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_base_params[i],</div><div class='add'>+				sizeof(config-&gt;stream_v1[i].base));</div><div class='add'>+</div><div class='add'>+			/* copy stream static sub-state */</div><div class='add'>+			memcpy(&amp;config-&gt;stream_v1[i].sub_state,</div><div class='add'>+				&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_sub_params_v2[i],</div><div class='add'>+				sizeof(config-&gt;stream_v1[i].sub_state));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	config-&gt;global.features.bits.enable_visual_confirm = dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_FAMS2;</div><div class='add'>+	config-&gt;global.features.bits.enable = enable;</div><div class='add'>+</div><div class='add'>+	dm_execute_dmub_cmd_list(dc-&gt;ctx, 1, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_fams2_update_config(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	if (dc-&gt;debug.fams_version.major == 2)</div><div class='add'>+		dc_dmub_srv_rb_based_fams2_update_config(dc, context, enable);</div><div class='add'>+	if (dc-&gt;debug.fams_version.major == 3)</div><div class='add'>+		dc_dmub_srv_ib_based_fams2_update_config(dc, context, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_fams2_drr_update(struct dc *dc,</div><div class='add'>+		uint32_t tg_inst,</div><div class='add'>+		uint32_t vtotal_min,</div><div class='add'>+		uint32_t vtotal_max,</div><div class='add'>+		uint32_t vtotal_mid,</div><div class='add'>+		uint32_t vtotal_mid_frame_num,</div><div class='add'>+		bool program_manual_trigger)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd = { 0 };</div><div class='add'>+</div><div class='add'>+	cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;</div><div class='add'>+	cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE;</div><div class='add'>+	cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst;</div><div class='add'>+	cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max;</div><div class='add'>+	cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min;</div><div class='add'>+	cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid;</div><div class='add'>+	cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid_frame_num = vtotal_mid_frame_num;</div><div class='add'>+	cmd.fams2_drr_update.dmub_optc_state_req.program_manual_trigger = program_manual_trigger;</div><div class='add'>+</div><div class='add'>+	cmd.fams2_drr_update.header.payload_bytes =</div><div class='add'>+			sizeof(cmd.fams2_drr_update) - sizeof(cmd.fams2_drr_update.header);</div><div class='add'>+</div><div class='add'>+	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_fams2_passthrough_flip(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count)</div><div class='add'>+{</div><div class='add'>+	int plane_index;</div><div class='add'>+	union dmub_rb_cmd cmds[MAX_PLANES];</div><div class='add'>+	struct dc_plane_address *address;</div><div class='add'>+	struct dc_plane_state *plane_state;</div><div class='add'>+	int num_cmds = 0;</div><div class='add'>+	struct dc_stream_status *stream_status = dc_stream_get_status(stream);</div><div class='add'>+</div><div class='add'>+	if (surface_count &lt;= 0 || stream_status == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(cmds, 0, sizeof(union dmub_rb_cmd) * MAX_PLANES);</div><div class='add'>+</div><div class='add'>+	/* build command for each surface update */</div><div class='add'>+	for (plane_index = 0; plane_index &lt; surface_count; plane_index++) {</div><div class='add'>+		plane_state = srf_updates[plane_index].surface;</div><div class='add'>+		address = &amp;plane_state-&gt;address;</div><div class='add'>+</div><div class='add'>+		/* skip if there is no address update for plane */</div><div class='add'>+		if (!srf_updates[plane_index].flip_addr)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* build command header */</div><div class='add'>+		cmds[num_cmds].fams2_flip.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;</div><div class='add'>+		cmds[num_cmds].fams2_flip.header.sub_type = DMUB_CMD__FAMS2_FLIP;</div><div class='add'>+		cmds[num_cmds].fams2_flip.header.payload_bytes =</div><div class='add'>+				sizeof(struct dmub_rb_cmd_fams2_flip) - sizeof(struct dmub_cmd_header);</div><div class='add'>+</div><div class='add'>+		/* for chaining multiple commands, all but last command should set to 1 */</div><div class='add'>+		cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1;</div><div class='add'>+</div><div class='add'>+		/* set topology info */</div><div class='add'>+		cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state);</div><div class='add'>+		if (stream_status)</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status-&gt;primary_otg_inst;</div><div class='add'>+</div><div class='add'>+		cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state-&gt;flip_immediate;</div><div class='add'>+</div><div class='add'>+		/* build address info for command */</div><div class='add'>+		switch (address-&gt;type) {</div><div class='add'>+		case PLN_ADDR_TYPE_GRAPHICS:</div><div class='add'>+			if (address-&gt;grph.addr.quad_part == 0) {</div><div class='add'>+				BREAK_TO_DEBUGGER();</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_lo =</div><div class='add'>+					address-&gt;grph.meta_addr.low_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_hi =</div><div class='add'>+					(uint16_t)address-&gt;grph.meta_addr.high_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_lo =</div><div class='add'>+					address-&gt;grph.addr.low_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_hi =</div><div class='add'>+					(uint16_t)address-&gt;grph.addr.high_part;</div><div class='add'>+			break;</div><div class='add'>+		case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:</div><div class='add'>+			if (address-&gt;video_progressive.luma_addr.quad_part == 0 ||</div><div class='add'>+				address-&gt;video_progressive.chroma_addr.quad_part == 0) {</div><div class='add'>+				BREAK_TO_DEBUGGER();</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_lo =</div><div class='add'>+					address-&gt;video_progressive.luma_meta_addr.low_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_hi =</div><div class='add'>+					(uint16_t)address-&gt;video_progressive.luma_meta_addr.high_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_c_lo =</div><div class='add'>+					address-&gt;video_progressive.chroma_meta_addr.low_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.meta_addr_c_hi =</div><div class='add'>+					(uint16_t)address-&gt;video_progressive.chroma_meta_addr.high_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_lo =</div><div class='add'>+					address-&gt;video_progressive.luma_addr.low_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_hi =</div><div class='add'>+					(uint16_t)address-&gt;video_progressive.luma_addr.high_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_c_lo =</div><div class='add'>+					address-&gt;video_progressive.chroma_addr.low_part;</div><div class='add'>+			cmds[num_cmds].fams2_flip.flip_info.addr_info.surf_addr_c_hi =</div><div class='add'>+					(uint16_t)address-&gt;video_progressive.chroma_addr.high_part;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			// Should never be hit</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		num_cmds++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (num_cmds &gt; 0)  {</div><div class='add'>+		cmds[num_cmds - 1].fams2_flip.header.multi_cmd_pending = 0;</div><div class='add'>+		dm_execute_dmub_cmd_list(dc-&gt;ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.ips_residency_cntl.header.type = DMUB_CMD__IPS;</div><div class='add'>+	cmd.ips_residency_cntl.header.sub_type = DMUB_CMD__IPS_RESIDENCY_CNTL;</div><div class='add'>+	cmd.ips_residency_cntl.header.payload_bytes = sizeof(struct dmub_cmd_ips_residency_cntl_data);</div><div class='add'>+</div><div class='add'>+	// only panel_inst=0 is supported at the moment</div><div class='add'>+	cmd.ips_residency_cntl.cntl_data.panel_inst = panel_inst;</div><div class='add'>+	cmd.ips_residency_cntl.cntl_data.start_measurement = start_measurement;</div><div class='add'>+</div><div class='add'>+	if (!dc_wake_and_execute_dmub_cmd(ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst, struct dmub_ips_residency_info *driver_info,</div><div class='add'>+					  enum ips_residency_mode ips_mode)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	uint32_t bytes = sizeof(struct dmub_ips_residency_info);</div><div class='add'>+</div><div class='add'>+	dmub_flush_buffer_mem(&amp;ctx-&gt;dmub_srv-&gt;dmub-&gt;scratch_mem_fb);</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.ips_query_residency_info.header.type = DMUB_CMD__IPS;</div><div class='add'>+	cmd.ips_query_residency_info.header.sub_type = DMUB_CMD__IPS_QUERY_RESIDENCY_INFO;</div><div class='add'>+	cmd.ips_query_residency_info.header.payload_bytes = sizeof(struct dmub_cmd_ips_query_residency_info_data);</div><div class='add'>+</div><div class='add'>+	cmd.ips_query_residency_info.info_data.dest.quad_part = ctx-&gt;dmub_srv-&gt;dmub-&gt;scratch_mem_fb.gpu_addr;</div><div class='add'>+	cmd.ips_query_residency_info.info_data.size = bytes;</div><div class='add'>+	cmd.ips_query_residency_info.info_data.panel_inst = panel_inst;</div><div class='add'>+	cmd.ips_query_residency_info.info_data.ips_mode = (uint32_t)ips_mode;</div><div class='add'>+</div><div class='add'>+	if (!dc_wake_and_execute_dmub_cmd(ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) ||</div><div class='add'>+					  cmd.ips_query_residency_info.header.ret_status == 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	// copy the result to the output since ret_status != 0 means the command returned data</div><div class='add'>+	memcpy(driver_info, ctx-&gt;dmub_srv-&gt;dmub-&gt;scratch_mem_fb.cpu_addr, bytes);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv-&gt;dmub-&gt;feature_caps.lsdma_support_in_dmu)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_INIT_CONFIG;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.init_data.gpu_addr_base.quad_part = dc_ctx-&gt;dmub_srv-&gt;dmub-&gt;lsdma_rb_fb.gpu_addr;</div><div class='add'>+	lsdma_data-&gt;u.init_data.ring_size               = dc_ctx-&gt;dmub_srv-&gt;dmub-&gt;lsdma_rb_fb.size;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA Init failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_linear_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	uint64_t src_addr,</div><div class='add'>+	uint64_t dst_addr,</div><div class='add'>+	uint32_t count</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_LINEAR_COPY;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.linear_copy_data.count   = count - 1; // LSDMA controller expects bytes to copy -1</div><div class='add'>+	lsdma_data-&gt;u.linear_copy_data.src_lo  = src_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.linear_copy_data.src_hi  = (src_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.linear_copy_data.dst_lo  = dst_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.linear_copy_data.dst_hi  = (dst_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA Linear Copy failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_linear_sub_window_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	struct lsdma_linear_sub_window_copy_params copy_data</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.tmz              = copy_data.tmz;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.element_size     = copy_data.element_size;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_lo           = copy_data.src_lo;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_hi           = copy_data.src_hi;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_x            = copy_data.src_x;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_y            = copy_data.src_y;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_pitch        = copy_data.src_pitch;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_slice_pitch  = copy_data.src_slice_pitch;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_lo           = copy_data.dst_lo;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_hi           = copy_data.dst_hi;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_x            = copy_data.dst_x;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_y            = copy_data.dst_y;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_pitch        = copy_data.dst_pitch;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_slice_pitch  = copy_data.dst_slice_pitch;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.rect_x           = copy_data.rect_x;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.rect_y           = copy_data.rect_y;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.src_cache_policy = copy_data.src_cache_policy;</div><div class='add'>+	lsdma_data-&gt;u.linear_sub_window_copy_data.dst_cache_policy = copy_data.dst_cache_policy;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA Linear Sub Window Copy failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_tiled_to_tiled_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	struct lsdma_send_tiled_to_tiled_copy_command_params params</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_TILED_TO_TILED_COPY;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_addr_lo      = params.src_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_addr_hi      = (params.src_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_addr_lo      = params.dst_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_addr_hi      = (params.dst_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_x            = params.src_x;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_y            = params.src_y;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_x            = params.dst_x;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_y            = params.dst_y;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_width        = params.src_width;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_width        = params.dst_width;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_swizzle_mode = params.swizzle_mode;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_swizzle_mode = params.swizzle_mode;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_element_size = params.element_size;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_element_size = params.element_size;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.rect_x           = params.rect_x;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.rect_y           = params.rect_y;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dcc              = params.dcc;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.tmz              = params.tmz;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.read_compress    = params.read_compress;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.write_compress   = params.write_compress;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.src_height       = params.src_height;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.dst_height       = params.dst_height;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.data_format      = params.data_format;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.max_com          = params.max_com;</div><div class='add'>+	lsdma_data-&gt;u.tiled_copy_data.max_uncom        = params.max_uncom;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA Tiled to Tiled Copy failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_pio_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	uint64_t src_addr,</div><div class='add'>+	uint64_t dst_addr,</div><div class='add'>+	uint32_t byte_count,</div><div class='add'>+	uint32_t overlap_disable</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_PIO_COPY;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.pio_copy_data.packet.fields.byte_count      = byte_count;</div><div class='add'>+	lsdma_data-&gt;u.pio_copy_data.packet.fields.overlap_disable = overlap_disable;</div><div class='add'>+	lsdma_data-&gt;u.pio_copy_data.src_lo                        = src_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.pio_copy_data.src_hi                        = (src_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.pio_copy_data.dst_lo                        = dst_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.pio_copy_data.dst_hi                        = (dst_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA PIO Copy failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_pio_constfill_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	uint64_t dst_addr,</div><div class='add'>+	uint32_t byte_count,</div><div class='add'>+	uint32_t data</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_PIO_CONSTFILL;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.pio_constfill_data.packet.fields.constant_fill = 1;</div><div class='add'>+	lsdma_data-&gt;u.pio_constfill_data.packet.fields.byte_count    = byte_count;</div><div class='add'>+	lsdma_data-&gt;u.pio_constfill_data.dst_lo                      = dst_addr &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.pio_constfill_data.dst_hi                      = (dst_addr &gt;&gt; 32) &amp; 0xFFFFFFFF;</div><div class='add'>+	lsdma_data-&gt;u.pio_constfill_data.data                        = data;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA PIO Constfill failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	enum dm_dmub_wait_type wait_type;</div><div class='add'>+	struct dmub_cmd_lsdma_data *lsdma_data = &amp;cmd.lsdma.lsdma_data;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.cmd_common.header.type     = DMUB_CMD__LSDMA;</div><div class='add'>+	cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_POLL_REG_WRITE;</div><div class='add'>+	wait_type                      = DM_DMUB_WAIT_TYPE_NO_WAIT;</div><div class='add'>+</div><div class='add'>+	lsdma_data-&gt;u.reg_write_data.reg_addr = reg_addr;</div><div class='add'>+	lsdma_data-&gt;u.reg_write_data.reg_data = reg_data;</div><div class='add'>+</div><div class='add'>+	result = dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (!result)</div><div class='add'>+		DC_ERROR("LSDMA Poll Reg failed in DMUB");</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	return dc-&gt;ctx-&gt;dmub_srv &amp;&amp; dc-&gt;ctx-&gt;dmub_srv-&gt;cursor_offload_enabled;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_release_hw(const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+	union dmub_rb_cmd cmd = {0};</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+	cmd.idle_opt_notify_idle.header.type = DMUB_CMD__IDLE_OPT;</div><div class='add'>+	cmd.idle_opt_notify_idle.header.sub_type = DMUB_CMD__IDLE_OPT_RELEASE_HW;</div><div class='add'>+	cmd.idle_opt_notify_idle.header.payload_bytes =</div><div class='add'>+		sizeof(cmd.idle_opt_notify_idle) -</div><div class='add'>+		sizeof(cmd.idle_opt_notify_idle.header);</div><div class='add'>+</div><div class='add'>+	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd,  DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv)</div><div class='add'>+{</div><div class='add'>+	struct dmub_srv *dmub;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dmub = dc_dmub_srv-&gt;dmub;</div><div class='add'>+</div><div class='add'>+	if (dmub_srv_get_preos_info(dmub)) {</div><div class='add'>+		DC_LOG_DEBUG("%s: PreOS DMCUB Info", __func__);</div><div class='add'>+		DC_LOG_DEBUG("fw_version				: 0x%08x", dmub-&gt;preos_info.fw_version);</div><div class='add'>+		DC_LOG_DEBUG("boot_options				: 0x%08x", dmub-&gt;preos_info.boot_options);</div><div class='add'>+		DC_LOG_DEBUG("boot_status				: 0x%08x", dmub-&gt;preos_info.boot_status);</div><div class='add'>+		DC_LOG_DEBUG("trace_buffer_phy_addr		: 0x%016llx", dmub-&gt;preos_info.trace_buffer_phy_addr);</div><div class='add'>+		DC_LOG_DEBUG("trace_buffer_size_bytes	: 0x%08x", dmub-&gt;preos_info.trace_buffer_size);</div><div class='add'>+		DC_LOG_DEBUG("fb_base					: 0x%016llx", dmub-&gt;preos_info.fb_base);</div><div class='add'>+		DC_LOG_DEBUG("fb_offset					: 0x%016llx", dmub-&gt;preos_info.fb_offset);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h<br/>index 952bfb368886..72e0a41f39f0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h</a></div><div class='hunk'>@@ -35,6 +35,7 @@ struct pipe_ctx;</div><div class='ctx'> struct dc_crtc_timing_adjust;</div><div class='ctx'> struct dc_crtc_timing;</div><div class='ctx'> struct dc_state;</div><div class='add'>+struct dc_surface_update;</div><div class='ctx'> </div><div class='ctx'> struct dc_reg_helper_state {</div><div class='ctx'> 	bool gather_in_progress;</div><div class='hunk'>@@ -51,10 +52,14 @@ struct dc_dmub_srv {</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='ctx'> 	void *dm;</div><div class='ctx'> </div><div class='add'>+	int32_t idle_exit_counter;</div><div class='add'>+	union dmub_shared_state_ips_driver_signals driver_signals;</div><div class='ctx'> 	bool idle_allowed;</div><div class='add'>+	bool needs_idle_wake;</div><div class='add'>+	bool cursor_offload_enabled;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);</div><div class='add'>+bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv);</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);</div><div class='ctx'> </div><div class='hunk'>@@ -71,7 +76,7 @@ bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd</div><div class='ctx'> bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type);</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,</div><div class='del'>-				    unsigned int stream_mask);</div><div class='add'>+				   unsigned int stream_mask);</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);</div><div class='ctx'> </div><div class='hunk'>@@ -90,7 +95,7 @@ void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);</div><div class='ctx'> void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);</div><div class='ctx'> void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);</div><div class='ctx'> </div><div class='del'>-bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *dmub_oca);</div><div class='add'>+bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);</div><div class='ctx'> </div><div class='ctx'> void dc_dmub_setup_subvp_dmub_command(struct dc *dc, struct dc_state *context, bool enable);</div><div class='ctx'> void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);</div><div class='hunk'>@@ -105,7 +110,39 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait);</div><div class='ctx'> </div><div class='ctx'> void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);</div><div class='ctx'> </div><div class='del'>-void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState);</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_set_power_state() - Sets the power state for DMUB service.</div><div class='add'>+ *</div><div class='add'>+ * Controls whether messaging the DMCUB or interfacing with it via HW register</div><div class='add'>+ * interaction is permittable.</div><div class='add'>+ *</div><div class='add'>+ * @dc_dmub_srv - The DC DMUB service pointer</div><div class='add'>+ * @power_state - the DC power state</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_notify_fw_dc_power_state() - Notifies firmware of the DC power state.</div><div class='add'>+ *</div><div class='add'>+ * Differs from dc_dmub_srv_set_power_state in that it needs to access HW in order</div><div class='add'>+ * to message DMCUB of the state transition. Should come after the D0 exit and</div><div class='add'>+ * before D3 set power state.</div><div class='add'>+ *</div><div class='add'>+ * @dc_dmub_srv - The DC DMUB service pointer</div><div class='add'>+ * @power_state - the DC power state</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+					  enum dc_acpi_cm_power_state power_state);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * @dc_dmub_srv_should_detect() - Checks if link detection is required.</div><div class='add'>+ *</div><div class='add'>+ * While in idle power states we may need driver to manually redetect in</div><div class='add'>+ * the case of a missing hotplug. Should be called from a polling timer.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if redetection is required.</div><div class='add'>+ */</div><div class='add'>+bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution.</div><div class='hunk'>@@ -157,4 +194,184 @@ bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned in</div><div class='ctx'> bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,</div><div class='ctx'> 			       uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type);</div><div class='ctx'> </div><div class='add'>+void dc_dmub_srv_fams2_update_config(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool enable);</div><div class='add'>+void dc_dmub_srv_fams2_drr_update(struct dc *dc,</div><div class='add'>+		uint32_t tg_inst,</div><div class='add'>+		uint32_t vtotal_min,</div><div class='add'>+		uint32_t vtotal_max,</div><div class='add'>+		uint32_t vtotal_mid,</div><div class='add'>+		uint32_t vtotal_mid_frame_num,</div><div class='add'>+		bool program_manual_trigger);</div><div class='add'>+void dc_dmub_srv_fams2_passthrough_flip(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_surface_update *srf_updates,</div><div class='add'>+		int surface_count);</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv);</div><div class='add'>+bool dmub_lsdma_send_linear_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	uint64_t src_addr,</div><div class='add'>+	uint64_t dst_addr,</div><div class='add'>+	uint32_t count);</div><div class='add'>+</div><div class='add'>+struct lsdma_linear_sub_window_copy_params {</div><div class='add'>+	uint32_t src_lo;</div><div class='add'>+	uint32_t src_hi;</div><div class='add'>+</div><div class='add'>+	uint32_t dst_lo;</div><div class='add'>+	uint32_t dst_hi;</div><div class='add'>+</div><div class='add'>+	uint32_t src_x        : 16;</div><div class='add'>+	uint32_t src_y        : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t dst_x        : 16;</div><div class='add'>+	uint32_t dst_y        : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t rect_x       : 16;</div><div class='add'>+	uint32_t rect_y       : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t src_pitch    : 16;</div><div class='add'>+	uint32_t dst_pitch    : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t src_slice_pitch;</div><div class='add'>+	uint32_t dst_slice_pitch;</div><div class='add'>+</div><div class='add'>+	uint32_t tmz              : 1;</div><div class='add'>+	uint32_t element_size     : 3;</div><div class='add'>+	uint32_t src_cache_policy : 3;</div><div class='add'>+	uint32_t dst_cache_policy : 3;</div><div class='add'>+	uint32_t padding          : 22;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_linear_sub_window_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	struct lsdma_linear_sub_window_copy_params copy_data</div><div class='add'>+);</div><div class='add'>+bool dmub_lsdma_send_pio_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	uint64_t src_addr,</div><div class='add'>+	uint64_t dst_addr,</div><div class='add'>+	uint32_t byte_count,</div><div class='add'>+	uint32_t overlap_disable);</div><div class='add'>+bool dmub_lsdma_send_pio_constfill_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	uint64_t dst_addr,</div><div class='add'>+	uint32_t byte_count,</div><div class='add'>+	uint32_t data);</div><div class='add'>+</div><div class='add'>+struct lsdma_send_tiled_to_tiled_copy_command_params {</div><div class='add'>+	uint64_t src_addr;</div><div class='add'>+	uint64_t dst_addr;</div><div class='add'>+</div><div class='add'>+	uint32_t src_x            : 16;</div><div class='add'>+	uint32_t src_y            : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t dst_x            : 16;</div><div class='add'>+	uint32_t dst_y            : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t src_width        : 16;</div><div class='add'>+	uint32_t dst_width        : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t rect_x           : 16;</div><div class='add'>+	uint32_t rect_y           : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t src_height       : 16;</div><div class='add'>+	uint32_t dst_height       : 16;</div><div class='add'>+</div><div class='add'>+	uint32_t data_format      : 6;</div><div class='add'>+	uint32_t swizzle_mode     : 5;</div><div class='add'>+	uint32_t element_size     : 3;</div><div class='add'>+	uint32_t dcc              : 1;</div><div class='add'>+	uint32_t tmz              : 1;</div><div class='add'>+	uint32_t read_compress    : 2;</div><div class='add'>+	uint32_t write_compress   : 2;</div><div class='add'>+	uint32_t max_com          : 2;</div><div class='add'>+	uint32_t max_uncom        : 1;</div><div class='add'>+	uint32_t padding          : 9;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dmub_lsdma_send_tiled_to_tiled_copy_command(</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv,</div><div class='add'>+	struct lsdma_send_tiled_to_tiled_copy_command_params params);</div><div class='add'>+bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uint32_t reg_addr, uint32_t reg_data);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct ips_residency_info - struct containing info from dmub_ips_residency_stats</div><div class='add'>+ *</div><div class='add'>+ * @ips_mode: The mode of IPS that the follow stats appertain to</div><div class='add'>+ * @residency_percent: The percentage of time spent in given IPS mode in millipercent</div><div class='add'>+ * @entry_counter: The number of entries made in to this IPS state</div><div class='add'>+ * @total_active_time_us: uint32_t array of length 2 representing time in the given IPS mode</div><div class='add'>+ *                        in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits.</div><div class='add'>+ * @total_inactive_time_us: uint32_t array of length 2 representing time outside the given IPS mode</div><div class='add'>+ *                          in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits.</div><div class='add'>+ * @histogram: Histogram of given IPS state durations - bucket definitions in dmub_ips.c</div><div class='add'>+ */</div><div class='add'>+struct ips_residency_info {</div><div class='add'>+	enum ips_residency_mode ips_mode;</div><div class='add'>+	unsigned int residency_percent;</div><div class='add'>+	unsigned int entry_counter;</div><div class='add'>+	unsigned int total_active_time_us[2];</div><div class='add'>+	unsigned int total_inactive_time_us[2];</div><div class='add'>+	unsigned int histogram[16];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_ips_residency_cntl(const struct dc_context *ctx, uint8_t panel_inst, bool start_measurement);</div><div class='add'>+</div><div class='add'>+bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t panel_inst,</div><div class='add'>+					  struct dmub_ips_residency_info *driver_info,</div><div class='add'>+					  enum ips_residency_mode ips_mode);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_cursor_offload_init() - Enables or disables cursor offloading for a stream.</div><div class='add'>+ *</div><div class='add'>+ * @dc: pointer to DC object</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_cursor_offload_init(struct dc *dc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_control_cursor_offload() - Enables or disables cursor offloading for a stream.</div><div class='add'>+ *</div><div class='add'>+ * @dc: pointer to DC object</div><div class='add'>+ * @context: the DC context to reference for pipe allocations</div><div class='add'>+ * @stream: the stream to control</div><div class='add'>+ * @enable: true to enable cursor offload, false to disable</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context,</div><div class='add'>+					const struct dc_stream_state *stream, bool enable);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_program_cursor_now() - Requests immediate cursor programming for a given pipe.</div><div class='add'>+ *</div><div class='add'>+ * @dc: pointer to DC object</div><div class='add'>+ * @pipe: top-most pipe for a stream.</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_is_cursor_offload_enabled() - Checks if cursor offload is supported.</div><div class='add'>+ *</div><div class='add'>+ * @dc: pointer to DC object</div><div class='add'>+ *</div><div class='add'>+ * Return: true if cursor offload is supported, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required.</div><div class='add'>+ *</div><div class='add'>+ * @dc - pointer to DC object</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_release_hw(const struct dc *dc);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_dmub_srv_log_preos_dmcub_info() - Logs preos dmcub fw info.</div><div class='add'>+ *</div><div class='add'>+ * @dc - pointer to DC object</div><div class='add'>+ */</div><div class='add'>+void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv);</div><div class='ctx'> #endif /* _DMUB_DC_SRV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h<br/>index 1cb7765f593a..79e1696def63 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dp_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dp_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dp_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_dp_types.h</a></div><div class='hunk'>@@ -137,8 +137,13 @@ enum dp_link_encoding {</div><div class='ctx'> </div><div class='ctx'> enum dp_test_link_rate {</div><div class='ctx'> 	DP_TEST_LINK_RATE_RBR		= 0x06,</div><div class='add'>+	DP_TEST_LINK_RATE_RATE_2    = 0x08,	// Rate_2        - 2.16 Gbps/Lane</div><div class='add'>+	DP_TEST_LINK_RATE_RATE_3    = 0x09,	// Rate_3        - 2.43 Gbps/Lane</div><div class='ctx'> 	DP_TEST_LINK_RATE_HBR		= 0x0A,</div><div class='add'>+	DP_TEST_LINK_RATE_RBR2      = 0x0C,	// Rate_5 (RBR2) - 3.24 Gbps/Lane</div><div class='add'>+	DP_TEST_LINK_RATE_RATE_6    = 0x10,	// Rate_6        - 4.32 Gbps/Lane</div><div class='ctx'> 	DP_TEST_LINK_RATE_HBR2		= 0x14,</div><div class='add'>+	DP_TEST_LINK_RATE_RATE_8    = 0x19,	// Rate_8        - 6.75 Gbps/Lane</div><div class='ctx'> 	DP_TEST_LINK_RATE_HBR3		= 0x1E,</div><div class='ctx'> 	DP_TEST_LINK_RATE_UHBR10	= 0x01,</div><div class='ctx'> 	DP_TEST_LINK_RATE_UHBR20	= 0x02,</div><div class='hunk'>@@ -154,6 +159,16 @@ struct dc_link_settings {</div><div class='ctx'> 	uint8_t link_rate_set;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dc_tunnel_settings {</div><div class='add'>+	bool should_enable_dp_tunneling;</div><div class='add'>+	bool should_use_dp_bw_allocation;</div><div class='add'>+	uint8_t cm_id;</div><div class='add'>+	uint8_t group_id;</div><div class='add'>+	uint32_t bw_granularity;</div><div class='add'>+	uint32_t estimated_bw;</div><div class='add'>+	uint32_t allocated_bw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union dc_dp_ffe_preset {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint8_t level		: 4;</div><div class='hunk'>@@ -295,6 +310,19 @@ union lane_align_status_updated {</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union link_service_irq_vector_esi0 {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t DP_LINK_RX_CAP_CHANGED:1;</div><div class='add'>+		uint8_t DP_LINK_STATUS_CHANGED:1;</div><div class='add'>+		uint8_t DP_LINK_STREAM_STATUS_CHANGED:1;</div><div class='add'>+		uint8_t DP_LINK_HDMI_LINK_STATUS_CHANGED:1;</div><div class='add'>+		uint8_t DP_LINK_CONNECTED_OFF_ENTRY_REQUESTED:1;</div><div class='add'>+		uint8_t DP_LINK_TUNNELING_IRQ:1;</div><div class='add'>+		uint8_t reserved:2;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union lane_adjust {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint8_t VOLTAGE_SWING_LANE:2;</div><div class='hunk'>@@ -405,14 +433,6 @@ union dwnstream_port_caps_byte3_hdmi {</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-union hdmi_sink_encoded_link_bw_support {</div><div class='del'>-	struct {</div><div class='del'>-		uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3;</div><div class='del'>-		uint8_t RESERVED:5;</div><div class='del'>-	} bits;</div><div class='del'>-	uint8_t raw;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> union hdmi_encoded_link_bw {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint8_t FRL_MODE:1; // Bit 0</div><div class='hunk'>@@ -422,7 +442,28 @@ union hdmi_encoded_link_bw {</div><div class='ctx'> 		uint8_t BW_32Gbps:1;</div><div class='ctx'> 		uint8_t BW_40Gbps:1;</div><div class='ctx'> 		uint8_t BW_48Gbps:1;</div><div class='del'>-		uint8_t RESERVED:1; // Bit 7</div><div class='add'>+		uint8_t FRL_LINK_TRAINING_FINISHED:1; // Bit 7</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union hdmi_tx_link_status {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t HDMI_TX_LINK_ACTIVE_STATUS:1;</div><div class='add'>+		uint8_t HDMI_TX_READY_STATUS:1;</div><div class='add'>+		uint8_t RESERVED:6;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union autonomous_mode_and_frl_link_status {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t FRL_LT_IN_PROGRESS_STATUS:1;</div><div class='add'>+		uint8_t FRL_LT_LINK_CONFIG_IN_PROGRESS:3;</div><div class='add'>+		uint8_t RESERVED:1;</div><div class='add'>+		uint8_t FALLBACK_POLICY:1;</div><div class='add'>+		uint8_t FALLBACK_POLICY_VALID:1;</div><div class='add'>+		uint8_t REGULATED_AUTONOMOUS_MODE_SUPPORTED:1;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='hunk'>@@ -465,8 +506,10 @@ union sink_status {</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/*6-byte structure corresponding to 6 registers (200h-205h)</div><div class='del'>-read during handling of HPD-IRQ*/</div><div class='add'>+/* 7-byte structure corresponding to 6 registers (200h-205h)</div><div class='add'>+ * and LINK_SERVICE_IRQ_ESI0 (2005h) for tunneling IRQ</div><div class='add'>+ * read during handling of HPD-IRQ</div><div class='add'>+ */</div><div class='ctx'> union hpd_irq_data {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		union sink_count sink_cnt;/* 200h */</div><div class='hunk'>@@ -474,9 +517,10 @@ union hpd_irq_data {</div><div class='ctx'> 		union lane_status lane01_status;/* 202h */</div><div class='ctx'> 		union lane_status lane23_status;/* 203h */</div><div class='ctx'> 		union lane_align_status_updated lane_status_updated;/* 204h */</div><div class='del'>-		union sink_status sink_status;</div><div class='add'>+		union sink_status sink_status;/* 205h */</div><div class='add'>+		union link_service_irq_vector_esi0 link_service_irq_esi0;/* 2005h */</div><div class='ctx'> 	} bytes;</div><div class='del'>-	uint8_t raw[6];</div><div class='add'>+	uint8_t raw[7];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union down_stream_port_count {</div><div class='hunk'>@@ -909,24 +953,34 @@ union dpia_info {</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* DPCD[0xE0020] USB4_DRIVER_BW_CAPABILITY register. */</div><div class='add'>+union usb4_driver_bw_cap {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t rsvd :7;</div><div class='add'>+		uint8_t driver_bw_alloc_support :1;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DPCD[0xE0021] DP_IN_ADAPTER_TUNNEL_INFORMATION register. */</div><div class='add'>+union dpia_tunnel_info {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t group_id :3;</div><div class='add'>+		uint8_t rsvd :5;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* DP Tunneling over USB4 */</div><div class='ctx'> struct dpcd_usb4_dp_tunneling_info {</div><div class='ctx'> 	union dp_tun_cap_support dp_tun_cap;</div><div class='ctx'> 	union dpia_info dpia_info;</div><div class='add'>+	union usb4_driver_bw_cap driver_bw_cap;</div><div class='add'>+	union dpia_tunnel_info dpia_tunnel_info;</div><div class='ctx'> 	uint8_t usb4_driver_id;</div><div class='ctx'> 	uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT</div><div class='del'>-#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT		0x0A3</div><div class='del'>-#endif</div><div class='del'>-#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0</div><div class='del'>-#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0		0X2230</div><div class='del'>-#endif</div><div class='del'>-#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256</div><div class='del'>-#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256		0X2250</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> union dp_main_line_channel_coding_cap {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint8_t DP_8b_10b_SUPPORTED	:1;</div><div class='hunk'>@@ -964,6 +1018,15 @@ union dp_128b_132b_supported_lttpr_link_rates {</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union dp_alpm_lttpr_cap {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t AUX_LESS_ALPM_SUPPORTED	:1;</div><div class='add'>+		uint8_t ASSR_SUPPORTED			:1;</div><div class='add'>+		uint8_t RESERVED			:6;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union dp_sink_video_fallback_formats {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint8_t dp_1024x768_60Hz_24bpp_support	:1;</div><div class='hunk'>@@ -974,6 +1037,29 @@ union dp_sink_video_fallback_formats {</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union dp_receive_port0_cap {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t RESERVED					:1;</div><div class='add'>+		uint8_t LOCAL_EDID_PRESENT			:1;</div><div class='add'>+		uint8_t ASSOCIATED_TO_PRECEDING_PORT:1;</div><div class='add'>+		uint8_t HBLANK_EXPANSION_CAPABLE	:1;</div><div class='add'>+		uint8_t BUFFER_SIZE_UNIT			:1;</div><div class='add'>+		uint8_t BUFFER_SIZE_PER_PORT		:1;</div><div class='add'>+		uint8_t HBLANK_REDUCTION_CAPABLE	:1;</div><div class='add'>+		uint8_t RESERVED2:1;</div><div class='add'>+		uint8_t BUFFER_SIZE:8;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union dpcd_max_uncompressed_pixel_rate_cap {</div><div class='add'>+	struct {</div><div class='add'>+		uint16_t max_uncompressed_pixel_rate_cap	:15;</div><div class='add'>+		uint16_t valid			:1;</div><div class='add'>+	} bits;</div><div class='add'>+	uint8_t raw[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union dp_fec_capability1 {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE	:1;</div><div class='hunk'>@@ -1034,10 +1120,11 @@ union dp_128b_132b_training_aux_rd_interval {</div><div class='ctx'> </div><div class='ctx'> union edp_alpm_caps {</div><div class='ctx'> 	struct {</div><div class='del'>-		uint8_t AUX_WAKE_ALPM_CAP       :1;</div><div class='del'>-		uint8_t PM_STATE_2A_SUPPORT     :1;</div><div class='del'>-		uint8_t AUX_LESS_ALPM_CAP       :1;</div><div class='del'>-		uint8_t RESERVED                :5;</div><div class='add'>+		uint8_t AUX_WAKE_ALPM_CAP                               :1;</div><div class='add'>+		uint8_t PM_STATE_2A_SUPPORT                             :1;</div><div class='add'>+		uint8_t AUX_LESS_ALPM_CAP                               :1;</div><div class='add'>+		uint8_t AUX_LESS_ALPM_ML_PHY_SLEEP_STATUS_SUPPORTED     :1;</div><div class='add'>+		uint8_t RESERVED                                        :4;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='hunk'>@@ -1070,6 +1157,16 @@ struct dprx_states {</div><div class='ctx'> 	bool cable_id_written;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union dpcd_panel_replay_capability_supported {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned char PANEL_REPLAY_SUPPORT          :1;</div><div class='add'>+		unsigned char SELECTIVE_UPDATE_SUPPORT      :1;</div><div class='add'>+		unsigned char EARLY_TRANSPORT_SUPPORT       :1;</div><div class='add'>+		unsigned char RESERVED				        :5;</div><div class='add'>+	} bits;</div><div class='add'>+	unsigned char raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum dpcd_downstream_port_max_bpc {</div><div class='ctx'> 	DOWN_STREAM_MAX_8BPC = 0,</div><div class='ctx'> 	DOWN_STREAM_MAX_10BPC,</div><div class='hunk'>@@ -1100,7 +1197,10 @@ struct dc_lttpr_caps {</div><div class='ctx'> 	uint8_t max_ext_timeout;</div><div class='ctx'> 	union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding;</div><div class='ctx'> 	union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;</div><div class='add'>+	union dp_alpm_lttpr_cap alpm;</div><div class='ctx'> 	uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];</div><div class='add'>+	uint8_t lttpr_ieee_oui[3]; // Always read from closest LTTPR to host</div><div class='add'>+	uint8_t lttpr_device_id[6]; // Always read from closest LTTPR to host</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_dongle_dfp_cap_ext {</div><div class='hunk'>@@ -1129,6 +1229,7 @@ struct dc_dongle_caps {</div><div class='ctx'> 	uint32_t dp_hdmi_max_bpc;</div><div class='ctx'> 	uint32_t dp_hdmi_max_pixel_clk_in_khz;</div><div class='ctx'> 	uint32_t dp_hdmi_frl_max_link_bw_in_kbps;</div><div class='add'>+	uint32_t dp_hdmi_regulated_autonomous_mode_support;</div><div class='ctx'> 	struct dc_dongle_dfp_cap_ext dfp_cap_ext;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1163,6 +1264,7 @@ struct dpcd_caps {</div><div class='ctx'> 	int8_t branch_dev_name[6];</div><div class='ctx'> 	int8_t branch_hw_revision;</div><div class='ctx'> 	int8_t branch_fw_revision[2];</div><div class='add'>+	int8_t branch_vendor_specific_data[4];</div><div class='ctx'> </div><div class='ctx'> 	bool allow_invalid_MSA_timing_param;</div><div class='ctx'> 	bool panel_mode_edp;</div><div class='hunk'>@@ -1175,6 +1277,7 @@ struct dpcd_caps {</div><div class='ctx'> 	struct dc_lttpr_caps lttpr_caps;</div><div class='ctx'> 	struct adaptive_sync_caps adaptive_sync_caps;</div><div class='ctx'> 	struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;</div><div class='add'>+	union dpcd_max_uncompressed_pixel_rate_cap max_uncompressed_pixel_rate_cap;</div><div class='ctx'> </div><div class='ctx'> 	union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;</div><div class='ctx'> 	union dp_main_line_channel_coding_cap channel_coding_cap;</div><div class='hunk'>@@ -1187,6 +1290,12 @@ struct dpcd_caps {</div><div class='ctx'> 	struct edp_psr_info psr_info;</div><div class='ctx'> </div><div class='ctx'> 	struct replay_info pr_info;</div><div class='add'>+	union dpcd_panel_replay_capability_supported pr_caps_supported;</div><div class='add'>+	uint16_t edp_oled_emission_rate;</div><div class='add'>+	union dp_receive_port0_cap receive_port0_cap;</div><div class='add'>+	/* Indicates the number of SST links supported by MSO (Multi-Stream Output) */</div><div class='add'>+	uint8_t mso_cap_sst_links_supported;</div><div class='add'>+	uint8_t dp_edp_general_cap_2;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union dpcd_sink_ext_caps {</div><div class='hunk'>@@ -1200,7 +1309,7 @@ union dpcd_sink_ext_caps {</div><div class='ctx'> 		uint8_t oled : 1;</div><div class='ctx'> 		uint8_t reserved_2 : 1;</div><div class='ctx'> 		uint8_t miniled : 1;</div><div class='del'>-		uint8_t reserved : 1;</div><div class='add'>+		uint8_t emission_output : 1;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint8_t raw;</div><div class='ctx'> };</div><div class='hunk'>@@ -1232,8 +1341,7 @@ union replay_enable_and_configuration {</div><div class='ctx'> 		unsigned char FREESYNC_PANEL_REPLAY_MODE              :1;</div><div class='ctx'> 		unsigned char TIMING_DESYNC_ERROR_VERIFICATION        :1;</div><div class='ctx'> 		unsigned char STATE_TRANSITION_ERROR_DETECTION        :1;</div><div class='del'>-		unsigned char RESERVED0                               :1;</div><div class='del'>-		unsigned char RESERVED1                               :4;</div><div class='add'>+		unsigned char RESERVED                                :5;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	unsigned char raw;</div><div class='ctx'> };</div><div class='hunk'>@@ -1249,11 +1357,38 @@ union dpcd_replay_configuration {</div><div class='ctx'> 	unsigned char raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union panel_replay_enable_and_configuration_1 {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned char PANEL_REPLAY_ENABLE                     :1;</div><div class='add'>+		unsigned char PANEL_REPLAY_CRC_ENABLE                 :1;</div><div class='add'>+		unsigned char IRQ_HPD_ASSDP_MISSING                   :1;</div><div class='add'>+		unsigned char IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR      :1;</div><div class='add'>+		unsigned char IRQ_HPD_RFB_ERROR                       :1;</div><div class='add'>+		unsigned char IRQ_HPD_ACTIVE_FRAME_CRC_ERROR          :1;</div><div class='add'>+		unsigned char PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE    :1;</div><div class='add'>+		unsigned char PANEL_REPLAY_EARLY_TRANSPORT_ENABLE     :1;</div><div class='add'>+	} bits;</div><div class='add'>+	unsigned char raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union panel_replay_enable_and_configuration_2 {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned char SINK_REFRESH_RATE_UNLOCK_GRANTED        :1;</div><div class='add'>+		unsigned char RESERVED                                :1;</div><div class='add'>+		unsigned char SU_Y_GRANULARITY_EXT_VALUE_ENABLED      :1;</div><div class='add'>+		unsigned char SU_Y_GRANULARITY_EXT_VALUE              :4;</div><div class='add'>+		unsigned char SU_REGION_SCAN_LINE_CAPTURE_INDICATION  :1;</div><div class='add'>+	} bits;</div><div class='add'>+	unsigned char raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union dpcd_alpm_configuration {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		unsigned char ENABLE                    : 1;</div><div class='ctx'> 		unsigned char IRQ_HPD_ENABLE            : 1;</div><div class='del'>-		unsigned char RESERVED                  : 6;</div><div class='add'>+		unsigned char ALPM_MODE_SEL             : 1;</div><div class='add'>+		unsigned char ACDS_PERIOD_DURATION      : 1;</div><div class='add'>+		unsigned char RESERVED                  : 4;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	unsigned char raw;</div><div class='ctx'> };</div><div class='hunk'>@@ -1346,12 +1481,30 @@ struct dp_trace {</div><div class='ctx'> #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX</div><div class='ctx'> #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX		0x110</div><div class='ctx'> #endif</div><div class='add'>+#ifndef DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP</div><div class='add'>+#define DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP    0x221c</div><div class='add'>+#endif</div><div class='add'>+#ifndef DP_LTTPR_ALPM_CAPABILITIES</div><div class='add'>+#define DP_LTTPR_ALPM_CAPABILITIES              0xF0009</div><div class='add'>+#endif</div><div class='add'>+#ifndef DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS</div><div class='add'>+#define DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS	0x303C</div><div class='add'>+#endif</div><div class='ctx'> #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE</div><div class='ctx'> #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE	0x50</div><div class='ctx'> #endif</div><div class='ctx'> #ifndef DP_TUNNELING_IRQ</div><div class='ctx'> #define DP_TUNNELING_IRQ				(1 &lt;&lt; 5)</div><div class='ctx'> #endif</div><div class='add'>+#ifndef DP_BRANCH_VENDOR_SPECIFIC_START</div><div class='add'>+#define DP_BRANCH_VENDOR_SPECIFIC_START     0x50C</div><div class='add'>+#endif</div><div class='add'>+#ifndef DP_LTTPR_IEEE_OUI</div><div class='add'>+#define DP_LTTPR_IEEE_OUI 0xF003D</div><div class='add'>+#endif</div><div class='add'>+#ifndef DP_LTTPR_DEVICE_ID</div><div class='add'>+#define DP_LTTPR_DEVICE_ID 0xF0040</div><div class='add'>+#endif</div><div class='ctx'> /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/</div><div class='ctx'> #ifndef DP_TUNNELING_CAPABILITIES</div><div class='ctx'> #define DP_TUNNELING_CAPABILITIES			0xE000D /* 1.4a */</div><div class='hunk'>@@ -1389,4 +1542,26 @@ struct dp_trace {</div><div class='ctx'> #ifndef REQUESTED_BW</div><div class='ctx'> #define REQUESTED_BW					0xE0031 /* 1.4a */</div><div class='ctx'> #endif</div><div class='add'>+# ifndef DP_TUNNELING_BW_ALLOC_BITS_MASK</div><div class='add'>+# define DP_TUNNELING_BW_ALLOC_BITS_MASK		(0x0F &lt;&lt; 0)</div><div class='add'>+# endif</div><div class='add'>+# ifndef DP_TUNNELING_BW_REQUEST_FAILED</div><div class='add'>+# define DP_TUNNELING_BW_REQUEST_FAILED			(1 &lt;&lt; 0)</div><div class='add'>+# endif</div><div class='add'>+# ifndef DP_TUNNELING_BW_REQUEST_SUCCEEDED</div><div class='add'>+# define DP_TUNNELING_BW_REQUEST_SUCCEEDED		(1 &lt;&lt; 1)</div><div class='add'>+# endif</div><div class='add'>+# ifndef DP_TUNNELING_ESTIMATED_BW_CHANGED</div><div class='add'>+# define DP_TUNNELING_ESTIMATED_BW_CHANGED		(1 &lt;&lt; 2)</div><div class='add'>+# endif</div><div class='add'>+# ifndef DP_TUNNELING_BW_ALLOC_CAP_CHANGED</div><div class='add'>+# define DP_TUNNELING_BW_ALLOC_CAP_CHANGED		(1 &lt;&lt; 3)</div><div class='add'>+# endif</div><div class='add'>+# ifndef DPTX_BW_ALLOC_UNMASK_IRQ</div><div class='add'>+# define DPTX_BW_ALLOC_UNMASK_IRQ			(1 &lt;&lt; 6)</div><div class='add'>+# endif</div><div class='add'>+# ifndef DPTX_BW_ALLOC_MODE_ENABLE</div><div class='add'>+# define DPTX_BW_ALLOC_MODE_ENABLE			(1 &lt;&lt; 7)</div><div class='add'>+# endif</div><div class='add'>+</div><div class='ctx'> #endif /* DC_DP_TYPES_H */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h<br/>index fe3078b8789e..9d18f1c08079 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dsc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_dsc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_dsc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_dsc.h</a></div><div class='hunk'>@@ -59,6 +59,7 @@ struct dc_dsc_config_options {</div><div class='ctx'> 	uint32_t max_target_bpp_limit_override_x16;</div><div class='ctx'> 	uint32_t slice_height_granularity;</div><div class='ctx'> 	uint32_t dsc_force_odm_hslice_override;</div><div class='add'>+	bool force_dsc_when_not_needed;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,</div><div class='hunk'>@@ -93,6 +94,11 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(</div><div class='ctx'> 		const int num_slices_h,</div><div class='ctx'> 		const bool is_dp);</div><div class='ctx'> </div><div class='add'>+void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,</div><div class='add'>+			      const struct dsc_dec_dpcd_caps *dsc_sink_caps);</div><div class='add'>+void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,</div><div class='add'>+			      const struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='ctx'> /* TODO - Hardware/specs limitation should be owned by dc dsc and returned to DM,</div><div class='ctx'>  * and DM can choose to OVERRIDE the limitation on CASE BY CASE basis.</div><div class='ctx'>  * Hardware/specs limitation should not be writable by DM.</div><div class='hunk'>@@ -100,7 +106,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(</div><div class='ctx'>  */</div><div class='ctx'> void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,</div><div class='ctx'> 		uint32_t max_target_bpp_limit_override_x16,</div><div class='del'>-		struct dc_dsc_policy *policy);</div><div class='add'>+		struct dc_dsc_policy *policy,</div><div class='add'>+		const enum dc_link_encoding_format link_encoding);</div><div class='ctx'> </div><div class='ctx'> void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c<br/>new file mode 100644<br/>index 000000000000..fee69642fb93<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_fused_io.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_fused_io.c</a></div><div class='hunk'>@@ -0,0 +1,148 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dc_fused_io.h"</div><div class='add'>+</div><div class='add'>+#include "dm_helpers.h"</div><div class='add'>+#include "gpio.h"</div><div class='add'>+</div><div class='add'>+static bool op_i2c_convert(</div><div class='add'>+		union dmub_rb_cmd *cmd,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *op,</div><div class='add'>+		enum dmub_cmd_fused_request_type type,</div><div class='add'>+		uint32_t ddc_line,</div><div class='add'>+		bool over_aux</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dmub_cmd_fused_request *req = &amp;cmd-&gt;fused_io.request;</div><div class='add'>+	struct dmub_cmd_fused_request_location_i2c *loc = &amp;req-&gt;u.i2c;</div><div class='add'>+</div><div class='add'>+	if (!op || op-&gt;size &gt; sizeof(req-&gt;buffer))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	req-&gt;type = type;</div><div class='add'>+	loc-&gt;is_aux = false;</div><div class='add'>+	loc-&gt;ddc_line = ddc_line;</div><div class='add'>+	loc-&gt;over_aux = over_aux;</div><div class='add'>+	loc-&gt;address = op-&gt;address;</div><div class='add'>+	loc-&gt;offset = op-&gt;offset;</div><div class='add'>+	loc-&gt;length = op-&gt;size;</div><div class='add'>+	memcpy(req-&gt;buffer, op-&gt;data, op-&gt;size);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool op_aux_convert(</div><div class='add'>+		union dmub_rb_cmd *cmd,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *op,</div><div class='add'>+		enum dmub_cmd_fused_request_type type,</div><div class='add'>+		uint32_t ddc_line</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	struct dmub_cmd_fused_request *req = &amp;cmd-&gt;fused_io.request;</div><div class='add'>+	struct dmub_cmd_fused_request_location_aux *loc = &amp;req-&gt;u.aux;</div><div class='add'>+</div><div class='add'>+	if (!op || op-&gt;size &gt; sizeof(req-&gt;buffer))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	req-&gt;type = type;</div><div class='add'>+	loc-&gt;is_aux = true;</div><div class='add'>+	loc-&gt;ddc_line = ddc_line;</div><div class='add'>+	loc-&gt;address = op-&gt;address;</div><div class='add'>+	loc-&gt;length = op-&gt;size;</div><div class='add'>+	memcpy(req-&gt;buffer, op-&gt;data, op-&gt;size);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool atomic_write_poll_read(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		union dmub_rb_cmd commands[3],</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	const uint8_t count = 3;</div><div class='add'>+	const uint32_t timeout_per_request_us = 10000;</div><div class='add'>+	const uint32_t timeout_per_aux_transaction_us = 10000;</div><div class='add'>+	uint64_t timeout_us = 0;</div><div class='add'>+</div><div class='add'>+	commands[1].fused_io.request.poll_mask_msb = poll_mask_msb;</div><div class='add'>+	commands[1].fused_io.request.timeout_us = poll_timeout_us;</div><div class='add'>+</div><div class='add'>+	for (uint8_t i = 0; i &lt; count; i++) {</div><div class='add'>+		struct dmub_rb_cmd_fused_io *io = &amp;commands[i].fused_io;</div><div class='add'>+</div><div class='add'>+		io-&gt;header.type = DMUB_CMD__FUSED_IO;</div><div class='add'>+		io-&gt;header.sub_type = DMUB_CMD__FUSED_IO_EXECUTE;</div><div class='add'>+		io-&gt;header.multi_cmd_pending = i != count - 1;</div><div class='add'>+		io-&gt;header.payload_bytes = sizeof(commands[i].fused_io) - sizeof(io-&gt;header);</div><div class='add'>+</div><div class='add'>+		timeout_us += timeout_per_request_us + io-&gt;request.timeout_us;</div><div class='add'>+		if (!io-&gt;request.timeout_us &amp;&amp; io-&gt;request.u.aux.is_aux)</div><div class='add'>+			timeout_us += timeout_per_aux_transaction_us * (io-&gt;request.u.aux.length / 16);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dm_helpers_execute_fused_io(link-&gt;ctx, link, commands, count, timeout_us))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return commands[0].fused_io.request.status == FUSED_REQUEST_STATUS_SUCCESS;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dm_atomic_write_poll_read_i2c(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *write,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *poll,</div><div class='add'>+		struct mod_hdcp_atomic_op_i2c *read,</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	if (!link)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	const bool over_aux = false;</div><div class='add'>+	const uint32_t ddc_line = link-&gt;ddc-&gt;ddc_pin-&gt;pin_data-&gt;en;</div><div class='add'>+</div><div class='add'>+	union dmub_rb_cmd commands[3] = { 0 };</div><div class='add'>+	const bool converted = op_i2c_convert(&amp;commands[0], write, FUSED_REQUEST_WRITE, ddc_line, over_aux)</div><div class='add'>+			&amp;&amp; op_i2c_convert(&amp;commands[1], poll, FUSED_REQUEST_POLL, ddc_line, over_aux)</div><div class='add'>+			&amp;&amp; op_i2c_convert(&amp;commands[2], read, FUSED_REQUEST_READ, ddc_line, over_aux);</div><div class='add'>+</div><div class='add'>+	if (!converted)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	const bool result = atomic_write_poll_read(link, commands, poll_timeout_us, poll_mask_msb);</div><div class='add'>+</div><div class='add'>+	memcpy(read-&gt;data, commands[0].fused_io.request.buffer, read-&gt;size);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dm_atomic_write_poll_read_aux(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *write,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *poll,</div><div class='add'>+		struct mod_hdcp_atomic_op_aux *read,</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+)</div><div class='add'>+{</div><div class='add'>+	if (!link)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	const uint32_t ddc_line = link-&gt;ddc-&gt;ddc_pin-&gt;pin_data-&gt;en;</div><div class='add'>+	union dmub_rb_cmd commands[3] = { 0 };</div><div class='add'>+	const bool converted = op_aux_convert(&amp;commands[0], write, FUSED_REQUEST_WRITE, ddc_line)</div><div class='add'>+			&amp;&amp; op_aux_convert(&amp;commands[1], poll, FUSED_REQUEST_POLL, ddc_line)</div><div class='add'>+			&amp;&amp; op_aux_convert(&amp;commands[2], read, FUSED_REQUEST_READ, ddc_line);</div><div class='add'>+</div><div class='add'>+	if (!converted)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	const bool result = atomic_write_poll_read(link, commands, poll_timeout_us, poll_mask_msb);</div><div class='add'>+</div><div class='add'>+	memcpy(read-&gt;data, commands[0].fused_io.request.buffer, read-&gt;size);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.h b/drivers/gpu/drm/amd/display/dc/dc_fused_io.h<br/>new file mode 100644<br/>index 000000000000..c74917240985<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_fused_io.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_fused_io.h</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_FUSED_IO_H__</div><div class='add'>+#define __DC_FUSED_IO_H__</div><div class='add'>+</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "mod_hdcp.h"</div><div class='add'>+</div><div class='add'>+bool dm_atomic_write_poll_read_i2c(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *write,</div><div class='add'>+		const struct mod_hdcp_atomic_op_i2c *poll,</div><div class='add'>+		struct mod_hdcp_atomic_op_i2c *read,</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+bool dm_atomic_write_poll_read_aux(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *write,</div><div class='add'>+		const struct mod_hdcp_atomic_op_aux *poll,</div><div class='add'>+		struct mod_hdcp_atomic_op_aux *read,</div><div class='add'>+		uint32_t poll_timeout_us,</div><div class='add'>+		uint8_t poll_mask_msb</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+#endif  // __DC_FUSED_IO_H__</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c<br/>index 8f9a67825615..5a365bd19933 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_helper.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_helper.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_helper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_helper.c</a></div><div class='hunk'>@@ -91,11 +91,6 @@ struct dc_reg_value_masks {</div><div class='ctx'> 	uint32_t mask;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dc_reg_sequence {</div><div class='del'>-	uint32_t addr;</div><div class='del'>-	struct dc_reg_value_masks value_masks;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static inline void set_reg_field_value_masks(</div><div class='ctx'> 	struct dc_reg_value_masks *field_value_mask,</div><div class='ctx'> 	uint32_t value,</div><div class='hunk'>@@ -266,7 +261,6 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,</div><div class='ctx'> </div><div class='ctx'> 	va_end(ap);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	/* mmio write directly */</div><div class='ctx'> 	reg_val = (reg_val &amp; ~field_value_mask.mask) | field_value_mask.value;</div><div class='ctx'> </div><div class='hunk'>@@ -688,13 +682,19 @@ void reg_sequence_wait_done(const struct dc_context *ctx)</div><div class='ctx'> 	if (offload &amp;&amp;</div><div class='ctx'> 	    ctx-&gt;dc-&gt;debug.dmub_offload_enabled &amp;&amp;</div><div class='ctx'> 	    !ctx-&gt;dc-&gt;debug.dmcub_emulation) {</div><div class='del'>-		dc_dmub_srv_wait_idle(ctx-&gt;dmub_srv);</div><div class='add'>+		dc_dmub_srv_wait_for_idle(ctx-&gt;dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> char *dce_version_to_string(const int version)</div><div class='ctx'> {</div><div class='ctx'> 	switch (version) {</div><div class='add'>+	case DCE_VERSION_6_0:</div><div class='add'>+		return "DCE 6.0";</div><div class='add'>+	case DCE_VERSION_6_1:</div><div class='add'>+		return "DCE 6.1";</div><div class='add'>+	case DCE_VERSION_6_4:</div><div class='add'>+		return "DCE 6.4";</div><div class='ctx'> 	case DCE_VERSION_8_0:</div><div class='ctx'> 		return "DCE 8.0";</div><div class='ctx'> 	case DCE_VERSION_8_1:</div><div class='hunk'>@@ -732,7 +732,7 @@ char *dce_version_to_string(const int version)</div><div class='ctx'> 	case DCN_VERSION_3_03:</div><div class='ctx'> 		return "DCN 3.0.3";</div><div class='ctx'> 	case DCN_VERSION_3_1:</div><div class='del'>-		return "DCN 3.1";</div><div class='add'>+		return "DCN 3.1.2";</div><div class='ctx'> 	case DCN_VERSION_3_14:</div><div class='ctx'> 		return "DCN 3.1.4";</div><div class='ctx'> 	case DCN_VERSION_3_15:</div><div class='hunk'>@@ -747,7 +747,16 @@ char *dce_version_to_string(const int version)</div><div class='ctx'> 		return "DCN 3.5";</div><div class='ctx'> 	case DCN_VERSION_3_51:</div><div class='ctx'> 		return "DCN 3.5.1";</div><div class='add'>+	case DCN_VERSION_3_6:</div><div class='add'>+		return "DCN 3.6";</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		return "DCN 4.0.1";</div><div class='ctx'> 	default:</div><div class='ctx'> 		return "Unknown";</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool dc_supports_vrr(const enum dce_version v)</div><div class='add'>+{</div><div class='add'>+	return v &gt;= DCE_VERSION_8_0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h<br/>index aae2f3a2660d..667852517246 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_hw_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_hw_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_hw_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_hw_types.h</a></div><div class='hunk'>@@ -60,6 +60,7 @@ union large_integer {</div><div class='ctx'> </div><div class='ctx'> enum dc_plane_addr_type {</div><div class='ctx'> 	PLN_ADDR_TYPE_GRAPHICS = 0,</div><div class='add'>+	PLN_ADDR_TYPE_3DLUT,</div><div class='ctx'> 	PLN_ADDR_TYPE_GRPH_STEREO,</div><div class='ctx'> 	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,</div><div class='ctx'> 	PLN_ADDR_TYPE_RGBEA</div><div class='hunk'>@@ -67,7 +68,7 @@ enum dc_plane_addr_type {</div><div class='ctx'> </div><div class='ctx'> struct dc_plane_address {</div><div class='ctx'> 	enum dc_plane_addr_type type;</div><div class='del'>-	bool tmz_surface;</div><div class='add'>+	uint8_t tmz_surface;</div><div class='ctx'> 	union {</div><div class='ctx'> 		struct{</div><div class='ctx'> 			PHYSICAL_ADDRESS_LOC addr;</div><div class='hunk'>@@ -76,6 +77,10 @@ struct dc_plane_address {</div><div class='ctx'> 			union large_integer dcc_const_color;</div><div class='ctx'> 		} grph;</div><div class='ctx'> </div><div class='add'>+		struct {</div><div class='add'>+			PHYSICAL_ADDRESS_LOC addr;</div><div class='add'>+		} lut3d;</div><div class='add'>+</div><div class='ctx'> 		/*stereo*/</div><div class='ctx'> 		struct {</div><div class='ctx'> 			PHYSICAL_ADDRESS_LOC left_addr;</div><div class='hunk'>@@ -93,7 +98,6 @@ struct dc_plane_address {</div><div class='ctx'> 			PHYSICAL_ADDRESS_LOC right_alpha_addr;</div><div class='ctx'> 			PHYSICAL_ADDRESS_LOC right_alpha_meta_addr;</div><div class='ctx'> 			union large_integer right_alpha_dcc_const_color;</div><div class='del'>-</div><div class='ctx'> 		} grph_stereo;</div><div class='ctx'> </div><div class='ctx'> 		/*video  progressive*/</div><div class='hunk'>@@ -263,6 +267,9 @@ enum tripleBuffer_enable {</div><div class='ctx'> 	DC_TRIPLEBUFFER_DISABLE = 0x0,</div><div class='ctx'> 	DC_TRIPLEBUFFER_ENABLE = 0x1,</div><div class='ctx'> };</div><div class='add'>+enum tile_split_values_new {</div><div class='add'>+	DC_SURF_TILE_SPLIT_1KB = 0x4,</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> /* TODO: These values come from hardware spec. We need to readdress this</div><div class='ctx'>  * if they ever change.</div><div class='hunk'>@@ -320,86 +327,115 @@ enum swizzle_mode_values {</div><div class='ctx'> 	DC_SW_UNKNOWN = DC_SW_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-union dc_tiling_info {</div><div class='del'>-</div><div class='del'>-	struct {</div><div class='del'>-		/* Specifies the number of memory banks for tiling</div><div class='del'>-		 *	purposes.</div><div class='del'>-		 * Only applies to 2D and 3D tiling modes.</div><div class='del'>-		 *	POSSIBLE VALUES: 2,4,8,16</div><div class='del'>-		 */</div><div class='del'>-		unsigned int num_banks;</div><div class='del'>-		/* Specifies the number of tiles in the x direction</div><div class='del'>-		 *	to be incorporated into the same bank.</div><div class='del'>-		 * Only applies to 2D and 3D tiling modes.</div><div class='del'>-		 *	POSSIBLE VALUES: 1,2,4,8</div><div class='del'>-		 */</div><div class='del'>-		unsigned int bank_width;</div><div class='del'>-		unsigned int bank_width_c;</div><div class='del'>-		/* Specifies the number of tiles in the y direction to</div><div class='del'>-		 *	be incorporated into the same bank.</div><div class='del'>-		 * Only applies to 2D and 3D tiling modes.</div><div class='del'>-		 *	POSSIBLE VALUES: 1,2,4,8</div><div class='del'>-		 */</div><div class='del'>-		unsigned int bank_height;</div><div class='del'>-		unsigned int bank_height_c;</div><div class='del'>-		/* Specifies the macro tile aspect ratio. Only applies</div><div class='del'>-		 * to 2D and 3D tiling modes.</div><div class='del'>-		 */</div><div class='del'>-		unsigned int tile_aspect;</div><div class='del'>-		unsigned int tile_aspect_c;</div><div class='del'>-		/* Specifies the number of bytes that will be stored</div><div class='del'>-		 *	contiguously for each tile.</div><div class='del'>-		 * If the tile data requires more storage than this</div><div class='del'>-		 *	amount, it is split into multiple slices.</div><div class='del'>-		 * This field must not be larger than</div><div class='del'>-		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.</div><div class='del'>-		 * Only applies to 2D and 3D tiling modes.</div><div class='del'>-		 * For color render targets, TILE_SPLIT &gt;= 256B.</div><div class='del'>-		 */</div><div class='del'>-		enum tile_split_values tile_split;</div><div class='del'>-		enum tile_split_values tile_split_c;</div><div class='del'>-		/* Specifies the addressing within a tile.</div><div class='del'>-		 *	0x0 - DISPLAY_MICRO_TILING</div><div class='del'>-		 *	0x1 - THIN_MICRO_TILING</div><div class='del'>-		 *	0x2 - DEPTH_MICRO_TILING</div><div class='del'>-		 *	0x3 - ROTATED_MICRO_TILING</div><div class='del'>-		 */</div><div class='del'>-		enum tile_mode_values tile_mode;</div><div class='del'>-		enum tile_mode_values tile_mode_c;</div><div class='del'>-		/* Specifies the number of pipes and how they are</div><div class='del'>-		 *	interleaved in the surface.</div><div class='del'>-		 * Refer to memory addressing document for complete</div><div class='del'>-		 *	details and constraints.</div><div class='del'>-		 */</div><div class='del'>-		unsigned int pipe_config;</div><div class='del'>-		/* Specifies the tiling mode of the surface.</div><div class='del'>-		 * THIN tiles use an 8x8x1 tile size.</div><div class='del'>-		 * THICK tiles use an 8x8x4 tile size.</div><div class='del'>-		 * 2D tiling modes rotate banks for successive Z slices</div><div class='del'>-		 * 3D tiling modes rotate pipes and banks for Z slices</div><div class='del'>-		 * Refer to memory addressing document for complete</div><div class='del'>-		 *	details and constraints.</div><div class='del'>-		 */</div><div class='del'>-		enum array_mode_values array_mode;</div><div class='del'>-	} gfx8;</div><div class='del'>-</div><div class='del'>-	struct {</div><div class='del'>-		enum swizzle_mode_values swizzle;</div><div class='del'>-		unsigned int num_pipes;</div><div class='del'>-		unsigned int max_compressed_frags;</div><div class='del'>-		unsigned int pipe_interleave;</div><div class='del'>-</div><div class='del'>-		unsigned int num_banks;</div><div class='del'>-		unsigned int num_shader_engines;</div><div class='del'>-		unsigned int num_rb_per_se;</div><div class='del'>-		bool shaderEnable;</div><div class='add'>+// Definition of swizzle modes with addr3 ASICs</div><div class='add'>+enum swizzle_mode_addr3_values {</div><div class='add'>+	DC_ADDR3_SW_LINEAR = 0,</div><div class='add'>+	DC_ADDR3_SW_256B_2D = 1,</div><div class='add'>+	DC_ADDR3_SW_4KB_2D = 2,</div><div class='add'>+	DC_ADDR3_SW_64KB_2D = 3,</div><div class='add'>+	DC_ADDR3_SW_256KB_2D = 4,</div><div class='add'>+	DC_ADDR3_SW_4KB_3D = 5,</div><div class='add'>+	DC_ADDR3_SW_64KB_3D = 6,</div><div class='add'>+	DC_ADDR3_SW_256KB_3D = 7,</div><div class='add'>+	DC_ADDR3_SW_MAX = 8,</div><div class='add'>+	DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_gfxversion {</div><div class='add'>+	DcGfxVersion7 = 0,</div><div class='add'>+	DcGfxVersion8,</div><div class='add'>+	DcGfxVersion9,</div><div class='add'>+	DcGfxVersion10,</div><div class='add'>+	DcGfxVersion11,</div><div class='add'>+	DcGfxAddr3,</div><div class='add'>+	DcGfxVersionUnknown</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+ struct dc_tiling_info {</div><div class='add'>+	unsigned int gfxversion;     // Specifies which part of the union to use. Must use DalGfxVersion enum</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			/* Specifies the number of memory banks for tiling</div><div class='add'>+			 *	purposes.</div><div class='add'>+			 * Only applies to 2D and 3D tiling modes.</div><div class='add'>+			 *	POSSIBLE VALUES: 2,4,8,16</div><div class='add'>+			 */</div><div class='add'>+			unsigned int num_banks;</div><div class='add'>+			/* Specifies the number of tiles in the x direction</div><div class='add'>+			 *	to be incorporated into the same bank.</div><div class='add'>+			 * Only applies to 2D and 3D tiling modes.</div><div class='add'>+			 *	POSSIBLE VALUES: 1,2,4,8</div><div class='add'>+			 */</div><div class='add'>+			unsigned int bank_width;</div><div class='add'>+			unsigned int bank_width_c;</div><div class='add'>+			/* Specifies the number of tiles in the y direction to</div><div class='add'>+			 *	be incorporated into the same bank.</div><div class='add'>+			 * Only applies to 2D and 3D tiling modes.</div><div class='add'>+			 *	POSSIBLE VALUES: 1,2,4,8</div><div class='add'>+			 */</div><div class='add'>+			unsigned int bank_height;</div><div class='add'>+			unsigned int bank_height_c;</div><div class='add'>+			/* Specifies the macro tile aspect ratio. Only applies</div><div class='add'>+			 * to 2D and 3D tiling modes.</div><div class='add'>+			 */</div><div class='add'>+			unsigned int tile_aspect;</div><div class='add'>+			unsigned int tile_aspect_c;</div><div class='add'>+			/* Specifies the number of bytes that will be stored</div><div class='add'>+			 *	contiguously for each tile.</div><div class='add'>+			 * If the tile data requires more storage than this</div><div class='add'>+			 *	amount, it is split into multiple slices.</div><div class='add'>+			 * This field must not be larger than</div><div class='add'>+			 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.</div><div class='add'>+			 * Only applies to 2D and 3D tiling modes.</div><div class='add'>+			 * For color render targets, TILE_SPLIT &gt;= 256B.</div><div class='add'>+			 */</div><div class='add'>+			enum tile_split_values tile_split;</div><div class='add'>+			enum tile_split_values tile_split_c;</div><div class='add'>+			/* Specifies the addressing within a tile.</div><div class='add'>+			 *	0x0 - DISPLAY_MICRO_TILING</div><div class='add'>+			 *	0x1 - THIN_MICRO_TILING</div><div class='add'>+			 *	0x2 - DEPTH_MICRO_TILING</div><div class='add'>+			 *	0x3 - ROTATED_MICRO_TILING</div><div class='add'>+			 */</div><div class='add'>+			enum tile_mode_values tile_mode;</div><div class='add'>+			enum tile_mode_values tile_mode_c;</div><div class='add'>+			/* Specifies the number of pipes and how they are</div><div class='add'>+			 *	interleaved in the surface.</div><div class='add'>+			 * Refer to memory addressing document for complete</div><div class='add'>+			 *	details and constraints.</div><div class='add'>+			 */</div><div class='add'>+			unsigned int pipe_config;</div><div class='add'>+			/* Specifies the tiling mode of the surface.</div><div class='add'>+			 * THIN tiles use an 8x8x1 tile size.</div><div class='add'>+			 * THICK tiles use an 8x8x4 tile size.</div><div class='add'>+			 * 2D tiling modes rotate banks for successive Z slices</div><div class='add'>+			 * 3D tiling modes rotate pipes and banks for Z slices</div><div class='add'>+			 * Refer to memory addressing document for complete</div><div class='add'>+			 *	details and constraints.</div><div class='add'>+			 */</div><div class='add'>+			enum array_mode_values array_mode;</div><div class='add'>+		} gfx8;</div><div class='ctx'> </div><div class='del'>-		bool meta_linear;</div><div class='del'>-		bool rb_aligned;</div><div class='del'>-		bool pipe_aligned;</div><div class='del'>-		unsigned int num_pkrs;</div><div class='del'>-	} gfx9;</div><div class='add'>+		struct {</div><div class='add'>+			enum swizzle_mode_values swizzle;</div><div class='add'>+			unsigned int num_pipes;</div><div class='add'>+			unsigned int max_compressed_frags;</div><div class='add'>+			unsigned int pipe_interleave;</div><div class='add'>+</div><div class='add'>+			unsigned int num_banks;</div><div class='add'>+			unsigned int num_shader_engines;</div><div class='add'>+			unsigned int num_rb_per_se;</div><div class='add'>+			bool shaderEnable;</div><div class='add'>+</div><div class='add'>+			bool meta_linear;</div><div class='add'>+			bool rb_aligned;</div><div class='add'>+			bool pipe_aligned;</div><div class='add'>+			unsigned int num_pkrs;</div><div class='add'>+		} gfx9;/*gfx9, gfx10 and above*/</div><div class='add'>+		struct {</div><div class='add'>+			enum swizzle_mode_addr3_values swizzle;</div><div class='add'>+		} gfx_addr3;/*gfx with addr3 and above*/</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Rotation angle */</div><div class='hunk'>@@ -461,6 +497,7 @@ struct dc_cursor_mi_param {</div><div class='ctx'> 	unsigned int pixel_clk_khz;</div><div class='ctx'> 	unsigned int ref_clk_khz;</div><div class='ctx'> 	struct rect viewport;</div><div class='add'>+	struct rect recout;</div><div class='ctx'> 	struct fixed31_32 h_scale_ratio;</div><div class='ctx'> 	struct fixed31_32 v_scale_ratio;</div><div class='ctx'> 	enum dc_rotation_angle rotation;</div><div class='hunk'>@@ -616,7 +653,8 @@ enum dc_color_space {</div><div class='ctx'> 	COLOR_SPACE_YCBCR709_LIMITED,</div><div class='ctx'> 	COLOR_SPACE_2020_RGB_FULLRANGE,</div><div class='ctx'> 	COLOR_SPACE_2020_RGB_LIMITEDRANGE,</div><div class='del'>-	COLOR_SPACE_2020_YCBCR,</div><div class='add'>+	COLOR_SPACE_2020_YCBCR_LIMITED,</div><div class='add'>+	COLOR_SPACE_2020_YCBCR_FULL,</div><div class='ctx'> 	COLOR_SPACE_ADOBERGB,</div><div class='ctx'> 	COLOR_SPACE_DCIP3,</div><div class='ctx'> 	COLOR_SPACE_DISPLAYNATIVE,</div><div class='hunk'>@@ -624,6 +662,7 @@ enum dc_color_space {</div><div class='ctx'> 	COLOR_SPACE_APPCTRL,</div><div class='ctx'> 	COLOR_SPACE_CUSTOMPOINTS,</div><div class='ctx'> 	COLOR_SPACE_YCBCR709_BLACK,</div><div class='add'>+	COLOR_SPACE_2020_YCBCR = COLOR_SPACE_2020_YCBCR_LIMITED,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum dc_dither_option {</div><div class='hunk'>@@ -935,6 +974,7 @@ struct dc_crtc_timing {</div><div class='ctx'> 	uint32_t pix_clk_100hz;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t min_refresh_in_uhz;</div><div class='add'>+	uint32_t max_refresh_in_uhz;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t vic;</div><div class='ctx'> 	uint32_t hdmi_vic;</div><div class='hunk'>@@ -950,6 +990,9 @@ struct dc_crtc_timing {</div><div class='ctx'> 	struct dc_crtc_timing_flags flags;</div><div class='ctx'> 	uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -&gt; 8bpp) */</div><div class='ctx'> 	struct dc_dsc_config dsc_cfg;</div><div class='add'>+</div><div class='add'>+	/* The number of pixels that HBlank has been expanded by from the original EDID timing. */</div><div class='add'>+	uint32_t expanded_hblank;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum trigger_delay {</div><div class='hunk'>@@ -974,6 +1017,8 @@ struct dc_crtc_timing_adjust {</div><div class='ctx'> 	uint32_t v_total_max;</div><div class='ctx'> 	uint32_t v_total_mid;</div><div class='ctx'> 	uint32_t v_total_mid_frame_num;</div><div class='add'>+	uint32_t allow_otg_v_count_halt;</div><div class='add'>+	uint8_t timing_adjust_pending;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -1050,6 +1095,25 @@ enum cm_gamut_coef_format {</div><div class='ctx'> 	CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum mpcc_gamut_remap_mode_select {</div><div class='add'>+	MPCC_GAMUT_REMAP_MODE_SELECT_0 = 0,</div><div class='add'>+	MPCC_GAMUT_REMAP_MODE_SELECT_1,</div><div class='add'>+	MPCC_GAMUT_REMAP_MODE_SELECT_2</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum mpcc_gamut_remap_id {</div><div class='add'>+	MPCC_OGAM_GAMUT_REMAP,</div><div class='add'>+	MPCC_MCM_FIRST_GAMUT_REMAP,</div><div class='add'>+	MPCC_MCM_SECOND_GAMUT_REMAP,</div><div class='add'>+	MPCC_RMCM_GAMUT_REMAP,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum cursor_matrix_mode {</div><div class='add'>+	CUR_MATRIX_BYPASS = 0,</div><div class='add'>+	CUR_MATRIX_SET_A,</div><div class='add'>+	CUR_MATRIX_SET_B</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mcif_warmup_params {</div><div class='ctx'> 	union large_integer	start_address;</div><div class='ctx'> 	unsigned int		address_increment;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/dc_plane.h<br/>index ef380cae816a..14feb843e694 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_plane.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_plane.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_plane.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_plane.h</a></div><div class='hunk'>@@ -26,13 +26,26 @@</div><div class='ctx'> #ifndef _DC_PLANE_H_</div><div class='ctx'> #define _DC_PLANE_H_</div><div class='ctx'> </div><div class='del'>-#include "dc.h"</div><div class='ctx'> #include "dc_hw_types.h"</div><div class='ctx'> </div><div class='del'>-struct dc_plane_state *dc_create_plane_state(struct dc *dc);</div><div class='add'>+union dc_plane_status_update_flags {</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t address : 1;</div><div class='add'>+	} bits;</div><div class='add'>+	uint32_t raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_plane_state *dc_create_plane_state(const struct dc *dc);</div><div class='ctx'> const struct dc_plane_status *dc_plane_get_status(</div><div class='del'>-		const struct dc_plane_state *plane_state);</div><div class='add'>+		const struct dc_plane_state *plane_state,</div><div class='add'>+		union dc_plane_status_update_flags flags);</div><div class='ctx'> void dc_plane_state_retain(struct dc_plane_state *plane_state);</div><div class='ctx'> void dc_plane_state_release(struct dc_plane_state *plane_state);</div><div class='ctx'> </div><div class='add'>+void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,</div><div class='add'>+					   bool clear_tiling);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dc_plane_copy_config(struct dc_plane_state *dst, const struct dc_plane_state *src);</div><div class='add'>+</div><div class='ctx'> #endif /* _DC_PLANE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h b/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h<br/>index 9ee184c1df00..ab13335f1d01 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_plane_priv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_plane_priv.h</a></div><div class='hunk'>@@ -30,5 +30,6 @@</div><div class='ctx'> </div><div class='ctx'> void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state);</div><div class='ctx'> void dc_plane_destruct(struct dc_plane_state *plane_state);</div><div class='add'>+uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);</div><div class='ctx'> </div><div class='ctx'> #endif /* _DC_PLANE_PRIV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c<br/>new file mode 100644<br/>index 000000000000..37d1a79e8241<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_spl_translate.c</a></div><div class='hunk'>@@ -0,0 +1,231 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dc_spl_translate.h"</div><div class='add'>+#include "dcn20/dcn20_dpp.h"</div><div class='add'>+#include "dcn32/dcn32_dpp.h"</div><div class='add'>+#include "dcn401/dcn401_dpp.h"</div><div class='add'>+</div><div class='add'>+static struct spl_callbacks dcn2_spl_callbacks = {</div><div class='add'>+	.spl_calc_lb_num_partitions = dscl2_spl_calc_lb_num_partitions,</div><div class='add'>+};</div><div class='add'>+static struct spl_callbacks dcn32_spl_callbacks = {</div><div class='add'>+	.spl_calc_lb_num_partitions = dscl32_spl_calc_lb_num_partitions,</div><div class='add'>+};</div><div class='add'>+static struct spl_callbacks dcn401_spl_callbacks = {</div><div class='add'>+	.spl_calc_lb_num_partitions = dscl401_spl_calc_lb_num_partitions,</div><div class='add'>+};</div><div class='add'>+static void populate_splrect_from_rect(struct spl_rect *spl_rect, const struct rect *rect)</div><div class='add'>+{</div><div class='add'>+	spl_rect-&gt;x = rect-&gt;x;</div><div class='add'>+	spl_rect-&gt;y = rect-&gt;y;</div><div class='add'>+	spl_rect-&gt;width = rect-&gt;width;</div><div class='add'>+	spl_rect-&gt;height = rect-&gt;height;</div><div class='add'>+}</div><div class='add'>+static void populate_rect_from_splrect(struct rect *rect, const struct spl_rect *spl_rect)</div><div class='add'>+{</div><div class='add'>+	rect-&gt;x = spl_rect-&gt;x;</div><div class='add'>+	rect-&gt;y = spl_rect-&gt;y;</div><div class='add'>+	rect-&gt;width = spl_rect-&gt;width;</div><div class='add'>+	rect-&gt;height = spl_rect-&gt;height;</div><div class='add'>+}</div><div class='add'>+static void populate_spltaps_from_taps(struct spl_taps *spl_scaling_quality,</div><div class='add'>+		const struct scaling_taps *scaling_quality)</div><div class='add'>+{</div><div class='add'>+	spl_scaling_quality-&gt;h_taps_c = scaling_quality-&gt;h_taps_c;</div><div class='add'>+	spl_scaling_quality-&gt;h_taps = scaling_quality-&gt;h_taps;</div><div class='add'>+	spl_scaling_quality-&gt;v_taps_c = scaling_quality-&gt;v_taps_c;</div><div class='add'>+	spl_scaling_quality-&gt;v_taps = scaling_quality-&gt;v_taps;</div><div class='add'>+	spl_scaling_quality-&gt;integer_scaling = scaling_quality-&gt;integer_scaling;</div><div class='add'>+}</div><div class='add'>+static void populate_taps_from_spltaps(struct scaling_taps *scaling_quality,</div><div class='add'>+		const struct spl_taps *spl_scaling_quality)</div><div class='add'>+{</div><div class='add'>+	scaling_quality-&gt;h_taps_c = spl_scaling_quality-&gt;h_taps_c + 1;</div><div class='add'>+	scaling_quality-&gt;h_taps = spl_scaling_quality-&gt;h_taps + 1;</div><div class='add'>+	scaling_quality-&gt;v_taps_c = spl_scaling_quality-&gt;v_taps_c + 1;</div><div class='add'>+	scaling_quality-&gt;v_taps = spl_scaling_quality-&gt;v_taps + 1;</div><div class='add'>+}</div><div class='add'>+static void populate_ratios_from_splratios(struct scaling_ratios *ratios,</div><div class='add'>+		const struct ratio *spl_ratios)</div><div class='add'>+{</div><div class='add'>+	ratios-&gt;horz = dc_fixpt_from_ux_dy(spl_ratios-&gt;h_scale_ratio &gt;&gt; 5, 3, 19);</div><div class='add'>+	ratios-&gt;vert = dc_fixpt_from_ux_dy(spl_ratios-&gt;v_scale_ratio &gt;&gt; 5, 3, 19);</div><div class='add'>+	ratios-&gt;horz_c = dc_fixpt_from_ux_dy(spl_ratios-&gt;h_scale_ratio_c &gt;&gt; 5, 3, 19);</div><div class='add'>+	ratios-&gt;vert_c = dc_fixpt_from_ux_dy(spl_ratios-&gt;v_scale_ratio_c &gt;&gt; 5, 3, 19);</div><div class='add'>+}</div><div class='add'>+static void populate_inits_from_splinits(struct scl_inits *inits,</div><div class='add'>+		const struct init *spl_inits)</div><div class='add'>+{</div><div class='add'>+	inits-&gt;h = dc_fixpt_from_int_dy(spl_inits-&gt;h_filter_init_int, spl_inits-&gt;h_filter_init_frac &gt;&gt; 5, 0, 19);</div><div class='add'>+	inits-&gt;v = dc_fixpt_from_int_dy(spl_inits-&gt;v_filter_init_int, spl_inits-&gt;v_filter_init_frac &gt;&gt; 5, 0, 19);</div><div class='add'>+	inits-&gt;h_c = dc_fixpt_from_int_dy(spl_inits-&gt;h_filter_init_int_c, spl_inits-&gt;h_filter_init_frac_c &gt;&gt; 5, 0, 19);</div><div class='add'>+	inits-&gt;v_c = dc_fixpt_from_int_dy(spl_inits-&gt;v_filter_init_int_c, spl_inits-&gt;v_filter_init_frac_c &gt;&gt; 5, 0, 19);</div><div class='add'>+}</div><div class='add'>+static void populate_splformat_from_format(enum spl_pixel_format *spl_pixel_format, const enum pixel_format pixel_format)</div><div class='add'>+{</div><div class='add'>+	if (pixel_format &lt; PIXEL_FORMAT_INVALID)</div><div class='add'>+		*spl_pixel_format = (enum spl_pixel_format)pixel_format;</div><div class='add'>+	else</div><div class='add'>+		*spl_pixel_format = SPL_PIXEL_FORMAT_INVALID;</div><div class='add'>+}</div><div class='add'>+/// @brief Translate SPL input parameters from pipe context</div><div class='add'>+/// @param pipe_ctx</div><div class='add'>+/// @param spl_in</div><div class='add'>+void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in)</div><div class='add'>+{</div><div class='add'>+	const struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='add'>+	const struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	// Assign the function to calculate the number of partitions in the line buffer</div><div class='add'>+	// This is used to determine the vtap support</div><div class='add'>+	switch (plane_state-&gt;ctx-&gt;dce_version)	{</div><div class='add'>+	case DCN_VERSION_2_0:</div><div class='add'>+		spl_in-&gt;callbacks = dcn2_spl_callbacks;</div><div class='add'>+		break;</div><div class='add'>+	case DCN_VERSION_3_2:</div><div class='add'>+		spl_in-&gt;callbacks = dcn32_spl_callbacks;</div><div class='add'>+		break;</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		spl_in-&gt;callbacks = dcn401_spl_callbacks;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		spl_in-&gt;callbacks = dcn2_spl_callbacks;</div><div class='add'>+	}</div><div class='add'>+	// Make format field from spl_in point to plane_res scl_data format</div><div class='add'>+	populate_splformat_from_format(&amp;spl_in-&gt;basic_in.format, pipe_ctx-&gt;plane_res.scl_data.format);</div><div class='add'>+	// Make view_format from basic_out point to view_format from stream</div><div class='add'>+	spl_in-&gt;basic_out.view_format = (enum spl_view_3d)stream-&gt;view_format;</div><div class='add'>+	// Populate spl input basic input clip rect from plane state clip rect</div><div class='add'>+	populate_splrect_from_rect(&amp;spl_in-&gt;basic_in.clip_rect, &amp;plane_state-&gt;clip_rect);</div><div class='add'>+	// Populate spl input basic out src rect from stream src rect</div><div class='add'>+	populate_splrect_from_rect(&amp;spl_in-&gt;basic_out.src_rect, &amp;stream-&gt;src);</div><div class='add'>+	// Populate spl input basic out dst rect from stream dst rect</div><div class='add'>+	populate_splrect_from_rect(&amp;spl_in-&gt;basic_out.dst_rect, &amp;stream-&gt;dst);</div><div class='add'>+	// Make spl input basic input info rotation field point to plane state rotation</div><div class='add'>+	spl_in-&gt;basic_in.rotation = (enum spl_rotation_angle)plane_state-&gt;rotation;</div><div class='add'>+	// Populate spl input basic input src rect from plane state src rect</div><div class='add'>+	populate_splrect_from_rect(&amp;spl_in-&gt;basic_in.src_rect, &amp;plane_state-&gt;src_rect);</div><div class='add'>+	// Populate spl input basic input dst rect from plane state dst rect</div><div class='add'>+	populate_splrect_from_rect(&amp;spl_in-&gt;basic_in.dst_rect, &amp;plane_state-&gt;dst_rect);</div><div class='add'>+	// Make spl input basic input info horiz mirror field point to plane state horz mirror</div><div class='add'>+	spl_in-&gt;basic_in.horizontal_mirror = plane_state-&gt;horizontal_mirror;</div><div class='add'>+</div><div class='add'>+	// Calculate horizontal splits and split index</div><div class='add'>+	spl_in-&gt;basic_in.num_h_slices_recout_width_align.use_recout_width_aligned = false;</div><div class='add'>+	spl_in-&gt;basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices =</div><div class='add'>+		resource_get_mpc_slice_count(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)</div><div class='add'>+		spl_in-&gt;basic_in.mpc_h_slice_index = 0;</div><div class='add'>+	else</div><div class='add'>+		spl_in-&gt;basic_in.mpc_h_slice_index = resource_get_mpc_slice_index(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	populate_splrect_from_rect(&amp;spl_in-&gt;basic_out.odm_slice_rect, &amp;odm_slice_src);</div><div class='add'>+	spl_in-&gt;basic_out.odm_combine_factor = 0;</div><div class='add'>+	spl_in-&gt;odm_slice_index = resource_get_odm_slice_index(pipe_ctx);</div><div class='add'>+	// Make spl input basic out info output_size width point to stream h active</div><div class='add'>+	spl_in-&gt;basic_out.output_size.width =</div><div class='add'>+		stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right + pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='add'>+	// Make spl input basic out info output_size height point to v active</div><div class='add'>+	spl_in-&gt;basic_out.output_size.height =</div><div class='add'>+		stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_bottom + stream-&gt;timing.v_border_top;</div><div class='add'>+	spl_in-&gt;basic_out.max_downscale_src_width =</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.max_downscale_src_width;</div><div class='add'>+	spl_in-&gt;basic_out.always_scale = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.always_scale;</div><div class='add'>+	// Make spl input basic output info alpha_en field point to plane res scl_data lb_params alpha_en</div><div class='add'>+	spl_in-&gt;basic_out.alpha_en = pipe_ctx-&gt;plane_res.scl_data.lb_params.alpha_en;</div><div class='add'>+	spl_in-&gt;basic_out.use_two_pixels_per_container = pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing);</div><div class='add'>+	// Make spl input basic input info scaling quality field point to plane state scaling_quality</div><div class='add'>+	populate_spltaps_from_taps(&amp;spl_in-&gt;scaling_quality, &amp;plane_state-&gt;scaling_quality);</div><div class='add'>+	// Translate edge adaptive scaler preference</div><div class='add'>+	spl_in-&gt;prefer_easf = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;config.prefer_easf;</div><div class='add'>+	spl_in-&gt;disable_easf = false;</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_easf == 1)</div><div class='add'>+		spl_in-&gt;prefer_easf = false;</div><div class='add'>+	else if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_easf == 2)</div><div class='add'>+		spl_in-&gt;disable_easf = true;</div><div class='add'>+	else if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_easf == 3)</div><div class='add'>+		spl_in-&gt;override_easf = true;</div><div class='add'>+	/* Translate adaptive sharpening preference */</div><div class='add'>+	unsigned int sharpness_setting = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_sharpness;</div><div class='add'>+	unsigned int force_sharpness_level = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_sharpness_level;</div><div class='add'>+	if (sharpness_setting == SHARPNESS_HW_OFF)</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.enable = false;</div><div class='add'>+	else if (sharpness_setting == SHARPNESS_ZERO) {</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.enable = true;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_level = 0;</div><div class='add'>+	} else if (sharpness_setting == SHARPNESS_CUSTOM) {</div><div class='add'>+		/* SAT: read harpness_range from dc_plane_state */</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.sdr_rgb_min = plane_state-&gt;sharpness_range.sdr_rgb_min;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.sdr_rgb_max = plane_state-&gt;sharpness_range.sdr_rgb_max;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.sdr_rgb_mid = plane_state-&gt;sharpness_range.sdr_rgb_mid;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.sdr_yuv_min = plane_state-&gt;sharpness_range.sdr_yuv_min;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.sdr_yuv_max = plane_state-&gt;sharpness_range.sdr_yuv_max;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.sdr_yuv_mid = plane_state-&gt;sharpness_range.sdr_yuv_mid;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.hdr_rgb_min = plane_state-&gt;sharpness_range.hdr_rgb_min;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.hdr_rgb_max = plane_state-&gt;sharpness_range.hdr_rgb_max;</div><div class='add'>+		spl_in-&gt;adaptive_sharpness.sharpness_range.hdr_rgb_mid = plane_state-&gt;sharpness_range.hdr_rgb_mid;</div><div class='add'>+</div><div class='add'>+		if (force_sharpness_level &gt; 0) {</div><div class='add'>+			if (force_sharpness_level &gt; 10)</div><div class='add'>+				force_sharpness_level = 10;</div><div class='add'>+			spl_in-&gt;adaptive_sharpness.enable = true;</div><div class='add'>+			spl_in-&gt;adaptive_sharpness.sharpness_level = force_sharpness_level;</div><div class='add'>+		} else if (!plane_state-&gt;adaptive_sharpness_en) {</div><div class='add'>+			spl_in-&gt;adaptive_sharpness.enable = false;</div><div class='add'>+			spl_in-&gt;adaptive_sharpness.sharpness_level = 0;</div><div class='add'>+		} else {</div><div class='add'>+			spl_in-&gt;adaptive_sharpness.enable = true;</div><div class='add'>+			spl_in-&gt;adaptive_sharpness.sharpness_level = plane_state-&gt;sharpness_level;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	// Translate linear light scaling preference</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_lls &gt; 0)</div><div class='add'>+		spl_in-&gt;lls_pref = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_lls;</div><div class='add'>+	else</div><div class='add'>+		spl_in-&gt;lls_pref = plane_state-&gt;linear_light_scaling;</div><div class='add'>+	/* Translate chroma subsampling offset ( cositing ) */</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_cositing)</div><div class='add'>+		spl_in-&gt;basic_in.cositing = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.force_cositing - 1;</div><div class='add'>+	else</div><div class='add'>+		spl_in-&gt;basic_in.cositing = plane_state-&gt;cositing;</div><div class='add'>+	/* Translate transfer function */</div><div class='add'>+	spl_in-&gt;basic_in.tf_type = (enum spl_transfer_func_type) plane_state-&gt;in_transfer_func.type;</div><div class='add'>+	spl_in-&gt;basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state-&gt;in_transfer_func.tf;</div><div class='add'>+</div><div class='add'>+	spl_in-&gt;h_active = pipe_ctx-&gt;plane_res.scl_data.h_active;</div><div class='add'>+	spl_in-&gt;v_active = pipe_ctx-&gt;plane_res.scl_data.v_active;</div><div class='add'>+</div><div class='add'>+	spl_in-&gt;sharpen_policy = (enum sharpen_policy)plane_state-&gt;adaptive_sharpness_policy;</div><div class='add'>+	spl_in-&gt;debug.scale_to_sharpness_policy =</div><div class='add'>+		(enum scale_to_sharpness_policy)pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.scale_to_sharpness_policy;</div><div class='add'>+</div><div class='add'>+	/* Check if it is stream is in fullscreen and if its HDR.</div><div class='add'>+	 * Use this to determine sharpness levels</div><div class='add'>+	 */</div><div class='add'>+	spl_in-&gt;is_fullscreen = pipe_ctx-&gt;stream-&gt;sharpening_required;</div><div class='add'>+	spl_in-&gt;is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx-&gt;stream-&gt;ctx, pipe_ctx-&gt;stream);</div><div class='add'>+	spl_in-&gt;sdr_white_level_nits = plane_state-&gt;sdr_white_level_nits;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/// @brief Translate SPL output parameters to pipe context</div><div class='add'>+/// @param pipe_ctx</div><div class='add'>+/// @param spl_out</div><div class='add'>+void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out)</div><div class='add'>+{</div><div class='add'>+	// Make scaler data recout point to spl output field recout</div><div class='add'>+	populate_rect_from_splrect(&amp;pipe_ctx-&gt;plane_res.scl_data.recout, &amp;spl_out-&gt;dscl_prog_data-&gt;recout);</div><div class='add'>+	// Make scaler data ratios point to spl output field ratios</div><div class='add'>+	populate_ratios_from_splratios(&amp;pipe_ctx-&gt;plane_res.scl_data.ratios, &amp;spl_out-&gt;dscl_prog_data-&gt;ratios);</div><div class='add'>+	// Make scaler data viewport point to spl output field viewport</div><div class='add'>+	populate_rect_from_splrect(&amp;pipe_ctx-&gt;plane_res.scl_data.viewport, &amp;spl_out-&gt;dscl_prog_data-&gt;viewport);</div><div class='add'>+	// Make scaler data viewport_c point to spl output field viewport_c</div><div class='add'>+	populate_rect_from_splrect(&amp;pipe_ctx-&gt;plane_res.scl_data.viewport_c, &amp;spl_out-&gt;dscl_prog_data-&gt;viewport_c);</div><div class='add'>+	// Make scaler data taps point to spl output field scaling taps</div><div class='add'>+	populate_taps_from_spltaps(&amp;pipe_ctx-&gt;plane_res.scl_data.taps, &amp;spl_out-&gt;dscl_prog_data-&gt;taps);</div><div class='add'>+	// Make scaler data init point to spl output field init</div><div class='add'>+	populate_inits_from_splinits(&amp;pipe_ctx-&gt;plane_res.scl_data.inits, &amp;spl_out-&gt;dscl_prog_data-&gt;init);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h<br/>new file mode 100644<br/>index 000000000000..eaa5c5373b28<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_spl_translate.h</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_TRANSLATE_H__</div><div class='add'>+#define __DC_SPL_TRANSLATE_H__</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "dm_helpers.h"</div><div class='add'>+</div><div class='add'>+/* Map SPL input parameters to pipe context</div><div class='add'>+ * @pipe_ctx: pipe context</div><div class='add'>+ * @spl_in: spl input structure</div><div class='add'>+ */</div><div class='add'>+void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_in *spl_in);</div><div class='add'>+</div><div class='add'>+/* Map SPL output parameters to pipe context</div><div class='add'>+ * @pipe_ctx: pipe context</div><div class='add'>+ * @spl_out: spl output structure</div><div class='add'>+ */</div><div class='add'>+void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_TRANSLATE_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_state.h b/drivers/gpu/drm/amd/display/dc/dc_state.h<br/>index d167fdbfa8a9..db1e63a7d460 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_state.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_state.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_state.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_state.h</a></div><div class='hunk'>@@ -26,10 +26,9 @@</div><div class='ctx'> #ifndef _DC_STATE_H_</div><div class='ctx'> #define _DC_STATE_H_</div><div class='ctx'> </div><div class='del'>-#include "dc.h"</div><div class='ctx'> #include "inc/core_status.h"</div><div class='ctx'> </div><div class='del'>-struct dc_state *dc_state_create(struct dc *dc);</div><div class='add'>+struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params);</div><div class='ctx'> void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state);</div><div class='ctx'> struct dc_state *dc_state_create_copy(struct dc_state *src_state);</div><div class='ctx'> void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state);</div><div class='hunk'>@@ -39,12 +38,12 @@ void dc_state_destruct(struct dc_state *state);</div><div class='ctx'> void dc_state_retain(struct dc_state *state);</div><div class='ctx'> void dc_state_release(struct dc_state *state);</div><div class='ctx'> </div><div class='del'>-enum dc_status dc_state_add_stream(struct dc *dc,</div><div class='add'>+enum dc_status dc_state_add_stream(const struct dc *dc,</div><div class='ctx'> 				    struct dc_state *state,</div><div class='ctx'> 				    struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> enum dc_status dc_state_remove_stream(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+		const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='hunk'>@@ -74,5 +73,5 @@ bool dc_state_add_all_planes_for_stream(</div><div class='ctx'> </div><div class='ctx'> struct dc_stream_status *dc_state_get_stream_status(</div><div class='ctx'> 	struct dc_state *state,</div><div class='del'>-	struct dc_stream_state *stream);</div><div class='add'>+	const struct dc_stream_state *stream);</div><div class='ctx'> #endif /* _DC_STATE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_state_priv.h b/drivers/gpu/drm/amd/display/dc/dc_state_priv.h<br/>index c1f44e09a6c1..1d9bae56ff6a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_state_priv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_state_priv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_state_priv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_state_priv.h</a></div><div class='hunk'>@@ -29,6 +29,8 @@</div><div class='ctx'> #include "dc_state.h"</div><div class='ctx'> #include "dc_stream.h"</div><div class='ctx'> </div><div class='add'>+struct dc_stream_state *dc_state_get_stream_from_id(const struct dc_state *state, unsigned int id);</div><div class='add'>+</div><div class='ctx'> /* Get the type of the provided resource (none, phantom, main) based on the provided</div><div class='ctx'>  * context. If the context is unavailable, determine only if phantom or not.</div><div class='ctx'>  */</div><div class='hunk'>@@ -45,7 +47,7 @@ struct dc_stream_state *dc_state_get_paired_subvp_stream(const struct dc_state *</div><div class='ctx'> struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *main_stream);</div><div class='del'>-struct dc_plane_state *dc_state_create_phantom_plane(struct dc *dc,</div><div class='add'>+struct dc_plane_state *dc_state_create_phantom_plane(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_plane_state *main_plane);</div><div class='ctx'> </div><div class='hunk'>@@ -58,11 +60,11 @@ void dc_state_release_phantom_plane(const struct dc *dc,</div><div class='ctx'> 		struct dc_plane_state *phantom_plane);</div><div class='ctx'> </div><div class='ctx'> /* add/remove phantom stream to context and generate subvp meta data */</div><div class='del'>-enum dc_status dc_state_add_phantom_stream(struct dc *dc,</div><div class='add'>+enum dc_status dc_state_add_phantom_stream(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *phantom_stream,</div><div class='ctx'> 		struct dc_stream_state *main_stream);</div><div class='del'>-enum dc_status dc_state_remove_phantom_stream(struct dc *dc,</div><div class='add'>+enum dc_status dc_state_remove_phantom_stream(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *phantom_stream);</div><div class='ctx'> </div><div class='hunk'>@@ -92,11 +94,35 @@ bool dc_state_add_all_phantom_planes_for_stream(</div><div class='ctx'> 		struct dc_state *state);</div><div class='ctx'> </div><div class='ctx'> bool dc_state_remove_phantom_streams_and_planes(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+		const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state);</div><div class='ctx'> </div><div class='ctx'> void dc_state_release_phantom_streams_and_planes(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+		const struct dc *dc,</div><div class='ctx'> 		struct dc_state *state);</div><div class='ctx'> </div><div class='add'>+bool dc_state_is_fams2_in_use(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_state *state);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dc_state_set_stream_subvp_cursor_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		bool limit);</div><div class='add'>+</div><div class='add'>+bool dc_state_get_stream_subvp_cursor_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+void dc_state_set_stream_cursor_subvp_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		bool limit);</div><div class='add'>+</div><div class='add'>+bool dc_state_get_stream_cursor_subvp_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_can_clear_stream_cursor_subvp_limit(const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_is_subvp_in_use(struct dc_state *state);</div><div class='add'>+</div><div class='ctx'> #endif /* _DC_STATE_PRIV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h<br/>index ee10941caa59..321cfe92d799 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_stream.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_stream.h</a></div><div class='hunk'>@@ -44,6 +44,8 @@ struct mall_stream_config {</div><div class='ctx'> 	 */</div><div class='ctx'> 	enum mall_stream_type type;</div><div class='ctx'> 	struct dc_stream_state *paired_stream;	// master / slave stream</div><div class='add'>+	bool subvp_limit_cursor_size; /* stream has/is using subvp limiting hw cursor support */</div><div class='add'>+	bool cursor_size_limit_subvp; /* stream is using hw cursor config preventing subvp */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_stream_status {</div><div class='hunk'>@@ -56,9 +58,10 @@ struct dc_stream_status {</div><div class='ctx'> 	int plane_count;</div><div class='ctx'> 	int audio_inst;</div><div class='ctx'> 	struct timing_sync_info timing_sync_info;</div><div class='del'>-	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];</div><div class='add'>+	struct dc_plane_state *plane_states[MAX_SURFACES];</div><div class='ctx'> 	bool is_abm_supported;</div><div class='ctx'> 	struct mall_stream_config mall_stream_config;</div><div class='add'>+	bool fpo_in_use;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum hubp_dmdata_mode {</div><div class='hunk'>@@ -141,6 +144,8 @@ union stream_update_flags {</div><div class='ctx'> 		uint32_t mst_bw : 1;</div><div class='ctx'> 		uint32_t crtc_timing_adjust : 1;</div><div class='ctx'> 		uint32_t fams_changed : 1;</div><div class='add'>+		uint32_t scaler_sharpener : 1;</div><div class='add'>+		uint32_t sharpening_required : 1;</div><div class='ctx'> 	} bits;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t raw;</div><div class='hunk'>@@ -158,6 +163,24 @@ struct test_pattern {</div><div class='ctx'> </div><div class='ctx'> struct dc_stream_debug_options {</div><div class='ctx'> 	char force_odm_combine_segments;</div><div class='add'>+	/*</div><div class='add'>+	 * When force_odm_combine_segments is non zero, allow dc to</div><div class='add'>+	 * temporarily transition to ODM bypass when minimal transition state</div><div class='add'>+	 * is required to prevent visual glitches showing on the screen</div><div class='add'>+	 */</div><div class='add'>+	char allow_transition_for_forced_odm;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define LUMINANCE_DATA_TABLE_SIZE 10</div><div class='add'>+</div><div class='add'>+struct luminance_data {</div><div class='add'>+	bool is_valid;</div><div class='add'>+	int refresh_rate_hz[LUMINANCE_DATA_TABLE_SIZE];</div><div class='add'>+	int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE];</div><div class='add'>+	int flicker_criteria_milli_nits_GAMING;</div><div class='add'>+	int flicker_criteria_milli_nits_STATIC;</div><div class='add'>+	int nominal_refresh_rate;</div><div class='add'>+	int dm_max_decrease_from_nominal;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_stream_state {</div><div class='hunk'>@@ -180,6 +203,7 @@ struct dc_stream_state {</div><div class='ctx'> 	struct dc_info_packet hfvsif_infopacket;</div><div class='ctx'> 	struct dc_info_packet vtem_infopacket;</div><div class='ctx'> 	struct dc_info_packet adaptive_sync_infopacket;</div><div class='add'>+	struct dc_info_packet avi_infopacket;</div><div class='ctx'> 	uint8_t dsc_packed_pps[128];</div><div class='ctx'> 	struct rect src; /* composition area */</div><div class='ctx'> 	struct rect dst; /* stream addressable area */</div><div class='hunk'>@@ -190,7 +214,7 @@ struct dc_stream_state {</div><div class='ctx'> 	PHYSICAL_ADDRESS_LOC dmdata_address;</div><div class='ctx'> 	bool   use_dynamic_meta;</div><div class='ctx'> </div><div class='del'>-	struct dc_transfer_func *out_transfer_func;</div><div class='add'>+	struct dc_transfer_func out_transfer_func;</div><div class='ctx'> 	struct colorspace_transform gamut_remap_matrix;</div><div class='ctx'> 	struct dc_csc_transform csc_color_matrix;</div><div class='ctx'> </div><div class='hunk'>@@ -247,6 +271,8 @@ struct dc_stream_state {</div><div class='ctx'> </div><div class='ctx'> 	struct dc_cursor_attributes cursor_attributes;</div><div class='ctx'> 	struct dc_cursor_position cursor_position;</div><div class='add'>+	bool hw_cursor_req;</div><div class='add'>+</div><div class='ctx'> 	uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode</div><div class='ctx'> </div><div class='ctx'> 	/* from stream struct */</div><div class='hunk'>@@ -284,8 +310,11 @@ struct dc_stream_state {</div><div class='ctx'> </div><div class='ctx'> 	bool has_non_synchronizable_pclk;</div><div class='ctx'> 	bool vblank_synchronized;</div><div class='del'>-	bool fpo_in_use;</div><div class='ctx'> 	bool is_phantom;</div><div class='add'>+</div><div class='add'>+	struct luminance_data lumin_data;</div><div class='add'>+	bool scaler_sharpener_update;</div><div class='add'>+	bool sharpening_required;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define ABM_LEVEL_IMMEDIATE_DISABLE 255</div><div class='hunk'>@@ -307,6 +336,8 @@ struct dc_stream_update {</div><div class='ctx'> 	struct dc_info_packet *hfvsif_infopacket;</div><div class='ctx'> 	struct dc_info_packet *vtem_infopacket;</div><div class='ctx'> 	struct dc_info_packet *adaptive_sync_infopacket;</div><div class='add'>+	struct dc_info_packet *avi_infopacket;</div><div class='add'>+</div><div class='ctx'> 	bool *dpms_off;</div><div class='ctx'> 	bool integer_scaling_update;</div><div class='ctx'> 	bool *allow_freesync;</div><div class='hunk'>@@ -327,6 +358,12 @@ struct dc_stream_update {</div><div class='ctx'> </div><div class='ctx'> 	struct test_pattern *pending_test_pattern;</div><div class='ctx'> 	struct dc_crtc_timing_adjust *crtc_timing_adjust;</div><div class='add'>+</div><div class='add'>+	struct dc_cursor_attributes *cursor_attributes;</div><div class='add'>+	struct dc_cursor_position *cursor_position;</div><div class='add'>+	bool *hw_cursor_req;</div><div class='add'>+	bool *scaler_sharpener_update;</div><div class='add'>+	bool *sharpening_required;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool dc_is_stream_unchanged(</div><div class='hunk'>@@ -415,10 +452,6 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='del'>-bool dc_stream_warmup_writeback(struct dc *dc,</div><div class='del'>-		int num_dwb,</div><div class='del'>-		struct dc_writeback_info *wb_info);</div><div class='del'>-</div><div class='ctx'> bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> bool dc_stream_set_dynamic_metadata(struct dc *dc,</div><div class='hunk'>@@ -428,14 +461,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,</div><div class='ctx'> enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Set up streams and links associated to drive sinks</div><div class='del'>- * The streams parameter is an absolute set of all active streams.</div><div class='del'>- *</div><div class='del'>- * After this call:</div><div class='del'>- *   Phy, Encoder, Timing Generator are programmed and enabled.</div><div class='del'>- *   New streams are enabled with blank stream; no memory read.</div><div class='del'>- */</div><div class='del'>-/*</div><div class='ctx'>  * Enable stereo when commit_streams is not required,</div><div class='ctx'>  * for example, frame alternate.</div><div class='ctx'>  */</div><div class='hunk'>@@ -448,12 +473,11 @@ void dc_enable_stereo(</div><div class='ctx'> /* Triggers multi-stream synchronization. */</div><div class='ctx'> void dc_trigger_sync(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='del'>-enum surface_update_type dc_check_update_surfaces_for_stream(</div><div class='del'>-		struct dc *dc,</div><div class='add'>+struct surface_update_descriptor dc_check_update_surfaces_for_stream(</div><div class='add'>+		const struct dc_check_config *check_config,</div><div class='ctx'> 		struct dc_surface_update *updates,</div><div class='ctx'> 		int surface_count,</div><div class='del'>-		struct dc_stream_update *stream_update,</div><div class='del'>-		const struct dc_stream_status *stream_status);</div><div class='add'>+		struct dc_stream_update *stream_update);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * Create a new default stream for the requested sink</div><div class='hunk'>@@ -467,21 +491,43 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);</div><div class='ctx'> void dc_stream_retain(struct dc_stream_state *dc_stream);</div><div class='ctx'> void dc_stream_release(struct dc_stream_state *dc_stream);</div><div class='ctx'> </div><div class='del'>-struct dc_stream_status *dc_stream_get_status(</div><div class='del'>-	struct dc_stream_state *dc_stream);</div><div class='add'>+struct dc_stream_status *dc_stream_get_status(struct dc_stream_state *dc_stream);</div><div class='add'>+const struct dc_stream_status *dc_stream_get_status_const(const struct dc_stream_state *dc_stream);</div><div class='ctx'> </div><div class='ctx'> /*******************************************************************************</div><div class='ctx'>  * Cursor interfaces - To manages the cursor within a stream</div><div class='ctx'>  ******************************************************************************/</div><div class='ctx'> /* TODO: Deprecated once we switch to dc_set_cursor_position */</div><div class='add'>+</div><div class='add'>+void program_cursor_attributes(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+void program_cursor_position(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+bool dc_stream_check_cursor_attributes(</div><div class='add'>+	const struct dc_stream_state *stream,</div><div class='add'>+	struct dc_state *state,</div><div class='add'>+	const struct dc_cursor_attributes *attributes);</div><div class='add'>+</div><div class='ctx'> bool dc_stream_set_cursor_attributes(</div><div class='ctx'> 	struct dc_stream_state *stream,</div><div class='ctx'> 	const struct dc_cursor_attributes *attributes);</div><div class='ctx'> </div><div class='add'>+bool dc_stream_program_cursor_attributes(</div><div class='add'>+	struct dc_stream_state *stream,</div><div class='add'>+	const struct dc_cursor_attributes *attributes);</div><div class='add'>+</div><div class='ctx'> bool dc_stream_set_cursor_position(</div><div class='ctx'> 	struct dc_stream_state *stream,</div><div class='ctx'> 	const struct dc_cursor_position *position);</div><div class='ctx'> </div><div class='add'>+bool dc_stream_program_cursor_position(</div><div class='add'>+	struct dc_stream_state *stream,</div><div class='add'>+	const struct dc_cursor_position *position);</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> bool dc_stream_adjust_vmin_vmax(struct dc *dc,</div><div class='ctx'> 				struct dc_stream_state *stream,</div><div class='hunk'>@@ -491,26 +537,29 @@ bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		uint32_t *refresh_rate);</div><div class='ctx'> </div><div class='del'>-bool dc_stream_get_crtc_position(struct dc *dc,</div><div class='del'>-				 struct dc_stream_state **stream,</div><div class='del'>-				 int num_streams,</div><div class='del'>-				 unsigned int *v_pos,</div><div class='del'>-				 unsigned int *nom_v_pos);</div><div class='del'>-</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='ctx'> bool dc_stream_forward_crc_window(struct dc_stream_state *stream,</div><div class='ctx'> 		struct rect *rect,</div><div class='add'>+		uint8_t phy_id,</div><div class='ctx'> 		bool is_stop);</div><div class='add'>+</div><div class='add'>+bool dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream,</div><div class='add'>+		struct crc_window *window,</div><div class='add'>+		uint8_t phy_id,</div><div class='add'>+		bool stop);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> bool dc_stream_configure_crc(struct dc *dc,</div><div class='ctx'> 			     struct dc_stream_state *stream,</div><div class='ctx'> 			     struct crc_params *crc_window,</div><div class='ctx'> 			     bool enable,</div><div class='del'>-			     bool continuous);</div><div class='add'>+			     bool continuous,</div><div class='add'>+			     uint8_t idx,</div><div class='add'>+			     bool reset);</div><div class='ctx'> </div><div class='ctx'> bool dc_stream_get_crc(struct dc *dc,</div><div class='ctx'> 		       struct dc_stream_state *stream,</div><div class='add'>+		       uint8_t idx,</div><div class='ctx'> 		       uint32_t *r_cr,</div><div class='ctx'> 		       uint32_t *g_y,</div><div class='ctx'> 		       uint32_t *b_cb);</div><div class='hunk'>@@ -532,11 +581,16 @@ bool dc_stream_set_gamut_remap(struct dc *dc,</div><div class='ctx'> bool dc_stream_program_csc_matrix(struct dc *dc,</div><div class='ctx'> 				  struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='del'>-bool dc_stream_get_crtc_position(struct dc *dc,</div><div class='del'>-				 struct dc_stream_state **stream,</div><div class='del'>-				 int num_streams,</div><div class='del'>-				 unsigned int *v_pos,</div><div class='del'>-				 unsigned int *nom_v_pos);</div><div class='add'>+struct dc_rmcm_3dlut *dc_stream_get_3dlut_for_stream(</div><div class='add'>+	const struct dc *dc,</div><div class='add'>+	const struct dc_stream_state *stream,</div><div class='add'>+	bool allocate_one);</div><div class='add'>+</div><div class='add'>+void dc_stream_release_3dlut_for_stream(</div><div class='add'>+	const struct dc *dc,</div><div class='add'>+	const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+void dc_stream_init_rmcm_3dlut(struct dc *dc);</div><div class='ctx'> </div><div class='ctx'> struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='hunk'>@@ -545,4 +599,8 @@ void dc_dmub_update_dirty_rect(struct dc *dc,</div><div class='ctx'> 			       struct dc_stream_state *stream,</div><div class='ctx'> 			       struct dc_surface_update *srf_updates,</div><div class='ctx'> 			       struct dc_state *context);</div><div class='add'>+</div><div class='add'>+bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream);</div><div class='add'>+bool dc_stream_can_clear_cursor_limit(struct dc *dc, struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> #endif /* DC_STREAM_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h b/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h<br/>index 7476fd52ce2b..ca37eac20986 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_stream_priv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_stream_priv.h</a></div><div class='hunk'>@@ -34,4 +34,42 @@ void dc_stream_destruct(struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> void dc_stream_assign_stream_id(struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Finds the highest refresh rate that can be achieved</div><div class='add'>+ * from starting_freq while staying within flicker criteria</div><div class='add'>+ */</div><div class='add'>+int dc_stream_calculate_max_flickerless_refresh_rate(struct dc_stream_state *stream,</div><div class='add'>+						      int starting_refresh_hz,</div><div class='add'>+						      bool is_gaming);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Finds the lowest refresh rate that can be achieved</div><div class='add'>+ * from starting_freq while staying within flicker criteria</div><div class='add'>+ */</div><div class='add'>+int dc_stream_calculate_min_flickerless_refresh_rate(struct dc_stream_state *stream,</div><div class='add'>+						      int starting_refresh_hz,</div><div class='add'>+						      bool is_gaming);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines if there will be a flicker when moving between 2 refresh rates</div><div class='add'>+ */</div><div class='add'>+bool dc_stream_is_refresh_rate_range_flickerless(struct dc_stream_state *stream,</div><div class='add'>+						  int hz1,</div><div class='add'>+						  int hz2,</div><div class='add'>+						  bool is_gaming);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the max instant vtotal delta increase that can be applied without</div><div class='add'>+ * flickering for a given stream</div><div class='add'>+ */</div><div class='add'>+unsigned int dc_stream_get_max_flickerless_instant_vtotal_decrease(struct dc_stream_state *stream,</div><div class='add'>+									  bool is_gaming);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the max instant vtotal delta decrease that can be applied without</div><div class='add'>+ * flickering for a given stream</div><div class='add'>+ */</div><div class='add'>+unsigned int dc_stream_get_max_flickerless_instant_vtotal_increase(struct dc_stream_state *stream,</div><div class='add'>+									  bool is_gaming);</div><div class='add'>+</div><div class='ctx'> #endif // _DC_STREAM_PRIV_H_</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h<br/>index be2ac5c442a4..f46039f64203 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dc_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dc_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dc_types.h</a></div><div class='hunk'>@@ -76,7 +76,6 @@ struct dc_perf_trace {</div><div class='ctx'> 	unsigned long last_entry_write;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define MAX_SURFACE_NUM 6</div><div class='ctx'> #define NUM_PIXEL_FORMATS 10</div><div class='ctx'> </div><div class='ctx'> enum tiling_mode {</div><div class='hunk'>@@ -176,10 +175,20 @@ struct dc_panel_patch {</div><div class='ctx'> 	unsigned int embedded_tiled_slave;</div><div class='ctx'> 	unsigned int disable_fams;</div><div class='ctx'> 	unsigned int skip_avmute;</div><div class='add'>+	unsigned int skip_audio_sab_check;</div><div class='ctx'> 	unsigned int mst_start_top_delay;</div><div class='ctx'> 	unsigned int remove_sink_ext_caps;</div><div class='add'>+	unsigned int disable_colorimetry;</div><div class='add'>+	uint8_t blankstream_before_otg_off;</div><div class='add'>+	bool oled_optimize_display_on;</div><div class='add'>+	unsigned int force_mst_blocked_discovery;</div><div class='add'>+	unsigned int wait_after_dpcd_poweroff_ms;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct dc_edid_caps - Capabilities read from EDID.</div><div class='add'>+ * @analog: Whether the monitor is analog. Used by DVI-I handling.</div><div class='add'>+ */</div><div class='ctx'> struct dc_edid_caps {</div><div class='ctx'> 	/* sink identification */</div><div class='ctx'> 	uint16_t manufacturer_id;</div><div class='hunk'>@@ -206,6 +215,9 @@ struct dc_edid_caps {</div><div class='ctx'> </div><div class='ctx'> 	bool edid_hdmi;</div><div class='ctx'> 	bool hdr_supported;</div><div class='add'>+	bool rr_capable;</div><div class='add'>+	bool scdc_present;</div><div class='add'>+	bool analog;</div><div class='ctx'> </div><div class='ctx'> 	struct dc_panel_patch panel_patch;</div><div class='ctx'> };</div><div class='hunk'>@@ -258,6 +270,7 @@ enum dc_timing_source {</div><div class='ctx'> 	TIMING_SOURCE_EDID_4BYTE,</div><div class='ctx'> 	TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,</div><div class='ctx'> 	TIMING_SOURCE_EDID_CEA_RID,</div><div class='add'>+	TIMING_SOURCE_EDID_DISPLAYID_TYPE5,</div><div class='ctx'> 	TIMING_SOURCE_VBIOS,</div><div class='ctx'> 	TIMING_SOURCE_CV,</div><div class='ctx'> 	TIMING_SOURCE_TV,</div><div class='hunk'>@@ -340,7 +353,8 @@ enum dc_connection_type {</div><div class='ctx'> 	dc_connection_none,</div><div class='ctx'> 	dc_connection_single,</div><div class='ctx'> 	dc_connection_mst_branch,</div><div class='del'>-	dc_connection_sst_branch</div><div class='add'>+	dc_connection_sst_branch,</div><div class='add'>+	dc_connection_dac_load</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_csc_adjustments {</div><div class='hunk'>@@ -422,7 +436,7 @@ struct dc_dwb_params {</div><div class='ctx'> 	enum dwb_capture_rate		capture_rate;	/* controls the frame capture rate */</div><div class='ctx'> 	struct scaling_taps 		scaler_taps;	/* Scaling taps */</div><div class='ctx'> 	enum dwb_subsample_position	subsample_position;</div><div class='del'>-	struct dc_transfer_func *out_transfer_func;</div><div class='add'>+	const struct dc_transfer_func *out_transfer_func;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* audio*/</div><div class='hunk'>@@ -556,6 +570,12 @@ struct dc_info_packet_128 {</div><div class='ctx'> 	uint8_t sb[128];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dc_edid_read_policy {</div><div class='add'>+	uint32_t max_retry_count;</div><div class='add'>+	uint32_t delay_time_ms;</div><div class='add'>+	uint32_t ignore_checksum;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define DC_PLANE_UPDATE_TIMES_MAX 10</div><div class='ctx'> </div><div class='ctx'> struct dc_plane_flip_time {</div><div class='hunk'>@@ -564,6 +584,12 @@ struct dc_plane_flip_time {</div><div class='ctx'> 	unsigned int prev_update_time_in_us;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dc_alpm_mode {</div><div class='add'>+	DC_ALPM_AUXWAKE = 0,</div><div class='add'>+	DC_ALPM_AUXLESS = 1,</div><div class='add'>+	DC_ALPM_UNSUPPORTED = 0xF,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum dc_psr_state {</div><div class='ctx'> 	PSR_STATE0 = 0x0,</div><div class='ctx'> 	PSR_STATE1,</div><div class='hunk'>@@ -590,6 +616,7 @@ enum dc_psr_state {</div><div class='ctx'> 	PSR_STATE5c,</div><div class='ctx'> 	PSR_STATE_HWLOCK_MGR,</div><div class='ctx'> 	PSR_STATE_POLLVUPDATE,</div><div class='add'>+	PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME,</div><div class='ctx'> 	PSR_STATE_INVALID = 0xFF</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -608,6 +635,7 @@ struct psr_config {</div><div class='ctx'> 	unsigned int line_time_in_us;</div><div class='ctx'> 	uint8_t rate_control_caps;</div><div class='ctx'> 	uint16_t dsc_slice_height;</div><div class='add'>+	bool os_request_force_ffu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union dmcu_psr_level {</div><div class='hunk'>@@ -720,6 +748,7 @@ struct psr_context {</div><div class='ctx'> 	unsigned int line_time_in_us;</div><div class='ctx'> 	uint8_t rate_control_caps;</div><div class='ctx'> 	uint16_t dsc_slice_height;</div><div class='add'>+	bool os_request_force_ffu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct colorspace_transform {</div><div class='hunk'>@@ -870,6 +899,14 @@ struct dsc_dec_dpcd_caps {</div><div class='ctx'> 	bool is_dp; /* Decoded format */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct hblank_expansion_dpcd_caps {</div><div class='add'>+	bool expansion_supported;</div><div class='add'>+	bool reduction_supported;</div><div class='add'>+	bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/</div><div class='add'>+	bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/</div><div class='add'>+	uint32_t buffer_size; /* Add 1 to value and multiply by 32 */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dc_golden_table {</div><div class='ctx'> 	uint16_t dc_golden_table_ver;</div><div class='ctx'> 	uint32_t aux_dphy_rx_control0_val;</div><div class='hunk'>@@ -904,6 +941,12 @@ enum dc_psr_version {</div><div class='ctx'> 	DC_PSR_VERSION_UNSUPPORTED		= 0xFFFFFFFF,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dc_replay_version {</div><div class='add'>+	DC_FREESYNC_REPLAY = 0,</div><div class='add'>+	DC_VESA_PANEL_REPLAY = 1,</div><div class='add'>+	DC_REPLAY_VERSION_UNSUPPORTED = 0XFF,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Possible values of display_endpoint_id.endpoint */</div><div class='ctx'> enum display_endpoint_type {</div><div class='ctx'> 	DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */</div><div class='hunk'>@@ -920,11 +963,24 @@ struct display_endpoint_id {</div><div class='ctx'> 	enum display_endpoint_type ep_type;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum backlight_control_type {</div><div class='add'>+	BACKLIGHT_CONTROL_PWM = 0,</div><div class='add'>+	BACKLIGHT_CONTROL_VESA_AUX = 1,</div><div class='add'>+	BACKLIGHT_CONTROL_AMD_AUX = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)</div><div class='add'>+#define MAX_CRC_WINDOW_NUM	2</div><div class='add'>+</div><div class='ctx'> struct otg_phy_mux {</div><div class='ctx'> 	uint8_t phy_output_num;</div><div class='ctx'> 	uint8_t otg_output_num;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+struct crc_window {</div><div class='add'>+	struct rect rect;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> enum dc_detect_reason {</div><div class='hunk'>@@ -1008,6 +1064,13 @@ struct psr_settings {</div><div class='ctx'> 	unsigned int psr_sdp_transmit_line_num_deadline;</div><div class='ctx'> 	uint8_t force_ffu_mode;</div><div class='ctx'> 	unsigned int psr_power_opt;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Some panels cannot handle idle pattern during PSR entry.</div><div class='add'>+	 * To power down phy before disable stream to avoid sending</div><div class='add'>+	 * idle pattern.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t power_down_phy_before_disable_stream;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum replay_coasting_vtotal_type {</div><div class='hunk'>@@ -1035,21 +1098,49 @@ enum replay_FW_Message_type {</div><div class='ctx'> 	Replay_Set_Timing_Sync_Supported,</div><div class='ctx'> 	Replay_Set_Residency_Frameupdate_Timer,</div><div class='ctx'> 	Replay_Set_Pseudo_VTotal,</div><div class='add'>+	Replay_Disabled_Adaptive_Sync_SDP,</div><div class='add'>+	Replay_Set_Version,</div><div class='add'>+	Replay_Set_General_Cmd,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union replay_error_status {</div><div class='ctx'> 	struct {</div><div class='del'>-		unsigned char STATE_TRANSITION_ERROR    :1;</div><div class='del'>-		unsigned char LINK_CRC_ERROR            :1;</div><div class='del'>-		unsigned char DESYNC_ERROR              :1;</div><div class='del'>-		unsigned char RESERVED                  :5;</div><div class='add'>+		unsigned int STATE_TRANSITION_ERROR     :1;</div><div class='add'>+		unsigned int LINK_CRC_ERROR             :1;</div><div class='add'>+		unsigned int DESYNC_ERROR               :1;</div><div class='add'>+		unsigned int RESERVED_3                 :1;</div><div class='add'>+		unsigned int LOW_RR_INCORRECT_VTOTAL    :1;</div><div class='add'>+		unsigned int NO_DOUBLED_RR              :1;</div><div class='add'>+		unsigned int RESERVED_6_7               :2;</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	unsigned char raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union replay_low_refresh_rate_enable_options {</div><div class='add'>+	struct {</div><div class='add'>+	//BIT[0-3]: Replay Low Hz Support control</div><div class='add'>+		unsigned int ENABLE_LOW_RR_SUPPORT          :1;</div><div class='add'>+		unsigned int SKIP_ASIC_CHECK                :1;</div><div class='add'>+		unsigned int RESERVED_2_3                   :2;</div><div class='add'>+	//BIT[4-15]: Replay Low Hz Enable Scenarios</div><div class='add'>+		unsigned int ENABLE_STATIC_SCREEN           :1;</div><div class='add'>+		unsigned int ENABLE_FULL_SCREEN_VIDEO       :1;</div><div class='add'>+		unsigned int ENABLE_GENERAL_UI              :1;</div><div class='add'>+		unsigned int RESERVED_7_15                  :9;</div><div class='add'>+	//BIT[16-31]: Replay Low Hz Enable Check</div><div class='add'>+		unsigned int ENABLE_STATIC_FLICKER_CHECK    :1;</div><div class='add'>+		unsigned int RESERVED_17_31                 :15;</div><div class='add'>+	} bits;</div><div class='add'>+	unsigned int raw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct replay_config {</div><div class='add'>+	/* Replay version */</div><div class='add'>+	enum dc_replay_version replay_version;</div><div class='ctx'> 	/* Replay feature is supported */</div><div class='ctx'> 	bool replay_supported;</div><div class='add'>+	/* Replay caps support DPCD &amp; EDID caps*/</div><div class='add'>+	bool replay_cap_support;</div><div class='ctx'> 	/* Power opt flags that are supported */</div><div class='ctx'> 	unsigned int replay_power_opt_supported;</div><div class='ctx'> 	/* SMU optimization is supported */</div><div class='hunk'>@@ -1068,6 +1159,18 @@ struct replay_config {</div><div class='ctx'> 	bool replay_support_fast_resync_in_ultra_sleep_mode;</div><div class='ctx'> 	/* Replay error status */</div><div class='ctx'> 	union replay_error_status replay_error_status;</div><div class='add'>+	/* Replay Low Hz enable Options */</div><div class='add'>+	union replay_low_refresh_rate_enable_options low_rr_enable_options;</div><div class='add'>+	/* Replay coasting vtotal is within low refresh rate range. */</div><div class='add'>+	bool low_rr_activated;</div><div class='add'>+	/* Replay low refresh rate supported*/</div><div class='add'>+	bool low_rr_supported;</div><div class='add'>+	/* Replay Video Conferencing Optimization Enabled */</div><div class='add'>+	bool replay_video_conferencing_optimization_enabled;</div><div class='add'>+	/* Replay alpm mode */</div><div class='add'>+	enum dc_alpm_mode alpm_mode;</div><div class='add'>+	/* Replay full screen only */</div><div class='add'>+	bool os_request_force_ffu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Replay feature flags*/</div><div class='hunk'>@@ -1088,12 +1191,22 @@ struct replay_settings {</div><div class='ctx'> 	uint32_t coasting_vtotal;</div><div class='ctx'> 	/* Coasting vtotal table */</div><div class='ctx'> 	uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];</div><div class='add'>+	/* Defer Update Coasting vtotal table */</div><div class='add'>+	uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM];</div><div class='add'>+	/* Skip frame number table */</div><div class='add'>+	uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM];</div><div class='add'>+	/* Defer skip frame number table */</div><div class='add'>+	uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM];</div><div class='ctx'> 	/* Maximum link off frame count */</div><div class='del'>-	enum replay_link_off_frame_count_level link_off_frame_count_level;</div><div class='del'>-	/* Replay pseudo vtotal for abm + ips on full screen video which can improve ips residency */</div><div class='del'>-	uint16_t abm_with_ips_on_full_screen_video_pseudo_vtotal;</div><div class='add'>+	uint32_t link_off_frame_count;</div><div class='add'>+	/* Replay pseudo vtotal for low refresh rate*/</div><div class='add'>+	uint16_t low_rr_full_screen_video_pseudo_vtotal;</div><div class='ctx'> 	/* Replay last pseudo vtotal set to DMUB */</div><div class='ctx'> 	uint16_t last_pseudo_vtotal;</div><div class='add'>+	/* Replay desync error */</div><div class='add'>+	uint32_t replay_desync_error_fail_count;</div><div class='add'>+	/* The frame skip number dal send to DMUB */</div><div class='add'>+	uint16_t frame_skip_number;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* To split out "global" and "per-panel" config settings.</div><div class='hunk'>@@ -1126,6 +1239,7 @@ struct dc_panel_config {</div><div class='ctx'> 		bool rc_disable;</div><div class='ctx'> 		bool rc_allow_static_screen;</div><div class='ctx'> 		bool rc_allow_fullscreen_VPB;</div><div class='add'>+		bool read_psrcap_again;</div><div class='ctx'> 		unsigned int replay_enable_option;</div><div class='ctx'> 	} psr;</div><div class='ctx'> 	/* ABM */</div><div class='hunk'>@@ -1159,7 +1273,6 @@ struct dc_dpia_bw_alloc {</div><div class='ctx'> 	int bw_granularity;    // BW Granularity</div><div class='ctx'> 	int dp_overhead;       // DP overhead in dp tunneling</div><div class='ctx'> 	bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3:  DP-Tx &amp; Dpia &amp; CM</div><div class='del'>-	bool response_ready;   // Response ready from the CM side</div><div class='ctx'> 	uint8_t nrd_max_lane_count; // Non-reduced max lane count</div><div class='ctx'> 	uint8_t nrd_max_link_rate; // Non-reduced max link rate</div><div class='ctx'> };</div><div class='hunk'>@@ -1170,9 +1283,150 @@ enum dc_hpd_enable_select {</div><div class='ctx'> 	HPD_EN_FOR_SECONDARY_EDP_ONLY,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dc_cm2_shaper_3dlut_setting {</div><div class='add'>+	DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL,</div><div class='add'>+	DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER,</div><div class='add'>+	/* Bypassing Shaper will always bypass 3DLUT */</div><div class='add'>+	DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_cm2_gpu_mem_layout {</div><div class='add'>+	DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB,</div><div class='add'>+	DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR,</div><div class='add'>+	DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_cm2_gpu_mem_pixel_component_order {</div><div class='add'>+	DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_cm2_gpu_mem_format {</div><div class='add'>+	DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB,</div><div class='add'>+	DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB,</div><div class='add'>+	DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_cm2_gpu_mem_format_parameters {</div><div class='add'>+	enum dc_cm2_gpu_mem_format format;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			/* bias &amp; scale for float only */</div><div class='add'>+			uint16_t bias;</div><div class='add'>+			uint16_t scale;</div><div class='add'>+		} float_params;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_cm2_gpu_mem_size {</div><div class='add'>+	DC_CM2_GPU_MEM_SIZE_171717,</div><div class='add'>+	DC_CM2_GPU_MEM_SIZE_TRANSFORMED,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_cm2_gpu_mem_parameters {</div><div class='add'>+	struct dc_plane_address addr;</div><div class='add'>+	enum dc_cm2_gpu_mem_layout layout;</div><div class='add'>+	struct dc_cm2_gpu_mem_format_parameters format_params;</div><div class='add'>+	enum dc_cm2_gpu_mem_pixel_component_order component_order;</div><div class='add'>+	enum dc_cm2_gpu_mem_size  size;</div><div class='add'>+	uint16_t bit_depth;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_cm2_transfer_func_source {</div><div class='add'>+	DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM,</div><div class='add'>+	DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_cm2_component_settings {</div><div class='add'>+	enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting;</div><div class='add'>+	bool lut1d_enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * All pointers in this struct must remain valid for as long as the 3DLUTs are used</div><div class='add'>+ */</div><div class='add'>+struct dc_cm2_func_luts {</div><div class='add'>+	const struct dc_transfer_func *shaper;</div><div class='add'>+	struct {</div><div class='add'>+		enum dc_cm2_transfer_func_source lut3d_src;</div><div class='add'>+		union {</div><div class='add'>+			const struct dc_3dlut *lut3d_func;</div><div class='add'>+			struct dc_cm2_gpu_mem_parameters gpu_mem_params;</div><div class='add'>+		};</div><div class='add'>+		bool rmcm_3dlut_shaper_select;</div><div class='add'>+		bool mpc_3dlut_enable;</div><div class='add'>+		bool rmcm_3dlut_enable;</div><div class='add'>+		bool mpc_mcm_post_blend;</div><div class='add'>+		uint8_t rmcm_tmz;</div><div class='add'>+	} lut3d_data;</div><div class='add'>+	const struct dc_transfer_func *lut1d_func;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_cm2_parameters {</div><div class='add'>+	struct dc_cm2_component_settings component_settings;</div><div class='add'>+	struct dc_cm2_func_luts cm2_luts;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum mall_stream_type {</div><div class='ctx'> 	SUBVP_NONE, // subvp not in use</div><div class='ctx'> 	SUBVP_MAIN, // subvp in use, this stream is main stream</div><div class='ctx'> 	SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+enum dc_power_source_type {</div><div class='add'>+	DC_POWER_SOURCE_AC, // wall power</div><div class='add'>+	DC_POWER_SOURCE_DC, // battery power</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_state_create_params {</div><div class='add'>+	enum dc_power_source_type power_source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_commit_streams_params {</div><div class='add'>+	struct dc_stream_state **streams;</div><div class='add'>+	uint8_t stream_count;</div><div class='add'>+	enum dc_power_source_type power_source;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_backlight_level_params {</div><div class='add'>+	/* backlight in pwm */</div><div class='add'>+	uint32_t backlight_pwm_u16_16;</div><div class='add'>+	/* brightness ramping */</div><div class='add'>+	uint32_t frame_ramp;</div><div class='add'>+	/* backlight control type</div><div class='add'>+	 * 0: PWM backlight control</div><div class='add'>+	 * 1: VESA AUX backlight control</div><div class='add'>+	 * 2: AMD AUX backlight control</div><div class='add'>+	 */</div><div class='add'>+	enum backlight_control_type control_type;</div><div class='add'>+	/* backlight in millinits */</div><div class='add'>+	uint32_t backlight_millinits;</div><div class='add'>+	/* transition time in ms */</div><div class='add'>+	uint32_t transition_time_in_ms;</div><div class='add'>+	/* minimum luminance in nits */</div><div class='add'>+	uint32_t min_luminance;</div><div class='add'>+	/* maximum luminance in nits */</div><div class='add'>+	uint32_t max_luminance;</div><div class='add'>+	/* minimum backlight in pwm */</div><div class='add'>+	uint32_t min_backlight_pwm;</div><div class='add'>+	/* maximum backlight in pwm */</div><div class='add'>+	uint32_t max_backlight_pwm;</div><div class='add'>+	/* AUX HW instance */</div><div class='add'>+	uint8_t aux_inst;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dc_validate_mode {</div><div class='add'>+	/* validate the mode and program HW */</div><div class='add'>+	DC_VALIDATE_MODE_AND_PROGRAMMING = 0,</div><div class='add'>+	/* only validate the mode */</div><div class='add'>+	DC_VALIDATE_MODE_ONLY = 1,</div><div class='add'>+	/* validate the mode and get the max state (voltage level) */</div><div class='add'>+	DC_VALIDATE_MODE_AND_STATE_INDEX = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_validation_dpia_set {</div><div class='add'>+	const struct dc_link *link;</div><div class='add'>+	const struct dc_tunnel_settings *tunnel_settings;</div><div class='add'>+	uint32_t required_bw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #endif /* DC_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dccg/Makefile b/drivers/gpu/drm/amd/display/dc/dccg/Makefile<br/>new file mode 100644<br/>index 000000000000..1d5cf0f8e79d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/Makefile</a></div><div class='hunk'>@@ -0,0 +1,103 @@</div><div class='add'>+</div><div class='add'>+# Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'dccg' sub-component of DAL.</div><div class='add'>+#</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN20 = dcn20_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN20 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn20/,$(DCCG_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN201 = dcn201_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN201 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn201/,$(DCCG_DCN201))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN201)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN21 = dcn21_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN21 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn21/,$(DCCG_DCN21))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN21)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+DCCG_DCN30 = dcn30_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN30 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn30/,$(DCCG_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+DCCG_DCN301 = dcn301_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN301 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn301/,$(DCCG_DCN301))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN301)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN31 = dcn31_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN31 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn31/,$(DCCG_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN31)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN314 = dcn314_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN314 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn314/,$(DCCG_DCN314))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN314)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN32 = dcn32_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN32 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn32/,$(DCCG_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DCCG_DCN35 = dcn35_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN35 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn35/,$(DCCG_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+DCCG_DCN401 = dcn401_dccg.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401)</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c<br/>index 5999b2da3a01..33d8bd91cb01 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c</a></div><div class='hunk'>@@ -148,7 +148,7 @@ struct dccg *dccg2_create(</div><div class='ctx'> 	const struct dccg_shift *dccg_shift,</div><div class='ctx'> 	const struct dccg_mask *dccg_mask)</div><div class='ctx'> {</div><div class='del'>-	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC);</div><div class='add'>+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);</div><div class='ctx'> 	struct dccg *base;</div><div class='ctx'> </div><div class='ctx'> 	if (dccg_dcn == NULL) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h<br/>index ef5c22f41563..8bdffd9ff31b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h</a></div><div class='hunk'>@@ -328,6 +328,36 @@</div><div class='ctx'> 	type DPSTREAMCLK1_GATE_DISABLE;\</div><div class='ctx'> 	type DPSTREAMCLK2_GATE_DISABLE;\</div><div class='ctx'> 	type DPSTREAMCLK3_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKA_FE_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKB_FE_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKC_FE_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKD_FE_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKE_FE_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKA_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKB_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKC_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKD_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKE_GATE_DISABLE;\</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define DCCG401_REG_FIELD_LIST(type) \</div><div class='add'>+	type OTG0_TMDS_PIXEL_RATE_DIV;\</div><div class='add'>+	type DPDTO0_INT;\</div><div class='add'>+	type OTG1_TMDS_PIXEL_RATE_DIV;\</div><div class='add'>+	type DPDTO1_INT;\</div><div class='add'>+	type OTG2_TMDS_PIXEL_RATE_DIV;\</div><div class='add'>+	type DPDTO2_INT;\</div><div class='add'>+	type OTG3_TMDS_PIXEL_RATE_DIV;\</div><div class='add'>+	type DPDTO3_INT;\</div><div class='add'>+	type SYMCLK32_ROOT_LE2_GATE_DISABLE;\</div><div class='add'>+	type SYMCLK32_ROOT_LE3_GATE_DISABLE;\</div><div class='add'>+	type SYMCLK32_LE2_GATE_DISABLE;\</div><div class='add'>+	type SYMCLK32_LE3_GATE_DISABLE;\</div><div class='add'>+	type SYMCLK32_LE2_SRC_SEL;\</div><div class='add'>+	type SYMCLK32_LE3_SRC_SEL;\</div><div class='add'>+	type SYMCLK32_LE2_EN;\</div><div class='add'>+	type SYMCLK32_LE3_EN;\</div><div class='add'>+	type DP_DTO_ENABLE[MAX_PIPES];</div><div class='ctx'> </div><div class='ctx'> struct dccg_shift {</div><div class='ctx'> 	DCCG_REG_FIELD_LIST(uint8_t)</div><div class='hunk'>@@ -336,6 +366,7 @@ struct dccg_shift {</div><div class='ctx'> 	DCCG314_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> 	DCCG32_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> 	DCCG35_REG_FIELD_LIST(uint8_t)</div><div class='add'>+	DCCG401_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dccg_mask {</div><div class='hunk'>@@ -345,53 +376,120 @@ struct dccg_mask {</div><div class='ctx'> 	DCCG314_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> 	DCCG32_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> 	DCCG35_REG_FIELD_LIST(uint32_t)</div><div class='add'>+	DCCG401_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define DCCG_REG_VARIABLE_LIST \</div><div class='add'>+	uint32_t DPPCLK_DTO_CTRL; \</div><div class='add'>+	uint32_t DPPCLK_DTO_PARAM[6]; \</div><div class='add'>+	uint32_t REFCLK_CNTL; \</div><div class='add'>+	uint32_t DISPCLK_FREQ_CHANGE_CNTL; \</div><div class='add'>+	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \</div><div class='add'>+	uint32_t HDMICHARCLK_CLOCK_CNTL[6]; \</div><div class='add'>+	uint32_t PHYASYMCLK_CLOCK_CNTL; \</div><div class='add'>+	uint32_t PHYBSYMCLK_CLOCK_CNTL; \</div><div class='add'>+	uint32_t PHYCSYMCLK_CLOCK_CNTL; \</div><div class='add'>+	uint32_t PHYDSYMCLK_CLOCK_CNTL; \</div><div class='add'>+	uint32_t PHYESYMCLK_CLOCK_CNTL; \</div><div class='add'>+	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \</div><div class='add'>+	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTO_SOURCE; \</div><div class='add'>+	uint32_t DPSTREAMCLK_CNTL; \</div><div class='add'>+	uint32_t HDMISTREAMCLK_CNTL; \</div><div class='add'>+	uint32_t SYMCLK32_SE_CNTL; \</div><div class='add'>+	uint32_t SYMCLK32_LE_CNTL; \</div><div class='add'>+	uint32_t DENTIST_DISPCLK_CNTL; \</div><div class='add'>+	uint32_t DSCCLK_DTO_CTRL; \</div><div class='add'>+	uint32_t DSCCLK0_DTO_PARAM; \</div><div class='add'>+	uint32_t DSCCLK1_DTO_PARAM; \</div><div class='add'>+	uint32_t DSCCLK2_DTO_PARAM; \</div><div class='add'>+	uint32_t DSCCLK3_DTO_PARAM; \</div><div class='add'>+	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; \</div><div class='add'>+	uint32_t DPSTREAMCLK_GATE_DISABLE; \</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL; \</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL2; \</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL3; \</div><div class='add'>+	uint32_t HDMISTREAMCLK0_DTO_PARAM; \</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL4; \</div><div class='add'>+	uint32_t OTG_PIXEL_RATE_DIV; \</div><div class='add'>+	uint32_t DTBCLK_P_CNTL; \</div><div class='add'>+	uint32_t DPPCLK_CTRL; \</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL5; \</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL6; \</div><div class='add'>+	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; \</div><div class='add'>+	uint32_t SYMCLKA_CLOCK_ENABLE; \</div><div class='add'>+	uint32_t SYMCLKB_CLOCK_ENABLE; \</div><div class='add'>+	uint32_t SYMCLKC_CLOCK_ENABLE; \</div><div class='add'>+	uint32_t SYMCLKD_CLOCK_ENABLE; \</div><div class='add'>+	uint32_t SYMCLKE_CLOCK_ENABLE; \</div><div class='add'>+	uint32_t DP_DTO_MODULO[MAX_PIPES]; \</div><div class='add'>+	uint32_t DP_DTO_PHASE[MAX_PIPES]; \</div><div class='add'>+	uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTO0_MODULE; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTO0_PHASE; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTO1_MODULE; \</div><div class='add'>+	uint32_t DCCG_AUDIO_DTO1_PHASE; \</div><div class='add'>+	uint32_t DCCG_CAC_STATUS; \</div><div class='add'>+	uint32_t DCCG_CAC_STATUS2; \</div><div class='add'>+	uint32_t DCCG_DISP_CNTL_REG; \</div><div class='add'>+	uint32_t DCCG_DS_CNTL; \</div><div class='add'>+	uint32_t DCCG_DS_DTO_INCR; \</div><div class='add'>+	uint32_t DCCG_DS_DTO_MODULO; \</div><div class='add'>+	uint32_t DCCG_DS_HW_CAL_INTERVAL; \</div><div class='add'>+	uint32_t DCCG_GTC_CNTL; \</div><div class='add'>+	uint32_t DCCG_GTC_CURRENT; \</div><div class='add'>+	uint32_t DCCG_GTC_DTO_INCR; \</div><div class='add'>+	uint32_t DCCG_GTC_DTO_MODULO; \</div><div class='add'>+	uint32_t DCCG_PERFMON_CNTL; \</div><div class='add'>+	uint32_t DCCG_PERFMON_CNTL2; \</div><div class='add'>+	uint32_t DCCG_SOFT_RESET; \</div><div class='add'>+	uint32_t DCCG_TEST_CLK_SEL; \</div><div class='add'>+	uint32_t DCCG_VSYNC_CNT_CTRL; \</div><div class='add'>+	uint32_t DCCG_VSYNC_CNT_INT_CTRL; \</div><div class='add'>+	uint32_t DCCG_VSYNC_OTG0_LATCH_VALUE; \</div><div class='add'>+	uint32_t DCCG_VSYNC_OTG1_LATCH_VALUE; \</div><div class='add'>+	uint32_t DCCG_VSYNC_OTG2_LATCH_VALUE; \</div><div class='add'>+	uint32_t DCCG_VSYNC_OTG3_LATCH_VALUE; \</div><div class='add'>+	uint32_t DCCG_VSYNC_OTG4_LATCH_VALUE; \</div><div class='add'>+	uint32_t DCCG_VSYNC_OTG5_LATCH_VALUE; \</div><div class='add'>+	uint32_t DISPCLK_CGTT_BLK_CTRL_REG; \</div><div class='add'>+	uint32_t DP_DTO_DBUF_EN; \</div><div class='add'>+	uint32_t DPIACLK_540M_DTO_MODULO; \</div><div class='add'>+	uint32_t DPIACLK_540M_DTO_PHASE; \</div><div class='add'>+	uint32_t DPIACLK_810M_DTO_MODULO; \</div><div class='add'>+	uint32_t DPIACLK_810M_DTO_PHASE; \</div><div class='add'>+	uint32_t DPIACLK_DTO_CNTL; \</div><div class='add'>+	uint32_t DPIASYMCLK_CNTL; \</div><div class='add'>+	uint32_t DPPCLK_CGTT_BLK_CTRL_REG; \</div><div class='add'>+	uint32_t DPREFCLK_CGTT_BLK_CTRL_REG; \</div><div class='add'>+	uint32_t DPREFCLK_CNTL; \</div><div class='add'>+	uint32_t DTBCLK_DTO_DBUF_EN; \</div><div class='add'>+	uint32_t FORCE_SYMCLK_DISABLE; \</div><div class='add'>+	uint32_t HDMICHARCLK0_CLOCK_CNTL; \</div><div class='add'>+	uint32_t MICROSECOND_TIME_BASE_DIV; \</div><div class='add'>+	uint32_t MILLISECOND_TIME_BASE_DIV; \</div><div class='add'>+	uint32_t OTG0_PHYPLL_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG0_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG1_PHYPLL_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG1_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG2_PHYPLL_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG2_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG3_PHYPLL_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t OTG3_PIXEL_RATE_CNTL; \</div><div class='add'>+	uint32_t PHYPLLA_PIXCLK_RESYNC_CNTL; \</div><div class='add'>+	uint32_t PHYPLLB_PIXCLK_RESYNC_CNTL; \</div><div class='add'>+	uint32_t PHYPLLC_PIXCLK_RESYNC_CNTL; \</div><div class='add'>+	uint32_t PHYPLLD_PIXCLK_RESYNC_CNTL; \</div><div class='add'>+	uint32_t PHYPLLE_PIXCLK_RESYNC_CNTL; \</div><div class='add'>+	uint32_t REFCLK_CGTT_BLK_CTRL_REG; \</div><div class='add'>+	uint32_t SOCCLK_CGTT_BLK_CTRL_REG; \</div><div class='add'>+	uint32_t SYMCLK_CGTT_BLK_CTRL_REG; \</div><div class='add'>+	uint32_t SYMCLK_PSP_CNTL</div><div class='add'>+</div><div class='ctx'> struct dccg_registers {</div><div class='del'>-	uint32_t DPPCLK_DTO_CTRL;</div><div class='del'>-	uint32_t DPPCLK_DTO_PARAM[6];</div><div class='del'>-	uint32_t REFCLK_CNTL;</div><div class='del'>-	uint32_t DISPCLK_FREQ_CHANGE_CNTL;</div><div class='del'>-	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];</div><div class='del'>-	uint32_t HDMICHARCLK_CLOCK_CNTL[6];</div><div class='del'>-	uint32_t PHYASYMCLK_CLOCK_CNTL;</div><div class='del'>-	uint32_t PHYBSYMCLK_CLOCK_CNTL;</div><div class='del'>-	uint32_t PHYCSYMCLK_CLOCK_CNTL;</div><div class='del'>-	uint32_t PHYDSYMCLK_CLOCK_CNTL;</div><div class='del'>-	uint32_t PHYESYMCLK_CLOCK_CNTL;</div><div class='del'>-	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];</div><div class='del'>-	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];</div><div class='del'>-	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;</div><div class='del'>-	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;</div><div class='del'>-	uint32_t DCCG_AUDIO_DTO_SOURCE;</div><div class='del'>-	uint32_t DPSTREAMCLK_CNTL;</div><div class='del'>-	uint32_t HDMISTREAMCLK_CNTL;</div><div class='del'>-	uint32_t SYMCLK32_SE_CNTL;</div><div class='del'>-	uint32_t SYMCLK32_LE_CNTL;</div><div class='del'>-	uint32_t DENTIST_DISPCLK_CNTL;</div><div class='del'>-	uint32_t DSCCLK_DTO_CTRL;</div><div class='del'>-	uint32_t DSCCLK0_DTO_PARAM;</div><div class='del'>-	uint32_t DSCCLK1_DTO_PARAM;</div><div class='del'>-	uint32_t DSCCLK2_DTO_PARAM;</div><div class='del'>-	uint32_t DSCCLK3_DTO_PARAM;</div><div class='del'>-	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;</div><div class='del'>-	uint32_t DPSTREAMCLK_GATE_DISABLE;</div><div class='del'>-	uint32_t DCCG_GATE_DISABLE_CNTL;</div><div class='del'>-	uint32_t DCCG_GATE_DISABLE_CNTL2;</div><div class='del'>-	uint32_t DCCG_GATE_DISABLE_CNTL3;</div><div class='del'>-	uint32_t HDMISTREAMCLK0_DTO_PARAM;</div><div class='del'>-	uint32_t DCCG_GATE_DISABLE_CNTL4;</div><div class='del'>-	uint32_t OTG_PIXEL_RATE_DIV;</div><div class='del'>-	uint32_t DTBCLK_P_CNTL;</div><div class='del'>-	uint32_t DPPCLK_CTRL;</div><div class='del'>-	uint32_t DCCG_GATE_DISABLE_CNTL5;</div><div class='del'>-	uint32_t DCCG_GATE_DISABLE_CNTL6;</div><div class='del'>-	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL;</div><div class='del'>-	uint32_t SYMCLKA_CLOCK_ENABLE;</div><div class='del'>-	uint32_t SYMCLKB_CLOCK_ENABLE;</div><div class='del'>-	uint32_t SYMCLKC_CLOCK_ENABLE;</div><div class='del'>-	uint32_t SYMCLKD_CLOCK_ENABLE;</div><div class='del'>-	uint32_t SYMCLKE_CLOCK_ENABLE;</div><div class='add'>+	DCCG_REG_VARIABLE_LIST;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn_dccg {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c<br/>index 9a3402148fde..9a3402148fde 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h<br/>index 80888b0484fb..80888b0484fb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c<br/>index d07c04458d31..d07c04458d31 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h<br/>index b7efa777ec73..b7efa777ec73 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c<br/>index d445dfefc047..d445dfefc047 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h<br/>index 35a613bb08bf..3f1da7f3a91c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h</a></div><div class='hunk'>@@ -29,15 +29,9 @@</div><div class='ctx'> #include "dcn20/dcn20_dccg.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-#define DCCG_REG_LIST_DCN3AG() \</div><div class='del'>-	DCCG_COMMON_REG_LIST_DCN_BASE(),\</div><div class='del'>-	SR(PHYASYMCLK_CLOCK_CNTL),\</div><div class='del'>-	SR(PHYBSYMCLK_CLOCK_CNTL),\</div><div class='del'>-	SR(PHYCSYMCLK_CLOCK_CNTL)</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> #define DCCG_REG_LIST_DCN30() \</div><div class='ctx'> 	DCCG_REG_LIST_DCN2(),\</div><div class='add'>+	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\</div><div class='ctx'> 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\</div><div class='ctx'> 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\</div><div class='ctx'> 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\</div><div class='hunk'>@@ -46,19 +40,10 @@</div><div class='ctx'> 	SR(PHYBSYMCLK_CLOCK_CNTL),\</div><div class='ctx'> 	SR(PHYCSYMCLK_CLOCK_CNTL)</div><div class='ctx'> </div><div class='del'>-#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \</div><div class='del'>-	DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\</div><div class='del'>-	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\</div><div class='del'>-	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\</div><div class='del'>-	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\</div><div class='del'>-	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\</div><div class='del'>-	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\</div><div class='del'>-	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\</div><div class='del'>-	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\</div><div class='del'>-	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)</div><div class='del'>-</div><div class='ctx'> #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \</div><div class='ctx'> 	DCCG_MASK_SH_LIST_DCN2(mask_sh),\</div><div class='add'>+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\</div><div class='ctx'> 	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c<br/>index 97e9be87afd9..97e9be87afd9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h<br/>index 73db962dbc03..067e49cb238e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h</a></div><div class='hunk'>@@ -56,10 +56,4 @@ struct dccg *dccg301_create(</div><div class='ctx'> 	const struct dccg_shift *dccg_shift,</div><div class='ctx'> 	const struct dccg_mask *dccg_mask);</div><div class='ctx'> </div><div class='del'>-struct dccg *dccg301_create(</div><div class='del'>-	struct dc_context *ctx,</div><div class='del'>-	const struct dccg_registers *regs,</div><div class='del'>-	const struct dccg_shift *dccg_shift,</div><div class='del'>-	const struct dccg_mask *dccg_mask);</div><div class='del'>-</div><div class='ctx'> #endif //__DCN301_DCCG_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h<br/>index c884dde1bb25..c884dde1bb25 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h<br/>index 2e12fb643005..2e12fb643005 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn303/dcn303_dccg.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c<br/>index 8664f0c4c9b7..97df04b7e39d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c</a></div><div class='hunk'>@@ -709,6 +709,128 @@ void dccg31_otg_drop_pixel(struct dccg *dccg,</div><div class='ctx'> 			OTG_DROP_PIXEL[otg_inst], 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	dccg_reg_state-&gt;dc_mem_global_pwr_req_cntl = REG_READ(DC_MEM_GLOBAL_PWR_REQ_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dtbclk_dto_modulo = REG_READ(DCCG_AUDIO_DTBCLK_DTO_MODULO);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dtbclk_dto_phase = REG_READ(DCCG_AUDIO_DTBCLK_DTO_PHASE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dto_source = REG_READ(DCCG_AUDIO_DTO_SOURCE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dto0_module = REG_READ(DCCG_AUDIO_DTO0_MODULE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dto0_phase = REG_READ(DCCG_AUDIO_DTO0_PHASE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dto1_module = REG_READ(DCCG_AUDIO_DTO1_MODULE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_audio_dto1_phase = REG_READ(DCCG_AUDIO_DTO1_PHASE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_cac_status = REG_READ(DCCG_CAC_STATUS);</div><div class='add'>+	dccg_reg_state-&gt;dccg_cac_status2 = REG_READ(DCCG_CAC_STATUS2);</div><div class='add'>+	dccg_reg_state-&gt;dccg_disp_cntl_reg = REG_READ(DCCG_DISP_CNTL_REG);</div><div class='add'>+	dccg_reg_state-&gt;dccg_ds_cntl = REG_READ(DCCG_DS_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_ds_dto_incr = REG_READ(DCCG_DS_DTO_INCR);</div><div class='add'>+	dccg_reg_state-&gt;dccg_ds_dto_modulo = REG_READ(DCCG_DS_DTO_MODULO);</div><div class='add'>+	dccg_reg_state-&gt;dccg_ds_hw_cal_interval = REG_READ(DCCG_DS_HW_CAL_INTERVAL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gate_disable_cntl = REG_READ(DCCG_GATE_DISABLE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gate_disable_cntl2 = REG_READ(DCCG_GATE_DISABLE_CNTL2);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gate_disable_cntl3 = REG_READ(DCCG_GATE_DISABLE_CNTL3);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gate_disable_cntl4 = REG_READ(DCCG_GATE_DISABLE_CNTL4);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gate_disable_cntl5 = REG_READ(DCCG_GATE_DISABLE_CNTL5);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gate_disable_cntl6 = REG_READ(DCCG_GATE_DISABLE_CNTL6);</div><div class='add'>+	dccg_reg_state-&gt;dccg_global_fgcg_rep_cntl = REG_READ(DCCG_GLOBAL_FGCG_REP_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gtc_cntl = REG_READ(DCCG_GTC_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gtc_current = REG_READ(DCCG_GTC_CURRENT);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gtc_dto_incr = REG_READ(DCCG_GTC_DTO_INCR);</div><div class='add'>+	dccg_reg_state-&gt;dccg_gtc_dto_modulo = REG_READ(DCCG_GTC_DTO_MODULO);</div><div class='add'>+	dccg_reg_state-&gt;dccg_perfmon_cntl = REG_READ(DCCG_PERFMON_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_perfmon_cntl2 = REG_READ(DCCG_PERFMON_CNTL2);</div><div class='add'>+	dccg_reg_state-&gt;dccg_soft_reset = REG_READ(DCCG_SOFT_RESET);</div><div class='add'>+	dccg_reg_state-&gt;dccg_test_clk_sel = REG_READ(DCCG_TEST_CLK_SEL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_cnt_ctrl = REG_READ(DCCG_VSYNC_CNT_CTRL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_cnt_int_ctrl = REG_READ(DCCG_VSYNC_CNT_INT_CTRL);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_otg0_latch_value = REG_READ(DCCG_VSYNC_OTG0_LATCH_VALUE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_otg1_latch_value = REG_READ(DCCG_VSYNC_OTG1_LATCH_VALUE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_otg2_latch_value = REG_READ(DCCG_VSYNC_OTG2_LATCH_VALUE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_otg3_latch_value = REG_READ(DCCG_VSYNC_OTG3_LATCH_VALUE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_otg4_latch_value = REG_READ(DCCG_VSYNC_OTG4_LATCH_VALUE);</div><div class='add'>+	dccg_reg_state-&gt;dccg_vsync_otg5_latch_value = REG_READ(DCCG_VSYNC_OTG5_LATCH_VALUE);</div><div class='add'>+	dccg_reg_state-&gt;dispclk_cgtt_blk_ctrl_reg = REG_READ(DISPCLK_CGTT_BLK_CTRL_REG);</div><div class='add'>+	dccg_reg_state-&gt;dispclk_freq_change_cntl = REG_READ(DISPCLK_FREQ_CHANGE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto_dbuf_en = REG_READ(DP_DTO_DBUF_EN);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto0_modulo = REG_READ(DP_DTO_MODULO[0]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto0_phase = REG_READ(DP_DTO_PHASE[0]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto1_modulo = REG_READ(DP_DTO_MODULO[1]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto1_phase = REG_READ(DP_DTO_PHASE[1]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto2_modulo = REG_READ(DP_DTO_MODULO[2]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto2_phase = REG_READ(DP_DTO_PHASE[2]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto3_modulo = REG_READ(DP_DTO_MODULO[3]);</div><div class='add'>+	dccg_reg_state-&gt;dp_dto3_phase = REG_READ(DP_DTO_PHASE[3]);</div><div class='add'>+	dccg_reg_state-&gt;dpiaclk_540m_dto_modulo = REG_READ(DPIACLK_540M_DTO_MODULO);</div><div class='add'>+	dccg_reg_state-&gt;dpiaclk_540m_dto_phase = REG_READ(DPIACLK_540M_DTO_PHASE);</div><div class='add'>+	dccg_reg_state-&gt;dpiaclk_810m_dto_modulo = REG_READ(DPIACLK_810M_DTO_MODULO);</div><div class='add'>+	dccg_reg_state-&gt;dpiaclk_810m_dto_phase = REG_READ(DPIACLK_810M_DTO_PHASE);</div><div class='add'>+	dccg_reg_state-&gt;dpiaclk_dto_cntl = REG_READ(DPIACLK_DTO_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dpiasymclk_cntl = REG_READ(DPIASYMCLK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dppclk_cgtt_blk_ctrl_reg = REG_READ(DPPCLK_CGTT_BLK_CTRL_REG);</div><div class='add'>+	dccg_reg_state-&gt;dppclk_ctrl = REG_READ(DPPCLK_CTRL);</div><div class='add'>+	dccg_reg_state-&gt;dppclk_dto_ctrl = REG_READ(DPPCLK_DTO_CTRL);</div><div class='add'>+	dccg_reg_state-&gt;dppclk0_dto_param = REG_READ(DPPCLK_DTO_PARAM[0]);</div><div class='add'>+	dccg_reg_state-&gt;dppclk1_dto_param = REG_READ(DPPCLK_DTO_PARAM[1]);</div><div class='add'>+	dccg_reg_state-&gt;dppclk2_dto_param = REG_READ(DPPCLK_DTO_PARAM[2]);</div><div class='add'>+	dccg_reg_state-&gt;dppclk3_dto_param = REG_READ(DPPCLK_DTO_PARAM[3]);</div><div class='add'>+	dccg_reg_state-&gt;dprefclk_cgtt_blk_ctrl_reg = REG_READ(DPREFCLK_CGTT_BLK_CTRL_REG);</div><div class='add'>+	dccg_reg_state-&gt;dprefclk_cntl = REG_READ(DPREFCLK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dpstreamclk_cntl = REG_READ(DPSTREAMCLK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;dscclk_dto_ctrl = REG_READ(DSCCLK_DTO_CTRL);</div><div class='add'>+	dccg_reg_state-&gt;dscclk0_dto_param = REG_READ(DSCCLK0_DTO_PARAM);</div><div class='add'>+	dccg_reg_state-&gt;dscclk1_dto_param = REG_READ(DSCCLK1_DTO_PARAM);</div><div class='add'>+	dccg_reg_state-&gt;dscclk2_dto_param = REG_READ(DSCCLK2_DTO_PARAM);</div><div class='add'>+	dccg_reg_state-&gt;dscclk3_dto_param = REG_READ(DSCCLK3_DTO_PARAM);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto_dbuf_en = REG_READ(DTBCLK_DTO_DBUF_EN);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto0_modulo = REG_READ(DTBCLK_DTO_MODULO[0]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto0_phase = REG_READ(DTBCLK_DTO_PHASE[0]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto1_modulo = REG_READ(DTBCLK_DTO_MODULO[1]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto1_phase = REG_READ(DTBCLK_DTO_PHASE[1]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto2_modulo = REG_READ(DTBCLK_DTO_MODULO[2]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto2_phase = REG_READ(DTBCLK_DTO_PHASE[2]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto3_modulo = REG_READ(DTBCLK_DTO_MODULO[3]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_dto3_phase = REG_READ(DTBCLK_DTO_PHASE[3]);</div><div class='add'>+	dccg_reg_state-&gt;dtbclk_p_cntl = REG_READ(DTBCLK_P_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;force_symclk_disable = REG_READ(FORCE_SYMCLK_DISABLE);</div><div class='add'>+	dccg_reg_state-&gt;hdmicharclk0_clock_cntl = REG_READ(HDMICHARCLK0_CLOCK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;hdmistreamclk_cntl = REG_READ(HDMISTREAMCLK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;hdmistreamclk0_dto_param = REG_READ(HDMISTREAMCLK0_DTO_PARAM);</div><div class='add'>+	dccg_reg_state-&gt;microsecond_time_base_div = REG_READ(MICROSECOND_TIME_BASE_DIV);</div><div class='add'>+	dccg_reg_state-&gt;millisecond_time_base_div = REG_READ(MILLISECOND_TIME_BASE_DIV);</div><div class='add'>+	dccg_reg_state-&gt;otg_pixel_rate_div = REG_READ(OTG_PIXEL_RATE_DIV);</div><div class='add'>+	dccg_reg_state-&gt;otg0_phypll_pixel_rate_cntl = REG_READ(OTG0_PHYPLL_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg0_pixel_rate_cntl = REG_READ(OTG0_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg1_phypll_pixel_rate_cntl = REG_READ(OTG1_PHYPLL_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg1_pixel_rate_cntl = REG_READ(OTG1_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg2_phypll_pixel_rate_cntl = REG_READ(OTG2_PHYPLL_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg2_pixel_rate_cntl = REG_READ(OTG2_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg3_phypll_pixel_rate_cntl = REG_READ(OTG3_PHYPLL_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;otg3_pixel_rate_cntl = REG_READ(OTG3_PIXEL_RATE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phyasymclk_clock_cntl = REG_READ(PHYASYMCLK_CLOCK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phybsymclk_clock_cntl = REG_READ(PHYBSYMCLK_CLOCK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phycsymclk_clock_cntl = REG_READ(PHYCSYMCLK_CLOCK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phydsymclk_clock_cntl = REG_READ(PHYDSYMCLK_CLOCK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phyesymclk_clock_cntl = REG_READ(PHYESYMCLK_CLOCK_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phyplla_pixclk_resync_cntl = REG_READ(PHYPLLA_PIXCLK_RESYNC_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phypllb_pixclk_resync_cntl = REG_READ(PHYPLLB_PIXCLK_RESYNC_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phypllc_pixclk_resync_cntl = REG_READ(PHYPLLC_PIXCLK_RESYNC_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phyplld_pixclk_resync_cntl = REG_READ(PHYPLLD_PIXCLK_RESYNC_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;phyplle_pixclk_resync_cntl = REG_READ(PHYPLLE_PIXCLK_RESYNC_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;refclk_cgtt_blk_ctrl_reg = REG_READ(REFCLK_CGTT_BLK_CTRL_REG);</div><div class='add'>+	dccg_reg_state-&gt;socclk_cgtt_blk_ctrl_reg = REG_READ(SOCCLK_CGTT_BLK_CTRL_REG);</div><div class='add'>+	dccg_reg_state-&gt;symclk_cgtt_blk_ctrl_reg = REG_READ(SYMCLK_CGTT_BLK_CTRL_REG);</div><div class='add'>+	dccg_reg_state-&gt;symclk_psp_cntl = REG_READ(SYMCLK_PSP_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;symclk32_le_cntl = REG_READ(SYMCLK32_LE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;symclk32_se_cntl = REG_READ(SYMCLK32_SE_CNTL);</div><div class='add'>+	dccg_reg_state-&gt;symclka_clock_enable = REG_READ(SYMCLKA_CLOCK_ENABLE);</div><div class='add'>+	dccg_reg_state-&gt;symclkb_clock_enable = REG_READ(SYMCLKB_CLOCK_ENABLE);</div><div class='add'>+	dccg_reg_state-&gt;symclkc_clock_enable = REG_READ(SYMCLKC_CLOCK_ENABLE);</div><div class='add'>+	dccg_reg_state-&gt;symclkd_clock_enable = REG_READ(SYMCLKD_CLOCK_ENABLE);</div><div class='add'>+	dccg_reg_state-&gt;symclke_clock_enable = REG_READ(SYMCLKE_CLOCK_ENABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct dccg_funcs dccg31_funcs = {</div><div class='ctx'> 	.update_dpp_dto = dccg31_update_dpp_dto,</div><div class='ctx'> 	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,</div><div class='hunk'>@@ -727,6 +849,7 @@ static const struct dccg_funcs dccg31_funcs = {</div><div class='ctx'> 	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,</div><div class='ctx'> 	.disable_dsc = dccg31_disable_dscclk,</div><div class='ctx'> 	.enable_dsc = dccg31_enable_dscclk,</div><div class='add'>+	.dccg_read_reg_state = dccg31_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dccg *dccg31_create(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h<br/>index e3caaacf7493..bf659920d4cc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h</a></div><div class='hunk'>@@ -34,12 +34,14 @@</div><div class='ctx'> 	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\</div><div class='ctx'> 	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\</div><div class='ctx'> 	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\</div><div class='add'>+	DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\</div><div class='ctx'> 	SR(PHYASYMCLK_CLOCK_CNTL),\</div><div class='ctx'> 	SR(PHYBSYMCLK_CLOCK_CNTL),\</div><div class='ctx'> 	SR(PHYCSYMCLK_CLOCK_CNTL),\</div><div class='ctx'> 	SR(PHYDSYMCLK_CLOCK_CNTL),\</div><div class='ctx'> 	SR(PHYESYMCLK_CLOCK_CNTL),\</div><div class='ctx'> 	SR(DPSTREAMCLK_CNTL),\</div><div class='add'>+	SR(HDMISTREAMCLK_CNTL),\</div><div class='ctx'> 	SR(SYMCLK32_SE_CNTL),\</div><div class='ctx'> 	SR(SYMCLK32_LE_CNTL),\</div><div class='ctx'> 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\</div><div class='hunk'>@@ -78,6 +80,8 @@</div><div class='ctx'> 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\</div><div class='ctx'> 	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\</div><div class='hunk'>@@ -92,6 +96,8 @@</div><div class='ctx'> 	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_DTO_FORCE_DIS, mask_sh),\</div><div class='ctx'> 	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\</div><div class='hunk'>@@ -126,7 +132,7 @@</div><div class='ctx'> 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\</div><div class='del'>-	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \</div><div class='add'>+	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\</div><div class='hunk'>@@ -230,4 +236,6 @@ void dccg31_disable_dscclk(struct dccg *dccg, int inst);</div><div class='ctx'> </div><div class='ctx'> void dccg31_enable_dscclk(struct dccg *dccg, int inst);</div><div class='ctx'> </div><div class='add'>+void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);</div><div class='add'>+</div><div class='ctx'> #endif //__DCN31_DCCG_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c<br/>index 17a1174b8d80..ef3db6beba25 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c</a></div><div class='hunk'>@@ -58,8 +58,8 @@ static void dccg314_trigger_dio_fifo_resync(</div><div class='ctx'> static void dccg314_get_pixel_rate_div(</div><div class='ctx'> 		struct dccg *dccg,</div><div class='ctx'> 		uint32_t otg_inst,</div><div class='del'>-		enum pixel_rate_div *k1,</div><div class='del'>-		enum pixel_rate_div *k2)</div><div class='add'>+		uint32_t *k1,</div><div class='add'>+		uint32_t *k2)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='ctx'> 	uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;</div><div class='hunk'>@@ -93,8 +93,8 @@ static void dccg314_get_pixel_rate_div(</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	*k1 = (enum pixel_rate_div)val_k1;</div><div class='del'>-	*k2 = (enum pixel_rate_div)val_k2;</div><div class='add'>+	*k1 = val_k1;</div><div class='add'>+	*k2 = val_k2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dccg314_set_pixel_rate_div(</div><div class='hunk'>@@ -104,7 +104,8 @@ static void dccg314_set_pixel_rate_div(</div><div class='ctx'> 		enum pixel_rate_div k2)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-	enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA;</div><div class='add'>+	uint32_t cur_k1 = PIXEL_RATE_DIV_NA;</div><div class='add'>+	uint32_t cur_k2 = PIXEL_RATE_DIV_NA;</div><div class='ctx'> </div><div class='ctx'> 	// Don't program 0xF into the register field. Not valid since</div><div class='ctx'> 	// K1 / K2 field is only 1 / 2 bits wide</div><div class='hunk'>@@ -373,9 +374,11 @@ static const struct dccg_funcs dccg314_funcs = {</div><div class='ctx'> 	.disable_dsc = dccg31_disable_dscclk,</div><div class='ctx'> 	.enable_dsc = dccg31_enable_dscclk,</div><div class='ctx'> 	.set_pixel_rate_div = dccg314_set_pixel_rate_div,</div><div class='add'>+	.get_pixel_rate_div = dccg314_get_pixel_rate_div,</div><div class='ctx'> 	.trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync,</div><div class='ctx'> 	.set_valid_pixel_rate = dccg314_set_valid_pixel_rate,</div><div class='del'>-	.set_dtbclk_p_src = dccg314_set_dtbclk_p_src</div><div class='add'>+	.set_dtbclk_p_src = dccg314_set_dtbclk_p_src,</div><div class='add'>+	.dccg_read_reg_state = dccg31_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dccg *dccg314_create(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h<br/>index 60ea1d248deb..a609635f35db 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h</a></div><div class='hunk'>@@ -74,8 +74,7 @@</div><div class='ctx'> 	SR(DCCG_GATE_DISABLE_CNTL3),\</div><div class='ctx'> 	SR(HDMISTREAMCLK0_DTO_PARAM),\</div><div class='ctx'> 	SR(OTG_PIXEL_RATE_DIV),\</div><div class='del'>-	SR(DTBCLK_P_CNTL),\</div><div class='del'>-	SR(DCCG_AUDIO_DTO_SOURCE)</div><div class='add'>+	SR(DTBCLK_P_CNTL)</div><div class='ctx'> </div><div class='ctx'> #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \</div><div class='ctx'> 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c<br/>index 036d05468d76..21a6ca5ca192 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c</a></div><div class='hunk'>@@ -58,8 +58,8 @@ static void dccg32_trigger_dio_fifo_resync(</div><div class='ctx'> static void dccg32_get_pixel_rate_div(</div><div class='ctx'> 		struct dccg *dccg,</div><div class='ctx'> 		uint32_t otg_inst,</div><div class='del'>-		enum pixel_rate_div *k1,</div><div class='del'>-		enum pixel_rate_div *k2)</div><div class='add'>+		uint32_t *k1,</div><div class='add'>+		uint32_t *k2)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='ctx'> 	uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;</div><div class='hunk'>@@ -93,8 +93,8 @@ static void dccg32_get_pixel_rate_div(</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	*k1 = (enum pixel_rate_div)val_k1;</div><div class='del'>-	*k2 = (enum pixel_rate_div)val_k2;</div><div class='add'>+	*k1 = val_k1;</div><div class='add'>+	*k2 = val_k2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dccg32_set_pixel_rate_div(</div><div class='hunk'>@@ -104,8 +104,8 @@ static void dccg32_set_pixel_rate_div(</div><div class='ctx'> 		enum pixel_rate_div k2)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA;</div><div class='add'>+	uint32_t cur_k1 = PIXEL_RATE_DIV_NA;</div><div class='add'>+	uint32_t cur_k2 = PIXEL_RATE_DIV_NA;</div><div class='ctx'> </div><div class='ctx'> 	// Don't program 0xF into the register field. Not valid since</div><div class='ctx'> 	// K1 / K2 field is only 1 / 2 bits wide</div><div class='hunk'>@@ -344,6 +344,7 @@ static const struct dccg_funcs dccg32_funcs = {</div><div class='ctx'> 	.otg_add_pixel = dccg32_otg_add_pixel,</div><div class='ctx'> 	.otg_drop_pixel = dccg32_otg_drop_pixel,</div><div class='ctx'> 	.set_pixel_rate_div = dccg32_set_pixel_rate_div,</div><div class='add'>+	.get_pixel_rate_div = dccg32_get_pixel_rate_div,</div><div class='ctx'> 	.trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync,</div><div class='ctx'> 	.set_dtbclk_p_src = dccg32_set_dtbclk_p_src,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h<br/>index cf5508718122..cf5508718122 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c<br/>new file mode 100644<br/>index 000000000000..bd2f528137b2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c</a></div><div class='hunk'>@@ -0,0 +1,2486 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "dcn35_dccg.h"</div><div class='add'>+</div><div class='add'>+#define TO_DCN_DCCG(dccg)\</div><div class='add'>+	container_of(dccg, struct dcn_dccg, base)</div><div class='add'>+</div><div class='add'>+#define REG(reg) \</div><div class='add'>+	(dccg_dcn-&gt;regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	dccg_dcn-&gt;dccg_shift-&gt;field_name, dccg_dcn-&gt;dccg_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	dccg_dcn-&gt;base.ctx</div><div class='add'>+#include "logger_types.h"</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dccg-&gt;ctx-&gt;logger</div><div class='add'>+</div><div class='add'>+enum symclk_fe_source {</div><div class='add'>+	SYMCLK_FE_SYMCLK_A = 0,	// Select functional clock from backend symclk A</div><div class='add'>+	SYMCLK_FE_SYMCLK_B,</div><div class='add'>+	SYMCLK_FE_SYMCLK_C,</div><div class='add'>+	SYMCLK_FE_SYMCLK_D,</div><div class='add'>+	SYMCLK_FE_SYMCLK_E,</div><div class='add'>+	SYMCLK_FE_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum symclk_be_source {</div><div class='add'>+	SYMCLK_BE_PHYCLK = 0,	// Select phy clk when sym_clk_enable = 1</div><div class='add'>+	SYMCLK_BE_DPIACLK_810 = 4,</div><div class='add'>+	SYMCLK_BE_DPIACLK_162 = 5,</div><div class='add'>+	SYMCLK_BE_DPIACLK_540 = 6,</div><div class='add'>+	SYMCLK_BE_DPIACLK_270 = 7,</div><div class='add'>+	SYMCLK_BE_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum physymclk_source {</div><div class='add'>+	PHYSYMCLK_PHYCLK = 0,		// Select symclk as source of clock which is output to PHY through DCIO.</div><div class='add'>+	PHYSYMCLK_PHYD18CLK,		// Select phyd18clk as the source of clock which is output to PHY through DCIO.</div><div class='add'>+	PHYSYMCLK_PHYD32CLK,		// Select phyd32clk as the source of clock which is output to PHY through DCIO.</div><div class='add'>+	PHYSYMCLK_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dtbclk_source {</div><div class='add'>+	DTBCLK_DPREFCLK = 0,		// Selects source for DTBCLK_P# as DPREFCLK (src sel 0 and 1 are same)</div><div class='add'>+	DTBCLK_DPREFCLK_0,			// Selects source for DTBCLK_P# as DPREFCLK (src sel 0 and 1 are same)</div><div class='add'>+	DTBCLK_DTBCLK0,				// Selects source for DTBCLK_P# as DTBCLK0</div><div class='add'>+	DTBCLK_DTBCLK1,				// Selects source for DTBCLK_P# as DTBCLK0</div><div class='add'>+	DTBCLK_REFCLK = 0xFF,		// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dppclk_clock_source {</div><div class='add'>+	DPP_REFCLK = 0,				// refclk is selected</div><div class='add'>+	DPP_DCCG_DTO,				// Functional clock selected is DTO tuned DPPCLK</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dp_stream_clk_source {</div><div class='add'>+	DP_STREAM_DTBCLK_P0 = 0,	// Selects functional for DP_STREAM_CLK as DTBCLK_P#</div><div class='add'>+	DP_STREAM_DTBCLK_P1,</div><div class='add'>+	DP_STREAM_DTBCLK_P2,</div><div class='add'>+	DP_STREAM_DTBCLK_P3,</div><div class='add'>+	DP_STREAM_DTBCLK_P4,</div><div class='add'>+	DP_STREAM_DTBCLK_P5,</div><div class='add'>+	DP_STREAM_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hdmi_char_clk {</div><div class='add'>+	HDMI_CHAR_PHYAD18CLK = 0,	// Selects functional for hdmi_char_clk as UNIPHYA PHYD18CLK</div><div class='add'>+	HDMI_CHAR_PHYBD18CLK,</div><div class='add'>+	HDMI_CHAR_PHYCD18CLK,</div><div class='add'>+	HDMI_CHAR_PHYDD18CLK,</div><div class='add'>+	HDMI_CHAR_PHYED18CLK,</div><div class='add'>+	HDMI_CHAR_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hdmi_stream_clk_source {</div><div class='add'>+	HDMI_STREAM_DTBCLK_P0 = 0,	// Selects functional for HDMI_STREAM_CLK as DTBCLK_P#</div><div class='add'>+	HDMI_STREAM_DTBCLK_P1,</div><div class='add'>+	HDMI_STREAM_DTBCLK_P2,</div><div class='add'>+	HDMI_STREAM_DTBCLK_P3,</div><div class='add'>+	HDMI_STREAM_DTBCLK_P4,</div><div class='add'>+	HDMI_STREAM_DTBCLK_P5,</div><div class='add'>+	HDMI_STREAM_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum symclk32_se_clk_source {</div><div class='add'>+	SYMCLK32_SE_PHYAD32CLK = 0,	// Selects functional for SYMCLK32 as UNIPHYA PHYD32CLK</div><div class='add'>+	SYMCLK32_SE_PHYBD32CLK,</div><div class='add'>+	SYMCLK32_SE_PHYCD32CLK,</div><div class='add'>+	SYMCLK32_SE_PHYDD32CLK,</div><div class='add'>+	SYMCLK32_SE_PHYED32CLK,</div><div class='add'>+	SYMCLK32_SE_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum symclk32_le_clk_source {</div><div class='add'>+	SYMCLK32_LE_PHYAD32CLK = 0,	// Selects functional for SYMCLK32 as UNIPHYA PHYD32CLK</div><div class='add'>+	SYMCLK32_LE_PHYBD32CLK,</div><div class='add'>+	SYMCLK32_LE_PHYCD32CLK,</div><div class='add'>+	SYMCLK32_LE_PHYDD32CLK,</div><div class='add'>+	SYMCLK32_LE_PHYED32CLK,</div><div class='add'>+	SYMCLK32_LE_REFCLK = 0xFF,	// Arbitrary value to pass refclk selection in software</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dsc_clk_source {</div><div class='add'>+	DSC_CLK_REF_CLK = 0,			// Ref clock selected for DSC_CLK</div><div class='add'>+	DSC_DTO_TUNED_CK_GPU_DISCLK_3,	// DTO divided clock selected as functional clock</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dsc &amp;&amp; allow_rcg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for clock to ramp */</div><div class='add'>+	if (!allow_rcg)</div><div class='add'>+		udelay(10);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk32_se_rcg(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* SYMCLK32_ROOT_SE#_GATE_DISABLE will clock gate in DCCG */</div><div class='add'>+	/* SYMCLK32_SE#_GATE_DISABLE will clock gate in HPO only */</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				   SYMCLK32_SE0_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   SYMCLK32_ROOT_SE0_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				   SYMCLK32_SE1_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   SYMCLK32_ROOT_SE1_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				   SYMCLK32_SE2_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   SYMCLK32_ROOT_SE2_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				   SYMCLK32_SE3_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   SYMCLK32_ROOT_SE3_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk32_le_rcg(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				   SYMCLK32_LE0_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   SYMCLK32_ROOT_LE0_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				   SYMCLK32_LE1_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   SYMCLK32_ROOT_LE1_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_physymclk_rcg(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk_fe_rcg(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk_fe &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKA_FE_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKB_FE_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKC_FE_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKD_FE_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKE_FE_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk_be_rcg(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* TBD add symclk_be in rcg control bits */</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk_fe &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKA_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKA_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKB_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKB_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKC_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKC_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKD_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKD_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				   SYMCLKE_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   SYMCLKE_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpp &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpp &amp;&amp; allow_rcg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for clock to ramp */</div><div class='add'>+	if (!allow_rcg)</div><div class='add'>+		udelay(10);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dpstreamclk_rcg(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					 DPSTREAMCLK0_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+					 DPSTREAMCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					 DPSTREAMCLK1_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+					 DPSTREAMCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   DPSTREAMCLK2_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   DPSTREAMCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				   DPSTREAMCLK3_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+				   DPSTREAMCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_smclk32_se_rcg(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int inst,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se &amp;&amp; enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					 SYMCLK32_SE0_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+					 SYMCLK32_ROOT_SE0_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					 SYMCLK32_SE1_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+					 SYMCLK32_ROOT_SE1_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					 SYMCLK32_SE2_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+					 SYMCLK32_ROOT_SE2_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					 SYMCLK32_SE3_GATE_DISABLE, enable ? 0 : 1,</div><div class='add'>+					 SYMCLK32_ROOT_SE3_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* DSCCLK#_EN=0 switches to refclock from functional clock */</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk32_se_src_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum symclk32_se_clk_source src</div><div class='add'>+	)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+					 SYMCLK32_SE0_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,</div><div class='add'>+					 SYMCLK32_SE0_EN,  (src == SYMCLK32_SE_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+					 SYMCLK32_SE1_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,</div><div class='add'>+					 SYMCLK32_SE1_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+					 SYMCLK32_SE2_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,</div><div class='add'>+					 SYMCLK32_SE2_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+					 SYMCLK32_SE3_SRC_SEL, (src == SYMCLK32_SE_REFCLK) ? 0 : src,</div><div class='add'>+					 SYMCLK32_SE3_EN, (src == SYMCLK32_SE_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t en;</div><div class='add'>+	uint32_t src_sel;</div><div class='add'>+</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, &amp;src_sel, SYMCLK32_SE3_EN, &amp;en);</div><div class='add'>+</div><div class='add'>+	if (en == 1 &amp;&amp; src_sel == symclk_32_le_inst)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk32_le_src_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum symclk32_le_clk_source src)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+					 SYMCLK32_LE0_SRC_SEL, (src == SYMCLK32_LE_REFCLK) ? 0 : src,</div><div class='add'>+					 SYMCLK32_LE0_EN, (src == SYMCLK32_LE_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+					 SYMCLK32_LE1_SRC_SEL, (src == SYMCLK32_LE_REFCLK) ? 0 : src,</div><div class='add'>+					 SYMCLK32_LE1_EN, (src == SYMCLK32_LE_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn35_set_dppclk_src_new(struct dccg *dccg,</div><div class='add'>+				 int inst, enum dppclk_clock_source src)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, src);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dtbclk_p_src_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	enum dtbclk_source src,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* If DTBCLK_P#_EN is 0 refclock is selected as functional clock</div><div class='add'>+	 * If DTBCLK_P#_EN is 1 functional clock is selected as DTBCLK_P#_SRC_SEL</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					 DTBCLK_P0_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,</div><div class='add'>+					 DTBCLK_P0_EN, (src == DTBCLK_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					 DTBCLK_P1_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,</div><div class='add'>+					 DTBCLK_P1_EN, (src == DTBCLK_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					 DTBCLK_P2_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,</div><div class='add'>+					 DTBCLK_P2_EN, (src == DTBCLK_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					 DTBCLK_P3_SRC_SEL, (src == DTBCLK_REFCLK) ? 0 : src,</div><div class='add'>+					 DTBCLK_P3_EN, (src == DTBCLK_REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dpstreamclk_src_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	enum dp_stream_clk_source src,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : 1,</div><div class='add'>+					 DPSTREAMCLK0_SRC_SEL,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : 1,</div><div class='add'>+					 DPSTREAMCLK1_SRC_SEL,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : src);</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : 1,</div><div class='add'>+					 DPSTREAMCLK2_SRC_SEL,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : src);</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : 1,</div><div class='add'>+					 DPSTREAMCLK3_SRC_SEL,</div><div class='add'>+					 (src == DP_STREAM_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_physymclk_src_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	enum physymclk_source src,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : 1,</div><div class='add'>+					 PHYASYMCLK_SRC_SEL,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : 1,</div><div class='add'>+					 PHYBSYMCLK_SRC_SEL,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : 1,</div><div class='add'>+					 PHYCSYMCLK_SRC_SEL,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : 1,</div><div class='add'>+					 PHYDSYMCLK_SRC_SEL,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : 1,</div><div class='add'>+					 PHYESYMCLK_SRC_SEL,</div><div class='add'>+					 (src == PHYSYMCLK_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk_be_src_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	enum symclk_be_source src,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKA_CLOCK_ENABLE, (src == SYMCLK_BE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKA_SRC_SEL, (src == SYMCLK_BE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKB_CLOCK_ENABLE, (src == SYMCLK_BE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKB_SRC_SEL, (src == SYMCLK_BE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKC_CLOCK_ENABLE, (src == SYMCLK_BE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKC_SRC_SEL, (src == SYMCLK_BE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKD_CLOCK_ENABLE, (src == SYMCLK_BE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKD_SRC_SEL, (src == SYMCLK_BE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKE_CLOCK_ENABLE, (src == SYMCLK_BE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKE_SRC_SEL, (src == SYMCLK_BE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dccg35_is_symclk_fe_src_functional_be(struct dccg *dccg,</div><div class='add'>+												 int symclk_fe_inst,</div><div class='add'>+												 int symclk_be_inst)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	uint32_t en = 0;</div><div class='add'>+	uint32_t src_sel = 0;</div><div class='add'>+</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (symclk_fe_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, &amp;src_sel, SYMCLKA_FE_EN, &amp;en);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, &amp;src_sel, SYMCLKB_FE_EN, &amp;en);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, &amp;src_sel, SYMCLKC_FE_EN, &amp;en);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, &amp;src_sel, SYMCLKD_FE_EN, &amp;en);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, &amp;src_sel, SYMCLKE_FE_EN, &amp;en);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (en == 1 &amp;&amp; src_sel == symclk_be_inst)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKA_FE_EN, (src == SYMCLK_FE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKA_FE_SRC_SEL, (src == SYMCLK_FE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKB_FE_EN, (src == SYMCLK_FE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKB_FE_SRC_SEL, (src == SYMCLK_FE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKC_FE_EN, (src == SYMCLK_FE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKC_FE_SRC_SEL, (src == SYMCLK_FE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKD_FE_EN, (src == SYMCLK_FE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKD_FE_SRC_SEL, (src == SYMCLK_FE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,</div><div class='add'>+					 SYMCLKE_FE_EN, (src == SYMCLK_FE_REFCLK) ? 0 : 1,</div><div class='add'>+					 SYMCLKE_FE_SRC_SEL, (src == SYMCLK_FE_REFCLK) ? 0 : src);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t enable = 0;</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_GET(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				SYMCLKA_FE_ROOT_GATE_DISABLE, &amp;enable);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_GET(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				SYMCLKB_FE_ROOT_GATE_DISABLE, &amp;enable);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_GET(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				SYMCLKC_FE_ROOT_GATE_DISABLE, &amp;enable);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_GET(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				SYMCLKD_FE_ROOT_GATE_DISABLE, &amp;enable);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_GET(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				SYMCLKE_FE_ROOT_GATE_DISABLE, &amp;enable);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return enable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)</div><div class='add'>+{</div><div class='add'>+	uint32_t disable_l1 = 0;</div><div class='add'>+	uint32_t disable_l2 = 0;</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_GET_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				  SYMCLK32_SE0_GATE_DISABLE, &amp;disable_l1,</div><div class='add'>+				  SYMCLK32_ROOT_SE0_GATE_DISABLE, &amp;disable_l2);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_GET_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				  SYMCLK32_SE1_GATE_DISABLE, &amp;disable_l1,</div><div class='add'>+				  SYMCLK32_ROOT_SE1_GATE_DISABLE, &amp;disable_l2);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_GET_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				  SYMCLK32_SE2_GATE_DISABLE, &amp;disable_l1,</div><div class='add'>+				  SYMCLK32_ROOT_SE2_GATE_DISABLE, &amp;disable_l2);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_GET_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+				  SYMCLK32_SE3_GATE_DISABLE, &amp;disable_l1,</div><div class='add'>+				  SYMCLK32_ROOT_SE3_GATE_DISABLE, &amp;disable_l2);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* return true if either block level or DCCG level gating is active */</div><div class='add'>+	return (disable_l1 | disable_l2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk_fe_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum symclk_fe_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_symclk_fe_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_symclk_fe_src_new(dccg, src, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk_fe_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_symclk_fe_src_new(dccg, SYMCLK_FE_REFCLK, inst);</div><div class='add'>+	dccg35_set_symclk_fe_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk_be_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum symclk_be_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_symclk_be_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_symclk_be_src_new(dccg, inst, src);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk_be_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Switch from functional clock to refclock */</div><div class='add'>+	dccg35_set_symclk_be_src_new(dccg, inst, SYMCLK_BE_REFCLK);</div><div class='add'>+</div><div class='add'>+	/* Check if any other SE connected LE and disable them */</div><div class='add'>+	for (i = 0; i &lt; 4; i++) {</div><div class='add'>+		/* Make sure FE is not already in RCG */</div><div class='add'>+		if (dccg35_is_fe_rcg(dccg, i) == 0) {</div><div class='add'>+			if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))</div><div class='add'>+				dccg35_disable_symclk_fe_new(dccg, i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/* Safe to RCG SYMCLK*/</div><div class='add'>+	dccg35_set_symclk_be_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk32_se_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum symclk32_se_clk_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_symclk32_se_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_symclk32_se_src_new(dccg, inst, src);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk32_se_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);</div><div class='add'>+	dccg35_set_symclk32_se_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk32_le_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum symclk32_le_clk_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_symclk32_le_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_symclk32_le_src_new(dccg, inst, src);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk32_le_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Switch from functional clock to refclock */</div><div class='add'>+	dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);</div><div class='add'>+</div><div class='add'>+	/* Check if any SE are connected and disable SE as well */</div><div class='add'>+	for (i = 0; i &lt; 4; i++) {</div><div class='add'>+		/* Make sure FE is not already in RCG */</div><div class='add'>+		if (dccg35_is_symclk32_se_rcg(dccg, i) == 0) {</div><div class='add'>+			/* Disable and SE connected to this LE before RCG */</div><div class='add'>+			if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))</div><div class='add'>+				dccg35_disable_symclk32_se_new(dccg, i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/* Safe to RCG SYM32_LE*/</div><div class='add'>+	dccg35_set_symclk32_le_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_physymclk_new(struct dccg *dccg,</div><div class='add'>+					int inst,</div><div class='add'>+					enum physymclk_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_physymclk_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_physymclk_src_new(dccg, src, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_physymclk_new(struct dccg *dccg,</div><div class='add'>+										 int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);</div><div class='add'>+	dccg35_set_physymclk_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_dpp_clk_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum dppclk_clock_source src)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	/* Sanitize inst before use in array de-ref */</div><div class='add'>+	if (inst &lt; 0) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	dccg35_set_dppclk_rcg(dccg, inst, false);</div><div class='add'>+	dcn35_set_dppclk_src_new(dccg, inst, src);</div><div class='add'>+	/* Switch DPP clock to DTO */</div><div class='add'>+	REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,</div><div class='add'>+			  DPPCLK0_DTO_PHASE, 0xFF,</div><div class='add'>+			  DPPCLK0_DTO_MODULO, 0xFF);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_dpp_clk_new(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	/* Sanitize inst before use in array de-ref */</div><div class='add'>+	if (inst &lt; 0) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	dcn35_set_dppclk_src_new(dccg, inst, DPP_REFCLK);</div><div class='add'>+	REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,</div><div class='add'>+			  DPPCLK0_DTO_PHASE, 0,</div><div class='add'>+			  DPPCLK0_DTO_MODULO, 1);</div><div class='add'>+	dccg35_set_dppclk_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_dscclk_new(struct dccg *dccg,</div><div class='add'>+									  int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);</div><div class='add'>+	dccg35_set_dsc_clk_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_dscclk_new(struct dccg *dccg,</div><div class='add'>+									 int inst,</div><div class='add'>+									 enum dsc_clk_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dsc_clk_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_dsc_clk_src_new(dccg, inst, src);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_dtbclk_p_new(struct dccg *dccg,</div><div class='add'>+									   enum dtbclk_source src,</div><div class='add'>+									   int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dtbclk_p_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_dtbclk_p_src_new(dccg, src, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_dtbclk_p_new(struct dccg *dccg,</div><div class='add'>+										int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);</div><div class='add'>+	dccg35_set_dtbclk_p_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_dpstreamclk_new(struct dccg *dccg,</div><div class='add'>+										  int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);</div><div class='add'>+	dccg35_set_dpstreamclk_rcg(dccg, inst, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_dpstreamclk_new(struct dccg *dccg,</div><div class='add'>+										   enum dp_stream_clk_source src,</div><div class='add'>+										   int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dpstreamclk_rcg(dccg, inst, false);</div><div class='add'>+	dccg35_set_dpstreamclk_src_new(dccg, src, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	uint32_t dispclk_rdivider_value = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &amp;dispclk_rdivider_value);</div><div class='add'>+	if (dispclk_rdivider_value != 0)</div><div class='add'>+		REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);</div><div class='add'>+}</div><div class='add'>+static void dccg35_wait_for_dentist_change_done(</div><div class='add'>+	struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);</div><div class='add'>+	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn35_set_dppclk_enable(struct dccg *dccg,</div><div class='add'>+				 uint32_t dpp_inst, uint32_t enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	switch (dpp_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,</div><div class='add'>+				  int req_dppclk)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;dpp_clock_gated[dpp_inst]) {</div><div class='add'>+		/*</div><div class='add'>+		 * Do not update the DPPCLK DTO if the clock is stopped.</div><div class='add'>+		 */</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ref_dppclk &amp;&amp; req_dppclk) {</div><div class='add'>+		int ref_dppclk = dccg-&gt;ref_dppclk;</div><div class='add'>+		int modulo, phase;</div><div class='add'>+</div><div class='add'>+		// phase / modulo = dpp pipe clk / dpp global clk</div><div class='add'>+		modulo = 0xff;   // use FF at the end</div><div class='add'>+		phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;</div><div class='add'>+</div><div class='add'>+		if (phase &gt; 0xff) {</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			phase = 0xff;</div><div class='add'>+		}</div><div class='add'>+		dccg35_set_dppclk_rcg(dccg, dpp_inst, false);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='add'>+				DPPCLK0_DTO_PHASE, phase,</div><div class='add'>+				DPPCLK0_DTO_MODULO, modulo);</div><div class='add'>+</div><div class='add'>+		dcn35_set_dppclk_enable(dccg, dpp_inst, true);</div><div class='add'>+	} else {</div><div class='add'>+		dcn35_set_dppclk_enable(dccg, dpp_inst, false);</div><div class='add'>+		dccg35_set_dppclk_rcg(dccg, dpp_inst, true);</div><div class='add'>+	}</div><div class='add'>+	udelay(10);</div><div class='add'>+	dccg-&gt;pipe_dppclk_khz[dpp_inst] = req_dppclk;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,</div><div class='add'>+		 uint32_t dpp_inst, uint32_t disallow_rcg)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpp &amp;&amp; !disallow_rcg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	switch (dpp_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, disallow_rcg);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, disallow_rcg);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, disallow_rcg);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, disallow_rcg);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for clock to ramp */</div><div class='add'>+	if (disallow_rcg)</div><div class='add'>+		udelay(10);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_get_pixel_rate_div(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		uint32_t *k1,</div><div class='add'>+		uint32_t *k2)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;</div><div class='add'>+</div><div class='add'>+	*k1 = PIXEL_RATE_DIV_NA;</div><div class='add'>+	*k2 = PIXEL_RATE_DIV_NA;</div><div class='add'>+</div><div class='add'>+	switch (otg_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG0_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='add'>+			OTG0_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG1_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='add'>+			OTG1_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG2_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='add'>+			OTG2_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG3_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='add'>+			OTG3_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*k1 = val_k1;</div><div class='add'>+	*k2 = val_k2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_pixel_rate_div(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		enum pixel_rate_div k1,</div><div class='add'>+		enum pixel_rate_div k2)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	uint32_t cur_k1 = PIXEL_RATE_DIV_NA;</div><div class='add'>+	uint32_t cur_k2 = PIXEL_RATE_DIV_NA;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	// Don't program 0xF into the register field. Not valid since</div><div class='add'>+	// K1 / K2 field is only 1 / 2 bits wide</div><div class='add'>+	if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dccg35_get_pixel_rate_div(dccg, otg_inst, &amp;cur_k1, &amp;cur_k2);</div><div class='add'>+	if (k1 == cur_k1 &amp;&amp; k2 == cur_k2)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (otg_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG0_PIXEL_RATE_DIVK1, k1,</div><div class='add'>+				OTG0_PIXEL_RATE_DIVK2, k2);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG1_PIXEL_RATE_DIVK1, k1,</div><div class='add'>+				OTG1_PIXEL_RATE_DIVK2, k2);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG2_PIXEL_RATE_DIVK1, k1,</div><div class='add'>+				OTG2_PIXEL_RATE_DIVK2, k2);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG3_PIXEL_RATE_DIVK1, k1,</div><div class='add'>+				OTG3_PIXEL_RATE_DIVK2, k2);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	if (otg_inst &lt; 4)</div><div class='add'>+		dccg35_wait_for_dentist_change_done(dccg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dtbclk_p_src(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		uint32_t otg_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	uint32_t p_src_sel = 0; /* selects dprefclk */</div><div class='add'>+	if (src == DTBCLK0)</div><div class='add'>+		p_src_sel = 2;  /* selects dtbclk0 */</div><div class='add'>+</div><div class='add'>+	switch (otg_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P0_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P0_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P0_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P1_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P1_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P1_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P2_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P2_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P2_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P3_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P3_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P3_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Controls the generation of pixel valid for OTG in (OTG -&gt; HPO case) */</div><div class='add'>+static void dccg35_set_dtbclk_dto(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		const struct dtbclk_dto_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	/* DTO Output Rate / Pixel Rate = 1/4 */</div><div class='add'>+	int req_dtbclk_khz = params-&gt;pixclk_khz / 4;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;ref_dtbclk_khz &amp;&amp; req_dtbclk_khz) {</div><div class='add'>+		uint32_t modulo, phase;</div><div class='add'>+</div><div class='add'>+		switch (params-&gt;otg_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// phase / modulo = dtbclk / dtbclk ref</div><div class='add'>+		modulo = params-&gt;ref_dtbclk_khz * 1000;</div><div class='add'>+		phase = req_dtbclk_khz * 1000;</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_MODULO[params-&gt;otg_inst], modulo);</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_PHASE[params-&gt;otg_inst], phase);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+				DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 1);</div><div class='add'>+</div><div class='add'>+		REG_WAIT(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+				DTBCLKDTO_ENABLE_STATUS[params-&gt;otg_inst], 1,</div><div class='add'>+				1, 100);</div><div class='add'>+</div><div class='add'>+		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */</div><div class='add'>+		dccg35_set_pixel_rate_div(dccg, params-&gt;otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);</div><div class='add'>+</div><div class='add'>+		/* The recommended programming sequence to enable DTBCLK DTO to generate</div><div class='add'>+		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should</div><div class='add'>+		 * be set only after DTO is enabled.</div><div class='add'>+		 * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the</div><div class='add'>+		 * programming is handled in program_pix_clk() regardless, so it can be removed from here.</div><div class='add'>+		 */</div><div class='add'>+		DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO enabled: pixclk_khz=%d, ref_dtbclk_khz=%d, req_dtbclk_khz=%d, phase=%d, modulo=%d\n",</div><div class='add'>+				__func__, params-&gt;otg_inst, params-&gt;pixclk_khz,</div><div class='add'>+				params-&gt;ref_dtbclk_khz, req_dtbclk_khz, phase, modulo);</div><div class='add'>+</div><div class='add'>+	} else if (!params-&gt;ref_dtbclk_khz &amp;&amp; !req_dtbclk_khz) {</div><div class='add'>+		switch (params-&gt;otg_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the</div><div class='add'>+		 * programming is handled in program_pix_clk() regardless, so it can be removed from here.</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+				DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 0);</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_MODULO[params-&gt;otg_inst], 0);</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_PHASE[params-&gt;otg_inst], 0);</div><div class='add'>+</div><div class='add'>+		DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO disabled\n", __func__, params-&gt;otg_inst);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dpstreamclk(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		int otg_inst,</div><div class='add'>+		int dp_hpo_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* set the dtbclk_p source */</div><div class='add'>+	dccg35_set_dtbclk_p_src(dccg, src, otg_inst);</div><div class='add'>+</div><div class='add'>+	/* enabled to select one of the DTBCLKs for pipe */</div><div class='add'>+	switch (dp_hpo_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN,</div><div class='add'>+				(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,</div><div class='add'>+				(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,</div><div class='add'>+				(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,</div><div class='add'>+				(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_EN = %d, DPSTREAMCLK_SRC_SEL = %d\n",</div><div class='add'>+			__func__, dp_hpo_inst, (src == REFCLK) ? 0 : 1, otg_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dpstreamclk_root_clock_gating(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int dp_hpo_inst,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (dp_hpo_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, enable ? 1 : 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_ROOT_GATE_DISABLE = %d\n",</div><div class='add'>+			__func__, dp_hpo_inst, enable ? 1 : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dccg35_set_physymclk_root_clock_gating(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int phy_inst,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (phy_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+				PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE: %d\n", __func__, phy_inst, enable ? 0 : 1);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_physymclk(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int phy_inst,</div><div class='add'>+		enum physymclk_clock_source clk_src,</div><div class='add'>+		bool force_enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */</div><div class='add'>+	switch (phy_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYASYMCLK_EN, 1,</div><div class='add'>+					PHYASYMCLK_SRC_SEL, clk_src);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYASYMCLK_EN, 0,</div><div class='add'>+					PHYASYMCLK_SRC_SEL, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYBSYMCLK_EN, 1,</div><div class='add'>+					PHYBSYMCLK_SRC_SEL, clk_src);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYBSYMCLK_EN, 0,</div><div class='add'>+					PHYBSYMCLK_SRC_SEL, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYCSYMCLK_EN, 1,</div><div class='add'>+					PHYCSYMCLK_SRC_SEL, clk_src);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYCSYMCLK_EN, 0,</div><div class='add'>+					PHYCSYMCLK_SRC_SEL, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYDSYMCLK_EN, 1,</div><div class='add'>+					PHYDSYMCLK_SRC_SEL, clk_src);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYDSYMCLK_EN, 0,</div><div class='add'>+					PHYDSYMCLK_SRC_SEL, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYESYMCLK_EN, 1,</div><div class='add'>+					PHYESYMCLK_SRC_SEL, clk_src);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYESYMCLK_EN, 0,</div><div class='add'>+					PHYESYMCLK_SRC_SEL, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	DC_LOG_DEBUG("%s: phy_inst(%d) PHYxSYMCLK_EN = %d, PHYxSYMCLK_SRC_SEL = %d\n",</div><div class='add'>+			__func__, phy_inst, force_enable ? 1 : 0, clk_src);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_valid_pixel_rate(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int ref_dtbclk_khz,</div><div class='add'>+		int otg_inst,</div><div class='add'>+		int pixclk_khz)</div><div class='add'>+{</div><div class='add'>+	struct dtbclk_dto_params dto_params = {0};</div><div class='add'>+</div><div class='add'>+	dto_params.ref_dtbclk_khz = ref_dtbclk_khz;</div><div class='add'>+	dto_params.otg_inst = otg_inst;</div><div class='add'>+	dto_params.pixclk_khz = pixclk_khz;</div><div class='add'>+	dto_params.is_hdmi = true;</div><div class='add'>+</div><div class='add'>+	dccg35_set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_dpp_root_clock_control(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		unsigned int dpp_inst,</div><div class='add'>+		bool clock_on)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;dpp_clock_gated[dpp_inst] != clock_on)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (clock_on) {</div><div class='add'>+		dccg35_set_dppclk_rcg(dccg, dpp_inst, false);</div><div class='add'>+</div><div class='add'>+		/* turn off the DTO and leave phase/modulo at max */</div><div class='add'>+		dcn35_set_dppclk_enable(dccg, dpp_inst, 1);</div><div class='add'>+		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='add'>+			  DPPCLK0_DTO_PHASE, 0xFF,</div><div class='add'>+			  DPPCLK0_DTO_MODULO, 0xFF);</div><div class='add'>+	} else {</div><div class='add'>+		dcn35_set_dppclk_enable(dccg, dpp_inst, 0);</div><div class='add'>+		/* turn on the DTO to generate a 0hz clock */</div><div class='add'>+		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='add'>+			  DPPCLK0_DTO_PHASE, 0,</div><div class='add'>+			  DPPCLK0_DTO_MODULO, 1);</div><div class='add'>+		/*we have this in hwss: disable_plane*/</div><div class='add'>+		dccg35_set_dppclk_rcg(dccg, dpp_inst, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// wait for clock to fully ramp</div><div class='add'>+	udelay(10);</div><div class='add'>+</div><div class='add'>+	dccg-&gt;dpp_clock_gated[dpp_inst] = !clock_on;</div><div class='add'>+	DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk32_se(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int hpo_se_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* set refclk as the source for symclk32_se */</div><div class='add'>+	switch (hpo_se_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE0_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE0_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE0_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE1_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE1_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE1_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE2_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE2_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE2_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE3_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE3_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE3_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_init_cb(struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	(void)dccg;</div><div class='add'>+	/* Any RCG should be done when driver enter low power mode*/</div><div class='add'>+}</div><div class='add'>+void dccg35_init(struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	int otg_inst;</div><div class='add'>+	/* Set HPO stream encoder to use refclk to avoid case where PHY is</div><div class='add'>+	 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which</div><div class='add'>+	 * will cause DCN to hang.</div><div class='add'>+	 */</div><div class='add'>+	for (otg_inst = 0; otg_inst &lt; 4; otg_inst++)</div><div class='add'>+		dccg35_disable_symclk32_se(dccg, otg_inst);</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+		for (otg_inst = 0; otg_inst &lt; 2; otg_inst++) {</div><div class='add'>+			dccg31_disable_symclk32_le(dccg, otg_inst);</div><div class='add'>+			dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);</div><div class='add'>+			DC_LOG_DEBUG("%s: OTG%d SYMCLK32_LE disabled and root clock gating disabled\n",</div><div class='add'>+					__func__, otg_inst);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+//	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+//		for (otg_inst = 0; otg_inst &lt; 4; otg_inst++)</div><div class='add'>+//			dccg35_disable_symclk_se(dccg, otg_inst, otg_inst);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+		for (otg_inst = 0; otg_inst &lt; 4; otg_inst++) {</div><div class='add'>+			dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst,</div><div class='add'>+						otg_inst);</div><div class='add'>+			dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);</div><div class='add'>+			DC_LOG_DEBUG("%s: OTG%d DPSTREAMCLK disabled and root clock gating disabled\n",</div><div class='add'>+					__func__, otg_inst);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+	dccg35_enable_global_fgcg_rep(</div><div class='add'>+		dccg, dccg-&gt;ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits</div><div class='add'>+			      .dccg_global_fgcg_rep);*/</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_dscclk(struct dccg *dccg, int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	//Disable DTO</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,</div><div class='add'>+				DSCCLK0_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK0_DTO_MODULO, 0);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL,	DSCCLK0_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,</div><div class='add'>+				DSCCLK1_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK1_DTO_MODULO, 0);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,</div><div class='add'>+				DSCCLK2_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK2_DTO_MODULO, 0);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(DSCCLK3_DTO_PARAM,</div><div class='add'>+				DSCCLK3_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK3_DTO_MODULO, 0);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for clock to ramp */</div><div class='add'>+	udelay(10);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_dscclk(struct dccg *dccg,</div><div class='add'>+				int inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,</div><div class='add'>+				DSCCLK0_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK0_DTO_MODULO, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dsc)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,</div><div class='add'>+				DSCCLK1_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK1_DTO_MODULO, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dsc)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,</div><div class='add'>+				DSCCLK2_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK2_DTO_MODULO, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dsc)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK3_DTO_PARAM,</div><div class='add'>+				DSCCLK3_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK3_DTO_MODULO, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dsc)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for clock ramp */</div><div class='add'>+	udelay(10);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (link_enc_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKA_CLOCK_ENABLE, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKB_CLOCK_ENABLE, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKC_CLOCK_ENABLE, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKD_CLOCK_ENABLE, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE(SYMCLKE_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKE_CLOCK_ENABLE, 1);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (stream_enc_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKA_FE_EN, 1,</div><div class='add'>+				SYMCLKA_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKB_FE_EN, 1,</div><div class='add'>+				SYMCLKB_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKC_FE_EN, 1,</div><div class='add'>+				SYMCLKC_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKD_FE_EN, 1,</div><div class='add'>+				SYMCLKD_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKE_FE_EN, 1,</div><div class='add'>+				SYMCLKE_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*get other front end connected to this backend*/</div><div class='add'>+static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	uint8_t num_enabled_symclk_fe = 0;</div><div class='add'>+	uint32_t fe_clk_en[5] = {0}, be_clk_sel[5] = {0};</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &amp;fe_clk_en[0],</div><div class='add'>+		SYMCLKA_FE_SRC_SEL, &amp;be_clk_sel[0]);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &amp;fe_clk_en[1],</div><div class='add'>+		SYMCLKB_FE_SRC_SEL, &amp;be_clk_sel[1]);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &amp;fe_clk_en[2],</div><div class='add'>+		SYMCLKC_FE_SRC_SEL, &amp;be_clk_sel[2]);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(SYMCLKD_CLOCK_ENABLE,	SYMCLKD_FE_EN, &amp;fe_clk_en[3],</div><div class='add'>+		SYMCLKD_FE_SRC_SEL, &amp;be_clk_sel[3]);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(SYMCLKE_CLOCK_ENABLE,	SYMCLKE_FE_EN, &amp;fe_clk_en[4],</div><div class='add'>+		SYMCLKE_FE_SRC_SEL, &amp;be_clk_sel[4]);</div><div class='add'>+</div><div class='add'>+	uint8_t i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(fe_clk_en); i++) {</div><div class='add'>+		if (fe_clk_en[i] &amp;&amp; be_clk_sel[i] == link_enc_inst)</div><div class='add'>+			num_enabled_symclk_fe++;</div><div class='add'>+	}</div><div class='add'>+	return num_enabled_symclk_fe;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	uint8_t num_enabled_symclk_fe = 0;</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (stream_enc_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKA_FE_EN, 0,</div><div class='add'>+				SYMCLKA_FE_SRC_SEL, 0);</div><div class='add'>+//		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKB_FE_EN, 0,</div><div class='add'>+				SYMCLKB_FE_SRC_SEL, 0);</div><div class='add'>+//		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKC_FE_EN, 0,</div><div class='add'>+				SYMCLKC_FE_SRC_SEL, 0);</div><div class='add'>+//		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKD_FE_EN, 0,</div><div class='add'>+				SYMCLKD_FE_SRC_SEL, 0);</div><div class='add'>+//		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKE_FE_EN, 0,</div><div class='add'>+				SYMCLKE_FE_SRC_SEL, 0);</div><div class='add'>+//		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*check other enabled symclk fe connected to this be */</div><div class='add'>+	num_enabled_symclk_fe = dccg35_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst);</div><div class='add'>+	/*only turn off backend clk if other front end attached to this backend are all off,</div><div class='add'>+	 for mst, only turn off the backend if this is the last front end*/</div><div class='add'>+	if (num_enabled_symclk_fe == 0) {</div><div class='add'>+		switch (link_enc_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+					SYMCLKA_CLOCK_ENABLE, 0);</div><div class='add'>+//			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+					SYMCLKB_CLOCK_ENABLE, 0);</div><div class='add'>+//			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+					SYMCLKC_CLOCK_ENABLE, 0);</div><div class='add'>+//			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+					SYMCLKD_CLOCK_ENABLE, 0);</div><div class='add'>+//			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 4:</div><div class='add'>+			REG_UPDATE(SYMCLKE_CLOCK_ENABLE,</div><div class='add'>+					SYMCLKE_CLOCK_ENABLE, 0);</div><div class='add'>+//			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+//				REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dpstreamclk_cb(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		int otg_inst,</div><div class='add'>+		int dp_hpo_inst)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	enum dtbclk_source dtb_clk_src;</div><div class='add'>+	enum dp_stream_clk_source dp_stream_clk_src;</div><div class='add'>+</div><div class='add'>+	switch (src) {</div><div class='add'>+	case REFCLK:</div><div class='add'>+		dtb_clk_src = DTBCLK_REFCLK;</div><div class='add'>+		dp_stream_clk_src = DP_STREAM_REFCLK;</div><div class='add'>+		break;</div><div class='add'>+	case DPREFCLK:</div><div class='add'>+		dtb_clk_src = DTBCLK_DPREFCLK;</div><div class='add'>+		dp_stream_clk_src = (enum dp_stream_clk_source)otg_inst;</div><div class='add'>+		break;</div><div class='add'>+	case DTBCLK0:</div><div class='add'>+		dtb_clk_src = DTBCLK_DTBCLK0;</div><div class='add'>+		dp_stream_clk_src = (enum dp_stream_clk_source)otg_inst;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dtb_clk_src == DTBCLK_REFCLK &amp;&amp;</div><div class='add'>+		dp_stream_clk_src == DP_STREAM_REFCLK) {</div><div class='add'>+		dccg35_disable_dtbclk_p_new(dccg, otg_inst);</div><div class='add'>+		dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);</div><div class='add'>+	} else {</div><div class='add'>+		dccg35_enable_dtbclk_p_new(dccg, dtb_clk_src, otg_inst);</div><div class='add'>+		dccg35_enable_dpstreamclk_new(dccg,</div><div class='add'>+										dp_stream_clk_src,</div><div class='add'>+										dp_hpo_inst);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dpstreamclk_root_clock_gating_cb(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int dp_hpo_inst,</div><div class='add'>+	bool power_on)</div><div class='add'>+{</div><div class='add'>+	/* power_on set indicates we need to ungate</div><div class='add'>+	 * Currently called from optimize_bandwidth and prepare_bandwidth calls</div><div class='add'>+	 * Since clock source is not passed restore to refclock on ungate</div><div class='add'>+	 * Instance 0 is implied here since only one streamclock resource</div><div class='add'>+	 * Redundant as gating when enabled is acheived through set_dpstreamclk</div><div class='add'>+	 */</div><div class='add'>+	if (power_on)</div><div class='add'>+		dccg35_enable_dpstreamclk_new(dccg,</div><div class='add'>+										DP_STREAM_REFCLK,</div><div class='add'>+										dp_hpo_inst);</div><div class='add'>+	else</div><div class='add'>+		dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,</div><div class='add'>+				  int req_dppclk)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;dpp_clock_gated[dpp_inst]) {</div><div class='add'>+		/*</div><div class='add'>+		 * Do not update the DPPCLK DTO if the clock is stopped.</div><div class='add'>+		 */</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ref_dppclk &amp;&amp; req_dppclk) {</div><div class='add'>+		int ref_dppclk = dccg-&gt;ref_dppclk;</div><div class='add'>+		int modulo, phase;</div><div class='add'>+</div><div class='add'>+		// phase / modulo = dpp pipe clk / dpp global clk</div><div class='add'>+		modulo = 0xff;   // use FF at the end</div><div class='add'>+		phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;</div><div class='add'>+</div><div class='add'>+		if (phase &gt; 0xff) {</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			phase = 0xff;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Enable DPP CLK DTO output */</div><div class='add'>+		dccg35_enable_dpp_clk_new(dccg, dpp_inst, DPP_DCCG_DTO);</div><div class='add'>+</div><div class='add'>+		/* Program DTO */</div><div class='add'>+		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='add'>+				DPPCLK0_DTO_PHASE, phase,</div><div class='add'>+				DPPCLK0_DTO_MODULO, modulo);</div><div class='add'>+	} else</div><div class='add'>+		dccg35_disable_dpp_clk_new(dccg, dpp_inst);</div><div class='add'>+</div><div class='add'>+	dccg-&gt;pipe_dppclk_khz[dpp_inst] = req_dppclk;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_dpp_root_clock_control_cb(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	unsigned int dpp_inst,</div><div class='add'>+	bool power_on)</div><div class='add'>+{</div><div class='add'>+	if (dccg-&gt;dpp_clock_gated[dpp_inst] == power_on)</div><div class='add'>+		return;</div><div class='add'>+	/* power_on set indicates we need to ungate</div><div class='add'>+	 * Currently called from optimize_bandwidth and prepare_bandwidth calls</div><div class='add'>+	 * Since clock source is not passed restore to refclock on ungate</div><div class='add'>+	 * Redundant as gating when enabled is acheived through update_dpp_dto</div><div class='add'>+	 */</div><div class='add'>+	dccg35_set_dppclk_rcg(dccg, dpp_inst, !power_on);</div><div class='add'>+</div><div class='add'>+	dccg-&gt;dpp_clock_gated[dpp_inst] = !power_on;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk32_se_cb(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum phyd32clk_clock_source phyd32clk)</div><div class='add'>+{</div><div class='add'>+	dccg35_enable_symclk32_se_new(dccg, inst, (enum symclk32_se_clk_source)phyd32clk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_disable_symclk32_se_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk32_le_cb(</div><div class='add'>+			struct dccg *dccg,</div><div class='add'>+			int inst,</div><div class='add'>+			enum phyd32clk_clock_source src)</div><div class='add'>+{</div><div class='add'>+	dccg35_enable_symclk32_le_new(dccg, inst, (enum symclk32_le_clk_source) src);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_disable_symclk32_le_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk32_le_root_clock_gating_cb(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool power_on)</div><div class='add'>+{</div><div class='add'>+	/* power_on set indicates we need to ungate</div><div class='add'>+	 * Currently called from optimize_bandwidth and prepare_bandwidth calls</div><div class='add'>+	 * Since clock source is not passed restore to refclock on ungate</div><div class='add'>+	 * Redundant as gating when enabled is acheived through disable_symclk32_le</div><div class='add'>+	 */</div><div class='add'>+	if (power_on)</div><div class='add'>+		dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);</div><div class='add'>+	else</div><div class='add'>+		dccg35_disable_symclk32_le_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_physymclk_cb(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	enum physymclk_clock_source clk_src,</div><div class='add'>+	bool force_enable)</div><div class='add'>+{</div><div class='add'>+	/* force_enable = 0 indicates we can switch to ref clock */</div><div class='add'>+	if (force_enable)</div><div class='add'>+		dccg35_enable_physymclk_new(dccg, inst, (enum physymclk_source)clk_src);</div><div class='add'>+	else</div><div class='add'>+		dccg35_disable_physymclk_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_physymclk_root_clock_gating_cb(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool power_on)</div><div class='add'>+{</div><div class='add'>+	/* Redundant RCG already done in disable_physymclk</div><div class='add'>+	 * power_on = 1 indicates we need to ungate</div><div class='add'>+	 */</div><div class='add'>+	if (power_on)</div><div class='add'>+		dccg35_enable_physymclk_new(dccg, inst, PHYSYMCLK_REFCLK);</div><div class='add'>+	else</div><div class='add'>+		dccg35_disable_physymclk_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_symclk32_le_root_clock_gating(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int inst,</div><div class='add'>+	bool power_on)</div><div class='add'>+{</div><div class='add'>+	/* power_on set indicates we need to ungate</div><div class='add'>+	 * Currently called from optimize_bandwidth and prepare_bandwidth calls</div><div class='add'>+	 * Since clock source is not passed restore to refclock on ungate</div><div class='add'>+	 * Redundant as gating when enabled is acheived through disable_symclk32_le</div><div class='add'>+	 */</div><div class='add'>+	if (power_on)</div><div class='add'>+		dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);</div><div class='add'>+	else</div><div class='add'>+		dccg35_disable_symclk32_le_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dtbclk_p_src_cb(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	if (src == DTBCLK0)</div><div class='add'>+		dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, inst);</div><div class='add'>+	else</div><div class='add'>+		dccg35_disable_dtbclk_p_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_set_dtbclk_dto_cb(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		const struct dtbclk_dto_params *params)</div><div class='add'>+{</div><div class='add'>+	/* set_dtbclk_p_src typ called earlier to switch to DTBCLK</div><div class='add'>+	 * if params-&gt;ref_dtbclk_khz and req_dtbclk_khz are 0 switch to ref-clock</div><div class='add'>+	 */</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	/* DTO Output Rate / Pixel Rate = 1/4 */</div><div class='add'>+	int req_dtbclk_khz = params-&gt;pixclk_khz / 4;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;ref_dtbclk_khz &amp;&amp; req_dtbclk_khz) {</div><div class='add'>+		uint32_t modulo, phase;</div><div class='add'>+</div><div class='add'>+		dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, params-&gt;otg_inst);</div><div class='add'>+</div><div class='add'>+		// phase / modulo = dtbclk / dtbclk ref</div><div class='add'>+		modulo = params-&gt;ref_dtbclk_khz * 1000;</div><div class='add'>+		phase = req_dtbclk_khz * 1000;</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_MODULO[params-&gt;otg_inst], modulo);</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_PHASE[params-&gt;otg_inst], phase);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+				DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 1);</div><div class='add'>+</div><div class='add'>+		REG_WAIT(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+				DTBCLKDTO_ENABLE_STATUS[params-&gt;otg_inst], 1,</div><div class='add'>+				1, 100);</div><div class='add'>+</div><div class='add'>+		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */</div><div class='add'>+		dccg35_set_pixel_rate_div(dccg, params-&gt;otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);</div><div class='add'>+</div><div class='add'>+		/* The recommended programming sequence to enable DTBCLK DTO to generate</div><div class='add'>+		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should</div><div class='add'>+		 * be set only after DTO is enabled</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+				PIPE_DTO_SRC_SEL[params-&gt;otg_inst], 2);</div><div class='add'>+	} else {</div><div class='add'>+		dccg35_disable_dtbclk_p_new(dccg, params-&gt;otg_inst);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+					 DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 0,</div><div class='add'>+					 PIPE_DTO_SRC_SEL[params-&gt;otg_inst], params-&gt;is_hdmi ? 0 : 1);</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_MODULO[params-&gt;otg_inst], 0);</div><div class='add'>+		REG_WRITE(DTBCLK_DTO_PHASE[params-&gt;otg_inst], 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_dscclk_cb(struct dccg *dccg,</div><div class='add'>+									 int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_disable_dscclk_new(dccg, inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_enable_dscclk_new(dccg, inst, DSC_DTO_TUNED_CK_GPU_DISCLK_3);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_enable_symclk_se_cb(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	/* Switch to functional clock if already not selected */</div><div class='add'>+	dccg35_enable_symclk_be_new(dccg, SYMCLK_BE_PHYCLK, link_enc_inst);</div><div class='add'>+</div><div class='add'>+	dccg35_enable_symclk_fe_new(dccg, stream_enc_inst, (enum symclk_fe_source) link_enc_inst);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg35_disable_symclk_se_cb(</div><div class='add'>+			struct dccg *dccg,</div><div class='add'>+			uint32_t stream_enc_inst,</div><div class='add'>+			uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	dccg35_disable_symclk_fe_new(dccg, stream_enc_inst);</div><div class='add'>+</div><div class='add'>+	/* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)</div><div class='add'>+{</div><div class='add'>+	dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dccg_funcs dccg35_funcs_new = {</div><div class='add'>+	.update_dpp_dto = dccg35_update_dpp_dto_cb,</div><div class='add'>+	.dpp_root_clock_control = dccg35_dpp_root_clock_control_cb,</div><div class='add'>+	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,</div><div class='add'>+	.dccg_init = dccg35_init_cb,</div><div class='add'>+	.set_dpstreamclk = dccg35_set_dpstreamclk_cb,</div><div class='add'>+	.set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating_cb,</div><div class='add'>+	.enable_symclk32_se = dccg35_enable_symclk32_se_cb,</div><div class='add'>+	.disable_symclk32_se = dccg35_disable_symclk32_se_cb,</div><div class='add'>+	.enable_symclk32_le = dccg35_enable_symclk32_le_cb,</div><div class='add'>+	.disable_symclk32_le = dccg35_disable_symclk32_le_cb,</div><div class='add'>+	.set_symclk32_le_root_clock_gating = dccg35_set_symclk32_le_root_clock_gating_cb,</div><div class='add'>+	.set_physymclk = dccg35_set_physymclk_cb,</div><div class='add'>+	.set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating_cb,</div><div class='add'>+	.set_dtbclk_dto = dccg35_set_dtbclk_dto_cb,</div><div class='add'>+	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,</div><div class='add'>+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,</div><div class='add'>+	.otg_add_pixel = dccg31_otg_add_pixel,</div><div class='add'>+	.otg_drop_pixel = dccg31_otg_drop_pixel,</div><div class='add'>+	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,</div><div class='add'>+	.disable_dsc = dccg35_disable_dscclk_cb,</div><div class='add'>+	.enable_dsc = dccg35_enable_dscclk_cb,</div><div class='add'>+	.set_pixel_rate_div = dccg35_set_pixel_rate_div,</div><div class='add'>+	.get_pixel_rate_div = dccg35_get_pixel_rate_div,</div><div class='add'>+	.trigger_dio_fifo_resync = dccg35_trigger_dio_fifo_resync,</div><div class='add'>+	.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,</div><div class='add'>+	.enable_symclk_se = dccg35_enable_symclk_se_cb,</div><div class='add'>+	.disable_symclk_se = dccg35_disable_symclk_se_cb,</div><div class='add'>+	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src_cb,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dccg_funcs dccg35_funcs = {</div><div class='add'>+	.update_dpp_dto = dccg35_update_dpp_dto,</div><div class='add'>+	.dpp_root_clock_control = dccg35_dpp_root_clock_control,</div><div class='add'>+	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,</div><div class='add'>+	.dccg_init = dccg35_init,</div><div class='add'>+	.set_dpstreamclk = dccg35_set_dpstreamclk,</div><div class='add'>+	.set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating,</div><div class='add'>+	.enable_symclk32_se = dccg31_enable_symclk32_se,</div><div class='add'>+	.disable_symclk32_se = dccg35_disable_symclk32_se,</div><div class='add'>+	.enable_symclk32_le = dccg31_enable_symclk32_le,</div><div class='add'>+	.disable_symclk32_le = dccg31_disable_symclk32_le,</div><div class='add'>+	.set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,</div><div class='add'>+	.set_physymclk = dccg35_set_physymclk,</div><div class='add'>+	.set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating,</div><div class='add'>+	.set_dtbclk_dto = dccg35_set_dtbclk_dto,</div><div class='add'>+	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,</div><div class='add'>+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,</div><div class='add'>+	.otg_add_pixel = dccg31_otg_add_pixel,</div><div class='add'>+	.otg_drop_pixel = dccg31_otg_drop_pixel,</div><div class='add'>+	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,</div><div class='add'>+	.disable_dsc = dccg35_disable_dscclk,</div><div class='add'>+	.enable_dsc = dccg35_enable_dscclk,</div><div class='add'>+	.set_pixel_rate_div = dccg35_set_pixel_rate_div,</div><div class='add'>+	.get_pixel_rate_div = dccg35_get_pixel_rate_div,</div><div class='add'>+	.trigger_dio_fifo_resync = dccg35_trigger_dio_fifo_resync,</div><div class='add'>+	.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,</div><div class='add'>+	.enable_symclk_se = dccg35_enable_symclk_se,</div><div class='add'>+	.disable_symclk_se = dccg35_disable_symclk_se,</div><div class='add'>+	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,</div><div class='add'>+	.dccg_root_gate_disable_control = dccg35_root_gate_disable_control,</div><div class='add'>+	.dccg_read_reg_state = dccg31_read_reg_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dccg *dccg35_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dccg_registers *regs,</div><div class='add'>+	const struct dccg_shift *dccg_shift,</div><div class='add'>+	const struct dccg_mask *dccg_mask)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);</div><div class='add'>+	struct dccg *base;</div><div class='add'>+</div><div class='add'>+	if (dccg_dcn == NULL) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+	(void)&amp;dccg35_disable_symclk_be_new;</div><div class='add'>+	(void)&amp;dccg35_set_symclk32_le_root_clock_gating;</div><div class='add'>+	(void)&amp;dccg35_set_smclk32_se_rcg;</div><div class='add'>+	(void)&amp;dccg35_funcs_new;</div><div class='add'>+</div><div class='add'>+	base = &amp;dccg_dcn-&gt;base;</div><div class='add'>+	base-&gt;ctx = ctx;</div><div class='add'>+	base-&gt;funcs = &amp;dccg35_funcs;</div><div class='add'>+</div><div class='add'>+	dccg_dcn-&gt;regs = regs;</div><div class='add'>+	dccg_dcn-&gt;dccg_shift = dccg_shift;</div><div class='add'>+	dccg_dcn-&gt;dccg_mask = dccg_mask;</div><div class='add'>+</div><div class='add'>+	return &amp;dccg_dcn-&gt;base;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h<br/>index 1586a45ca3bd..7b9c36456cd9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h</a></div><div class='hunk'>@@ -41,8 +41,9 @@</div><div class='ctx'> 	SR(SYMCLKA_CLOCK_ENABLE),\</div><div class='ctx'> 	SR(SYMCLKB_CLOCK_ENABLE),\</div><div class='ctx'> 	SR(SYMCLKC_CLOCK_ENABLE),\</div><div class='del'>-	SR(SYMCLKD_CLOCK_ENABLE),\</div><div class='del'>-	SR(SYMCLKE_CLOCK_ENABLE)</div><div class='add'>+	SR(SYMCLKD_CLOCK_ENABLE), \</div><div class='add'>+	SR(SYMCLKE_CLOCK_ENABLE),\</div><div class='add'>+	SR(SYMCLK_PSP_CNTL)</div><div class='ctx'> </div><div class='ctx'> #define DCCG_MASK_SH_LIST_DCN35(mask_sh) \</div><div class='ctx'> 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\</div><div class='hunk'>@@ -231,6 +232,14 @@</div><div class='ctx'> 	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\</div><div class='ctx'> 	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\</div><div class='ctx'> </div><div class='ctx'> struct dccg *dccg35_create(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='hunk'>@@ -241,6 +250,7 @@ struct dccg *dccg35_create(</div><div class='ctx'> void dccg35_init(struct dccg *dccg);</div><div class='ctx'> </div><div class='ctx'> void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);</div><div class='add'>+void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #endif //__DCN35_DCCG_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c<br/>new file mode 100644<br/>index 000000000000..663a18ee5162<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c</a></div><div class='hunk'>@@ -0,0 +1,915 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dcn401_dccg.h"</div><div class='add'>+#include "dcn31/dcn31_dccg.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+#include "dmub_common.h"</div><div class='add'>+#include "dmcub_reg_access_helper.h"</div><div class='add'>+</div><div class='add'>+#include "dmub401_common.h"</div><div class='add'>+#include "dmub401_regs.h"</div><div class='add'>+#include "dmub401_dccg.h"</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+#define TO_DCN_DCCG(dccg)\</div><div class='add'>+	container_of(dccg, struct dcn_dccg, base)</div><div class='add'>+</div><div class='add'>+#define REG(reg) \</div><div class='add'>+	(dccg_dcn-&gt;regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	dccg_dcn-&gt;dccg_shift-&gt;field_name, dccg_dcn-&gt;dccg_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	dccg_dcn-&gt;base.ctx</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dccg-&gt;ctx-&gt;logger</div><div class='add'>+</div><div class='add'>+static void dcn401_set_dppclk_enable(struct dccg *dccg,</div><div class='add'>+				 uint32_t dpp_inst, uint32_t enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (dpp_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ref_dppclk &amp;&amp; req_dppclk) {</div><div class='add'>+		int ref_dppclk = dccg-&gt;ref_dppclk;</div><div class='add'>+		int modulo, phase;</div><div class='add'>+</div><div class='add'>+		// phase / modulo = dpp pipe clk / dpp global clk</div><div class='add'>+		modulo = 0xff;   // use FF at the end</div><div class='add'>+		phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;</div><div class='add'>+</div><div class='add'>+		if (phase &gt; 0xff) {</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			phase = 0xff;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='add'>+				DPPCLK0_DTO_PHASE, phase,</div><div class='add'>+				DPPCLK0_DTO_MODULO, modulo);</div><div class='add'>+		dcn401_set_dppclk_enable(dccg, dpp_inst, true);</div><div class='add'>+	} else {</div><div class='add'>+		dcn401_set_dppclk_enable(dccg, dpp_inst, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dccg-&gt;pipe_dppclk_khz[dpp_inst] = req_dppclk;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* This function is a workaround for writing to OTG_PIXEL_RATE_DIV</div><div class='add'>+ * without the probability of causing a DIG FIFO error.</div><div class='add'>+ */</div><div class='add'>+static void dccg401_wait_for_dentist_change_done(</div><div class='add'>+	struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);</div><div class='add'>+	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_get_pixel_rate_div(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		uint32_t *tmds_div,</div><div class='add'>+		uint32_t *dp_dto_int)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	uint32_t val_tmds_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+</div><div class='add'>+	switch (otg_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG0_TMDS_PIXEL_RATE_DIV, &amp;val_tmds_div,</div><div class='add'>+			DPDTO0_INT, dp_dto_int);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG1_TMDS_PIXEL_RATE_DIV, &amp;val_tmds_div,</div><div class='add'>+			DPDTO1_INT, dp_dto_int);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG2_TMDS_PIXEL_RATE_DIV, &amp;val_tmds_div,</div><div class='add'>+			DPDTO2_INT, dp_dto_int);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='add'>+			OTG3_TMDS_PIXEL_RATE_DIV, &amp;val_tmds_div,</div><div class='add'>+			DPDTO3_INT, dp_dto_int);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*tmds_div = val_tmds_div == 0 ? PIXEL_RATE_DIV_BY_2 : PIXEL_RATE_DIV_BY_4;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_set_pixel_rate_div(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		enum pixel_rate_div tmds_div,</div><div class='add'>+		enum pixel_rate_div unused)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+	uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	uint32_t dp_dto_int;</div><div class='add'>+	uint32_t reg_val;</div><div class='add'>+</div><div class='add'>+	// only 2 and 4 are valid on dcn401</div><div class='add'>+	if (tmds_div != PIXEL_RATE_DIV_BY_2 &amp;&amp; tmds_div != PIXEL_RATE_DIV_BY_4) {</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dccg401_get_pixel_rate_div(dccg, otg_inst, &amp;cur_tmds_div, &amp;dp_dto_int);</div><div class='add'>+	if (tmds_div == cur_tmds_div)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	// encode enum to register value</div><div class='add'>+	reg_val = tmds_div == PIXEL_RATE_DIV_BY_4 ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	switch (otg_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG0_TMDS_PIXEL_RATE_DIV, reg_val);</div><div class='add'>+</div><div class='add'>+		dccg401_wait_for_dentist_change_done(dccg);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG1_TMDS_PIXEL_RATE_DIV, reg_val);</div><div class='add'>+</div><div class='add'>+		dccg401_wait_for_dentist_change_done(dccg);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG2_TMDS_PIXEL_RATE_DIV, reg_val);</div><div class='add'>+</div><div class='add'>+		dccg401_wait_for_dentist_change_done(dccg);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+				OTG3_TMDS_PIXEL_RATE_DIV, reg_val);</div><div class='add'>+</div><div class='add'>+		dccg401_wait_for_dentist_change_done(dccg);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dccg401_set_dtbclk_p_src(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		uint32_t otg_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	uint32_t p_src_sel = 0; /* selects dprefclk */</div><div class='add'>+	if (src == DTBCLK0)</div><div class='add'>+		p_src_sel = 2;  /* selects dtbclk0 */</div><div class='add'>+</div><div class='add'>+	switch (otg_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P0_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P0_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P0_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P1_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P1_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P1_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P2_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P2_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P2_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (src == REFCLK)</div><div class='add'>+			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P3_EN, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='add'>+					DTBCLK_P3_SRC_SEL, p_src_sel,</div><div class='add'>+					DTBCLK_P3_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_set_physymclk(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int phy_inst,</div><div class='add'>+		enum physymclk_clock_source clk_src,</div><div class='add'>+		bool force_enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */</div><div class='add'>+	switch (phy_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYASYMCLK_EN, 1,</div><div class='add'>+					PHYASYMCLK_SRC_SEL, clk_src);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYASYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYASYMCLK_EN, 0,</div><div class='add'>+					PHYASYMCLK_SRC_SEL, 0);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYASYMCLK_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYBSYMCLK_EN, 1,</div><div class='add'>+					PHYBSYMCLK_SRC_SEL, clk_src);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYBSYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYBSYMCLK_EN, 0,</div><div class='add'>+					PHYBSYMCLK_SRC_SEL, 0);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYBSYMCLK_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYCSYMCLK_EN, 1,</div><div class='add'>+					PHYCSYMCLK_SRC_SEL, clk_src);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYCSYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYCSYMCLK_EN, 0,</div><div class='add'>+					PHYCSYMCLK_SRC_SEL, 0);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYCSYMCLK_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (force_enable) {</div><div class='add'>+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYDSYMCLK_EN, 1,</div><div class='add'>+					PHYDSYMCLK_SRC_SEL, clk_src);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYDSYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,</div><div class='add'>+					PHYDSYMCLK_EN, 0,</div><div class='add'>+					PHYDSYMCLK_SRC_SEL, 0);</div><div class='add'>+			if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='add'>+				REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='add'>+					PHYDSYMCLK_ROOT_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_get_dccg_ref_freq(struct dccg *dccg,</div><div class='add'>+		unsigned int xtalin_freq_inKhz,</div><div class='add'>+		unsigned int *dccg_ref_freq_inKhz)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Assume refclk is sourced from xtalin</div><div class='add'>+	 * expect 100MHz</div><div class='add'>+	 */</div><div class='add'>+	*dccg_ref_freq_inKhz = xtalin_freq_inKhz;</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg401_otg_add_pixel(struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],</div><div class='add'>+			OTG_ADD_PIXEL[otg_inst], 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg401_otg_drop_pixel(struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],</div><div class='add'>+			OTG_DROP_PIXEL[otg_inst], 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_enable_symclk32_le(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int hpo_le_inst,</div><div class='add'>+		enum phyd32clk_clock_source phyd32clk)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* select one of the PHYD32CLKs as the source for symclk32_le */</div><div class='add'>+	switch (hpo_le_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE0_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE0_SRC_SEL, phyd32clk,</div><div class='add'>+				SYMCLK32_LE0_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE1_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE1_SRC_SEL, phyd32clk,</div><div class='add'>+				SYMCLK32_LE1_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE2_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE2_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE2_SRC_SEL, phyd32clk,</div><div class='add'>+				SYMCLK32_LE2_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE3_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE3_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE3_SRC_SEL, phyd32clk,</div><div class='add'>+				SYMCLK32_LE3_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_disable_symclk32_le(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int hpo_le_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* set refclk as the source for symclk32_le */</div><div class='add'>+	switch (hpo_le_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE0_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_LE0_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE0_GATE_DISABLE, 0,</div><div class='add'>+					SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE1_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_LE1_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE1_GATE_DISABLE, 0,</div><div class='add'>+					SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE2_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_LE2_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE2_GATE_DISABLE, 0,</div><div class='add'>+					SYMCLK32_ROOT_LE2_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_LE_CNTL,</div><div class='add'>+				SYMCLK32_LE3_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_LE3_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_LE3_GATE_DISABLE, 0,</div><div class='add'>+					SYMCLK32_ROOT_LE3_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_hpo_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* enabled to select one of the DTBCLKs for pipe */</div><div class='add'>+	switch (dp_hpo_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK0_ROOT_GATE_DISABLE, 1,</div><div class='add'>+					DPSTREAMCLK0_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK0_SRC_SEL, otg_inst,</div><div class='add'>+				DPSTREAMCLK0_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK1_ROOT_GATE_DISABLE, 1,</div><div class='add'>+					DPSTREAMCLK1_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK1_SRC_SEL, otg_inst,</div><div class='add'>+				DPSTREAMCLK1_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK2_ROOT_GATE_DISABLE, 1,</div><div class='add'>+					DPSTREAMCLK2_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK2_SRC_SEL, otg_inst,</div><div class='add'>+				DPSTREAMCLK2_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK3_ROOT_GATE_DISABLE, 1,</div><div class='add'>+					DPSTREAMCLK3_GATE_DISABLE, 1);</div><div class='add'>+		REG_UPDATE_2(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK3_SRC_SEL, otg_inst,</div><div class='add'>+				DPSTREAMCLK3_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+		REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+			DPSTREAMCLK_GATE_DISABLE, 1,</div><div class='add'>+			DPSTREAMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (dp_hpo_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK0_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK0_ROOT_GATE_DISABLE, 0,</div><div class='add'>+					DPSTREAMCLK0_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK1_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK1_ROOT_GATE_DISABLE, 0,</div><div class='add'>+					DPSTREAMCLK1_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK2_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK2_ROOT_GATE_DISABLE, 0,</div><div class='add'>+					DPSTREAMCLK2_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DPSTREAMCLK_CNTL,</div><div class='add'>+				DPSTREAMCLK3_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='add'>+			REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+					DPSTREAMCLK3_ROOT_GATE_DISABLE, 0,</div><div class='add'>+					DPSTREAMCLK3_GATE_DISABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_set_dpstreamclk(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		int otg_inst,</div><div class='add'>+		int dp_hpo_inst)</div><div class='add'>+{</div><div class='add'>+	/* enabled to select one of the DTBCLKs for pipe */</div><div class='add'>+	if (src == REFCLK)</div><div class='add'>+		dccg401_disable_dpstreamclk(dccg, dp_hpo_inst);</div><div class='add'>+	else</div><div class='add'>+		dccg401_enable_dpstreamclk(dccg, otg_inst, dp_hpo_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_set_dp_dto(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		const struct dp_dto_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	bool enable = false;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;otg_inst &gt; 3) {</div><div class='add'>+		/* dcn401 only has 4 instances */</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	if (!params-&gt;refclk_hz) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dc_is_tmds_signal(params-&gt;signal)) {</div><div class='add'>+		uint64_t dto_integer;</div><div class='add'>+		uint64_t dto_phase_hz;</div><div class='add'>+		uint64_t dto_modulo_hz = params-&gt;refclk_hz;</div><div class='add'>+</div><div class='add'>+		enable = true;</div><div class='add'>+</div><div class='add'>+		/* Set DTO values:</div><div class='add'>+		 * int = target_pix_rate / reference_clock</div><div class='add'>+		 * phase = target_pix_rate - int * reference_clock,</div><div class='add'>+		 * modulo = reference_clock */</div><div class='add'>+		dto_integer = div_u64(params-&gt;pixclk_hz, dto_modulo_hz);</div><div class='add'>+		dto_phase_hz = params-&gt;pixclk_hz - dto_integer * dto_modulo_hz;</div><div class='add'>+</div><div class='add'>+		if (dto_phase_hz &lt;= 0 &amp;&amp; dto_integer &lt;= 0) {</div><div class='add'>+			/* negative pixel rate should never happen */</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (params-&gt;otg_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);</div><div class='add'>+			REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE0_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_SE0_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_LE0_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);</div><div class='add'>+			REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE1_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_SE1_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_LE1_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);</div><div class='add'>+			REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE2_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_SE2_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_LE2_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE2_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);</div><div class='add'>+			REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE3_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_SE3_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_LE3_GATE_DISABLE, 1,</div><div class='add'>+					SYMCLK32_ROOT_LE3_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dccg401_set_dtbclk_p_src(dccg, params-&gt;clk_src, params-&gt;otg_inst);</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DP_DTO_PHASE[params-&gt;otg_inst], dto_phase_hz);</div><div class='add'>+		REG_WRITE(DP_DTO_MODULO[params-&gt;otg_inst], dto_modulo_hz);</div><div class='add'>+</div><div class='add'>+		switch (params-&gt;otg_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+					DPDTO0_INT, dto_integer);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+					DPDTO1_INT, dto_integer);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+					DPDTO2_INT, dto_integer);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(OTG_PIXEL_RATE_DIV,</div><div class='add'>+					DPDTO3_INT, dto_integer);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Toggle DTO */</div><div class='add'>+	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='add'>+			DP_DTO_ENABLE[params-&gt;otg_inst], enable,</div><div class='add'>+			PIPE_DTO_SRC_SEL[params-&gt;otg_inst], enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_init(struct dccg *dccg)</div><div class='add'>+{</div><div class='add'>+	/* Set HPO stream encoder to use refclk to avoid case where PHY is</div><div class='add'>+	 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which</div><div class='add'>+	 * will cause DCN to hang.</div><div class='add'>+	 */</div><div class='add'>+	dccg31_disable_symclk32_se(dccg, 0);</div><div class='add'>+	dccg31_disable_symclk32_se(dccg, 1);</div><div class='add'>+	dccg31_disable_symclk32_se(dccg, 2);</div><div class='add'>+	dccg31_disable_symclk32_se(dccg, 3);</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le) {</div><div class='add'>+		dccg401_disable_symclk32_le(dccg, 0);</div><div class='add'>+		dccg401_disable_symclk32_le(dccg, 1);</div><div class='add'>+		dccg401_disable_symclk32_le(dccg, 2);</div><div class='add'>+		dccg401_disable_symclk32_le(dccg, 3);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream) {</div><div class='add'>+		dccg401_disable_dpstreamclk(dccg, 0);</div><div class='add'>+		dccg401_disable_dpstreamclk(dccg, 1);</div><div class='add'>+		dccg401_disable_dpstreamclk(dccg, 2);</div><div class='add'>+		dccg401_disable_dpstreamclk(dccg, 3);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk) {</div><div class='add'>+		dccg401_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);</div><div class='add'>+		dccg401_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);</div><div class='add'>+		dccg401_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);</div><div class='add'>+		dccg401_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,</div><div class='add'>+				DSCCLK0_DTO_PHASE, 1,</div><div class='add'>+				DSCCLK0_DTO_MODULO, 1);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1);</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,</div><div class='add'>+				DSCCLK1_DTO_PHASE, 1,</div><div class='add'>+				DSCCLK1_DTO_MODULO, 1);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,</div><div class='add'>+				DSCCLK2_DTO_PHASE, 1,</div><div class='add'>+				DSCCLK2_DTO_MODULO, 1);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(DSCCLK3_DTO_PARAM,</div><div class='add'>+				DSCCLK3_DTO_PHASE, 1,</div><div class='add'>+				DSCCLK3_DTO_MODULO, 1);</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_set_ref_dscclk(struct dccg *dccg,</div><div class='add'>+				uint32_t dsc_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (dsc_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,</div><div class='add'>+				DSCCLK0_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK0_DTO_MODULO, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,</div><div class='add'>+				DSCCLK1_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK1_DTO_MODULO, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,</div><div class='add'>+				DSCCLK2_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK2_DTO_MODULO, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0);</div><div class='add'>+		REG_UPDATE_2(DSCCLK3_DTO_PARAM,</div><div class='add'>+				DSCCLK3_DTO_PHASE, 0,</div><div class='add'>+				DSCCLK3_DTO_MODULO, 0);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (stream_enc_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKA_FE_EN, 1,</div><div class='add'>+				SYMCLKA_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKB_FE_EN, 1,</div><div class='add'>+				SYMCLKB_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKC_FE_EN, 1,</div><div class='add'>+				SYMCLKC_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKD_FE_EN, 1,</div><div class='add'>+				SYMCLKD_FE_SRC_SEL, link_enc_inst);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se)</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	switch (stream_enc_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKA_FE_EN, 0,</div><div class='add'>+				SYMCLKA_FE_SRC_SEL, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKB_FE_EN, 0,</div><div class='add'>+				SYMCLKB_FE_SRC_SEL, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKC_FE_EN, 0,</div><div class='add'>+				SYMCLKC_FE_SRC_SEL, 0);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='add'>+				SYMCLKD_FE_EN, 0,</div><div class='add'>+				SYMCLKD_FE_SRC_SEL, 0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dccg_funcs dccg401_funcs = {</div><div class='add'>+	.update_dpp_dto = dccg401_update_dpp_dto,</div><div class='add'>+	.get_dccg_ref_freq = dccg401_get_dccg_ref_freq,</div><div class='add'>+	.dccg_init = dccg401_init,</div><div class='add'>+	.set_dpstreamclk = dccg401_set_dpstreamclk,</div><div class='add'>+	.enable_symclk32_se = dccg31_enable_symclk32_se,</div><div class='add'>+	.disable_symclk32_se = dccg31_disable_symclk32_se,</div><div class='add'>+	.enable_symclk32_le = dccg401_enable_symclk32_le,</div><div class='add'>+	.disable_symclk32_le = dccg401_disable_symclk32_le,</div><div class='add'>+	.set_physymclk = dccg401_set_physymclk,</div><div class='add'>+	.set_dtbclk_dto = NULL,</div><div class='add'>+	.set_dto_dscclk = dccg401_set_dto_dscclk,</div><div class='add'>+	.set_ref_dscclk = dccg401_set_ref_dscclk,</div><div class='add'>+	.set_valid_pixel_rate = NULL,</div><div class='add'>+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,</div><div class='add'>+	.set_audio_dtbclk_dto = NULL,</div><div class='add'>+	.otg_add_pixel = dccg401_otg_add_pixel,</div><div class='add'>+	.otg_drop_pixel = dccg401_otg_drop_pixel,</div><div class='add'>+	.set_pixel_rate_div = dccg401_set_pixel_rate_div,</div><div class='add'>+	.get_pixel_rate_div = dccg401_get_pixel_rate_div,</div><div class='add'>+	.set_dp_dto = dccg401_set_dp_dto,</div><div class='add'>+	.enable_symclk_se = dccg401_enable_symclk_se,</div><div class='add'>+	.disable_symclk_se = dccg401_disable_symclk_se,</div><div class='add'>+	.set_dtbclk_p_src = dccg401_set_dtbclk_p_src,</div><div class='add'>+	.dccg_read_reg_state = dccg31_read_reg_state</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dccg *dccg401_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dccg_registers *regs,</div><div class='add'>+	const struct dccg_shift *dccg_shift,</div><div class='add'>+	const struct dccg_mask *dccg_mask)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);</div><div class='add'>+	struct dccg *base;</div><div class='add'>+</div><div class='add'>+	if (dccg_dcn == NULL) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	base = &amp;dccg_dcn-&gt;base;</div><div class='add'>+	base-&gt;ctx = ctx;</div><div class='add'>+	base-&gt;funcs = &amp;dccg401_funcs;</div><div class='add'>+</div><div class='add'>+	dccg_dcn-&gt;regs = regs;</div><div class='add'>+	dccg_dcn-&gt;dccg_shift = dccg_shift;</div><div class='add'>+	dccg_dcn-&gt;dccg_mask = dccg_mask;</div><div class='add'>+</div><div class='add'>+	return &amp;dccg_dcn-&gt;base;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h<br/>new file mode 100644<br/>index 000000000000..5947a35363aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h</a></div><div class='hunk'>@@ -0,0 +1,249 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DCN401_DCCG_H__</div><div class='add'>+#define __DCN401_DCCG_H__</div><div class='add'>+</div><div class='add'>+#include "dcn32/dcn32_dccg.h"</div><div class='add'>+</div><div class='add'>+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\</div><div class='add'>+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+#define DCCG_MASK_SH_LIST_DCN401(mask_sh) \</div><div class='add'>+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\</div><div class='add'>+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\</div><div class='add'>+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\</div><div class='add'>+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\</div><div class='add'>+	DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\</div><div class='add'>+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_TMDS_PIXEL_RATE_DIV, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO0_INT, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_TMDS_PIXEL_RATE_DIV, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO1_INT, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_TMDS_PIXEL_RATE_DIV, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO2_INT, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_TMDS_PIXEL_RATE_DIV, mask_sh),\</div><div class='add'>+	DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO3_INT, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\</div><div class='add'>+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\</div><div class='add'>+	DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\</div><div class='add'>+</div><div class='add'>+void dccg401_init(struct dccg *dccg);</div><div class='add'>+</div><div class='add'>+void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);</div><div class='add'>+void dccg401_get_dccg_ref_freq(struct dccg *dccg,</div><div class='add'>+		unsigned int xtalin_freq_inKhz,</div><div class='add'>+		unsigned int *dccg_ref_freq_inKhz);</div><div class='add'>+void dccg401_set_dpstreamclk(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		int otg_inst,</div><div class='add'>+		int dp_hpo_inst);</div><div class='add'>+void dccg401_enable_symclk32_le(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int hpo_le_inst,</div><div class='add'>+		enum phyd32clk_clock_source phyd32clk);</div><div class='add'>+void dccg401_disable_symclk32_le(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int hpo_le_inst);</div><div class='add'>+void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);</div><div class='add'>+void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);</div><div class='add'>+void dccg401_set_ref_dscclk(struct dccg *dccg,</div><div class='add'>+				uint32_t dsc_inst);</div><div class='add'>+void dccg401_set_src_sel(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	const struct dtbclk_dto_params *params);</div><div class='add'>+void dccg401_set_pixel_rate_div(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		enum pixel_rate_div tmds_div,</div><div class='add'>+		enum pixel_rate_div unused);</div><div class='add'>+void dccg401_get_pixel_rate_div(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		uint32_t *tmds_div,</div><div class='add'>+		uint32_t *dp_dto_int);</div><div class='add'>+void dccg401_set_dp_dto(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		const struct dp_dto_params *params);</div><div class='add'>+void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);</div><div class='add'>+void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);</div><div class='add'>+void dccg401_set_dtbclk_p_src(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		enum streamclk_source src,</div><div class='add'>+		uint32_t otg_inst);</div><div class='add'>+struct dccg *dccg401_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dccg_registers *regs,</div><div class='add'>+	const struct dccg_shift *dccg_shift,</div><div class='add'>+	const struct dccg_mask *dccg_mask);</div><div class='add'>+</div><div class='add'>+void dccg401_set_physymclk(</div><div class='add'>+	struct dccg *dccg,</div><div class='add'>+	int phy_inst,</div><div class='add'>+	enum physymclk_clock_source clk_src,</div><div class='add'>+	bool force_enable);</div><div class='add'>+</div><div class='add'>+#endif //__DCN401_DCCG_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c<br/>index a6006776333d..2dcf394edf22 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.c</a></div><div class='hunk'>@@ -283,7 +283,7 @@ struct abm *dce_abm_create(</div><div class='ctx'> 	const struct dce_abm_shift *abm_shift,</div><div class='ctx'> 	const struct dce_abm_mask *abm_mask)</div><div class='ctx'> {</div><div class='del'>-	struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_ATOMIC);</div><div class='add'>+	struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (abm_dce == NULL) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h<br/>index 051e4c2b4cf2..3d819fc5654c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.h</a></div><div class='hunk'>@@ -236,6 +236,70 @@</div><div class='ctx'> 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \</div><div class='ctx'> 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)</div><div class='ctx'> </div><div class='add'>+#define ABM_MASK_SH_LIST_DCN401(mask_sh) \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \</div><div class='add'>+			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \</div><div class='add'>+			ABM1_HG_VMAX_SEL, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \</div><div class='add'>+			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \</div><div class='add'>+			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \</div><div class='add'>+			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \</div><div class='add'>+			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \</div><div class='add'>+			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \</div><div class='add'>+			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \</div><div class='add'>+			BL1_PWM_USER_LEVEL, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \</div><div class='add'>+			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \</div><div class='add'>+			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \</div><div class='add'>+			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \</div><div class='add'>+			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \</div><div class='add'>+			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \</div><div class='add'>+			ABM1_ACE_SLOPE_DATA, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \</div><div class='add'>+			ABM1_ACE_OFFSET_DATA, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \</div><div class='add'>+			ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \</div><div class='add'>+			ABM1_ACE_THRES_INDEX, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \</div><div class='add'>+			ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \</div><div class='add'>+			ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \</div><div class='add'>+			ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \</div><div class='add'>+			ABM1_ACE_LOCK, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \</div><div class='add'>+			ABM1_ACE_THRES_DATA_1, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_ACE_THRES_DATA, \</div><div class='add'>+			ABM1_ACE_THRES_DATA_2, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \</div><div class='add'>+			ABM1_HG_RESULT_DATA, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \</div><div class='add'>+			ABM1_HG_RESULT_INDEX, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \</div><div class='add'>+			ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \</div><div class='add'>+			ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \</div><div class='add'>+			ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \</div><div class='add'>+			ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \</div><div class='add'>+	ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \</div><div class='add'>+			ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)</div><div class='add'>+</div><div class='ctx'> #define ABM_REG_FIELD_LIST(type) \</div><div class='ctx'> 	type ABM1_HG_NUM_OF_BINS_SEL; \</div><div class='ctx'> 	type ABM1_HG_VMAX_SEL; \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c<br/>index 12f3c35b3a34..fcad61c618a1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.c</a></div><div class='hunk'>@@ -353,7 +353,7 @@ static uint32_t calculate_required_audio_bw_in_symbols(</div><div class='ctx'> 	/* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */</div><div class='ctx'> 	struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100);</div><div class='ctx'> 	struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction(</div><div class='del'>-			crtc_info-&gt;requested_pixel_clock_100Hz, crtc_info-&gt;h_total * 10);</div><div class='add'>+			crtc_info-&gt;requested_pixel_clock_100Hz, (long long)crtc_info-&gt;h_total * 10);</div><div class='ctx'> 	struct fixed31_32 samples_per_line;</div><div class='ctx'> 	struct fixed31_32 layouts_per_line;</div><div class='ctx'> 	struct fixed31_32 symbols_per_sdp_max_layout;</div><div class='hunk'>@@ -455,7 +455,8 @@ static uint32_t calculate_available_hblank_bw_in_symbols(</div><div class='ctx'> 	available_hblank_bw -= crtc_info-&gt;dsc_num_slices * 4; /* EOC overhead */</div><div class='ctx'> </div><div class='ctx'> 	if (available_hblank_bw &lt; dp_link_info-&gt;hblank_min_symbol_width)</div><div class='del'>-		available_hblank_bw = dp_link_info-&gt;hblank_min_symbol_width;</div><div class='add'>+		/* Each symbol takes 4 frames */</div><div class='add'>+		available_hblank_bw = 4 * dp_link_info-&gt;hblank_min_symbol_width;</div><div class='ctx'> </div><div class='ctx'> 	if (available_hblank_bw &lt; 12)</div><div class='ctx'> 		available_hblank_bw = 0;</div><div class='hunk'>@@ -629,6 +630,11 @@ void dce_aud_az_enable(struct audio *audio)</div><div class='ctx'> 			audio-&gt;inst, value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dce_aud_az_disable_hbr_audio(struct audio *audio)</div><div class='add'>+{</div><div class='add'>+	set_high_bit_rate_capable(audio, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dce_aud_az_disable(struct audio *audio)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t value;</div><div class='hunk'>@@ -1137,7 +1143,8 @@ void dce_aud_wall_dto_setup(</div><div class='ctx'> 		REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,</div><div class='ctx'> 				DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);</div><div class='ctx'> </div><div class='del'>-		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,</div><div class='add'>+		if (aud-&gt;masks-&gt;DCCG_AUDIO_DTO2_USE_512FBR_DTO)</div><div class='add'>+			REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,</div><div class='ctx'> 				DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='hunk'>@@ -1292,6 +1299,7 @@ static const struct audio_funcs funcs = {</div><div class='ctx'> 	.az_enable = dce_aud_az_enable,</div><div class='ctx'> 	.az_disable = dce_aud_az_disable,</div><div class='ctx'> 	.az_configure = dce_aud_az_configure,</div><div class='add'>+	.az_disable_hbr_audio = dce_aud_az_disable_hbr_audio,</div><div class='ctx'> 	.destroy = dce_aud_destroy,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h<br/>index 539f881928d1..1b7b8b079af4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.h</a></div><div class='hunk'>@@ -166,6 +166,7 @@ void dce_aud_hw_init(struct audio *audio);</div><div class='ctx'> </div><div class='ctx'> void dce_aud_az_enable(struct audio *audio);</div><div class='ctx'> void dce_aud_az_disable(struct audio *audio);</div><div class='add'>+void dce_aud_az_disable_hbr_audio(struct audio *audio);</div><div class='ctx'> </div><div class='ctx'> void dce_aud_az_configure(struct audio *audio,</div><div class='ctx'> 	enum signal_type signal,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c<br/>index 739298d2dff3..673bb87d2c17 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_aux.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_aux.c</a></div><div class='hunk'>@@ -725,20 +725,34 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,</div><div class='ctx'> 	for (i = 0; i &lt; AUX_MAX_RETRIES; i++) {</div><div class='ctx'> 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,</div><div class='ctx'> 					LOG_FLAG_I2cAux_DceAux,</div><div class='del'>-					"dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: address=0x%04x length=%u write=%d mot=%d",</div><div class='add'>+					"dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: "</div><div class='add'>+					"address=0x%04x length=%u write=%d mot=%d is_i2c=%d is_dpia=%d ddc_hw_inst=%d",</div><div class='ctx'> 					ddc &amp;&amp; ddc-&gt;link ? ddc-&gt;link-&gt;link_index : UINT_MAX,</div><div class='ctx'> 					i + 1,</div><div class='ctx'> 					(int)AUX_MAX_RETRIES,</div><div class='ctx'> 					payload-&gt;address,</div><div class='ctx'> 					payload-&gt;length,</div><div class='ctx'> 					(unsigned int) payload-&gt;write,</div><div class='del'>-					(unsigned int) payload-&gt;mot);</div><div class='add'>+					(unsigned int) payload-&gt;mot,</div><div class='add'>+					payload-&gt;i2c_over_aux,</div><div class='add'>+					(ddc-&gt;link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,</div><div class='add'>+					ddc-&gt;link-&gt;ddc_hw_inst);</div><div class='ctx'> 		if (payload-&gt;write)</div><div class='ctx'> 			dce_aux_log_payload("  write", payload-&gt;data, payload-&gt;length, 16);</div><div class='del'>-		ret = dce_aux_transfer_raw(ddc, payload, &amp;operation_result);</div><div class='add'>+</div><div class='add'>+		/* Check whether aux to be processed via dmub or dcn directly */</div><div class='add'>+		if (ddc-&gt;ctx-&gt;dc-&gt;debug.enable_dmub_aux_for_legacy_ddc</div><div class='add'>+			|| ddc-&gt;ddc_pin == NULL) {</div><div class='add'>+			ret = dce_aux_transfer_dmub_raw(ddc, payload, &amp;operation_result);</div><div class='add'>+		} else {</div><div class='add'>+			ret = dce_aux_transfer_raw(ddc, payload, &amp;operation_result);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,</div><div class='ctx'> 					LOG_FLAG_I2cAux_DceAux,</div><div class='del'>-					"dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d payload-&gt;reply=%u",</div><div class='add'>+					"dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: "</div><div class='add'>+					"address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d "</div><div class='add'>+					"payload-&gt;reply=%u  is_i2c=%d is_dpia=%d ddc_hw_inst=%d",</div><div class='ctx'> 					ddc &amp;&amp; ddc-&gt;link ? ddc-&gt;link-&gt;link_index : UINT_MAX,</div><div class='ctx'> 					i + 1,</div><div class='ctx'> 					(int)AUX_MAX_RETRIES,</div><div class='hunk'>@@ -748,7 +762,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,</div><div class='ctx'> 					(unsigned int) payload-&gt;mot,</div><div class='ctx'> 					ret,</div><div class='ctx'> 					(int)operation_result,</div><div class='del'>-					(unsigned int) *payload-&gt;reply);</div><div class='add'>+					(unsigned int) *payload-&gt;reply,</div><div class='add'>+					payload-&gt;i2c_over_aux,</div><div class='add'>+					(ddc-&gt;link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,</div><div class='add'>+					ddc-&gt;link-&gt;ddc_hw_inst);</div><div class='ctx'> 		if (!payload-&gt;write)</div><div class='ctx'> 			dce_aux_log_payload("  read", payload-&gt;data, ret &gt; 0 ? ret : 0, 16);</div><div class='ctx'> </div><div class='hunk'>@@ -770,7 +787,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,</div><div class='ctx'> 									aux_defer_retries,</div><div class='ctx'> 									AUX_MAX_RETRIES);</div><div class='ctx'> 						goto fail;</div><div class='del'>-					} else </div><div class='add'>+					} else</div><div class='ctx'> 						udelay(300);</div><div class='ctx'> 				} else if (payload-&gt;write &amp;&amp; ret &gt; 0) {</div><div class='ctx'> 					/* sink requested more time to complete the write via AUX_ACKM */</div><div class='hunk'>@@ -790,7 +807,6 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,</div><div class='ctx'> 					payload-&gt;write_status_update = true;</div><div class='ctx'> 					payload-&gt;length = 0;</div><div class='ctx'> 					udelay(300);</div><div class='del'>-</div><div class='ctx'> 				} else</div><div class='ctx'> 					return true;</div><div class='ctx'> 			break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c<br/>index 970644b695cd..b4f5b4a6331a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c</a></div><div class='hunk'>@@ -217,7 +217,7 @@ static bool calc_fb_divider_checking_tolerance(</div><div class='ctx'> 	actual_calc_clk_100hz = (uint64_t)feedback_divider *</div><div class='ctx'> 					calc_pll_cs-&gt;fract_fb_divider_factor +</div><div class='ctx'> 							fract_feedback_divider;</div><div class='del'>-	actual_calc_clk_100hz *= calc_pll_cs-&gt;ref_freq_khz * 10;</div><div class='add'>+	actual_calc_clk_100hz *= (uint64_t)calc_pll_cs-&gt;ref_freq_khz * 10;</div><div class='ctx'> 	actual_calc_clk_100hz =</div><div class='ctx'> 		div_u64(actual_calc_clk_100hz,</div><div class='ctx'> 			ref_divider * post_divider *</div><div class='hunk'>@@ -680,7 +680,7 @@ static bool calculate_ss(</div><div class='ctx'> 	 * so have to divided by 100 * 100*/</div><div class='ctx'> 	ss_amount = dc_fixpt_mul(</div><div class='ctx'> 		fb_div, dc_fixpt_from_fraction(ss_data-&gt;percentage,</div><div class='del'>-					100 * ss_data-&gt;percentage_divider));</div><div class='add'>+					100 * (long long)ss_data-&gt;percentage_divider));</div><div class='ctx'> 	ds_data-&gt;feedback_amount = dc_fixpt_floor(ss_amount);</div><div class='ctx'> </div><div class='ctx'> 	ss_nslip_amount = dc_fixpt_sub(ss_amount,</div><div class='hunk'>@@ -695,8 +695,8 @@ static bool calculate_ss(</div><div class='ctx'> </div><div class='ctx'> 	/* compute SS_STEP_SIZE_DSFRAC */</div><div class='ctx'> 	modulation_time = dc_fixpt_from_fraction(</div><div class='del'>-		pll_settings-&gt;reference_freq * 1000,</div><div class='del'>-		pll_settings-&gt;reference_divider * ss_data-&gt;modulation_freq_hz);</div><div class='add'>+		pll_settings-&gt;reference_freq * (uint64_t)1000,</div><div class='add'>+		pll_settings-&gt;reference_divider * (uint64_t)ss_data-&gt;modulation_freq_hz);</div><div class='ctx'> </div><div class='ctx'> 	if (ss_data-&gt;flags.CENTER_SPREAD)</div><div class='ctx'> 		modulation_time = dc_fixpt_div_int(modulation_time, 4);</div><div class='hunk'>@@ -976,8 +976,12 @@ static bool dcn31_program_pix_clk(</div><div class='ctx'> 	struct bp_pixel_clock_parameters bp_pc_params = {0};</div><div class='ctx'> 	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;</div><div class='ctx'> </div><div class='del'>-	if (clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz != 0)</div><div class='add'>+	// Apply ssed(spread spectrum) dpref clock for edp and dp</div><div class='add'>+	if (clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz != 0 &amp;&amp;</div><div class='add'>+		dc_is_dp_signal(pix_clk_params-&gt;signal_type) &amp;&amp;</div><div class='add'>+		encoding == DP_8b_10b_ENCODING)</div><div class='ctx'> 		dp_dto_ref_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz;</div><div class='add'>+</div><div class='ctx'> 	// For these signal types Driver to program DP_DTO without calling VBIOS Command table</div><div class='ctx'> 	if (dc_is_dp_signal(pix_clk_params-&gt;signal_type) || dc_is_virtual_signal(pix_clk_params-&gt;signal_type)) {</div><div class='ctx'> 		if (e) {</div><div class='hunk'>@@ -1060,6 +1064,108 @@ static bool dcn31_program_pix_clk(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool dcn401_program_pix_clk(</div><div class='add'>+		struct clock_source *clock_source,</div><div class='add'>+		struct pixel_clk_params *pix_clk_params,</div><div class='add'>+		enum dp_link_encoding encoding,</div><div class='add'>+		struct pll_settings *pll_settings)</div><div class='add'>+{</div><div class='add'>+	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);</div><div class='add'>+	unsigned int inst = pix_clk_params-&gt;controller_id - CONTROLLER_ID_D0;</div><div class='add'>+	const struct pixel_rate_range_table_entry *e =</div><div class='add'>+			look_up_in_video_optimized_rate_tlb(pix_clk_params-&gt;requested_pix_clk_100hz / 10);</div><div class='add'>+	struct bp_pixel_clock_parameters bp_pc_params = {0};</div><div class='add'>+	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;</div><div class='add'>+	struct dp_dto_params dto_params = { 0 };</div><div class='add'>+</div><div class='add'>+	dto_params.otg_inst = inst;</div><div class='add'>+	dto_params.signal = pix_clk_params-&gt;signal_type;</div><div class='add'>+</div><div class='add'>+	// all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table</div><div class='add'>+	if (!dc_is_tmds_signal(pix_clk_params-&gt;signal_type)) {</div><div class='add'>+		long long dtbclk_p_src_clk_khz;</div><div class='add'>+</div><div class='add'>+		dtbclk_p_src_clk_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz;</div><div class='add'>+		dto_params.clk_src = DPREFCLK;</div><div class='add'>+</div><div class='add'>+		if (e) {</div><div class='add'>+			dto_params.pixclk_hz = e-&gt;target_pixel_rate_khz;</div><div class='add'>+			dto_params.pixclk_hz *= e-&gt;mult_factor;</div><div class='add'>+			dto_params.refclk_hz = dtbclk_p_src_clk_khz;</div><div class='add'>+			dto_params.refclk_hz *= e-&gt;div_factor;</div><div class='add'>+		} else {</div><div class='add'>+			dto_params.pixclk_hz = pix_clk_params-&gt;requested_pix_clk_100hz;</div><div class='add'>+			dto_params.pixclk_hz *= 100;</div><div class='add'>+			dto_params.refclk_hz = dtbclk_p_src_clk_khz;</div><div class='add'>+			dto_params.refclk_hz *= 1000;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* enable DP DTO */</div><div class='add'>+		clock_source-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dp_dto(</div><div class='add'>+				clock_source-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg,</div><div class='add'>+				&amp;dto_params);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		if (pll_settings-&gt;actual_pix_clk_100hz &gt; 6000000UL)</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		/* disables DP DTO when provided with TMDS signal type */</div><div class='add'>+		clock_source-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dp_dto(</div><div class='add'>+				clock_source-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg,</div><div class='add'>+				&amp;dto_params);</div><div class='add'>+</div><div class='add'>+		/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/</div><div class='add'>+		bp_pc_params.controller_id = pix_clk_params-&gt;controller_id;</div><div class='add'>+		bp_pc_params.pll_id = clock_source-&gt;id;</div><div class='add'>+		bp_pc_params.target_pixel_clock_100hz = pll_settings-&gt;actual_pix_clk_100hz;</div><div class='add'>+		bp_pc_params.encoder_object_id = pix_clk_params-&gt;encoder_object_id;</div><div class='add'>+		bp_pc_params.signal_type = pix_clk_params-&gt;signal_type;</div><div class='add'>+</div><div class='add'>+		// Make sure we send the correct color depth to DMUB for HDMI</div><div class='add'>+		if (pix_clk_params-&gt;signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {</div><div class='add'>+			switch (pix_clk_params-&gt;color_depth) {</div><div class='add'>+			case COLOR_DEPTH_888:</div><div class='add'>+				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;</div><div class='add'>+				break;</div><div class='add'>+			case COLOR_DEPTH_101010:</div><div class='add'>+				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;</div><div class='add'>+				break;</div><div class='add'>+			case COLOR_DEPTH_121212:</div><div class='add'>+				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;</div><div class='add'>+				break;</div><div class='add'>+			case COLOR_DEPTH_161616:</div><div class='add'>+				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			bp_pc_params.color_depth = bp_pc_colour_depth;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (clock_source-&gt;id != CLOCK_SOURCE_ID_DP_DTO) {</div><div class='add'>+			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =</div><div class='add'>+							pll_settings-&gt;use_external_clk;</div><div class='add'>+			bp_pc_params.flags.SET_XTALIN_REF_SRC =</div><div class='add'>+							!pll_settings-&gt;use_external_clk;</div><div class='add'>+			if (pix_clk_params-&gt;flags.SUPPORT_YCBCR420) {</div><div class='add'>+				bp_pc_params.flags.SUPPORT_YUV_420 = 1;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (clk_src-&gt;bios-&gt;funcs-&gt;set_pixel_clock(</div><div class='add'>+				clk_src-&gt;bios, &amp;bp_pc_params) != BP_RESULT_OK)</div><div class='add'>+			return false;</div><div class='add'>+		/* Resync deep color DTO */</div><div class='add'>+		if (clock_source-&gt;id != CLOCK_SOURCE_ID_DP_DTO)</div><div class='add'>+			dce112_program_pixel_clk_resync(clk_src,</div><div class='add'>+						pix_clk_params-&gt;signal_type,</div><div class='add'>+						pix_clk_params-&gt;color_depth,</div><div class='add'>+						pix_clk_params-&gt;flags.SUPPORT_YCBCR420);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool dce110_clock_source_power_down(</div><div class='ctx'> 		struct clock_source *clk_src)</div><div class='ctx'> {</div><div class='hunk'>@@ -1093,9 +1199,6 @@ static bool get_pixel_clk_frequency_100hz(</div><div class='ctx'> 	unsigned int modulo_hz = 0;</div><div class='ctx'> 	unsigned int dp_dto_ref_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz;</div><div class='ctx'> </div><div class='del'>-	if (clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz != 0)</div><div class='del'>-		dp_dto_ref_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz;</div><div class='del'>-</div><div class='ctx'> 	if (clock_source-&gt;id == CLOCK_SOURCE_ID_DP_DTO) {</div><div class='ctx'> 		clock_hz = REG_READ(PHASE[inst]);</div><div class='ctx'> </div><div class='hunk'>@@ -1314,6 +1417,13 @@ static const struct clock_source_funcs dcn31_clk_src_funcs = {</div><div class='ctx'> 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct clock_source_funcs dcn401_clk_src_funcs = {</div><div class='add'>+	.cs_power_down = dce110_clock_source_power_down,</div><div class='add'>+	.program_pix_clk = dcn401_program_pix_clk,</div><div class='add'>+	.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,</div><div class='add'>+	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*****************************************/</div><div class='ctx'> /* Constructor                           */</div><div class='ctx'> /*****************************************/</div><div class='hunk'>@@ -1731,6 +1841,21 @@ bool dcn31_clk_src_construct(</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dcn401_clk_src_construct(</div><div class='add'>+	struct dce110_clk_src *clk_src,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct dc_bios *bios,</div><div class='add'>+	enum clock_source_id id,</div><div class='add'>+	const struct dce110_clk_src_regs *regs,</div><div class='add'>+	const struct dce110_clk_src_shift *cs_shift,</div><div class='add'>+	const struct dce110_clk_src_mask *cs_mask)</div><div class='add'>+{</div><div class='add'>+	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);</div><div class='add'>+</div><div class='add'>+	clk_src-&gt;base.funcs = &amp;dcn401_clk_src_funcs;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='ctx'> bool dcn301_clk_src_construct(</div><div class='ctx'> 	struct dce110_clk_src *clk_src,</div><div class='ctx'> 	struct dc_context *ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h<br/>index f600b7431e23..94128f7a18b1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h</a></div><div class='hunk'>@@ -257,7 +257,7 @@ bool dce110_clk_src_construct(</div><div class='ctx'> 	struct dce110_clk_src *clk_src,</div><div class='ctx'> 	struct dc_context *ctx,</div><div class='ctx'> 	struct dc_bios *bios,</div><div class='del'>-	enum clock_source_id,</div><div class='add'>+	enum clock_source_id id,</div><div class='ctx'> 	const struct dce110_clk_src_regs *regs,</div><div class='ctx'> 	const struct dce110_clk_src_shift *cs_shift,</div><div class='ctx'> 	const struct dce110_clk_src_mask *cs_mask);</div><div class='hunk'>@@ -307,6 +307,14 @@ bool dcn31_clk_src_construct(</div><div class='ctx'> 	const struct dce110_clk_src_shift *cs_shift,</div><div class='ctx'> 	const struct dce110_clk_src_mask *cs_mask);</div><div class='ctx'> </div><div class='add'>+bool dcn401_clk_src_construct(</div><div class='add'>+	struct dce110_clk_src *clk_src,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct dc_bios *bios,</div><div class='add'>+	enum clock_source_id id,</div><div class='add'>+	const struct dce110_clk_src_regs *regs,</div><div class='add'>+	const struct dce110_clk_src_shift *cs_shift,</div><div class='add'>+	const struct dce110_clk_src_mask *cs_mask);</div><div class='ctx'> /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */</div><div class='ctx'> struct pixel_rate_range_table_entry {</div><div class='ctx'> 	unsigned int range_min_khz;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c<br/>index a8e79104b684..5f8fba45d98d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c</a></div><div class='hunk'>@@ -1126,7 +1126,7 @@ struct dmcu *dcn10_dmcu_create(</div><div class='ctx'> 	const struct dce_dmcu_shift *dmcu_shift,</div><div class='ctx'> 	const struct dce_dmcu_mask *dmcu_mask)</div><div class='ctx'> {</div><div class='del'>-	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);</div><div class='add'>+	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (dmcu_dce == NULL) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -1147,7 +1147,7 @@ struct dmcu *dcn20_dmcu_create(</div><div class='ctx'> 	const struct dce_dmcu_shift *dmcu_shift,</div><div class='ctx'> 	const struct dce_dmcu_mask *dmcu_mask)</div><div class='ctx'> {</div><div class='del'>-	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);</div><div class='add'>+	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (dmcu_dce == NULL) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -1168,7 +1168,7 @@ struct dmcu *dcn21_dmcu_create(</div><div class='ctx'> 	const struct dce_dmcu_shift *dmcu_shift,</div><div class='ctx'> 	const struct dce_dmcu_mask *dmcu_mask)</div><div class='ctx'> {</div><div class='del'>-	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);</div><div class='add'>+	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (dmcu_dce == NULL) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c<br/>index a2f48d46d199..365dd2e37aea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c</a></div><div class='hunk'>@@ -22,9 +22,6 @@</div><div class='ctx'>  * Authors: AMD</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "dce_i2c.h"</div><div class='ctx'> #include "dce_i2c_hw.h"</div><div class='hunk'>@@ -295,28 +292,51 @@ static void set_speed(</div><div class='ctx'> 			     FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool acquire_engine(struct dce_i2c_hw *dce_i2c_hw)</div><div class='add'>+{</div><div class='add'>+	uint32_t arbitrate = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &amp;arbitrate);</div><div class='add'>+	switch (arbitrate) {</div><div class='add'>+	case DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW:</div><div class='add'>+		return true;</div><div class='add'>+	case DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW:</div><div class='add'>+		return false;</div><div class='add'>+	case DC_I2C_STATUS__DC_I2C_STATUS_IDLE:</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, true);</div><div class='add'>+	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &amp;arbitrate);</div><div class='add'>+	if (arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool setup_engine(</div><div class='ctx'> 	struct dce_i2c_hw *dce_i2c_hw)</div><div class='ctx'> {</div><div class='add'>+	// Deassert soft reset to unblock I2C engine registers</div><div class='add'>+	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, false);</div><div class='add'>+</div><div class='ctx'> 	uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;</div><div class='ctx'> 	uint32_t  reset_length = 0;</div><div class='ctx'> </div><div class='del'>-        if (dce_i2c_hw-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.i2c) {</div><div class='del'>-	     if (dce_i2c_hw-&gt;regs-&gt;DIO_MEM_PWR_CTRL) {</div><div class='del'>-		     REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);</div><div class='del'>-		     REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);</div><div class='del'>-		     }</div><div class='del'>-	     }</div><div class='add'>+	if (dce_i2c_hw-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.i2c) {</div><div class='add'>+		if (dce_i2c_hw-&gt;regs-&gt;DIO_MEM_PWR_CTRL) {</div><div class='add'>+			REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);</div><div class='add'>+			REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (dce_i2c_hw-&gt;masks-&gt;DC_I2C_DDC1_CLK_EN)</div><div class='ctx'> 		REG_UPDATE_N(SETUP, 1,</div><div class='ctx'> 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN), 1);</div><div class='ctx'> </div><div class='del'>-	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/</div><div class='del'>-	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);</div><div class='del'>-</div><div class='del'>-	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/</div><div class='del'>-	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);</div><div class='add'>+	if (!acquire_engine(dce_i2c_hw))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	/*set SW requested I2c speed to default, if API calls in it will be override later*/</div><div class='ctx'> 	set_speed(dce_i2c_hw, dce_i2c_hw-&gt;ctx-&gt;dc-&gt;caps.i2c_speed_in_khz);</div><div class='hunk'>@@ -325,9 +345,8 @@ static bool setup_engine(</div><div class='ctx'> 		i2c_setup_limit = dce_i2c_hw-&gt;setup_limit;</div><div class='ctx'> </div><div class='ctx'> 	/* Program pin select */</div><div class='del'>-	REG_UPDATE_6(DC_I2C_CONTROL,</div><div class='add'>+	REG_UPDATE_5(DC_I2C_CONTROL,</div><div class='ctx'> 		     DC_I2C_GO, 0,</div><div class='del'>-		     DC_I2C_SOFT_RESET, 0,</div><div class='ctx'> 		     DC_I2C_SEND_RESET, 0,</div><div class='ctx'> 		     DC_I2C_SW_STATUS_RESET, 1,</div><div class='ctx'> 		     DC_I2C_TRANSACTION_COUNT, 0,</div><div class='hunk'>@@ -357,6 +376,32 @@ static bool setup_engine(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * cntl_stuck_hw_workaround - Workaround for I2C engine stuck state</div><div class='add'>+ * @dce_i2c_hw: Pointer to dce_i2c_hw structure</div><div class='add'>+ *</div><div class='add'>+ * If we boot without an HDMI display, the I2C engine does not get initialized</div><div class='add'>+ * correctly. One of its symptoms is that SW_USE_I2C does not get cleared after</div><div class='add'>+ * acquire. After setting SW_DONE_USING_I2C on release, the engine gets</div><div class='add'>+ * immediately reacquired by SW, preventing DMUB from using it.</div><div class='add'>+ *</div><div class='add'>+ * This function checks the I2C arbitration status and applies a release</div><div class='add'>+ * workaround if necessary.</div><div class='add'>+ */</div><div class='add'>+static void cntl_stuck_hw_workaround(struct dce_i2c_hw *dce_i2c_hw)</div><div class='add'>+{</div><div class='add'>+	uint32_t arbitrate = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &amp;arbitrate);</div><div class='add'>+	if (arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	// Still acquired after release, release again as a workaround</div><div class='add'>+	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);</div><div class='add'>+	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &amp;arbitrate);</div><div class='add'>+	ASSERT(arbitrate != DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void release_engine(</div><div class='ctx'> 	struct dce_i2c_hw *dce_i2c_hw)</div><div class='ctx'> {</div><div class='hunk'>@@ -384,9 +429,9 @@ static void release_engine(</div><div class='ctx'> </div><div class='ctx'> 	/*for HW HDCP Ri polling failure w/a test*/</div><div class='ctx'> 	set_speed(dce_i2c_hw, dce_i2c_hw-&gt;ctx-&gt;dc-&gt;caps.i2c_speed_in_khz_hdcp);</div><div class='del'>-	/* Release I2C after reset, so HW or DMCU could use it */</div><div class='del'>-	REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,</div><div class='del'>-		DC_I2C_SW_USE_I2C_REG_REQ, 0);</div><div class='add'>+	// Release I2C engine so it can be used by HW or DMCU, automatically clears SW_USE_I2C</div><div class='add'>+	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);</div><div class='add'>+	cntl_stuck_hw_workaround(dce_i2c_hw);</div><div class='ctx'> </div><div class='ctx'> 	if (dce_i2c_hw-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.i2c) {</div><div class='ctx'> 		if (dce_i2c_hw-&gt;regs-&gt;DIO_MEM_PWR_CTRL)</div><div class='hunk'>@@ -546,7 +591,7 @@ static bool dce_i2c_hw_engine_submit_payload(struct dce_i2c_hw *dce_i2c_hw,</div><div class='ctx'> 			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE;</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-	request.address = (uint8_t) ((payload-&gt;address &lt;&lt; 1) | !payload-&gt;write);</div><div class='add'>+	request.address = (uint8_t) ((payload-&gt;address &lt;&lt; 1) | (payload-&gt;write ? 0 : 1));</div><div class='ctx'> 	request.length = payload-&gt;length;</div><div class='ctx'> 	request.data = payload-&gt;data;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h<br/>index 3da32217d9ec..a9a16f645994 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h</a></div><div class='hunk'>@@ -249,6 +249,10 @@ struct dce_i2c_mask {</div><div class='ctx'> 	I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh),\</div><div class='ctx'> 	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN, mask_sh)</div><div class='ctx'> </div><div class='add'>+#define I2C_COMMON_MASK_SH_LIST_DCN401(mask_sh)\</div><div class='add'>+	I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh),\</div><div class='add'>+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN, mask_sh)</div><div class='add'>+</div><div class='ctx'> struct dce_i2c_registers {</div><div class='ctx'> 	uint32_t SETUP;</div><div class='ctx'> 	uint32_t SPEED;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c<br/>index e188447c8156..2d73b94c515c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c</a></div><div class='hunk'>@@ -451,7 +451,7 @@ static bool dce_i2c_sw_engine_submit_payload(struct dce_i2c_sw *engine,</div><div class='ctx'> 			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT :</div><div class='ctx'> 			DCE_I2C_TRANSACTION_ACTION_I2C_WRITE;</div><div class='ctx'> </div><div class='del'>-	request.address = (uint8_t) ((payload-&gt;address &lt;&lt; 1) | !payload-&gt;write);</div><div class='add'>+	request.address = (uint8_t) ((payload-&gt;address &lt;&lt; 1) | (payload-&gt;write ? 0 : 1));</div><div class='ctx'> 	request.length = payload-&gt;length;</div><div class='ctx'> 	request.data = payload-&gt;data;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c<br/>index 136bd93c3b65..87dbb8d7ed27 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c</a></div><div class='hunk'>@@ -302,6 +302,10 @@ static void setup_panel_mode(</div><div class='ctx'> 	if (ctx-&gt;dc-&gt;caps.psp_setup_panel_mode)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	/* The code below is only applicable to encoders with a digital transmitter. */</div><div class='add'>+	if (enc110-&gt;base.transmitter == TRANSMITTER_UNKNOWN)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	ASSERT(REG(DP_DPHY_INTERNAL_CTRL));</div><div class='ctx'> 	value = REG_READ(DP_DPHY_INTERNAL_CTRL);</div><div class='ctx'> </div><div class='hunk'>@@ -804,6 +808,33 @@ bool dce110_link_encoder_validate_dp_output(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool dce110_link_encoder_validate_rgb_output(</div><div class='add'>+	const struct dce110_link_encoder *enc110,</div><div class='add'>+	const struct dc_crtc_timing *crtc_timing)</div><div class='add'>+{</div><div class='add'>+	/* When the VBIOS doesn't specify any limits, use 400 MHz.</div><div class='add'>+	 * The value comes from amdgpu_atombios_get_clock_info.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t max_pixel_clock_khz = 400000;</div><div class='add'>+</div><div class='add'>+	if (enc110-&gt;base.ctx-&gt;dc_bios-&gt;fw_info_valid &amp;&amp;</div><div class='add'>+	    enc110-&gt;base.ctx-&gt;dc_bios-&gt;fw_info.max_pixel_clock) {</div><div class='add'>+		max_pixel_clock_khz =</div><div class='add'>+			enc110-&gt;base.ctx-&gt;dc_bios-&gt;fw_info.max_pixel_clock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (crtc_timing-&gt;pix_clk_100hz &gt; max_pixel_clock_khz * 10)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (crtc_timing-&gt;display_color_depth != COLOR_DEPTH_888)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (crtc_timing-&gt;pixel_encoding != PIXEL_ENCODING_RGB)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dce110_link_encoder_construct(</div><div class='ctx'> 	struct dce110_link_encoder *enc110,</div><div class='ctx'> 	const struct encoder_init_data *init_data,</div><div class='hunk'>@@ -824,6 +855,7 @@ void dce110_link_encoder_construct(</div><div class='ctx'> 	enc110-&gt;base.connector = init_data-&gt;connector;</div><div class='ctx'> </div><div class='ctx'> 	enc110-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='add'>+	enc110-&gt;base.analog_engine = init_data-&gt;analog_engine;</div><div class='ctx'> </div><div class='ctx'> 	enc110-&gt;base.features = *enc_features;</div><div class='ctx'> </div><div class='hunk'>@@ -847,6 +879,11 @@ void dce110_link_encoder_construct(</div><div class='ctx'> 		SIGNAL_TYPE_EDP |</div><div class='ctx'> 		SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='ctx'> </div><div class='add'>+	if ((enc110-&gt;base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII ||</div><div class='add'>+	     enc110-&gt;base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) &amp;&amp;</div><div class='add'>+		enc110-&gt;base.analog_engine != ENGINE_ID_UNKNOWN)</div><div class='add'>+		enc110-&gt;base.output_signals |= SIGNAL_TYPE_RGB;</div><div class='add'>+</div><div class='ctx'> 	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.</div><div class='ctx'> 	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.</div><div class='ctx'> 	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer</div><div class='hunk'>@@ -885,6 +922,13 @@ void dce110_link_encoder_construct(</div><div class='ctx'> 		enc110-&gt;base.preferred_engine = ENGINE_ID_DIGG;</div><div class='ctx'> 	break;</div><div class='ctx'> 	default:</div><div class='add'>+		if (init_data-&gt;analog_engine != ENGINE_ID_UNKNOWN) {</div><div class='add'>+			/* The connector is analog-only, ie. VGA */</div><div class='add'>+			enc110-&gt;base.preferred_engine = init_data-&gt;analog_engine;</div><div class='add'>+			enc110-&gt;base.output_signals = SIGNAL_TYPE_RGB;</div><div class='add'>+			enc110-&gt;base.transmitter = TRANSMITTER_UNKNOWN;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		enc110-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -896,13 +940,13 @@ void dce110_link_encoder_construct(</div><div class='ctx'> 						enc110-&gt;base.id, &amp;bp_cap_info);</div><div class='ctx'> </div><div class='ctx'> 	/* Override features with DCE-specific values */</div><div class='del'>-	if (BP_RESULT_OK == result) {</div><div class='add'>+	if (result == BP_RESULT_OK) {</div><div class='ctx'> 		enc110-&gt;base.features.flags.bits.IS_HBR2_CAPABLE =</div><div class='ctx'> 				bp_cap_info.DP_HBR2_EN;</div><div class='ctx'> 		enc110-&gt;base.features.flags.bits.IS_HBR3_CAPABLE =</div><div class='ctx'> 				bp_cap_info.DP_HBR3_EN;</div><div class='ctx'> 		enc110-&gt;base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;</div><div class='del'>-	} else {</div><div class='add'>+	} else if (result != BP_RESULT_NORECORD) {</div><div class='ctx'> 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",</div><div class='ctx'> 				__func__,</div><div class='ctx'> 				result);</div><div class='hunk'>@@ -939,6 +983,10 @@ bool dce110_link_encoder_validate_output_with_stream(</div><div class='ctx'> 		is_valid = dce110_link_encoder_validate_dp_output(</div><div class='ctx'> 					enc110, &amp;stream-&gt;timing);</div><div class='ctx'> 	break;</div><div class='add'>+	case SIGNAL_TYPE_RGB:</div><div class='add'>+		is_valid = dce110_link_encoder_validate_rgb_output(</div><div class='add'>+					enc110, &amp;stream-&gt;timing);</div><div class='add'>+	break;</div><div class='ctx'> 	case SIGNAL_TYPE_EDP:</div><div class='ctx'> 	case SIGNAL_TYPE_LVDS:</div><div class='ctx'> 		is_valid = stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_RGB;</div><div class='hunk'>@@ -969,6 +1017,10 @@ void dce110_link_encoder_hw_init(</div><div class='ctx'> 	cntl.coherent = false;</div><div class='ctx'> 	cntl.hpd_sel = enc110-&gt;base.hpd_source;</div><div class='ctx'> </div><div class='add'>+	/* The code below is only applicable to encoders with a digital transmitter. */</div><div class='add'>+	if (enc110-&gt;base.transmitter == TRANSMITTER_UNKNOWN)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (enc110-&gt;base.connector.id == CONNECTOR_ID_EDP)</div><div class='ctx'> 		cntl.signal = SIGNAL_TYPE_EDP;</div><div class='ctx'> </div><div class='hunk'>@@ -1034,6 +1086,8 @@ void dce110_link_encoder_setup(</div><div class='ctx'> 		/* DP MST */</div><div class='ctx'> 		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);</div><div class='ctx'> 		break;</div><div class='add'>+	case SIGNAL_TYPE_RGB:</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		/* invalid mode ! */</div><div class='hunk'>@@ -1282,6 +1336,24 @@ void dce110_link_encoder_disable_output(</div><div class='ctx'> 	struct bp_transmitter_control cntl = { 0 };</div><div class='ctx'> 	enum bp_result result;</div><div class='ctx'> </div><div class='add'>+	switch (enc-&gt;analog_engine) {</div><div class='add'>+	case ENGINE_ID_DACA:</div><div class='add'>+		REG_UPDATE(DAC_ENABLE, DAC_ENABLE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DACB:</div><div class='add'>+		/* DACB doesn't seem to be present on DCE6+,</div><div class='add'>+		 * although there are references to it in the register file.</div><div class='add'>+		 */</div><div class='add'>+		DC_LOG_ERROR("%s DACB is unsupported\n", __func__);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* The code below only applies to connectors that support digital signals. */</div><div class='add'>+	if (enc-&gt;transmitter == TRANSMITTER_UNKNOWN)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (!dce110_is_dig_enabled(enc)) {</div><div class='ctx'> 		/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1361,7 +1433,10 @@ void dce110_link_encoder_dp_set_lane_settings(</div><div class='ctx'> 		cntl.lane_settings = training_lane_set.raw;</div><div class='ctx'> </div><div class='ctx'> 		/* call VBIOS table to set voltage swing and pre-emphasis */</div><div class='del'>-		link_transmitter_control(enc110, &amp;cntl);</div><div class='add'>+		if (link_transmitter_control(enc110, &amp;cntl) != BP_RESULT_OK) {</div><div class='add'>+			DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", __func__);</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1723,6 +1798,7 @@ void dce60_link_encoder_construct(</div><div class='ctx'> 	enc110-&gt;base.connector = init_data-&gt;connector;</div><div class='ctx'> </div><div class='ctx'> 	enc110-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='add'>+	enc110-&gt;base.analog_engine = init_data-&gt;analog_engine;</div><div class='ctx'> </div><div class='ctx'> 	enc110-&gt;base.features = *enc_features;</div><div class='ctx'> </div><div class='hunk'>@@ -1746,6 +1822,11 @@ void dce60_link_encoder_construct(</div><div class='ctx'> 		SIGNAL_TYPE_EDP |</div><div class='ctx'> 		SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='ctx'> </div><div class='add'>+	if ((enc110-&gt;base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII ||</div><div class='add'>+	     enc110-&gt;base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) &amp;&amp;</div><div class='add'>+		enc110-&gt;base.analog_engine != ENGINE_ID_UNKNOWN)</div><div class='add'>+		enc110-&gt;base.output_signals |= SIGNAL_TYPE_RGB;</div><div class='add'>+</div><div class='ctx'> 	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.</div><div class='ctx'> 	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.</div><div class='ctx'> 	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer</div><div class='hunk'>@@ -1784,6 +1865,13 @@ void dce60_link_encoder_construct(</div><div class='ctx'> 		enc110-&gt;base.preferred_engine = ENGINE_ID_DIGG;</div><div class='ctx'> 	break;</div><div class='ctx'> 	default:</div><div class='add'>+		if (init_data-&gt;analog_engine != ENGINE_ID_UNKNOWN) {</div><div class='add'>+			/* The connector is analog-only, ie. VGA */</div><div class='add'>+			enc110-&gt;base.preferred_engine = init_data-&gt;analog_engine;</div><div class='add'>+			enc110-&gt;base.output_signals = SIGNAL_TYPE_RGB;</div><div class='add'>+			enc110-&gt;base.transmitter = TRANSMITTER_UNKNOWN;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		enc110-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1795,13 +1883,13 @@ void dce60_link_encoder_construct(</div><div class='ctx'> 						enc110-&gt;base.id, &amp;bp_cap_info);</div><div class='ctx'> </div><div class='ctx'> 	/* Override features with DCE-specific values */</div><div class='del'>-	if (BP_RESULT_OK == result) {</div><div class='add'>+	if (result == BP_RESULT_OK) {</div><div class='ctx'> 		enc110-&gt;base.features.flags.bits.IS_HBR2_CAPABLE =</div><div class='ctx'> 				bp_cap_info.DP_HBR2_EN;</div><div class='ctx'> 		enc110-&gt;base.features.flags.bits.IS_HBR3_CAPABLE =</div><div class='ctx'> 				bp_cap_info.DP_HBR3_EN;</div><div class='ctx'> 		enc110-&gt;base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;</div><div class='del'>-	} else {</div><div class='add'>+	} else if (result != BP_RESULT_NORECORD) {</div><div class='ctx'> 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",</div><div class='ctx'> 				__func__,</div><div class='ctx'> 				result);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h<br/>index 261c70e01e33..c58b69bc319b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h</a></div><div class='hunk'>@@ -101,18 +101,21 @@</div><div class='ctx'> 	SRI(DP_SEC_CNTL, DP, id), \</div><div class='ctx'> 	SRI(DP_VID_STREAM_CNTL, DP, id), \</div><div class='ctx'> 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \</div><div class='del'>-	SRI(DP_SEC_CNTL1, DP, id)</div><div class='add'>+	SRI(DP_SEC_CNTL1, DP, id), \</div><div class='add'>+	SR(DAC_ENABLE)</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #define LE_DCE80_REG_LIST(id)\</div><div class='ctx'> 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \</div><div class='del'>-	LE_COMMON_REG_LIST_BASE(id)</div><div class='add'>+	LE_COMMON_REG_LIST_BASE(id), \</div><div class='add'>+	SR(DAC_ENABLE)</div><div class='ctx'> </div><div class='ctx'> #define LE_DCE100_REG_LIST(id)\</div><div class='ctx'> 	LE_COMMON_REG_LIST_BASE(id), \</div><div class='ctx'> 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \</div><div class='ctx'> 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \</div><div class='del'>-	SR(DCI_MEM_PWR_STATUS)</div><div class='add'>+	SR(DCI_MEM_PWR_STATUS), \</div><div class='add'>+	SR(DAC_ENABLE)</div><div class='ctx'> </div><div class='ctx'> #define LE_DCE110_REG_LIST(id)\</div><div class='ctx'> 	LE_COMMON_REG_LIST_BASE(id), \</div><div class='hunk'>@@ -181,6 +184,9 @@ struct dce110_link_enc_registers {</div><div class='ctx'> 	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;</div><div class='ctx'> 	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;</div><div class='ctx'> 	uint32_t DP_SEC_CNTL1;</div><div class='add'>+</div><div class='add'>+	/* DAC registers */</div><div class='add'>+	uint32_t DAC_ENABLE;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dce110_link_encoder {</div><div class='hunk'>@@ -215,10 +221,6 @@ bool dce110_link_encoder_validate_dvi_output(</div><div class='ctx'> 	enum signal_type signal,</div><div class='ctx'> 	const struct dc_crtc_timing *crtc_timing);</div><div class='ctx'> </div><div class='del'>-bool dce110_link_encoder_validate_rgb_output(</div><div class='del'>-	const struct dce110_link_encoder *enc110,</div><div class='del'>-	const struct dc_crtc_timing *crtc_timing);</div><div class='del'>-</div><div class='ctx'> bool dce110_link_encoder_validate_dp_output(</div><div class='ctx'> 	const struct dce110_link_encoder *enc110,</div><div class='ctx'> 	const struct dc_crtc_timing *crtc_timing);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c<br/>index 4cdd4dacb761..1c2009e38aa1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c</a></div><div class='hunk'>@@ -98,7 +98,7 @@ static enum mi_bits_per_pixel get_mi_bpp(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum mi_tiling_format get_mi_tiling(</div><div class='del'>-		union dc_tiling_info *tiling_info)</div><div class='add'>+		struct dc_tiling_info *tiling_info)</div><div class='ctx'> {</div><div class='ctx'> 	switch (tiling_info-&gt;gfx8.array_mode) {</div><div class='ctx'> 	case DC_ARRAY_1D_TILED_THIN1:</div><div class='hunk'>@@ -133,7 +133,7 @@ static bool is_vert_scan(enum dc_rotation_angle rotation)</div><div class='ctx'> static void dce_mi_program_pte_vm(</div><div class='ctx'> 		struct mem_input *mi,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		enum dc_rotation_angle rotation)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);</div><div class='hunk'>@@ -430,7 +430,7 @@ static void dce120_mi_program_display_marks(struct mem_input *mi,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void program_tiling(</div><div class='del'>-	struct dce_mem_input *dce_mi, const union dc_tiling_info *info)</div><div class='add'>+	struct dce_mem_input *dce_mi, const struct dc_tiling_info *info)</div><div class='ctx'> {</div><div class='ctx'> 	if (dce_mi-&gt;masks-&gt;GRPH_SW_MODE) { /* GFX9 */</div><div class='ctx'> 		REG_UPDATE_6(GRPH_CONTROL,</div><div class='hunk'>@@ -481,7 +481,6 @@ static void program_tiling(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> static void program_size_and_rotation(</div><div class='ctx'> 	struct dce_mem_input *dce_mi,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='hunk'>@@ -627,10 +626,31 @@ static void program_grph_pixel_format(</div><div class='ctx'> 			GRPH_PRESCALE_B_SIGN, sign);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dce_mi_clear_tiling(</div><div class='add'>+	struct mem_input *mi)</div><div class='add'>+{</div><div class='add'>+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);</div><div class='add'>+</div><div class='add'>+	if (dce_mi-&gt;masks-&gt;GRPH_SW_MODE) { /* GFX9 */</div><div class='add'>+		REG_UPDATE(GRPH_CONTROL,</div><div class='add'>+			   GRPH_SW_MODE, DC_SW_LINEAR);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dce_mi-&gt;masks-&gt;GRPH_MICRO_TILE_MODE) { /* GFX8 */</div><div class='add'>+		REG_UPDATE(GRPH_CONTROL,</div><div class='add'>+			   GRPH_ARRAY_MODE, DC_SW_LINEAR);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dce_mi-&gt;masks-&gt;GRPH_ARRAY_MODE) { /* GFX6 but reuses gfx8 struct */</div><div class='add'>+		REG_UPDATE(GRPH_CONTROL,</div><div class='add'>+			   GRPH_ARRAY_MODE, DC_SW_LINEAR);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dce_mi_program_surface_config(</div><div class='ctx'> 	struct mem_input *mi,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -642,8 +662,7 @@ static void dce_mi_program_surface_config(</div><div class='ctx'> 	program_tiling(dce_mi, tiling_info);</div><div class='ctx'> 	program_size_and_rotation(dce_mi, rotation, plane_size);</div><div class='ctx'> </div><div class='del'>-	if (format &gt;= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &amp;&amp;</div><div class='del'>-		format &lt; SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='add'>+	if (format &lt; SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='ctx'> 		program_grph_pixel_format(dce_mi, format);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -651,7 +670,7 @@ static void dce_mi_program_surface_config(</div><div class='ctx'> static void dce60_mi_program_surface_config(</div><div class='ctx'> 	struct mem_input *mi,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation, /* not used in DCE6 */</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -663,8 +682,7 @@ static void dce60_mi_program_surface_config(</div><div class='ctx'> 	program_tiling(dce_mi, tiling_info);</div><div class='ctx'> 	dce60_program_size(dce_mi, rotation, plane_size);</div><div class='ctx'> </div><div class='del'>-	if (format &gt;= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &amp;&amp;</div><div class='del'>-		format &lt; SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='add'>+	if (format &lt; SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='ctx'> 		program_grph_pixel_format(dce_mi, format);</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='hunk'>@@ -886,7 +904,8 @@ static const struct mem_input_funcs dce_mi_funcs = {</div><div class='ctx'> 	.mem_input_program_pte_vm = dce_mi_program_pte_vm,</div><div class='ctx'> 	.mem_input_program_surface_config =</div><div class='ctx'> 			dce_mi_program_surface_config,</div><div class='del'>-	.mem_input_is_flip_pending = dce_mi_is_flip_pending</div><div class='add'>+	.mem_input_is_flip_pending = dce_mi_is_flip_pending,</div><div class='add'>+	.mem_input_clear_tiling = dce_mi_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_SI)</div><div class='hunk'>@@ -899,7 +918,8 @@ static const struct mem_input_funcs dce60_mi_funcs = {</div><div class='ctx'> 	.mem_input_program_pte_vm = dce_mi_program_pte_vm,</div><div class='ctx'> 	.mem_input_program_surface_config =</div><div class='ctx'> 			dce60_mi_program_surface_config,</div><div class='del'>-	.mem_input_is_flip_pending = dce_mi_is_flip_pending</div><div class='add'>+	.mem_input_is_flip_pending = dce_mi_is_flip_pending,</div><div class='add'>+	.mem_input_clear_tiling = dce_mi_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -912,7 +932,8 @@ static const struct mem_input_funcs dce112_mi_funcs = {</div><div class='ctx'> 	.mem_input_program_pte_vm = dce_mi_program_pte_vm,</div><div class='ctx'> 	.mem_input_program_surface_config =</div><div class='ctx'> 			dce_mi_program_surface_config,</div><div class='del'>-	.mem_input_is_flip_pending = dce_mi_is_flip_pending</div><div class='add'>+	.mem_input_is_flip_pending = dce_mi_is_flip_pending,</div><div class='add'>+	.mem_input_clear_tiling = dce_mi_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mem_input_funcs dce120_mi_funcs = {</div><div class='hunk'>@@ -924,7 +945,8 @@ static const struct mem_input_funcs dce120_mi_funcs = {</div><div class='ctx'> 	.mem_input_program_pte_vm = dce_mi_program_pte_vm,</div><div class='ctx'> 	.mem_input_program_surface_config =</div><div class='ctx'> 			dce_mi_program_surface_config,</div><div class='del'>-	.mem_input_is_flip_pending = dce_mi_is_flip_pending</div><div class='add'>+	.mem_input_is_flip_pending = dce_mi_is_flip_pending,</div><div class='add'>+	.mem_input_clear_tiling = dce_mi_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dce_mem_input_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h<br/>index f98400efdd9b..e34e445a4013 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h</a></div><div class='hunk'>@@ -181,6 +181,7 @@ struct dce_mem_input_registers {</div><div class='ctx'> 	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\</div><div class='ctx'> 	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\</div><div class='ctx'> 	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\</div><div class='add'>+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\</div><div class='ctx'> 	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\</div><div class='ctx'> 	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\</div><div class='ctx'> 	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c<br/>index 63ae4bc2a2e5..f342da5a5e50 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_opp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_opp.c</a></div><div class='hunk'>@@ -575,7 +575,6 @@ static void dce60_opp_program_clamping_and_pixel_encoding(</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> static void program_formatter_420_memory(struct output_pixel_processor *opp)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h<br/>index bf1ffc3629c7..3d9be87aae45 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_opp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_opp.h</a></div><div class='hunk'>@@ -111,6 +111,7 @@ enum dce110_opp_reg_type {</div><div class='ctx'> 	OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\</div><div class='ctx'> 	OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\</div><div class='ctx'> 	OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\</div><div class='add'>+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\</div><div class='ctx'> 	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\</div><div class='ctx'> 	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\</div><div class='ctx'> 	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c<br/>index 5bca67407c5b..de31fb1b6819 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c</a></div><div class='hunk'>@@ -218,7 +218,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,</div><div class='ctx'> 	 * contain integer component, lower 16 bits contain fractional component</div><div class='ctx'> 	 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24</div><div class='ctx'> 	 */</div><div class='del'>-	active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;</div><div class='add'>+	active_duty_cycle = backlight_pwm_u16_16 * (uint64_t)masked_pwm_period;</div><div class='ctx'> </div><div class='ctx'> 	/* 1.3 Calculate 16 bit active duty cycle from integer and fractional</div><div class='ctx'> 	 * components shift by bitCount then mask 16 bits and add rounding bit</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c<br/>index f810825322ba..574618d5d4a4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c</a></div><div class='hunk'>@@ -277,7 +277,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 	uint32_t misc1 = 0;</div><div class='ctx'> 	uint32_t h_blank;</div><div class='ctx'> 	uint32_t h_back_porch;</div><div class='del'>-	uint8_t synchronous_clock = 0; /* asynchronous mode */</div><div class='ctx'> 	uint8_t colorimetry_bpc;</div><div class='ctx'> 	uint8_t dynamic_range_rgb = 0; /*full range*/</div><div class='ctx'> 	uint8_t dynamic_range_ycbcr = 1; /*bt709*/</div><div class='hunk'>@@ -380,7 +379,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	misc0 = misc0 | synchronous_clock;</div><div class='ctx'> 	misc0 = colorimetry_bpc &lt;&lt; 5;</div><div class='ctx'> </div><div class='ctx'> 	if (REG(DP_MSA_TIMING_PARAM1)) {</div><div class='hunk'>@@ -420,7 +418,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 			dynamic_range_rgb = 1; /*limited range*/</div><div class='ctx'> 			break;</div><div class='ctx'> 		case COLOR_SPACE_2020_RGB_FULLRANGE:</div><div class='del'>-		case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+		case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='ctx'> 		case COLOR_SPACE_XR_RGB:</div><div class='ctx'> 		case COLOR_SPACE_MSREF_SCRGB:</div><div class='ctx'> 		case COLOR_SPACE_ADOBERGB:</div><div class='hunk'>@@ -432,6 +430,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 		case COLOR_SPACE_APPCTRL:</div><div class='ctx'> 		case COLOR_SPACE_CUSTOMPOINTS:</div><div class='ctx'> 		case COLOR_SPACE_UNKNOWN:</div><div class='add'>+		default:</div><div class='ctx'> 			/* do nothing */</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1025,6 +1024,7 @@ static void dce110_reset_hdmi_stream_attribute(</div><div class='ctx'> 	struct stream_encoder *enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='ctx'> 	if (enc110-&gt;se_mask-&gt;HDMI_DATA_SCRAMBLE_EN)</div><div class='ctx'> 		REG_UPDATE_5(HDMI_CONTROL,</div><div class='ctx'> 			HDMI_PACKET_GEN_VERSION, 1,</div><div class='hunk'>@@ -1567,3 +1567,17 @@ void dce110_stream_encoder_construct(</div><div class='ctx'> 	enc110-&gt;se_shift = se_shift;</div><div class='ctx'> 	enc110-&gt;se_mask = se_mask;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static const struct stream_encoder_funcs dce110_an_str_enc_funcs = {};</div><div class='add'>+</div><div class='add'>+void dce110_analog_stream_encoder_construct(</div><div class='add'>+	struct dce110_stream_encoder *enc110,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct dc_bios *bp,</div><div class='add'>+	enum engine_id eng_id)</div><div class='add'>+{</div><div class='add'>+	enc110-&gt;base.funcs = &amp;dce110_an_str_enc_funcs;</div><div class='add'>+	enc110-&gt;base.ctx = ctx;</div><div class='add'>+	enc110-&gt;base.id = eng_id;</div><div class='add'>+	enc110-&gt;base.bp = bp;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h<br/>index cc5020a8e1e1..068de1392121 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h</a></div><div class='hunk'>@@ -708,6 +708,11 @@ void dce110_stream_encoder_construct(</div><div class='ctx'> 	const struct dce_stream_encoder_shift *se_shift,</div><div class='ctx'> 	const struct dce_stream_encoder_mask *se_mask);</div><div class='ctx'> </div><div class='add'>+void dce110_analog_stream_encoder_construct(</div><div class='add'>+	struct dce110_stream_encoder *enc110,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct dc_bios *bp,</div><div class='add'>+	enum engine_id eng_id);</div><div class='ctx'> </div><div class='ctx'> void dce110_se_audio_mute_control(</div><div class='ctx'> 	struct stream_encoder *enc, bool mute);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c<br/>index 670d5ab9d998..1ab5ae9b5ea5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_transform.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_transform.c</a></div><div class='hunk'>@@ -154,10 +154,13 @@ static bool dce60_setup_scaling_configuration(</div><div class='ctx'> 	REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (data-&gt;taps.h_taps + data-&gt;taps.v_taps &lt;= 2) {</div><div class='del'>-		/* Set bypass */</div><div class='del'>-</div><div class='del'>-		/* DCE6 has no SCL_MODE register, skip scale mode programming */</div><div class='add'>+		/* Disable scaler functionality */</div><div class='add'>+		REG_WRITE(SCL_SCALER_ENABLE, 0);</div><div class='ctx'> </div><div class='add'>+		/* Clear registers that can cause glitches even when the scaler is off */</div><div class='add'>+		REG_WRITE(SCL_TAP_CONTROL, 0);</div><div class='add'>+		REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);</div><div class='add'>+		REG_WRITE(SCL_F_SHARP_CONTROL, 0);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -165,7 +168,7 @@ static bool dce60_setup_scaling_configuration(</div><div class='ctx'> 			SCL_H_NUM_OF_TAPS, data-&gt;taps.h_taps - 1,</div><div class='ctx'> 			SCL_V_NUM_OF_TAPS, data-&gt;taps.v_taps - 1);</div><div class='ctx'> </div><div class='del'>-	/* DCE6 has no SCL_MODE register, skip scale mode programming */</div><div class='add'>+	REG_WRITE(SCL_SCALER_ENABLE, 1);</div><div class='ctx'> </div><div class='ctx'> 	/* DCE6 has no SCL_BOUNDARY_MODE bit, skip replace out of bound pixels */</div><div class='ctx'> </div><div class='hunk'>@@ -502,6 +505,8 @@ static void dce60_transform_set_scaler(</div><div class='ctx'> 	REG_SET(DC_LB_MEM_SIZE, 0,</div><div class='ctx'> 		DC_LB_MEM_SIZE, xfm_dce-&gt;lb_memory_size);</div><div class='ctx'> </div><div class='add'>+	REG_WRITE(SCL_UPDATE, 0x00010000);</div><div class='add'>+</div><div class='ctx'> 	/* Clear SCL_F_SHARP_CONTROL value to 0 */</div><div class='ctx'> 	REG_WRITE(SCL_F_SHARP_CONTROL, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -527,8 +532,7 @@ static void dce60_transform_set_scaler(</div><div class='ctx'> 		if (coeffs_v != xfm_dce-&gt;filter_v || coeffs_h != xfm_dce-&gt;filter_h) {</div><div class='ctx'> 			/* 4. Program vertical filters */</div><div class='ctx'> 			if (xfm_dce-&gt;filter_v == NULL)</div><div class='del'>-				REG_SET(SCL_VERT_FILTER_CONTROL, 0,</div><div class='del'>-						SCL_V_2TAP_HARDCODE_COEF_EN, 0);</div><div class='add'>+				REG_WRITE(SCL_VERT_FILTER_CONTROL, 0);</div><div class='ctx'> 			program_multi_taps_filter(</div><div class='ctx'> 					xfm_dce,</div><div class='ctx'> 					data-&gt;taps.v_taps,</div><div class='hunk'>@@ -542,8 +546,7 @@ static void dce60_transform_set_scaler(</div><div class='ctx'> </div><div class='ctx'> 			/* 5. Program horizontal filters */</div><div class='ctx'> 			if (xfm_dce-&gt;filter_h == NULL)</div><div class='del'>-				REG_SET(SCL_HORZ_FILTER_CONTROL, 0,</div><div class='del'>-						SCL_H_2TAP_HARDCODE_COEF_EN, 0);</div><div class='add'>+				REG_WRITE(SCL_HORZ_FILTER_CONTROL, 0);</div><div class='ctx'> 			program_multi_taps_filter(</div><div class='ctx'> 					xfm_dce,</div><div class='ctx'> 					data-&gt;taps.h_taps,</div><div class='hunk'>@@ -566,6 +569,8 @@ static void dce60_transform_set_scaler(</div><div class='ctx'> 	/* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient memory */</div><div class='ctx'> </div><div class='ctx'> 	/* DCE6 DATA_FORMAT register does not support ALPHA_EN */</div><div class='add'>+</div><div class='add'>+	REG_WRITE(SCL_UPDATE, 0);</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -1408,7 +1413,7 @@ void dce110_opp_set_csc_default(</div><div class='ctx'> static void program_pwl(struct dce_transform *xfm_dce,</div><div class='ctx'> 			const struct pwl_params *params)</div><div class='ctx'> {</div><div class='del'>-	int retval;</div><div class='add'>+	uint32_t retval;</div><div class='ctx'> 	uint8_t max_tries = 10;</div><div class='ctx'> 	uint8_t counter = 0;</div><div class='ctx'> 	uint32_t i = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h<br/>index cbce194ec7b8..eb716e8337e2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dce_transform.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dce_transform.h</a></div><div class='hunk'>@@ -155,6 +155,9 @@</div><div class='ctx'> 	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \</div><div class='ctx'> 	SRI(VIEWPORT_START, SCL, id), \</div><div class='ctx'> 	SRI(VIEWPORT_SIZE, SCL, id), \</div><div class='add'>+	SRI(SCL_SCALER_ENABLE, SCL, id), \</div><div class='add'>+	SRI(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL, id), \</div><div class='add'>+	SRI(SCL_HORZ_FILTER_INIT_CHROMA, SCL, id), \</div><div class='ctx'> 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \</div><div class='ctx'> 	SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \</div><div class='ctx'> 	SRI(SCL_VERT_FILTER_INIT, SCL, id), \</div><div class='hunk'>@@ -590,6 +593,7 @@ struct dce_transform_registers {</div><div class='ctx'> 	uint32_t SCL_VERT_FILTER_SCALE_RATIO;</div><div class='ctx'> 	uint32_t SCL_HORZ_FILTER_INIT;</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_SI)</div><div class='add'>+	uint32_t SCL_SCALER_ENABLE;</div><div class='ctx'> 	uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;</div><div class='ctx'> 	uint32_t SCL_HORZ_FILTER_INIT_CHROMA;</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c<br/>index ccc154b0281c..3b9011ef9b68 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c</a></div><div class='hunk'>@@ -28,6 +28,8 @@</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dmub_cmd.h"</div><div class='add'>+#include "dc_dmub_srv.h"</div><div class='add'>+#include "dmub/dmub_srv.h"</div><div class='ctx'> </div><div class='ctx'> #define TO_DMUB_ABM(abm)\</div><div class='ctx'> 	container_of(abm, struct dce_abm, base)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c<br/>index f9d6a181164a..a641ae04450c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c</a></div><div class='hunk'>@@ -34,11 +34,7 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "fixed31_32.h"</div><div class='ctx'> </div><div class='del'>-#ifdef _WIN32</div><div class='del'>-#include "atombios.h"</div><div class='del'>-#else</div><div class='ctx'> #include "atom.h"</div><div class='del'>-#endif</div><div class='ctx'> </div><div class='ctx'> #define TO_DMUB_ABM(abm)\</div><div class='ctx'> 	container_of(abm, struct dce_abm, base)</div><div class='hunk'>@@ -244,7 +240,8 @@ bool dmub_abm_save_restore(</div><div class='ctx'> 	cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;</div><div class='ctx'> 	cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask;</div><div class='ctx'> </div><div class='del'>-	cmd.abm_save_restore.header.payload_bytes = sizeof(struct dmub_rb_cmd_abm_save_restore);</div><div class='add'>+	cmd.abm_save_restore.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_abm_save_restore) - sizeof(struct dmub_cmd_header);</div><div class='ctx'> </div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='hunk'>@@ -262,7 +259,7 @@ bool dmub_abm_set_pipe(struct abm *abm,</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct dc_context *dc = abm-&gt;ctx;</div><div class='del'>-	uint32_t ramping_boundary = 0xFFFF;</div><div class='add'>+	uint8_t ramping_boundary = 0xFF;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;</div><div class='hunk'>@@ -301,3 +298,21 @@ bool dmub_abm_set_backlight_level(struct abm *abm,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned int scaling_strength_map,</div><div class='add'>+		unsigned int panel_inst)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	struct dc_context *dc = abm-&gt;ctx;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+	cmd.abm_set_event.header.type = DMUB_CMD__ABM;</div><div class='add'>+	cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT;</div><div class='add'>+	cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable;</div><div class='add'>+	cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map;</div><div class='add'>+	cmd.abm_set_event.abm_set_event_data.panel_mask = (1&lt;&lt;panel_inst);</div><div class='add'>+	cmd.abm_set_event.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_event_data);</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h<br/>index 761685e5b8c9..13f54f1df780 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h</a></div><div class='hunk'>@@ -49,4 +49,6 @@ bool dmub_abm_set_backlight_level(struct abm *abm,</div><div class='ctx'> 		unsigned int backlight_pwm_u16_16,</div><div class='ctx'> 		unsigned int frame_ramp,</div><div class='ctx'> 		unsigned int panel_inst);</div><div class='add'>+bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned int scaling_strength_map,</div><div class='add'>+		unsigned int panel_inst);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c<br/>index bf636b28e3e1..5bfa2b0d2afd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c</a></div><div class='hunk'>@@ -61,13 +61,49 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,</div><div class='ctx'> 	dc_dmub_srv_wait_for_inbox0_ack(dmub_srv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool should_use_dmub_lock(struct dc_link *link)</div><div class='add'>+bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link)</div><div class='ctx'> {</div><div class='add'>+	if (!link)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	if (link-&gt;replay_settings.replay_feature_enabled)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1) {</div><div class='add'>+		struct dc_link *edp_links[MAX_NUM_EDP];</div><div class='add'>+		int edp_num;</div><div class='add'>+</div><div class='add'>+		dc_get_edp_links(dc, edp_links, &amp;edp_num);</div><div class='add'>+		if (edp_num == 1)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	if (!context)</div><div class='add'>+		return false;</div><div class='add'>+	for (int i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		const struct dc_link *link = context-&gt;streams[i]-&gt;link;</div><div class='add'>+</div><div class='add'>+		if (dmub_hw_lock_mgr_does_link_require_lock(dc, link))</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	/* ASIC doesn't support DMUB */</div><div class='add'>+	if (!dc-&gt;ctx-&gt;dmub_srv)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_4_01)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return dmub_hw_lock_mgr_does_link_require_lock(dc, link);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h<br/>index 5a72b168fb4a..4c80ca8484ad 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h</a></div><div class='hunk'>@@ -37,6 +37,16 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,</div><div class='ctx'> void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,</div><div class='ctx'> 		union dmub_inbox0_cmd_lock_hw hw_lock_cmd);</div><div class='ctx'> </div><div class='del'>-bool should_use_dmub_lock(struct dc_link *link);</div><div class='add'>+/**</div><div class='add'>+ * should_use_dmub_inbox1_lock() - Checks if the DMCUB hardware lock via inbox1 should be used.</div><div class='add'>+ *</div><div class='add'>+ * @dc: pointer to DC object</div><div class='add'>+ * @link: optional pointer to the link object to check for enabled link features</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the inbox1 lock should be used, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link);</div><div class='add'>+bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link);</div><div class='add'>+bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DMUB_HW_LOCK_MGR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c<br/>index 3e243e407bb8..87af4fdc04a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c</a></div><div class='hunk'>@@ -94,6 +94,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)</div><div class='ctx'> 		state = PSR_STATE_HWLOCK_MGR;</div><div class='ctx'> 	else if (raw_state == 0x61)</div><div class='ctx'> 		state = PSR_STATE_POLLVUPDATE;</div><div class='add'>+	else if (raw_state == 0x62)</div><div class='add'>+		state = PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME;</div><div class='ctx'> 	else</div><div class='ctx'> 		state = PSR_STATE_INVALID;</div><div class='ctx'> </div><div class='hunk'>@@ -363,6 +365,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,</div><div class='ctx'> 	copy_settings_data-&gt;debug.bitfields.visual_confirm	= dc-&gt;dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_PSR;</div><div class='ctx'> 	copy_settings_data-&gt;debug.bitfields.use_hw_lock_mgr		= 1;</div><div class='ctx'> 	copy_settings_data-&gt;debug.bitfields.force_full_frame_update	= 0;</div><div class='add'>+	copy_settings_data-&gt;debug.bitfields.enable_ips_visual_confirm = dc-&gt;dc-&gt;debug.enable_ips_visual_confirm;</div><div class='ctx'> </div><div class='ctx'> 	if (psr_context-&gt;su_granularity_required == 0)</div><div class='ctx'> 		copy_settings_data-&gt;su_y_granularity = 0;</div><div class='hunk'>@@ -387,9 +390,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,</div><div class='ctx'> 		!memcmp(link-&gt;dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,</div><div class='ctx'> 			sizeof(DP_SINK_DEVICE_STR_ID_1)))</div><div class='ctx'> 		link-&gt;psr_settings.force_ffu_mode = 1;</div><div class='del'>-	else</div><div class='del'>-		link-&gt;psr_settings.force_ffu_mode = 0;</div><div class='del'>-	copy_settings_data-&gt;force_ffu_mode = link-&gt;psr_settings.force_ffu_mode;</div><div class='add'>+</div><div class='add'>+	copy_settings_data-&gt;force_ffu_mode = link-&gt;psr_settings.force_ffu_mode || psr_context-&gt;os_request_force_ffu;</div><div class='ctx'> </div><div class='ctx'> 	if (((link-&gt;dpcd_caps.fec_cap.bits.FEC_CAPABLE &amp;&amp;</div><div class='ctx'> 		!link-&gt;dc-&gt;debug.disable_fec) &amp;&amp;</div><div class='hunk'>@@ -416,6 +418,10 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,</div><div class='ctx'> 	copy_settings_data-&gt;relock_delay_frame_cnt = 0;</div><div class='ctx'> 	if (link-&gt;dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)</div><div class='ctx'> 		copy_settings_data-&gt;relock_delay_frame_cnt = 2;</div><div class='add'>+</div><div class='add'>+	copy_settings_data-&gt;power_down_phy_before_disable_stream =</div><div class='add'>+		link-&gt;psr_settings.power_down_phy_before_disable_stream;</div><div class='add'>+</div><div class='ctx'> 	copy_settings_data-&gt;dsc_slice_height = psr_context-&gt;dsc_slice_height;</div><div class='ctx'> </div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='hunk'>@@ -445,10 +451,13 @@ static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)</div><div class='ctx'> /*</div><div class='ctx'>  * Get PSR residency from firmware.</div><div class='ctx'>  */</div><div class='del'>-static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)</div><div class='add'>+static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency,</div><div class='add'>+	uint8_t panel_inst, enum psr_residency_mode mode)</div><div class='ctx'> {</div><div class='ctx'> 	uint16_t param = (uint16_t)(panel_inst &lt;&lt; 8);</div><div class='ctx'> </div><div class='add'>+	param |= mode;</div><div class='add'>+</div><div class='ctx'> 	/* Send gpint command and wait for ack */</div><div class='ctx'> 	dc_wake_and_execute_gpint(dmub-&gt;ctx, DMUB_GPINT__PSR_RESIDENCY, param, residency,</div><div class='ctx'> 				  DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h<br/>index 289e42070ece..a6e282d950c3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> #define _DMUB_PSR_H_</div><div class='ctx'> </div><div class='ctx'> #include "dc_types.h"</div><div class='add'>+#include "dmub_cmd.h"</div><div class='ctx'> struct dc_link;</div><div class='ctx'> struct dmub_psr_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -46,7 +47,7 @@ struct dmub_psr_funcs {</div><div class='ctx'> 	uint8_t panel_inst);</div><div class='ctx'> 	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);</div><div class='ctx'> 	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,</div><div class='del'>-	uint8_t panel_inst);</div><div class='add'>+	uint8_t panel_inst,  enum psr_residency_mode mode);</div><div class='ctx'> 	void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,</div><div class='ctx'> 	uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);</div><div class='ctx'> 	void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c<br/>index b010814706fe..cf1372aaff6c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c</a></div><div class='hunk'>@@ -1,29 +1,9 @@</div><div class='del'>-/*</div><div class='del'>- * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- * Authors: AMD</div><div class='del'>- *</div><div class='del'>- */</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='ctx'> </div><div class='ctx'> #include "dc.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "dmub/dmub_srv.h"</div><div class='ctx'> #include "core_types.h"</div><div class='hunk'>@@ -33,26 +13,25 @@</div><div class='ctx'> </div><div class='ctx'> #define MAX_PIPES 6</div><div class='ctx'> </div><div class='add'>+#define GPINT_RETRY_NUM 20</div><div class='add'>+</div><div class='add'>+static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};</div><div class='add'>+static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Get Replay state from firmware.</div><div class='ctx'>  */</div><div class='ctx'> static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *srv = dmub-&gt;ctx-&gt;dmub_srv-&gt;dmub;</div><div class='del'>-	/* uint32_t raw_state = 0; */</div><div class='ctx'> 	uint32_t retry_count = 0;</div><div class='del'>-	enum dmub_status status;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		// Send gpint command and wait for ack</div><div class='del'>-		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, 30);</div><div class='del'>-</div><div class='del'>-		if (status == DMUB_STATUS_OK) {</div><div class='del'>-			// GPINT was executed, get response</div><div class='del'>-			dmub_srv_get_gpint_response(srv, (uint32_t *)state);</div><div class='del'>-		} else</div><div class='add'>+		if (!dc_wake_and_execute_gpint(dmub-&gt;ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst,</div><div class='add'>+					       (uint32_t *)state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {</div><div class='ctx'> 			// Return invalid state when GPINT times out</div><div class='ctx'> 			*state = REPLAY_STATE_INVALID;</div><div class='add'>+		}</div><div class='ctx'> 	} while (++retry_count &lt;= 1000 &amp;&amp; *state == REPLAY_STATE_INVALID);</div><div class='ctx'> </div><div class='ctx'> 	// Assert if max retry hit</div><div class='hunk'>@@ -84,7 +63,7 @@ static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait,</div><div class='ctx'> </div><div class='ctx'> 	cmd.replay_enable.header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_enable_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	/* Below loops 1000 x 500us = 500 ms.</div><div class='ctx'> 	 *  Exit REPLAY may need to wait 1-2 frames to power up. Timeout after at</div><div class='hunk'>@@ -102,14 +81,14 @@ static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait,</div><div class='ctx'> 					break;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			fsleep(500);</div><div class='add'>+			/* must *not* be fsleep - this can be called from high irq levels */</div><div class='add'>+			udelay(500);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* assert if max retry hit */</div><div class='ctx'> 		if (retry_count &gt;= 1000)</div><div class='ctx'> 			ASSERT(0);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -127,7 +106,7 @@ static void dmub_replay_set_power_opt(struct dmub_replay *dmub, unsigned int pow</div><div class='ctx'> 	cmd.replay_set_power_opt.replay_set_power_opt_data.power_opt = power_opt;</div><div class='ctx'> 	cmd.replay_set_power_opt.replay_set_power_opt_data.panel_inst = panel_inst;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -190,6 +169,9 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,</div><div class='ctx'> 	copy_settings_data-&gt;max_deviation_line			= link-&gt;dpcd_caps.pr_info.max_deviation_line;</div><div class='ctx'> 	copy_settings_data-&gt;smu_optimizations_en		= link-&gt;replay_settings.replay_smu_opt_enable;</div><div class='ctx'> 	copy_settings_data-&gt;replay_timing_sync_supported = link-&gt;replay_settings.config.replay_timing_sync_supported;</div><div class='add'>+	copy_settings_data-&gt;replay_support_fast_resync_in_ultra_sleep_mode = link-&gt;replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode;</div><div class='add'>+</div><div class='add'>+	copy_settings_data-&gt;debug.bitfields.enable_ips_visual_confirm = dc-&gt;dc-&gt;debug.enable_ips_visual_confirm;</div><div class='ctx'> </div><div class='ctx'> 	copy_settings_data-&gt;flags.u32All = 0;</div><div class='ctx'> 	copy_settings_data-&gt;flags.bitfields.fec_enable_status = (link-&gt;fec_state == dc_link_fec_enabled);</div><div class='hunk'>@@ -200,17 +182,28 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,</div><div class='ctx'> 		(link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &amp;&amp;</div><div class='ctx'> 		!link-&gt;panel_config.dsc.disable_dsc_edp &amp;&amp;</div><div class='ctx'> 		link-&gt;dc-&gt;caps.edp_dsc_support)) &amp;&amp;</div><div class='del'>-		link-&gt;dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 /*&amp;&amp;</div><div class='add'>+		link-&gt;dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &amp;&amp;</div><div class='ctx'> 		(!memcmp(link-&gt;dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,</div><div class='ctx'> 			sizeof(DP_SINK_DEVICE_STR_ID_1)) ||</div><div class='ctx'> 		!memcmp(link-&gt;dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,</div><div class='del'>-			sizeof(DP_SINK_DEVICE_STR_ID_2)))*/)</div><div class='add'>+			sizeof(DP_SINK_DEVICE_STR_ID_2))))</div><div class='ctx'> 		copy_settings_data-&gt;flags.bitfields.force_wakeup_by_tps3 = 1;</div><div class='ctx'> 	else</div><div class='ctx'> 		copy_settings_data-&gt;flags.bitfields.force_wakeup_by_tps3 = 0;</div><div class='ctx'> </div><div class='add'>+	copy_settings_data-&gt;flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link-&gt;replay_settings.config.alpm_mode;</div><div class='add'>+	if (link-&gt;replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {</div><div class='add'>+		copy_settings_data-&gt;auxless_alpm_data.lfps_setup_ns = dc-&gt;dc-&gt;debug.auxless_alpm_lfps_setup_ns;</div><div class='add'>+		copy_settings_data-&gt;auxless_alpm_data.lfps_period_ns = dc-&gt;dc-&gt;debug.auxless_alpm_lfps_period_ns;</div><div class='add'>+		copy_settings_data-&gt;auxless_alpm_data.lfps_silence_ns = dc-&gt;dc-&gt;debug.auxless_alpm_lfps_silence_ns;</div><div class='add'>+		copy_settings_data-&gt;auxless_alpm_data.lfps_t1_t2_override_us =</div><div class='add'>+			dc-&gt;dc-&gt;debug.auxless_alpm_lfps_t1t2_us;</div><div class='add'>+		copy_settings_data-&gt;auxless_alpm_data.lfps_t1_t2_offset_us =</div><div class='add'>+			dc-&gt;dc-&gt;debug.auxless_alpm_lfps_t1t2_offset_us;</div><div class='add'>+		copy_settings_data-&gt;auxless_alpm_data.lttpr_count = link-&gt;dc-&gt;link_srv-&gt;dp_get_lttpr_count(link);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -219,63 +212,98 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,</div><div class='ctx'>  * Set coasting vtotal.</div><div class='ctx'>  */</div><div class='ctx'> static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,</div><div class='del'>-		uint16_t coasting_vtotal,</div><div class='del'>-		uint8_t panel_inst)</div><div class='add'>+		uint32_t coasting_vtotal,</div><div class='add'>+		uint8_t panel_inst,</div><div class='add'>+		uint16_t frame_skip_number)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct dc_context *dc = dmub-&gt;ctx;</div><div class='add'>+	struct dmub_rb_cmd_replay_set_coasting_vtotal *pCmd = NULL;</div><div class='add'>+</div><div class='add'>+	pCmd = &amp;(cmd.replay_set_coasting_vtotal);</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	cmd.replay_set_coasting_vtotal.header.type = DMUB_CMD__REPLAY;</div><div class='del'>-	cmd.replay_set_coasting_vtotal.header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;</div><div class='del'>-	cmd.replay_set_coasting_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);</div><div class='del'>-	cmd.replay_set_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;</div><div class='add'>+	pCmd-&gt;header.type = DMUB_CMD__REPLAY;</div><div class='add'>+	pCmd-&gt;header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;</div><div class='add'>+	pCmd-&gt;header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);</div><div class='add'>+	pCmd-&gt;replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal &amp; 0xFFFF);</div><div class='add'>+	pCmd-&gt;replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal &amp; 0xFFFF0000) &gt;&gt; 16;</div><div class='add'>+	pCmd-&gt;replay_set_coasting_vtotal_data.frame_skip_number = frame_skip_number;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Get Replay residency from firmware.</div><div class='ctx'>  */</div><div class='ctx'> static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,</div><div class='del'>-	uint32_t *residency, const bool is_start, const bool is_alpm)</div><div class='add'>+	uint32_t *residency, const bool is_start, enum pr_residency_mode mode)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *srv = dmub-&gt;ctx-&gt;dmub_srv-&gt;dmub;</div><div class='ctx'> 	uint16_t param = (uint16_t)(panel_inst &lt;&lt; 8);</div><div class='add'>+	uint32_t i = 0;</div><div class='ctx'> </div><div class='del'>-	if (is_alpm)</div><div class='del'>-		param |= REPLAY_RESIDENCY_MODE_ALPM;</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case PR_RESIDENCY_MODE_PHY:</div><div class='add'>+		param |= REPLAY_RESIDENCY_FIELD_MODE_PHY;</div><div class='add'>+		break;</div><div class='add'>+	case PR_RESIDENCY_MODE_ALPM:</div><div class='add'>+		param |= REPLAY_RESIDENCY_FIELD_MODE_ALPM;</div><div class='add'>+		break;</div><div class='add'>+	case PR_RESIDENCY_MODE_IPS2:</div><div class='add'>+		param |= REPLAY_RESIDENCY_REVISION_1;</div><div class='add'>+		param |= REPLAY_RESIDENCY_FIELD_MODE2_IPS;</div><div class='add'>+		break;</div><div class='add'>+	case PR_RESIDENCY_MODE_FRAME_CNT:</div><div class='add'>+		param |= REPLAY_RESIDENCY_REVISION_1;</div><div class='add'>+		param |= REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT;</div><div class='add'>+		break;</div><div class='add'>+	case PR_RESIDENCY_MODE_ENABLEMENT_PERIOD:</div><div class='add'>+		param |= REPLAY_RESIDENCY_REVISION_1;</div><div class='add'>+		param |= REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (is_start)</div><div class='ctx'> 		param |= REPLAY_RESIDENCY_ENABLE;</div><div class='ctx'> </div><div class='del'>-	// Send gpint command and wait for ack</div><div class='del'>-	dmub_srv_send_gpint_command(srv, DMUB_GPINT__REPLAY_RESIDENCY, param, 30);</div><div class='add'>+	for (i = 0; i &lt; GPINT_RETRY_NUM; i++) {</div><div class='add'>+		// Send gpint command and wait for ack</div><div class='add'>+		if (dc_wake_and_execute_gpint(dmub-&gt;ctx, DMUB_GPINT__REPLAY_RESIDENCY, param,</div><div class='add'>+			residency, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+			return;</div><div class='ctx'> </div><div class='del'>-	if (!is_start)</div><div class='del'>-		dmub_srv_get_gpint_response(srv, residency);</div><div class='del'>-	else</div><div class='del'>-		*residency = 0;</div><div class='add'>+		udelay(100);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// it means gpint retry many times</div><div class='add'>+	*residency = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Set REPLAY power optimization flags and coasting vtotal.</div><div class='ctx'>  */</div><div class='ctx'> static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub,</div><div class='del'>-		unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal)</div><div class='add'>+		unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal, uint16_t frame_skip_number)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct dc_context *dc = dmub-&gt;ctx;</div><div class='add'>+	struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal *pCmd = NULL;</div><div class='add'>+</div><div class='add'>+	pCmd = &amp;(cmd.replay_set_power_opt_and_coasting_vtotal);</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	cmd.replay_set_power_opt_and_coasting_vtotal.header.type = DMUB_CMD__REPLAY;</div><div class='del'>-	cmd.replay_set_power_opt_and_coasting_vtotal.header.sub_type =</div><div class='del'>-		DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;</div><div class='del'>-	cmd.replay_set_power_opt_and_coasting_vtotal.header.payload_bytes =</div><div class='del'>-		sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal);</div><div class='del'>-	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.power_opt = power_opt;</div><div class='del'>-	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.panel_inst = panel_inst;</div><div class='del'>-	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;</div><div class='add'>+	pCmd-&gt;header.type = DMUB_CMD__REPLAY;</div><div class='add'>+	pCmd-&gt;header.sub_type = DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;</div><div class='add'>+	pCmd-&gt;header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='add'>+	pCmd-&gt;replay_set_power_opt_data.power_opt = power_opt;</div><div class='add'>+	pCmd-&gt;replay_set_power_opt_data.panel_inst = panel_inst;</div><div class='add'>+	pCmd-&gt;replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal &amp; 0xFFFF);</div><div class='add'>+	pCmd-&gt;replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal &amp; 0xFFFF0000) &gt;&gt; 16;</div><div class='add'>+	pCmd-&gt;replay_set_coasting_vtotal_data.frame_skip_number = frame_skip_number;</div><div class='ctx'> </div><div class='ctx'> 	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='hunk'>@@ -310,7 +338,8 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub,</div><div class='ctx'> 		cmd.replay_set_timing_sync.header.sub_type =</div><div class='ctx'> 			DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED;</div><div class='ctx'> 		cmd.replay_set_timing_sync.header.payload_bytes =</div><div class='del'>-			sizeof(struct dmub_rb_cmd_replay_set_timing_sync);</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_timing_sync) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='ctx'> 		//Cmd Body</div><div class='ctx'> 		cmd.replay_set_timing_sync.replay_set_timing_sync_data.panel_inst =</div><div class='ctx'> 						cmd_element-&gt;sync_data.panel_inst;</div><div class='hunk'>@@ -322,7 +351,8 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub,</div><div class='ctx'> 		cmd.replay_set_frameupdate_timer.header.sub_type =</div><div class='ctx'> 			DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER;</div><div class='ctx'> 		cmd.replay_set_frameupdate_timer.header.payload_bytes =</div><div class='del'>-			sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer);</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='ctx'> 		//Cmd Body</div><div class='ctx'> 		cmd.replay_set_frameupdate_timer.data.panel_inst =</div><div class='ctx'> 						cmd_element-&gt;panel_inst;</div><div class='hunk'>@@ -331,6 +361,62 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub,</div><div class='ctx'> 		cmd.replay_set_frameupdate_timer.data.frameupdate_count =</div><div class='ctx'> 						cmd_element-&gt;timer_data.frameupdate_count;</div><div class='ctx'> 		break;</div><div class='add'>+	case Replay_Set_Pseudo_VTotal:</div><div class='add'>+		//Header</div><div class='add'>+		cmd.replay_set_pseudo_vtotal.header.sub_type =</div><div class='add'>+			DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL;</div><div class='add'>+		cmd.replay_set_pseudo_vtotal.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_pseudo_vtotal) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='add'>+		//Cmd Body</div><div class='add'>+		cmd.replay_set_pseudo_vtotal.data.panel_inst =</div><div class='add'>+			cmd_element-&gt;pseudo_vtotal_data.panel_inst;</div><div class='add'>+		cmd.replay_set_pseudo_vtotal.data.vtotal =</div><div class='add'>+			cmd_element-&gt;pseudo_vtotal_data.vtotal;</div><div class='add'>+		break;</div><div class='add'>+	case Replay_Disabled_Adaptive_Sync_SDP:</div><div class='add'>+		//Header</div><div class='add'>+		cmd.replay_disabled_adaptive_sync_sdp.header.sub_type =</div><div class='add'>+			DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP;</div><div class='add'>+		cmd.replay_disabled_adaptive_sync_sdp.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='add'>+		//Cmd Body</div><div class='add'>+		cmd.replay_disabled_adaptive_sync_sdp.data.panel_inst =</div><div class='add'>+			cmd_element-&gt;disabled_adaptive_sync_sdp_data.panel_inst;</div><div class='add'>+		cmd.replay_disabled_adaptive_sync_sdp.data.force_disabled =</div><div class='add'>+			cmd_element-&gt;disabled_adaptive_sync_sdp_data.force_disabled;</div><div class='add'>+		break;</div><div class='add'>+	case Replay_Set_Version:</div><div class='add'>+		//Header</div><div class='add'>+		cmd.replay_set_version.header.sub_type =</div><div class='add'>+			DMUB_CMD__REPLAY_SET_VERSION;</div><div class='add'>+		cmd.replay_set_version.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_version) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='add'>+		//Cmd Body</div><div class='add'>+		cmd.replay_set_version.replay_set_version_data.panel_inst =</div><div class='add'>+			cmd_element-&gt;version_data.panel_inst;</div><div class='add'>+		cmd.replay_set_version.replay_set_version_data.version =</div><div class='add'>+			cmd_element-&gt;version_data.version;</div><div class='add'>+		break;</div><div class='add'>+	case Replay_Set_General_Cmd:</div><div class='add'>+		//Header</div><div class='add'>+		cmd.replay_set_general_cmd.header.sub_type =</div><div class='add'>+			DMUB_CMD__REPLAY_SET_GENERAL_CMD;</div><div class='add'>+		cmd.replay_set_general_cmd.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_general_cmd) -</div><div class='add'>+			sizeof(struct dmub_cmd_header);</div><div class='add'>+		//Cmd Body</div><div class='add'>+		cmd.replay_set_general_cmd.data.panel_inst =</div><div class='add'>+			cmd_element-&gt;set_general_cmd_data.panel_inst;</div><div class='add'>+		cmd.replay_set_general_cmd.data.subtype =</div><div class='add'>+			cmd_element-&gt;set_general_cmd_data.subtype;</div><div class='add'>+		cmd.replay_set_general_cmd.data.param1 =</div><div class='add'>+			cmd_element-&gt;set_general_cmd_data.param1;</div><div class='add'>+		cmd.replay_set_general_cmd.data.param2 =</div><div class='add'>+			cmd_element-&gt;set_general_cmd_data.param2;</div><div class='add'>+		break;</div><div class='ctx'> 	case Replay_Msg_Not_Support:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h<br/>index 3613aff994d7..07c79739a980 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h</a></div><div class='hunk'>@@ -1,27 +1,6 @@</div><div class='del'>-/*</div><div class='del'>- * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- * Authors: AMD</div><div class='del'>- *</div><div class='del'>- */</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='ctx'> </div><div class='ctx'> #ifndef _DMUB_REPLAY_H_</div><div class='ctx'> #define _DMUB_REPLAY_H_</div><div class='hunk'>@@ -47,12 +26,13 @@ struct dmub_replay_funcs {</div><div class='ctx'> 		uint8_t panel_inst);</div><div class='ctx'> 	void (*replay_send_cmd)(struct dmub_replay *dmub,</div><div class='ctx'> 		enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element);</div><div class='del'>-	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint16_t coasting_vtotal,</div><div class='del'>-		uint8_t panel_inst);</div><div class='add'>+	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,</div><div class='add'>+		uint8_t panel_inst, uint16_t frame_skip_number);</div><div class='ctx'> 	void (*replay_residency)(struct dmub_replay *dmub,</div><div class='del'>-		uint8_t panel_inst, uint32_t *residency, const bool is_start, const bool is_alpm);</div><div class='add'>+		uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);</div><div class='ctx'> 	void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,</div><div class='del'>-		unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal);</div><div class='add'>+		unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal,</div><div class='add'>+		uint16_t frame_skip_number);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dmub_replay *dmub_replay_create(struct dc_context *ctx);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile<br/>index f0777d61c2cb..c307f040e48f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/Makefile</a></div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'> # Makefile for the 'controller' sub-component of DAL.</div><div class='ctx'> # It provides the control and status of HW CRTC block.</div><div class='ctx'> </div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dce110/dce110_resource.o = $(call cc-disable-warning, override-init)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dce110/dce110_resource.o = -Wno-override-init</div><div class='ctx'> </div><div class='ctx'> DCE110 = dce110_timing_generator.o \</div><div class='ctx'> dce110_compressor.o dce110_opp_regamma_v.o \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c<br/>index d241ee13b293..59a0961b49da 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c</a></div><div class='hunk'>@@ -409,19 +409,6 @@ void dce110_compressor_destroy(struct compressor **compressor)</div><div class='ctx'> 	*compressor = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)</div><div class='del'>-{</div><div class='del'>-	*max_x = FBC_MAX_X;</div><div class='del'>-	*max_y = FBC_MAX_Y;</div><div class='del'>-</div><div class='del'>-	/* if (m_smallLocalFrameBufferMemory == 1)</div><div class='del'>-	 * {</div><div class='del'>-	 *	*max_x = FBC_MAX_X_SG;</div><div class='del'>-	 *	*max_y = FBC_MAX_Y_SG;</div><div class='del'>-	 * }</div><div class='del'>-	 */</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct compressor_funcs dce110_compressor_funcs = {</div><div class='ctx'> 	.power_up_fbc = dce110_compressor_power_up_fbc,</div><div class='ctx'> 	.enable_fbc = dce110_compressor_enable_fbc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h<br/>index 26c7335a1cbf..223c57941e92 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h</a></div><div class='hunk'>@@ -75,7 +75,5 @@ void dce110_compressor_program_lpt_control(struct compressor *cp,</div><div class='ctx'> </div><div class='ctx'> bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp);</div><div class='ctx'> </div><div class='del'>-void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y);</div><div class='del'>-</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c<br/>index db7557a1c613..2c43c2422638 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c</a></div><div class='hunk'>@@ -76,7 +76,6 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MAS</div><div class='ctx'> 		mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,</div><div class='ctx'> 		value);</div><div class='ctx'> </div><div class='del'>-	temp = 0;</div><div class='ctx'> 	value = 0;</div><div class='ctx'> 	temp = address.low_part &gt;&gt;</div><div class='ctx'> 	UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT;</div><div class='hunk'>@@ -112,7 +111,6 @@ UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MAS</div><div class='ctx'> 		mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,</div><div class='ctx'> 		value);</div><div class='ctx'> </div><div class='del'>-	temp = 0;</div><div class='ctx'> 	value = 0;</div><div class='ctx'> 	temp = address.low_part &gt;&gt;</div><div class='ctx'> 	UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;</div><div class='hunk'>@@ -164,7 +162,7 @@ static void enable(struct dce_mem_input *mem_input110)</div><div class='ctx'> </div><div class='ctx'> static void program_tiling(</div><div class='ctx'> 	struct dce_mem_input *mem_input110,</div><div class='del'>-	const union dc_tiling_info *info,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='ctx'> 	const enum surface_pixel_format pixel_format)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t value = 0;</div><div class='hunk'>@@ -525,7 +523,7 @@ static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {</div><div class='ctx'> </div><div class='ctx'> /* Helper to get table entry from surface info */</div><div class='ctx'> static const unsigned int *get_dvmm_hw_setting(</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='ctx'> 		bool chroma)</div><div class='ctx'> {</div><div class='hunk'>@@ -565,7 +563,7 @@ static const unsigned int *get_dvmm_hw_setting(</div><div class='ctx'> static void dce_mem_input_v_program_pte_vm(</div><div class='ctx'> 		struct mem_input *mem_input,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		enum dc_rotation_angle rotation)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);</div><div class='hunk'>@@ -638,7 +636,7 @@ static void dce_mem_input_v_program_pte_vm(</div><div class='ctx'> static void dce_mem_input_v_program_surface_config(</div><div class='ctx'> 	struct mem_input *mem_input,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c<br/>index 6424e7f279dc..61b0807693fb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c</a></div><div class='hunk'>@@ -1955,6 +1955,7 @@ void dce110_tg_program_timing(struct timing_generator *tg,</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios)</div><div class='ctx'> {</div><div class='hunk'>@@ -2015,6 +2016,23 @@ bool dce110_tg_validate_timing(struct timing_generator *tg,</div><div class='ctx'> 	return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* "Container" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:</div><div class='add'>+ *</div><div class='add'>+ * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as</div><div class='add'>+ *   container rate.</div><div class='add'>+ *</div><div class='add'>+ * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be</div><div class='add'>+ *   halved to maintain the correct pixel rate.</div><div class='add'>+ *</div><div class='add'>+ * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied</div><div class='add'>+ *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	return timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR420;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dce110_tg_wait_for_state(struct timing_generator *tg,</div><div class='ctx'> 	enum crtc_state state)</div><div class='ctx'> {</div><div class='hunk'>@@ -2109,70 +2127,131 @@ bool dce110_configure_crc(struct timing_generator *tg,</div><div class='ctx'> </div><div class='ctx'> 	cntl_addr = CRTC_REG(mmCRTC_CRC_CNTL);</div><div class='ctx'> </div><div class='del'>-	/* First, disable CRC before we configure it. */</div><div class='del'>-	dm_write_reg(tg-&gt;ctx, cntl_addr, 0);</div><div class='add'>+	if (!params-&gt;enable || params-&gt;reset)</div><div class='add'>+		/* First, disable CRC before we configure it. */</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, cntl_addr, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (!params-&gt;enable)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/* Program frame boundaries */</div><div class='del'>-	/* Window A x axis start and end. */</div><div class='del'>-	value = 0;</div><div class='del'>-	addr = CRTC_REG(mmCRTC_CRC0_WINDOWA_X_CONTROL);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowa_x_start,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_X_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_X_START);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowa_x_end,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_X_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_X_END);</div><div class='del'>-	dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='del'>-</div><div class='del'>-	/* Window A y axis start and end. */</div><div class='del'>-	value = 0;</div><div class='del'>-	addr = CRTC_REG(mmCRTC_CRC0_WINDOWA_Y_CONTROL);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowa_y_start,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_Y_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_Y_START);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowa_y_end,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_Y_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWA_Y_END);</div><div class='del'>-	dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='del'>-</div><div class='del'>-	/* Window B x axis start and end. */</div><div class='del'>-	value = 0;</div><div class='del'>-	addr = CRTC_REG(mmCRTC_CRC0_WINDOWB_X_CONTROL);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowb_x_start,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_X_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_X_START);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowb_x_end,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_X_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_X_END);</div><div class='del'>-	dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='del'>-</div><div class='del'>-	/* Window B y axis start and end. */</div><div class='del'>-	value = 0;</div><div class='del'>-	addr = CRTC_REG(mmCRTC_CRC0_WINDOWB_Y_CONTROL);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowb_y_start,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_Y_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_Y_START);</div><div class='del'>-	set_reg_field_value(value, params-&gt;windowb_y_end,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_Y_CONTROL,</div><div class='del'>-			    CRTC_CRC0_WINDOWB_Y_END);</div><div class='del'>-	dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='del'>-</div><div class='del'>-	/* Set crc mode and selection, and enable. Only using CRC0*/</div><div class='del'>-	value = 0;</div><div class='del'>-	set_reg_field_value(value, params-&gt;continuous_mode ? 1 : 0,</div><div class='del'>-			    CRTC_CRC_CNTL, CRTC_CRC_CONT_EN);</div><div class='del'>-	set_reg_field_value(value, params-&gt;selection,</div><div class='del'>-			    CRTC_CRC_CNTL, CRTC_CRC0_SELECT);</div><div class='del'>-	set_reg_field_value(value, 1, CRTC_CRC_CNTL, CRTC_CRC_EN);</div><div class='del'>-	dm_write_reg(tg-&gt;ctx, cntl_addr, value);</div><div class='add'>+	switch (params-&gt;crc_eng_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC0_WINDOWA_X_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_x_start,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_X_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_X_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_x_end,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_X_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_X_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC0_WINDOWA_Y_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_y_start,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_Y_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_y_end,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWA_Y_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC0_WINDOWB_X_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_x_start,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_X_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_X_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_x_end,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_X_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_X_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC0_WINDOWB_Y_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_y_start,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_Y_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_y_end,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC0_WINDOWB_Y_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Set crc mode and selection, and enable.*/</div><div class='add'>+		value = 0;</div><div class='add'>+		set_reg_field_value(value, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+				    CRTC_CRC_CNTL, CRTC_CRC_CONT_EN);</div><div class='add'>+		set_reg_field_value(value, params-&gt;selection,</div><div class='add'>+				    CRTC_CRC_CNTL, CRTC_CRC0_SELECT);</div><div class='add'>+		set_reg_field_value(value, 1, CRTC_CRC_CNTL, CRTC_CRC_EN);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, cntl_addr, value);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC1_WINDOWA_X_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_x_start,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_X_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_X_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_x_end,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_X_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_X_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC1_WINDOWA_Y_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_y_start,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_Y_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowa_y_end,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWA_Y_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC1_WINDOWB_X_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_x_start,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_X_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_X_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_x_end,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_X_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_X_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		value = 0;</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC1_WINDOWB_Y_CONTROL);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_y_start,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_Y_START);</div><div class='add'>+		set_reg_field_value(value, params-&gt;windowb_y_end,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_Y_CONTROL,</div><div class='add'>+				    CRTC_CRC1_WINDOWB_Y_END);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='add'>+</div><div class='add'>+		/* Set crc mode and selection, and enable.*/</div><div class='add'>+		value = 0;</div><div class='add'>+		set_reg_field_value(value, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+				    CRTC_CRC_CNTL, CRTC_CRC_CONT_EN);</div><div class='add'>+		set_reg_field_value(value, params-&gt;selection,</div><div class='add'>+				    CRTC_CRC_CNTL, CRTC_CRC1_SELECT);</div><div class='add'>+		set_reg_field_value(value, 1, CRTC_CRC_CNTL, CRTC_CRC_EN);</div><div class='add'>+		dm_write_reg(tg-&gt;ctx, cntl_addr, value);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dce110_get_crc(struct timing_generator *tg,</div><div class='add'>+bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,</div><div class='ctx'> 		    uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t addr = 0;</div><div class='hunk'>@@ -2188,14 +2267,30 @@ bool dce110_get_crc(struct timing_generator *tg,</div><div class='ctx'> 	if (!field)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	addr = CRTC_REG(mmCRTC_CRC0_DATA_RG);</div><div class='del'>-	value = dm_read_reg(tg-&gt;ctx, addr);</div><div class='del'>-	*r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR);</div><div class='del'>-	*g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y);</div><div class='add'>+	switch (idx) {</div><div class='add'>+	case 0:</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC0_DATA_RG);</div><div class='add'>+		value = dm_read_reg(tg-&gt;ctx, addr);</div><div class='add'>+		*r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR);</div><div class='add'>+		*g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y);</div><div class='ctx'> </div><div class='del'>-	addr = CRTC_REG(mmCRTC_CRC0_DATA_B);</div><div class='del'>-	value = dm_read_reg(tg-&gt;ctx, addr);</div><div class='del'>-	*b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB);</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC0_DATA_B);</div><div class='add'>+		value = dm_read_reg(tg-&gt;ctx, addr);</div><div class='add'>+		*b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC1_DATA_RG);</div><div class='add'>+		value = dm_read_reg(tg-&gt;ctx, addr);</div><div class='add'>+		*r_cr = get_reg_field_value(value, CRTC_CRC1_DATA_RG, CRC1_R_CR);</div><div class='add'>+		*g_y = get_reg_field_value(value, CRTC_CRC1_DATA_RG, CRC1_G_Y);</div><div class='add'>+</div><div class='add'>+		addr = CRTC_REG(mmCRTC_CRC1_DATA_B);</div><div class='add'>+		value = dm_read_reg(tg-&gt;ctx, addr);</div><div class='add'>+		*b_cb = get_reg_field_value(value, CRTC_CRC1_DATA_B, CRC1_B_CB);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -2239,6 +2334,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = {</div><div class='ctx'> 		.is_tg_enabled = dce110_is_tg_enabled,</div><div class='ctx'> 		.configure_crc = dce110_configure_crc,</div><div class='ctx'> 		.get_crc = dce110_get_crc,</div><div class='add'>+		.is_two_pixels_per_container = dce110_is_two_pixels_per_container,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dce110_timing_generator_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h<br/>index d8a5ed7b485d..e4f5cad64f32 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h</a></div><div class='hunk'>@@ -261,6 +261,7 @@ void dce110_tg_program_timing(struct timing_generator *tg,</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios);</div><div class='ctx'> </div><div class='hunk'>@@ -285,7 +286,9 @@ bool dce110_arm_vert_intr(</div><div class='ctx'> bool dce110_configure_crc(struct timing_generator *tg,</div><div class='ctx'> 			  const struct crc_params *params);</div><div class='ctx'> </div><div class='del'>-bool dce110_get_crc(struct timing_generator *tg,</div><div class='add'>+bool dce110_get_crc(struct timing_generator *tg, uint8_t idx,</div><div class='ctx'> 		    uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);</div><div class='ctx'> </div><div class='add'>+bool dce110_is_two_pixels_per_container(const struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_TIMING_GENERATOR_DCE110_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c<br/>index c509384fff54..9837dec837ff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c</a></div><div class='hunk'>@@ -438,6 +438,7 @@ static void dce110_timing_generator_v_program_timing(struct timing_generator *tg</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios)</div><div class='ctx'> {</div><div class='hunk'>@@ -682,7 +683,8 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {</div><div class='ctx'> 		.tear_down_global_swap_lock =</div><div class='ctx'> 				dce110_timing_generator_v_tear_down_global_swap_lock,</div><div class='ctx'> 		.enable_advanced_request =</div><div class='del'>-				dce110_timing_generator_v_enable_advanced_request</div><div class='add'>+				dce110_timing_generator_v_enable_advanced_request,</div><div class='add'>+		.is_two_pixels_per_container = dce110_is_two_pixels_per_container,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dce110_timing_generator_v_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile<br/>index 7e92effec894..683866797709 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce112/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce112/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce112/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce112/Makefile</a></div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'> # Makefile for the 'controller' sub-component of DAL.</div><div class='ctx'> # It provides the control and status of HW CRTC block.</div><div class='ctx'> </div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dce112/dce112_resource.o = $(call cc-disable-warning, override-init)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dce112/dce112_resource.o = -Wno-override-init</div><div class='ctx'> </div><div class='ctx'> DCE112 = dce112_compressor.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile<br/>index 1e3ef68a452a..8f508e662748 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce120/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce120/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce120/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce120/Makefile</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'> # It provides the control and status of HW CRTC block.</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dce120/dce120_resource.o = $(call cc-disable-warning, override-init)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dce120/dce120_resource.o = -Wno-override-init</div><div class='ctx'> </div><div class='ctx'> DCE120 = dce120_timing_generator.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c<br/>index 4af0c70098c4..31c4f44ceaac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c</a></div><div class='hunk'>@@ -697,6 +697,7 @@ static void dce120_tg_program_timing(struct timing_generator *tg,</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios)</div><div class='ctx'> {</div><div class='hunk'>@@ -1099,45 +1100,79 @@ static bool dce120_configure_crc(struct timing_generator *tg,</div><div class='ctx'> 	if (!dce120_is_tg_enabled(tg))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	/* First, disable CRC before we configure it. */</div><div class='del'>-	dm_write_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC_CNTL,</div><div class='del'>-			   tg110-&gt;offsets.crtc, 0);</div><div class='add'>+	if (!params-&gt;enable || params-&gt;reset)</div><div class='add'>+		/* First, disable CRC before we configure it. */</div><div class='add'>+		dm_write_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC_CNTL,</div><div class='add'>+				   tg110-&gt;offsets.crtc, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (!params-&gt;enable)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/* Program frame boundaries */</div><div class='del'>-	/* Window A x axis start and end. */</div><div class='del'>-	CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL,</div><div class='del'>-			  CRTC_CRC0_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='del'>-			  CRTC_CRC0_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='del'>-</div><div class='del'>-	/* Window A y axis start and end. */</div><div class='del'>-	CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL,</div><div class='del'>-			  CRTC_CRC0_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='del'>-			  CRTC_CRC0_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='del'>-</div><div class='del'>-	/* Window B x axis start and end. */</div><div class='del'>-	CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL,</div><div class='del'>-			  CRTC_CRC0_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='del'>-			  CRTC_CRC0_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='del'>-</div><div class='del'>-	/* Window B y axis start and end. */</div><div class='del'>-	CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL,</div><div class='del'>-			  CRTC_CRC0_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='del'>-			  CRTC_CRC0_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='del'>-</div><div class='del'>-	/* Set crc mode and selection, and enable. Only using CRC0*/</div><div class='del'>-	CRTC_REG_UPDATE_3(CRTC0_CRTC_CRC_CNTL,</div><div class='del'>-			  CRTC_CRC_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='del'>-			  CRTC_CRC0_SELECT, params-&gt;selection,</div><div class='del'>-			  CRTC_CRC_EN, 1);</div><div class='add'>+	switch (params-&gt;crc_eng_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWA_X_CONTROL,</div><div class='add'>+				  CRTC_CRC0_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='add'>+				  CRTC_CRC0_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL,</div><div class='add'>+				  CRTC_CRC0_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='add'>+				  CRTC_CRC0_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWB_X_CONTROL,</div><div class='add'>+				  CRTC_CRC0_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='add'>+				  CRTC_CRC0_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL,</div><div class='add'>+				  CRTC_CRC0_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='add'>+				  CRTC_CRC0_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='add'>+</div><div class='add'>+		/* Set crc mode and selection, and enable.*/</div><div class='add'>+		CRTC_REG_UPDATE_3(CRTC0_CRTC_CRC_CNTL,</div><div class='add'>+				  CRTC_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+				  CRTC_CRC0_SELECT, params-&gt;selection,</div><div class='add'>+				  CRTC_CRC_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC1_WINDOWA_X_CONTROL,</div><div class='add'>+				  CRTC_CRC1_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='add'>+				  CRTC_CRC1_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL,</div><div class='add'>+				  CRTC_CRC1_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='add'>+				  CRTC_CRC1_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC1_WINDOWB_X_CONTROL,</div><div class='add'>+				  CRTC_CRC1_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='add'>+				  CRTC_CRC1_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		CRTC_REG_UPDATE_2(CRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL,</div><div class='add'>+				  CRTC_CRC1_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='add'>+				  CRTC_CRC1_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='add'>+</div><div class='add'>+		/* Set crc mode and selection, and enable */</div><div class='add'>+		CRTC_REG_UPDATE_3(CRTC0_CRTC_CRC_CNTL,</div><div class='add'>+				  CRTC_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+				  CRTC_CRC1_SELECT, params-&gt;selection,</div><div class='add'>+				  CRTC_CRC_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce120_get_crc(struct timing_generator *tg, uint32_t *r_cr,</div><div class='del'>-			   uint32_t *g_y, uint32_t *b_cb)</div><div class='add'>+static bool dce120_get_crc(struct timing_generator *tg, uint8_t idx,</div><div class='add'>+			uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);</div><div class='ctx'> 	uint32_t value, field;</div><div class='hunk'>@@ -1150,14 +1185,30 @@ static bool dce120_get_crc(struct timing_generator *tg, uint32_t *r_cr,</div><div class='ctx'> 	if (!field)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	value = dm_read_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC0_DATA_RG,</div><div class='del'>-				  tg110-&gt;offsets.crtc);</div><div class='del'>-	*r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_R_CR);</div><div class='del'>-	*g_y = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_G_Y);</div><div class='add'>+	switch (idx) {</div><div class='add'>+	case 0:</div><div class='add'>+		value = dm_read_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC0_DATA_RG,</div><div class='add'>+					  tg110-&gt;offsets.crtc);</div><div class='add'>+		*r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_R_CR);</div><div class='add'>+		*g_y = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_G_Y);</div><div class='ctx'> </div><div class='del'>-	value = dm_read_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC0_DATA_B,</div><div class='del'>-				  tg110-&gt;offsets.crtc);</div><div class='del'>-	*b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_B, CRC0_B_CB);</div><div class='add'>+		value = dm_read_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC0_DATA_B,</div><div class='add'>+					  tg110-&gt;offsets.crtc);</div><div class='add'>+		*b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_B, CRC0_B_CB);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		value = dm_read_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC1_DATA_RG,</div><div class='add'>+					  tg110-&gt;offsets.crtc);</div><div class='add'>+		*r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_RG, CRC1_R_CR);</div><div class='add'>+		*g_y = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_RG, CRC1_G_Y);</div><div class='add'>+</div><div class='add'>+		value = dm_read_reg_soc15(tg-&gt;ctx, mmCRTC0_CRTC_CRC1_DATA_B,</div><div class='add'>+					  tg110-&gt;offsets.crtc);</div><div class='add'>+		*b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC1_DATA_B, CRC1_B_CB);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -1197,6 +1248,7 @@ static const struct timing_generator_funcs dce120_tg_funcs = {</div><div class='ctx'> 		.is_tg_enabled = dce120_is_tg_enabled,</div><div class='ctx'> 		.configure_crc = dce120_configure_crc,</div><div class='ctx'> 		.get_crc = dce120_get_crc,</div><div class='add'>+		.is_two_pixels_per_container = dce110_is_two_pixels_per_container,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile b/drivers/gpu/drm/amd/display/dc/dce60/Makefile<br/>index fee331accc0e..824f73eb3326 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce60/Makefile</a></div><div class='hunk'>@@ -23,10 +23,9 @@</div><div class='ctx'> # Makefile for the 'controller' sub-component of DAL.</div><div class='ctx'> # It provides the control and status of HW CRTC block.</div><div class='ctx'> </div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dce60/dce60_resource.o = $(call cc-disable-warning, override-init)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dce60/dce60_resource.o = -Wno-override-init</div><div class='ctx'> </div><div class='del'>-DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \</div><div class='del'>-	dce60_resource.o</div><div class='add'>+DCE60 = dce60_timing_generator.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c<br/>index c1a85ee374d9..e691a1cf3356 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c</a></div><div class='hunk'>@@ -111,13 +111,14 @@ static void program_timing(struct timing_generator *tg,</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios)</div><div class='ctx'> {</div><div class='ctx'> 	if (!use_vbios)</div><div class='ctx'> 		program_pix_dur(tg, timing-&gt;pix_clk_100hz);</div><div class='ctx'> </div><div class='del'>-	dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);</div><div class='add'>+	dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dce60_timing_generator_enable_advanced_request(</div><div class='hunk'>@@ -238,6 +239,7 @@ static const struct timing_generator_funcs dce60_tg_funcs = {</div><div class='ctx'> 				dce60_timing_generator_enable_advanced_request,</div><div class='ctx'> 		.configure_crc = dce60_configure_crc,</div><div class='ctx'> 		.get_crc = dce110_get_crc,</div><div class='add'>+		.is_two_pixels_per_container = dce110_is_two_pixels_per_container,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dce60_timing_generator_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile<br/>index 7eefffbdc925..fba189d26652 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce80/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce80/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce80/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce80/Makefile</a></div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'> # Makefile for the 'controller' sub-component of DAL.</div><div class='ctx'> # It provides the control and status of HW CRTC block.</div><div class='ctx'> </div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dce80/dce80_resource.o = $(call cc-disable-warning, override-init)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dce80/dce80_resource.o = -Wno-override-init</div><div class='ctx'> </div><div class='ctx'> DCE80 = dce80_timing_generator.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c<br/>index b8fd43dc010b..88e7a1fc9a30 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c</a></div><div class='hunk'>@@ -105,19 +105,20 @@ static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)</div><div class='ctx'> 	dm_write_reg(tg-&gt;ctx, addr, value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void program_timing(struct timing_generator *tg,</div><div class='add'>+static void dce80_timing_generator_program_timing(struct timing_generator *tg,</div><div class='ctx'> 	const struct dc_crtc_timing *timing,</div><div class='ctx'> 	int vready_offset,</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios)</div><div class='ctx'> {</div><div class='ctx'> 	if (!use_vbios)</div><div class='ctx'> 		program_pix_dur(tg, timing-&gt;pix_clk_100hz);</div><div class='ctx'> </div><div class='del'>-	dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);</div><div class='add'>+	dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, 0, use_vbios);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dce80_timing_generator_enable_advanced_request(</div><div class='hunk'>@@ -184,7 +185,7 @@ static void dce80_timing_generator_enable_advanced_request(</div><div class='ctx'> </div><div class='ctx'> static const struct timing_generator_funcs dce80_tg_funcs = {</div><div class='ctx'> 		.validate_timing = dce110_tg_validate_timing,</div><div class='del'>-		.program_timing = program_timing,</div><div class='add'>+		.program_timing = dce80_timing_generator_program_timing,</div><div class='ctx'> 		.enable_crtc = dce110_timing_generator_enable_crtc,</div><div class='ctx'> 		.disable_crtc = dce110_timing_generator_disable_crtc,</div><div class='ctx'> 		.is_counter_moving = dce110_timing_generator_is_counter_moving,</div><div class='hunk'>@@ -220,6 +221,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = {</div><div class='ctx'> 				dce80_timing_generator_enable_advanced_request,</div><div class='ctx'> 		.configure_crc = dce110_configure_crc,</div><div class='ctx'> 		.get_crc = dce110_get_crc,</div><div class='add'>+		.is_two_pixels_per_container = dce110_is_two_pixels_per_container,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dce80_timing_generator_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile<br/>index ae6a131be71b..e1f6623d4936 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn10/Makefile</a></div><div class='hunk'>@@ -24,10 +24,7 @@</div><div class='ctx'> </div><div class='ctx'> DCN10 = dcn10_ipp.o \</div><div class='ctx'> 		dcn10_hw_sequencer_debug.o \</div><div class='del'>-		dcn10_dpp.o dcn10_opp.o \</div><div class='del'>-		dcn10_hubp.o dcn10_mpc.o \</div><div class='del'>-		dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \</div><div class='del'>-		dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o</div><div class='add'>+		dcn10_cm_common.o \</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c<br/>index b7e57aa27361..dcd2cdfe91eb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn10_dpp.h"</div><div class='add'>+#include "dcn10/dcn10_dpp.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn10_cm_common.h"</div><div class='ctx'> #include "custom_float.h"</div><div class='hunk'>@@ -365,23 +365,18 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx,</div><div class='ctx'> 		region_start = -MAX_LOW_POINT;</div><div class='ctx'> 		region_end   = NUMBER_REGIONS - MAX_LOW_POINT;</div><div class='ctx'> 	} else {</div><div class='del'>-		/* 11 segments</div><div class='del'>-		 * segment is from 2^-10 to 2^1</div><div class='add'>+		/* 13 segments</div><div class='add'>+		 * segment is from 2^-12 to 2^0</div><div class='ctx'> 		 * There are less than 256 points, for optimization</div><div class='ctx'> 		 */</div><div class='del'>-		seg_distr[0] = 3;</div><div class='del'>-		seg_distr[1] = 4;</div><div class='del'>-		seg_distr[2] = 4;</div><div class='del'>-		seg_distr[3] = 4;</div><div class='del'>-		seg_distr[4] = 4;</div><div class='del'>-		seg_distr[5] = 4;</div><div class='del'>-		seg_distr[6] = 4;</div><div class='del'>-		seg_distr[7] = 4;</div><div class='del'>-		seg_distr[8] = 4;</div><div class='del'>-		seg_distr[9] = 4;</div><div class='del'>-		seg_distr[10] = 1;</div><div class='del'>-</div><div class='del'>-		region_start = -10;</div><div class='add'>+		const uint8_t SEG_COUNT = 12;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; SEG_COUNT; i++)</div><div class='add'>+			seg_distr[i] = 4;</div><div class='add'>+</div><div class='add'>+		seg_distr[SEG_COUNT] = 1;</div><div class='add'>+</div><div class='add'>+		region_start = -SEG_COUNT;</div><div class='ctx'> 		region_end = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -402,6 +397,11 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx,</div><div class='ctx'> 				i += increment) {</div><div class='ctx'> 			if (j == hw_points - 1)</div><div class='ctx'> 				break;</div><div class='add'>+			if (i &gt;= TRANSFER_FUNC_POINTS) {</div><div class='add'>+				DC_LOG_ERROR("Index out of bounds: i=%d, TRANSFER_FUNC_POINTS=%d\n",</div><div class='add'>+					     i, TRANSFER_FUNC_POINTS);</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='ctx'> 			rgb_resulted[j].red = output_tf-&gt;tf_pts.red[i];</div><div class='ctx'> 			rgb_resulted[j].green = output_tf-&gt;tf_pts.green[i];</div><div class='ctx'> 			rgb_resulted[j].blue = output_tf-&gt;tf_pts.blue[i];</div><div class='hunk'>@@ -586,6 +586,8 @@ bool cm_helper_translate_curve_to_degamma_hw_format(</div><div class='ctx'> 				i += increment) {</div><div class='ctx'> 			if (j == hw_points - 1)</div><div class='ctx'> 				break;</div><div class='add'>+			if (i &gt;= TRANSFER_FUNC_POINTS)</div><div class='add'>+				return false;</div><div class='ctx'> 			rgb_resulted[j].red = output_tf-&gt;tf_pts.red[i];</div><div class='ctx'> 			rgb_resulted[j].green = output_tf-&gt;tf_pts.green[i];</div><div class='ctx'> 			rgb_resulted[j].blue = output_tf-&gt;tf_pts.blue[i];</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c<br/>index 9033b39e0e0c..baf663b661c8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c</a></div><div class='hunk'>@@ -40,13 +40,13 @@</div><div class='ctx'> #include "ipp.h"</div><div class='ctx'> #include "mpc.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn10_hubp.h"</div><div class='del'>-#include "dcn10_hubbub.h"</div><div class='add'>+#include "dcn10/dcn10_hubp.h"</div><div class='add'>+#include "dcn10/dcn10_hubbub.h"</div><div class='ctx'> #include "dcn10_cm_common.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> __printf(3, 4)</div><div class='del'>-unsigned int snprintf_count(char *pbuf, unsigned int bufsize, char *fmt, ...)</div><div class='add'>+unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt, ...)</div><div class='ctx'> {</div><div class='ctx'> 	int ret_vsnprintf;</div><div class='ctx'> 	unsigned int chars_printed;</div><div class='hunk'>@@ -392,7 +392,7 @@ static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned in</div><div class='ctx'> 	remaining_buffer -= chars_printed;</div><div class='ctx'> 	pBuf += chars_printed;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;mpcc_count; i++) {</div><div class='ctx'> 		struct mpcc_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		pool-&gt;mpc-&gt;funcs-&gt;read_mpcc_state(pool-&gt;mpc, i, &amp;s);</div><div class='hunk'>@@ -429,7 +429,9 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int</div><div class='ctx'> 		struct dcn_otg_state s = {0};</div><div class='ctx'> 		int pix_clk = 0;</div><div class='ctx'> </div><div class='del'>-		optc1_read_otg_state(DCN10TG_FROM_TG(tg), &amp;s);</div><div class='add'>+		if (tg-&gt;funcs-&gt;read_otg_state)</div><div class='add'>+			tg-&gt;funcs-&gt;read_otg_state(tg, &amp;s);</div><div class='add'>+</div><div class='ctx'> 		pix_clk = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;</div><div class='ctx'> </div><div class='ctx'> 		//only print if OTG master is enabled</div><div class='hunk'>@@ -495,7 +497,8 @@ static void dcn10_clear_otpc_underflow(struct dc *dc)</div><div class='ctx'> 		struct timing_generator *tg = pool-&gt;timing_generators[i];</div><div class='ctx'> 		struct dcn_otg_state s = {0};</div><div class='ctx'> </div><div class='del'>-		optc1_read_otg_state(DCN10TG_FROM_TG(tg), &amp;s);</div><div class='add'>+		if (tg-&gt;funcs-&gt;read_otg_state)</div><div class='add'>+			tg-&gt;funcs-&gt;read_otg_state(tg, &amp;s);</div><div class='ctx'> </div><div class='ctx'> 		if (s.otg_enabled &amp; 1)</div><div class='ctx'> 			tg-&gt;funcs-&gt;clear_optc_underflow(tg);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile<br/>index 3dae3943b056..25ba0d310d46 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn20/Makefile</a></div><div class='hunk'>@@ -1,11 +1,7 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='del'>-#</div><div class='del'>-# Makefile for DCN.</div><div class='add'>+# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'> </div><div class='del'>-DCN20 = dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \</div><div class='del'>-		dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_mmhubbub.o \</div><div class='del'>-		dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \</div><div class='del'>-		dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o</div><div class='add'>+DCN20 = dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c<br/>index f8667be57046..80779e85e2c5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c</a></div><div class='hunk'>@@ -299,6 +299,17 @@ void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+	if (dwbc20-&gt;dwbc_mask-&gt;WBSCL_COEF_RAM_SEL) {</div><div class='add'>+		/* Swap double buffered coefficient set */</div><div class='add'>+		uint32_t wbscl_mode = REG_READ(WBSCL_MODE);</div><div class='add'>+		bool coef_ram_current = get_reg_field_value_ex(</div><div class='add'>+			wbscl_mode, dwbc20-&gt;dwbc_mask-&gt;WBSCL_COEF_RAM_SEL_CURRENT,</div><div class='add'>+			dwbc20-&gt;dwbc_shift-&gt;WBSCL_COEF_RAM_SEL_CURRENT);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(WBSCL_MODE, WBSCL_COEF_RAM_SEL, !coef_ram_current);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dwbc_funcs dcn20_dwbc_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c<br/>index 994fb732a7cb..a0d437f0ce2b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c</a></div><div class='hunk'>@@ -690,6 +690,9 @@ static void wbscl_set_scaler_filter(</div><div class='ctx'> 	int pair;</div><div class='ctx'> 	uint16_t odd_coef, even_coef;</div><div class='ctx'> </div><div class='add'>+	if (!filter)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	for (phase = 0; phase &lt; (NUM_PHASES / 2 + 1); phase++) {</div><div class='ctx'> 		for (pair = 0; pair &lt; tap_pairs; pair++) {</div><div class='ctx'> 			even_coef = filter[phase * taps + 2 * pair];</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile<br/>index 2b0b4f32e13b..c9f4a5a9f522 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn201/Makefile</a></div><div class='hunk'>@@ -1,9 +1,8 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='del'>-#</div><div class='del'>-# Makefile for DCN.</div><div class='del'>-DCN201 = dcn201_hubbub.o\</div><div class='del'>-	dcn201_mpc.o dcn201_hubp.o dcn201_opp.o dcn201_dpp.o \</div><div class='del'>-	dcn201_dccg.o dcn201_link_encoder.o</div><div class='add'>+# Copyright © 2021-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='add'>+</div><div class='add'>+DCN201 = dcn201_mpc.o dcn201_opp.o \</div><div class='add'>+	dcn201_link_encoder.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN201 = $(addprefix $(AMDDALPATH)/dc/dcn201/,$(DCN201))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h<br/>index 8b95ef251332..be25e8dc0636 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h</a></div><div class='hunk'>@@ -30,6 +30,10 @@</div><div class='ctx'> </div><div class='ctx'> #define DPCS_DCN201_MASK_SH_LIST(mask_sh)\</div><div class='ctx'> 	DPCS_MASK_SH_LIST(mask_sh),\</div><div class='add'>+	LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD, mask_sh),\</div><div class='add'>+	LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, VCO_LD_VAL_OVRD_EN, mask_sh),\</div><div class='add'>+	LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD, mask_sh),\</div><div class='add'>+	LE_SF(DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, REF_LD_VAL_OVRD_EN, mask_sh),\</div><div class='ctx'> 	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\</div><div class='ctx'> 	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, mask_sh),\</div><div class='ctx'> 	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DP4, mask_sh),\</div><div class='hunk'>@@ -44,7 +48,15 @@</div><div class='ctx'> 	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_EN, mask_sh)</div><div class='ctx'> </div><div class='ctx'> #define DPCS_DCN201_REG_LIST(id) \</div><div class='del'>-	DPCS_DCN2_CMN_REG_LIST(id)</div><div class='add'>+	DPCS_DCN2_CMN_REG_LIST(id), \</div><div class='add'>+	SRI_IX(RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2, DPCSSYS_CR, id), \</div><div class='add'>+	SRI_IX(RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3, DPCSSYS_CR, id)</div><div class='ctx'> </div><div class='ctx'> void dcn201_link_encoder_construct(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c<br/>index 6a71ba3dfc63..e83367a9b6b3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c</a></div><div class='hunk'>@@ -54,6 +54,7 @@ static struct opp_funcs dcn201_opp_funcs = {</div><div class='ctx'> 		.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,</div><div class='ctx'> 		.opp_destroy = opp1_destroy,</div><div class='ctx'> 		.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,</div><div class='add'>+		.opp_get_left_edge_extra_pixel_count = opp2_get_left_edge_extra_pixel_count,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn201_opp_construct(struct dcn201_opp *oppn201,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h<br/>index aca389ec1779..edb7f9653cb6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h</a></div><div class='hunk'>@@ -42,8 +42,7 @@</div><div class='ctx'> 	OPP_MASK_SH_LIST_DCN20(mask_sh)</div><div class='ctx'> </div><div class='ctx'> #define OPP_DCN201_REG_FIELD_LIST(type) \</div><div class='del'>-	OPP_DCN20_REG_FIELD_LIST(type);</div><div class='del'>-</div><div class='add'>+	OPP_DCN20_REG_FIELD_LIST(type)</div><div class='ctx'> struct dcn201_opp_shift {</div><div class='ctx'> 	OPP_DCN201_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile<br/>index ca92f5c8e7fb..c215f3cc6e44 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn21/Makefile</a></div><div class='hunk'>@@ -1,9 +1,7 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='del'>-#</div><div class='del'>-# Makefile for DCN21.</div><div class='add'>+# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'> </div><div class='del'>-DCN21 = dcn21_hubp.o dcn21_hubbub.o \</div><div class='del'>-	 dcn21_link_encoder.o dcn21_dccg.o</div><div class='add'>+DCN21 = dcn21_link_encoder.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile<br/>index b5b2aa3b3783..b17277de0340 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn30/Makefile</a></div><div class='hunk'>@@ -23,21 +23,10 @@</div><div class='ctx'> #</div><div class='ctx'> #</div><div class='ctx'> </div><div class='del'>-DCN30 := dcn30_hubbub.o \</div><div class='del'>-	dcn30_hubp.o \</div><div class='del'>-	dcn30_dpp.o \</div><div class='del'>-	dcn30_dccg.o \</div><div class='del'>-	dcn30_mpc.o dcn30_vpg.o \</div><div class='add'>+DCN30 := dcn30_vpg.o \</div><div class='ctx'> 	dcn30_afmt.o \</div><div class='del'>-	dcn30_dio_stream_encoder.o \</div><div class='del'>-	dcn30_dwb.o \</div><div class='del'>-	dcn30_dpp_cm.o \</div><div class='del'>-	dcn30_dwb_cm.o \</div><div class='ctx'> 	dcn30_cm_common.o \</div><div class='ctx'> 	dcn30_mmhubbub.o \</div><div class='del'>-	dcn30_dio_link_encoder.o</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c<br/>index ddb344056d40..0690c346f2c5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c</a></div><div class='hunk'>@@ -26,9 +26,9 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn30_dpp.h"</div><div class='add'>+#include "dcn30/dcn30_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='del'>-#include "dcn30_cm_common.h"</div><div class='add'>+#include "dcn30/dcn30_cm_common.h"</div><div class='ctx'> #include "custom_float.h"</div><div class='ctx'> </div><div class='ctx'> #define REG(reg) reg</div><div class='hunk'>@@ -140,23 +140,18 @@ bool cm3_helper_translate_curve_to_hw_format(</div><div class='ctx'> 		region_start = -MAX_LOW_POINT;</div><div class='ctx'> 		region_end   = NUMBER_REGIONS - MAX_LOW_POINT;</div><div class='ctx'> 	} else {</div><div class='del'>-		/* 11 segments</div><div class='del'>-		 * segment is from 2^-10 to 2^0</div><div class='add'>+		/* 13 segments</div><div class='add'>+		 * segment is from 2^-12 to 2^0</div><div class='ctx'> 		 * There are less than 256 points, for optimization</div><div class='ctx'> 		 */</div><div class='del'>-		seg_distr[0] = 3;</div><div class='del'>-		seg_distr[1] = 4;</div><div class='del'>-		seg_distr[2] = 4;</div><div class='del'>-		seg_distr[3] = 4;</div><div class='del'>-		seg_distr[4] = 4;</div><div class='del'>-		seg_distr[5] = 4;</div><div class='del'>-		seg_distr[6] = 4;</div><div class='del'>-		seg_distr[7] = 4;</div><div class='del'>-		seg_distr[8] = 4;</div><div class='del'>-		seg_distr[9] = 4;</div><div class='del'>-		seg_distr[10] = 1;</div><div class='del'>-</div><div class='del'>-		region_start = -10;</div><div class='add'>+		const uint8_t SEG_COUNT = 12;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; SEG_COUNT; i++)</div><div class='add'>+			seg_distr[i] = 4;</div><div class='add'>+</div><div class='add'>+		seg_distr[SEG_COUNT] = 1;</div><div class='add'>+</div><div class='add'>+		region_start = -SEG_COUNT;</div><div class='ctx'> 		region_end = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -177,6 +172,8 @@ bool cm3_helper_translate_curve_to_hw_format(</div><div class='ctx'> 				i += increment) {</div><div class='ctx'> 			if (j == hw_points)</div><div class='ctx'> 				break;</div><div class='add'>+			if (i &gt;= TRANSFER_FUNC_POINTS)</div><div class='add'>+				return false;</div><div class='ctx'> 			rgb_resulted[j].red = output_tf-&gt;tf_pts.red[i];</div><div class='ctx'> 			rgb_resulted[j].green = output_tf-&gt;tf_pts.green[i];</div><div class='ctx'> 			rgb_resulted[j].blue = output_tf-&gt;tf_pts.blue[i];</div><div class='hunk'>@@ -283,155 +280,6 @@ bool cm3_helper_translate_curve_to_hw_format(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define NUM_DEGAMMA_REGIONS    12</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-bool cm3_helper_translate_curve_to_degamma_hw_format(</div><div class='del'>-				const struct dc_transfer_func *output_tf,</div><div class='del'>-				struct pwl_params *lut_params)</div><div class='del'>-{</div><div class='del'>-	struct curve_points3 *corner_points;</div><div class='del'>-	struct pwl_result_data *rgb_resulted;</div><div class='del'>-	struct pwl_result_data *rgb;</div><div class='del'>-	struct pwl_result_data *rgb_plus_1;</div><div class='del'>-</div><div class='del'>-	int32_t region_start, region_end;</div><div class='del'>-	int32_t i;</div><div class='del'>-	uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;</div><div class='del'>-</div><div class='del'>-	if (output_tf == NULL || lut_params == NULL || output_tf-&gt;type == TF_TYPE_BYPASS)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	corner_points = lut_params-&gt;corner_points;</div><div class='del'>-	rgb_resulted = lut_params-&gt;rgb_resulted;</div><div class='del'>-	hw_points = 0;</div><div class='del'>-</div><div class='del'>-	memset(lut_params, 0, sizeof(struct pwl_params));</div><div class='del'>-	memset(seg_distr, 0, sizeof(seg_distr));</div><div class='del'>-</div><div class='del'>-	region_start = -NUM_DEGAMMA_REGIONS;</div><div class='del'>-	region_end   = 0;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	for (i = region_end - region_start; i &lt; MAX_REGIONS_NUMBER ; i++)</div><div class='del'>-		seg_distr[i] = -1;</div><div class='del'>-	/* 12 segments</div><div class='del'>-	 * segments are from 2^-12 to 0</div><div class='del'>-	 */</div><div class='del'>-	for (i = 0; i &lt; NUM_DEGAMMA_REGIONS ; i++)</div><div class='del'>-		seg_distr[i] = 4;</div><div class='del'>-</div><div class='del'>-	for (k = 0; k &lt; MAX_REGIONS_NUMBER; k++) {</div><div class='del'>-		if (seg_distr[k] != -1)</div><div class='del'>-			hw_points += (1 &lt;&lt; seg_distr[k]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	j = 0;</div><div class='del'>-	for (k = 0; k &lt; (region_end - region_start); k++) {</div><div class='del'>-		increment = NUMBER_SW_SEGMENTS / (1 &lt;&lt; seg_distr[k]);</div><div class='del'>-		start_index = (region_start + k + MAX_LOW_POINT) *</div><div class='del'>-				NUMBER_SW_SEGMENTS;</div><div class='del'>-		for (i = start_index; i &lt; start_index + NUMBER_SW_SEGMENTS;</div><div class='del'>-				i += increment) {</div><div class='del'>-			if (j == hw_points - 1)</div><div class='del'>-				break;</div><div class='del'>-			rgb_resulted[j].red = output_tf-&gt;tf_pts.red[i];</div><div class='del'>-			rgb_resulted[j].green = output_tf-&gt;tf_pts.green[i];</div><div class='del'>-			rgb_resulted[j].blue = output_tf-&gt;tf_pts.blue[i];</div><div class='del'>-			j++;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* last point */</div><div class='del'>-	start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;</div><div class='del'>-	rgb_resulted[hw_points - 1].red = output_tf-&gt;tf_pts.red[start_index];</div><div class='del'>-	rgb_resulted[hw_points - 1].green = output_tf-&gt;tf_pts.green[start_index];</div><div class='del'>-	rgb_resulted[hw_points - 1].blue = output_tf-&gt;tf_pts.blue[start_index];</div><div class='del'>-</div><div class='del'>-	corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),</div><div class='del'>-					     dc_fixpt_from_int(region_start));</div><div class='del'>-	corner_points[0].green.x = corner_points[0].red.x;</div><div class='del'>-	corner_points[0].blue.x = corner_points[0].red.x;</div><div class='del'>-	corner_points[1].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),</div><div class='del'>-					     dc_fixpt_from_int(region_end));</div><div class='del'>-	corner_points[1].green.x = corner_points[1].red.x;</div><div class='del'>-	corner_points[1].blue.x = corner_points[1].red.x;</div><div class='del'>-</div><div class='del'>-	corner_points[0].red.y = rgb_resulted[0].red;</div><div class='del'>-	corner_points[0].green.y = rgb_resulted[0].green;</div><div class='del'>-	corner_points[0].blue.y = rgb_resulted[0].blue;</div><div class='del'>-</div><div class='del'>-	/* see comment above, m_arrPoints[1].y should be the Y value for the</div><div class='del'>-	 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)</div><div class='del'>-	 */</div><div class='del'>-	corner_points[1].red.y = rgb_resulted[hw_points - 1].red;</div><div class='del'>-	corner_points[1].green.y = rgb_resulted[hw_points - 1].green;</div><div class='del'>-	corner_points[1].blue.y = rgb_resulted[hw_points - 1].blue;</div><div class='del'>-	corner_points[1].red.slope = dc_fixpt_zero;</div><div class='del'>-	corner_points[1].green.slope = dc_fixpt_zero;</div><div class='del'>-	corner_points[1].blue.slope = dc_fixpt_zero;</div><div class='del'>-</div><div class='del'>-	if (output_tf-&gt;tf == TRANSFER_FUNCTION_PQ) {</div><div class='del'>-		/* for PQ, we want to have a straight line from last HW X point,</div><div class='del'>-		 * and the slope to be such that we hit 1.0 at 10000 nits.</div><div class='del'>-		 */</div><div class='del'>-		const struct fixed31_32 end_value =</div><div class='del'>-				dc_fixpt_from_int(125);</div><div class='del'>-</div><div class='del'>-		corner_points[1].red.slope = dc_fixpt_div(</div><div class='del'>-			dc_fixpt_sub(dc_fixpt_one, corner_points[1].red.y),</div><div class='del'>-			dc_fixpt_sub(end_value, corner_points[1].red.x));</div><div class='del'>-		corner_points[1].green.slope = dc_fixpt_div(</div><div class='del'>-			dc_fixpt_sub(dc_fixpt_one, corner_points[1].green.y),</div><div class='del'>-			dc_fixpt_sub(end_value, corner_points[1].green.x));</div><div class='del'>-		corner_points[1].blue.slope = dc_fixpt_div(</div><div class='del'>-			dc_fixpt_sub(dc_fixpt_one, corner_points[1].blue.y),</div><div class='del'>-			dc_fixpt_sub(end_value, corner_points[1].blue.x));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	lut_params-&gt;hw_points_num = hw_points;</div><div class='del'>-</div><div class='del'>-	k = 0;</div><div class='del'>-	for (i = 1; i &lt; MAX_REGIONS_NUMBER; i++) {</div><div class='del'>-		if (seg_distr[k] != -1) {</div><div class='del'>-			lut_params-&gt;arr_curve_points[k].segments_num =</div><div class='del'>-					seg_distr[k];</div><div class='del'>-			lut_params-&gt;arr_curve_points[i].offset =</div><div class='del'>-					lut_params-&gt;arr_curve_points[k].offset + (1 &lt;&lt; seg_distr[k]);</div><div class='del'>-		}</div><div class='del'>-		k++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (seg_distr[k] != -1)</div><div class='del'>-		lut_params-&gt;arr_curve_points[k].segments_num = seg_distr[k];</div><div class='del'>-</div><div class='del'>-	rgb = rgb_resulted;</div><div class='del'>-	rgb_plus_1 = rgb_resulted + 1;</div><div class='del'>-</div><div class='del'>-	i = 1;</div><div class='del'>-	while (i != hw_points + 1) {</div><div class='del'>-		if (dc_fixpt_lt(rgb_plus_1-&gt;red, rgb-&gt;red))</div><div class='del'>-			rgb_plus_1-&gt;red = rgb-&gt;red;</div><div class='del'>-		if (dc_fixpt_lt(rgb_plus_1-&gt;green, rgb-&gt;green))</div><div class='del'>-			rgb_plus_1-&gt;green = rgb-&gt;green;</div><div class='del'>-		if (dc_fixpt_lt(rgb_plus_1-&gt;blue, rgb-&gt;blue))</div><div class='del'>-			rgb_plus_1-&gt;blue = rgb-&gt;blue;</div><div class='del'>-</div><div class='del'>-		rgb-&gt;delta_red   = dc_fixpt_sub(rgb_plus_1-&gt;red,   rgb-&gt;red);</div><div class='del'>-		rgb-&gt;delta_green = dc_fixpt_sub(rgb_plus_1-&gt;green, rgb-&gt;green);</div><div class='del'>-		rgb-&gt;delta_blue  = dc_fixpt_sub(rgb_plus_1-&gt;blue,  rgb-&gt;blue);</div><div class='del'>-</div><div class='del'>-		++rgb_plus_1;</div><div class='del'>-		++rgb;</div><div class='del'>-		++i;</div><div class='del'>-	}</div><div class='del'>-	cm3_helper_convert_to_custom_float(rgb_resulted,</div><div class='del'>-						lut_params-&gt;corner_points,</div><div class='del'>-						hw_points, false);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool cm3_helper_convert_to_custom_float(</div><div class='ctx'> 		struct pwl_result_data *rgb_resulted,</div><div class='ctx'> 		struct curve_points3 *corner_points,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h<br/>index ed9a5549c389..466ba20b9c61 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #ifndef __DAL_DCN30_VPG_H__</div><div class='ctx'> #define __DAL_DCN30_VPG_H__</div><div class='ctx'> </div><div class='add'>+#include "vpg.h"</div><div class='ctx'> </div><div class='ctx'> #define DCN30_VPG_FROM_VPG(vpg)\</div><div class='ctx'> 	container_of(vpg, struct dcn30_vpg, base)</div><div class='hunk'>@@ -132,28 +133,6 @@ struct dcn30_vpg_mask {</div><div class='ctx'> 	VPG_DCN3_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct vpg;</div><div class='del'>-</div><div class='del'>-struct vpg_funcs {</div><div class='del'>-	void (*update_generic_info_packet)(</div><div class='del'>-		struct vpg *vpg,</div><div class='del'>-		uint32_t packet_index,</div><div class='del'>-		const struct dc_info_packet *info_packet,</div><div class='del'>-		bool immediate_update);</div><div class='del'>-</div><div class='del'>-	void (*vpg_poweron)(</div><div class='del'>-		struct vpg *vpg);</div><div class='del'>-</div><div class='del'>-	void (*vpg_powerdown)(</div><div class='del'>-		struct vpg *vpg);</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct vpg {</div><div class='del'>-	const struct vpg_funcs *funcs;</div><div class='del'>-	struct dc_context *ctx;</div><div class='del'>-	int inst;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct dcn30_vpg {</div><div class='ctx'> 	struct vpg base;</div><div class='ctx'> 	const struct dcn30_vpg_registers *regs;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile<br/>index d241f665e40a..fb4814ab3f05 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn301/Makefile</a></div><div class='hunk'>@@ -1,17 +1,9 @@</div><div class='del'>-#</div><div class='del'>-# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='add'>+# SPDX-License-Identifier: MIT</div><div class='add'>+# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn30.</div><div class='ctx'> </div><div class='del'>-DCN301 = dcn301_dccg.o \</div><div class='del'>-		dcn301_dio_link_encoder.o dcn301_panel_cntl.o dcn301_hubbub.o</div><div class='add'>+DCN301 = dcn301_panel_cntl.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/Makefile b/drivers/gpu/drm/amd/display/dc/dcn303/Makefile<br/>deleted file mode 100644<br/>index a954e316aca2..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn303/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,13 +0,0 @@</div><div class='del'>-# SPDX-License-Identifier: MIT</div><div class='del'>-#</div><div class='del'>-# Copyright (C) 2021 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn303.</div><div class='del'>-</div><div class='del'>-DCN3_03 = dcn303_init.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/dcn303/,$(DCN3_03))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_03)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile<br/>index 5d93ac16c03a..d510e4652c18 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn31/Makefile</a></div><div class='hunk'>@@ -1,18 +1,11 @@</div><div class='add'>+# SPDX-License-Identifier: MIT</div><div class='add'>+# Copyright © 2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'> #</div><div class='del'>-# Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn31.</div><div class='ctx'> </div><div class='del'>-DCN31 = dcn31_hubbub.o dcn31_hubp.o \</div><div class='del'>-	dcn31_dccg.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o \</div><div class='del'>-	dcn31_apg.o dcn31_hpo_dp_stream_encoder.o dcn31_hpo_dp_link_encoder.o \</div><div class='add'>+DCN31 = dcn31_panel_cntl.o \</div><div class='add'>+	dcn31_apg.o \</div><div class='ctx'> 	dcn31_afmt.o dcn31_vpg.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN31 = $(addprefix $(AMDDALPATH)/dc/dcn31/,$(DCN31))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c<br/>index 281be20b1a10..f9961a6446f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c</a></div><div class='hunk'>@@ -70,6 +70,7 @@ static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)</div><div class='ctx'> 	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);</div><div class='ctx'> 	struct dc_dmub_srv *dc_dmub_srv = panel_cntl-&gt;ctx-&gt;dmub_srv;</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='add'>+	uint32_t freq_to_set = panel_cntl-&gt;ctx-&gt;dc-&gt;debug.pwm_freq;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_dmub_srv)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -96,6 +97,19 @@ static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)</div><div class='ctx'> 	panel_cntl-&gt;stored_backlight_registers.PANEL_PWRSEQ_REF_DIV2 =</div><div class='ctx'> 		cmd.panel_cntl.data.bl_pwm_ref_div2;</div><div class='ctx'> </div><div class='add'>+	if (freq_to_set &gt;= MIN_DEBUG_FREQ_HZ &amp;&amp; freq_to_set &lt;= MAX_DEBUG_FREQ_HZ) {</div><div class='add'>+		uint32_t xtal = panel_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz;</div><div class='add'>+</div><div class='add'>+		memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+		cmd.panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;</div><div class='add'>+		cmd.panel_cntl.header.sub_type = DMUB_CMD__PANEL_DEBUG_PWM_FREQ;</div><div class='add'>+		cmd.panel_cntl.header.payload_bytes = sizeof(cmd.panel_cntl.data);</div><div class='add'>+		cmd.panel_cntl.data.pwrseq_inst = dcn31_panel_cntl-&gt;base.pwrseq_inst;</div><div class='add'>+		cmd.panel_cntl.data.bl_pwm_cntl = xtal;</div><div class='add'>+		cmd.panel_cntl.data.bl_pwm_period_cntl = freq_to_set;</div><div class='add'>+		if (!dc_wake_and_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='ctx'> 	return cmd.panel_cntl.data.current_backlight;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -154,24 +168,33 @@ void dcn31_panel_cntl_construct(</div><div class='ctx'> 	struct dcn31_panel_cntl *dcn31_panel_cntl,</div><div class='ctx'> 	const struct panel_cntl_init_data *init_data)</div><div class='ctx'> {</div><div class='del'>-	uint8_t pwrseq_inst = 0xF;</div><div class='ctx'> </div><div class='ctx'> 	dcn31_panel_cntl-&gt;base.funcs = &amp;dcn31_link_panel_cntl_funcs;</div><div class='ctx'> 	dcn31_panel_cntl-&gt;base.ctx = init_data-&gt;ctx;</div><div class='ctx'> 	dcn31_panel_cntl-&gt;base.inst = init_data-&gt;inst;</div><div class='ctx'> </div><div class='del'>-	switch (init_data-&gt;eng_id) {</div><div class='del'>-	case ENGINE_ID_DIGA:</div><div class='del'>-		pwrseq_inst = 0;</div><div class='del'>-		break;</div><div class='del'>-	case ENGINE_ID_DIGB:</div><div class='del'>-		pwrseq_inst = 1;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", init_data-&gt;eng_id);</div><div class='del'>-		ASSERT(false);</div><div class='del'>-		break;</div><div class='add'>+	if (dcn31_panel_cntl-&gt;base.ctx-&gt;dc-&gt;config.support_edp0_on_dp1) {</div><div class='add'>+		//If supported, power sequencer mapping shall follow the DIG instance</div><div class='add'>+		uint8_t pwrseq_inst = 0xF;</div><div class='add'>+</div><div class='add'>+		switch (init_data-&gt;eng_id) {</div><div class='add'>+		case ENGINE_ID_DIGA:</div><div class='add'>+			pwrseq_inst = 0;</div><div class='add'>+			break;</div><div class='add'>+		case ENGINE_ID_DIGB:</div><div class='add'>+			pwrseq_inst = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", init_data-&gt;eng_id);</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dcn31_panel_cntl-&gt;base.pwrseq_inst = pwrseq_inst;</div><div class='add'>+	} else {</div><div class='add'>+		/* If not supported, pwrseq will be assigned in order,</div><div class='add'>+		 * so first pwrseq will be assigned to first panel instance (legacy behavior)</div><div class='add'>+		 */</div><div class='add'>+		dcn31_panel_cntl-&gt;base.pwrseq_inst = dcn31_panel_cntl-&gt;base.inst;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	dcn31_panel_cntl-&gt;base.pwrseq_inst = pwrseq_inst;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h<br/>index d33ccd6ef8c3..8cf0259e211e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h</a></div><div class='hunk'>@@ -29,6 +29,9 @@</div><div class='ctx'> #include "panel_cntl.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='add'>+#define MIN_DEBUG_FREQ_HZ 200</div><div class='add'>+#define MAX_DEBUG_FREQ_HZ 6250</div><div class='add'>+</div><div class='ctx'> struct dcn31_panel_cntl {</div><div class='ctx'> 	struct panel_cntl base;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c<br/>index f1deb1c3c363..cfb923d85630 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.c</a></div><div class='hunk'>@@ -63,7 +63,12 @@ void vpg31_poweron(struct vpg *vpg)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn31_vpg *vpg31 = DCN31_VPG_FROM_VPG(vpg);</div><div class='ctx'> </div><div class='del'>-	if (vpg-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.vpg == false)</div><div class='add'>+	uint32_t vpg_gsp_mem_pwr_state;</div><div class='add'>+</div><div class='add'>+	REG_GET(VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, &amp;vpg_gsp_mem_pwr_state);</div><div class='add'>+</div><div class='add'>+	if (vpg-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.vpg == false &amp;&amp;</div><div class='add'>+			vpg_gsp_mem_pwr_state == 0)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE_2(VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, 1, VPG_GSP_LIGHT_SLEEP_FORCE, 0);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h<br/>index 0e76eabce441..609e58dbd056 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #ifndef __DAL_DCN31_VPG_H__</div><div class='ctx'> #define __DAL_DCN31_VPG_H__</div><div class='ctx'> </div><div class='add'>+#include "vpg.h"</div><div class='ctx'> </div><div class='ctx'> #define DCN31_VPG_FROM_VPG(vpg)\</div><div class='ctx'> 	container_of(vpg, struct dcn31_vpg, base)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/Makefile b/drivers/gpu/drm/amd/display/dc/dcn314/Makefile<br/>deleted file mode 100644<br/>index b134ab05aa71..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn314/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,17 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn314.</div><div class='del'>-</div><div class='del'>-DCN314 = dcn314_dio_stream_encoder.o dcn314_dccg.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN314 = $(addprefix $(AMDDALPATH)/dc/dcn314/,$(DCN314))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN314)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile<br/>deleted file mode 100644<br/>index 5314770fff1c..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,20 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn32.</div><div class='del'>-</div><div class='del'>-DCN32 = dcn32_hubbub.o dcn32_dccg.o \</div><div class='del'>-		dcn32_mmhubbub.o dcn32_dpp.o dcn32_hubp.o dcn32_mpc.o \</div><div class='del'>-		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_resource_helpers.o \</div><div class='del'>-		dcn32_hpo_dp_link_encoder.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN32)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile<br/>deleted file mode 100644<br/>index c195c47f58b4..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn321/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,17 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn321.</div><div class='del'>-</div><div class='del'>-DCN321 = dcn321_dio_link_encoder.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN321)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/Makefile b/drivers/gpu/drm/amd/display/dc/dcn35/Makefile<br/>deleted file mode 100644<br/>index 0e317e0c36a0..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,20 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for DCN35.</div><div class='del'>-</div><div class='del'>-DCN35 = dcn35_dio_stream_encoder.o \</div><div class='del'>-	dcn35_dio_link_encoder.o dcn35_dccg.o \</div><div class='del'>-	dcn35_hubp.o dcn35_hubbub.o \</div><div class='del'>-	dcn35_mmhubbub.o dcn35_opp.o dcn35_dpp.o dcn35_pg_cntl.o dcn35_dwb.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN35 = $(addprefix $(AMDDALPATH)/dc/dcn35/,$(DCN35))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN35)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c<br/>deleted file mode 100644<br/>index f1ba7bb792ea..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,893 +0,0 @@</div><div class='del'>-/* SPDX-License-Identifier: MIT */</div><div class='del'>-/*</div><div class='del'>- * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include "reg_helper.h"</div><div class='del'>-#include "core_types.h"</div><div class='del'>-#include "dcn35_dccg.h"</div><div class='del'>-</div><div class='del'>-#define TO_DCN_DCCG(dccg)\</div><div class='del'>-	container_of(dccg, struct dcn_dccg, base)</div><div class='del'>-</div><div class='del'>-#define REG(reg) \</div><div class='del'>-	(dccg_dcn-&gt;regs-&gt;reg)</div><div class='del'>-</div><div class='del'>-#undef FN</div><div class='del'>-#define FN(reg_name, field_name) \</div><div class='del'>-	dccg_dcn-&gt;dccg_shift-&gt;field_name, dccg_dcn-&gt;dccg_mask-&gt;field_name</div><div class='del'>-</div><div class='del'>-#define CTX \</div><div class='del'>-	dccg_dcn-&gt;base.ctx</div><div class='del'>-#define DC_LOGGER \</div><div class='del'>-	dccg-&gt;ctx-&gt;logger</div><div class='del'>-</div><div class='del'>-static void dcn35_set_dppclk_enable(struct dccg *dccg,</div><div class='del'>-				 uint32_t dpp_inst, uint32_t enable)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	switch (dpp_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,</div><div class='del'>-				  int req_dppclk)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	if (dccg-&gt;dpp_clock_gated[dpp_inst]) {</div><div class='del'>-		/*</div><div class='del'>-		 * Do not update the DPPCLK DTO if the clock is stopped.</div><div class='del'>-		 */</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (dccg-&gt;ref_dppclk &amp;&amp; req_dppclk) {</div><div class='del'>-		int ref_dppclk = dccg-&gt;ref_dppclk;</div><div class='del'>-		int modulo, phase;</div><div class='del'>-</div><div class='del'>-		// phase / modulo = dpp pipe clk / dpp global clk</div><div class='del'>-		modulo = 0xff;   // use FF at the end</div><div class='del'>-		phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;</div><div class='del'>-</div><div class='del'>-		if (phase &gt; 0xff) {</div><div class='del'>-			ASSERT(false);</div><div class='del'>-			phase = 0xff;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='del'>-				DPPCLK0_DTO_PHASE, phase,</div><div class='del'>-				DPPCLK0_DTO_MODULO, modulo);</div><div class='del'>-</div><div class='del'>-		dcn35_set_dppclk_enable(dccg, dpp_inst, true);</div><div class='del'>-	} else</div><div class='del'>-		dcn35_set_dppclk_enable(dccg, dpp_inst, false);</div><div class='del'>-	dccg-&gt;pipe_dppclk_khz[dpp_inst] = req_dppclk;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_get_pixel_rate_div(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		uint32_t otg_inst,</div><div class='del'>-		enum pixel_rate_div *k1,</div><div class='del'>-		enum pixel_rate_div *k2)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-	uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA;</div><div class='del'>-</div><div class='del'>-	*k1 = PIXEL_RATE_DIV_NA;</div><div class='del'>-	*k2 = PIXEL_RATE_DIV_NA;</div><div class='del'>-</div><div class='del'>-	switch (otg_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-			OTG0_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='del'>-			OTG0_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-			OTG1_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='del'>-			OTG1_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-			OTG2_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='del'>-			OTG2_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_GET_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-			OTG3_PIXEL_RATE_DIVK1, &amp;val_k1,</div><div class='del'>-			OTG3_PIXEL_RATE_DIVK2, &amp;val_k2);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	*k1 = (enum pixel_rate_div)val_k1;</div><div class='del'>-	*k2 = (enum pixel_rate_div)val_k2;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_set_pixel_rate_div(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		uint32_t otg_inst,</div><div class='del'>-		enum pixel_rate_div k1,</div><div class='del'>-		enum pixel_rate_div k2)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-	enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA;</div><div class='del'>-</div><div class='del'>-	// Don't program 0xF into the register field. Not valid since</div><div class='del'>-	// K1 / K2 field is only 1 / 2 bits wide</div><div class='del'>-	if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) {</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dccg35_get_pixel_rate_div(dccg, otg_inst, &amp;cur_k1, &amp;cur_k2);</div><div class='del'>-	if (k1 == cur_k1 &amp;&amp; k2 == cur_k2)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (otg_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-				OTG0_PIXEL_RATE_DIVK1, k1,</div><div class='del'>-				OTG0_PIXEL_RATE_DIVK2, k2);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-				OTG1_PIXEL_RATE_DIVK1, k1,</div><div class='del'>-				OTG1_PIXEL_RATE_DIVK2, k2);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-				OTG2_PIXEL_RATE_DIVK1, k1,</div><div class='del'>-				OTG2_PIXEL_RATE_DIVK2, k2);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE_2(OTG_PIXEL_RATE_DIV,</div><div class='del'>-				OTG3_PIXEL_RATE_DIVK1, k1,</div><div class='del'>-				OTG3_PIXEL_RATE_DIVK2, k2);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_set_dtbclk_p_src(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		enum streamclk_source src,</div><div class='del'>-		uint32_t otg_inst)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	uint32_t p_src_sel = 0; /* selects dprefclk */</div><div class='del'>-	if (src == DTBCLK0)</div><div class='del'>-		p_src_sel = 2;  /* selects dtbclk0 */</div><div class='del'>-</div><div class='del'>-	switch (otg_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		if (src == REFCLK)</div><div class='del'>-			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P0_EN, 0);</div><div class='del'>-		else</div><div class='del'>-			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P0_SRC_SEL, p_src_sel,</div><div class='del'>-					DTBCLK_P0_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		if (src == REFCLK)</div><div class='del'>-			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P1_EN, 0);</div><div class='del'>-		else</div><div class='del'>-			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P1_SRC_SEL, p_src_sel,</div><div class='del'>-					DTBCLK_P1_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		if (src == REFCLK)</div><div class='del'>-			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P2_EN, 0);</div><div class='del'>-		else</div><div class='del'>-			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P2_SRC_SEL, p_src_sel,</div><div class='del'>-					DTBCLK_P2_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		if (src == REFCLK)</div><div class='del'>-			REG_UPDATE(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P3_EN, 0);</div><div class='del'>-		else</div><div class='del'>-			REG_UPDATE_2(DTBCLK_P_CNTL,</div><div class='del'>-					DTBCLK_P3_SRC_SEL, p_src_sel,</div><div class='del'>-					DTBCLK_P3_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Controls the generation of pixel valid for OTG in (OTG -&gt; HPO case) */</div><div class='del'>-static void dccg35_set_dtbclk_dto(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		const struct dtbclk_dto_params *params)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-	/* DTO Output Rate / Pixel Rate = 1/4 */</div><div class='del'>-	int req_dtbclk_khz = params-&gt;pixclk_khz / 4;</div><div class='del'>-</div><div class='del'>-	if (params-&gt;ref_dtbclk_khz &amp;&amp; req_dtbclk_khz) {</div><div class='del'>-		uint32_t modulo, phase;</div><div class='del'>-</div><div class='del'>-		switch (params-&gt;otg_inst) {</div><div class='del'>-		case 0:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);</div><div class='del'>-			break;</div><div class='del'>-		case 1:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);</div><div class='del'>-			break;</div><div class='del'>-		case 2:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);</div><div class='del'>-			break;</div><div class='del'>-		case 3:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		// phase / modulo = dtbclk / dtbclk ref</div><div class='del'>-		modulo = params-&gt;ref_dtbclk_khz * 1000;</div><div class='del'>-		phase = req_dtbclk_khz * 1000;</div><div class='del'>-</div><div class='del'>-		REG_WRITE(DTBCLK_DTO_MODULO[params-&gt;otg_inst], modulo);</div><div class='del'>-		REG_WRITE(DTBCLK_DTO_PHASE[params-&gt;otg_inst], phase);</div><div class='del'>-</div><div class='del'>-		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='del'>-				DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 1);</div><div class='del'>-</div><div class='del'>-		REG_WAIT(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='del'>-				DTBCLKDTO_ENABLE_STATUS[params-&gt;otg_inst], 1,</div><div class='del'>-				1, 100);</div><div class='del'>-</div><div class='del'>-		/* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */</div><div class='del'>-		dccg35_set_pixel_rate_div(dccg, params-&gt;otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);</div><div class='del'>-</div><div class='del'>-		/* The recommended programming sequence to enable DTBCLK DTO to generate</div><div class='del'>-		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should</div><div class='del'>-		 * be set only after DTO is enabled</div><div class='del'>-		 */</div><div class='del'>-		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='del'>-				PIPE_DTO_SRC_SEL[params-&gt;otg_inst], 2);</div><div class='del'>-	} else {</div><div class='del'>-		switch (params-&gt;otg_inst) {</div><div class='del'>-		case 0:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 1:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 2:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 3:</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='del'>-				DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 0,</div><div class='del'>-				PIPE_DTO_SRC_SEL[params-&gt;otg_inst], params-&gt;is_hdmi ? 0 : 1);</div><div class='del'>-</div><div class='del'>-		REG_WRITE(DTBCLK_DTO_MODULO[params-&gt;otg_inst], 0);</div><div class='del'>-		REG_WRITE(DTBCLK_DTO_PHASE[params-&gt;otg_inst], 0);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_set_dpstreamclk(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		enum streamclk_source src,</div><div class='del'>-		int otg_inst,</div><div class='del'>-		int dp_hpo_inst)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	/* set the dtbclk_p source */</div><div class='del'>-	dccg35_set_dtbclk_p_src(dccg, src, otg_inst);</div><div class='del'>-</div><div class='del'>-	/* enabled to select one of the DTBCLKs for pipe */</div><div class='del'>-	switch (dp_hpo_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE_2(DPSTREAMCLK_CNTL,</div><div class='del'>-				DPSTREAMCLK0_EN,</div><div class='del'>-				(src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,</div><div class='del'>-				(src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,</div><div class='del'>-				(src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,</div><div class='del'>-				(src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_set_physymclk_root_clock_gating(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		int phy_inst,</div><div class='del'>-		bool enable)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (phy_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='del'>-				PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='del'>-				PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='del'>-				PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='del'>-				PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,</div><div class='del'>-				PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_set_physymclk(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		int phy_inst,</div><div class='del'>-		enum physymclk_clock_source clk_src,</div><div class='del'>-		bool force_enable)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */</div><div class='del'>-	switch (phy_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		if (force_enable) {</div><div class='del'>-			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYASYMCLK_EN, 1,</div><div class='del'>-					PHYASYMCLK_SRC_SEL, clk_src);</div><div class='del'>-		} else {</div><div class='del'>-			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYASYMCLK_EN, 0,</div><div class='del'>-					PHYASYMCLK_SRC_SEL, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		if (force_enable) {</div><div class='del'>-			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYBSYMCLK_EN, 1,</div><div class='del'>-					PHYBSYMCLK_SRC_SEL, clk_src);</div><div class='del'>-		} else {</div><div class='del'>-			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYBSYMCLK_EN, 0,</div><div class='del'>-					PHYBSYMCLK_SRC_SEL, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		if (force_enable) {</div><div class='del'>-			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYCSYMCLK_EN, 1,</div><div class='del'>-					PHYCSYMCLK_SRC_SEL, clk_src);</div><div class='del'>-		} else {</div><div class='del'>-			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYCSYMCLK_EN, 0,</div><div class='del'>-					PHYCSYMCLK_SRC_SEL, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		if (force_enable) {</div><div class='del'>-			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYDSYMCLK_EN, 1,</div><div class='del'>-					PHYDSYMCLK_SRC_SEL, clk_src);</div><div class='del'>-		} else {</div><div class='del'>-			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYDSYMCLK_EN, 0,</div><div class='del'>-					PHYDSYMCLK_SRC_SEL, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		if (force_enable) {</div><div class='del'>-			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYESYMCLK_EN, 1,</div><div class='del'>-					PHYESYMCLK_SRC_SEL, clk_src);</div><div class='del'>-		} else {</div><div class='del'>-			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,</div><div class='del'>-					PHYESYMCLK_EN, 0,</div><div class='del'>-					PHYESYMCLK_SRC_SEL, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_set_valid_pixel_rate(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		int ref_dtbclk_khz,</div><div class='del'>-		int otg_inst,</div><div class='del'>-		int pixclk_khz)</div><div class='del'>-{</div><div class='del'>-	struct dtbclk_dto_params dto_params = {0};</div><div class='del'>-</div><div class='del'>-	dto_params.ref_dtbclk_khz = ref_dtbclk_khz;</div><div class='del'>-	dto_params.otg_inst = otg_inst;</div><div class='del'>-	dto_params.pixclk_khz = pixclk_khz;</div><div class='del'>-	dto_params.is_hdmi = true;</div><div class='del'>-</div><div class='del'>-	dccg35_set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_dpp_root_clock_control(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		unsigned int dpp_inst,</div><div class='del'>-		bool clock_on)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	if (dccg-&gt;dpp_clock_gated[dpp_inst] == clock_on)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (clock_on) {</div><div class='del'>-		/* turn off the DTO and leave phase/modulo at max */</div><div class='del'>-		dcn35_set_dppclk_enable(dccg, dpp_inst, 0);</div><div class='del'>-		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='del'>-			  DPPCLK0_DTO_PHASE, 0xFF,</div><div class='del'>-			  DPPCLK0_DTO_MODULO, 0xFF);</div><div class='del'>-	} else {</div><div class='del'>-		dcn35_set_dppclk_enable(dccg, dpp_inst, 1);</div><div class='del'>-		/* turn on the DTO to generate a 0hz clock */</div><div class='del'>-		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,</div><div class='del'>-			  DPPCLK0_DTO_PHASE, 0,</div><div class='del'>-			  DPPCLK0_DTO_MODULO, 1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dccg-&gt;dpp_clock_gated[dpp_inst] = !clock_on;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_disable_symclk32_se(</div><div class='del'>-		struct dccg *dccg,</div><div class='del'>-		int hpo_se_inst)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	/* set refclk as the source for symclk32_se */</div><div class='del'>-	switch (hpo_se_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='del'>-				SYMCLK32_SE0_SRC_SEL, 0,</div><div class='del'>-				SYMCLK32_SE0_EN, 0);</div><div class='del'>-		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-					SYMCLK32_SE0_GATE_DISABLE, 0);</div><div class='del'>-//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-//					SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='del'>-				SYMCLK32_SE1_SRC_SEL, 0,</div><div class='del'>-				SYMCLK32_SE1_EN, 0);</div><div class='del'>-		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-					SYMCLK32_SE1_GATE_DISABLE, 0);</div><div class='del'>-//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-//					SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='del'>-				SYMCLK32_SE2_SRC_SEL, 0,</div><div class='del'>-				SYMCLK32_SE2_EN, 0);</div><div class='del'>-		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-					SYMCLK32_SE2_GATE_DISABLE, 0);</div><div class='del'>-//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-//					SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='del'>-				SYMCLK32_SE3_SRC_SEL, 0,</div><div class='del'>-				SYMCLK32_SE3_EN, 0);</div><div class='del'>-		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='del'>-			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-					SYMCLK32_SE3_GATE_DISABLE, 0);</div><div class='del'>-//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='del'>-//					SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dccg35_init(struct dccg *dccg)</div><div class='del'>-{</div><div class='del'>-	int otg_inst;</div><div class='del'>-	/* Set HPO stream encoder to use refclk to avoid case where PHY is</div><div class='del'>-	 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which</div><div class='del'>-	 * will cause DCN to hang.</div><div class='del'>-	 */</div><div class='del'>-	for (otg_inst = 0; otg_inst &lt; 4; otg_inst++)</div><div class='del'>-		dccg35_disable_symclk32_se(dccg, otg_inst);</div><div class='del'>-</div><div class='del'>-	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='del'>-		for (otg_inst = 0; otg_inst &lt; 2; otg_inst++)</div><div class='del'>-			dccg31_disable_symclk32_le(dccg, otg_inst);</div><div class='del'>-</div><div class='del'>-	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='del'>-		for (otg_inst = 0; otg_inst &lt; 4; otg_inst++)</div><div class='del'>-			dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst,</div><div class='del'>-						otg_inst);</div><div class='del'>-</div><div class='del'>-	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='del'>-		for (otg_inst = 0; otg_inst &lt; 5; otg_inst++)</div><div class='del'>-			dccg35_set_physymclk_root_clock_gating(dccg, otg_inst,</div><div class='del'>-					false);</div><div class='del'>-/*</div><div class='del'>-	dccg35_enable_global_fgcg_rep(</div><div class='del'>-		dccg, dccg-&gt;ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits</div><div class='del'>-			      .dccg_global_fgcg_rep);*/</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_enable_dscclk(struct dccg *dccg, int inst)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	//Disable DTO</div><div class='del'>-	switch (inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE_2(DSCCLK0_DTO_PARAM,</div><div class='del'>-				DSCCLK0_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK0_DTO_MODULO, 0);</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL,	DSCCLK0_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE_2(DSCCLK1_DTO_PARAM,</div><div class='del'>-				DSCCLK1_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK1_DTO_MODULO, 0);</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE_2(DSCCLK2_DTO_PARAM,</div><div class='del'>-				DSCCLK2_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK2_DTO_MODULO, 0);</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE_2(DSCCLK3_DTO_PARAM,</div><div class='del'>-				DSCCLK3_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK3_DTO_MODULO, 0);</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_disable_dscclk(struct dccg *dccg,</div><div class='del'>-				int inst)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	if (!dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dsc)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);</div><div class='del'>-		REG_UPDATE_2(DSCCLK0_DTO_PARAM,</div><div class='del'>-				DSCCLK0_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK0_DTO_MODULO, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0);</div><div class='del'>-		REG_UPDATE_2(DSCCLK1_DTO_PARAM,</div><div class='del'>-				DSCCLK1_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK1_DTO_MODULO, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0);</div><div class='del'>-		REG_UPDATE_2(DSCCLK2_DTO_PARAM,</div><div class='del'>-				DSCCLK2_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK2_DTO_MODULO, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0);</div><div class='del'>-		REG_UPDATE_2(DSCCLK3_DTO_PARAM,</div><div class='del'>-				DSCCLK3_DTO_PHASE, 0,</div><div class='del'>-				DSCCLK3_DTO_MODULO, 1);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	switch (link_enc_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE(SYMCLKA_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKA_CLOCK_ENABLE, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE(SYMCLKB_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKB_CLOCK_ENABLE, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE(SYMCLKC_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKC_CLOCK_ENABLE, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE(SYMCLKD_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKD_CLOCK_ENABLE, 1);</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		REG_UPDATE(SYMCLKE_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKE_CLOCK_ENABLE, 1);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (stream_enc_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKA_FE_EN, 1,</div><div class='del'>-				SYMCLKA_FE_SRC_SEL, link_enc_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKB_FE_EN, 1,</div><div class='del'>-				SYMCLKB_FE_SRC_SEL, link_enc_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKC_FE_EN, 1,</div><div class='del'>-				SYMCLKC_FE_SRC_SEL, link_enc_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKD_FE_EN, 1,</div><div class='del'>-				SYMCLKD_FE_SRC_SEL, link_enc_inst);</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKE_FE_EN, 1,</div><div class='del'>-				SYMCLKE_FE_SRC_SEL, link_enc_inst);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*get other front end connected to this backend*/</div><div class='del'>-static uint8_t dccg35_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='del'>-{</div><div class='del'>-	uint8_t num_enabled_symclk_fe = 0;</div><div class='del'>-	uint32_t be_clk_en = 0, fe_clk_en[5] = {0}, be_clk_sel[5] = {0};</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	switch (link_enc_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, &amp;be_clk_en,</div><div class='del'>-				SYMCLKA_FE_EN, &amp;fe_clk_en[0],</div><div class='del'>-				SYMCLKA_FE_SRC_SEL, &amp;be_clk_sel[0]);</div><div class='del'>-				break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, &amp;be_clk_en,</div><div class='del'>-				SYMCLKB_FE_EN, &amp;fe_clk_en[1],</div><div class='del'>-				SYMCLKB_FE_SRC_SEL, &amp;be_clk_sel[1]);</div><div class='del'>-				break;</div><div class='del'>-	case 2:</div><div class='del'>-			REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, &amp;be_clk_en,</div><div class='del'>-				SYMCLKC_FE_EN, &amp;fe_clk_en[2],</div><div class='del'>-				SYMCLKC_FE_SRC_SEL, &amp;be_clk_sel[2]);</div><div class='del'>-				break;</div><div class='del'>-	case 3:</div><div class='del'>-			REG_GET_3(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, &amp;be_clk_en,</div><div class='del'>-				SYMCLKD_FE_EN, &amp;fe_clk_en[3],</div><div class='del'>-				SYMCLKD_FE_SRC_SEL, &amp;be_clk_sel[3]);</div><div class='del'>-				break;</div><div class='del'>-	case 4:</div><div class='del'>-			REG_GET_3(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, &amp;be_clk_en,</div><div class='del'>-				SYMCLKE_FE_EN, &amp;fe_clk_en[4],</div><div class='del'>-				SYMCLKE_FE_SRC_SEL, &amp;be_clk_sel[4]);</div><div class='del'>-				break;</div><div class='del'>-	}</div><div class='del'>-	if (be_clk_en) {</div><div class='del'>-	/* for DPMST, this backend could be used by multiple front end.</div><div class='del'>-	only disable the backend if this stream_enc_ins is the last active stream enc connected to this back_end*/</div><div class='del'>-		uint8_t i;</div><div class='del'>-		for (i = 0; i != link_enc_inst &amp;&amp; i &lt; sizeof(fe_clk_en); i++) {</div><div class='del'>-			if (fe_clk_en[i] &amp;&amp; be_clk_sel[i] == link_enc_inst)</div><div class='del'>-				num_enabled_symclk_fe++;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return num_enabled_symclk_fe;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)</div><div class='del'>-{</div><div class='del'>-	uint8_t num_enabled_symclk_fe = 0;</div><div class='del'>-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='del'>-</div><div class='del'>-	switch (stream_enc_inst) {</div><div class='del'>-	case 0:</div><div class='del'>-		REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKA_FE_EN, 0,</div><div class='del'>-				SYMCLKA_FE_SRC_SEL, 0);</div><div class='del'>-		break;</div><div class='del'>-	case 1:</div><div class='del'>-		REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKB_FE_EN, 0,</div><div class='del'>-				SYMCLKB_FE_SRC_SEL, 0);</div><div class='del'>-		break;</div><div class='del'>-	case 2:</div><div class='del'>-		REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKC_FE_EN, 0,</div><div class='del'>-				SYMCLKC_FE_SRC_SEL, 0);</div><div class='del'>-		break;</div><div class='del'>-	case 3:</div><div class='del'>-		REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKD_FE_EN, 0,</div><div class='del'>-				SYMCLKD_FE_SRC_SEL, 0);</div><div class='del'>-		break;</div><div class='del'>-	case 4:</div><div class='del'>-		REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE,</div><div class='del'>-				SYMCLKE_FE_EN, 0,</div><div class='del'>-				SYMCLKE_FE_SRC_SEL, 0);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*check other enabled symclk fe */</div><div class='del'>-	num_enabled_symclk_fe = dccg35_get_other_enabled_symclk_fe(dccg, stream_enc_inst, link_enc_inst);</div><div class='del'>-	/*only turn off backend clk if other front end attachecd to this backend are all off,</div><div class='del'>-	 for mst, only turn off the backend if this is the last front end*/</div><div class='del'>-	if (num_enabled_symclk_fe == 0) {</div><div class='del'>-		switch (link_enc_inst) {</div><div class='del'>-		case 0:</div><div class='del'>-			REG_UPDATE(SYMCLKA_CLOCK_ENABLE,</div><div class='del'>-					SYMCLKA_CLOCK_ENABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 1:</div><div class='del'>-			REG_UPDATE(SYMCLKB_CLOCK_ENABLE,</div><div class='del'>-					SYMCLKB_CLOCK_ENABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 2:</div><div class='del'>-			REG_UPDATE(SYMCLKC_CLOCK_ENABLE,</div><div class='del'>-					SYMCLKC_CLOCK_ENABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 3:</div><div class='del'>-			REG_UPDATE(SYMCLKD_CLOCK_ENABLE,</div><div class='del'>-					SYMCLKD_CLOCK_ENABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		case 4:</div><div class='del'>-			REG_UPDATE(SYMCLKE_CLOCK_ENABLE,</div><div class='del'>-					SYMCLKE_CLOCK_ENABLE, 0);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct dccg_funcs dccg35_funcs = {</div><div class='del'>-	.update_dpp_dto = dccg35_update_dpp_dto,</div><div class='del'>-	.dpp_root_clock_control = dccg35_dpp_root_clock_control,</div><div class='del'>-	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,</div><div class='del'>-	.dccg_init = dccg35_init,</div><div class='del'>-	.set_dpstreamclk = dccg35_set_dpstreamclk,</div><div class='del'>-	.enable_symclk32_se = dccg31_enable_symclk32_se,</div><div class='del'>-	.disable_symclk32_se = dccg35_disable_symclk32_se,</div><div class='del'>-	.enable_symclk32_le = dccg31_enable_symclk32_le,</div><div class='del'>-	.disable_symclk32_le = dccg31_disable_symclk32_le,</div><div class='del'>-	.set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,</div><div class='del'>-	.set_physymclk = dccg35_set_physymclk,</div><div class='del'>-	.set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating,</div><div class='del'>-	.set_dtbclk_dto = dccg35_set_dtbclk_dto,</div><div class='del'>-	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,</div><div class='del'>-	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,</div><div class='del'>-	.otg_add_pixel = dccg31_otg_add_pixel,</div><div class='del'>-	.otg_drop_pixel = dccg31_otg_drop_pixel,</div><div class='del'>-	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,</div><div class='del'>-	.disable_dsc = dccg35_disable_dscclk,</div><div class='del'>-	.enable_dsc = dccg35_enable_dscclk,</div><div class='del'>-	.set_pixel_rate_div = dccg35_set_pixel_rate_div,</div><div class='del'>-	.set_valid_pixel_rate = dccg35_set_valid_pixel_rate,</div><div class='del'>-	.enable_symclk_se = dccg35_enable_symclk_se,</div><div class='del'>-	.disable_symclk_se = dccg35_disable_symclk_se,</div><div class='del'>-	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct dccg *dccg35_create(</div><div class='del'>-	struct dc_context *ctx,</div><div class='del'>-	const struct dccg_registers *regs,</div><div class='del'>-	const struct dccg_shift *dccg_shift,</div><div class='del'>-	const struct dccg_mask *dccg_mask)</div><div class='del'>-{</div><div class='del'>-	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);</div><div class='del'>-	struct dccg *base;</div><div class='del'>-</div><div class='del'>-	if (dccg_dcn == NULL) {</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		return NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	base = &amp;dccg_dcn-&gt;base;</div><div class='del'>-	base-&gt;ctx = ctx;</div><div class='del'>-	base-&gt;funcs = &amp;dccg35_funcs;</div><div class='del'>-</div><div class='del'>-	dccg_dcn-&gt;regs = regs;</div><div class='del'>-	dccg_dcn-&gt;dccg_shift = dccg_shift;</div><div class='del'>-	dccg_dcn-&gt;dccg_mask = dccg_mask;</div><div class='del'>-</div><div class='del'>-	return &amp;dccg_dcn-&gt;base;</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile b/drivers/gpu/drm/amd/display/dc/dio/Makefile<br/>new file mode 100644<br/>index 000000000000..0dfd480976f7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/Makefile</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN10</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/dio/dcn10/,$(DIO_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN10)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN20</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN20 = dcn20_link_encoder.o dcn20_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/dio/dcn20/,$(DIO_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN30</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN30 = dcn30_dio_link_encoder.o dcn30_dio_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN30 = $(addprefix $(AMDDALPATH)/dc/dio/dcn30/,$(DIO_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN301</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN301 = dcn301_dio_link_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN301 = $(addprefix $(AMDDALPATH)/dc/dio/dcn301/,$(DIO_DCN301))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN301)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN31</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN31 = dcn31_dio_link_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN31 = $(addprefix $(AMDDALPATH)/dc/dio/dcn31/,$(DIO_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN31)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN314</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN314 = dcn314_dio_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN314 = $(addprefix $(AMDDALPATH)/dc/dio/dcn314/,$(DIO_DCN314))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN314)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN32</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN32 = dcn32_dio_link_encoder.o dcn32_dio_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN32 = $(addprefix $(AMDDALPATH)/dc/dio/dcn32/,$(DIO_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN35</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN35 = dcn35_dio_link_encoder.o dcn35_dio_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN35 = $(addprefix $(AMDDALPATH)/dc/dio/dcn35/,$(DIO_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN321</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN321 = dcn321_dio_link_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN321 = $(addprefix $(AMDDALPATH)/dc/dio/dcn321/,$(DIO_DCN321))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN321)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN401</div><div class='add'>+###############################################################################</div><div class='add'>+DIO_DCN401 = dcn401_dio_link_encoder.o dcn401_dio_stream_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/dio/dcn401/,$(DIO_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN401)</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c<br/>index 377f1ba1a81b..1c1228116487 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c</a></div><div class='hunk'>@@ -812,7 +812,7 @@ bool dcn10_link_encoder_validate_output_with_stream(</div><div class='ctx'> 					enc10, &amp;stream-&gt;timing);</div><div class='ctx'> 	break;</div><div class='ctx'> 	case SIGNAL_TYPE_EDP:</div><div class='del'>-		is_valid = (stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;</div><div class='add'>+		is_valid = stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_RGB;</div><div class='ctx'> 	break;</div><div class='ctx'> 	case SIGNAL_TYPE_VIRTUAL:</div><div class='ctx'> 		is_valid = true;</div><div class='hunk'>@@ -1104,6 +1104,7 @@ void dcn10_link_encoder_dp_set_lane_settings(</div><div class='ctx'> 	union dpcd_training_lane_set training_lane_set = { { 0 } };</div><div class='ctx'> 	int32_t lane = 0;</div><div class='ctx'> 	struct bp_transmitter_control cntl = { 0 };</div><div class='add'>+	enum bp_result result;</div><div class='ctx'> </div><div class='ctx'> 	if (!link_settings) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -1138,7 +1139,12 @@ void dcn10_link_encoder_dp_set_lane_settings(</div><div class='ctx'> 		cntl.lane_settings = training_lane_set.raw;</div><div class='ctx'> </div><div class='ctx'> 		/* call VBIOS table to set voltage swing and pre-emphasis */</div><div class='del'>-		link_transmitter_control(enc10, &amp;cntl);</div><div class='add'>+		result = link_transmitter_control(enc10, &amp;cntl);</div><div class='add'>+</div><div class='add'>+		if (result != BP_RESULT_OK) {</div><div class='add'>+			DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", __func__);</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1439,7 +1445,6 @@ enum signal_type dcn10_get_dig_mode(</div><div class='ctx'> 	default:</div><div class='ctx'> 		return SIGNAL_TYPE_NONE;</div><div class='ctx'> 	}</div><div class='del'>-	return SIGNAL_TYPE_NONE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h<br/>index d980e6bd6c66..b7a89c39f445 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h</a></div><div class='hunk'>@@ -167,7 +167,6 @@ struct dcn10_link_enc_registers {</div><div class='ctx'> 	uint32_t DIO_LINKD_CNTL;</div><div class='ctx'> 	uint32_t DIO_LINKE_CNTL;</div><div class='ctx'> 	uint32_t DIO_LINKF_CNTL;</div><div class='del'>-	uint32_t DIG_FIFO_CTRL0;</div><div class='ctx'> 	uint32_t DIO_CLK_CNTL;</div><div class='ctx'> 	uint32_t DIG_BE_CLK_CNTL;</div><div class='ctx'> };</div><div class='hunk'>@@ -475,9 +474,6 @@ struct dcn10_link_enc_registers {</div><div class='ctx'> 	type HPO_DP_ENC_SEL;\</div><div class='ctx'> 	type HPO_HDMI_ENC_SEL</div><div class='ctx'> </div><div class='del'>-#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \</div><div class='del'>-	type DIG_FIFO_OUTPUT_PIXEL_MODE</div><div class='del'>-</div><div class='ctx'> #define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \</div><div class='ctx'> 	type DIG_BE_ENABLE;\</div><div class='ctx'> 	type DIG_RB_SWITCH_EN;\</div><div class='hunk'>@@ -512,7 +508,6 @@ struct dcn10_link_enc_shift {</div><div class='ctx'> 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> 	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);</div><div class='del'>-	DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> 	DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -521,7 +516,6 @@ struct dcn10_link_enc_mask {</div><div class='ctx'> 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> 	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);</div><div class='del'>-	DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> 	DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c<br/>index f496e952ceec..d928b4dcf6b8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "dcn10_stream_encoder.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "hw_shared.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "dcn30/dcn30_afmt.h"</div><div class='ctx'> </div><div class='hunk'>@@ -255,7 +255,6 @@ void enc1_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 	uint32_t misc1 = 0;</div><div class='ctx'> 	uint32_t h_blank;</div><div class='ctx'> 	uint32_t h_back_porch;</div><div class='del'>-	uint8_t synchronous_clock = 0; /* asynchronous mode */</div><div class='ctx'> 	uint8_t colorimetry_bpc;</div><div class='ctx'> 	uint8_t dp_pixel_encoding = 0;</div><div class='ctx'> 	uint8_t dp_component_depth = 0;</div><div class='hunk'>@@ -362,7 +361,6 @@ void enc1_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	misc0 = misc0 | synchronous_clock;</div><div class='ctx'> 	misc0 = colorimetry_bpc &lt;&lt; 5;</div><div class='ctx'> </div><div class='ctx'> 	switch (output_color_space) {</div><div class='hunk'>@@ -393,7 +391,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 		break;</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_FULLRANGE:</div><div class='del'>-	case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='ctx'> 	case COLOR_SPACE_XR_RGB:</div><div class='ctx'> 	case COLOR_SPACE_MSREF_SCRGB:</div><div class='ctx'> 	case COLOR_SPACE_ADOBERGB:</div><div class='hunk'>@@ -406,6 +404,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(</div><div class='ctx'> 	case COLOR_SPACE_CUSTOMPOINTS:</div><div class='ctx'> 	case COLOR_SPACE_UNKNOWN:</div><div class='ctx'> 	case COLOR_SPACE_YCBCR709_BLACK:</div><div class='add'>+	default:</div><div class='ctx'> 		/* do nothing */</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h<br/>index c429590f1298..54a6a4ebd636 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h</a></div><div class='hunk'>@@ -127,7 +127,6 @@ struct dcn10_stream_enc_registers {</div><div class='ctx'> 	uint32_t AFMT_60958_1;</div><div class='ctx'> 	uint32_t AFMT_60958_2;</div><div class='ctx'> 	uint32_t DIG_FE_CNTL;</div><div class='del'>-	uint32_t DIG_FE_CNTL2;</div><div class='ctx'> 	uint32_t DIG_FIFO_STATUS;</div><div class='ctx'> 	uint32_t DP_MSE_RATE_CNTL;</div><div class='ctx'> 	uint32_t DP_MSE_RATE_UPDATE;</div><div class='hunk'>@@ -570,7 +569,7 @@ struct dcn10_stream_enc_registers {</div><div class='ctx'> 	type DP_SEC_GSP11_ENABLE;\</div><div class='ctx'> 	type DP_SEC_GSP11_LINE_NUM</div><div class='ctx'> </div><div class='del'>-#define SE_REG_FIELD_LIST_DCN3_2(type) \</div><div class='add'>+#define SE_REG_FIELD_LIST_DCN3_1_COMMON(type) \</div><div class='ctx'> 	type DIG_FIFO_OUTPUT_PIXEL_MODE;\</div><div class='ctx'> 	type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\</div><div class='ctx'> 	type DIG_SYMCLK_FE_ON;\</div><div class='hunk'>@@ -594,13 +593,19 @@ struct dcn10_stream_enc_registers {</div><div class='ctx'> 	type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\</div><div class='ctx'> 	type DIG_STREAM_LINK_TARGET</div><div class='ctx'> </div><div class='add'>+#define SE_REG_FIELD_LIST_DCN4_01_COMMON(type) \</div><div class='add'>+	type COMPRESSED_PIXEL_FORMAT;\</div><div class='add'>+	type DP_VID_N_INTERVAL;\</div><div class='add'>+	type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;\</div><div class='add'>+	type DP_STEER_FIFO_ENABLE</div><div class='ctx'> struct dcn10_stream_encoder_shift {</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN1_0(uint8_t);</div><div class='ctx'> 	uint8_t HDMI_ACP_SEND;</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN2_0(uint8_t);</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN3_0(uint8_t);</div><div class='del'>-	SE_REG_FIELD_LIST_DCN3_2(uint8_t);</div><div class='add'>+	SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);</div><div class='add'>+	SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn10_stream_encoder_mask {</div><div class='hunk'>@@ -608,8 +613,9 @@ struct dcn10_stream_encoder_mask {</div><div class='ctx'> 	uint32_t HDMI_ACP_SEND;</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN2_0(uint32_t);</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN3_0(uint32_t);</div><div class='del'>-	SE_REG_FIELD_LIST_DCN3_2(uint32_t);</div><div class='add'>+	SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);</div><div class='ctx'> 	SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);</div><div class='add'>+	SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn10_stream_encoder {</div><div class='hunk'>@@ -667,9 +673,6 @@ void enc1_stream_encoder_send_immediate_sdp_message(</div><div class='ctx'> void enc1_stream_encoder_stop_dp_info_packets(</div><div class='ctx'> 	struct stream_encoder *enc);</div><div class='ctx'> </div><div class='del'>-void enc1_stream_encoder_reset_fifo(</div><div class='del'>-	struct stream_encoder *enc);</div><div class='del'>-</div><div class='ctx'> void enc1_stream_encoder_dp_blank(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	struct stream_encoder *enc);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c<br/>index 51a57dae1811..51a57dae1811 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h<br/>index b2b266953d18..762c579fcb44 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h</a></div><div class='hunk'>@@ -147,7 +147,8 @@</div><div class='ctx'> 	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\</div><div class='ctx'> 	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\</div><div class='ctx'> 	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\</div><div class='del'>-	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh)</div><div class='add'>+	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\</div><div class='add'>+	LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh)</div><div class='ctx'> </div><div class='ctx'> #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\</div><div class='ctx'> 	DPCS_MASK_SH_LIST(mask_sh),\</div><div class='hunk'>@@ -231,6 +232,8 @@</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \</div><div class='ctx'> 	SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \</div><div class='ctx'> 	SRI(DPCSTX_TX_CNTL, DPCSTX, id), \</div><div class='add'>+	SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \</div><div class='add'>+	SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \</div><div class='ctx'> 	SR(RDPCSTX0_RDPCSTX_SCRATCH)</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -279,7 +282,6 @@ struct mpll_cfg {</div><div class='ctx'> 	uint32_t tx_peaking_lvl;</div><div class='ctx'> 	uint32_t ctr_reqs_pll;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dpcssys_phy_seq_cfg {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c<br/>index 0b47aeb60e79..bec0b4aaeb2b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c</a></div><div class='hunk'>@@ -29,7 +29,7 @@</div><div class='ctx'> #include "dcn20_stream_encoder.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "hw_shared.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h<br/>index baa1e539f341..baa1e539f341 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c<br/>index 1fb8fd7afc95..b8e31b5ea114 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c</a></div><div class='hunk'>@@ -30,8 +30,6 @@</div><div class='ctx'> #include "dcn30_dio_link_encoder.h"</div><div class='ctx'> #include "stream_encoder.h"</div><div class='ctx'> #include "dc_bios_types.h"</div><div class='del'>-/* #include "dcn3ag/dcn3ag_phy_fw.h" */</div><div class='del'>-</div><div class='ctx'> #include "gpio_service_interface.h"</div><div class='ctx'> </div><div class='ctx'> #define CTX \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h<br/>index f2d90f2b8bf1..5b6177c2ae98 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h</a></div><div class='hunk'>@@ -55,7 +55,8 @@</div><div class='ctx'> 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)</div><div class='ctx'> </div><div class='ctx'> #define LINK_ENCODER_MASK_SH_LIST_DCN30(mask_sh) \</div><div class='del'>-	LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)</div><div class='add'>+	LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\</div><div class='add'>+	LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)</div><div class='ctx'> </div><div class='ctx'> #define DPCS_DCN3_MASK_SH_LIST(mask_sh)\</div><div class='ctx'> 	DPCS_DCN2_MASK_SH_LIST(mask_sh),\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c<br/>index 005dbe099a7a..e93be7b6d9b0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c</a></div><div class='hunk'>@@ -29,9 +29,6 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "hw_shared.h"</div><div class='ctx'> #include "dc.h"</div><div class='del'>-#include "core_types.h"</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 		enc1-&gt;base.ctx-&gt;logger</div><div class='hunk'>@@ -50,7 +47,7 @@</div><div class='ctx'> 	enc1-&gt;base.ctx</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static void enc3_update_hdmi_info_packet(</div><div class='add'>+void enc3_update_hdmi_info_packet(</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1,</div><div class='ctx'> 	uint32_t packet_index,</div><div class='ctx'> 	const struct dc_info_packet *info_packet)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h<br/>index 06310973ded2..830ce7e47035 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h</a></div><div class='hunk'>@@ -322,6 +322,10 @@ void enc3_dp_set_dsc_pps_info_packet(</div><div class='ctx'> 	struct stream_encoder *enc,</div><div class='ctx'> 	bool enable,</div><div class='ctx'> 	uint8_t *dsc_packed_pps,</div><div class='del'>-    bool immediate_update);</div><div class='add'>+	bool immediate_update);</div><div class='add'>+void enc3_update_hdmi_info_packet(</div><div class='add'>+	struct dcn10_stream_encoder *enc1,</div><div class='add'>+	uint32_t packet_index,</div><div class='add'>+	const struct dc_info_packet *info_packet);</div><div class='ctx'> </div><div class='ctx'> #endif /* __DC_DIO_STREAM_ENCODER_DCN30_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c<br/>index 1b39a6e8a1ac..1b39a6e8a1ac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h<br/>index 49f8d91d4951..49f8d91d4951 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c<br/>index 26be5fee7411..84cc2ddc52fe 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c</a></div><div class='hunk'>@@ -37,7 +37,7 @@</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "dal_asic_id.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #define CTX \</div><div class='ctx'> 	enc10-&gt;base.ctx</div><div class='hunk'>@@ -205,7 +205,7 @@ void dcn31_link_encoder_set_dio_phy_mux(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void enc31_hw_init(struct link_encoder *enc)</div><div class='add'>+void enc31_hw_init(struct link_encoder *enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='ctx'> </div><div class='hunk'>@@ -653,8 +653,9 @@ void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_lin</div><div class='ctx'> 		if (!query_dp_alt_from_dmub(enc, &amp;cmd))</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='del'>-		if (cmd.query_dp_alt.data.is_usb &amp;&amp;</div><div class='del'>-		    cmd.query_dp_alt.data.is_dp4 == 0)</div><div class='add'>+		if (cmd.query_dp_alt.data.is_dp_alt_disable == 0 &amp;&amp;</div><div class='add'>+				cmd.query_dp_alt.data.is_usb &amp;&amp;</div><div class='add'>+				cmd.query_dp_alt.data.is_dp4 == 0)</div><div class='ctx'> 			link_settings-&gt;lane_count = MIN(LANE_COUNT_TWO, link_settings-&gt;lane_count);</div><div class='ctx'> </div><div class='ctx'> 		return;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h<br/>index 221671563a0b..ee78ba80797c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.h</a></div><div class='hunk'>@@ -89,6 +89,7 @@</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \</div><div class='add'>+	SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \</div><div class='ctx'> 	SR(RDPCSTX0_RDPCSTX_SCRATCH), \</div><div class='ctx'> 	SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\</div><div class='ctx'> 	SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)</div><div class='hunk'>@@ -222,6 +223,7 @@</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \</div><div class='ctx'> 	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \</div><div class='add'>+	SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \</div><div class='ctx'> 	SR(RDPCSTX0_RDPCSTX_SCRATCH), \</div><div class='ctx'> 	SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\</div><div class='ctx'> 	SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)</div><div class='hunk'>@@ -283,4 +285,6 @@ bool dcn31_link_encoder_is_in_alt_mode(</div><div class='ctx'> void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,</div><div class='ctx'> 	struct dc_link_settings *link_settings);</div><div class='ctx'> </div><div class='add'>+void enc31_hw_init(struct link_encoder *enc);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_LINK_ENCODER__DCN31_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c<br/>index 5b343f745cf3..3e85e9c3d2cb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c</a></div><div class='hunk'>@@ -30,7 +30,7 @@</div><div class='ctx'> #include "dcn314_dio_stream_encoder.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "hw_shared.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='hunk'>@@ -83,6 +83,15 @@ void enc314_disable_fifo(struct stream_encoder *enc)</div><div class='ctx'> 	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool enc314_is_fifo_enabled(struct stream_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+	uint32_t reset_val;</div><div class='add'>+</div><div class='add'>+	REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &amp;reset_val);</div><div class='add'>+	return (reset_val != 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void enc314_dp_set_odm_combine(</div><div class='ctx'> 	struct stream_encoder *enc,</div><div class='ctx'> 	bool odm_combine)</div><div class='hunk'>@@ -468,6 +477,7 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = {</div><div class='ctx'> </div><div class='ctx'> 	.enable_fifo = enc314_enable_fifo,</div><div class='ctx'> 	.disable_fifo = enc314_disable_fifo,</div><div class='add'>+	.is_fifo_enabled = enc314_is_fifo_enabled,</div><div class='ctx'> 	.set_input_mode = enc314_set_dig_input_mode,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h<br/>index 86548be591be..86548be591be 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c<br/>index e224a028d68a..06907e8a4eda 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c</a></div><div class='hunk'>@@ -251,11 +251,6 @@ void dcn32_link_encoder_construct(</div><div class='ctx'> 	enc10-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='ctx'> </div><div class='ctx'> 	enc10-&gt;base.features = *enc_features;</div><div class='del'>-	if (enc10-&gt;base.connector.id == CONNECTOR_ID_USBC)</div><div class='del'>-		enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='del'>-</div><div class='del'>-	if (enc10-&gt;base.connector.id == CONNECTOR_ID_USBC)</div><div class='del'>-		enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='ctx'> </div><div class='ctx'> 	enc10-&gt;base.transmitter = init_data-&gt;transmitter;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.h<br/>index 2d5f25290ed1..35d23d9db45e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.h</a></div><div class='hunk'>@@ -26,15 +26,7 @@</div><div class='ctx'> #ifndef __DC_LINK_ENCODER__DCN32_H__</div><div class='ctx'> #define __DC_LINK_ENCODER__DCN32_H__</div><div class='ctx'> </div><div class='del'>-#include "dcn31/dcn31_dio_link_encoder.h"</div><div class='del'>-</div><div class='del'>-#define LE_DCN32_REG_LIST(id)\</div><div class='del'>-	LE_DCN31_REG_LIST(id),\</div><div class='del'>-	SRI(DIG_FIFO_CTRL0, DIG, id)</div><div class='del'>-</div><div class='del'>-#define LINK_ENCODER_MASK_SH_LIST_DCN32(mask_sh) \</div><div class='del'>-	LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh),\</div><div class='del'>-	LE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)</div><div class='add'>+#include "dcn30/dcn30_dio_link_encoder.h"</div><div class='ctx'> </div><div class='ctx'> void dcn32_link_encoder_construct(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c<br/>index 2fef1419ae91..3523d1cdc1a3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c</a></div><div class='hunk'>@@ -29,7 +29,7 @@</div><div class='ctx'> #include "dcn32_dio_stream_encoder.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "hw_shared.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='hunk'>@@ -52,11 +52,11 @@</div><div class='ctx'> </div><div class='ctx'> static void enc32_dp_set_odm_combine(</div><div class='ctx'> 	struct stream_encoder *enc,</div><div class='del'>-	bool odm_combine)</div><div class='add'>+	bool two_pixel_per_cyle)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine ? 1 : 0);</div><div class='add'>+	REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, two_pixel_per_cyle ? 1 : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* setup stream encoder in dvi mode */</div><div class='hunk'>@@ -241,46 +241,12 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)</div><div class='ctx'> 	return two_pix;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	/* math borrowed from function of same name in inc/resource</div><div class='del'>-	 * checks if h_timing is divisible by 2</div><div class='del'>-	 */</div><div class='del'>-</div><div class='del'>-	bool divisible = false;</div><div class='del'>-	uint16_t h_blank_start = 0;</div><div class='del'>-	uint16_t h_blank_end = 0;</div><div class='del'>-</div><div class='del'>-	if (timing) {</div><div class='del'>-		h_blank_start = timing-&gt;h_total - timing-&gt;h_front_porch;</div><div class='del'>-		h_blank_end = h_blank_start - timing-&gt;h_addressable;</div><div class='del'>-</div><div class='del'>-		/* HTOTAL, Hblank start/end, and Hsync start/end all must be</div><div class='del'>-		 * divisible by 2 in order for the horizontal timing params</div><div class='del'>-		 * to be considered divisible by 2. Hsync start is always 0.</div><div class='del'>-		 */</div><div class='del'>-		divisible = (timing-&gt;h_total % 2 == 0) &amp;&amp;</div><div class='del'>-				(h_blank_start % 2 == 0) &amp;&amp;</div><div class='del'>-				(h_blank_end % 2 == 0) &amp;&amp;</div><div class='del'>-				(timing-&gt;h_sync_width % 2 == 0);</div><div class='del'>-	}</div><div class='del'>-	return divisible;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	/* should be functionally the same as dcn32_is_dp_dig_pixel_rate_div_policy for DP encoders*/</div><div class='del'>-	return is_h_timing_divisible_by_2(timing) &amp;&amp;</div><div class='del'>-		dc-&gt;debug.enable_dp_dig_pixel_rate_div_policy;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void enc32_stream_encoder_dp_unblank(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	struct stream_encoder *enc,</div><div class='ctx'> 	const struct encoder_unblank_param *param)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='del'>-	struct dc *dc = enc-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	if (param-&gt;link_settings.link_rate != LINK_RATE_UNKNOWN) {</div><div class='ctx'> 		uint32_t n_vid = 0x8000;</div><div class='hunk'>@@ -291,7 +257,7 @@ void enc32_stream_encoder_dp_unblank(</div><div class='ctx'> </div><div class='ctx'> 		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */</div><div class='ctx'> 		if (is_two_pixels_per_containter(&amp;param-&gt;timing) || param-&gt;opp_cnt &gt; 1</div><div class='del'>-			|| is_dp_dig_pixel_rate_div_policy(dc, &amp;param-&gt;timing)) {</div><div class='add'>+			|| param-&gt;pix_per_cycle &gt; 1) {</div><div class='ctx'> 			/*this logic should be the same in get_pixel_clock_parameters() */</div><div class='ctx'> 			n_multiply = 1;</div><div class='ctx'> 			pix_per_cycle = 1;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h<br/>index 1be5410cce97..ca53d39561d2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h</a></div><div class='hunk'>@@ -177,11 +177,12 @@</div><div class='ctx'> 	SE_SF(DIG0_DIG_FE_CNTL, DIG_SYMCLK_FE_ON, mask_sh),\</div><div class='ctx'> 	SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\</div><div class='ctx'> 	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh),\</div><div class='ctx'> 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\</div><div class='ctx'> 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\</div><div class='ctx'> 	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\</div><div class='del'>-	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\</div><div class='del'>-	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh)</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> void dcn32_dio_stream_encoder_construct(</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c<br/>index 13be5f06d987..2ed382a8e79c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c</a></div><div class='hunk'>@@ -23,7 +23,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> </div><div class='ctx'> #include "core_types.h"</div><div class='hunk'>@@ -127,11 +126,6 @@ void dcn321_link_encoder_construct(</div><div class='ctx'> 	 * while doing the DP sink detect</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-/*	if (dal_adapter_service_is_feature_supported(as,</div><div class='del'>-		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))</div><div class='del'>-		enc10-&gt;base.features.flags.bits.</div><div class='del'>-			DP_SINK_DETECT_POLL_DATA_PIN = true;*/</div><div class='del'>-</div><div class='ctx'> 	enc10-&gt;base.output_signals =</div><div class='ctx'> 		SIGNAL_TYPE_DVI_SINGLE_LINK |</div><div class='ctx'> 		SIGNAL_TYPE_DVI_DUAL_LINK |</div><div class='hunk'>@@ -191,7 +185,6 @@ void dcn321_link_encoder_construct(</div><div class='ctx'> 				__func__,</div><div class='ctx'> 				result);</div><div class='ctx'> 	}</div><div class='del'>-	if (enc10-&gt;base.ctx-&gt;dc-&gt;debug.hdmi20_disable) {</div><div class='add'>+	if (enc10-&gt;base.ctx-&gt;dc-&gt;debug.hdmi20_disable)</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = 0;</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.h<br/>index 2205f39b0a24..2205f39b0a24 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn321/dcn321_dio_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c<br/>new file mode 100644<br/>index 000000000000..9972911330b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c</a></div><div class='hunk'>@@ -0,0 +1,391 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "link_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_dio_link_encoder.h"</div><div class='add'>+#include "dcn35_dio_link_encoder.h"</div><div class='add'>+#include "dc_dmub_srv.h"</div><div class='add'>+#define CTX \</div><div class='add'>+	enc10-&gt;base.ctx</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	enc10-&gt;base.ctx-&gt;logger</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	(enc10-&gt;link_regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	enc10-&gt;link_shift-&gt;field_name, enc10-&gt;link_mask-&gt;field_name</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Trigger Source Select</div><div class='add'>+ * ASIC-dependent, actual values for register programming</div><div class='add'>+ */</div><div class='add'>+#define DCN35_DIG_FE_SOURCE_SELECT_INVALID 0x0</div><div class='add'>+#define DCN35_DIG_FE_SOURCE_SELECT_DIGA 0x1</div><div class='add'>+#define DCN35_DIG_FE_SOURCE_SELECT_DIGB 0x2</div><div class='add'>+#define DCN35_DIG_FE_SOURCE_SELECT_DIGC 0x4</div><div class='add'>+#define DCN35_DIG_FE_SOURCE_SELECT_DIGD 0x08</div><div class='add'>+#define DCN35_DIG_FE_SOURCE_SELECT_DIGE 0x10</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dcn35_is_dig_enabled(struct link_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	uint32_t enabled;</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &amp;enabled);</div><div class='add'>+	return (enabled == 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum signal_type dcn35_get_dig_mode(</div><div class='add'>+	struct link_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &amp;value);</div><div class='add'>+	switch (value) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SIGNAL_TYPE_DISPLAY_PORT;</div><div class='add'>+	case 2:</div><div class='add'>+		return SIGNAL_TYPE_DVI_SINGLE_LINK;</div><div class='add'>+	case 3:</div><div class='add'>+		return SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='add'>+	case 5:</div><div class='add'>+		return SIGNAL_TYPE_DISPLAY_PORT_MST;</div><div class='add'>+	default:</div><div class='add'>+		return SIGNAL_TYPE_NONE;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_setup(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	switch (signal) {</div><div class='add'>+	case SIGNAL_TYPE_EDP:</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='add'>+		/* DP SST */</div><div class='add'>+		REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0);</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+	case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='add'>+		/* TMDS-DVI */</div><div class='add'>+		REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2);</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='add'>+		/* TMDS-HDMI */</div><div class='add'>+		REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3);</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT_MST:</div><div class='add'>+		/* DP MST */</div><div class='add'>+		REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+		/* invalid mode ! */</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_init(struct link_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	enc31_hw_init(enc);</div><div class='add'>+	dcn35_link_encoder_set_fgcg(enc, enc-&gt;ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.dio);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct link_encoder_funcs dcn35_link_enc_funcs = {</div><div class='add'>+	.read_state = link_enc2_read_state,</div><div class='add'>+	.validate_output_with_stream =</div><div class='add'>+			dcn30_link_encoder_validate_output_with_stream,</div><div class='add'>+	.hw_init = dcn35_link_encoder_init,</div><div class='add'>+	.setup = dcn35_link_encoder_setup,</div><div class='add'>+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,</div><div class='add'>+	.enable_dp_output = dcn35_link_encoder_enable_dp_output,</div><div class='add'>+	.enable_dp_mst_output = dcn35_link_encoder_enable_dp_mst_output,</div><div class='add'>+	.disable_output = dcn35_link_encoder_disable_output,</div><div class='add'>+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,</div><div class='add'>+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,</div><div class='add'>+	.update_mst_stream_allocation_table =</div><div class='add'>+		dcn10_link_encoder_update_mst_stream_allocation_table,</div><div class='add'>+	.psr_program_dp_dphy_fast_training =</div><div class='add'>+			dcn10_psr_program_dp_dphy_fast_training,</div><div class='add'>+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,</div><div class='add'>+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,</div><div class='add'>+	.enable_hpd = dcn10_link_encoder_enable_hpd,</div><div class='add'>+	.disable_hpd = dcn10_link_encoder_disable_hpd,</div><div class='add'>+	.is_dig_enabled = dcn35_is_dig_enabled,</div><div class='add'>+	.destroy = dcn10_link_encoder_destroy,</div><div class='add'>+	.fec_set_enable = enc2_fec_set_enable,</div><div class='add'>+	.fec_set_ready = enc2_fec_set_ready,</div><div class='add'>+	.fec_is_active = enc2_fec_is_active,</div><div class='add'>+	.get_dig_frontend = dcn10_get_dig_frontend,</div><div class='add'>+	.get_dig_mode = dcn35_get_dig_mode,</div><div class='add'>+	.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,</div><div class='add'>+	.get_max_link_cap = dcn31_link_encoder_get_max_link_cap,</div><div class='add'>+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,</div><div class='add'>+	.enable_dpia_output = dcn35_link_encoder_enable_dpia_output,</div><div class='add'>+	.disable_dpia_output = dcn35_link_encoder_disable_dpia_output,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_construct(</div><div class='add'>+	struct dcn20_link_encoder *enc20,</div><div class='add'>+	const struct encoder_init_data *init_data,</div><div class='add'>+	const struct encoder_feature_support *enc_features,</div><div class='add'>+	const struct dcn10_link_enc_registers *link_regs,</div><div class='add'>+	const struct dcn10_link_enc_aux_registers *aux_regs,</div><div class='add'>+	const struct dcn10_link_enc_hpd_registers *hpd_regs,</div><div class='add'>+	const struct dcn10_link_enc_shift *link_shift,</div><div class='add'>+	const struct dcn10_link_enc_mask *link_mask)</div><div class='add'>+{</div><div class='add'>+	struct bp_connector_speed_cap_info bp_cap_info = {0};</div><div class='add'>+	const struct dc_vbios_funcs *bp_funcs = init_data-&gt;ctx-&gt;dc_bios-&gt;funcs;</div><div class='add'>+	enum bp_result result = BP_RESULT_OK;</div><div class='add'>+	struct dcn10_link_encoder *enc10 = &amp;enc20-&gt;enc10;</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.funcs = &amp;dcn35_link_enc_funcs;</div><div class='add'>+	enc10-&gt;base.ctx = init_data-&gt;ctx;</div><div class='add'>+	enc10-&gt;base.id = init_data-&gt;encoder;</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.hpd_source = init_data-&gt;hpd_source;</div><div class='add'>+	enc10-&gt;base.connector = init_data-&gt;connector;</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.features = *enc_features;</div><div class='add'>+</div><div class='add'>+	if (enc10-&gt;base.connector.id == CONNECTOR_ID_USBC)</div><div class='add'>+		enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.transmitter = init_data-&gt;transmitter;</div><div class='add'>+</div><div class='add'>+	/* set the flag to indicate whether driver poll the I2C data pin</div><div class='add'>+	 * while doing the DP sink detect</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+/*	if (dal_adapter_service_is_feature_supported(as,</div><div class='add'>+ *		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))</div><div class='add'>+ *		enc10-&gt;base.features.flags.bits.</div><div class='add'>+ *			DP_SINK_DETECT_POLL_DATA_PIN = true;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.output_signals =</div><div class='add'>+		SIGNAL_TYPE_DVI_SINGLE_LINK |</div><div class='add'>+		SIGNAL_TYPE_DVI_DUAL_LINK |</div><div class='add'>+		SIGNAL_TYPE_LVDS |</div><div class='add'>+		SIGNAL_TYPE_DISPLAY_PORT |</div><div class='add'>+		SIGNAL_TYPE_DISPLAY_PORT_MST |</div><div class='add'>+		SIGNAL_TYPE_EDP |</div><div class='add'>+		SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='add'>+</div><div class='add'>+	enc10-&gt;link_regs = link_regs;</div><div class='add'>+	enc10-&gt;aux_regs = aux_regs;</div><div class='add'>+	enc10-&gt;hpd_regs = hpd_regs;</div><div class='add'>+	enc10-&gt;link_shift = link_shift;</div><div class='add'>+	enc10-&gt;link_mask = link_mask;</div><div class='add'>+</div><div class='add'>+	switch (enc10-&gt;base.transmitter) {</div><div class='add'>+	case TRANSMITTER_UNIPHY_A:</div><div class='add'>+		enc10-&gt;base.preferred_engine = ENGINE_ID_DIGA;</div><div class='add'>+	break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_B:</div><div class='add'>+		enc10-&gt;base.preferred_engine = ENGINE_ID_DIGB;</div><div class='add'>+	break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_C:</div><div class='add'>+		enc10-&gt;base.preferred_engine = ENGINE_ID_DIGC;</div><div class='add'>+	break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_D:</div><div class='add'>+		enc10-&gt;base.preferred_engine = ENGINE_ID_DIGD;</div><div class='add'>+	break;</div><div class='add'>+	case TRANSMITTER_UNIPHY_E:</div><div class='add'>+		enc10-&gt;base.preferred_engine = ENGINE_ID_DIGE;</div><div class='add'>+	break;</div><div class='add'>+	default:</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+		enc10-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = 1;</div><div class='add'>+</div><div class='add'>+	if (bp_funcs-&gt;get_connector_speed_cap_info)</div><div class='add'>+		result = bp_funcs-&gt;get_connector_speed_cap_info(enc10-&gt;base.ctx-&gt;dc_bios,</div><div class='add'>+						enc10-&gt;base.connector, &amp;bp_cap_info);</div><div class='add'>+</div><div class='add'>+	/* Override features with DCE-specific values */</div><div class='add'>+	if (result == BP_RESULT_OK) {</div><div class='add'>+		enc10-&gt;base.features.flags.bits.IS_HBR2_CAPABLE =</div><div class='add'>+				bp_cap_info.DP_HBR2_EN;</div><div class='add'>+		enc10-&gt;base.features.flags.bits.IS_HBR3_CAPABLE =</div><div class='add'>+				bp_cap_info.DP_HBR3_EN;</div><div class='add'>+		enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;</div><div class='add'>+		enc10-&gt;base.features.flags.bits.IS_DP2_CAPABLE = 1;</div><div class='add'>+		enc10-&gt;base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;</div><div class='add'>+		enc10-&gt;base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;</div><div class='add'>+		enc10-&gt;base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",</div><div class='add'>+				__func__,</div><div class='add'>+				result);</div><div class='add'>+	}</div><div class='add'>+	if (enc10-&gt;base.ctx-&gt;dc-&gt;debug.hdmi20_disable)</div><div class='add'>+		enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = 0;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* DPIA equivalent of link_transmitter_control. */</div><div class='add'>+static bool link_dpia_control(struct dc_context *dc_ctx,</div><div class='add'>+	struct dmub_cmd_dig_dpia_control_data *dpia_control)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	cmd.dig1_dpia_control.header.type = DMUB_CMD__DPIA;</div><div class='add'>+	cmd.dig1_dpia_control.header.sub_type =</div><div class='add'>+			DMUB_CMD__DPIA_DIG1_DPIA_CONTROL;</div><div class='add'>+	cmd.dig1_dpia_control.header.payload_bytes =</div><div class='add'>+		sizeof(cmd.dig1_dpia_control) -</div><div class='add'>+		sizeof(cmd.dig1_dpia_control.header);</div><div class='add'>+</div><div class='add'>+	cmd.dig1_dpia_control.dpia_control = *dpia_control;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void link_encoder_disable(struct dcn10_link_encoder *enc10)</div><div class='add'>+{</div><div class='add'>+	/* reset training complete */</div><div class='add'>+	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_enable_dp_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	enum clock_source_id clock_source)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	if (!enc-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		dcn31_link_encoder_enable_dp_output(enc, link_settings, clock_source);</div><div class='add'>+	else {</div><div class='add'>+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc-&gt;preferred_engine);</div><div class='add'>+		dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_enable_dp_mst_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	enum clock_source_id clock_source)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	if (!enc-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		dcn31_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);</div><div class='add'>+	else {</div><div class='add'>+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc-&gt;preferred_engine);</div><div class='add'>+		dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_disable_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	if (!enc-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		dcn31_link_encoder_disable_output(enc, signal);</div><div class='add'>+	else {</div><div class='add'>+		DC_LOG_DEBUG("%s: enc_id(%d)\n", __func__, enc-&gt;preferred_engine);</div><div class='add'>+		dcn10_link_encoder_disable_output(enc, signal);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_enable_dpia_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	uint8_t dpia_id,</div><div class='add'>+	uint8_t digmode,</div><div class='add'>+	uint8_t fec_rdy)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+	struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };</div><div class='add'>+</div><div class='add'>+	enc1_configure_encoder(enc10, link_settings);</div><div class='add'>+</div><div class='add'>+	dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE;</div><div class='add'>+	dpia_control.enc_id = enc-&gt;preferred_engine;</div><div class='add'>+	dpia_control.mode_laneset.digmode = digmode;</div><div class='add'>+	dpia_control.lanenum = (uint8_t)link_settings-&gt;lane_count;</div><div class='add'>+	dpia_control.symclk_10khz = link_settings-&gt;link_rate *</div><div class='add'>+			LINK_RATE_REF_FREQ_IN_KHZ / 10;</div><div class='add'>+	/* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin unused by DPIA. */</div><div class='add'>+	dpia_control.hpdsel = 6;</div><div class='add'>+	dpia_control.dpia_id = dpia_id;</div><div class='add'>+	dpia_control.fec_rdy = fec_rdy;</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);</div><div class='add'>+	link_dpia_control(enc-&gt;ctx, &amp;dpia_control);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_link_encoder_disable_dpia_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	uint8_t dpia_id,</div><div class='add'>+	uint8_t digmode)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+	struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 };</div><div class='add'>+</div><div class='add'>+	if (enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp; !enc-&gt;funcs-&gt;is_dig_enabled(enc))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE;</div><div class='add'>+	dpia_control.enc_id = enc-&gt;preferred_engine;</div><div class='add'>+	dpia_control.mode_laneset.digmode = digmode;</div><div class='add'>+	dpia_control.dpia_id = dpia_id;</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("%s: DPIA(%d) - enc_id(%d)\n", __func__, dpia_control.dpia_id, dpia_control.enc_id);</div><div class='add'>+	link_dpia_control(enc-&gt;ctx, &amp;dpia_control);</div><div class='add'>+</div><div class='add'>+	link_encoder_disable(enc10);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h<br/>index e1e560732a9d..5712e6553fab 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.h</a></div><div class='hunk'>@@ -37,7 +37,9 @@</div><div class='ctx'> 	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\</div><div class='ctx'> 	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\</div><div class='ctx'> 	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, HDCP_SOFT_RESET, mask_sh),\</div><div class='ctx'> 	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_HDCP_CLOCK_ON, mask_sh),\</div><div class='ctx'> 	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\</div><div class='ctx'> 	LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\</div><div class='ctx'> 	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \</div><div class='hunk'>@@ -114,7 +116,15 @@</div><div class='ctx'> 	LE_SF(DIO_CLK_CNTL, SYMCLK_FE_G_GATE_DIS, mask_sh),\</div><div class='ctx'> 	LE_SF(DIO_CLK_CNTL, SYMCLK_R_GATE_DIS, mask_sh),\</div><div class='ctx'> 	LE_SF(DIO_CLK_CNTL, SYMCLK_G_GATE_DIS, mask_sh),\</div><div class='del'>-	LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh)</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, DISPCLK_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKA_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKB_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\</div><div class='add'>+	LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh)</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> void dcn35_link_encoder_construct(</div><div class='hunk'>@@ -134,4 +144,45 @@ bool dcn35_is_dig_enabled(struct link_encoder *enc);</div><div class='ctx'> enum signal_type dcn35_get_dig_mode(struct link_encoder *enc);</div><div class='ctx'> void dcn35_link_encoder_setup(struct link_encoder *enc, enum signal_type signal);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Enable DP transmitter and its encoder.</div><div class='add'>+ */</div><div class='add'>+void dcn35_link_encoder_enable_dp_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	enum clock_source_id clock_source);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Enable DP transmitter and its encoder in MST mode.</div><div class='add'>+ */</div><div class='add'>+void dcn35_link_encoder_enable_dp_mst_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	enum clock_source_id clock_source);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Disable transmitter and its encoder.</div><div class='add'>+ */</div><div class='add'>+void dcn35_link_encoder_disable_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	enum signal_type signal);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Enable DP transmitter and its encoder for dpia port.</div><div class='add'>+ */</div><div class='add'>+void dcn35_link_encoder_enable_dpia_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	uint8_t dpia_id,</div><div class='add'>+	uint8_t digmode,</div><div class='add'>+	uint8_t fec_rdy);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Disable transmitter and its encoder for dpia port.</div><div class='add'>+ */</div><div class='add'>+void dcn35_link_encoder_disable_dpia_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	uint8_t dpia_id,</div><div class='add'>+	uint8_t digmode);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_LINK_ENCODER__DCN35_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c<br/>index 62a8f0b56006..fd5d1dbf9dc6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c</a></div><div class='hunk'>@@ -22,7 +22,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> #include "dc_bios_types.h"</div><div class='ctx'> #include "dcn30/dcn30_dio_stream_encoder.h"</div><div class='ctx'> #include "dcn314/dcn314_dio_stream_encoder.h"</div><div class='hunk'>@@ -30,7 +29,7 @@</div><div class='ctx'> #include "dcn35_dio_stream_encoder.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "hw_shared.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='hunk'>@@ -254,6 +253,7 @@ static void enc35_stream_encoder_enable(</div><div class='ctx'> 			break;</div><div class='ctx'> 		case SIGNAL_TYPE_EDP:</div><div class='ctx'> 		case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='add'>+		case SIGNAL_TYPE_VIRTUAL:</div><div class='ctx'> 			/* DP SST */</div><div class='ctx'> 			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 0);</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -273,46 +273,12 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)</div><div class='ctx'> 	return two_pix;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	/* math borrowed from function of same name in inc/resource</div><div class='del'>-	 * checks if h_timing is divisible by 2</div><div class='del'>-	 */</div><div class='del'>-</div><div class='del'>-	bool divisible = false;</div><div class='del'>-	uint16_t h_blank_start = 0;</div><div class='del'>-	uint16_t h_blank_end = 0;</div><div class='del'>-</div><div class='del'>-	if (timing) {</div><div class='del'>-		h_blank_start = timing-&gt;h_total - timing-&gt;h_front_porch;</div><div class='del'>-		h_blank_end = h_blank_start - timing-&gt;h_addressable;</div><div class='del'>-</div><div class='del'>-		/* HTOTAL, Hblank start/end, and Hsync start/end all must be</div><div class='del'>-		 * divisible by 2 in order for the horizontal timing params</div><div class='del'>-		 * to be considered divisible by 2. Hsync start is always 0.</div><div class='del'>-		 */</div><div class='del'>-		divisible = (timing-&gt;h_total % 2 == 0) &amp;&amp;</div><div class='del'>-				(h_blank_start % 2 == 0) &amp;&amp;</div><div class='del'>-				(h_blank_end % 2 == 0) &amp;&amp;</div><div class='del'>-				(timing-&gt;h_sync_width % 2 == 0);</div><div class='del'>-	}</div><div class='del'>-	return divisible;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	/* should be functionally the same as dcn32_is_dp_dig_pixel_rate_div_policy for DP encoders*/</div><div class='del'>-	return is_h_timing_divisible_by_2(timing) &amp;&amp;</div><div class='del'>-		dc-&gt;debug.enable_dp_dig_pixel_rate_div_policy;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void enc35_stream_encoder_dp_unblank(</div><div class='ctx'> 		struct dc_link *link,</div><div class='ctx'> 		struct stream_encoder *enc,</div><div class='ctx'> 		const struct encoder_unblank_param *param)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='del'>-	struct dc *dc = enc-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	if (param-&gt;link_settings.link_rate != LINK_RATE_UNKNOWN) {</div><div class='ctx'> 		uint32_t n_vid = 0x8000;</div><div class='hunk'>@@ -323,7 +289,7 @@ static void enc35_stream_encoder_dp_unblank(</div><div class='ctx'> </div><div class='ctx'> 		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */</div><div class='ctx'> 		if (is_two_pixels_per_containter(&amp;param-&gt;timing) || param-&gt;opp_cnt &gt; 1</div><div class='del'>-			|| is_dp_dig_pixel_rate_div_policy(dc, &amp;param-&gt;timing)) {</div><div class='add'>+			|| param-&gt;pix_per_cycle &gt; 1) {</div><div class='ctx'> 			/*this logic should be the same in get_pixel_clock_parameters() */</div><div class='ctx'> 			n_multiply = 1;</div><div class='ctx'> 			pix_per_cycle = 1;</div><div class='hunk'>@@ -425,7 +391,15 @@ static void enc35_reset_fifo(struct stream_encoder *enc, bool reset)</div><div class='ctx'> 		udelay(10);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void enc35_disable_fifo(struct stream_encoder *enc)</div><div class='add'>+static bool enc35_is_fifo_enabled(struct stream_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+	uint32_t reset_val;</div><div class='add'>+</div><div class='add'>+	REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &amp;reset_val);</div><div class='add'>+	return reset_val != 0;</div><div class='add'>+}</div><div class='add'>+void enc35_disable_fifo(struct stream_encoder *enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='ctx'> </div><div class='hunk'>@@ -434,7 +408,7 @@ static void enc35_disable_fifo(struct stream_encoder *enc)</div><div class='ctx'> 	REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void enc35_enable_fifo(struct stream_encoder *enc)</div><div class='add'>+void enc35_enable_fifo(struct stream_encoder *enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='ctx'> </div><div class='hunk'>@@ -448,6 +422,24 @@ static void enc35_enable_fifo(struct stream_encoder *enc)</div><div class='ctx'> 	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t enc35_get_pixels_per_cycle(struct stream_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+	uint32_t value;</div><div class='add'>+</div><div class='add'>+	REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, &amp;value);</div><div class='add'>+</div><div class='add'>+	switch (value) {</div><div class='add'>+	case 0:</div><div class='add'>+		return 1;</div><div class='add'>+	case 1:</div><div class='add'>+		return 2;</div><div class='add'>+	default:</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+		return 1;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct stream_encoder_funcs dcn35_str_enc_funcs = {</div><div class='ctx'> 	.dp_set_odm_combine =</div><div class='ctx'> 		enc314_dp_set_odm_combine,</div><div class='hunk'>@@ -493,12 +485,14 @@ static const struct stream_encoder_funcs dcn35_str_enc_funcs = {</div><div class='ctx'> 	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,</div><div class='ctx'> 	.set_dynamic_metadata = enc2_set_dynamic_metadata,</div><div class='ctx'> 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,</div><div class='del'>-	.dig_stream_enable = enc35_stream_encoder_enable,</div><div class='add'>+	.enable_stream = enc35_stream_encoder_enable,</div><div class='ctx'> </div><div class='ctx'> 	.set_input_mode = enc314_set_dig_input_mode,</div><div class='ctx'> 	.enable_fifo = enc35_enable_fifo,</div><div class='ctx'> 	.disable_fifo = enc35_disable_fifo,</div><div class='add'>+	.is_fifo_enabled = enc35_is_fifo_enabled,</div><div class='ctx'> 	.map_stream_to_link = enc35_stream_encoder_map_to_link,</div><div class='add'>+	.get_pixels_per_cycle = enc35_get_pixels_per_cycle,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn35_dio_stream_encoder_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h<br/>index 499052329ebb..ddb33fdfb4ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h</a></div><div class='hunk'>@@ -28,7 +28,6 @@</div><div class='ctx'> #include "dcn30/dcn30_vpg.h"</div><div class='ctx'> #include "dcn30/dcn30_afmt.h"</div><div class='ctx'> #include "stream_encoder.h"</div><div class='del'>-#include "dcn10/dcn10_link_encoder.h"</div><div class='ctx'> #include "dcn20/dcn20_stream_encoder.h"</div><div class='ctx'> </div><div class='ctx'> /* Register bit field name change */</div><div class='hunk'>@@ -323,5 +322,11 @@ void enc3_dp_set_dsc_pps_info_packet(</div><div class='ctx'> 	uint8_t *dsc_packed_pps,</div><div class='ctx'> 	bool immediate_update);</div><div class='ctx'> </div><div class='add'>+void enc35_disable_fifo(</div><div class='add'>+	struct stream_encoder *enc);</div><div class='add'>+</div><div class='add'>+void enc35_enable_fifo(</div><div class='add'>+	struct stream_encoder *enc);</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> #endif /* __DC_DIO_STREAM_ENCODER_DCN35_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c<br/>index 81e349d5835b..7e558ca195ef 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c</a></div><div class='hunk'>@@ -1,6 +1,5 @@</div><div class='del'>-/* SPDX-License-Identifier: MIT */</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'>  * copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -20,14 +19,27 @@</div><div class='ctx'>  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='ctx'>  * OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> </div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "link_encoder.h"</div><div class='ctx'> #include "dcn31/dcn31_dio_link_encoder.h"</div><div class='del'>-#include "dcn35_dio_link_encoder.h"</div><div class='add'>+#include "dcn32/dcn32_dio_link_encoder.h"</div><div class='add'>+#include "dcn401_dio_link_encoder.h"</div><div class='add'>+#include "stream_encoder.h"</div><div class='add'>+#include "dc_bios_types.h"</div><div class='add'>+</div><div class='add'>+#include "gpio_service_interface.h"</div><div class='add'>+</div><div class='add'>+#ifndef MIN</div><div class='add'>+#define MIN(X, Y) ((X) &lt; (Y) ? (X) : (Y))</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> #define CTX \</div><div class='ctx'> 	enc10-&gt;base.ctx</div><div class='ctx'> #define DC_LOGGER \</div><div class='hunk'>@@ -39,51 +51,76 @@</div><div class='ctx'> #undef FN</div><div class='ctx'> #define FN(reg_name, field_name) \</div><div class='ctx'> 	enc10-&gt;link_shift-&gt;field_name, enc10-&gt;link_mask-&gt;field_name</div><div class='del'>-/*</div><div class='del'>- * @brief</div><div class='del'>- * Trigger Source Select</div><div class='del'>- * ASIC-dependent, actual values for register programming</div><div class='del'>- */</div><div class='del'>-#define DCN35_DIG_FE_SOURCE_SELECT_INVALID 0x0</div><div class='del'>-#define DCN35_DIG_FE_SOURCE_SELECT_DIGA 0x1</div><div class='del'>-#define DCN35_DIG_FE_SOURCE_SELECT_DIGB 0x2</div><div class='del'>-#define DCN35_DIG_FE_SOURCE_SELECT_DIGC 0x4</div><div class='del'>-#define DCN35_DIG_FE_SOURCE_SELECT_DIGD 0x08</div><div class='del'>-#define DCN35_DIG_FE_SOURCE_SELECT_DIGE 0x10</div><div class='ctx'> </div><div class='add'>+#define AUX_REG(reg)\</div><div class='add'>+	(enc10-&gt;aux_regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#define AUX_REG_READ(reg_name) \</div><div class='add'>+		dm_read_reg(CTX, AUX_REG(reg_name))</div><div class='ctx'> </div><div class='del'>-bool dcn35_is_dig_enabled(struct link_encoder *enc)</div><div class='add'>+#define AUX_REG_WRITE(reg_name, val) \</div><div class='add'>+			dm_write_reg(CTX, AUX_REG(reg_name), val)</div><div class='add'>+</div><div class='add'>+#ifndef MIN</div><div class='add'>+#define MIN(X, Y) ((X) &lt; (Y) ? (X) : (Y))</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void enc401_hw_init(struct link_encoder *enc)</div><div class='ctx'> {</div><div class='del'>-	uint32_t enabled;</div><div class='ctx'> 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='ctx'> </div><div class='del'>-	REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &amp;enabled);</div><div class='del'>-	return (enabled == 1);</div><div class='add'>+/*</div><div class='add'>+	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2</div><div class='add'>+	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4</div><div class='add'>+	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8</div><div class='add'>+	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16</div><div class='add'>+	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32</div><div class='add'>+	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64</div><div class='add'>+	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128</div><div class='add'>+	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,</div><div class='add'>+	AUX_RX_START_WINDOW = 1 [6:4]</div><div class='add'>+	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]</div><div class='add'>+	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1</div><div class='add'>+	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1</div><div class='add'>+	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0</div><div class='add'>+	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1</div><div class='add'>+	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1</div><div class='add'>+	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3</div><div class='add'>+	AUX_RX_DETECTION_THRESHOLD [30:28] = 1</div><div class='add'>+*/</div><div class='add'>+	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);</div><div class='add'>+</div><div class='add'>+	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);</div><div class='add'>+</div><div class='add'>+	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;</div><div class='add'>+	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk</div><div class='add'>+	// 27MHz -&gt; 0xd</div><div class='add'>+	// 100MHz -&gt; 0x32</div><div class='add'>+	// 48MHz -&gt; 0x18</div><div class='add'>+</div><div class='add'>+	// Set TMDS_CTL0 to 1.  This is a legacy setting.</div><div class='add'>+	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);</div><div class='add'>+</div><div class='add'>+	dcn10_aux_initialize(enc10);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum signal_type dcn35_get_dig_mode(</div><div class='del'>-	struct link_encoder *enc)</div><div class='del'>-{</div><div class='del'>-	uint32_t value;</div><div class='del'>-	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='ctx'> </div><div class='del'>-	REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &amp;value);</div><div class='del'>-	switch (value) {</div><div class='del'>-	case 0:</div><div class='del'>-		return SIGNAL_TYPE_DISPLAY_PORT;</div><div class='del'>-	case 2:</div><div class='del'>-		return SIGNAL_TYPE_DVI_SINGLE_LINK;</div><div class='del'>-	case 3:</div><div class='del'>-		return SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='del'>-	case 5:</div><div class='del'>-		return SIGNAL_TYPE_DISPLAY_PORT_MST;</div><div class='del'>-	default:</div><div class='del'>-		return SIGNAL_TYPE_NONE;</div><div class='add'>+void dcn401_link_encoder_enable_dp_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	enum clock_source_id clock_source)</div><div class='add'>+{</div><div class='add'>+	if (!enc-&gt;ctx-&gt;dc-&gt;debug.avoid_vbios_exec_table) {</div><div class='add'>+		dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='del'>-	return SIGNAL_TYPE_NONE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_link_encoder_setup(</div><div class='add'>+void dcn401_link_encoder_setup(</div><div class='ctx'> 	struct link_encoder *enc,</div><div class='ctx'> 	enum signal_type signal)</div><div class='ctx'> {</div><div class='hunk'>@@ -114,32 +151,50 @@ void dcn35_link_encoder_setup(</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);</div><div class='del'>-</div><div class='add'>+	REG_UPDATE(DIG_BE_EN_CNTL, DIG_BE_ENABLE, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_link_encoder_init(struct link_encoder *enc)</div><div class='add'>+bool dcn401_is_dig_enabled(struct link_encoder *enc)</div><div class='ctx'> {</div><div class='del'>-	enc32_hw_init(enc);</div><div class='del'>-	dcn35_link_encoder_set_fgcg(enc, enc-&gt;ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.dio);</div><div class='add'>+	uint32_t clk_enabled;</div><div class='add'>+	uint32_t dig_enabled;</div><div class='add'>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='add'>+</div><div class='add'>+	REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &amp;clk_enabled);</div><div class='add'>+	REG_GET(DIG_BE_EN_CNTL, DIG_BE_ENABLE, &amp;dig_enabled);</div><div class='add'>+	return (clk_enabled == 1 &amp;&amp; dig_enabled == 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable)</div><div class='add'>+enum signal_type dcn401_get_dig_mode(</div><div class='add'>+	struct link_encoder *enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable);</div><div class='add'>+	uint32_t value;</div><div class='add'>+	REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &amp;value);</div><div class='add'>+	switch (value) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SIGNAL_TYPE_DISPLAY_PORT;</div><div class='add'>+	case 2:</div><div class='add'>+		return SIGNAL_TYPE_DVI_SINGLE_LINK;</div><div class='add'>+	case 3:</div><div class='add'>+		return SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='add'>+	case 5:</div><div class='add'>+		return SIGNAL_TYPE_DISPLAY_PORT_MST;</div><div class='add'>+	default:</div><div class='add'>+		return SIGNAL_TYPE_NONE;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct link_encoder_funcs dcn35_link_enc_funcs = {</div><div class='add'>+static const struct link_encoder_funcs dcn401_link_enc_funcs = {</div><div class='ctx'> 	.read_state = link_enc2_read_state,</div><div class='ctx'> 	.validate_output_with_stream =</div><div class='ctx'> 			dcn30_link_encoder_validate_output_with_stream,</div><div class='del'>-	.hw_init = dcn35_link_encoder_init,</div><div class='del'>-	.setup = dcn35_link_encoder_setup,</div><div class='add'>+	.hw_init = enc401_hw_init,</div><div class='add'>+	.setup = dcn401_link_encoder_setup,</div><div class='ctx'> 	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,</div><div class='del'>-	.enable_dp_output = dcn31_link_encoder_enable_dp_output,</div><div class='del'>-	.enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,</div><div class='del'>-	.disable_output = dcn31_link_encoder_disable_output,</div><div class='add'>+	.enable_dp_output = dcn401_link_encoder_enable_dp_output,</div><div class='add'>+	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,</div><div class='add'>+	.disable_output = dcn10_link_encoder_disable_output,</div><div class='ctx'> 	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,</div><div class='ctx'> 	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,</div><div class='ctx'> 	.update_mst_stream_allocation_table =</div><div class='hunk'>@@ -150,19 +205,19 @@ static const struct link_encoder_funcs dcn35_link_enc_funcs = {</div><div class='ctx'> 	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,</div><div class='ctx'> 	.enable_hpd = dcn10_link_encoder_enable_hpd,</div><div class='ctx'> 	.disable_hpd = dcn10_link_encoder_disable_hpd,</div><div class='del'>-	.is_dig_enabled = dcn35_is_dig_enabled,</div><div class='add'>+	.is_dig_enabled = dcn401_is_dig_enabled,</div><div class='ctx'> 	.destroy = dcn10_link_encoder_destroy,</div><div class='ctx'> 	.fec_set_enable = enc2_fec_set_enable,</div><div class='ctx'> 	.fec_set_ready = enc2_fec_set_ready,</div><div class='ctx'> 	.fec_is_active = enc2_fec_is_active,</div><div class='ctx'> 	.get_dig_frontend = dcn10_get_dig_frontend,</div><div class='del'>-	.get_dig_mode = dcn35_get_dig_mode,</div><div class='del'>-	.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,</div><div class='del'>-	.get_max_link_cap = dcn31_link_encoder_get_max_link_cap,</div><div class='add'>+	.get_dig_mode = dcn401_get_dig_mode,</div><div class='add'>+	.is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,</div><div class='add'>+	.get_max_link_cap = dcn32_link_encoder_get_max_link_cap,</div><div class='ctx'> 	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-void dcn35_link_encoder_construct(</div><div class='add'>+void dcn401_link_encoder_construct(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20,</div><div class='ctx'> 	const struct encoder_init_data *init_data,</div><div class='ctx'> 	const struct encoder_feature_support *enc_features,</div><div class='hunk'>@@ -177,7 +232,7 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 	enum bp_result result = BP_RESULT_OK;</div><div class='ctx'> 	struct dcn10_link_encoder *enc10 = &amp;enc20-&gt;enc10;</div><div class='ctx'> </div><div class='del'>-	enc10-&gt;base.funcs = &amp;dcn35_link_enc_funcs;</div><div class='add'>+	enc10-&gt;base.funcs = &amp;dcn401_link_enc_funcs;</div><div class='ctx'> 	enc10-&gt;base.ctx = init_data-&gt;ctx;</div><div class='ctx'> 	enc10-&gt;base.id = init_data-&gt;encoder;</div><div class='ctx'> </div><div class='hunk'>@@ -188,6 +243,8 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 	enc10-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='ctx'> </div><div class='ctx'> 	enc10-&gt;base.features = *enc_features;</div><div class='add'>+	if (enc10-&gt;base.connector.id == CONNECTOR_ID_USBC)</div><div class='add'>+		enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='ctx'> </div><div class='ctx'> 	enc10-&gt;base.transmitter = init_data-&gt;transmitter;</div><div class='ctx'> </div><div class='hunk'>@@ -196,10 +253,9 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> /*	if (dal_adapter_service_is_feature_supported(as,</div><div class='del'>- *		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))</div><div class='del'>- *		enc10-&gt;base.features.flags.bits.</div><div class='del'>- *			DP_SINK_DETECT_POLL_DATA_PIN = true;</div><div class='del'>- */</div><div class='add'>+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))</div><div class='add'>+		enc10-&gt;base.features.flags.bits.</div><div class='add'>+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/</div><div class='ctx'> </div><div class='ctx'> 	enc10-&gt;base.output_signals =</div><div class='ctx'> 		SIGNAL_TYPE_DVI_SINGLE_LINK |</div><div class='hunk'>@@ -237,9 +293,8 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 		enc10-&gt;base.preferred_engine = ENGINE_ID_UNKNOWN;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* default to one to mirror Windows behavior */</div><div class='ctx'> 	enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = 1;</div><div class='del'>-	if (enc10-&gt;base.connector.id == CONNECTOR_ID_USBC)</div><div class='del'>-		enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (bp_funcs-&gt;get_connector_speed_cap_info)</div><div class='ctx'> 		result = bp_funcs-&gt;get_connector_speed_cap_info(enc10-&gt;base.ctx-&gt;dc_bios,</div><div class='hunk'>@@ -256,17 +311,12 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;</div><div class='del'>-		if (bp_cap_info.DP_IS_USB_C) {</div><div class='del'>-			/*BIOS not switch to use CONNECTOR_ID_USBC = 24 yet*/</div><div class='del'>-			enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 	} else {</div><div class='ctx'> 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",</div><div class='ctx'> 				__func__,</div><div class='ctx'> 				result);</div><div class='ctx'> 	}</div><div class='del'>-	if (enc10-&gt;base.ctx-&gt;dc-&gt;debug.hdmi20_disable)</div><div class='add'>+	if (enc10-&gt;base.ctx-&gt;dc-&gt;debug.hdmi20_disable) {</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = 0;</div><div class='del'>-</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h<br/>new file mode 100644<br/>index 000000000000..6baab8302b81<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.h</a></div><div class='hunk'>@@ -0,0 +1,134 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ *  and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_LINK_ENCODER__DCN401_H__</div><div class='add'>+#define __DC_LINK_ENCODER__DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "dcn30/dcn30_dio_link_encoder.h"</div><div class='add'>+</div><div class='add'>+#define LINK_ENCODER_MASK_SH_LIST_DCN401(mask_sh) \</div><div class='add'>+	LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, HDCP_SOFT_RESET, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_HDCP_CLOCK_ON, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\</div><div class='add'>+	LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\</div><div class='add'>+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\</div><div class='add'>+	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\</div><div class='add'>+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)</div><div class='add'>+</div><div class='add'>+void dcn401_link_encoder_construct(</div><div class='add'>+	struct dcn20_link_encoder *enc20,</div><div class='add'>+	const struct encoder_init_data *init_data,</div><div class='add'>+	const struct encoder_feature_support *enc_features,</div><div class='add'>+	const struct dcn10_link_enc_registers *link_regs,</div><div class='add'>+	const struct dcn10_link_enc_aux_registers *aux_regs,</div><div class='add'>+	const struct dcn10_link_enc_hpd_registers *hpd_regs,</div><div class='add'>+	const struct dcn10_link_enc_shift *link_shift,</div><div class='add'>+	const struct dcn10_link_enc_mask *link_mask);</div><div class='add'>+</div><div class='add'>+void enc401_hw_init(struct link_encoder *enc);</div><div class='add'>+</div><div class='add'>+void dcn401_link_encoder_enable_dp_output(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	const struct dc_link_settings *link_settings,</div><div class='add'>+	enum clock_source_id clock_source);</div><div class='add'>+</div><div class='add'>+void dcn401_link_encoder_setup(</div><div class='add'>+	struct link_encoder *enc,</div><div class='add'>+	enum signal_type signal);</div><div class='add'>+</div><div class='add'>+enum signal_type dcn401_get_dig_mode(</div><div class='add'>+	struct link_encoder *enc);</div><div class='add'>+</div><div class='add'>+bool dcn401_is_dig_enabled(struct link_encoder *enc);</div><div class='add'>+</div><div class='add'>+enum signal_type dcn401_get_dig_mode(struct link_encoder *enc);</div><div class='add'>+#endif /* __DC_LINK_ENCODER__DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c<br/>new file mode 100644<br/>index 000000000000..99aab70ef3e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c</a></div><div class='hunk'>@@ -0,0 +1,856 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ *  and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "dc_bios_types.h"</div><div class='add'>+#include "dcn30/dcn30_dio_stream_encoder.h"</div><div class='add'>+#include "dcn32/dcn32_dio_stream_encoder.h"</div><div class='add'>+#include "dcn35/dcn35_dio_stream_encoder.h"</div><div class='add'>+</div><div class='add'>+#include "dcn401_dio_stream_encoder.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "hw_shared.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+#include "dpcd_defs.h"</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+		enc1-&gt;base.ctx-&gt;logger</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	(enc1-&gt;regs-&gt;reg)</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	enc1-&gt;se_shift-&gt;field_name, enc1-&gt;se_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+#define VBI_LINE_0 0</div><div class='add'>+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	enc1-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void enc401_dp_set_odm_combine(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	bool odm_combine)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* setup stream encoder in dvi mode */</div><div class='add'>+void enc401_stream_encoder_dvi_set_stream_attribute(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	struct dc_crtc_timing *crtc_timing,</div><div class='add'>+	bool is_dual_link)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	if (!enc-&gt;ctx-&gt;dc-&gt;debug.avoid_vbios_exec_table) {</div><div class='add'>+		struct bp_encoder_control cntl = {0};</div><div class='add'>+</div><div class='add'>+		cntl.action = ENCODER_CONTROL_SETUP;</div><div class='add'>+		cntl.engine_id = enc1-&gt;base.id;</div><div class='add'>+		cntl.signal = is_dual_link ?</div><div class='add'>+			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;</div><div class='add'>+		cntl.enable_dp_audio = false;</div><div class='add'>+		cntl.pixel_clock = crtc_timing-&gt;pix_clk_100hz / 10;</div><div class='add'>+		cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;</div><div class='add'>+</div><div class='add'>+		if (enc1-&gt;base.bp-&gt;funcs-&gt;encoder_control(</div><div class='add'>+				enc1-&gt;base.bp, &amp;cntl) != BP_RESULT_OK)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+</div><div class='add'>+		//Set pattern for clock channel, default vlue 0x63 does not work</div><div class='add'>+		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);</div><div class='add'>+</div><div class='add'>+		//DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup</div><div class='add'>+</div><div class='add'>+		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg</div><div class='add'>+</div><div class='add'>+		/* DIG_START is removed from the register spec */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ASSERT(crtc_timing-&gt;pixel_encoding == PIXEL_ENCODING_RGB);</div><div class='add'>+	ASSERT(crtc_timing-&gt;display_color_depth == COLOR_DEPTH_888);</div><div class='add'>+	enc401_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* setup stream encoder in hdmi mode */</div><div class='add'>+void enc401_stream_encoder_hdmi_set_stream_attribute(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	struct dc_crtc_timing *crtc_timing,</div><div class='add'>+	int actual_pix_clk_khz,</div><div class='add'>+	bool enable_audio)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	if (!enc-&gt;ctx-&gt;dc-&gt;debug.avoid_vbios_exec_table) {</div><div class='add'>+		struct bp_encoder_control cntl = {0};</div><div class='add'>+</div><div class='add'>+		cntl.action = ENCODER_CONTROL_SETUP;</div><div class='add'>+		cntl.engine_id = enc1-&gt;base.id;</div><div class='add'>+		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='add'>+		cntl.enable_dp_audio = enable_audio;</div><div class='add'>+		cntl.pixel_clock = actual_pix_clk_khz;</div><div class='add'>+		cntl.lanes_number = LANE_COUNT_FOUR;</div><div class='add'>+</div><div class='add'>+		if (enc1-&gt;base.bp-&gt;funcs-&gt;encoder_control(</div><div class='add'>+				enc1-&gt;base.bp, &amp;cntl) != BP_RESULT_OK)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+</div><div class='add'>+		//Set pattern for clock channel, default vlue 0x63 does not work</div><div class='add'>+		REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);</div><div class='add'>+</div><div class='add'>+		//DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup</div><div class='add'>+</div><div class='add'>+		//DIG_SOURCE_SELECT is already set in dig_connect_to_otg</div><div class='add'>+</div><div class='add'>+		/* DIG_START is removed from the register spec */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Configure pixel encoding */</div><div class='add'>+	enc401_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);</div><div class='add'>+</div><div class='add'>+	/* setup HDMI engine */</div><div class='add'>+	REG_UPDATE_6(HDMI_CONTROL,</div><div class='add'>+		HDMI_PACKET_GEN_VERSION, 1,</div><div class='add'>+		HDMI_KEEPOUT_MODE, 1,</div><div class='add'>+		HDMI_DEEP_COLOR_ENABLE, 0,</div><div class='add'>+		HDMI_DATA_SCRAMBLE_EN, 0,</div><div class='add'>+		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,</div><div class='add'>+		HDMI_CLOCK_CHANNEL_RATE, 0);</div><div class='add'>+</div><div class='add'>+	/* Configure color depth */</div><div class='add'>+	switch (crtc_timing-&gt;display_color_depth) {</div><div class='add'>+	case COLOR_DEPTH_888:</div><div class='add'>+		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_101010:</div><div class='add'>+		if (crtc_timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422) {</div><div class='add'>+			REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+					HDMI_DEEP_COLOR_DEPTH, 1,</div><div class='add'>+					HDMI_DEEP_COLOR_ENABLE, 0);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+					HDMI_DEEP_COLOR_DEPTH, 1,</div><div class='add'>+					HDMI_DEEP_COLOR_ENABLE, 1);</div><div class='add'>+			}</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_121212:</div><div class='add'>+		if (crtc_timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422) {</div><div class='add'>+			REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+					HDMI_DEEP_COLOR_DEPTH, 2,</div><div class='add'>+					HDMI_DEEP_COLOR_ENABLE, 0);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+					HDMI_DEEP_COLOR_DEPTH, 2,</div><div class='add'>+					HDMI_DEEP_COLOR_ENABLE, 1);</div><div class='add'>+			}</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_161616:</div><div class='add'>+		REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+				HDMI_DEEP_COLOR_DEPTH, 3,</div><div class='add'>+				HDMI_DEEP_COLOR_ENABLE, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (actual_pix_clk_khz &gt;= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {</div><div class='add'>+		/* enable HDMI data scrambler</div><div class='add'>+		 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M</div><div class='add'>+		 * Clock channel frequency is 1/4 of character rate.</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+			HDMI_DATA_SCRAMBLE_EN, 1,</div><div class='add'>+			HDMI_CLOCK_CHANNEL_RATE, 1);</div><div class='add'>+	} else if (crtc_timing-&gt;flags.LTE_340MCSC_SCRAMBLE) {</div><div class='add'>+</div><div class='add'>+		/* TODO: New feature for DCE11, still need to implement */</div><div class='add'>+</div><div class='add'>+		/* enable HDMI data scrambler</div><div class='add'>+		 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE</div><div class='add'>+		 * Clock channel frequency is the same</div><div class='add'>+		 * as character rate</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE_2(HDMI_CONTROL,</div><div class='add'>+			HDMI_DATA_SCRAMBLE_EN, 1,</div><div class='add'>+			HDMI_CLOCK_CHANNEL_RATE, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/* Enable transmission of General Control packet on every frame */</div><div class='add'>+	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,</div><div class='add'>+		HDMI_GC_CONT, 1,</div><div class='add'>+		HDMI_GC_SEND, 1,</div><div class='add'>+		HDMI_NULL_SEND, 1);</div><div class='add'>+</div><div class='add'>+	/* Disable Audio Content Protection packet transmission */</div><div class='add'>+	REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);</div><div class='add'>+	/* following belongs to audio */</div><div class='add'>+	/* Enable Audio InfoFrame packet transmission. */</div><div class='add'>+	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);</div><div class='add'>+</div><div class='add'>+	/* update double-buffered AUDIO_INFO registers immediately */</div><div class='add'>+	ASSERT(enc-&gt;afmt);</div><div class='add'>+	enc-&gt;afmt-&gt;funcs-&gt;audio_info_immediate_update(enc-&gt;afmt);</div><div class='add'>+</div><div class='add'>+	/* Select line number on which to send Audio InfoFrame packets */</div><div class='add'>+	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,</div><div class='add'>+				VBI_LINE_0 + 2);</div><div class='add'>+</div><div class='add'>+	/* set HDMI GC AVMUTE */</div><div class='add'>+	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	// The naming of this field is confusing, what it means is the output mode of otg, which</div><div class='add'>+	// is the input mode of the dig</div><div class='add'>+	switch (pix_per_container)	{</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);</div><div class='add'>+		break;</div><div class='add'>+	case 8:</div><div class='add'>+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	bool two_pix = timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR420;</div><div class='add'>+</div><div class='add'>+	two_pix = two_pix || (timing-&gt;flags.DSC &amp;&amp; timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422</div><div class='add'>+			&amp;&amp; !timing-&gt;dsc_cfg.ycbcr422_simple);</div><div class='add'>+	return two_pix;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void enc401_stream_encoder_dp_unblank(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		struct stream_encoder *enc,</div><div class='add'>+		const struct encoder_unblank_param *param)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	if (param-&gt;link_settings.link_rate != LINK_RATE_UNKNOWN) {</div><div class='add'>+		uint32_t n_vid = 0x8000;</div><div class='add'>+		uint32_t m_vid;</div><div class='add'>+		uint32_t pix_per_container = 1;</div><div class='add'>+		uint64_t m_vid_l = n_vid;</div><div class='add'>+</div><div class='add'>+		/* YCbCr 4:2:0 or YCbCr4:2:2 simple + DSC: Computed VID_M will be 2X the input rate */</div><div class='add'>+		if (is_two_pixels_per_containter(&amp;param-&gt;timing)) {</div><div class='add'>+			pix_per_container = 2;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* M / N = Fstream / Flink</div><div class='add'>+		 * m_vid / n_vid = pixel rate / link rate</div><div class='add'>+		 */</div><div class='add'>+		m_vid_l *= param-&gt;timing.pix_clk_100hz / pix_per_container / 10;</div><div class='add'>+		m_vid_l = div_u64(m_vid_l,</div><div class='add'>+			param-&gt;link_settings.link_rate</div><div class='add'>+				* LINK_RATE_REF_FREQ_IN_KHZ);</div><div class='add'>+</div><div class='add'>+		m_vid = (uint32_t) m_vid_l;</div><div class='add'>+</div><div class='add'>+		/* enable auto measurement */</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);</div><div class='add'>+</div><div class='add'>+		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,</div><div class='add'>+		 * therefore program initial value for Mvid and Nvid</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);</div><div class='add'>+</div><div class='add'>+		/* reduce jitter based on read rate */</div><div class='add'>+		switch (param-&gt;pix_per_cycle)	{</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x1);</div><div class='add'>+			break;</div><div class='add'>+		case 4:</div><div class='add'>+			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x2);</div><div class='add'>+			break;</div><div class='add'>+		case 8:</div><div class='add'>+			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x3);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* make sure stream is disabled before resetting steer fifo */</div><div class='add'>+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);</div><div class='add'>+	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);</div><div class='add'>+</div><div class='add'>+	/* DIG_START is removed from the register spec */</div><div class='add'>+</div><div class='add'>+	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen</div><div class='add'>+	 * that it overflows during mode transition, and sometimes doesn't recover.</div><div class='add'>+	 */</div><div class='add'>+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);</div><div class='add'>+	udelay(10);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 1, DP_VID_STREAM_DIS_DEFER, 2);</div><div class='add'>+	udelay(200);</div><div class='add'>+</div><div class='add'>+	/* DIG Resync FIFO now needs to be explicitly enabled</div><div class='add'>+	 */</div><div class='add'>+	/* read start level = 0 will bring underflow / overflow and DIG_FIFO_ERROR = 1</div><div class='add'>+	 * so set it to 1/2 full = 7 before reset as suggested by hardware team.</div><div class='add'>+	 */</div><div class='add'>+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);</div><div class='add'>+</div><div class='add'>+	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);</div><div class='add'>+</div><div class='add'>+	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	/* wait 100us for DIG/DP logic to prime</div><div class='add'>+	 * (i.e. a few video lines)</div><div class='add'>+	 */</div><div class='add'>+	udelay(100);</div><div class='add'>+</div><div class='add'>+	/* the hardware would start sending video at the start of the next DP</div><div class='add'>+	 * frame (i.e. rising edge of the vblank).</div><div class='add'>+	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this</div><div class='add'>+	 * register has no effect on enable transition! HW always guarantees</div><div class='add'>+	 * VID_STREAM enable at start of next frame, and this is not</div><div class='add'>+	 * programmable</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);</div><div class='add'>+</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* this function read dsc related register fields to be logged later in dcn10_log_hw_state</div><div class='add'>+ * into a dcn_dsc_state struct.</div><div class='add'>+ */</div><div class='add'>+void enc401_read_state(struct stream_encoder *enc, struct enc_state *s)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	//if dsc is enabled, continue to read</div><div class='add'>+	REG_GET(DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, &amp;s-&gt;dsc_mode);</div><div class='add'>+</div><div class='add'>+	if (s-&gt;dsc_mode) {</div><div class='add'>+		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &amp;s-&gt;sec_gsp_pps_line_num);</div><div class='add'>+</div><div class='add'>+		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &amp;s-&gt;vbid6_line_reference);</div><div class='add'>+		REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &amp;s-&gt;vbid6_line_num);</div><div class='add'>+</div><div class='add'>+		REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &amp;s-&gt;sec_gsp_pps_enable);</div><div class='add'>+		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &amp;s-&gt;sec_stream_enable);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void enc401_stream_encoder_enable(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	enum signal_type signal,</div><div class='add'>+	bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+	if (enable) {</div><div class='add'>+		switch (signal) {</div><div class='add'>+		case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+		case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='add'>+			/* TMDS-DVI */</div><div class='add'>+			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 2);</div><div class='add'>+			break;</div><div class='add'>+		case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='add'>+			/* TMDS-HDMI */</div><div class='add'>+			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 3);</div><div class='add'>+			break;</div><div class='add'>+		case SIGNAL_TYPE_DISPLAY_PORT_MST:</div><div class='add'>+			/* DP MST */</div><div class='add'>+			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 5);</div><div class='add'>+			break;</div><div class='add'>+		case SIGNAL_TYPE_EDP:</div><div class='add'>+		case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='add'>+		case SIGNAL_TYPE_VIRTUAL:</div><div class='add'>+			/* DP SST */</div><div class='add'>+			REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 0);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			/* invalid mode ! */</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 1);</div><div class='add'>+		REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 1);</div><div class='add'>+	} else {</div><div class='add'>+		REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 0);</div><div class='add'>+		REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void enc401_stream_encoder_dp_set_stream_attribute(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	struct dc_crtc_timing *crtc_timing,</div><div class='add'>+	enum dc_color_space output_color_space,</div><div class='add'>+	bool use_vsc_sdp_for_colorimetry,</div><div class='add'>+	uint32_t enable_sdp_splitting)</div><div class='add'>+{</div><div class='add'>+	uint32_t h_active_start;</div><div class='add'>+	uint32_t v_active_start;</div><div class='add'>+	uint32_t misc0 = 0;</div><div class='add'>+	uint32_t misc1 = 0;</div><div class='add'>+	uint32_t h_blank;</div><div class='add'>+	uint32_t h_back_porch;</div><div class='add'>+	uint8_t colorimetry_bpc;</div><div class='add'>+	uint8_t dp_pixel_encoding = 0;</div><div class='add'>+	uint8_t dp_component_depth = 0;</div><div class='add'>+	uint8_t dp_translate_pixel_enc = 0;</div><div class='add'>+	// Fix set but not used warnings</div><div class='add'>+	//uint8_t dp_pixel_encoding_type = 0;</div><div class='add'>+	uint8_t dp_compressed_pixel_format = 0;</div><div class='add'>+</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+	struct dc_crtc_timing hw_crtc_timing = *crtc_timing;</div><div class='add'>+</div><div class='add'>+	if (hw_crtc_timing.flags.INTERLACE) {</div><div class='add'>+		/*the input timing is in VESA spec format with Interlace flag =1*/</div><div class='add'>+		hw_crtc_timing.v_total /= 2;</div><div class='add'>+		hw_crtc_timing.v_border_top /= 2;</div><div class='add'>+		hw_crtc_timing.v_addressable /= 2;</div><div class='add'>+		hw_crtc_timing.v_border_bottom /= 2;</div><div class='add'>+		hw_crtc_timing.v_front_porch /= 2;</div><div class='add'>+		hw_crtc_timing.v_sync_width /= 2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/* set pixel encoding */</div><div class='add'>+	switch (hw_crtc_timing.pixel_encoding) {</div><div class='add'>+	case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;</div><div class='add'>+		break;</div><div class='add'>+	case PIXEL_ENCODING_YCBCR444:</div><div class='add'>+		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;</div><div class='add'>+</div><div class='add'>+		if (hw_crtc_timing.flags.Y_ONLY)</div><div class='add'>+			if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)</div><div class='add'>+				/* HW testing only, no use case yet.</div><div class='add'>+				 * Color depth of Y-only could be</div><div class='add'>+				 * 8, 10, 12, 16 bits</div><div class='add'>+				 */</div><div class='add'>+				dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;</div><div class='add'>+</div><div class='add'>+		/* Note: DP_MSA_MISC1 bit 7 is the indicator</div><div class='add'>+		 * of Y-only mode.</div><div class='add'>+		 * This bit is set in HW if register</div><div class='add'>+		 * DP_PIXEL_ENCODING is programmed to 0x4</div><div class='add'>+		 */</div><div class='add'>+		break;</div><div class='add'>+	case PIXEL_ENCODING_YCBCR420:</div><div class='add'>+		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	misc1 = REG_READ(DP_MSA_MISC);</div><div class='add'>+	/* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.</div><div class='add'>+	 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the</div><div class='add'>+	 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,</div><div class='add'>+	 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").</div><div class='add'>+	 */</div><div class='add'>+	if (use_vsc_sdp_for_colorimetry)</div><div class='add'>+		misc1 = misc1 | 0x40;</div><div class='add'>+	else</div><div class='add'>+		misc1 = misc1 &amp; ~0x40;</div><div class='add'>+</div><div class='add'>+	/* set color depth */</div><div class='add'>+	switch (hw_crtc_timing.display_color_depth) {</div><div class='add'>+	case COLOR_DEPTH_666:</div><div class='add'>+		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_888:</div><div class='add'>+		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_101010:</div><div class='add'>+		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_121212:</div><div class='add'>+		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_161616:</div><div class='add'>+		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hw_crtc_timing.flags.DSC) {</div><div class='add'>+		// Fix set but not used error</div><div class='add'>+		//dp_pixel_encoding_type = 1;</div><div class='add'>+		switch (hw_crtc_timing.pixel_encoding) {</div><div class='add'>+		case PIXEL_ENCODING_YCBCR444:</div><div class='add'>+			dp_compressed_pixel_format = 0;</div><div class='add'>+			break;</div><div class='add'>+		case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+			dp_compressed_pixel_format = 1;</div><div class='add'>+			if (hw_crtc_timing.dsc_cfg.ycbcr422_simple)</div><div class='add'>+				dp_compressed_pixel_format = 0;</div><div class='add'>+			break;</div><div class='add'>+		case PIXEL_ENCODING_YCBCR420:</div><div class='add'>+			dp_compressed_pixel_format = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			dp_compressed_pixel_format = 0;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		// Fix set but not used error</div><div class='add'>+		//dp_pixel_encoding_type = 0;</div><div class='add'>+		switch (dp_pixel_encoding) {</div><div class='add'>+		case DP_PIXEL_ENCODING_TYPE_RGB444:</div><div class='add'>+			dp_translate_pixel_enc = 0;</div><div class='add'>+			break;</div><div class='add'>+		case DP_PIXEL_ENCODING_TYPE_YCBCR422:</div><div class='add'>+			dp_translate_pixel_enc = 1;</div><div class='add'>+			break;</div><div class='add'>+		case DP_PIXEL_ENCODING_TYPE_YCBCR444:</div><div class='add'>+			dp_translate_pixel_enc = 0;</div><div class='add'>+			break;</div><div class='add'>+		case DP_PIXEL_ENCODING_TYPE_Y_ONLY:</div><div class='add'>+			dp_translate_pixel_enc = 3;</div><div class='add'>+			break;</div><div class='add'>+		case DP_PIXEL_ENCODING_TYPE_YCBCR420:</div><div class='add'>+			dp_translate_pixel_enc = 2;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/* Set DP pixel encoding and component depth */</div><div class='add'>+	REG_UPDATE_4(DP_PIXEL_FORMAT,</div><div class='add'>+			PIXEL_ENCODING_TYPE, hw_crtc_timing.flags.DSC ? 1 : 0,</div><div class='add'>+			UNCOMPRESSED_PIXEL_FORMAT, dp_translate_pixel_enc,</div><div class='add'>+			UNCOMPRESSED_COMPONENT_DEPTH, dp_component_depth,</div><div class='add'>+			COMPRESSED_PIXEL_FORMAT, dp_compressed_pixel_format);</div><div class='add'>+</div><div class='add'>+	/* set dynamic range and YCbCr range */</div><div class='add'>+</div><div class='add'>+	switch (hw_crtc_timing.display_color_depth) {</div><div class='add'>+	case COLOR_DEPTH_666:</div><div class='add'>+		colorimetry_bpc = 0;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_888:</div><div class='add'>+		colorimetry_bpc = 1;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_101010:</div><div class='add'>+		colorimetry_bpc = 2;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_121212:</div><div class='add'>+		colorimetry_bpc = 3;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		colorimetry_bpc = 0;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	misc0 = colorimetry_bpc &lt;&lt; 5;</div><div class='add'>+</div><div class='add'>+	switch (output_color_space) {</div><div class='add'>+	case COLOR_SPACE_SRGB:</div><div class='add'>+		misc1 = misc1 &amp; ~0x80; /* bit7 = 0*/</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_SPACE_SRGB_LIMITED:</div><div class='add'>+		misc0 = misc0 | 0x8; /* bit3=1 */</div><div class='add'>+		misc1 = misc1 &amp; ~0x80; /* bit7 = 0*/</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_SPACE_YCBCR601:</div><div class='add'>+	case COLOR_SPACE_YCBCR601_LIMITED:</div><div class='add'>+		misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */</div><div class='add'>+		misc1 = misc1 &amp; ~0x80; /* bit7 = 0*/</div><div class='add'>+		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)</div><div class='add'>+			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */</div><div class='add'>+		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)</div><div class='add'>+			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_SPACE_YCBCR709:</div><div class='add'>+	case COLOR_SPACE_YCBCR709_LIMITED:</div><div class='add'>+		misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */</div><div class='add'>+		misc1 = misc1 &amp; ~0x80; /* bit7 = 0*/</div><div class='add'>+		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)</div><div class='add'>+			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */</div><div class='add'>+		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)</div><div class='add'>+			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:</div><div class='add'>+	case COLOR_SPACE_2020_RGB_FULLRANGE:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='add'>+	case COLOR_SPACE_XR_RGB:</div><div class='add'>+	case COLOR_SPACE_MSREF_SCRGB:</div><div class='add'>+	case COLOR_SPACE_ADOBERGB:</div><div class='add'>+	case COLOR_SPACE_DCIP3:</div><div class='add'>+	case COLOR_SPACE_XV_YCC_709:</div><div class='add'>+	case COLOR_SPACE_XV_YCC_601:</div><div class='add'>+	case COLOR_SPACE_DISPLAYNATIVE:</div><div class='add'>+	case COLOR_SPACE_DOLBYVISION:</div><div class='add'>+	case COLOR_SPACE_APPCTRL:</div><div class='add'>+	case COLOR_SPACE_CUSTOMPOINTS:</div><div class='add'>+	case COLOR_SPACE_UNKNOWN:</div><div class='add'>+	case COLOR_SPACE_YCBCR709_BLACK:</div><div class='add'>+	default:</div><div class='add'>+		/* do nothing */</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);</div><div class='add'>+	REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */</div><div class='add'>+</div><div class='add'>+	/* dcn new register</div><div class='add'>+	 * dc_crtc_timing is vesa dmt struct. data from edid</div><div class='add'>+	 */</div><div class='add'>+	REG_SET_2(DP_MSA_TIMING_PARAM1, 0,</div><div class='add'>+			DP_MSA_HTOTAL, hw_crtc_timing.h_total,</div><div class='add'>+			DP_MSA_VTOTAL, hw_crtc_timing.v_total);</div><div class='add'>+</div><div class='add'>+	/* calculate from vesa timing parameters</div><div class='add'>+	 * h_active_start related to leading edge of sync</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -</div><div class='add'>+			hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;</div><div class='add'>+</div><div class='add'>+	h_back_porch = h_blank - hw_crtc_timing.h_front_porch -</div><div class='add'>+			hw_crtc_timing.h_sync_width;</div><div class='add'>+</div><div class='add'>+	/* start at beginning of left border */</div><div class='add'>+	h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -</div><div class='add'>+			hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -</div><div class='add'>+			hw_crtc_timing.v_front_porch;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/* start at beginning of left border */</div><div class='add'>+	REG_SET_2(DP_MSA_TIMING_PARAM2, 0,</div><div class='add'>+		DP_MSA_HSTART, h_active_start,</div><div class='add'>+		DP_MSA_VSTART, v_active_start);</div><div class='add'>+</div><div class='add'>+	REG_SET_4(DP_MSA_TIMING_PARAM3, 0,</div><div class='add'>+			DP_MSA_HSYNCWIDTH,</div><div class='add'>+			hw_crtc_timing.h_sync_width,</div><div class='add'>+			DP_MSA_HSYNCPOLARITY,</div><div class='add'>+			!hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,</div><div class='add'>+			DP_MSA_VSYNCWIDTH,</div><div class='add'>+			hw_crtc_timing.v_sync_width,</div><div class='add'>+			DP_MSA_VSYNCPOLARITY,</div><div class='add'>+			!hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);</div><div class='add'>+</div><div class='add'>+	/* HWDITH include border or overscan */</div><div class='add'>+	REG_SET_2(DP_MSA_TIMING_PARAM4, 0,</div><div class='add'>+		DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +</div><div class='add'>+		hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,</div><div class='add'>+		DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +</div><div class='add'>+		hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DP_SEC_FRAMING4,</div><div class='add'>+		DP_SST_SDP_SPLITTING, enable_sdp_splitting);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void enc401_stream_encoder_map_to_link(</div><div class='add'>+		struct stream_encoder *enc,</div><div class='add'>+		uint32_t stream_enc_inst,</div><div class='add'>+		uint32_t link_enc_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(STREAM_MAPPER_CONTROL,</div><div class='add'>+				DIG_STREAM_LINK_TARGET, link_enc_inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct stream_encoder_funcs dcn401_str_enc_funcs = {</div><div class='add'>+	.dp_set_odm_combine =</div><div class='add'>+		enc401_dp_set_odm_combine,</div><div class='add'>+	.dp_set_stream_attribute =</div><div class='add'>+		enc401_stream_encoder_dp_set_stream_attribute,</div><div class='add'>+	.hdmi_set_stream_attribute =</div><div class='add'>+		enc401_stream_encoder_hdmi_set_stream_attribute,</div><div class='add'>+	.dvi_set_stream_attribute =</div><div class='add'>+		enc401_stream_encoder_dvi_set_stream_attribute,</div><div class='add'>+	.set_throttled_vcp_size =</div><div class='add'>+		enc1_stream_encoder_set_throttled_vcp_size,</div><div class='add'>+	.update_hdmi_info_packets =</div><div class='add'>+		enc3_stream_encoder_update_hdmi_info_packets,</div><div class='add'>+	.stop_hdmi_info_packets =</div><div class='add'>+		enc3_stream_encoder_stop_hdmi_info_packets,</div><div class='add'>+	.update_dp_info_packets_sdp_line_num =</div><div class='add'>+		enc3_stream_encoder_update_dp_info_packets_sdp_line_num,</div><div class='add'>+	.update_dp_info_packets =</div><div class='add'>+		enc3_stream_encoder_update_dp_info_packets,</div><div class='add'>+	.stop_dp_info_packets =</div><div class='add'>+		enc1_stream_encoder_stop_dp_info_packets,</div><div class='add'>+	.dp_blank =</div><div class='add'>+		enc1_stream_encoder_dp_blank,</div><div class='add'>+	.dp_unblank =</div><div class='add'>+		enc401_stream_encoder_dp_unblank,</div><div class='add'>+	.audio_mute_control = enc3_audio_mute_control,</div><div class='add'>+</div><div class='add'>+	.dp_audio_setup = enc3_se_dp_audio_setup,</div><div class='add'>+	.dp_audio_enable = enc3_se_dp_audio_enable,</div><div class='add'>+	.dp_audio_disable = enc1_se_dp_audio_disable,</div><div class='add'>+</div><div class='add'>+	.hdmi_audio_setup = enc3_se_hdmi_audio_setup,</div><div class='add'>+	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,</div><div class='add'>+	.setup_stereo_sync  = enc1_setup_stereo_sync,</div><div class='add'>+	.set_avmute = enc1_stream_encoder_set_avmute,</div><div class='add'>+	.dig_connect_to_otg = enc1_dig_connect_to_otg,</div><div class='add'>+	.dig_source_otg = enc1_dig_source_otg,</div><div class='add'>+</div><div class='add'>+	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,</div><div class='add'>+</div><div class='add'>+	.enc_read_state = enc401_read_state,</div><div class='add'>+	.dp_set_dsc_config = NULL,</div><div class='add'>+	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,</div><div class='add'>+	.set_dynamic_metadata = enc401_set_dynamic_metadata,</div><div class='add'>+	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,</div><div class='add'>+	.enable_stream = enc401_stream_encoder_enable,</div><div class='add'>+</div><div class='add'>+	.set_input_mode = enc401_set_dig_input_mode,</div><div class='add'>+	.enable_fifo = enc35_enable_fifo,</div><div class='add'>+	.disable_fifo = enc35_disable_fifo,</div><div class='add'>+	.map_stream_to_link = enc401_stream_encoder_map_to_link,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn401_dio_stream_encoder_construct(</div><div class='add'>+	struct dcn10_stream_encoder *enc1,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct dc_bios *bp,</div><div class='add'>+	enum engine_id eng_id,</div><div class='add'>+	struct vpg *vpg,</div><div class='add'>+	struct afmt *afmt,</div><div class='add'>+	const struct dcn10_stream_enc_registers *regs,</div><div class='add'>+	const struct dcn10_stream_encoder_shift *se_shift,</div><div class='add'>+	const struct dcn10_stream_encoder_mask *se_mask)</div><div class='add'>+{</div><div class='add'>+	enc1-&gt;base.funcs = &amp;dcn401_str_enc_funcs;</div><div class='add'>+	enc1-&gt;base.ctx = ctx;</div><div class='add'>+	enc1-&gt;base.id = eng_id;</div><div class='add'>+	enc1-&gt;base.bp = bp;</div><div class='add'>+	enc1-&gt;base.vpg = vpg;</div><div class='add'>+	enc1-&gt;base.afmt = afmt;</div><div class='add'>+	enc1-&gt;regs = regs;</div><div class='add'>+	enc1-&gt;se_shift = se_shift;</div><div class='add'>+	enc1-&gt;se_mask = se_mask;</div><div class='add'>+	enc1-&gt;base.stream_enc_inst = vpg-&gt;inst;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void enc401_set_dynamic_metadata(struct stream_encoder *enc,</div><div class='add'>+		bool enable_dme,</div><div class='add'>+		uint32_t hubp_requestor_id,</div><div class='add'>+		enum dynamic_metadata_mode dmdata_mode)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);</div><div class='add'>+</div><div class='add'>+	if (enable_dme) {</div><div class='add'>+		REG_UPDATE_2(DME_CONTROL,</div><div class='add'>+				METADATA_HUBP_REQUESTOR_ID, hubp_requestor_id,</div><div class='add'>+				METADATA_STREAM_TYPE, (dmdata_mode == dmdata_dolby_vision) ? 1 : 0);</div><div class='add'>+</div><div class='add'>+		/* Use default line reference DP_SOF for bringup.</div><div class='add'>+		 * Should use OTG_SOF for DRR cases</div><div class='add'>+		 */</div><div class='add'>+		if (dmdata_mode == dmdata_dp)</div><div class='add'>+			REG_UPDATE_3(DP_SEC_METADATA_TRANSMISSION,</div><div class='add'>+					DP_SEC_METADATA_PACKET_ENABLE, 1,</div><div class='add'>+					DP_SEC_METADATA_PACKET_LINE_REFERENCE, 0,</div><div class='add'>+					DP_SEC_METADATA_PACKET_LINE, 20);</div><div class='add'>+		else {</div><div class='add'>+			REG_UPDATE_3(HDMI_METADATA_PACKET_CONTROL,</div><div class='add'>+					HDMI_METADATA_PACKET_ENABLE, 1,</div><div class='add'>+					HDMI_METADATA_PACKET_LINE_REFERENCE, 0,</div><div class='add'>+					HDMI_METADATA_PACKET_LINE, 2);</div><div class='add'>+</div><div class='add'>+			if (dmdata_mode == dmdata_dolby_vision)</div><div class='add'>+				REG_UPDATE(HDMI_CONTROL,</div><div class='add'>+						DOLBY_VISION_EN, 1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DME_CONTROL,</div><div class='add'>+				METADATA_ENGINE_EN, 1);</div><div class='add'>+	} else {</div><div class='add'>+		REG_UPDATE(DME_CONTROL,</div><div class='add'>+				METADATA_ENGINE_EN, 0);</div><div class='add'>+</div><div class='add'>+		if (dmdata_mode == dmdata_dp)</div><div class='add'>+			REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,</div><div class='add'>+					DP_SEC_METADATA_PACKET_ENABLE, 0);</div><div class='add'>+		else {</div><div class='add'>+			REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,</div><div class='add'>+					HDMI_METADATA_PACKET_ENABLE, 0);</div><div class='add'>+			REG_UPDATE(HDMI_CONTROL,</div><div class='add'>+					DOLBY_VISION_EN, 0);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+void enc401_stream_encoder_set_stream_attribute_helper(</div><div class='add'>+		struct dcn10_stream_encoder *enc1,</div><div class='add'>+		struct dc_crtc_timing *crtc_timing)</div><div class='add'>+{</div><div class='add'>+	switch (crtc_timing-&gt;pixel_encoding) {</div><div class='add'>+	case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+		REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h<br/>new file mode 100644<br/>index 000000000000..d6b00cd246b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h</a></div><div class='hunk'>@@ -0,0 +1,240 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2021 - Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ *  and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_DIO_STREAM_ENCODER_DCN401_H__</div><div class='add'>+#define __DC_DIO_STREAM_ENCODER_DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "dcn30/dcn30_vpg.h"</div><div class='add'>+#include "dcn30/dcn30_afmt.h"</div><div class='add'>+#include "stream_encoder.h"</div><div class='add'>+#include "dcn20/dcn20_stream_encoder.h"</div><div class='add'>+</div><div class='add'>+#define SE_COMMON_MASK_SH_LIST_DCN401(mask_sh)\</div><div class='add'>+	SE_SF(DP0_DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_FORMAT, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_PIXEL_FORMAT, COMPRESSED_PIXEL_FORMAT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\</div><div class='add'>+	SE_SF(DIG1_HDMI_CONTROL, TMDS_PIXEL_ENCODING, mask_sh),\</div><div class='add'>+	SE_SF(DIG1_HDMI_CONTROL, TMDS_COLOR_FORMAT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_INTERVAL, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\</div><div class='add'>+	SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\</div><div class='add'>+	SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\</div><div class='add'>+	SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_HDMI_CONTROL, DOLBY_VISION_EN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_EN_CNTL, DIG_FE_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_MODE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SOFT_RESET, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\</div><div class='add'>+	SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\</div><div class='add'>+	SE_SF(DIG0_STREAM_MAPPER_CONTROL, DIG_STREAM_LINK_TARGET, mask_sh),</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dcn401_dio_stream_encoder_construct(</div><div class='add'>+	struct dcn10_stream_encoder *enc1,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct dc_bios *bp,</div><div class='add'>+	enum engine_id eng_id,</div><div class='add'>+	struct vpg *vpg,</div><div class='add'>+	struct afmt *afmt,</div><div class='add'>+	const struct dcn10_stream_enc_registers *regs,</div><div class='add'>+	const struct dcn10_stream_encoder_shift *se_shift,</div><div class='add'>+	const struct dcn10_stream_encoder_mask *se_mask);</div><div class='add'>+</div><div class='add'>+void enc401_set_dynamic_metadata(struct stream_encoder *enc,</div><div class='add'>+		bool enable_dme,</div><div class='add'>+		uint32_t hubp_requestor_id,</div><div class='add'>+		enum dynamic_metadata_mode dmdata_mode);</div><div class='add'>+void enc401_stream_encoder_set_stream_attribute_helper(</div><div class='add'>+		struct dcn10_stream_encoder *enc1,</div><div class='add'>+		struct dc_crtc_timing *crtc_timing);</div><div class='add'>+void enc401_stream_encoder_dp_set_stream_attribute(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	struct dc_crtc_timing *crtc_timing,</div><div class='add'>+	enum dc_color_space output_color_space,</div><div class='add'>+	bool use_vsc_sdp_for_colorimetry,</div><div class='add'>+	uint32_t enable_sdp_splitting);</div><div class='add'>+void enc401_stream_encoder_dvi_set_stream_attribute(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	struct dc_crtc_timing *crtc_timing,</div><div class='add'>+	bool is_dual_link);</div><div class='add'>+void enc401_stream_encoder_dp_unblank(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		struct stream_encoder *enc,</div><div class='add'>+		const struct encoder_unblank_param *param);</div><div class='add'>+void enc401_stream_encoder_enable(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	enum signal_type signal,</div><div class='add'>+	bool enable);</div><div class='add'>+void enc401_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container);</div><div class='add'>+void enc401_stream_encoder_map_to_link(</div><div class='add'>+		struct stream_encoder *enc,</div><div class='add'>+		uint32_t stream_enc_inst,</div><div class='add'>+		uint32_t link_enc_inst);</div><div class='add'>+void enc401_read_state(struct stream_encoder *enc, struct enc_state *s);</div><div class='add'>+void enc401_stream_encoder_hdmi_set_stream_attribute(</div><div class='add'>+	struct stream_encoder *enc,</div><div class='add'>+	struct dc_crtc_timing *crtc_timing,</div><div class='add'>+	int actual_pix_clk_khz,</div><div class='add'>+	bool enable_audio);</div><div class='add'>+#endif /* __DC_DIO_STREAM_ENCODER_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h<br/>index 6d7a15dcf8a7..9d160b39e8c5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_helpers.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_helpers.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_helpers.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dm_helpers.h</a></div><div class='hunk'>@@ -36,6 +36,7 @@</div><div class='ctx'> struct dc_dp_mst_stream_allocation_table;</div><div class='ctx'> struct aux_payload;</div><div class='ctx'> enum aux_return_code_type;</div><div class='add'>+enum set_config_status;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Allocate memory accessible by the GPU</div><div class='hunk'>@@ -152,11 +153,24 @@ bool dm_helpers_submit_i2c(</div><div class='ctx'> 		const struct dc_link *link,</div><div class='ctx'> 		struct i2c_command *cmd);</div><div class='ctx'> </div><div class='add'>+bool dm_helpers_execute_fused_io(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		union dmub_rb_cmd *commands,</div><div class='add'>+		uint8_t count,</div><div class='add'>+		uint32_t timeout_us</div><div class='add'>+);</div><div class='add'>+</div><div class='ctx'> bool dm_helpers_dp_write_dsc_enable(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		bool enable</div><div class='ctx'> );</div><div class='add'>+</div><div class='add'>+bool dm_helpers_dp_write_hblank_reduction(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> bool dm_helpers_is_dp_sink_present(</div><div class='ctx'> 		struct dc_link *link);</div><div class='ctx'> </div><div class='hunk'>@@ -200,7 +214,7 @@ int dm_helper_dmub_aux_transfer_sync(</div><div class='ctx'> 		const struct dc_link *link,</div><div class='ctx'> 		struct aux_payload *payload,</div><div class='ctx'> 		enum aux_return_code_type *operation_result);</div><div class='del'>-enum set_config_status;</div><div class='add'>+</div><div class='ctx'> int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,</div><div class='ctx'> 		const struct dc_link *link,</div><div class='ctx'> 		struct set_config_cmd_payload *payload,</div><div class='hunk'>@@ -209,4 +223,7 @@ enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link);</div><div class='ctx'> </div><div class='ctx'> enum dc_edid_status dm_helpers_get_sbios_edid(struct dc_link *link, struct dc_edid *edid);</div><div class='ctx'> </div><div class='add'>+bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream);</div><div class='add'>+bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> #endif /* __DM_HELPERS__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h<br/>index bd7ba0a25198..b0e17a594ec3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_pp_smu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dm_pp_smu.h</a></div><div class='hunk'>@@ -40,8 +40,9 @@ enum pp_smu_ver {</div><div class='ctx'> 	PP_SMU_UNSUPPORTED,</div><div class='ctx'> 	PP_SMU_VER_RV,</div><div class='ctx'> 	PP_SMU_VER_NV,</div><div class='del'>-	PP_SMU_VER_RN,</div><div class='ctx'> </div><div class='add'>+	PP_SMU_VER_RN,</div><div class='add'>+	PP_SMU_VER_VG,</div><div class='ctx'> 	PP_SMU_VER_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h<br/>index d0eed3b4771e..fbbf9c757b3c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_services.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_services.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_services.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dm_services.h</a></div><div class='hunk'>@@ -143,7 +143,7 @@ void generic_reg_wait(const struct dc_context *ctx,</div><div class='ctx'> 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,</div><div class='ctx'> 	const char *func_name, int line);</div><div class='ctx'> </div><div class='del'>-unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);</div><div class='add'>+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, const char *fmt, ...);</div><div class='ctx'> </div><div class='ctx'> /* These macros need to be used with soc15 registers in order to retrieve</div><div class='ctx'>  * the actual offset.</div><div class='hunk'>@@ -275,12 +275,30 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc</div><div class='ctx'> #define PERF_TRACE_CTX(__CTX)	dm_perf_trace_timestamp(__func__, __LINE__, __CTX)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * SMU message tracing</div><div class='add'>+ */</div><div class='add'>+void dm_trace_smu_enter(uint32_t msg_id, uint32_t param_in, unsigned int delay, struct dc_context *ctx);</div><div class='add'>+void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx);</div><div class='add'>+</div><div class='add'>+#define TRACE_SMU_MSG_DELAY(msg_id, param_in, delay, ctx)	dm_trace_smu_enter(msg_id, param_in, delay, ctx)</div><div class='add'>+#define TRACE_SMU_MSG(msg_id, param_in, ctx)	dm_trace_smu_enter(msg_id, param_in, 0, ctx)</div><div class='add'>+#define TRACE_SMU_MSG_ENTER(msg_id, param_in, ctx)	dm_trace_smu_enter(msg_id, param_in, 0, ctx)</div><div class='add'>+#define TRACE_SMU_MSG_EXIT(success, response, ctx)	dm_trace_smu_exit(success, response, ctx)</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * DMUB Interfaces</div><div class='ctx'>  */</div><div class='ctx'> bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);</div><div class='ctx'> bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * ACPI Interfaces</div><div class='add'>+ */</div><div class='add'>+void dm_acpi_process_phy_transition_interlock(</div><div class='add'>+	const struct dc_context *ctx,</div><div class='add'>+	struct dm_process_phy_transition_init_params process_phy_transition_init_params);</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * Debug and verification hooks</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -294,4 +312,6 @@ void dm_dtn_log_end(struct dc_context *ctx,</div><div class='ctx'> </div><div class='ctx'> char *dce_version_to_string(const int version);</div><div class='ctx'> </div><div class='add'>+bool dc_supports_vrr(const enum dce_version v);</div><div class='add'>+</div><div class='ctx'> #endif /* __DM_SERVICES_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h<br/>index facf269c4326..3b093b8699ab 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_services_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dm_services_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dm_services_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dm_services_types.h</a></div><div class='hunk'>@@ -127,7 +127,7 @@ struct dm_pp_single_disp_config {</div><div class='ctx'> 	uint32_t src_height;</div><div class='ctx'> 	uint32_t src_width;</div><div class='ctx'> 	uint32_t v_refresh;</div><div class='del'>-	uint32_t sym_clock; /* HDMI only */</div><div class='add'>+	uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */</div><div class='ctx'> 	struct dc_link_settings link_settings; /* DP only */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -275,4 +275,30 @@ enum dm_dmub_wait_type {</div><div class='ctx'> 	DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dm_acpi_transition_link_type {</div><div class='add'>+	hdmi_tmds,</div><div class='add'>+	hdmi_frl,</div><div class='add'>+	dp_8b_10b,</div><div class='add'>+	dp_128b_132b,</div><div class='add'>+	none</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dm_process_phy_transition_init_params {</div><div class='add'>+	uint32_t phy_id;</div><div class='add'>+	uint8_t action;</div><div class='add'>+	uint32_t sym_clock_10khz;</div><div class='add'>+	enum signal_type signal;</div><div class='add'>+	enum dc_lane_count display_port_lanes_count;</div><div class='add'>+	enum dc_link_rate display_port_link_rate;</div><div class='add'>+	uint32_t transition_bitmask;</div><div class='add'>+	uint8_t hdmi_frl_num_lanes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dm_process_phy_transition_input_params {</div><div class='add'>+	uint32_t phy_id;</div><div class='add'>+	uint32_t transition_id;</div><div class='add'>+	uint32_t phy_configuration;</div><div class='add'>+	uint32_t data_rate;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile<br/>index c4a5efd2dda5..b357683b4255 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/Makefile</a></div><div class='hunk'>@@ -25,47 +25,19 @@</div><div class='ctx'> # It provides the general basic services required by other DAL</div><div class='ctx'> # subcomponents.</div><div class='ctx'> </div><div class='del'>-ifdef CONFIG_X86</div><div class='del'>-dml_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float</div><div class='del'>-dml_ccflags := $(dml_ccflags-y) -msse</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_PPC64</div><div class='del'>-dml_ccflags := -mhard-float -maltivec</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_ARM64</div><div class='del'>-dml_rcflags := -mgeneral-regs-only</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_LOONGARCH</div><div class='del'>-dml_ccflags := -mfpu=64</div><div class='del'>-dml_rcflags := -msoft-float</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_CC_IS_GCC</div><div class='del'>-ifneq ($(call gcc-min-version, 70100),y)</div><div class='del'>-IS_OLD_GCC = 1</div><div class='del'>-endif</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_X86</div><div class='del'>-ifdef IS_OLD_GCC</div><div class='del'>-# Stack alignment mismatch, proceed with caution.</div><div class='del'>-# GCC &lt; 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3</div><div class='del'>-# (8B stack alignment).</div><div class='del'>-dml_ccflags += -mpreferred-stack-boundary=4</div><div class='del'>-else</div><div class='del'>-dml_ccflags += -msse2</div><div class='del'>-endif</div><div class='del'>-endif</div><div class='add'>+dml_ccflags := $(CC_FLAGS_FPU)</div><div class='add'>+dml_rcflags := $(CC_FLAGS_NO_FPU)</div><div class='ctx'> </div><div class='ctx'> ifneq ($(CONFIG_FRAME_WARN),0)</div><div class='del'>-ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)</div><div class='del'>-frame_warn_flag := -Wframe-larger-than=3072</div><div class='del'>-else</div><div class='del'>-frame_warn_flag := -Wframe-larger-than=2048</div><div class='del'>-endif</div><div class='add'>+    ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)</div><div class='add'>+        frame_warn_limit := 3072</div><div class='add'>+    else</div><div class='add'>+        frame_warn_limit := 2048</div><div class='add'>+    endif</div><div class='add'>+</div><div class='add'>+    ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)</div><div class='add'>+        frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)</div><div class='add'>+    endif</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)</div><div class='hunk'>@@ -115,6 +87,8 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcfla</div><div class='ctx'> CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags)</div><div class='ctx'> CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags)</div><div class='ctx'> CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn314/display_mode_vba_314.o := $(dml_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn314/display_rq_dlg_calc_314.o := $(dml_rcflags)</div><div class='ctx'> CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags)</div><div class='ctx'> CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)</div><div class='ctx'> CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o  := $(dml_rcflags)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c<br/>index 0c4a8fe8e5ca..74962791302f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c</a></div><div class='hunk'>@@ -690,7 +690,7 @@ static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)</div><div class='ctx'> static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,</div><div class='ctx'> 		unsigned int pixel_rate_100hz)</div><div class='ctx'> {</div><div class='del'>-	float pixel_rate_mhz = pixel_rate_100hz / 10000;</div><div class='add'>+	float pixel_rate_mhz = pixel_rate_100hz / 10000.0;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * force enabling pipe split by lower dpp clock for DPM0 to just</div><div class='hunk'>@@ -748,7 +748,7 @@ static unsigned int get_highest_allowed_voltage_level(bool is_vmin_only_asic)</div><div class='ctx'> bool dcn_validate_bandwidth(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * we want a breakdown of the various stages of validation, which the</div><div class='hunk'>@@ -1119,7 +1119,7 @@ bool dcn_validate_bandwidth(</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (v-&gt;voltage_level != number_of_states_plus_one &amp;&amp; !fast_validate) {</div><div class='add'>+	if (v-&gt;voltage_level != number_of_states_plus_one &amp;&amp; validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		float bw_consumed = v-&gt;total_bandwidth_consumed_gbyte_per_second;</div><div class='ctx'> </div><div class='ctx'> 		if (bw_consumed &lt; v-&gt;fabric_and_dram_bandwidth_vmin0p65)</div><div class='hunk'>@@ -1286,7 +1286,7 @@ bool dcn_validate_bandwidth(</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (v-&gt;voltage_level == number_of_states_plus_one) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fail);</div><div class='del'>-	} else if (fast_validate) {</div><div class='add'>+	} else if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1312,138 +1312,6 @@ bool dcn_validate_bandwidth(</div><div class='ctx'> 		return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned int dcn_find_normalized_clock_vdd_Level(</div><div class='del'>-	const struct dc *dc,</div><div class='del'>-	enum dm_pp_clock_type clocks_type,</div><div class='del'>-	int clocks_in_khz)</div><div class='del'>-{</div><div class='del'>-	int vdd_level = dcn_bw_v_min0p65;</div><div class='del'>-</div><div class='del'>-	if (clocks_in_khz == 0)/*todo some clock not in the considerations*/</div><div class='del'>-		return vdd_level;</div><div class='del'>-</div><div class='del'>-	switch (clocks_type) {</div><div class='del'>-	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:</div><div class='del'>-		if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dispclk_vmax0p9*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p91;</div><div class='del'>-			BREAK_TO_DEBUGGER();</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dispclk_vnom0p8*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p9;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dispclk_vmid0p72*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_nom0p8;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dispclk_vmin0p65*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_mid0p72;</div><div class='del'>-		} else</div><div class='del'>-			vdd_level = dcn_bw_v_min0p65;</div><div class='del'>-		break;</div><div class='del'>-	case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:</div><div class='del'>-		if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;phyclkv_max0p9*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p91;</div><div class='del'>-			BREAK_TO_DEBUGGER();</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;phyclkv_nom0p8*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p9;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;phyclkv_mid0p72*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_nom0p8;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;phyclkv_min0p65*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_mid0p72;</div><div class='del'>-		} else</div><div class='del'>-			vdd_level = dcn_bw_v_min0p65;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case DM_PP_CLOCK_TYPE_DPPCLK:</div><div class='del'>-		if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dppclk_vmax0p9*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p91;</div><div class='del'>-			BREAK_TO_DEBUGGER();</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dppclk_vnom0p8*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p9;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dppclk_vmid0p72*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_nom0p8;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;max_dppclk_vmin0p65*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_mid0p72;</div><div class='del'>-		} else</div><div class='del'>-			vdd_level = dcn_bw_v_min0p65;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case DM_PP_CLOCK_TYPE_MEMORY_CLK:</div><div class='del'>-		{</div><div class='del'>-			unsigned factor = (ddr4_dram_factor_single_Channel * dc-&gt;dcn_soc-&gt;number_of_channels);</div><div class='del'>-</div><div class='del'>-			if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {</div><div class='del'>-				vdd_level = dcn_bw_v_max0p91;</div><div class='del'>-				BREAK_TO_DEBUGGER();</div><div class='del'>-			} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {</div><div class='del'>-				vdd_level = dcn_bw_v_max0p9;</div><div class='del'>-			} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {</div><div class='del'>-				vdd_level = dcn_bw_v_nom0p8;</div><div class='del'>-			} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {</div><div class='del'>-				vdd_level = dcn_bw_v_mid0p72;</div><div class='del'>-			} else</div><div class='del'>-				vdd_level = dcn_bw_v_min0p65;</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case DM_PP_CLOCK_TYPE_DCFCLK:</div><div class='del'>-		if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;dcfclkv_max0p9*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p91;</div><div class='del'>-			BREAK_TO_DEBUGGER();</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;dcfclkv_nom0p8*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_max0p9;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;dcfclkv_mid0p72*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_nom0p8;</div><div class='del'>-		} else if (clocks_in_khz &gt; dc-&gt;dcn_soc-&gt;dcfclkv_min0p65*1000) {</div><div class='del'>-			vdd_level = dcn_bw_v_mid0p72;</div><div class='del'>-		} else</div><div class='del'>-			vdd_level = dcn_bw_v_min0p65;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		 break;</div><div class='del'>-	}</div><div class='del'>-	return vdd_level;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-unsigned int dcn_find_dcfclk_suits_all(</div><div class='del'>-	const struct dc *dc,</div><div class='del'>-	struct dc_clocks *clocks)</div><div class='del'>-{</div><div class='del'>-	unsigned vdd_level, vdd_level_temp;</div><div class='del'>-	unsigned dcf_clk;</div><div class='del'>-</div><div class='del'>-	/*find a common supported voltage level*/</div><div class='del'>-	vdd_level = dcn_find_normalized_clock_vdd_Level(</div><div class='del'>-		dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks-&gt;dispclk_khz);</div><div class='del'>-	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(</div><div class='del'>-		dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks-&gt;phyclk_khz);</div><div class='del'>-</div><div class='del'>-	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);</div><div class='del'>-	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(</div><div class='del'>-		dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks-&gt;dppclk_khz);</div><div class='del'>-	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);</div><div class='del'>-</div><div class='del'>-	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(</div><div class='del'>-		dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks-&gt;fclk_khz);</div><div class='del'>-	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);</div><div class='del'>-	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(</div><div class='del'>-		dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks-&gt;dcfclk_khz);</div><div class='del'>-</div><div class='del'>-	/*find that level conresponding dcfclk*/</div><div class='del'>-	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);</div><div class='del'>-	if (vdd_level == dcn_bw_v_max0p91) {</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		dcf_clk = dc-&gt;dcn_soc-&gt;dcfclkv_max0p9*1000;</div><div class='del'>-	} else if (vdd_level == dcn_bw_v_max0p9)</div><div class='del'>-		dcf_clk =  dc-&gt;dcn_soc-&gt;dcfclkv_max0p9*1000;</div><div class='del'>-	else if (vdd_level == dcn_bw_v_nom0p8)</div><div class='del'>-		dcf_clk =  dc-&gt;dcn_soc-&gt;dcfclkv_nom0p8*1000;</div><div class='del'>-	else if (vdd_level == dcn_bw_v_mid0p72)</div><div class='del'>-		dcf_clk =  dc-&gt;dcn_soc-&gt;dcfclkv_mid0p72*1000;</div><div class='del'>-	else</div><div class='del'>-		dcf_clk =  dc-&gt;dcn_soc-&gt;dcfclkv_min0p65*1000;</div><div class='del'>-</div><div class='del'>-	DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);</div><div class='del'>-	return dcf_clk;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void dcn_bw_update_from_pplib_fclks(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct dm_pp_clock_levels_with_voltage *fclks)</div><div class='hunk'>@@ -1453,10 +1321,9 @@ void dcn_bw_update_from_pplib_fclks(</div><div class='ctx'> 	ASSERT(fclks-&gt;num_levels);</div><div class='ctx'> </div><div class='ctx'> 	vmin0p65_idx = 0;</div><div class='del'>-	vmid0p72_idx = fclks-&gt;num_levels -</div><div class='del'>-		(fclks-&gt;num_levels &gt; 2 ? 3 : (fclks-&gt;num_levels &gt; 1 ? 2 : 1));</div><div class='del'>-	vnom0p8_idx = fclks-&gt;num_levels - (fclks-&gt;num_levels &gt; 1 ? 2 : 1);</div><div class='del'>-	vmax0p9_idx = fclks-&gt;num_levels - 1;</div><div class='add'>+	vmid0p72_idx = fclks-&gt;num_levels &gt; 2 ? fclks-&gt;num_levels - 3 : 0;</div><div class='add'>+	vnom0p8_idx = fclks-&gt;num_levels &gt; 1 ? fclks-&gt;num_levels - 2 : 0;</div><div class='add'>+	vmax0p9_idx = fclks-&gt;num_levels &gt; 0 ? fclks-&gt;num_levels - 1 : 0;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_soc-&gt;fabric_and_dram_bandwidth_vmin0p65 =</div><div class='ctx'> 		32 * (fclks-&gt;data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h<br/>index 63219ecd8478..1bf6b12f5663 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h</a></div><div class='hunk'>@@ -29,4 +29,4 @@</div><div class='ctx'> </div><div class='ctx'> void dcn10_resource_construct_fp(struct dc *dc);</div><div class='ctx'> </div><div class='del'>-#endif /* __DCN20_FPU_H__ */</div><div class='add'>+#endif /* __DCN10_FPU_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c<br/>index 38ab9ad60ef8..7aaf13bbd4e4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c</a></div><div class='hunk'>@@ -30,8 +30,7 @@</div><div class='ctx'> #include "dcn20/dcn20_resource.h"</div><div class='ctx'> #include "dcn21/dcn21_resource.h"</div><div class='ctx'> #include "clk_mgr/dcn21/rn_clk_mgr.h"</div><div class='del'>-</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn20_fpu.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='hunk'>@@ -1084,7 +1083,10 @@ static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struc</div><div class='ctx'> 		struct dc_stream_status *stream_status = &amp;context-&gt;stream_status[0];</div><div class='ctx'> 		int minmum_z8_residency = dc-&gt;debug.minimum_z8_residency_time &gt; 0 ? dc-&gt;debug.minimum_z8_residency_time : 1000;</div><div class='ctx'> 		bool allow_z8 = context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; (double)minmum_z8_residency;</div><div class='del'>-		bool is_pwrseq0 = link-&gt;link_index == 0;</div><div class='add'>+		bool is_pwrseq0 = (link &amp;&amp; link-&gt;link_index == 0);</div><div class='add'>+		bool is_psr = (link &amp;&amp; (link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1 ||</div><div class='add'>+						link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1) &amp;&amp; !link-&gt;panel_config.psr.disable_psr);</div><div class='add'>+		bool is_replay = link &amp;&amp; link-&gt;replay_settings.replay_feature_enabled;</div><div class='ctx'> </div><div class='ctx'> 		/* Don't support multi-plane configurations */</div><div class='ctx'> 		if (stream_status-&gt;plane_count &gt; 1)</div><div class='hunk'>@@ -1092,8 +1094,8 @@ static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struc</div><div class='ctx'> </div><div class='ctx'> 		if (is_pwrseq0 &amp;&amp; context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; 5000.0)</div><div class='ctx'> 			return DCN_ZSTATE_SUPPORT_ALLOW;</div><div class='del'>-		else if (is_pwrseq0 &amp;&amp; link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1 &amp;&amp; !link-&gt;panel_config.psr.disable_psr)</div><div class='del'>-			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;</div><div class='add'>+		else if (is_pwrseq0 &amp;&amp; (is_psr || is_replay))</div><div class='add'>+			return DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;</div><div class='ctx'> 		else</div><div class='ctx'> 			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1129,7 +1131,8 @@ static void dcn20_adjust_freesync_v_startup(</div><div class='ctx'> 					patched_crtc_timing.v_addressable -</div><div class='ctx'> 					patched_crtc_timing.v_border_top;</div><div class='ctx'> </div><div class='del'>-	newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);</div><div class='add'>+	/* The newVStartUp is 1 line before vsync point */</div><div class='add'>+	newVstartup = asic_blank_end + 1;</div><div class='ctx'> </div><div class='ctx'> 	*vstartup_start = ((newVstartup &gt; *vstartup_start) ? newVstartup : *vstartup_start);</div><div class='ctx'> }</div><div class='hunk'>@@ -1311,7 +1314,7 @@ static void swizzle_to_dml_params(</div><div class='ctx'> int dcn20_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 					  struct dc_state *context,</div><div class='ctx'> 					  display_e2e_pipe_params_st *pipes,</div><div class='del'>-					  bool fast_validate)</div><div class='add'>+					  enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int pipe_cnt, i;</div><div class='ctx'> 	bool synchronized_vblank = true;</div><div class='hunk'>@@ -1559,6 +1562,8 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 			pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;</div><div class='ctx'> 			pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;</div><div class='ctx'> 			pipes[pipe_cnt].pipe.src.source_format = dm_444_32;</div><div class='add'>+			pipes[pipe_cnt].pipe.src.cur0_src_width = 0;</div><div class='add'>+			pipes[pipe_cnt].pipe.src.cur1_src_width = 0;</div><div class='ctx'> 			pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/</div><div class='ctx'> 			pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/</div><div class='ctx'> 			pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/</div><div class='hunk'>@@ -1727,7 +1732,7 @@ void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 			int *out_pipe_cnt,</div><div class='ctx'> 			int *pipe_split_from,</div><div class='ctx'> 			int vlevel,</div><div class='del'>-			bool fast_validate)</div><div class='add'>+			enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int pipe_cnt, i, pipe_idx;</div><div class='ctx'> </div><div class='hunk'>@@ -1774,10 +1779,10 @@ void dcn20_calculate_wm(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	if (pipe_cnt != pipe_idx) {</div><div class='ctx'> 		if (dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes)</div><div class='ctx'> 			pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc,</div><div class='del'>-				context, pipes, fast_validate);</div><div class='add'>+				context, pipes, validate_mode);</div><div class='ctx'> 		else</div><div class='ctx'> 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,</div><div class='del'>-				context, pipes, fast_validate);</div><div class='add'>+				context, pipes, validate_mode);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	*out_pipe_cnt = pipe_cnt;</div><div class='hunk'>@@ -1879,10 +1884,10 @@ void dcn20_update_bounding_box(struct dc *dc,</div><div class='ctx'> 		bb-&gt;clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk &lt; min_dcfclk) ?</div><div class='ctx'> 				min_dcfclk : min_fclk_required_by_uclk;</div><div class='ctx'> </div><div class='del'>-		bb-&gt;clock_limits[i].socclk_mhz = (bb-&gt;clock_limits[i].fabricclk_mhz &gt; max_clocks-&gt;socClockInKhz / 1000) ?</div><div class='add'>+		bb-&gt;clock_limits[i].socclk_mhz = (bb-&gt;clock_limits[i].fabricclk_mhz &gt; max_clocks-&gt;socClockInKhz / 1000.0) ?</div><div class='ctx'> 				max_clocks-&gt;socClockInKhz / 1000 : bb-&gt;clock_limits[i].fabricclk_mhz;</div><div class='ctx'> </div><div class='del'>-		bb-&gt;clock_limits[i].dcfclk_mhz = (bb-&gt;clock_limits[i].fabricclk_mhz &gt; max_clocks-&gt;dcfClockInKhz / 1000) ?</div><div class='add'>+		bb-&gt;clock_limits[i].dcfclk_mhz = (bb-&gt;clock_limits[i].fabricclk_mhz &gt; max_clocks-&gt;dcfClockInKhz / 1000.0) ?</div><div class='ctx'> 				max_clocks-&gt;dcfClockInKhz / 1000 : bb-&gt;clock_limits[i].fabricclk_mhz;</div><div class='ctx'> </div><div class='ctx'> 		bb-&gt;clock_limits[i].dispclk_mhz = max_clocks-&gt;displayClockInKhz / 1000;</div><div class='hunk'>@@ -1914,35 +1919,35 @@ void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,</div><div class='ctx'> </div><div class='ctx'> 	// First pass - cap all clocks higher than the reported max</div><div class='ctx'> 	for (i = 0; i &lt; bb-&gt;num_states; i++) {</div><div class='del'>-		if ((bb-&gt;clock_limits[i].dcfclk_mhz &gt; (max_clocks.dcfClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].dcfclk_mhz &gt; (max_clocks.dcfClockInKhz / 1000.0))</div><div class='ctx'> 				&amp;&amp; max_clocks.dcfClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].dram_speed_mts &gt; (max_clocks.uClockInKhz / 1000) * 16)</div><div class='add'>+		if ((bb-&gt;clock_limits[i].dram_speed_mts &gt; (max_clocks.uClockInKhz / 1000.0) * 16)</div><div class='ctx'> 						&amp;&amp; max_clocks.uClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].fabricclk_mhz &gt; (max_clocks.fabricClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].fabricclk_mhz &gt; (max_clocks.fabricClockInKhz / 1000.0))</div><div class='ctx'> 						&amp;&amp; max_clocks.fabricClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].dispclk_mhz &gt; (max_clocks.displayClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].dispclk_mhz &gt; (max_clocks.displayClockInKhz / 1000.0))</div><div class='ctx'> 						&amp;&amp; max_clocks.displayClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].dppclk_mhz &gt; (max_clocks.dppClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].dppclk_mhz &gt; (max_clocks.dppClockInKhz / 1000.0))</div><div class='ctx'> 						&amp;&amp; max_clocks.dppClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].phyclk_mhz &gt; (max_clocks.phyClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].phyclk_mhz &gt; (max_clocks.phyClockInKhz / 1000.0))</div><div class='ctx'> 						&amp;&amp; max_clocks.phyClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].socclk_mhz &gt; (max_clocks.socClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].socclk_mhz &gt; (max_clocks.socClockInKhz / 1000.0))</div><div class='ctx'> 						&amp;&amp; max_clocks.socClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);</div><div class='ctx'> </div><div class='del'>-		if ((bb-&gt;clock_limits[i].dscclk_mhz &gt; (max_clocks.dscClockInKhz / 1000))</div><div class='add'>+		if ((bb-&gt;clock_limits[i].dscclk_mhz &gt; (max_clocks.dscClockInKhz / 1000.0))</div><div class='ctx'> 						&amp;&amp; max_clocks.dscClockInKhz != 0)</div><div class='ctx'> 			bb-&gt;clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2021,7 +2026,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,</div><div class='del'>-		bool fast_validate, display_e2e_pipe_params_st *pipes)</div><div class='add'>+		enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='hunk'>@@ -2034,7 +2039,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_COUNT();</div><div class='ctx'> </div><div class='del'>-	out = dcn20_fast_validate_bw(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, &amp;vlevel, fast_validate);</div><div class='add'>+	out = dcn20_fast_validate_bw(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, &amp;vlevel, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='ctx'> 		goto validate_out;</div><div class='hunk'>@@ -2044,12 +2049,12 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dcn20_calculate_wm(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, vlevel, fast_validate);</div><div class='add'>+	dcn20_calculate_wm(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, vlevel, validate_mode);</div><div class='ctx'> 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_WATERMARKS();</div><div class='hunk'>@@ -2071,7 +2076,7 @@ validate_out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='del'>-				 bool fast_validate, display_e2e_pipe_params_st *pipes)</div><div class='add'>+				 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes)</div><div class='ctx'> {</div><div class='ctx'> 	bool voltage_supported = false;</div><div class='ctx'> 	bool full_pstate_supported = false;</div><div class='hunk'>@@ -2089,12 +2094,11 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	/*Unsafe due to current pipe merge and split logic*/</div><div class='ctx'> 	ASSERT(context != dc-&gt;current_state);</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='del'>-		return dcn20_validate_bandwidth_internal(dc, context, true, pipes);</div><div class='del'>-	}</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='add'>+		return dcn20_validate_bandwidth_internal(dc, context, validate_mode, pipes);</div><div class='ctx'> </div><div class='ctx'> 	// Best case, we support full UCLK switch latency</div><div class='del'>-	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);</div><div class='add'>+	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);</div><div class='ctx'> 	full_pstate_supported = context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='ctx'> </div><div class='ctx'> 	if (context-&gt;bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||</div><div class='hunk'>@@ -2107,7 +2111,7 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	context-&gt;bw_ctx.dml.soc.dram_clock_change_latency_us = context-&gt;bw_ctx.dml.soc.dummy_pstate_latency_us;</div><div class='ctx'> </div><div class='ctx'> 	memset(pipes, 0, dc-&gt;res_pool-&gt;pipe_count * sizeof(display_e2e_pipe_params_st));</div><div class='del'>-	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);</div><div class='add'>+	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);</div><div class='ctx'> 	dummy_pstate_supported = context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='ctx'> </div><div class='ctx'> 	if (voltage_supported &amp;&amp; (dummy_pstate_supported || !(context-&gt;stream_count))) {</div><div class='hunk'>@@ -2150,14 +2154,14 @@ void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,</div><div class='ctx'> int dcn21_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 					  struct dc_state *context,</div><div class='ctx'> 					  display_e2e_pipe_params_st *pipes,</div><div class='del'>-					  bool fast_validate)</div><div class='add'>+					  enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t pipe_cnt;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='del'>-	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; pipe_cnt; i++) {</div><div class='ctx'> </div><div class='hunk'>@@ -2233,7 +2237,7 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 			int *out_pipe_cnt,</div><div class='ctx'> 			int *pipe_split_from,</div><div class='ctx'> 			int vlevel_req,</div><div class='del'>-			bool fast_validate)</div><div class='add'>+			enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int pipe_cnt, i, pipe_idx;</div><div class='ctx'> 	int vlevel, vlevel_max;</div><div class='hunk'>@@ -2275,10 +2279,10 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	if (pipe_cnt != pipe_idx) {</div><div class='ctx'> 		if (dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes)</div><div class='ctx'> 			pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc,</div><div class='del'>-				context, pipes, fast_validate);</div><div class='add'>+				context, pipes, validate_mode);</div><div class='ctx'> 		else</div><div class='ctx'> 			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,</div><div class='del'>-				context, pipes, fast_validate);</div><div class='add'>+				context, pipes, validate_mode);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	*out_pipe_cnt = pipe_cnt;</div><div class='hunk'>@@ -2313,7 +2317,7 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='del'>-				 bool fast_validate, display_e2e_pipe_params_st *pipes)</div><div class='add'>+				 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='hunk'>@@ -2331,7 +2335,7 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	/*Unsafe due to current pipe merge and split logic*/</div><div class='ctx'> 	ASSERT(context != dc-&gt;current_state);</div><div class='ctx'> </div><div class='del'>-	out = dcn21_fast_validate_bw(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, &amp;vlevel, fast_validate);</div><div class='add'>+	out = dcn21_fast_validate_bw(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, &amp;vlevel, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='ctx'> 		goto validate_out;</div><div class='hunk'>@@ -2341,12 +2345,12 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dcn21_calculate_wm(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, vlevel, fast_validate);</div><div class='add'>+	dcn21_calculate_wm(dc, context, pipes, &amp;pipe_cnt, pipe_split_from, vlevel, validate_mode);</div><div class='ctx'> 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_WATERMARKS();</div><div class='hunk'>@@ -2369,7 +2373,7 @@ validate_out:</div><div class='ctx'> </div><div class='ctx'> static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)</div><div class='ctx'> {</div><div class='del'>-	struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;</div><div class='add'>+	struct _vcs_dpi_voltage_scaling_st low_pstate_lvl = {0};</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	low_pstate_lvl.state = 1;</div><div class='hunk'>@@ -2474,7 +2478,7 @@ void dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc,</div><div class='ctx'> 	int pipe_cnt, i, j;</div><div class='ctx'> 	double max_calc_writeback_dispclk;</div><div class='ctx'> 	double writeback_dispclk;</div><div class='del'>-	struct writeback_st dout_wb;</div><div class='add'>+	struct writeback_st dout_wb = {0};</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h<br/>index b6c34198ddc8..aed00039ca62 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h</a></div><div class='hunk'>@@ -44,14 +44,14 @@ void dcn20_calculate_dlg_params(struct dc *dc,</div><div class='ctx'> int dcn20_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 					  struct dc_state *context,</div><div class='ctx'> 					  display_e2e_pipe_params_st *pipes,</div><div class='del'>-					  bool fast_validate);</div><div class='add'>+					  enum dc_validate_mode validate_mode);</div><div class='ctx'> void dcn20_calculate_wm(struct dc *dc,</div><div class='ctx'> 			struct dc_state *context,</div><div class='ctx'> 			display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 			int *out_pipe_cnt,</div><div class='ctx'> 			int *pipe_split_from,</div><div class='ctx'> 			int vlevel,</div><div class='del'>-			bool fast_validate);</div><div class='add'>+			enum dc_validate_mode validate_mode);</div><div class='ctx'> void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,</div><div class='ctx'> 			  struct pp_smu_nv_clock_table max_clocks);</div><div class='ctx'> void dcn20_update_bounding_box(struct dc *dc,</div><div class='hunk'>@@ -62,7 +62,7 @@ void dcn20_update_bounding_box(struct dc *dc,</div><div class='ctx'> void dcn20_patch_bounding_box(struct dc *dc,</div><div class='ctx'> 			      struct _vcs_dpi_soc_bounding_box_st *bb);</div><div class='ctx'> bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,</div><div class='del'>-				 bool fast_validate, display_e2e_pipe_params_st *pipes);</div><div class='add'>+				 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes);</div><div class='ctx'> void dcn20_fpu_set_wm_ranges(int i,</div><div class='ctx'> 			     struct pp_smu_wm_range_sets *ranges,</div><div class='ctx'> 			     struct _vcs_dpi_soc_bounding_box_st *loaded_bb);</div><div class='hunk'>@@ -75,9 +75,9 @@ void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,</div><div class='ctx'> int dcn21_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 					  struct dc_state *context,</div><div class='ctx'> 					  display_e2e_pipe_params_st *pipes,</div><div class='del'>-					  bool fast_validate);</div><div class='del'>-bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool</div><div class='del'>-				 fast_validate, display_e2e_pipe_params_st *pipes);</div><div class='add'>+					  enum dc_validate_mode validate_mode);</div><div class='add'>+bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum</div><div class='add'>+				 dc_validate_mode, display_e2e_pipe_params_st *pipes);</div><div class='ctx'> void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);</div><div class='ctx'> </div><div class='ctx'> void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c<br/>index 7bf4bb7ad044..0c8c4a080c50 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c</a></div><div class='hunk'>@@ -785,12 +785,9 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBW = 0;</div><div class='hunk'>@@ -1017,7 +1014,7 @@ static unsigned int CalculateVMAndRowBytes(</div><div class='ctx'> 			if (ScanDirection == dm_horz)</div><div class='ctx'> 				FractionOfPTEReturnDrop = 0;</div><div class='ctx'> 			else</div><div class='del'>-				FractionOfPTEReturnDrop = 7 / 8;</div><div class='add'>+				FractionOfPTEReturnDrop = 7.0 / 8;</div><div class='ctx'> 		} else if (VMMPageSize == 4096 &amp;&amp; MacroTileSizeBytes &gt; 4096) {</div><div class='ctx'> 			PixelPTEReqHeight = 16 * BlockHeight256Bytes;</div><div class='ctx'> 			PixelPTEReqWidth = 16 * BlockWidth256Bytes;</div><div class='hunk'>@@ -3231,22 +3228,22 @@ static unsigned int TruncToValidBPP(</div><div class='ctx'> 			if (Format == dm_420) {</div><div class='ctx'> 				if (DecimalBPP &lt; 6)</div><div class='ctx'> 					return BPP_INVALID;</div><div class='del'>-				else if (DecimalBPP &gt;= 1.5 * DSCInputBitPerComponent - 1 / 16)</div><div class='del'>-					return 1.5 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+				else if (DecimalBPP &gt;= 1.5 * DSCInputBitPerComponent - 1.0 / 16)</div><div class='add'>+					return 1.5 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 				else</div><div class='ctx'> 					return dml_floor(16 * DecimalBPP, 1) / 16;</div><div class='ctx'> 			} else if (Format == dm_n422) {</div><div class='ctx'> 				if (DecimalBPP &lt; 7)</div><div class='ctx'> 					return BPP_INVALID;</div><div class='del'>-				else if (DecimalBPP &gt;= 2 * DSCInputBitPerComponent - 1 / 16)</div><div class='del'>-					return 2 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+				else if (DecimalBPP &gt;= 2 * DSCInputBitPerComponent - 1.0 / 16)</div><div class='add'>+					return 2 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 				else</div><div class='ctx'> 					return dml_floor(16 * DecimalBPP, 1) / 16;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				if (DecimalBPP &lt; 8)</div><div class='ctx'> 					return BPP_INVALID;</div><div class='del'>-				else if (DecimalBPP &gt;= 3 * DSCInputBitPerComponent - 1 / 16)</div><div class='del'>-					return 3 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+				else if (DecimalBPP &gt;= 3 * DSCInputBitPerComponent - 1.0 / 16)</div><div class='add'>+					return 3 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 				else</div><div class='ctx'> 					return dml_floor(16 * DecimalBPP, 1) / 16;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -4322,7 +4319,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 					locals-&gt;RoundedUpMaxSwathSizeBytesC = 0;</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='del'>-				if (locals-&gt;RoundedUpMaxSwathSizeBytesY + locals-&gt;RoundedUpMaxSwathSizeBytesC &lt;= locals-&gt;DETBufferSizeInKByte[0] * 1024 / 2) {</div><div class='add'>+				if (locals-&gt;RoundedUpMaxSwathSizeBytesY + locals-&gt;RoundedUpMaxSwathSizeBytesC &lt;= locals-&gt;DETBufferSizeInKByte[0] * 1024.0 / 2) {</div><div class='ctx'> 					locals-&gt;SwathHeightYPerState[i][j][k] = locals-&gt;MaxSwathHeightY[k];</div><div class='ctx'> 					locals-&gt;SwathHeightCPerState[i][j][k] = locals-&gt;MaxSwathHeightC[k];</div><div class='ctx'> 				} else {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c<br/>index 989d83ee3842..c935903b68e1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c</a></div><div class='hunk'>@@ -845,12 +845,9 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBW = 0;</div><div class='hunk'>@@ -1077,7 +1074,7 @@ static unsigned int CalculateVMAndRowBytes(</div><div class='ctx'> 			if (ScanDirection == dm_horz)</div><div class='ctx'> 				FractionOfPTEReturnDrop = 0;</div><div class='ctx'> 			else</div><div class='del'>-				FractionOfPTEReturnDrop = 7 / 8;</div><div class='add'>+				FractionOfPTEReturnDrop = 7.0 / 8;</div><div class='ctx'> 		} else if (VMMPageSize == 4096 &amp;&amp; MacroTileSizeBytes &gt; 4096) {</div><div class='ctx'> 			PixelPTEReqHeight = 16 * BlockHeight256Bytes;</div><div class='ctx'> 			PixelPTEReqWidth = 16 * BlockWidth256Bytes;</div><div class='hunk'>@@ -4443,7 +4440,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode</div><div class='ctx'> 					locals-&gt;RoundedUpMaxSwathSizeBytesC = 0;</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='del'>-				if (locals-&gt;RoundedUpMaxSwathSizeBytesY + locals-&gt;RoundedUpMaxSwathSizeBytesC &lt;= locals-&gt;DETBufferSizeInKByte[0] * 1024 / 2) {</div><div class='add'>+				if (locals-&gt;RoundedUpMaxSwathSizeBytesY + locals-&gt;RoundedUpMaxSwathSizeBytesC &lt;= locals-&gt;DETBufferSizeInKByte[0] * 1024.0 / 2) {</div><div class='ctx'> 					locals-&gt;SwathHeightYPerState[i][j][k] = locals-&gt;MaxSwathHeightY[k];</div><div class='ctx'> 					locals-&gt;SwathHeightCPerState[i][j][k] = locals-&gt;MaxSwathHeightC[k];</div><div class='ctx'> 				} else {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c<br/>index 548cdef8a8ad..9c58ff1069d6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c</a></div><div class='hunk'>@@ -78,7 +78,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,</div><div class='ctx'> </div><div class='ctx'> static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	unsigned int ret_val = 0;</div><div class='add'>+	unsigned int ret_val = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (source_format == dm_444_16) {</div><div class='ctx'> 		if (!is_chroma)</div><div class='hunk'>@@ -313,9 +313,6 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib,</div><div class='ctx'> </div><div class='ctx'> 		if (swath_height_c &gt; 0)</div><div class='ctx'> 			log2_swath_height_c = dml_log2(swath_height_c);</div><div class='del'>-</div><div class='del'>-		if (req128_c &amp;&amp; log2_swath_height_c &gt; 0)</div><div class='del'>-			log2_swath_height_c -= 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rq_param-&gt;dlg.rq_l.swath_height = 1 &lt;&lt; log2_swath_height_l;</div><div class='hunk'>@@ -446,8 +443,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	blk_bytes = surf_linear ?</div><div class='ctx'> 			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);</div><div class='ctx'> 	log2_blk_bytes = dml_log2((double) blk_bytes);</div><div class='del'>-	log2_blk_height = 0;</div><div class='del'>-	log2_blk_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	// remember log rule</div><div class='ctx'> 	// "+" in log is multiply</div><div class='hunk'>@@ -494,8 +489,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 			- log2_meta_req_height;</div><div class='ctx'> 	meta_req_width = 1 &lt;&lt; log2_meta_req_width;</div><div class='ctx'> 	meta_req_height = 1 &lt;&lt; log2_meta_req_height;</div><div class='del'>-	log2_meta_row_height = 0;</div><div class='del'>-	meta_row_width_ub = 0;</div><div class='ctx'> </div><div class='ctx'> 	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.</div><div class='ctx'> 	// calculate upper bound of the meta_row_width</div><div class='hunk'>@@ -653,7 +646,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> </div><div class='ctx'> 	// the dpte_group_bytes is reduced for the specific case of vertical</div><div class='ctx'> 	// access of a tile surface that has dpte request of 8x1 ptes.</div><div class='del'>-	if (!surf_linear &amp; (log2_dpte_req_height_ptes == 0) &amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='add'>+	if (!surf_linear &amp;&amp; (log2_dpte_req_height_ptes == 0) &amp;&amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='ctx'> 		rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 	else</div><div class='ctx'> 		//full size</div><div class='hunk'>@@ -688,12 +681,11 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,</div><div class='ctx'> 		const display_pipe_source_params_st *pipe_src_param,</div><div class='ctx'> 		bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = false;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> </div><div class='ctx'> 	// TODO check if ppe apply for both luma and chroma in 422 case</div><div class='ctx'> 	if (is_chroma) {</div><div class='hunk'>@@ -825,7 +817,6 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	double min_dst_y_ttu_vblank;</div><div class='ctx'> 	unsigned int dlg_vblank_start;</div><div class='ctx'> 	bool dual_plane;</div><div class='del'>-	bool mode_422;</div><div class='ctx'> 	unsigned int access_dir;</div><div class='ctx'> 	unsigned int vp_height_l;</div><div class='ctx'> 	unsigned int vp_width_l;</div><div class='hunk'>@@ -971,7 +962,6 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	// Source</div><div class='ctx'> //             dcc_en              = src.dcc;</div><div class='ctx'> 	dual_plane = is_dual_plane((enum source_format_class)(src-&gt;source_format));</div><div class='del'>-	mode_422 = false; // TODO</div><div class='ctx'> 	access_dir = (src-&gt;source_scan == dm_vert); // vp access direction: horizontal or vertical accessed</div><div class='ctx'> //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);</div><div class='ctx'> //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);</div><div class='hunk'>@@ -1148,18 +1138,8 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	dpte_row_height_l = rq_dlg_param-&gt;rq_l.dpte_row_height;</div><div class='ctx'> 	dpte_row_height_c = rq_dlg_param-&gt;rq_c.dpte_row_height;</div><div class='ctx'> </div><div class='del'>-	if (mode_422) {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 2;</div><div class='del'>-	} else {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 1;</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='add'>+	swath_width_pixels_ub_l = swath_width_ub_l;</div><div class='add'>+	swath_width_pixels_ub_c = swath_width_ub_c;</div><div class='ctx'> </div><div class='ctx'> 	if (htaps_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c<br/>index 0fc9f3e3ffae..570e6e39eb45 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c</a></div><div class='hunk'>@@ -78,7 +78,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,</div><div class='ctx'> </div><div class='ctx'> static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	unsigned int ret_val = 0;</div><div class='add'>+	unsigned int ret_val = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (source_format == dm_444_16) {</div><div class='ctx'> 		if (!is_chroma)</div><div class='hunk'>@@ -313,9 +313,6 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib,</div><div class='ctx'> </div><div class='ctx'> 		if (swath_height_c &gt; 0)</div><div class='ctx'> 			log2_swath_height_c = dml_log2(swath_height_c);</div><div class='del'>-</div><div class='del'>-		if (req128_c &amp;&amp; log2_swath_height_c &gt; 0)</div><div class='del'>-			log2_swath_height_c -= 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rq_param-&gt;dlg.rq_l.swath_height = 1 &lt;&lt; log2_swath_height_l;</div><div class='hunk'>@@ -446,8 +443,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	blk_bytes = surf_linear ?</div><div class='ctx'> 			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);</div><div class='ctx'> 	log2_blk_bytes = dml_log2((double) blk_bytes);</div><div class='del'>-	log2_blk_height = 0;</div><div class='del'>-	log2_blk_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	// remember log rule</div><div class='ctx'> 	// "+" in log is multiply</div><div class='hunk'>@@ -494,8 +489,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 			- log2_meta_req_height;</div><div class='ctx'> 	meta_req_width = 1 &lt;&lt; log2_meta_req_width;</div><div class='ctx'> 	meta_req_height = 1 &lt;&lt; log2_meta_req_height;</div><div class='del'>-	log2_meta_row_height = 0;</div><div class='del'>-	meta_row_width_ub = 0;</div><div class='ctx'> </div><div class='ctx'> 	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.</div><div class='ctx'> 	// calculate upper bound of the meta_row_width</div><div class='hunk'>@@ -653,7 +646,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> </div><div class='ctx'> 	// the dpte_group_bytes is reduced for the specific case of vertical</div><div class='ctx'> 	// access of a tile surface that has dpte request of 8x1 ptes.</div><div class='del'>-	if (!surf_linear &amp; (log2_dpte_req_height_ptes == 0) &amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='add'>+	if (!surf_linear &amp;&amp; (log2_dpte_req_height_ptes == 0) &amp;&amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='ctx'> 		rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 	else</div><div class='ctx'> 		//full size</div><div class='hunk'>@@ -688,12 +681,11 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,</div><div class='ctx'> 		const display_pipe_source_params_st *pipe_src_param,</div><div class='ctx'> 		bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = false;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> </div><div class='ctx'> 	// TODO check if ppe apply for both luma and chroma in 422 case</div><div class='ctx'> 	if (is_chroma) {</div><div class='hunk'>@@ -825,7 +817,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	double min_dst_y_ttu_vblank;</div><div class='ctx'> 	unsigned int dlg_vblank_start;</div><div class='ctx'> 	bool dual_plane;</div><div class='del'>-	bool mode_422;</div><div class='ctx'> 	unsigned int access_dir;</div><div class='ctx'> 	unsigned int vp_height_l;</div><div class='ctx'> 	unsigned int vp_width_l;</div><div class='hunk'>@@ -972,7 +963,6 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	// Source</div><div class='ctx'> //             dcc_en              = src.dcc;</div><div class='ctx'> 	dual_plane = is_dual_plane((enum source_format_class)(src-&gt;source_format));</div><div class='del'>-	mode_422 = false; // TODO</div><div class='ctx'> 	access_dir = (src-&gt;source_scan == dm_vert); // vp access direction: horizontal or vertical accessed</div><div class='ctx'> //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);</div><div class='ctx'> //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);</div><div class='hunk'>@@ -1149,18 +1139,8 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	dpte_row_height_l = rq_dlg_param-&gt;rq_l.dpte_row_height;</div><div class='ctx'> 	dpte_row_height_c = rq_dlg_param-&gt;rq_c.dpte_row_height;</div><div class='ctx'> </div><div class='del'>-	if (mode_422) {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 2;</div><div class='del'>-	} else {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 1;</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='add'>+	swath_width_pixels_ub_l = swath_width_ub_l;</div><div class='add'>+	swath_width_pixels_ub_c = swath_width_ub_c;</div><div class='ctx'> </div><div class='ctx'> 	if (htaps_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c<br/>index 57cf0358cc43..cd8cca651419 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c</a></div><div class='hunk'>@@ -1049,12 +1049,9 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBWLuma = 0;</div><div class='hunk'>@@ -1399,7 +1396,7 @@ static unsigned int CalculateVMAndRowBytes(</div><div class='ctx'> 			if (ScanDirection == dm_horz)</div><div class='ctx'> 				FractionOfPTEReturnDrop = 0;</div><div class='ctx'> 			else</div><div class='del'>-				FractionOfPTEReturnDrop = 7 / 8;</div><div class='add'>+				FractionOfPTEReturnDrop = 7.0 / 8;</div><div class='ctx'> 		} else if (VMMPageSize == 4096 &amp;&amp; MacroTileSizeBytes &gt; 4096) {</div><div class='ctx'> 			PixelPTEReqHeightPTEs = 16;</div><div class='ctx'> 			*PixelPTEReqHeight = 16 * BlockHeight256Bytes;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c<br/>index 618f4b682ab1..f549da082c01 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c</a></div><div class='hunk'>@@ -53,7 +53,7 @@ static void calculate_ttu_cursor(</div><div class='ctx'> </div><div class='ctx'> static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	unsigned int ret_val = 0;</div><div class='add'>+	unsigned int ret_val = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (source_format == dm_444_16) {</div><div class='ctx'> 		if (!is_chroma)</div><div class='hunk'>@@ -297,9 +297,6 @@ static void handle_det_buf_split(</div><div class='ctx'> </div><div class='ctx'> 		if (swath_height_c &gt; 0)</div><div class='ctx'> 			log2_swath_height_c = dml_log2(swath_height_c);</div><div class='del'>-</div><div class='del'>-		if (req128_c &amp;&amp; log2_swath_height_c &gt; 0)</div><div class='del'>-			log2_swath_height_c -= 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rq_param-&gt;dlg.rq_l.swath_height = 1 &lt;&lt; log2_swath_height_l;</div><div class='hunk'>@@ -438,8 +435,6 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	blk_bytes = surf_linear ?</div><div class='ctx'> 			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);</div><div class='ctx'> 	log2_blk_bytes = dml_log2((double) blk_bytes);</div><div class='del'>-	log2_blk_height = 0;</div><div class='del'>-	log2_blk_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	// remember log rule</div><div class='ctx'> 	// "+" in log is multiply</div><div class='hunk'>@@ -488,8 +483,6 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 			- log2_meta_req_height;</div><div class='ctx'> 	meta_req_width = 1 &lt;&lt; log2_meta_req_width;</div><div class='ctx'> 	meta_req_height = 1 &lt;&lt; log2_meta_req_height;</div><div class='del'>-	log2_meta_row_height = 0;</div><div class='del'>-	meta_row_width_ub = 0;</div><div class='ctx'> </div><div class='ctx'> 	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.</div><div class='ctx'> 	// calculate upper bound of the meta_row_width</div><div class='hunk'>@@ -659,7 +652,7 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	if (hostvm_enable)</div><div class='ctx'> 		rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 	else {</div><div class='del'>-		if (!surf_linear &amp; (log2_dpte_req_height_ptes == 0) &amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='add'>+		if (!surf_linear &amp;&amp; (log2_dpte_req_height_ptes == 0) &amp;&amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 		else</div><div class='ctx'> 			//full size</div><div class='hunk'>@@ -697,12 +690,11 @@ static void get_surf_rq_param(</div><div class='ctx'> 		const display_pipe_params_st *pipe_param,</div><div class='ctx'> 		bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = false;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> </div><div class='ctx'> 	// FIXME check if ppe apply for both luma and chroma in 422 case</div><div class='ctx'> 	if (is_chroma) {</div><div class='hunk'>@@ -871,7 +863,6 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	double min_dst_y_ttu_vblank;</div><div class='ctx'> 	unsigned int dlg_vblank_start;</div><div class='ctx'> 	bool dual_plane;</div><div class='del'>-	bool mode_422;</div><div class='ctx'> 	unsigned int access_dir;</div><div class='ctx'> 	unsigned int vp_height_l;</div><div class='ctx'> 	unsigned int vp_width_l;</div><div class='hunk'>@@ -1023,7 +1014,6 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	// Source</div><div class='ctx'> 	//             dcc_en              = src.dcc;</div><div class='ctx'> 	dual_plane = is_dual_plane((enum source_format_class) (src-&gt;source_format));</div><div class='del'>-	mode_422 = false; // FIXME</div><div class='ctx'> 	access_dir = (src-&gt;source_scan == dm_vert); // vp access direction: horizontal or vertical accessed</div><div class='ctx'> 						    //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);</div><div class='ctx'> 						    //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);</div><div class='hunk'>@@ -1200,18 +1190,8 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	dpte_row_height_l = rq_dlg_param-&gt;rq_l.dpte_row_height;</div><div class='ctx'> 	dpte_row_height_c = rq_dlg_param-&gt;rq_c.dpte_row_height;</div><div class='ctx'> </div><div class='del'>-	if (mode_422) {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 2;</div><div class='del'>-	} else {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 1;</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='add'>+	swath_width_pixels_ub_l = swath_width_ub_l;</div><div class='add'>+	swath_width_pixels_ub_c = swath_width_ub_c;</div><div class='ctx'> </div><div class='ctx'> 	if (hratio_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c<br/>index ccb4ad78f667..e5f5c0663750 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c</a></div><div class='hunk'>@@ -178,89 +178,13 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,</div><div class='del'>-		double vtotal_avg)</div><div class='del'>-{</div><div class='del'>-	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='del'>-	double vtotal_min, vtotal_max;</div><div class='del'>-	double ratio, modulo, phase;</div><div class='del'>-	uint32_t vblank_start;</div><div class='del'>-	uint32_t v_total_mask_value = 0;</div><div class='del'>-</div><div class='del'>-	dc_assert_fp_enabled();</div><div class='del'>-</div><div class='del'>-	/* Compute VTOTAL_MIN and VTOTAL_MAX, so that</div><div class='del'>-	 * VOTAL_MAX - VTOTAL_MIN = 1</div><div class='del'>-	 */</div><div class='del'>-	v_total_mask_value = 16;</div><div class='del'>-	vtotal_min = dcn_bw_floor(vtotal_avg);</div><div class='del'>-	vtotal_max = dcn_bw_ceil(vtotal_avg);</div><div class='del'>-</div><div class='del'>-	/* Check that bottom VBLANK is at least 2 lines tall when running with</div><div class='del'>-	 * VTOTAL_MIN. Note that VTOTAL registers are defined as 'total number</div><div class='del'>-	 * of lines in a frame - 1'.</div><div class='del'>-	 */</div><div class='del'>-	REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START,</div><div class='del'>-		&amp;vblank_start);</div><div class='del'>-	ASSERT(vtotal_min &gt;= vblank_start + 1);</div><div class='del'>-</div><div class='del'>-	/* Special case where the average frame rate can be achieved</div><div class='del'>-	 * without using the DTO</div><div class='del'>-	 */</div><div class='del'>-	if (vtotal_min == vtotal_max) {</div><div class='del'>-		REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);</div><div class='del'>-</div><div class='del'>-		optc-&gt;funcs-&gt;set_vtotal_min_max(optc, 0, 0);</div><div class='del'>-		REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);</div><div class='del'>-		REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);</div><div class='del'>-		REG_UPDATE_3(OTG_V_TOTAL_CONTROL,</div><div class='del'>-			OTG_V_TOTAL_MIN_SEL, 0,</div><div class='del'>-			OTG_V_TOTAL_MAX_SEL, 0,</div><div class='del'>-			OTG_SET_V_TOTAL_MIN_MASK_EN, 0);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ratio = vtotal_max - vtotal_avg;</div><div class='del'>-	modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */</div><div class='del'>-	phase = ratio * modulo;</div><div class='del'>-</div><div class='del'>-	/* Special cases where the DTO phase gets rounded to 0 or</div><div class='del'>-	 * to DTO modulo</div><div class='del'>-	 */</div><div class='del'>-	if (phase &lt;= 0 || phase &gt;= modulo) {</div><div class='del'>-		REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL,</div><div class='del'>-			phase &lt;= 0 ?</div><div class='del'>-				(uint32_t)vtotal_max : (uint32_t)vtotal_min);</div><div class='del'>-		REG_SET(OTG_V_TOTAL_MIN, 0, OTG_V_TOTAL_MIN, 0);</div><div class='del'>-		REG_SET(OTG_V_TOTAL_MAX, 0, OTG_V_TOTAL_MAX, 0);</div><div class='del'>-		REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);</div><div class='del'>-		REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);</div><div class='del'>-		REG_UPDATE_3(OTG_V_TOTAL_CONTROL,</div><div class='del'>-			OTG_V_TOTAL_MIN_SEL, 0,</div><div class='del'>-			OTG_V_TOTAL_MAX_SEL, 0,</div><div class='del'>-			OTG_SET_V_TOTAL_MIN_MASK_EN, 0);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-	REG_UPDATE_6(OTG_V_TOTAL_CONTROL,</div><div class='del'>-		OTG_V_TOTAL_MIN_SEL, 1,</div><div class='del'>-		OTG_V_TOTAL_MAX_SEL, 1,</div><div class='del'>-		OTG_SET_V_TOTAL_MIN_MASK_EN, 1,</div><div class='del'>-		OTG_SET_V_TOTAL_MIN_MASK, v_total_mask_value,</div><div class='del'>-		OTG_VTOTAL_MID_REPLACING_MIN_EN, 0,</div><div class='del'>-		OTG_VTOTAL_MID_REPLACING_MAX_EN, 0);</div><div class='del'>-	REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);</div><div class='del'>-	optc-&gt;funcs-&gt;set_vtotal_min_max(optc, vtotal_min, vtotal_max);</div><div class='del'>-	REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, (uint32_t)phase);</div><div class='del'>-	REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, (uint32_t)modulo);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void dcn30_fpu_populate_dml_writeback_from_context(</div><div class='ctx'> 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)</div><div class='ctx'> {</div><div class='ctx'> 	int pipe_cnt, i, j;</div><div class='ctx'> 	double max_calc_writeback_dispclk;</div><div class='ctx'> 	double writeback_dispclk;</div><div class='del'>-	struct writeback_st dout_wb;</div><div class='add'>+	struct writeback_st dout_wb = {0};</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='hunk'>@@ -387,13 +311,17 @@ void dcn30_fpu_calculate_wm_and_dlg(</div><div class='ctx'> 	double dcfclk = context-&gt;bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];</div><div class='ctx'> 	bool pstate_en = context-&gt;bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;</div><div class='ctx'> 	unsigned int dummy_latency_index = 0;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;</div><div class='del'>-    for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		stream_status = NULL;</div><div class='ctx'> 		if (context-&gt;streams[i])</div><div class='del'>-			context-&gt;streams[i]-&gt;fpo_in_use = false;</div><div class='add'>+			stream_status = dc_state_get_stream_status(context, context-&gt;streams[i]);</div><div class='add'>+		if (stream_status)</div><div class='add'>+			stream_status-&gt;fpo_in_use = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!pstate_en) {</div><div class='hunk'>@@ -411,7 +339,8 @@ void dcn30_fpu_calculate_wm_and_dlg(</div><div class='ctx'> 			 * newly found dummy_latency_index</div><div class='ctx'> 			 */</div><div class='ctx'> 			context-&gt;bw_ctx.dml.soc.dram_clock_change_latency_us = dc-&gt;clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;</div><div class='del'>-			dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, false, true);</div><div class='add'>+			dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel,</div><div class='add'>+				DC_VALIDATE_MODE_AND_PROGRAMMING, true);</div><div class='ctx'> 			maxMpcComb = context-&gt;bw_ctx.dml.vba.maxMpcComb;</div><div class='ctx'> 			dcfclk = context-&gt;bw_ctx.dml.vba.DCFCLKState[vlevel][context-&gt;bw_ctx.dml.vba.maxMpcComb];</div><div class='ctx'> 			pstate_en = context-&gt;bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;</div><div class='hunk'>@@ -702,7 +631,8 @@ int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,</div><div class='ctx'> 	while (dummy_latency_index &lt; max_latency_table_entries) {</div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.dram_clock_change_latency_us =</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;bw_params-&gt;dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;</div><div class='del'>-		dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, false, true);</div><div class='add'>+		dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel,</div><div class='add'>+			DC_VALIDATE_MODE_AND_PROGRAMMING, true);</div><div class='ctx'> </div><div class='ctx'> 		if (context-&gt;bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==</div><div class='ctx'> 			dm_allow_self_refresh_and_mclk_switch)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h<br/>index cab864095ce7..e3b6ad6a8784 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h</a></div><div class='hunk'>@@ -29,9 +29,6 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dcn20/dcn20_optc.h"</div><div class='ctx'> </div><div class='del'>-void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,</div><div class='del'>-		double vtotal_avg);</div><div class='del'>-</div><div class='ctx'> void dcn30_fpu_populate_dml_writeback_from_context(</div><div class='ctx'> 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c<br/>index e7f4a2d491cc..8d24763938ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c</a></div><div class='hunk'>@@ -281,10 +281,10 @@ static void CalculateDynamicMetadataParameters(</div><div class='ctx'> 		double DISPCLK,</div><div class='ctx'> 		double DCFClkDeepSleep,</div><div class='ctx'> 		double PixelClock,</div><div class='del'>-		long HTotal,</div><div class='del'>-		long VBlank,</div><div class='del'>-		long DynamicMetadataTransmittedBytes,</div><div class='del'>-		long DynamicMetadataLinesBeforeActiveRequired,</div><div class='add'>+		unsigned int HTotal,</div><div class='add'>+		unsigned int VBlank,</div><div class='add'>+		unsigned int DynamicMetadataTransmittedBytes,</div><div class='add'>+		int DynamicMetadataLinesBeforeActiveRequired,</div><div class='ctx'> 		int InterlaceEnable,</div><div class='ctx'> 		bool ProgressiveToInterlaceUnitInOPP,</div><div class='ctx'> 		double *Tsetup,</div><div class='hunk'>@@ -1002,6 +1002,7 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime</div><div class='ctx'> 			- (*DSTYAfterScaler + *DSTXAfterScaler / myPipe-&gt;HTotal);</div><div class='add'>+	dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH</div><div class='ctx'> </div><div class='ctx'> 	Lsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC);</div><div class='ctx'> 	Tsw_oto = Lsw_oto * LineTime;</div><div class='hunk'>@@ -1280,12 +1281,9 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBWLuma = 0;</div><div class='hunk'>@@ -1775,15 +1773,6 @@ static unsigned int CalculateVMAndRowBytes(</div><div class='ctx'> 		*PixelPTEReqWidth = 32768.0 / BytePerPixel;</div><div class='ctx'> 		*PTERequestSize = 64;</div><div class='ctx'> 		FractionOfPTEReturnDrop = 0;</div><div class='del'>-	} else if (MacroTileSizeBytes == 4096) {</div><div class='del'>-		PixelPTEReqHeightPTEs = 1;</div><div class='del'>-		*PixelPTEReqHeight = MacroTileHeight;</div><div class='del'>-		*PixelPTEReqWidth = 8 * *MacroTileWidth;</div><div class='del'>-		*PTERequestSize = 64;</div><div class='del'>-		if (ScanDirection != dm_vert)</div><div class='del'>-			FractionOfPTEReturnDrop = 0;</div><div class='del'>-		else</div><div class='del'>-			FractionOfPTEReturnDrop = 7 / 8;</div><div class='ctx'> 	} else if (GPUVMMinPageSize == 4 &amp;&amp; MacroTileSizeBytes &gt; 4096) {</div><div class='ctx'> 		PixelPTEReqHeightPTEs = 16;</div><div class='ctx'> 		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;</div><div class='hunk'>@@ -3277,8 +3266,8 @@ static double CalculateWriteBackDelay(</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> static void CalculateDynamicMetadataParameters(int MaxInterDCNTileRepeaters, double DPPCLK, double DISPCLK,</div><div class='del'>-		double DCFClkDeepSleep, double PixelClock, long HTotal, long VBlank, long DynamicMetadataTransmittedBytes,</div><div class='del'>-		long DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP,</div><div class='add'>+		double DCFClkDeepSleep, double PixelClock, unsigned int HTotal, unsigned int VBlank, unsigned int DynamicMetadataTransmittedBytes,</div><div class='add'>+		int DynamicMetadataLinesBeforeActiveRequired, int InterlaceEnable, bool ProgressiveToInterlaceUnitInOPP,</div><div class='ctx'> 		double *Tsetup, double *Tdmbf, double *Tdmec, double *Tdmsks)</div><div class='ctx'> {</div><div class='ctx'> 	double TotalRepeaterDelayTime = 0;</div><div class='hunk'>@@ -3535,7 +3524,6 @@ static double TruncToValidBPP(</div><div class='ctx'> 			return DesiredBPP;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	return BPP_INVALID;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c<br/>index 0497a5d74a62..4fb37df54d59 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c</a></div><div class='hunk'>@@ -392,8 +392,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	blk_bytes = surf_linear ?</div><div class='ctx'> 		256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);</div><div class='ctx'> 	log2_blk_bytes = dml_log2((double)blk_bytes);</div><div class='del'>-	log2_blk_height = 0;</div><div class='del'>-	log2_blk_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	// remember log rule</div><div class='ctx'> 	// "+" in log is multiply</div><div class='hunk'>@@ -464,8 +462,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 		- log2_meta_req_height;</div><div class='ctx'> 	meta_req_width = 1 &lt;&lt; log2_meta_req_width;</div><div class='ctx'> 	meta_req_height = 1 &lt;&lt; log2_meta_req_height;</div><div class='del'>-	log2_meta_row_height = 0;</div><div class='del'>-	meta_row_width_ub = 0;</div><div class='ctx'> </div><div class='ctx'> 	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.</div><div class='ctx'> 	// calculate upper bound of the meta_row_width</div><div class='hunk'>@@ -624,7 +620,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	if (hostvm_enable)</div><div class='ctx'> 		rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 	else {</div><div class='del'>-		if (!surf_linear &amp; (log2_dpte_req_height_ptes == 0) &amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='add'>+		if (!surf_linear &amp;&amp; (log2_dpte_req_height_ptes == 0) &amp;&amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 		else</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 2048;</div><div class='hunk'>@@ -660,13 +656,12 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	bool is_chroma,</div><div class='ctx'> 	bool is_alpha)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = 0;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='ctx'> 	unsigned int surface_height = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> </div><div class='ctx'> 	// FIXME check if ppe apply for both luma and chroma in 422 case</div><div class='ctx'> 	if (is_chroma | is_alpha) {</div><div class='hunk'>@@ -934,7 +929,6 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	double min_dst_y_ttu_vblank = 0;</div><div class='ctx'> 	unsigned int dlg_vblank_start = 0;</div><div class='ctx'> 	bool dual_plane = false;</div><div class='del'>-	bool mode_422 = false;</div><div class='ctx'> 	unsigned int access_dir = 0;</div><div class='ctx'> 	unsigned int vp_height_l = 0;</div><div class='ctx'> 	unsigned int vp_width_l = 0;</div><div class='hunk'>@@ -1083,7 +1077,6 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	// Source</div><div class='ctx'> 	//			 dcc_en			  = src.dcc;</div><div class='ctx'> 	dual_plane = is_dual_plane((enum source_format_class)(src-&gt;source_format));</div><div class='del'>-	mode_422 = false; // TODO</div><div class='ctx'> 	access_dir = (src-&gt;source_scan == dm_vert); // vp access direction: horizontal or vertical accessed</div><div class='ctx'> 	vp_height_l = src-&gt;viewport_height;</div><div class='ctx'> 	vp_width_l = src-&gt;viewport_width;</div><div class='hunk'>@@ -1301,18 +1294,8 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;</div><div class='ctx'> 	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;</div><div class='ctx'> </div><div class='del'>-	if (mode_422) {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 2;</div><div class='del'>-	} else {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 1;</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='add'>+	swath_width_pixels_ub_l = swath_width_ub_l;</div><div class='add'>+	swath_width_pixels_ub_c = swath_width_ub_c;</div><div class='ctx'> </div><div class='ctx'> 	if (hratio_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='hunk'>@@ -1579,6 +1562,7 @@ static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,</div><div class='ctx'> 	dml_print("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_row_vblank);</div><div class='ctx'> 	dml_print("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_vm_flip    = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_vm_flip);</div><div class='ctx'> 	dml_print("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_row_flip   = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_row_flip);</div><div class='add'>+</div><div class='ctx'> 	disp_dlg_regs-&gt;refcyc_per_pte_group_vblank_l =</div><div class='ctx'> 		(unsigned int)(dst_y_per_row_vblank * (double)htotal</div><div class='ctx'> 			* ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_l);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c<br/>index 6ce90678b33c..1aaa77265eed 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c</a></div><div class='hunk'>@@ -320,13 +320,13 @@ static void calculate_wm_set_for_vlevel(int vlevel,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='add'>+void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='ctx'> {</div><div class='ctx'> 	struct _vcs_dpi_voltage_scaling_st *s = dc-&gt;scratch.update_bw_bounding_box.clock_limits;</div><div class='ctx'> 	struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc-&gt;res_pool);</div><div class='ctx'> 	struct clk_limit_table *clk_table = &amp;bw_params-&gt;clk_table;</div><div class='ctx'> 	unsigned int i, closest_clk_lvl;</div><div class='del'>-	int j;</div><div class='add'>+	int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='hunk'>@@ -338,6 +338,15 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param</div><div class='ctx'> 	dcn3_01_soc.num_chans = bw_params-&gt;num_channels;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(clk_table-&gt;num_entries);</div><div class='add'>+</div><div class='add'>+	/* Prepass to find max clocks independent of voltage level. */</div><div class='add'>+	for (i = 0; i &lt; clk_table-&gt;num_entries; ++i) {</div><div class='add'>+		if (clk_table-&gt;entries[i].dispclk_mhz &gt; max_dispclk_mhz)</div><div class='add'>+			max_dispclk_mhz = clk_table-&gt;entries[i].dispclk_mhz;</div><div class='add'>+		if (clk_table-&gt;entries[i].dppclk_mhz &gt; max_dppclk_mhz)</div><div class='add'>+			max_dppclk_mhz = clk_table-&gt;entries[i].dppclk_mhz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; clk_table-&gt;num_entries; i++) {</div><div class='ctx'> 		/* loop backwards*/</div><div class='ctx'> 		for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j &gt;= 0; j--) {</div><div class='hunk'>@@ -353,8 +362,13 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param</div><div class='ctx'> 		s[i].socclk_mhz = clk_table-&gt;entries[i].socclk_mhz;</div><div class='ctx'> 		s[i].dram_speed_mts = clk_table-&gt;entries[i].memclk_mhz * 2;</div><div class='ctx'> </div><div class='del'>-		s[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;</div><div class='del'>-		s[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;</div><div class='add'>+		/* Clocks independent of voltage level. */</div><div class='add'>+		s[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :</div><div class='add'>+			dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;</div><div class='add'>+</div><div class='add'>+		s[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :</div><div class='add'>+			dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;</div><div class='add'>+</div><div class='ctx'> 		s[i].dram_bw_per_chan_gbps =</div><div class='ctx'> 			dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;</div><div class='ctx'> 		s[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;</div><div class='hunk'>@@ -409,7 +423,7 @@ void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)</div><div class='ctx'> 		dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,</div><div class='add'>+void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 		int pipe_cnt,</div><div class='hunk'>@@ -435,12 +449,12 @@ void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,</div><div class='ctx'> 						&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='ctx'> 	/* WM Set C */</div><div class='ctx'> 	table_entry = &amp;bw_params-&gt;wm_table.entries[WM_C];</div><div class='del'>-	vlevel = min(max(vlevel_req, 2), vlevel_max);</div><div class='add'>+	vlevel = clamp(vlevel_req, 2, vlevel_max);</div><div class='ctx'> 	calculate_wm_set_for_vlevel(vlevel, table_entry, &amp;context-&gt;bw_ctx.bw.dcn.watermarks.c,</div><div class='ctx'> 						&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='ctx'> 	/* WM Set B */</div><div class='ctx'> 	table_entry = &amp;bw_params-&gt;wm_table.entries[WM_B];</div><div class='del'>-	vlevel = min(max(vlevel_req, 1), vlevel_max);</div><div class='add'>+	vlevel = clamp(vlevel_req, 1, vlevel_max);</div><div class='ctx'> 	calculate_wm_set_for_vlevel(vlevel, table_entry, &amp;context-&gt;bw_ctx.bw.dcn.watermarks.b,</div><div class='ctx'> 						&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h<br/>index 774b0fdfc80b..3e103e23dc6f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h</a></div><div class='hunk'>@@ -26,15 +26,14 @@</div><div class='ctx'> #ifndef __DCN301_FPU_H__</div><div class='ctx'> #define __DCN301_FPU_H__</div><div class='ctx'> </div><div class='del'>-void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);</div><div class='add'>+void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);</div><div class='add'>+void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);</div><div class='ctx'> </div><div class='ctx'> void dcn301_fpu_set_wm_ranges(int i,</div><div class='ctx'> 	struct pp_smu_wm_range_sets *ranges,</div><div class='ctx'> 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb);</div><div class='ctx'> </div><div class='del'>-void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);</div><div class='del'>-</div><div class='del'>-void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,</div><div class='add'>+void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 		int pipe_cnt,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c<br/>index e2bcd205aa93..8d7c59ec701d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c</a></div><div class='hunk'>@@ -280,7 +280,7 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p</div><div class='ctx'> 		j = 0;</div><div class='ctx'> 		/* create the final dcfclk and uclk table */</div><div class='ctx'> 		while (i &lt; num_dcfclk_sta_targets &amp;&amp; j &lt; num_uclk_states &amp;&amp; num_states &lt; DC__VOLTAGE_STATES) {</div><div class='del'>-			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j] &amp;&amp; i &lt; num_dcfclk_sta_targets) {</div><div class='add'>+			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j]) {</div><div class='ctx'> 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];</div><div class='ctx'> 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -304,6 +304,16 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p</div><div class='ctx'> 			dram_speed_mts[num_states++] = bw_params-&gt;clk_table.entries[j++].memclk_mhz * 16;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/* bw_params-&gt;clk_table.entries[MAX_NUM_DPM_LVL].</div><div class='add'>+		 * MAX_NUM_DPM_LVL is 8.</div><div class='add'>+		 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].</div><div class='add'>+		 * DC__VOLTAGE_STATES is 40.</div><div class='add'>+		 */</div><div class='add'>+		if (num_states &gt; MAX_NUM_DPM_LVL) {</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		dcn3_02_soc.num_states = num_states;</div><div class='ctx'> 		for (i = 0; i &lt; dcn3_02_soc.num_states; i++) {</div><div class='ctx'> 			dcn3_02_soc.clock_limits[i].state = i;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c<br/>index 3f02bb806d42..b5d3fd4c3694 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c</a></div><div class='hunk'>@@ -285,7 +285,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p</div><div class='ctx'> 		j = 0;</div><div class='ctx'> 		/* create the final dcfclk and uclk table */</div><div class='ctx'> 		while (i &lt; num_dcfclk_sta_targets &amp;&amp; j &lt; num_uclk_states &amp;&amp; num_states &lt; DC__VOLTAGE_STATES) {</div><div class='del'>-			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j] &amp;&amp; i &lt; num_dcfclk_sta_targets) {</div><div class='add'>+			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j]) {</div><div class='ctx'> 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];</div><div class='ctx'> 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -310,6 +310,16 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p</div><div class='ctx'> 			dram_speed_mts[num_states++] = bw_params-&gt;clk_table.entries[j++].memclk_mhz * 16;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/* bw_params-&gt;clk_table.entries[MAX_NUM_DPM_LVL].</div><div class='add'>+		 * MAX_NUM_DPM_LVL is 8.</div><div class='add'>+		 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].</div><div class='add'>+		 * DC__VOLTAGE_STATES is 40.</div><div class='add'>+		 */</div><div class='add'>+		if (num_states &gt; MAX_NUM_DPM_LVL) {</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		dcn3_03_soc.num_states = num_states;</div><div class='ctx'> 		for (i = 0; i &lt; dcn3_03_soc.num_states; i++) {</div><div class='ctx'> 			dcn3_03_soc.clock_limits[i].state = i;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c<br/>index deb6d162a2d5..1a28061bb9ff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c</a></div><div class='hunk'>@@ -291,6 +291,7 @@ static struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = {</div><div class='ctx'> 	.do_urgent_latency_adjustment = false,</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_component_us = 0,</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,</div><div class='add'>+	.dispclk_dppclk_vco_speed_mhz = 2400.0,</div><div class='ctx'> 	.num_chans = 4,</div><div class='ctx'> 	.dummy_pstate_latency_us = 10.0</div><div class='ctx'> };</div><div class='hunk'>@@ -438,6 +439,7 @@ static struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {</div><div class='ctx'> 	.do_urgent_latency_adjustment = false,</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_component_us = 0,</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,</div><div class='add'>+	.dispclk_dppclk_vco_speed_mhz = 2500.0,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,</div><div class='hunk'>@@ -485,6 +487,7 @@ void dcn31_calculate_wm_and_dlg_fp(</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_idx, total_det = 0, active_hubp_count = 0;</div><div class='ctx'> 	double dcfclk = context-&gt;bw_ctx.dml.vba.DCFCLKState[vlevel][context-&gt;bw_ctx.dml.vba.maxMpcComb];</div><div class='add'>+	uint32_t cstate_enter_plus_exit_z8_ns;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='hunk'>@@ -504,6 +507,13 @@ void dcn31_calculate_wm_and_dlg_fp(</div><div class='ctx'> 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;</div><div class='ctx'> 	pipes[0].clks_cfg.socclk_mhz = context-&gt;bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;</div><div class='ctx'> </div><div class='add'>+	cstate_enter_plus_exit_z8_ns =</div><div class='add'>+		get_wm_z8_stutter_enter_exit(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='add'>+</div><div class='add'>+	if (get_stutter_period(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) &lt; dc-&gt;debug.minimum_z8_residency_time &amp;&amp;</div><div class='add'>+			cstate_enter_plus_exit_z8_ns &lt; dc-&gt;debug.minimum_z8_residency_time * 1000)</div><div class='add'>+		cstate_enter_plus_exit_z8_ns = dc-&gt;debug.minimum_z8_residency_time * 1000;</div><div class='add'>+</div><div class='ctx'> 	/* Set A:</div><div class='ctx'> 	 * All clocks min required</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -514,7 +524,7 @@ void dcn31_calculate_wm_and_dlg_fp(</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='del'>-	context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt) * 1000;</div><div class='hunk'>@@ -637,9 +647,9 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params</div><div class='ctx'> 			dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;</div><div class='ctx'> 		s[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;</div><div class='ctx'> 	}</div><div class='del'>-	if (clk_table-&gt;num_entries) {</div><div class='add'>+</div><div class='add'>+	if (clk_table-&gt;num_entries)</div><div class='ctx'> 		dcn3_1_soc.num_states = clk_table-&gt;num_entries;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(dcn3_1_soc.clock_limits, s, sizeof(dcn3_1_soc.clock_limits));</div><div class='ctx'> </div><div class='hunk'>@@ -752,23 +762,11 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-		// Ported from DCN315</div><div class='del'>-		if (clk_table-&gt;num_entries == 1) {</div><div class='del'>-			/*smu gives one DPM level, let's take the highest one*/</div><div class='del'>-			closest_clk_lvl = dcn3_16_soc.num_states - 1;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		s[i].state = i;</div><div class='ctx'> </div><div class='ctx'> 		/* Clocks dependent on voltage level. */</div><div class='ctx'> 		s[i].dcfclk_mhz = clk_table-&gt;entries[i].dcfclk_mhz;</div><div class='del'>-		if (clk_table-&gt;num_entries == 1 &amp;&amp;</div><div class='del'>-		    s[i].dcfclk_mhz &lt;</div><div class='del'>-		    dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {</div><div class='del'>-			/*SMU fix not released yet*/</div><div class='del'>-			s[i].dcfclk_mhz =</div><div class='del'>-				dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;</div><div class='del'>-		}</div><div class='ctx'> 		s[i].fabricclk_mhz = clk_table-&gt;entries[i].fclk_mhz;</div><div class='ctx'> 		s[i].socclk_mhz = clk_table-&gt;entries[i].socclk_mhz;</div><div class='ctx'> 		s[i].dram_speed_mts = clk_table-&gt;entries[i].memclk_mhz *</div><div class='hunk'>@@ -789,9 +787,9 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param</div><div class='ctx'> 			dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;</div><div class='ctx'> 		s[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;</div><div class='ctx'> 	}</div><div class='del'>-	if (clk_table-&gt;num_entries) {</div><div class='add'>+</div><div class='add'>+	if (clk_table-&gt;num_entries)</div><div class='ctx'> 		dcn3_16_soc.num_states = clk_table-&gt;num_entries;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(dcn3_16_soc.clock_limits, s, sizeof(dcn3_16_soc.clock_limits));</div><div class='ctx'> </div><div class='hunk'>@@ -810,6 +808,8 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param</div><div class='ctx'> </div><div class='ctx'> int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc)</div><div class='ctx'> {</div><div class='add'>+	dc_assert_fp_enabled();</div><div class='add'>+</div><div class='ctx'> 	return soc-&gt;clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc-&gt;dcn_downspread_percent / 100.0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -817,6 +817,8 @@ int dcn_get_approx_det_segs_required_for_pstate(</div><div class='ctx'> 		struct _vcs_dpi_soc_bounding_box_st *soc,</div><div class='ctx'> 		int pix_clk_100hz, int bpp, int seg_size_kb)</div><div class='ctx'> {</div><div class='add'>+	dc_assert_fp_enabled();</div><div class='add'>+</div><div class='ctx'> 	/* Roughly calculate required crb to hide latency. In practice there is slightly</div><div class='ctx'> 	 * more buffer available for latency hiding</div><div class='ctx'> 	 */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h<br/>index 8f9c8faed260..dfcc5d50071e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h</a></div><div class='hunk'>@@ -30,6 +30,7 @@</div><div class='ctx'> #define DCN3_15_DEFAULT_DET_SIZE 192</div><div class='ctx'> #define DCN3_15_MIN_COMPBUF_SIZE_KB 128</div><div class='ctx'> #define DCN3_16_DEFAULT_DET_SIZE 192</div><div class='add'>+#define DCN3_16_MIN_COMPBUF_SIZE_KB 128</div><div class='ctx'> </div><div class='ctx'> void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 				  int pipe_cnt);</div><div class='hunk'>@@ -54,5 +55,5 @@ int dcn_get_approx_det_segs_required_for_pstate(</div><div class='ctx'> int dcn31x_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 					  struct dc_state *context,</div><div class='ctx'> 					  display_e2e_pipe_params_st *pipes,</div><div class='del'>-					  bool fast_validate);</div><div class='add'>+					  enum dc_validate_mode validate_mode);</div><div class='ctx'> #endif /* __DCN31_FPU_H__*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c<br/>index adea459e7d36..ed59c77bc6f6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c</a></div><div class='hunk'>@@ -1105,6 +1105,7 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> 	Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;</div><div class='ctx'> 	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto;</div><div class='ctx'> 	dst_y_prefetch_equ =  VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe-&gt;HTotal);</div><div class='add'>+	dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH</div><div class='ctx'> 	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;</div><div class='ctx'> 	Tpre_rounded = dst_y_prefetch_equ * LineTime;</div><div class='ctx'> </div><div class='hunk'>@@ -1444,12 +1445,9 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBWLuma = 0;</div><div class='hunk'>@@ -1924,15 +1922,6 @@ static unsigned int CalculateVMAndRowBytes(</div><div class='ctx'> 		*PixelPTEReqWidth = 32768.0 / BytePerPixel;</div><div class='ctx'> 		*PTERequestSize = 64;</div><div class='ctx'> 		FractionOfPTEReturnDrop = 0;</div><div class='del'>-	} else if (MacroTileSizeBytes == 4096) {</div><div class='del'>-		PixelPTEReqHeightPTEs = 1;</div><div class='del'>-		*PixelPTEReqHeight = MacroTileHeight;</div><div class='del'>-		*PixelPTEReqWidth = 8 * *MacroTileWidth;</div><div class='del'>-		*PTERequestSize = 64;</div><div class='del'>-		if (ScanDirection != dm_vert)</div><div class='del'>-			FractionOfPTEReturnDrop = 0;</div><div class='del'>-		else</div><div class='del'>-			FractionOfPTEReturnDrop = 7 / 8;</div><div class='ctx'> 	} else if (GPUVMMinPageSize == 4 &amp;&amp; MacroTileSizeBytes &gt; 4096) {</div><div class='ctx'> 		PixelPTEReqHeightPTEs = 16;</div><div class='ctx'> 		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;</div><div class='hunk'>@@ -3617,7 +3606,7 @@ static double TruncToValidBPP(</div><div class='ctx'> 		NonDSCBPP1 = 15;</div><div class='ctx'> 		NonDSCBPP2 = 18;</div><div class='ctx'> 		MinDSCBPP = 6;</div><div class='del'>-		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 	} else if (Format == dm_444) {</div><div class='ctx'> 		NonDSCBPP0 = 24;</div><div class='ctx'> 		NonDSCBPP1 = 30;</div><div class='hunk'>@@ -3679,7 +3668,6 @@ static double TruncToValidBPP(</div><div class='ctx'> 			return DesiredBPP;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	return BPP_INVALID;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static noinline void CalculatePrefetchSchedulePerPlane(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c<br/>index 4113ce79c4af..bfeb01477f0c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c</a></div><div class='hunk'>@@ -413,8 +413,6 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	log2_blk256_height = dml_log2((double) blk256_height);</div><div class='ctx'> 	blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);</div><div class='ctx'> 	log2_blk_bytes = dml_log2((double) blk_bytes);</div><div class='del'>-	log2_blk_height = 0;</div><div class='del'>-	log2_blk_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	// remember log rule</div><div class='ctx'> 	// "+" in log is multiply</div><div class='hunk'>@@ -481,8 +479,6 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height;</div><div class='ctx'> 	meta_req_width = 1 &lt;&lt; log2_meta_req_width;</div><div class='ctx'> 	meta_req_height = 1 &lt;&lt; log2_meta_req_height;</div><div class='del'>-	log2_meta_row_height = 0;</div><div class='del'>-	meta_row_width_ub = 0;</div><div class='ctx'> </div><div class='ctx'> 	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.</div><div class='ctx'> 	// calculate upper bound of the meta_row_width</div><div class='hunk'>@@ -619,7 +615,7 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	if (hostvm_enable)</div><div class='ctx'> 		rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 	else {</div><div class='del'>-		if (!surf_linear &amp; (log2_dpte_req_height_ptes == 0) &amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='add'>+		if (!surf_linear &amp;&amp; (log2_dpte_req_height_ptes == 0) &amp;&amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 		else</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 2048;</div><div class='hunk'>@@ -655,13 +651,12 @@ static void get_surf_rq_param(</div><div class='ctx'> 		bool is_chroma,</div><div class='ctx'> 		bool is_alpha)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = 0;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='ctx'> 	unsigned int surface_height = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> </div><div class='ctx'> 	// FIXME check if ppe apply for both luma and chroma in 422 case</div><div class='ctx'> 	if (is_chroma | is_alpha) {</div><div class='hunk'>@@ -888,7 +883,6 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	double min_ttu_vblank;</div><div class='ctx'> 	unsigned int dlg_vblank_start;</div><div class='ctx'> 	bool dual_plane;</div><div class='del'>-	bool mode_422;</div><div class='ctx'> 	unsigned int access_dir;</div><div class='ctx'> 	unsigned int vp_height_l;</div><div class='ctx'> 	unsigned int vp_width_l;</div><div class='hunk'>@@ -1004,7 +998,6 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	// Prefetch Calc</div><div class='ctx'> 	// Source</div><div class='ctx'> 	dual_plane = is_dual_plane((enum source_format_class) (src-&gt;source_format));</div><div class='del'>-	mode_422 = 0;</div><div class='ctx'> 	access_dir = (src-&gt;source_scan == dm_vert);	// vp access direction: horizontal or vertical accessed</div><div class='ctx'> 	vp_height_l = src-&gt;viewport_height;</div><div class='ctx'> 	vp_width_l = src-&gt;viewport_width;</div><div class='hunk'>@@ -1142,18 +1135,8 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	dpte_row_height_l = rq_dlg_param-&gt;rq_l.dpte_row_height;</div><div class='ctx'> 	dpte_row_height_c = rq_dlg_param-&gt;rq_c.dpte_row_height;</div><div class='ctx'> </div><div class='del'>-	if (mode_422) {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 2;</div><div class='del'>-	} else {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 1;</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='add'>+	swath_width_pixels_ub_l = swath_width_ub_l;</div><div class='add'>+	swath_width_pixels_ub_c = swath_width_ub_c;</div><div class='ctx'> </div><div class='ctx'> 	if (hratio_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c<br/>index fb21572750e8..df9d50b9b57c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c</a></div><div class='hunk'>@@ -306,17 +306,17 @@ static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)</div><div class='ctx'> </div><div class='ctx'> int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 					       display_e2e_pipe_params_st *pipes,</div><div class='del'>-					       bool fast_validate)</div><div class='add'>+					       enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct pipe_ctx *pipe = 0;</div><div class='ctx'> 	bool upscaled = false;</div><div class='ctx'> 	const unsigned int max_allowed_vblank_nom = 1023;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='del'>-	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct dc_crtc_timing *timing;</div><div class='hunk'>@@ -409,6 +409,9 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c</div><div class='ctx'> 		context-&gt;bw_ctx.dml.ip.det_buffer_size_kbytes = 192;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;debug.force_odm_combine_4to1)</div><div class='add'>+		context-&gt;bw_ctx.dml.ip.odm_combine_4to1_supported = true;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h<br/>index d32c5bb99f4c..362ac79184ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h</a></div><div class='hunk'>@@ -35,6 +35,6 @@</div><div class='ctx'> void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);</div><div class='ctx'> int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 					       display_e2e_pipe_params_st *pipes,</div><div class='del'>-					       bool fast_validate);</div><div class='add'>+					       enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c<br/>index 88e56889a68c..9f3938a50240 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c</a></div><div class='hunk'>@@ -24,10 +24,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#define UNIT_TEST 0</div><div class='del'>-#if !UNIT_TEST</div><div class='ctx'> #include "dc.h"</div><div class='del'>-#endif</div><div class='ctx'> #include "../display_mode_lib.h"</div><div class='ctx'> #include "display_mode_vba_314.h"</div><div class='ctx'> #include "../dml_inline_defs.h"</div><div class='hunk'>@@ -1126,6 +1123,7 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> 	Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;</div><div class='ctx'> 	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto;</div><div class='ctx'> 	dst_y_prefetch_equ =  VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe-&gt;HTotal);</div><div class='add'>+	dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH</div><div class='ctx'> 	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;</div><div class='ctx'> 	Tpre_rounded = dst_y_prefetch_equ * LineTime;</div><div class='ctx'> </div><div class='hunk'>@@ -1464,12 +1462,9 @@ static bool CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBWLuma = 0;</div><div class='hunk'>@@ -1944,15 +1939,6 @@ static unsigned int CalculateVMAndRowBytes(</div><div class='ctx'> 		*PixelPTEReqWidth = 32768.0 / BytePerPixel;</div><div class='ctx'> 		*PTERequestSize = 64;</div><div class='ctx'> 		FractionOfPTEReturnDrop = 0;</div><div class='del'>-	} else if (MacroTileSizeBytes == 4096) {</div><div class='del'>-		PixelPTEReqHeightPTEs = 1;</div><div class='del'>-		*PixelPTEReqHeight = MacroTileHeight;</div><div class='del'>-		*PixelPTEReqWidth = 8 * *MacroTileWidth;</div><div class='del'>-		*PTERequestSize = 64;</div><div class='del'>-		if (ScanDirection != dm_vert)</div><div class='del'>-			FractionOfPTEReturnDrop = 0;</div><div class='del'>-		else</div><div class='del'>-			FractionOfPTEReturnDrop = 7 / 8;</div><div class='ctx'> 	} else if (GPUVMMinPageSize == 4 &amp;&amp; MacroTileSizeBytes &gt; 4096) {</div><div class='ctx'> 		PixelPTEReqHeightPTEs = 16;</div><div class='ctx'> 		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;</div><div class='hunk'>@@ -3726,7 +3712,7 @@ static double TruncToValidBPP(</div><div class='ctx'> 		NonDSCBPP1 = 15;</div><div class='ctx'> 		NonDSCBPP2 = 18;</div><div class='ctx'> 		MinDSCBPP = 6;</div><div class='del'>-		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 	} else if (Format == dm_444) {</div><div class='ctx'> 		NonDSCBPP0 = 24;</div><div class='ctx'> 		NonDSCBPP1 = 30;</div><div class='hunk'>@@ -3788,7 +3774,6 @@ static double TruncToValidBPP(</div><div class='ctx'> 			return DesiredBPP;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	return BPP_INVALID;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static noinline void CalculatePrefetchSchedulePerPlane(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c<br/>index b3e8dc08030c..04df263ff65e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c</a></div><div class='hunk'>@@ -501,8 +501,6 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	log2_blk256_height = dml_log2((double) blk256_height);</div><div class='ctx'> 	blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);</div><div class='ctx'> 	log2_blk_bytes = dml_log2((double) blk_bytes);</div><div class='del'>-	log2_blk_height = 0;</div><div class='del'>-	log2_blk_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	// remember log rule</div><div class='ctx'> 	// "+" in log is multiply</div><div class='hunk'>@@ -569,8 +567,6 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height;</div><div class='ctx'> 	meta_req_width = 1 &lt;&lt; log2_meta_req_width;</div><div class='ctx'> 	meta_req_height = 1 &lt;&lt; log2_meta_req_height;</div><div class='del'>-	log2_meta_row_height = 0;</div><div class='del'>-	meta_row_width_ub = 0;</div><div class='ctx'> </div><div class='ctx'> 	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.</div><div class='ctx'> 	// calculate upper bound of the meta_row_width</div><div class='hunk'>@@ -707,7 +703,7 @@ static void get_meta_and_pte_attr(</div><div class='ctx'> 	if (hostvm_enable)</div><div class='ctx'> 		rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 	else {</div><div class='del'>-		if (!surf_linear &amp; (log2_dpte_req_height_ptes == 0) &amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='add'>+		if (!surf_linear &amp;&amp; (log2_dpte_req_height_ptes == 0) &amp;&amp; surf_vert) //reduced, in this case, will have page fault within a group</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 512;</div><div class='ctx'> 		else</div><div class='ctx'> 			rq_sizing_param-&gt;dpte_group_bytes = 2048;</div><div class='hunk'>@@ -743,13 +739,12 @@ static void get_surf_rq_param(</div><div class='ctx'> 		bool is_chroma,</div><div class='ctx'> 		bool is_alpha)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = 0;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='ctx'> 	unsigned int surface_height = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> </div><div class='ctx'> 	// FIXME check if ppe apply for both luma and chroma in 422 case</div><div class='ctx'> 	if (is_chroma | is_alpha) {</div><div class='hunk'>@@ -973,7 +968,6 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	double min_ttu_vblank;</div><div class='ctx'> 	unsigned int dlg_vblank_start;</div><div class='ctx'> 	bool dual_plane;</div><div class='del'>-	bool mode_422;</div><div class='ctx'> 	unsigned int access_dir;</div><div class='ctx'> 	unsigned int vp_height_l;</div><div class='ctx'> 	unsigned int vp_width_l;</div><div class='hunk'>@@ -1091,7 +1085,6 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	// Prefetch Calc</div><div class='ctx'> 	// Source</div><div class='ctx'> 	dual_plane = is_dual_plane((enum source_format_class) (src-&gt;source_format));</div><div class='del'>-	mode_422 = 0;</div><div class='ctx'> 	access_dir = (src-&gt;source_scan == dm_vert);	// vp access direction: horizontal or vertical accessed</div><div class='ctx'> 	vp_height_l = src-&gt;viewport_height;</div><div class='ctx'> 	vp_width_l = src-&gt;viewport_width;</div><div class='hunk'>@@ -1230,18 +1223,8 @@ static void dml_rq_dlg_get_dlg_params(</div><div class='ctx'> 	dpte_row_height_l = rq_dlg_param-&gt;rq_l.dpte_row_height;</div><div class='ctx'> 	dpte_row_height_c = rq_dlg_param-&gt;rq_c.dpte_row_height;</div><div class='ctx'> </div><div class='del'>-	if (mode_422) {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 2;</div><div class='del'>-	} else {</div><div class='del'>-		swath_width_pixels_ub_l = swath_width_ub_l * 1;</div><div class='del'>-		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='add'>+	swath_width_pixels_ub_l = swath_width_ub_l;</div><div class='add'>+	swath_width_pixels_ub_c = swath_width_ub_c;</div><div class='ctx'> </div><div class='ctx'> 	if (hratio_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c<br/>index a0a65e099104..8a0f128722b0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c</a></div><div class='hunk'>@@ -31,7 +31,7 @@</div><div class='ctx'> // We need this includes for WATERMARKS_* defines</div><div class='ctx'> #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"</div><div class='ctx'> #include "dcn30/dcn30_resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='hunk'>@@ -160,8 +160,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {</div><div class='ctx'> 	.pct_ideal_sdp_bw_after_urgent = 90.0,</div><div class='ctx'> 	.pct_ideal_fabric_bw_after_urgent = 67.0,</div><div class='ctx'> 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,</div><div class='del'>-	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented</div><div class='del'>-	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,</div><div class='ctx'> 	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,</div><div class='ctx'> 	.max_avg_sdp_bw_use_normal_percent = 80.0,</div><div class='ctx'> 	.max_avg_fabric_bw_use_normal_percent = 60.0,</div><div class='hunk'>@@ -180,6 +180,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,</div><div class='add'>+	bool *repopulate_pipes, int *split, bool *merge);</div><div class='add'>+</div><div class='ctx'> void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> {</div><div class='ctx'> 	/* defaults */</div><div class='hunk'>@@ -287,7 +290,7 @@ int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,</div><div class='ctx'> 			vba-&gt;DRAMClockChangeSupport[vlevel][context-&gt;bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;</div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.dram_clock_change_latency_us =</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;bw_params-&gt;dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;</div><div class='del'>-		dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, false);</div><div class='add'>+		dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> </div><div class='ctx'> 		/* for subvp + DRR case, if subvp pipes are still present we support pstate */</div><div class='ctx'> 		if (vba-&gt;DRAMClockChangeSupport[vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_unsupported &amp;&amp;</div><div class='hunk'>@@ -622,7 +625,9 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,</div><div class='ctx'> 		 *   to combine this with SubVP can cause issues with the scheduling).</div><div class='ctx'> 		 * - Not TMZ surface</div><div class='ctx'> 		 */</div><div class='del'>-		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; !dcn32_is_center_timing(pipe) &amp;&amp;</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe &amp;&amp; !dcn32_is_center_timing(pipe) &amp;&amp;</div><div class='add'>+				!pipe-&gt;stream-&gt;hw_cursor_req &amp;&amp;</div><div class='add'>+				!dc_state_get_stream_cursor_subvp_limit(pipe-&gt;stream, context) &amp;&amp;</div><div class='ctx'> 				!(pipe-&gt;stream-&gt;timing.pix_clk_100hz / 10000 &gt; DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &amp;&amp;</div><div class='ctx'> 				(!dcn32_is_psr_capable(pipe) || (context-&gt;stream_count == 1 &amp;&amp; dc-&gt;caps.dmub_caps.subvp_psr)) &amp;&amp;</div><div class='ctx'> 				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &amp;&amp;</div><div class='hunk'>@@ -720,7 +725,7 @@ static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context</div><div class='ctx'>  */</div><div class='ctx'> static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> {</div><div class='del'>-	struct pipe_ctx *subvp_pipes[2];</div><div class='add'>+	struct pipe_ctx *subvp_pipes[2] = {0};</div><div class='ctx'> 	struct dc_stream_state *phantom = NULL;</div><div class='ctx'> 	uint32_t microschedule_lines = 0;</div><div class='ctx'> 	uint32_t index = 0;</div><div class='hunk'>@@ -735,9 +740,9 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		/* Loop to calculate the maximum microschedule time between the two SubVP pipes,</div><div class='ctx'> 		 * and also to store the two main SubVP pipe pointers in subvp_pipes[2].</div><div class='ctx'> 		 */</div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='add'>+		phantom = dc_state_get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='add'>+		if (phantom &amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='ctx'> 			dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='del'>-			phantom = dc_state_get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='ctx'> 			microschedule_lines = (phantom-&gt;timing.v_total - phantom-&gt;timing.v_front_porch) +</div><div class='ctx'> 					phantom-&gt;timing.v_addressable;</div><div class='ctx'> </div><div class='hunk'>@@ -842,8 +847,8 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (subvp_found &amp;&amp; drr_found) {</div><div class='del'>-		phantom_stream = dc_state_get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='add'>+	phantom_stream = dc_state_get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='add'>+	if (phantom_stream &amp;&amp; subvp_found &amp;&amp; drr_found) {</div><div class='ctx'> 		main_timing = &amp;pipe-&gt;stream-&gt;timing;</div><div class='ctx'> 		phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='ctx'> 		drr_timing = &amp;drr_pipe-&gt;stream-&gt;timing;</div><div class='hunk'>@@ -868,8 +873,9 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	 * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,</div><div class='ctx'> 	 * and the max of (VBLANK blanking time, MALL region)).</div><div class='ctx'> 	 */</div><div class='del'>-	if (stretched_drr_us &lt; (1 / (double)drr_timing-&gt;min_refresh_in_uhz) * 1000000 * 1000000 &amp;&amp;</div><div class='del'>-			subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion &gt; 0)</div><div class='add'>+	if (drr_timing &amp;&amp;</div><div class='add'>+	    stretched_drr_us &lt; (1 / (double)drr_timing-&gt;min_refresh_in_uhz) * 1000000 * 1000000 &amp;&amp;</div><div class='add'>+	    subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion &gt; 0)</div><div class='ctx'> 		schedulable = true;</div><div class='ctx'> </div><div class='ctx'> 	return schedulable;</div><div class='hunk'>@@ -934,7 +940,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		if (!subvp_pipe &amp;&amp; pipe_mall_type == SUBVP_MAIN)</div><div class='ctx'> 			subvp_pipe = pipe;</div><div class='ctx'> 	}</div><div class='del'>-	if (found) {</div><div class='add'>+	if (found &amp;&amp; subvp_pipe) {</div><div class='ctx'> 		phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 		main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='ctx'> 		phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='hunk'>@@ -994,7 +1000,7 @@ static bool subvp_subvp_admissable(struct dc *dc,</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='ctx'> 				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='ctx'> 			refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='del'>-				pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+				pipe-&gt;stream-&gt;timing.v_total * (uint64_t)pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 			refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 			refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> </div><div class='hunk'>@@ -1174,6 +1180,9 @@ static void init_pipe_slice_table_from_context(</div><div class='ctx'> 		stream = context-&gt;streams[i];</div><div class='ctx'> 		otg_master = resource_get_otg_master_for_stream(</div><div class='ctx'> 				&amp;context-&gt;res_ctx, stream);</div><div class='add'>+		if (!otg_master)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		count = resource_get_odm_slice_count(otg_master);</div><div class='ctx'> 		update_slice_table_for_stream(table, stream, count);</div><div class='ctx'> </div><div class='hunk'>@@ -1425,13 +1434,14 @@ static bool is_test_pattern_enabled(</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='add'>+static bool dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 				   struct dc_state *context,</div><div class='ctx'> 				   display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 				   int *vlevel,</div><div class='ctx'> 				   int *split,</div><div class='ctx'> 				   bool *merge,</div><div class='del'>-				   int *pipe_cnt)</div><div class='add'>+				   int *pipe_cnt,</div><div class='add'>+				   bool *repopulate_pipes)</div><div class='ctx'> {</div><div class='ctx'> 	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='ctx'> 	unsigned int dc_pipe_idx = 0;</div><div class='hunk'>@@ -1461,9 +1471,15 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 		vba-&gt;VoltageLevel = *vlevel;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Apply split and merge flags before checking for subvp */</div><div class='add'>+	if (!dcn32_apply_merge_split_flags_helper(dc, context, repopulate_pipes, split, merge))</div><div class='add'>+		return false;</div><div class='add'>+	memset(split, 0, MAX_PIPES * sizeof(int));</div><div class='add'>+	memset(merge, 0, MAX_PIPES * sizeof(bool));</div><div class='add'>+</div><div class='ctx'> 	/* Conditions for setting up phantom pipes for SubVP:</div><div class='ctx'> 	 * 1. Not force disable SubVP</div><div class='del'>-	 * 2. Full update (i.e. !fast_validate)</div><div class='add'>+	 * 2. Full update (i.e. DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='ctx'> 	 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)</div><div class='ctx'> 	 * 4. Display configuration passes validation</div><div class='ctx'> 	 * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc-&gt;debug.force_subvp_mclk_switch)</div><div class='hunk'>@@ -1475,19 +1491,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 	    vba-&gt;DRAMClockChangeSupport[*vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_unsupported ||</div><div class='ctx'> 	    dc-&gt;debug.force_subvp_mclk_switch)) {</div><div class='ctx'> </div><div class='del'>-		dcn32_merge_pipes_for_subvp(dc, context);</div><div class='del'>-		memset(merge, 0, MAX_PIPES * sizeof(bool));</div><div class='del'>-</div><div class='ctx'> 		vlevel_temp = *vlevel;</div><div class='del'>-		/* to re-initialize viewport after the pipe merge */</div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-			if (!pipe_ctx-&gt;plane_state || !pipe_ctx-&gt;stream)</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			resource_build_scaling_params(pipe_ctx);</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		while (!found_supported_config &amp;&amp; dcn32_enough_pipes_for_subvp(dc, context) &amp;&amp;</div><div class='ctx'> 			dcn32_assign_subvp_pipe(dc, context, &amp;dc_pipe_idx)) {</div><div class='hunk'>@@ -1513,7 +1517,8 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 			dc-&gt;res_pool-&gt;funcs-&gt;add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);</div><div class='ctx'> </div><div class='del'>-			*pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, false);</div><div class='add'>+			*pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes,</div><div class='add'>+				DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> 			// Populate dppclk to trigger a recalculate in dml_get_voltage_level</div><div class='ctx'> 			// so the phantom pipe DLG params can be assigned correctly.</div><div class='ctx'> 			pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&amp;context-&gt;bw_ctx.dml, pipes, *pipe_cnt, 0);</div><div class='hunk'>@@ -1556,7 +1561,8 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 			dc_state_remove_phantom_streams_and_planes(dc, context);</div><div class='ctx'> 			dc_state_release_phantom_streams_and_planes(dc, context);</div><div class='ctx'> 			vba-&gt;DRAMClockChangeSupport[*vlevel][vba-&gt;maxMpcComb] = dm_dram_clock_change_unsupported;</div><div class='del'>-			*pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, false);</div><div class='add'>+			*pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes,</div><div class='add'>+				DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> </div><div class='ctx'> 			*vlevel = dml_get_voltage_level(&amp;context-&gt;bw_ctx.dml, pipes, *pipe_cnt);</div><div class='ctx'> 			/* This may adjust vlevel and maxMpcComb */</div><div class='hunk'>@@ -1576,8 +1582,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 			 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main</div><div class='ctx'> 			 * and phantom pipes will be split in the regular pipe splitting sequence.</div><div class='ctx'> 			 */</div><div class='del'>-			memset(split, 0, MAX_PIPES * sizeof(int));</div><div class='del'>-			memset(merge, 0, MAX_PIPES * sizeof(bool));</div><div class='ctx'> 			*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);</div><div class='ctx'> 			vba-&gt;VoltageLevel = *vlevel;</div><div class='ctx'> 			// Note: We can't apply the phantom pipes to hardware at this time. We have to wait</div><div class='hunk'>@@ -1590,6 +1594,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 		try_odm_power_optimization_and_revalidate(</div><div class='ctx'> 				dc, context, pipes, split, merge, vlevel, *pipe_cnt);</div><div class='ctx'> </div><div class='add'>+	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)</div><div class='hunk'>@@ -1929,106 +1934,23 @@ static bool dcn32_split_stream_for_mpc_or_odm(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='del'>-				struct dc_state *context,</div><div class='del'>-				display_e2e_pipe_params_st *pipes,</div><div class='del'>-				int *pipe_cnt_out,</div><div class='del'>-				int *vlevel_out,</div><div class='del'>-				bool fast_validate)</div><div class='add'>+static bool dcn32_apply_merge_split_flags_helper(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool *repopulate_pipes,</div><div class='add'>+		int *split,</div><div class='add'>+		bool *merge)</div><div class='ctx'> {</div><div class='del'>-	bool out = false;</div><div class='del'>-	bool repopulate_pipes = false;</div><div class='del'>-	int split[MAX_PIPES] = { 0 };</div><div class='del'>-	bool merge[MAX_PIPES] = { false };</div><div class='add'>+	int i, pipe_idx;</div><div class='ctx'> 	bool newly_split[MAX_PIPES] = { false };</div><div class='del'>-	int pipe_cnt, i, pipe_idx;</div><div class='del'>-	int vlevel = context-&gt;bw_ctx.dml.soc.num_states;</div><div class='ctx'> 	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='ctx'> </div><div class='del'>-	dc_assert_fp_enabled();</div><div class='del'>-</div><div class='del'>-	ASSERT(pipes);</div><div class='del'>-	if (!pipes)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	// For each full update, remove all existing phantom pipes first</div><div class='del'>-	dc_state_remove_phantom_streams_and_planes(dc, context);</div><div class='del'>-	dc_state_release_phantom_streams_and_planes(dc, context);</div><div class='del'>-</div><div class='del'>-	dc-&gt;res_pool-&gt;funcs-&gt;update_soc_for_wm_a(dc, context);</div><div class='del'>-</div><div class='del'>-	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='del'>-</div><div class='del'>-	if (!pipe_cnt) {</div><div class='del'>-		out = true;</div><div class='del'>-		goto validate_out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dml_log_pipe_params(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='del'>-	context-&gt;bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);</div><div class='del'>-</div><div class='del'>-	if (!fast_validate)</div><div class='del'>-		dcn32_full_validate_bw_helper(dc, context, pipes, &amp;vlevel, split, merge, &amp;pipe_cnt);</div><div class='del'>-</div><div class='del'>-	if (fast_validate ||</div><div class='del'>-			(dc-&gt;debug.dml_disallow_alternate_prefetch_modes &amp;&amp;</div><div class='del'>-			(vlevel == context-&gt;bw_ctx.dml.soc.num_states ||</div><div class='del'>-				vba-&gt;DRAMClockChangeSupport[vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_unsupported))) {</div><div class='del'>-		/*</div><div class='del'>-		 * If dml_disallow_alternate_prefetch_modes is false, then we have already</div><div class='del'>-		 * tried alternate prefetch modes during full validation.</div><div class='del'>-		 *</div><div class='del'>-		 * If mode is unsupported or there is no p-state support, then</div><div class='del'>-		 * fall back to favouring voltage.</div><div class='del'>-		 *</div><div class='del'>-		 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try</div><div class='del'>-		 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)</div><div class='del'>-		 */</div><div class='del'>-		context-&gt;bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =</div><div class='del'>-			dm_prefetch_support_none;</div><div class='del'>-</div><div class='del'>-		context-&gt;bw_ctx.dml.validate_max_state = fast_validate;</div><div class='del'>-		vlevel = dml_get_voltage_level(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='del'>-</div><div class='del'>-		context-&gt;bw_ctx.dml.validate_max_state = false;</div><div class='del'>-</div><div class='del'>-		if (vlevel &lt; context-&gt;bw_ctx.dml.soc.num_states) {</div><div class='del'>-			memset(split, 0, sizeof(split));</div><div class='del'>-			memset(merge, 0, sizeof(merge));</div><div class='del'>-			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);</div><div class='del'>-			// dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML</div><div class='del'>-			vba-&gt;VoltageLevel = vlevel;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dml_log_mode_support_params(&amp;context-&gt;bw_ctx.dml);</div><div class='del'>-</div><div class='del'>-	if (vlevel == context-&gt;bw_ctx.dml.soc.num_states)</div><div class='del'>-		goto validate_fail;</div><div class='del'>-</div><div class='del'>-	for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-		struct pipe_ctx *mpo_pipe = pipe-&gt;bottom_pipe;</div><div class='del'>-</div><div class='del'>-		if (!pipe-&gt;stream)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (vba-&gt;ODMCombineEnabled[vba-&gt;pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled</div><div class='del'>-				&amp;&amp; !dc-&gt;config.enable_windowed_mpo_odm</div><div class='del'>-				&amp;&amp; pipe-&gt;plane_state &amp;&amp; mpo_pipe</div><div class='del'>-				&amp;&amp; memcmp(&amp;mpo_pipe-&gt;plane_state-&gt;clip_rect,</div><div class='del'>-						&amp;pipe-&gt;stream-&gt;src,</div><div class='del'>-						sizeof(struct rect)) != 0) {</div><div class='del'>-			ASSERT(mpo_pipe-&gt;plane_state != pipe-&gt;plane_state);</div><div class='del'>-			goto validate_fail;</div><div class='del'>-		}</div><div class='del'>-		pipe_idx++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (dc-&gt;config.enable_windowed_mpo_odm) {</div><div class='del'>-		repopulate_pipes = update_pipes_with_split_flags(</div><div class='del'>-				dc, context, vba, split, merge);</div><div class='add'>+		if (update_pipes_with_split_flags(</div><div class='add'>+			dc, context, vba, split, merge))</div><div class='add'>+			*repopulate_pipes = true;</div><div class='ctx'> 	} else {</div><div class='add'>+</div><div class='ctx'> 		/* the code below will be removed once windowed mpo odm is fully</div><div class='ctx'> 		 * enabled.</div><div class='ctx'> 		 */</div><div class='hunk'>@@ -2085,7 +2007,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 				memset(&amp;pipe-&gt;plane_res, 0, sizeof(pipe-&gt;plane_res));</div><div class='ctx'> 				memset(&amp;pipe-&gt;stream_res, 0, sizeof(pipe-&gt;stream_res));</div><div class='ctx'> 				memset(&amp;pipe-&gt;link_res, 0, sizeof(pipe-&gt;link_res));</div><div class='del'>-				repopulate_pipes = true;</div><div class='add'>+				*repopulate_pipes = true;</div><div class='ctx'> 			} else if (pipe-&gt;top_pipe &amp;&amp; pipe-&gt;top_pipe-&gt;plane_state == pipe-&gt;plane_state) {</div><div class='ctx'> 				struct pipe_ctx *top_pipe = pipe-&gt;top_pipe;</div><div class='ctx'> 				struct pipe_ctx *bottom_pipe = pipe-&gt;bottom_pipe;</div><div class='hunk'>@@ -2101,7 +2023,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 				memset(&amp;pipe-&gt;plane_res, 0, sizeof(pipe-&gt;plane_res));</div><div class='ctx'> 				memset(&amp;pipe-&gt;stream_res, 0, sizeof(pipe-&gt;stream_res));</div><div class='ctx'> 				memset(&amp;pipe-&gt;link_res, 0, sizeof(pipe-&gt;link_res));</div><div class='del'>-				repopulate_pipes = true;</div><div class='add'>+				*repopulate_pipes = true;</div><div class='ctx'> 			} else</div><div class='ctx'> 				ASSERT(0); /* Should never try to merge master pipe */</div><div class='ctx'> </div><div class='hunk'>@@ -2140,15 +2062,15 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 				hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);</div><div class='ctx'> 				ASSERT(hsplit_pipe);</div><div class='ctx'> 				if (!hsplit_pipe)</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> </div><div class='ctx'> 				if (!dcn32_split_stream_for_mpc_or_odm(</div><div class='ctx'> 						dc, &amp;context-&gt;res_ctx,</div><div class='ctx'> 						pipe, hsplit_pipe, odm))</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> </div><div class='ctx'> 				newly_split[hsplit_pipe-&gt;pipe_idx] = true;</div><div class='del'>-				repopulate_pipes = true;</div><div class='add'>+				*repopulate_pipes = true;</div><div class='ctx'> 			}</div><div class='ctx'> 			if (split[i] == 4) {</div><div class='ctx'> 				struct pipe_ctx *pipe_4to1;</div><div class='hunk'>@@ -2163,11 +2085,11 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 				pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);</div><div class='ctx'> 				ASSERT(pipe_4to1);</div><div class='ctx'> 				if (!pipe_4to1)</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> 				if (!dcn32_split_stream_for_mpc_or_odm(</div><div class='ctx'> 						dc, &amp;context-&gt;res_ctx,</div><div class='ctx'> 						pipe, pipe_4to1, odm))</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> 				newly_split[pipe_4to1-&gt;pipe_idx] = true;</div><div class='ctx'> </div><div class='ctx'> 				if (odm &amp;&amp; old_pipe-&gt;next_odm_pipe &amp;&amp; old_pipe-&gt;next_odm_pipe-&gt;next_odm_pipe</div><div class='hunk'>@@ -2182,11 +2104,11 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 				pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);</div><div class='ctx'> 				ASSERT(pipe_4to1);</div><div class='ctx'> 				if (!pipe_4to1)</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> 				if (!dcn32_split_stream_for_mpc_or_odm(</div><div class='ctx'> 						dc, &amp;context-&gt;res_ctx,</div><div class='ctx'> 						hsplit_pipe, pipe_4to1, odm))</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> 				newly_split[pipe_4to1-&gt;pipe_idx] = true;</div><div class='ctx'> 			}</div><div class='ctx'> 			if (odm)</div><div class='hunk'>@@ -2198,11 +2120,124 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 			if (pipe-&gt;plane_state) {</div><div class='ctx'> 				if (!resource_build_scaling_params(pipe))</div><div class='del'>-					goto validate_fail;</div><div class='add'>+					return false;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+			struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx,</div><div class='add'>+					context-&gt;streams[i]);</div><div class='add'>+</div><div class='add'>+			if (otg_master)</div><div class='add'>+				resource_build_test_pattern_params(&amp;context-&gt;res_ctx, otg_master);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='add'>+				struct dc_state *context,</div><div class='add'>+				display_e2e_pipe_params_st *pipes,</div><div class='add'>+				int *pipe_cnt_out,</div><div class='add'>+				int *vlevel_out,</div><div class='add'>+				enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	bool out = false;</div><div class='add'>+	bool repopulate_pipes = false;</div><div class='add'>+	int split[MAX_PIPES] = { 0 };</div><div class='add'>+	bool merge[MAX_PIPES] = { false };</div><div class='add'>+	int pipe_cnt, i, pipe_idx;</div><div class='add'>+	int vlevel = context-&gt;bw_ctx.dml.soc.num_states;</div><div class='add'>+	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='add'>+</div><div class='add'>+	dc_assert_fp_enabled();</div><div class='add'>+</div><div class='add'>+	ASSERT(pipes);</div><div class='add'>+	if (!pipes)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* For each full update, remove all existing phantom pipes first */</div><div class='add'>+	dc_state_remove_phantom_streams_and_planes(dc, context);</div><div class='add'>+	dc_state_release_phantom_streams_and_planes(dc, context);</div><div class='add'>+</div><div class='add'>+	dc-&gt;res_pool-&gt;funcs-&gt;update_soc_for_wm_a(dc, context);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='add'>+		resource_update_pipes_for_stream_with_slice_count(context, dc-&gt;current_state, dc-&gt;res_pool, context-&gt;streams[i], 1);</div><div class='add'>+	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, validate_mode);</div><div class='add'>+</div><div class='add'>+	if (!pipe_cnt) {</div><div class='add'>+		out = true;</div><div class='add'>+		goto validate_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dml_log_pipe_params(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='add'>+	context-&gt;bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);</div><div class='add'>+</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='add'>+		if (!dcn32_full_validate_bw_helper(dc, context, pipes, &amp;vlevel, split, merge,</div><div class='add'>+			&amp;pipe_cnt, &amp;repopulate_pipes))</div><div class='add'>+			goto validate_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING ||</div><div class='add'>+			(dc-&gt;debug.dml_disallow_alternate_prefetch_modes &amp;&amp;</div><div class='add'>+			(vlevel == context-&gt;bw_ctx.dml.soc.num_states ||</div><div class='add'>+				vba-&gt;DRAMClockChangeSupport[vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_unsupported))) {</div><div class='add'>+		/*</div><div class='add'>+		 * If dml_disallow_alternate_prefetch_modes is false, then we have already</div><div class='add'>+		 * tried alternate prefetch modes during full validation.</div><div class='add'>+		 *</div><div class='add'>+		 * If mode is unsupported or there is no p-state support, then</div><div class='add'>+		 * fall back to favouring voltage.</div><div class='add'>+		 *</div><div class='add'>+		 * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try</div><div class='add'>+		 * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)</div><div class='add'>+		 */</div><div class='add'>+		context-&gt;bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =</div><div class='add'>+			dm_prefetch_support_none;</div><div class='add'>+</div><div class='add'>+		context-&gt;bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='add'>+		vlevel = dml_get_voltage_level(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='add'>+</div><div class='add'>+		context-&gt;bw_ctx.dml.validate_max_state = false;</div><div class='add'>+</div><div class='add'>+		if (vlevel &lt; context-&gt;bw_ctx.dml.soc.num_states) {</div><div class='add'>+			memset(split, 0, sizeof(split));</div><div class='add'>+			memset(merge, 0, sizeof(merge));</div><div class='add'>+			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);</div><div class='add'>+			/* dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML */</div><div class='add'>+			vba-&gt;VoltageLevel = vlevel;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dml_log_mode_support_params(&amp;context-&gt;bw_ctx.dml);</div><div class='add'>+</div><div class='add'>+	if (vlevel == context-&gt;bw_ctx.dml.soc.num_states)</div><div class='add'>+		goto validate_fail;</div><div class='add'>+</div><div class='add'>+	for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *mpo_pipe = pipe-&gt;bottom_pipe;</div><div class='add'>+</div><div class='add'>+		if (!pipe-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (vba-&gt;ODMCombineEnabled[vba-&gt;pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled</div><div class='add'>+				&amp;&amp; !dc-&gt;config.enable_windowed_mpo_odm</div><div class='add'>+				&amp;&amp; pipe-&gt;plane_state &amp;&amp; mpo_pipe</div><div class='add'>+				&amp;&amp; memcmp(&amp;mpo_pipe-&gt;plane_state-&gt;clip_rect,</div><div class='add'>+						&amp;pipe-&gt;stream-&gt;src,</div><div class='add'>+						sizeof(struct rect)) != 0) {</div><div class='add'>+			ASSERT(mpo_pipe-&gt;plane_state != pipe-&gt;plane_state);</div><div class='add'>+			goto validate_fail;</div><div class='add'>+		}</div><div class='add'>+		pipe_idx++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dcn32_apply_merge_split_flags_helper(dc, context, &amp;repopulate_pipes, split, merge))</div><div class='add'>+		goto validate_fail;</div><div class='add'>+</div><div class='ctx'> 	/* Actual dsc count per stream dsc validation*/</div><div class='ctx'> 	if (!dcn20_validate_dsc(dc, context)) {</div><div class='ctx'> 		vba-&gt;ValidationStatus[vba-&gt;soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;</div><div class='hunk'>@@ -2214,7 +2249,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 		int flag_vlevel = vlevel;</div><div class='ctx'> 		int i;</div><div class='ctx'> </div><div class='del'>-		pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='add'>+		pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, validate_mode);</div><div class='ctx'> 		if (!dc-&gt;config.enable_windowed_mpo_odm)</div><div class='ctx'> 			dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);</div><div class='ctx'> </div><div class='hunk'>@@ -2284,6 +2319,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	bool need_fclk_lat_as_dummy = false;</div><div class='ctx'> 	bool is_subvp_p_drr = false;</div><div class='ctx'> 	struct dc_stream_state *fpo_candidate_stream = NULL;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='hunk'>@@ -2309,7 +2345,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		}</div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.dram_clock_change_latency_us =</div><div class='ctx'> 							dc-&gt;clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;</div><div class='del'>-		dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, false);</div><div class='add'>+		dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> 		maxMpcComb = context-&gt;bw_ctx.dml.vba.maxMpcComb;</div><div class='ctx'> 		if (is_subvp_p_drr) {</div><div class='ctx'> 			context-&gt;bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;</div><div class='hunk'>@@ -2318,8 +2354,11 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> </div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;</div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		stream_status = NULL;</div><div class='ctx'> 		if (context-&gt;streams[i])</div><div class='del'>-			context-&gt;streams[i]-&gt;fpo_in_use = false;</div><div class='add'>+			stream_status = dc_state_get_stream_status(context, context-&gt;streams[i]);</div><div class='add'>+		if (stream_status)</div><div class='add'>+			stream_status-&gt;fpo_in_use = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!pstate_en || (!dc-&gt;debug.disable_fpo_optimizations &amp;&amp;</div><div class='hunk'>@@ -2327,7 +2366,9 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		/* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */</div><div class='ctx'> 		fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);</div><div class='ctx'> 		if (fpo_candidate_stream) {</div><div class='del'>-			fpo_candidate_stream-&gt;fpo_in_use = true;</div><div class='add'>+			stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);</div><div class='add'>+			if (stream_status)</div><div class='add'>+				stream_status-&gt;fpo_in_use = true;</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -2350,7 +2391,8 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 				context-&gt;bw_ctx.dml.soc.fclk_change_latency_us =</div><div class='ctx'> 						dc-&gt;clk_mgr-&gt;bw_params-&gt;dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;</div><div class='ctx'> 			}</div><div class='del'>-			dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel_temp, false);</div><div class='add'>+			dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel_temp,</div><div class='add'>+				DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> 			if (vlevel_temp &lt; vlevel) {</div><div class='ctx'> 				vlevel = vlevel_temp;</div><div class='ctx'> 				maxMpcComb = context-&gt;bw_ctx.dml.vba.maxMpcComb;</div><div class='hunk'>@@ -2364,11 +2406,15 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 				 */</div><div class='ctx'> 				context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;</div><div class='ctx'> 				for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+					stream_status = NULL;</div><div class='ctx'> 					if (context-&gt;streams[i])</div><div class='del'>-						context-&gt;streams[i]-&gt;fpo_in_use = false;</div><div class='add'>+						stream_status = dc_state_get_stream_status(context, context-&gt;streams[i]);</div><div class='add'>+					if (stream_status)</div><div class='add'>+						stream_status-&gt;fpo_in_use = false;</div><div class='ctx'> 				}</div><div class='ctx'> 				context-&gt;bw_ctx.dml.soc.fclk_change_latency_us = dc-&gt;clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;</div><div class='del'>-				dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, false);</div><div class='add'>+				dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel,</div><div class='add'>+					DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3183,7 +3229,7 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa</div><div class='ctx'> 			j = 0;</div><div class='ctx'> 			// create the final dcfclk and uclk table</div><div class='ctx'> 			while (i &lt; num_dcfclk_sta_targets &amp;&amp; j &lt; num_uclk_states &amp;&amp; num_states &lt; DC__VOLTAGE_STATES) {</div><div class='del'>-				if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j] &amp;&amp; i &lt; num_dcfclk_sta_targets) {</div><div class='add'>+				if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j]) {</div><div class='ctx'> 					dcfclk_mhz[num_states] = dcfclk_sta_targets[i];</div><div class='ctx'> 					dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];</div><div class='ctx'> 				} else {</div><div class='hunk'>@@ -3207,6 +3253,16 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa</div><div class='ctx'> 				dram_speed_mts[num_states++] = bw_params-&gt;clk_table.entries[j++].memclk_mhz * 16;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='add'>+			/* bw_params-&gt;clk_table.entries[MAX_NUM_DPM_LVL].</div><div class='add'>+			 * MAX_NUM_DPM_LVL is 8.</div><div class='add'>+			 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].</div><div class='add'>+			 * DC__VOLTAGE_STATES is 40.</div><div class='add'>+			 */</div><div class='add'>+			if (num_states &gt; MAX_NUM_DPM_LVL) {</div><div class='add'>+				ASSERT(0);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			dcn3_2_soc.num_states = num_states;</div><div class='ctx'> 			for (i = 0; i &lt; dcn3_2_soc.num_states; i++) {</div><div class='ctx'> 				dcn3_2_soc.clock_limits[i].state = i;</div><div class='hunk'>@@ -3345,7 +3401,7 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)</div><div class='ctx'> 		uint32_t height = subvp_active_margin_list.res[i].height;</div><div class='ctx'> </div><div class='ctx'> 		refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='del'>-			pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+			(uint64_t)pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 		refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 		refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> </div><div class='hunk'>@@ -3496,15 +3552,16 @@ void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *co</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: current dc state</div><div class='ctx'>  * @context: new dc state</div><div class='add'>+ * @fpo_candidate_stream: candidate stream to be chosen for FPO</div><div class='ctx'>  * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found"</div><div class='ctx'>  *</div><div class='ctx'>  * Return: True if VACTIVE display is found, false otherwise</div><div class='ctx'>  */</div><div class='del'>-bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us)</div><div class='add'>+bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req_us)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i, pipe_idx;</div><div class='ctx'> 	const struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='del'>-	bool vactive_found = false;</div><div class='add'>+	bool vactive_found = true;</div><div class='ctx'> 	unsigned int blank_us = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -3513,11 +3570,20 @@ bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint</div><div class='ctx'> 		if (!pipe-&gt;stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		/* Don't need to check for vactive margin on the FPO candidate stream */</div><div class='add'>+		if (fpo_candidate_stream &amp;&amp; pipe-&gt;stream == fpo_candidate_stream) {</div><div class='add'>+			pipe_idx++;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Every plane (apart from the ones driven by the FPO pipes) needs to have active margin</div><div class='add'>+		 * in order for us to have found a valid "vactive" config for FPO + Vactive</div><div class='add'>+		 */</div><div class='ctx'> 		blank_us = ((pipe-&gt;stream-&gt;timing.v_total - pipe-&gt;stream-&gt;timing.v_addressable) * pipe-&gt;stream-&gt;timing.h_total /</div><div class='ctx'> 				(double)(pipe-&gt;stream-&gt;timing.pix_clk_100hz * 100)) * 1000000;</div><div class='del'>-		if (vba-&gt;ActiveDRAMClockChangeLatencyMarginPerState[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb][vba-&gt;pipe_plane[pipe_idx]] &gt;= vactive_margin_req_us &amp;&amp;</div><div class='del'>-				!(pipe-&gt;stream-&gt;vrr_active_variable || pipe-&gt;stream-&gt;vrr_active_fixed) &amp;&amp; blank_us &lt; dc-&gt;debug.fpo_vactive_max_blank_us) {</div><div class='del'>-			vactive_found = true;</div><div class='add'>+		if (vba-&gt;ActiveDRAMClockChangeLatencyMarginPerState[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb][vba-&gt;pipe_plane[pipe_idx]] &lt; vactive_margin_req_us ||</div><div class='add'>+				pipe-&gt;stream-&gt;vrr_active_variable || pipe-&gt;stream-&gt;vrr_active_fixed || blank_us &gt;= dc-&gt;debug.fpo_vactive_max_blank_us) {</div><div class='add'>+			vactive_found = false;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		pipe_idx++;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h<br/>index d25c3f730a59..273d2bd79d85 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h</a></div><div class='hunk'>@@ -49,7 +49,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 				display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 				int *pipe_cnt_out,</div><div class='ctx'> 				int *vlevel_out,</div><div class='del'>-				bool fast_validate);</div><div class='add'>+				enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 				display_e2e_pipe_params_st *pipes,</div><div class='hunk'>@@ -71,7 +71,7 @@ void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,</div><div class='ctx'> </div><div class='ctx'> void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream);</div><div class='ctx'> </div><div class='del'>-bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req);</div><div class='add'>+bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, struct dc_stream_state *fpo_candidate_stream, uint32_t vactive_margin_req);</div><div class='ctx'> </div><div class='ctx'> void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c<br/>index 6c84b0fa40f4..0782a34689a0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c</a></div><div class='hunk'>@@ -3364,6 +3364,9 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 							&amp;mode_lib-&gt;vba.UrgentBurstFactorLumaPre[k],</div><div class='ctx'> 							&amp;mode_lib-&gt;vba.UrgentBurstFactorChromaPre[k],</div><div class='ctx'> 							&amp;mode_lib-&gt;vba.NotUrgentLatencyHidingPre[k]);</div><div class='add'>+</div><div class='add'>+					v-&gt;cursor_bw_pre[k] = mode_lib-&gt;vba.NumberOfCursors[k] * mode_lib-&gt;vba.CursorWidth[k][0] * mode_lib-&gt;vba.CursorBPP[k][0] /</div><div class='add'>+							8.0 / (mode_lib-&gt;vba.HTotal[k] / mode_lib-&gt;vba.PixelClock[k]) * v-&gt;VRatioPreY[i][j][k];</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='ctx'> 				{</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c<br/>index 80fccd4999a5..0748ef36a16a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c</a></div><div class='hunk'>@@ -1401,13 +1401,13 @@ void dml32_CalculateOutputLink(</div><div class='ctx'> 			if (Output == dm_dp2p0) {</div><div class='ctx'> 				*OutBpp = 0;</div><div class='ctx'> 				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr10) &amp;&amp;</div><div class='del'>-						PHYCLKD32PerState &gt;= 10000 / 32) {</div><div class='add'>+						PHYCLKD32PerState &gt;= 10000.0 / 32) {</div><div class='ctx'> 					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 10000,</div><div class='ctx'> 							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,</div><div class='ctx'> 							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,</div><div class='ctx'> 							DSCInputBitPerComponent, NumberOfDSCSlices, AudioSampleRate,</div><div class='ctx'> 							AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='del'>-					if (*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &lt; 13500 / 32 &amp;&amp; DSCEnable == true &amp;&amp;</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &lt; 13500.0 / 32 &amp;&amp; DSCEnable == true &amp;&amp;</div><div class='ctx'> 							ForcedOutputLinkBPP == 0) {</div><div class='ctx'> 						*RequiresDSC = true;</div><div class='ctx'> 						LinkDSCEnable = true;</div><div class='hunk'>@@ -1423,7 +1423,7 @@ void dml32_CalculateOutputLink(</div><div class='ctx'> 					*OutputRate = dm_output_rate_dp_rate_uhbr10;</div><div class='ctx'> 				}</div><div class='ctx'> 				if ((OutputLinkDPRate == dm_dp_rate_na || OutputLinkDPRate == dm_dp_rate_uhbr13p5) &amp;&amp;</div><div class='del'>-						*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &gt;= 13500 / 32) {</div><div class='add'>+						*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &gt;= 13500.0 / 32) {</div><div class='ctx'> 					*OutBpp = dml32_TruncToValidBPP((1 - Downspreading / 100) * 13500,</div><div class='ctx'> 							OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd,</div><div class='ctx'> 							ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat,</div><div class='hunk'>@@ -1595,14 +1595,16 @@ double dml32_TruncToValidBPP(</div><div class='ctx'> 	unsigned int   NonDSCBPP0;</div><div class='ctx'> 	unsigned int   NonDSCBPP1;</div><div class='ctx'> 	unsigned int   NonDSCBPP2;</div><div class='add'>+	unsigned int   NonDSCBPP3 = BPP_INVALID;</div><div class='ctx'> </div><div class='ctx'> 	if (Format == dm_420) {</div><div class='ctx'> 		NonDSCBPP0 = 12;</div><div class='ctx'> 		NonDSCBPP1 = 15;</div><div class='ctx'> 		NonDSCBPP2 = 18;</div><div class='ctx'> 		MinDSCBPP = 6;</div><div class='del'>-		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 	} else if (Format == dm_444) {</div><div class='add'>+		NonDSCBPP3 = 18;</div><div class='ctx'> 		NonDSCBPP0 = 24;</div><div class='ctx'> 		NonDSCBPP1 = 30;</div><div class='ctx'> 		NonDSCBPP2 = 36;</div><div class='hunk'>@@ -1650,6 +1652,8 @@ double dml32_TruncToValidBPP(</div><div class='ctx'> 			MaxLinkBPP = 2 * MaxLinkBPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	*RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1);</div><div class='add'>+</div><div class='ctx'> 	if (DesiredBPP == 0) {</div><div class='ctx'> 		if (DSCEnable) {</div><div class='ctx'> 			if (MaxLinkBPP &lt; MinDSCBPP)</div><div class='hunk'>@@ -1665,6 +1669,8 @@ double dml32_TruncToValidBPP(</div><div class='ctx'> 				return NonDSCBPP1;</div><div class='ctx'> 			else if (MaxLinkBPP &gt;= NonDSCBPP0)</div><div class='ctx'> 				return 16.0;</div><div class='add'>+			else if ((Output == dm_dp2p0 || Output == dm_dp) &amp;&amp; NonDSCBPP3 != BPP_INVALID &amp;&amp;  MaxLinkBPP &gt;= NonDSCBPP3)</div><div class='add'>+				return NonDSCBPP3; // Special case to allow 6bpc RGB for DP connections.</div><div class='ctx'> 			else</div><div class='ctx'> 				return BPP_INVALID;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1676,10 +1682,6 @@ double dml32_TruncToValidBPP(</div><div class='ctx'> 		else</div><div class='ctx'> 			return DesiredBPP;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	*RequiredSlots = dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1);</div><div class='del'>-</div><div class='del'>-	return BPP_INVALID;</div><div class='ctx'> } // TruncToValidBPP</div><div class='ctx'> </div><div class='ctx'> double dml32_RequiredDTBCLK(</div><div class='hunk'>@@ -1975,8 +1977,8 @@ void dml32_CalculateVMRowAndSwath(</div><div class='ctx'> 	unsigned int PTEBufferSizeInRequestsForChroma[DC__NUM_DPP__MAX];</div><div class='ctx'> 	unsigned int PDEAndMetaPTEBytesFrameY;</div><div class='ctx'> 	unsigned int PDEAndMetaPTEBytesFrameC;</div><div class='del'>-	unsigned int MetaRowByteY[DC__NUM_DPP__MAX];</div><div class='del'>-	unsigned int MetaRowByteC[DC__NUM_DPP__MAX];</div><div class='add'>+	unsigned int MetaRowByteY[DC__NUM_DPP__MAX] = {0};</div><div class='add'>+	unsigned int MetaRowByteC[DC__NUM_DPP__MAX] = {0};</div><div class='ctx'> 	unsigned int PixelPTEBytesPerRowY[DC__NUM_DPP__MAX];</div><div class='ctx'> 	unsigned int PixelPTEBytesPerRowC[DC__NUM_DPP__MAX];</div><div class='ctx'> 	unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DC__NUM_DPP__MAX];</div><div class='hunk'>@@ -4099,12 +4101,9 @@ bool dml32_CalculatePrefetchSchedule(</div><div class='ctx'> </div><div class='ctx'> 	if (MyError) {</div><div class='ctx'> 		*PrefetchBandwidth = 0;</div><div class='del'>-		TimeForFetchingMetaPTE = 0;</div><div class='del'>-		TimeForFetchingRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesToRequestRowInVBlank = 0;</div><div class='ctx'> 		*DestinationLinesForPrefetch = 0;</div><div class='del'>-		LinesToRequestPrefetchPixelData = 0;</div><div class='ctx'> 		*VRatioPrefetchY = 0;</div><div class='ctx'> 		*VRatioPrefetchC = 0;</div><div class='ctx'> 		*RequiredPrefetchPixDataBWLuma = 0;</div><div class='hunk'>@@ -4291,7 +4290,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(</div><div class='ctx'> 	unsigned int i, j, k;</div><div class='ctx'> 	unsigned int SurfaceWithMinActiveFCLKChangeMargin = 0;</div><div class='ctx'> 	unsigned int DRAMClockChangeSupportNumber = 0;</div><div class='del'>-	unsigned int LastSurfaceWithoutMargin;</div><div class='add'>+	unsigned int LastSurfaceWithoutMargin = 0;</div><div class='ctx'> 	unsigned int DRAMClockChangeMethod = 0;</div><div class='ctx'> 	bool FoundFirstSurfaceWithMinActiveFCLKChangeMargin = false;</div><div class='ctx'> 	double MinActiveFCLKChangeMargin = 0.;</div><div class='hunk'>@@ -5656,9 +5655,9 @@ void dml32_CalculateStutterEfficiency(</div><div class='ctx'> 	double LastZ8StutterPeriod = 0.0;</div><div class='ctx'> 	double LastStutterPeriod = 0.0;</div><div class='ctx'> 	unsigned int TotalNumberOfActiveOTG = 0;</div><div class='del'>-	double doublePixelClock;</div><div class='del'>-	unsigned int doubleHTotal;</div><div class='del'>-	unsigned int doubleVTotal;</div><div class='add'>+	double doublePixelClock = 0;</div><div class='add'>+	unsigned int doubleHTotal = 0;</div><div class='add'>+	unsigned int doubleVTotal = 0;</div><div class='ctx'> 	bool SameTiming = true;</div><div class='ctx'> 	double DETBufferingTimeY;</div><div class='ctx'> 	double SwathWidthYCriticalSurface = 0.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c<br/>index 9ba6cb67655f..6c75aa82327a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c</a></div><div class='hunk'>@@ -139,7 +139,6 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,</div><div class='ctx'> 	if (dual_plane) {</div><div class='ctx'> 		unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param,</div><div class='ctx'> 				num_pipes, pipe_idx);</div><div class='del'>-		;</div><div class='ctx'> 		if (src-&gt;sw_mode == dm_sw_linear)</div><div class='ctx'> 			ASSERT(p1_pte_row_height_linear &gt;= 8);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c<br/>index ff4d795c7966..e0a1dc89ce43 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c</a></div><div class='hunk'>@@ -139,8 +139,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {</div><div class='ctx'> 	.pct_ideal_sdp_bw_after_urgent = 90.0,</div><div class='ctx'> 	.pct_ideal_fabric_bw_after_urgent = 67.0,</div><div class='ctx'> 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,</div><div class='del'>-	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented</div><div class='del'>-	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,</div><div class='ctx'> 	.pct_ideal_dram_bw_after_urgent_strobe = 67.0,</div><div class='ctx'> 	.max_avg_sdp_bw_use_normal_percent = 80.0,</div><div class='ctx'> 	.max_avg_fabric_bw_use_normal_percent = 60.0,</div><div class='hunk'>@@ -779,7 +779,7 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p</div><div class='ctx'> 		j = 0;</div><div class='ctx'> 		// create the final dcfclk and uclk table</div><div class='ctx'> 		while (i &lt; num_dcfclk_sta_targets &amp;&amp; j &lt; num_uclk_states &amp;&amp; num_states &lt; DC__VOLTAGE_STATES) {</div><div class='del'>-			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j] &amp;&amp; i &lt; num_dcfclk_sta_targets) {</div><div class='add'>+			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j]) {</div><div class='ctx'> 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];</div><div class='ctx'> 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -803,6 +803,16 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p</div><div class='ctx'> 			dram_speed_mts[num_states++] = bw_params-&gt;clk_table.entries[j++].memclk_mhz * 16;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/* bw_params-&gt;clk_table.entries[MAX_NUM_DPM_LVL].</div><div class='add'>+		 * MAX_NUM_DPM_LVL is 8.</div><div class='add'>+		 * dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].</div><div class='add'>+		 * DC__VOLTAGE_STATES is 40.</div><div class='add'>+		 */</div><div class='add'>+		if (num_states &gt; MAX_NUM_DPM_LVL) {</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		dcn3_21_soc.num_states = num_states;</div><div class='ctx'> 		for (i = 0; i &lt; dcn3_21_soc.num_states; i++) {</div><div class='ctx'> 			dcn3_21_soc.clock_limits[i].state = i;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c<br/>index 80bebfc268db..817a370e80a7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c</a></div><div class='hunk'>@@ -31,7 +31,7 @@</div><div class='ctx'> #include "dml/dcn31/dcn31_fpu.h"</div><div class='ctx'> #include "dml/dml_inline_defs.h"</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -159,15 +159,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 			.dppclk_mhz = 1200.0,</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='del'>-			.dscclk_mhz = 417.0,</div><div class='add'>+			.dscclk_mhz = 400.0,</div><div class='ctx'> 			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	.num_states = 5,</div><div class='ctx'> 	.sr_exit_time_us = 28.0,</div><div class='ctx'> 	.sr_enter_plus_exit_time_us = 30.0,</div><div class='del'>-	.sr_exit_z8_time_us = 210.0,</div><div class='del'>-	.sr_enter_plus_exit_z8_time_us = 320.0,</div><div class='add'>+	.sr_exit_z8_time_us = 250.0,</div><div class='add'>+	.sr_enter_plus_exit_z8_time_us = 350.0,</div><div class='ctx'> 	.fclk_change_latency_us = 24.0,</div><div class='ctx'> 	.usr_retraining_latency_us = 2,</div><div class='ctx'> 	.writeback_latency_us = 12.0,</div><div class='hunk'>@@ -177,7 +177,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 	.urgent_latency_pixel_data_only_us = 4.0,</div><div class='ctx'> 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,</div><div class='ctx'> 	.urgent_latency_vm_data_only_us = 4.0,</div><div class='del'>-	.dram_clock_change_latency_us = 11.72,</div><div class='add'>+	.dram_clock_change_latency_us = 34.0,</div><div class='ctx'> 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,</div><div class='ctx'> 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,</div><div class='ctx'> 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,</div><div class='hunk'>@@ -367,6 +367,8 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,</div><div class='ctx'> 				clock_limits[i].socclk_mhz;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =</div><div class='ctx'> 				clk_table-&gt;entries[i].memclk_mhz * clk_table-&gt;entries[i].wck_ratio;</div><div class='add'>+</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =</div><div class='ctx'> 				clock_limits[i].dtbclk_mhz;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =</div><div class='hunk'>@@ -435,16 +437,18 @@ static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)</div><div class='ctx'> int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> 					      struct dc_state *context,</div><div class='ctx'> 					      display_e2e_pipe_params_st *pipes,</div><div class='del'>-					      bool fast_validate)</div><div class='add'>+					      enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct pipe_ctx *pipe = 0;</div><div class='ctx'> 	bool upscaled = false;</div><div class='ctx'> 	const unsigned int max_allowed_vblank_nom = 1023;</div><div class='ctx'> </div><div class='add'>+	dc_assert_fp_enabled();</div><div class='add'>+</div><div class='ctx'> 	dcn31_populate_dml_pipes_from_context(dc, context, pipes,</div><div class='del'>-					      fast_validate);</div><div class='add'>+					      validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct dc_crtc_timing *timing;</div><div class='hunk'>@@ -496,9 +500,7 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;</div><div class='ctx'> </div><div class='del'>-		DC_FP_START();</div><div class='ctx'> 		dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);</div><div class='del'>-		DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 		pipes[pipe_cnt].pipe.dest.vfront_porch = timing-&gt;v_front_porch;</div><div class='ctx'> 		pipes[pipe_cnt].pipe.src.dcc_rate = 3;</div><div class='hunk'>@@ -577,6 +579,9 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;</div><div class='ctx'> 	unsigned int i, plane_count = 0;</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='hunk'>@@ -602,11 +607,14 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		if (is_pwrseq0 &amp;&amp; allow_z10)</div><div class='ctx'> 			support = DCN_ZSTATE_SUPPORT_ALLOW;</div><div class='ctx'> 		else if (is_pwrseq0 &amp;&amp; (is_psr || is_replay))</div><div class='del'>-			support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;</div><div class='add'>+			support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;</div><div class='ctx'> 		else if (allow_z8)</div><div class='ctx'> 			support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n", support,</div><div class='add'>+		   (int)context-&gt;bw_ctx.dml.vba.StutterPeriod);</div><div class='add'>+</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.zstate_support = support;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h<br/>index 067480fc3691..d121c5afce71 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h</a></div><div class='hunk'>@@ -37,7 +37,7 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,</div><div class='ctx'> int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> 					      struct dc_state *context,</div><div class='ctx'> 					      display_e2e_pipe_params_st *pipes,</div><div class='del'>-					      bool fast_validate);</div><div class='add'>+					      enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c<br/>index dc9e1b758ed6..77023b619f1e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c</a></div><div class='hunk'>@@ -10,7 +10,7 @@</div><div class='ctx'> #include "dml/dcn35/dcn35_fpu.h"</div><div class='ctx'> #include "dml/dml_inline_defs.h"</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -98,55 +98,114 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {</div><div class='ctx'> 	.clock_limits = {</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 0,</div><div class='del'>-			.dispclk_mhz = 1200.0,</div><div class='del'>-			.dppclk_mhz = 1200.0,</div><div class='add'>+			.dcfclk_mhz = 400.0,</div><div class='add'>+			.fabricclk_mhz = 400.0,</div><div class='add'>+			.socclk_mhz = 600.0,</div><div class='add'>+			.dram_speed_mts = 3200.0,</div><div class='add'>+			.dispclk_mhz = 600.0,</div><div class='add'>+			.dppclk_mhz = 600.0,</div><div class='ctx'> 			.phyclk_mhz = 600.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='del'>-			.dscclk_mhz = 186.0,</div><div class='add'>+			.dscclk_mhz = 200.0,</div><div class='ctx'> 			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 1,</div><div class='del'>-			.dispclk_mhz = 1200.0,</div><div class='del'>-			.dppclk_mhz = 1200.0,</div><div class='add'>+			.dcfclk_mhz = 600.0,</div><div class='add'>+			.fabricclk_mhz = 1000.0,</div><div class='add'>+			.socclk_mhz = 733.0,</div><div class='add'>+			.dram_speed_mts = 6400.0,</div><div class='add'>+			.dispclk_mhz = 800.0,</div><div class='add'>+			.dppclk_mhz = 800.0,</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='del'>-			.dscclk_mhz = 209.0,</div><div class='add'>+			.dscclk_mhz = 266.7,</div><div class='ctx'> 			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 2,</div><div class='del'>-			.dispclk_mhz = 1200.0,</div><div class='del'>-			.dppclk_mhz = 1200.0,</div><div class='add'>+			.dcfclk_mhz = 738.0,</div><div class='add'>+			.fabricclk_mhz = 1200.0,</div><div class='add'>+			.socclk_mhz = 880.0,</div><div class='add'>+			.dram_speed_mts = 7500.0,</div><div class='add'>+			.dispclk_mhz = 800.0,</div><div class='add'>+			.dppclk_mhz = 800.0,</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='del'>-			.dscclk_mhz = 209.0,</div><div class='add'>+			.dscclk_mhz = 266.7,</div><div class='ctx'> 			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 3,</div><div class='del'>-			.dispclk_mhz = 1200.0,</div><div class='del'>-			.dppclk_mhz = 1200.0,</div><div class='add'>+			.dcfclk_mhz = 800.0,</div><div class='add'>+			.fabricclk_mhz = 1400.0,</div><div class='add'>+			.socclk_mhz = 978.0,</div><div class='add'>+			.dram_speed_mts = 7500.0,</div><div class='add'>+			.dispclk_mhz = 960.0,</div><div class='add'>+			.dppclk_mhz = 960.0,</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='del'>-			.dscclk_mhz = 371.0,</div><div class='add'>+			.dscclk_mhz = 320.0,</div><div class='ctx'> 			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 4,</div><div class='add'>+			.dcfclk_mhz = 873.0,</div><div class='add'>+			.fabricclk_mhz = 1600.0,</div><div class='add'>+			.socclk_mhz = 1100.0,</div><div class='add'>+			.dram_speed_mts = 8533.0,</div><div class='add'>+			.dispclk_mhz = 1066.7,</div><div class='add'>+			.dppclk_mhz = 1066.7,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.phyclk_d18_mhz = 667.0,</div><div class='add'>+			.dscclk_mhz = 355.6,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 5,</div><div class='add'>+			.dcfclk_mhz = 960.0,</div><div class='add'>+			.fabricclk_mhz = 1700.0,</div><div class='add'>+			.socclk_mhz = 1257.0,</div><div class='add'>+			.dram_speed_mts = 8533.0,</div><div class='ctx'> 			.dispclk_mhz = 1200.0,</div><div class='ctx'> 			.dppclk_mhz = 1200.0,</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='del'>-			.dscclk_mhz = 417.0,</div><div class='add'>+			.dscclk_mhz = 400.0,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 6,</div><div class='add'>+			.dcfclk_mhz = 1067.0,</div><div class='add'>+			.fabricclk_mhz = 1850.0,</div><div class='add'>+			.socclk_mhz = 1257.0,</div><div class='add'>+			.dram_speed_mts = 8533.0,</div><div class='add'>+			.dispclk_mhz = 1371.4,</div><div class='add'>+			.dppclk_mhz = 1371.4,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.phyclk_d18_mhz = 667.0,</div><div class='add'>+			.dscclk_mhz = 457.1,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 7,</div><div class='add'>+			.dcfclk_mhz = 1200.0,</div><div class='add'>+			.fabricclk_mhz = 2000.0,</div><div class='add'>+			.socclk_mhz = 1467.0,</div><div class='add'>+			.dram_speed_mts = 8533.0,</div><div class='add'>+			.dispclk_mhz = 1600.0,</div><div class='add'>+			.dppclk_mhz = 1600.0,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.phyclk_d18_mhz = 667.0,</div><div class='add'>+			.dscclk_mhz = 533.3,</div><div class='ctx'> 			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='del'>-	.num_states = 5,</div><div class='add'>+	.num_states = 8,</div><div class='ctx'> 	.sr_exit_time_us = 28.0,</div><div class='ctx'> 	.sr_enter_plus_exit_time_us = 30.0,</div><div class='del'>-	.sr_exit_z8_time_us = 210.0,</div><div class='del'>-	.sr_enter_plus_exit_z8_time_us = 320.0,</div><div class='add'>+	.sr_exit_z8_time_us = 263.0,</div><div class='add'>+	.sr_enter_plus_exit_z8_time_us = 363.0,</div><div class='ctx'> 	.fclk_change_latency_us = 24.0,</div><div class='ctx'> 	.usr_retraining_latency_us = 2,</div><div class='ctx'> 	.writeback_latency_us = 12.0,</div><div class='hunk'>@@ -156,7 +215,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {</div><div class='ctx'> 	.urgent_latency_pixel_data_only_us = 4.0,</div><div class='ctx'> 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,</div><div class='ctx'> 	.urgent_latency_vm_data_only_us = 4.0,</div><div class='del'>-	.dram_clock_change_latency_us = 11.72,</div><div class='add'>+	.dram_clock_change_latency_us = 34,</div><div class='ctx'> 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,</div><div class='ctx'> 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,</div><div class='ctx'> 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,</div><div class='hunk'>@@ -177,6 +236,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {</div><div class='ctx'> 	.do_urgent_latency_adjustment = 0,</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_component_us = 0,</div><div class='ctx'> 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,</div><div class='add'>+	.num_chans = 4,</div><div class='add'>+	.dispclk_dppclk_vco_speed_mhz = 2400.0,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -340,6 +401,9 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,</div><div class='ctx'> 				clock_limits[i].socclk_mhz;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =</div><div class='ctx'> 				clk_table-&gt;entries[i].memclk_mhz * clk_table-&gt;entries[i].wck_ratio;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dram_speed_mts = clock_limits[i].dram_speed_mts;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =</div><div class='add'>+				clock_limits[i].dtbclk_mhz;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =</div><div class='ctx'> 				clk_table-&gt;num_entries;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =</div><div class='hunk'>@@ -352,6 +416,8 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,</div><div class='ctx'> 				clk_table-&gt;num_entries;</div><div class='ctx'> 			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =</div><div class='ctx'> 				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -404,16 +470,18 @@ static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)</div><div class='ctx'> int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> 					      struct dc_state *context,</div><div class='ctx'> 					      display_e2e_pipe_params_st *pipes,</div><div class='del'>-					      bool fast_validate)</div><div class='add'>+					      enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct pipe_ctx *pipe = 0;</div><div class='ctx'> 	bool upscaled = false;</div><div class='ctx'> 	const unsigned int max_allowed_vblank_nom = 1023;</div><div class='ctx'> </div><div class='add'>+	dc_assert_fp_enabled();</div><div class='add'>+</div><div class='ctx'> 	dcn31_populate_dml_pipes_from_context(dc, context, pipes,</div><div class='del'>-					      fast_validate);</div><div class='add'>+					      validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct dc_crtc_timing *timing;</div><div class='hunk'>@@ -465,9 +533,7 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;</div><div class='ctx'> </div><div class='del'>-		DC_FP_START();</div><div class='ctx'> 		dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);</div><div class='del'>-		DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 		pipes[pipe_cnt].pipe.dest.vfront_porch = timing-&gt;v_front_porch;</div><div class='ctx'> 		pipes[pipe_cnt].pipe.src.dcc_rate = 3;</div><div class='hunk'>@@ -551,6 +617,7 @@ void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='ctx'> 			plane_count++;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	/*dcn351 does not support z9/z10*/</div><div class='ctx'> 	if (context-&gt;stream_count == 0 || plane_count == 0) {</div><div class='ctx'> 		support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;</div><div class='hunk'>@@ -564,11 +631,9 @@ void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			dc-&gt;debug.minimum_z8_residency_time &gt; 0 ? dc-&gt;debug.minimum_z8_residency_time : 1000;</div><div class='ctx'> 		bool allow_z8 = context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; (double)minmum_z8_residency;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 		/*for psr1/psr-su, we allow z8 and z10 based on latency, for replay with IPS enabled, it will enter ips2*/</div><div class='del'>-		 if (is_pwrseq0 &amp;&amp; (is_psr || is_replay))</div><div class='add'>+		if (is_pwrseq0 &amp;&amp; (is_psr || is_replay))</div><div class='ctx'> 			support = allow_z8 ? allow_z8 : DCN_ZSTATE_SUPPORT_DISALLOW;</div><div class='del'>-</div><div class='ctx'> 	}</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.zstate_support = support;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h<br/>index f93efab9a668..f71d9d8d0759 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h</a></div><div class='hunk'>@@ -12,7 +12,7 @@ void dcn351_update_bw_bounding_box_fpu(struct dc *dc,</div><div class='ctx'> int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> 					      struct dc_state *context,</div><div class='ctx'> 					      display_e2e_pipe_params_st *pipes,</div><div class='del'>-					      bool fast_validate);</div><div class='add'>+					      enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h<br/>index fb17f8868cb4..641a8cd019cd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h</a></div><div class='hunk'>@@ -523,6 +523,7 @@ struct _vcs_dpi_display_pipe_dest_params_st {</div><div class='ctx'> 	unsigned int vupdate_offset;</div><div class='ctx'> 	unsigned int vupdate_width;</div><div class='ctx'> 	unsigned int vready_offset;</div><div class='add'>+	unsigned int pstate_keepout;</div><div class='ctx'> 	unsigned char interlaced;</div><div class='ctx'> 	double pixel_rate_mhz;</div><div class='ctx'> 	unsigned char synchronized_vblank_all_planes;</div><div class='hunk'>@@ -632,6 +633,7 @@ struct _vcs_dpi_display_dlg_regs_st {</div><div class='ctx'> 	unsigned int ref_freq_to_pix_freq;</div><div class='ctx'> 	unsigned int vratio_prefetch;</div><div class='ctx'> 	unsigned int vratio_prefetch_c;</div><div class='add'>+	unsigned int refcyc_per_tdlut_group;</div><div class='ctx'> 	unsigned int refcyc_per_pte_group_vblank_l;</div><div class='ctx'> 	unsigned int refcyc_per_pte_group_vblank_c;</div><div class='ctx'> 	unsigned int refcyc_per_meta_chunk_vblank_l;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c<br/>index 9a3ded311195..85453bbb4f9b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c</a></div><div class='hunk'>@@ -1099,8 +1099,13 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)</div><div class='ctx'> </div><div class='ctx'> 	// Total Available Pipes Support Check</div><div class='ctx'> 	for (k = 0; k &lt; mode_lib-&gt;vba.NumberOfActivePlanes; ++k) {</div><div class='del'>-		total_pipes += mode_lib-&gt;vba.DPPPerPlane[k];</div><div class='ctx'> 		pipe_idx = get_pipe_idx(mode_lib, k);</div><div class='add'>+		if (pipe_idx == -1) {</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			continue; // skip inactive planes</div><div class='add'>+		}</div><div class='add'>+		total_pipes += mode_lib-&gt;vba.DPPPerPlane[k];</div><div class='add'>+</div><div class='ctx'> 		if (mode_lib-&gt;vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz &gt; 0.0)</div><div class='ctx'> 			mode_lib-&gt;vba.DPPCLK[k] = mode_lib-&gt;vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;</div><div class='ctx'> 		else</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c<br/>index 412e75eb4704..12ff65b6a7e5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c</a></div><div class='hunk'>@@ -122,17 +122,6 @@ void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const stru</div><div class='ctx'> 	dml_print("DML_RQ_DLG_CALC: =====================================\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param)</div><div class='del'>-{</div><div class='del'>-	dml_print("DML_RQ_DLG_CALC: =====================================\n");</div><div class='del'>-	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");</div><div class='del'>-	dml_print("DML_RQ_DLG_CALC:  &lt;LUMA&gt;\n");</div><div class='del'>-	print__data_rq_dlg_params_st(mode_lib, &amp;rq_dlg_param-&gt;rq_l);</div><div class='del'>-	dml_print("DML_RQ_DLG_CALC:  &lt;CHROMA&gt;\n");</div><div class='del'>-	print__data_rq_dlg_params_st(mode_lib, &amp;rq_dlg_param-&gt;rq_c);</div><div class='del'>-	dml_print("DML_RQ_DLG_CALC: =====================================\n");</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param)</div><div class='ctx'> {</div><div class='ctx'> 	dml_print("DML_RQ_DLG_CALC: =====================================\n");</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h<br/>index ebcd717744e5..2bc64c4081dc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h</a></div><div class='hunk'>@@ -35,7 +35,6 @@ void print__rq_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dp</div><div class='ctx'> void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing);</div><div class='ctx'> void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param);</div><div class='ctx'> void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param);</div><div class='del'>-void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_dlg_params_st *rq_dlg_param);</div><div class='ctx'> void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param);</div><div class='ctx'> </div><div class='ctx'> void print__data_rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c<br/>index 3df559c591f8..88dc2b97e7bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c</a></div><div class='hunk'>@@ -39,7 +39,7 @@</div><div class='ctx'> </div><div class='ctx'> static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	unsigned int ret_val = 0;</div><div class='add'>+	unsigned int ret_val = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (source_format == dm_444_16) {</div><div class='ctx'> 		if (!is_chroma)</div><div class='hunk'>@@ -559,12 +559,11 @@ static void get_surf_rq_param(</div><div class='ctx'> 		const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param,</div><div class='ctx'> 		bool is_chroma)</div><div class='ctx'> {</div><div class='del'>-	bool mode_422 = 0;</div><div class='ctx'> 	unsigned int vp_width = 0;</div><div class='ctx'> 	unsigned int vp_height = 0;</div><div class='ctx'> 	unsigned int data_pitch = 0;</div><div class='ctx'> 	unsigned int meta_pitch = 0;</div><div class='del'>-	unsigned int ppe = mode_422 ? 2 : 1;</div><div class='add'>+	unsigned int ppe = 1;</div><div class='ctx'> 	bool surf_linear;</div><div class='ctx'> 	bool surf_vert;</div><div class='ctx'> 	unsigned int bytes_per_element;</div><div class='hunk'>@@ -1596,11 +1595,6 @@ void dml1_rq_dlg_get_dlg_params(</div><div class='ctx'> 		swath_width_pixels_ub_c = swath_width_ub_c * 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	hscale_pixel_rate_l = 0.;</div><div class='del'>-	hscale_pixel_rate_c = 0.;</div><div class='del'>-	min_hratio_fact_l = 1.0;</div><div class='del'>-	min_hratio_fact_c = 1.0;</div><div class='del'>-</div><div class='ctx'> 	if (htaps_l &lt;= 1)</div><div class='ctx'> 		min_hratio_fact_l = 2.0;</div><div class='ctx'> 	else if (htaps_l &lt;= 6) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h<br/>index 072bd0539605..6b2ab4ec2b5f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h</a></div><div class='hunk'>@@ -66,11 +66,15 @@ static inline double dml_max5(double a, double b, double c, double d, double e)</div><div class='ctx'> </div><div class='ctx'> static inline double dml_ceil(double a, double granularity)</div><div class='ctx'> {</div><div class='add'>+	if (granularity == 0)</div><div class='add'>+		return 0;</div><div class='ctx'> 	return (double) dcn_bw_ceil2(a, granularity);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline double dml_floor(double a, double granularity)</div><div class='ctx'> {</div><div class='add'>+	if (granularity == 0)</div><div class='add'>+		return 0;</div><div class='ctx'> 	return (double) dcn_bw_floor2(a, granularity);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -114,11 +118,15 @@ static inline double dml_ceil_2(double f)</div><div class='ctx'> </div><div class='ctx'> static inline double dml_ceil_ex(double x, double granularity)</div><div class='ctx'> {</div><div class='add'>+	if (granularity == 0)</div><div class='add'>+		return 0;</div><div class='ctx'> 	return (double) dcn_bw_ceil2(x, granularity);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline double dml_floor_ex(double x, double granularity)</div><div class='ctx'> {</div><div class='add'>+	if (granularity == 0)</div><div class='add'>+		return 0;</div><div class='ctx'> 	return (double) dcn_bw_floor2(x, granularity);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile<br/>deleted file mode 100644<br/>index acff3449b8d7..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,97 +0,0 @@</div><div class='del'>-# SPDX-License-Identifier: MIT */</div><div class='del'>-#</div><div class='del'>-# Copyright 2023 Advanced Micro Devices, Inc.</div><div class='del'>-#</div><div class='del'>-# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>-# copy of this software and associated documentation files (the "Software"),</div><div class='del'>-# to deal in the Software without restriction, including without limitation</div><div class='del'>-# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>-# and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>-# Software is furnished to do so, subject to the following conditions:</div><div class='del'>-#</div><div class='del'>-# The above copyright notice and this permission notice shall be included in</div><div class='del'>-# all copies or substantial portions of the Software.</div><div class='del'>-#</div><div class='del'>-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>-# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>-# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>-# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>-# OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>-#</div><div class='del'>-# Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dml2.</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_X86</div><div class='del'>-dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float</div><div class='del'>-dml2_ccflags := $(dml2_ccflags-y) -msse</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_PPC64</div><div class='del'>-dml2_ccflags := -mhard-float -maltivec</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_ARM64</div><div class='del'>-dml2_rcflags := -mgeneral-regs-only</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_LOONGARCH</div><div class='del'>-dml2_ccflags := -mfpu=64</div><div class='del'>-dml2_rcflags := -msoft-float</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_CC_IS_GCC</div><div class='del'>-ifeq ($(call cc-ifversion, -lt, 0701, y), y)</div><div class='del'>-IS_OLD_GCC = 1</div><div class='del'>-endif</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifdef CONFIG_X86</div><div class='del'>-ifdef IS_OLD_GCC</div><div class='del'>-# Stack alignment mismatch, proceed with caution.</div><div class='del'>-# GCC &lt; 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3</div><div class='del'>-# (8B stack alignment).</div><div class='del'>-dml2_ccflags += -mpreferred-stack-boundary=4</div><div class='del'>-else</div><div class='del'>-dml2_ccflags += -msse2</div><div class='del'>-endif</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-ifneq ($(CONFIG_FRAME_WARN),0)</div><div class='del'>-ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)</div><div class='del'>-frame_warn_flag := -Wframe-larger-than=3072</div><div class='del'>-else</div><div class='del'>-frame_warn_flag := -Wframe-larger-than=2048</div><div class='del'>-endif</div><div class='del'>-endif</div><div class='del'>-</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_utils.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_policy.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_translation_helper.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_mall_phantom.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml_display_rq_dlg_calc.o := $(dml2_ccflags)</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_dc_resource_mgmt.o := $(dml2_ccflags)</div><div class='del'>-</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_utils.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_policy.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_translation_helper.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_mall_phantom.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml_display_rq_dlg_calc.o := $(dml2_rcflags)</div><div class='del'>-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_dc_resource_mgmt.o := $(dml2_rcflags)</div><div class='del'>-</div><div class='del'>-DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \</div><div class='del'>-		dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \</div><div class='del'>-		dml_display_rq_dlg_calc.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2/,$(DML2))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DML2)</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile<br/>new file mode 100644<br/>index 000000000000..97e068b6bf6b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/Makefile</a></div><div class='hunk'>@@ -0,0 +1,140 @@</div><div class='add'>+# SPDX-License-Identifier: MIT */</div><div class='add'>+#</div><div class='add'>+# Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+# Makefile for dml2.</div><div class='add'>+</div><div class='add'>+dml2_ccflags := $(CC_FLAGS_FPU)</div><div class='add'>+dml2_rcflags := $(CC_FLAGS_NO_FPU)</div><div class='add'>+</div><div class='add'>+ifneq ($(CONFIG_FRAME_WARN),0)</div><div class='add'>+    ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)</div><div class='add'>+        ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)</div><div class='add'>+            frame_warn_limit := 4096</div><div class='add'>+        else</div><div class='add'>+            frame_warn_limit := 3072</div><div class='add'>+        endif</div><div class='add'>+    else</div><div class='add'>+        frame_warn_limit := 2056</div><div class='add'>+    endif</div><div class='add'>+</div><div class='add'>+    ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)</div><div class='add'>+        frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)</div><div class='add'>+    endif</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_core</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_mcg/</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_dpmm/</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_pmo/</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/inc</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/inc</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/</div><div class='add'>+</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags)</div><div class='add'>+</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags)</div><div class='add'>+</div><div class='add'>+DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \</div><div class='add'>+		dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \</div><div class='add'>+		dml_display_rq_dlg_calc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DML2)</div><div class='add'>+</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags)</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags)</div><div class='add'>+</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags)</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags)</div><div class='add'>+</div><div class='add'>+DML21 := src/dml2_top/dml2_top_interfaces.o</div><div class='add'>+DML21 += src/dml2_top/dml2_top_soc15.o</div><div class='add'>+DML21 += src/dml2_core/dml2_core_dcn4.o</div><div class='add'>+DML21 += src/dml2_core/dml2_core_utils.o</div><div class='add'>+DML21 += src/dml2_core/dml2_core_factory.o</div><div class='add'>+DML21 += src/dml2_core/dml2_core_dcn4_calcs.o</div><div class='add'>+DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o</div><div class='add'>+DML21 += src/dml2_dpmm/dml2_dpmm_factory.o</div><div class='add'>+DML21 += src/dml2_mcg/dml2_mcg_dcn4.o</div><div class='add'>+DML21 += src/dml2_mcg/dml2_mcg_factory.o</div><div class='add'>+DML21 += src/dml2_pmo/dml2_pmo_dcn3.o</div><div class='add'>+DML21 += src/dml2_pmo/dml2_pmo_factory.o</div><div class='add'>+DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o</div><div class='add'>+DML21 += src/dml2_standalone_libraries/lib_float_math.o</div><div class='add'>+DML21 += dml21_translation_helper.o</div><div class='add'>+DML21 += dml21_wrapper.o</div><div class='add'>+DML21 += dml21_utils.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2_0/dml21/,$(DML21))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DML21)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h b/drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h<br/>index e450445bc05d..b954c9648fbe 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h</a></div><div class='hunk'>@@ -53,17 +53,17 @@ typedef const void *const_pvoid;</div><div class='ctx'> typedef const char *const_pchar;</div><div class='ctx'> </div><div class='ctx'> typedef struct rgba_struct {</div><div class='del'>-    uint8 a;</div><div class='del'>-    uint8 r;</div><div class='del'>-    uint8 g;</div><div class='del'>-    uint8 b;</div><div class='add'>+	uint8 a;</div><div class='add'>+	uint8 r;</div><div class='add'>+	uint8 g;</div><div class='add'>+	uint8 b;</div><div class='ctx'> } rgba_t;</div><div class='ctx'> </div><div class='ctx'> typedef struct {</div><div class='del'>-    uint8 blue;</div><div class='del'>-    uint8 green;</div><div class='del'>-    uint8 red;</div><div class='del'>-    uint8 alpha;</div><div class='add'>+	uint8 blue;</div><div class='add'>+	uint8 green;</div><div class='add'>+	uint8 red;</div><div class='add'>+	uint8 alpha;</div><div class='ctx'> } gen_color_t;</div><div class='ctx'> </div><div class='ctx'> typedef union {</div><div class='hunk'>@@ -87,7 +87,7 @@ typedef union {</div><div class='ctx'> } uintfloat64;</div><div class='ctx'> </div><div class='ctx'> #ifndef UNREFERENCED_PARAMETER</div><div class='del'>-#define UNREFERENCED_PARAMETER(x) x = x</div><div class='add'>+#define UNREFERENCED_PARAMETER(x) (x = x)</div><div class='ctx'> #endif</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c<br/>index 9be5ebf3a8c0..c468f492b876 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c</a></div><div class='hunk'>@@ -31,6 +31,9 @@</div><div class='ctx'> #include "dml_assert.h"</div><div class='ctx'> </div><div class='ctx'> #define DML2_MAX_FMT_420_BUFFER_WIDTH 4096</div><div class='add'>+#define TB_BORROWED_MAX 400</div><div class='add'>+#define DML_MAX_VSTARTUP_START 1023</div><div class='add'>+</div><div class='ctx'> // ---------------------------</div><div class='ctx'> //  Declaration Begins</div><div class='ctx'> // ---------------------------</div><div class='hunk'>@@ -113,6 +116,7 @@ static void CalculateODMMode(</div><div class='ctx'> 	dml_float_t DISPCLKDPPCLKDSCCLKDownSpreading,</div><div class='ctx'> 	dml_float_t DISPCLKRampingMargin,</div><div class='ctx'> 	dml_float_t DISPCLKDPPCLKVCOSpeed,</div><div class='add'>+	dml_uint_t NumberOfDSCSlices,</div><div class='ctx'> </div><div class='ctx'> 	// Output</div><div class='ctx'> 	dml_bool_t *TotalAvailablePipesSupport,</div><div class='hunk'>@@ -1219,6 +1223,7 @@ static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *</div><div class='ctx'> 	s-&gt;dst_y_prefetch_oto = s-&gt;Tvm_oto_lines + 2 * s-&gt;Tr0_oto_lines + s-&gt;Lsw_oto;</div><div class='ctx'> </div><div class='ctx'> 	s-&gt;dst_y_prefetch_equ = p-&gt;VStartup - (*p-&gt;TSetup + dml_max(p-&gt;TWait + p-&gt;TCalc, *p-&gt;Tdmdl)) / s-&gt;LineTime - (*p-&gt;DSTYAfterScaler + (dml_float_t) *p-&gt;DSTXAfterScaler / (dml_float_t)p-&gt;myPipe-&gt;HTotal);</div><div class='add'>+	s-&gt;dst_y_prefetch_equ = dml_min(s-&gt;dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH</div><div class='ctx'> </div><div class='ctx'> #ifdef __DML_VBA_DEBUG__</div><div class='ctx'> 	dml_print("DML::%s: HTotal = %u\n", __func__, p-&gt;myPipe-&gt;HTotal);</div><div class='hunk'>@@ -1732,7 +1737,7 @@ static void CalculateBytePerPixelAndBlockSizes(</div><div class='ctx'> #endif</div><div class='ctx'> } // CalculateBytePerPixelAndBlockSizes</div><div class='ctx'> </div><div class='del'>-static dml_float_t CalculateTWait(</div><div class='add'>+static noinline_for_stack dml_float_t CalculateTWait(</div><div class='ctx'> 		dml_uint_t PrefetchMode,</div><div class='ctx'> 		enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange,</div><div class='ctx'> 		dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal,</div><div class='hunk'>@@ -2730,7 +2735,7 @@ static dml_float_t TruncToValidBPP(</div><div class='ctx'> 		NonDSCBPP1 = 15;</div><div class='ctx'> 		NonDSCBPP2 = 18;</div><div class='ctx'> 		MinDSCBPP = 6;</div><div class='del'>-		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;</div><div class='add'>+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1.0 / 16;</div><div class='ctx'> 	} else if (Format == dml_444) {</div><div class='ctx'> 		NonDSCBPP0 = 24;</div><div class='ctx'> 		NonDSCBPP1 = 30;</div><div class='hunk'>@@ -2782,6 +2787,8 @@ static dml_float_t TruncToValidBPP(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	*RequiredSlots = (dml_uint_t)(dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1));</div><div class='add'>+</div><div class='ctx'> 	if (DesiredBPP == 0) {</div><div class='ctx'> 		if (DSCEnable) {</div><div class='ctx'> 			if (MaxLinkBPP &lt; MinDSCBPP) {</div><div class='hunk'>@@ -2810,10 +2817,6 @@ static dml_float_t TruncToValidBPP(</div><div class='ctx'> 			return DesiredBPP;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	*RequiredSlots = (dml_uint_t)(dml_ceil(DesiredBPP / MaxLinkBPP * 64, 1));</div><div class='del'>-</div><div class='del'>-	return __DML_DPP_INVALID__;</div><div class='ctx'> } // TruncToValidBPP</div><div class='ctx'> </div><div class='ctx'> static void CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(</div><div class='hunk'>@@ -3790,9 +3793,9 @@ static void CalculateStutterEfficiency(struct display_mode_lib_scratch_st *scrat</div><div class='ctx'> 	dml_bool_t FoundCriticalSurface = false;</div><div class='ctx'> </div><div class='ctx'> 	dml_uint_t TotalNumberOfActiveOTG = 0;</div><div class='del'>-	dml_float_t SinglePixelClock;</div><div class='del'>-	dml_uint_t SingleHTotal;</div><div class='del'>-	dml_uint_t SingleVTotal;</div><div class='add'>+	dml_float_t SinglePixelClock = 0;</div><div class='add'>+	dml_uint_t SingleHTotal = 0;</div><div class='add'>+	dml_uint_t SingleVTotal = 0;</div><div class='ctx'> 	dml_bool_t SameTiming = true;</div><div class='ctx'> </div><div class='ctx'> 	dml_float_t LastStutterPeriod = 0.0;</div><div class='hunk'>@@ -4282,7 +4285,7 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	*p-&gt;compbuf_reserved_space_64b = 2 * p-&gt;PixelChunkSizeInKByte * 1024 / 64;</div><div class='del'>-	if (p-&gt;UnboundedRequestEnabled) {</div><div class='add'>+	if (*p-&gt;UnboundedRequestEnabled) {</div><div class='ctx'> 		*p-&gt;compbuf_reserved_space_64b = dml_max(*p-&gt;compbuf_reserved_space_64b,</div><div class='ctx'> 				(dml_float_t)(p-&gt;ROBBufferSizeInKByte * 1024/64)</div><div class='ctx'> 				- (dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * TTUFIFODEPTH / MAXIMUMCOMPRESSION/64));</div><div class='hunk'>@@ -4456,7 +4459,7 @@ static void CalculateSwathWidth(</div><div class='ctx'> 	}</div><div class='ctx'> } // CalculateSwathWidth</div><div class='ctx'> </div><div class='del'>-static  dml_float_t CalculateExtraLatency(</div><div class='add'>+static noinline_for_stack dml_float_t CalculateExtraLatency(</div><div class='ctx'> 		dml_uint_t RoundTripPingLatencyCycles,</div><div class='ctx'> 		dml_uint_t ReorderingBytes,</div><div class='ctx'> 		dml_float_t DCFCLK,</div><div class='hunk'>@@ -5403,10 +5406,10 @@ static void CalculateOutputLink(</div><div class='ctx'> 			}</div><div class='ctx'> 			if (Output == dml_dp2p0) {</div><div class='ctx'> 				*OutBpp = 0;</div><div class='del'>-				if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr10) &amp;&amp; PHYCLKD32PerState &gt;= 10000 / 32) {</div><div class='add'>+				if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr10) &amp;&amp; PHYCLKD32PerState &gt;= 10000 / 32.0) {</div><div class='ctx'> 					*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='ctx'> 												OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='del'>-					if (*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &lt; 13500 / 32 &amp;&amp; DSCEnable == dml_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &lt; 13500 / 32.0 &amp;&amp; DSCEnable == dml_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='ctx'> 						*RequiresDSC = true;</div><div class='ctx'> 						LinkDSCEnable = true;</div><div class='ctx'> 						*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='hunk'>@@ -5416,7 +5419,7 @@ static void CalculateOutputLink(</div><div class='ctx'> 					*OutputType = dml_output_type_dp2p0;</div><div class='ctx'> 					*OutputRate = dml_output_rate_dp_rate_uhbr10;</div><div class='ctx'> 				}</div><div class='del'>-				if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr13p5) &amp;&amp; *OutBpp == 0 &amp;&amp; PHYCLKD32PerState &gt;= 13500 / 32) {</div><div class='add'>+				if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr13p5) &amp;&amp; *OutBpp == 0 &amp;&amp; PHYCLKD32PerState &gt;= 13500 / 32.0) {</div><div class='ctx'> 					*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='ctx'> 												OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='ctx'> </div><div class='hunk'>@@ -5516,6 +5519,7 @@ static void CalculateODMMode(</div><div class='ctx'> 		dml_float_t DISPCLKDPPCLKDSCCLKDownSpreading,</div><div class='ctx'> 		dml_float_t DISPCLKRampingMargin,</div><div class='ctx'> 		dml_float_t DISPCLKDPPCLKVCOSpeed,</div><div class='add'>+		dml_uint_t NumberOfDSCSlices,</div><div class='ctx'> </div><div class='ctx'> 		// Output</div><div class='ctx'> 		dml_bool_t *TotalAvailablePipesSupport,</div><div class='hunk'>@@ -5538,7 +5542,7 @@ static void CalculateODMMode(</div><div class='ctx'> 			*TotalAvailablePipesSupport = false;</div><div class='ctx'> 		else if (HActive &gt; 2 * DML2_MAX_FMT_420_BUFFER_WIDTH)</div><div class='ctx'> 			ODMUse = dml_odm_use_policy_combine_4to1;</div><div class='del'>-		else if (HActive &gt; DML2_MAX_FMT_420_BUFFER_WIDTH)</div><div class='add'>+		else if (HActive &gt; DML2_MAX_FMT_420_BUFFER_WIDTH &amp;&amp; ODMUse != dml_odm_use_policy_combine_4to1)</div><div class='ctx'> 			ODMUse = dml_odm_use_policy_combine_2to1;</div><div class='ctx'> 		if (Output == dml_hdmi &amp;&amp; ODMUse == dml_odm_use_policy_combine_2to1)</div><div class='ctx'> 			*TotalAvailablePipesSupport = false;</div><div class='hunk'>@@ -5563,7 +5567,7 @@ static void CalculateODMMode(</div><div class='ctx'> 	*NumberOfDPP = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!(Output == dml_hdmi || Output == dml_dp || Output == dml_edp) &amp;&amp; (ODMUse == dml_odm_use_policy_combine_4to1 || (ODMUse == dml_odm_use_policy_combine_as_needed &amp;&amp;</div><div class='del'>-		(SurfaceRequiredDISPCLKWithODMCombineTwoToOne &gt; StateDispclk || (DSCEnable &amp;&amp; (HActive &gt; 2 * MaximumPixelsPerLinePerDSCUnit)))))) {</div><div class='add'>+		(SurfaceRequiredDISPCLKWithODMCombineTwoToOne &gt; StateDispclk || (DSCEnable &amp;&amp; (HActive &gt; 2 * MaximumPixelsPerLinePerDSCUnit)) || NumberOfDSCSlices &gt; 8)))) {</div><div class='ctx'> 		if (TotalNumberOfActiveDPP + 4 &lt;= MaxNumDPP) {</div><div class='ctx'> 			*ODMMode = dml_odm_mode_combine_4to1;</div><div class='ctx'> 			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne;</div><div class='hunk'>@@ -5573,7 +5577,7 @@ static void CalculateODMMode(</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (Output != dml_hdmi &amp;&amp; (ODMUse == dml_odm_use_policy_combine_2to1 || (ODMUse == dml_odm_use_policy_combine_as_needed &amp;&amp;</div><div class='ctx'> 				((SurfaceRequiredDISPCLKWithoutODMCombine &gt; StateDispclk &amp;&amp; SurfaceRequiredDISPCLKWithODMCombineTwoToOne &lt;= StateDispclk) ||</div><div class='del'>-				(DSCEnable &amp;&amp; (HActive &gt; MaximumPixelsPerLinePerDSCUnit)))))) {</div><div class='add'>+				(DSCEnable &amp;&amp; (HActive &gt; MaximumPixelsPerLinePerDSCUnit)) || (NumberOfDSCSlices &lt;= 8 &amp;&amp; NumberOfDSCSlices &gt; 4))))) {</div><div class='ctx'> 		if (TotalNumberOfActiveDPP + 2 &lt;= MaxNumDPP) {</div><div class='ctx'> 			*ODMMode = dml_odm_mode_combine_2to1;</div><div class='ctx'> 			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;</div><div class='hunk'>@@ -5880,11 +5884,11 @@ static dml_uint_t DSCDelayRequirement(</div><div class='ctx'> </div><div class='ctx'> 	if (DSCEnabled == true &amp;&amp; OutputBpp != 0) {</div><div class='ctx'> 		if (ODMMode == dml_odm_mode_combine_4to1) {</div><div class='del'>-			DSCDelayRequirement_val = 4 * (dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),</div><div class='del'>-												(dml_uint_t) (NumberOfDSCSlices / 4.0), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output));</div><div class='add'>+			DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),</div><div class='add'>+												(dml_uint_t) (NumberOfDSCSlices / 4.0), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output);</div><div class='ctx'> 		} else if (ODMMode == dml_odm_mode_combine_2to1) {</div><div class='del'>-			DSCDelayRequirement_val = 2 * (dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),</div><div class='del'>-												(dml_uint_t) (NumberOfDSCSlices / 2.0), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output));</div><div class='add'>+			DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_ceil((dml_float_t) HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),</div><div class='add'>+												(dml_uint_t) (NumberOfDSCSlices / 2.0), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)((dml_float_t) dml_ceil(HActive / (dml_float_t) NumberOfDSCSlices, 1.0)),</div><div class='ctx'> 										NumberOfDSCSlices, OutputFormat, Output) + dscComputeDelay(OutputFormat, Output);</div><div class='hunk'>@@ -5912,7 +5916,7 @@ static dml_uint_t DSCDelayRequirement(</div><div class='ctx'> 	return DSCDelayRequirement_val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static dml_bool_t CalculateVActiveBandwithSupport(dml_uint_t NumberOfActiveSurfaces,</div><div class='add'>+static noinline_for_stack dml_bool_t CalculateVActiveBandwithSupport(dml_uint_t NumberOfActiveSurfaces,</div><div class='ctx'> 										dml_float_t ReturnBW,</div><div class='ctx'> 										dml_bool_t NotUrgentLatencyHiding[],</div><div class='ctx'> 										dml_float_t ReadBandwidthLuma[],</div><div class='hunk'>@@ -6016,7 +6020,7 @@ static void CalculatePrefetchBandwithSupport(</div><div class='ctx'> #endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static dml_float_t CalculateBandwidthAvailableForImmediateFlip(</div><div class='add'>+static noinline_for_stack dml_float_t CalculateBandwidthAvailableForImmediateFlip(</div><div class='ctx'> 													dml_uint_t NumberOfActiveSurfaces,</div><div class='ctx'> 													dml_float_t ReturnBW,</div><div class='ctx'> 													dml_float_t ReadBandwidthLuma[],</div><div class='hunk'>@@ -6207,10 +6211,11 @@ static dml_uint_t CalculateMaxVStartup(</div><div class='ctx'> 	dml_print("DML::%s: vblank_avail = %u\n", __func__, vblank_avail);</div><div class='ctx'> 	dml_print("DML::%s: max_vstartup_lines = %u\n", __func__, max_vstartup_lines);</div><div class='ctx'> #endif</div><div class='add'>+	max_vstartup_lines = (dml_uint_t) dml_min(max_vstartup_lines, DML_MAX_VSTARTUP_START);</div><div class='ctx'> 	return max_vstartup_lines;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void set_calculate_prefetch_schedule_params(struct display_mode_lib_st *mode_lib,</div><div class='add'>+static noinline_for_stack void set_calculate_prefetch_schedule_params(struct display_mode_lib_st *mode_lib,</div><div class='ctx'> 						   struct CalculatePrefetchSchedule_params_st *CalculatePrefetchSchedule_params,</div><div class='ctx'> 						   dml_uint_t j,</div><div class='ctx'> 						   dml_uint_t k)</div><div class='hunk'>@@ -6262,7 +6267,7 @@ static void set_calculate_prefetch_schedule_params(struct display_mode_lib_st *m</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;Tno_bw = &amp;mode_lib-&gt;ms.Tno_bw[k];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='add'>+static noinline_for_stack void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> {</div><div class='ctx'> 	struct dml_core_mode_support_locals_st *s = &amp;mode_lib-&gt;scratch.dml_core_mode_support_locals;</div><div class='ctx'> 	struct CalculatePrefetchSchedule_params_st *CalculatePrefetchSchedule_params = &amp;mode_lib-&gt;scratch.CalculatePrefetchSchedule_params;</div><div class='hunk'>@@ -6298,9 +6303,9 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 			mode_lib-&gt;ms.meta_row_bandwidth_this_state,</div><div class='ctx'> 			mode_lib-&gt;ms.dpte_row_bandwidth_this_state,</div><div class='ctx'> 			mode_lib-&gt;ms.NoOfDPPThisState,</div><div class='del'>-			mode_lib-&gt;ms.UrgentBurstFactorLuma,</div><div class='del'>-			mode_lib-&gt;ms.UrgentBurstFactorChroma,</div><div class='del'>-			mode_lib-&gt;ms.UrgentBurstFactorCursor);</div><div class='add'>+			mode_lib-&gt;ms.UrgentBurstFactorLuma[j],</div><div class='add'>+			mode_lib-&gt;ms.UrgentBurstFactorChroma[j],</div><div class='add'>+			mode_lib-&gt;ms.UrgentBurstFactorCursor[j]);</div><div class='ctx'> </div><div class='ctx'> 		s-&gt;VMDataOnlyReturnBWPerState = dml_get_return_bw_mbps_vm_only(</div><div class='ctx'> 																	&amp;mode_lib-&gt;ms.soc,</div><div class='hunk'>@@ -6431,7 +6436,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 							/* Output */</div><div class='ctx'> 							&amp;mode_lib-&gt;ms.UrgentBurstFactorCursorPre[k],</div><div class='ctx'> 							&amp;mode_lib-&gt;ms.UrgentBurstFactorLumaPre[k],</div><div class='del'>-							&amp;mode_lib-&gt;ms.UrgentBurstFactorChroma[k],</div><div class='add'>+							&amp;mode_lib-&gt;ms.UrgentBurstFactorChromaPre[k],</div><div class='ctx'> 							&amp;mode_lib-&gt;ms.NotUrgentLatencyHidingPre[k]);</div><div class='ctx'> </div><div class='ctx'> 					mode_lib-&gt;ms.cursor_bw_pre[k] = mode_lib-&gt;ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib-&gt;ms.cache_display_cfg.plane.CursorWidth[k] *</div><div class='hunk'>@@ -6455,9 +6460,9 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 				mode_lib-&gt;ms.cursor_bw_pre,</div><div class='ctx'> 				mode_lib-&gt;ms.prefetch_vmrow_bw,</div><div class='ctx'> 				mode_lib-&gt;ms.NoOfDPPThisState,</div><div class='del'>-				mode_lib-&gt;ms.UrgentBurstFactorLuma,</div><div class='del'>-				mode_lib-&gt;ms.UrgentBurstFactorChroma,</div><div class='del'>-				mode_lib-&gt;ms.UrgentBurstFactorCursor,</div><div class='add'>+				mode_lib-&gt;ms.UrgentBurstFactorLuma[j],</div><div class='add'>+				mode_lib-&gt;ms.UrgentBurstFactorChroma[j],</div><div class='add'>+				mode_lib-&gt;ms.UrgentBurstFactorCursor[j],</div><div class='ctx'> 				mode_lib-&gt;ms.UrgentBurstFactorLumaPre,</div><div class='ctx'> 				mode_lib-&gt;ms.UrgentBurstFactorChromaPre,</div><div class='ctx'> 				mode_lib-&gt;ms.UrgentBurstFactorCursorPre,</div><div class='hunk'>@@ -6514,9 +6519,9 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 						mode_lib-&gt;ms.cursor_bw,</div><div class='ctx'> 						mode_lib-&gt;ms.cursor_bw_pre,</div><div class='ctx'> 						mode_lib-&gt;ms.NoOfDPPThisState,</div><div class='del'>-						mode_lib-&gt;ms.UrgentBurstFactorLuma,</div><div class='del'>-						mode_lib-&gt;ms.UrgentBurstFactorChroma,</div><div class='del'>-						mode_lib-&gt;ms.UrgentBurstFactorCursor,</div><div class='add'>+						mode_lib-&gt;ms.UrgentBurstFactorLuma[j],</div><div class='add'>+						mode_lib-&gt;ms.UrgentBurstFactorChroma[j],</div><div class='add'>+						mode_lib-&gt;ms.UrgentBurstFactorCursor[j],</div><div class='ctx'> 						mode_lib-&gt;ms.UrgentBurstFactorLumaPre,</div><div class='ctx'> 						mode_lib-&gt;ms.UrgentBurstFactorChromaPre,</div><div class='ctx'> 						mode_lib-&gt;ms.UrgentBurstFactorCursorPre);</div><div class='hunk'>@@ -6524,7 +6529,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 				mode_lib-&gt;ms.TotImmediateFlipBytes = 0;</div><div class='ctx'> 				for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='ctx'> 					if (!(mode_lib-&gt;ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required)) {</div><div class='del'>-						mode_lib-&gt;ms.TotImmediateFlipBytes = mode_lib-&gt;ms.TotImmediateFlipBytes + mode_lib-&gt;ms.NoOfDPP[j][k] * mode_lib-&gt;ms.PDEAndMetaPTEBytesPerFrame[j][k] + mode_lib-&gt;ms.MetaRowBytes[j][k];</div><div class='add'>+						mode_lib-&gt;ms.TotImmediateFlipBytes = mode_lib-&gt;ms.TotImmediateFlipBytes + mode_lib-&gt;ms.NoOfDPP[j][k] * (mode_lib-&gt;ms.PDEAndMetaPTEBytesPerFrame[j][k] + mode_lib-&gt;ms.MetaRowBytes[j][k]);</div><div class='ctx'> 						if (mode_lib-&gt;ms.use_one_row_for_frame_flip[j][k]) {</div><div class='ctx'> 							mode_lib-&gt;ms.TotImmediateFlipBytes = mode_lib-&gt;ms.TotImmediateFlipBytes + mode_lib-&gt;ms.NoOfDPP[j][k] * (2 * mode_lib-&gt;ms.DPTEBytesPerRow[j][k]);</div><div class='ctx'> 						} else {</div><div class='hunk'>@@ -6583,9 +6588,9 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 													mode_lib-&gt;ms.cursor_bw_pre,</div><div class='ctx'> 													mode_lib-&gt;ms.prefetch_vmrow_bw,</div><div class='ctx'> 													mode_lib-&gt;ms.NoOfDPP[j], // VBA_ERROR DPPPerSurface is not assigned at this point, should use NoOfDpp here</div><div class='del'>-													mode_lib-&gt;ms.UrgentBurstFactorLuma,</div><div class='del'>-													mode_lib-&gt;ms.UrgentBurstFactorChroma,</div><div class='del'>-													mode_lib-&gt;ms.UrgentBurstFactorCursor,</div><div class='add'>+													mode_lib-&gt;ms.UrgentBurstFactorLuma[j],</div><div class='add'>+													mode_lib-&gt;ms.UrgentBurstFactorChroma[j],</div><div class='add'>+													mode_lib-&gt;ms.UrgentBurstFactorCursor[j],</div><div class='ctx'> 													mode_lib-&gt;ms.UrgentBurstFactorLumaPre,</div><div class='ctx'> 													mode_lib-&gt;ms.UrgentBurstFactorChromaPre,</div><div class='ctx'> 													mode_lib-&gt;ms.UrgentBurstFactorCursorPre,</div><div class='hunk'>@@ -6938,20 +6943,25 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> </div><div class='ctx'> 	/*Number Of DSC Slices*/</div><div class='ctx'> 	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='del'>-		if (mode_lib-&gt;ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {</div><div class='del'>-			if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 4800) {</div><div class='del'>-				mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));</div><div class='del'>-			} else if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 2400) {</div><div class='del'>-				mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 8;</div><div class='del'>-			} else if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 1200) {</div><div class='del'>-				mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 4;</div><div class='del'>-			} else if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 340) {</div><div class='del'>-				mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 2;</div><div class='del'>-			} else {</div><div class='del'>-				mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 1;</div><div class='add'>+		if (mode_lib-&gt;ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &amp;&amp;</div><div class='add'>+			mode_lib-&gt;ms.cache_display_cfg.output.DSCEnable[k] != dml_dsc_disable) {</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = mode_lib-&gt;ms.cache_display_cfg.output.DSCSlices[k];</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;ms.support.NumberOfDSCSlices[k] == 0) {</div><div class='add'>+				if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 4800) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));</div><div class='add'>+				} else if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 2400) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 8;</div><div class='add'>+				} else if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 1200) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 4;</div><div class='add'>+				} else if (mode_lib-&gt;ms.cache_display_cfg.output.PixelClockBackEnd[k] &gt; 340) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 2;</div><div class='add'>+				} else {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 1;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 0;</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 1;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -7050,6 +7060,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 					mode_lib-&gt;ms.soc.dcn_downspread_percent,</div><div class='ctx'> 					mode_lib-&gt;ms.ip.dispclk_ramp_margin_percent,</div><div class='ctx'> 					mode_lib-&gt;ms.soc.dispclk_dppclk_vco_speed_mhz,</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='ctx'> </div><div class='ctx'> 					/* Output */</div><div class='ctx'> 					&amp;s-&gt;TotalAvailablePipesSupportNoDSC,</div><div class='hunk'>@@ -7072,6 +7083,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 					mode_lib-&gt;ms.soc.dcn_downspread_percent,</div><div class='ctx'> 					mode_lib-&gt;ms.ip.dispclk_ramp_margin_percent,</div><div class='ctx'> 					mode_lib-&gt;ms.soc.dispclk_dppclk_vco_speed_mhz,</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='ctx'> </div><div class='ctx'> 					/* Output */</div><div class='ctx'> 					&amp;s-&gt;TotalAvailablePipesSupportDSC,</div><div class='hunk'>@@ -7799,9 +7811,9 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 				mode_lib-&gt;ms.DETBufferSizeYThisState[k],</div><div class='ctx'> 				mode_lib-&gt;ms.DETBufferSizeCThisState[k],</div><div class='ctx'> 				/* Output */</div><div class='del'>-				&amp;mode_lib-&gt;ms.UrgentBurstFactorCursor[k],</div><div class='del'>-				&amp;mode_lib-&gt;ms.UrgentBurstFactorLuma[k],</div><div class='del'>-				&amp;mode_lib-&gt;ms.UrgentBurstFactorChroma[k],</div><div class='add'>+				&amp;mode_lib-&gt;ms.UrgentBurstFactorCursor[j][k],</div><div class='add'>+				&amp;mode_lib-&gt;ms.UrgentBurstFactorLuma[j][k],</div><div class='add'>+				&amp;mode_lib-&gt;ms.UrgentBurstFactorChroma[j][k],</div><div class='ctx'> 				&amp;mode_lib-&gt;ms.NotUrgentLatencyHiding[k]);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -8308,7 +8320,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 	if (clk_cfg-&gt;dcfclk_option != dml_use_override_freq)</div><div class='ctx'> 		locals-&gt;Dcfclk = mode_lib-&gt;ms.DCFCLK;</div><div class='ctx'> 	else</div><div class='del'>-		locals-&gt;Dcfclk = clk_cfg-&gt;dcfclk_freq_mhz;</div><div class='add'>+		locals-&gt;Dcfclk = clk_cfg-&gt;dcfclk_mhz;</div><div class='ctx'> </div><div class='ctx'> #ifdef __DML_VBA_DEBUG__</div><div class='ctx'> 	dml_print_dml_policy(&amp;mode_lib-&gt;ms.policy);</div><div class='hunk'>@@ -8361,7 +8373,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 	if (clk_cfg-&gt;dispclk_option == dml_use_required_freq)</div><div class='ctx'> 		locals-&gt;Dispclk = locals-&gt;Dispclk_calculated;</div><div class='ctx'> 	else if (clk_cfg-&gt;dispclk_option == dml_use_override_freq)</div><div class='del'>-		locals-&gt;Dispclk = clk_cfg-&gt;dispclk_freq_mhz;</div><div class='add'>+		locals-&gt;Dispclk = clk_cfg-&gt;dispclk_mhz;</div><div class='ctx'> 	else</div><div class='ctx'> 		locals-&gt;Dispclk = mode_lib-&gt;ms.state.dispclk_mhz;</div><div class='ctx'> #ifdef __DML_VBA_DEBUG__</div><div class='hunk'>@@ -8402,7 +8414,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 		if (clk_cfg-&gt;dppclk_option[k] == dml_use_required_freq)</div><div class='ctx'> 			locals-&gt;Dppclk[k] = locals-&gt;Dppclk_calculated[k];</div><div class='ctx'> 		else if (clk_cfg-&gt;dppclk_option[k] == dml_use_override_freq)</div><div class='del'>-			locals-&gt;Dppclk[k] = clk_cfg-&gt;dppclk_freq_mhz[k];</div><div class='add'>+			locals-&gt;Dppclk[k] = clk_cfg-&gt;dppclk_mhz[k];</div><div class='ctx'> 		else</div><div class='ctx'> 			locals-&gt;Dppclk[k] = mode_lib-&gt;ms.state.dppclk_mhz;</div><div class='ctx'> #ifdef __DML_VBA_DEBUG__</div><div class='hunk'>@@ -8917,7 +8929,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> </div><div class='ctx'> 	// The prefetch scheduling should only be calculated once as per AllowForPStateChangeOrStutterInVBlank requirement</div><div class='ctx'> 	// If the AllowForPStateChangeOrStutterInVBlank requirement is not strict (i.e. only try those power saving feature</div><div class='del'>-	// if possible, then will try to program for the best power saving features in order of diffculty (dram, fclk, stutter)</div><div class='add'>+	// if possible, then will try to program for the best power saving features in order of difficulty (dram, fclk, stutter)</div><div class='ctx'> 	s-&gt;iteration = 0;</div><div class='ctx'> 	s-&gt;MaxTotalRDBandwidth = 0;</div><div class='ctx'> 	s-&gt;AllPrefetchModeTested = false;</div><div class='hunk'>@@ -9180,6 +9192,8 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 			&amp;locals-&gt;FractionOfUrgentBandwidth,</div><div class='ctx'> 			&amp;s-&gt;dummy_boolean[0]); // dml_bool_t *PrefetchBandwidthSupport</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> 		if (s-&gt;VRatioPrefetchMoreThanMax != false || s-&gt;DestinationLineTimesForPrefetchLessThan2 != false) {</div><div class='ctx'> 			dml_print("DML::%s: VRatioPrefetchMoreThanMax                   = %u\n", __func__, s-&gt;VRatioPrefetchMoreThanMax);</div><div class='ctx'> 			dml_print("DML::%s: DestinationLineTimesForPrefetchLessThan2    = %u\n", __func__, s-&gt;DestinationLineTimesForPrefetchLessThan2);</div><div class='hunk'>@@ -9194,6 +9208,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> 		if (locals-&gt;PrefetchModeSupported == true &amp;&amp; mode_lib-&gt;ms.support.ImmediateFlipSupport == true) {</div><div class='ctx'> 			locals-&gt;BandwidthAvailableForImmediateFlip = CalculateBandwidthAvailableForImmediateFlip(</div><div class='ctx'> 																	mode_lib-&gt;ms.num_active_planes,</div><div class='hunk'>@@ -9460,8 +9475,10 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> </div><div class='ctx'> 		/* Copy the calculated watermarks to mp.Watermark as the getter functions are</div><div class='ctx'> 		 * implemented by the DML team to copy the calculated values from the mp.Watermark interface.</div><div class='add'>+		 * &amp;mode_lib-&gt;mp.Watermark and &amp;locals-&gt;Watermark are the same address, memcpy may lead to</div><div class='add'>+		 * unexpected behavior. memmove should be used.</div><div class='ctx'> 		 */</div><div class='del'>-		memcpy(&amp;mode_lib-&gt;mp.Watermark, CalculateWatermarks_params-&gt;Watermark, sizeof(struct Watermarks));</div><div class='add'>+		memmove(&amp;mode_lib-&gt;mp.Watermark, CalculateWatermarks_params-&gt;Watermark, sizeof(struct Watermarks));</div><div class='ctx'> </div><div class='ctx'> 		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='ctx'> 			if (mode_lib-&gt;ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {</div><div class='hunk'>@@ -9690,7 +9707,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 											+ dml_max(1.0, dml_ceil((dml_float_t) locals-&gt;WritebackDelay[k] / ((dml_float_t) mode_lib-&gt;ms.cache_display_cfg.timing.HTotal[k] / mode_lib-&gt;ms.cache_display_cfg.timing.PixelClock[k]), 1.0))</div><div class='ctx'> 											+ dml_floor(4.0 * locals-&gt;TSetup[k] / ((dml_float_t) mode_lib-&gt;ms.cache_display_cfg.timing.HTotal[k] / mode_lib-&gt;ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;</div><div class='ctx'> </div><div class='del'>-		if (((locals-&gt;VUpdateOffsetPix[k] + locals-&gt;VUpdateWidthPix[k] + locals-&gt;VReadyOffsetPix[k]) / mode_lib-&gt;ms.cache_display_cfg.timing.HTotal[k]) &lt;=</div><div class='add'>+		if (((locals-&gt;VUpdateOffsetPix[k] + locals-&gt;VUpdateWidthPix[k] + locals-&gt;VReadyOffsetPix[k]) / (double) mode_lib-&gt;ms.cache_display_cfg.timing.HTotal[k]) &lt;=</div><div class='ctx'> 			(isInterlaceTiming ?</div><div class='ctx'> 				dml_floor((mode_lib-&gt;ms.cache_display_cfg.timing.VTotal[k] - mode_lib-&gt;ms.cache_display_cfg.timing.VActive[k] - mode_lib-&gt;ms.cache_display_cfg.timing.VFrontPorch[k] - locals-&gt;VStartup[k]) / 2.0, 1.0) :</div><div class='ctx'> 				(int) (mode_lib-&gt;ms.cache_display_cfg.timing.VTotal[k] - mode_lib-&gt;ms.cache_display_cfg.timing.VActive[k] - mode_lib-&gt;ms.cache_display_cfg.timing.VFrontPorch[k] - locals-&gt;VStartup[k]))) {</div><div class='hunk'>@@ -9966,7 +9983,7 @@ void dml_core_get_row_heights(</div><div class='ctx'> 	dml_print("DML_DLG: %s: GPUVMMinPageSizeKBytes = %u\n", __func__, GPUVMMinPageSizeKBytes);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	// just suppluy with enough parameters to calculate meta and dte</div><div class='add'>+	// just supply with enough parameters to calculate meta and dte</div><div class='ctx'> 	CalculateVMAndRowBytes(</div><div class='ctx'> 			0, // dml_bool_t ViewportStationary,</div><div class='ctx'> 			1, // dml_bool_t DCCEnable,</div><div class='hunk'>@@ -10099,7 +10116,7 @@ dml_bool_t dml_mode_support(</div><div class='ctx'> /// Note: In this function, it is assumed that DCFCLK, SOCCLK freq are the state values, and mode_program will just use the DML calculated DPPCLK and DISPCLK</div><div class='ctx'> /// @param mode_lib mode_lib data struct that house all the input/output/bbox and calculation values.</div><div class='ctx'> /// @param state_idx Power state idx chosen</div><div class='del'>-/// @param display_cfg Display Congiuration</div><div class='add'>+/// @param display_cfg Display Configuration</div><div class='ctx'> /// @param call_standalone Calling mode_programming without calling mode support.  Some of the "support" struct member will be pre-calculated before doing mode programming</div><div class='ctx'> /// TODO: Add clk_cfg input, could be useful for standalone mode</div><div class='ctx'> dml_bool_t dml_mode_programming(</div><div class='hunk'>@@ -10172,7 +10189,7 @@ dml_uint_t dml_mode_support_ex(struct dml_mode_support_ex_params_st *in_out_para</div><div class='ctx'> 	result = mode_support_pwr_states(&amp;in_out_params-&gt;out_lowest_state_idx,</div><div class='ctx'> 		in_out_params-&gt;mode_lib,</div><div class='ctx'> 		in_out_params-&gt;in_display_cfg,</div><div class='del'>-		0,</div><div class='add'>+		in_out_params-&gt;in_start_state_idx,</div><div class='ctx'> 		in_out_params-&gt;mode_lib-&gt;states.num_states - 1);</div><div class='ctx'> </div><div class='ctx'> 	if (result)</div><div class='hunk'>@@ -10188,6 +10205,7 @@ dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uin</div><div class='ctx'> 	return (mode_lib-&gt;ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx] == dml_use_mall_pstate_change_phantom_pipe);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> #define dml_get_per_surface_var_func(variable, type, interval_var) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surface_idx) \</div><div class='ctx'> { \</div><div class='ctx'> 	dml_uint_t plane_idx; \</div><div class='hunk'>@@ -10214,6 +10232,7 @@ dml_get_var_func(fraction_of_urgent_bandwidth_imm_flip, dml_float_t, mode_lib-&gt;m</div><div class='ctx'> dml_get_var_func(urgent_latency, dml_float_t, mode_lib-&gt;mp.UrgentLatency);</div><div class='ctx'> dml_get_var_func(clk_dcf_deepsleep, dml_float_t, mode_lib-&gt;mp.DCFCLKDeepSleep);</div><div class='ctx'> dml_get_var_func(wm_writeback_dram_clock_change, dml_float_t, mode_lib-&gt;mp.Watermark.WritebackDRAMClockChangeWatermark);</div><div class='add'>+dml_get_var_func(wm_writeback_urgent, dml_float_t, mode_lib-&gt;mp.Watermark.WritebackUrgentWatermark);</div><div class='ctx'> dml_get_var_func(stutter_efficiency, dml_float_t, mode_lib-&gt;mp.StutterEfficiency);</div><div class='ctx'> dml_get_var_func(stutter_efficiency_no_vblank, dml_float_t, mode_lib-&gt;mp.StutterEfficiencyNotIncludingVBlank);</div><div class='ctx'> dml_get_var_func(stutter_efficiency_z8, dml_float_t, mode_lib-&gt;mp.Z8StutterEfficiency);</div><div class='hunk'>@@ -10223,9 +10242,11 @@ dml_get_var_func(stutter_efficiency_z8_bestcase, dml_float_t, mode_lib-&gt;mp.Z8Stu</div><div class='ctx'> dml_get_var_func(stutter_num_bursts_z8_bestcase, dml_float_t, mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrameBestCase);</div><div class='ctx'> dml_get_var_func(stutter_period_bestcase, dml_float_t, mode_lib-&gt;mp.StutterPeriodBestCase);</div><div class='ctx'> dml_get_var_func(urgent_extra_latency, dml_float_t, mode_lib-&gt;mp.UrgentExtraLatency);</div><div class='add'>+dml_get_var_func(fclk_change_latency, dml_float_t, mode_lib-&gt;mp.MaxActiveFCLKChangeLatencySupported);</div><div class='ctx'> dml_get_var_func(dispclk_calculated, dml_float_t, mode_lib-&gt;mp.Dispclk_calculated);</div><div class='ctx'> dml_get_var_func(total_data_read_bw, dml_float_t, mode_lib-&gt;mp.TotalDataReadBandwidth);</div><div class='ctx'> dml_get_var_func(return_bw, dml_float_t, mode_lib-&gt;ms.ReturnBW);</div><div class='add'>+dml_get_var_func(return_dram_bw, dml_float_t, mode_lib-&gt;ms.ReturnDRAMBW);</div><div class='ctx'> dml_get_var_func(tcalc, dml_float_t, mode_lib-&gt;mp.TCalc);</div><div class='ctx'> dml_get_var_func(comp_buffer_size_kbytes, dml_uint_t, mode_lib-&gt;mp.CompressedBufferSizeInkByte);</div><div class='ctx'> dml_get_var_func(pixel_chunk_size_in_kbyte, dml_uint_t, mode_lib-&gt;ms.ip.pixel_chunk_size_kbytes);</div><div class='hunk'>@@ -10313,3 +10334,4 @@ dml_get_per_surface_var_func(bigk_fragment_size, dml_uint_t, mode_lib-&gt;mp.BIGK_F</div><div class='ctx'> dml_get_per_surface_var_func(dpte_bytes_per_row, dml_uint_t, mode_lib-&gt;mp.PixelPTEBytesPerRow);</div><div class='ctx'> dml_get_per_surface_var_func(meta_bytes_per_row, dml_uint_t, mode_lib-&gt;mp.MetaRowByte);</div><div class='ctx'> dml_get_per_surface_var_func(det_buffer_size_kbytes, dml_uint_t, mode_lib-&gt;ms.DETBufferSizeInKByte);</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h<br/>index 8452485684f5..a38ed89c47a9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h</a></div><div class='hunk'>@@ -94,6 +94,7 @@ dml_get_var_decl(wm_usr_retraining, dml_float_t);</div><div class='ctx'> dml_get_var_decl(urgent_latency, dml_float_t);</div><div class='ctx'> </div><div class='ctx'> dml_get_var_decl(wm_writeback_dram_clock_change, dml_float_t);</div><div class='add'>+dml_get_var_decl(wm_writeback_urgent, dml_float_t);</div><div class='ctx'> dml_get_var_decl(stutter_efficiency_no_vblank, dml_float_t);</div><div class='ctx'> dml_get_var_decl(stutter_efficiency, dml_float_t);</div><div class='ctx'> dml_get_var_decl(stutter_efficiency_z8, dml_float_t);</div><div class='hunk'>@@ -104,10 +105,12 @@ dml_get_var_decl(stutter_num_bursts_z8_bestcase, dml_float_t);</div><div class='ctx'> dml_get_var_decl(stutter_period_bestcase, dml_float_t);</div><div class='ctx'> dml_get_var_decl(urgent_latency, dml_float_t);</div><div class='ctx'> dml_get_var_decl(urgent_extra_latency, dml_float_t);</div><div class='add'>+dml_get_var_decl(fclk_change_latency, dml_float_t);</div><div class='ctx'> dml_get_var_decl(nonurgent_latency, dml_float_t);</div><div class='ctx'> dml_get_var_decl(dispclk_calculated, dml_float_t);</div><div class='ctx'> dml_get_var_decl(total_data_read_bw, dml_float_t);</div><div class='ctx'> dml_get_var_decl(return_bw, dml_float_t);</div><div class='add'>+dml_get_var_decl(return_dram_bw, dml_float_t);</div><div class='ctx'> dml_get_var_decl(tcalc, dml_float_t);</div><div class='ctx'> dml_get_var_decl(fraction_of_urgent_bandwidth, dml_float_t);</div><div class='ctx'> dml_get_var_decl(fraction_of_urgent_bandwidth_imm_flip, dml_float_t);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h<br/>index b274bfb4225f..5b40dcdc4406 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #define __DISPLAY_MODE_CORE_STRUCT_H__</div><div class='ctx'> </div><div class='ctx'> #include "display_mode_lib_defines.h"</div><div class='add'>+#include "dml_top_display_cfg_types.h"</div><div class='ctx'> </div><div class='ctx'> enum dml_project_id {</div><div class='ctx'> 	dml_project_invalid = 0,</div><div class='hunk'>@@ -36,6 +37,8 @@ enum dml_project_id {</div><div class='ctx'> 	dml_project_dcn321 = 2,</div><div class='ctx'> 	dml_project_dcn35 = 3,</div><div class='ctx'> 	dml_project_dcn351 = 4,</div><div class='add'>+	dml_project_dcn401 = 5,</div><div class='add'>+	dml_project_dcn36 = 6,</div><div class='ctx'> };</div><div class='ctx'> enum dml_prefetch_modes {</div><div class='ctx'> 	dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0,</div><div class='hunk'>@@ -48,7 +51,9 @@ enum dml_use_mall_for_pstate_change_mode {</div><div class='ctx'> 	dml_use_mall_pstate_change_disable = 0,</div><div class='ctx'> 	dml_use_mall_pstate_change_full_frame = 1,</div><div class='ctx'> 	dml_use_mall_pstate_change_sub_viewport = 2,</div><div class='del'>-	dml_use_mall_pstate_change_phantom_pipe = 3</div><div class='add'>+	dml_use_mall_pstate_change_phantom_pipe = 3,</div><div class='add'>+	dml_use_mall_pstate_change_phantom_pipe_no_data_return = 4,</div><div class='add'>+	dml_use_mall_pstate_change_imall = 5</div><div class='ctx'> };</div><div class='ctx'> enum dml_use_mall_for_static_screen_mode {</div><div class='ctx'> 	dml_use_mall_static_screen_disable = 0,</div><div class='hunk'>@@ -170,7 +175,11 @@ enum dml_swizzle_mode {</div><div class='ctx'> 	dml_sw_256kb_z_x = 28,</div><div class='ctx'> 	dml_sw_256kb_s_x = 29,</div><div class='ctx'> 	dml_sw_256kb_d_x = 30,</div><div class='del'>-	dml_sw_256kb_r_x = 31</div><div class='add'>+	dml_sw_256kb_r_x = 31,</div><div class='add'>+	dml_sw_256b_2d = 32,</div><div class='add'>+	dml_sw_4kb_2d = 33,</div><div class='add'>+	dml_sw_64kb_2d = 34,</div><div class='add'>+	dml_sw_256kb_2d = 35</div><div class='ctx'> };</div><div class='ctx'> enum dml_lb_depth {</div><div class='ctx'> 	dml_lb_6 = 0,</div><div class='hunk'>@@ -222,24 +231,28 @@ enum dml_mpc_use_policy {</div><div class='ctx'> 	dml_mpc_disabled = 0,</div><div class='ctx'> 	dml_mpc_as_possible = 1,</div><div class='ctx'> 	dml_mpc_as_needed_for_voltage = 2,</div><div class='del'>-	dml_mpc_as_needed_for_pstate_and_voltage = 3</div><div class='add'>+	dml_mpc_as_needed_for_pstate_and_voltage = 3,</div><div class='add'>+	dml_mpc_as_needed = 4,</div><div class='add'>+	dml_mpc_2to1 = 5</div><div class='ctx'> };</div><div class='ctx'> enum dml_odm_use_policy {</div><div class='ctx'> 	dml_odm_use_policy_bypass = 0,</div><div class='ctx'> 	dml_odm_use_policy_combine_as_needed = 1,</div><div class='ctx'> 	dml_odm_use_policy_combine_2to1 = 2,</div><div class='del'>-	dml_odm_use_policy_combine_4to1 = 3,</div><div class='del'>-	dml_odm_use_policy_split_1to2 = 4,</div><div class='del'>-	dml_odm_use_policy_mso_1to2 = 5,</div><div class='del'>-	dml_odm_use_policy_mso_1to4 = 6</div><div class='add'>+	dml_odm_use_policy_combine_3to1 = 3,</div><div class='add'>+	dml_odm_use_policy_combine_4to1 = 4,</div><div class='add'>+	dml_odm_use_policy_split_1to2 = 5,</div><div class='add'>+	dml_odm_use_policy_mso_1to2 = 6,</div><div class='add'>+	dml_odm_use_policy_mso_1to4 = 7</div><div class='ctx'> };</div><div class='ctx'> enum dml_odm_mode {</div><div class='ctx'> 	dml_odm_mode_bypass = 0,</div><div class='ctx'> 	dml_odm_mode_combine_2to1 = 1,</div><div class='del'>-	dml_odm_mode_combine_4to1 = 2,</div><div class='del'>-	dml_odm_mode_split_1to2 = 3,</div><div class='del'>-	dml_odm_mode_mso_1to2 = 4,</div><div class='del'>-	dml_odm_mode_mso_1to4 = 5</div><div class='add'>+	dml_odm_mode_combine_3to1 = 2,</div><div class='add'>+	dml_odm_mode_combine_4to1 = 3,</div><div class='add'>+	dml_odm_mode_split_1to2 = 4,</div><div class='add'>+	dml_odm_mode_mso_1to2 = 5,</div><div class='add'>+	dml_odm_mode_mso_1to4 = 6</div><div class='ctx'> };</div><div class='ctx'> enum dml_writeback_configuration {</div><div class='ctx'> 	dml_whole_buffer_for_single_stream_no_interleave = 0,</div><div class='hunk'>@@ -261,7 +274,6 @@ enum dml_clk_cfg_policy {</div><div class='ctx'> 	dml_use_state_freq = 2</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> struct soc_state_bounding_box_st {</div><div class='ctx'> 	dml_float_t socclk_mhz;</div><div class='ctx'> 	dml_float_t dscclk_mhz;</div><div class='hunk'>@@ -288,6 +300,17 @@ struct soc_state_bounding_box_st {</div><div class='ctx'> 	dml_float_t fclk_change_latency_us;</div><div class='ctx'> 	dml_float_t usr_retraining_latency_us;</div><div class='ctx'> 	dml_bool_t use_ideal_dram_bw_strobe;</div><div class='add'>+	dml_float_t g6_temp_read_blackout_us;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		dml_uint_t urgent_ramp_uclk_cycles;</div><div class='add'>+		dml_uint_t trip_to_memory_uclk_cycles;</div><div class='add'>+		dml_uint_t meta_trip_to_memory_uclk_cycles;</div><div class='add'>+		dml_uint_t maximum_latency_when_urgent_uclk_cycles;</div><div class='add'>+		dml_uint_t average_latency_when_urgent_uclk_cycles;</div><div class='add'>+		dml_uint_t maximum_latency_when_non_urgent_uclk_cycles;</div><div class='add'>+		dml_uint_t average_latency_when_non_urgent_uclk_cycles;</div><div class='add'>+	}  dml_dcn401_uclk_dpm_dependent_soc_qos_params;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct soc_bounding_box_st {</div><div class='hunk'>@@ -296,7 +319,7 @@ struct soc_bounding_box_st {</div><div class='ctx'> 	dml_float_t pcierefclk_mhz;</div><div class='ctx'> 	dml_float_t refclk_mhz;</div><div class='ctx'> 	dml_float_t amclk_mhz;</div><div class='del'>-	dml_float_t max_outstanding_reqs;</div><div class='add'>+	dml_uint_t max_outstanding_reqs;</div><div class='ctx'> 	dml_float_t pct_ideal_sdp_bw_after_urgent;</div><div class='ctx'> 	dml_float_t pct_ideal_fabric_bw_after_urgent;</div><div class='ctx'> 	dml_float_t pct_ideal_dram_bw_after_urgent_pixel_only;</div><div class='hunk'>@@ -307,6 +330,16 @@ struct soc_bounding_box_st {</div><div class='ctx'> 	dml_float_t max_avg_fabric_bw_use_normal_percent;</div><div class='ctx'> 	dml_float_t max_avg_dram_bw_use_normal_percent;</div><div class='ctx'> 	dml_float_t max_avg_dram_bw_use_normal_strobe_percent;</div><div class='add'>+</div><div class='add'>+	dml_float_t svp_prefetch_pct_ideal_sdp_bw_after_urgent;</div><div class='add'>+	dml_float_t svp_prefetch_pct_ideal_fabric_bw_after_urgent;</div><div class='add'>+	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_only;</div><div class='add'>+	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_and_vm;</div><div class='add'>+	dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only;</div><div class='add'>+	dml_float_t svp_prefetch_max_avg_sdp_bw_use_normal_percent;</div><div class='add'>+	dml_float_t svp_prefetch_max_avg_fabric_bw_use_normal_percent;</div><div class='add'>+	dml_float_t svp_prefetch_max_avg_dram_bw_use_normal_percent;</div><div class='add'>+</div><div class='ctx'> 	dml_uint_t round_trip_ping_latency_dcfclk_cycles;</div><div class='ctx'> 	dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes;</div><div class='ctx'> 	dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;</div><div class='hunk'>@@ -323,6 +356,26 @@ struct soc_bounding_box_st {</div><div class='ctx'> 	dml_uint_t mall_allocated_for_dcn_mbytes;</div><div class='ctx'> 	dml_float_t dispclk_dppclk_vco_speed_mhz;</div><div class='ctx'> 	dml_bool_t do_urgent_latency_adjustment;</div><div class='add'>+</div><div class='add'>+	dml_uint_t mem_word_bytes;</div><div class='add'>+	dml_uint_t num_dcc_mcaches;</div><div class='add'>+	dml_uint_t mcache_size_bytes;</div><div class='add'>+	dml_uint_t mcache_line_size_bytes;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		dml_bool_t UseNewDCN401SOCParameters;</div><div class='add'>+		dml_uint_t df_qos_response_time_fclk_cycles;</div><div class='add'>+		dml_uint_t max_round_trip_to_furthest_cs_fclk_cycles;</div><div class='add'>+		dml_uint_t mall_overhead_fclk_cycles;</div><div class='add'>+		dml_uint_t meta_trip_adder_fclk_cycles;</div><div class='add'>+		dml_uint_t average_transport_distance_fclk_cycles;</div><div class='add'>+		dml_float_t umc_urgent_ramp_latency_margin;</div><div class='add'>+		dml_float_t umc_max_latency_margin;</div><div class='add'>+		dml_float_t umc_average_latency_margin;</div><div class='add'>+		dml_float_t fabric_max_transport_latency_margin;</div><div class='add'>+		dml_float_t fabric_average_transport_latency_margin;</div><div class='add'>+	}  dml_dcn401_soc_qos_params;</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ip_params_st {</div><div class='hunk'>@@ -514,6 +567,10 @@ struct dml_plane_cfg_st {</div><div class='ctx'> 	dml_uint_t CursorWidth[__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_uint_t CursorBPP[__DML_NUM_PLANES__];</div><div class='ctx'> </div><div class='add'>+	dml_bool_t setup_for_tdlut[__DML_NUM_PLANES__];</div><div class='add'>+	enum dml2_tdlut_addressing_mode tdlut_addressing_mode[__DML_NUM_PLANES__];</div><div class='add'>+	enum dml2_tdlut_width_mode tdlut_width_mode[__DML_NUM_PLANES__];</div><div class='add'>+</div><div class='ctx'> 	enum dml_use_mall_for_static_screen_mode UseMALLForStaticScreen[__DML_NUM_PLANES__];</div><div class='ctx'> 	enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange[__DML_NUM_PLANES__];</div><div class='ctx'> </div><div class='hunk'>@@ -574,6 +631,7 @@ struct dml_output_cfg_st {</div><div class='ctx'> 	dml_uint_t AudioSampleRate[__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_uint_t AudioSampleLayout[__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_bool_t OutputDisabled[__DML_NUM_PLANES__];</div><div class='add'>+	dml_uint_t DSCSlices[__DML_NUM_PLANES__];</div><div class='ctx'> }; // dml_timing_cfg_st;</div><div class='ctx'> </div><div class='ctx'> /// @brief Writeback Setting</div><div class='hunk'>@@ -602,6 +660,17 @@ struct dml_hw_resource_st {</div><div class='ctx'> 	dml_float_t DLGRefClkFreqMHz; /// &lt;brief DLG Global Reference timer</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/// @brief To control the clk usage for model programming</div><div class='add'>+struct dml_clk_cfg_st {</div><div class='add'>+	enum dml_clk_cfg_policy dcfclk_option; ///&lt; brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq</div><div class='add'>+	enum dml_clk_cfg_policy dispclk_option; ///&lt; brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq</div><div class='add'>+	enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__];</div><div class='add'>+</div><div class='add'>+	dml_float_t dcfclk_mhz;</div><div class='add'>+	dml_float_t dispclk_mhz;</div><div class='add'>+	dml_float_t dppclk_mhz[__DML_NUM_PLANES__];</div><div class='add'>+}; // dml_clk_cfg_st</div><div class='add'>+</div><div class='ctx'> /// @brief DML display configuration.</div><div class='ctx'> ///        Describe how to display a surface in multi-plane setup and output to different output and writeback using the specified timgin</div><div class='ctx'> struct dml_display_cfg_st {</div><div class='hunk'>@@ -614,19 +683,9 @@ struct dml_display_cfg_st {</div><div class='ctx'> 	unsigned int num_timings;</div><div class='ctx'> </div><div class='ctx'> 	struct dml_hw_resource_st hw; //&lt; brief for mode programming</div><div class='add'>+	struct dml_clk_cfg_st clk_overrides;   //&lt; brief for mode programming clk override</div><div class='ctx'> }; // dml_display_cfg_st</div><div class='ctx'> </div><div class='del'>-/// @brief To control the clk usage for model programming</div><div class='del'>-struct dml_clk_cfg_st {</div><div class='del'>-	enum dml_clk_cfg_policy dcfclk_option; ///&lt; brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq</div><div class='del'>-	enum dml_clk_cfg_policy dispclk_option; ///&lt; brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq</div><div class='del'>-	enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__];</div><div class='del'>-</div><div class='del'>-	dml_float_t dcfclk_freq_mhz;</div><div class='del'>-	dml_float_t dispclk_freq_mhz;</div><div class='del'>-	dml_float_t dppclk_freq_mhz[__DML_NUM_PLANES__];</div><div class='del'>-}; // dml_clk_cfg_st</div><div class='del'>-</div><div class='ctx'> /// @brief DML mode evaluation and programming policy</div><div class='ctx'> /// Those knobs that affect mode support and mode programming</div><div class='ctx'> struct dml_mode_eval_policy_st {</div><div class='hunk'>@@ -882,11 +941,11 @@ struct mode_support_st {</div><div class='ctx'> 	dml_uint_t meta_row_height[__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_float_t UrgLatency;</div><div class='del'>-	dml_float_t UrgentBurstFactorCursor[__DML_NUM_PLANES__];</div><div class='add'>+	dml_float_t UrgentBurstFactorCursor[2][__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_float_t UrgentBurstFactorCursorPre[__DML_NUM_PLANES__];</div><div class='del'>-	dml_float_t UrgentBurstFactorLuma[__DML_NUM_PLANES__];</div><div class='add'>+	dml_float_t UrgentBurstFactorLuma[2][__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_float_t UrgentBurstFactorLumaPre[__DML_NUM_PLANES__];</div><div class='del'>-	dml_float_t UrgentBurstFactorChroma[__DML_NUM_PLANES__];</div><div class='add'>+	dml_float_t UrgentBurstFactorChroma[2][__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_float_t UrgentBurstFactorChromaPre[__DML_NUM_PLANES__];</div><div class='ctx'> 	dml_float_t MaximumSwathWidthInLineBufferLuma;</div><div class='ctx'> 	dml_float_t MaximumSwathWidthInLineBufferChroma;</div><div class='hunk'>@@ -1834,7 +1893,7 @@ struct display_mode_lib_scratch_st {</div><div class='ctx'> 	struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output</div><div class='add'>+/// @brief Represent the overall soc/ip environment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output</div><div class='ctx'> struct display_mode_lib_st {</div><div class='ctx'> 	dml_uint_t project;</div><div class='ctx'> </div><div class='hunk'>@@ -1857,6 +1916,7 @@ struct display_mode_lib_st {</div><div class='ctx'> struct dml_mode_support_ex_params_st {</div><div class='ctx'> 	struct display_mode_lib_st *mode_lib;</div><div class='ctx'> 	const struct dml_display_cfg_st *in_display_cfg;</div><div class='add'>+	dml_uint_t in_start_state_idx;</div><div class='ctx'> 	dml_uint_t out_lowest_state_idx;</div><div class='ctx'> 	struct dml_mode_support_info_st *out_evaluation_info;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h<br/>index de63364be01d..e574c81edf5e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h</a></div><div class='hunk'>@@ -41,6 +41,7 @@</div><div class='ctx'> #define DCN_DML__VM_PRESENT__1 1</div><div class='ctx'> #define DCN_DML__HOST_VM_PRESENT 1</div><div class='ctx'> #define DCN_DML__HOST_VM_PRESENT__1 1</div><div class='add'>+#define DCN_DML__DWB 1</div><div class='ctx'> </div><div class='ctx'> #include "dml_depedencies.h"</div><div class='ctx'> </div><div class='hunk'>@@ -51,7 +52,7 @@</div><div class='ctx'> #define __DML_VBA_DEBUG__</div><div class='ctx'> #define __DML_VBA_ENABLE_INLINE_CHECK_                  0</div><div class='ctx'> #define __DML_VBA_MIN_VSTARTUP__                        9       //&lt;brief At which vstartup the DML start to try if the mode can be supported</div><div class='del'>-#define __DML_ARB_TO_RET_DELAY__                        7 + 95  //&lt;brief Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)</div><div class='add'>+#define __DML_ARB_TO_RET_DELAY__                        (7 + 95)  //&lt;brief Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)</div><div class='ctx'> #define __DML_MIN_DCFCLK_FACTOR__                       1.15    //&lt;brief fudge factor for min dcfclk calclation</div><div class='ctx'> #define __DML_MAX_VRATIO_PRE__                          4.0     //&lt;brief Prefetch schedule max vratio</div><div class='ctx'> #define __DML_MAX_VRATIO_PRE_OTO__                      4.0     //&lt;brief Prefetch schedule max vratio for one to one scheduling calculation for prefetch</div><div class='hunk'>@@ -59,6 +60,7 @@</div><div class='ctx'> #define __DML_NUM_PLANES__                              DCN_DML__NUM_PLANE</div><div class='ctx'> #define __DML_NUM_CURSORS__                             DCN_DML__NUM_CURSOR</div><div class='ctx'> #define __DML_DPP_INVALID__                             0</div><div class='add'>+#define __DML_NUM_DMB__                                 DCN_DML__DWB</div><div class='ctx'> #define __DML_PIPE_NO_PLANE__                           99</div><div class='ctx'> </div><div class='ctx'> #define __DML_MAX_STATE_ARRAY_SIZE__        DCN_DML__NUM_PWR_STATE</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c<br/>index c247aee89caf..89890c88fd66 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c</a></div><div class='hunk'>@@ -690,12 +690,12 @@ __DML_DLL_EXPORT__ void dml_print_clk_cfg(const struct dml_clk_cfg_st *clk_cfg)</div><div class='ctx'> 	dml_print("DML: clk_cfg: dcfclk_option = %d\n", clk_cfg-&gt;dcfclk_option);</div><div class='ctx'> 	dml_print("DML: clk_cfg: dispclk_option = %d\n", clk_cfg-&gt;dispclk_option);</div><div class='ctx'> </div><div class='del'>-	dml_print("DML: clk_cfg: dcfclk_freq_mhz = %f\n", clk_cfg-&gt;dcfclk_freq_mhz);</div><div class='del'>-	dml_print("DML: clk_cfg: dispclk_freq_mhz = %f\n", clk_cfg-&gt;dispclk_freq_mhz);</div><div class='add'>+	dml_print("DML: clk_cfg: dcfclk_mhz = %f\n", clk_cfg-&gt;dcfclk_mhz);</div><div class='add'>+	dml_print("DML: clk_cfg: dispclk_mhz = %f\n", clk_cfg-&gt;dispclk_mhz);</div><div class='ctx'> </div><div class='ctx'> 	for (dml_uint_t i = 0; i &lt; DCN_DML__NUM_PLANE; i++) {</div><div class='ctx'> 		dml_print("DML: clk_cfg: i=%d, dppclk_option = %d\n", i, clk_cfg-&gt;dppclk_option[i]);</div><div class='del'>-		dml_print("DML: clk_cfg: i=%d, dppclk_freq_mhz = %f\n", i, clk_cfg-&gt;dppclk_freq_mhz[i]);</div><div class='add'>+		dml_print("DML: clk_cfg: i=%d, dppclk_mhz = %f\n", i, clk_cfg-&gt;dppclk_mhz[i]);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h<br/>index 113b0265e1d1..a82b49cf7fb0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h</a></div><div class='hunk'>@@ -30,7 +30,6 @@</div><div class='ctx'> #include "display_mode_core_structs.h"</div><div class='ctx'> #include "cmntypes.h"</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> #include "dml_assert.h"</div><div class='ctx'> #include "dml_logging.h"</div><div class='ctx'> </div><div class='hunk'>@@ -72,5 +71,4 @@ __DML_DLL_EXPORT__ dml_uint_t dml_get_plane_idx(const struct display_mode_lib_st</div><div class='ctx'> __DML_DLL_EXPORT__ dml_uint_t dml_get_pipe_idx(const struct display_mode_lib_st *mode_lib, dml_uint_t plane_idx);</div><div class='ctx'> __DML_DLL_EXPORT__ void       dml_calc_pipe_plane_mapping(const struct dml_hw_resource_st *hw, dml_uint_t *pipe_plane);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c<br/>new file mode 100644<br/>index 000000000000..bf5e7f4e0416<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c</a></div><div class='hunk'>@@ -0,0 +1,929 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml21_wrapper.h"</div><div class='add'>+#include "dml2_core_dcn4_calcs.h"</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml2_internal_types.h"</div><div class='add'>+#include "dml21_utils.h"</div><div class='add'>+#include "dml21_translation_helper.h"</div><div class='add'>+#include "soc_and_ip_translator.h"</div><div class='add'>+</div><div class='add'>+static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options,</div><div class='add'>+		const struct dc *in_dc,</div><div class='add'>+		const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	bool disable_fams2 = !in_dc-&gt;debug.fams2_config.bits.enable;</div><div class='add'>+</div><div class='add'>+	/* ODM options */</div><div class='add'>+	pmo_options-&gt;disable_dyn_odm = !config-&gt;minimize_dispclk_using_odm;</div><div class='add'>+	pmo_options-&gt;disable_dyn_odm_for_multi_stream = true;</div><div class='add'>+	pmo_options-&gt;disable_dyn_odm_for_stream_with_svp = true;</div><div class='add'>+</div><div class='add'>+	pmo_options-&gt;disable_vblank = ((in_dc-&gt;debug.dml21_disable_pstate_method_mask &gt;&gt; 1) &amp; 1);</div><div class='add'>+</div><div class='add'>+	/* NOTE: DRR and SubVP Require FAMS2 */</div><div class='add'>+	pmo_options-&gt;disable_svp = ((in_dc-&gt;debug.dml21_disable_pstate_method_mask &gt;&gt; 2) &amp; 1) ||</div><div class='add'>+			in_dc-&gt;debug.force_disable_subvp ||</div><div class='add'>+			disable_fams2;</div><div class='add'>+	pmo_options-&gt;disable_drr_clamped = ((in_dc-&gt;debug.dml21_disable_pstate_method_mask &gt;&gt; 3) &amp; 1) ||</div><div class='add'>+			disable_fams2;</div><div class='add'>+	pmo_options-&gt;disable_drr_var = ((in_dc-&gt;debug.dml21_disable_pstate_method_mask &gt;&gt; 4) &amp; 1) ||</div><div class='add'>+			disable_fams2;</div><div class='add'>+	pmo_options-&gt;disable_fams2 = disable_fams2;</div><div class='add'>+</div><div class='add'>+	pmo_options-&gt;disable_drr_var_when_var_active = in_dc-&gt;debug.disable_fams_gaming == INGAME_FAMS_DISABLE ||</div><div class='add'>+			in_dc-&gt;debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY;</div><div class='add'>+	pmo_options-&gt;disable_drr_clamped_when_var_active = in_dc-&gt;debug.disable_fams_gaming == INGAME_FAMS_DISABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_project_id dml21_dcn_revision_to_dml2_project_id(enum dce_version dcn_version)</div><div class='add'>+{</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+	switch (dcn_version) {</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		project_id = dml2_project_dcn4x_stage2_auto_drr_svp;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		project_id = dml2_project_invalid;</div><div class='add'>+		DC_ERR("unsupported dcn version for DML21!");</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return project_id;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init,</div><div class='add'>+		const struct dml2_configuration_options *config,</div><div class='add'>+		const struct dc *in_dc)</div><div class='add'>+{</div><div class='add'>+	dml_init-&gt;options.project_id = dml21_dcn_revision_to_dml2_project_id(in_dc-&gt;ctx-&gt;dce_version);</div><div class='add'>+</div><div class='add'>+	if (config-&gt;use_native_soc_bb_construction) {</div><div class='add'>+		in_dc-&gt;soc_and_ip_translator-&gt;translator_funcs-&gt;get_soc_bb(&amp;dml_init-&gt;soc_bb, in_dc, config);</div><div class='add'>+		in_dc-&gt;soc_and_ip_translator-&gt;translator_funcs-&gt;get_ip_caps(&amp;dml_init-&gt;ip_caps);</div><div class='add'>+	} else {</div><div class='add'>+		dml_init-&gt;soc_bb = config-&gt;external_socbb_ip_params-&gt;soc_bb;</div><div class='add'>+		dml_init-&gt;ip_caps = config-&gt;external_socbb_ip_params-&gt;ip_params;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dml21_populate_pmo_options(&amp;dml_init-&gt;options.pmo_options, in_dc, config);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	unsigned int max_hw_v_total = stream-&gt;ctx-&gt;dc-&gt;caps.max_v_total;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;ctx-&gt;dc-&gt;caps.vtotal_limited_by_fp2) {</div><div class='add'>+		max_hw_v_total -= stream-&gt;timing.v_front_porch + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return max_hw_v_total;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz;</div><div class='add'>+	uint32_t pix_clk_100hz;</div><div class='add'>+</div><div class='add'>+	timing-&gt;h_active = stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right + pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='add'>+	timing-&gt;v_active = stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_bottom + stream-&gt;timing.v_border_top;</div><div class='add'>+	timing-&gt;h_front_porch = stream-&gt;timing.h_front_porch;</div><div class='add'>+	timing-&gt;v_front_porch = stream-&gt;timing.v_front_porch;</div><div class='add'>+	timing-&gt;pixel_clock_khz = stream-&gt;timing.pix_clk_100hz / 10;</div><div class='add'>+	if (pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding != 0)</div><div class='add'>+		timing-&gt;pixel_clock_khz = pipe_ctx-&gt;dsc_padding_params.dsc_pix_clk_100hz / 10;</div><div class='add'>+	if (stream-&gt;timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)</div><div class='add'>+		timing-&gt;pixel_clock_khz *= 2;</div><div class='add'>+	timing-&gt;h_total = stream-&gt;timing.h_total + pipe_ctx-&gt;dsc_padding_params.dsc_htotal_padding;</div><div class='add'>+	timing-&gt;v_total = stream-&gt;timing.v_total;</div><div class='add'>+	timing-&gt;h_sync_width = stream-&gt;timing.h_sync_width;</div><div class='add'>+	timing-&gt;interlaced = stream-&gt;timing.flags.INTERLACE;</div><div class='add'>+</div><div class='add'>+	hblank_start = stream-&gt;timing.h_total - stream-&gt;timing.h_front_porch;</div><div class='add'>+</div><div class='add'>+	timing-&gt;h_blank_end = hblank_start - stream-&gt;timing.h_addressable - pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding</div><div class='add'>+		- stream-&gt;timing.h_border_left - stream-&gt;timing.h_border_right;</div><div class='add'>+</div><div class='add'>+	if (hblank_start &lt; stream-&gt;timing.h_addressable)</div><div class='add'>+		timing-&gt;h_blank_end = 0;</div><div class='add'>+</div><div class='add'>+	vblank_start = stream-&gt;timing.v_total - stream-&gt;timing.v_front_porch;</div><div class='add'>+</div><div class='add'>+	timing-&gt;v_blank_end = vblank_start - stream-&gt;timing.v_addressable</div><div class='add'>+		- stream-&gt;timing.v_border_top - stream-&gt;timing.v_border_bottom;</div><div class='add'>+</div><div class='add'>+	timing-&gt;drr_config.enabled = stream-&gt;ignore_msa_timing_param;</div><div class='add'>+	timing-&gt;drr_config.drr_active_variable = stream-&gt;vrr_active_variable;</div><div class='add'>+	timing-&gt;drr_config.drr_active_fixed = stream-&gt;vrr_active_fixed;</div><div class='add'>+	timing-&gt;drr_config.disallowed = !stream-&gt;allow_freesync;</div><div class='add'>+</div><div class='add'>+	/* limit min refresh rate to DC cap */</div><div class='add'>+	min_hardware_refresh_in_uhz = stream-&gt;timing.min_refresh_in_uhz;</div><div class='add'>+	if (stream-&gt;ctx-&gt;dc-&gt;caps.max_v_total != 0) {</div><div class='add'>+		if (pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding != 0) {</div><div class='add'>+			pix_clk_100hz = pipe_ctx-&gt;dsc_padding_params.dsc_pix_clk_100hz;</div><div class='add'>+		} else {</div><div class='add'>+			pix_clk_100hz = stream-&gt;timing.pix_clk_100hz;</div><div class='add'>+		}</div><div class='add'>+		min_hardware_refresh_in_uhz = div64_u64((pix_clk_100hz * 100000000ULL),</div><div class='add'>+				(timing-&gt;h_total * (long long)calc_max_hardware_v_total(stream)));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	timing-&gt;drr_config.min_refresh_uhz = max(stream-&gt;timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz);</div><div class='add'>+</div><div class='add'>+	if (dml_ctx-&gt;config.callbacks.get_max_flickerless_instant_vtotal_increase &amp;&amp;</div><div class='add'>+			stream-&gt;ctx-&gt;dc-&gt;config.enable_fpo_flicker_detection == 1)</div><div class='add'>+		timing-&gt;drr_config.max_instant_vtotal_delta = dml_ctx-&gt;config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);</div><div class='add'>+	else</div><div class='add'>+		timing-&gt;drr_config.max_instant_vtotal_delta = 0;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;timing.flags.DSC) {</div><div class='add'>+		timing-&gt;dsc.enable = dml2_dsc_enable;</div><div class='add'>+		timing-&gt;dsc.overrides.num_slices = stream-&gt;timing.dsc_cfg.num_slices_h;</div><div class='add'>+		timing-&gt;dsc.dsc_compressed_bpp_x16 = stream-&gt;timing.dsc_cfg.bits_per_pixel;</div><div class='add'>+	} else</div><div class='add'>+		timing-&gt;dsc.enable = dml2_dsc_disable;</div><div class='add'>+</div><div class='add'>+	switch (stream-&gt;timing.display_color_depth) {</div><div class='add'>+	case COLOR_DEPTH_666:</div><div class='add'>+		timing-&gt;bpc = 6;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_888:</div><div class='add'>+		timing-&gt;bpc = 8;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_101010:</div><div class='add'>+		timing-&gt;bpc = 10;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_121212:</div><div class='add'>+		timing-&gt;bpc = 12;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_141414:</div><div class='add'>+		timing-&gt;bpc = 14;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_161616:</div><div class='add'>+		timing-&gt;bpc = 16;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_999:</div><div class='add'>+		timing-&gt;bpc = 9;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_111111:</div><div class='add'>+		timing-&gt;bpc = 11;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		timing-&gt;bpc = 8;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	timing-&gt;vblank_nom = timing-&gt;v_total - timing-&gt;v_active;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_output_config_from_stream_state(struct dml2_link_output_cfg *output,</div><div class='add'>+		struct dc_stream_state *stream, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	output-&gt;output_dp_lane_count = 4;</div><div class='add'>+</div><div class='add'>+	switch (stream-&gt;signal) {</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT_MST:</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='add'>+		output-&gt;output_encoder = dml2_dp;</div><div class='add'>+		if (check_dp2p0_output_encoder(pipe))</div><div class='add'>+			output-&gt;output_encoder = dml2_dp2p0;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_EDP:</div><div class='add'>+		output-&gt;output_encoder = dml2_edp;</div><div class='add'>+		break;</div><div class='add'>+	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='add'>+	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+	case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='add'>+		output-&gt;output_encoder = dml2_hdmi;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+			output-&gt;output_encoder = dml2_dp;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (stream-&gt;timing.pixel_encoding) {</div><div class='add'>+	case PIXEL_ENCODING_RGB:</div><div class='add'>+	case PIXEL_ENCODING_YCBCR444:</div><div class='add'>+		output-&gt;output_format = dml2_444;</div><div class='add'>+		break;</div><div class='add'>+	case PIXEL_ENCODING_YCBCR420:</div><div class='add'>+		output-&gt;output_format = dml2_420;</div><div class='add'>+		break;</div><div class='add'>+	case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+		if (stream-&gt;timing.flags.DSC &amp;&amp; !stream-&gt;timing.dsc_cfg.ycbcr422_simple)</div><div class='add'>+			output-&gt;output_format = dml2_n422;</div><div class='add'>+		else</div><div class='add'>+			output-&gt;output_format = dml2_s422;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		output-&gt;output_format = dml2_444;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (stream-&gt;signal) {</div><div class='add'>+	case SIGNAL_TYPE_NONE:</div><div class='add'>+	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+	case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='add'>+	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='add'>+	case SIGNAL_TYPE_LVDS:</div><div class='add'>+	case SIGNAL_TYPE_RGB:</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='add'>+	case SIGNAL_TYPE_DISPLAY_PORT_MST:</div><div class='add'>+	case SIGNAL_TYPE_EDP:</div><div class='add'>+	case SIGNAL_TYPE_VIRTUAL:</div><div class='add'>+	default:</div><div class='add'>+		output-&gt;output_dp_link_rate = dml2_dp_rate_na;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	output-&gt;audio_sample_layout = stream-&gt;audio_info.modes-&gt;sample_size;</div><div class='add'>+	output-&gt;audio_sample_rate = stream-&gt;audio_info.modes-&gt;max_bit_rate;</div><div class='add'>+	output-&gt;output_disabled = true;</div><div class='add'>+</div><div class='add'>+	//TODO : New to DML2.1. How do we populate this ?</div><div class='add'>+	// output-&gt;validate_output</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_stream_overrides_from_stream_state(</div><div class='add'>+		struct dml2_stream_parameters *stream_desc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_stream_status *stream_status)</div><div class='add'>+{</div><div class='add'>+	switch (stream-&gt;debug.force_odm_combine_segments) {</div><div class='add'>+	case 0:</div><div class='add'>+		stream_desc-&gt;overrides.odm_mode = dml2_odm_mode_auto;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		stream_desc-&gt;overrides.odm_mode = dml2_odm_mode_bypass;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		stream_desc-&gt;overrides.odm_mode = dml2_odm_mode_combine_2to1;</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		stream_desc-&gt;overrides.odm_mode = dml2_odm_mode_combine_3to1;</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		stream_desc-&gt;overrides.odm_mode = dml2_odm_mode_combine_4to1;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		stream_desc-&gt;overrides.odm_mode =  dml2_odm_mode_auto;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	if (!stream-&gt;ctx-&gt;dc-&gt;debug.enable_single_display_2to1_odm_policy ||</div><div class='add'>+			stream-&gt;debug.force_odm_combine_segments &gt; 0)</div><div class='add'>+		stream_desc-&gt;overrides.disable_dynamic_odm = true;</div><div class='add'>+	stream_desc-&gt;overrides.disable_subvp = stream-&gt;ctx-&gt;dc-&gt;debug.force_disable_subvp ||</div><div class='add'>+			stream-&gt;hw_cursor_req ||</div><div class='add'>+			stream_status-&gt;mall_stream_config.cursor_size_limit_subvp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_swizzle_mode gfx_addr3_to_dml2_swizzle_mode(enum swizzle_mode_addr3_values addr3_mode)</div><div class='add'>+{</div><div class='add'>+	enum dml2_swizzle_mode dml2_mode = dml2_sw_linear;</div><div class='add'>+</div><div class='add'>+	switch (addr3_mode) {</div><div class='add'>+	case DC_ADDR3_SW_LINEAR:</div><div class='add'>+		dml2_mode = dml2_sw_linear;</div><div class='add'>+		break;</div><div class='add'>+	case DC_ADDR3_SW_256B_2D:</div><div class='add'>+		dml2_mode = dml2_sw_256b_2d;</div><div class='add'>+		break;</div><div class='add'>+	case DC_ADDR3_SW_4KB_2D:</div><div class='add'>+		dml2_mode = dml2_sw_4kb_2d;</div><div class='add'>+		break;</div><div class='add'>+	case DC_ADDR3_SW_64KB_2D:</div><div class='add'>+		dml2_mode = dml2_sw_64kb_2d;</div><div class='add'>+		break;</div><div class='add'>+	case DC_ADDR3_SW_256KB_2D:</div><div class='add'>+		dml2_mode = dml2_sw_256kb_2d;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		/* invalid swizzle mode for DML2.1 */</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		dml2_mode = dml2_sw_linear;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dml2_mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_swizzle_mode gfx9_to_dml2_swizzle_mode(enum swizzle_mode_values gfx9_mode)</div><div class='add'>+{</div><div class='add'>+	enum dml2_swizzle_mode dml2_mode = dml2_sw_64kb_2d;</div><div class='add'>+</div><div class='add'>+	switch (gfx9_mode) {</div><div class='add'>+	case DC_SW_LINEAR:</div><div class='add'>+		dml2_mode = dml2_sw_linear;</div><div class='add'>+		break;</div><div class='add'>+	case DC_SW_256_D:</div><div class='add'>+	case DC_SW_256_R:</div><div class='add'>+		dml2_mode = dml2_sw_256b_2d;</div><div class='add'>+		break;</div><div class='add'>+	case DC_SW_4KB_D:</div><div class='add'>+	case DC_SW_4KB_R:</div><div class='add'>+	case DC_SW_4KB_R_X:</div><div class='add'>+		dml2_mode = dml2_sw_4kb_2d;</div><div class='add'>+		break;</div><div class='add'>+	case DC_SW_64KB_D:</div><div class='add'>+	case DC_SW_64KB_D_X:</div><div class='add'>+	case DC_SW_64KB_R:</div><div class='add'>+	case DC_SW_64KB_R_X:</div><div class='add'>+		dml2_mode = dml2_sw_64kb_2d;</div><div class='add'>+		break;</div><div class='add'>+	case DC_SW_256B_S:</div><div class='add'>+	case DC_SW_4KB_S:</div><div class='add'>+	case DC_SW_64KB_S:</div><div class='add'>+	case DC_SW_VAR_S:</div><div class='add'>+	case DC_SW_VAR_D:</div><div class='add'>+	case DC_SW_VAR_R:</div><div class='add'>+	case DC_SW_64KB_S_T:</div><div class='add'>+	case DC_SW_64KB_D_T:</div><div class='add'>+	case DC_SW_4KB_S_X:</div><div class='add'>+	case DC_SW_4KB_D_X:</div><div class='add'>+	case DC_SW_64KB_S_X:</div><div class='add'>+	case DC_SW_VAR_S_X:</div><div class='add'>+	case DC_SW_VAR_D_X:</div><div class='add'>+	case DC_SW_VAR_R_X:</div><div class='add'>+	default:</div><div class='add'>+		/*</div><div class='add'>+		 * invalid swizzle mode for DML2.1. This could happen because</div><div class='add'>+		 * DML21 is not intended to be used by N-1 in production. To</div><div class='add'>+		 * properly filter out unsupported swizzle modes, we will need</div><div class='add'>+		 * to fix capability reporting when DML2.1 is used for N-1 in</div><div class='add'>+		 * dc. So DML will only receive DML21 supported swizzle modes.</div><div class='add'>+		 * This implementation is not added and has a low value because</div><div class='add'>+		 * the supported swizzle modes should already cover most of our</div><div class='add'>+		 * N-1 test cases.</div><div class='add'>+		 */</div><div class='add'>+		return dml2_sw_64kb_2d;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dml2_mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_dummy_surface_cfg(struct dml2_surface_cfg *surface, const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	surface-&gt;plane0.width = stream-&gt;timing.h_addressable;</div><div class='add'>+	surface-&gt;plane0.height = stream-&gt;timing.v_addressable;</div><div class='add'>+	surface-&gt;plane1.width = stream-&gt;timing.h_addressable;</div><div class='add'>+	surface-&gt;plane1.height = stream-&gt;timing.v_addressable;</div><div class='add'>+	surface-&gt;plane0.pitch = ((surface-&gt;plane0.width + 127) / 128) * 128;</div><div class='add'>+	surface-&gt;plane1.pitch = 0;</div><div class='add'>+	surface-&gt;dcc.enable = false;</div><div class='add'>+	surface-&gt;dcc.informative.dcc_rate_plane0 = 1.0;</div><div class='add'>+	surface-&gt;dcc.informative.dcc_rate_plane1 = 1.0;</div><div class='add'>+	surface-&gt;dcc.informative.fraction_of_zero_size_request_plane0 = 0;</div><div class='add'>+	surface-&gt;dcc.informative.fraction_of_zero_size_request_plane1 = 0;</div><div class='add'>+	surface-&gt;tiling = dml2_sw_64kb_2d;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_dummy_plane_cfg(struct dml2_plane_parameters *plane, const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	unsigned int width, height;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;timing.h_addressable &gt; 3840)</div><div class='add'>+		width = 3840;</div><div class='add'>+	else</div><div class='add'>+		width = stream-&gt;timing.h_addressable;	// 4K max</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;timing.v_addressable &gt; 2160)</div><div class='add'>+		height = 2160;</div><div class='add'>+	else</div><div class='add'>+		height = stream-&gt;timing.v_addressable;	// 4K max</div><div class='add'>+</div><div class='add'>+	plane-&gt;cursor.cursor_bpp = 32;</div><div class='add'>+</div><div class='add'>+	plane-&gt;cursor.cursor_width = 256;</div><div class='add'>+	plane-&gt;cursor.num_cursors = 1;</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.viewport.plane0.width = width;</div><div class='add'>+	plane-&gt;composition.viewport.plane0.height = height;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.width = 0;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.height = 0;</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.viewport.stationary = false;</div><div class='add'>+	plane-&gt;composition.viewport.plane0.x_start = 0;</div><div class='add'>+	plane-&gt;composition.viewport.plane0.y_start = 0;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.x_start = 0;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.y_start = 0;</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.scaler_info.enabled = false;</div><div class='add'>+	plane-&gt;composition.rotation_angle = dml2_rotation_0;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane0.h_ratio = 1.0;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane0.v_ratio = 1.0;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane1.h_ratio = 0;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane1.v_ratio = 0;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane0.h_taps = 1;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane0.v_taps = 1;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane1.h_taps = 0;</div><div class='add'>+	plane-&gt;composition.scaler_info.plane1.v_taps = 0;</div><div class='add'>+	plane-&gt;composition.scaler_info.rect_out_width = width;</div><div class='add'>+	plane-&gt;pixel_format = dml2_444_32;</div><div class='add'>+</div><div class='add'>+	plane-&gt;dynamic_meta_data.enable = false;</div><div class='add'>+	plane-&gt;overrides.gpuvm_min_page_size_kbytes = 256;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_surface_config_from_plane_state(</div><div class='add'>+		const struct dc *in_dc,</div><div class='add'>+		struct dml2_surface_cfg *surface,</div><div class='add'>+		const struct dc_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	surface-&gt;plane0.pitch = plane_state-&gt;plane_size.surface_pitch;</div><div class='add'>+	surface-&gt;plane1.pitch = plane_state-&gt;plane_size.chroma_pitch;</div><div class='add'>+	surface-&gt;plane0.height = plane_state-&gt;plane_size.surface_size.height;</div><div class='add'>+	surface-&gt;plane0.width = plane_state-&gt;plane_size.surface_size.width;</div><div class='add'>+	surface-&gt;plane1.height = plane_state-&gt;plane_size.chroma_size.height;</div><div class='add'>+	surface-&gt;plane1.width = plane_state-&gt;plane_size.chroma_size.width;</div><div class='add'>+	surface-&gt;dcc.enable = plane_state-&gt;dcc.enable;</div><div class='add'>+	surface-&gt;dcc.informative.dcc_rate_plane0 = 1.0;</div><div class='add'>+	surface-&gt;dcc.informative.dcc_rate_plane1 = 1.0;</div><div class='add'>+	surface-&gt;dcc.informative.fraction_of_zero_size_request_plane0 = plane_state-&gt;dcc.independent_64b_blks;</div><div class='add'>+	surface-&gt;dcc.informative.fraction_of_zero_size_request_plane1 = plane_state-&gt;dcc.independent_64b_blks_c;</div><div class='add'>+	surface-&gt;dcc.plane0.pitch = plane_state-&gt;dcc.meta_pitch;</div><div class='add'>+	surface-&gt;dcc.plane1.pitch = plane_state-&gt;dcc.meta_pitch_c;</div><div class='add'>+</div><div class='add'>+	// Update swizzle / array mode based on the gfx_format</div><div class='add'>+	switch (plane_state-&gt;tiling_info.gfxversion) {</div><div class='add'>+	case DcGfxVersion7:</div><div class='add'>+	case DcGfxVersion8:</div><div class='add'>+		break;</div><div class='add'>+	case DcGfxVersion9:</div><div class='add'>+	case DcGfxVersion10:</div><div class='add'>+	case DcGfxVersion11:</div><div class='add'>+		surface-&gt;tiling = gfx9_to_dml2_swizzle_mode(plane_state-&gt;tiling_info.gfx9.swizzle);</div><div class='add'>+		break;</div><div class='add'>+	case DcGfxAddr3:</div><div class='add'>+		surface-&gt;tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state-&gt;tiling_info.gfx_addr3.swizzle);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct scaler_data *get_scaler_data_for_plane(</div><div class='add'>+		struct dml2_context *dml_ctx,</div><div class='add'>+		const struct dc_plane_state *in,</div><div class='add'>+		const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct pipe_ctx *temp_pipe = &amp;dml_ctx-&gt;v21.scratch.temp_pipe;</div><div class='add'>+</div><div class='add'>+	memset(temp_pipe, 0, sizeof(struct pipe_ctx));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++)	{</div><div class='add'>+		const struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;plane_state == in &amp;&amp; !pipe-&gt;prev_odm_pipe) {</div><div class='add'>+			temp_pipe-&gt;stream = pipe-&gt;stream;</div><div class='add'>+			temp_pipe-&gt;plane_state = pipe-&gt;plane_state;</div><div class='add'>+			temp_pipe-&gt;plane_res.scl_data.taps = pipe-&gt;plane_res.scl_data.taps;</div><div class='add'>+			temp_pipe-&gt;stream_res = pipe-&gt;stream_res;</div><div class='add'>+			temp_pipe-&gt;dsc_padding_params.dsc_hactive_padding = pipe-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='add'>+			temp_pipe-&gt;dsc_padding_params.dsc_htotal_padding = pipe-&gt;dsc_padding_params.dsc_htotal_padding;</div><div class='add'>+			temp_pipe-&gt;dsc_padding_params.dsc_pix_clk_100hz = pipe-&gt;dsc_padding_params.dsc_pix_clk_100hz;</div><div class='add'>+			dml_ctx-&gt;config.callbacks.build_scaling_params(temp_pipe);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ASSERT(i &lt; MAX_PIPES);</div><div class='add'>+	return &amp;temp_pipe-&gt;plane_res.scl_data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dml_ctx,</div><div class='add'>+		struct dml2_plane_parameters *plane, const struct dc_plane_state *plane_state,</div><div class='add'>+		const struct dc_state *context, unsigned int stream_index)</div><div class='add'>+{</div><div class='add'>+	const struct scaler_data *scaler_data = get_scaler_data_for_plane(dml_ctx, plane_state, context);</div><div class='add'>+	struct dc_stream_state *stream = context-&gt;streams[stream_index];</div><div class='add'>+</div><div class='add'>+	plane-&gt;cursor.cursor_bpp = 32;</div><div class='add'>+	plane-&gt;cursor.cursor_width = 256;</div><div class='add'>+	plane-&gt;cursor.num_cursors = 1;</div><div class='add'>+</div><div class='add'>+	switch (plane_state-&gt;format) {</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:</div><div class='add'>+		plane-&gt;pixel_format = dml2_420_8;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:</div><div class='add'>+		plane-&gt;pixel_format = dml2_420_10;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:</div><div class='add'>+		plane-&gt;pixel_format = dml2_444_64;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:</div><div class='add'>+		plane-&gt;pixel_format = dml2_444_16;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:</div><div class='add'>+		plane-&gt;pixel_format = dml2_444_8;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:</div><div class='add'>+		plane-&gt;pixel_format = dml2_rgbe_alpha;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		plane-&gt;pixel_format = dml2_444_32;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.viewport.plane0.height = scaler_data-&gt;viewport.height;</div><div class='add'>+	plane-&gt;composition.viewport.plane0.width = scaler_data-&gt;viewport.width;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.height = scaler_data-&gt;viewport_c.height;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.width = scaler_data-&gt;viewport_c.width;</div><div class='add'>+	plane-&gt;composition.viewport.plane0.x_start = scaler_data-&gt;viewport.x;</div><div class='add'>+	plane-&gt;composition.viewport.plane0.y_start = scaler_data-&gt;viewport.y;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.x_start = scaler_data-&gt;viewport_c.x;</div><div class='add'>+	plane-&gt;composition.viewport.plane1.y_start = scaler_data-&gt;viewport_c.y;</div><div class='add'>+	plane-&gt;composition.viewport.stationary = false;</div><div class='add'>+	plane-&gt;composition.scaler_info.enabled = scaler_data-&gt;ratios.horz.value != dc_fixpt_one.value ||</div><div class='add'>+		scaler_data-&gt;ratios.horz_c.value != dc_fixpt_one.value ||</div><div class='add'>+		scaler_data-&gt;ratios.vert.value != dc_fixpt_one.value ||</div><div class='add'>+		scaler_data-&gt;ratios.vert_c.value != dc_fixpt_one.value;</div><div class='add'>+</div><div class='add'>+	if (!scaler_data-&gt;taps.h_taps) {</div><div class='add'>+		/* Above logic determines scaling should be enabled even when there are no taps for</div><div class='add'>+		 * certain cases. Hence do corrective active and disable scaling.</div><div class='add'>+		 */</div><div class='add'>+		plane-&gt;composition.scaler_info.enabled = false;</div><div class='add'>+	} else if ((plane_state-&gt;ctx-&gt;dc-&gt;config.use_spl == true) &amp;&amp;</div><div class='add'>+		(plane-&gt;composition.scaler_info.enabled == false)) {</div><div class='add'>+		/* To enable sharpener for 1:1, scaler must be enabled.  If use_spl is set, then</div><div class='add'>+		 *  allow case where ratio is 1 but taps &gt; 1</div><div class='add'>+		 */</div><div class='add'>+		if ((scaler_data-&gt;taps.h_taps &gt; 1) || (scaler_data-&gt;taps.v_taps &gt; 1) ||</div><div class='add'>+			(scaler_data-&gt;taps.h_taps_c &gt; 1) || (scaler_data-&gt;taps.v_taps_c &gt; 1))</div><div class='add'>+			plane-&gt;composition.scaler_info.enabled = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* always_scale is only used for debug purposes not used in production but has to be</div><div class='add'>+	 * maintained for certain complainces. */</div><div class='add'>+	if (plane_state-&gt;ctx-&gt;dc-&gt;debug.always_scale == true) {</div><div class='add'>+		plane-&gt;composition.scaler_info.enabled = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (plane-&gt;composition.scaler_info.enabled == false) {</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.h_ratio = 1.0;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.v_ratio = 1.0;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.h_ratio = 1.0;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.v_ratio = 1.0;</div><div class='add'>+	} else {</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.h_ratio = (double)scaler_data-&gt;ratios.horz.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.v_ratio = (double)scaler_data-&gt;ratios.vert.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.h_ratio = (double)scaler_data-&gt;ratios.horz_c.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.v_ratio = (double)scaler_data-&gt;ratios.vert_c.value / (1ULL &lt;&lt; 32);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!scaler_data-&gt;taps.h_taps) {</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.h_taps = 1;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.h_taps = 1;</div><div class='add'>+	} else {</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.h_taps = scaler_data-&gt;taps.h_taps;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.h_taps = scaler_data-&gt;taps.h_taps_c;</div><div class='add'>+	}</div><div class='add'>+	if (!scaler_data-&gt;taps.v_taps) {</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.v_taps = 1;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.v_taps = 1;</div><div class='add'>+	} else {</div><div class='add'>+		plane-&gt;composition.scaler_info.plane0.v_taps = scaler_data-&gt;taps.v_taps;</div><div class='add'>+		plane-&gt;composition.scaler_info.plane1.v_taps = scaler_data-&gt;taps.v_taps_c;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.viewport.stationary = false;</div><div class='add'>+</div><div class='add'>+	if (plane_state-&gt;mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {</div><div class='add'>+		plane-&gt;tdlut.setup_for_tdlut = true;</div><div class='add'>+</div><div class='add'>+		switch (plane_state-&gt;mcm_luts.lut3d_data.gpu_mem_params.layout) {</div><div class='add'>+		case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB:</div><div class='add'>+		case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR:</div><div class='add'>+			plane-&gt;tdlut.tdlut_addressing_mode = dml2_tdlut_sw_linear;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR:</div><div class='add'>+			plane-&gt;tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (plane_state-&gt;mcm_luts.lut3d_data.gpu_mem_params.size) {</div><div class='add'>+		case DC_CM2_GPU_MEM_SIZE_171717:</div><div class='add'>+			plane-&gt;tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_SIZE_TRANSFORMED:</div><div class='add'>+		default:</div><div class='add'>+			//plane-&gt;tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	plane-&gt;tdlut.setup_for_tdlut |= dml_ctx-&gt;config.force_tdlut_enable;</div><div class='add'>+</div><div class='add'>+	plane-&gt;dynamic_meta_data.enable = false;</div><div class='add'>+	plane-&gt;dynamic_meta_data.lines_before_active_required = 0;</div><div class='add'>+	plane-&gt;dynamic_meta_data.transmitted_bytes = 0;</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.scaler_info.rect_out_width = plane_state-&gt;dst_rect.width;</div><div class='add'>+	plane-&gt;composition.rotation_angle = (enum dml2_rotation_angle) plane_state-&gt;rotation;</div><div class='add'>+	plane-&gt;stream_index = stream_index;</div><div class='add'>+</div><div class='add'>+	plane-&gt;overrides.gpuvm_min_page_size_kbytes = 256;</div><div class='add'>+</div><div class='add'>+	plane-&gt;immediate_flip = plane_state-&gt;flip_immediate;</div><div class='add'>+</div><div class='add'>+	plane-&gt;composition.rect_out_height_spans_vactive =</div><div class='add'>+		plane_state-&gt;dst_rect.height &gt;= stream-&gt;src.height &amp;&amp;</div><div class='add'>+		stream-&gt;dst.height &gt;= stream-&gt;timing.v_addressable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+//TODO : Could be possibly moved to a common helper layer.</div><div class='add'>+static bool dml21_wrapper_get_plane_id(const struct dc_state *context, unsigned int stream_id, const struct dc_plane_state *plane, unsigned int *plane_id)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (!plane_id)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		if (context-&gt;streams[i]-&gt;stream_id == stream_id) {</div><div class='add'>+			for (j = 0; j &lt; context-&gt;stream_status[i].plane_count; j++) {</div><div class='add'>+				if (context-&gt;stream_status[i].plane_states[j] == plane) {</div><div class='add'>+					*plane_id = (i &lt;&lt; 16) | j;</div><div class='add'>+					return true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int map_stream_to_dml21_display_cfg(const struct dml2_context *dml_ctx, const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	int location = -1;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+		if (dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] &amp;&amp; dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream-&gt;stream_id) {</div><div class='add'>+			location = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return location;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id,</div><div class='add'>+		const struct dc_plane_state *plane, const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_id;</div><div class='add'>+	int i = 0;</div><div class='add'>+	int location = -1;</div><div class='add'>+</div><div class='add'>+	if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &amp;plane_id)) {</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		return -1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+		if (dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] &amp;&amp; dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {</div><div class='add'>+			location = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return location;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_uclk_pstate_change_strategy dml21_force_pstate_method_to_uclk_state_change_strategy(enum dml2_force_pstate_methods force_pstate_method)</div><div class='add'>+{</div><div class='add'>+	enum dml2_uclk_pstate_change_strategy val = dml2_uclk_pstate_change_strategy_auto;</div><div class='add'>+</div><div class='add'>+	switch (force_pstate_method) {</div><div class='add'>+	case dml2_force_pstate_method_vactive:</div><div class='add'>+		val = dml2_uclk_pstate_change_strategy_force_vactive;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_force_pstate_method_vblank:</div><div class='add'>+		val = dml2_uclk_pstate_change_strategy_force_vblank;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_force_pstate_method_drr:</div><div class='add'>+		val = dml2_uclk_pstate_change_strategy_force_drr;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_force_pstate_method_subvp:</div><div class='add'>+		val = dml2_uclk_pstate_change_strategy_force_mall_svp;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_force_pstate_method_auto:</div><div class='add'>+	default:</div><div class='add'>+		val = dml2_uclk_pstate_change_strategy_auto;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	int stream_index, plane_index;</div><div class='add'>+	int disp_cfg_stream_location, disp_cfg_plane_location;</div><div class='add'>+	struct dml2_display_cfg *dml_dispcfg = &amp;dml_ctx-&gt;v21.display_config;</div><div class='add'>+	unsigned int plane_count = 0;</div><div class='add'>+</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));</div><div class='add'>+</div><div class='add'>+	dml_dispcfg-&gt;gpuvm_enable = dml_ctx-&gt;config.gpuvm_enable;</div><div class='add'>+	dml_dispcfg-&gt;gpuvm_max_page_table_levels = 4;</div><div class='add'>+	dml_dispcfg-&gt;hostvm_enable = false;</div><div class='add'>+	dml_dispcfg-&gt;minimize_det_reallocation = true;</div><div class='add'>+	dml_dispcfg-&gt;overrides.enable_subvp_implicit_pmo = true;</div><div class='add'>+</div><div class='add'>+	if (in_dc-&gt;debug.disable_unbounded_requesting) {</div><div class='add'>+		dml_dispcfg-&gt;overrides.hw.force_unbounded_requesting.enable = true;</div><div class='add'>+		dml_dispcfg-&gt;overrides.hw.force_unbounded_requesting.value = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (stream_index = 0; stream_index &lt; context-&gt;stream_count; stream_index++) {</div><div class='add'>+		disp_cfg_stream_location = map_stream_to_dml21_display_cfg(dml_ctx, context-&gt;streams[stream_index]);</div><div class='add'>+</div><div class='add'>+		if (disp_cfg_stream_location &lt; 0)</div><div class='add'>+			disp_cfg_stream_location = dml_dispcfg-&gt;num_streams++;</div><div class='add'>+</div><div class='add'>+		ASSERT(disp_cfg_stream_location &gt;= 0 &amp;&amp; disp_cfg_stream_location &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='add'>+		populate_dml21_timing_config_from_stream_state(&amp;dml_dispcfg-&gt;stream_descriptors[disp_cfg_stream_location].timing, context-&gt;streams[stream_index], &amp;context-&gt;res_ctx.pipe_ctx[stream_index], dml_ctx);</div><div class='add'>+		populate_dml21_output_config_from_stream_state(&amp;dml_dispcfg-&gt;stream_descriptors[disp_cfg_stream_location].output, context-&gt;streams[stream_index], &amp;context-&gt;res_ctx.pipe_ctx[stream_index]);</div><div class='add'>+		populate_dml21_stream_overrides_from_stream_state(&amp;dml_dispcfg-&gt;stream_descriptors[disp_cfg_stream_location], context-&gt;streams[stream_index], &amp;context-&gt;stream_status[stream_index]);</div><div class='add'>+</div><div class='add'>+		dml_dispcfg-&gt;stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.fclk_pstate = dml2_twait_budgeting_setting_if_needed;</div><div class='add'>+		dml_dispcfg-&gt;stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.uclk_pstate = dml2_twait_budgeting_setting_if_needed;</div><div class='add'>+		dml_dispcfg-&gt;stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.stutter_enter_exit = dml2_twait_budgeting_setting_if_needed;</div><div class='add'>+</div><div class='add'>+		dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context-&gt;streams[stream_index]-&gt;stream_id;</div><div class='add'>+		dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;</div><div class='add'>+</div><div class='add'>+		if (context-&gt;stream_status[stream_index].plane_count == 0) {</div><div class='add'>+			disp_cfg_plane_location = dml_dispcfg-&gt;num_planes++;</div><div class='add'>+			populate_dml21_dummy_surface_cfg(&amp;dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location].surface, context-&gt;streams[stream_index]);</div><div class='add'>+			populate_dml21_dummy_plane_cfg(&amp;dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location], context-&gt;streams[stream_index]);</div><div class='add'>+			dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location].stream_index = disp_cfg_stream_location;</div><div class='add'>+		} else {</div><div class='add'>+			for (plane_index = 0; plane_index &lt; context-&gt;stream_status[stream_index].plane_count; plane_index++) {</div><div class='add'>+				disp_cfg_plane_location = map_plane_to_dml21_display_cfg(dml_ctx, context-&gt;streams[stream_index]-&gt;stream_id, context-&gt;stream_status[stream_index].plane_states[plane_index], context);</div><div class='add'>+</div><div class='add'>+				if (disp_cfg_plane_location &lt; 0)</div><div class='add'>+					disp_cfg_plane_location = dml_dispcfg-&gt;num_planes++;</div><div class='add'>+</div><div class='add'>+				ASSERT(disp_cfg_plane_location &gt;= 0 &amp;&amp; disp_cfg_plane_location &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='add'>+</div><div class='add'>+				populate_dml21_surface_config_from_plane_state(in_dc, &amp;dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location].surface, context-&gt;stream_status[stream_index].plane_states[plane_index]);</div><div class='add'>+				populate_dml21_plane_config_from_plane_state(dml_ctx, &amp;dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location], context-&gt;stream_status[stream_index].plane_states[plane_index], context, stream_index);</div><div class='add'>+				dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location].stream_index = disp_cfg_stream_location;</div><div class='add'>+</div><div class='add'>+				if (dml21_wrapper_get_plane_id(context, context-&gt;streams[stream_index]-&gt;stream_id, context-&gt;stream_status[stream_index].plane_states[plane_index], &amp;dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))</div><div class='add'>+					dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;</div><div class='add'>+</div><div class='add'>+				/* apply forced pstate policy */</div><div class='add'>+				if (dml_ctx-&gt;config.pmo.force_pstate_method_enable) {</div><div class='add'>+					dml_dispcfg-&gt;plane_descriptors[disp_cfg_plane_location].overrides.uclk_pstate_change_strategy =</div><div class='add'>+							dml21_force_pstate_method_to_uclk_state_change_strategy(dml_ctx-&gt;config.pmo.force_pstate_method_values[stream_index]);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				plane_count++;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (plane_count == 0) {</div><div class='add'>+		dml_dispcfg-&gt;overrides.all_streams_blanked = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	/* TODO these should be the max of active, svp prefetch and idle should be tracked seperately */</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.dispclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.active.dcfclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.active.uclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.fclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.active.fclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.idle.uclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.idle.fclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.deepsleep_dcfclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx-&gt;v21.mode_programming.programming-&gt;fclk_pstate_supported;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx-&gt;v21.mode_programming.programming-&gt;uclk_pstate_supported;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.dtbrefclk_khz &gt; 0;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.dtbrefclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.socclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.socclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx-&gt;v21.mode_programming.programming-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx-&gt;v21.mode_programming.programming-&gt;stutter.base_percent_efficiency;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx-&gt;v21.mode_programming.programming-&gt;stutter.low_power_percent_efficiency;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index)</div><div class='add'>+{</div><div class='add'>+	struct dml2_dchub_watermark_regs *wm_regs = NULL;</div><div class='add'>+</div><div class='add'>+	switch (wm_index) {</div><div class='add'>+	case DML2_DCHUB_WATERMARK_SET_A:</div><div class='add'>+		wm_regs = &amp;watermarks-&gt;dcn4x.a;</div><div class='add'>+		break;</div><div class='add'>+	case DML2_DCHUB_WATERMARK_SET_B:</div><div class='add'>+		wm_regs = &amp;watermarks-&gt;dcn4x.b;</div><div class='add'>+		break;</div><div class='add'>+	case DML2_DCHUB_WATERMARK_SET_C:</div><div class='add'>+		wm_regs = &amp;watermarks-&gt;dcn4x.c;</div><div class='add'>+		break;</div><div class='add'>+	case DML2_DCHUB_WATERMARK_SET_D:</div><div class='add'>+		wm_regs = &amp;watermarks-&gt;dcn4x.d;</div><div class='add'>+		break;</div><div class='add'>+	case DML2_DCHUB_WATERMARK_SET_NUM:</div><div class='add'>+	default:</div><div class='add'>+		/* invalid wm set index */</div><div class='add'>+		wm_regs = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return wm_regs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_display_cfg_programming *programming = in_ctx-&gt;v21.mode_programming.programming;</div><div class='add'>+</div><div class='add'>+	unsigned int wm_index;</div><div class='add'>+</div><div class='add'>+	/* copy watermark sets from DML */</div><div class='add'>+	for (wm_index = 0; wm_index &lt; programming-&gt;global_regs.num_watermark_sets; wm_index++) {</div><div class='add'>+		struct dml2_dchub_watermark_regs *wm_regs = wm_set_index_to_dc_wm_set(watermarks, wm_index);</div><div class='add'>+</div><div class='add'>+		if (wm_regs)</div><div class='add'>+			memcpy(wm_regs,</div><div class='add'>+				&amp;programming-&gt;global_regs.wm_regs[wm_index],</div><div class='add'>+				sizeof(struct dml2_dchub_watermark_regs));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_map_hw_resources(struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+		dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] = dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];</div><div class='add'>+		dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = true;</div><div class='add'>+		dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] = dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];</div><div class='add'>+		dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_get_pipe_mcache_config(</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dml2_per_plane_programming *pln_prog,</div><div class='add'>+	struct dml2_pipe_configuration_descriptor *mcache_pipe_config)</div><div class='add'>+{</div><div class='add'>+	mcache_pipe_config-&gt;plane0.viewport_x_start = pipe_ctx-&gt;plane_res.scl_data.viewport.x;</div><div class='add'>+	mcache_pipe_config-&gt;plane0.viewport_width = pipe_ctx-&gt;plane_res.scl_data.viewport.width;</div><div class='add'>+</div><div class='add'>+	mcache_pipe_config-&gt;plane1.viewport_x_start = pipe_ctx-&gt;plane_res.scl_data.viewport_c.x;</div><div class='add'>+	mcache_pipe_config-&gt;plane1.viewport_width = pipe_ctx-&gt;plane_res.scl_data.viewport_c.width;</div><div class='add'>+</div><div class='add'>+	mcache_pipe_config-&gt;plane1_enabled =</div><div class='add'>+			dml21_is_plane1_enabled(pln_prog-&gt;plane_descriptor-&gt;pixel_format);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_set_dc_p_state_type(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dml2_per_stream_programming *stream_programming,</div><div class='add'>+		bool sub_vp_enabled)</div><div class='add'>+{</div><div class='add'>+	switch (stream_programming-&gt;uclk_pstate_method) {</div><div class='add'>+	case dml2_pstate_method_vactive:</div><div class='add'>+	case dml2_pstate_method_fw_vactive_drr:</div><div class='add'>+		pipe_ctx-&gt;p_state_type = P_STATE_V_ACTIVE;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_vblank:</div><div class='add'>+	case dml2_pstate_method_fw_vblank_drr:</div><div class='add'>+		if (sub_vp_enabled)</div><div class='add'>+			pipe_ctx-&gt;p_state_type = P_STATE_V_BLANK_SUB_VP;</div><div class='add'>+		else</div><div class='add'>+			pipe_ctx-&gt;p_state_type = P_STATE_V_BLANK;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_svp:</div><div class='add'>+	case dml2_pstate_method_fw_svp_drr:</div><div class='add'>+		pipe_ctx-&gt;p_state_type = P_STATE_SUB_VP;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_drr:</div><div class='add'>+		if (sub_vp_enabled)</div><div class='add'>+			pipe_ctx-&gt;p_state_type = P_STATE_DRR_SUB_VP;</div><div class='add'>+		else</div><div class='add'>+			pipe_ctx-&gt;p_state_type = P_STATE_FPO;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		pipe_ctx-&gt;p_state_type = P_STATE_UNKNOWN;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h<br/>new file mode 100644<br/>index 000000000000..9880d3e0398e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifndef _DML21_TRANSLATION_HELPER_H_</div><div class='add'>+#define _DML21_TRANSLATION_HELPER_H_</div><div class='add'>+</div><div class='add'>+struct dc;</div><div class='add'>+struct dc_state;</div><div class='add'>+struct dcn_watermarks;</div><div class='add'>+union dcn_watermark_set;</div><div class='add'>+struct pipe_ctx;</div><div class='add'>+struct dc_plane_state;</div><div class='add'>+</div><div class='add'>+struct dml2_context;</div><div class='add'>+struct dml2_configuration_options;</div><div class='add'>+struct dml2_initialize_instance_in_out;</div><div class='add'>+</div><div class='add'>+void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);</div><div class='add'>+bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);</div><div class='add'>+void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);</div><div class='add'>+void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);</div><div class='add'>+void dml21_map_hw_resources(struct dml2_context *dml_ctx);</div><div class='add'>+void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);</div><div class='add'>+void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);</div><div class='add'>+unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c<br/>new file mode 100644<br/>index 000000000000..ee721606b883<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c</a></div><div class='hunk'>@@ -0,0 +1,516 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml21_translation_helper.h"</div><div class='add'>+#include "dml2_internal_types.h"</div><div class='add'>+#include "dml21_utils.h"</div><div class='add'>+#include "dml2_dc_resource_mgmt.h"</div><div class='add'>+</div><div class='add'>+#include "dml2_core_dcn4_calcs.h"</div><div class='add'>+</div><div class='add'>+int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+		if (ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] &amp;&amp; ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id)</div><div class='add'>+			return  i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+		if (ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] &amp;&amp; ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id)</div><div class='add'>+			return  i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (!plane_id)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		for (j = 0; j &lt; state-&gt;stream_status[i].plane_count; j++) {</div><div class='add'>+			if (state-&gt;stream_status[i].plane_states[j] == plane) {</div><div class='add'>+				*plane_id = (i &lt;&lt; 16) | j;</div><div class='add'>+				return true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id)</div><div class='add'>+{</div><div class='add'>+	return 0xffff &amp; plane_id;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void find_valid_pipe_idx_for_stream_index(const struct dml2_context *dml_ctx, unsigned int *dml_pipe_idx, unsigned int stream_index)</div><div class='add'>+{</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+		if (dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[i].plane_descriptor-&gt;stream_index == stream_index) {</div><div class='add'>+			*dml_pipe_idx = i;</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void find_pipe_regs_idx(const struct dml2_context *dml_ctx,</div><div class='add'>+		struct pipe_ctx *pipe, unsigned int *pipe_regs_idx)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *opp_head = dml_ctx-&gt;config.callbacks.get_opp_head(pipe);</div><div class='add'>+</div><div class='add'>+	*pipe_regs_idx = dml_ctx-&gt;config.callbacks.get_odm_slice_index(opp_head);</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;plane_state)</div><div class='add'>+		*pipe_regs_idx += dml_ctx-&gt;config.callbacks.get_mpc_slice_index(pipe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* places pipe references into pipes arrays and returns number of pipes */</div><div class='add'>+int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dml2_context *dml_ctx,</div><div class='add'>+		struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],</div><div class='add'>+		struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],</div><div class='add'>+		int dml_plane_idx)</div><div class='add'>+{</div><div class='add'>+	unsigned int dml_stream_index;</div><div class='add'>+	unsigned int main_stream_id;</div><div class='add'>+	unsigned int dc_plane_index;</div><div class='add'>+	struct dc_stream_state *dc_main_stream;</div><div class='add'>+	struct dc_stream_status *dc_main_stream_status;</div><div class='add'>+	struct dc_plane_state *dc_main_plane;</div><div class='add'>+	struct dc_stream_state *dc_phantom_stream;</div><div class='add'>+	struct dc_stream_status *dc_phantom_stream_status;</div><div class='add'>+	struct dc_plane_state *dc_phantom_plane;</div><div class='add'>+	int num_pipes = 0;</div><div class='add'>+</div><div class='add'>+	memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='add'>+	memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='add'>+</div><div class='add'>+	dml_stream_index = dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_plane_idx].plane_descriptor-&gt;stream_index;</div><div class='add'>+	main_stream_id = dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index];</div><div class='add'>+</div><div class='add'>+	dc_main_stream = dml_ctx-&gt;config.callbacks.get_stream_from_id(context, main_stream_id);</div><div class='add'>+	dc_main_stream_status = dml_ctx-&gt;config.callbacks.get_stream_status(context, dc_main_stream);</div><div class='add'>+	if (!dc_main_stream_status)</div><div class='add'>+		return num_pipes;</div><div class='add'>+</div><div class='add'>+	/* find main plane based on id */</div><div class='add'>+	dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_idx]);</div><div class='add'>+	dc_main_plane = dc_main_stream_status-&gt;plane_states[dc_plane_index];</div><div class='add'>+</div><div class='add'>+	if (dc_main_plane) {</div><div class='add'>+		num_pipes = dml_ctx-&gt;config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &amp;context-&gt;res_ctx, dc_main_pipes);</div><div class='add'>+	} else {</div><div class='add'>+		/* stream was configured with dummy plane, so get pipes from opp head */</div><div class='add'>+		struct pipe_ctx *otg_master_pipe = dml_ctx-&gt;config.callbacks.get_otg_master_for_stream(&amp;context-&gt;res_ctx, dc_main_stream);</div><div class='add'>+		if (otg_master_pipe != NULL)</div><div class='add'>+			num_pipes = dml_ctx-&gt;config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &amp;context-&gt;res_ctx, dc_main_pipes);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* if phantom exists, find associated pipes */</div><div class='add'>+	dc_phantom_stream = dml_ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(context, dc_main_stream);</div><div class='add'>+	if (dc_phantom_stream &amp;&amp; num_pipes &gt; 0) {</div><div class='add'>+		dc_phantom_stream_status = dml_ctx-&gt;config.callbacks.get_stream_status(context, dc_phantom_stream);</div><div class='add'>+</div><div class='add'>+		if (dc_phantom_stream_status) {</div><div class='add'>+			/* phantom plane will have same index as main */</div><div class='add'>+			dc_phantom_plane = dc_phantom_stream_status-&gt;plane_states[dc_plane_index];</div><div class='add'>+</div><div class='add'>+			if (dc_phantom_plane) {</div><div class='add'>+				/* only care about phantom pipes if they contain the phantom plane */</div><div class='add'>+				dml_ctx-&gt;config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &amp;context-&gt;res_ctx, dc_phantom_pipes);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return num_pipes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_pipe_populate_global_sync(struct dml2_context *dml_ctx,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dml2_per_stream_programming *stream_programming)</div><div class='add'>+{</div><div class='add'>+	union dml2_global_sync_programming *global_sync = &amp;stream_programming-&gt;global_sync;</div><div class='add'>+</div><div class='add'>+	if (dml_ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {</div><div class='add'>+		/* phantom has its own global sync */</div><div class='add'>+		global_sync = &amp;stream_programming-&gt;phantom_stream.global_sync;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;pipe_ctx-&gt;global_sync,</div><div class='add'>+		global_sync,</div><div class='add'>+		sizeof(union dml2_global_sync_programming));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_populate_mall_allocation_size(struct dc_state *context,</div><div class='add'>+		struct dml2_context *in_ctx,</div><div class='add'>+		struct dml2_per_plane_programming *pln_prog,</div><div class='add'>+		struct pipe_ctx *dc_pipe)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	/* Reuse MALL Allocation Sizes logic from dcn32_fpu.c */</div><div class='add'>+	/* Count from active, top pipes per plane only. Only add mall_ss_size_bytes for each unique plane. */</div><div class='add'>+	if (dc_pipe-&gt;stream &amp;&amp; dc_pipe-&gt;plane_state &amp;&amp;</div><div class='add'>+			(dc_pipe-&gt;top_pipe == NULL ||</div><div class='add'>+			dc_pipe-&gt;plane_state != dc_pipe-&gt;top_pipe-&gt;plane_state) &amp;&amp;</div><div class='add'>+			dc_pipe-&gt;prev_odm_pipe == NULL) {</div><div class='add'>+		/* SS: all active surfaces stored in MALL */</div><div class='add'>+		if (in_ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, dc_pipe) != SUBVP_PHANTOM) {</div><div class='add'>+			dc_pipe-&gt;surface_size_in_mall_bytes = pln_prog-&gt;surface_size_mall_bytes;</div><div class='add'>+			context-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe-&gt;surface_size_in_mall_bytes;</div><div class='add'>+		} else {</div><div class='add'>+			/* SUBVP: phantom surfaces only stored in MALL */</div><div class='add'>+			dc_pipe-&gt;surface_size_in_mall_bytes = pln_prog-&gt;svp_size_mall_bytes;</div><div class='add'>+			context-&gt;bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe-&gt;surface_size_in_mall_bytes;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	/* If this assert is hit then we have a link encoder dynamic management issue */</div><div class='add'>+	ASSERT(pipe_ctx-&gt;stream_res.hpo_dp_stream_enc ? pipe_ctx-&gt;link_res.hpo_dp_link_enc != NULL : true);</div><div class='add'>+	return (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='add'>+		pipe_ctx-&gt;link_res.hpo_dp_link_enc &amp;&amp;</div><div class='add'>+		dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; dc_state_get_paired_subvp_stream(context, pipe_ctx-&gt;stream) &amp;&amp;</div><div class='add'>+							dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog,</div><div class='add'>+		struct dml2_per_stream_programming *stream_prog)</div><div class='add'>+{</div><div class='add'>+	unsigned int pipe_reg_index = 0;</div><div class='add'>+</div><div class='add'>+	dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog);</div><div class='add'>+	find_pipe_regs_idx(dml_ctx, pipe_ctx, &amp;pipe_reg_index);</div><div class='add'>+</div><div class='add'>+	if (dml_ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {</div><div class='add'>+		memcpy(&amp;pipe_ctx-&gt;hubp_regs, pln_prog-&gt;phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));</div><div class='add'>+		pipe_ctx-&gt;unbounded_req = false;</div><div class='add'>+		pipe_ctx-&gt;det_buffer_size_kb = 0;</div><div class='add'>+	} else {</div><div class='add'>+		memcpy(&amp;pipe_ctx-&gt;hubp_regs, pln_prog-&gt;pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));</div><div class='add'>+		pipe_ctx-&gt;unbounded_req = pln_prog-&gt;pipe_regs[pipe_reg_index]-&gt;rq_regs.unbounded_request_enabled;</div><div class='add'>+		pipe_ctx-&gt;det_buffer_size_kb = pln_prog-&gt;pipe_regs[pipe_reg_index]-&gt;det_size * 64;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;plane_res.bw.dppclk_khz = pln_prog-&gt;min_clocks.dcn4x.dppclk_khz;</div><div class='add'>+	if (context-&gt;bw_ctx.bw.dcn.clk.dppclk_khz &lt; pipe_ctx-&gt;plane_res.bw.dppclk_khz)</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx-&gt;plane_res.bw.dppclk_khz;</div><div class='add'>+</div><div class='add'>+	dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx);</div><div class='add'>+</div><div class='add'>+	bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx-&gt;stream-&gt;ctx-&gt;dc, context);</div><div class='add'>+</div><div class='add'>+	dml21_set_dc_p_state_type(pipe_ctx, stream_prog, sub_vp_enabled);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml_ctx,</div><div class='add'>+	const struct dc *dc,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct dc_stream_state *main_stream,</div><div class='add'>+	struct dml2_per_stream_programming *stream_programming)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='add'>+	struct dml2_stream_parameters *phantom_stream_descriptor = &amp;stream_programming-&gt;phantom_stream.descriptor;</div><div class='add'>+</div><div class='add'>+	phantom_stream = dml_ctx-&gt;config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream);</div><div class='add'>+	if (!phantom_stream)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	/* copy details of phantom stream from main */</div><div class='add'>+	memcpy(&amp;phantom_stream-&gt;timing, &amp;main_stream-&gt;timing, sizeof(phantom_stream-&gt;timing));</div><div class='add'>+	memcpy(&amp;phantom_stream-&gt;src, &amp;main_stream-&gt;src, sizeof(phantom_stream-&gt;src));</div><div class='add'>+	memcpy(&amp;phantom_stream-&gt;dst, &amp;main_stream-&gt;dst, sizeof(phantom_stream-&gt;dst));</div><div class='add'>+</div><div class='add'>+	/* modify timing for phantom */</div><div class='add'>+	phantom_stream-&gt;timing.v_front_porch = phantom_stream_descriptor-&gt;timing.v_front_porch;</div><div class='add'>+	phantom_stream-&gt;timing.v_addressable = phantom_stream_descriptor-&gt;timing.v_active;</div><div class='add'>+	phantom_stream-&gt;timing.v_total = phantom_stream_descriptor-&gt;timing.v_total;</div><div class='add'>+	phantom_stream-&gt;timing.flags.DSC = 0; // phantom always has DSC disabled</div><div class='add'>+</div><div class='add'>+	phantom_stream-&gt;dst.y = 0;</div><div class='add'>+	phantom_stream-&gt;dst.height = stream_programming-&gt;phantom_stream.descriptor.timing.v_active;</div><div class='add'>+</div><div class='add'>+	phantom_stream-&gt;src.y = 0;</div><div class='add'>+	phantom_stream-&gt;src.height = (double)phantom_stream_descriptor-&gt;timing.v_active * (double)main_stream-&gt;src.height / (double)main_stream-&gt;dst.height;</div><div class='add'>+</div><div class='add'>+	phantom_stream-&gt;use_dynamic_meta = false;</div><div class='add'>+</div><div class='add'>+	dml_ctx-&gt;config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream);</div><div class='add'>+</div><div class='add'>+	return phantom_stream;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dc_plane_state *dml21_add_phantom_plane(struct dml2_context *dml_ctx,</div><div class='add'>+	const struct dc *dc,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct dc_stream_state *phantom_stream,</div><div class='add'>+	struct dc_plane_state *main_plane,</div><div class='add'>+	struct dml2_per_plane_programming *plane_programming)</div><div class='add'>+{</div><div class='add'>+	struct dc_plane_state *phantom_plane;</div><div class='add'>+</div><div class='add'>+	phantom_plane = dml_ctx-&gt;config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane);</div><div class='add'>+	if (!phantom_plane)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	phantom_plane-&gt;format = main_plane-&gt;format;</div><div class='add'>+	phantom_plane-&gt;rotation = main_plane-&gt;rotation;</div><div class='add'>+	phantom_plane-&gt;visible = main_plane-&gt;visible;</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;address, &amp;main_plane-&gt;address, sizeof(phantom_plane-&gt;address));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;scaling_quality, &amp;main_plane-&gt;scaling_quality,</div><div class='add'>+		sizeof(phantom_plane-&gt;scaling_quality));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;src_rect, &amp;main_plane-&gt;src_rect, sizeof(phantom_plane-&gt;src_rect));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;dst_rect, &amp;main_plane-&gt;dst_rect, sizeof(phantom_plane-&gt;dst_rect));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;clip_rect, &amp;main_plane-&gt;clip_rect, sizeof(phantom_plane-&gt;clip_rect));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;plane_size, &amp;main_plane-&gt;plane_size,</div><div class='add'>+		sizeof(phantom_plane-&gt;plane_size));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;tiling_info, &amp;main_plane-&gt;tiling_info,</div><div class='add'>+		sizeof(phantom_plane-&gt;tiling_info));</div><div class='add'>+	memcpy(&amp;phantom_plane-&gt;dcc, &amp;main_plane-&gt;dcc, sizeof(phantom_plane-&gt;dcc));</div><div class='add'>+</div><div class='add'>+	phantom_plane-&gt;format = main_plane-&gt;format;</div><div class='add'>+	phantom_plane-&gt;rotation = main_plane-&gt;rotation;</div><div class='add'>+	phantom_plane-&gt;visible = main_plane-&gt;visible;</div><div class='add'>+</div><div class='add'>+	/* Shadow pipe has small viewport. */</div><div class='add'>+	phantom_plane-&gt;clip_rect.y = 0;</div><div class='add'>+	phantom_plane-&gt;clip_rect.height = phantom_stream-&gt;src.height;</div><div class='add'>+</div><div class='add'>+	dml_ctx-&gt;config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context);</div><div class='add'>+</div><div class='add'>+	return phantom_plane;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	unsigned int dml_stream_index, dml_plane_index, dc_plane_index;</div><div class='add'>+	struct dc_stream_state *main_stream;</div><div class='add'>+	struct dc_stream_status *main_stream_status;</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='add'>+	struct dc_plane_state *main_plane;</div><div class='add'>+	bool phantoms_added = false;</div><div class='add'>+</div><div class='add'>+	/* create phantom streams and planes and add to context */</div><div class='add'>+	for (dml_stream_index = 0; dml_stream_index &lt; dml_ctx-&gt;v21.mode_programming.programming-&gt;display_config.num_streams; dml_stream_index++) {</div><div class='add'>+		/* iterate through DML streams looking for phantoms */</div><div class='add'>+		if (dml_ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[dml_stream_index].phantom_stream.enabled) {</div><div class='add'>+			/* find associated dc stream */</div><div class='add'>+			main_stream = dml_ctx-&gt;config.callbacks.get_stream_from_id(context,</div><div class='add'>+					dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]);</div><div class='add'>+</div><div class='add'>+			main_stream_status = dml_ctx-&gt;config.callbacks.get_stream_status(context, main_stream);</div><div class='add'>+</div><div class='add'>+			if (!main_stream_status || main_stream_status-&gt;plane_count == 0)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			/* create phantom stream for subvp enabled stream */</div><div class='add'>+			phantom_stream = dml21_add_phantom_stream(dml_ctx,</div><div class='add'>+					dc,</div><div class='add'>+					context,</div><div class='add'>+					main_stream,</div><div class='add'>+					&amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[dml_stream_index]);</div><div class='add'>+</div><div class='add'>+			if (!phantom_stream)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			/* iterate through DML planes associated with this stream */</div><div class='add'>+			for (dml_plane_index = 0; dml_plane_index &lt; dml_ctx-&gt;v21.mode_programming.programming-&gt;display_config.num_planes; dml_plane_index++) {</div><div class='add'>+				if (dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_plane_index].plane_descriptor-&gt;stream_index == dml_stream_index) {</div><div class='add'>+					/* find associated dc plane */</div><div class='add'>+					dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx-&gt;v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_index]);</div><div class='add'>+					main_plane = main_stream_status-&gt;plane_states[dc_plane_index];</div><div class='add'>+</div><div class='add'>+					/* create phantom planes for subvp enabled plane */</div><div class='add'>+					dml21_add_phantom_plane(dml_ctx,</div><div class='add'>+							dc,</div><div class='add'>+							context,</div><div class='add'>+							phantom_stream,</div><div class='add'>+							main_plane,</div><div class='add'>+							&amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_plane_index]);</div><div class='add'>+</div><div class='add'>+					phantoms_added = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (phantoms_added)</div><div class='add'>+		dml2_map_dc_pipes(dml_ctx, context, NULL, &amp;dml_ctx-&gt;v21.dml_to_dc_pipe_mapping, dc-&gt;current_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_build_fams2_programming(const struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	int i, j, k;</div><div class='add'>+	unsigned int num_fams2_streams = 0;</div><div class='add'>+</div><div class='add'>+	/* reset fams2 data */</div><div class='add'>+	memset(&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);</div><div class='add'>+	memset(&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);</div><div class='add'>+	memset(&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES);</div><div class='add'>+	memset(&amp;context-&gt;bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config));</div><div class='add'>+</div><div class='add'>+	if (dml_ctx-&gt;v21.mode_programming.programming-&gt;fams2_required) {</div><div class='add'>+		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+			int dml_stream_idx;</div><div class='add'>+			struct dc_stream_state *phantom_stream;</div><div class='add'>+			struct dc_stream_status *phantom_status;</div><div class='add'>+			enum fams2_stream_type type = 0;</div><div class='add'>+</div><div class='add'>+			union dmub_cmd_fams2_config *static_base_state = &amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams];</div><div class='add'>+			union dmub_cmd_fams2_config *static_sub_state = &amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams];</div><div class='add'>+</div><div class='add'>+			struct dc_stream_state *stream = context-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+			if (context-&gt;stream_status[i].plane_count == 0 ||</div><div class='add'>+					dml_ctx-&gt;config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) {</div><div class='add'>+				/* can ignore blanked or phantom streams */</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream-&gt;stream_id);</div><div class='add'>+			if (dml_stream_idx &lt; 0) {</div><div class='add'>+				ASSERT(dml_stream_idx &gt;= 0);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* copy static state from PMO */</div><div class='add'>+			memcpy(static_base_state,</div><div class='add'>+					&amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[dml_stream_idx].fams2_base_params,</div><div class='add'>+					sizeof(union dmub_cmd_fams2_config));</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;debug.fams_version.major == 3) {</div><div class='add'>+				memcpy(&amp;context-&gt;bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams],</div><div class='add'>+						&amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[dml_stream_idx].fams2_sub_params_v2,</div><div class='add'>+						sizeof(union dmub_fams2_stream_static_sub_state_v2));</div><div class='add'>+			} else {</div><div class='add'>+				memcpy(static_sub_state,</div><div class='add'>+						&amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[dml_stream_idx].fams2_sub_params,</div><div class='add'>+						sizeof(union dmub_cmd_fams2_config));</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			switch (dc-&gt;debug.fams_version.minor) {</div><div class='add'>+			case 1:</div><div class='add'>+			default:</div><div class='add'>+				type = static_base_state-&gt;stream_v1.base.type;</div><div class='add'>+</div><div class='add'>+				/* get information from context */</div><div class='add'>+				static_base_state-&gt;stream_v1.base.num_planes = context-&gt;stream_status[i].plane_count;</div><div class='add'>+				static_base_state-&gt;stream_v1.base.otg_inst = context-&gt;stream_status[i].primary_otg_inst;</div><div class='add'>+</div><div class='add'>+				/* populate pipe masks for planes */</div><div class='add'>+				for (j = 0; j &lt; context-&gt;stream_status[i].plane_count; j++) {</div><div class='add'>+					for (k = 0; k &lt; dc-&gt;res_pool-&gt;pipe_count; k++) {</div><div class='add'>+						if (context-&gt;res_ctx.pipe_ctx[k].stream &amp;&amp;</div><div class='add'>+								context-&gt;res_ctx.pipe_ctx[k].stream-&gt;stream_id == stream-&gt;stream_id &amp;&amp;</div><div class='add'>+								context-&gt;res_ctx.pipe_ctx[k].plane_state == context-&gt;stream_status[i].plane_states[j]) {</div><div class='add'>+							static_base_state-&gt;stream_v1.base.pipe_mask |= (1 &lt;&lt; k);</div><div class='add'>+							static_base_state-&gt;stream_v1.base.plane_pipe_masks[j] |= (1 &lt;&lt; k);</div><div class='add'>+						}</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+			/* get per method programming */</div><div class='add'>+			switch (type) {</div><div class='add'>+			case FAMS2_STREAM_TYPE_VBLANK:</div><div class='add'>+			case FAMS2_STREAM_TYPE_VACTIVE:</div><div class='add'>+			case FAMS2_STREAM_TYPE_DRR:</div><div class='add'>+				break;</div><div class='add'>+			case FAMS2_STREAM_TYPE_SUBVP:</div><div class='add'>+				phantom_stream = dml_ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream);</div><div class='add'>+				if (!phantom_stream)</div><div class='add'>+					break;</div><div class='add'>+</div><div class='add'>+				phantom_status = dml_ctx-&gt;config.callbacks.get_stream_status(context, phantom_stream);</div><div class='add'>+</div><div class='add'>+				/* phantom status should always be present */</div><div class='add'>+				ASSERT(phantom_status);</div><div class='add'>+				if (!phantom_status)</div><div class='add'>+					break;</div><div class='add'>+</div><div class='add'>+				switch (dc-&gt;debug.fams_version.minor) {</div><div class='add'>+				case 1:</div><div class='add'>+				default:</div><div class='add'>+					static_sub_state-&gt;stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status-&gt;primary_otg_inst;</div><div class='add'>+</div><div class='add'>+					/* populate pipe masks for phantom planes */</div><div class='add'>+					for (j = 0; j &lt; phantom_status-&gt;plane_count; j++) {</div><div class='add'>+						for (k = 0; k &lt; dc-&gt;res_pool-&gt;pipe_count; k++) {</div><div class='add'>+							if (context-&gt;res_ctx.pipe_ctx[k].stream &amp;&amp;</div><div class='add'>+									context-&gt;res_ctx.pipe_ctx[k].stream-&gt;stream_id == phantom_stream-&gt;stream_id &amp;&amp;</div><div class='add'>+									context-&gt;res_ctx.pipe_ctx[k].plane_state == phantom_status-&gt;plane_states[j]) {</div><div class='add'>+								switch (dc-&gt;debug.fams_version.minor) {</div><div class='add'>+								case 1:</div><div class='add'>+								default:</div><div class='add'>+									static_sub_state-&gt;stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 &lt;&lt; k);</div><div class='add'>+									static_sub_state-&gt;stream_v1.sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 &lt;&lt; k);</div><div class='add'>+								}</div><div class='add'>+							}</div><div class='add'>+						}</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				ASSERT(false);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			num_fams2_streams++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (num_fams2_streams &gt; 0) {</div><div class='add'>+		/* copy FAMS2 configuration */</div><div class='add'>+		memcpy(&amp;context-&gt;bw_ctx.bw.dcn.fams2_global_config,</div><div class='add'>+				&amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;fams2_global_config,</div><div class='add'>+				sizeof(struct dmub_cmd_fams2_global_config));</div><div class='add'>+</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	return source_format &gt;= dml2_420_8 &amp;&amp; source_format &lt;= dml2_rgbe_alpha;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h<br/>new file mode 100644<br/>index 000000000000..4bff52eaaef8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifndef _DML21_UTILS_H_</div><div class='add'>+#define _DML21_UTILS_H_</div><div class='add'>+</div><div class='add'>+struct dc_state;</div><div class='add'>+struct dc_plane_state;</div><div class='add'>+struct pipe_ctx;</div><div class='add'>+</div><div class='add'>+struct dml2_context;</div><div class='add'>+struct dml2_display_rq_regs;</div><div class='add'>+struct dml2_display_dlg_regs;</div><div class='add'>+struct dml2_display_ttu_regs;</div><div class='add'>+</div><div class='add'>+int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id);</div><div class='add'>+int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id);</div><div class='add'>+bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id);</div><div class='add'>+void dml21_pipe_populate_global_sync(struct dml2_context *dml_ctx,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dml2_per_stream_programming *stream_programming);</div><div class='add'>+void dml21_populate_mall_allocation_size(struct dc_state *context,</div><div class='add'>+		struct dml2_context *in_ctx,</div><div class='add'>+		struct dml2_per_plane_programming *pln_prog,</div><div class='add'>+		struct pipe_ctx *dc_pipe);</div><div class='add'>+bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx);</div><div class='add'>+void find_valid_pipe_idx_for_stream_index(const struct dml2_context *dml_ctx, unsigned int *dml_pipe_idx, unsigned int stream_index);</div><div class='add'>+void find_pipe_regs_idx(const struct dml2_context *dml_ctx,</div><div class='add'>+		struct pipe_ctx *pipe, unsigned int *pipe_regs_idx);</div><div class='add'>+int dml21_find_dc_pipes_for_plane(const struct dc *in_dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dml2_context *dml_ctx,</div><div class='add'>+		struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],</div><div class='add'>+		struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],</div><div class='add'>+		int dml_plane_idx);</div><div class='add'>+void dml21_program_dc_pipe(struct dml2_context *dml_ctx,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dml2_per_plane_programming *pln_prog,</div><div class='add'>+		struct dml2_per_stream_programming *stream_prog);</div><div class='add'>+void dml21_handle_phantom_streams_planes(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);</div><div class='add'>+unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id);</div><div class='add'>+void dml21_build_fams2_programming(const struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dml2_context *dml_ctx);</div><div class='add'>+bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c<br/>new file mode 100644<br/>index 000000000000..798abb2b2e67<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c</a></div><div class='hunk'>@@ -0,0 +1,466 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_types.h"</div><div class='add'>+#include "dml_top.h"</div><div class='add'>+#include "dml2_core_dcn4_calcs.h"</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml21_utils.h"</div><div class='add'>+#include "dml21_translation_helper.h"</div><div class='add'>+#include "dml2_dc_resource_mgmt.h"</div><div class='add'>+</div><div class='add'>+#define INVALID -1</div><div class='add'>+</div><div class='add'>+static bool dml21_allocate_memory(struct dml2_context **dml_ctx)</div><div class='add'>+{</div><div class='add'>+	*dml_ctx = vzalloc(sizeof(struct dml2_context));</div><div class='add'>+	if (!(*dml_ctx))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	(*dml_ctx)-&gt;v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance));</div><div class='add'>+	if (!((*dml_ctx)-&gt;v21.dml_init.dml2_instance))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	(*dml_ctx)-&gt;v21.mode_support.dml2_instance = (*dml_ctx)-&gt;v21.dml_init.dml2_instance;</div><div class='add'>+	(*dml_ctx)-&gt;v21.mode_programming.dml2_instance = (*dml_ctx)-&gt;v21.dml_init.dml2_instance;</div><div class='add'>+</div><div class='add'>+	(*dml_ctx)-&gt;v21.mode_support.display_config = &amp;(*dml_ctx)-&gt;v21.display_config;</div><div class='add'>+	(*dml_ctx)-&gt;v21.mode_programming.display_config = (*dml_ctx)-&gt;v21.mode_support.display_config;</div><div class='add'>+</div><div class='add'>+	(*dml_ctx)-&gt;v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming));</div><div class='add'>+	if (!((*dml_ctx)-&gt;v21.mode_programming.programming))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml21_populate_configuration_options(const struct dc *in_dc,</div><div class='add'>+		struct dml2_context *dml_ctx,</div><div class='add'>+		const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	dml_ctx-&gt;config = *config;</div><div class='add'>+</div><div class='add'>+	/* UCLK P-State options */</div><div class='add'>+	if (in_dc-&gt;debug.dml21_force_pstate_method) {</div><div class='add'>+		dml_ctx-&gt;config.pmo.force_pstate_method_enable = true;</div><div class='add'>+		for (int i = 0; i &lt; MAX_PIPES; i++)</div><div class='add'>+			dml_ctx-&gt;config.pmo.force_pstate_method_values[i] = in_dc-&gt;debug.dml21_force_pstate_method_values[i];</div><div class='add'>+	} else {</div><div class='add'>+		dml_ctx-&gt;config.pmo.force_pstate_method_enable = false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	dml_ctx-&gt;architecture = dml2_architecture_21;</div><div class='add'>+</div><div class='add'>+	dml21_populate_configuration_options(in_dc, dml_ctx, config);</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+</div><div class='add'>+	dml21_populate_dml_init_params(&amp;dml_ctx-&gt;v21.dml_init, &amp;dml_ctx-&gt;config, in_dc);</div><div class='add'>+</div><div class='add'>+	dml2_initialize_instance(&amp;dml_ctx-&gt;v21.dml_init);</div><div class='add'>+</div><div class='add'>+	DC_FP_END();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	/* Allocate memory for initializing DML21 instance */</div><div class='add'>+	if (!dml21_allocate_memory(dml_ctx))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dml21_init(in_dc, *dml_ctx, config);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_destroy(struct dml2_context *dml2)</div><div class='add'>+{</div><div class='add'>+	vfree(dml2-&gt;v21.dml_init.dml2_instance);</div><div class='add'>+	vfree(dml2-&gt;v21.mode_programming.programming);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,</div><div class='add'>+	struct dml2_context *in_ctx, unsigned int pipe_cnt)</div><div class='add'>+{</div><div class='add'>+	unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0;</div><div class='add'>+	struct dml2_per_plane_programming *pln_prog = NULL;</div><div class='add'>+	struct dml2_per_stream_programming *stream_prog = NULL;</div><div class='add'>+	struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];</div><div class='add'>+	struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};</div><div class='add'>+	int num_pipes;</div><div class='add'>+	unsigned int dml_phantom_prog_idx;</div><div class='add'>+</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.dppclk_khz = 0;</div><div class='add'>+</div><div class='add'>+	/* copy global DCHUBBUB arbiter registers */</div><div class='add'>+	memcpy(&amp;context-&gt;bw_ctx.bw.dcn.arb_regs, &amp;in_ctx-&gt;v21.mode_programming.programming-&gt;global_regs.arb_regs, sizeof(struct dml2_display_arb_regs));</div><div class='add'>+</div><div class='add'>+	/* legacy only */</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx-&gt;v21.mode_programming.programming-&gt;global_regs.arb_regs.compbuf_size * 64;</div><div class='add'>+</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes = 0;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;</div><div class='add'>+</div><div class='add'>+	/* phantom's start after main planes */</div><div class='add'>+	dml_phantom_prog_idx = in_ctx-&gt;v21.mode_programming.programming-&gt;display_config.num_planes;</div><div class='add'>+</div><div class='add'>+	for (dml_prog_idx = 0; dml_prog_idx &lt; DML2_MAX_PLANES; dml_prog_idx++) {</div><div class='add'>+		pln_prog = &amp;in_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_prog_idx];</div><div class='add'>+</div><div class='add'>+		if (!pln_prog-&gt;plane_descriptor)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		stream_prog = &amp;in_ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[pln_prog-&gt;plane_descriptor-&gt;stream_index];</div><div class='add'>+		num_dpps_required = pln_prog-&gt;num_dpps_required;</div><div class='add'>+</div><div class='add'>+		if (num_dpps_required == 0) {</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+		num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);</div><div class='add'>+</div><div class='add'>+		if (num_pipes &lt;= 0)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* program each pipe */</div><div class='add'>+		for (dc_pipe_index = 0; dc_pipe_index &lt; num_pipes; dc_pipe_index++) {</div><div class='add'>+			dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog);</div><div class='add'>+</div><div class='add'>+			if (pln_prog-&gt;phantom_plane.valid &amp;&amp; dc_phantom_pipes[dc_pipe_index]) {</div><div class='add'>+				dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* copy per plane mcache allocation */</div><div class='add'>+		memcpy(&amp;context-&gt;bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &amp;pln_prog-&gt;mcache_allocation, sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+		if (pln_prog-&gt;phantom_plane.valid) {</div><div class='add'>+			memcpy(&amp;context-&gt;bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx],</div><div class='add'>+					&amp;pln_prog-&gt;phantom_plane.mcache_allocation,</div><div class='add'>+					sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+</div><div class='add'>+			dml_phantom_prog_idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* assign global clocks */</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.bw_dppclk_khz = context-&gt;bw_ctx.bw.dcn.clk.dppclk_khz;</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.bw_dispclk_khz = context-&gt;bw_ctx.bw.dcn.clk.dispclk_khz;</div><div class='add'>+	if (in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values &gt; 1) {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =</div><div class='add'>+			in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000;</div><div class='add'>+	} else {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values &gt; 1) {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =</div><div class='add'>+			in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000;</div><div class='add'>+	} else {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx-&gt;v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* get global mall allocation */</div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes) {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.num_ways = dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes(dc, context-&gt;bw_ctx.bw.dcn.mall_subvp_size_bytes);</div><div class='add'>+	} else {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.num_ways = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params)</div><div class='add'>+{</div><div class='add'>+	int dc_plane_idx = 0;</div><div class='add'>+	int dml_prog_idx, stream_idx, plane_idx;</div><div class='add'>+	struct dml2_per_plane_programming *pln_prog = NULL;</div><div class='add'>+</div><div class='add'>+	for (stream_idx = 0; stream_idx &lt; context-&gt;stream_count; stream_idx++) {</div><div class='add'>+		for (plane_idx = 0; plane_idx &lt; context-&gt;stream_status[stream_idx].plane_count; plane_idx++) {</div><div class='add'>+			dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context-&gt;streams[stream_idx]-&gt;stream_id, context-&gt;stream_status[stream_idx].plane_states[plane_idx], context);</div><div class='add'>+			if (dml_prog_idx == INVALID) {</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+			pln_prog = &amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_prog_idx];</div><div class='add'>+			mcache_params[dc_plane_idx].valid = pln_prog-&gt;mcache_allocation.valid;</div><div class='add'>+			mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog-&gt;mcache_allocation.num_mcaches_plane0;</div><div class='add'>+			mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog-&gt;mcache_allocation.num_mcaches_plane1;</div><div class='add'>+			mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog-&gt;mcache_allocation.requires_dedicated_mall_mcache;</div><div class='add'>+			mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog-&gt;mcache_allocation.last_slice_sharing.plane0_plane1;</div><div class='add'>+			memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0,</div><div class='add'>+				pln_prog-&gt;mcache_allocation.mcache_x_offsets_plane0,</div><div class='add'>+				sizeof(int) * (DML2_MAX_MCACHES + 1));</div><div class='add'>+			memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1,</div><div class='add'>+				pln_prog-&gt;mcache_allocation.mcache_x_offsets_plane1,</div><div class='add'>+				sizeof(int) * (DML2_MAX_MCACHES + 1));</div><div class='add'>+			dc_plane_idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+	struct dml2_build_mode_programming_in_out *mode_programming = &amp;dml_ctx-&gt;v21.mode_programming;</div><div class='add'>+	struct dc_mcache_params mcache_params[MAX_PLANES] = {0};</div><div class='add'>+</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.display_config, 0, sizeof(struct dml2_display_cfg));</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.mode_programming.dml2_instance-&gt;scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out));</div><div class='add'>+</div><div class='add'>+	if (!context)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (context-&gt;stream_count == 0) {</div><div class='add'>+		dml21_build_fams2_programming(in_dc, context, dml_ctx);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* scrub phantom's from current dc_state */</div><div class='add'>+	dml_ctx-&gt;config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);</div><div class='add'>+	dml_ctx-&gt;config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);</div><div class='add'>+</div><div class='add'>+	/* Populate stream, plane mappings and other fields in display config. */</div><div class='add'>+	result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);</div><div class='add'>+	if (!result)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	result = dml2_build_mode_programming(mode_programming);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+	if (!result)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Check and map HW resources */</div><div class='add'>+	if (result &amp;&amp; !dml_ctx-&gt;config.skip_hw_state_mapping) {</div><div class='add'>+		dml21_map_hw_resources(dml_ctx);</div><div class='add'>+		dml2_map_dc_pipes(dml_ctx, context, NULL, &amp;dml_ctx-&gt;v21.dml_to_dc_pipe_mapping, in_dc-&gt;current_state);</div><div class='add'>+		/* if subvp phantoms are present, expand them into dc context */</div><div class='add'>+		dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx);</div><div class='add'>+</div><div class='add'>+		if (in_dc-&gt;res_pool-&gt;funcs-&gt;program_mcache_pipe_config) {</div><div class='add'>+			//Prepare mcache params for each plane based on mcache output from DML</div><div class='add'>+			dml21_prepare_mcache_params(dml_ctx, context, mcache_params);</div><div class='add'>+</div><div class='add'>+			//populate mcache regs to each pipe</div><div class='add'>+			dml_ctx-&gt;config.callbacks.allocate_mcache(context, mcache_params);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Copy DML CLK, WM and REG outputs to bandwidth context */</div><div class='add'>+	if (result &amp;&amp; !dml_ctx-&gt;config.skip_hw_state_mapping) {</div><div class='add'>+		dml21_calculate_rq_and_dlg_params(in_dc, context, &amp;context-&gt;res_ctx, dml_ctx, in_dc-&gt;res_pool-&gt;pipe_count);</div><div class='add'>+		dml21_copy_clocks_to_dc_state(dml_ctx, context);</div><div class='add'>+		dml21_extract_watermark_sets(in_dc, &amp;context-&gt;bw_ctx.bw.dcn.watermarks, dml_ctx);</div><div class='add'>+		dml21_build_fams2_programming(in_dc, context, dml_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	bool is_supported = false;</div><div class='add'>+	struct dml2_initialize_instance_in_out *dml_init = &amp;dml_ctx-&gt;v21.dml_init;</div><div class='add'>+	struct dml2_check_mode_supported_in_out *mode_support = &amp;dml_ctx-&gt;v21.mode_support;</div><div class='add'>+</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.display_config, 0, sizeof(struct dml2_display_cfg));</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));</div><div class='add'>+	memset(&amp;dml_ctx-&gt;v21.mode_programming.dml2_instance-&gt;scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out));</div><div class='add'>+</div><div class='add'>+	if (!context || context-&gt;stream_count == 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* Scrub phantom's from current dc_state */</div><div class='add'>+	dml_ctx-&gt;config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);</div><div class='add'>+	dml_ctx-&gt;config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);</div><div class='add'>+</div><div class='add'>+	mode_support-&gt;dml2_instance = dml_init-&gt;dml2_instance;</div><div class='add'>+	dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);</div><div class='add'>+	dml_ctx-&gt;v21.mode_programming.dml2_instance-&gt;scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx-&gt;v21.mode_programming.programming;</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	is_supported = dml2_check_mode_supported(mode_support);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+	if (!is_supported)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	bool out = false;</div><div class='add'>+</div><div class='add'>+	/* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='add'>+		out = dml21_check_mode_support(in_dc, context, dml_ctx);</div><div class='add'>+	else</div><div class='add'>+		out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);</div><div class='add'>+</div><div class='add'>+	return out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)</div><div class='add'>+{</div><div class='add'>+	unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;</div><div class='add'>+	int num_pipes;</div><div class='add'>+	struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];</div><div class='add'>+	struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};</div><div class='add'>+</div><div class='add'>+	struct dml2_per_plane_programming *pln_prog = NULL;</div><div class='add'>+	struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL;</div><div class='add'>+	struct prepare_mcache_programming_locals *l = &amp;dml_ctx-&gt;v21.scratch.prepare_mcache_locals;</div><div class='add'>+</div><div class='add'>+	if (context-&gt;stream_count == 0) {</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(&amp;l-&gt;build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out));</div><div class='add'>+	l-&gt;build_mcache_programming_params.dml2_instance = dml_ctx-&gt;v21.dml_init.dml2_instance;</div><div class='add'>+</div><div class='add'>+	/* phantom's start after main planes */</div><div class='add'>+	dml_phantom_prog_idx = dml_ctx-&gt;v21.mode_programming.programming-&gt;display_config.num_planes;</div><div class='add'>+</div><div class='add'>+	/* Build mcache programming parameters per plane per pipe */</div><div class='add'>+	for (dml_prog_idx = 0; dml_prog_idx &lt; dml_ctx-&gt;v21.mode_programming.programming-&gt;display_config.num_planes; dml_prog_idx++) {</div><div class='add'>+		pln_prog = &amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_prog_idx];</div><div class='add'>+</div><div class='add'>+		mcache_config = &amp;l-&gt;build_mcache_programming_params.mcache_configurations[dml_prog_idx];</div><div class='add'>+		memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));</div><div class='add'>+		mcache_config-&gt;plane_descriptor = pln_prog-&gt;plane_descriptor;</div><div class='add'>+		mcache_config-&gt;mcache_allocation = &amp;context-&gt;bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];</div><div class='add'>+		mcache_config-&gt;num_pipes = pln_prog-&gt;num_dpps_required;</div><div class='add'>+		l-&gt;build_mcache_programming_params.num_configurations++;</div><div class='add'>+</div><div class='add'>+		if (pln_prog-&gt;num_dpps_required == 0) {</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);</div><div class='add'>+		if (num_pipes &lt;= 0 || dc_main_pipes[0]-&gt;stream == NULL ||</div><div class='add'>+		    dc_main_pipes[0]-&gt;plane_state == NULL)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* get config for each pipe */</div><div class='add'>+		for (dc_pipe_index = 0; dc_pipe_index &lt; num_pipes; dc_pipe_index++) {</div><div class='add'>+			ASSERT(dc_main_pipes[dc_pipe_index]);</div><div class='add'>+			dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &amp;mcache_config-&gt;pipe_configurations[dc_pipe_index]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* get config for each phantom pipe */</div><div class='add'>+		if (pln_prog-&gt;phantom_plane.valid &amp;&amp;</div><div class='add'>+				dc_phantom_pipes[0] &amp;&amp;</div><div class='add'>+				dc_main_pipes[0]-&gt;stream &amp;&amp;</div><div class='add'>+				dc_phantom_pipes[0]-&gt;plane_state) {</div><div class='add'>+			mcache_config = &amp;l-&gt;build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx];</div><div class='add'>+			memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));</div><div class='add'>+			mcache_config-&gt;plane_descriptor = pln_prog-&gt;plane_descriptor;</div><div class='add'>+			mcache_config-&gt;mcache_allocation = &amp;context-&gt;bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];</div><div class='add'>+			mcache_config-&gt;num_pipes = pln_prog-&gt;num_dpps_required;</div><div class='add'>+			l-&gt;build_mcache_programming_params.num_configurations++;</div><div class='add'>+</div><div class='add'>+			for (dc_pipe_index = 0; dc_pipe_index &lt; num_pipes; dc_pipe_index++) {</div><div class='add'>+				ASSERT(dc_phantom_pipes[dc_pipe_index]);</div><div class='add'>+				dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &amp;mcache_config-&gt;pipe_configurations[dc_pipe_index]);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* increment phantom index */</div><div class='add'>+			dml_phantom_prog_idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Call to generate mcache programming per plane per pipe for the given display configuration */</div><div class='add'>+	dml2_build_mcache_programming(&amp;l-&gt;build_mcache_programming_params);</div><div class='add'>+</div><div class='add'>+	/* get per plane per pipe mcache programming */</div><div class='add'>+	for (dml_prog_idx = 0; dml_prog_idx &lt; dml_ctx-&gt;v21.mode_programming.programming-&gt;display_config.num_planes; dml_prog_idx++) {</div><div class='add'>+		pln_prog = &amp;dml_ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[dml_prog_idx];</div><div class='add'>+</div><div class='add'>+		num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);</div><div class='add'>+		if (num_pipes &lt;= 0 || dc_main_pipes[0]-&gt;stream == NULL ||</div><div class='add'>+		    dc_main_pipes[0]-&gt;plane_state == NULL)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* get config for each pipe */</div><div class='add'>+		for (dc_pipe_index = 0; dc_pipe_index &lt; num_pipes; dc_pipe_index++) {</div><div class='add'>+			ASSERT(dc_main_pipes[dc_pipe_index]);</div><div class='add'>+			if (l-&gt;build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) {</div><div class='add'>+				memcpy(&amp;dc_main_pipes[dc_pipe_index]-&gt;mcache_regs,</div><div class='add'>+						l-&gt;build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index],</div><div class='add'>+						sizeof(struct dml2_hubp_pipe_mcache_regs));</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* get config for each phantom pipe */</div><div class='add'>+		if (pln_prog-&gt;phantom_plane.valid &amp;&amp;</div><div class='add'>+				dc_phantom_pipes[0] &amp;&amp;</div><div class='add'>+				dc_main_pipes[0]-&gt;stream &amp;&amp;</div><div class='add'>+				dc_phantom_pipes[0]-&gt;plane_state) {</div><div class='add'>+			for (dc_pipe_index = 0; dc_pipe_index &lt; num_pipes; dc_pipe_index++) {</div><div class='add'>+				ASSERT(dc_phantom_pipes[dc_pipe_index]);</div><div class='add'>+				if (l-&gt;build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) {</div><div class='add'>+					memcpy(&amp;dc_phantom_pipes[dc_pipe_index]-&gt;mcache_regs,</div><div class='add'>+							l-&gt;build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index],</div><div class='add'>+							sizeof(struct dml2_hubp_pipe_mcache_regs));</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			/* increment phantom index */</div><div class='add'>+			dml_phantom_prog_idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_copy(struct dml2_context *dst_dml_ctx,</div><div class='add'>+	struct dml2_context *src_dml_ctx)</div><div class='add'>+{</div><div class='add'>+	/* Preserve references to internals */</div><div class='add'>+	struct dml2_instance *dst_dml2_instance = dst_dml_ctx-&gt;v21.dml_init.dml2_instance;</div><div class='add'>+	struct dml2_display_cfg_programming *dst_dml2_programming = dst_dml_ctx-&gt;v21.mode_programming.programming;</div><div class='add'>+</div><div class='add'>+	/* Copy context */</div><div class='add'>+	memcpy(dst_dml_ctx, src_dml_ctx, sizeof(struct dml2_context));</div><div class='add'>+</div><div class='add'>+	/* Copy Internals */</div><div class='add'>+	memcpy(dst_dml2_instance, src_dml_ctx-&gt;v21.dml_init.dml2_instance, sizeof(struct dml2_instance));</div><div class='add'>+	memcpy(dst_dml2_programming, src_dml_ctx-&gt;v21.mode_programming.programming, sizeof(struct dml2_display_cfg_programming));</div><div class='add'>+</div><div class='add'>+	/* Restore references to internals */</div><div class='add'>+	dst_dml_ctx-&gt;v21.dml_init.dml2_instance = dst_dml2_instance;</div><div class='add'>+</div><div class='add'>+	dst_dml_ctx-&gt;v21.mode_support.dml2_instance = dst_dml2_instance;</div><div class='add'>+	dst_dml_ctx-&gt;v21.mode_programming.dml2_instance = dst_dml2_instance;</div><div class='add'>+</div><div class='add'>+	dst_dml_ctx-&gt;v21.mode_support.display_config = &amp;dst_dml_ctx-&gt;v21.display_config;</div><div class='add'>+	dst_dml_ctx-&gt;v21.mode_programming.display_config = dst_dml_ctx-&gt;v21.mode_support.display_config;</div><div class='add'>+</div><div class='add'>+	dst_dml_ctx-&gt;v21.mode_programming.programming = dst_dml2_programming;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+</div><div class='add'>+	/* need to initialize copied instance for internal references to be correct */</div><div class='add'>+	dml2_initialize_instance(&amp;dst_dml_ctx-&gt;v21.dml_init);</div><div class='add'>+</div><div class='add'>+	DC_FP_END();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml21_create_copy(struct dml2_context **dst_dml_ctx,</div><div class='add'>+	struct dml2_context *src_dml_ctx)</div><div class='add'>+{</div><div class='add'>+	/* Allocate memory for initializing DML21 instance */</div><div class='add'>+	if (!dml21_allocate_memory(dst_dml_ctx))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dml21_copy(*dst_dml_ctx, src_dml_ctx);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	dml21_init(in_dc, dml_ctx, config);</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h<br/>new file mode 100644<br/>index 000000000000..15f92029d2e5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h</a></div><div class='hunk'>@@ -0,0 +1,135 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifndef _DML21_WRAPPER_H_</div><div class='add'>+#define _DML21_WRAPPER_H_</div><div class='add'>+</div><div class='add'>+#include "os_types.h"</div><div class='add'>+#include "dml_top_soc_parameter_types.h"</div><div class='add'>+#include "dml_top_display_cfg_types.h"</div><div class='add'>+</div><div class='add'>+struct dc;</div><div class='add'>+struct dc_state;</div><div class='add'>+struct dml2_configuration_options;</div><div class='add'>+struct dml2_context;</div><div class='add'>+enum dc_validate_mode;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dml2_create - Creates dml21_context.</div><div class='add'>+ * @in_dc: dc.</div><div class='add'>+ * @dml2: Created dml21 context.</div><div class='add'>+ * @config: dml21 configuration options.</div><div class='add'>+ *</div><div class='add'>+ * Create of DML21 is done as part of dc_state creation.</div><div class='add'>+ * DML21 IP, SOC and STATES are initialized at</div><div class='add'>+ * creation time.</div><div class='add'>+ *</div><div class='add'>+ * Return: True if dml2 is successfully created, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);</div><div class='add'>+void dml21_destroy(struct dml2_context *dml2);</div><div class='add'>+void dml21_copy(struct dml2_context *dst_dml_ctx,</div><div class='add'>+	struct dml2_context *src_dml_ctx);</div><div class='add'>+bool dml21_create_copy(struct dml2_context **dst_dml_ctx,</div><div class='add'>+	struct dml2_context *src_dml_ctx);</div><div class='add'>+void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dml21_validate - Determines if a display configuration is supported or not.</div><div class='add'>+ * @in_dc: dc.</div><div class='add'>+ * @context: dc_state to be validated.</div><div class='add'>+ * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX</div><div class='add'>+ *           will not populate context.res_ctx.</div><div class='add'>+ *</div><div class='add'>+ * Based on fast_validate option internally would call:</div><div class='add'>+ *</div><div class='add'>+ * -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option</div><div class='add'>+ * Calculates if dc_state can be supported on the input display</div><div class='add'>+ * configuration. If supported, generates the necessary HW</div><div class='add'>+ * programming for the new dc_state.</div><div class='add'>+ *</div><div class='add'>+ * -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option</div><div class='add'>+ * Calculates if dc_state can be supported for the input display</div><div class='add'>+ * config.</div><div class='add'>+</div><div class='add'>+ * Context: Two threads may not invoke this function concurrently unless they reference</div><div class='add'>+ *          separate dc_states for validation.</div><div class='add'>+ * Return: True if mode is supported, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,</div><div class='add'>+	enum dc_validate_mode validate_mode);</div><div class='add'>+</div><div class='add'>+/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */</div><div class='add'>+void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);</div><div class='add'>+</div><div class='add'>+/* Structure for inputting external SOCBB and DCNIP values for tool based debugging. */</div><div class='add'>+struct socbb_ip_params_external {</div><div class='add'>+	struct dml2_ip_capabilities ip_params;</div><div class='add'>+	struct dml2_soc_bb soc_bb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*mcache parameters decided by dml*/</div><div class='add'>+struct dc_mcache_params {</div><div class='add'>+	bool valid;</div><div class='add'>+	/*</div><div class='add'>+	* For iMALL, dedicated mall mcaches are required (sharing of last</div><div class='add'>+	* slice possible), for legacy phantom or phantom without return</div><div class='add'>+	* the only mall mcaches need to be valid.</div><div class='add'>+	*/</div><div class='add'>+	bool requires_dedicated_mall_mcache;</div><div class='add'>+	unsigned int num_mcaches_plane0;</div><div class='add'>+	unsigned int num_mcaches_plane1;</div><div class='add'>+	/*</div><div class='add'>+	* Generally, plane0/1 slices must use a disjoint set of caches</div><div class='add'>+	* but in some cases the final segement of the two planes can</div><div class='add'>+	* use the same cache. If plane0_plane1 is set, then this is</div><div class='add'>+	* allowed.</div><div class='add'>+	*</div><div class='add'>+	* Similarly, the caches allocated to MALL prefetcher are generally</div><div class='add'>+	* disjoint, but if mall_prefetch is set, then the final segment</div><div class='add'>+	* between the main and the mall pixel requestor can use the same</div><div class='add'>+	* cache.</div><div class='add'>+	*</div><div class='add'>+	* Note that both bits may be set at the same time.</div><div class='add'>+	*/</div><div class='add'>+	struct {</div><div class='add'>+		bool mall_comb_mcache_p0;</div><div class='add'>+		bool mall_comb_mcache_p1;</div><div class='add'>+		bool plane0_plane1;</div><div class='add'>+	} last_slice_sharing;</div><div class='add'>+	/*</div><div class='add'>+	* A plane is divided into vertical slices of mcaches,</div><div class='add'>+	* which wrap on the surface width.</div><div class='add'>+	*</div><div class='add'>+	* For example, if the surface width is 7680, and split into</div><div class='add'>+	* three slices of equal width, the boundary array would contain</div><div class='add'>+	* [2560, 5120, 7680]</div><div class='add'>+	*</div><div class='add'>+	* The assignments are</div><div class='add'>+	* 0 = [0 .. 2559]</div><div class='add'>+	* 1 = [2560 .. 5119]</div><div class='add'>+	* 2 = [5120 .. 7679]</div><div class='add'>+	* 0 = [7680 .. INF]</div><div class='add'>+	* The final element implicitly is the same as the first, and</div><div class='add'>+	* at first seems invalid since it is never referenced (since)</div><div class='add'>+	* it is outside the surface. However, its useful when shifting</div><div class='add'>+	* (see below).</div><div class='add'>+	*</div><div class='add'>+	* For any given valid mcache assignment, a shifted version, wrapped</div><div class='add'>+	* on the surface width boundary is also assumed to be valid.</div><div class='add'>+	*</div><div class='add'>+	* For example, shifting [2560, 5120, 7680] by -50 results in</div><div class='add'>+	* [2510, 5170, 7630].</div><div class='add'>+	*</div><div class='add'>+	* The assignments are now:</div><div class='add'>+	* 0 = [0 .. 2509]</div><div class='add'>+	* 1 = [2510 .. 5169]</div><div class='add'>+	* 2 = [5170 .. 7629]</div><div class='add'>+	* 0 = [7630 .. INF]</div><div class='add'>+	*/</div><div class='add'>+	int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];</div><div class='add'>+	int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h<br/>new file mode 100644<br/>index 000000000000..16a4f97bca4e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h</a></div><div class='hunk'>@@ -0,0 +1,372 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML_DML_DCN4_SOC_BB__</div><div class='add'>+#define __DML_DML_DCN4_SOC_BB__</div><div class='add'>+</div><div class='add'>+#include "dml_top_soc_parameter_types.h"</div><div class='add'>+</div><div class='add'>+static const struct dml2_soc_qos_parameters dml_dcn4_variant_a_soc_qos_params = {</div><div class='add'>+	.derate_table = {</div><div class='add'>+		.system_active_urgent = {</div><div class='add'>+			.dram_derate_percent_pixel = 22,</div><div class='add'>+			.dram_derate_percent_vm = 0,</div><div class='add'>+			.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+			.fclk_derate_percent = 76,</div><div class='add'>+			.dcfclk_derate_percent = 100,</div><div class='add'>+		},</div><div class='add'>+		.system_active_average = {</div><div class='add'>+			.dram_derate_percent_pixel = 17,</div><div class='add'>+			.dram_derate_percent_vm = 0,</div><div class='add'>+			.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+			.fclk_derate_percent = 57,</div><div class='add'>+			.dcfclk_derate_percent = 75,</div><div class='add'>+		},</div><div class='add'>+		.dcn_mall_prefetch_urgent = {</div><div class='add'>+			.dram_derate_percent_pixel = 40,</div><div class='add'>+			.dram_derate_percent_vm = 0,</div><div class='add'>+			.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+			.fclk_derate_percent = 83,</div><div class='add'>+			.dcfclk_derate_percent = 100,</div><div class='add'>+		},</div><div class='add'>+		.dcn_mall_prefetch_average = {</div><div class='add'>+			.dram_derate_percent_pixel = 33,</div><div class='add'>+			.dram_derate_percent_vm = 0,</div><div class='add'>+			.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+			.fclk_derate_percent = 62,</div><div class='add'>+			.dcfclk_derate_percent = 83,</div><div class='add'>+		},</div><div class='add'>+		.system_idle_average = {</div><div class='add'>+			.dram_derate_percent_pixel = 70,</div><div class='add'>+			.dram_derate_percent_vm = 0,</div><div class='add'>+			.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+			.fclk_derate_percent = 83,</div><div class='add'>+			.dcfclk_derate_percent = 100,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	.writeback = {</div><div class='add'>+		.base_latency_us = 12,</div><div class='add'>+		.scaling_factor_us = 0,</div><div class='add'>+		.scaling_factor_mhz = 0,</div><div class='add'>+	},</div><div class='add'>+	.qos_params = {</div><div class='add'>+		.dcn4x = {</div><div class='add'>+			.df_qos_response_time_fclk_cycles = 300,</div><div class='add'>+			.max_round_trip_to_furthest_cs_fclk_cycles = 350,</div><div class='add'>+			.mall_overhead_fclk_cycles = 50,</div><div class='add'>+			.meta_trip_adder_fclk_cycles = 36,</div><div class='add'>+			.average_transport_distance_fclk_cycles = 257,</div><div class='add'>+			.umc_urgent_ramp_latency_margin = 50,</div><div class='add'>+			.umc_max_latency_margin = 30,</div><div class='add'>+			.umc_average_latency_margin = 20,</div><div class='add'>+			.fabric_max_transport_latency_margin = 20,</div><div class='add'>+			.fabric_average_transport_latency_margin = 10,</div><div class='add'>+</div><div class='add'>+			.per_uclk_dpm_params = {</div><div class='add'>+				{</div><div class='add'>+					.minimum_uclk_khz = 97 * 1000,</div><div class='add'>+					.urgent_ramp_uclk_cycles = 472,</div><div class='add'>+					.trip_to_memory_uclk_cycles = 827,</div><div class='add'>+					.meta_trip_to_memory_uclk_cycles = 827,</div><div class='add'>+					.maximum_latency_when_urgent_uclk_cycles = 72,</div><div class='add'>+					.average_latency_when_urgent_uclk_cycles = 61,</div><div class='add'>+					.maximum_latency_when_non_urgent_uclk_cycles = 827,</div><div class='add'>+					.average_latency_when_non_urgent_uclk_cycles = 118,</div><div class='add'>+				},</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	.qos_type = dml2_qos_param_type_dcn4x,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dml2_soc_bb dml2_socbb_dcn401 = {</div><div class='add'>+	.clk_table = {</div><div class='add'>+		.uclk = {</div><div class='add'>+				.clk_values_khz = {97000},</div><div class='add'>+				.num_clk_values = 1,</div><div class='add'>+		},</div><div class='add'>+		.fclk = {</div><div class='add'>+				.clk_values_khz = {300000, 2500000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.dcfclk = {</div><div class='add'>+				.clk_values_khz = {200000, 1564000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.dispclk = {</div><div class='add'>+				.clk_values_khz = {100000, 2000000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.dppclk = {</div><div class='add'>+				.clk_values_khz = {100000, 2000000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.dtbclk = {</div><div class='add'>+				.clk_values_khz = {100000, 1564000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.phyclk = {</div><div class='add'>+				.clk_values_khz = {810000, 810000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.socclk = {</div><div class='add'>+				.clk_values_khz = {300000, 1200000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.dscclk = {</div><div class='add'>+				.clk_values_khz = {666667, 666667},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.phyclk_d18 = {</div><div class='add'>+				.clk_values_khz = {625000, 625000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.phyclk_d32 = {</div><div class='add'>+				.clk_values_khz = {625000, 625000},</div><div class='add'>+				.num_clk_values = 2,</div><div class='add'>+		},</div><div class='add'>+		.dram_config = {</div><div class='add'>+			.channel_width_bytes = 2,</div><div class='add'>+			.channel_count = 16,</div><div class='add'>+			.transactions_per_clock = 16,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	.qos_parameters = {</div><div class='add'>+		.derate_table = {</div><div class='add'>+			.system_active_urgent = {</div><div class='add'>+				.dram_derate_percent_pixel = 22,</div><div class='add'>+				.dram_derate_percent_vm = 0,</div><div class='add'>+				.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+				.fclk_derate_percent = 76,</div><div class='add'>+				.dcfclk_derate_percent = 100,</div><div class='add'>+			},</div><div class='add'>+			.system_active_average = {</div><div class='add'>+				.dram_derate_percent_pixel = 15,</div><div class='add'>+				.dram_derate_percent_vm = 0,</div><div class='add'>+				.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+				.fclk_derate_percent = 57,</div><div class='add'>+				.dcfclk_derate_percent = 75,</div><div class='add'>+			},</div><div class='add'>+			.dcn_mall_prefetch_urgent = {</div><div class='add'>+				.dram_derate_percent_pixel = 40,</div><div class='add'>+				.dram_derate_percent_vm = 0,</div><div class='add'>+				.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+				.fclk_derate_percent = 83,</div><div class='add'>+				.dcfclk_derate_percent = 100,</div><div class='add'>+			},</div><div class='add'>+			.dcn_mall_prefetch_average = {</div><div class='add'>+				.dram_derate_percent_pixel = 30,</div><div class='add'>+				.dram_derate_percent_vm = 0,</div><div class='add'>+				.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+				.fclk_derate_percent = 62,</div><div class='add'>+				.dcfclk_derate_percent = 83,</div><div class='add'>+			},</div><div class='add'>+			.system_idle_average = {</div><div class='add'>+				.dram_derate_percent_pixel = 70,</div><div class='add'>+				.dram_derate_percent_vm = 0,</div><div class='add'>+				.dram_derate_percent_pixel_and_vm = 0,</div><div class='add'>+				.fclk_derate_percent = 83,</div><div class='add'>+				.dcfclk_derate_percent = 100,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.writeback = {</div><div class='add'>+			.base_latency_us = 0,</div><div class='add'>+			.scaling_factor_us = 0,</div><div class='add'>+			.scaling_factor_mhz = 0,</div><div class='add'>+		},</div><div class='add'>+		.qos_params = {</div><div class='add'>+			.dcn4x = {</div><div class='add'>+				.df_qos_response_time_fclk_cycles = 300,</div><div class='add'>+				.max_round_trip_to_furthest_cs_fclk_cycles = 350,</div><div class='add'>+				.mall_overhead_fclk_cycles = 50,</div><div class='add'>+				.meta_trip_adder_fclk_cycles = 36,</div><div class='add'>+				.average_transport_distance_fclk_cycles = 260,</div><div class='add'>+				.umc_urgent_ramp_latency_margin = 50,</div><div class='add'>+				.umc_max_latency_margin = 30,</div><div class='add'>+				.umc_average_latency_margin = 20,</div><div class='add'>+				.fabric_max_transport_latency_margin = 20,</div><div class='add'>+				.fabric_average_transport_latency_margin = 10,</div><div class='add'>+</div><div class='add'>+				.per_uclk_dpm_params = {</div><div class='add'>+					{</div><div class='add'>+						// State 1</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 472,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 827,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 827,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 72,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 72,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 827,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 117,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 2</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 546,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 848,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 848,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 146,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 146,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 848,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 133,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 3</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 564,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 853,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 853,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 164,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 164,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 853,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 136,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 4</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 613,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 869,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 869,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 213,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 213,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 869,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 149,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 5</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 632,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 874,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 874,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 232,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 232,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 874,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 153,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 6</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 665,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 885,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 885,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 265,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 265,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 885,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 161,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 7</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 689,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 895,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 895,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 289,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 289,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 895,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 167,</div><div class='add'>+					},</div><div class='add'>+					{</div><div class='add'>+						// State 8</div><div class='add'>+						.minimum_uclk_khz = 0,</div><div class='add'>+						.urgent_ramp_uclk_cycles = 716,</div><div class='add'>+						.trip_to_memory_uclk_cycles = 902,</div><div class='add'>+						.meta_trip_to_memory_uclk_cycles = 902,</div><div class='add'>+						.maximum_latency_when_urgent_uclk_cycles = 316,</div><div class='add'>+						.average_latency_when_urgent_uclk_cycles = 316,</div><div class='add'>+						.maximum_latency_when_non_urgent_uclk_cycles = 902,</div><div class='add'>+						.average_latency_when_non_urgent_uclk_cycles = 174,</div><div class='add'>+					},</div><div class='add'>+				},</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.qos_type = dml2_qos_param_type_dcn4x,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	.power_management_parameters = {</div><div class='add'>+		.dram_clk_change_blackout_us = 400,</div><div class='add'>+		.fclk_change_blackout_us = 0,</div><div class='add'>+		.g7_ppt_blackout_us = 0,</div><div class='add'>+		.stutter_enter_plus_exit_latency_us = 54,</div><div class='add'>+		.stutter_exit_latency_us = 41,</div><div class='add'>+		.z8_stutter_enter_plus_exit_latency_us = 0,</div><div class='add'>+		.z8_stutter_exit_latency_us = 0,</div><div class='add'>+		/*</div><div class='add'>+		.g6_temp_read_blackout_us = {</div><div class='add'>+			23.00,</div><div class='add'>+			10.00,</div><div class='add'>+			10.00,</div><div class='add'>+			8.00,</div><div class='add'>+			8.00,</div><div class='add'>+			5.00,</div><div class='add'>+			5.00,</div><div class='add'>+			5.00,</div><div class='add'>+		},</div><div class='add'>+		*/</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	 .vmin_limit = {</div><div class='add'>+		.dispclk_khz = 600 * 1000,</div><div class='add'>+	 },</div><div class='add'>+</div><div class='add'>+	.dprefclk_mhz = 720,</div><div class='add'>+	.xtalclk_mhz = 100,</div><div class='add'>+	.pcie_refclk_mhz = 100,</div><div class='add'>+	.dchub_refclk_mhz = 50,</div><div class='add'>+	.mall_allocated_for_dcn_mbytes = 64,</div><div class='add'>+	.max_outstanding_reqs = 512,</div><div class='add'>+	.fabric_datapath_to_dcn_data_return_bytes = 64,</div><div class='add'>+	.return_bus_width_bytes = 64,</div><div class='add'>+	.hostvm_min_page_size_kbytes = 0,</div><div class='add'>+	.gpuvm_min_page_size_kbytes = 256,</div><div class='add'>+	.phy_downspread_percent = 0.38,</div><div class='add'>+	.dcn_downspread_percent = 0.38,</div><div class='add'>+	.dispclk_dppclk_vco_speed_mhz = 4500,</div><div class='add'>+	.do_urgent_latency_adjustment = 0,</div><div class='add'>+	.mem_word_bytes = 32,</div><div class='add'>+	.num_dcc_mcaches = 8,</div><div class='add'>+	.mcache_size_bytes = 2048,</div><div class='add'>+	.mcache_line_size_bytes = 32,</div><div class='add'>+	.max_fclk_for_uclk_dpm_khz = 1250 * 1000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = {</div><div class='add'>+	.pipe_count = 4,</div><div class='add'>+	.otg_count = 4,</div><div class='add'>+	.num_dsc = 4,</div><div class='add'>+	.max_num_dp2p0_streams = 4,</div><div class='add'>+	.max_num_hdmi_frl_outputs = 1,</div><div class='add'>+	.max_num_dp2p0_outputs = 4,</div><div class='add'>+	.rob_buffer_size_kbytes = 192,</div><div class='add'>+	.config_return_buffer_size_in_kbytes = 1344,</div><div class='add'>+	.config_return_buffer_segment_size_in_kbytes = 64,</div><div class='add'>+	.meta_fifo_size_in_kentries = 22,</div><div class='add'>+	.compressed_buffer_segment_size_in_kbytes = 64,</div><div class='add'>+	.cursor_buffer_size = 24,</div><div class='add'>+	.max_flip_time_us = 80,</div><div class='add'>+	.max_flip_time_lines = 32,</div><div class='add'>+	.hostvm_mode = 0,</div><div class='add'>+	.subvp_drr_scheduling_margin_us = 100,</div><div class='add'>+	.subvp_prefetch_end_to_mall_start_us = 15,</div><div class='add'>+	.subvp_fw_processing_delay = 15,</div><div class='add'>+	.max_vactive_det_fill_delay_us = 400,</div><div class='add'>+</div><div class='add'>+	.fams2 = {</div><div class='add'>+		.max_allow_delay_us = 100 * 1000,</div><div class='add'>+		.scheduling_delay_us = 550,</div><div class='add'>+		.vertical_interrupt_ack_delay_us = 40,</div><div class='add'>+		.allow_programming_delay_us = 18,</div><div class='add'>+		.min_allow_width_us = 20,</div><div class='add'>+		.subvp_df_throttle_delay_us = 100,</div><div class='add'>+		.subvp_programming_delay_us = 200,</div><div class='add'>+		.subvp_prefetch_to_mall_delay_us = 18,</div><div class='add'>+		.drr_programming_delay_us = 35,</div><div class='add'>+</div><div class='add'>+		.lock_timeout_us = 5000,</div><div class='add'>+		.recovery_timeout_us = 5000,</div><div class='add'>+		.flip_programming_delay_us = 300,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h<br/>new file mode 100644<br/>index 000000000000..281d7ad230d8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_EXTERNAL_LIB_DEPS__</div><div class='add'>+#define __DML2_EXTERNAL_LIB_DEPS__</div><div class='add'>+</div><div class='add'>+#include "os_types.h"</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h<br/>new file mode 100644<br/>index 000000000000..a64ec4dcf11a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML_TOP_H__</div><div class='add'>+#define __DML_TOP_H__</div><div class='add'>+</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Top Level Interface for DML2</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Returns the size of the DML instance for the caller to allocate</div><div class='add'>+ */</div><div class='add'>+unsigned int dml2_get_instance_size_bytes(void);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Initializes the DML instance (i.e. with configuration, soc BB, IP params, etc...)</div><div class='add'>+ */</div><div class='add'>+bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines if the input mode is supported (boolean) on the SoC at all.  Does not return</div><div class='add'>+ * information on how mode should be programmed.</div><div class='add'>+ */</div><div class='add'>+bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the full (optimized) programming for the input mode.  Returns minimum</div><div class='add'>+ * clocks as well as dchub register programming values for all pipes, additional meta</div><div class='add'>+ * such as ODM or MPCC combine factors.</div><div class='add'>+ */</div><div class='add'>+bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Determines the correct per pipe mcache register programming for a valid mode.</div><div class='add'>+ * The mcache allocation must have been calculated (successfully) in a previous</div><div class='add'>+ * call to dml2_build_mode_programming.</div><div class='add'>+ * The actual hubp viewport dimensions be what the actual registers will be</div><div class='add'>+ * programmed to (i.e. based on scaler setup).</div><div class='add'>+ */</div><div class='add'>+bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h<br/>new file mode 100644<br/>index 000000000000..bf57df42d1d9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __dml2_TOP_DCHUB_REGISTERS_H__</div><div class='add'>+#define __dml2_TOP_DCHUB_REGISTERS_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+// These types are uint32_t as they represent actual calculated register values for HW</div><div class='add'>+</div><div class='add'>+struct dml2_display_dlg_regs {</div><div class='add'>+	uint32_t refcyc_h_blank_end;</div><div class='add'>+	uint32_t dlg_vblank_end;</div><div class='add'>+	uint32_t min_dst_y_next_start;</div><div class='add'>+	uint32_t refcyc_per_htotal;</div><div class='add'>+	uint32_t refcyc_x_after_scaler;</div><div class='add'>+	uint32_t dst_y_after_scaler;</div><div class='add'>+	uint32_t dst_y_prefetch;</div><div class='add'>+	uint32_t dst_y_per_vm_vblank;</div><div class='add'>+	uint32_t dst_y_per_row_vblank;</div><div class='add'>+	uint32_t dst_y_per_vm_flip;</div><div class='add'>+	uint32_t dst_y_per_row_flip;</div><div class='add'>+	uint32_t ref_freq_to_pix_freq;</div><div class='add'>+	uint32_t vratio_prefetch;</div><div class='add'>+	uint32_t vratio_prefetch_c;</div><div class='add'>+	uint32_t refcyc_per_tdlut_group;</div><div class='add'>+	uint32_t refcyc_per_pte_group_vblank_l;</div><div class='add'>+	uint32_t refcyc_per_pte_group_vblank_c;</div><div class='add'>+	uint32_t refcyc_per_pte_group_flip_l;</div><div class='add'>+	uint32_t refcyc_per_pte_group_flip_c;</div><div class='add'>+	uint32_t dst_y_per_pte_row_nom_l;</div><div class='add'>+	uint32_t dst_y_per_pte_row_nom_c;</div><div class='add'>+	uint32_t refcyc_per_pte_group_nom_l;</div><div class='add'>+	uint32_t refcyc_per_pte_group_nom_c;</div><div class='add'>+	uint32_t refcyc_per_line_delivery_pre_l;</div><div class='add'>+	uint32_t refcyc_per_line_delivery_pre_c;</div><div class='add'>+	uint32_t refcyc_per_line_delivery_l;</div><div class='add'>+	uint32_t refcyc_per_line_delivery_c;</div><div class='add'>+	uint32_t refcyc_per_vm_group_vblank;</div><div class='add'>+	uint32_t refcyc_per_vm_group_flip;</div><div class='add'>+	uint32_t refcyc_per_vm_req_vblank;</div><div class='add'>+	uint32_t refcyc_per_vm_req_flip;</div><div class='add'>+	uint32_t dst_y_offset_cur0;</div><div class='add'>+	uint32_t chunk_hdl_adjust_cur0;</div><div class='add'>+	uint32_t vready_after_vcount0;</div><div class='add'>+	uint32_t dst_y_delta_drq_limit;</div><div class='add'>+	uint32_t refcyc_per_vm_dmdata;</div><div class='add'>+	uint32_t dmdata_dl_delta;</div><div class='add'>+</div><div class='add'>+	// MRQ</div><div class='add'>+	uint32_t refcyc_per_meta_chunk_vblank_l;</div><div class='add'>+	uint32_t refcyc_per_meta_chunk_vblank_c;</div><div class='add'>+	uint32_t refcyc_per_meta_chunk_flip_l;</div><div class='add'>+	uint32_t refcyc_per_meta_chunk_flip_c;</div><div class='add'>+	uint32_t dst_y_per_meta_row_nom_l;</div><div class='add'>+	uint32_t dst_y_per_meta_row_nom_c;</div><div class='add'>+	uint32_t refcyc_per_meta_chunk_nom_l;</div><div class='add'>+	uint32_t refcyc_per_meta_chunk_nom_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_display_ttu_regs {</div><div class='add'>+	uint32_t qos_level_low_wm;</div><div class='add'>+	uint32_t qos_level_high_wm;</div><div class='add'>+	uint32_t min_ttu_vblank;</div><div class='add'>+	uint32_t qos_level_flip;</div><div class='add'>+	uint32_t refcyc_per_req_delivery_l;</div><div class='add'>+	uint32_t refcyc_per_req_delivery_c;</div><div class='add'>+	uint32_t refcyc_per_req_delivery_cur0;</div><div class='add'>+	uint32_t refcyc_per_req_delivery_pre_l;</div><div class='add'>+	uint32_t refcyc_per_req_delivery_pre_c;</div><div class='add'>+	uint32_t refcyc_per_req_delivery_pre_cur0;</div><div class='add'>+	uint32_t qos_level_fixed_l;</div><div class='add'>+	uint32_t qos_level_fixed_c;</div><div class='add'>+	uint32_t qos_level_fixed_cur0;</div><div class='add'>+	uint32_t qos_ramp_disable_l;</div><div class='add'>+	uint32_t qos_ramp_disable_c;</div><div class='add'>+	uint32_t qos_ramp_disable_cur0;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_display_arb_regs {</div><div class='add'>+	uint32_t max_req_outstanding;</div><div class='add'>+	uint32_t min_req_outstanding;</div><div class='add'>+	uint32_t sat_level_us;</div><div class='add'>+	uint32_t hvm_max_qos_commit_threshold;</div><div class='add'>+	uint32_t hvm_min_req_outstand_commit_threshold;</div><div class='add'>+	uint32_t compbuf_reserved_space_kbytes;</div><div class='add'>+	uint32_t compbuf_size;</div><div class='add'>+	uint32_t sdpif_request_rate_limit;</div><div class='add'>+	uint32_t allow_sdpif_rate_limit_when_cstate_req;</div><div class='add'>+	uint32_t dcfclk_deep_sleep_hysteresis;</div><div class='add'>+	uint32_t pstate_stall_threshold;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_cursor_dlg_regs{</div><div class='add'>+	uint32_t dst_x_offset;			   // CURSOR0_DST_X_OFFSET</div><div class='add'>+	uint32_t dst_y_offset;			   // CURSOR0_DST_Y_OFFSET</div><div class='add'>+	uint32_t chunk_hdl_adjust;		   // CURSOR0_CHUNK_HDL_ADJUST</div><div class='add'>+</div><div class='add'>+	uint32_t qos_level_fixed;</div><div class='add'>+	uint32_t qos_ramp_disable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_display_plane_rq_regs {</div><div class='add'>+	uint32_t chunk_size;</div><div class='add'>+	uint32_t min_chunk_size;</div><div class='add'>+	uint32_t dpte_group_size;</div><div class='add'>+	uint32_t mpte_group_size;</div><div class='add'>+	uint32_t swath_height;</div><div class='add'>+	uint32_t pte_row_height_linear;</div><div class='add'>+</div><div class='add'>+	// MRQ</div><div class='add'>+	uint32_t meta_chunk_size;</div><div class='add'>+	uint32_t min_meta_chunk_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_display_rq_regs {</div><div class='add'>+	struct dml2_display_plane_rq_regs rq_regs_l;</div><div class='add'>+	struct dml2_display_plane_rq_regs rq_regs_c;</div><div class='add'>+	uint32_t drq_expansion_mode;</div><div class='add'>+	uint32_t prq_expansion_mode;</div><div class='add'>+	uint32_t crq_expansion_mode;</div><div class='add'>+	uint32_t plane1_base_address;</div><div class='add'>+	uint32_t unbounded_request_enabled;</div><div class='add'>+	bool pte_buffer_mode;</div><div class='add'>+	bool force_one_row_for_frame;</div><div class='add'>+</div><div class='add'>+	// MRQ</div><div class='add'>+	uint32_t mrq_expansion_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_display_mcache_regs {</div><div class='add'>+	uint32_t mcache_id_first;</div><div class='add'>+	uint32_t mcache_id_second;</div><div class='add'>+	uint32_t split_location;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_hubp_pipe_mcache_regs {</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_display_mcache_regs p0;</div><div class='add'>+		struct dml2_display_mcache_regs p1;</div><div class='add'>+	} main;</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_display_mcache_regs p0;</div><div class='add'>+		struct dml2_display_mcache_regs p1;</div><div class='add'>+	} mall;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dchub_per_pipe_register_set {</div><div class='add'>+	struct dml2_display_rq_regs rq_regs;</div><div class='add'>+	struct dml2_display_ttu_regs ttu_regs;</div><div class='add'>+	struct dml2_display_dlg_regs dlg_regs;</div><div class='add'>+</div><div class='add'>+	uint32_t det_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dchub_watermark_regs {</div><div class='add'>+	/* watermarks */</div><div class='add'>+	uint32_t urgent;</div><div class='add'>+	uint32_t sr_enter;</div><div class='add'>+	uint32_t sr_exit;</div><div class='add'>+	uint32_t sr_enter_z8;</div><div class='add'>+	uint32_t sr_exit_z8;</div><div class='add'>+	uint32_t sr_enter_low_power;</div><div class='add'>+	uint32_t sr_exit_low_power;</div><div class='add'>+	uint32_t uclk_pstate;</div><div class='add'>+	uint32_t fclk_pstate;</div><div class='add'>+	uint32_t temp_read_or_ppt;</div><div class='add'>+	uint32_t usr;</div><div class='add'>+	/* qos */</div><div class='add'>+	uint32_t refcyc_per_trip_to_mem;</div><div class='add'>+	uint32_t refcyc_per_meta_trip_to_mem;</div><div class='add'>+	uint32_t frac_urg_bw_flip;</div><div class='add'>+	uint32_t frac_urg_bw_nom;</div><div class='add'>+	uint32_t frac_urg_bw_mall;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_dchub_watermark_reg_set_index {</div><div class='add'>+	DML2_DCHUB_WATERMARK_SET_A = 0,</div><div class='add'>+	DML2_DCHUB_WATERMARK_SET_B = 1,</div><div class='add'>+	DML2_DCHUB_WATERMARK_SET_C = 2,</div><div class='add'>+	DML2_DCHUB_WATERMARK_SET_D = 3,</div><div class='add'>+	DML2_DCHUB_WATERMARK_SET_NUM = 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dchub_global_register_set {</div><div class='add'>+	struct dml2_display_arb_regs arb_regs;</div><div class='add'>+	struct dml2_dchub_watermark_regs wm_regs[DML2_DCHUB_WATERMARK_SET_NUM];</div><div class='add'>+	unsigned int num_watermark_sets;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h<br/>new file mode 100644<br/>index 000000000000..35aa954248cd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h</a></div><div class='hunk'>@@ -0,0 +1,526 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML_TOP_DISPLAY_CFG_TYPES_H__</div><div class='add'>+#define __DML_TOP_DISPLAY_CFG_TYPES_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+</div><div class='add'>+#define DML2_MAX_PLANES 8</div><div class='add'>+#define DML2_MAX_DCN_PIPES 8</div><div class='add'>+#define DML2_MAX_MCACHES 8 // assume plane is going to be supported by a max of 8 mcaches</div><div class='add'>+#define DML2_MAX_WRITEBACK 3</div><div class='add'>+</div><div class='add'>+enum dml2_swizzle_mode {</div><div class='add'>+	dml2_sw_linear, // SW_LINEAR accepts 256 byte aligned pitch and also 128 byte aligned pitch if DCC is not enabled</div><div class='add'>+	dml2_sw_256b_2d,</div><div class='add'>+	dml2_sw_4kb_2d,</div><div class='add'>+	dml2_sw_64kb_2d,</div><div class='add'>+	dml2_sw_256kb_2d,</div><div class='add'>+</div><div class='add'>+	dml2_gfx11_sw_linear,</div><div class='add'>+	dml2_gfx11_sw_64kb_d,</div><div class='add'>+	dml2_gfx11_sw_64kb_d_t,</div><div class='add'>+	dml2_gfx11_sw_64kb_d_x,</div><div class='add'>+	dml2_gfx11_sw_64kb_r_x,</div><div class='add'>+	dml2_gfx11_sw_256kb_d_x,</div><div class='add'>+	dml2_gfx11_sw_256kb_r_x,</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_source_format_class {</div><div class='add'>+	dml2_444_8 = 0,</div><div class='add'>+	dml2_444_16 = 1,</div><div class='add'>+	dml2_444_32 = 2,</div><div class='add'>+	dml2_444_64 = 3,</div><div class='add'>+	dml2_420_8 = 4,</div><div class='add'>+	dml2_420_10 = 5,</div><div class='add'>+	dml2_420_12 = 6,</div><div class='add'>+	dml2_rgbe_alpha = 9,</div><div class='add'>+	dml2_rgbe = 10,</div><div class='add'>+	dml2_mono_8 = 11,</div><div class='add'>+	dml2_mono_16 = 12,</div><div class='add'>+	dml2_422_planar_8 = 13,</div><div class='add'>+	dml2_422_planar_10 = 14,</div><div class='add'>+	dml2_422_planar_12 = 15,</div><div class='add'>+	dml2_422_packed_8 = 16,</div><div class='add'>+	dml2_422_packed_10 = 17,</div><div class='add'>+	dml2_422_packed_12 = 18</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_sample_positioning {</div><div class='add'>+	dml2_interstitial = 0,</div><div class='add'>+	dml2_cosited = 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_rotation_angle {</div><div class='add'>+	dml2_rotation_0 = 0,</div><div class='add'>+	dml2_rotation_90 = 1,</div><div class='add'>+	dml2_rotation_180 = 2,</div><div class='add'>+	dml2_rotation_270 = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_output_format_class {</div><div class='add'>+	dml2_444 = 0,</div><div class='add'>+	dml2_s422 = 1,</div><div class='add'>+	dml2_n422 = 2,</div><div class='add'>+	dml2_420 = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_output_encoder_class {</div><div class='add'>+	dml2_dp = 0,</div><div class='add'>+	dml2_edp = 1,</div><div class='add'>+	dml2_dp2p0 = 2,</div><div class='add'>+	dml2_hdmi = 3,</div><div class='add'>+	dml2_hdmifrl = 4,</div><div class='add'>+	dml2_none = 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_output_link_dp_rate {</div><div class='add'>+	dml2_dp_rate_na = 0,</div><div class='add'>+	dml2_dp_rate_hbr = 1,</div><div class='add'>+	dml2_dp_rate_hbr2 = 2,</div><div class='add'>+	dml2_dp_rate_hbr3 = 3,</div><div class='add'>+	dml2_dp_rate_uhbr10 = 4,</div><div class='add'>+	dml2_dp_rate_uhbr13p5 = 5,</div><div class='add'>+	dml2_dp_rate_uhbr20 = 6</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_pstate_type {</div><div class='add'>+	dml2_pstate_type_uclk = 0,</div><div class='add'>+	dml2_pstate_type_fclk = 1,</div><div class='add'>+	dml2_pstate_type_ppt = 2,</div><div class='add'>+	dml2_pstate_type_temp_read = 3,</div><div class='add'>+	dml2_pstate_type_dummy_pstate = 4,</div><div class='add'>+	dml2_pstate_type_count = 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_uclk_pstate_change_strategy {</div><div class='add'>+	dml2_uclk_pstate_change_strategy_auto = 0,</div><div class='add'>+	dml2_uclk_pstate_change_strategy_force_vactive = 1,</div><div class='add'>+	dml2_uclk_pstate_change_strategy_force_vblank = 2,</div><div class='add'>+	dml2_uclk_pstate_change_strategy_force_drr = 3,</div><div class='add'>+	dml2_uclk_pstate_change_strategy_force_mall_svp = 4,</div><div class='add'>+	dml2_uclk_pstate_change_strategy_force_mall_full_frame = 5,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_svp_mode_override {</div><div class='add'>+	dml2_svp_mode_override_auto = 0,</div><div class='add'>+	dml2_svp_mode_override_main_pipe = 1,</div><div class='add'>+	dml2_svp_mode_override_phantom_pipe = 2, //does not need to be defined explicitly, main overrides result in implicit phantom additions</div><div class='add'>+	dml2_svp_mode_override_phantom_pipe_no_data_return = 3,</div><div class='add'>+	dml2_svp_mode_override_imall = 4</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_refresh_from_mall_mode_override {</div><div class='add'>+	dml2_refresh_from_mall_mode_override_auto = 0,</div><div class='add'>+	dml2_refresh_from_mall_mode_override_force_disable = 1,</div><div class='add'>+	dml2_refresh_from_mall_mode_override_force_enable = 2</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_odm_mode {</div><div class='add'>+	dml2_odm_mode_auto = 0,</div><div class='add'>+	dml2_odm_mode_bypass,</div><div class='add'>+	dml2_odm_mode_combine_2to1,</div><div class='add'>+	dml2_odm_mode_combine_3to1,</div><div class='add'>+	dml2_odm_mode_combine_4to1,</div><div class='add'>+	dml2_odm_mode_split_1to2,</div><div class='add'>+	dml2_odm_mode_mso_1to2,</div><div class='add'>+	dml2_odm_mode_mso_1to4</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_scaling_transform {</div><div class='add'>+	dml2_scaling_transform_explicit = 0,</div><div class='add'>+	dml2_scaling_transform_fullscreen,</div><div class='add'>+	dml2_scaling_transform_aspect_ratio,</div><div class='add'>+	dml2_scaling_transform_centered</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_dsc_enable_option {</div><div class='add'>+	dml2_dsc_disable = 0,</div><div class='add'>+	dml2_dsc_enable = 1,</div><div class='add'>+	dml2_dsc_enable_if_necessary = 2</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_tdlut_addressing_mode {</div><div class='add'>+	dml2_tdlut_sw_linear = 0,</div><div class='add'>+	dml2_tdlut_simple_linear = 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_tdlut_width_mode {</div><div class='add'>+	dml2_tdlut_width_17_cube = 0,</div><div class='add'>+	dml2_tdlut_width_33_cube = 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_twait_budgeting_setting {</div><div class='add'>+	dml2_twait_budgeting_setting_ignore = 0,// Ignore this budget in twait</div><div class='add'>+</div><div class='add'>+	dml2_twait_budgeting_setting_if_needed,         // Budget for it only if needed</div><div class='add'>+											//(i.e. UCLK/FCLK DPM cannot be supported in active)</div><div class='add'>+</div><div class='add'>+	dml2_twait_budgeting_setting_try,	   // Budget for it as long as there is an SoC state that</div><div class='add'>+											// can support it</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_get_cursor_dlg_reg{</div><div class='add'>+	unsigned int cursor_x_position;</div><div class='add'>+	unsigned int cursor_hotspot_x;</div><div class='add'>+	unsigned int cursor_primary_offset;</div><div class='add'>+	unsigned int cursor_secondary_offset;</div><div class='add'>+	bool cursor_stereo_en;</div><div class='add'>+	bool cursor_2x_magnify;</div><div class='add'>+	double hratio;</div><div class='add'>+	double pixel_rate_mhz;</div><div class='add'>+	double dlg_refclk_mhz;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/// @brief Surface Parameters</div><div class='add'>+struct dml2_surface_cfg {</div><div class='add'>+	enum dml2_swizzle_mode tiling;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned long pitch; // In elements, two pixels per element in 422 packed format</div><div class='add'>+		unsigned long width;</div><div class='add'>+		unsigned long height;</div><div class='add'>+	} plane0;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned long pitch;</div><div class='add'>+		unsigned long width;</div><div class='add'>+		unsigned long height;</div><div class='add'>+	} plane1;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool enable;</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long pitch;</div><div class='add'>+		} plane0;</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long pitch;</div><div class='add'>+		} plane1;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			double dcc_rate_plane0;</div><div class='add'>+			double dcc_rate_plane1;</div><div class='add'>+			double fraction_of_zero_size_request_plane0;</div><div class='add'>+			double fraction_of_zero_size_request_plane1;</div><div class='add'>+		} informative;</div><div class='add'>+	} dcc;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+struct dml2_composition_cfg {</div><div class='add'>+	enum dml2_rotation_angle rotation_angle;</div><div class='add'>+	bool mirrored;</div><div class='add'>+	enum dml2_scaling_transform scaling_transform;</div><div class='add'>+	bool rect_out_height_spans_vactive;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool stationary;</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long width;</div><div class='add'>+			unsigned long height;</div><div class='add'>+			unsigned long x_start;</div><div class='add'>+			unsigned long y_start;</div><div class='add'>+		} plane0;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long width;</div><div class='add'>+			unsigned long height;</div><div class='add'>+			unsigned long x_start;</div><div class='add'>+			unsigned long y_start;</div><div class='add'>+		} plane1;</div><div class='add'>+	} viewport;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool enabled;</div><div class='add'>+		bool easf_enabled;</div><div class='add'>+		bool isharp_enabled;</div><div class='add'>+		bool upsp_enabled;</div><div class='add'>+		enum dml2_sample_positioning upsp_sample_positioning;</div><div class='add'>+		unsigned int upsp_vtaps;</div><div class='add'>+		struct {</div><div class='add'>+			double h_ratio;</div><div class='add'>+			double v_ratio;</div><div class='add'>+			unsigned int h_taps;</div><div class='add'>+			unsigned int v_taps;</div><div class='add'>+		} plane0;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			double h_ratio;</div><div class='add'>+			double v_ratio;</div><div class='add'>+			unsigned int h_taps;</div><div class='add'>+			unsigned int v_taps;</div><div class='add'>+		} plane1;</div><div class='add'>+</div><div class='add'>+		unsigned long rect_out_width;</div><div class='add'>+	} scaler_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_timing_cfg {</div><div class='add'>+	unsigned long h_total;</div><div class='add'>+	unsigned long v_total;</div><div class='add'>+	unsigned long h_blank_end;</div><div class='add'>+	unsigned long v_blank_end;</div><div class='add'>+	unsigned long h_front_porch;</div><div class='add'>+	unsigned long v_front_porch;</div><div class='add'>+	unsigned long h_sync_width;</div><div class='add'>+	unsigned long pixel_clock_khz;</div><div class='add'>+	unsigned long h_active;</div><div class='add'>+	unsigned long v_active;</div><div class='add'>+	unsigned int bpc; //FIXME: review with Jun</div><div class='add'>+	struct {</div><div class='add'>+		enum dml2_dsc_enable_option enable;</div><div class='add'>+		unsigned int dsc_compressed_bpp_x16;</div><div class='add'>+		struct {</div><div class='add'>+			// for dv to specify num dsc slices to use</div><div class='add'>+			unsigned int num_slices;</div><div class='add'>+		} overrides;</div><div class='add'>+	} dsc;</div><div class='add'>+	bool interlaced;</div><div class='add'>+	struct {</div><div class='add'>+		/* static */</div><div class='add'>+		bool enabled;</div><div class='add'>+		unsigned long min_refresh_uhz;</div><div class='add'>+		unsigned int max_instant_vtotal_delta;</div><div class='add'>+		/* dynamic */</div><div class='add'>+		bool disallowed;</div><div class='add'>+		bool drr_active_variable;</div><div class='add'>+		bool drr_active_fixed;</div><div class='add'>+	} drr_config;</div><div class='add'>+	unsigned long vblank_nom;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_link_output_cfg {</div><div class='add'>+	enum dml2_output_format_class output_format;</div><div class='add'>+	enum dml2_output_encoder_class output_encoder;</div><div class='add'>+	unsigned int output_dp_lane_count;</div><div class='add'>+	enum dml2_output_link_dp_rate output_dp_link_rate;</div><div class='add'>+	unsigned long audio_sample_rate;</div><div class='add'>+	unsigned long audio_sample_layout;</div><div class='add'>+	bool output_disabled; // The stream does not go to a backend for output to a physical</div><div class='add'>+						  //connector (e.g. writeback only, phantom pipe) goes to writeback</div><div class='add'>+	bool validate_output; // Do not validate the link configuration for this display stream.</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_writeback_info {</div><div class='add'>+	enum dml2_source_format_class pixel_format;</div><div class='add'>+	unsigned long input_width;</div><div class='add'>+	unsigned long input_height;</div><div class='add'>+	unsigned long output_width;</div><div class='add'>+	unsigned long output_height;</div><div class='add'>+	unsigned long v_taps;</div><div class='add'>+	unsigned long h_taps;</div><div class='add'>+	unsigned long v_taps_chroma;</div><div class='add'>+	unsigned long h_taps_chroma;</div><div class='add'>+	double h_ratio;</div><div class='add'>+	double v_ratio;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_writeback_cfg {</div><div class='add'>+	unsigned int active_writebacks_per_stream;</div><div class='add'>+	struct dml2_writeback_info writeback_stream[DML2_MAX_WRITEBACK];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_plane_parameters {</div><div class='add'>+	unsigned int stream_index; // Identifies which plane will be composed</div><div class='add'>+</div><div class='add'>+	enum dml2_source_format_class pixel_format;</div><div class='add'>+	/*</div><div class='add'>+	 * The surface and composition structures use</div><div class='add'>+	 * the terms plane0 and plane1.  These planes</div><div class='add'>+	 * are expected to hold the following data based</div><div class='add'>+	 * on the pixel format.</div><div class='add'>+	 *</div><div class='add'>+	 * RGB or YUV Non-Planar Types:</div><div class='add'>+	 *  dml2_444_8</div><div class='add'>+	 *	dml2_444_16</div><div class='add'>+	 *	dml2_444_32</div><div class='add'>+	 *	dml2_444_64</div><div class='add'>+	 *	dml2_rgbe</div><div class='add'>+	 *</div><div class='add'>+	 * plane0 = argb or rgbe</div><div class='add'>+	 * plane1 = not used</div><div class='add'>+	 *</div><div class='add'>+	 * YUV Planar-Types:</div><div class='add'>+	 *	dml2_420_8</div><div class='add'>+	 *	dml2_420_10</div><div class='add'>+	 *	dml2_420_12</div><div class='add'>+	 *</div><div class='add'>+	 * plane0 = luma</div><div class='add'>+	 * plane1 = chroma</div><div class='add'>+	 *</div><div class='add'>+	 * RGB Planar Types:</div><div class='add'>+	 *	dml2_rgbe_alpha</div><div class='add'>+	 *</div><div class='add'>+	 * plane0 = rgbe</div><div class='add'>+	 * plane1 = alpha</div><div class='add'>+	 *</div><div class='add'>+	 * Mono Non-Planar Types:</div><div class='add'>+	 *	dml2_mono_8</div><div class='add'>+	 *	dml2_mono_16</div><div class='add'>+	 *</div><div class='add'>+	 * plane0 = luma</div><div class='add'>+	 * plane1 = not used</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	struct dml2_surface_cfg surface;</div><div class='add'>+	struct dml2_composition_cfg composition;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool enable;</div><div class='add'>+		unsigned long lines_before_active_required;</div><div class='add'>+		unsigned long transmitted_bytes;</div><div class='add'>+	} dynamic_meta_data;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int num_cursors;</div><div class='add'>+		unsigned long cursor_width;</div><div class='add'>+		unsigned long cursor_bpp;</div><div class='add'>+	} cursor;</div><div class='add'>+</div><div class='add'>+	// For TDLUT, SW would assume TDLUT is setup and enable all the time and</div><div class='add'>+	// budget for worst case addressing/width mode</div><div class='add'>+	struct {</div><div class='add'>+		bool setup_for_tdlut;</div><div class='add'>+		enum dml2_tdlut_addressing_mode tdlut_addressing_mode;</div><div class='add'>+		enum dml2_tdlut_width_mode tdlut_width_mode;</div><div class='add'>+		bool tdlut_mpc_width_flag;</div><div class='add'>+	} tdlut;</div><div class='add'>+</div><div class='add'>+	bool immediate_flip;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		// Logical overrides to power management policies (usually)</div><div class='add'>+		enum dml2_uclk_pstate_change_strategy uclk_pstate_change_strategy;</div><div class='add'>+		enum dml2_refresh_from_mall_mode_override refresh_from_mall;</div><div class='add'>+		unsigned int det_size_override_kb;</div><div class='add'>+		unsigned int mpcc_combine_factor;</div><div class='add'>+</div><div class='add'>+		// reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait</div><div class='add'>+		// The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override.</div><div class='add'>+		long reserved_vblank_time_ns;</div><div class='add'>+		unsigned int max_vactive_det_fill_delay_us[dml2_pstate_type_count]; // 0 = no reserved time, +ve = explicit max delay</div><div class='add'>+		unsigned int gpuvm_min_page_size_kbytes;</div><div class='add'>+		unsigned int hostvm_min_page_size_kbytes;</div><div class='add'>+</div><div class='add'>+		enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			// HW specific overrides, there's almost no reason to mess with these</div><div class='add'>+			// generally used for debugging or simulation</div><div class='add'>+			bool force_one_row_for_frame;</div><div class='add'>+			struct {</div><div class='add'>+				bool enable;</div><div class='add'>+				bool value;</div><div class='add'>+			} force_pte_buffer_mode;</div><div class='add'>+			double dppclk_mhz;</div><div class='add'>+		} hw;</div><div class='add'>+	} overrides;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_stream_parameters {</div><div class='add'>+	struct dml2_timing_cfg timing;</div><div class='add'>+	struct dml2_link_output_cfg output;</div><div class='add'>+	struct dml2_writeback_cfg writeback;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		enum dml2_odm_mode odm_mode;</div><div class='add'>+		bool disable_dynamic_odm;</div><div class='add'>+		bool disable_subvp;</div><div class='add'>+		int minimum_vblank_idle_requirement_us;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			struct {</div><div class='add'>+				enum dml2_twait_budgeting_setting uclk_pstate;</div><div class='add'>+				enum dml2_twait_budgeting_setting fclk_pstate;</div><div class='add'>+				enum dml2_twait_budgeting_setting stutter_enter_exit;</div><div class='add'>+			} twait_budgeting;</div><div class='add'>+		} hw;</div><div class='add'>+	} overrides;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_display_cfg {</div><div class='add'>+	bool gpuvm_enable;</div><div class='add'>+	bool ffbm_enable;</div><div class='add'>+	bool hostvm_enable;</div><div class='add'>+</div><div class='add'>+	// Allocate DET proportionally between streams based on pixel rate</div><div class='add'>+	// and then allocate proportionally between planes.</div><div class='add'>+	bool minimize_det_reallocation;</div><div class='add'>+</div><div class='add'>+	unsigned int gpuvm_max_page_table_levels;</div><div class='add'>+	unsigned int hostvm_max_non_cached_page_table_levels;</div><div class='add'>+</div><div class='add'>+	struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];</div><div class='add'>+	struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int num_planes;</div><div class='add'>+	unsigned int num_streams;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct {</div><div class='add'>+			// HW specific overrides, there's almost no reason to mess with these</div><div class='add'>+			// generally used for debugging or simulation</div><div class='add'>+			struct {</div><div class='add'>+				bool enable;</div><div class='add'>+				bool value;</div><div class='add'>+			} force_unbounded_requesting;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				bool enable;</div><div class='add'>+				bool value;</div><div class='add'>+			} force_nom_det_size_kbytes;</div><div class='add'>+</div><div class='add'>+			bool mode_support_check_disable;</div><div class='add'>+			bool mcache_admissibility_check_disable;</div><div class='add'>+			bool surface_viewport_size_check_disable;</div><div class='add'>+			double dlg_ref_clk_mhz;</div><div class='add'>+			double dispclk_mhz;</div><div class='add'>+			double dcfclk_mhz;</div><div class='add'>+			bool optimize_tdlut_scheduling; // TBD: for DV, will set this to 1, to ensure tdlut schedule is calculated based on address/width mode</div><div class='add'>+		} hw;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			bool uclk_pstate_change_disable;</div><div class='add'>+			bool fclk_pstate_change_disable;</div><div class='add'>+			bool g6_temp_read_pstate_disable;</div><div class='add'>+			bool g7_ppt_pstate_disable;</div><div class='add'>+		} power_management;</div><div class='add'>+</div><div class='add'>+		bool enhanced_prefetch_schedule_acceleration;</div><div class='add'>+		bool dcc_programming_assumes_scan_direction_unknown;</div><div class='add'>+		bool synchronize_timings;</div><div class='add'>+		bool synchronize_ddr_displays_for_uclk_pstate_change;</div><div class='add'>+		bool max_outstanding_when_urgent_expected_disable;</div><div class='add'>+		bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming</div><div class='add'>+		bool all_streams_blanked;</div><div class='add'>+	} overrides;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pipe_configuration_descriptor {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int viewport_x_start;</div><div class='add'>+		unsigned int viewport_width;</div><div class='add'>+	} plane0;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int viewport_x_start;</div><div class='add'>+		unsigned int viewport_width;</div><div class='add'>+	} plane1;</div><div class='add'>+</div><div class='add'>+	bool plane1_enabled;</div><div class='add'>+	bool imall_enabled;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_plane_mcache_configuration_descriptor {</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+	const struct dml2_mcache_surface_allocation *mcache_allocation;</div><div class='add'>+</div><div class='add'>+	struct dml2_pipe_configuration_descriptor pipe_configurations[DML2_MAX_DCN_PIPES];</div><div class='add'>+	char num_pipes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h<br/>new file mode 100644<br/>index 000000000000..8f624a912e78<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML_TOP_POLICY_TYPES_H__</div><div class='add'>+#define __DML_TOP_POLICY_TYPES_H__</div><div class='add'>+</div><div class='add'>+struct dml2_policy_parameters {</div><div class='add'>+	unsigned long odm_combine_dispclk_threshold_khz;</div><div class='add'>+	unsigned int max_immediate_flip_latency;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h<br/>new file mode 100644<br/>index 000000000000..1fbc520c2540<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h</a></div><div class='hunk'>@@ -0,0 +1,215 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML_TOP_SOC_PARAMETER_TYPES_H__</div><div class='add'>+#define __DML_TOP_SOC_PARAMETER_TYPES_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+</div><div class='add'>+#define DML_MAX_CLK_TABLE_SIZE 20</div><div class='add'>+</div><div class='add'>+struct dml2_soc_derate_values {</div><div class='add'>+	unsigned int dram_derate_percent_pixel;</div><div class='add'>+	unsigned int dram_derate_percent_vm;</div><div class='add'>+	unsigned int dram_derate_percent_pixel_and_vm;</div><div class='add'>+</div><div class='add'>+	unsigned int fclk_derate_percent;</div><div class='add'>+	unsigned int dcfclk_derate_percent;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_soc_derates {</div><div class='add'>+	struct dml2_soc_derate_values system_active_urgent;</div><div class='add'>+	struct dml2_soc_derate_values system_active_average;</div><div class='add'>+	struct dml2_soc_derate_values dcn_mall_prefetch_urgent;</div><div class='add'>+	struct dml2_soc_derate_values dcn_mall_prefetch_average;</div><div class='add'>+	struct dml2_soc_derate_values system_idle_average;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dcn32x_soc_qos_params {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int base_latency_us;</div><div class='add'>+		unsigned int base_latency_pixel_vm_us;</div><div class='add'>+		unsigned int base_latency_vm_us;</div><div class='add'>+		unsigned int scaling_factor_fclk_us;</div><div class='add'>+		unsigned int scaling_factor_mhz;</div><div class='add'>+	} urgent_latency_us;</div><div class='add'>+</div><div class='add'>+	unsigned int loaded_round_trip_latency_fclk_cycles;</div><div class='add'>+	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;</div><div class='add'>+	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;</div><div class='add'>+	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dcn4_uclk_dpm_dependent_qos_params {</div><div class='add'>+	unsigned long minimum_uclk_khz;</div><div class='add'>+	unsigned int urgent_ramp_uclk_cycles;</div><div class='add'>+	unsigned int trip_to_memory_uclk_cycles;</div><div class='add'>+	unsigned int meta_trip_to_memory_uclk_cycles;</div><div class='add'>+	unsigned int maximum_latency_when_urgent_uclk_cycles;</div><div class='add'>+	unsigned int average_latency_when_urgent_uclk_cycles;</div><div class='add'>+	unsigned int maximum_latency_when_non_urgent_uclk_cycles;</div><div class='add'>+	unsigned int average_latency_when_non_urgent_uclk_cycles;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dcn4x_soc_qos_params {</div><div class='add'>+	unsigned int df_qos_response_time_fclk_cycles;</div><div class='add'>+	unsigned int max_round_trip_to_furthest_cs_fclk_cycles;</div><div class='add'>+	unsigned int mall_overhead_fclk_cycles;</div><div class='add'>+	unsigned int meta_trip_adder_fclk_cycles;</div><div class='add'>+	unsigned int average_transport_distance_fclk_cycles;</div><div class='add'>+	double umc_urgent_ramp_latency_margin;</div><div class='add'>+	double umc_max_latency_margin;</div><div class='add'>+	double umc_average_latency_margin;</div><div class='add'>+	double fabric_max_transport_latency_margin;</div><div class='add'>+	double fabric_average_transport_latency_margin;</div><div class='add'>+	struct dml2_dcn4_uclk_dpm_dependent_qos_params per_uclk_dpm_params[DML_MAX_CLK_TABLE_SIZE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_qos_param_type {</div><div class='add'>+	dml2_qos_param_type_dcn3,</div><div class='add'>+	dml2_qos_param_type_dcn4x</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_soc_qos_parameters {</div><div class='add'>+	struct dml2_soc_derates derate_table;</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int base_latency_us;</div><div class='add'>+		unsigned int scaling_factor_us;</div><div class='add'>+		unsigned int scaling_factor_mhz;</div><div class='add'>+	} writeback;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct dml2_dcn32x_soc_qos_params dcn32x;</div><div class='add'>+		struct dml2_dcn4x_soc_qos_params dcn4x;</div><div class='add'>+	} qos_params;</div><div class='add'>+</div><div class='add'>+	enum dml2_qos_param_type qos_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_soc_power_management_parameters {</div><div class='add'>+	double dram_clk_change_blackout_us;</div><div class='add'>+	double dram_clk_change_read_only_us; // deprecated</div><div class='add'>+	double dram_clk_change_write_only_us; // deprecated</div><div class='add'>+	double fclk_change_blackout_us;</div><div class='add'>+	double g7_ppt_blackout_us;</div><div class='add'>+	double g7_temperature_read_blackout_us;</div><div class='add'>+	double stutter_enter_plus_exit_latency_us;</div><div class='add'>+	double stutter_exit_latency_us;</div><div class='add'>+	double low_power_stutter_enter_plus_exit_latency_us;</div><div class='add'>+	double low_power_stutter_exit_latency_us;</div><div class='add'>+	double z8_stutter_enter_plus_exit_latency_us;</div><div class='add'>+	double z8_stutter_exit_latency_us;</div><div class='add'>+	double z8_min_idle_time;</div><div class='add'>+	double g6_temp_read_blackout_us[DML_MAX_CLK_TABLE_SIZE];</div><div class='add'>+	double type_b_dram_clk_change_blackout_us;</div><div class='add'>+	double type_b_ppt_blackout_us;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_clk_table {</div><div class='add'>+	unsigned long clk_values_khz[DML_MAX_CLK_TABLE_SIZE];</div><div class='add'>+	unsigned char num_clk_values;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dram_params {</div><div class='add'>+	unsigned int channel_width_bytes;</div><div class='add'>+	unsigned int channel_count;</div><div class='add'>+	unsigned int transactions_per_clock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_soc_state_table {</div><div class='add'>+	struct dml2_clk_table uclk;</div><div class='add'>+	struct dml2_clk_table fclk;</div><div class='add'>+	struct dml2_clk_table dcfclk;</div><div class='add'>+	struct dml2_clk_table dispclk;</div><div class='add'>+	struct dml2_clk_table dppclk;</div><div class='add'>+	struct dml2_clk_table dtbclk;</div><div class='add'>+	struct dml2_clk_table phyclk;</div><div class='add'>+	struct dml2_clk_table socclk;</div><div class='add'>+	struct dml2_clk_table dscclk;</div><div class='add'>+	struct dml2_clk_table phyclk_d18;</div><div class='add'>+	struct dml2_clk_table phyclk_d32;</div><div class='add'>+</div><div class='add'>+	struct dml2_dram_params dram_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_soc_vmin_clock_limits {</div><div class='add'>+	unsigned long dispclk_khz;</div><div class='add'>+	unsigned long dcfclk_khz;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_soc_bb {</div><div class='add'>+	struct dml2_soc_state_table clk_table;</div><div class='add'>+	struct dml2_soc_qos_parameters qos_parameters;</div><div class='add'>+	struct dml2_soc_power_management_parameters power_management_parameters;</div><div class='add'>+	struct dml2_soc_vmin_clock_limits vmin_limit;</div><div class='add'>+</div><div class='add'>+	double lower_bound_bandwidth_dchub;</div><div class='add'>+	double fraction_of_urgent_bandwidth_nominal_target;</div><div class='add'>+	double fraction_of_urgent_bandwidth_flip_target;</div><div class='add'>+	unsigned int dprefclk_mhz;</div><div class='add'>+	unsigned int xtalclk_mhz;</div><div class='add'>+	unsigned int pcie_refclk_mhz;</div><div class='add'>+	unsigned int dchub_refclk_mhz;</div><div class='add'>+	unsigned int mall_allocated_for_dcn_mbytes;</div><div class='add'>+	unsigned int max_outstanding_reqs;</div><div class='add'>+	unsigned long fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	unsigned long return_bus_width_bytes;</div><div class='add'>+	unsigned long hostvm_min_page_size_kbytes;</div><div class='add'>+	unsigned long gpuvm_min_page_size_kbytes;</div><div class='add'>+	double phy_downspread_percent;</div><div class='add'>+	double dcn_downspread_percent;</div><div class='add'>+	double dispclk_dppclk_vco_speed_mhz;</div><div class='add'>+	bool no_dfs;</div><div class='add'>+	bool do_urgent_latency_adjustment;</div><div class='add'>+	unsigned int mem_word_bytes;</div><div class='add'>+	unsigned int num_dcc_mcaches;</div><div class='add'>+	unsigned int mcache_size_bytes;</div><div class='add'>+	unsigned int mcache_line_size_bytes;</div><div class='add'>+	unsigned long max_fclk_for_uclk_dpm_khz;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_ip_capabilities {</div><div class='add'>+	unsigned int pipe_count;</div><div class='add'>+	unsigned int otg_count;</div><div class='add'>+	unsigned int TDLUT_33cube_count;</div><div class='add'>+	unsigned int num_dsc;</div><div class='add'>+	unsigned int max_num_dp2p0_streams;</div><div class='add'>+	unsigned int max_num_hdmi_frl_outputs;</div><div class='add'>+	unsigned int max_num_dp2p0_outputs;</div><div class='add'>+	unsigned int max_num_wb;</div><div class='add'>+	unsigned int rob_buffer_size_kbytes;</div><div class='add'>+	unsigned int config_return_buffer_size_in_kbytes;</div><div class='add'>+	unsigned int config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+	unsigned int meta_fifo_size_in_kentries;</div><div class='add'>+	unsigned int compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	unsigned int cursor_buffer_size;</div><div class='add'>+	unsigned int max_flip_time_us;</div><div class='add'>+	unsigned int max_flip_time_lines;</div><div class='add'>+	unsigned int hostvm_mode;</div><div class='add'>+	unsigned int subvp_drr_scheduling_margin_us;</div><div class='add'>+	unsigned int subvp_prefetch_end_to_mall_start_us;</div><div class='add'>+	unsigned int subvp_fw_processing_delay;</div><div class='add'>+	unsigned int max_vactive_det_fill_delay_us;</div><div class='add'>+	unsigned int ppt_max_allow_delay_us;</div><div class='add'>+	unsigned int temp_read_max_allow_delay_us;</div><div class='add'>+	unsigned int dummy_pstate_max_allow_delay_us;</div><div class='add'>+	/* FAMS2 delays */</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int max_allow_delay_us;</div><div class='add'>+		unsigned int scheduling_delay_us;</div><div class='add'>+		unsigned int vertical_interrupt_ack_delay_us; // delay to acknowledge vline int</div><div class='add'>+		unsigned int allow_programming_delay_us; // time requires to program allow</div><div class='add'>+		unsigned int min_allow_width_us;</div><div class='add'>+		unsigned int subvp_df_throttle_delay_us;</div><div class='add'>+		unsigned int subvp_programming_delay_us;</div><div class='add'>+		unsigned int subvp_prefetch_to_mall_delay_us;</div><div class='add'>+		unsigned int drr_programming_delay_us;</div><div class='add'>+</div><div class='add'>+		unsigned int lock_timeout_us;</div><div class='add'>+		unsigned int recovery_timeout_us;</div><div class='add'>+		unsigned int flip_programming_delay_us;</div><div class='add'>+	} fams2;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h<br/>new file mode 100644<br/>index 000000000000..452e4a2e72c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h</a></div><div class='hunk'>@@ -0,0 +1,744 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML_TOP_TYPES_H__</div><div class='add'>+#define __DML_TOP_TYPES_H__</div><div class='add'>+</div><div class='add'>+#include "dml_top_display_cfg_types.h"</div><div class='add'>+#include "dml_top_soc_parameter_types.h"</div><div class='add'>+#include "dml_top_policy_types.h"</div><div class='add'>+#include "dml_top_dchub_registers.h"</div><div class='add'>+</div><div class='add'>+#include "dmub_cmd.h"</div><div class='add'>+</div><div class='add'>+struct dml2_instance;</div><div class='add'>+</div><div class='add'>+enum dml2_project_id {</div><div class='add'>+	dml2_project_invalid = 0,</div><div class='add'>+	dml2_project_dcn4x_stage1,</div><div class='add'>+	dml2_project_dcn4x_stage2,</div><div class='add'>+	dml2_project_dcn4x_stage2_auto_drr_svp,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_pstate_change_support {</div><div class='add'>+	dml2_pstate_change_vactive = 0,</div><div class='add'>+	dml2_pstate_change_vblank = 1,</div><div class='add'>+	dml2_pstate_change_vblank_and_vactive = 2,</div><div class='add'>+	dml2_pstate_change_drr = 3,</div><div class='add'>+	dml2_pstate_change_mall_svp = 4,</div><div class='add'>+	dml2_pstate_change_mall_full_frame = 6,</div><div class='add'>+	dml2_pstate_change_unsupported = 7</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_output_type_and_rate__type {</div><div class='add'>+	dml2_output_type_unknown = 0,</div><div class='add'>+	dml2_output_type_dp = 1,</div><div class='add'>+	dml2_output_type_edp = 2,</div><div class='add'>+	dml2_output_type_dp2p0 = 3,</div><div class='add'>+	dml2_output_type_hdmi = 4,</div><div class='add'>+	dml2_output_type_hdmifrl = 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_output_type_and_rate__rate {</div><div class='add'>+	dml2_output_rate_unknown = 0,</div><div class='add'>+	dml2_output_rate_dp_rate_hbr = 1,</div><div class='add'>+	dml2_output_rate_dp_rate_hbr2 = 2,</div><div class='add'>+	dml2_output_rate_dp_rate_hbr3 = 3,</div><div class='add'>+	dml2_output_rate_dp_rate_uhbr10 = 4,</div><div class='add'>+	dml2_output_rate_dp_rate_uhbr13p5 = 5,</div><div class='add'>+	dml2_output_rate_dp_rate_uhbr20 = 6,</div><div class='add'>+	dml2_output_rate_hdmi_rate_3x3 = 7,</div><div class='add'>+	dml2_output_rate_hdmi_rate_6x3 = 8,</div><div class='add'>+	dml2_output_rate_hdmi_rate_6x4 = 9,</div><div class='add'>+	dml2_output_rate_hdmi_rate_8x4 = 10,</div><div class='add'>+	dml2_output_rate_hdmi_rate_10x4 = 11,</div><div class='add'>+	dml2_output_rate_hdmi_rate_12x4 = 12,</div><div class='add'>+	dml2_output_rate_hdmi_rate_16x4 = 13,</div><div class='add'>+	dml2_output_rate_hdmi_rate_20x4 = 14</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_options {</div><div class='add'>+	bool disable_vblank;</div><div class='add'>+	bool disable_svp;</div><div class='add'>+	bool disable_drr_var;</div><div class='add'>+	bool disable_drr_clamped;</div><div class='add'>+	bool disable_drr_var_when_var_active;</div><div class='add'>+	bool disable_drr_clamped_when_var_active;</div><div class='add'>+	bool disable_fams2;</div><div class='add'>+	bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */</div><div class='add'>+	bool disable_dyn_odm;</div><div class='add'>+	bool disable_dyn_odm_for_multi_stream;</div><div class='add'>+	bool disable_dyn_odm_for_stream_with_svp;</div><div class='add'>+	struct dml2_pmo_pstate_strategy *override_strategy_lists[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int num_override_strategies_per_list[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_options {</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+	struct dml2_pmo_options pmo_options;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_initialize_instance_in_out {</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+	struct dml2_options options;</div><div class='add'>+	struct dml2_soc_bb soc_bb;</div><div class='add'>+	struct dml2_ip_capabilities ip_caps;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		void *explicit_ip_bb;</div><div class='add'>+		unsigned int explicit_ip_bb_size;</div><div class='add'>+	} overrides;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_reset_instance_in_out {</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_check_mode_supported_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+	const struct dml2_display_cfg *display_config;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	bool is_supported;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_mcache_surface_allocation {</div><div class='add'>+	bool valid;</div><div class='add'>+	/*</div><div class='add'>+	* For iMALL, dedicated mall mcaches are required (sharing of last</div><div class='add'>+	* slice possible), for legacy phantom or phantom without return</div><div class='add'>+	* the only mall mcaches need to be valid.</div><div class='add'>+	*/</div><div class='add'>+	bool requires_dedicated_mall_mcache;</div><div class='add'>+</div><div class='add'>+	unsigned int num_mcaches_plane0;</div><div class='add'>+	unsigned int num_mcaches_plane1;</div><div class='add'>+	/*</div><div class='add'>+	* A plane is divided into vertical slices of mcaches,</div><div class='add'>+	* which wrap on the surface width.</div><div class='add'>+	*</div><div class='add'>+	* For example, if the surface width is 7680, and split into</div><div class='add'>+	* three slices of equal width, the boundary array would contain</div><div class='add'>+	* [2560, 5120, 7680]</div><div class='add'>+	*</div><div class='add'>+	* The assignments are</div><div class='add'>+	* 0 = [0 .. 2559]</div><div class='add'>+	* 1 = [2560 .. 5119]</div><div class='add'>+	* 2 = [5120 .. 7679]</div><div class='add'>+	* 0 = [7680 .. INF]</div><div class='add'>+	* The final element implicitly is the same as the first, and</div><div class='add'>+	* at first seems invalid since it is never referenced (since)</div><div class='add'>+	* it is outside the surface. However, its useful when shifting</div><div class='add'>+	* (see below).</div><div class='add'>+	*</div><div class='add'>+	* For any given valid mcache assignment, a shifted version, wrapped</div><div class='add'>+	* on the surface width boundary is also assumed to be valid.</div><div class='add'>+	*</div><div class='add'>+	* For example, shifting [2560, 5120, 7680] by -50 results in</div><div class='add'>+	* [2510, 5170, 7630].</div><div class='add'>+	*</div><div class='add'>+	* The assignments are now:</div><div class='add'>+	* 0 = [0 .. 2509]</div><div class='add'>+	* 1 = [2510 .. 5169]</div><div class='add'>+	* 2 = [5170 .. 7629]</div><div class='add'>+	* 0 = [7630 .. INF]</div><div class='add'>+	*/</div><div class='add'>+	int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];</div><div class='add'>+	int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Shift grainularity is not necessarily 1</div><div class='add'>+	*/</div><div class='add'>+	struct {</div><div class='add'>+		int p0;</div><div class='add'>+		int p1;</div><div class='add'>+	} shift_granularity;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* MCacheIDs have global scope in the SoC, and they are stored here.</div><div class='add'>+	* These IDs are generally not valid until all planes in a display</div><div class='add'>+	* configuration have had their mcache requirements calculated.</div><div class='add'>+	*/</div><div class='add'>+	int global_mcache_ids_plane0[DML2_MAX_MCACHES + 1];</div><div class='add'>+	int global_mcache_ids_plane1[DML2_MAX_MCACHES + 1];</div><div class='add'>+	int global_mcache_ids_mall_plane0[DML2_MAX_MCACHES + 1];</div><div class='add'>+	int global_mcache_ids_mall_plane1[DML2_MAX_MCACHES + 1];</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Generally, plane0/1 slices must use a disjoint set of caches</div><div class='add'>+	* but in some cases the final segement of the two planes can</div><div class='add'>+	* use the same cache. If plane0_plane1 is set, then this is</div><div class='add'>+	* allowed.</div><div class='add'>+	*</div><div class='add'>+	* Similarly, the caches allocated to MALL prefetcher are generally</div><div class='add'>+	* disjoint, but if mall_prefetch is set, then the final segment</div><div class='add'>+	* between the main and the mall pixel requestor can use the same</div><div class='add'>+	* cache.</div><div class='add'>+	*</div><div class='add'>+	* Note that both bits may be set at the same time.</div><div class='add'>+	*/</div><div class='add'>+	struct {</div><div class='add'>+		bool mall_comb_mcache_p0;</div><div class='add'>+		bool mall_comb_mcache_p1;</div><div class='add'>+		bool plane0_plane1;</div><div class='add'>+	} last_slice_sharing;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		int meta_row_bytes_plane0;</div><div class='add'>+		int meta_row_bytes_plane1;</div><div class='add'>+	} informative;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_pstate_method {</div><div class='add'>+	dml2_pstate_method_na = 0,</div><div class='add'>+	/* hw exclusive modes */</div><div class='add'>+	dml2_pstate_method_vactive = 1,</div><div class='add'>+	dml2_pstate_method_vblank = 2,</div><div class='add'>+	dml2_pstate_method_reserved_hw = 5,</div><div class='add'>+	/* fw assisted exclusive modes */</div><div class='add'>+	dml2_pstate_method_fw_svp = 6,</div><div class='add'>+	dml2_pstate_method_reserved_fw = 10,</div><div class='add'>+	/* fw assisted modes requiring drr modulation */</div><div class='add'>+	dml2_pstate_method_fw_vactive_drr = 11,</div><div class='add'>+	dml2_pstate_method_fw_vblank_drr = 12,</div><div class='add'>+	dml2_pstate_method_fw_svp_drr = 13,</div><div class='add'>+	dml2_pstate_method_reserved_fw_drr_clamped = 20,</div><div class='add'>+	dml2_pstate_method_fw_drr = 21,</div><div class='add'>+	dml2_pstate_method_reserved_fw_drr_var = 22,</div><div class='add'>+	dml2_pstate_method_count</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_per_plane_programming {</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long dppclk_khz;</div><div class='add'>+		} dcn4x;</div><div class='add'>+	} min_clocks;</div><div class='add'>+</div><div class='add'>+	struct dml2_mcache_surface_allocation mcache_allocation;</div><div class='add'>+</div><div class='add'>+	// If a stream is using automatic or forced odm combine</div><div class='add'>+	// and the stream for this plane has num_odms_required &gt; 1</div><div class='add'>+	// num_dpps_required is always equal to num_odms_required for</div><div class='add'>+	// ALL planes of the stream</div><div class='add'>+</div><div class='add'>+	// If a stream is using odm split, then this value is always 1</div><div class='add'>+	unsigned int num_dpps_required;</div><div class='add'>+</div><div class='add'>+	enum dml2_pstate_method uclk_pstate_support_method;</div><div class='add'>+</div><div class='add'>+	// MALL size requirements for MALL SS and SubVP</div><div class='add'>+	unsigned int surface_size_mall_bytes;</div><div class='add'>+	unsigned int svp_size_mall_bytes;</div><div class='add'>+</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool valid;</div><div class='add'>+		struct dml2_plane_parameters descriptor;</div><div class='add'>+		struct dml2_mcache_surface_allocation mcache_allocation;</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];</div><div class='add'>+	} phantom_plane;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union dml2_global_sync_programming {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int vstartup_lines;</div><div class='add'>+		unsigned int vupdate_offset_pixels;</div><div class='add'>+		unsigned int vupdate_vupdate_width_pixels;</div><div class='add'>+		unsigned int vready_offset_pixels;</div><div class='add'>+		unsigned int pstate_keepout_start_lines;</div><div class='add'>+	} dcn4x;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_per_stream_programming {</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long dscclk_khz;</div><div class='add'>+			unsigned long dtbclk_khz;</div><div class='add'>+			unsigned long phyclk_khz;</div><div class='add'>+		} dcn4x;</div><div class='add'>+	} min_clocks;</div><div class='add'>+</div><div class='add'>+	union dml2_global_sync_programming global_sync;</div><div class='add'>+</div><div class='add'>+	unsigned int num_odms_required;</div><div class='add'>+</div><div class='add'>+	enum dml2_pstate_method uclk_pstate_method;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool enabled;</div><div class='add'>+		struct dml2_stream_parameters descriptor;</div><div class='add'>+		union dml2_global_sync_programming global_sync;</div><div class='add'>+	} phantom_stream;</div><div class='add'>+</div><div class='add'>+	union dmub_cmd_fams2_config fams2_base_params;</div><div class='add'>+	union {</div><div class='add'>+		union dmub_cmd_fams2_config fams2_sub_params;</div><div class='add'>+		union dmub_fams2_stream_static_sub_state_v2 fams2_sub_params_v2;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//-----------------</div><div class='add'>+// Mode Support Information</div><div class='add'>+//-----------------</div><div class='add'>+</div><div class='add'>+struct dml2_mode_support_info {</div><div class='add'>+	bool ModeIsSupported; //&lt;brief Is the mode support any voltage and combine setting</div><div class='add'>+	bool ImmediateFlipSupport; //&lt;brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming</div><div class='add'>+	// Mode Support Reason</div><div class='add'>+	bool WritebackLatencySupport;</div><div class='add'>+	bool ScaleRatioAndTapsSupport;</div><div class='add'>+	bool SourceFormatPixelAndScanSupport;</div><div class='add'>+	bool P2IWith420;</div><div class='add'>+	bool DSCOnlyIfNecessaryWithBPP;</div><div class='add'>+	bool DSC422NativeNotSupported;</div><div class='add'>+	bool LinkRateDoesNotMatchDPVersion;</div><div class='add'>+	bool LinkRateForMultistreamNotIndicated;</div><div class='add'>+	bool BPPForMultistreamNotIndicated;</div><div class='add'>+	bool MultistreamWithHDMIOreDP;</div><div class='add'>+	bool MSOOrODMSplitWithNonDPLink;</div><div class='add'>+	bool NotEnoughLanesForMSO;</div><div class='add'>+	bool NumberOfOTGSupport;</div><div class='add'>+	bool NumberOfHDMIFRLSupport;</div><div class='add'>+	bool NumberOfDP2p0Support;</div><div class='add'>+	bool NumberOfTDLUT33cubeSupport;</div><div class='add'>+	bool WritebackScaleRatioAndTapsSupport;</div><div class='add'>+	bool CursorSupport;</div><div class='add'>+	bool PitchSupport;</div><div class='add'>+	bool ViewportExceedsSurface;</div><div class='add'>+	bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;</div><div class='add'>+	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;</div><div class='add'>+	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;</div><div class='add'>+	bool InvalidCombinationOfMALLUseForPState;</div><div class='add'>+	bool ExceededMALLSize;</div><div class='add'>+	bool EnoughWritebackUnits;</div><div class='add'>+	bool ExceededMultistreamSlots;</div><div class='add'>+	bool NotEnoughDSCUnits;</div><div class='add'>+	bool NotEnoughDSCSlices;</div><div class='add'>+	bool PixelsPerLinePerDSCUnitSupport;</div><div class='add'>+	bool DSCCLKRequiredMoreThanSupported;</div><div class='add'>+	bool DTBCLKRequiredMoreThanSupported;</div><div class='add'>+	bool LinkCapacitySupport;</div><div class='add'>+	bool ROBSupport;</div><div class='add'>+	bool OutstandingRequestsSupport;</div><div class='add'>+	bool OutstandingRequestsUrgencyAvoidance;</div><div class='add'>+	bool PTEBufferSizeNotExceeded;</div><div class='add'>+	bool DCCMetaBufferSizeNotExceeded;</div><div class='add'>+	bool TotalVerticalActiveBandwidthSupport;</div><div class='add'>+	bool VActiveBandwidthSupport;</div><div class='add'>+	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];</div><div class='add'>+	bool USRRetrainingSupport;</div><div class='add'>+	bool PrefetchSupported;</div><div class='add'>+	bool DynamicMetadataSupported;</div><div class='add'>+	bool VRatioInPrefetchSupported;</div><div class='add'>+	bool DISPCLK_DPPCLK_Support;</div><div class='add'>+	bool TotalAvailablePipesSupport;</div><div class='add'>+	bool ViewportSizeSupport;</div><div class='add'>+	bool ImmediateFlipSupportedForState;</div><div class='add'>+	double MaxTotalVerticalActiveAvailableBandwidth;</div><div class='add'>+	bool MPCCombineEnable[DML2_MAX_PLANES]; /// &lt;brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting</div><div class='add'>+	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// &lt;brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage</div><div class='add'>+	unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// &lt;brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.</div><div class='add'>+	bool DSCEnabled[DML2_MAX_PLANES]; /// &lt;brief Indicate if the DSC is actually required; used in mode_programming</div><div class='add'>+	bool FECEnabled[DML2_MAX_PLANES]; /// &lt;brief Indicate if the FEC is actually required</div><div class='add'>+	unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// &lt;brief Indicate how many slices needed to support the given mode</div><div class='add'>+	double OutputBpp[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_output_type_and_rate__type OutputType[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_output_type_and_rate__rate OutputRate[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int AlignedYPitch[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int AlignedCPitch[DML2_MAX_PLANES];</div><div class='add'>+	bool g6_temp_read_support;</div><div class='add'>+	bool temp_read_or_ppt_support;</div><div class='add'>+	bool qos_bandwidth_support;</div><div class='add'>+	bool dcfclk_support;</div><div class='add'>+}; // dml2_mode_support_info</div><div class='add'>+</div><div class='add'>+struct dml2_display_cfg_programming {</div><div class='add'>+	struct dml2_display_cfg display_config;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long dcfclk_khz;</div><div class='add'>+			unsigned long fclk_khz;</div><div class='add'>+			unsigned long uclk_khz;</div><div class='add'>+			unsigned long socclk_khz;</div><div class='add'>+			unsigned long dispclk_khz;</div><div class='add'>+			unsigned long dcfclk_deepsleep_khz;</div><div class='add'>+			unsigned long dpp_ref_khz;</div><div class='add'>+		} dcn32x;</div><div class='add'>+		struct {</div><div class='add'>+			struct {</div><div class='add'>+				unsigned long uclk_khz;</div><div class='add'>+				unsigned long fclk_khz;</div><div class='add'>+				unsigned long dcfclk_khz;</div><div class='add'>+			} active;</div><div class='add'>+			struct {</div><div class='add'>+				unsigned long uclk_khz;</div><div class='add'>+				unsigned long fclk_khz;</div><div class='add'>+				unsigned long dcfclk_khz;</div><div class='add'>+			} idle;</div><div class='add'>+			struct {</div><div class='add'>+				unsigned long uclk_khz;</div><div class='add'>+				unsigned long fclk_khz;</div><div class='add'>+				unsigned long dcfclk_khz;</div><div class='add'>+			} svp_prefetch;</div><div class='add'>+			struct {</div><div class='add'>+				unsigned long uclk_khz;</div><div class='add'>+				unsigned long fclk_khz;</div><div class='add'>+				unsigned long dcfclk_khz;</div><div class='add'>+			} svp_prefetch_no_throttle;</div><div class='add'>+</div><div class='add'>+			unsigned long deepsleep_dcfclk_khz;</div><div class='add'>+			unsigned long dispclk_khz;</div><div class='add'>+			unsigned long dpprefclk_khz;</div><div class='add'>+			unsigned long dtbrefclk_khz;</div><div class='add'>+			unsigned long socclk_khz;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				uint32_t dispclk_did;</div><div class='add'>+				uint32_t dpprefclk_did;</div><div class='add'>+				uint32_t dtbrefclk_did;</div><div class='add'>+			} divider_ids;</div><div class='add'>+		} dcn4x;</div><div class='add'>+	} min_clocks;</div><div class='add'>+</div><div class='add'>+	bool uclk_pstate_supported;</div><div class='add'>+	bool fclk_pstate_supported;</div><div class='add'>+</div><div class='add'>+	/* indicates this configuration requires FW to support */</div><div class='add'>+	bool fams2_required;</div><div class='add'>+	struct dmub_cmd_fams2_global_config fams2_global_config;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition</div><div class='add'>+		uint8_t base_percent_efficiency; //LP1</div><div class='add'>+		uint8_t low_power_percent_efficiency; //LP2</div><div class='add'>+	} stutter;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		bool meets_eco; // Stutter cycles will meet Z8 ECO criteria</div><div class='add'>+		bool supported_in_blank; // Changing to configurations where this is false requires Z8 to be disabled during the transition</div><div class='add'>+	} z8_stutter;</div><div class='add'>+</div><div class='add'>+	struct dml2_dchub_global_register_set global_regs;</div><div class='add'>+</div><div class='add'>+	struct dml2_per_plane_programming plane_programming[DML2_MAX_PLANES];</div><div class='add'>+	struct dml2_per_stream_programming stream_programming[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Don't access this structure directly, access it through plane_programming.pipe_regs</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set pipe_regs[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct {</div><div class='add'>+			double urgent_us;</div><div class='add'>+			double writeback_urgent_us;</div><div class='add'>+			double writeback_pstate_us;</div><div class='add'>+			double writeback_fclk_pstate_us;</div><div class='add'>+			double cstate_exit_us;</div><div class='add'>+			double cstate_enter_plus_exit_us;</div><div class='add'>+			double z8_cstate_exit_us;</div><div class='add'>+			double z8_cstate_enter_plus_exit_us;</div><div class='add'>+			double pstate_change_us;</div><div class='add'>+			double fclk_pstate_change_us;</div><div class='add'>+			double usr_retraining_us;</div><div class='add'>+			double temp_read_or_ppt_watermark_us;</div><div class='add'>+		} watermarks;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned int swath_width_plane0;</div><div class='add'>+			unsigned int swath_height_plane0;</div><div class='add'>+			unsigned int swath_height_plane1;</div><div class='add'>+			unsigned int dpte_row_height_plane0;</div><div class='add'>+			unsigned int dpte_row_height_plane1;</div><div class='add'>+			unsigned int meta_row_height_plane0;</div><div class='add'>+			unsigned int meta_row_height_plane1;</div><div class='add'>+		} plane_info[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned int total_num_dpps_required;</div><div class='add'>+		} dpp;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long long total_surface_size_in_mall_bytes;</div><div class='add'>+			unsigned int subviewport_lines_needed_in_mall[DML2_MAX_PLANES];</div><div class='add'>+		} mall;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			double urgent_latency_us; // urgent ramp latency</div><div class='add'>+			double max_non_urgent_latency_us;</div><div class='add'>+			double max_urgent_latency_us;</div><div class='add'>+			double avg_non_urgent_latency_us;</div><div class='add'>+			double avg_urgent_latency_us;</div><div class='add'>+			double wm_memory_trip_us;</div><div class='add'>+			double meta_trip_memory_us;</div><div class='add'>+			double fraction_of_urgent_bandwidth; // nom</div><div class='add'>+			double fraction_of_urgent_bandwidth_immediate_flip;</div><div class='add'>+			double fraction_of_urgent_bandwidth_mall;</div><div class='add'>+			double max_active_fclk_change_latency_supported;</div><div class='add'>+			unsigned int min_return_latency_in_dcfclk;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+					double dram_vm_only_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+					double dram_vm_only_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+			} urg_bw_available;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+			} avg_bw_available;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+			} non_urg_bw_required;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+			} non_urg_bw_required_with_flip;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+</div><div class='add'>+			} urg_bw_required;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+			} urg_bw_required_with_flip;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} svp_prefetch;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double sdp_bw_mbps;</div><div class='add'>+					double dram_bw_mbps;</div><div class='add'>+				} sys_active;</div><div class='add'>+			} avg_bw_required;</div><div class='add'>+		} qos;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long long det_size_in_kbytes[DML2_MAX_PLANES];</div><div class='add'>+			unsigned long long DETBufferSizeY[DML2_MAX_PLANES];</div><div class='add'>+			unsigned long long comp_buffer_size_kbytes;</div><div class='add'>+			bool UnboundedRequestEnabled;</div><div class='add'>+			unsigned int compbuf_reserved_space_64b;</div><div class='add'>+		} crb;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned int max_uncompressed_block_plane0;</div><div class='add'>+			unsigned int max_compressed_block_plane0;</div><div class='add'>+			unsigned int independent_block_plane0;</div><div class='add'>+			unsigned int max_uncompressed_block_plane1;</div><div class='add'>+			unsigned int max_compressed_block_plane1;</div><div class='add'>+			unsigned int independent_block_plane1;</div><div class='add'>+		} dcc_control[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			double stutter_efficiency;</div><div class='add'>+			double stutter_efficiency_with_vblank;</div><div class='add'>+			double stutter_num_bursts;</div><div class='add'>+</div><div class='add'>+			struct {</div><div class='add'>+				double stutter_efficiency;</div><div class='add'>+				double stutter_efficiency_with_vblank;</div><div class='add'>+				double stutter_num_bursts;</div><div class='add'>+				double stutter_period;</div><div class='add'>+</div><div class='add'>+				struct {</div><div class='add'>+					double stutter_efficiency;</div><div class='add'>+					double stutter_num_bursts;</div><div class='add'>+					double stutter_period;</div><div class='add'>+				} bestcase;</div><div class='add'>+			} z8;</div><div class='add'>+		} power_management;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			double min_ttu_vblank_us[DML2_MAX_PLANES];</div><div class='add'>+			bool vready_at_or_after_vsync[DML2_MAX_PLANES];</div><div class='add'>+			double min_dst_y_next_start[DML2_MAX_PLANES];</div><div class='add'>+			bool cstate_max_cap_mode;</div><div class='add'>+			bool hw_debug5;</div><div class='add'>+			unsigned int dcfclk_deep_sleep_hysteresis;</div><div class='add'>+			unsigned int dst_x_after_scaler[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int dst_y_after_scaler[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int prefetch_source_lines_plane0[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int prefetch_source_lines_plane1[DML2_MAX_PLANES];</div><div class='add'>+			bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];</div><div class='add'>+			bool UsesMALLForStaticScreen[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int CursorDstXOffset[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int CursorDstYOffset[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int dpte_group_bytes[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int vm_group_bytes[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+			double TimePerVMGroupVBlank[DML2_MAX_PLANES];</div><div class='add'>+			double TimePerVMGroupFlip[DML2_MAX_PLANES];</div><div class='add'>+			double TimePerVMRequestVBlank[DML2_MAX_PLANES];</div><div class='add'>+			double TimePerVMRequestFlip[DML2_MAX_PLANES];</div><div class='add'>+			double Tdmdl_vm[DML2_MAX_PLANES];</div><div class='add'>+			double Tdmdl[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int VStartup[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int VUpdateWidthPix[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int VReadyOffsetPix[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+			double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES];</div><div class='add'>+			double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES];</div><div class='add'>+			double time_per_pte_group_nom_luma[DML2_MAX_PLANES];</div><div class='add'>+			double time_per_pte_group_nom_chroma[DML2_MAX_PLANES];</div><div class='add'>+			double time_per_pte_group_vblank_luma[DML2_MAX_PLANES];</div><div class='add'>+			double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES];</div><div class='add'>+			double time_per_pte_group_flip_luma[DML2_MAX_PLANES];</div><div class='add'>+			double time_per_pte_group_flip_chroma[DML2_MAX_PLANES];</div><div class='add'>+			double VRatioPrefetchY[DML2_MAX_PLANES];</div><div class='add'>+			double VRatioPrefetchC[DML2_MAX_PLANES];</div><div class='add'>+			double DestinationLinesForPrefetch[DML2_MAX_PLANES];</div><div class='add'>+			double DestinationLinesToRequestVMInVBlank[DML2_MAX_PLANES];</div><div class='add'>+			double DestinationLinesToRequestRowInVBlank[DML2_MAX_PLANES];</div><div class='add'>+			double DestinationLinesToRequestVMInImmediateFlip[DML2_MAX_PLANES];</div><div class='add'>+			double DestinationLinesToRequestRowInImmediateFlip[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+			double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+			double WritebackRequiredBandwidth;</div><div class='add'>+			double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];</div><div class='add'>+			double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];</div><div class='add'>+			double DSCCLK_calculated[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];</div><div class='add'>+			bool PTE_BUFFER_MODE[DML2_MAX_PLANES];</div><div class='add'>+			double DSCDelay[DML2_MAX_PLANES];</div><div class='add'>+			double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY</div><div class='add'>+			bool ROBUrgencyAvoidance;</div><div class='add'>+			double LowestPrefetchMargin;</div><div class='add'>+</div><div class='add'>+			unsigned int pstate_recout_reduction_lines[DML2_MAX_PLANES];</div><div class='add'>+		} misc;</div><div class='add'>+</div><div class='add'>+		struct dml2_mode_support_info mode_support_info;</div><div class='add'>+		unsigned int voltage_level; // LEGACY_ONLY</div><div class='add'>+</div><div class='add'>+		// For DV only</div><div class='add'>+		// This is what dml core calculated, only on the full_vp width and assume we have</div><div class='add'>+		// unlimited # of mcache</div><div class='add'>+		struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+		bool failed_prefetch;</div><div class='add'>+		bool failed_uclk_pstate;</div><div class='add'>+		bool failed_mcache_validation;</div><div class='add'>+		bool failed_dpmm;</div><div class='add'>+		bool failed_mode_programming;</div><div class='add'>+		bool failed_mode_programming_dcfclk;</div><div class='add'>+		bool failed_mode_programming_prefetch;</div><div class='add'>+		bool failed_mode_programming_flip;</div><div class='add'>+		bool failed_map_watermarks;</div><div class='add'>+	} informative;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_build_mode_programming_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+	const struct dml2_display_cfg *display_config;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_cfg_programming *programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_build_mcache_programming_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+</div><div class='add'>+	struct dml2_plane_mcache_configuration_descriptor mcache_configurations[DML2_MAX_PLANES];</div><div class='add'>+	char num_configurations;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	// per_plane_pipe_mcache_regs[i][j] refers to the proper programming for the j-th pipe of the</div><div class='add'>+	// i-th plane (from mcache_configurations)</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];</div><div class='add'>+</div><div class='add'>+	// It's not a good idea to reference this directly, better to use the pointer structure above instead</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_unit_test_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c<br/>new file mode 100644<br/>index 000000000000..eba948e187c1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c</a></div><div class='hunk'>@@ -0,0 +1,661 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml2_core_shared_types.h"</div><div class='add'>+#include "dml2_core_dcn4.h"</div><div class='add'>+#include "dml2_core_dcn4_calcs.h"</div><div class='add'>+#include "dml2_debug.h"</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+</div><div class='add'>+struct dml2_core_ip_params core_dcn4_ip_caps_base = {</div><div class='add'>+	// Hardcoded values for DCN3x</div><div class='add'>+	.vblank_nom_default_us = 668,</div><div class='add'>+	.remote_iommu_outstanding_translations = 256,</div><div class='add'>+	.rob_buffer_size_kbytes = 128,</div><div class='add'>+	.config_return_buffer_size_in_kbytes = 1280,</div><div class='add'>+	.config_return_buffer_segment_size_in_kbytes = 64,</div><div class='add'>+	.compressed_buffer_segment_size_in_kbytes = 64,</div><div class='add'>+	.dpte_buffer_size_in_pte_reqs_luma = 68,</div><div class='add'>+	.dpte_buffer_size_in_pte_reqs_chroma = 36,</div><div class='add'>+	.pixel_chunk_size_kbytes = 8,</div><div class='add'>+	.alpha_pixel_chunk_size_kbytes = 4,</div><div class='add'>+	.min_pixel_chunk_size_bytes = 1024,</div><div class='add'>+	.writeback_chunk_size_kbytes = 8,</div><div class='add'>+	.line_buffer_size_bits = 1171920,</div><div class='add'>+	.max_line_buffer_lines = 32,</div><div class='add'>+	.writeback_interface_buffer_size_kbytes = 90,</div><div class='add'>+	//Number of pipes after DCN Pipe harvesting</div><div class='add'>+	.max_num_dpp = 4,</div><div class='add'>+	.max_num_opp = 4,</div><div class='add'>+	.max_num_otg = 4,</div><div class='add'>+	.max_num_wb = 1,</div><div class='add'>+	.max_dchub_pscl_bw_pix_per_clk = 4,</div><div class='add'>+	.max_pscl_lb_bw_pix_per_clk = 2,</div><div class='add'>+	.max_lb_vscl_bw_pix_per_clk = 4,</div><div class='add'>+	.max_vscl_hscl_bw_pix_per_clk = 4,</div><div class='add'>+	.max_hscl_ratio = 6,</div><div class='add'>+	.max_vscl_ratio = 6,</div><div class='add'>+	.max_hscl_taps = 8,</div><div class='add'>+	.max_vscl_taps = 8,</div><div class='add'>+	.dispclk_ramp_margin_percent = 1,</div><div class='add'>+	.dppclk_delay_subtotal = 47,</div><div class='add'>+	.dppclk_delay_scl = 50,</div><div class='add'>+	.dppclk_delay_scl_lb_only = 16,</div><div class='add'>+	.dppclk_delay_cnvc_formatter = 28,</div><div class='add'>+	.dppclk_delay_cnvc_cursor = 6,</div><div class='add'>+	.cursor_buffer_size = 24,</div><div class='add'>+	.cursor_chunk_size = 2,</div><div class='add'>+	.dispclk_delay_subtotal = 125,</div><div class='add'>+	.max_inter_dcn_tile_repeaters = 8,</div><div class='add'>+	.writeback_max_hscl_ratio = 1,</div><div class='add'>+	.writeback_max_vscl_ratio = 1,</div><div class='add'>+	.writeback_min_hscl_ratio = 1,</div><div class='add'>+	.writeback_min_vscl_ratio = 1,</div><div class='add'>+	.writeback_max_hscl_taps = 1,</div><div class='add'>+	.writeback_max_vscl_taps = 1,</div><div class='add'>+	.writeback_line_buffer_buffer_size = 0,</div><div class='add'>+	.num_dsc = 4,</div><div class='add'>+	.maximum_dsc_bits_per_component = 12,</div><div class='add'>+	.maximum_pixels_per_line_per_dsc_unit = 5760,</div><div class='add'>+	.dsc422_native_support = true,</div><div class='add'>+	.dcc_supported = true,</div><div class='add'>+	.ptoi_supported = false,</div><div class='add'>+</div><div class='add'>+	.cursor_64bpp_support = true,</div><div class='add'>+	.dynamic_metadata_vm_enabled = false,</div><div class='add'>+</div><div class='add'>+	.max_num_dp2p0_outputs = 4,</div><div class='add'>+	.max_num_dp2p0_streams = 4,</div><div class='add'>+	.imall_supported = 1,</div><div class='add'>+	.max_flip_time_us = 80,</div><div class='add'>+	.max_flip_time_lines = 32,</div><div class='add'>+	.words_per_channel = 16,</div><div class='add'>+</div><div class='add'>+	.subvp_fw_processing_delay_us = 15,</div><div class='add'>+	.subvp_pstate_allow_width_us = 20,</div><div class='add'>+	.subvp_swath_height_margin_lines = 16,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *ip_caps, const struct dml2_core_ip_params *ip_params)</div><div class='add'>+{</div><div class='add'>+	ip_caps-&gt;pipe_count = ip_params-&gt;max_num_dpp;</div><div class='add'>+	ip_caps-&gt;otg_count = ip_params-&gt;max_num_otg;</div><div class='add'>+	ip_caps-&gt;num_dsc = ip_params-&gt;num_dsc;</div><div class='add'>+	ip_caps-&gt;max_num_dp2p0_streams = ip_params-&gt;max_num_dp2p0_streams;</div><div class='add'>+	ip_caps-&gt;max_num_dp2p0_outputs = ip_params-&gt;max_num_dp2p0_outputs;</div><div class='add'>+	ip_caps-&gt;max_num_hdmi_frl_outputs = ip_params-&gt;max_num_hdmi_frl_outputs;</div><div class='add'>+	ip_caps-&gt;rob_buffer_size_kbytes = ip_params-&gt;rob_buffer_size_kbytes;</div><div class='add'>+	ip_caps-&gt;config_return_buffer_size_in_kbytes = ip_params-&gt;config_return_buffer_size_in_kbytes;</div><div class='add'>+	ip_caps-&gt;config_return_buffer_segment_size_in_kbytes = ip_params-&gt;config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+	ip_caps-&gt;meta_fifo_size_in_kentries = ip_params-&gt;meta_fifo_size_in_kentries;</div><div class='add'>+	ip_caps-&gt;compressed_buffer_segment_size_in_kbytes = ip_params-&gt;compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	ip_caps-&gt;cursor_buffer_size = ip_params-&gt;cursor_buffer_size;</div><div class='add'>+	ip_caps-&gt;max_flip_time_us = ip_params-&gt;max_flip_time_us;</div><div class='add'>+	ip_caps-&gt;max_flip_time_lines = ip_params-&gt;max_flip_time_lines;</div><div class='add'>+	ip_caps-&gt;hostvm_mode = ip_params-&gt;hostvm_mode;</div><div class='add'>+</div><div class='add'>+	// FIXME_STAGE2: cleanup after adding all dv override to ip_caps</div><div class='add'>+	ip_caps-&gt;subvp_drr_scheduling_margin_us = 100;</div><div class='add'>+	ip_caps-&gt;subvp_prefetch_end_to_mall_start_us = 15;</div><div class='add'>+	ip_caps-&gt;subvp_fw_processing_delay = 16;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void patch_ip_params_with_ip_caps(struct dml2_core_ip_params *ip_params, const struct dml2_ip_capabilities *ip_caps)</div><div class='add'>+{</div><div class='add'>+	ip_params-&gt;max_num_dpp = ip_caps-&gt;pipe_count;</div><div class='add'>+	ip_params-&gt;max_num_otg = ip_caps-&gt;otg_count;</div><div class='add'>+	ip_params-&gt;num_dsc = ip_caps-&gt;num_dsc;</div><div class='add'>+	ip_params-&gt;max_num_dp2p0_streams = ip_caps-&gt;max_num_dp2p0_streams;</div><div class='add'>+	ip_params-&gt;max_num_dp2p0_outputs = ip_caps-&gt;max_num_dp2p0_outputs;</div><div class='add'>+	ip_params-&gt;max_num_hdmi_frl_outputs = ip_caps-&gt;max_num_hdmi_frl_outputs;</div><div class='add'>+	ip_params-&gt;rob_buffer_size_kbytes = ip_caps-&gt;rob_buffer_size_kbytes;</div><div class='add'>+	ip_params-&gt;config_return_buffer_size_in_kbytes = ip_caps-&gt;config_return_buffer_size_in_kbytes;</div><div class='add'>+	ip_params-&gt;config_return_buffer_segment_size_in_kbytes = ip_caps-&gt;config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+	ip_params-&gt;meta_fifo_size_in_kentries = ip_caps-&gt;meta_fifo_size_in_kentries;</div><div class='add'>+	ip_params-&gt;compressed_buffer_segment_size_in_kbytes = ip_caps-&gt;compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	ip_params-&gt;cursor_buffer_size = ip_caps-&gt;cursor_buffer_size;</div><div class='add'>+	ip_params-&gt;max_flip_time_us = ip_caps-&gt;max_flip_time_us;</div><div class='add'>+	ip_params-&gt;max_flip_time_lines = ip_caps-&gt;max_flip_time_lines;</div><div class='add'>+	ip_params-&gt;hostvm_mode = ip_caps-&gt;hostvm_mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_instance *core = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	if (!in_out-&gt;minimum_clock_table)</div><div class='add'>+		return false;</div><div class='add'>+	else</div><div class='add'>+		core-&gt;minimum_clock_table = in_out-&gt;minimum_clock_table;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;explicit_ip_bb &amp;&amp; in_out-&gt;explicit_ip_bb_size &gt; 0) {</div><div class='add'>+		memcpy(&amp;core-&gt;clean_me_up.mode_lib.ip, in_out-&gt;explicit_ip_bb, in_out-&gt;explicit_ip_bb_size);</div><div class='add'>+</div><div class='add'>+		// FIXME_STAGE2:</div><div class='add'>+		// DV still uses stage1 ip_param_st for each variant, need to patch the ip_caps with ip_param info</div><div class='add'>+		// Should move DV to use ip_caps but need move more overrides to ip_caps</div><div class='add'>+		patch_ip_caps_with_explicit_ip_params(in_out-&gt;ip_caps, in_out-&gt;explicit_ip_bb);</div><div class='add'>+		core-&gt;clean_me_up.mode_lib.ip.subvp_pstate_allow_width_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;</div><div class='add'>+		core-&gt;clean_me_up.mode_lib.ip.subvp_fw_processing_delay_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us;</div><div class='add'>+		core-&gt;clean_me_up.mode_lib.ip.subvp_swath_height_margin_lines = core_dcn4_ip_caps_base.subvp_swath_height_margin_lines;</div><div class='add'>+	} else {</div><div class='add'>+		memcpy(&amp;core-&gt;clean_me_up.mode_lib.ip, &amp;core_dcn4_ip_caps_base, sizeof(struct dml2_core_ip_params));</div><div class='add'>+		patch_ip_params_with_ip_caps(&amp;core-&gt;clean_me_up.mode_lib.ip, in_out-&gt;ip_caps);</div><div class='add'>+		core-&gt;clean_me_up.mode_lib.ip.imall_supported = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;core-&gt;clean_me_up.mode_lib.soc, in_out-&gt;soc_bb, sizeof(struct dml2_soc_bb));</div><div class='add'>+	memcpy(&amp;core-&gt;clean_me_up.mode_lib.ip_caps, in_out-&gt;ip_caps, sizeof(struct dml2_ip_capabilities));</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main,</div><div class='add'>+	const struct dml2_implicit_svp_meta *meta)</div><div class='add'>+{</div><div class='add'>+	memcpy(phantom, main, sizeof(struct dml2_stream_parameters));</div><div class='add'>+</div><div class='add'>+	phantom-&gt;timing.v_total = meta-&gt;v_total;</div><div class='add'>+	phantom-&gt;timing.v_active = meta-&gt;v_active;</div><div class='add'>+	phantom-&gt;timing.v_front_porch = meta-&gt;v_front_porch;</div><div class='add'>+	phantom-&gt;timing.v_blank_end = phantom-&gt;timing.v_total - phantom-&gt;timing.v_front_porch - phantom-&gt;timing.v_active;</div><div class='add'>+	phantom-&gt;timing.vblank_nom = phantom-&gt;timing.v_total - phantom-&gt;timing.v_active;</div><div class='add'>+	phantom-&gt;timing.drr_config.enabled = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void create_phantom_plane_from_main_plane(struct dml2_plane_parameters *phantom, const struct dml2_plane_parameters *main,</div><div class='add'>+	const struct dml2_stream_parameters *phantom_stream, int phantom_stream_index, const struct dml2_stream_parameters *main_stream)</div><div class='add'>+{</div><div class='add'>+	memcpy(phantom, main, sizeof(struct dml2_plane_parameters));</div><div class='add'>+</div><div class='add'>+	phantom-&gt;stream_index = phantom_stream_index;</div><div class='add'>+	phantom-&gt;overrides.refresh_from_mall = dml2_refresh_from_mall_mode_override_force_disable;</div><div class='add'>+	phantom-&gt;overrides.legacy_svp_config = dml2_svp_mode_override_phantom_pipe_no_data_return;</div><div class='add'>+	phantom-&gt;composition.viewport.plane0.height = (long int unsigned) math_min2(math_ceil2(</div><div class='add'>+		(double)main-&gt;composition.scaler_info.plane0.v_ratio * (double)phantom_stream-&gt;timing.v_active, 16.0),</div><div class='add'>+		(double)main-&gt;composition.viewport.plane0.height);</div><div class='add'>+	phantom-&gt;composition.viewport.plane1.height = (long int unsigned) math_min2(math_ceil2(</div><div class='add'>+		(double)main-&gt;composition.scaler_info.plane1.v_ratio * (double)phantom_stream-&gt;timing.v_active, 16.0),</div><div class='add'>+		(double)main-&gt;composition.viewport.plane1.height);</div><div class='add'>+	phantom-&gt;immediate_flip = false;</div><div class='add'>+	phantom-&gt;dynamic_meta_data.enable = false;</div><div class='add'>+	phantom-&gt;cursor.num_cursors = 0;</div><div class='add'>+	phantom-&gt;cursor.cursor_width = 0;</div><div class='add'>+	phantom-&gt;tdlut.setup_for_tdlut = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,</div><div class='add'>+	struct dml2_core_scratch *scratch)</div><div class='add'>+{</div><div class='add'>+	unsigned int stream_index, plane_index;</div><div class='add'>+	const struct dml2_plane_parameters *main_plane;</div><div class='add'>+	const struct dml2_stream_parameters *main_stream;</div><div class='add'>+	const struct dml2_stream_parameters *phantom_stream;</div><div class='add'>+</div><div class='add'>+	memcpy(svp_expanded_display_cfg, &amp;display_cfg-&gt;display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+	memset(scratch-&gt;main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);</div><div class='add'>+	memset(scratch-&gt;svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);</div><div class='add'>+	memset(scratch-&gt;main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);</div><div class='add'>+</div><div class='add'>+	if (!display_cfg-&gt;display_config.overrides.enable_subvp_implicit_pmo)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* disable unbounded requesting for all planes until stage 3 has been performed */</div><div class='add'>+	if (!display_cfg-&gt;stage3.performed) {</div><div class='add'>+		svp_expanded_display_cfg-&gt;overrides.hw.force_unbounded_requesting.enable = true;</div><div class='add'>+		svp_expanded_display_cfg-&gt;overrides.hw.force_unbounded_requesting.value = false;</div><div class='add'>+	}</div><div class='add'>+	// Create the phantom streams</div><div class='add'>+	for (stream_index = 0; stream_index &lt; display_cfg-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		main_stream = &amp;display_cfg-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+		scratch-&gt;main_stream_index_from_svp_stream_index[stream_index] = stream_index;</div><div class='add'>+		scratch-&gt;svp_stream_index_from_main_stream_index[stream_index] = stream_index;</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;stage3.stream_svp_meta[stream_index].valid) {</div><div class='add'>+			// Create the phantom stream</div><div class='add'>+			create_phantom_stream_from_main_stream(&amp;svp_expanded_display_cfg-&gt;stream_descriptors[svp_expanded_display_cfg-&gt;num_streams],</div><div class='add'>+				main_stream, &amp;display_cfg-&gt;stage3.stream_svp_meta[stream_index]);</div><div class='add'>+</div><div class='add'>+			// Associate this phantom stream to the main stream</div><div class='add'>+			scratch-&gt;main_stream_index_from_svp_stream_index[svp_expanded_display_cfg-&gt;num_streams] = stream_index;</div><div class='add'>+			scratch-&gt;svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg-&gt;num_streams;</div><div class='add'>+</div><div class='add'>+			// Increment num streams</div><div class='add'>+			svp_expanded_display_cfg-&gt;num_streams++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Create the phantom planes</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_cfg-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		main_plane = &amp;display_cfg-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;stage3.stream_svp_meta[main_plane-&gt;stream_index].valid) {</div><div class='add'>+			main_stream = &amp;display_cfg-&gt;display_config.stream_descriptors[main_plane-&gt;stream_index];</div><div class='add'>+			phantom_stream = &amp;svp_expanded_display_cfg-&gt;stream_descriptors[scratch-&gt;svp_stream_index_from_main_stream_index[main_plane-&gt;stream_index]];</div><div class='add'>+			create_phantom_plane_from_main_plane(&amp;svp_expanded_display_cfg-&gt;plane_descriptors[svp_expanded_display_cfg-&gt;num_planes],</div><div class='add'>+				main_plane, phantom_stream, scratch-&gt;svp_stream_index_from_main_stream_index[main_plane-&gt;stream_index], main_stream);</div><div class='add'>+</div><div class='add'>+			// Associate this phantom plane to the main plane</div><div class='add'>+			scratch-&gt;phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg-&gt;num_planes] = plane_index;</div><div class='add'>+			scratch-&gt;main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg-&gt;num_planes;</div><div class='add'>+</div><div class='add'>+			// Increment num planes</div><div class='add'>+			svp_expanded_display_cfg-&gt;num_planes++;</div><div class='add'>+</div><div class='add'>+			// Adjust the main plane settings</div><div class='add'>+			svp_expanded_display_cfg-&gt;plane_descriptors[plane_index].overrides.legacy_svp_config = dml2_svp_mode_override_main_pipe;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pack_mode_programming_params_with_implicit_subvp(struct dml2_core_instance *core, const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+	const struct dml2_display_cfg *svp_expanded_display_cfg, struct dml2_display_cfg_programming *programming, struct dml2_core_scratch *scratch)</div><div class='add'>+{</div><div class='add'>+	unsigned int stream_index, plane_index, pipe_offset, stream_already_populated_mask, main_plane_index, mcache_index;</div><div class='add'>+	unsigned int total_main_mcaches_required = 0;</div><div class='add'>+	int total_pipe_regs_copied = 0;</div><div class='add'>+	int dml_internal_pipe_index = 0;</div><div class='add'>+	const struct dml2_plane_parameters *main_plane;</div><div class='add'>+	const struct dml2_plane_parameters *phantom_plane;</div><div class='add'>+	const struct dml2_stream_parameters *main_stream;</div><div class='add'>+	const struct dml2_stream_parameters *phantom_stream;</div><div class='add'>+</div><div class='add'>+	// Copy the unexpanded display config to output</div><div class='add'>+	memcpy(&amp;programming-&gt;display_config, &amp;display_cfg-&gt;display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+</div><div class='add'>+	// Set the global register values</div><div class='add'>+	dml2_core_calcs_get_arb_params(&amp;display_cfg-&gt;display_config, &amp;core-&gt;clean_me_up.mode_lib, &amp;programming-&gt;global_regs.arb_regs);</div><div class='add'>+	// Get watermarks uses display config for ref clock override, so it doesn't matter whether we pass the pre or post expansion</div><div class='add'>+	// display config</div><div class='add'>+	dml2_core_calcs_get_watermarks(&amp;display_cfg-&gt;display_config, &amp;core-&gt;clean_me_up.mode_lib, &amp;programming-&gt;global_regs.wm_regs[0]);</div><div class='add'>+</div><div class='add'>+	// Check if FAMS2 is required</div><div class='add'>+	if (display_cfg-&gt;stage3.performed &amp;&amp; display_cfg-&gt;stage3.success) {</div><div class='add'>+		programming-&gt;fams2_required = display_cfg-&gt;stage3.fams2_required;</div><div class='add'>+</div><div class='add'>+		dml2_core_calcs_get_global_fams2_programming(&amp;core-&gt;clean_me_up.mode_lib, display_cfg, &amp;programming-&gt;fams2_global_config);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Only loop over all the main streams (the implicit svp streams will be packed as part of the main stream)</div><div class='add'>+	for (stream_index = 0; stream_index &lt; programming-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		main_stream = &amp;svp_expanded_display_cfg-&gt;stream_descriptors[stream_index];</div><div class='add'>+		phantom_stream = &amp;svp_expanded_display_cfg-&gt;stream_descriptors[scratch-&gt;svp_stream_index_from_main_stream_index[stream_index]];</div><div class='add'>+</div><div class='add'>+		// Set the descriptor</div><div class='add'>+		programming-&gt;stream_programming[stream_index].stream_descriptor = &amp;programming-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+</div><div class='add'>+		// Set the odm combine factor</div><div class='add'>+		programming-&gt;stream_programming[stream_index].num_odms_required = display_cfg-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index].odms_used;</div><div class='add'>+</div><div class='add'>+		// Check if the stream has implicit SVP enabled</div><div class='add'>+		if (main_stream != phantom_stream) {</div><div class='add'>+			// If so, copy the phantom stream descriptor</div><div class='add'>+			programming-&gt;stream_programming[stream_index].phantom_stream.enabled = true;</div><div class='add'>+			memcpy(&amp;programming-&gt;stream_programming[stream_index].phantom_stream.descriptor, phantom_stream, sizeof(struct dml2_stream_parameters));</div><div class='add'>+		} else {</div><div class='add'>+			programming-&gt;stream_programming[stream_index].phantom_stream.enabled = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// Due to the way DML indexes data internally, it's easier to populate the rest of the display</div><div class='add'>+		// stream programming in the next stage</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dml_internal_pipe_index = 0;</div><div class='add'>+	total_pipe_regs_copied = 0;</div><div class='add'>+	stream_already_populated_mask = 0x0;</div><div class='add'>+</div><div class='add'>+	// Loop over all main planes</div><div class='add'>+	for (plane_index = 0; plane_index &lt; programming-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		main_plane = &amp;svp_expanded_display_cfg-&gt;plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+		// Set the descriptor</div><div class='add'>+		programming-&gt;plane_programming[plane_index].plane_descriptor = &amp;programming-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+		// Set the mpc combine factor</div><div class='add'>+		programming-&gt;plane_programming[plane_index].num_dpps_required = core-&gt;clean_me_up.mode_lib.mp.NoOfDPP[plane_index];</div><div class='add'>+</div><div class='add'>+		// Setup the appropriate p-state strategy</div><div class='add'>+		if (display_cfg-&gt;stage3.performed &amp;&amp; display_cfg-&gt;stage3.success) {</div><div class='add'>+			programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = display_cfg-&gt;stage3.pstate_switch_modes[plane_index];</div><div class='add'>+		} else {</div><div class='add'>+			programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_na;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dml2_core_calcs_get_mall_allocation(&amp;core-&gt;clean_me_up.mode_lib, &amp;programming-&gt;plane_programming[plane_index].surface_size_mall_bytes, dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+		memcpy(&amp;programming-&gt;plane_programming[plane_index].mcache_allocation,</div><div class='add'>+			&amp;display_cfg-&gt;stage2.mcache_allocations[plane_index],</div><div class='add'>+			sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+		total_main_mcaches_required += programming-&gt;plane_programming[plane_index].mcache_allocation.num_mcaches_plane0 +</div><div class='add'>+			programming-&gt;plane_programming[plane_index].mcache_allocation.num_mcaches_plane1 -</div><div class='add'>+			(programming-&gt;plane_programming[plane_index].mcache_allocation.last_slice_sharing.plane0_plane1 ? 1 : 0);</div><div class='add'>+</div><div class='add'>+		for (pipe_offset = 0; pipe_offset &lt; programming-&gt;plane_programming[plane_index].num_dpps_required; pipe_offset++) {</div><div class='add'>+			// Assign storage for this pipe's register values</div><div class='add'>+			programming-&gt;plane_programming[plane_index].pipe_regs[pipe_offset] = &amp;programming-&gt;pipe_regs[total_pipe_regs_copied];</div><div class='add'>+			memset(programming-&gt;plane_programming[plane_index].pipe_regs[pipe_offset], 0, sizeof(struct dml2_dchub_per_pipe_register_set));</div><div class='add'>+			total_pipe_regs_copied++;</div><div class='add'>+</div><div class='add'>+			// Populate the main plane regs</div><div class='add'>+			dml2_core_calcs_get_pipe_regs(svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, programming-&gt;plane_programming[plane_index].pipe_regs[pipe_offset], dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+			// Multiple planes can refer to the same stream index, so it's only necessary to populate it once</div><div class='add'>+			if (!(stream_already_populated_mask &amp; (0x1 &lt;&lt; main_plane-&gt;stream_index))) {</div><div class='add'>+				dml2_core_calcs_get_stream_programming(&amp;core-&gt;clean_me_up.mode_lib, &amp;programming-&gt;stream_programming[main_plane-&gt;stream_index], dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+				programming-&gt;stream_programming[main_plane-&gt;stream_index].uclk_pstate_method = programming-&gt;plane_programming[plane_index].uclk_pstate_support_method;</div><div class='add'>+</div><div class='add'>+				/* unconditionally populate fams2 params */</div><div class='add'>+				dml2_core_calcs_get_stream_fams2_programming(&amp;core-&gt;clean_me_up.mode_lib,</div><div class='add'>+					display_cfg,</div><div class='add'>+					&amp;programming-&gt;stream_programming[main_plane-&gt;stream_index].fams2_base_params,</div><div class='add'>+					&amp;programming-&gt;stream_programming[main_plane-&gt;stream_index].fams2_sub_params,</div><div class='add'>+					programming-&gt;stream_programming[main_plane-&gt;stream_index].uclk_pstate_method,</div><div class='add'>+					plane_index);</div><div class='add'>+</div><div class='add'>+				stream_already_populated_mask |= (0x1 &lt;&lt; main_plane-&gt;stream_index);</div><div class='add'>+			}</div><div class='add'>+			dml_internal_pipe_index++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (plane_index = programming-&gt;display_config.num_planes; plane_index &lt; svp_expanded_display_cfg-&gt;num_planes; plane_index++) {</div><div class='add'>+		phantom_plane = &amp;svp_expanded_display_cfg-&gt;plane_descriptors[plane_index];</div><div class='add'>+		main_plane_index = scratch-&gt;phantom_plane_index_to_main_plane_index[plane_index];</div><div class='add'>+		main_plane = &amp;svp_expanded_display_cfg-&gt;plane_descriptors[main_plane_index];</div><div class='add'>+</div><div class='add'>+		programming-&gt;plane_programming[main_plane_index].phantom_plane.valid = true;</div><div class='add'>+		memcpy(&amp;programming-&gt;plane_programming[main_plane_index].phantom_plane.descriptor, phantom_plane, sizeof(struct dml2_plane_parameters));</div><div class='add'>+</div><div class='add'>+		dml2_core_calcs_get_mall_allocation(&amp;core-&gt;clean_me_up.mode_lib, &amp;programming-&gt;plane_programming[main_plane_index].svp_size_mall_bytes, dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+		/* generate mcache allocation, phantoms use identical mcache configuration, but in the MALL set and unique mcache ID's beginning after all main ID's */</div><div class='add'>+		memcpy(&amp;programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation,</div><div class='add'>+			&amp;programming-&gt;plane_programming[main_plane_index].mcache_allocation,</div><div class='add'>+			sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+		for (mcache_index = 0; mcache_index &lt; programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.num_mcaches_plane0; mcache_index++) {</div><div class='add'>+			programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.global_mcache_ids_plane0[mcache_index] += total_main_mcaches_required;</div><div class='add'>+			programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.global_mcache_ids_mall_plane0[mcache_index] =</div><div class='add'>+				programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.global_mcache_ids_plane0[mcache_index];</div><div class='add'>+		}</div><div class='add'>+		for (mcache_index = 0; mcache_index &lt; programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.num_mcaches_plane1; mcache_index++) {</div><div class='add'>+			programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.global_mcache_ids_plane1[mcache_index] += total_main_mcaches_required;</div><div class='add'>+			programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.global_mcache_ids_mall_plane1[mcache_index] =</div><div class='add'>+				programming-&gt;plane_programming[main_plane_index].phantom_plane.mcache_allocation.global_mcache_ids_plane1[mcache_index];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (pipe_offset = 0; pipe_offset &lt; programming-&gt;plane_programming[main_plane_index].num_dpps_required; pipe_offset++) {</div><div class='add'>+			// Assign storage for this pipe's register values</div><div class='add'>+			programming-&gt;plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset] = &amp;programming-&gt;pipe_regs[total_pipe_regs_copied];</div><div class='add'>+			memset(programming-&gt;plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset], 0, sizeof(struct dml2_dchub_per_pipe_register_set));</div><div class='add'>+			total_pipe_regs_copied++;</div><div class='add'>+</div><div class='add'>+			// Populate the phantom plane regs</div><div class='add'>+			dml2_core_calcs_get_pipe_regs(svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, programming-&gt;plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset], dml_internal_pipe_index);</div><div class='add'>+			// Populate the phantom stream specific programming</div><div class='add'>+			if (!(stream_already_populated_mask &amp; (0x1 &lt;&lt; phantom_plane-&gt;stream_index))) {</div><div class='add'>+				dml2_core_calcs_get_global_sync_programming(&amp;core-&gt;clean_me_up.mode_lib, &amp;programming-&gt;stream_programming[main_plane-&gt;stream_index].phantom_stream.global_sync, dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+				stream_already_populated_mask |= (0x1 &lt;&lt; phantom_plane-&gt;stream_index);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			dml_internal_pipe_index++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_instance *core = (struct dml2_core_instance *)in_out-&gt;instance;</div><div class='add'>+	struct dml2_core_mode_support_locals *l = &amp;core-&gt;scratch.mode_support_locals;</div><div class='add'>+</div><div class='add'>+	bool result;</div><div class='add'>+	unsigned int i, stream_index, stream_bitmask;</div><div class='add'>+	int unsigned odm_count, num_odm_output_segments, dpp_count;</div><div class='add'>+</div><div class='add'>+	expand_implict_subvp(in_out-&gt;display_cfg, &amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;scratch);</div><div class='add'>+</div><div class='add'>+	l-&gt;mode_support_ex_params.mode_lib = &amp;core-&gt;clean_me_up.mode_lib;</div><div class='add'>+	l-&gt;mode_support_ex_params.in_display_cfg = &amp;l-&gt;svp_expanded_display_cfg;</div><div class='add'>+	l-&gt;mode_support_ex_params.min_clk_table = in_out-&gt;min_clk_table;</div><div class='add'>+	l-&gt;mode_support_ex_params.min_clk_index = in_out-&gt;min_clk_index;</div><div class='add'>+	l-&gt;mode_support_ex_params.out_evaluation_info = &amp;in_out-&gt;mode_support_result.cfg_support_info.clean_me_up.support_info;</div><div class='add'>+</div><div class='add'>+	result = dml2_core_calcs_mode_support_ex(&amp;l-&gt;mode_support_ex_params);</div><div class='add'>+</div><div class='add'>+	in_out-&gt;mode_support_result.cfg_support_info.is_supported = result;</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		in_out-&gt;mode_support_result.global.dispclk_khz = (unsigned int)(core-&gt;clean_me_up.mode_lib.ms.RequiredDISPCLK * 1000);</div><div class='add'>+		in_out-&gt;mode_support_result.global.dcfclk_deepsleep_khz = (unsigned int)(core-&gt;clean_me_up.mode_lib.ms.dcfclk_deepsleep * 1000);</div><div class='add'>+		in_out-&gt;mode_support_result.global.socclk_khz = (unsigned int)(core-&gt;clean_me_up.mode_lib.ms.SOCCLK * 1000);</div><div class='add'>+</div><div class='add'>+		in_out-&gt;mode_support_result.global.fclk_pstate_supported = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;global_fclk_change_supported;</div><div class='add'>+		in_out-&gt;mode_support_result.global.uclk_pstate_supported = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;global_dram_clock_change_supported;</div><div class='add'>+</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.fclk_khz = (unsigned long)(core-&gt;clean_me_up.mode_lib.ms.FabricClock * 1000);</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.dcfclk_khz = (unsigned long)(core-&gt;clean_me_up.mode_lib.ms.DCFCLK * 1000);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.fclk_khz = (unsigned long)core-&gt;clean_me_up.mode_lib.ms.FabricClock * 1000;</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.dcfclk_khz = (unsigned long)core-&gt;clean_me_up.mode_lib.ms.DCFCLK * 1000;</div><div class='add'>+</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.average_bw_sdp_kbps = 0;</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.urgent_bw_dram_kbps = 0;</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.average_bw_sdp_kbps = 0;</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_dram_kbps = 0;</div><div class='add'>+</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.average_bw_sdp_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] * 1000), 1.0);</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.urgent_bw_sdp_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] * 1000), 1.0);</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.average_bw_sdp_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] * 1000), 1.0);</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_sdp_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;urg_bandwidth_required_flip[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] * 1000), 1.0);</div><div class='add'>+</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.average_bw_dram_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] * 1000), 1.0);</div><div class='add'>+		in_out-&gt;mode_support_result.global.active.urgent_bw_dram_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] * 1000), 1.0);</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.average_bw_dram_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] * 1000), 1.0);</div><div class='add'>+		in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_dram_kbps = (unsigned long)math_ceil2((l-&gt;mode_support_ex_params.out_evaluation_info-&gt;urg_bandwidth_required_flip[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] * 1000), 1.0);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: in_out-&gt;mode_support_result.global.active.urgent_bw_sdp_kbps = %ld\n", __func__, in_out-&gt;mode_support_result.global.active.urgent_bw_sdp_kbps);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_sdp_kbps = %ld\n", __func__, in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_sdp_kbps);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: in_out-&gt;mode_support_result.global.active.urgent_bw_dram_kbps = %ld\n", __func__, in_out-&gt;mode_support_result.global.active.urgent_bw_dram_kbps);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_dram_kbps = %ld\n", __func__, in_out-&gt;mode_support_result.global.svp_prefetch.urgent_bw_dram_kbps);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; l-&gt;svp_expanded_display_cfg.num_planes; i++) {</div><div class='add'>+			in_out-&gt;mode_support_result.per_plane[i].dppclk_khz = (unsigned int)(core-&gt;clean_me_up.mode_lib.ms.RequiredDPPCLK[i] * 1000);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		stream_bitmask = 0;</div><div class='add'>+		for (i = 0; i &lt; l-&gt;svp_expanded_display_cfg.num_planes; i++) {</div><div class='add'>+			odm_count = 1;</div><div class='add'>+			dpp_count = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;DPPPerSurface[i];</div><div class='add'>+			num_odm_output_segments = 1;</div><div class='add'>+</div><div class='add'>+			switch (l-&gt;mode_support_ex_params.out_evaluation_info-&gt;ODMMode[i]) {</div><div class='add'>+			case dml2_odm_mode_bypass:</div><div class='add'>+				odm_count = 1;</div><div class='add'>+				dpp_count = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;DPPPerSurface[i];</div><div class='add'>+				break;</div><div class='add'>+			case dml2_odm_mode_combine_2to1:</div><div class='add'>+				odm_count = 2;</div><div class='add'>+				dpp_count = 2;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_odm_mode_combine_3to1:</div><div class='add'>+				odm_count = 3;</div><div class='add'>+				dpp_count = 3;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_odm_mode_combine_4to1:</div><div class='add'>+				odm_count = 4;</div><div class='add'>+				dpp_count = 4;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_odm_mode_split_1to2:</div><div class='add'>+			case dml2_odm_mode_mso_1to2:</div><div class='add'>+				num_odm_output_segments = 2;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_odm_mode_mso_1to4:</div><div class='add'>+				num_odm_output_segments = 4;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_odm_mode_auto:</div><div class='add'>+			default:</div><div class='add'>+				odm_count = 1;</div><div class='add'>+				dpp_count = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;DPPPerSurface[i];</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			in_out-&gt;mode_support_result.cfg_support_info.plane_support_info[i].dpps_used = dpp_count;</div><div class='add'>+</div><div class='add'>+			dml2_core_calcs_get_plane_support_info(&amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, &amp;in_out-&gt;mode_support_result.cfg_support_info.plane_support_info[i], i);</div><div class='add'>+</div><div class='add'>+			stream_index = l-&gt;svp_expanded_display_cfg.plane_descriptors[i].stream_index;</div><div class='add'>+</div><div class='add'>+			in_out-&gt;mode_support_result.per_stream[stream_index].dscclk_khz = (unsigned int)core-&gt;clean_me_up.mode_lib.ms.required_dscclk_freq_mhz[i] * 1000;</div><div class='add'>+			DML_LOG_VERBOSE("CORE_DCN4::%s: i=%d stream_index=%d, in_out-&gt;mode_support_result.per_stream[stream_index].dscclk_khz = %u\n", __func__, i, stream_index, in_out-&gt;mode_support_result.per_stream[stream_index].dscclk_khz);</div><div class='add'>+</div><div class='add'>+			if (!((stream_bitmask &gt;&gt; stream_index) &amp; 0x1)) {</div><div class='add'>+				in_out-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index].odms_used = odm_count;</div><div class='add'>+				in_out-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index].num_odm_output_segments = num_odm_output_segments;</div><div class='add'>+				in_out-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index].dsc_enable = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;DSCEnabled[i];</div><div class='add'>+				in_out-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index].num_dsc_slices = l-&gt;mode_support_ex_params.out_evaluation_info-&gt;NumberOfDSCSlices[i];</div><div class='add'>+				dml2_core_calcs_get_stream_support_info(&amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, &amp;in_out-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index], i);</div><div class='add'>+				in_out-&gt;mode_support_result.per_stream[stream_index].dtbclk_khz = (unsigned int)(core-&gt;clean_me_up.mode_lib.ms.RequiredDTBCLK[i] * 1000);</div><div class='add'>+				stream_bitmask |= 0x1 &lt;&lt; stream_index;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int lookup_uclk_dpm_index_by_freq(unsigned long uclk_freq_khz, struct dml2_soc_bb *soc_bb)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; soc_bb-&gt;clk_table.uclk.num_clk_values; i++) {</div><div class='add'>+		if (uclk_freq_khz == soc_bb-&gt;clk_table.uclk.clk_values_khz[i])</div><div class='add'>+			return i;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_instance *core = (struct dml2_core_instance *)in_out-&gt;instance;</div><div class='add'>+	struct dml2_core_mode_programming_locals *l = &amp;core-&gt;scratch.mode_programming_locals;</div><div class='add'>+</div><div class='add'>+	bool result = false;</div><div class='add'>+	unsigned int pipe_offset;</div><div class='add'>+	int dml_internal_pipe_index;</div><div class='add'>+	int total_pipe_regs_copied = 0;</div><div class='add'>+	int stream_already_populated_mask = 0;</div><div class='add'>+</div><div class='add'>+	int main_stream_index;</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+</div><div class='add'>+	expand_implict_subvp(in_out-&gt;display_cfg, &amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;scratch);</div><div class='add'>+</div><div class='add'>+	l-&gt;mode_programming_ex_params.mode_lib = &amp;core-&gt;clean_me_up.mode_lib;</div><div class='add'>+	l-&gt;mode_programming_ex_params.in_display_cfg = &amp;l-&gt;svp_expanded_display_cfg;</div><div class='add'>+	l-&gt;mode_programming_ex_params.min_clk_table = in_out-&gt;instance-&gt;minimum_clock_table;</div><div class='add'>+	l-&gt;mode_programming_ex_params.cfg_support_info = in_out-&gt;cfg_support_info;</div><div class='add'>+	l-&gt;mode_programming_ex_params.programming = in_out-&gt;programming;</div><div class='add'>+	l-&gt;mode_programming_ex_params.min_clk_index = lookup_uclk_dpm_index_by_freq(in_out-&gt;programming-&gt;min_clocks.dcn4x.active.uclk_khz,</div><div class='add'>+		&amp;core-&gt;clean_me_up.mode_lib.soc);</div><div class='add'>+</div><div class='add'>+	result = dml2_core_calcs_mode_programming_ex(&amp;l-&gt;mode_programming_ex_params);</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		// If the input display configuration contains implict SVP, we need to use a special packer</div><div class='add'>+		if (in_out-&gt;display_cfg-&gt;display_config.overrides.enable_subvp_implicit_pmo) {</div><div class='add'>+			pack_mode_programming_params_with_implicit_subvp(core, in_out-&gt;display_cfg, &amp;l-&gt;svp_expanded_display_cfg, in_out-&gt;programming, &amp;core-&gt;scratch);</div><div class='add'>+		} else {</div><div class='add'>+			memcpy(&amp;in_out-&gt;programming-&gt;display_config, in_out-&gt;display_cfg, sizeof(struct dml2_display_cfg));</div><div class='add'>+</div><div class='add'>+			dml2_core_calcs_get_arb_params(&amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, &amp;in_out-&gt;programming-&gt;global_regs.arb_regs);</div><div class='add'>+			dml2_core_calcs_get_watermarks(&amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, &amp;in_out-&gt;programming-&gt;global_regs.wm_regs[0]);</div><div class='add'>+</div><div class='add'>+			dml_internal_pipe_index = 0;</div><div class='add'>+</div><div class='add'>+			for (plane_index = 0; plane_index &lt; in_out-&gt;programming-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+				in_out-&gt;programming-&gt;plane_programming[plane_index].num_dpps_required = core-&gt;clean_me_up.mode_lib.mp.NoOfDPP[plane_index];</div><div class='add'>+</div><div class='add'>+				if (in_out-&gt;programming-&gt;display_config.plane_descriptors[plane_index].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe)</div><div class='add'>+					in_out-&gt;programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_fw_svp;</div><div class='add'>+				else if (in_out-&gt;programming-&gt;display_config.plane_descriptors[plane_index].overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe)</div><div class='add'>+					in_out-&gt;programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_fw_svp;</div><div class='add'>+				else if (in_out-&gt;programming-&gt;display_config.plane_descriptors[plane_index].overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return)</div><div class='add'>+					in_out-&gt;programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_fw_svp;</div><div class='add'>+				else {</div><div class='add'>+					if (core-&gt;clean_me_up.mode_lib.mp.MaxActiveDRAMClockChangeLatencySupported[plane_index] &gt;= core-&gt;clean_me_up.mode_lib.soc.power_management_parameters.dram_clk_change_blackout_us)</div><div class='add'>+						in_out-&gt;programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_vactive;</div><div class='add'>+					else if (core-&gt;clean_me_up.mode_lib.mp.TWait[plane_index] &gt;= core-&gt;clean_me_up.mode_lib.soc.power_management_parameters.dram_clk_change_blackout_us)</div><div class='add'>+						in_out-&gt;programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_vblank;</div><div class='add'>+					else</div><div class='add'>+						in_out-&gt;programming-&gt;plane_programming[plane_index].uclk_pstate_support_method = dml2_pstate_method_na;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				dml2_core_calcs_get_mall_allocation(&amp;core-&gt;clean_me_up.mode_lib, &amp;in_out-&gt;programming-&gt;plane_programming[plane_index].surface_size_mall_bytes, dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+				memcpy(&amp;in_out-&gt;programming-&gt;plane_programming[plane_index].mcache_allocation,</div><div class='add'>+					&amp;in_out-&gt;display_cfg-&gt;stage2.mcache_allocations[plane_index],</div><div class='add'>+					sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+</div><div class='add'>+				for (pipe_offset = 0; pipe_offset &lt; in_out-&gt;programming-&gt;plane_programming[plane_index].num_dpps_required; pipe_offset++) {</div><div class='add'>+					in_out-&gt;programming-&gt;plane_programming[plane_index].plane_descriptor = &amp;in_out-&gt;programming-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+					// Assign storage for this pipe's register values</div><div class='add'>+					in_out-&gt;programming-&gt;plane_programming[plane_index].pipe_regs[pipe_offset] = &amp;in_out-&gt;programming-&gt;pipe_regs[total_pipe_regs_copied];</div><div class='add'>+					memset(in_out-&gt;programming-&gt;plane_programming[plane_index].pipe_regs[pipe_offset], 0, sizeof(struct dml2_dchub_per_pipe_register_set));</div><div class='add'>+					total_pipe_regs_copied++;</div><div class='add'>+</div><div class='add'>+					// Populate</div><div class='add'>+					dml2_core_calcs_get_pipe_regs(&amp;l-&gt;svp_expanded_display_cfg, &amp;core-&gt;clean_me_up.mode_lib, in_out-&gt;programming-&gt;plane_programming[plane_index].pipe_regs[pipe_offset], dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+					main_stream_index = in_out-&gt;programming-&gt;display_config.plane_descriptors[plane_index].stream_index;</div><div class='add'>+</div><div class='add'>+					// Multiple planes can refer to the same stream index, so it's only necessary to populate it once</div><div class='add'>+					if (!(stream_already_populated_mask &amp; (0x1 &lt;&lt; main_stream_index))) {</div><div class='add'>+						in_out-&gt;programming-&gt;stream_programming[main_stream_index].stream_descriptor = &amp;in_out-&gt;programming-&gt;display_config.stream_descriptors[main_stream_index];</div><div class='add'>+						in_out-&gt;programming-&gt;stream_programming[main_stream_index].num_odms_required = in_out-&gt;cfg_support_info-&gt;stream_support_info[main_stream_index].odms_used;</div><div class='add'>+						dml2_core_calcs_get_stream_programming(&amp;core-&gt;clean_me_up.mode_lib, &amp;in_out-&gt;programming-&gt;stream_programming[main_stream_index], dml_internal_pipe_index);</div><div class='add'>+</div><div class='add'>+						stream_already_populated_mask |= (0x1 &lt;&lt; main_stream_index);</div><div class='add'>+					}</div><div class='add'>+					dml_internal_pipe_index++;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_internal_display_mode_lib *mode_lib = &amp;in_out-&gt;instance-&gt;clean_me_up.mode_lib;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;mode_is_supported)</div><div class='add'>+		in_out-&gt;programming-&gt;informative.voltage_level = in_out-&gt;instance-&gt;scratch.mode_programming_locals.mode_programming_ex_params.min_clk_index;</div><div class='add'>+	else</div><div class='add'>+		in_out-&gt;programming-&gt;informative.voltage_level = in_out-&gt;instance-&gt;scratch.mode_support_locals.mode_support_ex_params.min_clk_index;</div><div class='add'>+</div><div class='add'>+	dml2_core_calcs_get_informative(mode_lib, in_out-&gt;programming);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool core_dcn4_calculate_mcache_allocation(struct dml2_calculate_mcache_allocation_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	memset(in_out-&gt;mcache_allocation, 0, sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+</div><div class='add'>+	dml2_core_calcs_get_mcache_allocation(&amp;in_out-&gt;instance-&gt;clean_me_up.mode_lib, in_out-&gt;mcache_allocation, in_out-&gt;plane_index);</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;mcache_allocation-&gt;num_mcaches_plane0 &gt; 0)</div><div class='add'>+		in_out-&gt;mcache_allocation-&gt;mcache_x_offsets_plane0[in_out-&gt;mcache_allocation-&gt;num_mcaches_plane0 - 1] = in_out-&gt;plane_descriptor-&gt;surface.plane0.width;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;mcache_allocation-&gt;num_mcaches_plane1 &gt; 0)</div><div class='add'>+		in_out-&gt;mcache_allocation-&gt;mcache_x_offsets_plane1[in_out-&gt;mcache_allocation-&gt;num_mcaches_plane1 - 1] = in_out-&gt;plane_descriptor-&gt;surface.plane1.width;</div><div class='add'>+</div><div class='add'>+	in_out-&gt;mcache_allocation-&gt;requires_dedicated_mall_mcache = false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h<br/>new file mode 100644<br/>index 000000000000..a68bb001a346<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_CORE_DCN4_H__</div><div class='add'>+#define __DML2_CORE_DCN4_H__</div><div class='add'>+bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out);</div><div class='add'>+bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out);</div><div class='add'>+bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out);</div><div class='add'>+bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out);</div><div class='add'>+bool core_dcn4_calculate_mcache_allocation(struct dml2_calculate_mcache_allocation_in_out *in_out);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c<br/>new file mode 100644<br/>index 000000000000..a02e9fd6b5ca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c</a></div><div class='hunk'>@@ -0,0 +1,13342 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml2_core_dcn4_calcs.h"</div><div class='add'>+#include "dml2_debug.h"</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+#define DML2_MAX_FMT_420_BUFFER_WIDTH 4096</div><div class='add'>+#define DML_MAX_NUM_OF_SLICES_PER_DSC 4</div><div class='add'>+#define DML_MAX_COMPRESSION_RATIO 4</div><div class='add'>+//#define DML_MODE_SUPPORT_USE_DPM_DRAM_BW</div><div class='add'>+//#define DML_GLOBAL_PREFETCH_CHECK</div><div class='add'>+#define ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE</div><div class='add'>+#define DML_MAX_VSTARTUP_START 1023</div><div class='add'>+</div><div class='add'>+const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type)</div><div class='add'>+{</div><div class='add'>+	switch (bw_type) {</div><div class='add'>+	case (dml2_core_internal_bw_sdp):</div><div class='add'>+		return("dml2_core_internal_bw_sdp");</div><div class='add'>+	case (dml2_core_internal_bw_dram):</div><div class='add'>+		return("dml2_core_internal_bw_dram");</div><div class='add'>+	case (dml2_core_internal_bw_max):</div><div class='add'>+		return("dml2_core_internal_bw_max");</div><div class='add'>+	default:</div><div class='add'>+		return("dml2_core_internal_bw_unknown");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const char *dml2_core_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type)</div><div class='add'>+{</div><div class='add'>+	switch (dml2_core_internal_soc_state_type) {</div><div class='add'>+	case (dml2_core_internal_soc_state_sys_idle):</div><div class='add'>+		return("dml2_core_internal_soc_state_sys_idle");</div><div class='add'>+	case (dml2_core_internal_soc_state_sys_active):</div><div class='add'>+		return("dml2_core_internal_soc_state_sys_active");</div><div class='add'>+	case (dml2_core_internal_soc_state_svp_prefetch):</div><div class='add'>+		return("dml2_core_internal_soc_state_svp_prefetch");</div><div class='add'>+	case dml2_core_internal_soc_state_max:</div><div class='add'>+	default:</div><div class='add'>+		return("dml2_core_internal_soc_state_unknown");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double dml2_core_div_rem(double dividend, unsigned int divisor, unsigned int *remainder)</div><div class='add'>+{</div><div class='add'>+	*remainder = ((dividend / divisor) - (int)(dividend / divisor) &gt; 0);</div><div class='add'>+	return dividend / divisor;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml2_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)</div><div class='add'>+{</div><div class='add'>+	DML_LOG_VERBOSE("DML: ===================================== \n");</div><div class='add'>+	DML_LOG_VERBOSE("DML: DML_MODE_SUPPORT_INFO_ST\n");</div><div class='add'>+	if (!fail_only || support-&gt;ScaleRatioAndTapsSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ScaleRatioAndTapsSupport = %d\n", support-&gt;ScaleRatioAndTapsSupport);</div><div class='add'>+	if (!fail_only || support-&gt;SourceFormatPixelAndScanSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: SourceFormatPixelAndScanSupport = %d\n", support-&gt;SourceFormatPixelAndScanSupport);</div><div class='add'>+	if (!fail_only || support-&gt;ViewportSizeSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ViewportSizeSupport = %d\n", support-&gt;ViewportSizeSupport);</div><div class='add'>+	if (!fail_only || support-&gt;LinkRateDoesNotMatchDPVersion == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support-&gt;LinkRateDoesNotMatchDPVersion);</div><div class='add'>+	if (!fail_only || support-&gt;LinkRateForMultistreamNotIndicated == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support-&gt;LinkRateForMultistreamNotIndicated);</div><div class='add'>+	if (!fail_only || support-&gt;BPPForMultistreamNotIndicated == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: BPPForMultistreamNotIndicated = %d\n", support-&gt;BPPForMultistreamNotIndicated);</div><div class='add'>+	if (!fail_only || support-&gt;MultistreamWithHDMIOreDP == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: MultistreamWithHDMIOreDP = %d\n", support-&gt;MultistreamWithHDMIOreDP);</div><div class='add'>+	if (!fail_only || support-&gt;ExceededMultistreamSlots == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ExceededMultistreamSlots = %d\n", support-&gt;ExceededMultistreamSlots);</div><div class='add'>+	if (!fail_only || support-&gt;MSOOrODMSplitWithNonDPLink == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support-&gt;MSOOrODMSplitWithNonDPLink);</div><div class='add'>+	if (!fail_only || support-&gt;NotEnoughLanesForMSO == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NotEnoughLanesForMSO = %d\n", support-&gt;NotEnoughLanesForMSO);</div><div class='add'>+	if (!fail_only || support-&gt;P2IWith420 == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: P2IWith420 = %d\n", support-&gt;P2IWith420);</div><div class='add'>+	if (!fail_only || support-&gt;DSC422NativeNotSupported == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DSC422NativeNotSupported = %d\n", support-&gt;DSC422NativeNotSupported);</div><div class='add'>+	if (!fail_only || support-&gt;DSCSlicesODMModeSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DSCSlicesODMModeSupported = %d\n", support-&gt;DSCSlicesODMModeSupported);</div><div class='add'>+	if (!fail_only || support-&gt;NotEnoughDSCUnits == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NotEnoughDSCUnits = %d\n", support-&gt;NotEnoughDSCUnits);</div><div class='add'>+	if (!fail_only || support-&gt;NotEnoughDSCSlices == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NotEnoughDSCSlices = %d\n", support-&gt;NotEnoughDSCSlices);</div><div class='add'>+	if (!fail_only || support-&gt;ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support-&gt;ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);</div><div class='add'>+	if (!fail_only || support-&gt;InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support-&gt;InvalidCombinationOfMALLUseForPStateAndStaticScreen);</div><div class='add'>+	if (!fail_only || support-&gt;DSCCLKRequiredMoreThanSupported == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support-&gt;DSCCLKRequiredMoreThanSupported);</div><div class='add'>+	if (!fail_only || support-&gt;PixelsPerLinePerDSCUnitSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support-&gt;PixelsPerLinePerDSCUnitSupport);</div><div class='add'>+	if (!fail_only || support-&gt;DTBCLKRequiredMoreThanSupported == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support-&gt;DTBCLKRequiredMoreThanSupported);</div><div class='add'>+	if (!fail_only || support-&gt;InvalidCombinationOfMALLUseForPState == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support-&gt;InvalidCombinationOfMALLUseForPState);</div><div class='add'>+	if (!fail_only || support-&gt;ROBSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ROBSupport = %d\n", support-&gt;ROBSupport);</div><div class='add'>+	if (!fail_only || support-&gt;OutstandingRequestsSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: OutstandingRequestsSupport = %d\n", support-&gt;OutstandingRequestsSupport);</div><div class='add'>+	if (!fail_only || support-&gt;OutstandingRequestsUrgencyAvoidance == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support-&gt;OutstandingRequestsUrgencyAvoidance);</div><div class='add'>+	if (!fail_only || support-&gt;DISPCLK_DPPCLK_Support == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DISPCLK_DPPCLK_Support = %d\n", support-&gt;DISPCLK_DPPCLK_Support);</div><div class='add'>+	if (!fail_only || support-&gt;TotalAvailablePipesSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: TotalAvailablePipesSupport = %d\n", support-&gt;TotalAvailablePipesSupport);</div><div class='add'>+	if (!fail_only || support-&gt;NumberOfOTGSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NumberOfOTGSupport = %d\n", support-&gt;NumberOfOTGSupport);</div><div class='add'>+	if (!fail_only || support-&gt;NumberOfHDMIFRLSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NumberOfHDMIFRLSupport = %d\n", support-&gt;NumberOfHDMIFRLSupport);</div><div class='add'>+	if (!fail_only || support-&gt;NumberOfDP2p0Support == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NumberOfDP2p0Support = %d\n", support-&gt;NumberOfDP2p0Support);</div><div class='add'>+	if (!fail_only || support-&gt;EnoughWritebackUnits == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: EnoughWritebackUnits = %d\n", support-&gt;EnoughWritebackUnits);</div><div class='add'>+	if (!fail_only || support-&gt;WritebackScaleRatioAndTapsSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support-&gt;WritebackScaleRatioAndTapsSupport);</div><div class='add'>+	if (!fail_only || support-&gt;WritebackLatencySupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: WritebackLatencySupport = %d\n", support-&gt;WritebackLatencySupport);</div><div class='add'>+	if (!fail_only || support-&gt;CursorSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: CursorSupport = %d\n", support-&gt;CursorSupport);</div><div class='add'>+	if (!fail_only || support-&gt;PitchSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PitchSupport = %d\n", support-&gt;PitchSupport);</div><div class='add'>+	if (!fail_only || support-&gt;ViewportExceedsSurface == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ViewportExceedsSurface = %d\n", support-&gt;ViewportExceedsSurface);</div><div class='add'>+	if (!fail_only || support-&gt;PrefetchSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PrefetchSupported = %d\n", support-&gt;PrefetchSupported);</div><div class='add'>+	if (!fail_only || support-&gt;EnoughUrgentLatencyHidingSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support-&gt;EnoughUrgentLatencyHidingSupport);</div><div class='add'>+	if (!fail_only || support-&gt;AvgBandwidthSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: AvgBandwidthSupport = %d\n", support-&gt;AvgBandwidthSupport);</div><div class='add'>+	if (!fail_only || support-&gt;DynamicMetadataSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DynamicMetadataSupported = %d\n", support-&gt;DynamicMetadataSupported);</div><div class='add'>+	if (!fail_only || support-&gt;VRatioInPrefetchSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: VRatioInPrefetchSupported = %d\n", support-&gt;VRatioInPrefetchSupported);</div><div class='add'>+	if (!fail_only || support-&gt;PTEBufferSizeNotExceeded == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PTEBufferSizeNotExceeded = %d\n", support-&gt;PTEBufferSizeNotExceeded);</div><div class='add'>+	if (!fail_only || support-&gt;DCCMetaBufferSizeNotExceeded == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support-&gt;DCCMetaBufferSizeNotExceeded);</div><div class='add'>+	if (!fail_only || support-&gt;ExceededMALLSize == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support-&gt;ExceededMALLSize);</div><div class='add'>+	if (!fail_only || support-&gt;g6_temp_read_support == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support-&gt;g6_temp_read_support);</div><div class='add'>+	if (!fail_only || support-&gt;ImmediateFlipSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support-&gt;ImmediateFlipSupport);</div><div class='add'>+	if (!fail_only || support-&gt;LinkCapacitySupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: LinkCapacitySupport = %d\n", support-&gt;LinkCapacitySupport);</div><div class='add'>+</div><div class='add'>+	if (!fail_only || support-&gt;ModeSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ModeSupport = %d\n", support-&gt;ModeSupport);</div><div class='add'>+	DML_LOG_VERBOSE("DML: ===================================== \n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg)</div><div class='add'>+{</div><div class='add'>+	for (unsigned int k = 0; k &lt; display_cfg-&gt;num_planes; k++) {</div><div class='add'>+		double bpc = (double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.bpc;</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {</div><div class='add'>+			switch (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format) {</div><div class='add'>+			case dml2_444:</div><div class='add'>+				out_bpp[k] = bpc * 3;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_s422:</div><div class='add'>+				out_bpp[k] = bpc * 2;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_n422:</div><div class='add'>+				out_bpp[k] = bpc * 2;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_420:</div><div class='add'>+			default:</div><div class='add'>+				out_bpp[k] = bpc * 1.5;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {</div><div class='add'>+			out_bpp[k] = (double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;</div><div class='add'>+		} else {</div><div class='add'>+			out_bpp[k] = 0;</div><div class='add'>+		}</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dml_round_to_multiple(unsigned int num, unsigned int multiple, bool up)</div><div class='add'>+{</div><div class='add'>+	unsigned int remainder;</div><div class='add'>+</div><div class='add'>+	if (multiple == 0)</div><div class='add'>+		return num;</div><div class='add'>+</div><div class='add'>+	remainder = num % multiple;</div><div class='add'>+	if (remainder == 0)</div><div class='add'>+		return num;</div><div class='add'>+</div><div class='add'>+	if (up)</div><div class='add'>+		return (num + multiple - remainder);</div><div class='add'>+	else</div><div class='add'>+		return (num - remainder);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dml_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_active_pipes = 0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; num_planes; k++) {</div><div class='add'>+		num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info-&gt;plane_support_info[k].dpps_used;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes);</div><div class='add'>+	return num_active_pipes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml_calc_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane)</div><div class='add'>+{</div><div class='add'>+	unsigned int pipe_idx = 0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; DML2_MAX_PLANES; ++k) {</div><div class='add'>+		pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int plane_idx = 0; plane_idx &lt; DML2_MAX_PLANES; plane_idx++) {</div><div class='add'>+		for (int i = 0; i &lt; cfg_support_info-&gt;plane_support_info[plane_idx].dpps_used; i++) {</div><div class='add'>+			pipe_plane[pipe_idx] = plane_idx;</div><div class='add'>+			pipe_idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg)</div><div class='add'>+{</div><div class='add'>+	bool is_phantom = false;</div><div class='add'>+</div><div class='add'>+	if (plane_cfg-&gt;overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe ||</div><div class='add'>+		plane_cfg-&gt;overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return) {</div><div class='add'>+		is_phantom = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return is_phantom;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml_get_is_phantom_pipe(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int pipe_idx)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_idx = mode_lib-&gt;mp.pipe_plane[pipe_idx];</div><div class='add'>+</div><div class='add'>+	bool is_phantom = dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[plane_idx]);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: pipe_idx=%d legacy_svp_config=%0d is_phantom=%d\n", __func__, pipe_idx, display_cfg-&gt;plane_descriptors[plane_idx].overrides.legacy_svp_config, is_phantom);</div><div class='add'>+	return is_phantom;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define dml_get_per_pipe_var_func(variable, type, interval_var) static type dml_get_##variable(const struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int pipe_idx) \</div><div class='add'>+{ \</div><div class='add'>+unsigned int plane_idx; \</div><div class='add'>+plane_idx = mode_lib-&gt;mp.pipe_plane[pipe_idx]; \</div><div class='add'>+return (type) interval_var[plane_idx]; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dml_get_per_pipe_var_func(dpte_group_size_in_bytes, unsigned int, mode_lib-&gt;mp.dpte_group_bytes);</div><div class='add'>+dml_get_per_pipe_var_func(vm_group_size_in_bytes, unsigned int, mode_lib-&gt;mp.vm_group_bytes);</div><div class='add'>+dml_get_per_pipe_var_func(swath_height_l, unsigned int, mode_lib-&gt;mp.SwathHeightY);</div><div class='add'>+dml_get_per_pipe_var_func(swath_height_c, unsigned int, mode_lib-&gt;mp.SwathHeightC);</div><div class='add'>+dml_get_per_pipe_var_func(dpte_row_height_linear_l, unsigned int, mode_lib-&gt;mp.dpte_row_height_linear);</div><div class='add'>+dml_get_per_pipe_var_func(dpte_row_height_linear_c, unsigned int, mode_lib-&gt;mp.dpte_row_height_linear_chroma);</div><div class='add'>+</div><div class='add'>+dml_get_per_pipe_var_func(vstartup_calculated, unsigned int, mode_lib-&gt;mp.VStartup);</div><div class='add'>+dml_get_per_pipe_var_func(vupdate_offset, unsigned int, mode_lib-&gt;mp.VUpdateOffsetPix);</div><div class='add'>+dml_get_per_pipe_var_func(vupdate_width, unsigned int, mode_lib-&gt;mp.VUpdateWidthPix);</div><div class='add'>+dml_get_per_pipe_var_func(vready_offset, unsigned int, mode_lib-&gt;mp.VReadyOffsetPix);</div><div class='add'>+dml_get_per_pipe_var_func(pstate_keepout_dst_lines, unsigned int, mode_lib-&gt;mp.pstate_keepout_dst_lines);</div><div class='add'>+dml_get_per_pipe_var_func(det_stored_buffer_size_l_bytes, unsigned int, mode_lib-&gt;mp.DETBufferSizeY);</div><div class='add'>+dml_get_per_pipe_var_func(det_stored_buffer_size_c_bytes, unsigned int, mode_lib-&gt;mp.DETBufferSizeC);</div><div class='add'>+dml_get_per_pipe_var_func(det_buffer_size_kbytes, unsigned int, mode_lib-&gt;mp.DETBufferSizeInKByte);</div><div class='add'>+dml_get_per_pipe_var_func(surface_size_in_mall_bytes, unsigned int, mode_lib-&gt;mp.SurfaceSizeInTheMALL);</div><div class='add'>+</div><div class='add'>+#define dml_get_per_plane_var_func(variable, type, interval_var) static type dml_get_plane_##variable(const struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int plane_idx) \</div><div class='add'>+{ \</div><div class='add'>+return (type) interval_var[plane_idx]; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dml_get_per_plane_var_func(num_mcaches_plane0, unsigned int, mode_lib-&gt;ms.num_mcaches_l);</div><div class='add'>+dml_get_per_plane_var_func(mcache_row_bytes_plane0, unsigned int, mode_lib-&gt;ms.mcache_row_bytes_l);</div><div class='add'>+dml_get_per_plane_var_func(mcache_shift_granularity_plane0, unsigned int, mode_lib-&gt;ms.mcache_shift_granularity_l);</div><div class='add'>+dml_get_per_plane_var_func(num_mcaches_plane1, unsigned int, mode_lib-&gt;ms.num_mcaches_c);</div><div class='add'>+dml_get_per_plane_var_func(mcache_row_bytes_plane1, unsigned int, mode_lib-&gt;ms.mcache_row_bytes_c);</div><div class='add'>+dml_get_per_plane_var_func(mcache_shift_granularity_plane1, unsigned int, mode_lib-&gt;ms.mcache_shift_granularity_c);</div><div class='add'>+dml_get_per_plane_var_func(mall_comb_mcache_l, unsigned int, mode_lib-&gt;ms.mall_comb_mcache_l);</div><div class='add'>+dml_get_per_plane_var_func(mall_comb_mcache_c, unsigned int, mode_lib-&gt;ms.mall_comb_mcache_c);</div><div class='add'>+dml_get_per_plane_var_func(lc_comb_mcache, unsigned int, mode_lib-&gt;ms.lc_comb_mcache);</div><div class='add'>+dml_get_per_plane_var_func(subviewport_lines_needed_in_mall, unsigned int, mode_lib-&gt;ms.SubViewportLinesNeededInMALL);</div><div class='add'>+dml_get_per_plane_var_func(max_vstartup_lines, unsigned int, mode_lib-&gt;ms.MaxVStartupLines);</div><div class='add'>+</div><div class='add'>+#define dml_get_per_plane_array_var_func(variable, type, interval_var) static type dml_get_plane_array_##variable(const struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int plane_idx, unsigned int array_idx) \</div><div class='add'>+{ \</div><div class='add'>+return (type) interval_var[plane_idx][array_idx]; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dml_get_per_plane_array_var_func(mcache_offsets_plane0, unsigned int, mode_lib-&gt;ms.mcache_offsets_l);</div><div class='add'>+dml_get_per_plane_array_var_func(mcache_offsets_plane1, unsigned int, mode_lib-&gt;ms.mcache_offsets_c);</div><div class='add'>+</div><div class='add'>+#define dml_get_var_func(var, type, internal_var) static type dml_get_##var(const struct dml2_core_internal_display_mode_lib *mode_lib) \</div><div class='add'>+{ \</div><div class='add'>+return (type) internal_var; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dml_get_var_func(wm_urgent, double, mode_lib-&gt;mp.Watermark.UrgentWatermark);</div><div class='add'>+dml_get_var_func(wm_stutter_exit, double, mode_lib-&gt;mp.Watermark.StutterExitWatermark);</div><div class='add'>+dml_get_var_func(wm_stutter_enter_exit, double, mode_lib-&gt;mp.Watermark.StutterEnterPlusExitWatermark);</div><div class='add'>+dml_get_var_func(wm_z8_stutter_exit, double, mode_lib-&gt;mp.Watermark.Z8StutterExitWatermark);</div><div class='add'>+dml_get_var_func(wm_z8_stutter_enter_exit, double, mode_lib-&gt;mp.Watermark.Z8StutterEnterPlusExitWatermark);</div><div class='add'>+dml_get_var_func(wm_memory_trip, double, mode_lib-&gt;mp.UrgentLatency);</div><div class='add'>+dml_get_var_func(meta_trip_memory_us, double, mode_lib-&gt;mp.MetaTripToMemory);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(wm_fclk_change, double, mode_lib-&gt;mp.Watermark.FCLKChangeWatermark);</div><div class='add'>+dml_get_var_func(wm_usr_retraining, double, mode_lib-&gt;mp.Watermark.USRRetrainingWatermark);</div><div class='add'>+dml_get_var_func(wm_temp_read_or_ppt, double, mode_lib-&gt;mp.Watermark.temp_read_or_ppt_watermark_us);</div><div class='add'>+dml_get_var_func(wm_dram_clock_change, double, mode_lib-&gt;mp.Watermark.DRAMClockChangeWatermark);</div><div class='add'>+dml_get_var_func(fraction_of_urgent_bandwidth, double, mode_lib-&gt;mp.FractionOfUrgentBandwidth);</div><div class='add'>+dml_get_var_func(fraction_of_urgent_bandwidth_imm_flip, double, mode_lib-&gt;mp.FractionOfUrgentBandwidthImmediateFlip);</div><div class='add'>+dml_get_var_func(fraction_of_urgent_bandwidth_mall, double, mode_lib-&gt;mp.FractionOfUrgentBandwidthMALL);</div><div class='add'>+dml_get_var_func(wm_writeback_dram_clock_change, double, mode_lib-&gt;mp.Watermark.WritebackDRAMClockChangeWatermark);</div><div class='add'>+dml_get_var_func(wm_writeback_fclk_change, double, mode_lib-&gt;mp.Watermark.WritebackFCLKChangeWatermark);</div><div class='add'>+dml_get_var_func(stutter_efficiency, double, mode_lib-&gt;mp.StutterEfficiency);</div><div class='add'>+dml_get_var_func(stutter_efficiency_no_vblank, double, mode_lib-&gt;mp.StutterEfficiencyNotIncludingVBlank);</div><div class='add'>+dml_get_var_func(stutter_num_bursts, double, mode_lib-&gt;mp.NumberOfStutterBurstsPerFrame);</div><div class='add'>+dml_get_var_func(stutter_efficiency_z8, double, mode_lib-&gt;mp.Z8StutterEfficiency);</div><div class='add'>+dml_get_var_func(stutter_num_bursts_z8, double, mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrame);</div><div class='add'>+dml_get_var_func(stutter_period, double, mode_lib-&gt;mp.StutterPeriod);</div><div class='add'>+dml_get_var_func(stutter_efficiency_z8_bestcase, double, mode_lib-&gt;mp.Z8StutterEfficiencyBestCase);</div><div class='add'>+dml_get_var_func(stutter_num_bursts_z8_bestcase, double, mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrameBestCase);</div><div class='add'>+dml_get_var_func(stutter_period_bestcase, double, mode_lib-&gt;mp.StutterPeriodBestCase);</div><div class='add'>+dml_get_var_func(fclk_change_latency, double, mode_lib-&gt;mp.MaxActiveFCLKChangeLatencySupported);</div><div class='add'>+dml_get_var_func(global_dppclk_khz, double, mode_lib-&gt;mp.GlobalDPPCLK * 1000.0);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_avg_bw_required_sdp, double, mode_lib-&gt;ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_avg_bw_required_dram, double, mode_lib-&gt;ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(svp_prefetch_avg_bw_required_sdp, double, mode_lib-&gt;ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_avg_bw_required_dram, double, mode_lib-&gt;ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_avg_bw_available_sdp, double, mode_lib-&gt;mp.avg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_avg_bw_available_dram, double, mode_lib-&gt;mp.avg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(svp_prefetch_avg_bw_available_sdp, double, mode_lib-&gt;mp.avg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_avg_bw_available_dram, double, mode_lib-&gt;mp.avg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_available_sdp, double, mode_lib-&gt;mp.urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_available_dram, double, mode_lib-&gt;mp.urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_available_dram_vm_only, double, mode_lib-&gt;mp.urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_sys_active]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_available_sdp, double, mode_lib-&gt;mp.urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_available_dram, double, mode_lib-&gt;mp.urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_available_dram_vm_only, double, mode_lib-&gt;mp.urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_svp_prefetch]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(urgent_latency, double, mode_lib-&gt;mp.UrgentLatency);</div><div class='add'>+dml_get_var_func(max_urgent_latency_us, double, mode_lib-&gt;ms.support.max_urgent_latency_us);</div><div class='add'>+dml_get_var_func(max_non_urgent_latency_us, double, mode_lib-&gt;ms.support.max_non_urgent_latency_us);</div><div class='add'>+dml_get_var_func(avg_non_urgent_latency_us, double, mode_lib-&gt;ms.support.avg_non_urgent_latency_us);</div><div class='add'>+dml_get_var_func(avg_urgent_latency_us, double, mode_lib-&gt;ms.support.avg_urgent_latency_us);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_required_sdp, double, mode_lib-&gt;mp.urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_required_dram, double, mode_lib-&gt;mp.urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_required_sdp, double, mode_lib-&gt;mp.urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_required_dram, double, mode_lib-&gt;mp.urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_non_urg_required_sdp, double, mode_lib-&gt;mp.non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_non_urg_required_dram, double, mode_lib-&gt;mp.non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+dml_get_var_func(svp_prefetch_non_urg_bw_required_sdp, double, mode_lib-&gt;mp.non_urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_non_urg_bw_required_dram, double, mode_lib-&gt;mp.non_urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_required_sdp_flip, double, mode_lib-&gt;mp.urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_urg_bw_required_dram_flip, double, mode_lib-&gt;mp.urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_required_sdp_flip, double, mode_lib-&gt;mp.urg_bandwidth_required_flip[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_urg_bw_required_dram_flip, double, mode_lib-&gt;mp.urg_bandwidth_required_flip[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(sys_active_non_urg_required_sdp_flip, double, mode_lib-&gt;mp.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(sys_active_non_urg_required_dram_flip, double, mode_lib-&gt;mp.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+dml_get_var_func(svp_prefetch_non_urg_bw_required_sdp_flip, double, mode_lib-&gt;mp.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+dml_get_var_func(svp_prefetch_non_urg_bw_required_dram_flip, double, mode_lib-&gt;mp.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(comp_buffer_size_kbytes, unsigned int, mode_lib-&gt;mp.CompressedBufferSizeInkByte);</div><div class='add'>+</div><div class='add'>+dml_get_var_func(unbounded_request_enabled, bool, mode_lib-&gt;mp.UnboundedRequestEnabled);</div><div class='add'>+dml_get_var_func(wm_writeback_urgent, double, mode_lib-&gt;mp.Watermark.WritebackUrgentWatermark);</div><div class='add'>+dml_get_var_func(cstate_max_cap_mode, bool, mode_lib-&gt;mp.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);</div><div class='add'>+dml_get_var_func(compbuf_reserved_space_64b, unsigned int, mode_lib-&gt;mp.compbuf_reserved_space_64b);</div><div class='add'>+dml_get_var_func(hw_debug5, bool, mode_lib-&gt;mp.hw_debug5);</div><div class='add'>+dml_get_var_func(dcfclk_deep_sleep_hysteresis, unsigned int, mode_lib-&gt;mp.dcfclk_deep_sleep_hysteresis);</div><div class='add'>+</div><div class='add'>+static void CalculateMaxDETAndMinCompressedBufferSize(</div><div class='add'>+	unsigned int ConfigReturnBufferSizeInKByte,</div><div class='add'>+	unsigned int ConfigReturnBufferSegmentSizeInKByte,</div><div class='add'>+	unsigned int ROBBufferSizeInKByte,</div><div class='add'>+	unsigned int MaxNumDPP,</div><div class='add'>+	unsigned int nomDETInKByteOverrideEnable, // VBA_DELTA, allow DV to override default DET size</div><div class='add'>+	unsigned int nomDETInKByteOverrideValue, // VBA_DELTA</div><div class='add'>+	bool is_mrq_present,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int *MaxTotalDETInKByte,</div><div class='add'>+	unsigned int *nomDETInKByte,</div><div class='add'>+	unsigned int *MinCompressedBufferSizeInKByte)</div><div class='add'>+{</div><div class='add'>+	if (is_mrq_present)</div><div class='add'>+		*MaxTotalDETInKByte = (unsigned int) math_ceil2((double)(ConfigReturnBufferSizeInKByte + ROBBufferSizeInKByte)*4/5, 64);</div><div class='add'>+	else</div><div class='add'>+		*MaxTotalDETInKByte = ConfigReturnBufferSizeInKByte - ConfigReturnBufferSegmentSizeInKByte;</div><div class='add'>+</div><div class='add'>+	*nomDETInKByte = (unsigned int)(math_floor2((double)*MaxTotalDETInKByte / (double)MaxNumDPP, ConfigReturnBufferSegmentSizeInKByte));</div><div class='add'>+	*MinCompressedBufferSizeInKByte = ConfigReturnBufferSizeInKByte - *MaxTotalDETInKByte;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: is_mrq_present = %u\n", __func__, is_mrq_present);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ConfigReturnBufferSizeInKByte = %u\n", __func__, ConfigReturnBufferSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ROBBufferSizeInKByte = %u\n", __func__, ROBBufferSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxNumDPP = %u\n", __func__, MaxNumDPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxTotalDETInKByte = %u\n", __func__, *MaxTotalDETInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: nomDETInKByte = %u\n", __func__, *nomDETInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MinCompressedBufferSizeInKByte = %u\n", __func__, *MinCompressedBufferSizeInKByte);</div><div class='add'>+</div><div class='add'>+	if (nomDETInKByteOverrideEnable) {</div><div class='add'>+		*nomDETInKByte = nomDETInKByteOverrideValue;</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: nomDETInKByte = %u (overrided)\n", __func__, *nomDETInKByte);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void PixelClockAdjustmentForProgressiveToInterlaceUnit(const struct dml2_display_cfg *display_cfg, bool ptoi_supported, double *PixelClockBackEnd)</div><div class='add'>+{</div><div class='add'>+	//unsigned int num_active_planes = display_cfg-&gt;num_planes;</div><div class='add'>+</div><div class='add'>+	//Progressive To Interlace Unit Effect</div><div class='add'>+	for (unsigned int k = 0; k &lt; display_cfg-&gt;num_planes; ++k) {</div><div class='add'>+		PixelClockBackEnd[k] = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced == 1 &amp;&amp; ptoi_supported == true) {</div><div class='add'>+			// FIXME_STAGE2... can sw pass the pixel rate for interlaced directly</div><div class='add'>+			//display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz = 2 * display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml_is_420(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	bool val = false;</div><div class='add'>+</div><div class='add'>+	switch (source_format) {</div><div class='add'>+	case dml2_444_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_32:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_64:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_8:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_10:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_12:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe_alpha:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dml_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode)</div><div class='add'>+{</div><div class='add'>+	if (sw_mode == dml2_sw_linear)</div><div class='add'>+		return 256;</div><div class='add'>+	else if (sw_mode == dml2_sw_256b_2d)</div><div class='add'>+		return 256;</div><div class='add'>+	else if (sw_mode == dml2_sw_4kb_2d)</div><div class='add'>+		return 4096;</div><div class='add'>+	else if (sw_mode == dml2_sw_64kb_2d)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_sw_256kb_2d)</div><div class='add'>+		return 262144;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_linear)</div><div class='add'>+		return 256;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_d)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_d_t)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_d_x)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_r_x)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_256kb_d_x)</div><div class='add'>+		return 262144;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_256kb_r_x)</div><div class='add'>+		return 262144;</div><div class='add'>+	else {</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+		return 256;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml_is_vertical_rotation(enum dml2_rotation_angle Scan)</div><div class='add'>+{</div><div class='add'>+	bool is_vert = false;</div><div class='add'>+	if (Scan == dml2_rotation_90 || Scan == dml2_rotation_270) {</div><div class='add'>+		is_vert = true;</div><div class='add'>+	} else {</div><div class='add'>+		is_vert = false;</div><div class='add'>+	}</div><div class='add'>+	return is_vert;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int unsigned dml_get_gfx_version(enum dml2_swizzle_mode sw_mode)</div><div class='add'>+{</div><div class='add'>+	int unsigned version = 0;</div><div class='add'>+</div><div class='add'>+	if (sw_mode == dml2_sw_linear ||</div><div class='add'>+		sw_mode == dml2_sw_256b_2d ||</div><div class='add'>+		sw_mode == dml2_sw_4kb_2d ||</div><div class='add'>+		sw_mode == dml2_sw_64kb_2d ||</div><div class='add'>+		sw_mode == dml2_sw_256kb_2d) {</div><div class='add'>+		version = 12;</div><div class='add'>+	} else if (sw_mode == dml2_gfx11_sw_linear ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_d ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_d_t ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_d_x ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_r_x ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_256kb_d_x ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_256kb_r_x) {</div><div class='add'>+		version = 11;</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode);</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return version;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateBytePerPixelAndBlockSizes(</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat,</div><div class='add'>+	enum dml2_swizzle_mode SurfaceTiling,</div><div class='add'>+	unsigned int pitch_y,</div><div class='add'>+	unsigned int pitch_c,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int *BytePerPixelY,</div><div class='add'>+	unsigned int *BytePerPixelC,</div><div class='add'>+	double *BytePerPixelDETY,</div><div class='add'>+	double *BytePerPixelDETC,</div><div class='add'>+	unsigned int *BlockHeight256BytesY,</div><div class='add'>+	unsigned int *BlockHeight256BytesC,</div><div class='add'>+	unsigned int *BlockWidth256BytesY,</div><div class='add'>+	unsigned int *BlockWidth256BytesC,</div><div class='add'>+	unsigned int *MacroTileHeightY,</div><div class='add'>+	unsigned int *MacroTileHeightC,</div><div class='add'>+	unsigned int *MacroTileWidthY,</div><div class='add'>+	unsigned int *MacroTileWidthC,</div><div class='add'>+	bool *surf_linear128_l,</div><div class='add'>+	bool *surf_linear128_c)</div><div class='add'>+{</div><div class='add'>+	*BytePerPixelDETY = 0;</div><div class='add'>+	*BytePerPixelDETC = 0;</div><div class='add'>+	*BytePerPixelY = 1;</div><div class='add'>+	*BytePerPixelC = 1;</div><div class='add'>+</div><div class='add'>+	if (SourcePixelFormat == dml2_444_64) {</div><div class='add'>+		*BytePerPixelDETY = 8;</div><div class='add'>+		*BytePerPixelDETC = 0;</div><div class='add'>+		*BytePerPixelY = 8;</div><div class='add'>+		*BytePerPixelC = 0;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_444_32 || SourcePixelFormat == dml2_rgbe) {</div><div class='add'>+		*BytePerPixelDETY = 4;</div><div class='add'>+		*BytePerPixelDETC = 0;</div><div class='add'>+		*BytePerPixelY = 4;</div><div class='add'>+		*BytePerPixelC = 0;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_444_16 || SourcePixelFormat == dml2_mono_16) {</div><div class='add'>+		*BytePerPixelDETY = 2;</div><div class='add'>+		*BytePerPixelDETC = 0;</div><div class='add'>+		*BytePerPixelY = 2;</div><div class='add'>+		*BytePerPixelC = 0;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_444_8 || SourcePixelFormat == dml2_mono_8) {</div><div class='add'>+		*BytePerPixelDETY = 1;</div><div class='add'>+		*BytePerPixelDETC = 0;</div><div class='add'>+		*BytePerPixelY = 1;</div><div class='add'>+		*BytePerPixelC = 0;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_rgbe_alpha) {</div><div class='add'>+		*BytePerPixelDETY = 4;</div><div class='add'>+		*BytePerPixelDETC = 1;</div><div class='add'>+		*BytePerPixelY = 4;</div><div class='add'>+		*BytePerPixelC = 1;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_420_8) {</div><div class='add'>+		*BytePerPixelDETY = 1;</div><div class='add'>+		*BytePerPixelDETC = 2;</div><div class='add'>+		*BytePerPixelY = 1;</div><div class='add'>+		*BytePerPixelC = 2;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_420_12) {</div><div class='add'>+		*BytePerPixelDETY = 2;</div><div class='add'>+		*BytePerPixelDETC = 4;</div><div class='add'>+		*BytePerPixelY = 2;</div><div class='add'>+		*BytePerPixelC = 4;</div><div class='add'>+	} else if (SourcePixelFormat == dml2_420_10) {</div><div class='add'>+		*BytePerPixelDETY = (double)(4.0 / 3);</div><div class='add'>+		*BytePerPixelDETC = (double)(8.0 / 3);</div><div class='add'>+		*BytePerPixelY = 2;</div><div class='add'>+		*BytePerPixelC = 4;</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("ERROR: DML::%s: SourcePixelFormat = %u not supported!\n", __func__, SourcePixelFormat);</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SourcePixelFormat = %u\n", __func__, SourcePixelFormat);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelDETY = %f\n", __func__, *BytePerPixelDETY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelDETC = %f\n", __func__, *BytePerPixelDETC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelY = %u\n", __func__, *BytePerPixelY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelC = %u\n", __func__, *BytePerPixelC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: pitch_y = %u\n", __func__, pitch_y);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: pitch_c = %u\n", __func__, pitch_c);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: surf_linear128_l = %u\n", __func__, *surf_linear128_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: surf_linear128_c = %u\n", __func__, *surf_linear128_c);</div><div class='add'>+</div><div class='add'>+	if (dml_get_gfx_version(SurfaceTiling) == 11) {</div><div class='add'>+		*surf_linear128_l = 0;</div><div class='add'>+		*surf_linear128_c = 0;</div><div class='add'>+	} else {</div><div class='add'>+		if (SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+			*surf_linear128_l = (((pitch_y * *BytePerPixelY) % 256) != 0);</div><div class='add'>+</div><div class='add'>+			if (dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha)</div><div class='add'>+				*surf_linear128_c = (((pitch_c * *BytePerPixelC) % 256) != 0);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!(dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha)) {</div><div class='add'>+		if (SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+			*BlockHeight256BytesY = 1;</div><div class='add'>+		} else if (SourcePixelFormat == dml2_444_64) {</div><div class='add'>+			*BlockHeight256BytesY = 4;</div><div class='add'>+		} else if (SourcePixelFormat == dml2_444_8) {</div><div class='add'>+			*BlockHeight256BytesY = 16;</div><div class='add'>+		} else {</div><div class='add'>+			*BlockHeight256BytesY = 8;</div><div class='add'>+		}</div><div class='add'>+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;</div><div class='add'>+		*BlockHeight256BytesC = 0;</div><div class='add'>+		*BlockWidth256BytesC = 0;</div><div class='add'>+	} else { // dual plane</div><div class='add'>+		if (SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+			*BlockHeight256BytesY = 1;</div><div class='add'>+			*BlockHeight256BytesC = 1;</div><div class='add'>+		} else if (SourcePixelFormat == dml2_rgbe_alpha) {</div><div class='add'>+			*BlockHeight256BytesY = 8;</div><div class='add'>+			*BlockHeight256BytesC = 16;</div><div class='add'>+		} else if (SourcePixelFormat == dml2_420_8) {</div><div class='add'>+			*BlockHeight256BytesY = 16;</div><div class='add'>+			*BlockHeight256BytesC = 8;</div><div class='add'>+		} else {</div><div class='add'>+			*BlockHeight256BytesY = 8;</div><div class='add'>+			*BlockHeight256BytesC = 8;</div><div class='add'>+		}</div><div class='add'>+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;</div><div class='add'>+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BlockWidth256BytesY = %u\n", __func__, *BlockWidth256BytesY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BlockHeight256BytesY = %u\n", __func__, *BlockHeight256BytesY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BlockWidth256BytesC = %u\n", __func__, *BlockWidth256BytesC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BlockHeight256BytesC = %u\n", __func__, *BlockHeight256BytesC);</div><div class='add'>+</div><div class='add'>+	if (dml_get_gfx_version(SurfaceTiling) == 11) {</div><div class='add'>+		if (SurfaceTiling == dml2_gfx11_sw_linear) {</div><div class='add'>+			*MacroTileHeightY = *BlockHeight256BytesY;</div><div class='add'>+			*MacroTileWidthY = 256 / *BytePerPixelY / *MacroTileHeightY;</div><div class='add'>+			*MacroTileHeightC = *BlockHeight256BytesC;</div><div class='add'>+			if (*MacroTileHeightC == 0) {</div><div class='add'>+				*MacroTileWidthC = 0;</div><div class='add'>+			} else {</div><div class='add'>+				*MacroTileWidthC = 256 / *BytePerPixelC / *MacroTileHeightC;</div><div class='add'>+			}</div><div class='add'>+		} else if (SurfaceTiling == dml2_gfx11_sw_64kb_d || SurfaceTiling == dml2_gfx11_sw_64kb_d_t || SurfaceTiling == dml2_gfx11_sw_64kb_d_x || SurfaceTiling == dml2_gfx11_sw_64kb_r_x) {</div><div class='add'>+			*MacroTileHeightY = 16 * *BlockHeight256BytesY;</div><div class='add'>+			*MacroTileWidthY = 65536 / *BytePerPixelY / *MacroTileHeightY;</div><div class='add'>+			*MacroTileHeightC = 16 * *BlockHeight256BytesC;</div><div class='add'>+			if (*MacroTileHeightC == 0) {</div><div class='add'>+				*MacroTileWidthC = 0;</div><div class='add'>+			} else {</div><div class='add'>+				*MacroTileWidthC = 65536 / *BytePerPixelC / *MacroTileHeightC;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			*MacroTileHeightY = 32 * *BlockHeight256BytesY;</div><div class='add'>+			*MacroTileWidthY = 65536 * 4 / *BytePerPixelY / *MacroTileHeightY;</div><div class='add'>+			*MacroTileHeightC = 32 * *BlockHeight256BytesC;</div><div class='add'>+			if (*MacroTileHeightC == 0) {</div><div class='add'>+				*MacroTileWidthC = 0;</div><div class='add'>+			} else {</div><div class='add'>+				*MacroTileWidthC = 65536 * 4 / *BytePerPixelC / *MacroTileHeightC;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		unsigned int macro_tile_size_bytes = dml_get_tile_block_size_bytes(SurfaceTiling);</div><div class='add'>+		unsigned int macro_tile_scale = 1; // macro tile to 256B req scaling</div><div class='add'>+</div><div class='add'>+		if (SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+			macro_tile_scale = 1;</div><div class='add'>+		} else if (SurfaceTiling == dml2_sw_4kb_2d) {</div><div class='add'>+			macro_tile_scale = 4;</div><div class='add'>+		} else if (SurfaceTiling == dml2_sw_64kb_2d) {</div><div class='add'>+			macro_tile_scale = 16;</div><div class='add'>+		} else if (SurfaceTiling == dml2_sw_256kb_2d) {</div><div class='add'>+			macro_tile_scale = 32;</div><div class='add'>+		} else {</div><div class='add'>+			DML_LOG_VERBOSE("ERROR: Invalid SurfaceTiling setting! val=%u\n", SurfaceTiling);</div><div class='add'>+			DML_ASSERT(0);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*MacroTileHeightY = macro_tile_scale * *BlockHeight256BytesY;</div><div class='add'>+		*MacroTileWidthY = macro_tile_size_bytes / *BytePerPixelY / *MacroTileHeightY;</div><div class='add'>+		*MacroTileHeightC = macro_tile_scale * *BlockHeight256BytesC;</div><div class='add'>+		if (*MacroTileHeightC == 0) {</div><div class='add'>+			*MacroTileWidthC = 0;</div><div class='add'>+		} else {</div><div class='add'>+			*MacroTileWidthC = macro_tile_size_bytes / *BytePerPixelC / *MacroTileHeightC;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MacroTileWidthY = %u\n", __func__, *MacroTileWidthY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MacroTileHeightY = %u\n", __func__, *MacroTileHeightY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MacroTileWidthC = %u\n", __func__, *MacroTileWidthC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MacroTileHeightC = %u\n", __func__, *MacroTileHeightC);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateSinglePipeDPPCLKAndSCLThroughput(</div><div class='add'>+	double HRatio,</div><div class='add'>+	double HRatioChroma,</div><div class='add'>+	double VRatio,</div><div class='add'>+	double VRatioChroma,</div><div class='add'>+	double MaxDCHUBToPSCLThroughput,</div><div class='add'>+	double MaxPSCLToLBThroughput,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat,</div><div class='add'>+	unsigned int HTaps,</div><div class='add'>+	unsigned int HTapsChroma,</div><div class='add'>+	unsigned int VTaps,</div><div class='add'>+	unsigned int VTapsChroma,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *PSCL_THROUGHPUT,</div><div class='add'>+	double *PSCL_THROUGHPUT_CHROMA,</div><div class='add'>+	double *DPPCLKUsingSingleDPP)</div><div class='add'>+{</div><div class='add'>+	double DPPCLKUsingSingleDPPLuma;</div><div class='add'>+	double DPPCLKUsingSingleDPPChroma;</div><div class='add'>+</div><div class='add'>+	if (HRatio &gt; 1) {</div><div class='add'>+		*PSCL_THROUGHPUT = math_min2(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatio / math_ceil2((double)HTaps / 6.0, 1.0));</div><div class='add'>+	} else {</div><div class='add'>+		*PSCL_THROUGHPUT = math_min2(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DPPCLKUsingSingleDPPLuma = PixelClock * math_max3(VTaps / 6 * math_min2(1, HRatio), HRatio * VRatio / *PSCL_THROUGHPUT, 1);</div><div class='add'>+</div><div class='add'>+	if ((HTaps &gt; 6 || VTaps &gt; 6) &amp;&amp; DPPCLKUsingSingleDPPLuma &lt; 2 * PixelClock)</div><div class='add'>+		DPPCLKUsingSingleDPPLuma = 2 * PixelClock;</div><div class='add'>+</div><div class='add'>+	if (!dml_is_420(SourcePixelFormat) &amp;&amp; SourcePixelFormat != dml2_rgbe_alpha) {</div><div class='add'>+		*PSCL_THROUGHPUT_CHROMA = 0;</div><div class='add'>+		*DPPCLKUsingSingleDPP = DPPCLKUsingSingleDPPLuma;</div><div class='add'>+	} else {</div><div class='add'>+		if (HRatioChroma &gt; 1) {</div><div class='add'>+			*PSCL_THROUGHPUT_CHROMA = math_min2(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput * HRatioChroma / math_ceil2((double)HTapsChroma / 6.0, 1.0));</div><div class='add'>+		} else {</div><div class='add'>+			*PSCL_THROUGHPUT_CHROMA = math_min2(MaxDCHUBToPSCLThroughput, MaxPSCLToLBThroughput);</div><div class='add'>+		}</div><div class='add'>+		DPPCLKUsingSingleDPPChroma = PixelClock * math_max3(VTapsChroma / 6 * math_min2(1, HRatioChroma),</div><div class='add'>+			HRatioChroma * VRatioChroma / *PSCL_THROUGHPUT_CHROMA, 1);</div><div class='add'>+		if ((HTapsChroma &gt; 6 || VTapsChroma &gt; 6) &amp;&amp; DPPCLKUsingSingleDPPChroma &lt; 2 * PixelClock)</div><div class='add'>+			DPPCLKUsingSingleDPPChroma = 2 * PixelClock;</div><div class='add'>+		*DPPCLKUsingSingleDPP = math_max2(DPPCLKUsingSingleDPPLuma, DPPCLKUsingSingleDPPChroma);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateSwathWidth(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	bool ForceSingleDPP,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	enum dml2_odm_mode ODMMode[],</div><div class='add'>+	unsigned int BytePerPixY[],</div><div class='add'>+	unsigned int BytePerPixC[],</div><div class='add'>+	unsigned int Read256BytesBlockHeightY[],</div><div class='add'>+	unsigned int Read256BytesBlockHeightC[],</div><div class='add'>+	unsigned int Read256BytesBlockWidthY[],</div><div class='add'>+	unsigned int Read256BytesBlockWidthC[],</div><div class='add'>+	bool surf_linear128_l[],</div><div class='add'>+	bool surf_linear128_c[],</div><div class='add'>+	unsigned int DPPPerSurface[],</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int req_per_swath_ub_l[],</div><div class='add'>+	unsigned int req_per_swath_ub_c[],</div><div class='add'>+	unsigned int SwathWidthSingleDPPY[], // post-rotated plane width</div><div class='add'>+	unsigned int SwathWidthSingleDPPC[],</div><div class='add'>+	unsigned int SwathWidthY[], // per-pipe</div><div class='add'>+	unsigned int SwathWidthC[], // per-pipe</div><div class='add'>+	unsigned int MaximumSwathHeightY[],</div><div class='add'>+	unsigned int MaximumSwathHeightC[],</div><div class='add'>+	unsigned int swath_width_luma_ub[], // per-pipe</div><div class='add'>+	unsigned int swath_width_chroma_ub[]) // per-pipe</div><div class='add'>+{</div><div class='add'>+	enum dml2_odm_mode MainSurfaceODMMode;</div><div class='add'>+	double odm_hactive_factor = 1.0;</div><div class='add'>+	unsigned int req_width_horz_y;</div><div class='add'>+	unsigned int req_width_horz_c;</div><div class='add'>+	unsigned int surface_width_ub_l;</div><div class='add'>+	unsigned int surface_height_ub_l;</div><div class='add'>+	unsigned int surface_width_ub_c;</div><div class='add'>+	unsigned int surface_height_ub_c;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ForceSingleDPP = %u\n", __func__, ForceSingleDPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfActiveSurfaces = %u\n", __func__, NumberOfActiveSurfaces);</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (!dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+			SwathWidthSingleDPPY[k] = (unsigned int)display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width;</div><div class='add'>+		} else {</div><div class='add'>+			SwathWidthSingleDPPY[k] = (unsigned int)display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth=%lu\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight=%lu\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);</div><div class='add'>+</div><div class='add'>+		MainSurfaceODMMode = ODMMode[k];</div><div class='add'>+</div><div class='add'>+		if (ForceSingleDPP) {</div><div class='add'>+			SwathWidthY[k] = SwathWidthSingleDPPY[k];</div><div class='add'>+		} else {</div><div class='add'>+			if (MainSurfaceODMMode == dml2_odm_mode_combine_4to1)</div><div class='add'>+				odm_hactive_factor = 4.0;</div><div class='add'>+			else if (MainSurfaceODMMode == dml2_odm_mode_combine_3to1)</div><div class='add'>+				odm_hactive_factor = 3.0;</div><div class='add'>+			else if (MainSurfaceODMMode == dml2_odm_mode_combine_2to1)</div><div class='add'>+				odm_hactive_factor = 2.0;</div><div class='add'>+</div><div class='add'>+			if (MainSurfaceODMMode == dml2_odm_mode_combine_4to1 || MainSurfaceODMMode == dml2_odm_mode_combine_3to1 || MainSurfaceODMMode == dml2_odm_mode_combine_2to1) {</div><div class='add'>+				SwathWidthY[k] = (unsigned int)(math_min2((double)SwathWidthSingleDPPY[k], math_round((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active / odm_hactive_factor * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio)));</div><div class='add'>+			} else if (DPPPerSurface[k] == 2) {</div><div class='add'>+				SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;</div><div class='add'>+			} else {</div><div class='add'>+				SwathWidthY[k] = SwathWidthSingleDPPY[k];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u HRatio=%f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MainSurfaceODMMode=%u\n", __func__, k, MainSurfaceODMMode);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthSingleDPPY=%u\n", __func__, k, SwathWidthSingleDPPY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthY=%u\n", __func__, k, SwathWidthY[k]);</div><div class='add'>+</div><div class='add'>+		if (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format)) {</div><div class='add'>+			SwathWidthC[k] = SwathWidthY[k] / 2;</div><div class='add'>+			SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;</div><div class='add'>+		} else {</div><div class='add'>+			SwathWidthC[k] = SwathWidthY[k];</div><div class='add'>+			SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ForceSingleDPP == true) {</div><div class='add'>+			SwathWidthY[k] = SwathWidthSingleDPPY[k];</div><div class='add'>+			SwathWidthC[k] = SwathWidthSingleDPPC[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		req_width_horz_y = Read256BytesBlockWidthY[k];</div><div class='add'>+		req_width_horz_c = Read256BytesBlockWidthC[k];</div><div class='add'>+</div><div class='add'>+		if (surf_linear128_l[k])</div><div class='add'>+			req_width_horz_y = req_width_horz_y / 2;</div><div class='add'>+</div><div class='add'>+		if (surf_linear128_c[k])</div><div class='add'>+			req_width_horz_c = req_width_horz_c / 2;</div><div class='add'>+</div><div class='add'>+		surface_width_ub_l = (unsigned int)math_ceil2((double)display_cfg-&gt;plane_descriptors[k].surface.plane0.width, req_width_horz_y);</div><div class='add'>+		surface_height_ub_l = (unsigned int)math_ceil2((double)display_cfg-&gt;plane_descriptors[k].surface.plane0.height, Read256BytesBlockHeightY[k]);</div><div class='add'>+		surface_width_ub_c = (unsigned int)math_ceil2((double)display_cfg-&gt;plane_descriptors[k].surface.plane1.width, req_width_horz_c);</div><div class='add'>+		surface_height_ub_c = (unsigned int)math_ceil2((double)display_cfg-&gt;plane_descriptors[k].surface.plane1.height, Read256BytesBlockHeightC[k]);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u surface_width_ub_l=%u\n", __func__, k, surface_width_ub_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u surface_height_ub_l=%u\n", __func__, k, surface_height_ub_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u surface_width_ub_c=%u\n", __func__, k, surface_width_ub_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u surface_height_ub_c=%u\n", __func__, k, surface_height_ub_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_y=%u\n", __func__, k, req_width_horz_y);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_c=%u\n", __func__, k, req_width_horz_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockWidthY=%u\n", __func__, k, Read256BytesBlockWidthY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockHeightY=%u\n", __func__, k, Read256BytesBlockHeightY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockWidthC=%u\n", __func__, k, Read256BytesBlockWidthC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockHeightC=%u\n", __func__, k, Read256BytesBlockHeightC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_y=%u\n", __func__, k, req_width_horz_y);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_c=%u\n", __func__, k, req_width_horz_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u ViewportStationary=%u\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);</div><div class='add'>+</div><div class='add'>+		req_per_swath_ub_l[k] = 0;</div><div class='add'>+		req_per_swath_ub_c[k] = 0;</div><div class='add'>+		if (!dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+			MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];</div><div class='add'>+			MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary &amp;&amp; DPPPerSurface[k] == 1) {</div><div class='add'>+				swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_width_ub_l, math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.x_start + SwathWidthY[k] + req_width_horz_y - 1, req_width_horz_y) - math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.x_start, req_width_horz_y)));</div><div class='add'>+			} else {</div><div class='add'>+				swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_width_ub_l, math_ceil2((double)SwathWidthY[k] - 1, req_width_horz_y) + req_width_horz_y));</div><div class='add'>+			}</div><div class='add'>+			req_per_swath_ub_l[k] = swath_width_luma_ub[k] / req_width_horz_y;</div><div class='add'>+</div><div class='add'>+			if (BytePerPixC[k] &gt; 0) {</div><div class='add'>+				if (display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary &amp;&amp; DPPPerSurface[k] == 1) {</div><div class='add'>+					swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_width_ub_c, math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start + SwathWidthC[k] + req_width_horz_c - 1, req_width_horz_c) - math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start, req_width_horz_c)));</div><div class='add'>+				} else {</div><div class='add'>+					swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_width_ub_c, math_ceil2((double)SwathWidthC[k] - 1, req_width_horz_c) + req_width_horz_c));</div><div class='add'>+				}</div><div class='add'>+				req_per_swath_ub_c[k] = swath_width_chroma_ub[k] / req_width_horz_c;</div><div class='add'>+			} else {</div><div class='add'>+				swath_width_chroma_ub[k] = 0;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];</div><div class='add'>+			MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary &amp;&amp; DPPPerSurface[k] == 1) {</div><div class='add'>+				swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_height_ub_l, math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.y_start + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.y_start, Read256BytesBlockHeightY[k])));</div><div class='add'>+			} else {</div><div class='add'>+				swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_height_ub_l, math_ceil2((double)SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));</div><div class='add'>+			}</div><div class='add'>+			req_per_swath_ub_l[k] = swath_width_luma_ub[k] / Read256BytesBlockHeightY[k];</div><div class='add'>+			if (BytePerPixC[k] &gt; 0) {</div><div class='add'>+				if (display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary &amp;&amp; DPPPerSurface[k] == 1) {</div><div class='add'>+					swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_height_ub_c, math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - math_floor2(display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start, Read256BytesBlockHeightC[k])));</div><div class='add'>+				} else {</div><div class='add'>+					swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_height_ub_c, math_ceil2((double)SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));</div><div class='add'>+				}</div><div class='add'>+				req_per_swath_ub_c[k] = swath_width_chroma_ub[k] / Read256BytesBlockHeightC[k];</div><div class='add'>+			} else {</div><div class='add'>+				swath_width_chroma_ub[k] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u swath_width_luma_ub=%u\n", __func__, k, swath_width_luma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u swath_width_chroma_ub=%u\n", __func__, k, swath_width_chroma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightY=%u\n", __func__, k, MaximumSwathHeightY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightC=%u\n", __func__, k, MaximumSwathHeightC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u req_per_swath_ub_l=%u\n", __func__, k, req_per_swath_ub_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u req_per_swath_ub_c=%u\n", __func__, k, req_per_swath_ub_c[k]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool UnboundedRequest(bool unb_req_force_en, bool unb_req_force_val, unsigned int TotalNumberOfActiveDPP, bool NoChromaOrLinear)</div><div class='add'>+{</div><div class='add'>+	bool unb_req_ok = false;</div><div class='add'>+	bool unb_req_en = false;</div><div class='add'>+</div><div class='add'>+	unb_req_ok = (TotalNumberOfActiveDPP == 1 &amp;&amp; NoChromaOrLinear);</div><div class='add'>+	unb_req_en = unb_req_ok;</div><div class='add'>+</div><div class='add'>+	if (unb_req_force_en) {</div><div class='add'>+		unb_req_en = unb_req_force_val &amp;&amp; unb_req_ok;</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: unb_req_force_en = %u\n", __func__, unb_req_force_en);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: unb_req_force_val = %u\n", __func__, unb_req_force_val);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: unb_req_ok = %u\n", __func__, unb_req_ok);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: unb_req_en = %u\n", __func__, unb_req_en);</div><div class='add'>+	return unb_req_en;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateDETBufferSize(</div><div class='add'>+	struct dml2_core_shared_CalculateDETBufferSize_locals *l,</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	bool ForceSingleDPP,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	bool UnboundedRequestEnabled,</div><div class='add'>+	unsigned int nomDETInKByte,</div><div class='add'>+	unsigned int MaxTotalDETInKByte,</div><div class='add'>+	unsigned int ConfigReturnBufferSizeInKByte,</div><div class='add'>+	unsigned int MinCompressedBufferSizeInKByte,</div><div class='add'>+	unsigned int ConfigReturnBufferSegmentSizeInkByte,</div><div class='add'>+	unsigned int CompressedBufferSegmentSizeInkByte,</div><div class='add'>+	double ReadBandwidthLuma[],</div><div class='add'>+	double ReadBandwidthChroma[],</div><div class='add'>+	unsigned int full_swath_bytes_l[],</div><div class='add'>+	unsigned int full_swath_bytes_c[],</div><div class='add'>+	unsigned int DPPPerSurface[],</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int DETBufferSizeInKByte[],</div><div class='add'>+	unsigned int *CompressedBufferSizeInkByte)</div><div class='add'>+{</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_core_shared_CalculateDETBufferSize_locals));</div><div class='add'>+</div><div class='add'>+	bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES];</div><div class='add'>+	bool NextPotentialSurfaceToAssignDETPieceFound;</div><div class='add'>+	bool MinimizeReallocationSuccess = false;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ForceSingleDPP = %u\n", __func__, ForceSingleDPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: nomDETInKByte = %u\n", __func__, nomDETInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfActiveSurfaces = %u\n", __func__, NumberOfActiveSurfaces);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UnboundedRequestEnabled = %u\n", __func__, UnboundedRequestEnabled);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxTotalDETInKByte = %u\n", __func__, MaxTotalDETInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ConfigReturnBufferSizeInKByte = %u\n", __func__, ConfigReturnBufferSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MinCompressedBufferSizeInKByte = %u\n", __func__, MinCompressedBufferSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: CompressedBufferSegmentSizeInkByte = %u\n", __func__, CompressedBufferSegmentSizeInkByte);</div><div class='add'>+</div><div class='add'>+	// Note: Will use default det size if that fits 2 swaths</div><div class='add'>+	if (UnboundedRequestEnabled) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[0].overrides.det_size_override_kb &gt; 0) {</div><div class='add'>+			DETBufferSizeInKByte[0] = display_cfg-&gt;plane_descriptors[0].overrides.det_size_override_kb;</div><div class='add'>+		} else {</div><div class='add'>+			DETBufferSizeInKByte[0] = (unsigned int)math_max2(128.0, math_ceil2(2.0 * ((double)full_swath_bytes_l[0] + (double)full_swath_bytes_c[0]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte));</div><div class='add'>+		}</div><div class='add'>+		*CompressedBufferSizeInkByte = ConfigReturnBufferSizeInKByte - DETBufferSizeInKByte[0];</div><div class='add'>+	} else {</div><div class='add'>+		l-&gt;DETBufferSizePoolInKByte = MaxTotalDETInKByte;</div><div class='add'>+		for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+			DETBufferSizeInKByte[k] = 0;</div><div class='add'>+			if (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format)) {</div><div class='add'>+				l-&gt;max_minDET = nomDETInKByte - ConfigReturnBufferSegmentSizeInkByte;</div><div class='add'>+			} else {</div><div class='add'>+				l-&gt;max_minDET = nomDETInKByte;</div><div class='add'>+			}</div><div class='add'>+			l-&gt;minDET = 128;</div><div class='add'>+			l-&gt;minDET_pipe = 0;</div><div class='add'>+</div><div class='add'>+			// add DET resource until can hold 2 full swaths</div><div class='add'>+			while (l-&gt;minDET &lt;= l-&gt;max_minDET &amp;&amp; l-&gt;minDET_pipe == 0) {</div><div class='add'>+				if (2.0 * ((double)full_swath_bytes_l[k] + (double)full_swath_bytes_c[k]) / 1024.0 &lt;= l-&gt;minDET)</div><div class='add'>+					l-&gt;minDET_pipe = l-&gt;minDET;</div><div class='add'>+				l-&gt;minDET = l-&gt;minDET + ConfigReturnBufferSegmentSizeInkByte;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u minDET = %u\n", __func__, k, l-&gt;minDET);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u max_minDET = %u\n", __func__, k, l-&gt;max_minDET);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u minDET_pipe = %u\n", __func__, k, l-&gt;minDET_pipe);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, full_swath_bytes_l[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, full_swath_bytes_c[k]);</div><div class='add'>+</div><div class='add'>+			if (l-&gt;minDET_pipe == 0) {</div><div class='add'>+				l-&gt;minDET_pipe = (unsigned int)(math_max2(128, math_ceil2(((double)full_swath_bytes_l[k] + (double)full_swath_bytes_c[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u minDET_pipe = %u (assume each plane take half DET)\n", __func__, k, l-&gt;minDET_pipe);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+				DETBufferSizeInKByte[k] = 0;</div><div class='add'>+			} else if (display_cfg-&gt;plane_descriptors[k].overrides.det_size_override_kb &gt; 0) {</div><div class='add'>+				DETBufferSizeInKByte[k] = display_cfg-&gt;plane_descriptors[k].overrides.det_size_override_kb;</div><div class='add'>+				l-&gt;DETBufferSizePoolInKByte = l-&gt;DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * display_cfg-&gt;plane_descriptors[k].overrides.det_size_override_kb;</div><div class='add'>+			} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * l-&gt;minDET_pipe &lt;= l-&gt;DETBufferSizePoolInKByte) {</div><div class='add'>+				DETBufferSizeInKByte[k] = l-&gt;minDET_pipe;</div><div class='add'>+				l-&gt;DETBufferSizePoolInKByte = l-&gt;DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * l-&gt;minDET_pipe;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u DETSizeOverride = %u\n", __func__, k, display_cfg-&gt;plane_descriptors[k].overrides.det_size_override_kb);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: DETBufferSizePoolInKByte = %u\n", __func__, l-&gt;DETBufferSizePoolInKByte);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;minimize_det_reallocation) {</div><div class='add'>+			MinimizeReallocationSuccess = true;</div><div class='add'>+			// To minimize det reallocation, we don't distribute based on each surfaces bandwidth proportional to the global</div><div class='add'>+			// but rather distribute DET across streams proportionally based on pixel rate, and only distribute based on</div><div class='add'>+			// bandwidth between the planes on the same stream.  This ensures that large scale re-distribution only on a</div><div class='add'>+			// stream count and/or pixel rate change, which is must less likely then general bandwidth changes per plane.</div><div class='add'>+</div><div class='add'>+			// Calculate total pixel rate</div><div class='add'>+			for (unsigned int k = 0; k &lt; display_cfg-&gt;num_streams; ++k) {</div><div class='add'>+				l-&gt;TotalPixelRate += display_cfg-&gt;stream_descriptors[k].timing.pixel_clock_khz;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			// Calculate per stream DET budget</div><div class='add'>+			for (unsigned int k = 0; k &lt; display_cfg-&gt;num_streams; ++k) {</div><div class='add'>+				l-&gt;DETBudgetPerStream[k] = (unsigned int)((double) display_cfg-&gt;stream_descriptors[k].timing.pixel_clock_khz * MaxTotalDETInKByte / l-&gt;TotalPixelRate);</div><div class='add'>+				l-&gt;RemainingDETBudgetPerStream[k] = l-&gt;DETBudgetPerStream[k];</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			// Calculate the per stream total bandwidth</div><div class='add'>+			for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+				if (!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+					l-&gt;TotalBandwidthPerStream[display_cfg-&gt;plane_descriptors[k].stream_index] += (unsigned int)(ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);</div><div class='add'>+</div><div class='add'>+					// Check the minimum can be satisfied by budget</div><div class='add'>+					if (l-&gt;RemainingDETBudgetPerStream[display_cfg-&gt;plane_descriptors[k].stream_index] &gt;= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {</div><div class='add'>+						l-&gt;RemainingDETBudgetPerStream[display_cfg-&gt;plane_descriptors[k].stream_index] -= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k]);</div><div class='add'>+					} else {</div><div class='add'>+						MinimizeReallocationSuccess = false;</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (MinimizeReallocationSuccess) {</div><div class='add'>+				// Since a fixed budget per stream is sufficient to satisfy the minimums, just re-distribute each streams</div><div class='add'>+				// budget proportionally across its planes</div><div class='add'>+				l-&gt;ResidualDETAfterRounding = MaxTotalDETInKByte;</div><div class='add'>+</div><div class='add'>+				for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+					if (!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+						l-&gt;IdealDETBudget = (unsigned int)(((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / l-&gt;TotalBandwidthPerStream[display_cfg-&gt;plane_descriptors[k].stream_index])</div><div class='add'>+							* l-&gt;DETBudgetPerStream[display_cfg-&gt;plane_descriptors[k].stream_index]);</div><div class='add'>+</div><div class='add'>+						if (l-&gt;IdealDETBudget &gt; DETBufferSizeInKByte[k]) {</div><div class='add'>+							l-&gt;DeltaDETBudget = l-&gt;IdealDETBudget - DETBufferSizeInKByte[k];</div><div class='add'>+							if (l-&gt;DeltaDETBudget &gt; l-&gt;RemainingDETBudgetPerStream[display_cfg-&gt;plane_descriptors[k].stream_index])</div><div class='add'>+								l-&gt;DeltaDETBudget = l-&gt;RemainingDETBudgetPerStream[display_cfg-&gt;plane_descriptors[k].stream_index];</div><div class='add'>+</div><div class='add'>+							/* split the additional budgeted DET among the pipes per plane */</div><div class='add'>+							DETBufferSizeInKByte[k] += (unsigned int)((double)l-&gt;DeltaDETBudget / (ForceSingleDPP ? 1 : DPPPerSurface[k]));</div><div class='add'>+							l-&gt;RemainingDETBudgetPerStream[display_cfg-&gt;plane_descriptors[k].stream_index] -= l-&gt;DeltaDETBudget;</div><div class='add'>+						}</div><div class='add'>+</div><div class='add'>+						// Round down to segment size</div><div class='add'>+						DETBufferSizeInKByte[k] = (DETBufferSizeInKByte[k] / ConfigReturnBufferSegmentSizeInkByte) * ConfigReturnBufferSegmentSizeInkByte;</div><div class='add'>+</div><div class='add'>+						l-&gt;ResidualDETAfterRounding -= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k]);</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!MinimizeReallocationSuccess) {</div><div class='add'>+			l-&gt;TotalBandwidth = 0;</div><div class='add'>+			for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+				if (!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+					l-&gt;TotalBandwidth = l-&gt;TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: --- Before bandwidth adjustment ---\n", __func__);</div><div class='add'>+			for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);</div><div class='add'>+			}</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: --- DET allocation with bandwidth ---\n", __func__);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: TotalBandwidth = %f\n", __func__, l-&gt;TotalBandwidth);</div><div class='add'>+			l-&gt;BandwidthOfSurfacesNotAssignedDETPiece = l-&gt;TotalBandwidth;</div><div class='add'>+			for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+</div><div class='add'>+				if (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+					DETPieceAssignedToThisSurfaceAlready[k] = true;</div><div class='add'>+				} else if (display_cfg-&gt;plane_descriptors[k].overrides.det_size_override_kb &gt; 0 || (((double)(ForceSingleDPP ? 1 : DPPPerSurface[k]) * (double)DETBufferSizeInKByte[k] / (double)MaxTotalDETInKByte) &gt;= ((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / l-&gt;TotalBandwidth))) {</div><div class='add'>+					DETPieceAssignedToThisSurfaceAlready[k] = true;</div><div class='add'>+					l-&gt;BandwidthOfSurfacesNotAssignedDETPiece = l-&gt;BandwidthOfSurfacesNotAssignedDETPiece - ReadBandwidthLuma[k] - ReadBandwidthChroma[k];</div><div class='add'>+				} else {</div><div class='add'>+					DETPieceAssignedToThisSurfaceAlready[k] = false;</div><div class='add'>+				}</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, k, DETPieceAssignedToThisSurfaceAlready[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k, l-&gt;BandwidthOfSurfacesNotAssignedDETPiece);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			for (unsigned int j = 0; j &lt; NumberOfActiveSurfaces; ++j) {</div><div class='add'>+				NextPotentialSurfaceToAssignDETPieceFound = false;</div><div class='add'>+				l-&gt;NextSurfaceToAssignDETPiece = 0;</div><div class='add'>+</div><div class='add'>+				for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthLuma[k] = %f\n", __func__, j, k, ReadBandwidthLuma[k]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthChroma[k] = %f\n", __func__, j, k, ReadBandwidthChroma[k]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthLuma[Next] = %f\n", __func__, j, k, ReadBandwidthLuma[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthChroma[Next] = %f\n", __func__, j, k, ReadBandwidthChroma[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, NextSurfaceToAssignDETPiece = %u\n", __func__, j, k, l-&gt;NextSurfaceToAssignDETPiece);</div><div class='add'>+					if (!DETPieceAssignedToThisSurfaceAlready[k] &amp;&amp; (!NextPotentialSurfaceToAssignDETPieceFound ||</div><div class='add'>+						ReadBandwidthLuma[k] + ReadBandwidthChroma[k] &lt; ReadBandwidthLuma[l-&gt;NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[l-&gt;NextSurfaceToAssignDETPiece])) {</div><div class='add'>+						l-&gt;NextSurfaceToAssignDETPiece = k;</div><div class='add'>+						NextPotentialSurfaceToAssignDETPieceFound = true;</div><div class='add'>+					}</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u k=%u, NextPotentialSurfaceToAssignDETPieceFound = %u\n", __func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if (NextPotentialSurfaceToAssignDETPieceFound) {</div><div class='add'>+					l-&gt;NextDETBufferPieceInKByte = (unsigned int)(math_min2(</div><div class='add'>+						math_round((double)l-&gt;DETBufferSizePoolInKByte * (ReadBandwidthLuma[l-&gt;NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[l-&gt;NextSurfaceToAssignDETPiece]) / l-&gt;BandwidthOfSurfacesNotAssignedDETPiece /</div><div class='add'>+							((ForceSingleDPP ? 1 : DPPPerSurface[l-&gt;NextSurfaceToAssignDETPiece]) * ConfigReturnBufferSegmentSizeInkByte))</div><div class='add'>+						* (ForceSingleDPP ? 1 : DPPPerSurface[l-&gt;NextSurfaceToAssignDETPiece]) * ConfigReturnBufferSegmentSizeInkByte,</div><div class='add'>+						math_floor2((double)l-&gt;DETBufferSizePoolInKByte, (ForceSingleDPP ? 1 : DPPPerSurface[l-&gt;NextSurfaceToAssignDETPiece]) * ConfigReturnBufferSegmentSizeInkByte)));</div><div class='add'>+</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, DETBufferSizePoolInKByte = %u\n", __func__, j, l-&gt;DETBufferSizePoolInKByte);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, NextSurfaceToAssignDETPiece = %u\n", __func__, j, l-&gt;NextSurfaceToAssignDETPiece);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, ReadBandwidthLuma[%u] = %f\n", __func__, j, l-&gt;NextSurfaceToAssignDETPiece, ReadBandwidthLuma[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, ReadBandwidthChroma[%u] = %f\n", __func__, j, l-&gt;NextSurfaceToAssignDETPiece, ReadBandwidthChroma[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, j, l-&gt;BandwidthOfSurfacesNotAssignedDETPiece);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, NextDETBufferPieceInKByte = %u\n", __func__, j, l-&gt;NextDETBufferPieceInKByte);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: j=%u, DETBufferSizeInKByte[%u] increases from %u ", __func__, j, l-&gt;NextSurfaceToAssignDETPiece, DETBufferSizeInKByte[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+</div><div class='add'>+					DETBufferSizeInKByte[l-&gt;NextSurfaceToAssignDETPiece] = DETBufferSizeInKByte[l-&gt;NextSurfaceToAssignDETPiece] + l-&gt;NextDETBufferPieceInKByte / (ForceSingleDPP ? 1 : DPPPerSurface[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+					DML_LOG_VERBOSE("to %u\n", DETBufferSizeInKByte[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+</div><div class='add'>+					l-&gt;DETBufferSizePoolInKByte = l-&gt;DETBufferSizePoolInKByte - l-&gt;NextDETBufferPieceInKByte;</div><div class='add'>+					DETPieceAssignedToThisSurfaceAlready[l-&gt;NextSurfaceToAssignDETPiece] = true;</div><div class='add'>+					l-&gt;BandwidthOfSurfacesNotAssignedDETPiece = l-&gt;BandwidthOfSurfacesNotAssignedDETPiece - (ReadBandwidthLuma[l-&gt;NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[l-&gt;NextSurfaceToAssignDETPiece]);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		*CompressedBufferSizeInkByte = MinCompressedBufferSizeInKByte;</div><div class='add'>+	}</div><div class='add'>+	*CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByte / ConfigReturnBufferSegmentSizeInkByte;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: --- After bandwidth adjustment ---\n", __func__);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, *CompressedBufferSizeInkByte);</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u (TotalReadBandWidth=%f)\n", __func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateRequiredDispclk(</div><div class='add'>+	enum dml2_odm_mode ODMMode,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	bool isTMDS420)</div><div class='add'>+{</div><div class='add'>+	double DispClk;</div><div class='add'>+</div><div class='add'>+	if (ODMMode == dml2_odm_mode_combine_4to1) {</div><div class='add'>+		DispClk = PixelClock / 4.0;</div><div class='add'>+	} else if (ODMMode == dml2_odm_mode_combine_3to1) {</div><div class='add'>+		DispClk = PixelClock / 3.0;</div><div class='add'>+	} else if (ODMMode == dml2_odm_mode_combine_2to1) {</div><div class='add'>+		DispClk = PixelClock / 2.0;</div><div class='add'>+	} else {</div><div class='add'>+		DispClk = PixelClock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (isTMDS420) {</div><div class='add'>+		double TMDS420MinPixClock = PixelClock / 2.0;</div><div class='add'>+		DispClk = math_max2(DispClk, TMDS420MinPixClock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return DispClk;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double TruncToValidBPP(</div><div class='add'>+	struct dml2_core_shared_TruncToValidBPP_locals *l,</div><div class='add'>+	double LinkBitRate,</div><div class='add'>+	unsigned int Lanes,</div><div class='add'>+	unsigned int HTotal,</div><div class='add'>+	unsigned int HActive,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	double DesiredBPP,</div><div class='add'>+	bool DSCEnable,</div><div class='add'>+	enum dml2_output_encoder_class Output,</div><div class='add'>+	enum dml2_output_format_class Format,</div><div class='add'>+	unsigned int DSCInputBitPerComponent,</div><div class='add'>+	unsigned int DSCSlices,</div><div class='add'>+	unsigned int AudioRate,</div><div class='add'>+	unsigned int AudioLayout,</div><div class='add'>+	enum dml2_odm_mode ODMModeNoDSC,</div><div class='add'>+	enum dml2_odm_mode ODMModeDSC,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int *RequiredSlots)</div><div class='add'>+{</div><div class='add'>+	double MaxLinkBPP;</div><div class='add'>+	unsigned int MinDSCBPP;</div><div class='add'>+	double MaxDSCBPP;</div><div class='add'>+	unsigned int NonDSCBPP0;</div><div class='add'>+	unsigned int NonDSCBPP1;</div><div class='add'>+	unsigned int NonDSCBPP2;</div><div class='add'>+	enum dml2_odm_mode ODMMode;</div><div class='add'>+</div><div class='add'>+	if (Format == dml2_420) {</div><div class='add'>+		NonDSCBPP0 = 12;</div><div class='add'>+		NonDSCBPP1 = 15;</div><div class='add'>+		NonDSCBPP2 = 18;</div><div class='add'>+		MinDSCBPP = 6;</div><div class='add'>+		MaxDSCBPP = 16;</div><div class='add'>+	} else if (Format == dml2_444) {</div><div class='add'>+		NonDSCBPP0 = 24;</div><div class='add'>+		NonDSCBPP1 = 30;</div><div class='add'>+		NonDSCBPP2 = 36;</div><div class='add'>+		MinDSCBPP = 8;</div><div class='add'>+		MaxDSCBPP = 16;</div><div class='add'>+	} else {</div><div class='add'>+</div><div class='add'>+		if (Output == dml2_hdmi || Output == dml2_hdmifrl) {</div><div class='add'>+			NonDSCBPP0 = 24;</div><div class='add'>+			NonDSCBPP1 = 24;</div><div class='add'>+			NonDSCBPP2 = 24;</div><div class='add'>+		} else {</div><div class='add'>+			NonDSCBPP0 = 16;</div><div class='add'>+			NonDSCBPP1 = 20;</div><div class='add'>+			NonDSCBPP2 = 24;</div><div class='add'>+		}</div><div class='add'>+		if (Format == dml2_n422 || Output == dml2_hdmifrl) {</div><div class='add'>+			MinDSCBPP = 7;</div><div class='add'>+			MaxDSCBPP = 16;</div><div class='add'>+		} else {</div><div class='add'>+			MinDSCBPP = 8;</div><div class='add'>+			MaxDSCBPP = 16;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (Output == dml2_dp2p0) {</div><div class='add'>+		MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128.0 / 132.0 * 383.0 / 384.0 * 65536.0 / 65540.0;</div><div class='add'>+	} else if (DSCEnable &amp;&amp; Output == dml2_dp) {</div><div class='add'>+		MaxLinkBPP = LinkBitRate / 10.0 * 8.0 * Lanes / PixelClock * (1 - 2.4 / 100);</div><div class='add'>+	} else {</div><div class='add'>+		MaxLinkBPP = LinkBitRate / 10.0 * 8.0 * Lanes / PixelClock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ODMMode = DSCEnable ? ODMModeDSC : ODMModeNoDSC;</div><div class='add'>+</div><div class='add'>+	if (ODMMode == dml2_odm_mode_split_1to2) {</div><div class='add'>+		MaxLinkBPP = 2 * MaxLinkBPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (DesiredBPP == 0) {</div><div class='add'>+		if (DSCEnable) {</div><div class='add'>+			if (MaxLinkBPP &lt; MinDSCBPP) {</div><div class='add'>+				return __DML2_CALCS_DPP_INVALID__;</div><div class='add'>+			} else if (MaxLinkBPP &gt;= MaxDSCBPP) {</div><div class='add'>+				return MaxDSCBPP;</div><div class='add'>+			} else {</div><div class='add'>+				return math_floor2(16.0 * MaxLinkBPP, 1.0) / 16.0;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			if (MaxLinkBPP &gt;= NonDSCBPP2) {</div><div class='add'>+				return NonDSCBPP2;</div><div class='add'>+			} else if (MaxLinkBPP &gt;= NonDSCBPP1) {</div><div class='add'>+				return NonDSCBPP1;</div><div class='add'>+			} else if (MaxLinkBPP &gt;= NonDSCBPP0) {</div><div class='add'>+				return NonDSCBPP0;</div><div class='add'>+			} else {</div><div class='add'>+				return __DML2_CALCS_DPP_INVALID__;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (!((DSCEnable == false &amp;&amp; (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||</div><div class='add'>+			(DSCEnable &amp;&amp; DesiredBPP &gt;= MinDSCBPP &amp;&amp; DesiredBPP &lt;= MaxDSCBPP))) {</div><div class='add'>+			return __DML2_CALCS_DPP_INVALID__;</div><div class='add'>+		} else {</div><div class='add'>+			return DesiredBPP;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+// updated for dcn4</div><div class='add'>+static unsigned int dscceComputeDelay(</div><div class='add'>+	unsigned int bpc,</div><div class='add'>+	double BPP,</div><div class='add'>+	unsigned int sliceWidth,</div><div class='add'>+	unsigned int numSlices,</div><div class='add'>+	enum dml2_output_format_class pixelFormat,</div><div class='add'>+	enum dml2_output_encoder_class Output)</div><div class='add'>+{</div><div class='add'>+	// valid bpc = source bits per component in the set of {8, 10, 12}</div><div class='add'>+	// valid bpp = increments of 1/16 of a bit</div><div class='add'>+	// min = 6/7/8 in N420/N422/444, respectively</div><div class='add'>+	// max = such that compression is 1:1</div><div class='add'>+	//valid sliceWidth = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)</div><div class='add'>+	//valid numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}</div><div class='add'>+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}</div><div class='add'>+</div><div class='add'>+	// fixed value</div><div class='add'>+	unsigned int rcModelSize = 8192;</div><div class='add'>+</div><div class='add'>+	// N422/N420 operate at 2 pixels per clock</div><div class='add'>+	unsigned int pixelsPerClock, padding_pixels, ssm_group_priming_delay, ssm_pipeline_delay, obsm_pipeline_delay, slice_padded_pixels, ixd_plus_padding, ixd_plus_padding_groups, cycles_per_group, group_delay, pipeline_delay, pixels, additional_group_delay, lines_to_reach_ixd, groups_to_reach_ixd, slice_width_groups, initial_xmit_delay, number_of_lines_to_reach_ixd, slice_width_modified;</div><div class='add'>+</div><div class='add'>+	if (pixelFormat == dml2_420)</div><div class='add'>+		pixelsPerClock = 2;</div><div class='add'>+	// #all other modes operate at 1 pixel per clock</div><div class='add'>+	else if (pixelFormat == dml2_444)</div><div class='add'>+		pixelsPerClock = 1;</div><div class='add'>+	else if (pixelFormat == dml2_n422 || Output == dml2_hdmifrl)</div><div class='add'>+		pixelsPerClock = 2;</div><div class='add'>+	else</div><div class='add'>+		pixelsPerClock = 1;</div><div class='add'>+</div><div class='add'>+	//initial transmit delay as per PPS</div><div class='add'>+	initial_xmit_delay = (unsigned int)(math_round(rcModelSize / 2.0 / BPP / pixelsPerClock));</div><div class='add'>+</div><div class='add'>+	//slice width as seen by dscc_bcl in pixels or pixels pairs (depending on number of pixels per pixel container based on pixel format)</div><div class='add'>+	slice_width_modified = (pixelFormat == dml2_444 || pixelFormat == dml2_420 || Output == dml2_hdmifrl) ? sliceWidth / 2 : sliceWidth;</div><div class='add'>+</div><div class='add'>+	padding_pixels = ((slice_width_modified % 3) != 0) ? (3 - (slice_width_modified % 3)) * (initial_xmit_delay / slice_width_modified) : 0;</div><div class='add'>+</div><div class='add'>+	if ((3.0 * pixelsPerClock * BPP) &gt;= ((double)((initial_xmit_delay + 2) / 3) * (double)(3 + (pixelFormat == dml2_n422)))) {</div><div class='add'>+		if ((initial_xmit_delay + padding_pixels) % 3 == 1) {</div><div class='add'>+			initial_xmit_delay++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//sub-stream multiplexer balance fifo priming delay in groups as per dsc standard</div><div class='add'>+	if (bpc == 8)</div><div class='add'>+		ssm_group_priming_delay = 83;</div><div class='add'>+	else if (bpc == 10)</div><div class='add'>+		ssm_group_priming_delay = 91;</div><div class='add'>+	else if (bpc == 12)</div><div class='add'>+		ssm_group_priming_delay = 115;</div><div class='add'>+	else if (bpc == 14)</div><div class='add'>+		ssm_group_priming_delay = 123;</div><div class='add'>+	else</div><div class='add'>+		ssm_group_priming_delay = 128;</div><div class='add'>+</div><div class='add'>+	//slice width in groups is rounded up to the nearest group as DSC adds padded pixels such that there are an integer number of groups per slice</div><div class='add'>+	slice_width_groups = (slice_width_modified + 2) / 3;</div><div class='add'>+</div><div class='add'>+	//determine number of padded pixels in the last group of a slice line, computed as</div><div class='add'>+	slice_padded_pixels = 3 * slice_width_groups - slice_width_modified;</div><div class='add'>+</div><div class='add'>+	//determine integer number of complete slice lines required to reach initial transmit delay without ssm delay considered</div><div class='add'>+	number_of_lines_to_reach_ixd = initial_xmit_delay / slice_width_modified;</div><div class='add'>+</div><div class='add'>+	//increase initial transmit delay by the number of padded pixels added to a slice line multipled by the integer number of complete lines to reach initial transmit delay</div><div class='add'>+	//this step is necessary as each padded pixel added takes up a clock cycle and, therefore, adds to the overall delay</div><div class='add'>+	ixd_plus_padding = initial_xmit_delay + slice_padded_pixels * number_of_lines_to_reach_ixd;</div><div class='add'>+</div><div class='add'>+	//convert the padded initial transmit delay from pixels to groups by rounding up to the nearest group as DSC processes in groups of pixels</div><div class='add'>+	ixd_plus_padding_groups = (ixd_plus_padding + 2) / 3;</div><div class='add'>+</div><div class='add'>+	//number of groups required for a slice to reach initial transmit delay is the sum of the padded initial transmit delay plus the ssm group priming delay</div><div class='add'>+	groups_to_reach_ixd = ixd_plus_padding_groups + ssm_group_priming_delay;</div><div class='add'>+</div><div class='add'>+	//number of lines required to reach padded initial transmit delay in groups in slices to the left of the last horizontal slice</div><div class='add'>+	//needs to be rounded up as a complete slice lines are buffered prior to initial transmit delay being reached in the last horizontal slice</div><div class='add'>+	lines_to_reach_ixd = (groups_to_reach_ixd + slice_width_groups - 1) / slice_width_groups; //round up lines to reach ixd to next</div><div class='add'>+</div><div class='add'>+	//determine if there are non-zero number of pixels reached in the group where initial transmit delay is reached</div><div class='add'>+	//an additional group time (i.e., 3 pixel times) is required before the first output if there are no additional pixels beyond initial transmit delay</div><div class='add'>+	additional_group_delay = ((initial_xmit_delay - number_of_lines_to_reach_ixd * slice_width_modified) % 3) == 0 ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	//number of pipeline delay cycles in the ssm block (can be determined empirically or analytically by inspecting the ssm block)</div><div class='add'>+	ssm_pipeline_delay = 2;</div><div class='add'>+</div><div class='add'>+	//number of pipe delay cycles in the obsm block (can be determined empirically or analytically by inspecting the obsm block)</div><div class='add'>+	obsm_pipeline_delay = 1;</div><div class='add'>+</div><div class='add'>+	//a group of pixels is worth 6 pixels in N422/N420 mode or 3 pixels in all other modes</div><div class='add'>+	if (pixelFormat == dml2_420 || pixelFormat == dml2_444 || pixelFormat == dml2_n422 || Output == dml2_hdmifrl)</div><div class='add'>+		cycles_per_group = 6;</div><div class='add'>+	else</div><div class='add'>+		cycles_per_group = 3;</div><div class='add'>+	//delay of the bit stream contruction layer in pixels is the sum of:</div><div class='add'>+	//1. number of pixel containers in a slice line multipled by the number of lines required to reach initial transmit delay multipled by number of slices to the left of the last horizontal slice</div><div class='add'>+	//2. number of pixel containers required to reach initial transmit delay (specifically, in the last horizontal slice)</div><div class='add'>+	//3. additional group of delay if initial transmit delay is reached exactly in a group</div><div class='add'>+	//4. ssm and obsm pipeline delay (i.e., clock cycles of delay)</div><div class='add'>+	group_delay = (lines_to_reach_ixd * slice_width_groups * (numSlices - 1)) + groups_to_reach_ixd + additional_group_delay;</div><div class='add'>+	pipeline_delay = ssm_pipeline_delay + obsm_pipeline_delay;</div><div class='add'>+</div><div class='add'>+	//pixel delay is group_delay (converted to pixels) + pipeline, however, first group is a special case since it is processed as soon as it arrives (i.e., in 3 cycles regardless of pixel format)</div><div class='add'>+	pixels = (group_delay - 1) * cycles_per_group + 3 + pipeline_delay;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: bpc: %u\n", __func__, bpc);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BPP: %f\n", __func__, BPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: sliceWidth: %u\n", __func__, sliceWidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: numSlices: %u\n", __func__, numSlices);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: pixelFormat: %u\n", __func__, pixelFormat);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Output: %u\n", __func__, Output);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: pixels: %u\n", __func__, pixels);</div><div class='add'>+	return pixels;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+//updated in dcn4</div><div class='add'>+static unsigned int dscComputeDelay(enum dml2_output_format_class pixelFormat, enum dml2_output_encoder_class Output)</div><div class='add'>+{</div><div class='add'>+	unsigned int Delay = 0;</div><div class='add'>+	unsigned int dispclk_per_dscclk = 3;</div><div class='add'>+</div><div class='add'>+	// sfr</div><div class='add'>+	Delay = Delay + 2;</div><div class='add'>+</div><div class='add'>+	if (pixelFormat == dml2_420 || pixelFormat == dml2_n422 || (Output == dml2_hdmifrl &amp;&amp; pixelFormat != dml2_444)) {</div><div class='add'>+		dispclk_per_dscclk = 3 * 2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pixelFormat == dml2_420) {</div><div class='add'>+		//dscc top delay for pixel compression layer</div><div class='add'>+		Delay = Delay + 16 * dispclk_per_dscclk;</div><div class='add'>+</div><div class='add'>+		// dscc - input deserializer</div><div class='add'>+		Delay = Delay + 5;</div><div class='add'>+</div><div class='add'>+		// dscc - input cdc fifo</div><div class='add'>+		Delay = Delay + 1 + 4 * dispclk_per_dscclk;</div><div class='add'>+</div><div class='add'>+		// dscc - output cdc fifo</div><div class='add'>+		Delay = Delay + 3 + 1 * dispclk_per_dscclk;</div><div class='add'>+</div><div class='add'>+		// dscc - cdc uncertainty</div><div class='add'>+		Delay = Delay + 3 + 3 * dispclk_per_dscclk;</div><div class='add'>+	} else if (pixelFormat == dml2_n422 || (Output == dml2_hdmifrl &amp;&amp; pixelFormat != dml2_444)) {</div><div class='add'>+		//dscc top delay for pixel compression layer</div><div class='add'>+		Delay = Delay + 16 * dispclk_per_dscclk;</div><div class='add'>+		// dsccif</div><div class='add'>+		Delay = Delay + 1;</div><div class='add'>+		// dscc - input deserializer</div><div class='add'>+		Delay = Delay + 5;</div><div class='add'>+		// dscc - input cdc fifo</div><div class='add'>+		Delay = Delay + 1 + 4 * dispclk_per_dscclk;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		// dscc - output cdc fifo</div><div class='add'>+		Delay = Delay + 3 + 1 * dispclk_per_dscclk;</div><div class='add'>+		// dscc - cdc uncertainty</div><div class='add'>+		Delay = Delay + 3 + 3 * dispclk_per_dscclk;</div><div class='add'>+	} else if (pixelFormat == dml2_s422) {</div><div class='add'>+		//dscc top delay for pixel compression layer</div><div class='add'>+		Delay = Delay + 17 * dispclk_per_dscclk;</div><div class='add'>+</div><div class='add'>+		// dscc - input deserializer</div><div class='add'>+		Delay = Delay + 3;</div><div class='add'>+		// dscc - input cdc fifo</div><div class='add'>+		Delay = Delay + 1 + 4 * dispclk_per_dscclk;</div><div class='add'>+		// dscc - output cdc fifo</div><div class='add'>+		Delay = Delay + 3 + 1 * dispclk_per_dscclk;</div><div class='add'>+		// dscc - cdc uncertainty</div><div class='add'>+		Delay = Delay + 3 + 3 * dispclk_per_dscclk;</div><div class='add'>+	} else {</div><div class='add'>+		//dscc top delay for pixel compression layer</div><div class='add'>+		Delay = Delay + 16 * dispclk_per_dscclk;</div><div class='add'>+		// dscc - input deserializer</div><div class='add'>+		Delay = Delay + 3;</div><div class='add'>+		// dscc - input cdc fifo</div><div class='add'>+		Delay = Delay + 1 + 4 * dispclk_per_dscclk;</div><div class='add'>+		// dscc - output cdc fifo</div><div class='add'>+		Delay = Delay + 3 + 1 * dispclk_per_dscclk;</div><div class='add'>+</div><div class='add'>+		// dscc - cdc uncertainty</div><div class='add'>+		Delay = Delay + 3 + 3 * dispclk_per_dscclk;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// sft</div><div class='add'>+	Delay = Delay + 1;</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: pixelFormat = %u\n", __func__, pixelFormat);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Delay = %u\n", __func__, Delay);</div><div class='add'>+</div><div class='add'>+	return Delay;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int CalculateHostVMDynamicLevels(</div><div class='add'>+	bool GPUVMEnable,</div><div class='add'>+	bool HostVMEnable,</div><div class='add'>+	unsigned int HostVMMinPageSize,</div><div class='add'>+	unsigned int HostVMMaxNonCachedPageTableLevels)</div><div class='add'>+{</div><div class='add'>+	unsigned int HostVMDynamicLevels = 0;</div><div class='add'>+</div><div class='add'>+	if (GPUVMEnable &amp;&amp; HostVMEnable) {</div><div class='add'>+		if (HostVMMinPageSize &lt; 2048)</div><div class='add'>+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;</div><div class='add'>+		else if (HostVMMinPageSize &gt;= 2048 &amp;&amp; HostVMMinPageSize &lt; 1048576)</div><div class='add'>+			HostVMDynamicLevels = (unsigned int)math_max2(0, (double)HostVMMaxNonCachedPageTableLevels - 1);</div><div class='add'>+		else</div><div class='add'>+			HostVMDynamicLevels = (unsigned int)math_max2(0, (double)HostVMMaxNonCachedPageTableLevels - 2);</div><div class='add'>+	} else {</div><div class='add'>+		HostVMDynamicLevels = 0;</div><div class='add'>+	}</div><div class='add'>+	return HostVMDynamicLevels;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int CalculateVMAndRowBytes(struct dml2_core_shared_calculate_vm_and_row_bytes_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int extra_dpde_bytes;</div><div class='add'>+	unsigned int extra_mpde_bytes;</div><div class='add'>+	unsigned int MacroTileSizeBytes;</div><div class='add'>+	unsigned int vp_height_dpte_ub;</div><div class='add'>+</div><div class='add'>+	unsigned int meta_surface_bytes;</div><div class='add'>+	unsigned int vm_bytes;</div><div class='add'>+	unsigned int vp_height_meta_ub;</div><div class='add'>+	unsigned int PixelPTEReqWidth_linear = 0; // VBA_DELTA. VBA doesn't calculate this</div><div class='add'>+</div><div class='add'>+	*p-&gt;MetaRequestHeight = 8 * p-&gt;BlockHeight256Bytes;</div><div class='add'>+	*p-&gt;MetaRequestWidth = 8 * p-&gt;BlockWidth256Bytes;</div><div class='add'>+	if (p-&gt;SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+		*p-&gt;meta_row_height = 32;</div><div class='add'>+		*p-&gt;meta_row_width = (unsigned int)(math_floor2(p-&gt;ViewportXStart + p-&gt;SwathWidth + *p-&gt;MetaRequestWidth - 1, *p-&gt;MetaRequestWidth) - math_floor2(p-&gt;ViewportXStart, *p-&gt;MetaRequestWidth));</div><div class='add'>+		*p-&gt;meta_row_bytes = (unsigned int)(*p-&gt;meta_row_width * *p-&gt;MetaRequestHeight * p-&gt;BytePerPixel / 256.0); // FIXME_DCN4SW missing in old code but no dcc for linear anyways?</div><div class='add'>+	} else if (!dml_is_vertical_rotation(p-&gt;RotationAngle)) {</div><div class='add'>+		*p-&gt;meta_row_height = *p-&gt;MetaRequestHeight;</div><div class='add'>+		if (p-&gt;ViewportStationary &amp;&amp; p-&gt;NumberOfDPPs == 1) {</div><div class='add'>+			*p-&gt;meta_row_width = (unsigned int)(math_floor2(p-&gt;ViewportXStart + p-&gt;SwathWidth + *p-&gt;MetaRequestWidth - 1, *p-&gt;MetaRequestWidth) - math_floor2(p-&gt;ViewportXStart, *p-&gt;MetaRequestWidth));</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;meta_row_width = (unsigned int)(math_ceil2(p-&gt;SwathWidth - 1, *p-&gt;MetaRequestWidth) + *p-&gt;MetaRequestWidth);</div><div class='add'>+		}</div><div class='add'>+		*p-&gt;meta_row_bytes = (unsigned int)(*p-&gt;meta_row_width * *p-&gt;MetaRequestHeight * p-&gt;BytePerPixel / 256.0);</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;meta_row_height = *p-&gt;MetaRequestWidth;</div><div class='add'>+		if (p-&gt;ViewportStationary &amp;&amp; p-&gt;NumberOfDPPs == 1) {</div><div class='add'>+			*p-&gt;meta_row_width = (unsigned int)(math_floor2(p-&gt;ViewportYStart + p-&gt;ViewportHeight + *p-&gt;MetaRequestHeight - 1, *p-&gt;MetaRequestHeight) - math_floor2(p-&gt;ViewportYStart, *p-&gt;MetaRequestHeight));</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;meta_row_width = (unsigned int)(math_ceil2(p-&gt;SwathWidth - 1, *p-&gt;MetaRequestHeight) + *p-&gt;MetaRequestHeight);</div><div class='add'>+		}</div><div class='add'>+		*p-&gt;meta_row_bytes = (unsigned int)(*p-&gt;meta_row_width * *p-&gt;MetaRequestWidth * p-&gt;BytePerPixel / 256.0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;ViewportStationary &amp;&amp; p-&gt;is_phantom &amp;&amp; (p-&gt;NumberOfDPPs == 1 || !dml_is_vertical_rotation(p-&gt;RotationAngle))) {</div><div class='add'>+		vp_height_meta_ub = (unsigned int)(math_floor2(p-&gt;ViewportYStart + p-&gt;ViewportHeight + 64 * p-&gt;BlockHeight256Bytes - 1, 64 * p-&gt;BlockHeight256Bytes) - math_floor2(p-&gt;ViewportYStart, 64 * p-&gt;BlockHeight256Bytes));</div><div class='add'>+	} else if (!dml_is_vertical_rotation(p-&gt;RotationAngle)) {</div><div class='add'>+		vp_height_meta_ub = (unsigned int)(math_ceil2(p-&gt;ViewportHeight - 1, 64 * p-&gt;BlockHeight256Bytes) + 64 * p-&gt;BlockHeight256Bytes);</div><div class='add'>+	} else {</div><div class='add'>+		vp_height_meta_ub = (unsigned int)(math_ceil2(p-&gt;SwathWidth - 1, 64 * p-&gt;BlockHeight256Bytes) + 64 * p-&gt;BlockHeight256Bytes);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	meta_surface_bytes = (unsigned int)(p-&gt;DCCMetaPitch * vp_height_meta_ub * p-&gt;BytePerPixel / 256.0);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCCMetaPitch = %u\n", __func__, p-&gt;DCCMetaPitch);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_surface_bytes = %u\n", __func__, meta_surface_bytes);</div><div class='add'>+	if (p-&gt;GPUVMEnable == true) {</div><div class='add'>+		double meta_vmpg_bytes = 4.0 * 1024.0;</div><div class='add'>+		*p-&gt;meta_pte_bytes_per_frame_ub = (unsigned int)((math_ceil2((double) (meta_surface_bytes - meta_vmpg_bytes) / (8 * meta_vmpg_bytes), 1) + 1) * 64);</div><div class='add'>+		extra_mpde_bytes = 128 * (p-&gt;GPUVMMaxPageTableLevels - 1);</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;meta_pte_bytes_per_frame_ub = 0;</div><div class='add'>+		extra_mpde_bytes = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;DCCEnable || !p-&gt;mrq_present) {</div><div class='add'>+		*p-&gt;meta_pte_bytes_per_frame_ub = 0;</div><div class='add'>+		extra_mpde_bytes = 0;</div><div class='add'>+		*p-&gt;meta_row_bytes = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;GPUVMEnable) {</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow = 0;</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRowStorage = 0;</div><div class='add'>+		*p-&gt;dpte_row_width_ub = 0;</div><div class='add'>+		*p-&gt;dpte_row_height = 0;</div><div class='add'>+		*p-&gt;dpte_row_height_linear = 0;</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow_one_row_per_frame = 0;</div><div class='add'>+		*p-&gt;dpte_row_width_ub_one_row_per_frame = 0;</div><div class='add'>+		*p-&gt;dpte_row_height_one_row_per_frame = 0;</div><div class='add'>+		*p-&gt;vmpg_width = 0;</div><div class='add'>+		*p-&gt;vmpg_height = 0;</div><div class='add'>+		*p-&gt;PixelPTEReqWidth = 0;</div><div class='add'>+		*p-&gt;PixelPTEReqHeight = 0;</div><div class='add'>+		*p-&gt;PTERequestSize = 0;</div><div class='add'>+		*p-&gt;dpde0_bytes_per_frame_ub = 0;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	MacroTileSizeBytes = p-&gt;MacroTileWidth * p-&gt;BytePerPixel * p-&gt;MacroTileHeight;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;ViewportStationary &amp;&amp; p-&gt;is_phantom &amp;&amp; (p-&gt;NumberOfDPPs == 1 || !dml_is_vertical_rotation(p-&gt;RotationAngle))) {</div><div class='add'>+		vp_height_dpte_ub = (unsigned int)(math_floor2(p-&gt;ViewportYStart + p-&gt;ViewportHeight + p-&gt;MacroTileHeight - 1, p-&gt;MacroTileHeight) - math_floor2(p-&gt;ViewportYStart, p-&gt;MacroTileHeight));</div><div class='add'>+	} else if (!dml_is_vertical_rotation(p-&gt;RotationAngle)) {</div><div class='add'>+		vp_height_dpte_ub = (unsigned int)(math_ceil2((double)p-&gt;ViewportHeight - 1, p-&gt;MacroTileHeight) + p-&gt;MacroTileHeight);</div><div class='add'>+	} else {</div><div class='add'>+		vp_height_dpte_ub = (unsigned int)(math_ceil2((double)p-&gt;SwathWidth - 1, p-&gt;MacroTileHeight) + p-&gt;MacroTileHeight);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;GPUVMEnable == true &amp;&amp; p-&gt;GPUVMMaxPageTableLevels &gt; 1) {</div><div class='add'>+		*p-&gt;dpde0_bytes_per_frame_ub = (unsigned int)(64 * (math_ceil2((double)(p-&gt;Pitch * vp_height_dpte_ub * p-&gt;BytePerPixel - MacroTileSizeBytes) / (double)(8 * 2097152), 1) + 1));</div><div class='add'>+		extra_dpde_bytes = 128 * (p-&gt;GPUVMMaxPageTableLevels - 2);</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;dpde0_bytes_per_frame_ub = 0;</div><div class='add'>+		extra_dpde_bytes = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vm_bytes = *p-&gt;meta_pte_bytes_per_frame_ub + extra_mpde_bytes + *p-&gt;dpde0_bytes_per_frame_ub + extra_dpde_bytes;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p-&gt;DCCEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMEnable = %u\n", __func__, p-&gt;GPUVMEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SwModeLinear = %u\n", __func__, p-&gt;SurfaceTiling == dml2_sw_linear);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixel = %u\n", __func__, p-&gt;BytePerPixel);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMMaxPageTableLevels = %u\n", __func__, p-&gt;GPUVMMaxPageTableLevels);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BlockHeight256Bytes = %u\n", __func__, p-&gt;BlockHeight256Bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BlockWidth256Bytes = %u\n", __func__, p-&gt;BlockWidth256Bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MacroTileHeight = %u\n", __func__, p-&gt;MacroTileHeight);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MacroTileWidth = %u\n", __func__, p-&gt;MacroTileWidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_pte_bytes_per_frame_ub = %u\n", __func__, *p-&gt;meta_pte_bytes_per_frame_ub);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpde0_bytes_per_frame_ub = %u\n", __func__, *p-&gt;dpde0_bytes_per_frame_ub);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: extra_mpde_bytes = %u\n", __func__, extra_mpde_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: extra_dpde_bytes = %u\n", __func__, extra_dpde_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vm_bytes = %u\n", __func__, vm_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ViewportHeight = %u\n", __func__, p-&gt;ViewportHeight);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SwathWidth = %u\n", __func__, p-&gt;SwathWidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vp_height_dpte_ub = %u\n", __func__, vp_height_dpte_ub);</div><div class='add'>+</div><div class='add'>+	if (p-&gt;SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+		*p-&gt;PixelPTEReqHeight = 1;</div><div class='add'>+		*p-&gt;PixelPTEReqWidth = p-&gt;GPUVMMinPageSizeKBytes * 1024 * 8 / p-&gt;BytePerPixel;</div><div class='add'>+		PixelPTEReqWidth_linear = p-&gt;GPUVMMinPageSizeKBytes * 1024 * 8 / p-&gt;BytePerPixel;</div><div class='add'>+		*p-&gt;PTERequestSize = 64;</div><div class='add'>+</div><div class='add'>+		*p-&gt;vmpg_height = 1;</div><div class='add'>+		*p-&gt;vmpg_width = p-&gt;GPUVMMinPageSizeKBytes * 1024 / p-&gt;BytePerPixel;</div><div class='add'>+	} else if (p-&gt;GPUVMMinPageSizeKBytes * 1024 &gt;= dml_get_tile_block_size_bytes(p-&gt;SurfaceTiling)) { // 1 64B 8x1 PTE</div><div class='add'>+		*p-&gt;PixelPTEReqHeight = p-&gt;MacroTileHeight;</div><div class='add'>+		*p-&gt;PixelPTEReqWidth = 8 * 1024 * p-&gt;GPUVMMinPageSizeKBytes / (p-&gt;MacroTileHeight * p-&gt;BytePerPixel);</div><div class='add'>+		*p-&gt;PTERequestSize = 64;</div><div class='add'>+</div><div class='add'>+		*p-&gt;vmpg_height = p-&gt;MacroTileHeight;</div><div class='add'>+		*p-&gt;vmpg_width = 1024 * p-&gt;GPUVMMinPageSizeKBytes / (p-&gt;MacroTileHeight * p-&gt;BytePerPixel);</div><div class='add'>+</div><div class='add'>+	} else if (p-&gt;GPUVMMinPageSizeKBytes == 4 &amp;&amp; dml_get_tile_block_size_bytes(p-&gt;SurfaceTiling) == 65536) { // 2 64B PTE requests to get 16 PTEs to cover the 64K tile</div><div class='add'>+		// one 64KB tile, is 16x16x256B req</div><div class='add'>+		*p-&gt;PixelPTEReqHeight = 16 * p-&gt;BlockHeight256Bytes;</div><div class='add'>+		*p-&gt;PixelPTEReqWidth = 16 * p-&gt;BlockWidth256Bytes;</div><div class='add'>+		*p-&gt;PTERequestSize = 128;</div><div class='add'>+</div><div class='add'>+		*p-&gt;vmpg_height = *p-&gt;PixelPTEReqHeight;</div><div class='add'>+		*p-&gt;vmpg_width = *p-&gt;PixelPTEReqWidth;</div><div class='add'>+	} else {</div><div class='add'>+		// default for rest of calculation to go through, when vm is disable, the calulated pte related values shouldnt be used anyways</div><div class='add'>+		*p-&gt;PixelPTEReqHeight = p-&gt;MacroTileHeight;</div><div class='add'>+		*p-&gt;PixelPTEReqWidth = 8 * 1024 * p-&gt;GPUVMMinPageSizeKBytes / (p-&gt;MacroTileHeight * p-&gt;BytePerPixel);</div><div class='add'>+		*p-&gt;PTERequestSize = 64;</div><div class='add'>+</div><div class='add'>+		*p-&gt;vmpg_height = p-&gt;MacroTileHeight;</div><div class='add'>+		*p-&gt;vmpg_width = 1024 * p-&gt;GPUVMMinPageSizeKBytes / (p-&gt;MacroTileHeight * p-&gt;BytePerPixel);</div><div class='add'>+</div><div class='add'>+		if (p-&gt;GPUVMEnable == true) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: GPUVMMinPageSizeKBytes=%u and sw_mode=%u (tile_size=%d) not supported!\n",</div><div class='add'>+				__func__, p-&gt;GPUVMMinPageSizeKBytes, p-&gt;SurfaceTiling, dml_get_tile_block_size_bytes(p-&gt;SurfaceTiling));</div><div class='add'>+			DML_ASSERT(0);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMMinPageSizeKBytes = %u\n", __func__, p-&gt;GPUVMMinPageSizeKBytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEReqHeight = %u\n", __func__, *p-&gt;PixelPTEReqHeight);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEReqWidth = %u\n", __func__, *p-&gt;PixelPTEReqWidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEReqWidth_linear = %u\n", __func__, PixelPTEReqWidth_linear);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PTERequestSize = %u\n", __func__, *p-&gt;PTERequestSize);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Pitch = %u\n", __func__, p-&gt;Pitch);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vmpg_width = %u\n", __func__, *p-&gt;vmpg_width);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vmpg_height = %u\n", __func__, *p-&gt;vmpg_height);</div><div class='add'>+</div><div class='add'>+	*p-&gt;dpte_row_height_one_row_per_frame = vp_height_dpte_ub;</div><div class='add'>+	*p-&gt;dpte_row_width_ub_one_row_per_frame = (unsigned int)((math_ceil2(((double)p-&gt;Pitch * (double)*p-&gt;dpte_row_height_one_row_per_frame / (double)*p-&gt;PixelPTEReqHeight - 1) / (double)*p-&gt;PixelPTEReqWidth, 1) + 1) * (double)*p-&gt;PixelPTEReqWidth);</div><div class='add'>+	*p-&gt;PixelPTEBytesPerRow_one_row_per_frame = (unsigned int)((double)*p-&gt;dpte_row_width_ub_one_row_per_frame / (double)*p-&gt;PixelPTEReqWidth * *p-&gt;PTERequestSize);</div><div class='add'>+	*p-&gt;dpte_row_height_linear = 0;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;SurfaceTiling == dml2_sw_linear) {</div><div class='add'>+		*p-&gt;dpte_row_height = (unsigned int)(math_min2(128, (double)(1ULL &lt;&lt; (unsigned int)math_floor2(math_log((float)(p-&gt;PTEBufferSizeInRequests * *p-&gt;PixelPTEReqWidth / p-&gt;Pitch), 2.0), 1))));</div><div class='add'>+		*p-&gt;dpte_row_width_ub = (unsigned int)(math_ceil2(((double)p-&gt;Pitch * (double)*p-&gt;dpte_row_height - 1), (double)*p-&gt;PixelPTEReqWidth) + *p-&gt;PixelPTEReqWidth);</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow = (unsigned int)((double)*p-&gt;dpte_row_width_ub / (double)*p-&gt;PixelPTEReqWidth * *p-&gt;PTERequestSize);</div><div class='add'>+</div><div class='add'>+		// VBA_DELTA, VBA doesn't have programming value for pte row height linear.</div><div class='add'>+		*p-&gt;dpte_row_height_linear = (unsigned int)1 &lt;&lt; (unsigned int)math_floor2(math_log((float)(p-&gt;PTEBufferSizeInRequests * PixelPTEReqWidth_linear / p-&gt;Pitch), 2.0), 1);</div><div class='add'>+		if (*p-&gt;dpte_row_height_linear &gt; 128)</div><div class='add'>+			*p-&gt;dpte_row_height_linear = 128;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dpte_row_width_ub = %u (linear)\n", __func__, *p-&gt;dpte_row_width_ub);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	} else if (!dml_is_vertical_rotation(p-&gt;RotationAngle)) {</div><div class='add'>+		*p-&gt;dpte_row_height = *p-&gt;PixelPTEReqHeight;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;GPUVMMinPageSizeKBytes &gt; 64) {</div><div class='add'>+			*p-&gt;dpte_row_width_ub = (unsigned int)((math_ceil2(((double)p-&gt;Pitch * (double)*p-&gt;dpte_row_height / (double)*p-&gt;PixelPTEReqHeight - 1) / (double)*p-&gt;PixelPTEReqWidth, 1) + 1) * *p-&gt;PixelPTEReqWidth);</div><div class='add'>+		} else if (p-&gt;ViewportStationary &amp;&amp; (p-&gt;NumberOfDPPs == 1)) {</div><div class='add'>+			*p-&gt;dpte_row_width_ub = (unsigned int)(math_floor2(p-&gt;ViewportXStart + p-&gt;SwathWidth + *p-&gt;PixelPTEReqWidth - 1, *p-&gt;PixelPTEReqWidth) - math_floor2(p-&gt;ViewportXStart, *p-&gt;PixelPTEReqWidth));</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;dpte_row_width_ub = (unsigned int)((math_ceil2((double)(p-&gt;SwathWidth - 1) / (double)*p-&gt;PixelPTEReqWidth, 1) + 1.0) * *p-&gt;PixelPTEReqWidth);</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dpte_row_width_ub = %u (tiled horz)\n", __func__, *p-&gt;dpte_row_width_ub);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow = *p-&gt;dpte_row_width_ub / *p-&gt;PixelPTEReqWidth * *p-&gt;PTERequestSize;</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;dpte_row_height = (unsigned int)(math_min2(*p-&gt;PixelPTEReqWidth, p-&gt;MacroTileWidth));</div><div class='add'>+</div><div class='add'>+		if (p-&gt;ViewportStationary &amp;&amp; (p-&gt;NumberOfDPPs == 1)) {</div><div class='add'>+			*p-&gt;dpte_row_width_ub = (unsigned int)(math_floor2(p-&gt;ViewportYStart + p-&gt;ViewportHeight + *p-&gt;PixelPTEReqHeight - 1, *p-&gt;PixelPTEReqHeight) - math_floor2(p-&gt;ViewportYStart, *p-&gt;PixelPTEReqHeight));</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;dpte_row_width_ub = (unsigned int)((math_ceil2((double)(p-&gt;SwathWidth - 1) / (double)*p-&gt;PixelPTEReqHeight, 1) + 1) * *p-&gt;PixelPTEReqHeight);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow = (unsigned int)((double)*p-&gt;dpte_row_width_ub / (double)*p-&gt;PixelPTEReqHeight * *p-&gt;PTERequestSize);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dpte_row_width_ub = %u (tiled vert)\n", __func__, *p-&gt;dpte_row_width_ub);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;GPUVMEnable != true) {</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow = 0;</div><div class='add'>+		*p-&gt;PixelPTEBytesPerRow_one_row_per_frame = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;PixelPTEBytesPerRowStorage = *p-&gt;PixelPTEBytesPerRow;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMMinPageSizeKBytes = %u\n", __func__, p-&gt;GPUVMMinPageSizeKBytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMEnable = %u\n", __func__, p-&gt;GPUVMEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_row_height = %u\n", __func__, *p-&gt;meta_row_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_height = %u\n", __func__, *p-&gt;dpte_row_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_height_linear = %u\n", __func__, *p-&gt;dpte_row_height_linear);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_width_ub = %u\n", __func__, *p-&gt;dpte_row_width_ub);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, *p-&gt;PixelPTEBytesPerRow);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRowStorage = %u\n", __func__, *p-&gt;PixelPTEBytesPerRowStorage);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PTEBufferSizeInRequests = %u\n", __func__, p-&gt;PTEBufferSizeInRequests);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_height_one_row_per_frame = %u\n", __func__, *p-&gt;dpte_row_height_one_row_per_frame);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_width_ub_one_row_per_frame = %u\n", __func__, *p-&gt;dpte_row_width_ub_one_row_per_frame);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow_one_row_per_frame = %u\n", __func__, *p-&gt;PixelPTEBytesPerRow_one_row_per_frame);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return vm_bytes;</div><div class='add'>+} // CalculateVMAndRowBytes</div><div class='add'>+</div><div class='add'>+static unsigned int CalculatePrefetchSourceLines(</div><div class='add'>+	double VRatio,</div><div class='add'>+	unsigned int VTaps,</div><div class='add'>+	bool Interlace,</div><div class='add'>+	bool ProgressiveToInterlaceUnitInOPP,</div><div class='add'>+	unsigned int SwathHeight,</div><div class='add'>+	enum dml2_rotation_angle RotationAngle,</div><div class='add'>+	bool mirrored,</div><div class='add'>+	bool ViewportStationary,</div><div class='add'>+	unsigned int SwathWidth,</div><div class='add'>+	unsigned int ViewportHeight,</div><div class='add'>+	unsigned int ViewportXStart,</div><div class='add'>+	unsigned int ViewportYStart,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int *VInitPreFill,</div><div class='add'>+	unsigned int *MaxNumSwath)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	unsigned int vp_start_rot = 0;</div><div class='add'>+	unsigned int sw0_tmp = 0;</div><div class='add'>+	unsigned int MaxPartialSwath = 0;</div><div class='add'>+	double numLines = 0;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VRatio = %f\n", __func__, VRatio);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VTaps = %u\n", __func__, VTaps);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ViewportXStart = %u\n", __func__, ViewportXStart);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ViewportYStart = %u\n", __func__, ViewportYStart);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ViewportStationary = %u\n", __func__, ViewportStationary);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SwathHeight = %u\n", __func__, SwathHeight);</div><div class='add'>+#endif</div><div class='add'>+	if (ProgressiveToInterlaceUnitInOPP)</div><div class='add'>+		*VInitPreFill = (unsigned int)(math_floor2((VRatio + (double)VTaps + 1) / 2.0, 1));</div><div class='add'>+	else</div><div class='add'>+		*VInitPreFill = (unsigned int)(math_floor2((VRatio + (double)VTaps + 1 + (Interlace ? 1 : 0) * 0.5 * VRatio) / 2.0, 1));</div><div class='add'>+</div><div class='add'>+	if (ViewportStationary) {</div><div class='add'>+		if (RotationAngle == dml2_rotation_180) {</div><div class='add'>+			vp_start_rot = SwathHeight - (((unsigned int)(ViewportYStart + ViewportHeight - 1) % SwathHeight) + 1);</div><div class='add'>+		} else if ((RotationAngle == dml2_rotation_270 &amp;&amp; !mirrored) || (RotationAngle == dml2_rotation_90 &amp;&amp; mirrored)) {</div><div class='add'>+			vp_start_rot = ViewportXStart;</div><div class='add'>+		} else if ((RotationAngle == dml2_rotation_90 &amp;&amp; !mirrored) || (RotationAngle == dml2_rotation_270 &amp;&amp; mirrored)) {</div><div class='add'>+			vp_start_rot = SwathHeight - (((unsigned int)(ViewportYStart + SwathWidth - 1) % SwathHeight) + 1);</div><div class='add'>+		} else {</div><div class='add'>+			vp_start_rot = ViewportYStart;</div><div class='add'>+		}</div><div class='add'>+		sw0_tmp = SwathHeight - (vp_start_rot % SwathHeight);</div><div class='add'>+		if (sw0_tmp &lt; *VInitPreFill) {</div><div class='add'>+			*MaxNumSwath = (unsigned int)(math_ceil2((*VInitPreFill - sw0_tmp) / (double)SwathHeight, 1) + 1);</div><div class='add'>+		} else {</div><div class='add'>+			*MaxNumSwath = 1;</div><div class='add'>+		}</div><div class='add'>+		MaxPartialSwath = (unsigned int)(math_max2(1, (unsigned int)(vp_start_rot + *VInitPreFill - 1) % SwathHeight));</div><div class='add'>+	} else {</div><div class='add'>+		*MaxNumSwath = (unsigned int)(math_ceil2((*VInitPreFill - 1.0) / (double)SwathHeight, 1) + 1);</div><div class='add'>+		if (*VInitPreFill &gt; 1) {</div><div class='add'>+			MaxPartialSwath = (unsigned int)(math_max2(1, (unsigned int)(*VInitPreFill - 2) % SwathHeight));</div><div class='add'>+		} else {</div><div class='add'>+			MaxPartialSwath = (unsigned int)(math_max2(1, (unsigned int)(*VInitPreFill + SwathHeight - 2) % SwathHeight));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	numLines = *MaxNumSwath * SwathHeight + MaxPartialSwath;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vp_start_rot = %u\n", __func__, vp_start_rot);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VInitPreFill = %u\n", __func__, *VInitPreFill);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxPartialSwath = %u\n", __func__, MaxPartialSwath);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxNumSwath = %u\n", __func__, *MaxNumSwath);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Prefetch source lines = %3.2f\n", __func__, numLines);</div><div class='add'>+#endif</div><div class='add'>+	return (unsigned int)(numLines);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateRowBandwidth(</div><div class='add'>+	bool GPUVMEnable,</div><div class='add'>+	bool use_one_row_for_frame,</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat,</div><div class='add'>+	double VRatio,</div><div class='add'>+	double VRatioChroma,</div><div class='add'>+	bool DCCEnable,</div><div class='add'>+	double LineTime,</div><div class='add'>+	unsigned int PixelPTEBytesPerRowLuma,</div><div class='add'>+	unsigned int PixelPTEBytesPerRowChroma,</div><div class='add'>+	unsigned int dpte_row_height_luma,</div><div class='add'>+	unsigned int dpte_row_height_chroma,</div><div class='add'>+</div><div class='add'>+	bool mrq_present,</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_l,</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_c,</div><div class='add'>+	unsigned int meta_row_height_luma,</div><div class='add'>+	unsigned int meta_row_height_chroma,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *dpte_row_bw,</div><div class='add'>+	double *meta_row_bw)</div><div class='add'>+{</div><div class='add'>+	if (!DCCEnable || !mrq_present) {</div><div class='add'>+		*meta_row_bw = 0;</div><div class='add'>+	} else if (dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha) {</div><div class='add'>+		*meta_row_bw = VRatio * meta_row_bytes_per_row_ub_l / (meta_row_height_luma * LineTime)</div><div class='add'>+				+ VRatioChroma * meta_row_bytes_per_row_ub_c / (meta_row_height_chroma * LineTime);</div><div class='add'>+	} else {</div><div class='add'>+		*meta_row_bw = VRatio * meta_row_bytes_per_row_ub_l / (meta_row_height_luma * LineTime);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (GPUVMEnable != true) {</div><div class='add'>+		*dpte_row_bw = 0;</div><div class='add'>+	} else if (dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha) {</div><div class='add'>+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)</div><div class='add'>+			+ VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime);</div><div class='add'>+	} else {</div><div class='add'>+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateMALLUseForStaticScreen(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int MALLAllocatedForDCN,</div><div class='add'>+	unsigned int SurfaceSizeInMALL[],</div><div class='add'>+	bool one_row_per_frame_fits_in_buffer[],</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	bool is_using_mall_for_ss[])</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	unsigned int SurfaceToAddToMALL;</div><div class='add'>+	bool CanAddAnotherSurfaceToMALL;</div><div class='add'>+	unsigned int TotalSurfaceSizeInMALL;</div><div class='add'>+</div><div class='add'>+	TotalSurfaceSizeInMALL = 0;</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		is_using_mall_for_ss[k] = (display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable);</div><div class='add'>+		if (is_using_mall_for_ss[k])</div><div class='add'>+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, is_using_mall_for_ss = %u\n", __func__, k, is_using_mall_for_ss[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, TotalSurfaceSizeInMALL = %u\n", __func__, k, TotalSurfaceSizeInMALL);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	SurfaceToAddToMALL = 0;</div><div class='add'>+	CanAddAnotherSurfaceToMALL = true;</div><div class='add'>+	while (CanAddAnotherSurfaceToMALL) {</div><div class='add'>+		CanAddAnotherSurfaceToMALL = false;</div><div class='add'>+		for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+			if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] &lt;= MALLAllocatedForDCN * 1024 * 1024 &amp;&amp;</div><div class='add'>+				!is_using_mall_for_ss[k] &amp;&amp; display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall != dml2_refresh_from_mall_mode_override_force_disable &amp;&amp; one_row_per_frame_fits_in_buffer[k] &amp;&amp;</div><div class='add'>+				(!CanAddAnotherSurfaceToMALL || SurfaceSizeInMALL[k] &lt; SurfaceSizeInMALL[SurfaceToAddToMALL])) {</div><div class='add'>+				CanAddAnotherSurfaceToMALL = true;</div><div class='add'>+				SurfaceToAddToMALL = k;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, UseMALLForStaticScreen = %u (dis, en, optimize)\n", __func__, k, display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (CanAddAnotherSurfaceToMALL) {</div><div class='add'>+			is_using_mall_for_ss[SurfaceToAddToMALL] = true;</div><div class='add'>+			TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[SurfaceToAddToMALL];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: SurfaceToAddToMALL = %u\n", __func__, SurfaceToAddToMALL);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: TotalSurfaceSizeInMALL = %u\n", __func__, TotalSurfaceSizeInMALL);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateDCCConfiguration(</div><div class='add'>+	bool DCCEnabled,</div><div class='add'>+	bool DCCProgrammingAssumesScanDirectionUnknown,</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat,</div><div class='add'>+	unsigned int SurfaceWidthLuma,</div><div class='add'>+	unsigned int SurfaceWidthChroma,</div><div class='add'>+	unsigned int SurfaceHeightLuma,</div><div class='add'>+	unsigned int SurfaceHeightChroma,</div><div class='add'>+	unsigned int nomDETInKByte,</div><div class='add'>+	unsigned int RequestHeight256ByteLuma,</div><div class='add'>+	unsigned int RequestHeight256ByteChroma,</div><div class='add'>+	enum dml2_swizzle_mode TilingFormat,</div><div class='add'>+	unsigned int BytePerPixelY,</div><div class='add'>+	unsigned int BytePerPixelC,</div><div class='add'>+	double BytePerPixelDETY,</div><div class='add'>+	double BytePerPixelDETC,</div><div class='add'>+	enum dml2_rotation_angle RotationAngle,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	enum dml2_core_internal_request_type *RequestLuma,</div><div class='add'>+	enum dml2_core_internal_request_type *RequestChroma,</div><div class='add'>+	unsigned int *MaxUncompressedBlockLuma,</div><div class='add'>+	unsigned int *MaxUncompressedBlockChroma,</div><div class='add'>+	unsigned int *MaxCompressedBlockLuma,</div><div class='add'>+	unsigned int *MaxCompressedBlockChroma,</div><div class='add'>+	unsigned int *IndependentBlockLuma,</div><div class='add'>+	unsigned int *IndependentBlockChroma)</div><div class='add'>+{</div><div class='add'>+	unsigned int DETBufferSizeForDCC = nomDETInKByte * 1024;</div><div class='add'>+</div><div class='add'>+	unsigned int segment_order_horz_contiguous_luma;</div><div class='add'>+	unsigned int segment_order_horz_contiguous_chroma;</div><div class='add'>+	unsigned int segment_order_vert_contiguous_luma;</div><div class='add'>+	unsigned int segment_order_vert_contiguous_chroma;</div><div class='add'>+</div><div class='add'>+	unsigned int req128_horz_wc_l;</div><div class='add'>+	unsigned int req128_horz_wc_c;</div><div class='add'>+	unsigned int req128_vert_wc_l;</div><div class='add'>+	unsigned int req128_vert_wc_c;</div><div class='add'>+</div><div class='add'>+	unsigned int yuv420;</div><div class='add'>+	unsigned int horz_div_l;</div><div class='add'>+	unsigned int horz_div_c;</div><div class='add'>+	unsigned int vert_div_l;</div><div class='add'>+	unsigned int vert_div_c;</div><div class='add'>+</div><div class='add'>+	unsigned int swath_buf_size;</div><div class='add'>+	double detile_buf_vp_horz_limit;</div><div class='add'>+	double detile_buf_vp_vert_limit;</div><div class='add'>+</div><div class='add'>+	unsigned int MAS_vp_horz_limit;</div><div class='add'>+	unsigned int MAS_vp_vert_limit;</div><div class='add'>+	unsigned int max_vp_horz_width;</div><div class='add'>+	unsigned int max_vp_vert_height;</div><div class='add'>+	unsigned int eff_surf_width_l;</div><div class='add'>+	unsigned int eff_surf_width_c;</div><div class='add'>+	unsigned int eff_surf_height_l;</div><div class='add'>+	unsigned int eff_surf_height_c;</div><div class='add'>+</div><div class='add'>+	unsigned int full_swath_bytes_horz_wc_l;</div><div class='add'>+	unsigned int full_swath_bytes_horz_wc_c;</div><div class='add'>+	unsigned int full_swath_bytes_vert_wc_l;</div><div class='add'>+	unsigned int full_swath_bytes_vert_wc_c;</div><div class='add'>+</div><div class='add'>+	if (dml_is_420(SourcePixelFormat))</div><div class='add'>+		yuv420 = 1;</div><div class='add'>+	else</div><div class='add'>+		yuv420 = 0;</div><div class='add'>+	horz_div_l = 1;</div><div class='add'>+	horz_div_c = 1;</div><div class='add'>+	vert_div_l = 1;</div><div class='add'>+	vert_div_c = 1;</div><div class='add'>+</div><div class='add'>+	if (BytePerPixelY == 1)</div><div class='add'>+		vert_div_l = 0;</div><div class='add'>+	if (BytePerPixelC == 1)</div><div class='add'>+		vert_div_c = 0;</div><div class='add'>+</div><div class='add'>+	if (BytePerPixelC == 0) {</div><div class='add'>+		swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 256;</div><div class='add'>+		detile_buf_vp_horz_limit = (double)swath_buf_size / ((double)RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l));</div><div class='add'>+		detile_buf_vp_vert_limit = (double)swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l));</div><div class='add'>+	} else {</div><div class='add'>+		swath_buf_size = DETBufferSizeForDCC / 2 - 2 * 2 * 256;</div><div class='add'>+		detile_buf_vp_horz_limit = (double)swath_buf_size / ((double)RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l) + (double)RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420));</div><div class='add'>+		detile_buf_vp_vert_limit = (double)swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma / (1 + vert_div_c) / (1 + yuv420));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (SourcePixelFormat == dml2_420_10) {</div><div class='add'>+		detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit;</div><div class='add'>+		detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	detile_buf_vp_horz_limit = math_floor2(detile_buf_vp_horz_limit - 1, 16);</div><div class='add'>+	detile_buf_vp_vert_limit = math_floor2(detile_buf_vp_vert_limit - 1, 16);</div><div class='add'>+</div><div class='add'>+	MAS_vp_horz_limit = SourcePixelFormat == dml2_rgbe_alpha ? 3840 : 6144;</div><div class='add'>+	MAS_vp_vert_limit = SourcePixelFormat == dml2_rgbe_alpha ? 3840 : (BytePerPixelY == 8 ? 3072 : 6144);</div><div class='add'>+	max_vp_horz_width = (unsigned int)(math_min2((double)MAS_vp_horz_limit, detile_buf_vp_horz_limit));</div><div class='add'>+	max_vp_vert_height = (unsigned int)(math_min2((double)MAS_vp_vert_limit, detile_buf_vp_vert_limit));</div><div class='add'>+	eff_surf_width_l = (SurfaceWidthLuma &gt; max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);</div><div class='add'>+	eff_surf_width_c = eff_surf_width_l / (1 + yuv420);</div><div class='add'>+	eff_surf_height_l = (SurfaceHeightLuma &gt; max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma);</div><div class='add'>+	eff_surf_height_c = eff_surf_height_l / (1 + yuv420);</div><div class='add'>+</div><div class='add'>+	full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;</div><div class='add'>+	full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma;</div><div class='add'>+	if (BytePerPixelC &gt; 0) {</div><div class='add'>+		full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC;</div><div class='add'>+		full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma;</div><div class='add'>+	} else {</div><div class='add'>+		full_swath_bytes_horz_wc_c = 0;</div><div class='add'>+		full_swath_bytes_vert_wc_c = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (SourcePixelFormat == dml2_420_10) {</div><div class='add'>+		full_swath_bytes_horz_wc_l = (unsigned int)(math_ceil2((double)full_swath_bytes_horz_wc_l * 2.0 / 3.0, 256.0));</div><div class='add'>+		full_swath_bytes_horz_wc_c = (unsigned int)(math_ceil2((double)full_swath_bytes_horz_wc_c * 2.0 / 3.0, 256.0));</div><div class='add'>+		full_swath_bytes_vert_wc_l = (unsigned int)(math_ceil2((double)full_swath_bytes_vert_wc_l * 2.0 / 3.0, 256.0));</div><div class='add'>+		full_swath_bytes_vert_wc_c = (unsigned int)(math_ceil2((double)full_swath_bytes_vert_wc_c * 2.0 / 3.0, 256.0));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c &lt;= DETBufferSizeForDCC) {</div><div class='add'>+		req128_horz_wc_l = 0;</div><div class='add'>+		req128_horz_wc_c = 0;</div><div class='add'>+	} else if (full_swath_bytes_horz_wc_l &lt; 1.5 * full_swath_bytes_horz_wc_c &amp;&amp; 2 * full_swath_bytes_horz_wc_l + full_swath_bytes_horz_wc_c &lt;= DETBufferSizeForDCC) {</div><div class='add'>+		req128_horz_wc_l = 0;</div><div class='add'>+		req128_horz_wc_c = 1;</div><div class='add'>+	} else if (full_swath_bytes_horz_wc_l &gt;= 1.5 * full_swath_bytes_horz_wc_c &amp;&amp; full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c &lt;= DETBufferSizeForDCC) {</div><div class='add'>+		req128_horz_wc_l = 1;</div><div class='add'>+		req128_horz_wc_c = 0;</div><div class='add'>+	} else {</div><div class='add'>+		req128_horz_wc_l = 1;</div><div class='add'>+		req128_horz_wc_c = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c &lt;= DETBufferSizeForDCC) {</div><div class='add'>+		req128_vert_wc_l = 0;</div><div class='add'>+		req128_vert_wc_c = 0;</div><div class='add'>+	} else if (full_swath_bytes_vert_wc_l &lt; 1.5 * full_swath_bytes_vert_wc_c &amp;&amp; 2 * full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c &lt;= DETBufferSizeForDCC) {</div><div class='add'>+		req128_vert_wc_l = 0;</div><div class='add'>+		req128_vert_wc_c = 1;</div><div class='add'>+	} else if (full_swath_bytes_vert_wc_l &gt;= 1.5 * full_swath_bytes_vert_wc_c &amp;&amp; full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c &lt;= DETBufferSizeForDCC) {</div><div class='add'>+		req128_vert_wc_l = 1;</div><div class='add'>+		req128_vert_wc_c = 0;</div><div class='add'>+	} else {</div><div class='add'>+		req128_vert_wc_l = 1;</div><div class='add'>+		req128_vert_wc_c = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (BytePerPixelY == 2) {</div><div class='add'>+		segment_order_horz_contiguous_luma = 0;</div><div class='add'>+		segment_order_vert_contiguous_luma = 1;</div><div class='add'>+	} else {</div><div class='add'>+		segment_order_horz_contiguous_luma = 1;</div><div class='add'>+		segment_order_vert_contiguous_luma = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (BytePerPixelC == 2) {</div><div class='add'>+		segment_order_horz_contiguous_chroma = 0;</div><div class='add'>+		segment_order_vert_contiguous_chroma = 1;</div><div class='add'>+	} else {</div><div class='add'>+		segment_order_horz_contiguous_chroma = 1;</div><div class='add'>+		segment_order_vert_contiguous_chroma = 0;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCCEnabled = %u\n", __func__, DCCEnabled);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: nomDETInKByte = %u\n", __func__, nomDETInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DETBufferSizeForDCC = %u\n", __func__, DETBufferSizeForDCC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: req128_horz_wc_l = %u\n", __func__, req128_horz_wc_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: req128_horz_wc_c = %u\n", __func__, req128_horz_wc_c);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: full_swath_bytes_horz_wc_l = %u\n", __func__, full_swath_bytes_horz_wc_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: full_swath_bytes_vert_wc_c = %u\n", __func__, full_swath_bytes_vert_wc_c);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: segment_order_horz_contiguous_luma = %u\n", __func__, segment_order_horz_contiguous_luma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: segment_order_horz_contiguous_chroma = %u\n", __func__, segment_order_horz_contiguous_chroma);</div><div class='add'>+#endif</div><div class='add'>+	if (DCCProgrammingAssumesScanDirectionUnknown == true) {</div><div class='add'>+		if (req128_horz_wc_l == 0 &amp;&amp; req128_vert_wc_l == 0) {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_256_bytes;</div><div class='add'>+		} else if ((req128_horz_wc_l == 1 &amp;&amp; segment_order_horz_contiguous_luma == 0) || (req128_vert_wc_l == 1 &amp;&amp; segment_order_vert_contiguous_luma == 0)) {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_128_bytes_non_contiguous;</div><div class='add'>+		} else {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_128_bytes_contiguous;</div><div class='add'>+		}</div><div class='add'>+		if (req128_horz_wc_c == 0 &amp;&amp; req128_vert_wc_c == 0) {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_256_bytes;</div><div class='add'>+		} else if ((req128_horz_wc_c == 1 &amp;&amp; segment_order_horz_contiguous_chroma == 0) || (req128_vert_wc_c == 1 &amp;&amp; segment_order_vert_contiguous_chroma == 0)) {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_128_bytes_non_contiguous;</div><div class='add'>+		} else {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_128_bytes_contiguous;</div><div class='add'>+		}</div><div class='add'>+	} else if (!dml_is_vertical_rotation(RotationAngle)) {</div><div class='add'>+		if (req128_horz_wc_l == 0) {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_256_bytes;</div><div class='add'>+		} else if (segment_order_horz_contiguous_luma == 0) {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_128_bytes_non_contiguous;</div><div class='add'>+		} else {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_128_bytes_contiguous;</div><div class='add'>+		}</div><div class='add'>+		if (req128_horz_wc_c == 0) {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_256_bytes;</div><div class='add'>+		} else if (segment_order_horz_contiguous_chroma == 0) {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_128_bytes_non_contiguous;</div><div class='add'>+		} else {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_128_bytes_contiguous;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (req128_vert_wc_l == 0) {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_256_bytes;</div><div class='add'>+		} else if (segment_order_vert_contiguous_luma == 0) {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_128_bytes_non_contiguous;</div><div class='add'>+		} else {</div><div class='add'>+			*RequestLuma = dml2_core_internal_request_type_128_bytes_contiguous;</div><div class='add'>+		}</div><div class='add'>+		if (req128_vert_wc_c == 0) {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_256_bytes;</div><div class='add'>+		} else if (segment_order_vert_contiguous_chroma == 0) {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_128_bytes_non_contiguous;</div><div class='add'>+		} else {</div><div class='add'>+			*RequestChroma = dml2_core_internal_request_type_128_bytes_contiguous;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (*RequestLuma == dml2_core_internal_request_type_256_bytes) {</div><div class='add'>+		*MaxUncompressedBlockLuma = 256;</div><div class='add'>+		*MaxCompressedBlockLuma = 256;</div><div class='add'>+		*IndependentBlockLuma = 0;</div><div class='add'>+	} else if (*RequestLuma == dml2_core_internal_request_type_128_bytes_contiguous) {</div><div class='add'>+		*MaxUncompressedBlockLuma = 256;</div><div class='add'>+		*MaxCompressedBlockLuma = 128;</div><div class='add'>+		*IndependentBlockLuma = 128;</div><div class='add'>+	} else {</div><div class='add'>+		*MaxUncompressedBlockLuma = 256;</div><div class='add'>+		*MaxCompressedBlockLuma = 64;</div><div class='add'>+		*IndependentBlockLuma = 64;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (*RequestChroma == dml2_core_internal_request_type_256_bytes) {</div><div class='add'>+		*MaxUncompressedBlockChroma = 256;</div><div class='add'>+		*MaxCompressedBlockChroma = 256;</div><div class='add'>+		*IndependentBlockChroma = 0;</div><div class='add'>+	} else if (*RequestChroma == dml2_core_internal_request_type_128_bytes_contiguous) {</div><div class='add'>+		*MaxUncompressedBlockChroma = 256;</div><div class='add'>+		*MaxCompressedBlockChroma = 128;</div><div class='add'>+		*IndependentBlockChroma = 128;</div><div class='add'>+	} else {</div><div class='add'>+		*MaxUncompressedBlockChroma = 256;</div><div class='add'>+		*MaxCompressedBlockChroma = 64;</div><div class='add'>+		*IndependentBlockChroma = 64;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (DCCEnabled != true || BytePerPixelC == 0) {</div><div class='add'>+		*MaxUncompressedBlockChroma = 0;</div><div class='add'>+		*MaxCompressedBlockChroma = 0;</div><div class='add'>+		*IndependentBlockChroma = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (DCCEnabled != true) {</div><div class='add'>+		*MaxUncompressedBlockLuma = 0;</div><div class='add'>+		*MaxCompressedBlockLuma = 0;</div><div class='add'>+		*IndependentBlockLuma = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxUncompressedBlockLuma = %u\n", __func__, *MaxUncompressedBlockLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxCompressedBlockLuma = %u\n", __func__, *MaxCompressedBlockLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: IndependentBlockLuma = %u\n", __func__, *IndependentBlockLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxUncompressedBlockChroma = %u\n", __func__, *MaxUncompressedBlockChroma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxCompressedBlockChroma = %u\n", __func__, *MaxCompressedBlockChroma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: IndependentBlockChroma = %u\n", __func__, *IndependentBlockChroma);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_mcache_row_bytes(</div><div class='add'>+	struct dml2_core_internal_scratch *scratch,</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_row_bytes_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int vmpg_bytes = 0;</div><div class='add'>+	unsigned int blk_bytes = 0;</div><div class='add'>+	float meta_per_mvmpg_per_channel = 0;</div><div class='add'>+	unsigned int est_blk_per_vmpg = 2;</div><div class='add'>+	unsigned int mvmpg_per_row_ub = 0;</div><div class='add'>+	unsigned int full_vp_width_mvmpg_aligned = 0;</div><div class='add'>+	unsigned int full_vp_height_mvmpg_aligned = 0;</div><div class='add'>+	unsigned int meta_per_mvmpg_per_channel_ub = 0;</div><div class='add'>+	unsigned int mvmpg_per_mcache;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_chans = %u\n", __func__, p-&gt;num_chans);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mem_word_bytes = %u\n", __func__, p-&gt;mem_word_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mcache_line_size_bytes = %u\n", __func__, p-&gt;mcache_line_size_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mcache_size_bytes = %u\n", __func__, p-&gt;mcache_size_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: gpuvm_enable = %u\n", __func__, p-&gt;gpuvm_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: gpuvm_page_size_kbytes = %u\n", __func__, p-&gt;gpuvm_page_size_kbytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vp_stationary = %u\n", __func__, p-&gt;vp_stationary);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tiling_mode = %u\n", __func__, p-&gt;tiling_mode);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vp_start_x = %u\n", __func__, p-&gt;vp_start_x);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vp_start_y = %u\n", __func__, p-&gt;vp_start_y);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: full_vp_width = %u\n", __func__, p-&gt;full_vp_width);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: full_vp_height = %u\n", __func__, p-&gt;full_vp_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: blk_width = %u\n", __func__, p-&gt;blk_width);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: blk_height = %u\n", __func__, p-&gt;blk_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vmpg_width = %u\n", __func__, p-&gt;vmpg_width);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vmpg_height = %u\n", __func__, p-&gt;vmpg_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: full_swath_bytes = %u\n", __func__, p-&gt;full_swath_bytes);</div><div class='add'>+#endif</div><div class='add'>+	DML_ASSERT(p-&gt;mcache_line_size_bytes != 0);</div><div class='add'>+	DML_ASSERT(p-&gt;mcache_size_bytes != 0);</div><div class='add'>+</div><div class='add'>+	*p-&gt;mvmpg_width = 0;</div><div class='add'>+	*p-&gt;mvmpg_height = 0;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;full_vp_height == 0 &amp;&amp; p-&gt;full_vp_width == 0) {</div><div class='add'>+		*p-&gt;num_mcaches = 0;</div><div class='add'>+		*p-&gt;mcache_row_bytes = 0;</div><div class='add'>+		*p-&gt;mcache_row_bytes_per_channel = 0;</div><div class='add'>+	} else {</div><div class='add'>+		blk_bytes = dml_get_tile_block_size_bytes(p-&gt;tiling_mode);</div><div class='add'>+</div><div class='add'>+		// if gpuvm is not enable, the alignment boundary should be in terms of tiling block size</div><div class='add'>+		vmpg_bytes = p-&gt;gpuvm_page_size_kbytes * 1024;</div><div class='add'>+</div><div class='add'>+		//With vmpg_bytes &gt;= tile blk_bytes, the meta_row_width alignment equations are relative to the vmpg_width/height.</div><div class='add'>+		// But for 4KB page with 64KB tile block, we need the meta for all pages in the tile block.</div><div class='add'>+		// Therefore, the alignment is relative to the blk_width/height. The factor of 16 vmpg per 64KB tile block is applied at the end.</div><div class='add'>+		*p-&gt;mvmpg_width = p-&gt;blk_width;</div><div class='add'>+		*p-&gt;mvmpg_height = p-&gt;blk_height;</div><div class='add'>+		if (p-&gt;gpuvm_enable) {</div><div class='add'>+			if (vmpg_bytes &gt;= blk_bytes) {</div><div class='add'>+				*p-&gt;mvmpg_width = p-&gt;vmpg_width;</div><div class='add'>+				*p-&gt;mvmpg_height = p-&gt;vmpg_height;</div><div class='add'>+			} else if (!((blk_bytes == 65536) &amp;&amp; (vmpg_bytes == 4096))) {</div><div class='add'>+				DML_LOG_VERBOSE("ERROR: DML::%s: Tiling size and vm page size combination not supported\n", __func__);</div><div class='add'>+				DML_ASSERT(0);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		//For plane0 &amp; 1, first calculate full_vp_width/height_l/c aligned to vmpg_width/height_l/c</div><div class='add'>+		full_vp_width_mvmpg_aligned = (unsigned int)(math_floor2((p-&gt;vp_start_x + p-&gt;full_vp_width) + *p-&gt;mvmpg_width - 1, *p-&gt;mvmpg_width) - math_floor2(p-&gt;vp_start_x, *p-&gt;mvmpg_width));</div><div class='add'>+		full_vp_height_mvmpg_aligned = (unsigned int)(math_floor2((p-&gt;vp_start_y + p-&gt;full_vp_height) + *p-&gt;mvmpg_height - 1, *p-&gt;mvmpg_height) - math_floor2(p-&gt;vp_start_y, *p-&gt;mvmpg_height));</div><div class='add'>+</div><div class='add'>+		*p-&gt;full_vp_access_width_mvmpg_aligned = p-&gt;surf_vert ? full_vp_height_mvmpg_aligned : full_vp_width_mvmpg_aligned;</div><div class='add'>+</div><div class='add'>+		//Use the equation for the exact alignment when possible. Note that the exact alignment cannot be used for horizontal access if vmpg_bytes &gt; blk_bytes.</div><div class='add'>+		if (!p-&gt;surf_vert) { //horizontal access</div><div class='add'>+			if (p-&gt;vp_stationary == 1 &amp;&amp; vmpg_bytes &lt;= blk_bytes)</div><div class='add'>+				*p-&gt;meta_row_width_ub = full_vp_width_mvmpg_aligned;</div><div class='add'>+			else</div><div class='add'>+				*p-&gt;meta_row_width_ub = (unsigned int)math_ceil2((double)p-&gt;full_vp_width - 1, *p-&gt;mvmpg_width) + *p-&gt;mvmpg_width;</div><div class='add'>+			mvmpg_per_row_ub = *p-&gt;meta_row_width_ub / *p-&gt;mvmpg_width;</div><div class='add'>+		} else { //vertical access</div><div class='add'>+			if (p-&gt;vp_stationary == 1)</div><div class='add'>+				*p-&gt;meta_row_width_ub = full_vp_height_mvmpg_aligned;</div><div class='add'>+			else</div><div class='add'>+				*p-&gt;meta_row_width_ub = (unsigned int)math_ceil2((double)p-&gt;full_vp_height - 1, *p-&gt;mvmpg_height) + *p-&gt;mvmpg_height;</div><div class='add'>+			mvmpg_per_row_ub = *p-&gt;meta_row_width_ub / *p-&gt;mvmpg_height;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;gpuvm_enable) {</div><div class='add'>+			meta_per_mvmpg_per_channel = (float)vmpg_bytes / (float)256 / p-&gt;num_chans;</div><div class='add'>+</div><div class='add'>+			//but using the est_blk_per_vmpg between 2 and 4, to be not as pessimestic</div><div class='add'>+			if (p-&gt;surf_vert &amp;&amp; vmpg_bytes &gt; blk_bytes) {</div><div class='add'>+				meta_per_mvmpg_per_channel = (float)est_blk_per_vmpg * blk_bytes / (float)256 / p-&gt;num_chans;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			*p-&gt;dcc_dram_bw_nom_overhead_factor = 1 + math_max2(1.0 / 256.0, math_ceil2(meta_per_mvmpg_per_channel, p-&gt;mem_word_bytes) / (256 * meta_per_mvmpg_per_channel)); // dcc_dr_oh_nom</div><div class='add'>+		} else {</div><div class='add'>+			meta_per_mvmpg_per_channel = (float) blk_bytes / (float)256 / p-&gt;num_chans;</div><div class='add'>+</div><div class='add'>+			if (!p-&gt;surf_vert)</div><div class='add'>+				*p-&gt;dcc_dram_bw_nom_overhead_factor = 1 + 1.0 / 256.0;</div><div class='add'>+			else</div><div class='add'>+				 *p-&gt;dcc_dram_bw_nom_overhead_factor = 1 + math_max2(1.0 / 256.0, math_ceil2(meta_per_mvmpg_per_channel, p-&gt;mem_word_bytes) / (256 * meta_per_mvmpg_per_channel));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		meta_per_mvmpg_per_channel_ub = (unsigned int)math_ceil2((double)meta_per_mvmpg_per_channel, p-&gt;mcache_line_size_bytes);</div><div class='add'>+</div><div class='add'>+		//but for 4KB vmpg with 64KB tile blk</div><div class='add'>+		if (p-&gt;gpuvm_enable &amp;&amp; (blk_bytes == 65536) &amp;&amp; (vmpg_bytes == 4096))</div><div class='add'>+			meta_per_mvmpg_per_channel_ub = 16 * meta_per_mvmpg_per_channel_ub;</div><div class='add'>+</div><div class='add'>+		// If this mcache_row_bytes for the full viewport of the surface is less than or equal to mcache_bytes,</div><div class='add'>+		// then one mcache can be used for this request stream. If not, it is useful to know the width of the viewport that can be supported in the mcache_bytes.</div><div class='add'>+		if (p-&gt;gpuvm_enable || p-&gt;surf_vert) {</div><div class='add'>+			*p-&gt;mcache_row_bytes_per_channel = mvmpg_per_row_ub * meta_per_mvmpg_per_channel_ub;</div><div class='add'>+			*p-&gt;mcache_row_bytes = *p-&gt;mcache_row_bytes_per_channel * p-&gt;num_chans;</div><div class='add'>+		} else { // horizontal and gpuvm disable</div><div class='add'>+			*p-&gt;mcache_row_bytes = *p-&gt;meta_row_width_ub * p-&gt;blk_height * p-&gt;bytes_per_pixel / 256;</div><div class='add'>+			if (p-&gt;mcache_line_size_bytes != 0)</div><div class='add'>+				*p-&gt;mcache_row_bytes_per_channel = (unsigned int)math_ceil2((double)*p-&gt;mcache_row_bytes / p-&gt;num_chans, p-&gt;mcache_line_size_bytes);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*p-&gt;dcc_dram_bw_pref_overhead_factor = 1 + math_max2(1.0 / 256.0, *p-&gt;mcache_row_bytes / p-&gt;full_swath_bytes); // dcc_dr_oh_pref</div><div class='add'>+		if (p-&gt;mcache_size_bytes != 0)</div><div class='add'>+			*p-&gt;num_mcaches = (unsigned int)math_ceil2((double)*p-&gt;mcache_row_bytes_per_channel / p-&gt;mcache_size_bytes, 1);</div><div class='add'>+</div><div class='add'>+		mvmpg_per_mcache = p-&gt;mcache_size_bytes / meta_per_mvmpg_per_channel_ub;</div><div class='add'>+		*p-&gt;mvmpg_per_mcache_lb = (unsigned int)math_floor2(mvmpg_per_mcache, 1);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: gpuvm_enable = %u\n", __func__, p-&gt;gpuvm_enable);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: vmpg_bytes = %u\n", __func__, vmpg_bytes);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: blk_bytes = %u\n", __func__, blk_bytes);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: meta_per_mvmpg_per_channel = %f\n", __func__, meta_per_mvmpg_per_channel);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mvmpg_per_row_ub = %u\n", __func__, mvmpg_per_row_ub);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: meta_row_width_ub = %u\n", __func__, *p-&gt;meta_row_width_ub);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mvmpg_width = %u\n", __func__, *p-&gt;mvmpg_width);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mvmpg_height = %u\n", __func__, *p-&gt;mvmpg_height);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor = %f\n", __func__, *p-&gt;dcc_dram_bw_nom_overhead_factor);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_pref_overhead_factor = %f\n", __func__, *p-&gt;dcc_dram_bw_pref_overhead_factor);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mcache_row_bytes = %u\n", __func__, *p-&gt;mcache_row_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mcache_row_bytes_per_channel = %u\n", __func__, *p-&gt;mcache_row_bytes_per_channel);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_mcaches = %u\n", __func__, *p-&gt;num_mcaches);</div><div class='add'>+#endif</div><div class='add'>+	DML_ASSERT(*p-&gt;num_mcaches &gt; 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_mcache_setting(</div><div class='add'>+	struct dml2_core_internal_scratch *scratch,</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_setting_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int n;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_shared_calculate_mcache_setting_locals *l = &amp;scratch-&gt;calculate_mcache_setting_locals;</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_core_shared_calculate_mcache_setting_locals));</div><div class='add'>+</div><div class='add'>+	*p-&gt;num_mcaches_l = 0;</div><div class='add'>+	*p-&gt;mcache_row_bytes_l = 0;</div><div class='add'>+	*p-&gt;mcache_row_bytes_per_channel_l = 0;</div><div class='add'>+	*p-&gt;dcc_dram_bw_nom_overhead_factor_l = 1.0;</div><div class='add'>+	*p-&gt;dcc_dram_bw_pref_overhead_factor_l = 1.0;</div><div class='add'>+</div><div class='add'>+	*p-&gt;num_mcaches_c = 0;</div><div class='add'>+	*p-&gt;mcache_row_bytes_c = 0;</div><div class='add'>+	*p-&gt;mcache_row_bytes_per_channel_c = 0;</div><div class='add'>+	*p-&gt;dcc_dram_bw_nom_overhead_factor_c = 1.0;</div><div class='add'>+	*p-&gt;dcc_dram_bw_pref_overhead_factor_c = 1.0;</div><div class='add'>+</div><div class='add'>+	*p-&gt;mall_comb_mcache_l = 0;</div><div class='add'>+	*p-&gt;mall_comb_mcache_c = 0;</div><div class='add'>+	*p-&gt;lc_comb_mcache = 0;</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;dcc_enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	l-&gt;is_dual_plane = dml_is_420(p-&gt;source_format) || p-&gt;source_format == dml2_rgbe_alpha;</div><div class='add'>+</div><div class='add'>+	l-&gt;l_p.num_chans = p-&gt;num_chans;</div><div class='add'>+	l-&gt;l_p.mem_word_bytes = p-&gt;mem_word_bytes;</div><div class='add'>+	l-&gt;l_p.mcache_size_bytes = p-&gt;mcache_size_bytes;</div><div class='add'>+	l-&gt;l_p.mcache_line_size_bytes = p-&gt;mcache_line_size_bytes;</div><div class='add'>+	l-&gt;l_p.gpuvm_enable = p-&gt;gpuvm_enable;</div><div class='add'>+	l-&gt;l_p.gpuvm_page_size_kbytes = p-&gt;gpuvm_page_size_kbytes;</div><div class='add'>+	l-&gt;l_p.surf_vert = p-&gt;surf_vert;</div><div class='add'>+	l-&gt;l_p.vp_stationary = p-&gt;vp_stationary;</div><div class='add'>+	l-&gt;l_p.tiling_mode = p-&gt;tiling_mode;</div><div class='add'>+	l-&gt;l_p.vp_start_x = p-&gt;vp_start_x_l;</div><div class='add'>+	l-&gt;l_p.vp_start_y = p-&gt;vp_start_y_l;</div><div class='add'>+	l-&gt;l_p.full_vp_width = p-&gt;full_vp_width_l;</div><div class='add'>+	l-&gt;l_p.full_vp_height = p-&gt;full_vp_height_l;</div><div class='add'>+	l-&gt;l_p.blk_width = p-&gt;blk_width_l;</div><div class='add'>+	l-&gt;l_p.blk_height = p-&gt;blk_height_l;</div><div class='add'>+	l-&gt;l_p.vmpg_width = p-&gt;vmpg_width_l;</div><div class='add'>+	l-&gt;l_p.vmpg_height = p-&gt;vmpg_height_l;</div><div class='add'>+	l-&gt;l_p.full_swath_bytes = p-&gt;full_swath_bytes_l;</div><div class='add'>+	l-&gt;l_p.bytes_per_pixel = p-&gt;bytes_per_pixel_l;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	l-&gt;l_p.num_mcaches = p-&gt;num_mcaches_l;</div><div class='add'>+	l-&gt;l_p.mcache_row_bytes = p-&gt;mcache_row_bytes_l;</div><div class='add'>+	l-&gt;l_p.mcache_row_bytes_per_channel = p-&gt;mcache_row_bytes_per_channel_l;</div><div class='add'>+	l-&gt;l_p.dcc_dram_bw_nom_overhead_factor = p-&gt;dcc_dram_bw_nom_overhead_factor_l;</div><div class='add'>+	l-&gt;l_p.dcc_dram_bw_pref_overhead_factor = p-&gt;dcc_dram_bw_pref_overhead_factor_l;</div><div class='add'>+	l-&gt;l_p.mvmpg_width = &amp;l-&gt;mvmpg_width_l;</div><div class='add'>+	l-&gt;l_p.mvmpg_height = &amp;l-&gt;mvmpg_height_l;</div><div class='add'>+	l-&gt;l_p.full_vp_access_width_mvmpg_aligned = &amp;l-&gt;full_vp_access_width_mvmpg_aligned_l;</div><div class='add'>+	l-&gt;l_p.meta_row_width_ub = &amp;l-&gt;meta_row_width_l;</div><div class='add'>+	l-&gt;l_p.mvmpg_per_mcache_lb = &amp;l-&gt;mvmpg_per_mcache_lb_l;</div><div class='add'>+</div><div class='add'>+	calculate_mcache_row_bytes(scratch, &amp;l-&gt;l_p);</div><div class='add'>+	DML_ASSERT(*p-&gt;num_mcaches_l &gt; 0);</div><div class='add'>+</div><div class='add'>+	if (l-&gt;is_dual_plane) {</div><div class='add'>+		l-&gt;c_p.num_chans = p-&gt;num_chans;</div><div class='add'>+		l-&gt;c_p.mem_word_bytes = p-&gt;mem_word_bytes;</div><div class='add'>+		l-&gt;c_p.mcache_size_bytes = p-&gt;mcache_size_bytes;</div><div class='add'>+		l-&gt;c_p.mcache_line_size_bytes = p-&gt;mcache_line_size_bytes;</div><div class='add'>+		l-&gt;c_p.gpuvm_enable = p-&gt;gpuvm_enable;</div><div class='add'>+		l-&gt;c_p.gpuvm_page_size_kbytes = p-&gt;gpuvm_page_size_kbytes;</div><div class='add'>+		l-&gt;c_p.surf_vert = p-&gt;surf_vert;</div><div class='add'>+		l-&gt;c_p.vp_stationary = p-&gt;vp_stationary;</div><div class='add'>+		l-&gt;c_p.tiling_mode = p-&gt;tiling_mode;</div><div class='add'>+		l-&gt;c_p.vp_start_x = p-&gt;vp_start_x_c;</div><div class='add'>+		l-&gt;c_p.vp_start_y = p-&gt;vp_start_y_c;</div><div class='add'>+		l-&gt;c_p.full_vp_width = p-&gt;full_vp_width_c;</div><div class='add'>+		l-&gt;c_p.full_vp_height = p-&gt;full_vp_height_c;</div><div class='add'>+		l-&gt;c_p.blk_width = p-&gt;blk_width_c;</div><div class='add'>+		l-&gt;c_p.blk_height = p-&gt;blk_height_c;</div><div class='add'>+		l-&gt;c_p.vmpg_width = p-&gt;vmpg_width_c;</div><div class='add'>+		l-&gt;c_p.vmpg_height = p-&gt;vmpg_height_c;</div><div class='add'>+		l-&gt;c_p.full_swath_bytes = p-&gt;full_swath_bytes_c;</div><div class='add'>+		l-&gt;c_p.bytes_per_pixel = p-&gt;bytes_per_pixel_c;</div><div class='add'>+</div><div class='add'>+		// output</div><div class='add'>+		l-&gt;c_p.num_mcaches = p-&gt;num_mcaches_c;</div><div class='add'>+		l-&gt;c_p.mcache_row_bytes = p-&gt;mcache_row_bytes_c;</div><div class='add'>+		l-&gt;c_p.mcache_row_bytes_per_channel = p-&gt;mcache_row_bytes_per_channel_c;</div><div class='add'>+		l-&gt;c_p.dcc_dram_bw_nom_overhead_factor = p-&gt;dcc_dram_bw_nom_overhead_factor_c;</div><div class='add'>+		l-&gt;c_p.dcc_dram_bw_pref_overhead_factor = p-&gt;dcc_dram_bw_pref_overhead_factor_c;</div><div class='add'>+		l-&gt;c_p.mvmpg_width = &amp;l-&gt;mvmpg_width_c;</div><div class='add'>+		l-&gt;c_p.mvmpg_height = &amp;l-&gt;mvmpg_height_c;</div><div class='add'>+		l-&gt;c_p.full_vp_access_width_mvmpg_aligned = &amp;l-&gt;full_vp_access_width_mvmpg_aligned_c;</div><div class='add'>+		l-&gt;c_p.meta_row_width_ub = &amp;l-&gt;meta_row_width_c;</div><div class='add'>+		l-&gt;c_p.mvmpg_per_mcache_lb = &amp;l-&gt;mvmpg_per_mcache_lb_c;</div><div class='add'>+</div><div class='add'>+		calculate_mcache_row_bytes(scratch, &amp;l-&gt;c_p);</div><div class='add'>+		DML_ASSERT(*p-&gt;num_mcaches_c &gt; 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Sharing for iMALL access</div><div class='add'>+	l-&gt;mcache_remainder_l = *p-&gt;mcache_row_bytes_per_channel_l % p-&gt;mcache_size_bytes;</div><div class='add'>+	l-&gt;mcache_remainder_c = *p-&gt;mcache_row_bytes_per_channel_c % p-&gt;mcache_size_bytes;</div><div class='add'>+	l-&gt;mvmpg_access_width_l = p-&gt;surf_vert ? l-&gt;mvmpg_height_l : l-&gt;mvmpg_width_l;</div><div class='add'>+	l-&gt;mvmpg_access_width_c = p-&gt;surf_vert ? l-&gt;mvmpg_height_c : l-&gt;mvmpg_width_c;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;imall_enable) {</div><div class='add'>+		*p-&gt;mall_comb_mcache_l = (2 * l-&gt;mcache_remainder_l &lt;= p-&gt;mcache_size_bytes);</div><div class='add'>+</div><div class='add'>+		if (l-&gt;is_dual_plane)</div><div class='add'>+			*p-&gt;mall_comb_mcache_c = (2 * l-&gt;mcache_remainder_c &lt;= p-&gt;mcache_size_bytes);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;surf_vert) // horizonatal access</div><div class='add'>+		l-&gt;luma_time_factor = (double)l-&gt;mvmpg_height_c / l-&gt;mvmpg_height_l * 2;</div><div class='add'>+	else // vertical access</div><div class='add'>+		l-&gt;luma_time_factor = (double)l-&gt;mvmpg_width_c / l-&gt;mvmpg_width_l * 2;</div><div class='add'>+</div><div class='add'>+	// The algorithm starts with computing a non-integer, avg_mcache_element_size_l/c:</div><div class='add'>+	if (*p-&gt;num_mcaches_l) {</div><div class='add'>+		l-&gt;avg_mcache_element_size_l = l-&gt;meta_row_width_l / *p-&gt;num_mcaches_l;</div><div class='add'>+	}</div><div class='add'>+	if (l-&gt;is_dual_plane) {</div><div class='add'>+		l-&gt;avg_mcache_element_size_c = l-&gt;meta_row_width_c / *p-&gt;num_mcaches_c;</div><div class='add'>+</div><div class='add'>+		/* if either remainder is 0, then mcache sharing is not needed or not possible due to full utilization */</div><div class='add'>+		if (l-&gt;mcache_remainder_l &amp;&amp; l-&gt;mcache_remainder_c) {</div><div class='add'>+			if (!p-&gt;imall_enable || (*p-&gt;mall_comb_mcache_l == *p-&gt;mall_comb_mcache_c)) {</div><div class='add'>+				l-&gt;lc_comb_last_mcache_size = (unsigned int)((l-&gt;mcache_remainder_l * (*p-&gt;mall_comb_mcache_l ? 2 : 1) * l-&gt;luma_time_factor) +</div><div class='add'>+					(l-&gt;mcache_remainder_c * (*p-&gt;mall_comb_mcache_c ? 2 : 1)));</div><div class='add'>+			}</div><div class='add'>+			*p-&gt;lc_comb_mcache = (l-&gt;lc_comb_last_mcache_size &lt;= p-&gt;mcache_size_bytes) &amp;&amp; (*p-&gt;mall_comb_mcache_l == *p-&gt;mall_comb_mcache_c);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: imall_enable = %u\n", __func__, p-&gt;imall_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: is_dual_plane = %u\n", __func__, l-&gt;is_dual_plane);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: surf_vert = %u\n", __func__, p-&gt;surf_vert);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mvmpg_width_l = %u\n", __func__, l-&gt;mvmpg_width_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mvmpg_height_l = %u\n", __func__, l-&gt;mvmpg_height_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mcache_remainder_l = %f\n", __func__, l-&gt;mcache_remainder_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_mcaches_l = %u\n", __func__, *p-&gt;num_mcaches_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: avg_mcache_element_size_l = %u\n", __func__, l-&gt;avg_mcache_element_size_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mvmpg_access_width_l = %u\n", __func__, l-&gt;mvmpg_access_width_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mall_comb_mcache_l = %u\n", __func__, *p-&gt;mall_comb_mcache_l);</div><div class='add'>+</div><div class='add'>+	if (l-&gt;is_dual_plane) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mvmpg_width_c = %u\n", __func__, l-&gt;mvmpg_width_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mvmpg_height_c = %u\n", __func__, l-&gt;mvmpg_height_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mcache_remainder_c = %f\n", __func__, l-&gt;mcache_remainder_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: luma_time_factor = %f\n", __func__, l-&gt;luma_time_factor);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: num_mcaches_c = %u\n", __func__, *p-&gt;num_mcaches_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: avg_mcache_element_size_c = %u\n", __func__, l-&gt;avg_mcache_element_size_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mvmpg_access_width_c = %u\n", __func__, l-&gt;mvmpg_access_width_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mall_comb_mcache_c = %u\n", __func__, *p-&gt;mall_comb_mcache_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: lc_comb_last_mcache_size = %u\n", __func__, l-&gt;lc_comb_last_mcache_size);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: lc_comb_mcache = %u\n", __func__, *p-&gt;lc_comb_mcache);</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+	// calculate split_coordinate</div><div class='add'>+	l-&gt;full_vp_access_width_l = p-&gt;surf_vert ? p-&gt;full_vp_height_l : p-&gt;full_vp_width_l;</div><div class='add'>+	l-&gt;full_vp_access_width_c = p-&gt;surf_vert ? p-&gt;full_vp_height_c : p-&gt;full_vp_width_c;</div><div class='add'>+</div><div class='add'>+	for (n = 0; n &lt; *p-&gt;num_mcaches_l - 1; n++) {</div><div class='add'>+		p-&gt;mcache_offsets_l[n] = (unsigned int)(math_floor2((n + 1) * l-&gt;avg_mcache_element_size_l / l-&gt;mvmpg_access_width_l, 1)) * l-&gt;mvmpg_access_width_l;</div><div class='add'>+	}</div><div class='add'>+	p-&gt;mcache_offsets_l[*p-&gt;num_mcaches_l - 1] = l-&gt;full_vp_access_width_l;</div><div class='add'>+</div><div class='add'>+	if (l-&gt;is_dual_plane) {</div><div class='add'>+		for (n = 0; n &lt; *p-&gt;num_mcaches_c - 1; n++) {</div><div class='add'>+			p-&gt;mcache_offsets_c[n] = (unsigned int)(math_floor2((n + 1) * l-&gt;avg_mcache_element_size_c / l-&gt;mvmpg_access_width_c, 1)) * l-&gt;mvmpg_access_width_c;</div><div class='add'>+		}</div><div class='add'>+		p-&gt;mcache_offsets_c[*p-&gt;num_mcaches_c - 1] = l-&gt;full_vp_access_width_c;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	for (n = 0; n &lt; *p-&gt;num_mcaches_l; n++)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mcache_offsets_l[%u] = %u\n", __func__, n, p-&gt;mcache_offsets_l[n]);</div><div class='add'>+</div><div class='add'>+	if (l-&gt;is_dual_plane) {</div><div class='add'>+		for (n = 0; n &lt; *p-&gt;num_mcaches_c; n++)</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: mcache_offsets_c[%u] = %u\n", __func__, n, p-&gt;mcache_offsets_c[n]);</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	// Luma/Chroma combine in the last mcache</div><div class='add'>+	// In the case of Luma/Chroma combine-mCache (with lc_comb_mcache==1), all mCaches except the last segment are filled as much as possible, when stay aligned to mvmpg boundary</div><div class='add'>+	if (*p-&gt;lc_comb_mcache &amp;&amp; l-&gt;is_dual_plane) {</div><div class='add'>+		for (n = 0; n &lt; *p-&gt;num_mcaches_l - 1; n++)</div><div class='add'>+			p-&gt;mcache_offsets_l[n] = (n + 1) * l-&gt;mvmpg_per_mcache_lb_l * l-&gt;mvmpg_access_width_l;</div><div class='add'>+		p-&gt;mcache_offsets_l[*p-&gt;num_mcaches_l - 1] = l-&gt;full_vp_access_width_l;</div><div class='add'>+</div><div class='add'>+		for (n = 0; n &lt; *p-&gt;num_mcaches_c - 1; n++)</div><div class='add'>+			p-&gt;mcache_offsets_c[n] = (n + 1) * l-&gt;mvmpg_per_mcache_lb_c * l-&gt;mvmpg_access_width_c;</div><div class='add'>+		p-&gt;mcache_offsets_c[*p-&gt;num_mcaches_c - 1] = l-&gt;full_vp_access_width_c;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		for (n = 0; n &lt; *p-&gt;num_mcaches_l; n++)</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: mcache_offsets_l[%u] = %u\n", __func__, n, p-&gt;mcache_offsets_l[n]);</div><div class='add'>+</div><div class='add'>+		for (n = 0; n &lt; *p-&gt;num_mcaches_c; n++)</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: mcache_offsets_c[%u] = %u\n", __func__, n, p-&gt;mcache_offsets_c[n]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;mcache_shift_granularity_l = l-&gt;mvmpg_access_width_l;</div><div class='add'>+	*p-&gt;mcache_shift_granularity_c = l-&gt;mvmpg_access_width_c;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_mall_bw_overhead_factor(</div><div class='add'>+	double mall_prefetch_sdp_overhead_factor[], //mall_sdp_oh_nom/pref</div><div class='add'>+	double mall_prefetch_dram_overhead_factor[], //mall_dram_oh_nom/pref</div><div class='add'>+</div><div class='add'>+	// input</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int num_active_planes)</div><div class='add'>+{</div><div class='add'>+	for (unsigned int k = 0; k &lt; num_active_planes; ++k) {</div><div class='add'>+		mall_prefetch_sdp_overhead_factor[k] = 1.0;</div><div class='add'>+		mall_prefetch_dram_overhead_factor[k] = 1.0;</div><div class='add'>+</div><div class='add'>+		// SDP - on the return side</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall) // always no data return</div><div class='add'>+			mall_prefetch_sdp_overhead_factor[k] = 1.25;</div><div class='add'>+		else if (display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return)</div><div class='add'>+			mall_prefetch_sdp_overhead_factor[k] = 0.25;</div><div class='add'>+</div><div class='add'>+		// DRAM</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall)</div><div class='add'>+			mall_prefetch_dram_overhead_factor[k] = 2.0;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, mall_prefetch_sdp_overhead_factor = %f\n", __func__, k, mall_prefetch_sdp_overhead_factor[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, mall_prefetch_dram_overhead_factor = %f\n", __func__, k, mall_prefetch_dram_overhead_factor[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double dml_get_return_bandwidth_available(</div><div class='add'>+	const struct dml2_soc_bb *soc,</div><div class='add'>+	enum dml2_core_internal_soc_state_type state_type,</div><div class='add'>+	enum dml2_core_internal_bw_type bw_type,</div><div class='add'>+	bool is_avg_bw,</div><div class='add'>+	bool is_hvm_en,</div><div class='add'>+	bool is_hvm_only,</div><div class='add'>+	double dcfclk_mhz,</div><div class='add'>+	double fclk_mhz,</div><div class='add'>+	double dram_bw_mbps)</div><div class='add'>+{</div><div class='add'>+	double return_bw_mbps = 0.;</div><div class='add'>+	double ideal_sdp_bandwidth = (double)soc-&gt;return_bus_width_bytes * dcfclk_mhz;</div><div class='add'>+	double ideal_fabric_bandwidth = fclk_mhz * (double)soc-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	double ideal_dram_bandwidth = dram_bw_mbps; //dram_speed_mts * soc-&gt;clk_table.dram_config.channel_count * soc-&gt;clk_table.dram_config.channel_width_bytes;</div><div class='add'>+</div><div class='add'>+	double derate_sdp_factor;</div><div class='add'>+	double derate_fabric_factor;</div><div class='add'>+	double derate_dram_factor;</div><div class='add'>+</div><div class='add'>+	double derate_sdp_bandwidth;</div><div class='add'>+	double derate_fabric_bandwidth;</div><div class='add'>+	double derate_dram_bandwidth;</div><div class='add'>+</div><div class='add'>+	if (is_avg_bw) {</div><div class='add'>+		if (state_type == dml2_core_internal_soc_state_svp_prefetch) {</div><div class='add'>+			derate_sdp_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_average.dcfclk_derate_percent / 100.0;</div><div class='add'>+			derate_fabric_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_average.fclk_derate_percent / 100.0;</div><div class='add'>+			derate_dram_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100.0;</div><div class='add'>+		} else { // just assume sys_active</div><div class='add'>+			derate_sdp_factor = soc-&gt;qos_parameters.derate_table.system_active_average.dcfclk_derate_percent / 100.0;</div><div class='add'>+			derate_fabric_factor = soc-&gt;qos_parameters.derate_table.system_active_average.fclk_derate_percent / 100.0;</div><div class='add'>+			derate_dram_factor = soc-&gt;qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100.0;</div><div class='add'>+		}</div><div class='add'>+	} else { // urgent bw</div><div class='add'>+		if (state_type == dml2_core_internal_soc_state_svp_prefetch) {</div><div class='add'>+			derate_sdp_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dcfclk_derate_percent / 100.0;</div><div class='add'>+			derate_fabric_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.fclk_derate_percent / 100.0;</div><div class='add'>+			derate_dram_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100.0;</div><div class='add'>+</div><div class='add'>+			if (is_hvm_en) {</div><div class='add'>+				if (is_hvm_only)</div><div class='add'>+					derate_dram_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_vm / 100.0;</div><div class='add'>+				else</div><div class='add'>+					derate_dram_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel_and_vm / 100.0;</div><div class='add'>+			} else {</div><div class='add'>+				derate_dram_factor = soc-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100.0;</div><div class='add'>+			}</div><div class='add'>+		} else { // just assume sys_active</div><div class='add'>+			derate_sdp_factor = soc-&gt;qos_parameters.derate_table.system_active_urgent.dcfclk_derate_percent / 100.0;</div><div class='add'>+			derate_fabric_factor = soc-&gt;qos_parameters.derate_table.system_active_urgent.fclk_derate_percent / 100.0;</div><div class='add'>+</div><div class='add'>+			if (is_hvm_en) {</div><div class='add'>+				if (is_hvm_only)</div><div class='add'>+					derate_dram_factor = soc-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_vm / 100.0;</div><div class='add'>+				else</div><div class='add'>+					derate_dram_factor = soc-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100.0;</div><div class='add'>+			} else {</div><div class='add'>+				derate_dram_factor = soc-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100.0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	derate_sdp_bandwidth = ideal_sdp_bandwidth * derate_sdp_factor;</div><div class='add'>+	derate_fabric_bandwidth = ideal_fabric_bandwidth * derate_fabric_factor;</div><div class='add'>+	derate_dram_bandwidth = ideal_dram_bandwidth * derate_dram_factor;</div><div class='add'>+</div><div class='add'>+	if (bw_type == dml2_core_internal_bw_sdp)</div><div class='add'>+		return_bw_mbps = math_min2(derate_sdp_bandwidth, derate_fabric_bandwidth);</div><div class='add'>+	else // dml2_core_internal_bw_dram</div><div class='add'>+		return_bw_mbps = derate_dram_bandwidth;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: is_avg_bw = %u\n", __func__, is_avg_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: is_hvm_en = %u\n", __func__, is_hvm_en);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: is_hvm_only = %u\n", __func__, is_hvm_only);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: state_type = %s\n", __func__, dml2_core_internal_soc_state_type_str(state_type));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: bw_type = %s\n", __func__, dml2_core_internal_bw_type_str(bw_type));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dcfclk_mhz = %f\n", __func__, dcfclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: fclk_mhz = %f\n", __func__, fclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ideal_sdp_bandwidth = %f\n", __func__, ideal_sdp_bandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ideal_fabric_bandwidth = %f\n", __func__, ideal_fabric_bandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ideal_dram_bandwidth = %f\n", __func__, ideal_dram_bandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: derate_sdp_bandwidth = %f (derate %f)\n", __func__, derate_sdp_bandwidth, derate_sdp_factor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: derate_fabric_bandwidth = %f (derate %f)\n", __func__, derate_fabric_bandwidth, derate_fabric_factor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: derate_dram_bandwidth = %f (derate %f)\n", __func__, derate_dram_bandwidth, derate_dram_factor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: return_bw_mbps = %f\n", __func__, return_bw_mbps);</div><div class='add'>+	return return_bw_mbps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static noinline_for_stack void calculate_bandwidth_available(</div><div class='add'>+	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max],</div><div class='add'>+	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max], // min between SDP and DRAM</div><div class='add'>+	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max],</div><div class='add'>+	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max],</div><div class='add'>+</div><div class='add'>+	const struct dml2_soc_bb *soc,</div><div class='add'>+	bool HostVMEnable,</div><div class='add'>+	double dcfclk_mhz,</div><div class='add'>+	double fclk_mhz,</div><div class='add'>+	double dram_bw_mbps)</div><div class='add'>+{</div><div class='add'>+	unsigned int n, m;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dcfclk_mhz = %f\n", __func__, dcfclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: fclk_mhz = %f\n", __func__, fclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dram_bw_mbps = %f\n", __func__, dram_bw_mbps);</div><div class='add'>+</div><div class='add'>+	// Calculate all the bandwidth availabe</div><div class='add'>+	for (m = 0; m &lt; dml2_core_internal_soc_state_max; m++) {</div><div class='add'>+		for (n = 0; n &lt; dml2_core_internal_bw_max; n++) {</div><div class='add'>+			avg_bandwidth_available[m][n] = dml_get_return_bandwidth_available(soc,</div><div class='add'>+				m, // soc_state</div><div class='add'>+				n, // bw_type</div><div class='add'>+				1, // avg_bw</div><div class='add'>+				HostVMEnable,</div><div class='add'>+				0, // hvm_only</div><div class='add'>+				dcfclk_mhz,</div><div class='add'>+				fclk_mhz,</div><div class='add'>+				dram_bw_mbps);</div><div class='add'>+</div><div class='add'>+			urg_bandwidth_available[m][n] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_bw_mbps);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: avg_bandwidth_available[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), avg_bandwidth_available[m][n]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: urg_bandwidth_available[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), urg_bandwidth_available[m][n]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+			// urg_bandwidth_available_vm_only is indexed by soc_state</div><div class='add'>+			if (n == dml2_core_internal_bw_dram) {</div><div class='add'>+				urg_bandwidth_available_vm_only[m] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 1, dcfclk_mhz, fclk_mhz, dram_bw_mbps);</div><div class='add'>+				urg_bandwidth_available_pixel_and_vm[m] = dml_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_bw_mbps);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		avg_bandwidth_available_min[m] = math_min2(avg_bandwidth_available[m][dml2_core_internal_bw_dram], avg_bandwidth_available[m][dml2_core_internal_bw_sdp]);</div><div class='add'>+		urg_bandwidth_available_min[m] = math_min2(urg_bandwidth_available[m][dml2_core_internal_bw_dram], urg_bandwidth_available[m][dml2_core_internal_bw_sdp]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: avg_bandwidth_available_min[%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), avg_bandwidth_available_min[m]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: urg_bandwidth_available_min[%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), urg_bandwidth_available_min[m]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: urg_bandwidth_available_vm_only[%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), urg_bandwidth_available_vm_only[n]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_avg_bandwidth_required(</div><div class='add'>+	double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+</div><div class='add'>+	// input</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int num_active_planes,</div><div class='add'>+	double ReadBandwidthLuma[],</div><div class='add'>+	double ReadBandwidthChroma[],</div><div class='add'>+	double cursor_bw[],</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p0[],</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p1[],</div><div class='add'>+	double mall_prefetch_dram_overhead_factor[],</div><div class='add'>+	double mall_prefetch_sdp_overhead_factor[])</div><div class='add'>+{</div><div class='add'>+	unsigned int n, m, k;</div><div class='add'>+	double sdp_overhead_factor;</div><div class='add'>+	double dram_overhead_factor_p0;</div><div class='add'>+	double dram_overhead_factor_p1;</div><div class='add'>+</div><div class='add'>+	// Average BW support check</div><div class='add'>+	for (m = 0; m &lt; dml2_core_internal_soc_state_max; m++) {</div><div class='add'>+		for (n = 0; n &lt; dml2_core_internal_bw_max; n++) { // sdp, dram</div><div class='add'>+			avg_bandwidth_required[m][n] = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// SysActive and SVP Prefetch AVG bandwidth Check</div><div class='add'>+	for (k = 0; k &lt; num_active_planes; ++k) {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: plane %0d\n", __func__, k);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: ReadBandwidthLuma=%f\n", __func__, ReadBandwidthLuma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: ReadBandwidthChroma=%f\n", __func__, ReadBandwidthChroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor_p0=%f\n", __func__, dcc_dram_bw_nom_overhead_factor_p0[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor_p1=%f\n", __func__, dcc_dram_bw_nom_overhead_factor_p1[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mall_prefetch_dram_overhead_factor=%f\n", __func__, mall_prefetch_dram_overhead_factor[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mall_prefetch_sdp_overhead_factor=%f\n", __func__, mall_prefetch_sdp_overhead_factor[k]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		sdp_overhead_factor = mall_prefetch_sdp_overhead_factor[k];</div><div class='add'>+		dram_overhead_factor_p0 = dcc_dram_bw_nom_overhead_factor_p0[k] * mall_prefetch_dram_overhead_factor[k];</div><div class='add'>+		dram_overhead_factor_p1 = dcc_dram_bw_nom_overhead_factor_p1[k] * mall_prefetch_dram_overhead_factor[k];</div><div class='add'>+</div><div class='add'>+		// FIXME_DCN4, was missing cursor_bw in here, but do I actually need that and tdlut bw for average bandwidth calculation?</div><div class='add'>+		// active avg bw not include phantom, but svp_prefetch avg bw should include phantom pipes</div><div class='add'>+		if (!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+			avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] += sdp_overhead_factor * (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) + cursor_bw[k];</div><div class='add'>+			avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] += dram_overhead_factor_p0 * ReadBandwidthLuma[k] + dram_overhead_factor_p1 * ReadBandwidthChroma[k] + cursor_bw[k];</div><div class='add'>+		}</div><div class='add'>+		avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] += sdp_overhead_factor * (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) + cursor_bw[k];</div><div class='add'>+		avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] += dram_overhead_factor_p0 * ReadBandwidthLuma[k] + dram_overhead_factor_p1 * ReadBandwidthChroma[k] + cursor_bw[k];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: avg_bandwidth_required[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(dml2_core_internal_soc_state_sys_active), dml2_core_internal_bw_type_str(dml2_core_internal_bw_sdp), avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: avg_bandwidth_required[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(dml2_core_internal_soc_state_sys_active), dml2_core_internal_bw_type_str(dml2_core_internal_bw_dram), avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: avg_bandwidth_required[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(dml2_core_internal_soc_state_svp_prefetch), dml2_core_internal_bw_type_str(dml2_core_internal_bw_sdp), avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: avg_bandwidth_required[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(dml2_core_internal_soc_state_svp_prefetch), dml2_core_internal_bw_type_str(dml2_core_internal_bw_dram), avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateVMRowAndSwath(struct dml2_core_internal_scratch *scratch,</div><div class='add'>+	struct dml2_core_calcs_CalculateVMRowAndSwath_params *p)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_calcs_CalculateVMRowAndSwath_locals *s = &amp;scratch-&gt;CalculateVMRowAndSwath_locals;</div><div class='add'>+</div><div class='add'>+	s-&gt;HostVMDynamicLevels = CalculateHostVMDynamicLevels(p-&gt;display_cfg-&gt;gpuvm_enable, p-&gt;display_cfg-&gt;hostvm_enable, p-&gt;HostVMMinPageSize, p-&gt;display_cfg-&gt;hostvm_max_non_cached_page_table_levels);</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (p-&gt;display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+			p-&gt;vm_group_bytes[k] = 512;</div><div class='add'>+			p-&gt;dpte_group_bytes[k] = 512;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;vm_group_bytes[k] = 0;</div><div class='add'>+			p-&gt;dpte_group_bytes[k] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dml_is_420(p-&gt;myPipe[k].SourcePixelFormat) || p-&gt;myPipe[k].SourcePixelFormat == dml2_rgbe_alpha) {</div><div class='add'>+			if ((p-&gt;myPipe[k].SourcePixelFormat == dml2_420_10 || p-&gt;myPipe[k].SourcePixelFormat == dml2_420_12) &amp;&amp; !dml_is_vertical_rotation(p-&gt;myPipe[k].RotationAngle)) {</div><div class='add'>+				s-&gt;PTEBufferSizeInRequestsForLuma[k] = (p-&gt;PTEBufferSizeInRequestsLuma + p-&gt;PTEBufferSizeInRequestsChroma) / 2;</div><div class='add'>+				s-&gt;PTEBufferSizeInRequestsForChroma[k] = s-&gt;PTEBufferSizeInRequestsForLuma[k];</div><div class='add'>+			} else {</div><div class='add'>+				s-&gt;PTEBufferSizeInRequestsForLuma[k] = p-&gt;PTEBufferSizeInRequestsLuma;</div><div class='add'>+				s-&gt;PTEBufferSizeInRequestsForChroma[k] = p-&gt;PTEBufferSizeInRequestsChroma;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.ViewportStationary = p-&gt;myPipe[k].ViewportStationary;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.DCCEnable = p-&gt;myPipe[k].DCCEnable;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.NumberOfDPPs = p-&gt;myPipe[k].DPPPerSurface;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p-&gt;myPipe[k].BlockHeight256BytesC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p-&gt;myPipe[k].BlockWidth256BytesC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.SourcePixelFormat = p-&gt;myPipe[k].SourcePixelFormat;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.SurfaceTiling = p-&gt;myPipe[k].SurfaceTiling;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.BytePerPixel = p-&gt;myPipe[k].BytePerPixelC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.RotationAngle = p-&gt;myPipe[k].RotationAngle;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.SwathWidth = p-&gt;SwathWidthC[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.ViewportHeight = p-&gt;myPipe[k].ViewportHeightC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.ViewportXStart = p-&gt;myPipe[k].ViewportXStartC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.ViewportYStart = p-&gt;myPipe[k].ViewportYStartC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.GPUVMEnable = p-&gt;display_cfg-&gt;gpuvm_enable;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s-&gt;PTEBufferSizeInRequestsForChroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.Pitch = p-&gt;myPipe[k].PitchC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.MacroTileWidth = p-&gt;myPipe[k].BlockWidthC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.MacroTileHeight = p-&gt;myPipe[k].BlockHeightC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k]);</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.DCCMetaPitch = p-&gt;myPipe[k].DCCMetaPitchC;</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.mrq_present = p-&gt;mrq_present;</div><div class='add'>+</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &amp;s-&gt;PixelPTEBytesPerRowC[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &amp;s-&gt;PixelPTEBytesPerRowStorageC[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_width_ub = &amp;p-&gt;dpte_row_width_chroma_ub[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_height = &amp;p-&gt;dpte_row_height_chroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_height_linear = &amp;p-&gt;dpte_row_height_linear_chroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &amp;s-&gt;PixelPTEBytesPerRowC_one_row_per_frame[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &amp;s-&gt;dpte_row_width_chroma_ub_one_row_per_frame[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &amp;s-&gt;dpte_row_height_chroma_one_row_per_frame[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.vmpg_width = &amp;p-&gt;vmpg_width_c[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.vmpg_height = &amp;p-&gt;vmpg_height_c[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &amp;p-&gt;PixelPTEReqWidthC[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &amp;p-&gt;PixelPTEReqHeightC[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.PTERequestSize = &amp;p-&gt;PTERequestSizeC[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &amp;p-&gt;dpde0_bytes_per_frame_ub_c[k];</div><div class='add'>+</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.meta_row_bytes = &amp;s-&gt;meta_row_bytes_per_row_ub_c[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.MetaRequestWidth = &amp;p-&gt;meta_req_width_chroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.MetaRequestHeight = &amp;p-&gt;meta_req_height_chroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.meta_row_width = &amp;p-&gt;meta_row_width_chroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.meta_row_height = &amp;p-&gt;meta_row_height_chroma[k];</div><div class='add'>+			scratch-&gt;calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &amp;p-&gt;meta_pte_bytes_per_frame_ub_c[k];</div><div class='add'>+</div><div class='add'>+			s-&gt;vm_bytes_c = CalculateVMAndRowBytes(&amp;scratch-&gt;calculate_vm_and_row_bytes_params);</div><div class='add'>+</div><div class='add'>+			p-&gt;PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(</div><div class='add'>+				p-&gt;myPipe[k].VRatioChroma,</div><div class='add'>+				p-&gt;myPipe[k].VTapsChroma,</div><div class='add'>+				p-&gt;myPipe[k].InterlaceEnable,</div><div class='add'>+				p-&gt;myPipe[k].ProgressiveToInterlaceUnitInOPP,</div><div class='add'>+				p-&gt;myPipe[k].SwathHeightC,</div><div class='add'>+				p-&gt;myPipe[k].RotationAngle,</div><div class='add'>+				p-&gt;myPipe[k].mirrored,</div><div class='add'>+				p-&gt;myPipe[k].ViewportStationary,</div><div class='add'>+				p-&gt;SwathWidthC[k],</div><div class='add'>+				p-&gt;myPipe[k].ViewportHeightC,</div><div class='add'>+				p-&gt;myPipe[k].ViewportXStartC,</div><div class='add'>+				p-&gt;myPipe[k].ViewportYStartC,</div><div class='add'>+</div><div class='add'>+				// Output</div><div class='add'>+				&amp;p-&gt;VInitPreFillC[k],</div><div class='add'>+				&amp;p-&gt;MaxNumSwathC[k]);</div><div class='add'>+		} else {</div><div class='add'>+			s-&gt;PTEBufferSizeInRequestsForLuma[k] = p-&gt;PTEBufferSizeInRequestsLuma + p-&gt;PTEBufferSizeInRequestsChroma;</div><div class='add'>+			s-&gt;PTEBufferSizeInRequestsForChroma[k] = 0;</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowC[k] = 0;</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowStorageC[k] = 0;</div><div class='add'>+			s-&gt;vm_bytes_c = 0;</div><div class='add'>+			p-&gt;MaxNumSwathC[k] = 0;</div><div class='add'>+			p-&gt;PrefetchSourceLinesC[k] = 0;</div><div class='add'>+			s-&gt;dpte_row_height_chroma_one_row_per_frame[k] = 0;</div><div class='add'>+			s-&gt;dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.ViewportStationary = p-&gt;myPipe[k].ViewportStationary;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.DCCEnable = p-&gt;myPipe[k].DCCEnable;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.NumberOfDPPs = p-&gt;myPipe[k].DPPPerSurface;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p-&gt;myPipe[k].BlockHeight256BytesY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p-&gt;myPipe[k].BlockWidth256BytesY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.SourcePixelFormat = p-&gt;myPipe[k].SourcePixelFormat;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.SurfaceTiling = p-&gt;myPipe[k].SurfaceTiling;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.BytePerPixel = p-&gt;myPipe[k].BytePerPixelY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.RotationAngle = p-&gt;myPipe[k].RotationAngle;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.SwathWidth = p-&gt;SwathWidthY[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.ViewportHeight = p-&gt;myPipe[k].ViewportHeight;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.ViewportXStart = p-&gt;myPipe[k].ViewportXStart;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.ViewportYStart = p-&gt;myPipe[k].ViewportYStart;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.GPUVMEnable = p-&gt;display_cfg-&gt;gpuvm_enable;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s-&gt;PTEBufferSizeInRequestsForLuma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.Pitch = p-&gt;myPipe[k].PitchY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.MacroTileWidth = p-&gt;myPipe[k].BlockWidthY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.MacroTileHeight = p-&gt;myPipe[k].BlockHeightY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k]);</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.DCCMetaPitch = p-&gt;myPipe[k].DCCMetaPitchY;</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.mrq_present = p-&gt;mrq_present;</div><div class='add'>+</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &amp;s-&gt;PixelPTEBytesPerRowY[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &amp;s-&gt;PixelPTEBytesPerRowStorageY[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_width_ub = &amp;p-&gt;dpte_row_width_luma_ub[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_height = &amp;p-&gt;dpte_row_height_luma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_height_linear = &amp;p-&gt;dpte_row_height_linear_luma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &amp;s-&gt;PixelPTEBytesPerRowY_one_row_per_frame[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &amp;s-&gt;dpte_row_width_luma_ub_one_row_per_frame[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &amp;s-&gt;dpte_row_height_luma_one_row_per_frame[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.vmpg_width = &amp;p-&gt;vmpg_width_y[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.vmpg_height = &amp;p-&gt;vmpg_height_y[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &amp;p-&gt;PixelPTEReqWidthY[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &amp;p-&gt;PixelPTEReqHeightY[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.PTERequestSize = &amp;p-&gt;PTERequestSizeY[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &amp;p-&gt;dpde0_bytes_per_frame_ub_l[k];</div><div class='add'>+</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.meta_row_bytes = &amp;s-&gt;meta_row_bytes_per_row_ub_l[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.MetaRequestWidth = &amp;p-&gt;meta_req_width_luma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.MetaRequestHeight = &amp;p-&gt;meta_req_height_luma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.meta_row_width = &amp;p-&gt;meta_row_width_luma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.meta_row_height = &amp;p-&gt;meta_row_height_luma[k];</div><div class='add'>+		scratch-&gt;calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &amp;p-&gt;meta_pte_bytes_per_frame_ub_l[k];</div><div class='add'>+</div><div class='add'>+		s-&gt;vm_bytes_l = CalculateVMAndRowBytes(&amp;scratch-&gt;calculate_vm_and_row_bytes_params);</div><div class='add'>+</div><div class='add'>+		p-&gt;PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(</div><div class='add'>+			p-&gt;myPipe[k].VRatio,</div><div class='add'>+			p-&gt;myPipe[k].VTaps,</div><div class='add'>+			p-&gt;myPipe[k].InterlaceEnable,</div><div class='add'>+			p-&gt;myPipe[k].ProgressiveToInterlaceUnitInOPP,</div><div class='add'>+			p-&gt;myPipe[k].SwathHeightY,</div><div class='add'>+			p-&gt;myPipe[k].RotationAngle,</div><div class='add'>+			p-&gt;myPipe[k].mirrored,</div><div class='add'>+			p-&gt;myPipe[k].ViewportStationary,</div><div class='add'>+			p-&gt;SwathWidthY[k],</div><div class='add'>+			p-&gt;myPipe[k].ViewportHeight,</div><div class='add'>+			p-&gt;myPipe[k].ViewportXStart,</div><div class='add'>+			p-&gt;myPipe[k].ViewportYStart,</div><div class='add'>+</div><div class='add'>+			// Output</div><div class='add'>+			&amp;p-&gt;VInitPreFillY[k],</div><div class='add'>+			&amp;p-&gt;MaxNumSwathY[k]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes_l = %u (before hvm level)\n", __func__, k, s-&gt;vm_bytes_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes_c = %u (before hvm level)\n", __func__, k, s-&gt;vm_bytes_c);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes_per_row_ub_l = %u\n", __func__, k, s-&gt;meta_row_bytes_per_row_ub_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes_per_row_ub_c = %u\n", __func__, k, s-&gt;meta_row_bytes_per_row_ub_c[k]);</div><div class='add'>+#endif</div><div class='add'>+		p-&gt;vm_bytes[k] = (s-&gt;vm_bytes_l + s-&gt;vm_bytes_c) * (1 + 8 * s-&gt;HostVMDynamicLevels);</div><div class='add'>+		p-&gt;meta_row_bytes[k] = s-&gt;meta_row_bytes_per_row_ub_l[k] + s-&gt;meta_row_bytes_per_row_ub_c[k];</div><div class='add'>+		p-&gt;meta_row_bytes_per_row_ub_l[k] = s-&gt;meta_row_bytes_per_row_ub_l[k];</div><div class='add'>+		p-&gt;meta_row_bytes_per_row_ub_c[k] = s-&gt;meta_row_bytes_per_row_ub_c[k];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes = %u\n", __func__, k, p-&gt;meta_row_bytes[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes = %u (after hvm level)\n", __func__, k, p-&gt;vm_bytes[k]);</div><div class='add'>+#endif</div><div class='add'>+		if (s-&gt;PixelPTEBytesPerRowStorageY[k] &lt;= 64 * s-&gt;PTEBufferSizeInRequestsForLuma[k] &amp;&amp; s-&gt;PixelPTEBytesPerRowStorageC[k] &lt;= 64 * s-&gt;PTEBufferSizeInRequestsForChroma[k]) {</div><div class='add'>+			p-&gt;PTEBufferSizeNotExceeded[k] = true;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;PTEBufferSizeNotExceeded[k] = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		s-&gt;one_row_per_frame_fits_in_buffer[k] = (s-&gt;PixelPTEBytesPerRowY_one_row_per_frame[k] &lt;= 64 * 2 * s-&gt;PTEBufferSizeInRequestsForLuma[k] &amp;&amp;</div><div class='add'>+												s-&gt;PixelPTEBytesPerRowC_one_row_per_frame[k] &lt;= 64 * 2 * s-&gt;PTEBufferSizeInRequestsForChroma[k]);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		if (p-&gt;PTEBufferSizeNotExceeded[k] == 0 || s-&gt;one_row_per_frame_fits_in_buffer[k] == 0) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY = %u (before hvm level)\n", __func__, k, s-&gt;PixelPTEBytesPerRowY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC = %u (before hvm level)\n", __func__, k, s-&gt;PixelPTEBytesPerRowC[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowStorageY = %u\n", __func__, k, s-&gt;PixelPTEBytesPerRowStorageY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowStorageC = %u\n", __func__, k, s-&gt;PixelPTEBytesPerRowStorageC[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeInRequestsForLuma = %u\n", __func__, k, s-&gt;PTEBufferSizeInRequestsForLuma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeInRequestsForChroma = %u\n", __func__, k, s-&gt;PTEBufferSizeInRequestsForChroma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded (not one_row_per_frame) = %u\n", __func__, k, p-&gt;PTEBufferSizeNotExceeded[k]);</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, HostVMDynamicLevels = %u\n", __func__, k, s-&gt;HostVMDynamicLevels);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY_one_row_per_frame = %u\n", __func__, k, s-&gt;PixelPTEBytesPerRowY_one_row_per_frame[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC_one_row_per_frame = %u\n", __func__, k, s-&gt;PixelPTEBytesPerRowC_one_row_per_frame[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, one_row_per_frame_fits_in_buffer = %u\n", __func__, k, s-&gt;one_row_per_frame_fits_in_buffer[k]);</div><div class='add'>+		}</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateMALLUseForStaticScreen(</div><div class='add'>+		p-&gt;display_cfg,</div><div class='add'>+		p-&gt;NumberOfActiveSurfaces,</div><div class='add'>+		p-&gt;MALLAllocatedForDCN,</div><div class='add'>+		p-&gt;SurfaceSizeInMALL,</div><div class='add'>+		s-&gt;one_row_per_frame_fits_in_buffer,</div><div class='add'>+		// Output</div><div class='add'>+		p-&gt;is_using_mall_for_ss);</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (p-&gt;display_cfg-&gt;gpuvm_enable) {</div><div class='add'>+			if (p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.hw.force_pte_buffer_mode.enable == 1) {</div><div class='add'>+				p-&gt;PTE_BUFFER_MODE[k] = p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.hw.force_pte_buffer_mode.value;</div><div class='add'>+			}</div><div class='add'>+			p-&gt;PTE_BUFFER_MODE[k] = p-&gt;myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p-&gt;is_using_mall_for_ss[k] || (p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) ||</div><div class='add'>+				dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k]) || (p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes &gt; 64);</div><div class='add'>+			p-&gt;BIGK_FRAGMENT_SIZE[k] = (unsigned int)(math_log((float)p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes * 1024, 2) - 12);</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;PTE_BUFFER_MODE[k] = 0;</div><div class='add'>+			p-&gt;BIGK_FRAGMENT_SIZE[k] = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		p-&gt;DCCMetaBufferSizeNotExceeded[k] = true;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, SurfaceSizeInMALL = %u\n", __func__, k, p-&gt;SurfaceSizeInMALL[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, is_using_mall_for_ss = %u\n", __func__, k, p-&gt;is_using_mall_for_ss[k]);</div><div class='add'>+#endif</div><div class='add'>+		p-&gt;use_one_row_for_frame[k] = p-&gt;myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p-&gt;is_using_mall_for_ss[k] || (p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) ||</div><div class='add'>+			(dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k])) || (p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes &gt; 64 &amp;&amp; dml_is_vertical_rotation(p-&gt;myPipe[k].RotationAngle));</div><div class='add'>+</div><div class='add'>+		p-&gt;use_one_row_for_frame_flip[k] = p-&gt;use_one_row_for_frame[k] &amp;&amp; !(p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame);</div><div class='add'>+</div><div class='add'>+		if (p-&gt;use_one_row_for_frame[k]) {</div><div class='add'>+			p-&gt;dpte_row_height_luma[k] = s-&gt;dpte_row_height_luma_one_row_per_frame[k];</div><div class='add'>+			p-&gt;dpte_row_width_luma_ub[k] = s-&gt;dpte_row_width_luma_ub_one_row_per_frame[k];</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowY[k] = s-&gt;PixelPTEBytesPerRowY_one_row_per_frame[k];</div><div class='add'>+			p-&gt;dpte_row_height_chroma[k] = s-&gt;dpte_row_height_chroma_one_row_per_frame[k];</div><div class='add'>+			p-&gt;dpte_row_width_chroma_ub[k] = s-&gt;dpte_row_width_chroma_ub_one_row_per_frame[k];</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowC[k] = s-&gt;PixelPTEBytesPerRowC_one_row_per_frame[k];</div><div class='add'>+			p-&gt;PTEBufferSizeNotExceeded[k] = s-&gt;one_row_per_frame_fits_in_buffer[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;meta_row_bytes[k] &lt;= p-&gt;DCCMetaBufferSizeBytes) {</div><div class='add'>+			p-&gt;DCCMetaBufferSizeNotExceeded[k] = true;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;DCCMetaBufferSizeNotExceeded[k] = false;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, meta_row_bytes = %d\n",  __func__, k, p-&gt;meta_row_bytes[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, DCCMetaBufferSizeBytes = %d\n",  __func__, k, p-&gt;DCCMetaBufferSizeBytes);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, DCCMetaBufferSizeNotExceeded = %d\n",  __func__, k, p-&gt;DCCMetaBufferSizeNotExceeded[k]);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		s-&gt;PixelPTEBytesPerRowY[k] = s-&gt;PixelPTEBytesPerRowY[k] * (1 + 8 * s-&gt;HostVMDynamicLevels);</div><div class='add'>+		s-&gt;PixelPTEBytesPerRowC[k] = s-&gt;PixelPTEBytesPerRowC[k] * (1 + 8 * s-&gt;HostVMDynamicLevels);</div><div class='add'>+		p-&gt;PixelPTEBytesPerRow[k] = s-&gt;PixelPTEBytesPerRowY[k] + s-&gt;PixelPTEBytesPerRowC[k];</div><div class='add'>+		p-&gt;dpte_row_bytes_per_row_l[k] = s-&gt;PixelPTEBytesPerRowY[k];</div><div class='add'>+		p-&gt;dpte_row_bytes_per_row_c[k] = s-&gt;PixelPTEBytesPerRowC[k];</div><div class='add'>+</div><div class='add'>+		// if one row of dPTEs is meant to span the entire frame, then for these calculations, we will pretend like that one big row is fetched in two halfs</div><div class='add'>+		if (p-&gt;use_one_row_for_frame[k])</div><div class='add'>+			p-&gt;PixelPTEBytesPerRow[k] = p-&gt;PixelPTEBytesPerRow[k] / 2;</div><div class='add'>+</div><div class='add'>+		CalculateRowBandwidth(</div><div class='add'>+			p-&gt;display_cfg-&gt;gpuvm_enable,</div><div class='add'>+			p-&gt;use_one_row_for_frame[k],</div><div class='add'>+			p-&gt;myPipe[k].SourcePixelFormat,</div><div class='add'>+			p-&gt;myPipe[k].VRatio,</div><div class='add'>+			p-&gt;myPipe[k].VRatioChroma,</div><div class='add'>+			p-&gt;myPipe[k].DCCEnable,</div><div class='add'>+			p-&gt;myPipe[k].HTotal / p-&gt;myPipe[k].PixelClock,</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowY[k],</div><div class='add'>+			s-&gt;PixelPTEBytesPerRowC[k],</div><div class='add'>+			p-&gt;dpte_row_height_luma[k],</div><div class='add'>+			p-&gt;dpte_row_height_chroma[k],</div><div class='add'>+</div><div class='add'>+			p-&gt;mrq_present,</div><div class='add'>+			p-&gt;meta_row_bytes_per_row_ub_l[k],</div><div class='add'>+			p-&gt;meta_row_bytes_per_row_ub_c[k],</div><div class='add'>+			p-&gt;meta_row_height_luma[k],</div><div class='add'>+			p-&gt;meta_row_height_chroma[k],</div><div class='add'>+</div><div class='add'>+			// Output</div><div class='add'>+			&amp;p-&gt;dpte_row_bw[k],</div><div class='add'>+			&amp;p-&gt;meta_row_bw[k]);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p-&gt;use_one_row_for_frame[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame_flip = %u\n", __func__, k, p-&gt;use_one_row_for_frame_flip[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, UseMALLForPStateChange = %u\n", __func__, k, p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_height_luma = %u\n", __func__, k, p-&gt;dpte_row_height_luma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p-&gt;dpte_row_width_luma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY = %u (after hvm level)\n", __func__, k, s-&gt;PixelPTEBytesPerRowY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_height_chroma = %u\n", __func__, k, p-&gt;dpte_row_height_chroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p-&gt;dpte_row_width_chroma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC = %u (after hvm level)\n", __func__, k, s-&gt;PixelPTEBytesPerRowC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRow = %u\n", __func__, k, p-&gt;PixelPTEBytesPerRow[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p-&gt;PTEBufferSizeNotExceeded[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, gpuvm_enable = %u\n", __func__, k, p-&gt;display_cfg-&gt;gpuvm_enable);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PTE_BUFFER_MODE = %u\n", __func__, k, p-&gt;PTE_BUFFER_MODE[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, BIGK_FRAGMENT_SIZE = %u\n", __func__, k, p-&gt;BIGK_FRAGMENT_SIZE[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateUrgentLatency(</div><div class='add'>+	double UrgentLatencyPixelDataOnly,</div><div class='add'>+	double UrgentLatencyPixelMixedWithVMData,</div><div class='add'>+	double UrgentLatencyVMDataOnly,</div><div class='add'>+	bool DoUrgentLatencyAdjustment,</div><div class='add'>+	double UrgentLatencyAdjustmentFabricClockComponent,</div><div class='add'>+	double UrgentLatencyAdjustmentFabricClockReference,</div><div class='add'>+	double FabricClock,</div><div class='add'>+	double uclk_freq_mhz,</div><div class='add'>+	enum dml2_qos_param_type qos_type,</div><div class='add'>+	unsigned int urgent_ramp_uclk_cycles,</div><div class='add'>+	unsigned int df_qos_response_time_fclk_cycles,</div><div class='add'>+	unsigned int max_round_trip_to_furthest_cs_fclk_cycles,</div><div class='add'>+	unsigned int mall_overhead_fclk_cycles,</div><div class='add'>+	double umc_urgent_ramp_latency_margin,</div><div class='add'>+	double fabric_max_transport_latency_margin)</div><div class='add'>+{</div><div class='add'>+	double urgent_latency = 0;</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		urgent_latency = (df_qos_response_time_fclk_cycles + mall_overhead_fclk_cycles) / FabricClock</div><div class='add'>+			+ max_round_trip_to_furthest_cs_fclk_cycles / FabricClock * (1 + fabric_max_transport_latency_margin / 100.0)</div><div class='add'>+			+ urgent_ramp_uclk_cycles / uclk_freq_mhz * (1 + umc_urgent_ramp_latency_margin / 100.0);</div><div class='add'>+	} else {</div><div class='add'>+		urgent_latency = math_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);</div><div class='add'>+		if (DoUrgentLatencyAdjustment == true) {</div><div class='add'>+			urgent_latency = urgent_latency + UrgentLatencyAdjustmentFabricClockComponent * (UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: qos_type = %d\n", __func__, qos_type);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: urgent_ramp_uclk_cycles = %d\n", __func__, urgent_ramp_uclk_cycles);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: uclk_freq_mhz = %f\n", __func__, uclk_freq_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: umc_urgent_ramp_latency_margin = %f\n", __func__, umc_urgent_ramp_latency_margin);</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgentLatencyPixelDataOnly = %f\n", __func__, UrgentLatencyPixelDataOnly);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgentLatencyPixelMixedWithVMData = %f\n", __func__, UrgentLatencyPixelMixedWithVMData);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgentLatencyVMDataOnly = %f\n", __func__, UrgentLatencyVMDataOnly);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgentLatencyAdjustmentFabricClockComponent = %f\n", __func__, UrgentLatencyAdjustmentFabricClockComponent);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgentLatencyAdjustmentFabricClockReference = %f\n", __func__, UrgentLatencyAdjustmentFabricClockReference);</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FabricClock = %f\n", __func__, FabricClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentLatency = %f\n", __func__, urgent_latency);</div><div class='add'>+#endif</div><div class='add'>+	return urgent_latency;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateTripToMemory(</div><div class='add'>+	double UrgLatency,</div><div class='add'>+	double FabricClock,</div><div class='add'>+	double uclk_freq_mhz,</div><div class='add'>+	enum dml2_qos_param_type qos_type,</div><div class='add'>+	unsigned int trip_to_memory_uclk_cycles,</div><div class='add'>+	unsigned int max_round_trip_to_furthest_cs_fclk_cycles,</div><div class='add'>+	unsigned int mall_overhead_fclk_cycles,</div><div class='add'>+	double umc_max_latency_margin,</div><div class='add'>+	double fabric_max_transport_latency_margin)</div><div class='add'>+{</div><div class='add'>+	double trip_to_memory_us;</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		trip_to_memory_us = mall_overhead_fclk_cycles / FabricClock</div><div class='add'>+			+ max_round_trip_to_furthest_cs_fclk_cycles / FabricClock * (1.0 + fabric_max_transport_latency_margin / 100.0)</div><div class='add'>+			+ trip_to_memory_uclk_cycles / uclk_freq_mhz * (1.0 + umc_max_latency_margin / 100.0);</div><div class='add'>+	} else {</div><div class='add'>+		trip_to_memory_us = UrgLatency;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: qos_type = %d\n", __func__, qos_type);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: max_round_trip_to_furthest_cs_fclk_cycles = %d\n", __func__, max_round_trip_to_furthest_cs_fclk_cycles);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: mall_overhead_fclk_cycles = %d\n", __func__, mall_overhead_fclk_cycles);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: trip_to_memory_uclk_cycles = %d\n", __func__, trip_to_memory_uclk_cycles);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: uclk_freq_mhz = %f\n", __func__, uclk_freq_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: FabricClock = %f\n", __func__, FabricClock);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: fabric_max_transport_latency_margin = %f\n", __func__, fabric_max_transport_latency_margin);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: umc_max_latency_margin = %f\n", __func__, umc_max_latency_margin);</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgLatency = %f\n", __func__, UrgLatency);</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: trip_to_memory_us = %f\n", __func__, trip_to_memory_us);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	return trip_to_memory_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateMetaTripToMemory(</div><div class='add'>+	double UrgLatency,</div><div class='add'>+	double FabricClock,</div><div class='add'>+	double uclk_freq_mhz,</div><div class='add'>+	enum dml2_qos_param_type qos_type,</div><div class='add'>+	unsigned int meta_trip_to_memory_uclk_cycles,</div><div class='add'>+	unsigned int meta_trip_to_memory_fclk_cycles,</div><div class='add'>+	double umc_max_latency_margin,</div><div class='add'>+	double fabric_max_transport_latency_margin)</div><div class='add'>+{</div><div class='add'>+	double meta_trip_to_memory_us;</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		meta_trip_to_memory_us = meta_trip_to_memory_fclk_cycles / FabricClock * (1.0 + fabric_max_transport_latency_margin / 100.0)</div><div class='add'>+			+ meta_trip_to_memory_uclk_cycles / uclk_freq_mhz * (1.0 + umc_max_latency_margin / 100.0);</div><div class='add'>+	} else {</div><div class='add'>+		meta_trip_to_memory_us = UrgLatency;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: qos_type = %d\n", __func__, qos_type);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: meta_trip_to_memory_fclk_cycles = %d\n", __func__, meta_trip_to_memory_fclk_cycles);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: meta_trip_to_memory_uclk_cycles = %d\n", __func__, meta_trip_to_memory_uclk_cycles);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: uclk_freq_mhz = %f\n", __func__, uclk_freq_mhz);</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgLatency = %f\n", __func__, UrgLatency);</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_trip_to_memory_us = %f\n", __func__, meta_trip_to_memory_us);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	return meta_trip_to_memory_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_cursor_req_attributes(</div><div class='add'>+	unsigned int cursor_width,</div><div class='add'>+	unsigned int cursor_bpp,</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	unsigned int *cursor_lines_per_chunk,</div><div class='add'>+	unsigned int *cursor_bytes_per_line,</div><div class='add'>+	unsigned int *cursor_bytes_per_chunk,</div><div class='add'>+	unsigned int *cursor_bytes)</div><div class='add'>+{</div><div class='add'>+	unsigned int cursor_bytes_per_req = 0;</div><div class='add'>+	unsigned int cursor_width_bytes = 0;</div><div class='add'>+	unsigned int cursor_height = 0;</div><div class='add'>+</div><div class='add'>+	//SW determines the cursor pitch to support the maximum cursor_width that will be used but the following restrictions apply.</div><div class='add'>+	//- For 2bpp, cursor_pitch = 256 pixels due to min cursor request size of 64B</div><div class='add'>+	//- For 32 or 64 bpp, cursor_pitch = 64, 128 or 256 pixels depending on the cursor width</div><div class='add'>+</div><div class='add'>+	//The cursor requestor uses a cursor request size of 64B, 128B, or 256B depending on the cursor_width and cursor_bpp as follows.</div><div class='add'>+</div><div class='add'>+	cursor_width_bytes = (unsigned int)math_ceil2((double)cursor_width * cursor_bpp / 8, 1);</div><div class='add'>+	if (cursor_width_bytes &lt;= 64)</div><div class='add'>+		cursor_bytes_per_req = 64;</div><div class='add'>+	else if (cursor_width_bytes &lt;= 128)</div><div class='add'>+		cursor_bytes_per_req = 128;</div><div class='add'>+	else</div><div class='add'>+		cursor_bytes_per_req = 256;</div><div class='add'>+</div><div class='add'>+	//If cursor_width_bytes is greater than 256B, then multiple 256B requests are issued to fetch the entire cursor line.</div><div class='add'>+	*cursor_bytes_per_line = (unsigned int)math_ceil2((double)cursor_width_bytes, cursor_bytes_per_req);</div><div class='add'>+</div><div class='add'>+	//Nominally, the cursor chunk is 1KB or 2KB but it is restricted to a power of 2 number of lines with a maximum of 16 lines.</div><div class='add'>+	if (cursor_bpp == 2) {</div><div class='add'>+		*cursor_lines_per_chunk = 16;</div><div class='add'>+	} else if (cursor_bpp == 32) {</div><div class='add'>+		if (cursor_width &lt;= 32)</div><div class='add'>+			*cursor_lines_per_chunk = 16;</div><div class='add'>+		else if (cursor_width &lt;= 64)</div><div class='add'>+			*cursor_lines_per_chunk = 8;</div><div class='add'>+		else if (cursor_width &lt;= 128)</div><div class='add'>+			*cursor_lines_per_chunk = 4;</div><div class='add'>+		else</div><div class='add'>+			*cursor_lines_per_chunk = 2;</div><div class='add'>+	} else if (cursor_bpp == 64) {</div><div class='add'>+		if (cursor_width &lt;= 16)</div><div class='add'>+			*cursor_lines_per_chunk = 16;</div><div class='add'>+		else if (cursor_width &lt;= 32)</div><div class='add'>+			*cursor_lines_per_chunk = 8;</div><div class='add'>+		else if (cursor_width &lt;= 64)</div><div class='add'>+			*cursor_lines_per_chunk = 4;</div><div class='add'>+		else if (cursor_width &lt;= 128)</div><div class='add'>+			*cursor_lines_per_chunk = 2;</div><div class='add'>+		else</div><div class='add'>+			*cursor_lines_per_chunk = 1;</div><div class='add'>+	} else {</div><div class='add'>+		if (cursor_width &gt; 0) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Invalid cursor_bpp = %d\n", __func__, cursor_bpp);</div><div class='add'>+			DML_ASSERT(0);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*cursor_bytes_per_chunk = *cursor_bytes_per_line * *cursor_lines_per_chunk;</div><div class='add'>+</div><div class='add'>+	// For the cursor implementation, all requested data is stored in the return buffer. Given this fact, the cursor_bytes can be directly compared with the CursorBufferSize.</div><div class='add'>+	// Only cursor_width is provided for worst case sizing so assume that the cursor is square</div><div class='add'>+	cursor_height = cursor_width;</div><div class='add'>+	*cursor_bytes = *cursor_bytes_per_line * cursor_height;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_bpp = %d\n", __func__, cursor_bpp);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_width = %d\n", __func__, cursor_width);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_width_bytes = %d\n", __func__, cursor_width_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_req = %d\n", __func__, cursor_bytes_per_req);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_lines_per_chunk = %d\n", __func__, *cursor_lines_per_chunk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_line = %d\n", __func__, *cursor_bytes_per_line);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_chunk = %d\n", __func__, *cursor_bytes_per_chunk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_bytes = %d\n", __func__, *cursor_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: cursor_pitch = %d\n", __func__, cursor_bpp == 2 ? 256 : (unsigned int)1 &lt;&lt; (unsigned int)math_ceil2(math_log((float)cursor_width, 2), 1));</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_cursor_urgent_burst_factor(</div><div class='add'>+	unsigned int CursorBufferSize,</div><div class='add'>+	unsigned int CursorWidth,</div><div class='add'>+	unsigned int cursor_bytes_per_chunk,</div><div class='add'>+	unsigned int cursor_lines_per_chunk,</div><div class='add'>+	double LineTime,</div><div class='add'>+	double UrgentLatency,</div><div class='add'>+</div><div class='add'>+	double *UrgentBurstFactorCursor,</div><div class='add'>+	bool *NotEnoughUrgentLatencyHiding)</div><div class='add'>+{</div><div class='add'>+	unsigned int LinesInCursorBuffer = 0;</div><div class='add'>+	double CursorBufferSizeInTime = 0;</div><div class='add'>+</div><div class='add'>+	if (CursorWidth &gt; 0) {</div><div class='add'>+		LinesInCursorBuffer = (unsigned int)math_floor2(CursorBufferSize * 1024.0 / (double)cursor_bytes_per_chunk, 1) * cursor_lines_per_chunk;</div><div class='add'>+</div><div class='add'>+		CursorBufferSizeInTime = LinesInCursorBuffer * LineTime;</div><div class='add'>+		if (CursorBufferSizeInTime - UrgentLatency &lt;= 0) {</div><div class='add'>+			*NotEnoughUrgentLatencyHiding = 1;</div><div class='add'>+			*UrgentBurstFactorCursor = 1;</div><div class='add'>+		} else {</div><div class='add'>+			*NotEnoughUrgentLatencyHiding = 0;</div><div class='add'>+			*UrgentBurstFactorCursor = CursorBufferSizeInTime / (CursorBufferSizeInTime - UrgentLatency);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: LinesInCursorBuffer = %u\n", __func__, LinesInCursorBuffer);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: CursorBufferSizeInTime = %f\n", __func__, CursorBufferSizeInTime);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: CursorBufferSize = %u (kbytes)\n", __func__, CursorBufferSize);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_chunk = %u\n", __func__, cursor_bytes_per_chunk);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: cursor_lines_per_chunk = %u\n", __func__, cursor_lines_per_chunk);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: UrgentBurstFactorCursor = %f\n", __func__, *UrgentBurstFactorCursor);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: NotEnoughUrgentLatencyHiding = %d\n", __func__, *NotEnoughUrgentLatencyHiding);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateUrgentBurstFactor(</div><div class='add'>+	const struct dml2_plane_parameters *plane_cfg,</div><div class='add'>+	unsigned int swath_width_luma_ub,</div><div class='add'>+	unsigned int swath_width_chroma_ub,</div><div class='add'>+	unsigned int SwathHeightY,</div><div class='add'>+	unsigned int SwathHeightC,</div><div class='add'>+	double LineTime,</div><div class='add'>+	double UrgentLatency,</div><div class='add'>+	double VRatio,</div><div class='add'>+	double VRatioC,</div><div class='add'>+	double BytePerPixelInDETY,</div><div class='add'>+	double BytePerPixelInDETC,</div><div class='add'>+	unsigned int DETBufferSizeY,</div><div class='add'>+	unsigned int DETBufferSizeC,</div><div class='add'>+	// Output</div><div class='add'>+	double *UrgentBurstFactorLuma,</div><div class='add'>+	double *UrgentBurstFactorChroma,</div><div class='add'>+	bool *NotEnoughUrgentLatencyHiding)</div><div class='add'>+{</div><div class='add'>+	double LinesInDETLuma;</div><div class='add'>+	double LinesInDETChroma;</div><div class='add'>+	double DETBufferSizeInTimeLuma;</div><div class='add'>+	double DETBufferSizeInTimeChroma;</div><div class='add'>+</div><div class='add'>+	*NotEnoughUrgentLatencyHiding = 0;</div><div class='add'>+	*UrgentBurstFactorLuma = 0;</div><div class='add'>+	*UrgentBurstFactorChroma = 0;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VRatio = %f\n", __func__, VRatio);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VRatioC = %f\n", __func__, VRatioC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DETBufferSizeY = %d\n", __func__, DETBufferSizeY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DETBufferSizeC = %d\n", __func__, DETBufferSizeC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelInDETY = %f\n", __func__, BytePerPixelInDETY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, LineTime);</div><div class='add'>+#endif</div><div class='add'>+	DML_ASSERT(VRatio &gt; 0);</div><div class='add'>+</div><div class='add'>+	LinesInDETLuma = (dml_is_phantom_pipe(plane_cfg) ? 1024 * 1024 : DETBufferSizeY) / BytePerPixelInDETY / swath_width_luma_ub;</div><div class='add'>+</div><div class='add'>+	DETBufferSizeInTimeLuma = math_floor2(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;</div><div class='add'>+	if (DETBufferSizeInTimeLuma - UrgentLatency &lt;= 0) {</div><div class='add'>+		*NotEnoughUrgentLatencyHiding = 1;</div><div class='add'>+		*UrgentBurstFactorLuma = 1;</div><div class='add'>+	} else {</div><div class='add'>+		*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (BytePerPixelInDETC &gt; 0) {</div><div class='add'>+		LinesInDETChroma = (dml_is_phantom_pipe(plane_cfg) ? 1024 * 1024 : DETBufferSizeC) / BytePerPixelInDETC / swath_width_chroma_ub;</div><div class='add'>+</div><div class='add'>+		DETBufferSizeInTimeChroma = math_floor2(LinesInDETChroma, SwathHeightC) * LineTime / VRatioC;</div><div class='add'>+		if (DETBufferSizeInTimeChroma - UrgentLatency &lt;= 0) {</div><div class='add'>+			*NotEnoughUrgentLatencyHiding = 1;</div><div class='add'>+			*UrgentBurstFactorChroma = 1;</div><div class='add'>+		} else {</div><div class='add'>+			*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma / (DETBufferSizeInTimeChroma - UrgentLatency);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: LinesInDETLuma = %f\n", __func__, LinesInDETLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DETBufferSizeInTimeLuma = %f\n", __func__, DETBufferSizeInTimeLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentBurstFactorLuma = %f\n", __func__, *UrgentBurstFactorLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentBurstFactorChroma = %f\n", __func__, *UrgentBurstFactorChroma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NotEnoughUrgentLatencyHiding = %d\n", __func__, *NotEnoughUrgentLatencyHiding);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateDCFCLKDeepSleepTdlut(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int BytePerPixelY[],</div><div class='add'>+	unsigned int BytePerPixelC[],</div><div class='add'>+	unsigned int SwathWidthY[],</div><div class='add'>+	unsigned int SwathWidthC[],</div><div class='add'>+	unsigned int DPPPerSurface[],</div><div class='add'>+	double PSCL_THROUGHPUT[],</div><div class='add'>+	double PSCL_THROUGHPUT_CHROMA[],</div><div class='add'>+	double Dppclk[],</div><div class='add'>+	double ReadBandwidthLuma[],</div><div class='add'>+	double ReadBandwidthChroma[],</div><div class='add'>+	unsigned int ReturnBusWidth,</div><div class='add'>+</div><div class='add'>+	double dispclk,</div><div class='add'>+	unsigned int tdlut_bytes_to_deliver[],</div><div class='add'>+	double prefetch_swath_time_us[],</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *DCFClkDeepSleep)</div><div class='add'>+{</div><div class='add'>+	double DisplayPipeLineDeliveryTimeLuma;</div><div class='add'>+	double DisplayPipeLineDeliveryTimeChroma;</div><div class='add'>+	double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES];</div><div class='add'>+	double ReadBandwidth = 0.0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		double pixel_rate_mhz = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio &lt;= 1) {</div><div class='add'>+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_rate_mhz;</div><div class='add'>+		} else {</div><div class='add'>+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];</div><div class='add'>+		}</div><div class='add'>+		if (BytePerPixelC[k] == 0) {</div><div class='add'>+			DisplayPipeLineDeliveryTimeChroma = 0;</div><div class='add'>+		} else {</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio &lt;= 1) {</div><div class='add'>+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerSurface[k] / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_rate_mhz;</div><div class='add'>+			} else {</div><div class='add'>+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (BytePerPixelC[k] &gt; 0) {</div><div class='add'>+			DCFClkDeepSleepPerSurface[k] = math_max2(__DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,</div><div class='add'>+				__DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);</div><div class='add'>+		} else {</div><div class='add'>+			DCFClkDeepSleepPerSurface[k] = __DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;</div><div class='add'>+		}</div><div class='add'>+		DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], pixel_rate_mhz / 16);</div><div class='add'>+</div><div class='add'>+		// adjust for 3dlut delivery time</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut &amp;&amp; tdlut_bytes_to_deliver[k] &gt; 0) {</div><div class='add'>+			double tdlut_required_deepsleep_dcfclk = (double) tdlut_bytes_to_deliver[k] / 64.0 / prefetch_swath_time_us[k];</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, tdlut_bytes_to_deliver = %d\n", __func__, k, tdlut_bytes_to_deliver[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_swath_time_us = %f\n", __func__, k, prefetch_swath_time_us[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, tdlut_required_deepsleep_dcfclk = %f\n", __func__, k, tdlut_required_deepsleep_dcfclk);</div><div class='add'>+</div><div class='add'>+			// increase the deepsleep dcfclk to match the original dispclk throughput rate</div><div class='add'>+			if (tdlut_required_deepsleep_dcfclk &gt; DCFClkDeepSleepPerSurface[k]) {</div><div class='add'>+				DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], tdlut_required_deepsleep_dcfclk);</div><div class='add'>+				DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], dispclk / 4.0);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PixelClock = %f\n", __func__, k, pixel_rate_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*DCFClkDeepSleep = math_max2(8.0, __DML2_CALCS_DCFCLK_FACTOR__ * ReadBandwidth / (double)ReturnBusWidth);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: __DML2_CALCS_DCFCLK_FACTOR__ = %f\n", __func__, __DML2_CALCS_DCFCLK_FACTOR__);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ReadBandwidth = %f\n", __func__, ReadBandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ReturnBusWidth = %u\n", __func__, ReturnBusWidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFClkDeepSleep = %f\n", __func__, *DCFClkDeepSleep);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		*DCFClkDeepSleep = math_max2(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFClkDeepSleep = %f (final)\n", __func__, *DCFClkDeepSleep);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static noinline_for_stack void CalculateDCFCLKDeepSleep(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int BytePerPixelY[],</div><div class='add'>+	unsigned int BytePerPixelC[],</div><div class='add'>+	unsigned int SwathWidthY[],</div><div class='add'>+	unsigned int SwathWidthC[],</div><div class='add'>+	unsigned int DPPPerSurface[],</div><div class='add'>+	double PSCL_THROUGHPUT[],</div><div class='add'>+	double PSCL_THROUGHPUT_CHROMA[],</div><div class='add'>+	double Dppclk[],</div><div class='add'>+	double ReadBandwidthLuma[],</div><div class='add'>+	double ReadBandwidthChroma[],</div><div class='add'>+	unsigned int ReturnBusWidth,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *DCFClkDeepSleep)</div><div class='add'>+{</div><div class='add'>+	double zero_double[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int zero_integer[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	memset(zero_double, 0, DML2_MAX_PLANES * sizeof(double));</div><div class='add'>+	memset(zero_integer, 0, DML2_MAX_PLANES * sizeof(unsigned int));</div><div class='add'>+</div><div class='add'>+	CalculateDCFCLKDeepSleepTdlut(</div><div class='add'>+		display_cfg,</div><div class='add'>+		NumberOfActiveSurfaces,</div><div class='add'>+		BytePerPixelY,</div><div class='add'>+		BytePerPixelC,</div><div class='add'>+		SwathWidthY,</div><div class='add'>+		SwathWidthC,</div><div class='add'>+		DPPPerSurface,</div><div class='add'>+		PSCL_THROUGHPUT,</div><div class='add'>+		PSCL_THROUGHPUT_CHROMA,</div><div class='add'>+		Dppclk,</div><div class='add'>+		ReadBandwidthLuma,</div><div class='add'>+		ReadBandwidthChroma,</div><div class='add'>+		ReturnBusWidth,</div><div class='add'>+		0,</div><div class='add'>+		zero_integer, //tdlut_bytes_to_deliver,</div><div class='add'>+		zero_double, //prefetch_swath_time_us,</div><div class='add'>+</div><div class='add'>+		// Output</div><div class='add'>+		DCFClkDeepSleep);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateWriteBackDelay(</div><div class='add'>+	enum dml2_source_format_class WritebackPixelFormat,</div><div class='add'>+	double WritebackHRatio,</div><div class='add'>+	double WritebackVRatio,</div><div class='add'>+	unsigned int WritebackVTaps,</div><div class='add'>+	unsigned int WritebackDestinationWidth,</div><div class='add'>+	unsigned int WritebackDestinationHeight,</div><div class='add'>+	unsigned int WritebackSourceHeight,</div><div class='add'>+	unsigned int HTotal)</div><div class='add'>+{</div><div class='add'>+	double CalculateWriteBackDelay;</div><div class='add'>+	double Line_length;</div><div class='add'>+	double Output_lines_last_notclamped;</div><div class='add'>+	double WritebackVInit;</div><div class='add'>+</div><div class='add'>+	WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2;</div><div class='add'>+	Line_length = math_max2((double)WritebackDestinationWidth, math_ceil2((double)WritebackDestinationWidth / 6.0, 1.0) * WritebackVTaps);</div><div class='add'>+	Output_lines_last_notclamped = WritebackDestinationHeight - 1 - math_ceil2(((double)WritebackSourceHeight - (double)WritebackVInit) / (double)WritebackVRatio, 1.0);</div><div class='add'>+	if (Output_lines_last_notclamped &lt; 0) {</div><div class='add'>+		CalculateWriteBackDelay = 0;</div><div class='add'>+	} else {</div><div class='add'>+		CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length + (HTotal - WritebackDestinationWidth) + 80;</div><div class='add'>+	}</div><div class='add'>+	return CalculateWriteBackDelay;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int CalculateMaxVStartup(</div><div class='add'>+	bool ptoi_supported,</div><div class='add'>+	unsigned int vblank_nom_default_us,</div><div class='add'>+	const struct dml2_timing_cfg *timing,</div><div class='add'>+	double write_back_delay_us)</div><div class='add'>+{</div><div class='add'>+	unsigned int vblank_size = 0;</div><div class='add'>+	unsigned int max_vstartup_lines = 0;</div><div class='add'>+</div><div class='add'>+	double line_time_us = (double)timing-&gt;h_total / ((double)timing-&gt;pixel_clock_khz / 1000);</div><div class='add'>+	unsigned int vblank_actual = timing-&gt;v_total - timing-&gt;v_active;</div><div class='add'>+	unsigned int vblank_nom_default_in_line = (unsigned int)math_floor2((double)vblank_nom_default_us / line_time_us, 1.0);</div><div class='add'>+	unsigned int vblank_avail = (timing-&gt;vblank_nom == 0) ? vblank_nom_default_in_line : (unsigned int)timing-&gt;vblank_nom;</div><div class='add'>+</div><div class='add'>+	vblank_size = (unsigned int)math_min2(vblank_actual, vblank_avail);</div><div class='add'>+</div><div class='add'>+	if (timing-&gt;interlaced &amp;&amp; !ptoi_supported)</div><div class='add'>+		max_vstartup_lines = (unsigned int)(math_floor2((vblank_size - 1) / 2.0, 1.0));</div><div class='add'>+	else</div><div class='add'>+		max_vstartup_lines = vblank_size - (unsigned int)math_max2(1.0, math_ceil2(write_back_delay_us / line_time_us, 1.0));</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VBlankNom = %lu\n", __func__, timing-&gt;vblank_nom);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vblank_nom_default_us = %u\n", __func__, vblank_nom_default_us);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: line_time_us = %f\n", __func__, line_time_us);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vblank_actual = %u\n", __func__, vblank_actual);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vblank_avail = %u\n", __func__, vblank_avail);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_vstartup_lines = %u\n", __func__, max_vstartup_lines);</div><div class='add'>+#endif</div><div class='add'>+	max_vstartup_lines = (unsigned int)math_min2(max_vstartup_lines, DML_MAX_VSTARTUP_START);</div><div class='add'>+	return max_vstartup_lines;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch *scratch,</div><div class='add'>+	struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int MaximumSwathHeightY[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+	unsigned int MaximumSwathHeightC[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+	unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+	unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+	unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+	unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+</div><div class='add'>+	unsigned int TotalActiveDPP = 0;</div><div class='add'>+	bool NoChromaOrLinear = true;</div><div class='add'>+	unsigned int SurfaceDoingUnboundedRequest = 0;</div><div class='add'>+	unsigned int DETBufferSizeInKByteForSwathCalculation;</div><div class='add'>+</div><div class='add'>+	const long TTUFIFODEPTH = 8;</div><div class='add'>+	const long MAXIMUMCOMPRESSION = 4;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ForceSingleDPP = %u\n", __func__, p-&gt;ForceSingleDPP);</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: DPPPerSurface[%u] = %u\n", __func__, k, p-&gt;DPPPerSurface[k]);</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+	CalculateSwathWidth(</div><div class='add'>+		p-&gt;display_cfg,</div><div class='add'>+		p-&gt;ForceSingleDPP,</div><div class='add'>+		p-&gt;NumberOfActiveSurfaces,</div><div class='add'>+		p-&gt;ODMMode,</div><div class='add'>+		p-&gt;BytePerPixY,</div><div class='add'>+		p-&gt;BytePerPixC,</div><div class='add'>+		p-&gt;Read256BytesBlockHeightY,</div><div class='add'>+		p-&gt;Read256BytesBlockHeightC,</div><div class='add'>+		p-&gt;Read256BytesBlockWidthY,</div><div class='add'>+		p-&gt;Read256BytesBlockWidthC,</div><div class='add'>+		p-&gt;surf_linear128_l,</div><div class='add'>+		p-&gt;surf_linear128_c,</div><div class='add'>+		p-&gt;DPPPerSurface,</div><div class='add'>+</div><div class='add'>+		// Output</div><div class='add'>+		p-&gt;req_per_swath_ub_l,</div><div class='add'>+		p-&gt;req_per_swath_ub_c,</div><div class='add'>+		SwathWidthSingleDPP,</div><div class='add'>+		SwathWidthSingleDPPChroma,</div><div class='add'>+		p-&gt;SwathWidth,</div><div class='add'>+		p-&gt;SwathWidthChroma,</div><div class='add'>+		MaximumSwathHeightY,</div><div class='add'>+		MaximumSwathHeightC,</div><div class='add'>+		p-&gt;swath_width_luma_ub,</div><div class='add'>+		p-&gt;swath_width_chroma_ub);</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		p-&gt;full_swath_bytes_l[k] = (unsigned int)(p-&gt;swath_width_luma_ub[k] * p-&gt;BytePerPixDETY[k] * MaximumSwathHeightY[k]);</div><div class='add'>+		p-&gt;full_swath_bytes_c[k] = (unsigned int)(p-&gt;swath_width_chroma_ub[k] * p-&gt;BytePerPixDETC[k] * MaximumSwathHeightC[k]);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, p-&gt;DPPPerSurface[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u swath_width_luma_ub = %u\n", __func__, k, p-&gt;swath_width_luma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u BytePerPixDETY = %f\n", __func__, k, p-&gt;BytePerPixDETY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightY = %u\n", __func__, k, MaximumSwathHeightY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, p-&gt;full_swath_bytes_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u swath_width_chroma_ub = %u\n", __func__, k, p-&gt;swath_width_chroma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u BytePerPixDETC = %f\n", __func__, k, p-&gt;BytePerPixDETC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightC = %u\n", __func__, k, MaximumSwathHeightC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, p-&gt;full_swath_bytes_c[k]);</div><div class='add'>+#endif</div><div class='add'>+		if (p-&gt;display_cfg-&gt;plane_descriptors[k].pixel_format == dml2_420_10) {</div><div class='add'>+			p-&gt;full_swath_bytes_l[k] = (unsigned int)(math_ceil2((double)p-&gt;full_swath_bytes_l[k], 256));</div><div class='add'>+			p-&gt;full_swath_bytes_c[k] = (unsigned int)(math_ceil2((double)p-&gt;full_swath_bytes_c[k], 256));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		TotalActiveDPP = TotalActiveDPP + (p-&gt;ForceSingleDPP ? 1 : p-&gt;DPPPerSurface[k]);</div><div class='add'>+		if (p-&gt;DPPPerSurface[k] &gt; 0)</div><div class='add'>+			SurfaceDoingUnboundedRequest = k;</div><div class='add'>+		if (dml_is_420(p-&gt;display_cfg-&gt;plane_descriptors[k].pixel_format) || p-&gt;display_cfg-&gt;plane_descriptors[k].pixel_format == dml2_rgbe_alpha</div><div class='add'>+			|| p-&gt;display_cfg-&gt;plane_descriptors[k].surface.tiling == dml2_sw_linear) {</div><div class='add'>+			NoChromaOrLinear = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;UnboundedRequestEnabled = UnboundedRequest(p-&gt;display_cfg-&gt;overrides.hw.force_unbounded_requesting.enable, p-&gt;display_cfg-&gt;overrides.hw.force_unbounded_requesting.value, TotalActiveDPP, NoChromaOrLinear);</div><div class='add'>+</div><div class='add'>+	CalculateDETBufferSize(</div><div class='add'>+		&amp;scratch-&gt;CalculateDETBufferSize_locals,</div><div class='add'>+		p-&gt;display_cfg,</div><div class='add'>+		p-&gt;ForceSingleDPP,</div><div class='add'>+		p-&gt;NumberOfActiveSurfaces,</div><div class='add'>+		*p-&gt;UnboundedRequestEnabled,</div><div class='add'>+		p-&gt;nomDETInKByte,</div><div class='add'>+		p-&gt;MaxTotalDETInKByte,</div><div class='add'>+		p-&gt;ConfigReturnBufferSizeInKByte,</div><div class='add'>+		p-&gt;MinCompressedBufferSizeInKByte,</div><div class='add'>+		p-&gt;ConfigReturnBufferSegmentSizeInkByte,</div><div class='add'>+		p-&gt;CompressedBufferSegmentSizeInkByte,</div><div class='add'>+		p-&gt;ReadBandwidthLuma,</div><div class='add'>+		p-&gt;ReadBandwidthChroma,</div><div class='add'>+		p-&gt;full_swath_bytes_l,</div><div class='add'>+		p-&gt;full_swath_bytes_c,</div><div class='add'>+		p-&gt;DPPPerSurface,</div><div class='add'>+</div><div class='add'>+		// Output</div><div class='add'>+		p-&gt;DETBufferSizeInKByte, // per hubp pipe</div><div class='add'>+		p-&gt;CompressedBufferSizeInkByte);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalActiveDPP = %u\n", __func__, TotalActiveDPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: nomDETInKByte = %u\n", __func__, p-&gt;nomDETInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ConfigReturnBufferSizeInKByte = %u\n", __func__, p-&gt;ConfigReturnBufferSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UnboundedRequestEnabled = %u\n", __func__, *p-&gt;UnboundedRequestEnabled);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, *p-&gt;CompressedBufferSizeInkByte);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	*p-&gt;ViewportSizeSupport = true;</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+</div><div class='add'>+		DETBufferSizeInKByteForSwathCalculation = (dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k]) ? 1024 : p-&gt;DETBufferSizeInKByte[k]);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation = %u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);</div><div class='add'>+#endif</div><div class='add'>+		if (p-&gt;display_cfg-&gt;plane_descriptors[k].surface.tiling == dml2_sw_linear) {</div><div class='add'>+			p-&gt;SwathHeightY[k] = MaximumSwathHeightY[k];</div><div class='add'>+			p-&gt;SwathHeightC[k] = MaximumSwathHeightC[k];</div><div class='add'>+			RoundedUpSwathSizeBytesY[k] = p-&gt;full_swath_bytes_l[k];</div><div class='add'>+			RoundedUpSwathSizeBytesC[k] = p-&gt;full_swath_bytes_c[k];</div><div class='add'>+</div><div class='add'>+			if (p-&gt;surf_linear128_l[k])</div><div class='add'>+				p-&gt;request_size_bytes_luma[k] = 128;</div><div class='add'>+			else</div><div class='add'>+				p-&gt;request_size_bytes_luma[k] = 256;</div><div class='add'>+</div><div class='add'>+			if (p-&gt;surf_linear128_c[k])</div><div class='add'>+				p-&gt;request_size_bytes_chroma[k] = 128;</div><div class='add'>+			else</div><div class='add'>+				p-&gt;request_size_bytes_chroma[k] = 256;</div><div class='add'>+</div><div class='add'>+		} else if (p-&gt;full_swath_bytes_l[k] + p-&gt;full_swath_bytes_c[k] &lt;= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {</div><div class='add'>+			p-&gt;SwathHeightY[k] = MaximumSwathHeightY[k];</div><div class='add'>+			p-&gt;SwathHeightC[k] = MaximumSwathHeightC[k];</div><div class='add'>+			RoundedUpSwathSizeBytesY[k] = p-&gt;full_swath_bytes_l[k];</div><div class='add'>+			RoundedUpSwathSizeBytesC[k] = p-&gt;full_swath_bytes_c[k];</div><div class='add'>+			p-&gt;request_size_bytes_luma[k] = 256;</div><div class='add'>+			p-&gt;request_size_bytes_chroma[k] = 256;</div><div class='add'>+</div><div class='add'>+		} else if (p-&gt;full_swath_bytes_l[k] &gt;= 1.5 * p-&gt;full_swath_bytes_c[k] &amp;&amp; p-&gt;full_swath_bytes_l[k] / 2 + p-&gt;full_swath_bytes_c[k] &lt;= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {</div><div class='add'>+			p-&gt;SwathHeightY[k] = MaximumSwathHeightY[k] / 2;</div><div class='add'>+			p-&gt;SwathHeightC[k] = MaximumSwathHeightC[k];</div><div class='add'>+			RoundedUpSwathSizeBytesY[k] = p-&gt;full_swath_bytes_l[k] / 2;</div><div class='add'>+			RoundedUpSwathSizeBytesC[k] = p-&gt;full_swath_bytes_c[k];</div><div class='add'>+			p-&gt;request_size_bytes_luma[k] = ((p-&gt;BytePerPixY[k] == 2) == dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;</div><div class='add'>+			p-&gt;request_size_bytes_chroma[k] = 256;</div><div class='add'>+</div><div class='add'>+		} else if (p-&gt;full_swath_bytes_l[k] &lt; 1.5 * p-&gt;full_swath_bytes_c[k] &amp;&amp; p-&gt;full_swath_bytes_l[k] + p-&gt;full_swath_bytes_c[k] / 2 &lt;= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {</div><div class='add'>+			p-&gt;SwathHeightY[k] = MaximumSwathHeightY[k];</div><div class='add'>+			p-&gt;SwathHeightC[k] = MaximumSwathHeightC[k] / 2;</div><div class='add'>+			RoundedUpSwathSizeBytesY[k] = p-&gt;full_swath_bytes_l[k];</div><div class='add'>+			RoundedUpSwathSizeBytesC[k] = p-&gt;full_swath_bytes_c[k] / 2;</div><div class='add'>+			p-&gt;request_size_bytes_luma[k] = 256;</div><div class='add'>+			p-&gt;request_size_bytes_chroma[k] = ((p-&gt;BytePerPixC[k] == 2) == dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;SwathHeightY[k] = MaximumSwathHeightY[k] / 2;</div><div class='add'>+			p-&gt;SwathHeightC[k] = MaximumSwathHeightC[k] / 2;</div><div class='add'>+			RoundedUpSwathSizeBytesY[k] = p-&gt;full_swath_bytes_l[k] / 2;</div><div class='add'>+			RoundedUpSwathSizeBytesC[k] = p-&gt;full_swath_bytes_c[k] / 2;</div><div class='add'>+			p-&gt;request_size_bytes_luma[k] = ((p-&gt;BytePerPixY[k] == 2) == dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;</div><div class='add'>+			p-&gt;request_size_bytes_chroma[k] = ((p-&gt;BytePerPixC[k] == 2) == dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;SwathHeightC[k] == 0)</div><div class='add'>+			p-&gt;request_size_bytes_chroma[k] = 0;</div><div class='add'>+</div><div class='add'>+		if ((p-&gt;full_swath_bytes_l[k] / 2 + p-&gt;full_swath_bytes_c[k] / 2 &gt; DETBufferSizeInKByteForSwathCalculation * 1024 / 2) ||</div><div class='add'>+			p-&gt;SwathWidth[k] &gt; p-&gt;MaximumSwathWidthLuma[k] || (p-&gt;SwathHeightC[k] &gt; 0 &amp;&amp; p-&gt;SwathWidthChroma[k] &gt; p-&gt;MaximumSwathWidthChroma[k])) {</div><div class='add'>+			*p-&gt;ViewportSizeSupport = false;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l=%u\n", __func__, k, p-&gt;full_swath_bytes_l[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c=%u\n", __func__, k, p-&gt;full_swath_bytes_c[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation=%u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u SwathWidth=%u\n", __func__, k, p-&gt;SwathWidth[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthLuma=%f\n", __func__, k, p-&gt;MaximumSwathWidthLuma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthChroma=%d\n", __func__, k, p-&gt;SwathWidthChroma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthChroma=%f\n", __func__, k, p-&gt;MaximumSwathWidthChroma[k]);</div><div class='add'>+			p-&gt;ViewportSizeSupportPerSurface[k] = false;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;ViewportSizeSupportPerSurface[k] = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;SwathHeightC[k] == 0) {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, All DET will be used for plane0\n", __func__, k);</div><div class='add'>+#endif</div><div class='add'>+			p-&gt;DETBufferSizeY[k] = p-&gt;DETBufferSizeInKByte[k] * 1024;</div><div class='add'>+			p-&gt;DETBufferSizeC[k] = 0;</div><div class='add'>+		} else if (RoundedUpSwathSizeBytesY[k] &lt;= 1.5 * RoundedUpSwathSizeBytesC[k]) {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, Half DET will be used for plane0, and half for plane1\n", __func__, k);</div><div class='add'>+#endif</div><div class='add'>+			p-&gt;DETBufferSizeY[k] = p-&gt;DETBufferSizeInKByte[k] * 1024 / 2;</div><div class='add'>+			p-&gt;DETBufferSizeC[k] = p-&gt;DETBufferSizeInKByte[k] * 1024 / 2;</div><div class='add'>+		} else {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, 2/3 DET will be used for plane0, and 1/3 for plane1\n", __func__, k);</div><div class='add'>+#endif</div><div class='add'>+			p-&gt;DETBufferSizeY[k] = (unsigned int)(math_floor2(p-&gt;DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024));</div><div class='add'>+			p-&gt;DETBufferSizeC[k] = p-&gt;DETBufferSizeInKByte[k] * 1024 - p-&gt;DETBufferSizeY[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u SwathHeightY = %u\n", __func__, k, p-&gt;SwathHeightY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u SwathHeightC = %u\n", __func__, k, p-&gt;SwathHeightC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, p-&gt;full_swath_bytes_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, p-&gt;full_swath_bytes_c[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesY = %u\n", __func__, k, RoundedUpSwathSizeBytesY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, p-&gt;DETBufferSizeInKByte[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeY = %u\n", __func__, k, p-&gt;DETBufferSizeY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeC = %u\n", __func__, k, p-&gt;DETBufferSizeC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u ViewportSizeSupportPerSurface = %u\n", __func__, k, p-&gt;ViewportSizeSupportPerSurface[k]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;compbuf_reserved_space_64b = 2 * p-&gt;pixel_chunk_size_kbytes * 1024 / 64;</div><div class='add'>+	if (*p-&gt;UnboundedRequestEnabled) {</div><div class='add'>+		*p-&gt;compbuf_reserved_space_64b = (unsigned int)math_ceil2(math_max2(*p-&gt;compbuf_reserved_space_64b,</div><div class='add'>+			(double)(p-&gt;rob_buffer_size_kbytes * 1024 / 64) - (double)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * TTUFIFODEPTH / (p-&gt;mrq_present ? MAXIMUMCOMPRESSION : 1) / 64)), 1.0);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: RoundedUpSwathSizeBytesY[%d] = %u\n", __func__, SurfaceDoingUnboundedRequest, RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: rob_buffer_size_kbytes = %u\n", __func__, p-&gt;rob_buffer_size_kbytes);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: compbuf_reserved_space_64b = %u\n", __func__, *p-&gt;compbuf_reserved_space_64b);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	*p-&gt;hw_debug5 = false;</div><div class='add'>+#ifdef ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE</div><div class='add'>+	if (p-&gt;NumberOfActiveSurfaces &gt; 1)</div><div class='add'>+		*p-&gt;hw_debug5 = true;</div><div class='add'>+#else</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (!(p-&gt;mrq_present) &amp;&amp; (!(*p-&gt;UnboundedRequestEnabled)) &amp;&amp; (TotalActiveDPP == 1)</div><div class='add'>+			&amp;&amp; p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.enable</div><div class='add'>+			&amp;&amp; ((p-&gt;rob_buffer_size_kbytes * 1024 * (p-&gt;mrq_present ? MAXIMUMCOMPRESSION : 1)</div><div class='add'>+				+ *p-&gt;CompressedBufferSizeInkByte * MAXIMUMCOMPRESSION * 1024) &gt; TTUFIFODEPTH * (RoundedUpSwathSizeBytesY[k] + RoundedUpSwathSizeBytesC[k])))</div><div class='add'>+			*p-&gt;hw_debug5 = true;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u UnboundedRequestEnabled = %u\n", __func__, k, *p-&gt;UnboundedRequestEnabled);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MAXIMUMCOMPRESSION = %lu\n", __func__, k, MAXIMUMCOMPRESSION);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u TTUFIFODEPTH = %lu\n", __func__, k, TTUFIFODEPTH);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u CompressedBufferSizeInkByte = %u\n", __func__, k, *p-&gt;CompressedBufferSizeInkByte);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u hw_debug5 = %u\n", __func__, k, *p-&gt;hw_debug5);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_odm_mode DecideODMMode(unsigned int HActive,</div><div class='add'>+	double MaxDispclk,</div><div class='add'>+	unsigned int MaximumPixelsPerLinePerDSCUnit,</div><div class='add'>+	enum dml2_output_format_class OutFormat,</div><div class='add'>+	bool UseDSC,</div><div class='add'>+	unsigned int NumberOfDSCSlices,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithoutODMCombine,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineTwoToOne,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineThreeToOne,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineFourToOne)</div><div class='add'>+{</div><div class='add'>+	enum dml2_odm_mode MinimumRequiredODMModeForMaxDispClock;</div><div class='add'>+	enum dml2_odm_mode MinimumRequiredODMModeForMaxDSCHActive;</div><div class='add'>+	enum dml2_odm_mode MinimumRequiredODMModeForMax420HActive;</div><div class='add'>+	enum dml2_odm_mode ODMMode = dml2_odm_mode_bypass;</div><div class='add'>+</div><div class='add'>+	MinimumRequiredODMModeForMaxDispClock =</div><div class='add'>+			(SurfaceRequiredDISPCLKWithoutODMCombine &lt;= MaxDispclk) ? dml2_odm_mode_bypass :</div><div class='add'>+			(SurfaceRequiredDISPCLKWithODMCombineTwoToOne &lt;= MaxDispclk) ? dml2_odm_mode_combine_2to1 :</div><div class='add'>+			(SurfaceRequiredDISPCLKWithODMCombineThreeToOne &lt;= MaxDispclk) ? dml2_odm_mode_combine_3to1 : dml2_odm_mode_combine_4to1;</div><div class='add'>+	if (ODMMode &lt; MinimumRequiredODMModeForMaxDispClock)</div><div class='add'>+		ODMMode = MinimumRequiredODMModeForMaxDispClock;</div><div class='add'>+</div><div class='add'>+	if (UseDSC) {</div><div class='add'>+		MinimumRequiredODMModeForMaxDSCHActive =</div><div class='add'>+				(HActive &lt;= 1 * MaximumPixelsPerLinePerDSCUnit) ? dml2_odm_mode_bypass :</div><div class='add'>+				(HActive &lt;= 2 * MaximumPixelsPerLinePerDSCUnit) ? dml2_odm_mode_combine_2to1 :</div><div class='add'>+				(HActive &lt;= 3 * MaximumPixelsPerLinePerDSCUnit) ? dml2_odm_mode_combine_3to1 : dml2_odm_mode_combine_4to1;</div><div class='add'>+		if (ODMMode &lt; MinimumRequiredODMModeForMaxDSCHActive)</div><div class='add'>+			ODMMode = MinimumRequiredODMModeForMaxDSCHActive;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (OutFormat == dml2_420) {</div><div class='add'>+		MinimumRequiredODMModeForMax420HActive =</div><div class='add'>+				(HActive &lt;= 1 * DML2_MAX_FMT_420_BUFFER_WIDTH) ? dml2_odm_mode_bypass :</div><div class='add'>+				(HActive &lt;= 2 * DML2_MAX_FMT_420_BUFFER_WIDTH) ? dml2_odm_mode_combine_2to1 :</div><div class='add'>+				(HActive &lt;= 3 * DML2_MAX_FMT_420_BUFFER_WIDTH) ? dml2_odm_mode_combine_3to1 : dml2_odm_mode_combine_4to1;</div><div class='add'>+		if (ODMMode &lt; MinimumRequiredODMModeForMax420HActive)</div><div class='add'>+			ODMMode = MinimumRequiredODMModeForMax420HActive;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (UseDSC) {</div><div class='add'>+		if (ODMMode == dml2_odm_mode_bypass &amp;&amp; NumberOfDSCSlices &gt; 4)</div><div class='add'>+			ODMMode = dml2_odm_mode_combine_2to1;</div><div class='add'>+		if (ODMMode == dml2_odm_mode_combine_2to1 &amp;&amp; NumberOfDSCSlices &gt; 8)</div><div class='add'>+			ODMMode = dml2_odm_mode_combine_3to1;</div><div class='add'>+		if (ODMMode == dml2_odm_mode_combine_3to1 &amp;&amp; NumberOfDSCSlices != 12)</div><div class='add'>+			ODMMode = dml2_odm_mode_combine_4to1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ODMMode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateODMConstraints(</div><div class='add'>+	enum dml2_odm_mode ODMUse,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithoutODMCombine,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineTwoToOne,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineThreeToOne,</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineFourToOne,</div><div class='add'>+	unsigned int MaximumPixelsPerLinePerDSCUnit,</div><div class='add'>+	/* Output */</div><div class='add'>+	double *DISPCLKRequired,</div><div class='add'>+	unsigned int *NumberOfDPPRequired,</div><div class='add'>+	unsigned int *MaxHActiveForDSC,</div><div class='add'>+	unsigned int *MaxDSCSlices,</div><div class='add'>+	unsigned int *MaxHActiveFor420)</div><div class='add'>+{</div><div class='add'>+	switch (ODMUse) {</div><div class='add'>+	case dml2_odm_mode_combine_2to1:</div><div class='add'>+		*DISPCLKRequired = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;</div><div class='add'>+		*NumberOfDPPRequired = 2;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_odm_mode_combine_3to1:</div><div class='add'>+		*DISPCLKRequired = SurfaceRequiredDISPCLKWithODMCombineThreeToOne;</div><div class='add'>+		*NumberOfDPPRequired = 3;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_odm_mode_combine_4to1:</div><div class='add'>+		*DISPCLKRequired = SurfaceRequiredDISPCLKWithODMCombineFourToOne;</div><div class='add'>+		*NumberOfDPPRequired = 4;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_odm_mode_auto:</div><div class='add'>+	case dml2_odm_mode_split_1to2:</div><div class='add'>+	case dml2_odm_mode_mso_1to2:</div><div class='add'>+	case dml2_odm_mode_mso_1to4:</div><div class='add'>+	case dml2_odm_mode_bypass:</div><div class='add'>+	default:</div><div class='add'>+		*DISPCLKRequired = SurfaceRequiredDISPCLKWithoutODMCombine;</div><div class='add'>+		*NumberOfDPPRequired = 1;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	*MaxHActiveForDSC = *NumberOfDPPRequired * MaximumPixelsPerLinePerDSCUnit;</div><div class='add'>+	*MaxDSCSlices = *NumberOfDPPRequired * DML_MAX_NUM_OF_SLICES_PER_DSC;</div><div class='add'>+	*MaxHActiveFor420 = *NumberOfDPPRequired * DML2_MAX_FMT_420_BUFFER_WIDTH;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool ValidateODMMode(enum dml2_odm_mode ODMMode,</div><div class='add'>+	double MaxDispclk,</div><div class='add'>+	unsigned int HActive,</div><div class='add'>+	enum dml2_output_format_class OutFormat,</div><div class='add'>+	bool UseDSC,</div><div class='add'>+	unsigned int NumberOfDSCSlices,</div><div class='add'>+	unsigned int TotalNumberOfActiveDPP,</div><div class='add'>+	unsigned int TotalNumberOfActiveOPP,</div><div class='add'>+	unsigned int MaxNumDPP,</div><div class='add'>+	unsigned int MaxNumOPP,</div><div class='add'>+	double DISPCLKRequired,</div><div class='add'>+	unsigned int NumberOfDPPRequired,</div><div class='add'>+	unsigned int MaxHActiveForDSC,</div><div class='add'>+	unsigned int MaxDSCSlices,</div><div class='add'>+	unsigned int MaxHActiveFor420)</div><div class='add'>+{</div><div class='add'>+	bool are_odm_segments_symmetrical = (ODMMode == dml2_odm_mode_combine_3to1) ? UseDSC : true;</div><div class='add'>+	bool is_max_dsc_slice_required = (ODMMode == dml2_odm_mode_combine_3to1);</div><div class='add'>+	unsigned int pixels_per_clock_cycle = (OutFormat == dml2_420 || OutFormat == dml2_n422) ? 2 : 1;</div><div class='add'>+	unsigned int h_timing_div_mode =</div><div class='add'>+			(ODMMode == dml2_odm_mode_combine_4to1 || ODMMode == dml2_odm_mode_combine_3to1) ? 4 :</div><div class='add'>+			(ODMMode == dml2_odm_mode_combine_2to1) ? 2 : pixels_per_clock_cycle;</div><div class='add'>+</div><div class='add'>+	if (DISPCLKRequired &gt; MaxDispclk)</div><div class='add'>+		return false;</div><div class='add'>+	if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) &gt; MaxNumDPP || (TotalNumberOfActiveOPP + NumberOfDPPRequired) &gt; MaxNumOPP)</div><div class='add'>+		return false;</div><div class='add'>+	if (are_odm_segments_symmetrical) {</div><div class='add'>+		if (HActive % (NumberOfDPPRequired * pixels_per_clock_cycle))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+	if (HActive % h_timing_div_mode)</div><div class='add'>+		/*</div><div class='add'>+		 * TODO - OTG_H_TOTAL, OTG_H_BLANK_START/END and</div><div class='add'>+		 * OTG_H_SYNC_A_START/END all need to be visible by h timing div</div><div class='add'>+		 * mode. This logic only checks H active.</div><div class='add'>+		 */</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (UseDSC) {</div><div class='add'>+		if (HActive &gt; MaxHActiveForDSC)</div><div class='add'>+			return false;</div><div class='add'>+		if (NumberOfDSCSlices &gt; MaxDSCSlices)</div><div class='add'>+			return false;</div><div class='add'>+		if (HActive % NumberOfDSCSlices)</div><div class='add'>+			return false;</div><div class='add'>+		if (NumberOfDSCSlices % NumberOfDPPRequired)</div><div class='add'>+			return false;</div><div class='add'>+		if (is_max_dsc_slice_required) {</div><div class='add'>+			if (NumberOfDSCSlices != MaxDSCSlices)</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (OutFormat == dml2_420) {</div><div class='add'>+		if (HActive &gt; MaxHActiveFor420)</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static noinline_for_stack void CalculateODMMode(</div><div class='add'>+	unsigned int MaximumPixelsPerLinePerDSCUnit,</div><div class='add'>+	unsigned int HActive,</div><div class='add'>+	enum dml2_output_format_class OutFormat,</div><div class='add'>+	enum dml2_output_encoder_class Output,</div><div class='add'>+	enum dml2_odm_mode ODMUse,</div><div class='add'>+	double MaxDispclk,</div><div class='add'>+	bool DSCEnable,</div><div class='add'>+	unsigned int TotalNumberOfActiveDPP,</div><div class='add'>+	unsigned int TotalNumberOfActiveOPP,</div><div class='add'>+	unsigned int MaxNumDPP,</div><div class='add'>+	unsigned int MaxNumOPP,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	unsigned int NumberOfDSCSlices,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	bool *TotalAvailablePipesSupport,</div><div class='add'>+	unsigned int *NumberOfDPP,</div><div class='add'>+	enum dml2_odm_mode *ODMMode,</div><div class='add'>+	double *RequiredDISPCLKPerSurface)</div><div class='add'>+{</div><div class='add'>+	double SurfaceRequiredDISPCLKWithoutODMCombine;</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineTwoToOne;</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineThreeToOne;</div><div class='add'>+	double SurfaceRequiredDISPCLKWithODMCombineFourToOne;</div><div class='add'>+	double DISPCLKRequired;</div><div class='add'>+	unsigned int NumberOfDPPRequired;</div><div class='add'>+	unsigned int MaxHActiveForDSC;</div><div class='add'>+	unsigned int MaxDSCSlices;</div><div class='add'>+	unsigned int MaxHActiveFor420;</div><div class='add'>+	bool success;</div><div class='add'>+	bool UseDSC = DSCEnable &amp;&amp; (NumberOfDSCSlices &gt; 0);</div><div class='add'>+	enum dml2_odm_mode DecidedODMMode;</div><div class='add'>+	bool isTMDS420 = (OutFormat == dml2_420 &amp;&amp; Output == dml2_hdmi);</div><div class='add'>+</div><div class='add'>+	SurfaceRequiredDISPCLKWithoutODMCombine = CalculateRequiredDispclk(dml2_odm_mode_bypass, PixelClock, isTMDS420);</div><div class='add'>+	SurfaceRequiredDISPCLKWithODMCombineTwoToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_2to1, PixelClock, isTMDS420);</div><div class='add'>+	SurfaceRequiredDISPCLKWithODMCombineThreeToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_3to1, PixelClock, isTMDS420);</div><div class='add'>+	SurfaceRequiredDISPCLKWithODMCombineFourToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_4to1, PixelClock, isTMDS420);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ODMUse = %d\n", __func__, ODMUse);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Output = %d\n", __func__, Output);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSCEnable = %d\n", __func__, DSCEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxDispclk = %f\n", __func__, MaxDispclk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaximumPixelsPerLinePerDSCUnit = %d\n", __func__, MaximumPixelsPerLinePerDSCUnit);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SurfaceRequiredDISPCLKWithoutODMCombine = %f\n", __func__, SurfaceRequiredDISPCLKWithoutODMCombine);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SurfaceRequiredDISPCLKWithODMCombineTwoToOne = %f\n", __func__, SurfaceRequiredDISPCLKWithODMCombineTwoToOne);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SurfaceRequiredDISPCLKWithODMCombineThreeToOne = %f\n", __func__, SurfaceRequiredDISPCLKWithODMCombineThreeToOne);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SurfaceRequiredDISPCLKWithODMCombineFourToOne = %f\n", __func__, SurfaceRequiredDISPCLKWithODMCombineFourToOne);</div><div class='add'>+#endif</div><div class='add'>+	if (ODMUse == dml2_odm_mode_auto)</div><div class='add'>+		DecidedODMMode = DecideODMMode(HActive,</div><div class='add'>+				MaxDispclk,</div><div class='add'>+				MaximumPixelsPerLinePerDSCUnit,</div><div class='add'>+				OutFormat,</div><div class='add'>+				UseDSC,</div><div class='add'>+				NumberOfDSCSlices,</div><div class='add'>+				SurfaceRequiredDISPCLKWithoutODMCombine,</div><div class='add'>+				SurfaceRequiredDISPCLKWithODMCombineTwoToOne,</div><div class='add'>+				SurfaceRequiredDISPCLKWithODMCombineThreeToOne,</div><div class='add'>+				SurfaceRequiredDISPCLKWithODMCombineFourToOne);</div><div class='add'>+	else</div><div class='add'>+		DecidedODMMode = ODMUse;</div><div class='add'>+	CalculateODMConstraints(DecidedODMMode,</div><div class='add'>+			SurfaceRequiredDISPCLKWithoutODMCombine,</div><div class='add'>+			SurfaceRequiredDISPCLKWithODMCombineTwoToOne,</div><div class='add'>+			SurfaceRequiredDISPCLKWithODMCombineThreeToOne,</div><div class='add'>+			SurfaceRequiredDISPCLKWithODMCombineFourToOne,</div><div class='add'>+			MaximumPixelsPerLinePerDSCUnit,</div><div class='add'>+			&amp;DISPCLKRequired,</div><div class='add'>+			&amp;NumberOfDPPRequired,</div><div class='add'>+			&amp;MaxHActiveForDSC,</div><div class='add'>+			&amp;MaxDSCSlices,</div><div class='add'>+			&amp;MaxHActiveFor420);</div><div class='add'>+	success = ValidateODMMode(DecidedODMMode,</div><div class='add'>+			MaxDispclk,</div><div class='add'>+			HActive,</div><div class='add'>+			OutFormat,</div><div class='add'>+			UseDSC,</div><div class='add'>+			NumberOfDSCSlices,</div><div class='add'>+			TotalNumberOfActiveDPP,</div><div class='add'>+			TotalNumberOfActiveOPP,</div><div class='add'>+			MaxNumDPP,</div><div class='add'>+			MaxNumOPP,</div><div class='add'>+			DISPCLKRequired,</div><div class='add'>+			NumberOfDPPRequired,</div><div class='add'>+			MaxHActiveForDSC,</div><div class='add'>+			MaxDSCSlices,</div><div class='add'>+			MaxHActiveFor420);</div><div class='add'>+</div><div class='add'>+	*ODMMode = DecidedODMMode;</div><div class='add'>+	*TotalAvailablePipesSupport = success;</div><div class='add'>+	*NumberOfDPP = NumberOfDPPRequired;</div><div class='add'>+	*RequiredDISPCLKPerSurface = success ? DISPCLKRequired : 0;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ODMMode = %d\n", __func__, *ODMMode);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfDPP = %d\n", __func__, *NumberOfDPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalAvailablePipesSupport = %d\n", __func__, *TotalAvailablePipesSupport);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: RequiredDISPCLKPerSurface = %f\n", __func__, *RequiredDISPCLKPerSurface);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static noinline_for_stack void CalculateOutputLink(</div><div class='add'>+	struct dml2_core_internal_scratch *s,</div><div class='add'>+	double PHYCLK,</div><div class='add'>+	double PHYCLKD18,</div><div class='add'>+	double PHYCLKD32,</div><div class='add'>+	double Downspreading,</div><div class='add'>+	enum dml2_output_encoder_class Output,</div><div class='add'>+	enum dml2_output_format_class OutputFormat,</div><div class='add'>+	unsigned int HTotal,</div><div class='add'>+	unsigned int HActive,</div><div class='add'>+	double PixelClockBackEnd,</div><div class='add'>+	double ForcedOutputLinkBPP,</div><div class='add'>+	unsigned int DSCInputBitPerComponent,</div><div class='add'>+	unsigned int NumberOfDSCSlices,</div><div class='add'>+	double AudioSampleRate,</div><div class='add'>+	unsigned int AudioSampleLayout,</div><div class='add'>+	enum dml2_odm_mode ODMModeNoDSC,</div><div class='add'>+	enum dml2_odm_mode ODMModeDSC,</div><div class='add'>+	enum dml2_dsc_enable_option DSCEnable,</div><div class='add'>+	unsigned int OutputLinkDPLanes,</div><div class='add'>+	enum dml2_output_link_dp_rate OutputLinkDPRate,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	bool *RequiresDSC,</div><div class='add'>+	bool *RequiresFEC,</div><div class='add'>+	double *OutBpp,</div><div class='add'>+	enum dml2_core_internal_output_type *OutputType,</div><div class='add'>+	enum dml2_core_internal_output_type_rate *OutputRate,</div><div class='add'>+	unsigned int *RequiredSlots)</div><div class='add'>+{</div><div class='add'>+	bool LinkDSCEnable;</div><div class='add'>+	unsigned int dummy;</div><div class='add'>+	*RequiresDSC = false;</div><div class='add'>+	*RequiresFEC = false;</div><div class='add'>+	*OutBpp = 0;</div><div class='add'>+</div><div class='add'>+	*OutputType = dml2_core_internal_output_type_unknown;</div><div class='add'>+	*OutputRate = dml2_core_internal_output_rate_unknown;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSCEnable = %u (dis, en, en_if_necessary)\n", __func__, DSCEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PHYCLK = %f\n", __func__, PHYCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelClockBackEnd = %f\n", __func__, PixelClockBackEnd);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: AudioSampleRate = %f\n", __func__, AudioSampleRate);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HActive = %u\n", __func__, HActive);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HTotal = %u\n", __func__, HTotal);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ODMModeNoDSC = %u\n", __func__, ODMModeNoDSC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ODMModeDSC = %u\n", __func__, ODMModeDSC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ForcedOutputLinkBPP = %f\n", __func__, ForcedOutputLinkBPP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Output (encoder) = %u\n", __func__, Output);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: OutputLinkDPRate = %u\n", __func__, OutputLinkDPRate);</div><div class='add'>+#endif</div><div class='add'>+	{</div><div class='add'>+		if (Output == dml2_hdmi) {</div><div class='add'>+			*RequiresDSC = false;</div><div class='add'>+			*RequiresFEC = false;</div><div class='add'>+			*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, math_min2(600, PHYCLK) * 10, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, false, Output,</div><div class='add'>+				OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+			//OutputTypeAndRate = "HDMI";</div><div class='add'>+			*OutputType = dml2_core_internal_output_type_hdmi;</div><div class='add'>+		} else if (Output == dml2_dp || Output == dml2_dp2p0 || Output == dml2_edp) {</div><div class='add'>+			if (DSCEnable == dml2_dsc_enable) {</div><div class='add'>+				*RequiresDSC = true;</div><div class='add'>+				LinkDSCEnable = true;</div><div class='add'>+				if (Output == dml2_dp || Output == dml2_dp2p0) {</div><div class='add'>+					*RequiresFEC = true;</div><div class='add'>+				} else {</div><div class='add'>+					*RequiresFEC = false;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				*RequiresDSC = false;</div><div class='add'>+				LinkDSCEnable = false;</div><div class='add'>+				if (Output == dml2_dp2p0) {</div><div class='add'>+					*RequiresFEC = true;</div><div class='add'>+				} else {</div><div class='add'>+					*RequiresFEC = false;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			if (Output == dml2_dp2p0) {</div><div class='add'>+				*OutBpp = 0;</div><div class='add'>+				if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_uhbr10) &amp;&amp; PHYCLKD32 &gt;= 10000.0 / 32) {</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+						OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLKD32 &lt; 13500.0 / 32 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+						*RequiresDSC = true;</div><div class='add'>+						LinkDSCEnable = true;</div><div class='add'>+						*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 10000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					}</div><div class='add'>+					//OutputTypeAndRate = Output &amp; " UHBR10";</div><div class='add'>+					*OutputType = dml2_core_internal_output_type_dp2p0;</div><div class='add'>+					*OutputRate = dml2_core_internal_output_rate_dp_rate_uhbr10;</div><div class='add'>+				}</div><div class='add'>+				if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_uhbr13p5) &amp;&amp; *OutBpp == 0 &amp;&amp; PHYCLKD32 &gt;= 13500.0 / 32) {</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+						OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLKD32 &lt; 20000.0 / 32 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+						*RequiresDSC = true;</div><div class='add'>+						LinkDSCEnable = true;</div><div class='add'>+						*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					}</div><div class='add'>+					//OutputTypeAndRate = Output &amp; " UHBR13p5";</div><div class='add'>+					*OutputType = dml2_core_internal_output_type_dp2p0;</div><div class='add'>+					*OutputRate = dml2_core_internal_output_rate_dp_rate_uhbr13p5;</div><div class='add'>+				}</div><div class='add'>+				if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_uhbr20) &amp;&amp; *OutBpp == 0 &amp;&amp; PHYCLKD32 &gt;= 20000.0 / 32) {</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+						OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+						*RequiresDSC = true;</div><div class='add'>+						LinkDSCEnable = true;</div><div class='add'>+						*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 20000, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					}</div><div class='add'>+					//OutputTypeAndRate = Output &amp; " UHBR20";</div><div class='add'>+					*OutputType = dml2_core_internal_output_type_dp2p0;</div><div class='add'>+					*OutputRate = dml2_core_internal_output_rate_dp_rate_uhbr20;</div><div class='add'>+				}</div><div class='add'>+			} else { // output is dp or edp</div><div class='add'>+				*OutBpp = 0;</div><div class='add'>+				if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_hbr) &amp;&amp; PHYCLK &gt;= 270) {</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 2700, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+						OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLK &lt; 540 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+						*RequiresDSC = true;</div><div class='add'>+						LinkDSCEnable = true;</div><div class='add'>+						if (Output == dml2_dp) {</div><div class='add'>+							*RequiresFEC = true;</div><div class='add'>+						}</div><div class='add'>+						*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 2700, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					}</div><div class='add'>+					//OutputTypeAndRate = Output &amp; " HBR";</div><div class='add'>+					*OutputType = (Output == dml2_dp) ? dml2_core_internal_output_type_dp : dml2_core_internal_output_type_edp;</div><div class='add'>+					*OutputRate = dml2_core_internal_output_rate_dp_rate_hbr;</div><div class='add'>+				}</div><div class='add'>+				if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_hbr2) &amp;&amp; *OutBpp == 0 &amp;&amp; PHYCLK &gt;= 540) {</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 5400, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+						OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLK &lt; 810 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+						*RequiresDSC = true;</div><div class='add'>+						LinkDSCEnable = true;</div><div class='add'>+						if (Output == dml2_dp) {</div><div class='add'>+							*RequiresFEC = true;</div><div class='add'>+						}</div><div class='add'>+						*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 5400, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					}</div><div class='add'>+					//OutputTypeAndRate = Output &amp; " HBR2";</div><div class='add'>+					*OutputType = (Output == dml2_dp) ? dml2_core_internal_output_type_dp : dml2_core_internal_output_type_edp;</div><div class='add'>+					*OutputRate = dml2_core_internal_output_rate_dp_rate_hbr2;</div><div class='add'>+				}</div><div class='add'>+				if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_hbr3) &amp;&amp; *OutBpp == 0 &amp;&amp; PHYCLK &gt;= 810) { // VBA_ERROR, vba code doesn't have hbr3 check</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 8100, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+						OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+						*RequiresDSC = true;</div><div class='add'>+						LinkDSCEnable = true;</div><div class='add'>+						if (Output == dml2_dp) {</div><div class='add'>+							*RequiresFEC = true;</div><div class='add'>+						}</div><div class='add'>+						*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, (1 - Downspreading / 100) * 8100, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='add'>+							OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='add'>+					}</div><div class='add'>+					//OutputTypeAndRate = Output &amp; " HBR3";</div><div class='add'>+					*OutputType = (Output == dml2_dp) ? dml2_core_internal_output_type_dp : dml2_core_internal_output_type_edp;</div><div class='add'>+					*OutputRate = dml2_core_internal_output_rate_dp_rate_hbr3;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else if (Output == dml2_hdmifrl) {</div><div class='add'>+			if (DSCEnable == dml2_dsc_enable) {</div><div class='add'>+				*RequiresDSC = true;</div><div class='add'>+				LinkDSCEnable = true;</div><div class='add'>+				*RequiresFEC = true;</div><div class='add'>+			} else {</div><div class='add'>+				*RequiresDSC = false;</div><div class='add'>+				LinkDSCEnable = false;</div><div class='add'>+				*RequiresFEC = false;</div><div class='add'>+			}</div><div class='add'>+			*OutBpp = 0;</div><div class='add'>+			if (PHYCLKD18 &gt;= 3000.0 / 18) {</div><div class='add'>+				*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 3000, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				//OutputTypeAndRate = Output &amp; "3x3";</div><div class='add'>+				*OutputType = dml2_core_internal_output_type_hdmifrl;</div><div class='add'>+				*OutputRate = dml2_core_internal_output_rate_hdmi_rate_3x3;</div><div class='add'>+			}</div><div class='add'>+			if (*OutBpp == 0 &amp;&amp; PHYCLKD18 &gt;= 6000.0 / 18) {</div><div class='add'>+				*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 6000, 3, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				//OutputTypeAndRate = Output &amp; "6x3";</div><div class='add'>+				*OutputType = dml2_core_internal_output_type_hdmifrl;</div><div class='add'>+				*OutputRate = dml2_core_internal_output_rate_hdmi_rate_6x3;</div><div class='add'>+			}</div><div class='add'>+			if (*OutBpp == 0 &amp;&amp; PHYCLKD18 &gt;= 6000.0 / 18) {</div><div class='add'>+				*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 6000, 4, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				//OutputTypeAndRate = Output &amp; "6x4";</div><div class='add'>+				*OutputType = dml2_core_internal_output_type_hdmifrl;</div><div class='add'>+				*OutputRate = dml2_core_internal_output_rate_hdmi_rate_6x4;</div><div class='add'>+			}</div><div class='add'>+			if (*OutBpp == 0 &amp;&amp; PHYCLKD18 &gt;= 8000.0 / 18) {</div><div class='add'>+				*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 8000, 4, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				//OutputTypeAndRate = Output &amp; "8x4";</div><div class='add'>+				*OutputType = dml2_core_internal_output_type_hdmifrl;</div><div class='add'>+				*OutputRate = dml2_core_internal_output_rate_hdmi_rate_8x4;</div><div class='add'>+			}</div><div class='add'>+			if (*OutBpp == 0 &amp;&amp; PHYCLKD18 &gt;= 10000.0 / 18) {</div><div class='add'>+				*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 10000, 4, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				if (*OutBpp == 0 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0 &amp;&amp; PHYCLKD18 &lt; 12000.0 / 18) {</div><div class='add'>+					*RequiresDSC = true;</div><div class='add'>+					LinkDSCEnable = true;</div><div class='add'>+					*RequiresFEC = true;</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 10000, 4, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				}</div><div class='add'>+				//OutputTypeAndRate = Output &amp; "10x4";</div><div class='add'>+				*OutputType = dml2_core_internal_output_type_hdmifrl;</div><div class='add'>+				*OutputRate = dml2_core_internal_output_rate_hdmi_rate_10x4;</div><div class='add'>+			}</div><div class='add'>+			if (*OutBpp == 0 &amp;&amp; PHYCLKD18 &gt;= 12000.0 / 18) {</div><div class='add'>+				*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 12000, 4, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				if (*OutBpp == 0 &amp;&amp; DSCEnable == dml2_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+					*RequiresDSC = true;</div><div class='add'>+					LinkDSCEnable = true;</div><div class='add'>+					*RequiresFEC = true;</div><div class='add'>+					*OutBpp = TruncToValidBPP(&amp;s-&gt;TruncToValidBPP_locals, 12000, 4, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output, OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (unsigned int)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, &amp;dummy);</div><div class='add'>+				}</div><div class='add'>+				//OutputTypeAndRate = Output &amp; "12x4";</div><div class='add'>+				*OutputType = dml2_core_internal_output_type_hdmifrl;</div><div class='add'>+				*OutputRate = dml2_core_internal_output_rate_hdmi_rate_12x4;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: RequiresDSC = %u\n", __func__, *RequiresDSC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: RequiresFEC = %u\n", __func__, *RequiresFEC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: OutBpp = %f\n", __func__, *OutBpp);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateWriteBackDISPCLK(</div><div class='add'>+	enum dml2_source_format_class WritebackPixelFormat,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	double WritebackHRatio,</div><div class='add'>+	double WritebackVRatio,</div><div class='add'>+	unsigned int WritebackHTaps,</div><div class='add'>+	unsigned int WritebackVTaps,</div><div class='add'>+	unsigned int WritebackSourceWidth,</div><div class='add'>+	unsigned int WritebackDestinationWidth,</div><div class='add'>+	unsigned int HTotal,</div><div class='add'>+	unsigned int WritebackLineBufferSize)</div><div class='add'>+{</div><div class='add'>+	double DISPCLK_H, DISPCLK_V, DISPCLK_HB;</div><div class='add'>+</div><div class='add'>+	DISPCLK_H = PixelClock * math_ceil2((double)WritebackHTaps / 8.0, 1) / WritebackHRatio;</div><div class='add'>+	DISPCLK_V = PixelClock * (WritebackVTaps * math_ceil2((double)WritebackDestinationWidth / 6.0, 1) + 8.0) / (double)HTotal;</div><div class='add'>+	DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / (double)WritebackSourceWidth;</div><div class='add'>+	return math_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double RequiredDTBCLK(</div><div class='add'>+	bool DSCEnable,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	enum dml2_output_format_class OutputFormat,</div><div class='add'>+	double OutputBpp,</div><div class='add'>+	unsigned int DSCSlices,</div><div class='add'>+	unsigned int HTotal,</div><div class='add'>+	unsigned int HActive,</div><div class='add'>+	unsigned int AudioRate,</div><div class='add'>+	unsigned int AudioLayout)</div><div class='add'>+{</div><div class='add'>+	if (DSCEnable != true) {</div><div class='add'>+		return math_max2(PixelClock / 4.0 * OutputBpp / 24.0, 25.0);</div><div class='add'>+	} else {</div><div class='add'>+		double PixelWordRate = PixelClock / (OutputFormat == dml2_444 ? 1 : 2);</div><div class='add'>+		double HCActive = math_ceil2(DSCSlices * math_ceil2(OutputBpp * math_ceil2(HActive / DSCSlices, 1) / 8.0, 1) / 3.0, 1);</div><div class='add'>+		double HCBlank = 64 + 32 * math_ceil2(AudioRate * (AudioLayout == 1 ? 1 : 0.25) * HTotal / (PixelClock * 1000), 1);</div><div class='add'>+		double AverageTribyteRate = PixelWordRate * (HCActive + HCBlank) / HTotal;</div><div class='add'>+		double HActiveTribyteRate = PixelWordRate * HCActive / HActive;</div><div class='add'>+		return math_max4(PixelWordRate / 4.0, AverageTribyteRate / 4.0, HActiveTribyteRate / 4.0, 25.0) * 1.002;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int DSCDelayRequirement(</div><div class='add'>+	bool DSCEnabled,</div><div class='add'>+	enum dml2_odm_mode ODMMode,</div><div class='add'>+	unsigned int DSCInputBitPerComponent,</div><div class='add'>+	double OutputBpp,</div><div class='add'>+	unsigned int HActive,</div><div class='add'>+	unsigned int HTotal,</div><div class='add'>+	unsigned int NumberOfDSCSlices,</div><div class='add'>+	enum dml2_output_format_class OutputFormat,</div><div class='add'>+	enum dml2_output_encoder_class Output,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	double PixelClockBackEnd)</div><div class='add'>+{</div><div class='add'>+	unsigned int DSCDelayRequirement_val = 0;</div><div class='add'>+	unsigned int NumberOfDSCSlicesFactor = 1;</div><div class='add'>+</div><div class='add'>+	if (DSCEnabled == true &amp;&amp; OutputBpp != 0) {</div><div class='add'>+</div><div class='add'>+		if (ODMMode == dml2_odm_mode_combine_4to1)</div><div class='add'>+			NumberOfDSCSlicesFactor = 4;</div><div class='add'>+		else if (ODMMode == dml2_odm_mode_combine_3to1)</div><div class='add'>+			NumberOfDSCSlicesFactor = 3;</div><div class='add'>+		else if (ODMMode == dml2_odm_mode_combine_2to1)</div><div class='add'>+			NumberOfDSCSlicesFactor = 2;</div><div class='add'>+</div><div class='add'>+		DSCDelayRequirement_val = NumberOfDSCSlicesFactor * (dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (unsigned int)(math_ceil2((double)HActive / (double)NumberOfDSCSlices, 1.0)),</div><div class='add'>+			(NumberOfDSCSlices / NumberOfDSCSlicesFactor), OutputFormat, Output) + dscComputeDelay(OutputFormat, Output));</div><div class='add'>+</div><div class='add'>+		DSCDelayRequirement_val = (unsigned int)(DSCDelayRequirement_val + (HTotal - HActive) * math_ceil2((double)DSCDelayRequirement_val / (double)HActive, 1.0));</div><div class='add'>+		DSCDelayRequirement_val = (unsigned int)(DSCDelayRequirement_val * PixelClock / PixelClockBackEnd);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		DSCDelayRequirement_val = 0;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSCEnabled= %u\n", __func__, DSCEnabled);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ODMMode = %u\n", __func__, ODMMode);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: OutputBpp = %f\n", __func__, OutputBpp);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HActive = %u\n", __func__, HActive);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HTotal = %u\n", __func__, HTotal);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelClock = %f\n", __func__, PixelClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelClockBackEnd = %f\n", __func__, PixelClockBackEnd);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: OutputFormat = %u\n", __func__, OutputFormat);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSCInputBitPerComponent = %u\n", __func__, DSCInputBitPerComponent);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfDSCSlices = %u\n", __func__, NumberOfDSCSlices);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSCDelayRequirement_val = %u\n", __func__, DSCDelayRequirement_val);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return DSCDelayRequirement_val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateSurfaceSizeInMall(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int MALLAllocatedForDCN,</div><div class='add'>+	unsigned int BytesPerPixelY[],</div><div class='add'>+	unsigned int BytesPerPixelC[],</div><div class='add'>+	unsigned int Read256BytesBlockWidthY[],</div><div class='add'>+	unsigned int Read256BytesBlockWidthC[],</div><div class='add'>+	unsigned int Read256BytesBlockHeightY[],</div><div class='add'>+	unsigned int Read256BytesBlockHeightC[],</div><div class='add'>+	unsigned int ReadBlockWidthY[],</div><div class='add'>+	unsigned int ReadBlockWidthC[],</div><div class='add'>+	unsigned int ReadBlockHeightY[],</div><div class='add'>+	unsigned int ReadBlockHeightC[],</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int SurfaceSizeInMALL[],</div><div class='add'>+	bool *ExceededMALLSize)</div><div class='add'>+{</div><div class='add'>+	unsigned int TotalSurfaceSizeInMALLForSS = 0;</div><div class='add'>+	unsigned int TotalSurfaceSizeInMALLForSubVP = 0;</div><div class='add'>+	unsigned int MALLAllocatedForDCNInBytes = MALLAllocatedForDCN * 1024 * 1024;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		const struct dml2_composition_cfg *composition = &amp;display_cfg-&gt;plane_descriptors[k].composition;</div><div class='add'>+		const struct dml2_surface_cfg *surface = &amp;display_cfg-&gt;plane_descriptors[k].surface;</div><div class='add'>+</div><div class='add'>+		if (composition-&gt;viewport.stationary) {</div><div class='add'>+			SurfaceSizeInMALL[k] = (unsigned int)(math_min2(math_ceil2((double)surface-&gt;plane0.width, ReadBlockWidthY[k]),</div><div class='add'>+				math_floor2(composition-&gt;viewport.plane0.x_start + composition-&gt;viewport.plane0.width + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) -</div><div class='add'>+				math_floor2((double)composition-&gt;viewport.plane0.x_start, ReadBlockWidthY[k])) *</div><div class='add'>+				math_min2(math_ceil2((double)surface-&gt;plane0.height, ReadBlockHeightY[k]),</div><div class='add'>+					math_floor2((double)composition-&gt;viewport.plane0.y_start + composition-&gt;viewport.plane0.height + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -</div><div class='add'>+					math_floor2((double)composition-&gt;viewport.plane0.y_start, ReadBlockHeightY[k])) * BytesPerPixelY[k]);</div><div class='add'>+</div><div class='add'>+			if (ReadBlockWidthC[k] &gt; 0) {</div><div class='add'>+				SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +</div><div class='add'>+					math_min2(math_ceil2((double)surface-&gt;plane1.width, ReadBlockWidthC[k]),</div><div class='add'>+						math_floor2((double)composition-&gt;viewport.plane1.y_start + composition-&gt;viewport.plane1.width + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -</div><div class='add'>+						math_floor2((double)composition-&gt;viewport.plane1.y_start, ReadBlockWidthC[k])) *</div><div class='add'>+					math_min2(math_ceil2((double)surface-&gt;plane1.height, ReadBlockHeightC[k]),</div><div class='add'>+						math_floor2((double)composition-&gt;viewport.plane1.y_start + composition-&gt;viewport.plane1.height + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -</div><div class='add'>+						math_floor2(composition-&gt;viewport.plane1.y_start, ReadBlockHeightC[k])) * BytesPerPixelC[k]);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			SurfaceSizeInMALL[k] = (unsigned int)(math_ceil2(math_min2(surface-&gt;plane0.width, composition-&gt;viewport.plane0.width + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *</div><div class='add'>+				math_ceil2(math_min2(surface-&gt;plane0.height, composition-&gt;viewport.plane0.height + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);</div><div class='add'>+			if (ReadBlockWidthC[k] &gt; 0) {</div><div class='add'>+				SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +</div><div class='add'>+					math_ceil2(math_min2(surface-&gt;plane1.width, composition-&gt;viewport.plane1.width + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *</div><div class='add'>+					math_ceil2(math_min2(surface-&gt;plane1.height, composition-&gt;viewport.plane1.height + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		/* SS and Subvp counted separate as they are never used at the same time */</div><div class='add'>+		if (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k]))</div><div class='add'>+			TotalSurfaceSizeInMALLForSubVP += SurfaceSizeInMALL[k];</div><div class='add'>+		else if (display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable)</div><div class='add'>+			TotalSurfaceSizeInMALLForSS += SurfaceSizeInMALL[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*ExceededMALLSize = (TotalSurfaceSizeInMALLForSS &gt; MALLAllocatedForDCNInBytes) ||</div><div class='add'>+		(TotalSurfaceSizeInMALLForSubVP &gt; MALLAllocatedForDCNInBytes);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MALLAllocatedForDCN = %u\n", __func__, MALLAllocatedForDCN * 1024 * 1024);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalSurfaceSizeInMALLForSubVP = %u\n", __func__, TotalSurfaceSizeInMALLForSubVP);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalSurfaceSizeInMALLForSS = %u\n", __func__, TotalSurfaceSizeInMALLForSS);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExceededMALLSize = %u\n", __func__, *ExceededMALLSize);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_tdlut_setting(</div><div class='add'>+		struct dml2_core_internal_scratch *scratch,</div><div class='add'>+		struct dml2_core_calcs_calculate_tdlut_setting_params *p)</div><div class='add'>+{</div><div class='add'>+	// locals</div><div class='add'>+	unsigned int tdlut_bpe = 8;</div><div class='add'>+	unsigned int tdlut_width;</div><div class='add'>+	unsigned int tdlut_pitch_bytes;</div><div class='add'>+	unsigned int tdlut_footprint_bytes;</div><div class='add'>+	unsigned int vmpg_bytes;</div><div class='add'>+	unsigned int tdlut_vmpg_per_frame;</div><div class='add'>+	unsigned int tdlut_pte_req_per_frame;</div><div class='add'>+	unsigned int tdlut_bytes_per_line;</div><div class='add'>+	double tdlut_drain_rate;</div><div class='add'>+	unsigned int tdlut_mpc_width;</div><div class='add'>+	unsigned int tdlut_bytes_per_group_simple;</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;setup_for_tdlut) {</div><div class='add'>+		*p-&gt;tdlut_groups_per_2row_ub = 0;</div><div class='add'>+		*p-&gt;tdlut_opt_time = 0;</div><div class='add'>+		*p-&gt;tdlut_drain_time = 0;</div><div class='add'>+		*p-&gt;tdlut_bytes_to_deliver = 0;</div><div class='add'>+		*p-&gt;tdlut_bytes_per_group = 0;</div><div class='add'>+		*p-&gt;tdlut_pte_bytes_per_frame = 0;</div><div class='add'>+		*p-&gt;tdlut_bytes_per_frame = 0;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;tdlut_mpc_width_flag) {</div><div class='add'>+		tdlut_mpc_width = 33;</div><div class='add'>+		tdlut_bytes_per_group_simple = 39*256;</div><div class='add'>+	} else {</div><div class='add'>+		tdlut_mpc_width = 17;</div><div class='add'>+		tdlut_bytes_per_group_simple = 10*256;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vmpg_bytes = p-&gt;gpuvm_page_size_kbytes * 1024;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;tdlut_addressing_mode == dml2_tdlut_simple_linear) {</div><div class='add'>+		if (p-&gt;tdlut_width_mode == dml2_tdlut_width_17_cube)</div><div class='add'>+			tdlut_width = 4916;</div><div class='add'>+		else</div><div class='add'>+			tdlut_width = 35940;</div><div class='add'>+	} else {</div><div class='add'>+		if (p-&gt;tdlut_width_mode == dml2_tdlut_width_17_cube)</div><div class='add'>+			tdlut_width = 17;</div><div class='add'>+		else // dml2_tdlut_width_33_cube</div><div class='add'>+			tdlut_width = 33;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;is_gfx11)</div><div class='add'>+		tdlut_pitch_bytes = (unsigned int)math_ceil2(tdlut_width * tdlut_bpe, 256); //256B alignment</div><div class='add'>+	else</div><div class='add'>+		tdlut_pitch_bytes = (unsigned int)math_ceil2(tdlut_width * tdlut_bpe, 128); //128B alignment</div><div class='add'>+</div><div class='add'>+	if (p-&gt;tdlut_addressing_mode == dml2_tdlut_sw_linear)</div><div class='add'>+		tdlut_footprint_bytes = tdlut_pitch_bytes * tdlut_width * tdlut_width;</div><div class='add'>+	else</div><div class='add'>+		tdlut_footprint_bytes = tdlut_pitch_bytes;</div><div class='add'>+</div><div class='add'>+	if (!p-&gt;gpuvm_enable) {</div><div class='add'>+		tdlut_vmpg_per_frame = 0;</div><div class='add'>+		tdlut_pte_req_per_frame = 0;</div><div class='add'>+	} else {</div><div class='add'>+		tdlut_vmpg_per_frame = (unsigned int)math_ceil2(tdlut_footprint_bytes - 1, vmpg_bytes) / vmpg_bytes + 1;</div><div class='add'>+		tdlut_pte_req_per_frame = (unsigned int)math_ceil2(tdlut_vmpg_per_frame - 1, 8) / 8 + 1;</div><div class='add'>+	}</div><div class='add'>+	tdlut_bytes_per_line = (unsigned int)math_ceil2(tdlut_width * tdlut_bpe, 64); //64b request</div><div class='add'>+	*p-&gt;tdlut_pte_bytes_per_frame = tdlut_pte_req_per_frame * 64;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;tdlut_addressing_mode == dml2_tdlut_sw_linear) {</div><div class='add'>+		//the tdlut_width is either 17 or 33 but the 33x33x33 is subsampled every other line/slice</div><div class='add'>+		*p-&gt;tdlut_bytes_per_frame = tdlut_bytes_per_line * tdlut_mpc_width * tdlut_mpc_width;</div><div class='add'>+		*p-&gt;tdlut_bytes_per_group = tdlut_bytes_per_line * tdlut_mpc_width;</div><div class='add'>+		//the delivery cycles is DispClk cycles per line * number of lines * number of slices</div><div class='add'>+		//tdlut_delivery_cycles = (unsigned int)math_ceil2(tdlut_mpc_width/2.0, 1) * tdlut_mpc_width * tdlut_mpc_width;</div><div class='add'>+		tdlut_drain_rate = tdlut_bytes_per_line * p-&gt;dispclk_mhz / math_ceil2(tdlut_mpc_width/2.0, 1);</div><div class='add'>+	} else {</div><div class='add'>+		//tdlut_addressing_mode = tdlut_simple_linear, 3dlut width should be 4*1229=4916 elements</div><div class='add'>+		*p-&gt;tdlut_bytes_per_frame = (unsigned int)math_ceil2(tdlut_width * tdlut_bpe, 256);</div><div class='add'>+		*p-&gt;tdlut_bytes_per_group = tdlut_bytes_per_group_simple;</div><div class='add'>+		//tdlut_delivery_cycles = (unsigned int)math_ceil2(tdlut_width/2.0, 1);</div><div class='add'>+		tdlut_drain_rate = 2 * tdlut_bpe * p-&gt;dispclk_mhz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//the tdlut is fetched during the 2 row times of prefetch.</div><div class='add'>+	if (p-&gt;setup_for_tdlut) {</div><div class='add'>+		*p-&gt;tdlut_groups_per_2row_ub = (unsigned int)math_ceil2((double) *p-&gt;tdlut_bytes_per_frame / *p-&gt;tdlut_bytes_per_group, 1);</div><div class='add'>+		if (*p-&gt;tdlut_bytes_per_frame &gt; p-&gt;cursor_buffer_size * 1024)</div><div class='add'>+			*p-&gt;tdlut_opt_time = (*p-&gt;tdlut_bytes_per_frame - p-&gt;cursor_buffer_size * 1024) / tdlut_drain_rate;</div><div class='add'>+		else</div><div class='add'>+			*p-&gt;tdlut_opt_time = 0;</div><div class='add'>+		*p-&gt;tdlut_drain_time = p-&gt;cursor_buffer_size * 1024 / tdlut_drain_rate;</div><div class='add'>+		*p-&gt;tdlut_bytes_to_deliver = (unsigned int) (p-&gt;cursor_buffer_size * 1024.0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: gpuvm_enable = %d\n", __func__, p-&gt;gpuvm_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vmpg_bytes = %d\n", __func__, vmpg_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_vmpg_per_frame = %d\n", __func__, tdlut_vmpg_per_frame);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_pte_req_per_frame = %d\n", __func__, tdlut_pte_req_per_frame);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dispclk_mhz = %f\n", __func__, p-&gt;dispclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_width = %u\n", __func__, tdlut_width);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_addressing_mode = %s\n", __func__, (p-&gt;tdlut_addressing_mode == dml2_tdlut_sw_linear) ? "sw_linear" : "simple_linear");</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_pitch_bytes = %u\n", __func__, tdlut_pitch_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_footprint_bytes = %u\n", __func__, tdlut_footprint_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_bytes_per_frame = %u\n", __func__, *p-&gt;tdlut_bytes_per_frame);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_bytes_per_line = %u\n", __func__, tdlut_bytes_per_line);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_bytes_per_group = %u\n", __func__, *p-&gt;tdlut_bytes_per_group);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_drain_rate = %f\n", __func__, tdlut_drain_rate);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_delivery_cycles = %u\n", __func__, p-&gt;tdlut_addressing_mode == dml2_tdlut_sw_linear ? (unsigned int)math_ceil2(tdlut_mpc_width/2.0, 1) * tdlut_mpc_width * tdlut_mpc_width : (unsigned int)math_ceil2(tdlut_width/2.0, 1));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_opt_time = %f\n", __func__, *p-&gt;tdlut_opt_time);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_drain_time = %f\n", __func__, *p-&gt;tdlut_drain_time);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_bytes_to_deliver = %d\n", __func__, *p-&gt;tdlut_bytes_to_deliver);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_groups_per_2row_ub = %d\n", __func__, *p-&gt;tdlut_groups_per_2row_ub);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateTarb(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int PixelChunkSizeInKByte,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int NumberOfDPP[],</div><div class='add'>+	unsigned int dpte_group_bytes[],</div><div class='add'>+	unsigned int tdlut_bytes_per_group[],</div><div class='add'>+	double HostVMInefficiencyFactor,</div><div class='add'>+	double HostVMInefficiencyFactorPrefetch,</div><div class='add'>+	unsigned int HostVMMinPageSize,</div><div class='add'>+	double ReturnBW,</div><div class='add'>+	unsigned int MetaChunkSize,</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	double *Tarb,</div><div class='add'>+	double *Tarb_prefetch)</div><div class='add'>+{</div><div class='add'>+	double extra_bytes = 0;</div><div class='add'>+	double extra_bytes_prefetch = 0;</div><div class='add'>+	double HostVMDynamicLevels = CalculateHostVMDynamicLevels(display_cfg-&gt;gpuvm_enable, display_cfg-&gt;hostvm_enable, HostVMMinPageSize, display_cfg-&gt;hostvm_max_non_cached_page_table_levels);</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		extra_bytes = extra_bytes + (NumberOfDPP[k] * PixelChunkSizeInKByte * 1024);</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].surface.dcc.enable)</div><div class='add'>+			extra_bytes = extra_bytes + (MetaChunkSize * 1024);</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut)</div><div class='add'>+			extra_bytes = extra_bytes + tdlut_bytes_per_group[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	extra_bytes_prefetch = extra_bytes;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+			extra_bytes = extra_bytes + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;</div><div class='add'>+			extra_bytes_prefetch = extra_bytes_prefetch + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactorPrefetch;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	*Tarb = extra_bytes / ReturnBW;</div><div class='add'>+	*Tarb_prefetch = extra_bytes_prefetch / ReturnBW;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelChunkSizeInKByte = %d\n", __func__, PixelChunkSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MetaChunkSize = %d\n", __func__, MetaChunkSize);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: extra_bytes = %f\n", __func__, extra_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: extra_bytes_prefetch = %f\n", __func__, extra_bytes_prefetch);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double CalculateTWait(</div><div class='add'>+	long reserved_vblank_time_ns,</div><div class='add'>+	double UrgentLatency,</div><div class='add'>+	double Ttrip,</div><div class='add'>+	double g6_temp_read_blackout_us)</div><div class='add'>+{</div><div class='add'>+	double TWait;</div><div class='add'>+	double t_urg_trip = math_max2(UrgentLatency, Ttrip);</div><div class='add'>+	TWait = math_max2(reserved_vblank_time_ns/1000.0, g6_temp_read_blackout_us) + t_urg_trip;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: reserved_vblank_time_ns = %ld\n", __func__, reserved_vblank_time_ns);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Ttrip = %f\n", __func__, Ttrip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait = %f\n", __func__, TWait);</div><div class='add'>+#endif</div><div class='add'>+	return TWait;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void CalculateVUpdateAndDynamicMetadataParameters(</div><div class='add'>+	unsigned int MaxInterDCNTileRepeaters,</div><div class='add'>+	double Dppclk,</div><div class='add'>+	double Dispclk,</div><div class='add'>+	double DCFClkDeepSleep,</div><div class='add'>+	double PixelClock,</div><div class='add'>+	unsigned int HTotal,</div><div class='add'>+	unsigned int VBlank,</div><div class='add'>+	unsigned int DynamicMetadataTransmittedBytes,</div><div class='add'>+	unsigned int DynamicMetadataLinesBeforeActiveRequired,</div><div class='add'>+	unsigned int InterlaceEnable,</div><div class='add'>+	bool ProgressiveToInterlaceUnitInOPP,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *TSetup,</div><div class='add'>+	double *Tdmbf,</div><div class='add'>+	double *Tdmec,</div><div class='add'>+	double *Tdmsks,</div><div class='add'>+	unsigned int *VUpdateOffsetPix,</div><div class='add'>+	unsigned int *VUpdateWidthPix,</div><div class='add'>+	unsigned int *VReadyOffsetPix)</div><div class='add'>+{</div><div class='add'>+	double TotalRepeaterDelayTime;</div><div class='add'>+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / Dppclk + 3 / Dispclk);</div><div class='add'>+	*VUpdateWidthPix = (unsigned int)(math_ceil2((14.0 / DCFClkDeepSleep + 12.0 / Dppclk + TotalRepeaterDelayTime) * PixelClock, 1.0));</div><div class='add'>+	*VReadyOffsetPix = (unsigned int)(math_ceil2(math_max2(150.0 / Dppclk, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / Dppclk) * PixelClock, 1.0));</div><div class='add'>+	*VUpdateOffsetPix = (unsigned int)(math_ceil2(HTotal / 4.0, 1.0));</div><div class='add'>+	*TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;</div><div class='add'>+	*Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / Dispclk;</div><div class='add'>+	*Tdmec = HTotal / PixelClock;</div><div class='add'>+</div><div class='add'>+	if (DynamicMetadataLinesBeforeActiveRequired == 0) {</div><div class='add'>+		*Tdmsks = VBlank * HTotal / PixelClock / 2.0;</div><div class='add'>+	} else {</div><div class='add'>+		*Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock;</div><div class='add'>+	}</div><div class='add'>+	if (InterlaceEnable == 1 &amp;&amp; ProgressiveToInterlaceUnitInOPP == false) {</div><div class='add'>+		*Tdmsks = *Tdmsks / 2;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DynamicMetadataLinesBeforeActiveRequired = %u\n", __func__, DynamicMetadataLinesBeforeActiveRequired);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VBlank = %u\n", __func__, VBlank);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HTotal = %u\n", __func__, HTotal);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelClock = %f\n", __func__, PixelClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Dppclk = %f\n", __func__, Dppclk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFClkDeepSleep = %f\n", __func__, DCFClkDeepSleep);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxInterDCNTileRepeaters = %u\n", __func__, MaxInterDCNTileRepeaters);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalRepeaterDelayTime = %f\n", __func__, TotalRepeaterDelayTime);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VUpdateWidthPix = %u\n", __func__, *VUpdateWidthPix);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VReadyOffsetPix = %u\n", __func__, *VReadyOffsetPix);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VUpdateOffsetPix = %u\n", __func__, *VUpdateOffsetPix);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tdmsks = %f\n", __func__, *Tdmsks);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double get_urgent_bandwidth_required(</div><div class='add'>+	struct dml2_core_shared_get_urgent_bandwidth_required_locals *l,</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	enum dml2_core_internal_soc_state_type state_type,</div><div class='add'>+	enum dml2_core_internal_bw_type bw_type,</div><div class='add'>+	bool inc_flip_bw, // including flip bw</div><div class='add'>+	bool use_qual_row_bw,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int NumberOfDPP[],</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p0[],</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p1[],</div><div class='add'>+	double dcc_dram_bw_pref_overhead_factor_p0[],</div><div class='add'>+	double dcc_dram_bw_pref_overhead_factor_p1[],</div><div class='add'>+	double mall_prefetch_sdp_overhead_factor[],</div><div class='add'>+	double mall_prefetch_dram_overhead_factor[],</div><div class='add'>+	double ReadBandwidthLuma[],</div><div class='add'>+	double ReadBandwidthChroma[],</div><div class='add'>+	double PrefetchBandwidthLuma[],</div><div class='add'>+	double PrefetchBandwidthChroma[],</div><div class='add'>+	double PrefetchBandwidthMax[],</div><div class='add'>+	double excess_vactive_fill_bw_l[],</div><div class='add'>+	double excess_vactive_fill_bw_c[],</div><div class='add'>+	double cursor_bw[],</div><div class='add'>+	double dpte_row_bw[],</div><div class='add'>+	double meta_row_bw[],</div><div class='add'>+	double prefetch_cursor_bw[],</div><div class='add'>+	double prefetch_vmrow_bw[],</div><div class='add'>+	double flip_bw[],</div><div class='add'>+	double UrgentBurstFactorLuma[],</div><div class='add'>+	double UrgentBurstFactorChroma[],</div><div class='add'>+	double UrgentBurstFactorCursor[],</div><div class='add'>+	double UrgentBurstFactorLumaPre[],</div><div class='add'>+	double UrgentBurstFactorChromaPre[],</div><div class='add'>+	double UrgentBurstFactorCursorPre[],</div><div class='add'>+	/* outputs */</div><div class='add'>+	double surface_required_bw[],</div><div class='add'>+	double surface_peak_required_bw[])</div><div class='add'>+{</div><div class='add'>+	// set inc_flip_bw = 0 for total_dchub_urgent_read_bw_noflip calculation, 1 for total_dchub_urgent_read_bw as described in the MAS</div><div class='add'>+	// set use_qual_row_bw = 1 to calculate using qualified row bandwidth, used for total_flip_bw calculation</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_core_shared_get_urgent_bandwidth_required_locals));</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		l-&gt;mall_svp_prefetch_factor = (state_type == dml2_core_internal_soc_state_svp_prefetch) ? (bw_type == dml2_core_internal_bw_dram ? mall_prefetch_dram_overhead_factor[k] : mall_prefetch_sdp_overhead_factor[k]) : 1.0;</div><div class='add'>+		l-&gt;tmp_nom_adj_factor_p0 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p0[k] : 1.0) * l-&gt;mall_svp_prefetch_factor;</div><div class='add'>+		l-&gt;tmp_nom_adj_factor_p1 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p1[k] : 1.0) * l-&gt;mall_svp_prefetch_factor;</div><div class='add'>+		l-&gt;tmp_pref_adj_factor_p0 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_pref_overhead_factor_p0[k] : 1.0) * l-&gt;mall_svp_prefetch_factor;</div><div class='add'>+		l-&gt;tmp_pref_adj_factor_p1 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_pref_overhead_factor_p1[k] : 1.0) * l-&gt;mall_svp_prefetch_factor;</div><div class='add'>+</div><div class='add'>+		l-&gt;adj_factor_p0 = UrgentBurstFactorLuma[k] * l-&gt;tmp_nom_adj_factor_p0;</div><div class='add'>+		l-&gt;adj_factor_p1 = UrgentBurstFactorChroma[k] * l-&gt;tmp_nom_adj_factor_p1;</div><div class='add'>+		l-&gt;adj_factor_cur = UrgentBurstFactorCursor[k];</div><div class='add'>+		l-&gt;adj_factor_p0_pre = UrgentBurstFactorLumaPre[k] * l-&gt;tmp_pref_adj_factor_p0;</div><div class='add'>+		l-&gt;adj_factor_p1_pre = UrgentBurstFactorChromaPre[k] * l-&gt;tmp_pref_adj_factor_p1;</div><div class='add'>+		l-&gt;adj_factor_cur_pre = UrgentBurstFactorCursorPre[k];</div><div class='add'>+</div><div class='add'>+		bool is_phantom = dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k]);</div><div class='add'>+		bool exclude_this_plane = false;</div><div class='add'>+</div><div class='add'>+		// Exclude phantom pipe in bw calculation for non svp prefetch state</div><div class='add'>+		if (state_type != dml2_core_internal_soc_state_svp_prefetch &amp;&amp; is_phantom)</div><div class='add'>+			exclude_this_plane = true;</div><div class='add'>+</div><div class='add'>+		// The qualified row bandwidth, qual_row_bw, accounts for the regular non-flip row bandwidth when there is no possible immediate flip or HostVM invalidation flip.</div><div class='add'>+		// The qual_row_bw is zero if HostVM is possible and only non-zero and equal to row_bw(i) if immediate flip is not allowed for that pipe.</div><div class='add'>+		if (use_qual_row_bw) {</div><div class='add'>+			if (display_cfg-&gt;hostvm_enable)</div><div class='add'>+				l-&gt;per_plane_flip_bw[k] = 0; // qual_row_bw</div><div class='add'>+			else if (!display_cfg-&gt;plane_descriptors[k].immediate_flip)</div><div class='add'>+				l-&gt;per_plane_flip_bw[k] = NumberOfDPP[k] * (dpte_row_bw[k] + meta_row_bw[k]);</div><div class='add'>+		} else {</div><div class='add'>+			// the final_flip_bw includes the regular row_bw when immediate flip is disallowed (and no HostVM)</div><div class='add'>+			if ((!display_cfg-&gt;plane_descriptors[k].immediate_flip &amp;&amp; !display_cfg-&gt;hostvm_enable) || !inc_flip_bw)</div><div class='add'>+				l-&gt;per_plane_flip_bw[k] = NumberOfDPP[k] * (dpte_row_bw[k] + meta_row_bw[k]);</div><div class='add'>+			else</div><div class='add'>+				l-&gt;per_plane_flip_bw[k] = NumberOfDPP[k] * flip_bw[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!exclude_this_plane) {</div><div class='add'>+			l-&gt;vm_row_bw = NumberOfDPP[k] * prefetch_vmrow_bw[k];</div><div class='add'>+			l-&gt;flip_and_active_bw = l-&gt;per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l-&gt;adj_factor_p0 + ReadBandwidthChroma[k] * l-&gt;adj_factor_p1 + cursor_bw[k] * l-&gt;adj_factor_cur;</div><div class='add'>+			l-&gt;flip_and_prefetch_bw = l-&gt;per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l-&gt;adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l-&gt;adj_factor_p1_pre) + prefetch_cursor_bw[k] * l-&gt;adj_factor_cur_pre;</div><div class='add'>+			l-&gt;flip_and_prefetch_bw_max = l-&gt;per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthMax[k] * l-&gt;adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l-&gt;adj_factor_p1_pre) + prefetch_cursor_bw[k] * l-&gt;adj_factor_cur_pre;</div><div class='add'>+			l-&gt;active_and_excess_bw = (ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l-&gt;tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l-&gt;tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k];</div><div class='add'>+			surface_required_bw[k] = math_max5(l-&gt;vm_row_bw, l-&gt;flip_and_active_bw, l-&gt;flip_and_prefetch_bw, l-&gt;active_and_excess_bw, l-&gt;flip_and_prefetch_bw_max);</div><div class='add'>+</div><div class='add'>+			/* export peak required bandwidth for the surface */</div><div class='add'>+			surface_peak_required_bw[k] = math_max2(surface_required_bw[k], surface_peak_required_bw[k]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, max1: vm_row_bw=%f\n", __func__, k, l-&gt;vm_row_bw);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, max2: flip_and_active_bw=%f\n", __func__, k, l-&gt;flip_and_active_bw);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, max3: flip_and_prefetch_bw=%f\n", __func__, k, l-&gt;flip_and_prefetch_bw);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, max4: active_and_excess_bw=%f\n", __func__, k, l-&gt;active_and_excess_bw);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, surface_required_bw=%f\n", __func__, k, surface_required_bw[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, surface_peak_required_bw=%f\n", __func__, k, surface_peak_required_bw[k]);</div><div class='add'>+#endif</div><div class='add'>+		} else {</div><div class='add'>+			surface_required_bw[k] = 0.0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		l-&gt;required_bandwidth_mbps += surface_required_bw[k];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, NumberOfDPP=%d\n", __func__, k, NumberOfDPP[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, use_qual_row_bw=%d\n", __func__, k, use_qual_row_bw);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, immediate_flip=%d\n", __func__, k, display_cfg-&gt;plane_descriptors[k].immediate_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, mall_svp_prefetch_factor=%f\n", __func__, k, l-&gt;mall_svp_prefetch_factor);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p0=%f\n", __func__, k, l-&gt;adj_factor_p0);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p1=%f\n", __func__, k, l-&gt;adj_factor_p1);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_cur=%f\n", __func__, k, l-&gt;adj_factor_cur);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p0_pre=%f\n", __func__, k, l-&gt;adj_factor_p0_pre);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p1_pre=%f\n", __func__, k, l-&gt;adj_factor_p1_pre);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_cur_pre=%f\n", __func__, k, l-&gt;adj_factor_cur_pre);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, per_plane_flip_bw=%f\n", __func__, k, l-&gt;per_plane_flip_bw[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_vmrow_bw=%f\n", __func__, k, prefetch_vmrow_bw[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, ReadBandwidthLuma=%f\n", __func__, k, ReadBandwidthLuma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, ReadBandwidthChroma=%f\n", __func__, k, ReadBandwidthChroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, excess_vactive_fill_bw_l=%f\n", __func__, k, excess_vactive_fill_bw_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, excess_vactive_fill_bw_c=%f\n", __func__, k, excess_vactive_fill_bw_c[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, cursor_bw=%f\n", __func__, k, cursor_bw[k]);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, meta_row_bw=%f\n", __func__, k, meta_row_bw[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, dpte_row_bw=%f\n", __func__, k, dpte_row_bw[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, PrefetchBandwidthLuma=%f\n", __func__, k, PrefetchBandwidthLuma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, PrefetchBandwidthChroma=%f\n", __func__, k, PrefetchBandwidthChroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_cursor_bw=%f\n", __func__, k, prefetch_cursor_bw[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l-&gt;required_bandwidth_mbps, inc_flip_bw, is_phantom, exclude_this_plane);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), soc_state=%s, inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l-&gt;required_bandwidth_mbps, dml2_core_internal_soc_state_type_str(state_type), inc_flip_bw, is_phantom, exclude_this_plane);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l-&gt;required_bandwidth_mbps, inc_flip_bw, is_phantom, exclude_this_plane);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return l-&gt;required_bandwidth_mbps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateExtraLatency(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int ROBBufferSizeInKByte,</div><div class='add'>+	unsigned int RoundTripPingLatencyCycles,</div><div class='add'>+	unsigned int ReorderingBytes,</div><div class='add'>+	double DCFCLK,</div><div class='add'>+	double FabricClock,</div><div class='add'>+	unsigned int PixelChunkSizeInKByte,</div><div class='add'>+	double ReturnBW,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int NumberOfDPP[],</div><div class='add'>+	unsigned int dpte_group_bytes[],</div><div class='add'>+	unsigned int tdlut_bytes_per_group[],</div><div class='add'>+	double HostVMInefficiencyFactor,</div><div class='add'>+	double HostVMInefficiencyFactorPrefetch,</div><div class='add'>+	unsigned int HostVMMinPageSize,</div><div class='add'>+	enum dml2_qos_param_type qos_type,</div><div class='add'>+	bool max_outstanding_when_urgent_expected,</div><div class='add'>+	unsigned int max_outstanding_requests,</div><div class='add'>+	unsigned int request_size_bytes_luma[],</div><div class='add'>+	unsigned int request_size_bytes_chroma[],</div><div class='add'>+	unsigned int MetaChunkSize,</div><div class='add'>+	unsigned int dchub_arb_to_ret_delay,</div><div class='add'>+	double Ttrip,</div><div class='add'>+	unsigned int hostvm_mode,</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	double *ExtraLatency, // Tex</div><div class='add'>+	double *ExtraLatency_sr, // Tex_sr</div><div class='add'>+	double *ExtraLatencyPrefetch)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	double Tarb;</div><div class='add'>+	double Tarb_prefetch;</div><div class='add'>+	double Tex_trips;</div><div class='add'>+	unsigned int max_request_size_bytes = 0;</div><div class='add'>+</div><div class='add'>+	CalculateTarb(</div><div class='add'>+		display_cfg,</div><div class='add'>+		PixelChunkSizeInKByte,</div><div class='add'>+		NumberOfActiveSurfaces,</div><div class='add'>+		NumberOfDPP,</div><div class='add'>+		dpte_group_bytes,</div><div class='add'>+		tdlut_bytes_per_group,</div><div class='add'>+		HostVMInefficiencyFactor,</div><div class='add'>+		HostVMInefficiencyFactorPrefetch,</div><div class='add'>+		HostVMMinPageSize,</div><div class='add'>+		ReturnBW,</div><div class='add'>+		MetaChunkSize,</div><div class='add'>+		// output</div><div class='add'>+		&amp;Tarb,</div><div class='add'>+		&amp;Tarb_prefetch);</div><div class='add'>+</div><div class='add'>+	Tex_trips = (display_cfg-&gt;hostvm_enable &amp;&amp; hostvm_mode == 1) ? (2.0 * Ttrip) : 0.0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (request_size_bytes_luma[k] &gt; max_request_size_bytes)</div><div class='add'>+			max_request_size_bytes = request_size_bytes_luma[k];</div><div class='add'>+		if (request_size_bytes_chroma[k] &gt; max_request_size_bytes)</div><div class='add'>+			max_request_size_bytes = request_size_bytes_chroma[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		*ExtraLatency_sr = dchub_arb_to_ret_delay / DCFCLK;</div><div class='add'>+		*ExtraLatency = *ExtraLatency_sr;</div><div class='add'>+		if (max_outstanding_when_urgent_expected)</div><div class='add'>+			*ExtraLatency = *ExtraLatency + (ROBBufferSizeInKByte * 1024 - max_outstanding_requests * max_request_size_bytes) / ReturnBW;</div><div class='add'>+	} else {</div><div class='add'>+		*ExtraLatency_sr = dchub_arb_to_ret_delay / DCFCLK + RoundTripPingLatencyCycles / FabricClock + ReorderingBytes / ReturnBW;</div><div class='add'>+		*ExtraLatency = *ExtraLatency_sr;</div><div class='add'>+	}</div><div class='add'>+	*ExtraLatency = *ExtraLatency + Tex_trips;</div><div class='add'>+	*ExtraLatencyPrefetch = *ExtraLatency + Tarb_prefetch;</div><div class='add'>+	*ExtraLatency = *ExtraLatency + Tarb;</div><div class='add'>+	*ExtraLatency_sr = *ExtraLatency_sr + Tarb;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: qos_type=%u\n", __func__, qos_type);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: hostvm_mode=%u\n", __func__, hostvm_mode);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tex_trips=%f\n", __func__, Tex_trips);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_outstanding_when_urgent_expected=%u\n", __func__, max_outstanding_when_urgent_expected);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FabricClock=%f\n", __func__, FabricClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFCLK=%f\n", __func__, DCFCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ReturnBW=%f\n", __func__, ReturnBW);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: RoundTripPingLatencyCycles=%u\n", __func__, RoundTripPingLatencyCycles);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ReorderingBytes=%u\n", __func__, ReorderingBytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tarb=%f\n", __func__, Tarb);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExtraLatency=%f\n", __func__, *ExtraLatency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExtraLatency_sr=%f\n", __func__, *ExtraLatency_sr);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExtraLatencyPrefetch=%f\n", __func__, *ExtraLatencyPrefetch);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch, struct dml2_core_calcs_CalculatePrefetchSchedule_params *p)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_calcs_CalculatePrefetchSchedule_locals *s = &amp;scratch-&gt;CalculatePrefetchSchedule_locals;</div><div class='add'>+	bool dcc_mrq_enable;</div><div class='add'>+</div><div class='add'>+	unsigned int vm_bytes;</div><div class='add'>+	unsigned int extra_tdpe_bytes;</div><div class='add'>+	unsigned int tdlut_row_bytes;</div><div class='add'>+	unsigned int Lo;</div><div class='add'>+</div><div class='add'>+	s-&gt;NoTimeToPrefetch = false;</div><div class='add'>+	s-&gt;DPPCycles = 0;</div><div class='add'>+	s-&gt;DISPCLKCycles = 0;</div><div class='add'>+	s-&gt;DSTTotalPixelsAfterScaler = 0.0;</div><div class='add'>+	s-&gt;LineTime = 0.0;</div><div class='add'>+	s-&gt;dst_y_prefetch_equ = 0.0;</div><div class='add'>+	s-&gt;prefetch_bw_oto = 0.0;</div><div class='add'>+	s-&gt;Tvm_oto = 0.0;</div><div class='add'>+	s-&gt;Tr0_oto = 0.0;</div><div class='add'>+	s-&gt;Tvm_oto_lines = 0.0;</div><div class='add'>+	s-&gt;Tr0_oto_lines = 0.0;</div><div class='add'>+	s-&gt;dst_y_prefetch_oto = 0.0;</div><div class='add'>+	s-&gt;TimeForFetchingVM = 0.0;</div><div class='add'>+	s-&gt;TimeForFetchingRowInVBlank = 0.0;</div><div class='add'>+	s-&gt;LinesToRequestPrefetchPixelData = 0.0;</div><div class='add'>+	s-&gt;HostVMDynamicLevelsTrips = 0;</div><div class='add'>+	s-&gt;trip_to_mem = 0.0;</div><div class='add'>+	*p-&gt;Tvm_trips = 0.0;</div><div class='add'>+	*p-&gt;Tr0_trips = 0.0;</div><div class='add'>+	s-&gt;Tvm_trips_rounded = 0.0;</div><div class='add'>+	s-&gt;Tr0_trips_rounded = 0.0;</div><div class='add'>+	s-&gt;max_Tsw = 0.0;</div><div class='add'>+	s-&gt;Lsw_oto = 0.0;</div><div class='add'>+	*p-&gt;Tpre_rounded = 0.0;</div><div class='add'>+	s-&gt;prefetch_bw_equ = 0.0;</div><div class='add'>+	s-&gt;Tvm_equ = 0.0;</div><div class='add'>+	s-&gt;Tr0_equ = 0.0;</div><div class='add'>+	s-&gt;Tdmbf = 0.0;</div><div class='add'>+	s-&gt;Tdmec = 0.0;</div><div class='add'>+	s-&gt;Tdmsks = 0.0;</div><div class='add'>+	*p-&gt;prefetch_sw_bytes = 0.0;</div><div class='add'>+	s-&gt;prefetch_bw_pr = 0.0;</div><div class='add'>+	s-&gt;bytes_pp = 0.0;</div><div class='add'>+	s-&gt;dep_bytes = 0.0;</div><div class='add'>+	s-&gt;min_Lsw_oto = 0.0;</div><div class='add'>+	s-&gt;min_Lsw_equ = 0.0;</div><div class='add'>+	s-&gt;Tsw_est1 = 0.0;</div><div class='add'>+	s-&gt;Tsw_est2 = 0.0;</div><div class='add'>+	s-&gt;Tsw_est3 = 0.0;</div><div class='add'>+	s-&gt;cursor_prefetch_bytes = 0;</div><div class='add'>+	*p-&gt;prefetch_cursor_bw = 0;</div><div class='add'>+	*p-&gt;RequiredPrefetchBWMax = 0.0;</div><div class='add'>+</div><div class='add'>+	dcc_mrq_enable = (p-&gt;dcc_enable &amp;&amp; p-&gt;mrq_present);</div><div class='add'>+</div><div class='add'>+	s-&gt;TWait_p = p-&gt;TWait - p-&gt;Ttrip; // TWait includes max(Turg, Ttrip) and Ttrip here is already max(Turg, Ttrip)</div><div class='add'>+</div><div class='add'>+	if (p-&gt;display_cfg-&gt;gpuvm_enable == true &amp;&amp; p-&gt;display_cfg-&gt;hostvm_enable == true) {</div><div class='add'>+		s-&gt;HostVMDynamicLevelsTrips = p-&gt;display_cfg-&gt;hostvm_max_non_cached_page_table_levels;</div><div class='add'>+	} else {</div><div class='add'>+		s-&gt;HostVMDynamicLevelsTrips = 0;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dcc_enable = %u\n", __func__, p-&gt;dcc_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mrq_present = %u\n", __func__, p-&gt;mrq_present);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dcc_mrq_enable = %u\n", __func__, dcc_mrq_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMEnable = %u\n", __func__, p-&gt;display_cfg-&gt;gpuvm_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMPageTableLevels = %u\n", __func__, p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p-&gt;myPipe-&gt;DCCEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VStartup = %u\n", __func__, p-&gt;VStartup);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HostVMEnable = %u\n", __func__, p-&gt;display_cfg-&gt;hostvm_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, p-&gt;HostVMInefficiencyFactor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait = %f\n", __func__, p-&gt;TWait);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait_p = %f\n", __func__, s-&gt;TWait_p);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Ttrip = %f\n", __func__, p-&gt;Ttrip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: myPipe-&gt;Dppclk = %f\n", __func__, p-&gt;myPipe-&gt;Dppclk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: myPipe-&gt;Dispclk = %f\n", __func__, p-&gt;myPipe-&gt;Dispclk);</div><div class='add'>+#endif</div><div class='add'>+	CalculateVUpdateAndDynamicMetadataParameters(</div><div class='add'>+		p-&gt;MaxInterDCNTileRepeaters,</div><div class='add'>+		p-&gt;myPipe-&gt;Dppclk,</div><div class='add'>+		p-&gt;myPipe-&gt;Dispclk,</div><div class='add'>+		p-&gt;myPipe-&gt;DCFClkDeepSleep,</div><div class='add'>+		p-&gt;myPipe-&gt;PixelClock,</div><div class='add'>+		p-&gt;myPipe-&gt;HTotal,</div><div class='add'>+		p-&gt;myPipe-&gt;VBlank,</div><div class='add'>+		p-&gt;DynamicMetadataTransmittedBytes,</div><div class='add'>+		p-&gt;DynamicMetadataLinesBeforeActiveRequired,</div><div class='add'>+		p-&gt;myPipe-&gt;InterlaceEnable,</div><div class='add'>+		p-&gt;myPipe-&gt;ProgressiveToInterlaceUnitInOPP,</div><div class='add'>+		p-&gt;TSetup,</div><div class='add'>+</div><div class='add'>+		// Output</div><div class='add'>+		&amp;s-&gt;Tdmbf,</div><div class='add'>+		&amp;s-&gt;Tdmec,</div><div class='add'>+		&amp;s-&gt;Tdmsks,</div><div class='add'>+		p-&gt;VUpdateOffsetPix,</div><div class='add'>+		p-&gt;VUpdateWidthPix,</div><div class='add'>+		p-&gt;VReadyOffsetPix);</div><div class='add'>+</div><div class='add'>+	s-&gt;LineTime = p-&gt;myPipe-&gt;HTotal / p-&gt;myPipe-&gt;PixelClock;</div><div class='add'>+	s-&gt;trip_to_mem = p-&gt;Ttrip;</div><div class='add'>+	*p-&gt;Tvm_trips = p-&gt;ExtraLatencyPrefetch + math_max2(s-&gt;trip_to_mem * (p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels * (s-&gt;HostVMDynamicLevelsTrips + 1)), p-&gt;Turg);</div><div class='add'>+	if (dcc_mrq_enable)</div><div class='add'>+		*p-&gt;Tvm_trips_flip = *p-&gt;Tvm_trips;</div><div class='add'>+	else</div><div class='add'>+		*p-&gt;Tvm_trips_flip = *p-&gt;Tvm_trips - s-&gt;trip_to_mem;</div><div class='add'>+</div><div class='add'>+	*p-&gt;Tr0_trips_flip = s-&gt;trip_to_mem * (s-&gt;HostVMDynamicLevelsTrips + 1);</div><div class='add'>+	*p-&gt;Tr0_trips = math_max2(*p-&gt;Tr0_trips_flip, p-&gt;tdlut_opt_time / 2);</div><div class='add'>+</div><div class='add'>+	if (p-&gt;DynamicMetadataVMEnabled == true) {</div><div class='add'>+		*p-&gt;Tdmdl_vm = s-&gt;TWait_p + *p-&gt;Tvm_trips;</div><div class='add'>+		*p-&gt;Tdmdl = *p-&gt;Tdmdl_vm + p-&gt;Ttrip;</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;Tdmdl_vm = 0;</div><div class='add'>+		*p-&gt;Tdmdl = s-&gt;TWait_p + p-&gt;ExtraLatencyPrefetch + p-&gt;Ttrip; // Tex</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;DynamicMetadataEnable == true) {</div><div class='add'>+		if (p-&gt;VStartup * s-&gt;LineTime &lt; *p-&gt;TSetup + *p-&gt;Tdmdl + s-&gt;Tdmbf + s-&gt;Tdmec + s-&gt;Tdmsks) {</div><div class='add'>+			*p-&gt;NotEnoughTimeForDynamicMetadata = true;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, s-&gt;Tdmbf);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, s-&gt;Tdmec);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", __func__, s-&gt;Tdmsks);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", __func__, *p-&gt;Tdmdl);</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;NotEnoughTimeForDynamicMetadata = false;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;NotEnoughTimeForDynamicMetadata = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;myPipe-&gt;ScalerEnabled)</div><div class='add'>+		s-&gt;DPPCycles = (unsigned int)(p-&gt;DPPCLKDelaySubtotalPlusCNVCFormater + p-&gt;DPPCLKDelaySCL);</div><div class='add'>+	else</div><div class='add'>+		s-&gt;DPPCycles = (unsigned int)(p-&gt;DPPCLKDelaySubtotalPlusCNVCFormater + p-&gt;DPPCLKDelaySCLLBOnly);</div><div class='add'>+</div><div class='add'>+	s-&gt;DPPCycles = (unsigned int)(s-&gt;DPPCycles + p-&gt;myPipe-&gt;NumberOfCursors * p-&gt;DPPCLKDelayCNVCCursor);</div><div class='add'>+</div><div class='add'>+	s-&gt;DISPCLKCycles = (unsigned int)p-&gt;DISPCLKDelaySubtotal;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;myPipe-&gt;Dppclk == 0.0 || p-&gt;myPipe-&gt;Dispclk == 0.0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	*p-&gt;DSTXAfterScaler = (unsigned int)math_round(s-&gt;DPPCycles * p-&gt;myPipe-&gt;PixelClock / p-&gt;myPipe-&gt;Dppclk + s-&gt;DISPCLKCycles * p-&gt;myPipe-&gt;PixelClock / p-&gt;myPipe-&gt;Dispclk + p-&gt;DSCDelay);</div><div class='add'>+	*p-&gt;DSTXAfterScaler = (unsigned int)math_round(*p-&gt;DSTXAfterScaler + (p-&gt;myPipe-&gt;ODMMode != dml2_odm_mode_bypass ? 18 : 0) + (p-&gt;myPipe-&gt;DPPPerSurface - 1) * p-&gt;DPP_RECOUT_WIDTH +</div><div class='add'>+		((p-&gt;myPipe-&gt;ODMMode == dml2_odm_mode_split_1to2 || p-&gt;myPipe-&gt;ODMMode == dml2_odm_mode_mso_1to2) ? (double)p-&gt;myPipe-&gt;HActive / 2.0 : 0) +</div><div class='add'>+		((p-&gt;myPipe-&gt;ODMMode == dml2_odm_mode_mso_1to4) ? (double)p-&gt;myPipe-&gt;HActive * 3.0 / 4.0 : 0));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DynamicMetadataVMEnabled = %u\n", __func__, p-&gt;DynamicMetadataVMEnabled);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DPPCycles = %u\n", __func__, s-&gt;DPPCycles);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelClock = %f\n", __func__, p-&gt;myPipe-&gt;PixelClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Dppclk = %f\n", __func__, p-&gt;myPipe-&gt;Dppclk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DISPCLKCycles = %u\n", __func__, s-&gt;DISPCLKCycles);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DISPCLK = %f\n", __func__, p-&gt;myPipe-&gt;Dispclk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSCDelay = %u\n", __func__, p-&gt;DSCDelay);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ODMMode = %u\n", __func__, p-&gt;myPipe-&gt;ODMMode);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DPP_RECOUT_WIDTH = %u\n", __func__, p-&gt;DPP_RECOUT_WIDTH);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSTXAfterScaler = %u\n", __func__, *p-&gt;DSTXAfterScaler);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: setup_for_tdlut = %u\n", __func__, p-&gt;setup_for_tdlut);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_opt_time = %f\n", __func__, p-&gt;tdlut_opt_time);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_pte_bytes_per_frame = %u\n", __func__, p-&gt;tdlut_pte_bytes_per_frame);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_drain_time = %f\n", __func__, p-&gt;tdlut_drain_time);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (p-&gt;OutputFormat == dml2_420 || (p-&gt;myPipe-&gt;InterlaceEnable &amp;&amp; p-&gt;myPipe-&gt;ProgressiveToInterlaceUnitInOPP))</div><div class='add'>+		*p-&gt;DSTYAfterScaler = 1;</div><div class='add'>+	else</div><div class='add'>+		*p-&gt;DSTYAfterScaler = 0;</div><div class='add'>+</div><div class='add'>+	s-&gt;DSTTotalPixelsAfterScaler = *p-&gt;DSTYAfterScaler * p-&gt;myPipe-&gt;HTotal + *p-&gt;DSTXAfterScaler;</div><div class='add'>+	*p-&gt;DSTYAfterScaler = (unsigned int)(math_floor2(s-&gt;DSTTotalPixelsAfterScaler / p-&gt;myPipe-&gt;HTotal, 1));</div><div class='add'>+	*p-&gt;DSTXAfterScaler = (unsigned int)(s-&gt;DSTTotalPixelsAfterScaler - ((double)(*p-&gt;DSTYAfterScaler * p-&gt;myPipe-&gt;HTotal)));</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSTXAfterScaler = %u (final)\n", __func__, *p-&gt;DSTXAfterScaler);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSTYAfterScaler = %u (final)\n", __func__, *p-&gt;DSTYAfterScaler);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_trips = %f\n", __func__, *p-&gt;Tr0_trips);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_trips = %f\n", __func__, *p-&gt;Tvm_trips);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: trip_to_mem = %f\n", __func__, s-&gt;trip_to_mem);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExtraLatencyPrefetch = %f\n", __func__, p-&gt;ExtraLatencyPrefetch);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMPageTableLevels = %u\n", __func__, p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HostVMDynamicLevelsTrips = %u\n", __func__, s-&gt;HostVMDynamicLevelsTrips);</div><div class='add'>+#endif</div><div class='add'>+	if (p-&gt;display_cfg-&gt;gpuvm_enable) {</div><div class='add'>+		s-&gt;Tvm_trips_rounded = math_ceil2(4.0 * *p-&gt;Tvm_trips / s-&gt;LineTime, 1.0) / 4.0 * s-&gt;LineTime;</div><div class='add'>+		*p-&gt;Tvm_trips_flip_rounded = math_ceil2(4.0 * *p-&gt;Tvm_trips_flip / s-&gt;LineTime, 1.0) / 4.0 * s-&gt;LineTime;</div><div class='add'>+	} else {</div><div class='add'>+		if (p-&gt;DynamicMetadataEnable || dcc_mrq_enable || p-&gt;setup_for_tdlut)</div><div class='add'>+			s-&gt;Tvm_trips_rounded = math_max2(s-&gt;LineTime * math_ceil2(4.0*math_max3(p-&gt;ExtraLatencyPrefetch, p-&gt;Turg, s-&gt;trip_to_mem)/s-&gt;LineTime, 1)/4, s-&gt;LineTime/4.0);</div><div class='add'>+		else</div><div class='add'>+			s-&gt;Tvm_trips_rounded = s-&gt;LineTime / 4.0;</div><div class='add'>+		*p-&gt;Tvm_trips_flip_rounded = s-&gt;LineTime / 4.0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	s-&gt;Tvm_trips_rounded = math_max2(s-&gt;Tvm_trips_rounded, s-&gt;LineTime / 4.0);</div><div class='add'>+	*p-&gt;Tvm_trips_flip_rounded = math_max2(*p-&gt;Tvm_trips_flip_rounded, s-&gt;LineTime / 4.0);</div><div class='add'>+</div><div class='add'>+	if (p-&gt;display_cfg-&gt;gpuvm_enable == true || p-&gt;setup_for_tdlut || dcc_mrq_enable) {</div><div class='add'>+		s-&gt;Tr0_trips_rounded = math_ceil2(4.0 * *p-&gt;Tr0_trips / s-&gt;LineTime, 1.0) / 4.0 * s-&gt;LineTime;</div><div class='add'>+		*p-&gt;Tr0_trips_flip_rounded = math_ceil2(4.0 * *p-&gt;Tr0_trips_flip / s-&gt;LineTime, 1.0) / 4.0 * s-&gt;LineTime;</div><div class='add'>+	} else {</div><div class='add'>+		s-&gt;Tr0_trips_rounded = s-&gt;LineTime / 4.0;</div><div class='add'>+		*p-&gt;Tr0_trips_flip_rounded = s-&gt;LineTime / 4.0;</div><div class='add'>+	}</div><div class='add'>+	s-&gt;Tr0_trips_rounded = math_max2(s-&gt;Tr0_trips_rounded, s-&gt;LineTime / 4.0);</div><div class='add'>+	*p-&gt;Tr0_trips_flip_rounded = math_max2(*p-&gt;Tr0_trips_flip_rounded, s-&gt;LineTime / 4.0);</div><div class='add'>+</div><div class='add'>+	if (p-&gt;display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+		if (p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels &gt;= 3) {</div><div class='add'>+			*p-&gt;Tno_bw = p-&gt;ExtraLatencyPrefetch + s-&gt;trip_to_mem * (double)((p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels - 2) * (s-&gt;HostVMDynamicLevelsTrips + 1));</div><div class='add'>+		} else if (p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels == 1 &amp;&amp; !dcc_mrq_enable &amp;&amp; !p-&gt;setup_for_tdlut) {</div><div class='add'>+			*p-&gt;Tno_bw = p-&gt;ExtraLatencyPrefetch;</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;Tno_bw = 0;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;Tno_bw = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;mrq_present || p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels &gt;= 3)</div><div class='add'>+		*p-&gt;Tno_bw_flip = *p-&gt;Tno_bw;</div><div class='add'>+	else</div><div class='add'>+		*p-&gt;Tno_bw_flip = 0; //because there is no 3DLUT for iFlip</div><div class='add'>+</div><div class='add'>+	if (dml_is_420(p-&gt;myPipe-&gt;SourcePixelFormat)) {</div><div class='add'>+		s-&gt;bytes_pp = p-&gt;myPipe-&gt;BytePerPixelY + p-&gt;myPipe-&gt;BytePerPixelC / 4.0;</div><div class='add'>+	} else {</div><div class='add'>+		s-&gt;bytes_pp = p-&gt;myPipe-&gt;BytePerPixelY + p-&gt;myPipe-&gt;BytePerPixelC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;prefetch_sw_bytes = p-&gt;PrefetchSourceLinesY * p-&gt;swath_width_luma_ub * p-&gt;myPipe-&gt;BytePerPixelY + p-&gt;PrefetchSourceLinesC * p-&gt;swath_width_chroma_ub * p-&gt;myPipe-&gt;BytePerPixelC;</div><div class='add'>+	*p-&gt;prefetch_sw_bytes = *p-&gt;prefetch_sw_bytes * p-&gt;mall_prefetch_sdp_overhead_factor;</div><div class='add'>+</div><div class='add'>+	vm_bytes = p-&gt;vm_bytes; // vm_bytes is dpde0_bytes_per_frame_ub_l + dpde0_bytes_per_frame_ub_c + 2*extra_dpde_bytes;</div><div class='add'>+	extra_tdpe_bytes = (unsigned int)math_max2(0, (p-&gt;display_cfg-&gt;gpuvm_max_page_table_levels - 1) * 128);</div><div class='add'>+</div><div class='add'>+	if (p-&gt;setup_for_tdlut)</div><div class='add'>+		vm_bytes = vm_bytes + p-&gt;tdlut_pte_bytes_per_frame + (p-&gt;display_cfg-&gt;gpuvm_enable ? extra_tdpe_bytes : 0);</div><div class='add'>+</div><div class='add'>+	tdlut_row_bytes = (unsigned long) math_ceil2(p-&gt;tdlut_bytes_per_frame/2.0, 1.0);</div><div class='add'>+</div><div class='add'>+	s-&gt;min_Lsw_oto = math_max2(p-&gt;PrefetchSourceLinesY, p-&gt;PrefetchSourceLinesC) / __DML2_CALCS_MAX_VRATIO_PRE_OTO__;</div><div class='add'>+	s-&gt;min_Lsw_oto = math_max2(s-&gt;min_Lsw_oto, p-&gt;tdlut_drain_time / s-&gt;LineTime);</div><div class='add'>+	s-&gt;min_Lsw_oto = math_max2(s-&gt;min_Lsw_oto, 2.0);</div><div class='add'>+</div><div class='add'>+	// use vactive swath bw for prefetch oto and also cap prefetch_bw_oto to max_vratio_oto</div><div class='add'>+	// Note: in prefetch calculation, acounting is done mostly per-pipe.</div><div class='add'>+	// vactive swath bw represents the per-surface (aka per dml plane) bw to move vratio_l/c lines of bytes_l/c per line time</div><div class='add'>+	s-&gt;per_pipe_vactive_sw_bw = p-&gt;vactive_sw_bw_l / (double)p-&gt;myPipe-&gt;DPPPerSurface;</div><div class='add'>+</div><div class='add'>+	// one-to-one prefetch bw as one line of bytes per line time (as per vratio_pre_l/c = 1)</div><div class='add'>+	s-&gt;prefetch_bw_oto = (p-&gt;swath_width_luma_ub * p-&gt;myPipe-&gt;BytePerPixelY) / s-&gt;LineTime;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;myPipe-&gt;BytePerPixelC &gt; 0) {</div><div class='add'>+		s-&gt;per_pipe_vactive_sw_bw += p-&gt;vactive_sw_bw_c / (double)p-&gt;myPipe-&gt;DPPPerSurface;</div><div class='add'>+		s-&gt;prefetch_bw_oto += (p-&gt;swath_width_chroma_ub * p-&gt;myPipe-&gt;BytePerPixelC) / s-&gt;LineTime;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* oto prefetch bw should be always be less than total vactive bw */</div><div class='add'>+	//DML_ASSERT(s-&gt;prefetch_bw_oto &lt; s-&gt;per_pipe_vactive_sw_bw * p-&gt;myPipe-&gt;DPPPerSurface);</div><div class='add'>+</div><div class='add'>+	s-&gt;prefetch_bw_oto = math_max2(s-&gt;per_pipe_vactive_sw_bw, s-&gt;prefetch_bw_oto) * p-&gt;mall_prefetch_sdp_overhead_factor;</div><div class='add'>+</div><div class='add'>+	s-&gt;prefetch_bw_oto = math_min2(s-&gt;prefetch_bw_oto, *p-&gt;prefetch_sw_bytes/(s-&gt;min_Lsw_oto*s-&gt;LineTime));</div><div class='add'>+</div><div class='add'>+	s-&gt;Lsw_oto = math_ceil2(4.0 * *p-&gt;prefetch_sw_bytes / s-&gt;prefetch_bw_oto / s-&gt;LineTime, 1.0) / 4.0;</div><div class='add'>+</div><div class='add'>+	s-&gt;prefetch_bw_oto = math_max3(s-&gt;prefetch_bw_oto,</div><div class='add'>+					p-&gt;vm_bytes * p-&gt;HostVMInefficiencyFactor / (31 * s-&gt;LineTime) - *p-&gt;Tno_bw,</div><div class='add'>+					(p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes) / (15 * s-&gt;LineTime));</div><div class='add'>+</div><div class='add'>+	/* oto bw needs to be outputted even if the oto schedule isn't being used to avoid ms/mp mismatch.</div><div class='add'>+	 * mp will fail if ms decides to use equ schedule and mp decides to use oto schedule</div><div class='add'>+	 * and the required bandwidth increases when going from ms to mp</div><div class='add'>+	 */</div><div class='add'>+	*p-&gt;RequiredPrefetchBWMax = s-&gt;prefetch_bw_oto;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_l = %f\n", __func__, p-&gt;vactive_sw_bw_l);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_c = %f\n", __func__, p-&gt;vactive_sw_bw_c);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: per_pipe_vactive_sw_bw = %f\n", __func__, s-&gt;per_pipe_vactive_sw_bw);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (p-&gt;display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+		s-&gt;Tvm_oto = math_max3(</div><div class='add'>+			*p-&gt;Tvm_trips,</div><div class='add'>+			*p-&gt;Tno_bw + vm_bytes * p-&gt;HostVMInefficiencyFactor / s-&gt;prefetch_bw_oto,</div><div class='add'>+			s-&gt;LineTime / 4.0);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_oto max0 = %f\n", __func__, *p-&gt;Tvm_trips);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_oto max1 = %f\n", __func__, *p-&gt;Tno_bw + vm_bytes * p-&gt;HostVMInefficiencyFactor / s-&gt;prefetch_bw_oto);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_oto max2 = %f\n", __func__, s-&gt;LineTime / 4.0);</div><div class='add'>+#endif</div><div class='add'>+	} else {</div><div class='add'>+		s-&gt;Tvm_oto = s-&gt;Tvm_trips_rounded;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((p-&gt;display_cfg-&gt;gpuvm_enable == true || p-&gt;setup_for_tdlut || dcc_mrq_enable)) {</div><div class='add'>+		s-&gt;Tr0_oto = math_max3(</div><div class='add'>+			*p-&gt;Tr0_trips,</div><div class='add'>+			(p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes) / s-&gt;prefetch_bw_oto,</div><div class='add'>+			s-&gt;LineTime / 4.0);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tr0_oto max0 = %f\n", __func__, *p-&gt;Tr0_trips);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tr0_oto max1 = %f\n", __func__, (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes) / s-&gt;prefetch_bw_oto);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tr0_oto max2 = %f\n", __func__, s-&gt;LineTime / 4);</div><div class='add'>+#endif</div><div class='add'>+	} else</div><div class='add'>+		s-&gt;Tr0_oto = s-&gt;LineTime / 4.0;</div><div class='add'>+</div><div class='add'>+	s-&gt;Tvm_oto_lines = math_ceil2(4.0 * s-&gt;Tvm_oto / s-&gt;LineTime, 1) / 4.0;</div><div class='add'>+	s-&gt;Tr0_oto_lines = math_ceil2(4.0 * s-&gt;Tr0_oto / s-&gt;LineTime, 1) / 4.0;</div><div class='add'>+	s-&gt;dst_y_prefetch_oto = s-&gt;Tvm_oto_lines + 2 * s-&gt;Tr0_oto_lines + s-&gt;Lsw_oto;</div><div class='add'>+</div><div class='add'>+#ifdef DML_GLOBAL_PREFETCH_CHECK</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: impacted_Tpre = %f\n", __func__, p-&gt;impacted_dst_y_pre);</div><div class='add'>+	if (p-&gt;impacted_dst_y_pre &gt; 0) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_prefetch_oto = %f\n", __func__, s-&gt;dst_y_prefetch_oto);</div><div class='add'>+		s-&gt;dst_y_prefetch_oto = math_max2(s-&gt;dst_y_prefetch_oto, p-&gt;impacted_dst_y_pre);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_prefetch_oto = %f (impacted)\n", __func__, s-&gt;dst_y_prefetch_oto);</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+	*p-&gt;Tpre_oto = s-&gt;dst_y_prefetch_oto * s-&gt;LineTime;</div><div class='add'>+</div><div class='add'>+	//To (time for delay after scaler) in line time</div><div class='add'>+	Lo = (unsigned int)(*p-&gt;DSTYAfterScaler + (double)*p-&gt;DSTXAfterScaler / (double)p-&gt;myPipe-&gt;HTotal);</div><div class='add'>+</div><div class='add'>+	s-&gt;min_Lsw_equ = math_max2(p-&gt;PrefetchSourceLinesY, p-&gt;PrefetchSourceLinesC) / __DML2_CALCS_MAX_VRATIO_PRE_EQU__;</div><div class='add'>+	s-&gt;min_Lsw_equ = math_max2(s-&gt;min_Lsw_equ, p-&gt;tdlut_drain_time / s-&gt;LineTime);</div><div class='add'>+	s-&gt;min_Lsw_equ = math_max2(s-&gt;min_Lsw_equ, 2.0);</div><div class='add'>+	//Tpre_equ in line time</div><div class='add'>+	if (p-&gt;DynamicMetadataVMEnabled &amp;&amp; p-&gt;DynamicMetadataEnable)</div><div class='add'>+		s-&gt;dst_y_prefetch_equ = p-&gt;VStartup - (*p-&gt;TSetup + math_max2(p-&gt;TCalc, *p-&gt;Tvm_trips) + s-&gt;TWait_p) / s-&gt;LineTime - Lo;</div><div class='add'>+	else</div><div class='add'>+		s-&gt;dst_y_prefetch_equ = p-&gt;VStartup - (*p-&gt;TSetup + math_max2(p-&gt;TCalc, p-&gt;ExtraLatencyPrefetch) + s-&gt;TWait_p) / s-&gt;LineTime - Lo;</div><div class='add'>+</div><div class='add'>+#ifdef DML_GLOBAL_PREFETCH_CHECK</div><div class='add'>+	s-&gt;dst_y_prefetch_equ_impacted = math_max2(p-&gt;impacted_dst_y_pre, s-&gt;dst_y_prefetch_equ);</div><div class='add'>+</div><div class='add'>+	s-&gt;dst_y_prefetch_equ_impacted = math_min2(s-&gt;dst_y_prefetch_equ_impacted, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH</div><div class='add'>+</div><div class='add'>+	if (s-&gt;dst_y_prefetch_equ_impacted &gt; s-&gt;dst_y_prefetch_equ)</div><div class='add'>+		s-&gt;dst_y_prefetch_equ -= s-&gt;dst_y_prefetch_equ_impacted - s-&gt;dst_y_prefetch_equ;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	s-&gt;dst_y_prefetch_equ = math_min2(s-&gt;dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HTotal = %u\n", __func__, p-&gt;myPipe-&gt;HTotal);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_Lsw_oto = %f\n", __func__, s-&gt;min_Lsw_oto);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_Lsw_equ = %f\n", __func__, s-&gt;min_Lsw_equ);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tno_bw = %f\n", __func__, *p-&gt;Tno_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tno_bw_flip = %f\n", __func__, *p-&gt;Tno_bw_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExtraLatencyPrefetch = %f\n", __func__, p-&gt;ExtraLatencyPrefetch);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: trip_to_mem = %f\n", __func__, s-&gt;trip_to_mem);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mall_prefetch_sdp_overhead_factor = %f\n", __func__, p-&gt;mall_prefetch_sdp_overhead_factor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelY = %u\n", __func__, p-&gt;myPipe-&gt;BytePerPixelY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PrefetchSourceLinesY = %f\n", __func__, p-&gt;PrefetchSourceLinesY);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: swath_width_luma_ub = %u\n", __func__, p-&gt;swath_width_luma_ub);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BytePerPixelC = %u\n", __func__, p-&gt;myPipe-&gt;BytePerPixelC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PrefetchSourceLinesC = %f\n", __func__, p-&gt;PrefetchSourceLinesC);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: swath_width_chroma_ub = %u\n", __func__, p-&gt;swath_width_chroma_ub);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: prefetch_sw_bytes = %f\n", __func__, *p-&gt;prefetch_sw_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_Tsw = %f\n", __func__, s-&gt;max_Tsw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: bytes_pp = %f\n", __func__, s-&gt;bytes_pp);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vm_bytes = %u\n", __func__, vm_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, p-&gt;PixelPTEBytesPerRow);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, p-&gt;HostVMInefficiencyFactor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_trips = %f\n", __func__, *p-&gt;Tvm_trips);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_trips = %f\n", __func__, *p-&gt;Tr0_trips);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_trips_flip = %f\n", __func__, *p-&gt;Tvm_trips_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_trips_flip = %f\n", __func__, *p-&gt;Tr0_trips_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: prefetch_bw_pr = %f\n", __func__, s-&gt;prefetch_bw_pr);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: prefetch_bw_oto = %f\n", __func__, s-&gt;prefetch_bw_oto);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_oto = %f\n", __func__, s-&gt;Tr0_oto);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_oto = %f\n", __func__, s-&gt;Tvm_oto);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_oto_lines = %f\n", __func__, s-&gt;Tvm_oto_lines);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_oto_lines = %f\n", __func__, s-&gt;Tr0_oto_lines);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Lsw_oto = %f\n", __func__, s-&gt;Lsw_oto);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dst_y_prefetch_oto = %f\n", __func__, s-&gt;dst_y_prefetch_oto);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dst_y_prefetch_equ = %f\n", __func__, s-&gt;dst_y_prefetch_equ);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: tdlut_row_bytes = %d\n", __func__, tdlut_row_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_row_bytes = %d\n", __func__, p-&gt;meta_row_bytes);</div><div class='add'>+#endif</div><div class='add'>+	s-&gt;dst_y_prefetch_equ = math_floor2(4.0 * (s-&gt;dst_y_prefetch_equ + 0.125), 1) / 4.0;</div><div class='add'>+	*p-&gt;Tpre_rounded = s-&gt;dst_y_prefetch_equ * s-&gt;LineTime;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, s-&gt;dst_y_prefetch_equ);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: LineTime: %f\n", __func__, s-&gt;LineTime);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VStartup: %u\n", __func__, p-&gt;VStartup);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvstartup: %fus - time between vstartup and first pixel of active\n", __func__, p-&gt;VStartup * s-&gt;LineTime);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TSetup: %fus - time from vstartup to vready\n", __func__, *p-&gt;TSetup);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TCalc: %fus - time for calculations in dchub starting at vready\n", __func__, p-&gt;TCalc);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait: %fus - time for fabric to become ready max(pstate exit,cstate enter/exit, urgent latency) after TCalc\n", __func__, p-&gt;TWait);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, s-&gt;Tdmbf);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, s-&gt;Tdmec);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", __func__, s-&gt;Tdmsks);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait = %f\n", __func__, p-&gt;TWait);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait_p = %f\n", __func__, s-&gt;TWait_p);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Ttrip = %f\n", __func__, p-&gt;Ttrip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tex = %f\n", __func__, p-&gt;ExtraLatencyPrefetch);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tdmdl_vm: %fus - time for vm stages of dmd \n", __func__, *p-&gt;Tdmdl_vm);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", __func__, *p-&gt;Tdmdl);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TWait_p: %fus\n", __func__, s-&gt;TWait_p);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Ttrip: %fus\n", __func__, p-&gt;Ttrip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSTXAfterScaler: %u pixels - number of pixel clocks pipeline and buffer delay after scaler \n", __func__, *p-&gt;DSTXAfterScaler);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DSTYAfterScaler: %u lines - number of lines of pipeline and buffer delay after scaler \n", __func__, *p-&gt;DSTYAfterScaler);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vm_bytes: %f (hvm inefficiency scaled)\n", __func__, vm_bytes*p-&gt;HostVMInefficiencyFactor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: row_bytes: %f (hvm inefficiency scaled, 1 row)\n", __func__, p-&gt;PixelPTEBytesPerRow*p-&gt;HostVMInefficiencyFactor+p-&gt;meta_row_bytes+tdlut_row_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tno_bw: %f\n", __func__, *p-&gt;Tno_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tpre=%f Tpre_rounded: %f, delta=%f\n", __func__, (s-&gt;dst_y_prefetch_equ * s-&gt;LineTime), *p-&gt;Tpre_rounded, (*p-&gt;Tpre_rounded - (s-&gt;dst_y_prefetch_equ * s-&gt;LineTime)));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_trips=%f Tvm_trips_rounded: %f, delta=%f\n", __func__, *p-&gt;Tvm_trips, s-&gt;Tvm_trips_rounded, (s-&gt;Tvm_trips_rounded - *p-&gt;Tvm_trips));</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	*p-&gt;dst_y_per_vm_vblank = 0;</div><div class='add'>+	*p-&gt;dst_y_per_row_vblank = 0;</div><div class='add'>+	*p-&gt;VRatioPrefetchY = 0;</div><div class='add'>+	*p-&gt;VRatioPrefetchC = 0;</div><div class='add'>+	*p-&gt;RequiredPrefetchPixelDataBWLuma = 0;</div><div class='add'>+</div><div class='add'>+	// Derive bandwidth by finding how much data to move within the time constraint</div><div class='add'>+	// Tpre_rounded is Tpre rounding to 2-bit fraction</div><div class='add'>+	// Tvm_trips_rounded is Tvm_trips ceiling to 1/4 line time</div><div class='add'>+	// Tr0_trips_rounded is Tr0_trips ceiling to 1/4 line time</div><div class='add'>+	// So that means prefetch bw calculated can be higher since the total time available for prefetch is less</div><div class='add'>+	bool min_Lsw_equ_ok = *p-&gt;Tpre_rounded &gt;= s-&gt;Tvm_trips_rounded + 2.0*s-&gt;Tr0_trips_rounded + s-&gt;min_Lsw_equ*s-&gt;LineTime;</div><div class='add'>+	bool tpre_gt_req_latency = true;</div><div class='add'>+#if 0</div><div class='add'>+	// Check that Tpre_rounded is big enough if all of the stages of the prefetch are time constrained.</div><div class='add'>+	// The terms Tvm_trips_rounded and Tr0_trips_rounded represent the min time constraints for the VM and row stages.</div><div class='add'>+	// Normally, these terms cover the overall time constraint for Tpre &gt;= (Tex + max{Ttrip, Turg}), but if these terms are at their minimum, an explicit check is necessary.</div><div class='add'>+	tpre_gt_req_latency = *p-&gt;Tpre_rounded &gt; (math_max2(p-&gt;Turg, s-&gt;trip_to_mem) + p-&gt;ExtraLatencyPrefetch);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (s-&gt;dst_y_prefetch_equ &gt; 1 &amp;&amp; min_Lsw_equ_ok &amp;&amp; tpre_gt_req_latency) {</div><div class='add'>+		s-&gt;prefetch_bw1 = 0.;</div><div class='add'>+		s-&gt;prefetch_bw2 = 0.;</div><div class='add'>+		s-&gt;prefetch_bw3 = 0.;</div><div class='add'>+		s-&gt;prefetch_bw4 = 0.;</div><div class='add'>+</div><div class='add'>+		// prefetch_bw1: VM + 2*R0 + SW</div><div class='add'>+		if (*p-&gt;Tpre_rounded - *p-&gt;Tno_bw &gt; 0) {</div><div class='add'>+			s-&gt;prefetch_bw1 = (vm_bytes * p-&gt;HostVMInefficiencyFactor</div><div class='add'>+				+ 2 * (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes)</div><div class='add'>+				+ *p-&gt;prefetch_sw_bytes)</div><div class='add'>+				/ (*p-&gt;Tpre_rounded - *p-&gt;Tno_bw);</div><div class='add'>+			s-&gt;Tsw_est1 = *p-&gt;prefetch_sw_bytes / s-&gt;prefetch_bw1;</div><div class='add'>+		} else</div><div class='add'>+			s-&gt;prefetch_bw1 = 0;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw1: %f\n", __func__, s-&gt;prefetch_bw1);</div><div class='add'>+		if ((s-&gt;Tsw_est1 &lt; s-&gt;min_Lsw_equ * s-&gt;LineTime) &amp;&amp; (*p-&gt;Tpre_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.75 * s-&gt;LineTime - *p-&gt;Tno_bw &gt; 0)) {</div><div class='add'>+			s-&gt;prefetch_bw1 = (vm_bytes * p-&gt;HostVMInefficiencyFactor + 2 * (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes)) /</div><div class='add'>+				(*p-&gt;Tpre_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.75 * s-&gt;LineTime - *p-&gt;Tno_bw);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: vm and 2 rows bytes = %f\n", __func__, (vm_bytes * p-&gt;HostVMInefficiencyFactor + 2 * (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes)));</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tpre_rounded = %f\n", __func__, *p-&gt;Tpre_rounded);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: minus term = %f\n", __func__, s-&gt;min_Lsw_equ * s-&gt;LineTime + 0.75 * s-&gt;LineTime + *p-&gt;Tno_bw);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: min_Lsw_equ = %f\n", __func__, s-&gt;min_Lsw_equ);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, s-&gt;LineTime);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tno_bw = %f\n", __func__, *p-&gt;Tno_bw);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Time to fetch vm and 2 rows = %f\n", __func__, (*p-&gt;Tpre_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.75 * s-&gt;LineTime - *p-&gt;Tno_bw));</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: prefetch_bw1: %f (updated)\n", __func__, s-&gt;prefetch_bw1);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// prefetch_bw2: VM + SW</div><div class='add'>+		if (*p-&gt;Tpre_rounded - *p-&gt;Tno_bw - 2.0 * s-&gt;Tr0_trips_rounded &gt; 0) {</div><div class='add'>+			s-&gt;prefetch_bw2 = (vm_bytes * p-&gt;HostVMInefficiencyFactor + *p-&gt;prefetch_sw_bytes) /</div><div class='add'>+			(*p-&gt;Tpre_rounded - *p-&gt;Tno_bw - 2.0 * s-&gt;Tr0_trips_rounded);</div><div class='add'>+			s-&gt;Tsw_est2 = *p-&gt;prefetch_sw_bytes / s-&gt;prefetch_bw2;</div><div class='add'>+		} else</div><div class='add'>+			s-&gt;prefetch_bw2 = 0;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw2: %f\n", __func__, s-&gt;prefetch_bw2);</div><div class='add'>+		if ((s-&gt;Tsw_est2 &lt; s-&gt;min_Lsw_equ * s-&gt;LineTime) &amp;&amp; ((*p-&gt;Tpre_rounded - *p-&gt;Tno_bw - 2.0 * s-&gt;Tr0_trips_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.25 * s-&gt;LineTime) &gt; 0)) {</div><div class='add'>+			s-&gt;prefetch_bw2 = vm_bytes * p-&gt;HostVMInefficiencyFactor / (*p-&gt;Tpre_rounded - *p-&gt;Tno_bw - 2.0 * s-&gt;Tr0_trips_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.25 * s-&gt;LineTime);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: prefetch_bw2: %f (updated)\n", __func__, s-&gt;prefetch_bw2);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// prefetch_bw3: 2*R0 + SW</div><div class='add'>+		if (*p-&gt;Tpre_rounded - s-&gt;Tvm_trips_rounded &gt; 0) {</div><div class='add'>+			s-&gt;prefetch_bw3 = (2 * (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes) + *p-&gt;prefetch_sw_bytes) /</div><div class='add'>+				(*p-&gt;Tpre_rounded - s-&gt;Tvm_trips_rounded);</div><div class='add'>+			s-&gt;Tsw_est3 = *p-&gt;prefetch_sw_bytes / s-&gt;prefetch_bw3;</div><div class='add'>+		} else</div><div class='add'>+			s-&gt;prefetch_bw3 = 0;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw3: %f\n", __func__, s-&gt;prefetch_bw3);</div><div class='add'>+		if ((s-&gt;Tsw_est3 &lt; s-&gt;min_Lsw_equ * s-&gt;LineTime) &amp;&amp; ((*p-&gt;Tpre_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.5 * s-&gt;LineTime - s-&gt;Tvm_trips_rounded) &gt; 0)) {</div><div class='add'>+			s-&gt;prefetch_bw3 = (2 * (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes)) / (*p-&gt;Tpre_rounded - s-&gt;min_Lsw_equ * s-&gt;LineTime - 0.5 * s-&gt;LineTime - s-&gt;Tvm_trips_rounded);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: prefetch_bw3: %f (updated)\n", __func__, s-&gt;prefetch_bw3);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// prefetch_bw4: SW</div><div class='add'>+		if (*p-&gt;Tpre_rounded - s-&gt;Tvm_trips_rounded - 2 * s-&gt;Tr0_trips_rounded &gt; 0)</div><div class='add'>+			s-&gt;prefetch_bw4 = *p-&gt;prefetch_sw_bytes / (*p-&gt;Tpre_rounded - s-&gt;Tvm_trips_rounded - 2 * s-&gt;Tr0_trips_rounded);</div><div class='add'>+		else</div><div class='add'>+			s-&gt;prefetch_bw4 = 0;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tno_bw: %f\n", __func__, *p-&gt;Tno_bw);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tpre=%f Tpre_rounded: %f, delta=%f\n", __func__, s-&gt;dst_y_prefetch_equ * s-&gt;LineTime, *p-&gt;Tpre_rounded, (*p-&gt;Tpre_rounded - (s-&gt;dst_y_prefetch_equ * s-&gt;LineTime)));</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_trips=%f Tvm_trips_rounded: %f, delta=%f\n", __func__, *p-&gt;Tvm_trips, s-&gt;Tvm_trips_rounded, (s-&gt;Tvm_trips_rounded - *p-&gt;Tvm_trips));</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tr0_trips=%f Tr0_trips_rounded: %f, delta=%f\n", __func__, *p-&gt;Tr0_trips, s-&gt;Tr0_trips_rounded, (s-&gt;Tr0_trips_rounded - *p-&gt;Tr0_trips));</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tsw_est1: %f\n", __func__, s-&gt;Tsw_est1);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tsw_est2: %f\n", __func__, s-&gt;Tsw_est2);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tsw_est3: %f\n", __func__, s-&gt;Tsw_est3);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw1: %f (final)\n", __func__, s-&gt;prefetch_bw1);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw2: %f (final)\n", __func__, s-&gt;prefetch_bw2);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw3: %f (final)\n", __func__, s-&gt;prefetch_bw3);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_bw4: %f (final)\n", __func__, s-&gt;prefetch_bw4);</div><div class='add'>+#endif</div><div class='add'>+		{</div><div class='add'>+			bool Case1OK = false;</div><div class='add'>+			bool Case2OK = false;</div><div class='add'>+			bool Case3OK = false;</div><div class='add'>+</div><div class='add'>+			// get "equalized" bw among all stages (vm, r0, sw), so based is all 3 stages are just above the latency-based requirement</div><div class='add'>+			// so it is not too dis-portionally favor a particular stage, next is either r0 more agressive and next is vm more agressive, the worst is all are agressive</div><div class='add'>+			// vs the latency based number</div><div class='add'>+</div><div class='add'>+			// prefetch_bw1: VM + 2*R0 + SW</div><div class='add'>+			// so prefetch_bw1 will have enough bw to transfer the necessary data within Tpre_rounded - Tno_bw (Tpre is the the worst-case latency based time to fetch the data)</div><div class='add'>+			// here is to make sure equ bw wont be more agressive than the latency-based requirement.</div><div class='add'>+			// check vm time &gt;= vm_trips</div><div class='add'>+			// check r0 time &gt;= r0_trips</div><div class='add'>+</div><div class='add'>+			double total_row_bytes = (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes);</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tvm_trips_rounded = %f\n", __func__, s-&gt;Tvm_trips_rounded);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Tr0_trips_rounded = %f\n", __func__, s-&gt;Tr0_trips_rounded);</div><div class='add'>+</div><div class='add'>+			if (s-&gt;prefetch_bw1 &gt; 0) {</div><div class='add'>+				double vm_transfer_time = *p-&gt;Tno_bw + vm_bytes * p-&gt;HostVMInefficiencyFactor / s-&gt;prefetch_bw1;</div><div class='add'>+				double row_transfer_time = total_row_bytes / s-&gt;prefetch_bw1;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Case1: vm_transfer_time  = %f\n", __func__, vm_transfer_time);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Case1: row_transfer_time = %f\n", __func__, row_transfer_time);</div><div class='add'>+				if (vm_transfer_time &gt;= s-&gt;Tvm_trips_rounded &amp;&amp; row_transfer_time &gt;= s-&gt;Tr0_trips_rounded) {</div><div class='add'>+					Case1OK = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			// prefetch_bw2: VM + SW</div><div class='add'>+			// prefetch_bw2 will be enough bw to transfer VM and SW data within (Tpre_rounded - Tr0_trips_rounded - Tno_bw)</div><div class='add'>+			// check vm time &gt;= vm_trips</div><div class='add'>+			// check r0 time &lt; r0_trips</div><div class='add'>+			if (s-&gt;prefetch_bw2 &gt; 0) {</div><div class='add'>+				double vm_transfer_time = *p-&gt;Tno_bw + vm_bytes * p-&gt;HostVMInefficiencyFactor / s-&gt;prefetch_bw2;</div><div class='add'>+				double row_transfer_time = total_row_bytes / s-&gt;prefetch_bw2;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Case2: vm_transfer_time  = %f\n", __func__, vm_transfer_time);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Case2: row_transfer_time = %f\n", __func__, row_transfer_time);</div><div class='add'>+				if (vm_transfer_time &gt;= s-&gt;Tvm_trips_rounded &amp;&amp; row_transfer_time &lt; s-&gt;Tr0_trips_rounded) {</div><div class='add'>+					Case2OK = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			// prefetch_bw3: VM + 2*R0</div><div class='add'>+			// check vm time &lt; vm_trips</div><div class='add'>+			// check r0 time &gt;= r0_trips</div><div class='add'>+			if (s-&gt;prefetch_bw3 &gt; 0) {</div><div class='add'>+				double vm_transfer_time = *p-&gt;Tno_bw + vm_bytes * p-&gt;HostVMInefficiencyFactor / s-&gt;prefetch_bw3;</div><div class='add'>+				double row_transfer_time = total_row_bytes / s-&gt;prefetch_bw3;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Case3: vm_transfer_time  = %f\n", __func__, vm_transfer_time);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Case3: row_transfer_time = %f\n", __func__, row_transfer_time);</div><div class='add'>+				if (vm_transfer_time &lt; s-&gt;Tvm_trips_rounded &amp;&amp; row_transfer_time &gt;= s-&gt;Tr0_trips_rounded) {</div><div class='add'>+					Case3OK = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (Case1OK) {</div><div class='add'>+				s-&gt;prefetch_bw_equ = s-&gt;prefetch_bw1;</div><div class='add'>+			} else if (Case2OK) {</div><div class='add'>+				s-&gt;prefetch_bw_equ = s-&gt;prefetch_bw2;</div><div class='add'>+			} else if (Case3OK) {</div><div class='add'>+				s-&gt;prefetch_bw_equ = s-&gt;prefetch_bw3;</div><div class='add'>+			} else {</div><div class='add'>+				s-&gt;prefetch_bw_equ = s-&gt;prefetch_bw4;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			s-&gt;prefetch_bw_equ = math_max3(s-&gt;prefetch_bw_equ,</div><div class='add'>+							p-&gt;vm_bytes * p-&gt;HostVMInefficiencyFactor / (31 * s-&gt;LineTime) - *p-&gt;Tno_bw,</div><div class='add'>+							(p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes) / (15 * s-&gt;LineTime));</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Case1OK: %u\n", __func__, Case1OK);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Case2OK: %u\n", __func__, Case2OK);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Case3OK: %u\n", __func__, Case3OK);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: prefetch_bw_equ: %f\n", __func__, s-&gt;prefetch_bw_equ);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+			if (s-&gt;prefetch_bw_equ &gt; 0) {</div><div class='add'>+				if (p-&gt;display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+					s-&gt;Tvm_equ = math_max3(*p-&gt;Tno_bw + vm_bytes * p-&gt;HostVMInefficiencyFactor / s-&gt;prefetch_bw_equ, *p-&gt;Tvm_trips, s-&gt;LineTime / 4);</div><div class='add'>+				} else {</div><div class='add'>+					s-&gt;Tvm_equ = s-&gt;LineTime / 4;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if (p-&gt;display_cfg-&gt;gpuvm_enable == true || dcc_mrq_enable || p-&gt;setup_for_tdlut) {</div><div class='add'>+					s-&gt;Tr0_equ = math_max3((p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + p-&gt;meta_row_bytes + tdlut_row_bytes) / s-&gt;prefetch_bw_equ, // PixelPTEBytesPerRow is dpte_row_bytes</div><div class='add'>+						*p-&gt;Tr0_trips,</div><div class='add'>+						s-&gt;LineTime / 4);</div><div class='add'>+				} else {</div><div class='add'>+					s-&gt;Tr0_equ = s-&gt;LineTime / 4;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				s-&gt;Tvm_equ = 0;</div><div class='add'>+				s-&gt;Tr0_equ = 0;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: prefetch_bw_equ equals 0!\n", __func__);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_equ = %f\n", __func__, s-&gt;Tvm_equ);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tr0_equ = %f\n", __func__, s-&gt;Tr0_equ);</div><div class='add'>+#endif</div><div class='add'>+		// Use the more stressful prefetch schedule</div><div class='add'>+		if (s-&gt;dst_y_prefetch_oto &lt; s-&gt;dst_y_prefetch_equ) {</div><div class='add'>+			*p-&gt;dst_y_prefetch = s-&gt;dst_y_prefetch_oto;</div><div class='add'>+			s-&gt;TimeForFetchingVM = s-&gt;Tvm_oto;</div><div class='add'>+			s-&gt;TimeForFetchingRowInVBlank = s-&gt;Tr0_oto;</div><div class='add'>+</div><div class='add'>+			*p-&gt;dst_y_per_vm_vblank = math_ceil2(4.0 * s-&gt;TimeForFetchingVM / s-&gt;LineTime, 1.0) / 4.0;</div><div class='add'>+			*p-&gt;dst_y_per_row_vblank = math_ceil2(4.0 * s-&gt;TimeForFetchingRowInVBlank / s-&gt;LineTime, 1.0) / 4.0;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Using oto scheduling for prefetch\n", __func__);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;dst_y_prefetch = s-&gt;dst_y_prefetch_equ;</div><div class='add'>+</div><div class='add'>+			if (s-&gt;dst_y_prefetch_equ &lt; s-&gt;dst_y_prefetch_equ_impacted)</div><div class='add'>+				*p-&gt;dst_y_prefetch = s-&gt;dst_y_prefetch_equ_impacted;</div><div class='add'>+</div><div class='add'>+			s-&gt;TimeForFetchingVM = s-&gt;Tvm_equ;</div><div class='add'>+			s-&gt;TimeForFetchingRowInVBlank = s-&gt;Tr0_equ;</div><div class='add'>+</div><div class='add'>+			*p-&gt;dst_y_per_vm_vblank = math_ceil2(4.0 * s-&gt;TimeForFetchingVM / s-&gt;LineTime, 1.0) / 4.0;</div><div class='add'>+			*p-&gt;dst_y_per_row_vblank = math_ceil2(4.0 * s-&gt;TimeForFetchingRowInVBlank / s-&gt;LineTime, 1.0) / 4.0;</div><div class='add'>+</div><div class='add'>+			/* equ bw should be propagated so a ceiling of the equ bw is accounted for prior to mode programming.</div><div class='add'>+			 * Overall bandwidth may be lower when going from mode support to mode programming but final pixel data</div><div class='add'>+			 * bandwidth may end up higher than what was calculated in mode support.</div><div class='add'>+			 */</div><div class='add'>+			*p-&gt;RequiredPrefetchBWMax = math_max2(s-&gt;prefetch_bw_equ, *p-&gt;RequiredPrefetchBWMax);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Using equ bw scheduling for prefetch\n", __func__);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// Lsw = dst_y_prefetch - (dst_y_per_vm_vblank + 2*dst_y_per_row_vblank)</div><div class='add'>+		s-&gt;LinesToRequestPrefetchPixelData = *p-&gt;dst_y_prefetch - *p-&gt;dst_y_per_vm_vblank - 2 * *p-&gt;dst_y_per_row_vblank; // Lsw</div><div class='add'>+</div><div class='add'>+		s-&gt;cursor_prefetch_bytes = (unsigned int)math_max2(p-&gt;cursor_bytes_per_chunk, 4 * p-&gt;cursor_bytes_per_line);</div><div class='add'>+		*p-&gt;prefetch_cursor_bw = p-&gt;num_cursors * s-&gt;cursor_prefetch_bytes / (s-&gt;LinesToRequestPrefetchPixelData * s-&gt;LineTime);</div><div class='add'>+		*p-&gt;prefetch_swath_time_us = (s-&gt;LinesToRequestPrefetchPixelData * s-&gt;LineTime);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: TimeForFetchingVM = %f\n", __func__, s-&gt;TimeForFetchingVM);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, s-&gt;TimeForFetchingRowInVBlank);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, s-&gt;LineTime);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_prefetch = %f\n", __func__, *p-&gt;dst_y_prefetch);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_per_vm_vblank = %f\n", __func__, *p-&gt;dst_y_per_vm_vblank);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_per_row_vblank = %f\n", __func__, *p-&gt;dst_y_per_row_vblank);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, s-&gt;LinesToRequestPrefetchPixelData);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: PrefetchSourceLinesY = %f\n", __func__, p-&gt;PrefetchSourceLinesY);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_swath_time_us = %f\n", __func__, *p-&gt;prefetch_swath_time_us);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_chunk = %d\n", __func__, p-&gt;cursor_bytes_per_chunk);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_line = %d\n", __func__, p-&gt;cursor_bytes_per_line);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: cursor_prefetch_bytes = %d\n", __func__, s-&gt;cursor_prefetch_bytes);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: prefetch_cursor_bw = %f\n", __func__, *p-&gt;prefetch_cursor_bw);</div><div class='add'>+#endif</div><div class='add'>+		DML_ASSERT(*p-&gt;dst_y_prefetch &lt; 64);</div><div class='add'>+</div><div class='add'>+		unsigned int min_lsw_required = (unsigned int)math_max2(2, p-&gt;tdlut_drain_time / s-&gt;LineTime);</div><div class='add'>+		if (s-&gt;LinesToRequestPrefetchPixelData &gt;= min_lsw_required &amp;&amp; s-&gt;prefetch_bw_equ &gt; 0) {</div><div class='add'>+			*p-&gt;VRatioPrefetchY = (double)p-&gt;PrefetchSourceLinesY / s-&gt;LinesToRequestPrefetchPixelData;</div><div class='add'>+			*p-&gt;VRatioPrefetchY = math_max2(*p-&gt;VRatioPrefetchY, 1.0);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: VRatioPrefetchY = %f\n", __func__, *p-&gt;VRatioPrefetchY);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: SwathHeightY = %u\n", __func__, p-&gt;SwathHeightY);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: VInitPreFillY = %u\n", __func__, p-&gt;VInitPreFillY);</div><div class='add'>+#endif</div><div class='add'>+			if ((p-&gt;SwathHeightY &gt; 4) &amp;&amp; (p-&gt;VInitPreFillY &gt; 3)) {</div><div class='add'>+				if (s-&gt;LinesToRequestPrefetchPixelData &gt; (p-&gt;VInitPreFillY - 3.0) / 2.0) {</div><div class='add'>+					*p-&gt;VRatioPrefetchY = math_max2(*p-&gt;VRatioPrefetchY,</div><div class='add'>+						(double)p-&gt;MaxNumSwathY * p-&gt;SwathHeightY / (s-&gt;LinesToRequestPrefetchPixelData - (p-&gt;VInitPreFillY - 3.0) / 2.0));</div><div class='add'>+				} else {</div><div class='add'>+					s-&gt;NoTimeToPrefetch = true;</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: No time to prefetch!. LinesToRequestPrefetchPixelData=%f VinitPreFillY=%u\n", __func__, s-&gt;LinesToRequestPrefetchPixelData, p-&gt;VInitPreFillY);</div><div class='add'>+					*p-&gt;VRatioPrefetchY = 0;</div><div class='add'>+				}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: VRatioPrefetchY = %f\n", __func__, *p-&gt;VRatioPrefetchY);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: PrefetchSourceLinesY = %f\n", __func__, p-&gt;PrefetchSourceLinesY);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: MaxNumSwathY = %u\n", __func__, p-&gt;MaxNumSwathY);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			*p-&gt;VRatioPrefetchC = (double)p-&gt;PrefetchSourceLinesC / s-&gt;LinesToRequestPrefetchPixelData;</div><div class='add'>+			*p-&gt;VRatioPrefetchC = math_max2(*p-&gt;VRatioPrefetchC, 1.0);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: VRatioPrefetchC = %f\n", __func__, *p-&gt;VRatioPrefetchC);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: SwathHeightC = %u\n", __func__, p-&gt;SwathHeightC);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: VInitPreFillC = %u\n", __func__, p-&gt;VInitPreFillC);</div><div class='add'>+#endif</div><div class='add'>+			if ((p-&gt;SwathHeightC &gt; 4) &amp;&amp; (p-&gt;VInitPreFillC &gt; 3)) {</div><div class='add'>+				if (s-&gt;LinesToRequestPrefetchPixelData &gt; (p-&gt;VInitPreFillC - 3.0) / 2.0) {</div><div class='add'>+					*p-&gt;VRatioPrefetchC = math_max2(*p-&gt;VRatioPrefetchC, (double)p-&gt;MaxNumSwathC * p-&gt;SwathHeightC / (s-&gt;LinesToRequestPrefetchPixelData - (p-&gt;VInitPreFillC - 3.0) / 2.0));</div><div class='add'>+				} else {</div><div class='add'>+					s-&gt;NoTimeToPrefetch = true;</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: No time to prefetch!. LinesToRequestPrefetchPixelData=%f VInitPreFillC=%u\n", __func__, s-&gt;LinesToRequestPrefetchPixelData, p-&gt;VInitPreFillC);</div><div class='add'>+					*p-&gt;VRatioPrefetchC = 0;</div><div class='add'>+				}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: VRatioPrefetchC = %f\n", __func__, *p-&gt;VRatioPrefetchC);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: PrefetchSourceLinesC = %f\n", __func__, p-&gt;PrefetchSourceLinesC);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: MaxNumSwathC = %u\n", __func__, p-&gt;MaxNumSwathC);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			*p-&gt;RequiredPrefetchPixelDataBWLuma = (double)p-&gt;PrefetchSourceLinesY / s-&gt;LinesToRequestPrefetchPixelData * p-&gt;myPipe-&gt;BytePerPixelY * p-&gt;swath_width_luma_ub / s-&gt;LineTime;</div><div class='add'>+			*p-&gt;RequiredPrefetchPixelDataBWChroma = (double)p-&gt;PrefetchSourceLinesC / s-&gt;LinesToRequestPrefetchPixelData * p-&gt;myPipe-&gt;BytePerPixelC * p-&gt;swath_width_chroma_ub / s-&gt;LineTime;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: BytePerPixelY = %u\n", __func__, p-&gt;myPipe-&gt;BytePerPixelY);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: swath_width_luma_ub = %u\n", __func__, p-&gt;swath_width_luma_ub);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, s-&gt;LineTime);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: RequiredPrefetchPixelDataBWLuma = %f\n", __func__, *p-&gt;RequiredPrefetchPixelDataBWLuma);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: RequiredPrefetchPixelDataBWChroma = %f\n", __func__, *p-&gt;RequiredPrefetchPixelDataBWChroma);</div><div class='add'>+#endif</div><div class='add'>+		} else {</div><div class='add'>+			s-&gt;NoTimeToPrefetch = true;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: No time to prefetch!, LinesToRequestPrefetchPixelData: %f, should be &gt;= %d\n", __func__, s-&gt;LinesToRequestPrefetchPixelData, min_lsw_required);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: No time to prefetch!, prefetch_bw_equ: %f, should be &gt; 0\n", __func__, s-&gt;prefetch_bw_equ);</div><div class='add'>+			*p-&gt;VRatioPrefetchY = 0;</div><div class='add'>+			*p-&gt;VRatioPrefetchC = 0;</div><div class='add'>+			*p-&gt;RequiredPrefetchPixelDataBWLuma = 0;</div><div class='add'>+			*p-&gt;RequiredPrefetchPixelDataBWChroma = 0;</div><div class='add'>+		}</div><div class='add'>+		DML_LOG_VERBOSE("DML: Tpre: %fus - sum of time to request 2 x data pte, swaths\n", (double)s-&gt;LinesToRequestPrefetchPixelData * s-&gt;LineTime + 2.0 * s-&gt;TimeForFetchingRowInVBlank + s-&gt;TimeForFetchingVM);</div><div class='add'>+		DML_LOG_VERBOSE("DML: Tvm: %fus - time to fetch vm\n", s-&gt;TimeForFetchingVM);</div><div class='add'>+		DML_LOG_VERBOSE("DML: Tr0: %fus - time to fetch first row of data pagetables\n", s-&gt;TimeForFetchingRowInVBlank);</div><div class='add'>+		DML_LOG_VERBOSE("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n", (double)s-&gt;LinesToRequestPrefetchPixelData * s-&gt;LineTime);</div><div class='add'>+		DML_LOG_VERBOSE("DML: To: %fus - time for propagation from scaler to optc\n", (*p-&gt;DSTYAfterScaler + ((double)(*p-&gt;DSTXAfterScaler) / (double)p-&gt;myPipe-&gt;HTotal)) * s-&gt;LineTime);</div><div class='add'>+		DML_LOG_VERBOSE("DML: Tvstartup - TSetup - Tcalc - TWait - Tpre - To &gt; 0\n");</div><div class='add'>+		DML_LOG_VERBOSE("DML: Tslack(pre): %fus - time left over in schedule\n", p-&gt;VStartup * s-&gt;LineTime - s-&gt;TimeForFetchingVM - 2 * s-&gt;TimeForFetchingRowInVBlank - (*p-&gt;DSTYAfterScaler + ((double)(*p-&gt;DSTXAfterScaler) / (double)p-&gt;myPipe-&gt;HTotal)) * s-&gt;LineTime - p-&gt;TWait - p-&gt;TCalc - *p-&gt;TSetup);</div><div class='add'>+		DML_LOG_VERBOSE("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %u\n", p-&gt;PixelPTEBytesPerRow);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: No time to prefetch! dst_y_prefetch_equ = %f (should be &gt; 1)\n", __func__, s-&gt;dst_y_prefetch_equ);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: No time to prefetch! min_Lsw_equ_ok = %d, Tpre_rounded (%f) should be &gt;= Tvm_trips_rounded (%f) + 2.0*Tr0_trips_rounded (%f) + min_Tsw_equ (%f)\n",</div><div class='add'>+				__func__, min_Lsw_equ_ok, *p-&gt;Tpre_rounded, s-&gt;Tvm_trips_rounded, 2.0*s-&gt;Tr0_trips_rounded, s-&gt;min_Lsw_equ*s-&gt;LineTime);</div><div class='add'>+		s-&gt;NoTimeToPrefetch = true;</div><div class='add'>+		s-&gt;TimeForFetchingVM = 0;</div><div class='add'>+		s-&gt;TimeForFetchingRowInVBlank = 0;</div><div class='add'>+		*p-&gt;dst_y_per_vm_vblank = 0;</div><div class='add'>+		*p-&gt;dst_y_per_row_vblank = 0;</div><div class='add'>+		s-&gt;LinesToRequestPrefetchPixelData = 0;</div><div class='add'>+		*p-&gt;VRatioPrefetchY = 0;</div><div class='add'>+		*p-&gt;VRatioPrefetchC = 0;</div><div class='add'>+		*p-&gt;RequiredPrefetchPixelDataBWLuma = 0;</div><div class='add'>+		*p-&gt;RequiredPrefetchPixelDataBWChroma = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	{</div><div class='add'>+		double prefetch_vm_bw;</div><div class='add'>+		double prefetch_row_bw;</div><div class='add'>+</div><div class='add'>+		if (vm_bytes == 0) {</div><div class='add'>+			prefetch_vm_bw = 0;</div><div class='add'>+		} else if (*p-&gt;dst_y_per_vm_vblank &gt; 0) {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, p-&gt;HostVMInefficiencyFactor);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: dst_y_per_vm_vblank = %f\n", __func__, *p-&gt;dst_y_per_vm_vblank);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, s-&gt;LineTime);</div><div class='add'>+#endif</div><div class='add'>+			prefetch_vm_bw = vm_bytes * p-&gt;HostVMInefficiencyFactor / (*p-&gt;dst_y_per_vm_vblank * s-&gt;LineTime);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw);</div><div class='add'>+#endif</div><div class='add'>+		} else {</div><div class='add'>+			prefetch_vm_bw = 0;</div><div class='add'>+			s-&gt;NoTimeToPrefetch = true;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: No time to prefetch!. dst_y_per_vm_vblank=%f (should be &gt; 0)\n", __func__, *p-&gt;dst_y_per_vm_vblank);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;PixelPTEBytesPerRow == 0 &amp;&amp; tdlut_row_bytes == 0) {</div><div class='add'>+			prefetch_row_bw = 0;</div><div class='add'>+		} else if (*p-&gt;dst_y_per_row_vblank &gt; 0) {</div><div class='add'>+			prefetch_row_bw = (p-&gt;PixelPTEBytesPerRow * p-&gt;HostVMInefficiencyFactor + tdlut_row_bytes) / (*p-&gt;dst_y_per_row_vblank * s-&gt;LineTime);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, p-&gt;PixelPTEBytesPerRow);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: dst_y_per_row_vblank = %f\n", __func__, *p-&gt;dst_y_per_row_vblank);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw);</div><div class='add'>+#endif</div><div class='add'>+		} else {</div><div class='add'>+			prefetch_row_bw = 0;</div><div class='add'>+			s-&gt;NoTimeToPrefetch = true;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: No time to prefetch!. dst_y_per_row_vblank=%f (should be &gt; 0)\n", __func__, *p-&gt;dst_y_per_row_vblank);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*p-&gt;prefetch_vmrow_bw = math_max2(prefetch_vm_bw, prefetch_row_bw);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (s-&gt;NoTimeToPrefetch) {</div><div class='add'>+		s-&gt;TimeForFetchingVM = 0;</div><div class='add'>+		s-&gt;TimeForFetchingRowInVBlank = 0;</div><div class='add'>+		*p-&gt;dst_y_per_vm_vblank = 0;</div><div class='add'>+		*p-&gt;dst_y_per_row_vblank = 0;</div><div class='add'>+		*p-&gt;dst_y_prefetch = 0;</div><div class='add'>+		s-&gt;LinesToRequestPrefetchPixelData = 0;</div><div class='add'>+		*p-&gt;VRatioPrefetchY = 0;</div><div class='add'>+		*p-&gt;VRatioPrefetchC = 0;</div><div class='add'>+		*p-&gt;RequiredPrefetchPixelDataBWLuma = 0;</div><div class='add'>+		*p-&gt;RequiredPrefetchPixelDataBWChroma = 0;</div><div class='add'>+		*p-&gt;prefetch_vmrow_bw = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dst_y_per_vm_vblank = %f (final)\n", __func__, *p-&gt;dst_y_per_vm_vblank);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dst_y_per_row_vblank = %f (final)\n", __func__, *p-&gt;dst_y_per_row_vblank);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: prefetch_vmrow_bw = %f (final)\n", __func__, *p-&gt;prefetch_vmrow_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: RequiredPrefetchPixelDataBWLuma = %f (final)\n", __func__, *p-&gt;RequiredPrefetchPixelDataBWLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: RequiredPrefetchPixelDataBWChroma = %f (final)\n", __func__, *p-&gt;RequiredPrefetchPixelDataBWChroma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NoTimeToPrefetch=%d\n", __func__, s-&gt;NoTimeToPrefetch);</div><div class='add'>+</div><div class='add'>+	return s-&gt;NoTimeToPrefetch;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_num_lb_source_lines(unsigned int max_line_buffer_lines,</div><div class='add'>+									unsigned int line_buffer_size_bits,</div><div class='add'>+									unsigned int num_pipes,</div><div class='add'>+									unsigned int vp_width,</div><div class='add'>+									unsigned int vp_height,</div><div class='add'>+									double h_ratio,</div><div class='add'>+									enum dml2_rotation_angle rotation_angle)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_lb_source_lines = 0;</div><div class='add'>+	double lb_bit_per_pixel = 57.0;</div><div class='add'>+	unsigned recin_width = vp_width/num_pipes;</div><div class='add'>+</div><div class='add'>+	if (dml_is_vertical_rotation(rotation_angle))</div><div class='add'>+		recin_width = vp_height/num_pipes;</div><div class='add'>+</div><div class='add'>+	num_lb_source_lines = (unsigned int) math_min2((double) max_line_buffer_lines,</div><div class='add'>+								math_floor2(line_buffer_size_bits / lb_bit_per_pixel / (recin_width / math_max2(h_ratio, 1.0)), 1.0));</div><div class='add'>+</div><div class='add'>+	return num_lb_source_lines;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int find_max_impact_plane(unsigned int this_plane_idx, unsigned int num_planes, unsigned int Trpd_dcfclk_cycles[])</div><div class='add'>+{</div><div class='add'>+	int max_value = -1;</div><div class='add'>+	int max_idx = -1;</div><div class='add'>+	for (unsigned int i = 0; i &lt; num_planes; i++) {</div><div class='add'>+		if (i != this_plane_idx &amp;&amp; (int) Trpd_dcfclk_cycles[i] &gt; max_value) {</div><div class='add'>+			max_value = Trpd_dcfclk_cycles[i];</div><div class='add'>+			max_idx = i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	if (max_idx &lt;= 0) {</div><div class='add'>+		DML_ASSERT(max_idx &gt;= 0);</div><div class='add'>+		max_idx = this_plane_idx;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return max_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double calculate_impacted_Tsw(unsigned int exclude_plane_idx, unsigned int num_planes, double *prefetch_swath_bytes, double bw_mbps)</div><div class='add'>+{</div><div class='add'>+	double sum = 0.;</div><div class='add'>+	for (unsigned int i = 0; i &lt; num_planes; i++) {</div><div class='add'>+		if (i != exclude_plane_idx) {</div><div class='add'>+			sum += prefetch_swath_bytes[i];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return sum / bw_mbps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+// a global check against the aggregate effect of the per plane prefetch schedule</div><div class='add'>+static noinline_for_stack bool CheckGlobalPrefetchAdmissibility(struct dml2_core_internal_scratch *scratch,</div><div class='add'>+											 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *p)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals *s = &amp;scratch-&gt;CheckGlobalPrefetchAdmissibility_locals;</div><div class='add'>+	unsigned int i, k;</div><div class='add'>+</div><div class='add'>+	memset(s, 0, sizeof(struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals));</div><div class='add'>+</div><div class='add'>+	*p-&gt;recalc_prefetch_schedule = 0;</div><div class='add'>+	s-&gt;prefetch_global_check_passed = 1;</div><div class='add'>+	// worst case if the rob and cdb is fully hogged</div><div class='add'>+	s-&gt;max_Trpd_dcfclk_cycles = (unsigned int) math_ceil2((p-&gt;rob_buffer_size_kbytes*1024 + p-&gt;compressed_buffer_size_kbytes*DML_MAX_COMPRESSION_RATIO*1024)/64.0, 1.0);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_active_planes = %d\n", __func__, p-&gt;num_active_planes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: rob_buffer_size_kbytes = %d\n", __func__, p-&gt;rob_buffer_size_kbytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: compressed_buffer_size_kbytes = %d\n", __func__, p-&gt;compressed_buffer_size_kbytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: estimated_urg_bandwidth_required_mbps = %f\n", __func__, p-&gt;estimated_urg_bandwidth_required_mbps);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: estimated_dcfclk_mhz = %f\n", __func__, p-&gt;estimated_dcfclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_Trpd_dcfclk_cycles = %u\n", __func__, s-&gt;max_Trpd_dcfclk_cycles);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	// calculate the return impact from each plane, request is 256B per dcfclk</div><div class='add'>+	for (i = 0; i &lt; p-&gt;num_active_planes; i++) {</div><div class='add'>+		s-&gt;src_detile_buf_size_bytes_l[i] = p-&gt;detile_buffer_size_bytes_l[i];</div><div class='add'>+		s-&gt;src_detile_buf_size_bytes_c[i] = p-&gt;detile_buffer_size_bytes_c[i];</div><div class='add'>+		s-&gt;src_swath_bytes_l[i] = p-&gt;full_swath_bytes_l[i];</div><div class='add'>+		s-&gt;src_swath_bytes_c[i] = p-&gt;full_swath_bytes_c[i];</div><div class='add'>+</div><div class='add'>+		if (p-&gt;pixel_format[i] == dml2_420_10) {</div><div class='add'>+			s-&gt;src_detile_buf_size_bytes_l[i] = (unsigned int) (s-&gt;src_detile_buf_size_bytes_l[i] * 1.5);</div><div class='add'>+			s-&gt;src_detile_buf_size_bytes_c[i] = (unsigned int) (s-&gt;src_detile_buf_size_bytes_c[i] * 1.5);</div><div class='add'>+			s-&gt;src_swath_bytes_l[i] = (unsigned int) (s-&gt;src_swath_bytes_l[i] * 1.5);</div><div class='add'>+			s-&gt;src_swath_bytes_c[i] = (unsigned int) (s-&gt;src_swath_bytes_c[i] * 1.5);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		s-&gt;burst_bytes_to_fill_det = (unsigned int) (math_floor2(s-&gt;src_detile_buf_size_bytes_l[i] / p-&gt;chunk_bytes_l, 1) * p-&gt;chunk_bytes_l);</div><div class='add'>+		s-&gt;burst_bytes_to_fill_det += (unsigned int) (math_floor2(p-&gt;lb_source_lines_l[i] / p-&gt;swath_height_l[i], 1) * s-&gt;src_swath_bytes_l[i]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u pixel_format = %d\n", __func__, i, p-&gt;pixel_format[i]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u chunk_bytes_l = %d\n", __func__, i, p-&gt;chunk_bytes_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u lb_source_lines_l = %d\n", __func__, i, p-&gt;lb_source_lines_l[i]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u src_detile_buf_size_bytes_l=%d\n", __func__, i, s-&gt;src_detile_buf_size_bytes_l[i]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u src_swath_bytes_l=%d\n", __func__, i, s-&gt;src_swath_bytes_l[i]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u burst_bytes_to_fill_det=%d (luma)\n", __func__, i, s-&gt;burst_bytes_to_fill_det);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		if (s-&gt;src_swath_bytes_c[i] &gt; 0) { // dual_plane</div><div class='add'>+			s-&gt;burst_bytes_to_fill_det += (unsigned int) (math_floor2(s-&gt;src_detile_buf_size_bytes_c[i] / p-&gt;chunk_bytes_c, 1) * p-&gt;chunk_bytes_c);</div><div class='add'>+</div><div class='add'>+			if (p-&gt;pixel_format[i] == dml2_422_planar_8 || p-&gt;pixel_format[i] == dml2_422_planar_10 || p-&gt;pixel_format[i] == dml2_422_planar_12) {</div><div class='add'>+				s-&gt;burst_bytes_to_fill_det += (unsigned int) (math_floor2(p-&gt;lb_source_lines_c[i] / p-&gt;swath_height_c[i], 1) * s-&gt;src_swath_bytes_c[i]);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: i=%u chunk_bytes_c = %d\n", __func__, i, p-&gt;chunk_bytes_c);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: i=%u lb_source_lines_c = %d\n", __func__, i, p-&gt;lb_source_lines_c[i]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: i=%u src_detile_buf_size_bytes_c=%d\n", __func__, i, s-&gt;src_detile_buf_size_bytes_c[i]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: i=%u src_swath_bytes_c=%d\n", __func__, i, s-&gt;src_swath_bytes_c[i]);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		s-&gt;time_to_fill_det_us = (double) s-&gt;burst_bytes_to_fill_det / (256 * p-&gt;estimated_dcfclk_mhz); // fill time assume full burst at request rate</div><div class='add'>+		s-&gt;accumulated_return_path_dcfclk_cycles[i] = (unsigned int) math_ceil2(((DML_MAX_COMPRESSION_RATIO-1) * 64 * p-&gt;estimated_dcfclk_mhz) * s-&gt;time_to_fill_det_us / 64.0, 1.0); //for 64B per DCFClk</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u burst_bytes_to_fill_det=%d\n", __func__, i, s-&gt;burst_bytes_to_fill_det);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u time_to_fill_det_us=%f\n", __func__, i, s-&gt;time_to_fill_det_us);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u accumulated_return_path_dcfclk_cycles=%u\n", __func__, i, s-&gt;accumulated_return_path_dcfclk_cycles[i]);</div><div class='add'>+#endif</div><div class='add'>+		// clamping to worst case delay which is one which occupy the full rob+cdb</div><div class='add'>+		if (s-&gt;accumulated_return_path_dcfclk_cycles[i] &gt; s-&gt;max_Trpd_dcfclk_cycles)</div><div class='add'>+			s-&gt;accumulated_return_path_dcfclk_cycles[i] = s-&gt;max_Trpd_dcfclk_cycles;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Figure out the impacted prefetch time for each plane</div><div class='add'>+	// if impacted_Tre is &gt; equ bw Tpre, we need to fail the prefetch schedule as we need a higher state to support the bw</div><div class='add'>+	for (i = 0; i &lt; p-&gt;num_active_planes; i++) {</div><div class='add'>+		k = find_max_impact_plane(i, p-&gt;num_active_planes, s-&gt;accumulated_return_path_dcfclk_cycles); // plane k causes most impact to plane i</div><div class='add'>+		// the rest of planes (except for k) complete for bw</div><div class='add'>+		p-&gt;impacted_dst_y_pre[i] = s-&gt;accumulated_return_path_dcfclk_cycles[k]/p-&gt;estimated_dcfclk_mhz;</div><div class='add'>+		p-&gt;impacted_dst_y_pre[i] += calculate_impacted_Tsw(k, p-&gt;num_active_planes, p-&gt;prefetch_sw_bytes, p-&gt;estimated_urg_bandwidth_required_mbps);</div><div class='add'>+		p-&gt;impacted_dst_y_pre[i] = math_ceil2(p-&gt;impacted_dst_y_pre[i] / p-&gt;line_time[i], 0.25);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: i=%u impacted_Tpre=%f (k=%u)\n", __func__, i, p-&gt;impacted_dst_y_pre[i], k);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;Tpre_rounded != NULL &amp;&amp; p-&gt;Tpre_oto != NULL) {</div><div class='add'>+		for (i = 0; i &lt; p-&gt;num_active_planes; i++) {</div><div class='add'>+			if (p-&gt;impacted_dst_y_pre[i] &gt; p-&gt;dst_y_prefetch[i]) {</div><div class='add'>+				s-&gt;prefetch_global_check_passed = 0;</div><div class='add'>+				*p-&gt;recalc_prefetch_schedule = 1;</div><div class='add'>+			}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: i=%u Tpre_rounded=%f\n", __func__, i, p-&gt;Tpre_rounded[i]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: i=%u Tpre_oto=%f\n", __func__, i, p-&gt;Tpre_oto[i]);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		// likely a mode programming calls, assume support, and no recalc - not used anyways</div><div class='add'>+		s-&gt;prefetch_global_check_passed = 1;</div><div class='add'>+		*p-&gt;recalc_prefetch_schedule = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: prefetch_global_check_passed=%u\n", __func__, s-&gt;prefetch_global_check_passed);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: recalc_prefetch_schedule=%u\n", __func__, *p-&gt;recalc_prefetch_schedule);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return s-&gt;prefetch_global_check_passed;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_peak_bandwidth_required(</div><div class='add'>+	struct dml2_core_internal_scratch *s,</div><div class='add'>+	struct dml2_core_calcs_calculate_peak_bandwidth_required_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int n;</div><div class='add'>+	unsigned int m;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_shared_calculate_peak_bandwidth_required_locals *l = &amp;s-&gt;calculate_peak_bandwidth_required_locals;</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_core_shared_calculate_peak_bandwidth_required_locals));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: inc_flip_bw = %d\n", __func__, p-&gt;inc_flip_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfActiveSurfaces = %d\n", __func__, p-&gt;num_active_planes);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;num_active_planes; ++k) {</div><div class='add'>+		l-&gt;unity_array[k] = 1.0;</div><div class='add'>+		l-&gt;zero_array[k] = 0.0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (m = 0; m &lt; dml2_core_internal_soc_state_max; m++) {</div><div class='add'>+		for (n = 0; n &lt; dml2_core_internal_bw_max; n++) {</div><div class='add'>+			get_urgent_bandwidth_required(</div><div class='add'>+				&amp;s-&gt;get_urgent_bandwidth_required_locals,</div><div class='add'>+				p-&gt;display_cfg,</div><div class='add'>+				m,</div><div class='add'>+				n,</div><div class='add'>+				0, //inc_flip_bw,</div><div class='add'>+				0, //use_qual_row_bw</div><div class='add'>+				p-&gt;num_active_planes,</div><div class='add'>+				p-&gt;num_of_dpp,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p1,</div><div class='add'>+				p-&gt;mall_prefetch_sdp_overhead_factor,</div><div class='add'>+				p-&gt;mall_prefetch_dram_overhead_factor,</div><div class='add'>+				p-&gt;surface_read_bandwidth_l,</div><div class='add'>+				p-&gt;surface_read_bandwidth_c,</div><div class='add'>+				l-&gt;zero_array, //PrefetchBandwidthLuma,</div><div class='add'>+				l-&gt;zero_array, //PrefetchBandwidthChroma,</div><div class='add'>+				l-&gt;zero_array, //PrefetchBWMax</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				p-&gt;dpte_row_bw,</div><div class='add'>+				p-&gt;meta_row_bw,</div><div class='add'>+				l-&gt;zero_array, //prefetch_cursor_bw,</div><div class='add'>+				l-&gt;zero_array, //prefetch_vmrow_bw,</div><div class='add'>+				l-&gt;zero_array, //flip_bw,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				l-&gt;zero_array,</div><div class='add'>+				p-&gt;surface_avg_vactive_required_bw[m][n],</div><div class='add'>+				p-&gt;surface_peak_required_bw[m][n]);</div><div class='add'>+</div><div class='add'>+			p-&gt;urg_vactive_bandwidth_required[m][n] = get_urgent_bandwidth_required(</div><div class='add'>+				&amp;s-&gt;get_urgent_bandwidth_required_locals,</div><div class='add'>+				p-&gt;display_cfg,</div><div class='add'>+				m,</div><div class='add'>+				n,</div><div class='add'>+				0, //inc_flip_bw,</div><div class='add'>+				0, //use_qual_row_bw</div><div class='add'>+				p-&gt;num_active_planes,</div><div class='add'>+				p-&gt;num_of_dpp,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p1,</div><div class='add'>+				p-&gt;mall_prefetch_sdp_overhead_factor,</div><div class='add'>+				p-&gt;mall_prefetch_dram_overhead_factor,</div><div class='add'>+				p-&gt;surface_read_bandwidth_l,</div><div class='add'>+				p-&gt;surface_read_bandwidth_c,</div><div class='add'>+				l-&gt;zero_array, //PrefetchBandwidthLuma,</div><div class='add'>+				l-&gt;zero_array, //PrefetchBandwidthChroma,</div><div class='add'>+				l-&gt;zero_array, //PrefetchBWMax</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_l,</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_c,</div><div class='add'>+				p-&gt;cursor_bw,</div><div class='add'>+				p-&gt;dpte_row_bw,</div><div class='add'>+				p-&gt;meta_row_bw,</div><div class='add'>+				l-&gt;zero_array, //prefetch_cursor_bw,</div><div class='add'>+				l-&gt;zero_array, //prefetch_vmrow_bw,</div><div class='add'>+				l-&gt;zero_array, //flip_bw,</div><div class='add'>+				p-&gt;urgent_burst_factor_l,</div><div class='add'>+				p-&gt;urgent_burst_factor_c,</div><div class='add'>+				p-&gt;urgent_burst_factor_cursor,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_l,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_c,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_cursor,</div><div class='add'>+				l-&gt;surface_dummy_bw,</div><div class='add'>+				p-&gt;surface_peak_required_bw[m][n]);</div><div class='add'>+</div><div class='add'>+			p-&gt;urg_bandwidth_required[m][n] = get_urgent_bandwidth_required(</div><div class='add'>+				&amp;s-&gt;get_urgent_bandwidth_required_locals,</div><div class='add'>+				p-&gt;display_cfg,</div><div class='add'>+				m,</div><div class='add'>+				n,</div><div class='add'>+				p-&gt;inc_flip_bw,</div><div class='add'>+				0, //use_qual_row_bw</div><div class='add'>+				p-&gt;num_active_planes,</div><div class='add'>+				p-&gt;num_of_dpp,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p1,</div><div class='add'>+				p-&gt;mall_prefetch_sdp_overhead_factor,</div><div class='add'>+				p-&gt;mall_prefetch_dram_overhead_factor,</div><div class='add'>+				p-&gt;surface_read_bandwidth_l,</div><div class='add'>+				p-&gt;surface_read_bandwidth_c,</div><div class='add'>+				p-&gt;prefetch_bandwidth_l,</div><div class='add'>+				p-&gt;prefetch_bandwidth_c,</div><div class='add'>+				p-&gt;prefetch_bandwidth_max, // to prevent ms/mp mismatches where mp prefetch bw &gt; ms prefetch bw</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_l,</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_c,</div><div class='add'>+				p-&gt;cursor_bw,</div><div class='add'>+				p-&gt;dpte_row_bw,</div><div class='add'>+				p-&gt;meta_row_bw,</div><div class='add'>+				p-&gt;prefetch_cursor_bw,</div><div class='add'>+				p-&gt;prefetch_vmrow_bw,</div><div class='add'>+				p-&gt;flip_bw,</div><div class='add'>+				p-&gt;urgent_burst_factor_l,</div><div class='add'>+				p-&gt;urgent_burst_factor_c,</div><div class='add'>+				p-&gt;urgent_burst_factor_cursor,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_l,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_c,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_cursor,</div><div class='add'>+				l-&gt;surface_dummy_bw,</div><div class='add'>+				p-&gt;surface_peak_required_bw[m][n]);</div><div class='add'>+</div><div class='add'>+			p-&gt;urg_bandwidth_required_qual[m][n] = get_urgent_bandwidth_required(</div><div class='add'>+				&amp;s-&gt;get_urgent_bandwidth_required_locals,</div><div class='add'>+				p-&gt;display_cfg,</div><div class='add'>+				m,</div><div class='add'>+				n,</div><div class='add'>+				0, //inc_flip_bw</div><div class='add'>+				1, //use_qual_row_bw</div><div class='add'>+				p-&gt;num_active_planes,</div><div class='add'>+				p-&gt;num_of_dpp,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p1,</div><div class='add'>+				p-&gt;mall_prefetch_sdp_overhead_factor,</div><div class='add'>+				p-&gt;mall_prefetch_dram_overhead_factor,</div><div class='add'>+				p-&gt;surface_read_bandwidth_l,</div><div class='add'>+				p-&gt;surface_read_bandwidth_c,</div><div class='add'>+				p-&gt;prefetch_bandwidth_l,</div><div class='add'>+				p-&gt;prefetch_bandwidth_c,</div><div class='add'>+				p-&gt;prefetch_bandwidth_max, // to prevent ms/mp mismatch where mp prefetch bw &gt; ms prefetch bw</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_l,</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_c,</div><div class='add'>+				p-&gt;cursor_bw,</div><div class='add'>+				p-&gt;dpte_row_bw,</div><div class='add'>+				p-&gt;meta_row_bw,</div><div class='add'>+				p-&gt;prefetch_cursor_bw,</div><div class='add'>+				p-&gt;prefetch_vmrow_bw,</div><div class='add'>+				p-&gt;flip_bw,</div><div class='add'>+				p-&gt;urgent_burst_factor_l,</div><div class='add'>+				p-&gt;urgent_burst_factor_c,</div><div class='add'>+				p-&gt;urgent_burst_factor_cursor,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_l,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_c,</div><div class='add'>+				p-&gt;urgent_burst_factor_prefetch_cursor,</div><div class='add'>+				l-&gt;surface_dummy_bw,</div><div class='add'>+				p-&gt;surface_peak_required_bw[m][n]);</div><div class='add'>+</div><div class='add'>+			p-&gt;non_urg_bandwidth_required[m][n] = get_urgent_bandwidth_required(</div><div class='add'>+				&amp;s-&gt;get_urgent_bandwidth_required_locals,</div><div class='add'>+				p-&gt;display_cfg,</div><div class='add'>+				m,</div><div class='add'>+				n,</div><div class='add'>+				p-&gt;inc_flip_bw,</div><div class='add'>+				0, //use_qual_row_bw</div><div class='add'>+				p-&gt;num_active_planes,</div><div class='add'>+				p-&gt;num_of_dpp,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p0,</div><div class='add'>+				p-&gt;dcc_dram_bw_pref_overhead_factor_p1,</div><div class='add'>+				p-&gt;mall_prefetch_sdp_overhead_factor,</div><div class='add'>+				p-&gt;mall_prefetch_dram_overhead_factor,</div><div class='add'>+				p-&gt;surface_read_bandwidth_l,</div><div class='add'>+				p-&gt;surface_read_bandwidth_c,</div><div class='add'>+				p-&gt;prefetch_bandwidth_l,</div><div class='add'>+				p-&gt;prefetch_bandwidth_c,</div><div class='add'>+				p-&gt;prefetch_bandwidth_max, // to prevent ms/mp mismatches where mp prefetch bw &gt; ms prefetch bw</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_l,</div><div class='add'>+				p-&gt;excess_vactive_fill_bw_c,</div><div class='add'>+				p-&gt;cursor_bw,</div><div class='add'>+				p-&gt;dpte_row_bw,</div><div class='add'>+				p-&gt;meta_row_bw,</div><div class='add'>+				p-&gt;prefetch_cursor_bw,</div><div class='add'>+				p-&gt;prefetch_vmrow_bw,</div><div class='add'>+				p-&gt;flip_bw,</div><div class='add'>+				l-&gt;unity_array,</div><div class='add'>+				l-&gt;unity_array,</div><div class='add'>+				l-&gt;unity_array,</div><div class='add'>+				l-&gt;unity_array,</div><div class='add'>+				l-&gt;unity_array,</div><div class='add'>+				l-&gt;unity_array,</div><div class='add'>+				l-&gt;surface_dummy_bw,</div><div class='add'>+				p-&gt;surface_peak_required_bw[m][n]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: urg_vactive_bandwidth_required%s[%s][%s]=%f\n", __func__, (p-&gt;inc_flip_bw ? "_flip" : ""), dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), p-&gt;urg_vactive_bandwidth_required[m][n]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: urg_bandwidth_required%s[%s][%s]=%f\n", __func__, (p-&gt;inc_flip_bw ? "_flip" : ""), dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), p-&gt;urg_bandwidth_required[m][n]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: urg_bandwidth_required_qual[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), p-&gt;urg_bandwidth_required[m][n]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: non_urg_bandwidth_required%s[%s][%s]=%f\n", __func__, (p-&gt;inc_flip_bw ? "_flip" : ""), dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), p-&gt;non_urg_bandwidth_required[m][n]);</div><div class='add'>+#endif</div><div class='add'>+			DML_ASSERT(p-&gt;urg_bandwidth_required[m][n] &gt;= p-&gt;non_urg_bandwidth_required[m][n]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void check_urgent_bandwidth_support(</div><div class='add'>+	double *frac_urg_bandwidth_nom,</div><div class='add'>+	double *frac_urg_bandwidth_mall,</div><div class='add'>+	bool *vactive_bandwidth_support_ok, // vactive ok</div><div class='add'>+	bool *bandwidth_support_ok,// max of vm, prefetch, vactive all ok</div><div class='add'>+</div><div class='add'>+	unsigned int mall_allocated_for_dcn_mbytes,</div><div class='add'>+	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max])</div><div class='add'>+{</div><div class='add'>+	double frac_urg_bandwidth_nom_sdp = non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] / urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp];</div><div class='add'>+	double frac_urg_bandwidth_nom_dram = non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] / urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram];</div><div class='add'>+	double frac_urg_bandwidth_mall_sdp;</div><div class='add'>+	double frac_urg_bandwidth_mall_dram;</div><div class='add'>+	if (urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] &gt; 0)</div><div class='add'>+		frac_urg_bandwidth_mall_sdp = non_urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] / urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp];</div><div class='add'>+	else</div><div class='add'>+		frac_urg_bandwidth_mall_sdp = 0.0;</div><div class='add'>+	if (urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] &gt; 0)</div><div class='add'>+		frac_urg_bandwidth_mall_dram = non_urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] / urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram];</div><div class='add'>+	else</div><div class='add'>+		frac_urg_bandwidth_mall_dram = 0.0;</div><div class='add'>+</div><div class='add'>+	*bandwidth_support_ok = 1;</div><div class='add'>+	*vactive_bandwidth_support_ok = 1;</div><div class='add'>+</div><div class='add'>+	// Check urgent bandwidth required at sdp vs urgent bandwidth avail at sdp -&gt; FractionOfUrgentBandwidth</div><div class='add'>+	// Check urgent bandwidth required at dram vs urgent bandwidth avail at dram</div><div class='add'>+	// Check urgent bandwidth required at sdp vs urgent bandwidth avail at sdp, svp_prefetch -&gt; FractionOfUrgentBandwidthMALL</div><div class='add'>+	// Check urgent bandwidth required at dram vs urgent bandwidth avail at dram, svp_prefetch</div><div class='add'>+</div><div class='add'>+	*bandwidth_support_ok &amp;= urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp];</div><div class='add'>+	*bandwidth_support_ok &amp;= urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram];</div><div class='add'>+</div><div class='add'>+	if (mall_allocated_for_dcn_mbytes &gt; 0) {</div><div class='add'>+		*bandwidth_support_ok &amp;= urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp];</div><div class='add'>+		*bandwidth_support_ok &amp;= urg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*frac_urg_bandwidth_nom = math_max2(frac_urg_bandwidth_nom_sdp, frac_urg_bandwidth_nom_dram);</div><div class='add'>+	*frac_urg_bandwidth_mall = math_max2(frac_urg_bandwidth_mall_sdp, frac_urg_bandwidth_mall_dram);</div><div class='add'>+</div><div class='add'>+	*bandwidth_support_ok &amp;= (*frac_urg_bandwidth_nom &lt;= 1.0);</div><div class='add'>+</div><div class='add'>+	if (mall_allocated_for_dcn_mbytes &gt; 0)</div><div class='add'>+		*bandwidth_support_ok &amp;= (*frac_urg_bandwidth_mall &lt;= 1.0);</div><div class='add'>+</div><div class='add'>+	*vactive_bandwidth_support_ok &amp;= urg_vactive_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp];</div><div class='add'>+	*vactive_bandwidth_support_ok &amp;= urg_vactive_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram];</div><div class='add'>+	if (mall_allocated_for_dcn_mbytes &gt; 0) {</div><div class='add'>+		*vactive_bandwidth_support_ok &amp;= urg_vactive_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp];</div><div class='add'>+		*vactive_bandwidth_support_ok &amp;= urg_vactive_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] &lt;= urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_nom_sdp = %f\n", __func__, frac_urg_bandwidth_nom_sdp);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_nom_dram = %f\n", __func__, frac_urg_bandwidth_nom_dram);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_nom = %f\n", __func__, *frac_urg_bandwidth_nom);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_mall_sdp = %f\n", __func__, frac_urg_bandwidth_mall_sdp);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_mall_dram = %f\n", __func__, frac_urg_bandwidth_mall_dram);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_mall = %f\n", __func__, *frac_urg_bandwidth_mall);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: bandwidth_support_ok = %d\n", __func__, *bandwidth_support_ok);</div><div class='add'>+</div><div class='add'>+	for (unsigned int m = 0; m &lt; dml2_core_internal_soc_state_max; m++) {</div><div class='add'>+		for (unsigned int n = 0; n &lt; dml2_core_internal_bw_max; n++) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: state:%s bw_type:%s urg_bandwidth_available=%f %s urg_bandwidth_required=%f\n",</div><div class='add'>+			__func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n),</div><div class='add'>+			urg_bandwidth_available[m][n], (urg_bandwidth_available[m][n] &lt; urg_bandwidth_required[m][n]) ? "&lt;" : "&gt;=", urg_bandwidth_required[m][n]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double get_bandwidth_available_for_immediate_flip(enum dml2_core_internal_soc_state_type eval_state,</div><div class='add'>+	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max], // no flip</div><div class='add'>+	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max])</div><div class='add'>+{</div><div class='add'>+	double flip_bw_available_mbps;</div><div class='add'>+	double flip_bw_available_sdp_mbps;</div><div class='add'>+	double flip_bw_available_dram_mbps;</div><div class='add'>+</div><div class='add'>+	flip_bw_available_sdp_mbps = urg_bandwidth_available[eval_state][dml2_core_internal_bw_sdp] - urg_bandwidth_required[eval_state][dml2_core_internal_bw_sdp];</div><div class='add'>+	flip_bw_available_dram_mbps = urg_bandwidth_available[eval_state][dml2_core_internal_bw_dram] - urg_bandwidth_required[eval_state][dml2_core_internal_bw_dram];</div><div class='add'>+	flip_bw_available_mbps = flip_bw_available_sdp_mbps &lt; flip_bw_available_dram_mbps ? flip_bw_available_sdp_mbps : flip_bw_available_dram_mbps;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: eval_state = %s\n", __func__, dml2_core_internal_soc_state_type_str(eval_state));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: urg_bandwidth_available_sdp_mbps = %f\n", __func__, urg_bandwidth_available[eval_state][dml2_core_internal_bw_sdp]);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: urg_bandwidth_available_dram_mbps = %f\n", __func__, urg_bandwidth_available[eval_state][dml2_core_internal_bw_dram]);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: urg_bandwidth_required_sdp_mbps = %f\n", __func__, urg_bandwidth_required[eval_state][dml2_core_internal_bw_sdp]);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: urg_bandwidth_required_dram_mbps = %f\n", __func__, urg_bandwidth_required[eval_state][dml2_core_internal_bw_dram]);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: flip_bw_available_sdp_mbps = %f\n", __func__, flip_bw_available_sdp_mbps);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: flip_bw_available_dram_mbps = %f\n", __func__, flip_bw_available_dram_mbps);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: flip_bw_available_mbps = %f\n", __func__, flip_bw_available_mbps);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return flip_bw_available_mbps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_immediate_flip_bandwidth_support(</div><div class='add'>+	// Output</div><div class='add'>+	double *frac_urg_bandwidth_flip,</div><div class='add'>+	bool *flip_bandwidth_support_ok,</div><div class='add'>+</div><div class='add'>+	// Input</div><div class='add'>+	enum dml2_core_internal_soc_state_type eval_state,</div><div class='add'>+	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],</div><div class='add'>+	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max])</div><div class='add'>+{</div><div class='add'>+	double frac_urg_bw_flip_sdp = non_urg_bandwidth_required_flip[eval_state][dml2_core_internal_bw_sdp] / urg_bandwidth_available[eval_state][dml2_core_internal_bw_sdp];</div><div class='add'>+	double frac_urg_bw_flip_dram = non_urg_bandwidth_required_flip[eval_state][dml2_core_internal_bw_dram] / urg_bandwidth_available[eval_state][dml2_core_internal_bw_dram];</div><div class='add'>+</div><div class='add'>+	*flip_bandwidth_support_ok = true;</div><div class='add'>+	for (unsigned int n = 0; n &lt; dml2_core_internal_bw_max; n++) { // check sdp and dram</div><div class='add'>+		*flip_bandwidth_support_ok &amp;= urg_bandwidth_available[eval_state][n] &gt;= urg_bandwidth_required_flip[eval_state][n];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: n = %s\n", __func__, dml2_core_internal_bw_type_str(n));</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: urg_bandwidth_available = %f\n", __func__, urg_bandwidth_available[eval_state][n]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: non_urg_bandwidth_required_flip = %f\n", __func__, non_urg_bandwidth_required_flip[eval_state][n]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: urg_bandwidth_required_flip = %f\n", __func__, urg_bandwidth_required_flip[eval_state][n]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: flip_bandwidth_support_ok = %d\n", __func__, *flip_bandwidth_support_ok);</div><div class='add'>+#endif</div><div class='add'>+		DML_ASSERT(urg_bandwidth_required_flip[eval_state][n] &gt;= non_urg_bandwidth_required_flip[eval_state][n]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*frac_urg_bandwidth_flip = (frac_urg_bw_flip_sdp &gt; frac_urg_bw_flip_dram) ? frac_urg_bw_flip_sdp : frac_urg_bw_flip_dram;</div><div class='add'>+	*flip_bandwidth_support_ok &amp;= (*frac_urg_bandwidth_flip &lt;= 1.0);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: eval_state = %s\n", __func__, dml2_core_internal_soc_state_type_str(eval_state));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bw_flip_sdp = %f\n", __func__, frac_urg_bw_flip_sdp);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bw_flip_dram = %f\n", __func__, frac_urg_bw_flip_dram);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: frac_urg_bandwidth_flip = %f\n", __func__, *frac_urg_bandwidth_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: flip_bandwidth_support_ok = %d\n", __func__, *flip_bandwidth_support_ok);</div><div class='add'>+</div><div class='add'>+	for (unsigned int m = 0; m &lt; dml2_core_internal_soc_state_max; m++) {</div><div class='add'>+		for (unsigned int n = 0; n &lt; dml2_core_internal_bw_max; n++) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: state:%s bw_type:%s, urg_bandwidth_available=%f %s urg_bandwidth_required=%f\n",</div><div class='add'>+			__func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n),</div><div class='add'>+			urg_bandwidth_available[m][n], (urg_bandwidth_available[m][n] &lt; urg_bandwidth_required_flip[m][n]) ? "&lt;" : "&gt;=", urg_bandwidth_required_flip[m][n]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateFlipSchedule(</div><div class='add'>+	struct dml2_core_internal_scratch *s,</div><div class='add'>+	bool iflip_enable,</div><div class='add'>+	bool use_lb_flip_bw,</div><div class='add'>+	double HostVMInefficiencyFactor,</div><div class='add'>+	double Tvm_trips_flip,</div><div class='add'>+	double Tr0_trips_flip,</div><div class='add'>+	double Tvm_trips_flip_rounded,</div><div class='add'>+	double Tr0_trips_flip_rounded,</div><div class='add'>+	bool GPUVMEnable,</div><div class='add'>+	double vm_bytes, // vm_bytes</div><div class='add'>+	double DPTEBytesPerRow, // dpte_row_bytes</div><div class='add'>+	double BandwidthAvailableForImmediateFlip,</div><div class='add'>+	unsigned int TotImmediateFlipBytes,</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat,</div><div class='add'>+	double LineTime,</div><div class='add'>+	double VRatio,</div><div class='add'>+	double VRatioChroma,</div><div class='add'>+	double Tno_bw_flip,</div><div class='add'>+	unsigned int dpte_row_height,</div><div class='add'>+	unsigned int dpte_row_height_chroma,</div><div class='add'>+	bool use_one_row_for_frame_flip,</div><div class='add'>+	unsigned int max_flip_time_us,</div><div class='add'>+	unsigned int max_flip_time_lines,</div><div class='add'>+	unsigned int per_pipe_flip_bytes,</div><div class='add'>+	unsigned int meta_row_bytes,</div><div class='add'>+	unsigned int meta_row_height,</div><div class='add'>+	unsigned int meta_row_height_chroma,</div><div class='add'>+	bool dcc_mrq_enable,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *dst_y_per_vm_flip,</div><div class='add'>+	double *dst_y_per_row_flip,</div><div class='add'>+	double *final_flip_bw,</div><div class='add'>+	bool *ImmediateFlipSupportedForPipe)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_shared_CalculateFlipSchedule_locals *l = &amp;s-&gt;CalculateFlipSchedule_locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;dual_plane = dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha;</div><div class='add'>+	l-&gt;dpte_row_bytes = DPTEBytesPerRow;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GPUVMEnable = %u\n", __func__, GPUVMEnable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ip.max_flip_time_us = %d\n", __func__, max_flip_time_us);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ip.max_flip_time_lines = %d\n", __func__, max_flip_time_lines);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: BandwidthAvailableForImmediateFlip = %f\n", __func__, BandwidthAvailableForImmediateFlip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotImmediateFlipBytes = %u\n", __func__, TotImmediateFlipBytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: use_lb_flip_bw = %u\n", __func__, use_lb_flip_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: iflip_enable = %u\n", __func__, iflip_enable);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, LineTime);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tno_bw_flip = %f\n", __func__, Tno_bw_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_trips_flip = %f\n", __func__, Tvm_trips_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_trips_flip = %f\n", __func__, Tr0_trips_flip);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tvm_trips_flip_rounded = %f\n", __func__, Tvm_trips_flip_rounded);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Tr0_trips_flip_rounded = %f\n", __func__, Tr0_trips_flip_rounded);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vm_bytes = %f\n", __func__, vm_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DPTEBytesPerRow = %f\n", __func__, DPTEBytesPerRow);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_row_bytes = %d\n", __func__, meta_row_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_bytes = %f\n", __func__, l-&gt;dpte_row_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dpte_row_height = %d\n", __func__, dpte_row_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: meta_row_height = %d\n", __func__, meta_row_height);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VRatio = %f\n", __func__, VRatio);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (TotImmediateFlipBytes &gt; 0 &amp;&amp; (GPUVMEnable || dcc_mrq_enable)) {</div><div class='add'>+		if (l-&gt;dual_plane) {</div><div class='add'>+			if (dcc_mrq_enable &amp; GPUVMEnable) {</div><div class='add'>+				l-&gt;min_row_height = math_min2(dpte_row_height, meta_row_height);</div><div class='add'>+				l-&gt;min_row_height_chroma = math_min2(dpte_row_height_chroma, meta_row_height_chroma);</div><div class='add'>+			} else if (GPUVMEnable) {</div><div class='add'>+				l-&gt;min_row_height = dpte_row_height;</div><div class='add'>+				l-&gt;min_row_height_chroma = dpte_row_height_chroma;</div><div class='add'>+			} else {</div><div class='add'>+				l-&gt;min_row_height = meta_row_height;</div><div class='add'>+				l-&gt;min_row_height_chroma = meta_row_height_chroma;</div><div class='add'>+			}</div><div class='add'>+			l-&gt;min_row_time = math_min2(l-&gt;min_row_height * LineTime / VRatio, l-&gt;min_row_height_chroma * LineTime / VRatioChroma);</div><div class='add'>+		} else {</div><div class='add'>+			if (dcc_mrq_enable &amp; GPUVMEnable)</div><div class='add'>+				l-&gt;min_row_height = math_min2(dpte_row_height, meta_row_height);</div><div class='add'>+			else if (GPUVMEnable)</div><div class='add'>+				l-&gt;min_row_height = dpte_row_height;</div><div class='add'>+			else</div><div class='add'>+				l-&gt;min_row_height = meta_row_height;</div><div class='add'>+</div><div class='add'>+			l-&gt;min_row_time = l-&gt;min_row_height * LineTime / VRatio;</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min_row_time = %f\n", __func__, l-&gt;min_row_time);</div><div class='add'>+#endif</div><div class='add'>+		DML_ASSERT(l-&gt;min_row_time &gt; 0);</div><div class='add'>+</div><div class='add'>+		if (use_lb_flip_bw) {</div><div class='add'>+			// For mode check, calculation the flip bw requirement with worst case flip time</div><div class='add'>+			l-&gt;max_flip_time = math_min2(math_min2(l-&gt;min_row_time, (double)max_flip_time_lines * LineTime / VRatio),</div><div class='add'>+				math_max2(Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded, (double)max_flip_time_us));</div><div class='add'>+</div><div class='add'>+			//The lower bound on flip bandwidth</div><div class='add'>+			// Note: The get_urgent_bandwidth_required already consider dpte_row_bw and meta_row_bw in bandwidth calculation, so leave final_flip_bw = 0 if iflip not required</div><div class='add'>+			l-&gt;lb_flip_bw = 0;</div><div class='add'>+</div><div class='add'>+			if (iflip_enable) {</div><div class='add'>+				l-&gt;hvm_scaled_vm_bytes = vm_bytes * HostVMInefficiencyFactor;</div><div class='add'>+				l-&gt;num_rows = 2;</div><div class='add'>+				l-&gt;hvm_scaled_row_bytes = (l-&gt;num_rows * l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + l-&gt;num_rows * meta_row_bytes);</div><div class='add'>+				l-&gt;hvm_scaled_vm_row_bytes = l-&gt;hvm_scaled_vm_bytes + l-&gt;hvm_scaled_row_bytes;</div><div class='add'>+				l-&gt;lb_flip_bw = math_max3(</div><div class='add'>+					l-&gt;hvm_scaled_vm_row_bytes / (l-&gt;max_flip_time - Tno_bw_flip),</div><div class='add'>+					l-&gt;hvm_scaled_vm_bytes / (l-&gt;max_flip_time - Tno_bw_flip - 2 * Tr0_trips_flip_rounded),</div><div class='add'>+					l-&gt;hvm_scaled_row_bytes / (l-&gt;max_flip_time - Tvm_trips_flip_rounded));</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: max_flip_time = %f\n", __func__, l-&gt;max_flip_time);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: total vm bytes (hvm ineff scaled) = %f\n", __func__, l-&gt;hvm_scaled_vm_bytes);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: total row bytes (%f row, hvm ineff scaled) = %f\n", __func__, l-&gt;num_rows, l-&gt;hvm_scaled_row_bytes);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: total vm+row bytes (hvm ineff scaled) = %f\n", __func__, l-&gt;hvm_scaled_vm_row_bytes);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: lb_flip_bw for vm and row = %f\n", __func__, l-&gt;hvm_scaled_vm_row_bytes / (l-&gt;max_flip_time - Tno_bw_flip));</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: lb_flip_bw for vm = %f\n", __func__, l-&gt;hvm_scaled_vm_bytes / (l-&gt;max_flip_time - Tno_bw_flip - 2 * Tr0_trips_flip_rounded));</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: lb_flip_bw for row = %f\n", __func__, l-&gt;hvm_scaled_row_bytes / (l-&gt;max_flip_time - Tvm_trips_flip_rounded));</div><div class='add'>+</div><div class='add'>+				if (l-&gt;lb_flip_bw &gt; 0) {</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: mode_support est Tvm_flip = %f (bw-based)\n", __func__, Tno_bw_flip + l-&gt;hvm_scaled_vm_bytes / l-&gt;lb_flip_bw);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: mode_support est Tr0_flip = %f (bw-based)\n", __func__, l-&gt;hvm_scaled_row_bytes / l-&gt;lb_flip_bw / l-&gt;num_rows);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: mode_support est dst_y_per_vm_flip = %f (bw-based)\n", __func__, Tno_bw_flip + l-&gt;hvm_scaled_vm_bytes / l-&gt;lb_flip_bw / LineTime);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: mode_support est dst_y_per_row_flip = %f (bw-based)\n", __func__, l-&gt;hvm_scaled_row_bytes / l-&gt;lb_flip_bw / LineTime / l-&gt;num_rows);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: Tvm_trips_flip_rounded + 2*Tr0_trips_flip_rounded = %f\n", __func__, (Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded));</div><div class='add'>+				}</div><div class='add'>+#endif</div><div class='add'>+				l-&gt;lb_flip_bw = math_max3(l-&gt;lb_flip_bw,</div><div class='add'>+						l-&gt;hvm_scaled_vm_bytes / (31 * LineTime) - Tno_bw_flip,</div><div class='add'>+						(l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + meta_row_bytes) / (15 * LineTime));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: lb_flip_bw for vm reg limit = %f\n", __func__, l-&gt;hvm_scaled_vm_bytes / (31 * LineTime) - Tno_bw_flip);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: lb_flip_bw for row reg limit = %f\n", __func__, (l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + meta_row_bytes) / (15 * LineTime));</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			*final_flip_bw = l-&gt;lb_flip_bw;</div><div class='add'>+</div><div class='add'>+			*dst_y_per_vm_flip = 1; // not used</div><div class='add'>+			*dst_y_per_row_flip = 1; // not used</div><div class='add'>+			*ImmediateFlipSupportedForPipe = l-&gt;min_row_time &gt;= (Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded);</div><div class='add'>+		} else {</div><div class='add'>+			if (iflip_enable) {</div><div class='add'>+				l-&gt;ImmediateFlipBW = (double)per_pipe_flip_bytes * BandwidthAvailableForImmediateFlip / (double)TotImmediateFlipBytes; // flip_bw(i)</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: per_pipe_flip_bytes = %d\n", __func__, per_pipe_flip_bytes);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: BandwidthAvailableForImmediateFlip = %f\n", __func__, BandwidthAvailableForImmediateFlip);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: ImmediateFlipBW = %f\n", __func__, l-&gt;ImmediateFlipBW);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: portion of flip bw = %f\n", __func__, (double)per_pipe_flip_bytes / (double)TotImmediateFlipBytes);</div><div class='add'>+#endif</div><div class='add'>+				if (l-&gt;ImmediateFlipBW == 0) {</div><div class='add'>+					l-&gt;Tvm_flip = 0;</div><div class='add'>+					l-&gt;Tr0_flip = 0;</div><div class='add'>+				} else {</div><div class='add'>+					l-&gt;Tvm_flip = math_max3(Tvm_trips_flip,</div><div class='add'>+						Tno_bw_flip + vm_bytes * HostVMInefficiencyFactor / l-&gt;ImmediateFlipBW,</div><div class='add'>+						LineTime / 4.0);</div><div class='add'>+</div><div class='add'>+					l-&gt;Tr0_flip = math_max3(Tr0_trips_flip,</div><div class='add'>+						(l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + meta_row_bytes) / l-&gt;ImmediateFlipBW,</div><div class='add'>+						LineTime / 4.0);</div><div class='add'>+				}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: total vm bytes (hvm ineff scaled) = %f\n", __func__, vm_bytes * HostVMInefficiencyFactor);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: total row bytes (hvm ineff scaled, one row) = %f\n", __func__, (l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + meta_row_bytes));</div><div class='add'>+</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Tvm_flip = %f (bw-based), Tvm_trips_flip = %f (latency-based)\n", __func__, Tno_bw_flip + vm_bytes * HostVMInefficiencyFactor / l-&gt;ImmediateFlipBW, Tvm_trips_flip);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Tr0_flip = %f (bw-based), Tr0_trips_flip = %f (latency-based)\n", __func__, (l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + meta_row_bytes) / l-&gt;ImmediateFlipBW, Tr0_trips_flip);</div><div class='add'>+#endif</div><div class='add'>+				*dst_y_per_vm_flip = math_ceil2(4.0 * (l-&gt;Tvm_flip / LineTime), 1.0) / 4.0;</div><div class='add'>+				*dst_y_per_row_flip = math_ceil2(4.0 * (l-&gt;Tr0_flip / LineTime), 1.0) / 4.0;</div><div class='add'>+</div><div class='add'>+				*final_flip_bw = math_max2(vm_bytes * HostVMInefficiencyFactor / (*dst_y_per_vm_flip * LineTime),</div><div class='add'>+					(l-&gt;dpte_row_bytes * HostVMInefficiencyFactor + meta_row_bytes) / (*dst_y_per_row_flip * LineTime));</div><div class='add'>+</div><div class='add'>+				if (*dst_y_per_vm_flip &gt;= 32 || *dst_y_per_row_flip &gt;= 16 || l-&gt;Tvm_flip + 2 * l-&gt;Tr0_flip &gt; l-&gt;min_row_time) {</div><div class='add'>+					*ImmediateFlipSupportedForPipe = false;</div><div class='add'>+				} else {</div><div class='add'>+					*ImmediateFlipSupportedForPipe = iflip_enable;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				l-&gt;Tvm_flip = 0;</div><div class='add'>+				l-&gt;Tr0_flip = 0;</div><div class='add'>+				*dst_y_per_vm_flip = 0;</div><div class='add'>+				*dst_y_per_row_flip = 0;</div><div class='add'>+				*final_flip_bw = 0;</div><div class='add'>+				*ImmediateFlipSupportedForPipe = iflip_enable;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		l-&gt;Tvm_flip = 0;</div><div class='add'>+		l-&gt;Tr0_flip = 0;</div><div class='add'>+		*dst_y_per_vm_flip = 0;</div><div class='add'>+		*dst_y_per_row_flip = 0;</div><div class='add'>+		*final_flip_bw = 0;</div><div class='add'>+		*ImmediateFlipSupportedForPipe = iflip_enable;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	if (!use_lb_flip_bw) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_per_vm_flip = %f (should be &lt; 32)\n", __func__, *dst_y_per_vm_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: dst_y_per_row_flip = %f (should be &lt; 16)\n", __func__, *dst_y_per_row_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_flip = %f (final)\n", __func__, l-&gt;Tvm_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tr0_flip = %f (final)\n", __func__, l-&gt;Tr0_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Tvm_flip + 2*Tr0_flip = %f (should be &lt;= min_row_time=%f)\n", __func__, l-&gt;Tvm_flip + 2 * l-&gt;Tr0_flip, l-&gt;min_row_time);</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: final_flip_bw = %f\n", __func__, *final_flip_bw);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ImmediateFlipSupportedForPipe = %u\n", __func__, *ImmediateFlipSupportedForPipe);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(</div><div class='add'>+	struct dml2_core_internal_scratch *scratch,</div><div class='add'>+	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *p)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals *s = &amp;scratch-&gt;CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;</div><div class='add'>+</div><div class='add'>+	enum dml2_uclk_pstate_change_strategy uclk_pstate_change_strategy;</div><div class='add'>+	double reserved_vblank_time_us;</div><div class='add'>+	bool FoundCriticalSurface = false;</div><div class='add'>+</div><div class='add'>+	s-&gt;TotalActiveWriteback = 0;</div><div class='add'>+	p-&gt;Watermark-&gt;UrgentWatermark = p-&gt;mmSOCParameters.UrgentLatency + p-&gt;mmSOCParameters.ExtraLatency;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentWatermark = %f\n", __func__, p-&gt;Watermark-&gt;UrgentWatermark);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	p-&gt;Watermark-&gt;USRRetrainingWatermark = p-&gt;mmSOCParameters.UrgentLatency + p-&gt;mmSOCParameters.ExtraLatency + p-&gt;mmSOCParameters.USRRetrainingLatency + p-&gt;mmSOCParameters.SMNLatency;</div><div class='add'>+	p-&gt;Watermark-&gt;DRAMClockChangeWatermark = p-&gt;mmSOCParameters.DRAMClockChangeLatency + p-&gt;Watermark-&gt;UrgentWatermark;</div><div class='add'>+	p-&gt;Watermark-&gt;FCLKChangeWatermark = p-&gt;mmSOCParameters.FCLKChangeLatency + p-&gt;Watermark-&gt;UrgentWatermark;</div><div class='add'>+	p-&gt;Watermark-&gt;StutterExitWatermark = p-&gt;mmSOCParameters.SRExitTime + p-&gt;mmSOCParameters.ExtraLatency_sr + 10 / p-&gt;DCFClkDeepSleep;</div><div class='add'>+	p-&gt;Watermark-&gt;StutterEnterPlusExitWatermark = p-&gt;mmSOCParameters.SREnterPlusExitTime + p-&gt;mmSOCParameters.ExtraLatency_sr + 10 / p-&gt;DCFClkDeepSleep;</div><div class='add'>+	p-&gt;Watermark-&gt;Z8StutterExitWatermark = p-&gt;mmSOCParameters.SRExitZ8Time + p-&gt;mmSOCParameters.ExtraLatency_sr + 10 / p-&gt;DCFClkDeepSleep;</div><div class='add'>+	p-&gt;Watermark-&gt;Z8StutterEnterPlusExitWatermark = p-&gt;mmSOCParameters.SREnterPlusExitZ8Time + p-&gt;mmSOCParameters.ExtraLatency_sr + 10 / p-&gt;DCFClkDeepSleep;</div><div class='add'>+	if (p-&gt;mmSOCParameters.qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		p-&gt;Watermark-&gt;StutterExitWatermark += p-&gt;mmSOCParameters.max_urgent_latency_us + p-&gt;mmSOCParameters.df_response_time_us;</div><div class='add'>+		p-&gt;Watermark-&gt;StutterEnterPlusExitWatermark += p-&gt;mmSOCParameters.max_urgent_latency_us + p-&gt;mmSOCParameters.df_response_time_us;</div><div class='add'>+		p-&gt;Watermark-&gt;Z8StutterExitWatermark += p-&gt;mmSOCParameters.max_urgent_latency_us + p-&gt;mmSOCParameters.df_response_time_us;</div><div class='add'>+		p-&gt;Watermark-&gt;Z8StutterEnterPlusExitWatermark += p-&gt;mmSOCParameters.max_urgent_latency_us + p-&gt;mmSOCParameters.df_response_time_us;</div><div class='add'>+	}</div><div class='add'>+	p-&gt;Watermark-&gt;temp_read_or_ppt_watermark_us = p-&gt;mmSOCParameters.g6_temp_read_blackout_us + p-&gt;Watermark-&gt;UrgentWatermark;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentLatency = %f\n", __func__, p-&gt;mmSOCParameters.UrgentLatency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ExtraLatency = %f\n", __func__, p-&gt;mmSOCParameters.ExtraLatency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DRAMClockChangeLatency = %f\n", __func__, p-&gt;mmSOCParameters.DRAMClockChangeLatency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SREnterPlusExitZ8Time = %f\n", __func__, p-&gt;mmSOCParameters.SREnterPlusExitZ8Time);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SREnterPlusExitTime = %f\n", __func__, p-&gt;mmSOCParameters.SREnterPlusExitTime);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UrgentWatermark = %f\n", __func__, p-&gt;Watermark-&gt;UrgentWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: USRRetrainingWatermark = %f\n", __func__, p-&gt;Watermark-&gt;USRRetrainingWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, p-&gt;Watermark-&gt;DRAMClockChangeWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FCLKChangeWatermark = %f\n", __func__, p-&gt;Watermark-&gt;FCLKChangeWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterExitWatermark = %f\n", __func__, p-&gt;Watermark-&gt;StutterExitWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, p-&gt;Watermark-&gt;StutterEnterPlusExitWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8StutterExitWatermark = %f\n", __func__, p-&gt;Watermark-&gt;Z8StutterExitWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, p-&gt;Watermark-&gt;Z8StutterEnterPlusExitWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: temp_read_or_ppt_watermark_us = %f\n", __func__, p-&gt;Watermark-&gt;temp_read_or_ppt_watermark_us);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	s-&gt;TotalActiveWriteback = 0;</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			s-&gt;TotalActiveWriteback = s-&gt;TotalActiveWriteback + 1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (s-&gt;TotalActiveWriteback &lt;= 1) {</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackUrgentWatermark = p-&gt;mmSOCParameters.WritebackLatency;</div><div class='add'>+	} else {</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackUrgentWatermark = p-&gt;mmSOCParameters.WritebackLatency + p-&gt;WritebackChunkSize * 1024.0 / 32.0 / p-&gt;SOCCLK;</div><div class='add'>+	}</div><div class='add'>+	if (p-&gt;USRRetrainingRequired)</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackUrgentWatermark = p-&gt;Watermark-&gt;WritebackUrgentWatermark + p-&gt;mmSOCParameters.USRRetrainingLatency;</div><div class='add'>+</div><div class='add'>+	if (s-&gt;TotalActiveWriteback &lt;= 1) {</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackDRAMClockChangeWatermark = p-&gt;mmSOCParameters.DRAMClockChangeLatency + p-&gt;mmSOCParameters.WritebackLatency;</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackFCLKChangeWatermark = p-&gt;mmSOCParameters.FCLKChangeLatency + p-&gt;mmSOCParameters.WritebackLatency;</div><div class='add'>+	} else {</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackDRAMClockChangeWatermark = p-&gt;mmSOCParameters.DRAMClockChangeLatency + p-&gt;mmSOCParameters.WritebackLatency + p-&gt;WritebackChunkSize * 1024.0 / 32.0 / p-&gt;SOCCLK;</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackFCLKChangeWatermark = p-&gt;mmSOCParameters.FCLKChangeLatency + p-&gt;mmSOCParameters.WritebackLatency + p-&gt;WritebackChunkSize * 1024 / 32 / p-&gt;SOCCLK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p-&gt;USRRetrainingRequired)</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackDRAMClockChangeWatermark = p-&gt;Watermark-&gt;WritebackDRAMClockChangeWatermark + p-&gt;mmSOCParameters.USRRetrainingLatency;</div><div class='add'>+</div><div class='add'>+	if (p-&gt;USRRetrainingRequired)</div><div class='add'>+		p-&gt;Watermark-&gt;WritebackFCLKChangeWatermark = p-&gt;Watermark-&gt;WritebackFCLKChangeWatermark + p-&gt;mmSOCParameters.USRRetrainingLatency;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: WritebackDRAMClockChangeWatermark = %f\n", __func__, p-&gt;Watermark-&gt;WritebackDRAMClockChangeWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, p-&gt;Watermark-&gt;WritebackFCLKChangeWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: WritebackUrgentWatermark = %f\n", __func__, p-&gt;Watermark-&gt;WritebackUrgentWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: USRRetrainingRequired = %u\n", __func__, p-&gt;USRRetrainingRequired);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: USRRetrainingLatency = %f\n", __func__, p-&gt;mmSOCParameters.USRRetrainingLatency);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	s-&gt;TotalPixelBW = 0.0;</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		double h_total = (double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+		double pixel_clock_mhz = p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;</div><div class='add'>+		double v_ratio = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		double v_ratio_c = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		s-&gt;TotalPixelBW = s-&gt;TotalPixelBW + p-&gt;DPPPerSurface[k]</div><div class='add'>+			* (p-&gt;SwathWidthY[k] * p-&gt;BytePerPixelDETY[k] * v_ratio + p-&gt;SwathWidthC[k] * p-&gt;BytePerPixelDETC[k] * v_ratio_c) / (h_total / pixel_clock_mhz);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;global_fclk_change_supported = true;</div><div class='add'>+	*p-&gt;global_dram_clock_change_supported = true;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		double h_total = (double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+		double pixel_clock_mhz = p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;</div><div class='add'>+		double v_ratio = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		double v_ratio_c = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		double v_taps = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps;</div><div class='add'>+		double v_taps_c = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps;</div><div class='add'>+		double h_ratio = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio;</div><div class='add'>+		double h_ratio_c = p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio;</div><div class='add'>+		double LBBitPerPixel = 57;</div><div class='add'>+</div><div class='add'>+		s-&gt;LBLatencyHidingSourceLinesY[k] = (unsigned int)(math_min2((double)p-&gt;MaxLineBufferLines, math_floor2((double)p-&gt;LineBufferSize / LBBitPerPixel / ((double)p-&gt;SwathWidthY[k] / math_max2(h_ratio, 1.0)), 1)) - (v_taps - 1));</div><div class='add'>+		s-&gt;LBLatencyHidingSourceLinesC[k] = (unsigned int)(math_min2((double)p-&gt;MaxLineBufferLines, math_floor2((double)p-&gt;LineBufferSize / LBBitPerPixel / ((double)p-&gt;SwathWidthC[k] / math_max2(h_ratio_c, 1.0)), 1)) - (v_taps_c - 1));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, MaxLineBufferLines = %u\n", __func__, k, p-&gt;MaxLineBufferLines);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, LineBufferSize = %u\n", __func__, k, p-&gt;LineBufferSize);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, LBBitPerPixel = %f\n", __func__, k, LBBitPerPixel);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, HRatio = %f\n", __func__, k, h_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, VTaps = %f\n", __func__, k, v_taps);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		s-&gt;EffectiveLBLatencyHidingY = s-&gt;LBLatencyHidingSourceLinesY[k] / v_ratio * (h_total / pixel_clock_mhz);</div><div class='add'>+		s-&gt;EffectiveLBLatencyHidingC = s-&gt;LBLatencyHidingSourceLinesC[k] / v_ratio_c * (h_total / pixel_clock_mhz);</div><div class='add'>+</div><div class='add'>+		s-&gt;EffectiveDETBufferSizeY = p-&gt;DETBufferSizeY[k];</div><div class='add'>+		if (p-&gt;UnboundedRequestEnabled) {</div><div class='add'>+			s-&gt;EffectiveDETBufferSizeY = s-&gt;EffectiveDETBufferSizeY + p-&gt;CompressedBufferSizeInkByte * 1024 * (p-&gt;SwathWidthY[k] * p-&gt;BytePerPixelDETY[k] * v_ratio) / (h_total / pixel_clock_mhz) / s-&gt;TotalPixelBW;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		s-&gt;LinesInDETY[k] = (double)s-&gt;EffectiveDETBufferSizeY / p-&gt;BytePerPixelDETY[k] / p-&gt;SwathWidthY[k];</div><div class='add'>+		s-&gt;LinesInDETYRoundedDownToSwath[k] = (unsigned int)(math_floor2(s-&gt;LinesInDETY[k], p-&gt;SwathHeightY[k]));</div><div class='add'>+		s-&gt;FullDETBufferingTimeY = s-&gt;LinesInDETYRoundedDownToSwath[k] * (h_total / pixel_clock_mhz) / v_ratio;</div><div class='add'>+</div><div class='add'>+		s-&gt;ActiveClockChangeLatencyHidingY = s-&gt;EffectiveLBLatencyHidingY + s-&gt;FullDETBufferingTimeY - ((double)p-&gt;DSTXAfterScaler[k] / h_total + (double)p-&gt;DSTYAfterScaler[k]) * h_total / pixel_clock_mhz;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;NumberOfActiveSurfaces &gt; 1) {</div><div class='add'>+			s-&gt;ActiveClockChangeLatencyHidingY = s-&gt;ActiveClockChangeLatencyHidingY - (1.0 - 1.0 / (double)p-&gt;NumberOfActiveSurfaces) * (double)p-&gt;SwathHeightY[k] * (double)h_total / pixel_clock_mhz / v_ratio;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;BytePerPixelDETC[k] &gt; 0) {</div><div class='add'>+			s-&gt;LinesInDETC[k] = p-&gt;DETBufferSizeC[k] / p-&gt;BytePerPixelDETC[k] / p-&gt;SwathWidthC[k];</div><div class='add'>+			s-&gt;LinesInDETCRoundedDownToSwath[k] = (unsigned int)(math_floor2(s-&gt;LinesInDETC[k], p-&gt;SwathHeightC[k]));</div><div class='add'>+			s-&gt;FullDETBufferingTimeC = s-&gt;LinesInDETCRoundedDownToSwath[k] * (h_total / pixel_clock_mhz) / v_ratio_c;</div><div class='add'>+			s-&gt;ActiveClockChangeLatencyHidingC = s-&gt;EffectiveLBLatencyHidingC + s-&gt;FullDETBufferingTimeC - ((double)p-&gt;DSTXAfterScaler[k] / (double)h_total + (double)p-&gt;DSTYAfterScaler[k]) * (double)h_total / pixel_clock_mhz;</div><div class='add'>+			if (p-&gt;NumberOfActiveSurfaces &gt; 1) {</div><div class='add'>+				s-&gt;ActiveClockChangeLatencyHidingC = s-&gt;ActiveClockChangeLatencyHidingC - (1.0 - 1.0 / (double)p-&gt;NumberOfActiveSurfaces) * (double)p-&gt;SwathHeightC[k] * (double)h_total / pixel_clock_mhz / v_ratio_c;</div><div class='add'>+			}</div><div class='add'>+			s-&gt;ActiveClockChangeLatencyHiding = math_min2(s-&gt;ActiveClockChangeLatencyHidingY, s-&gt;ActiveClockChangeLatencyHidingC);</div><div class='add'>+		} else {</div><div class='add'>+			s-&gt;ActiveClockChangeLatencyHiding = s-&gt;ActiveClockChangeLatencyHidingY;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		s-&gt;ActiveDRAMClockChangeLatencyMargin[k] = s-&gt;ActiveClockChangeLatencyHiding - p-&gt;Watermark-&gt;DRAMClockChangeWatermark;</div><div class='add'>+		s-&gt;ActiveFCLKChangeLatencyMargin[k] = s-&gt;ActiveClockChangeLatencyHiding - p-&gt;Watermark-&gt;FCLKChangeWatermark;</div><div class='add'>+		s-&gt;USRRetrainingLatencyMargin[k] = s-&gt;ActiveClockChangeLatencyHiding - p-&gt;Watermark-&gt;USRRetrainingWatermark;</div><div class='add'>+		s-&gt;g6_temp_read_latency_margin[k] = s-&gt;ActiveClockChangeLatencyHiding - p-&gt;Watermark-&gt;temp_read_or_ppt_watermark_us;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;VActiveLatencyHidingMargin)</div><div class='add'>+			p-&gt;VActiveLatencyHidingMargin[k] = s-&gt;ActiveDRAMClockChangeLatencyMargin[k];</div><div class='add'>+</div><div class='add'>+		if (p-&gt;VActiveLatencyHidingUs)</div><div class='add'>+			p-&gt;VActiveLatencyHidingUs[k] = s-&gt;ActiveClockChangeLatencyHiding;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			s-&gt;WritebackLatencyHiding = (double)p-&gt;WritebackInterfaceBufferSize * 1024.0</div><div class='add'>+				/ ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height</div><div class='add'>+					* (double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width</div><div class='add'>+					/ ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height * (double)h_total / pixel_clock_mhz) * 4.0);</div><div class='add'>+			if (p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {</div><div class='add'>+				s-&gt;WritebackLatencyHiding = s-&gt;WritebackLatencyHiding / 2;</div><div class='add'>+			}</div><div class='add'>+			s-&gt;WritebackDRAMClockChangeLatencyMargin = s-&gt;WritebackLatencyHiding - p-&gt;Watermark-&gt;WritebackDRAMClockChangeWatermark;</div><div class='add'>+</div><div class='add'>+			s-&gt;WritebackFCLKChangeLatencyMargin = s-&gt;WritebackLatencyHiding - p-&gt;Watermark-&gt;WritebackFCLKChangeWatermark;</div><div class='add'>+</div><div class='add'>+			s-&gt;ActiveDRAMClockChangeLatencyMargin[k] = math_min2(s-&gt;ActiveDRAMClockChangeLatencyMargin[k], s-&gt;WritebackDRAMClockChangeLatencyMargin);</div><div class='add'>+			s-&gt;ActiveFCLKChangeLatencyMargin[k] = math_min2(s-&gt;ActiveFCLKChangeLatencyMargin[k], s-&gt;WritebackFCLKChangeLatencyMargin);</div><div class='add'>+		}</div><div class='add'>+		p-&gt;MaxActiveDRAMClockChangeLatencySupported[k] = dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k]) ? 0 : (s-&gt;ActiveDRAMClockChangeLatencyMargin[k] + p-&gt;mmSOCParameters.DRAMClockChangeLatency);</div><div class='add'>+</div><div class='add'>+		uclk_pstate_change_strategy = p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.uclk_pstate_change_strategy;</div><div class='add'>+		reserved_vblank_time_us = (double)p-&gt;display_cfg-&gt;plane_descriptors[k].overrides.reserved_vblank_time_ns / 1000;</div><div class='add'>+</div><div class='add'>+		p-&gt;FCLKChangeSupport[k] = dml2_pstate_change_unsupported;</div><div class='add'>+		if (s-&gt;ActiveFCLKChangeLatencyMargin[k] &gt; 0)</div><div class='add'>+			p-&gt;FCLKChangeSupport[k] = dml2_pstate_change_vactive;</div><div class='add'>+		else if (reserved_vblank_time_us &gt;= p-&gt;mmSOCParameters.FCLKChangeLatency)</div><div class='add'>+			p-&gt;FCLKChangeSupport[k] = dml2_pstate_change_vblank;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;FCLKChangeSupport[k] == dml2_pstate_change_unsupported)</div><div class='add'>+			*p-&gt;global_fclk_change_supported = false;</div><div class='add'>+</div><div class='add'>+		p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_unsupported;</div><div class='add'>+		if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_auto) {</div><div class='add'>+			if (p-&gt;display_cfg-&gt;overrides.all_streams_blanked ||</div><div class='add'>+					(s-&gt;ActiveDRAMClockChangeLatencyMargin[k] &gt; 0 &amp;&amp; reserved_vblank_time_us &gt;= p-&gt;mmSOCParameters.DRAMClockChangeLatency))</div><div class='add'>+				p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_vblank_and_vactive;</div><div class='add'>+			else if (s-&gt;ActiveDRAMClockChangeLatencyMargin[k] &gt; 0)</div><div class='add'>+				p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_vactive;</div><div class='add'>+			else if (reserved_vblank_time_us &gt;= p-&gt;mmSOCParameters.DRAMClockChangeLatency)</div><div class='add'>+				p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_vblank;</div><div class='add'>+		} else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_vactive &amp;&amp; s-&gt;ActiveDRAMClockChangeLatencyMargin[k] &gt; 0)</div><div class='add'>+			p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_vactive;</div><div class='add'>+		else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_vblank &amp;&amp; reserved_vblank_time_us &gt;= p-&gt;mmSOCParameters.DRAMClockChangeLatency)</div><div class='add'>+			p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_vblank;</div><div class='add'>+		else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_drr)</div><div class='add'>+			p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_drr;</div><div class='add'>+		else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_svp)</div><div class='add'>+			p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_mall_svp;</div><div class='add'>+		else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame)</div><div class='add'>+			p-&gt;DRAMClockChangeSupport[k] = dml2_pstate_change_mall_full_frame;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;DRAMClockChangeSupport[k] == dml2_pstate_change_unsupported)</div><div class='add'>+			*p-&gt;global_dram_clock_change_supported = false;</div><div class='add'>+</div><div class='add'>+		s-&gt;dst_y_pstate = (unsigned int)(math_ceil2((p-&gt;mmSOCParameters.DRAMClockChangeLatency + p-&gt;mmSOCParameters.UrgentLatency) / (h_total / pixel_clock_mhz), 1));</div><div class='add'>+		s-&gt;src_y_pstate_l = (unsigned int)(math_ceil2(s-&gt;dst_y_pstate * v_ratio, p-&gt;SwathHeightY[k]));</div><div class='add'>+		s-&gt;src_y_ahead_l = (unsigned int)(math_floor2(p-&gt;DETBufferSizeY[k] / p-&gt;BytePerPixelDETY[k] / p-&gt;SwathWidthY[k], p-&gt;SwathHeightY[k]) + s-&gt;LBLatencyHidingSourceLinesY[k]);</div><div class='add'>+		s-&gt;sub_vp_lines_l = s-&gt;src_y_pstate_l + s-&gt;src_y_ahead_l + p-&gt;meta_row_height_l[k];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p-&gt;DETBufferSizeY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p-&gt;BytePerPixelDETY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p-&gt;SwathWidthY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, SwathHeightY = %u\n", __func__, k, p-&gt;SwathHeightY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, LBLatencyHidingSourceLinesY = %u\n", __func__, k, s-&gt;LBLatencyHidingSourceLinesY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_pstate = %u\n", __func__, k, s-&gt;dst_y_pstate);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, src_y_pstate_l = %u\n", __func__, k, s-&gt;src_y_pstate_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, src_y_ahead_l = %u\n", __func__, k, s-&gt;src_y_ahead_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_height_l = %u\n", __func__, k, p-&gt;meta_row_height_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, sub_vp_lines_l = %u\n", __func__, k, s-&gt;sub_vp_lines_l);</div><div class='add'>+#endif</div><div class='add'>+		p-&gt;SubViewportLinesNeededInMALL[k] = s-&gt;sub_vp_lines_l;</div><div class='add'>+</div><div class='add'>+		if (p-&gt;BytePerPixelDETC[k] &gt; 0) {</div><div class='add'>+			s-&gt;src_y_pstate_c = (unsigned int)(math_ceil2(s-&gt;dst_y_pstate * v_ratio_c, p-&gt;SwathHeightC[k]));</div><div class='add'>+			s-&gt;src_y_ahead_c = (unsigned int)(math_floor2(p-&gt;DETBufferSizeC[k] / p-&gt;BytePerPixelDETC[k] / p-&gt;SwathWidthC[k], p-&gt;SwathHeightC[k]) + s-&gt;LBLatencyHidingSourceLinesC[k]);</div><div class='add'>+			s-&gt;sub_vp_lines_c = s-&gt;src_y_pstate_c + s-&gt;src_y_ahead_c + p-&gt;meta_row_height_c[k];</div><div class='add'>+</div><div class='add'>+			if (dml_is_420(p-&gt;display_cfg-&gt;plane_descriptors[k].pixel_format))</div><div class='add'>+				p-&gt;SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s-&gt;sub_vp_lines_l, 2 * s-&gt;sub_vp_lines_c));</div><div class='add'>+			else</div><div class='add'>+				p-&gt;SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s-&gt;sub_vp_lines_l, s-&gt;sub_vp_lines_c));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, k, p-&gt;meta_row_height_c[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s-&gt;src_y_pstate_c);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s-&gt;src_y_ahead_c);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s-&gt;sub_vp_lines_c);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*p-&gt;g6_temp_read_support = true;</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if ((!dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k])) &amp;&amp;</div><div class='add'>+			(s-&gt;g6_temp_read_latency_margin[k] &lt; 0)) {</div><div class='add'>+			*p-&gt;g6_temp_read_support = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if ((!dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k])) &amp;&amp; ((!FoundCriticalSurface)</div><div class='add'>+			|| ((s-&gt;ActiveFCLKChangeLatencyMargin[k] + p-&gt;mmSOCParameters.FCLKChangeLatency) &lt; *p-&gt;MaxActiveFCLKChangeLatencySupported))) {</div><div class='add'>+			FoundCriticalSurface = true;</div><div class='add'>+			*p-&gt;MaxActiveFCLKChangeLatencySupported = s-&gt;ActiveFCLKChangeLatencyMargin[k] + p-&gt;mmSOCParameters.FCLKChangeLatency;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DRAMClockChangeSupport = %u\n", __func__, *p-&gt;global_dram_clock_change_supported);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FCLKChangeSupport = %u\n", __func__, *p-&gt;global_fclk_change_supported);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxActiveFCLKChangeLatencySupported = %f\n", __func__, *p-&gt;MaxActiveFCLKChangeLatencySupported);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: USRRetrainingSupport = %u\n", __func__, *p-&gt;USRRetrainingSupport);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_bytes_to_fetch_required_to_hide_latency(</div><div class='add'>+		struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int dst_lines_to_hide;</div><div class='add'>+	unsigned int src_lines_to_hide_l;</div><div class='add'>+	unsigned int src_lines_to_hide_c;</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; p-&gt;num_active_planes; plane_index++) {</div><div class='add'>+		if (dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[plane_index]))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		stream_index = p-&gt;display_cfg-&gt;plane_descriptors[plane_index].stream_index;</div><div class='add'>+</div><div class='add'>+		dst_lines_to_hide = (unsigned int)math_ceil(p-&gt;latency_to_hide_us[0] /</div><div class='add'>+			((double)p-&gt;display_cfg-&gt;stream_descriptors[stream_index].timing.h_total /</div><div class='add'>+				(double)p-&gt;display_cfg-&gt;stream_descriptors[stream_index].timing.pixel_clock_khz * 1000.0));</div><div class='add'>+</div><div class='add'>+		src_lines_to_hide_l = (unsigned int)math_ceil2(p-&gt;display_cfg-&gt;plane_descriptors[plane_index].composition.scaler_info.plane0.v_ratio * dst_lines_to_hide,</div><div class='add'>+			p-&gt;swath_height_l[plane_index]);</div><div class='add'>+		p-&gt;bytes_required_l[plane_index] = src_lines_to_hide_l * p-&gt;num_of_dpp[plane_index] * p-&gt;swath_width_l[plane_index] * p-&gt;byte_per_pix_l[plane_index];</div><div class='add'>+</div><div class='add'>+		src_lines_to_hide_c = (unsigned int)math_ceil2(p-&gt;display_cfg-&gt;plane_descriptors[plane_index].composition.scaler_info.plane1.v_ratio * dst_lines_to_hide,</div><div class='add'>+			p-&gt;swath_height_c[plane_index]);</div><div class='add'>+		p-&gt;bytes_required_c[plane_index] = src_lines_to_hide_c * p-&gt;num_of_dpp[plane_index] * p-&gt;swath_width_c[plane_index] * p-&gt;byte_per_pix_c[plane_index];</div><div class='add'>+</div><div class='add'>+		if (p-&gt;display_cfg-&gt;plane_descriptors[plane_index].surface.dcc.enable &amp;&amp; p-&gt;mrq_present) {</div><div class='add'>+			p-&gt;bytes_required_l[plane_index] += (unsigned int)math_ceil((double)src_lines_to_hide_l / p-&gt;meta_row_height_l[plane_index]) * p-&gt;meta_row_bytes_per_row_ub_l[plane_index];</div><div class='add'>+			if (p-&gt;meta_row_height_c[plane_index]) {</div><div class='add'>+				p-&gt;bytes_required_c[plane_index] += (unsigned int)math_ceil((double)src_lines_to_hide_c / p-&gt;meta_row_height_c[plane_index]) * p-&gt;meta_row_bytes_per_row_ub_c[plane_index];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p-&gt;display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+			p-&gt;bytes_required_l[plane_index] += (unsigned int)math_ceil((double)src_lines_to_hide_l / p-&gt;dpte_row_height_l[plane_index]) * p-&gt;dpte_bytes_per_row_l[plane_index];</div><div class='add'>+			if (p-&gt;dpte_row_height_c[plane_index]) {</div><div class='add'>+				p-&gt;bytes_required_c[plane_index] += (unsigned int)math_ceil((double)src_lines_to_hide_c / p-&gt;dpte_row_height_c[plane_index]) * p-&gt;dpte_bytes_per_row_c[plane_index];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static noinline_for_stack void calculate_vactive_det_fill_latency(</div><div class='add'>+		const struct dml2_display_cfg *display_cfg,</div><div class='add'>+		unsigned int num_active_planes,</div><div class='add'>+		unsigned int bytes_required_l[],</div><div class='add'>+		unsigned int bytes_required_c[],</div><div class='add'>+		double dcc_dram_bw_nom_overhead_factor_p0[],</div><div class='add'>+		double dcc_dram_bw_nom_overhead_factor_p1[],</div><div class='add'>+		double surface_read_bw_l[],</div><div class='add'>+		double surface_read_bw_c[],</div><div class='add'>+		double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],</div><div class='add'>+		double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],</div><div class='add'>+		/* output */</div><div class='add'>+		double vactive_det_fill_delay_us[])</div><div class='add'>+{</div><div class='add'>+	double effective_excess_bandwidth;</div><div class='add'>+	double effective_excess_bandwidth_l;</div><div class='add'>+	double effective_excess_bandwidth_c;</div><div class='add'>+	double adj_factor;</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	unsigned int soc_state;</div><div class='add'>+	unsigned int bw_type;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; num_active_planes; plane_index++) {</div><div class='add'>+		if (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[plane_index]))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vactive_det_fill_delay_us[plane_index] = 0.0;</div><div class='add'>+		for (soc_state = 0; soc_state &lt; dml2_core_internal_soc_state_max; soc_state++) {</div><div class='add'>+			for (bw_type = 0; bw_type &lt; dml2_core_internal_bw_max; bw_type++) {</div><div class='add'>+				effective_excess_bandwidth = (surface_peak_required_bw[soc_state][bw_type][plane_index] - surface_avg_vactive_required_bw[soc_state][bw_type][plane_index]);</div><div class='add'>+</div><div class='add'>+				/* luma */</div><div class='add'>+				adj_factor = bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p0[plane_index] : 1.0;</div><div class='add'>+</div><div class='add'>+				effective_excess_bandwidth_l = effective_excess_bandwidth * surface_read_bw_l[plane_index] / (surface_read_bw_l[plane_index] + surface_read_bw_c[plane_index]) / adj_factor;</div><div class='add'>+				if (effective_excess_bandwidth_l &gt; 0.0) {</div><div class='add'>+					vactive_det_fill_delay_us[plane_index] = math_max2(vactive_det_fill_delay_us[plane_index], bytes_required_l[plane_index] / effective_excess_bandwidth_l);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				/* chroma */</div><div class='add'>+				adj_factor = bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p1[plane_index] : 1.0;</div><div class='add'>+</div><div class='add'>+				effective_excess_bandwidth_c = effective_excess_bandwidth * surface_read_bw_c[plane_index] / (surface_read_bw_l[plane_index] + surface_read_bw_c[plane_index]) / adj_factor;</div><div class='add'>+				if (effective_excess_bandwidth_c &gt; 0.0) {</div><div class='add'>+					vactive_det_fill_delay_us[plane_index] = math_max2(vactive_det_fill_delay_us[plane_index], bytes_required_c[plane_index] / effective_excess_bandwidth_c);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_excess_vactive_bandwidth_required(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int num_active_planes,</div><div class='add'>+	unsigned int bytes_required_l[],</div><div class='add'>+	unsigned int bytes_required_c[],</div><div class='add'>+	/* outputs */</div><div class='add'>+	double excess_vactive_fill_bw_l[],</div><div class='add'>+	double excess_vactive_fill_bw_c[])</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; num_active_planes; plane_index++) {</div><div class='add'>+		if (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[plane_index]))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		excess_vactive_fill_bw_l[plane_index] = 0.0;</div><div class='add'>+		excess_vactive_fill_bw_c[plane_index] = 0.0;</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] &gt; 0) {</div><div class='add'>+			excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg-&gt;plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk];</div><div class='add'>+			excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg-&gt;plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config)</div><div class='add'>+{</div><div class='add'>+	double bw_mbps = 0;</div><div class='add'>+	bw_mbps = ((double)uclk_khz * dram_config-&gt;channel_count * dram_config-&gt;channel_width_bytes * dram_config-&gt;transactions_per_clock) / 1000.0;</div><div class='add'>+</div><div class='add'>+	return bw_mbps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double dram_bw_kbps_to_uclk_mhz(unsigned long long bw_kbps, const struct dml2_dram_params *dram_config)</div><div class='add'>+{</div><div class='add'>+	double uclk_mhz = 0;</div><div class='add'>+</div><div class='add'>+	uclk_mhz = (double)bw_kbps / (dram_config-&gt;channel_count * dram_config-&gt;channel_width_bytes * dram_config-&gt;transactions_per_clock) / 1000.0;</div><div class='add'>+</div><div class='add'>+	return uclk_mhz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned int index = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML_MAX_CLK_TABLE_SIZE; i++) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: per_uclk_dpm_params[%d].minimum_uclk_khz = %ld\n", __func__, i, per_uclk_dpm_params[i].minimum_uclk_khz);</div><div class='add'>+</div><div class='add'>+		if (i == 0)</div><div class='add'>+			index = 0;</div><div class='add'>+		else</div><div class='add'>+			index = i - 1;</div><div class='add'>+</div><div class='add'>+		if (uclk_freq_khz &lt; per_uclk_dpm_params[i].minimum_uclk_khz ||</div><div class='add'>+			per_uclk_dpm_params[i].minimum_uclk_khz == 0) {</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: index = %d\n", __func__, index);</div><div class='add'>+	return index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool clk_entry_found = false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; clk_table-&gt;uclk.num_clk_values; i++) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table-&gt;uclk.clk_values_khz[i]);</div><div class='add'>+</div><div class='add'>+		if (uclk_freq_khz == clk_table-&gt;uclk.clk_values_khz[i]) {</div><div class='add'>+			clk_entry_found = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!clk_entry_found)</div><div class='add'>+		DML_ASSERT(clk_entry_found);</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: index = %d\n", __func__, i);</div><div class='add'>+#endif</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_pipe_flip_bytes(</div><div class='add'>+		double hostvm_inefficiency_factor,</div><div class='add'>+		unsigned int vm_bytes,</div><div class='add'>+		unsigned int dpte_row_bytes,</div><div class='add'>+		unsigned int meta_row_bytes)</div><div class='add'>+{</div><div class='add'>+	unsigned int flip_bytes = 0;</div><div class='add'>+</div><div class='add'>+	flip_bytes += (unsigned int) ((vm_bytes * hostvm_inefficiency_factor) + 2*meta_row_bytes);</div><div class='add'>+	flip_bytes += (unsigned int) (2*dpte_row_bytes * hostvm_inefficiency_factor);</div><div class='add'>+</div><div class='add'>+	return flip_bytes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_hostvm_inefficiency_factor(</div><div class='add'>+		double *HostVMInefficiencyFactor,</div><div class='add'>+		double *HostVMInefficiencyFactorPrefetch,</div><div class='add'>+</div><div class='add'>+		bool gpuvm_enable,</div><div class='add'>+		bool hostvm_enable,</div><div class='add'>+		unsigned int remote_iommu_outstanding_translations,</div><div class='add'>+		unsigned int max_outstanding_reqs,</div><div class='add'>+		double urg_bandwidth_avail_active_pixel_and_vm,</div><div class='add'>+		double urg_bandwidth_avail_active_vm_only)</div><div class='add'>+{</div><div class='add'>+		*HostVMInefficiencyFactor = 1;</div><div class='add'>+		*HostVMInefficiencyFactorPrefetch = 1;</div><div class='add'>+</div><div class='add'>+		if (gpuvm_enable &amp;&amp; hostvm_enable) {</div><div class='add'>+			*HostVMInefficiencyFactor = urg_bandwidth_avail_active_pixel_and_vm / urg_bandwidth_avail_active_vm_only;</div><div class='add'>+			*HostVMInefficiencyFactorPrefetch = *HostVMInefficiencyFactor;</div><div class='add'>+</div><div class='add'>+			if ((*HostVMInefficiencyFactorPrefetch &lt; 4) &amp;&amp; (remote_iommu_outstanding_translations &lt; max_outstanding_reqs))</div><div class='add'>+				*HostVMInefficiencyFactorPrefetch = 4;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: urg_bandwidth_avail_active_pixel_and_vm = %f\n", __func__, urg_bandwidth_avail_active_pixel_and_vm);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: urg_bandwidth_avail_active_vm_only = %f\n", __func__, urg_bandwidth_avail_active_vm_only);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, *HostVMInefficiencyFactor);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: HostVMInefficiencyFactorPrefetch = %f\n", __func__, *HostVMInefficiencyFactorPrefetch);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_g6_temp_read_blackouts_table {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int uclk_khz;</div><div class='add'>+		unsigned int blackout_us;</div><div class='add'>+	} entries[DML_MAX_CLK_TABLE_SIZE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_g6_temp_read_blackouts_table core_dcn4_g6_temp_read_blackout_table = {</div><div class='add'>+	.entries = {</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 96000,</div><div class='add'>+			.blackout_us = 23,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 435000,</div><div class='add'>+			.blackout_us = 10,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 521000,</div><div class='add'>+			.blackout_us = 10,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 731000,</div><div class='add'>+			.blackout_us = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 822000,</div><div class='add'>+			.blackout_us = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 962000,</div><div class='add'>+			.blackout_us = 5,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 1069000,</div><div class='add'>+			.blackout_us = 5,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.uclk_khz = 1187000,</div><div class='add'>+			.blackout_us = 5,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static double get_g6_temp_read_blackout_us(</div><div class='add'>+	struct dml2_soc_bb *soc,</div><div class='add'>+	unsigned int uclk_freq_khz,</div><div class='add'>+	unsigned int min_clk_index)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned int blackout_us = core_dcn4_g6_temp_read_blackout_table.entries[0].blackout_us;</div><div class='add'>+</div><div class='add'>+	if (soc-&gt;power_management_parameters.g6_temp_read_blackout_us[0] &gt; 0.0) {</div><div class='add'>+		/* overrides are present in the SoC BB */</div><div class='add'>+		return soc-&gt;power_management_parameters.g6_temp_read_blackout_us[min_clk_index];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* use internal table */</div><div class='add'>+	blackout_us = core_dcn4_g6_temp_read_blackout_table.entries[0].blackout_us;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML_MAX_CLK_TABLE_SIZE; i++) {</div><div class='add'>+		if (uclk_freq_khz &lt; core_dcn4_g6_temp_read_blackout_table.entries[i].uclk_khz ||</div><div class='add'>+			core_dcn4_g6_temp_read_blackout_table.entries[i].uclk_khz == 0) {</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		blackout_us = core_dcn4_g6_temp_read_blackout_table.entries[i].blackout_us;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return (double)blackout_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double get_max_urgent_latency_us(</div><div class='add'>+	struct dml2_dcn4x_soc_qos_params *dcn4x,</div><div class='add'>+	double uclk_freq_mhz,</div><div class='add'>+	double FabricClock,</div><div class='add'>+	unsigned int min_clk_index)</div><div class='add'>+{</div><div class='add'>+	double latency;</div><div class='add'>+	latency = dcn4x-&gt;per_uclk_dpm_params[min_clk_index].maximum_latency_when_urgent_uclk_cycles / uclk_freq_mhz</div><div class='add'>+		* (1 + dcn4x-&gt;umc_max_latency_margin / 100.0)</div><div class='add'>+		+ dcn4x-&gt;mall_overhead_fclk_cycles / FabricClock</div><div class='add'>+		+ dcn4x-&gt;max_round_trip_to_furthest_cs_fclk_cycles / FabricClock</div><div class='add'>+		* (1 + dcn4x-&gt;fabric_max_transport_latency_margin / 100.0);</div><div class='add'>+	return latency;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_pstate_keepout_dst_lines(</div><div class='add'>+		const struct dml2_display_cfg *display_cfg,</div><div class='add'>+		const struct dml2_core_internal_watermarks *watermarks,</div><div class='add'>+		unsigned int pstate_keepout_dst_lines[])</div><div class='add'>+{</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		if (!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[i])) {</div><div class='add'>+			stream_descriptor = &amp;display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[i].stream_index];</div><div class='add'>+</div><div class='add'>+			pstate_keepout_dst_lines[i] =</div><div class='add'>+					(unsigned int)math_ceil(watermarks-&gt;DRAMClockChangeWatermark / ((double)stream_descriptor-&gt;timing.h_total * 1000.0 / (double)stream_descriptor-&gt;timing.pixel_clock_khz));</div><div class='add'>+</div><div class='add'>+			if (pstate_keepout_dst_lines[i] &gt; stream_descriptor-&gt;timing.v_total - 1) {</div><div class='add'>+				pstate_keepout_dst_lines[i] = stream_descriptor-&gt;timing.v_total - 1;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static noinline_for_stack void dml_core_ms_prefetch_check(struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+	const struct dml2_display_cfg *display_cfg)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_calcs_mode_support_locals *s = &amp;mode_lib-&gt;scratch.dml_core_mode_support_locals;</div><div class='add'>+	struct dml2_core_calcs_calculate_tdlut_setting_params *calculate_tdlut_setting_params = &amp;mode_lib-&gt;scratch.calculate_tdlut_setting_params;</div><div class='add'>+	struct dml2_core_calcs_CalculatePrefetchSchedule_params *CalculatePrefetchSchedule_params = &amp;mode_lib-&gt;scratch.CalculatePrefetchSchedule_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_peak_bandwidth_required_params *calculate_peak_bandwidth_params = &amp;mode_lib-&gt;scratch.calculate_peak_bandwidth_params;</div><div class='add'>+#ifdef DML_GLOBAL_PREFETCH_CHECK</div><div class='add'>+	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *CheckGlobalPrefetchAdmissibility_params = &amp;mode_lib-&gt;scratch.CheckGlobalPrefetchAdmissibility_params;</div><div class='add'>+#endif</div><div class='add'>+	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *CalculateWatermarks_params = &amp;mode_lib-&gt;scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;</div><div class='add'>+</div><div class='add'>+	double min_return_bw_for_latency;</div><div class='add'>+	unsigned int k;</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TimeCalc = 24 / mode_lib-&gt;ms.dcfclk_deepsleep;</div><div class='add'>+</div><div class='add'>+	calculate_hostvm_inefficiency_factor(</div><div class='add'>+			&amp;s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+			&amp;s-&gt;HostVMInefficiencyFactorPrefetch,</div><div class='add'>+</div><div class='add'>+			display_cfg-&gt;gpuvm_enable,</div><div class='add'>+			display_cfg-&gt;hostvm_enable,</div><div class='add'>+			mode_lib-&gt;ip.remote_iommu_outstanding_translations,</div><div class='add'>+			mode_lib-&gt;soc.max_outstanding_reqs,</div><div class='add'>+			mode_lib-&gt;ms.support.urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_sys_active],</div><div class='add'>+			mode_lib-&gt;ms.support.urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_sys_active]);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.Total3dlutActive = 0;</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut)</div><div class='add'>+			mode_lib-&gt;ms.Total3dlutActive = mode_lib-&gt;ms.Total3dlutActive + 1;</div><div class='add'>+</div><div class='add'>+		// Calculate tdlut schedule related terms</div><div class='add'>+		calculate_tdlut_setting_params-&gt;dispclk_mhz = mode_lib-&gt;ms.RequiredDISPCLK;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;setup_for_tdlut = display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_width_mode = display_cfg-&gt;plane_descriptors[k].tdlut.tdlut_width_mode;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_addressing_mode = display_cfg-&gt;plane_descriptors[k].tdlut.tdlut_addressing_mode;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;cursor_buffer_size = mode_lib-&gt;ip.cursor_buffer_size;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;gpuvm_enable = display_cfg-&gt;gpuvm_enable;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;gpuvm_page_size_kbytes = display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_mpc_width_flag = display_cfg-&gt;plane_descriptors[k].tdlut.tdlut_mpc_width_flag;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;is_gfx11 = dml_get_gfx_version(display_cfg-&gt;plane_descriptors[k].surface.tiling);</div><div class='add'>+</div><div class='add'>+		// output</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_pte_bytes_per_frame = &amp;s-&gt;tdlut_pte_bytes_per_frame[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_bytes_per_frame = &amp;s-&gt;tdlut_bytes_per_frame[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_groups_per_2row_ub = &amp;s-&gt;tdlut_groups_per_2row_ub[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_opt_time = &amp;s-&gt;tdlut_opt_time[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_drain_time = &amp;s-&gt;tdlut_drain_time[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_bytes_to_deliver = &amp;s-&gt;tdlut_bytes_to_deliver[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_bytes_per_group = &amp;s-&gt;tdlut_bytes_per_group[k];</div><div class='add'>+</div><div class='add'>+		calculate_tdlut_setting(&amp;mode_lib-&gt;scratch, calculate_tdlut_setting_params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_return_bw_for_latency = mode_lib-&gt;ms.support.urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_sys_active];</div><div class='add'>+</div><div class='add'>+	if (mode_lib-&gt;soc.qos_parameters.qos_type == dml2_qos_param_type_dcn3)</div><div class='add'>+		s-&gt;ReorderingBytes = (unsigned int)(mode_lib-&gt;soc.clk_table.dram_config.channel_count * math_max3(mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_out_of_order_return_per_channel_pixel_only_bytes,</div><div class='add'>+										mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes,</div><div class='add'>+										mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_out_of_order_return_per_channel_vm_only_bytes));</div><div class='add'>+</div><div class='add'>+	CalculateExtraLatency(</div><div class='add'>+		display_cfg,</div><div class='add'>+		mode_lib-&gt;ip.rob_buffer_size_kbytes,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.loaded_round_trip_latency_fclk_cycles,</div><div class='add'>+		s-&gt;ReorderingBytes,</div><div class='add'>+		mode_lib-&gt;ms.DCFCLK,</div><div class='add'>+		mode_lib-&gt;ms.FabricClock,</div><div class='add'>+		mode_lib-&gt;ip.pixel_chunk_size_kbytes,</div><div class='add'>+		min_return_bw_for_latency,</div><div class='add'>+		mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+		mode_lib-&gt;ms.NoOfDPP,</div><div class='add'>+		mode_lib-&gt;ms.dpte_group_bytes,</div><div class='add'>+		s-&gt;tdlut_bytes_per_group,</div><div class='add'>+		s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+		s-&gt;HostVMInefficiencyFactorPrefetch,</div><div class='add'>+		mode_lib-&gt;soc.hostvm_min_page_size_kbytes,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		!(display_cfg-&gt;overrides.max_outstanding_when_urgent_expected_disable),</div><div class='add'>+		mode_lib-&gt;soc.max_outstanding_reqs,</div><div class='add'>+		mode_lib-&gt;ms.support.request_size_bytes_luma,</div><div class='add'>+		mode_lib-&gt;ms.support.request_size_bytes_chroma,</div><div class='add'>+		mode_lib-&gt;ip.meta_chunk_size_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.dchub_arb_to_ret_delay,</div><div class='add'>+		mode_lib-&gt;ms.TripToMemory,</div><div class='add'>+		mode_lib-&gt;ip.hostvm_mode,</div><div class='add'>+</div><div class='add'>+		// output</div><div class='add'>+		&amp;mode_lib-&gt;ms.ExtraLatency,</div><div class='add'>+		&amp;mode_lib-&gt;ms.ExtraLatency_sr,</div><div class='add'>+		&amp;mode_lib-&gt;ms.ExtraLatencyPrefetch);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++)</div><div class='add'>+		s-&gt;impacted_dst_y_pre[k] = 0;</div><div class='add'>+</div><div class='add'>+	s-&gt;recalc_prefetch_schedule = 0;</div><div class='add'>+	s-&gt;recalc_prefetch_done = 0;</div><div class='add'>+	do {</div><div class='add'>+		mode_lib-&gt;ms.support.PrefetchSupported = true;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			s-&gt;line_times[k] = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+			s-&gt;pixel_format[k] = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+</div><div class='add'>+			s-&gt;lb_source_lines_l[k] = get_num_lb_source_lines(mode_lib-&gt;ip.max_line_buffer_lines, mode_lib-&gt;ip.line_buffer_size_bits,</div><div class='add'>+																mode_lib-&gt;ms.NoOfDPP[k],</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.rotation_angle);</div><div class='add'>+</div><div class='add'>+			s-&gt;lb_source_lines_c[k] = get_num_lb_source_lines(mode_lib-&gt;ip.max_line_buffer_lines, mode_lib-&gt;ip.line_buffer_size_bits,</div><div class='add'>+																mode_lib-&gt;ms.NoOfDPP[k],</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.width,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].composition.rotation_angle);</div><div class='add'>+</div><div class='add'>+			struct dml2_core_internal_DmlPipe *myPipe = &amp;s-&gt;myPipe;</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;ms.TWait[k] = CalculateTWait(</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].overrides.reserved_vblank_time_ns,</div><div class='add'>+				mode_lib-&gt;ms.UrgLatency,</div><div class='add'>+				mode_lib-&gt;ms.TripToMemory,</div><div class='add'>+				!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k]) &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.drr_config.enabled ?</div><div class='add'>+				get_g6_temp_read_blackout_us(&amp;mode_lib-&gt;soc, (unsigned int)(mode_lib-&gt;ms.uclk_freq_mhz * 1000), mode_lib-&gt;ms.state_idx) : 0.0);</div><div class='add'>+</div><div class='add'>+			myPipe-&gt;Dppclk = mode_lib-&gt;ms.RequiredDPPCLK[k];</div><div class='add'>+			myPipe-&gt;Dispclk = mode_lib-&gt;ms.RequiredDISPCLK;</div><div class='add'>+			myPipe-&gt;PixelClock = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+			myPipe-&gt;DCFClkDeepSleep = mode_lib-&gt;ms.dcfclk_deepsleep;</div><div class='add'>+			myPipe-&gt;DPPPerSurface = mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+			myPipe-&gt;ScalerEnabled = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.enabled;</div><div class='add'>+			myPipe-&gt;VRatio = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+			myPipe-&gt;VRatioChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+			myPipe-&gt;VTaps = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps;</div><div class='add'>+			myPipe-&gt;VTapsChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps;</div><div class='add'>+			myPipe-&gt;RotationAngle = display_cfg-&gt;plane_descriptors[k].composition.rotation_angle;</div><div class='add'>+			myPipe-&gt;mirrored = display_cfg-&gt;plane_descriptors[k].composition.mirrored;</div><div class='add'>+			myPipe-&gt;BlockWidth256BytesY = mode_lib-&gt;ms.Read256BlockWidthY[k];</div><div class='add'>+			myPipe-&gt;BlockHeight256BytesY = mode_lib-&gt;ms.Read256BlockHeightY[k];</div><div class='add'>+			myPipe-&gt;BlockWidth256BytesC = mode_lib-&gt;ms.Read256BlockWidthC[k];</div><div class='add'>+			myPipe-&gt;BlockHeight256BytesC = mode_lib-&gt;ms.Read256BlockHeightC[k];</div><div class='add'>+			myPipe-&gt;InterlaceEnable = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced;</div><div class='add'>+			myPipe-&gt;NumberOfCursors = display_cfg-&gt;plane_descriptors[k].cursor.num_cursors;</div><div class='add'>+			myPipe-&gt;VBlank = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active;</div><div class='add'>+			myPipe-&gt;HTotal = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+			myPipe-&gt;HActive = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active;</div><div class='add'>+			myPipe-&gt;DCCEnable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+			myPipe-&gt;ODMMode = mode_lib-&gt;ms.ODMMode[k];</div><div class='add'>+			myPipe-&gt;SourcePixelFormat = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+			myPipe-&gt;BytePerPixelY = mode_lib-&gt;ms.BytePerPixelY[k];</div><div class='add'>+			myPipe-&gt;BytePerPixelC = mode_lib-&gt;ms.BytePerPixelC[k];</div><div class='add'>+			myPipe-&gt;ProgressiveToInterlaceUnitInOPP = mode_lib-&gt;ip.ptoi_supported;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: MaximumVStartup = %u\n", __func__, s-&gt;MaximumVStartup[k]);</div><div class='add'>+#endif</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;display_cfg = display_cfg;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;HostVMInefficiencyFactor = s-&gt;HostVMInefficiencyFactorPrefetch;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;myPipe = myPipe;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DSCDelay = mode_lib-&gt;ms.DSCDelay[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelaySubtotalPlusCNVCFormater = mode_lib-&gt;ip.dppclk_delay_subtotal + mode_lib-&gt;ip.dppclk_delay_cnvc_formatter;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelaySCL = mode_lib-&gt;ip.dppclk_delay_scl;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelaySCLLBOnly = mode_lib-&gt;ip.dppclk_delay_scl_lb_only;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelayCNVCCursor = mode_lib-&gt;ip.dppclk_delay_cnvc_cursor;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DISPCLKDelaySubtotal = mode_lib-&gt;ip.dispclk_delay_subtotal;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPP_RECOUT_WIDTH = (unsigned int)(mode_lib-&gt;ms.SwathWidthY[k] / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio);</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;OutputFormat = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;MaxInterDCNTileRepeaters = mode_lib-&gt;ip.max_inter_dcn_tile_repeaters;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VStartup = s-&gt;MaximumVStartup[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;HostVMMinPageSize = mode_lib-&gt;soc.hostvm_min_page_size_kbytes;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataEnable = display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.enable;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataVMEnabled = mode_lib-&gt;ip.dynamic_metadata_vm_enabled;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataLinesBeforeActiveRequired = display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.lines_before_active_required;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataTransmittedBytes = display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.transmitted_bytes;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;UrgentLatency = mode_lib-&gt;ms.UrgLatency;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;ExtraLatencyPrefetch = mode_lib-&gt;ms.ExtraLatencyPrefetch;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;TCalc = mode_lib-&gt;ms.TimeCalc;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;vm_bytes = mode_lib-&gt;ms.vm_bytes[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;PixelPTEBytesPerRow = mode_lib-&gt;ms.DPTEBytesPerRow[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;PrefetchSourceLinesY = mode_lib-&gt;ms.PrefetchLinesY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VInitPreFillY = mode_lib-&gt;ms.PrefillY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;MaxNumSwathY = mode_lib-&gt;ms.MaxNumSwathY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;PrefetchSourceLinesC = mode_lib-&gt;ms.PrefetchLinesC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VInitPreFillC = mode_lib-&gt;ms.PrefillC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;MaxNumSwathC = mode_lib-&gt;ms.MaxNumSwathC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;swath_width_luma_ub = mode_lib-&gt;ms.swath_width_luma_ub[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;swath_width_chroma_ub = mode_lib-&gt;ms.swath_width_chroma_ub[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;SwathHeightY = mode_lib-&gt;ms.SwathHeightY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;SwathHeightC = mode_lib-&gt;ms.SwathHeightC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;TWait = mode_lib-&gt;ms.TWait[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Ttrip = mode_lib-&gt;ms.TripToMemory;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Turg = mode_lib-&gt;ms.UrgLatency;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;setup_for_tdlut = display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_pte_bytes_per_frame = s-&gt;tdlut_pte_bytes_per_frame[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_bytes_per_frame = s-&gt;tdlut_bytes_per_frame[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_opt_time = s-&gt;tdlut_opt_time[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_drain_time = s-&gt;tdlut_drain_time[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;num_cursors = (display_cfg-&gt;plane_descriptors[k].cursor.cursor_width &gt; 0);</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;cursor_bytes_per_chunk = s-&gt;cursor_bytes_per_chunk[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;cursor_bytes_per_line = s-&gt;cursor_bytes_per_line[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dcc_enable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;meta_row_bytes = mode_lib-&gt;ms.meta_row_bytes[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;mall_prefetch_sdp_overhead_factor = mode_lib-&gt;ms.mall_prefetch_sdp_overhead_factor[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;impacted_dst_y_pre = s-&gt;impacted_dst_y_pre[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;vactive_sw_bw_l = mode_lib-&gt;ms.vactive_sw_bw_l[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;vactive_sw_bw_c = mode_lib-&gt;ms.vactive_sw_bw_c[k];</div><div class='add'>+</div><div class='add'>+			// output</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DSTXAfterScaler = &amp;s-&gt;DSTXAfterScaler[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DSTYAfterScaler = &amp;s-&gt;DSTYAfterScaler[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dst_y_prefetch = &amp;mode_lib-&gt;ms.dst_y_prefetch[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dst_y_per_vm_vblank = &amp;mode_lib-&gt;ms.LinesForVM[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dst_y_per_row_vblank = &amp;mode_lib-&gt;ms.LinesForDPTERow[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VRatioPrefetchY = &amp;mode_lib-&gt;ms.VRatioPreY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VRatioPrefetchC = &amp;mode_lib-&gt;ms.VRatioPreC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;RequiredPrefetchPixelDataBWLuma = &amp;mode_lib-&gt;ms.RequiredPrefetchPixelDataBWLuma[k]; // prefetch_sw_bw_l</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;RequiredPrefetchPixelDataBWChroma = &amp;mode_lib-&gt;ms.RequiredPrefetchPixelDataBWChroma[k]; // prefetch_sw_bw_c</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;RequiredPrefetchBWMax = &amp;mode_lib-&gt;ms.RequiredPrefetchBWMax[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;NotEnoughTimeForDynamicMetadata = &amp;mode_lib-&gt;ms.NoTimeForDynamicMetadata[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tno_bw = &amp;mode_lib-&gt;ms.Tno_bw[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tno_bw_flip = &amp;mode_lib-&gt;ms.Tno_bw_flip[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_vmrow_bw = &amp;mode_lib-&gt;ms.prefetch_vmrow_bw[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tdmdl_vm = &amp;s-&gt;dummy_single[0];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tdmdl = &amp;s-&gt;dummy_single[1];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;TSetup = &amp;s-&gt;dummy_single[2];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tvm_trips = &amp;s-&gt;Tvm_trips[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tr0_trips = &amp;s-&gt;Tr0_trips[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tvm_trips_flip = &amp;s-&gt;Tvm_trips_flip[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tr0_trips_flip = &amp;s-&gt;Tr0_trips_flip[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tvm_trips_flip_rounded = &amp;s-&gt;Tvm_trips_flip_rounded[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tr0_trips_flip_rounded = &amp;s-&gt;Tr0_trips_flip_rounded[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VUpdateOffsetPix = &amp;s-&gt;dummy_integer[0];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VUpdateWidthPix = &amp;s-&gt;dummy_integer[1];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VReadyOffsetPix = &amp;s-&gt;dummy_integer[2];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_cursor_bw = &amp;mode_lib-&gt;ms.prefetch_cursor_bw[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_sw_bytes = &amp;s-&gt;prefetch_sw_bytes[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tpre_rounded = &amp;s-&gt;Tpre_rounded[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tpre_oto = &amp;s-&gt;Tpre_oto[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_swath_time_us = &amp;s-&gt;prefetch_swath_time_us[k];</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;ms.NoTimeForPrefetch[k] = CalculatePrefetchSchedule(&amp;mode_lib-&gt;scratch, CalculatePrefetchSchedule_params);</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;ms.support.PrefetchSupported &amp;= !mode_lib-&gt;ms.NoTimeForPrefetch[k];</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_per_vm_vblank = %f\n", __func__, k, *CalculatePrefetchSchedule_params-&gt;dst_y_per_vm_vblank);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_per_row_vblank = %f\n", __func__, k, *CalculatePrefetchSchedule_params-&gt;dst_y_per_row_vblank);</div><div class='add'>+		} // for k num_planes</div><div class='add'>+</div><div class='add'>+		CalculateDCFCLKDeepSleepTdlut(</div><div class='add'>+			display_cfg,</div><div class='add'>+			mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+			mode_lib-&gt;ms.BytePerPixelY,</div><div class='add'>+			mode_lib-&gt;ms.BytePerPixelC,</div><div class='add'>+			mode_lib-&gt;ms.SwathWidthY,</div><div class='add'>+			mode_lib-&gt;ms.SwathWidthC,</div><div class='add'>+			mode_lib-&gt;ms.NoOfDPP,</div><div class='add'>+			mode_lib-&gt;ms.PSCL_FACTOR,</div><div class='add'>+			mode_lib-&gt;ms.PSCL_FACTOR_CHROMA,</div><div class='add'>+			mode_lib-&gt;ms.RequiredDPPCLK,</div><div class='add'>+			mode_lib-&gt;ms.vactive_sw_bw_l,</div><div class='add'>+			mode_lib-&gt;ms.vactive_sw_bw_c,</div><div class='add'>+			mode_lib-&gt;soc.return_bus_width_bytes,</div><div class='add'>+			mode_lib-&gt;ms.RequiredDISPCLK,</div><div class='add'>+			s-&gt;tdlut_bytes_to_deliver,</div><div class='add'>+			s-&gt;prefetch_swath_time_us,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;mode_lib-&gt;ms.dcfclk_deepsleep);</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			if (mode_lib-&gt;ms.dst_y_prefetch[k] &lt; 2.0</div><div class='add'>+				|| mode_lib-&gt;ms.LinesForVM[k] &gt;= 32.0</div><div class='add'>+				|| mode_lib-&gt;ms.LinesForDPTERow[k] &gt;= 16.0</div><div class='add'>+				|| mode_lib-&gt;ms.NoTimeForPrefetch[k] == true</div><div class='add'>+				|| s-&gt;DSTYAfterScaler[k] &gt; 8) {</div><div class='add'>+				mode_lib-&gt;ms.support.PrefetchSupported = false;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_prefetch=%f (should not be &lt; 2)\n", __func__, k, mode_lib-&gt;ms.dst_y_prefetch[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, LinesForVM=%f (should not be &gt;= 32)\n", __func__, k, mode_lib-&gt;ms.LinesForVM[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, LinesForDPTERow=%f (should not be &gt;= 16)\n", __func__, k, mode_lib-&gt;ms.LinesForDPTERow[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, DSTYAfterScaler=%d (should be &lt;= 8)\n", __func__, k, s-&gt;DSTYAfterScaler[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib-&gt;ms.NoTimeForPrefetch[k]);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.support.DynamicMetadataSupported = true;</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+			if (mode_lib-&gt;ms.NoTimeForDynamicMetadata[k] == true) {</div><div class='add'>+				mode_lib-&gt;ms.support.DynamicMetadataSupported = false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.support.VRatioInPrefetchSupported = true;</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			if (mode_lib-&gt;ms.VRatioPreY[k] &gt; __DML2_CALCS_MAX_VRATIO_PRE__ ||</div><div class='add'>+				mode_lib-&gt;ms.VRatioPreC[k] &gt; __DML2_CALCS_MAX_VRATIO_PRE__) {</div><div class='add'>+				mode_lib-&gt;ms.support.VRatioInPrefetchSupported = false;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d VRatioPreY = %f (should be &lt;= %f)\n", __func__, k, mode_lib-&gt;ms.VRatioPreY[k], __DML2_CALCS_MAX_VRATIO_PRE__);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d VRatioPreC = %f (should be &lt;= %f)\n", __func__, k, mode_lib-&gt;ms.VRatioPreC[k], __DML2_CALCS_MAX_VRATIO_PRE__);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: VRatioInPrefetchSupported = %u\n", __func__, mode_lib-&gt;ms.support.VRatioInPrefetchSupported);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.support.PrefetchSupported &amp;= mode_lib-&gt;ms.support.VRatioInPrefetchSupported;</div><div class='add'>+</div><div class='add'>+		// By default, do not recalc prefetch schedule</div><div class='add'>+		s-&gt;recalc_prefetch_schedule = 0;</div><div class='add'>+</div><div class='add'>+		// Only do urg vs prefetch bandwidth check, flip schedule check, power saving feature support check IF the Prefetch Schedule Check is ok</div><div class='add'>+		if (mode_lib-&gt;ms.support.PrefetchSupported) {</div><div class='add'>+			for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+				// Calculate Urgent burst factor for prefetch</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, Calling CalculateUrgentBurstFactor (for prefetch)\n", __func__, k);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPreY=%f\n", __func__, k, mode_lib-&gt;ms.VRatioPreY[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPreC=%f\n", __func__, k, mode_lib-&gt;ms.VRatioPreC[k]);</div><div class='add'>+#endif</div><div class='add'>+				CalculateUrgentBurstFactor(</div><div class='add'>+					&amp;display_cfg-&gt;plane_descriptors[k],</div><div class='add'>+					mode_lib-&gt;ms.swath_width_luma_ub[k],</div><div class='add'>+					mode_lib-&gt;ms.swath_width_chroma_ub[k],</div><div class='add'>+					mode_lib-&gt;ms.SwathHeightY[k],</div><div class='add'>+					mode_lib-&gt;ms.SwathHeightC[k],</div><div class='add'>+					s-&gt;line_times[k],</div><div class='add'>+					mode_lib-&gt;ms.UrgLatency,</div><div class='add'>+					mode_lib-&gt;ms.VRatioPreY[k],</div><div class='add'>+					mode_lib-&gt;ms.VRatioPreC[k],</div><div class='add'>+					mode_lib-&gt;ms.BytePerPixelInDETY[k],</div><div class='add'>+					mode_lib-&gt;ms.BytePerPixelInDETC[k],</div><div class='add'>+					mode_lib-&gt;ms.DETBufferSizeY[k],</div><div class='add'>+					mode_lib-&gt;ms.DETBufferSizeC[k],</div><div class='add'>+					/* Output */</div><div class='add'>+					&amp;mode_lib-&gt;ms.UrgentBurstFactorLumaPre[k],</div><div class='add'>+					&amp;mode_lib-&gt;ms.UrgentBurstFactorChromaPre[k],</div><div class='add'>+					&amp;mode_lib-&gt;ms.NotEnoughUrgentLatencyHidingPre[k]);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			// Calculate urgent bandwidth required, both urg and non urg peak bandwidth</div><div class='add'>+			// assume flip bw is 0 at this point</div><div class='add'>+			for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++)</div><div class='add'>+				mode_lib-&gt;ms.final_flip_bw[k] = 0;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_vactive_bandwidth_required = mode_lib-&gt;ms.support.urg_vactive_bandwidth_required;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_bandwidth_required = mode_lib-&gt;ms.support.urg_bandwidth_required;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_bandwidth_required_qual = mode_lib-&gt;ms.support.urg_bandwidth_required_qual;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;non_urg_bandwidth_required = mode_lib-&gt;ms.support.non_urg_bandwidth_required;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_avg_vactive_required_bw = mode_lib-&gt;ms.surface_avg_vactive_required_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_peak_required_bw = mode_lib-&gt;ms.surface_peak_required_bw;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;display_cfg = display_cfg;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;inc_flip_bw = 0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;num_active_planes =  mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;num_of_dpp = mode_lib-&gt;ms.NoOfDPP;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p0 = mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p1 = mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p0 = mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p1 = mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;mall_prefetch_sdp_overhead_factor = mode_lib-&gt;ms.mall_prefetch_sdp_overhead_factor;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;mall_prefetch_dram_overhead_factor = mode_lib-&gt;ms.mall_prefetch_dram_overhead_factor;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_l = mode_lib-&gt;ms.vactive_sw_bw_l;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_c = mode_lib-&gt;ms.vactive_sw_bw_c;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_l = mode_lib-&gt;ms.RequiredPrefetchPixelDataBWLuma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_c = mode_lib-&gt;ms.RequiredPrefetchPixelDataBWChroma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_max = mode_lib-&gt;ms.RequiredPrefetchBWMax;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_l = mode_lib-&gt;ms.excess_vactive_fill_bw_l;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_c = mode_lib-&gt;ms.excess_vactive_fill_bw_c;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;cursor_bw = mode_lib-&gt;ms.cursor_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dpte_row_bw = mode_lib-&gt;ms.dpte_row_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;meta_row_bw = mode_lib-&gt;ms.meta_row_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_cursor_bw = mode_lib-&gt;ms.prefetch_cursor_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_vmrow_bw = mode_lib-&gt;ms.prefetch_vmrow_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;flip_bw = mode_lib-&gt;ms.final_flip_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_l = mode_lib-&gt;ms.UrgentBurstFactorLuma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_c = mode_lib-&gt;ms.UrgentBurstFactorChroma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_cursor = mode_lib-&gt;ms.UrgentBurstFactorCursor;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_l = mode_lib-&gt;ms.UrgentBurstFactorLumaPre;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_c = mode_lib-&gt;ms.UrgentBurstFactorChromaPre;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_cursor = mode_lib-&gt;ms.UrgentBurstFactorCursorPre;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_required(</div><div class='add'>+					&amp;mode_lib-&gt;scratch,</div><div class='add'>+					calculate_peak_bandwidth_params);</div><div class='add'>+</div><div class='add'>+			// Check urg peak bandwidth against available urg bw</div><div class='add'>+			// check at SDP and DRAM, for all soc states (SVP prefetch an Sys Active)</div><div class='add'>+			check_urgent_bandwidth_support(</div><div class='add'>+				&amp;s-&gt;dummy_single[0], // double* frac_urg_bandwidth</div><div class='add'>+				&amp;s-&gt;dummy_single[1], // double* frac_urg_bandwidth_mall</div><div class='add'>+				&amp;mode_lib-&gt;ms.support.UrgVactiveBandwidthSupport,</div><div class='add'>+				&amp;mode_lib-&gt;ms.support.PrefetchBandwidthSupported,</div><div class='add'>+</div><div class='add'>+				mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes,</div><div class='add'>+				mode_lib-&gt;ms.support.non_urg_bandwidth_required,</div><div class='add'>+				mode_lib-&gt;ms.support.urg_vactive_bandwidth_required,</div><div class='add'>+				mode_lib-&gt;ms.support.urg_bandwidth_required,</div><div class='add'>+				mode_lib-&gt;ms.support.urg_bandwidth_available);</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;ms.support.PrefetchSupported &amp;= mode_lib-&gt;ms.support.PrefetchBandwidthSupported;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: PrefetchBandwidthSupported=%0d\n", __func__, mode_lib-&gt;ms.support.PrefetchBandwidthSupported);</div><div class='add'>+</div><div class='add'>+			for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+				if (mode_lib-&gt;ms.NotEnoughUrgentLatencyHidingPre[k]) {</div><div class='add'>+					mode_lib-&gt;ms.support.PrefetchSupported = false;</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%d, NotEnoughUrgentLatencyHidingPre=%d\n", __func__, k, mode_lib-&gt;ms.NotEnoughUrgentLatencyHidingPre[k]);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+#ifdef DML_GLOBAL_PREFETCH_CHECK</div><div class='add'>+			if (mode_lib-&gt;ms.support.PrefetchSupported &amp;&amp; mode_lib-&gt;ms.num_active_planes &gt; 1 &amp;&amp; s-&gt;recalc_prefetch_done == 0) {</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;num_active_planes =  mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;pixel_format = s-&gt;pixel_format;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;chunk_bytes_l = mode_lib-&gt;ip.pixel_chunk_size_kbytes * 1024;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;chunk_bytes_c = mode_lib-&gt;ip.pixel_chunk_size_kbytes * 1024;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;lb_source_lines_l = s-&gt;lb_source_lines_l;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;lb_source_lines_c = s-&gt;lb_source_lines_c;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;swath_height_l =  mode_lib-&gt;ms.SwathHeightY;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;swath_height_c =  mode_lib-&gt;ms.SwathHeightC;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;rob_buffer_size_kbytes = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;compressed_buffer_size_kbytes = mode_lib-&gt;ms.CompressedBufferSizeInkByte;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;detile_buffer_size_bytes_l = mode_lib-&gt;ms.DETBufferSizeY;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;detile_buffer_size_bytes_c = mode_lib-&gt;ms.DETBufferSizeC;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;full_swath_bytes_l = s-&gt;full_swath_bytes_l;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;full_swath_bytes_c = s-&gt;full_swath_bytes_c;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;prefetch_sw_bytes = s-&gt;prefetch_sw_bytes;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;Tpre_rounded = s-&gt;Tpre_rounded;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;Tpre_oto = s-&gt;Tpre_oto;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;estimated_urg_bandwidth_required_mbps = mode_lib-&gt;ms.support.urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp];</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;line_time = s-&gt;line_times;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;dst_y_prefetch = mode_lib-&gt;ms.dst_y_prefetch;</div><div class='add'>+				if (CheckGlobalPrefetchAdmissibility_params-&gt;estimated_urg_bandwidth_required_mbps &lt; 10 * 1024)</div><div class='add'>+					CheckGlobalPrefetchAdmissibility_params-&gt;estimated_urg_bandwidth_required_mbps = 10 * 1024;</div><div class='add'>+</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;estimated_dcfclk_mhz = (CheckGlobalPrefetchAdmissibility_params-&gt;estimated_urg_bandwidth_required_mbps / (double) mode_lib-&gt;soc.return_bus_width_bytes) /</div><div class='add'>+																				((double)mode_lib-&gt;soc.qos_parameters.derate_table.system_active_urgent.dcfclk_derate_percent / 100.0);</div><div class='add'>+</div><div class='add'>+				// if recalc_prefetch_schedule is set, recalculate the prefetch schedule with the new impacted_Tpre, prefetch should be possible</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;recalc_prefetch_schedule = &amp;s-&gt;recalc_prefetch_schedule;</div><div class='add'>+				CheckGlobalPrefetchAdmissibility_params-&gt;impacted_dst_y_pre = s-&gt;impacted_dst_y_pre;</div><div class='add'>+				mode_lib-&gt;ms.support.PrefetchSupported = CheckGlobalPrefetchAdmissibility(&amp;mode_lib-&gt;scratch, CheckGlobalPrefetchAdmissibility_params);</div><div class='add'>+				s-&gt;recalc_prefetch_done = 1;</div><div class='add'>+				s-&gt;recalc_prefetch_schedule = 1;</div><div class='add'>+			}</div><div class='add'>+#endif</div><div class='add'>+		} // prefetch schedule ok, do urg bw and flip schedule</div><div class='add'>+	} while (s-&gt;recalc_prefetch_schedule);</div><div class='add'>+</div><div class='add'>+	// Flip Schedule</div><div class='add'>+	// Both prefetch schedule and BW okay</div><div class='add'>+	if (mode_lib-&gt;ms.support.PrefetchSupported == true) {</div><div class='add'>+		mode_lib-&gt;ms.BandwidthAvailableForImmediateFlip =</div><div class='add'>+			get_bandwidth_available_for_immediate_flip(</div><div class='add'>+				dml2_core_internal_soc_state_sys_active,</div><div class='add'>+				mode_lib-&gt;ms.support.urg_bandwidth_required_qual, // no flip</div><div class='add'>+				mode_lib-&gt;ms.support.urg_bandwidth_available);</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.TotImmediateFlipBytes = 0;</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].immediate_flip) {</div><div class='add'>+				s-&gt;per_pipe_flip_bytes[k] = get_pipe_flip_bytes(</div><div class='add'>+								s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+								mode_lib-&gt;ms.vm_bytes[k],</div><div class='add'>+								mode_lib-&gt;ms.DPTEBytesPerRow[k],</div><div class='add'>+								mode_lib-&gt;ms.meta_row_bytes[k]);</div><div class='add'>+			} else {</div><div class='add'>+				s-&gt;per_pipe_flip_bytes[k] = 0;</div><div class='add'>+			}</div><div class='add'>+			mode_lib-&gt;ms.TotImmediateFlipBytes += s-&gt;per_pipe_flip_bytes[k] * mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			CalculateFlipSchedule(</div><div class='add'>+				&amp;mode_lib-&gt;scratch,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].immediate_flip,</div><div class='add'>+				1, // use_lb_flip_bw</div><div class='add'>+				s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+				s-&gt;Tvm_trips_flip[k],</div><div class='add'>+				s-&gt;Tr0_trips_flip[k],</div><div class='add'>+				s-&gt;Tvm_trips_flip_rounded[k],</div><div class='add'>+				s-&gt;Tr0_trips_flip_rounded[k],</div><div class='add'>+				display_cfg-&gt;gpuvm_enable,</div><div class='add'>+				mode_lib-&gt;ms.vm_bytes[k],</div><div class='add'>+				mode_lib-&gt;ms.DPTEBytesPerRow[k],</div><div class='add'>+				mode_lib-&gt;ms.BandwidthAvailableForImmediateFlip,</div><div class='add'>+				mode_lib-&gt;ms.TotImmediateFlipBytes,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+				(display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)),</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio,</div><div class='add'>+				mode_lib-&gt;ms.Tno_bw_flip[k],</div><div class='add'>+				mode_lib-&gt;ms.dpte_row_height[k],</div><div class='add'>+				mode_lib-&gt;ms.dpte_row_height_chroma[k],</div><div class='add'>+				mode_lib-&gt;ms.use_one_row_for_frame_flip[k],</div><div class='add'>+				mode_lib-&gt;ip.max_flip_time_us,</div><div class='add'>+				mode_lib-&gt;ip.max_flip_time_lines,</div><div class='add'>+				s-&gt;per_pipe_flip_bytes[k],</div><div class='add'>+				mode_lib-&gt;ms.meta_row_bytes[k],</div><div class='add'>+				s-&gt;meta_row_height_luma[k],</div><div class='add'>+				s-&gt;meta_row_height_chroma[k],</div><div class='add'>+				mode_lib-&gt;ip.dcn_mrq_present &amp;&amp; display_cfg-&gt;plane_descriptors[k].surface.dcc.enable,</div><div class='add'>+</div><div class='add'>+				/* Output */</div><div class='add'>+				&amp;mode_lib-&gt;ms.dst_y_per_vm_flip[k],</div><div class='add'>+				&amp;mode_lib-&gt;ms.dst_y_per_row_flip[k],</div><div class='add'>+				&amp;mode_lib-&gt;ms.final_flip_bw[k],</div><div class='add'>+				&amp;mode_lib-&gt;ms.ImmediateFlipSupportedForPipe[k]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urg_vactive_bandwidth_required = s-&gt;dummy_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urg_bandwidth_required = mode_lib-&gt;ms.support.urg_bandwidth_required_flip;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urg_bandwidth_required_qual = s-&gt;dummy_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;non_urg_bandwidth_required = mode_lib-&gt;ms.support.non_urg_bandwidth_required_flip;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;surface_avg_vactive_required_bw = s-&gt;surface_dummy_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;surface_peak_required_bw = mode_lib-&gt;ms.surface_peak_required_bw;</div><div class='add'>+</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;display_cfg = display_cfg;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;inc_flip_bw = 1;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;num_active_planes = mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;num_of_dpp = mode_lib-&gt;ms.NoOfDPP;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p0 = mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p0;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p1 = mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p1;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p0 = mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p0;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p1 = mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p1;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;mall_prefetch_sdp_overhead_factor = mode_lib-&gt;ms.mall_prefetch_sdp_overhead_factor;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;mall_prefetch_dram_overhead_factor = mode_lib-&gt;ms.mall_prefetch_dram_overhead_factor;</div><div class='add'>+</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_l = mode_lib-&gt;ms.vactive_sw_bw_l;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_c = mode_lib-&gt;ms.vactive_sw_bw_c;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_l = mode_lib-&gt;ms.RequiredPrefetchPixelDataBWLuma;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_c = mode_lib-&gt;ms.RequiredPrefetchPixelDataBWChroma;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_max = mode_lib-&gt;ms.RequiredPrefetchBWMax;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_l = mode_lib-&gt;ms.excess_vactive_fill_bw_l;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_c = mode_lib-&gt;ms.excess_vactive_fill_bw_c;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;cursor_bw = mode_lib-&gt;ms.cursor_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;dpte_row_bw = mode_lib-&gt;ms.dpte_row_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;meta_row_bw = mode_lib-&gt;ms.meta_row_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;prefetch_cursor_bw = mode_lib-&gt;ms.prefetch_cursor_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;prefetch_vmrow_bw = mode_lib-&gt;ms.prefetch_vmrow_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;flip_bw = mode_lib-&gt;ms.final_flip_bw;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urgent_burst_factor_l = mode_lib-&gt;ms.UrgentBurstFactorLuma;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urgent_burst_factor_c = mode_lib-&gt;ms.UrgentBurstFactorChroma;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urgent_burst_factor_cursor = mode_lib-&gt;ms.UrgentBurstFactorCursor;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_l = mode_lib-&gt;ms.UrgentBurstFactorLumaPre;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_c = mode_lib-&gt;ms.UrgentBurstFactorChromaPre;</div><div class='add'>+		calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_cursor = mode_lib-&gt;ms.UrgentBurstFactorCursorPre;</div><div class='add'>+</div><div class='add'>+		calculate_peak_bandwidth_required(</div><div class='add'>+				&amp;mode_lib-&gt;scratch,</div><div class='add'>+				calculate_peak_bandwidth_params);</div><div class='add'>+</div><div class='add'>+		calculate_immediate_flip_bandwidth_support(</div><div class='add'>+			&amp;s-&gt;dummy_single[0], // double* frac_urg_bandwidth_flip</div><div class='add'>+			&amp;mode_lib-&gt;ms.support.ImmediateFlipSupport,</div><div class='add'>+</div><div class='add'>+			dml2_core_internal_soc_state_sys_active,</div><div class='add'>+			mode_lib-&gt;ms.support.urg_bandwidth_required_flip,</div><div class='add'>+			mode_lib-&gt;ms.support.non_urg_bandwidth_required_flip,</div><div class='add'>+			mode_lib-&gt;ms.support.urg_bandwidth_available);</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].immediate_flip == true &amp;&amp; mode_lib-&gt;ms.ImmediateFlipSupportedForPipe[k] == false)</div><div class='add'>+				mode_lib-&gt;ms.support.ImmediateFlipSupport = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	} else { // if prefetch not support, assume iflip is not supported too</div><div class='add'>+		mode_lib-&gt;ms.support.ImmediateFlipSupport = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	s-&gt;mSOCParameters.UrgentLatency = mode_lib-&gt;ms.UrgLatency;</div><div class='add'>+	s-&gt;mSOCParameters.ExtraLatency = mode_lib-&gt;ms.ExtraLatency;</div><div class='add'>+	s-&gt;mSOCParameters.ExtraLatency_sr = mode_lib-&gt;ms.ExtraLatency_sr;</div><div class='add'>+	s-&gt;mSOCParameters.WritebackLatency = mode_lib-&gt;soc.qos_parameters.writeback.base_latency_us;</div><div class='add'>+	s-&gt;mSOCParameters.DRAMClockChangeLatency = mode_lib-&gt;soc.power_management_parameters.dram_clk_change_blackout_us;</div><div class='add'>+	s-&gt;mSOCParameters.FCLKChangeLatency = mode_lib-&gt;soc.power_management_parameters.fclk_change_blackout_us;</div><div class='add'>+	s-&gt;mSOCParameters.SRExitTime = mode_lib-&gt;soc.power_management_parameters.stutter_exit_latency_us;</div><div class='add'>+	s-&gt;mSOCParameters.SREnterPlusExitTime = mode_lib-&gt;soc.power_management_parameters.stutter_enter_plus_exit_latency_us;</div><div class='add'>+	s-&gt;mSOCParameters.SRExitZ8Time = mode_lib-&gt;soc.power_management_parameters.z8_stutter_exit_latency_us;</div><div class='add'>+	s-&gt;mSOCParameters.SREnterPlusExitZ8Time = mode_lib-&gt;soc.power_management_parameters.z8_stutter_enter_plus_exit_latency_us;</div><div class='add'>+	s-&gt;mSOCParameters.USRRetrainingLatency = 0;</div><div class='add'>+	s-&gt;mSOCParameters.SMNLatency = 0;</div><div class='add'>+	s-&gt;mSOCParameters.g6_temp_read_blackout_us = get_g6_temp_read_blackout_us(&amp;mode_lib-&gt;soc, (unsigned int)(mode_lib-&gt;ms.uclk_freq_mhz * 1000), mode_lib-&gt;ms.state_idx);</div><div class='add'>+	s-&gt;mSOCParameters.max_urgent_latency_us = get_max_urgent_latency_us(&amp;mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x, mode_lib-&gt;ms.uclk_freq_mhz, mode_lib-&gt;ms.FabricClock, mode_lib-&gt;ms.state_idx);</div><div class='add'>+	s-&gt;mSOCParameters.df_response_time_us = mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles / mode_lib-&gt;ms.FabricClock;</div><div class='add'>+	s-&gt;mSOCParameters.qos_type = mode_lib-&gt;soc.qos_parameters.qos_type;</div><div class='add'>+</div><div class='add'>+	CalculateWatermarks_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	CalculateWatermarks_params-&gt;USRRetrainingRequired = false;</div><div class='add'>+	CalculateWatermarks_params-&gt;NumberOfActiveSurfaces = mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+	CalculateWatermarks_params-&gt;MaxLineBufferLines = mode_lib-&gt;ip.max_line_buffer_lines;</div><div class='add'>+	CalculateWatermarks_params-&gt;LineBufferSize = mode_lib-&gt;ip.line_buffer_size_bits;</div><div class='add'>+	CalculateWatermarks_params-&gt;WritebackInterfaceBufferSize = mode_lib-&gt;ip.writeback_interface_buffer_size_kbytes;</div><div class='add'>+	CalculateWatermarks_params-&gt;DCFCLK = mode_lib-&gt;ms.DCFCLK;</div><div class='add'>+	CalculateWatermarks_params-&gt;SynchronizeTimings = display_cfg-&gt;overrides.synchronize_timings;</div><div class='add'>+	CalculateWatermarks_params-&gt;SynchronizeDRRDisplaysForUCLKPStateChange = display_cfg-&gt;overrides.synchronize_ddr_displays_for_uclk_pstate_change;</div><div class='add'>+	CalculateWatermarks_params-&gt;dpte_group_bytes = mode_lib-&gt;ms.dpte_group_bytes;</div><div class='add'>+	CalculateWatermarks_params-&gt;mmSOCParameters = s-&gt;mSOCParameters;</div><div class='add'>+	CalculateWatermarks_params-&gt;WritebackChunkSize = mode_lib-&gt;ip.writeback_chunk_size_kbytes;</div><div class='add'>+	CalculateWatermarks_params-&gt;SOCCLK = mode_lib-&gt;ms.SOCCLK;</div><div class='add'>+	CalculateWatermarks_params-&gt;DCFClkDeepSleep = mode_lib-&gt;ms.dcfclk_deepsleep;</div><div class='add'>+	CalculateWatermarks_params-&gt;DETBufferSizeY = mode_lib-&gt;ms.DETBufferSizeY;</div><div class='add'>+	CalculateWatermarks_params-&gt;DETBufferSizeC = mode_lib-&gt;ms.DETBufferSizeC;</div><div class='add'>+	CalculateWatermarks_params-&gt;SwathHeightY = mode_lib-&gt;ms.SwathHeightY;</div><div class='add'>+	CalculateWatermarks_params-&gt;SwathHeightC = mode_lib-&gt;ms.SwathHeightC;</div><div class='add'>+	CalculateWatermarks_params-&gt;SwathWidthY = mode_lib-&gt;ms.SwathWidthY;</div><div class='add'>+	CalculateWatermarks_params-&gt;SwathWidthC = mode_lib-&gt;ms.SwathWidthC;</div><div class='add'>+	CalculateWatermarks_params-&gt;DPPPerSurface = mode_lib-&gt;ms.NoOfDPP;</div><div class='add'>+	CalculateWatermarks_params-&gt;BytePerPixelDETY = mode_lib-&gt;ms.BytePerPixelInDETY;</div><div class='add'>+	CalculateWatermarks_params-&gt;BytePerPixelDETC = mode_lib-&gt;ms.BytePerPixelInDETC;</div><div class='add'>+	CalculateWatermarks_params-&gt;DSTXAfterScaler = s-&gt;DSTXAfterScaler;</div><div class='add'>+	CalculateWatermarks_params-&gt;DSTYAfterScaler = s-&gt;DSTYAfterScaler;</div><div class='add'>+	CalculateWatermarks_params-&gt;UnboundedRequestEnabled = mode_lib-&gt;ms.UnboundedRequestEnabled;</div><div class='add'>+	CalculateWatermarks_params-&gt;CompressedBufferSizeInkByte = mode_lib-&gt;ms.CompressedBufferSizeInkByte;</div><div class='add'>+	CalculateWatermarks_params-&gt;meta_row_height_l = s-&gt;meta_row_height_luma;</div><div class='add'>+	CalculateWatermarks_params-&gt;meta_row_height_c = s-&gt;meta_row_height_chroma;</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	CalculateWatermarks_params-&gt;Watermark = &amp;mode_lib-&gt;ms.support.watermarks; // Watermarks *Watermark</div><div class='add'>+	CalculateWatermarks_params-&gt;DRAMClockChangeSupport = mode_lib-&gt;ms.support.DRAMClockChangeSupport;</div><div class='add'>+	CalculateWatermarks_params-&gt;global_dram_clock_change_supported = &amp;mode_lib-&gt;ms.support.global_dram_clock_change_supported;</div><div class='add'>+	CalculateWatermarks_params-&gt;MaxActiveDRAMClockChangeLatencySupported = &amp;s-&gt;dummy_single_array[0]; // double *MaxActiveDRAMClockChangeLatencySupported[]</div><div class='add'>+	CalculateWatermarks_params-&gt;SubViewportLinesNeededInMALL = mode_lib-&gt;ms.SubViewportLinesNeededInMALL; // unsigned int SubViewportLinesNeededInMALL[]</div><div class='add'>+	CalculateWatermarks_params-&gt;FCLKChangeSupport = mode_lib-&gt;ms.support.FCLKChangeSupport;</div><div class='add'>+	CalculateWatermarks_params-&gt;global_fclk_change_supported = &amp;mode_lib-&gt;ms.support.global_fclk_change_supported;</div><div class='add'>+	CalculateWatermarks_params-&gt;MaxActiveFCLKChangeLatencySupported = &amp;s-&gt;dummy_single[0]; // double *MaxActiveFCLKChangeLatencySupported</div><div class='add'>+	CalculateWatermarks_params-&gt;USRRetrainingSupport = &amp;mode_lib-&gt;ms.support.USRRetrainingSupport;</div><div class='add'>+	CalculateWatermarks_params-&gt;g6_temp_read_support = &amp;mode_lib-&gt;ms.support.g6_temp_read_support;</div><div class='add'>+	CalculateWatermarks_params-&gt;VActiveLatencyHidingMargin = mode_lib-&gt;ms.VActiveLatencyHidingMargin;</div><div class='add'>+	CalculateWatermarks_params-&gt;VActiveLatencyHidingUs = mode_lib-&gt;ms.VActiveLatencyHidingUs;</div><div class='add'>+</div><div class='add'>+	CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&amp;mode_lib-&gt;scratch, CalculateWatermarks_params);</div><div class='add'>+</div><div class='add'>+	calculate_pstate_keepout_dst_lines(display_cfg, &amp;mode_lib-&gt;ms.support.watermarks, s-&gt;dummy_integer_array[0]);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Done prefetch calculation\n", __func__);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_internal_display_mode_lib *mode_lib = in_out_params-&gt;mode_lib;</div><div class='add'>+	const struct dml2_display_cfg *display_cfg = in_out_params-&gt;in_display_cfg;</div><div class='add'>+	const struct dml2_mcg_min_clock_table *min_clk_table = in_out_params-&gt;min_clk_table;</div><div class='add'>+</div><div class='add'>+	double outstanding_latency_us = 0;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_calcs_mode_support_locals *s = &amp;mode_lib-&gt;scratch.dml_core_mode_support_locals;</div><div class='add'>+	struct dml2_core_calcs_CalculateVMRowAndSwath_params *CalculateVMRowAndSwath_params = &amp;mode_lib-&gt;scratch.CalculateVMRowAndSwath_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *CalculateSwathAndDETConfiguration_params = &amp;mode_lib-&gt;scratch.CalculateSwathAndDETConfiguration_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_setting_params *calculate_mcache_setting_params = &amp;mode_lib-&gt;scratch.calculate_mcache_setting_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *calculate_bytes_to_fetch_required_to_hide_latency_params = &amp;mode_lib-&gt;scratch.calculate_bytes_to_fetch_required_to_hide_latency_params;</div><div class='add'>+	unsigned int k, m, n;</div><div class='add'>+</div><div class='add'>+	memset(&amp;mode_lib-&gt;scratch, 0, sizeof(struct dml2_core_internal_scratch));</div><div class='add'>+	memset(&amp;mode_lib-&gt;ms, 0, sizeof(struct dml2_core_internal_mode_support));</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.num_active_planes = display_cfg-&gt;num_planes;</div><div class='add'>+	get_stream_output_bpp(s-&gt;OutputBpp, display_cfg);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.state_idx = in_out_params-&gt;min_clk_index;</div><div class='add'>+	mode_lib-&gt;ms.SOCCLK = ((double)mode_lib-&gt;soc.clk_table.socclk.clk_values_khz[0] / 1000);</div><div class='add'>+	mode_lib-&gt;ms.DCFCLK = ((double)min_clk_table-&gt;dram_bw_table.entries[in_out_params-&gt;min_clk_index].min_dcfclk_khz / 1000);</div><div class='add'>+	mode_lib-&gt;ms.FabricClock = ((double)min_clk_table-&gt;dram_bw_table.entries[in_out_params-&gt;min_clk_index].min_fclk_khz / 1000);</div><div class='add'>+	mode_lib-&gt;ms.MaxDCFCLK = (double)min_clk_table-&gt;max_clocks_khz.dcfclk / 1000;</div><div class='add'>+	mode_lib-&gt;ms.MaxFabricClock = (double)min_clk_table-&gt;max_clocks_khz.fclk / 1000;</div><div class='add'>+	mode_lib-&gt;ms.max_dispclk_freq_mhz = (double)min_clk_table-&gt;max_ss_clocks_khz.dispclk / 1000;</div><div class='add'>+	mode_lib-&gt;ms.max_dscclk_freq_mhz = (double)min_clk_table-&gt;max_clocks_khz.dscclk / 1000;</div><div class='add'>+	mode_lib-&gt;ms.max_dppclk_freq_mhz = (double)min_clk_table-&gt;max_ss_clocks_khz.dppclk / 1000;</div><div class='add'>+	mode_lib-&gt;ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table-&gt;dram_bw_table.entries[in_out_params-&gt;min_clk_index].pre_derate_dram_bw_kbps, &amp;mode_lib-&gt;soc.clk_table.dram_config);</div><div class='add'>+	mode_lib-&gt;ms.dram_bw_mbps = ((double)min_clk_table-&gt;dram_bw_table.entries[in_out_params-&gt;min_clk_index].pre_derate_dram_bw_kbps / 1000);</div><div class='add'>+	mode_lib-&gt;ms.max_dram_bw_mbps = ((double)min_clk_table-&gt;dram_bw_table.entries[min_clk_table-&gt;dram_bw_table.num_entries - 1].pre_derate_dram_bw_kbps / 1000);</div><div class='add'>+	mode_lib-&gt;ms.qos_param_index = get_qos_param_index((unsigned int) (mode_lib-&gt;ms.uclk_freq_mhz * 1000.0), mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params);</div><div class='add'>+	mode_lib-&gt;ms.active_min_uclk_dpm_index = get_active_min_uclk_dpm_index((unsigned int) (mode_lib-&gt;ms.uclk_freq_mhz * 1000.0), &amp;mode_lib-&gt;soc.clk_table);</div><div class='add'>+</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: --- START --- \n", __func__);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_active_planes = %u\n", __func__, mode_lib-&gt;ms.num_active_planes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_clk_index = %0d\n", __func__, in_out_params-&gt;min_clk_index);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: qos_param_index = %0d\n", __func__, mode_lib-&gt;ms.qos_param_index);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, mode_lib-&gt;ms.SOCCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dram_bw_mbps = %f\n", __func__, mode_lib-&gt;ms.dram_bw_mbps);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: uclk_freq_mhz = %f\n", __func__, mode_lib-&gt;ms.uclk_freq_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFCLK = %f\n", __func__, mode_lib-&gt;ms.DCFCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FabricClock = %f\n", __func__, mode_lib-&gt;ms.FabricClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxDCFCLK = %f\n", __func__, mode_lib-&gt;ms.MaxDCFCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_dispclk_freq_mhz = %f\n", __func__, mode_lib-&gt;ms.max_dispclk_freq_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_dscclk_freq_mhz = %f\n", __func__, mode_lib-&gt;ms.max_dscclk_freq_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_dppclk_freq_mhz = %f\n", __func__, mode_lib-&gt;ms.max_dppclk_freq_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaxFabricClock = %f\n", __func__, mode_lib-&gt;ms.MaxFabricClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ip.compressed_buffer_segment_size_in_kbytes = %u\n", __func__, mode_lib-&gt;ip.compressed_buffer_segment_size_in_kbytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ip.dcn_mrq_present = %u\n", __func__, mode_lib-&gt;ip.dcn_mrq_present);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg-&gt;plane_descriptors[k].overrides.reserved_vblank_time_ns);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	CalculateMaxDETAndMinCompressedBufferSize(</div><div class='add'>+		mode_lib-&gt;ip.config_return_buffer_size_in_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.config_return_buffer_segment_size_in_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.rob_buffer_size_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.max_num_dpp,</div><div class='add'>+		display_cfg-&gt;overrides.hw.force_nom_det_size_kbytes.enable,</div><div class='add'>+		display_cfg-&gt;overrides.hw.force_nom_det_size_kbytes.value,</div><div class='add'>+		mode_lib-&gt;ip.dcn_mrq_present,</div><div class='add'>+</div><div class='add'>+		/* Output */</div><div class='add'>+		&amp;mode_lib-&gt;ms.MaxTotalDETInKByte,</div><div class='add'>+		&amp;mode_lib-&gt;ms.NomDETInKByte,</div><div class='add'>+		&amp;mode_lib-&gt;ms.MinCompressedBufferSizeInKByte);</div><div class='add'>+</div><div class='add'>+	PixelClockAdjustmentForProgressiveToInterlaceUnit(display_cfg, mode_lib-&gt;ip.ptoi_supported, s-&gt;PixelClockBackEnd);</div><div class='add'>+</div><div class='add'>+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/</div><div class='add'>+</div><div class='add'>+	/*Scale Ratio, taps Support Check*/</div><div class='add'>+	mode_lib-&gt;ms.support.ScaleRatioAndTapsSupport = true;</div><div class='add'>+	// Many core tests are still setting scaling parameters "incorrectly"</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.enabled == false</div><div class='add'>+			&amp;&amp; (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format)</div><div class='add'>+				|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio != 1.0</div><div class='add'>+				|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0</div><div class='add'>+				|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio != 1.0</div><div class='add'>+				|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) {</div><div class='add'>+			mode_lib-&gt;ms.support.ScaleRatioAndTapsSupport = false;</div><div class='add'>+		} else if (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps &lt; 1.0 || display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps &gt; 8.0</div><div class='add'>+			|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps &lt; 1.0 || display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps &gt; 8.0</div><div class='add'>+			|| (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps &gt; 1.0 &amp;&amp; (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps % 2) == 1)</div><div class='add'>+			|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio &gt; mode_lib-&gt;ip.max_hscl_ratio</div><div class='add'>+			|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio &gt; mode_lib-&gt;ip.max_vscl_ratio</div><div class='add'>+			|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio &gt; display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps</div><div class='add'>+			|| display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio &gt; display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps</div><div class='add'>+			|| (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format)</div><div class='add'>+				&amp;&amp; (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps &lt; 1 || display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps &gt; 8 ||</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps &lt; 1 || display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps &gt; 8 ||</div><div class='add'>+					(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps &gt; 1 &amp;&amp; display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps % 2 == 1) ||</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio &gt; mode_lib-&gt;ip.max_hscl_ratio ||</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio &gt; mode_lib-&gt;ip.max_vscl_ratio ||</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio &gt; display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps ||</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio &gt; display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps))) {</div><div class='add'>+			mode_lib-&gt;ms.support.ScaleRatioAndTapsSupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*Source Format, Pixel Format and Scan Support Check*/</div><div class='add'>+	mode_lib-&gt;ms.support.SourceFormatPixelAndScanSupport = true;</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].surface.tiling == dml2_sw_linear &amp;&amp; dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+			mode_lib-&gt;ms.support.SourceFormatPixelAndScanSupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		CalculateBytePerPixelAndBlockSizes(</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].surface.tiling,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;mode_lib-&gt;ms.BytePerPixelY[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.BytePerPixelC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.BytePerPixelInDETY[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.BytePerPixelInDETC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.Read256BlockHeightY[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.Read256BlockHeightC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.Read256BlockWidthY[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.Read256BlockWidthC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.MacroTileHeightY[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.MacroTileHeightC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.MacroTileWidthY[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.MacroTileWidthC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.surf_linear128_l[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.surf_linear128_c[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*Bandwidth Support Check*/</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (!dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+			mode_lib-&gt;ms.SwathWidthYSingleDPP[k] = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width;</div><div class='add'>+			mode_lib-&gt;ms.SwathWidthCSingleDPP[k] = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.width;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.SwathWidthYSingleDPP[k] = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height;</div><div class='add'>+			mode_lib-&gt;ms.SwathWidthCSingleDPP[k] = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		mode_lib-&gt;ms.vactive_sw_bw_l[k] = mode_lib-&gt;ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib-&gt;ms.BytePerPixelY[k], 1.0) / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		mode_lib-&gt;ms.vactive_sw_bw_c[k] = mode_lib-&gt;ms.SwathWidthCSingleDPP[k] * math_ceil2(mode_lib-&gt;ms.BytePerPixelC[k], 2.0) / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.cursor_bw[k] = display_cfg-&gt;plane_descriptors[k].cursor.num_cursors * display_cfg-&gt;plane_descriptors[k].cursor.cursor_width *</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].cursor.cursor_bpp / 8.0 / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthLuma = %f\n", __func__, k, mode_lib-&gt;ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib-&gt;ms.BytePerPixelInDETY[k], 1.0) / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthChroma = %f\n", __func__, k, mode_lib-&gt;ms.SwathWidthYSingleDPP[k] / 2 * math_ceil2(mode_lib-&gt;ms.BytePerPixelInDETC[k], 2.0) / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio / 2.0);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_l = %f\n", __func__, k, mode_lib-&gt;ms.vactive_sw_bw_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_c = %f\n", __func__, k, mode_lib-&gt;ms.vactive_sw_bw_c[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Writeback bandwidth</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0 &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {</div><div class='add'>+			mode_lib-&gt;ms.WriteBandwidth[k][0] = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height</div><div class='add'>+				* display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width</div><div class='add'>+				/ (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height</div><div class='add'>+					* display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total</div><div class='add'>+					/ ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 8.0;</div><div class='add'>+		} else if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			mode_lib-&gt;ms.WriteBandwidth[k][0] = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height</div><div class='add'>+				* display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width</div><div class='add'>+				/ (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height</div><div class='add'>+					* display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total</div><div class='add'>+					/ ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 4.0;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.WriteBandwidth[k][0] = 0.0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*Writeback Latency support check*/</div><div class='add'>+	mode_lib-&gt;ms.support.WritebackLatencySupport = true;</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0 &amp;&amp;</div><div class='add'>+			(mode_lib-&gt;ms.WriteBandwidth[k][0] &gt; mode_lib-&gt;ip.writeback_interface_buffer_size_kbytes * 1024 / ((double)mode_lib-&gt;soc.qos_parameters.writeback.base_latency_us))) {</div><div class='add'>+			mode_lib-&gt;ms.support.WritebackLatencySupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/* Writeback Scale Ratio and Taps Support Check */</div><div class='add'>+	mode_lib-&gt;ms.support.WritebackScaleRatioAndTapsSupport = true;</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio &gt; mode_lib-&gt;ip.writeback_max_hscl_ratio</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio &gt; mode_lib-&gt;ip.writeback_max_vscl_ratio</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio &lt; mode_lib-&gt;ip.writeback_min_hscl_ratio</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio &lt; mode_lib-&gt;ip.writeback_min_vscl_ratio</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps &gt; (unsigned int) mode_lib-&gt;ip.writeback_max_hscl_taps</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps &gt; (unsigned int) mode_lib-&gt;ip.writeback_max_vscl_taps</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio &gt; (unsigned int)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps</div><div class='add'>+				|| display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio &gt; (unsigned int)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps</div><div class='add'>+				|| (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps &gt; 2.0 &amp;&amp; ((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps % 2) == 1))) {</div><div class='add'>+				mode_lib-&gt;ms.support.WritebackScaleRatioAndTapsSupport = false;</div><div class='add'>+			}</div><div class='add'>+			if (2.0 * display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height * (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps - 1) * 57 &gt; mode_lib-&gt;ip.writeback_line_buffer_buffer_size) {</div><div class='add'>+				mode_lib-&gt;ms.support.WritebackScaleRatioAndTapsSupport = false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		CalculateSinglePipeDPPCLKAndSCLThroughput(</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio,</div><div class='add'>+			mode_lib-&gt;ip.max_dchub_pscl_bw_pix_per_clk,</div><div class='add'>+			mode_lib-&gt;ip.max_pscl_lb_bw_pix_per_clk,</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps,</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;mode_lib-&gt;ms.PSCL_FACTOR[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.PSCL_FACTOR_CHROMA[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.MinDPPCLKUsingSingleDPP[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Max Viewport Size support</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].surface.tiling == dml2_sw_linear) {</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportLuma = 15360;</div><div class='add'>+		} else if (!dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; mode_lib-&gt;ms.BytePerPixelC[k] &gt; 0 &amp;&amp; display_cfg-&gt;plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // horz video</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportLuma = 7680 + 16;</div><div class='add'>+		} else if (dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; mode_lib-&gt;ms.BytePerPixelC[k] &gt; 0 &amp;&amp; display_cfg-&gt;plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // vert video</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportLuma = 4320 + 16;</div><div class='add'>+		} else if (display_cfg-&gt;plane_descriptors[k].pixel_format == dml2_rgbe_alpha) { // rgbe + alpha</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportLuma = 5120 + 16;</div><div class='add'>+		} else if (dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; mode_lib-&gt;ms.BytePerPixelY[k] == 8 &amp;&amp; display_cfg-&gt;plane_descriptors[k].surface.dcc.enable == true) { // vert 64bpp</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportLuma = 3072 + 16;</div><div class='add'>+		} else {</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportLuma = 6144 + 16;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format)) {</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportChroma = (unsigned int)(s-&gt;MaximumSwathWidthSupportLuma / 2.0);</div><div class='add'>+		} else {</div><div class='add'>+			s-&gt;MaximumSwathWidthSupportChroma = s-&gt;MaximumSwathWidthSupportLuma;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		unsigned lb_buffer_size_bits_luma = mode_lib-&gt;ip.line_buffer_size_bits;</div><div class='add'>+		unsigned lb_buffer_size_bits_chroma = mode_lib-&gt;ip.line_buffer_size_bits;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+#if defined(DV_BUILD)</div><div class='add'>+		// Assume a memory config setting of 3 in 420 mode or get a new ip parameter that reflects the programming.</div><div class='add'>+		if (mode_lib-&gt;ms.BytePerPixelC[k] != 0.0 &amp;&amp; display_cfg-&gt;plane_descriptors[k].pixel_format != dml2_rgbe_alpha) {</div><div class='add'>+			lb_buffer_size_bits_luma = 34620 * 57;</div><div class='add'>+			lb_buffer_size_bits_chroma = 13560 * 57;</div><div class='add'>+		}</div><div class='add'>+#endif</div><div class='add'>+*/</div><div class='add'>+		mode_lib-&gt;ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 /</div><div class='add'>+			(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps + math_max2(math_ceil2(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio, 1.0) - 2, 0.0));</div><div class='add'>+		if (mode_lib-&gt;ms.BytePerPixelC[k] == 0.0) {</div><div class='add'>+			mode_lib-&gt;ms.MaximumSwathWidthInLineBufferChroma = 0;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 /</div><div class='add'>+				(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps + math_max2(math_ceil2(display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio, 1.0) - 2, 0.0));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.MaximumSwathWidthLuma[k] = math_min2(s-&gt;MaximumSwathWidthSupportLuma, mode_lib-&gt;ms.MaximumSwathWidthInLineBufferLuma);</div><div class='add'>+		mode_lib-&gt;ms.MaximumSwathWidthChroma[k] = math_min2(s-&gt;MaximumSwathWidthSupportChroma, mode_lib-&gt;ms.MaximumSwathWidthInLineBufferChroma);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthLuma=%f\n", __func__, k, mode_lib-&gt;ms.MaximumSwathWidthLuma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthSupportLuma=%u\n", __func__, k, s-&gt;MaximumSwathWidthSupportLuma);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthInLineBufferLuma=%f\n", __func__, k, mode_lib-&gt;ms.MaximumSwathWidthInLineBufferLuma);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthChroma=%f\n", __func__, k, mode_lib-&gt;ms.MaximumSwathWidthChroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthSupportChroma=%u\n", __func__, k, s-&gt;MaximumSwathWidthSupportChroma);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthInLineBufferChroma=%f\n", __func__, k, mode_lib-&gt;ms.MaximumSwathWidthInLineBufferChroma);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Cursor Support Check */</div><div class='add'>+	mode_lib-&gt;ms.support.CursorSupport = true;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].cursor.num_cursors &gt; 0) {</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].cursor.cursor_bpp == 64 &amp;&amp; mode_lib-&gt;ip.cursor_64bpp_support == false)</div><div class='add'>+				mode_lib-&gt;ms.support.CursorSupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Valid Pitch Check */</div><div class='add'>+	mode_lib-&gt;ms.support.PitchSupport = true;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+</div><div class='add'>+		// data pitch</div><div class='add'>+		unsigned int alignment_l = mode_lib-&gt;ms.MacroTileWidthY[k];</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.surf_linear128_l[k])</div><div class='add'>+			alignment_l = alignment_l / 2;</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.support.AlignedYPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch, display_cfg-&gt;plane_descriptors[k].surface.plane0.width), alignment_l);</div><div class='add'>+		if (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format) || display_cfg-&gt;plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {</div><div class='add'>+			unsigned int alignment_c = mode_lib-&gt;ms.MacroTileWidthC[k];</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;ms.surf_linear128_c[k])</div><div class='add'>+				alignment_c = alignment_c / 2;</div><div class='add'>+			mode_lib-&gt;ms.support.AlignedCPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch, display_cfg-&gt;plane_descriptors[k].surface.plane1.width), alignment_c);</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.support.AlignedCPitch[k] = display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.support.AlignedYPitch[k] &gt; display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch ||</div><div class='add'>+			mode_lib-&gt;ms.support.AlignedCPitch[k] &gt; display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch) {</div><div class='add'>+			mode_lib-&gt;ms.support.PitchSupport = false;</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u AlignedYPitch = %d\n", __func__, k, mode_lib-&gt;ms.support.AlignedYPitch[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u PitchY = %ld\n", __func__, k, display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u AlignedCPitch = %d\n", __func__, k, mode_lib-&gt;ms.support.AlignedCPitch[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u PitchC = %ld\n", __func__, k, display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u PitchSupport = %d\n", __func__, k, mode_lib-&gt;ms.support.PitchSupport);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// meta pitch</div><div class='add'>+		if (mode_lib-&gt;ip.dcn_mrq_present &amp;&amp; display_cfg-&gt;plane_descriptors[k].surface.dcc.enable) {</div><div class='add'>+			mode_lib-&gt;ms.support.AlignedDCCMetaPitchY[k] = (unsigned int)math_ceil2(math_max2(display_cfg-&gt;plane_descriptors[k].surface.dcc.plane0.pitch,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].surface.plane0.width), 64.0 * mode_lib-&gt;ms.Read256BlockWidthY[k]);</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;ms.support.AlignedDCCMetaPitchY[k] &gt; display_cfg-&gt;plane_descriptors[k].surface.dcc.plane0.pitch)</div><div class='add'>+				mode_lib-&gt;ms.support.PitchSupport = false;</div><div class='add'>+</div><div class='add'>+			if (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format) || display_cfg-&gt;plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {</div><div class='add'>+				mode_lib-&gt;ms.support.AlignedDCCMetaPitchC[k] = (unsigned int)math_ceil2(math_max2(display_cfg-&gt;plane_descriptors[k].surface.dcc.plane1.pitch,</div><div class='add'>+																display_cfg-&gt;plane_descriptors[k].surface.plane1.width), 64.0 * mode_lib-&gt;ms.Read256BlockWidthC[k]);</div><div class='add'>+</div><div class='add'>+				if (mode_lib-&gt;ms.support.AlignedDCCMetaPitchC[k] &gt; display_cfg-&gt;plane_descriptors[k].surface.dcc.plane1.pitch)</div><div class='add'>+					mode_lib-&gt;ms.support.PitchSupport = false;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.support.AlignedDCCMetaPitchY[k] = 0;</div><div class='add'>+			mode_lib-&gt;ms.support.AlignedDCCMetaPitchC[k] = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.ViewportExceedsSurface = false;</div><div class='add'>+	if (!display_cfg-&gt;overrides.hw.surface_viewport_size_check_disable) {</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width &gt; display_cfg-&gt;plane_descriptors[k].surface.plane0.width ||</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height &gt; display_cfg-&gt;plane_descriptors[k].surface.plane0.height) {</div><div class='add'>+				mode_lib-&gt;ms.support.ViewportExceedsSurface = true;</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth = %ld\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u SurfaceWidthY = %ld\n", __func__, k, display_cfg-&gt;plane_descriptors[k].surface.plane0.width);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight = %ld\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u SurfaceHeightY = %ld\n", __func__, k, display_cfg-&gt;plane_descriptors[k].surface.plane0.height);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u ViewportExceedsSurface = %d\n", __func__, k, mode_lib-&gt;ms.support.ViewportExceedsSurface);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+			if (dml_is_420(display_cfg-&gt;plane_descriptors[k].pixel_format) || display_cfg-&gt;plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {</div><div class='add'>+				if (display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.width &gt; display_cfg-&gt;plane_descriptors[k].surface.plane1.width ||</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height &gt; display_cfg-&gt;plane_descriptors[k].surface.plane1.height) {</div><div class='add'>+					mode_lib-&gt;ms.support.ViewportExceedsSurface = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ConfigReturnBufferSizeInKByte = mode_lib-&gt;ip.config_return_buffer_size_in_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MaxTotalDETInKByte = mode_lib-&gt;ms.MaxTotalDETInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MinCompressedBufferSizeInKByte = mode_lib-&gt;ms.MinCompressedBufferSizeInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;rob_buffer_size_kbytes = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;pixel_chunk_size_kbytes = mode_lib-&gt;ip.pixel_chunk_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;rob_buffer_size_kbytes = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;pixel_chunk_size_kbytes = mode_lib-&gt;ip.pixel_chunk_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ForceSingleDPP = 1;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;NumberOfActiveSurfaces = mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;nomDETInKByte = mode_lib-&gt;ms.NomDETInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ConfigReturnBufferSegmentSizeInkByte = mode_lib-&gt;ip.config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;CompressedBufferSegmentSizeInkByte = mode_lib-&gt;ip.compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ReadBandwidthLuma = mode_lib-&gt;ms.vactive_sw_bw_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ReadBandwidthChroma = mode_lib-&gt;ms.vactive_sw_bw_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MaximumSwathWidthLuma = mode_lib-&gt;ms.MaximumSwathWidthLuma;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MaximumSwathWidthChroma = mode_lib-&gt;ms.MaximumSwathWidthChroma;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockHeightY = mode_lib-&gt;ms.Read256BlockHeightY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockHeightC = mode_lib-&gt;ms.Read256BlockHeightC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockWidthY = mode_lib-&gt;ms.Read256BlockWidthY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockWidthC = mode_lib-&gt;ms.Read256BlockWidthC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;surf_linear128_l = mode_lib-&gt;ms.surf_linear128_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;surf_linear128_c = mode_lib-&gt;ms.surf_linear128_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ODMMode = s-&gt;dummy_odm_mode;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixY = mode_lib-&gt;ms.BytePerPixelY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixC = mode_lib-&gt;ms.BytePerPixelC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixDETY = mode_lib-&gt;ms.BytePerPixelInDETY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixDETC = mode_lib-&gt;ms.BytePerPixelInDETC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DPPPerSurface = s-&gt;dummy_integer_array[2];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;req_per_swath_ub_l = s-&gt;dummy_integer_array[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;req_per_swath_ub_c = s-&gt;dummy_integer_array[1];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;swath_width_luma_ub = s-&gt;dummy_integer_array[3];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;swath_width_chroma_ub = s-&gt;dummy_integer_array[4];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathWidth = s-&gt;dummy_integer_array[5];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathWidthChroma = s-&gt;dummy_integer_array[6];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathHeightY = s-&gt;dummy_integer_array[7];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathHeightC = s-&gt;dummy_integer_array[8];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;request_size_bytes_luma = s-&gt;dummy_integer_array[26];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;request_size_bytes_chroma = s-&gt;dummy_integer_array[27];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeInKByte = s-&gt;dummy_integer_array[9];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeY = s-&gt;dummy_integer_array[10];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeC = s-&gt;dummy_integer_array[11];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;full_swath_bytes_l = s-&gt;full_swath_bytes_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;full_swath_bytes_c = s-&gt;full_swath_bytes_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;UnboundedRequestEnabled = &amp;s-&gt;dummy_boolean[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;compbuf_reserved_space_64b = &amp;s-&gt;dummy_integer[1];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;hw_debug5 = &amp;s-&gt;dummy_boolean[2];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;CompressedBufferSizeInkByte = &amp;s-&gt;dummy_integer[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ViewportSizeSupportPerSurface = mode_lib-&gt;ms.SingleDPPViewportSizeSupportPerSurface;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ViewportSizeSupport = &amp;s-&gt;dummy_boolean[1];</div><div class='add'>+</div><div class='add'>+	// This calls is just to find out if there is enough DET space to support full vp in 1 pipe.</div><div class='add'>+	CalculateSwathAndDETConfiguration(&amp;mode_lib-&gt;scratch, CalculateSwathAndDETConfiguration_params);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TotalNumberOfActiveDPP = 0;</div><div class='add'>+	mode_lib-&gt;ms.TotalNumberOfActiveOPP = 0;</div><div class='add'>+	mode_lib-&gt;ms.support.TotalAvailablePipesSupport = true;</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		/*Number Of DSC Slices*/</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)</div><div class='add'>+				mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;</div><div class='add'>+			else {</div><div class='add'>+				if (s-&gt;PixelClockBackEnd[k] &gt; 4800) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = (unsigned int)(math_ceil2(s-&gt;PixelClockBackEnd[k] / 600, 4));</div><div class='add'>+				} else if (s-&gt;PixelClockBackEnd[k] &gt; 2400) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 8;</div><div class='add'>+				} else if (s-&gt;PixelClockBackEnd[k] &gt; 1200) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 4;</div><div class='add'>+				} else if (s-&gt;PixelClockBackEnd[k] &gt; 340) {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 2;</div><div class='add'>+				} else {</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 1;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		CalculateODMMode(</div><div class='add'>+			mode_lib-&gt;ip.maximum_pixels_per_line_per_dsc_unit,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode,</div><div class='add'>+			mode_lib-&gt;ms.max_dispclk_freq_mhz,</div><div class='add'>+			false, // DSCEnable</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfActiveDPP,</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfActiveOPP,</div><div class='add'>+			mode_lib-&gt;ip.max_num_dpp,</div><div class='add'>+			mode_lib-&gt;ip.max_num_opp,</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;s-&gt;TotalAvailablePipesSupportNoDSC,</div><div class='add'>+			&amp;s-&gt;NumberOfDPPNoDSC,</div><div class='add'>+			&amp;s-&gt;ODMModeNoDSC,</div><div class='add'>+			&amp;s-&gt;RequiredDISPCLKPerSurfaceNoDSC);</div><div class='add'>+</div><div class='add'>+		CalculateODMMode(</div><div class='add'>+			mode_lib-&gt;ip.maximum_pixels_per_line_per_dsc_unit,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode,</div><div class='add'>+			mode_lib-&gt;ms.max_dispclk_freq_mhz,</div><div class='add'>+			true, // DSCEnable</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfActiveDPP,</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfActiveOPP,</div><div class='add'>+			mode_lib-&gt;ip.max_num_dpp,</div><div class='add'>+			mode_lib-&gt;ip.max_num_opp,</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;s-&gt;TotalAvailablePipesSupportDSC,</div><div class='add'>+			&amp;s-&gt;NumberOfDPPDSC,</div><div class='add'>+			&amp;s-&gt;ODMModeDSC,</div><div class='add'>+			&amp;s-&gt;RequiredDISPCLKPerSurfaceDSC);</div><div class='add'>+</div><div class='add'>+		CalculateOutputLink(</div><div class='add'>+			&amp;mode_lib-&gt;scratch,</div><div class='add'>+			((double)mode_lib-&gt;soc.clk_table.phyclk.clk_values_khz[0] / 1000),</div><div class='add'>+			((double)mode_lib-&gt;soc.clk_table.phyclk_d18.clk_values_khz[0] / 1000),</div><div class='add'>+			((double)mode_lib-&gt;soc.clk_table.phyclk_d32.clk_values_khz[0] / 1000),</div><div class='add'>+			mode_lib-&gt;soc.phy_downspread_percent,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active,</div><div class='add'>+			s-&gt;PixelClockBackEnd[k],</div><div class='add'>+			s-&gt;OutputBpp[k],</div><div class='add'>+			mode_lib-&gt;ip.maximum_dsc_bits_per_component,</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.audio_sample_rate,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.audio_sample_layout,</div><div class='add'>+			s-&gt;ODMModeNoDSC,</div><div class='add'>+			s-&gt;ODMModeDSC,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_lane_count,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;mode_lib-&gt;ms.RequiresDSC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.RequiresFEC[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.OutputBpp[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.OutputType[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.OutputRate[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.RequiredSlots[k]);</div><div class='add'>+</div><div class='add'>+		if (s-&gt;OutputBpp[k] == 0.0) {</div><div class='add'>+			s-&gt;OutputBpp[k] = mode_lib-&gt;ms.OutputBpp[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.RequiresDSC[k] == false) {</div><div class='add'>+			mode_lib-&gt;ms.ODMMode[k] = s-&gt;ODMModeNoDSC;</div><div class='add'>+			mode_lib-&gt;ms.RequiredDISPCLKPerSurface[k] = s-&gt;RequiredDISPCLKPerSurfaceNoDSC;</div><div class='add'>+			if (!s-&gt;TotalAvailablePipesSupportNoDSC)</div><div class='add'>+				mode_lib-&gt;ms.support.TotalAvailablePipesSupport = false;</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfActiveDPP = mode_lib-&gt;ms.TotalNumberOfActiveDPP + s-&gt;NumberOfDPPNoDSC;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.ODMMode[k] = s-&gt;ODMModeDSC;</div><div class='add'>+			mode_lib-&gt;ms.RequiredDISPCLKPerSurface[k] = s-&gt;RequiredDISPCLKPerSurfaceDSC;</div><div class='add'>+			if (!s-&gt;TotalAvailablePipesSupportDSC)</div><div class='add'>+				mode_lib-&gt;ms.support.TotalAvailablePipesSupport = false;</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfActiveDPP = mode_lib-&gt;ms.TotalNumberOfActiveDPP + s-&gt;NumberOfDPPDSC;</div><div class='add'>+		}</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d RequiresDSC = %d\n", __func__, k, mode_lib-&gt;ms.RequiresDSC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d ODMMode = %d\n", __func__, k, mode_lib-&gt;ms.ODMMode[k]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		// ensure the number dsc slices is integer multiple based on ODM mode</div><div class='add'>+		mode_lib-&gt;ms.support.DSCSlicesODMModeSupported = true;</div><div class='add'>+		if (mode_lib-&gt;ms.RequiresDSC[k]) {</div><div class='add'>+			// fail a ms check if the override num_slices doesn't align with odm mode setting</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {</div><div class='add'>+				if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_2to1)</div><div class='add'>+					mode_lib-&gt;ms.support.DSCSlicesODMModeSupported = ((mode_lib-&gt;ms.support.NumberOfDSCSlices[k] % 2) == 0);</div><div class='add'>+				else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_3to1)</div><div class='add'>+					mode_lib-&gt;ms.support.DSCSlicesODMModeSupported = (mode_lib-&gt;ms.support.NumberOfDSCSlices[k] == 12);</div><div class='add'>+				else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_4to1)</div><div class='add'>+					mode_lib-&gt;ms.support.DSCSlicesODMModeSupported = ((mode_lib-&gt;ms.support.NumberOfDSCSlices[k] % 4) == 0);</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+				if (!mode_lib-&gt;ms.support.DSCSlicesODMModeSupported) {</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%d Invalid dsc num_slices and ODM mode setting\n", __func__, k);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%d ODMMode = %d\n", __func__, k, mode_lib-&gt;ms.ODMMode[k]);</div><div class='add'>+				}</div><div class='add'>+#endif</div><div class='add'>+			} else {</div><div class='add'>+				// safe guard to ensure the dml derived dsc slices and odm setting are compatible</div><div class='add'>+				if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_2to1)</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 2 * (unsigned int)math_ceil2(mode_lib-&gt;ms.support.NumberOfDSCSlices[k] / 2.0, 1.0);</div><div class='add'>+				else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_3to1)</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 12;</div><div class='add'>+				else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_4to1)</div><div class='add'>+					mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 4 * (unsigned int)math_ceil2(mode_lib-&gt;ms.support.NumberOfDSCSlices[k] / 4.0, 1.0);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k] = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.incorrect_imall_usage = 0;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (mode_lib-&gt;ip.imall_supported &amp;&amp; display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall)</div><div class='add'>+			mode_lib-&gt;ms.support.incorrect_imall_usage = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.MPCCombine[k] = false;</div><div class='add'>+		mode_lib-&gt;ms.NoOfDPP[k] = 1;</div><div class='add'>+		mode_lib-&gt;ms.NoOfOPP[k] = 1;</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_4to1) {</div><div class='add'>+			mode_lib-&gt;ms.MPCCombine[k] = false;</div><div class='add'>+			mode_lib-&gt;ms.NoOfDPP[k] = 4;</div><div class='add'>+			mode_lib-&gt;ms.NoOfOPP[k] = 4;</div><div class='add'>+		} else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_3to1) {</div><div class='add'>+			mode_lib-&gt;ms.MPCCombine[k] = false;</div><div class='add'>+			mode_lib-&gt;ms.NoOfDPP[k] = 3;</div><div class='add'>+			mode_lib-&gt;ms.NoOfOPP[k] = 3;</div><div class='add'>+		} else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_2to1) {</div><div class='add'>+			mode_lib-&gt;ms.MPCCombine[k] = false;</div><div class='add'>+			mode_lib-&gt;ms.NoOfDPP[k] = 2;</div><div class='add'>+			mode_lib-&gt;ms.NoOfOPP[k] = 2;</div><div class='add'>+		} else if (display_cfg-&gt;plane_descriptors[k].overrides.mpcc_combine_factor == 2) {</div><div class='add'>+			mode_lib-&gt;ms.MPCCombine[k] = true;</div><div class='add'>+			mode_lib-&gt;ms.NoOfDPP[k] = 2;</div><div class='add'>+		} else if (display_cfg-&gt;plane_descriptors[k].overrides.mpcc_combine_factor == 1) {</div><div class='add'>+			mode_lib-&gt;ms.MPCCombine[k] = false;</div><div class='add'>+			mode_lib-&gt;ms.NoOfDPP[k] = 1;</div><div class='add'>+			if (!mode_lib-&gt;ms.SingleDPPViewportSizeSupportPerSurface[k]) {</div><div class='add'>+				DML_LOG_VERBOSE("WARNING: DML::%s: MPCC is override to disable but viewport is too large to be supported with single pipe!\n", __func__);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			if ((mode_lib-&gt;ms.MinDPPCLKUsingSingleDPP[k] &gt; mode_lib-&gt;ms.max_dppclk_freq_mhz) || !mode_lib-&gt;ms.SingleDPPViewportSizeSupportPerSurface[k]) {</div><div class='add'>+				mode_lib-&gt;ms.MPCCombine[k] = true;</div><div class='add'>+				mode_lib-&gt;ms.NoOfDPP[k] = 2;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, NoOfDPP = %d\n", __func__, k, mode_lib-&gt;ms.NoOfDPP[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TotalNumberOfActiveDPP = 0;</div><div class='add'>+	mode_lib-&gt;ms.TotalNumberOfActiveOPP = 0;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.TotalNumberOfActiveDPP += mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+		mode_lib-&gt;ms.TotalNumberOfActiveOPP += mode_lib-&gt;ms.NoOfOPP[k];</div><div class='add'>+	}</div><div class='add'>+	if (mode_lib-&gt;ms.TotalNumberOfActiveDPP &gt; (unsigned int)mode_lib-&gt;ip.max_num_dpp)</div><div class='add'>+		mode_lib-&gt;ms.support.TotalAvailablePipesSupport = false;</div><div class='add'>+	if (mode_lib-&gt;ms.TotalNumberOfActiveOPP &gt; (unsigned int)mode_lib-&gt;ip.max_num_opp)</div><div class='add'>+		mode_lib-&gt;ms.support.TotalAvailablePipesSupport = false;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TotalNumberOfSingleDPPSurfaces = 0;</div><div class='add'>+	for (k = 0; k &lt; (unsigned int)mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (mode_lib-&gt;ms.NoOfDPP[k] == 1)</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfSingleDPPSurfaces = mode_lib-&gt;ms.TotalNumberOfSingleDPPSurfaces + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//DISPCLK/DPPCLK</div><div class='add'>+	mode_lib-&gt;ms.WritebackRequiredDISPCLK = 0;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			mode_lib-&gt;ms.WritebackRequiredDISPCLK = math_max2(mode_lib-&gt;ms.WritebackRequiredDISPCLK,</div><div class='add'>+				CalculateWriteBackDISPCLK(display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,</div><div class='add'>+					((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_width,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total,</div><div class='add'>+					mode_lib-&gt;ip.writeback_line_buffer_buffer_size));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.RequiredDISPCLK = mode_lib-&gt;ms.WritebackRequiredDISPCLK;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.RequiredDISPCLK = math_max2(mode_lib-&gt;ms.RequiredDISPCLK, mode_lib-&gt;ms.RequiredDISPCLKPerSurface[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.GlobalDPPCLK = 0;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.RequiredDPPCLK[k] = mode_lib-&gt;ms.MinDPPCLKUsingSingleDPP[k] / mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+		mode_lib-&gt;ms.GlobalDPPCLK = math_max2(mode_lib-&gt;ms.GlobalDPPCLK, mode_lib-&gt;ms.RequiredDPPCLK[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.DISPCLK_DPPCLK_Support = !((mode_lib-&gt;ms.RequiredDISPCLK &gt; mode_lib-&gt;ms.max_dispclk_freq_mhz) || (mode_lib-&gt;ms.GlobalDPPCLK &gt; mode_lib-&gt;ms.max_dppclk_freq_mhz));</div><div class='add'>+</div><div class='add'>+	/* Total Available OTG, Writeback, HDMIFRL, DP Support Check */</div><div class='add'>+	s-&gt;TotalNumberOfActiveOTG = 0;</div><div class='add'>+	s-&gt;TotalNumberOfActiveHDMIFRL = 0;</div><div class='add'>+	s-&gt;TotalNumberOfActiveDP2p0 = 0;</div><div class='add'>+	s-&gt;TotalNumberOfActiveDP2p0Outputs = 0;</div><div class='add'>+	s-&gt;TotalNumberOfActiveWriteback = 0;</div><div class='add'>+	memset(s-&gt;stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+			if (!s-&gt;stream_visited[display_cfg-&gt;plane_descriptors[k].stream_index]) {</div><div class='add'>+				s-&gt;stream_visited[display_cfg-&gt;plane_descriptors[k].stream_index] = 1;</div><div class='add'>+</div><div class='add'>+				if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0)</div><div class='add'>+					s-&gt;TotalNumberOfActiveWriteback = s-&gt;TotalNumberOfActiveWriteback + 1;</div><div class='add'>+</div><div class='add'>+				s-&gt;TotalNumberOfActiveOTG = s-&gt;TotalNumberOfActiveOTG + 1;</div><div class='add'>+				if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)</div><div class='add'>+					s-&gt;TotalNumberOfActiveHDMIFRL = s-&gt;TotalNumberOfActiveHDMIFRL + 1;</div><div class='add'>+				if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0) {</div><div class='add'>+					s-&gt;TotalNumberOfActiveDP2p0 = s-&gt;TotalNumberOfActiveDP2p0 + 1;</div><div class='add'>+					// FIXME_STAGE2: SW not using backend related stuff, need mapping for mst setup</div><div class='add'>+					//if (display_cfg-&gt;output.OutputMultistreamId[k] == k || display_cfg-&gt;output.OutputMultistreamEn[k] == false) {</div><div class='add'>+					s-&gt;TotalNumberOfActiveDP2p0Outputs = s-&gt;TotalNumberOfActiveDP2p0Outputs + 1;</div><div class='add'>+					//}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Writeback Mode Support Check */</div><div class='add'>+	mode_lib-&gt;ms.support.EnoughWritebackUnits = 1;</div><div class='add'>+	if (s-&gt;TotalNumberOfActiveWriteback &gt; (unsigned int)mode_lib-&gt;ip.max_num_wb) {</div><div class='add'>+		mode_lib-&gt;ms.support.EnoughWritebackUnits = false;</div><div class='add'>+	}</div><div class='add'>+	mode_lib-&gt;ms.support.NumberOfOTGSupport = (s-&gt;TotalNumberOfActiveOTG &lt;= (unsigned int)mode_lib-&gt;ip.max_num_otg);</div><div class='add'>+	mode_lib-&gt;ms.support.NumberOfHDMIFRLSupport = (s-&gt;TotalNumberOfActiveHDMIFRL &lt;= (unsigned int)mode_lib-&gt;ip.max_num_hdmi_frl_outputs);</div><div class='add'>+	mode_lib-&gt;ms.support.NumberOfDP2p0Support = (s-&gt;TotalNumberOfActiveDP2p0 &lt;= (unsigned int)mode_lib-&gt;ip.max_num_dp2p0_streams &amp;&amp; s-&gt;TotalNumberOfActiveDP2p0Outputs &lt;= (unsigned int)mode_lib-&gt;ip.max_num_dp2p0_outputs);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.ExceededMultistreamSlots = false;</div><div class='add'>+	mode_lib-&gt;ms.support.LinkCapacitySupport = true;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_disabled == false &amp;&amp;</div><div class='add'>+				(display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) &amp;&amp; mode_lib-&gt;ms.OutputBpp[k] == 0) {</div><div class='add'>+			mode_lib-&gt;ms.support.LinkCapacitySupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.P2IWith420 = false;</div><div class='add'>+	mode_lib-&gt;ms.support.DSCOnlyIfNecessaryWithBPP = false;</div><div class='add'>+	mode_lib-&gt;ms.support.DSC422NativeNotSupported = false;</div><div class='add'>+	mode_lib-&gt;ms.support.LinkRateDoesNotMatchDPVersion = false;</div><div class='add'>+	mode_lib-&gt;ms.support.LinkRateForMultistreamNotIndicated = false;</div><div class='add'>+	mode_lib-&gt;ms.support.BPPForMultistreamNotIndicated = false;</div><div class='add'>+	mode_lib-&gt;ms.support.MultistreamWithHDMIOreDP = false;</div><div class='add'>+	mode_lib-&gt;ms.support.MSOOrODMSplitWithNonDPLink = false;</div><div class='add'>+	mode_lib-&gt;ms.support.NotEnoughLanesForMSO = false;</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format == dml2_420 &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced == 1 &amp;&amp; mode_lib-&gt;ip.ptoi_supported == true)</div><div class='add'>+				mode_lib-&gt;ms.support.P2IWith420 = true;</div><div class='add'>+</div><div class='add'>+			if ((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format == dml2_n422 &amp;&amp; !mode_lib-&gt;ip.dsc422_native_support)</div><div class='add'>+				mode_lib-&gt;ms.support.DSC422NativeNotSupported = true;</div><div class='add'>+</div><div class='add'>+			if (((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr2 ||</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr3) &amp;&amp;</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder != dml2_dp &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder != dml2_edp) ||</div><div class='add'>+				((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr10 || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr13p5 ||</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr20) &amp;&amp;</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder != dml2_dp2p0))</div><div class='add'>+				mode_lib-&gt;ms.support.LinkRateDoesNotMatchDPVersion = true;</div><div class='add'>+</div><div class='add'>+			// FIXME_STAGE2</div><div class='add'>+			//if (display_cfg-&gt;output.OutputMultistreamEn[k] == 1) {</div><div class='add'>+			// if (display_cfg-&gt;output.OutputMultistreamId[k] == k &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_na)</div><div class='add'>+			// mode_lib-&gt;ms.support.LinkRateForMultistreamNotIndicated = true;</div><div class='add'>+			// if (display_cfg-&gt;output.OutputMultistreamId[k] == k &amp;&amp; s-&gt;OutputBpp[k] == 0)</div><div class='add'>+			// mode_lib-&gt;ms.support.BPPForMultistreamNotIndicated = true;</div><div class='add'>+			// for (n = 0; n &lt; mode_lib-&gt;ms.num_active_planes; ++n) {</div><div class='add'>+			// if (display_cfg-&gt;output.OutputMultistreamId[k] == n &amp;&amp; s-&gt;OutputBpp[k] == 0)</div><div class='add'>+			// mode_lib-&gt;ms.support.BPPForMultistreamNotIndicated = true;</div><div class='add'>+			// }</div><div class='add'>+			//}</div><div class='add'>+</div><div class='add'>+			if ((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi ||</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)) {</div><div class='add'>+				// FIXME_STAGE2</div><div class='add'>+				//if (display_cfg-&gt;output.OutputMultistreamEn[k] == 1 &amp;&amp; display_cfg-&gt;output.OutputMultistreamId[k] == k)</div><div class='add'>+				// mode_lib-&gt;ms.support.MultistreamWithHDMIOreDP = true;</div><div class='add'>+				//for (n = 0; n &lt; mode_lib-&gt;ms.num_active_planes; ++n) {</div><div class='add'>+				// if (display_cfg-&gt;output.OutputMultistreamEn[k] == 1 &amp;&amp; display_cfg-&gt;output.OutputMultistreamId[k] == n)</div><div class='add'>+				// mode_lib-&gt;ms.support.MultistreamWithHDMIOreDP = true;</div><div class='add'>+				//}</div><div class='add'>+			}</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder != dml2_dp &amp;&amp; (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_split_1to2 ||</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to2 || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to4))</div><div class='add'>+				mode_lib-&gt;ms.support.MSOOrODMSplitWithNonDPLink = true;</div><div class='add'>+</div><div class='add'>+			if ((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to2 &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_lane_count &lt; 2) ||</div><div class='add'>+				(display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to4 &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_dp_lane_count &lt; 4))</div><div class='add'>+				mode_lib-&gt;ms.support.NotEnoughLanesForMSO = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.DTBCLKRequiredMoreThanSupported = false;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl &amp;&amp;</div><div class='add'>+				!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+			mode_lib-&gt;ms.RequiredDTBCLK[k] = RequiredDTBCLK(</div><div class='add'>+				mode_lib-&gt;ms.RequiresDSC[k],</div><div class='add'>+				s-&gt;PixelClockBackEnd[k],</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format,</div><div class='add'>+				mode_lib-&gt;ms.OutputBpp[k],</div><div class='add'>+				mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.audio_sample_rate,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.audio_sample_layout);</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;ms.RequiredDTBCLK[k] &gt; ((double)min_clk_table-&gt;max_ss_clocks_khz.dtbclk / 1000)) {</div><div class='add'>+				mode_lib-&gt;ms.support.DTBCLKRequiredMoreThanSupported = true;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* Phantom DTBCLK can be calculated different from main because phantom has no DSC and thus</div><div class='add'>+			 * will have a different output BPP. Ignore phantom DTBCLK requirement and only consider</div><div class='add'>+			 * non-phantom DTBCLK requirements. In map_mode_to_soc_dpm we choose the highest DTBCLK</div><div class='add'>+			 * required - by setting phantom dtbclk to 0 we ignore it.</div><div class='add'>+			 */</div><div class='add'>+			mode_lib-&gt;ms.RequiredDTBCLK[k] = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.DSCCLKRequiredMoreThanSupported = false;</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp ||</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 ||</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format == dml2_420) {</div><div class='add'>+				s-&gt;DSCFormatFactor = 2;</div><div class='add'>+			} else if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format == dml2_444) {</div><div class='add'>+				s-&gt;DSCFormatFactor = 1;</div><div class='add'>+			} else if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format == dml2_n422 || display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {</div><div class='add'>+				s-&gt;DSCFormatFactor = 2;</div><div class='add'>+			} else {</div><div class='add'>+				s-&gt;DSCFormatFactor = 1;</div><div class='add'>+			}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, RequiresDSC = %u\n", __func__, k, mode_lib-&gt;ms.RequiresDSC[k]);</div><div class='add'>+#endif</div><div class='add'>+			if (mode_lib-&gt;ms.RequiresDSC[k] == true) {</div><div class='add'>+				s-&gt;PixelClockBackEndFactor = 3.0;</div><div class='add'>+</div><div class='add'>+				if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_4to1)</div><div class='add'>+					s-&gt;PixelClockBackEndFactor = 12.0;</div><div class='add'>+				else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_3to1)</div><div class='add'>+					s-&gt;PixelClockBackEndFactor = 9.0;</div><div class='add'>+				else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_2to1)</div><div class='add'>+					s-&gt;PixelClockBackEndFactor = 6.0;</div><div class='add'>+</div><div class='add'>+				mode_lib-&gt;ms.required_dscclk_freq_mhz[k] = s-&gt;PixelClockBackEnd[k] / s-&gt;PixelClockBackEndFactor / (double)s-&gt;DSCFormatFactor;</div><div class='add'>+				if (mode_lib-&gt;ms.required_dscclk_freq_mhz[k] &gt; mode_lib-&gt;ms.max_dscclk_freq_mhz) {</div><div class='add'>+					mode_lib-&gt;ms.support.DSCCLKRequiredMoreThanSupported = true;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, PixelClockBackEnd = %f\n", __func__, k, s-&gt;PixelClockBackEnd[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, required_dscclk_freq_mhz = %f\n", __func__, k, mode_lib-&gt;ms.required_dscclk_freq_mhz[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, DSCFormatFactor = %u\n", __func__, k, s-&gt;DSCFormatFactor);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, DSCCLKRequiredMoreThanSupported = %u\n", __func__, k, mode_lib-&gt;ms.support.DSCCLKRequiredMoreThanSupported);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check DSC Unit and Slices Support */</div><div class='add'>+	mode_lib-&gt;ms.support.NotEnoughDSCSlices = false;</div><div class='add'>+	s-&gt;TotalDSCUnitsRequired = 0;</div><div class='add'>+	mode_lib-&gt;ms.support.PixelsPerLinePerDSCUnitSupport = true;</div><div class='add'>+	memset(s-&gt;stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (mode_lib-&gt;ms.RequiresDSC[k] == true &amp;&amp; !s-&gt;stream_visited[display_cfg-&gt;plane_descriptors[k].stream_index]) {</div><div class='add'>+			s-&gt;NumDSCUnitRequired = 1;</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_4to1)</div><div class='add'>+				s-&gt;NumDSCUnitRequired = 4;</div><div class='add'>+			else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_3to1)</div><div class='add'>+				s-&gt;NumDSCUnitRequired = 3;</div><div class='add'>+			else if (mode_lib-&gt;ms.ODMMode[k] == dml2_odm_mode_combine_2to1)</div><div class='add'>+				s-&gt;NumDSCUnitRequired = 2;</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active &gt; s-&gt;NumDSCUnitRequired * (unsigned int)mode_lib-&gt;ip.maximum_pixels_per_line_per_dsc_unit)</div><div class='add'>+				mode_lib-&gt;ms.support.PixelsPerLinePerDSCUnitSupport = false;</div><div class='add'>+			s-&gt;TotalDSCUnitsRequired = s-&gt;TotalDSCUnitsRequired + s-&gt;NumDSCUnitRequired;</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;ms.support.NumberOfDSCSlices[k] &gt; 4 * s-&gt;NumDSCUnitRequired)</div><div class='add'>+				mode_lib-&gt;ms.support.NotEnoughDSCSlices = true;</div><div class='add'>+		}</div><div class='add'>+		s-&gt;stream_visited[display_cfg-&gt;plane_descriptors[k].stream_index] = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.NotEnoughDSCUnits = false;</div><div class='add'>+	if (s-&gt;TotalDSCUnitsRequired &gt; (unsigned int)mode_lib-&gt;ip.num_dsc) {</div><div class='add'>+		mode_lib-&gt;ms.support.NotEnoughDSCUnits = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*DSC Delay per state*/</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.DSCDelay[k] = DSCDelayRequirement(mode_lib-&gt;ms.RequiresDSC[k],</div><div class='add'>+			mode_lib-&gt;ms.ODMMode[k],</div><div class='add'>+			mode_lib-&gt;ip.maximum_dsc_bits_per_component,</div><div class='add'>+			s-&gt;OutputBpp[k],</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total,</div><div class='add'>+			mode_lib-&gt;ms.support.NumberOfDSCSlices[k],</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder,</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+			s-&gt;PixelClockBackEnd[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Figure out the swath and DET configuration after the num dpp per plane is figured out</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ForceSingleDPP = false;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ODMMode = mode_lib-&gt;ms.ODMMode;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DPPPerSurface = mode_lib-&gt;ms.NoOfDPP;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;req_per_swath_ub_l = s-&gt;dummy_integer_array[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;req_per_swath_ub_c = s-&gt;dummy_integer_array[1];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;swath_width_luma_ub = mode_lib-&gt;ms.swath_width_luma_ub;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;swath_width_chroma_ub = mode_lib-&gt;ms.swath_width_chroma_ub;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathWidth = mode_lib-&gt;ms.SwathWidthY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathWidthChroma = mode_lib-&gt;ms.SwathWidthC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathHeightY = mode_lib-&gt;ms.SwathHeightY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathHeightC = mode_lib-&gt;ms.SwathHeightC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;request_size_bytes_luma = mode_lib-&gt;ms.support.request_size_bytes_luma;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;request_size_bytes_chroma = mode_lib-&gt;ms.support.request_size_bytes_chroma;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeInKByte = mode_lib-&gt;ms.DETBufferSizeInKByte; // FIXME: This is per pipe but the pipes in plane will use that</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeY = mode_lib-&gt;ms.DETBufferSizeY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeC = mode_lib-&gt;ms.DETBufferSizeC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;UnboundedRequestEnabled = &amp;mode_lib-&gt;ms.UnboundedRequestEnabled;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;compbuf_reserved_space_64b = s-&gt;dummy_integer_array[3];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;hw_debug5 = s-&gt;dummy_boolean_array[1];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;CompressedBufferSizeInkByte = &amp;mode_lib-&gt;ms.CompressedBufferSizeInkByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ViewportSizeSupportPerSurface = s-&gt;dummy_boolean_array[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ViewportSizeSupport = &amp;mode_lib-&gt;ms.support.ViewportSizeSupport;</div><div class='add'>+</div><div class='add'>+	CalculateSwathAndDETConfiguration(&amp;mode_lib-&gt;scratch, CalculateSwathAndDETConfiguration_params);</div><div class='add'>+</div><div class='add'>+	if (mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes == 0) {</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++)</div><div class='add'>+			mode_lib-&gt;ms.SurfaceSizeInMALL[k] = 0;</div><div class='add'>+		mode_lib-&gt;ms.support.ExceededMALLSize = 0;</div><div class='add'>+	} else {</div><div class='add'>+		CalculateSurfaceSizeInMall(</div><div class='add'>+			display_cfg,</div><div class='add'>+			mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+			mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes,</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;ms.BytePerPixelY,</div><div class='add'>+			mode_lib-&gt;ms.BytePerPixelC,</div><div class='add'>+			mode_lib-&gt;ms.Read256BlockWidthY,</div><div class='add'>+			mode_lib-&gt;ms.Read256BlockWidthC,</div><div class='add'>+			mode_lib-&gt;ms.Read256BlockHeightY,</div><div class='add'>+			mode_lib-&gt;ms.Read256BlockHeightC,</div><div class='add'>+			mode_lib-&gt;ms.MacroTileWidthY,</div><div class='add'>+			mode_lib-&gt;ms.MacroTileWidthC,</div><div class='add'>+			mode_lib-&gt;ms.MacroTileHeightY,</div><div class='add'>+			mode_lib-&gt;ms.MacroTileHeightC,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			mode_lib-&gt;ms.SurfaceSizeInMALL,</div><div class='add'>+			&amp;mode_lib-&gt;ms.support.ExceededMALLSize);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TotalNumberOfDCCActiveDPP = 0;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].surface.dcc.enable == true) {</div><div class='add'>+			mode_lib-&gt;ms.TotalNumberOfDCCActiveDPP = mode_lib-&gt;ms.TotalNumberOfDCCActiveDPP + mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		s-&gt;SurfParameters[k].PixelClock = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+		s-&gt;SurfParameters[k].DPPPerSurface = mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+		s-&gt;SurfParameters[k].RotationAngle = display_cfg-&gt;plane_descriptors[k].composition.rotation_angle;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportHeight = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportHeightC = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height;</div><div class='add'>+		s-&gt;SurfParameters[k].BlockWidth256BytesY = mode_lib-&gt;ms.Read256BlockWidthY[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockHeight256BytesY = mode_lib-&gt;ms.Read256BlockHeightY[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockWidth256BytesC = mode_lib-&gt;ms.Read256BlockWidthC[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockHeight256BytesC = mode_lib-&gt;ms.Read256BlockHeightC[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockWidthY = mode_lib-&gt;ms.MacroTileWidthY[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockHeightY = mode_lib-&gt;ms.MacroTileHeightY[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockWidthC = mode_lib-&gt;ms.MacroTileWidthC[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BlockHeightC = mode_lib-&gt;ms.MacroTileHeightC[k];</div><div class='add'>+		s-&gt;SurfParameters[k].InterlaceEnable = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced;</div><div class='add'>+		s-&gt;SurfParameters[k].HTotal = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+		s-&gt;SurfParameters[k].DCCEnable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+		s-&gt;SurfParameters[k].SourcePixelFormat = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+		s-&gt;SurfParameters[k].SurfaceTiling = display_cfg-&gt;plane_descriptors[k].surface.tiling;</div><div class='add'>+		s-&gt;SurfParameters[k].BytePerPixelY = mode_lib-&gt;ms.BytePerPixelY[k];</div><div class='add'>+		s-&gt;SurfParameters[k].BytePerPixelC = mode_lib-&gt;ms.BytePerPixelC[k];</div><div class='add'>+		s-&gt;SurfParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib-&gt;ip.ptoi_supported;</div><div class='add'>+		s-&gt;SurfParameters[k].VRatio = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		s-&gt;SurfParameters[k].VRatioChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		s-&gt;SurfParameters[k].VTaps = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps;</div><div class='add'>+		s-&gt;SurfParameters[k].VTapsChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps;</div><div class='add'>+		s-&gt;SurfParameters[k].PitchY = display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch;</div><div class='add'>+		s-&gt;SurfParameters[k].PitchC = display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportStationary = display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportXStart = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.x_start;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportYStart = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.y_start;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportXStartC = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+		s-&gt;SurfParameters[k].ViewportYStartC = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+		s-&gt;SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = display_cfg-&gt;plane_descriptors[k].overrides.hw.force_one_row_for_frame;</div><div class='add'>+		s-&gt;SurfParameters[k].SwathHeightY = mode_lib-&gt;ms.SwathHeightY[k];</div><div class='add'>+		s-&gt;SurfParameters[k].SwathHeightC = mode_lib-&gt;ms.SwathHeightC[k];</div><div class='add'>+</div><div class='add'>+		s-&gt;SurfParameters[k].DCCMetaPitchY = display_cfg-&gt;plane_descriptors[k].surface.dcc.plane0.pitch;</div><div class='add'>+		s-&gt;SurfParameters[k].DCCMetaPitchC = display_cfg-&gt;plane_descriptors[k].surface.dcc.plane1.pitch;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;NumberOfActiveSurfaces = mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;myPipe = s-&gt;SurfParameters;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;SurfaceSizeInMALL = mode_lib-&gt;ms.SurfaceSizeInMALL;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeInRequestsLuma = mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_luma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeInRequestsChroma = mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;MALLAllocatedForDCN = mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;SwathWidthY = mode_lib-&gt;ms.SwathWidthY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;SwathWidthC = mode_lib-&gt;ms.SwathWidthC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;HostVMMinPageSize = mode_lib-&gt;soc.hostvm_min_page_size_kbytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;DCCMetaBufferSizeBytes = mode_lib-&gt;ip.dcc_meta_buffer_size_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeNotExceeded = mode_lib-&gt;ms.PTEBufferSizeNotExceeded;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_width_luma_ub = s-&gt;dummy_integer_array[12];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_width_chroma_ub = s-&gt;dummy_integer_array[13];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_luma = mode_lib-&gt;ms.dpte_row_height;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_chroma = mode_lib-&gt;ms.dpte_row_height_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_linear_luma = s-&gt;dummy_integer_array[14]; // VBA_DELTA</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_linear_chroma = s-&gt;dummy_integer_array[15]; // VBA_DELTA</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vm_group_bytes = s-&gt;dummy_integer_array[16];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_group_bytes = mode_lib-&gt;ms.dpte_group_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqWidthY = s-&gt;dummy_integer_array[17];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqHeightY = s-&gt;dummy_integer_array[18];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTERequestSizeY = s-&gt;dummy_integer_array[19];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqWidthC = s-&gt;dummy_integer_array[20];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqHeightC = s-&gt;dummy_integer_array[21];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTERequestSizeC = s-&gt;dummy_integer_array[22];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_width_y = s-&gt;vmpg_width_y;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_height_y = s-&gt;vmpg_height_y;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_width_c = s-&gt;vmpg_width_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_height_c = s-&gt;vmpg_height_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpde0_bytes_per_frame_ub_l = s-&gt;dummy_integer_array[23];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpde0_bytes_per_frame_ub_c = s-&gt;dummy_integer_array[24];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PrefetchSourceLinesY = mode_lib-&gt;ms.PrefetchLinesY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PrefetchSourceLinesC = mode_lib-&gt;ms.PrefetchLinesC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;VInitPreFillY = mode_lib-&gt;ms.PrefillY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;VInitPreFillC = mode_lib-&gt;ms.PrefillC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;MaxNumSwathY = mode_lib-&gt;ms.MaxNumSwathY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;MaxNumSwathC = mode_lib-&gt;ms.MaxNumSwathC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_bw = mode_lib-&gt;ms.dpte_row_bw;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEBytesPerRow = mode_lib-&gt;ms.DPTEBytesPerRow;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_bytes_per_row_l = s-&gt;dpte_row_bytes_per_row_l;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_bytes_per_row_c = s-&gt;dpte_row_bytes_per_row_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vm_bytes = mode_lib-&gt;ms.vm_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;use_one_row_for_frame = mode_lib-&gt;ms.use_one_row_for_frame;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;use_one_row_for_frame_flip = mode_lib-&gt;ms.use_one_row_for_frame_flip;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;is_using_mall_for_ss = s-&gt;dummy_boolean_array[0];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTE_BUFFER_MODE = s-&gt;dummy_boolean_array[1];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;BIGK_FRAGMENT_SIZE = s-&gt;dummy_integer_array[25];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;DCCMetaBufferSizeNotExceeded = mode_lib-&gt;ms.DCCMetaBufferSizeNotExceeded;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bw = mode_lib-&gt;ms.meta_row_bw;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bytes = mode_lib-&gt;ms.meta_row_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bytes_per_row_ub_l = s-&gt;meta_row_bytes_per_row_ub_l;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bytes_per_row_ub_c = s-&gt;meta_row_bytes_per_row_ub_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_width_luma = s-&gt;dummy_integer_array[26];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_height_luma = s-&gt;dummy_integer_array[27];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_width_luma = s-&gt;dummy_integer_array[28];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_height_luma = s-&gt;meta_row_height_luma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_pte_bytes_per_frame_ub_l = s-&gt;dummy_integer_array[29];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_width_chroma = s-&gt;dummy_integer_array[30];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_height_chroma = s-&gt;dummy_integer_array[31];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_width_chroma = s-&gt;dummy_integer_array[32];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_height_chroma = s-&gt;meta_row_height_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_pte_bytes_per_frame_ub_c = s-&gt;dummy_integer_array[33];</div><div class='add'>+</div><div class='add'>+	CalculateVMRowAndSwath(&amp;mode_lib-&gt;scratch, CalculateVMRowAndSwath_params);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.PTEBufferSizeNotExceeded = true;</div><div class='add'>+	mode_lib-&gt;ms.support.DCCMetaBufferSizeNotExceeded = true;</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (mode_lib-&gt;ms.PTEBufferSizeNotExceeded[k] == false)</div><div class='add'>+			mode_lib-&gt;ms.support.PTEBufferSizeNotExceeded = false;</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.DCCMetaBufferSizeNotExceeded[k] == false)</div><div class='add'>+			mode_lib-&gt;ms.support.DCCMetaBufferSizeNotExceeded = false;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, mode_lib-&gt;ms.PTEBufferSizeNotExceeded[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, DCCMetaBufferSizeNotExceeded = %u\n", __func__, k, mode_lib-&gt;ms.DCCMetaBufferSizeNotExceeded[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PTEBufferSizeNotExceeded = %u\n", __func__, mode_lib-&gt;ms.support.PTEBufferSizeNotExceeded);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCCMetaBufferSizeNotExceeded = %u\n", __func__, mode_lib-&gt;ms.support.DCCMetaBufferSizeNotExceeded);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	/* VActive bytes to fetch for UCLK P-State */</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;num_active_planes = mode_lib-&gt;ms.num_active_planes;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;num_of_dpp = mode_lib-&gt;ms.NoOfDPP;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_height_l = s-&gt;meta_row_height_luma;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_height_c = s-&gt;meta_row_height_chroma;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_bytes_per_row_ub_l = s-&gt;meta_row_bytes_per_row_ub_l;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_bytes_per_row_ub_c = s-&gt;meta_row_bytes_per_row_ub_c;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_row_height_l = mode_lib-&gt;ms.dpte_row_height;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_row_height_c = mode_lib-&gt;ms.dpte_row_height_chroma;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_bytes_per_row_l = s-&gt;dpte_row_bytes_per_row_l;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_bytes_per_row_c = s-&gt;dpte_row_bytes_per_row_c;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;byte_per_pix_l = mode_lib-&gt;ms.BytePerPixelY;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;byte_per_pix_c = mode_lib-&gt;ms.BytePerPixelC;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_width_l = mode_lib-&gt;ms.SwathWidthY;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_width_c = mode_lib-&gt;ms.SwathWidthC;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_height_l = mode_lib-&gt;ms.SwathHeightY;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_height_c = mode_lib-&gt;ms.SwathHeightC;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;latency_to_hide_us[0] = mode_lib-&gt;soc.power_management_parameters.dram_clk_change_blackout_us;</div><div class='add'>+</div><div class='add'>+	/* outputs */</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;bytes_required_l = s-&gt;pstate_bytes_required_l[dml2_pstate_type_uclk];</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;bytes_required_c = s-&gt;pstate_bytes_required_c[dml2_pstate_type_uclk];</div><div class='add'>+</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params);</div><div class='add'>+</div><div class='add'>+	/* Excess VActive bandwidth required to fill DET */</div><div class='add'>+	calculate_excess_vactive_bandwidth_required(</div><div class='add'>+			display_cfg,</div><div class='add'>+			mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+			s-&gt;pstate_bytes_required_l[dml2_pstate_type_uclk],</div><div class='add'>+			s-&gt;pstate_bytes_required_c[dml2_pstate_type_uclk],</div><div class='add'>+			/* outputs */</div><div class='add'>+			mode_lib-&gt;ms.excess_vactive_fill_bw_l,</div><div class='add'>+			mode_lib-&gt;ms.excess_vactive_fill_bw_c);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.UrgLatency = CalculateUrgentLatency(</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.base_latency_us,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.base_latency_pixel_vm_us,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.base_latency_vm_us,</div><div class='add'>+		mode_lib-&gt;soc.do_urgent_latency_adjustment,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.scaling_factor_fclk_us,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.scaling_factor_mhz,</div><div class='add'>+		mode_lib-&gt;ms.FabricClock,</div><div class='add'>+		mode_lib-&gt;ms.uclk_freq_mhz,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;ms.qos_param_index].urgent_ramp_uclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_urgent_ramp_latency_margin,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TripToMemory = CalculateTripToMemory(</div><div class='add'>+		mode_lib-&gt;ms.UrgLatency,</div><div class='add'>+		mode_lib-&gt;ms.FabricClock,</div><div class='add'>+		mode_lib-&gt;ms.uclk_freq_mhz,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;ms.qos_param_index].trip_to_memory_uclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.TripToMemory = math_max2(mode_lib-&gt;ms.UrgLatency, mode_lib-&gt;ms.TripToMemory);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		double line_time_us = (double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+		bool cursor_not_enough_urgent_latency_hiding = false;</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].cursor.num_cursors &gt; 0) {</div><div class='add'>+			calculate_cursor_req_attributes(</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].cursor.cursor_width,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].cursor.cursor_bpp,</div><div class='add'>+</div><div class='add'>+				// output</div><div class='add'>+				&amp;s-&gt;cursor_lines_per_chunk[k],</div><div class='add'>+				&amp;s-&gt;cursor_bytes_per_line[k],</div><div class='add'>+				&amp;s-&gt;cursor_bytes_per_chunk[k],</div><div class='add'>+				&amp;s-&gt;cursor_bytes[k]);</div><div class='add'>+</div><div class='add'>+			calculate_cursor_urgent_burst_factor(</div><div class='add'>+				mode_lib-&gt;ip.cursor_buffer_size,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].cursor.cursor_width,</div><div class='add'>+				s-&gt;cursor_bytes_per_chunk[k],</div><div class='add'>+				s-&gt;cursor_lines_per_chunk[k],</div><div class='add'>+				line_time_us,</div><div class='add'>+				mode_lib-&gt;ms.UrgLatency,</div><div class='add'>+</div><div class='add'>+				// output</div><div class='add'>+				&amp;mode_lib-&gt;ms.UrgentBurstFactorCursor[k],</div><div class='add'>+				&amp;cursor_not_enough_urgent_latency_hiding);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.UrgentBurstFactorCursorPre[k] = mode_lib-&gt;ms.UrgentBurstFactorCursor[k];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, Calling CalculateUrgentBurstFactor\n", __func__, k);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, VRatio=%f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, VRatioChroma=%f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		CalculateUrgentBurstFactor(</div><div class='add'>+			&amp;display_cfg-&gt;plane_descriptors[k],</div><div class='add'>+			mode_lib-&gt;ms.swath_width_luma_ub[k],</div><div class='add'>+			mode_lib-&gt;ms.swath_width_chroma_ub[k],</div><div class='add'>+			mode_lib-&gt;ms.SwathHeightY[k],</div><div class='add'>+			mode_lib-&gt;ms.SwathHeightC[k],</div><div class='add'>+			line_time_us,</div><div class='add'>+			mode_lib-&gt;ms.UrgLatency,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio,</div><div class='add'>+			mode_lib-&gt;ms.BytePerPixelInDETY[k],</div><div class='add'>+			mode_lib-&gt;ms.BytePerPixelInDETC[k],</div><div class='add'>+			mode_lib-&gt;ms.DETBufferSizeY[k],</div><div class='add'>+			mode_lib-&gt;ms.DETBufferSizeC[k],</div><div class='add'>+</div><div class='add'>+			// Output</div><div class='add'>+			&amp;mode_lib-&gt;ms.UrgentBurstFactorLuma[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.UrgentBurstFactorChroma[k],</div><div class='add'>+			&amp;mode_lib-&gt;ms.NotEnoughUrgentLatencyHiding[k]);</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;ms.NotEnoughUrgentLatencyHiding[k] = mode_lib-&gt;ms.NotEnoughUrgentLatencyHiding[k] || cursor_not_enough_urgent_latency_hiding;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateDCFCLKDeepSleep(</div><div class='add'>+		display_cfg,</div><div class='add'>+		mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+		mode_lib-&gt;ms.BytePerPixelY,</div><div class='add'>+		mode_lib-&gt;ms.BytePerPixelC,</div><div class='add'>+		mode_lib-&gt;ms.SwathWidthY,</div><div class='add'>+		mode_lib-&gt;ms.SwathWidthC,</div><div class='add'>+		mode_lib-&gt;ms.NoOfDPP,</div><div class='add'>+		mode_lib-&gt;ms.PSCL_FACTOR,</div><div class='add'>+		mode_lib-&gt;ms.PSCL_FACTOR_CHROMA,</div><div class='add'>+		mode_lib-&gt;ms.RequiredDPPCLK,</div><div class='add'>+		mode_lib-&gt;ms.vactive_sw_bw_l,</div><div class='add'>+		mode_lib-&gt;ms.vactive_sw_bw_c,</div><div class='add'>+		mode_lib-&gt;soc.return_bus_width_bytes,</div><div class='add'>+</div><div class='add'>+		/* Output */</div><div class='add'>+		&amp;mode_lib-&gt;ms.dcfclk_deepsleep);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			mode_lib-&gt;ms.WritebackDelayTime[k] = mode_lib-&gt;soc.qos_parameters.writeback.base_latency_us + CalculateWriteBackDelay(</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total) / mode_lib-&gt;ms.RequiredDISPCLK;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.WritebackDelayTime[k] = 0.0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// MaximumVStartup is actually Tvstartup_min in DCN4 programming guide</div><div class='add'>+	for (k = 0; k &lt;= mode_lib-&gt;ms.num_active_planes - 1; k++) {</div><div class='add'>+		bool isInterlaceTiming = (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced &amp;&amp; !mode_lib-&gt;ip.ptoi_supported);</div><div class='add'>+		s-&gt;MaximumVStartup[k] = CalculateMaxVStartup(</div><div class='add'>+			mode_lib-&gt;ip.ptoi_supported,</div><div class='add'>+			mode_lib-&gt;ip.vblank_nom_default_us,</div><div class='add'>+			&amp;display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing,</div><div class='add'>+			mode_lib-&gt;ms.WritebackDelayTime[k]);</div><div class='add'>+		mode_lib-&gt;ms.MaxVStartupLines[k] = (isInterlaceTiming ? (2 * s-&gt;MaximumVStartup[k]) : s-&gt;MaximumVStartup[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: k=%u, MaximumVStartup = %u\n", __func__, k, s-&gt;MaximumVStartup[k]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	/* Immediate Flip and MALL parameters */</div><div class='add'>+	s-&gt;ImmediateFlipRequired = false;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		s-&gt;ImmediateFlipRequired = s-&gt;ImmediateFlipRequired || display_cfg-&gt;plane_descriptors[k].immediate_flip;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = false;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe =</div><div class='add'>+			mode_lib-&gt;ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe ||</div><div class='add'>+			((display_cfg-&gt;hostvm_enable == true || display_cfg-&gt;plane_descriptors[k].immediate_flip == true) &amp;&amp;</div><div class='add'>+				(display_cfg-&gt;plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame || dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k])));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = false;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen = mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen ||</div><div class='add'>+			((display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable || display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_auto) &amp;&amp; (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k]))) ||</div><div class='add'>+			((display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_disable || display_cfg-&gt;plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_auto) &amp;&amp; (display_cfg-&gt;plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	s-&gt;FullFrameMALLPStateMethod = false;</div><div class='add'>+	s-&gt;SubViewportMALLPStateMethod = false;</div><div class='add'>+	s-&gt;PhantomPipeMALLPStateMethod = false;</div><div class='add'>+	s-&gt;SubViewportMALLRefreshGreaterThan120Hz = false;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame)</div><div class='add'>+			s-&gt;FullFrameMALLPStateMethod = true;</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) {</div><div class='add'>+			s-&gt;SubViewportMALLPStateMethod = true;</div><div class='add'>+			if (!display_cfg-&gt;overrides.enable_subvp_implicit_pmo) {</div><div class='add'>+				// For dv, small frame tests will have very high refresh rate</div><div class='add'>+				unsigned long long refresh_rate = (unsigned long long) ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz * 1000 /</div><div class='add'>+					(double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+					(double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total);</div><div class='add'>+				if (refresh_rate &gt; 120)</div><div class='add'>+					s-&gt;SubViewportMALLRefreshGreaterThan120Hz = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k]))</div><div class='add'>+			s-&gt;PhantomPipeMALLPStateMethod = true;</div><div class='add'>+	}</div><div class='add'>+	mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPState = (s-&gt;SubViewportMALLPStateMethod != s-&gt;PhantomPipeMALLPStateMethod) ||</div><div class='add'>+		(s-&gt;SubViewportMALLPStateMethod &amp;&amp; s-&gt;FullFrameMALLPStateMethod) || s-&gt;SubViewportMALLRefreshGreaterThan120Hz;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SubViewportMALLPStateMethod = %u\n", __func__, s-&gt;SubViewportMALLPStateMethod);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PhantomPipeMALLPStateMethod = %u\n", __func__, s-&gt;PhantomPipeMALLPStateMethod);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FullFrameMALLPStateMethod = %u\n", __func__, s-&gt;FullFrameMALLPStateMethod);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SubViewportMALLRefreshGreaterThan120Hz = %u\n", __func__, s-&gt;SubViewportMALLRefreshGreaterThan120Hz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: InvalidCombinationOfMALLUseForPState = %u\n", __func__, mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPState);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: in_out_params-&gt;min_clk_index = %u\n", __func__, in_out_params-&gt;min_clk_index);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mode_lib-&gt;ms.DCFCLK = %f\n", __func__, mode_lib-&gt;ms.DCFCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mode_lib-&gt;ms.FabricClock = %f\n", __func__, mode_lib-&gt;ms.FabricClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: mode_lib-&gt;ms.uclk_freq_mhz = %f\n", __func__, mode_lib-&gt;ms.uclk_freq_mhz);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.OutstandingRequestsSupport = true;</div><div class='add'>+	mode_lib-&gt;ms.support.OutstandingRequestsUrgencyAvoidance = true;</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.avg_urgent_latency_us</div><div class='add'>+		= (mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;ms.qos_param_index].average_latency_when_urgent_uclk_cycles / mode_lib-&gt;ms.uclk_freq_mhz</div><div class='add'>+			* (1 + mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_average_latency_margin / 100.0)</div><div class='add'>+			+ mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.average_transport_distance_fclk_cycles / mode_lib-&gt;ms.FabricClock)</div><div class='add'>+		* (1 + mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_average_transport_latency_margin / 100.0);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.avg_non_urgent_latency_us</div><div class='add'>+		= (mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;ms.qos_param_index].average_latency_when_non_urgent_uclk_cycles / mode_lib-&gt;ms.uclk_freq_mhz</div><div class='add'>+			* (1 + mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_average_latency_margin / 100.0)</div><div class='add'>+			+ mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.average_transport_distance_fclk_cycles / mode_lib-&gt;ms.FabricClock)</div><div class='add'>+		* (1 + mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_average_transport_latency_margin / 100.0);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.max_non_urgent_latency_us</div><div class='add'>+		= mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;ms.qos_param_index].maximum_latency_when_non_urgent_uclk_cycles</div><div class='add'>+		/ mode_lib-&gt;ms.uclk_freq_mhz * (1 + mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin / 100.0)</div><div class='add'>+		+ mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles / mode_lib-&gt;ms.FabricClock</div><div class='add'>+		+ mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib-&gt;ms.FabricClock</div><div class='add'>+		* (1 + mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin / 100.0);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+			outstanding_latency_us = (mode_lib-&gt;soc.max_outstanding_reqs * mode_lib-&gt;ms.support.request_size_bytes_luma[k]</div><div class='add'>+				/ (mode_lib-&gt;ms.DCFCLK * mode_lib-&gt;soc.return_bus_width_bytes));</div><div class='add'>+</div><div class='add'>+			if (outstanding_latency_us &lt; mode_lib-&gt;ms.support.avg_urgent_latency_us) {</div><div class='add'>+				mode_lib-&gt;ms.support.OutstandingRequestsSupport = false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (outstanding_latency_us &lt; mode_lib-&gt;ms.support.avg_non_urgent_latency_us) {</div><div class='add'>+				mode_lib-&gt;ms.support.OutstandingRequestsUrgencyAvoidance = false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: avg_urgent_latency_us = %f\n", __func__, mode_lib-&gt;ms.support.avg_urgent_latency_us);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: avg_non_urgent_latency_us = %f\n", __func__, mode_lib-&gt;ms.support.avg_non_urgent_latency_us);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_luma = %d\n", __func__, k, mode_lib-&gt;ms.support.request_size_bytes_luma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, outstanding_latency_us = %f (luma)\n", __func__, k, outstanding_latency_us);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x &amp;&amp; mode_lib-&gt;ms.BytePerPixelC[k] &gt; 0) {</div><div class='add'>+			outstanding_latency_us = (mode_lib-&gt;soc.max_outstanding_reqs * mode_lib-&gt;ms.support.request_size_bytes_chroma[k]</div><div class='add'>+				/ (mode_lib-&gt;ms.DCFCLK * mode_lib-&gt;soc.return_bus_width_bytes));</div><div class='add'>+</div><div class='add'>+			if (outstanding_latency_us &lt; mode_lib-&gt;ms.support.avg_urgent_latency_us) {</div><div class='add'>+				mode_lib-&gt;ms.support.OutstandingRequestsSupport = false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (outstanding_latency_us &lt; mode_lib-&gt;ms.support.avg_non_urgent_latency_us) {</div><div class='add'>+				mode_lib-&gt;ms.support.OutstandingRequestsUrgencyAvoidance = false;</div><div class='add'>+			}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_chroma = %d\n", __func__, k, mode_lib-&gt;ms.support.request_size_bytes_chroma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d, outstanding_latency_us = %f (chroma)\n", __func__, k, outstanding_latency_us);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(calculate_mcache_setting_params, 0, sizeof(struct dml2_core_calcs_calculate_mcache_setting_params));</div><div class='add'>+	if (mode_lib-&gt;soc.mcache_size_bytes == 0 || mode_lib-&gt;ip.dcn_mrq_present) {</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			mode_lib-&gt;ms.mall_prefetch_sdp_overhead_factor[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;ms.mall_prefetch_dram_overhead_factor[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p0[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p0[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p1[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p1[k] = 1.0;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_enable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+			calculate_mcache_setting_params-&gt;num_chans = mode_lib-&gt;soc.clk_table.dram_config.channel_count;</div><div class='add'>+			calculate_mcache_setting_params-&gt;mem_word_bytes = mode_lib-&gt;soc.mem_word_bytes;</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_size_bytes = mode_lib-&gt;soc.mcache_size_bytes;</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_line_size_bytes = mode_lib-&gt;soc.mcache_line_size_bytes;</div><div class='add'>+			calculate_mcache_setting_params-&gt;gpuvm_enable = display_cfg-&gt;gpuvm_enable;</div><div class='add'>+			calculate_mcache_setting_params-&gt;gpuvm_page_size_kbytes = display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;source_format = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+			calculate_mcache_setting_params-&gt;surf_vert = dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle);</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_stationary = display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary;</div><div class='add'>+			calculate_mcache_setting_params-&gt;tiling_mode = display_cfg-&gt;plane_descriptors[k].surface.tiling;</div><div class='add'>+			calculate_mcache_setting_params-&gt;imall_enable = mode_lib-&gt;ip.imall_supported &amp;&amp; display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall;</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_x_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.x_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_y_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.y_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_width_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_height_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height;</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_width_l = mode_lib-&gt;ms.MacroTileWidthY[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_height_l = mode_lib-&gt;ms.MacroTileHeightY[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_width_l = s-&gt;vmpg_width_y[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_height_l = s-&gt;vmpg_height_y[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_swath_bytes_l = s-&gt;full_swath_bytes_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;bytes_per_pixel_l = mode_lib-&gt;ms.BytePerPixelY[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_x_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.x_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_y_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_width_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.width;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_height_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height;</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_width_c = mode_lib-&gt;ms.MacroTileWidthC[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_height_c = mode_lib-&gt;ms.MacroTileHeightC[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_width_c = s-&gt;vmpg_width_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_height_c = s-&gt;vmpg_height_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_swath_bytes_c = s-&gt;full_swath_bytes_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;bytes_per_pixel_c = mode_lib-&gt;ms.BytePerPixelC[k];</div><div class='add'>+</div><div class='add'>+			// output</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_nom_overhead_factor_l = &amp;mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p0[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_pref_overhead_factor_l = &amp;mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p0[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_nom_overhead_factor_c = &amp;mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p1[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_pref_overhead_factor_c = &amp;mode_lib-&gt;ms.dcc_dram_bw_pref_overhead_factor_p1[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;num_mcaches_l = &amp;mode_lib-&gt;ms.num_mcaches_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_l = &amp;mode_lib-&gt;ms.mcache_row_bytes_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_per_channel_l = &amp;mode_lib-&gt;ms.mcache_row_bytes_per_channel_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_offsets_l = mode_lib-&gt;ms.mcache_offsets_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_shift_granularity_l = &amp;mode_lib-&gt;ms.mcache_shift_granularity_l[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;num_mcaches_c = &amp;mode_lib-&gt;ms.num_mcaches_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_c = &amp;mode_lib-&gt;ms.mcache_row_bytes_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_per_channel_c = &amp;mode_lib-&gt;ms.mcache_row_bytes_per_channel_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_offsets_c = mode_lib-&gt;ms.mcache_offsets_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_shift_granularity_c = &amp;mode_lib-&gt;ms.mcache_shift_granularity_c[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;mall_comb_mcache_l = &amp;mode_lib-&gt;ms.mall_comb_mcache_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mall_comb_mcache_c = &amp;mode_lib-&gt;ms.mall_comb_mcache_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;lc_comb_mcache = &amp;mode_lib-&gt;ms.lc_comb_mcache[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting(&amp;mode_lib-&gt;scratch, calculate_mcache_setting_params);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		calculate_mall_bw_overhead_factor(</div><div class='add'>+				mode_lib-&gt;ms.mall_prefetch_sdp_overhead_factor,</div><div class='add'>+				mode_lib-&gt;ms.mall_prefetch_dram_overhead_factor,</div><div class='add'>+</div><div class='add'>+				// input</div><div class='add'>+				display_cfg,</div><div class='add'>+				mode_lib-&gt;ms.num_active_planes);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Calculate all the bandwidth available</div><div class='add'>+	// Need anothe bw for latency evaluation</div><div class='add'>+	calculate_bandwidth_available(</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_available_min, // not used</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_available, // not used</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available_min_latency,</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available, // not used</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available_vm_only, // not used</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available_pixel_and_vm, // not used</div><div class='add'>+</div><div class='add'>+		&amp;mode_lib-&gt;soc,</div><div class='add'>+		display_cfg-&gt;hostvm_enable,</div><div class='add'>+		mode_lib-&gt;ms.DCFCLK,</div><div class='add'>+		mode_lib-&gt;ms.FabricClock,</div><div class='add'>+		mode_lib-&gt;ms.dram_bw_mbps);</div><div class='add'>+</div><div class='add'>+	calculate_bandwidth_available(</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_available_min,</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_available,</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available_min,</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available,</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available_vm_only,</div><div class='add'>+		mode_lib-&gt;ms.support.urg_bandwidth_available_pixel_and_vm,</div><div class='add'>+</div><div class='add'>+		&amp;mode_lib-&gt;soc,</div><div class='add'>+		display_cfg-&gt;hostvm_enable,</div><div class='add'>+		mode_lib-&gt;ms.MaxDCFCLK,</div><div class='add'>+		mode_lib-&gt;ms.MaxFabricClock,</div><div class='add'>+#ifdef DML_MODE_SUPPORT_USE_DPM_DRAM_BW</div><div class='add'>+		mode_lib-&gt;ms.dram_bw_mbps);</div><div class='add'>+#else</div><div class='add'>+		mode_lib-&gt;ms.max_dram_bw_mbps);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	// Average BW support check</div><div class='add'>+	calculate_avg_bandwidth_required(</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_required,</div><div class='add'>+		// input</div><div class='add'>+		display_cfg,</div><div class='add'>+		mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+		mode_lib-&gt;ms.vactive_sw_bw_l,</div><div class='add'>+		mode_lib-&gt;ms.vactive_sw_bw_c,</div><div class='add'>+		mode_lib-&gt;ms.cursor_bw,</div><div class='add'>+		mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+		mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+		mode_lib-&gt;ms.mall_prefetch_dram_overhead_factor,</div><div class='add'>+		mode_lib-&gt;ms.mall_prefetch_sdp_overhead_factor);</div><div class='add'>+</div><div class='add'>+	for (m = 0; m &lt; dml2_core_internal_bw_max; m++) { // check sdp and dram</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_support_ok[dml2_core_internal_soc_state_sys_idle][m] = 1;</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_support_ok[dml2_core_internal_soc_state_sys_active][m] = (mode_lib-&gt;ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][m] &lt;= mode_lib-&gt;ms.support.avg_bandwidth_available[dml2_core_internal_soc_state_sys_active][m]);</div><div class='add'>+		mode_lib-&gt;ms.support.avg_bandwidth_support_ok[dml2_core_internal_soc_state_svp_prefetch][m] = (mode_lib-&gt;ms.support.avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][m] &lt;= mode_lib-&gt;ms.support.avg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][m]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.AvgBandwidthSupport = true;</div><div class='add'>+	mode_lib-&gt;ms.support.EnoughUrgentLatencyHidingSupport = true;</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; ++k) {</div><div class='add'>+		if (mode_lib-&gt;ms.NotEnoughUrgentLatencyHiding[k]) {</div><div class='add'>+			mode_lib-&gt;ms.support.EnoughUrgentLatencyHidingSupport = false;</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u NotEnoughUrgentLatencyHiding set\n", __func__, k);</div><div class='add'>+</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	for (m = 0; m &lt; dml2_core_internal_soc_state_max; m++) {</div><div class='add'>+		for (n = 0; n &lt; dml2_core_internal_bw_max; n++) { // check sdp and dram</div><div class='add'>+			if (!mode_lib-&gt;ms.support.avg_bandwidth_support_ok[m][n] &amp;&amp; (m == dml2_core_internal_soc_state_sys_active || mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes &gt; 0)) {</div><div class='add'>+				mode_lib-&gt;ms.support.AvgBandwidthSupport = false;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: avg_bandwidth_support_ok[%s][%s] not ok\n", __func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n));</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dml_core_ms_prefetch_check(mode_lib, display_cfg);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;ms.support.max_urgent_latency_us = s-&gt;mSOCParameters.max_urgent_latency_us;</div><div class='add'>+</div><div class='add'>+	//Re-ordering Buffer Support Check</div><div class='add'>+	if (mode_lib-&gt;soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		if (((mode_lib-&gt;ip.rob_buffer_size_kbytes - mode_lib-&gt;ip.pixel_chunk_size_kbytes) * 1024</div><div class='add'>+			/ mode_lib-&gt;ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) &gt;= s-&gt;mSOCParameters.max_urgent_latency_us) {</div><div class='add'>+			mode_lib-&gt;ms.support.ROBSupport = true;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.support.ROBSupport = false;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (mode_lib-&gt;ip.rob_buffer_size_kbytes * 1024 &gt;= mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.loaded_round_trip_latency_fclk_cycles * mode_lib-&gt;soc.fabric_datapath_to_dcn_data_return_bytes) {</div><div class='add'>+			mode_lib-&gt;ms.support.ROBSupport = true;</div><div class='add'>+		} else {</div><div class='add'>+			mode_lib-&gt;ms.support.ROBSupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* VActive fill time calculations (informative) */</div><div class='add'>+	calculate_vactive_det_fill_latency(</div><div class='add'>+			display_cfg,</div><div class='add'>+			mode_lib-&gt;ms.num_active_planes,</div><div class='add'>+			s-&gt;pstate_bytes_required_l[dml2_pstate_type_uclk],</div><div class='add'>+			s-&gt;pstate_bytes_required_c[dml2_pstate_type_uclk],</div><div class='add'>+			mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p0,</div><div class='add'>+			mode_lib-&gt;ms.dcc_dram_bw_nom_overhead_factor_p1,</div><div class='add'>+			mode_lib-&gt;ms.vactive_sw_bw_l,</div><div class='add'>+			mode_lib-&gt;ms.vactive_sw_bw_c,</div><div class='add'>+			mode_lib-&gt;ms.surface_avg_vactive_required_bw,</div><div class='add'>+			mode_lib-&gt;ms.surface_peak_required_bw,</div><div class='add'>+			/* outputs */</div><div class='add'>+			mode_lib-&gt;ms.pstate_vactive_det_fill_delay_us[dml2_pstate_type_uclk]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_urgent_latency_us = %f\n", __func__, s-&gt;mSOCParameters.max_urgent_latency_us);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ROBSupport = %u\n", __func__, mode_lib-&gt;ms.support.ROBSupport);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	/*Mode Support, Voltage State and SOC Configuration*/</div><div class='add'>+	{</div><div class='add'>+		if (mode_lib-&gt;ms.support.ScaleRatioAndTapsSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.SourceFormatPixelAndScanSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.ViewportSizeSupport</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.LinkRateDoesNotMatchDPVersion</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.LinkRateForMultistreamNotIndicated</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.BPPForMultistreamNotIndicated</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.MultistreamWithHDMIOreDP</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.ExceededMultistreamSlots</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.MSOOrODMSplitWithNonDPLink</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.NotEnoughLanesForMSO</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.P2IWith420</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.DSC422NativeNotSupported</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.DSCSlicesODMModeSupported</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.NotEnoughDSCUnits</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.NotEnoughDSCSlices</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.DSCCLKRequiredMoreThanSupported</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.PixelsPerLinePerDSCUnitSupport</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.DTBCLKRequiredMoreThanSupported</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPState</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.ROBSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.OutstandingRequestsSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.OutstandingRequestsUrgencyAvoidance</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.DISPCLK_DPPCLK_Support</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.TotalAvailablePipesSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.NumberOfOTGSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.NumberOfHDMIFRLSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.NumberOfDP2p0Support</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.EnoughWritebackUnits</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.WritebackLatencySupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.WritebackScaleRatioAndTapsSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.CursorSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.PitchSupport</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.ViewportExceedsSurface</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.PrefetchSupported</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.EnoughUrgentLatencyHidingSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.AvgBandwidthSupport</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.DynamicMetadataSupported</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.VRatioInPrefetchSupported</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.PTEBufferSizeNotExceeded</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.DCCMetaBufferSizeNotExceeded</div><div class='add'>+			&amp;&amp; !mode_lib-&gt;ms.support.ExceededMALLSize</div><div class='add'>+			&amp;&amp; mode_lib-&gt;ms.support.g6_temp_read_support</div><div class='add'>+			&amp;&amp; ((!display_cfg-&gt;hostvm_enable &amp;&amp; !s-&gt;ImmediateFlipRequired) || mode_lib-&gt;ms.support.ImmediateFlipSupport)) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: mode is supported\n", __func__);</div><div class='add'>+			mode_lib-&gt;ms.support.ModeSupport = true;</div><div class='add'>+		} else {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: mode is NOT supported\n", __func__);</div><div class='add'>+			mode_lib-&gt;ms.support.ModeSupport = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Since now the mode_support work on 1 particular power state, so there is only 1 state idx (index 0).</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ModeSupport = %u\n", __func__, mode_lib-&gt;ms.support.ModeSupport);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ImmediateFlipSupport = %u\n", __func__, mode_lib-&gt;ms.support.ImmediateFlipSupport);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+		mode_lib-&gt;ms.support.MPCCombineEnable[k] = mode_lib-&gt;ms.MPCCombine[k];</div><div class='add'>+		mode_lib-&gt;ms.support.DPPPerSurface[k] = mode_lib-&gt;ms.NoOfDPP[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;ms.num_active_planes; k++) {</div><div class='add'>+		mode_lib-&gt;ms.support.ODMMode[k] = mode_lib-&gt;ms.ODMMode[k];</div><div class='add'>+		mode_lib-&gt;ms.support.DSCEnabled[k] = mode_lib-&gt;ms.RequiresDSC[k];</div><div class='add'>+		mode_lib-&gt;ms.support.FECEnabled[k] = mode_lib-&gt;ms.RequiresFEC[k];</div><div class='add'>+		mode_lib-&gt;ms.support.OutputBpp[k] = mode_lib-&gt;ms.OutputBpp[k];</div><div class='add'>+		mode_lib-&gt;ms.support.OutputType[k] = mode_lib-&gt;ms.OutputType[k];</div><div class='add'>+		mode_lib-&gt;ms.support.OutputRate[k] = mode_lib-&gt;ms.OutputRate[k];</div><div class='add'>+</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, ODMMode = %u\n", __func__, k, mode_lib-&gt;ms.support.ODMMode[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, DSCEnabled = %u\n", __func__, k, mode_lib-&gt;ms.support.DSCEnabled[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+	if (!mode_lib-&gt;ms.support.ModeSupport)</div><div class='add'>+		dml2_print_mode_support_info(&amp;mode_lib-&gt;ms.support, true);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: --- DONE --- \n", __func__);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return mode_lib-&gt;ms.support.ModeSupport;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_calcs_mode_support_ex(struct dml2_core_calcs_mode_support_ex *in_out_params)</div><div class='add'>+{</div><div class='add'>+	unsigned int result;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ------------- START ----------\n", __func__);</div><div class='add'>+	result = dml_core_mode_support(in_out_params);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		*in_out_params-&gt;out_evaluation_info = in_out_params-&gt;mode_lib-&gt;ms.support;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: is_mode_support = %u (min_clk_index=%d)\n", __func__, result, in_out_params-&gt;min_clk_index);</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; in_out_params-&gt;in_display_cfg-&gt;num_planes; k++)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, in_out_params-&gt;in_display_cfg-&gt;plane_descriptors[k].overrides.reserved_vblank_time_ns);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ------------- DONE ----------\n", __func__);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculatePixelDeliveryTimes(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	const struct core_display_cfg_support_info *cfg_support_info,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	double VRatioPrefetchY[],</div><div class='add'>+	double VRatioPrefetchC[],</div><div class='add'>+	unsigned int swath_width_luma_ub[],</div><div class='add'>+	unsigned int swath_width_chroma_ub[],</div><div class='add'>+	double PSCL_THROUGHPUT[],</div><div class='add'>+	double PSCL_THROUGHPUT_CHROMA[],</div><div class='add'>+	double Dppclk[],</div><div class='add'>+	unsigned int BytePerPixelC[],</div><div class='add'>+	unsigned int req_per_swath_ub_l[],</div><div class='add'>+	unsigned int req_per_swath_ub_c[],</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double DisplayPipeLineDeliveryTimeLuma[],</div><div class='add'>+	double DisplayPipeLineDeliveryTimeChroma[],</div><div class='add'>+	double DisplayPipeLineDeliveryTimeLumaPrefetch[],</div><div class='add'>+	double DisplayPipeLineDeliveryTimeChromaPrefetch[],</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeLuma[],</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeChroma[],</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeLumaPrefetch[],</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeChromaPrefetch[])</div><div class='add'>+{</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		double pixel_clock_mhz = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : HRatio = %f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : VRatio = %f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : HRatioChroma = %f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : VRatioChroma = %f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : VRatioPrefetchY = %f\n", __func__, k, VRatioPrefetchY[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : VRatioPrefetchC = %f\n", __func__, k, VRatioPrefetchC[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : swath_width_luma_ub = %u\n", __func__, k, swath_width_luma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : swath_width_chroma_ub = %u\n", __func__, k, swath_width_chroma_ub[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DPPPerSurface = %u\n", __func__, k, cfg_support_info-&gt;plane_support_info[k].dpps_used);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : pixel_clock_mhz = %f\n", __func__, k, pixel_clock_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : Dppclk = %f\n", __func__, k, Dppclk[k]);</div><div class='add'>+#endif</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio &lt;= 1) {</div><div class='add'>+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * cfg_support_info-&gt;plane_support_info[k].dpps_used / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_clock_mhz;</div><div class='add'>+		} else {</div><div class='add'>+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (BytePerPixelC[k] == 0) {</div><div class='add'>+			DisplayPipeLineDeliveryTimeChroma[k] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio &lt;= 1) {</div><div class='add'>+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * cfg_support_info-&gt;plane_support_info[k].dpps_used / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_clock_mhz;</div><div class='add'>+			} else {</div><div class='add'>+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (VRatioPrefetchY[k] &lt;= 1) {</div><div class='add'>+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * cfg_support_info-&gt;plane_support_info[k].dpps_used / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_clock_mhz;</div><div class='add'>+		} else {</div><div class='add'>+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (BytePerPixelC[k] == 0) {</div><div class='add'>+			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			if (VRatioPrefetchC[k] &lt;= 1) {</div><div class='add'>+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * cfg_support_info-&gt;plane_support_info[k].dpps_used / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_clock_mhz;</div><div class='add'>+			} else {</div><div class='add'>+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+</div><div class='add'>+		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub_l[k];</div><div class='add'>+		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub_l[k];</div><div class='add'>+		if (BytePerPixelC[k] == 0) {</div><div class='add'>+			DisplayPipeRequestDeliveryTimeChroma[k] = 0;</div><div class='add'>+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub_c[k];</div><div class='add'>+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub_c[k];</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : req_per_swath_ub_l = %d\n", __func__, k, req_per_swath_ub_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u : req_per_swath_ub_c = %d\n", __func__, k, req_per_swath_ub_c[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateMetaAndPTETimes(struct dml2_core_shared_CalculateMetaAndPTETimes_params *p)</div><div class='add'>+{</div><div class='add'>+	unsigned int meta_chunk_width;</div><div class='add'>+	unsigned int min_meta_chunk_width;</div><div class='add'>+	unsigned int meta_chunk_per_row_int;</div><div class='add'>+	unsigned int meta_row_remainder;</div><div class='add'>+	unsigned int meta_chunk_threshold;</div><div class='add'>+	unsigned int meta_chunks_per_row_ub;</div><div class='add'>+	unsigned int meta_chunk_width_chroma;</div><div class='add'>+	unsigned int min_meta_chunk_width_chroma;</div><div class='add'>+	unsigned int meta_chunk_per_row_int_chroma;</div><div class='add'>+	unsigned int meta_row_remainder_chroma;</div><div class='add'>+	unsigned int meta_chunk_threshold_chroma;</div><div class='add'>+	unsigned int meta_chunks_per_row_ub_chroma;</div><div class='add'>+	unsigned int dpte_group_width_luma;</div><div class='add'>+	unsigned int dpte_groups_per_row_luma_ub;</div><div class='add'>+	unsigned int dpte_group_width_chroma;</div><div class='add'>+	unsigned int dpte_groups_per_row_chroma_ub;</div><div class='add'>+	double pixel_clock_mhz;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		p-&gt;DST_Y_PER_PTE_ROW_NOM_L[k] = p-&gt;dpte_row_height[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		if (p-&gt;BytePerPixelC[k] == 0) {</div><div class='add'>+			p-&gt;DST_Y_PER_PTE_ROW_NOM_C[k] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;DST_Y_PER_PTE_ROW_NOM_C[k] = p-&gt;dpte_row_height_chroma[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		}</div><div class='add'>+		p-&gt;DST_Y_PER_META_ROW_NOM_L[k] = p-&gt;meta_row_height[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		if (p-&gt;BytePerPixelC[k] == 0) {</div><div class='add'>+			p-&gt;DST_Y_PER_META_ROW_NOM_C[k] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;DST_Y_PER_META_ROW_NOM_C[k] = p-&gt;meta_row_height_chroma[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.enable == true &amp;&amp; p-&gt;mrq_present) {</div><div class='add'>+			meta_chunk_width = p-&gt;MetaChunkSize * 1024 * 256 / p-&gt;BytePerPixelY[k] / p-&gt;meta_row_height[k];</div><div class='add'>+			min_meta_chunk_width = p-&gt;MinMetaChunkSizeBytes * 256 / p-&gt;BytePerPixelY[k] / p-&gt;meta_row_height[k];</div><div class='add'>+			meta_chunk_per_row_int = p-&gt;meta_row_width[k] / meta_chunk_width;</div><div class='add'>+			meta_row_remainder = p-&gt;meta_row_width[k] % meta_chunk_width;</div><div class='add'>+			if (!dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+				meta_chunk_threshold = 2 * min_meta_chunk_width - p-&gt;meta_req_width[k];</div><div class='add'>+			} else {</div><div class='add'>+				meta_chunk_threshold = 2 * min_meta_chunk_width - p-&gt;meta_req_height[k];</div><div class='add'>+			}</div><div class='add'>+			if (meta_row_remainder &lt;= meta_chunk_threshold) {</div><div class='add'>+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;</div><div class='add'>+			} else {</div><div class='add'>+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;</div><div class='add'>+			}</div><div class='add'>+			p-&gt;TimePerMetaChunkNominal[k] = p-&gt;meta_row_height[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio *</div><div class='add'>+				p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+				(p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;</div><div class='add'>+			p-&gt;TimePerMetaChunkVBlank[k] = p-&gt;dst_y_per_row_vblank[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+				(p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;</div><div class='add'>+			p-&gt;TimePerMetaChunkFlip[k] = p-&gt;dst_y_per_row_flip[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+				(p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;</div><div class='add'>+			if (p-&gt;BytePerPixelC[k] == 0) {</div><div class='add'>+				p-&gt;TimePerChromaMetaChunkNominal[k] = 0;</div><div class='add'>+				p-&gt;TimePerChromaMetaChunkVBlank[k] = 0;</div><div class='add'>+				p-&gt;TimePerChromaMetaChunkFlip[k] = 0;</div><div class='add'>+			} else {</div><div class='add'>+				meta_chunk_width_chroma = p-&gt;MetaChunkSize * 1024 * 256 / p-&gt;BytePerPixelC[k] / p-&gt;meta_row_height_chroma[k];</div><div class='add'>+				min_meta_chunk_width_chroma = p-&gt;MinMetaChunkSizeBytes * 256 / p-&gt;BytePerPixelC[k] / p-&gt;meta_row_height_chroma[k];</div><div class='add'>+				meta_chunk_per_row_int_chroma = (unsigned int)((double)p-&gt;meta_row_width_chroma[k] / meta_chunk_width_chroma);</div><div class='add'>+				meta_row_remainder_chroma = p-&gt;meta_row_width_chroma[k] % meta_chunk_width_chroma;</div><div class='add'>+				if (!dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - p-&gt;meta_req_width_chroma[k];</div><div class='add'>+				} else {</div><div class='add'>+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - p-&gt;meta_req_height_chroma[k];</div><div class='add'>+				}</div><div class='add'>+				if (meta_row_remainder_chroma &lt;= meta_chunk_threshold_chroma) {</div><div class='add'>+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1;</div><div class='add'>+				} else {</div><div class='add'>+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2;</div><div class='add'>+				}</div><div class='add'>+				p-&gt;TimePerChromaMetaChunkNominal[k] = p-&gt;meta_row_height_chroma[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / (p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;</div><div class='add'>+				p-&gt;TimePerChromaMetaChunkVBlank[k] = p-&gt;dst_y_per_row_vblank[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / (p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;</div><div class='add'>+				p-&gt;TimePerChromaMetaChunkFlip[k] = p-&gt;dst_y_per_row_flip[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / (p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;TimePerMetaChunkNominal[k] = 0;</div><div class='add'>+			p-&gt;TimePerMetaChunkVBlank[k] = 0;</div><div class='add'>+			p-&gt;TimePerMetaChunkFlip[k] = 0;</div><div class='add'>+			p-&gt;TimePerChromaMetaChunkNominal[k] = 0;</div><div class='add'>+			p-&gt;TimePerChromaMetaChunkVBlank[k] = 0;</div><div class='add'>+			p-&gt;TimePerChromaMetaChunkFlip[k] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, DST_Y_PER_META_ROW_NOM_L = %f\n", __func__, k, p-&gt;DST_Y_PER_META_ROW_NOM_L[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, DST_Y_PER_META_ROW_NOM_C = %f\n", __func__, k, p-&gt;DST_Y_PER_META_ROW_NOM_C[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkNominal		  = %f\n", __func__, k, p-&gt;TimePerMetaChunkNominal[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkVBlank		   = %f\n", __func__, k, p-&gt;TimePerMetaChunkVBlank[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkFlip			 = %f\n", __func__, k, p-&gt;TimePerMetaChunkFlip[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkNominal	= %f\n", __func__, k, p-&gt;TimePerChromaMetaChunkNominal[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkVBlank	 = %f\n", __func__, k, p-&gt;TimePerChromaMetaChunkVBlank[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkFlip	   = %f\n", __func__, k, p-&gt;TimePerChromaMetaChunkFlip[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		p-&gt;DST_Y_PER_PTE_ROW_NOM_L[k] = p-&gt;dpte_row_height[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		if (p-&gt;BytePerPixelC[k] == 0) {</div><div class='add'>+			p-&gt;DST_Y_PER_PTE_ROW_NOM_C[k] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;DST_Y_PER_PTE_ROW_NOM_C[k] = p-&gt;dpte_row_height_chroma[k] / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		pixel_clock_mhz = ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+</div><div class='add'>+		if (p-&gt;display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut)</div><div class='add'>+			p-&gt;time_per_tdlut_group[k] = 2 * p-&gt;dst_y_per_row_vblank[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / p-&gt;tdlut_groups_per_2row_ub[k];</div><div class='add'>+		else</div><div class='add'>+			p-&gt;time_per_tdlut_group[k] = 0;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_tdlut_group = %f\n", __func__, k, p-&gt;time_per_tdlut_group[k]);</div><div class='add'>+</div><div class='add'>+		if (p-&gt;display_cfg-&gt;gpuvm_enable == true) {</div><div class='add'>+			if (!dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+				dpte_group_width_luma = (unsigned int)((double)p-&gt;dpte_group_bytes[k] / (double)p-&gt;PTERequestSizeY[k] * p-&gt;PixelPTEReqWidthY[k]);</div><div class='add'>+			} else {</div><div class='add'>+				dpte_group_width_luma = (unsigned int)((double)p-&gt;dpte_group_bytes[k] / (double)p-&gt;PTERequestSizeY[k] * p-&gt;PixelPTEReqHeightY[k]);</div><div class='add'>+			}</div><div class='add'>+			if (p-&gt;use_one_row_for_frame[k]) {</div><div class='add'>+				dpte_groups_per_row_luma_ub = (unsigned int)(math_ceil2((double)p-&gt;dpte_row_width_luma_ub[k] / (double)dpte_group_width_luma / 2.0, 1.0));</div><div class='add'>+			} else {</div><div class='add'>+				dpte_groups_per_row_luma_ub = (unsigned int)(math_ceil2((double)p-&gt;dpte_row_width_luma_ub[k] / (double)dpte_group_width_luma, 1.0));</div><div class='add'>+			}</div><div class='add'>+			if (dpte_groups_per_row_luma_ub &lt;= 2) {</div><div class='add'>+				dpte_groups_per_row_luma_ub = dpte_groups_per_row_luma_ub + 1;</div><div class='add'>+			}</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p-&gt;use_one_row_for_frame[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_bytes = %u\n", __func__, k, p-&gt;dpte_group_bytes[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PTERequestSizeY = %u\n", __func__, k, p-&gt;PTERequestSizeY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEReqWidthY = %u\n", __func__, k, p-&gt;PixelPTEReqWidthY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEReqHeightY = %u\n", __func__, k, p-&gt;PixelPTEReqHeightY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p-&gt;dpte_row_width_luma_ub[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_width_luma = %u\n", __func__, k, dpte_group_width_luma);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, dpte_groups_per_row_luma_ub = %u\n", __func__, k, dpte_groups_per_row_luma_ub);</div><div class='add'>+</div><div class='add'>+			p-&gt;time_per_pte_group_nom_luma[k] = p-&gt;DST_Y_PER_PTE_ROW_NOM_L[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;</div><div class='add'>+			p-&gt;time_per_pte_group_vblank_luma[k] = p-&gt;dst_y_per_row_vblank[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;</div><div class='add'>+			p-&gt;time_per_pte_group_flip_luma[k] = p-&gt;dst_y_per_row_flip[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;</div><div class='add'>+			if (p-&gt;BytePerPixelC[k] == 0) {</div><div class='add'>+				p-&gt;time_per_pte_group_nom_chroma[k] = 0;</div><div class='add'>+				p-&gt;time_per_pte_group_vblank_chroma[k] = 0;</div><div class='add'>+				p-&gt;time_per_pte_group_flip_chroma[k] = 0;</div><div class='add'>+			} else {</div><div class='add'>+				if (!dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle)) {</div><div class='add'>+					dpte_group_width_chroma = (unsigned int)((double)p-&gt;dpte_group_bytes[k] / (double)p-&gt;PTERequestSizeC[k] * p-&gt;PixelPTEReqWidthC[k]);</div><div class='add'>+				} else {</div><div class='add'>+					dpte_group_width_chroma = (unsigned int)((double)p-&gt;dpte_group_bytes[k] / (double)p-&gt;PTERequestSizeC[k] * p-&gt;PixelPTEReqHeightC[k]);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if (p-&gt;use_one_row_for_frame[k]) {</div><div class='add'>+					dpte_groups_per_row_chroma_ub = (unsigned int)(math_ceil2((double)p-&gt;dpte_row_width_chroma_ub[k] / (double)dpte_group_width_chroma / 2.0, 1.0));</div><div class='add'>+				} else {</div><div class='add'>+					dpte_groups_per_row_chroma_ub = (unsigned int)(math_ceil2((double)p-&gt;dpte_row_width_chroma_ub[k] / (double)dpte_group_width_chroma, 1.0));</div><div class='add'>+				}</div><div class='add'>+				if (dpte_groups_per_row_chroma_ub &lt;= 2) {</div><div class='add'>+					dpte_groups_per_row_chroma_ub = dpte_groups_per_row_chroma_ub + 1;</div><div class='add'>+				}</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p-&gt;dpte_row_width_chroma_ub[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_width_chroma = %u\n", __func__, k, dpte_group_width_chroma);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, dpte_groups_per_row_chroma_ub = %u\n", __func__, k, dpte_groups_per_row_chroma_ub);</div><div class='add'>+</div><div class='add'>+				p-&gt;time_per_pte_group_nom_chroma[k] = p-&gt;DST_Y_PER_PTE_ROW_NOM_C[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;</div><div class='add'>+				p-&gt;time_per_pte_group_vblank_chroma[k] = p-&gt;dst_y_per_row_vblank[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;</div><div class='add'>+				p-&gt;time_per_pte_group_flip_chroma[k] = p-&gt;dst_y_per_row_flip[k] * p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			p-&gt;time_per_pte_group_nom_luma[k] = 0;</div><div class='add'>+			p-&gt;time_per_pte_group_vblank_luma[k] = 0;</div><div class='add'>+			p-&gt;time_per_pte_group_flip_luma[k] = 0;</div><div class='add'>+			p-&gt;time_per_pte_group_nom_chroma[k] = 0;</div><div class='add'>+			p-&gt;time_per_pte_group_vblank_chroma[k] = 0;</div><div class='add'>+			p-&gt;time_per_pte_group_flip_chroma[k] = 0;</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_row_vblank = %f\n", __func__, k, p-&gt;dst_y_per_row_vblank[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_row_flip = %f\n", __func__, k, p-&gt;dst_y_per_row_flip[k]);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_L = %f\n", __func__, k, p-&gt;DST_Y_PER_PTE_ROW_NOM_L[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_C = %f\n", __func__, k, p-&gt;DST_Y_PER_PTE_ROW_NOM_C[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_nom_luma = %f\n", __func__, k, p-&gt;time_per_pte_group_nom_luma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_vblank_luma = %f\n", __func__, k, p-&gt;time_per_pte_group_vblank_luma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_flip_luma = %f\n", __func__, k, p-&gt;time_per_pte_group_flip_luma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_nom_chroma = %f\n", __func__, k, p-&gt;time_per_pte_group_nom_chroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_vblank_chroma = %f\n", __func__, k, p-&gt;time_per_pte_group_vblank_chroma[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_flip_chroma = %f\n", __func__, k, p-&gt;time_per_pte_group_flip_chroma[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+} // CalculateMetaAndPTETimes</div><div class='add'>+</div><div class='add'>+static void CalculateVMGroupAndRequestTimes(</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	unsigned int NumberOfActiveSurfaces,</div><div class='add'>+	unsigned int BytePerPixelC[],</div><div class='add'>+	double dst_y_per_vm_vblank[],</div><div class='add'>+	double dst_y_per_vm_flip[],</div><div class='add'>+	unsigned int dpte_row_width_luma_ub[],</div><div class='add'>+	unsigned int dpte_row_width_chroma_ub[],</div><div class='add'>+	unsigned int vm_group_bytes[],</div><div class='add'>+	unsigned int dpde0_bytes_per_frame_ub_l[],</div><div class='add'>+	unsigned int dpde0_bytes_per_frame_ub_c[],</div><div class='add'>+	unsigned int tdlut_pte_bytes_per_frame[],</div><div class='add'>+	unsigned int meta_pte_bytes_per_frame_ub_l[],</div><div class='add'>+	unsigned int meta_pte_bytes_per_frame_ub_c[],</div><div class='add'>+	bool mrq_present,</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double TimePerVMGroupVBlank[],</div><div class='add'>+	double TimePerVMGroupFlip[],</div><div class='add'>+	double TimePerVMRequestVBlank[],</div><div class='add'>+	double TimePerVMRequestFlip[])</div><div class='add'>+{</div><div class='add'>+	unsigned int num_group_per_lower_vm_stage = 0;</div><div class='add'>+	unsigned int num_req_per_lower_vm_stage = 0;</div><div class='add'>+	unsigned int num_group_per_lower_vm_stage_flip;</div><div class='add'>+	unsigned int num_group_per_lower_vm_stage_pref;</div><div class='add'>+	unsigned int num_req_per_lower_vm_stage_flip;</div><div class='add'>+	unsigned int num_req_per_lower_vm_stage_pref;</div><div class='add'>+	double line_time;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfActiveSurfaces = %u\n", __func__, NumberOfActiveSurfaces);</div><div class='add'>+#endif</div><div class='add'>+	for (unsigned int k = 0; k &lt; NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		double pixel_clock_mhz = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+		bool dcc_mrq_enable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable &amp;&amp; mrq_present;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dcc_mrq_enable = %u\n", __func__, k, dcc_mrq_enable);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, vm_group_bytes = %u\n", __func__, k, vm_group_bytes[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dpde0_bytes_per_frame_ub_l = %u\n", __func__, k, dpde0_bytes_per_frame_ub_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, dpde0_bytes_per_frame_ub_c = %u\n", __func__, k, dpde0_bytes_per_frame_ub_c[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, meta_pte_bytes_per_frame_ub_l = %d\n", __func__, k, meta_pte_bytes_per_frame_ub_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d, meta_pte_bytes_per_frame_ub_c = %d\n", __func__, k, meta_pte_bytes_per_frame_ub_c[k]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;gpuvm_enable) {</div><div class='add'>+			if (display_cfg-&gt;gpuvm_max_page_table_levels &gt;= 2) {</div><div class='add'>+				num_group_per_lower_vm_stage += (unsigned int) math_ceil2((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);</div><div class='add'>+</div><div class='add'>+				if (BytePerPixelC[k] &gt; 0)</div><div class='add'>+					num_group_per_lower_vm_stage += (unsigned int) math_ceil2((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (dcc_mrq_enable) {</div><div class='add'>+				if (BytePerPixelC[k] &gt; 0) {</div><div class='add'>+					num_group_per_lower_vm_stage += (unsigned int)(2.0 /*for each mpde0 group*/ + math_ceil2((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) +</div><div class='add'>+																math_ceil2((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1));</div><div class='add'>+				} else {</div><div class='add'>+					num_group_per_lower_vm_stage += (unsigned int)(1.0 + math_ceil2((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1));</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			num_group_per_lower_vm_stage_flip = num_group_per_lower_vm_stage;</div><div class='add'>+			num_group_per_lower_vm_stage_pref = num_group_per_lower_vm_stage;</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut &amp;&amp; display_cfg-&gt;gpuvm_enable) {</div><div class='add'>+				num_group_per_lower_vm_stage_pref += (unsigned int) math_ceil2(tdlut_pte_bytes_per_frame[k] / vm_group_bytes[k], 1);</div><div class='add'>+				if (display_cfg-&gt;gpuvm_max_page_table_levels &gt;= 2)</div><div class='add'>+					num_group_per_lower_vm_stage_pref += 1; // tdpe0 group</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;gpuvm_max_page_table_levels &gt;= 2) {</div><div class='add'>+				num_req_per_lower_vm_stage += dpde0_bytes_per_frame_ub_l[k] / 64;</div><div class='add'>+				if (BytePerPixelC[k] &gt; 0)</div><div class='add'>+					num_req_per_lower_vm_stage += dpde0_bytes_per_frame_ub_c[k];</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (dcc_mrq_enable) {</div><div class='add'>+				num_req_per_lower_vm_stage += meta_pte_bytes_per_frame_ub_l[k] / 64;</div><div class='add'>+				if (BytePerPixelC[k] &gt; 0)</div><div class='add'>+					num_req_per_lower_vm_stage += meta_pte_bytes_per_frame_ub_c[k] / 64;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			num_req_per_lower_vm_stage_flip = num_req_per_lower_vm_stage;</div><div class='add'>+			num_req_per_lower_vm_stage_pref = num_req_per_lower_vm_stage;</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut &amp;&amp; display_cfg-&gt;gpuvm_enable) {</div><div class='add'>+				num_req_per_lower_vm_stage_pref += tdlut_pte_bytes_per_frame[k] / 64;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			line_time = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz;</div><div class='add'>+</div><div class='add'>+			if (num_group_per_lower_vm_stage_pref &gt; 0)</div><div class='add'>+				TimePerVMGroupVBlank[k] = dst_y_per_vm_vblank[k] * line_time / num_group_per_lower_vm_stage_pref;</div><div class='add'>+			else</div><div class='add'>+				TimePerVMGroupVBlank[k] = 0;</div><div class='add'>+</div><div class='add'>+			if (num_group_per_lower_vm_stage_flip &gt; 0)</div><div class='add'>+				TimePerVMGroupFlip[k] = dst_y_per_vm_flip[k] * line_time / num_group_per_lower_vm_stage_flip;</div><div class='add'>+			else</div><div class='add'>+				TimePerVMGroupFlip[k] = 0;</div><div class='add'>+</div><div class='add'>+			if (num_req_per_lower_vm_stage_pref &gt; 0)</div><div class='add'>+				TimePerVMRequestVBlank[k] = dst_y_per_vm_vblank[k] * line_time / num_req_per_lower_vm_stage_pref;</div><div class='add'>+			else</div><div class='add'>+				TimePerVMRequestVBlank[k] = 0.0;</div><div class='add'>+			if (num_req_per_lower_vm_stage_flip &gt; 0)</div><div class='add'>+				TimePerVMRequestFlip[k] = dst_y_per_vm_flip[k] * line_time / num_req_per_lower_vm_stage_flip;</div><div class='add'>+			else</div><div class='add'>+				TimePerVMRequestFlip[k] = 0.0;</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_vm_vblank = %f\n", __func__, k, dst_y_per_vm_vblank[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_vm_flip = %f\n", __func__, k, dst_y_per_vm_flip[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, line_time = %f\n", __func__, k, line_time);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, num_group_per_lower_vm_stage_pref = %d\n", __func__, k, num_group_per_lower_vm_stage_pref);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, num_group_per_lower_vm_stage_flip = %d\n", __func__, k, num_group_per_lower_vm_stage_flip);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, num_req_per_lower_vm_stage_pref = %d\n", __func__, k, num_req_per_lower_vm_stage_pref);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, num_req_per_lower_vm_stage_flip = %d\n", __func__, k, num_req_per_lower_vm_stage_flip);</div><div class='add'>+</div><div class='add'>+			if (display_cfg-&gt;gpuvm_max_page_table_levels &gt; 2) {</div><div class='add'>+				TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;</div><div class='add'>+				TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;</div><div class='add'>+				TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;</div><div class='add'>+				TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			TimePerVMGroupVBlank[k] = 0;</div><div class='add'>+			TimePerVMGroupFlip[k] = 0;</div><div class='add'>+			TimePerVMRequestVBlank[k] = 0;</div><div class='add'>+			TimePerVMRequestFlip[k] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void CalculateStutterEfficiency(struct dml2_core_internal_scratch *scratch,</div><div class='add'>+	struct dml2_core_calcs_CalculateStutterEfficiency_params *p)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_calcs_CalculateStutterEfficiency_locals *l = &amp;scratch-&gt;CalculateStutterEfficiency_locals;</div><div class='add'>+</div><div class='add'>+	unsigned int TotalNumberOfActiveOTG = 0;</div><div class='add'>+	double SinglePixelClock = 0;</div><div class='add'>+	unsigned int SingleHTotal = 0;</div><div class='add'>+	unsigned int SingleVTotal = 0;</div><div class='add'>+	bool SameTiming = true;</div><div class='add'>+	bool FoundCriticalSurface = false;</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_core_calcs_CalculateStutterEfficiency_locals));</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (!dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+			if (p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.enable == true) {</div><div class='add'>+				if ((dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; p-&gt;BlockWidth256BytesY[k] &gt; p-&gt;SwathHeightY[k]) || (!dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; p-&gt;BlockHeight256BytesY[k] &gt; p-&gt;SwathHeightY[k]) || p-&gt;DCCYMaxUncompressedBlock[k] &lt; 256) {</div><div class='add'>+					l-&gt;MaximumEffectiveCompressionLuma = 2;</div><div class='add'>+				} else {</div><div class='add'>+					l-&gt;MaximumEffectiveCompressionLuma = 4;</div><div class='add'>+				}</div><div class='add'>+				l-&gt;TotalCompressedReadBandwidth = l-&gt;TotalCompressedReadBandwidth + p-&gt;ReadBandwidthSurfaceLuma[k] / math_min2(p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.dcc_rate_plane0, l-&gt;MaximumEffectiveCompressionLuma);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p-&gt;ReadBandwidthSurfaceLuma[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, NetDCCRateLuma = %f\n", __func__, k, p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.dcc_rate_plane0);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, MaximumEffectiveCompressionLuma = %f\n", __func__, k, l-&gt;MaximumEffectiveCompressionLuma);</div><div class='add'>+#endif</div><div class='add'>+				l-&gt;TotalZeroSizeRequestReadBandwidth = l-&gt;TotalZeroSizeRequestReadBandwidth + p-&gt;ReadBandwidthSurfaceLuma[k] * p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane0;</div><div class='add'>+				l-&gt;TotalZeroSizeCompressedReadBandwidth = l-&gt;TotalZeroSizeCompressedReadBandwidth + p-&gt;ReadBandwidthSurfaceLuma[k] * p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane0 / l-&gt;MaximumEffectiveCompressionLuma;</div><div class='add'>+</div><div class='add'>+				if (p-&gt;ReadBandwidthSurfaceChroma[k] &gt; 0) {</div><div class='add'>+					if ((dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; p-&gt;BlockWidth256BytesC[k] &gt; p-&gt;SwathHeightC[k]) || (!dml_is_vertical_rotation(p-&gt;display_cfg-&gt;plane_descriptors[k].composition.rotation_angle) &amp;&amp; p-&gt;BlockHeight256BytesC[k] &gt; p-&gt;SwathHeightC[k]) || p-&gt;DCCCMaxUncompressedBlock[k] &lt; 256) {</div><div class='add'>+						l-&gt;MaximumEffectiveCompressionChroma = 2;</div><div class='add'>+					} else {</div><div class='add'>+						l-&gt;MaximumEffectiveCompressionChroma = 4;</div><div class='add'>+					}</div><div class='add'>+					l-&gt;TotalCompressedReadBandwidth = l-&gt;TotalCompressedReadBandwidth + p-&gt;ReadBandwidthSurfaceChroma[k] / math_min2(p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.dcc_rate_plane1, l-&gt;MaximumEffectiveCompressionChroma);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, p-&gt;ReadBandwidthSurfaceChroma[k]);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%u, NetDCCRateChroma = %f\n", __func__, k, p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.dcc_rate_plane1);</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%u, MaximumEffectiveCompressionChroma = %f\n", __func__, k, l-&gt;MaximumEffectiveCompressionChroma);</div><div class='add'>+#endif</div><div class='add'>+					l-&gt;TotalZeroSizeRequestReadBandwidth = l-&gt;TotalZeroSizeRequestReadBandwidth + p-&gt;ReadBandwidthSurfaceChroma[k] * p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane1;</div><div class='add'>+					l-&gt;TotalZeroSizeCompressedReadBandwidth = l-&gt;TotalZeroSizeCompressedReadBandwidth + p-&gt;ReadBandwidthSurfaceChroma[k] * p-&gt;display_cfg-&gt;plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane1 / l-&gt;MaximumEffectiveCompressionChroma;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				l-&gt;TotalCompressedReadBandwidth = l-&gt;TotalCompressedReadBandwidth + p-&gt;ReadBandwidthSurfaceLuma[k] + p-&gt;ReadBandwidthSurfaceChroma[k];</div><div class='add'>+			}</div><div class='add'>+			l-&gt;TotalRowReadBandwidth = l-&gt;TotalRowReadBandwidth + p-&gt;DPPPerSurface[k] * (p-&gt;meta_row_bw[k] + p-&gt;dpte_row_bw[k]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	l-&gt;AverageDCCCompressionRate = p-&gt;TotalDataReadBandwidth / l-&gt;TotalCompressedReadBandwidth;</div><div class='add'>+	l-&gt;AverageDCCZeroSizeFraction = l-&gt;TotalZeroSizeRequestReadBandwidth / p-&gt;TotalDataReadBandwidth;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: UnboundedRequestEnabled = %u\n", __func__, p-&gt;UnboundedRequestEnabled);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, l-&gt;TotalCompressedReadBandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, l-&gt;TotalZeroSizeRequestReadBandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n", __func__, l-&gt;TotalZeroSizeCompressedReadBandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, l-&gt;MaximumEffectiveCompressionLuma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, l-&gt;MaximumEffectiveCompressionChroma);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: AverageDCCCompressionRate = %f\n", __func__, l-&gt;AverageDCCCompressionRate);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, l-&gt;AverageDCCZeroSizeFraction);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: CompbufReservedSpace64B = %u (%f kbytes)\n", __func__, p-&gt;CompbufReservedSpace64B, p-&gt;CompbufReservedSpace64B * 64 / 1024.0);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: CompbufReservedSpaceZs = %u\n", __func__, p-&gt;CompbufReservedSpaceZs);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: CompressedBufferSizeInkByte = %u kbytes\n", __func__, p-&gt;CompressedBufferSizeInkByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ROBBufferSizeInKByte = %u kbytes\n", __func__, p-&gt;ROBBufferSizeInKByte);</div><div class='add'>+#endif</div><div class='add'>+	if (l-&gt;AverageDCCZeroSizeFraction == 1) {</div><div class='add'>+		l-&gt;AverageZeroSizeCompressionRate = l-&gt;TotalZeroSizeRequestReadBandwidth / l-&gt;TotalZeroSizeCompressedReadBandwidth;</div><div class='add'>+		l-&gt;EffectiveCompressedBufferSize = (double)p-&gt;MetaFIFOSizeInKEntries * 1024 * 64 * l-&gt;AverageZeroSizeCompressionRate + ((double)p-&gt;ZeroSizeBufferEntries - p-&gt;CompbufReservedSpaceZs) * 64 * l-&gt;AverageZeroSizeCompressionRate;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	} else if (l-&gt;AverageDCCZeroSizeFraction &gt; 0) {</div><div class='add'>+		l-&gt;AverageZeroSizeCompressionRate = l-&gt;TotalZeroSizeRequestReadBandwidth / l-&gt;TotalZeroSizeCompressedReadBandwidth;</div><div class='add'>+		l-&gt;EffectiveCompressedBufferSize = math_min2((double)p-&gt;CompressedBufferSizeInkByte * 1024 * l-&gt;AverageDCCCompressionRate,</div><div class='add'>+			(double)p-&gt;MetaFIFOSizeInKEntries * 1024 * 64 / (l-&gt;AverageDCCZeroSizeFraction / l-&gt;AverageZeroSizeCompressionRate + 1 / l-&gt;AverageDCCCompressionRate)) +</div><div class='add'>+			(p-&gt;rob_alloc_compressed ? math_min2(((double)p-&gt;ROBBufferSizeInKByte * 1024 - p-&gt;CompbufReservedSpace64B * 64) * l-&gt;AverageDCCCompressionRate,</div><div class='add'>+				((double)p-&gt;ZeroSizeBufferEntries - p-&gt;CompbufReservedSpaceZs) * 64 / (l-&gt;AverageDCCZeroSizeFraction / l-&gt;AverageZeroSizeCompressionRate))</div><div class='add'>+				: ((double)p-&gt;ROBBufferSizeInKByte * 1024 - p-&gt;CompbufReservedSpace64B * 64));</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min 1 = %f\n", __func__, p-&gt;CompressedBufferSizeInkByte * 1024 * l-&gt;AverageDCCCompressionRate);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min 2 = %f\n", __func__, p-&gt;MetaFIFOSizeInKEntries * 1024 * 64 / (l-&gt;AverageDCCZeroSizeFraction / l-&gt;AverageZeroSizeCompressionRate + 1 / l-&gt;AverageDCCCompressionRate));</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min 3 = %d\n", __func__, (p-&gt;ROBBufferSizeInKByte * 1024 - p-&gt;CompbufReservedSpace64B * 64));</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min 4 = %f\n", __func__, (p-&gt;ZeroSizeBufferEntries - p-&gt;CompbufReservedSpaceZs) * 64 / (l-&gt;AverageDCCZeroSizeFraction / l-&gt;AverageZeroSizeCompressionRate));</div><div class='add'>+#endif</div><div class='add'>+	} else {</div><div class='add'>+		l-&gt;EffectiveCompressedBufferSize = math_min2((double)p-&gt;CompressedBufferSizeInkByte * 1024 * l-&gt;AverageDCCCompressionRate,</div><div class='add'>+			(double)p-&gt;MetaFIFOSizeInKEntries * 1024 * 64 * l-&gt;AverageDCCCompressionRate) +</div><div class='add'>+			((double)p-&gt;ROBBufferSizeInKByte * 1024 - p-&gt;CompbufReservedSpace64B * 64) * (p-&gt;rob_alloc_compressed ? l-&gt;AverageDCCCompressionRate : 1.0);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min 1 = %f\n", __func__, p-&gt;CompressedBufferSizeInkByte * 1024 * l-&gt;AverageDCCCompressionRate);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: min 2 = %f\n", __func__, p-&gt;MetaFIFOSizeInKEntries * 1024 * 64 * l-&gt;AverageDCCCompressionRate);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: MetaFIFOSizeInKEntries = %u\n", __func__, p-&gt;MetaFIFOSizeInKEntries);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ZeroSizeBufferEntries = %u\n", __func__, p-&gt;ZeroSizeBufferEntries);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, l-&gt;AverageZeroSizeCompressionRate);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: EffectiveCompressedBufferSize = %f (%f kbytes)\n", __func__, l-&gt;EffectiveCompressedBufferSize, l-&gt;EffectiveCompressedBufferSize / 1024.0);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	*p-&gt;StutterPeriod = 0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (!dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+			l-&gt;LinesInDETY = ((double)p-&gt;DETBufferSizeY[k] + (p-&gt;UnboundedRequestEnabled == true ? l-&gt;EffectiveCompressedBufferSize : 0) * p-&gt;ReadBandwidthSurfaceLuma[k] / p-&gt;TotalDataReadBandwidth) / p-&gt;BytePerPixelDETY[k] / p-&gt;SwathWidthY[k];</div><div class='add'>+			l-&gt;LinesInDETYRoundedDownToSwath = math_floor2(l-&gt;LinesInDETY, p-&gt;SwathHeightY[k]);</div><div class='add'>+			l-&gt;DETBufferingTimeY = l-&gt;LinesInDETYRoundedDownToSwath * ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) / p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferSizeY = %u (%u kbytes)\n", __func__, k, p-&gt;DETBufferSizeY[k], p-&gt;DETBufferSizeY[k] / 1024);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p-&gt;BytePerPixelDETY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p-&gt;SwathWidthY[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p-&gt;ReadBandwidthSurfaceLuma[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, p-&gt;TotalDataReadBandwidth);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, LinesInDETY = %f\n", __func__, k, l-&gt;LinesInDETY);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, LinesInDETYRoundedDownToSwath = %f\n", __func__, k, l-&gt;LinesInDETYRoundedDownToSwath);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VRatio = %f\n", __func__, k, p-&gt;display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferingTimeY = %f\n", __func__, k, l-&gt;DETBufferingTimeY);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+			if (!FoundCriticalSurface || l-&gt;DETBufferingTimeY &lt; *p-&gt;StutterPeriod) {</div><div class='add'>+				bool isInterlaceTiming = p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced &amp;&amp; !p-&gt;ProgressiveToInterlaceUnitInOPP;</div><div class='add'>+</div><div class='add'>+				FoundCriticalSurface = true;</div><div class='add'>+				*p-&gt;StutterPeriod = l-&gt;DETBufferingTimeY;</div><div class='add'>+				l-&gt;FrameTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total / 2.0, 1.0) : p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total) * (double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+				l-&gt;VActiveTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active / 2.0, 1.0) : p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active) * (double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+				l-&gt;BytePerPixelYCriticalSurface = p-&gt;BytePerPixelY[k];</div><div class='add'>+				l-&gt;SwathWidthYCriticalSurface = p-&gt;SwathWidthY[k];</div><div class='add'>+				l-&gt;SwathHeightYCriticalSurface = p-&gt;SwathHeightY[k];</div><div class='add'>+				l-&gt;BlockWidth256BytesYCriticalSurface = p-&gt;BlockWidth256BytesY[k];</div><div class='add'>+				l-&gt;DETBufferSizeYCriticalSurface = p-&gt;DETBufferSizeY[k];</div><div class='add'>+				l-&gt;MinTTUVBlankCriticalSurface = p-&gt;MinTTUVBlank[k];</div><div class='add'>+				l-&gt;SinglePlaneCriticalSurface = (p-&gt;ReadBandwidthSurfaceChroma[k] == 0);</div><div class='add'>+				l-&gt;SinglePipeCriticalSurface = (p-&gt;DPPPerSurface[k] == 1);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, FoundCriticalSurface = %u\n", __func__, k, FoundCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, StutterPeriod = %f\n", __func__, k, *p-&gt;StutterPeriod);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlankCriticalSurface = %f\n", __func__, k, l-&gt;MinTTUVBlankCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, FrameTimeCriticalSurface= %f\n", __func__, k, l-&gt;FrameTimeCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, VActiveTimeCriticalSurface = %f\n", __func__, k, l-&gt;VActiveTimeCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelYCriticalSurface = %u\n", __func__, k, l-&gt;BytePerPixelYCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthYCriticalSurface = %f\n", __func__, k, l-&gt;SwathWidthYCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, SwathHeightYCriticalSurface = %f\n", __func__, k, l-&gt;SwathHeightYCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, BlockWidth256BytesYCriticalSurface = %u\n", __func__, k, l-&gt;BlockWidth256BytesYCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, SinglePlaneCriticalSurface = %u\n", __func__, k, l-&gt;SinglePlaneCriticalSurface);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, SinglePipeCriticalSurface = %u\n", __func__, k, l-&gt;SinglePipeCriticalSurface);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// for bounded req, the stutter period is calculated only based on DET size, but during burst there can be some return inside ROB/compressed buffer</div><div class='add'>+	// stutter period is calculated only on the det sizing</div><div class='add'>+	// if (cdb + rob &gt;= det) the stutter burst will be absorbed by the cdb + rob which is before decompress</div><div class='add'>+	// else</div><div class='add'>+	// the cdb + rob part will be in compressed rate with urg bw (idea bw)</div><div class='add'>+	// the det part will be return at uncompressed rate with 64B/dcfclk</div><div class='add'>+	//</div><div class='add'>+	// for unbounded req, the stutter period should be calculated as total of CDB+ROB+DET, so the term "PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer"</div><div class='add'>+	// should be == EffectiveCompressedBufferSize which will returned a compressed rate, the rest of stutter period is from the DET will be returned at uncompressed rate with 64B/dcfclk</div><div class='add'>+</div><div class='add'>+	l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = math_min2(*p-&gt;StutterPeriod * p-&gt;TotalDataReadBandwidth, l-&gt;EffectiveCompressedBufferSize);</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: AverageDCCCompressionRate = %f\n", __func__, l-&gt;AverageDCCCompressionRate);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterPeriod*TotalDataReadBandwidth = %f (%f kbytes)\n", __func__, *p-&gt;StutterPeriod * p-&gt;TotalDataReadBandwidth, (*p-&gt;StutterPeriod * p-&gt;TotalDataReadBandwidth) / 1024.0);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: EffectiveCompressedBufferSize = %f (%f kbytes)\n", __func__, l-&gt;EffectiveCompressedBufferSize, l-&gt;EffectiveCompressedBufferSize / 1024.0);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f (%f kbytes)\n", __func__, l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer, l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / 1024);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ReturnBW = %f\n", __func__, p-&gt;ReturnBW);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalDataReadBandwidth = %f\n", __func__, p-&gt;TotalDataReadBandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalRowReadBandwidth = %f\n", __func__, l-&gt;TotalRowReadBandwidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFCLK = %f\n", __func__, p-&gt;DCFCLK);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	l-&gt;StutterBurstTime = l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer</div><div class='add'>+		/ (p-&gt;ReturnBW * (p-&gt;hw_debug5 ? 1 : l-&gt;AverageDCCCompressionRate)) +</div><div class='add'>+		(*p-&gt;StutterPeriod * p-&gt;TotalDataReadBandwidth - l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer)</div><div class='add'>+		/ math_min2(p-&gt;DCFCLK * 64, p-&gt;ReturnBW * (p-&gt;hw_debug5 ? 1 : l-&gt;AverageDCCCompressionRate)) +</div><div class='add'>+		*p-&gt;StutterPeriod * l-&gt;TotalRowReadBandwidth / p-&gt;ReturnBW;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Part 1 = %f\n", __func__, l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / p-&gt;ReturnBW / (p-&gt;hw_debug5 ? 1 : l-&gt;AverageDCCCompressionRate));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Part 2 = %f\n", __func__, (*p-&gt;StutterPeriod * p-&gt;TotalDataReadBandwidth - l-&gt;PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p-&gt;DCFCLK * 64));</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Part 3 = %f\n", __func__, *p-&gt;StutterPeriod * l-&gt;TotalRowReadBandwidth / p-&gt;ReturnBW);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterBurstTime = %f\n", __func__, l-&gt;StutterBurstTime);</div><div class='add'>+#endif</div><div class='add'>+	l-&gt;TotalActiveWriteback = 0;</div><div class='add'>+	memset(l-&gt;stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; p-&gt;NumberOfActiveSurfaces; ++k) {</div><div class='add'>+		if (!dml_is_phantom_pipe(&amp;p-&gt;display_cfg-&gt;plane_descriptors[k])) {</div><div class='add'>+			if (!l-&gt;stream_visited[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index]) {</div><div class='add'>+</div><div class='add'>+				if (p-&gt;display_cfg-&gt;stream_descriptors[k].writeback.active_writebacks_per_stream &gt; 0)</div><div class='add'>+					l-&gt;TotalActiveWriteback = l-&gt;TotalActiveWriteback + 1;</div><div class='add'>+</div><div class='add'>+				if (TotalNumberOfActiveOTG == 0) { // first otg</div><div class='add'>+					SinglePixelClock = ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+					SingleHTotal = p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+					SingleVTotal = p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total;</div><div class='add'>+				} else if (SinglePixelClock != ((double)p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) ||</div><div class='add'>+							SingleHTotal != p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total ||</div><div class='add'>+							SingleVTotal != p-&gt;display_cfg-&gt;stream_descriptors[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total) {</div><div class='add'>+					SameTiming = false;</div><div class='add'>+				}</div><div class='add'>+				TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;</div><div class='add'>+				l-&gt;stream_visited[p-&gt;display_cfg-&gt;plane_descriptors[k].stream_index] = 1;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (l-&gt;TotalActiveWriteback == 0) {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: SRExitTime = %f\n", __func__, p-&gt;SRExitTime);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: SRExitZ8Time = %f\n", __func__, p-&gt;SRExitZ8Time);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: StutterPeriod = %f\n", __func__, *p-&gt;StutterPeriod);</div><div class='add'>+#endif</div><div class='add'>+		*p-&gt;StutterEfficiencyNotIncludingVBlank = math_max2(0., 1 - (p-&gt;SRExitTime + l-&gt;StutterBurstTime) / *p-&gt;StutterPeriod) * 100;</div><div class='add'>+		*p-&gt;Z8StutterEfficiencyNotIncludingVBlank = math_max2(0., 1 - (p-&gt;SRExitZ8Time + l-&gt;StutterBurstTime) / *p-&gt;StutterPeriod) * 100;</div><div class='add'>+		*p-&gt;NumberOfStutterBurstsPerFrame = (*p-&gt;StutterEfficiencyNotIncludingVBlank &gt; 0 ? (unsigned int)(math_ceil2(l-&gt;VActiveTimeCriticalSurface / *p-&gt;StutterPeriod, 1)) : 0);</div><div class='add'>+		*p-&gt;Z8NumberOfStutterBurstsPerFrame = (*p-&gt;Z8StutterEfficiencyNotIncludingVBlank &gt; 0 ? (unsigned int)(math_ceil2(l-&gt;VActiveTimeCriticalSurface / *p-&gt;StutterPeriod, 1)) : 0);</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;StutterEfficiencyNotIncludingVBlank = 0.;</div><div class='add'>+		*p-&gt;Z8StutterEfficiencyNotIncludingVBlank = 0.;</div><div class='add'>+		*p-&gt;NumberOfStutterBurstsPerFrame = 0;</div><div class='add'>+		*p-&gt;Z8NumberOfStutterBurstsPerFrame = 0;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: VActiveTimeCriticalSurface = %f\n", __func__, l-&gt;VActiveTimeCriticalSurface);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *p-&gt;StutterEfficiencyNotIncludingVBlank);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *p-&gt;Z8StutterEfficiencyNotIncludingVBlank);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: NumberOfStutterBurstsPerFrame = %u\n", __func__, *p-&gt;NumberOfStutterBurstsPerFrame);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8NumberOfStutterBurstsPerFrame = %u\n", __func__, *p-&gt;Z8NumberOfStutterBurstsPerFrame);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (*p-&gt;StutterEfficiencyNotIncludingVBlank &gt; 0) {</div><div class='add'>+		if (!((p-&gt;SynchronizeTimings || TotalNumberOfActiveOTG == 1) &amp;&amp; SameTiming)) {</div><div class='add'>+			*p-&gt;StutterEfficiency = *p-&gt;StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;StutterEfficiency = (1 - (*p-&gt;NumberOfStutterBurstsPerFrame * p-&gt;SRExitTime + l-&gt;StutterBurstTime * l-&gt;VActiveTimeCriticalSurface / *p-&gt;StutterPeriod) / l-&gt;FrameTimeCriticalSurface) * 100;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;StutterEfficiency = 0;</div><div class='add'>+		*p-&gt;NumberOfStutterBurstsPerFrame = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (*p-&gt;Z8StutterEfficiencyNotIncludingVBlank &gt; 0) {</div><div class='add'>+		//LastZ8StutterPeriod = l-&gt;VActiveTimeCriticalSurface - (*p-&gt;Z8NumberOfStutterBurstsPerFrame - 1) * *p-&gt;StutterPeriod;</div><div class='add'>+		if (!((p-&gt;SynchronizeTimings || TotalNumberOfActiveOTG == 1) &amp;&amp; SameTiming)) {</div><div class='add'>+			*p-&gt;Z8StutterEfficiency = *p-&gt;Z8StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+		} else {</div><div class='add'>+			*p-&gt;Z8StutterEfficiency = (1 - (*p-&gt;Z8NumberOfStutterBurstsPerFrame * p-&gt;SRExitZ8Time + l-&gt;StutterBurstTime * l-&gt;VActiveTimeCriticalSurface / *p-&gt;StutterPeriod) / l-&gt;FrameTimeCriticalSurface) * 100;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*p-&gt;Z8StutterEfficiency = 0.;</div><div class='add'>+		*p-&gt;Z8NumberOfStutterBurstsPerFrame = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: TotalNumberOfActiveOTG = %u\n", __func__, TotalNumberOfActiveOTG);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SameTiming = %u\n", __func__, SameTiming);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SynchronizeTimings = %u\n", __func__, p-&gt;SynchronizeTimings);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: LastZ8StutterPeriod = %f\n", __func__, *p-&gt;Z8StutterEfficiencyNotIncludingVBlank &gt; 0 ? l-&gt;VActiveTimeCriticalSurface - (*p-&gt;Z8NumberOfStutterBurstsPerFrame - 1) * *p-&gt;StutterPeriod : 0);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, p-&gt;Z8StutterEnterPlusExitWatermark);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterBurstTime = %f\n", __func__, l-&gt;StutterBurstTime);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterPeriod = %f\n", __func__, *p-&gt;StutterPeriod);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterEfficiency = %f\n", __func__, *p-&gt;StutterEfficiency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8StutterEfficiency = %f\n", __func__, *p-&gt;Z8StutterEfficiency);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *p-&gt;StutterEfficiencyNotIncludingVBlank);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Z8NumberOfStutterBurstsPerFrame = %u\n", __func__, *p-&gt;Z8NumberOfStutterBurstsPerFrame);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	*p-&gt;DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = !(!p-&gt;UnboundedRequestEnabled &amp;&amp; (p-&gt;NumberOfActiveSurfaces == 1) &amp;&amp; l-&gt;SinglePlaneCriticalSurface &amp;&amp; l-&gt;SinglePipeCriticalSurface);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DETBufferSizeYCriticalSurface = %u\n", __func__, l-&gt;DETBufferSizeYCriticalSurface);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: PixelChunkSizeInKByte = %u\n", __func__, p-&gt;PixelChunkSizeInKByte);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = %u\n", __func__, *p-&gt;DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex *in_out_params)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_display_cfg *display_cfg = in_out_params-&gt;in_display_cfg;</div><div class='add'>+	const struct dml2_mcg_min_clock_table *min_clk_table = in_out_params-&gt;min_clk_table;</div><div class='add'>+	const struct core_display_cfg_support_info *cfg_support_info = in_out_params-&gt;cfg_support_info;</div><div class='add'>+	struct dml2_core_internal_display_mode_lib *mode_lib = in_out_params-&gt;mode_lib;</div><div class='add'>+	struct dml2_display_cfg_programming *programming = in_out_params-&gt;programming;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_calcs_mode_programming_locals *s = &amp;mode_lib-&gt;scratch.dml_core_mode_programming_locals;</div><div class='add'>+	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params *CalculateWatermarks_params = &amp;mode_lib-&gt;scratch.CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateVMRowAndSwath_params *CalculateVMRowAndSwath_params = &amp;mode_lib-&gt;scratch.CalculateVMRowAndSwath_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params *CalculateSwathAndDETConfiguration_params = &amp;mode_lib-&gt;scratch.CalculateSwathAndDETConfiguration_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateStutterEfficiency_params *CalculateStutterEfficiency_params = &amp;mode_lib-&gt;scratch.CalculateStutterEfficiency_params;</div><div class='add'>+	struct dml2_core_calcs_CalculatePrefetchSchedule_params *CalculatePrefetchSchedule_params = &amp;mode_lib-&gt;scratch.CalculatePrefetchSchedule_params;</div><div class='add'>+	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params *CheckGlobalPrefetchAdmissibility_params = &amp;mode_lib-&gt;scratch.CheckGlobalPrefetchAdmissibility_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_setting_params *calculate_mcache_setting_params = &amp;mode_lib-&gt;scratch.calculate_mcache_setting_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_tdlut_setting_params *calculate_tdlut_setting_params = &amp;mode_lib-&gt;scratch.calculate_tdlut_setting_params;</div><div class='add'>+	struct dml2_core_shared_CalculateMetaAndPTETimes_params *CalculateMetaAndPTETimes_params = &amp;mode_lib-&gt;scratch.CalculateMetaAndPTETimes_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_peak_bandwidth_required_params *calculate_peak_bandwidth_params = &amp;mode_lib-&gt;scratch.calculate_peak_bandwidth_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params *calculate_bytes_to_fetch_required_to_hide_latency_params = &amp;mode_lib-&gt;scratch.calculate_bytes_to_fetch_required_to_hide_latency_params;</div><div class='add'>+</div><div class='add'>+	unsigned int k;</div><div class='add'>+	bool must_support_iflip;</div><div class='add'>+	const long min_return_uclk_cycles = 83;</div><div class='add'>+	const long min_return_fclk_cycles = 75;</div><div class='add'>+	const double max_fclk_mhz = min_clk_table-&gt;max_clocks_khz.fclk / 1000.0;</div><div class='add'>+	double hard_minimum_dcfclk_mhz = (double)min_clk_table-&gt;dram_bw_table.entries[0].min_dcfclk_khz / 1000.0;</div><div class='add'>+	double max_uclk_mhz = 0;</div><div class='add'>+	double min_return_latency_in_DCFCLK_cycles = 0;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: --- START --- \n", __func__);</div><div class='add'>+</div><div class='add'>+	memset(&amp;mode_lib-&gt;scratch, 0, sizeof(struct dml2_core_internal_scratch));</div><div class='add'>+	memset(&amp;mode_lib-&gt;mp, 0, sizeof(struct dml2_core_internal_mode_program));</div><div class='add'>+</div><div class='add'>+	s-&gt;num_active_planes = display_cfg-&gt;num_planes;</div><div class='add'>+	get_stream_output_bpp(s-&gt;OutputBpp, display_cfg);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.num_active_pipes = dml_get_num_active_pipes(display_cfg-&gt;num_planes, cfg_support_info);</div><div class='add'>+	dml_calc_pipe_plane_mapping(cfg_support_info, mode_lib-&gt;mp.pipe_plane);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.Dcfclk = programming-&gt;min_clocks.dcn4x.active.dcfclk_khz / 1000.0;</div><div class='add'>+	mode_lib-&gt;mp.FabricClock = programming-&gt;min_clocks.dcn4x.active.fclk_khz / 1000.0;</div><div class='add'>+	mode_lib-&gt;mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming-&gt;min_clocks.dcn4x.active.uclk_khz, &amp;mode_lib-&gt;soc.clk_table.dram_config);</div><div class='add'>+	mode_lib-&gt;mp.uclk_freq_mhz = programming-&gt;min_clocks.dcn4x.active.uclk_khz / 1000.0;</div><div class='add'>+	mode_lib-&gt;mp.GlobalDPPCLK = programming-&gt;min_clocks.dcn4x.dpprefclk_khz / 1000.0;</div><div class='add'>+	s-&gt;SOCCLK = (double)programming-&gt;min_clocks.dcn4x.socclk_khz / 1000;</div><div class='add'>+	mode_lib-&gt;mp.qos_param_index = get_qos_param_index(programming-&gt;min_clocks.dcn4x.active.uclk_khz, mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params);</div><div class='add'>+	mode_lib-&gt;mp.active_min_uclk_dpm_index = get_active_min_uclk_dpm_index(programming-&gt;min_clocks.dcn4x.active.uclk_khz, &amp;mode_lib-&gt;soc.clk_table);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		unsigned int stream_index = display_cfg-&gt;plane_descriptors[k].stream_index;</div><div class='add'>+		DML_ASSERT(cfg_support_info-&gt;stream_support_info[stream_index].odms_used &lt;= 4);</div><div class='add'>+		DML_ASSERT(cfg_support_info-&gt;stream_support_info[stream_index].num_odm_output_segments == 4 ||</div><div class='add'>+					cfg_support_info-&gt;stream_support_info[stream_index].num_odm_output_segments == 2 ||</div><div class='add'>+					cfg_support_info-&gt;stream_support_info[stream_index].num_odm_output_segments == 1);</div><div class='add'>+</div><div class='add'>+		if (cfg_support_info-&gt;stream_support_info[stream_index].odms_used &gt; 1)</div><div class='add'>+			DML_ASSERT(cfg_support_info-&gt;stream_support_info[stream_index].num_odm_output_segments == 1);</div><div class='add'>+</div><div class='add'>+		switch (cfg_support_info-&gt;stream_support_info[stream_index].odms_used) {</div><div class='add'>+		case (4):</div><div class='add'>+			mode_lib-&gt;mp.ODMMode[k] = dml2_odm_mode_combine_4to1;</div><div class='add'>+			break;</div><div class='add'>+		case (3):</div><div class='add'>+			mode_lib-&gt;mp.ODMMode[k] = dml2_odm_mode_combine_3to1;</div><div class='add'>+			break;</div><div class='add'>+		case (2):</div><div class='add'>+			mode_lib-&gt;mp.ODMMode[k] = dml2_odm_mode_combine_2to1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			if (cfg_support_info-&gt;stream_support_info[stream_index].num_odm_output_segments == 4)</div><div class='add'>+				mode_lib-&gt;mp.ODMMode[k] = dml2_odm_mode_mso_1to4;</div><div class='add'>+			else if (cfg_support_info-&gt;stream_support_info[stream_index].num_odm_output_segments == 2)</div><div class='add'>+				mode_lib-&gt;mp.ODMMode[k] = dml2_odm_mode_mso_1to2;</div><div class='add'>+			else</div><div class='add'>+				mode_lib-&gt;mp.ODMMode[k] = dml2_odm_mode_bypass;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;mp.NoOfDPP[k] = cfg_support_info-&gt;plane_support_info[k].dpps_used;</div><div class='add'>+		mode_lib-&gt;mp.Dppclk[k] = programming-&gt;plane_programming[k].min_clocks.dcn4x.dppclk_khz / 1000.0;</div><div class='add'>+		DML_ASSERT(mode_lib-&gt;mp.Dppclk[k] &gt; 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		unsigned int stream_index = display_cfg-&gt;plane_descriptors[k].stream_index;</div><div class='add'>+		mode_lib-&gt;mp.DSCCLK[k] = programming-&gt;stream_programming[stream_index].min_clocks.dcn4x.dscclk_khz / 1000.0;</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d stream_index=%d, mode_lib-&gt;mp.DSCCLK = %f\n", __func__, k, stream_index, mode_lib-&gt;mp.DSCCLK[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.Dispclk = programming-&gt;min_clocks.dcn4x.dispclk_khz / 1000.0;</div><div class='add'>+	mode_lib-&gt;mp.DCFCLKDeepSleep = programming-&gt;min_clocks.dcn4x.deepsleep_dcfclk_khz / 1000.0;</div><div class='add'>+</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.Dcfclk &gt; 0);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.FabricClock &gt; 0);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.dram_bw_mbps &gt; 0);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.uclk_freq_mhz &gt; 0);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.GlobalDPPCLK &gt; 0);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.Dispclk &gt; 0);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.DCFCLKDeepSleep &gt; 0);</div><div class='add'>+	DML_ASSERT(s-&gt;SOCCLK &gt; 0);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_active_planes = %u\n", __func__, s-&gt;num_active_planes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_active_pipes = %u\n", __func__, mode_lib-&gt;mp.num_active_pipes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Dcfclk = %f\n", __func__, mode_lib-&gt;mp.Dcfclk);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: FabricClock = %f\n", __func__, mode_lib-&gt;mp.FabricClock);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dram_bw_mbps = %f\n", __func__, mode_lib-&gt;mp.dram_bw_mbps);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: uclk_freq_mhz = %f\n", __func__, mode_lib-&gt;mp.uclk_freq_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: Dispclk = %f\n", __func__, mode_lib-&gt;mp.Dispclk);</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Dppclk[%0d] = %f\n", __func__, k, mode_lib-&gt;mp.Dppclk[k]);</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: GlobalDPPCLK = %f\n", __func__, mode_lib-&gt;mp.GlobalDPPCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: DCFCLKDeepSleep = %f\n", __func__, mode_lib-&gt;mp.DCFCLKDeepSleep);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s-&gt;SOCCLK);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_clk_index = %0d\n", __func__, in_out_params-&gt;min_clk_index);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_clk_table min_fclk_khz = %ld\n", __func__, min_clk_table-&gt;dram_bw_table.entries[in_out_params-&gt;min_clk_index].min_fclk_khz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table-&gt;dram_bw_table.entries[in_out_params-&gt;min_clk_index].pre_derate_dram_bw_kbps, &amp;mode_lib-&gt;soc.clk_table.dram_config));</div><div class='add'>+	for (k = 0; k &lt; mode_lib-&gt;mp.num_active_pipes; ++k) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib-&gt;mp.pipe_plane[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Per-plane DPPPerSurface[%0d] = %d\n", __func__, k, mode_lib-&gt;mp.NoOfDPP[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; k++)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg-&gt;plane_descriptors[k].overrides.reserved_vblank_time_ns);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	CalculateMaxDETAndMinCompressedBufferSize(</div><div class='add'>+		mode_lib-&gt;ip.config_return_buffer_size_in_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.config_return_buffer_segment_size_in_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.rob_buffer_size_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.max_num_dpp,</div><div class='add'>+		display_cfg-&gt;overrides.hw.force_nom_det_size_kbytes.enable,</div><div class='add'>+		display_cfg-&gt;overrides.hw.force_nom_det_size_kbytes.value,</div><div class='add'>+		mode_lib-&gt;ip.dcn_mrq_present,</div><div class='add'>+</div><div class='add'>+		/* Output */</div><div class='add'>+		&amp;s-&gt;MaxTotalDETInKByte,</div><div class='add'>+		&amp;s-&gt;NomDETInKByte,</div><div class='add'>+		&amp;s-&gt;MinCompressedBufferSizeInKByte);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	PixelClockAdjustmentForProgressiveToInterlaceUnit(display_cfg, mode_lib-&gt;ip.ptoi_supported, s-&gt;PixelClockBackEnd);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		CalculateSinglePipeDPPCLKAndSCLThroughput(</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio,</div><div class='add'>+			mode_lib-&gt;ip.max_dchub_pscl_bw_pix_per_clk,</div><div class='add'>+			mode_lib-&gt;ip.max_pscl_lb_bw_pix_per_clk,</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_taps,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_taps,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			&amp;mode_lib-&gt;mp.PSCL_THROUGHPUT[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.PSCL_THROUGHPUT_CHROMA[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.DPPCLKUsingSingleDPP[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		CalculateBytePerPixelAndBlockSizes(</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].surface.tiling,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch,</div><div class='add'>+</div><div class='add'>+			// Output</div><div class='add'>+			&amp;mode_lib-&gt;mp.BytePerPixelY[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.BytePerPixelC[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.BytePerPixelInDETY[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.BytePerPixelInDETC[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.Read256BlockHeightY[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.Read256BlockHeightC[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.Read256BlockWidthY[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.Read256BlockWidthC[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.MacroTileHeightY[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.MacroTileHeightC[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.MacroTileWidthY[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.MacroTileWidthC[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.surf_linear128_l[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.surf_linear128_c[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateSwathWidth(</div><div class='add'>+		display_cfg,</div><div class='add'>+		false, // ForceSingleDPP</div><div class='add'>+		s-&gt;num_active_planes,</div><div class='add'>+		mode_lib-&gt;mp.ODMMode,</div><div class='add'>+		mode_lib-&gt;mp.BytePerPixelY,</div><div class='add'>+		mode_lib-&gt;mp.BytePerPixelC,</div><div class='add'>+		mode_lib-&gt;mp.Read256BlockHeightY,</div><div class='add'>+		mode_lib-&gt;mp.Read256BlockHeightC,</div><div class='add'>+		mode_lib-&gt;mp.Read256BlockWidthY,</div><div class='add'>+		mode_lib-&gt;mp.Read256BlockWidthC,</div><div class='add'>+		mode_lib-&gt;mp.surf_linear128_l,</div><div class='add'>+		mode_lib-&gt;mp.surf_linear128_c,</div><div class='add'>+		mode_lib-&gt;mp.NoOfDPP,</div><div class='add'>+</div><div class='add'>+		/* Output */</div><div class='add'>+		mode_lib-&gt;mp.req_per_swath_ub_l,</div><div class='add'>+		mode_lib-&gt;mp.req_per_swath_ub_c,</div><div class='add'>+		mode_lib-&gt;mp.SwathWidthSingleDPPY,</div><div class='add'>+		mode_lib-&gt;mp.SwathWidthSingleDPPC,</div><div class='add'>+		mode_lib-&gt;mp.SwathWidthY,</div><div class='add'>+		mode_lib-&gt;mp.SwathWidthC,</div><div class='add'>+		s-&gt;dummy_integer_array[0], // unsigned int MaximumSwathHeightY[]</div><div class='add'>+		s-&gt;dummy_integer_array[1], // unsigned int MaximumSwathHeightC[]</div><div class='add'>+		mode_lib-&gt;mp.swath_width_luma_ub,</div><div class='add'>+		mode_lib-&gt;mp.swath_width_chroma_ub);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;mp.cursor_bw[k] = display_cfg-&gt;plane_descriptors[k].cursor.num_cursors * display_cfg-&gt;plane_descriptors[k].cursor.cursor_width * display_cfg-&gt;plane_descriptors[k].cursor.cursor_bpp / 8.0 /</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));</div><div class='add'>+		mode_lib-&gt;mp.vactive_sw_bw_l[k] = mode_lib-&gt;mp.SwathWidthSingleDPPY[k] * mode_lib-&gt;mp.BytePerPixelY[k] / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		mode_lib-&gt;mp.vactive_sw_bw_c[k] = mode_lib-&gt;mp.SwathWidthSingleDPPC[k] * mode_lib-&gt;mp.BytePerPixelC[k] / (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_l[%i] = %fBps\n", __func__, k, mode_lib-&gt;mp.vactive_sw_bw_l[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_c[%i] = %fBps\n", __func__, k, mode_lib-&gt;mp.vactive_sw_bw_c[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ConfigReturnBufferSizeInKByte = mode_lib-&gt;ip.config_return_buffer_size_in_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MaxTotalDETInKByte = s-&gt;MaxTotalDETInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MinCompressedBufferSizeInKByte = s-&gt;MinCompressedBufferSizeInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;rob_buffer_size_kbytes = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;pixel_chunk_size_kbytes = mode_lib-&gt;ip.pixel_chunk_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;rob_buffer_size_kbytes = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;pixel_chunk_size_kbytes = mode_lib-&gt;ip.pixel_chunk_size_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ForceSingleDPP = false;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;NumberOfActiveSurfaces = s-&gt;num_active_planes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;nomDETInKByte = s-&gt;NomDETInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ConfigReturnBufferSegmentSizeInkByte = mode_lib-&gt;ip.config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;CompressedBufferSegmentSizeInkByte = mode_lib-&gt;ip.compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ReadBandwidthLuma = mode_lib-&gt;mp.vactive_sw_bw_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ReadBandwidthChroma = mode_lib-&gt;mp.vactive_sw_bw_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MaximumSwathWidthLuma = s-&gt;dummy_single_array[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;MaximumSwathWidthChroma = s-&gt;dummy_single_array[1];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockHeightY = mode_lib-&gt;mp.Read256BlockHeightY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockHeightC = mode_lib-&gt;mp.Read256BlockHeightC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockWidthY = mode_lib-&gt;mp.Read256BlockWidthY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;Read256BytesBlockWidthC = mode_lib-&gt;mp.Read256BlockWidthC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;surf_linear128_l = mode_lib-&gt;mp.surf_linear128_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;surf_linear128_c = mode_lib-&gt;mp.surf_linear128_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ODMMode = mode_lib-&gt;mp.ODMMode;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DPPPerSurface = mode_lib-&gt;mp.NoOfDPP;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixY = mode_lib-&gt;mp.BytePerPixelY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixC = mode_lib-&gt;mp.BytePerPixelC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixDETY = mode_lib-&gt;mp.BytePerPixelInDETY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;BytePerPixDETC = mode_lib-&gt;mp.BytePerPixelInDETC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;req_per_swath_ub_l = mode_lib-&gt;mp.req_per_swath_ub_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;req_per_swath_ub_c = mode_lib-&gt;mp.req_per_swath_ub_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;swath_width_luma_ub = s-&gt;dummy_long_array[0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;swath_width_chroma_ub = s-&gt;dummy_long_array[1];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathWidth = s-&gt;dummy_long_array[2];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathWidthChroma = s-&gt;dummy_long_array[3];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathHeightY = mode_lib-&gt;mp.SwathHeightY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;SwathHeightC = mode_lib-&gt;mp.SwathHeightC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;request_size_bytes_luma = mode_lib-&gt;mp.request_size_bytes_luma;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;request_size_bytes_chroma = mode_lib-&gt;mp.request_size_bytes_chroma;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeInKByte = mode_lib-&gt;mp.DETBufferSizeInKByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeY = mode_lib-&gt;mp.DETBufferSizeY;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;DETBufferSizeC = mode_lib-&gt;mp.DETBufferSizeC;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;full_swath_bytes_l = s-&gt;full_swath_bytes_l;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;full_swath_bytes_c = s-&gt;full_swath_bytes_c;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;UnboundedRequestEnabled = &amp;mode_lib-&gt;mp.UnboundedRequestEnabled;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;compbuf_reserved_space_64b = &amp;mode_lib-&gt;mp.compbuf_reserved_space_64b;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;hw_debug5 = &amp;mode_lib-&gt;mp.hw_debug5;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;CompressedBufferSizeInkByte = &amp;mode_lib-&gt;mp.CompressedBufferSizeInkByte;</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ViewportSizeSupportPerSurface = &amp;s-&gt;dummy_boolean_array[0][0];</div><div class='add'>+	CalculateSwathAndDETConfiguration_params-&gt;ViewportSizeSupport = &amp;s-&gt;dummy_boolean[0];</div><div class='add'>+</div><div class='add'>+	// Calculate DET size, swath height here.</div><div class='add'>+	CalculateSwathAndDETConfiguration(&amp;mode_lib-&gt;scratch, CalculateSwathAndDETConfiguration_params);</div><div class='add'>+</div><div class='add'>+	// DSC Delay</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		mode_lib-&gt;mp.DSCDelay[k] = DSCDelayRequirement(cfg_support_info-&gt;stream_support_info[display_cfg-&gt;plane_descriptors[k].stream_index].dsc_enable,</div><div class='add'>+			mode_lib-&gt;mp.ODMMode[k],</div><div class='add'>+			mode_lib-&gt;ip.maximum_dsc_bits_per_component,</div><div class='add'>+			s-&gt;OutputBpp[k],</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total,</div><div class='add'>+			cfg_support_info-&gt;stream_support_info[display_cfg-&gt;plane_descriptors[k].stream_index].num_dsc_slices,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format,</div><div class='add'>+			display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_encoder,</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+			s-&gt;PixelClockBackEnd[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Prefetch</div><div class='add'>+	if (mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes == 0) {</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k)</div><div class='add'>+			mode_lib-&gt;mp.SurfaceSizeInTheMALL[k] = 0;</div><div class='add'>+	} else {</div><div class='add'>+		CalculateSurfaceSizeInMall(</div><div class='add'>+			display_cfg,</div><div class='add'>+			s-&gt;num_active_planes,</div><div class='add'>+			mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes,</div><div class='add'>+			mode_lib-&gt;mp.BytePerPixelY,</div><div class='add'>+			mode_lib-&gt;mp.BytePerPixelC,</div><div class='add'>+			mode_lib-&gt;mp.Read256BlockWidthY,</div><div class='add'>+			mode_lib-&gt;mp.Read256BlockWidthC,</div><div class='add'>+			mode_lib-&gt;mp.Read256BlockHeightY,</div><div class='add'>+			mode_lib-&gt;mp.Read256BlockHeightC,</div><div class='add'>+			mode_lib-&gt;mp.MacroTileWidthY,</div><div class='add'>+			mode_lib-&gt;mp.MacroTileWidthC,</div><div class='add'>+			mode_lib-&gt;mp.MacroTileHeightY,</div><div class='add'>+			mode_lib-&gt;mp.MacroTileHeightC,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			mode_lib-&gt;mp.SurfaceSizeInTheMALL,</div><div class='add'>+			&amp;s-&gt;dummy_boolean[0]); /* bool *ExceededMALLSize */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		s-&gt;SurfaceParameters[k].PixelClock = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+		s-&gt;SurfaceParameters[k].DPPPerSurface = mode_lib-&gt;mp.NoOfDPP[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].RotationAngle = display_cfg-&gt;plane_descriptors[k].composition.rotation_angle;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportHeight = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportHeightC = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height;</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockWidth256BytesY = mode_lib-&gt;mp.Read256BlockWidthY[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockHeight256BytesY = mode_lib-&gt;mp.Read256BlockHeightY[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockWidth256BytesC = mode_lib-&gt;mp.Read256BlockWidthC[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockHeight256BytesC = mode_lib-&gt;mp.Read256BlockHeightC[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockWidthY = mode_lib-&gt;mp.MacroTileWidthY[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockHeightY = mode_lib-&gt;mp.MacroTileHeightY[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockWidthC = mode_lib-&gt;mp.MacroTileWidthC[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BlockHeightC = mode_lib-&gt;mp.MacroTileHeightC[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].InterlaceEnable = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced;</div><div class='add'>+		s-&gt;SurfaceParameters[k].HTotal = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+		s-&gt;SurfaceParameters[k].DCCEnable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+		s-&gt;SurfaceParameters[k].SourcePixelFormat = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+		s-&gt;SurfaceParameters[k].SurfaceTiling = display_cfg-&gt;plane_descriptors[k].surface.tiling;</div><div class='add'>+		s-&gt;SurfaceParameters[k].BytePerPixelY = mode_lib-&gt;mp.BytePerPixelY[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].BytePerPixelC = mode_lib-&gt;mp.BytePerPixelC[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib-&gt;ip.ptoi_supported;</div><div class='add'>+		s-&gt;SurfaceParameters[k].VRatio = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+		s-&gt;SurfaceParameters[k].VRatioChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+		s-&gt;SurfaceParameters[k].VTaps = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps;</div><div class='add'>+		s-&gt;SurfaceParameters[k].VTapsChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps;</div><div class='add'>+		s-&gt;SurfaceParameters[k].PitchY = display_cfg-&gt;plane_descriptors[k].surface.plane0.pitch;</div><div class='add'>+		s-&gt;SurfaceParameters[k].PitchC = display_cfg-&gt;plane_descriptors[k].surface.plane1.pitch;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportStationary = display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportXStart = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.x_start;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportYStart = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.y_start;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportXStartC = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+		s-&gt;SurfaceParameters[k].ViewportYStartC = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+		s-&gt;SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = display_cfg-&gt;plane_descriptors[k].overrides.hw.force_one_row_for_frame;</div><div class='add'>+		s-&gt;SurfaceParameters[k].SwathHeightY = mode_lib-&gt;mp.SwathHeightY[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].SwathHeightC = mode_lib-&gt;mp.SwathHeightC[k];</div><div class='add'>+		s-&gt;SurfaceParameters[k].DCCMetaPitchY = display_cfg-&gt;plane_descriptors[k].surface.dcc.plane0.pitch;</div><div class='add'>+		s-&gt;SurfaceParameters[k].DCCMetaPitchC = display_cfg-&gt;plane_descriptors[k].surface.dcc.plane1.pitch;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;NumberOfActiveSurfaces = s-&gt;num_active_planes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;myPipe = s-&gt;SurfaceParameters;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;SurfaceSizeInMALL = mode_lib-&gt;mp.SurfaceSizeInTheMALL;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeInRequestsLuma = mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_luma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeInRequestsChroma = mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;MALLAllocatedForDCN = mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;SwathWidthY = mode_lib-&gt;mp.SwathWidthY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;SwathWidthC = mode_lib-&gt;mp.SwathWidthC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;HostVMMinPageSize = mode_lib-&gt;soc.hostvm_min_page_size_kbytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;DCCMetaBufferSizeBytes = mode_lib-&gt;ip.dcc_meta_buffer_size_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeNotExceeded = s-&gt;dummy_boolean_array[0];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_width_luma_ub = mode_lib-&gt;mp.dpte_row_width_luma_ub;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_width_chroma_ub = mode_lib-&gt;mp.dpte_row_width_chroma_ub;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_luma = mode_lib-&gt;mp.dpte_row_height;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_chroma = mode_lib-&gt;mp.dpte_row_height_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_linear_luma = mode_lib-&gt;mp.dpte_row_height_linear;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_height_linear_chroma = mode_lib-&gt;mp.dpte_row_height_linear_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vm_group_bytes = mode_lib-&gt;mp.vm_group_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_group_bytes = mode_lib-&gt;mp.dpte_group_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqWidthY = mode_lib-&gt;mp.PixelPTEReqWidthY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqHeightY = mode_lib-&gt;mp.PixelPTEReqHeightY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTERequestSizeY = mode_lib-&gt;mp.PTERequestSizeY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqWidthC = mode_lib-&gt;mp.PixelPTEReqWidthC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEReqHeightC = mode_lib-&gt;mp.PixelPTEReqHeightC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTERequestSizeC = mode_lib-&gt;mp.PTERequestSizeC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_width_y = s-&gt;vmpg_width_y;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_height_y = s-&gt;vmpg_height_y;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_width_c = s-&gt;vmpg_width_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vmpg_height_c = s-&gt;vmpg_height_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpde0_bytes_per_frame_ub_l = mode_lib-&gt;mp.dpde0_bytes_per_frame_ub_l;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpde0_bytes_per_frame_ub_c = mode_lib-&gt;mp.dpde0_bytes_per_frame_ub_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PrefetchSourceLinesY = mode_lib-&gt;mp.PrefetchSourceLinesY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PrefetchSourceLinesC = mode_lib-&gt;mp.PrefetchSourceLinesC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;VInitPreFillY = mode_lib-&gt;mp.VInitPreFillY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;VInitPreFillC = mode_lib-&gt;mp.VInitPreFillC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;MaxNumSwathY = mode_lib-&gt;mp.MaxNumSwathY;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;MaxNumSwathC = mode_lib-&gt;mp.MaxNumSwathC;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_bw = mode_lib-&gt;mp.dpte_row_bw;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PixelPTEBytesPerRow = mode_lib-&gt;mp.PixelPTEBytesPerRow;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_bytes_per_row_l = s-&gt;dpte_row_bytes_per_row_l;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;dpte_row_bytes_per_row_c = s-&gt;dpte_row_bytes_per_row_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;vm_bytes = mode_lib-&gt;mp.vm_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;use_one_row_for_frame = mode_lib-&gt;mp.use_one_row_for_frame;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;use_one_row_for_frame_flip = mode_lib-&gt;mp.use_one_row_for_frame_flip;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;is_using_mall_for_ss = mode_lib-&gt;mp.is_using_mall_for_ss;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;PTE_BUFFER_MODE = mode_lib-&gt;mp.PTE_BUFFER_MODE;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;BIGK_FRAGMENT_SIZE = mode_lib-&gt;mp.BIGK_FRAGMENT_SIZE;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;DCCMetaBufferSizeNotExceeded = s-&gt;dummy_boolean_array[1];</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bw = mode_lib-&gt;mp.meta_row_bw;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bytes = mode_lib-&gt;mp.meta_row_bytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bytes_per_row_ub_l = s-&gt;meta_row_bytes_per_row_ub_l;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_bytes_per_row_ub_c = s-&gt;meta_row_bytes_per_row_ub_c;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_width_luma = mode_lib-&gt;mp.meta_req_width;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_height_luma = mode_lib-&gt;mp.meta_req_height;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_width_luma = mode_lib-&gt;mp.meta_row_width;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_height_luma = mode_lib-&gt;mp.meta_row_height;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_pte_bytes_per_frame_ub_l = mode_lib-&gt;mp.meta_pte_bytes_per_frame_ub_l;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_width_chroma = mode_lib-&gt;mp.meta_req_width_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_height_chroma = mode_lib-&gt;mp.meta_row_height_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_row_width_chroma = mode_lib-&gt;mp.meta_row_width_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_req_height_chroma = mode_lib-&gt;mp.meta_req_height_chroma;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;meta_pte_bytes_per_frame_ub_c = mode_lib-&gt;mp.meta_pte_bytes_per_frame_ub_c;</div><div class='add'>+</div><div class='add'>+	CalculateVMRowAndSwath(&amp;mode_lib-&gt;scratch, CalculateVMRowAndSwath_params);</div><div class='add'>+</div><div class='add'>+	memset(calculate_mcache_setting_params, 0, sizeof(struct dml2_core_calcs_calculate_mcache_setting_params));</div><div class='add'>+	if (mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes == 0 || mode_lib-&gt;ip.dcn_mrq_present) {</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; k++) {</div><div class='add'>+			mode_lib-&gt;mp.mall_prefetch_sdp_overhead_factor[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;mp.mall_prefetch_dram_overhead_factor[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p0[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p0[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p1[k] = 1.0;</div><div class='add'>+			mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p1[k] = 1.0;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; k++) {</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_enable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+			calculate_mcache_setting_params-&gt;num_chans = mode_lib-&gt;soc.clk_table.dram_config.channel_count;</div><div class='add'>+			calculate_mcache_setting_params-&gt;mem_word_bytes = mode_lib-&gt;soc.mem_word_bytes;</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_size_bytes = mode_lib-&gt;soc.mcache_size_bytes;</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_line_size_bytes = mode_lib-&gt;soc.mcache_line_size_bytes;</div><div class='add'>+			calculate_mcache_setting_params-&gt;gpuvm_enable = display_cfg-&gt;gpuvm_enable;</div><div class='add'>+			calculate_mcache_setting_params-&gt;gpuvm_page_size_kbytes = display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;source_format = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+			calculate_mcache_setting_params-&gt;surf_vert = dml_is_vertical_rotation(display_cfg-&gt;plane_descriptors[k].composition.rotation_angle);</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_stationary = display_cfg-&gt;plane_descriptors[k].composition.viewport.stationary;</div><div class='add'>+			calculate_mcache_setting_params-&gt;tiling_mode = display_cfg-&gt;plane_descriptors[k].surface.tiling;</div><div class='add'>+			calculate_mcache_setting_params-&gt;imall_enable = mode_lib-&gt;ip.imall_supported &amp;&amp; display_cfg-&gt;plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall;</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_x_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.x_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_y_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.y_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_width_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_height_l = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height;</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_width_l = mode_lib-&gt;mp.MacroTileWidthY[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_height_l = mode_lib-&gt;mp.MacroTileHeightY[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_width_l = s-&gt;vmpg_width_y[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_height_l = s-&gt;vmpg_height_y[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_swath_bytes_l = s-&gt;full_swath_bytes_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;bytes_per_pixel_l = mode_lib-&gt;mp.BytePerPixelY[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_x_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;vp_start_y_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.y_start;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_width_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.width;</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_vp_height_c = display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height;</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_width_c = mode_lib-&gt;mp.MacroTileWidthC[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;blk_height_c = mode_lib-&gt;mp.MacroTileHeightC[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_width_c = s-&gt;vmpg_width_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;vmpg_height_c = s-&gt;vmpg_height_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;full_swath_bytes_c = s-&gt;full_swath_bytes_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;bytes_per_pixel_c = mode_lib-&gt;mp.BytePerPixelC[k];</div><div class='add'>+</div><div class='add'>+			// output</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_nom_overhead_factor_l = &amp;mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p0[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_pref_overhead_factor_l = &amp;mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p0[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_nom_overhead_factor_c = &amp;mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p1[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;dcc_dram_bw_pref_overhead_factor_c = &amp;mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p1[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;num_mcaches_l = &amp;mode_lib-&gt;mp.num_mcaches_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_l = &amp;mode_lib-&gt;mp.mcache_row_bytes_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_per_channel_l = &amp;mode_lib-&gt;mp.mcache_row_bytes_per_channel_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_offsets_l = mode_lib-&gt;mp.mcache_offsets_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_shift_granularity_l = &amp;mode_lib-&gt;mp.mcache_shift_granularity_l[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;num_mcaches_c = &amp;mode_lib-&gt;mp.num_mcaches_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_c = &amp;mode_lib-&gt;mp.mcache_row_bytes_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_row_bytes_per_channel_c = &amp;mode_lib-&gt;mp.mcache_row_bytes_per_channel_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_offsets_c = mode_lib-&gt;mp.mcache_offsets_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mcache_shift_granularity_c = &amp;mode_lib-&gt;mp.mcache_shift_granularity_c[k];</div><div class='add'>+</div><div class='add'>+			calculate_mcache_setting_params-&gt;mall_comb_mcache_l = &amp;mode_lib-&gt;mp.mall_comb_mcache_l[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;mall_comb_mcache_c = &amp;mode_lib-&gt;mp.mall_comb_mcache_c[k];</div><div class='add'>+			calculate_mcache_setting_params-&gt;lc_comb_mcache = &amp;mode_lib-&gt;mp.lc_comb_mcache[k];</div><div class='add'>+			calculate_mcache_setting(&amp;mode_lib-&gt;scratch, calculate_mcache_setting_params);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		calculate_mall_bw_overhead_factor(</div><div class='add'>+			mode_lib-&gt;mp.mall_prefetch_sdp_overhead_factor,</div><div class='add'>+			mode_lib-&gt;mp.mall_prefetch_dram_overhead_factor,</div><div class='add'>+</div><div class='add'>+			// input</div><div class='add'>+			display_cfg,</div><div class='add'>+			s-&gt;num_active_planes);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Calculate all the bandwidth availabe</div><div class='add'>+	calculate_bandwidth_available(</div><div class='add'>+		mode_lib-&gt;mp.avg_bandwidth_available_min,</div><div class='add'>+		mode_lib-&gt;mp.avg_bandwidth_available,</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available_min,</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available,</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available_vm_only,</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available_pixel_and_vm,</div><div class='add'>+</div><div class='add'>+		&amp;mode_lib-&gt;soc,</div><div class='add'>+		display_cfg-&gt;hostvm_enable,</div><div class='add'>+		mode_lib-&gt;mp.Dcfclk,</div><div class='add'>+		mode_lib-&gt;mp.FabricClock,</div><div class='add'>+		mode_lib-&gt;mp.dram_bw_mbps);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	calculate_hostvm_inefficiency_factor(</div><div class='add'>+		&amp;s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+		&amp;s-&gt;HostVMInefficiencyFactorPrefetch,</div><div class='add'>+</div><div class='add'>+		display_cfg-&gt;gpuvm_enable,</div><div class='add'>+		display_cfg-&gt;hostvm_enable,</div><div class='add'>+		mode_lib-&gt;ip.remote_iommu_outstanding_translations,</div><div class='add'>+		mode_lib-&gt;soc.max_outstanding_reqs,</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_sys_active],</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_sys_active]);</div><div class='add'>+</div><div class='add'>+	s-&gt;TotalDCCActiveDPP = 0;</div><div class='add'>+	s-&gt;TotalActiveDPP = 0;</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		s-&gt;TotalActiveDPP = s-&gt;TotalActiveDPP + mode_lib-&gt;mp.NoOfDPP[k];</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].surface.dcc.enable)</div><div class='add'>+			s-&gt;TotalDCCActiveDPP = s-&gt;TotalDCCActiveDPP + mode_lib-&gt;mp.NoOfDPP[k];</div><div class='add'>+	}</div><div class='add'>+	// Calculate tdlut schedule related terms</div><div class='add'>+	for (k = 0; k &lt;= s-&gt;num_active_planes - 1; k++) {</div><div class='add'>+		calculate_tdlut_setting_params-&gt;dispclk_mhz = mode_lib-&gt;mp.Dispclk;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;setup_for_tdlut = display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_width_mode = display_cfg-&gt;plane_descriptors[k].tdlut.tdlut_width_mode;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_addressing_mode = display_cfg-&gt;plane_descriptors[k].tdlut.tdlut_addressing_mode;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;cursor_buffer_size = mode_lib-&gt;ip.cursor_buffer_size;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;gpuvm_enable = display_cfg-&gt;gpuvm_enable;</div><div class='add'>+		calculate_tdlut_setting_params-&gt;gpuvm_page_size_kbytes = display_cfg-&gt;plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;</div><div class='add'>+</div><div class='add'>+		// output</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_pte_bytes_per_frame = &amp;s-&gt;tdlut_pte_bytes_per_frame[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_bytes_per_frame = &amp;s-&gt;tdlut_bytes_per_frame[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_groups_per_2row_ub = &amp;s-&gt;tdlut_groups_per_2row_ub[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_opt_time = &amp;s-&gt;tdlut_opt_time[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_drain_time = &amp;s-&gt;tdlut_drain_time[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_bytes_to_deliver = &amp;s-&gt;tdlut_bytes_to_deliver[k];</div><div class='add'>+		calculate_tdlut_setting_params-&gt;tdlut_bytes_per_group = &amp;s-&gt;tdlut_bytes_per_group[k];</div><div class='add'>+		calculate_tdlut_setting(&amp;mode_lib-&gt;scratch, calculate_tdlut_setting_params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mode_lib-&gt;soc.qos_parameters.qos_type == dml2_qos_param_type_dcn3)</div><div class='add'>+		s-&gt;ReorderingBytes = (unsigned int)(mode_lib-&gt;soc.clk_table.dram_config.channel_count * math_max3(mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_out_of_order_return_per_channel_pixel_only_bytes,</div><div class='add'>+										mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes,</div><div class='add'>+										mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_out_of_order_return_per_channel_vm_only_bytes));</div><div class='add'>+</div><div class='add'>+	CalculateExtraLatency(</div><div class='add'>+		display_cfg,</div><div class='add'>+		mode_lib-&gt;ip.rob_buffer_size_kbytes,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.loaded_round_trip_latency_fclk_cycles,</div><div class='add'>+		s-&gt;ReorderingBytes,</div><div class='add'>+		mode_lib-&gt;mp.Dcfclk,</div><div class='add'>+		mode_lib-&gt;mp.FabricClock,</div><div class='add'>+		mode_lib-&gt;ip.pixel_chunk_size_kbytes,</div><div class='add'>+		mode_lib-&gt;mp.urg_bandwidth_available_min[dml2_core_internal_soc_state_sys_active],</div><div class='add'>+		s-&gt;num_active_planes,</div><div class='add'>+		mode_lib-&gt;mp.NoOfDPP,</div><div class='add'>+		mode_lib-&gt;mp.dpte_group_bytes,</div><div class='add'>+		s-&gt;tdlut_bytes_per_group,</div><div class='add'>+		s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+		s-&gt;HostVMInefficiencyFactorPrefetch,</div><div class='add'>+		mode_lib-&gt;soc.hostvm_min_page_size_kbytes,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		!(display_cfg-&gt;overrides.max_outstanding_when_urgent_expected_disable),</div><div class='add'>+		mode_lib-&gt;soc.max_outstanding_reqs,</div><div class='add'>+		mode_lib-&gt;mp.request_size_bytes_luma,</div><div class='add'>+		mode_lib-&gt;mp.request_size_bytes_chroma,</div><div class='add'>+		mode_lib-&gt;ip.meta_chunk_size_kbytes,</div><div class='add'>+		mode_lib-&gt;ip.dchub_arb_to_ret_delay,</div><div class='add'>+		mode_lib-&gt;mp.TripToMemory,</div><div class='add'>+		mode_lib-&gt;ip.hostvm_mode,</div><div class='add'>+</div><div class='add'>+		// output</div><div class='add'>+		&amp;mode_lib-&gt;mp.ExtraLatency,</div><div class='add'>+		&amp;mode_lib-&gt;mp.ExtraLatency_sr,</div><div class='add'>+		&amp;mode_lib-&gt;mp.ExtraLatencyPrefetch);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.TCalc = 24.0 / mode_lib-&gt;mp.DCFCLKDeepSleep;</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+			mode_lib-&gt;mp.WritebackDelay[k] =</div><div class='add'>+				mode_lib-&gt;soc.qos_parameters.writeback.base_latency_us</div><div class='add'>+				+ CalculateWriteBackDelay(</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total) / mode_lib-&gt;mp.Dispclk;</div><div class='add'>+		} else</div><div class='add'>+			mode_lib-&gt;mp.WritebackDelay[k] = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* VActive bytes to fetch for UCLK P-State */</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;display_cfg = display_cfg;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;num_active_planes = s-&gt;num_active_planes;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;num_of_dpp = mode_lib-&gt;mp.NoOfDPP;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_height_l = mode_lib-&gt;mp.meta_row_height;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_height_c = mode_lib-&gt;mp.meta_row_height_chroma;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_bytes_per_row_ub_l = s-&gt;meta_row_bytes_per_row_ub_l;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;meta_row_bytes_per_row_ub_c = s-&gt;meta_row_bytes_per_row_ub_c;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_row_height_l = mode_lib-&gt;mp.dpte_row_height;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_row_height_c = mode_lib-&gt;mp.dpte_row_height_chroma;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_bytes_per_row_l = s-&gt;dpte_row_bytes_per_row_l;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;dpte_bytes_per_row_c = s-&gt;dpte_row_bytes_per_row_c;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;byte_per_pix_l = mode_lib-&gt;mp.BytePerPixelY;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;byte_per_pix_c = mode_lib-&gt;mp.BytePerPixelC;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_width_l = mode_lib-&gt;mp.SwathWidthY;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_width_c = mode_lib-&gt;mp.SwathWidthC;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_height_l = mode_lib-&gt;mp.SwathHeightY;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;swath_height_c = mode_lib-&gt;mp.SwathHeightC;</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;latency_to_hide_us[0] = mode_lib-&gt;soc.power_management_parameters.dram_clk_change_blackout_us;</div><div class='add'>+</div><div class='add'>+	/* outputs */</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;bytes_required_l = s-&gt;pstate_bytes_required_l[dml2_pstate_type_uclk];</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency_params-&gt;bytes_required_c = s-&gt;pstate_bytes_required_c[dml2_pstate_type_uclk];</div><div class='add'>+</div><div class='add'>+	calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params);</div><div class='add'>+</div><div class='add'>+	/* Excess VActive bandwidth required to fill DET */</div><div class='add'>+	calculate_excess_vactive_bandwidth_required(</div><div class='add'>+			display_cfg,</div><div class='add'>+			s-&gt;num_active_planes,</div><div class='add'>+			s-&gt;pstate_bytes_required_l[dml2_pstate_type_uclk],</div><div class='add'>+			s-&gt;pstate_bytes_required_c[dml2_pstate_type_uclk],</div><div class='add'>+			/* outputs */</div><div class='add'>+			mode_lib-&gt;mp.excess_vactive_fill_bw_l,</div><div class='add'>+			mode_lib-&gt;mp.excess_vactive_fill_bw_c);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.UrgentLatency = CalculateUrgentLatency(</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.base_latency_us,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.base_latency_pixel_vm_us,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.base_latency_vm_us,</div><div class='add'>+		mode_lib-&gt;soc.do_urgent_latency_adjustment,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.scaling_factor_fclk_us,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn32x.urgent_latency_us.scaling_factor_mhz,</div><div class='add'>+		mode_lib-&gt;mp.FabricClock,</div><div class='add'>+		mode_lib-&gt;mp.uclk_freq_mhz,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;mp.qos_param_index].urgent_ramp_uclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_urgent_ramp_latency_margin,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.TripToMemory = CalculateTripToMemory(</div><div class='add'>+		mode_lib-&gt;mp.UrgentLatency,</div><div class='add'>+		mode_lib-&gt;mp.FabricClock,</div><div class='add'>+		mode_lib-&gt;mp.uclk_freq_mhz,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;mp.qos_param_index].trip_to_memory_uclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.TripToMemory = math_max2(mode_lib-&gt;mp.UrgentLatency, mode_lib-&gt;mp.TripToMemory);</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;mp.MetaTripToMemory = CalculateMetaTripToMemory(</div><div class='add'>+		mode_lib-&gt;mp.UrgentLatency,</div><div class='add'>+		mode_lib-&gt;mp.FabricClock,</div><div class='add'>+		mode_lib-&gt;mp.uclk_freq_mhz,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_type,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib-&gt;mp.qos_param_index].meta_trip_to_memory_uclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.meta_trip_adder_fclk_cycles,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin,</div><div class='add'>+		mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin);</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		bool cursor_not_enough_urgent_latency_hiding = false;</div><div class='add'>+		s-&gt;line_times[k] = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+</div><div class='add'>+		s-&gt;pixel_format[k] = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+</div><div class='add'>+		s-&gt;lb_source_lines_l[k] = get_num_lb_source_lines(mode_lib-&gt;ip.max_line_buffer_lines, mode_lib-&gt;ip.line_buffer_size_bits,</div><div class='add'>+															mode_lib-&gt;mp.NoOfDPP[k],</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.width,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.viewport.plane0.height,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.rotation_angle);</div><div class='add'>+</div><div class='add'>+		s-&gt;lb_source_lines_c[k] = get_num_lb_source_lines(mode_lib-&gt;ip.max_line_buffer_lines, mode_lib-&gt;ip.line_buffer_size_bits,</div><div class='add'>+															mode_lib-&gt;mp.NoOfDPP[k],</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.width,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.viewport.plane1.height,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.h_ratio,</div><div class='add'>+															display_cfg-&gt;plane_descriptors[k].composition.rotation_angle);</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[k].cursor.num_cursors &gt; 0) {</div><div class='add'>+			calculate_cursor_req_attributes(</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].cursor.cursor_width,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].cursor.cursor_bpp,</div><div class='add'>+</div><div class='add'>+				// output</div><div class='add'>+				&amp;s-&gt;cursor_lines_per_chunk[k],</div><div class='add'>+				&amp;s-&gt;cursor_bytes_per_line[k],</div><div class='add'>+				&amp;s-&gt;cursor_bytes_per_chunk[k],</div><div class='add'>+				&amp;s-&gt;cursor_bytes[k]);</div><div class='add'>+</div><div class='add'>+			calculate_cursor_urgent_burst_factor(</div><div class='add'>+				mode_lib-&gt;ip.cursor_buffer_size,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].cursor.cursor_width,</div><div class='add'>+				s-&gt;cursor_bytes_per_chunk[k],</div><div class='add'>+				s-&gt;cursor_lines_per_chunk[k],</div><div class='add'>+				s-&gt;line_times[k],</div><div class='add'>+				mode_lib-&gt;mp.UrgentLatency,</div><div class='add'>+</div><div class='add'>+				// output</div><div class='add'>+				&amp;mode_lib-&gt;mp.UrgentBurstFactorCursor[k],</div><div class='add'>+				&amp;cursor_not_enough_urgent_latency_hiding);</div><div class='add'>+		}</div><div class='add'>+		mode_lib-&gt;mp.UrgentBurstFactorCursorPre[k] = mode_lib-&gt;mp.UrgentBurstFactorCursor[k];</div><div class='add'>+</div><div class='add'>+		CalculateUrgentBurstFactor(</div><div class='add'>+			&amp;display_cfg-&gt;plane_descriptors[k],</div><div class='add'>+			mode_lib-&gt;mp.swath_width_luma_ub[k],</div><div class='add'>+			mode_lib-&gt;mp.swath_width_chroma_ub[k],</div><div class='add'>+			mode_lib-&gt;mp.SwathHeightY[k],</div><div class='add'>+			mode_lib-&gt;mp.SwathHeightC[k],</div><div class='add'>+			s-&gt;line_times[k],</div><div class='add'>+			mode_lib-&gt;mp.UrgentLatency,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio,</div><div class='add'>+			display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio,</div><div class='add'>+			mode_lib-&gt;mp.BytePerPixelInDETY[k],</div><div class='add'>+			mode_lib-&gt;mp.BytePerPixelInDETC[k],</div><div class='add'>+			mode_lib-&gt;mp.DETBufferSizeY[k],</div><div class='add'>+			mode_lib-&gt;mp.DETBufferSizeC[k],</div><div class='add'>+</div><div class='add'>+			/* output */</div><div class='add'>+			&amp;mode_lib-&gt;mp.UrgentBurstFactorLuma[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.UrgentBurstFactorChroma[k],</div><div class='add'>+			&amp;mode_lib-&gt;mp.NotEnoughUrgentLatencyHiding[k]);</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;mp.NotEnoughUrgentLatencyHiding[k] = mode_lib-&gt;mp.NotEnoughUrgentLatencyHiding[k] || cursor_not_enough_urgent_latency_hiding;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		s-&gt;MaxVStartupLines[k] = CalculateMaxVStartup(</div><div class='add'>+			mode_lib-&gt;ip.ptoi_supported,</div><div class='add'>+			mode_lib-&gt;ip.vblank_nom_default_us,</div><div class='add'>+			&amp;display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing,</div><div class='add'>+			mode_lib-&gt;mp.WritebackDelay[k]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u MaxVStartupLines = %u\n", __func__, k, s-&gt;MaxVStartupLines[k]);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%u WritebackDelay = %f\n", __func__, k, mode_lib-&gt;mp.WritebackDelay[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	s-&gt;immediate_flip_required = false;</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+		s-&gt;immediate_flip_required = s-&gt;immediate_flip_required || display_cfg-&gt;plane_descriptors[k].immediate_flip;</div><div class='add'>+	}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: immediate_flip_required = %u\n", __func__, s-&gt;immediate_flip_required);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (s-&gt;num_active_planes &gt; 1) {</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;num_active_planes =  s-&gt;num_active_planes;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;pixel_format = s-&gt;pixel_format;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;chunk_bytes_l = mode_lib-&gt;ip.pixel_chunk_size_kbytes * 1024;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;chunk_bytes_c = mode_lib-&gt;ip.pixel_chunk_size_kbytes * 1024;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;lb_source_lines_l = s-&gt;lb_source_lines_l;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;lb_source_lines_c = s-&gt;lb_source_lines_c;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;swath_height_l =  mode_lib-&gt;mp.SwathHeightY;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;swath_height_c =  mode_lib-&gt;mp.SwathHeightC;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;rob_buffer_size_kbytes = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;compressed_buffer_size_kbytes = mode_lib-&gt;mp.CompressedBufferSizeInkByte;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;detile_buffer_size_bytes_l = mode_lib-&gt;mp.DETBufferSizeY;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;detile_buffer_size_bytes_c = mode_lib-&gt;mp.DETBufferSizeC;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;full_swath_bytes_l = s-&gt;full_swath_bytes_l;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;full_swath_bytes_c = s-&gt;full_swath_bytes_c;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;prefetch_sw_bytes = s-&gt;prefetch_sw_bytes;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;Tpre_rounded = 0; // don't care</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;Tpre_oto = 0; // don't care</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;estimated_urg_bandwidth_required_mbps = mode_lib-&gt;mp.urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp];</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;estimated_dcfclk_mhz = mode_lib-&gt;mp.Dcfclk;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;line_time = s-&gt;line_times;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;dst_y_prefetch = mode_lib-&gt;mp.dst_y_prefetch;</div><div class='add'>+</div><div class='add'>+		// if recalc_prefetch_schedule is set, recalculate the prefetch schedule with the new impacted_Tpre, prefetch should be possible</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;recalc_prefetch_schedule = &amp;s-&gt;dummy_boolean[0];</div><div class='add'>+		CheckGlobalPrefetchAdmissibility_params-&gt;impacted_dst_y_pre = s-&gt;impacted_dst_y_pre;</div><div class='add'>+		CheckGlobalPrefetchAdmissibility(&amp;mode_lib-&gt;scratch, CheckGlobalPrefetchAdmissibility_params); // dont care about the check output for mode programming</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	{</div><div class='add'>+		s-&gt;DestinationLineTimesForPrefetchLessThan2 = false;</div><div class='add'>+		s-&gt;VRatioPrefetchMoreThanMax = false;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Start one iteration of prefetch schedule evaluation\n", __func__);</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+			struct dml2_core_internal_DmlPipe *myPipe = &amp;s-&gt;myPipe;</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%d MaxVStartupLines = %u\n", __func__, k, s-&gt;MaxVStartupLines[k]);</div><div class='add'>+			mode_lib-&gt;mp.TWait[k] = CalculateTWait(</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].overrides.reserved_vblank_time_ns,</div><div class='add'>+					mode_lib-&gt;mp.UrgentLatency,</div><div class='add'>+					mode_lib-&gt;mp.TripToMemory,</div><div class='add'>+					!dml_is_phantom_pipe(&amp;display_cfg-&gt;plane_descriptors[k]) &amp;&amp; display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.drr_config.enabled ?</div><div class='add'>+					get_g6_temp_read_blackout_us(&amp;mode_lib-&gt;soc, (unsigned int)(mode_lib-&gt;mp.uclk_freq_mhz * 1000), in_out_params-&gt;min_clk_index) : 0.0);</div><div class='add'>+</div><div class='add'>+			myPipe-&gt;Dppclk = mode_lib-&gt;mp.Dppclk[k];</div><div class='add'>+			myPipe-&gt;Dispclk = mode_lib-&gt;mp.Dispclk;</div><div class='add'>+			myPipe-&gt;PixelClock = ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+			myPipe-&gt;DCFClkDeepSleep = mode_lib-&gt;mp.DCFCLKDeepSleep;</div><div class='add'>+			myPipe-&gt;DPPPerSurface = mode_lib-&gt;mp.NoOfDPP[k];</div><div class='add'>+			myPipe-&gt;ScalerEnabled = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.enabled;</div><div class='add'>+			myPipe-&gt;VRatio = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio;</div><div class='add'>+			myPipe-&gt;VRatioChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio;</div><div class='add'>+			myPipe-&gt;VTaps = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_taps;</div><div class='add'>+			myPipe-&gt;VTapsChroma = display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_taps;</div><div class='add'>+			myPipe-&gt;RotationAngle = display_cfg-&gt;plane_descriptors[k].composition.rotation_angle;</div><div class='add'>+			myPipe-&gt;mirrored = display_cfg-&gt;plane_descriptors[k].composition.mirrored;</div><div class='add'>+			myPipe-&gt;BlockWidth256BytesY = mode_lib-&gt;mp.Read256BlockWidthY[k];</div><div class='add'>+			myPipe-&gt;BlockHeight256BytesY = mode_lib-&gt;mp.Read256BlockHeightY[k];</div><div class='add'>+			myPipe-&gt;BlockWidth256BytesC = mode_lib-&gt;mp.Read256BlockWidthC[k];</div><div class='add'>+			myPipe-&gt;BlockHeight256BytesC = mode_lib-&gt;mp.Read256BlockHeightC[k];</div><div class='add'>+			myPipe-&gt;InterlaceEnable = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced;</div><div class='add'>+			myPipe-&gt;NumberOfCursors = display_cfg-&gt;plane_descriptors[k].cursor.num_cursors;</div><div class='add'>+			myPipe-&gt;VBlank = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active;</div><div class='add'>+			myPipe-&gt;HTotal = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total;</div><div class='add'>+			myPipe-&gt;HActive = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_active;</div><div class='add'>+			myPipe-&gt;DCCEnable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+			myPipe-&gt;ODMMode = mode_lib-&gt;mp.ODMMode[k];</div><div class='add'>+			myPipe-&gt;SourcePixelFormat = display_cfg-&gt;plane_descriptors[k].pixel_format;</div><div class='add'>+			myPipe-&gt;BytePerPixelY = mode_lib-&gt;mp.BytePerPixelY[k];</div><div class='add'>+			myPipe-&gt;BytePerPixelC = mode_lib-&gt;mp.BytePerPixelC[k];</div><div class='add'>+			myPipe-&gt;ProgressiveToInterlaceUnitInOPP = mode_lib-&gt;ip.ptoi_supported;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);</div><div class='add'>+#endif</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;display_cfg = display_cfg;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;HostVMInefficiencyFactor = s-&gt;HostVMInefficiencyFactorPrefetch;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;myPipe = myPipe;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DSCDelay = mode_lib-&gt;mp.DSCDelay[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelaySubtotalPlusCNVCFormater = mode_lib-&gt;ip.dppclk_delay_subtotal + mode_lib-&gt;ip.dppclk_delay_cnvc_formatter;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelaySCL = mode_lib-&gt;ip.dppclk_delay_scl;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelaySCLLBOnly = mode_lib-&gt;ip.dppclk_delay_scl_lb_only;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPPCLKDelayCNVCCursor = mode_lib-&gt;ip.dppclk_delay_cnvc_cursor;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DISPCLKDelaySubtotal = mode_lib-&gt;ip.dispclk_delay_subtotal;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DPP_RECOUT_WIDTH = (unsigned int)(mode_lib-&gt;mp.SwathWidthY[k] / display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.h_ratio);</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;OutputFormat = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;MaxInterDCNTileRepeaters = mode_lib-&gt;ip.max_inter_dcn_tile_repeaters;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VStartup = s-&gt;MaxVStartupLines[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;HostVMMinPageSize = mode_lib-&gt;soc.hostvm_min_page_size_kbytes;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataEnable = display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.enable;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataVMEnabled = mode_lib-&gt;ip.dynamic_metadata_vm_enabled;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataLinesBeforeActiveRequired = display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.lines_before_active_required;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DynamicMetadataTransmittedBytes = display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.transmitted_bytes;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;UrgentLatency = mode_lib-&gt;mp.UrgentLatency;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;ExtraLatencyPrefetch = mode_lib-&gt;mp.ExtraLatencyPrefetch;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;TCalc = mode_lib-&gt;mp.TCalc;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;vm_bytes = mode_lib-&gt;mp.vm_bytes[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;PixelPTEBytesPerRow = mode_lib-&gt;mp.PixelPTEBytesPerRow[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;PrefetchSourceLinesY = mode_lib-&gt;mp.PrefetchSourceLinesY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VInitPreFillY = mode_lib-&gt;mp.VInitPreFillY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;MaxNumSwathY = mode_lib-&gt;mp.MaxNumSwathY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;PrefetchSourceLinesC = mode_lib-&gt;mp.PrefetchSourceLinesC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VInitPreFillC = mode_lib-&gt;mp.VInitPreFillC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;MaxNumSwathC = mode_lib-&gt;mp.MaxNumSwathC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;swath_width_luma_ub = mode_lib-&gt;mp.swath_width_luma_ub[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;swath_width_chroma_ub = mode_lib-&gt;mp.swath_width_chroma_ub[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;SwathHeightY = mode_lib-&gt;mp.SwathHeightY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;SwathHeightC = mode_lib-&gt;mp.SwathHeightC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;TWait = mode_lib-&gt;mp.TWait[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Ttrip = mode_lib-&gt;mp.TripToMemory;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Turg = mode_lib-&gt;mp.UrgentLatency;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;setup_for_tdlut = display_cfg-&gt;plane_descriptors[k].tdlut.setup_for_tdlut;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_pte_bytes_per_frame = s-&gt;tdlut_pte_bytes_per_frame[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_bytes_per_frame = s-&gt;tdlut_bytes_per_frame[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_opt_time = s-&gt;tdlut_opt_time[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;tdlut_drain_time = s-&gt;tdlut_drain_time[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;num_cursors = (display_cfg-&gt;plane_descriptors[k].cursor.cursor_width &gt; 0);</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;cursor_bytes_per_chunk = s-&gt;cursor_bytes_per_chunk[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;cursor_bytes_per_line = s-&gt;cursor_bytes_per_line[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dcc_enable = display_cfg-&gt;plane_descriptors[k].surface.dcc.enable;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;meta_row_bytes = mode_lib-&gt;mp.meta_row_bytes[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;mall_prefetch_sdp_overhead_factor = mode_lib-&gt;mp.mall_prefetch_sdp_overhead_factor[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;impacted_dst_y_pre = s-&gt;impacted_dst_y_pre[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;vactive_sw_bw_l = mode_lib-&gt;mp.vactive_sw_bw_l[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;vactive_sw_bw_c = mode_lib-&gt;mp.vactive_sw_bw_c[k];</div><div class='add'>+</div><div class='add'>+			// output</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DSTXAfterScaler = &amp;mode_lib-&gt;mp.DSTXAfterScaler[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;DSTYAfterScaler = &amp;mode_lib-&gt;mp.DSTYAfterScaler[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dst_y_prefetch = &amp;mode_lib-&gt;mp.dst_y_prefetch[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dst_y_per_vm_vblank = &amp;mode_lib-&gt;mp.dst_y_per_vm_vblank[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;dst_y_per_row_vblank = &amp;mode_lib-&gt;mp.dst_y_per_row_vblank[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VRatioPrefetchY = &amp;mode_lib-&gt;mp.VRatioPrefetchY[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VRatioPrefetchC = &amp;mode_lib-&gt;mp.VRatioPrefetchC[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;RequiredPrefetchPixelDataBWLuma = &amp;mode_lib-&gt;mp.RequiredPrefetchPixelDataBWLuma[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;RequiredPrefetchPixelDataBWChroma = &amp;mode_lib-&gt;mp.RequiredPrefetchPixelDataBWChroma[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;RequiredPrefetchBWMax = &amp;s-&gt;dummy_single_array[0][k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;NotEnoughTimeForDynamicMetadata = &amp;mode_lib-&gt;mp.NotEnoughTimeForDynamicMetadata[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tno_bw = &amp;mode_lib-&gt;mp.Tno_bw[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tno_bw_flip = &amp;mode_lib-&gt;mp.Tno_bw_flip[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_vmrow_bw = &amp;mode_lib-&gt;mp.prefetch_vmrow_bw[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tdmdl_vm = &amp;mode_lib-&gt;mp.Tdmdl_vm[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tdmdl = &amp;mode_lib-&gt;mp.Tdmdl[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;TSetup = &amp;mode_lib-&gt;mp.TSetup[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tvm_trips = &amp;s-&gt;Tvm_trips[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tr0_trips = &amp;s-&gt;Tr0_trips[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tvm_trips_flip = &amp;s-&gt;Tvm_trips_flip[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tr0_trips_flip = &amp;s-&gt;Tr0_trips_flip[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tvm_trips_flip_rounded = &amp;s-&gt;Tvm_trips_flip_rounded[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tr0_trips_flip_rounded = &amp;s-&gt;Tr0_trips_flip_rounded[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VUpdateOffsetPix = &amp;mode_lib-&gt;mp.VUpdateOffsetPix[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VUpdateWidthPix = &amp;mode_lib-&gt;mp.VUpdateWidthPix[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;VReadyOffsetPix = &amp;mode_lib-&gt;mp.VReadyOffsetPix[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_cursor_bw = &amp;mode_lib-&gt;mp.prefetch_cursor_bw[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_sw_bytes = &amp;s-&gt;prefetch_sw_bytes[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tpre_rounded = &amp;s-&gt;Tpre_rounded[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;Tpre_oto = &amp;s-&gt;Tpre_oto[k];</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;prefetch_swath_time_us = &amp;s-&gt;dummy_single[0];</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;mp.NoTimeToPrefetch[k] = CalculatePrefetchSchedule(&amp;mode_lib-&gt;scratch, CalculatePrefetchSchedule_params);</div><div class='add'>+</div><div class='add'>+			if (s-&gt;impacted_dst_y_pre[k] &gt; 0)</div><div class='add'>+				mode_lib-&gt;mp.impacted_prefetch_margin_us[k] = (mode_lib-&gt;mp.dst_y_prefetch[k] - s-&gt;impacted_dst_y_pre[k]) * s-&gt;line_times[k];</div><div class='add'>+			else</div><div class='add'>+				mode_lib-&gt;mp.impacted_prefetch_margin_us[k] = 0;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%0u NoTimeToPrefetch=%0d\n", __func__, k, mode_lib-&gt;mp.NoTimeToPrefetch[k]);</div><div class='add'>+#endif</div><div class='add'>+			mode_lib-&gt;mp.VStartupMin[k] = s-&gt;MaxVStartupLines[k];</div><div class='add'>+		} // for k</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;mp.PrefetchModeSupported = true;</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+			if (mode_lib-&gt;mp.NoTimeToPrefetch[k] == true ||</div><div class='add'>+				mode_lib-&gt;mp.NotEnoughTimeForDynamicMetadata[k] ||</div><div class='add'>+				mode_lib-&gt;mp.DSTYAfterScaler[k] &gt; 8) {</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, NoTimeToPrefetch = %0d\n", __func__, k, mode_lib-&gt;mp.NoTimeToPrefetch[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughTimeForDynamicMetadata=%u\n", __func__, k, mode_lib-&gt;mp.NotEnoughTimeForDynamicMetadata[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, DSTYAfterScaler=%u (should be &lt;= 0)\n", __func__, k, mode_lib-&gt;mp.DSTYAfterScaler[k]);</div><div class='add'>+				mode_lib-&gt;mp.PrefetchModeSupported = false;</div><div class='add'>+			}</div><div class='add'>+			if (mode_lib-&gt;mp.dst_y_prefetch[k] &lt; 2)</div><div class='add'>+				s-&gt;DestinationLineTimesForPrefetchLessThan2 = true;</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;mp.VRatioPrefetchY[k] &gt; __DML2_CALCS_MAX_VRATIO_PRE__ ||</div><div class='add'>+				mode_lib-&gt;mp.VRatioPrefetchC[k] &gt; __DML2_CALCS_MAX_VRATIO_PRE__) {</div><div class='add'>+				s-&gt;VRatioPrefetchMoreThanMax = true;</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPrefetchY=%f (should not be &lt; %f)\n", __func__, k, mode_lib-&gt;mp.VRatioPrefetchY[k], __DML2_CALCS_MAX_VRATIO_PRE__);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPrefetchC=%f (should not be &lt; %f)\n", __func__, k, mode_lib-&gt;mp.VRatioPrefetchC[k], __DML2_CALCS_MAX_VRATIO_PRE__);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: VRatioPrefetchMoreThanMax = %u\n", __func__, s-&gt;VRatioPrefetchMoreThanMax);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (mode_lib-&gt;mp.NotEnoughUrgentLatencyHiding[k]) {</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughUrgentLatencyHiding = %u\n", __func__, k, mode_lib-&gt;mp.NotEnoughUrgentLatencyHiding[k]);</div><div class='add'>+				mode_lib-&gt;mp.PrefetchModeSupported = false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (s-&gt;VRatioPrefetchMoreThanMax == true || s-&gt;DestinationLineTimesForPrefetchLessThan2 == true) {</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: VRatioPrefetchMoreThanMax = %u\n", __func__, s-&gt;VRatioPrefetchMoreThanMax);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: DestinationLineTimesForPrefetchLessThan2 = %u\n", __func__, s-&gt;DestinationLineTimesForPrefetchLessThan2);</div><div class='add'>+			mode_lib-&gt;mp.PrefetchModeSupported = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Prefetch schedule is %sOK at vstartup = %u\n", __func__,</div><div class='add'>+			mode_lib-&gt;mp.PrefetchModeSupported ? "" : "NOT ", CalculatePrefetchSchedule_params-&gt;VStartup);</div><div class='add'>+</div><div class='add'>+		// Prefetch schedule OK, now check prefetch bw</div><div class='add'>+		if (mode_lib-&gt;mp.PrefetchModeSupported == true) {</div><div class='add'>+			for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+				double line_time_us = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+					((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+				CalculateUrgentBurstFactor(</div><div class='add'>+					&amp;display_cfg-&gt;plane_descriptors[k],</div><div class='add'>+					mode_lib-&gt;mp.swath_width_luma_ub[k],</div><div class='add'>+					mode_lib-&gt;mp.swath_width_chroma_ub[k],</div><div class='add'>+					mode_lib-&gt;mp.SwathHeightY[k],</div><div class='add'>+					mode_lib-&gt;mp.SwathHeightC[k],</div><div class='add'>+					line_time_us,</div><div class='add'>+					mode_lib-&gt;mp.UrgentLatency,</div><div class='add'>+					mode_lib-&gt;mp.VRatioPrefetchY[k],</div><div class='add'>+					mode_lib-&gt;mp.VRatioPrefetchC[k],</div><div class='add'>+					mode_lib-&gt;mp.BytePerPixelInDETY[k],</div><div class='add'>+					mode_lib-&gt;mp.BytePerPixelInDETC[k],</div><div class='add'>+					mode_lib-&gt;mp.DETBufferSizeY[k],</div><div class='add'>+					mode_lib-&gt;mp.DETBufferSizeC[k],</div><div class='add'>+					/* Output */</div><div class='add'>+					&amp;mode_lib-&gt;mp.UrgentBurstFactorLumaPre[k],</div><div class='add'>+					&amp;mode_lib-&gt;mp.UrgentBurstFactorChromaPre[k],</div><div class='add'>+					&amp;mode_lib-&gt;mp.NotEnoughUrgentLatencyHidingPre[k]);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u DPPPerSurface=%u\n", __func__, k, mode_lib-&gt;mp.NoOfDPP[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorLuma=%f\n", __func__, k, mode_lib-&gt;mp.UrgentBurstFactorLuma[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorChroma=%f\n", __func__, k, mode_lib-&gt;mp.UrgentBurstFactorChroma[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorLumaPre=%f\n", __func__, k, mode_lib-&gt;mp.UrgentBurstFactorLumaPre[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorChromaPre=%f\n", __func__, k, mode_lib-&gt;mp.UrgentBurstFactorChromaPre[k]);</div><div class='add'>+</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u VRatioPrefetchY=%f\n", __func__, k, mode_lib-&gt;mp.VRatioPrefetchY[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u VRatioY=%f\n", __func__, k, display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio);</div><div class='add'>+</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u prefetch_vmrow_bw=%f\n", __func__, k, mode_lib-&gt;mp.prefetch_vmrow_bw[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u vactive_sw_bw_l=%f\n", __func__, k, mode_lib-&gt;mp.vactive_sw_bw_l[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u vactive_sw_bw_c=%f\n", __func__, k, mode_lib-&gt;mp.vactive_sw_bw_c[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u cursor_bw=%f\n", __func__, k, mode_lib-&gt;mp.cursor_bw[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u dpte_row_bw=%f\n", __func__, k, mode_lib-&gt;mp.dpte_row_bw[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u meta_row_bw=%f\n", __func__, k, mode_lib-&gt;mp.meta_row_bw[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u RequiredPrefetchPixelDataBWLuma=%f\n", __func__, k, mode_lib-&gt;mp.RequiredPrefetchPixelDataBWLuma[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u RequiredPrefetchPixelDataBWChroma=%f\n", __func__, k, mode_lib-&gt;mp.RequiredPrefetchPixelDataBWChroma[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k=%0u prefetch_cursor_bw=%f\n", __func__, k, mode_lib-&gt;mp.prefetch_cursor_bw[k]);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			for (k = 0; k &lt;= s-&gt;num_active_planes - 1; k++)</div><div class='add'>+				mode_lib-&gt;mp.final_flip_bw[k] = 0;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_vactive_bandwidth_required = mode_lib-&gt;mp.urg_vactive_bandwidth_required;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_bandwidth_required = mode_lib-&gt;mp.urg_bandwidth_required;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_bandwidth_required_qual = mode_lib-&gt;mp.urg_bandwidth_required_qual;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;non_urg_bandwidth_required = mode_lib-&gt;mp.non_urg_bandwidth_required;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_avg_vactive_required_bw = s-&gt;surface_dummy_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_peak_required_bw = s-&gt;surface_dummy_bw0;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;display_cfg = display_cfg;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;inc_flip_bw = 0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;num_active_planes = s-&gt;num_active_planes;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;num_of_dpp = mode_lib-&gt;mp.NoOfDPP;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p0 = mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p1 = mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p0 = mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p1 = mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;mall_prefetch_sdp_overhead_factor = mode_lib-&gt;mp.mall_prefetch_sdp_overhead_factor;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;mall_prefetch_dram_overhead_factor = mode_lib-&gt;mp.mall_prefetch_dram_overhead_factor;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_l = mode_lib-&gt;mp.vactive_sw_bw_l;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_c = mode_lib-&gt;mp.vactive_sw_bw_c;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_l = mode_lib-&gt;mp.RequiredPrefetchPixelDataBWLuma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_c = mode_lib-&gt;mp.RequiredPrefetchPixelDataBWChroma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_max = s-&gt;dummy_single_array[0];</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_l = mode_lib-&gt;mp.excess_vactive_fill_bw_l;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_c = mode_lib-&gt;mp.excess_vactive_fill_bw_c;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;cursor_bw = mode_lib-&gt;mp.cursor_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dpte_row_bw = mode_lib-&gt;mp.dpte_row_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;meta_row_bw = mode_lib-&gt;mp.meta_row_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_cursor_bw = mode_lib-&gt;mp.prefetch_cursor_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_vmrow_bw = mode_lib-&gt;mp.prefetch_vmrow_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;flip_bw = mode_lib-&gt;mp.final_flip_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_l = mode_lib-&gt;mp.UrgentBurstFactorLuma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_c = mode_lib-&gt;mp.UrgentBurstFactorChroma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_cursor = mode_lib-&gt;mp.UrgentBurstFactorCursor;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_l = mode_lib-&gt;mp.UrgentBurstFactorLumaPre;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_c = mode_lib-&gt;mp.UrgentBurstFactorChromaPre;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_cursor = mode_lib-&gt;mp.UrgentBurstFactorCursorPre;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_required(</div><div class='add'>+					&amp;mode_lib-&gt;scratch,</div><div class='add'>+					calculate_peak_bandwidth_params);</div><div class='add'>+</div><div class='add'>+			// Check urg peak bandwidth against available urg bw</div><div class='add'>+			// check at SDP and DRAM, for all soc states (SVP prefetch an Sys Active)</div><div class='add'>+			check_urgent_bandwidth_support(</div><div class='add'>+				&amp;mode_lib-&gt;mp.FractionOfUrgentBandwidth, // double* frac_urg_bandwidth</div><div class='add'>+				&amp;mode_lib-&gt;mp.FractionOfUrgentBandwidthMALL, // double* frac_urg_bandwidth_mall</div><div class='add'>+				&amp;s-&gt;dummy_boolean[1], // vactive bw ok</div><div class='add'>+				&amp;mode_lib-&gt;mp.PrefetchModeSupported, // prefetch bw ok</div><div class='add'>+</div><div class='add'>+				mode_lib-&gt;soc.mall_allocated_for_dcn_mbytes,</div><div class='add'>+				mode_lib-&gt;mp.non_urg_bandwidth_required,</div><div class='add'>+				mode_lib-&gt;mp.urg_vactive_bandwidth_required,</div><div class='add'>+				mode_lib-&gt;mp.urg_bandwidth_required,</div><div class='add'>+				mode_lib-&gt;mp.urg_bandwidth_available);</div><div class='add'>+</div><div class='add'>+			if (!mode_lib-&gt;mp.PrefetchModeSupported)</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Bandwidth not sufficient for prefetch!\n", __func__);</div><div class='add'>+</div><div class='add'>+			for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+				if (mode_lib-&gt;mp.NotEnoughUrgentLatencyHidingPre[k]) {</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughUrgentLatencyHidingPre = %u\n", __func__, k, mode_lib-&gt;mp.NotEnoughUrgentLatencyHidingPre[k]);</div><div class='add'>+					mode_lib-&gt;mp.PrefetchModeSupported = false;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} // prefetch schedule ok</div><div class='add'>+</div><div class='add'>+		// Prefetch schedule and prefetch bw ok, now check flip bw</div><div class='add'>+		if (mode_lib-&gt;mp.PrefetchModeSupported == true) { // prefetch schedule and prefetch bw ok, now check flip bw</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;mp.BandwidthAvailableForImmediateFlip =</div><div class='add'>+				get_bandwidth_available_for_immediate_flip(</div><div class='add'>+					dml2_core_internal_soc_state_sys_active,</div><div class='add'>+					mode_lib-&gt;mp.urg_bandwidth_required_qual, // no flip</div><div class='add'>+					mode_lib-&gt;mp.urg_bandwidth_available);</div><div class='add'>+			mode_lib-&gt;mp.TotImmediateFlipBytes = 0;</div><div class='add'>+			for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+				if (display_cfg-&gt;plane_descriptors[k].immediate_flip) {</div><div class='add'>+					s-&gt;per_pipe_flip_bytes[k] =  get_pipe_flip_bytes(s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+											mode_lib-&gt;mp.vm_bytes[k],</div><div class='add'>+											mode_lib-&gt;mp.PixelPTEBytesPerRow[k],</div><div class='add'>+											mode_lib-&gt;mp.meta_row_bytes[k]);</div><div class='add'>+				} else {</div><div class='add'>+					s-&gt;per_pipe_flip_bytes[k] = 0;</div><div class='add'>+				}</div><div class='add'>+				mode_lib-&gt;mp.TotImmediateFlipBytes += s-&gt;per_pipe_flip_bytes[k] * mode_lib-&gt;mp.NoOfDPP[k];</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: k = %u\n", __func__, k);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: DPPPerSurface = %u\n", __func__, mode_lib-&gt;mp.NoOfDPP[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: vm_bytes = %u\n", __func__, mode_lib-&gt;mp.vm_bytes[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, mode_lib-&gt;mp.PixelPTEBytesPerRow[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: meta_row_bytes = %u\n", __func__, mode_lib-&gt;mp.meta_row_bytes[k]);</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: TotImmediateFlipBytes = %u\n", __func__, mode_lib-&gt;mp.TotImmediateFlipBytes);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+			for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+				CalculateFlipSchedule(</div><div class='add'>+					&amp;mode_lib-&gt;scratch,</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].immediate_flip,</div><div class='add'>+					0, // use_lb_flip_bw</div><div class='add'>+					s-&gt;HostVMInefficiencyFactor,</div><div class='add'>+					s-&gt;Tvm_trips_flip[k],</div><div class='add'>+					s-&gt;Tr0_trips_flip[k],</div><div class='add'>+					s-&gt;Tvm_trips_flip_rounded[k],</div><div class='add'>+					s-&gt;Tr0_trips_flip_rounded[k],</div><div class='add'>+					display_cfg-&gt;gpuvm_enable,</div><div class='add'>+					mode_lib-&gt;mp.vm_bytes[k],</div><div class='add'>+					mode_lib-&gt;mp.PixelPTEBytesPerRow[k],</div><div class='add'>+					mode_lib-&gt;mp.BandwidthAvailableForImmediateFlip,</div><div class='add'>+					mode_lib-&gt;mp.TotImmediateFlipBytes,</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+					display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane0.v_ratio,</div><div class='add'>+					display_cfg-&gt;plane_descriptors[k].composition.scaler_info.plane1.v_ratio,</div><div class='add'>+					mode_lib-&gt;mp.Tno_bw[k],</div><div class='add'>+					mode_lib-&gt;mp.dpte_row_height[k],</div><div class='add'>+					mode_lib-&gt;mp.dpte_row_height_chroma[k],</div><div class='add'>+					mode_lib-&gt;mp.use_one_row_for_frame_flip[k],</div><div class='add'>+					mode_lib-&gt;ip.max_flip_time_us,</div><div class='add'>+					mode_lib-&gt;ip.max_flip_time_lines,</div><div class='add'>+					s-&gt;per_pipe_flip_bytes[k],</div><div class='add'>+					mode_lib-&gt;mp.meta_row_bytes[k],</div><div class='add'>+					mode_lib-&gt;mp.meta_row_height[k],</div><div class='add'>+					mode_lib-&gt;mp.meta_row_height_chroma[k],</div><div class='add'>+					mode_lib-&gt;ip.dcn_mrq_present &amp;&amp; display_cfg-&gt;plane_descriptors[k].surface.dcc.enable,</div><div class='add'>+</div><div class='add'>+					// Output</div><div class='add'>+					&amp;mode_lib-&gt;mp.dst_y_per_vm_flip[k],</div><div class='add'>+					&amp;mode_lib-&gt;mp.dst_y_per_row_flip[k],</div><div class='add'>+					&amp;mode_lib-&gt;mp.final_flip_bw[k],</div><div class='add'>+					&amp;mode_lib-&gt;mp.ImmediateFlipSupportedForPipe[k]);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_vactive_bandwidth_required = s-&gt;dummy_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_bandwidth_required = mode_lib-&gt;mp.urg_bandwidth_required_flip;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urg_bandwidth_required_qual = s-&gt;dummy_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;non_urg_bandwidth_required = mode_lib-&gt;mp.non_urg_bandwidth_required_flip;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_avg_vactive_required_bw = s-&gt;surface_dummy_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_peak_required_bw = s-&gt;surface_dummy_bw0;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;display_cfg = display_cfg;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;inc_flip_bw = 1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;num_active_planes = s-&gt;num_active_planes;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;num_of_dpp = mode_lib-&gt;mp.NoOfDPP;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p0 = mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_nom_overhead_factor_p1 = mode_lib-&gt;mp.dcc_dram_bw_nom_overhead_factor_p1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p0 = mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p0;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dcc_dram_bw_pref_overhead_factor_p1 = mode_lib-&gt;mp.dcc_dram_bw_pref_overhead_factor_p1;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;mall_prefetch_sdp_overhead_factor = mode_lib-&gt;mp.mall_prefetch_sdp_overhead_factor;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;mall_prefetch_dram_overhead_factor = mode_lib-&gt;mp.mall_prefetch_dram_overhead_factor;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_l = mode_lib-&gt;mp.vactive_sw_bw_l;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;surface_read_bandwidth_c = mode_lib-&gt;mp.vactive_sw_bw_c;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_l = mode_lib-&gt;mp.RequiredPrefetchPixelDataBWLuma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_c = mode_lib-&gt;mp.RequiredPrefetchPixelDataBWChroma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_l = mode_lib-&gt;mp.excess_vactive_fill_bw_l;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;excess_vactive_fill_bw_c = mode_lib-&gt;mp.excess_vactive_fill_bw_c;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;cursor_bw = mode_lib-&gt;mp.cursor_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;dpte_row_bw = mode_lib-&gt;mp.dpte_row_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;meta_row_bw = mode_lib-&gt;mp.meta_row_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_cursor_bw = mode_lib-&gt;mp.prefetch_cursor_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_vmrow_bw = mode_lib-&gt;mp.prefetch_vmrow_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;prefetch_bandwidth_max = s-&gt;dummy_single_array[0];</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;flip_bw = mode_lib-&gt;mp.final_flip_bw;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_l = mode_lib-&gt;mp.UrgentBurstFactorLuma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_c = mode_lib-&gt;mp.UrgentBurstFactorChroma;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_cursor = mode_lib-&gt;mp.UrgentBurstFactorCursor;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_l = mode_lib-&gt;mp.UrgentBurstFactorLumaPre;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_c = mode_lib-&gt;mp.UrgentBurstFactorChromaPre;</div><div class='add'>+			calculate_peak_bandwidth_params-&gt;urgent_burst_factor_prefetch_cursor = mode_lib-&gt;mp.UrgentBurstFactorCursorPre;</div><div class='add'>+</div><div class='add'>+			calculate_peak_bandwidth_required(</div><div class='add'>+					&amp;mode_lib-&gt;scratch,</div><div class='add'>+					calculate_peak_bandwidth_params);</div><div class='add'>+</div><div class='add'>+			calculate_immediate_flip_bandwidth_support(</div><div class='add'>+				&amp;mode_lib-&gt;mp.FractionOfUrgentBandwidthImmediateFlip, // double* frac_urg_bandwidth_flip</div><div class='add'>+				&amp;mode_lib-&gt;mp.ImmediateFlipSupported, // bool* flip_bandwidth_support_ok</div><div class='add'>+</div><div class='add'>+				dml2_core_internal_soc_state_sys_active,</div><div class='add'>+				mode_lib-&gt;mp.urg_bandwidth_required_flip,</div><div class='add'>+				mode_lib-&gt;mp.non_urg_bandwidth_required_flip,</div><div class='add'>+				mode_lib-&gt;mp.urg_bandwidth_available);</div><div class='add'>+</div><div class='add'>+			if (!mode_lib-&gt;mp.ImmediateFlipSupported)</div><div class='add'>+				DML_LOG_VERBOSE("DML::%s: Bandwidth not sufficient for flip!", __func__);</div><div class='add'>+</div><div class='add'>+			for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+				if (display_cfg-&gt;plane_descriptors[k].immediate_flip &amp;&amp; mode_lib-&gt;mp.ImmediateFlipSupportedForPipe[k] == false) {</div><div class='add'>+					mode_lib-&gt;mp.ImmediateFlipSupported = false;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+					DML_LOG_VERBOSE("DML::%s: Pipe %0d not supporting iflip!\n", __func__, k);</div><div class='add'>+#endif</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else { // flip or prefetch not support</div><div class='add'>+			mode_lib-&gt;mp.ImmediateFlipSupported = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// consider flip support is okay if the flip bw is ok or (when user does't require a iflip and there is no host vm)</div><div class='add'>+		must_support_iflip = display_cfg-&gt;hostvm_enable || s-&gt;immediate_flip_required;</div><div class='add'>+		mode_lib-&gt;mp.PrefetchAndImmediateFlipSupported = (mode_lib-&gt;mp.PrefetchModeSupported == true &amp;&amp; (!must_support_iflip || mode_lib-&gt;mp.ImmediateFlipSupported));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: PrefetchModeSupported = %u\n", __func__, mode_lib-&gt;mp.PrefetchModeSupported);</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k)</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: immediate_flip_required[%u] = %u\n", __func__, k, display_cfg-&gt;plane_descriptors[k].immediate_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: HostVMEnable = %u\n", __func__, display_cfg-&gt;hostvm_enable);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: ImmediateFlipSupported = %u\n", __func__, mode_lib-&gt;mp.ImmediateFlipSupported);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: PrefetchAndImmediateFlipSupported = %u\n", __func__, mode_lib-&gt;mp.PrefetchAndImmediateFlipSupported);</div><div class='add'>+#endif</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Done one iteration: k=%d, MaxVStartupLines=%u\n", __func__, k, s-&gt;MaxVStartupLines[k]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; s-&gt;num_active_planes; ++k)</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d MaxVStartupLines = %u\n", __func__, k, s-&gt;MaxVStartupLines[k]);</div><div class='add'>+</div><div class='add'>+	if (!mode_lib-&gt;mp.PrefetchAndImmediateFlipSupported) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Bad, Prefetch and flip scheduling solution NOT found!\n", __func__);</div><div class='add'>+	} else {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: Good, Prefetch and flip scheduling solution found\n", __func__);</div><div class='add'>+</div><div class='add'>+		// DCC Configuration</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: Calculate DCC configuration for surface k=%u\n", __func__, k);</div><div class='add'>+#endif</div><div class='add'>+			CalculateDCCConfiguration(</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].surface.dcc.enable,</div><div class='add'>+				display_cfg-&gt;overrides.dcc_programming_assumes_scan_direction_unknown,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].pixel_format,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].surface.plane0.width,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].surface.plane1.width,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].surface.plane0.height,</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].surface.plane1.height,</div><div class='add'>+				s-&gt;NomDETInKByte,</div><div class='add'>+				mode_lib-&gt;mp.Read256BlockHeightY[k],</div><div class='add'>+				mode_lib-&gt;mp.Read256BlockHeightC[k],</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].surface.tiling,</div><div class='add'>+				mode_lib-&gt;mp.BytePerPixelY[k],</div><div class='add'>+				mode_lib-&gt;mp.BytePerPixelC[k],</div><div class='add'>+				mode_lib-&gt;mp.BytePerPixelInDETY[k],</div><div class='add'>+				mode_lib-&gt;mp.BytePerPixelInDETC[k],</div><div class='add'>+				display_cfg-&gt;plane_descriptors[k].composition.rotation_angle,</div><div class='add'>+</div><div class='add'>+				/* Output */</div><div class='add'>+				&amp;mode_lib-&gt;mp.RequestLuma[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.RequestChroma[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.DCCYMaxUncompressedBlock[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.DCCCMaxUncompressedBlock[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.DCCYMaxCompressedBlock[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.DCCCMaxCompressedBlock[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.DCCYIndependentBlock[k],</div><div class='add'>+				&amp;mode_lib-&gt;mp.DCCCIndependentBlock[k]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		//Watermarks and NB P-State/DRAM Clock Change Support</div><div class='add'>+		s-&gt;mmSOCParameters.UrgentLatency = mode_lib-&gt;mp.UrgentLatency;</div><div class='add'>+		s-&gt;mmSOCParameters.ExtraLatency = mode_lib-&gt;mp.ExtraLatency;</div><div class='add'>+		s-&gt;mmSOCParameters.ExtraLatency_sr = mode_lib-&gt;mp.ExtraLatency_sr;</div><div class='add'>+		s-&gt;mmSOCParameters.WritebackLatency = mode_lib-&gt;soc.qos_parameters.writeback.base_latency_us;</div><div class='add'>+		s-&gt;mmSOCParameters.DRAMClockChangeLatency = mode_lib-&gt;soc.power_management_parameters.dram_clk_change_blackout_us;</div><div class='add'>+		s-&gt;mmSOCParameters.FCLKChangeLatency = mode_lib-&gt;soc.power_management_parameters.fclk_change_blackout_us;</div><div class='add'>+		s-&gt;mmSOCParameters.SRExitTime = mode_lib-&gt;soc.power_management_parameters.stutter_exit_latency_us;</div><div class='add'>+		s-&gt;mmSOCParameters.SREnterPlusExitTime = mode_lib-&gt;soc.power_management_parameters.stutter_enter_plus_exit_latency_us;</div><div class='add'>+		s-&gt;mmSOCParameters.SRExitZ8Time = mode_lib-&gt;soc.power_management_parameters.z8_stutter_exit_latency_us;</div><div class='add'>+		s-&gt;mmSOCParameters.SREnterPlusExitZ8Time = mode_lib-&gt;soc.power_management_parameters.z8_stutter_enter_plus_exit_latency_us;</div><div class='add'>+		s-&gt;mmSOCParameters.USRRetrainingLatency = 0;</div><div class='add'>+		s-&gt;mmSOCParameters.SMNLatency = 0;</div><div class='add'>+		s-&gt;mmSOCParameters.g6_temp_read_blackout_us = get_g6_temp_read_blackout_us(&amp;mode_lib-&gt;soc, (unsigned int)(mode_lib-&gt;mp.uclk_freq_mhz * 1000), in_out_params-&gt;min_clk_index);</div><div class='add'>+		s-&gt;mmSOCParameters.max_urgent_latency_us = get_max_urgent_latency_us(&amp;mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x, mode_lib-&gt;mp.uclk_freq_mhz, mode_lib-&gt;mp.FabricClock, in_out_params-&gt;min_clk_index);</div><div class='add'>+		s-&gt;mmSOCParameters.df_response_time_us = mode_lib-&gt;soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles / mode_lib-&gt;mp.FabricClock;</div><div class='add'>+		s-&gt;mmSOCParameters.qos_type = mode_lib-&gt;soc.qos_parameters.qos_type;</div><div class='add'>+</div><div class='add'>+		CalculateWatermarks_params-&gt;display_cfg = display_cfg;</div><div class='add'>+		CalculateWatermarks_params-&gt;USRRetrainingRequired = false;</div><div class='add'>+		CalculateWatermarks_params-&gt;NumberOfActiveSurfaces = s-&gt;num_active_planes;</div><div class='add'>+		CalculateWatermarks_params-&gt;MaxLineBufferLines = mode_lib-&gt;ip.max_line_buffer_lines;</div><div class='add'>+		CalculateWatermarks_params-&gt;LineBufferSize = mode_lib-&gt;ip.line_buffer_size_bits;</div><div class='add'>+		CalculateWatermarks_params-&gt;WritebackInterfaceBufferSize = mode_lib-&gt;ip.writeback_interface_buffer_size_kbytes;</div><div class='add'>+		CalculateWatermarks_params-&gt;DCFCLK = mode_lib-&gt;mp.Dcfclk;</div><div class='add'>+		CalculateWatermarks_params-&gt;SynchronizeTimings = display_cfg-&gt;overrides.synchronize_timings;</div><div class='add'>+		CalculateWatermarks_params-&gt;SynchronizeDRRDisplaysForUCLKPStateChange = display_cfg-&gt;overrides.synchronize_ddr_displays_for_uclk_pstate_change;</div><div class='add'>+		CalculateWatermarks_params-&gt;dpte_group_bytes = mode_lib-&gt;mp.dpte_group_bytes;</div><div class='add'>+		CalculateWatermarks_params-&gt;mmSOCParameters = s-&gt;mmSOCParameters;</div><div class='add'>+		CalculateWatermarks_params-&gt;WritebackChunkSize = mode_lib-&gt;ip.writeback_chunk_size_kbytes;</div><div class='add'>+		CalculateWatermarks_params-&gt;SOCCLK = s-&gt;SOCCLK;</div><div class='add'>+		CalculateWatermarks_params-&gt;DCFClkDeepSleep = mode_lib-&gt;mp.DCFCLKDeepSleep;</div><div class='add'>+		CalculateWatermarks_params-&gt;DETBufferSizeY = mode_lib-&gt;mp.DETBufferSizeY;</div><div class='add'>+		CalculateWatermarks_params-&gt;DETBufferSizeC = mode_lib-&gt;mp.DETBufferSizeC;</div><div class='add'>+		CalculateWatermarks_params-&gt;SwathHeightY = mode_lib-&gt;mp.SwathHeightY;</div><div class='add'>+		CalculateWatermarks_params-&gt;SwathHeightC = mode_lib-&gt;mp.SwathHeightC;</div><div class='add'>+		CalculateWatermarks_params-&gt;SwathWidthY = mode_lib-&gt;mp.SwathWidthY;</div><div class='add'>+		CalculateWatermarks_params-&gt;SwathWidthC = mode_lib-&gt;mp.SwathWidthC;</div><div class='add'>+		CalculateWatermarks_params-&gt;BytePerPixelDETY = mode_lib-&gt;mp.BytePerPixelInDETY;</div><div class='add'>+		CalculateWatermarks_params-&gt;BytePerPixelDETC = mode_lib-&gt;mp.BytePerPixelInDETC;</div><div class='add'>+		CalculateWatermarks_params-&gt;DSTXAfterScaler = mode_lib-&gt;mp.DSTXAfterScaler;</div><div class='add'>+		CalculateWatermarks_params-&gt;DSTYAfterScaler = mode_lib-&gt;mp.DSTYAfterScaler;</div><div class='add'>+		CalculateWatermarks_params-&gt;UnboundedRequestEnabled = mode_lib-&gt;mp.UnboundedRequestEnabled;</div><div class='add'>+		CalculateWatermarks_params-&gt;CompressedBufferSizeInkByte = mode_lib-&gt;mp.CompressedBufferSizeInkByte;</div><div class='add'>+		CalculateWatermarks_params-&gt;meta_row_height_l = mode_lib-&gt;mp.meta_row_height;</div><div class='add'>+		CalculateWatermarks_params-&gt;meta_row_height_c = mode_lib-&gt;mp.meta_row_height_chroma;</div><div class='add'>+		CalculateWatermarks_params-&gt;DPPPerSurface = mode_lib-&gt;mp.NoOfDPP;</div><div class='add'>+</div><div class='add'>+		// Output</div><div class='add'>+		CalculateWatermarks_params-&gt;Watermark = &amp;mode_lib-&gt;mp.Watermark;</div><div class='add'>+		CalculateWatermarks_params-&gt;DRAMClockChangeSupport = mode_lib-&gt;mp.DRAMClockChangeSupport;</div><div class='add'>+		CalculateWatermarks_params-&gt;global_dram_clock_change_supported = &amp;mode_lib-&gt;mp.global_dram_clock_change_supported;</div><div class='add'>+		CalculateWatermarks_params-&gt;MaxActiveDRAMClockChangeLatencySupported = mode_lib-&gt;mp.MaxActiveDRAMClockChangeLatencySupported;</div><div class='add'>+		CalculateWatermarks_params-&gt;SubViewportLinesNeededInMALL = mode_lib-&gt;mp.SubViewportLinesNeededInMALL;</div><div class='add'>+		CalculateWatermarks_params-&gt;FCLKChangeSupport = mode_lib-&gt;mp.FCLKChangeSupport;</div><div class='add'>+		CalculateWatermarks_params-&gt;global_fclk_change_supported = &amp;mode_lib-&gt;mp.global_fclk_change_supported;</div><div class='add'>+		CalculateWatermarks_params-&gt;MaxActiveFCLKChangeLatencySupported = &amp;mode_lib-&gt;mp.MaxActiveFCLKChangeLatencySupported;</div><div class='add'>+		CalculateWatermarks_params-&gt;USRRetrainingSupport = &amp;mode_lib-&gt;mp.USRRetrainingSupport;</div><div class='add'>+		CalculateWatermarks_params-&gt;g6_temp_read_support = &amp;mode_lib-&gt;mp.g6_temp_read_support;</div><div class='add'>+		CalculateWatermarks_params-&gt;VActiveLatencyHidingMargin = 0;</div><div class='add'>+		CalculateWatermarks_params-&gt;VActiveLatencyHidingUs = 0;</div><div class='add'>+</div><div class='add'>+		CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(&amp;mode_lib-&gt;scratch, CalculateWatermarks_params);</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+				mode_lib-&gt;mp.WritebackAllowDRAMClockChangeEndPosition[k] = math_max2(0, mode_lib-&gt;mp.VStartupMin[k] * display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+					((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib-&gt;mp.Watermark.WritebackDRAMClockChangeWatermark);</div><div class='add'>+				mode_lib-&gt;mp.WritebackAllowFCLKChangeEndPosition[k] = math_max2(0, mode_lib-&gt;mp.VStartupMin[k] * display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total /</div><div class='add'>+					((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib-&gt;mp.Watermark.WritebackFCLKChangeWatermark);</div><div class='add'>+			} else {</div><div class='add'>+				mode_lib-&gt;mp.WritebackAllowDRAMClockChangeEndPosition[k] = 0;</div><div class='add'>+				mode_lib-&gt;mp.WritebackAllowFCLKChangeEndPosition[k] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		calculate_pstate_keepout_dst_lines(display_cfg, &amp;mode_lib-&gt;mp.Watermark, mode_lib-&gt;mp.pstate_keepout_dst_lines);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: DEBUG stream_index = %0d\n", __func__, display_cfg-&gt;plane_descriptors[0].stream_index);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: DEBUG PixelClock = %ld kHz\n", __func__, (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[0].stream_index].timing.pixel_clock_khz));</div><div class='add'>+</div><div class='add'>+		//Display Pipeline Delivery Time in Prefetch, Groups</div><div class='add'>+		CalculatePixelDeliveryTimes(</div><div class='add'>+			display_cfg,</div><div class='add'>+			cfg_support_info,</div><div class='add'>+			s-&gt;num_active_planes,</div><div class='add'>+			mode_lib-&gt;mp.VRatioPrefetchY,</div><div class='add'>+			mode_lib-&gt;mp.VRatioPrefetchC,</div><div class='add'>+			mode_lib-&gt;mp.swath_width_luma_ub,</div><div class='add'>+			mode_lib-&gt;mp.swath_width_chroma_ub,</div><div class='add'>+			mode_lib-&gt;mp.PSCL_THROUGHPUT,</div><div class='add'>+			mode_lib-&gt;mp.PSCL_THROUGHPUT_CHROMA,</div><div class='add'>+			mode_lib-&gt;mp.Dppclk,</div><div class='add'>+			mode_lib-&gt;mp.BytePerPixelC,</div><div class='add'>+			mode_lib-&gt;mp.req_per_swath_ub_l,</div><div class='add'>+			mode_lib-&gt;mp.req_per_swath_ub_c,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeLuma,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeChroma,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeLumaPrefetch,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeChromaPrefetch,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeLuma,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeChroma,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeLumaPrefetch,</div><div class='add'>+			mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeChromaPrefetch);</div><div class='add'>+</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;scratch = &amp;mode_lib-&gt;scratch;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;display_cfg = display_cfg;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;NumberOfActiveSurfaces = s-&gt;num_active_planes;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;use_one_row_for_frame = mode_lib-&gt;mp.use_one_row_for_frame;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dst_y_per_row_vblank = mode_lib-&gt;mp.dst_y_per_row_vblank;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dst_y_per_row_flip = mode_lib-&gt;mp.dst_y_per_row_flip;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;BytePerPixelY = mode_lib-&gt;mp.BytePerPixelY;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;BytePerPixelC = mode_lib-&gt;mp.BytePerPixelC;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dpte_row_height = mode_lib-&gt;mp.dpte_row_height;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dpte_row_height_chroma = mode_lib-&gt;mp.dpte_row_height_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dpte_group_bytes = mode_lib-&gt;mp.dpte_group_bytes;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;PTERequestSizeY = mode_lib-&gt;mp.PTERequestSizeY;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;PTERequestSizeC = mode_lib-&gt;mp.PTERequestSizeC;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;PixelPTEReqWidthY = mode_lib-&gt;mp.PixelPTEReqWidthY;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;PixelPTEReqHeightY = mode_lib-&gt;mp.PixelPTEReqHeightY;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;PixelPTEReqWidthC = mode_lib-&gt;mp.PixelPTEReqWidthC;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;PixelPTEReqHeightC = mode_lib-&gt;mp.PixelPTEReqHeightC;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dpte_row_width_luma_ub = mode_lib-&gt;mp.dpte_row_width_luma_ub;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;dpte_row_width_chroma_ub = mode_lib-&gt;mp.dpte_row_width_chroma_ub;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;tdlut_groups_per_2row_ub = s-&gt;tdlut_groups_per_2row_ub;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;mrq_present = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;MetaChunkSize = mode_lib-&gt;ip.meta_chunk_size_kbytes;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;MinMetaChunkSizeBytes = mode_lib-&gt;ip.min_meta_chunk_size_bytes;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_row_width = mode_lib-&gt;mp.meta_row_width;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_row_width_chroma = mode_lib-&gt;mp.meta_row_width_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_row_height = mode_lib-&gt;mp.meta_row_height;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_row_height_chroma = mode_lib-&gt;mp.meta_row_height_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_req_width = mode_lib-&gt;mp.meta_req_width;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_req_width_chroma = mode_lib-&gt;mp.meta_req_width_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_req_height = mode_lib-&gt;mp.meta_req_height;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;meta_req_height_chroma = mode_lib-&gt;mp.meta_req_height_chroma;</div><div class='add'>+</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_tdlut_group = mode_lib-&gt;mp.time_per_tdlut_group;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;DST_Y_PER_PTE_ROW_NOM_L = mode_lib-&gt;mp.DST_Y_PER_PTE_ROW_NOM_L;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;DST_Y_PER_PTE_ROW_NOM_C = mode_lib-&gt;mp.DST_Y_PER_PTE_ROW_NOM_C;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_pte_group_nom_luma = mode_lib-&gt;mp.time_per_pte_group_nom_luma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_pte_group_vblank_luma = mode_lib-&gt;mp.time_per_pte_group_vblank_luma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_pte_group_flip_luma = mode_lib-&gt;mp.time_per_pte_group_flip_luma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_pte_group_nom_chroma = mode_lib-&gt;mp.time_per_pte_group_nom_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_pte_group_vblank_chroma = mode_lib-&gt;mp.time_per_pte_group_vblank_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;time_per_pte_group_flip_chroma = mode_lib-&gt;mp.time_per_pte_group_flip_chroma;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;DST_Y_PER_META_ROW_NOM_L = mode_lib-&gt;mp.DST_Y_PER_META_ROW_NOM_L;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;DST_Y_PER_META_ROW_NOM_C = mode_lib-&gt;mp.DST_Y_PER_META_ROW_NOM_C;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;TimePerMetaChunkNominal = mode_lib-&gt;mp.TimePerMetaChunkNominal;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;TimePerChromaMetaChunkNominal = mode_lib-&gt;mp.TimePerChromaMetaChunkNominal;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;TimePerMetaChunkVBlank = mode_lib-&gt;mp.TimePerMetaChunkVBlank;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;TimePerChromaMetaChunkVBlank = mode_lib-&gt;mp.TimePerChromaMetaChunkVBlank;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;TimePerMetaChunkFlip = mode_lib-&gt;mp.TimePerMetaChunkFlip;</div><div class='add'>+		CalculateMetaAndPTETimes_params-&gt;TimePerChromaMetaChunkFlip = mode_lib-&gt;mp.TimePerChromaMetaChunkFlip;</div><div class='add'>+</div><div class='add'>+		CalculateMetaAndPTETimes(CalculateMetaAndPTETimes_params);</div><div class='add'>+</div><div class='add'>+		CalculateVMGroupAndRequestTimes(</div><div class='add'>+			display_cfg,</div><div class='add'>+			s-&gt;num_active_planes,</div><div class='add'>+			mode_lib-&gt;mp.BytePerPixelC,</div><div class='add'>+			mode_lib-&gt;mp.dst_y_per_vm_vblank,</div><div class='add'>+			mode_lib-&gt;mp.dst_y_per_vm_flip,</div><div class='add'>+			mode_lib-&gt;mp.dpte_row_width_luma_ub,</div><div class='add'>+			mode_lib-&gt;mp.dpte_row_width_chroma_ub,</div><div class='add'>+			mode_lib-&gt;mp.vm_group_bytes,</div><div class='add'>+			mode_lib-&gt;mp.dpde0_bytes_per_frame_ub_l,</div><div class='add'>+			mode_lib-&gt;mp.dpde0_bytes_per_frame_ub_c,</div><div class='add'>+			s-&gt;tdlut_pte_bytes_per_frame,</div><div class='add'>+			mode_lib-&gt;mp.meta_pte_bytes_per_frame_ub_l,</div><div class='add'>+			mode_lib-&gt;mp.meta_pte_bytes_per_frame_ub_c,</div><div class='add'>+			mode_lib-&gt;ip.dcn_mrq_present,</div><div class='add'>+</div><div class='add'>+			/* Output */</div><div class='add'>+			mode_lib-&gt;mp.TimePerVMGroupVBlank,</div><div class='add'>+			mode_lib-&gt;mp.TimePerVMGroupFlip,</div><div class='add'>+			mode_lib-&gt;mp.TimePerVMRequestVBlank,</div><div class='add'>+			mode_lib-&gt;mp.TimePerVMRequestFlip);</div><div class='add'>+</div><div class='add'>+		// VStartup Adjustment</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+			bool isInterlaceTiming;</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;mp.MinTTUVBlank[k] = mode_lib-&gt;mp.TWait[k] + mode_lib-&gt;mp.ExtraLatency;</div><div class='add'>+			if (!display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.enable)</div><div class='add'>+				mode_lib-&gt;mp.MinTTUVBlank[k] = mode_lib-&gt;mp.TCalc + mode_lib-&gt;mp.MinTTUVBlank[k];</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k, mode_lib-&gt;mp.MinTTUVBlank[k]);</div><div class='add'>+#endif</div><div class='add'>+			s-&gt;Tvstartup_margin = (s-&gt;MaxVStartupLines[k] - mode_lib-&gt;mp.VStartupMin[k]) * display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);</div><div class='add'>+			mode_lib-&gt;mp.MinTTUVBlank[k] = mode_lib-&gt;mp.MinTTUVBlank[k] + s-&gt;Tvstartup_margin;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, Tvstartup_margin = %f\n", __func__, k, s-&gt;Tvstartup_margin);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, MaxVStartupLines = %u\n", __func__, k, s-&gt;MaxVStartupLines[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlank = %f\n", __func__, k, mode_lib-&gt;mp.MinTTUVBlank[k]);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+			mode_lib-&gt;mp.Tdmdl[k] = mode_lib-&gt;mp.Tdmdl[k] + s-&gt;Tvstartup_margin;</div><div class='add'>+			if (display_cfg-&gt;plane_descriptors[k].dynamic_meta_data.enable &amp;&amp; mode_lib-&gt;ip.dynamic_metadata_vm_enabled) {</div><div class='add'>+				mode_lib-&gt;mp.Tdmdl_vm[k] = mode_lib-&gt;mp.Tdmdl_vm[k] + s-&gt;Tvstartup_margin;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			isInterlaceTiming = (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.interlaced &amp;&amp; !mode_lib-&gt;ip.ptoi_supported);</div><div class='add'>+</div><div class='add'>+			// The actual positioning of the vstartup</div><div class='add'>+			mode_lib-&gt;mp.VStartup[k] = (isInterlaceTiming ? (2 * s-&gt;MaxVStartupLines[k]) : s-&gt;MaxVStartupLines[k]);</div><div class='add'>+</div><div class='add'>+			s-&gt;dlg_vblank_start = ((isInterlaceTiming ? math_floor2((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_front_porch) / 2.0, 1.0) :</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total) - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_front_porch);</div><div class='add'>+			s-&gt;LSetup = math_floor2(4.0 * mode_lib-&gt;mp.TSetup[k] / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)), 1.0) / 4.0;</div><div class='add'>+			s-&gt;blank_lines_remaining = (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active) - mode_lib-&gt;mp.VStartup[k];</div><div class='add'>+</div><div class='add'>+			if (s-&gt;blank_lines_remaining &lt; 0) {</div><div class='add'>+				DML_LOG_VERBOSE("ERROR: Vstartup is larger than vblank!?\n");</div><div class='add'>+				s-&gt;blank_lines_remaining = 0;</div><div class='add'>+				DML_ASSERT(0);</div><div class='add'>+			}</div><div class='add'>+			mode_lib-&gt;mp.MIN_DST_Y_NEXT_START[k] = s-&gt;dlg_vblank_start + s-&gt;blank_lines_remaining + s-&gt;LSetup;</div><div class='add'>+</div><div class='add'>+			// debug only</div><div class='add'>+			if (((mode_lib-&gt;mp.VUpdateOffsetPix[k] + mode_lib-&gt;mp.VUpdateWidthPix[k] + mode_lib-&gt;mp.VReadyOffsetPix[k]) / (double) display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total) &lt;=</div><div class='add'>+				(isInterlaceTiming ?</div><div class='add'>+					math_floor2((display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib-&gt;mp.VStartup[k]) / 2.0, 1.0) :</div><div class='add'>+					(int)(display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib-&gt;mp.VStartup[k]))) {</div><div class='add'>+				mode_lib-&gt;mp.VREADY_AT_OR_AFTER_VSYNC[k] = true;</div><div class='add'>+			} else {</div><div class='add'>+				mode_lib-&gt;mp.VREADY_AT_OR_AFTER_VSYNC[k] = false;</div><div class='add'>+			}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VStartup = %u (max)\n", __func__, k, mode_lib-&gt;mp.VStartup[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VStartupMin = %u (max)\n", __func__, k, mode_lib-&gt;mp.VStartupMin[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VUpdateOffsetPix = %u\n", __func__, k, mode_lib-&gt;mp.VUpdateOffsetPix[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VUpdateWidthPix = %u\n", __func__, k, mode_lib-&gt;mp.VUpdateWidthPix[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VReadyOffsetPix = %u\n", __func__, k, mode_lib-&gt;mp.VReadyOffsetPix[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, HTotal = %lu\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.h_total);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VTotal = %lu\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_total);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VActive = %lu\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_active);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VFrontPorch = %lu\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.v_front_porch);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, TSetup = %f\n", __func__, k, mode_lib-&gt;mp.TSetup[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f\n", __func__, k, mode_lib-&gt;mp.MIN_DST_Y_NEXT_START[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, mode_lib-&gt;mp.VREADY_AT_OR_AFTER_VSYNC[k]);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		//Maximum Bandwidth Used</div><div class='add'>+		mode_lib-&gt;mp.TotalWRBandwidth = 0;</div><div class='add'>+		for (k = 0; k &lt; display_cfg-&gt;num_streams; ++k) {</div><div class='add'>+			s-&gt;WRBandwidth = 0;</div><div class='add'>+			if (display_cfg-&gt;stream_descriptors[k].writeback.active_writebacks_per_stream &gt; 0) {</div><div class='add'>+				s-&gt;WRBandwidth = display_cfg-&gt;stream_descriptors[k].writeback.writeback_stream[0].output_height</div><div class='add'>+					* display_cfg-&gt;stream_descriptors[k].writeback.writeback_stream[0].output_width /</div><div class='add'>+					(display_cfg-&gt;stream_descriptors[k].timing.h_total * display_cfg-&gt;stream_descriptors[k].writeback.writeback_stream[0].input_height</div><div class='add'>+						/ ((double)display_cfg-&gt;stream_descriptors[k].timing.pixel_clock_khz / 1000))</div><div class='add'>+					* (display_cfg-&gt;stream_descriptors[k].writeback.writeback_stream[0].pixel_format == dml2_444_32 ? 4.0 : 8.0);</div><div class='add'>+				mode_lib-&gt;mp.TotalWRBandwidth = mode_lib-&gt;mp.TotalWRBandwidth + s-&gt;WRBandwidth;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mode_lib-&gt;mp.TotalDataReadBandwidth = 0;</div><div class='add'>+		for (k = 0; k &lt; s-&gt;num_active_planes; ++k) {</div><div class='add'>+			mode_lib-&gt;mp.TotalDataReadBandwidth = mode_lib-&gt;mp.TotalDataReadBandwidth + mode_lib-&gt;mp.vactive_sw_bw_l[k] + mode_lib-&gt;mp.vactive_sw_bw_c[k];</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, mode_lib-&gt;mp.TotalDataReadBandwidth);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_l = %f\n", __func__, k, mode_lib-&gt;mp.vactive_sw_bw_l[k]);</div><div class='add'>+			DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_c = %f\n", __func__, k, mode_lib-&gt;mp.vactive_sw_bw_c[k]);</div><div class='add'>+#endif</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;display_cfg = display_cfg;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;CompressedBufferSizeInkByte = mode_lib-&gt;mp.CompressedBufferSizeInkByte;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;UnboundedRequestEnabled = mode_lib-&gt;mp.UnboundedRequestEnabled;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;MetaFIFOSizeInKEntries = mode_lib-&gt;ip.meta_fifo_size_in_kentries;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;ZeroSizeBufferEntries = mode_lib-&gt;ip.zero_size_buffer_entries;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;PixelChunkSizeInKByte = mode_lib-&gt;ip.pixel_chunk_size_kbytes;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;NumberOfActiveSurfaces = s-&gt;num_active_planes;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;ROBBufferSizeInKByte = mode_lib-&gt;ip.rob_buffer_size_kbytes;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;TotalDataReadBandwidth = mode_lib-&gt;mp.TotalDataReadBandwidth;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;DCFCLK = mode_lib-&gt;mp.Dcfclk;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;ReturnBW = mode_lib-&gt;mp.urg_bandwidth_available_min[dml2_core_internal_soc_state_sys_active];</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;CompbufReservedSpace64B = mode_lib-&gt;mp.compbuf_reserved_space_64b;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;CompbufReservedSpaceZs = mode_lib-&gt;ip.compbuf_reserved_space_zs;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;SRExitTime = mode_lib-&gt;soc.power_management_parameters.stutter_exit_latency_us;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;SRExitZ8Time = mode_lib-&gt;soc.power_management_parameters.z8_stutter_exit_latency_us;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;SynchronizeTimings = display_cfg-&gt;overrides.synchronize_timings;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;StutterEnterPlusExitWatermark = mode_lib-&gt;mp.Watermark.StutterEnterPlusExitWatermark;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8StutterEnterPlusExitWatermark = mode_lib-&gt;mp.Watermark.Z8StutterEnterPlusExitWatermark;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;ProgressiveToInterlaceUnitInOPP = mode_lib-&gt;ip.ptoi_supported;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;MinTTUVBlank = mode_lib-&gt;mp.MinTTUVBlank;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;DPPPerSurface = mode_lib-&gt;mp.NoOfDPP;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;DETBufferSizeY = mode_lib-&gt;mp.DETBufferSizeY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;BytePerPixelY = mode_lib-&gt;mp.BytePerPixelY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;BytePerPixelDETY = mode_lib-&gt;mp.BytePerPixelInDETY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;SwathWidthY = mode_lib-&gt;mp.SwathWidthY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;SwathHeightY = mode_lib-&gt;mp.SwathHeightY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;SwathHeightC = mode_lib-&gt;mp.SwathHeightC;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;BlockHeight256BytesY = mode_lib-&gt;mp.Read256BlockHeightY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;BlockWidth256BytesY = mode_lib-&gt;mp.Read256BlockWidthY;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;BlockHeight256BytesC = mode_lib-&gt;mp.Read256BlockHeightC;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;BlockWidth256BytesC = mode_lib-&gt;mp.Read256BlockWidthC;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;DCCYMaxUncompressedBlock = mode_lib-&gt;mp.DCCYMaxUncompressedBlock;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;DCCCMaxUncompressedBlock = mode_lib-&gt;mp.DCCCMaxUncompressedBlock;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;ReadBandwidthSurfaceLuma = mode_lib-&gt;mp.vactive_sw_bw_l;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;ReadBandwidthSurfaceChroma = mode_lib-&gt;mp.vactive_sw_bw_c;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;dpte_row_bw = mode_lib-&gt;mp.dpte_row_bw;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;meta_row_bw = mode_lib-&gt;mp.meta_row_bw;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;rob_alloc_compressed = mode_lib-&gt;ip.dcn_mrq_present;</div><div class='add'>+</div><div class='add'>+		// output</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;StutterEfficiencyNotIncludingVBlank = &amp;mode_lib-&gt;mp.StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;StutterEfficiency = &amp;mode_lib-&gt;mp.StutterEfficiency;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;NumberOfStutterBurstsPerFrame = &amp;mode_lib-&gt;mp.NumberOfStutterBurstsPerFrame;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8StutterEfficiencyNotIncludingVBlank = &amp;mode_lib-&gt;mp.Z8StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8StutterEfficiency = &amp;mode_lib-&gt;mp.Z8StutterEfficiency;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8NumberOfStutterBurstsPerFrame = &amp;mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrame;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;StutterPeriod = &amp;mode_lib-&gt;mp.StutterPeriod;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE = &amp;mode_lib-&gt;mp.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;</div><div class='add'>+</div><div class='add'>+		// Stutter Efficiency</div><div class='add'>+		CalculateStutterEfficiency(&amp;mode_lib-&gt;scratch, CalculateStutterEfficiency_params);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_ALLOW_DELTA__</div><div class='add'>+		// Calculate z8 stutter eff assuming 0 reserved space</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;CompbufReservedSpace64B = 0;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;CompbufReservedSpaceZs = 0;</div><div class='add'>+</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8StutterEfficiencyNotIncludingVBlank = &amp;mode_lib-&gt;mp.Z8StutterEfficiencyNotIncludingVBlankBestCase;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8StutterEfficiency = &amp;mode_lib-&gt;mp.Z8StutterEfficiencyBestCase;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;Z8NumberOfStutterBurstsPerFrame = &amp;mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrameBestCase;</div><div class='add'>+		CalculateStutterEfficiency_params-&gt;StutterPeriod = &amp;mode_lib-&gt;mp.StutterPeriodBestCase;</div><div class='add'>+</div><div class='add'>+		// Stutter Efficiency</div><div class='add'>+		CalculateStutterEfficiency(&amp;mode_lib-&gt;scratch, CalculateStutterEfficiency_params);</div><div class='add'>+#else</div><div class='add'>+		mode_lib-&gt;mp.Z8StutterEfficiencyNotIncludingVBlankBestCase = mode_lib-&gt;mp.Z8StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+		mode_lib-&gt;mp.Z8StutterEfficiencyBestCase = mode_lib-&gt;mp.Z8StutterEfficiency;</div><div class='add'>+		mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrameBestCase = mode_lib-&gt;mp.Z8NumberOfStutterBurstsPerFrame;</div><div class='add'>+		mode_lib-&gt;mp.StutterPeriodBestCase = mode_lib-&gt;mp.StutterPeriod;</div><div class='add'>+#endif</div><div class='add'>+	} // PrefetchAndImmediateFlipSupported</div><div class='add'>+</div><div class='add'>+	max_uclk_mhz = mode_lib-&gt;soc.clk_table.uclk.clk_values_khz[mode_lib-&gt;soc.clk_table.uclk.num_clk_values - 1] / 1000.0;</div><div class='add'>+	min_return_latency_in_DCFCLK_cycles = (min_return_uclk_cycles / max_uclk_mhz + min_return_fclk_cycles / max_fclk_mhz) * hard_minimum_dcfclk_mhz;</div><div class='add'>+	mode_lib-&gt;mp.min_return_latency_in_dcfclk = (unsigned int)min_return_latency_in_DCFCLK_cycles;</div><div class='add'>+	mode_lib-&gt;mp.dcfclk_deep_sleep_hysteresis = (unsigned int)math_max2(32, (double)mode_lib-&gt;ip.pixel_chunk_size_kbytes * 1024 * 3 / 4 / 64 - min_return_latency_in_DCFCLK_cycles);</div><div class='add'>+	DML_ASSERT(mode_lib-&gt;mp.dcfclk_deep_sleep_hysteresis &lt; 256);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_fclk_mhz = %f\n", __func__, max_fclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_uclk_mhz = %f\n", __func__, max_uclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: hard_minimum_dcfclk_mhz = %f\n", __func__, hard_minimum_dcfclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_return_uclk_cycles = %ld\n", __func__, min_return_uclk_cycles);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_return_fclk_cycles = %ld\n", __func__, min_return_fclk_cycles);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: min_return_latency_in_DCFCLK_cycles = %f\n", __func__, min_return_latency_in_DCFCLK_cycles);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dcfclk_deep_sleep_hysteresis = %d \n", __func__, mode_lib-&gt;mp.dcfclk_deep_sleep_hysteresis);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: --- END --- \n", __func__);</div><div class='add'>+#endif</div><div class='add'>+	return (in_out_params-&gt;mode_lib-&gt;mp.PrefetchAndImmediateFlipSupported);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_calcs_mode_programming_ex(struct dml2_core_calcs_mode_programming_ex *in_out_params)</div><div class='add'>+{</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ------------- START ----------\n", __func__);</div><div class='add'>+	bool result = dml_core_mode_programming(in_out_params);</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: result = %0d\n", __func__, result);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: ------------- DONE ----------\n", __func__);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_dpte_row_height(</div><div class='add'>+						unsigned int							   *dpte_row_height,</div><div class='add'>+						struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+						bool										is_plane1,</div><div class='add'>+						enum dml2_source_format_class				SourcePixelFormat,</div><div class='add'>+						enum dml2_swizzle_mode						SurfaceTiling,</div><div class='add'>+						enum dml2_rotation_angle					ScanDirection,</div><div class='add'>+						unsigned int								pitch,</div><div class='add'>+						unsigned int								GPUVMMinPageSizeKBytes)</div><div class='add'>+{</div><div class='add'>+	unsigned int BytePerPixelY;</div><div class='add'>+	unsigned int BytePerPixelC;</div><div class='add'>+	double BytePerPixelInDETY;</div><div class='add'>+	double BytePerPixelInDETC;</div><div class='add'>+	unsigned int BlockHeight256BytesY;</div><div class='add'>+	unsigned int BlockHeight256BytesC;</div><div class='add'>+	unsigned int BlockWidth256BytesY;</div><div class='add'>+	unsigned int BlockWidth256BytesC;</div><div class='add'>+	unsigned int MacroTileWidthY;</div><div class='add'>+	unsigned int MacroTileWidthC;</div><div class='add'>+	unsigned int MacroTileHeightY;</div><div class='add'>+	unsigned int MacroTileHeightC;</div><div class='add'>+	bool surf_linear_128_l = false;</div><div class='add'>+	bool surf_linear_128_c = false;</div><div class='add'>+</div><div class='add'>+	CalculateBytePerPixelAndBlockSizes(</div><div class='add'>+		SourcePixelFormat,</div><div class='add'>+		SurfaceTiling,</div><div class='add'>+		pitch,</div><div class='add'>+		pitch,</div><div class='add'>+</div><div class='add'>+		/* Output */</div><div class='add'>+		&amp;BytePerPixelY,</div><div class='add'>+		&amp;BytePerPixelC,</div><div class='add'>+		&amp;BytePerPixelInDETY,</div><div class='add'>+		&amp;BytePerPixelInDETC,</div><div class='add'>+		&amp;BlockHeight256BytesY,</div><div class='add'>+		&amp;BlockHeight256BytesC,</div><div class='add'>+		&amp;BlockWidth256BytesY,</div><div class='add'>+		&amp;BlockWidth256BytesC,</div><div class='add'>+		&amp;MacroTileHeightY,</div><div class='add'>+		&amp;MacroTileHeightC,</div><div class='add'>+		&amp;MacroTileWidthY,</div><div class='add'>+		&amp;MacroTileWidthC,</div><div class='add'>+		&amp;surf_linear_128_l,</div><div class='add'>+		&amp;surf_linear_128_c);</div><div class='add'>+</div><div class='add'>+	unsigned int BytePerPixel			= is_plane1 ? BytePerPixelC : BytePerPixelY;</div><div class='add'>+	unsigned int BlockHeight256Bytes	= is_plane1 ? BlockHeight256BytesC : BlockHeight256BytesY;</div><div class='add'>+	unsigned int BlockWidth256Bytes		= is_plane1 ? BlockWidth256BytesC  : BlockWidth256BytesY;</div><div class='add'>+	unsigned int MacroTileWidth			= is_plane1 ? MacroTileWidthC  : MacroTileWidthY;</div><div class='add'>+	unsigned int MacroTileHeight		= is_plane1 ? MacroTileHeightC : MacroTileHeightY;</div><div class='add'>+	unsigned int PTEBufferSizeInRequests = is_plane1 ? mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_luma;</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: is_plane1 = %u\n", __func__, is_plane1);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: BytePerPixel = %u\n", __func__, BytePerPixel);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: BlockHeight256Bytes = %u\n", __func__, BlockHeight256Bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: BlockWidth256Bytes = %u\n", __func__, BlockWidth256Bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: MacroTileWidth = %u\n", __func__, MacroTileWidth);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: MacroTileHeight = %u\n", __func__, MacroTileHeight);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: PTEBufferSizeInRequests = %u\n", __func__, PTEBufferSizeInRequests);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: dpte_buffer_size_in_pte_reqs_luma = %u\n", __func__, mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_luma);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: dpte_buffer_size_in_pte_reqs_chroma = %u\n", __func__, mode_lib-&gt;ip.dpte_buffer_size_in_pte_reqs_chroma);</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: GPUVMMinPageSizeKBytes = %u\n", __func__, GPUVMMinPageSizeKBytes);</div><div class='add'>+#endif</div><div class='add'>+	unsigned int dummy_integer[21];</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.ViewportStationary = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.DCCEnable = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.NumberOfDPPs = 1;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.BlockHeight256Bytes = BlockHeight256Bytes;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.BlockWidth256Bytes = BlockWidth256Bytes;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.SourcePixelFormat = SourcePixelFormat;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.SurfaceTiling = SurfaceTiling;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.BytePerPixel = BytePerPixel;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.RotationAngle = ScanDirection;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.SwathWidth = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.ViewportHeight = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.ViewportXStart = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.ViewportYStart = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.GPUVMEnable = 1;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.GPUVMMaxPageTableLevels = 4;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = GPUVMMinPageSizeKBytes;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = PTEBufferSizeInRequests;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.Pitch = pitch;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.MacroTileWidth = MacroTileWidth;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.MacroTileHeight = MacroTileHeight;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.is_phantom = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.DCCMetaPitch = 0;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.mrq_present = 0;</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &amp;dummy_integer[1];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &amp;dummy_integer[2];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.dpte_row_width_ub = &amp;dummy_integer[3];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.dpte_row_height = dpte_row_height;</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.dpte_row_height_linear = &amp;dummy_integer[4];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &amp;dummy_integer[5];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &amp;dummy_integer[6];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &amp;dummy_integer[7];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.vmpg_width = &amp;dummy_integer[8];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.vmpg_height = &amp;dummy_integer[9];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &amp;dummy_integer[11];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &amp;dummy_integer[12];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.PTERequestSize = &amp;dummy_integer[13];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &amp;dummy_integer[14];</div><div class='add'>+</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.meta_row_bytes = &amp;dummy_integer[15];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.MetaRequestWidth = &amp;dummy_integer[16];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.MetaRequestHeight = &amp;dummy_integer[17];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.meta_row_width = &amp;dummy_integer[18];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.meta_row_height = &amp;dummy_integer[19];</div><div class='add'>+	mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &amp;dummy_integer[20];</div><div class='add'>+</div><div class='add'>+	// just supply with enough parameters to calculate dpte</div><div class='add'>+	CalculateVMAndRowBytes(&amp;mode_lib-&gt;scratch.calculate_vm_and_row_bytes_params);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML: %s: dpte_row_height = %u\n", __func__, *dpte_row_height);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_dual_plane(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	bool ret_val = false;</div><div class='add'>+</div><div class='add'>+	if ((source_format == dml2_420_12) || (source_format == dml2_420_8) || (source_format == dml2_420_10) || (source_format == dml2_rgbe_alpha))</div><div class='add'>+		ret_val = true;</div><div class='add'>+</div><div class='add'>+	return ret_val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dml_get_plane_idx(const struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int pipe_idx)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_idx = mode_lib-&gt;mp.pipe_plane[pipe_idx];</div><div class='add'>+	return plane_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rq_dlg_get_wm_regs(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_watermark_regs *wm_regs)</div><div class='add'>+{</div><div class='add'>+	double refclk_freq_in_mhz = (display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz &gt; 0) ? (double)display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz : mode_lib-&gt;soc.dchub_refclk_mhz;</div><div class='add'>+</div><div class='add'>+	wm_regs-&gt;fclk_pstate = (int unsigned)(mode_lib-&gt;mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;sr_enter = (int unsigned)(mode_lib-&gt;mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;sr_exit = (int unsigned)(mode_lib-&gt;mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;sr_enter_z8 = (int unsigned)(mode_lib-&gt;mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;sr_exit_z8 = (int unsigned)(mode_lib-&gt;mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;temp_read_or_ppt = (int unsigned)(mode_lib-&gt;mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;uclk_pstate = (int unsigned)(mode_lib-&gt;mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;urgent = (int unsigned)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;usr = (int unsigned)(mode_lib-&gt;mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;refcyc_per_trip_to_mem = (unsigned int)(mode_lib-&gt;mp.UrgentLatency * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib-&gt;mp.MetaTripToMemory * refclk_freq_in_mhz);</div><div class='add'>+	wm_regs-&gt;frac_urg_bw_flip = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidthImmediateFlip * 1000);</div><div class='add'>+	wm_regs-&gt;frac_urg_bw_nom = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidth * 1000);</div><div class='add'>+	wm_regs-&gt;frac_urg_bw_mall = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidthMALL * 1000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend)</div><div class='add'>+{</div><div class='add'>+	if (a == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return (math_log2_approx(a) - subtrahend);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_cursor_dlg_reg(struct dml2_cursor_dlg_regs *cursor_dlg_regs, const struct dml2_get_cursor_dlg_reg *p)</div><div class='add'>+{</div><div class='add'>+	int dst_x_offset = (int) ((p-&gt;cursor_x_position + (p-&gt;cursor_stereo_en == 0 ? 0 : math_max2(p-&gt;cursor_primary_offset, p-&gt;cursor_secondary_offset)) -</div><div class='add'>+						(p-&gt;cursor_hotspot_x * (p-&gt;cursor_2x_magnify == 0 ? 1 : 2))) * p-&gt;dlg_refclk_mhz / p-&gt;pixel_rate_mhz / p-&gt;hratio);</div><div class='add'>+	cursor_dlg_regs-&gt;dst_x_offset = (unsigned int) ((dst_x_offset &gt; 0) ? dst_x_offset : 0);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: cursor_x_position=%d\n", __func__, p-&gt;cursor_x_position);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: dlg_refclk_mhz=%f\n", __func__, p-&gt;dlg_refclk_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: pixel_rate_mhz=%f\n", __func__, p-&gt;pixel_rate_mhz);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: dst_x_offset=%d\n", __func__, dst_x_offset);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: dst_x_offset=%d (reg)\n", __func__, cursor_dlg_regs-&gt;dst_x_offset);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	cursor_dlg_regs-&gt;chunk_hdl_adjust = 3;</div><div class='add'>+	cursor_dlg_regs-&gt;dst_y_offset	 = 0;</div><div class='add'>+</div><div class='add'>+	cursor_dlg_regs-&gt;qos_level_fixed  = 8;</div><div class='add'>+	cursor_dlg_regs-&gt;qos_ramp_disable = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs,</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	const struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+	unsigned int pipe_idx)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_idx = dml_get_plane_idx(mode_lib, pipe_idx);</div><div class='add'>+	enum dml2_source_format_class source_format = display_cfg-&gt;plane_descriptors[plane_idx].pixel_format;</div><div class='add'>+	enum dml2_swizzle_mode sw_mode = display_cfg-&gt;plane_descriptors[plane_idx].surface.tiling;</div><div class='add'>+	bool dual_plane = is_dual_plane((enum dml2_source_format_class)(source_format));</div><div class='add'>+</div><div class='add'>+	unsigned int pixel_chunk_bytes = 0;</div><div class='add'>+	unsigned int min_pixel_chunk_bytes = 0;</div><div class='add'>+	unsigned int dpte_group_bytes = 0;</div><div class='add'>+	unsigned int mpte_group_bytes = 0;</div><div class='add'>+</div><div class='add'>+	unsigned int p1_pixel_chunk_bytes = 0;</div><div class='add'>+	unsigned int p1_min_pixel_chunk_bytes = 0;</div><div class='add'>+	unsigned int p1_dpte_group_bytes = 0;</div><div class='add'>+	unsigned int p1_mpte_group_bytes = 0;</div><div class='add'>+</div><div class='add'>+	unsigned int detile_buf_plane1_addr = 0;</div><div class='add'>+	unsigned int detile_buf_size_in_bytes;</div><div class='add'>+	double stored_swath_l_bytes;</div><div class='add'>+	double stored_swath_c_bytes;</div><div class='add'>+	bool is_phantom_pipe;</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: Calculation for pipe[%d] start\n", __func__, pipe_idx);</div><div class='add'>+</div><div class='add'>+	pixel_chunk_bytes = (unsigned int)(mode_lib-&gt;ip.pixel_chunk_size_kbytes * 1024);</div><div class='add'>+	min_pixel_chunk_bytes = (unsigned int)(mode_lib-&gt;ip.min_pixel_chunk_size_bytes);</div><div class='add'>+</div><div class='add'>+	if (pixel_chunk_bytes == 64 * 1024)</div><div class='add'>+		min_pixel_chunk_bytes = 0;</div><div class='add'>+</div><div class='add'>+	dpte_group_bytes = (unsigned int)(dml_get_dpte_group_size_in_bytes(mode_lib, pipe_idx));</div><div class='add'>+	mpte_group_bytes = (unsigned int)(dml_get_vm_group_size_in_bytes(mode_lib, pipe_idx));</div><div class='add'>+</div><div class='add'>+	p1_pixel_chunk_bytes = pixel_chunk_bytes;</div><div class='add'>+	p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes;</div><div class='add'>+	p1_dpte_group_bytes = dpte_group_bytes;</div><div class='add'>+	p1_mpte_group_bytes = mpte_group_bytes;</div><div class='add'>+</div><div class='add'>+	if (source_format == dml2_rgbe_alpha)</div><div class='add'>+		p1_pixel_chunk_bytes = (unsigned int)(mode_lib-&gt;ip.alpha_pixel_chunk_size_kbytes * 1024);</div><div class='add'>+</div><div class='add'>+	rq_regs-&gt;unbounded_request_enabled = dml_get_unbounded_request_enabled(mode_lib);</div><div class='add'>+	rq_regs-&gt;rq_regs_l.chunk_size = log_and_substract_if_non_zero(pixel_chunk_bytes, 10);</div><div class='add'>+	rq_regs-&gt;rq_regs_c.chunk_size = log_and_substract_if_non_zero(p1_pixel_chunk_bytes, 10);</div><div class='add'>+</div><div class='add'>+	if (min_pixel_chunk_bytes == 0)</div><div class='add'>+		rq_regs-&gt;rq_regs_l.min_chunk_size = 0;</div><div class='add'>+	else</div><div class='add'>+		rq_regs-&gt;rq_regs_l.min_chunk_size = log_and_substract_if_non_zero(min_pixel_chunk_bytes, 8 - 1);</div><div class='add'>+</div><div class='add'>+	if (p1_min_pixel_chunk_bytes == 0)</div><div class='add'>+		rq_regs-&gt;rq_regs_c.min_chunk_size = 0;</div><div class='add'>+	else</div><div class='add'>+		rq_regs-&gt;rq_regs_c.min_chunk_size = log_and_substract_if_non_zero(p1_min_pixel_chunk_bytes, 8 - 1);</div><div class='add'>+</div><div class='add'>+	rq_regs-&gt;rq_regs_l.dpte_group_size = log_and_substract_if_non_zero(dpte_group_bytes, 6);</div><div class='add'>+	rq_regs-&gt;rq_regs_l.mpte_group_size = log_and_substract_if_non_zero(mpte_group_bytes, 6);</div><div class='add'>+	rq_regs-&gt;rq_regs_c.dpte_group_size = log_and_substract_if_non_zero(p1_dpte_group_bytes, 6);</div><div class='add'>+	rq_regs-&gt;rq_regs_c.mpte_group_size = log_and_substract_if_non_zero(p1_mpte_group_bytes, 6);</div><div class='add'>+</div><div class='add'>+	detile_buf_size_in_bytes = (unsigned int)(dml_get_det_buffer_size_kbytes(mode_lib, pipe_idx) * 1024);</div><div class='add'>+</div><div class='add'>+	if (sw_mode == dml2_sw_linear &amp;&amp; display_cfg-&gt;gpuvm_enable) {</div><div class='add'>+		unsigned int p0_pte_row_height_linear = (unsigned int)(dml_get_dpte_row_height_linear_l(mode_lib, pipe_idx));</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: p0_pte_row_height_linear = %u\n", __func__, p0_pte_row_height_linear);</div><div class='add'>+#endif</div><div class='add'>+		DML_ASSERT(p0_pte_row_height_linear &gt;= 8);</div><div class='add'>+</div><div class='add'>+		rq_regs-&gt;rq_regs_l.pte_row_height_linear = math_log2_approx(p0_pte_row_height_linear) - 3;</div><div class='add'>+		if (dual_plane) {</div><div class='add'>+			unsigned int p1_pte_row_height_linear = (unsigned int)(dml_get_dpte_row_height_linear_c(mode_lib, pipe_idx));</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: p1_pte_row_height_linear = %u\n", __func__, p1_pte_row_height_linear);</div><div class='add'>+#endif</div><div class='add'>+			if (sw_mode == dml2_sw_linear) {</div><div class='add'>+				DML_ASSERT(p1_pte_row_height_linear &gt;= 8);</div><div class='add'>+			}</div><div class='add'>+			rq_regs-&gt;rq_regs_c.pte_row_height_linear = math_log2_approx(p1_pte_row_height_linear) - 3;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		rq_regs-&gt;rq_regs_l.pte_row_height_linear = 0;</div><div class='add'>+		rq_regs-&gt;rq_regs_c.pte_row_height_linear = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rq_regs-&gt;rq_regs_l.swath_height = log_and_substract_if_non_zero(dml_get_swath_height_l(mode_lib, pipe_idx), 0);</div><div class='add'>+	rq_regs-&gt;rq_regs_c.swath_height = log_and_substract_if_non_zero(dml_get_swath_height_c(mode_lib, pipe_idx), 0);</div><div class='add'>+</div><div class='add'>+	// FIXME_DCN4, programming guide has dGPU condition</div><div class='add'>+	if (pixel_chunk_bytes &gt;= 32 * 1024 || (dual_plane &amp;&amp; p1_pixel_chunk_bytes &gt;= 32 * 1024)) { //32kb</div><div class='add'>+		rq_regs-&gt;drq_expansion_mode = 0;</div><div class='add'>+	} else {</div><div class='add'>+		rq_regs-&gt;drq_expansion_mode = 2;</div><div class='add'>+	}</div><div class='add'>+	rq_regs-&gt;prq_expansion_mode = 1;</div><div class='add'>+	rq_regs-&gt;crq_expansion_mode = 1;</div><div class='add'>+	rq_regs-&gt;mrq_expansion_mode = 1;</div><div class='add'>+</div><div class='add'>+	stored_swath_l_bytes = dml_get_det_stored_buffer_size_l_bytes(mode_lib, pipe_idx);</div><div class='add'>+	stored_swath_c_bytes = dml_get_det_stored_buffer_size_c_bytes(mode_lib, pipe_idx);</div><div class='add'>+	is_phantom_pipe = dml_get_is_phantom_pipe(display_cfg, mode_lib, pipe_idx);</div><div class='add'>+</div><div class='add'>+	// Note: detile_buf_plane1_addr is in unit of 1KB</div><div class='add'>+	if (dual_plane) {</div><div class='add'>+		if (is_phantom_pipe) {</div><div class='add'>+			detile_buf_plane1_addr = (unsigned int)((1024.0 * 1024.0) / 2.0 / 1024.0); // half to chroma</div><div class='add'>+		} else {</div><div class='add'>+			if (stored_swath_l_bytes / stored_swath_c_bytes &lt;= 1.5) {</div><div class='add'>+				detile_buf_plane1_addr = (unsigned int)(detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML_DLG: %s: detile_buf_plane1_addr = %d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr);</div><div class='add'>+#endif</div><div class='add'>+			} else {</div><div class='add'>+				detile_buf_plane1_addr = (unsigned int)(dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0); // 2/3 to luma</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+				DML_LOG_VERBOSE("DML_DLG: %s: detile_buf_plane1_addr = %d (1/3 chroma)\n", __func__, detile_buf_plane1_addr);</div><div class='add'>+#endif</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	rq_regs-&gt;plane1_base_address = detile_buf_plane1_addr;</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG: %s: is_phantom_pipe = %d\n", __func__, is_phantom_pipe);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG: %s: stored_swath_l_bytes = %f\n", __func__, stored_swath_l_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG: %s: stored_swath_c_bytes = %f\n", __func__, stored_swath_c_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG: %s: detile_buf_size_in_bytes = %d\n", __func__, detile_buf_size_in_bytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG: %s: detile_buf_plane1_addr = %d\n", __func__, detile_buf_plane1_addr);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG: %s: plane1_base_address = %d\n", __func__, rq_regs-&gt;plane1_base_address);</div><div class='add'>+#endif</div><div class='add'>+	//DML_LOG_VERBOSE_rq_regs_st(rq_regs);</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: Calculation for pipe[%d] done\n", __func__, pipe_idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rq_dlg_get_dlg_reg(</div><div class='add'>+	struct dml2_core_internal_scratch *s,</div><div class='add'>+	struct dml2_display_dlg_regs *disp_dlg_regs,</div><div class='add'>+	struct dml2_display_ttu_regs *disp_ttu_regs,</div><div class='add'>+	const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	const struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+	const unsigned int pipe_idx)</div><div class='add'>+{</div><div class='add'>+	struct dml2_core_shared_rq_dlg_get_dlg_reg_locals *l = &amp;s-&gt;rq_dlg_get_dlg_reg_locals;</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_core_shared_rq_dlg_get_dlg_reg_locals));</div><div class='add'>+</div><div class='add'>+	DML_LOG_VERBOSE("DML_DLG::%s: Calculation for pipe_idx=%d\n", __func__, pipe_idx);</div><div class='add'>+</div><div class='add'>+	l-&gt;plane_idx = dml_get_plane_idx(mode_lib, pipe_idx);</div><div class='add'>+	DML_ASSERT(l-&gt;plane_idx &lt; DML2_MAX_PLANES);</div><div class='add'>+</div><div class='add'>+	l-&gt;source_format = dml2_444_8;</div><div class='add'>+	l-&gt;odm_mode = dml2_odm_mode_bypass;</div><div class='add'>+	l-&gt;dual_plane = false;</div><div class='add'>+	l-&gt;htotal = 0;</div><div class='add'>+	l-&gt;hactive = 0;</div><div class='add'>+	l-&gt;hblank_end = 0;</div><div class='add'>+	l-&gt;vblank_end = 0;</div><div class='add'>+	l-&gt;interlaced = false;</div><div class='add'>+	l-&gt;pclk_freq_in_mhz = 0.0;</div><div class='add'>+	l-&gt;refclk_freq_in_mhz = (display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz &gt; 0) ? (double)display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz : mode_lib-&gt;soc.dchub_refclk_mhz;</div><div class='add'>+	l-&gt;ref_freq_to_pix_freq = 0.0;</div><div class='add'>+</div><div class='add'>+	if (l-&gt;plane_idx &lt; DML2_MAX_PLANES) {</div><div class='add'>+</div><div class='add'>+		l-&gt;timing = &amp;display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[l-&gt;plane_idx].stream_index].timing;</div><div class='add'>+		l-&gt;source_format = display_cfg-&gt;plane_descriptors[l-&gt;plane_idx].pixel_format;</div><div class='add'>+		l-&gt;odm_mode = mode_lib-&gt;mp.ODMMode[l-&gt;plane_idx];</div><div class='add'>+</div><div class='add'>+		l-&gt;dual_plane = is_dual_plane(l-&gt;source_format);</div><div class='add'>+</div><div class='add'>+		l-&gt;htotal = l-&gt;timing-&gt;h_total;</div><div class='add'>+		l-&gt;hactive = l-&gt;timing-&gt;h_active;</div><div class='add'>+		l-&gt;hblank_end = l-&gt;timing-&gt;h_blank_end;</div><div class='add'>+		l-&gt;vblank_end = l-&gt;timing-&gt;v_blank_end;</div><div class='add'>+		l-&gt;interlaced = l-&gt;timing-&gt;interlaced;</div><div class='add'>+		l-&gt;pclk_freq_in_mhz = (double)l-&gt;timing-&gt;pixel_clock_khz / 1000;</div><div class='add'>+		l-&gt;ref_freq_to_pix_freq = l-&gt;refclk_freq_in_mhz / l-&gt;pclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG::%s: plane_idx = %d\n", __func__, l-&gt;plane_idx);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: htotal = %d\n", __func__, l-&gt;htotal);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, l-&gt;refclk_freq_in_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dlg_ref_clk_mhz = %3.2f\n", __func__, display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: soc.refclk_mhz = %d\n", __func__, mode_lib-&gt;soc.dchub_refclk_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, l-&gt;pclk_freq_in_mhz);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, l-&gt;ref_freq_to_pix_freq);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: interlaced = %d\n", __func__, l-&gt;interlaced);</div><div class='add'>+</div><div class='add'>+		DML_ASSERT(l-&gt;refclk_freq_in_mhz != 0);</div><div class='add'>+		DML_ASSERT(l-&gt;pclk_freq_in_mhz != 0);</div><div class='add'>+		DML_ASSERT(l-&gt;ref_freq_to_pix_freq &lt; 4.0);</div><div class='add'>+</div><div class='add'>+		// Need to figure out which side of odm combine we're in</div><div class='add'>+		// Assume the pipe instance under the same plane is in order</div><div class='add'>+</div><div class='add'>+		if (l-&gt;odm_mode == dml2_odm_mode_bypass) {</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_h_blank_end = (unsigned int)((double)l-&gt;hblank_end * l-&gt;ref_freq_to_pix_freq);</div><div class='add'>+		} else if (l-&gt;odm_mode == dml2_odm_mode_combine_2to1 || l-&gt;odm_mode == dml2_odm_mode_combine_3to1 || l-&gt;odm_mode == dml2_odm_mode_combine_4to1) {</div><div class='add'>+			// find out how many pipe are in this plane</div><div class='add'>+			l-&gt;num_active_pipes = mode_lib-&gt;mp.num_active_pipes;</div><div class='add'>+			l-&gt;first_pipe_idx_in_plane = DML2_MAX_PLANES;</div><div class='add'>+			l-&gt;pipe_idx_in_combine = 0; // pipe index within the plane</div><div class='add'>+			l-&gt;odm_combine_factor = 2;</div><div class='add'>+</div><div class='add'>+			if (l-&gt;odm_mode == dml2_odm_mode_combine_3to1)</div><div class='add'>+				l-&gt;odm_combine_factor = 3;</div><div class='add'>+			else if (l-&gt;odm_mode == dml2_odm_mode_combine_4to1)</div><div class='add'>+				l-&gt;odm_combine_factor = 4;</div><div class='add'>+</div><div class='add'>+			for (unsigned int i = 0; i &lt; l-&gt;num_active_pipes; i++) {</div><div class='add'>+				if (dml_get_plane_idx(mode_lib, i) == l-&gt;plane_idx) {</div><div class='add'>+					if (i &lt; l-&gt;first_pipe_idx_in_plane) {</div><div class='add'>+						l-&gt;first_pipe_idx_in_plane = i;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			l-&gt;pipe_idx_in_combine = pipe_idx - l-&gt;first_pipe_idx_in_plane; // DML assumes the pipes in the same plane will have continuous indexing (i.e. plane 0 use pipe 0, 1, and plane 1 uses pipe 2, 3, etc.)</div><div class='add'>+</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_h_blank_end = (unsigned int)(((double)l-&gt;hblank_end + (double)l-&gt;pipe_idx_in_combine * (double)l-&gt;hactive / (double)l-&gt;odm_combine_factor) * l-&gt;ref_freq_to_pix_freq);</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: pipe_idx = %d\n", __func__, pipe_idx);</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: first_pipe_idx_in_plane = %d\n", __func__, l-&gt;first_pipe_idx_in_plane);</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: pipe_idx_in_combine = %d\n", __func__, l-&gt;pipe_idx_in_combine);</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: odm_combine_factor = %d\n", __func__, l-&gt;odm_combine_factor);</div><div class='add'>+		}</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: refcyc_h_blank_end = %d\n", __func__, disp_dlg_regs-&gt;refcyc_h_blank_end);</div><div class='add'>+</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_h_blank_end &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;ref_freq_to_pix_freq = (unsigned int)(l-&gt;ref_freq_to_pix_freq * math_pow(2, 19));</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_htotal = (unsigned int)(l-&gt;ref_freq_to_pix_freq * (double)l-&gt;htotal * math_pow(2, 8));</div><div class='add'>+		disp_dlg_regs-&gt;dlg_vblank_end = l-&gt;interlaced ? (l-&gt;vblank_end / 2) : l-&gt;vblank_end; // 15 bits</div><div class='add'>+</div><div class='add'>+		l-&gt;min_ttu_vblank = mode_lib-&gt;mp.MinTTUVBlank[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;min_dst_y_next_start = (unsigned int)(mode_lib-&gt;mp.MIN_DST_Y_NEXT_START[mode_lib-&gt;mp.pipe_plane[pipe_idx]]);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: min_ttu_vblank (us) = %3.2f\n", __func__, l-&gt;min_ttu_vblank);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: min_dst_y_next_start = %d\n", __func__, l-&gt;min_dst_y_next_start);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", __func__, l-&gt;ref_freq_to_pix_freq);</div><div class='add'>+</div><div class='add'>+		l-&gt;vready_after_vcount0 = (unsigned int)(mode_lib-&gt;mp.VREADY_AT_OR_AFTER_VSYNC[mode_lib-&gt;mp.pipe_plane[pipe_idx]]);</div><div class='add'>+		disp_dlg_regs-&gt;vready_after_vcount0 = l-&gt;vready_after_vcount0;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs-&gt;vready_after_vcount0);</div><div class='add'>+</div><div class='add'>+		l-&gt;dst_x_after_scaler = (unsigned int)(mode_lib-&gt;mp.DSTXAfterScaler[mode_lib-&gt;mp.pipe_plane[pipe_idx]]);</div><div class='add'>+		l-&gt;dst_y_after_scaler = (unsigned int)(mode_lib-&gt;mp.DSTYAfterScaler[mode_lib-&gt;mp.pipe_plane[pipe_idx]]);</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_x_after_scaler = %d\n", __func__, l-&gt;dst_x_after_scaler);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_y_after_scaler = %d\n", __func__, l-&gt;dst_y_after_scaler);</div><div class='add'>+</div><div class='add'>+		l-&gt;dst_y_prefetch = mode_lib-&gt;mp.dst_y_prefetch[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;dst_y_per_vm_vblank = mode_lib-&gt;mp.dst_y_per_vm_vblank[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;dst_y_per_row_vblank = mode_lib-&gt;mp.dst_y_per_row_vblank[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;dst_y_per_vm_flip = mode_lib-&gt;mp.dst_y_per_vm_flip[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;dst_y_per_row_flip = mode_lib-&gt;mp.dst_y_per_row_flip[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, l-&gt;dst_y_prefetch);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, l-&gt;dst_y_per_vm_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, l-&gt;dst_y_per_row_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, l-&gt;dst_y_per_vm_vblank);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, l-&gt;dst_y_per_row_vblank);</div><div class='add'>+</div><div class='add'>+		if (l-&gt;dst_y_prefetch &gt; 0 &amp;&amp; l-&gt;dst_y_per_vm_vblank &gt; 0 &amp;&amp; l-&gt;dst_y_per_row_vblank &gt; 0) {</div><div class='add'>+			DML_ASSERT(l-&gt;dst_y_prefetch &gt; (l-&gt;dst_y_per_vm_vblank + l-&gt;dst_y_per_row_vblank));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		l-&gt;vratio_pre_l = mode_lib-&gt;mp.VRatioPrefetchY[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;vratio_pre_c = mode_lib-&gt;mp.VRatioPrefetchC[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, l-&gt;vratio_pre_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, l-&gt;vratio_pre_c);</div><div class='add'>+</div><div class='add'>+		// Active</div><div class='add'>+		l-&gt;refcyc_per_line_delivery_pre_l = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeLumaPrefetch[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_line_delivery_l = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeLuma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, l-&gt;refcyc_per_line_delivery_pre_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", __func__, l-&gt;refcyc_per_line_delivery_l);</div><div class='add'>+</div><div class='add'>+		l-&gt;refcyc_per_line_delivery_pre_c = 0.0;</div><div class='add'>+		l-&gt;refcyc_per_line_delivery_c = 0.0;</div><div class='add'>+</div><div class='add'>+		if (l-&gt;dual_plane) {</div><div class='add'>+			l-&gt;refcyc_per_line_delivery_pre_c = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeChromaPrefetch[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+			l-&gt;refcyc_per_line_delivery_c = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeChroma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, l-&gt;refcyc_per_line_delivery_pre_c);</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", __func__, l-&gt;refcyc_per_line_delivery_c);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_vm_dmdata = (unsigned int)(mode_lib-&gt;mp.Tdmdl_vm[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz);</div><div class='add'>+		disp_dlg_regs-&gt;dmdata_dl_delta = (unsigned int)(mode_lib-&gt;mp.Tdmdl[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz);</div><div class='add'>+</div><div class='add'>+		l-&gt;refcyc_per_req_delivery_pre_l = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeLumaPrefetch[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_req_delivery_l = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeLuma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, l-&gt;refcyc_per_req_delivery_pre_l);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", __func__, l-&gt;refcyc_per_req_delivery_l);</div><div class='add'>+</div><div class='add'>+		l-&gt;refcyc_per_req_delivery_pre_c = 0.0;</div><div class='add'>+		l-&gt;refcyc_per_req_delivery_c = 0.0;</div><div class='add'>+		if (l-&gt;dual_plane) {</div><div class='add'>+			l-&gt;refcyc_per_req_delivery_pre_c = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeChromaPrefetch[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+			l-&gt;refcyc_per_req_delivery_c = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeChroma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, l-&gt;refcyc_per_req_delivery_pre_c);</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", __func__, l-&gt;refcyc_per_req_delivery_c);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// TTU - Cursor</div><div class='add'>+		DML_ASSERT(display_cfg-&gt;plane_descriptors[l-&gt;plane_idx].cursor.num_cursors &lt;= 1);</div><div class='add'>+</div><div class='add'>+		// Assign to register structures</div><div class='add'>+		disp_dlg_regs-&gt;min_dst_y_next_start = (unsigned int)((double)l-&gt;min_dst_y_next_start * math_pow(2, 2));</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;min_dst_y_next_start &lt; (unsigned int)math_pow(2, 18));</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_after_scaler = l-&gt;dst_y_after_scaler; // in terms of line</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_x_after_scaler = (unsigned int)((double)l-&gt;dst_x_after_scaler * l-&gt;ref_freq_to_pix_freq); // in terms of refclk</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_prefetch = (unsigned int)(l-&gt;dst_y_prefetch * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_vm_vblank = (unsigned int)(l-&gt;dst_y_per_vm_vblank * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_row_vblank = (unsigned int)(l-&gt;dst_y_per_row_vblank * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_vm_flip = (unsigned int)(l-&gt;dst_y_per_vm_flip * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_row_flip = (unsigned int)(l-&gt;dst_y_per_row_flip * math_pow(2, 2));</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;vratio_prefetch = (unsigned int)(l-&gt;vratio_pre_l * math_pow(2, 19));</div><div class='add'>+		disp_dlg_regs-&gt;vratio_prefetch_c = (unsigned int)(l-&gt;vratio_pre_c * math_pow(2, 19));</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_vm_vblank);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_row_vblank);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_vm_flip);</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_row_flip);</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_vm_group_vblank = (unsigned int)(mode_lib-&gt;mp.TimePerVMGroupVBlank[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_vm_group_flip = (unsigned int)(mode_lib-&gt;mp.TimePerVMGroupFlip[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_vm_req_vblank = (unsigned int)(mode_lib-&gt;mp.TimePerVMRequestVBlank[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz * math_pow(2, 10));</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_vm_req_flip = (unsigned int)(mode_lib-&gt;mp.TimePerVMRequestFlip[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz * math_pow(2, 10));</div><div class='add'>+</div><div class='add'>+		l-&gt;dst_y_per_pte_row_nom_l = mode_lib-&gt;mp.DST_Y_PER_PTE_ROW_NOM_L[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;dst_y_per_pte_row_nom_c = mode_lib-&gt;mp.DST_Y_PER_PTE_ROW_NOM_C[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;refcyc_per_pte_group_nom_l = mode_lib-&gt;mp.time_per_pte_group_nom_luma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_pte_group_nom_c = mode_lib-&gt;mp.time_per_pte_group_nom_chroma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_pte_group_vblank_l = mode_lib-&gt;mp.time_per_pte_group_vblank_luma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_pte_group_vblank_c = mode_lib-&gt;mp.time_per_pte_group_vblank_chroma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_pte_group_flip_l = mode_lib-&gt;mp.time_per_pte_group_flip_luma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_pte_group_flip_c = mode_lib-&gt;mp.time_per_pte_group_flip_chroma[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_tdlut_group = mode_lib-&gt;mp.time_per_tdlut_group[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_pte_row_nom_l = (unsigned int)(l-&gt;dst_y_per_pte_row_nom_l * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_pte_row_nom_c = (unsigned int)(l-&gt;dst_y_per_pte_row_nom_c * math_pow(2, 2));</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_pte_group_nom_l = (unsigned int)(l-&gt;refcyc_per_pte_group_nom_l);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_pte_group_nom_c = (unsigned int)(l-&gt;refcyc_per_pte_group_nom_c);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_pte_group_vblank_l = (unsigned int)(l-&gt;refcyc_per_pte_group_vblank_l);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_pte_group_vblank_c = (unsigned int)(l-&gt;refcyc_per_pte_group_vblank_c);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_pte_group_flip_l = (unsigned int)(l-&gt;refcyc_per_pte_group_flip_l);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_pte_group_flip_c = (unsigned int)(l-&gt;refcyc_per_pte_group_flip_c);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_line_delivery_pre_l = (unsigned int)math_floor2(l-&gt;refcyc_per_line_delivery_pre_l, 1);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_line_delivery_l = (unsigned int)math_floor2(l-&gt;refcyc_per_line_delivery_l, 1);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_line_delivery_pre_c = (unsigned int)math_floor2(l-&gt;refcyc_per_line_delivery_pre_c, 1);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_line_delivery_c = (unsigned int)math_floor2(l-&gt;refcyc_per_line_delivery_c, 1);</div><div class='add'>+</div><div class='add'>+		l-&gt;dst_y_per_meta_row_nom_l = mode_lib-&gt;mp.DST_Y_PER_META_ROW_NOM_L[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;dst_y_per_meta_row_nom_c = mode_lib-&gt;mp.DST_Y_PER_META_ROW_NOM_C[mode_lib-&gt;mp.pipe_plane[pipe_idx]];</div><div class='add'>+		l-&gt;refcyc_per_meta_chunk_nom_l = mode_lib-&gt;mp.TimePerMetaChunkNominal[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_meta_chunk_nom_c = mode_lib-&gt;mp.TimePerChromaMetaChunkNominal[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_meta_chunk_vblank_l = mode_lib-&gt;mp.TimePerMetaChunkVBlank[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_meta_chunk_vblank_c = mode_lib-&gt;mp.TimePerChromaMetaChunkVBlank[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_meta_chunk_flip_l = mode_lib-&gt;mp.TimePerMetaChunkFlip[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+		l-&gt;refcyc_per_meta_chunk_flip_c = mode_lib-&gt;mp.TimePerChromaMetaChunkFlip[mode_lib-&gt;mp.pipe_plane[pipe_idx]] * l-&gt;refclk_freq_in_mhz;</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_meta_row_nom_l = (unsigned int)(l-&gt;dst_y_per_meta_row_nom_l * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_per_meta_row_nom_c = (unsigned int)(l-&gt;dst_y_per_meta_row_nom_c * math_pow(2, 2));</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_meta_chunk_nom_l = (unsigned int)(l-&gt;refcyc_per_meta_chunk_nom_l);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_meta_chunk_nom_c = (unsigned int)(l-&gt;refcyc_per_meta_chunk_nom_c);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_meta_chunk_vblank_l = (unsigned int)(l-&gt;refcyc_per_meta_chunk_vblank_l);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_meta_chunk_vblank_c = (unsigned int)(l-&gt;refcyc_per_meta_chunk_vblank_c);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_meta_chunk_flip_l = (unsigned int)(l-&gt;refcyc_per_meta_chunk_flip_l);</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_meta_chunk_flip_c = (unsigned int)(l-&gt;refcyc_per_meta_chunk_flip_c);</div><div class='add'>+</div><div class='add'>+		disp_dlg_regs-&gt;refcyc_per_tdlut_group = (unsigned int)(l-&gt;refcyc_per_tdlut_group);</div><div class='add'>+		disp_dlg_regs-&gt;dst_y_delta_drq_limit = 0x7fff; // off</div><div class='add'>+</div><div class='add'>+		disp_ttu_regs-&gt;refcyc_per_req_delivery_pre_l = (unsigned int)(l-&gt;refcyc_per_req_delivery_pre_l * math_pow(2, 10));</div><div class='add'>+		disp_ttu_regs-&gt;refcyc_per_req_delivery_l = (unsigned int)(l-&gt;refcyc_per_req_delivery_l * math_pow(2, 10));</div><div class='add'>+		disp_ttu_regs-&gt;refcyc_per_req_delivery_pre_c = (unsigned int)(l-&gt;refcyc_per_req_delivery_pre_c * math_pow(2, 10));</div><div class='add'>+		disp_ttu_regs-&gt;refcyc_per_req_delivery_c = (unsigned int)(l-&gt;refcyc_per_req_delivery_c * math_pow(2, 10));</div><div class='add'>+		disp_ttu_regs-&gt;qos_level_low_wm = 0;</div><div class='add'>+</div><div class='add'>+		disp_ttu_regs-&gt;qos_level_high_wm = (unsigned int)(4.0 * (double)l-&gt;htotal * l-&gt;ref_freq_to_pix_freq);</div><div class='add'>+</div><div class='add'>+		disp_ttu_regs-&gt;qos_level_flip = 14;</div><div class='add'>+		disp_ttu_regs-&gt;qos_level_fixed_l = 8;</div><div class='add'>+		disp_ttu_regs-&gt;qos_level_fixed_c = 8;</div><div class='add'>+		disp_ttu_regs-&gt;qos_ramp_disable_l = 0;</div><div class='add'>+		disp_ttu_regs-&gt;qos_ramp_disable_c = 0;</div><div class='add'>+		disp_ttu_regs-&gt;min_ttu_vblank = (unsigned int)(l-&gt;min_ttu_vblank * l-&gt;refclk_freq_in_mhz);</div><div class='add'>+</div><div class='add'>+		// CHECK for HW registers' range, DML_ASSERT or clamp</div><div class='add'>+		DML_ASSERT(l-&gt;refcyc_per_req_delivery_pre_l &lt; math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(l-&gt;refcyc_per_req_delivery_l &lt; math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(l-&gt;refcyc_per_req_delivery_pre_c &lt; math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(l-&gt;refcyc_per_req_delivery_c &lt; math_pow(2, 13));</div><div class='add'>+		if (disp_dlg_regs-&gt;refcyc_per_vm_group_vblank &gt;= (unsigned int)math_pow(2, 23))</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_per_vm_group_vblank = (unsigned int)(math_pow(2, 23) - 1);</div><div class='add'>+</div><div class='add'>+		if (disp_dlg_regs-&gt;refcyc_per_vm_group_flip &gt;= (unsigned int)math_pow(2, 23))</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_per_vm_group_flip = (unsigned int)(math_pow(2, 23) - 1);</div><div class='add'>+</div><div class='add'>+		if (disp_dlg_regs-&gt;refcyc_per_vm_req_vblank &gt;= (unsigned int)math_pow(2, 23))</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_per_vm_req_vblank = (unsigned int)(math_pow(2, 23) - 1);</div><div class='add'>+</div><div class='add'>+		if (disp_dlg_regs-&gt;refcyc_per_vm_req_flip &gt;= (unsigned int)math_pow(2, 23))</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_per_vm_req_flip = (unsigned int)(math_pow(2, 23) - 1);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;dst_y_after_scaler &lt; (unsigned int)8);</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_x_after_scaler &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+</div><div class='add'>+		if (disp_dlg_regs-&gt;dst_y_per_pte_row_nom_l &gt;= (unsigned int)math_pow(2, 17)) {</div><div class='add'>+			DML_LOG_VERBOSE("DML_DLG: %s: Warning DST_Y_PER_PTE_ROW_NOM_L %u &gt; register max U15.2 %u, clamp to max\n", __func__, disp_dlg_regs-&gt;dst_y_per_pte_row_nom_l, (unsigned int)math_pow(2, 17) - 1);</div><div class='add'>+			l-&gt;dst_y_per_pte_row_nom_l = (unsigned int)math_pow(2, 17) - 1;</div><div class='add'>+		}</div><div class='add'>+		if (l-&gt;dual_plane) {</div><div class='add'>+			if (disp_dlg_regs-&gt;dst_y_per_pte_row_nom_c &gt;= (unsigned int)math_pow(2, 17)) {</div><div class='add'>+				DML_LOG_VERBOSE("DML_DLG: %s: Warning DST_Y_PER_PTE_ROW_NOM_C %u &gt; register max U15.2 %u, clamp to max\n", __func__, disp_dlg_regs-&gt;dst_y_per_pte_row_nom_c, (unsigned int)math_pow(2, 17) - 1);</div><div class='add'>+				l-&gt;dst_y_per_pte_row_nom_c = (unsigned int)math_pow(2, 17) - 1;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (disp_dlg_regs-&gt;refcyc_per_pte_group_nom_l &gt;= (unsigned int)math_pow(2, 23))</div><div class='add'>+			disp_dlg_regs-&gt;refcyc_per_pte_group_nom_l = (unsigned int)(math_pow(2, 23) - 1);</div><div class='add'>+		if (l-&gt;dual_plane) {</div><div class='add'>+			if (disp_dlg_regs-&gt;refcyc_per_pte_group_nom_c &gt;= (unsigned int)math_pow(2, 23))</div><div class='add'>+				disp_dlg_regs-&gt;refcyc_per_pte_group_nom_c = (unsigned int)(math_pow(2, 23) - 1);</div><div class='add'>+		}</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_per_pte_group_vblank_l &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+		if (l-&gt;dual_plane) {</div><div class='add'>+			DML_ASSERT(disp_dlg_regs-&gt;refcyc_per_pte_group_vblank_c &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_per_line_delivery_pre_l &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_per_line_delivery_l &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_per_line_delivery_pre_c &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(disp_dlg_regs-&gt;refcyc_per_line_delivery_c &lt; (unsigned int)math_pow(2, 13));</div><div class='add'>+		DML_ASSERT(disp_ttu_regs-&gt;qos_level_low_wm &lt; (unsigned int)math_pow(2, 14));</div><div class='add'>+		DML_ASSERT(disp_ttu_regs-&gt;qos_level_high_wm &lt; (unsigned int)math_pow(2, 14));</div><div class='add'>+		DML_ASSERT(disp_ttu_regs-&gt;min_ttu_vblank &lt; (unsigned int)math_pow(2, 24));</div><div class='add'>+</div><div class='add'>+		DML_LOG_VERBOSE("DML_DLG::%s: Calculation for pipe[%d] done\n", __func__, pipe_idx);</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rq_dlg_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_arb_regs *arb_param)</div><div class='add'>+{</div><div class='add'>+	double refclk_freq_in_mhz = (display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz &gt; 0) ? (double)display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz : mode_lib-&gt;soc.dchub_refclk_mhz;</div><div class='add'>+</div><div class='add'>+	arb_param-&gt;max_req_outstanding = mode_lib-&gt;soc.max_outstanding_reqs;</div><div class='add'>+	arb_param-&gt;min_req_outstanding = mode_lib-&gt;soc.max_outstanding_reqs; // turn off the sat level feature if this set to max</div><div class='add'>+	arb_param-&gt;sdpif_request_rate_limit = (3 * mode_lib-&gt;ip.words_per_channel * mode_lib-&gt;soc.clk_table.dram_config.channel_count) / 4;</div><div class='add'>+	arb_param-&gt;sdpif_request_rate_limit = arb_param-&gt;sdpif_request_rate_limit &lt; 96 ? 96 : arb_param-&gt;sdpif_request_rate_limit;</div><div class='add'>+	arb_param-&gt;sat_level_us = 60;</div><div class='add'>+	arb_param-&gt;hvm_max_qos_commit_threshold = 0xf;</div><div class='add'>+	arb_param-&gt;hvm_min_req_outstand_commit_threshold = 0xa;</div><div class='add'>+	arb_param-&gt;compbuf_reserved_space_kbytes = dml_get_compbuf_reserved_space_64b(mode_lib) * 64 / 1024;</div><div class='add'>+	arb_param-&gt;compbuf_size = mode_lib-&gt;mp.CompressedBufferSizeInkByte / mode_lib-&gt;ip.compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	arb_param-&gt;allow_sdpif_rate_limit_when_cstate_req = dml_get_hw_debug5(mode_lib);</div><div class='add'>+	arb_param-&gt;dcfclk_deep_sleep_hysteresis = dml_get_dcfclk_deep_sleep_hysteresis(mode_lib);</div><div class='add'>+	arb_param-&gt;pstate_stall_threshold = (unsigned int)(mode_lib-&gt;ip_caps.fams2.max_allow_delay_us * refclk_freq_in_mhz);</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: max_req_outstanding = %d\n", __func__, arb_param-&gt;max_req_outstanding);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: sdpif_request_rate_limit = %d\n", __func__, arb_param-&gt;sdpif_request_rate_limit);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: compbuf_reserved_space_kbytes = %d\n", __func__, arb_param-&gt;compbuf_reserved_space_kbytes);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: allow_sdpif_rate_limit_when_cstate_req = %d\n", __func__, arb_param-&gt;allow_sdpif_rate_limit_when_cstate_req);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: dcfclk_deep_sleep_hysteresis = %d\n", __func__, arb_param-&gt;dcfclk_deep_sleep_hysteresis);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_watermark_regs *out)</div><div class='add'>+{</div><div class='add'>+	rq_dlg_get_wm_regs(display_cfg, mode_lib, out);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_arb_regs *out)</div><div class='add'>+{</div><div class='add'>+	rq_dlg_get_arb_params(display_cfg, mode_lib, out);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_pipe_regs(const struct dml2_display_cfg *display_cfg,</div><div class='add'>+	struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set *out, int pipe_index)</div><div class='add'>+{</div><div class='add'>+	rq_dlg_get_rq_reg(&amp;out-&gt;rq_regs, display_cfg, mode_lib, pipe_index);</div><div class='add'>+	rq_dlg_get_dlg_reg(&amp;mode_lib-&gt;scratch, &amp;out-&gt;dlg_regs, &amp;out-&gt;ttu_regs, display_cfg, mode_lib, pipe_index);</div><div class='add'>+	out-&gt;det_size = dml_get_det_buffer_size_kbytes(mode_lib, pipe_index) / mode_lib-&gt;ip.config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_global_sync_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, union dml2_global_sync_programming *out, int pipe_index)</div><div class='add'>+{</div><div class='add'>+	out-&gt;dcn4x.vready_offset_pixels = dml_get_vready_offset(mode_lib, pipe_index);</div><div class='add'>+	out-&gt;dcn4x.vstartup_lines = dml_get_vstartup_calculated(mode_lib, pipe_index);</div><div class='add'>+	out-&gt;dcn4x.vupdate_offset_pixels = dml_get_vupdate_offset(mode_lib, pipe_index);</div><div class='add'>+	out-&gt;dcn4x.vupdate_vupdate_width_pixels = dml_get_vupdate_width(mode_lib, pipe_index);</div><div class='add'>+	out-&gt;dcn4x.pstate_keepout_start_lines = dml_get_pstate_keepout_dst_lines(mode_lib, pipe_index);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_stream_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_per_stream_programming *out, int pipe_index)</div><div class='add'>+{</div><div class='add'>+	dml2_core_calcs_get_global_sync_programming(mode_lib, &amp;out-&gt;global_sync, pipe_index);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_global_fams2_programming(const struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+		const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+		struct dmub_cmd_fams2_global_config *fams2_global_config)</div><div class='add'>+{</div><div class='add'>+	fams2_global_config-&gt;features.bits.enable = display_cfg-&gt;stage3.fams2_required;</div><div class='add'>+</div><div class='add'>+	if (fams2_global_config-&gt;features.bits.enable) {</div><div class='add'>+		fams2_global_config-&gt;features.bits.enable_stall_recovery = true;</div><div class='add'>+		fams2_global_config-&gt;features.bits.allow_delay_check_mode = FAMS2_ALLOW_DELAY_CHECK_FROM_START;</div><div class='add'>+</div><div class='add'>+		fams2_global_config-&gt;max_allow_delay_us = mode_lib-&gt;ip_caps.fams2.max_allow_delay_us;</div><div class='add'>+		fams2_global_config-&gt;lock_wait_time_us = mode_lib-&gt;ip_caps.fams2.lock_timeout_us;</div><div class='add'>+		fams2_global_config-&gt;recovery_timeout_us = mode_lib-&gt;ip_caps.fams2.recovery_timeout_us;</div><div class='add'>+		fams2_global_config-&gt;hwfq_flip_programming_delay_us = mode_lib-&gt;ip_caps.fams2.flip_programming_delay_us;</div><div class='add'>+</div><div class='add'>+		fams2_global_config-&gt;num_streams = display_cfg-&gt;display_config.num_streams;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_internal_display_mode_lib *mode_lib,</div><div class='add'>+		const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+		union dmub_cmd_fams2_config *fams2_base_programming,</div><div class='add'>+		union dmub_cmd_fams2_config *fams2_sub_programming,</div><div class='add'>+		enum dml2_pstate_method pstate_method,</div><div class='add'>+		int plane_index)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor = &amp;display_cfg-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor = &amp;display_cfg-&gt;display_config.stream_descriptors[plane_descriptor-&gt;stream_index];</div><div class='add'>+	const struct dml2_pstate_meta *stream_pstate_meta = &amp;display_cfg-&gt;stage3.stream_pstate_meta[plane_descriptor-&gt;stream_index];</div><div class='add'>+</div><div class='add'>+	struct dmub_fams2_cmd_stream_static_base_state *base_programming = &amp;fams2_base_programming-&gt;stream_v1.base;</div><div class='add'>+	union dmub_fams2_cmd_stream_static_sub_state *sub_programming = &amp;fams2_sub_programming-&gt;stream_v1.sub_state;</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (display_cfg-&gt;display_config.overrides.all_streams_blanked) {</div><div class='add'>+		/* stream is blanked, so do nothing */</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* from display configuration */</div><div class='add'>+	base_programming-&gt;htotal = (uint16_t)stream_descriptor-&gt;timing.h_total;</div><div class='add'>+	base_programming-&gt;vtotal = (uint16_t)stream_descriptor-&gt;timing.v_total;</div><div class='add'>+	base_programming-&gt;vblank_start = (uint16_t)(stream_pstate_meta-&gt;nom_vtotal -</div><div class='add'>+		stream_descriptor-&gt;timing.v_front_porch);</div><div class='add'>+	base_programming-&gt;vblank_end = (uint16_t)(stream_pstate_meta-&gt;nom_vtotal -</div><div class='add'>+		stream_descriptor-&gt;timing.v_front_porch -</div><div class='add'>+		stream_descriptor-&gt;timing.v_active);</div><div class='add'>+	base_programming-&gt;config.bits.is_drr = stream_descriptor-&gt;timing.drr_config.enabled;</div><div class='add'>+</div><div class='add'>+	/* from meta */</div><div class='add'>+	base_programming-&gt;otg_vline_time_ns =</div><div class='add'>+		(unsigned int)(stream_pstate_meta-&gt;otg_vline_time_us * 1000.0);</div><div class='add'>+	base_programming-&gt;scheduling_delay_otg_vlines = (uint8_t)stream_pstate_meta-&gt;scheduling_delay_otg_vlines;</div><div class='add'>+	base_programming-&gt;contention_delay_otg_vlines = (uint8_t)stream_pstate_meta-&gt;contention_delay_otg_vlines;</div><div class='add'>+	base_programming-&gt;vline_int_ack_delay_otg_vlines = (uint8_t)stream_pstate_meta-&gt;vertical_interrupt_ack_delay_otg_vlines;</div><div class='add'>+	base_programming-&gt;drr_keepout_otg_vline = (uint16_t)(stream_pstate_meta-&gt;nom_vtotal -</div><div class='add'>+		stream_descriptor-&gt;timing.v_front_porch -</div><div class='add'>+		stream_pstate_meta-&gt;method_drr.programming_delay_otg_vlines);</div><div class='add'>+	base_programming-&gt;allow_to_target_delay_otg_vlines = (uint8_t)stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines;</div><div class='add'>+	base_programming-&gt;max_vtotal = (uint16_t)stream_pstate_meta-&gt;max_vtotal;</div><div class='add'>+</div><div class='add'>+	/* from core */</div><div class='add'>+	base_programming-&gt;config.bits.min_ttu_vblank_usable = true;</div><div class='add'>+	for (i = 0; i &lt; display_cfg-&gt;display_config.num_planes; i++) {</div><div class='add'>+		/* check if all planes support p-state in blank */</div><div class='add'>+		if (display_cfg-&gt;display_config.plane_descriptors[i].stream_index == plane_descriptor-&gt;stream_index &amp;&amp;</div><div class='add'>+				mode_lib-&gt;mp.MinTTUVBlank[i] &lt;= mode_lib-&gt;mp.Watermark.DRAMClockChangeWatermark) {</div><div class='add'>+			base_programming-&gt;config.bits.min_ttu_vblank_usable = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (pstate_method) {</div><div class='add'>+	case dml2_pstate_method_vactive:</div><div class='add'>+	case dml2_pstate_method_fw_vactive_drr:</div><div class='add'>+		/* legacy vactive */</div><div class='add'>+		base_programming-&gt;type = FAMS2_STREAM_TYPE_VACTIVE;</div><div class='add'>+		sub_programming-&gt;legacy.vactive_det_fill_delay_otg_vlines =</div><div class='add'>+			(uint8_t)stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_otg_vlines;</div><div class='add'>+		base_programming-&gt;allow_start_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_vactive.common.allow_start_otg_vline;</div><div class='add'>+		base_programming-&gt;allow_end_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_vactive.common.allow_end_otg_vline;</div><div class='add'>+		base_programming-&gt;config.bits.clamp_vtotal_min = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_vblank:</div><div class='add'>+	case dml2_pstate_method_fw_vblank_drr:</div><div class='add'>+		/* legacy vblank */</div><div class='add'>+		base_programming-&gt;type = FAMS2_STREAM_TYPE_VBLANK;</div><div class='add'>+		base_programming-&gt;allow_start_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_vblank.common.allow_start_otg_vline;</div><div class='add'>+		base_programming-&gt;allow_end_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_vblank.common.allow_end_otg_vline;</div><div class='add'>+		base_programming-&gt;config.bits.clamp_vtotal_min = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_drr:</div><div class='add'>+		/* drr */</div><div class='add'>+		base_programming-&gt;type = FAMS2_STREAM_TYPE_DRR;</div><div class='add'>+		sub_programming-&gt;drr.programming_delay_otg_vlines =</div><div class='add'>+			(uint8_t)stream_pstate_meta-&gt;method_drr.programming_delay_otg_vlines;</div><div class='add'>+		sub_programming-&gt;drr.nom_stretched_vtotal =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_drr.stretched_vtotal;</div><div class='add'>+		base_programming-&gt;allow_start_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_drr.common.allow_start_otg_vline;</div><div class='add'>+		base_programming-&gt;allow_end_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_drr.common.allow_end_otg_vline;</div><div class='add'>+		/* drr only clamps to vtotal min for single display */</div><div class='add'>+		base_programming-&gt;config.bits.clamp_vtotal_min = display_cfg-&gt;display_config.num_streams == 1;</div><div class='add'>+		sub_programming-&gt;drr.only_stretch_if_required = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_svp:</div><div class='add'>+	case dml2_pstate_method_fw_svp_drr:</div><div class='add'>+		/* subvp */</div><div class='add'>+		base_programming-&gt;type = FAMS2_STREAM_TYPE_SUBVP;</div><div class='add'>+		sub_programming-&gt;subvp.vratio_numerator =</div><div class='add'>+			(uint16_t)(plane_descriptor-&gt;composition.scaler_info.plane0.v_ratio * 1000.0);</div><div class='add'>+		sub_programming-&gt;subvp.vratio_denominator = 1000;</div><div class='add'>+		sub_programming-&gt;subvp.programming_delay_otg_vlines =</div><div class='add'>+			(uint8_t)stream_pstate_meta-&gt;method_subvp.programming_delay_otg_vlines;</div><div class='add'>+		sub_programming-&gt;subvp.prefetch_to_mall_otg_vlines =</div><div class='add'>+			(uint8_t)stream_pstate_meta-&gt;method_subvp.prefetch_to_mall_delay_otg_vlines;</div><div class='add'>+		sub_programming-&gt;subvp.phantom_vtotal =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_subvp.phantom_vtotal;</div><div class='add'>+		sub_programming-&gt;subvp.phantom_vactive =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_subvp.phantom_vactive;</div><div class='add'>+		sub_programming-&gt;subvp.config.bits.is_multi_planar =</div><div class='add'>+			plane_descriptor-&gt;surface.plane1.height &gt; 0;</div><div class='add'>+		sub_programming-&gt;subvp.config.bits.is_yuv420 =</div><div class='add'>+			plane_descriptor-&gt;pixel_format == dml2_420_8 ||</div><div class='add'>+			plane_descriptor-&gt;pixel_format == dml2_420_10 ||</div><div class='add'>+			plane_descriptor-&gt;pixel_format == dml2_420_12;</div><div class='add'>+</div><div class='add'>+		base_programming-&gt;allow_start_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_subvp.common.allow_start_otg_vline;</div><div class='add'>+		base_programming-&gt;allow_end_otg_vline =</div><div class='add'>+			(uint16_t)stream_pstate_meta-&gt;method_subvp.common.allow_end_otg_vline;</div><div class='add'>+		base_programming-&gt;config.bits.clamp_vtotal_min = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_reserved_hw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_clamped:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_var:</div><div class='add'>+	case dml2_pstate_method_na:</div><div class='add'>+	case dml2_pstate_method_count:</div><div class='add'>+	default:</div><div class='add'>+		/* this should never happen */</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_mcache_allocation(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_mcache_surface_allocation *out, int plane_idx)</div><div class='add'>+{</div><div class='add'>+	unsigned int n;</div><div class='add'>+</div><div class='add'>+	out-&gt;num_mcaches_plane0 = dml_get_plane_num_mcaches_plane0(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;num_mcaches_plane1 = dml_get_plane_num_mcaches_plane1(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;shift_granularity.p0 = dml_get_plane_mcache_shift_granularity_plane0(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;shift_granularity.p1 = dml_get_plane_mcache_shift_granularity_plane1(mode_lib, plane_idx);</div><div class='add'>+</div><div class='add'>+	for (n = 0; n &lt; out-&gt;num_mcaches_plane0; n++)</div><div class='add'>+		out-&gt;mcache_x_offsets_plane0[n] = dml_get_plane_array_mcache_offsets_plane0(mode_lib, plane_idx, n);</div><div class='add'>+</div><div class='add'>+	for (n = 0; n &lt; out-&gt;num_mcaches_plane1; n++)</div><div class='add'>+		out-&gt;mcache_x_offsets_plane1[n] = dml_get_plane_array_mcache_offsets_plane1(mode_lib, plane_idx, n);</div><div class='add'>+</div><div class='add'>+	out-&gt;last_slice_sharing.mall_comb_mcache_p0 = dml_get_plane_mall_comb_mcache_l(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;last_slice_sharing.mall_comb_mcache_p1 = dml_get_plane_mall_comb_mcache_c(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;last_slice_sharing.plane0_plane1 = dml_get_plane_lc_comb_mcache(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;informative.meta_row_bytes_plane0 = dml_get_plane_mcache_row_bytes_plane0(mode_lib, plane_idx);</div><div class='add'>+	out-&gt;informative.meta_row_bytes_plane1 = dml_get_plane_mcache_row_bytes_plane1(mode_lib, plane_idx);</div><div class='add'>+</div><div class='add'>+	out-&gt;valid = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_mall_allocation(struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int *out, int pipe_index)</div><div class='add'>+{</div><div class='add'>+	*out = dml_get_surface_size_in_mall_bytes(mode_lib, pipe_index);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_plane_support_info *out, int plane_idx)</div><div class='add'>+{</div><div class='add'>+	out-&gt;mall_svp_size_requirement_ways = 0;</div><div class='add'>+</div><div class='add'>+	out-&gt;nominal_vblank_pstate_latency_hiding_us =</div><div class='add'>+		(int)(display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_idx].stream_index].timing.h_total /</div><div class='add'>+			((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_idx].stream_index].timing.pixel_clock_khz / 1000) * mode_lib-&gt;ms.TWait[plane_idx]);</div><div class='add'>+</div><div class='add'>+	out-&gt;dram_change_latency_hiding_margin_in_active = (int)mode_lib-&gt;ms.VActiveLatencyHidingMargin[plane_idx];</div><div class='add'>+</div><div class='add'>+	out-&gt;active_latency_hiding_us = (int)mode_lib-&gt;ms.VActiveLatencyHidingUs[plane_idx];</div><div class='add'>+</div><div class='add'>+	out-&gt;vactive_det_fill_delay_us[dml2_pstate_type_uclk] =</div><div class='add'>+			(unsigned int)math_ceil(mode_lib-&gt;ms.pstate_vactive_det_fill_delay_us[dml2_pstate_type_uclk][plane_idx]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index)</div><div class='add'>+{</div><div class='add'>+	double phantom_processing_delay_pix;</div><div class='add'>+	unsigned int phantom_processing_delay_lines;</div><div class='add'>+	unsigned int phantom_min_v_active_lines;</div><div class='add'>+	unsigned int phantom_v_active_lines;</div><div class='add'>+	unsigned int phantom_v_startup_lines;</div><div class='add'>+	unsigned int phantom_v_blank_lines;</div><div class='add'>+	unsigned int main_v_blank_lines;</div><div class='add'>+	unsigned int rem;</div><div class='add'>+</div><div class='add'>+	phantom_processing_delay_pix = (double)((mode_lib-&gt;ip.subvp_fw_processing_delay_us + mode_lib-&gt;ip.subvp_pstate_allow_width_us) *</div><div class='add'>+		((double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_index].stream_index].timing.pixel_clock_khz / 1000));</div><div class='add'>+	phantom_processing_delay_lines = (unsigned int)(phantom_processing_delay_pix / (double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_index].stream_index].timing.h_total);</div><div class='add'>+	dml2_core_div_rem(phantom_processing_delay_pix,</div><div class='add'>+				display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_index].stream_index].timing.h_total,</div><div class='add'>+				&amp;rem);</div><div class='add'>+	if (rem)</div><div class='add'>+		phantom_processing_delay_lines++;</div><div class='add'>+</div><div class='add'>+	phantom_v_startup_lines = dml_get_plane_max_vstartup_lines(mode_lib, plane_index);</div><div class='add'>+	phantom_min_v_active_lines = (unsigned int)math_ceil((double)dml_get_plane_subviewport_lines_needed_in_mall(mode_lib, plane_index) /</div><div class='add'>+			display_cfg-&gt;plane_descriptors[plane_index].composition.scaler_info.plane0.v_ratio);</div><div class='add'>+	phantom_v_active_lines = phantom_processing_delay_lines + phantom_min_v_active_lines + mode_lib-&gt;ip.subvp_swath_height_margin_lines;</div><div class='add'>+</div><div class='add'>+	// phantom_vblank = max(vbp(vstartup) + vactive + vfp(always 1) + vsync(can be 1), main_vblank)</div><div class='add'>+	phantom_v_blank_lines = phantom_v_startup_lines + 1 + 1;</div><div class='add'>+	main_v_blank_lines = display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_index].stream_index].timing.v_total - display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[plane_index].stream_index].timing.v_active;</div><div class='add'>+	if (phantom_v_blank_lines &gt; main_v_blank_lines)</div><div class='add'>+		phantom_v_blank_lines = main_v_blank_lines;</div><div class='add'>+</div><div class='add'>+	out-&gt;phantom_v_active = phantom_v_active_lines;</div><div class='add'>+	// phantom_vtotal = vactive + vblank</div><div class='add'>+	out-&gt;phantom_v_total = phantom_v_active_lines + phantom_v_blank_lines;</div><div class='add'>+</div><div class='add'>+	out-&gt;phantom_min_v_active = phantom_min_v_active_lines;</div><div class='add'>+	out-&gt;phantom_v_startup = phantom_v_startup_lines;</div><div class='add'>+</div><div class='add'>+	out-&gt;vblank_reserved_time_us = display_cfg-&gt;plane_descriptors[plane_index].overrides.reserved_vblank_time_ns / 1000;</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: subvp_fw_processing_delay_us = %d\n", __func__, mode_lib-&gt;ip.subvp_fw_processing_delay_us);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: subvp_pstate_allow_width_us = %d\n", __func__, mode_lib-&gt;ip.subvp_pstate_allow_width_us);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: subvp_swath_height_margin_lines = %d\n", __func__, mode_lib-&gt;ip.subvp_swath_height_margin_lines);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: vblank_reserved_time_us = %u\n", __func__, out-&gt;vblank_reserved_time_us);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_cfg_programming *out)</div><div class='add'>+{</div><div class='add'>+	unsigned int k, n;</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.mode_support_info.ModeIsSupported = mode_lib-&gt;ms.support.ModeSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.ImmediateFlipSupport = mode_lib-&gt;ms.support.ImmediateFlipSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.WritebackLatencySupport = mode_lib-&gt;ms.support.WritebackLatencySupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.ScaleRatioAndTapsSupport = mode_lib-&gt;ms.support.ScaleRatioAndTapsSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.SourceFormatPixelAndScanSupport = mode_lib-&gt;ms.support.SourceFormatPixelAndScanSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.P2IWith420 = mode_lib-&gt;ms.support.P2IWith420;</div><div class='add'>+	out-&gt;informative.mode_support_info.DSCOnlyIfNecessaryWithBPP = false;</div><div class='add'>+	out-&gt;informative.mode_support_info.DSC422NativeNotSupported = mode_lib-&gt;ms.support.DSC422NativeNotSupported;</div><div class='add'>+	out-&gt;informative.mode_support_info.LinkRateDoesNotMatchDPVersion = mode_lib-&gt;ms.support.LinkRateDoesNotMatchDPVersion;</div><div class='add'>+	out-&gt;informative.mode_support_info.LinkRateForMultistreamNotIndicated = mode_lib-&gt;ms.support.LinkRateForMultistreamNotIndicated;</div><div class='add'>+	out-&gt;informative.mode_support_info.BPPForMultistreamNotIndicated = mode_lib-&gt;ms.support.BPPForMultistreamNotIndicated;</div><div class='add'>+	out-&gt;informative.mode_support_info.MultistreamWithHDMIOreDP = mode_lib-&gt;ms.support.MultistreamWithHDMIOreDP;</div><div class='add'>+	out-&gt;informative.mode_support_info.MSOOrODMSplitWithNonDPLink = mode_lib-&gt;ms.support.MSOOrODMSplitWithNonDPLink;</div><div class='add'>+	out-&gt;informative.mode_support_info.NotEnoughLanesForMSO = mode_lib-&gt;ms.support.NotEnoughLanesForMSO;</div><div class='add'>+	out-&gt;informative.mode_support_info.NumberOfOTGSupport = mode_lib-&gt;ms.support.NumberOfOTGSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.NumberOfHDMIFRLSupport = mode_lib-&gt;ms.support.NumberOfHDMIFRLSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.NumberOfDP2p0Support = mode_lib-&gt;ms.support.NumberOfDP2p0Support;</div><div class='add'>+	out-&gt;informative.mode_support_info.WritebackScaleRatioAndTapsSupport = mode_lib-&gt;ms.support.WritebackScaleRatioAndTapsSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.CursorSupport = mode_lib-&gt;ms.support.CursorSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.PitchSupport = mode_lib-&gt;ms.support.PitchSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.ViewportExceedsSurface = mode_lib-&gt;ms.support.ViewportExceedsSurface;</div><div class='add'>+	out-&gt;informative.mode_support_info.ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified = false;</div><div class='add'>+	out-&gt;informative.mode_support_info.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = mode_lib-&gt;ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;</div><div class='add'>+	out-&gt;informative.mode_support_info.InvalidCombinationOfMALLUseForPStateAndStaticScreen = mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPStateAndStaticScreen;</div><div class='add'>+	out-&gt;informative.mode_support_info.InvalidCombinationOfMALLUseForPState = mode_lib-&gt;ms.support.InvalidCombinationOfMALLUseForPState;</div><div class='add'>+	out-&gt;informative.mode_support_info.ExceededMALLSize = mode_lib-&gt;ms.support.ExceededMALLSize;</div><div class='add'>+	out-&gt;informative.mode_support_info.EnoughWritebackUnits = mode_lib-&gt;ms.support.EnoughWritebackUnits;</div><div class='add'>+	out-&gt;informative.mode_support_info.temp_read_or_ppt_support = mode_lib-&gt;ms.support.global_temp_read_or_ppt_supported;</div><div class='add'>+	out-&gt;informative.mode_support_info.g6_temp_read_support = mode_lib-&gt;ms.support.g6_temp_read_support;</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.mode_support_info.ExceededMultistreamSlots = mode_lib-&gt;ms.support.ExceededMultistreamSlots;</div><div class='add'>+	out-&gt;informative.mode_support_info.NotEnoughDSCUnits = mode_lib-&gt;ms.support.NotEnoughDSCUnits;</div><div class='add'>+	out-&gt;informative.mode_support_info.NotEnoughDSCSlices = mode_lib-&gt;ms.support.NotEnoughDSCSlices;</div><div class='add'>+	out-&gt;informative.mode_support_info.PixelsPerLinePerDSCUnitSupport = mode_lib-&gt;ms.support.PixelsPerLinePerDSCUnitSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.DSCCLKRequiredMoreThanSupported = mode_lib-&gt;ms.support.DSCCLKRequiredMoreThanSupported;</div><div class='add'>+	out-&gt;informative.mode_support_info.DTBCLKRequiredMoreThanSupported = mode_lib-&gt;ms.support.DTBCLKRequiredMoreThanSupported;</div><div class='add'>+	out-&gt;informative.mode_support_info.LinkCapacitySupport = mode_lib-&gt;ms.support.LinkCapacitySupport;</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.mode_support_info.ROBSupport = mode_lib-&gt;ms.support.ROBSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.OutstandingRequestsSupport = mode_lib-&gt;ms.support.OutstandingRequestsSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.OutstandingRequestsUrgencyAvoidance = mode_lib-&gt;ms.support.OutstandingRequestsUrgencyAvoidance;</div><div class='add'>+	out-&gt;informative.mode_support_info.PTEBufferSizeNotExceeded = mode_lib-&gt;ms.support.PTEBufferSizeNotExceeded;</div><div class='add'>+	out-&gt;informative.mode_support_info.DCCMetaBufferSizeNotExceeded = mode_lib-&gt;ms.support.DCCMetaBufferSizeNotExceeded;</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.mode_support_info.TotalVerticalActiveBandwidthSupport = mode_lib-&gt;ms.support.AvgBandwidthSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.VActiveBandwidthSupport = mode_lib-&gt;ms.support.UrgVactiveBandwidthSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.USRRetrainingSupport = mode_lib-&gt;ms.support.USRRetrainingSupport;</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.mode_support_info.PrefetchSupported = mode_lib-&gt;ms.support.PrefetchSupported;</div><div class='add'>+	out-&gt;informative.mode_support_info.DynamicMetadataSupported = mode_lib-&gt;ms.support.DynamicMetadataSupported;</div><div class='add'>+	out-&gt;informative.mode_support_info.VRatioInPrefetchSupported = mode_lib-&gt;ms.support.VRatioInPrefetchSupported;</div><div class='add'>+	out-&gt;informative.mode_support_info.DISPCLK_DPPCLK_Support = mode_lib-&gt;ms.support.DISPCLK_DPPCLK_Support;</div><div class='add'>+	out-&gt;informative.mode_support_info.TotalAvailablePipesSupport = mode_lib-&gt;ms.support.TotalAvailablePipesSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.NumberOfTDLUT33cubeSupport = mode_lib-&gt;ms.support.NumberOfTDLUT33cubeSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.ViewportSizeSupport = mode_lib-&gt;ms.support.ViewportSizeSupport;</div><div class='add'>+	out-&gt;informative.mode_support_info.qos_bandwidth_support = mode_lib-&gt;ms.support.qos_bandwidth_support;</div><div class='add'>+	out-&gt;informative.mode_support_info.dcfclk_support = mode_lib-&gt;ms.support.dcfclk_support;</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; out-&gt;display_config.num_planes; k++) {</div><div class='add'>+</div><div class='add'>+		out-&gt;informative.mode_support_info.FCLKChangeSupport[k] = mode_lib-&gt;ms.support.FCLKChangeSupport[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.MPCCombineEnable[k] = mode_lib-&gt;ms.support.MPCCombineEnable[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.ODMMode[k] = mode_lib-&gt;ms.support.ODMMode[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.DPPPerSurface[k] = mode_lib-&gt;ms.support.DPPPerSurface[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.DSCEnabled[k] = mode_lib-&gt;ms.support.DSCEnabled[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.FECEnabled[k] = mode_lib-&gt;ms.support.FECEnabled[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.NumberOfDSCSlices[k] = mode_lib-&gt;ms.support.NumberOfDSCSlices[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.OutputBpp[k] = mode_lib-&gt;ms.support.OutputBpp[k];</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.support.OutputType[k] == dml2_core_internal_output_type_unknown)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputType[k] = dml2_output_type_unknown;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputType[k] == dml2_core_internal_output_type_dp)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputType[k] = dml2_output_type_dp;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputType[k] == dml2_core_internal_output_type_edp)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputType[k] = dml2_output_type_edp;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputType[k] == dml2_core_internal_output_type_dp2p0)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputType[k] = dml2_output_type_dp2p0;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputType[k] == dml2_core_internal_output_type_hdmi)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputType[k] = dml2_output_type_hdmi;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputType[k] == dml2_core_internal_output_type_hdmifrl)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputType[k] = dml2_output_type_hdmifrl;</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_unknown)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_unknown;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr2)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr2;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr3)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr3;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr10)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr10;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr13p5)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr13p5;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr20)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr20;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_3x3)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_3x3;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x3)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_6x3;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x4)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_6x4;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_8x4)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_8x4;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_10x4)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_10x4;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_12x4)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_12x4;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_16x4)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_16x4;</div><div class='add'>+		else if (mode_lib-&gt;ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_20x4)</div><div class='add'>+			out-&gt;informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_20x4;</div><div class='add'>+</div><div class='add'>+		out-&gt;informative.mode_support_info.AlignedYPitch[k] = mode_lib-&gt;ms.support.AlignedYPitch[k];</div><div class='add'>+		out-&gt;informative.mode_support_info.AlignedCPitch[k] = mode_lib-&gt;ms.support.AlignedCPitch[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.watermarks.urgent_us = dml_get_wm_urgent(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.writeback_urgent_us = dml_get_wm_writeback_urgent(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.writeback_pstate_us = dml_get_wm_writeback_dram_clock_change(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.writeback_fclk_pstate_us = dml_get_wm_writeback_fclk_change(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.watermarks.cstate_exit_us = dml_get_wm_stutter_exit(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.cstate_enter_plus_exit_us = dml_get_wm_stutter_enter_exit(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.z8_cstate_exit_us = dml_get_wm_z8_stutter_exit(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.z8_cstate_enter_plus_exit_us = dml_get_wm_z8_stutter_enter_exit(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.pstate_change_us = dml_get_wm_dram_clock_change(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.fclk_pstate_change_us = dml_get_wm_fclk_change(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.usr_retraining_us = dml_get_wm_usr_retraining(mode_lib);</div><div class='add'>+	out-&gt;informative.watermarks.temp_read_or_ppt_watermark_us = dml_get_wm_temp_read_or_ppt(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.mall.total_surface_size_in_mall_bytes = 0;</div><div class='add'>+	out-&gt;informative.dpp.total_num_dpps_required = 0;</div><div class='add'>+	for (k = 0; k &lt; out-&gt;display_config.num_planes; ++k) {</div><div class='add'>+		out-&gt;informative.mall.total_surface_size_in_mall_bytes += mode_lib-&gt;mp.SurfaceSizeInTheMALL[k];</div><div class='add'>+		out-&gt;informative.dpp.total_num_dpps_required += mode_lib-&gt;mp.NoOfDPP[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.min_return_latency_in_dcfclk = mode_lib-&gt;mp.min_return_latency_in_dcfclk;</div><div class='add'>+	out-&gt;informative.qos.urgent_latency_us = dml_get_urgent_latency(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.max_urgent_latency_us = dml_get_max_urgent_latency_us(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_non_urgent_latency_us = dml_get_avg_non_urgent_latency_us(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_urgent_latency_us = dml_get_avg_urgent_latency_us(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.wm_memory_trip_us = dml_get_wm_memory_trip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.meta_trip_memory_us = dml_get_meta_trip_memory_us(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.fraction_of_urgent_bandwidth = dml_get_fraction_of_urgent_bandwidth(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.fraction_of_urgent_bandwidth_immediate_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.fraction_of_urgent_bandwidth_mall = dml_get_fraction_of_urgent_bandwidth_mall(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.avg_bw_required.sys_active.sdp_bw_mbps = dml_get_sys_active_avg_bw_required_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_bw_required.sys_active.dram_bw_mbps = dml_get_sys_active_avg_bw_required_dram(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_bw_required.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_avg_bw_required_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_bw_required.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_avg_bw_required_dram(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.avg_bw_available.sys_active.sdp_bw_mbps = dml_get_sys_active_avg_bw_available_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_bw_available.sys_active.dram_bw_mbps = dml_get_sys_active_avg_bw_available_dram(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_bw_available.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_avg_bw_available_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.avg_bw_available.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_avg_bw_available_dram(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.urg_bw_available.sys_active.sdp_bw_mbps = dml_get_sys_active_urg_bw_available_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_available.sys_active.dram_bw_mbps = dml_get_sys_active_urg_bw_available_dram(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_available.sys_active.dram_vm_only_bw_mbps = dml_get_sys_active_urg_bw_available_dram_vm_only(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.urg_bw_available.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_urg_bw_available_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_available.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_urg_bw_available_dram(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_available.svp_prefetch.dram_vm_only_bw_mbps = dml_get_svp_prefetch_urg_bw_available_dram_vm_only(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required.sys_active.sdp_bw_mbps = dml_get_sys_active_urg_bw_required_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required.sys_active.dram_bw_mbps = dml_get_sys_active_urg_bw_required_dram(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_urg_bw_required_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_urg_bw_required_dram(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required.sys_active.sdp_bw_mbps = dml_get_sys_active_non_urg_required_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required.sys_active.dram_bw_mbps = dml_get_sys_active_non_urg_required_dram(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_non_urg_bw_required_sdp(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_non_urg_bw_required_dram(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required_with_flip.sys_active.sdp_bw_mbps = dml_get_sys_active_urg_bw_required_sdp_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required_with_flip.sys_active.dram_bw_mbps = dml_get_sys_active_urg_bw_required_dram_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required_with_flip.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_urg_bw_required_sdp_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.urg_bw_required_with_flip.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_urg_bw_required_dram_flip(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required_with_flip.sys_active.sdp_bw_mbps = dml_get_sys_active_non_urg_required_sdp_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required_with_flip.sys_active.dram_bw_mbps = dml_get_sys_active_non_urg_required_dram_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required_with_flip.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_non_urg_bw_required_sdp_flip(mode_lib);</div><div class='add'>+	out-&gt;informative.qos.non_urg_bw_required_with_flip.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_non_urg_bw_required_dram_flip(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.crb.comp_buffer_size_kbytes = dml_get_comp_buffer_size_kbytes(mode_lib);</div><div class='add'>+	out-&gt;informative.crb.UnboundedRequestEnabled = dml_get_unbounded_request_enabled(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.crb.compbuf_reserved_space_64b = dml_get_compbuf_reserved_space_64b(mode_lib);</div><div class='add'>+	out-&gt;informative.misc.hw_debug5 = dml_get_hw_debug5(mode_lib);</div><div class='add'>+	out-&gt;informative.misc.dcfclk_deep_sleep_hysteresis = dml_get_dcfclk_deep_sleep_hysteresis(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.power_management.stutter_efficiency = dml_get_stutter_efficiency_no_vblank(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.stutter_efficiency_with_vblank = dml_get_stutter_efficiency(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.stutter_num_bursts = dml_get_stutter_num_bursts(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.power_management.z8.stutter_efficiency = dml_get_stutter_efficiency_z8(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.z8.stutter_efficiency_with_vblank = dml_get_stutter_efficiency(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.z8.stutter_num_bursts = dml_get_stutter_num_bursts_z8(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.z8.stutter_period = dml_get_stutter_period(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.power_management.z8.bestcase.stutter_efficiency = dml_get_stutter_efficiency_z8_bestcase(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.z8.bestcase.stutter_num_bursts = dml_get_stutter_num_bursts_z8_bestcase(mode_lib);</div><div class='add'>+	out-&gt;informative.power_management.z8.bestcase.stutter_period = dml_get_stutter_period_bestcase(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.misc.cstate_max_cap_mode = dml_get_cstate_max_cap_mode(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;min_clocks.dcn4x.dpprefclk_khz = (int unsigned)dml_get_global_dppclk_khz(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.qos.max_active_fclk_change_latency_supported = dml_get_fclk_change_latency(mode_lib);</div><div class='add'>+</div><div class='add'>+	out-&gt;informative.misc.LowestPrefetchMargin = 10 * 1000 * 1000;</div><div class='add'>+</div><div class='add'>+	for (k = 0; k &lt; out-&gt;display_config.num_planes; k++) {</div><div class='add'>+</div><div class='add'>+		if ((out-&gt;display_config.plane_descriptors-&gt;overrides.reserved_vblank_time_ns &gt;= 1000.0 * mode_lib-&gt;soc.power_management_parameters.dram_clk_change_blackout_us)</div><div class='add'>+			&amp;&amp; (out-&gt;display_config.plane_descriptors-&gt;overrides.reserved_vblank_time_ns &gt;= 1000.0 * mode_lib-&gt;soc.power_management_parameters.fclk_change_blackout_us)</div><div class='add'>+			&amp;&amp; (out-&gt;display_config.plane_descriptors-&gt;overrides.reserved_vblank_time_ns &gt;= 1000.0 * mode_lib-&gt;soc.power_management_parameters.stutter_enter_plus_exit_latency_us))</div><div class='add'>+			out-&gt;informative.misc.PrefetchMode[k] = 0;</div><div class='add'>+		else if ((out-&gt;display_config.plane_descriptors-&gt;overrides.reserved_vblank_time_ns &gt;= 1000.0 * mode_lib-&gt;soc.power_management_parameters.fclk_change_blackout_us)</div><div class='add'>+			&amp;&amp; (out-&gt;display_config.plane_descriptors-&gt;overrides.reserved_vblank_time_ns &gt;= 1000.0 * mode_lib-&gt;soc.power_management_parameters.stutter_enter_plus_exit_latency_us))</div><div class='add'>+			out-&gt;informative.misc.PrefetchMode[k] = 1;</div><div class='add'>+		else if (out-&gt;display_config.plane_descriptors-&gt;overrides.reserved_vblank_time_ns &gt;= 1000.0 * mode_lib-&gt;soc.power_management_parameters.stutter_enter_plus_exit_latency_us)</div><div class='add'>+			out-&gt;informative.misc.PrefetchMode[k] = 2;</div><div class='add'>+		else</div><div class='add'>+			out-&gt;informative.misc.PrefetchMode[k] = 3;</div><div class='add'>+</div><div class='add'>+		out-&gt;informative.misc.min_ttu_vblank_us[k] = mode_lib-&gt;mp.MinTTUVBlank[k];</div><div class='add'>+		out-&gt;informative.mall.subviewport_lines_needed_in_mall[k] = mode_lib-&gt;mp.SubViewportLinesNeededInMALL[k];</div><div class='add'>+		out-&gt;informative.crb.det_size_in_kbytes[k] = mode_lib-&gt;mp.DETBufferSizeInKByte[k];</div><div class='add'>+		out-&gt;informative.crb.DETBufferSizeY[k] = mode_lib-&gt;mp.DETBufferSizeY[k];</div><div class='add'>+		out-&gt;informative.misc.ImmediateFlipSupportedForPipe[k] = mode_lib-&gt;mp.ImmediateFlipSupportedForPipe[k];</div><div class='add'>+		out-&gt;informative.misc.UsesMALLForStaticScreen[k] = mode_lib-&gt;mp.is_using_mall_for_ss[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].dpte_row_height_plane0 = mode_lib-&gt;mp.dpte_row_height[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].dpte_row_height_plane1 = mode_lib-&gt;mp.dpte_row_height_chroma[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].meta_row_height_plane0 = mode_lib-&gt;mp.meta_row_height[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].meta_row_height_plane1 = mode_lib-&gt;mp.meta_row_height_chroma[k];</div><div class='add'>+		out-&gt;informative.dcc_control[k].max_uncompressed_block_plane0 = mode_lib-&gt;mp.DCCYMaxUncompressedBlock[k];</div><div class='add'>+		out-&gt;informative.dcc_control[k].max_compressed_block_plane0 = mode_lib-&gt;mp.DCCYMaxCompressedBlock[k];</div><div class='add'>+		out-&gt;informative.dcc_control[k].independent_block_plane0 = mode_lib-&gt;mp.DCCYIndependentBlock[k];</div><div class='add'>+		out-&gt;informative.dcc_control[k].max_uncompressed_block_plane1 = mode_lib-&gt;mp.DCCCMaxUncompressedBlock[k];</div><div class='add'>+		out-&gt;informative.dcc_control[k].max_compressed_block_plane1 = mode_lib-&gt;mp.DCCCMaxCompressedBlock[k];</div><div class='add'>+		out-&gt;informative.dcc_control[k].independent_block_plane1 = mode_lib-&gt;mp.DCCCIndependentBlock[k];</div><div class='add'>+		out-&gt;informative.misc.dst_x_after_scaler[k] = mode_lib-&gt;mp.DSTXAfterScaler[k];</div><div class='add'>+		out-&gt;informative.misc.dst_y_after_scaler[k] = mode_lib-&gt;mp.DSTYAfterScaler[k];</div><div class='add'>+		out-&gt;informative.misc.prefetch_source_lines_plane0[k] = mode_lib-&gt;mp.PrefetchSourceLinesY[k];</div><div class='add'>+		out-&gt;informative.misc.prefetch_source_lines_plane1[k] = mode_lib-&gt;mp.PrefetchSourceLinesC[k];</div><div class='add'>+		out-&gt;informative.misc.vready_at_or_after_vsync[k] = mode_lib-&gt;mp.VREADY_AT_OR_AFTER_VSYNC[k];</div><div class='add'>+		out-&gt;informative.misc.min_dst_y_next_start[k] = mode_lib-&gt;mp.MIN_DST_Y_NEXT_START[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].swath_width_plane0 = mode_lib-&gt;mp.SwathWidthY[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].swath_height_plane0 = mode_lib-&gt;mp.SwathHeightY[k];</div><div class='add'>+		out-&gt;informative.plane_info[k].swath_height_plane1 = mode_lib-&gt;mp.SwathHeightC[k];</div><div class='add'>+		out-&gt;informative.misc.CursorDstXOffset[k] = mode_lib-&gt;mp.CursorDstXOffset[k];</div><div class='add'>+		out-&gt;informative.misc.CursorDstYOffset[k] = mode_lib-&gt;mp.CursorDstYOffset[k];</div><div class='add'>+		out-&gt;informative.misc.CursorChunkHDLAdjust[k] = mode_lib-&gt;mp.CursorChunkHDLAdjust[k];</div><div class='add'>+		out-&gt;informative.misc.dpte_group_bytes[k] = mode_lib-&gt;mp.dpte_group_bytes[k];</div><div class='add'>+		out-&gt;informative.misc.vm_group_bytes[k] = mode_lib-&gt;mp.vm_group_bytes[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeRequestDeliveryTimeLuma[k] = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeLuma[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeRequestDeliveryTimeChroma[k] = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeChroma[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeLumaPrefetch[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = mode_lib-&gt;mp.DisplayPipeRequestDeliveryTimeChromaPrefetch[k];</div><div class='add'>+		out-&gt;informative.misc.TimePerVMGroupVBlank[k] = mode_lib-&gt;mp.TimePerVMGroupVBlank[k];</div><div class='add'>+		out-&gt;informative.misc.TimePerVMGroupFlip[k] = mode_lib-&gt;mp.TimePerVMGroupFlip[k];</div><div class='add'>+		out-&gt;informative.misc.TimePerVMRequestVBlank[k] = mode_lib-&gt;mp.TimePerVMRequestVBlank[k];</div><div class='add'>+		out-&gt;informative.misc.TimePerVMRequestFlip[k] = mode_lib-&gt;mp.TimePerVMRequestFlip[k];</div><div class='add'>+		out-&gt;informative.misc.Tdmdl_vm[k] = mode_lib-&gt;mp.Tdmdl_vm[k];</div><div class='add'>+		out-&gt;informative.misc.Tdmdl[k] = mode_lib-&gt;mp.Tdmdl[k];</div><div class='add'>+		out-&gt;informative.misc.VStartup[k] = mode_lib-&gt;mp.VStartup[k];</div><div class='add'>+		out-&gt;informative.misc.VUpdateOffsetPix[k] = mode_lib-&gt;mp.VUpdateOffsetPix[k];</div><div class='add'>+		out-&gt;informative.misc.VUpdateWidthPix[k] = mode_lib-&gt;mp.VUpdateWidthPix[k];</div><div class='add'>+		out-&gt;informative.misc.VReadyOffsetPix[k] = mode_lib-&gt;mp.VReadyOffsetPix[k];</div><div class='add'>+</div><div class='add'>+		out-&gt;informative.misc.DST_Y_PER_PTE_ROW_NOM_L[k] = mode_lib-&gt;mp.DST_Y_PER_PTE_ROW_NOM_L[k];</div><div class='add'>+		out-&gt;informative.misc.DST_Y_PER_PTE_ROW_NOM_C[k] = mode_lib-&gt;mp.DST_Y_PER_PTE_ROW_NOM_C[k];</div><div class='add'>+		out-&gt;informative.misc.time_per_pte_group_nom_luma[k] = mode_lib-&gt;mp.time_per_pte_group_nom_luma[k];</div><div class='add'>+		out-&gt;informative.misc.time_per_pte_group_nom_chroma[k] = mode_lib-&gt;mp.time_per_pte_group_nom_chroma[k];</div><div class='add'>+		out-&gt;informative.misc.time_per_pte_group_vblank_luma[k] = mode_lib-&gt;mp.time_per_pte_group_vblank_luma[k];</div><div class='add'>+		out-&gt;informative.misc.time_per_pte_group_vblank_chroma[k] = mode_lib-&gt;mp.time_per_pte_group_vblank_chroma[k];</div><div class='add'>+		out-&gt;informative.misc.time_per_pte_group_flip_luma[k] = mode_lib-&gt;mp.time_per_pte_group_flip_luma[k];</div><div class='add'>+		out-&gt;informative.misc.time_per_pte_group_flip_chroma[k] = mode_lib-&gt;mp.time_per_pte_group_flip_chroma[k];</div><div class='add'>+		out-&gt;informative.misc.VRatioPrefetchY[k] = mode_lib-&gt;mp.VRatioPrefetchY[k];</div><div class='add'>+		out-&gt;informative.misc.VRatioPrefetchC[k] = mode_lib-&gt;mp.VRatioPrefetchC[k];</div><div class='add'>+		out-&gt;informative.misc.DestinationLinesForPrefetch[k] = mode_lib-&gt;mp.dst_y_prefetch[k];</div><div class='add'>+		out-&gt;informative.misc.DestinationLinesToRequestVMInVBlank[k] = mode_lib-&gt;mp.dst_y_per_vm_vblank[k];</div><div class='add'>+		out-&gt;informative.misc.DestinationLinesToRequestRowInVBlank[k] = mode_lib-&gt;mp.dst_y_per_row_vblank[k];</div><div class='add'>+		out-&gt;informative.misc.DestinationLinesToRequestVMInImmediateFlip[k] = mode_lib-&gt;mp.dst_y_per_vm_flip[k];</div><div class='add'>+		out-&gt;informative.misc.DestinationLinesToRequestRowInImmediateFlip[k] = mode_lib-&gt;mp.dst_y_per_row_flip[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeLineDeliveryTimeLuma[k] = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeLuma[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeLineDeliveryTimeChroma[k] = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeChroma[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeLumaPrefetch[k];</div><div class='add'>+		out-&gt;informative.misc.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = mode_lib-&gt;mp.DisplayPipeLineDeliveryTimeChromaPrefetch[k];</div><div class='add'>+</div><div class='add'>+		out-&gt;informative.misc.WritebackRequiredBandwidth = mode_lib-&gt;mp.TotalWRBandwidth / 1000.0;</div><div class='add'>+		out-&gt;informative.misc.WritebackAllowDRAMClockChangeEndPosition[k] = mode_lib-&gt;mp.WritebackAllowDRAMClockChangeEndPosition[k];</div><div class='add'>+		out-&gt;informative.misc.WritebackAllowFCLKChangeEndPosition[k] = mode_lib-&gt;mp.WritebackAllowFCLKChangeEndPosition[k];</div><div class='add'>+		out-&gt;informative.misc.DSCCLK_calculated[k] = mode_lib-&gt;mp.DSCCLK[k];</div><div class='add'>+		out-&gt;informative.misc.BIGK_FRAGMENT_SIZE[k] = mode_lib-&gt;mp.BIGK_FRAGMENT_SIZE[k];</div><div class='add'>+		out-&gt;informative.misc.PTE_BUFFER_MODE[k] = mode_lib-&gt;mp.PTE_BUFFER_MODE[k];</div><div class='add'>+		out-&gt;informative.misc.DSCDelay[k] = mode_lib-&gt;mp.DSCDelay[k];</div><div class='add'>+		out-&gt;informative.misc.MaxActiveDRAMClockChangeLatencySupported[k] = mode_lib-&gt;mp.MaxActiveDRAMClockChangeLatencySupported[k];</div><div class='add'>+</div><div class='add'>+		if (mode_lib-&gt;mp.impacted_prefetch_margin_us[k] &lt; out-&gt;informative.misc.LowestPrefetchMargin)</div><div class='add'>+			out-&gt;informative.misc.LowestPrefetchMargin = mode_lib-&gt;mp.impacted_prefetch_margin_us[k];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// For this DV informative layer, all pipes in the same planes will just use the same id</div><div class='add'>+	// will have the optimization and helper layer later on</div><div class='add'>+	// only work when we can have high "mcache" that fit everything without thrashing the cache</div><div class='add'>+	for (k = 0; k &lt; out-&gt;display_config.num_planes; k++) {</div><div class='add'>+		out-&gt;informative.non_optimized_mcache_allocation[k].num_mcaches_plane0 = dml_get_plane_num_mcaches_plane0(mode_lib, k);</div><div class='add'>+		out-&gt;informative.non_optimized_mcache_allocation[k].informative.meta_row_bytes_plane0 = dml_get_plane_mcache_row_bytes_plane0(mode_lib, k);</div><div class='add'>+</div><div class='add'>+		for (n = 0; n &lt; out-&gt;informative.non_optimized_mcache_allocation[k].num_mcaches_plane0; n++) {</div><div class='add'>+			out-&gt;informative.non_optimized_mcache_allocation[k].mcache_x_offsets_plane0[n] = dml_get_plane_array_mcache_offsets_plane0(mode_lib, k, n);</div><div class='add'>+			out-&gt;informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane0[n] = k;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		out-&gt;informative.non_optimized_mcache_allocation[k].num_mcaches_plane1 = dml_get_plane_num_mcaches_plane1(mode_lib, k);</div><div class='add'>+		out-&gt;informative.non_optimized_mcache_allocation[k].informative.meta_row_bytes_plane1 = dml_get_plane_mcache_row_bytes_plane1(mode_lib, k);</div><div class='add'>+</div><div class='add'>+		for (n = 0; n &lt; out-&gt;informative.non_optimized_mcache_allocation[k].num_mcaches_plane1; n++) {</div><div class='add'>+			out-&gt;informative.non_optimized_mcache_allocation[k].mcache_x_offsets_plane1[n] = dml_get_plane_array_mcache_offsets_plane1(mode_lib, k, n);</div><div class='add'>+			out-&gt;informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane1[n] = k;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	out-&gt;informative.qos.max_non_urgent_latency_us = dml_get_max_non_urgent_latency_us(mode_lib);</div><div class='add'>+</div><div class='add'>+	if (mode_lib-&gt;soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x) {</div><div class='add'>+		if (((mode_lib-&gt;ip.rob_buffer_size_kbytes - mode_lib-&gt;ip.pixel_chunk_size_kbytes) * 1024</div><div class='add'>+			/ mode_lib-&gt;ms.support.non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) &gt;= out-&gt;informative.qos.max_non_urgent_latency_us) {</div><div class='add'>+			out-&gt;informative.misc.ROBUrgencyAvoidance = true;</div><div class='add'>+		} else {</div><div class='add'>+			out-&gt;informative.misc.ROBUrgencyAvoidance = false;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		out-&gt;informative.misc.ROBUrgencyAvoidance = true;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h<br/>new file mode 100644<br/>index 000000000000..27ef0e096b25<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_CORE_DCN4_CALCS_H__</div><div class='add'>+#define __DML2_CORE_DCN4_CALCS_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_core_shared_types.h"</div><div class='add'>+</div><div class='add'>+struct dml2_dchub_watermark_regs;</div><div class='add'>+struct dml2_display_arb_regs;</div><div class='add'>+struct dml2_per_stream_programming;</div><div class='add'>+struct dml2_dchub_per_pipe_register_set;</div><div class='add'>+struct core_plane_support_info;</div><div class='add'>+struct core_stream_support_info;</div><div class='add'>+struct dml2_cursor_dlg_regs;</div><div class='add'>+struct display_configuation_with_meta;</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_calcs_mode_support_ex(struct dml2_core_calcs_mode_support_ex *in_out_params);</div><div class='add'>+bool dml2_core_calcs_mode_programming_ex(struct dml2_core_calcs_mode_programming_ex *in_out_params);</div><div class='add'>+void dml2_core_calcs_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_watermark_regs *out);</div><div class='add'>+void dml2_core_calcs_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_arb_regs *out);</div><div class='add'>+void dml2_core_calcs_get_pipe_regs(const struct dml2_display_cfg *dml2_display_cfg, struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_per_pipe_register_set *out, int pipe_index);</div><div class='add'>+void dml2_core_calcs_get_stream_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_per_stream_programming *out, int pipe_index);</div><div class='add'>+void dml2_core_calcs_get_global_sync_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, union dml2_global_sync_programming *out, int pipe_index);</div><div class='add'>+void dml2_core_calcs_get_mcache_allocation(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_mcache_surface_allocation *out, int plane_index);</div><div class='add'>+void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_plane_support_info *out, int plane_index);</div><div class='add'>+void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_cfg_programming *out);</div><div class='add'>+void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index);</div><div class='add'>+void dml2_core_calcs_get_mall_allocation(struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int *out, int pipe_index);</div><div class='add'>+void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, union dmub_cmd_fams2_config *fams2_base_programming, union dmub_cmd_fams2_config *fams2_sub_programming, enum dml2_pstate_method pstate_method, int plane_index);</div><div class='add'>+void dml2_core_calcs_get_global_fams2_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, const struct display_configuation_with_meta *display_cfg, struct dmub_cmd_fams2_global_config *fams2_global_config);</div><div class='add'>+</div><div class='add'>+void dml2_core_calcs_get_dpte_row_height(unsigned int *dpte_row_height, struct dml2_core_internal_display_mode_lib *mode_lib, bool is_plane1, enum dml2_source_format_class SourcePixelFormat, enum dml2_swizzle_mode SurfaceTiling, enum dml2_rotation_angle ScanDirection, unsigned int pitch, unsigned int GPUVMMinPageSizeKBytes);</div><div class='add'>+void dml2_core_calcs_cursor_dlg_reg(struct dml2_cursor_dlg_regs *cursor_dlg_regs, const struct dml2_get_cursor_dlg_reg *p);</div><div class='add'>+const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type);</div><div class='add'>+const char *dml2_core_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c<br/>new file mode 100644<br/>index 000000000000..cc4f0663c6d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_core_factory.h"</div><div class='add'>+#include "dml2_core_dcn4.h"</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+</div><div class='add'>+bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance *out)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (!out)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memset(out, 0, sizeof(struct dml2_core_instance));</div><div class='add'>+</div><div class='add'>+	out-&gt;project_id = project_id;</div><div class='add'>+</div><div class='add'>+	switch (project_id) {</div><div class='add'>+	case dml2_project_dcn4x_stage1:</div><div class='add'>+		result = false;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_dcn4x_stage2:</div><div class='add'>+	case dml2_project_dcn4x_stage2_auto_drr_svp:</div><div class='add'>+		out-&gt;initialize = &amp;core_dcn4_initialize;</div><div class='add'>+		out-&gt;mode_support = &amp;core_dcn4_mode_support;</div><div class='add'>+		out-&gt;mode_programming = &amp;core_dcn4_mode_programming;</div><div class='add'>+		out-&gt;populate_informative = &amp;core_dcn4_populate_informative;</div><div class='add'>+		out-&gt;calculate_mcache_allocation = &amp;core_dcn4_calculate_mcache_allocation;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_invalid:</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h<br/>new file mode 100644<br/>index 000000000000..411c514fe65c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_CORE_FACTORY_H__</div><div class='add'>+#define __DML2_CORE_FACTORY_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance *out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h<br/>new file mode 100644<br/>index 000000000000..1087a8c926ff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h</a></div><div class='hunk'>@@ -0,0 +1,2341 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_CORE_SHARED_TYPES_H__</div><div class='add'>+#define __DML2_CORE_SHARED_TYPES_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+#include "dml_top_display_cfg_types.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+#define __DML_VBA_DEBUG__</div><div class='add'>+#define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //&lt;brief max vratio for one-to-one prefetch bw scheduling</div><div class='add'>+#define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //&lt;brief max vratio for equalized prefetch bw scheduling</div><div class='add'>+#define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //&lt;brief max prefetch vratio register limit</div><div class='add'>+</div><div class='add'>+#define __DML2_CALCS_DPP_INVALID__ 0</div><div class='add'>+#define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //&lt;brief fudge factor for min dcfclk calclation</div><div class='add'>+#define __DML2_CALCS_PIPE_NO_PLANE__ 99</div><div class='add'>+</div><div class='add'>+struct dml2_core_ip_params {</div><div class='add'>+	unsigned int vblank_nom_default_us;</div><div class='add'>+	unsigned int remote_iommu_outstanding_translations;</div><div class='add'>+	unsigned int rob_buffer_size_kbytes;</div><div class='add'>+	unsigned int config_return_buffer_size_in_kbytes;</div><div class='add'>+	unsigned int config_return_buffer_segment_size_in_kbytes;</div><div class='add'>+	unsigned int compressed_buffer_segment_size_in_kbytes;</div><div class='add'>+	unsigned int meta_fifo_size_in_kentries;</div><div class='add'>+	unsigned int dpte_buffer_size_in_pte_reqs_luma;</div><div class='add'>+	unsigned int dpte_buffer_size_in_pte_reqs_chroma;</div><div class='add'>+	unsigned int pixel_chunk_size_kbytes;</div><div class='add'>+	unsigned int alpha_pixel_chunk_size_kbytes;</div><div class='add'>+	unsigned int min_pixel_chunk_size_bytes;</div><div class='add'>+	unsigned int writeback_chunk_size_kbytes;</div><div class='add'>+	unsigned int line_buffer_size_bits;</div><div class='add'>+	unsigned int max_line_buffer_lines;</div><div class='add'>+	unsigned int writeback_interface_buffer_size_kbytes;</div><div class='add'>+	unsigned int max_num_dpp;</div><div class='add'>+	unsigned int max_num_opp;</div><div class='add'>+	unsigned int max_num_otg;</div><div class='add'>+	unsigned int TDLUT_33cube_count;</div><div class='add'>+	unsigned int max_num_wb;</div><div class='add'>+	unsigned int max_dchub_pscl_bw_pix_per_clk;</div><div class='add'>+	unsigned int max_pscl_lb_bw_pix_per_clk;</div><div class='add'>+	unsigned int max_lb_vscl_bw_pix_per_clk;</div><div class='add'>+	unsigned int max_vscl_hscl_bw_pix_per_clk;</div><div class='add'>+	double max_hscl_ratio;</div><div class='add'>+	double max_vscl_ratio;</div><div class='add'>+	unsigned int max_hscl_taps;</div><div class='add'>+	unsigned int max_vscl_taps;</div><div class='add'>+	unsigned int odm_combine_support_mask;</div><div class='add'>+	unsigned int num_dsc;</div><div class='add'>+	unsigned int maximum_dsc_bits_per_component;</div><div class='add'>+	unsigned int maximum_pixels_per_line_per_dsc_unit;</div><div class='add'>+	bool dsc422_native_support;</div><div class='add'>+	bool cursor_64bpp_support;</div><div class='add'>+	double dispclk_ramp_margin_percent;</div><div class='add'>+	unsigned int dppclk_delay_subtotal;</div><div class='add'>+	unsigned int dppclk_delay_scl;</div><div class='add'>+	unsigned int dppclk_delay_scl_lb_only;</div><div class='add'>+	unsigned int dppclk_delay_cnvc_formatter;</div><div class='add'>+	unsigned int dppclk_delay_cnvc_cursor;</div><div class='add'>+	unsigned int cursor_buffer_size;</div><div class='add'>+	unsigned int cursor_chunk_size;</div><div class='add'>+	unsigned int dispclk_delay_subtotal;</div><div class='add'>+	bool dynamic_metadata_vm_enabled;</div><div class='add'>+	unsigned int max_inter_dcn_tile_repeaters;</div><div class='add'>+	unsigned int max_num_hdmi_frl_outputs;</div><div class='add'>+	unsigned int max_num_dp2p0_outputs;</div><div class='add'>+	unsigned int max_num_dp2p0_streams;</div><div class='add'>+	bool dcc_supported;</div><div class='add'>+	bool ptoi_supported;</div><div class='add'>+	double writeback_max_hscl_ratio;</div><div class='add'>+	double writeback_max_vscl_ratio;</div><div class='add'>+	double writeback_min_hscl_ratio;</div><div class='add'>+	double writeback_min_vscl_ratio;</div><div class='add'>+	unsigned int writeback_max_hscl_taps;</div><div class='add'>+	unsigned int writeback_max_vscl_taps;</div><div class='add'>+	unsigned int writeback_line_buffer_buffer_size;</div><div class='add'>+</div><div class='add'>+	unsigned int words_per_channel;</div><div class='add'>+	bool imall_supported;</div><div class='add'>+	unsigned int max_flip_time_us;</div><div class='add'>+	unsigned int max_flip_time_lines;</div><div class='add'>+	unsigned int subvp_swath_height_margin_lines;</div><div class='add'>+	unsigned int subvp_fw_processing_delay_us;</div><div class='add'>+	unsigned int subvp_pstate_allow_width_us;</div><div class='add'>+	// MRQ</div><div class='add'>+	bool dcn_mrq_present;</div><div class='add'>+	unsigned int zero_size_buffer_entries;</div><div class='add'>+	unsigned int compbuf_reserved_space_zs;</div><div class='add'>+	unsigned int dcc_meta_buffer_size_bytes;</div><div class='add'>+	unsigned int meta_chunk_size_kbytes;</div><div class='add'>+	unsigned int min_meta_chunk_size_bytes;</div><div class='add'>+</div><div class='add'>+	unsigned int dchub_arb_to_ret_delay; // num of dcfclk</div><div class='add'>+	unsigned int hostvm_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_DmlPipe {</div><div class='add'>+	double Dppclk;</div><div class='add'>+	double Dispclk;</div><div class='add'>+	double PixelClock;</div><div class='add'>+	double DCFClkDeepSleep;</div><div class='add'>+	unsigned int DPPPerSurface;</div><div class='add'>+	bool ScalerEnabled;</div><div class='add'>+	bool UPSPEnabled;</div><div class='add'>+	unsigned int UPSPVTaps;</div><div class='add'>+	enum dml2_sample_positioning UPSPSamplePositioning;</div><div class='add'>+	enum dml2_rotation_angle RotationAngle;</div><div class='add'>+	bool mirrored;</div><div class='add'>+	unsigned int ViewportHeight;</div><div class='add'>+	unsigned int ViewportHeightC;</div><div class='add'>+	unsigned int BlockWidth256BytesY;</div><div class='add'>+	unsigned int BlockHeight256BytesY;</div><div class='add'>+	unsigned int BlockWidth256BytesC;</div><div class='add'>+	unsigned int BlockHeight256BytesC;</div><div class='add'>+	unsigned int BlockWidthY;</div><div class='add'>+	unsigned int BlockHeightY;</div><div class='add'>+	unsigned int BlockWidthC;</div><div class='add'>+	unsigned int BlockHeightC;</div><div class='add'>+	unsigned int InterlaceEnable;</div><div class='add'>+	unsigned int NumberOfCursors;</div><div class='add'>+	unsigned int VBlank;</div><div class='add'>+	unsigned int HTotal;</div><div class='add'>+	unsigned int HActive;</div><div class='add'>+	bool DCCEnable;</div><div class='add'>+	enum dml2_odm_mode ODMMode;</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat;</div><div class='add'>+	enum dml2_swizzle_mode SurfaceTiling;</div><div class='add'>+	unsigned int BytePerPixelY;</div><div class='add'>+	unsigned int BytePerPixelC;</div><div class='add'>+	bool ProgressiveToInterlaceUnitInOPP;</div><div class='add'>+	double VRatio;</div><div class='add'>+	double VRatioChroma;</div><div class='add'>+	unsigned int VTaps;</div><div class='add'>+	unsigned int VTapsChroma;</div><div class='add'>+	unsigned int PitchY;</div><div class='add'>+	unsigned int PitchC;</div><div class='add'>+	bool ViewportStationary;</div><div class='add'>+	unsigned int ViewportXStart;</div><div class='add'>+	unsigned int ViewportYStart;</div><div class='add'>+	unsigned int ViewportXStartC;</div><div class='add'>+	unsigned int ViewportYStartC;</div><div class='add'>+	bool FORCE_ONE_ROW_FOR_FRAME;</div><div class='add'>+	unsigned int SwathHeightY;</div><div class='add'>+	unsigned int SwathHeightC;</div><div class='add'>+</div><div class='add'>+	unsigned int DCCMetaPitchY;</div><div class='add'>+	unsigned int DCCMetaPitchC;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_core_internal_request_type {</div><div class='add'>+	dml2_core_internal_request_type_256_bytes = 0,</div><div class='add'>+	dml2_core_internal_request_type_128_bytes_non_contiguous = 1,</div><div class='add'>+	dml2_core_internal_request_type_128_bytes_contiguous = 2,</div><div class='add'>+	dml2_core_internal_request_type_na = 3</div><div class='add'>+};</div><div class='add'>+enum dml2_core_internal_bw_type {</div><div class='add'>+	dml2_core_internal_bw_sdp = 0,</div><div class='add'>+	dml2_core_internal_bw_dram = 1,</div><div class='add'>+	dml2_core_internal_bw_max</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_core_internal_soc_state_type {</div><div class='add'>+	dml2_core_internal_soc_state_sys_active = 0,</div><div class='add'>+	dml2_core_internal_soc_state_svp_prefetch = 1,</div><div class='add'>+	dml2_core_internal_soc_state_sys_idle = 2,</div><div class='add'>+	dml2_core_internal_soc_state_max</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_core_internal_output_type {</div><div class='add'>+	dml2_core_internal_output_type_unknown = 0,</div><div class='add'>+	dml2_core_internal_output_type_dp = 1,</div><div class='add'>+	dml2_core_internal_output_type_edp = 2,</div><div class='add'>+	dml2_core_internal_output_type_dp2p0 = 3,</div><div class='add'>+	dml2_core_internal_output_type_hdmi = 4,</div><div class='add'>+	dml2_core_internal_output_type_hdmifrl = 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dml2_core_internal_output_type_rate {</div><div class='add'>+	dml2_core_internal_output_rate_unknown = 0,</div><div class='add'>+	dml2_core_internal_output_rate_dp_rate_hbr = 1,</div><div class='add'>+	dml2_core_internal_output_rate_dp_rate_hbr2 = 2,</div><div class='add'>+	dml2_core_internal_output_rate_dp_rate_hbr3 = 3,</div><div class='add'>+	dml2_core_internal_output_rate_dp_rate_uhbr10 = 4,</div><div class='add'>+	dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5,</div><div class='add'>+	dml2_core_internal_output_rate_dp_rate_uhbr20 = 6,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_3x3 = 7,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_6x3 = 8,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_6x4 = 9,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_8x4 = 10,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_10x4 = 11,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_12x4 = 12,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_16x4 = 13,</div><div class='add'>+	dml2_core_internal_output_rate_hdmi_rate_20x4 = 14</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_watermarks {</div><div class='add'>+	double UrgentWatermark;</div><div class='add'>+	double WritebackUrgentWatermark;</div><div class='add'>+	double DRAMClockChangeWatermark;</div><div class='add'>+	double FCLKChangeWatermark;</div><div class='add'>+	double WritebackDRAMClockChangeWatermark;</div><div class='add'>+	double WritebackFCLKChangeWatermark;</div><div class='add'>+	double StutterExitWatermark;</div><div class='add'>+	double StutterEnterPlusExitWatermark;</div><div class='add'>+	double LowPowerStutterExitWatermark;</div><div class='add'>+	double LowPowerStutterEnterPlusExitWatermark;</div><div class='add'>+	double Z8StutterExitWatermark;</div><div class='add'>+	double Z8StutterEnterPlusExitWatermark;</div><div class='add'>+	double USRRetrainingWatermark;</div><div class='add'>+	double temp_read_or_ppt_watermark_us;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_mode_support_info {</div><div class='add'>+	//-----------------</div><div class='add'>+	// Mode Support Information</div><div class='add'>+	//-----------------</div><div class='add'>+	bool ImmediateFlipSupport; //&lt;brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming</div><div class='add'>+</div><div class='add'>+	// Mode Support Reason/</div><div class='add'>+	bool WritebackLatencySupport;</div><div class='add'>+	bool ScaleRatioAndTapsSupport;</div><div class='add'>+	bool SourceFormatPixelAndScanSupport;</div><div class='add'>+	bool P2IWith420;</div><div class='add'>+	bool DSCSlicesODMModeSupported;</div><div class='add'>+	bool DSCOnlyIfNecessaryWithBPP;</div><div class='add'>+	bool DSC422NativeNotSupported;</div><div class='add'>+	bool LinkRateDoesNotMatchDPVersion;</div><div class='add'>+	bool LinkRateForMultistreamNotIndicated;</div><div class='add'>+	bool BPPForMultistreamNotIndicated;</div><div class='add'>+	bool MultistreamWithHDMIOreDP;</div><div class='add'>+	bool MSOOrODMSplitWithNonDPLink;</div><div class='add'>+	bool NotEnoughLanesForMSO;</div><div class='add'>+	bool NumberOfOTGSupport;</div><div class='add'>+	bool NumberOfTDLUT33cubeSupport;</div><div class='add'>+	bool NumberOfHDMIFRLSupport;</div><div class='add'>+	bool NumberOfDP2p0Support;</div><div class='add'>+	bool WritebackScaleRatioAndTapsSupport;</div><div class='add'>+	bool CursorSupport;</div><div class='add'>+	bool PitchSupport;</div><div class='add'>+	bool ViewportExceedsSurface;</div><div class='add'>+	//bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;</div><div class='add'>+	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;</div><div class='add'>+	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;</div><div class='add'>+	bool InvalidCombinationOfMALLUseForPState;</div><div class='add'>+	bool ExceededMALLSize;</div><div class='add'>+	bool EnoughWritebackUnits;</div><div class='add'>+</div><div class='add'>+	bool ExceededMultistreamSlots;</div><div class='add'>+	bool NotEnoughDSCUnits;</div><div class='add'>+	bool NotEnoughDSCSlices;</div><div class='add'>+	bool PixelsPerLinePerDSCUnitSupport;</div><div class='add'>+	bool DSCCLKRequiredMoreThanSupported;</div><div class='add'>+	bool DTBCLKRequiredMoreThanSupported;</div><div class='add'>+	bool LinkCapacitySupport;</div><div class='add'>+</div><div class='add'>+	bool ROBSupport;</div><div class='add'>+	bool OutstandingRequestsSupport;</div><div class='add'>+	bool OutstandingRequestsUrgencyAvoidance;</div><div class='add'>+</div><div class='add'>+	bool PTEBufferSizeNotExceeded;</div><div class='add'>+	bool DCCMetaBufferSizeNotExceeded;</div><div class='add'>+	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES];</div><div class='add'>+	bool global_dram_clock_change_support_required;</div><div class='add'>+	bool global_dram_clock_change_supported;</div><div class='add'>+	bool global_fclk_change_supported;</div><div class='add'>+	bool global_temp_read_or_ppt_supported;</div><div class='add'>+	bool USRRetrainingSupport;</div><div class='add'>+	bool AvgBandwidthSupport;</div><div class='add'>+	bool UrgVactiveBandwidthSupport;</div><div class='add'>+	bool EnoughUrgentLatencyHidingSupport;</div><div class='add'>+	bool PrefetchScheduleSupported;</div><div class='add'>+	bool PrefetchSupported;</div><div class='add'>+	bool PrefetchBandwidthSupported;</div><div class='add'>+	bool DynamicMetadataSupported;</div><div class='add'>+	bool VRatioInPrefetchSupported;</div><div class='add'>+	bool DISPCLK_DPPCLK_Support;</div><div class='add'>+	bool TotalAvailablePipesSupport;</div><div class='add'>+	bool ODMSupport;</div><div class='add'>+	bool ModeSupport;</div><div class='add'>+	bool ViewportSizeSupport;</div><div class='add'>+</div><div class='add'>+	bool MPCCombineEnable[DML2_MAX_PLANES]; /// &lt;brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting</div><div class='add'>+	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// &lt;brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage</div><div class='add'>+	unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// &lt;brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.</div><div class='add'>+	bool DSCEnabled[DML2_MAX_PLANES]; /// &lt;brief Indicate if the DSC is actually required; used in mode_programming</div><div class='add'>+	bool FECEnabled[DML2_MAX_PLANES]; /// &lt;brief Indicate if the FEC is actually required</div><div class='add'>+	unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// &lt;brief Indicate how many slices needed to support the given mode</div><div class='add'>+</div><div class='add'>+	double OutputBpp[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int AlignedYPitch[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int AlignedCPitch[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int request_size_bytes_luma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];</div><div class='add'>+	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation</div><div class='add'>+	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM</div><div class='add'>+	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc.</div><div class='add'>+	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc.</div><div class='add'>+</div><div class='add'>+	double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor</div><div class='add'>+	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor</div><div class='add'>+	double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw</div><div class='add'>+	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip</div><div class='add'>+</div><div class='add'>+	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor</div><div class='add'>+	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double max_urgent_latency_us;</div><div class='add'>+	double max_non_urgent_latency_us;</div><div class='add'>+	double avg_non_urgent_latency_us;</div><div class='add'>+	double avg_urgent_latency_us;</div><div class='add'>+	double df_response_time_us;</div><div class='add'>+</div><div class='add'>+	bool incorrect_imall_usage;</div><div class='add'>+</div><div class='add'>+	bool g6_temp_read_support;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_internal_watermarks watermarks;</div><div class='add'>+	bool dcfclk_support;</div><div class='add'>+	bool qos_bandwidth_support;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_mode_support {</div><div class='add'>+	// Physical info; only using for programming</div><div class='add'>+	unsigned int state_idx; // &lt;brief min clk state table index for mode support call</div><div class='add'>+	unsigned int qos_param_index; // to access the uclk dependent qos_parameters table</div><div class='add'>+	unsigned int active_min_uclk_dpm_index; // to access the min_clk table</div><div class='add'>+	unsigned int num_active_planes; // &lt;brief As determined by either e2e_pipe_param or display_cfg</div><div class='add'>+</div><div class='add'>+	// Calculated Clocks</div><div class='add'>+	double RequiredDISPCLK; /// &lt;brief Required DISPCLK; depends on pixel rate; odm mode etc.</div><div class='add'>+	double RequiredDPPCLK[DML2_MAX_PLANES];</div><div class='add'>+	double RequiredDISPCLKPerSurface[DML2_MAX_PLANES];</div><div class='add'>+	double RequiredDTBCLK[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double required_dscclk_freq_mhz[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double FabricClock; /// &lt;brief Basically just the clock freq at the min (or given) state</div><div class='add'>+	double SOCCLK; /// &lt;brief Basically just the clock freq at the min (or given) state</div><div class='add'>+	double DCFCLK; /// &lt;brief Basically just the clock freq at the min (or given) state and max combine setting</div><div class='add'>+	double GlobalDPPCLK; /// &lt;brief the Max DPPCLK freq out of all pipes</div><div class='add'>+	double GlobalDTBCLK; /// &lt;brief the Max DTBCLK freq out of all pipes</div><div class='add'>+	double uclk_freq_mhz;</div><div class='add'>+	double dram_bw_mbps;</div><div class='add'>+	double max_dram_bw_mbps;</div><div class='add'>+	double min_available_urgent_bandwidth_MBps; /// &lt;brief Minimum guaranteed available urgent return bandwidth in MBps</div><div class='add'>+</div><div class='add'>+	double MaxFabricClock; /// &lt;brief Basically just the clock freq at the min (or given) state</div><div class='add'>+	double MaxDCFCLK; /// &lt;brief Basically just the clock freq at the min (or given) state and max combine setting</div><div class='add'>+	double max_dispclk_freq_mhz;</div><div class='add'>+	double max_dppclk_freq_mhz;</div><div class='add'>+	double max_dscclk_freq_mhz;</div><div class='add'>+</div><div class='add'>+	bool NoTimeForPrefetch[DML2_MAX_PLANES];</div><div class='add'>+	bool NoTimeForDynamicMetadata[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// ----------------------------------</div><div class='add'>+	// Mode Support Info and fail reason</div><div class='add'>+	// ----------------------------------</div><div class='add'>+	struct dml2_core_internal_mode_support_info support;</div><div class='add'>+</div><div class='add'>+	// These are calculated before the ModeSupport and ModeProgram step</div><div class='add'>+	// They represent the bound for the return buffer sizing</div><div class='add'>+	unsigned int MaxTotalDETInKByte;</div><div class='add'>+	unsigned int NomDETInKByte;</div><div class='add'>+	unsigned int MinCompressedBufferSizeInKByte;</div><div class='add'>+</div><div class='add'>+	// Info obtained at the end of mode support calculations</div><div class='add'>+	// The reported info is at the "optimal" state and combine setting</div><div class='add'>+	unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // &lt;brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.</div><div class='add'>+	unsigned int DETBufferSizeY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DETBufferSizeC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe</div><div class='add'>+	unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe</div><div class='add'>+</div><div class='add'>+	// ----------------------------------</div><div class='add'>+	// Intermediates/Informational</div><div class='add'>+	// ----------------------------------</div><div class='add'>+	unsigned int TotImmediateFlipBytes;</div><div class='add'>+	bool DCCEnabledInAnySurface;</div><div class='add'>+	double WritebackRequiredDISPCLK;</div><div class='add'>+	double TimeCalc;</div><div class='add'>+	double TWait[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool UnboundedRequestEnabled;</div><div class='add'>+	unsigned int compbuf_reserved_space_64b;</div><div class='add'>+	bool hw_debug5;</div><div class='add'>+	unsigned int CompressedBufferSizeInkByte;</div><div class='add'>+	double VRatioPreY[DML2_MAX_PLANES];</div><div class='add'>+	double VRatioPreC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int req_per_swath_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int req_per_swath_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int swath_width_luma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int RequiredSlots[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vm_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DPTEBytesPerRow[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PrefetchLinesY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PrefetchLinesC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// &lt;brief Max number of swath for prefetch</div><div class='add'>+	unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// &lt;brief Max number of swath for prefetch</div><div class='add'>+	unsigned int PrefillY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PrefillC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool use_one_row_for_frame[DML2_MAX_PLANES];</div><div class='add'>+	bool use_one_row_for_frame_flip[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double dst_y_prefetch[DML2_MAX_PLANES];</div><div class='add'>+	double LinesForVM[DML2_MAX_PLANES];</div><div class='add'>+	double LinesForDPTERow[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthYSingleDPP[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthCSingleDPP[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int BytePerPixelY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int BytePerPixelC[DML2_MAX_PLANES];</div><div class='add'>+	double BytePerPixelInDETY[DML2_MAX_PLANES];</div><div class='add'>+	double BytePerPixelInDETC[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int Read256BlockHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int Read256BlockWidthY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int Read256BlockHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int Read256BlockWidthC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileWidthY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileWidthC[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool surf_linear128_l[DML2_MAX_PLANES];</div><div class='add'>+	bool surf_linear128_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double PSCL_FACTOR[DML2_MAX_PLANES];</div><div class='add'>+	double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES];</div><div class='add'>+	double MaximumSwathWidthLuma[DML2_MAX_PLANES];</div><div class='add'>+	double MaximumSwathWidthChroma[DML2_MAX_PLANES];</div><div class='add'>+	double Tno_bw[DML2_MAX_PLANES];</div><div class='add'>+	double Tno_bw_flip[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_per_vm_flip[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_per_row_flip[DML2_MAX_PLANES];</div><div class='add'>+	double WritebackDelayTime[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_group_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+	double UrgLatency;</div><div class='add'>+	double TripToMemory;</div><div class='add'>+	double UrgentBurstFactorCursor[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorLuma[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorChroma[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];</div><div class='add'>+	double MaximumSwathWidthInLineBufferLuma;</div><div class='add'>+	double MaximumSwathWidthInLineBufferChroma;</div><div class='add'>+	double ExtraLatency;</div><div class='add'>+	double ExtraLatency_sr;</div><div class='add'>+	double ExtraLatencyPrefetch;</div><div class='add'>+</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];</div><div class='add'>+	double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta</div><div class='add'>+	double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];</div><div class='add'>+	double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe</div><div class='add'>+	double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool is_using_mall_for_ss[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_width_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES];</div><div class='add'>+	bool PTE_BUFFER_MODE[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_width[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_width[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_linear[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PTERequestSizeY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PTERequestSizeC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_height[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_width_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vm_group_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VReadyOffsetPix[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VUpdateWidthPix[DML2_MAX_PLANES];</div><div class='add'>+	double TSetup[DML2_MAX_PLANES];</div><div class='add'>+	double Tdmdl_vm_raw[DML2_MAX_PLANES];</div><div class='add'>+	double Tdmdl_raw[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VStartupMin[DML2_MAX_PLANES]; /// &lt;brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.</div><div class='add'>+	double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];</div><div class='add'>+	double MaxActiveFCLKChangeLatencySupported;</div><div class='add'>+</div><div class='add'>+	// Backend</div><div class='add'>+	bool RequiresDSC[DML2_MAX_PLANES];</div><div class='add'>+	bool RequiresFEC[DML2_MAX_PLANES];</div><div class='add'>+	double OutputBpp[DML2_MAX_PLANES];</div><div class='add'>+	double DesiredOutputBpp[DML2_MAX_PLANES];</div><div class='add'>+	double PixelClockBackEnd[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSCDelay[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];</div><div class='add'>+	bool TotalAvailablePipesSupportNoDSC;</div><div class='add'>+	bool TotalAvailablePipesSupportDSC;</div><div class='add'>+	unsigned int NumberOfDPPNoDSC;</div><div class='add'>+	unsigned int NumberOfDPPDSC;</div><div class='add'>+	enum dml2_odm_mode ODMModeNoDSC;</div><div class='add'>+	enum dml2_odm_mode ODMModeDSC;</div><div class='add'>+	double RequiredDISPCLKPerSurfaceNoDSC;</div><div class='add'>+	double RequiredDISPCLKPerSurfaceDSC;</div><div class='add'>+	unsigned int EstimatedNumberOfDSCSlices[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Bandwidth Related Info</div><div class='add'>+	double BandwidthAvailableForImmediateFlip;</div><div class='add'>+	double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane</div><div class='add'>+	double vactive_sw_bw_c[DML2_MAX_PLANES];</div><div class='add'>+	double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK];</div><div class='add'>+	double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];</div><div class='add'>+	double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];</div><div class='add'>+	/* Max bandwidth calculated from prefetch schedule should be considered in addition to the pixel data bw to avoid ms/mp mismatches.</div><div class='add'>+	 * 1. oto bw should also be considered when calculating peak urgent bw to avoid situations oto/equ mismatches between ms and mp</div><div class='add'>+	 *</div><div class='add'>+	 * 2. equ bandwidth needs to be considered for calculating peak urgent bw when equ schedule is used in mode support.</div><div class='add'>+	 *    Some slight difference in variables may cause the pixel data bandwidth to be higher</div><div class='add'>+	 *    even though overall equ prefetch bandwidths can be lower going from ms to mp</div><div class='add'>+	 */</div><div class='add'>+	double RequiredPrefetchBWMax[DML2_MAX_PLANES];</div><div class='add'>+	double cursor_bw[DML2_MAX_PLANES];</div><div class='add'>+	double prefetch_cursor_bw[DML2_MAX_PLANES];</div><div class='add'>+	double prefetch_vmrow_bw[DML2_MAX_PLANES];</div><div class='add'>+	double final_flip_bw[DML2_MAX_PLANES];</div><div class='add'>+	double meta_row_bw[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes[DML2_MAX_PLANES];</div><div class='add'>+	double dpte_row_bw[DML2_MAX_PLANES];</div><div class='add'>+	double excess_vactive_fill_bw_l[DML2_MAX_PLANES];</div><div class='add'>+	double excess_vactive_fill_bw_c[DML2_MAX_PLANES];</div><div class='add'>+	double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+	double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Something that should be feedback to caller</div><div class='add'>+	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int NoOfDPP[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int NoOfOPP[DML2_MAX_PLANES];</div><div class='add'>+	bool MPCCombine[DML2_MAX_PLANES];</div><div class='add'>+	double dcfclk_deepsleep;</div><div class='add'>+	double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES];</div><div class='add'>+	bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES];</div><div class='add'>+	bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];</div><div class='add'>+	bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];</div><div class='add'>+	bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];</div><div class='add'>+	bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES];</div><div class='add'>+	bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int TotalNumberOfActiveDPP;</div><div class='add'>+	unsigned int TotalNumberOfActiveOPP;</div><div class='add'>+	unsigned int TotalNumberOfSingleDPPSurfaces;</div><div class='add'>+	unsigned int TotalNumberOfDCCActiveDPP;</div><div class='add'>+	unsigned int Total3dlutActive;</div><div class='add'>+</div><div class='add'>+	unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];</div><div class='add'>+	double VActiveLatencyHidingMargin[DML2_MAX_PLANES];</div><div class='add'>+	double VActiveLatencyHidingUs[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MaxVStartupLines[DML2_MAX_PLANES];</div><div class='add'>+	double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int num_mcaches_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];</div><div class='add'>+	unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int num_mcaches_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];</div><div class='add'>+	unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool mall_comb_mcache_l[DML2_MAX_PLANES];</div><div class='add'>+	bool mall_comb_mcache_c[DML2_MAX_PLANES];</div><div class='add'>+	bool lc_comb_mcache[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int vmpg_width_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_width_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int meta_row_height_luma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int MaximumVStartup[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double HostVMInefficiencyFactor;</div><div class='add'>+	double HostVMInefficiencyFactorPrefetch;</div><div class='add'>+</div><div class='add'>+	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_opt_time[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_drain_time[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double Tvm_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/// @brief A mega structure that houses various info for model programming step.</div><div class='add'>+struct dml2_core_internal_mode_program {</div><div class='add'>+	unsigned int qos_param_index; // to access the uclk dependent dpm table</div><div class='add'>+	unsigned int active_min_uclk_dpm_index; // to access the min_clk table</div><div class='add'>+	double FabricClock; /// &lt;brief Basically just the clock freq at the min (or given) state</div><div class='add'>+	//double DCFCLK; /// &lt;brief Basically just the clock freq at the min (or given) state and max combine setting</div><div class='add'>+	double dram_bw_mbps;</div><div class='add'>+	double min_available_urgent_bandwidth_MBps; /// &lt;brief Minimum guaranteed available urgent return bandwidth in MBps</div><div class='add'>+	double uclk_freq_mhz;</div><div class='add'>+	unsigned int NoOfDPP[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	//-------------</div><div class='add'>+	// Intermediate/Informational</div><div class='add'>+	//-------------</div><div class='add'>+	double UrgentLatency;</div><div class='add'>+	double TripToMemory;</div><div class='add'>+	double MetaTripToMemory;</div><div class='add'>+	unsigned int VInitPreFillY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VInitPreFillC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MaxNumSwathY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MaxNumSwathC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double BytePerPixelInDETY[DML2_MAX_PLANES];</div><div class='add'>+	double BytePerPixelInDETC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int BytePerPixelY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int BytePerPixelC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe</div><div class='add'>+	unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe</div><div class='add'>+	unsigned int req_per_swath_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int req_per_swath_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES];</div><div class='add'>+	double vactive_sw_bw_l[DML2_MAX_PLANES];</div><div class='add'>+	double vactive_sw_bw_c[DML2_MAX_PLANES];</div><div class='add'>+	double excess_vactive_fill_bw_l[DML2_MAX_PLANES];</div><div class='add'>+	double excess_vactive_fill_bw_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vm_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES];</div><div class='add'>+	double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];</div><div class='add'>+	double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES];</div><div class='add'>+	double PSCL_THROUGHPUT[DML2_MAX_PLANES];</div><div class='add'>+	double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSCDelay[DML2_MAX_PLANES];</div><div class='add'>+	double DPPCLKUsingSingleDPP[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int Read256BlockHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int Read256BlockWidthY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int Read256BlockHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int Read256BlockWidthC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileWidthY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MacroTileWidthC[DML2_MAX_PLANES];</div><div class='add'>+	double MaximumSwathWidthLuma[DML2_MAX_PLANES];</div><div class='add'>+	double MaximumSwathWidthChroma[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool surf_linear128_l[DML2_MAX_PLANES];</div><div class='add'>+	bool surf_linear128_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES];</div><div class='add'>+	double VRatioPrefetchY[DML2_MAX_PLANES];</div><div class='add'>+	double VRatioPrefetchC[DML2_MAX_PLANES];</div><div class='add'>+	double Tno_bw[DML2_MAX_PLANES];</div><div class='add'>+	double Tno_bw_flip[DML2_MAX_PLANES];</div><div class='add'>+	double final_flip_bw[DML2_MAX_PLANES];</div><div class='add'>+	double prefetch_vmrow_bw[DML2_MAX_PLANES];</div><div class='add'>+	double cursor_bw[DML2_MAX_PLANES];</div><div class='add'>+	double prefetch_cursor_bw[DML2_MAX_PLANES];</div><div class='add'>+	double WritebackDelay[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_linear[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vm_group_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_group_bytes[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double dpte_row_bw[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_tdlut_group[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorCursor[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorLuma[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorChroma[DML2_MAX_PLANES];</div><div class='add'>+	double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double MaximumSwathWidthInLineBufferLuma;</div><div class='add'>+	double MaximumSwathWidthInLineBufferChroma;</div><div class='add'>+</div><div class='add'>+	unsigned int vmpg_width_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_width_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double meta_row_bw[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_width[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_height[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_width[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_height[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_width_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_width_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_req_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int swath_width_luma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PTERequestSizeY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PTERequestSizeC[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double TWait[DML2_MAX_PLANES];</div><div class='add'>+	double Tdmdl_vm_raw[DML2_MAX_PLANES];</div><div class='add'>+	double Tdmdl_vm[DML2_MAX_PLANES];</div><div class='add'>+	double Tdmdl_raw[DML2_MAX_PLANES];</div><div class='add'>+	double Tdmdl[DML2_MAX_PLANES];</div><div class='add'>+	double TSetup[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool UnboundedRequestEnabled;</div><div class='add'>+	unsigned int CompressedBufferSizeInkByte;</div><div class='add'>+	unsigned int compbuf_reserved_space_64b;</div><div class='add'>+	bool hw_debug5;</div><div class='add'>+	unsigned int dcfclk_deep_sleep_hysteresis;</div><div class='add'>+	unsigned int min_return_latency_in_dcfclk;</div><div class='add'>+</div><div class='add'>+	bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];</div><div class='add'>+	bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];</div><div class='add'>+	double ExtraLatency;</div><div class='add'>+	double ExtraLatency_sr;</div><div class='add'>+	double ExtraLatencyPrefetch;</div><div class='add'>+	bool PrefetchAndImmediateFlipSupported;</div><div class='add'>+	double TotalDataReadBandwidth;</div><div class='add'>+	double BandwidthAvailableForImmediateFlip;</div><div class='add'>+	bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool use_one_row_for_frame[DML2_MAX_PLANES];</div><div class='add'>+	bool use_one_row_for_frame_flip[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double TCalc;</div><div class='add'>+	unsigned int TotImmediateFlipBytes;</div><div class='add'>+</div><div class='add'>+	unsigned int MaxTotalDETInKByte;</div><div class='add'>+	unsigned int NomDETInKByte;</div><div class='add'>+	unsigned int MinCompressedBufferSizeInKByte;</div><div class='add'>+	double PixelClockBackEnd[DML2_MAX_PLANES];</div><div class='add'>+	double OutputBpp[DML2_MAX_PLANES];</div><div class='add'>+	bool dsc_enable[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int num_dsc_slices[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// &lt;brief more like vblank for the plane's OTG</div><div class='add'>+	double HostVMInefficiencyFactor;</div><div class='add'>+	double HostVMInefficiencyFactorPrefetch;</div><div class='add'>+	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_opt_time[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_drain_time[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	bool immediate_flip_required; // any pipes need immediate flip</div><div class='add'>+	double SOCCLK; /// &lt;brief Basically just the clock freq at the min (or given) state</div><div class='add'>+	double TotalWRBandwidth;</div><div class='add'>+	double max_urgent_latency_us;</div><div class='add'>+	double df_response_time_us;</div><div class='add'>+</div><div class='add'>+	enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES];</div><div class='add'>+	// -------------------</div><div class='add'>+	// Output</div><div class='add'>+	// -------------------</div><div class='add'>+	unsigned int pipe_plane[DML2_MAX_PLANES]; // &lt;brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe</div><div class='add'>+	unsigned int num_active_pipes;</div><div class='add'>+</div><div class='add'>+	bool NoTimeToPrefetch[DML2_MAX_PLANES]; // &lt;brief Prefetch schedule calculation result</div><div class='add'>+</div><div class='add'>+	// Support</div><div class='add'>+	bool UrgVactiveBandwidthSupport;</div><div class='add'>+	bool PrefetchScheduleSupported;</div><div class='add'>+	bool UrgentBandwidthSupport;</div><div class='add'>+	bool PrefetchModeSupported; // &lt;brief Is the prefetch mode (bandwidth and latency) supported</div><div class='add'>+	bool ImmediateFlipSupported;</div><div class='add'>+	bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];</div><div class='add'>+	bool dcfclk_support;</div><div class='add'>+</div><div class='add'>+	// Clock</div><div class='add'>+	double Dcfclk;</div><div class='add'>+	double Dispclk; // &lt;brief dispclk being used in mode programming</div><div class='add'>+	double Dppclk[DML2_MAX_PLANES]; // &lt;brief dppclk being used in mode programming</div><div class='add'>+	double GlobalDPPCLK;</div><div class='add'>+</div><div class='add'>+	double DSCCLK[DML2_MAX_PLANES]; //&lt; brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now</div><div class='add'>+	double DCFCLKDeepSleep;</div><div class='add'>+</div><div class='add'>+	// ARB reg</div><div class='add'>+	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;</div><div class='add'>+	struct dml2_core_internal_watermarks Watermark;</div><div class='add'>+</div><div class='add'>+	// DCC compression control</div><div class='add'>+	unsigned int request_size_bytes_luma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Stutter Efficiency</div><div class='add'>+	double StutterEfficiency;</div><div class='add'>+	double StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+	unsigned int NumberOfStutterBurstsPerFrame;</div><div class='add'>+	double Z8StutterEfficiency;</div><div class='add'>+	unsigned int Z8NumberOfStutterBurstsPerFrame;</div><div class='add'>+	double Z8StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+	double LowPowerStutterEfficiency;</div><div class='add'>+	double LowPowerStutterEfficiencyNotIncludingVBlank;</div><div class='add'>+	unsigned int LowPowerNumberOfStutterBurstsPerFrame;</div><div class='add'>+	double StutterPeriod;</div><div class='add'>+	double Z8StutterEfficiencyBestCase;</div><div class='add'>+	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;</div><div class='add'>+	double Z8StutterEfficiencyNotIncludingVBlankBestCase;</div><div class='add'>+	double StutterPeriodBestCase;</div><div class='add'>+</div><div class='add'>+	// DLG TTU reg</div><div class='add'>+	double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES];</div><div class='add'>+	bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_prefetch[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_per_vm_vblank[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_per_row_vblank[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_per_vm_flip[DML2_MAX_PLANES];</div><div class='add'>+	double dst_y_per_row_flip[DML2_MAX_PLANES];</div><div class='add'>+	double MinTTUVBlank[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+	double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int CursorDstXOffset[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int CursorDstYOffset[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES];</div><div class='add'>+	double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_pte_group_nom_luma[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_pte_group_nom_chroma[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_pte_group_vblank_luma[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_pte_group_flip_luma[DML2_MAX_PLANES];</div><div class='add'>+	double time_per_pte_group_flip_chroma[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerVMGroupVBlank[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerVMGroupFlip[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerVMRequestVBlank[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerVMRequestFlip[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES];</div><div class='add'>+	double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerMetaChunkNominal[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerMetaChunkVBlank[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerMetaChunkFlip[DML2_MAX_PLANES];</div><div class='add'>+	double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double FractionOfUrgentBandwidth;</div><div class='add'>+	double FractionOfUrgentBandwidthImmediateFlip;</div><div class='add'>+	double FractionOfUrgentBandwidthMALL;</div><div class='add'>+</div><div class='add'>+	// RQ registers</div><div class='add'>+	bool PTE_BUFFER_MODE[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];</div><div class='add'>+	double VActiveLatencyHidingUs[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];</div><div class='add'>+	bool is_using_mall_for_ss[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// OTG</div><div class='add'>+	unsigned int VStartupMin[DML2_MAX_PLANES]; /// &lt;brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.</div><div class='add'>+	unsigned int VStartup[DML2_MAX_PLANES]; /// &lt;brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))</div><div class='add'>+	unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VUpdateWidthPix[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int VReadyOffsetPix[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Latency and Support</div><div class='add'>+	double MaxActiveFCLKChangeLatencySupported;</div><div class='add'>+	bool USRRetrainingSupport;</div><div class='add'>+	bool g6_temp_read_support;</div><div class='add'>+	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES];</div><div class='add'>+	bool global_dram_clock_change_supported;</div><div class='add'>+	bool global_fclk_change_supported;</div><div class='add'>+	bool global_temp_read_or_ppt_supported;</div><div class='add'>+	double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];</div><div class='add'>+	double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];</div><div class='add'>+	double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// buffer sizing</div><div class='add'>+	unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // &lt;brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.</div><div class='add'>+	unsigned int DETBufferSizeY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DETBufferSizeC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathHeightC[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor</div><div class='add'>+	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor</div><div class='add'>+	double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw</div><div class='add'>+	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip</div><div class='add'>+	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor</div><div class='add'>+	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+</div><div class='add'>+	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];</div><div class='add'>+	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM</div><div class='add'>+	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc.</div><div class='add'>+	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc.</div><div class='add'>+</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES];</div><div class='add'>+	double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];</div><div class='add'>+	double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES];</div><div class='add'>+	double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];</div><div class='add'>+	double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES];</div><div class='add'>+	double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int num_mcaches_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];</div><div class='add'>+	unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int num_mcaches_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];</div><div class='add'>+	unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool mall_comb_mcache_l[DML2_MAX_PLANES];</div><div class='add'>+	bool mall_comb_mcache_c[DML2_MAX_PLANES];</div><div class='add'>+	bool lc_comb_mcache[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double impacted_prefetch_margin_us[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_SOCParametersList {</div><div class='add'>+	double UrgentLatency;</div><div class='add'>+	double ExtraLatency_sr;</div><div class='add'>+	double ExtraLatency;</div><div class='add'>+	double WritebackLatency;</div><div class='add'>+	double DRAMClockChangeLatency;</div><div class='add'>+	double FCLKChangeLatency;</div><div class='add'>+	double SRExitTime;</div><div class='add'>+	double SREnterPlusExitTime;</div><div class='add'>+	double SRExitTimeLowPower;</div><div class='add'>+	double SREnterPlusExitTimeLowPower;</div><div class='add'>+	double SRExitZ8Time;</div><div class='add'>+	double SREnterPlusExitZ8Time;</div><div class='add'>+	double USRRetrainingLatency;</div><div class='add'>+	double SMNLatency;</div><div class='add'>+	double g6_temp_read_blackout_us;</div><div class='add'>+	double temp_read_or_ppt_blackout_us;</div><div class='add'>+	double max_urgent_latency_us;</div><div class='add'>+	double df_response_time_us;</div><div class='add'>+	enum dml2_qos_param_type qos_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_mode_support_locals {</div><div class='add'>+	double PixelClockBackEnd[DML2_MAX_PLANES];</div><div class='add'>+	double OutputBpp[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int meta_row_height_luma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	bool dummy_boolean[3];</div><div class='add'>+	unsigned int dummy_integer[3];</div><div class='add'>+	unsigned int dummy_integer_array[36][DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES];</div><div class='add'>+	bool dummy_boolean_array[2][DML2_MAX_PLANES];</div><div class='add'>+	double dummy_single[3];</div><div class='add'>+	double dummy_single_array[DML2_MAX_PLANES];</div><div class='add'>+	struct dml2_core_internal_watermarks dummy_watermark;</div><div class='add'>+	double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int MaximumVStartup[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];</div><div class='add'>+	struct dml2_core_internal_SOCParametersList mSOCParameters;</div><div class='add'>+	struct dml2_core_internal_DmlPipe myPipe;</div><div class='add'>+	struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int TotalNumberOfActiveWriteback;</div><div class='add'>+	unsigned int MaximumSwathWidthSupportLuma;</div><div class='add'>+	unsigned int MaximumSwathWidthSupportChroma;</div><div class='add'>+	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;</div><div class='add'>+	bool MPCCombineMethodAsPossible;</div><div class='add'>+	bool TotalAvailablePipesSupportNoDSC;</div><div class='add'>+	unsigned int NumberOfDPPNoDSC;</div><div class='add'>+	enum dml2_odm_mode ODMModeNoDSC;</div><div class='add'>+	double RequiredDISPCLKPerSurfaceNoDSC;</div><div class='add'>+	bool TotalAvailablePipesSupportDSC;</div><div class='add'>+	unsigned int NumberOfDPPDSC;</div><div class='add'>+	enum dml2_odm_mode ODMModeDSC;</div><div class='add'>+	double RequiredDISPCLKPerSurfaceDSC;</div><div class='add'>+	double BWOfNonCombinedSurfaceOfMaximumBandwidth;</div><div class='add'>+	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;</div><div class='add'>+	unsigned int TotalNumberOfActiveOTG;</div><div class='add'>+	unsigned int TotalNumberOfActiveHDMIFRL;</div><div class='add'>+	unsigned int TotalNumberOfActiveDP2p0;</div><div class='add'>+	unsigned int TotalNumberOfActiveDP2p0Outputs;</div><div class='add'>+	unsigned int TotalSlots;</div><div class='add'>+	unsigned int DSCFormatFactor;</div><div class='add'>+	unsigned int TotalDSCUnitsRequired;</div><div class='add'>+	unsigned int ReorderingBytes;</div><div class='add'>+	bool ImmediateFlipRequired;</div><div class='add'>+	bool FullFrameMALLPStateMethod;</div><div class='add'>+	bool SubViewportMALLPStateMethod;</div><div class='add'>+	bool PhantomPipeMALLPStateMethod;</div><div class='add'>+	bool SubViewportMALLRefreshGreaterThan120Hz;</div><div class='add'>+</div><div class='add'>+	double HostVMInefficiencyFactor;</div><div class='add'>+	double HostVMInefficiencyFactorPrefetch;</div><div class='add'>+	unsigned int MaxVStartup;</div><div class='add'>+	double PixelClockBackEndFactor;</div><div class='add'>+	unsigned int NumDSCUnitRequired;</div><div class='add'>+</div><div class='add'>+	double Tvm_trips[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int vmpg_width_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_width_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_row_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_opt_time[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_drain_time[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes[DML2_MAX_PLANES];</div><div class='add'>+	bool stream_visited[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double prefetch_sw_bytes[DML2_MAX_PLANES];</div><div class='add'>+	double Tpre_rounded[DML2_MAX_PLANES];</div><div class='add'>+	double Tpre_oto[DML2_MAX_PLANES];</div><div class='add'>+	bool recalc_prefetch_schedule;</div><div class='add'>+	bool recalc_prefetch_done;</div><div class='add'>+	double impacted_dst_y_pre[DML2_MAX_PLANES];</div><div class='add'>+	double line_times[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int lb_source_lines_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int lb_source_lines_c[DML2_MAX_PLANES];</div><div class='add'>+	double prefetch_swath_time_us[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_mode_programming_locals {</div><div class='add'>+	double PixelClockBackEnd[DML2_MAX_PLANES];</div><div class='add'>+	double OutputBpp[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int num_active_planes; // &lt;brief As determined by either e2e_pipe_param or display_cfg</div><div class='add'>+	unsigned int MaxTotalDETInKByte;</div><div class='add'>+	unsigned int NomDETInKByte;</div><div class='add'>+	unsigned int MinCompressedBufferSizeInKByte;</div><div class='add'>+	double SOCCLK; /// &lt;brief Basically just the clock freq at the min (or given) state</div><div class='add'>+</div><div class='add'>+	double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];</div><div class='add'>+	double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+	double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dummy_integer_array[4][DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES];</div><div class='add'>+	double dummy_single_array[2][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dummy_long_array[8][DML2_MAX_PLANES];</div><div class='add'>+	bool dummy_boolean_array[2][DML2_MAX_PLANES];</div><div class='add'>+	bool dummy_boolean[2];</div><div class='add'>+	double dummy_single[2];</div><div class='add'>+	struct dml2_core_internal_watermarks dummy_watermark;</div><div class='add'>+</div><div class='add'>+	unsigned int DSCFormatFactor;</div><div class='add'>+	struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int ReorderingBytes;</div><div class='add'>+	double HostVMInefficiencyFactor;</div><div class='add'>+	double HostVMInefficiencyFactorPrefetch;</div><div class='add'>+	unsigned int TotalDCCActiveDPP;</div><div class='add'>+	unsigned int TotalActiveDPP;</div><div class='add'>+	unsigned int Total3dlutActive;</div><div class='add'>+	unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// &lt;brief more like vblank for the plane's OTG</div><div class='add'>+	bool immediate_flip_required; // any pipes need immediate flip</div><div class='add'>+	bool DestinationLineTimesForPrefetchLessThan2;</div><div class='add'>+	bool VRatioPrefetchMoreThanMax;</div><div class='add'>+	double MaxTotalRDBandwidthNotIncludingMALLPrefetch;</div><div class='add'>+	struct dml2_core_internal_SOCParametersList mmSOCParameters;</div><div class='add'>+	double Tvstartup_margin;</div><div class='add'>+	double dlg_vblank_start;</div><div class='add'>+	double LSetup;</div><div class='add'>+	double blank_lines_remaining;</div><div class='add'>+	double WRBandwidth;</div><div class='add'>+	struct dml2_core_internal_DmlPipe myPipe;</div><div class='add'>+	double PixelClockBackEndFactor;</div><div class='add'>+	unsigned int vmpg_width_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_y[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_width_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vmpg_height_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_row_bytes[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_opt_time[DML2_MAX_PLANES];</div><div class='add'>+	double tdlut_drain_time[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int cursor_bytes[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double Tvm_trips[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip[DML2_MAX_PLANES];</div><div class='add'>+	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double prefetch_sw_bytes[DML2_MAX_PLANES];</div><div class='add'>+	double Tpre_rounded[DML2_MAX_PLANES];</div><div class='add'>+	double Tpre_oto[DML2_MAX_PLANES];</div><div class='add'>+	bool recalc_prefetch_schedule;</div><div class='add'>+	double impacted_dst_y_pre[DML2_MAX_PLANES];</div><div class='add'>+	double line_times[DML2_MAX_PLANES];</div><div class='add'>+	enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int lb_source_lines_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int lb_source_lines_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int num_dsc_slices[DML2_MAX_PLANES];</div><div class='add'>+	bool dsc_enable[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals {</div><div class='add'>+	double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES];</div><div class='add'>+	double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES];</div><div class='add'>+	double USRRetrainingLatencyMargin[DML2_MAX_PLANES];</div><div class='add'>+	double g6_temp_read_latency_margin[DML2_MAX_PLANES];</div><div class='add'>+	double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	double EffectiveLBLatencyHidingY;</div><div class='add'>+	double EffectiveLBLatencyHidingC;</div><div class='add'>+	double LinesInDETY[DML2_MAX_PLANES];</div><div class='add'>+	double LinesInDETC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES];</div><div class='add'>+	double FullDETBufferingTimeY;</div><div class='add'>+	double FullDETBufferingTimeC;</div><div class='add'>+	double WritebackDRAMClockChangeLatencyMargin;</div><div class='add'>+	double WritebackFCLKChangeLatencyMargin;</div><div class='add'>+	double WritebackLatencyHiding;</div><div class='add'>+</div><div class='add'>+	unsigned int TotalActiveWriteback;</div><div class='add'>+	unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES];</div><div class='add'>+	double TotalPixelBW;</div><div class='add'>+	double EffectiveDETBufferSizeY;</div><div class='add'>+	double ActiveClockChangeLatencyHidingY;</div><div class='add'>+	double ActiveClockChangeLatencyHidingC;</div><div class='add'>+	double ActiveClockChangeLatencyHiding;</div><div class='add'>+	unsigned int dst_y_pstate;</div><div class='add'>+	unsigned int src_y_pstate_l;</div><div class='add'>+	unsigned int src_y_pstate_c;</div><div class='add'>+	unsigned int src_y_ahead_l;</div><div class='add'>+	unsigned int src_y_ahead_c;</div><div class='add'>+	unsigned int sub_vp_lines_l;</div><div class='add'>+	unsigned int sub_vp_lines_c;</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateVMRowAndSwath_locals {</div><div class='add'>+	unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int vm_bytes_l;</div><div class='add'>+	unsigned int vm_bytes_c;</div><div class='add'>+	unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES];</div><div class='add'>+	bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int HostVMDynamicLevels;</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateVMRowAndSwath_params {</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	unsigned int NumberOfActiveSurfaces;</div><div class='add'>+	struct dml2_core_internal_DmlPipe *myPipe;</div><div class='add'>+	unsigned int *SurfaceSizeInMALL;</div><div class='add'>+	unsigned int PTEBufferSizeInRequestsLuma;</div><div class='add'>+	unsigned int PTEBufferSizeInRequestsChroma;</div><div class='add'>+	unsigned int MALLAllocatedForDCN;</div><div class='add'>+	unsigned int *SwathWidthY;</div><div class='add'>+	unsigned int *SwathWidthC;</div><div class='add'>+	unsigned int HostVMMinPageSize;</div><div class='add'>+	unsigned int DCCMetaBufferSizeBytes;</div><div class='add'>+	bool mrq_present;</div><div class='add'>+	enum dml2_pstate_method *uclk_pstate_switch_modes;</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	bool *PTEBufferSizeNotExceeded;</div><div class='add'>+	bool *DCCMetaBufferSizeNotExceeded;</div><div class='add'>+</div><div class='add'>+	unsigned int *dpte_row_width_luma_ub;</div><div class='add'>+	unsigned int *dpte_row_width_chroma_ub;</div><div class='add'>+	unsigned int *dpte_row_height_luma;</div><div class='add'>+	unsigned int *dpte_row_height_chroma;</div><div class='add'>+	unsigned int *dpte_row_height_linear_luma; // VBA_DELTA</div><div class='add'>+	unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA</div><div class='add'>+</div><div class='add'>+	unsigned int *vm_group_bytes;</div><div class='add'>+	unsigned int *dpte_group_bytes;</div><div class='add'>+	unsigned int *PixelPTEReqWidthY;</div><div class='add'>+	unsigned int *PixelPTEReqHeightY;</div><div class='add'>+	unsigned int *PTERequestSizeY;</div><div class='add'>+	unsigned int *vmpg_width_y;</div><div class='add'>+	unsigned int *vmpg_height_y;</div><div class='add'>+</div><div class='add'>+	unsigned int *PixelPTEReqWidthC;</div><div class='add'>+	unsigned int *PixelPTEReqHeightC;</div><div class='add'>+	unsigned int *PTERequestSizeC;</div><div class='add'>+	unsigned int *vmpg_width_c;</div><div class='add'>+	unsigned int *vmpg_height_c;</div><div class='add'>+</div><div class='add'>+	unsigned int *dpde0_bytes_per_frame_ub_l;</div><div class='add'>+	unsigned int *dpde0_bytes_per_frame_ub_c;</div><div class='add'>+</div><div class='add'>+	unsigned int *PrefetchSourceLinesY;</div><div class='add'>+	unsigned int *PrefetchSourceLinesC;</div><div class='add'>+	unsigned int *VInitPreFillY;</div><div class='add'>+	unsigned int *VInitPreFillC;</div><div class='add'>+	unsigned int *MaxNumSwathY;</div><div class='add'>+	unsigned int *MaxNumSwathC;</div><div class='add'>+	double *dpte_row_bw;</div><div class='add'>+	unsigned int *PixelPTEBytesPerRow;</div><div class='add'>+	unsigned int *dpte_row_bytes_per_row_l;</div><div class='add'>+	unsigned int *dpte_row_bytes_per_row_c;</div><div class='add'>+	unsigned int *vm_bytes;</div><div class='add'>+	bool *use_one_row_for_frame;</div><div class='add'>+	bool *use_one_row_for_frame_flip;</div><div class='add'>+	bool *is_using_mall_for_ss;</div><div class='add'>+	bool *PTE_BUFFER_MODE;</div><div class='add'>+	unsigned int *BIGK_FRAGMENT_SIZE;</div><div class='add'>+</div><div class='add'>+	// MRQ</div><div class='add'>+	unsigned int *meta_req_width_luma;</div><div class='add'>+	unsigned int *meta_req_height_luma;</div><div class='add'>+	unsigned int *meta_row_width_luma;</div><div class='add'>+	unsigned int *meta_row_height_luma;</div><div class='add'>+	unsigned int *meta_pte_bytes_per_frame_ub_l;</div><div class='add'>+</div><div class='add'>+	unsigned int *meta_req_width_chroma;</div><div class='add'>+	unsigned int *meta_req_height_chroma;</div><div class='add'>+	unsigned int *meta_row_width_chroma;</div><div class='add'>+	unsigned int *meta_row_height_chroma;</div><div class='add'>+	unsigned int *meta_pte_bytes_per_frame_ub_c;</div><div class='add'>+	double *meta_row_bw;</div><div class='add'>+	unsigned int *meta_row_bytes;</div><div class='add'>+	unsigned int *meta_row_bytes_per_row_ub_l;</div><div class='add'>+	unsigned int *meta_row_bytes_per_row_ub_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculatePrefetchSchedule_locals {</div><div class='add'>+	bool NoTimeToPrefetch;</div><div class='add'>+	unsigned int DPPCycles;</div><div class='add'>+	unsigned int DISPCLKCycles;</div><div class='add'>+	double DSTTotalPixelsAfterScaler;</div><div class='add'>+	double LineTime;</div><div class='add'>+	double dst_y_prefetch_equ;</div><div class='add'>+	double prefetch_bw_oto;</div><div class='add'>+	double per_pipe_vactive_sw_bw;</div><div class='add'>+	double Tvm_oto;</div><div class='add'>+	double Tr0_oto;</div><div class='add'>+	double Tvm_oto_lines;</div><div class='add'>+	double Tr0_oto_lines;</div><div class='add'>+	double dst_y_prefetch_oto;</div><div class='add'>+	double TimeForFetchingVM;</div><div class='add'>+	double TimeForFetchingRowInVBlank;</div><div class='add'>+	double LinesToRequestPrefetchPixelData;</div><div class='add'>+	unsigned int HostVMDynamicLevelsTrips;</div><div class='add'>+	double trip_to_mem;</div><div class='add'>+	double Tvm_trips_rounded;</div><div class='add'>+	double Tr0_trips_rounded;</div><div class='add'>+	double max_Tsw;</div><div class='add'>+	double Lsw_oto;</div><div class='add'>+	double prefetch_bw_equ;</div><div class='add'>+	double Tvm_equ;</div><div class='add'>+	double Tr0_equ;</div><div class='add'>+	double Tdmbf;</div><div class='add'>+	double Tdmec;</div><div class='add'>+	double Tdmsks;</div><div class='add'>+	double total_row_bytes;</div><div class='add'>+	double prefetch_bw_pr;</div><div class='add'>+	double bytes_pp;</div><div class='add'>+	double dep_bytes;</div><div class='add'>+	double min_Lsw_oto;</div><div class='add'>+	double min_Lsw_equ;</div><div class='add'>+	double Tsw_est1;</div><div class='add'>+	double Tsw_est2;</div><div class='add'>+	double Tsw_est3;</div><div class='add'>+	double prefetch_bw1;</div><div class='add'>+	double prefetch_bw2;</div><div class='add'>+	double prefetch_bw3;</div><div class='add'>+	double prefetch_bw4;</div><div class='add'>+	double dst_y_prefetch_equ_impacted;</div><div class='add'>+</div><div class='add'>+	double TWait_p;</div><div class='add'>+	unsigned int cursor_prefetch_bytes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_calculate_det_buffer_size_params {</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	bool ForceSingleDPP;</div><div class='add'>+	unsigned int NumberOfActiveSurfaces;</div><div class='add'>+	bool UnboundedRequestEnabled;</div><div class='add'>+	unsigned int nomDETInKByte;</div><div class='add'>+	unsigned int MaxTotalDETInKByte;</div><div class='add'>+	unsigned int ConfigReturnBufferSizeInKByte;</div><div class='add'>+	unsigned int MinCompressedBufferSizeInKByte;</div><div class='add'>+	unsigned int ConfigReturnBufferSegmentSizeInkByte;</div><div class='add'>+	unsigned int CompressedBufferSegmentSizeInkByte;</div><div class='add'>+	double *ReadBandwidthLuma;</div><div class='add'>+	double *ReadBandwidthChroma;</div><div class='add'>+	unsigned int *full_swath_bytes_l;</div><div class='add'>+	unsigned int *full_swath_bytes_c;</div><div class='add'>+	unsigned int *swath_time_value_us;</div><div class='add'>+	unsigned int *DPPPerSurface;</div><div class='add'>+	bool TryToAllocateForWriteLatency;</div><div class='add'>+	unsigned int bestEffortMinActiveLatencyHidingUs;</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int *DETBufferSizeInKByte;</div><div class='add'>+	unsigned int *CompressedBufferSizeInkByte;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_calculate_vm_and_row_bytes_params {</div><div class='add'>+	bool ViewportStationary;</div><div class='add'>+	bool DCCEnable;</div><div class='add'>+	unsigned int NumberOfDPPs;</div><div class='add'>+	unsigned int BlockHeight256Bytes;</div><div class='add'>+	unsigned int BlockWidth256Bytes;</div><div class='add'>+	enum dml2_source_format_class SourcePixelFormat;</div><div class='add'>+	unsigned int SurfaceTiling;</div><div class='add'>+	unsigned int BytePerPixel;</div><div class='add'>+	enum dml2_rotation_angle RotationAngle;</div><div class='add'>+	unsigned int SwathWidth; // per pipe</div><div class='add'>+	unsigned int ViewportHeight;</div><div class='add'>+	unsigned int ViewportXStart;</div><div class='add'>+	unsigned int ViewportYStart;</div><div class='add'>+	bool GPUVMEnable;</div><div class='add'>+	unsigned int GPUVMMaxPageTableLevels;</div><div class='add'>+	unsigned int GPUVMMinPageSizeKBytes;</div><div class='add'>+	unsigned int PTEBufferSizeInRequests;</div><div class='add'>+	unsigned int Pitch;</div><div class='add'>+	unsigned int MacroTileWidth;</div><div class='add'>+	unsigned int MacroTileHeight;</div><div class='add'>+	bool is_phantom;</div><div class='add'>+	unsigned int DCCMetaPitch;</div><div class='add'>+	bool mrq_present;</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation</div><div class='add'>+	unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check</div><div class='add'>+	unsigned int *dpte_row_width_ub;</div><div class='add'>+	unsigned int *dpte_row_height;</div><div class='add'>+	unsigned int *dpte_row_height_linear;</div><div class='add'>+	unsigned int *PixelPTEBytesPerRow_one_row_per_frame;</div><div class='add'>+	unsigned int *dpte_row_width_ub_one_row_per_frame;</div><div class='add'>+	unsigned int *dpte_row_height_one_row_per_frame;</div><div class='add'>+	unsigned int *vmpg_width;</div><div class='add'>+	unsigned int *vmpg_height;</div><div class='add'>+	unsigned int *PixelPTEReqWidth;</div><div class='add'>+	unsigned int *PixelPTEReqHeight;</div><div class='add'>+	unsigned int *PTERequestSize;</div><div class='add'>+	unsigned int *dpde0_bytes_per_frame_ub;</div><div class='add'>+</div><div class='add'>+	unsigned int *meta_row_bytes;</div><div class='add'>+	unsigned int *MetaRequestWidth;</div><div class='add'>+	unsigned int *MetaRequestHeight;</div><div class='add'>+	unsigned int *meta_row_width;</div><div class='add'>+	unsigned int *meta_row_height;</div><div class='add'>+	unsigned int *meta_pte_bytes_per_frame_ub;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals {</div><div class='add'>+	unsigned int MaximumSwathHeightY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int MaximumSwathHeightC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int SwathTimeValueUs[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_TruncToValidBPP_locals {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_CalculateDETBufferSize_locals {</div><div class='add'>+	unsigned int DETBufferSizePoolInKByte;</div><div class='add'>+	unsigned int NextDETBufferPieceInKByte;</div><div class='add'>+	unsigned int NextSurfaceToAssignDETPiece;</div><div class='add'>+	double TotalBandwidth;</div><div class='add'>+	double BandwidthOfSurfacesNotAssignedDETPiece;</div><div class='add'>+	unsigned int max_minDET;</div><div class='add'>+	unsigned int minDET;</div><div class='add'>+	unsigned int minDET_pipe;</div><div class='add'>+	unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int TotalPixelRate;</div><div class='add'>+	unsigned int DETBudgetPerStream[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int IdealDETBudget, DeltaDETBudget;</div><div class='add'>+	unsigned int ResidualDETAfterRounding;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_get_urgent_bandwidth_required_locals {</div><div class='add'>+	double required_bandwidth_mbps;</div><div class='add'>+	double required_bandwidth_mbps_this_surface;</div><div class='add'>+	double adj_factor_p0;</div><div class='add'>+	double adj_factor_p1;</div><div class='add'>+	double adj_factor_cur;</div><div class='add'>+	double adj_factor_p0_pre;</div><div class='add'>+	double adj_factor_p1_pre;</div><div class='add'>+	double adj_factor_cur_pre;</div><div class='add'>+	double per_plane_flip_bw[DML2_MAX_PLANES];</div><div class='add'>+	double mall_svp_prefetch_factor;</div><div class='add'>+	double tmp_nom_adj_factor_p0;</div><div class='add'>+	double tmp_nom_adj_factor_p1;</div><div class='add'>+	double tmp_pref_adj_factor_p0;</div><div class='add'>+	double tmp_pref_adj_factor_p1;</div><div class='add'>+	double vm_row_bw;</div><div class='add'>+	double flip_and_active_bw;</div><div class='add'>+	double flip_and_prefetch_bw;</div><div class='add'>+	double flip_and_prefetch_bw_max;</div><div class='add'>+	double active_and_excess_bw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_calculate_peak_bandwidth_required_locals {</div><div class='add'>+	double unity_array[DML2_MAX_PLANES];</div><div class='add'>+	double zero_array[DML2_MAX_PLANES];</div><div class='add'>+	double surface_dummy_bw[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_CalculateFlipSchedule_locals {</div><div class='add'>+	double min_row_time;</div><div class='add'>+	double Tvm_flip;</div><div class='add'>+	double Tr0_flip;</div><div class='add'>+	double ImmediateFlipBW;</div><div class='add'>+	double dpte_row_bytes;</div><div class='add'>+	double min_row_height;</div><div class='add'>+	double min_row_height_chroma;</div><div class='add'>+	double max_flip_time;</div><div class='add'>+	double lb_flip_bw;</div><div class='add'>+	double hvm_scaled_vm_bytes;</div><div class='add'>+	double num_rows;</div><div class='add'>+	double hvm_scaled_row_bytes;</div><div class='add'>+	double hvm_scaled_vm_row_bytes;</div><div class='add'>+	bool dual_plane;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_rq_dlg_get_dlg_reg_locals {</div><div class='add'>+	unsigned int plane_idx;</div><div class='add'>+	unsigned int stream_idx;</div><div class='add'>+	enum dml2_source_format_class source_format;</div><div class='add'>+	const struct dml2_timing_cfg *timing;</div><div class='add'>+	bool dual_plane;</div><div class='add'>+	enum dml2_odm_mode odm_mode;</div><div class='add'>+</div><div class='add'>+	unsigned int htotal;</div><div class='add'>+	unsigned int hactive;</div><div class='add'>+	unsigned int hblank_end;</div><div class='add'>+	unsigned int vblank_end;</div><div class='add'>+	bool interlaced;</div><div class='add'>+	double pclk_freq_in_mhz;</div><div class='add'>+	double refclk_freq_in_mhz;</div><div class='add'>+	double ref_freq_to_pix_freq;</div><div class='add'>+</div><div class='add'>+	unsigned int num_active_pipes;</div><div class='add'>+	unsigned int first_pipe_idx_in_plane;</div><div class='add'>+	unsigned int pipe_idx_in_combine;</div><div class='add'>+	unsigned int odm_combine_factor;</div><div class='add'>+</div><div class='add'>+	double min_ttu_vblank;</div><div class='add'>+	unsigned int min_dst_y_next_start;</div><div class='add'>+</div><div class='add'>+	unsigned int vready_after_vcount0;</div><div class='add'>+</div><div class='add'>+	unsigned int dst_x_after_scaler;</div><div class='add'>+	unsigned int dst_y_after_scaler;</div><div class='add'>+</div><div class='add'>+	double dst_y_prefetch;</div><div class='add'>+	double dst_y_per_vm_vblank;</div><div class='add'>+	double dst_y_per_row_vblank;</div><div class='add'>+	double dst_y_per_vm_flip;</div><div class='add'>+	double dst_y_per_row_flip;</div><div class='add'>+</div><div class='add'>+	double max_dst_y_per_vm_vblank;</div><div class='add'>+	double max_dst_y_per_row_vblank;</div><div class='add'>+</div><div class='add'>+	double vratio_pre_l;</div><div class='add'>+	double vratio_pre_c;</div><div class='add'>+</div><div class='add'>+	double refcyc_per_line_delivery_pre_l;</div><div class='add'>+	double refcyc_per_line_delivery_l;</div><div class='add'>+</div><div class='add'>+	double refcyc_per_line_delivery_pre_c;</div><div class='add'>+	double refcyc_per_line_delivery_c;</div><div class='add'>+</div><div class='add'>+	double refcyc_per_req_delivery_pre_l;</div><div class='add'>+	double refcyc_per_req_delivery_l;</div><div class='add'>+</div><div class='add'>+	double refcyc_per_req_delivery_pre_c;</div><div class='add'>+	double refcyc_per_req_delivery_c;</div><div class='add'>+</div><div class='add'>+	double dst_y_per_pte_row_nom_l;</div><div class='add'>+	double dst_y_per_pte_row_nom_c;</div><div class='add'>+	double refcyc_per_pte_group_nom_l;</div><div class='add'>+	double refcyc_per_pte_group_nom_c;</div><div class='add'>+	double refcyc_per_pte_group_vblank_l;</div><div class='add'>+	double refcyc_per_pte_group_vblank_c;</div><div class='add'>+	double refcyc_per_pte_group_flip_l;</div><div class='add'>+	double refcyc_per_pte_group_flip_c;</div><div class='add'>+	double refcyc_per_tdlut_group;</div><div class='add'>+</div><div class='add'>+	double dst_y_per_meta_row_nom_l;</div><div class='add'>+	double dst_y_per_meta_row_nom_c;</div><div class='add'>+	double refcyc_per_meta_chunk_nom_l;</div><div class='add'>+	double refcyc_per_meta_chunk_nom_c;</div><div class='add'>+	double refcyc_per_meta_chunk_vblank_l;</div><div class='add'>+	double refcyc_per_meta_chunk_vblank_c;</div><div class='add'>+	double refcyc_per_meta_chunk_flip_l;</div><div class='add'>+	double refcyc_per_meta_chunk_flip_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_CalculateMetaAndPTETimes_params {</div><div class='add'>+	struct dml2_core_internal_scratch *scratch;</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	unsigned int NumberOfActiveSurfaces;</div><div class='add'>+	bool *use_one_row_for_frame;</div><div class='add'>+	double *dst_y_per_row_vblank;</div><div class='add'>+	double *dst_y_per_row_flip;</div><div class='add'>+	unsigned int *BytePerPixelY;</div><div class='add'>+	unsigned int *BytePerPixelC;</div><div class='add'>+	unsigned int *dpte_row_height;</div><div class='add'>+	unsigned int *dpte_row_height_chroma;</div><div class='add'>+	unsigned int *dpte_group_bytes;</div><div class='add'>+	unsigned int *PTERequestSizeY;</div><div class='add'>+	unsigned int *PTERequestSizeC;</div><div class='add'>+	unsigned int *PixelPTEReqWidthY;</div><div class='add'>+	unsigned int *PixelPTEReqHeightY;</div><div class='add'>+	unsigned int *PixelPTEReqWidthC;</div><div class='add'>+	unsigned int *PixelPTEReqHeightC;</div><div class='add'>+	unsigned int *dpte_row_width_luma_ub;</div><div class='add'>+	unsigned int *dpte_row_width_chroma_ub;</div><div class='add'>+	unsigned int *tdlut_groups_per_2row_ub;</div><div class='add'>+	bool mrq_present;</div><div class='add'>+	unsigned int MetaChunkSize;</div><div class='add'>+	unsigned int MinMetaChunkSizeBytes;</div><div class='add'>+	unsigned int *meta_row_width;</div><div class='add'>+	unsigned int *meta_row_width_chroma;</div><div class='add'>+	unsigned int *meta_row_height;</div><div class='add'>+	unsigned int *meta_row_height_chroma;</div><div class='add'>+	unsigned int *meta_req_width;</div><div class='add'>+	unsigned int *meta_req_width_chroma;</div><div class='add'>+	unsigned int *meta_req_height;</div><div class='add'>+	unsigned int *meta_req_height_chroma;</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	double *time_per_tdlut_group;</div><div class='add'>+	double *DST_Y_PER_PTE_ROW_NOM_L;</div><div class='add'>+	double *DST_Y_PER_PTE_ROW_NOM_C;</div><div class='add'>+	double *time_per_pte_group_nom_luma;</div><div class='add'>+	double *time_per_pte_group_vblank_luma;</div><div class='add'>+	double *time_per_pte_group_flip_luma;</div><div class='add'>+	double *time_per_pte_group_nom_chroma;</div><div class='add'>+	double *time_per_pte_group_vblank_chroma;</div><div class='add'>+	double *time_per_pte_group_flip_chroma;</div><div class='add'>+</div><div class='add'>+	double *DST_Y_PER_META_ROW_NOM_L;</div><div class='add'>+	double *DST_Y_PER_META_ROW_NOM_C;</div><div class='add'>+</div><div class='add'>+	double *TimePerMetaChunkNominal;</div><div class='add'>+	double *TimePerChromaMetaChunkNominal;</div><div class='add'>+	double *TimePerMetaChunkVBlank;</div><div class='add'>+	double *TimePerChromaMetaChunkVBlank;</div><div class='add'>+	double *TimePerMetaChunkFlip;</div><div class='add'>+	double *TimePerChromaMetaChunkFlip;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params {</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	bool USRRetrainingRequired;</div><div class='add'>+	unsigned int NumberOfActiveSurfaces;</div><div class='add'>+	unsigned int MaxLineBufferLines;</div><div class='add'>+	unsigned int LineBufferSize;</div><div class='add'>+	unsigned int WritebackInterfaceBufferSize;</div><div class='add'>+	double DCFCLK;</div><div class='add'>+	double ReturnBW;</div><div class='add'>+	bool SynchronizeTimings;</div><div class='add'>+	bool SynchronizeDRRDisplaysForUCLKPStateChange;</div><div class='add'>+	unsigned int *dpte_group_bytes;</div><div class='add'>+	struct dml2_core_internal_SOCParametersList mmSOCParameters;</div><div class='add'>+	unsigned int WritebackChunkSize;</div><div class='add'>+	double SOCCLK;</div><div class='add'>+	double DCFClkDeepSleep;</div><div class='add'>+	unsigned int *DETBufferSizeY;</div><div class='add'>+	unsigned int *DETBufferSizeC;</div><div class='add'>+	unsigned int *SwathHeightY;</div><div class='add'>+	unsigned int *SwathHeightC;</div><div class='add'>+	unsigned int *SwathWidthY;</div><div class='add'>+	unsigned int *SwathWidthC;</div><div class='add'>+	unsigned int *DPPPerSurface;</div><div class='add'>+	double *BytePerPixelDETY;</div><div class='add'>+	double *BytePerPixelDETC;</div><div class='add'>+	unsigned int *DSTXAfterScaler;</div><div class='add'>+	unsigned int *DSTYAfterScaler;</div><div class='add'>+	bool UnboundedRequestEnabled;</div><div class='add'>+	unsigned int CompressedBufferSizeInkByte;</div><div class='add'>+	bool max_outstanding_when_urgent_expected;</div><div class='add'>+	unsigned int max_outstanding_requests;</div><div class='add'>+	unsigned int max_request_size_bytes;</div><div class='add'>+	unsigned int *meta_row_height_l;</div><div class='add'>+	unsigned int *meta_row_height_c;</div><div class='add'>+	enum dml2_pstate_method *uclk_pstate_switch_modes;</div><div class='add'>+</div><div class='add'>+	// Output</div><div class='add'>+	struct dml2_core_internal_watermarks *Watermark;</div><div class='add'>+	enum dml2_pstate_change_support *DRAMClockChangeSupport;</div><div class='add'>+	bool *global_dram_clock_change_support_required;</div><div class='add'>+	bool *global_dram_clock_change_supported;</div><div class='add'>+	double *MaxActiveDRAMClockChangeLatencySupported;</div><div class='add'>+	unsigned int *SubViewportLinesNeededInMALL;</div><div class='add'>+	enum dml2_pstate_change_support *FCLKChangeSupport;</div><div class='add'>+	bool *global_fclk_change_supported;</div><div class='add'>+	double *MaxActiveFCLKChangeLatencySupported;</div><div class='add'>+	bool *USRRetrainingSupport;</div><div class='add'>+	double *VActiveLatencyHidingMargin;</div><div class='add'>+	double *VActiveLatencyHidingUs;</div><div class='add'>+	bool *g6_temp_read_support;</div><div class='add'>+	enum dml2_pstate_change_support *temp_read_or_ppt_support;</div><div class='add'>+	bool *global_temp_read_or_ppt_supported;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params {</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	unsigned int ConfigReturnBufferSizeInKByte;</div><div class='add'>+	unsigned int MaxTotalDETInKByte;</div><div class='add'>+	unsigned int MinCompressedBufferSizeInKByte;</div><div class='add'>+	unsigned int rob_buffer_size_kbytes;</div><div class='add'>+	unsigned int pixel_chunk_size_kbytes;</div><div class='add'>+	bool ForceSingleDPP;</div><div class='add'>+	unsigned int NumberOfActiveSurfaces;</div><div class='add'>+	unsigned int nomDETInKByte;</div><div class='add'>+	unsigned int ConfigReturnBufferSegmentSizeInkByte;</div><div class='add'>+	unsigned int CompressedBufferSegmentSizeInkByte;</div><div class='add'>+	double *ReadBandwidthLuma;</div><div class='add'>+	double *ReadBandwidthChroma;</div><div class='add'>+	double *MaximumSwathWidthLuma;</div><div class='add'>+	double *MaximumSwathWidthChroma;</div><div class='add'>+	unsigned int *Read256BytesBlockHeightY;</div><div class='add'>+	unsigned int *Read256BytesBlockHeightC;</div><div class='add'>+	unsigned int *Read256BytesBlockWidthY;</div><div class='add'>+	unsigned int *Read256BytesBlockWidthC;</div><div class='add'>+	bool *surf_linear128_l;</div><div class='add'>+	bool *surf_linear128_c;</div><div class='add'>+	enum dml2_odm_mode *ODMMode;</div><div class='add'>+	unsigned int *BytePerPixY;</div><div class='add'>+	unsigned int *BytePerPixC;</div><div class='add'>+	double *BytePerPixDETY;</div><div class='add'>+	double *BytePerPixDETC;</div><div class='add'>+	unsigned int *DPPPerSurface;</div><div class='add'>+	bool mrq_present;</div><div class='add'>+	unsigned int dummy[2][DML2_MAX_PLANES];</div><div class='add'>+	unsigned int swath_width_luma_ub_single_dpp[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int swath_width_chroma_ub_single_dpp[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	unsigned int *req_per_swath_ub_l;</div><div class='add'>+	unsigned int *req_per_swath_ub_c;</div><div class='add'>+	unsigned int *swath_width_luma_ub;</div><div class='add'>+	unsigned int *swath_width_chroma_ub;</div><div class='add'>+	unsigned int *SwathWidth;</div><div class='add'>+	unsigned int *SwathWidthChroma;</div><div class='add'>+	unsigned int *SwathHeightY;</div><div class='add'>+	unsigned int *SwathHeightC;</div><div class='add'>+	unsigned int *request_size_bytes_luma;</div><div class='add'>+	unsigned int *request_size_bytes_chroma;</div><div class='add'>+	unsigned int *DETBufferSizeInKByte;</div><div class='add'>+	unsigned int *DETBufferSizeY;</div><div class='add'>+	unsigned int *DETBufferSizeC;</div><div class='add'>+	unsigned int *full_swath_bytes_l;</div><div class='add'>+	unsigned int *full_swath_bytes_c;</div><div class='add'>+	unsigned int *full_swath_bytes_single_dpp_l;</div><div class='add'>+	unsigned int *full_swath_bytes_single_dpp_c;</div><div class='add'>+	bool *UnboundedRequestEnabled;</div><div class='add'>+	unsigned int *compbuf_reserved_space_64b;</div><div class='add'>+	unsigned int *CompressedBufferSizeInkByte;</div><div class='add'>+	bool *ViewportSizeSupportPerSurface;</div><div class='add'>+	bool *ViewportSizeSupport;</div><div class='add'>+	bool *hw_debug5;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_shared_calculation_funcs *funcs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateStutterEfficiency_locals {</div><div class='add'>+	double DETBufferingTimeY;</div><div class='add'>+	double SwathWidthYCriticalSurface;</div><div class='add'>+	double SwathHeightYCriticalSurface;</div><div class='add'>+	double VActiveTimeCriticalSurface;</div><div class='add'>+	double FrameTimeCriticalSurface;</div><div class='add'>+	unsigned int BytePerPixelYCriticalSurface;</div><div class='add'>+	unsigned int DETBufferSizeYCriticalSurface;</div><div class='add'>+	double MinTTUVBlankCriticalSurface;</div><div class='add'>+	unsigned int BlockWidth256BytesYCriticalSurface;</div><div class='add'>+	bool SinglePlaneCriticalSurface;</div><div class='add'>+	bool SinglePipeCriticalSurface;</div><div class='add'>+	double TotalCompressedReadBandwidth;</div><div class='add'>+	double TotalRowReadBandwidth;</div><div class='add'>+	double AverageDCCCompressionRate;</div><div class='add'>+	double EffectiveCompressedBufferSize;</div><div class='add'>+	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;</div><div class='add'>+	double StutterBurstTime;</div><div class='add'>+	unsigned int TotalActiveWriteback;</div><div class='add'>+	double LinesInDETY;</div><div class='add'>+	double LinesInDETYRoundedDownToSwath;</div><div class='add'>+	double MaximumEffectiveCompressionLuma;</div><div class='add'>+	double MaximumEffectiveCompressionChroma;</div><div class='add'>+	double TotalZeroSizeRequestReadBandwidth;</div><div class='add'>+	double TotalZeroSizeCompressedReadBandwidth;</div><div class='add'>+	double AverageDCCZeroSizeFraction;</div><div class='add'>+	double AverageZeroSizeCompressionRate;</div><div class='add'>+	bool stream_visited[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculateStutterEfficiency_params {</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	unsigned int CompressedBufferSizeInkByte;</div><div class='add'>+	bool UnboundedRequestEnabled;</div><div class='add'>+	unsigned int MetaFIFOSizeInKEntries;</div><div class='add'>+	unsigned int ZeroSizeBufferEntries;</div><div class='add'>+	unsigned int PixelChunkSizeInKByte;</div><div class='add'>+	unsigned int NumberOfActiveSurfaces;</div><div class='add'>+	unsigned int ROBBufferSizeInKByte;</div><div class='add'>+	double TotalDataReadBandwidth;</div><div class='add'>+	double DCFCLK;</div><div class='add'>+	double ReturnBW;</div><div class='add'>+	unsigned int CompbufReservedSpace64B;</div><div class='add'>+	unsigned int CompbufReservedSpaceZs;</div><div class='add'>+	bool hw_debug5;</div><div class='add'>+	double SRExitTime;</div><div class='add'>+	double SRExitTimeLowPower;</div><div class='add'>+	double SRExitZ8Time;</div><div class='add'>+	bool SynchronizeTimings;</div><div class='add'>+	double StutterEnterPlusExitWatermark;</div><div class='add'>+	double LowPowerStutterEnterPlusExitWatermark;</div><div class='add'>+	double Z8StutterEnterPlusExitWatermark;</div><div class='add'>+	bool ProgressiveToInterlaceUnitInOPP;</div><div class='add'>+	double *MinTTUVBlank;</div><div class='add'>+	unsigned int *DPPPerSurface;</div><div class='add'>+	unsigned int *DETBufferSizeY;</div><div class='add'>+	unsigned int *BytePerPixelY;</div><div class='add'>+	double *BytePerPixelDETY;</div><div class='add'>+	unsigned int *SwathWidthY;</div><div class='add'>+	unsigned int *SwathHeightY;</div><div class='add'>+	unsigned int *SwathHeightC;</div><div class='add'>+	unsigned int *BlockHeight256BytesY;</div><div class='add'>+	unsigned int *BlockWidth256BytesY;</div><div class='add'>+	unsigned int *BlockHeight256BytesC;</div><div class='add'>+	unsigned int *BlockWidth256BytesC;</div><div class='add'>+	unsigned int *DCCYMaxUncompressedBlock;</div><div class='add'>+	unsigned int *DCCCMaxUncompressedBlock;</div><div class='add'>+	double *ReadBandwidthSurfaceLuma;</div><div class='add'>+	double *ReadBandwidthSurfaceChroma;</div><div class='add'>+	double *meta_row_bw;</div><div class='add'>+	double *dpte_row_bw;</div><div class='add'>+	bool rob_alloc_compressed;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	double *StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+	double *StutterEfficiency;</div><div class='add'>+	double *LowPowerStutterEfficiencyNotIncludingVBlank;</div><div class='add'>+	double *LowPowerStutterEfficiency;</div><div class='add'>+	unsigned int *NumberOfStutterBurstsPerFrame;</div><div class='add'>+	unsigned int *LowPowerNumberOfStutterBurstsPerFrame;</div><div class='add'>+	double *Z8StutterEfficiencyNotIncludingVBlank;</div><div class='add'>+	double *Z8StutterEfficiency;</div><div class='add'>+	unsigned int *Z8NumberOfStutterBurstsPerFrame;</div><div class='add'>+	double *StutterPeriod;</div><div class='add'>+	bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CalculatePrefetchSchedule_params {</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	double HostVMInefficiencyFactor;</div><div class='add'>+	struct dml2_core_internal_DmlPipe *myPipe;</div><div class='add'>+	unsigned int DSCDelay;</div><div class='add'>+	double DPPCLKDelaySubtotalPlusCNVCFormater;</div><div class='add'>+	double DPPCLKDelaySCL;</div><div class='add'>+	double DPPCLKDelaySCLLBOnly;</div><div class='add'>+	double DPPCLKDelayCNVCCursor;</div><div class='add'>+	double DISPCLKDelaySubtotal;</div><div class='add'>+	unsigned int DPP_RECOUT_WIDTH;</div><div class='add'>+	enum dml2_output_format_class OutputFormat;</div><div class='add'>+	unsigned int MaxInterDCNTileRepeaters;</div><div class='add'>+	unsigned int VStartup;</div><div class='add'>+	unsigned int HostVMMinPageSize;</div><div class='add'>+	bool DynamicMetadataEnable;</div><div class='add'>+	bool DynamicMetadataVMEnabled;</div><div class='add'>+	unsigned int DynamicMetadataLinesBeforeActiveRequired;</div><div class='add'>+	unsigned int DynamicMetadataTransmittedBytes;</div><div class='add'>+	double UrgentLatency;</div><div class='add'>+	double ExtraLatencyPrefetch;</div><div class='add'>+	double TCalc;</div><div class='add'>+	unsigned int vm_bytes;</div><div class='add'>+	unsigned int PixelPTEBytesPerRow;</div><div class='add'>+	double PrefetchSourceLinesY;</div><div class='add'>+	unsigned int VInitPreFillY;</div><div class='add'>+	unsigned int MaxNumSwathY;</div><div class='add'>+	double PrefetchSourceLinesC;</div><div class='add'>+	unsigned int VInitPreFillC;</div><div class='add'>+	unsigned int MaxNumSwathC;</div><div class='add'>+	unsigned int swath_width_luma_ub;  // per-pipe</div><div class='add'>+	unsigned int swath_width_chroma_ub; // per-pipe</div><div class='add'>+	unsigned int SwathHeightY;</div><div class='add'>+	unsigned int SwathHeightC;</div><div class='add'>+	double TWait;</div><div class='add'>+	double Ttrip;</div><div class='add'>+	double Turg;</div><div class='add'>+	bool setup_for_tdlut;</div><div class='add'>+	unsigned int tdlut_pte_bytes_per_frame;</div><div class='add'>+	unsigned int tdlut_bytes_per_frame;</div><div class='add'>+	double tdlut_opt_time;</div><div class='add'>+	double tdlut_drain_time;</div><div class='add'>+</div><div class='add'>+	unsigned int num_cursors;</div><div class='add'>+	unsigned int cursor_bytes_per_chunk;</div><div class='add'>+	unsigned int cursor_bytes_per_line;</div><div class='add'>+</div><div class='add'>+	// MRQ</div><div class='add'>+	bool dcc_enable;</div><div class='add'>+	bool mrq_present;</div><div class='add'>+	unsigned int meta_row_bytes;</div><div class='add'>+	double mall_prefetch_sdp_overhead_factor;</div><div class='add'>+</div><div class='add'>+	double impacted_dst_y_pre;</div><div class='add'>+	double vactive_sw_bw_l; // per surface bw</div><div class='add'>+	double vactive_sw_bw_c; // per surface bw</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	unsigned int *DSTXAfterScaler;</div><div class='add'>+	unsigned int *DSTYAfterScaler;</div><div class='add'>+	double *dst_y_prefetch;</div><div class='add'>+	double *dst_y_per_vm_vblank;</div><div class='add'>+	double *dst_y_per_row_vblank;</div><div class='add'>+	double *VRatioPrefetchY;</div><div class='add'>+	double *VRatioPrefetchC;</div><div class='add'>+	double *RequiredPrefetchPixelDataBWLuma;</div><div class='add'>+	double *RequiredPrefetchPixelDataBWChroma;</div><div class='add'>+	double *RequiredPrefetchBWMax;</div><div class='add'>+	bool *NotEnoughTimeForDynamicMetadata;</div><div class='add'>+	double *Tno_bw;</div><div class='add'>+	double *Tno_bw_flip;</div><div class='add'>+	double *prefetch_vmrow_bw;</div><div class='add'>+	double *Tdmdl_vm;</div><div class='add'>+	double *Tdmdl;</div><div class='add'>+	double *TSetup;</div><div class='add'>+	double *Tpre_rounded;</div><div class='add'>+	double *Tpre_oto;</div><div class='add'>+	double *Tvm_trips;</div><div class='add'>+	double *Tr0_trips;</div><div class='add'>+	double *Tvm_trips_flip;</div><div class='add'>+	double *Tr0_trips_flip;</div><div class='add'>+	double *Tvm_trips_flip_rounded;</div><div class='add'>+	double *Tr0_trips_flip_rounded;</div><div class='add'>+	unsigned int *VUpdateOffsetPix;</div><div class='add'>+	unsigned int *VUpdateWidthPix;</div><div class='add'>+	unsigned int *VReadyOffsetPix;</div><div class='add'>+	double *prefetch_cursor_bw;</div><div class='add'>+	double *prefetch_sw_bytes;</div><div class='add'>+	double *prefetch_swath_time_us;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params {</div><div class='add'>+	unsigned int num_active_planes;</div><div class='add'>+	enum dml2_source_format_class *pixel_format;</div><div class='add'>+	unsigned int rob_buffer_size_kbytes;</div><div class='add'>+	unsigned int compressed_buffer_size_kbytes;</div><div class='add'>+	unsigned int chunk_bytes_l; // same for all planes</div><div class='add'>+	unsigned int chunk_bytes_c;</div><div class='add'>+	unsigned int *detile_buffer_size_bytes_l;</div><div class='add'>+	unsigned int *detile_buffer_size_bytes_c;</div><div class='add'>+	unsigned int *full_swath_bytes_l;</div><div class='add'>+	unsigned int *full_swath_bytes_c;</div><div class='add'>+	unsigned int *lb_source_lines_l;</div><div class='add'>+	unsigned int *lb_source_lines_c;</div><div class='add'>+	unsigned int *swath_height_l;</div><div class='add'>+	unsigned int *swath_height_c;</div><div class='add'>+	double *prefetch_sw_bytes;</div><div class='add'>+	double *Tpre_rounded;</div><div class='add'>+	double *Tpre_oto;</div><div class='add'>+	double estimated_dcfclk_mhz;</div><div class='add'>+	double estimated_urg_bandwidth_required_mbps;</div><div class='add'>+	double *line_time;</div><div class='add'>+	double *dst_y_prefetch;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	bool *recalc_prefetch_schedule;</div><div class='add'>+	double *impacted_dst_y_pre;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals {</div><div class='add'>+	unsigned int max_Trpd_dcfclk_cycles;</div><div class='add'>+	unsigned int burst_bytes_to_fill_det;</div><div class='add'>+	double time_to_fill_det_us;</div><div class='add'>+	unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES];</div><div class='add'>+	bool prefetch_global_check_passed;</div><div class='add'>+	unsigned int src_swath_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int src_swath_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_calculate_mcache_row_bytes_params {</div><div class='add'>+	unsigned int num_chans;</div><div class='add'>+	unsigned int mem_word_bytes;</div><div class='add'>+	unsigned int mcache_size_bytes;</div><div class='add'>+	unsigned int mcache_line_size_bytes;</div><div class='add'>+	unsigned int gpuvm_enable;</div><div class='add'>+	unsigned int gpuvm_page_size_kbytes;</div><div class='add'>+</div><div class='add'>+	//enum dml_rotation_angle rotation_angle;</div><div class='add'>+	bool surf_vert;</div><div class='add'>+	unsigned int vp_stationary;</div><div class='add'>+	unsigned int tiling_mode;</div><div class='add'>+	bool imall_enable;</div><div class='add'>+</div><div class='add'>+	unsigned int vp_start_x;</div><div class='add'>+	unsigned int vp_start_y;</div><div class='add'>+	unsigned int full_vp_width;</div><div class='add'>+	unsigned int full_vp_height;</div><div class='add'>+	unsigned int blk_width;</div><div class='add'>+	unsigned int blk_height;</div><div class='add'>+	unsigned int vmpg_width;</div><div class='add'>+	unsigned int vmpg_height;</div><div class='add'>+	unsigned int full_swath_bytes;</div><div class='add'>+	unsigned int bytes_per_pixel;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	unsigned int *num_mcaches;</div><div class='add'>+	unsigned int *mcache_row_bytes;</div><div class='add'>+	unsigned int *mcache_row_bytes_per_channel;</div><div class='add'>+	unsigned int *meta_row_width_ub;</div><div class='add'>+	double *dcc_dram_bw_nom_overhead_factor;</div><div class='add'>+	double *dcc_dram_bw_pref_overhead_factor;</div><div class='add'>+	unsigned int *mvmpg_width;</div><div class='add'>+	unsigned int *mvmpg_height;</div><div class='add'>+	unsigned int *full_vp_access_width_mvmpg_aligned;</div><div class='add'>+	unsigned int *mvmpg_per_mcache_lb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_shared_calculate_mcache_setting_locals {</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p;</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p;</div><div class='add'>+</div><div class='add'>+	bool is_dual_plane;</div><div class='add'>+	unsigned int mvmpg_width_l;</div><div class='add'>+	unsigned int mvmpg_height_l;</div><div class='add'>+	unsigned int full_vp_access_width_mvmpg_aligned_l;</div><div class='add'>+	unsigned int mvmpg_per_mcache_lb_l;</div><div class='add'>+	unsigned int meta_row_width_l;</div><div class='add'>+</div><div class='add'>+	unsigned int mvmpg_width_c;</div><div class='add'>+	unsigned int mvmpg_height_c;</div><div class='add'>+	unsigned int full_vp_access_width_mvmpg_aligned_c;</div><div class='add'>+	unsigned int mvmpg_per_mcache_lb_c;</div><div class='add'>+	unsigned int meta_row_width_c;</div><div class='add'>+</div><div class='add'>+	unsigned int lc_comb_last_mcache_size;</div><div class='add'>+	double luma_time_factor;</div><div class='add'>+	double mcache_remainder_l;</div><div class='add'>+	double mcache_remainder_c;</div><div class='add'>+	unsigned int mvmpg_access_width_l;</div><div class='add'>+	unsigned int mvmpg_access_width_c;</div><div class='add'>+	unsigned int avg_mcache_element_size_l;</div><div class='add'>+	unsigned int avg_mcache_element_size_c;</div><div class='add'>+</div><div class='add'>+	unsigned int full_vp_access_width_l;</div><div class='add'>+	unsigned int full_vp_access_width_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_calculate_mcache_setting_params {</div><div class='add'>+	bool dcc_enable;</div><div class='add'>+	unsigned int num_chans;</div><div class='add'>+	unsigned int mem_word_bytes;</div><div class='add'>+	unsigned int mcache_size_bytes;</div><div class='add'>+	unsigned int mcache_line_size_bytes;</div><div class='add'>+	unsigned int gpuvm_enable;</div><div class='add'>+	unsigned int gpuvm_page_size_kbytes;</div><div class='add'>+</div><div class='add'>+	enum dml2_source_format_class source_format;</div><div class='add'>+	bool surf_vert;</div><div class='add'>+	unsigned int vp_stationary;</div><div class='add'>+	unsigned int tiling_mode;</div><div class='add'>+	bool imall_enable;</div><div class='add'>+</div><div class='add'>+	unsigned int vp_start_x_l;</div><div class='add'>+	unsigned int vp_start_y_l;</div><div class='add'>+	unsigned int full_vp_width_l;</div><div class='add'>+	unsigned int full_vp_height_l;</div><div class='add'>+	unsigned int blk_width_l;</div><div class='add'>+	unsigned int blk_height_l;</div><div class='add'>+	unsigned int vmpg_width_l;</div><div class='add'>+	unsigned int vmpg_height_l;</div><div class='add'>+	unsigned int full_swath_bytes_l;</div><div class='add'>+	unsigned int bytes_per_pixel_l;</div><div class='add'>+</div><div class='add'>+	unsigned int vp_start_x_c;</div><div class='add'>+	unsigned int vp_start_y_c;</div><div class='add'>+	unsigned int full_vp_width_c;</div><div class='add'>+	unsigned int full_vp_height_c;</div><div class='add'>+	unsigned int blk_width_c;</div><div class='add'>+	unsigned int blk_height_c;</div><div class='add'>+	unsigned int vmpg_width_c;</div><div class='add'>+	unsigned int vmpg_height_c;</div><div class='add'>+	unsigned int full_swath_bytes_c;</div><div class='add'>+	unsigned int bytes_per_pixel_c;</div><div class='add'>+</div><div class='add'>+	// output</div><div class='add'>+	unsigned int *num_mcaches_l;</div><div class='add'>+	unsigned int *mcache_row_bytes_l;</div><div class='add'>+	unsigned int *mcache_row_bytes_per_channel_l;</div><div class='add'>+	unsigned int *mcache_offsets_l;</div><div class='add'>+	unsigned int *mcache_shift_granularity_l;</div><div class='add'>+	double *dcc_dram_bw_nom_overhead_factor_l;</div><div class='add'>+	double *dcc_dram_bw_pref_overhead_factor_l;</div><div class='add'>+</div><div class='add'>+	unsigned int *num_mcaches_c;</div><div class='add'>+	unsigned int *mcache_row_bytes_c;</div><div class='add'>+	unsigned int *mcache_row_bytes_per_channel_c;</div><div class='add'>+	unsigned int *mcache_offsets_c;</div><div class='add'>+	unsigned int *mcache_shift_granularity_c;</div><div class='add'>+	double *dcc_dram_bw_nom_overhead_factor_c;</div><div class='add'>+	double *dcc_dram_bw_pref_overhead_factor_c;</div><div class='add'>+</div><div class='add'>+	bool *mall_comb_mcache_l;</div><div class='add'>+	bool *mall_comb_mcache_c;</div><div class='add'>+	bool *lc_comb_mcache;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_calculate_tdlut_setting_params {</div><div class='add'>+	// input params</div><div class='add'>+	double dispclk_mhz;</div><div class='add'>+	bool setup_for_tdlut;</div><div class='add'>+	enum dml2_tdlut_width_mode tdlut_width_mode;</div><div class='add'>+	enum dml2_tdlut_addressing_mode tdlut_addressing_mode;</div><div class='add'>+	unsigned int cursor_buffer_size;</div><div class='add'>+	bool gpuvm_enable;</div><div class='add'>+	unsigned int gpuvm_page_size_kbytes;</div><div class='add'>+	bool is_gfx11;</div><div class='add'>+	bool tdlut_mpc_width_flag;</div><div class='add'>+</div><div class='add'>+	// output param</div><div class='add'>+	unsigned int *tdlut_pte_bytes_per_frame;</div><div class='add'>+	unsigned int *tdlut_bytes_per_frame;</div><div class='add'>+	unsigned int *tdlut_groups_per_2row_ub;</div><div class='add'>+	double *tdlut_opt_time;</div><div class='add'>+	double *tdlut_drain_time;</div><div class='add'>+	unsigned int *tdlut_bytes_to_deliver;</div><div class='add'>+	unsigned int *tdlut_bytes_per_group;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_calculate_peak_bandwidth_required_params {</div><div class='add'>+	// output</div><div class='add'>+	double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max];</div><div class='add'>+	double (*urg_bandwidth_required)[dml2_core_internal_bw_max];</div><div class='add'>+	double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max];</div><div class='add'>+	double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max];</div><div class='add'>+	double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+	double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// input</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	bool inc_flip_bw;</div><div class='add'>+	unsigned int num_active_planes;</div><div class='add'>+	unsigned int *num_of_dpp;</div><div class='add'>+	double *dcc_dram_bw_nom_overhead_factor_p0;</div><div class='add'>+	double *dcc_dram_bw_nom_overhead_factor_p1;</div><div class='add'>+	double *dcc_dram_bw_pref_overhead_factor_p0;</div><div class='add'>+	double *dcc_dram_bw_pref_overhead_factor_p1;</div><div class='add'>+	double *mall_prefetch_sdp_overhead_factor;</div><div class='add'>+	double *mall_prefetch_dram_overhead_factor;</div><div class='add'>+	double *surface_read_bandwidth_l;</div><div class='add'>+	double *surface_read_bandwidth_c;</div><div class='add'>+	double *prefetch_bandwidth_l;</div><div class='add'>+	double *prefetch_bandwidth_c;</div><div class='add'>+	double *prefetch_bandwidth_max;</div><div class='add'>+	double *excess_vactive_fill_bw_l;</div><div class='add'>+	double *excess_vactive_fill_bw_c;</div><div class='add'>+	double *cursor_bw;</div><div class='add'>+	double *dpte_row_bw;</div><div class='add'>+	double *meta_row_bw;</div><div class='add'>+	double *prefetch_cursor_bw;</div><div class='add'>+	double *prefetch_vmrow_bw;</div><div class='add'>+	double *flip_bw;</div><div class='add'>+	double *urgent_burst_factor_l;</div><div class='add'>+	double *urgent_burst_factor_c;</div><div class='add'>+	double *urgent_burst_factor_cursor;</div><div class='add'>+	double *urgent_burst_factor_prefetch_l;</div><div class='add'>+	double *urgent_burst_factor_prefetch_c;</div><div class='add'>+	double *urgent_burst_factor_prefetch_cursor;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params {</div><div class='add'>+	/* inputs */</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	bool mrq_present;</div><div class='add'>+	unsigned int num_active_planes;</div><div class='add'>+	unsigned int *num_of_dpp;</div><div class='add'>+	unsigned int *meta_row_height_l;</div><div class='add'>+	unsigned int *meta_row_height_c;</div><div class='add'>+	unsigned int *meta_row_bytes_per_row_ub_l;</div><div class='add'>+	unsigned int *meta_row_bytes_per_row_ub_c;</div><div class='add'>+	unsigned int *dpte_row_height_l;</div><div class='add'>+	unsigned int *dpte_row_height_c;</div><div class='add'>+	unsigned int *dpte_bytes_per_row_l;</div><div class='add'>+	unsigned int *dpte_bytes_per_row_c;</div><div class='add'>+	unsigned int *byte_per_pix_l;</div><div class='add'>+	unsigned int *byte_per_pix_c;</div><div class='add'>+	unsigned int *swath_width_l;</div><div class='add'>+	unsigned int *swath_width_c;</div><div class='add'>+	unsigned int *swath_height_l;</div><div class='add'>+	unsigned int *swath_height_c;</div><div class='add'>+	double latency_to_hide_us[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	/* outputs */</div><div class='add'>+	unsigned int *bytes_required_l;</div><div class='add'>+	unsigned int *bytes_required_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// A list of overridable function pointers in the core</div><div class='add'>+// shared calculation library.</div><div class='add'>+struct dml2_core_shared_calculation_funcs {</div><div class='add'>+	void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_scratch {</div><div class='add'>+	// Scratch space for function locals</div><div class='add'>+	struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals;</div><div class='add'>+	struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals;</div><div class='add'>+	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;</div><div class='add'>+	struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals;</div><div class='add'>+	struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals;</div><div class='add'>+	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals;</div><div class='add'>+	struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals;</div><div class='add'>+	struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals;</div><div class='add'>+	struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals;</div><div class='add'>+	struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals;</div><div class='add'>+	struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals;</div><div class='add'>+	struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals;</div><div class='add'>+	struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals;</div><div class='add'>+	struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals;</div><div class='add'>+</div><div class='add'>+	// Scratch space for function params</div><div class='add'>+	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params;</div><div class='add'>+	struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params;</div><div class='add'>+	struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params;</div><div class='add'>+	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params;</div><div class='add'>+	struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params;</div><div class='add'>+	struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals;</div><div class='add'>+	struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params;</div><div class='add'>+	struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//struct dml2_svp_mode_override;</div><div class='add'>+struct dml2_core_internal_display_mode_lib {</div><div class='add'>+	struct dml2_core_ip_params ip;</div><div class='add'>+	struct dml2_soc_bb soc;</div><div class='add'>+	struct dml2_ip_capabilities ip_caps;</div><div class='add'>+</div><div class='add'>+	//@brief Mode Support and Mode programming struct</div><div class='add'>+	// Used to hold input; intermediate and output of the calculations</div><div class='add'>+	struct dml2_core_internal_mode_support ms; // struct for mode support</div><div class='add'>+	struct dml2_core_internal_mode_program mp; // struct for mode programming</div><div class='add'>+	// Available overridable calculators for core_shared.</div><div class='add'>+	// if null, core_shared will use default calculators.</div><div class='add'>+	struct dml2_core_shared_calculation_funcs funcs;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_internal_scratch scratch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_mode_support_ex {</div><div class='add'>+	struct dml2_core_internal_display_mode_lib *mode_lib;</div><div class='add'>+	const struct dml2_display_cfg *in_display_cfg;</div><div class='add'>+	const struct dml2_mcg_min_clock_table *min_clk_table;</div><div class='add'>+	int min_clk_index;</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+	//unsigned int in_state_index;</div><div class='add'>+	struct dml2_core_internal_mode_support_info *out_evaluation_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct core_display_cfg_support_info;</div><div class='add'>+</div><div class='add'>+struct dml2_core_calcs_mode_programming_ex {</div><div class='add'>+	struct dml2_core_internal_display_mode_lib *mode_lib;</div><div class='add'>+	const struct dml2_display_cfg *in_display_cfg;</div><div class='add'>+	const struct dml2_mcg_min_clock_table *min_clk_table;</div><div class='add'>+	const struct core_display_cfg_support_info *cfg_support_info;</div><div class='add'>+	int min_clk_index;</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+	struct dml2_display_cfg_programming *programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c<br/>new file mode 100644<br/>index 000000000000..b57d0f6ea6a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c</a></div><div class='hunk'>@@ -0,0 +1,788 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_core_utils.h"</div><div class='add'>+</div><div class='add'>+double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder)</div><div class='add'>+{</div><div class='add'>+	*remainder = ((dividend / divisor) - (int)(dividend / divisor) &gt; 0);</div><div class='add'>+	return dividend / divisor;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type)</div><div class='add'>+{</div><div class='add'>+	switch (bw_type) {</div><div class='add'>+	case (dml2_core_internal_bw_sdp):</div><div class='add'>+		return("dml2_core_internal_bw_sdp");</div><div class='add'>+	case (dml2_core_internal_bw_dram):</div><div class='add'>+		return("dml2_core_internal_bw_dram");</div><div class='add'>+	case (dml2_core_internal_bw_max):</div><div class='add'>+		return("dml2_core_internal_bw_max");</div><div class='add'>+	default:</div><div class='add'>+		return("dml2_core_internal_bw_unknown");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_420(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	bool val = false;</div><div class='add'>+</div><div class='add'>+	switch (source_format) {</div><div class='add'>+	case dml2_444_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_32:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_64:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_8:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_10:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_12:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe_alpha:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_422_planar(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	bool val = false;</div><div class='add'>+</div><div class='add'>+	switch (source_format) {</div><div class='add'>+	case dml2_444_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_32:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_64:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe_alpha:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_8:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_10:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_12:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_422_packed(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	bool val = false;</div><div class='add'>+</div><div class='add'>+	switch (source_format) {</div><div class='add'>+	case dml2_444_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_32:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_444_64:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_420_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe_alpha:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_rgbe:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_mono_16:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_8:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_10:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_planar_12:</div><div class='add'>+		val = 0;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_8:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_10:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_422_packed_12:</div><div class='add'>+		val = 1;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)</div><div class='add'>+{</div><div class='add'>+	DML_LOG_VERBOSE("DML: ===================================== \n");</div><div class='add'>+	DML_LOG_VERBOSE("DML: DML_MODE_SUPPORT_INFO_ST\n");</div><div class='add'>+	if (!fail_only || support-&gt;ScaleRatioAndTapsSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ScaleRatioAndTapsSupport = %d\n", support-&gt;ScaleRatioAndTapsSupport);</div><div class='add'>+	if (!fail_only || support-&gt;SourceFormatPixelAndScanSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: SourceFormatPixelAndScanSupport = %d\n", support-&gt;SourceFormatPixelAndScanSupport);</div><div class='add'>+	if (!fail_only || support-&gt;ViewportSizeSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ViewportSizeSupport = %d\n", support-&gt;ViewportSizeSupport);</div><div class='add'>+	if (!fail_only || support-&gt;LinkRateDoesNotMatchDPVersion == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support-&gt;LinkRateDoesNotMatchDPVersion);</div><div class='add'>+	if (!fail_only || support-&gt;LinkRateForMultistreamNotIndicated == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support-&gt;LinkRateForMultistreamNotIndicated);</div><div class='add'>+	if (!fail_only || support-&gt;BPPForMultistreamNotIndicated == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: BPPForMultistreamNotIndicated = %d\n", support-&gt;BPPForMultistreamNotIndicated);</div><div class='add'>+	if (!fail_only || support-&gt;MultistreamWithHDMIOreDP == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: MultistreamWithHDMIOreDP = %d\n", support-&gt;MultistreamWithHDMIOreDP);</div><div class='add'>+	if (!fail_only || support-&gt;ExceededMultistreamSlots == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ExceededMultistreamSlots = %d\n", support-&gt;ExceededMultistreamSlots);</div><div class='add'>+	if (!fail_only || support-&gt;MSOOrODMSplitWithNonDPLink == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support-&gt;MSOOrODMSplitWithNonDPLink);</div><div class='add'>+	if (!fail_only || support-&gt;NotEnoughLanesForMSO == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NotEnoughLanesForMSO = %d\n", support-&gt;NotEnoughLanesForMSO);</div><div class='add'>+	if (!fail_only || support-&gt;P2IWith420 == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: P2IWith420 = %d\n", support-&gt;P2IWith420);</div><div class='add'>+	if (!fail_only || support-&gt;DSC422NativeNotSupported == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DSC422NativeNotSupported = %d\n", support-&gt;DSC422NativeNotSupported);</div><div class='add'>+	if (!fail_only || support-&gt;DSCSlicesODMModeSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DSCSlicesODMModeSupported = %d\n", support-&gt;DSCSlicesODMModeSupported);</div><div class='add'>+	if (!fail_only || support-&gt;NotEnoughDSCUnits == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NotEnoughDSCUnits = %d\n", support-&gt;NotEnoughDSCUnits);</div><div class='add'>+	if (!fail_only || support-&gt;NotEnoughDSCSlices == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NotEnoughDSCSlices = %d\n", support-&gt;NotEnoughDSCSlices);</div><div class='add'>+	if (!fail_only || support-&gt;ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support-&gt;ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);</div><div class='add'>+	if (!fail_only || support-&gt;InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support-&gt;InvalidCombinationOfMALLUseForPStateAndStaticScreen);</div><div class='add'>+	if (!fail_only || support-&gt;DSCCLKRequiredMoreThanSupported == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support-&gt;DSCCLKRequiredMoreThanSupported);</div><div class='add'>+	if (!fail_only || support-&gt;PixelsPerLinePerDSCUnitSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support-&gt;PixelsPerLinePerDSCUnitSupport);</div><div class='add'>+	if (!fail_only || support-&gt;DTBCLKRequiredMoreThanSupported == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support-&gt;DTBCLKRequiredMoreThanSupported);</div><div class='add'>+	if (!fail_only || support-&gt;InvalidCombinationOfMALLUseForPState == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support-&gt;InvalidCombinationOfMALLUseForPState);</div><div class='add'>+	if (!fail_only || support-&gt;ROBSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ROBSupport = %d\n", support-&gt;ROBSupport);</div><div class='add'>+	if (!fail_only || support-&gt;OutstandingRequestsSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: OutstandingRequestsSupport = %d\n", support-&gt;OutstandingRequestsSupport);</div><div class='add'>+	if (!fail_only || support-&gt;OutstandingRequestsUrgencyAvoidance == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support-&gt;OutstandingRequestsUrgencyAvoidance);</div><div class='add'>+	if (!fail_only || support-&gt;DISPCLK_DPPCLK_Support == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DISPCLK_DPPCLK_Support = %d\n", support-&gt;DISPCLK_DPPCLK_Support);</div><div class='add'>+	if (!fail_only || support-&gt;TotalAvailablePipesSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: TotalAvailablePipesSupport = %d\n", support-&gt;TotalAvailablePipesSupport);</div><div class='add'>+	if (!fail_only || support-&gt;NumberOfOTGSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NumberOfOTGSupport = %d\n", support-&gt;NumberOfOTGSupport);</div><div class='add'>+	if (!fail_only || support-&gt;NumberOfHDMIFRLSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NumberOfHDMIFRLSupport = %d\n", support-&gt;NumberOfHDMIFRLSupport);</div><div class='add'>+	if (!fail_only || support-&gt;NumberOfDP2p0Support == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: NumberOfDP2p0Support = %d\n", support-&gt;NumberOfDP2p0Support);</div><div class='add'>+	if (!fail_only || support-&gt;EnoughWritebackUnits == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: EnoughWritebackUnits = %d\n", support-&gt;EnoughWritebackUnits);</div><div class='add'>+	if (!fail_only || support-&gt;WritebackScaleRatioAndTapsSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support-&gt;WritebackScaleRatioAndTapsSupport);</div><div class='add'>+	if (!fail_only || support-&gt;WritebackLatencySupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: WritebackLatencySupport = %d\n", support-&gt;WritebackLatencySupport);</div><div class='add'>+	if (!fail_only || support-&gt;CursorSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: CursorSupport = %d\n", support-&gt;CursorSupport);</div><div class='add'>+	if (!fail_only || support-&gt;PitchSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PitchSupport = %d\n", support-&gt;PitchSupport);</div><div class='add'>+	if (!fail_only || support-&gt;ViewportExceedsSurface == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ViewportExceedsSurface = %d\n", support-&gt;ViewportExceedsSurface);</div><div class='add'>+	if (!fail_only || support-&gt;PrefetchSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PrefetchSupported = %d\n", support-&gt;PrefetchSupported);</div><div class='add'>+	if (!fail_only || support-&gt;EnoughUrgentLatencyHidingSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support-&gt;EnoughUrgentLatencyHidingSupport);</div><div class='add'>+	if (!fail_only || support-&gt;AvgBandwidthSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: AvgBandwidthSupport = %d\n", support-&gt;AvgBandwidthSupport);</div><div class='add'>+	if (!fail_only || support-&gt;DynamicMetadataSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DynamicMetadataSupported = %d\n", support-&gt;DynamicMetadataSupported);</div><div class='add'>+	if (!fail_only || support-&gt;VRatioInPrefetchSupported == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: VRatioInPrefetchSupported = %d\n", support-&gt;VRatioInPrefetchSupported);</div><div class='add'>+	if (!fail_only || support-&gt;PTEBufferSizeNotExceeded == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: PTEBufferSizeNotExceeded = %d\n", support-&gt;PTEBufferSizeNotExceeded);</div><div class='add'>+	if (!fail_only || support-&gt;DCCMetaBufferSizeNotExceeded == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support-&gt;DCCMetaBufferSizeNotExceeded);</div><div class='add'>+	if (!fail_only || support-&gt;ExceededMALLSize == 1)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support-&gt;ExceededMALLSize);</div><div class='add'>+	if (!fail_only || support-&gt;g6_temp_read_support == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support-&gt;g6_temp_read_support);</div><div class='add'>+	if (!fail_only || (support-&gt;global_dram_clock_change_supported == 0 &amp;&amp; support-&gt;global_dram_clock_change_support_required))</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: dram_clock_change_support = %d\n", support-&gt;global_dram_clock_change_supported);</div><div class='add'>+	if (!fail_only || support-&gt;ImmediateFlipSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support-&gt;ImmediateFlipSupport);</div><div class='add'>+	if (!fail_only || support-&gt;LinkCapacitySupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: LinkCapacitySupport = %d\n", support-&gt;LinkCapacitySupport);</div><div class='add'>+</div><div class='add'>+	if (!fail_only || support-&gt;ModeSupport == 0)</div><div class='add'>+		DML_LOG_VERBOSE("DML: support: ModeSupport = %d\n", support-&gt;ModeSupport);</div><div class='add'>+	DML_LOG_VERBOSE("DML: ===================================== \n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type)</div><div class='add'>+{</div><div class='add'>+	switch (dml2_core_internal_soc_state_type) {</div><div class='add'>+	case (dml2_core_internal_soc_state_sys_idle):</div><div class='add'>+		return("dml2_core_internal_soc_state_sys_idle");</div><div class='add'>+	case (dml2_core_internal_soc_state_sys_active):</div><div class='add'>+		return("dml2_core_internal_soc_state_sys_active");</div><div class='add'>+	case (dml2_core_internal_soc_state_svp_prefetch):</div><div class='add'>+		return("dml2_core_internal_soc_state_svp_prefetch");</div><div class='add'>+	case dml2_core_internal_soc_state_max:</div><div class='add'>+	default:</div><div class='add'>+		return("dml2_core_internal_soc_state_unknown");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg)</div><div class='add'>+{</div><div class='add'>+	for (unsigned int k = 0; k &lt; display_cfg-&gt;num_planes; k++) {</div><div class='add'>+		double bpc = (double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.bpc;</div><div class='add'>+		if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {</div><div class='add'>+			switch (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].output.output_format) {</div><div class='add'>+			case dml2_444:</div><div class='add'>+				out_bpp[k] = bpc * 3;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_s422:</div><div class='add'>+				out_bpp[k] = bpc * 2;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_n422:</div><div class='add'>+				out_bpp[k] = bpc * 2;</div><div class='add'>+				break;</div><div class='add'>+			case dml2_420:</div><div class='add'>+			default:</div><div class='add'>+				out_bpp[k] = bpc * 1.5;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else if (display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {</div><div class='add'>+			out_bpp[k] = (double)display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;</div><div class='add'>+		} else {</div><div class='add'>+			out_bpp[k] = 0;</div><div class='add'>+		}</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg-&gt;stream_descriptors[display_cfg-&gt;plane_descriptors[k].stream_index].timing.dsc.enable);</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);</div><div class='add'>+#endif</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up)</div><div class='add'>+{</div><div class='add'>+	unsigned int remainder;</div><div class='add'>+</div><div class='add'>+	if (multiple == 0)</div><div class='add'>+		return num;</div><div class='add'>+</div><div class='add'>+	remainder = num % multiple;</div><div class='add'>+	if (remainder == 0)</div><div class='add'>+		return num;</div><div class='add'>+</div><div class='add'>+	if (up)</div><div class='add'>+		return (num + multiple - remainder);</div><div class='add'>+	else</div><div class='add'>+		return (num - remainder);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_active_pipes = 0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; num_planes; k++) {</div><div class='add'>+		num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info-&gt;plane_support_info[k].dpps_used;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#ifdef __DML_VBA_DEBUG__</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes);</div><div class='add'>+#endif</div><div class='add'>+	return num_active_pipes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane)</div><div class='add'>+{</div><div class='add'>+	unsigned int pipe_idx = 0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int k = 0; k &lt; DML2_MAX_PLANES; ++k) {</div><div class='add'>+		pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (unsigned int plane_idx = 0; plane_idx &lt; DML2_MAX_PLANES; plane_idx++) {</div><div class='add'>+		for (int i = 0; i &lt; cfg_support_info-&gt;plane_support_info[plane_idx].dpps_used; i++) {</div><div class='add'>+			pipe_plane[pipe_idx] = plane_idx;</div><div class='add'>+			pipe_idx++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg)</div><div class='add'>+{</div><div class='add'>+	bool is_phantom = false;</div><div class='add'>+</div><div class='add'>+	if (plane_cfg-&gt;overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe ||</div><div class='add'>+		plane_cfg-&gt;overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return) {</div><div class='add'>+		is_phantom = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return is_phantom;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	if (sw_mode == dml2_sw_linear)</div><div class='add'>+		return 256;</div><div class='add'>+	else if (sw_mode == dml2_sw_256b_2d)</div><div class='add'>+		return 256;</div><div class='add'>+	else if (sw_mode == dml2_sw_4kb_2d)</div><div class='add'>+		return 4096;</div><div class='add'>+	else if (sw_mode == dml2_sw_64kb_2d)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_sw_256kb_2d)</div><div class='add'>+		return 262144;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_linear)</div><div class='add'>+		return 256;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_d)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_d_t)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_d_x)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_64kb_r_x)</div><div class='add'>+		return 65536;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_256kb_d_x)</div><div class='add'>+		return 262144;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_256kb_r_x)</div><div class='add'>+		return 262144;</div><div class='add'>+	else {</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+		return 256;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel)</div><div class='add'>+{</div><div class='add'>+	return (byte_per_pixel != 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode)</div><div class='add'>+{</div><div class='add'>+	return sw_mode == dml2_sw_linear;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan)</div><div class='add'>+{</div><div class='add'>+	bool is_vert = false;</div><div class='add'>+	if (Scan == dml2_rotation_90 || Scan == dml2_rotation_270) {</div><div class='add'>+		is_vert = true;</div><div class='add'>+	} else {</div><div class='add'>+		is_vert = false;</div><div class='add'>+	}</div><div class='add'>+	return is_vert;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode)</div><div class='add'>+{</div><div class='add'>+	int unsigned version = 0;</div><div class='add'>+</div><div class='add'>+	if (sw_mode == dml2_sw_linear ||</div><div class='add'>+		sw_mode == dml2_sw_256b_2d ||</div><div class='add'>+		sw_mode == dml2_sw_4kb_2d ||</div><div class='add'>+		sw_mode == dml2_sw_64kb_2d ||</div><div class='add'>+		sw_mode == dml2_sw_256kb_2d)</div><div class='add'>+		version = 12;</div><div class='add'>+	else if (sw_mode == dml2_gfx11_sw_linear ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_d ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_d_t ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_d_x ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_64kb_r_x ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_256kb_d_x ||</div><div class='add'>+		sw_mode == dml2_gfx11_sw_256kb_r_x)</div><div class='add'>+		version = 11;</div><div class='add'>+	else {</div><div class='add'>+		DML_LOG_VERBOSE("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode);</div><div class='add'>+		DML_ASSERT(0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return version;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned int index = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML_MAX_CLK_TABLE_SIZE; i++) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: per_uclk_dpm_params[%d].minimum_uclk_khz = %ld\n", __func__, i, per_uclk_dpm_params[i].minimum_uclk_khz);</div><div class='add'>+</div><div class='add'>+		if (i == 0)</div><div class='add'>+			index = 0;</div><div class='add'>+		else</div><div class='add'>+			index = i - 1;</div><div class='add'>+</div><div class='add'>+		if (uclk_freq_khz &lt; per_uclk_dpm_params[i].minimum_uclk_khz ||</div><div class='add'>+			per_uclk_dpm_params[i].minimum_uclk_khz == 0) {</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: index = %d\n", __func__, index);</div><div class='add'>+#endif</div><div class='add'>+	return index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool clk_entry_found = false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; clk_table-&gt;uclk.num_clk_values; i++) {</div><div class='add'>+		DML_LOG_VERBOSE("DML::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table-&gt;uclk.clk_values_khz[i]);</div><div class='add'>+</div><div class='add'>+		if (uclk_freq_khz == clk_table-&gt;uclk.clk_values_khz[i]) {</div><div class='add'>+			clk_entry_found = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!clk_entry_found)</div><div class='add'>+		DML_ASSERT(clk_entry_found);</div><div class='add'>+#if defined(__DML_VBA_DEBUG__)</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);</div><div class='add'>+	DML_LOG_VERBOSE("DML::%s: index = %d\n", __func__, i);</div><div class='add'>+#endif</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format)</div><div class='add'>+{</div><div class='add'>+	bool ret_val = false;</div><div class='add'>+</div><div class='add'>+	if (dml2_core_utils_is_420(source_format) || dml2_core_utils_is_422_planar(source_format) || (source_format == dml2_rgbe_alpha))</div><div class='add'>+		ret_val = true;</div><div class='add'>+</div><div class='add'>+	return ret_val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend)</div><div class='add'>+{</div><div class='add'>+	if (a == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return (math_log2_approx(a) - subtrahend);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main,</div><div class='add'>+	const struct dml2_implicit_svp_meta *meta)</div><div class='add'>+{</div><div class='add'>+	memcpy(phantom, main, sizeof(struct dml2_stream_parameters));</div><div class='add'>+</div><div class='add'>+	phantom-&gt;timing.v_total = meta-&gt;v_total;</div><div class='add'>+	phantom-&gt;timing.v_active = meta-&gt;v_active;</div><div class='add'>+	phantom-&gt;timing.v_front_porch = meta-&gt;v_front_porch;</div><div class='add'>+	phantom-&gt;timing.v_blank_end = phantom-&gt;timing.v_total - phantom-&gt;timing.v_front_porch - phantom-&gt;timing.v_active;</div><div class='add'>+	phantom-&gt;timing.vblank_nom = phantom-&gt;timing.v_total - phantom-&gt;timing.v_active;</div><div class='add'>+	phantom-&gt;timing.drr_config.enabled = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void create_phantom_plane_from_main_plane(struct dml2_plane_parameters *phantom, const struct dml2_plane_parameters *main,</div><div class='add'>+	const struct dml2_stream_parameters *phantom_stream, int phantom_stream_index, const struct dml2_stream_parameters *main_stream)</div><div class='add'>+{</div><div class='add'>+	memcpy(phantom, main, sizeof(struct dml2_plane_parameters));</div><div class='add'>+</div><div class='add'>+	phantom-&gt;stream_index = phantom_stream_index;</div><div class='add'>+	phantom-&gt;overrides.refresh_from_mall = dml2_refresh_from_mall_mode_override_force_disable;</div><div class='add'>+	phantom-&gt;overrides.legacy_svp_config = dml2_svp_mode_override_phantom_pipe_no_data_return;</div><div class='add'>+	phantom-&gt;composition.viewport.plane0.height = (long int unsigned) math_min2(math_ceil2(</div><div class='add'>+		(double)main-&gt;composition.scaler_info.plane0.v_ratio * (double)phantom_stream-&gt;timing.v_active, 16.0),</div><div class='add'>+		(double)main-&gt;composition.viewport.plane0.height);</div><div class='add'>+	phantom-&gt;composition.viewport.plane1.height = (long int unsigned) math_min2(math_ceil2(</div><div class='add'>+		(double)main-&gt;composition.scaler_info.plane1.v_ratio * (double)phantom_stream-&gt;timing.v_active, 16.0),</div><div class='add'>+		(double)main-&gt;composition.viewport.plane1.height);</div><div class='add'>+	phantom-&gt;immediate_flip = false;</div><div class='add'>+	phantom-&gt;dynamic_meta_data.enable = false;</div><div class='add'>+	phantom-&gt;cursor.num_cursors = 0;</div><div class='add'>+	phantom-&gt;cursor.cursor_width = 0;</div><div class='add'>+	phantom-&gt;tdlut.setup_for_tdlut = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,</div><div class='add'>+	struct dml2_core_scratch *scratch)</div><div class='add'>+{</div><div class='add'>+	unsigned int stream_index, plane_index;</div><div class='add'>+	const struct dml2_plane_parameters *main_plane;</div><div class='add'>+	const struct dml2_stream_parameters *main_stream;</div><div class='add'>+	const struct dml2_stream_parameters *phantom_stream;</div><div class='add'>+</div><div class='add'>+	memcpy(svp_expanded_display_cfg, &amp;display_cfg-&gt;display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+	memset(scratch-&gt;main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);</div><div class='add'>+	memset(scratch-&gt;svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);</div><div class='add'>+	memset(scratch-&gt;main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);</div><div class='add'>+</div><div class='add'>+	if (!display_cfg-&gt;display_config.overrides.enable_subvp_implicit_pmo)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* disable unbounded requesting for all planes until stage 3 has been performed */</div><div class='add'>+	if (!display_cfg-&gt;stage3.performed) {</div><div class='add'>+		svp_expanded_display_cfg-&gt;overrides.hw.force_unbounded_requesting.enable = true;</div><div class='add'>+		svp_expanded_display_cfg-&gt;overrides.hw.force_unbounded_requesting.value = false;</div><div class='add'>+	}</div><div class='add'>+	// Create the phantom streams</div><div class='add'>+	for (stream_index = 0; stream_index &lt; display_cfg-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		main_stream = &amp;display_cfg-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+		scratch-&gt;main_stream_index_from_svp_stream_index[stream_index] = stream_index;</div><div class='add'>+		scratch-&gt;svp_stream_index_from_main_stream_index[stream_index] = stream_index;</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;stage3.stream_svp_meta[stream_index].valid) {</div><div class='add'>+			// Create the phantom stream</div><div class='add'>+			create_phantom_stream_from_main_stream(&amp;svp_expanded_display_cfg-&gt;stream_descriptors[svp_expanded_display_cfg-&gt;num_streams],</div><div class='add'>+				main_stream, &amp;display_cfg-&gt;stage3.stream_svp_meta[stream_index]);</div><div class='add'>+</div><div class='add'>+			// Associate this phantom stream to the main stream</div><div class='add'>+			scratch-&gt;main_stream_index_from_svp_stream_index[svp_expanded_display_cfg-&gt;num_streams] = stream_index;</div><div class='add'>+			scratch-&gt;svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg-&gt;num_streams;</div><div class='add'>+</div><div class='add'>+			// Increment num streams</div><div class='add'>+			svp_expanded_display_cfg-&gt;num_streams++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Create the phantom planes</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_cfg-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		main_plane = &amp;display_cfg-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+		if (display_cfg-&gt;stage3.stream_svp_meta[main_plane-&gt;stream_index].valid) {</div><div class='add'>+			main_stream = &amp;display_cfg-&gt;display_config.stream_descriptors[main_plane-&gt;stream_index];</div><div class='add'>+			phantom_stream = &amp;svp_expanded_display_cfg-&gt;stream_descriptors[scratch-&gt;svp_stream_index_from_main_stream_index[main_plane-&gt;stream_index]];</div><div class='add'>+			create_phantom_plane_from_main_plane(&amp;svp_expanded_display_cfg-&gt;plane_descriptors[svp_expanded_display_cfg-&gt;num_planes],</div><div class='add'>+				main_plane, phantom_stream, scratch-&gt;svp_stream_index_from_main_stream_index[main_plane-&gt;stream_index], main_stream);</div><div class='add'>+</div><div class='add'>+			// Associate this phantom plane to the main plane</div><div class='add'>+			scratch-&gt;phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg-&gt;num_planes] = plane_index;</div><div class='add'>+			scratch-&gt;main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg-&gt;num_planes;</div><div class='add'>+</div><div class='add'>+			// Increment num planes</div><div class='add'>+			svp_expanded_display_cfg-&gt;num_planes++;</div><div class='add'>+</div><div class='add'>+			// Adjust the main plane settings</div><div class='add'>+			svp_expanded_display_cfg-&gt;plane_descriptors[plane_index].overrides.legacy_svp_config = dml2_svp_mode_override_main_pipe;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor)</div><div class='add'>+{</div><div class='add'>+	switch (stream_descriptor-&gt;output.output_encoder) {</div><div class='add'>+	case dml2_dp:</div><div class='add'>+	case dml2_dp2p0:</div><div class='add'>+	case dml2_edp:</div><div class='add'>+	case dml2_hdmi:</div><div class='add'>+	case dml2_hdmifrl:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_none:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor)</div><div class='add'>+{</div><div class='add'>+	switch (stream_descriptor-&gt;output.output_encoder) {</div><div class='add'>+	case dml2_dp:</div><div class='add'>+	case dml2_dp2p0:</div><div class='add'>+	case dml2_edp:</div><div class='add'>+	case dml2_hdmifrl:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_hdmi:</div><div class='add'>+	case dml2_none:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)</div><div class='add'>+{</div><div class='add'>+	switch (stream_descriptor-&gt;output.output_encoder) {</div><div class='add'>+	case dml2_dp:</div><div class='add'>+	case dml2_edp:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_dp2p0:</div><div class='add'>+	case dml2_hdmi:</div><div class='add'>+	case dml2_hdmifrl:</div><div class='add'>+	case dml2_none:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)</div><div class='add'>+{</div><div class='add'>+	switch (stream_descriptor-&gt;output.output_encoder) {</div><div class='add'>+	case dml2_dp2p0:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_dp:</div><div class='add'>+	case dml2_edp:</div><div class='add'>+	case dml2_hdmi:</div><div class='add'>+	case dml2_hdmifrl:</div><div class='add'>+	case dml2_none:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)</div><div class='add'>+{</div><div class='add'>+	return dml2_core_utils_is_dio_dp_encoder(stream_descriptor)</div><div class='add'>+			|| dml2_core_utils_is_hpo_dp_encoder(stream_descriptor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate)</div><div class='add'>+{</div><div class='add'>+	switch (rate) {</div><div class='add'>+	case dml2_dp_rate_hbr:</div><div class='add'>+	case dml2_dp_rate_hbr2:</div><div class='add'>+	case dml2_dp_rate_hbr3:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_dp_rate_na:</div><div class='add'>+	case dml2_dp_rate_uhbr10:</div><div class='add'>+	case dml2_dp_rate_uhbr13p5:</div><div class='add'>+	case dml2_dp_rate_uhbr20:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate)</div><div class='add'>+{</div><div class='add'>+	switch (rate) {</div><div class='add'>+	case dml2_dp_rate_uhbr10:</div><div class='add'>+	case dml2_dp_rate_uhbr13p5:</div><div class='add'>+	case dml2_dp_rate_uhbr20:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_dp_rate_hbr:</div><div class='add'>+	case dml2_dp_rate_hbr2:</div><div class='add'>+	case dml2_dp_rate_hbr3:</div><div class='add'>+	case dml2_dp_rate_na:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode)</div><div class='add'>+{</div><div class='add'>+	switch (odm_mode) {</div><div class='add'>+	case dml2_odm_mode_split_1to2:</div><div class='add'>+	case dml2_odm_mode_mso_1to2:</div><div class='add'>+	case dml2_odm_mode_mso_1to4:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_odm_mode_auto:</div><div class='add'>+	case dml2_odm_mode_bypass:</div><div class='add'>+	case dml2_odm_mode_combine_2to1:</div><div class='add'>+	case dml2_odm_mode_combine_3to1:</div><div class='add'>+	case dml2_odm_mode_combine_4to1:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h<br/>new file mode 100644<br/>index 000000000000..95f0d017add4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h</a></div><div class='hunk'>@@ -0,0 +1,43 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_CORE_UTILS_H__</div><div class='add'>+#define __DML2_CORE_UTILS_H__</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml2_debug.h"</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+</div><div class='add'>+double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder);</div><div class='add'>+const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type);</div><div class='add'>+bool dml2_core_utils_is_420(enum dml2_source_format_class source_format);</div><div class='add'>+bool dml2_core_utils_is_422_planar(enum dml2_source_format_class source_format);</div><div class='add'>+bool dml2_core_utils_is_422_packed(enum dml2_source_format_class source_format);</div><div class='add'>+void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only);</div><div class='add'>+const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type);</div><div class='add'>+void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);</div><div class='add'>+unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up);</div><div class='add'>+unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info);</div><div class='add'>+void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);</div><div class='add'>+bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg);</div><div class='add'>+unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);</div><div class='add'>+bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel);</div><div class='add'>+bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan);</div><div class='add'>+bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode);</div><div class='add'>+int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode);</div><div class='add'>+unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params);</div><div class='add'>+unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table);</div><div class='add'>+bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format);</div><div class='add'>+unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend);</div><div class='add'>+void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,</div><div class='add'>+	struct dml2_core_scratch *scratch);</div><div class='add'>+bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor);</div><div class='add'>+bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor);</div><div class='add'>+bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);</div><div class='add'>+bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);</div><div class='add'>+bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);</div><div class='add'>+bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate);</div><div class='add'>+bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate);</div><div class='add'>+bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode);</div><div class='add'>+</div><div class='add'>+#endif /* __DML2_CORE_UTILS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c<br/>new file mode 100644<br/>index 000000000000..22969a533a7b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c</a></div><div class='hunk'>@@ -0,0 +1,785 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_dpmm_dcn4.h"</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+</div><div class='add'>+static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config)</div><div class='add'>+{</div><div class='add'>+	double uclk_khz = 0;</div><div class='add'>+	unsigned long uclk_mbytes_per_tick = 0;</div><div class='add'>+</div><div class='add'>+	uclk_mbytes_per_tick = dram_config-&gt;channel_count * dram_config-&gt;channel_width_bytes * dram_config-&gt;transactions_per_clock;</div><div class='add'>+</div><div class='add'>+	uclk_khz = (double)bandwidth_kbps / uclk_mbytes_per_tick;</div><div class='add'>+</div><div class='add'>+	return uclk_khz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void get_minimum_clocks_for_latency(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out,</div><div class='add'>+	double *uclk,</div><div class='add'>+	double *fclk,</div><div class='add'>+	double *dcfclk)</div><div class='add'>+{</div><div class='add'>+	int min_clock_index_for_latency;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;display_cfg-&gt;stage3.success)</div><div class='add'>+		min_clock_index_for_latency = in_out-&gt;display_cfg-&gt;stage3.min_clk_index_for_latency;</div><div class='add'>+	else</div><div class='add'>+		min_clock_index_for_latency = in_out-&gt;display_cfg-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+</div><div class='add'>+	*dcfclk = in_out-&gt;min_clk_table-&gt;dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz;</div><div class='add'>+	*fclk = in_out-&gt;min_clk_table-&gt;dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz;</div><div class='add'>+	*uclk = dram_bw_kbps_to_uclk_khz(in_out-&gt;min_clk_table-&gt;dram_bw_table.entries[min_clock_index_for_latency].pre_derate_dram_bw_kbps,</div><div class='add'>+		&amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned long dml_round_up(double a)</div><div class='add'>+{</div><div class='add'>+	if (a - (unsigned long)a &gt; 0) {</div><div class='add'>+		return ((unsigned long)a) + 1;</div><div class='add'>+	}</div><div class='add'>+	return (unsigned long)a;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_system_active_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	double min_uclk_avg, min_uclk_urgent, min_uclk_bw;</div><div class='add'>+	double min_fclk_avg, min_fclk_urgent, min_fclk_bw;</div><div class='add'>+	double min_dcfclk_avg, min_dcfclk_urgent, min_dcfclk_bw;</div><div class='add'>+	double min_uclk_latency, min_fclk_latency, min_dcfclk_latency;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result = &amp;in_out-&gt;display_cfg-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.active.average_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	min_uclk_avg = (double)min_uclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.active.urgent_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	if (in_out-&gt;display_cfg-&gt;display_config.hostvm_enable)</div><div class='add'>+		min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100);</div><div class='add'>+	else</div><div class='add'>+		min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_uclk_bw = min_uclk_urgent &gt; min_uclk_avg ? min_uclk_urgent : min_uclk_avg;</div><div class='add'>+</div><div class='add'>+	min_fclk_avg = (double)mode_support_result-&gt;global.active.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_avg = (double)min_fclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_average.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_urgent = (double)mode_support_result-&gt;global.active.urgent_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_urgent = (double)min_fclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_bw = min_fclk_urgent &gt; min_fclk_avg ? min_fclk_urgent : min_fclk_avg;</div><div class='add'>+</div><div class='add'>+	min_dcfclk_avg = (double)mode_support_result-&gt;global.active.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_avg = (double)min_dcfclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_average.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_urgent = (double)mode_support_result-&gt;global.active.urgent_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_urgent = (double)min_dcfclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_bw = min_dcfclk_urgent &gt; min_dcfclk_avg ? min_dcfclk_urgent : min_dcfclk_avg;</div><div class='add'>+</div><div class='add'>+	get_minimum_clocks_for_latency(in_out, &amp;min_uclk_latency, &amp;min_fclk_latency, &amp;min_dcfclk_latency);</div><div class='add'>+</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.active.uclk_khz = dml_round_up(min_uclk_bw &gt; min_uclk_latency ? min_uclk_bw : min_uclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.active.fclk_khz = dml_round_up(min_fclk_bw &gt; min_fclk_latency ? min_fclk_bw : min_fclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.active.dcfclk_khz = dml_round_up(min_dcfclk_bw &gt; min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	double min_uclk_avg, min_uclk_urgent, min_uclk_bw;</div><div class='add'>+	double min_fclk_avg, min_fclk_urgent, min_fclk_bw;</div><div class='add'>+	double min_dcfclk_avg, min_dcfclk_urgent, min_dcfclk_bw;</div><div class='add'>+	double min_fclk_latency, min_dcfclk_latency;</div><div class='add'>+	double min_uclk_latency;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result = &amp;in_out-&gt;display_cfg-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	/* assumes DF throttling is enabled */</div><div class='add'>+	min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.svp_prefetch.average_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	min_uclk_avg = (double)min_uclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.svp_prefetch.urgent_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_uclk_bw = min_uclk_urgent &gt; min_uclk_avg ? min_uclk_urgent : min_uclk_avg;</div><div class='add'>+</div><div class='add'>+	min_fclk_avg = (double)mode_support_result-&gt;global.svp_prefetch.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_avg = (double)min_fclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.dcn_mall_prefetch_average.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_urgent = (double)mode_support_result-&gt;global.svp_prefetch.urgent_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_urgent = (double)min_fclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_bw = min_fclk_urgent &gt; min_fclk_avg ? min_fclk_urgent : min_fclk_avg;</div><div class='add'>+</div><div class='add'>+	min_dcfclk_avg = (double)mode_support_result-&gt;global.svp_prefetch.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_avg = (double)min_dcfclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.dcn_mall_prefetch_average.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_urgent = (double)mode_support_result-&gt;global.svp_prefetch.urgent_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_urgent = (double)min_dcfclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.dcn_mall_prefetch_urgent.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_bw = min_dcfclk_urgent &gt; min_dcfclk_avg ? min_dcfclk_urgent : min_dcfclk_avg;</div><div class='add'>+</div><div class='add'>+	get_minimum_clocks_for_latency(in_out, &amp;min_uclk_latency, &amp;min_fclk_latency, &amp;min_dcfclk_latency);</div><div class='add'>+</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.uclk_khz = dml_round_up(min_uclk_bw &gt; min_uclk_latency ? min_uclk_bw : min_uclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.fclk_khz = dml_round_up(min_fclk_bw &gt; min_fclk_latency ? min_fclk_bw : min_fclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw &gt; min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency);</div><div class='add'>+</div><div class='add'>+	/* assumes DF throttling is disabled */</div><div class='add'>+	min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.svp_prefetch.average_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	min_uclk_avg = (double)min_uclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.svp_prefetch.urgent_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_uclk_bw = min_uclk_urgent &gt; min_uclk_avg ? min_uclk_urgent : min_uclk_avg;</div><div class='add'>+</div><div class='add'>+	min_fclk_avg = (double)mode_support_result-&gt;global.svp_prefetch.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_avg = (double)min_fclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_average.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_urgent = (double)mode_support_result-&gt;global.svp_prefetch.urgent_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_urgent = (double)min_fclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_bw = min_fclk_urgent &gt; min_fclk_avg ? min_fclk_urgent : min_fclk_avg;</div><div class='add'>+</div><div class='add'>+	min_dcfclk_avg = (double)mode_support_result-&gt;global.svp_prefetch.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_avg = (double)min_dcfclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_average.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_urgent = (double)mode_support_result-&gt;global.svp_prefetch.urgent_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_urgent = (double)min_dcfclk_urgent / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_bw = min_dcfclk_urgent &gt; min_dcfclk_avg ? min_dcfclk_urgent : min_dcfclk_avg;</div><div class='add'>+</div><div class='add'>+	get_minimum_clocks_for_latency(in_out, &amp;min_uclk_latency, &amp;min_fclk_latency, &amp;min_dcfclk_latency);</div><div class='add'>+</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz = dml_round_up(min_uclk_bw &gt; min_uclk_latency ? min_uclk_bw : min_uclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz = dml_round_up(min_fclk_bw &gt; min_fclk_latency ? min_fclk_bw : min_fclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.dcfclk_khz = dml_round_up(min_dcfclk_bw &gt; min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void calculate_idle_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	double min_uclk_avg;</div><div class='add'>+	double min_fclk_avg;</div><div class='add'>+	double min_dcfclk_avg;</div><div class='add'>+	double min_uclk_latency, min_fclk_latency, min_dcfclk_latency;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result = &amp;in_out-&gt;display_cfg-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result-&gt;global.active.average_bw_dram_kbps, &amp;in_out-&gt;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+	min_uclk_avg = (double)min_uclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100);</div><div class='add'>+</div><div class='add'>+	min_fclk_avg = (double)mode_support_result-&gt;global.active.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='add'>+	min_fclk_avg = (double)min_fclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_idle_average.fclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	min_dcfclk_avg = (double)mode_support_result-&gt;global.active.average_bw_sdp_kbps / in_out-&gt;soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+	min_dcfclk_avg = (double)min_dcfclk_avg / ((double)in_out-&gt;soc_bb-&gt;qos_parameters.derate_table.system_idle_average.dcfclk_derate_percent / 100);</div><div class='add'>+</div><div class='add'>+	get_minimum_clocks_for_latency(in_out, &amp;min_uclk_latency, &amp;min_fclk_latency, &amp;min_dcfclk_latency);</div><div class='add'>+</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.idle.uclk_khz = dml_round_up(min_uclk_avg &gt; min_uclk_latency ? min_uclk_avg : min_uclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.idle.fclk_khz = dml_round_up(min_fclk_avg &gt; min_fclk_latency ? min_fclk_avg : min_fclk_latency);</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.idle.dcfclk_khz = dml_round_up(min_dcfclk_avg &gt; min_dcfclk_latency ? min_dcfclk_avg : min_dcfclk_latency);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool add_margin_and_round_to_dfs_grainularity(double clock_khz, double margin, unsigned long vco_freq_khz, unsigned long *rounded_khz, uint32_t *divider_id)</div><div class='add'>+{</div><div class='add'>+	enum dentist_divider_range {</div><div class='add'>+		DFS_DIVIDER_RANGE_1_START = 8, /* 2.00 */</div><div class='add'>+		DFS_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */</div><div class='add'>+		DFS_DIVIDER_RANGE_2_START = 64, /* 16.00 */</div><div class='add'>+		DFS_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */</div><div class='add'>+		DFS_DIVIDER_RANGE_3_START = 128, /* 32.00 */</div><div class='add'>+		DFS_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */</div><div class='add'>+		DFS_DIVIDER_RANGE_4_START = 248, /* 62.00 */</div><div class='add'>+		DFS_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */</div><div class='add'>+		DFS_DIVIDER_RANGE_SCALE_FACTOR = 4</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	enum DFS_base_divider_id {</div><div class='add'>+		DFS_BASE_DID_1 = 0x08,</div><div class='add'>+		DFS_BASE_DID_2 = 0x40,</div><div class='add'>+		DFS_BASE_DID_3 = 0x60,</div><div class='add'>+		DFS_BASE_DID_4 = 0x7e,</div><div class='add'>+		DFS_MAX_DID = 0x7f</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	unsigned int divider;</div><div class='add'>+</div><div class='add'>+	if (clock_khz &lt; 1 || vco_freq_khz &lt; 1 || clock_khz &gt; vco_freq_khz)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	clock_khz *= 1.0 + margin;</div><div class='add'>+</div><div class='add'>+	divider = (unsigned int)((int)DFS_DIVIDER_RANGE_SCALE_FACTOR * (vco_freq_khz / clock_khz));</div><div class='add'>+</div><div class='add'>+	/* we want to floor here to get higher clock than required rather than lower */</div><div class='add'>+	if (divider &lt; DFS_DIVIDER_RANGE_2_START) {</div><div class='add'>+		if (divider &lt; DFS_DIVIDER_RANGE_1_START)</div><div class='add'>+			*divider_id = DFS_BASE_DID_1;</div><div class='add'>+		else</div><div class='add'>+			*divider_id = DFS_BASE_DID_1 + ((divider - DFS_DIVIDER_RANGE_1_START) / DFS_DIVIDER_RANGE_1_STEP);</div><div class='add'>+	} else if (divider &lt; DFS_DIVIDER_RANGE_3_START) {</div><div class='add'>+		*divider_id = DFS_BASE_DID_2 + ((divider - DFS_DIVIDER_RANGE_2_START) / DFS_DIVIDER_RANGE_2_STEP);</div><div class='add'>+	} else if (divider &lt; DFS_DIVIDER_RANGE_4_START) {</div><div class='add'>+		*divider_id = DFS_BASE_DID_3 + ((divider - DFS_DIVIDER_RANGE_3_START) / DFS_DIVIDER_RANGE_3_STEP);</div><div class='add'>+	} else {</div><div class='add'>+		*divider_id = DFS_BASE_DID_4 + ((divider - DFS_DIVIDER_RANGE_4_START) / DFS_DIVIDER_RANGE_4_STEP);</div><div class='add'>+		if (*divider_id &gt; DFS_MAX_DID)</div><div class='add'>+			*divider_id = DFS_MAX_DID;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*rounded_khz = vco_freq_khz * DFS_DIVIDER_RANGE_SCALE_FACTOR / divider;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool round_to_non_dfs_granularity(unsigned long dispclk_khz, unsigned long dpprefclk_khz, unsigned long dtbrefclk_khz,</div><div class='add'>+	unsigned long *rounded_dispclk_khz, unsigned long *rounded_dpprefclk_khz, unsigned long *rounded_dtbrefclk_khz)</div><div class='add'>+{</div><div class='add'>+	unsigned long pll_frequency_khz;</div><div class='add'>+</div><div class='add'>+	pll_frequency_khz = (unsigned long) math_max2(600000, math_ceil2(math_max3(dispclk_khz, dpprefclk_khz, dtbrefclk_khz), 1000));</div><div class='add'>+</div><div class='add'>+	*rounded_dispclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dispclk_khz, 32);</div><div class='add'>+</div><div class='add'>+	*rounded_dpprefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dpprefclk_khz, 32);</div><div class='add'>+</div><div class='add'>+	if (dtbrefclk_khz &gt; 0) {</div><div class='add'>+		*rounded_dtbrefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dtbrefclk_khz, 32);</div><div class='add'>+	} else {</div><div class='add'>+		*rounded_dtbrefclk_khz = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool round_up_and_copy_to_next_dpm(unsigned long min_value, unsigned long *rounded_value, const struct dml2_clk_table *clock_table)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+	int index = 0;</div><div class='add'>+</div><div class='add'>+	if (clock_table-&gt;num_clk_values &gt; 2) {</div><div class='add'>+		while (index &lt; clock_table-&gt;num_clk_values &amp;&amp; clock_table-&gt;clk_values_khz[index] &lt; min_value)</div><div class='add'>+			index++;</div><div class='add'>+</div><div class='add'>+		if (index &lt; clock_table-&gt;num_clk_values) {</div><div class='add'>+			*rounded_value = clock_table-&gt;clk_values_khz[index];</div><div class='add'>+			result = true;</div><div class='add'>+		}</div><div class='add'>+	} else if (clock_table-&gt;clk_values_khz[clock_table-&gt;num_clk_values - 1] &gt;= min_value) {</div><div class='add'>+		*rounded_value = min_value;</div><div class='add'>+		result = true;</div><div class='add'>+	}</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool round_up_to_next_dpm(unsigned long *clock_value, const struct dml2_clk_table *clock_table)</div><div class='add'>+{</div><div class='add'>+	return round_up_and_copy_to_next_dpm(*clock_value, clock_value, clock_table);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)</div><div class='add'>+{</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.active.dcfclk_khz, &amp;state_table-&gt;dcfclk);</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.active.fclk_khz, &amp;state_table-&gt;fclk);</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.active.uclk_khz, &amp;state_table-&gt;uclk);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.svp_prefetch.dcfclk_khz, &amp;state_table-&gt;dcfclk);</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.svp_prefetch.fclk_khz, &amp;state_table-&gt;fclk);</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.svp_prefetch.uclk_khz, &amp;state_table-&gt;uclk);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.idle.dcfclk_khz, &amp;state_table-&gt;dcfclk);</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.idle.fclk_khz, &amp;state_table-&gt;fclk);</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.idle.uclk_khz, &amp;state_table-&gt;uclk);</div><div class='add'>+</div><div class='add'>+	/* these clocks are optional, so they can fail to map, in which case map all to 0 */</div><div class='add'>+	if (result) {</div><div class='add'>+		if (!round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.dcfclk_khz, &amp;state_table-&gt;dcfclk) ||</div><div class='add'>+			!round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz, &amp;state_table-&gt;fclk) ||</div><div class='add'>+			!round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz, &amp;state_table-&gt;uclk)) {</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.dcfclk_khz = 0;</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz = 0;</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool map_soc_min_clocks_to_dpm_coarse_grained(struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)</div><div class='add'>+{</div><div class='add'>+	bool result;</div><div class='add'>+	int index;</div><div class='add'>+</div><div class='add'>+	result = false;</div><div class='add'>+	for (index = 0; index &lt; state_table-&gt;uclk.num_clk_values; index++) {</div><div class='add'>+		if (display_cfg-&gt;min_clocks.dcn4x.active.dcfclk_khz &lt;= state_table-&gt;dcfclk.clk_values_khz[index] &amp;&amp;</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.active.fclk_khz &lt;= state_table-&gt;fclk.clk_values_khz[index] &amp;&amp;</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.active.uclk_khz &lt;= state_table-&gt;uclk.clk_values_khz[index]) {</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.active.dcfclk_khz = state_table-&gt;dcfclk.clk_values_khz[index];</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.active.fclk_khz = state_table-&gt;fclk.clk_values_khz[index];</div><div class='add'>+			display_cfg-&gt;min_clocks.dcn4x.active.uclk_khz = state_table-&gt;uclk.clk_values_khz[index];</div><div class='add'>+			result = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		result = false;</div><div class='add'>+		for (index = 0; index &lt; state_table-&gt;uclk.num_clk_values; index++) {</div><div class='add'>+			if (display_cfg-&gt;min_clocks.dcn4x.idle.dcfclk_khz &lt;= state_table-&gt;dcfclk.clk_values_khz[index] &amp;&amp;</div><div class='add'>+				display_cfg-&gt;min_clocks.dcn4x.idle.fclk_khz &lt;= state_table-&gt;fclk.clk_values_khz[index] &amp;&amp;</div><div class='add'>+				display_cfg-&gt;min_clocks.dcn4x.idle.uclk_khz &lt;= state_table-&gt;uclk.clk_values_khz[index]) {</div><div class='add'>+				display_cfg-&gt;min_clocks.dcn4x.idle.dcfclk_khz = state_table-&gt;dcfclk.clk_values_khz[index];</div><div class='add'>+				display_cfg-&gt;min_clocks.dcn4x.idle.fclk_khz = state_table-&gt;fclk.clk_values_khz[index];</div><div class='add'>+				display_cfg-&gt;min_clocks.dcn4x.idle.uclk_khz = state_table-&gt;uclk.clk_values_khz[index];</div><div class='add'>+				result = true;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// SVP is not supported on any coarse grained SoCs</div><div class='add'>+	display_cfg-&gt;min_clocks.dcn4x.svp_prefetch.dcfclk_khz = 0;</div><div class='add'>+	display_cfg-&gt;min_clocks.dcn4x.svp_prefetch.fclk_khz = 0;</div><div class='add'>+	display_cfg-&gt;min_clocks.dcn4x.svp_prefetch.uclk_khz = 0;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mode_support_result, struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+	bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_identical = false;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (!state_table || !display_cfg)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (state_table-&gt;dcfclk.num_clk_values == 2) {</div><div class='add'>+		dcfclk_fine_grained = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (state_table-&gt;fclk.num_clk_values == 2) {</div><div class='add'>+		fclk_fine_grained = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (state_table-&gt;fclk.num_clk_values == state_table-&gt;dcfclk.num_clk_values &amp;&amp;</div><div class='add'>+		state_table-&gt;fclk.num_clk_values == state_table-&gt;uclk.num_clk_values) {</div><div class='add'>+		clock_state_count_identical = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dcfclk_fine_grained || fclk_fine_grained || !clock_state_count_identical)</div><div class='add'>+		result = map_soc_min_clocks_to_dpm_fine_grained(display_cfg, state_table);</div><div class='add'>+	else</div><div class='add'>+		result = map_soc_min_clocks_to_dpm_coarse_grained(display_cfg, state_table);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.dispclk_khz, &amp;state_table-&gt;dispclk);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_DCN_PIPES; i++) {</div><div class='add'>+		if (result)</div><div class='add'>+			result = round_up_to_next_dpm(&amp;display_cfg-&gt;plane_programming[i].min_clocks.dcn4x.dppclk_khz, &amp;state_table-&gt;dppclk);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_cfg-&gt;display_config.num_streams; i++) {</div><div class='add'>+		if (result)</div><div class='add'>+			result = round_up_and_copy_to_next_dpm(mode_support_result-&gt;per_stream[i].dscclk_khz, &amp;display_cfg-&gt;stream_programming[i].min_clocks.dcn4x.dscclk_khz, &amp;state_table-&gt;dscclk);</div><div class='add'>+		if (result)</div><div class='add'>+			result = round_up_and_copy_to_next_dpm(mode_support_result-&gt;per_stream[i].dtbclk_khz, &amp;display_cfg-&gt;stream_programming[i].min_clocks.dcn4x.dtbclk_khz, &amp;state_table-&gt;dtbclk);</div><div class='add'>+		if (result)</div><div class='add'>+			result = round_up_and_copy_to_next_dpm(mode_support_result-&gt;per_stream[i].phyclk_khz, &amp;display_cfg-&gt;stream_programming[i].min_clocks.dcn4x.phyclk_khz, &amp;state_table-&gt;phyclk);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.dpprefclk_khz, &amp;state_table-&gt;dppclk);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = round_up_to_next_dpm(&amp;display_cfg-&gt;min_clocks.dcn4x.dtbrefclk_khz, &amp;state_table-&gt;dtbclk);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool identical = true;</div><div class='add'>+	bool contains_drr = false;</div><div class='add'>+	unsigned int remap_array[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int remap_array_size = 0;</div><div class='add'>+</div><div class='add'>+	// Create a remap array to enable simple iteration through only masked stream indicies</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_streams; i++) {</div><div class='add'>+		if (mask &amp; (0x1 &lt;&lt; i)) {</div><div class='add'>+			remap_array[remap_array_size++] = i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// 0 or 1 display is always trivially synchronizable</div><div class='add'>+	if (remap_array_size &lt;= 1)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	// Check that all displays timings are the same</div><div class='add'>+	for (i = 1; i &lt; remap_array_size; i++) {</div><div class='add'>+		if (memcmp(&amp;display_config-&gt;stream_descriptors[remap_array[i - 1]].timing, &amp;display_config-&gt;stream_descriptors[remap_array[i]].timing, sizeof(struct dml2_timing_cfg))) {</div><div class='add'>+			identical = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Check if any displays are drr</div><div class='add'>+	for (i = 0; i &lt; remap_array_size; i++) {</div><div class='add'>+		if (display_config-&gt;stream_descriptors[remap_array[i]].timing.drr_config.enabled) {</div><div class='add'>+			contains_drr = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Trivial sync is possible if all displays are identical and none are DRR</div><div class='add'>+	return !contains_drr &amp;&amp; identical;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int find_smallest_idle_time_in_vblank_us(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out, int mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int min_idle_us = 0;</div><div class='add'>+	unsigned int remap_array[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int remap_array_size = 0;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result = &amp;in_out-&gt;display_cfg-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	// Create a remap array to enable simple iteration through only masked stream indicies</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;programming-&gt;display_config.num_streams; i++) {</div><div class='add'>+		if (mask &amp; (0x1 &lt;&lt; i)) {</div><div class='add'>+			remap_array[remap_array_size++] = i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (remap_array_size == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	min_idle_us = mode_support_result-&gt;cfg_support_info.stream_support_info[remap_array[0]].vblank_reserved_time_us;</div><div class='add'>+</div><div class='add'>+	for (i = 1; i &lt; remap_array_size; i++) {</div><div class='add'>+		if (min_idle_us &gt; mode_support_result-&gt;cfg_support_info.stream_support_info[remap_array[i]].vblank_reserved_time_us)</div><div class='add'>+			min_idle_us = mode_support_result-&gt;cfg_support_info.stream_support_info[remap_array[i]].vblank_reserved_time_us;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return min_idle_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool determine_power_management_features_with_vblank_only(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int min_idle_us;</div><div class='add'>+</div><div class='add'>+	if (are_timings_trivially_synchronizable(&amp;in_out-&gt;programming-&gt;display_config, 0xF)) {</div><div class='add'>+		min_idle_us = find_smallest_idle_time_in_vblank_us(in_out, 0xF);</div><div class='add'>+</div><div class='add'>+		if (min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us)</div><div class='add'>+			in_out-&gt;programming-&gt;uclk_pstate_supported = true;</div><div class='add'>+</div><div class='add'>+		if (min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us)</div><div class='add'>+			in_out-&gt;programming-&gt;fclk_pstate_supported = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_displays_without_vactive_margin_mask(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out, int latency_hiding_requirement_us)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int displays_without_vactive_margin_mask = 0x0;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result = &amp;in_out-&gt;display_cfg-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;programming-&gt;display_config.num_planes; i++) {</div><div class='add'>+		if (mode_support_result-&gt;cfg_support_info.plane_support_info[i].active_latency_hiding_us</div><div class='add'>+			&lt; latency_hiding_requirement_us)</div><div class='add'>+			displays_without_vactive_margin_mask |= (0x1 &lt;&lt; i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return displays_without_vactive_margin_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_displays_with_fams_mask(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out, int latency_hiding_requirement_us)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int displays_with_fams_mask = 0x0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;programming-&gt;display_config.num_planes; i++) {</div><div class='add'>+		if (in_out-&gt;programming-&gt;display_config.plane_descriptors-&gt;overrides.legacy_svp_config != dml2_svp_mode_override_auto)</div><div class='add'>+			displays_with_fams_mask |= (0x1 &lt;&lt; i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return displays_with_fams_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool determine_power_management_features_with_vactive_and_vblank(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int displays_without_vactive_margin_mask = 0x0;</div><div class='add'>+	int min_idle_us = 0;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;uclk_pstate_supported == false) {</div><div class='add'>+		displays_without_vactive_margin_mask =</div><div class='add'>+			get_displays_without_vactive_margin_mask(in_out, (int)(in_out-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us));</div><div class='add'>+</div><div class='add'>+		if (are_timings_trivially_synchronizable(&amp;in_out-&gt;programming-&gt;display_config, displays_without_vactive_margin_mask)) {</div><div class='add'>+			min_idle_us = find_smallest_idle_time_in_vblank_us(in_out, displays_without_vactive_margin_mask);</div><div class='add'>+</div><div class='add'>+			if (min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us)</div><div class='add'>+				in_out-&gt;programming-&gt;uclk_pstate_supported = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;fclk_pstate_supported == false) {</div><div class='add'>+		displays_without_vactive_margin_mask =</div><div class='add'>+			get_displays_without_vactive_margin_mask(in_out, (int)(in_out-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us));</div><div class='add'>+</div><div class='add'>+		if (are_timings_trivially_synchronizable(&amp;in_out-&gt;programming-&gt;display_config, displays_without_vactive_margin_mask)) {</div><div class='add'>+			min_idle_us = find_smallest_idle_time_in_vblank_us(in_out, displays_without_vactive_margin_mask);</div><div class='add'>+</div><div class='add'>+			if (min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us)</div><div class='add'>+				in_out-&gt;programming-&gt;fclk_pstate_supported = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool determine_power_management_features_with_fams(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int displays_without_vactive_margin_mask = 0x0;</div><div class='add'>+	int displays_without_fams_mask = 0x0;</div><div class='add'>+</div><div class='add'>+	displays_without_vactive_margin_mask =</div><div class='add'>+		get_displays_without_vactive_margin_mask(in_out, (int)(in_out-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us));</div><div class='add'>+</div><div class='add'>+	displays_without_fams_mask =</div><div class='add'>+		get_displays_with_fams_mask(in_out, (int)(in_out-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us));</div><div class='add'>+</div><div class='add'>+	if ((displays_without_vactive_margin_mask &amp; ~displays_without_fams_mask) == 0)</div><div class='add'>+		in_out-&gt;programming-&gt;uclk_pstate_supported = true;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clamp_uclk_to_max(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.active.uclk_khz = in_out-&gt;soc_bb-&gt;clk_table.uclk.clk_values_khz[in_out-&gt;soc_bb-&gt;clk_table.uclk.num_clk_values - 1];</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.uclk_khz = in_out-&gt;soc_bb-&gt;clk_table.uclk.clk_values_khz[in_out-&gt;soc_bb-&gt;clk_table.uclk.num_clk_values - 1];</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.idle.uclk_khz = in_out-&gt;soc_bb-&gt;clk_table.uclk.clk_values_khz[in_out-&gt;soc_bb-&gt;clk_table.uclk.num_clk_values - 1];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clamp_fclk_to_max(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.active.fclk_khz = in_out-&gt;soc_bb-&gt;clk_table.fclk.clk_values_khz[in_out-&gt;soc_bb-&gt;clk_table.fclk.num_clk_values - 1];</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.idle.fclk_khz = in_out-&gt;soc_bb-&gt;clk_table.fclk.clk_values_khz[in_out-&gt;soc_bb-&gt;clk_table.fclk.num_clk_values - 1];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	bool result;</div><div class='add'>+	double dispclk_khz;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result = &amp;in_out-&gt;display_cfg-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	calculate_system_active_minimums(in_out);</div><div class='add'>+	calculate_svp_prefetch_minimums(in_out);</div><div class='add'>+	calculate_idle_minimums(in_out);</div><div class='add'>+</div><div class='add'>+	// In NV4, there's no support for FCLK or DCFCLK DPM change before SVP prefetch starts, therefore</div><div class='add'>+	// active minimums must be boosted to prefetch minimums</div><div class='add'>+	if (in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.uclk_khz &gt; in_out-&gt;programming-&gt;min_clocks.dcn4x.active.uclk_khz)</div><div class='add'>+		in_out-&gt;programming-&gt;min_clocks.dcn4x.active.uclk_khz = in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.uclk_khz;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.fclk_khz &gt; in_out-&gt;programming-&gt;min_clocks.dcn4x.active.fclk_khz)</div><div class='add'>+		in_out-&gt;programming-&gt;min_clocks.dcn4x.active.fclk_khz = in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.fclk_khz;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.dcfclk_khz &gt; in_out-&gt;programming-&gt;min_clocks.dcn4x.active.dcfclk_khz)</div><div class='add'>+		in_out-&gt;programming-&gt;min_clocks.dcn4x.active.dcfclk_khz = in_out-&gt;programming-&gt;min_clocks.dcn4x.svp_prefetch.dcfclk_khz;</div><div class='add'>+</div><div class='add'>+	// need some massaging for the dispclk ramping cases:</div><div class='add'>+	dispclk_khz = mode_support_result-&gt;global.dispclk_khz * (1 + in_out-&gt;soc_bb-&gt;dcn_downspread_percent / 100.0) * (1.0 + in_out-&gt;ip-&gt;dispclk_ramp_margin_percent / 100.0);</div><div class='add'>+	// ramping margin should not make dispclk exceed the maximum dispclk speed:</div><div class='add'>+	dispclk_khz = math_min2(dispclk_khz, in_out-&gt;min_clk_table-&gt;max_clocks_khz.dispclk);</div><div class='add'>+	// but still the required dispclk can be more than the maximum dispclk speed:</div><div class='add'>+	dispclk_khz = math_max2(dispclk_khz, mode_support_result-&gt;global.dispclk_khz * (1 + in_out-&gt;soc_bb-&gt;dcn_downspread_percent / 100.0));</div><div class='add'>+</div><div class='add'>+	// DPP Ref is always set to max of all DPP clocks</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_DCN_PIPES; i++) {</div><div class='add'>+		if (in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz &lt; mode_support_result-&gt;per_plane[i].dppclk_khz)</div><div class='add'>+			in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz = mode_support_result-&gt;per_plane[i].dppclk_khz;</div><div class='add'>+	}</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz = (unsigned long) (in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz * (1 + in_out-&gt;soc_bb-&gt;dcn_downspread_percent / 100.0));</div><div class='add'>+</div><div class='add'>+	// DTB Ref is always set to max of all DTB clocks</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_DCN_PIPES; i++) {</div><div class='add'>+		if (in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz &lt; mode_support_result-&gt;per_stream[i].dtbclk_khz)</div><div class='add'>+			in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz = mode_support_result-&gt;per_stream[i].dtbclk_khz;</div><div class='add'>+	}</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz = (unsigned long)(in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz * (1 + in_out-&gt;soc_bb-&gt;dcn_downspread_percent / 100.0));</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;soc_bb-&gt;no_dfs) {</div><div class='add'>+		round_to_non_dfs_granularity((unsigned long)dispclk_khz, in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz, in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz,</div><div class='add'>+			&amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.dispclk_khz, &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz, &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz);</div><div class='add'>+	} else {</div><div class='add'>+		add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0,</div><div class='add'>+			(unsigned long)(in_out-&gt;soc_bb-&gt;dispclk_dppclk_vco_speed_mhz * 1000), &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.dispclk_khz, &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.divider_ids.dispclk_did);</div><div class='add'>+</div><div class='add'>+		add_margin_and_round_to_dfs_grainularity(in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz, 0.0,</div><div class='add'>+			(unsigned long)(in_out-&gt;soc_bb-&gt;dispclk_dppclk_vco_speed_mhz * 1000), &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz, &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.divider_ids.dpprefclk_did);</div><div class='add'>+</div><div class='add'>+		add_margin_and_round_to_dfs_grainularity(in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz, 0.0,</div><div class='add'>+			(unsigned long)(in_out-&gt;soc_bb-&gt;dispclk_dppclk_vco_speed_mhz * 1000), &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.dtbrefclk_khz, &amp;in_out-&gt;programming-&gt;min_clocks.dcn4x.divider_ids.dtbrefclk_did);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_DCN_PIPES; i++) {</div><div class='add'>+		in_out-&gt;programming-&gt;plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz / 255.0</div><div class='add'>+			* math_ceil2(in_out-&gt;display_cfg-&gt;mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out-&gt;soc_bb-&gt;dcn_downspread_percent / 100.0) * 255.0 / in_out-&gt;programming-&gt;min_clocks.dcn4x.dpprefclk_khz, 1.0));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.deepsleep_dcfclk_khz = mode_support_result-&gt;global.dcfclk_deepsleep_khz;</div><div class='add'>+	in_out-&gt;programming-&gt;min_clocks.dcn4x.socclk_khz = mode_support_result-&gt;global.socclk_khz;</div><div class='add'>+</div><div class='add'>+	result = map_min_clocks_to_dpm(mode_support_result, in_out-&gt;programming, &amp;in_out-&gt;soc_bb-&gt;clk_table);</div><div class='add'>+</div><div class='add'>+	// By default, all power management features are not enabled</div><div class='add'>+	in_out-&gt;programming-&gt;fclk_pstate_supported = false;</div><div class='add'>+	in_out-&gt;programming-&gt;uclk_pstate_supported = false;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	result = map_mode_to_soc_dpm(in_out);</div><div class='add'>+</div><div class='add'>+	// Check if any can be enabled by nominal vblank idle time</div><div class='add'>+	determine_power_management_features_with_vblank_only(in_out);</div><div class='add'>+</div><div class='add'>+	// Check if any can be enabled in vactive/vblank</div><div class='add'>+	determine_power_management_features_with_vactive_and_vblank(in_out);</div><div class='add'>+</div><div class='add'>+	// Check if any can be enabled via fams</div><div class='add'>+	determine_power_management_features_with_fams(in_out);</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;uclk_pstate_supported == false)</div><div class='add'>+		clamp_uclk_to_max(in_out);</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;fclk_pstate_supported == false)</div><div class='add'>+		clamp_fclk_to_max(in_out);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool result;</div><div class='add'>+	int displays_without_vactive_margin_mask = 0x0;</div><div class='add'>+	int min_idle_us = 0;</div><div class='add'>+</div><div class='add'>+	result = map_mode_to_soc_dpm(in_out);</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;display_cfg-&gt;stage3.success)</div><div class='add'>+		in_out-&gt;programming-&gt;uclk_pstate_supported = true;</div><div class='add'>+</div><div class='add'>+	displays_without_vactive_margin_mask =</div><div class='add'>+		get_displays_without_vactive_margin_mask(in_out, (int)(in_out-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us));</div><div class='add'>+</div><div class='add'>+	if (displays_without_vactive_margin_mask == 0) {</div><div class='add'>+		in_out-&gt;programming-&gt;fclk_pstate_supported = true;</div><div class='add'>+	} else {</div><div class='add'>+		if (are_timings_trivially_synchronizable(&amp;in_out-&gt;programming-&gt;display_config, displays_without_vactive_margin_mask)) {</div><div class='add'>+			min_idle_us = find_smallest_idle_time_in_vblank_us(in_out, displays_without_vactive_margin_mask);</div><div class='add'>+</div><div class='add'>+			if (min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us)</div><div class='add'>+				in_out-&gt;programming-&gt;fclk_pstate_supported = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;uclk_pstate_supported == false)</div><div class='add'>+		clamp_uclk_to_max(in_out);</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;programming-&gt;fclk_pstate_supported == false)</div><div class='add'>+		clamp_fclk_to_max(in_out);</div><div class='add'>+</div><div class='add'>+	min_idle_us = find_smallest_idle_time_in_vblank_us(in_out, 0xFF);</div><div class='add'>+	if (in_out-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us &gt; 0 &amp;&amp;</div><div class='add'>+		min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us)</div><div class='add'>+		in_out-&gt;programming-&gt;stutter.supported_in_blank = true;</div><div class='add'>+	else</div><div class='add'>+		in_out-&gt;programming-&gt;stutter.supported_in_blank = false;</div><div class='add'>+</div><div class='add'>+	// TODO: Fix me Sam</div><div class='add'>+	if (in_out-&gt;soc_bb-&gt;power_management_parameters.z8_min_idle_time &gt; 0 &amp;&amp;</div><div class='add'>+		in_out-&gt;programming-&gt;informative.power_management.z8.stutter_period &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.z8_min_idle_time)</div><div class='add'>+		in_out-&gt;programming-&gt;z8_stutter.meets_eco = true;</div><div class='add'>+	else</div><div class='add'>+		in_out-&gt;programming-&gt;z8_stutter.meets_eco = false;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us &gt; 0 &amp;&amp;</div><div class='add'>+		min_idle_us &gt;= in_out-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us)</div><div class='add'>+		in_out-&gt;programming-&gt;z8_stutter.supported_in_blank = true;</div><div class='add'>+	else</div><div class='add'>+		in_out-&gt;programming-&gt;z8_stutter.supported_in_blank = false;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_display_cfg *display_cfg = &amp;in_out-&gt;display_cfg-&gt;display_config;</div><div class='add'>+	const struct dml2_core_internal_display_mode_lib *mode_lib = &amp;in_out-&gt;core-&gt;clean_me_up.mode_lib;</div><div class='add'>+	struct dml2_dchub_global_register_set *dchubbub_regs = &amp;in_out-&gt;programming-&gt;global_regs;</div><div class='add'>+</div><div class='add'>+	double refclk_freq_in_mhz = (display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz &gt; 0) ? (double)display_cfg-&gt;overrides.hw.dlg_ref_clk_mhz : mode_lib-&gt;soc.dchub_refclk_mhz;</div><div class='add'>+</div><div class='add'>+	/* set A */</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].fclk_pstate = (int unsigned)(mode_lib-&gt;mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter = (int unsigned)(mode_lib-&gt;mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit = (int unsigned)(mode_lib-&gt;mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter_z8 = (int unsigned)(mode_lib-&gt;mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit_z8 = (int unsigned)(mode_lib-&gt;mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].temp_read_or_ppt = (int unsigned)(mode_lib-&gt;mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].uclk_pstate = (int unsigned)(mode_lib-&gt;mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].urgent = (int unsigned)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].usr = (int unsigned)(mode_lib-&gt;mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_trip_to_mem = (unsigned int)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_flip = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidthImmediateFlip * 1000);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_nom = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidth * 1000);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_mall = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidthMALL * 1000);</div><div class='add'>+</div><div class='add'>+	/* set B */</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].fclk_pstate = (int unsigned)(mode_lib-&gt;mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].sr_enter = (int unsigned)(mode_lib-&gt;mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].sr_exit = (int unsigned)(mode_lib-&gt;mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].sr_enter_z8 = (int unsigned)(mode_lib-&gt;mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].sr_exit_z8 = (int unsigned)(mode_lib-&gt;mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].temp_read_or_ppt = (int unsigned)(mode_lib-&gt;mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].uclk_pstate = (int unsigned)(mode_lib-&gt;mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].urgent = (int unsigned)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].usr = (int unsigned)(mode_lib-&gt;mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].refcyc_per_trip_to_mem = (unsigned int)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib-&gt;mp.Watermark.UrgentWatermark * refclk_freq_in_mhz);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].frac_urg_bw_flip = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidthImmediateFlip * 1000);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].frac_urg_bw_nom = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidth * 1000);</div><div class='add'>+	dchubbub_regs-&gt;wm_regs[DML2_DCHUB_WATERMARK_SET_B].frac_urg_bw_mall = (unsigned int)(mode_lib-&gt;mp.FractionOfUrgentBandwidthMALL * 1000);</div><div class='add'>+</div><div class='add'>+	dchubbub_regs-&gt;num_watermark_sets = 2;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h<br/>new file mode 100644<br/>index 000000000000..e7b58f2efda4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_DPMM_DCN4_H__</div><div class='add'>+#define __DML2_DPMM_DCN4_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+</div><div class='add'>+bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);</div><div class='add'>+bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);</div><div class='add'>+bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c<br/>new file mode 100644<br/>index 000000000000..dfd01440737d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_dpmm_factory.h"</div><div class='add'>+#include "dml2_dpmm_dcn4.h"</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+</div><div class='add'>+static bool dummy_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dummy_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance *out)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (!out)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memset(out, 0, sizeof(struct dml2_dpmm_instance));</div><div class='add'>+</div><div class='add'>+	switch (project_id) {</div><div class='add'>+	case dml2_project_dcn4x_stage1:</div><div class='add'>+		out-&gt;map_mode_to_soc_dpm = &amp;dummy_map_mode_to_soc_dpm;</div><div class='add'>+		out-&gt;map_watermarks = &amp;dummy_map_watermarks;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_dcn4x_stage2:</div><div class='add'>+		out-&gt;map_mode_to_soc_dpm = &amp;dpmm_dcn3_map_mode_to_soc_dpm;</div><div class='add'>+		out-&gt;map_watermarks = &amp;dummy_map_watermarks;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_dcn4x_stage2_auto_drr_svp:</div><div class='add'>+		out-&gt;map_mode_to_soc_dpm = &amp;dpmm_dcn4_map_mode_to_soc_dpm;</div><div class='add'>+		out-&gt;map_watermarks = &amp;dpmm_dcn4_map_watermarks;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_invalid:</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h<br/>new file mode 100644<br/>index 000000000000..20ba2e446f1d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_DPMM_FACTORY_H__</div><div class='add'>+#define __DML2_DPMM_FACTORY_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance *out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c<br/>new file mode 100644<br/>index 000000000000..a265f254152c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c</a></div><div class='hunk'>@@ -0,0 +1,198 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_mcg_dcn4.h"</div><div class='add'>+#include "dml_top_soc_parameter_types.h"</div><div class='add'>+</div><div class='add'>+static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table);</div><div class='add'>+</div><div class='add'>+bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return build_min_clock_table(in_out-&gt;soc_bb, in_out-&gt;min_clk_table);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned long long uclk_to_dram_bw_kbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config)</div><div class='add'>+{</div><div class='add'>+	unsigned long long bw_kbps = 0;</div><div class='add'>+</div><div class='add'>+	bw_kbps = (unsigned long long) uclk_khz * dram_config-&gt;channel_count * dram_config-&gt;channel_width_bytes * dram_config-&gt;transactions_per_clock;</div><div class='add'>+</div><div class='add'>+	return bw_kbps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned long round_up_to_quantized_values(unsigned long value, const unsigned long *quantized_values, int num_quantized_values)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!quantized_values)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_quantized_values; i++) {</div><div class='add'>+		if (quantized_values[i] &gt; value)</div><div class='add'>+			return quantized_values[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool build_min_clk_table_fine_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)</div><div class='add'>+{</div><div class='add'>+	bool dcfclk_fine_grained = false, fclk_fine_grained = false;</div><div class='add'>+</div><div class='add'>+	int i;</div><div class='add'>+	unsigned int j;</div><div class='add'>+</div><div class='add'>+	unsigned long min_dcfclk_khz = 0;</div><div class='add'>+	unsigned long min_fclk_khz = 0;</div><div class='add'>+	unsigned long prev_100, cur_50;</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.dcfclk.num_clk_values == 2) {</div><div class='add'>+		dcfclk_fine_grained = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.fclk.num_clk_values == 2) {</div><div class='add'>+		fclk_fine_grained = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_dcfclk_khz = soc_bb-&gt;clk_table.dcfclk.clk_values_khz[0];</div><div class='add'>+	min_fclk_khz = soc_bb-&gt;clk_table.fclk.clk_values_khz[0];</div><div class='add'>+</div><div class='add'>+	// First calculate the table for "balanced" bandwidths across UCLK/FCLK</div><div class='add'>+	for (i = 0; i &lt; soc_bb-&gt;clk_table.uclk.num_clk_values; i++) {</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb-&gt;clk_table.uclk.clk_values_khz[i], &amp;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].min_fclk_khz = (unsigned long)((((double)min_table-&gt;dram_bw_table.entries[i].pre_derate_dram_bw_kbps * soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100) / ((double)soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.fclk_derate_percent / 100)) / soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes);</div><div class='add'>+	}</div><div class='add'>+	min_table-&gt;dram_bw_table.num_entries = soc_bb-&gt;clk_table.uclk.num_clk_values;</div><div class='add'>+</div><div class='add'>+	// To create the minium table, effectively shift "up" all the dcfclk/fclk entries by 1, and then replace the lowest entry with min fclk/dcfclk</div><div class='add'>+	for (i = min_table-&gt;dram_bw_table.num_entries - 1; i &gt; 0; i--) {</div><div class='add'>+		prev_100 = min_table-&gt;dram_bw_table.entries[i - 1].min_fclk_khz;</div><div class='add'>+		cur_50 = min_table-&gt;dram_bw_table.entries[i].min_fclk_khz / 2;</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].min_fclk_khz = prev_100 &gt; cur_50 ? prev_100 : cur_50;</div><div class='add'>+</div><div class='add'>+		if (!fclk_fine_grained) {</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz = round_up_to_quantized_values(min_table-&gt;dram_bw_table.entries[i].min_fclk_khz, soc_bb-&gt;clk_table.fclk.clk_values_khz, soc_bb-&gt;clk_table.fclk.num_clk_values);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	min_table-&gt;dram_bw_table.entries[0].min_fclk_khz /= 2;</div><div class='add'>+</div><div class='add'>+	// Clamp to minimums and maximums</div><div class='add'>+	for (i = 0; i &lt; (int)min_table-&gt;dram_bw_table.num_entries; i++) {</div><div class='add'>+		if (min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz &lt; min_dcfclk_khz)</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz = min_dcfclk_khz;</div><div class='add'>+</div><div class='add'>+		if (min_table-&gt;dram_bw_table.entries[i].min_fclk_khz &lt; min_fclk_khz)</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz = min_fclk_khz;</div><div class='add'>+</div><div class='add'>+		if (soc_bb-&gt;max_fclk_for_uclk_dpm_khz &gt; 0 &amp;&amp;</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz &gt; soc_bb-&gt;max_fclk_for_uclk_dpm_khz)</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz = soc_bb-&gt;max_fclk_for_uclk_dpm_khz;</div><div class='add'>+</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz =</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz *</div><div class='add'>+			soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.fclk_derate_percent / soc_bb-&gt;qos_parameters.derate_table.system_active_urgent.dcfclk_derate_percent;</div><div class='add'>+</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz =</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz * soc_bb-&gt;fabric_datapath_to_dcn_data_return_bytes / soc_bb-&gt;return_bus_width_bytes;</div><div class='add'>+</div><div class='add'>+		if (!dcfclk_fine_grained) {</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz = round_up_to_quantized_values(min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz, soc_bb-&gt;clk_table.dcfclk.clk_values_khz, soc_bb-&gt;clk_table.dcfclk.num_clk_values);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Prune states which are invalid (some clocks exceed maximum)</div><div class='add'>+	for (i = 0; i &lt; (int)min_table-&gt;dram_bw_table.num_entries; i++) {</div><div class='add'>+		if (min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz &gt; min_table-&gt;max_clocks_khz.dcfclk ||</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz &gt; min_table-&gt;max_clocks_khz.fclk) {</div><div class='add'>+			min_table-&gt;dram_bw_table.num_entries = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Prune duplicate states</div><div class='add'>+	for (i = 0; i &lt; (int)min_table-&gt;dram_bw_table.num_entries - 1; i++) {</div><div class='add'>+		if (min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz == min_table-&gt;dram_bw_table.entries[i + 1].min_dcfclk_khz &amp;&amp;</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].min_fclk_khz == min_table-&gt;dram_bw_table.entries[i + 1].min_fclk_khz &amp;&amp;</div><div class='add'>+			min_table-&gt;dram_bw_table.entries[i].pre_derate_dram_bw_kbps == min_table-&gt;dram_bw_table.entries[i + 1].pre_derate_dram_bw_kbps) {</div><div class='add'>+</div><div class='add'>+			// i + 1 is the same state as i, so shift everything</div><div class='add'>+			for (j = i + 1; j &lt; min_table-&gt;dram_bw_table.num_entries; j++) {</div><div class='add'>+				min_table-&gt;dram_bw_table.entries[j].min_dcfclk_khz = min_table-&gt;dram_bw_table.entries[j + 1].min_dcfclk_khz;</div><div class='add'>+				min_table-&gt;dram_bw_table.entries[j].min_fclk_khz = min_table-&gt;dram_bw_table.entries[j + 1].min_fclk_khz;</div><div class='add'>+				min_table-&gt;dram_bw_table.entries[j].pre_derate_dram_bw_kbps = min_table-&gt;dram_bw_table.entries[j + 1].pre_derate_dram_bw_kbps;</div><div class='add'>+			}</div><div class='add'>+			min_table-&gt;dram_bw_table.num_entries--;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; soc_bb-&gt;clk_table.uclk.num_clk_values; i++) {</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb-&gt;clk_table.uclk.clk_values_khz[i], &amp;soc_bb-&gt;clk_table.dram_config);</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].min_dcfclk_khz = soc_bb-&gt;clk_table.dcfclk.clk_values_khz[i];</div><div class='add'>+		min_table-&gt;dram_bw_table.entries[i].min_fclk_khz = soc_bb-&gt;clk_table.fclk.clk_values_khz[i];</div><div class='add'>+	}</div><div class='add'>+	min_table-&gt;dram_bw_table.num_entries = soc_bb-&gt;clk_table.uclk.num_clk_values;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)</div><div class='add'>+{</div><div class='add'>+	bool result;</div><div class='add'>+	bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_equal = false;</div><div class='add'>+</div><div class='add'>+	if (!soc_bb || !min_table)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.dcfclk.num_clk_values &lt; 2 || soc_bb-&gt;clk_table.fclk.num_clk_values &lt; 2)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.uclk.num_clk_values &gt; DML_MCG_MAX_CLK_TABLE_SIZE)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.dcfclk.num_clk_values == 2) {</div><div class='add'>+		dcfclk_fine_grained = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.fclk.num_clk_values == 2) {</div><div class='add'>+		fclk_fine_grained = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (soc_bb-&gt;clk_table.fclk.num_clk_values == soc_bb-&gt;clk_table.dcfclk.num_clk_values &amp;&amp;</div><div class='add'>+		soc_bb-&gt;clk_table.fclk.num_clk_values == soc_bb-&gt;clk_table.uclk.num_clk_values)</div><div class='add'>+		clock_state_count_equal = true;</div><div class='add'>+</div><div class='add'>+	min_table-&gt;fixed_clocks_khz.amclk = 0;</div><div class='add'>+	min_table-&gt;fixed_clocks_khz.dprefclk = soc_bb-&gt;dprefclk_mhz * 1000;</div><div class='add'>+	min_table-&gt;fixed_clocks_khz.pcierefclk = soc_bb-&gt;pcie_refclk_mhz * 1000;</div><div class='add'>+	min_table-&gt;fixed_clocks_khz.dchubrefclk = soc_bb-&gt;dchub_refclk_mhz * 1000;</div><div class='add'>+	min_table-&gt;fixed_clocks_khz.xtalclk = soc_bb-&gt;xtalclk_mhz * 1000;</div><div class='add'>+</div><div class='add'>+	min_table-&gt;max_clocks_khz.dispclk = soc_bb-&gt;clk_table.dispclk.clk_values_khz[soc_bb-&gt;clk_table.dispclk.num_clk_values - 1];</div><div class='add'>+	min_table-&gt;max_clocks_khz.dppclk = soc_bb-&gt;clk_table.dppclk.clk_values_khz[soc_bb-&gt;clk_table.dppclk.num_clk_values - 1];</div><div class='add'>+	min_table-&gt;max_clocks_khz.dscclk = soc_bb-&gt;clk_table.dscclk.clk_values_khz[soc_bb-&gt;clk_table.dscclk.num_clk_values - 1];</div><div class='add'>+	min_table-&gt;max_clocks_khz.dtbclk = soc_bb-&gt;clk_table.dtbclk.clk_values_khz[soc_bb-&gt;clk_table.dtbclk.num_clk_values - 1];</div><div class='add'>+	min_table-&gt;max_clocks_khz.phyclk = soc_bb-&gt;clk_table.phyclk.clk_values_khz[soc_bb-&gt;clk_table.phyclk.num_clk_values - 1];</div><div class='add'>+</div><div class='add'>+	min_table-&gt;max_ss_clocks_khz.dispclk = (unsigned int)((double)min_table-&gt;max_clocks_khz.dispclk / (1.0 + soc_bb-&gt;dcn_downspread_percent / 100.0));</div><div class='add'>+	min_table-&gt;max_ss_clocks_khz.dppclk = (unsigned int)((double)min_table-&gt;max_clocks_khz.dppclk / (1.0 + soc_bb-&gt;dcn_downspread_percent / 100.0));</div><div class='add'>+	min_table-&gt;max_ss_clocks_khz.dtbclk = (unsigned int)((double)min_table-&gt;max_clocks_khz.dtbclk / (1.0 + soc_bb-&gt;dcn_downspread_percent / 100.0));</div><div class='add'>+</div><div class='add'>+	min_table-&gt;max_clocks_khz.dcfclk = soc_bb-&gt;clk_table.dcfclk.clk_values_khz[soc_bb-&gt;clk_table.dcfclk.num_clk_values - 1];</div><div class='add'>+	min_table-&gt;max_clocks_khz.fclk = soc_bb-&gt;clk_table.fclk.clk_values_khz[soc_bb-&gt;clk_table.fclk.num_clk_values - 1];</div><div class='add'>+</div><div class='add'>+	if (dcfclk_fine_grained || fclk_fine_grained || !clock_state_count_equal)</div><div class='add'>+		result = build_min_clk_table_fine_grained(soc_bb, min_table);</div><div class='add'>+	else</div><div class='add'>+		result = build_min_clk_table_coarse_grained(soc_bb, min_table);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h<br/>new file mode 100644<br/>index 000000000000..f54fde8fba90<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_MCG_DCN4_H__</div><div class='add'>+#define __DML2_MCG_DCN4_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+</div><div class='add'>+bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);</div><div class='add'>+bool mcg_dcn4_unit_test(void);</div><div class='add'>+</div><div class='add'>+#endif
\ No newline at end of file</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c<br/>new file mode 100644<br/>index 000000000000..c60b8fe90819<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_mcg_factory.h"</div><div class='add'>+#include "dml2_mcg_dcn4.h"</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+</div><div class='add'>+static bool dummy_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *out)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (!out)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memset(out, 0, sizeof(struct dml2_mcg_instance));</div><div class='add'>+</div><div class='add'>+	switch (project_id) {</div><div class='add'>+	case dml2_project_dcn4x_stage1:</div><div class='add'>+		out-&gt;build_min_clock_table = &amp;dummy_build_min_clock_table;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_dcn4x_stage2:</div><div class='add'>+	case dml2_project_dcn4x_stage2_auto_drr_svp:</div><div class='add'>+		out-&gt;build_min_clock_table = &amp;mcg_dcn4_build_min_clock_table;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_invalid:</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h<br/>new file mode 100644<br/>index 000000000000..ad307deca3b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_MCG_FACTORY_H__</div><div class='add'>+#define __DML2_MCG_FACTORY_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c<br/>new file mode 100644<br/>index 000000000000..1b9579a32ff2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c</a></div><div class='hunk'>@@ -0,0 +1,706 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_pmo_factory.h"</div><div class='add'>+#include "dml2_pmo_dcn3.h"</div><div class='add'>+</div><div class='add'>+static void sort(double *list_a, int list_a_size)</div><div class='add'>+{</div><div class='add'>+	// For all elements b[i] in list_b[]</div><div class='add'>+	for (int i = 0; i &lt; list_a_size - 1; i++) {</div><div class='add'>+		// Find the first element of list_a that's larger than b[i]</div><div class='add'>+		for (int j = i; j &lt; list_a_size - 1; j++) {</div><div class='add'>+			if (list_a[j] &gt; list_a[j + 1])</div><div class='add'>+				swap(list_a[j], list_a[j + 1]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static double get_max_reserved_time_on_all_planes_with_stream_index(struct display_configuation_with_meta *config, unsigned int stream_index)</div><div class='add'>+{</div><div class='add'>+	struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+	long max_reserved_time_ns = 0;</div><div class='add'>+</div><div class='add'>+	for (unsigned int i = 0; i &lt; config-&gt;display_config.num_planes; i++) {</div><div class='add'>+		plane_descriptor = &amp;config-&gt;display_config.plane_descriptors[i];</div><div class='add'>+</div><div class='add'>+		if (plane_descriptor-&gt;stream_index == stream_index)</div><div class='add'>+			if (plane_descriptor-&gt;overrides.reserved_vblank_time_ns &gt; max_reserved_time_ns)</div><div class='add'>+				max_reserved_time_ns = plane_descriptor-&gt;overrides.reserved_vblank_time_ns;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return (max_reserved_time_ns / 1000.0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void set_reserved_time_on_all_planes_with_stream_index(struct display_configuation_with_meta *config, unsigned int stream_index, double reserved_time_us)</div><div class='add'>+{</div><div class='add'>+	struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+</div><div class='add'>+	for (unsigned int i = 0; i &lt; config-&gt;display_config.num_planes; i++) {</div><div class='add'>+		plane_descriptor = &amp;config-&gt;display_config.plane_descriptors[i];</div><div class='add'>+</div><div class='add'>+		if (plane_descriptor-&gt;stream_index == stream_index)</div><div class='add'>+			plane_descriptor-&gt;overrides.reserved_vblank_time_ns = (long int)(reserved_time_us * 1000);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void remove_duplicates(double *list_a, int *list_a_size)</div><div class='add'>+{</div><div class='add'>+	int j = 0;</div><div class='add'>+</div><div class='add'>+	if (*list_a_size == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (int i = 1; i &lt; *list_a_size; i++) {</div><div class='add'>+		if (list_a[j] != list_a[i]) {</div><div class='add'>+			j++;</div><div class='add'>+			list_a[j] = list_a[i];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*list_a_size = j + 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit)</div><div class='add'>+{</div><div class='add'>+	if (*mpc_combine_factor &lt; limit) {</div><div class='add'>+		(*mpc_combine_factor)++;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool optimize_dcc_mcache_no_odm(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out,</div><div class='add'>+	int free_pipes)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;optimized_display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		// For pipes that failed dcc mcache check, we want to increase the pipe count.</div><div class='add'>+		// The logic for doing this depends on how many pipes is already being used,</div><div class='add'>+		// and whether it's mpcc or odm combine.</div><div class='add'>+		if (!in_out-&gt;dcc_mcache_supported[i]) {</div><div class='add'>+			// For the general case of "n displays", we can only optimize streams with an ODM combine factor of 1</div><div class='add'>+			if (in_out-&gt;cfg_support_info-&gt;stream_support_info[in_out-&gt;optimized_display_cfg-&gt;plane_descriptors[i].stream_index].odms_used == 1) {</div><div class='add'>+				in_out-&gt;optimized_display_cfg-&gt;plane_descriptors[i].overrides.mpcc_combine_factor =</div><div class='add'>+					in_out-&gt;cfg_support_info-&gt;plane_support_info[i].dpps_used;</div><div class='add'>+				// For each plane that is not passing mcache validation, just add another pipe to it, up to the limit.</div><div class='add'>+				if (free_pipes &gt; 0) {</div><div class='add'>+					if (!increase_mpc_combine_factor(&amp;in_out-&gt;optimized_display_cfg-&gt;plane_descriptors[i].overrides.mpcc_combine_factor,</div><div class='add'>+						pmo-&gt;mpc_combine_limit)) {</div><div class='add'>+						// We've reached max pipes allocatable to a single plane, so we fail.</div><div class='add'>+						result = false;</div><div class='add'>+						break;</div><div class='add'>+					} else {</div><div class='add'>+						// Successfully added another pipe to this failing plane.</div><div class='add'>+						free_pipes--;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					// No free pipes to add.</div><div class='add'>+					result = false;</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				// If the stream of this plane needs ODM combine, no further optimization can be done.</div><div class='add'>+				result = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool iterate_to_next_candidiate(struct dml2_pmo_instance *pmo, int size)</div><div class='add'>+{</div><div class='add'>+	int borrow_from, i;</div><div class='add'>+	bool success = false;</div><div class='add'>+</div><div class='add'>+	if (pmo-&gt;scratch.pmo_dcn3.current_candidate[0] &gt; 0) {</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn3.current_candidate[0]--;</div><div class='add'>+		success = true;</div><div class='add'>+	} else {</div><div class='add'>+		for (borrow_from = 1; borrow_from &lt; size &amp;&amp; pmo-&gt;scratch.pmo_dcn3.current_candidate[borrow_from] == 0; borrow_from++)</div><div class='add'>+			;</div><div class='add'>+</div><div class='add'>+		if (borrow_from &lt; size) {</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.current_candidate[borrow_from]--;</div><div class='add'>+			for (i = 0; i &lt; borrow_from; i++) {</div><div class='add'>+				pmo-&gt;scratch.pmo_dcn3.current_candidate[i] = pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates_count[i] - 1;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)</div><div class='add'>+{</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='add'>+	if (*odm_mode == dml2_odm_mode_auto) {</div><div class='add'>+		switch (odms_calculated) {</div><div class='add'>+		case 1:</div><div class='add'>+			*odm_mode = dml2_odm_mode_bypass;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_2to1;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_3to1;</div><div class='add'>+			break;</div><div class='add'>+		case 4:</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_4to1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			result = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		if (*odm_mode == dml2_odm_mode_bypass) {</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_2to1;</div><div class='add'>+		} else if (*odm_mode == dml2_odm_mode_combine_2to1) {</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_3to1;</div><div class='add'>+		} else if (*odm_mode == dml2_odm_mode_combine_3to1) {</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_4to1;</div><div class='add'>+		} else {</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int stream_index)</div><div class='add'>+{</div><div class='add'>+	unsigned int i, count;</div><div class='add'>+</div><div class='add'>+	count = 0;</div><div class='add'>+	for (i = 0; i &lt; display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[i].stream_index == stream_index)</div><div class='add'>+			count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool are_timings_trivially_synchronizable(struct display_configuation_with_meta *display_config, int mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool identical = true;</div><div class='add'>+	bool contains_drr = false;</div><div class='add'>+	unsigned int remap_array[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int remap_array_size = 0;</div><div class='add'>+</div><div class='add'>+	// Create a remap array to enable simple iteration through only masked stream indicies</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;display_config.num_streams; i++) {</div><div class='add'>+		if (mask &amp; (0x1 &lt;&lt; i)) {</div><div class='add'>+			remap_array[remap_array_size++] = i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// 0 or 1 display is always trivially synchronizable</div><div class='add'>+	if (remap_array_size &lt;= 1)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	for (i = 1; i &lt; remap_array_size; i++) {</div><div class='add'>+		if (memcmp(&amp;display_config-&gt;display_config.stream_descriptors[remap_array[i - 1]].timing,</div><div class='add'>+			&amp;display_config-&gt;display_config.stream_descriptors[remap_array[i]].timing,</div><div class='add'>+			sizeof(struct dml2_timing_cfg))) {</div><div class='add'>+			identical = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; remap_array_size; i++) {</div><div class='add'>+		if (display_config-&gt;display_config.stream_descriptors[remap_array[i]].timing.drr_config.enabled) {</div><div class='add'>+			contains_drr = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return !contains_drr &amp;&amp; identical;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_initialize(struct dml2_pmo_initialize_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	pmo-&gt;soc_bb = in_out-&gt;soc_bb;</div><div class='add'>+	pmo-&gt;ip_caps = in_out-&gt;ip_caps;</div><div class='add'>+	pmo-&gt;mpc_combine_limit = 2;</div><div class='add'>+	pmo-&gt;odm_combine_limit = 4;</div><div class='add'>+	pmo-&gt;mcg_clock_table_size = in_out-&gt;mcg_clock_table_size;</div><div class='add'>+</div><div class='add'>+	pmo-&gt;options = in_out-&gt;options;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Htotal, Hblank start/end, and Hsync start/end all must be divisible</div><div class='add'>+	 * in order for the horizontal timing params to be considered divisible</div><div class='add'>+	 * by 2. Hsync start is always 0.</div><div class='add'>+	 */</div><div class='add'>+	unsigned long h_blank_start = timing-&gt;h_total - timing-&gt;h_front_porch;</div><div class='add'>+</div><div class='add'>+	return (timing-&gt;h_total % denominator == 0) &amp;&amp;</div><div class='add'>+			(h_blank_start % denominator == 0) &amp;&amp;</div><div class='add'>+			(timing-&gt;h_blank_end % denominator == 0) &amp;&amp;</div><div class='add'>+			(timing-&gt;h_sync_width % denominator == 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_dp_encoder(enum dml2_output_encoder_class encoder_type)</div><div class='add'>+{</div><div class='add'>+	switch (encoder_type) {</div><div class='add'>+	case dml2_dp:</div><div class='add'>+	case dml2_edp:</div><div class='add'>+	case dml2_dp2p0:</div><div class='add'>+	case dml2_none:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_hdmi:</div><div class='add'>+	case dml2_hdmifrl:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	const struct dml2_display_cfg *display_config =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;display_config;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;mode_support_result;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm ||</div><div class='add'>+			(in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm_for_multi_stream &amp;&amp; display_config-&gt;num_streams &gt; 1))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_planes; i++)</div><div class='add'>+		/*</div><div class='add'>+		 * vmin optimization is required to be seamlessly switched off</div><div class='add'>+		 * at any time when the new configuration is no longer</div><div class='add'>+		 * supported. However switching from ODM combine to MPC combine</div><div class='add'>+		 * is not always seamless. When there not enough free pipes, we</div><div class='add'>+		 * will have to use the same secondary OPP heads as secondary</div><div class='add'>+		 * DPP pipes in MPC combine in new state. This transition is</div><div class='add'>+		 * expected to cause glitches. To avoid the transition, we only</div><div class='add'>+		 * allow vmin optimization if the stream's base configuration</div><div class='add'>+		 * doesn't require MPC combine. This condition checks if MPC</div><div class='add'>+		 * combine is enabled. If so do not optimize the stream.</div><div class='add'>+		 */</div><div class='add'>+		if (mode_support_result-&gt;cfg_support_info.plane_support_info[i].dpps_used &gt; 1 &amp;&amp;</div><div class='add'>+				mode_support_result-&gt;cfg_support_info.stream_support_info[display_config-&gt;plane_descriptors[i].stream_index].odms_used == 1)</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[display_config-&gt;plane_descriptors[i].stream_index] = true;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_streams; i++) {</div><div class='add'>+		if (display_config-&gt;stream_descriptors[i].overrides.disable_dynamic_odm)</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[i] = true;</div><div class='add'>+		else if (in_out-&gt;base_display_config-&gt;stage3.stream_svp_meta[i].valid &amp;&amp;</div><div class='add'>+				in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm_for_stream_with_svp)</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[i] = true;</div><div class='add'>+		/*</div><div class='add'>+		 * ODM Combine requires horizontal timing divisible by 2 so each</div><div class='add'>+		 * ODM segment has the same size.</div><div class='add'>+		 */</div><div class='add'>+		else if (!is_h_timing_divisible_by(&amp;display_config-&gt;stream_descriptors[i].timing, 2))</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[i] = true;</div><div class='add'>+		/*</div><div class='add'>+		 * Our hardware support seamless ODM transitions for DP encoders</div><div class='add'>+		 * only.</div><div class='add'>+		 */</div><div class='add'>+		else if (!is_dp_encoder(display_config-&gt;stream_descriptors[i].output.output_encoder))</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[i] = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool is_vmin = true;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;vmin_limits-&gt;dispclk_khz &gt; 0 &amp;&amp;</div><div class='add'>+		in_out-&gt;display_config-&gt;mode_support_result.global.dispclk_khz &gt; in_out-&gt;vmin_limits-&gt;dispclk_khz)</div><div class='add'>+		is_vmin = false;</div><div class='add'>+</div><div class='add'>+	return is_vmin;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int find_highest_odm_load_stream_index(</div><div class='add'>+		const struct dml2_display_cfg *display_config,</div><div class='add'>+		const struct dml2_core_mode_support_result *mode_support_result)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int odm_load, highest_odm_load = -1, highest_odm_load_index = -1;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_streams; i++) {</div><div class='add'>+		if (mode_support_result-&gt;cfg_support_info.stream_support_info[i].odms_used &gt; 0)</div><div class='add'>+			odm_load = display_config-&gt;stream_descriptors[i].timing.pixel_clock_khz</div><div class='add'>+				/ mode_support_result-&gt;cfg_support_info.stream_support_info[i].odms_used;</div><div class='add'>+		else</div><div class='add'>+			odm_load = 0;</div><div class='add'>+</div><div class='add'>+		if (odm_load &gt; highest_odm_load) {</div><div class='add'>+			highest_odm_load_index = i;</div><div class='add'>+			highest_odm_load = odm_load;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return highest_odm_load_index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int stream_index;</div><div class='add'>+	const struct dml2_display_cfg *display_config =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;display_config;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;mode_support_result;</div><div class='add'>+	unsigned int odms_used;</div><div class='add'>+	struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+	bool optimizable = false;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * highest odm load stream must be optimizable to continue as dispclk is</div><div class='add'>+	 * bounded by it.</div><div class='add'>+	 */</div><div class='add'>+	stream_index = find_highest_odm_load_stream_index(display_config,</div><div class='add'>+			mode_support_result);</div><div class='add'>+</div><div class='add'>+	if (stream_index &lt; 0 ||</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[stream_index])</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	odms_used = mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].odms_used;</div><div class='add'>+	if ((int)odms_used &gt;= in_out-&gt;instance-&gt;odm_combine_limit)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memcpy(in_out-&gt;optimized_display_config,</div><div class='add'>+			in_out-&gt;base_display_config,</div><div class='add'>+			sizeof(struct display_configuation_with_meta));</div><div class='add'>+</div><div class='add'>+	stream_descriptor = &amp;in_out-&gt;optimized_display_config-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+	while (!optimizable &amp;&amp; increase_odm_combine_factor(</div><div class='add'>+			&amp;stream_descriptor-&gt;overrides.odm_mode,</div><div class='add'>+			odms_used)) {</div><div class='add'>+		switch (stream_descriptor-&gt;overrides.odm_mode) {</div><div class='add'>+		case dml2_odm_mode_combine_2to1:</div><div class='add'>+			optimizable = true;</div><div class='add'>+			break;</div><div class='add'>+		case dml2_odm_mode_combine_3to1:</div><div class='add'>+			/*</div><div class='add'>+			 * In ODM Combine 3:1 OTG_valid_pixel rate is 1/4 of</div><div class='add'>+			 * actual pixel rate. Therefore horizontal timing must</div><div class='add'>+			 * be divisible by 4.</div><div class='add'>+			 */</div><div class='add'>+			if (is_h_timing_divisible_by(&amp;display_config-&gt;stream_descriptors[stream_index].timing, 4)) {</div><div class='add'>+				if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].dsc_enable) {</div><div class='add'>+					/*</div><div class='add'>+					 * DSC h slice count must be divisible</div><div class='add'>+					 * by 3.</div><div class='add'>+					 */</div><div class='add'>+					if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].num_dsc_slices % 3 == 0)</div><div class='add'>+						optimizable = true;</div><div class='add'>+				} else {</div><div class='add'>+					optimizable = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case dml2_odm_mode_combine_4to1:</div><div class='add'>+			/*</div><div class='add'>+			 * In ODM Combine 4:1 OTG_valid_pixel rate is 1/4 of</div><div class='add'>+			 * actual pixel rate. Therefore horizontal timing must</div><div class='add'>+			 * be divisible by 4.</div><div class='add'>+			 */</div><div class='add'>+			if (is_h_timing_divisible_by(&amp;display_config-&gt;stream_descriptors[stream_index].timing, 4)) {</div><div class='add'>+				if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].dsc_enable) {</div><div class='add'>+					/*</div><div class='add'>+					 * DSC h slice count must be divisible</div><div class='add'>+					 * by 4.</div><div class='add'>+					 */</div><div class='add'>+					if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].num_dsc_slices % 4 == 0)</div><div class='add'>+						optimizable = true;</div><div class='add'>+				} else {</div><div class='add'>+					optimizable = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case dml2_odm_mode_auto:</div><div class='add'>+		case dml2_odm_mode_bypass:</div><div class='add'>+		case dml2_odm_mode_split_1to2:</div><div class='add'>+		case dml2_odm_mode_mso_1to2:</div><div class='add'>+		case dml2_odm_mode_mso_1to4:</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return optimizable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int i, used_pipes, free_pipes, planes_on_stream;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;display_config != in_out-&gt;optimized_display_cfg) {</div><div class='add'>+		memcpy(in_out-&gt;optimized_display_cfg, in_out-&gt;display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//Count number of free pipes, and check if any odm combine is in use.</div><div class='add'>+	used_pipes = 0;</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;optimized_display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		used_pipes += in_out-&gt;cfg_support_info-&gt;plane_support_info[i].dpps_used;</div><div class='add'>+	}</div><div class='add'>+	free_pipes = pmo-&gt;ip_caps-&gt;pipe_count - used_pipes;</div><div class='add'>+</div><div class='add'>+	// Optimization loop</div><div class='add'>+	// The goal here is to add more pipes to any planes</div><div class='add'>+	// which are failing mcache admissibility</div><div class='add'>+	result = true;</div><div class='add'>+</div><div class='add'>+	// The optimization logic depends on whether ODM combine is enabled, and the stream count.</div><div class='add'>+	if (in_out-&gt;optimized_display_cfg-&gt;num_streams &gt; 1) {</div><div class='add'>+		// If there are multiple streams, we are limited to only be able to optimize mcache failures on planes</div><div class='add'>+		// which are not ODM combined.</div><div class='add'>+</div><div class='add'>+		result = optimize_dcc_mcache_no_odm(in_out, free_pipes);</div><div class='add'>+	} else if (in_out-&gt;optimized_display_cfg-&gt;num_streams == 1) {</div><div class='add'>+		// In single stream cases, we still optimize mcache failures when there's ODM combine with some</div><div class='add'>+		// additional logic.</div><div class='add'>+</div><div class='add'>+		if (in_out-&gt;cfg_support_info-&gt;stream_support_info[0].odms_used &gt; 1) {</div><div class='add'>+			// If ODM combine is enabled, then the logic is to increase ODM combine factor.</div><div class='add'>+</div><div class='add'>+			// Optimization for streams with &gt; 1 ODM combine factor is only supported for single display.</div><div class='add'>+			planes_on_stream = count_planes_with_stream_index(in_out-&gt;optimized_display_cfg, 0);</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; in_out-&gt;optimized_display_cfg-&gt;num_planes; i++) {</div><div class='add'>+				// For pipes that failed dcc mcache check, we want to increase the pipe count.</div><div class='add'>+				// The logic for doing this depends on how many pipes is already being used,</div><div class='add'>+				// and whether it's mpcc or odm combine.</div><div class='add'>+				if (!in_out-&gt;dcc_mcache_supported[i]) {</div><div class='add'>+					// Increasing ODM combine factor on a stream requires a free pipe for each plane on the stream.</div><div class='add'>+					if (free_pipes &gt;= planes_on_stream) {</div><div class='add'>+						if (!increase_odm_combine_factor(&amp;in_out-&gt;optimized_display_cfg-&gt;stream_descriptors[i].overrides.odm_mode,</div><div class='add'>+							in_out-&gt;cfg_support_info-&gt;plane_support_info[i].dpps_used)) {</div><div class='add'>+							result = false;</div><div class='add'>+						} else {</div><div class='add'>+							break;</div><div class='add'>+						}</div><div class='add'>+					} else {</div><div class='add'>+						result = false;</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			// If ODM combine is not enabled, then we can actually use the same logic as before.</div><div class='add'>+</div><div class='add'>+			result = optimize_dcc_mcache_no_odm(in_out, free_pipes);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		result = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+	struct dml2_optimization_stage3_state *state = &amp;in_out-&gt;base_display_config-&gt;stage3;</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+	unsigned int stream_index, plane_index, candidate_count;</div><div class='add'>+	double min_reserved_vblank_time = 0;</div><div class='add'>+	int fclk_twait_needed_mask = 0x0;</div><div class='add'>+	int uclk_twait_needed_mask = 0x0;</div><div class='add'>+</div><div class='add'>+	state-&gt;performed = true;</div><div class='add'>+	state-&gt;min_clk_index_for_latency = in_out-&gt;base_display_config-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn3.min_latency_index = in_out-&gt;base_display_config-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn3.max_latency_index = pmo-&gt;mcg_clock_table_size - 1;</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn3.cur_latency_index = in_out-&gt;base_display_config-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn3.stream_mask = 0xF;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; in_out-&gt;base_display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		plane_descriptor = &amp;in_out-&gt;base_display_config-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+		stream_descriptor = &amp;in_out-&gt;base_display_config-&gt;display_config.stream_descriptors[plane_descriptor-&gt;stream_index];</div><div class='add'>+</div><div class='add'>+		if (in_out-&gt;base_display_config-&gt;mode_support_result.cfg_support_info.plane_support_info[plane_index].active_latency_hiding_us &lt;</div><div class='add'>+			in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;overrides.hw.twait_budgeting.uclk_pstate == dml2_twait_budgeting_setting_if_needed)</div><div class='add'>+			uclk_twait_needed_mask |= (0x1 &lt;&lt; plane_descriptor-&gt;stream_index);</div><div class='add'>+</div><div class='add'>+		if (stream_descriptor-&gt;overrides.hw.twait_budgeting.uclk_pstate == dml2_twait_budgeting_setting_try)</div><div class='add'>+			uclk_twait_needed_mask |= (0x1 &lt;&lt; plane_descriptor-&gt;stream_index);</div><div class='add'>+</div><div class='add'>+		if (in_out-&gt;base_display_config-&gt;mode_support_result.cfg_support_info.plane_support_info[plane_index].active_latency_hiding_us &lt;</div><div class='add'>+			in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;overrides.hw.twait_budgeting.fclk_pstate == dml2_twait_budgeting_setting_if_needed)</div><div class='add'>+			fclk_twait_needed_mask |= (0x1 &lt;&lt; plane_descriptor-&gt;stream_index);</div><div class='add'>+</div><div class='add'>+		if (stream_descriptor-&gt;overrides.hw.twait_budgeting.fclk_pstate == dml2_twait_budgeting_setting_try)</div><div class='add'>+			fclk_twait_needed_mask |= (0x1 &lt;&lt; plane_descriptor-&gt;stream_index);</div><div class='add'>+</div><div class='add'>+		if (plane_descriptor-&gt;overrides.legacy_svp_config != dml2_svp_mode_override_auto) {</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.stream_mask &amp;= ~(0x1 &lt;&lt; plane_descriptor-&gt;stream_index);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (stream_index = 0; stream_index &lt; in_out-&gt;base_display_config-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		stream_descriptor = &amp;in_out-&gt;base_display_config-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+</div><div class='add'>+		// The absolute minimum required time is the minimum of all the required budgets</div><div class='add'>+		/*</div><div class='add'>+		if (stream_descriptor-&gt;overrides.hw.twait_budgeting.fclk_pstate</div><div class='add'>+			== dml2_twait_budgeting_setting_require)</div><div class='add'>+</div><div class='add'>+			if (are_timings_trivially_synchronizable(in_out-&gt;base_display_config, pmo-&gt;scratch.pmo_dcn3.stream_mask)) {</div><div class='add'>+				min_reserved_vblank_time = max_double2(min_reserved_vblank_time,</div><div class='add'>+					in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+		if (stream_descriptor-&gt;overrides.hw.twait_budgeting.uclk_pstate</div><div class='add'>+			== dml2_twait_budgeting_setting_require) {</div><div class='add'>+</div><div class='add'>+			if (are_timings_trivially_synchronizable(in_out-&gt;base_display_config, pmo-&gt;scratch.pmo_dcn3.stream_mask)) {</div><div class='add'>+				min_reserved_vblank_time = max_double2(min_reserved_vblank_time,</div><div class='add'>+					in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (stream_descriptor-&gt;overrides.hw.twait_budgeting.stutter_enter_exit</div><div class='add'>+			== dml2_twait_budgeting_setting_require)</div><div class='add'>+			min_reserved_vblank_time = max_double2(min_reserved_vblank_time,</div><div class='add'>+				in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us);</div><div class='add'>+		*/</div><div class='add'>+</div><div class='add'>+		min_reserved_vblank_time = get_max_reserved_time_on_all_planes_with_stream_index(in_out-&gt;base_display_config, stream_index);</div><div class='add'>+</div><div class='add'>+		// Insert the absolute minimum into the array</div><div class='add'>+		candidate_count = 1;</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index][0] = min_reserved_vblank_time;</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] = candidate_count;</div><div class='add'>+</div><div class='add'>+		if (!(pmo-&gt;scratch.pmo_dcn3.stream_mask &amp; (0x1 &lt;&lt; stream_index)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		// For every optional feature, we create a candidate for it only if it's larger minimum.</div><div class='add'>+		if ((fclk_twait_needed_mask &amp; (0x1 &lt;&lt; stream_index)) &amp;&amp;</div><div class='add'>+			in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us &gt; min_reserved_vblank_time) {</div><div class='add'>+</div><div class='add'>+			if (are_timings_trivially_synchronizable(in_out-&gt;base_display_config, pmo-&gt;scratch.pmo_dcn3.stream_mask)) {</div><div class='add'>+				pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =</div><div class='add'>+					in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.fclk_change_blackout_us;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((uclk_twait_needed_mask &amp; (0x1 &lt;&lt; stream_index)) &amp;&amp;</div><div class='add'>+			in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us &gt; min_reserved_vblank_time) {</div><div class='add'>+</div><div class='add'>+			if (are_timings_trivially_synchronizable(in_out-&gt;base_display_config, pmo-&gt;scratch.pmo_dcn3.stream_mask)) {</div><div class='add'>+				pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =</div><div class='add'>+					in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((stream_descriptor-&gt;overrides.hw.twait_budgeting.stutter_enter_exit == dml2_twait_budgeting_setting_try ||</div><div class='add'>+			stream_descriptor-&gt;overrides.hw.twait_budgeting.stutter_enter_exit == dml2_twait_budgeting_setting_if_needed) &amp;&amp;</div><div class='add'>+			in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us &gt; min_reserved_vblank_time) {</div><div class='add'>+</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index][candidate_count++] =</div><div class='add'>+				in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] = candidate_count;</div><div class='add'>+</div><div class='add'>+		// Finally sort the array of candidates</div><div class='add'>+		sort(pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index],</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates_count[stream_index]);</div><div class='add'>+</div><div class='add'>+		remove_duplicates(pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index],</div><div class='add'>+			&amp;pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates_count[stream_index]);</div><div class='add'>+</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn3.current_candidate[stream_index] =</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates_count[stream_index] - 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int i, stream_index;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;base_display_config-&gt;display_config.num_planes; i++) {</div><div class='add'>+		stream_index = in_out-&gt;base_display_config-&gt;display_config.plane_descriptors[i].stream_index;</div><div class='add'>+</div><div class='add'>+		if (in_out-&gt;base_display_config-&gt;display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns &lt;</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index][pmo-&gt;scratch.pmo_dcn3.current_candidate[stream_index]] * 1000) {</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+	bool success = false;</div><div class='add'>+	bool reached_end;</div><div class='add'>+</div><div class='add'>+	memcpy(in_out-&gt;optimized_display_config, in_out-&gt;base_display_config, sizeof(struct display_configuation_with_meta));</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;last_candidate_failed) {</div><div class='add'>+		if (pmo-&gt;scratch.pmo_dcn3.cur_latency_index &lt; pmo-&gt;scratch.pmo_dcn3.max_latency_index) {</div><div class='add'>+			// If we haven't tried all the clock bounds to support this state, try a higher one</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn3.cur_latency_index++;</div><div class='add'>+</div><div class='add'>+			success = true;</div><div class='add'>+		} else {</div><div class='add'>+			// If there's nothing higher to try, then we have to have a smaller canadidate</div><div class='add'>+			reached_end = !iterate_to_next_candidiate(pmo, in_out-&gt;optimized_display_config-&gt;display_config.num_streams);</div><div class='add'>+</div><div class='add'>+			if (!reached_end) {</div><div class='add'>+				pmo-&gt;scratch.pmo_dcn3.cur_latency_index = pmo-&gt;scratch.pmo_dcn3.min_latency_index;</div><div class='add'>+				success = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		success = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (success) {</div><div class='add'>+		in_out-&gt;optimized_display_config-&gt;stage3.min_clk_index_for_latency = pmo-&gt;scratch.pmo_dcn3.cur_latency_index;</div><div class='add'>+</div><div class='add'>+		for (stream_index = 0; stream_index &lt; in_out-&gt;optimized_display_config-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+			set_reserved_time_on_all_planes_with_stream_index(in_out-&gt;optimized_display_config, stream_index,</div><div class='add'>+				pmo-&gt;scratch.pmo_dcn3.reserved_time_candidates[stream_index][pmo-&gt;scratch.pmo_dcn3.current_candidate[stream_index]]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h<br/>new file mode 100644<br/>index 000000000000..f00bd9e72a86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_PMO_DCN3_H__</div><div class='add'>+#define __DML2_PMO_DCN3_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_initialize(struct dml2_pmo_initialize_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out);</div><div class='add'>+bool pmo_dcn3_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out);</div><div class='add'>+bool pmo_dcn3_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn3_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out);</div><div class='add'>+bool pmo_dcn3_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out);</div><div class='add'>+bool pmo_dcn3_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c<br/>new file mode 100644<br/>index 000000000000..c26e100fcaf2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c</a></div><div class='hunk'>@@ -0,0 +1,2390 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_pmo_factory.h"</div><div class='add'>+#include "dml2_debug.h"</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+#include "dml2_pmo_dcn4_fams2.h"</div><div class='add'>+</div><div class='add'>+static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding</div><div class='add'>+static const double MIN_BLANK_STUTTER_FACTOR = 3.0;</div><div class='add'>+</div><div class='add'>+static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = {</div><div class='add'>+	// VActive Preferred</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then SVP</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_svp, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then VBlank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then DRR</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_drr, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Finally VBlank, but allow base clocks for latency to increase</div><div class='add'>+	/*</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+	*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int base_strategy_list_1_display_size = sizeof(base_strategy_list_1_display) / sizeof(struct dml2_pmo_pstate_strategy);</div><div class='add'>+</div><div class='add'>+static const struct dml2_pmo_pstate_strategy base_strategy_list_2_display[] = {</div><div class='add'>+	// VActive only is preferred</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then VActive + VBlank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then VBlank only</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then SVP + VBlank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_svp, dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then SVP + DRR</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_svp, dml2_pstate_method_fw_drr, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then SVP + SVP</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_svp, dml2_pstate_method_fw_svp, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then DRR + VActive</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_fw_drr, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Then DRR + DRR</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_drr, dml2_pstate_method_fw_drr, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// Finally VBlank, but allow base clocks for latency to increase</div><div class='add'>+	/*</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+	*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int base_strategy_list_2_display_size = sizeof(base_strategy_list_2_display) / sizeof(struct dml2_pmo_pstate_strategy);</div><div class='add'>+</div><div class='add'>+static const struct dml2_pmo_pstate_strategy base_strategy_list_3_display[] = {</div><div class='add'>+	// All VActive</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// VActive + 1 VBlank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vblank, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// All VBlank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// All DRR</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_drr, dml2_pstate_method_fw_drr, dml2_pstate_method_fw_drr, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// All VBlank, with state increase allowed</div><div class='add'>+	/*</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_na },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+	*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int base_strategy_list_3_display_size = sizeof(base_strategy_list_3_display) / sizeof(struct dml2_pmo_pstate_strategy);</div><div class='add'>+</div><div class='add'>+static const struct dml2_pmo_pstate_strategy base_strategy_list_4_display[] = {</div><div class='add'>+	// All VActive</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vactive },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// VActive + 1 VBlank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vblank },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// All Vblank</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_vblank },</div><div class='add'>+		.allow_state_increase = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// All DRR</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_fw_drr, dml2_pstate_method_fw_drr, dml2_pstate_method_fw_drr, dml2_pstate_method_fw_drr },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// All VBlank, with state increase allowed</div><div class='add'>+	/*</div><div class='add'>+	{</div><div class='add'>+		.per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_vblank, dml2_pstate_method_vblank },</div><div class='add'>+		.allow_state_increase = true,</div><div class='add'>+	},</div><div class='add'>+	*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int base_strategy_list_4_display_size = sizeof(base_strategy_list_4_display) / sizeof(struct dml2_pmo_pstate_strategy);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool increase_odm_combine_factor(enum dml2_odm_mode *odm_mode, int odms_calculated)</div><div class='add'>+{</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='add'>+	if (*odm_mode == dml2_odm_mode_auto) {</div><div class='add'>+		switch (odms_calculated) {</div><div class='add'>+		case 1:</div><div class='add'>+			*odm_mode = dml2_odm_mode_bypass;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_2to1;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_3to1;</div><div class='add'>+			break;</div><div class='add'>+		case 4:</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_4to1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			result = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		if (*odm_mode == dml2_odm_mode_bypass) {</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_2to1;</div><div class='add'>+		} else if (*odm_mode == dml2_odm_mode_combine_2to1) {</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_3to1;</div><div class='add'>+		} else if (*odm_mode == dml2_odm_mode_combine_3to1) {</div><div class='add'>+			*odm_mode = dml2_odm_mode_combine_4to1;</div><div class='add'>+		} else {</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit)</div><div class='add'>+{</div><div class='add'>+	if (*mpc_combine_factor &lt; limit) {</div><div class='add'>+		(*mpc_combine_factor)++;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int count_planes_with_stream_index(const struct dml2_display_cfg *display_cfg, unsigned int stream_index)</div><div class='add'>+{</div><div class='add'>+	unsigned int i, count;</div><div class='add'>+</div><div class='add'>+	count = 0;</div><div class='add'>+	for (i = 0; i &lt; display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		if (display_cfg-&gt;plane_descriptors[i].stream_index == stream_index)</div><div class='add'>+			count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool optimize_dcc_mcache_no_odm(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out,</div><div class='add'>+	int free_pipes)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;optimized_display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		// For pipes that failed dcc mcache check, we want to increase the pipe count.</div><div class='add'>+		// The logic for doing this depends on how many pipes is already being used,</div><div class='add'>+		// and whether it's mpcc or odm combine.</div><div class='add'>+		if (!in_out-&gt;dcc_mcache_supported[i]) {</div><div class='add'>+			// For the general case of "n displays", we can only optimize streams with an ODM combine factor of 1</div><div class='add'>+			if (in_out-&gt;cfg_support_info-&gt;stream_support_info[in_out-&gt;optimized_display_cfg-&gt;plane_descriptors[i].stream_index].odms_used == 1) {</div><div class='add'>+				in_out-&gt;optimized_display_cfg-&gt;plane_descriptors[i].overrides.mpcc_combine_factor =</div><div class='add'>+					in_out-&gt;cfg_support_info-&gt;plane_support_info[i].dpps_used;</div><div class='add'>+				// For each plane that is not passing mcache validation, just add another pipe to it, up to the limit.</div><div class='add'>+				if (free_pipes &gt; 0) {</div><div class='add'>+					if (!increase_mpc_combine_factor(&amp;in_out-&gt;optimized_display_cfg-&gt;plane_descriptors[i].overrides.mpcc_combine_factor,</div><div class='add'>+						pmo-&gt;mpc_combine_limit)) {</div><div class='add'>+						// We've reached max pipes allocatable to a single plane, so we fail.</div><div class='add'>+						result = false;</div><div class='add'>+						break;</div><div class='add'>+					} else {</div><div class='add'>+						// Successfully added another pipe to this failing plane.</div><div class='add'>+						free_pipes--;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					// No free pipes to add.</div><div class='add'>+					result = false;</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				// If the stream of this plane needs ODM combine, no further optimization can be done.</div><div class='add'>+				result = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int i, used_pipes, free_pipes, planes_on_stream;</div><div class='add'>+	bool result;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;display_config != in_out-&gt;optimized_display_cfg) {</div><div class='add'>+		memcpy(in_out-&gt;optimized_display_cfg, in_out-&gt;display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//Count number of free pipes, and check if any odm combine is in use.</div><div class='add'>+	used_pipes = 0;</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;optimized_display_cfg-&gt;num_planes; i++) {</div><div class='add'>+		used_pipes += in_out-&gt;cfg_support_info-&gt;plane_support_info[i].dpps_used;</div><div class='add'>+	}</div><div class='add'>+	free_pipes = pmo-&gt;ip_caps-&gt;pipe_count - used_pipes;</div><div class='add'>+</div><div class='add'>+	// Optimization loop</div><div class='add'>+	// The goal here is to add more pipes to any planes</div><div class='add'>+	// which are failing mcache admissibility</div><div class='add'>+	result = true;</div><div class='add'>+</div><div class='add'>+	// The optimization logic depends on whether ODM combine is enabled, and the stream count.</div><div class='add'>+	if (in_out-&gt;optimized_display_cfg-&gt;num_streams &gt; 1 || in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm) {</div><div class='add'>+		// If there are multiple streams, we are limited to only be able to optimize mcache failures on planes</div><div class='add'>+		// which are not ODM combined.</div><div class='add'>+</div><div class='add'>+		result = optimize_dcc_mcache_no_odm(in_out, free_pipes);</div><div class='add'>+	} else if (in_out-&gt;optimized_display_cfg-&gt;num_streams == 1) {</div><div class='add'>+		// In single stream cases, we still optimize mcache failures when there's ODM combine with some</div><div class='add'>+		// additional logic.</div><div class='add'>+</div><div class='add'>+		if (in_out-&gt;cfg_support_info-&gt;stream_support_info[0].odms_used &gt; 1) {</div><div class='add'>+			// If ODM combine is enabled, then the logic is to increase ODM combine factor.</div><div class='add'>+</div><div class='add'>+			// Optimization for streams with &gt; 1 ODM combine factor is only supported for single display.</div><div class='add'>+			planes_on_stream = count_planes_with_stream_index(in_out-&gt;optimized_display_cfg, 0);</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; in_out-&gt;optimized_display_cfg-&gt;num_planes; i++) {</div><div class='add'>+				// For pipes that failed dcc mcache check, we want to increase the pipe count.</div><div class='add'>+				// The logic for doing this depends on how many pipes is already being used,</div><div class='add'>+				// and whether it's mpcc or odm combine.</div><div class='add'>+				if (!in_out-&gt;dcc_mcache_supported[i]) {</div><div class='add'>+					// Increasing ODM combine factor on a stream requires a free pipe for each plane on the stream.</div><div class='add'>+					if (free_pipes &gt;= planes_on_stream) {</div><div class='add'>+						if (!increase_odm_combine_factor(&amp;in_out-&gt;optimized_display_cfg-&gt;stream_descriptors[i].overrides.odm_mode,</div><div class='add'>+							in_out-&gt;cfg_support_info-&gt;plane_support_info[i].dpps_used)) {</div><div class='add'>+							result = false;</div><div class='add'>+						} else {</div><div class='add'>+							break;</div><div class='add'>+						}</div><div class='add'>+					} else {</div><div class='add'>+						result = false;</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			// If ODM combine is not enabled, then we can actually use the same logic as before.</div><div class='add'>+</div><div class='add'>+			result = optimize_dcc_mcache_no_odm(in_out, free_pipes);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		result = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_pstate_method convert_strategy_to_drr_variant(const enum dml2_pstate_method base_strategy)</div><div class='add'>+{</div><div class='add'>+	enum dml2_pstate_method variant_strategy = 0;</div><div class='add'>+</div><div class='add'>+	switch (base_strategy) {</div><div class='add'>+	case dml2_pstate_method_vactive:</div><div class='add'>+		variant_strategy = dml2_pstate_method_fw_vactive_drr;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_vblank:</div><div class='add'>+		variant_strategy = dml2_pstate_method_fw_vblank_drr;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_svp:</div><div class='add'>+		variant_strategy = dml2_pstate_method_fw_svp_drr;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_vactive_drr:</div><div class='add'>+	case dml2_pstate_method_fw_vblank_drr:</div><div class='add'>+	case dml2_pstate_method_fw_svp_drr:</div><div class='add'>+	case dml2_pstate_method_fw_drr:</div><div class='add'>+	case dml2_pstate_method_reserved_hw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_clamped:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_var:</div><div class='add'>+	case dml2_pstate_method_count:</div><div class='add'>+	case dml2_pstate_method_na:</div><div class='add'>+	default:</div><div class='add'>+		/* no variant for this mode */</div><div class='add'>+		variant_strategy = base_strategy;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return variant_strategy;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dml2_pmo_pstate_strategy *get_expanded_strategy_list(struct dml2_pmo_init_data *init_data, int stream_count)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_pstate_strategy *expanded_strategy_list = NULL;</div><div class='add'>+</div><div class='add'>+	switch (stream_count) {</div><div class='add'>+	case 1:</div><div class='add'>+		expanded_strategy_list = init_data-&gt;pmo_dcn4.expanded_strategy_list_1_display;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		expanded_strategy_list = init_data-&gt;pmo_dcn4.expanded_strategy_list_2_display;</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		expanded_strategy_list = init_data-&gt;pmo_dcn4.expanded_strategy_list_3_display;</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		expanded_strategy_list = init_data-&gt;pmo_dcn4.expanded_strategy_list_4_display;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return expanded_strategy_list;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_num_expanded_strategies(</div><div class='add'>+	struct dml2_pmo_init_data *init_data,</div><div class='add'>+	int stream_count)</div><div class='add'>+{</div><div class='add'>+	return init_data-&gt;pmo_dcn4.num_expanded_strategies_per_list[stream_count - 1];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void insert_strategy_into_expanded_list(</div><div class='add'>+	const struct dml2_pmo_pstate_strategy *per_stream_pstate_strategy,</div><div class='add'>+	const int stream_count,</div><div class='add'>+	struct dml2_pmo_pstate_strategy *expanded_strategy_list,</div><div class='add'>+	unsigned int *num_expanded_strategies)</div><div class='add'>+{</div><div class='add'>+	if (expanded_strategy_list &amp;&amp; num_expanded_strategies) {</div><div class='add'>+		memcpy(&amp;expanded_strategy_list[*num_expanded_strategies], per_stream_pstate_strategy, sizeof(struct dml2_pmo_pstate_strategy));</div><div class='add'>+</div><div class='add'>+		(*num_expanded_strategies)++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void expand_base_strategy(</div><div class='add'>+	const struct dml2_pmo_pstate_strategy *base_strategy,</div><div class='add'>+	const unsigned int stream_count,</div><div class='add'>+	struct dml2_pmo_pstate_strategy *expanded_strategy_list,</div><div class='add'>+	unsigned int *num_expanded_strategies)</div><div class='add'>+{</div><div class='add'>+	bool skip_to_next_stream;</div><div class='add'>+	bool expanded_strategy_added;</div><div class='add'>+	bool skip_iteration;</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+	unsigned int num_streams_per_method[PMO_DCN4_MAX_DISPLAYS] = { 0 };</div><div class='add'>+	unsigned int stream_iteration_indices[PMO_DCN4_MAX_DISPLAYS] = { 0 };</div><div class='add'>+	struct dml2_pmo_pstate_strategy cur_strategy_list = { 0 };</div><div class='add'>+</div><div class='add'>+	/* determine number of displays per method */</div><div class='add'>+	for (i = 0; i &lt; stream_count; i++) {</div><div class='add'>+		/* increment the count of the earliest index with the same method */</div><div class='add'>+		for (j = 0; j &lt; stream_count; j++) {</div><div class='add'>+			if (base_strategy-&gt;per_stream_pstate_method[i] == base_strategy-&gt;per_stream_pstate_method[j]) {</div><div class='add'>+				num_streams_per_method[j] = num_streams_per_method[j] + 1;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cur_strategy_list.allow_state_increase = base_strategy-&gt;allow_state_increase;</div><div class='add'>+</div><div class='add'>+	i = 0;</div><div class='add'>+	/* uses a while loop instead of recursion to build permutations of base strategy */</div><div class='add'>+	while (stream_iteration_indices[0] &lt; stream_count) {</div><div class='add'>+		skip_to_next_stream = false;</div><div class='add'>+		expanded_strategy_added = false;</div><div class='add'>+		skip_iteration = false;</div><div class='add'>+</div><div class='add'>+		/* determine what to do for this iteration */</div><div class='add'>+		if (stream_iteration_indices[i] &lt; stream_count &amp;&amp; num_streams_per_method[stream_iteration_indices[i]] != 0) {</div><div class='add'>+			/* decrement count and assign method */</div><div class='add'>+			cur_strategy_list.per_stream_pstate_method[i] = base_strategy-&gt;per_stream_pstate_method[stream_iteration_indices[i]];</div><div class='add'>+			num_streams_per_method[stream_iteration_indices[i]] -= 1;</div><div class='add'>+</div><div class='add'>+			if (i &gt;= stream_count - 1) {</div><div class='add'>+				/* insert into strategy list */</div><div class='add'>+				insert_strategy_into_expanded_list(&amp;cur_strategy_list, stream_count, expanded_strategy_list, num_expanded_strategies);</div><div class='add'>+				expanded_strategy_added = true;</div><div class='add'>+			} else {</div><div class='add'>+				/* skip to next stream */</div><div class='add'>+				skip_to_next_stream = true;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			skip_iteration = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* prepare for next iteration */</div><div class='add'>+		if (skip_to_next_stream) {</div><div class='add'>+			i++;</div><div class='add'>+		} else {</div><div class='add'>+			/* restore count */</div><div class='add'>+			if (!skip_iteration) {</div><div class='add'>+				num_streams_per_method[stream_iteration_indices[i]] += 1;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* increment iteration count */</div><div class='add'>+			stream_iteration_indices[i]++;</div><div class='add'>+</div><div class='add'>+			/* if iterations are complete, or last stream was reached */</div><div class='add'>+			if ((stream_iteration_indices[i] &gt;= stream_count || expanded_strategy_added) &amp;&amp; i &gt; 0) {</div><div class='add'>+				/* reset per stream index, decrement i */</div><div class='add'>+				stream_iteration_indices[i] = 0;</div><div class='add'>+				i--;</div><div class='add'>+</div><div class='add'>+				/* restore previous stream's count and increment index */</div><div class='add'>+				num_streams_per_method[stream_iteration_indices[i]] += 1;</div><div class='add'>+				stream_iteration_indices[i]++;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool is_variant_method_valid(const struct dml2_pmo_pstate_strategy *base_strategy,</div><div class='add'>+		const struct dml2_pmo_pstate_strategy *variant_strategy,</div><div class='add'>+		const unsigned int num_streams_per_base_method[PMO_DCN4_MAX_DISPLAYS],</div><div class='add'>+		const unsigned int num_streams_per_variant_method[PMO_DCN4_MAX_DISPLAYS],</div><div class='add'>+		const unsigned int stream_count)</div><div class='add'>+{</div><div class='add'>+	bool valid = true;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* check all restrictions are met */</div><div class='add'>+	for (i = 0; i &lt; stream_count; i++) {</div><div class='add'>+		/* vblank + vblank_drr variants are invalid */</div><div class='add'>+		if (base_strategy-&gt;per_stream_pstate_method[i] == dml2_pstate_method_vblank &amp;&amp;</div><div class='add'>+				((num_streams_per_base_method[i] &gt; 0 &amp;&amp; num_streams_per_variant_method[i] &gt; 0) ||</div><div class='add'>+				num_streams_per_variant_method[i] &gt; 1)) {</div><div class='add'>+			valid = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return valid;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void expand_variant_strategy(</div><div class='add'>+		const struct dml2_pmo_pstate_strategy *base_strategy,</div><div class='add'>+		const unsigned int stream_count,</div><div class='add'>+		const bool should_permute,</div><div class='add'>+		struct dml2_pmo_pstate_strategy *expanded_strategy_list,</div><div class='add'>+		unsigned int *num_expanded_strategies)</div><div class='add'>+{</div><div class='add'>+	bool variant_found;</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+	unsigned int method_index;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+	unsigned int num_streams_per_method[PMO_DCN4_MAX_DISPLAYS] = { 0 };</div><div class='add'>+	unsigned int num_streams_per_base_method[PMO_DCN4_MAX_DISPLAYS] = { 0 };</div><div class='add'>+	unsigned int num_streams_per_variant_method[PMO_DCN4_MAX_DISPLAYS] = { 0 };</div><div class='add'>+	enum dml2_pstate_method per_stream_variant_method[DML2_MAX_PLANES];</div><div class='add'>+	struct dml2_pmo_pstate_strategy variant_strategy = { 0 };</div><div class='add'>+</div><div class='add'>+	/* determine number of displays per method */</div><div class='add'>+	for (i = 0; i &lt; stream_count; i++) {</div><div class='add'>+		/* increment the count of the earliest index with the same method */</div><div class='add'>+		for (j = 0; j &lt; stream_count; j++) {</div><div class='add'>+			if (base_strategy-&gt;per_stream_pstate_method[i] == base_strategy-&gt;per_stream_pstate_method[j]) {</div><div class='add'>+				num_streams_per_method[j] = num_streams_per_method[j] + 1;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		per_stream_variant_method[i] = convert_strategy_to_drr_variant(base_strategy-&gt;per_stream_pstate_method[i]);</div><div class='add'>+	}</div><div class='add'>+	memcpy(num_streams_per_base_method, num_streams_per_method, sizeof(unsigned int) * PMO_DCN4_MAX_DISPLAYS);</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;variant_strategy, base_strategy, sizeof(struct dml2_pmo_pstate_strategy));</div><div class='add'>+</div><div class='add'>+	method_index = 0;</div><div class='add'>+	/* uses a while loop instead of recursion to build permutations of base strategy */</div><div class='add'>+	while (num_streams_per_base_method[0] &gt; 0 || method_index != 0) {</div><div class='add'>+		if (method_index == stream_count) {</div><div class='add'>+			/* construct variant strategy */</div><div class='add'>+			variant_found = false;</div><div class='add'>+			stream_index = 0;</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; stream_count; i++) {</div><div class='add'>+				for (j = 0; j &lt; num_streams_per_base_method[i]; j++) {</div><div class='add'>+					variant_strategy.per_stream_pstate_method[stream_index++] = base_strategy-&gt;per_stream_pstate_method[i];</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				for (j = 0; j &lt; num_streams_per_variant_method[i]; j++) {</div><div class='add'>+					variant_strategy.per_stream_pstate_method[stream_index++] = per_stream_variant_method[i];</div><div class='add'>+					if (base_strategy-&gt;per_stream_pstate_method[i] != per_stream_variant_method[i]) {</div><div class='add'>+						variant_found = true;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (variant_found &amp;&amp; is_variant_method_valid(base_strategy, &amp;variant_strategy, num_streams_per_base_method, num_streams_per_variant_method, stream_count)) {</div><div class='add'>+				if (should_permute) {</div><div class='add'>+					/* permutations are permitted, proceed to expand */</div><div class='add'>+					expand_base_strategy(&amp;variant_strategy, stream_count, expanded_strategy_list, num_expanded_strategies);</div><div class='add'>+				} else {</div><div class='add'>+					/* no permutations allowed, so add to list now */</div><div class='add'>+					insert_strategy_into_expanded_list(&amp;variant_strategy, stream_count, expanded_strategy_list, num_expanded_strategies);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* rollback to earliest method with bases remaining */</div><div class='add'>+			for (method_index = stream_count - 1; method_index &gt; 0; method_index--) {</div><div class='add'>+				if (num_streams_per_base_method[method_index]) {</div><div class='add'>+					/* bases remaining */</div><div class='add'>+					break;</div><div class='add'>+				} else {</div><div class='add'>+					/* reset counters */</div><div class='add'>+					num_streams_per_base_method[method_index] = num_streams_per_method[method_index];</div><div class='add'>+					num_streams_per_variant_method[method_index] = 0;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (num_streams_per_base_method[method_index]) {</div><div class='add'>+			num_streams_per_base_method[method_index]--;</div><div class='add'>+			num_streams_per_variant_method[method_index]++;</div><div class='add'>+</div><div class='add'>+			method_index++;</div><div class='add'>+		} else if (method_index != 0) {</div><div class='add'>+			method_index++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void pmo_dcn4_fams2_expand_base_pstate_strategies(</div><div class='add'>+		const struct dml2_pmo_pstate_strategy *base_strategies_list,</div><div class='add'>+		const unsigned int num_base_strategies,</div><div class='add'>+		const unsigned int stream_count,</div><div class='add'>+		struct dml2_pmo_pstate_strategy *expanded_strategy_list,</div><div class='add'>+		unsigned int *num_expanded_strategies)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* expand every explicit base strategy (except all DRR) */</div><div class='add'>+	for (i = 0; i &lt; num_base_strategies; i++) {</div><div class='add'>+		expand_base_strategy(&amp;base_strategies_list[i], stream_count, expanded_strategy_list, num_expanded_strategies);</div><div class='add'>+		expand_variant_strategy(&amp;base_strategies_list[i], stream_count, true, expanded_strategy_list, num_expanded_strategies);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int base_list_size = 0;</div><div class='add'>+	const struct dml2_pmo_pstate_strategy *base_list = NULL;</div><div class='add'>+	unsigned int *expanded_list_size = NULL;</div><div class='add'>+	struct dml2_pmo_pstate_strategy *expanded_list = NULL;</div><div class='add'>+</div><div class='add'>+	pmo-&gt;soc_bb = in_out-&gt;soc_bb;</div><div class='add'>+	pmo-&gt;ip_caps = in_out-&gt;ip_caps;</div><div class='add'>+	pmo-&gt;mpc_combine_limit = 2;</div><div class='add'>+	pmo-&gt;odm_combine_limit = 4;</div><div class='add'>+	pmo-&gt;mcg_clock_table_size = in_out-&gt;mcg_clock_table_size;</div><div class='add'>+</div><div class='add'>+	pmo-&gt;fams_params.v2.subvp.refresh_rate_limit_max = 175;</div><div class='add'>+	pmo-&gt;fams_params.v2.subvp.refresh_rate_limit_min = 0;</div><div class='add'>+	pmo-&gt;fams_params.v2.drr.refresh_rate_limit_max = 1000;</div><div class='add'>+	pmo-&gt;fams_params.v2.drr.refresh_rate_limit_min = 119;</div><div class='add'>+</div><div class='add'>+	pmo-&gt;options = in_out-&gt;options;</div><div class='add'>+</div><div class='add'>+	/* generate permutations of p-state configs from base strategy list */</div><div class='add'>+	for (i = 0; i &lt; PMO_DCN4_MAX_DISPLAYS; i++) {</div><div class='add'>+		switch (i+1) {</div><div class='add'>+		case 1:</div><div class='add'>+			if (pmo-&gt;options-&gt;override_strategy_lists[i] &amp;&amp; pmo-&gt;options-&gt;num_override_strategies_per_list[i]) {</div><div class='add'>+				base_list = pmo-&gt;options-&gt;override_strategy_lists[i];</div><div class='add'>+				base_list_size = pmo-&gt;options-&gt;num_override_strategies_per_list[i];</div><div class='add'>+			} else {</div><div class='add'>+				base_list = base_strategy_list_1_display;</div><div class='add'>+				base_list_size = base_strategy_list_1_display_size;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			expanded_list_size = &amp;pmo-&gt;init_data.pmo_dcn4.num_expanded_strategies_per_list[i];</div><div class='add'>+			expanded_list = pmo-&gt;init_data.pmo_dcn4.expanded_strategy_list_1_display;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			if (pmo-&gt;options-&gt;override_strategy_lists[i] &amp;&amp; pmo-&gt;options-&gt;num_override_strategies_per_list[i]) {</div><div class='add'>+				base_list = pmo-&gt;options-&gt;override_strategy_lists[i];</div><div class='add'>+				base_list_size = pmo-&gt;options-&gt;num_override_strategies_per_list[i];</div><div class='add'>+			} else {</div><div class='add'>+				base_list = base_strategy_list_2_display;</div><div class='add'>+				base_list_size = base_strategy_list_2_display_size;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			expanded_list_size = &amp;pmo-&gt;init_data.pmo_dcn4.num_expanded_strategies_per_list[i];</div><div class='add'>+			expanded_list = pmo-&gt;init_data.pmo_dcn4.expanded_strategy_list_2_display;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			if (pmo-&gt;options-&gt;override_strategy_lists[i] &amp;&amp; pmo-&gt;options-&gt;num_override_strategies_per_list[i]) {</div><div class='add'>+				base_list = pmo-&gt;options-&gt;override_strategy_lists[i];</div><div class='add'>+				base_list_size = pmo-&gt;options-&gt;num_override_strategies_per_list[i];</div><div class='add'>+			} else {</div><div class='add'>+				base_list = base_strategy_list_3_display;</div><div class='add'>+				base_list_size = base_strategy_list_3_display_size;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			expanded_list_size = &amp;pmo-&gt;init_data.pmo_dcn4.num_expanded_strategies_per_list[i];</div><div class='add'>+			expanded_list = pmo-&gt;init_data.pmo_dcn4.expanded_strategy_list_3_display;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		case 4:</div><div class='add'>+			if (pmo-&gt;options-&gt;override_strategy_lists[i] &amp;&amp; pmo-&gt;options-&gt;num_override_strategies_per_list[i]) {</div><div class='add'>+				base_list = pmo-&gt;options-&gt;override_strategy_lists[i];</div><div class='add'>+				base_list_size = pmo-&gt;options-&gt;num_override_strategies_per_list[i];</div><div class='add'>+			} else {</div><div class='add'>+				base_list = base_strategy_list_4_display;</div><div class='add'>+				base_list_size = base_strategy_list_4_display_size;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			expanded_list_size = &amp;pmo-&gt;init_data.pmo_dcn4.num_expanded_strategies_per_list[i];</div><div class='add'>+			expanded_list = pmo-&gt;init_data.pmo_dcn4.expanded_strategy_list_4_display;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		DML_ASSERT(base_list_size &lt;= PMO_DCN4_MAX_BASE_STRATEGIES);</div><div class='add'>+</div><div class='add'>+		/* populate list */</div><div class='add'>+		pmo_dcn4_fams2_expand_base_pstate_strategies(</div><div class='add'>+				base_list,</div><div class='add'>+				base_list_size,</div><div class='add'>+				i + 1,</div><div class='add'>+				expanded_list,</div><div class='add'>+				expanded_list_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_h_timing_divisible_by(const struct dml2_timing_cfg *timing, unsigned char denominator)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Htotal, Hblank start/end, and Hsync start/end all must be divisible</div><div class='add'>+	 * in order for the horizontal timing params to be considered divisible</div><div class='add'>+	 * by 2. Hsync start is always 0.</div><div class='add'>+	 */</div><div class='add'>+	unsigned long h_blank_start = timing-&gt;h_total - timing-&gt;h_front_porch;</div><div class='add'>+</div><div class='add'>+	return (timing-&gt;h_total % denominator == 0) &amp;&amp;</div><div class='add'>+			(h_blank_start % denominator == 0) &amp;&amp;</div><div class='add'>+			(timing-&gt;h_blank_end % denominator == 0) &amp;&amp;</div><div class='add'>+			(timing-&gt;h_sync_width % denominator == 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_dp_encoder(enum dml2_output_encoder_class encoder_type)</div><div class='add'>+{</div><div class='add'>+	switch (encoder_type) {</div><div class='add'>+	case dml2_dp:</div><div class='add'>+	case dml2_edp:</div><div class='add'>+	case dml2_dp2p0:</div><div class='add'>+	case dml2_none:</div><div class='add'>+		return true;</div><div class='add'>+	case dml2_hdmi:</div><div class='add'>+	case dml2_hdmifrl:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	const struct dml2_display_cfg *display_config =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;display_config;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;mode_support_result;</div><div class='add'>+	struct dml2_optimization_stage4_state *state =</div><div class='add'>+				&amp;in_out-&gt;base_display_config-&gt;stage4;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm ||</div><div class='add'>+			(in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm_for_multi_stream &amp;&amp; display_config-&gt;num_streams &gt; 1))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_planes; i++)</div><div class='add'>+		/*</div><div class='add'>+		 * vmin optimization is required to be seamlessly switched off</div><div class='add'>+		 * at any time when the new configuration is no longer</div><div class='add'>+		 * supported. However switching from ODM combine to MPC combine</div><div class='add'>+		 * is not always seamless. When there not enough free pipes, we</div><div class='add'>+		 * will have to use the same secondary OPP heads as secondary</div><div class='add'>+		 * DPP pipes in MPC combine in new state. This transition is</div><div class='add'>+		 * expected to cause glitches. To avoid the transition, we only</div><div class='add'>+		 * allow vmin optimization if the stream's base configuration</div><div class='add'>+		 * doesn't require MPC combine. This condition checks if MPC</div><div class='add'>+		 * combine is enabled. If so do not optimize the stream.</div><div class='add'>+		 */</div><div class='add'>+		if (mode_support_result-&gt;cfg_support_info.plane_support_info[i].dpps_used &gt; 1 &amp;&amp;</div><div class='add'>+				mode_support_result-&gt;cfg_support_info.stream_support_info[display_config-&gt;plane_descriptors[i].stream_index].odms_used == 1)</div><div class='add'>+			state-&gt;unoptimizable_streams[display_config-&gt;plane_descriptors[i].stream_index] = true;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_streams; i++) {</div><div class='add'>+		if (display_config-&gt;stream_descriptors[i].overrides.disable_dynamic_odm)</div><div class='add'>+			state-&gt;unoptimizable_streams[i] = true;</div><div class='add'>+		else if (in_out-&gt;base_display_config-&gt;stage3.stream_svp_meta[i].valid &amp;&amp;</div><div class='add'>+				in_out-&gt;instance-&gt;options-&gt;disable_dyn_odm_for_stream_with_svp)</div><div class='add'>+			state-&gt;unoptimizable_streams[i] = true;</div><div class='add'>+		/*</div><div class='add'>+		 * ODM Combine requires horizontal timing divisible by 2 so each</div><div class='add'>+		 * ODM segment has the same size.</div><div class='add'>+		 */</div><div class='add'>+		else if (!is_h_timing_divisible_by(&amp;display_config-&gt;stream_descriptors[i].timing, 2))</div><div class='add'>+			state-&gt;unoptimizable_streams[i] = true;</div><div class='add'>+		/*</div><div class='add'>+		 * Our hardware support seamless ODM transitions for DP encoders</div><div class='add'>+		 * only.</div><div class='add'>+		 */</div><div class='add'>+		else if (!is_dp_encoder(display_config-&gt;stream_descriptors[i].output.output_encoder))</div><div class='add'>+			state-&gt;unoptimizable_streams[i] = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	state-&gt;performed = true;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool is_vmin = true;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;vmin_limits-&gt;dispclk_khz &gt; 0 &amp;&amp;</div><div class='add'>+		in_out-&gt;display_config-&gt;mode_support_result.global.dispclk_khz &gt; in_out-&gt;vmin_limits-&gt;dispclk_khz)</div><div class='add'>+		is_vmin = false;</div><div class='add'>+</div><div class='add'>+	return is_vmin;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int find_highest_odm_load_stream_index(</div><div class='add'>+		const struct dml2_display_cfg *display_config,</div><div class='add'>+		const struct dml2_core_mode_support_result *mode_support_result)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int odm_load, highest_odm_load = -1, highest_odm_load_index = -1;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;num_streams; i++) {</div><div class='add'>+		if (mode_support_result-&gt;cfg_support_info.stream_support_info[i].odms_used &gt; 0)</div><div class='add'>+			odm_load = display_config-&gt;stream_descriptors[i].timing.pixel_clock_khz</div><div class='add'>+				/ mode_support_result-&gt;cfg_support_info.stream_support_info[i].odms_used;</div><div class='add'>+		else</div><div class='add'>+			odm_load = 0;</div><div class='add'>+</div><div class='add'>+		if (odm_load &gt; highest_odm_load) {</div><div class='add'>+			highest_odm_load_index = i;</div><div class='add'>+			highest_odm_load = odm_load;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return highest_odm_load_index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	int stream_index;</div><div class='add'>+	const struct dml2_display_cfg *display_config =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;display_config;</div><div class='add'>+	const struct dml2_core_mode_support_result *mode_support_result =</div><div class='add'>+			&amp;in_out-&gt;base_display_config-&gt;mode_support_result;</div><div class='add'>+	unsigned int odms_used;</div><div class='add'>+	struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+	bool optimizable = false;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * highest odm load stream must be optimizable to continue as dispclk is</div><div class='add'>+	 * bounded by it.</div><div class='add'>+	 */</div><div class='add'>+	stream_index = find_highest_odm_load_stream_index(display_config,</div><div class='add'>+			mode_support_result);</div><div class='add'>+</div><div class='add'>+	if (stream_index &lt; 0 ||</div><div class='add'>+			in_out-&gt;base_display_config-&gt;stage4.unoptimizable_streams[stream_index])</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	odms_used = mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].odms_used;</div><div class='add'>+	if ((int)odms_used &gt;= in_out-&gt;instance-&gt;odm_combine_limit)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memcpy(in_out-&gt;optimized_display_config,</div><div class='add'>+			in_out-&gt;base_display_config,</div><div class='add'>+			sizeof(struct display_configuation_with_meta));</div><div class='add'>+</div><div class='add'>+	stream_descriptor = &amp;in_out-&gt;optimized_display_config-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+	while (!optimizable &amp;&amp; increase_odm_combine_factor(</div><div class='add'>+			&amp;stream_descriptor-&gt;overrides.odm_mode,</div><div class='add'>+			odms_used)) {</div><div class='add'>+		switch (stream_descriptor-&gt;overrides.odm_mode) {</div><div class='add'>+		case dml2_odm_mode_combine_2to1:</div><div class='add'>+			optimizable = true;</div><div class='add'>+			break;</div><div class='add'>+		case dml2_odm_mode_combine_3to1:</div><div class='add'>+			/*</div><div class='add'>+			 * In ODM Combine 3:1 OTG_valid_pixel rate is 1/4 of</div><div class='add'>+			 * actual pixel rate. Therefore horizontal timing must</div><div class='add'>+			 * be divisible by 4.</div><div class='add'>+			 */</div><div class='add'>+			if (is_h_timing_divisible_by(&amp;display_config-&gt;stream_descriptors[stream_index].timing, 4)) {</div><div class='add'>+				if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].dsc_enable) {</div><div class='add'>+					/*</div><div class='add'>+					 * DSC h slice count must be divisible</div><div class='add'>+					 * by 3.</div><div class='add'>+					 */</div><div class='add'>+					if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].num_dsc_slices % 3 == 0)</div><div class='add'>+						optimizable = true;</div><div class='add'>+				} else {</div><div class='add'>+					optimizable = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case dml2_odm_mode_combine_4to1:</div><div class='add'>+			/*</div><div class='add'>+			 * In ODM Combine 4:1 OTG_valid_pixel rate is 1/4 of</div><div class='add'>+			 * actual pixel rate. Therefore horizontal timing must</div><div class='add'>+			 * be divisible by 4.</div><div class='add'>+			 */</div><div class='add'>+			if (is_h_timing_divisible_by(&amp;display_config-&gt;stream_descriptors[stream_index].timing, 4)) {</div><div class='add'>+				if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].dsc_enable) {</div><div class='add'>+					/*</div><div class='add'>+					 * DSC h slice count must be divisible</div><div class='add'>+					 * by 4.</div><div class='add'>+					 */</div><div class='add'>+					if (mode_support_result-&gt;cfg_support_info.stream_support_info[stream_index].num_dsc_slices % 4 == 0)</div><div class='add'>+						optimizable = true;</div><div class='add'>+				} else {</div><div class='add'>+					optimizable = true;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case dml2_odm_mode_auto:</div><div class='add'>+		case dml2_odm_mode_bypass:</div><div class='add'>+		case dml2_odm_mode_split_1to2:</div><div class='add'>+		case dml2_odm_mode_mso_1to2:</div><div class='add'>+		case dml2_odm_mode_mso_1to4:</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return optimizable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_bit_in_bitfield(unsigned int *bit_field, unsigned int bit_offset)</div><div class='add'>+{</div><div class='add'>+	*bit_field = *bit_field | (0x1 &lt;&lt; bit_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_bit_set_in_bitfield(unsigned int bit_field, unsigned int bit_offset)</div><div class='add'>+{</div><div class='add'>+	if (bit_field &amp; (0x1 &lt;&lt; bit_offset))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void build_synchronized_timing_groups(</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	struct display_configuation_with_meta *display_config)</div><div class='add'>+{</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+	struct dml2_timing_cfg *master_timing;</div><div class='add'>+</div><div class='add'>+	unsigned int stream_mapped_mask = 0;</div><div class='add'>+	unsigned int num_timing_groups = 0;</div><div class='add'>+	unsigned int timing_group_idx = 0;</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	/* clear all group masks */</div><div class='add'>+	memset(s-&gt;pmo_dcn4.synchronized_timing_group_masks, 0, sizeof(s-&gt;pmo_dcn4.synchronized_timing_group_masks));</div><div class='add'>+	memset(s-&gt;pmo_dcn4.group_is_drr_enabled, 0, sizeof(s-&gt;pmo_dcn4.group_is_drr_enabled));</div><div class='add'>+	memset(s-&gt;pmo_dcn4.group_is_drr_active, 0, sizeof(s-&gt;pmo_dcn4.group_is_drr_active));</div><div class='add'>+	memset(s-&gt;pmo_dcn4.group_line_time_us, 0, sizeof(s-&gt;pmo_dcn4.group_line_time_us));</div><div class='add'>+	s-&gt;pmo_dcn4.num_timing_groups = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;display_config.num_streams; i++) {</div><div class='add'>+		master_timing = &amp;display_config-&gt;display_config.stream_descriptors[i].timing;</div><div class='add'>+</div><div class='add'>+		/* only need to build group of this stream is not in a group already */</div><div class='add'>+		if (is_bit_set_in_bitfield(stream_mapped_mask, i)) {</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+		set_bit_in_bitfield(&amp;stream_mapped_mask, i);</div><div class='add'>+		timing_group_idx = num_timing_groups;</div><div class='add'>+		num_timing_groups++;</div><div class='add'>+</div><div class='add'>+		/* trivially set default timing group to itself */</div><div class='add'>+		set_bit_in_bitfield(&amp;s-&gt;pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], i);</div><div class='add'>+		s-&gt;pmo_dcn4.group_line_time_us[timing_group_idx] = (double)master_timing-&gt;h_total / master_timing-&gt;pixel_clock_khz * 1000.0;</div><div class='add'>+</div><div class='add'>+		/* if drr is in use, timing is not sychnronizable */</div><div class='add'>+		if (master_timing-&gt;drr_config.enabled) {</div><div class='add'>+			s-&gt;pmo_dcn4.group_is_drr_enabled[timing_group_idx] = true;</div><div class='add'>+			s-&gt;pmo_dcn4.group_is_drr_active[timing_group_idx] = !master_timing-&gt;drr_config.disallowed &amp;&amp;</div><div class='add'>+					(master_timing-&gt;drr_config.drr_active_fixed || master_timing-&gt;drr_config.drr_active_variable);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* find synchronizable timing groups */</div><div class='add'>+		for (j = i + 1; j &lt; display_config-&gt;display_config.num_streams; j++) {</div><div class='add'>+			if (memcmp(master_timing,</div><div class='add'>+				&amp;display_config-&gt;display_config.stream_descriptors[j].timing,</div><div class='add'>+				sizeof(struct dml2_timing_cfg)) == 0) {</div><div class='add'>+				set_bit_in_bitfield(&amp;pmo-&gt;scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);</div><div class='add'>+				set_bit_in_bitfield(&amp;stream_mapped_mask, j);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	s-&gt;pmo_dcn4.num_timing_groups = num_timing_groups;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool all_timings_support_vactive(const struct dml2_pmo_instance *pmo,</div><div class='add'>+		const struct display_configuation_with_meta *display_config,</div><div class='add'>+		unsigned int mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool valid = true;</div><div class='add'>+</div><div class='add'>+	// Create a remap array to enable simple iteration through only masked stream indicies</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;display_config.num_streams; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(mask, i)) {</div><div class='add'>+			/* check if stream has enough vactive margin */</div><div class='add'>+			valid &amp;= is_bit_set_in_bitfield(pmo-&gt;scratch.pmo_dcn4.stream_vactive_capability_mask, i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return valid;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool all_timings_support_vblank(const struct dml2_pmo_instance *pmo,</div><div class='add'>+		const struct display_configuation_with_meta *display_config,</div><div class='add'>+		unsigned int mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	bool synchronizable = true;</div><div class='add'>+</div><div class='add'>+	/* find first vblank stream index and compare the timing group mask */</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;display_config.num_streams; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(mask, i)) {</div><div class='add'>+			if (mask != pmo-&gt;scratch.pmo_dcn4.synchronized_timing_group_masks[i]) {</div><div class='add'>+				/* vblank streams are not synchronizable */</div><div class='add'>+				synchronizable = false;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return synchronizable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int calc_svp_microschedule(const struct dml2_pstate_meta *pstate_meta)</div><div class='add'>+{</div><div class='add'>+	return pstate_meta-&gt;contention_delay_otg_vlines +</div><div class='add'>+		pstate_meta-&gt;method_subvp.programming_delay_otg_vlines +</div><div class='add'>+		pstate_meta-&gt;method_subvp.phantom_vtotal +</div><div class='add'>+		pstate_meta-&gt;method_subvp.prefetch_to_mall_delay_otg_vlines +</div><div class='add'>+		pstate_meta-&gt;blackout_otg_vlines;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo,</div><div class='add'>+	const struct display_configuation_with_meta *display_config,</div><div class='add'>+	unsigned int mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_PLANES; i++) {</div><div class='add'>+		const struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+		const struct dml2_pstate_meta *stream_pstate_meta;</div><div class='add'>+</div><div class='add'>+		if (is_bit_set_in_bitfield(mask, i)) {</div><div class='add'>+			stream_descriptor = &amp;display_config-&gt;display_config.stream_descriptors[i];</div><div class='add'>+			stream_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[i];</div><div class='add'>+</div><div class='add'>+			if (!stream_descriptor-&gt;timing.drr_config.enabled)</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='add'>+			/* cannot support required vtotal */</div><div class='add'>+			if (stream_pstate_meta-&gt;method_drr.stretched_vtotal &gt; stream_pstate_meta-&gt;max_vtotal) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* check rr is within bounds */</div><div class='add'>+			if (stream_pstate_meta-&gt;nom_refresh_rate_hz &lt; pmo-&gt;fams_params.v2.drr.refresh_rate_limit_min ||</div><div class='add'>+				stream_pstate_meta-&gt;nom_refresh_rate_hz &gt; pmo-&gt;fams_params.v2.drr.refresh_rate_limit_max) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* check required stretch is allowed */</div><div class='add'>+			if (stream_descriptor-&gt;timing.drr_config.max_instant_vtotal_delta &gt; 0 &amp;&amp;</div><div class='add'>+					stream_pstate_meta-&gt;method_drr.stretched_vtotal - stream_pstate_meta-&gt;nom_vtotal &gt; (int)stream_descriptor-&gt;timing.drr_config.max_instant_vtotal_delta) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo,</div><div class='add'>+	const struct display_configuation_with_meta *display_config,</div><div class='add'>+	unsigned int mask)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor;</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+	const struct dml2_pstate_meta *stream_pstate_meta;</div><div class='add'>+	unsigned int microschedule_vlines;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned int mcaches_per_plane;</div><div class='add'>+	unsigned int total_mcaches_required = 0;</div><div class='add'>+</div><div class='add'>+	unsigned int num_planes_per_stream[DML2_MAX_PLANES] = { 0 };</div><div class='add'>+</div><div class='add'>+	/* confirm timing it is not a centered timing */</div><div class='add'>+	for (i = 0; i &lt; display_config-&gt;display_config.num_planes; i++) {</div><div class='add'>+		plane_descriptor = &amp;display_config-&gt;display_config.plane_descriptors[i];</div><div class='add'>+		mcaches_per_plane = 0;</div><div class='add'>+</div><div class='add'>+		if (plane_descriptor-&gt;surface.dcc.enable) {</div><div class='add'>+			mcaches_per_plane += display_config-&gt;stage2.mcache_allocations[i].num_mcaches_plane0 +</div><div class='add'>+				display_config-&gt;stage2.mcache_allocations[i].num_mcaches_plane1 -</div><div class='add'>+				(display_config-&gt;stage2.mcache_allocations[i].last_slice_sharing.plane0_plane1 ? 1 : 0);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (is_bit_set_in_bitfield(mask, (unsigned char)plane_descriptor-&gt;stream_index)) {</div><div class='add'>+			num_planes_per_stream[plane_descriptor-&gt;stream_index]++;</div><div class='add'>+</div><div class='add'>+			/* check recout height covers entire otg vactive, and single plane */</div><div class='add'>+			if (num_planes_per_stream[plane_descriptor-&gt;stream_index] &gt; 1 ||</div><div class='add'>+					!plane_descriptor-&gt;composition.rect_out_height_spans_vactive ||</div><div class='add'>+					plane_descriptor-&gt;composition.rotation_angle != dml2_rotation_0) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* phantom requires same number of mcaches as main */</div><div class='add'>+			if (plane_descriptor-&gt;surface.dcc.enable) {</div><div class='add'>+				mcaches_per_plane *= 2;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		total_mcaches_required += mcaches_per_plane;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (total_mcaches_required &gt; pmo-&gt;soc_bb-&gt;num_dcc_mcaches) {</div><div class='add'>+		/* too many mcaches required */</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_PLANES; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(mask, i)) {</div><div class='add'>+			stream_descriptor = &amp;display_config-&gt;display_config.stream_descriptors[i];</div><div class='add'>+			stream_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[i];</div><div class='add'>+</div><div class='add'>+			if (stream_descriptor-&gt;overrides.disable_subvp) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			microschedule_vlines = calc_svp_microschedule(&amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[i]);</div><div class='add'>+</div><div class='add'>+			/* block if using an interlaced timing */</div><div class='add'>+			if (stream_descriptor-&gt;timing.interlaced) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* 1) svp main stream's vactive must be able to fit the microschedule</div><div class='add'>+			*  2) refresh rate must be within the allowed bounds</div><div class='add'>+			*/</div><div class='add'>+			if (microschedule_vlines &gt;= stream_descriptor-&gt;timing.v_active ||</div><div class='add'>+					(stream_pstate_meta-&gt;nom_refresh_rate_hz &lt; pmo-&gt;fams_params.v2.subvp.refresh_rate_limit_min ||</div><div class='add'>+					stream_pstate_meta-&gt;nom_refresh_rate_hz &gt; pmo-&gt;fams_params.v2.subvp.refresh_rate_limit_max)) {</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void insert_into_candidate_list(const struct dml2_pmo_pstate_strategy *pstate_strategy, int stream_count, struct dml2_pmo_scratch *scratch)</div><div class='add'>+{</div><div class='add'>+	scratch-&gt;pmo_dcn4.pstate_strategy_candidates[scratch-&gt;pmo_dcn4.num_pstate_candidates] = *pstate_strategy;</div><div class='add'>+	scratch-&gt;pmo_dcn4.num_pstate_candidates++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_pstate_method uclk_pstate_strategy_override_to_pstate_method(const enum dml2_uclk_pstate_change_strategy override_strategy)</div><div class='add'>+{</div><div class='add'>+	enum dml2_pstate_method method = dml2_pstate_method_na;</div><div class='add'>+</div><div class='add'>+	switch (override_strategy) {</div><div class='add'>+	case dml2_uclk_pstate_change_strategy_force_vactive:</div><div class='add'>+		method = dml2_pstate_method_vactive;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_uclk_pstate_change_strategy_force_vblank:</div><div class='add'>+		method = dml2_pstate_method_vblank;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_uclk_pstate_change_strategy_force_drr:</div><div class='add'>+		method = dml2_pstate_method_fw_drr;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_uclk_pstate_change_strategy_force_mall_svp:</div><div class='add'>+		method = dml2_pstate_method_fw_svp;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_uclk_pstate_change_strategy_force_mall_full_frame:</div><div class='add'>+	case dml2_uclk_pstate_change_strategy_auto:</div><div class='add'>+	default:</div><div class='add'>+		method = dml2_pstate_method_na;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return method;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dml2_uclk_pstate_change_strategy pstate_method_to_uclk_pstate_strategy_override(const enum dml2_pstate_method method)</div><div class='add'>+{</div><div class='add'>+	enum dml2_uclk_pstate_change_strategy override_strategy = dml2_uclk_pstate_change_strategy_auto;</div><div class='add'>+</div><div class='add'>+	switch (method) {</div><div class='add'>+	case dml2_pstate_method_vactive:</div><div class='add'>+	case dml2_pstate_method_fw_vactive_drr:</div><div class='add'>+		override_strategy = dml2_uclk_pstate_change_strategy_force_vactive;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_vblank:</div><div class='add'>+	case dml2_pstate_method_fw_vblank_drr:</div><div class='add'>+		override_strategy = dml2_uclk_pstate_change_strategy_force_vblank;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_svp:</div><div class='add'>+	case dml2_pstate_method_fw_svp_drr:</div><div class='add'>+		override_strategy = dml2_uclk_pstate_change_strategy_force_mall_svp;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_drr:</div><div class='add'>+		override_strategy = dml2_uclk_pstate_change_strategy_force_drr;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_reserved_hw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_clamped:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_var:</div><div class='add'>+	case dml2_pstate_method_count:</div><div class='add'>+	case dml2_pstate_method_na:</div><div class='add'>+	default:</div><div class='add'>+		override_strategy = dml2_uclk_pstate_change_strategy_auto;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return override_strategy;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool all_planes_match_method(const struct display_configuation_with_meta *display_cfg, int plane_mask, enum dml2_pstate_method method)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_PLANES; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, i)) {</div><div class='add'>+			if (display_cfg-&gt;display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != dml2_uclk_pstate_change_strategy_auto &amp;&amp;</div><div class='add'>+				display_cfg-&gt;display_config.plane_descriptors[i].overrides.uclk_pstate_change_strategy != pstate_method_to_uclk_pstate_strategy_override(method))</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void build_method_scheduling_params(</div><div class='add'>+	struct dml2_pstate_per_method_common_meta *stream_method_pstate_meta,</div><div class='add'>+	struct dml2_pstate_meta *stream_pstate_meta)</div><div class='add'>+{</div><div class='add'>+	stream_method_pstate_meta-&gt;allow_time_us =</div><div class='add'>+			(double)((int)stream_method_pstate_meta-&gt;allow_end_otg_vline - (int)stream_method_pstate_meta-&gt;allow_start_otg_vline) *</div><div class='add'>+			stream_pstate_meta-&gt;otg_vline_time_us;</div><div class='add'>+	if (stream_method_pstate_meta-&gt;allow_time_us &gt;= stream_method_pstate_meta-&gt;period_us) {</div><div class='add'>+		/* when allow wave overlaps an entire frame, it is always schedulable (DRR can do this)*/</div><div class='add'>+		stream_method_pstate_meta-&gt;disallow_time_us = 0.0;</div><div class='add'>+	} else {</div><div class='add'>+		stream_method_pstate_meta-&gt;disallow_time_us =</div><div class='add'>+				stream_method_pstate_meta-&gt;period_us - stream_method_pstate_meta-&gt;allow_time_us;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dml2_pstate_per_method_common_meta *get_per_method_common_meta(</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	enum dml2_pstate_method stream_pstate_method,</div><div class='add'>+	int stream_idx)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pstate_per_method_common_meta *stream_method_pstate_meta = NULL;</div><div class='add'>+</div><div class='add'>+	switch (stream_pstate_method) {</div><div class='add'>+	case dml2_pstate_method_vactive:</div><div class='add'>+	case dml2_pstate_method_fw_vactive_drr:</div><div class='add'>+		stream_method_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_vactive.common;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_vblank:</div><div class='add'>+	case dml2_pstate_method_fw_vblank_drr:</div><div class='add'>+		stream_method_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_vblank.common;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_svp:</div><div class='add'>+	case dml2_pstate_method_fw_svp_drr:</div><div class='add'>+		stream_method_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_subvp.common;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_fw_drr:</div><div class='add'>+		stream_method_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_drr.common;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_pstate_method_reserved_hw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_clamped:</div><div class='add'>+	case dml2_pstate_method_reserved_fw_drr_var:</div><div class='add'>+	case dml2_pstate_method_count:</div><div class='add'>+	case dml2_pstate_method_na:</div><div class='add'>+	default:</div><div class='add'>+		stream_method_pstate_meta = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return stream_method_pstate_meta;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_timing_group_schedulable(</div><div class='add'>+		struct dml2_pmo_instance *pmo,</div><div class='add'>+		const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+		const struct dml2_pmo_pstate_strategy *pstate_strategy,</div><div class='add'>+		const unsigned int timing_group_idx,</div><div class='add'>+		struct dml2_pstate_per_method_common_meta *group_pstate_meta)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	struct dml2_pstate_per_method_common_meta *stream_method_pstate_meta;</div><div class='add'>+</div><div class='add'>+	unsigned int base_stream_idx = 0;</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	/* find base stream idx */</div><div class='add'>+	for (base_stream_idx = 0; base_stream_idx &lt; display_cfg-&gt;display_config.num_streams; base_stream_idx++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(s-&gt;pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], base_stream_idx)) {</div><div class='add'>+			/* master stream found */</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* init allow start and end lines for timing group */</div><div class='add'>+	stream_method_pstate_meta = get_per_method_common_meta(pmo, pstate_strategy-&gt;per_stream_pstate_method[base_stream_idx], base_stream_idx);</div><div class='add'>+	if (!stream_method_pstate_meta)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	group_pstate_meta-&gt;allow_start_otg_vline = stream_method_pstate_meta-&gt;allow_start_otg_vline;</div><div class='add'>+	group_pstate_meta-&gt;allow_end_otg_vline = stream_method_pstate_meta-&gt;allow_end_otg_vline;</div><div class='add'>+	group_pstate_meta-&gt;period_us = stream_method_pstate_meta-&gt;period_us;</div><div class='add'>+	for (i = base_stream_idx + 1; i &lt; display_cfg-&gt;display_config.num_streams; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(pmo-&gt;scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], i)) {</div><div class='add'>+			stream_method_pstate_meta = get_per_method_common_meta(pmo, pstate_strategy-&gt;per_stream_pstate_method[i], i);</div><div class='add'>+			if (!stream_method_pstate_meta)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			if (group_pstate_meta-&gt;allow_start_otg_vline &lt; stream_method_pstate_meta-&gt;allow_start_otg_vline) {</div><div class='add'>+				/* set group allow start to larger otg vline */</div><div class='add'>+				group_pstate_meta-&gt;allow_start_otg_vline = stream_method_pstate_meta-&gt;allow_start_otg_vline;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (group_pstate_meta-&gt;allow_end_otg_vline &gt; stream_method_pstate_meta-&gt;allow_end_otg_vline) {</div><div class='add'>+				/* set group allow end to smaller otg vline */</div><div class='add'>+				group_pstate_meta-&gt;allow_end_otg_vline = stream_method_pstate_meta-&gt;allow_end_otg_vline;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* check waveform still has positive width */</div><div class='add'>+			if (group_pstate_meta-&gt;allow_start_otg_vline &gt;= group_pstate_meta-&gt;allow_end_otg_vline) {</div><div class='add'>+				/* timing group is not schedulable */</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* calculate the rest of the meta */</div><div class='add'>+	build_method_scheduling_params(group_pstate_meta, &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[base_stream_idx]);</div><div class='add'>+</div><div class='add'>+	return group_pstate_meta-&gt;allow_time_us &gt; 0.0 &amp;&amp;</div><div class='add'>+			group_pstate_meta-&gt;disallow_time_us &lt; pmo-&gt;ip_caps-&gt;fams2.max_allow_delay_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_config_schedulable(</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+	const struct dml2_pmo_pstate_strategy *pstate_strategy)</div><div class='add'>+{</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+	bool schedulable;</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	double max_allow_delay_us = 0.0;</div><div class='add'>+</div><div class='add'>+	memset(s-&gt;pmo_dcn4.group_common_pstate_meta, 0, sizeof(s-&gt;pmo_dcn4.group_common_pstate_meta));</div><div class='add'>+	memset(s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES);</div><div class='add'>+</div><div class='add'>+	/* search for a general solution to the schedule */</div><div class='add'>+</div><div class='add'>+	/* STAGE 0: Early return for special cases */</div><div class='add'>+	if (display_cfg-&gt;display_config.num_streams == 0) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* STAGE 1: confirm allow waves overlap for synchronizable streams */</div><div class='add'>+	schedulable = true;</div><div class='add'>+	for (i = 0; i &lt; s-&gt;pmo_dcn4.num_timing_groups; i++) {</div><div class='add'>+		s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index[i] = i;</div><div class='add'>+		s-&gt;pmo_dcn4.sorted_group_gtl_period_index[i] = i;</div><div class='add'>+		if (!is_timing_group_schedulable(pmo, display_cfg, pstate_strategy, i, &amp;s-&gt;pmo_dcn4.group_common_pstate_meta[i])) {</div><div class='add'>+			/* synchronized timing group was not schedulable */</div><div class='add'>+			schedulable = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		max_allow_delay_us += s-&gt;pmo_dcn4.group_common_pstate_meta[i].disallow_time_us;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((schedulable &amp;&amp; s-&gt;pmo_dcn4.num_timing_groups &lt;= 1) || !schedulable) {</div><div class='add'>+		/* 1. the only timing group was schedulable, so early pass</div><div class='add'>+		 * 2. one of the timing groups was not schedulable, so early fail */</div><div class='add'>+		return schedulable;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* STAGE 2: Check allow can't be masked entirely by other disallows */</div><div class='add'>+	schedulable = true;</div><div class='add'>+</div><div class='add'>+	/* sort disallow times from greatest to least */</div><div class='add'>+	for (i = 0; i &lt; s-&gt;pmo_dcn4.num_timing_groups; i++) {</div><div class='add'>+		bool swapped = false;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; s-&gt;pmo_dcn4.num_timing_groups - 1; j++) {</div><div class='add'>+			double j_disallow_us = s-&gt;pmo_dcn4.group_common_pstate_meta[s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index[j]].disallow_time_us;</div><div class='add'>+			double jp1_disallow_us = s-&gt;pmo_dcn4.group_common_pstate_meta[s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index[j + 1]].disallow_time_us;</div><div class='add'>+			if (j_disallow_us &lt; jp1_disallow_us) {</div><div class='add'>+				/* swap as A &lt; B */</div><div class='add'>+				swap(s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index[j],</div><div class='add'>+					 s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index[j + 1]);</div><div class='add'>+				swapped = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* sorted, exit early */</div><div class='add'>+		if (!swapped)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check worst case disallow region occurs in the middle of allow for the</div><div class='add'>+	* other display, or when &gt;2 streams continue to halve the remaining allow time.</div><div class='add'>+	*/</div><div class='add'>+	for (i = 0; i &lt; s-&gt;pmo_dcn4.num_timing_groups; i++) {</div><div class='add'>+		if (s-&gt;pmo_dcn4.group_common_pstate_meta[i].disallow_time_us &lt;= 0.0) {</div><div class='add'>+			/* this timing group always allows */</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		double max_allow_time_us = s-&gt;pmo_dcn4.group_common_pstate_meta[i].allow_time_us;</div><div class='add'>+		for (j = 0; j &lt; s-&gt;pmo_dcn4.num_timing_groups; j++) {</div><div class='add'>+			unsigned int sorted_j = s-&gt;pmo_dcn4.sorted_group_gtl_disallow_index[j];</div><div class='add'>+			/* stream can't overlap itself */</div><div class='add'>+			if (i != sorted_j &amp;&amp; s-&gt;pmo_dcn4.group_common_pstate_meta[sorted_j].disallow_time_us &gt; 0.0) {</div><div class='add'>+				max_allow_time_us = math_min2(</div><div class='add'>+						s-&gt;pmo_dcn4.group_common_pstate_meta[sorted_j].allow_time_us,</div><div class='add'>+						(max_allow_time_us - s-&gt;pmo_dcn4.group_common_pstate_meta[sorted_j].disallow_time_us) / 2);</div><div class='add'>+</div><div class='add'>+				if (max_allow_time_us &lt; 0.0) {</div><div class='add'>+					/* failed exit early */</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (max_allow_time_us &lt;= 0.0) {</div><div class='add'>+			/* not enough time for microschedule in the worst case */</div><div class='add'>+			schedulable = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (schedulable &amp;&amp; max_allow_delay_us &lt; pmo-&gt;ip_caps-&gt;fams2.max_allow_delay_us) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* STAGE 3: check larger allow can fit period of all other streams */</div><div class='add'>+	schedulable = true;</div><div class='add'>+</div><div class='add'>+	/* sort periods from greatest to least */</div><div class='add'>+	for (i = 0; i &lt; s-&gt;pmo_dcn4.num_timing_groups; i++) {</div><div class='add'>+		bool swapped = false;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; s-&gt;pmo_dcn4.num_timing_groups - 1; j++) {</div><div class='add'>+			double j_period_us = s-&gt;pmo_dcn4.group_common_pstate_meta[s-&gt;pmo_dcn4.sorted_group_gtl_period_index[j]].period_us;</div><div class='add'>+			double jp1_period_us = s-&gt;pmo_dcn4.group_common_pstate_meta[s-&gt;pmo_dcn4.sorted_group_gtl_period_index[j + 1]].period_us;</div><div class='add'>+			if (j_period_us &lt; jp1_period_us) {</div><div class='add'>+				/* swap as A &lt; B */</div><div class='add'>+				swap(s-&gt;pmo_dcn4.sorted_group_gtl_period_index[j],</div><div class='add'>+					 s-&gt;pmo_dcn4.sorted_group_gtl_period_index[j + 1]);</div><div class='add'>+				swapped = true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* sorted, exit early */</div><div class='add'>+		if (!swapped)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* check larger allow can fit period of all other streams */</div><div class='add'>+	for (i = 0; i &lt; s-&gt;pmo_dcn4.num_timing_groups - 1; i++) {</div><div class='add'>+		unsigned int sorted_i = s-&gt;pmo_dcn4.sorted_group_gtl_period_index[i];</div><div class='add'>+		unsigned int sorted_ip1 = s-&gt;pmo_dcn4.sorted_group_gtl_period_index[i + 1];</div><div class='add'>+</div><div class='add'>+		if (s-&gt;pmo_dcn4.group_common_pstate_meta[sorted_i].allow_time_us &lt; s-&gt;pmo_dcn4.group_common_pstate_meta[sorted_ip1].period_us ||</div><div class='add'>+				(s-&gt;pmo_dcn4.group_is_drr_enabled[sorted_ip1] &amp;&amp; s-&gt;pmo_dcn4.group_is_drr_active[sorted_ip1])) {</div><div class='add'>+			schedulable = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (schedulable &amp;&amp; max_allow_delay_us &lt; pmo-&gt;ip_caps-&gt;fams2.max_allow_delay_us) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* STAGE 4: When using HW exclusive modes, check disallow alignments are within allowed threshold */</div><div class='add'>+	if (s-&gt;pmo_dcn4.num_timing_groups == 2 &amp;&amp;</div><div class='add'>+			!is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, pstate_strategy-&gt;per_stream_pstate_method[0]) &amp;&amp;</div><div class='add'>+			!is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, pstate_strategy-&gt;per_stream_pstate_method[1])) {</div><div class='add'>+		double period_ratio;</div><div class='add'>+		double max_shift_us;</div><div class='add'>+		double shift_per_period;</div><div class='add'>+</div><div class='add'>+		/* default period_0 &gt; period_1 */</div><div class='add'>+		unsigned int lrg_idx = 0;</div><div class='add'>+		unsigned int sml_idx = 1;</div><div class='add'>+		if (s-&gt;pmo_dcn4.group_common_pstate_meta[0].period_us &lt; s-&gt;pmo_dcn4.group_common_pstate_meta[1].period_us) {</div><div class='add'>+			/* period_0 &lt; period_1 */</div><div class='add'>+			lrg_idx = 1;</div><div class='add'>+			sml_idx = 0;</div><div class='add'>+		}</div><div class='add'>+		period_ratio = s-&gt;pmo_dcn4.group_common_pstate_meta[lrg_idx].period_us / s-&gt;pmo_dcn4.group_common_pstate_meta[sml_idx].period_us;</div><div class='add'>+		shift_per_period = s-&gt;pmo_dcn4.group_common_pstate_meta[sml_idx].period_us * (period_ratio - math_floor(period_ratio));</div><div class='add'>+		max_shift_us = s-&gt;pmo_dcn4.group_common_pstate_meta[lrg_idx].disallow_time_us - s-&gt;pmo_dcn4.group_common_pstate_meta[sml_idx].allow_time_us;</div><div class='add'>+		max_allow_delay_us = max_shift_us / shift_per_period * s-&gt;pmo_dcn4.group_common_pstate_meta[lrg_idx].period_us;</div><div class='add'>+</div><div class='add'>+		if (shift_per_period &gt; 0.0 &amp;&amp;</div><div class='add'>+			shift_per_period &lt; s-&gt;pmo_dcn4.group_common_pstate_meta[lrg_idx].allow_time_us + s-&gt;pmo_dcn4.group_common_pstate_meta[sml_idx].allow_time_us &amp;&amp;</div><div class='add'>+			max_allow_delay_us &lt; pmo-&gt;ip_caps-&gt;fams2.max_allow_delay_us) {</div><div class='add'>+			schedulable = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return schedulable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo,</div><div class='add'>+	const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+	const enum dml2_pstate_method stream_pstate_method,</div><div class='add'>+	unsigned int stream_index)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor = &amp;display_cfg-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+	bool strategy_matches_drr_requirements = true;</div><div class='add'>+</div><div class='add'>+	/* check if strategy is compatible with stream drr capability and strategy */</div><div class='add'>+	if (is_bit_set_in_bitfield(PMO_NO_DRR_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+			display_cfg-&gt;display_config.num_streams &gt; 1 &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.enabled &amp;&amp;</div><div class='add'>+			(stream_descriptor-&gt;timing.drr_config.drr_active_fixed || stream_descriptor-&gt;timing.drr_config.drr_active_variable)) {</div><div class='add'>+		/* DRR is active, so config may become unschedulable */</div><div class='add'>+		strategy_matches_drr_requirements = false;</div><div class='add'>+	} else if (is_bit_set_in_bitfield(PMO_NO_DRR_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+			is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.enabled &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.drr_active_variable) {</div><div class='add'>+		/* DRR is variable, fw exclusive methods require DRR to be clamped */</div><div class='add'>+		strategy_matches_drr_requirements = false;</div><div class='add'>+	} else if (is_bit_set_in_bitfield(PMO_DRR_VAR_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+			pmo-&gt;options-&gt;disable_drr_var_when_var_active &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.enabled &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.drr_active_variable) {</div><div class='add'>+		/* DRR variable is active, but policy blocks DRR for p-state when this happens */</div><div class='add'>+		strategy_matches_drr_requirements = false;</div><div class='add'>+	} else if (is_bit_set_in_bitfield(PMO_DRR_VAR_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+			(pmo-&gt;options-&gt;disable_drr_var ||</div><div class='add'>+			!stream_descriptor-&gt;timing.drr_config.enabled ||</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.disallowed)) {</div><div class='add'>+		/* DRR variable strategies are disallowed due to settings or policy */</div><div class='add'>+		strategy_matches_drr_requirements = false;</div><div class='add'>+	} else if (is_bit_set_in_bitfield(PMO_DRR_CLAMPED_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+		(pmo-&gt;options-&gt;disable_drr_clamped ||</div><div class='add'>+			(!stream_descriptor-&gt;timing.drr_config.enabled ||</div><div class='add'>+			(!stream_descriptor-&gt;timing.drr_config.drr_active_fixed &amp;&amp; !stream_descriptor-&gt;timing.drr_config.drr_active_variable)) ||</div><div class='add'>+			(pmo-&gt;options-&gt;disable_drr_clamped_when_var_active &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.enabled &amp;&amp;</div><div class='add'>+			stream_descriptor-&gt;timing.drr_config.drr_active_variable))) {</div><div class='add'>+		/* DRR fixed strategies are disallowed due to settings or policy */</div><div class='add'>+		strategy_matches_drr_requirements = false;</div><div class='add'>+	} else if (is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, stream_pstate_method) &amp;&amp;</div><div class='add'>+			pmo-&gt;options-&gt;disable_fams2) {</div><div class='add'>+		/* FW modes require FAMS2 */</div><div class='add'>+		strategy_matches_drr_requirements = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return strategy_matches_drr_requirements;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_instance *pmo,</div><div class='add'>+		const struct display_configuation_with_meta *display_cfg,</div><div class='add'>+		const struct dml2_pmo_pstate_strategy *pstate_strategy)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	unsigned int stream_index = 0;</div><div class='add'>+</div><div class='add'>+	unsigned int svp_count = 0;</div><div class='add'>+	unsigned int svp_stream_mask = 0;</div><div class='add'>+	unsigned int drr_count = 0;</div><div class='add'>+	unsigned int drr_stream_mask = 0;</div><div class='add'>+	unsigned int vactive_count = 0;</div><div class='add'>+	unsigned int vactive_stream_mask = 0;</div><div class='add'>+	unsigned int vblank_count = 0;</div><div class='add'>+	unsigned int vblank_stream_mask = 0;</div><div class='add'>+</div><div class='add'>+	bool strategy_matches_forced_requirements = true;</div><div class='add'>+	bool strategy_matches_drr_requirements = true;</div><div class='add'>+</div><div class='add'>+	// Tabulate everything</div><div class='add'>+	for (stream_index = 0; stream_index &lt; display_cfg-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+</div><div class='add'>+		if (!all_planes_match_method(display_cfg, s-&gt;pmo_dcn4.stream_plane_mask[stream_index],</div><div class='add'>+			pstate_strategy-&gt;per_stream_pstate_method[stream_index])) {</div><div class='add'>+			strategy_matches_forced_requirements = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		strategy_matches_drr_requirements &amp;=</div><div class='add'>+			stream_matches_drr_policy(pmo, display_cfg, pstate_strategy-&gt;per_stream_pstate_method[stream_index], stream_index);</div><div class='add'>+</div><div class='add'>+		if (pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp ||</div><div class='add'>+			pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp_drr) {</div><div class='add'>+			svp_count++;</div><div class='add'>+			set_bit_in_bitfield(&amp;svp_stream_mask, stream_index);</div><div class='add'>+		} else if (pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_drr) {</div><div class='add'>+			drr_count++;</div><div class='add'>+			set_bit_in_bitfield(&amp;drr_stream_mask, stream_index);</div><div class='add'>+		} else if (pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_vactive ||</div><div class='add'>+			pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vactive_drr) {</div><div class='add'>+			vactive_count++;</div><div class='add'>+			set_bit_in_bitfield(&amp;vactive_stream_mask, stream_index);</div><div class='add'>+		} else if (pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_vblank ||</div><div class='add'>+			pstate_strategy-&gt;per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vblank_drr) {</div><div class='add'>+			vblank_count++;</div><div class='add'>+			set_bit_in_bitfield(&amp;vblank_stream_mask, stream_index);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!strategy_matches_forced_requirements || !strategy_matches_drr_requirements)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (vactive_count &gt; 0 &amp;&amp; !all_timings_support_vactive(pmo, display_cfg, vactive_stream_mask))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (vblank_count &gt; 0 &amp;&amp; (pmo-&gt;options-&gt;disable_vblank || !all_timings_support_vblank(pmo, display_cfg, vblank_stream_mask)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (drr_count &gt; 0 &amp;&amp; (pmo-&gt;options-&gt;disable_drr_var || !all_timings_support_drr(pmo, display_cfg, drr_stream_mask)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (svp_count &gt; 0 &amp;&amp; (pmo-&gt;options-&gt;disable_svp || !all_timings_support_svp(pmo, display_cfg, svp_stream_mask)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return is_config_schedulable(pmo, display_cfg, pstate_strategy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_vactive_pstate_margin(const struct display_configuation_with_meta *display_cfg, int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int min_vactive_margin_us = 0xFFFFFFF;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_PLANES; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, i)) {</div><div class='add'>+			if (display_cfg-&gt;mode_support_result.cfg_support_info.plane_support_info[i].dram_change_latency_hiding_margin_in_active &lt; min_vactive_margin_us)</div><div class='add'>+				min_vactive_margin_us = display_cfg-&gt;mode_support_result.cfg_support_info.plane_support_info[i].dram_change_latency_hiding_margin_in_active;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return min_vactive_margin_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned char i;</div><div class='add'>+	int max_vactive_fill_us = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DML2_MAX_PLANES; i++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, i)) {</div><div class='add'>+			if (display_cfg-&gt;mode_support_result.cfg_support_info.plane_support_info[i].vactive_det_fill_delay_us[dml2_pstate_type_uclk] &gt; max_vactive_fill_us)</div><div class='add'>+				max_vactive_fill_us = display_cfg-&gt;mode_support_result.cfg_support_info.plane_support_info[i].vactive_det_fill_delay_us[dml2_pstate_type_uclk];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return max_vactive_fill_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void build_pstate_meta_per_stream(struct dml2_pmo_instance *pmo,</div><div class='add'>+	struct display_configuation_with_meta *display_config,</div><div class='add'>+	int stream_index)</div><div class='add'>+{</div><div class='add'>+	const struct dml2_ip_capabilities *ip_caps = pmo-&gt;ip_caps;</div><div class='add'>+	const struct dml2_stream_parameters *stream_descriptor = &amp;display_config-&gt;display_config.stream_descriptors[stream_index];</div><div class='add'>+	const struct core_stream_support_info *stream_info = &amp;display_config-&gt;mode_support_result.cfg_support_info.stream_support_info[stream_index];</div><div class='add'>+	const struct dml2_timing_cfg *timing = &amp;stream_descriptor-&gt;timing;</div><div class='add'>+	struct dml2_pstate_meta *stream_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_index];</div><div class='add'>+</div><div class='add'>+	/* worst case all other streams require some programming at the same time, 0 if only 1 stream */</div><div class='add'>+	unsigned int contention_delay_us = (ip_caps-&gt;fams2.vertical_interrupt_ack_delay_us +</div><div class='add'>+			(unsigned int)math_max3(ip_caps-&gt;fams2.subvp_programming_delay_us, ip_caps-&gt;fams2.drr_programming_delay_us, ip_caps-&gt;fams2.allow_programming_delay_us)) *</div><div class='add'>+			(display_config-&gt;display_config.num_streams - 1);</div><div class='add'>+</div><div class='add'>+	/* common */</div><div class='add'>+	stream_pstate_meta-&gt;valid = true;</div><div class='add'>+	stream_pstate_meta-&gt;otg_vline_time_us = (double)timing-&gt;h_total / timing-&gt;pixel_clock_khz * 1000.0;</div><div class='add'>+	stream_pstate_meta-&gt;nom_vtotal = stream_descriptor-&gt;timing.vblank_nom + stream_descriptor-&gt;timing.v_active;</div><div class='add'>+	stream_pstate_meta-&gt;nom_refresh_rate_hz = timing-&gt;pixel_clock_khz * 1000.0 /</div><div class='add'>+			(stream_pstate_meta-&gt;nom_vtotal * timing-&gt;h_total);</div><div class='add'>+	stream_pstate_meta-&gt;nom_frame_time_us =</div><div class='add'>+			(double)stream_pstate_meta-&gt;nom_vtotal * stream_pstate_meta-&gt;otg_vline_time_us;</div><div class='add'>+	stream_pstate_meta-&gt;vblank_start = timing-&gt;v_blank_end + timing-&gt;v_active;</div><div class='add'>+</div><div class='add'>+	if (stream_descriptor-&gt;timing.drr_config.enabled == true) {</div><div class='add'>+		if (stream_descriptor-&gt;timing.drr_config.min_refresh_uhz != 0.0) {</div><div class='add'>+			stream_pstate_meta-&gt;max_vtotal = (unsigned int)math_floor((double)stream_descriptor-&gt;timing.pixel_clock_khz /</div><div class='add'>+					((double)stream_descriptor-&gt;timing.drr_config.min_refresh_uhz * stream_descriptor-&gt;timing.h_total) * 1e9);</div><div class='add'>+		} else {</div><div class='add'>+			/* assume min of 48Hz */</div><div class='add'>+			stream_pstate_meta-&gt;max_vtotal = (unsigned int)math_floor((double)stream_descriptor-&gt;timing.pixel_clock_khz /</div><div class='add'>+					(48000000.0 * stream_descriptor-&gt;timing.h_total) * 1e9);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		stream_pstate_meta-&gt;max_vtotal = stream_pstate_meta-&gt;nom_vtotal;</div><div class='add'>+	}</div><div class='add'>+	stream_pstate_meta-&gt;min_refresh_rate_hz = timing-&gt;pixel_clock_khz * 1000.0 /</div><div class='add'>+			(stream_pstate_meta-&gt;max_vtotal * timing-&gt;h_total);</div><div class='add'>+	stream_pstate_meta-&gt;max_frame_time_us =</div><div class='add'>+			(double)stream_pstate_meta-&gt;max_vtotal * stream_pstate_meta-&gt;otg_vline_time_us;</div><div class='add'>+</div><div class='add'>+	stream_pstate_meta-&gt;scheduling_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.scheduling_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	stream_pstate_meta-&gt;vertical_interrupt_ack_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.vertical_interrupt_ack_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	stream_pstate_meta-&gt;contention_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(contention_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	/* worst case allow to target needs to account for all streams' allow events overlapping, and 1 line for error */</div><div class='add'>+	stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines =</div><div class='add'>+			(unsigned int)(math_ceil((ip_caps-&gt;fams2.vertical_interrupt_ack_delay_us + contention_delay_us + ip_caps-&gt;fams2.allow_programming_delay_us) / stream_pstate_meta-&gt;otg_vline_time_us)) + 1;</div><div class='add'>+	stream_pstate_meta-&gt;min_allow_width_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.min_allow_width_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	/* this value should account for urgent latency */</div><div class='add'>+	stream_pstate_meta-&gt;blackout_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(pmo-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us /</div><div class='add'>+			stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+</div><div class='add'>+	/* scheduling params should be built based on the worst case for allow_time:disallow_time */</div><div class='add'>+</div><div class='add'>+	/* vactive */</div><div class='add'>+	if (display_config-&gt;display_config.num_streams == 1) {</div><div class='add'>+		/* for single stream, guarantee at least an instant of allow */</div><div class='add'>+		stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_otg_vlines = (unsigned int)math_floor(</div><div class='add'>+				math_max2(0.0,</div><div class='add'>+				timing-&gt;v_active - math_max2(1.0, stream_pstate_meta-&gt;min_allow_width_otg_vlines) - stream_pstate_meta-&gt;blackout_otg_vlines));</div><div class='add'>+	} else {</div><div class='add'>+		/* for multi stream, bound to a max fill time defined by IP caps */</div><div class='add'>+		stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_otg_vlines =</div><div class='add'>+				(unsigned int)math_floor((double)ip_caps-&gt;max_vactive_det_fill_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	}</div><div class='add'>+	stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_us = stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_otg_vlines * stream_pstate_meta-&gt;otg_vline_time_us;</div><div class='add'>+</div><div class='add'>+	if (stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_us &gt; 0.0) {</div><div class='add'>+		stream_pstate_meta-&gt;method_vactive.common.allow_start_otg_vline =</div><div class='add'>+			timing-&gt;v_blank_end + stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_otg_vlines;</div><div class='add'>+		stream_pstate_meta-&gt;method_vactive.common.allow_end_otg_vline =</div><div class='add'>+			stream_pstate_meta-&gt;vblank_start -</div><div class='add'>+			stream_pstate_meta-&gt;blackout_otg_vlines;</div><div class='add'>+	} else {</div><div class='add'>+		stream_pstate_meta-&gt;method_vactive.common.allow_start_otg_vline = 0;</div><div class='add'>+		stream_pstate_meta-&gt;method_vactive.common.allow_end_otg_vline = 0;</div><div class='add'>+	}</div><div class='add'>+	stream_pstate_meta-&gt;method_vactive.common.period_us = stream_pstate_meta-&gt;nom_frame_time_us;</div><div class='add'>+	build_method_scheduling_params(&amp;stream_pstate_meta-&gt;method_vactive.common, stream_pstate_meta);</div><div class='add'>+</div><div class='add'>+	/* vblank */</div><div class='add'>+	stream_pstate_meta-&gt;method_vblank.common.allow_start_otg_vline = stream_pstate_meta-&gt;vblank_start;</div><div class='add'>+	stream_pstate_meta-&gt;method_vblank.common.allow_end_otg_vline =</div><div class='add'>+			stream_pstate_meta-&gt;method_vblank.common.allow_start_otg_vline + 1;</div><div class='add'>+	stream_pstate_meta-&gt;method_vblank.common.period_us = stream_pstate_meta-&gt;nom_frame_time_us;</div><div class='add'>+	build_method_scheduling_params(&amp;stream_pstate_meta-&gt;method_vblank.common, stream_pstate_meta);</div><div class='add'>+</div><div class='add'>+	/* subvp */</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.programming_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.subvp_programming_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.df_throttle_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.subvp_df_throttle_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.prefetch_to_mall_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.subvp_prefetch_to_mall_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.phantom_vactive =</div><div class='add'>+			stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines +</div><div class='add'>+			stream_pstate_meta-&gt;min_allow_width_otg_vlines +</div><div class='add'>+			stream_info-&gt;phantom_min_v_active;</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.phantom_vfp =</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.df_throttle_delay_otg_vlines;</div><div class='add'>+	/* phantom vtotal = v_bp(vstartup) + v_sync(1) + v_fp(throttle_delay) + v_active(allow_to_target + min_allow + min_vactive)*/</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.phantom_vtotal =</div><div class='add'>+			stream_info-&gt;phantom_v_startup +</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.phantom_vfp +</div><div class='add'>+			1 +</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.df_throttle_delay_otg_vlines +</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.phantom_vactive;</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.common.allow_start_otg_vline =</div><div class='add'>+			stream_descriptor-&gt;timing.v_blank_end +</div><div class='add'>+			stream_pstate_meta-&gt;contention_delay_otg_vlines +</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.programming_delay_otg_vlines +</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.phantom_vtotal +</div><div class='add'>+			stream_pstate_meta-&gt;method_subvp.prefetch_to_mall_delay_otg_vlines +</div><div class='add'>+			stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines;</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.common.allow_end_otg_vline =</div><div class='add'>+			stream_pstate_meta-&gt;vblank_start -</div><div class='add'>+			stream_pstate_meta-&gt;blackout_otg_vlines;</div><div class='add'>+	stream_pstate_meta-&gt;method_subvp.common.period_us = stream_pstate_meta-&gt;nom_frame_time_us;</div><div class='add'>+	build_method_scheduling_params(&amp;stream_pstate_meta-&gt;method_subvp.common, stream_pstate_meta);</div><div class='add'>+</div><div class='add'>+	/* drr */</div><div class='add'>+	stream_pstate_meta-&gt;method_drr.programming_delay_otg_vlines =</div><div class='add'>+			(unsigned int)math_ceil(ip_caps-&gt;fams2.drr_programming_delay_us / stream_pstate_meta-&gt;otg_vline_time_us);</div><div class='add'>+	stream_pstate_meta-&gt;method_drr.common.allow_start_otg_vline =</div><div class='add'>+			stream_pstate_meta-&gt;vblank_start +</div><div class='add'>+			stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines;</div><div class='add'>+	stream_pstate_meta-&gt;method_drr.common.period_us = stream_pstate_meta-&gt;nom_frame_time_us;</div><div class='add'>+	if (display_config-&gt;display_config.num_streams &lt;= 1) {</div><div class='add'>+		/* only need to stretch vblank for blackout time */</div><div class='add'>+		stream_pstate_meta-&gt;method_drr.stretched_vtotal =</div><div class='add'>+				stream_pstate_meta-&gt;nom_vtotal +</div><div class='add'>+				stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines +</div><div class='add'>+				stream_pstate_meta-&gt;min_allow_width_otg_vlines +</div><div class='add'>+				stream_pstate_meta-&gt;blackout_otg_vlines;</div><div class='add'>+	} else {</div><div class='add'>+		/* multi display needs to always be schedulable */</div><div class='add'>+		stream_pstate_meta-&gt;method_drr.stretched_vtotal =</div><div class='add'>+				stream_pstate_meta-&gt;nom_vtotal * 2 +</div><div class='add'>+				stream_pstate_meta-&gt;allow_to_target_delay_otg_vlines +</div><div class='add'>+				stream_pstate_meta-&gt;min_allow_width_otg_vlines +</div><div class='add'>+				stream_pstate_meta-&gt;blackout_otg_vlines;</div><div class='add'>+	}</div><div class='add'>+	stream_pstate_meta-&gt;method_drr.common.allow_end_otg_vline =</div><div class='add'>+			stream_pstate_meta-&gt;method_drr.stretched_vtotal -</div><div class='add'>+			stream_pstate_meta-&gt;blackout_otg_vlines;</div><div class='add'>+	build_method_scheduling_params(&amp;stream_pstate_meta-&gt;method_drr.common, stream_pstate_meta);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void build_subvp_meta_per_stream(struct dml2_pmo_instance *pmo,</div><div class='add'>+	struct display_configuation_with_meta *display_config,</div><div class='add'>+	int stream_index)</div><div class='add'>+{</div><div class='add'>+	struct dml2_implicit_svp_meta *stream_svp_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_svp_meta[stream_index];</div><div class='add'>+	struct dml2_pstate_meta *stream_pstate_meta = &amp;pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_index];</div><div class='add'>+</div><div class='add'>+	stream_svp_meta-&gt;valid = true;</div><div class='add'>+</div><div class='add'>+	/* PMO FAMS2 precaulcates these values */</div><div class='add'>+	stream_svp_meta-&gt;v_active = stream_pstate_meta-&gt;method_subvp.phantom_vactive;</div><div class='add'>+	stream_svp_meta-&gt;v_front_porch = stream_pstate_meta-&gt;method_subvp.phantom_vfp;</div><div class='add'>+	stream_svp_meta-&gt;v_total = stream_pstate_meta-&gt;method_subvp.phantom_vtotal;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+	struct dml2_optimization_stage3_state *state = &amp;in_out-&gt;base_display_config-&gt;stage3;</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	struct display_configuation_with_meta *display_config;</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+	const struct dml2_pmo_pstate_strategy *strategy_list = NULL;</div><div class='add'>+	struct dml2_pmo_pstate_strategy override_base_strategy = { 0 };</div><div class='add'>+	unsigned int strategy_list_size = 0;</div><div class='add'>+	unsigned int plane_index, stream_index, i;</div><div class='add'>+	bool build_override_strategy = true;</div><div class='add'>+</div><div class='add'>+	state-&gt;performed = true;</div><div class='add'>+	in_out-&gt;base_display_config-&gt;stage3.min_clk_index_for_latency = in_out-&gt;base_display_config-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+</div><div class='add'>+	display_config = in_out-&gt;base_display_config;</div><div class='add'>+	display_config-&gt;display_config.overrides.enable_subvp_implicit_pmo = true;</div><div class='add'>+</div><div class='add'>+	memset(s, 0, sizeof(struct dml2_pmo_scratch));</div><div class='add'>+</div><div class='add'>+	if (display_config-&gt;display_config.overrides.all_streams_blanked) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn4.min_latency_index = in_out-&gt;base_display_config-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn4.max_latency_index = pmo-&gt;mcg_clock_table_size;</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn4.cur_latency_index = in_out-&gt;base_display_config-&gt;stage1.min_clk_index_for_latency;</div><div class='add'>+</div><div class='add'>+	// First build the stream plane mask (array of bitfields indexed by stream, indicating plane mapping)</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		plane_descriptor = &amp;display_config-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+		set_bit_in_bitfield(&amp;s-&gt;pmo_dcn4.stream_plane_mask[plane_descriptor-&gt;stream_index], plane_index);</div><div class='add'>+</div><div class='add'>+		state-&gt;pstate_switch_modes[plane_index] = dml2_pstate_method_vactive;</div><div class='add'>+</div><div class='add'>+		build_override_strategy &amp;= plane_descriptor-&gt;overrides.uclk_pstate_change_strategy != dml2_uclk_pstate_change_strategy_auto;</div><div class='add'>+		override_base_strategy.per_stream_pstate_method[plane_descriptor-&gt;stream_index] =</div><div class='add'>+				uclk_pstate_strategy_override_to_pstate_method(plane_descriptor-&gt;overrides.uclk_pstate_change_strategy);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Figure out which streams can do vactive, and also build up implicit SVP and FAMS2 meta</div><div class='add'>+	for (stream_index = 0; stream_index &lt; display_config-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		if (get_vactive_pstate_margin(display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index]) &gt;= (int)(MIN_VACTIVE_MARGIN_PCT * pmo-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us))</div><div class='add'>+			set_bit_in_bitfield(&amp;s-&gt;pmo_dcn4.stream_vactive_capability_mask, stream_index);</div><div class='add'>+</div><div class='add'>+		/* FAMS2 meta */</div><div class='add'>+		build_pstate_meta_per_stream(pmo, display_config, stream_index);</div><div class='add'>+</div><div class='add'>+		/* SVP meta */</div><div class='add'>+		build_subvp_meta_per_stream(pmo, display_config, stream_index);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* get synchronized timing groups */</div><div class='add'>+	build_synchronized_timing_groups(pmo, display_config);</div><div class='add'>+</div><div class='add'>+	if (build_override_strategy) {</div><div class='add'>+		/* build expanded override strategy list (no permutations) */</div><div class='add'>+		override_base_strategy.allow_state_increase = true;</div><div class='add'>+		s-&gt;pmo_dcn4.num_expanded_override_strategies = 0;</div><div class='add'>+		insert_strategy_into_expanded_list(&amp;override_base_strategy,</div><div class='add'>+				display_config-&gt;display_config.num_streams,</div><div class='add'>+				s-&gt;pmo_dcn4.expanded_override_strategy_list,</div><div class='add'>+				&amp;s-&gt;pmo_dcn4.num_expanded_override_strategies);</div><div class='add'>+		expand_variant_strategy(&amp;override_base_strategy,</div><div class='add'>+				display_config-&gt;display_config.num_streams,</div><div class='add'>+				false,</div><div class='add'>+				s-&gt;pmo_dcn4.expanded_override_strategy_list,</div><div class='add'>+				&amp;s-&gt;pmo_dcn4.num_expanded_override_strategies);</div><div class='add'>+</div><div class='add'>+		/* use override strategy list */</div><div class='add'>+		strategy_list = s-&gt;pmo_dcn4.expanded_override_strategy_list;</div><div class='add'>+		strategy_list_size = s-&gt;pmo_dcn4.num_expanded_override_strategies;</div><div class='add'>+	} else {</div><div class='add'>+		/* use predefined strategy list */</div><div class='add'>+		strategy_list = get_expanded_strategy_list(&amp;pmo-&gt;init_data, display_config-&gt;display_config.num_streams);</div><div class='add'>+		strategy_list_size = get_num_expanded_strategies(&amp;pmo-&gt;init_data, display_config-&gt;display_config.num_streams);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!strategy_list || strategy_list_size == 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	s-&gt;pmo_dcn4.num_pstate_candidates = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; strategy_list_size &amp;&amp; s-&gt;pmo_dcn4.num_pstate_candidates &lt; DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE; i++) {</div><div class='add'>+		if (validate_pstate_support_strategy_cofunctionality(pmo, display_config, &amp;strategy_list[i])) {</div><div class='add'>+			insert_into_candidate_list(&amp;strategy_list[i], display_config-&gt;display_config.num_streams, s);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (s-&gt;pmo_dcn4.num_pstate_candidates &gt; 0) {</div><div class='add'>+		s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.num_pstate_candidates-1].allow_state_increase = true;</div><div class='add'>+		s-&gt;pmo_dcn4.cur_pstate_candidate = -1;</div><div class='add'>+		return true;</div><div class='add'>+	} else {</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reset_display_configuration(struct display_configuation_with_meta *display_config)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+	struct dml2_plane_parameters *plane;</div><div class='add'>+</div><div class='add'>+	for (stream_index = 0; stream_index &lt; display_config-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		display_config-&gt;stage3.stream_svp_meta[stream_index].valid = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		plane = &amp;display_config-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+		// Unset SubVP</div><div class='add'>+		plane-&gt;overrides.legacy_svp_config = dml2_svp_mode_override_auto;</div><div class='add'>+</div><div class='add'>+		// Remove reserve time</div><div class='add'>+		plane-&gt;overrides.reserved_vblank_time_ns = 0;</div><div class='add'>+</div><div class='add'>+		// Reset strategy to auto</div><div class='add'>+		plane-&gt;overrides.uclk_pstate_change_strategy = dml2_uclk_pstate_change_strategy_auto;</div><div class='add'>+</div><div class='add'>+		display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_na;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	struct dml2_plane_parameters *plane;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			plane = &amp;display_config-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+			plane-&gt;overrides.uclk_pstate_change_strategy = dml2_uclk_pstate_change_strategy_force_drr;</div><div class='add'>+</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_drr;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_svp_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_scratch *scratch = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	int stream_index = -1;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			stream_index = (char)display_config-&gt;display_config.plane_descriptors[plane_index].stream_index;</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_svp;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (stream_index &gt;= 0) {</div><div class='add'>+		memcpy(&amp;display_config-&gt;stage3.stream_svp_meta[stream_index],</div><div class='add'>+			&amp;scratch-&gt;pmo_dcn4.stream_svp_meta[stream_index],</div><div class='add'>+			sizeof(struct dml2_implicit_svp_meta));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_svp_drr_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_scratch *scratch = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	int stream_index = -1;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			stream_index = (char)display_config-&gt;display_config.plane_descriptors[plane_index].stream_index;</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_svp_drr;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (stream_index &gt;= 0) {</div><div class='add'>+		memcpy(&amp;display_config-&gt;stage3.stream_svp_meta[stream_index],</div><div class='add'>+			&amp;scratch-&gt;pmo_dcn4.stream_svp_meta[stream_index],</div><div class='add'>+			sizeof(struct dml2_implicit_svp_meta));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_vblank_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	struct dml2_plane_parameters *plane;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			plane = &amp;display_config-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+			plane-&gt;overrides.reserved_vblank_time_ns = (long)math_max2(pmo-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us * 1000.0,</div><div class='add'>+					plane-&gt;overrides.reserved_vblank_time_ns);</div><div class='add'>+</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vblank;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_vblank_drr_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	struct dml2_plane_parameters *plane;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			plane = &amp;display_config-&gt;display_config.plane_descriptors[plane_index];</div><div class='add'>+</div><div class='add'>+			plane-&gt;overrides.reserved_vblank_time_ns = (long)(pmo-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us * 1000);</div><div class='add'>+</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_vblank_drr;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_vactive_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			stream_index = display_config-&gt;display_config.plane_descriptors[plane_index].stream_index;</div><div class='add'>+</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vactive;</div><div class='add'>+</div><div class='add'>+			if (!pmo-&gt;options-&gt;disable_vactive_det_fill_bw_pad) {</div><div class='add'>+				display_config-&gt;display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] =</div><div class='add'>+					(unsigned int)math_floor(pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_planes_for_vactive_drr_by_mask(struct display_configuation_with_meta *display_config,</div><div class='add'>+	struct dml2_pmo_instance *pmo,</div><div class='add'>+	int plane_mask)</div><div class='add'>+{</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			stream_index = display_config-&gt;display_config.plane_descriptors[plane_index].stream_index;</div><div class='add'>+</div><div class='add'>+			display_config-&gt;stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_vactive_drr;</div><div class='add'>+</div><div class='add'>+			if (!pmo-&gt;options-&gt;disable_vactive_det_fill_bw_pad) {</div><div class='add'>+				display_config-&gt;display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] =</div><div class='add'>+					(unsigned int)math_floor(pmo-&gt;scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool setup_display_config(struct display_configuation_with_meta *display_config, struct dml2_pmo_instance *pmo, int strategy_index)</div><div class='add'>+{</div><div class='add'>+	struct dml2_pmo_scratch *scratch = &amp;pmo-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	bool fams2_required = false;</div><div class='add'>+	bool success = true;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+</div><div class='add'>+	reset_display_configuration(display_config);</div><div class='add'>+</div><div class='add'>+	for (stream_index = 0; stream_index &lt; display_config-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+</div><div class='add'>+		if (pmo-&gt;scratch.pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_na) {</div><div class='add'>+			success = false;</div><div class='add'>+			break;</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_vactive) {</div><div class='add'>+			setup_planes_for_vactive_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_vblank) {</div><div class='add'>+			setup_planes_for_vblank_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp) {</div><div class='add'>+			fams2_required = true;</div><div class='add'>+			setup_planes_for_svp_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vactive_drr) {</div><div class='add'>+			fams2_required = true;</div><div class='add'>+			setup_planes_for_vactive_drr_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vblank_drr) {</div><div class='add'>+			fams2_required = true;</div><div class='add'>+			setup_planes_for_vblank_drr_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp_drr) {</div><div class='add'>+			fams2_required = true;</div><div class='add'>+			setup_planes_for_svp_drr_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		} else if (scratch-&gt;pmo_dcn4.pstate_strategy_candidates[strategy_index].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_drr) {</div><div class='add'>+			fams2_required = true;</div><div class='add'>+			setup_planes_for_drr_by_mask(display_config, pmo, scratch-&gt;pmo_dcn4.stream_plane_mask[stream_index]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* copy FAMS2 meta */</div><div class='add'>+	if (success) {</div><div class='add'>+		display_config-&gt;stage3.fams2_required = fams2_required;</div><div class='add'>+		memcpy(&amp;display_config-&gt;stage3.stream_pstate_meta,</div><div class='add'>+			&amp;scratch-&gt;pmo_dcn4.stream_pstate_meta,</div><div class='add'>+			sizeof(struct dml2_pstate_meta) * DML2_MAX_PLANES);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_minimum_reserved_time_us_for_planes(struct display_configuation_with_meta *display_config, int plane_mask)</div><div class='add'>+{</div><div class='add'>+	int min_time_us = 0xFFFFFF;</div><div class='add'>+	unsigned int plane_index = 0;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; display_config-&gt;display_config.num_planes; plane_index++) {</div><div class='add'>+		if (is_bit_set_in_bitfield(plane_mask, plane_index)) {</div><div class='add'>+			if (min_time_us &gt; (display_config-&gt;display_config.plane_descriptors[plane_index].overrides.reserved_vblank_time_ns / 1000))</div><div class='add'>+				min_time_us = display_config-&gt;display_config.plane_descriptors[plane_index].overrides.reserved_vblank_time_ns / 1000;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return min_time_us;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool p_state_supported = true;</div><div class='add'>+	unsigned int stream_index;</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;in_out-&gt;instance-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	int MIN_VACTIVE_MARGIN_VBLANK = 0;</div><div class='add'>+	int MIN_VACTIVE_MARGIN_DRR = 0;</div><div class='add'>+	int REQUIRED_RESERVED_TIME = 0;</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;base_display_config-&gt;display_config.overrides.all_streams_blanked) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	MIN_VACTIVE_MARGIN_VBLANK = INT_MIN;</div><div class='add'>+	MIN_VACTIVE_MARGIN_DRR = INT_MIN;</div><div class='add'>+	REQUIRED_RESERVED_TIME = (int)in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us;</div><div class='add'>+</div><div class='add'>+	if (s-&gt;pmo_dcn4.cur_pstate_candidate &lt; 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (stream_index = 0; stream_index &lt; in_out-&gt;base_display_config-&gt;display_config.num_streams; stream_index++) {</div><div class='add'>+		struct dml2_pstate_meta *stream_pstate_meta = &amp;s-&gt;pmo_dcn4.stream_pstate_meta[stream_index];</div><div class='add'>+</div><div class='add'>+		if (s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_vactive ||</div><div class='add'>+				s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vactive_drr) {</div><div class='add'>+			if (get_vactive_pstate_margin(in_out-&gt;base_display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index]) &lt; (MIN_VACTIVE_MARGIN_PCT * in_out-&gt;instance-&gt;soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us) ||</div><div class='add'>+					get_vactive_det_fill_latency_delay_us(in_out-&gt;base_display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index]) &gt; stream_pstate_meta-&gt;method_vactive.max_vactive_det_fill_delay_us) {</div><div class='add'>+				p_state_supported = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else if (s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_vblank ||</div><div class='add'>+				s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vblank_drr) {</div><div class='add'>+			if (get_minimum_reserved_time_us_for_planes(in_out-&gt;base_display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index]) &lt;</div><div class='add'>+				REQUIRED_RESERVED_TIME ||</div><div class='add'>+				get_vactive_pstate_margin(in_out-&gt;base_display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index]) &lt; MIN_VACTIVE_MARGIN_VBLANK) {</div><div class='add'>+				p_state_supported = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else if (s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp ||</div><div class='add'>+				s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_svp_drr) {</div><div class='add'>+			if (in_out-&gt;base_display_config-&gt;stage3.stream_svp_meta[stream_index].valid == false) {</div><div class='add'>+				p_state_supported = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else if (s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_drr) {</div><div class='add'>+			if (!all_planes_match_method(in_out-&gt;base_display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index], dml2_pstate_method_fw_drr) ||</div><div class='add'>+				get_vactive_pstate_margin(in_out-&gt;base_display_config, s-&gt;pmo_dcn4.stream_plane_mask[stream_index]) &lt; MIN_VACTIVE_MARGIN_DRR) {</div><div class='add'>+				p_state_supported = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		} else if (s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_na) {</div><div class='add'>+			p_state_supported = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return p_state_supported;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool success = false;</div><div class='add'>+	struct dml2_pmo_scratch *s = &amp;in_out-&gt;instance-&gt;scratch;</div><div class='add'>+</div><div class='add'>+	memcpy(in_out-&gt;optimized_display_config, in_out-&gt;base_display_config, sizeof(struct display_configuation_with_meta));</div><div class='add'>+</div><div class='add'>+	if (in_out-&gt;last_candidate_failed) {</div><div class='add'>+		if (s-&gt;pmo_dcn4.pstate_strategy_candidates[s-&gt;pmo_dcn4.cur_pstate_candidate].allow_state_increase &amp;&amp;</div><div class='add'>+			s-&gt;pmo_dcn4.cur_latency_index &lt; s-&gt;pmo_dcn4.max_latency_index - 1) {</div><div class='add'>+			s-&gt;pmo_dcn4.cur_latency_index++;</div><div class='add'>+</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!success) {</div><div class='add'>+		s-&gt;pmo_dcn4.cur_latency_index = s-&gt;pmo_dcn4.min_latency_index;</div><div class='add'>+		s-&gt;pmo_dcn4.cur_pstate_candidate++;</div><div class='add'>+</div><div class='add'>+		if (s-&gt;pmo_dcn4.cur_pstate_candidate &lt; s-&gt;pmo_dcn4.num_pstate_candidates) {</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (success) {</div><div class='add'>+		in_out-&gt;optimized_display_config-&gt;stage3.min_clk_index_for_latency = s-&gt;pmo_dcn4.cur_latency_index;</div><div class='add'>+		setup_display_config(in_out-&gt;optimized_display_config, in_out-&gt;instance, in_out-&gt;instance-&gt;scratch.pmo_dcn4.cur_pstate_candidate);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool success = true;</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+	bool stutter_period_meets_z8_eco = true;</div><div class='add'>+	bool z8_stutter_optimization_too_expensive = false;</div><div class='add'>+	bool stutter_optimization_too_expensive = false;</div><div class='add'>+	double line_time_us, vblank_nom_time_us;</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us &gt; 0 &amp;&amp;</div><div class='add'>+		pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us &gt; 0 &amp;&amp;</div><div class='add'>+		pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us &lt; pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us)</div><div class='add'>+		return false; // Unexpected SoCBB setup</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;base_display_config-&gt;display_config.num_planes; i++) {</div><div class='add'>+		if (in_out-&gt;base_display_config-&gt;mode_support_result.cfg_support_info.plane_support_info[i].active_latency_hiding_us &lt;</div><div class='add'>+			pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us + pmo-&gt;soc_bb-&gt;power_management_parameters.z8_min_idle_time) {</div><div class='add'>+			stutter_period_meets_z8_eco = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;base_display_config-&gt;display_config.num_streams; i++) {</div><div class='add'>+		line_time_us = (double)in_out-&gt;base_display_config-&gt;display_config.stream_descriptors[i].timing.h_total / (in_out-&gt;base_display_config-&gt;display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000;</div><div class='add'>+		vblank_nom_time_us = line_time_us * in_out-&gt;base_display_config-&gt;display_config.stream_descriptors[i].timing.vblank_nom;</div><div class='add'>+</div><div class='add'>+		if (vblank_nom_time_us &lt; pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) {</div><div class='add'>+			z8_stutter_optimization_too_expensive = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (vblank_nom_time_us &lt; pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) {</div><div class='add'>+			stutter_optimization_too_expensive = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates = 0;</div><div class='add'>+	pmo-&gt;scratch.pmo_dcn4.cur_stutter_candidate = 0;</div><div class='add'>+</div><div class='add'>+	if (stutter_period_meets_z8_eco &amp;&amp; !z8_stutter_optimization_too_expensive) {</div><div class='add'>+		if (pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us &gt; 0) {</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us;</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates++;</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn4.z8_vblank_optimizable = true;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn4.z8_vblank_optimizable = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!stutter_optimization_too_expensive &amp;&amp; pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us &gt; 0) {</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us;</div><div class='add'>+		pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates == 0)</div><div class='add'>+		success = false;</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool success = true;</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; in_out-&gt;base_display_config-&gt;display_config.num_planes; i++) {</div><div class='add'>+		if (pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us &gt; 0 &amp;&amp;</div><div class='add'>+			pmo-&gt;scratch.pmo_dcn4.z8_vblank_optimizable &amp;&amp;</div><div class='add'>+			in_out-&gt;base_display_config-&gt;display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns &lt; (int)pmo-&gt;soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us * 1000) {</div><div class='add'>+			success = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		if (pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us &gt; 0 &amp;&amp;</div><div class='add'>+			in_out-&gt;base_display_config-&gt;display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns &lt; (int)pmo-&gt;soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us * 1000) {</div><div class='add'>+			success = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	bool success = false;</div><div class='add'>+	struct dml2_pmo_instance *pmo = in_out-&gt;instance;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	memcpy(in_out-&gt;optimized_display_config, in_out-&gt;base_display_config, sizeof(struct display_configuation_with_meta));</div><div class='add'>+</div><div class='add'>+	if (!in_out-&gt;last_candidate_failed) {</div><div class='add'>+		if (pmo-&gt;scratch.pmo_dcn4.cur_stutter_candidate &lt; pmo-&gt;scratch.pmo_dcn4.num_stutter_candidates) {</div><div class='add'>+			for (i = 0; i &lt; in_out-&gt;optimized_display_config-&gt;display_config.num_planes; i++) {</div><div class='add'>+				/* take the max of the current and the optimal reserved time */</div><div class='add'>+				in_out-&gt;optimized_display_config-&gt;display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns =</div><div class='add'>+						(long)math_max2(pmo-&gt;scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo-&gt;scratch.pmo_dcn4.cur_stutter_candidate] * 1000,</div><div class='add'>+						in_out-&gt;optimized_display_config-&gt;display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h<br/>new file mode 100644<br/>index 000000000000..6baab7ad6ecc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_PMO_FAMS2_DCN4_H__</div><div class='add'>+#define __DML2_PMO_FAMS2_DCN4_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out);</div><div class='add'>+bool pmo_dcn4_fams2_test_for_vmin(struct dml2_pmo_test_for_vmin_in_out *in_out);</div><div class='add'>+bool pmo_dcn4_fams2_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out);</div><div class='add'>+bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_support_in_out *in_out);</div><div class='add'>+bool pmo_dcn4_fams2_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out);</div><div class='add'>+bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out);</div><div class='add'>+bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out);</div><div class='add'>+</div><div class='add'>+void pmo_dcn4_fams2_expand_base_pstate_strategies(</div><div class='add'>+	const struct dml2_pmo_pstate_strategy *base_strategies_list,</div><div class='add'>+	const unsigned int num_base_strategies,</div><div class='add'>+	const unsigned int stream_count,</div><div class='add'>+	struct dml2_pmo_pstate_strategy *expanded_strategy_list,</div><div class='add'>+	unsigned int *num_expanded_strategies);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c<br/>new file mode 100644<br/>index 000000000000..55d2464365d0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c</a></div><div class='hunk'>@@ -0,0 +1,83 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_pmo_factory.h"</div><div class='add'>+#include "dml2_pmo_dcn4_fams2.h"</div><div class='add'>+#include "dml2_pmo_dcn3.h"</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+</div><div class='add'>+static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dummy_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dummy_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (!out)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	memset(out, 0, sizeof(struct dml2_pmo_instance));</div><div class='add'>+</div><div class='add'>+	switch (project_id) {</div><div class='add'>+	case dml2_project_dcn4x_stage1:</div><div class='add'>+		out-&gt;initialize = pmo_dcn4_fams2_initialize;</div><div class='add'>+		out-&gt;optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_dcn4x_stage2:</div><div class='add'>+		out-&gt;initialize = pmo_dcn3_initialize;</div><div class='add'>+</div><div class='add'>+		out-&gt;optimize_dcc_mcache = pmo_dcn3_optimize_dcc_mcache;</div><div class='add'>+</div><div class='add'>+		out-&gt;init_for_vmin = pmo_dcn3_init_for_vmin;</div><div class='add'>+		out-&gt;test_for_vmin = pmo_dcn3_test_for_vmin;</div><div class='add'>+		out-&gt;optimize_for_vmin = pmo_dcn3_optimize_for_vmin;</div><div class='add'>+</div><div class='add'>+		out-&gt;init_for_uclk_pstate = pmo_dcn3_init_for_pstate_support;</div><div class='add'>+		out-&gt;test_for_uclk_pstate = pmo_dcn3_test_for_pstate_support;</div><div class='add'>+		out-&gt;optimize_for_uclk_pstate = pmo_dcn3_optimize_for_pstate_support;</div><div class='add'>+</div><div class='add'>+		out-&gt;init_for_stutter = dummy_init_for_stutter;</div><div class='add'>+		out-&gt;test_for_stutter = dummy_test_for_stutter;</div><div class='add'>+		out-&gt;optimize_for_stutter = dummy_optimize_for_stutter;</div><div class='add'>+</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_dcn4x_stage2_auto_drr_svp:</div><div class='add'>+		out-&gt;initialize = pmo_dcn4_fams2_initialize;</div><div class='add'>+</div><div class='add'>+		out-&gt;optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache;</div><div class='add'>+</div><div class='add'>+		out-&gt;init_for_vmin = pmo_dcn4_fams2_init_for_vmin;</div><div class='add'>+		out-&gt;test_for_vmin = pmo_dcn4_fams2_test_for_vmin;</div><div class='add'>+		out-&gt;optimize_for_vmin = pmo_dcn4_fams2_optimize_for_vmin;</div><div class='add'>+</div><div class='add'>+		out-&gt;init_for_uclk_pstate = pmo_dcn4_fams2_init_for_pstate_support;</div><div class='add'>+		out-&gt;test_for_uclk_pstate = pmo_dcn4_fams2_test_for_pstate_support;</div><div class='add'>+		out-&gt;optimize_for_uclk_pstate = pmo_dcn4_fams2_optimize_for_pstate_support;</div><div class='add'>+</div><div class='add'>+		out-&gt;init_for_stutter = pmo_dcn4_fams2_init_for_stutter;</div><div class='add'>+		out-&gt;test_for_stutter = pmo_dcn4_fams2_test_for_stutter;</div><div class='add'>+		out-&gt;optimize_for_stutter = pmo_dcn4_fams2_optimize_for_stutter;</div><div class='add'>+		result = true;</div><div class='add'>+		break;</div><div class='add'>+	case dml2_project_invalid:</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h<br/>new file mode 100644<br/>index 000000000000..b90f6263cd85<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_PMO_FACTORY_H__</div><div class='add'>+#define __DML2_PMO_FACTORY_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+</div><div class='add'>+bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out);</div><div class='add'>+</div><div class='add'>+#endif
\ No newline at end of file</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c<br/>new file mode 100644<br/>index 000000000000..e17b5ceba447<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c</a></div><div class='hunk'>@@ -0,0 +1,147 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+</div><div class='add'>+#define ASSERT(condition)</div><div class='add'>+</div><div class='add'>+#define isNaN(number) ((number) != (number))</div><div class='add'>+</div><div class='add'>+ /*</div><div class='add'>+  * NOTE:</div><div class='add'>+  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.</div><div class='add'>+  *</div><div class='add'>+  * It doesn't adhere to Linux kernel style and sometimes will do things in odd</div><div class='add'>+  * ways. Unless there is something clearly wrong with it the code should</div><div class='add'>+  * remain as-is as it provides us with a guarantee from HW that it is correct.</div><div class='add'>+  */</div><div class='add'>+</div><div class='add'>+double math_mod(const double arg1, const double arg2)</div><div class='add'>+{</div><div class='add'>+	if (isNaN(arg1))</div><div class='add'>+		return arg2;</div><div class='add'>+	if (isNaN(arg2))</div><div class='add'>+		return arg1;</div><div class='add'>+	return arg1 - arg1 * ((int)(arg1 / arg2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_min2(const double arg1, const double arg2)</div><div class='add'>+{</div><div class='add'>+	if (isNaN(arg1))</div><div class='add'>+		return arg2;</div><div class='add'>+	if (isNaN(arg2))</div><div class='add'>+		return arg1;</div><div class='add'>+	return arg1 &lt; arg2 ? arg1 : arg2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_max2(const double arg1, const double arg2)</div><div class='add'>+{</div><div class='add'>+	if (isNaN(arg1))</div><div class='add'>+		return arg2;</div><div class='add'>+	if (isNaN(arg2))</div><div class='add'>+		return arg1;</div><div class='add'>+	return arg1 &gt; arg2 ? arg1 : arg2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_floor2(const double arg, const double significance)</div><div class='add'>+{</div><div class='add'>+	ASSERT(significance != 0);</div><div class='add'>+</div><div class='add'>+	return ((int)(arg / significance)) * significance;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_floor(const double arg)</div><div class='add'>+{</div><div class='add'>+	return ((int)(arg));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_ceil(const double arg)</div><div class='add'>+{</div><div class='add'>+	return (int)(arg + 0.99999);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_ceil2(const double arg, const double significance)</div><div class='add'>+{</div><div class='add'>+	return ((int)(arg / significance + 0.99999)) * significance;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_max3(double v1, double v2, double v3)</div><div class='add'>+{</div><div class='add'>+	return v3 &gt; math_max2(v1, v2) ? v3 : math_max2(v1, v2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_max4(double v1, double v2, double v3, double v4)</div><div class='add'>+{</div><div class='add'>+	return v4 &gt; math_max3(v1, v2, v3) ? v4 : math_max3(v1, v2, v3);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_max5(double v1, double v2, double v3, double v4, double v5)</div><div class='add'>+{</div><div class='add'>+	return math_max3(v1, v2, v3) &gt; math_max2(v4, v5) ? math_max3(v1, v2, v3) : math_max2(v4, v5);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+float math_pow(float a, float exp)</div><div class='add'>+{</div><div class='add'>+	double temp;</div><div class='add'>+	if ((int)exp == 0)</div><div class='add'>+		return 1;</div><div class='add'>+	temp = math_pow(a, (float)((int)(exp / 2)));</div><div class='add'>+	if (((int)exp % 2) == 0) {</div><div class='add'>+		return (float)(temp * temp);</div><div class='add'>+	} else {</div><div class='add'>+		if ((int)exp &gt; 0)</div><div class='add'>+			return (float)(a * temp * temp);</div><div class='add'>+		else</div><div class='add'>+			return (float)((temp * temp) / a);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_fabs(double a)</div><div class='add'>+{</div><div class='add'>+	if (a &gt; 0)</div><div class='add'>+		return (a);</div><div class='add'>+	else</div><div class='add'>+		return (-a);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+float math_log(float a, float b)</div><div class='add'>+{</div><div class='add'>+	int *const exp_ptr = (int *)(&amp;a);</div><div class='add'>+	int x = *exp_ptr;</div><div class='add'>+	const int log_2 = ((x &gt;&gt; 23) &amp; 255) - 128;</div><div class='add'>+	x &amp;= ~(255 &lt;&lt; 23);</div><div class='add'>+	x += 127 &lt;&lt; 23;</div><div class='add'>+	*exp_ptr = x;</div><div class='add'>+</div><div class='add'>+	a = ((-1.0f / 3) * a + 2) * a - 2.0f / 3;</div><div class='add'>+</div><div class='add'>+	if (b &gt; 2.00001 || b &lt; 1.99999)</div><div class='add'>+		return (a + log_2) / math_log(b, 2);</div><div class='add'>+	else</div><div class='add'>+		return (a + log_2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+float math_log2(float a)</div><div class='add'>+{</div><div class='add'>+	return math_log(a, 2.0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+// approximate log2 value of a input</div><div class='add'>+//  - precise if the input pwr of 2, else the approximation will be an integer = floor(actual_log2)</div><div class='add'>+unsigned int math_log2_approx(unsigned int a)</div><div class='add'>+{</div><div class='add'>+	unsigned int log2_val = 0;</div><div class='add'>+	while (a &gt; 1) {</div><div class='add'>+		a = a &gt;&gt; 1;</div><div class='add'>+		log2_val++;</div><div class='add'>+	}</div><div class='add'>+	return log2_val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+double math_round(double a)</div><div class='add'>+{</div><div class='add'>+	const double round_pt = 0.5;</div><div class='add'>+</div><div class='add'>+	return math_floor(a + round_pt);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h<br/>new file mode 100644<br/>index 000000000000..e13b0c5939b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __LIB_FLOAT_MATH_H__</div><div class='add'>+#define __LIB_FLOAT_MATH_H__</div><div class='add'>+</div><div class='add'>+double math_mod(const double arg1, const double arg2);</div><div class='add'>+double math_min2(const double arg1, const double arg2);</div><div class='add'>+double math_max2(const double arg1, const double arg2);</div><div class='add'>+double math_floor2(const double arg, const double significance);</div><div class='add'>+double math_floor(const double arg);</div><div class='add'>+double math_ceil(const double arg);</div><div class='add'>+double math_ceil2(const double arg, const double significance);</div><div class='add'>+double math_max3(double v1, double v2, double v3);</div><div class='add'>+double math_max4(double v1, double v2, double v3, double v4);</div><div class='add'>+double math_max5(double v1, double v2, double v3, double v4, double v5);</div><div class='add'>+float math_pow(float a, float exp);</div><div class='add'>+double math_fabs(double a);</div><div class='add'>+float math_log(float a, float b);</div><div class='add'>+float math_log2(float a);</div><div class='add'>+unsigned int math_log2_approx(unsigned int a);</div><div class='add'>+double math_round(double a);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c<br/>new file mode 100644<br/>index 000000000000..5a33e2f357f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml_top.h"</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+#include "dml2_top_soc15.h"</div><div class='add'>+</div><div class='add'>+unsigned int dml2_get_instance_size_bytes(void)</div><div class='add'>+{</div><div class='add'>+	return sizeof(struct dml2_instance);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	switch (in_out-&gt;options.project_id) {</div><div class='add'>+	case dml2_project_dcn4x_stage1:</div><div class='add'>+	case dml2_project_dcn4x_stage2:</div><div class='add'>+	case dml2_project_dcn4x_stage2_auto_drr_svp:</div><div class='add'>+		return dml2_top_soc15_initialize_instance(in_out);</div><div class='add'>+	case dml2_project_invalid:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	if (!in_out-&gt;dml2_instance-&gt;funcs.check_mode_supported)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return in_out-&gt;dml2_instance-&gt;funcs.check_mode_supported(in_out);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	if (!in_out-&gt;dml2_instance-&gt;funcs.build_mode_programming)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return in_out-&gt;dml2_instance-&gt;funcs.build_mode_programming(in_out);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_build_mcache_programming(struct dml2_build_mcache_programming_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	if (!in_out-&gt;dml2_instance-&gt;funcs.build_mcache_programming)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return in_out-&gt;dml2_instance-&gt;funcs.build_mcache_programming(in_out);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c<br/>new file mode 100644<br/>index 000000000000..5e14d85821e2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_top_legacy.h"</div><div class='add'>+#include "dml2_top_soc15.h"</div><div class='add'>+#include "dml2_core_factory.h"</div><div class='add'>+#include "dml2_pmo_factory.h"</div><div class='add'>+#include "display_mode_core_structs.h"</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h<br/>new file mode 100644<br/>index 000000000000..14d0ae03dce6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_TOP_LEGACY_H__</div><div class='add'>+#define __DML2_TOP_LEGACY_H__</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+bool dml2_top_legacy_initialize_instance(struct dml2_initialize_instance_in_out *in_out);</div><div class='add'>+#endif /* __DML2_TOP_LEGACY_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c<br/>new file mode 100644<br/>index 000000000000..4a7c4c62111e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c</a></div><div class='hunk'>@@ -0,0 +1,1170 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dml2_top_soc15.h"</div><div class='add'>+#include "dml2_mcg_factory.h"</div><div class='add'>+#include "dml2_dpmm_factory.h"</div><div class='add'>+#include "dml2_core_factory.h"</div><div class='add'>+#include "dml2_pmo_factory.h"</div><div class='add'>+#include "lib_float_math.h"</div><div class='add'>+#include "dml2_debug.h"</div><div class='add'>+static void setup_unoptimized_display_config_with_meta(const struct dml2_instance *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config)</div><div class='add'>+{</div><div class='add'>+	memcpy(&amp;out-&gt;display_config, display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+	out-&gt;stage1.min_clk_index_for_latency = dml-&gt;min_clk_table.dram_bw_table.num_entries - 1; //dml-&gt;min_clk_table.clean_me_up.soc_bb.num_states - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void setup_speculative_display_config_with_meta(const struct dml2_instance *dml, struct display_configuation_with_meta *out, const struct dml2_display_cfg *display_config)</div><div class='add'>+{</div><div class='add'>+	memcpy(&amp;out-&gt;display_config, display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+	out-&gt;stage1.min_clk_index_for_latency = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void copy_display_configuration_with_meta(struct display_configuation_with_meta *dst, const struct display_configuation_with_meta *src)</div><div class='add'>+{</div><div class='add'>+	memcpy(dst, src, sizeof(struct display_configuation_with_meta));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_init_function_min_clk_for_latency(const struct optimization_init_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_stage1_state *state = &amp;params-&gt;display_config-&gt;stage1;</div><div class='add'>+</div><div class='add'>+	state-&gt;performed = true;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_test_function_min_clk_for_latency(const struct optimization_test_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_stage1_state *state = &amp;params-&gt;display_config-&gt;stage1;</div><div class='add'>+</div><div class='add'>+	return state-&gt;min_clk_index_for_latency == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_optimize_function_min_clk_for_latency(const struct optimization_optimize_function_params *params)</div><div class='add'>+{</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;display_config-&gt;stage1.min_clk_index_for_latency &gt; 0) {</div><div class='add'>+		copy_display_configuration_with_meta(params-&gt;optimized_display_config, params-&gt;display_config);</div><div class='add'>+		params-&gt;optimized_display_config-&gt;stage1.min_clk_index_for_latency--;</div><div class='add'>+		result = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_test_function_mcache(const struct optimization_test_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_test_function_locals *l = params-&gt;locals;</div><div class='add'>+	bool mcache_success = false;</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_optimization_test_function_locals));</div><div class='add'>+</div><div class='add'>+	l-&gt;test_mcache.calc_mcache_count_params.dml2_instance = params-&gt;dml;</div><div class='add'>+	l-&gt;test_mcache.calc_mcache_count_params.display_config = &amp;params-&gt;display_config-&gt;display_config;</div><div class='add'>+	l-&gt;test_mcache.calc_mcache_count_params.mcache_allocations = params-&gt;display_config-&gt;stage2.mcache_allocations;</div><div class='add'>+</div><div class='add'>+	result = dml2_top_mcache_calc_mcache_count_and_offsets(&amp;l-&gt;test_mcache.calc_mcache_count_params); // use core to get the basic mcache_allocations</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		l-&gt;test_mcache.assign_global_mcache_ids_params.allocations = params-&gt;display_config-&gt;stage2.mcache_allocations;</div><div class='add'>+		l-&gt;test_mcache.assign_global_mcache_ids_params.num_allocations = params-&gt;display_config-&gt;display_config.num_planes;</div><div class='add'>+</div><div class='add'>+		dml2_top_mcache_assign_global_mcache_ids(&amp;l-&gt;test_mcache.assign_global_mcache_ids_params);</div><div class='add'>+</div><div class='add'>+		l-&gt;test_mcache.validate_admissibility_params.dml2_instance = params-&gt;dml;</div><div class='add'>+		l-&gt;test_mcache.validate_admissibility_params.display_cfg = &amp;params-&gt;display_config-&gt;display_config;</div><div class='add'>+		l-&gt;test_mcache.validate_admissibility_params.mcache_allocations = params-&gt;display_config-&gt;stage2.mcache_allocations;</div><div class='add'>+		l-&gt;test_mcache.validate_admissibility_params.cfg_support_info = &amp;params-&gt;display_config-&gt;mode_support_result.cfg_support_info;</div><div class='add'>+</div><div class='add'>+		mcache_success = dml2_top_mcache_validate_admissability(&amp;l-&gt;test_mcache.validate_admissibility_params); // also find the shift to make mcache allocation works</div><div class='add'>+</div><div class='add'>+		memcpy(params-&gt;display_config-&gt;stage2.per_plane_mcache_support, l-&gt;test_mcache.validate_admissibility_params.per_plane_status, sizeof(bool) * DML2_MAX_PLANES);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return mcache_success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_optimize_function_mcache(const struct optimization_optimize_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_optimize_function_locals *l = params-&gt;locals;</div><div class='add'>+	bool optimize_success = false;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;last_candidate_supported == false)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	copy_display_configuration_with_meta(params-&gt;optimized_display_config, params-&gt;display_config);</div><div class='add'>+</div><div class='add'>+	l-&gt;optimize_mcache.optimize_mcache_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;optimize_mcache.optimize_mcache_params.dcc_mcache_supported = params-&gt;display_config-&gt;stage2.per_plane_mcache_support;</div><div class='add'>+	l-&gt;optimize_mcache.optimize_mcache_params.display_config = &amp;params-&gt;display_config-&gt;display_config;</div><div class='add'>+	l-&gt;optimize_mcache.optimize_mcache_params.optimized_display_cfg = &amp;params-&gt;optimized_display_config-&gt;display_config;</div><div class='add'>+	l-&gt;optimize_mcache.optimize_mcache_params.cfg_support_info = &amp;params-&gt;optimized_display_config-&gt;mode_support_result.cfg_support_info;</div><div class='add'>+</div><div class='add'>+	optimize_success = params-&gt;dml-&gt;pmo_instance.optimize_dcc_mcache(&amp;l-&gt;optimize_mcache.optimize_mcache_params);</div><div class='add'>+</div><div class='add'>+	return optimize_success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_init_function_vmin(const struct optimization_init_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_init_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;vmin.init_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;vmin.init_params.base_display_config = params-&gt;display_config;</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.init_for_vmin(&amp;l-&gt;vmin.init_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_test_function_vmin(const struct optimization_test_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_test_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;test_vmin.pmo_test_vmin_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;test_vmin.pmo_test_vmin_params.display_config = params-&gt;display_config;</div><div class='add'>+	l-&gt;test_vmin.pmo_test_vmin_params.vmin_limits = &amp;params-&gt;dml-&gt;soc_bbox.vmin_limit;</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.test_for_vmin(&amp;l-&gt;test_vmin.pmo_test_vmin_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_optimize_function_vmin(const struct optimization_optimize_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_optimize_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;last_candidate_supported == false)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	l-&gt;optimize_vmin.pmo_optimize_vmin_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;optimize_vmin.pmo_optimize_vmin_params.base_display_config = params-&gt;display_config;</div><div class='add'>+	l-&gt;optimize_vmin.pmo_optimize_vmin_params.optimized_display_config = params-&gt;optimized_display_config;</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.optimize_for_vmin(&amp;l-&gt;optimize_vmin.pmo_optimize_vmin_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_init_function_uclk_pstate(const struct optimization_init_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_init_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;uclk_pstate.init_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;uclk_pstate.init_params.base_display_config = params-&gt;display_config;</div><div class='add'>+</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.init_for_uclk_pstate(&amp;l-&gt;uclk_pstate.init_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_test_function_uclk_pstate(const struct optimization_test_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_test_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;uclk_pstate.test_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;uclk_pstate.test_params.base_display_config = params-&gt;display_config;</div><div class='add'>+</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.test_for_uclk_pstate(&amp;l-&gt;uclk_pstate.test_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_optimize_function_uclk_pstate(const struct optimization_optimize_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_optimize_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;uclk_pstate.optimize_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;uclk_pstate.optimize_params.base_display_config = params-&gt;display_config;</div><div class='add'>+	l-&gt;uclk_pstate.optimize_params.optimized_display_config = params-&gt;optimized_display_config;</div><div class='add'>+	l-&gt;uclk_pstate.optimize_params.last_candidate_failed = !params-&gt;last_candidate_supported;</div><div class='add'>+</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.optimize_for_uclk_pstate(&amp;l-&gt;uclk_pstate.optimize_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_init_function_stutter(const struct optimization_init_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_init_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;uclk_pstate.init_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;uclk_pstate.init_params.base_display_config = params-&gt;display_config;</div><div class='add'>+</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.init_for_stutter(&amp;l-&gt;stutter.stutter_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_test_function_stutter(const struct optimization_test_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_test_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;stutter.stutter_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;stutter.stutter_params.base_display_config = params-&gt;display_config;</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.test_for_stutter(&amp;l-&gt;stutter.stutter_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_optimize_function_stutter(const struct optimization_optimize_function_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_optimization_optimize_function_locals *l = params-&gt;locals;</div><div class='add'>+</div><div class='add'>+	l-&gt;stutter.stutter_params.instance = &amp;params-&gt;dml-&gt;pmo_instance;</div><div class='add'>+	l-&gt;stutter.stutter_params.base_display_config = params-&gt;display_config;</div><div class='add'>+	l-&gt;stutter.stutter_params.optimized_display_config = params-&gt;optimized_display_config;</div><div class='add'>+	l-&gt;stutter.stutter_params.last_candidate_failed = !params-&gt;last_candidate_supported;</div><div class='add'>+	return params-&gt;dml-&gt;pmo_instance.optimize_for_stutter(&amp;l-&gt;stutter.stutter_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_perform_optimization_phase(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params)</div><div class='add'>+{</div><div class='add'>+	bool test_passed = false;</div><div class='add'>+	bool optimize_succeeded = true;</div><div class='add'>+	bool candidate_validation_passed = true;</div><div class='add'>+	struct optimization_init_function_params init_params = { 0 };</div><div class='add'>+	struct optimization_test_function_params test_params = { 0 };</div><div class='add'>+	struct optimization_optimize_function_params optimize_params = { 0 };</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;dml ||</div><div class='add'>+		!params-&gt;optimize_function ||</div><div class='add'>+		!params-&gt;test_function ||</div><div class='add'>+		!params-&gt;display_config ||</div><div class='add'>+		!params-&gt;optimized_display_config)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	copy_display_configuration_with_meta(&amp;l-&gt;cur_candidate_display_cfg, params-&gt;display_config);</div><div class='add'>+</div><div class='add'>+	init_params.locals = &amp;l-&gt;init_function_locals;</div><div class='add'>+	init_params.dml = params-&gt;dml;</div><div class='add'>+	init_params.display_config = &amp;l-&gt;cur_candidate_display_cfg;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;init_function &amp;&amp; !params-&gt;init_function(&amp;init_params))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	test_params.locals = &amp;l-&gt;test_function_locals;</div><div class='add'>+	test_params.dml = params-&gt;dml;</div><div class='add'>+	test_params.display_config = &amp;l-&gt;cur_candidate_display_cfg;</div><div class='add'>+</div><div class='add'>+	test_passed = params-&gt;test_function(&amp;test_params);</div><div class='add'>+</div><div class='add'>+	while (!test_passed &amp;&amp; optimize_succeeded) {</div><div class='add'>+		memset(&amp;optimize_params, 0, sizeof(struct optimization_optimize_function_params));</div><div class='add'>+</div><div class='add'>+		optimize_params.locals = &amp;l-&gt;optimize_function_locals;</div><div class='add'>+		optimize_params.dml = params-&gt;dml;</div><div class='add'>+		optimize_params.display_config = &amp;l-&gt;cur_candidate_display_cfg;</div><div class='add'>+		optimize_params.optimized_display_config = &amp;l-&gt;next_candidate_display_cfg;</div><div class='add'>+		optimize_params.last_candidate_supported = candidate_validation_passed;</div><div class='add'>+</div><div class='add'>+		optimize_succeeded = params-&gt;optimize_function(&amp;optimize_params);</div><div class='add'>+</div><div class='add'>+		if (optimize_succeeded) {</div><div class='add'>+			l-&gt;mode_support_params.instance = &amp;params-&gt;dml-&gt;core_instance;</div><div class='add'>+			l-&gt;mode_support_params.display_cfg = &amp;l-&gt;next_candidate_display_cfg;</div><div class='add'>+			l-&gt;mode_support_params.min_clk_table = &amp;params-&gt;dml-&gt;min_clk_table;</div><div class='add'>+</div><div class='add'>+			if (l-&gt;next_candidate_display_cfg.stage3.performed)</div><div class='add'>+				l-&gt;mode_support_params.min_clk_index = l-&gt;next_candidate_display_cfg.stage3.min_clk_index_for_latency;</div><div class='add'>+			else</div><div class='add'>+				l-&gt;mode_support_params.min_clk_index = l-&gt;next_candidate_display_cfg.stage1.min_clk_index_for_latency;</div><div class='add'>+			candidate_validation_passed = params-&gt;dml-&gt;core_instance.mode_support(&amp;l-&gt;mode_support_params);</div><div class='add'>+			l-&gt;next_candidate_display_cfg.mode_support_result = l-&gt;mode_support_params.mode_support_result;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (optimize_succeeded &amp;&amp; candidate_validation_passed) {</div><div class='add'>+			memset(&amp;test_params, 0, sizeof(struct optimization_test_function_params));</div><div class='add'>+			test_params.locals = &amp;l-&gt;test_function_locals;</div><div class='add'>+			test_params.dml = params-&gt;dml;</div><div class='add'>+			test_params.display_config = &amp;l-&gt;next_candidate_display_cfg;</div><div class='add'>+			test_passed = params-&gt;test_function(&amp;test_params);</div><div class='add'>+</div><div class='add'>+			copy_display_configuration_with_meta(&amp;l-&gt;cur_candidate_display_cfg, &amp;l-&gt;next_candidate_display_cfg);</div><div class='add'>+</div><div class='add'>+			// If optimization is not all or nothing, then store partial progress in output</div><div class='add'>+			if (!params-&gt;all_or_nothing)</div><div class='add'>+				copy_display_configuration_with_meta(params-&gt;optimized_display_config, &amp;l-&gt;next_candidate_display_cfg);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (test_passed)</div><div class='add'>+		copy_display_configuration_with_meta(params-&gt;optimized_display_config, &amp;l-&gt;cur_candidate_display_cfg);</div><div class='add'>+</div><div class='add'>+	return test_passed;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_optimization_perform_optimization_phase_1(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params)</div><div class='add'>+{</div><div class='add'>+	int highest_state, lowest_state, cur_state;</div><div class='add'>+	bool supported = false;</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;dml ||</div><div class='add'>+		!params-&gt;optimize_function ||</div><div class='add'>+		!params-&gt;test_function ||</div><div class='add'>+		!params-&gt;display_config ||</div><div class='add'>+		!params-&gt;optimized_display_config)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	copy_display_configuration_with_meta(&amp;l-&gt;cur_candidate_display_cfg, params-&gt;display_config);</div><div class='add'>+	highest_state = l-&gt;cur_candidate_display_cfg.stage1.min_clk_index_for_latency;</div><div class='add'>+	lowest_state = 0;</div><div class='add'>+</div><div class='add'>+	while (highest_state &gt; lowest_state) {</div><div class='add'>+		cur_state = (highest_state + lowest_state) / 2;</div><div class='add'>+</div><div class='add'>+		l-&gt;mode_support_params.instance = &amp;params-&gt;dml-&gt;core_instance;</div><div class='add'>+		l-&gt;mode_support_params.display_cfg = &amp;l-&gt;cur_candidate_display_cfg;</div><div class='add'>+		l-&gt;mode_support_params.min_clk_table = &amp;params-&gt;dml-&gt;min_clk_table;</div><div class='add'>+		l-&gt;mode_support_params.min_clk_index = cur_state;</div><div class='add'>+		supported = params-&gt;dml-&gt;core_instance.mode_support(&amp;l-&gt;mode_support_params);</div><div class='add'>+</div><div class='add'>+		if (supported) {</div><div class='add'>+			l-&gt;cur_candidate_display_cfg.mode_support_result = l-&gt;mode_support_params.mode_support_result;</div><div class='add'>+			highest_state = cur_state;</div><div class='add'>+		} else {</div><div class='add'>+			lowest_state = cur_state + 1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	l-&gt;cur_candidate_display_cfg.stage1.min_clk_index_for_latency = lowest_state;</div><div class='add'>+</div><div class='add'>+	copy_display_configuration_with_meta(params-&gt;optimized_display_config, &amp;l-&gt;cur_candidate_display_cfg);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* Takes an input set of mcache boundaries and finds the appropriate setting of cache programming.</div><div class='add'>+* Returns true if a valid set of programming can be made, and false otherwise. "Valid" means</div><div class='add'>+* that the horizontal viewport does not span more than 2 cache slices.</div><div class='add'>+*</div><div class='add'>+* It optionally also can apply a constant shift to all the cache boundaries.</div><div class='add'>+*/</div><div class='add'>+static const uint32_t MCACHE_ID_UNASSIGNED = 0xF;</div><div class='add'>+static const uint32_t SPLIT_LOCATION_UNDEFINED = 0xFFFF;</div><div class='add'>+</div><div class='add'>+static bool calculate_first_second_splitting(const int *mcache_boundaries, int num_boundaries, int shift,</div><div class='add'>+	int pipe_h_vp_start, int pipe_h_vp_end, int *first_offset, int *second_offset)</div><div class='add'>+{</div><div class='add'>+	const int MAX_VP = 0xFFFFFF;</div><div class='add'>+	int left_cache_id;</div><div class='add'>+	int right_cache_id;</div><div class='add'>+	int range_start;</div><div class='add'>+	int range_end;</div><div class='add'>+	bool success = false;</div><div class='add'>+</div><div class='add'>+	if (num_boundaries &lt;= 1) {</div><div class='add'>+		if (first_offset &amp;&amp; second_offset) {</div><div class='add'>+			*first_offset = 0;</div><div class='add'>+			*second_offset = -1;</div><div class='add'>+		}</div><div class='add'>+		success = true;</div><div class='add'>+		return success;</div><div class='add'>+	} else {</div><div class='add'>+		range_start = 0;</div><div class='add'>+		for (left_cache_id = 0; left_cache_id &lt; num_boundaries; left_cache_id++) {</div><div class='add'>+			range_end = mcache_boundaries[left_cache_id] - shift - 1;</div><div class='add'>+</div><div class='add'>+			if (range_start &lt;= pipe_h_vp_start &amp;&amp; pipe_h_vp_start &lt;= range_end)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			range_start = range_end + 1;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		range_end = MAX_VP;</div><div class='add'>+		for (right_cache_id = num_boundaries - 1; right_cache_id &gt;= -1; right_cache_id--) {</div><div class='add'>+			if (right_cache_id &gt;= 0)</div><div class='add'>+				range_start = mcache_boundaries[right_cache_id] - shift;</div><div class='add'>+			else</div><div class='add'>+				range_start = 0;</div><div class='add'>+</div><div class='add'>+			if (range_start &lt;= pipe_h_vp_end &amp;&amp; pipe_h_vp_end &lt;= range_end) {</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			range_end = range_start - 1;</div><div class='add'>+		}</div><div class='add'>+		right_cache_id = (right_cache_id + 1) % num_boundaries;</div><div class='add'>+</div><div class='add'>+		if (right_cache_id == left_cache_id) {</div><div class='add'>+			if (first_offset &amp;&amp; second_offset) {</div><div class='add'>+				*first_offset = left_cache_id;</div><div class='add'>+				*second_offset = -1;</div><div class='add'>+			}</div><div class='add'>+			success = true;</div><div class='add'>+		} else if (right_cache_id == (left_cache_id + 1) % num_boundaries) {</div><div class='add'>+			if (first_offset &amp;&amp; second_offset) {</div><div class='add'>+				*first_offset = left_cache_id;</div><div class='add'>+				*second_offset = right_cache_id;</div><div class='add'>+			}</div><div class='add'>+			success = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* For a given set of pipe start/end x positions, checks to see it can support the input mcache splitting.</div><div class='add'>+* It also attempts to "optimize" by finding a shift if the default 0 shift does not work.</div><div class='add'>+*/</div><div class='add'>+static bool find_shift_for_valid_cache_id_assignment(int *mcache_boundaries, unsigned int num_boundaries,</div><div class='add'>+	int *pipe_vp_startx, int *pipe_vp_endx, unsigned int pipe_count, int shift_granularity, int *shift)</div><div class='add'>+{</div><div class='add'>+	int max_shift = 0xFFFF;</div><div class='add'>+	unsigned int pipe_index;</div><div class='add'>+	unsigned int i, slice_width;</div><div class='add'>+	bool success = false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_boundaries; i++) {</div><div class='add'>+		if (i == 0)</div><div class='add'>+			slice_width = mcache_boundaries[i];</div><div class='add'>+		else</div><div class='add'>+			slice_width = mcache_boundaries[i] - mcache_boundaries[i - 1];</div><div class='add'>+</div><div class='add'>+		if (max_shift &gt; (int)slice_width) {</div><div class='add'>+			max_shift = slice_width;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (*shift = 0; *shift &lt;= max_shift; *shift += shift_granularity) {</div><div class='add'>+		success = true;</div><div class='add'>+		for (pipe_index = 0; pipe_index &lt; pipe_count; pipe_index++) {</div><div class='add'>+			if (!calculate_first_second_splitting(mcache_boundaries, num_boundaries, *shift,</div><div class='add'>+				pipe_vp_startx[pipe_index], pipe_vp_endx[pipe_index], 0, 0)) {</div><div class='add'>+				success = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (success)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* Counts the number of elements inside input array within the given span length.</div><div class='add'>+* Formally, what is the size of the largest subset of the array where the largest and smallest element</div><div class='add'>+* differ no more than the span.</div><div class='add'>+*/</div><div class='add'>+static unsigned int count_elements_in_span(int *array, unsigned int array_size, unsigned int span)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned int span_start_value;</div><div class='add'>+	unsigned int span_start_index;</div><div class='add'>+	unsigned int greatest_element_count;</div><div class='add'>+</div><div class='add'>+	if (array_size == 0)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	if (span == 0)</div><div class='add'>+		return array_size &gt; 0 ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	span_start_value = 0;</div><div class='add'>+	span_start_index = 0;</div><div class='add'>+	greatest_element_count = 0;</div><div class='add'>+</div><div class='add'>+	while (span_start_index &lt; array_size) {</div><div class='add'>+		for (i = span_start_index; i &lt; array_size; i++) {</div><div class='add'>+			if (array[i] - span_start_value &lt;= span) {</div><div class='add'>+				if (i - span_start_index + 1 &gt; greatest_element_count) {</div><div class='add'>+					greatest_element_count = i - span_start_index + 1;</div><div class='add'>+				}</div><div class='add'>+			} else</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		span_start_index++;</div><div class='add'>+</div><div class='add'>+		if (span_start_index &lt; array_size) {</div><div class='add'>+			span_start_value = array[span_start_index - 1] + 1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return greatest_element_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool calculate_h_split_for_scaling_transform(int full_vp_width, int h_active, int num_pipes,</div><div class='add'>+	enum dml2_scaling_transform scaling_transform, int *pipe_vp_x_start, int *pipe_vp_x_end)</div><div class='add'>+{</div><div class='add'>+	int i, slice_width;</div><div class='add'>+	const char MAX_SCL_VP_OVERLAP = 3;</div><div class='add'>+	bool success = false;</div><div class='add'>+</div><div class='add'>+	switch (scaling_transform) {</div><div class='add'>+	case dml2_scaling_transform_centered:</div><div class='add'>+	case dml2_scaling_transform_aspect_ratio:</div><div class='add'>+	case dml2_scaling_transform_fullscreen:</div><div class='add'>+		slice_width = full_vp_width / num_pipes;</div><div class='add'>+		for (i = 0; i &lt; num_pipes; i++) {</div><div class='add'>+			pipe_vp_x_start[i] = i * slice_width;</div><div class='add'>+			pipe_vp_x_end[i] = (i + 1) * slice_width - 1;</div><div class='add'>+</div><div class='add'>+			if (pipe_vp_x_start[i] &lt; MAX_SCL_VP_OVERLAP)</div><div class='add'>+				pipe_vp_x_start[i] = 0;</div><div class='add'>+			else</div><div class='add'>+				pipe_vp_x_start[i] -= MAX_SCL_VP_OVERLAP;</div><div class='add'>+</div><div class='add'>+			if (pipe_vp_x_end[i] &gt; full_vp_width - MAX_SCL_VP_OVERLAP - 1)</div><div class='add'>+				pipe_vp_x_end[i] = full_vp_width - 1;</div><div class='add'>+			else</div><div class='add'>+				pipe_vp_x_end[i] += MAX_SCL_VP_OVERLAP;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case dml2_scaling_transform_explicit:</div><div class='add'>+	default:</div><div class='add'>+		success = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_top_mcache_validate_admissability(struct top_mcache_validate_admissability_in_out *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_instance *dml = (struct dml2_instance *)params-&gt;dml2_instance;</div><div class='add'>+	struct dml2_top_mcache_validate_admissability_locals *l = &amp;dml-&gt;scratch.mcache_validate_admissability_locals;</div><div class='add'>+</div><div class='add'>+	const int MAX_PIXEL_OVERLAP = 6;</div><div class='add'>+	int max_per_pipe_vp_p0 = 0;</div><div class='add'>+	int max_per_pipe_vp_p1 = 0;</div><div class='add'>+	int temp, p0shift, p1shift;</div><div class='add'>+	unsigned int plane_index = 0;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	unsigned int odm_combine_factor;</div><div class='add'>+	unsigned int mpc_combine_factor;</div><div class='add'>+	unsigned int num_dpps;</div><div class='add'>+	unsigned int num_boundaries;</div><div class='add'>+	enum dml2_scaling_transform scaling_transform;</div><div class='add'>+	const struct dml2_plane_parameters *plane;</div><div class='add'>+	const struct dml2_stream_parameters *stream;</div><div class='add'>+</div><div class='add'>+	bool p0pass = false;</div><div class='add'>+	bool p1pass = false;</div><div class='add'>+	bool all_pass = true;</div><div class='add'>+</div><div class='add'>+	for (plane_index = 0; plane_index &lt; params-&gt;display_cfg-&gt;num_planes; plane_index++) {</div><div class='add'>+		if (!params-&gt;display_cfg-&gt;plane_descriptors[plane_index].surface.dcc.enable)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		plane = &amp;params-&gt;display_cfg-&gt;plane_descriptors[plane_index];</div><div class='add'>+		stream = &amp;params-&gt;display_cfg-&gt;stream_descriptors[plane-&gt;stream_index];</div><div class='add'>+</div><div class='add'>+		num_dpps = odm_combine_factor = params-&gt;cfg_support_info-&gt;stream_support_info[plane-&gt;stream_index].odms_used;</div><div class='add'>+</div><div class='add'>+		if (odm_combine_factor == 1)</div><div class='add'>+			num_dpps = mpc_combine_factor = (unsigned int)params-&gt;cfg_support_info-&gt;plane_support_info[plane_index].dpps_used;</div><div class='add'>+		else</div><div class='add'>+			mpc_combine_factor = 1;</div><div class='add'>+</div><div class='add'>+		if (odm_combine_factor &gt; 1) {</div><div class='add'>+			max_per_pipe_vp_p0 = plane-&gt;surface.plane0.width;</div><div class='add'>+			temp = (unsigned int)math_ceil(plane-&gt;composition.scaler_info.plane0.h_ratio * stream-&gt;timing.h_active / odm_combine_factor);</div><div class='add'>+</div><div class='add'>+			if (temp &lt; max_per_pipe_vp_p0)</div><div class='add'>+				max_per_pipe_vp_p0 = temp;</div><div class='add'>+</div><div class='add'>+			max_per_pipe_vp_p1 = plane-&gt;surface.plane1.width;</div><div class='add'>+			temp = (unsigned int)math_ceil(plane-&gt;composition.scaler_info.plane1.h_ratio * stream-&gt;timing.h_active / odm_combine_factor);</div><div class='add'>+</div><div class='add'>+			if (temp &lt; max_per_pipe_vp_p1)</div><div class='add'>+				max_per_pipe_vp_p1 = temp;</div><div class='add'>+		} else {</div><div class='add'>+			max_per_pipe_vp_p0 = plane-&gt;surface.plane0.width / mpc_combine_factor;</div><div class='add'>+			max_per_pipe_vp_p1 = plane-&gt;surface.plane1.width / mpc_combine_factor;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		max_per_pipe_vp_p0 += 2 * MAX_PIXEL_OVERLAP;</div><div class='add'>+		max_per_pipe_vp_p1 += MAX_PIXEL_OVERLAP;</div><div class='add'>+</div><div class='add'>+		p0shift = 0;</div><div class='add'>+		p1shift = 0;</div><div class='add'>+</div><div class='add'>+		// The last element in the unshifted boundary array will always be the first pixel outside the</div><div class='add'>+		// plane, which means theres no mcache associated with it, so -1</div><div class='add'>+		num_boundaries = params-&gt;mcache_allocations[plane_index].num_mcaches_plane0 == 0 ? 0 : params-&gt;mcache_allocations[plane_index].num_mcaches_plane0 - 1;</div><div class='add'>+		if ((count_elements_in_span(params-&gt;mcache_allocations[plane_index].mcache_x_offsets_plane0,</div><div class='add'>+			num_boundaries, max_per_pipe_vp_p0) &lt;= 1) &amp;&amp; (num_boundaries &lt;= num_dpps)) {</div><div class='add'>+			p0pass = true;</div><div class='add'>+		}</div><div class='add'>+		num_boundaries = params-&gt;mcache_allocations[plane_index].num_mcaches_plane1 == 0 ? 0 : params-&gt;mcache_allocations[plane_index].num_mcaches_plane1 - 1;</div><div class='add'>+		if ((count_elements_in_span(params-&gt;mcache_allocations[plane_index].mcache_x_offsets_plane1,</div><div class='add'>+			num_boundaries, max_per_pipe_vp_p1) &lt;= 1) &amp;&amp; (num_boundaries &lt;= num_dpps)) {</div><div class='add'>+			p1pass = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!p0pass || !p1pass) {</div><div class='add'>+			if (odm_combine_factor &gt; 1) {</div><div class='add'>+				num_dpps = odm_combine_factor;</div><div class='add'>+				scaling_transform = plane-&gt;composition.scaling_transform;</div><div class='add'>+			} else {</div><div class='add'>+				num_dpps = mpc_combine_factor;</div><div class='add'>+				scaling_transform = dml2_scaling_transform_fullscreen;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (!p0pass) {</div><div class='add'>+				if (plane-&gt;composition.viewport.stationary) {</div><div class='add'>+					calculate_h_split_for_scaling_transform(plane-&gt;surface.plane0.width,</div><div class='add'>+						stream-&gt;timing.h_active, num_dpps, scaling_transform,</div><div class='add'>+						&amp;l-&gt;plane0.pipe_vp_startx[plane_index], &amp;l-&gt;plane0.pipe_vp_endx[plane_index]);</div><div class='add'>+					p0pass = find_shift_for_valid_cache_id_assignment(params-&gt;mcache_allocations[plane_index].mcache_x_offsets_plane0,</div><div class='add'>+						params-&gt;mcache_allocations[plane_index].num_mcaches_plane0,</div><div class='add'>+						&amp;l-&gt;plane0.pipe_vp_startx[plane_index], &amp;l-&gt;plane0.pipe_vp_endx[plane_index], num_dpps,</div><div class='add'>+						params-&gt;mcache_allocations[plane_index].shift_granularity.p0, &amp;p0shift);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			if (!p1pass) {</div><div class='add'>+				if (plane-&gt;composition.viewport.stationary) {</div><div class='add'>+					calculate_h_split_for_scaling_transform(plane-&gt;surface.plane1.width,</div><div class='add'>+						stream-&gt;timing.h_active, num_dpps, scaling_transform,</div><div class='add'>+						&amp;l-&gt;plane0.pipe_vp_startx[plane_index], &amp;l-&gt;plane0.pipe_vp_endx[plane_index]);</div><div class='add'>+					p1pass = find_shift_for_valid_cache_id_assignment(params-&gt;mcache_allocations[plane_index].mcache_x_offsets_plane1,</div><div class='add'>+						params-&gt;mcache_allocations[plane_index].num_mcaches_plane1,</div><div class='add'>+						&amp;l-&gt;plane1.pipe_vp_startx[plane_index], &amp;l-&gt;plane1.pipe_vp_endx[plane_index], num_dpps,</div><div class='add'>+						params-&gt;mcache_allocations[plane_index].shift_granularity.p1, &amp;p1shift);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p0pass &amp;&amp; p1pass) {</div><div class='add'>+			for (i = 0; i &lt; params-&gt;mcache_allocations[plane_index].num_mcaches_plane0; i++) {</div><div class='add'>+				params-&gt;mcache_allocations[plane_index].mcache_x_offsets_plane0[i] -= p0shift;</div><div class='add'>+			}</div><div class='add'>+			for (i = 0; i &lt; params-&gt;mcache_allocations[plane_index].num_mcaches_plane1; i++) {</div><div class='add'>+				params-&gt;mcache_allocations[plane_index].mcache_x_offsets_plane1[i] -= p1shift;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		params-&gt;per_plane_status[plane_index] = p0pass &amp;&amp; p1pass;</div><div class='add'>+		all_pass &amp;= p0pass &amp;&amp; p1pass;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return all_pass;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs)</div><div class='add'>+{</div><div class='add'>+	// Initialize all entries to special valid MCache ID and special valid split coordinate</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;main.p0.split_location = SPLIT_LOCATION_UNDEFINED;</div><div class='add'>+</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;mall.p0.split_location = SPLIT_LOCATION_UNDEFINED;</div><div class='add'>+</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;main.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;main.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;main.p1.split_location = SPLIT_LOCATION_UNDEFINED;</div><div class='add'>+</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;mall.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;mall.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;</div><div class='add'>+	per_plane_pipe_mcache_regs-&gt;mall.p1.split_location = SPLIT_LOCATION_UNDEFINED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_top_mcache_assign_global_mcache_ids(struct top_mcache_assign_global_mcache_ids_in_out *params)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	unsigned int j;</div><div class='add'>+	int next_unused_cache_id = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; params-&gt;num_allocations; i++) {</div><div class='add'>+		if (!params-&gt;allocations[i].valid)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; params-&gt;allocations[i].num_mcaches_plane0; j++) {</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_plane0[j] = next_unused_cache_id++;</div><div class='add'>+		}</div><div class='add'>+		for (j = 0; j &lt; params-&gt;allocations[i].num_mcaches_plane1; j++) {</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_plane1[j] = next_unused_cache_id++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// The "psuedo-last" slice is always wrapped around</div><div class='add'>+		params-&gt;allocations[i].global_mcache_ids_plane0[params-&gt;allocations[i].num_mcaches_plane0] =</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_plane0[0];</div><div class='add'>+		params-&gt;allocations[i].global_mcache_ids_plane1[params-&gt;allocations[i].num_mcaches_plane1] =</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_plane1[0];</div><div class='add'>+</div><div class='add'>+		// If we need dedicated caches for mall requesting, then we assign them here.</div><div class='add'>+		if (params-&gt;allocations[i].requires_dedicated_mall_mcache) {</div><div class='add'>+			for (j = 0; j &lt; params-&gt;allocations[i].num_mcaches_plane0; j++) {</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane0[j] = next_unused_cache_id++;</div><div class='add'>+			}</div><div class='add'>+			for (j = 0; j &lt; params-&gt;allocations[i].num_mcaches_plane1; j++) {</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane1[j] = next_unused_cache_id++;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			// The "psuedo-last" slice is always wrapped around</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_mall_plane0[params-&gt;allocations[i].num_mcaches_plane0] =</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane0[0];</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_mall_plane1[params-&gt;allocations[i].num_mcaches_plane1] =</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane1[0];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// If P0 and P1 are sharing caches, then it means the largest mcache IDs for p0 and p1 can be the same</div><div class='add'>+		// since mcache IDs are always ascending, then it means the largest mcacheID of p1 should be the</div><div class='add'>+		// largest mcacheID of P0</div><div class='add'>+		if (params-&gt;allocations[i].num_mcaches_plane0 &gt; 0 &amp;&amp; params-&gt;allocations[i].num_mcaches_plane1 &gt; 0 &amp;&amp;</div><div class='add'>+			params-&gt;allocations[i].last_slice_sharing.plane0_plane1) {</div><div class='add'>+			params-&gt;allocations[i].global_mcache_ids_plane1[params-&gt;allocations[i].num_mcaches_plane1 - 1] =</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_plane0[params-&gt;allocations[i].num_mcaches_plane0 - 1];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// If we need dedicated caches handle last slice sharing</div><div class='add'>+		if (params-&gt;allocations[i].requires_dedicated_mall_mcache) {</div><div class='add'>+			if (params-&gt;allocations[i].num_mcaches_plane0 &gt; 0 &amp;&amp; params-&gt;allocations[i].num_mcaches_plane1 &gt; 0 &amp;&amp;</div><div class='add'>+				params-&gt;allocations[i].last_slice_sharing.plane0_plane1) {</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane1[params-&gt;allocations[i].num_mcaches_plane1 - 1] =</div><div class='add'>+					params-&gt;allocations[i].global_mcache_ids_mall_plane0[params-&gt;allocations[i].num_mcaches_plane0 - 1];</div><div class='add'>+			}</div><div class='add'>+			// If mall_comb_mcache_l is set then it means that largest mcache ID for MALL p0 can be same as regular read p0</div><div class='add'>+			if (params-&gt;allocations[i].num_mcaches_plane0 &gt; 0 &amp;&amp; params-&gt;allocations[i].last_slice_sharing.mall_comb_mcache_p0) {</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane0[params-&gt;allocations[i].num_mcaches_plane0 - 1] =</div><div class='add'>+					params-&gt;allocations[i].global_mcache_ids_plane0[params-&gt;allocations[i].num_mcaches_plane0 - 1];</div><div class='add'>+			}</div><div class='add'>+			// If mall_comb_mcache_c is set then it means that largest mcache ID for MALL p1 can be same as regular</div><div class='add'>+			// read p1 (which can be same as regular read p0 if plane0_plane1 is also set)</div><div class='add'>+			if (params-&gt;allocations[i].num_mcaches_plane1 &gt; 0 &amp;&amp; params-&gt;allocations[i].last_slice_sharing.mall_comb_mcache_p1) {</div><div class='add'>+				params-&gt;allocations[i].global_mcache_ids_mall_plane1[params-&gt;allocations[i].num_mcaches_plane1 - 1] =</div><div class='add'>+					params-&gt;allocations[i].global_mcache_ids_plane1[params-&gt;allocations[i].num_mcaches_plane1 - 1];</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		// If you don't need dedicated mall mcaches, the mall mcache assignments are identical to the normal requesting</div><div class='add'>+		if (!params-&gt;allocations[i].requires_dedicated_mall_mcache) {</div><div class='add'>+			memcpy(params-&gt;allocations[i].global_mcache_ids_mall_plane0, params-&gt;allocations[i].global_mcache_ids_plane0,</div><div class='add'>+				sizeof(params-&gt;allocations[i].global_mcache_ids_mall_plane0));</div><div class='add'>+			memcpy(params-&gt;allocations[i].global_mcache_ids_mall_plane1, params-&gt;allocations[i].global_mcache_ids_plane1,</div><div class='add'>+				sizeof(params-&gt;allocations[i].global_mcache_ids_mall_plane1));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_top_mcache_calc_mcache_count_and_offsets(struct top_mcache_calc_mcache_count_and_offsets_in_out *params)</div><div class='add'>+{</div><div class='add'>+	struct dml2_instance *dml = (struct dml2_instance *)params-&gt;dml2_instance;</div><div class='add'>+	struct dml2_top_mcache_verify_mcache_size_locals *l = &amp;dml-&gt;scratch.mcache_verify_mcache_size_locals;</div><div class='add'>+</div><div class='add'>+	unsigned int total_mcaches_required;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (dml-&gt;soc_bbox.num_dcc_mcaches == 0) {</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	total_mcaches_required = 0;</div><div class='add'>+	l-&gt;calc_mcache_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+	for (i = 0; i &lt; params-&gt;display_config-&gt;num_planes; i++) {</div><div class='add'>+		if (!params-&gt;display_config-&gt;plane_descriptors[i].surface.dcc.enable) {</div><div class='add'>+			memset(&amp;params-&gt;mcache_allocations[i], 0, sizeof(struct dml2_mcache_surface_allocation));</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		l-&gt;calc_mcache_params.plane_descriptor = &amp;params-&gt;display_config-&gt;plane_descriptors[i];</div><div class='add'>+		l-&gt;calc_mcache_params.mcache_allocation = &amp;params-&gt;mcache_allocations[i];</div><div class='add'>+		l-&gt;calc_mcache_params.plane_index = i;</div><div class='add'>+</div><div class='add'>+		if (!dml-&gt;core_instance.calculate_mcache_allocation(&amp;l-&gt;calc_mcache_params)) {</div><div class='add'>+			result = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (params-&gt;mcache_allocations[i].valid) {</div><div class='add'>+			total_mcaches_required += params-&gt;mcache_allocations[i].num_mcaches_plane0 + params-&gt;mcache_allocations[i].num_mcaches_plane1;</div><div class='add'>+			if (params-&gt;mcache_allocations[i].last_slice_sharing.plane0_plane1)</div><div class='add'>+				total_mcaches_required--;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	DML_LOG_VERBOSE("DML_CORE_DCN3::%s: plane_%d, total_mcaches_required=%d\n", __func__, i, total_mcaches_required);</div><div class='add'>+</div><div class='add'>+	if (total_mcaches_required &gt; dml-&gt;soc_bbox.num_dcc_mcaches) {</div><div class='add'>+		result = false;</div><div class='add'>+	} else {</div><div class='add'>+		result = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_soc15_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_instance *dml = (struct dml2_instance *)in_out-&gt;dml2_instance;</div><div class='add'>+	struct dml2_check_mode_supported_locals *l = &amp;dml-&gt;scratch.check_mode_supported_locals;</div><div class='add'>+	struct dml2_display_cfg_programming *dpmm_programming = &amp;dml-&gt;dpmm_instance.dpmm_scratch.programming;</div><div class='add'>+</div><div class='add'>+	bool result = false;</div><div class='add'>+	bool mcache_success = false;</div><div class='add'>+	memset(dpmm_programming, 0, sizeof(struct dml2_display_cfg_programming));</div><div class='add'>+</div><div class='add'>+	setup_unoptimized_display_config_with_meta(dml, &amp;l-&gt;base_display_config_with_meta, in_out-&gt;display_config);</div><div class='add'>+</div><div class='add'>+	l-&gt;mode_support_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+	l-&gt;mode_support_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+	l-&gt;mode_support_params.min_clk_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+	l-&gt;mode_support_params.min_clk_index = l-&gt;base_display_config_with_meta.stage1.min_clk_index_for_latency;</div><div class='add'>+	result = dml-&gt;core_instance.mode_support(&amp;l-&gt;mode_support_params);</div><div class='add'>+	l-&gt;base_display_config_with_meta.mode_support_result = l-&gt;mode_support_params.mode_support_result;</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		struct optimization_phase_params mcache_phase =	{</div><div class='add'>+		.dml = dml,</div><div class='add'>+		.display_config = &amp;l-&gt;base_display_config_with_meta,</div><div class='add'>+		.test_function = dml2_top_optimization_test_function_mcache,</div><div class='add'>+		.optimize_function = dml2_top_optimization_optimize_function_mcache,</div><div class='add'>+		.optimized_display_config = &amp;l-&gt;optimized_display_config_with_meta,</div><div class='add'>+		.all_or_nothing = false,</div><div class='add'>+		};</div><div class='add'>+		mcache_success = dml2_top_optimization_perform_optimization_phase(&amp;l-&gt;optimization_phase_locals, &amp;mcache_phase);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Call DPMM to map all requirements to minimum clock state</div><div class='add'>+	*/</div><div class='add'>+	if (result) {</div><div class='add'>+		l-&gt;dppm_map_mode_params.min_clk_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+		l-&gt;dppm_map_mode_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+		l-&gt;dppm_map_mode_params.programming = dpmm_programming;</div><div class='add'>+		l-&gt;dppm_map_mode_params.soc_bb = &amp;dml-&gt;soc_bbox;</div><div class='add'>+		l-&gt;dppm_map_mode_params.ip = &amp;dml-&gt;core_instance.clean_me_up.mode_lib.ip;</div><div class='add'>+		result = dml-&gt;dpmm_instance.map_mode_to_soc_dpm(&amp;l-&gt;dppm_map_mode_params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	in_out-&gt;is_supported = mcache_success;</div><div class='add'>+	result = result &amp;&amp; in_out-&gt;is_supported;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dml2_top_soc15_build_mode_programming(struct dml2_build_mode_programming_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_instance *dml = (struct dml2_instance *)in_out-&gt;dml2_instance;</div><div class='add'>+	struct dml2_build_mode_programming_locals *l = &amp;dml-&gt;scratch.build_mode_programming_locals;</div><div class='add'>+</div><div class='add'>+	bool result = false;</div><div class='add'>+	bool mcache_success = false;</div><div class='add'>+	bool uclk_pstate_success = false;</div><div class='add'>+	bool vmin_success = false;</div><div class='add'>+	bool stutter_success = false;</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_build_mode_programming_locals));</div><div class='add'>+	memset(in_out-&gt;programming, 0, sizeof(struct dml2_display_cfg_programming));</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;in_out-&gt;programming-&gt;display_config, in_out-&gt;display_config, sizeof(struct dml2_display_cfg));</div><div class='add'>+</div><div class='add'>+	setup_speculative_display_config_with_meta(dml, &amp;l-&gt;base_display_config_with_meta, in_out-&gt;display_config);</div><div class='add'>+</div><div class='add'>+	l-&gt;mode_support_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+	l-&gt;mode_support_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+	l-&gt;mode_support_params.min_clk_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+	l-&gt;mode_support_params.min_clk_index = l-&gt;base_display_config_with_meta.stage1.min_clk_index_for_latency;</div><div class='add'>+	result = dml-&gt;core_instance.mode_support(&amp;l-&gt;mode_support_params);</div><div class='add'>+</div><div class='add'>+	l-&gt;base_display_config_with_meta.mode_support_result = l-&gt;mode_support_params.mode_support_result;</div><div class='add'>+</div><div class='add'>+	if (!result) {</div><div class='add'>+		setup_unoptimized_display_config_with_meta(dml, &amp;l-&gt;base_display_config_with_meta, in_out-&gt;display_config);</div><div class='add'>+</div><div class='add'>+		l-&gt;mode_support_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+		l-&gt;mode_support_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+		l-&gt;mode_support_params.min_clk_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+		l-&gt;mode_support_params.min_clk_index = l-&gt;base_display_config_with_meta.stage1.min_clk_index_for_latency;</div><div class='add'>+		result = dml-&gt;core_instance.mode_support(&amp;l-&gt;mode_support_params);</div><div class='add'>+		l-&gt;base_display_config_with_meta.mode_support_result = l-&gt;mode_support_params.mode_support_result;</div><div class='add'>+</div><div class='add'>+		if (!result) {</div><div class='add'>+			l-&gt;informative_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+			l-&gt;informative_params.programming = in_out-&gt;programming;</div><div class='add'>+			l-&gt;informative_params.mode_is_supported = false;</div><div class='add'>+			dml-&gt;core_instance.populate_informative(&amp;l-&gt;informative_params);</div><div class='add'>+</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		* Phase 1: Determine minimum clocks to satisfy latency requirements for this mode</div><div class='add'>+		*/</div><div class='add'>+		memset(&amp;l-&gt;min_clock_for_latency_phase, 0, sizeof(struct optimization_phase_params));</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.dml = dml;</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.display_config = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.init_function = dml2_top_optimization_init_function_min_clk_for_latency;</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.test_function = dml2_top_optimization_test_function_min_clk_for_latency;</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.optimize_function = dml2_top_optimization_optimize_function_min_clk_for_latency;</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.optimized_display_config = &amp;l-&gt;optimized_display_config_with_meta;</div><div class='add'>+		l-&gt;min_clock_for_latency_phase.all_or_nothing = false;</div><div class='add'>+</div><div class='add'>+		dml2_top_optimization_perform_optimization_phase_1(&amp;l-&gt;optimization_phase_locals, &amp;l-&gt;min_clock_for_latency_phase);</div><div class='add'>+</div><div class='add'>+		memcpy(&amp;l-&gt;base_display_config_with_meta, &amp;l-&gt;optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Phase 2: Satisfy DCC mcache requirements</div><div class='add'>+	*/</div><div class='add'>+	memset(&amp;l-&gt;mcache_phase, 0, sizeof(struct optimization_phase_params));</div><div class='add'>+	l-&gt;mcache_phase.dml = dml;</div><div class='add'>+	l-&gt;mcache_phase.display_config = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+	l-&gt;mcache_phase.test_function = dml2_top_optimization_test_function_mcache;</div><div class='add'>+	l-&gt;mcache_phase.optimize_function = dml2_top_optimization_optimize_function_mcache;</div><div class='add'>+	l-&gt;mcache_phase.optimized_display_config = &amp;l-&gt;optimized_display_config_with_meta;</div><div class='add'>+	l-&gt;mcache_phase.all_or_nothing = true;</div><div class='add'>+</div><div class='add'>+	mcache_success = dml2_top_optimization_perform_optimization_phase(&amp;l-&gt;optimization_phase_locals, &amp;l-&gt;mcache_phase);</div><div class='add'>+</div><div class='add'>+	if (!mcache_success) {</div><div class='add'>+		l-&gt;informative_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+		l-&gt;informative_params.programming = in_out-&gt;programming;</div><div class='add'>+		l-&gt;informative_params.mode_is_supported = false;</div><div class='add'>+</div><div class='add'>+		dml-&gt;core_instance.populate_informative(&amp;l-&gt;informative_params);</div><div class='add'>+</div><div class='add'>+		in_out-&gt;programming-&gt;informative.failed_mcache_validation = true;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;l-&gt;base_display_config_with_meta, &amp;l-&gt;optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Phase 3: Optimize for Pstate</div><div class='add'>+	*/</div><div class='add'>+	memset(&amp;l-&gt;uclk_pstate_phase, 0, sizeof(struct optimization_phase_params));</div><div class='add'>+	l-&gt;uclk_pstate_phase.dml = dml;</div><div class='add'>+	l-&gt;uclk_pstate_phase.display_config = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+	l-&gt;uclk_pstate_phase.init_function = dml2_top_optimization_init_function_uclk_pstate;</div><div class='add'>+	l-&gt;uclk_pstate_phase.test_function = dml2_top_optimization_test_function_uclk_pstate;</div><div class='add'>+	l-&gt;uclk_pstate_phase.optimize_function = dml2_top_optimization_optimize_function_uclk_pstate;</div><div class='add'>+	l-&gt;uclk_pstate_phase.optimized_display_config = &amp;l-&gt;optimized_display_config_with_meta;</div><div class='add'>+	l-&gt;uclk_pstate_phase.all_or_nothing = true;</div><div class='add'>+</div><div class='add'>+	uclk_pstate_success = dml2_top_optimization_perform_optimization_phase(&amp;l-&gt;optimization_phase_locals, &amp;l-&gt;uclk_pstate_phase);</div><div class='add'>+</div><div class='add'>+	if (uclk_pstate_success) {</div><div class='add'>+		memcpy(&amp;l-&gt;base_display_config_with_meta, &amp;l-&gt;optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));</div><div class='add'>+		l-&gt;base_display_config_with_meta.stage3.success = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Phase 4: Optimize for Vmin</div><div class='add'>+	*/</div><div class='add'>+	memset(&amp;l-&gt;vmin_phase, 0, sizeof(struct optimization_phase_params));</div><div class='add'>+	l-&gt;vmin_phase.dml = dml;</div><div class='add'>+	l-&gt;vmin_phase.display_config = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+	l-&gt;vmin_phase.init_function = dml2_top_optimization_init_function_vmin;</div><div class='add'>+	l-&gt;vmin_phase.test_function = dml2_top_optimization_test_function_vmin;</div><div class='add'>+	l-&gt;vmin_phase.optimize_function = dml2_top_optimization_optimize_function_vmin;</div><div class='add'>+	l-&gt;vmin_phase.optimized_display_config = &amp;l-&gt;optimized_display_config_with_meta;</div><div class='add'>+	l-&gt;vmin_phase.all_or_nothing = false;</div><div class='add'>+</div><div class='add'>+	vmin_success = dml2_top_optimization_perform_optimization_phase(&amp;l-&gt;optimization_phase_locals, &amp;l-&gt;vmin_phase);</div><div class='add'>+</div><div class='add'>+	if (l-&gt;optimized_display_config_with_meta.stage4.performed) {</div><div class='add'>+		/*</div><div class='add'>+		 * when performed is true, optimization has applied to</div><div class='add'>+		 * optimized_display_config_with_meta and it has passed mode</div><div class='add'>+		 * support. However it may or may not pass the test function to</div><div class='add'>+		 * reach actual Vmin. As long as voltage is optimized even if it</div><div class='add'>+		 * doesn't reach Vmin level, there is still power benefit so in</div><div class='add'>+		 * this case we will still copy this optimization into base</div><div class='add'>+		 * display config.</div><div class='add'>+		 */</div><div class='add'>+		memcpy(&amp;l-&gt;base_display_config_with_meta, &amp;l-&gt;optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));</div><div class='add'>+		l-&gt;base_display_config_with_meta.stage4.success = vmin_success;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Phase 5: Optimize for Stutter</div><div class='add'>+	*/</div><div class='add'>+	memset(&amp;l-&gt;stutter_phase, 0, sizeof(struct optimization_phase_params));</div><div class='add'>+	l-&gt;stutter_phase.dml = dml;</div><div class='add'>+	l-&gt;stutter_phase.display_config = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+	l-&gt;stutter_phase.init_function = dml2_top_optimization_init_function_stutter;</div><div class='add'>+	l-&gt;stutter_phase.test_function = dml2_top_optimization_test_function_stutter;</div><div class='add'>+	l-&gt;stutter_phase.optimize_function = dml2_top_optimization_optimize_function_stutter;</div><div class='add'>+	l-&gt;stutter_phase.optimized_display_config = &amp;l-&gt;optimized_display_config_with_meta;</div><div class='add'>+	l-&gt;stutter_phase.all_or_nothing = true;</div><div class='add'>+</div><div class='add'>+	stutter_success = dml2_top_optimization_perform_optimization_phase(&amp;l-&gt;optimization_phase_locals, &amp;l-&gt;stutter_phase);</div><div class='add'>+</div><div class='add'>+	if (stutter_success) {</div><div class='add'>+		memcpy(&amp;l-&gt;base_display_config_with_meta, &amp;l-&gt;optimized_display_config_with_meta, sizeof(struct display_configuation_with_meta));</div><div class='add'>+		l-&gt;base_display_config_with_meta.stage5.success = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Call DPMM to map all requirements to minimum clock state</div><div class='add'>+	*/</div><div class='add'>+	if (result) {</div><div class='add'>+		l-&gt;dppm_map_mode_params.min_clk_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+		l-&gt;dppm_map_mode_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+		l-&gt;dppm_map_mode_params.programming = in_out-&gt;programming;</div><div class='add'>+		l-&gt;dppm_map_mode_params.soc_bb = &amp;dml-&gt;soc_bbox;</div><div class='add'>+		l-&gt;dppm_map_mode_params.ip = &amp;dml-&gt;core_instance.clean_me_up.mode_lib.ip;</div><div class='add'>+		result = dml-&gt;dpmm_instance.map_mode_to_soc_dpm(&amp;l-&gt;dppm_map_mode_params);</div><div class='add'>+		if (!result)</div><div class='add'>+			in_out-&gt;programming-&gt;informative.failed_dpmm = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		l-&gt;mode_programming_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+		l-&gt;mode_programming_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+		l-&gt;mode_programming_params.cfg_support_info = &amp;l-&gt;base_display_config_with_meta.mode_support_result.cfg_support_info;</div><div class='add'>+		l-&gt;mode_programming_params.programming = in_out-&gt;programming;</div><div class='add'>+		result = dml-&gt;core_instance.mode_programming(&amp;l-&gt;mode_programming_params);</div><div class='add'>+		if (!result)</div><div class='add'>+			in_out-&gt;programming-&gt;informative.failed_mode_programming = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		l-&gt;dppm_map_watermarks_params.core = &amp;dml-&gt;core_instance;</div><div class='add'>+		l-&gt;dppm_map_watermarks_params.display_cfg = &amp;l-&gt;base_display_config_with_meta;</div><div class='add'>+		l-&gt;dppm_map_watermarks_params.programming = in_out-&gt;programming;</div><div class='add'>+		result = dml-&gt;dpmm_instance.map_watermarks(&amp;l-&gt;dppm_map_watermarks_params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	l-&gt;informative_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+	l-&gt;informative_params.programming = in_out-&gt;programming;</div><div class='add'>+	l-&gt;informative_params.mode_is_supported = result;</div><div class='add'>+</div><div class='add'>+	dml-&gt;core_instance.populate_informative(&amp;l-&gt;informative_params);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_top_soc15_build_mcache_programming(struct dml2_build_mcache_programming_in_out *params)</div><div class='add'>+{</div><div class='add'>+	bool success = true;</div><div class='add'>+	int config_index, pipe_index;</div><div class='add'>+	int first_offset, second_offset;</div><div class='add'>+	int free_per_plane_reg_index = 0;</div><div class='add'>+</div><div class='add'>+	memset(params-&gt;per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct dml2_hubp_pipe_mcache_regs *));</div><div class='add'>+</div><div class='add'>+	for (config_index = 0; config_index &lt; params-&gt;num_configurations; config_index++) {</div><div class='add'>+		for (pipe_index = 0; pipe_index &lt; params-&gt;mcache_configurations[config_index].num_pipes; pipe_index++) {</div><div class='add'>+			// Allocate storage for the mcache regs</div><div class='add'>+			params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index] = &amp;params-&gt;mcache_regs_set[free_per_plane_reg_index++];</div><div class='add'>+</div><div class='add'>+			reset_mcache_allocations(params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]);</div><div class='add'>+</div><div class='add'>+			if (params-&gt;mcache_configurations[config_index].plane_descriptor-&gt;surface.dcc.enable) {</div><div class='add'>+				// P0 always enabled</div><div class='add'>+				if (!calculate_first_second_splitting(params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;mcache_x_offsets_plane0,</div><div class='add'>+					params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;num_mcaches_plane0,</div><div class='add'>+					0,</div><div class='add'>+					params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane0.viewport_x_start,</div><div class='add'>+					params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane0.viewport_x_start +</div><div class='add'>+					params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane0.viewport_width - 1,</div><div class='add'>+					&amp;first_offset, &amp;second_offset)) {</div><div class='add'>+					success = false;</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;main.p0.mcache_id_first =</div><div class='add'>+					params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_plane0[first_offset];</div><div class='add'>+</div><div class='add'>+				params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;mall.p0.mcache_id_first =</div><div class='add'>+					params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_mall_plane0[first_offset];</div><div class='add'>+</div><div class='add'>+				if (second_offset &gt;= 0) {</div><div class='add'>+					params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;main.p0.mcache_id_second =</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_plane0[second_offset];</div><div class='add'>+					params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;main.p0.split_location =</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;mcache_x_offsets_plane0[first_offset] - 1;</div><div class='add'>+</div><div class='add'>+					params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;mall.p0.mcache_id_second =</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_mall_plane0[second_offset];</div><div class='add'>+					params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;mall.p0.split_location =</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;mcache_x_offsets_plane0[first_offset] - 1;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				// Populate P1 if enabled</div><div class='add'>+				if (params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane1_enabled) {</div><div class='add'>+					if (!calculate_first_second_splitting(params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;mcache_x_offsets_plane1,</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;num_mcaches_plane1,</div><div class='add'>+						0,</div><div class='add'>+						params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane1.viewport_x_start,</div><div class='add'>+						params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane1.viewport_x_start +</div><div class='add'>+						params-&gt;mcache_configurations[config_index].pipe_configurations[pipe_index].plane1.viewport_width - 1,</div><div class='add'>+						&amp;first_offset, &amp;second_offset)) {</div><div class='add'>+						success = false;</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+</div><div class='add'>+					params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;main.p1.mcache_id_first =</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_plane1[first_offset];</div><div class='add'>+</div><div class='add'>+					params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;mall.p1.mcache_id_first =</div><div class='add'>+						params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_mall_plane1[first_offset];</div><div class='add'>+</div><div class='add'>+					if (second_offset &gt;= 0) {</div><div class='add'>+						params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;main.p1.mcache_id_second =</div><div class='add'>+							params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_plane1[second_offset];</div><div class='add'>+						params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;main.p1.split_location =</div><div class='add'>+							params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;mcache_x_offsets_plane1[first_offset] - 1;</div><div class='add'>+</div><div class='add'>+						params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;mall.p1.mcache_id_second =</div><div class='add'>+							params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;global_mcache_ids_mall_plane1[second_offset];</div><div class='add'>+						params-&gt;per_plane_pipe_mcache_regs[config_index][pipe_index]-&gt;mall.p1.split_location =</div><div class='add'>+							params-&gt;mcache_configurations[config_index].mcache_allocation-&gt;mcache_x_offsets_plane1[first_offset] - 1;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return success;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dml2_top_funcs soc15_funcs = {</div><div class='add'>+	.check_mode_supported = dml2_top_soc15_check_mode_supported,</div><div class='add'>+	.build_mode_programming = dml2_top_soc15_build_mode_programming,</div><div class='add'>+	.build_mcache_programming = dml2_top_soc15_build_mcache_programming,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dml2_top_soc15_initialize_instance(struct dml2_initialize_instance_in_out *in_out)</div><div class='add'>+{</div><div class='add'>+	struct dml2_instance *dml = (struct dml2_instance *)in_out-&gt;dml2_instance;</div><div class='add'>+	struct dml2_initialize_instance_locals *l = &amp;dml-&gt;scratch.initialize_instance_locals;</div><div class='add'>+	struct dml2_core_initialize_in_out core_init_params = { 0 };</div><div class='add'>+	struct dml2_mcg_build_min_clock_table_params_in_out mcg_build_min_clk_params = { 0 };</div><div class='add'>+	struct dml2_pmo_initialize_in_out pmo_init_params = { 0 };</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	memset(l, 0, sizeof(struct dml2_initialize_instance_locals));</div><div class='add'>+	memset(dml, 0, sizeof(struct dml2_instance));</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;dml-&gt;ip_caps, &amp;in_out-&gt;ip_caps, sizeof(struct dml2_ip_capabilities));</div><div class='add'>+	memcpy(&amp;dml-&gt;soc_bbox, &amp;in_out-&gt;soc_bb, sizeof(struct dml2_soc_bb));</div><div class='add'>+</div><div class='add'>+	dml-&gt;project_id = in_out-&gt;options.project_id;</div><div class='add'>+	dml-&gt;pmo_options = in_out-&gt;options.pmo_options;</div><div class='add'>+</div><div class='add'>+	// Initialize All Components</div><div class='add'>+	result = dml2_mcg_create(in_out-&gt;options.project_id, &amp;dml-&gt;mcg_instance);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = dml2_dpmm_create(in_out-&gt;options.project_id, &amp;dml-&gt;dpmm_instance);</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = dml2_core_create(in_out-&gt;options.project_id, &amp;dml-&gt;core_instance);</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		mcg_build_min_clk_params.soc_bb = &amp;in_out-&gt;soc_bb;</div><div class='add'>+		mcg_build_min_clk_params.min_clk_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+		result = dml-&gt;mcg_instance.build_min_clock_table(&amp;mcg_build_min_clk_params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		core_init_params.project_id = in_out-&gt;options.project_id;</div><div class='add'>+		core_init_params.instance = &amp;dml-&gt;core_instance;</div><div class='add'>+		core_init_params.minimum_clock_table = &amp;dml-&gt;min_clk_table;</div><div class='add'>+		core_init_params.explicit_ip_bb = in_out-&gt;overrides.explicit_ip_bb;</div><div class='add'>+		core_init_params.explicit_ip_bb_size = in_out-&gt;overrides.explicit_ip_bb_size;</div><div class='add'>+		core_init_params.ip_caps = &amp;in_out-&gt;ip_caps;</div><div class='add'>+		core_init_params.soc_bb = &amp;in_out-&gt;soc_bb;</div><div class='add'>+		result = dml-&gt;core_instance.initialize(&amp;core_init_params);</div><div class='add'>+</div><div class='add'>+		if (core_init_params.explicit_ip_bb &amp;&amp; core_init_params.explicit_ip_bb_size &gt; 0) {</div><div class='add'>+			memcpy(&amp;dml-&gt;ip_caps, &amp;in_out-&gt;ip_caps, sizeof(struct dml2_ip_capabilities));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result)</div><div class='add'>+		result = dml2_pmo_create(in_out-&gt;options.project_id, &amp;dml-&gt;pmo_instance);</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		pmo_init_params.instance = &amp;dml-&gt;pmo_instance;</div><div class='add'>+		pmo_init_params.soc_bb = &amp;dml-&gt;soc_bbox;</div><div class='add'>+		pmo_init_params.ip_caps = &amp;dml-&gt;ip_caps;</div><div class='add'>+		pmo_init_params.mcg_clock_table_size = dml-&gt;min_clk_table.dram_bw_table.num_entries;</div><div class='add'>+		pmo_init_params.options = &amp;dml-&gt;pmo_options;</div><div class='add'>+		dml-&gt;pmo_instance.initialize(&amp;pmo_init_params);</div><div class='add'>+	}</div><div class='add'>+	dml-&gt;funcs = soc15_funcs;</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h<br/>new file mode 100644<br/>index 000000000000..53bd8602f9ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_TOP_SOC15_H__</div><div class='add'>+#define __DML2_TOP_SOC15_H__</div><div class='add'>+#include "dml2_internal_shared_types.h"</div><div class='add'>+bool dml2_top_soc15_initialize_instance(struct dml2_initialize_instance_in_out *in_out);</div><div class='add'>+</div><div class='add'>+bool dml2_top_mcache_calc_mcache_count_and_offsets(struct top_mcache_calc_mcache_count_and_offsets_in_out *params);</div><div class='add'>+void dml2_top_mcache_assign_global_mcache_ids(struct top_mcache_assign_global_mcache_ids_in_out *params);</div><div class='add'>+bool dml2_top_mcache_validate_admissability(struct top_mcache_validate_admissability_in_out *params);</div><div class='add'>+bool dml2_top_soc15_build_mcache_programming(struct dml2_build_mcache_programming_in_out *params);</div><div class='add'>+#endif /* __DML2_TOP_SOC15_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h<br/>new file mode 100644<br/>index 000000000000..611c80f4f1bf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h</a></div><div class='hunk'>@@ -0,0 +1,189 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_DEBUG_H__</div><div class='add'>+#define __DML2_DEBUG_H__</div><div class='add'>+</div><div class='add'>+#include "os_types.h"</div><div class='add'>+#define DML_ASSERT(condition) ASSERT(condition)</div><div class='add'>+#define DML_LOG_LEVEL_DEFAULT DML_LOG_LEVEL_WARN</div><div class='add'>+#define DML_LOG_INTERNAL(fmt, ...) dm_output_to_console(fmt, ## __VA_ARGS__)</div><div class='add'>+</div><div class='add'>+/* private helper macros */</div><div class='add'>+#define _BOOL_FORMAT(field) "%s", field ? "true" : "false"</div><div class='add'>+#define _UINT_FORMAT(field) "%u", field</div><div class='add'>+#define _INT_FORMAT(field) "%d", field</div><div class='add'>+#define _DOUBLE_FORMAT(field) "%lf", field</div><div class='add'>+#define _ELEMENT_FUNC "function"</div><div class='add'>+#define _ELEMENT_COMP_IF "component_interface"</div><div class='add'>+#define _ELEMENT_TOP_IF "top_interface"</div><div class='add'>+#define _LOG_ENTRY(element) do {		\</div><div class='add'>+	DML_LOG_INTERNAL("&lt;"element" name=\"");	\</div><div class='add'>+	DML_LOG_INTERNAL(__func__);		\</div><div class='add'>+	DML_LOG_INTERNAL("\"&gt;\n");		\</div><div class='add'>+} while (0)</div><div class='add'>+#define _LOG_EXIT(element) DML_LOG_INTERNAL("&lt;/"element"&gt;\n")</div><div class='add'>+#define _LOG_SCALAR(field, format) do {						\</div><div class='add'>+	DML_LOG_INTERNAL(#field" = "format(field));				\</div><div class='add'>+	DML_LOG_INTERNAL("\n");							\</div><div class='add'>+} while (0)</div><div class='add'>+#define _LOG_ARRAY(field, size, format) do {					\</div><div class='add'>+	DML_LOG_INTERNAL(#field " = [");					\</div><div class='add'>+	for (int _i = 0; _i &lt; (int) size; _i++) {				\</div><div class='add'>+		DML_LOG_INTERNAL(format(field[_i]));				\</div><div class='add'>+		if (_i + 1 == (int) size)					\</div><div class='add'>+			DML_LOG_INTERNAL("]\n");				\</div><div class='add'>+		else								\</div><div class='add'>+			DML_LOG_INTERNAL(", ");					\</div><div class='add'>+}} while (0)</div><div class='add'>+#define _LOG_2D_ARRAY(field, size0, size1, format) do {				\</div><div class='add'>+	DML_LOG_INTERNAL(#field" = [");						\</div><div class='add'>+	for (int _i = 0; _i &lt; (int) size0; _i++) {				\</div><div class='add'>+		DML_LOG_INTERNAL("\n\t[");					\</div><div class='add'>+		for (int _j = 0; _j &lt; (int) size1; _j++) {			\</div><div class='add'>+			DML_LOG_INTERNAL(format(field[_i][_j]));		\</div><div class='add'>+			if (_j + 1 == (int) size1)				\</div><div class='add'>+				DML_LOG_INTERNAL("]");				\</div><div class='add'>+			else							\</div><div class='add'>+				DML_LOG_INTERNAL(", ");				\</div><div class='add'>+		}								\</div><div class='add'>+		if (_i + 1 == (int) size0)					\</div><div class='add'>+			DML_LOG_INTERNAL("]\n");				\</div><div class='add'>+		else								\</div><div class='add'>+			DML_LOG_INTERNAL(", ");					\</div><div class='add'>+	}									\</div><div class='add'>+} while (0)</div><div class='add'>+#define _LOG_3D_ARRAY(field, size0, size1, size2, format) do {			\</div><div class='add'>+	DML_LOG_INTERNAL(#field" = [");						\</div><div class='add'>+	for (int _i = 0; _i &lt; (int) size0; _i++) {				\</div><div class='add'>+		DML_LOG_INTERNAL("\n\t[");					\</div><div class='add'>+		for (int _j = 0; _j &lt; (int) size1; _j++) {			\</div><div class='add'>+			DML_LOG_INTERNAL("[");					\</div><div class='add'>+			for (int _k = 0; _k &lt; (int) size2; _k++) {		\</div><div class='add'>+				DML_LOG_INTERNAL(format(field[_i][_j][_k]));	\</div><div class='add'>+				if (_k + 1 == (int) size2)			\</div><div class='add'>+					DML_LOG_INTERNAL("]");			\</div><div class='add'>+				else						\</div><div class='add'>+					DML_LOG_INTERNAL(", ");			\</div><div class='add'>+			}							\</div><div class='add'>+			if (_j + 1 == (int) size1)				\</div><div class='add'>+				DML_LOG_INTERNAL("]");				\</div><div class='add'>+			else							\</div><div class='add'>+				DML_LOG_INTERNAL(", ");				\</div><div class='add'>+		}								\</div><div class='add'>+		if (_i + 1 == (int) size0)					\</div><div class='add'>+			DML_LOG_INTERNAL("]\n");				\</div><div class='add'>+		else								\</div><div class='add'>+			DML_LOG_INTERNAL(", ");					\</div><div class='add'>+	}									\</div><div class='add'>+} while (0)</div><div class='add'>+</div><div class='add'>+/* fatal errors for unrecoverable DML states until a full reset */</div><div class='add'>+#define DML_LOG_LEVEL_FATAL 0</div><div class='add'>+/* unexpected but recoverable failures inside DML */</div><div class='add'>+#define DML_LOG_LEVEL_ERROR 1</div><div class='add'>+/* unexpected inputs or events to DML */</div><div class='add'>+#define DML_LOG_LEVEL_WARN 2</div><div class='add'>+/* high level tracing of DML interfaces */</div><div class='add'>+#define DML_LOG_LEVEL_INFO 3</div><div class='add'>+/* tracing of DML internal executions */</div><div class='add'>+#define DML_LOG_LEVEL_DEBUG 4</div><div class='add'>+/* detailed tracing of DML calculation procedure */</div><div class='add'>+#define DML_LOG_LEVEL_VERBOSE 5</div><div class='add'>+</div><div class='add'>+#ifndef DML_LOG_LEVEL</div><div class='add'>+#define DML_LOG_LEVEL DML_LOG_LEVEL_DEFAULT</div><div class='add'>+#endif /* #ifndef DML_LOG_LEVEL */</div><div class='add'>+</div><div class='add'>+/* public macros for DML_LOG_LEVEL_FATAL and up */</div><div class='add'>+#define DML_LOG_FATAL(fmt, ...) DML_LOG_INTERNAL("[DML FATAL] " fmt, ## __VA_ARGS__)</div><div class='add'>+</div><div class='add'>+/* public macros for DML_LOG_LEVEL_ERROR and up */</div><div class='add'>+#if DML_LOG_LEVEL &gt;= DML_LOG_LEVEL_ERROR</div><div class='add'>+#define DML_LOG_ERROR(fmt, ...) DML_LOG_INTERNAL("[DML ERROR] "fmt, ## __VA_ARGS__)</div><div class='add'>+#define DML_ASSERT_MSG(condition, fmt, ...)								\</div><div class='add'>+	do {												\</div><div class='add'>+		if (!(condition)) {									\</div><div class='add'>+			DML_LOG_ERROR("ASSERT hit in %s line %d\n", __func__, __LINE__);		\</div><div class='add'>+			DML_LOG_ERROR(fmt, ## __VA_ARGS__);						\</div><div class='add'>+			DML_ASSERT(condition);								\</div><div class='add'>+		}											\</div><div class='add'>+	} while (0)</div><div class='add'>+#else</div><div class='add'>+#define DML_LOG_ERROR(fmt, ...) ((void)0)</div><div class='add'>+#define DML_ASSERT_MSG(condition, fmt, ...) ((void)0)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/* public macros for DML_LOG_LEVEL_WARN and up */</div><div class='add'>+#if DML_LOG_LEVEL &gt;= DML_LOG_LEVEL_WARN</div><div class='add'>+#define DML_LOG_WARN(fmt, ...) DML_LOG_INTERNAL("[DML WARN] "fmt, ## __VA_ARGS__)</div><div class='add'>+#else</div><div class='add'>+#define DML_LOG_WARN(fmt, ...) ((void)0)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/* public macros for DML_LOG_LEVEL_INFO and up */</div><div class='add'>+#if DML_LOG_LEVEL &gt;= DML_LOG_LEVEL_INFO</div><div class='add'>+#define DML_LOG_INFO(fmt, ...) DML_LOG_INTERNAL("[DML INFO] "fmt, ## __VA_ARGS__)</div><div class='add'>+#define DML_LOG_TOP_IF_ENTER() _LOG_ENTRY(_ELEMENT_TOP_IF)</div><div class='add'>+#define DML_LOG_TOP_IF_EXIT() _LOG_EXIT(_ELEMENT_TOP_IF)</div><div class='add'>+#else</div><div class='add'>+#define DML_LOG_INFO(fmt, ...) ((void)0)</div><div class='add'>+#define DML_LOG_TOP_IF_ENTER() ((void)0)</div><div class='add'>+#define DML_LOG_TOP_IF_EXIT() ((void)0)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/* public macros for DML_LOG_LEVEL_DEBUG and up */</div><div class='add'>+#if DML_LOG_LEVEL &gt;= DML_LOG_LEVEL_DEBUG</div><div class='add'>+#define DML_LOG_DEBUG(fmt, ...) DML_LOG_INTERNAL(fmt, ## __VA_ARGS__)</div><div class='add'>+#define DML_LOG_COMP_IF_ENTER() _LOG_ENTRY(_ELEMENT_COMP_IF)</div><div class='add'>+#define DML_LOG_COMP_IF_EXIT() _LOG_EXIT(_ELEMENT_COMP_IF)</div><div class='add'>+#define DML_LOG_FUNC_ENTER() _LOG_ENTRY(_ELEMENT_FUNC)</div><div class='add'>+#define DML_LOG_FUNC_EXIT() _LOG_EXIT(_ELEMENT_FUNC)</div><div class='add'>+#define DML_LOG_DEBUG_BOOL(field) _LOG_SCALAR(field, _BOOL_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_UINT(field) _LOG_SCALAR(field, _UINT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_INT(field) _LOG_SCALAR(field, _INT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_DOUBLE(field) _LOG_SCALAR(field, _DOUBLE_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_BOOL(field, size) _LOG_ARRAY(field, size, _BOOL_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_UINT(field, size) _LOG_ARRAY(field, size, _UINT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_INT(field, size) _LOG_ARRAY(field, size, _INT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_DOUBLE(field, size) _LOG_ARRAY(field, size, _DOUBLE_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_BOOL(field, size0, size1) _LOG_2D_ARRAY(field, size0, size1, _BOOL_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_UINT(field, size0, size1) _LOG_2D_ARRAY(field, size0, size1, _UINT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_INT(field, size0, size1) _LOG_2D_ARRAY(field, size0, size1, _INT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_DOUBLE(field, size0, size1) _LOG_2D_ARRAY(field, size0, size1, _DOUBLE_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_BOOL(field, size0, size1, size2) _LOG_3D_ARRAY(field, size0, size1, size2, _BOOL_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_UINT(field, size0, size1, size2) _LOG_3D_ARRAY(field, size0, size1, size2, _UINT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_INT(field, size0, size1, size2) _LOG_3D_ARRAY(field, size0, size1, size2, _INT_FORMAT)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_DOUBLE(field, size0, size1, size2) _LOG_3D_ARRAY(field, size0, size1, size2, _DOUBLE_FORMAT)</div><div class='add'>+#else</div><div class='add'>+#define DML_LOG_DEBUG(fmt, ...) ((void)0)</div><div class='add'>+#define DML_LOG_COMP_IF_ENTER() ((void)0)</div><div class='add'>+#define DML_LOG_COMP_IF_EXIT() ((void)0)</div><div class='add'>+#define DML_LOG_FUNC_ENTER() ((void)0)</div><div class='add'>+#define DML_LOG_FUNC_EXIT() ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_BOOL(field) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_UINT(field) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_INT(field) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_DOUBLE(field) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_BOOL(field, size) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_UINT(field, size) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_INT(field, size) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_ARRAY_DOUBLE(field, size) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_BOOL(field, size0, size1) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_UINT(field, size0, size1) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_INT(field, size0, size1) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_2D_ARRAY_DOUBLE(field, size0, size1) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_BOOL(field, size0, size1, size2) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_UINT(field, size0, size1, size2) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_INT(field, size0, size1, size2) ((void)0)</div><div class='add'>+#define DML_LOG_DEBUG_3D_ARRAY_DOUBLE(field, size0, size1, size2) ((void)0)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/* public macros for DML_LOG_LEVEL_VERBOSE */</div><div class='add'>+#if DML_LOG_LEVEL &gt;= DML_LOG_LEVEL_VERBOSE</div><div class='add'>+#define DML_LOG_VERBOSE(fmt, ...) DML_LOG_INTERNAL(fmt, ## __VA_ARGS__)</div><div class='add'>+#else</div><div class='add'>+#define DML_LOG_VERBOSE(fmt, ...) ((void)0)</div><div class='add'>+#endif /* #if DML_LOG_LEVEL &gt;= DML_LOG_LEVEL_VERBOSE */</div><div class='add'>+#endif /* __DML2_DEBUG_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h<br/>new file mode 100644<br/>index 000000000000..1a6c0727cd2a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h</a></div><div class='hunk'>@@ -0,0 +1,1010 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DML2_INTERNAL_SHARED_TYPES_H__</div><div class='add'>+#define __DML2_INTERNAL_SHARED_TYPES_H__</div><div class='add'>+</div><div class='add'>+#include "dml2_external_lib_deps.h"</div><div class='add'>+#include "dml_top_types.h"</div><div class='add'>+#include "dml2_core_shared_types.h"</div><div class='add'>+/*</div><div class='add'>+* DML2 MCG Types and Interfaces</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+#define DML_MCG_MAX_CLK_TABLE_SIZE 20</div><div class='add'>+</div><div class='add'>+struct dram_bw_to_min_clk_table_entry {</div><div class='add'>+	unsigned long long pre_derate_dram_bw_kbps;</div><div class='add'>+	unsigned long min_fclk_khz;</div><div class='add'>+	unsigned long min_dcfclk_khz;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_mcg_dram_bw_to_min_clk_table {</div><div class='add'>+	struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE];</div><div class='add'>+</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_mcg_min_clock_table {</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int dispclk;</div><div class='add'>+		unsigned int dppclk;</div><div class='add'>+		unsigned int dscclk;</div><div class='add'>+		unsigned int dtbclk;</div><div class='add'>+		unsigned int phyclk;</div><div class='add'>+		unsigned int fclk;</div><div class='add'>+		unsigned int dcfclk;</div><div class='add'>+	} max_clocks_khz;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int dispclk;</div><div class='add'>+		unsigned int dppclk;</div><div class='add'>+		unsigned int dtbclk;</div><div class='add'>+	} max_ss_clocks_khz;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int dprefclk;</div><div class='add'>+		unsigned int xtalclk;</div><div class='add'>+		unsigned int pcierefclk;</div><div class='add'>+		unsigned int dchubrefclk;</div><div class='add'>+		unsigned int amclk;</div><div class='add'>+	} fixed_clocks_khz;</div><div class='add'>+</div><div class='add'>+	struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_mcg_build_min_clock_table_params_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_soc_bb *soc_bb;</div><div class='add'>+	struct {</div><div class='add'>+		bool perform_pseudo_build;</div><div class='add'>+	} clean_me_up;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_mcg_min_clock_table *min_clk_table;</div><div class='add'>+};</div><div class='add'>+struct dml2_mcg_instance {</div><div class='add'>+	bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* DML2 DPMM Types and Interfaces</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_core_ip_params *ip;</div><div class='add'>+	struct dml2_soc_bb *soc_bb;</div><div class='add'>+	struct dml2_mcg_min_clock_table *min_clk_table;</div><div class='add'>+	const struct display_configuation_with_meta *display_cfg;</div><div class='add'>+	struct {</div><div class='add'>+		bool perform_pseudo_map;</div><div class='add'>+		struct dml2_core_internal_soc_bb *soc_bb;</div><div class='add'>+	} clean_me_up;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_cfg_programming *programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dpmm_map_watermarks_params_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	const struct display_configuation_with_meta *display_cfg;</div><div class='add'>+	const struct dml2_core_instance *core;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_cfg_programming *programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dpmm_scratch {</div><div class='add'>+	struct dml2_display_cfg_programming programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_dpmm_instance {</div><div class='add'>+	bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out);</div><div class='add'>+	bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out);</div><div class='add'>+</div><div class='add'>+	struct dml2_dpmm_scratch dpmm_scratch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* DML2 Core Types and Interfaces</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+struct dml2_core_initialize_in_out {</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+	struct dml2_core_instance *instance;</div><div class='add'>+	struct dml2_soc_bb *soc_bb;</div><div class='add'>+	struct dml2_ip_capabilities *ip_caps;</div><div class='add'>+</div><div class='add'>+	struct dml2_mcg_min_clock_table *minimum_clock_table;</div><div class='add'>+</div><div class='add'>+	void *explicit_ip_bb;</div><div class='add'>+	unsigned int explicit_ip_bb_size;</div><div class='add'>+</div><div class='add'>+	// FIXME_STAGE2 can remove but dcn3 version still need this</div><div class='add'>+	struct {</div><div class='add'>+		struct soc_bounding_box_st *soc_bb;</div><div class='add'>+		struct soc_states_st *soc_states;</div><div class='add'>+	} legacy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct core_bandwidth_requirements {</div><div class='add'>+	int urgent_bandwidth_kbytes_per_sec;</div><div class='add'>+	int average_bandwidth_kbytes_per_sec;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct core_plane_support_info {</div><div class='add'>+	int dpps_used;</div><div class='add'>+	int dram_change_latency_hiding_margin_in_active;</div><div class='add'>+	int active_latency_hiding_us;</div><div class='add'>+	int mall_svp_size_requirement_ways;</div><div class='add'>+	int nominal_vblank_pstate_latency_hiding_us;</div><div class='add'>+	int vactive_det_fill_delay_us[dml2_pstate_type_count];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct core_stream_support_info {</div><div class='add'>+	unsigned int odms_used;</div><div class='add'>+	unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2)</div><div class='add'>+</div><div class='add'>+	/* FAMS2 SubVP support info */</div><div class='add'>+	unsigned int phantom_min_v_active;</div><div class='add'>+	unsigned int phantom_v_startup;</div><div class='add'>+</div><div class='add'>+	unsigned int phantom_v_active;</div><div class='add'>+	unsigned int phantom_v_total;</div><div class='add'>+	int vblank_reserved_time_us;</div><div class='add'>+	int num_dsc_slices;</div><div class='add'>+	bool dsc_enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct core_display_cfg_support_info {</div><div class='add'>+	bool is_supported;</div><div class='add'>+</div><div class='add'>+	struct core_stream_support_info stream_support_info[DML2_MAX_PLANES];</div><div class='add'>+	struct core_plane_support_info plane_support_info[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_core_internal_mode_support_info support_info;</div><div class='add'>+	} clean_me_up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_mode_support_result {</div><div class='add'>+	struct {</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long urgent_bw_sdp_kbps;</div><div class='add'>+			unsigned long average_bw_sdp_kbps;</div><div class='add'>+			unsigned long urgent_bw_dram_kbps;</div><div class='add'>+			unsigned long average_bw_dram_kbps;</div><div class='add'>+			unsigned long dcfclk_khz;</div><div class='add'>+			unsigned long fclk_khz;</div><div class='add'>+		} svp_prefetch;</div><div class='add'>+</div><div class='add'>+		struct {</div><div class='add'>+			unsigned long urgent_bw_sdp_kbps;</div><div class='add'>+			unsigned long average_bw_sdp_kbps;</div><div class='add'>+			unsigned long urgent_bw_dram_kbps;</div><div class='add'>+			unsigned long average_bw_dram_kbps;</div><div class='add'>+			unsigned long dcfclk_khz;</div><div class='add'>+			unsigned long fclk_khz;</div><div class='add'>+		} active;</div><div class='add'>+</div><div class='add'>+		unsigned int dispclk_khz;</div><div class='add'>+		unsigned int dpprefclk_khz;</div><div class='add'>+		unsigned int dtbrefclk_khz;</div><div class='add'>+		unsigned int dcfclk_deepsleep_khz;</div><div class='add'>+		unsigned int socclk_khz;</div><div class='add'>+</div><div class='add'>+		unsigned int uclk_pstate_supported;</div><div class='add'>+		unsigned int fclk_pstate_supported;</div><div class='add'>+		struct dml2_core_internal_watermarks watermarks;</div><div class='add'>+	} global;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int dscclk_khz;</div><div class='add'>+		unsigned int dtbclk_khz;</div><div class='add'>+		unsigned int phyclk_khz;</div><div class='add'>+	} per_stream[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int dppclk_khz;</div><div class='add'>+		unsigned int mall_svp_allocation_mblks;</div><div class='add'>+		unsigned int mall_full_frame_allocation_mblks;</div><div class='add'>+	} per_plane[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct core_display_cfg_support_info cfg_support_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_stage1_state {</div><div class='add'>+	bool performed;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	int min_clk_index_for_latency;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_stage2_state {</div><div class='add'>+	bool performed;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	// Whether or not each plane supports mcache</div><div class='add'>+	// The number of valid elements == display_cfg.num_planes</div><div class='add'>+	// The indexing of pstate_switch_modes matches plane_descriptors[]</div><div class='add'>+	bool per_plane_mcache_support[DML2_MAX_PLANES];</div><div class='add'>+	struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8</div><div class='add'>+#define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10</div><div class='add'>+#define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3</div><div class='add'>+</div><div class='add'>+struct dml2_implicit_svp_meta {</div><div class='add'>+	bool valid;</div><div class='add'>+	unsigned long v_active;</div><div class='add'>+	unsigned long v_total;</div><div class='add'>+	unsigned long v_front_porch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pstate_per_method_common_meta {</div><div class='add'>+	/* generic params */</div><div class='add'>+	int allow_start_otg_vline;</div><div class='add'>+	int allow_end_otg_vline;</div><div class='add'>+	/* scheduling params */</div><div class='add'>+	double allow_time_us;</div><div class='add'>+	double disallow_time_us;</div><div class='add'>+	double period_us;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pstate_meta {</div><div class='add'>+	bool valid;</div><div class='add'>+	double otg_vline_time_us;</div><div class='add'>+	int scheduling_delay_otg_vlines;</div><div class='add'>+	int vertical_interrupt_ack_delay_otg_vlines;</div><div class='add'>+	int allow_to_target_delay_otg_vlines;</div><div class='add'>+	int contention_delay_otg_vlines;</div><div class='add'>+	int min_allow_width_otg_vlines;</div><div class='add'>+	int nom_vtotal;</div><div class='add'>+	int vblank_start;</div><div class='add'>+	double nom_refresh_rate_hz;</div><div class='add'>+	double nom_frame_time_us;</div><div class='add'>+	int max_vtotal;</div><div class='add'>+	double min_refresh_rate_hz;</div><div class='add'>+	double max_frame_time_us;</div><div class='add'>+	int blackout_otg_vlines;</div><div class='add'>+	int max_allow_delay_otg_vlines;</div><div class='add'>+	double nom_vblank_time_us;</div><div class='add'>+	struct {</div><div class='add'>+		double max_vactive_det_fill_delay_us;</div><div class='add'>+		double vactive_latency_hiding_us;</div><div class='add'>+		double reserved_vblank_required_us;</div><div class='add'>+		int max_vactive_det_fill_delay_otg_vlines;</div><div class='add'>+		int reserved_blank_required_vlines;</div><div class='add'>+		struct dml2_pstate_per_method_common_meta common;</div><div class='add'>+	} method_vactive;</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_pstate_per_method_common_meta common;</div><div class='add'>+	} method_vblank;</div><div class='add'>+	struct {</div><div class='add'>+		int programming_delay_otg_vlines;</div><div class='add'>+		int df_throttle_delay_otg_vlines;</div><div class='add'>+		int prefetch_to_mall_delay_otg_vlines;</div><div class='add'>+		unsigned long phantom_vactive;</div><div class='add'>+		unsigned long phantom_vfp;</div><div class='add'>+		unsigned long phantom_vtotal;</div><div class='add'>+		struct dml2_pstate_per_method_common_meta common;</div><div class='add'>+	} method_subvp;</div><div class='add'>+	struct {</div><div class='add'>+		int programming_delay_otg_vlines;</div><div class='add'>+		int stretched_vtotal;</div><div class='add'>+		struct dml2_pstate_per_method_common_meta common;</div><div class='add'>+	} method_drr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* mask of synchronized timings by stream index */</div><div class='add'>+struct dml2_pmo_synchronized_timing_groups {</div><div class='add'>+	unsigned int num_timing_groups;</div><div class='add'>+	unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES];</div><div class='add'>+	bool group_is_drr_enabled[DML2_MAX_PLANES];</div><div class='add'>+	bool group_is_drr_active[DML2_MAX_PLANES];</div><div class='add'>+	double group_line_time_us[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_stage3_state {</div><div class='add'>+	bool performed;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	// The pstate support mode for each plane</div><div class='add'>+	// The number of valid elements == display_cfg.num_planes</div><div class='add'>+	// The indexing of pstate_switch_modes matches plane_descriptors[]</div><div class='add'>+	enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Meta-data for implicit SVP generation, indexed by stream index</div><div class='add'>+	struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	// Meta-data for FAMS2</div><div class='add'>+	bool fams2_required;</div><div class='add'>+	struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	int min_clk_index_for_latency;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_stage4_state {</div><div class='add'>+	bool performed;</div><div class='add'>+	bool success;</div><div class='add'>+	bool unoptimizable_streams[DML2_MAX_DCN_PIPES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_stage5_state {</div><div class='add'>+	bool performed;</div><div class='add'>+	bool success;</div><div class='add'>+</div><div class='add'>+	bool optimal_reserved_time_in_vblank_us;</div><div class='add'>+	bool vblank_includes_z8_optimization;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct display_configuation_with_meta {</div><div class='add'>+	struct dml2_display_cfg display_config;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_mode_support_result mode_support_result;</div><div class='add'>+</div><div class='add'>+	// Stage 1 = Min Clocks for Latency</div><div class='add'>+	struct dml2_optimization_stage1_state stage1;</div><div class='add'>+</div><div class='add'>+	// Stage 2 = MCache</div><div class='add'>+	struct dml2_optimization_stage2_state stage2;</div><div class='add'>+</div><div class='add'>+	// Stage 3 = UCLK PState</div><div class='add'>+	struct dml2_optimization_stage3_state stage3;</div><div class='add'>+</div><div class='add'>+	// Stage 4 = Vmin</div><div class='add'>+	struct dml2_optimization_stage4_state stage4;</div><div class='add'>+</div><div class='add'>+	// Stage 5 = Stutter</div><div class='add'>+	struct dml2_optimization_stage5_state stage5;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_pstate_strategy {</div><div class='add'>+	enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES];</div><div class='add'>+	bool allow_state_increase;</div><div class='add'>+};</div><div class='add'>+struct dml2_core_mode_support_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_core_instance *instance;</div><div class='add'>+	const struct display_configuation_with_meta *display_cfg;</div><div class='add'>+</div><div class='add'>+	struct dml2_mcg_min_clock_table *min_clk_table;</div><div class='add'>+	int min_clk_index;</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_core_mode_support_result mode_support_result;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		// Inputs</div><div class='add'>+		struct dml_display_cfg_st *display_cfg;</div><div class='add'>+</div><div class='add'>+		// Outputs</div><div class='add'>+		struct dml_mode_support_info_st *support_info;</div><div class='add'>+		unsigned int out_lowest_state_idx;</div><div class='add'>+		unsigned int min_fclk_khz;</div><div class='add'>+		unsigned int min_dcfclk_khz;</div><div class='add'>+		unsigned int min_dram_speed_mts;</div><div class='add'>+		unsigned int min_socclk_khz;</div><div class='add'>+		unsigned int min_dscclk_khz;</div><div class='add'>+		unsigned int min_dtbclk_khz;</div><div class='add'>+		unsigned int min_phyclk_khz;</div><div class='add'>+	} legacy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_mode_programming_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_core_instance *instance;</div><div class='add'>+	const struct display_configuation_with_meta *display_cfg;</div><div class='add'>+	const struct core_display_cfg_support_info *cfg_support_info;</div><div class='add'>+	/*</div><div class='add'>+	* Outputs (also Input the clk freq are also from programming struct)</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_cfg_programming *programming;</div><div class='add'>+</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_populate_informative_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_core_instance *instance;</div><div class='add'>+</div><div class='add'>+	// If this is set, then the mode was supported, and mode programming</div><div class='add'>+	// was successfully run.</div><div class='add'>+	// Otherwise, mode programming was not run, because mode support failed.</div><div class='add'>+	bool mode_is_supported;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_cfg_programming *programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_calculate_mcache_allocation_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_core_instance *instance;</div><div class='add'>+	const struct dml2_plane_parameters *plane_descriptor;</div><div class='add'>+	unsigned int plane_index;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_mcache_surface_allocation *mcache_allocation;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_state_inputs {</div><div class='add'>+	unsigned int dummy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_internal_state_intermediates {</div><div class='add'>+	unsigned int dummy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_mode_support_locals {</div><div class='add'>+	union {</div><div class='add'>+		struct dml2_core_calcs_mode_support_ex mode_support_ex_params;</div><div class='add'>+	};</div><div class='add'>+	struct dml2_display_cfg svp_expanded_display_cfg;</div><div class='add'>+	struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_mode_programming_locals {</div><div class='add'>+	union {</div><div class='add'>+		struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params;</div><div class='add'>+	};</div><div class='add'>+	struct dml2_display_cfg svp_expanded_display_cfg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_scratch {</div><div class='add'>+	struct dml2_core_mode_support_locals mode_support_locals;</div><div class='add'>+	struct dml2_core_mode_programming_locals mode_programming_locals;</div><div class='add'>+	int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES];</div><div class='add'>+	int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES];</div><div class='add'>+	int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES];</div><div class='add'>+	int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_core_instance {</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+	struct dml2_mcg_min_clock_table *minimum_clock_table;</div><div class='add'>+	struct dml2_core_internal_state_inputs inputs;</div><div class='add'>+	struct dml2_core_internal_state_intermediates intermediates;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_scratch scratch;</div><div class='add'>+</div><div class='add'>+	bool (*initialize)(struct dml2_core_initialize_in_out *in_out);</div><div class='add'>+	bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out);</div><div class='add'>+	bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out);</div><div class='add'>+	bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out);</div><div class='add'>+	bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out);</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_core_internal_display_mode_lib mode_lib;</div><div class='add'>+	} clean_me_up;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* DML2 PMO Types and Interfaces</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_initialize_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct dml2_soc_bb *soc_bb;</div><div class='add'>+	struct dml2_ip_capabilities *ip_caps;</div><div class='add'>+	struct dml2_pmo_options *options;</div><div class='add'>+	int mcg_clock_table_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_optimize_dcc_mcache_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	const struct dml2_display_cfg *display_config;</div><div class='add'>+	bool *dcc_mcache_supported;</div><div class='add'>+	struct core_display_cfg_support_info *cfg_support_info;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_cfg *optimized_display_cfg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_init_for_vmin_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_test_for_vmin_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	const struct display_configuation_with_meta *display_config;</div><div class='add'>+	const struct dml2_soc_vmin_clock_limits *vmin_limits;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_optimize_for_vmin_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct display_configuation_with_meta *optimized_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_init_for_pstate_support_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_test_for_pstate_support_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_optimize_for_pstate_support_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+	bool last_candidate_failed;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct display_configuation_with_meta *optimized_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_init_for_stutter_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_test_for_stutter_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_optimize_for_stutter_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_pmo_instance *instance;</div><div class='add'>+	struct display_configuation_with_meta *base_display_config;</div><div class='add'>+	bool last_candidate_failed;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct display_configuation_with_meta *optimized_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define PMO_NO_DRR_STRATEGY_MASK (((1 &lt;&lt; (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) &lt;&lt; dml2_pstate_method_na)</div><div class='add'>+#define PMO_DRR_STRATEGY_MASK (((1 &lt;&lt; (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) - 1) &lt;&lt; dml2_pstate_method_fw_vactive_drr)</div><div class='add'>+#define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 &lt;&lt; (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) - 1) &lt;&lt; dml2_pstate_method_fw_vactive_drr)</div><div class='add'>+#define PMO_DRR_VAR_STRATEGY_MASK (((1 &lt;&lt; (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) &lt;&lt; dml2_pstate_method_fw_drr)</div><div class='add'>+#define PMO_FW_STRATEGY_MASK (((1 &lt;&lt; (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) &lt;&lt; dml2_pstate_method_fw_svp)</div><div class='add'>+</div><div class='add'>+#define PMO_DCN4_MAX_DISPLAYS 4</div><div class='add'>+#define PMO_DCN4_MAX_NUM_VARIANTS 2</div><div class='add'>+#define PMO_DCN4_MAX_BASE_STRATEGIES 10</div><div class='add'>+</div><div class='add'>+struct dml2_scheduling_check_locals {</div><div class='add'>+	struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES];</div><div class='add'>+	unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_scratch {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS];</div><div class='add'>+			int reserved_time_candidates_count[DML2_MAX_PLANES];</div><div class='add'>+			int current_candidate[DML2_MAX_PLANES];</div><div class='add'>+			int min_latency_index;</div><div class='add'>+			int max_latency_index;</div><div class='add'>+			int cur_latency_index;</div><div class='add'>+			int stream_mask;</div><div class='add'>+		} pmo_dcn3;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_pstate_strategy expanded_override_strategy_list[2 * 2 * 2 * 2];</div><div class='add'>+			unsigned int num_expanded_override_strategies;</div><div class='add'>+			struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE];</div><div class='add'>+			int num_pstate_candidates;</div><div class='add'>+			int cur_pstate_candidate;</div><div class='add'>+</div><div class='add'>+			unsigned int stream_plane_mask[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+			unsigned int stream_vactive_capability_mask;</div><div class='add'>+</div><div class='add'>+			int min_latency_index;</div><div class='add'>+			int max_latency_index;</div><div class='add'>+			int cur_latency_index;</div><div class='add'>+</div><div class='add'>+			// Stores all the implicit SVP meta information indexed by stream index of the display</div><div class='add'>+			// configuration under inspection, built at optimization stage init</div><div class='add'>+			struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES];</div><div class='add'>+			struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+			unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE];</div><div class='add'>+			unsigned int num_stutter_candidates;</div><div class='add'>+			unsigned int cur_stutter_candidate;</div><div class='add'>+			bool z8_vblank_optimizable;</div><div class='add'>+</div><div class='add'>+			/* mask of synchronized timings by stream index */</div><div class='add'>+			unsigned int num_timing_groups;</div><div class='add'>+			unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES];</div><div class='add'>+			bool group_is_drr_enabled[DML2_MAX_PLANES];</div><div class='add'>+			bool group_is_drr_active[DML2_MAX_PLANES];</div><div class='add'>+			double group_line_time_us[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+			/* scheduling check locals */</div><div class='add'>+			struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES];</div><div class='add'>+			unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES];</div><div class='add'>+			double group_phase_offset[DML2_MAX_PLANES];</div><div class='add'>+		} pmo_dcn4;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_init_data {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			/* populated once during initialization */</div><div class='add'>+			struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2];</div><div class='add'>+			struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4];</div><div class='add'>+			struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6];</div><div class='add'>+			struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8];</div><div class='add'>+			unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS];</div><div class='add'>+		} pmo_dcn4;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pmo_instance {</div><div class='add'>+	struct dml2_soc_bb *soc_bb;</div><div class='add'>+	struct dml2_ip_capabilities *ip_caps;</div><div class='add'>+</div><div class='add'>+	struct dml2_pmo_options *options;</div><div class='add'>+</div><div class='add'>+	int disp_clk_vmin_threshold;</div><div class='add'>+	int mpc_combine_limit;</div><div class='add'>+	int odm_combine_limit;</div><div class='add'>+	int mcg_clock_table_size;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			struct {</div><div class='add'>+				int prefetch_end_to_mall_start_us;</div><div class='add'>+				int fw_processing_delay_us;</div><div class='add'>+				int refresh_rate_limit_min;</div><div class='add'>+				int refresh_rate_limit_max;</div><div class='add'>+			} subvp;</div><div class='add'>+		} v1;</div><div class='add'>+		struct {</div><div class='add'>+			struct {</div><div class='add'>+				int refresh_rate_limit_min;</div><div class='add'>+				int refresh_rate_limit_max;</div><div class='add'>+			} subvp;</div><div class='add'>+			struct {</div><div class='add'>+				int refresh_rate_limit_min;</div><div class='add'>+				int refresh_rate_limit_max;</div><div class='add'>+			} drr;</div><div class='add'>+		} v2;</div><div class='add'>+	} fams_params;</div><div class='add'>+</div><div class='add'>+	bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out);</div><div class='add'>+	bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out);</div><div class='add'>+</div><div class='add'>+	bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out);</div><div class='add'>+	bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out);</div><div class='add'>+	bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out);</div><div class='add'>+</div><div class='add'>+	bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out);</div><div class='add'>+	bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out);</div><div class='add'>+	bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out);</div><div class='add'>+</div><div class='add'>+	bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out);</div><div class='add'>+	bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out);</div><div class='add'>+	bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out);</div><div class='add'>+</div><div class='add'>+	struct dml2_pmo_init_data init_data;</div><div class='add'>+	struct dml2_pmo_scratch scratch;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* DML2 MCache Types</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+struct top_mcache_validate_admissability_in_out {</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+</div><div class='add'>+	const struct dml2_display_cfg *display_cfg;</div><div class='add'>+	const struct core_display_cfg_support_info *cfg_support_info;</div><div class='add'>+	struct dml2_mcache_surface_allocation *mcache_allocations;</div><div class='add'>+</div><div class='add'>+	bool per_plane_status[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		const struct dml_mode_support_info_st *mode_support_info;</div><div class='add'>+	} legacy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct top_mcache_assign_ids_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Input</div><div class='add'>+	*/</div><div class='add'>+	const struct dml2_mcache_surface_allocation *mcache_allocations;</div><div class='add'>+	int plane_count;</div><div class='add'>+</div><div class='add'>+	int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];</div><div class='add'>+	int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];</div><div class='add'>+	int pipe_count_per_plane[DML2_MAX_PLANES];</div><div class='add'>+</div><div class='add'>+	struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Output</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp</div><div class='add'>+	struct dml2_build_mcache_programming_in_out *mcache_programming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct top_mcache_calc_mcache_count_and_offsets_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_instance *dml2_instance;</div><div class='add'>+	const struct dml2_display_cfg *display_config;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	* Outputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_mcache_surface_allocation *mcache_allocations;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct top_mcache_assign_global_mcache_ids_in_out {</div><div class='add'>+	/*</div><div class='add'>+	* Inputs/Outputs</div><div class='add'>+	*/</div><div class='add'>+	struct dml2_mcache_surface_allocation *allocations;</div><div class='add'>+	int num_allocations;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+* DML2 Top Types</div><div class='add'>+*/</div><div class='add'>+</div><div class='add'>+struct dml2_initialize_instance_locals {</div><div class='add'>+	int dummy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_init_function_locals {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_init_for_pstate_support_in_out init_params;</div><div class='add'>+		} uclk_pstate;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_init_for_stutter_in_out stutter_params;</div><div class='add'>+		} stutter;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_init_for_vmin_in_out init_params;</div><div class='add'>+		} vmin;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_test_function_locals {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params;</div><div class='add'>+			struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params;</div><div class='add'>+			struct top_mcache_validate_admissability_in_out validate_admissibility_params;</div><div class='add'>+		} test_mcache;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params;</div><div class='add'>+		} test_vmin;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_test_for_pstate_support_in_out test_params;</div><div class='add'>+		} uclk_pstate;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_test_for_stutter_in_out stutter_params;</div><div class='add'>+		} stutter;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_optimize_function_locals {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params;</div><div class='add'>+		} optimize_mcache;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params;</div><div class='add'>+		} optimize_vmin;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params;</div><div class='add'>+		} uclk_pstate;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_pmo_optimize_for_stutter_in_out stutter_params;</div><div class='add'>+		} stutter;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_optimization_phase_locals {</div><div class='add'>+	struct display_configuation_with_meta cur_candidate_display_cfg;</div><div class='add'>+	struct display_configuation_with_meta next_candidate_display_cfg;</div><div class='add'>+	struct dml2_core_mode_support_in_out mode_support_params;</div><div class='add'>+	struct dml2_optimization_init_function_locals init_function_locals;</div><div class='add'>+	struct dml2_optimization_test_function_locals test_function_locals;</div><div class='add'>+	struct dml2_optimization_optimize_function_locals optimize_function_locals;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_check_mode_supported_locals {</div><div class='add'>+	struct dml2_display_cfg display_cfg_working_copy;</div><div class='add'>+	struct dml2_core_mode_support_in_out mode_support_params;</div><div class='add'>+	struct dml2_optimization_phase_locals optimization_phase_locals;</div><div class='add'>+	struct display_configuation_with_meta base_display_config_with_meta;</div><div class='add'>+	struct display_configuation_with_meta optimized_display_config_with_meta;</div><div class='add'>+	struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct optimization_init_function_params {</div><div class='add'>+	struct dml2_optimization_init_function_locals *locals;</div><div class='add'>+	struct dml2_instance *dml;</div><div class='add'>+	struct display_configuation_with_meta *display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct optimization_test_function_params {</div><div class='add'>+	struct dml2_optimization_test_function_locals *locals;</div><div class='add'>+	struct dml2_instance *dml;</div><div class='add'>+	struct display_configuation_with_meta *display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct optimization_optimize_function_params {</div><div class='add'>+	bool last_candidate_supported;</div><div class='add'>+	struct dml2_optimization_optimize_function_locals *locals;</div><div class='add'>+	struct dml2_instance *dml;</div><div class='add'>+	struct display_configuation_with_meta *display_config;</div><div class='add'>+	struct display_configuation_with_meta *optimized_display_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct optimization_phase_params {</div><div class='add'>+	struct dml2_instance *dml;</div><div class='add'>+	const struct display_configuation_with_meta *display_config; // Initial Display Configuration</div><div class='add'>+	bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete</div><div class='add'>+	bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete</div><div class='add'>+	bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration</div><div class='add'>+	struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration</div><div class='add'>+</div><div class='add'>+	bool all_or_nothing;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_build_mode_programming_locals {</div><div class='add'>+	struct dml2_core_mode_support_in_out mode_support_params;</div><div class='add'>+	struct dml2_core_mode_programming_in_out mode_programming_params;</div><div class='add'>+	struct dml2_core_populate_informative_in_out informative_params;</div><div class='add'>+	struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params;</div><div class='add'>+	struct display_configuation_with_meta base_display_config_with_meta;</div><div class='add'>+	struct display_configuation_with_meta optimized_display_config_with_meta;</div><div class='add'>+	struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params;</div><div class='add'>+	struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params;</div><div class='add'>+	struct dml2_optimization_phase_locals optimization_phase_locals;</div><div class='add'>+	struct optimization_phase_params min_clock_for_latency_phase;</div><div class='add'>+	struct optimization_phase_params mcache_phase;</div><div class='add'>+	struct optimization_phase_params uclk_pstate_phase;</div><div class='add'>+	struct optimization_phase_params vmin_phase;</div><div class='add'>+	struct optimization_phase_params stutter_phase;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_legacy_core_build_mode_programming_wrapper_locals {</div><div class='add'>+	struct dml2_core_mode_support_in_out mode_support_params;</div><div class='add'>+	struct dml2_core_mode_programming_in_out mode_programming_params;</div><div class='add'>+	struct dml2_core_populate_informative_in_out informative_params;</div><div class='add'>+	struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params;</div><div class='add'>+	struct top_mcache_validate_admissability_in_out validate_admissibility_params;</div><div class='add'>+	struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];</div><div class='add'>+	struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params;</div><div class='add'>+	struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params;</div><div class='add'>+	struct dml2_display_cfg optimized_display_cfg;</div><div class='add'>+	struct core_display_cfg_support_info core_support_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_top_mcache_verify_mcache_size_locals {</div><div class='add'>+	struct dml2_calculate_mcache_allocation_in_out calc_mcache_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_top_mcache_validate_admissability_locals {</div><div class='add'>+	struct {</div><div class='add'>+		int pipe_vp_startx[DML2_MAX_DCN_PIPES];</div><div class='add'>+		int pipe_vp_endx[DML2_MAX_DCN_PIPES];</div><div class='add'>+	} plane0;</div><div class='add'>+	struct {</div><div class='add'>+		int pipe_vp_startx[DML2_MAX_DCN_PIPES];</div><div class='add'>+		int pipe_vp_endx[DML2_MAX_DCN_PIPES];</div><div class='add'>+	} plane1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_top_display_cfg_support_info {</div><div class='add'>+	const struct dml2_display_cfg *display_config;</div><div class='add'>+	struct core_display_cfg_support_info core_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_top_funcs {</div><div class='add'>+	bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out);</div><div class='add'>+	bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out);</div><div class='add'>+	bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_instance {</div><div class='add'>+	enum dml2_project_id project_id;</div><div class='add'>+</div><div class='add'>+	struct dml2_core_instance core_instance;</div><div class='add'>+	struct dml2_mcg_instance mcg_instance;</div><div class='add'>+	struct dml2_dpmm_instance dpmm_instance;</div><div class='add'>+	struct dml2_pmo_instance pmo_instance;</div><div class='add'>+</div><div class='add'>+	struct dml2_soc_bb soc_bbox;</div><div class='add'>+	struct dml2_ip_capabilities ip_caps;</div><div class='add'>+</div><div class='add'>+	struct dml2_mcg_min_clock_table min_clk_table;</div><div class='add'>+	struct dml2_pmo_options pmo_options;</div><div class='add'>+	struct dml2_top_funcs funcs;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_initialize_instance_locals initialize_instance_locals;</div><div class='add'>+		struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals;</div><div class='add'>+		struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals;</div><div class='add'>+		struct dml2_check_mode_supported_locals check_mode_supported_locals;</div><div class='add'>+		struct dml2_build_mode_programming_locals build_mode_programming_locals;</div><div class='add'>+	} scratch;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct {</div><div class='add'>+			struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals;</div><div class='add'>+		} scratch;</div><div class='add'>+	} legacy;</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c<br/>index a52c594e1ba4..4cfe64aa8492 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c</a></div><div class='hunk'>@@ -68,7 +68,7 @@ static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state</div><div class='ctx'> 		if (state-&gt;streams[i]-&gt;stream_id == stream_id) {</div><div class='ctx'> 			for (j = 0; j &lt; state-&gt;stream_status[i].plane_count; j++) {</div><div class='ctx'> 				if (state-&gt;stream_status[i].plane_states[j] == plane &amp;&amp;</div><div class='del'>-					(!is_plane_duplicate || (is_plane_duplicate &amp;&amp; (j == plane_index)))) {</div><div class='add'>+					(!is_plane_duplicate || (j == plane_index))) {</div><div class='ctx'> 					*plane_id = (i &lt;&lt; 16) | j;</div><div class='ctx'> 					return true;</div><div class='ctx'> 				}</div><div class='hunk'>@@ -88,7 +88,8 @@ static int find_disp_cfg_idx_by_plane_id(struct dml2_dml_to_dc_pipe_mapping *map</div><div class='ctx'> 			return  i;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return -1;</div><div class='add'>+	ASSERT(false);</div><div class='add'>+	return __DML2_WRAPPER_MAX_STREAMS_PLANES__;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int find_disp_cfg_idx_by_stream_id(struct dml2_dml_to_dc_pipe_mapping *mapping, unsigned int stream_id)</div><div class='hunk'>@@ -100,7 +101,8 @@ static int find_disp_cfg_idx_by_stream_id(struct dml2_dml_to_dc_pipe_mapping *ma</div><div class='ctx'> 			return  i;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return -1;</div><div class='add'>+	ASSERT(false);</div><div class='add'>+	return __DML2_WRAPPER_MAX_STREAMS_PLANES__;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> // The master pipe of a stream is defined as the top pipe in odm slice 0</div><div class='hunk'>@@ -256,12 +258,25 @@ static unsigned int find_preferred_pipe_candidates(const struct dc_state *existi</div><div class='ctx'> 	 * However this condition comes with a caveat. We need to ignore pipes that will</div><div class='ctx'> 	 * require a change in OPP but still have the same stream id. For example during</div><div class='ctx'> 	 * an MPC to ODM transiton.</div><div class='add'>+	 *</div><div class='add'>+	 * Adding check to avoid pipe select on the head pipe by utilizing dc resource</div><div class='add'>+	 * helper function resource_get_primary_dpp_pipe and comparing the pipe index.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (existing_state) {</div><div class='ctx'> 		for (i = 0; i &lt; pipe_count; i++) {</div><div class='ctx'> 			if (existing_state-&gt;res_ctx.pipe_ctx[i].stream &amp;&amp; existing_state-&gt;res_ctx.pipe_ctx[i].stream-&gt;stream_id == stream_id) {</div><div class='add'>+				struct pipe_ctx *head_pipe =</div><div class='add'>+					resource_is_pipe_type(&amp;existing_state-&gt;res_ctx.pipe_ctx[i], DPP_PIPE) ?</div><div class='add'>+						resource_get_primary_dpp_pipe(&amp;existing_state-&gt;res_ctx.pipe_ctx[i]) :</div><div class='add'>+							NULL;</div><div class='add'>+</div><div class='add'>+				// we should always respect the head pipe from selection</div><div class='add'>+				if (head_pipe &amp;&amp; head_pipe-&gt;pipe_idx == i)</div><div class='add'>+					continue;</div><div class='ctx'> 				if (existing_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp &amp;&amp;</div><div class='del'>-					existing_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;opp_id != i)</div><div class='add'>+					existing_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;opp_id != i &amp;&amp;</div><div class='add'>+						(existing_state-&gt;res_ctx.pipe_ctx[i].prev_odm_pipe ||</div><div class='add'>+						existing_state-&gt;res_ctx.pipe_ctx[i].next_odm_pipe))</div><div class='ctx'> 					continue;</div><div class='ctx'> </div><div class='ctx'> 				preferred_pipe_candidates[num_preferred_candidates++] = i;</div><div class='hunk'>@@ -290,6 +305,14 @@ static unsigned int find_last_resort_pipe_candidates(const struct dc_state *exis</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (existing_state) {</div><div class='ctx'> 		for (i  = 0; i &lt; pipe_count; i++) {</div><div class='add'>+			struct pipe_ctx *head_pipe =</div><div class='add'>+				resource_is_pipe_type(&amp;existing_state-&gt;res_ctx.pipe_ctx[i], DPP_PIPE) ?</div><div class='add'>+					resource_get_primary_dpp_pipe(&amp;existing_state-&gt;res_ctx.pipe_ctx[i]) :</div><div class='add'>+						NULL;</div><div class='add'>+</div><div class='add'>+			// we should always respect the head pipe from selection</div><div class='add'>+			if (head_pipe &amp;&amp; head_pipe-&gt;pipe_idx == i)</div><div class='add'>+				continue;</div><div class='ctx'> 			if ((existing_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp &amp;&amp;</div><div class='ctx'> 				existing_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;opp_id != i) ||</div><div class='ctx'> 				existing_state-&gt;res_ctx.pipe_ctx[i].stream_res.tg)</div><div class='hunk'>@@ -450,7 +473,6 @@ static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes)</div><div class='ctx'> {</div><div class='ctx'> 	bool sorted, swapped;</div><div class='ctx'> 	unsigned int cur_index;</div><div class='del'>-	unsigned int temp;</div><div class='ctx'> 	int odm_slice_index;</div><div class='ctx'> </div><div class='ctx'> 	for (odm_slice_index = 0; odm_slice_index &lt; pipes-&gt;num_pipes_assigned_to_plane_for_odm_combine; odm_slice_index++) {</div><div class='hunk'>@@ -466,9 +488,8 @@ static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes)</div><div class='ctx'> 		swapped = false;</div><div class='ctx'> 		while (!sorted) {</div><div class='ctx'> 			if (pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index] &gt; pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index + 1]) {</div><div class='del'>-				temp = pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index];</div><div class='del'>-				pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index] = pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index + 1];</div><div class='del'>-				pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index + 1] = temp;</div><div class='add'>+				swap(pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index + 1],</div><div class='add'>+					 pipes-&gt;pipes_assigned_to_plane[odm_slice_index][cur_index]);</div><div class='ctx'> </div><div class='ctx'> 				swapped = true;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -509,26 +530,6 @@ static void calculate_odm_slices(const struct dc_stream_state *stream, unsigned</div><div class='ctx'> 	odm_slice_end_x[odm_factor - 1] = stream-&gt;src.width - 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool is_plane_in_odm_slice(const struct dc_plane_state *plane, unsigned int slice_index, unsigned int *odm_slice_end_x, unsigned int num_slices)</div><div class='del'>-{</div><div class='del'>-	unsigned int slice_start_x, slice_end_x;</div><div class='del'>-</div><div class='del'>-	if (slice_index == 0)</div><div class='del'>-		slice_start_x = 0;</div><div class='del'>-	else</div><div class='del'>-		slice_start_x = odm_slice_end_x[slice_index - 1] + 1;</div><div class='del'>-</div><div class='del'>-	slice_end_x = odm_slice_end_x[slice_index];</div><div class='del'>-</div><div class='del'>-	if (plane-&gt;clip_rect.x + plane-&gt;clip_rect.width &lt; slice_start_x)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	if (plane-&gt;clip_rect.x &gt; slice_end_x)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void add_odm_slice_to_odm_tree(struct dml2_context *ctx,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct dc_pipe_mapping_scratch *scratch,</div><div class='hunk'>@@ -705,8 +706,8 @@ static void free_unused_pipes_for_plane(struct dml2_context *ctx, struct dc_stat</div><div class='ctx'> 	for (i = 0; i &lt; ctx-&gt;config.dcn_pipe_count; i++) {</div><div class='ctx'> 		if (state-&gt;res_ctx.pipe_ctx[i].plane_state == plane &amp;&amp;</div><div class='ctx'> 			state-&gt;res_ctx.pipe_ctx[i].stream-&gt;stream_id == stream_id &amp;&amp;</div><div class='del'>-			(!is_plane_duplicate || (is_plane_duplicate &amp;&amp;</div><div class='del'>-			ctx-&gt;v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state-&gt;res_ctx.pipe_ctx[i].pipe_idx] == plane_index)) &amp;&amp;</div><div class='add'>+			(!is_plane_duplicate ||</div><div class='add'>+			ctx-&gt;v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state-&gt;res_ctx.pipe_ctx[i].pipe_idx] == plane_index) &amp;&amp;</div><div class='ctx'> 			!is_pipe_used(pool, state-&gt;res_ctx.pipe_ctx[i].pipe_idx)) {</div><div class='ctx'> 			free_pipe(&amp;state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -768,12 +769,6 @@ static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state</div><div class='ctx'> 	sort_pipes_for_splitting(&amp;scratch-&gt;pipe_pool);</div><div class='ctx'> </div><div class='ctx'> 	for (odm_slice_index = 0; odm_slice_index &lt; scratch-&gt;odm_info.odm_factor; odm_slice_index++) {</div><div class='del'>-		// We build the tree for one ODM slice at a time.</div><div class='del'>-		// Each ODM slice shares a common OPP</div><div class='del'>-		if (!is_plane_in_odm_slice(plane, odm_slice_index, scratch-&gt;odm_info.odm_slice_end_x, scratch-&gt;odm_info.odm_factor)) {</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 		// Now we have a list of all pipes to be used for this plane/stream, now setup the tree.</div><div class='ctx'> 		scratch-&gt;odm_info.next_higher_pipe_for_odm_slice[odm_slice_index] = add_plane_to_blend_tree(ctx, state,</div><div class='ctx'> 				plane,</div><div class='hunk'>@@ -793,8 +788,8 @@ static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state</div><div class='ctx'> 	free_unused_pipes_for_plane(ctx, state, plane, &amp;scratch-&gt;pipe_pool, stream-&gt;stream_id, plane_index);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned int get_mpc_factor(struct dml2_context *ctx,</div><div class='del'>-		const struct dc_state *state,</div><div class='add'>+static unsigned int get_target_mpc_factor(struct dml2_context *ctx,</div><div class='add'>+		struct dc_state *state,</div><div class='ctx'> 		const struct dml_display_cfg_st *disp_cfg,</div><div class='ctx'> 		struct dml2_dml_to_dc_pipe_mapping *mapping,</div><div class='ctx'> 		const struct dc_stream_status *status,</div><div class='hunk'>@@ -805,11 +800,39 @@ static unsigned int get_mpc_factor(struct dml2_context *ctx,</div><div class='ctx'> 	unsigned int cfg_idx;</div><div class='ctx'> 	unsigned int mpc_factor;</div><div class='ctx'> </div><div class='del'>-	get_plane_id(ctx, state, status-&gt;plane_states[plane_idx],</div><div class='del'>-			stream-&gt;stream_id, plane_idx, &amp;plane_id);</div><div class='del'>-	cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);</div><div class='ctx'> 	if (ctx-&gt;architecture == dml2_architecture_20) {</div><div class='add'>+		get_plane_id(ctx, state, status-&gt;plane_states[plane_idx],</div><div class='add'>+				stream-&gt;stream_id, plane_idx, &amp;plane_id);</div><div class='add'>+		cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);</div><div class='ctx'> 		mpc_factor = (unsigned int)disp_cfg-&gt;hw.DPPPerSurface[cfg_idx];</div><div class='add'>+	} else if (ctx-&gt;architecture == dml2_architecture_21) {</div><div class='add'>+		if (ctx-&gt;config.svp_pstate.callbacks.get_stream_subvp_type(state, stream) == SUBVP_PHANTOM) {</div><div class='add'>+			struct dc_stream_state *main_stream;</div><div class='add'>+			struct dc_stream_status *main_stream_status;</div><div class='add'>+</div><div class='add'>+			/* get stream id of main stream */</div><div class='add'>+			main_stream = ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(state, stream);</div><div class='add'>+			if (!main_stream) {</div><div class='add'>+				ASSERT(false);</div><div class='add'>+				return 1;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			main_stream_status = ctx-&gt;config.callbacks.get_stream_status(state, main_stream);</div><div class='add'>+			if (!main_stream_status) {</div><div class='add'>+				ASSERT(false);</div><div class='add'>+				return 1;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* get plane id for associated main plane */</div><div class='add'>+			get_plane_id(ctx, state, main_stream_status-&gt;plane_states[plane_idx],</div><div class='add'>+					main_stream-&gt;stream_id, plane_idx, &amp;plane_id);</div><div class='add'>+		} else {</div><div class='add'>+			get_plane_id(ctx, state, status-&gt;plane_states[plane_idx],</div><div class='add'>+					stream-&gt;stream_id, plane_idx, &amp;plane_id);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);</div><div class='add'>+		mpc_factor = ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[cfg_idx].num_dpps_required;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		mpc_factor = 1;</div><div class='ctx'> 		ASSERT(false);</div><div class='hunk'>@@ -822,16 +845,18 @@ static unsigned int get_mpc_factor(struct dml2_context *ctx,</div><div class='ctx'> 	return mpc_factor;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned int get_odm_factor(</div><div class='add'>+static unsigned int get_target_odm_factor(</div><div class='ctx'> 		const struct dml2_context *ctx,</div><div class='add'>+		struct dc_state *state,</div><div class='ctx'> 		const struct dml_display_cfg_st *disp_cfg,</div><div class='ctx'> 		struct dml2_dml_to_dc_pipe_mapping *mapping,</div><div class='ctx'> 		const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='del'>-	unsigned int cfg_idx = find_disp_cfg_idx_by_stream_id(</div><div class='del'>-			mapping, stream-&gt;stream_id);</div><div class='add'>+	unsigned int cfg_idx;</div><div class='ctx'> </div><div class='del'>-	if (ctx-&gt;architecture == dml2_architecture_20)</div><div class='add'>+	if (ctx-&gt;architecture == dml2_architecture_20) {</div><div class='add'>+		cfg_idx = find_disp_cfg_idx_by_stream_id(</div><div class='add'>+				mapping, stream-&gt;stream_id);</div><div class='ctx'> 		switch (disp_cfg-&gt;hw.ODMMode[cfg_idx]) {</div><div class='ctx'> 		case dml_odm_mode_bypass:</div><div class='ctx'> 			return 1;</div><div class='hunk'>@@ -842,83 +867,145 @@ static unsigned int get_odm_factor(</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='add'>+	} else if (ctx-&gt;architecture == dml2_architecture_21) {</div><div class='add'>+		if (ctx-&gt;config.svp_pstate.callbacks.get_stream_subvp_type(state, stream) == SUBVP_PHANTOM) {</div><div class='add'>+			struct dc_stream_state *main_stream;</div><div class='add'>+</div><div class='add'>+			/* get stream id of main stream */</div><div class='add'>+			main_stream = ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(state, stream);</div><div class='add'>+			if (!main_stream)</div><div class='add'>+				goto failed;</div><div class='add'>+</div><div class='add'>+			/* get cfg idx for associated main stream */</div><div class='add'>+			cfg_idx = find_disp_cfg_idx_by_stream_id(</div><div class='add'>+					mapping, main_stream-&gt;stream_id);</div><div class='add'>+		} else {</div><div class='add'>+			cfg_idx = find_disp_cfg_idx_by_stream_id(</div><div class='add'>+					mapping, stream-&gt;stream_id);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[cfg_idx].num_odms_required;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+failed:</div><div class='ctx'> 	ASSERT(false);</div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static unsigned int get_source_odm_factor(const struct dml2_context *ctx,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *otg_master = ctx-&gt;config.callbacks.get_otg_master_for_stream(&amp;state-&gt;res_ctx, stream);</div><div class='add'>+</div><div class='add'>+	if (!otg_master)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return ctx-&gt;config.callbacks.get_odm_slice_count(otg_master);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_source_mpc_factor(const struct dml2_context *ctx,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		const struct dc_plane_state *plane)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};</div><div class='add'>+	int dpp_pipe_count = ctx-&gt;config.callbacks.get_dpp_pipes_for_plane(plane,</div><div class='add'>+			&amp;state-&gt;res_ctx, dpp_pipes);</div><div class='add'>+</div><div class='add'>+	ASSERT(dpp_pipe_count &gt; 0);</div><div class='add'>+	return ctx-&gt;config.callbacks.get_mpc_slice_count(dpp_pipes[0]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> static void populate_mpc_factors_for_stream(</div><div class='ctx'> 		struct dml2_context *ctx,</div><div class='ctx'> 		const struct dml_display_cfg_st *disp_cfg,</div><div class='ctx'> 		struct dml2_dml_to_dc_pipe_mapping *mapping,</div><div class='del'>-		const struct dc_state *state,</div><div class='add'>+		struct dc_state *state,</div><div class='ctx'> 		unsigned int stream_idx,</div><div class='del'>-		unsigned int odm_factor,</div><div class='del'>-		unsigned int mpc_factors[MAX_PIPES])</div><div class='add'>+		struct dml2_pipe_combine_factor odm_factor,</div><div class='add'>+		struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])</div><div class='ctx'> {</div><div class='ctx'> 	const struct dc_stream_status *status = &amp;state-&gt;stream_status[stream_idx];</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; status-&gt;plane_count; i++)</div><div class='del'>-		if (odm_factor == 1)</div><div class='del'>-			mpc_factors[i] = get_mpc_factor(</div><div class='del'>-					ctx, state, disp_cfg, mapping, status,</div><div class='del'>-					state-&gt;streams[stream_idx], i);</div><div class='del'>-		else</div><div class='del'>-			mpc_factors[i] = 1;</div><div class='add'>+	for (i = 0; i &lt; status-&gt;plane_count; i++) {</div><div class='add'>+		mpc_factors[i].source = get_source_mpc_factor(ctx, state, status-&gt;plane_states[i]);</div><div class='add'>+		mpc_factors[i].target = (odm_factor.target == 1) ?</div><div class='add'>+				get_target_mpc_factor(ctx, state, disp_cfg, mapping, status, state-&gt;streams[stream_idx], i) : 1;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void populate_odm_factors(const struct dml2_context *ctx,</div><div class='ctx'> 		const struct dml_display_cfg_st *disp_cfg,</div><div class='ctx'> 		struct dml2_dml_to_dc_pipe_mapping *mapping,</div><div class='del'>-		const struct dc_state *state,</div><div class='del'>-		unsigned int odm_factors[MAX_PIPES])</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dml2_pipe_combine_factor odm_factors[MAX_PIPES])</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='del'>-		odm_factors[i] = get_odm_factor(</div><div class='del'>-				ctx, disp_cfg, mapping, state-&gt;streams[i]);</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		odm_factors[i].source = get_source_odm_factor(ctx, state, state-&gt;streams[i]);</div><div class='add'>+		odm_factors[i].target = get_target_odm_factor(</div><div class='add'>+				ctx, state, disp_cfg, mapping, state-&gt;streams[i]);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool map_dc_pipes_for_stream(struct dml2_context *ctx,</div><div class='add'>+static bool unmap_dc_pipes_for_stream(struct dml2_context *ctx,</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		const struct dc_state *existing_state,</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		const struct dc_stream_status *status,</div><div class='del'>-		unsigned int odm_factor,</div><div class='del'>-		unsigned int mpc_factors[MAX_PIPES])</div><div class='add'>+		struct dml2_pipe_combine_factor odm_factor,</div><div class='add'>+		struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])</div><div class='ctx'> {</div><div class='ctx'> 	int plane_idx;</div><div class='ctx'> 	bool result = true;</div><div class='ctx'> </div><div class='del'>-	if (odm_factor == 1)</div><div class='del'>-		/*</div><div class='del'>-		 * ODM and MPC combines are by DML design mutually exclusive.</div><div class='del'>-		 * ODM factor of 1 means MPC factors may be greater than 1.</div><div class='del'>-		 * In this case, we want to set ODM factor to 1 first to free up</div><div class='del'>-		 * pipe resources from previous ODM configuration before setting</div><div class='del'>-		 * up MPC combine to acquire more pipe resources.</div><div class='del'>-		 */</div><div class='add'>+	for (plane_idx = 0; plane_idx &lt; status-&gt;plane_count; plane_idx++)</div><div class='add'>+		if (mpc_factors[plane_idx].target &lt; mpc_factors[plane_idx].source)</div><div class='add'>+			result &amp;= ctx-&gt;config.callbacks.update_pipes_for_plane_with_slice_count(</div><div class='add'>+					state,</div><div class='add'>+					existing_state,</div><div class='add'>+					ctx-&gt;config.callbacks.dc-&gt;res_pool,</div><div class='add'>+					status-&gt;plane_states[plane_idx],</div><div class='add'>+					mpc_factors[plane_idx].target);</div><div class='add'>+	if (odm_factor.target &lt; odm_factor.source)</div><div class='ctx'> 		result &amp;= ctx-&gt;config.callbacks.update_pipes_for_stream_with_slice_count(</div><div class='ctx'> 				state,</div><div class='ctx'> 				existing_state,</div><div class='ctx'> 				ctx-&gt;config.callbacks.dc-&gt;res_pool,</div><div class='ctx'> 				stream,</div><div class='del'>-				odm_factor);</div><div class='add'>+				odm_factor.target);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool map_dc_pipes_for_stream(struct dml2_context *ctx,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		const struct dc_state *existing_state,</div><div class='add'>+		const struct dc_stream_state *stream,</div><div class='add'>+		const struct dc_stream_status *status,</div><div class='add'>+		struct dml2_pipe_combine_factor odm_factor,</div><div class='add'>+		struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])</div><div class='add'>+{</div><div class='add'>+	int plane_idx;</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='ctx'> 	for (plane_idx = 0; plane_idx &lt; status-&gt;plane_count; plane_idx++)</div><div class='del'>-		result &amp;= ctx-&gt;config.callbacks.update_pipes_for_plane_with_slice_count(</div><div class='del'>-				state,</div><div class='del'>-				existing_state,</div><div class='del'>-				ctx-&gt;config.callbacks.dc-&gt;res_pool,</div><div class='del'>-				status-&gt;plane_states[plane_idx],</div><div class='del'>-				mpc_factors[plane_idx]);</div><div class='del'>-	if (odm_factor &gt; 1)</div><div class='add'>+		if (mpc_factors[plane_idx].target &gt; mpc_factors[plane_idx].source)</div><div class='add'>+			result &amp;= ctx-&gt;config.callbacks.update_pipes_for_plane_with_slice_count(</div><div class='add'>+					state,</div><div class='add'>+					existing_state,</div><div class='add'>+					ctx-&gt;config.callbacks.dc-&gt;res_pool,</div><div class='add'>+					status-&gt;plane_states[plane_idx],</div><div class='add'>+					mpc_factors[plane_idx].target);</div><div class='add'>+	if (odm_factor.target &gt; odm_factor.source)</div><div class='ctx'> 		result &amp;= ctx-&gt;config.callbacks.update_pipes_for_stream_with_slice_count(</div><div class='ctx'> 				state,</div><div class='ctx'> 				existing_state,</div><div class='ctx'> 				ctx-&gt;config.callbacks.dc-&gt;res_pool,</div><div class='ctx'> 				stream,</div><div class='del'>-				odm_factor);</div><div class='add'>+				odm_factor.target);</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -928,20 +1015,20 @@ static bool map_dc_pipes_with_callbacks(struct dml2_context *ctx,</div><div class='ctx'> 		struct dml2_dml_to_dc_pipe_mapping *mapping,</div><div class='ctx'> 		const struct dc_state *existing_state)</div><div class='ctx'> {</div><div class='del'>-	unsigned int odm_factors[MAX_PIPES];</div><div class='del'>-	unsigned int mpc_factors_for_stream[MAX_PIPES];</div><div class='ctx'> 	int i;</div><div class='ctx'> 	bool result = true;</div><div class='ctx'> </div><div class='del'>-	populate_odm_factors(ctx, disp_cfg, mapping, state, odm_factors);</div><div class='del'>-	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+	populate_odm_factors(ctx, disp_cfg, mapping, state, ctx-&gt;pipe_combine_scratch.odm_factors);</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='ctx'> 		populate_mpc_factors_for_stream(ctx, disp_cfg, mapping, state,</div><div class='del'>-				i, odm_factors[i], mpc_factors_for_stream);</div><div class='del'>-		result &amp;= map_dc_pipes_for_stream(ctx, state, existing_state,</div><div class='del'>-				state-&gt;streams[i],</div><div class='del'>-				&amp;state-&gt;stream_status[i],</div><div class='del'>-				odm_factors[i], mpc_factors_for_stream);</div><div class='del'>-	}</div><div class='add'>+				i, ctx-&gt;pipe_combine_scratch.odm_factors[i], ctx-&gt;pipe_combine_scratch.mpc_factors[i]);</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		result &amp;= unmap_dc_pipes_for_stream(ctx, state, existing_state, state-&gt;streams[i],</div><div class='add'>+				&amp;state-&gt;stream_status[i], ctx-&gt;pipe_combine_scratch.odm_factors[i], ctx-&gt;pipe_combine_scratch.mpc_factors[i]);</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		result &amp;= map_dc_pipes_for_stream(ctx, state, existing_state, state-&gt;streams[i],</div><div class='add'>+				&amp;state-&gt;stream_status[i], ctx-&gt;pipe_combine_scratch.odm_factors[i], ctx-&gt;pipe_combine_scratch.mpc_factors[i]);</div><div class='add'>+</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -951,37 +1038,75 @@ bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const s</div><div class='ctx'> </div><div class='ctx'> 	unsigned int stream_disp_cfg_index;</div><div class='ctx'> 	unsigned int plane_disp_cfg_index;</div><div class='add'>+	unsigned int disp_cfg_index_max;</div><div class='ctx'> </div><div class='ctx'> 	unsigned int plane_id;</div><div class='ctx'> 	unsigned int stream_id;</div><div class='ctx'> </div><div class='ctx'> 	const unsigned int *ODMMode, *DPPPerSurface;</div><div class='add'>+	unsigned int odm_mode_array[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}, dpp_per_surface_array[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};</div><div class='ctx'> 	struct dc_pipe_mapping_scratch scratch;</div><div class='ctx'> </div><div class='ctx'> 	if (ctx-&gt;config.map_dc_pipes_with_callbacks)</div><div class='ctx'> 		return map_dc_pipes_with_callbacks(</div><div class='ctx'> 				ctx, state, disp_cfg, mapping, existing_state);</div><div class='ctx'> </div><div class='del'>-	ODMMode = (unsigned int *)disp_cfg-&gt;hw.ODMMode;</div><div class='del'>-	DPPPerSurface = disp_cfg-&gt;hw.DPPPerSurface;</div><div class='add'>+	if (ctx-&gt;architecture == dml2_architecture_21) {</div><div class='add'>+		/*</div><div class='add'>+		 * Extract ODM and DPP outputs from DML2.1 and map them in an array as required for pipe mapping in dml2_map_dc_pipes.</div><div class='add'>+		 * As data cannot be directly extracted in const pointers, assign these arrays to const pointers before proceeding to</div><div class='add'>+		 * maximize the reuse of existing code. Const pointers are required because dml2.0 dml_display_cfg_st is const.</div><div class='add'>+		 *</div><div class='add'>+		 */</div><div class='add'>+		for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='add'>+			odm_mode_array[i] = ctx-&gt;v21.mode_programming.programming-&gt;stream_programming[i].num_odms_required;</div><div class='add'>+			dpp_per_surface_array[i] = ctx-&gt;v21.mode_programming.programming-&gt;plane_programming[i].num_dpps_required;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ODMMode = (const unsigned int *)odm_mode_array;</div><div class='add'>+		DPPPerSurface = (const unsigned int *)dpp_per_surface_array;</div><div class='add'>+		disp_cfg_index_max = __DML2_WRAPPER_MAX_STREAMS_PLANES__;</div><div class='add'>+	} else {</div><div class='add'>+		ODMMode = (unsigned int *)disp_cfg-&gt;hw.ODMMode;</div><div class='add'>+		DPPPerSurface = disp_cfg-&gt;hw.DPPPerSurface;</div><div class='add'>+		disp_cfg_index_max = __DML_NUM_PLANES__;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (stream_index = 0; stream_index &lt; state-&gt;stream_count; stream_index++) {</div><div class='ctx'> 		memset(&amp;scratch, 0, sizeof(struct dc_pipe_mapping_scratch));</div><div class='ctx'> </div><div class='ctx'> 		stream_id = state-&gt;streams[stream_index]-&gt;stream_id;</div><div class='ctx'> 		stream_disp_cfg_index = find_disp_cfg_idx_by_stream_id(mapping, stream_id);</div><div class='add'>+		if (stream_disp_cfg_index &gt;= disp_cfg_index_max)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-		if (ODMMode[stream_disp_cfg_index] == dml_odm_mode_bypass) {</div><div class='del'>-			scratch.odm_info.odm_factor = 1;</div><div class='del'>-		} else if (ODMMode[stream_disp_cfg_index] == dml_odm_mode_combine_2to1) {</div><div class='del'>-			scratch.odm_info.odm_factor = 2;</div><div class='del'>-		} else if (ODMMode[stream_disp_cfg_index] == dml_odm_mode_combine_4to1) {</div><div class='del'>-			scratch.odm_info.odm_factor = 4;</div><div class='del'>-		} else {</div><div class='del'>-			ASSERT(false);</div><div class='del'>-			scratch.odm_info.odm_factor = 1;</div><div class='add'>+		if (ctx-&gt;architecture == dml2_architecture_20) {</div><div class='add'>+			if (ODMMode[stream_disp_cfg_index] == dml_odm_mode_bypass) {</div><div class='add'>+				scratch.odm_info.odm_factor = 1;</div><div class='add'>+			} else if (ODMMode[stream_disp_cfg_index] == dml_odm_mode_combine_2to1) {</div><div class='add'>+				scratch.odm_info.odm_factor = 2;</div><div class='add'>+			} else if (ODMMode[stream_disp_cfg_index] == dml_odm_mode_combine_4to1) {</div><div class='add'>+				scratch.odm_info.odm_factor = 4;</div><div class='add'>+			} else {</div><div class='add'>+				ASSERT(false);</div><div class='add'>+				scratch.odm_info.odm_factor = 1;</div><div class='add'>+			}</div><div class='add'>+		} else if (ctx-&gt;architecture == dml2_architecture_21) {</div><div class='add'>+		/* After DML2.1 update, ODM interpretation needs to change and is no longer same as for DML2.0.</div><div class='add'>+		 * This is not an issue with new resource management logic. This block ensure backcompat</div><div class='add'>+		 * with legacy pipe management with updated DML.</div><div class='add'>+		 * */</div><div class='add'>+			if (ODMMode[stream_disp_cfg_index] == 1) {</div><div class='add'>+				scratch.odm_info.odm_factor = 1;</div><div class='add'>+			} else if (ODMMode[stream_disp_cfg_index] == 2) {</div><div class='add'>+				scratch.odm_info.odm_factor = 2;</div><div class='add'>+			} else if (ODMMode[stream_disp_cfg_index] == 4) {</div><div class='add'>+				scratch.odm_info.odm_factor = 4;</div><div class='add'>+			} else {</div><div class='add'>+				ASSERT(false);</div><div class='add'>+				scratch.odm_info.odm_factor = 1;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='ctx'> 		calculate_odm_slices(state-&gt;streams[stream_index], scratch.odm_info.odm_factor, scratch.odm_info.odm_slice_end_x);</div><div class='ctx'> </div><div class='ctx'> 		// If there are no planes, you still want to setup ODM...</div><div class='hunk'>@@ -997,7 +1122,7 @@ bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const s</div><div class='ctx'> </div><div class='ctx'> 				// Setup mpc_info for this plane</div><div class='ctx'> 				scratch.mpc_info.prev_odm_pipe = NULL;</div><div class='del'>-				if (scratch.odm_info.odm_factor == 1) {</div><div class='add'>+				if (scratch.odm_info.odm_factor == 1 &amp;&amp; plane_disp_cfg_index &lt; disp_cfg_index_max) {</div><div class='ctx'> 					// If ODM combine is not inuse, then the number of pipes</div><div class='ctx'> 					// per plane is determined by MPC combine factor</div><div class='ctx'> 					scratch.mpc_info.mpc_factor = DPPPerSurface[plane_disp_cfg_index];</div><div class='hunk'>@@ -1037,6 +1162,12 @@ bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const s</div><div class='ctx'> 				ASSERT(false);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		if (ctx-&gt;config.callbacks.build_test_pattern_params &amp;&amp;</div><div class='add'>+				pipe-&gt;stream &amp;&amp;</div><div class='add'>+				pipe-&gt;prev_odm_pipe == NULL &amp;&amp;</div><div class='add'>+				pipe-&gt;top_pipe == NULL)</div><div class='add'>+			ctx-&gt;config.callbacks.build_test_pattern_params(&amp;state-&gt;res_ctx, pipe);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h<br/>index 2f91244a7b01..1538b708d8be 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h</a></div><div class='hunk'>@@ -30,6 +30,8 @@</div><div class='ctx'> #include "dml2_dc_types.h"</div><div class='ctx'> </div><div class='ctx'> struct dml2_context;</div><div class='add'>+struct dml2_dml_to_dc_pipe_mapping;</div><div class='add'>+struct dml_display_cfg_st;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * dml2_map_dc_pipes - Creates a pipe linkage in dc_state based on current display config.</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h<br/>index 7ca7f2a743c2..7ca7f2a743c2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h<br/>index 1cf8a884c0fb..55b3e3ca54f7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h</a></div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'>  * Authors: AMD</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>- </div><div class='add'>+</div><div class='ctx'> #ifndef __DML2_INTERNAL_TYPES_H__</div><div class='ctx'> #define __DML2_INTERNAL_TYPES_H__</div><div class='ctx'> </div><div class='hunk'>@@ -32,6 +32,8 @@</div><div class='ctx'> #include "dml2_wrapper.h"</div><div class='ctx'> #include "dml2_policy.h"</div><div class='ctx'> </div><div class='add'>+#include "dml_top.h"</div><div class='add'>+#include "dml21_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> struct dml2_wrapper_optimize_configuration_params {</div><div class='ctx'> 	struct display_mode_lib_st *dml_core_ctx;</div><div class='hunk'>@@ -99,6 +101,7 @@ struct dml2_wrapper_scratch {</div><div class='ctx'> 	struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;</div><div class='ctx'> 	bool enable_flexible_pipe_mapping;</div><div class='ctx'> 	bool plane_duplicate_exists;</div><div class='add'>+	int hpo_stream_to_link_encoder_mapping[MAX_HPO_DP2_ENCODERS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dml2_helper_det_policy_scratch {</div><div class='hunk'>@@ -107,18 +110,47 @@ struct dml2_helper_det_policy_scratch {</div><div class='ctx'> </div><div class='ctx'> enum dml2_architecture {</div><div class='ctx'> 	dml2_architecture_20,</div><div class='add'>+	dml2_architecture_21</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct prepare_mcache_programming_locals {</div><div class='add'>+	struct dml2_build_mcache_programming_in_out build_mcache_programming_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml21_wrapper_scratch {</div><div class='add'>+	struct prepare_mcache_programming_locals prepare_mcache_locals;</div><div class='add'>+	struct pipe_ctx temp_pipe;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pipe_combine_factor {</div><div class='add'>+	unsigned int source;</div><div class='add'>+	unsigned int target;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dml2_pipe_combine_scratch {</div><div class='add'>+	struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];</div><div class='add'>+	struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dml2_context {</div><div class='ctx'> 	enum dml2_architecture architecture;</div><div class='ctx'> 	struct dml2_configuration_options config;</div><div class='ctx'> 	struct dml2_helper_det_policy_scratch det_helper_scratch;</div><div class='add'>+	struct dml2_pipe_combine_scratch pipe_combine_scratch;</div><div class='ctx'> 	union {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			struct display_mode_lib_st dml_core_ctx;</div><div class='ctx'> 			struct dml2_wrapper_scratch scratch;</div><div class='ctx'> 			struct dcn_watermarks g6_temp_read_watermark_set;</div><div class='ctx'> 		} v20;</div><div class='add'>+		struct {</div><div class='add'>+			struct dml21_wrapper_scratch scratch;</div><div class='add'>+			struct dml2_initialize_instance_in_out dml_init;</div><div class='add'>+			struct dml2_display_cfg display_config;</div><div class='add'>+			struct dml2_check_mode_supported_in_out mode_support;</div><div class='add'>+			struct dml2_build_mode_programming_in_out mode_programming;</div><div class='add'>+			struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;</div><div class='add'>+		} v21;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c<br/>index 282d70e2b18a..66040c877d68 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> #include "dml2_dc_types.h"</div><div class='ctx'> #include "dml2_internal_types.h"</div><div class='ctx'> #include "dml2_utils.h"</div><div class='hunk'>@@ -654,14 +655,14 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state</div><div class='ctx'> 				     unsigned int svp_height,</div><div class='ctx'> 				     unsigned int svp_vstartup)</div><div class='ctx'> {</div><div class='del'>-	unsigned int i, pipe_idx;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> 	double line_time, fp_and_sync_width_time;</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='ctx'> 	uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;</div><div class='ctx'> 	static const double cvt_rb_vblank_max = ((double) 460 / (1000 * 1000));</div><div class='ctx'> </div><div class='ctx'> 	// Find DML pipe index (pipe_idx) using dc_pipe_idx</div><div class='del'>-	for (i = 0, pipe_idx = 0; i &lt; ctx-&gt;config.dcn_pipe_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; ctx-&gt;config.dcn_pipe_count; i++) {</div><div class='ctx'> 		pipe = &amp;state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe-&gt;stream)</div><div class='hunk'>@@ -669,8 +670,6 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state</div><div class='ctx'> </div><div class='ctx'> 		if (i == dc_pipe_idx)</div><div class='ctx'> 			break;</div><div class='del'>-</div><div class='del'>-		pipe_idx++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// Calculate lines required for pstate allow width and FW processing delays</div><div class='hunk'>@@ -750,6 +749,8 @@ static void enable_phantom_plane(struct dml2_context *ctx,</div><div class='ctx'> 					ctx-&gt;config.svp_pstate.callbacks.dc,</div><div class='ctx'> 					state,</div><div class='ctx'> 					curr_pipe-&gt;plane_state);</div><div class='add'>+			if (!phantom_plane)</div><div class='add'>+				return;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		memcpy(&amp;phantom_plane-&gt;address, &amp;curr_pipe-&gt;plane_state-&gt;address, sizeof(phantom_plane-&gt;address));</div><div class='hunk'>@@ -811,7 +812,7 @@ static bool remove_all_phantom_planes_for_stream(struct dml2_context *ctx, struc</div><div class='ctx'> {</div><div class='ctx'> 	int i, old_plane_count;</div><div class='ctx'> 	struct dc_stream_status *stream_status = NULL;</div><div class='del'>-	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };</div><div class='add'>+	struct dc_plane_state *del_planes[MAX_SURFACES] = { 0 };</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='ctx'> 			if (context-&gt;streams[i] == stream) {</div><div class='hunk'>@@ -866,7 +867,7 @@ bool dml2_svp_remove_all_phantom_pipes(struct dml2_context *ctx, struct dc_state</div><div class='ctx'> </div><div class='ctx'> /* Conditions for setting up phantom pipes for SubVP:</div><div class='ctx'>  * 1. Not force disable SubVP</div><div class='del'>- * 2. Full update (i.e. !fast_validate)</div><div class='add'>+ * 2. Full update (i.e. DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='ctx'>  * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)</div><div class='ctx'>  * 4. Display configuration passes validation</div><div class='ctx'>  * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc-&gt;debug.force_subvp_mclk_switch)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h<br/>index 9d64851f54e7..9d64851f54e7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c<br/>index c4c52173ef22..ef693f608d59 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c</a></div><div class='hunk'>@@ -301,6 +301,7 @@ void build_unoptimized_policy_settings(enum dml_project_id project, struct dml_m</div><div class='ctx'> 	policy-&gt;AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported = true; // TOREVIEW: What does this mean?</div><div class='ctx'> 	policy-&gt;AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported = true; // TOREVIEW: What does this mean?</div><div class='ctx'> 	if (project == dml_project_dcn35 ||</div><div class='add'>+		project == dml_project_dcn36 ||</div><div class='ctx'> 		project == dml_project_dcn351) {</div><div class='ctx'> 		policy-&gt;DCCProgrammingAssumesScanDirectionUnknownFinal = false;</div><div class='ctx'> 		policy-&gt;EnhancedPrefetchScheduleAccelerationFinal = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h<br/>index e83e05248592..e83e05248592 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c<br/>index 17a58f41fc6a..d834cb595afa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c</a></div><div class='hunk'>@@ -29,11 +29,11 @@</div><div class='ctx'> #include "dml2_translation_helper.h"</div><div class='ctx'> </div><div class='ctx'> #define NUM_DCFCLK_STAS 5</div><div class='add'>+#define NUM_DCFCLK_STAS_NEW 8</div><div class='ctx'> </div><div class='ctx'> void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)</div><div class='ctx'> {</div><div class='ctx'> 	switch (dml2-&gt;v20.dml_core_ctx.project) {</div><div class='del'>-</div><div class='ctx'> 	case dml_project_dcn32:</div><div class='ctx'> 	case dml_project_dcn321:</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -107,6 +107,7 @@ void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, stru</div><div class='ctx'> </div><div class='ctx'> 	case dml_project_dcn35:</div><div class='ctx'> 	case dml_project_dcn351:</div><div class='add'>+	case dml_project_dcn36:</div><div class='ctx'> 		out-&gt;rob_buffer_size_kbytes = 64;</div><div class='ctx'> 		out-&gt;config_return_buffer_size_in_kbytes = 1792;</div><div class='ctx'> 		out-&gt;compressed_buffer_segment_size_in_kbytes = 64;</div><div class='hunk'>@@ -175,6 +176,69 @@ void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, stru</div><div class='ctx'> 		out-&gt;config_return_buffer_segment_size_in_kbytes = 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='add'>+	case dml_project_dcn401:</div><div class='add'>+		// Hardcoded values for DCN4m</div><div class='add'>+		out-&gt;vblank_nom_default_us = 668;	//600;</div><div class='add'>+		out-&gt;rob_buffer_size_kbytes = 192;	//128;</div><div class='add'>+		out-&gt;config_return_buffer_size_in_kbytes = 1344;	//1280;</div><div class='add'>+		out-&gt;config_return_buffer_segment_size_in_kbytes = 64;</div><div class='add'>+		out-&gt;compressed_buffer_segment_size_in_kbytes = 64;</div><div class='add'>+		out-&gt;meta_fifo_size_in_kentries = 22;</div><div class='add'>+		out-&gt;dpte_buffer_size_in_pte_reqs_luma = 68;</div><div class='add'>+		out-&gt;dpte_buffer_size_in_pte_reqs_chroma = 36;</div><div class='add'>+		out-&gt;gpuvm_max_page_table_levels = 4;</div><div class='add'>+		out-&gt;pixel_chunk_size_kbytes = 8;</div><div class='add'>+		out-&gt;alpha_pixel_chunk_size_kbytes = 4;</div><div class='add'>+		out-&gt;min_pixel_chunk_size_bytes = 1024;</div><div class='add'>+		out-&gt;writeback_chunk_size_kbytes = 8;</div><div class='add'>+		out-&gt;line_buffer_size_bits = 1171920;</div><div class='add'>+		out-&gt;max_line_buffer_lines = 32;</div><div class='add'>+		out-&gt;writeback_interface_buffer_size_kbytes = 90;</div><div class='add'>+		//Number of pipes after DCN Pipe harvesting</div><div class='add'>+		out-&gt;max_num_dpp = dml2-&gt;config.dcn_pipe_count;</div><div class='add'>+		out-&gt;max_num_otg = dml2-&gt;config.dcn_pipe_count;</div><div class='add'>+		out-&gt;max_num_wb = 1;</div><div class='add'>+		out-&gt;max_dchub_pscl_bw_pix_per_clk = 4;</div><div class='add'>+		out-&gt;max_pscl_lb_bw_pix_per_clk = 2;</div><div class='add'>+		out-&gt;max_lb_vscl_bw_pix_per_clk = 4;</div><div class='add'>+		out-&gt;max_vscl_hscl_bw_pix_per_clk = 4;</div><div class='add'>+		out-&gt;max_hscl_ratio = 6;</div><div class='add'>+		out-&gt;max_vscl_ratio = 6;</div><div class='add'>+		out-&gt;max_hscl_taps = 8;</div><div class='add'>+		out-&gt;max_vscl_taps = 8;</div><div class='add'>+		out-&gt;dispclk_ramp_margin_percent = 1;</div><div class='add'>+		out-&gt;dppclk_delay_subtotal = 47;</div><div class='add'>+		out-&gt;dppclk_delay_scl = 50;</div><div class='add'>+		out-&gt;dppclk_delay_scl_lb_only = 16;</div><div class='add'>+		out-&gt;dppclk_delay_cnvc_formatter = 28;</div><div class='add'>+		out-&gt;dppclk_delay_cnvc_cursor = 6;</div><div class='add'>+		out-&gt;dispclk_delay_subtotal = 125;</div><div class='add'>+		out-&gt;cursor_buffer_size = 24;	//16</div><div class='add'>+		out-&gt;cursor_chunk_size = 2;</div><div class='add'>+		out-&gt;max_inter_dcn_tile_repeaters = 8;</div><div class='add'>+		out-&gt;writeback_max_hscl_ratio = 1;</div><div class='add'>+		out-&gt;writeback_max_vscl_ratio = 1;</div><div class='add'>+		out-&gt;writeback_min_hscl_ratio = 1;</div><div class='add'>+		out-&gt;writeback_min_vscl_ratio = 1;</div><div class='add'>+		out-&gt;writeback_max_hscl_taps = 1;</div><div class='add'>+		out-&gt;writeback_max_vscl_taps = 1;</div><div class='add'>+		out-&gt;writeback_line_buffer_buffer_size = 0;</div><div class='add'>+		out-&gt;num_dsc = 4;</div><div class='add'>+		out-&gt;maximum_dsc_bits_per_component = 12;</div><div class='add'>+		out-&gt;maximum_pixels_per_line_per_dsc_unit = 5760;</div><div class='add'>+		out-&gt;dsc422_native_support = true;</div><div class='add'>+		out-&gt;dcc_supported = true;</div><div class='add'>+		out-&gt;ptoi_supported = false;</div><div class='add'>+</div><div class='add'>+		out-&gt;gpuvm_enable = false;</div><div class='add'>+		out-&gt;hostvm_enable = false;</div><div class='add'>+		out-&gt;cursor_64bpp_support = true;	//false;</div><div class='add'>+		out-&gt;dynamic_metadata_vm_enabled = false;</div><div class='add'>+</div><div class='add'>+		out-&gt;max_num_hdmi_frl_outputs = 1;</div><div class='add'>+		out-&gt;max_num_dp2p0_outputs = 4;		//2;</div><div class='add'>+		out-&gt;max_num_dp2p0_streams = 4;</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -228,16 +292,29 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case dml_project_dcn35:</div><div class='add'>+	case dml_project_dcn351:</div><div class='add'>+	case dml_project_dcn36:</div><div class='ctx'> 		out-&gt;num_chans = 4;</div><div class='ctx'> 		out-&gt;round_trip_ping_latency_dcfclk_cycles = 106;</div><div class='ctx'> 		out-&gt;smn_latency_us = 2;</div><div class='ctx'> 		out-&gt;dispclk_dppclk_vco_speed_mhz = 3600;</div><div class='add'>+		out-&gt;pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='del'>-	case dml_project_dcn351:</div><div class='add'>+</div><div class='add'>+	case dml_project_dcn401:</div><div class='add'>+		out-&gt;pct_ideal_fabric_bw_after_urgent = 76;			//67;</div><div class='add'>+		out-&gt;max_avg_sdp_bw_use_normal_percent = 75;		//80;</div><div class='add'>+		out-&gt;max_avg_fabric_bw_use_normal_percent = 57;		//60;</div><div class='add'>+</div><div class='add'>+		out-&gt;urgent_out_of_order_return_per_channel_pixel_only_bytes = 0;	//4096;</div><div class='add'>+		out-&gt;urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 0;	//4096;</div><div class='add'>+		out-&gt;urgent_out_of_order_return_per_channel_vm_only_bytes = 0;		//4096;</div><div class='add'>+</div><div class='ctx'> 		out-&gt;num_chans = 16;</div><div class='del'>-		out-&gt;round_trip_ping_latency_dcfclk_cycles = 1100;</div><div class='del'>-		out-&gt;smn_latency_us = 2;</div><div class='add'>+		out-&gt;round_trip_ping_latency_dcfclk_cycles = 1000;	//263;</div><div class='add'>+		out-&gt;smn_latency_us = 0;							//2 us</div><div class='add'>+		out-&gt;mall_allocated_for_dcn_mbytes = dml2-&gt;config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* ---Overrides if available--- */</div><div class='hunk'>@@ -253,12 +330,21 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> {</div><div class='ctx'> 	struct dml2_policy_build_synthetic_soc_states_scratch *s = &amp;dml2-&gt;v20.scratch.create_scratch.build_synthetic_socbb_scratch;</div><div class='ctx'> 	struct dml2_policy_build_synthetic_soc_states_params *p = &amp;dml2-&gt;v20.scratch.build_synthetic_socbb_params;</div><div class='del'>-	unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS];</div><div class='add'>+	unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS] = {0};</div><div class='add'>+	unsigned int dcfclk_stas_mhz_new[NUM_DCFCLK_STAS_NEW] = {0};</div><div class='add'>+	unsigned int dml_project = dml2-&gt;v20.dml_core_ctx.project;</div><div class='add'>+</div><div class='ctx'> 	unsigned int i = 0;</div><div class='ctx'> 	unsigned int transactions_per_mem_clock = 16; // project specific, depends on used Memory type</div><div class='ctx'> </div><div class='del'>-	p-&gt;dcfclk_stas_mhz = dcfclk_stas_mhz;</div><div class='del'>-	p-&gt;num_dcfclk_stas = NUM_DCFCLK_STAS;</div><div class='add'>+	if (dml_project == dml_project_dcn351) {</div><div class='add'>+		p-&gt;dcfclk_stas_mhz = dcfclk_stas_mhz_new;</div><div class='add'>+		p-&gt;num_dcfclk_stas = NUM_DCFCLK_STAS_NEW;</div><div class='add'>+	} else {</div><div class='add'>+		p-&gt;dcfclk_stas_mhz = dcfclk_stas_mhz;</div><div class='add'>+		p-&gt;num_dcfclk_stas = NUM_DCFCLK_STAS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	p-&gt;in_bbox = in_bbox;</div><div class='ctx'> 	p-&gt;out_states = out;</div><div class='ctx'> 	p-&gt;in_states = &amp;dml2-&gt;v20.scratch.create_scratch.in_states;</div><div class='hunk'>@@ -339,6 +425,43 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> 		p-&gt;in_states-&gt;state_array[1].dcfclk_mhz = 1434.0;</div><div class='ctx'> 		p-&gt;in_states-&gt;state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock;</div><div class='ctx'> 		break;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	case dml_project_dcn401:</div><div class='add'>+		p-&gt;in_states-&gt;num_states = 2;</div><div class='add'>+		transactions_per_mem_clock = 16;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].socclk_mhz = 300;		//620.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dscclk_mhz = 666.667;	//716.667;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].phyclk_mhz = 810;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].phyclk_d18_mhz = 667;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].phyclk_d32_mhz = 625;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dtbclk_mhz = 2000;		//1564.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].fabricclk_mhz = 300;	//450.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dcfclk_mhz = 200;		//300.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dispclk_mhz = 2000;	//2150.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dppclk_mhz = 2000;		//2150.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dram_speed_mts = 97 * transactions_per_mem_clock; //100 *</div><div class='add'>+</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].urgent_latency_pixel_data_only_us = 4;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].urgent_latency_vm_data_only_us = 0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].writeback_latency_us = 12;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 1000;	//3000;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].sr_exit_z8_time_us = 0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].sr_enter_plus_exit_z8_time_us = 0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].dram_clock_change_latency_us = 400;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].use_ideal_dram_bw_strobe = true;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].sr_exit_time_us = 15.70;	//42.97;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].sr_enter_plus_exit_time_us = 20.20;	//49.94;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].fclk_change_latency_us = 0;	//20;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[0].usr_retraining_latency_us = 0;	//2;</div><div class='add'>+</div><div class='add'>+		p-&gt;in_states-&gt;state_array[1].socclk_mhz = 1600;		//1200.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[1].fabricclk_mhz = 2500;	//2500.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[1].dcfclk_mhz = 1800;		//1564.0;</div><div class='add'>+		p-&gt;in_states-&gt;state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock;</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Override from passed values, if available */</div><div class='hunk'>@@ -388,6 +511,7 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> 		p-&gt;dcfclk_stas_mhz[3] = 1324;</div><div class='ctx'> 		p-&gt;dcfclk_stas_mhz[4] = p-&gt;in_states-&gt;state_array[1].dcfclk_mhz;</div><div class='ctx'> 	} else if (dml2-&gt;v20.dml_core_ctx.project != dml_project_dcn35 &amp;&amp;</div><div class='add'>+			dml2-&gt;v20.dml_core_ctx.project != dml_project_dcn36 &amp;&amp;</div><div class='ctx'> 			dml2-&gt;v20.dml_core_ctx.project != dml_project_dcn351) {</div><div class='ctx'> 		p-&gt;dcfclk_stas_mhz[0] = 300;</div><div class='ctx'> 		p-&gt;dcfclk_stas_mhz[1] = 615;</div><div class='hunk'>@@ -435,14 +559,54 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dml2_policy_build_synthetic_soc_states(s, p);</div><div class='ctx'> 	if (dml2-&gt;v20.dml_core_ctx.project == dml_project_dcn35 ||</div><div class='del'>-		dml2-&gt;v20.dml_core_ctx.project == dml_project_dcn351) {</div><div class='del'>-		// Override last out_state with data from last in_state</div><div class='del'>-		// This will ensure that out_state contains max fclk</div><div class='del'>-		memcpy(&amp;p-&gt;out_states-&gt;state_array[p-&gt;out_states-&gt;num_states - 1],</div><div class='del'>-				&amp;p-&gt;in_states-&gt;state_array[p-&gt;in_states-&gt;num_states - 1],</div><div class='del'>-				sizeof(struct soc_state_bounding_box_st));</div><div class='add'>+	    dml2-&gt;v20.dml_core_ctx.project == dml_project_dcn36 ||</div><div class='add'>+	    dml2-&gt;v20.dml_core_ctx.project == dml_project_dcn351) {</div><div class='add'>+		int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0,</div><div class='add'>+			max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0, max_socclk_mhz = 0;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; p-&gt;in_states-&gt;num_states; i++) {</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].dcfclk_mhz &gt; max_dcfclk_mhz)</div><div class='add'>+				max_dcfclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].dcfclk_mhz;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].fabricclk_mhz &gt; max_fclk_mhz)</div><div class='add'>+				max_fclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].fabricclk_mhz;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].socclk_mhz &gt; max_socclk_mhz)</div><div class='add'>+				max_socclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].socclk_mhz;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].dram_speed_mts &gt; max_uclk_mhz)</div><div class='add'>+				max_uclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].dram_speed_mts;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].dispclk_mhz &gt; max_dispclk_mhz)</div><div class='add'>+				max_dispclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].dispclk_mhz;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].dppclk_mhz &gt; max_dppclk_mhz)</div><div class='add'>+				max_dppclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].dppclk_mhz;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].phyclk_mhz &gt; max_phyclk_mhz)</div><div class='add'>+				max_phyclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].phyclk_mhz;</div><div class='add'>+			if (p-&gt;in_states-&gt;state_array[i].dtbclk_mhz &gt; max_dtbclk_mhz)</div><div class='add'>+				max_dtbclk_mhz = (int)p-&gt;in_states-&gt;state_array[i].dtbclk_mhz;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; p-&gt;in_states-&gt;num_states; i++) {</div><div class='add'>+			/* Independent states - including base (unlisted) parameters from state 0. */</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i] = p-&gt;in_states-&gt;state_array[0];</div><div class='add'>+</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dispclk_mhz = max_dispclk_mhz;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dppclk_mhz = max_dppclk_mhz;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dtbclk_mhz = max_dtbclk_mhz;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].phyclk_mhz = max_phyclk_mhz;</div><div class='add'>+</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dscclk_mhz = max_dispclk_mhz / 3.0;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].phyclk_mhz = max_phyclk_mhz;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dtbclk_mhz = max_dtbclk_mhz;</div><div class='add'>+</div><div class='add'>+			/* Dependent states. */</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dram_speed_mts = p-&gt;in_states-&gt;state_array[i].dram_speed_mts;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].fabricclk_mhz = p-&gt;in_states-&gt;state_array[i].fabricclk_mhz;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].socclk_mhz = p-&gt;in_states-&gt;state_array[i].socclk_mhz;</div><div class='add'>+			p-&gt;out_states-&gt;state_array[i].dcfclk_mhz = p-&gt;in_states-&gt;state_array[i].dcfclk_mhz;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		p-&gt;out_states-&gt;num_states = p-&gt;in_states-&gt;num_states;</div><div class='add'>+	} else {</div><div class='add'>+		dml2_policy_build_synthetic_soc_states(s, p);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -616,20 +780,21 @@ static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location,</div><div class='del'>-				const struct dc_stream_state *in, const struct pipe_ctx *pipe)</div><div class='add'>+				const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int output_bpc;</div><div class='ctx'> </div><div class='ctx'> 	out-&gt;DSCEnable[location] = (enum dml_dsc_enable)in-&gt;timing.flags.DSC;</div><div class='ctx'> 	out-&gt;OutputLinkDPLanes[location] = 4; // As per code in dcn20_resource.c</div><div class='ctx'> 	out-&gt;DSCInputBitPerComponent[location] = 12; // As per code in dcn20_resource.c</div><div class='add'>+	out-&gt;DSCSlices[location] = in-&gt;timing.dsc_cfg.num_slices_h;</div><div class='ctx'> </div><div class='ctx'> 	switch (in-&gt;signal) {</div><div class='ctx'> 	case SIGNAL_TYPE_DISPLAY_PORT_MST:</div><div class='ctx'> 	case SIGNAL_TYPE_DISPLAY_PORT:</div><div class='ctx'> 		out-&gt;OutputEncoder[location] = dml_dp;</div><div class='del'>-		if (is_dp2p0_output_encoder(pipe))</div><div class='del'>-			out-&gt;OutputEncoder[location] = dml_dp2p0;</div><div class='add'>+		if (location &lt; MAX_HPO_DP2_ENCODERS &amp;&amp; dml2-&gt;v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)</div><div class='add'>+			out-&gt;OutputEncoder[dml2-&gt;v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SIGNAL_TYPE_EDP:</div><div class='ctx'> 		out-&gt;OutputEncoder[location] = dml_edp;</div><div class='hunk'>@@ -734,7 +899,7 @@ static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st *out, unsig</div><div class='ctx'> 	out-&gt;SurfaceWidthC[location] = in-&gt;timing.h_addressable;</div><div class='ctx'> 	out-&gt;SurfaceHeightC[location] = in-&gt;timing.v_addressable;</div><div class='ctx'> 	out-&gt;PitchY[location] = ((out-&gt;SurfaceWidthY[location] + 127) / 128) * 128;</div><div class='del'>-	out-&gt;PitchC[location] = 0;</div><div class='add'>+	out-&gt;PitchC[location] = 1;</div><div class='ctx'> 	out-&gt;DCCEnable[location] = false;</div><div class='ctx'> 	out-&gt;DCCMetaPitchY[location] = 0;</div><div class='ctx'> 	out-&gt;DCCMetaPitchC[location] = 0;</div><div class='hunk'>@@ -766,6 +931,19 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p</div><div class='ctx'> 	default:</div><div class='ctx'> 		out-&gt;SurfaceTiling[location] = (enum dml_swizzle_mode)in-&gt;tiling_info.gfx9.swizzle;</div><div class='ctx'> 		break;</div><div class='add'>+	case dml_project_dcn401:</div><div class='add'>+		// Temporary use gfx11 swizzle in dml, until proper dml for DCN4x is integrated/implemented</div><div class='add'>+		switch (in-&gt;tiling_info.gfx_addr3.swizzle) {</div><div class='add'>+		case DC_ADDR3_SW_4KB_2D:</div><div class='add'>+		case DC_ADDR3_SW_64KB_2D:</div><div class='add'>+		case DC_ADDR3_SW_256KB_2D:</div><div class='add'>+		default:</div><div class='add'>+			out-&gt;SurfaceTiling[location] = dml_sw_64kb_r_x;</div><div class='add'>+			break;</div><div class='add'>+		case DC_ADDR3_SW_LINEAR:</div><div class='add'>+			out-&gt;SurfaceTiling[location] = dml_sw_linear;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (in-&gt;format) {</div><div class='hunk'>@@ -778,6 +956,7 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p</div><div class='ctx'> 		out-&gt;SourcePixelFormat[location] = dml_420_10;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:</div><div class='ctx'> 		out-&gt;SourcePixelFormat[location] = dml_444_64;</div><div class='hunk'>@@ -798,7 +977,9 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context)</div><div class='add'>+static struct scaler_data *get_scaler_data_for_plane(</div><div class='add'>+		const struct dc_plane_state *in,</div><div class='add'>+		struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct pipe_ctx *temp_pipe = &amp;context-&gt;res_ctx.temp_pipe;</div><div class='hunk'>@@ -812,17 +993,19 @@ static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state</div><div class='ctx'> 			temp_pipe-&gt;stream = pipe-&gt;stream;</div><div class='ctx'> 			temp_pipe-&gt;plane_state = pipe-&gt;plane_state;</div><div class='ctx'> 			temp_pipe-&gt;plane_res.scl_data.taps = pipe-&gt;plane_res.scl_data.taps;</div><div class='del'>-</div><div class='add'>+			temp_pipe-&gt;stream_res = pipe-&gt;stream_res;</div><div class='ctx'> 			resource_build_scaling_params(temp_pipe);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(i &lt; MAX_PIPES);</div><div class='del'>-	return temp_pipe-&gt;plane_res.scl_data;</div><div class='add'>+	return &amp;temp_pipe-&gt;plane_res.scl_data;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in)</div><div class='add'>+static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location,</div><div class='add'>+					 const struct dc_stream_state *in,</div><div class='add'>+					 const struct soc_bounding_box_st *soc)</div><div class='ctx'> {</div><div class='ctx'> 	dml_uint_t width, height;</div><div class='ctx'> </div><div class='hunk'>@@ -839,7 +1022,7 @@ static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned</div><div class='ctx'> 	out-&gt;CursorBPP[location] = dml_cur_32bit;</div><div class='ctx'> 	out-&gt;CursorWidth[location] = 256;</div><div class='ctx'> </div><div class='del'>-	out-&gt;GPUVMMinPageSizeKBytes[location] = 256;</div><div class='add'>+	out-&gt;GPUVMMinPageSizeKBytes[location] = soc-&gt;gpuvm_min_page_size_kbytes;</div><div class='ctx'> </div><div class='ctx'> 	out-&gt;ViewportWidth[location] = width;</div><div class='ctx'> 	out-&gt;ViewportHeight[location] = height;</div><div class='hunk'>@@ -876,29 +1059,31 @@ static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned</div><div class='ctx'> 	out-&gt;ScalerEnabled[location] = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context)</div><div class='add'>+static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location,</div><div class='add'>+						    const struct dc_plane_state *in, struct dc_state *context,</div><div class='add'>+						    const struct soc_bounding_box_st *soc)</div><div class='ctx'> {</div><div class='del'>-	const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context);</div><div class='add'>+	struct scaler_data *scaler_data = get_scaler_data_for_plane(in, context);</div><div class='ctx'> </div><div class='ctx'> 	out-&gt;CursorBPP[location] = dml_cur_32bit;</div><div class='ctx'> 	out-&gt;CursorWidth[location] = 256;</div><div class='ctx'> </div><div class='del'>-	out-&gt;GPUVMMinPageSizeKBytes[location] = 256;</div><div class='add'>+	out-&gt;GPUVMMinPageSizeKBytes[location] = soc-&gt;gpuvm_min_page_size_kbytes;</div><div class='ctx'> </div><div class='del'>-	out-&gt;ViewportWidth[location] = scaler_data.viewport.width;</div><div class='del'>-	out-&gt;ViewportHeight[location] = scaler_data.viewport.height;</div><div class='del'>-	out-&gt;ViewportWidthChroma[location] = scaler_data.viewport_c.width;</div><div class='del'>-	out-&gt;ViewportHeightChroma[location] = scaler_data.viewport_c.height;</div><div class='del'>-	out-&gt;ViewportXStart[location] = scaler_data.viewport.x;</div><div class='del'>-	out-&gt;ViewportYStart[location] = scaler_data.viewport.y;</div><div class='del'>-	out-&gt;ViewportXStartC[location] = scaler_data.viewport_c.x;</div><div class='del'>-	out-&gt;ViewportYStartC[location] = scaler_data.viewport_c.y;</div><div class='add'>+	out-&gt;ViewportWidth[location] = scaler_data-&gt;viewport.width;</div><div class='add'>+	out-&gt;ViewportHeight[location] = scaler_data-&gt;viewport.height;</div><div class='add'>+	out-&gt;ViewportWidthChroma[location] = scaler_data-&gt;viewport_c.width;</div><div class='add'>+	out-&gt;ViewportHeightChroma[location] = scaler_data-&gt;viewport_c.height;</div><div class='add'>+	out-&gt;ViewportXStart[location] = scaler_data-&gt;viewport.x;</div><div class='add'>+	out-&gt;ViewportYStart[location] = scaler_data-&gt;viewport.y;</div><div class='add'>+	out-&gt;ViewportXStartC[location] = scaler_data-&gt;viewport_c.x;</div><div class='add'>+	out-&gt;ViewportYStartC[location] = scaler_data-&gt;viewport_c.y;</div><div class='ctx'> 	out-&gt;ViewportStationary[location] = false;</div><div class='ctx'> </div><div class='del'>-	out-&gt;ScalerEnabled[location] = scaler_data.ratios.horz.value != dc_fixpt_one.value ||</div><div class='del'>-				scaler_data.ratios.horz_c.value != dc_fixpt_one.value ||</div><div class='del'>-				scaler_data.ratios.vert.value != dc_fixpt_one.value ||</div><div class='del'>-				scaler_data.ratios.vert_c.value != dc_fixpt_one.value;</div><div class='add'>+	out-&gt;ScalerEnabled[location] = scaler_data-&gt;ratios.horz.value != dc_fixpt_one.value ||</div><div class='add'>+				scaler_data-&gt;ratios.horz_c.value != dc_fixpt_one.value ||</div><div class='add'>+				scaler_data-&gt;ratios.vert.value != dc_fixpt_one.value ||</div><div class='add'>+				scaler_data-&gt;ratios.vert_c.value != dc_fixpt_one.value;</div><div class='ctx'> </div><div class='ctx'> 	/* Current driver code base uses LBBitPerPixel as 57. There is a discrepancy</div><div class='ctx'> 	 * from the HW/DML teams about this value. Initialize LBBitPerPixel with the</div><div class='hunk'>@@ -914,25 +1099,25 @@ static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out</div><div class='ctx'> 		out-&gt;VRatioChroma[location] = 1;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Follow the original dml_wrapper.c code direction to fix scaling issues */</div><div class='del'>-		out-&gt;HRatio[location] = (dml_float_t)scaler_data.ratios.horz.value / (1ULL &lt;&lt; 32);</div><div class='del'>-		out-&gt;HRatioChroma[location] = (dml_float_t)scaler_data.ratios.horz_c.value / (1ULL &lt;&lt; 32);</div><div class='del'>-		out-&gt;VRatio[location] = (dml_float_t)scaler_data.ratios.vert.value / (1ULL &lt;&lt; 32);</div><div class='del'>-		out-&gt;VRatioChroma[location] = (dml_float_t)scaler_data.ratios.vert_c.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		out-&gt;HRatio[location] = (dml_float_t)scaler_data-&gt;ratios.horz.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		out-&gt;HRatioChroma[location] = (dml_float_t)scaler_data-&gt;ratios.horz_c.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		out-&gt;VRatio[location] = (dml_float_t)scaler_data-&gt;ratios.vert.value / (1ULL &lt;&lt; 32);</div><div class='add'>+		out-&gt;VRatioChroma[location] = (dml_float_t)scaler_data-&gt;ratios.vert_c.value / (1ULL &lt;&lt; 32);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!scaler_data.taps.h_taps) {</div><div class='add'>+	if (!scaler_data-&gt;taps.h_taps) {</div><div class='ctx'> 		out-&gt;HTaps[location] = 1;</div><div class='ctx'> 		out-&gt;HTapsChroma[location] = 1;</div><div class='ctx'> 	} else {</div><div class='del'>-		out-&gt;HTaps[location] = scaler_data.taps.h_taps;</div><div class='del'>-		out-&gt;HTapsChroma[location] = scaler_data.taps.h_taps_c;</div><div class='add'>+		out-&gt;HTaps[location] = scaler_data-&gt;taps.h_taps;</div><div class='add'>+		out-&gt;HTapsChroma[location] = scaler_data-&gt;taps.h_taps_c;</div><div class='ctx'> 	}</div><div class='del'>-	if (!scaler_data.taps.v_taps) {</div><div class='add'>+	if (!scaler_data-&gt;taps.v_taps) {</div><div class='ctx'> 		out-&gt;VTaps[location] = 1;</div><div class='ctx'> 		out-&gt;VTapsChroma[location] = 1;</div><div class='ctx'> 	} else {</div><div class='del'>-		out-&gt;VTaps[location] = scaler_data.taps.v_taps;</div><div class='del'>-		out-&gt;VTapsChroma[location] = scaler_data.taps.v_taps_c;</div><div class='add'>+		out-&gt;VTaps[location] = scaler_data-&gt;taps.v_taps;</div><div class='add'>+		out-&gt;VTapsChroma[location] = scaler_data-&gt;taps.v_taps_c;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	out-&gt;SourceScan[location] = (enum dml_rotation_angle)in-&gt;rotation;</div><div class='hunk'>@@ -974,7 +1159,7 @@ static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *conte</div><div class='ctx'> 		if (context-&gt;streams[i]-&gt;stream_id == stream_id) {</div><div class='ctx'> 			for (j = 0; j &lt; context-&gt;stream_status[i].plane_count; j++) {</div><div class='ctx'> 				if (context-&gt;stream_status[i].plane_states[j] == plane &amp;&amp;</div><div class='del'>-					(!is_plane_duplicate || (is_plane_duplicate &amp;&amp; (j == plane_index)))) {</div><div class='add'>+					(!is_plane_duplicate || (j == plane_index))) {</div><div class='ctx'> 					*plane_id = (i &lt;&lt; 16) | j;</div><div class='ctx'> 					return true;</div><div class='ctx'> 				}</div><div class='hunk'>@@ -1007,22 +1192,6 @@ static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2</div><div class='ctx'> 	return location;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void apply_legacy_svp_drr_settings(struct dml2_context *dml2, const struct dc_state *state, struct dml_display_cfg_st *dml_dispcfg)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (state-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {</div><div class='del'>-		ASSERT(state-&gt;stream_count == 1);</div><div class='del'>-		dml_dispcfg-&gt;timing.DRRDisplay[0] = true;</div><div class='del'>-	} else if (state-&gt;bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid) {</div><div class='del'>-</div><div class='del'>-		for (i = 0; i &lt; dml_dispcfg-&gt;num_timings; i++) {</div><div class='del'>-			if (dml2-&gt;v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == state-&gt;streams[state-&gt;bw_ctx.bw.dcn.legacy_svp_drr_stream_index]-&gt;stream_id)</div><div class='del'>-				dml_dispcfg-&gt;timing.DRRDisplay[i] = true;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -1057,6 +1226,70 @@ static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cfg_st *out,</div><div class='add'>+		unsigned int location, const struct dc_stream_state *in)</div><div class='add'>+{</div><div class='add'>+	if (in-&gt;num_wb_info &gt; 0) {</div><div class='add'>+		for (int i = 0; i &lt; __DML_NUM_DMB__; i++) {</div><div class='add'>+			const struct dc_writeback_info *wb_info = &amp;in-&gt;writeback_info[i];</div><div class='add'>+			/*current dml support 1 dwb per stream, limitation*/</div><div class='add'>+			if (wb_info-&gt;wb_enabled) {</div><div class='add'>+				out-&gt;WritebackEnable[location] = wb_info-&gt;wb_enabled;</div><div class='add'>+				out-&gt;ActiveWritebacksPerSurface[location] = wb_info-&gt;dwb_params.cnv_params.src_width;</div><div class='add'>+				out-&gt;WritebackDestinationWidth[location] = wb_info-&gt;dwb_params.dest_width;</div><div class='add'>+				out-&gt;WritebackDestinationHeight[location] = wb_info-&gt;dwb_params.dest_height;</div><div class='add'>+</div><div class='add'>+				out-&gt;WritebackSourceWidth[location] = wb_info-&gt;dwb_params.cnv_params.crop_en ?</div><div class='add'>+					wb_info-&gt;dwb_params.cnv_params.crop_width :</div><div class='add'>+					wb_info-&gt;dwb_params.cnv_params.src_width;</div><div class='add'>+</div><div class='add'>+				out-&gt;WritebackSourceHeight[location] = wb_info-&gt;dwb_params.cnv_params.crop_en ?</div><div class='add'>+					wb_info-&gt;dwb_params.cnv_params.crop_height :</div><div class='add'>+					wb_info-&gt;dwb_params.cnv_params.src_height;</div><div class='add'>+				/*current design does not have chroma scaling, need to follow up*/</div><div class='add'>+				out-&gt;WritebackHTaps[location] = wb_info-&gt;dwb_params.scaler_taps.h_taps &gt; 0 ?</div><div class='add'>+					wb_info-&gt;dwb_params.scaler_taps.h_taps : 1;</div><div class='add'>+				out-&gt;WritebackVTaps[location] = wb_info-&gt;dwb_params.scaler_taps.v_taps &gt; 0 ?</div><div class='add'>+					wb_info-&gt;dwb_params.scaler_taps.v_taps : 1;</div><div class='add'>+</div><div class='add'>+				out-&gt;WritebackHRatio[location] = wb_info-&gt;dwb_params.cnv_params.crop_en ?</div><div class='add'>+					(double)wb_info-&gt;dwb_params.cnv_params.crop_width /</div><div class='add'>+						(double)wb_info-&gt;dwb_params.dest_width :</div><div class='add'>+					(double)wb_info-&gt;dwb_params.cnv_params.src_width /</div><div class='add'>+						(double)wb_info-&gt;dwb_params.dest_width;</div><div class='add'>+				out-&gt;WritebackVRatio[location] = wb_info-&gt;dwb_params.cnv_params.crop_en ?</div><div class='add'>+					(double)wb_info-&gt;dwb_params.cnv_params.crop_height /</div><div class='add'>+						(double)wb_info-&gt;dwb_params.dest_height :</div><div class='add'>+					(double)wb_info-&gt;dwb_params.cnv_params.src_height /</div><div class='add'>+						(double)wb_info-&gt;dwb_params.dest_height;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct dml2_context *dml2, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct pipe_ctx *current_pipe_context;</div><div class='add'>+</div><div class='add'>+	/* Scratch gets reset to zero in dml, but link encoder instance can be zero, so reset to -1 */</div><div class='add'>+	for (i = 0; i &lt; MAX_HPO_DP2_ENCODERS; i++) {</div><div class='add'>+		dml2-&gt;v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If an HPO stream encoder is allocated to a pipe, get the instance of it's allocated HPO Link encoder */</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		current_pipe_context = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (current_pipe_context-&gt;stream &amp;&amp;</div><div class='add'>+			current_pipe_context-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='add'>+			current_pipe_context-&gt;link_res.hpo_dp_link_enc &amp;&amp;</div><div class='add'>+			dc_is_dp_signal(current_pipe_context-&gt;stream-&gt;signal)) {</div><div class='add'>+				dml2-&gt;v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context-&gt;stream_res.hpo_dp_stream_enc-&gt;inst] =</div><div class='add'>+					current_pipe_context-&gt;link_res.hpo_dp_link_enc-&gt;inst;</div><div class='add'>+			}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)</div><div class='ctx'> {</div><div class='ctx'> 	int i = 0, j = 0, k = 0;</div><div class='hunk'>@@ -1080,6 +1313,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 		dml2-&gt;v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;</div><div class='ctx'> </div><div class='ctx'> 	dml2_populate_pipe_to_plane_index_mapping(dml2, context);</div><div class='add'>+	dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(dml2, context);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		current_pipe_context = NULL;</div><div class='hunk'>@@ -1097,10 +1331,14 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 		if (disp_cfg_stream_location &lt; 0)</div><div class='ctx'> 			disp_cfg_stream_location = dml_dispcfg-&gt;num_timings++;</div><div class='ctx'> </div><div class='del'>-		ASSERT(disp_cfg_stream_location &gt;= 0 &amp;&amp; disp_cfg_stream_location &lt;= __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='add'>+		ASSERT(disp_cfg_stream_location &gt;= 0 &amp;&amp; disp_cfg_stream_location &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='ctx'> </div><div class='ctx'> 		populate_dml_timing_cfg_from_stream_state(&amp;dml_dispcfg-&gt;timing, disp_cfg_stream_location, context-&gt;streams[i]);</div><div class='del'>-		populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_stream_location, context-&gt;streams[i], current_pipe_context);</div><div class='add'>+		populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_stream_location, context-&gt;streams[i], current_pipe_context, dml2);</div><div class='add'>+		/*Call site for populate_dml_writeback_cfg_from_stream_state*/</div><div class='add'>+		populate_dml_writeback_cfg_from_stream_state(&amp;dml_dispcfg-&gt;writeback,</div><div class='add'>+			disp_cfg_stream_location, context-&gt;streams[i]);</div><div class='add'>+</div><div class='ctx'> 		switch (context-&gt;streams[i]-&gt;debug.force_odm_combine_segments) {</div><div class='ctx'> 		case 2:</div><div class='ctx'> 			dml2-&gt;v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;</div><div class='hunk'>@@ -1119,7 +1357,8 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 			disp_cfg_plane_location = dml_dispcfg-&gt;num_surfaces++;</div><div class='ctx'> </div><div class='ctx'> 			populate_dummy_dml_surface_cfg(&amp;dml_dispcfg-&gt;surface, disp_cfg_plane_location, context-&gt;streams[i]);</div><div class='del'>-			populate_dummy_dml_plane_cfg(&amp;dml_dispcfg-&gt;plane, disp_cfg_plane_location, context-&gt;streams[i]);</div><div class='add'>+			populate_dummy_dml_plane_cfg(&amp;dml_dispcfg-&gt;plane, disp_cfg_plane_location,</div><div class='add'>+						     context-&gt;streams[i], &amp;dml2-&gt;v20.dml_core_ctx.soc);</div><div class='ctx'> </div><div class='ctx'> 			dml_dispcfg-&gt;plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;</div><div class='ctx'> </div><div class='hunk'>@@ -1132,10 +1371,13 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 				if (disp_cfg_plane_location &lt; 0)</div><div class='ctx'> 					disp_cfg_plane_location = dml_dispcfg-&gt;num_surfaces++;</div><div class='ctx'> </div><div class='del'>-				ASSERT(disp_cfg_plane_location &gt;= 0 &amp;&amp; disp_cfg_plane_location &lt;= __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='add'>+				ASSERT(disp_cfg_plane_location &gt;= 0 &amp;&amp; disp_cfg_plane_location &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='ctx'> </div><div class='ctx'> 				populate_dml_surface_cfg_from_plane_state(dml2-&gt;v20.dml_core_ctx.project, &amp;dml_dispcfg-&gt;surface, disp_cfg_plane_location, context-&gt;stream_status[i].plane_states[j]);</div><div class='del'>-				populate_dml_plane_cfg_from_plane_state(&amp;dml_dispcfg-&gt;plane, disp_cfg_plane_location, context-&gt;stream_status[i].plane_states[j], context);</div><div class='add'>+				populate_dml_plane_cfg_from_plane_state(</div><div class='add'>+					&amp;dml_dispcfg-&gt;plane, disp_cfg_plane_location,</div><div class='add'>+					context-&gt;stream_status[i].plane_states[j], context,</div><div class='add'>+					&amp;dml2-&gt;v20.dml_core_ctx.soc);</div><div class='ctx'> </div><div class='ctx'> 				if (stream_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 					dml_dispcfg-&gt;plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;</div><div class='hunk'>@@ -1157,7 +1399,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> </div><div class='ctx'> 				if (j &gt;= 1) {</div><div class='ctx'> 					populate_dml_timing_cfg_from_stream_state(&amp;dml_dispcfg-&gt;timing, disp_cfg_plane_location, context-&gt;streams[i]);</div><div class='del'>-					populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_plane_location, context-&gt;streams[i], current_pipe_context);</div><div class='add'>+					populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_plane_location, context-&gt;streams[i], current_pipe_context, dml2);</div><div class='ctx'> 					switch (context-&gt;streams[i]-&gt;debug.force_odm_combine_segments) {</div><div class='ctx'> 					case 2:</div><div class='ctx'> 						dml2-&gt;v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1;</div><div class='hunk'>@@ -1182,9 +1424,6 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	if (!dml2-&gt;config.use_native_pstate_optimization)</div><div class='del'>-		apply_legacy_svp_drr_settings(dml2, context, dml_dispcfg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h<br/>index d764773938f4..d764773938f4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c<br/>index f15d1dbad6a9..9a33158b63bf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c</a></div><div class='hunk'>@@ -161,14 +161,6 @@ bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	/* If this assert is hit then we have a link encoder dynamic management issue */</div><div class='ctx'> 	ASSERT(pipe_ctx-&gt;stream_res.hpo_dp_stream_enc ? pipe_ctx-&gt;link_res.hpo_dp_link_enc != NULL : true);</div><div class='ctx'> </div><div class='del'>-	/* Count MST hubs once by treating only 1st remote sink in topology as an encoder */</div><div class='del'>-	if (pipe_ctx-&gt;stream-&gt;link &amp;&amp; pipe_ctx-&gt;stream-&gt;link-&gt;remote_sinks[0]) {</div><div class='del'>-		return (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='del'>-			pipe_ctx-&gt;link_res.hpo_dp_link_enc &amp;&amp;</div><div class='del'>-			dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp;</div><div class='del'>-			(pipe_ctx-&gt;stream-&gt;link-&gt;remote_sinks[0]-&gt;sink_id == pipe_ctx-&gt;stream-&gt;sink-&gt;sink_id));</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='ctx'> 		pipe_ctx-&gt;link_res.hpo_dp_link_enc &amp;&amp;</div><div class='ctx'> 		dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal));</div><div class='hunk'>@@ -224,7 +216,7 @@ static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int</div><div class='ctx'> static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane,</div><div class='ctx'> 	unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)</div><div class='ctx'> {</div><div class='del'>-	int i, j;</div><div class='add'>+	unsigned int i, j;</div><div class='ctx'> 	bool is_plane_duplicate = dml2-&gt;v20.scratch.plane_duplicate_exists;</div><div class='ctx'> </div><div class='ctx'> 	if (!plane_id)</div><div class='hunk'>@@ -288,13 +280,12 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id;</div><div class='ctx'> 	enum mall_stream_type pipe_mall_type;</div><div class='del'>-	bool unbounded_req_enabled = false;</div><div class='ctx'> 	struct dml2_calculate_rq_and_dlg_params_scratch *s = &amp;in_ctx-&gt;v20.scratch.calculate_rq_and_dlg_params_scratch;</div><div class='ctx'> </div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx-&gt;v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.dppclk_khz = 0;</div><div class='ctx'> </div><div class='del'>-	if (in_ctx-&gt;v20.dml_core_ctx.ms.support.FCLKChangeSupport[in_ctx-&gt;v20.scratch.mode_support_params.out_lowest_state_idx] == dml_fclock_change_unsupported)</div><div class='add'>+	if (in_ctx-&gt;v20.dml_core_ctx.ms.support.FCLKChangeSupport[0] == dml_fclock_change_unsupported)</div><div class='ctx'> 		context-&gt;bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;</div><div class='ctx'> 	else</div><div class='ctx'> 		context-&gt;bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;</div><div class='hunk'>@@ -302,14 +293,6 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> 	if (context-&gt;bw_ctx.bw.dcn.clk.dispclk_khz &lt; dc-&gt;debug.min_disp_clk_khz)</div><div class='ctx'> 		context-&gt;bw_ctx.bw.dcn.clk.dispclk_khz = dc-&gt;debug.min_disp_clk_khz;</div><div class='ctx'> </div><div class='del'>-	unbounded_req_enabled = in_ctx-&gt;v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;</div><div class='del'>-</div><div class='del'>-	if (unbounded_req_enabled &amp;&amp; pipe_cnt &gt; 1) {</div><div class='del'>-		// Unbounded requesting should not ever be used when more than 1 pipe is enabled.</div><div class='del'>-		//ASSERT(false);</div><div class='del'>-		unbounded_req_enabled = false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.compbuf_size_kb = in_ctx-&gt;v20.dml_core_ctx.ip.config_return_buffer_size_in_kbytes;</div><div class='ctx'> </div><div class='ctx'> 	for (dc_pipe_ctx_index = 0; dc_pipe_ctx_index &lt; pipe_cnt; dc_pipe_ctx_index++) {</div><div class='hunk'>@@ -327,6 +310,8 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> 			dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].stream-&gt;stream_id);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (dml_pipe_idx == 0xFFFFFFFF)</div><div class='add'>+			continue;</div><div class='ctx'> 		ASSERT(in_ctx-&gt;v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]);</div><div class='ctx'> 		ASSERT(in_ctx-&gt;v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].stream-&gt;stream_id);</div><div class='ctx'> </div><div class='hunk'>@@ -342,7 +327,8 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&amp;context-&gt;bw_ctx.dml2-&gt;v20.dml_core_ctx, dml_pipe_idx);</div><div class='del'>-			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = unbounded_req_enabled;</div><div class='add'>+			// Unbounded requesting should not ever be used when more than 1 pipe is enabled.</div><div class='add'>+			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = in_ctx-&gt;v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		context-&gt;bw_ctx.bw.dcn.compbuf_size_kb -= context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;</div><div class='hunk'>@@ -374,10 +360,16 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> </div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.bw_dppclk_khz = context-&gt;bw_ctx.bw.dcn.clk.dppclk_khz;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.bw_dispclk_khz = context-&gt;bw_ctx.bw.dcn.clk.dispclk_khz;</div><div class='add'>+</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx-&gt;v20.dml_core_ctx.states.state_array[in_ctx-&gt;v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz</div><div class='ctx'> 		* 1000;</div><div class='ctx'> 	context-&gt;bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx-&gt;v20.dml_core_ctx.states.state_array[in_ctx-&gt;v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz</div><div class='ctx'> 		* 1000;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;config.forced_clocks || dc-&gt;debug.max_disp_clk) {</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.bw_dispclk_khz = context-&gt;bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.bw_dppclk_khz = context-&gt;bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx)</div><div class='hunk'>@@ -396,6 +388,71 @@ void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display</div><div class='ctx'> 	watermark-&gt;cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+unsigned int dml2_calc_max_scaled_time(</div><div class='add'>+		unsigned int time_per_pixel,</div><div class='add'>+		enum mmhubbub_wbif_mode mode,</div><div class='add'>+		unsigned int urgent_watermark)</div><div class='add'>+{</div><div class='add'>+	unsigned int time_per_byte = 0;</div><div class='add'>+	unsigned int total_free_entry = 0xb40;</div><div class='add'>+	unsigned int buf_lh_capability;</div><div class='add'>+	unsigned int max_scaled_time;</div><div class='add'>+</div><div class='add'>+	if (mode == PACKED_444) /* packed mode 32 bpp */</div><div class='add'>+		time_per_byte = time_per_pixel/4;</div><div class='add'>+	else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */</div><div class='add'>+		time_per_byte = time_per_pixel/8;</div><div class='add'>+</div><div class='add'>+	if (time_per_byte == 0)</div><div class='add'>+		time_per_byte = 1;</div><div class='add'>+</div><div class='add'>+	buf_lh_capability = (total_free_entry*time_per_byte*32) &gt;&gt; 6; /* time_per_byte is in u6.6*/</div><div class='add'>+	max_scaled_time   = buf_lh_capability - urgent_watermark;</div><div class='add'>+	return max_scaled_time;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx)</div><div class='add'>+{</div><div class='add'>+	int i, j = 0;</div><div class='add'>+	struct mcif_arb_params *wb_arb_params = NULL;</div><div class='add'>+	struct dcn_bw_writeback *bw_writeback = NULL;</div><div class='add'>+	enum mmhubbub_wbif_mode wbif_mode = PACKED_444_FP16; /*for now*/</div><div class='add'>+</div><div class='add'>+	if (context-&gt;stream_count != 0) {</div><div class='add'>+		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+			if (context-&gt;streams[i]-&gt;num_wb_info != 0)</div><div class='add'>+				j++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	if (j == 0) /*no dwb */</div><div class='add'>+		return;</div><div class='add'>+	for (i = 0; i &lt; __DML_NUM_DMB__; i++) {</div><div class='add'>+		bw_writeback = &amp;context-&gt;bw_ctx.bw.dcn.bw_writeback;</div><div class='add'>+		wb_arb_params = &amp;context-&gt;bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[i];</div><div class='add'>+</div><div class='add'>+		for (j = 0 ; j &lt; 4; j++) {</div><div class='add'>+			/*current dml only has one set of watermark, need to follow up*/</div><div class='add'>+			bw_writeback-&gt;mcif_wb_arb[i].cli_watermark[j] =</div><div class='add'>+					dml_get_wm_writeback_urgent(dml_core_ctx) * 1000;</div><div class='add'>+			bw_writeback-&gt;mcif_wb_arb[i].pstate_watermark[j] =</div><div class='add'>+					dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;</div><div class='add'>+		}</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].stream-&gt;phy_pix_clk != 0) {</div><div class='add'>+			/* time_per_pixel should be in u6.6 format */</div><div class='add'>+			bw_writeback-&gt;mcif_wb_arb[i].time_per_pixel =</div><div class='add'>+				(1000000 &lt;&lt; 6) / context-&gt;res_ctx.pipe_ctx[i].stream-&gt;phy_pix_clk;</div><div class='add'>+		}</div><div class='add'>+		bw_writeback-&gt;mcif_wb_arb[i].slice_lines = 32;</div><div class='add'>+		bw_writeback-&gt;mcif_wb_arb[i].arbitration_slice = 2;</div><div class='add'>+		bw_writeback-&gt;mcif_wb_arb[i].max_scaled_time =</div><div class='add'>+			dml2_calc_max_scaled_time(wb_arb_params-&gt;time_per_pixel,</div><div class='add'>+					wbif_mode, 	wb_arb_params-&gt;cli_watermark[0]);</div><div class='add'>+		/*not required any more*/</div><div class='add'>+		bw_writeback-&gt;mcif_wb_arb[i].dram_speed_change_duration =</div><div class='add'>+			dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> void dml2_initialize_det_scratch(struct dml2_context *in_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -468,6 +525,9 @@ bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc</div><div class='ctx'> 			dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id);</div><div class='ctx'> 		else</div><div class='ctx'> 			dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state-&gt;res_ctx.pipe_ctx[i].stream-&gt;stream_id);</div><div class='add'>+</div><div class='add'>+		if (dml_pipe_idx == 0xFFFFFFFF)</div><div class='add'>+			continue;</div><div class='ctx'> 		total_det_allocated += dml_get_det_buffer_size_kbytes(&amp;in_ctx-&gt;v20.dml_core_ctx, dml_pipe_idx);</div><div class='ctx'> 		if (total_det_allocated &gt; max_det_size) {</div><div class='ctx'> 			need_recalculation = true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h<br/>index 5842d6d3c4b6..04fcfe637119 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h</a></div><div class='hunk'>@@ -40,9 +40,14 @@ void dml2_util_copy_dml_output(struct dml_output_cfg_st *dml_output_array, unsig</div><div class='ctx'> unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, enum dml_output_encoder_class encoder, bool dsc_enabled);</div><div class='ctx'> void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context);</div><div class='ctx'> void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx);</div><div class='add'>+void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib_st *dml_core_ctx);</div><div class='ctx'> int dml2_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id);</div><div class='ctx'> bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);</div><div class='ctx'> bool dml2_is_stereo_timing(const struct dc_stream_state *stream);</div><div class='add'>+unsigned int dml2_calc_max_scaled_time(</div><div class='add'>+		unsigned int time_per_pixel,</div><div class='add'>+		enum mmhubbub_wbif_mode mode,</div><div class='add'>+		unsigned int urgent_watermark);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * dml2_dc_construct_pipes - This function will determine if we need additional pipes based</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c<br/>index 72cca367062e..9deb03a18ccc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c</a></div><div class='hunk'>@@ -31,7 +31,7 @@</div><div class='ctx'> #include "dml2_translation_helper.h"</div><div class='ctx'> #include "dml2_mall_phantom.h"</div><div class='ctx'> #include "dml2_dc_resource_mgmt.h"</div><div class='del'>-</div><div class='add'>+#include "dml21_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> static void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)</div><div class='ctx'> {</div><div class='hunk'>@@ -71,6 +71,7 @@ static void map_hw_resources(struct dml2_context *dml2,</div><div class='ctx'> 		in_out_display_cfg-&gt;hw.NumberOfDSCSlices[i] = mode_support_info-&gt;NumberOfDSCSlices[i];</div><div class='ctx'> 		in_out_display_cfg-&gt;hw.DLGRefClkFreqMHz = 24;</div><div class='ctx'> 		if (dml2-&gt;v20.dml_core_ctx.project != dml_project_dcn35 &amp;&amp;</div><div class='add'>+			dml2-&gt;v20.dml_core_ctx.project != dml_project_dcn36 &amp;&amp;</div><div class='ctx'> 			dml2-&gt;v20.dml_core_ctx.project != dml_project_dcn351) {</div><div class='ctx'> 			/*dGPU default as 50Mhz*/</div><div class='ctx'> 			in_out_display_cfg-&gt;hw.DLGRefClkFreqMHz = 50;</div><div class='hunk'>@@ -92,12 +93,17 @@ static void map_hw_resources(struct dml2_context *dml2,</div><div class='ctx'> </div><div class='ctx'> static unsigned int pack_and_call_dml_mode_support_ex(struct dml2_context *dml2,</div><div class='ctx'> 	const struct dml_display_cfg_st *display_cfg,</div><div class='del'>-	struct dml_mode_support_info_st *evaluation_info)</div><div class='add'>+	struct dml_mode_support_info_st *evaluation_info,</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dml2_wrapper_scratch *s = &amp;dml2-&gt;v20.scratch;</div><div class='ctx'> </div><div class='ctx'> 	s-&gt;mode_support_params.mode_lib = &amp;dml2-&gt;v20.dml_core_ctx;</div><div class='ctx'> 	s-&gt;mode_support_params.in_display_cfg = display_cfg;</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_ONLY)</div><div class='add'>+		s-&gt;mode_support_params.in_start_state_idx = dml2-&gt;v20.dml_core_ctx.states.num_states - 1;</div><div class='add'>+	else</div><div class='add'>+		s-&gt;mode_support_params.in_start_state_idx = 0;</div><div class='ctx'> 	s-&gt;mode_support_params.out_evaluation_info = evaluation_info;</div><div class='ctx'> </div><div class='ctx'> 	memset(evaluation_info, 0, sizeof(struct dml_mode_support_info_st));</div><div class='hunk'>@@ -109,10 +115,8 @@ static unsigned int pack_and_call_dml_mode_support_ex(struct dml2_context *dml2,</div><div class='ctx'> static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrapper_optimize_configuration_params *p)</div><div class='ctx'> {</div><div class='ctx'> 	int unused_dpps = p-&gt;ip_params-&gt;max_num_dpp;</div><div class='del'>-	int i, j;</div><div class='del'>-	int odms_needed, refresh_rate_hz, dpps_needed, subvp_height, pstate_width_fw_delay_lines, surface_count;</div><div class='del'>-	int subvp_timing_to_add, new_timing_index, subvp_surface_to_add, new_surface_index;</div><div class='del'>-	float frame_time_sec, max_frame_time_sec;</div><div class='add'>+	int i;</div><div class='add'>+	int odms_needed;</div><div class='ctx'> 	int largest_blend_and_timing = 0;</div><div class='ctx'> 	bool optimization_done = false;</div><div class='ctx'> </div><div class='hunk'>@@ -127,79 +131,6 @@ static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrappe</div><div class='ctx'> 	if (p-&gt;new_display_config != p-&gt;cur_display_config)</div><div class='ctx'> 		*p-&gt;new_display_config = *p-&gt;cur_display_config;</div><div class='ctx'> </div><div class='del'>-	// Optimize P-State Support</div><div class='del'>-	if (dml2-&gt;config.use_native_pstate_optimization) {</div><div class='del'>-		if (p-&gt;cur_mode_support_info-&gt;DRAMClockChangeSupport[0] == dml_dram_clock_change_unsupported) {</div><div class='del'>-			// Find a display with &lt; 120Hz refresh rate with maximal refresh rate that's not already subvp</div><div class='del'>-			subvp_timing_to_add = -1;</div><div class='del'>-			subvp_surface_to_add = -1;</div><div class='del'>-			max_frame_time_sec = 0;</div><div class='del'>-			surface_count = 0;</div><div class='del'>-			for (i = 0; i &lt; (int) p-&gt;cur_display_config-&gt;num_timings; i++) {</div><div class='del'>-				refresh_rate_hz = (int)div_u64((unsigned long long) p-&gt;cur_display_config-&gt;timing.PixelClock[i] * 1000 * 1000,</div><div class='del'>-					(p-&gt;cur_display_config-&gt;timing.HTotal[i] * p-&gt;cur_display_config-&gt;timing.VTotal[i]));</div><div class='del'>-				if (refresh_rate_hz &lt; 120) {</div><div class='del'>-					// Check its upstream surfaces to see if this one could be converted to subvp.</div><div class='del'>-					dpps_needed = 0;</div><div class='del'>-				for (j = 0; j &lt; (int) p-&gt;cur_display_config-&gt;num_surfaces; j++) {</div><div class='del'>-					if (p-&gt;cur_display_config-&gt;plane.BlendingAndTiming[j] == i &amp;&amp;</div><div class='del'>-						p-&gt;cur_display_config-&gt;plane.UseMALLForPStateChange[j] == dml_use_mall_pstate_change_disable) {</div><div class='del'>-						dpps_needed += p-&gt;cur_mode_support_info-&gt;DPPPerSurface[j];</div><div class='del'>-						subvp_surface_to_add = j;</div><div class='del'>-						surface_count++;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-</div><div class='del'>-				if (surface_count == 1 &amp;&amp; dpps_needed &gt; 0 &amp;&amp; dpps_needed &lt;= unused_dpps) {</div><div class='del'>-					frame_time_sec = (float)1 / refresh_rate_hz;</div><div class='del'>-					if (frame_time_sec &gt; max_frame_time_sec) {</div><div class='del'>-						max_frame_time_sec = frame_time_sec;</div><div class='del'>-						subvp_timing_to_add = i;</div><div class='del'>-						}</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-			if (subvp_timing_to_add &gt;= 0) {</div><div class='del'>-				new_timing_index = p-&gt;new_display_config-&gt;num_timings++;</div><div class='del'>-				new_surface_index = p-&gt;new_display_config-&gt;num_surfaces++;</div><div class='del'>-				// Add a phantom pipe reflecting the main pipe's timing</div><div class='del'>-				dml2_util_copy_dml_timing(&amp;p-&gt;new_display_config-&gt;timing, new_timing_index, subvp_timing_to_add);</div><div class='del'>-</div><div class='del'>-				pstate_width_fw_delay_lines = (int)(((double)(p-&gt;config-&gt;svp_pstate.subvp_fw_processing_delay_us +</div><div class='del'>-					p-&gt;config-&gt;svp_pstate.subvp_pstate_allow_width_us) / 1000000) *</div><div class='del'>-				(p-&gt;new_display_config-&gt;timing.PixelClock[subvp_timing_to_add] * 1000 * 1000) /</div><div class='del'>-				(double)p-&gt;new_display_config-&gt;timing.HTotal[subvp_timing_to_add]);</div><div class='del'>-</div><div class='del'>-				subvp_height = p-&gt;cur_mode_support_info-&gt;SubViewportLinesNeededInMALL[subvp_timing_to_add] + pstate_width_fw_delay_lines;</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;timing.VActive[new_timing_index] = subvp_height;</div><div class='del'>-				p-&gt;new_display_config-&gt;timing.VTotal[new_timing_index] = subvp_height +</div><div class='del'>-				p-&gt;new_display_config-&gt;timing.VTotal[subvp_timing_to_add] - p-&gt;new_display_config-&gt;timing.VActive[subvp_timing_to_add];</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;output.OutputDisabled[new_timing_index] = true;</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.UseMALLForPStateChange[subvp_surface_to_add] = dml_use_mall_pstate_change_sub_viewport;</div><div class='del'>-</div><div class='del'>-				dml2_util_copy_dml_plane(&amp;p-&gt;new_display_config-&gt;plane, new_surface_index, subvp_surface_to_add);</div><div class='del'>-				dml2_util_copy_dml_surface(&amp;p-&gt;new_display_config-&gt;surface, new_surface_index, subvp_surface_to_add);</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.ViewportHeight[new_surface_index] = subvp_height;</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.ViewportHeightChroma[new_surface_index] = subvp_height;</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.ViewportStationary[new_surface_index] = false;</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.UseMALLForStaticScreen[new_surface_index] = dml_use_mall_static_screen_disable;</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.UseMALLForPStateChange[new_surface_index] = dml_use_mall_pstate_change_phantom_pipe;</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.NumberOfCursors[new_surface_index] = 0;</div><div class='del'>-</div><div class='del'>-				p-&gt;new_policy-&gt;ImmediateFlipRequirement[new_surface_index] = dml_immediate_flip_not_required;</div><div class='del'>-</div><div class='del'>-				p-&gt;new_display_config-&gt;plane.BlendingAndTiming[new_surface_index] = new_timing_index;</div><div class='del'>-</div><div class='del'>-				optimization_done = true;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	// Optimize Clocks</div><div class='ctx'> 	if (!optimization_done) {</div><div class='hunk'>@@ -208,8 +139,6 @@ static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrappe</div><div class='ctx'> 				p-&gt;cur_display_config-&gt;output.OutputEncoder[0], p-&gt;cur_mode_support_info-&gt;DSCEnabled[0]) - 1;</div><div class='ctx'> </div><div class='ctx'> 			if (odms_needed &lt;= unused_dpps) {</div><div class='del'>-				unused_dpps -= odms_needed;</div><div class='del'>-</div><div class='ctx'> 				if (odms_needed == 1) {</div><div class='ctx'> 					p-&gt;new_policy-&gt;ODMUse[0] = dml_odm_use_policy_combine_2to1;</div><div class='ctx'> 					optimization_done = true;</div><div class='hunk'>@@ -225,7 +154,8 @@ static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrappe</div><div class='ctx'> 	return optimization_done;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state)</div><div class='add'>+static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &amp;dml2-&gt;v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch;</div><div class='ctx'> 	struct dml2_wrapper_scratch *s_global = &amp;dml2-&gt;v20.scratch;</div><div class='hunk'>@@ -267,7 +197,8 @@ static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *d</div><div class='ctx'> 			dml2-&gt;v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global-&gt;dummy_pstate_table[i].dummy_pstate_latency_us;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		dml_result = pack_and_call_dml_mode_support_ex(dml2, &amp;s-&gt;cur_display_config, &amp;s-&gt;evaluation_info);</div><div class='add'>+		dml_result = pack_and_call_dml_mode_support_ex(dml2, &amp;s-&gt;cur_display_config, &amp;s-&gt;evaluation_info,</div><div class='add'>+						validate_mode);</div><div class='ctx'> </div><div class='ctx'> 		if (dml_result &amp;&amp; s-&gt;evaluation_info.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive) {</div><div class='ctx'> 			map_hw_resources(dml2, &amp;s-&gt;cur_display_config, &amp;s-&gt;evaluation_info);</div><div class='hunk'>@@ -332,7 +263,8 @@ static bool does_configuration_meet_sw_policies(struct dml2_context *ctx, const</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool dml_mode_support_wrapper(struct dml2_context *dml2,</div><div class='del'>-		struct dc_state *display_state)</div><div class='add'>+		struct dc_state *display_state,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dml2_wrapper_scratch *s = &amp;dml2-&gt;v20.scratch;</div><div class='ctx'> 	unsigned int result = 0, i;</div><div class='hunk'>@@ -368,7 +300,8 @@ static bool dml_mode_support_wrapper(struct dml2_context *dml2,</div><div class='ctx'> </div><div class='ctx'> 	result = pack_and_call_dml_mode_support_ex(dml2,</div><div class='ctx'> 		&amp;s-&gt;cur_display_config,</div><div class='del'>-		&amp;s-&gt;mode_support_info);</div><div class='add'>+		&amp;s-&gt;mode_support_info,</div><div class='add'>+		validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	if (result)</div><div class='ctx'> 		result = does_configuration_meet_sw_policies(dml2, &amp;s-&gt;cur_display_config, &amp;s-&gt;mode_support_info);</div><div class='hunk'>@@ -389,7 +322,8 @@ static bool dml_mode_support_wrapper(struct dml2_context *dml2,</div><div class='ctx'> 			dml2-&gt;v20.dml_core_ctx.policy = s-&gt;new_policy;</div><div class='ctx'> 			optimized_result = pack_and_call_dml_mode_support_ex(dml2,</div><div class='ctx'> 				&amp;s-&gt;new_display_config,</div><div class='del'>-				&amp;s-&gt;mode_support_info);</div><div class='add'>+				&amp;s-&gt;mode_support_info,</div><div class='add'>+				validate_mode);</div><div class='ctx'> </div><div class='ctx'> 			if (optimized_result)</div><div class='ctx'> 				optimized_result = does_configuration_meet_sw_policies(dml2, &amp;s-&gt;new_display_config, &amp;s-&gt;mode_support_info);</div><div class='hunk'>@@ -408,7 +342,8 @@ static bool dml_mode_support_wrapper(struct dml2_context *dml2,</div><div class='ctx'> 		if (!optimized_result) {</div><div class='ctx'> 			result = pack_and_call_dml_mode_support_ex(dml2,</div><div class='ctx'> 				&amp;s-&gt;cur_display_config,</div><div class='del'>-				&amp;s-&gt;mode_support_info);</div><div class='add'>+				&amp;s-&gt;mode_support_info,</div><div class='add'>+				validate_mode);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -418,161 +353,73 @@ static bool dml_mode_support_wrapper(struct dml2_context *dml2,</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int find_drr_eligible_stream(struct dc_state *display_state)</div><div class='add'>+static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; display_state-&gt;stream_count; i++) {</div><div class='del'>-		if (dc_state_get_stream_subvp_type(display_state, display_state-&gt;streams[i]) == SUBVP_NONE</div><div class='del'>-			&amp;&amp; display_state-&gt;streams[i]-&gt;ignore_msa_timing_param) {</div><div class='del'>-			// Use ignore_msa_timing_param flag to identify as DRR</div><div class='del'>-			return i;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool optimize_pstate_with_svp_and_drr(struct dml2_context *dml2, struct dc_state *display_state)</div><div class='del'>-{</div><div class='del'>-	struct dml2_wrapper_scratch *s = &amp;dml2-&gt;v20.scratch;</div><div class='del'>-	bool pstate_optimization_done = false;</div><div class='del'>-	bool pstate_optimization_success = false;</div><div class='del'>-	bool result = false;</div><div class='del'>-	int drr_display_index = 0, non_svp_streams = 0;</div><div class='del'>-	bool force_svp = dml2-&gt;config.svp_pstate.force_enable_subvp;</div><div class='del'>-	bool advanced_pstate_switching = false;</div><div class='del'>-</div><div class='del'>-	display_state-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;</div><div class='del'>-	display_state-&gt;bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false;</div><div class='del'>-</div><div class='del'>-	result = dml_mode_support_wrapper(dml2, display_state);</div><div class='del'>-</div><div class='del'>-	if (!result) {</div><div class='del'>-		pstate_optimization_done = true;</div><div class='del'>-	} else if (!advanced_pstate_switching ||</div><div class='del'>-		(s-&gt;mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported &amp;&amp; !force_svp)) {</div><div class='del'>-		pstate_optimization_success = true;</div><div class='del'>-		pstate_optimization_done = true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (display_state-&gt;stream_count == 1 &amp;&amp; dml2-&gt;config.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch(dml2-&gt;config.callbacks.dc, display_state)) {</div><div class='del'>-			display_state-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;</div><div class='del'>-</div><div class='del'>-			result = dml_mode_support_wrapper(dml2, display_state);</div><div class='del'>-	} else {</div><div class='del'>-		non_svp_streams = display_state-&gt;stream_count;</div><div class='del'>-</div><div class='del'>-		while (!pstate_optimization_done) {</div><div class='del'>-			result = dml_mode_programming(&amp;dml2-&gt;v20.dml_core_ctx, s-&gt;mode_support_params.out_lowest_state_idx, &amp;s-&gt;cur_display_config, true);</div><div class='del'>-</div><div class='del'>-			// Always try adding SVP first</div><div class='del'>-			if (result)</div><div class='del'>-				result = dml2_svp_add_phantom_pipe_to_dc_state(dml2, display_state, &amp;s-&gt;mode_support_info);</div><div class='del'>-			else</div><div class='del'>-				pstate_optimization_done = true;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-			if (result) {</div><div class='del'>-				result = dml_mode_support_wrapper(dml2, display_state);</div><div class='del'>-			} else {</div><div class='del'>-				pstate_optimization_done = true;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (result) {</div><div class='del'>-				non_svp_streams--;</div><div class='del'>-</div><div class='del'>-				if (s-&gt;mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported) {</div><div class='del'>-					if (dml2_svp_validate_static_schedulability(dml2, display_state, s-&gt;mode_support_info.DRAMClockChangeSupport[0])) {</div><div class='del'>-						pstate_optimization_success = true;</div><div class='del'>-						pstate_optimization_done = true;</div><div class='del'>-					} else {</div><div class='del'>-						pstate_optimization_success = false;</div><div class='del'>-						pstate_optimization_done = false;</div><div class='del'>-					}</div><div class='del'>-				} else {</div><div class='del'>-					drr_display_index = find_drr_eligible_stream(display_state);</div><div class='del'>-</div><div class='del'>-					// If there is only 1 remaining non SubVP pipe that is DRR, check static</div><div class='del'>-					// schedulability for SubVP + DRR.</div><div class='del'>-					if (non_svp_streams == 1 &amp;&amp; drr_display_index &gt;= 0) {</div><div class='del'>-						if (dml2_svp_drr_schedulable(dml2, display_state, &amp;display_state-&gt;streams[drr_display_index]-&gt;timing)) {</div><div class='del'>-							display_state-&gt;bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = true;</div><div class='del'>-							display_state-&gt;bw_ctx.bw.dcn.legacy_svp_drr_stream_index = drr_display_index;</div><div class='del'>-							result = dml_mode_support_wrapper(dml2, display_state);</div><div class='del'>-						}</div><div class='del'>-</div><div class='del'>-						if (result &amp;&amp; s-&gt;mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported) {</div><div class='del'>-							pstate_optimization_success = true;</div><div class='del'>-							pstate_optimization_done = true;</div><div class='del'>-						} else {</div><div class='del'>-							pstate_optimization_success = false;</div><div class='del'>-							pstate_optimization_done = false;</div><div class='del'>-						}</div><div class='del'>-					}</div><div class='del'>-</div><div class='del'>-					if (pstate_optimization_success) {</div><div class='del'>-						pstate_optimization_done = true;</div><div class='del'>-					} else {</div><div class='del'>-						pstate_optimization_done = false;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	unsigned int result = 0;</div><div class='add'>+	unsigned int min_state = 0;</div><div class='add'>+	int min_state_for_g6_temp_read = 0;</div><div class='ctx'> </div><div class='del'>-	if (!pstate_optimization_success) {</div><div class='del'>-		dml2_svp_remove_all_phantom_pipes(dml2, display_state);</div><div class='del'>-		display_state-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;</div><div class='del'>-		display_state-&gt;bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false;</div><div class='del'>-		result = dml_mode_support_wrapper(dml2, display_state);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	return result;</div><div class='del'>-}</div><div class='add'>+	if (!context)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-static bool call_dml_mode_support_and_programming(struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	unsigned int result = 0;</div><div class='del'>-	unsigned int min_state;</div><div class='del'>-	int min_state_for_g6_temp_read = 0;</div><div class='ctx'> 	struct dml2_context *dml2 = context-&gt;bw_ctx.dml2;</div><div class='ctx'> 	struct dml2_wrapper_scratch *s = &amp;dml2-&gt;v20.scratch;</div><div class='ctx'> </div><div class='del'>-	min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context);</div><div class='del'>-</div><div class='del'>-	ASSERT(min_state_for_g6_temp_read &gt;= 0);</div><div class='add'>+	if (!context-&gt;streams[0]-&gt;sink-&gt;link-&gt;dc-&gt;caps.is_apu) {</div><div class='add'>+		min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context,</div><div class='add'>+										validate_mode);</div><div class='ctx'> </div><div class='del'>-	if (!dml2-&gt;config.use_native_pstate_optimization) {</div><div class='del'>-		result = optimize_pstate_with_svp_and_drr(dml2, context);</div><div class='del'>-	} else {</div><div class='del'>-		result = dml_mode_support_wrapper(dml2, context);</div><div class='add'>+		ASSERT(min_state_for_g6_temp_read &gt;= 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	result = dml_mode_support_wrapper(dml2, context, validate_mode);</div><div class='add'>+</div><div class='ctx'> 	/* Upon trying to sett certain frequencies in FRL, min_state_for_g6_temp_read is reported as -1. This leads to an invalid value of min_state causing crashes later on.</div><div class='ctx'> 	 * Use the default logic for min_state only when min_state_for_g6_temp_read is a valid value. In other cases, use the value calculated by the DML directly.</div><div class='ctx'> 	 */</div><div class='del'>-	if (min_state_for_g6_temp_read &gt;= 0)</div><div class='del'>-		min_state = min_state_for_g6_temp_read &gt; s-&gt;mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s-&gt;mode_support_params.out_lowest_state_idx;</div><div class='del'>-	else</div><div class='del'>-		min_state = s-&gt;mode_support_params.out_lowest_state_idx;</div><div class='del'>-</div><div class='del'>-	if (result)</div><div class='del'>-		result = dml_mode_programming(&amp;dml2-&gt;v20.dml_core_ctx, min_state, &amp;s-&gt;cur_display_config, true);</div><div class='add'>+	if (!context-&gt;streams[0]-&gt;sink-&gt;link-&gt;dc-&gt;caps.is_apu) {</div><div class='add'>+		if (min_state_for_g6_temp_read &gt;= 0)</div><div class='add'>+			min_state = min_state_for_g6_temp_read &gt; s-&gt;mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s-&gt;mode_support_params.out_lowest_state_idx;</div><div class='add'>+		else</div><div class='add'>+			min_state = s-&gt;mode_support_params.out_lowest_state_idx;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	if (result) {</div><div class='add'>+		if (!context-&gt;streams[0]-&gt;sink-&gt;link-&gt;dc-&gt;caps.is_apu) {</div><div class='add'>+			result = dml_mode_programming(&amp;dml2-&gt;v20.dml_core_ctx, min_state, &amp;s-&gt;cur_display_config, true);</div><div class='add'>+		} else {</div><div class='add'>+			result = dml_mode_programming(&amp;dml2-&gt;v20.dml_core_ctx, s-&gt;mode_support_params.out_lowest_state_idx, &amp;s-&gt;cur_display_config, true);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context)</div><div class='add'>+static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dml2_context *dml2 = context-&gt;bw_ctx.dml2;</div><div class='ctx'> 	struct dml2_wrapper_scratch *s = &amp;dml2-&gt;v20.scratch;</div><div class='ctx'> 	struct dml2_dcn_clocks out_clks;</div><div class='ctx'> 	unsigned int result = 0;</div><div class='ctx'> 	bool need_recalculation = false;</div><div class='add'>+	uint32_t cstate_enter_plus_exit_z8_ns;</div><div class='ctx'> </div><div class='del'>-	if (!context || context-&gt;stream_count == 0)</div><div class='add'>+	if (context-&gt;stream_count == 0) {</div><div class='add'>+		unsigned int lowest_state_idx = 0;</div><div class='add'>+</div><div class='add'>+		out_clks.p_state_supported = true;</div><div class='add'>+		out_clks.dispclk_khz = 0; /* No requirement, and lowest index will generally be maximum dispclk. */</div><div class='add'>+		out_clks.dcfclk_khz = (unsigned int)dml2-&gt;v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000;</div><div class='add'>+		out_clks.fclk_khz = (unsigned int)dml2-&gt;v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000;</div><div class='add'>+		out_clks.uclk_mts = (unsigned int)dml2-&gt;v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts;</div><div class='add'>+		out_clks.phyclk_khz = (unsigned int)dml2-&gt;v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000;</div><div class='add'>+		out_clks.socclk_khz = (unsigned int)dml2-&gt;v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000;</div><div class='add'>+		out_clks.ref_dtbclk_khz = (unsigned int)dml2-&gt;v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000;</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.dtbclk_en = false;</div><div class='add'>+		dml2_copy_clocks_to_dc_state(&amp;out_clks, context);</div><div class='ctx'> 		return true;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Zero out before each call before proceeding */</div><div class='ctx'> 	memset(&amp;dml2-&gt;v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));</div><div class='hunk'>@@ -585,7 +432,7 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s</div><div class='ctx'> </div><div class='ctx'> 	copy_dummy_pstate_table(s-&gt;dummy_pstate_table, in_dc-&gt;clk_mgr-&gt;bw_params-&gt;dummy_pstate_table, 4);</div><div class='ctx'> </div><div class='del'>-	result = call_dml_mode_support_and_programming(context);</div><div class='add'>+	result = call_dml_mode_support_and_programming(context, validate_mode);</div><div class='ctx'> 	/* Call map dc pipes to map the pipes based on the DML output. For correctly determining if recalculation</div><div class='ctx'> 	 * is required or not, the resource context needs to correctly reflect the number of active pipes. We would</div><div class='ctx'> 	 * only know the correct number if active pipes after dml2_map_dc_pipes is called.</div><div class='hunk'>@@ -602,7 +449,7 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s</div><div class='ctx'> 		need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &amp;dml2-&gt;det_helper_scratch);</div><div class='ctx'> 		if (need_recalculation) {</div><div class='ctx'> 			/* Engage the DML again if recalculation is required. */</div><div class='del'>-			call_dml_mode_support_and_programming(context);</div><div class='add'>+			call_dml_mode_support_and_programming(context, validate_mode);</div><div class='ctx'> 			if (!dml2-&gt;config.skip_hw_state_mapping) {</div><div class='ctx'> 				dml2_map_dc_pipes(dml2, context, &amp;s-&gt;cur_display_config, &amp;s-&gt;dml_to_dc_pipe_mapping, in_dc-&gt;current_state);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -637,23 +484,37 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s</div><div class='ctx'> 		dml2_copy_clocks_to_dc_state(&amp;out_clks, context);</div><div class='ctx'> 		dml2_extract_watermark_set(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.a, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='ctx'> 		dml2_extract_watermark_set(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.b, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='del'>-		memcpy(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.c, &amp;dml2-&gt;v20.g6_temp_read_watermark_set, sizeof(context-&gt;bw_ctx.bw.dcn.watermarks.c));</div><div class='add'>+		if (context-&gt;streams[0]-&gt;sink-&gt;link-&gt;dc-&gt;caps.is_apu)</div><div class='add'>+			dml2_extract_watermark_set(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.c, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='add'>+		else</div><div class='add'>+			memcpy(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.c, &amp;dml2-&gt;v20.g6_temp_read_watermark_set, sizeof(context-&gt;bw_ctx.bw.dcn.watermarks.c));</div><div class='ctx'> 		dml2_extract_watermark_set(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.d, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='add'>+		dml2_extract_writeback_wm(context, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='ctx'> 		//copy for deciding zstate use</div><div class='ctx'> 		context-&gt;bw_ctx.dml.vba.StutterPeriod = context-&gt;bw_ctx.dml2-&gt;v20.dml_core_ctx.mp.StutterPeriod;</div><div class='add'>+</div><div class='add'>+		cstate_enter_plus_exit_z8_ns = context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns;</div><div class='add'>+</div><div class='add'>+		if (context-&gt;bw_ctx.dml.vba.StutterPeriod &lt; in_dc-&gt;debug.minimum_z8_residency_time &amp;&amp;</div><div class='add'>+				cstate_enter_plus_exit_z8_ns &lt; in_dc-&gt;debug.minimum_z8_residency_time * 1000)</div><div class='add'>+			cstate_enter_plus_exit_z8_ns = in_dc-&gt;debug.minimum_z8_residency_time * 1000;</div><div class='add'>+</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dml2_validate_only(struct dc_state *context)</div><div class='add'>+static bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='del'>-	struct dml2_context *dml2 = context-&gt;bw_ctx.dml2;</div><div class='add'>+	struct dml2_context *dml2;</div><div class='ctx'> 	unsigned int result = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!context || context-&gt;stream_count == 0)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='add'>+	dml2 = context-&gt;bw_ctx.dml2;</div><div class='add'>+</div><div class='ctx'> 	/* Zero out before each call before proceeding */</div><div class='ctx'> 	memset(&amp;dml2-&gt;v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));</div><div class='ctx'> 	memset(&amp;dml2-&gt;v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));</div><div class='hunk'>@@ -663,15 +524,18 @@ static bool dml2_validate_only(struct dc_state *context)</div><div class='ctx'> 	build_unoptimized_policy_settings(dml2-&gt;v20.dml_core_ctx.project, &amp;dml2-&gt;v20.dml_core_ctx.policy);</div><div class='ctx'> </div><div class='ctx'> 	map_dc_state_into_dml_display_cfg(dml2, context, &amp;dml2-&gt;v20.scratch.cur_display_config);</div><div class='add'>+	 if (!dml2-&gt;config.skip_hw_state_mapping)</div><div class='add'>+		 dml2_apply_det_buffer_allocation_policy(dml2, &amp;dml2-&gt;v20.scratch.cur_display_config);</div><div class='ctx'> </div><div class='ctx'> 	result = pack_and_call_dml_mode_support_ex(dml2,</div><div class='ctx'> 		&amp;dml2-&gt;v20.scratch.cur_display_config,</div><div class='del'>-		&amp;dml2-&gt;v20.scratch.mode_support_info);</div><div class='add'>+		&amp;dml2-&gt;v20.scratch.mode_support_info,</div><div class='add'>+		validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	if (result)</div><div class='ctx'> 		result = does_configuration_meet_sw_policies(dml2, &amp;dml2-&gt;v20.scratch.cur_display_config, &amp;dml2-&gt;v20.scratch.mode_support_info);</div><div class='ctx'> </div><div class='del'>-	return (result == 1) ? true : false;</div><div class='add'>+	return result == 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2)</div><div class='hunk'>@@ -681,30 +545,45 @@ static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *d</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dml2_validate(const struct dc *in_dc, struct dc_state *context, bool fast_validate)</div><div class='add'>+bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='del'>-	if (!(context-&gt;bw_ctx.dml2))</div><div class='add'>+	if (!dml2)</div><div class='ctx'> 		return false;</div><div class='del'>-	dml2_apply_debug_options(in_dc, context-&gt;bw_ctx.dml2);</div><div class='add'>+	dml2_apply_debug_options(in_dc, dml2);</div><div class='ctx'> </div><div class='add'>+	/* DML2.1 validation path */</div><div class='add'>+	if (dml2-&gt;architecture == dml2_architecture_21) {</div><div class='add'>+		out = dml21_validate(in_dc, context, dml2, validate_mode);</div><div class='add'>+		return out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='ctx'> </div><div class='del'>-	/* Use dml_validate_only for fast_validate path */</div><div class='del'>-	if (fast_validate)</div><div class='del'>-		out = dml2_validate_only(context);</div><div class='add'>+	/* Use dml_validate_only for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='add'>+		out = dml2_validate_only(context, validate_mode);</div><div class='ctx'> 	else</div><div class='del'>-		out = dml2_validate_and_build_resource(in_dc, context);</div><div class='add'>+		out = dml2_validate_and_build_resource(in_dc, context, validate_mode);</div><div class='add'>+</div><div class='add'>+	DC_FP_END();</div><div class='add'>+</div><div class='ctx'> 	return out;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline struct dml2_context *dml2_allocate_memory(void)</div><div class='ctx'> {</div><div class='del'>-	return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_KERNEL);</div><div class='add'>+	return (struct dml2_context *) vzalloc(sizeof(struct dml2_context));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)</div><div class='ctx'> {</div><div class='add'>+	if ((in_dc-&gt;debug.using_dml21) &amp;&amp; (in_dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_4_01)) {</div><div class='add'>+		dml21_reinit(in_dc, *dml2, config);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	// Store config options</div><div class='ctx'> 	(*dml2)-&gt;config = *config;</div><div class='hunk'>@@ -716,26 +595,40 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op</div><div class='ctx'> 	case DCN_VERSION_3_51:</div><div class='ctx'> 		(*dml2)-&gt;v20.dml_core_ctx.project = dml_project_dcn351;</div><div class='ctx'> 		break;</div><div class='add'>+	case DCN_VERSION_3_6:</div><div class='add'>+		(*dml2)-&gt;v20.dml_core_ctx.project = dml_project_dcn36;</div><div class='add'>+		break;</div><div class='ctx'> 	case DCN_VERSION_3_2:</div><div class='ctx'> 		(*dml2)-&gt;v20.dml_core_ctx.project = dml_project_dcn32;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DCN_VERSION_3_21:</div><div class='ctx'> 		(*dml2)-&gt;v20.dml_core_ctx.project = dml_project_dcn321;</div><div class='ctx'> 		break;</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		(*dml2)-&gt;v20.dml_core_ctx.project = dml_project_dcn401;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		(*dml2)-&gt;v20.dml_core_ctx.project = dml_project_default;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	DC_FP_START();</div><div class='add'>+</div><div class='ctx'> 	initialize_dml2_ip_params(*dml2, in_dc, &amp;(*dml2)-&gt;v20.dml_core_ctx.ip);</div><div class='ctx'> </div><div class='ctx'> 	initialize_dml2_soc_bbox(*dml2, in_dc, &amp;(*dml2)-&gt;v20.dml_core_ctx.soc);</div><div class='ctx'> </div><div class='ctx'> 	initialize_dml2_soc_states(*dml2, in_dc, &amp;(*dml2)-&gt;v20.dml_core_ctx.soc, &amp;(*dml2)-&gt;v20.dml_core_ctx.states);</div><div class='add'>+</div><div class='add'>+	DC_FP_END();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)</div><div class='ctx'> {</div><div class='add'>+	// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.</div><div class='add'>+	if ((in_dc-&gt;debug.using_dml21) &amp;&amp; (in_dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_4_01))</div><div class='add'>+		return dml21_create(in_dc, dml2, config);</div><div class='add'>+</div><div class='ctx'> 	// Allocate Mode Lib Ctx</div><div class='ctx'> 	*dml2 = dml2_allocate_memory();</div><div class='ctx'> </div><div class='hunk'>@@ -752,7 +645,9 @@ void dml2_destroy(struct dml2_context *dml2)</div><div class='ctx'> 	if (!dml2)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	kfree(dml2);</div><div class='add'>+	if (dml2-&gt;architecture == dml2_architecture_21)</div><div class='add'>+		dml21_destroy(dml2);</div><div class='add'>+	vfree(dml2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,</div><div class='hunk'>@@ -762,9 +657,19 @@ void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,</div><div class='ctx'> 	*dram_clk_change_support = (unsigned int) dml2-&gt;v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2)</div><div class='add'>+{</div><div class='add'>+	if (dml2-&gt;architecture == dml2_architecture_21)</div><div class='add'>+		dml21_prepare_mcache_programming(in_dc, context, dml2);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dml2_copy(struct dml2_context *dst_dml2,</div><div class='ctx'> 	struct dml2_context *src_dml2)</div><div class='ctx'> {</div><div class='add'>+	if (src_dml2-&gt;architecture == dml2_architecture_21) {</div><div class='add'>+		dml21_copy(dst_dml2, src_dml2);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> 	/* copy Mode Lib Ctx */</div><div class='ctx'> 	memcpy(dst_dml2, src_dml2, sizeof(struct dml2_context));</div><div class='ctx'> }</div><div class='hunk'>@@ -772,6 +677,8 @@ void dml2_copy(struct dml2_context *dst_dml2,</div><div class='ctx'> bool dml2_create_copy(struct dml2_context **dst_dml2,</div><div class='ctx'> 	struct dml2_context *src_dml2)</div><div class='ctx'> {</div><div class='add'>+	if (src_dml2-&gt;architecture == dml2_architecture_21)</div><div class='add'>+		return dml21_create_copy(dst_dml2, src_dml2);</div><div class='ctx'> 	/* Allocate Mode Lib Ctx */</div><div class='ctx'> 	*dst_dml2 = dml2_allocate_memory();</div><div class='ctx'> </div><div class='hunk'>@@ -788,6 +695,10 @@ void dml2_reinit(const struct dc *in_dc,</div><div class='ctx'> 				 const struct dml2_configuration_options *config,</div><div class='ctx'> 				 struct dml2_context **dml2)</div><div class='ctx'> {</div><div class='add'>+	if ((in_dc-&gt;debug.using_dml21) &amp;&amp; (in_dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_4_01)) {</div><div class='add'>+		dml21_reinit(in_dc, *dml2, config);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	dml2_init(in_dc, config, dml2);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h<br/>index cc662d682fd4..c384e141cebc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h</a></div><div class='hunk'>@@ -40,6 +40,7 @@ struct dc_sink;</div><div class='ctx'> struct dc_stream_state;</div><div class='ctx'> struct resource_context;</div><div class='ctx'> struct display_stream_compressor;</div><div class='add'>+struct dc_mcache_params;</div><div class='ctx'> </div><div class='ctx'> // Configuration of the MALL on the SoC</div><div class='ctx'> struct dml2_soc_mall_info {</div><div class='hunk'>@@ -71,6 +72,7 @@ struct dml2_dcn_clocks {</div><div class='ctx'> struct dml2_dc_callbacks {</div><div class='ctx'> 	struct dc *dc;</div><div class='ctx'> 	bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*build_test_pattern_params)(struct resource_context *res_ctx, struct pipe_ctx *otg_master);</div><div class='ctx'> 	bool (*can_support_mclk_switch_using_fw_based_vblank_stretch)(struct dc *dc, struct dc_state *context);</div><div class='ctx'> 	bool (*acquire_secondary_pipe_for_mpc_odm)(const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm);</div><div class='ctx'> 	bool (*update_pipes_for_stream_with_slice_count)(</div><div class='hunk'>@@ -86,8 +88,27 @@ struct dml2_dc_callbacks {</div><div class='ctx'> 			const struct dc_plane_state *plane,</div><div class='ctx'> 			int slice_count);</div><div class='ctx'> 	int (*get_odm_slice_index)(const struct pipe_ctx *opp_head);</div><div class='add'>+	int (*get_odm_slice_count)(const struct pipe_ctx *opp_head);</div><div class='ctx'> 	int (*get_mpc_slice_index)(const struct pipe_ctx *dpp_pipe);</div><div class='add'>+	int (*get_mpc_slice_count)(const struct pipe_ctx *dpp_pipe);</div><div class='ctx'> 	struct pipe_ctx *(*get_opp_head)(const struct pipe_ctx *pipe_ctx);</div><div class='add'>+	struct pipe_ctx *(*get_otg_master_for_stream)(</div><div class='add'>+		struct resource_context *res_ctx,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+	int (*get_opp_heads_for_otg_master)(const struct pipe_ctx *otg_master,</div><div class='add'>+		struct resource_context *res_ctx,</div><div class='add'>+		struct pipe_ctx *opp_heads[MAX_PIPES]);</div><div class='add'>+	int (*get_dpp_pipes_for_plane)(const struct dc_plane_state *plane,</div><div class='add'>+			struct resource_context *res_ctx,</div><div class='add'>+			struct pipe_ctx *dpp_pipes[MAX_PIPES]);</div><div class='add'>+	struct dc_stream_status *(*get_stream_status)(</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+	struct dc_stream_state *(*get_stream_from_id)(const struct dc_state *state, unsigned int id);</div><div class='add'>+	unsigned int (*get_max_flickerless_instant_vtotal_increase)(</div><div class='add'>+			struct dc_stream_state *stream,</div><div class='add'>+			bool is_gaming);</div><div class='add'>+	bool (*allocate_mcache)(struct dc_state *context, const struct dc_mcache_params *mcache_params);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dml2_dc_svp_callbacks {</div><div class='hunk'>@@ -96,10 +117,10 @@ struct dml2_dc_svp_callbacks {</div><div class='ctx'> 	struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc,</div><div class='ctx'> 			struct dc_state *state,</div><div class='ctx'> 			struct dc_stream_state *main_stream);</div><div class='del'>-	struct dc_plane_state* (*create_phantom_plane)(struct dc *dc,</div><div class='add'>+	struct dc_plane_state* (*create_phantom_plane)(const struct dc *dc,</div><div class='ctx'> 			struct dc_state *state,</div><div class='ctx'> 			struct dc_plane_state *main_plane);</div><div class='del'>-	enum dc_status (*add_phantom_stream)(struct dc *dc,</div><div class='add'>+	enum dc_status (*add_phantom_stream)(const struct dc *dc,</div><div class='ctx'> 			struct dc_state *state,</div><div class='ctx'> 			struct dc_stream_state *phantom_stream,</div><div class='ctx'> 			struct dc_stream_state *main_stream);</div><div class='hunk'>@@ -108,7 +129,7 @@ struct dml2_dc_svp_callbacks {</div><div class='ctx'> 			struct dc_stream_state *stream,</div><div class='ctx'> 			struct dc_plane_state *plane_state,</div><div class='ctx'> 			struct dc_state *context);</div><div class='del'>-	enum dc_status (*remove_phantom_stream)(struct dc *dc,</div><div class='add'>+	enum dc_status (*remove_phantom_stream)(const struct dc *dc,</div><div class='ctx'> 			struct dc_state *state,</div><div class='ctx'> 			struct dc_stream_state *stream);</div><div class='ctx'> 	void (*release_phantom_plane)(const struct dc *dc,</div><div class='hunk'>@@ -121,6 +142,15 @@ struct dml2_dc_svp_callbacks {</div><div class='ctx'> 	enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream);</div><div class='ctx'> 	struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream);</div><div class='add'>+	bool (*remove_phantom_streams_and_planes)(</div><div class='add'>+			const struct dc *dc,</div><div class='add'>+			struct dc_state *state);</div><div class='add'>+	void (*release_phantom_streams_and_planes)(</div><div class='add'>+			const struct dc *dc,</div><div class='add'>+			struct dc_state *state);</div><div class='add'>+	unsigned int (*calculate_mall_ways_from_bytes)(</div><div class='add'>+				const struct dc *dc,</div><div class='add'>+				unsigned int total_size_in_mall_bytes);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dml2_clks_table_entry {</div><div class='hunk'>@@ -131,6 +161,7 @@ struct dml2_clks_table_entry {</div><div class='ctx'> 	unsigned int dtbclk_mhz;</div><div class='ctx'> 	unsigned int dispclk_mhz;</div><div class='ctx'> 	unsigned int dppclk_mhz;</div><div class='add'>+	unsigned int dram_speed_mts; /*which is based on wck_ratio*/</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dml2_clks_num_entries {</div><div class='hunk'>@@ -167,6 +198,14 @@ struct dml2_soc_bbox_overrides {</div><div class='ctx'> 	struct dml2_clks_limit_table clks_table;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dml2_force_pstate_methods {</div><div class='add'>+	dml2_force_pstate_method_auto = 0,</div><div class='add'>+	dml2_force_pstate_method_vactive,</div><div class='add'>+	dml2_force_pstate_method_vblank,</div><div class='add'>+	dml2_force_pstate_method_drr,</div><div class='add'>+	dml2_force_pstate_method_subvp,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dml2_configuration_options {</div><div class='ctx'> 	int dcn_pipe_count;</div><div class='ctx'> 	bool use_native_pstate_optimization;</div><div class='hunk'>@@ -190,7 +229,18 @@ struct dml2_configuration_options {</div><div class='ctx'> 	struct dml2_soc_bbox_overrides bbox_overrides;</div><div class='ctx'> 	unsigned int max_segments_per_hubp;</div><div class='ctx'> 	unsigned int det_segment_size;</div><div class='add'>+	/* Only for debugging purposes when initializing SOCBB params via tool for DML21. */</div><div class='add'>+	struct socbb_ip_params_external *external_socbb_ip_params;</div><div class='add'>+	struct {</div><div class='add'>+		bool force_pstate_method_enable;</div><div class='add'>+		enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];</div><div class='add'>+	} pmo;</div><div class='ctx'> 	bool map_dc_pipes_with_callbacks;</div><div class='add'>+</div><div class='add'>+	bool use_clock_dc_limits;</div><div class='add'>+	bool gpuvm_enable;</div><div class='add'>+	bool force_tdlut_enable;</div><div class='add'>+	void *bb_from_dmub;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -222,7 +272,7 @@ void dml2_reinit(const struct dc *in_dc,</div><div class='ctx'>  * dml2_validate - Determines if a display configuration is supported or not.</div><div class='ctx'>  * @in_dc: dc.</div><div class='ctx'>  * @context: dc_state to be validated.</div><div class='del'>- * @fast_validate: Fast validate will not populate context.res_ctx.</div><div class='add'>+ * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX will not populate context.res_ctx.</div><div class='ctx'>  *</div><div class='ctx'>  * DML1.0 compatible interface for validation.</div><div class='ctx'>  *</div><div class='hunk'>@@ -244,7 +294,8 @@ void dml2_reinit(const struct dc *in_dc,</div><div class='ctx'>  */</div><div class='ctx'> bool dml2_validate(const struct dc *in_dc,</div><div class='ctx'> 				   struct dc_state *context,</div><div class='del'>-				   bool fast_validate);</div><div class='add'>+				   struct dml2_context *dml2,</div><div class='add'>+				   enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info.</div><div class='hunk'>@@ -254,5 +305,5 @@ bool dml2_validate(const struct dc *in_dc,</div><div class='ctx'>  */</div><div class='ctx'> void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,</div><div class='ctx'> 	unsigned int *fclk_change_support, unsigned int *dram_clk_change_support);</div><div class='del'>-</div><div class='add'>+void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2);</div><div class='ctx'> #endif //_DML2_WRAPPER_H_</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h<br/>index 17f0972b1af7..17f0972b1af7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h<br/>index f7d30b47beff..d459f93cf40b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h</a></div><div class='hunk'>@@ -31,3 +31,4 @@</div><div class='ctx'>  */</div><div class='ctx'> #include "os_types.h"</div><div class='ctx'> #include "cmntypes.h"</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c<br/>index 377ef6d01ae5..00d22e542469 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c</a></div><div class='hunk'>@@ -427,18 +427,6 @@ void dml_rq_dlg_get_dlg_reg(dml_display_dlg_regs_st		   *disp_dlg_regs,</div><div class='ctx'> 	dml_print("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_vm_flip	= 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_vm_flip);</div><div class='ctx'> 	dml_print("DML_DLG: %s: disp_dlg_regs-&gt;dst_y_per_row_flip	= 0x%x\n", __func__, disp_dlg_regs-&gt;dst_y_per_row_flip);</div><div class='ctx'> </div><div class='del'>-	// hack for FPGA</div><div class='del'>-	/* NOTE: We dont have getenv defined in driver and it does not make any sense in the driver */</div><div class='del'>-	/*char* fpga_env = getenv("FPGA_FPDIV");</div><div class='del'>-	if(fpga_env !=NULL)</div><div class='del'>-	{</div><div class='del'>-		if(disp_dlg_regs-&gt;vratio_prefetch &gt;= (dml_uint_t)dml_pow(2, 22))</div><div class='del'>-		{</div><div class='del'>-			disp_dlg_regs-&gt;vratio_prefetch = (dml_uint_t)dml_pow(2, 22)-1;</div><div class='del'>-			dml_print("FPGA msg: vratio_prefetch exceed the max value, the register field is [21:0]\n");</div><div class='del'>-		}</div><div class='del'>-	}*/</div><div class='del'>-</div><div class='ctx'> 	disp_dlg_regs-&gt;refcyc_per_vm_group_vblank		= (dml_uint_t)(dml_get_refcyc_per_vm_group_vblank_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz);</div><div class='ctx'> 	disp_dlg_regs-&gt;refcyc_per_vm_group_flip			= (dml_uint_t)(dml_get_refcyc_per_vm_group_flip_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz);</div><div class='ctx'> 	disp_dlg_regs-&gt;refcyc_per_vm_req_vblank			= (dml_uint_t)(dml_get_refcyc_per_vm_req_vblank_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h<br/>index bf491cf0582d..bf491cf0582d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h<br/>index 2a2f84e07ca8..7fadbe6d7af4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'>  * Authors: AMD</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='add'>+</div><div class='ctx'> #ifndef __DML_LOGGING_H__</div><div class='ctx'> #define __DML_LOGGING_H__</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dpp/Makefile b/drivers/gpu/drm/amd/display/dc/dpp/Makefile<br/>new file mode 100644<br/>index 000000000000..8324a56fe7db<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/Makefile</a></div><div class='hunk'>@@ -0,0 +1,83 @@</div><div class='add'>+</div><div class='add'>+# Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'dpp' sub-component of DAL.</div><div class='add'>+#</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN10 = dcn10_dpp.o dcn10_dpp_dscl.o dcn10_dpp_cm.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN10 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn10/,$(DPP_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN10)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN20 = dcn20_dpp.o dcn20_dpp_cm.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN20 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn20/,$(DPP_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN201 = dcn201_dpp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN201 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn201/,$(DPP_DCN201))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN201)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN30 = dcn30_dpp.o dcn30_dpp_cm.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN30 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn30/,$(DPP_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN32 = dcn32_dpp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN32 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn32/,$(DPP_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN35 = dcn35_dpp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN35 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn35/,$(DPP_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DPP_DCN401 = dcn401_dpp.o dcn401_dpp_cm.o dcn401_dpp_dscl.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN401)</div><div class='add'>+</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c<br/>index 4e391fd1d71c..ce91e5d28956 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn10_dpp.h"</div><div class='add'>+#include "dcn10/dcn10_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> </div><div class='ctx'> #define NUM_PHASES    64</div><div class='hunk'>@@ -194,8 +194,13 @@ void dpp_reset(struct dpp *dpp_base)</div><div class='ctx'> 	dpp-&gt;filter_h = NULL;</div><div class='ctx'> 	dpp-&gt;filter_v = NULL;</div><div class='ctx'> </div><div class='add'>+	memset(&amp;dpp_base-&gt;pos, 0, sizeof(dpp_base-&gt;pos));</div><div class='add'>+	memset(&amp;dpp_base-&gt;att, 0, sizeof(dpp_base-&gt;att));</div><div class='add'>+</div><div class='ctx'> 	memset(&amp;dpp-&gt;scl_data, 0, sizeof(dpp-&gt;scl_data));</div><div class='ctx'> 	memset(&amp;dpp-&gt;pwl_data, 0, sizeof(dpp-&gt;pwl_data));</div><div class='add'>+</div><div class='add'>+	dpp_base-&gt;cursor_offload = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -480,10 +485,13 @@ void dpp1_set_cursor_position(</div><div class='ctx'> 	if (src_y_offset + cursor_height &lt;= 0)</div><div class='ctx'> 		cur_en = 0;  /* not visible beyond top edge*/</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(CURSOR0_CONTROL,</div><div class='del'>-			CUR0_ENABLE, cur_en);</div><div class='add'>+	if (dpp_base-&gt;pos.cur0_ctl.bits.cur0_enable != cur_en) {</div><div class='add'>+		if (!dpp_base-&gt;cursor_offload)</div><div class='add'>+			REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	dpp_base-&gt;pos.cur0_ctl.bits.cur0_enable = cur_en;</div><div class='add'>+	dpp_base-&gt;att.cur0_ctl.bits.cur0_enable = cur_en;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dpp1_cnv_set_optional_cursor_attributes(</div><div class='hunk'>@@ -493,8 +501,13 @@ void dpp1_cnv_set_optional_cursor_attributes(</div><div class='ctx'> 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);</div><div class='ctx'> </div><div class='ctx'> 	if (attr) {</div><div class='del'>-		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr-&gt;bias);</div><div class='del'>-		REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr-&gt;scale);</div><div class='add'>+		if (!dpp_base-&gt;cursor_offload) {</div><div class='add'>+			REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr-&gt;bias);</div><div class='add'>+			REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr-&gt;scale);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dpp_base-&gt;att.fp_scale_bias.bits.fp_bias = attr-&gt;bias;</div><div class='add'>+		dpp_base-&gt;att.fp_scale_bias.bits.fp_scale = attr-&gt;scale;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -516,6 +529,15 @@ void dpp1_dppclk_control(</div><div class='ctx'> 		REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dpp_force_disable_cursor(struct dpp *dpp_base)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	/* Force disable cursor */</div><div class='add'>+	REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0);</div><div class='add'>+	dpp_base-&gt;pos.cur0_ctl.bits.cur0_enable = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct dpp_funcs dcn10_dpp_funcs = {</div><div class='ctx'> 		.dpp_read_state = dpp_read_state,</div><div class='ctx'> 		.dpp_reset = dpp_reset,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h<br/>index a039eedc7c24..b12f34345a58 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h</a></div><div class='hunk'>@@ -1090,7 +1090,8 @@</div><div class='ctx'> 	type DPP_CLOCK_ENABLE; \</div><div class='ctx'> 	type CM_HDR_MULT_COEF; \</div><div class='ctx'> 	type CUR0_FP_BIAS; \</div><div class='del'>-	type CUR0_FP_SCALE;</div><div class='add'>+	type CUR0_FP_SCALE;\</div><div class='add'>+	type DISPCLK_R_GATE_DISABLE;</div><div class='ctx'> </div><div class='ctx'> struct dcn_dpp_shift {</div><div class='ctx'> 	TF_REG_FIELD_LIST(uint8_t)</div><div class='hunk'>@@ -1347,7 +1348,8 @@ struct dcn_dpp_mask {</div><div class='ctx'> 	uint32_t CURSOR0_COLOR1; \</div><div class='ctx'> 	uint32_t DPP_CONTROL; \</div><div class='ctx'> 	uint32_t CM_HDR_MULT_COEF; \</div><div class='del'>-	uint32_t CURSOR0_FP_SCALE_BIAS;</div><div class='add'>+	uint32_t CURSOR0_FP_SCALE_BIAS; \</div><div class='add'>+	uint32_t OBUF_CONTROL;</div><div class='ctx'> </div><div class='ctx'> struct dcn_dpp_registers {</div><div class='ctx'> 	DPP_COMMON_REG_VARIABLE_LIST</div><div class='hunk'>@@ -1449,7 +1451,6 @@ void dpp1_set_degamma(</div><div class='ctx'> void dpp1_set_degamma_pwl(struct dpp *dpp_base,</div><div class='ctx'> 		const struct pwl_params *params);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> void dpp_read_state(struct dpp *dpp_base,</div><div class='ctx'> 		struct dcn_dpp_state *s);</div><div class='ctx'> </div><div class='hunk'>@@ -1524,4 +1525,6 @@ void dpp1_construct(struct dcn10_dpp *dpp1,</div><div class='ctx'> </div><div class='ctx'> void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,</div><div class='ctx'> 			     struct dpp_grph_csc_adjustment *adjust);</div><div class='add'>+void dpp_force_disable_cursor(struct dpp *dpp_base);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c<br/>index 2f994a3a0b9c..f8f6019d8304 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c</a></div><div class='hunk'>@@ -28,9 +28,9 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn10_dpp.h"</div><div class='add'>+#include "dcn10/dcn10_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='del'>-#include "dcn10_cm_common.h"</div><div class='add'>+#include "dcn10/dcn10_cm_common.h"</div><div class='ctx'> </div><div class='ctx'> #define NUM_PHASES    64</div><div class='ctx'> #define HORZ_MAX_TAPS 8</div><div class='hunk'>@@ -234,7 +234,7 @@ void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,</div><div class='ctx'> 			     struct dpp_grph_csc_adjustment *adjust)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);</div><div class='del'>-	uint16_t arr_reg_val[12];</div><div class='add'>+	uint16_t arr_reg_val[12] = {0};</div><div class='ctx'> 	enum gamut_remap_select select;</div><div class='ctx'> </div><div class='ctx'> 	read_gamut_remap(dpp, arr_reg_val, &amp;select);</div><div class='hunk'>@@ -410,9 +410,10 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,</div><div class='ctx'> 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);</div><div class='ctx'> 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);</div><div class='ctx'> 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);</div><div class='del'>-</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	REG_SEQ_SUBMIT();</div><div class='add'>+	REG_SEQ_WAIT_DONE();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dpp1_cm_configure_regamma_lut(</div><div class='hunk'>@@ -683,9 +684,6 @@ void dpp1_set_degamma(</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	REG_SEQ_SUBMIT();</div><div class='del'>-	REG_SEQ_WAIT_DONE();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dpp1_degamma_ram_select(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c<br/>index 5ca9ab8a76e8..808bca9fb804 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn10_dpp.h"</div><div class='add'>+#include "dcn10/dcn10_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c<br/>index 1516c0a48726..c433f4b876e9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn20_dpp.h"</div><div class='add'>+#include "dcn20/dcn20_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> </div><div class='ctx'> #define NUM_PHASES    64</div><div class='hunk'>@@ -432,4 +432,60 @@ bool dpp2_construct(</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='add'>+/*compute the maximum number of lines that we can fit in the line buffer*/</div><div class='add'>+void dscl2_spl_calc_lb_num_partitions(</div><div class='add'>+		bool alpha_en,</div><div class='add'>+		const struct spl_scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c)</div><div class='add'>+{</div><div class='add'>+	int memory_line_size_y, memory_line_size_c, memory_line_size_a,</div><div class='add'>+	lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;</div><div class='add'>+</div><div class='add'>+	int line_size = scl_data-&gt;viewport.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport.width : scl_data-&gt;recout.width;</div><div class='add'>+	int line_size_c = scl_data-&gt;viewport_c.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport_c.width : scl_data-&gt;recout.width;</div><div class='add'>+</div><div class='add'>+	if (line_size == 0)</div><div class='add'>+		line_size = 1;</div><div class='add'>+</div><div class='add'>+	if (line_size_c == 0)</div><div class='add'>+		line_size_c = 1;</div><div class='add'>+</div><div class='add'>+	memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+</div><div class='add'>+	if (lb_config == LB_MEMORY_CONFIG_1) {</div><div class='add'>+		lb_memory_size = 970;</div><div class='add'>+		lb_memory_size_c = 970;</div><div class='add'>+		lb_memory_size_a = 970;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_2) {</div><div class='add'>+		lb_memory_size = 1290;</div><div class='add'>+		lb_memory_size_c = 1290;</div><div class='add'>+		lb_memory_size_a = 1290;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_3) {</div><div class='add'>+		/* 420 mode: using 3rd mem from Y, Cr and Cb */</div><div class='add'>+		lb_memory_size = 970 + 1290 + 484 + 484 + 484;</div><div class='add'>+		lb_memory_size_c = 970 + 1290;</div><div class='add'>+		lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+	} else {</div><div class='add'>+		lb_memory_size = 970 + 1290 + 484;</div><div class='add'>+		lb_memory_size_c = 970 + 1290 + 484;</div><div class='add'>+		lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+	}</div><div class='add'>+	*num_part_y = lb_memory_size / memory_line_size_y;</div><div class='add'>+	*num_part_c = lb_memory_size_c / memory_line_size_c;</div><div class='add'>+	num_partitions_a = lb_memory_size_a / memory_line_size_a;</div><div class='ctx'> </div><div class='add'>+	if (alpha_en</div><div class='add'>+			&amp;&amp; (num_partitions_a &lt; *num_part_y))</div><div class='add'>+		*num_part_y = num_partitions_a;</div><div class='add'>+</div><div class='add'>+	if (*num_part_y &gt; 64)</div><div class='add'>+		*num_part_y = 64;</div><div class='add'>+	if (*num_part_c &gt; 64)</div><div class='add'>+		*num_part_c = 64;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h<br/>index 672cde46c4b9..85f359b5da67 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h</a></div><div class='hunk'>@@ -26,7 +26,6 @@</div><div class='ctx'> #define __DCN20_DPP_H__</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_dpp.h"</div><div class='del'>-</div><div class='ctx'> #define TO_DCN20_DPP(dpp)\</div><div class='ctx'> 	container_of(dpp, struct dcn20_dpp, base)</div><div class='ctx'> </div><div class='hunk'>@@ -690,6 +689,7 @@ struct dcn20_dpp {</div><div class='ctx'> 	int lb_memory_size;</div><div class='ctx'> 	int lb_bits_per_entry;</div><div class='ctx'> 	bool is_write_to_ram_a_safe;</div><div class='add'>+	bool dispclk_r_gate_disable;</div><div class='ctx'> 	struct scaler_data scl_data;</div><div class='ctx'> 	struct pwl_params pwl_data;</div><div class='ctx'> };</div><div class='hunk'>@@ -736,7 +736,7 @@ bool dpp20_program_shaper(</div><div class='ctx'> </div><div class='ctx'> bool dpp20_program_3dlut(</div><div class='ctx'> 		struct dpp *dpp_base,</div><div class='del'>-		struct tetrahedral_params *params);</div><div class='add'>+		const struct tetrahedral_params *params);</div><div class='ctx'> </div><div class='ctx'> void dpp2_cnv_set_alpha_keyer(</div><div class='ctx'> 			struct dpp *dpp_base,</div><div class='hunk'>@@ -748,6 +748,13 @@ void dscl2_calc_lb_num_partitions(</div><div class='ctx'> 			int *num_part_y,</div><div class='ctx'> 			int *num_part_c);</div><div class='ctx'> </div><div class='add'>+void dscl2_spl_calc_lb_num_partitions(</div><div class='add'>+	bool alpha_en,</div><div class='add'>+	const struct spl_scaler_data *scl_data,</div><div class='add'>+	enum lb_memory_config lb_config,</div><div class='add'>+	int *num_part_y,</div><div class='add'>+	int *num_part_c);</div><div class='add'>+</div><div class='ctx'> void dpp2_set_cursor_attributes(</div><div class='ctx'> 		struct dpp *dpp_base,</div><div class='ctx'> 		struct dc_cursor_attributes *cursor_attributes);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c<br/>index 58dc69926e8a..31613372e214 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn20_dpp.h"</div><div class='add'>+#include "dcn20/dcn20_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_cm_common.h"</div><div class='hunk'>@@ -274,7 +274,7 @@ void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,</div><div class='ctx'> 			     struct dpp_grph_csc_adjustment *adjust)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);</div><div class='del'>-	uint16_t arr_reg_val[12];</div><div class='add'>+	uint16_t arr_reg_val[12] = {0};</div><div class='ctx'> 	enum dcn20_gamut_remap_select select;</div><div class='ctx'> </div><div class='ctx'> 	read_gamut_remap(dpp, arr_reg_val, &amp;select);</div><div class='hunk'>@@ -1114,15 +1114,15 @@ static void dpp20_select_3dlut_ram_mask(</div><div class='ctx'> </div><div class='ctx'> bool dpp20_program_3dlut(</div><div class='ctx'> 		struct dpp *dpp_base,</div><div class='del'>-		struct tetrahedral_params *params)</div><div class='add'>+		const struct tetrahedral_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_lut_mode mode;</div><div class='ctx'> 	bool is_17x17x17;</div><div class='ctx'> 	bool is_12bits_color_channel;</div><div class='del'>-	struct dc_rgb *lut0;</div><div class='del'>-	struct dc_rgb *lut1;</div><div class='del'>-	struct dc_rgb *lut2;</div><div class='del'>-	struct dc_rgb *lut3;</div><div class='add'>+	const struct dc_rgb *lut0;</div><div class='add'>+	const struct dc_rgb *lut1;</div><div class='add'>+	const struct dc_rgb *lut2;</div><div class='add'>+	const struct dc_rgb *lut3;</div><div class='ctx'> 	int lut_size0;</div><div class='ctx'> 	int lut_size;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c<br/>index f809a7d21033..d78ab3ffd95d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn201_dpp.h"</div><div class='add'>+#include "dcn201/dcn201_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> </div><div class='ctx'> #define REG(reg)\</div><div class='hunk'>@@ -61,6 +61,13 @@ static void dpp201_cnv_setup(</div><div class='ctx'> 		CNVC_BYPASS, 0,</div><div class='ctx'> 		FORMAT_EXPANSION_MODE, mode);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * hardcode default</div><div class='add'>+	 * FORMAT_CONTROL. FORMAT_CNV16				default 0: U0.16/S.1.15;	1: U1.15/ S.1.14</div><div class='add'>+	 * FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN		default 0: disabled			1: enabled</div><div class='add'>+	 * FORMAT_CONTROL. CLAMP_POSITIVE			default 0: disabled			1: enabled</div><div class='add'>+	 * FORMAT_CONTROL. CLAMP_POSITIVE_C			default 0: disabled			1: enabled</div><div class='add'>+	 */</div><div class='ctx'> 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);</div><div class='ctx'> 	REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);</div><div class='ctx'> 	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);</div><div class='hunk'>@@ -185,6 +192,7 @@ static bool dpp201_get_optimal_number_of_taps(</div><div class='ctx'> 		struct scaler_data *scl_data,</div><div class='ctx'> 		const struct scaling_taps *in_taps)</div><div class='ctx'> {</div><div class='add'>+	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/</div><div class='ctx'> 	if (scl_data-&gt;viewport.width  != scl_data-&gt;h_active &amp;&amp;</div><div class='ctx'> 		scl_data-&gt;viewport.height != scl_data-&gt;v_active &amp;&amp;</div><div class='ctx'> 		dpp-&gt;caps-&gt;dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &amp;&amp;</div><div class='hunk'>@@ -196,6 +204,7 @@ static bool dpp201_get_optimal_number_of_taps(</div><div class='ctx'> 		scl_data-&gt;viewport.width &gt; dpp-&gt;ctx-&gt;dc-&gt;debug.max_downscale_src_width)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	/* No support for programming ratio of 8, drop to 7.99999.. */</div><div class='ctx'> 	if (scl_data-&gt;ratios.horz.value == (8ll &lt;&lt; 32))</div><div class='ctx'> 		scl_data-&gt;ratios.horz.value--;</div><div class='ctx'> 	if (scl_data-&gt;ratios.vert.value == (8ll &lt;&lt; 32))</div><div class='hunk'>@@ -205,6 +214,7 @@ static bool dpp201_get_optimal_number_of_taps(</div><div class='ctx'> 	if (scl_data-&gt;ratios.vert_c.value == (8ll &lt;&lt; 32))</div><div class='ctx'> 		scl_data-&gt;ratios.vert_c.value--;</div><div class='ctx'> </div><div class='add'>+	/* Set default taps if none are provided */</div><div class='ctx'> 	if (in_taps-&gt;h_taps == 0) {</div><div class='ctx'> 		if (dc_fixpt_ceil(scl_data-&gt;ratios.horz) &gt; 4)</div><div class='ctx'> 			scl_data-&gt;taps.h_taps = 8;</div><div class='hunk'>@@ -233,6 +243,7 @@ static bool dpp201_get_optimal_number_of_taps(</div><div class='ctx'> 		else</div><div class='ctx'> 			scl_data-&gt;taps.h_taps_c = 2;</div><div class='ctx'> 	} else if ((in_taps-&gt;h_taps_c % 2) != 0 &amp;&amp; in_taps-&gt;h_taps_c != 1)</div><div class='add'>+		/* Only 1 and even h_taps_c are supported by hw */</div><div class='ctx'> 		scl_data-&gt;taps.h_taps_c = in_taps-&gt;h_taps_c - 1;</div><div class='ctx'> 	else</div><div class='ctx'> 		scl_data-&gt;taps.h_taps_c = in_taps-&gt;h_taps_c;</div><div class='hunk'>@@ -307,7 +318,7 @@ bool dpp201_construct(</div><div class='ctx'> 		LB_PIXEL_DEPTH_30BPP;</div><div class='ctx'> </div><div class='ctx'> 	dpp-&gt;lb_bits_per_entry = LB_BITS_PER_ENTRY;</div><div class='del'>-	dpp-&gt;lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES;</div><div class='add'>+	dpp-&gt;lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h<br/>index cbd5b47b4acf..cbd5b47b4acf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c<br/>index a3a769aad042..ef4a16117181 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c</a></div><div class='hunk'>@@ -26,9 +26,9 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn30_dpp.h"</div><div class='add'>+#include "dcn30/dcn30_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='del'>-#include "dcn30_cm_common.h"</div><div class='add'>+#include "dcn30/dcn30_cm_common.h"</div><div class='ctx'> </div><div class='ctx'> #define REG(reg)\</div><div class='ctx'> 	dpp-&gt;tf_regs-&gt;reg</div><div class='hunk'>@@ -64,25 +64,42 @@ void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// Shaper LUT (RAM), 3D LUT (mode, bit-depth, size)</div><div class='del'>-	REG_GET(CM_SHAPER_CONTROL,</div><div class='del'>-		CM_SHAPER_LUT_MODE, &amp;s-&gt;shaper_lut_mode);</div><div class='del'>-	REG_GET(CM_3DLUT_MODE,</div><div class='del'>-		CM_3DLUT_MODE_CURRENT, &amp;s-&gt;lut3d_mode);</div><div class='del'>-	REG_GET(CM_3DLUT_READ_WRITE_CONTROL,</div><div class='del'>-		CM_3DLUT_30BIT_EN, &amp;s-&gt;lut3d_bit_depth);</div><div class='del'>-	REG_GET(CM_3DLUT_MODE,</div><div class='del'>-		CM_3DLUT_SIZE, &amp;s-&gt;lut3d_size);</div><div class='add'>+	if (REG(CM_SHAPER_CONTROL))</div><div class='add'>+		REG_GET(CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, &amp;s-&gt;shaper_lut_mode);</div><div class='add'>+	if (REG(CM_3DLUT_MODE))</div><div class='add'>+		REG_GET(CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, &amp;s-&gt;lut3d_mode);</div><div class='add'>+	if (REG(CM_3DLUT_READ_WRITE_CONTROL))</div><div class='add'>+		REG_GET(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, &amp;s-&gt;lut3d_bit_depth);</div><div class='add'>+	if (REG(CM_3DLUT_MODE))</div><div class='add'>+		REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &amp;s-&gt;lut3d_size);</div><div class='ctx'> </div><div class='ctx'> 	// Blend/Out Gamma (RAM)</div><div class='del'>-	REG_GET(CM_BLNDGAM_CONTROL,</div><div class='del'>-		CM_BLNDGAM_MODE_CURRENT, &amp;s-&gt;rgam_lut_mode);</div><div class='del'>-	if (s-&gt;rgam_lut_mode){</div><div class='del'>-		REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &amp;rgam_lut_mode);</div><div class='del'>-		if (!rgam_lut_mode)</div><div class='del'>-			s-&gt;rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B</div><div class='add'>+	if (REG(CM_BLNDGAM_CONTROL)) {</div><div class='add'>+		REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, &amp;s-&gt;rgam_lut_mode);</div><div class='add'>+		if (s-&gt;rgam_lut_mode) {</div><div class='add'>+			REG_GET(CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, &amp;rgam_lut_mode);</div><div class='add'>+			if (!rgam_lut_mode)</div><div class='add'>+				s-&gt;rgam_lut_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	dpp_reg_state-&gt;recout_start = REG_READ(RECOUT_START);</div><div class='add'>+	dpp_reg_state-&gt;recout_size = REG_READ(RECOUT_SIZE);</div><div class='add'>+	dpp_reg_state-&gt;scl_horz_filter_scale_ratio = REG_READ(SCL_HORZ_FILTER_SCALE_RATIO);</div><div class='add'>+	dpp_reg_state-&gt;scl_vert_filter_scale_ratio = REG_READ(SCL_VERT_FILTER_SCALE_RATIO);</div><div class='add'>+	dpp_reg_state-&gt;scl_mode = REG_READ(SCL_MODE);</div><div class='add'>+	dpp_reg_state-&gt;cm_control = REG_READ(CM_CONTROL);</div><div class='add'>+	dpp_reg_state-&gt;dpp_control = REG_READ(DPP_CONTROL);</div><div class='add'>+	dpp_reg_state-&gt;dscl_control = REG_READ(DSCL_CONTROL);</div><div class='add'>+	dpp_reg_state-&gt;obuf_control = REG_READ(OBUF_CONTROL);</div><div class='add'>+	dpp_reg_state-&gt;mpc_size = REG_READ(MPC_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*program post scaler scs block in dpp CM*/</div><div class='ctx'> void dpp3_program_post_csc(</div><div class='ctx'> 		struct dpp *dpp_base,</div><div class='hunk'>@@ -218,7 +235,6 @@ void dpp3_cnv_setup (</div><div class='ctx'> 	uint32_t alpha_plane_enable = 0;</div><div class='ctx'> 	uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;</div><div class='ctx'> 	uint32_t realpha_en = 0, realpha_ablnd_en = 0;</div><div class='del'>-	uint32_t program_prealpha_dealpha = 0;</div><div class='ctx'> 	struct out_csc_color_matrix tbl_entry;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -293,9 +309,11 @@ void dpp3_cnv_setup (</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:</div><div class='ctx'> 		pixel_format = 112;</div><div class='add'>+		alpha_en = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:</div><div class='ctx'> 		pixel_format = 113;</div><div class='add'>+		alpha_en = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:</div><div class='ctx'> 		pixel_format = 114;</div><div class='hunk'>@@ -319,9 +337,11 @@ void dpp3_cnv_setup (</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:</div><div class='ctx'> 		pixel_format = 118;</div><div class='add'>+		alpha_en = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:</div><div class='ctx'> 		pixel_format = 119;</div><div class='add'>+		alpha_en = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -342,10 +362,6 @@ void dpp3_cnv_setup (</div><div class='ctx'> 			CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);</div><div class='ctx'> 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);</div><div class='ctx'> </div><div class='del'>-	if (program_prealpha_dealpha) {</div><div class='del'>-		dealpha_en = 1;</div><div class='del'>-		realpha_en = 1;</div><div class='del'>-	}</div><div class='ctx'> 	REG_SET_2(PRE_DEALPHA, 0,</div><div class='ctx'> 			PRE_DEALPHA_EN, dealpha_en,</div><div class='ctx'> 			PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);</div><div class='hunk'>@@ -396,17 +412,21 @@ void dpp3_set_cursor_attributes(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE_3(CURSOR0_CONTROL,</div><div class='del'>-			CUR0_MODE, color_format,</div><div class='del'>-			CUR0_EXPANSION_MODE, 0,</div><div class='del'>-			CUR0_ROM_EN, cur_rom_en);</div><div class='add'>+	if (!dpp_base-&gt;cursor_offload)</div><div class='add'>+		REG_UPDATE_3(CURSOR0_CONTROL,</div><div class='add'>+				CUR0_MODE, color_format,</div><div class='add'>+				CUR0_EXPANSION_MODE, 0,</div><div class='add'>+				CUR0_ROM_EN, cur_rom_en);</div><div class='ctx'> </div><div class='ctx'> 	if (color_format == CURSOR_MODE_MONO) {</div><div class='ctx'> 		/* todo: clarify what to program these to */</div><div class='del'>-		REG_UPDATE(CURSOR0_COLOR0,</div><div class='del'>-				CUR0_COLOR0, 0x00000000);</div><div class='del'>-		REG_UPDATE(CURSOR0_COLOR1,</div><div class='del'>-				CUR0_COLOR1, 0xFFFFFFFF);</div><div class='add'>+</div><div class='add'>+		if (!dpp_base-&gt;cursor_offload) {</div><div class='add'>+			REG_UPDATE(CURSOR0_COLOR0,</div><div class='add'>+					CUR0_COLOR0, 0x00000000);</div><div class='add'>+			REG_UPDATE(CURSOR0_COLOR1,</div><div class='add'>+					CUR0_COLOR1, 0xFFFFFFFF);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dpp_base-&gt;att.cur0_ctl.bits.expansion_mode = 0;</div><div class='hunk'>@@ -425,11 +445,6 @@ bool dpp3_get_optimal_number_of_taps(</div><div class='ctx'> 	int min_taps_y, min_taps_c;</div><div class='ctx'> 	enum lb_memory_config lb_config;</div><div class='ctx'> </div><div class='del'>-	if (scl_data-&gt;viewport.width &gt; scl_data-&gt;h_active &amp;&amp;</div><div class='del'>-		dpp-&gt;ctx-&gt;dc-&gt;debug.max_downscale_src_width != 0 &amp;&amp;</div><div class='del'>-		scl_data-&gt;viewport.width &gt; dpp-&gt;ctx-&gt;dc-&gt;debug.max_downscale_src_width)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Set default taps if none are provided</div><div class='ctx'> 	 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling</div><div class='hunk'>@@ -467,6 +482,12 @@ bool dpp3_get_optimal_number_of_taps(</div><div class='ctx'> 	else</div><div class='ctx'> 		scl_data-&gt;taps.h_taps_c = in_taps-&gt;h_taps_c;</div><div class='ctx'> </div><div class='add'>+	// Avoid null data in the scl data with this early return, proceed non-adaptive calcualtion first</div><div class='add'>+	if (scl_data-&gt;viewport.width &gt; scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+		dpp-&gt;ctx-&gt;dc-&gt;debug.max_downscale_src_width != 0 &amp;&amp;</div><div class='add'>+		scl_data-&gt;viewport.width &gt; dpp-&gt;ctx-&gt;dc-&gt;debug.max_downscale_src_width)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	/*Ensure we can support the requested number of vtaps*/</div><div class='ctx'> 	min_taps_y = dc_fixpt_ceil(scl_data-&gt;ratios.vert);</div><div class='ctx'> 	min_taps_c = dc_fixpt_ceil(scl_data-&gt;ratios.vert_c);</div><div class='hunk'>@@ -577,9 +598,6 @@ static void dpp3_power_on_blnd_lut(</div><div class='ctx'> 			dpp_base-&gt;ctx-&gt;dc-&gt;optimized_required = true;</div><div class='ctx'> 			dpp_base-&gt;deferred_reg_writes.bits.disable_blnd_lut = true;</div><div class='ctx'> 		}</div><div class='del'>-	} else {</div><div class='del'>-		REG_SET(CM_MEM_PWR_CTRL, 0,</div><div class='del'>-				BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -789,8 +807,7 @@ static bool dpp3_program_blnd_lut(struct dpp *dpp_base,</div><div class='ctx'> </div><div class='ctx'> 	if (params == NULL) {</div><div class='ctx'> 		REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);</div><div class='del'>-		if (dpp_base-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.cm)</div><div class='del'>-			dpp3_power_on_blnd_lut(dpp_base, false);</div><div class='add'>+		dpp3_power_on_blnd_lut(dpp_base, false);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1203,8 +1220,7 @@ static bool dpp3_program_shaper(struct dpp *dpp_base,</div><div class='ctx'> </div><div class='ctx'> 	if (params == NULL) {</div><div class='ctx'> 		REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);</div><div class='del'>-		if (dpp_base-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.cm)</div><div class='del'>-			dpp3_power_on_shaper(dpp_base, false);</div><div class='add'>+		dpp3_power_on_shaper(dpp_base, false);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1384,22 +1400,21 @@ static void dpp3_select_3dlut_ram_mask(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool dpp3_program_3dlut(struct dpp *dpp_base,</div><div class='del'>-			       struct tetrahedral_params *params)</div><div class='add'>+			       const struct tetrahedral_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_lut_mode mode;</div><div class='ctx'> 	bool is_17x17x17;</div><div class='ctx'> 	bool is_12bits_color_channel;</div><div class='del'>-	struct dc_rgb *lut0;</div><div class='del'>-	struct dc_rgb *lut1;</div><div class='del'>-	struct dc_rgb *lut2;</div><div class='del'>-	struct dc_rgb *lut3;</div><div class='add'>+	const struct dc_rgb *lut0;</div><div class='add'>+	const struct dc_rgb *lut1;</div><div class='add'>+	const struct dc_rgb *lut2;</div><div class='add'>+	const struct dc_rgb *lut3;</div><div class='ctx'> 	int lut_size0;</div><div class='ctx'> 	int lut_size;</div><div class='ctx'> </div><div class='ctx'> 	if (params == NULL) {</div><div class='ctx'> 		dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);</div><div class='del'>-		if (dpp_base-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.cm)</div><div class='del'>-			dpp3_power_on_hdr3dlut(dpp_base, false);</div><div class='add'>+		dpp3_power_on_hdr3dlut(dpp_base, false);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1496,6 +1511,7 @@ static struct dpp_funcs dcn30_dpp_funcs = {</div><div class='ctx'> 	.dpp_dppclk_control		= dpp1_dppclk_control,</div><div class='ctx'> 	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,</div><div class='ctx'> 	.dpp_get_gamut_remap		= dpp3_cm_get_gamut_remap,</div><div class='add'>+	.dpp_force_disable_cursor 	= dpp_force_disable_cursor,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h<br/>index 2ac8045a87a1..d4a70b4379ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h</a></div><div class='hunk'>@@ -132,6 +132,8 @@</div><div class='ctx'> 	SRI(CM_POST_CSC_B_C33_C34, CM, id), \</div><div class='ctx'> 	SRI(CM_MEM_PWR_CTRL, CM, id), \</div><div class='ctx'> 	SRI(CM_CONTROL, CM, id), \</div><div class='add'>+	SRI(CM_TEST_DEBUG_INDEX, CM, id), \</div><div class='add'>+	SRI(CM_TEST_DEBUG_DATA, CM, id), \</div><div class='ctx'> 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \</div><div class='ctx'> 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \</div><div class='ctx'> 	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \</div><div class='hunk'>@@ -173,8 +175,6 @@</div><div class='ctx'> 	SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\</div><div class='ctx'> 	SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> #define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\</div><div class='ctx'> 	TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\</div><div class='ctx'> 	TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\</div><div class='hunk'>@@ -294,6 +294,7 @@</div><div class='ctx'> 	TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \</div><div class='ctx'> 	TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \</div><div class='ctx'> 	TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \</div><div class='ctx'> 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \</div><div class='ctx'> 	TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \</div><div class='ctx'> 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \</div><div class='hunk'>@@ -426,6 +427,7 @@</div><div class='ctx'> 	type CM_GAMCOR_LUT_DATA; \</div><div class='ctx'> 	type CM_GAMCOR_LUT_WRITE_COLOR_MASK; \</div><div class='ctx'> 	type CM_GAMCOR_LUT_READ_COLOR_SEL; \</div><div class='add'>+	type CM_GAMCOR_LUT_READ_DBG; \</div><div class='ctx'> 	type CM_GAMCOR_LUT_HOST_SEL; \</div><div class='ctx'> 	type CM_GAMCOR_LUT_CONFIG_MODE; \</div><div class='ctx'> 	type CM_GAMCOR_LUT_STATUS; \</div><div class='hunk'>@@ -570,6 +572,7 @@ struct dcn3_dpp {</div><div class='ctx'> 	int lb_memory_size;</div><div class='ctx'> 	int lb_bits_per_entry;</div><div class='ctx'> 	bool is_write_to_ram_a_safe;</div><div class='add'>+	bool dispclk_r_gate_disable;</div><div class='ctx'> 	struct scaler_data scl_data;</div><div class='ctx'> 	struct pwl_params pwl_data;</div><div class='ctx'> };</div><div class='hunk'>@@ -591,12 +594,14 @@ void dpp3_program_CM_dealpha(</div><div class='ctx'> void dpp30_read_state(struct dpp *dpp_base,</div><div class='ctx'> 		struct dcn_dpp_state *s);</div><div class='ctx'> </div><div class='add'>+void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);</div><div class='add'>+</div><div class='ctx'> bool dpp3_get_optimal_number_of_taps(</div><div class='ctx'> 		struct dpp *dpp,</div><div class='ctx'> 		struct scaler_data *scl_data,</div><div class='ctx'> 		const struct scaling_taps *in_taps);</div><div class='ctx'> </div><div class='del'>-void dpp3_cnv_setup (</div><div class='add'>+void dpp3_cnv_setup(</div><div class='ctx'> 		struct dpp *dpp_base,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='ctx'> 		enum expansion_mode mode,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c<br/>index 2f5b3fbd3507..82eca0e7b7d0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c</a></div><div class='hunk'>@@ -26,9 +26,9 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn30_dpp.h"</div><div class='add'>+#include "dcn30/dcn30_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='del'>-#include "dcn30_cm_common.h"</div><div class='add'>+#include "dcn30/dcn30_cm_common.h"</div><div class='ctx'> </div><div class='ctx'> #define REG(reg)\</div><div class='ctx'> 	dpp-&gt;tf_regs-&gt;reg</div><div class='hunk'>@@ -445,7 +445,7 @@ void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,</div><div class='ctx'> 			     struct dpp_grph_csc_adjustment *adjust)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);</div><div class='del'>-	uint16_t arr_reg_val[12];</div><div class='add'>+	uint16_t arr_reg_val[12] = {0};</div><div class='ctx'> 	int select;</div><div class='ctx'> </div><div class='ctx'> 	read_gamut_remap(dpp, arr_reg_val, &amp;select);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c<br/>index 681e75c6dbaf..8a5aa5e86850 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='del'>-#include "dcn32_dpp.h"</div><div class='add'>+#include "dcn32/dcn32_dpp.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> #include "dcn30/dcn30_cm_common.h"</div><div class='ctx'> </div><div class='hunk'>@@ -134,6 +134,7 @@ static struct dpp_funcs dcn32_dpp_funcs = {</div><div class='ctx'> 	.dpp_dppclk_control			= dpp1_dppclk_control,</div><div class='ctx'> 	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,</div><div class='ctx'> 	.dpp_get_gamut_remap		= dpp3_cm_get_gamut_remap,</div><div class='add'>+	.dpp_read_reg_state			= dpp30_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -163,3 +164,76 @@ bool dpp32_construct(</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='add'>+void dscl32_spl_calc_lb_num_partitions(</div><div class='add'>+		bool alpha_en,</div><div class='add'>+		const struct spl_scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c)</div><div class='add'>+{</div><div class='add'>+	int memory_line_size_y, memory_line_size_c, memory_line_size_a,</div><div class='add'>+	lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;</div><div class='add'>+</div><div class='add'>+	int line_size = scl_data-&gt;viewport.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport.width : scl_data-&gt;recout.width;</div><div class='add'>+	int line_size_c = scl_data-&gt;viewport_c.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport_c.width : scl_data-&gt;recout.width;</div><div class='add'>+</div><div class='add'>+	if (line_size == 0)</div><div class='add'>+		line_size = 1;</div><div class='add'>+</div><div class='add'>+	if (line_size_c == 0)</div><div class='add'>+		line_size_c = 1;</div><div class='add'>+</div><div class='add'>+	memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+</div><div class='add'>+	if (lb_config == LB_MEMORY_CONFIG_1) {</div><div class='add'>+		lb_memory_size = 970;</div><div class='add'>+		lb_memory_size_c = 970;</div><div class='add'>+		lb_memory_size_a = 970;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_2) {</div><div class='add'>+		lb_memory_size = 1290;</div><div class='add'>+		lb_memory_size_c = 1290;</div><div class='add'>+		lb_memory_size_a = 1290;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_3) {</div><div class='add'>+		if (scl_data-&gt;viewport.width  == scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+			scl_data-&gt;viewport.height == scl_data-&gt;v_active) {</div><div class='add'>+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */</div><div class='add'>+			/* use increased LB size for calculation only if Scaler not enabled */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;</div><div class='add'>+			lb_memory_size_c = 970 + 1290;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 1170;</div><div class='add'>+		} else {</div><div class='add'>+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 484 + 484 + 484;</div><div class='add'>+			lb_memory_size_c = 970 + 1290;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (scl_data-&gt;viewport.width  == scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+			scl_data-&gt;viewport.height == scl_data-&gt;v_active) {</div><div class='add'>+			/* use increased LB size for calculation only if Scaler not enabled */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 1170;</div><div class='add'>+			lb_memory_size_c = 970 + 1290 + 1170;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 1170;</div><div class='add'>+		} else {</div><div class='add'>+			lb_memory_size = 970 + 1290 + 484;</div><div class='add'>+			lb_memory_size_c = 970 + 1290 + 484;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	*num_part_y = lb_memory_size / memory_line_size_y;</div><div class='add'>+	*num_part_c = lb_memory_size_c / memory_line_size_c;</div><div class='add'>+	num_partitions_a = lb_memory_size_a / memory_line_size_a;</div><div class='add'>+</div><div class='add'>+	if (alpha_en</div><div class='add'>+			&amp;&amp; (num_partitions_a &lt; *num_part_y))</div><div class='add'>+		*num_part_y = num_partitions_a;</div><div class='add'>+</div><div class='add'>+	if (*num_part_y &gt; 32)</div><div class='add'>+		*num_part_y = 32;</div><div class='add'>+	if (*num_part_c &gt; 32)</div><div class='add'>+		*num_part_c = 32;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h<br/>index 572958d287eb..f33dddbfcc31 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h</a></div><div class='hunk'>@@ -35,4 +35,11 @@ bool dpp32_construct(struct dcn3_dpp *dpp3,</div><div class='ctx'> 	const struct dcn3_dpp_shift *tf_shift,</div><div class='ctx'> 	const struct dcn3_dpp_mask *tf_mask);</div><div class='ctx'> </div><div class='add'>+void dscl32_spl_calc_lb_num_partitions(</div><div class='add'>+		bool alpha_en,</div><div class='add'>+		const struct spl_scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c);</div><div class='add'>+</div><div class='ctx'> #endif /* __DCN32_DPP_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c<br/>new file mode 100644<br/>index 000000000000..977d83bf7741<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c</a></div><div class='hunk'>@@ -0,0 +1,150 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dcn35/dcn35_dpp.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+</div><div class='add'>+#define REG(reg) dpp-&gt;tf_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX dpp-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name)                                       \</div><div class='add'>+	((const struct dcn35_dpp_shift *)(dpp-&gt;tf_shift))-&gt;field_name, \</div><div class='add'>+	((const struct dcn35_dpp_mask *)(dpp-&gt;tf_mask))-&gt;field_name</div><div class='add'>+</div><div class='add'>+void dpp35_dppclk_control(</div><div class='add'>+		struct dpp *dpp_base,</div><div class='add'>+		bool dppclk_div,</div><div class='add'>+		bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (dpp-&gt;tf_mask-&gt;DPPCLK_RATE_CONTROL)</div><div class='add'>+			REG_UPDATE_2(DPP_CONTROL,</div><div class='add'>+				DPPCLK_RATE_CONTROL, dppclk_div,</div><div class='add'>+				DPP_CLOCK_ENABLE, 1);</div><div class='add'>+		else</div><div class='add'>+			if (dpp-&gt;dispclk_r_gate_disable)</div><div class='add'>+				REG_UPDATE_2(DPP_CONTROL,</div><div class='add'>+					DPP_CLOCK_ENABLE, 1,</div><div class='add'>+					DISPCLK_R_GATE_DISABLE, 1);</div><div class='add'>+			else</div><div class='add'>+				REG_UPDATE(DPP_CONTROL,</div><div class='add'>+						DPP_CLOCK_ENABLE, 1);</div><div class='add'>+	} else</div><div class='add'>+		if (dpp-&gt;dispclk_r_gate_disable)</div><div class='add'>+			REG_UPDATE_2(DPP_CONTROL,</div><div class='add'>+				DPP_CLOCK_ENABLE, 0,</div><div class='add'>+				DISPCLK_R_GATE_DISABLE, 0);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE(DPP_CONTROL,</div><div class='add'>+					DPP_CLOCK_ENABLE, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dpp35_program_bias_and_scale_fcnv(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	struct dc_bias_and_scale *params)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;bias_and_scale_valid) {</div><div class='add'>+		REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, 0);</div><div class='add'>+		REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, 0);</div><div class='add'>+		REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, 0);</div><div class='add'>+</div><div class='add'>+		REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, 0x1F000);</div><div class='add'>+		REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, 0x1F000);</div><div class='add'>+		REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, 0x1F000);</div><div class='add'>+	} else {</div><div class='add'>+		REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, params-&gt;bias_red);</div><div class='add'>+		REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, params-&gt;bias_green);</div><div class='add'>+		REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, params-&gt;bias_blue);</div><div class='add'>+</div><div class='add'>+		REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, params-&gt;scale_red);</div><div class='add'>+		REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, params-&gt;scale_green);</div><div class='add'>+		REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, params-&gt;scale_blue);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dpp_funcs dcn35_dpp_funcs = {</div><div class='add'>+	.dpp_program_gamcor_lut		= dpp3_program_gamcor_lut,</div><div class='add'>+	.dpp_read_state				= dpp30_read_state,</div><div class='add'>+	.dpp_read_reg_state			= dpp30_read_reg_state,</div><div class='add'>+	.dpp_reset					= dpp_reset,</div><div class='add'>+	.dpp_set_scaler				= dpp1_dscl_set_scaler_manual_scale,</div><div class='add'>+	.dpp_get_optimal_number_of_taps	= dpp3_get_optimal_number_of_taps,</div><div class='add'>+	.dpp_set_gamut_remap		= dpp3_cm_set_gamut_remap,</div><div class='add'>+	.dpp_set_csc_adjustment		= NULL,</div><div class='add'>+	.dpp_set_csc_default		= NULL,</div><div class='add'>+	.dpp_program_regamma_pwl	= NULL,</div><div class='add'>+	.dpp_set_pre_degam			= dpp3_set_pre_degam,</div><div class='add'>+	.dpp_program_input_lut		= NULL,</div><div class='add'>+	.dpp_full_bypass			= dpp1_full_bypass,</div><div class='add'>+	.dpp_setup					= dpp3_cnv_setup,</div><div class='add'>+	.dpp_program_degamma_pwl	= NULL,</div><div class='add'>+	.dpp_program_cm_dealpha		= dpp3_program_cm_dealpha,</div><div class='add'>+	.dpp_program_cm_bias		= dpp3_program_cm_bias,</div><div class='add'>+</div><div class='add'>+	.dpp_program_blnd_lut		= NULL, // BLNDGAM is removed completely in DCN3.2 DPP</div><div class='add'>+	.dpp_program_shaper_lut		= NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)</div><div class='add'>+	.dpp_program_3dlut			= NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)</div><div class='add'>+</div><div class='add'>+	.dpp_program_bias_and_scale	= dpp35_program_bias_and_scale_fcnv,</div><div class='add'>+	.dpp_cnv_set_alpha_keyer	= dpp2_cnv_set_alpha_keyer,</div><div class='add'>+	.set_cursor_attributes		= dpp3_set_cursor_attributes,</div><div class='add'>+	.set_cursor_position		= dpp1_set_cursor_position,</div><div class='add'>+	.set_optional_cursor_attributes	= dpp1_cnv_set_optional_cursor_attributes,</div><div class='add'>+	.dpp_dppclk_control			= dpp35_dppclk_control,</div><div class='add'>+	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,</div><div class='add'>+	.dpp_get_gamut_remap		= dpp3_cm_get_gamut_remap,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dpp35_construct(</div><div class='add'>+	struct dcn3_dpp *dpp, struct dc_context *ctx,</div><div class='add'>+	uint32_t inst, const struct dcn3_dpp_registers *tf_regs,</div><div class='add'>+	const struct dcn35_dpp_shift *tf_shift,</div><div class='add'>+	const struct dcn35_dpp_mask *tf_mask)</div><div class='add'>+{</div><div class='add'>+	bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,</div><div class='add'>+			      (const struct dcn3_dpp_shift *)(tf_shift),</div><div class='add'>+			      (const struct dcn3_dpp_mask *)(tf_mask));</div><div class='add'>+</div><div class='add'>+	dpp-&gt;base.funcs = &amp;dcn35_dpp_funcs;</div><div class='add'>+</div><div class='add'>+	// w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs</div><div class='add'>+	if (dpp-&gt;base.ctx-&gt;asic_id.hw_internal_rev &lt; 0x40)</div><div class='add'>+		dpp-&gt;dispclk_r_gate_disable = true;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h<br/>index 09b84307cd9e..3ca339a16e5b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h</a></div><div class='hunk'>@@ -31,7 +31,9 @@</div><div class='ctx'> </div><div class='ctx'> #define DPP_REG_LIST_SH_MASK_DCN35(mask_sh)  \</div><div class='ctx'> 	DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \</div><div class='del'>-		TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh)</div><div class='add'>+		TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh), \</div><div class='add'>+		TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh), \</div><div class='add'>+		TF_SF(DPP_TOP0_DPP_CONTROL, DISPCLK_R_GATE_DISABLE, mask_sh)</div><div class='ctx'> </div><div class='ctx'> #define DPP_REG_FIELD_LIST_DCN35(type)         \</div><div class='ctx'> 	struct {                               \</div><div class='hunk'>@@ -47,6 +49,11 @@ struct dcn35_dpp_mask {</div><div class='ctx'> 	DPP_REG_FIELD_LIST_DCN35(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+void dpp35_dppclk_control(</div><div class='add'>+		struct dpp *dpp_base,</div><div class='add'>+		bool dppclk_div,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='ctx'> bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx,</div><div class='ctx'> 		     uint32_t inst, const struct dcn3_dpp_registers *tf_regs,</div><div class='ctx'> 		     const struct dcn35_dpp_shift *tf_shift,</div><div class='hunk'>@@ -54,4 +61,7 @@ bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx,</div><div class='ctx'> </div><div class='ctx'> void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);</div><div class='ctx'> </div><div class='add'>+void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,</div><div class='add'>+		struct dc_bias_and_scale *bias_and_scale);</div><div class='add'>+</div><div class='ctx'> #endif // __DCN35_DPP_H</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c<br/>new file mode 100644<br/>index 000000000000..96c2c853de42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c</a></div><div class='hunk'>@@ -0,0 +1,429 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dcn401/dcn401_dpp.h"</div><div class='add'>+#include "basics/conversion.h"</div><div class='add'>+#include "dcn30/dcn30_cm_common.h"</div><div class='add'>+#include "dcn32/dcn32_dpp.h"</div><div class='add'>+#include "dcn35/dcn35_dpp.h"</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	dpp-&gt;tf_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	dpp-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	dpp-&gt;tf_shift-&gt;field_name, dpp-&gt;tf_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)</div><div class='add'>+{</div><div class='add'>+	struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	REG_GET(DPP_CONTROL,</div><div class='add'>+		DPP_CLOCK_ENABLE, &amp;s-&gt;is_enabled);</div><div class='add'>+</div><div class='add'>+	// TODO: Implement for DCN4</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dpp401_dpp_setup(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	enum surface_pixel_format format,</div><div class='add'>+	enum expansion_mode mode,</div><div class='add'>+	struct dc_csc_transform input_csc_color_matrix,</div><div class='add'>+	enum dc_color_space input_color_space,</div><div class='add'>+	struct cnv_alpha_2bit_lut *alpha_2bit_lut)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+	uint32_t pixel_format = 0;</div><div class='add'>+	uint32_t alpha_en = 1;</div><div class='add'>+	enum dc_color_space color_space = COLOR_SPACE_SRGB;</div><div class='add'>+	enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;</div><div class='add'>+	uint32_t is_2bit = 0;</div><div class='add'>+	uint32_t alpha_plane_enable = 0;</div><div class='add'>+	uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;</div><div class='add'>+	uint32_t realpha_en = 0, realpha_ablnd_en = 0;</div><div class='add'>+	struct out_csc_color_matrix tbl_entry;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	REG_SET_2(FORMAT_CONTROL, 0,</div><div class='add'>+		CNVC_BYPASS, 0,</div><div class='add'>+		FORMAT_EXPANSION_MODE, mode);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);</div><div class='add'>+</div><div class='add'>+	switch (format) {</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:</div><div class='add'>+		pixel_format = 1;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:</div><div class='add'>+		pixel_format = 3;</div><div class='add'>+		alpha_en = 0;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:</div><div class='add'>+		pixel_format = 8;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:</div><div class='add'>+		pixel_format = 10;</div><div class='add'>+		is_2bit = 1;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:</div><div class='add'>+		pixel_format = 65;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:</div><div class='add'>+		pixel_format = 64;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:</div><div class='add'>+		pixel_format = 67;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:</div><div class='add'>+		pixel_format = 66;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:</div><div class='add'>+		pixel_format = 26; /* ARGB16161616_UNORM */</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:</div><div class='add'>+		pixel_format = 24;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:</div><div class='add'>+		pixel_format = 25;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:</div><div class='add'>+		pixel_format = 12;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:</div><div class='add'>+		pixel_format = 112;</div><div class='add'>+		alpha_en = 0;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:</div><div class='add'>+		pixel_format = 113;</div><div class='add'>+		alpha_en = 0;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:</div><div class='add'>+		pixel_format = 114;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		is_2bit = 1;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:</div><div class='add'>+		pixel_format = 115;</div><div class='add'>+		color_space = COLOR_SPACE_YCBCR709;</div><div class='add'>+		select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		is_2bit = 1;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:</div><div class='add'>+		pixel_format = 116;</div><div class='add'>+		alpha_plane_enable = 0;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:</div><div class='add'>+		pixel_format = 116;</div><div class='add'>+		alpha_plane_enable = 1;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:</div><div class='add'>+		pixel_format = 118;</div><div class='add'>+		alpha_en = 0;</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:</div><div class='add'>+		pixel_format = 119;</div><div class='add'>+		alpha_en = 0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set default color space based on format if none is given. */</div><div class='add'>+	color_space = input_color_space ? input_color_space : color_space;</div><div class='add'>+</div><div class='add'>+	if (is_2bit == 1 &amp;&amp; alpha_2bit_lut != NULL) {</div><div class='add'>+		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut-&gt;lut0);</div><div class='add'>+		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut-&gt;lut1);</div><div class='add'>+		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut-&gt;lut2);</div><div class='add'>+		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut-&gt;lut3);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,</div><div class='add'>+		CNVC_SURFACE_PIXEL_FORMAT, pixel_format,</div><div class='add'>+		CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);</div><div class='add'>+	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(PRE_DEALPHA, 0,</div><div class='add'>+		PRE_DEALPHA_EN, dealpha_en,</div><div class='add'>+		PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);</div><div class='add'>+	REG_SET_2(PRE_REALPHA, 0,</div><div class='add'>+		PRE_REALPHA_EN, realpha_en,</div><div class='add'>+		PRE_REALPHA_ABLND_EN, realpha_ablnd_en);</div><div class='add'>+</div><div class='add'>+	/* If input adjustment exists, program the ICSC with those values. */</div><div class='add'>+	if (input_csc_color_matrix.enable_adjustment == true) {</div><div class='add'>+		for (i = 0; i &lt; 12; i++)</div><div class='add'>+			tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];</div><div class='add'>+</div><div class='add'>+		tbl_entry.color_space = input_color_space;</div><div class='add'>+</div><div class='add'>+		if (color_space &gt;= COLOR_SPACE_YCBCR601)</div><div class='add'>+			select = INPUT_CSC_SELECT_ICSC;</div><div class='add'>+		else</div><div class='add'>+			select = INPUT_CSC_SELECT_BYPASS;</div><div class='add'>+</div><div class='add'>+		dpp3_program_post_csc(dpp_base, color_space, select,</div><div class='add'>+			&amp;tbl_entry);</div><div class='add'>+	} else {</div><div class='add'>+		dpp3_program_post_csc(dpp_base, color_space, select, NULL);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static struct dpp_funcs dcn401_dpp_funcs = {</div><div class='add'>+	.dpp_program_gamcor_lut		= dpp3_program_gamcor_lut,</div><div class='add'>+	.dpp_read_state				= dpp401_read_state,</div><div class='add'>+	.dpp_reset					= dpp_reset,</div><div class='add'>+	.dpp_set_scaler				= dpp401_dscl_set_scaler_manual_scale,</div><div class='add'>+	.dpp_get_optimal_number_of_taps	= dpp3_get_optimal_number_of_taps,</div><div class='add'>+	.dpp_set_gamut_remap		= NULL,</div><div class='add'>+	.dpp_set_csc_adjustment		= NULL,</div><div class='add'>+	.dpp_set_csc_default		= NULL,</div><div class='add'>+	.dpp_program_regamma_pwl	= NULL,</div><div class='add'>+	.dpp_set_pre_degam			= dpp3_set_pre_degam,</div><div class='add'>+	.dpp_program_input_lut		= NULL,</div><div class='add'>+	.dpp_full_bypass			= NULL,</div><div class='add'>+	.dpp_setup					= dpp401_dpp_setup,</div><div class='add'>+	.dpp_program_degamma_pwl	= NULL,</div><div class='add'>+	.dpp_program_cm_dealpha		= dpp3_program_cm_dealpha,</div><div class='add'>+	.dpp_program_cm_bias		= dpp3_program_cm_bias,</div><div class='add'>+</div><div class='add'>+	.dpp_program_blnd_lut		= NULL, // BLNDGAM is removed completely in DCN3.2 DPP</div><div class='add'>+	.dpp_program_shaper_lut		= NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)</div><div class='add'>+	.dpp_program_3dlut			= NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)</div><div class='add'>+</div><div class='add'>+	.dpp_program_bias_and_scale	= dpp35_program_bias_and_scale_fcnv,</div><div class='add'>+	.dpp_cnv_set_alpha_keyer	= dpp2_cnv_set_alpha_keyer,</div><div class='add'>+	.set_cursor_attributes		= dpp401_set_cursor_attributes,</div><div class='add'>+	.set_cursor_position		= dpp401_set_cursor_position,</div><div class='add'>+	.set_optional_cursor_attributes	= dpp401_set_optional_cursor_attributes,</div><div class='add'>+	.dpp_dppclk_control			= dpp1_dppclk_control,</div><div class='add'>+	.dpp_set_hdr_multiplier		= dpp3_set_hdr_multiplier,</div><div class='add'>+	.dpp_read_reg_state			= dpp30_read_reg_state,</div><div class='add'>+	.set_cursor_matrix			= dpp401_set_cursor_matrix,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static struct dpp_caps dcn401_dpp_cap = {</div><div class='add'>+	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,</div><div class='add'>+	.max_lb_partitions = 63,</div><div class='add'>+	.dscl_calc_lb_num_partitions = dscl401_calc_lb_num_partitions,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dpp401_construct(</div><div class='add'>+	struct dcn401_dpp *dpp,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst,</div><div class='add'>+	const struct dcn401_dpp_registers *tf_regs,</div><div class='add'>+	const struct dcn401_dpp_shift *tf_shift,</div><div class='add'>+	const struct dcn401_dpp_mask *tf_mask)</div><div class='add'>+{</div><div class='add'>+	dpp-&gt;base.ctx = ctx;</div><div class='add'>+</div><div class='add'>+	dpp-&gt;base.inst = inst;</div><div class='add'>+	dpp-&gt;base.funcs = &amp;dcn401_dpp_funcs;</div><div class='add'>+	dpp-&gt;base.caps = &amp;dcn401_dpp_cap;</div><div class='add'>+</div><div class='add'>+	dpp-&gt;tf_regs = tf_regs;</div><div class='add'>+	dpp-&gt;tf_shift = tf_shift;</div><div class='add'>+	dpp-&gt;tf_mask = tf_mask;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+/* Compute the maximum number of lines that we can fit in the line buffer */</div><div class='add'>+</div><div class='add'>+void dscl401_calc_lb_num_partitions(</div><div class='add'>+		const struct scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c)</div><div class='add'>+{</div><div class='add'>+	int memory_line_size_y, memory_line_size_c, memory_line_size_a,</div><div class='add'>+	lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;</div><div class='add'>+</div><div class='add'>+	int line_size = scl_data-&gt;viewport.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport.width : scl_data-&gt;recout.width;</div><div class='add'>+	int line_size_c = scl_data-&gt;viewport_c.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport_c.width : scl_data-&gt;recout.width;</div><div class='add'>+</div><div class='add'>+	if (line_size == 0)</div><div class='add'>+		line_size = 1;</div><div class='add'>+</div><div class='add'>+	if (line_size_c == 0)</div><div class='add'>+		line_size_c = 1;</div><div class='add'>+</div><div class='add'>+	memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+</div><div class='add'>+	if (lb_config == LB_MEMORY_CONFIG_1) {</div><div class='add'>+		lb_memory_size = 970;</div><div class='add'>+		lb_memory_size_c = 970;</div><div class='add'>+		lb_memory_size_a = 970;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_2) {</div><div class='add'>+		lb_memory_size = 1290;</div><div class='add'>+		lb_memory_size_c = 1290;</div><div class='add'>+		lb_memory_size_a = 1290;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_3) {</div><div class='add'>+		if (scl_data-&gt;viewport.width  == scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+			scl_data-&gt;viewport.height == scl_data-&gt;v_active) {</div><div class='add'>+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */</div><div class='add'>+			/* use increased LB size for calculation only if Scaler not enabled */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;</div><div class='add'>+			lb_memory_size_c = 970 + 1290;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 1170;</div><div class='add'>+		} else {</div><div class='add'>+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 484 + 484 + 484;</div><div class='add'>+			lb_memory_size_c = 970 + 1290;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (scl_data-&gt;viewport.width  == scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+			scl_data-&gt;viewport.height == scl_data-&gt;v_active) {</div><div class='add'>+			/* use increased LB size for calculation only if Scaler not enabled */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 1170;</div><div class='add'>+			lb_memory_size_c = 970 + 1290 + 1170;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 1170;</div><div class='add'>+		} else {</div><div class='add'>+			lb_memory_size = 970 + 1290 + 484;</div><div class='add'>+			lb_memory_size_c = 970 + 1290 + 484;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	*num_part_y = lb_memory_size / memory_line_size_y;</div><div class='add'>+	*num_part_c = lb_memory_size_c / memory_line_size_c;</div><div class='add'>+	num_partitions_a = lb_memory_size_a / memory_line_size_a;</div><div class='add'>+</div><div class='add'>+	if (scl_data-&gt;lb_params.alpha_en</div><div class='add'>+			&amp;&amp; (num_partitions_a &lt; *num_part_y))</div><div class='add'>+		*num_part_y = num_partitions_a;</div><div class='add'>+</div><div class='add'>+	if (*num_part_y &gt; 64)</div><div class='add'>+		*num_part_y = 64;</div><div class='add'>+	if (*num_part_c &gt; 64)</div><div class='add'>+		*num_part_c = 64;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Compute the maximum number of lines that we can fit in the line buffer */</div><div class='add'>+void dscl401_spl_calc_lb_num_partitions(</div><div class='add'>+		bool alpha_en,</div><div class='add'>+		const struct spl_scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c)</div><div class='add'>+{</div><div class='add'>+	int memory_line_size_y, memory_line_size_c, memory_line_size_a,</div><div class='add'>+	lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;</div><div class='add'>+</div><div class='add'>+	int line_size = scl_data-&gt;viewport.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport.width : scl_data-&gt;recout.width;</div><div class='add'>+	int line_size_c = scl_data-&gt;viewport_c.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+			scl_data-&gt;viewport_c.width : scl_data-&gt;recout.width;</div><div class='add'>+</div><div class='add'>+	if (line_size == 0)</div><div class='add'>+		line_size = 1;</div><div class='add'>+</div><div class='add'>+	if (line_size_c == 0)</div><div class='add'>+		line_size_c = 1;</div><div class='add'>+</div><div class='add'>+	memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */</div><div class='add'>+	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+</div><div class='add'>+	if (lb_config == LB_MEMORY_CONFIG_1) {</div><div class='add'>+		lb_memory_size = 970;</div><div class='add'>+		lb_memory_size_c = 970;</div><div class='add'>+		lb_memory_size_a = 970;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_2) {</div><div class='add'>+		lb_memory_size = 1290;</div><div class='add'>+		lb_memory_size_c = 1290;</div><div class='add'>+		lb_memory_size_a = 1290;</div><div class='add'>+	} else if (lb_config == LB_MEMORY_CONFIG_3) {</div><div class='add'>+		if (scl_data-&gt;viewport.width  == scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+			scl_data-&gt;viewport.height == scl_data-&gt;v_active) {</div><div class='add'>+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */</div><div class='add'>+			/* use increased LB size for calculation only if Scaler not enabled */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;</div><div class='add'>+			lb_memory_size_c = 970 + 1290;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 1170;</div><div class='add'>+		} else {</div><div class='add'>+			/* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 484 + 484 + 484;</div><div class='add'>+			lb_memory_size_c = 970 + 1290;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (scl_data-&gt;viewport.width  == scl_data-&gt;h_active &amp;&amp;</div><div class='add'>+			scl_data-&gt;viewport.height == scl_data-&gt;v_active) {</div><div class='add'>+			/* use increased LB size for calculation only if Scaler not enabled */</div><div class='add'>+			lb_memory_size = 970 + 1290 + 1170;</div><div class='add'>+			lb_memory_size_c = 970 + 1290 + 1170;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 1170;</div><div class='add'>+		} else {</div><div class='add'>+			lb_memory_size = 970 + 1290 + 484;</div><div class='add'>+			lb_memory_size_c = 970 + 1290 + 484;</div><div class='add'>+			lb_memory_size_a = 970 + 1290 + 484;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	*num_part_y = lb_memory_size / memory_line_size_y;</div><div class='add'>+	*num_part_c = lb_memory_size_c / memory_line_size_c;</div><div class='add'>+	num_partitions_a = lb_memory_size_a / memory_line_size_a;</div><div class='add'>+</div><div class='add'>+	if (alpha_en &amp;&amp; (num_partitions_a &lt; *num_part_y))</div><div class='add'>+		*num_part_y = num_partitions_a;</div><div class='add'>+</div><div class='add'>+	if (*num_part_y &gt; 64)</div><div class='add'>+		*num_part_y = 64;</div><div class='add'>+	if (*num_part_c &gt; 64)</div><div class='add'>+		*num_part_c = 64;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h<br/>new file mode 100644<br/>index 000000000000..5f6b431ec398<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h</a></div><div class='hunk'>@@ -0,0 +1,740 @@</div><div class='add'>+/* Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DCN401_DPP_H__</div><div class='add'>+#define __DCN401_DPP_H__</div><div class='add'>+</div><div class='add'>+#include "dcn20/dcn20_dpp.h"</div><div class='add'>+#include "dcn30/dcn30_dpp.h"</div><div class='add'>+#include "dcn32/dcn32_dpp.h"</div><div class='add'>+</div><div class='add'>+#define TO_DCN401_DPP(dpp)\</div><div class='add'>+	container_of(dpp, struct dcn401_dpp, base)</div><div class='add'>+</div><div class='add'>+#define DPP_REG_LIST_SH_MASK_DCN401_COMMON(mask_sh)\</div><div class='add'>+	TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\</div><div class='add'>+	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\</div><div class='add'>+	TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \</div><div class='add'>+	TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_COEF_FORMAT, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C11_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C12_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C13_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C14_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C21_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C22_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C23_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C24_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C31_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C32_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C33_A, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C34_A, mask_sh), \</div><div class='add'>+	TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \</div><div class='add'>+	TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \</div><div class='add'>+	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \</div><div class='add'>+	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \</div><div class='add'>+	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, LUMA_KEYER_EN, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \</div><div class='add'>+	TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \</div><div class='add'>+	TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_RINGEST_FORCE_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_2TAP_SHARP_FACTOR, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF1_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF3_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT1_GAIN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT2_GAIN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_ROC_GAIN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXA, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXB, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINA, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINB, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_IN_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_BASE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_SLOPE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_IN_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_BASE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_SLOPE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_IN_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_BASE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_SLOPE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_IN_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_BASE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_SLOPE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_IN_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_BASE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_SLOPE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_IN_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_BASE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_SLOPE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_IN_SEG6, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_BASE_SEG6, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_SLOPE_SEG6, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_IN_SEG7, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_BASE_SEG7, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_IN_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_BASE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_SLOPE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_IN_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_BASE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_SLOPE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_IN_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_BASE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_SLOPE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_IN_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_BASE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_SLOPE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_IN_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_BASE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_SLOPE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_IN_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_BASE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_RINGEST_FORCE_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_2TAP_SHARP_FACTOR, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF1_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF3_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT1_GAIN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT2_GAIN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_ROC_GAIN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXA, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXB, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINA, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINB, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_IN_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_BASE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_SLOPE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_IN_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_BASE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_SLOPE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_IN_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_BASE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_SLOPE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_IN_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_BASE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_SLOPE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_IN_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_BASE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_SLOPE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_IN_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_BASE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_SLOPE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_IN_SEG6, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_BASE_SEG6, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_SLOPE_SEG6, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_IN_SEG7, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_BASE_SEG7, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_IN_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_BASE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_SLOPE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_IN_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_BASE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_SLOPE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_IN_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_BASE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_SLOPE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_IN_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_BASE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_SLOPE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_IN_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_BASE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_SLOPE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_IN_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_BASE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_EN, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_LBA_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_MODE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_NORM, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT_CURRENT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_IN_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_BASE_SEG0, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_SLOPE_SEG0, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_IN_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_BASE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_SLOPE_SEG1, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_IN_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_BASE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_SLOPE_SEG2, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_IN_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_BASE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_SLOPE_SEG3, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_IN_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_BASE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_SLOPE_SEG4, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_IN_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_BASE_SEG5, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_UTHRE, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_DTHRE, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_START_IN, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_END_IN, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_SLOPE, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_P, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_P, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_P, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_N, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_N, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_N, mask_sh), \</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\</div><div class='add'>+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh)</div><div class='add'>+</div><div class='add'>+#define DPP_REG_FIELD_LIST_DCN401(type) \</div><div class='add'>+	DPP_REG_FIELD_LIST_DCN3(type); \</div><div class='add'>+	type CUR0_FP_BIAS_G_Y; \</div><div class='add'>+	type CUR0_FP_SCALE_G_Y; \</div><div class='add'>+	type CUR0_FP_BIAS_RB_CRCB; \</div><div class='add'>+	type CUR0_FP_SCALE_RB_CRCB; \</div><div class='add'>+	type CUR0_MATRIX_MODE; \</div><div class='add'>+	type CUR0_MATRIX_MODE_CURRENT; \</div><div class='add'>+	type CUR0_MATRIX_COEF_FORMAT; \</div><div class='add'>+	type CUR0_MATRIX_C11_A; \</div><div class='add'>+	type CUR0_MATRIX_C12_A; \</div><div class='add'>+	type CUR0_MATRIX_C13_A; \</div><div class='add'>+	type CUR0_MATRIX_C14_A; \</div><div class='add'>+	type CUR0_MATRIX_C21_A; \</div><div class='add'>+	type CUR0_MATRIX_C22_A; \</div><div class='add'>+	type CUR0_MATRIX_C23_A; \</div><div class='add'>+	type CUR0_MATRIX_C24_A; \</div><div class='add'>+	type CUR0_MATRIX_C31_A; \</div><div class='add'>+	type CUR0_MATRIX_C32_A; \</div><div class='add'>+	type CUR0_MATRIX_C33_A; \</div><div class='add'>+	type CUR0_MATRIX_C34_A; \</div><div class='add'>+	type LUMA_KEYER_EN;	\</div><div class='add'>+	type SCL_SC_MATRIX_MODE; \</div><div class='add'>+	type SCL_SC_LTONL_EN; \</div><div class='add'>+	type SCL_EASF_H_EN; \</div><div class='add'>+	type SCL_EASF_H_RINGEST_FORCE_EN; \</div><div class='add'>+	type SCL_EASF_H_2TAP_SHARP_FACTOR; \</div><div class='add'>+	type SCL_EASF_H_BF1_EN; \</div><div class='add'>+	type SCL_EASF_H_BF2_MODE; \</div><div class='add'>+	type SCL_EASF_H_BF3_MODE; \</div><div class='add'>+	type SCL_EASF_H_BF2_FLAT1_GAIN; \</div><div class='add'>+	type SCL_EASF_H_BF2_FLAT2_GAIN; \</div><div class='add'>+	type SCL_EASF_H_BF2_ROC_GAIN; \</div><div class='add'>+	type SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1; \</div><div class='add'>+	type SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2; \</div><div class='add'>+	type SCL_EASF_H_RINGEST_EVENTAP_GAIN1; \</div><div class='add'>+	type SCL_EASF_H_RINGEST_EVENTAP_GAIN2; \</div><div class='add'>+	type SCL_EASF_H_BF_MAXA; \</div><div class='add'>+	type SCL_EASF_H_BF_MAXB; \</div><div class='add'>+	type SCL_EASF_H_BF_MINA; \</div><div class='add'>+	type SCL_EASF_H_BF_MINB; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG0; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG0; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG0; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG1; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG1; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG1; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG2; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG2; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG2; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG3; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG3; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG3; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG4; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG4; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG4; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG5; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG5; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG5; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG6; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG6; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_SLOPE_SEG6; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_IN_SEG7; \</div><div class='add'>+	type SCL_EASF_H_BF1_PWL_BASE_SEG7; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_IN_SEG0; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_BASE_SEG0; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_SLOPE_SEG0; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_IN_SEG1; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_BASE_SEG1; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_SLOPE_SEG1; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_IN_SEG2; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_BASE_SEG2; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_SLOPE_SEG2; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_IN_SEG3; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_BASE_SEG3; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_SLOPE_SEG3; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_IN_SEG4; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_BASE_SEG4; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_SLOPE_SEG4; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_IN_SEG5; \</div><div class='add'>+	type SCL_EASF_H_BF3_PWL_BASE_SEG5; \</div><div class='add'>+	type SCL_EASF_V_EN; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_FORCE_EN; \</div><div class='add'>+	type SCL_EASF_V_2TAP_SHARP_FACTOR; \</div><div class='add'>+	type SCL_EASF_V_BF1_EN; \</div><div class='add'>+	type SCL_EASF_V_BF2_MODE; \</div><div class='add'>+	type SCL_EASF_V_BF3_MODE; \</div><div class='add'>+	type SCL_EASF_V_BF2_FLAT1_GAIN; \</div><div class='add'>+	type SCL_EASF_V_BF2_FLAT2_GAIN; \</div><div class='add'>+	type SCL_EASF_V_BF2_ROC_GAIN; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_EVENTAP_GAIN1; \</div><div class='add'>+	type SCL_EASF_V_RINGEST_EVENTAP_GAIN2; \</div><div class='add'>+	type SCL_EASF_V_BF_MAXA; \</div><div class='add'>+	type SCL_EASF_V_BF_MAXB; \</div><div class='add'>+	type SCL_EASF_V_BF_MINA; \</div><div class='add'>+	type SCL_EASF_V_BF_MINB; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG0; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG0; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG0; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG1; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG1; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG1; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG2; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG2; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG2; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG3; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG3; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG3; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG4; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG4; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG4; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG5; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG5; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG5; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG6; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG6; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_SLOPE_SEG6; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_IN_SEG7; \</div><div class='add'>+	type SCL_EASF_V_BF1_PWL_BASE_SEG7; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_IN_SEG0; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_BASE_SEG0; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_SLOPE_SEG0; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_IN_SEG1; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_BASE_SEG1; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_SLOPE_SEG1; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_IN_SEG2; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_BASE_SEG2; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_SLOPE_SEG2; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_IN_SEG3; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_BASE_SEG3; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_SLOPE_SEG3; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_IN_SEG4; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_BASE_SEG4; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_SLOPE_SEG4; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_IN_SEG5; \</div><div class='add'>+	type SCL_EASF_V_BF3_PWL_BASE_SEG5; \</div><div class='add'>+	type SCL_SC_MATRIX_C0; \</div><div class='add'>+	type SCL_SC_MATRIX_C1; \</div><div class='add'>+	type SCL_SC_MATRIX_C2; \</div><div class='add'>+	type SCL_SC_MATRIX_C3; \</div><div class='add'>+	type ISHARP_EN;	\</div><div class='add'>+	type ISHARP_NOISEDET_EN;	\</div><div class='add'>+	type ISHARP_NOISEDET_MODE;	\</div><div class='add'>+	type ISHARP_NOISEDET_UTHRE;	\</div><div class='add'>+	type ISHARP_NOISEDET_DTHRE;	\</div><div class='add'>+	type ISHARP_NOISEDET_PWL_START_IN;	\</div><div class='add'>+	type ISHARP_NOISEDET_PWL_END_IN;	\</div><div class='add'>+	type ISHARP_NOISEDET_PWL_SLOPE;	\</div><div class='add'>+	type ISHARP_LBA_MODE;	\</div><div class='add'>+	type ISHARP_LBA_PWL_IN_SEG0;	\</div><div class='add'>+	type ISHARP_LBA_PWL_BASE_SEG0;	\</div><div class='add'>+	type ISHARP_LBA_PWL_SLOPE_SEG0;	\</div><div class='add'>+	type ISHARP_LBA_PWL_IN_SEG1;	\</div><div class='add'>+	type ISHARP_LBA_PWL_BASE_SEG1;	\</div><div class='add'>+	type ISHARP_LBA_PWL_SLOPE_SEG1;	\</div><div class='add'>+	type ISHARP_LBA_PWL_IN_SEG2;	\</div><div class='add'>+	type ISHARP_LBA_PWL_BASE_SEG2;	\</div><div class='add'>+	type ISHARP_LBA_PWL_SLOPE_SEG2;	\</div><div class='add'>+	type ISHARP_LBA_PWL_IN_SEG3;	\</div><div class='add'>+	type ISHARP_LBA_PWL_BASE_SEG3;	\</div><div class='add'>+	type ISHARP_LBA_PWL_SLOPE_SEG3;	\</div><div class='add'>+	type ISHARP_LBA_PWL_IN_SEG4;	\</div><div class='add'>+	type ISHARP_LBA_PWL_BASE_SEG4;	\</div><div class='add'>+	type ISHARP_LBA_PWL_SLOPE_SEG4;	\</div><div class='add'>+	type ISHARP_LBA_PWL_IN_SEG5;	\</div><div class='add'>+	type ISHARP_LBA_PWL_BASE_SEG5;	\</div><div class='add'>+	type ISHARP_FMT_MODE;	\</div><div class='add'>+	type ISHARP_FMT_NORM;	\</div><div class='add'>+	type ISHARP_DELTA_LUT_SELECT;	\</div><div class='add'>+	type ISHARP_DELTA_LUT_SELECT_CURRENT;	\</div><div class='add'>+	type ISHARP_DELTA_LUT_HOST_SELECT;	\</div><div class='add'>+	type ISHARP_DELTA_DATA;	\</div><div class='add'>+	type ISHARP_DELTA_INDEX; \</div><div class='add'>+	type ISHARP_NLDELTA_SCLIP_EN_P;	\</div><div class='add'>+	type ISHARP_NLDELTA_SCLIP_PIVOT_P;	\</div><div class='add'>+	type ISHARP_NLDELTA_SCLIP_SLOPE_P;	\</div><div class='add'>+	type ISHARP_NLDELTA_SCLIP_EN_N;	\</div><div class='add'>+	type ISHARP_NLDELTA_SCLIP_PIVOT_N;	\</div><div class='add'>+	type ISHARP_NLDELTA_SCLIP_SLOPE_N</div><div class='add'>+</div><div class='add'>+#define DPP_REG_VARIABLE_LIST_DCN401 \</div><div class='add'>+	DPP_DCN3_REG_VARIABLE_LIST_COMMON; \</div><div class='add'>+	uint32_t CURSOR0_FP_SCALE_BIAS_G_Y; \</div><div class='add'>+	uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB; \</div><div class='add'>+	uint32_t CUR0_MATRIX_MODE; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C11_C12_A; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C13_C14_A; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C21_C22_A; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C23_C24_A; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C31_C32_A; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C33_C34_A; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C11_C12_B; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C13_C14_B; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C21_C22_B; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C23_C24_B; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C31_C32_B; \</div><div class='add'>+	uint32_t CUR0_MATRIX_C33_C34_B; \</div><div class='add'>+	uint32_t DSCL_SC_MODE; \</div><div class='add'>+	uint32_t DSCL_EASF_H_MODE; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF_CNTL; \</div><div class='add'>+	uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE; \</div><div class='add'>+	uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG0; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG1; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG2; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG3; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG4; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG5; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG6; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF1_PWL_SEG7; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF3_PWL_SEG0; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF3_PWL_SEG1; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF3_PWL_SEG2; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF3_PWL_SEG3; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF3_PWL_SEG4; \</div><div class='add'>+	uint32_t DSCL_EASF_H_BF3_PWL_SEG5; \</div><div class='add'>+	uint32_t DSCL_EASF_V_MODE; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF_CNTL; \</div><div class='add'>+	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1; \</div><div class='add'>+	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2; \</div><div class='add'>+	uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3; \</div><div class='add'>+	uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE; \</div><div class='add'>+	uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG0; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG1; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG2; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG3; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG4; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG5; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG6; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF1_PWL_SEG7; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF3_PWL_SEG0; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF3_PWL_SEG1; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF3_PWL_SEG2; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF3_PWL_SEG3; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF3_PWL_SEG4; \</div><div class='add'>+	uint32_t DSCL_EASF_V_BF3_PWL_SEG5; \</div><div class='add'>+	uint32_t DSCL_SC_MATRIX_C0C1; \</div><div class='add'>+	uint32_t DSCL_SC_MATRIX_C2C3; \</div><div class='add'>+	uint32_t ISHARP_MODE; \</div><div class='add'>+	uint32_t ISHARP_NOISEDET_THRESHOLD; \</div><div class='add'>+	uint32_t ISHARP_NOISE_GAIN_PWL; \</div><div class='add'>+	uint32_t ISHARP_LBA_PWL_SEG0; \</div><div class='add'>+	uint32_t ISHARP_LBA_PWL_SEG1; \</div><div class='add'>+	uint32_t ISHARP_LBA_PWL_SEG2; \</div><div class='add'>+	uint32_t ISHARP_LBA_PWL_SEG3; \</div><div class='add'>+	uint32_t ISHARP_LBA_PWL_SEG4; \</div><div class='add'>+	uint32_t ISHARP_LBA_PWL_SEG5; \</div><div class='add'>+	uint32_t ISHARP_DELTA_CTRL; \</div><div class='add'>+	uint32_t ISHARP_DELTA_DATA; \</div><div class='add'>+	uint32_t ISHARP_DELTA_INDEX; \</div><div class='add'>+	uint32_t ISHARP_NLDELTA_SOFT_CLIP</div><div class='add'>+</div><div class='add'>+struct dcn401_dpp_registers {</div><div class='add'>+	DPP_REG_VARIABLE_LIST_DCN401;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_dpp_shift {</div><div class='add'>+	DPP_REG_FIELD_LIST_DCN401(uint8_t);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_dpp_mask {</div><div class='add'>+	DPP_REG_FIELD_LIST_DCN401(uint32_t);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_dpp {</div><div class='add'>+	struct dpp base;</div><div class='add'>+</div><div class='add'>+	const struct dcn401_dpp_registers *tf_regs;</div><div class='add'>+	const struct dcn401_dpp_shift *tf_shift;</div><div class='add'>+	const struct dcn401_dpp_mask *tf_mask;</div><div class='add'>+</div><div class='add'>+	const uint16_t *filter_v;</div><div class='add'>+	const uint16_t *filter_h;</div><div class='add'>+	const uint16_t *filter_v_c;</div><div class='add'>+	const uint16_t *filter_h_c;</div><div class='add'>+	int lb_pixel_depth_supported;</div><div class='add'>+	int lb_memory_size;</div><div class='add'>+	int lb_bits_per_entry;</div><div class='add'>+	bool is_write_to_ram_a_safe;</div><div class='add'>+	struct scaler_data scl_data;</div><div class='add'>+	struct pwl_params pwl_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dcn401_dscl_mode_sel {</div><div class='add'>+	DCN401_DSCL_MODE_SCALING_444_BYPASS = 0,</div><div class='add'>+	DCN401_DSCL_MODE_SCALING_444_RGB_ENABLE = 1,</div><div class='add'>+	DCN401_DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,</div><div class='add'>+	DCN401_DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,</div><div class='add'>+	DCN401_DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,</div><div class='add'>+	DCN401_DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,</div><div class='add'>+	DCN401_DSCL_MODE_DSCL_BYPASS = 6</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool dpp401_construct(struct dcn401_dpp *dpp401,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst,</div><div class='add'>+	const struct dcn401_dpp_registers *tf_regs,</div><div class='add'>+	const struct dcn401_dpp_shift *tf_shift,</div><div class='add'>+	const struct dcn401_dpp_mask *tf_mask);</div><div class='add'>+</div><div class='add'>+void dpp401_dscl_set_scaler_manual_scale(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	const struct scaler_data *scl_data);</div><div class='add'>+</div><div class='add'>+void dpp401_dpp_setup(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	enum surface_pixel_format format,</div><div class='add'>+	enum expansion_mode mode,</div><div class='add'>+	struct dc_csc_transform input_csc_color_matrix,</div><div class='add'>+	enum dc_color_space input_color_space,</div><div class='add'>+	struct cnv_alpha_2bit_lut *alpha_2bit_lut);</div><div class='add'>+</div><div class='add'>+void dpp401_set_cursor_attributes(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	struct dc_cursor_attributes *cursor_attributes);</div><div class='add'>+</div><div class='add'>+void dpp401_set_cursor_position(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	const struct dc_cursor_position *pos,</div><div class='add'>+	const struct dc_cursor_mi_param *param,</div><div class='add'>+	uint32_t width,</div><div class='add'>+	uint32_t height);</div><div class='add'>+</div><div class='add'>+void dpp401_set_optional_cursor_attributes(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	struct dpp_cursor_attributes *attr);</div><div class='add'>+</div><div class='add'>+void dscl401_calc_lb_num_partitions(</div><div class='add'>+		const struct scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c);</div><div class='add'>+</div><div class='add'>+void dscl401_spl_calc_lb_num_partitions(</div><div class='add'>+		bool alpha_en,</div><div class='add'>+		const struct spl_scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c);</div><div class='add'>+</div><div class='add'>+void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);</div><div class='add'>+</div><div class='add'>+void dpp401_set_cursor_matrix(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	enum dc_color_space color_space,</div><div class='add'>+	struct dc_csc_transform cursor_csc_color_matrix);</div><div class='add'>+</div><div class='add'>+#endif /* __DCN401_DPP_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c<br/>new file mode 100644<br/>index 000000000000..62bf7cea21d8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c</a></div><div class='hunk'>@@ -0,0 +1,242 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2016 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dcn401/dcn401_dpp.h"</div><div class='add'>+#include "basics/conversion.h"</div><div class='add'>+#include "dcn10/dcn10_cm_common.h"</div><div class='add'>+</div><div class='add'>+#define NUM_PHASES    64</div><div class='add'>+#define HORZ_MAX_TAPS 8</div><div class='add'>+#define VERT_MAX_TAPS 8</div><div class='add'>+</div><div class='add'>+#define BLACK_OFFSET_RGB_Y 0x0</div><div class='add'>+#define BLACK_OFFSET_CBCR  0x8000</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	dpp-&gt;tf_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	dpp-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	dpp-&gt;tf_shift-&gt;field_name, dpp-&gt;tf_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+enum dcn401_coef_filter_type_sel {</div><div class='add'>+	SCL_COEF_LUMA_VERT_FILTER = 0,</div><div class='add'>+	SCL_COEF_LUMA_HORZ_FILTER = 1,</div><div class='add'>+	SCL_COEF_CHROMA_VERT_FILTER = 2,</div><div class='add'>+	SCL_COEF_CHROMA_HORZ_FILTER = 3,</div><div class='add'>+	SCL_COEF_SC_VERT_FILTER = 4,</div><div class='add'>+	SCL_COEF_SC_HORZ_FILTER = 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dscl_autocal_mode {</div><div class='add'>+	AUTOCAL_MODE_OFF = 0,</div><div class='add'>+</div><div class='add'>+	/* Autocal calculate the scaling ratio and initial phase and the</div><div class='add'>+	 * DSCL_MODE_SEL must be set to 1</div><div class='add'>+	 */</div><div class='add'>+	AUTOCAL_MODE_AUTOSCALE = 1,</div><div class='add'>+	/* Autocal perform auto centering without replication and the</div><div class='add'>+	 * DSCL_MODE_SEL must be set to 0</div><div class='add'>+	 */</div><div class='add'>+	AUTOCAL_MODE_AUTOCENTER = 2,</div><div class='add'>+	/* Autocal perform auto centering and auto replication and the</div><div class='add'>+	 * DSCL_MODE_SEL must be set to 0</div><div class='add'>+	 */</div><div class='add'>+	AUTOCAL_MODE_AUTOREPLICATE = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dscl_mode_sel {</div><div class='add'>+	DSCL_MODE_SCALING_444_BYPASS = 0,</div><div class='add'>+	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,</div><div class='add'>+	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,</div><div class='add'>+	DSCL_MODE_SCALING_YCBCR_ENABLE = 3,</div><div class='add'>+	DSCL_MODE_LUMA_SCALING_BYPASS = 4,</div><div class='add'>+	DSCL_MODE_CHROMA_SCALING_BYPASS = 5,</div><div class='add'>+	DSCL_MODE_DSCL_BYPASS = 6</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dpp401_set_cursor_attributes(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	struct dc_cursor_attributes *cursor_attributes)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+	enum dc_cursor_color_format color_format = cursor_attributes-&gt;color_format;</div><div class='add'>+	int cur_rom_en = 0;</div><div class='add'>+</div><div class='add'>+	if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||</div><div class='add'>+		color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {</div><div class='add'>+		if (cursor_attributes-&gt;attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {</div><div class='add'>+			cur_rom_en = 1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dpp_base-&gt;cursor_offload)</div><div class='add'>+		REG_UPDATE_3(CURSOR0_CONTROL,</div><div class='add'>+			CUR0_MODE, color_format,</div><div class='add'>+			CUR0_EXPANSION_MODE, 0,</div><div class='add'>+			CUR0_ROM_EN, cur_rom_en);</div><div class='add'>+</div><div class='add'>+	if (color_format == CURSOR_MODE_MONO) {</div><div class='add'>+		/* todo: clarify what to program these to */</div><div class='add'>+</div><div class='add'>+		if (!dpp_base-&gt;cursor_offload) {</div><div class='add'>+			REG_UPDATE(CURSOR0_COLOR0,</div><div class='add'>+				CUR0_COLOR0, 0x00000000);</div><div class='add'>+			REG_UPDATE(CURSOR0_COLOR1,</div><div class='add'>+				CUR0_COLOR1, 0xFFFFFFFF);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dpp_base-&gt;att.cur0_ctl.bits.expansion_mode = 0;</div><div class='add'>+	dpp_base-&gt;att.cur0_ctl.bits.cur0_rom_en = cur_rom_en;</div><div class='add'>+	dpp_base-&gt;att.cur0_ctl.bits.mode = color_format;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dpp401_set_cursor_position(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	const struct dc_cursor_position *pos,</div><div class='add'>+	const struct dc_cursor_mi_param *param,</div><div class='add'>+	uint32_t width,</div><div class='add'>+	uint32_t height)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+	uint32_t cur_en = pos-&gt;enable ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	if (dpp_base-&gt;pos.cur0_ctl.bits.cur0_enable != cur_en) {</div><div class='add'>+		if (!dpp_base-&gt;cursor_offload)</div><div class='add'>+			REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dpp_base-&gt;pos.cur0_ctl.bits.cur0_enable = cur_en;</div><div class='add'>+	dpp_base-&gt;att.cur0_ctl.bits.cur0_enable = cur_en;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dpp401_set_optional_cursor_attributes(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	struct dpp_cursor_attributes *attr)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	if (attr) {</div><div class='add'>+		if (!dpp_base-&gt;cursor_offload) {</div><div class='add'>+			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr-&gt;bias);</div><div class='add'>+			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr-&gt;scale);</div><div class='add'>+			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr-&gt;bias);</div><div class='add'>+			REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr-&gt;scale);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dpp_base-&gt;att.fp_scale_bias_g_y.bits.fp_bias_g_y = attr-&gt;bias;</div><div class='add'>+		dpp_base-&gt;att.fp_scale_bias_g_y.bits.fp_scale_g_y = attr-&gt;scale;</div><div class='add'>+		dpp_base-&gt;att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb = attr-&gt;bias;</div><div class='add'>+		dpp_base-&gt;att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb = attr-&gt;scale;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Program Cursor matrix block in DPP CM */</div><div class='add'>+static void dpp401_program_cursor_csc(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	enum dc_color_space color_space,</div><div class='add'>+	const struct dpp_input_csc_matrix *tbl_entry)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+	uint32_t mode_select = 0;</div><div class='add'>+	struct color_matrices_reg cur_matrix_regs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	const uint16_t *regval = NULL;</div><div class='add'>+	int arr_size = sizeof(dpp_input_csc_matrix) / sizeof(struct dpp_input_csc_matrix);</div><div class='add'>+</div><div class='add'>+	if (color_space &lt; COLOR_SPACE_YCBCR601) {</div><div class='add'>+		REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If adjustments not provided use hardcoded table for color space conversion */</div><div class='add'>+	if (tbl_entry == NULL) {</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; arr_size; i++)</div><div class='add'>+			if (dpp_input_csc_matrix[i].color_space == color_space) {</div><div class='add'>+				regval = dpp_input_csc_matrix[i].regval;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+		if (regval == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		regval = tbl_entry-&gt;regval;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_GET(CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, &amp;mode_select);</div><div class='add'>+</div><div class='add'>+	//If current set in use not set A, then use set A, otherwise use set B</div><div class='add'>+	if (mode_select != CUR_MATRIX_SET_A)</div><div class='add'>+		mode_select = CUR_MATRIX_SET_A;</div><div class='add'>+	else</div><div class='add'>+		mode_select = CUR_MATRIX_SET_B;</div><div class='add'>+</div><div class='add'>+	cur_matrix_regs.shifts.csc_c11 = dpp-&gt;tf_shift-&gt;CUR0_MATRIX_C11_A;</div><div class='add'>+	cur_matrix_regs.masks.csc_c11 = dpp-&gt;tf_mask-&gt;CUR0_MATRIX_C11_A;</div><div class='add'>+	cur_matrix_regs.shifts.csc_c12 = dpp-&gt;tf_shift-&gt;CUR0_MATRIX_C12_A;</div><div class='add'>+	cur_matrix_regs.masks.csc_c12 = dpp-&gt;tf_mask-&gt;CUR0_MATRIX_C12_A;</div><div class='add'>+</div><div class='add'>+	if (mode_select == CUR_MATRIX_SET_A) {</div><div class='add'>+		cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_A);</div><div class='add'>+		cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_A);</div><div class='add'>+	} else {</div><div class='add'>+		cur_matrix_regs.csc_c11_c12 = REG(CUR0_MATRIX_C11_C12_B);</div><div class='add'>+		cur_matrix_regs.csc_c33_c34 = REG(CUR0_MATRIX_C33_C34_B);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cm_helper_program_color_matrices(</div><div class='add'>+		dpp-&gt;base.ctx,</div><div class='add'>+		regval,</div><div class='add'>+		&amp;cur_matrix_regs);</div><div class='add'>+</div><div class='add'>+	//select coefficient set to use</div><div class='add'>+	REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, mode_select);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Program Cursor matrix block in DPP CM */</div><div class='add'>+void dpp401_set_cursor_matrix(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	enum dc_color_space color_space,</div><div class='add'>+	struct dc_csc_transform cursor_csc_color_matrix)</div><div class='add'>+{</div><div class='add'>+	//Since we don't have cursor matrix information, force bypass mode by passing in unknown color space</div><div class='add'>+	dpp401_program_cursor_csc(dpp_base, COLOR_SPACE_UNKNOWN, NULL);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c<br/>new file mode 100644<br/>index 000000000000..6df3419f825f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c</a></div><div class='hunk'>@@ -0,0 +1,1186 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2016 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dcn401/dcn401_dpp.h"</div><div class='add'>+#include "basics/conversion.h"</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define NUM_PHASES    64</div><div class='add'>+#define HORZ_MAX_TAPS 8</div><div class='add'>+#define VERT_MAX_TAPS 8</div><div class='add'>+#define NUM_LEVELS    32</div><div class='add'>+#define BLACK_OFFSET_RGB_Y 0x0</div><div class='add'>+#define BLACK_OFFSET_CBCR  0x8000</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	dpp-&gt;tf_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	dpp-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	dpp-&gt;tf_shift-&gt;field_name, dpp-&gt;tf_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+enum dcn401_coef_filter_type_sel {</div><div class='add'>+	SCL_COEF_LUMA_VERT_FILTER = 0,</div><div class='add'>+	SCL_COEF_LUMA_HORZ_FILTER = 1,</div><div class='add'>+	SCL_COEF_CHROMA_VERT_FILTER = 2,</div><div class='add'>+	SCL_COEF_CHROMA_HORZ_FILTER = 3,</div><div class='add'>+	SCL_COEF_ALPHA_VERT_FILTER = 4,</div><div class='add'>+	SCL_COEF_ALPHA_HORZ_FILTER = 5,</div><div class='add'>+	SCL_COEF_VERTICAL_BLUR_SCALE = SCL_COEF_ALPHA_VERT_FILTER,</div><div class='add'>+	SCL_COEF_HORIZONTAL_BLUR_SCALE = SCL_COEF_ALPHA_HORZ_FILTER</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dscl_autocal_mode {</div><div class='add'>+	AUTOCAL_MODE_OFF = 0,</div><div class='add'>+</div><div class='add'>+	/* Autocal calculate the scaling ratio and initial phase and the</div><div class='add'>+	 * DSCL_MODE_SEL must be set to 1</div><div class='add'>+	 */</div><div class='add'>+	AUTOCAL_MODE_AUTOSCALE = 1,</div><div class='add'>+	/* Autocal perform auto centering without replication and the</div><div class='add'>+	 * DSCL_MODE_SEL must be set to 0</div><div class='add'>+	 */</div><div class='add'>+	AUTOCAL_MODE_AUTOCENTER = 2,</div><div class='add'>+	/* Autocal perform auto centering and auto replication and the</div><div class='add'>+	 * DSCL_MODE_SEL must be set to 0</div><div class='add'>+	 */</div><div class='add'>+	AUTOCAL_MODE_AUTOREPLICATE = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dpp401_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)</div><div class='add'>+{</div><div class='add'>+	if (depth == LB_PIXEL_DEPTH_30BPP)</div><div class='add'>+		return 0; /* 10 bpc */</div><div class='add'>+	else if (depth == LB_PIXEL_DEPTH_24BPP)</div><div class='add'>+		return 1; /* 8 bpc */</div><div class='add'>+	else if (depth == LB_PIXEL_DEPTH_18BPP)</div><div class='add'>+		return 2; /* 6 bpc */</div><div class='add'>+	else if (depth == LB_PIXEL_DEPTH_36BPP)</div><div class='add'>+		return 3; /* 12 bpc */</div><div class='add'>+	else {</div><div class='add'>+		ASSERT(0);</div><div class='add'>+		return -1; /* Unsupported */</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dpp401_dscl_is_video_format(enum pixel_format format)</div><div class='add'>+{</div><div class='add'>+	if (format &gt;= PIXEL_FORMAT_VIDEO_BEGIN</div><div class='add'>+			&amp;&amp; format &lt;= PIXEL_FORMAT_VIDEO_END)</div><div class='add'>+		return true;</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dpp401_dscl_is_420_format(enum pixel_format format)</div><div class='add'>+{</div><div class='add'>+	if (format == PIXEL_FORMAT_420BPP8 ||</div><div class='add'>+			format == PIXEL_FORMAT_420BPP10)</div><div class='add'>+		return true;</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dcn401_dscl_mode_sel dpp401_dscl_get_dscl_mode(</div><div class='add'>+		struct dpp *dpp_base,</div><div class='add'>+		const struct scaler_data *data,</div><div class='add'>+		bool dbg_always_scale)</div><div class='add'>+{</div><div class='add'>+	const long long one = dc_fixpt_one.value;</div><div class='add'>+</div><div class='add'>+	if (dpp_base-&gt;caps-&gt;dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {</div><div class='add'>+		/* DSCL is processing data in fixed format */</div><div class='add'>+		if (data-&gt;format == PIXEL_FORMAT_FP16)</div><div class='add'>+			return DCN401_DSCL_MODE_DSCL_BYPASS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (data-&gt;ratios.horz.value == one</div><div class='add'>+			&amp;&amp; data-&gt;ratios.vert.value == one</div><div class='add'>+			&amp;&amp; data-&gt;ratios.horz_c.value == one</div><div class='add'>+			&amp;&amp; data-&gt;ratios.vert_c.value == one</div><div class='add'>+			&amp;&amp; !dbg_always_scale)</div><div class='add'>+		return DCN401_DSCL_MODE_SCALING_444_BYPASS;</div><div class='add'>+</div><div class='add'>+	if (!dpp401_dscl_is_420_format(data-&gt;format)) {</div><div class='add'>+		if (dpp401_dscl_is_video_format(data-&gt;format))</div><div class='add'>+			return DCN401_DSCL_MODE_SCALING_444_YCBCR_ENABLE;</div><div class='add'>+		else</div><div class='add'>+			return DCN401_DSCL_MODE_SCALING_444_RGB_ENABLE;</div><div class='add'>+	}</div><div class='add'>+	if (data-&gt;ratios.horz.value == one &amp;&amp; data-&gt;ratios.vert.value == one)</div><div class='add'>+		return DCN401_DSCL_MODE_SCALING_420_LUMA_BYPASS;</div><div class='add'>+	if (data-&gt;ratios.horz_c.value == one &amp;&amp; data-&gt;ratios.vert_c.value == one)</div><div class='add'>+		return DCN401_DSCL_MODE_SCALING_420_CHROMA_BYPASS;</div><div class='add'>+</div><div class='add'>+	return DCN401_DSCL_MODE_SCALING_420_YCBCR_ENABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dpp401_power_on_dscl(</div><div class='add'>+	struct dpp *dpp_base,</div><div class='add'>+	bool power_on)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	if (dpp-&gt;tf_regs-&gt;DSCL_MEM_PWR_CTRL) {</div><div class='add'>+		if (power_on) {</div><div class='add'>+			REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0);</div><div class='add'>+			REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);</div><div class='add'>+		} else {</div><div class='add'>+			if (dpp-&gt;base.ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.dscl) {</div><div class='add'>+				dpp-&gt;base.ctx-&gt;dc-&gt;optimized_required = true;</div><div class='add'>+				dpp-&gt;base.deferred_reg_writes.bits.disable_dscl = true;</div><div class='add'>+			} else {</div><div class='add'>+				REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dpp401_dscl_set_lb(</div><div class='add'>+	struct dcn401_dpp *dpp,</div><div class='add'>+	const struct line_buffer_params *lb_params,</div><div class='add'>+	enum lb_memory_config mem_size_config)</div><div class='add'>+{</div><div class='add'>+	uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */</div><div class='add'>+</div><div class='add'>+	/* LB */</div><div class='add'>+	if (dpp-&gt;base.caps-&gt;dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {</div><div class='add'>+		/* DSCL caps: pixel data processed in fixed format */</div><div class='add'>+		uint32_t pixel_depth = dpp401_dscl_get_pixel_depth_val(lb_params-&gt;depth);</div><div class='add'>+		uint32_t dyn_pix_depth = lb_params-&gt;dynamic_pixel_depth;</div><div class='add'>+</div><div class='add'>+		REG_SET_7(LB_DATA_FORMAT, 0,</div><div class='add'>+			PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */</div><div class='add'>+			PIXEL_EXPAN_MODE, lb_params-&gt;pixel_expan_mode, /* Pixel expansion mode */</div><div class='add'>+			PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */</div><div class='add'>+			DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */</div><div class='add'>+			DITHER_EN, 0, /* Dithering enable: Disabled */</div><div class='add'>+			INTERLEAVE_EN, lb_params-&gt;interleave_en, /* Interleave source enable */</div><div class='add'>+			LB_DATA_FORMAT__ALPHA_EN, lb_params-&gt;alpha_en); /* Alpha enable */</div><div class='add'>+	}	else {</div><div class='add'>+		/* DSCL caps: pixel data processed in float format */</div><div class='add'>+		REG_SET_2(LB_DATA_FORMAT, 0,</div><div class='add'>+			INTERLEAVE_EN, lb_params-&gt;interleave_en, /* Interleave source enable */</div><div class='add'>+			LB_DATA_FORMAT__ALPHA_EN, lb_params-&gt;alpha_en); /* Alpha enable */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dpp-&gt;base.caps-&gt;max_lb_partitions == 31)</div><div class='add'>+		max_partitions = 31;</div><div class='add'>+</div><div class='add'>+	REG_SET_2(LB_MEMORY_CTRL, 0,</div><div class='add'>+		MEMORY_CONFIG, mem_size_config,</div><div class='add'>+		LB_MAX_PARTITIONS, max_partitions);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *dpp401_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (taps == 8)</div><div class='add'>+		return get_filter_8tap_64p(ratio);</div><div class='add'>+	else if (taps == 7)</div><div class='add'>+		return get_filter_7tap_64p(ratio);</div><div class='add'>+	else if (taps == 6)</div><div class='add'>+		return get_filter_6tap_64p(ratio);</div><div class='add'>+	else if (taps == 5)</div><div class='add'>+		return get_filter_5tap_64p(ratio);</div><div class='add'>+	else if (taps == 4)</div><div class='add'>+		return get_filter_4tap_64p(ratio);</div><div class='add'>+	else if (taps == 3)</div><div class='add'>+		return get_filter_3tap_64p(ratio);</div><div class='add'>+	else if (taps == 2)</div><div class='add'>+		return get_filter_2tap_64p();</div><div class='add'>+	else if (taps == 1)</div><div class='add'>+		return NULL;</div><div class='add'>+	else {</div><div class='add'>+		/* should never happen, bug */</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dpp401_dscl_set_scaler_filter(</div><div class='add'>+		struct dcn401_dpp *dpp,</div><div class='add'>+		uint32_t taps,</div><div class='add'>+		enum dcn401_coef_filter_type_sel filter_type,</div><div class='add'>+		const uint16_t *filter)</div><div class='add'>+{</div><div class='add'>+	const int tap_pairs = (taps + 1) / 2;</div><div class='add'>+	int phase;</div><div class='add'>+	int pair;</div><div class='add'>+	uint16_t odd_coef, even_coef;</div><div class='add'>+</div><div class='add'>+	REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,</div><div class='add'>+		SCL_COEF_RAM_TAP_PAIR_IDX, 0,</div><div class='add'>+		SCL_COEF_RAM_PHASE, 0,</div><div class='add'>+		SCL_COEF_RAM_FILTER_TYPE, filter_type);</div><div class='add'>+</div><div class='add'>+	for (phase = 0; phase &lt; (NUM_PHASES / 2 + 1); phase++) {</div><div class='add'>+		for (pair = 0; pair &lt; tap_pairs; pair++) {</div><div class='add'>+			even_coef = filter[phase * taps + 2 * pair];</div><div class='add'>+			if ((pair * 2 + 1) &lt; taps)</div><div class='add'>+				odd_coef = filter[phase * taps + 2 * pair + 1];</div><div class='add'>+			else</div><div class='add'>+				odd_coef = 0;</div><div class='add'>+</div><div class='add'>+			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,</div><div class='add'>+				/* Even tap coefficient (bits 1:0 fixed to 0) */</div><div class='add'>+				SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,</div><div class='add'>+				/* Write/read control for even coefficient */</div><div class='add'>+				SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,</div><div class='add'>+				/* Odd tap coefficient (bits 1:0 fixed to 0) */</div><div class='add'>+				SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,</div><div class='add'>+				/* Write/read control for odd coefficient */</div><div class='add'>+				SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dpp401_dscl_set_scl_filter(</div><div class='add'>+		struct dcn401_dpp *dpp,</div><div class='add'>+		const struct scaler_data *scl_data,</div><div class='add'>+		bool chroma_coef_mode,</div><div class='add'>+		bool force_coeffs_update)</div><div class='add'>+{</div><div class='add'>+	bool h_2tap_hardcode_coef_en = false;</div><div class='add'>+	bool v_2tap_hardcode_coef_en = false;</div><div class='add'>+	bool h_2tap_sharp_en = false;</div><div class='add'>+	bool v_2tap_sharp_en = false;</div><div class='add'>+	uint32_t h_2tap_sharp_factor = scl_data-&gt;sharpness.horz;</div><div class='add'>+	uint32_t v_2tap_sharp_factor = scl_data-&gt;sharpness.vert;</div><div class='add'>+	bool coef_ram_current;</div><div class='add'>+	const uint16_t *filter_h = NULL;</div><div class='add'>+	const uint16_t *filter_v = NULL;</div><div class='add'>+	const uint16_t *filter_h_c = NULL;</div><div class='add'>+	const uint16_t *filter_v_c = NULL;</div><div class='add'>+</div><div class='add'>+	if ((dpp-&gt;base.ctx-&gt;dc-&gt;config.use_spl) &amp;&amp; (!dpp-&gt;base.ctx-&gt;dc-&gt;debug.disable_spl)) {</div><div class='add'>+		filter_h = scl_data-&gt;dscl_prog_data.filter_h;</div><div class='add'>+		filter_v = scl_data-&gt;dscl_prog_data.filter_v;</div><div class='add'>+		if (chroma_coef_mode) {</div><div class='add'>+			filter_h_c = scl_data-&gt;dscl_prog_data.filter_h_c;</div><div class='add'>+			filter_v_c = scl_data-&gt;dscl_prog_data.filter_v_c;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		filter_h = dpp401_dscl_get_filter_coeffs_64p(</div><div class='add'>+			scl_data-&gt;taps.h_taps, scl_data-&gt;ratios.horz);</div><div class='add'>+		filter_v = dpp401_dscl_get_filter_coeffs_64p(</div><div class='add'>+			scl_data-&gt;taps.v_taps, scl_data-&gt;ratios.vert);</div><div class='add'>+		if (chroma_coef_mode) {</div><div class='add'>+			filter_h_c = dpp401_dscl_get_filter_coeffs_64p(</div><div class='add'>+				scl_data-&gt;taps.h_taps_c, scl_data-&gt;ratios.horz_c);</div><div class='add'>+			filter_v_c = dpp401_dscl_get_filter_coeffs_64p(</div><div class='add'>+				scl_data-&gt;taps.v_taps_c, scl_data-&gt;ratios.vert_c);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	h_2tap_hardcode_coef_en = scl_data-&gt;taps.h_taps &lt; 3</div><div class='add'>+					&amp;&amp; scl_data-&gt;taps.h_taps_c &lt; 3</div><div class='add'>+		&amp;&amp; (scl_data-&gt;taps.h_taps &gt; 1 &amp;&amp; scl_data-&gt;taps.h_taps_c &gt; 1);</div><div class='add'>+	v_2tap_hardcode_coef_en = scl_data-&gt;taps.v_taps &lt; 3</div><div class='add'>+					&amp;&amp; scl_data-&gt;taps.v_taps_c &lt; 3</div><div class='add'>+		&amp;&amp; (scl_data-&gt;taps.v_taps &gt; 1 &amp;&amp; scl_data-&gt;taps.v_taps_c &gt; 1);</div><div class='add'>+</div><div class='add'>+	h_2tap_sharp_en = h_2tap_hardcode_coef_en &amp;&amp; h_2tap_sharp_factor != 0;</div><div class='add'>+	v_2tap_sharp_en = v_2tap_hardcode_coef_en &amp;&amp; v_2tap_sharp_factor != 0;</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_6(DSCL_2TAP_CONTROL,</div><div class='add'>+		SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,</div><div class='add'>+		SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,</div><div class='add'>+		SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,</div><div class='add'>+		SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,</div><div class='add'>+		SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,</div><div class='add'>+		SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);</div><div class='add'>+</div><div class='add'>+	if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {</div><div class='add'>+		bool filter_updated = false;</div><div class='add'>+</div><div class='add'>+		filter_updated = (filter_h &amp;&amp; (filter_h != dpp-&gt;filter_h))</div><div class='add'>+				|| (filter_v &amp;&amp; (filter_v != dpp-&gt;filter_v));</div><div class='add'>+</div><div class='add'>+		if (chroma_coef_mode) {</div><div class='add'>+			filter_updated = filter_updated || (filter_h_c &amp;&amp; (filter_h_c != dpp-&gt;filter_h_c))</div><div class='add'>+							|| (filter_v_c &amp;&amp; (filter_v_c != dpp-&gt;filter_v_c));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((filter_updated) || (force_coeffs_update)) {</div><div class='add'>+			uint32_t scl_mode = REG_READ(SCL_MODE);</div><div class='add'>+</div><div class='add'>+			if (!h_2tap_hardcode_coef_en &amp;&amp; filter_h) {</div><div class='add'>+				dpp401_dscl_set_scaler_filter(</div><div class='add'>+					dpp, scl_data-&gt;taps.h_taps,</div><div class='add'>+					SCL_COEF_LUMA_HORZ_FILTER, filter_h);</div><div class='add'>+			}</div><div class='add'>+			dpp-&gt;filter_h = filter_h;</div><div class='add'>+			if (!v_2tap_hardcode_coef_en &amp;&amp; filter_v) {</div><div class='add'>+				dpp401_dscl_set_scaler_filter(</div><div class='add'>+					dpp, scl_data-&gt;taps.v_taps,</div><div class='add'>+					SCL_COEF_LUMA_VERT_FILTER, filter_v);</div><div class='add'>+			}</div><div class='add'>+			dpp-&gt;filter_v = filter_v;</div><div class='add'>+			if (chroma_coef_mode) {</div><div class='add'>+				if (!h_2tap_hardcode_coef_en &amp;&amp; filter_h_c) {</div><div class='add'>+					dpp401_dscl_set_scaler_filter(</div><div class='add'>+						dpp, scl_data-&gt;taps.h_taps_c,</div><div class='add'>+						SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);</div><div class='add'>+				}</div><div class='add'>+				if (!v_2tap_hardcode_coef_en &amp;&amp; filter_v_c) {</div><div class='add'>+					dpp401_dscl_set_scaler_filter(</div><div class='add'>+						dpp, scl_data-&gt;taps.v_taps_c,</div><div class='add'>+						SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			dpp-&gt;filter_h_c = filter_h_c;</div><div class='add'>+			dpp-&gt;filter_v_c = filter_v_c;</div><div class='add'>+</div><div class='add'>+			coef_ram_current = get_reg_field_value_ex(</div><div class='add'>+				scl_mode, dpp-&gt;tf_mask-&gt;SCL_COEF_RAM_SELECT_CURRENT,</div><div class='add'>+				dpp-&gt;tf_shift-&gt;SCL_COEF_RAM_SELECT_CURRENT);</div><div class='add'>+</div><div class='add'>+			/* Swap coefficient RAM and set chroma coefficient mode */</div><div class='add'>+			REG_SET_2(SCL_MODE, scl_mode,</div><div class='add'>+					SCL_COEF_RAM_SELECT, !coef_ram_current,</div><div class='add'>+					SCL_CHROMA_COEF_MODE, chroma_coef_mode);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+// TODO: Fix defined but not used error</div><div class='add'>+//static int dpp401_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)</div><div class='add'>+//{</div><div class='add'>+//	if (depth == LB_PIXEL_DEPTH_30BPP)</div><div class='add'>+//		return 10;</div><div class='add'>+//	else if (depth == LB_PIXEL_DEPTH_24BPP)</div><div class='add'>+//		return 8;</div><div class='add'>+//	else if (depth == LB_PIXEL_DEPTH_18BPP)</div><div class='add'>+//		return 6;</div><div class='add'>+//	else if (depth == LB_PIXEL_DEPTH_36BPP)</div><div class='add'>+//		return 12;</div><div class='add'>+//	else {</div><div class='add'>+//		BREAK_TO_DEBUGGER();</div><div class='add'>+//		return -1; /* Unsupported */</div><div class='add'>+//	}</div><div class='add'>+//}</div><div class='add'>+</div><div class='add'>+// TODO: Fix defined but not used error</div><div class='add'>+//void dpp401_dscl_calc_lb_num_partitions(</div><div class='add'>+//		const struct scaler_data *scl_data,</div><div class='add'>+//		enum lb_memory_config lb_config,</div><div class='add'>+//		int *num_part_y,</div><div class='add'>+//		int *num_part_c)</div><div class='add'>+//{</div><div class='add'>+//	int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,</div><div class='add'>+//	lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;</div><div class='add'>+//</div><div class='add'>+//	int line_size = scl_data-&gt;viewport.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+//			scl_data-&gt;viewport.width : scl_data-&gt;recout.width;</div><div class='add'>+//	int line_size_c = scl_data-&gt;viewport_c.width &lt; scl_data-&gt;recout.width ?</div><div class='add'>+//			scl_data-&gt;viewport_c.width : scl_data-&gt;recout.width;</div><div class='add'>+//</div><div class='add'>+//	if (line_size == 0)</div><div class='add'>+//		line_size = 1;</div><div class='add'>+//</div><div class='add'>+//	if (line_size_c == 0)</div><div class='add'>+//		line_size_c = 1;</div><div class='add'>+//</div><div class='add'>+//</div><div class='add'>+//	lb_bpc = dpp401_dscl_get_lb_depth_bpc(scl_data-&gt;lb_params.depth);</div><div class='add'>+//	memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */</div><div class='add'>+//	memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */</div><div class='add'>+//	memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */</div><div class='add'>+//</div><div class='add'>+//	if (lb_config == LB_MEMORY_CONFIG_1) {</div><div class='add'>+//		lb_memory_size = 816;</div><div class='add'>+//		lb_memory_size_c = 816;</div><div class='add'>+//		lb_memory_size_a = 984;</div><div class='add'>+//	} else if (lb_config == LB_MEMORY_CONFIG_2) {</div><div class='add'>+//		lb_memory_size = 1088;</div><div class='add'>+//		lb_memory_size_c = 1088;</div><div class='add'>+//		lb_memory_size_a = 1312;</div><div class='add'>+//	} else if (lb_config == LB_MEMORY_CONFIG_3) {</div><div class='add'>+//		/* 420 mode: using 3rd mem from Y, Cr and Cb */</div><div class='add'>+//		lb_memory_size = 816 + 1088 + 848 + 848 + 848;</div><div class='add'>+//		lb_memory_size_c = 816 + 1088;</div><div class='add'>+//		lb_memory_size_a = 984 + 1312 + 456;</div><div class='add'>+//	} else {</div><div class='add'>+//		lb_memory_size = 816 + 1088 + 848;</div><div class='add'>+//		lb_memory_size_c = 816 + 1088 + 848;</div><div class='add'>+//		lb_memory_size_a = 984 + 1312 + 456;</div><div class='add'>+//	}</div><div class='add'>+//	*num_part_y = lb_memory_size / memory_line_size_y;</div><div class='add'>+//	*num_part_c = lb_memory_size_c / memory_line_size_c;</div><div class='add'>+//	num_partitions_a = lb_memory_size_a / memory_line_size_a;</div><div class='add'>+//</div><div class='add'>+//	if (scl_data-&gt;lb_params.alpha_en</div><div class='add'>+//			&amp;&amp; (num_partitions_a &lt; *num_part_y))</div><div class='add'>+//		*num_part_y = num_partitions_a;</div><div class='add'>+//</div><div class='add'>+//	if (*num_part_y &gt; 64)</div><div class='add'>+//		*num_part_y = 64;</div><div class='add'>+//	if (*num_part_c &gt; 64)</div><div class='add'>+//		*num_part_c = 64;</div><div class='add'>+//</div><div class='add'>+//}</div><div class='add'>+</div><div class='add'>+static bool dpp401_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)</div><div class='add'>+{</div><div class='add'>+	if (ceil_vratio &gt; 2)</div><div class='add'>+		return vtaps &lt;= (num_partitions - ceil_vratio + 2);</div><div class='add'>+	else</div><div class='add'>+		return vtaps &lt;= num_partitions;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*find first match configuration which meets the min required lb size*/</div><div class='add'>+static enum lb_memory_config dpp401_dscl_find_lb_memory_config(struct dcn401_dpp *dpp,</div><div class='add'>+		const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	int num_part_y, num_part_c;</div><div class='add'>+	int vtaps = scl_data-&gt;taps.v_taps;</div><div class='add'>+	int vtaps_c = scl_data-&gt;taps.v_taps_c;</div><div class='add'>+	int ceil_vratio = dc_fixpt_ceil(scl_data-&gt;ratios.vert);</div><div class='add'>+	int ceil_vratio_c = dc_fixpt_ceil(scl_data-&gt;ratios.vert_c);</div><div class='add'>+</div><div class='add'>+	if (dpp-&gt;base.ctx-&gt;dc-&gt;debug.use_max_lb) {</div><div class='add'>+		if (scl_data-&gt;format == PIXEL_FORMAT_420BPP8</div><div class='add'>+				|| scl_data-&gt;format == PIXEL_FORMAT_420BPP10)</div><div class='add'>+			return LB_MEMORY_CONFIG_3;</div><div class='add'>+		return LB_MEMORY_CONFIG_0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dpp-&gt;base.caps-&gt;dscl_calc_lb_num_partitions(</div><div class='add'>+			scl_data, LB_MEMORY_CONFIG_1, &amp;num_part_y, &amp;num_part_c);</div><div class='add'>+</div><div class='add'>+	if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)</div><div class='add'>+			&amp;&amp; dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))</div><div class='add'>+		return LB_MEMORY_CONFIG_1;</div><div class='add'>+</div><div class='add'>+	dpp-&gt;base.caps-&gt;dscl_calc_lb_num_partitions(</div><div class='add'>+			scl_data, LB_MEMORY_CONFIG_2, &amp;num_part_y, &amp;num_part_c);</div><div class='add'>+</div><div class='add'>+	if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)</div><div class='add'>+			&amp;&amp; dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))</div><div class='add'>+		return LB_MEMORY_CONFIG_2;</div><div class='add'>+</div><div class='add'>+	if (scl_data-&gt;format == PIXEL_FORMAT_420BPP8</div><div class='add'>+			|| scl_data-&gt;format == PIXEL_FORMAT_420BPP10) {</div><div class='add'>+		dpp-&gt;base.caps-&gt;dscl_calc_lb_num_partitions(</div><div class='add'>+				scl_data, LB_MEMORY_CONFIG_3, &amp;num_part_y, &amp;num_part_c);</div><div class='add'>+</div><div class='add'>+		if (dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)</div><div class='add'>+				&amp;&amp; dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))</div><div class='add'>+			return LB_MEMORY_CONFIG_3;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dpp-&gt;base.caps-&gt;dscl_calc_lb_num_partitions(</div><div class='add'>+			scl_data, LB_MEMORY_CONFIG_0, &amp;num_part_y, &amp;num_part_c);</div><div class='add'>+</div><div class='add'>+	/*Ensure we can support the requested number of vtaps*/</div><div class='add'>+	ASSERT(dpp401_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)</div><div class='add'>+			&amp;&amp; dpp401_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));</div><div class='add'>+</div><div class='add'>+	return LB_MEMORY_CONFIG_0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void dpp401_dscl_set_manual_ratio_init(</div><div class='add'>+		struct dcn401_dpp *dpp, const struct scaler_data *data)</div><div class='add'>+{</div><div class='add'>+	uint32_t init_frac = 0;</div><div class='add'>+	uint32_t init_int = 0;</div><div class='add'>+	if ((dpp-&gt;base.ctx-&gt;dc-&gt;config.use_spl) &amp;&amp; (!dpp-&gt;base.ctx-&gt;dc-&gt;debug.disable_spl)) {</div><div class='add'>+		REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,</div><div class='add'>+			SCL_H_SCALE_RATIO, data-&gt;dscl_prog_data.ratios.h_scale_ratio);</div><div class='add'>+</div><div class='add'>+		REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,</div><div class='add'>+			SCL_V_SCALE_RATIO, data-&gt;dscl_prog_data.ratios.v_scale_ratio);</div><div class='add'>+</div><div class='add'>+		REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,</div><div class='add'>+			SCL_H_SCALE_RATIO_C, data-&gt;dscl_prog_data.ratios.h_scale_ratio_c);</div><div class='add'>+</div><div class='add'>+		REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,</div><div class='add'>+			SCL_V_SCALE_RATIO_C, data-&gt;dscl_prog_data.ratios.v_scale_ratio_c);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(SCL_HORZ_FILTER_INIT, 0,</div><div class='add'>+				SCL_H_INIT_FRAC, data-&gt;dscl_prog_data.init.h_filter_init_frac,</div><div class='add'>+				SCL_H_INIT_INT, data-&gt;dscl_prog_data.init.h_filter_init_int);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,</div><div class='add'>+				SCL_H_INIT_FRAC_C, data-&gt;dscl_prog_data.init.h_filter_init_frac_c,</div><div class='add'>+				SCL_H_INIT_INT_C, data-&gt;dscl_prog_data.init.h_filter_init_int_c);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(SCL_VERT_FILTER_INIT, 0,</div><div class='add'>+				SCL_V_INIT_FRAC, data-&gt;dscl_prog_data.init.v_filter_init_frac,</div><div class='add'>+				SCL_V_INIT_INT, data-&gt;dscl_prog_data.init.v_filter_init_int);</div><div class='add'>+</div><div class='add'>+		if (REG(SCL_VERT_FILTER_INIT_BOT)) {</div><div class='add'>+			REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,</div><div class='add'>+					SCL_V_INIT_FRAC_BOT, data-&gt;dscl_prog_data.init.v_filter_init_bot_frac,</div><div class='add'>+					SCL_V_INIT_INT_BOT, data-&gt;dscl_prog_data.init.v_filter_init_bot_int);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,</div><div class='add'>+				SCL_V_INIT_FRAC_C, data-&gt;dscl_prog_data.init.v_filter_init_frac_c,</div><div class='add'>+				SCL_V_INIT_INT_C, data-&gt;dscl_prog_data.init.v_filter_init_int_c);</div><div class='add'>+</div><div class='add'>+		if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {</div><div class='add'>+			REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,</div><div class='add'>+					SCL_V_INIT_FRAC_BOT_C, data-&gt;dscl_prog_data.init.v_filter_init_bot_frac_c,</div><div class='add'>+					SCL_V_INIT_INT_BOT_C, data-&gt;dscl_prog_data.init.v_filter_init_bot_int_c);</div><div class='add'>+		}</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,</div><div class='add'>+			SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data-&gt;ratios.horz) &lt;&lt; 5);</div><div class='add'>+</div><div class='add'>+	REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,</div><div class='add'>+			SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data-&gt;ratios.vert) &lt;&lt; 5);</div><div class='add'>+</div><div class='add'>+	REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,</div><div class='add'>+			SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data-&gt;ratios.horz_c) &lt;&lt; 5);</div><div class='add'>+</div><div class='add'>+	REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,</div><div class='add'>+			SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data-&gt;ratios.vert_c) &lt;&lt; 5);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * 0.24 format for fraction, first five bits zeroed</div><div class='add'>+	 */</div><div class='add'>+	init_frac = dc_fixpt_u0d19(data-&gt;inits.h) &lt;&lt; 5;</div><div class='add'>+	init_int = dc_fixpt_floor(data-&gt;inits.h);</div><div class='add'>+	REG_SET_2(SCL_HORZ_FILTER_INIT, 0,</div><div class='add'>+		SCL_H_INIT_FRAC, init_frac,</div><div class='add'>+		SCL_H_INIT_INT, init_int);</div><div class='add'>+</div><div class='add'>+	init_frac = dc_fixpt_u0d19(data-&gt;inits.h_c) &lt;&lt; 5;</div><div class='add'>+	init_int = dc_fixpt_floor(data-&gt;inits.h_c);</div><div class='add'>+	REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,</div><div class='add'>+		SCL_H_INIT_FRAC_C, init_frac,</div><div class='add'>+		SCL_H_INIT_INT_C, init_int);</div><div class='add'>+</div><div class='add'>+	init_frac = dc_fixpt_u0d19(data-&gt;inits.v) &lt;&lt; 5;</div><div class='add'>+	init_int = dc_fixpt_floor(data-&gt;inits.v);</div><div class='add'>+	REG_SET_2(SCL_VERT_FILTER_INIT, 0,</div><div class='add'>+		SCL_V_INIT_FRAC, init_frac,</div><div class='add'>+		SCL_V_INIT_INT, init_int);</div><div class='add'>+</div><div class='add'>+	if (REG(SCL_VERT_FILTER_INIT_BOT)) {</div><div class='add'>+		struct fixed31_32 bot = dc_fixpt_add(data-&gt;inits.v, data-&gt;ratios.vert);</div><div class='add'>+</div><div class='add'>+		init_frac = dc_fixpt_u0d19(bot) &lt;&lt; 5;</div><div class='add'>+		init_int = dc_fixpt_floor(bot);</div><div class='add'>+		REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,</div><div class='add'>+			SCL_V_INIT_FRAC_BOT, init_frac,</div><div class='add'>+			SCL_V_INIT_INT_BOT, init_int);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	init_frac = dc_fixpt_u0d19(data-&gt;inits.v_c) &lt;&lt; 5;</div><div class='add'>+	init_int = dc_fixpt_floor(data-&gt;inits.v_c);</div><div class='add'>+	REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,</div><div class='add'>+		SCL_V_INIT_FRAC_C, init_frac,</div><div class='add'>+		SCL_V_INIT_INT_C, init_int);</div><div class='add'>+</div><div class='add'>+	if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {</div><div class='add'>+		struct fixed31_32 bot = dc_fixpt_add(data-&gt;inits.v_c, data-&gt;ratios.vert_c);</div><div class='add'>+</div><div class='add'>+		init_frac = dc_fixpt_u0d19(bot) &lt;&lt; 5;</div><div class='add'>+		init_int = dc_fixpt_floor(bot);</div><div class='add'>+		REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,</div><div class='add'>+			SCL_V_INIT_FRAC_BOT_C, init_frac,</div><div class='add'>+			SCL_V_INIT_INT_BOT_C, init_int);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area</div><div class='add'>+ *</div><div class='add'>+ * @dpp: DPP data struct</div><div class='add'>+ * @recout: Rectangle information</div><div class='add'>+ *</div><div class='add'>+ * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on</div><div class='add'>+ * the values specified in the recount parameter.</div><div class='add'>+ *</div><div class='add'>+ * Note: This function only have effect if AutoCal is disabled.</div><div class='add'>+ */</div><div class='add'>+static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp,</div><div class='add'>+				 const struct rect *recout)</div><div class='add'>+{</div><div class='add'>+	REG_SET_2(RECOUT_START, 0,</div><div class='add'>+		  /* First pixel of RECOUT in the active OTG area */</div><div class='add'>+		  RECOUT_START_X, recout-&gt;x,</div><div class='add'>+		  /* First line of RECOUT in the active OTG area */</div><div class='add'>+		  RECOUT_START_Y, recout-&gt;y);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(RECOUT_SIZE, 0,</div><div class='add'>+		  /* Number of RECOUT horizontal pixels */</div><div class='add'>+		  RECOUT_WIDTH, recout-&gt;width,</div><div class='add'>+		  /* Number of RECOUT vertical lines */</div><div class='add'>+		  RECOUT_HEIGHT, recout-&gt;height);</div><div class='add'>+}</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_program_easf_v - Program EASF_V</div><div class='add'>+ *</div><div class='add'>+ * @dpp_base: High level DPP struct</div><div class='add'>+ * @scl_data: scalaer_data info</div><div class='add'>+ *</div><div class='add'>+ * This is the primary function to program vertical EASF registers</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+	/* DSCL_EASF_V_MODE */</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_MODE, 0,</div><div class='add'>+			SCL_EASF_V_EN, scl_data-&gt;dscl_prog_data.easf_v_en,</div><div class='add'>+			SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data-&gt;dscl_prog_data.easf_v_sharp_factor,</div><div class='add'>+			SCL_EASF_V_RINGEST_FORCE_EN, scl_data-&gt;dscl_prog_data.easf_v_ring);</div><div class='add'>+</div><div class='add'>+	if (!scl_data-&gt;dscl_prog_data.easf_v_en) {</div><div class='add'>+		PERF_TRACE();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DSCL_EASF_V_BF_CNTL */</div><div class='add'>+	REG_SET_6(DSCL_EASF_V_BF_CNTL, 0,</div><div class='add'>+			SCL_EASF_V_BF1_EN, scl_data-&gt;dscl_prog_data.easf_v_bf1_en,</div><div class='add'>+			SCL_EASF_V_BF2_MODE, scl_data-&gt;dscl_prog_data.easf_v_bf2_mode,</div><div class='add'>+			SCL_EASF_V_BF3_MODE, scl_data-&gt;dscl_prog_data.easf_v_bf3_mode,</div><div class='add'>+			SCL_EASF_V_BF2_FLAT1_GAIN, scl_data-&gt;dscl_prog_data.easf_v_bf2_flat1_gain,</div><div class='add'>+			SCL_EASF_V_BF2_FLAT2_GAIN, scl_data-&gt;dscl_prog_data.easf_v_bf2_flat2_gain,</div><div class='add'>+			SCL_EASF_V_BF2_ROC_GAIN, scl_data-&gt;dscl_prog_data.easf_v_bf2_roc_gain);</div><div class='add'>+	/* DSCL_EASF_V_RINGEST_3TAP_CNTLn */</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL1, 0,</div><div class='add'>+		SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data-&gt;dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt,</div><div class='add'>+		SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data-&gt;dscl_prog_data.easf_v_ringest_3tap_uptilt_max);</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL2, 0,</div><div class='add'>+		SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data-&gt;dscl_prog_data.easf_v_ringest_3tap_dntilt_slope,</div><div class='add'>+		SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data-&gt;dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope);</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL3, 0,</div><div class='add'>+		SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data-&gt;dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope,</div><div class='add'>+		SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data-&gt;dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset);</div><div class='add'>+	/* DSCL_EASF_V_RINGEST_EVENTAP_REDUCE */</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, 0,</div><div class='add'>+		SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data-&gt;dscl_prog_data.easf_v_ringest_eventap_reduceg1,</div><div class='add'>+		SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data-&gt;dscl_prog_data.easf_v_ringest_eventap_reduceg2);</div><div class='add'>+	/* DSCL_EASF_V_RINGEST_EVENTAP_GAIN */</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, 0,</div><div class='add'>+		SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data-&gt;dscl_prog_data.easf_v_ringest_eventap_gain1,</div><div class='add'>+		SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data-&gt;dscl_prog_data.easf_v_ringest_eventap_gain2);</div><div class='add'>+	/* DSCL_EASF_V_BF_FINAL_MAX_MIN */</div><div class='add'>+	REG_SET_4(DSCL_EASF_V_BF_FINAL_MAX_MIN, 0,</div><div class='add'>+			SCL_EASF_V_BF_MAXA, scl_data-&gt;dscl_prog_data.easf_v_bf_maxa,</div><div class='add'>+			SCL_EASF_V_BF_MAXB, scl_data-&gt;dscl_prog_data.easf_v_bf_maxb,</div><div class='add'>+			SCL_EASF_V_BF_MINA, scl_data-&gt;dscl_prog_data.easf_v_bf_mina,</div><div class='add'>+			SCL_EASF_V_BF_MINB, scl_data-&gt;dscl_prog_data.easf_v_bf_minb);</div><div class='add'>+	/* DSCL_EASF_V_BF1_PWL_SEGn */</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG0, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg0);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG1, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg1,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg1,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg1);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG2, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg2,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg2,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg2);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG3, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg3,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg3,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg3);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG4, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg4,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg4,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg4);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG5, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg5,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg5,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg5);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG6, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg6,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg6,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_slope_seg6);</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_BF1_PWL_SEG7, 0,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_in_seg7,</div><div class='add'>+			SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data-&gt;dscl_prog_data.easf_v_bf1_pwl_base_seg7);</div><div class='add'>+	/* DSCL_EASF_V_BF3_PWL_SEGn */</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG0, 0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_in_set0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_base_set0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_slope_set0);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG1, 0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_in_set1,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_base_set1,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_slope_set1);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG2, 0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_in_set2,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_base_set2,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_slope_set2);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG3, 0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_in_set3,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_base_set3,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_slope_set3);</div><div class='add'>+	REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG4, 0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_in_set4,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_base_set4,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_slope_set4);</div><div class='add'>+	REG_SET_2(DSCL_EASF_V_BF3_PWL_SEG5, 0,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_in_set5,</div><div class='add'>+			SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data-&gt;dscl_prog_data.easf_v_bf3_pwl_base_set5);</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+}</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_program_easf_h - Program EASF_H</div><div class='add'>+ *</div><div class='add'>+ * @dpp_base: High level DPP struct</div><div class='add'>+ * @scl_data: scalaer_data info</div><div class='add'>+ *</div><div class='add'>+ * This is the primary function to program horizontal EASF registers</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+	/* DSCL_EASF_H_MODE */</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_MODE, 0,</div><div class='add'>+			SCL_EASF_H_EN, scl_data-&gt;dscl_prog_data.easf_h_en,</div><div class='add'>+			SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data-&gt;dscl_prog_data.easf_h_sharp_factor,</div><div class='add'>+			SCL_EASF_H_RINGEST_FORCE_EN, scl_data-&gt;dscl_prog_data.easf_h_ring);</div><div class='add'>+</div><div class='add'>+	if (!scl_data-&gt;dscl_prog_data.easf_h_en) {</div><div class='add'>+		PERF_TRACE();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DSCL_EASF_H_BF_CNTL */</div><div class='add'>+	REG_SET_6(DSCL_EASF_H_BF_CNTL, 0,</div><div class='add'>+			SCL_EASF_H_BF1_EN, scl_data-&gt;dscl_prog_data.easf_h_bf1_en,</div><div class='add'>+			SCL_EASF_H_BF2_MODE, scl_data-&gt;dscl_prog_data.easf_h_bf2_mode,</div><div class='add'>+			SCL_EASF_H_BF3_MODE, scl_data-&gt;dscl_prog_data.easf_h_bf3_mode,</div><div class='add'>+			SCL_EASF_H_BF2_FLAT1_GAIN, scl_data-&gt;dscl_prog_data.easf_h_bf2_flat1_gain,</div><div class='add'>+			SCL_EASF_H_BF2_FLAT2_GAIN, scl_data-&gt;dscl_prog_data.easf_h_bf2_flat2_gain,</div><div class='add'>+			SCL_EASF_H_BF2_ROC_GAIN, scl_data-&gt;dscl_prog_data.easf_h_bf2_roc_gain);</div><div class='add'>+	/* DSCL_EASF_H_RINGEST_EVENTAP_REDUCE */</div><div class='add'>+	REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, 0,</div><div class='add'>+			SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data-&gt;dscl_prog_data.easf_h_ringest_eventap_reduceg1,</div><div class='add'>+			SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data-&gt;dscl_prog_data.easf_h_ringest_eventap_reduceg2);</div><div class='add'>+	/* DSCL_EASF_H_RINGEST_EVENTAP_GAIN */</div><div class='add'>+	REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, 0,</div><div class='add'>+			SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data-&gt;dscl_prog_data.easf_h_ringest_eventap_gain1,</div><div class='add'>+			SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data-&gt;dscl_prog_data.easf_h_ringest_eventap_gain2);</div><div class='add'>+	/* DSCL_EASF_H_BF_FINAL_MAX_MIN */</div><div class='add'>+	REG_SET_4(DSCL_EASF_H_BF_FINAL_MAX_MIN, 0,</div><div class='add'>+			SCL_EASF_H_BF_MAXA, scl_data-&gt;dscl_prog_data.easf_h_bf_maxa,</div><div class='add'>+			SCL_EASF_H_BF_MAXB, scl_data-&gt;dscl_prog_data.easf_h_bf_maxb,</div><div class='add'>+			SCL_EASF_H_BF_MINA, scl_data-&gt;dscl_prog_data.easf_h_bf_mina,</div><div class='add'>+			SCL_EASF_H_BF_MINB, scl_data-&gt;dscl_prog_data.easf_h_bf_minb);</div><div class='add'>+	/* DSCL_EASF_H_BF1_PWL_SEGn */</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG0, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg0);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG1, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg1,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg1,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg1);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG2, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg2,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg2,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg2);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG3, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg3,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg3,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg3);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG4, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg4,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg4,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg4);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG5, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg5,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg5,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg5);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG6, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg6,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg6,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_slope_seg6);</div><div class='add'>+	REG_SET_2(DSCL_EASF_H_BF1_PWL_SEG7, 0,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_in_seg7,</div><div class='add'>+			SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data-&gt;dscl_prog_data.easf_h_bf1_pwl_base_seg7);</div><div class='add'>+	/* DSCL_EASF_H_BF3_PWL_SEGn */</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG0, 0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_in_set0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_base_set0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_slope_set0);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG1, 0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_in_set1,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_base_set1,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_slope_set1);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG2, 0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_in_set2,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_base_set2,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_slope_set2);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG3, 0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_in_set3,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_base_set3,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_slope_set3);</div><div class='add'>+	REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG4, 0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_in_set4,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_base_set4,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_slope_set4);</div><div class='add'>+	REG_SET_2(DSCL_EASF_H_BF3_PWL_SEG5, 0,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_in_set5,</div><div class='add'>+			SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data-&gt;dscl_prog_data.easf_h_bf3_pwl_base_set5);</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+}</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_program_easf - Program EASF</div><div class='add'>+ *</div><div class='add'>+ * @dpp_base: High level DPP struct</div><div class='add'>+ * @scl_data: scalaer_data info</div><div class='add'>+ *</div><div class='add'>+ * This is the primary function to program EASF</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+	/* DSCL_SC_MODE */</div><div class='add'>+	REG_SET_2(DSCL_SC_MODE, 0,</div><div class='add'>+			SCL_SC_MATRIX_MODE, scl_data-&gt;dscl_prog_data.easf_matrix_mode,</div><div class='add'>+			SCL_SC_LTONL_EN, scl_data-&gt;dscl_prog_data.easf_ltonl_en);</div><div class='add'>+	/* DSCL_EASF_SC_MATRIX_C0C1, DSCL_EASF_SC_MATRIX_C2C3 */</div><div class='add'>+	REG_SET_2(DSCL_SC_MATRIX_C0C1, 0,</div><div class='add'>+			SCL_SC_MATRIX_C0, scl_data-&gt;dscl_prog_data.easf_matrix_c0,</div><div class='add'>+			SCL_SC_MATRIX_C1, scl_data-&gt;dscl_prog_data.easf_matrix_c1);</div><div class='add'>+	REG_SET_2(DSCL_SC_MATRIX_C2C3, 0,</div><div class='add'>+			SCL_SC_MATRIX_C2, scl_data-&gt;dscl_prog_data.easf_matrix_c2,</div><div class='add'>+			SCL_SC_MATRIX_C3, scl_data-&gt;dscl_prog_data.easf_matrix_c3);</div><div class='add'>+	dpp401_dscl_program_easf_v(dpp_base, scl_data);</div><div class='add'>+	dpp401_dscl_program_easf_h(dpp_base, scl_data);</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+}</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_disable_easf - Disable EASF when no scaling (1:1)</div><div class='add'>+ *</div><div class='add'>+ * @dpp_base: High level DPP struct</div><div class='add'>+ * @scl_data: scalaer_data info</div><div class='add'>+ *</div><div class='add'>+ * When we have 1:1 scaling, we need to disable EASF</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void dpp401_dscl_disable_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+	/* DSCL_EASF_V_MODE */</div><div class='add'>+	REG_UPDATE(DSCL_EASF_V_MODE,</div><div class='add'>+			SCL_EASF_V_EN, scl_data-&gt;dscl_prog_data.easf_v_en);</div><div class='add'>+	/* DSCL_EASF_H_MODE */</div><div class='add'>+	REG_UPDATE(DSCL_EASF_H_MODE,</div><div class='add'>+			SCL_EASF_H_EN, scl_data-&gt;dscl_prog_data.easf_h_en);</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+}</div><div class='add'>+static void dpp401_dscl_set_isharp_filter(</div><div class='add'>+	struct dcn401_dpp *dpp, const uint32_t *filter)</div><div class='add'>+{</div><div class='add'>+	int level;</div><div class='add'>+	uint32_t filter_data;</div><div class='add'>+	if (filter == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(ISHARP_DELTA_CTRL,</div><div class='add'>+		ISHARP_DELTA_LUT_HOST_SELECT, 0);</div><div class='add'>+	/* LUT data write is auto-indexed.  Write index once */</div><div class='add'>+	REG_SET(ISHARP_DELTA_INDEX, 0,</div><div class='add'>+			ISHARP_DELTA_INDEX, 0);</div><div class='add'>+	for (level = 0; level &lt; NUM_LEVELS; level++)	{</div><div class='add'>+		filter_data = filter[level];</div><div class='add'>+		REG_SET(ISHARP_DELTA_DATA, 0,</div><div class='add'>+				ISHARP_DELTA_DATA, filter_data);</div><div class='add'>+	}</div><div class='add'>+} // dpp401_dscl_set_isharp_filter</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_program_isharp - Program isharp</div><div class='add'>+ *</div><div class='add'>+ * @dpp_base: High level DPP struct</div><div class='add'>+ * @scl_data: scalaer_data info</div><div class='add'>+ * @program_isharp_1dlut: flag to program isharp 1D LUT</div><div class='add'>+ * @bs_coeffs_updated: Blur and Scale Coefficients update flag</div><div class='add'>+ *</div><div class='add'>+ * This is the primary function to program isharp</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void dpp401_dscl_program_isharp(struct dpp *dpp_base,</div><div class='add'>+		const struct scaler_data *scl_data,</div><div class='add'>+		bool program_isharp_1dlut,</div><div class='add'>+		bool *bs_coeffs_updated)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+	*bs_coeffs_updated = false;</div><div class='add'>+</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+	/* ISHARP_MODE */</div><div class='add'>+	REG_SET_6(ISHARP_MODE, 0,</div><div class='add'>+		ISHARP_EN, scl_data-&gt;dscl_prog_data.isharp_en,</div><div class='add'>+		ISHARP_NOISEDET_EN, scl_data-&gt;dscl_prog_data.isharp_noise_det.enable,</div><div class='add'>+		ISHARP_NOISEDET_MODE, scl_data-&gt;dscl_prog_data.isharp_noise_det.mode,</div><div class='add'>+		ISHARP_LBA_MODE, scl_data-&gt;dscl_prog_data.isharp_lba.mode,</div><div class='add'>+		ISHARP_FMT_MODE, scl_data-&gt;dscl_prog_data.isharp_fmt.mode,</div><div class='add'>+		ISHARP_FMT_NORM, scl_data-&gt;dscl_prog_data.isharp_fmt.norm);</div><div class='add'>+</div><div class='add'>+	/* Skip remaining register programming if ISHARP is disabled */</div><div class='add'>+	if (!scl_data-&gt;dscl_prog_data.isharp_en) {</div><div class='add'>+		PERF_TRACE();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* ISHARP_NOISEDET_THRESHOLD */</div><div class='add'>+	REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0,</div><div class='add'>+		ISHARP_NOISEDET_UTHRE, scl_data-&gt;dscl_prog_data.isharp_noise_det.uthreshold,</div><div class='add'>+		ISHARP_NOISEDET_DTHRE, scl_data-&gt;dscl_prog_data.isharp_noise_det.dthreshold);</div><div class='add'>+</div><div class='add'>+	/* ISHARP_NOISE_GAIN_PWL */</div><div class='add'>+	REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0,</div><div class='add'>+		ISHARP_NOISEDET_PWL_START_IN, scl_data-&gt;dscl_prog_data.isharp_noise_det.pwl_start_in,</div><div class='add'>+		ISHARP_NOISEDET_PWL_END_IN, scl_data-&gt;dscl_prog_data.isharp_noise_det.pwl_end_in,</div><div class='add'>+		ISHARP_NOISEDET_PWL_SLOPE, scl_data-&gt;dscl_prog_data.isharp_noise_det.pwl_slope);</div><div class='add'>+</div><div class='add'>+	/* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */</div><div class='add'>+	REG_SET_3(ISHARP_LBA_PWL_SEG0, 0,</div><div class='add'>+		ISHARP_LBA_PWL_IN_SEG0, scl_data-&gt;dscl_prog_data.isharp_lba.in_seg[0],</div><div class='add'>+		ISHARP_LBA_PWL_BASE_SEG0, scl_data-&gt;dscl_prog_data.isharp_lba.base_seg[0],</div><div class='add'>+		ISHARP_LBA_PWL_SLOPE_SEG0, scl_data-&gt;dscl_prog_data.isharp_lba.slope_seg[0]);</div><div class='add'>+	REG_SET_3(ISHARP_LBA_PWL_SEG1, 0,</div><div class='add'>+		ISHARP_LBA_PWL_IN_SEG1, scl_data-&gt;dscl_prog_data.isharp_lba.in_seg[1],</div><div class='add'>+		ISHARP_LBA_PWL_BASE_SEG1, scl_data-&gt;dscl_prog_data.isharp_lba.base_seg[1],</div><div class='add'>+		ISHARP_LBA_PWL_SLOPE_SEG1, scl_data-&gt;dscl_prog_data.isharp_lba.slope_seg[1]);</div><div class='add'>+	REG_SET_3(ISHARP_LBA_PWL_SEG2, 0,</div><div class='add'>+		ISHARP_LBA_PWL_IN_SEG2, scl_data-&gt;dscl_prog_data.isharp_lba.in_seg[2],</div><div class='add'>+		ISHARP_LBA_PWL_BASE_SEG2, scl_data-&gt;dscl_prog_data.isharp_lba.base_seg[2],</div><div class='add'>+		ISHARP_LBA_PWL_SLOPE_SEG2, scl_data-&gt;dscl_prog_data.isharp_lba.slope_seg[2]);</div><div class='add'>+	REG_SET_3(ISHARP_LBA_PWL_SEG3, 0,</div><div class='add'>+		ISHARP_LBA_PWL_IN_SEG3, scl_data-&gt;dscl_prog_data.isharp_lba.in_seg[3],</div><div class='add'>+		ISHARP_LBA_PWL_BASE_SEG3, scl_data-&gt;dscl_prog_data.isharp_lba.base_seg[3],</div><div class='add'>+		ISHARP_LBA_PWL_SLOPE_SEG3, scl_data-&gt;dscl_prog_data.isharp_lba.slope_seg[3]);</div><div class='add'>+	REG_SET_3(ISHARP_LBA_PWL_SEG4, 0,</div><div class='add'>+		ISHARP_LBA_PWL_IN_SEG4, scl_data-&gt;dscl_prog_data.isharp_lba.in_seg[4],</div><div class='add'>+		ISHARP_LBA_PWL_BASE_SEG4, scl_data-&gt;dscl_prog_data.isharp_lba.base_seg[4],</div><div class='add'>+		ISHARP_LBA_PWL_SLOPE_SEG4, scl_data-&gt;dscl_prog_data.isharp_lba.slope_seg[4]);</div><div class='add'>+	REG_SET_2(ISHARP_LBA_PWL_SEG5, 0,</div><div class='add'>+		ISHARP_LBA_PWL_IN_SEG5, scl_data-&gt;dscl_prog_data.isharp_lba.in_seg[5],</div><div class='add'>+		ISHARP_LBA_PWL_BASE_SEG5, scl_data-&gt;dscl_prog_data.isharp_lba.base_seg[5]);</div><div class='add'>+</div><div class='add'>+	/* ISHARP_DELTA_LUT */</div><div class='add'>+	if (!program_isharp_1dlut)</div><div class='add'>+		dpp401_dscl_set_isharp_filter(dpp, scl_data-&gt;dscl_prog_data.isharp_delta);</div><div class='add'>+</div><div class='add'>+	/* ISHARP_NLDELTA_SOFT_CLIP */</div><div class='add'>+	REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0,</div><div class='add'>+		ISHARP_NLDELTA_SCLIP_EN_P, scl_data-&gt;dscl_prog_data.isharp_nldelta_sclip.enable_p,</div><div class='add'>+		ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data-&gt;dscl_prog_data.isharp_nldelta_sclip.pivot_p,</div><div class='add'>+		ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data-&gt;dscl_prog_data.isharp_nldelta_sclip.slope_p,</div><div class='add'>+		ISHARP_NLDELTA_SCLIP_EN_N, scl_data-&gt;dscl_prog_data.isharp_nldelta_sclip.enable_n,</div><div class='add'>+		ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data-&gt;dscl_prog_data.isharp_nldelta_sclip.pivot_n,</div><div class='add'>+		ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data-&gt;dscl_prog_data.isharp_nldelta_sclip.slope_n);</div><div class='add'>+</div><div class='add'>+	/* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */</div><div class='add'>+	if (scl_data-&gt;dscl_prog_data.isharp_en) {</div><div class='add'>+		if (scl_data-&gt;dscl_prog_data.filter_blur_scale_v) {</div><div class='add'>+			dpp401_dscl_set_scaler_filter(</div><div class='add'>+				dpp, scl_data-&gt;taps.v_taps,</div><div class='add'>+				SCL_COEF_VERTICAL_BLUR_SCALE,</div><div class='add'>+				scl_data-&gt;dscl_prog_data.filter_blur_scale_v);</div><div class='add'>+			*bs_coeffs_updated = true;</div><div class='add'>+		}</div><div class='add'>+		if (scl_data-&gt;dscl_prog_data.filter_blur_scale_h) {</div><div class='add'>+			dpp401_dscl_set_scaler_filter(</div><div class='add'>+				dpp, scl_data-&gt;taps.h_taps,</div><div class='add'>+				SCL_COEF_HORIZONTAL_BLUR_SCALE,</div><div class='add'>+				scl_data-&gt;dscl_prog_data.filter_blur_scale_h);</div><div class='add'>+			*bs_coeffs_updated = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+} // dpp401_dscl_program_isharp</div><div class='add'>+/**</div><div class='add'>+ * dpp401_dscl_set_scaler_manual_scale - Manually program scaler and line buffer</div><div class='add'>+ *</div><div class='add'>+ * @dpp_base: High level DPP struct</div><div class='add'>+ * @scl_data: scalaer_data info</div><div class='add'>+ *</div><div class='add'>+ * This is the primary function to program scaler and line buffer in manual</div><div class='add'>+ * scaling mode. To execute the required operations for manual scale, we need</div><div class='add'>+ * to disable AutoCal first.</div><div class='add'>+ */</div><div class='add'>+void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base,</div><div class='add'>+				       const struct scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	enum lb_memory_config lb_config;</div><div class='add'>+	struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);</div><div class='add'>+	const struct rect *rect = &amp;scl_data-&gt;recout;</div><div class='add'>+	uint32_t mpc_width = scl_data-&gt;h_active;</div><div class='add'>+	uint32_t mpc_height = scl_data-&gt;v_active;</div><div class='add'>+	uint32_t v_num_taps = scl_data-&gt;taps.v_taps - 1;</div><div class='add'>+	uint32_t v_num_taps_c = scl_data-&gt;taps.v_taps_c - 1;</div><div class='add'>+	uint32_t h_num_taps = scl_data-&gt;taps.h_taps - 1;</div><div class='add'>+	uint32_t h_num_taps_c = scl_data-&gt;taps.h_taps_c - 1;</div><div class='add'>+	enum dcn401_dscl_mode_sel dscl_mode = dpp401_dscl_get_dscl_mode(</div><div class='add'>+			dpp_base, scl_data, dpp_base-&gt;ctx-&gt;dc-&gt;debug.always_scale);</div><div class='add'>+	bool ycbcr = scl_data-&gt;format &gt;= PIXEL_FORMAT_VIDEO_BEGIN</div><div class='add'>+				&amp;&amp; scl_data-&gt;format &lt;= PIXEL_FORMAT_VIDEO_END;</div><div class='add'>+	bool program_isharp_1dlut = false;</div><div class='add'>+	bool bs_coeffs_updated = false;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (memcmp(&amp;dpp-&gt;scl_data, scl_data, sizeof(*scl_data)) == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+</div><div class='add'>+	/* If only sharpness has changed, then only update 1dlut, then return */</div><div class='add'>+	if (scl_data-&gt;dscl_prog_data.isharp_en &amp;&amp;</div><div class='add'>+		(dpp-&gt;scl_data.dscl_prog_data.sharpness_level</div><div class='add'>+		!= scl_data-&gt;dscl_prog_data.sharpness_level)) {</div><div class='add'>+		/* ISHARP_DELTA_LUT */</div><div class='add'>+		dpp401_dscl_set_isharp_filter(dpp, scl_data-&gt;dscl_prog_data.isharp_delta);</div><div class='add'>+		dpp-&gt;scl_data.dscl_prog_data.sharpness_level = scl_data-&gt;dscl_prog_data.sharpness_level;</div><div class='add'>+		memcpy(dpp-&gt;scl_data.dscl_prog_data.isharp_delta, scl_data-&gt;dscl_prog_data.isharp_delta,</div><div class='add'>+			sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE);</div><div class='add'>+</div><div class='add'>+		if (memcmp(&amp;dpp-&gt;scl_data, scl_data, sizeof(*scl_data)) == 0)</div><div class='add'>+			return;</div><div class='add'>+		program_isharp_1dlut = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dpp-&gt;scl_data = *scl_data;</div><div class='add'>+</div><div class='add'>+	if ((dpp-&gt;base.ctx-&gt;dc-&gt;config.use_spl) &amp;&amp; (!dpp-&gt;base.ctx-&gt;dc-&gt;debug.disable_spl)) {</div><div class='add'>+		dscl_mode = (enum dcn401_dscl_mode_sel) scl_data-&gt;dscl_prog_data.dscl_mode;</div><div class='add'>+		rect = (struct rect *)&amp;scl_data-&gt;dscl_prog_data.recout;</div><div class='add'>+		mpc_width = scl_data-&gt;dscl_prog_data.mpc_size.width;</div><div class='add'>+		mpc_height = scl_data-&gt;dscl_prog_data.mpc_size.height;</div><div class='add'>+		v_num_taps = scl_data-&gt;dscl_prog_data.taps.v_taps;</div><div class='add'>+		v_num_taps_c = scl_data-&gt;dscl_prog_data.taps.v_taps_c;</div><div class='add'>+		h_num_taps = scl_data-&gt;dscl_prog_data.taps.h_taps;</div><div class='add'>+		h_num_taps_c = scl_data-&gt;dscl_prog_data.taps.h_taps_c;</div><div class='add'>+	}</div><div class='add'>+	if (dpp_base-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.dscl) {</div><div class='add'>+		if (dscl_mode != DCN401_DSCL_MODE_DSCL_BYPASS)</div><div class='add'>+			dpp401_power_on_dscl(dpp_base, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Autocal off */</div><div class='add'>+	REG_SET_3(DSCL_AUTOCAL, 0,</div><div class='add'>+		AUTOCAL_MODE, AUTOCAL_MODE_OFF,</div><div class='add'>+		AUTOCAL_NUM_PIPE, 0,</div><div class='add'>+		AUTOCAL_PIPE_ID, 0);</div><div class='add'>+</div><div class='add'>+	/*clean scaler boundary mode when Autocal off*/</div><div class='add'>+	REG_SET(DSCL_CONTROL, 0,</div><div class='add'>+		SCL_BOUNDARY_MODE, 0);</div><div class='add'>+</div><div class='add'>+	/* Recout */</div><div class='add'>+	dpp401_dscl_set_recout(dpp, rect);</div><div class='add'>+</div><div class='add'>+	/* MPC Size */</div><div class='add'>+	REG_SET_2(MPC_SIZE, 0,</div><div class='add'>+		/* Number of horizontal pixels of MPC */</div><div class='add'>+			 MPC_WIDTH, mpc_width,</div><div class='add'>+		/* Number of vertical lines of MPC */</div><div class='add'>+			 MPC_HEIGHT, mpc_height);</div><div class='add'>+</div><div class='add'>+	/* SCL mode */</div><div class='add'>+	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);</div><div class='add'>+</div><div class='add'>+	if (dscl_mode == DCN401_DSCL_MODE_DSCL_BYPASS) {</div><div class='add'>+		if (dpp_base-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.dscl)</div><div class='add'>+			dpp401_power_on_dscl(dpp_base, false);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* LB */</div><div class='add'>+	lb_config =  dpp401_dscl_find_lb_memory_config(dpp, scl_data);</div><div class='add'>+	dpp401_dscl_set_lb(dpp, &amp;scl_data-&gt;lb_params, lb_config);</div><div class='add'>+</div><div class='add'>+	if (dscl_mode == DCN401_DSCL_MODE_SCALING_444_BYPASS) {</div><div class='add'>+		if (dpp-&gt;base.ctx-&gt;dc-&gt;config.prefer_easf)</div><div class='add'>+			dpp401_dscl_disable_easf(dpp_base, scl_data);</div><div class='add'>+		dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &amp;bs_coeffs_updated);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Black offsets */</div><div class='add'>+	if (REG(SCL_BLACK_OFFSET)) {</div><div class='add'>+		if (ycbcr)</div><div class='add'>+			REG_SET_2(SCL_BLACK_OFFSET, 0,</div><div class='add'>+					SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,</div><div class='add'>+					SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);</div><div class='add'>+		else</div><div class='add'>+</div><div class='add'>+			REG_SET_2(SCL_BLACK_OFFSET, 0,</div><div class='add'>+					SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,</div><div class='add'>+					SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Manually calculate scale ratio and init values */</div><div class='add'>+	dpp401_dscl_set_manual_ratio_init(dpp, scl_data);</div><div class='add'>+</div><div class='add'>+	/* HTaps/VTaps */</div><div class='add'>+	REG_SET_4(SCL_TAP_CONTROL, 0,</div><div class='add'>+		SCL_V_NUM_TAPS, v_num_taps,</div><div class='add'>+		SCL_H_NUM_TAPS, h_num_taps,</div><div class='add'>+		SCL_V_NUM_TAPS_C, v_num_taps_c,</div><div class='add'>+		SCL_H_NUM_TAPS_C, h_num_taps_c);</div><div class='add'>+</div><div class='add'>+	/* ISharp configuration</div><div class='add'>+	 * - B&amp;S coeffs are written to same coeff RAM as WB scaler coeffs</div><div class='add'>+	 * - coeff RAM toggle is in EASF programming</div><div class='add'>+	 * - if we are only programming B&amp;S coeffs, then need to reprogram</div><div class='add'>+	 *   WB scaler coeffs and toggle coeff RAM together</div><div class='add'>+	 */</div><div class='add'>+	//if (dpp-&gt;base.ctx-&gt;dc-&gt;config.prefer_easf)</div><div class='add'>+	dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &amp;bs_coeffs_updated);</div><div class='add'>+</div><div class='add'>+	dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated);</div><div class='add'>+	/* Edge adaptive scaler function configuration */</div><div class='add'>+	if (dpp-&gt;base.ctx-&gt;dc-&gt;config.prefer_easf)</div><div class='add'>+		dpp401_dscl_program_easf(dpp_base, scl_data);</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile<br/>index b183ba5a692e..94883c4e4c61 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/Makefile</a></div><div class='hunk'>@@ -1,6 +1,5 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='del'>-#</div><div class='del'>-# Makefile for the 'dsc' sub-component of DAL.</div><div class='add'>+# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> </div><div class='hunk'>@@ -22,7 +21,13 @@ DSC_DCN35 = dcn35_dsc.o</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))</div><div class='ctx'> </div><div class='add'>+###############################################################################</div><div class='add'>+# DCN401</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DSC_DCN401 += dcn401_dsc.o</div><div class='ctx'> </div><div class='add'>+AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))</div><div class='ctx'> </div><div class='ctx'> endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c<br/>index ac41f9c0a283..e4144b244332 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c</a></div><div class='hunk'>@@ -30,6 +30,12 @@</div><div class='ctx'> #include "rc_calc.h"</div><div class='ctx'> #include "fixed31_32.h"</div><div class='ctx'> </div><div class='add'>+#include "clk_mgr.h"</div><div class='add'>+#include "resource.h"</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dsc-&gt;ctx-&gt;logger</div><div class='add'>+</div><div class='ctx'> /* This module's internal functions */</div><div class='ctx'> </div><div class='ctx'> /* default DSC policy target bitrate limit is 16bpp */</div><div class='hunk'>@@ -145,8 +151,12 @@ uint32_t dc_bandwidth_in_kbps_from_timing(</div><div class='ctx'> 	return kbps;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> /* Forward Declerations */</div><div class='add'>+static unsigned int get_min_dsc_slice_count_for_odm(</div><div class='add'>+		const struct display_stream_compressor *dsc,</div><div class='add'>+		const struct dsc_enc_caps *dsc_enc_caps,</div><div class='add'>+		const struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='ctx'> static bool decide_dsc_bandwidth_range(</div><div class='ctx'> 		const uint32_t min_bpp_x16,</div><div class='ctx'> 		const uint32_t max_bpp_x16,</div><div class='hunk'>@@ -181,6 +191,7 @@ static bool setup_dsc_config(</div><div class='ctx'> 		const struct dc_crtc_timing *timing,</div><div class='ctx'> 		const struct dc_dsc_config_options *options,</div><div class='ctx'> 		const enum dc_link_encoding_format link_encoding,</div><div class='add'>+		int min_slice_count,</div><div class='ctx'> 		struct dc_dsc_config *dsc_cfg);</div><div class='ctx'> </div><div class='ctx'> static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)</div><div class='hunk'>@@ -440,7 +451,6 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> /* If DSC is possbile, get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range and</div><div class='ctx'>  * timing's pixel clock and uncompressed bandwidth.</div><div class='ctx'>  * If DSC is not possible, leave '*range' untouched.</div><div class='hunk'>@@ -456,9 +466,10 @@ bool dc_dsc_compute_bandwidth_range(</div><div class='ctx'> 		struct dc_dsc_bw_range *range)</div><div class='ctx'> {</div><div class='ctx'> 	bool is_dsc_possible = false;</div><div class='add'>+	unsigned int min_dsc_slice_count;</div><div class='ctx'> 	struct dsc_enc_caps dsc_enc_caps;</div><div class='ctx'> 	struct dsc_enc_caps dsc_common_caps;</div><div class='del'>-	struct dc_dsc_config config;</div><div class='add'>+	struct dc_dsc_config config = {0};</div><div class='ctx'> 	struct dc_dsc_config_options options = {0};</div><div class='ctx'> </div><div class='ctx'> 	options.dsc_min_slice_height_override = dsc_min_slice_height_override;</div><div class='hunk'>@@ -467,12 +478,14 @@ bool dc_dsc_compute_bandwidth_range(</div><div class='ctx'> </div><div class='ctx'> 	get_dsc_enc_caps(dsc, &amp;dsc_enc_caps, timing-&gt;pix_clk_100hz);</div><div class='ctx'> </div><div class='add'>+	min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &amp;dsc_enc_caps, timing);</div><div class='add'>+</div><div class='ctx'> 	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &amp;dsc_enc_caps,</div><div class='ctx'> 			timing-&gt;pixel_encoding, &amp;dsc_common_caps);</div><div class='ctx'> </div><div class='ctx'> 	if (is_dsc_possible)</div><div class='ctx'> 		is_dsc_possible = setup_dsc_config(dsc_sink_caps, &amp;dsc_enc_caps, 0, timing,</div><div class='del'>-				&amp;options, link_encoding, &amp;config);</div><div class='add'>+				&amp;options, link_encoding, min_dsc_slice_count, &amp;config);</div><div class='ctx'> </div><div class='ctx'> 	if (is_dsc_possible)</div><div class='ctx'> 		is_dsc_possible = decide_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16,</div><div class='hunk'>@@ -481,20 +494,195 @@ bool dc_dsc_compute_bandwidth_range(</div><div class='ctx'> 	return is_dsc_possible;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,</div><div class='add'>+			      const struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	struct dsc_enc_caps dsc_enc_caps;</div><div class='add'>+</div><div class='add'>+	get_dsc_enc_caps(dsc, &amp;dsc_enc_caps, timing-&gt;pix_clk_100hz);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DSC("dsc encoder caps:");</div><div class='add'>+	DC_LOG_DSC("\tdsc_version 0x%x", dsc_enc_caps.dsc_version);</div><div class='add'>+	DC_LOG_DSC("\tslice_caps 0x%x", dsc_enc_caps.slice_caps.raw);</div><div class='add'>+	DC_LOG_DSC("\tlb_bit_depth %d", dsc_enc_caps.lb_bit_depth);</div><div class='add'>+	DC_LOG_DSC("\tis_block_pred_supported %d", dsc_enc_caps.is_block_pred_supported);</div><div class='add'>+	DC_LOG_DSC("\tcolor_formats 0x%x", dsc_enc_caps.color_formats.raw);</div><div class='add'>+	DC_LOG_DSC("\tcolor_depth 0x%x", dsc_enc_caps.color_depth.raw);</div><div class='add'>+	DC_LOG_DSC("\tmax_total_throughput_mps %d", dsc_enc_caps.max_total_throughput_mps);</div><div class='add'>+	DC_LOG_DSC("\tmax_slice_width %d", dsc_enc_caps.max_slice_width);</div><div class='add'>+	DC_LOG_DSC("\tbpp_increment_div %d", dsc_enc_caps.bpp_increment_div);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,</div><div class='add'>+			      const struct dsc_dec_dpcd_caps *dsc_sink_caps)</div><div class='add'>+{</div><div class='add'>+	DC_LOG_DSC("dsc decoder caps:");</div><div class='add'>+	DC_LOG_DSC("\tis_dsc_supported %d", dsc_sink_caps-&gt;is_dsc_supported);</div><div class='add'>+	DC_LOG_DSC("\tdsc_version 0x%x", dsc_sink_caps-&gt;dsc_version);</div><div class='add'>+	DC_LOG_DSC("\trc_buffer_size %d", dsc_sink_caps-&gt;rc_buffer_size);</div><div class='add'>+	DC_LOG_DSC("\tslice_caps1 0x%x", dsc_sink_caps-&gt;slice_caps1.raw);</div><div class='add'>+	DC_LOG_DSC("\tslice_caps2 0x%x", dsc_sink_caps-&gt;slice_caps2.raw);</div><div class='add'>+	DC_LOG_DSC("\tlb_bit_depth %d", dsc_sink_caps-&gt;lb_bit_depth);</div><div class='add'>+	DC_LOG_DSC("\tis_block_pred_supported %d", dsc_sink_caps-&gt;is_block_pred_supported);</div><div class='add'>+	DC_LOG_DSC("\tedp_max_bits_per_pixel %d", dsc_sink_caps-&gt;edp_max_bits_per_pixel);</div><div class='add'>+	DC_LOG_DSC("\tcolor_formats 0x%x", dsc_sink_caps-&gt;color_formats.raw);</div><div class='add'>+	DC_LOG_DSC("\tthroughput_mode_0_mps %d", dsc_sink_caps-&gt;throughput_mode_0_mps);</div><div class='add'>+	DC_LOG_DSC("\tthroughput_mode_1_mps %d", dsc_sink_caps-&gt;throughput_mode_1_mps);</div><div class='add'>+	DC_LOG_DSC("\tmax_slice_width %d", dsc_sink_caps-&gt;max_slice_width);</div><div class='add'>+	DC_LOG_DSC("\tbpp_increment_div %d", dsc_sink_caps-&gt;bpp_increment_div);</div><div class='add'>+	DC_LOG_DSC("\tbranch_overall_throughput_0_mps %d", dsc_sink_caps-&gt;branch_overall_throughput_0_mps);</div><div class='add'>+	DC_LOG_DSC("\tbranch_overall_throughput_1_mps %d", dsc_sink_caps-&gt;branch_overall_throughput_1_mps);</div><div class='add'>+	DC_LOG_DSC("\tbranch_max_line_width %d", dsc_sink_caps-&gt;branch_max_line_width);</div><div class='add'>+	DC_LOG_DSC("\tis_dp %d", dsc_sink_caps-&gt;is_dp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void build_dsc_enc_combined_slice_caps(</div><div class='add'>+		const struct dsc_enc_caps *single_dsc_enc_caps,</div><div class='add'>+		struct dsc_enc_caps *dsc_enc_caps,</div><div class='add'>+		unsigned int max_odm_combine_factor)</div><div class='add'>+{</div><div class='add'>+	/* 1-16 slice configurations, single DSC */</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.raw |= single_dsc_enc_caps-&gt;slice_caps.raw;</div><div class='add'>+</div><div class='add'>+	/* 2x DSC's */</div><div class='add'>+	if (max_odm_combine_factor &gt;= 2) {</div><div class='add'>+		/* 1 + 1 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_2 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_1;</div><div class='add'>+</div><div class='add'>+		/* 2 + 2 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_2;</div><div class='add'>+</div><div class='add'>+		/* 4 + 4 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4;</div><div class='add'>+</div><div class='add'>+		/* 8 + 8 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_8;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 3x DSC's */</div><div class='add'>+	if (max_odm_combine_factor &gt;= 3) {</div><div class='add'>+		/* 4 + 4 + 4 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 4x DSC's */</div><div class='add'>+	if (max_odm_combine_factor &gt;= 4) {</div><div class='add'>+		/* 1 + 1 + 1 + 1 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_1;</div><div class='add'>+</div><div class='add'>+		/* 2 + 2 + 2 + 2 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_2;</div><div class='add'>+</div><div class='add'>+		/* 3 + 3 + 3 + 3 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_3;</div><div class='add'>+</div><div class='add'>+		/* 4 + 4 + 4 + 4 */</div><div class='add'>+		dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void build_dsc_enc_caps(</div><div class='add'>+		const struct display_stream_compressor *dsc,</div><div class='add'>+		struct dsc_enc_caps *dsc_enc_caps)</div><div class='add'>+{</div><div class='add'>+	unsigned int max_dscclk_khz;</div><div class='add'>+	unsigned int num_dsc;</div><div class='add'>+	unsigned int max_odm_combine_factor;</div><div class='add'>+	struct dsc_enc_caps single_dsc_enc_caps;</div><div class='add'>+</div><div class='add'>+	struct dc *dc;</div><div class='add'>+</div><div class='add'>+	if (!dsc || !dsc-&gt;ctx || !dsc-&gt;ctx-&gt;dc || !dsc-&gt;funcs-&gt;dsc_get_single_enc_caps)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dc = dsc-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;clk_mgr || !dc-&gt;clk_mgr-&gt;funcs-&gt;get_max_clock_khz || !dc-&gt;res_pool || dc-&gt;debug.disable_dsc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* get max DSCCLK from clk_mgr */</div><div class='add'>+	max_dscclk_khz = dc-&gt;clk_mgr-&gt;funcs-&gt;get_max_clock_khz(dc-&gt;clk_mgr, CLK_TYPE_DSCCLK);</div><div class='add'>+</div><div class='add'>+	dsc-&gt;funcs-&gt;dsc_get_single_enc_caps(&amp;single_dsc_enc_caps, max_dscclk_khz);</div><div class='add'>+</div><div class='add'>+	/* global capabilities */</div><div class='add'>+	dsc_enc_caps-&gt;dsc_version = single_dsc_enc_caps.dsc_version;</div><div class='add'>+	dsc_enc_caps-&gt;lb_bit_depth = single_dsc_enc_caps.lb_bit_depth;</div><div class='add'>+	dsc_enc_caps-&gt;is_block_pred_supported = single_dsc_enc_caps.is_block_pred_supported;</div><div class='add'>+	dsc_enc_caps-&gt;max_slice_width = single_dsc_enc_caps.max_slice_width;</div><div class='add'>+	dsc_enc_caps-&gt;bpp_increment_div = single_dsc_enc_caps.bpp_increment_div;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.raw = single_dsc_enc_caps.color_formats.raw;</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.raw = single_dsc_enc_caps.color_depth.raw;</div><div class='add'>+</div><div class='add'>+	/* expand per DSC capabilities to global */</div><div class='add'>+	max_odm_combine_factor = dc-&gt;caps.max_odm_combine_factor;</div><div class='add'>+	num_dsc = dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc;</div><div class='add'>+	max_odm_combine_factor = min(max_odm_combine_factor, num_dsc);</div><div class='add'>+	dsc_enc_caps-&gt;max_total_throughput_mps =</div><div class='add'>+			single_dsc_enc_caps.max_total_throughput_mps *</div><div class='add'>+			max_odm_combine_factor;</div><div class='add'>+</div><div class='add'>+	/* check slice counts possible for with ODM combine */</div><div class='add'>+	build_dsc_enc_combined_slice_caps(&amp;single_dsc_enc_caps, dsc_enc_caps, max_odm_combine_factor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline uint32_t dsc_div_by_10_round_up(uint32_t value)</div><div class='add'>+{</div><div class='add'>+	return (value + 9) / 10;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int get_min_dsc_slice_count_for_odm(</div><div class='add'>+		const struct display_stream_compressor *dsc,</div><div class='add'>+		const struct dsc_enc_caps *dsc_enc_caps,</div><div class='add'>+		const struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	unsigned int max_dispclk_khz;</div><div class='add'>+</div><div class='add'>+	/* get max pixel rate and combine caps */</div><div class='add'>+	max_dispclk_khz = dsc_enc_caps-&gt;max_total_throughput_mps * 1000;</div><div class='add'>+	if (dsc &amp;&amp; dsc-&gt;ctx-&gt;dc) {</div><div class='add'>+		if (dsc-&gt;ctx-&gt;dc-&gt;clk_mgr &amp;&amp;</div><div class='add'>+			dsc-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;funcs-&gt;get_max_clock_khz) {</div><div class='add'>+			/* dispclk is available */</div><div class='add'>+			max_dispclk_khz = dsc-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;funcs-&gt;get_max_clock_khz(dsc-&gt;ctx-&gt;dc-&gt;clk_mgr, CLK_TYPE_DISPCLK);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* validate parameters */</div><div class='add'>+	if (max_dispclk_khz == 0 || dsc_enc_caps-&gt;max_slice_width == 0)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	/* consider minimum odm slices required due to</div><div class='add'>+	 * 1) display pipe throughput (dispclk)</div><div class='add'>+	 * 2) max image width per slice</div><div class='add'>+	 */</div><div class='add'>+	return dc_fixpt_ceil(dc_fixpt_max(</div><div class='add'>+			dc_fixpt_div_int(dc_fixpt_from_int(dsc_div_by_10_round_up(timing-&gt;pix_clk_100hz)),</div><div class='add'>+			max_dispclk_khz), // throughput</div><div class='add'>+			dc_fixpt_div_int(dc_fixpt_from_int(timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right),</div><div class='add'>+			dsc_enc_caps-&gt;max_slice_width))); // slice width</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void get_dsc_enc_caps(</div><div class='ctx'> 		const struct display_stream_compressor *dsc,</div><div class='ctx'> 		struct dsc_enc_caps *dsc_enc_caps,</div><div class='ctx'> 		int pixel_clock_100Hz)</div><div class='ctx'> {</div><div class='del'>-	// This is a static HW query, so we can use any DSC</div><div class='del'>-</div><div class='ctx'> 	memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));</div><div class='del'>-	if (dsc) {</div><div class='del'>-		if (!dsc-&gt;ctx-&gt;dc-&gt;debug.disable_dsc)</div><div class='del'>-			dsc-&gt;funcs-&gt;dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);</div><div class='del'>-		if (dsc-&gt;ctx-&gt;dc-&gt;debug.native422_support)</div><div class='del'>-			dsc_enc_caps-&gt;color_formats.bits.YCBCR_NATIVE_422 = 1;</div><div class='add'>+</div><div class='add'>+	if (!dsc || !dsc-&gt;ctx || !dsc-&gt;ctx-&gt;dc || dsc-&gt;ctx-&gt;dc-&gt;debug.disable_dsc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* check if reported cap global or only for a single DCN DSC enc */</div><div class='add'>+	if (dsc-&gt;funcs-&gt;dsc_get_enc_caps) {</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);</div><div class='add'>+	} else {</div><div class='add'>+		build_dsc_enc_caps(dsc, dsc_enc_caps);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (dsc-&gt;ctx-&gt;dc-&gt;debug.native422_support)</div><div class='add'>+		dsc_enc_caps-&gt;color_formats.bits.YCBCR_NATIVE_422 = 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Returns 'false' if no intersection was found for at least one capability.</div><div class='hunk'>@@ -577,11 +765,6 @@ static bool intersect_dsc_caps(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline uint32_t dsc_div_by_10_round_up(uint32_t value)</div><div class='del'>-{</div><div class='del'>-	return (value + 9) / 10;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static uint32_t compute_bpp_x16_from_target_bandwidth(</div><div class='ctx'> 	const uint32_t bandwidth_in_kbps,</div><div class='ctx'> 	const struct dc_crtc_timing *timing,</div><div class='hunk'>@@ -669,6 +852,7 @@ static bool decide_dsc_bandwidth_range(</div><div class='ctx'>  */</div><div class='ctx'> static bool decide_dsc_target_bpp_x16(</div><div class='ctx'> 		const struct dc_dsc_policy *policy,</div><div class='add'>+		const struct dc_dsc_config_options *options,</div><div class='ctx'> 		const struct dsc_enc_caps *dsc_common_caps,</div><div class='ctx'> 		const int target_bandwidth_kbps,</div><div class='ctx'> 		const struct dc_crtc_timing *timing,</div><div class='hunk'>@@ -683,7 +867,7 @@ static bool decide_dsc_target_bpp_x16(</div><div class='ctx'> 	if (decide_dsc_bandwidth_range(policy-&gt;min_target_bpp * 16, policy-&gt;max_target_bpp * 16,</div><div class='ctx'> 			num_slices_h, dsc_common_caps, timing, link_encoding, &amp;range)) {</div><div class='ctx'> 		if (target_bandwidth_kbps &gt;= range.stream_kbps) {</div><div class='del'>-			if (policy-&gt;enable_dsc_when_not_needed)</div><div class='add'>+			if (policy-&gt;enable_dsc_when_not_needed || options-&gt;force_dsc_when_not_needed)</div><div class='ctx'> 				/* enable max bpp even dsc is not needed */</div><div class='ctx'> 				*target_bpp_x16 = range.max_target_bpp_x16;</div><div class='ctx'> 		} else if (target_bandwidth_kbps &gt;= range.max_kbps) {</div><div class='hunk'>@@ -865,12 +1049,12 @@ static bool setup_dsc_config(</div><div class='ctx'> 		const struct dc_crtc_timing *timing,</div><div class='ctx'> 		const struct dc_dsc_config_options *options,</div><div class='ctx'> 		const enum dc_link_encoding_format link_encoding,</div><div class='add'>+		int min_slices_h,</div><div class='ctx'> 		struct dc_dsc_config *dsc_cfg)</div><div class='ctx'> {</div><div class='ctx'> 	struct dsc_enc_caps dsc_common_caps;</div><div class='del'>-	int max_slices_h;</div><div class='del'>-	int min_slices_h;</div><div class='del'>-	int num_slices_h;</div><div class='add'>+	int max_slices_h = 0;</div><div class='add'>+	int num_slices_h = 0;</div><div class='ctx'> 	int pic_width;</div><div class='ctx'> 	int slice_width;</div><div class='ctx'> 	int target_bpp;</div><div class='hunk'>@@ -883,7 +1067,7 @@ static bool setup_dsc_config(</div><div class='ctx'> </div><div class='ctx'> 	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));</div><div class='ctx'> </div><div class='del'>-	dc_dsc_get_policy_for_timing(timing, options-&gt;max_target_bpp_limit_override_x16, &amp;policy);</div><div class='add'>+	dc_dsc_get_policy_for_timing(timing, options-&gt;max_target_bpp_limit_override_x16, &amp;policy, link_encoding);</div><div class='ctx'> 	pic_width = timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right;</div><div class='ctx'> 	pic_height = timing-&gt;v_addressable + timing-&gt;v_border_top + timing-&gt;v_border_bottom;</div><div class='ctx'> </div><div class='hunk'>@@ -973,12 +1157,14 @@ static bool setup_dsc_config(</div><div class='ctx'> 	if (!is_dsc_possible)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='del'>-	min_slices_h = pic_width / dsc_common_caps.max_slice_width;</div><div class='del'>-	if (pic_width % dsc_common_caps.max_slice_width)</div><div class='del'>-		min_slices_h++;</div><div class='add'>+	/* increase miniumum slice count to meet sink slice width limitations */</div><div class='add'>+	min_slices_h = dc_fixpt_ceil(dc_fixpt_max(</div><div class='add'>+			dc_fixpt_div_int(dc_fixpt_from_int(pic_width), dsc_common_caps.max_slice_width), // sink min</div><div class='add'>+			dc_fixpt_from_int(min_slices_h))); // source min</div><div class='ctx'> </div><div class='ctx'> 	min_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, min_slices_h);</div><div class='ctx'> </div><div class='add'>+	/* increase minimum slice count to meet sink throughput limitations */</div><div class='ctx'> 	while (min_slices_h &lt;= max_slices_h) {</div><div class='ctx'> 		int pix_clk_per_slice_khz = dsc_div_by_10_round_up(timing-&gt;pix_clk_100hz) / min_slices_h;</div><div class='ctx'> 		if (pix_clk_per_slice_khz &lt;= sink_per_slice_throughput_mps * 1000)</div><div class='hunk'>@@ -987,14 +1173,12 @@ static bool setup_dsc_config(</div><div class='ctx'> 		min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, min_slices_h);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	is_dsc_possible = (min_slices_h &lt;= max_slices_h);</div><div class='del'>-</div><div class='del'>-	if (pic_width % min_slices_h != 0)</div><div class='del'>-		min_slices_h = 0; // DSC TODO: Maybe try increasing the number of slices first?</div><div class='del'>-</div><div class='del'>-	if (min_slices_h == 0 &amp;&amp; max_slices_h == 0)</div><div class='del'>-		is_dsc_possible = false;</div><div class='add'>+	/* increase minimum slice count to meet divisibility requirements */</div><div class='add'>+	while (pic_width % min_slices_h != 0 &amp;&amp; min_slices_h &lt;= max_slices_h) {</div><div class='add'>+		min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, min_slices_h);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	is_dsc_possible = (min_slices_h &lt;= max_slices_h) &amp;&amp; max_slices_h != 0;</div><div class='ctx'> 	if (!is_dsc_possible)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='hunk'>@@ -1019,14 +1203,30 @@ static bool setup_dsc_config(</div><div class='ctx'> 		else</div><div class='ctx'> 			is_dsc_possible = false;</div><div class='ctx'> 	}</div><div class='del'>-	// When we force 2:1 ODM, we can't have 1 slice to divide amongst 2 separate DSC instances</div><div class='del'>-	// need to enforce at minimum 2 horizontal slices</div><div class='del'>-	if (options-&gt;dsc_force_odm_hslice_override) {</div><div class='del'>-		num_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, 2);</div><div class='del'>-		if (num_slices_h == 0)</div><div class='del'>-			is_dsc_possible = false;</div><div class='add'>+	// When we force ODM, num dsc h slices must be divisible by num odm h slices</div><div class='add'>+	switch (options-&gt;dsc_force_odm_hslice_override) {</div><div class='add'>+	case 0:</div><div class='add'>+	case 1:</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		if (num_slices_h &lt; 2)</div><div class='add'>+			num_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, 2);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		if (dsc_common_caps.slice_caps.bits.NUM_SLICES_12)</div><div class='add'>+			num_slices_h = 12;</div><div class='add'>+		else</div><div class='add'>+			num_slices_h = 0;</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+		if (num_slices_h &lt; 4)</div><div class='add'>+			num_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, 4);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	if (num_slices_h == 0)</div><div class='add'>+		is_dsc_possible = false;</div><div class='ctx'> 	if (!is_dsc_possible)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='hunk'>@@ -1055,11 +1255,17 @@ static bool setup_dsc_config(</div><div class='ctx'> 	if (!is_dsc_possible)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='del'>-	dsc_cfg-&gt;num_slices_v = pic_height/slice_height;</div><div class='add'>+	if (slice_height &gt; 0) {</div><div class='add'>+		dsc_cfg-&gt;num_slices_v = pic_height / slice_height;</div><div class='add'>+	} else {</div><div class='add'>+		is_dsc_possible = false;</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (target_bandwidth_kbps &gt; 0) {</div><div class='ctx'> 		is_dsc_possible = decide_dsc_target_bpp_x16(</div><div class='ctx'> 				&amp;policy,</div><div class='add'>+				options,</div><div class='ctx'> 				&amp;dsc_common_caps,</div><div class='ctx'> 				target_bandwidth_kbps,</div><div class='ctx'> 				timing,</div><div class='hunk'>@@ -1071,14 +1277,11 @@ static bool setup_dsc_config(</div><div class='ctx'> 	if (!is_dsc_possible)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='del'>-	// Final decission: can we do DSC or not?</div><div class='del'>-	if (is_dsc_possible) {</div><div class='del'>-		// Fill out the rest of DSC settings</div><div class='del'>-		dsc_cfg-&gt;block_pred_enable = dsc_common_caps.is_block_pred_supported;</div><div class='del'>-		dsc_cfg-&gt;linebuf_depth = dsc_common_caps.lb_bit_depth;</div><div class='del'>-		dsc_cfg-&gt;version_minor = (dsc_common_caps.dsc_version &amp; 0xf0) &gt;&gt; 4;</div><div class='del'>-		dsc_cfg-&gt;is_dp = dsc_sink_caps-&gt;is_dp;</div><div class='del'>-	}</div><div class='add'>+	/* Fill out the rest of DSC settings */</div><div class='add'>+	dsc_cfg-&gt;block_pred_enable = dsc_common_caps.is_block_pred_supported;</div><div class='add'>+	dsc_cfg-&gt;linebuf_depth = dsc_common_caps.lb_bit_depth;</div><div class='add'>+	dsc_cfg-&gt;version_minor = (dsc_common_caps.dsc_version &amp; 0xf0) &gt;&gt; 4;</div><div class='add'>+	dsc_cfg-&gt;is_dp = dsc_sink_caps-&gt;is_dp;</div><div class='ctx'> </div><div class='ctx'> done:</div><div class='ctx'> 	if (!is_dsc_possible)</div><div class='hunk'>@@ -1098,12 +1301,19 @@ bool dc_dsc_compute_config(</div><div class='ctx'> {</div><div class='ctx'> 	bool is_dsc_possible = false;</div><div class='ctx'> 	struct dsc_enc_caps dsc_enc_caps;</div><div class='del'>-</div><div class='add'>+	unsigned int min_dsc_slice_count;</div><div class='ctx'> 	get_dsc_enc_caps(dsc, &amp;dsc_enc_caps, timing-&gt;pix_clk_100hz);</div><div class='add'>+</div><div class='add'>+	min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &amp;dsc_enc_caps, timing);</div><div class='add'>+</div><div class='ctx'> 	is_dsc_possible = setup_dsc_config(dsc_sink_caps,</div><div class='ctx'> 		&amp;dsc_enc_caps,</div><div class='ctx'> 		target_bandwidth_kbps,</div><div class='del'>-		timing, options, link_encoding, dsc_cfg);</div><div class='add'>+		timing,</div><div class='add'>+		options,</div><div class='add'>+		link_encoding,</div><div class='add'>+		min_dsc_slice_count,</div><div class='add'>+		dsc_cfg);</div><div class='ctx'> 	return is_dsc_possible;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1151,7 +1361,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps(</div><div class='ctx'> </div><div class='ctx'> void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,</div><div class='ctx'> 		uint32_t max_target_bpp_limit_override_x16,</div><div class='del'>-		struct dc_dsc_policy *policy)</div><div class='add'>+		struct dc_dsc_policy *policy,</div><div class='add'>+		const enum dc_link_encoding_format link_encoding)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t bpc = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1215,10 +1426,7 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,</div><div class='ctx'> 		policy-&gt;max_target_bpp = max_target_bpp_limit_override_x16 / 16;</div><div class='ctx'> </div><div class='ctx'> 	/* enable DSC when not needed, default false */</div><div class='del'>-	if (dsc_policy_enable_dsc_when_not_needed)</div><div class='del'>-		policy-&gt;enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed;</div><div class='del'>-	else</div><div class='del'>-		policy-&gt;enable_dsc_when_not_needed = false;</div><div class='add'>+	policy-&gt;enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit)</div><div class='hunk'>@@ -1247,4 +1455,5 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_</div><div class='ctx'> 	options-&gt;dsc_force_odm_hslice_override = dc-&gt;debug.force_odm_combine;</div><div class='ctx'> 	options-&gt;max_target_bpp_limit_override_x16 = 0;</div><div class='ctx'> 	options-&gt;slice_height_granularity = 1;</div><div class='add'>+	options-&gt;force_dsc_when_not_needed = false;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c<br/>index c9ae2d8f0096..242f1e6f0d8f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c</a></div><div class='hunk'>@@ -32,24 +32,17 @@</div><div class='ctx'> </div><div class='ctx'> static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);</div><div class='ctx'> </div><div class='del'>-/* Object I/F functions */</div><div class='del'>-static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);</div><div class='del'>-static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);</div><div class='del'>-static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='del'>-		struct dsc_optc_config *dsc_optc_cfg);</div><div class='del'>-static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);</div><div class='del'>-static void dsc2_disable(struct display_stream_compressor *dsc);</div><div class='del'>-static void dsc2_disconnect(struct display_stream_compressor *dsc);</div><div class='del'>-</div><div class='ctx'> static const struct dsc_funcs dcn20_dsc_funcs = {</div><div class='ctx'> 	.dsc_get_enc_caps = dsc2_get_enc_caps,</div><div class='ctx'> 	.dsc_read_state = dsc2_read_state,</div><div class='add'>+	.dsc_read_reg_state = dsc2_read_reg_state,</div><div class='ctx'> 	.dsc_validate_stream = dsc2_validate_stream,</div><div class='ctx'> 	.dsc_set_config = dsc2_set_config,</div><div class='ctx'> 	.dsc_get_packed_pps = dsc2_get_packed_pps,</div><div class='ctx'> 	.dsc_enable = dsc2_enable,</div><div class='ctx'> 	.dsc_disable = dsc2_disable,</div><div class='ctx'> 	.dsc_disconnect = dsc2_disconnect,</div><div class='add'>+	.dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Macro definitios for REG_SET macros*/</div><div class='hunk'>@@ -65,13 +58,6 @@ static const struct dsc_funcs dcn20_dsc_funcs = {</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dsc-&gt;ctx-&gt;logger</div><div class='ctx'> </div><div class='del'>-enum dsc_bits_per_comp {</div><div class='del'>-	DSC_BPC_8 = 8,</div><div class='del'>-	DSC_BPC_10 = 10,</div><div class='del'>-	DSC_BPC_12 = 12,</div><div class='del'>-	DSC_BPC_UNKNOWN</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* API functions (external or via structure-&gt;function_pointer) */</div><div class='ctx'> </div><div class='ctx'> void dsc2_construct(struct dcn20_dsc *dsc,</div><div class='hunk'>@@ -154,7 +140,7 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)</div><div class='ctx'> /* this function read dsc related register fields to be logged later in dcn10_log_hw_state</div><div class='ctx'>  * into a dcn_dsc_state struct.</div><div class='ctx'>  */</div><div class='del'>-static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)</div><div class='add'>+void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='ctx'> </div><div class='hunk'>@@ -170,8 +156,15 @@ static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_ds</div><div class='ctx'> 		DSCRM_DSC_OPP_PIPE_SOURCE, &amp;s-&gt;dsc_opp_source);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='ctx'> </div><div class='del'>-static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)</div><div class='add'>+	dccg_reg_state-&gt;dsc_top_control = REG_READ(DSC_TOP_CONTROL);</div><div class='add'>+	dccg_reg_state-&gt;dscc_interrupt_control_status = REG_READ(DSCC_INTERRUPT_CONTROL_STATUS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)</div><div class='ctx'> {</div><div class='ctx'> 	struct dsc_optc_config dsc_optc_cfg;</div><div class='ctx'> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='hunk'>@@ -194,7 +187,7 @@ void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_conf</div><div class='ctx'> 	DC_LOG_DSC("\tcolor_depth %d", config-&gt;color_depth);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='add'>+void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='ctx'> 		struct dsc_optc_config *dsc_optc_cfg)</div><div class='ctx'> {</div><div class='ctx'> 	bool is_config_ok;</div><div class='hunk'>@@ -231,7 +224,7 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)</div><div class='add'>+void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='ctx'> 	int dsc_clock_en;</div><div class='hunk'>@@ -256,20 +249,16 @@ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static void dsc2_disable(struct display_stream_compressor *dsc)</div><div class='add'>+void dsc2_disable(struct display_stream_compressor *dsc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='ctx'> 	int dsc_clock_en;</div><div class='del'>-	int dsc_fw_config;</div><div class='del'>-	int enabled_opp_pipe;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_DSC("disable DSC %d", dsc-&gt;inst);</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &amp;dsc_clock_en);</div><div class='del'>-	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &amp;dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &amp;enabled_opp_pipe);</div><div class='del'>-	if (!dsc_clock_en || !dsc_fw_config) {</div><div class='del'>-		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc-&gt;inst, enabled_opp_pipe);</div><div class='del'>-		ASSERT(0);</div><div class='add'>+	if (!dsc_clock_en) {</div><div class='add'>+		DC_LOG_DSC("DSC %d already disabled!", dsc-&gt;inst);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,</div><div class='hunk'>@@ -279,7 +268,14 @@ static void dsc2_disable(struct display_stream_compressor *dsc)</div><div class='ctx'> 		DSC_CLOCK_EN, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dsc2_disconnect(struct display_stream_compressor *dsc)</div><div class='add'>+void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dsc2_disconnect(struct display_stream_compressor *dsc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='ctx'> </div><div class='hunk'>@@ -418,9 +414,10 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values</div><div class='ctx'> 	dsc_reg_vals-&gt;alternate_ich_encoding_en = dsc_reg_vals-&gt;pps.dsc_version_minor == 1 ? 0 : 1;</div><div class='ctx'> 	dsc_reg_vals-&gt;ich_reset_at_eol = (dsc_cfg-&gt;is_odm || dsc_reg_vals-&gt;num_slices_h &gt; 1) ? 0xF : 0;</div><div class='ctx'> </div><div class='add'>+	// Need to find the ceiling value for the slice width</div><div class='add'>+	dsc_reg_vals-&gt;pps.slice_width = (dsc_cfg-&gt;pic_width + dsc_cfg-&gt;dsc_padding + dsc_cfg-&gt;dc_dsc_cfg.num_slices_h - 1) / dsc_cfg-&gt;dc_dsc_cfg.num_slices_h;</div><div class='ctx'> 	// TODO: in addition to validating slice height (pic height must be divisible by slice height),</div><div class='ctx'> 	// see what happens when the same condition doesn't apply for slice_width/pic_width.</div><div class='del'>-	dsc_reg_vals-&gt;pps.slice_width = dsc_cfg-&gt;pic_width / dsc_cfg-&gt;dc_dsc_cfg.num_slices_h;</div><div class='ctx'> 	dsc_reg_vals-&gt;pps.slice_height = dsc_cfg-&gt;pic_height / dsc_cfg-&gt;dc_dsc_cfg.num_slices_v;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(dsc_reg_vals-&gt;pps.slice_height * dsc_cfg-&gt;dc_dsc_cfg.num_slices_v == dsc_cfg-&gt;pic_height);</div><div class='hunk'>@@ -777,4 +774,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const</div><div class='ctx'> 		RANGE_BPG_OFFSET14, reg_vals-&gt;pps.rc_range_params[14].range_bpg_offset);</div><div class='ctx'> </div><div class='ctx'> }</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h<br/>index ba869387c3c5..2337c3a97235 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h</a></div><div class='hunk'>@@ -78,6 +78,7 @@</div><div class='ctx'> 	SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\</div><div class='ctx'> 	SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\</div><div class='ctx'> 	SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\</div><div class='add'>+	SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\</div><div class='ctx'> 	SRI(DSCCIF_CONFIG0, DSCCIF, id),\</div><div class='ctx'> 	SRI(DSCCIF_CONFIG1, DSCCIF, id),\</div><div class='ctx'> 	SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)</div><div class='hunk'>@@ -95,6 +96,7 @@</div><div class='ctx'> 	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \</div><div class='hunk'>@@ -247,6 +249,10 @@</div><div class='ctx'> 	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \</div><div class='ctx'> 	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \</div><div class='hunk'>@@ -421,6 +427,10 @@</div><div class='ctx'> 	type DSCC_UPDATE_PENDING_STATUS; \</div><div class='ctx'> 	type DSCC_UPDATE_TAKEN_STATUS; \</div><div class='ctx'> 	type DSCC_UPDATE_TAKEN_ACK; \</div><div class='add'>+	type DSCC_TEST_DEBUG_BUS0_ROTATE; \</div><div class='add'>+	type DSCC_TEST_DEBUG_BUS1_ROTATE; \</div><div class='add'>+	type DSCC_TEST_DEBUG_BUS2_ROTATE; \</div><div class='add'>+	type DSCC_TEST_DEBUG_BUS3_ROTATE; \</div><div class='ctx'> 	type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \</div><div class='ctx'> 	type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \</div><div class='ctx'> 	type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \</div><div class='hunk'>@@ -443,7 +453,16 @@</div><div class='ctx'> 	type DSCCIF_UPDATE_TAKEN_STATUS; \</div><div class='ctx'> 	type DSCCIF_UPDATE_TAKEN_ACK; \</div><div class='ctx'> 	type DSCRM_DSC_FORWARD_EN; \</div><div class='del'>-	type DSCRM_DSC_OPP_PIPE_SOURCE</div><div class='add'>+	type DSCRM_DSC_OPP_PIPE_SOURCE; \</div><div class='add'>+	type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \</div><div class='add'>+	type DSCRM_DSC_FORWARD_EN_STATUS</div><div class='add'>+</div><div class='add'>+enum dsc_bits_per_comp {</div><div class='add'>+	DSC_BPC_8 = 8,</div><div class='add'>+	DSC_BPC_10 = 10,</div><div class='add'>+	DSC_BPC_12 = 12,</div><div class='add'>+	DSC_BPC_UNKNOWN</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> struct dcn20_dsc_registers {</div><div class='ctx'> 	uint32_t DSC_TOP_CONTROL;</div><div class='hunk'>@@ -492,6 +511,7 @@ struct dcn20_dsc_registers {</div><div class='ctx'> 	uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;</div><div class='ctx'> 	uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;</div><div class='ctx'> 	uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;</div><div class='add'>+	uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;</div><div class='ctx'> 	uint32_t DSCCIF_CONFIG0;</div><div class='ctx'> 	uint32_t DSCCIF_CONFIG1;</div><div class='ctx'> 	uint32_t DSCRM_DSC_FORWARD_CONFIG;</div><div class='hunk'>@@ -585,5 +605,15 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,</div><div class='ctx'> 		const struct dsc_config *dsc_cfg,</div><div class='ctx'> 		uint8_t *dsc_packed_pps);</div><div class='ctx'> </div><div class='add'>+void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);</div><div class='add'>+void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);</div><div class='add'>+bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);</div><div class='add'>+void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='add'>+		struct dsc_optc_config *dsc_optc_cfg);</div><div class='add'>+void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);</div><div class='add'>+void dsc2_disable(struct display_stream_compressor *dsc);</div><div class='add'>+void dsc2_disconnect(struct display_stream_compressor *dsc);</div><div class='add'>+void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c<br/>index 71d2dff9986d..e712985f7abd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c</a></div><div class='hunk'>@@ -27,6 +27,22 @@</div><div class='ctx'> #include "dcn35_dsc.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> </div><div class='add'>+static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);</div><div class='add'>+static void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);</div><div class='add'>+</div><div class='add'>+static const struct dsc_funcs dcn35_dsc_funcs = {</div><div class='add'>+	.dsc_read_state = dsc2_read_state,</div><div class='add'>+	.dsc_read_reg_state = dsc2_read_reg_state,</div><div class='add'>+	.dsc_validate_stream = dsc2_validate_stream,</div><div class='add'>+	.dsc_set_config = dsc2_set_config,</div><div class='add'>+	.dsc_get_packed_pps = dsc2_get_packed_pps,</div><div class='add'>+	.dsc_enable = dsc35_enable,</div><div class='add'>+	.dsc_disable = dsc2_disable,</div><div class='add'>+	.dsc_disconnect = dsc2_disconnect,</div><div class='add'>+	.dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,</div><div class='add'>+	.dsc_get_single_enc_caps = dsc35_get_single_enc_caps,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Macro definitios for REG_SET macros*/</div><div class='ctx'> #define CTX \</div><div class='ctx'> 	dsc20-&gt;base.ctx</div><div class='hunk'>@@ -49,12 +65,78 @@ void dsc35_construct(struct dcn20_dsc *dsc,</div><div class='ctx'> 		const struct dcn35_dsc_shift *dsc_shift,</div><div class='ctx'> 		const struct dcn35_dsc_mask *dsc_mask)</div><div class='ctx'> {</div><div class='del'>-	dsc2_construct(dsc, ctx, inst, dsc_regs,</div><div class='del'>-		(const struct dcn20_dsc_shift *)(dsc_shift),</div><div class='del'>-		(const struct dcn20_dsc_mask *)(dsc_mask));</div><div class='add'>+	dsc-&gt;base.ctx = ctx;</div><div class='add'>+	dsc-&gt;base.inst = inst;</div><div class='add'>+	dsc-&gt;base.funcs = &amp;dcn35_dsc_funcs;</div><div class='add'>+</div><div class='add'>+	dsc-&gt;dsc_regs = dsc_regs;</div><div class='add'>+	dsc-&gt;dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift);</div><div class='add'>+	dsc-&gt;dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask);</div><div class='add'>+</div><div class='add'>+	dsc-&gt;max_image_width = 5184;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);</div><div class='add'>+	int dsc_clock_en;</div><div class='add'>+	int dsc_fw_config;</div><div class='add'>+	int enabled_opp_pipe;</div><div class='add'>+</div><div class='add'>+	DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc-&gt;inst, opp_pipe);</div><div class='add'>+</div><div class='add'>+	// TODO: After an idle exit, the HW default values for power control</div><div class='add'>+	// are changed intermittently due to unknown reasons. There are cases</div><div class='add'>+	// when dscc memory are still in shutdown state during enablement.</div><div class='add'>+	// Reset power control to hw default values.</div><div class='add'>+	REG_UPDATE_2(DSCC_MEM_POWER_CONTROL,</div><div class='add'>+		DSCC_MEM_PWR_FORCE, 0,</div><div class='add'>+		DSCC_MEM_PWR_DIS, 0);</div><div class='add'>+</div><div class='add'>+	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &amp;dsc_clock_en);</div><div class='add'>+	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &amp;dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &amp;enabled_opp_pipe);</div><div class='add'>+	if ((dsc_clock_en || dsc_fw_config) &amp;&amp; enabled_opp_pipe != opp_pipe) {</div><div class='add'>+		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc-&gt;inst, enabled_opp_pipe);</div><div class='add'>+		ASSERT(0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DSC_TOP_CONTROL,</div><div class='add'>+		DSC_CLOCK_EN, 1);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,</div><div class='add'>+		DSCRM_DSC_FORWARD_EN, 1,</div><div class='add'>+		DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)</div><div class='add'>+{</div><div class='add'>+	dsc_enc_caps-&gt;dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_1 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_2 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_3 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4 = 1;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;lb_bit_depth = 13;</div><div class='add'>+	dsc_enc_caps-&gt;is_block_pred_supported = true;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.RGB = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_444 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_SIMPLE_422 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_NATIVE_422 = 0;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_NATIVE_420 = 1;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.bits.COLOR_DEPTH_8_BPC = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.bits.COLOR_DEPTH_10_BPC = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.bits.COLOR_DEPTH_12_BPC = 1;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;max_total_throughput_mps = max_dscclk_khz * 3 / 1000;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */</div><div class='add'>+	dsc_enc_caps-&gt;bpp_increment_div = 16; /* 1/16th of a bit */</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c<br/>new file mode 100644<br/>index 000000000000..c1bdbb38c690<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c</a></div><div class='hunk'>@@ -0,0 +1,394 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include &lt;drm/display/drm_dsc_helper.h&gt;</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dcn401_dsc.h"</div><div class='add'>+#include "dsc/dscc_types.h"</div><div class='add'>+#include "dsc/rc_calc.h"</div><div class='add'>+</div><div class='add'>+static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);</div><div class='add'>+</div><div class='add'>+/* Object I/F functions */</div><div class='add'>+//static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);</div><div class='add'>+//static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);</div><div class='add'>+static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);</div><div class='add'>+</div><div class='add'>+static const struct dsc_funcs dcn401_dsc_funcs = {</div><div class='add'>+	.dsc_read_state = dsc401_read_state,</div><div class='add'>+	.dsc_validate_stream = dsc401_validate_stream,</div><div class='add'>+	.dsc_set_config = dsc401_set_config,</div><div class='add'>+	.dsc_get_packed_pps = dsc2_get_packed_pps,</div><div class='add'>+	.dsc_enable = dsc401_enable,</div><div class='add'>+	.dsc_disable = dsc401_disable,</div><div class='add'>+	.dsc_disconnect = dsc401_disconnect,</div><div class='add'>+	.dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear,</div><div class='add'>+	.dsc_get_single_enc_caps = dsc401_get_single_enc_caps,</div><div class='add'>+	.dsc_read_reg_state = dsc2_read_reg_state</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Macro definitios for REG_SET macros*/</div><div class='add'>+#define CTX \</div><div class='add'>+	dsc401-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	dsc401-&gt;dsc_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	dsc401-&gt;dsc_shift-&gt;field_name, dsc401-&gt;dsc_mask-&gt;field_name</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dsc-&gt;ctx-&gt;logger</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* API functions (external or via structure-&gt;function_pointer) */</div><div class='add'>+</div><div class='add'>+void dsc401_construct(struct dcn401_dsc *dsc,</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		int inst,</div><div class='add'>+		const struct dcn401_dsc_registers *dsc_regs,</div><div class='add'>+		const struct dcn401_dsc_shift *dsc_shift,</div><div class='add'>+		const struct dcn401_dsc_mask *dsc_mask)</div><div class='add'>+{</div><div class='add'>+	dsc-&gt;base.ctx = ctx;</div><div class='add'>+	dsc-&gt;base.inst = inst;</div><div class='add'>+	dsc-&gt;base.funcs = &amp;dcn401_dsc_funcs;</div><div class='add'>+</div><div class='add'>+	dsc-&gt;dsc_regs = dsc_regs;</div><div class='add'>+	dsc-&gt;dsc_shift = dsc_shift;</div><div class='add'>+	dsc-&gt;dsc_mask = dsc_mask;</div><div class='add'>+</div><div class='add'>+	dsc-&gt;max_image_width = 5184;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)</div><div class='add'>+{</div><div class='add'>+	dsc_enc_caps-&gt;dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_1 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_2 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_3 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;slice_caps.bits.NUM_SLICES_4 = 1;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;lb_bit_depth = 13;</div><div class='add'>+	dsc_enc_caps-&gt;is_block_pred_supported = true;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.RGB = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_444 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_SIMPLE_422 = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_NATIVE_422 = 0;</div><div class='add'>+	dsc_enc_caps-&gt;color_formats.bits.YCBCR_NATIVE_420 = 1;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.bits.COLOR_DEPTH_8_BPC = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.bits.COLOR_DEPTH_10_BPC = 1;</div><div class='add'>+	dsc_enc_caps-&gt;color_depth.bits.COLOR_DEPTH_12_BPC = 1;</div><div class='add'>+	dsc_enc_caps-&gt;max_total_throughput_mps = max_dscclk_khz * 3 / 1000;</div><div class='add'>+</div><div class='add'>+	dsc_enc_caps-&gt;max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */</div><div class='add'>+	dsc_enc_caps-&gt;bpp_increment_div = 16; /* 1/16th of a bit */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* this function read dsc related register fields to be logged later in dcn10_log_hw_state</div><div class='add'>+ * into a dcn_dsc_state struct.</div><div class='add'>+ */</div><div class='add'>+void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &amp;s-&gt;dsc_clock_en);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &amp;s-&gt;dsc_slice_width);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &amp;s-&gt;dsc_bits_per_pixel);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &amp;s-&gt;dsc_slice_height);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &amp;s-&gt;dsc_chunk_size);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &amp;s-&gt;dsc_pic_width);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &amp;s-&gt;dsc_pic_height);</div><div class='add'>+	REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &amp;s-&gt;dsc_slice_bpg_offset);</div><div class='add'>+	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &amp;s-&gt;dsc_fw_en,</div><div class='add'>+		DSCRM_DSC_OPP_PIPE_SOURCE, &amp;s-&gt;dsc_opp_source);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)</div><div class='add'>+{</div><div class='add'>+	struct dsc_optc_config dsc_optc_cfg;</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	if (dsc_cfg-&gt;pic_width &gt; dsc401-&gt;max_image_width)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return dsc_prepare_config(dsc_cfg, &amp;dsc401-&gt;reg_vals, &amp;dsc_optc_cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='add'>+		struct dsc_optc_config *dsc_optc_cfg)</div><div class='add'>+{</div><div class='add'>+	bool is_config_ok;</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc-&gt;inst);</div><div class='add'>+	dsc_config_log(dsc, dsc_cfg);</div><div class='add'>+	is_config_ok = dsc_prepare_config(dsc_cfg, &amp;dsc401-&gt;reg_vals, dsc_optc_cfg);</div><div class='add'>+	ASSERT(is_config_ok);</div><div class='add'>+	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");</div><div class='add'>+	dsc_log_pps(dsc, &amp;dsc401-&gt;reg_vals.pps);</div><div class='add'>+	dsc_write_to_registers(dsc, &amp;dsc401-&gt;reg_vals);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+	int dsc_clock_en;</div><div class='add'>+	int dsc_fw_config;</div><div class='add'>+	int enabled_opp_pipe;</div><div class='add'>+</div><div class='add'>+	DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc-&gt;inst, opp_pipe);</div><div class='add'>+</div><div class='add'>+	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &amp;dsc_clock_en);</div><div class='add'>+	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &amp;dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &amp;enabled_opp_pipe);</div><div class='add'>+	if ((dsc_clock_en || dsc_fw_config) &amp;&amp; enabled_opp_pipe != opp_pipe) {</div><div class='add'>+		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc-&gt;inst, enabled_opp_pipe);</div><div class='add'>+		ASSERT(0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DSC_TOP_CONTROL,</div><div class='add'>+		DSC_CLOCK_EN, 1);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,</div><div class='add'>+		DSCRM_DSC_FORWARD_EN, 1,</div><div class='add'>+		DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dsc401_disable(struct display_stream_compressor *dsc)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+	int dsc_clock_en;</div><div class='add'>+</div><div class='add'>+	DC_LOG_DSC("disable DSC %d", dsc-&gt;inst);</div><div class='add'>+</div><div class='add'>+	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &amp;dsc_clock_en);</div><div class='add'>+	if (!dsc_clock_en) {</div><div class='add'>+		DC_LOG_DSC("DSC %d already disabled!", dsc-&gt;inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,</div><div class='add'>+		DSCRM_DSC_FORWARD_EN, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DSC_TOP_CONTROL,</div><div class='add'>+		DSC_CLOCK_EN, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dsc401_disconnect(struct display_stream_compressor *dsc)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DSC("disconnect DSC %d", dsc-&gt;inst);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,</div><div class='add'>+		DSCRM_DSC_FORWARD_EN, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)</div><div class='add'>+{</div><div class='add'>+	uint32_t temp_int;</div><div class='add'>+	struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);</div><div class='add'>+</div><div class='add'>+	REG_SET(DSC_DEBUG_CONTROL, 0,</div><div class='add'>+		DSC_DBG_EN, reg_vals-&gt;dsc_dbg_en);</div><div class='add'>+</div><div class='add'>+	// dsccif registers</div><div class='add'>+	REG_SET_2(DSCCIF_CONFIG0, 0,</div><div class='add'>+		//INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals-&gt;underflow_recovery_en,</div><div class='add'>+		//INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals-&gt;underflow_occurred_int_en,</div><div class='add'>+		//INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals-&gt;underflow_occurred_status,</div><div class='add'>+		INPUT_PIXEL_FORMAT, reg_vals-&gt;pixel_format,</div><div class='add'>+		DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals-&gt;pps.bits_per_component);</div><div class='add'>+</div><div class='add'>+	/* REG_SET_2(DSCCIF_CONFIG1, 0,</div><div class='add'>+		PIC_WIDTH, reg_vals-&gt;pps.pic_width,</div><div class='add'>+		PIC_HEIGHT, reg_vals-&gt;pps.pic_height);</div><div class='add'>+	*/</div><div class='add'>+	// dscc registers</div><div class='add'>+	if (dsc401-&gt;dsc_mask-&gt;ICH_RESET_AT_END_OF_LINE == 0) {</div><div class='add'>+		REG_SET_3(DSCC_CONFIG0, 0,</div><div class='add'>+			  NUMBER_OF_SLICES_PER_LINE, reg_vals-&gt;num_slices_h - 1,</div><div class='add'>+			  ALTERNATE_ICH_ENCODING_EN, reg_vals-&gt;alternate_ich_encoding_en,</div><div class='add'>+			  NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals-&gt;num_slices_v - 1);</div><div class='add'>+	} else {</div><div class='add'>+		REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,</div><div class='add'>+			  reg_vals-&gt;ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,</div><div class='add'>+			  reg_vals-&gt;num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,</div><div class='add'>+			  reg_vals-&gt;alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,</div><div class='add'>+			  reg_vals-&gt;num_slices_v - 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_SET(DSCC_CONFIG1, 0,</div><div class='add'>+			DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals-&gt;rc_buffer_model_size);</div><div class='add'>+	/*REG_SET_2(DSCC_CONFIG1, 0,</div><div class='add'>+		DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals-&gt;rc_buffer_model_size,</div><div class='add'>+		DSCC_DISABLE_ICH, reg_vals-&gt;disable_ich);*/</div><div class='add'>+</div><div class='add'>+	REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0,</div><div class='add'>+		DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals-&gt;rc_buffer_model_overflow_int_en[0],</div><div class='add'>+		DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals-&gt;rc_buffer_model_overflow_int_en[1],</div><div class='add'>+		DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals-&gt;rc_buffer_model_overflow_int_en[2],</div><div class='add'>+		DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals-&gt;rc_buffer_model_overflow_int_en[3]);</div><div class='add'>+</div><div class='add'>+	REG_SET_3(DSCC_PPS_CONFIG0, 0,</div><div class='add'>+		DSC_VERSION_MINOR, reg_vals-&gt;pps.dsc_version_minor,</div><div class='add'>+		LINEBUF_DEPTH, reg_vals-&gt;pps.line_buf_depth,</div><div class='add'>+		DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals-&gt;pps.bits_per_component);</div><div class='add'>+</div><div class='add'>+	if (reg_vals-&gt;pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals-&gt;pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)</div><div class='add'>+		temp_int = reg_vals-&gt;bpp_x32;</div><div class='add'>+	else</div><div class='add'>+		temp_int = reg_vals-&gt;bpp_x32 &gt;&gt; 1;</div><div class='add'>+</div><div class='add'>+	REG_SET_7(DSCC_PPS_CONFIG1, 0,</div><div class='add'>+		BITS_PER_PIXEL, temp_int,</div><div class='add'>+		SIMPLE_422, reg_vals-&gt;pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,</div><div class='add'>+		CONVERT_RGB, reg_vals-&gt;pixel_format == DSC_PIXFMT_RGB,</div><div class='add'>+		BLOCK_PRED_ENABLE, reg_vals-&gt;pps.block_pred_enable,</div><div class='add'>+		NATIVE_422, reg_vals-&gt;pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,</div><div class='add'>+		NATIVE_420, reg_vals-&gt;pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,</div><div class='add'>+		CHUNK_SIZE, reg_vals-&gt;pps.slice_chunk_size);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DSCC_PPS_CONFIG2, 0,</div><div class='add'>+		PIC_WIDTH, reg_vals-&gt;pps.pic_width,</div><div class='add'>+		PIC_HEIGHT, reg_vals-&gt;pps.pic_height);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DSCC_PPS_CONFIG3, 0,</div><div class='add'>+		SLICE_WIDTH, reg_vals-&gt;pps.slice_width,</div><div class='add'>+		SLICE_HEIGHT, reg_vals-&gt;pps.slice_height);</div><div class='add'>+</div><div class='add'>+	REG_SET(DSCC_PPS_CONFIG4, 0,</div><div class='add'>+		INITIAL_XMIT_DELAY, reg_vals-&gt;pps.initial_xmit_delay);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DSCC_PPS_CONFIG5, 0,</div><div class='add'>+		INITIAL_SCALE_VALUE, reg_vals-&gt;pps.initial_scale_value,</div><div class='add'>+		SCALE_INCREMENT_INTERVAL, reg_vals-&gt;pps.scale_increment_interval);</div><div class='add'>+</div><div class='add'>+	REG_SET_3(DSCC_PPS_CONFIG6, 0,</div><div class='add'>+		SCALE_DECREMENT_INTERVAL, reg_vals-&gt;pps.scale_decrement_interval,</div><div class='add'>+		FIRST_LINE_BPG_OFFSET, reg_vals-&gt;pps.first_line_bpg_offset,</div><div class='add'>+		SECOND_LINE_BPG_OFFSET, reg_vals-&gt;pps.second_line_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DSCC_PPS_CONFIG7, 0,</div><div class='add'>+		NFL_BPG_OFFSET, reg_vals-&gt;pps.nfl_bpg_offset,</div><div class='add'>+		SLICE_BPG_OFFSET, reg_vals-&gt;pps.slice_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DSCC_PPS_CONFIG8, 0,</div><div class='add'>+		NSL_BPG_OFFSET, reg_vals-&gt;pps.nsl_bpg_offset,</div><div class='add'>+		SECOND_LINE_OFFSET_ADJ, reg_vals-&gt;pps.second_line_offset_adj);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DSCC_PPS_CONFIG9, 0,</div><div class='add'>+		INITIAL_OFFSET, reg_vals-&gt;pps.initial_offset,</div><div class='add'>+		FINAL_OFFSET, reg_vals-&gt;pps.final_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_3(DSCC_PPS_CONFIG10, 0,</div><div class='add'>+		FLATNESS_MIN_QP, reg_vals-&gt;pps.flatness_min_qp,</div><div class='add'>+		FLATNESS_MAX_QP, reg_vals-&gt;pps.flatness_max_qp,</div><div class='add'>+		RC_MODEL_SIZE, reg_vals-&gt;pps.rc_model_size);</div><div class='add'>+</div><div class='add'>+	REG_SET_5(DSCC_PPS_CONFIG11, 0,</div><div class='add'>+		RC_EDGE_FACTOR, reg_vals-&gt;pps.rc_edge_factor,</div><div class='add'>+		RC_QUANT_INCR_LIMIT0, reg_vals-&gt;pps.rc_quant_incr_limit0,</div><div class='add'>+		RC_QUANT_INCR_LIMIT1, reg_vals-&gt;pps.rc_quant_incr_limit1,</div><div class='add'>+		RC_TGT_OFFSET_LO, reg_vals-&gt;pps.rc_tgt_offset_low,</div><div class='add'>+		RC_TGT_OFFSET_HI, reg_vals-&gt;pps.rc_tgt_offset_high);</div><div class='add'>+</div><div class='add'>+	REG_SET_4(DSCC_PPS_CONFIG12, 0,</div><div class='add'>+		RC_BUF_THRESH0, reg_vals-&gt;pps.rc_buf_thresh[0],</div><div class='add'>+		RC_BUF_THRESH1, reg_vals-&gt;pps.rc_buf_thresh[1],</div><div class='add'>+		RC_BUF_THRESH2, reg_vals-&gt;pps.rc_buf_thresh[2],</div><div class='add'>+		RC_BUF_THRESH3, reg_vals-&gt;pps.rc_buf_thresh[3]);</div><div class='add'>+</div><div class='add'>+	REG_SET_4(DSCC_PPS_CONFIG13, 0,</div><div class='add'>+		RC_BUF_THRESH4, reg_vals-&gt;pps.rc_buf_thresh[4],</div><div class='add'>+		RC_BUF_THRESH5, reg_vals-&gt;pps.rc_buf_thresh[5],</div><div class='add'>+		RC_BUF_THRESH6, reg_vals-&gt;pps.rc_buf_thresh[6],</div><div class='add'>+		RC_BUF_THRESH7, reg_vals-&gt;pps.rc_buf_thresh[7]);</div><div class='add'>+</div><div class='add'>+	REG_SET_4(DSCC_PPS_CONFIG14, 0,</div><div class='add'>+		RC_BUF_THRESH8, reg_vals-&gt;pps.rc_buf_thresh[8],</div><div class='add'>+		RC_BUF_THRESH9, reg_vals-&gt;pps.rc_buf_thresh[9],</div><div class='add'>+		RC_BUF_THRESH10, reg_vals-&gt;pps.rc_buf_thresh[10],</div><div class='add'>+		RC_BUF_THRESH11, reg_vals-&gt;pps.rc_buf_thresh[11]);</div><div class='add'>+</div><div class='add'>+	REG_SET_5(DSCC_PPS_CONFIG15, 0,</div><div class='add'>+		RC_BUF_THRESH12, reg_vals-&gt;pps.rc_buf_thresh[12],</div><div class='add'>+		RC_BUF_THRESH13, reg_vals-&gt;pps.rc_buf_thresh[13],</div><div class='add'>+		RANGE_MIN_QP0, reg_vals-&gt;pps.rc_range_params[0].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP0, reg_vals-&gt;pps.rc_range_params[0].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET0, reg_vals-&gt;pps.rc_range_params[0].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG16, 0,</div><div class='add'>+		RANGE_MIN_QP1, reg_vals-&gt;pps.rc_range_params[1].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP1, reg_vals-&gt;pps.rc_range_params[1].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET1, reg_vals-&gt;pps.rc_range_params[1].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP2, reg_vals-&gt;pps.rc_range_params[2].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP2, reg_vals-&gt;pps.rc_range_params[2].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET2, reg_vals-&gt;pps.rc_range_params[2].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG17, 0,</div><div class='add'>+		RANGE_MIN_QP3, reg_vals-&gt;pps.rc_range_params[3].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP3, reg_vals-&gt;pps.rc_range_params[3].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET3, reg_vals-&gt;pps.rc_range_params[3].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP4, reg_vals-&gt;pps.rc_range_params[4].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP4, reg_vals-&gt;pps.rc_range_params[4].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET4, reg_vals-&gt;pps.rc_range_params[4].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG18, 0,</div><div class='add'>+		RANGE_MIN_QP5, reg_vals-&gt;pps.rc_range_params[5].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP5, reg_vals-&gt;pps.rc_range_params[5].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET5, reg_vals-&gt;pps.rc_range_params[5].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP6, reg_vals-&gt;pps.rc_range_params[6].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP6, reg_vals-&gt;pps.rc_range_params[6].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET6, reg_vals-&gt;pps.rc_range_params[6].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG19, 0,</div><div class='add'>+		RANGE_MIN_QP7, reg_vals-&gt;pps.rc_range_params[7].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP7, reg_vals-&gt;pps.rc_range_params[7].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET7, reg_vals-&gt;pps.rc_range_params[7].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP8, reg_vals-&gt;pps.rc_range_params[8].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP8, reg_vals-&gt;pps.rc_range_params[8].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET8, reg_vals-&gt;pps.rc_range_params[8].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG20, 0,</div><div class='add'>+		RANGE_MIN_QP9, reg_vals-&gt;pps.rc_range_params[9].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP9, reg_vals-&gt;pps.rc_range_params[9].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET9, reg_vals-&gt;pps.rc_range_params[9].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP10, reg_vals-&gt;pps.rc_range_params[10].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP10, reg_vals-&gt;pps.rc_range_params[10].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET10, reg_vals-&gt;pps.rc_range_params[10].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG21, 0,</div><div class='add'>+		RANGE_MIN_QP11, reg_vals-&gt;pps.rc_range_params[11].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP11, reg_vals-&gt;pps.rc_range_params[11].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET11, reg_vals-&gt;pps.rc_range_params[11].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP12, reg_vals-&gt;pps.rc_range_params[12].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP12, reg_vals-&gt;pps.rc_range_params[12].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET12, reg_vals-&gt;pps.rc_range_params[12].range_bpg_offset);</div><div class='add'>+</div><div class='add'>+	REG_SET_6(DSCC_PPS_CONFIG22, 0,</div><div class='add'>+		RANGE_MIN_QP13, reg_vals-&gt;pps.rc_range_params[13].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP13, reg_vals-&gt;pps.rc_range_params[13].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET13, reg_vals-&gt;pps.rc_range_params[13].range_bpg_offset,</div><div class='add'>+		RANGE_MIN_QP14, reg_vals-&gt;pps.rc_range_params[14].range_min_qp,</div><div class='add'>+		RANGE_MAX_QP14, reg_vals-&gt;pps.rc_range_params[14].range_max_qp,</div><div class='add'>+		RANGE_BPG_OFFSET14, reg_vals-&gt;pps.rc_range_params[14].range_bpg_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h<br/>new file mode 100644<br/>index 000000000000..7acd57eb4f42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h</a></div><div class='hunk'>@@ -0,0 +1,346 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DCN401_DSC_H__</div><div class='add'>+#define __DCN401_DSC_H__</div><div class='add'>+</div><div class='add'>+#include "dsc.h"</div><div class='add'>+#include "dsc/dscc_types.h"</div><div class='add'>+#include "dcn20/dcn20_dsc.h"</div><div class='add'>+#include &lt;drm/display/drm_dsc.h&gt;</div><div class='add'>+</div><div class='add'>+#define TO_DCN401_DSC(dsc)\</div><div class='add'>+	container_of(dsc, struct dcn401_dsc, base)</div><div class='add'>+</div><div class='add'>+#define DSC_REG_LIST_SH_MASK_DCN401(mask_sh)\</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, mask_sh), \</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \</div><div class='add'>+	DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \</div><div class='add'>+	/*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_END_OF_FRAME_NOT_REACHED_CLEAR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \</div><div class='add'>+	DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_FORCE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_DIS, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_STATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_FORCE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_DIS, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_STATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \</div><div class='add'>+	DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \</div><div class='add'>+	DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \</div><div class='add'>+	DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \</div><div class='add'>+	DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \</div><div class='add'>+	DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh)</div><div class='add'>+</div><div class='add'>+struct dcn401_dsc_registers {</div><div class='add'>+	uint32_t DSC_TOP_CONTROL;</div><div class='add'>+	uint32_t DSC_DEBUG_CONTROL;</div><div class='add'>+	uint32_t DSCC_CONFIG0;</div><div class='add'>+	uint32_t DSCC_CONFIG1;</div><div class='add'>+	uint32_t DSCC_STATUS;</div><div class='add'>+	uint32_t DSCC_INTERRUPT_CONTROL0;</div><div class='add'>+	uint32_t DSCC_INTERRUPT_CONTROL1;</div><div class='add'>+	uint32_t DSCC_INTERRUPT_STATUS0;</div><div class='add'>+	uint32_t DSCC_INTERRUPT_STATUS1;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG0;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG1;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG2;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG3;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG4;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG5;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG6;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG7;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG8;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG9;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG10;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG11;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG12;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG13;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG14;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG15;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG16;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG17;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG18;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG19;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG20;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG21;</div><div class='add'>+	uint32_t DSCC_PPS_CONFIG22;</div><div class='add'>+	uint32_t DSCC_MEM_POWER_CONTROL0;</div><div class='add'>+	uint32_t DSCC_MEM_POWER_CONTROL1;</div><div class='add'>+	uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;</div><div class='add'>+	uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;</div><div class='add'>+	uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;</div><div class='add'>+	uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;</div><div class='add'>+	uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;</div><div class='add'>+	uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;</div><div class='add'>+	uint32_t DSCC_MAX_ABS_ERROR0;</div><div class='add'>+	uint32_t DSCC_MAX_ABS_ERROR1;</div><div class='add'>+	uint32_t DSCC_TEST_DEBUG_BUS_ROTATE;</div><div class='add'>+	uint32_t DSCCIF_CONFIG0;</div><div class='add'>+	uint32_t DSCRM_DSC_FORWARD_CONFIG;</div><div class='add'>+	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0;</div><div class='add'>+	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1;</div><div class='add'>+	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2;</div><div class='add'>+	uint32_t DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3;</div><div class='add'>+	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0;</div><div class='add'>+	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1;</div><div class='add'>+	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2;</div><div class='add'>+	uint32_t DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DSC_FIELD_LIST_DCN401(type)\</div><div class='add'>+	DSC_FIELD_LIST_DCN20(type); \</div><div class='add'>+	type DSC_FGCG_REP_DIS; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3; \</div><div class='add'>+	type DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3; \</div><div class='add'>+	type DSCC_END_OF_FRAME_NOT_REACHED_CLEAR; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2; \</div><div class='add'>+	type DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3; \</div><div class='add'>+	type DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2; \</div><div class='add'>+	type DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3; \</div><div class='add'>+	type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0; \</div><div class='add'>+	type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1; \</div><div class='add'>+	type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2; \</div><div class='add'>+	type DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3</div><div class='add'>+</div><div class='add'>+struct dcn401_dsc_shift {</div><div class='add'>+	DSC_FIELD_LIST_DCN401(uint8_t);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_dsc_mask {</div><div class='add'>+	DSC_FIELD_LIST_DCN401(uint32_t);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_dsc {</div><div class='add'>+	struct display_stream_compressor base;</div><div class='add'>+	const struct dcn401_dsc_registers *dsc_regs;</div><div class='add'>+	const struct dcn401_dsc_shift *dsc_shift;</div><div class='add'>+	const struct dcn401_dsc_mask *dsc_mask;</div><div class='add'>+</div><div class='add'>+	struct dsc_reg_values reg_vals;</div><div class='add'>+</div><div class='add'>+	int max_image_width;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dsc401_construct(struct dcn401_dsc *dsc,</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		int inst,</div><div class='add'>+		const struct dcn401_dsc_registers *dsc_regs,</div><div class='add'>+		const struct dcn401_dsc_shift *dsc_shift,</div><div class='add'>+		const struct dcn401_dsc_mask *dsc_mask);</div><div class='add'>+</div><div class='add'>+void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable);</div><div class='add'>+</div><div class='add'>+void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);</div><div class='add'>+bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);</div><div class='add'>+void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='add'>+		struct dsc_optc_config *dsc_optc_cfg);</div><div class='add'>+void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);</div><div class='add'>+void dsc401_disable(struct display_stream_compressor *dsc);</div><div class='add'>+void dsc401_disconnect(struct display_stream_compressor *dsc);</div><div class='add'>+void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h<br/>index 4b27f29d0d80..81c83d5fe042 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dsc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/dsc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dsc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/dsc.h</a></div><div class='hunk'>@@ -41,6 +41,7 @@ struct dsc_config {</div><div class='ctx'> 	enum dc_color_depth color_depth;  /* Bits per component */</div><div class='ctx'> 	bool is_odm;</div><div class='ctx'> 	struct dc_dsc_config dc_dsc_cfg;</div><div class='add'>+	uint32_t dsc_padding;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -65,6 +66,10 @@ struct dcn_dsc_state {</div><div class='ctx'> 	uint32_t dsc_opp_source;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn_dsc_reg_state {</div><div class='add'>+	uint32_t dsc_top_control;</div><div class='add'>+	uint32_t dscc_interrupt_control_status;</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> /* DSC encoder capabilities</div><div class='ctx'>  * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.</div><div class='hunk'>@@ -99,6 +104,7 @@ struct dsc_enc_caps {</div><div class='ctx'> struct dsc_funcs {</div><div class='ctx'> 	void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);</div><div class='ctx'> 	void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);</div><div class='add'>+	void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);</div><div class='ctx'> 	bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);</div><div class='ctx'> 	void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,</div><div class='ctx'> 			struct dsc_optc_config *dsc_optc_cfg);</div><div class='hunk'>@@ -107,6 +113,8 @@ struct dsc_funcs {</div><div class='ctx'> 	void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);</div><div class='ctx'> 	void (*dsc_disable)(struct display_stream_compressor *dsc);</div><div class='ctx'> 	void (*dsc_disconnect)(struct display_stream_compressor *dsc);</div><div class='add'>+	void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc);</div><div class='add'>+	void (*dsc_get_single_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c<br/>index 36d6c1646a51..59864130cf83 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c</a></div><div class='hunk'>@@ -101,7 +101,6 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,</div><div class='ctx'> {</div><div class='ctx'> 	int              ret;</div><div class='ctx'> 	struct drm_dsc_config   dsc_cfg;</div><div class='del'>-	unsigned long long tmp;</div><div class='ctx'> </div><div class='ctx'> 	dsc_params-&gt;pps = *pps;</div><div class='ctx'> 	dsc_params-&gt;pps.initial_scale_value = 8 * rc-&gt;rc_model_size / (rc-&gt;rc_model_size - rc-&gt;initial_fullness_offset);</div><div class='hunk'>@@ -112,9 +111,9 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,</div><div class='ctx'> 	dsc_cfg.mux_word_size = dsc_params-&gt;pps.bits_per_component &lt;= 10 ? 48 : 64;</div><div class='ctx'> </div><div class='ctx'> 	ret = drm_dsc_compute_rc_parameters(&amp;dsc_cfg);</div><div class='del'>-	tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1);</div><div class='del'>-	do_div(tmp, (uint32_t)dsc_cfg.slice_width);  //ROUND-UP</div><div class='del'>-	dsc_params-&gt;bytes_per_pixel = (uint32_t)tmp;</div><div class='add'>+	dsc_params-&gt;bytes_per_pixel =</div><div class='add'>+			(uint32_t)(div_u64(((uint64_t)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1)),</div><div class='add'>+							(uint32_t)dsc_cfg.slice_width));  /* Round-up */</div><div class='ctx'> </div><div class='ctx'> 	copy_pps_fields(&amp;dsc_params-&gt;pps, &amp;dsc_cfg);</div><div class='ctx'> 	dsc_params-&gt;rc_buffer_model_size = dsc_cfg.rc_bits;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dwb/Makefile b/drivers/gpu/drm/amd/display/dc/dwb/Makefile<br/>new file mode 100644<br/>index 000000000000..3952ba4cd508<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/Makefile</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN30</div><div class='add'>+###############################################################################</div><div class='add'>+DWB_DCN30 = dcn30_dwb.o dcn30_dwb_cm.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DWB_DCN30 = $(addprefix $(AMDDALPATH)/dc/dwb/dcn30/,$(DWB_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DWB_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN35</div><div class='add'>+###############################################################################</div><div class='add'>+DWB_DCN35 = dcn35_dwb.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DWB_DCN35 = $(addprefix $(AMDDALPATH)/dc/dwb/dcn35/,$(DWB_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DWB_DCN35)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.h b/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h<br/>index bd98b327a6c7..b86347c9b038 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h</a></div><div class='hunk'>@@ -63,10 +63,6 @@ bool cm3_helper_translate_curve_to_hw_format(</div><div class='ctx'> 	const struct dc_transfer_func *output_tf,</div><div class='ctx'> 	struct pwl_params *lut_params, bool fixpoint);</div><div class='ctx'> </div><div class='del'>-bool cm3_helper_translate_curve_to_degamma_hw_format(</div><div class='del'>-				const struct dc_transfer_func *output_tf,</div><div class='del'>-				struct pwl_params *lut_params);</div><div class='del'>-</div><div class='ctx'> bool cm3_helper_convert_to_custom_float(</div><div class='ctx'> 		struct pwl_result_data *rgb_resulted,</div><div class='ctx'> 		struct curve_points3 *corner_points,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c b/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c<br/>index 1b9d9495f76d..bc058f682438 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c</a></div><div class='hunk'>@@ -251,9 +251,7 @@ static const struct dwbc_funcs dcn30_dwbc_funcs = {</div><div class='ctx'> 	.set_fc_enable		= dwb3_set_fc_enable,</div><div class='ctx'> 	.set_stereo		= dwb3_set_stereo,</div><div class='ctx'> 	.set_new_content	= dwb3_set_new_content,</div><div class='del'>-	.dwb_program_output_csc	= NULL,</div><div class='ctx'> 	.dwb_ogam_set_input_transfer_func	= dwb3_ogam_set_input_transfer_func, //TODO: rename</div><div class='del'>-	.dwb_set_scaler		= NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,</div><div class='hunk'>@@ -272,16 +270,3 @@ void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,</div><div class='ctx'> 	dwbc30-&gt;dwbc_shift = dwbc_shift;</div><div class='ctx'> 	dwbc30-&gt;dwbc_mask = dwbc_mask;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay)</div><div class='del'>-{</div><div class='del'>-	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Set maximum delay of host read access to DWBSCL LUT or OGAM LUT if there are no</div><div class='del'>-	 * idle cycles in HW pipeline (in number of clock cycles times 4)</div><div class='del'>-	 */</div><div class='del'>-	REG_UPDATE(DWB_HOST_READ_CONTROL, DWB_HOST_READ_RATE_CONTROL, host_read_delay);</div><div class='del'>-</div><div class='del'>-	DC_LOG_DWB("%s dwb3_rate_control at inst = %d", __func__, dwbc-&gt;inst);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h b/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h<br/>index 332634b76aac..7f053f49ec6a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h</a></div><div class='hunk'>@@ -217,6 +217,7 @@</div><div class='ctx'> 	SF_DWB2(DWB_OGAM_LUT_DATA, DWBCP, 0, DWB_OGAM_LUT_DATA, mask_sh),\</div><div class='ctx'> 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\</div><div class='ctx'> 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_COLOR_SEL, mask_sh),\</div><div class='add'>+	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_DBG, mask_sh),\</div><div class='ctx'> 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_HOST_SEL, mask_sh),\</div><div class='ctx'> 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_CONFIG_MODE, mask_sh),\</div><div class='ctx'> 	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\</div><div class='hunk'>@@ -524,6 +525,7 @@</div><div class='ctx'> 	type DWB_OGAM_LUT_DATA;\</div><div class='ctx'> 	type DWB_OGAM_LUT_WRITE_COLOR_MASK;\</div><div class='ctx'> 	type DWB_OGAM_LUT_READ_COLOR_SEL;\</div><div class='add'>+	type DWB_OGAM_LUT_READ_DBG;\</div><div class='ctx'> 	type DWB_OGAM_LUT_HOST_SEL;\</div><div class='ctx'> 	type DWB_OGAM_LUT_CONFIG_MODE;\</div><div class='ctx'> 	type DWB_OGAM_LUT_STATUS;\</div><div class='hunk'>@@ -710,7 +712,7 @@</div><div class='ctx'> 	type DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET;\</div><div class='ctx'> 	type DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS;\</div><div class='ctx'> 	type DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET;\</div><div class='del'>-	type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS;</div><div class='add'>+	type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS</div><div class='ctx'> </div><div class='ctx'> struct dcn30_dwbc_registers {</div><div class='ctx'> 	/* DCN3AG */</div><div class='hunk'>@@ -733,6 +735,10 @@ struct dcn30_dwbc_registers {</div><div class='ctx'> 	uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT;</div><div class='ctx'> 	uint32_t DWB_HOST_READ_CONTROL;</div><div class='ctx'> 	uint32_t DWB_SOFT_RESET;</div><div class='add'>+	uint32_t DWB_DEBUG_CTRL;</div><div class='add'>+	uint32_t DWB_DEBUG;</div><div class='add'>+	uint32_t DWB_TEST_DEBUG_INDEX;</div><div class='add'>+	uint32_t DWB_TEST_DEBUG_DATA;</div><div class='ctx'> </div><div class='ctx'> 	/* DWBSCL */</div><div class='ctx'> 	uint32_t DWBSCL_COEF_RAM_TAP_SELECT;</div><div class='hunk'>@@ -747,6 +753,9 @@ struct dcn30_dwbc_registers {</div><div class='ctx'> 	uint32_t DWBSCL_DEST_SIZE;</div><div class='ctx'> 	uint32_t DWBSCL_OVERFLOW_STATUS;</div><div class='ctx'> 	uint32_t DWBSCL_OVERFLOW_COUNTER;</div><div class='add'>+	uint32_t DWBSCL_DEBUG;</div><div class='add'>+	uint32_t DWBSCL_TEST_DEBUG_INDEX;</div><div class='add'>+	uint32_t DWBSCL_TEST_DEBUG_DATA;</div><div class='ctx'> </div><div class='ctx'> 	/* DWBCP */</div><div class='ctx'> 	uint32_t DWB_HDR_MULT_COEF;</div><div class='hunk'>@@ -838,6 +847,9 @@ struct dcn30_dwbc_registers {</div><div class='ctx'> 	uint32_t DWB_OGAM_RAMB_REGION_28_29;</div><div class='ctx'> 	uint32_t DWB_OGAM_RAMB_REGION_30_31;</div><div class='ctx'> 	uint32_t DWB_OGAM_RAMB_REGION_32_33;</div><div class='add'>+	uint32_t DWBCP_DEBUG;</div><div class='add'>+	uint32_t DWBCP_TEST_DEBUG_INDEX;</div><div class='add'>+	uint32_t DWBCP_TEST_DEBUG_DATA;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Internal enums / structs */</div><div class='hunk'>@@ -902,7 +914,6 @@ bool dwb3_ogam_set_input_transfer_func(</div><div class='ctx'> 	struct dwbc *dwbc,</div><div class='ctx'> 	const struct dc_transfer_func *in_transfer_func_dwb_ogam);</div><div class='ctx'> </div><div class='del'>-void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c b/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c<br/>index 03a50c32fcfe..03a50c32fcfe 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c b/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c<br/>index b23a809999ed..d5e8294f5a16 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  * OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='del'>-</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "dcn35_dwb.h"</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h b/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h<br/>index 886e727ed080..886e727ed080 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile<br/>index bc47481a158e..b72e2a9f9a28 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/Makefile</a></div><div class='hunk'>@@ -122,3 +122,13 @@ GPIO_DCN32 = hw_translate_dcn32.o hw_factory_dcn32.o</div><div class='ctx'> AMD_DAL_GPIO_DCN32 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn32/,$(GPIO_DCN32))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN 4.01</div><div class='add'>+###############################################################################</div><div class='add'>+GPIO_DCN401 = hw_translate_dcn401.o hw_factory_dcn401.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_GPIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn401/,$(GPIO_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN401)</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c<br/>index d734e3a134d1..e3b11b3c1daa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c</a></div><div class='hunk'>@@ -95,10 +95,6 @@ static bool offset_to_id(</div><div class='ctx'> 			return true;</div><div class='ctx'> 		default:</div><div class='ctx'> 			ASSERT_CRITICAL(false);</div><div class='del'>-#ifdef PALLADIUM_SUPPORTED</div><div class='del'>-		*en = GPIO_DDC_LINE_DDC1;</div><div class='del'>-		return true;</div><div class='del'>-#endif</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> 	break;</div><div class='hunk'>@@ -183,12 +179,7 @@ static bool offset_to_id(</div><div class='ctx'>  */</div><div class='ctx'> 	/* UNEXPECTED */</div><div class='ctx'> 	default:</div><div class='del'>-/*	case REG(DC_GPIO_SYNCA_A): not exista */</div><div class='del'>-#ifdef PALLADIUM_SUPPORTED</div><div class='del'>-		*id = GPIO_ID_HPD;</div><div class='del'>-		*en = GPIO_DDC_LINE_DDC1;</div><div class='del'>-		return true;</div><div class='del'>-#endif</div><div class='add'>+/*	case REG(DC_GPIO_SYNCA_A): not exist */</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -308,10 +299,6 @@ static bool id_to_offset(</div><div class='ctx'> 		break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			ASSERT_CRITICAL(false);</div><div class='del'>-#ifdef PALLADIUM_SUPPORTED</div><div class='del'>-			info-&gt;mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;</div><div class='del'>-			result = true;</div><div class='del'>-#endif</div><div class='ctx'> 			result = false;</div><div class='ctx'> 		}</div><div class='ctx'> 	break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c<br/>new file mode 100644<br/>index 000000000000..928abca18a18<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c</a></div><div class='hunk'>@@ -0,0 +1,264 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "include/gpio_types.h"</div><div class='add'>+#include "../hw_factory.h"</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "../hw_gpio.h"</div><div class='add'>+#include "../hw_ddc.h"</div><div class='add'>+#include "../hw_hpd.h"</div><div class='add'>+#include "../hw_generic.h"</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_4_1_0_offset.h"</div><div class='add'>+#include "dcn/dcn_4_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "../hpd_regs.h"</div><div class='add'>+#include "hw_factory_dcn401.h"</div><div class='add'>+</div><div class='add'>+#define DCN_BASE__INST0_SEG2                       0x000034C0</div><div class='add'>+</div><div class='add'>+/* begin *********************</div><div class='add'>+ * macros to expend register list macro defined in HW object header file */</div><div class='add'>+</div><div class='add'>+/* DCN */</div><div class='add'>+#define block HPD</div><div class='add'>+#define reg_num 0</div><div class='add'>+</div><div class='add'>+#undef BASE_INNER</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define REG(reg_name)\</div><div class='add'>+		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define SF_HPD(reg_name, field_name, post_fix)\</div><div class='add'>+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+#define REGI(reg_name, block, id)\</div><div class='add'>+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+				reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SF(reg_name, field_name, post_fix)\</div><div class='add'>+	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+/* macros to expend register list macro defined in HW object header file</div><div class='add'>+ * end *********************/</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define hpd_regs(id) \</div><div class='add'>+{\</div><div class='add'>+	HPD_REG_LIST(id)\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hpd_registers hpd_regs[] = {</div><div class='add'>+	hpd_regs(0),</div><div class='add'>+	hpd_regs(1),</div><div class='add'>+	hpd_regs(2),</div><div class='add'>+	hpd_regs(3),</div><div class='add'>+//	hpd_regs(4),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hpd_sh_mask hpd_shift = {</div><div class='add'>+		HPD_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hpd_sh_mask hpd_mask = {</div><div class='add'>+		HPD_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "../ddc_regs.h"</div><div class='add'>+</div><div class='add'>+ /* set field name */</div><div class='add'>+#define SF_DDC(reg_name, field_name, post_fix)\</div><div class='add'>+	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+static const struct ddc_registers ddc_data_regs_dcn[] = {</div><div class='add'>+	ddc_data_regs_dcn2(1),</div><div class='add'>+	ddc_data_regs_dcn2(2),</div><div class='add'>+	ddc_data_regs_dcn2(3),</div><div class='add'>+	ddc_data_regs_dcn2(4),</div><div class='add'>+	{</div><div class='add'>+		// add a dummy entry for cases no such port</div><div class='add'>+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},</div><div class='add'>+		.ddc_setup = 0,</div><div class='add'>+		.phy_aux_cntl = 0,</div><div class='add'>+		.dc_gpio_aux_ctrl_5 = 0</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		// add a dummy entry for cases no such port</div><div class='add'>+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},</div><div class='add'>+		.ddc_setup = 0,</div><div class='add'>+		.phy_aux_cntl = 0,</div><div class='add'>+		.dc_gpio_aux_ctrl_5 = 0</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+			DDC_GPIO_VGA_REG_LIST(DATA),</div><div class='add'>+			.ddc_setup = 0,</div><div class='add'>+			.phy_aux_cntl = 0,</div><div class='add'>+			.dc_gpio_aux_ctrl_5 = 0</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ddc_registers ddc_clk_regs_dcn[] = {</div><div class='add'>+	ddc_clk_regs_dcn2(1),</div><div class='add'>+	ddc_clk_regs_dcn2(2),</div><div class='add'>+	ddc_clk_regs_dcn2(3),</div><div class='add'>+	ddc_clk_regs_dcn2(4),</div><div class='add'>+	{</div><div class='add'>+		// add a dummy entry for cases no such port</div><div class='add'>+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},</div><div class='add'>+		.ddc_setup = 0,</div><div class='add'>+		.phy_aux_cntl = 0,</div><div class='add'>+		.dc_gpio_aux_ctrl_5 = 0</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		// add a dummy entry for cases no such port</div><div class='add'>+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},</div><div class='add'>+		.ddc_setup = 0,</div><div class='add'>+		.phy_aux_cntl = 0,</div><div class='add'>+		.dc_gpio_aux_ctrl_5 = 0</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+			DDC_GPIO_VGA_REG_LIST(CLK),</div><div class='add'>+			.ddc_setup = 0,</div><div class='add'>+			.phy_aux_cntl = 0,</div><div class='add'>+			.dc_gpio_aux_ctrl_5 = 0</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ddc_sh_mask ddc_shift[] = {</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ddc_sh_mask ddc_mask[] = {</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(_MASK, 1),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(_MASK, 2),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(_MASK, 3),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(_MASK, 4),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(_MASK, 5),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2(_MASK, 6),</div><div class='add'>+	DDC_MASK_SH_LIST_DCN2_VGA(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#include "../generic_regs.h"</div><div class='add'>+</div><div class='add'>+/* set field name */</div><div class='add'>+#define SF_GENERIC(reg_name, field_name, post_fix)\</div><div class='add'>+	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+#define generic_regs(id) \</div><div class='add'>+{\</div><div class='add'>+	GENERIC_REG_LIST(id)\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct generic_registers generic_regs[] = {</div><div class='add'>+	generic_regs(A),</div><div class='add'>+	generic_regs(B),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct generic_sh_mask generic_shift[] = {</div><div class='add'>+	GENERIC_MASK_SH_LIST(__SHIFT, A),</div><div class='add'>+	GENERIC_MASK_SH_LIST(__SHIFT, B),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct generic_sh_mask generic_mask[] = {</div><div class='add'>+	GENERIC_MASK_SH_LIST(_MASK, A),</div><div class='add'>+	GENERIC_MASK_SH_LIST(_MASK, B),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)</div><div class='add'>+{</div><div class='add'>+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);</div><div class='add'>+</div><div class='add'>+	generic-&gt;regs = &amp;generic_regs[en];</div><div class='add'>+	generic-&gt;shifts = &amp;generic_shift[en];</div><div class='add'>+	generic-&gt;masks = &amp;generic_mask[en];</div><div class='add'>+	generic-&gt;base.regs = &amp;generic_regs[en].gpio;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void define_ddc_registers(</div><div class='add'>+		struct hw_gpio_pin *pin,</div><div class='add'>+		uint32_t en)</div><div class='add'>+{</div><div class='add'>+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);</div><div class='add'>+</div><div class='add'>+	switch (pin-&gt;id) {</div><div class='add'>+	case GPIO_ID_DDC_DATA:</div><div class='add'>+		ddc-&gt;regs = &amp;ddc_data_regs_dcn[en];</div><div class='add'>+		ddc-&gt;base.regs = &amp;ddc_data_regs_dcn[en].gpio;</div><div class='add'>+		break;</div><div class='add'>+	case GPIO_ID_DDC_CLOCK:</div><div class='add'>+		ddc-&gt;regs = &amp;ddc_clk_regs_dcn[en];</div><div class='add'>+		ddc-&gt;base.regs = &amp;ddc_clk_regs_dcn[en].gpio;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ddc-&gt;shifts = &amp;ddc_shift[en];</div><div class='add'>+	ddc-&gt;masks = &amp;ddc_mask[en];</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)</div><div class='add'>+{</div><div class='add'>+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);</div><div class='add'>+</div><div class='add'>+	hpd-&gt;regs = &amp;hpd_regs[en];</div><div class='add'>+	hpd-&gt;shifts = &amp;hpd_shift;</div><div class='add'>+	hpd-&gt;masks = &amp;hpd_mask;</div><div class='add'>+	hpd-&gt;base.regs = &amp;hpd_regs[en].gpio;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* function table */</div><div class='add'>+static const struct hw_factory_funcs funcs = {</div><div class='add'>+	.init_ddc_data = dal_hw_ddc_init,</div><div class='add'>+	.init_generic = dal_hw_generic_init,</div><div class='add'>+	.init_hpd = dal_hw_hpd_init,</div><div class='add'>+	.get_ddc_pin = dal_hw_ddc_get_pin,</div><div class='add'>+	.get_hpd_pin = dal_hw_hpd_get_pin,</div><div class='add'>+	.get_generic_pin = dal_hw_generic_get_pin,</div><div class='add'>+	.define_hpd_registers = define_hpd_registers,</div><div class='add'>+	.define_ddc_registers = define_ddc_registers,</div><div class='add'>+	.define_generic_registers = define_generic_registers</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * dal_hw_factory_dcn401_init</div><div class='add'>+ *</div><div class='add'>+ * @brief</div><div class='add'>+ * Initialize HW factory function pointers and pin info</div><div class='add'>+ *</div><div class='add'>+ * @param</div><div class='add'>+ * struct hw_factory *factory - [out] struct of function pointers</div><div class='add'>+ */</div><div class='add'>+void dal_hw_factory_dcn401_init(struct hw_factory *factory)</div><div class='add'>+{</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_DDC_DATA] = 8;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_DDC_CLOCK] = 8;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_GENERIC] = 4;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_HPD] = 5;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_GPIO_PAD] = 28;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_VIP_PAD] = 0;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_SYNC] = 0;</div><div class='add'>+	factory-&gt;number_of_pins[GPIO_ID_GSL] = 0;/*add this*/</div><div class='add'>+</div><div class='add'>+	factory-&gt;funcs = &amp;funcs;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.h<br/>new file mode 100644<br/>index 000000000000..22e650723ee7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.h</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DAL_HW_FACTORY_DCN401_H__</div><div class='add'>+#define __DAL_HW_FACTORY_DCN401_H__</div><div class='add'>+</div><div class='add'>+/* Initialize HW factory function pointers and pin info */</div><div class='add'>+void dal_hw_factory_dcn401_init(struct hw_factory *factory);</div><div class='add'>+</div><div class='add'>+#endif /* __DAL_HW_FACTORY_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c<br/>new file mode 100644<br/>index 000000000000..ea416f01f888<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c</a></div><div class='hunk'>@@ -0,0 +1,335 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "hw_translate_dcn401.h"</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "include/gpio_types.h"</div><div class='add'>+#include "../hw_translate.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_4_1_0_offset.h"</div><div class='add'>+#include "dcn/dcn_4_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#define DCN_BASE__INST0_SEG2                       0x000034C0</div><div class='add'>+/* begin *********************</div><div class='add'>+ * macros to expend register list macro defined in HW object header file */</div><div class='add'>+</div><div class='add'>+/* DCN */</div><div class='add'>+#define block HPD</div><div class='add'>+#define reg_num 0</div><div class='add'>+</div><div class='add'>+#undef BASE_INNER</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#undef REG</div><div class='add'>+#define REG(reg_name)\</div><div class='add'>+		BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name</div><div class='add'>+#define SF_HPD(reg_name, field_name, post_fix)\</div><div class='add'>+	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* macros to expend register list macro defined in HW object header file</div><div class='add'>+ * end *********************/</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool offset_to_id(</div><div class='add'>+	uint32_t offset,</div><div class='add'>+	uint32_t mask,</div><div class='add'>+	enum gpio_id *id,</div><div class='add'>+	uint32_t *en)</div><div class='add'>+{</div><div class='add'>+	switch (offset) {</div><div class='add'>+	/* GENERIC */</div><div class='add'>+	case REG(DC_GPIO_GENERIC_A):</div><div class='add'>+		*id = GPIO_ID_GENERIC;</div><div class='add'>+		switch (mask) {</div><div class='add'>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:</div><div class='add'>+			*en = GPIO_GENERIC_A;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:</div><div class='add'>+			*en = GPIO_GENERIC_B;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:</div><div class='add'>+			*en = GPIO_GENERIC_C;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:</div><div class='add'>+			*en = GPIO_GENERIC_D;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:</div><div class='add'>+			*en = GPIO_GENERIC_E;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:</div><div class='add'>+			*en = GPIO_GENERIC_F;</div><div class='add'>+			return true;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	/* HPD */</div><div class='add'>+	case REG(DC_GPIO_HPD_A):</div><div class='add'>+		*id = GPIO_ID_HPD;</div><div class='add'>+		switch (mask) {</div><div class='add'>+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:</div><div class='add'>+			*en = GPIO_HPD_1;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:</div><div class='add'>+			*en = GPIO_HPD_2;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:</div><div class='add'>+			*en = GPIO_HPD_3;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:</div><div class='add'>+			*en = GPIO_HPD_4;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:</div><div class='add'>+			*en = GPIO_HPD_5;</div><div class='add'>+			return true;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	/* REG(DC_GPIO_GENLK_MASK */</div><div class='add'>+	case REG(DC_GPIO_GENLK_A):</div><div class='add'>+		*id = GPIO_ID_GSL;</div><div class='add'>+		switch (mask) {</div><div class='add'>+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:</div><div class='add'>+			*en = GPIO_GSL_GENLOCK_CLOCK;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:</div><div class='add'>+			*en = GPIO_GSL_GENLOCK_VSYNC;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:</div><div class='add'>+			*en = GPIO_GSL_SWAPLOCK_A;</div><div class='add'>+			return true;</div><div class='add'>+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:</div><div class='add'>+			*en = GPIO_GSL_SWAPLOCK_B;</div><div class='add'>+			return true;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	/* DDC */</div><div class='add'>+	/* we don't care about the GPIO_ID for DDC</div><div class='add'>+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK</div><div class='add'>+	 * directly in the create method</div><div class='add'>+	 */</div><div class='add'>+	case REG(DC_GPIO_DDC1_A):</div><div class='add'>+		*en = GPIO_DDC_LINE_DDC1;</div><div class='add'>+		return true;</div><div class='add'>+	case REG(DC_GPIO_DDC2_A):</div><div class='add'>+		*en = GPIO_DDC_LINE_DDC2;</div><div class='add'>+		return true;</div><div class='add'>+	case REG(DC_GPIO_DDC3_A):</div><div class='add'>+		*en = GPIO_DDC_LINE_DDC3;</div><div class='add'>+		return true;</div><div class='add'>+	case REG(DC_GPIO_DDC4_A):</div><div class='add'>+		*en = GPIO_DDC_LINE_DDC4;</div><div class='add'>+		return true;</div><div class='add'>+	case REG(DC_GPIO_DDCVGA_A):</div><div class='add'>+		*en = GPIO_DDC_LINE_DDC_VGA;</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ *	case REG(DC_GPIO_I2CPAD_A): not exit</div><div class='add'>+ *	case REG(DC_GPIO_PWRSEQ_A):</div><div class='add'>+ *	case REG(DC_GPIO_PAD_STRENGTH_1):</div><div class='add'>+ *	case REG(DC_GPIO_PAD_STRENGTH_2):</div><div class='add'>+ *	case REG(DC_GPIO_DEBUG):</div><div class='add'>+ */</div><div class='add'>+	/* UNEXPECTED */</div><div class='add'>+	default:</div><div class='add'>+/*	case REG(DC_GPIO_SYNCA_A): not exist */</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool id_to_offset(</div><div class='add'>+	enum gpio_id id,</div><div class='add'>+	uint32_t en,</div><div class='add'>+	struct gpio_pin_info *info)</div><div class='add'>+{</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='add'>+	switch (id) {</div><div class='add'>+	case GPIO_ID_DDC_DATA:</div><div class='add'>+		info-&gt;mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;</div><div class='add'>+		switch (en) {</div><div class='add'>+		case GPIO_DDC_LINE_DDC1:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC1_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_DDC2:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC2_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_DDC3:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC3_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_DDC4:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC4_A);</div><div class='add'>+		break;</div><div class='add'>+/*		case GPIO_DDC_LINE_DDC5:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC5_A);</div><div class='add'>+		break; */</div><div class='add'>+		case GPIO_DDC_LINE_DDC_VGA:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDCVGA_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_I2C_PAD:</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	case GPIO_ID_DDC_CLOCK:</div><div class='add'>+		info-&gt;mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;</div><div class='add'>+		switch (en) {</div><div class='add'>+		case GPIO_DDC_LINE_DDC1:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC1_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_DDC2:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC2_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_DDC3:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC3_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_DDC4:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC4_A);</div><div class='add'>+		break;</div><div class='add'>+/*		case GPIO_DDC_LINE_DDC5:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDC5_A);</div><div class='add'>+		break; */</div><div class='add'>+		case GPIO_DDC_LINE_DDC_VGA:</div><div class='add'>+			info-&gt;offset = REG(DC_GPIO_DDCVGA_A);</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_DDC_LINE_I2C_PAD:</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	case GPIO_ID_GENERIC:</div><div class='add'>+		info-&gt;offset = REG(DC_GPIO_GENERIC_A);</div><div class='add'>+		switch (en) {</div><div class='add'>+		case GPIO_GENERIC_A:</div><div class='add'>+			info-&gt;mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GENERIC_B:</div><div class='add'>+			info-&gt;mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GENERIC_C:</div><div class='add'>+			info-&gt;mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GENERIC_D:</div><div class='add'>+			info-&gt;mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GENERIC_E:</div><div class='add'>+			info-&gt;mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GENERIC_F:</div><div class='add'>+			info-&gt;mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	case GPIO_ID_HPD:</div><div class='add'>+		info-&gt;offset = REG(DC_GPIO_HPD_A);</div><div class='add'>+		switch (en) {</div><div class='add'>+		case GPIO_HPD_1:</div><div class='add'>+			info-&gt;mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_HPD_2:</div><div class='add'>+			info-&gt;mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_HPD_3:</div><div class='add'>+			info-&gt;mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_HPD_4:</div><div class='add'>+			info-&gt;mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_HPD_5:</div><div class='add'>+			info-&gt;mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;</div><div class='add'>+		break;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	case GPIO_ID_GSL:</div><div class='add'>+		switch (en) {</div><div class='add'>+		case GPIO_GSL_GENLOCK_CLOCK:</div><div class='add'>+				/*not implmented*/</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GSL_GENLOCK_VSYNC:</div><div class='add'>+			/*not implmented*/</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GSL_SWAPLOCK_A:</div><div class='add'>+			/*not implmented*/</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		break;</div><div class='add'>+		case GPIO_GSL_SWAPLOCK_B:</div><div class='add'>+			/*not implmented*/</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT_CRITICAL(false);</div><div class='add'>+			result = false;</div><div class='add'>+		}</div><div class='add'>+	break;</div><div class='add'>+	case GPIO_ID_SYNC:</div><div class='add'>+	case GPIO_ID_VIP_PAD:</div><div class='add'>+	default:</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+		result = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (result) {</div><div class='add'>+		info-&gt;offset_y = info-&gt;offset + 2;</div><div class='add'>+		info-&gt;offset_en = info-&gt;offset + 1;</div><div class='add'>+		info-&gt;offset_mask = info-&gt;offset - 1;</div><div class='add'>+</div><div class='add'>+		info-&gt;mask_y = info-&gt;mask;</div><div class='add'>+		info-&gt;mask_en = info-&gt;mask;</div><div class='add'>+		info-&gt;mask_mask = info-&gt;mask;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* function table */</div><div class='add'>+static const struct hw_translate_funcs funcs = {</div><div class='add'>+	.offset_to_id = offset_to_id,</div><div class='add'>+	.id_to_offset = id_to_offset,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * dal_hw_translate_dcn401_init</div><div class='add'>+ *</div><div class='add'>+ * @brief</div><div class='add'>+ * Initialize Hw translate function pointers.</div><div class='add'>+ *</div><div class='add'>+ * @param</div><div class='add'>+ * struct hw_translate *tr - [out] struct of function pointers</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void dal_hw_translate_dcn401_init(struct hw_translate *tr)</div><div class='add'>+{</div><div class='add'>+	tr-&gt;funcs = &amp;funcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.h<br/>new file mode 100644<br/>index 000000000000..aadecb05bba1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DAL_HW_TRANSLATE_DCN401_H__</div><div class='add'>+#define __DAL_HW_TRANSLATE_DCN401_H__</div><div class='add'>+</div><div class='add'>+struct hw_translate;</div><div class='add'>+</div><div class='add'>+/* Initialize Hw translate function pointers */</div><div class='add'>+void dal_hw_translate_dcn401_init(struct hw_translate *tr);</div><div class='add'>+</div><div class='add'>+#endif /* __DAL_HW_TRANSLATE_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c<br/>index 3ede6e02c3a7..942d9f0b6df2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c</a></div><div class='hunk'>@@ -56,7 +56,7 @@ struct gpio_service *dal_gpio_service_create(</div><div class='ctx'> 	struct dc_context *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_service *service;</div><div class='del'>-	uint32_t index_of_id;</div><div class='add'>+	int32_t index_of_id;</div><div class='ctx'> </div><div class='ctx'> 	service = kzalloc(sizeof(struct gpio_service), GFP_KERNEL);</div><div class='ctx'> </div><div class='hunk'>@@ -112,7 +112,7 @@ struct gpio_service *dal_gpio_service_create(</div><div class='ctx'> 	return service;</div><div class='ctx'> </div><div class='ctx'> failure_2:</div><div class='del'>-	while (index_of_id) {</div><div class='add'>+	while (index_of_id &gt; 0) {</div><div class='ctx'> 		--index_of_id;</div><div class='ctx'> 		kfree(service-&gt;busyness[index_of_id]);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -128,7 +128,7 @@ struct gpio *dal_gpio_service_create_irq(</div><div class='ctx'> 	uint32_t offset,</div><div class='ctx'> 	uint32_t mask)</div><div class='ctx'> {</div><div class='del'>-	enum gpio_id id;</div><div class='add'>+	enum gpio_id id = 0;</div><div class='ctx'> 	uint32_t en;</div><div class='ctx'> </div><div class='ctx'> 	if (!service-&gt;translate.funcs-&gt;offset_to_id(offset, mask, &amp;id, &amp;en)) {</div><div class='hunk'>@@ -144,7 +144,7 @@ struct gpio *dal_gpio_service_create_generic_mux(</div><div class='ctx'> 	uint32_t offset,</div><div class='ctx'> 	uint32_t mask)</div><div class='ctx'> {</div><div class='del'>-	enum gpio_id id;</div><div class='add'>+	enum gpio_id id = 0;</div><div class='ctx'> 	uint32_t en;</div><div class='ctx'> 	struct gpio *generic;</div><div class='ctx'> </div><div class='hunk'>@@ -178,7 +178,7 @@ struct gpio_pin_info dal_gpio_get_generic_pin_info(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_pin_info pin;</div><div class='add'>+	struct gpio_pin_info pin = {0};</div><div class='ctx'> </div><div class='ctx'> 	if (service-&gt;translate.funcs-&gt;id_to_offset) {</div><div class='ctx'> 		service-&gt;translate.funcs-&gt;id_to_offset(id, en, &amp;pin);</div><div class='hunk'>@@ -239,6 +239,9 @@ static bool is_pin_busy(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='add'>+	if (id == GPIO_ID_UNKNOWN)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	return service-&gt;busyness[id][en];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -247,6 +250,9 @@ static void set_pin_busy(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='add'>+	if (id == GPIO_ID_UNKNOWN)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	service-&gt;busyness[id][en] = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -255,6 +261,9 @@ static void set_pin_free(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='add'>+	if (id == GPIO_ID_UNKNOWN)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	service-&gt;busyness[id][en] = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -263,7 +272,7 @@ enum gpio_result dal_gpio_service_lock(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='del'>-	if (!service-&gt;busyness[id]) {</div><div class='add'>+	if (id != GPIO_ID_UNKNOWN &amp;&amp; !service-&gt;busyness[id]) {</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		return GPIO_RESULT_OPEN_FAILED;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -277,7 +286,7 @@ enum gpio_result dal_gpio_service_unlock(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='del'>-	if (!service-&gt;busyness[id]) {</div><div class='add'>+	if (id != GPIO_ID_UNKNOWN &amp;&amp; !service-&gt;busyness[id]) {</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		return GPIO_RESULT_OPEN_FAILED;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -402,6 +411,20 @@ enum dc_irq_source dal_irq_get_rx_source(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+enum dc_irq_source dal_irq_get_read_request(</div><div class='add'>+	const struct gpio *irq)</div><div class='add'>+{</div><div class='add'>+	enum gpio_id id = dal_gpio_get_id(irq);</div><div class='add'>+</div><div class='add'>+	switch (id) {</div><div class='add'>+	case GPIO_ID_HPD:</div><div class='add'>+		return (enum dc_irq_source)(DC_IRQ_SOURCE_DCI2C_RR_DDC1 +</div><div class='add'>+			dal_gpio_get_enum(irq));</div><div class='add'>+	default:</div><div class='add'>+		return DC_IRQ_SOURCE_INVALID;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum gpio_result dal_irq_setup_hpd_filter(</div><div class='ctx'> 	struct gpio *irq,</div><div class='ctx'> 	struct gpio_hpd_config *config)</div><div class='hunk'>@@ -434,7 +457,6 @@ struct gpio *dal_gpio_create_irq(</div><div class='ctx'> 	case GPIO_ID_GPIO_PAD:</div><div class='ctx'> 	break;</div><div class='ctx'> 	default:</div><div class='del'>-		id = GPIO_ID_HPD;</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c<br/>index 525bc8881950..d9e6e70dc394 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c</a></div><div class='hunk'>@@ -170,8 +170,7 @@ static enum gpio_result set_config(</div><div class='ctx'> </div><div class='ctx'> 		return GPIO_RESULT_OK;</div><div class='ctx'> 	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:</div><div class='del'>-		if ((hw_gpio-&gt;base.en &gt;= GPIO_DDC_LINE_DDC1) &amp;&amp;</div><div class='del'>-			(hw_gpio-&gt;base.en &lt;= GPIO_DDC_LINE_DDC_VGA)) {</div><div class='add'>+		if (hw_gpio-&gt;base.en &lt;= GPIO_DDC_LINE_DDC_VGA) {</div><div class='ctx'> 			REG_UPDATE_3(ddc_setup,</div><div class='ctx'> 				DC_I2C_DDC1_ENABLE, 1,</div><div class='ctx'> 				DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,</div><div class='hunk'>@@ -180,8 +179,7 @@ static enum gpio_result set_config(</div><div class='ctx'> 		}</div><div class='ctx'> 	break;</div><div class='ctx'> 	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:</div><div class='del'>-		if ((hw_gpio-&gt;base.en &gt;= GPIO_DDC_LINE_DDC1) &amp;&amp;</div><div class='del'>-			(hw_gpio-&gt;base.en &lt;= GPIO_DDC_LINE_DDC_VGA)) {</div><div class='add'>+		if (hw_gpio-&gt;base.en &lt;= GPIO_DDC_LINE_DDC_VGA) {</div><div class='ctx'> 			REG_UPDATE_3(ddc_setup,</div><div class='ctx'> 				DC_I2C_DDC1_ENABLE, 1,</div><div class='ctx'> 				DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,</div><div class='hunk'>@@ -190,8 +188,7 @@ static enum gpio_result set_config(</div><div class='ctx'> 		}</div><div class='ctx'> 	break;</div><div class='ctx'> 	case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:</div><div class='del'>-		if ((hw_gpio-&gt;base.en &gt;= GPIO_DDC_LINE_DDC1) &amp;&amp;</div><div class='del'>-			(hw_gpio-&gt;base.en &lt;= GPIO_DDC_LINE_DDC_VGA)) {</div><div class='add'>+		if (hw_gpio-&gt;base.en &lt;= GPIO_DDC_LINE_DDC_VGA) {</div><div class='ctx'> 			REG_UPDATE_2(ddc_setup,</div><div class='ctx'> 				DC_I2C_DDC1_ENABLE, 0,</div><div class='ctx'> 				DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);</div><div class='hunk'>@@ -231,7 +228,7 @@ void dal_hw_ddc_init(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='del'>-	if ((en &lt; GPIO_DDC_LINE_MIN) || (en &gt; GPIO_DDC_LINE_MAX)) {</div><div class='add'>+	if (en &gt; GPIO_DDC_LINE_MAX) {</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		*hw_ddc = NULL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c<br/>index 8f1a95b77830..8bc67ca42197 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c</a></div><div class='hunk'>@@ -52,6 +52,7 @@</div><div class='ctx'> #include "dcn30/hw_factory_dcn30.h"</div><div class='ctx'> #include "dcn315/hw_factory_dcn315.h"</div><div class='ctx'> #include "dcn32/hw_factory_dcn32.h"</div><div class='add'>+#include "dcn401/hw_factory_dcn401.h"</div><div class='ctx'> </div><div class='ctx'> bool dal_hw_factory_init(</div><div class='ctx'> 	struct hw_factory *factory,</div><div class='hunk'>@@ -111,8 +112,12 @@ bool dal_hw_factory_init(</div><div class='ctx'> 	case DCN_VERSION_3_21:</div><div class='ctx'> 	case DCN_VERSION_3_5:</div><div class='ctx'> 	case DCN_VERSION_3_51:</div><div class='add'>+	case DCN_VERSION_3_6:</div><div class='ctx'> 		dal_hw_factory_dcn32_init(factory);</div><div class='ctx'> 		return true;</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		dal_hw_factory_dcn401_init(factory);</div><div class='add'>+		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		return false;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c<br/>index f9e847e6555d..6cd50232c432 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c</a></div><div class='hunk'>@@ -106,7 +106,7 @@ void dal_hw_generic_init(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='del'>-	if ((en &lt; GPIO_DDC_LINE_MIN) || (en &gt; GPIO_DDC_LINE_MAX)) {</div><div class='add'>+	if (en &gt; GPIO_DDC_LINE_MAX) {</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		*hw_generic = NULL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c<br/>index 1489fdfaf0e7..01ec451004f7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c</a></div><div class='hunk'>@@ -62,7 +62,7 @@ static void dal_hw_hpd_destroy(</div><div class='ctx'> 	*ptr = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum gpio_result get_value(</div><div class='add'>+static enum gpio_result dal_hw_hpd_get_value(</div><div class='ctx'> 	const struct hw_gpio_pin *ptr,</div><div class='ctx'> 	uint32_t *value)</div><div class='ctx'> {</div><div class='hunk'>@@ -85,7 +85,7 @@ static enum gpio_result get_value(</div><div class='ctx'> 	return dal_hw_gpio_get_value(ptr, value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum gpio_result set_config(</div><div class='add'>+static enum gpio_result dal_hw_hpd_set_config(</div><div class='ctx'> 	struct hw_gpio_pin *ptr,</div><div class='ctx'> 	const struct gpio_config_data *config_data)</div><div class='ctx'> {</div><div class='hunk'>@@ -104,9 +104,9 @@ static enum gpio_result set_config(</div><div class='ctx'> static const struct hw_gpio_pin_funcs funcs = {</div><div class='ctx'> 	.destroy = dal_hw_hpd_destroy,</div><div class='ctx'> 	.open = dal_hw_gpio_open,</div><div class='del'>-	.get_value = get_value,</div><div class='add'>+	.get_value = dal_hw_hpd_get_value,</div><div class='ctx'> 	.set_value = dal_hw_gpio_set_value,</div><div class='del'>-	.set_config = set_config,</div><div class='add'>+	.set_config = dal_hw_hpd_set_config,</div><div class='ctx'> 	.change_mode = dal_hw_gpio_change_mode,</div><div class='ctx'> 	.close = dal_hw_gpio_close,</div><div class='ctx'> };</div><div class='hunk'>@@ -127,7 +127,7 @@ void dal_hw_hpd_init(</div><div class='ctx'> 	enum gpio_id id,</div><div class='ctx'> 	uint32_t en)</div><div class='ctx'> {</div><div class='del'>-	if ((en &lt; GPIO_DDC_LINE_MIN) || (en &gt; GPIO_DDC_LINE_MAX)) {</div><div class='add'>+	if (en &gt; GPIO_DDC_LINE_MAX) {</div><div class='ctx'> 		ASSERT_CRITICAL(false);</div><div class='ctx'> 		*hw_hpd = NULL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c<br/>index 37166b2b3fee..cb79a2832287 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c</a></div><div class='hunk'>@@ -52,6 +52,7 @@</div><div class='ctx'> #include "dcn30/hw_translate_dcn30.h"</div><div class='ctx'> #include "dcn315/hw_translate_dcn315.h"</div><div class='ctx'> #include "dcn32/hw_translate_dcn32.h"</div><div class='add'>+#include "dcn401/hw_translate_dcn401.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * This unit</div><div class='hunk'>@@ -112,8 +113,12 @@ bool dal_hw_translate_init(</div><div class='ctx'> 	case DCN_VERSION_3_21:</div><div class='ctx'> 	case DCN_VERSION_3_5:</div><div class='ctx'> 	case DCN_VERSION_3_51:</div><div class='add'>+	case DCN_VERSION_3_6:</div><div class='ctx'> 		dal_hw_translate_dcn32_init(translate);</div><div class='ctx'> 		return true;</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		dal_hw_translate_dcn401_init(translate);</div><div class='add'>+		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='ctx'> 		return false;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c<br/>index 99e17c164ce7..73a1e6a03719 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@</div><div class='ctx'> #include "include/hdcp_msg_types.h"</div><div class='ctx'> #include "include/signal_types.h"</div><div class='ctx'> #include "core_types.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "link_hwss.h"</div><div class='ctx'> #include "link/protocols/link_dpcd.h"</div><div class='ctx'> </div><div class='hunk'>@@ -70,7 +70,7 @@ static const bool hdcp_cmd_is_read[HDCP_MESSAGE_ID_MAX] = {</div><div class='ctx'> 	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = false,</div><div class='ctx'> 	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = true,</div><div class='ctx'> 	[HDCP_MESSAGE_ID_READ_RXSTATUS] = true,</div><div class='del'>-	[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false</div><div class='add'>+	[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint8_t hdcp_i2c_offsets[HDCP_MESSAGE_ID_MAX] = {</div><div class='hunk'>@@ -128,13 +128,21 @@ static bool hdmi_14_process_transaction(</div><div class='ctx'> 	const uint8_t hdcp_i2c_addr_link_primary = 0x3a; /* 0x74 &gt;&gt; 1*/</div><div class='ctx'> 	const uint8_t hdcp_i2c_addr_link_secondary = 0x3b; /* 0x76 &gt;&gt; 1*/</div><div class='ctx'> 	struct i2c_command i2c_command;</div><div class='del'>-	uint8_t offset = hdcp_i2c_offsets[message_info-&gt;msg_id];</div><div class='add'>+	uint8_t offset;</div><div class='ctx'> 	struct i2c_payload i2c_payloads[] = {</div><div class='del'>-		{ true, 0, 1, &amp;offset },</div><div class='add'>+		{ true, 0, 1, 0 },</div><div class='ctx'> 		/* actual hdcp payload, will be filled later, zeroed for now*/</div><div class='ctx'> 		{ 0 }</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	if (message_info-&gt;msg_id == HDCP_MESSAGE_ID_INVALID) {</div><div class='add'>+		DC_LOG_ERROR("%s: Invalid message_info msg_id - %d\n", __func__, message_info-&gt;msg_id);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	offset = hdcp_i2c_offsets[message_info-&gt;msg_id];</div><div class='add'>+	i2c_payloads[0].data = &amp;offset;</div><div class='add'>+</div><div class='ctx'> 	switch (message_info-&gt;link) {</div><div class='ctx'> 	case HDCP_LINK_SECONDARY:</div><div class='ctx'> 		i2c_payloads[0].address = hdcp_i2c_addr_link_secondary;</div><div class='hunk'>@@ -308,6 +316,11 @@ static bool dp_11_process_transaction(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	struct hdcp_protection_message *message_info)</div><div class='ctx'> {</div><div class='add'>+	if (message_info-&gt;msg_id == HDCP_MESSAGE_ID_INVALID) {</div><div class='add'>+		DC_LOG_ERROR("%s: Invalid message_info msg_id - %d\n", __func__, message_info-&gt;msg_id);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return dpcd_access_helper(</div><div class='ctx'> 		link,</div><div class='ctx'> 		message_info-&gt;length,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hpo/Makefile b/drivers/gpu/drm/amd/display/dc/hpo/Makefile<br/>new file mode 100644<br/>index 000000000000..7f2c9ee0dff1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/Makefile</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN30</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+AMD_DAL_HPO_DCN30 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn30/,$(HPO_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN30)</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN31</div><div class='add'>+###############################################################################</div><div class='add'>+HPO_DCN31 = dcn31_hpo_dp_stream_encoder.o dcn31_hpo_dp_link_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HPO_DCN31 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn31/,$(HPO_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN31)</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN32</div><div class='add'>+###############################################################################</div><div class='add'>+HPO_DCN32 = dcn32_hpo_dp_link_encoder.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HPO_DCN32 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn32/,$(HPO_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN32)</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c<br/>index 5b7ad38f85e0..0d2ae21abbdd 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c</a></div><div class='hunk'>@@ -262,7 +262,7 @@ void dcn31_hpo_dp_link_enc_set_link_test_pattern(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void fill_stream_allocation_row_info(</div><div class='add'>+void dcn31_fill_stream_allocation_row_info(</div><div class='ctx'> 		const struct link_mst_stream_allocation *stream_allocation,</div><div class='ctx'> 		uint32_t *src,</div><div class='ctx'> 		uint32_t *slots)</div><div class='hunk'>@@ -296,7 +296,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(</div><div class='ctx'> 	/* we should clean-up table each time */</div><div class='ctx'> </div><div class='ctx'> 	if (table-&gt;stream_count &gt;= 1) {</div><div class='del'>-		fill_stream_allocation_row_info(</div><div class='add'>+		dcn31_fill_stream_allocation_row_info(</div><div class='ctx'> 			&amp;table-&gt;stream_allocations[0],</div><div class='ctx'> 			&amp;src,</div><div class='ctx'> 			&amp;slots);</div><div class='hunk'>@@ -310,7 +310,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(</div><div class='ctx'> 			SAT_SLOT_COUNT, slots);</div><div class='ctx'> </div><div class='ctx'> 	if (table-&gt;stream_count &gt;= 2) {</div><div class='del'>-		fill_stream_allocation_row_info(</div><div class='add'>+		dcn31_fill_stream_allocation_row_info(</div><div class='ctx'> 			&amp;table-&gt;stream_allocations[1],</div><div class='ctx'> 			&amp;src,</div><div class='ctx'> 			&amp;slots);</div><div class='hunk'>@@ -324,7 +324,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(</div><div class='ctx'> 			SAT_SLOT_COUNT, slots);</div><div class='ctx'> </div><div class='ctx'> 	if (table-&gt;stream_count &gt;= 3) {</div><div class='del'>-		fill_stream_allocation_row_info(</div><div class='add'>+		dcn31_fill_stream_allocation_row_info(</div><div class='ctx'> 			&amp;table-&gt;stream_allocations[2],</div><div class='ctx'> 			&amp;src,</div><div class='ctx'> 			&amp;slots);</div><div class='hunk'>@@ -338,7 +338,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(</div><div class='ctx'> 			SAT_SLOT_COUNT, slots);</div><div class='ctx'> </div><div class='ctx'> 	if (table-&gt;stream_count &gt;= 4) {</div><div class='del'>-		fill_stream_allocation_row_info(</div><div class='add'>+		dcn31_fill_stream_allocation_row_info(</div><div class='ctx'> 			&amp;table-&gt;stream_allocations[3],</div><div class='ctx'> 			&amp;src,</div><div class='ctx'> 			&amp;slots);</div><div class='hunk'>@@ -377,7 +377,7 @@ void dcn31_hpo_dp_link_enc_update_stream_allocation_table(</div><div class='ctx'> 	 */</div><div class='ctx'> 	REG_WAIT(DP_DPHY_SYM32_STATUS,</div><div class='ctx'> 			SAT_UPDATE_PENDING, 0,</div><div class='del'>-			10, DP_SAT_UPDATE_MAX_RETRY);</div><div class='add'>+			100, DP_SAT_UPDATE_MAX_RETRY);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(</div><div class='hunk'>@@ -395,6 +395,12 @@ void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(</div><div class='ctx'> 				x),</div><div class='ctx'> 			25));</div><div class='ctx'> </div><div class='add'>+	// If y rounds up to integer, carry it over to x.</div><div class='add'>+	if (y &gt;&gt; 25) {</div><div class='add'>+		x += 1;</div><div class='add'>+		y = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	switch (stream_encoder_inst) {</div><div class='ctx'> 	case 0:</div><div class='ctx'> 		REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, 0,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h<br/>index 51f5781325e8..40859660e4dc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.h</a></div><div class='hunk'>@@ -226,4 +226,10 @@ void dcn31_hpo_dp_link_enc_set_ffe(</div><div class='ctx'> 	const struct dc_link_settings *link_settings,</div><div class='ctx'> 	uint8_t ffe_preset);</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+void dcn31_fill_stream_allocation_row_info(</div><div class='add'>+		const struct link_mst_stream_allocation *stream_allocation,</div><div class='add'>+		uint32_t *src,</div><div class='add'>+		uint32_t *slots);</div><div class='add'>+</div><div class='ctx'> #endif   // __DAL_DCN31_HPO_LINK_ENCODER_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c<br/>index 45143459eedd..759b453385c4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c</a></div><div class='hunk'>@@ -323,7 +323,7 @@ static void dcn31_hpo_dp_stream_enc_set_stream_attribute(</div><div class='ctx'> 		break;</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:</div><div class='ctx'> 	case COLOR_SPACE_2020_RGB_FULLRANGE:</div><div class='del'>-	case COLOR_SPACE_2020_YCBCR:</div><div class='add'>+	case COLOR_SPACE_2020_YCBCR_LIMITED:</div><div class='ctx'> 	case COLOR_SPACE_XR_RGB:</div><div class='ctx'> 	case COLOR_SPACE_MSREF_SCRGB:</div><div class='ctx'> 	case COLOR_SPACE_ADOBERGB:</div><div class='hunk'>@@ -336,6 +336,7 @@ static void dcn31_hpo_dp_stream_enc_set_stream_attribute(</div><div class='ctx'> 	case COLOR_SPACE_CUSTOMPOINTS:</div><div class='ctx'> 	case COLOR_SPACE_UNKNOWN:</div><div class='ctx'> 	case COLOR_SPACE_YCBCR709_BLACK:</div><div class='add'>+	default:</div><div class='ctx'> 		/* do nothing */</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -474,6 +475,10 @@ static void dcn31_hpo_dp_stream_enc_update_dp_info_packets(</div><div class='ctx'> 				&amp;info_frame-&gt;hdrsmd,</div><div class='ctx'> 				true);</div><div class='ctx'> </div><div class='add'>+	/* packetIndex 4 is used for send immediate sdp message, and please</div><div class='add'>+	 * use other packetIndex (such as 5,6) for other info packet</div><div class='add'>+	 */</div><div class='add'>+</div><div class='ctx'> 	if (info_frame-&gt;adaptive_sync.valid)</div><div class='ctx'> 		enc-&gt;vpg-&gt;funcs-&gt;update_generic_info_packet(</div><div class='ctx'> 				enc-&gt;vpg,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h<br/>index 82c3b3ac1f0d..82c3b3ac1f0d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c<br/>index 8af01f579690..de3ec4fcade2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.c</a></div><div class='hunk'>@@ -41,7 +41,7 @@</div><div class='ctx'> #define CTX \</div><div class='ctx'> 	enc3-&gt;base.ctx</div><div class='ctx'> </div><div class='del'>-static bool dcn32_hpo_dp_link_enc_is_in_alt_mode(</div><div class='add'>+bool dcn32_hpo_dp_link_enc_is_in_alt_mode(</div><div class='ctx'> 		struct hpo_dp_link_encoder *enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h<br/>index 176b1537d2a1..bea4e1a8ff90 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hpo_dp_link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hpo/dcn32/dcn32_hpo_dp_link_encoder.h</a></div><div class='hunk'>@@ -54,6 +54,7 @@</div><div class='ctx'> 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\</div><div class='ctx'> 	SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)</div><div class='ctx'> </div><div class='add'>+bool dcn32_hpo_dp_link_enc_is_in_alt_mode(struct hpo_dp_link_encoder *enc);</div><div class='ctx'> void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,</div><div class='ctx'> 	struct dc_context *ctx,</div><div class='ctx'> 	uint32_t inst,</div><div class='hunk'>@@ -61,4 +62,7 @@ void hpo_dp_link_encoder32_construct(struct dcn31_hpo_dp_link_encoder *enc31,</div><div class='ctx'> 	const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,</div><div class='ctx'> 	const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask);</div><div class='ctx'> </div><div class='add'>+bool dcn32_hpo_dp_link_enc_is_in_alt_mode(</div><div class='add'>+		struct hpo_dp_link_encoder *enc);</div><div class='add'>+</div><div class='ctx'> #endif   // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile<br/>new file mode 100644<br/>index 000000000000..66ca5a6a0415<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/Makefile</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+</div><div class='add'>+# Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'hubbub' sub-component of DAL.</div><div class='add'>+#</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBBUB_DCN10 = dcn10_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN10 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn10/,$(HUBBUB_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN10)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBBUB_DCN20 = dcn20_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN20 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn20/,$(HUBBUB_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBBUB_DCN201 = dcn201_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN201 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn201/,$(HUBBUB_DCN201))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN201)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBBUB_DCN21 = dcn21_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN21 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn21/,$(HUBBUB_DCN21))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN21)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+HUBBUB_DCN30 = dcn30_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN30 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn30/,$(HUBBUB_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+HUBBUB_DCN301 = dcn301_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN301 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn301/,$(HUBBUB_DCN301))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN301)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBBUB_DCN31 = dcn31_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN31 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn31/,$(HUBBUB_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN31)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+HUBBUB_DCN32 = dcn32_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN32 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn32/,$(HUBBUB_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBBUB_DCN35 = dcn35_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN35 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn35/,$(HUBBUB_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+HUBBUB_DCN401 = dcn401_hubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBBUB_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn401/,$(HUBBUB_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN401)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c<br/>index d51f1ce02874..7847c1c4927b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "dm_services.h"</div><div class='del'>-#include "dcn10_hubp.h"</div><div class='add'>+#include "dcn10/dcn10_hubp.h"</div><div class='ctx'> #include "dcn10_hubbub.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> </div><div class='hunk'>@@ -130,7 +130,7 @@ bool hubbub1_verify_allow_pstate_change_high(</div><div class='ctx'> 	static unsigned int max_sampled_pstate_wait_us; /* data collection */</div><div class='ctx'> 	static bool forced_pstate_allow; /* help with revert wa */</div><div class='ctx'> </div><div class='del'>-	unsigned int debug_data;</div><div class='add'>+	unsigned int debug_data = 0;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	if (forced_pstate_allow) {</div><div class='hunk'>@@ -242,7 +242,7 @@ void hubbub1_wm_change_req_wa(struct hubbub *hubbub)</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -356,7 +356,7 @@ bool hubbub1_program_urgent_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -501,7 +501,7 @@ bool hubbub1_program_stutter_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -582,7 +582,7 @@ bool hubbub1_program_pstate_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -679,24 +679,6 @@ void hubbub1_update_dchub(</div><div class='ctx'> 	dh_data-&gt;dchub_info_valid = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)</div><div class='del'>-{</div><div class='del'>-	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);</div><div class='del'>-</div><div class='del'>-	uint32_t watermark_change_req;</div><div class='del'>-</div><div class='del'>-	REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,</div><div class='del'>-			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &amp;watermark_change_req);</div><div class='del'>-</div><div class='del'>-	if (watermark_change_req)</div><div class='del'>-		watermark_change_req = 0;</div><div class='del'>-	else</div><div class='del'>-		watermark_change_req = 1;</div><div class='del'>-</div><div class='del'>-	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,</div><div class='del'>-			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h<br/>index 4201b7627030..fa5c4c18ed59 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h</a></div><div class='hunk'>@@ -178,6 +178,29 @@ struct dcn_hubbub_registers {</div><div class='ctx'> 	uint32_t DCHUBBUB_CLOCK_CNTL;</div><div class='ctx'> 	uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL;</div><div class='ctx'> 	uint32_t DCHUBBUB_ARB_QOS_FORCE;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;</div><div class='add'>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B;</div><div class='add'>+	uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL1;</div><div class='add'>+	uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL2;</div><div class='add'>+	uint32_t DCHUBBUB_CTRL_STATUS;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define HUBBUB_REG_FIELD_LIST_DCN32(type) \</div><div class='hunk'>@@ -200,7 +223,7 @@ struct dcn_hubbub_registers {</div><div class='ctx'> 		type MALL_PREFETCH_COMPLETE;\</div><div class='ctx'> 		type MALL_IN_USE</div><div class='ctx'> </div><div class='del'>- #define HUBBUB_REG_FIELD_LIST_DCN35(type) \</div><div class='add'>+#define HUBBUB_REG_FIELD_LIST_DCN35(type) \</div><div class='ctx'> 		type DCHUBBUB_FGCG_REP_DIS;\</div><div class='ctx'> 		type DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE</div><div class='ctx'> </div><div class='hunk'>@@ -293,7 +316,17 @@ struct dcn_hubbub_registers {</div><div class='ctx'> 		type DCN_VM_ERROR_VMID;\</div><div class='ctx'> 		type DCN_VM_ERROR_TABLE_LEVEL;\</div><div class='ctx'> 		type DCN_VM_ERROR_PIPE;\</div><div class='del'>-		type DCN_VM_ERROR_INTERRUPT_STATUS</div><div class='add'>+		type DCN_VM_ERROR_INTERRUPT_STATUS;\</div><div class='add'>+		type DCHUBBUB_TIMEOUT_ERROR_STATUS;\</div><div class='add'>+		type DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD;\</div><div class='add'>+		type DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD;\</div><div class='add'>+		type DCHUBBUB_TIMEOUT_DETECTION_EN;\</div><div class='add'>+		type DCHUBBUB_TIMEOUT_TIMER_RESET;\</div><div class='add'>+		type ROB_UNDERFLOW_STATUS;\</div><div class='add'>+		type ROB_OVERFLOW_STATUS;\</div><div class='add'>+		type ROB_OVERFLOW_CLEAR;\</div><div class='add'>+		type DCHUBBUB_HW_DEBUG;\</div><div class='add'>+		type CSTATE_SWATH_CHK_GOOD_MODE</div><div class='ctx'> </div><div class='ctx'> #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \</div><div class='ctx'> 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\</div><div class='hunk'>@@ -305,6 +338,7 @@ struct dcn_hubbub_registers {</div><div class='ctx'> 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\</div><div class='ctx'> 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> #define HUBBUB_HVM_REG_FIELD_LIST(type) \</div><div class='ctx'> 		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\</div><div class='ctx'> 		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\</div><div class='hunk'>@@ -383,6 +417,28 @@ struct dcn_hubbub_registers {</div><div class='ctx'> 		type DET_MEM_PWR_LS_MODE</div><div class='ctx'> </div><div class='ctx'> </div><div class='add'>+#define HUBBUB_REG_FIELD_LIST_DCN4_01(type) \</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B;\</div><div class='add'>+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B;\</div><div class='add'>+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A;\</div><div class='add'>+		type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B;\</div><div class='add'>+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A;\</div><div class='add'>+		type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B;\</div><div class='add'>+		type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;\</div><div class='add'>+		type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;\</div><div class='add'>+		type DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;\</div><div class='add'>+		type DCHUBBUB_ARB_FRAC_URG_BW_MALL_B</div><div class='add'>+</div><div class='ctx'> struct dcn_hubbub_shift {</div><div class='ctx'> 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);</div><div class='hunk'>@@ -390,6 +446,7 @@ struct dcn_hubbub_shift {</div><div class='ctx'> 	HUBBUB_RET_REG_FIELD_LIST(uint8_t);</div><div class='ctx'> 	HUBBUB_REG_FIELD_LIST_DCN32(uint8_t);</div><div class='ctx'> 	HUBBUB_REG_FIELD_LIST_DCN35(uint8_t);</div><div class='add'>+	HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn_hubbub_mask {</div><div class='hunk'>@@ -399,6 +456,7 @@ struct dcn_hubbub_mask {</div><div class='ctx'> 	HUBBUB_RET_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> 	HUBBUB_REG_FIELD_LIST_DCN32(uint32_t);</div><div class='ctx'> 	HUBBUB_REG_FIELD_LIST_DCN35(uint32_t);</div><div class='add'>+	HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc;</div><div class='hunk'>@@ -409,7 +467,7 @@ struct dcn10_hubbub {</div><div class='ctx'> 	const struct dcn_hubbub_shift *shifts;</div><div class='ctx'> 	const struct dcn_hubbub_mask *masks;</div><div class='ctx'> 	unsigned int debug_test_index_pstate;</div><div class='del'>-	struct dcn_watermark_set watermarks;</div><div class='add'>+	union dcn_watermark_set watermarks;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void hubbub1_update_dchub(</div><div class='hunk'>@@ -423,7 +481,7 @@ void hubbub1_wm_change_req_wa(struct hubbub *hubbub);</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='hunk'>@@ -431,9 +489,6 @@ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);</div><div class='ctx'> </div><div class='del'>-void hubbub1_toggle_watermark_change_req(</div><div class='del'>-		struct hubbub *hubbub);</div><div class='del'>-</div><div class='ctx'> void hubbub1_wm_read_state(struct hubbub *hubbub,</div><div class='ctx'> 		struct dcn_hubbub_wm *wm);</div><div class='ctx'> </div><div class='hunk'>@@ -446,17 +501,17 @@ void hubbub1_construct(struct hubbub *hubbub,</div><div class='ctx'> </div><div class='ctx'> bool hubbub1_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> bool hubbub1_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> bool hubbub1_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c<br/>index 6eebcb22e317..5c6f7ddafd6b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c</a></div><div class='hunk'>@@ -339,15 +339,36 @@ static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigne</div><div class='ctx'> 	case 4096:</div><div class='ctx'> 		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;</div><div class='ctx'> 		break;</div><div class='del'>-	case 65536:</div><div class='del'>-		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;</div><div class='add'>+	case 8192:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_8KB;</div><div class='add'>+		break;</div><div class='add'>+	case 16384:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_16KB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 32768:</div><div class='ctx'> 		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_32KB;</div><div class='ctx'> 		break;</div><div class='add'>+	case 65536:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;</div><div class='add'>+		break;</div><div class='add'>+	case 131072:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_128KB;</div><div class='add'>+		break;</div><div class='add'>+	case 262144:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_256KB;</div><div class='add'>+		break;</div><div class='add'>+	case 524288:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_512KB;</div><div class='add'>+		break;</div><div class='add'>+	case 1048576:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_1024KB;</div><div class='add'>+		break;</div><div class='add'>+	case 2097152:</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_2048KB;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT(false);</div><div class='del'>-		block_size = page_table_block_size;</div><div class='add'>+		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -570,7 +591,7 @@ void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,</div><div class='ctx'> </div><div class='ctx'> static bool hubbub2_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -595,7 +616,8 @@ static bool hubbub2_program_watermarks(</div><div class='ctx'> 		hubbub1-&gt;base.ctx-&gt;dc-&gt;clk_mgr-&gt;clks.p_state_change_support == false)</div><div class='ctx'> 		safe_to_lower = true;</div><div class='ctx'> </div><div class='del'>-	hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);</div><div class='add'>+	if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))</div><div class='add'>+		wm_pending = true;</div><div class='ctx'> </div><div class='ctx'> 	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,</div><div class='ctx'> 			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h<br/>index 2f6146bf1d32..46d8f5c70750 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> #define __DC_HUBBUB_DCN20_H__</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_hubbub.h"</div><div class='del'>-#include "dcn20_vmid.h"</div><div class='add'>+#include "dcn20/dcn20_vmid.h"</div><div class='ctx'> </div><div class='ctx'> #define TO_DCN20_HUBBUB(hubbub)\</div><div class='ctx'> 	container_of(hubbub, struct dcn20_hubbub, base)</div><div class='hunk'>@@ -85,7 +85,7 @@ struct dcn20_hubbub {</div><div class='ctx'> 	const struct dcn_hubbub_shift *shifts;</div><div class='ctx'> 	const struct dcn_hubbub_mask *masks;</div><div class='ctx'> 	unsigned int debug_test_index_pstate;</div><div class='del'>-	struct dcn_watermark_set watermarks;</div><div class='add'>+	union dcn_watermark_set watermarks;</div><div class='ctx'> 	int num_vmid;</div><div class='ctx'> 	struct dcn20_vmid vmid[16];</div><div class='ctx'> 	unsigned int detile_buf_size;</div><div class='hunk'>@@ -96,6 +96,7 @@ struct dcn20_hubbub {</div><div class='ctx'> 	unsigned int det1_size;</div><div class='ctx'> 	unsigned int det2_size;</div><div class='ctx'> 	unsigned int det3_size;</div><div class='add'>+	bool allow_sdpif_rate_limit_when_cstate_req;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void hubbub2_construct(struct dcn20_hubbub *hubbub,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c<br/>index 037d265431c6..63798132ed95 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c</a></div><div class='hunk'>@@ -52,7 +52,7 @@</div><div class='ctx'> </div><div class='ctx'> static bool hubbub201_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -103,5 +103,5 @@ void hubbub201_construct(struct dcn20_hubbub *hubbub,</div><div class='ctx'> 	hubbub-&gt;masks = hubbub_mask;</div><div class='ctx'> </div><div class='ctx'> 	hubbub-&gt;debug_test_index_pstate = 0xB;</div><div class='del'>-	hubbub-&gt;detile_buf_size = 164 * 1024;</div><div class='add'>+	hubbub-&gt;detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.h<br/>index 5aeca0be3e15..5aeca0be3e15 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c<br/>index aeb0e0d9b70a..e4496ad203b2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c</a></div><div class='hunk'>@@ -132,15 +132,15 @@ int hubbub21_init_dchub(struct hubbub *hubbub,</div><div class='ctx'> 		// Init VMID 0 based on PA config</div><div class='ctx'> 		dcn20_vmid_setup(&amp;hubbub1-&gt;vmid[0], &amp;phys_config);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	dcn21_dchvm_init(hubbub);</div><div class='del'>-</div><div class='add'>+	if (!hubbub1-&gt;base.ctx-&gt;dc-&gt;config.skip_riommu_prefetch_wa) {</div><div class='add'>+		dcn21_dchvm_init(hubbub);</div><div class='add'>+	}</div><div class='ctx'> 	return hubbub1-&gt;num_vmid;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool hubbub21_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -334,7 +334,7 @@ bool hubbub21_program_urgent_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub21_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -487,7 +487,7 @@ bool hubbub21_program_stutter_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub21_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -573,7 +573,7 @@ bool hubbub21_program_pstate_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub21_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h<br/>index d8eb2bb7282c..ab2ce0313529 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.h</a></div><div class='hunk'>@@ -127,22 +127,22 @@ int hubbub21_init_dchub(struct hubbub *hubbub,</div><div class='ctx'> 		struct dcn_hubbub_phys_addr_config *pa_config);</div><div class='ctx'> bool hubbub21_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> bool hubbub21_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> bool hubbub21_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> bool hubbub21_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c<br/>index 152c9c5733f1..181a93dc46e6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c</a></div><div class='hunk'>@@ -95,7 +95,7 @@ int hubbub3_init_dchub_sys_ctx(struct hubbub *hubbub,</div><div class='ctx'> </div><div class='ctx'> bool hubbub3_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -129,7 +129,8 @@ bool hubbub3_program_watermarks(</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,</div><div class='ctx'> 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);</div><div class='ctx'> </div><div class='del'>-	hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='add'>+	if (safe_to_lower || hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter)</div><div class='add'>+		hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='ctx'> </div><div class='ctx'> 	return wm_pending;</div><div class='ctx'> }</div><div class='hunk'>@@ -339,6 +340,7 @@ bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	switch (dcc_control) {</div><div class='add'>+	case dcc_control__256_256:</div><div class='ctx'> 	case dcc_control__256_256_xxx:</div><div class='ctx'> 		output-&gt;grph.rgb.max_uncompressed_blk_size = 256;</div><div class='ctx'> 		output-&gt;grph.rgb.max_compressed_blk_size = 256;</div><div class='hunk'>@@ -346,6 +348,7 @@ bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='ctx'> 		output-&gt;grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;</div><div class='ctx'> 		output-&gt;grph.rgb.dcc_controls.dcc_256_128_128 = 1;</div><div class='ctx'> 		break;</div><div class='add'>+	case dcc_control__256_128:</div><div class='ctx'> 	case dcc_control__128_128_xxx:</div><div class='ctx'> 		output-&gt;grph.rgb.max_uncompressed_blk_size = 128;</div><div class='ctx'> 		output-&gt;grph.rgb.max_compressed_blk_size = 128;</div><div class='hunk'>@@ -353,6 +356,7 @@ bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='ctx'> 		output-&gt;grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;</div><div class='ctx'> 		output-&gt;grph.rgb.dcc_controls.dcc_256_128_128 = 1;</div><div class='ctx'> 		break;</div><div class='add'>+	case dcc_control__256_64:</div><div class='ctx'> 	case dcc_control__256_64_64:</div><div class='ctx'> 		output-&gt;grph.rgb.max_uncompressed_blk_size = 256;</div><div class='ctx'> 		output-&gt;grph.rgb.max_compressed_blk_size = 64;</div><div class='hunk'>@@ -436,6 +440,17 @@ void hubbub3_init_watermarks(struct hubbub *hubbub)</div><div class='ctx'> 	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	hubbub_reg_state-&gt;det0_ctrl = REG_READ(DCHUBBUB_DET0_CTRL);</div><div class='add'>+	hubbub_reg_state-&gt;det1_ctrl = REG_READ(DCHUBBUB_DET1_CTRL);</div><div class='add'>+	hubbub_reg_state-&gt;det2_ctrl = REG_READ(DCHUBBUB_DET2_CTRL);</div><div class='add'>+	hubbub_reg_state-&gt;det3_ctrl = REG_READ(DCHUBBUB_DET3_CTRL);</div><div class='add'>+	hubbub_reg_state-&gt;compbuf_ctrl = REG_READ(DCHUBBUB_COMPBUF_CTRL);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct hubbub_funcs hubbub30_funcs = {</div><div class='ctx'> 	.update_dchub = hubbub2_update_dchub,</div><div class='ctx'> 	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,</div><div class='hunk'>@@ -453,6 +468,7 @@ static const struct hubbub_funcs hubbub30_funcs = {</div><div class='ctx'> 	.force_pstate_change_control = hubbub3_force_pstate_change_control,</div><div class='ctx'> 	.init_watermarks = hubbub3_init_watermarks,</div><div class='ctx'> 	.hubbub_read_state = hubbub2_read_state,</div><div class='add'>+	.hubbub_read_reg_state = hubbub3_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void hubbub3_construct(struct dcn20_hubbub *hubbub3,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h<br/>index 7b597908b937..9e14de3ccaee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h</a></div><div class='hunk'>@@ -124,7 +124,7 @@ bool hubbub3_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='ctx'> </div><div class='ctx'> bool hubbub3_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='hunk'>@@ -133,4 +133,6 @@ void hubbub3_force_pstate_change_control(struct hubbub *hubbub,</div><div class='ctx'> </div><div class='ctx'> void hubbub3_init_watermarks(struct hubbub *hubbub);</div><div class='ctx'> </div><div class='add'>+void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c<br/>index a046664e2031..c1959672df50 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.c</a></div><div class='hunk'>@@ -63,6 +63,7 @@ static const struct hubbub_funcs hubbub301_funcs = {</div><div class='ctx'> 	.verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high,</div><div class='ctx'> 	.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,</div><div class='ctx'> 	.force_pstate_change_control = hubbub3_force_pstate_change_control,</div><div class='add'>+	.init_watermarks = hubbub3_init_watermarks,</div><div class='ctx'> 	.hubbub_read_state = hubbub2_read_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.h<br/>index b599f4475479..b599f4475479 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn301/dcn301_hubbub.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c<br/>index 5b5b5e0775fa..5a03758e3de6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c</a></div><div class='hunk'>@@ -172,7 +172,7 @@ static uint32_t convert_and_clamp(</div><div class='ctx'> </div><div class='ctx'> static bool hubbub31_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -362,7 +362,7 @@ static bool hubbub31_program_urgent_watermarks(</div><div class='ctx'> </div><div class='ctx'> static bool hubbub31_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -635,7 +635,7 @@ static bool hubbub31_program_stutter_watermarks(</div><div class='ctx'> </div><div class='ctx'> static bool hubbub31_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -717,7 +717,7 @@ static bool hubbub31_program_pstate_watermarks(</div><div class='ctx'> </div><div class='ctx'> static bool hubbub31_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -750,7 +750,8 @@ static bool hubbub31_program_watermarks(</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,</div><div class='ctx'> 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/</div><div class='ctx'> </div><div class='del'>-	hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='add'>+	if (safe_to_lower || hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter)</div><div class='add'>+		hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='ctx'> 	return wm_pending;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -866,6 +867,7 @@ static bool hubbub31_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	switch (dcc_control) {</div><div class='add'>+	case dcc_control__256_256:</div><div class='ctx'> 	case dcc_control__256_256_xxx:</div><div class='ctx'> 		output-&gt;grph.rgb.max_uncompressed_blk_size = 256;</div><div class='ctx'> 		output-&gt;grph.rgb.max_compressed_blk_size = 256;</div><div class='hunk'>@@ -881,12 +883,14 @@ static bool hubbub31_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='ctx'> 		output-&gt;grph.rgb.dcc_controls.dcc_256_128_128 = 1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case dcc_control__256_64_64:</div><div class='add'>+	case dcc_control__256_64:</div><div class='ctx'> 		output-&gt;grph.rgb.max_uncompressed_blk_size = 256;</div><div class='ctx'> 		output-&gt;grph.rgb.max_compressed_blk_size = 64;</div><div class='ctx'> 		output-&gt;grph.rgb.independent_64b_blks = true;</div><div class='ctx'> 		output-&gt;grph.rgb.dcc_controls.dcc_256_64_64 = 1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case dcc_control__256_128_128:</div><div class='add'>+	case dcc_control__256_128:</div><div class='ctx'> 		output-&gt;grph.rgb.max_uncompressed_blk_size = 256;</div><div class='ctx'> 		output-&gt;grph.rgb.max_compressed_blk_size = 128;</div><div class='ctx'> 		output-&gt;grph.rgb.independent_64b_blks = false;</div><div class='hunk'>@@ -929,8 +933,8 @@ int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,</div><div class='ctx'> </div><div class='ctx'> 		dcn20_vmid_setup(&amp;hubbub2-&gt;vmid[15], &amp;phys_config);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	dcn21_dchvm_init(hubbub);</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;dchvm_init)</div><div class='add'>+		hubbub-&gt;funcs-&gt;dchvm_init(hubbub);</div><div class='ctx'> </div><div class='ctx'> 	return NUM_VMID;</div><div class='ctx'> }</div><div class='hunk'>@@ -1067,6 +1071,8 @@ static const struct hubbub_funcs hubbub31_funcs = {</div><div class='ctx'> 	.program_compbuf_size = dcn31_program_compbuf_size,</div><div class='ctx'> 	.init_crb = dcn31_init_crb,</div><div class='ctx'> 	.hubbub_read_state = hubbub2_read_state,</div><div class='add'>+	.hubbub_read_reg_state = hubbub3_read_reg_state,</div><div class='add'>+	.dchvm_init  = dcn21_dchvm_init</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void hubbub31_construct(struct dcn20_hubbub *hubbub31,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h<br/>index 89d6208287b5..89d6208287b5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c<br/>index 88dfc907553d..237331b35378 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #include "dcn32_hubbub.h"</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='add'>+#include "dal_asic_id.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #define CTX \</div><div class='hunk'>@@ -72,6 +73,14 @@ static void dcn32_init_crb(struct hubbub *hubbub)</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void hubbub32_set_sdp_control(struct hubbub *hubbub, bool dc_control)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBBUB_SDPIF_CFG0,</div><div class='add'>+			SDPIF_PORT_CONTROL, dc_control);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hubbub32_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='hunk'>@@ -128,7 +137,7 @@ void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int d</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)</div><div class='add'>+void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='ctx'> 	unsigned int compbuf_size_segments = (compbuf_size_kb + DCN32_CRB_SEGMENT_SIZE_KB - 1) / DCN32_CRB_SEGMENT_SIZE_KB;</div><div class='hunk'>@@ -167,7 +176,7 @@ static uint32_t convert_and_clamp(</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -357,7 +366,7 @@ bool hubbub32_program_urgent_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -503,7 +512,7 @@ bool hubbub32_program_stutter_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -656,7 +665,7 @@ bool hubbub32_program_pstate_watermarks(</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_usr_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -750,12 +759,22 @@ void hubbub32_force_usr_retraining_allow(struct hubbub *hubbub, bool allow)</div><div class='ctx'> </div><div class='ctx'> static bool hubbub32_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='add'>+	struct dc *dc = hubbub-&gt;ctx-&gt;dc;</div><div class='ctx'> 	bool wm_pending = false;</div><div class='ctx'> </div><div class='add'>+	if (!safe_to_lower &amp;&amp; dc-&gt;debug.disable_stutter_for_wm_program &amp;&amp;</div><div class='add'>+			(ASICREV_IS_GC_11_0_0(dc-&gt;ctx-&gt;asic_id.hw_internal_rev) ||</div><div class='add'>+			ASICREV_IS_GC_11_0_3(dc-&gt;ctx-&gt;asic_id.hw_internal_rev))) {</div><div class='add'>+		/* before raising watermarks, SDP control give to DF, stutter must be disabled */</div><div class='add'>+		wm_pending = true;</div><div class='add'>+		hubbub32_set_sdp_control(hubbub, false);</div><div class='add'>+		hubbub1_allow_self_refresh_control(hubbub, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))</div><div class='ctx'> 		wm_pending = true;</div><div class='ctx'> </div><div class='hunk'>@@ -786,9 +805,20 @@ static bool hubbub32_program_watermarks(</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,</div><div class='ctx'> 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/</div><div class='ctx'> </div><div class='del'>-	hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='add'>+	if (safe_to_lower) {</div><div class='add'>+		/* after lowering watermarks, stutter setting is restored, SDP control given to DC */</div><div class='add'>+		hubbub1_allow_self_refresh_control(hubbub, !dc-&gt;debug.disable_stutter);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;debug.disable_stutter_for_wm_program &amp;&amp;</div><div class='add'>+				(ASICREV_IS_GC_11_0_0(dc-&gt;ctx-&gt;asic_id.hw_internal_rev) ||</div><div class='add'>+				ASICREV_IS_GC_11_0_3(dc-&gt;ctx-&gt;asic_id.hw_internal_rev))) {</div><div class='add'>+			hubbub32_set_sdp_control(hubbub, true);</div><div class='add'>+		}</div><div class='add'>+	} else if (dc-&gt;debug.disable_stutter) {</div><div class='add'>+		hubbub1_allow_self_refresh_control(hubbub, !dc-&gt;debug.disable_stutter);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	hubbub32_force_usr_retraining_allow(hubbub, hubbub-&gt;ctx-&gt;dc-&gt;debug.force_usr_allow);</div><div class='add'>+	hubbub32_force_usr_retraining_allow(hubbub, dc-&gt;debug.force_usr_allow);</div><div class='ctx'> </div><div class='ctx'> 	return wm_pending;</div><div class='ctx'> }</div><div class='hunk'>@@ -973,8 +1003,7 @@ void hubbub32_init(struct hubbub *hubbub)</div><div class='ctx'> 	ignore the "df_pre_cstate_req" from the SDP port control.</div><div class='ctx'> 	only the DCN will determine when to connect the SDP port</div><div class='ctx'> 	*/</div><div class='del'>-	REG_UPDATE(DCHUBBUB_SDPIF_CFG0,</div><div class='del'>-			SDPIF_PORT_CONTROL, 1);</div><div class='add'>+	hubbub32_set_sdp_control(hubbub, true);</div><div class='ctx'> 	/*Set SDP's max outstanding request to 512</div><div class='ctx'> 	must set the register back to 0 (max outstanding = 256) in zero frame buffer mode*/</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_SDPIF_CFG1,</div><div class='hunk'>@@ -1008,6 +1037,7 @@ static const struct hubbub_funcs hubbub32_funcs = {</div><div class='ctx'> 	.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,</div><div class='ctx'> 	.set_request_limit = hubbub32_set_request_limit,</div><div class='ctx'> 	.get_mall_en = hubbub32_get_mall_en,</div><div class='add'>+	.hubbub_read_reg_state = hubbub3_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void hubbub32_construct(struct dcn20_hubbub *hubbub2,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h<br/>index f073839a4b6d..bfc55dbbad1f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.h</a></div><div class='hunk'>@@ -118,25 +118,25 @@</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_urgent_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_stutter_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_pstate_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='ctx'> bool hubbub32_program_usr_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower);</div><div class='ctx'> </div><div class='hunk'>@@ -161,4 +161,6 @@ void hubbub32_set_request_limit(struct hubbub *hubbub, int umc_count, int words_</div><div class='ctx'> </div><div class='ctx'> void hubbub32_get_mall_en(struct hubbub *hubbub, unsigned int *mall_in_use);</div><div class='ctx'> </div><div class='add'>+void dcn32_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c<br/>index 339bf0c722dd..43ba399f4822 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c</a></div><div class='hunk'>@@ -46,7 +46,7 @@</div><div class='ctx'> </div><div class='ctx'> #define DCN35_CRB_SEGMENT_SIZE_KB 64</div><div class='ctx'> </div><div class='del'>-static void dcn35_init_crb(struct hubbub *hubbub)</div><div class='add'>+void dcn35_init_crb(struct hubbub *hubbub)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='ctx'> </div><div class='hunk'>@@ -71,7 +71,7 @@ static void dcn35_init_crb(struct hubbub *hubbub)</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x5FF);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn35_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)</div><div class='add'>+void dcn35_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='ctx'> 	unsigned int compbuf_size_segments = (compbuf_size_kb + DCN35_CRB_SEGMENT_SIZE_KB - 1) / DCN35_CRB_SEGMENT_SIZE_KB;</div><div class='hunk'>@@ -111,7 +111,7 @@ static uint32_t convert_and_clamp(</div><div class='ctx'> </div><div class='ctx'> static bool hubbub35_program_stutter_z8_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -255,7 +255,7 @@ static bool hubbub35_program_stutter_z8_watermarks(</div><div class='ctx'> 	return wm_pending;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void hubbub35_get_dchub_ref_freq(struct hubbub *hubbub,</div><div class='add'>+void hubbub35_get_dchub_ref_freq(struct hubbub *hubbub,</div><div class='ctx'> 		unsigned int dccg_ref_freq_inKhz,</div><div class='ctx'> 		unsigned int *dchub_ref_freq_inKhz)</div><div class='ctx'> {</div><div class='hunk'>@@ -295,9 +295,9 @@ static void hubbub35_get_dchub_ref_freq(struct hubbub *hubbub,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static bool hubbub35_program_watermarks(</div><div class='add'>+bool hubbub35_program_watermarks(</div><div class='ctx'> 		struct hubbub *hubbub,</div><div class='del'>-		struct dcn_watermark_set *watermarks,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='ctx'> 		unsigned int refclk_mhz,</div><div class='ctx'> 		bool safe_to_lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -326,7 +326,8 @@ static bool hubbub35_program_watermarks(</div><div class='ctx'> 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);</div><div class='ctx'> </div><div class='del'>-	hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='add'>+	if (safe_to_lower || hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter)</div><div class='add'>+		hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='ctx'> </div><div class='ctx'> 	hubbub32_force_usr_retraining_allow(hubbub, hubbub-&gt;ctx-&gt;dc-&gt;debug.force_usr_allow);</div><div class='ctx'> </div><div class='hunk'>@@ -334,7 +335,7 @@ static bool hubbub35_program_watermarks(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Copy values from WM set A to all other sets */</div><div class='del'>-static void hubbub35_init_watermarks(struct hubbub *hubbub)</div><div class='add'>+void hubbub35_init_watermarks(struct hubbub *hubbub)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='ctx'> 	uint32_t reg;</div><div class='hunk'>@@ -396,7 +397,7 @@ static void hubbub35_init_watermarks(struct hubbub *hubbub)</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void hubbub35_wm_read_state(struct hubbub *hubbub,</div><div class='add'>+void hubbub35_wm_read_state(struct hubbub *hubbub,</div><div class='ctx'> 		struct dcn_hubbub_wm *wm)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='hunk'>@@ -513,7 +514,7 @@ static void hubbub35_set_fgcg(struct dcn20_hubbub *hubbub2, bool enable)</div><div class='ctx'> 	REG_UPDATE(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, !enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void hubbub35_init(struct hubbub *hubbub)</div><div class='add'>+void hubbub35_init(struct hubbub *hubbub)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='ctx'> 	/*Enable clock gaters*/</div><div class='hunk'>@@ -545,6 +546,56 @@ static void hubbub35_init(struct hubbub *hubbub)</div><div class='ctx'> 			DCHUBBUB_ARB_MAX_REQ_OUTSTAND, 256,</div><div class='ctx'> 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 256);</div><div class='ctx'> </div><div class='add'>+	memset(&amp;hubbub2-&gt;watermarks.a.cstate_pstate, 0, sizeof(hubbub2-&gt;watermarks.a.cstate_pstate));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_dchvm_init(struct hubbub *hubbub)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	uint32_t riommu_active;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	//Init DCHVM block</div><div class='add'>+	REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);</div><div class='add'>+</div><div class='add'>+	//Poll until RIOMMU_ACTIVE = 1</div><div class='add'>+	for (i = 0; i &lt; 100; i++) {</div><div class='add'>+		REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &amp;riommu_active);</div><div class='add'>+</div><div class='add'>+		if (riommu_active)</div><div class='add'>+			break;</div><div class='add'>+		else</div><div class='add'>+			udelay(5);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (riommu_active) {</div><div class='add'>+		// Disable gating and memory power requests</div><div class='add'>+		REG_UPDATE(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, 1);</div><div class='add'>+		REG_UPDATE_4(DCHVM_CLK_CTRL,</div><div class='add'>+						HVM_DISPCLK_R_GATE_DIS, 1,</div><div class='add'>+						HVM_DISPCLK_G_GATE_DIS, 1,</div><div class='add'>+						HVM_DCFCLK_R_GATE_DIS, 1,</div><div class='add'>+						HVM_DCFCLK_G_GATE_DIS, 1);</div><div class='add'>+</div><div class='add'>+		//Reflect the power status of DCHUBBUB</div><div class='add'>+		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);</div><div class='add'>+</div><div class='add'>+		//Start rIOMMU prefetching</div><div class='add'>+		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);</div><div class='add'>+</div><div class='add'>+		//Poll until HOSTVM_PREFETCH_DONE = 1</div><div class='add'>+		REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);</div><div class='add'>+</div><div class='add'>+		//Enable memory power requests</div><div class='add'>+		REG_UPDATE(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, 0);</div><div class='add'>+		// Enable dynamic clock gating</div><div class='add'>+		REG_UPDATE_4(DCHVM_CLK_CTRL,</div><div class='add'>+						HVM_DISPCLK_R_GATE_DIS, 0,</div><div class='add'>+						HVM_DISPCLK_G_GATE_DIS, 0,</div><div class='add'>+						HVM_DCFCLK_R_GATE_DIS, 0,</div><div class='add'>+						HVM_DCFCLK_G_GATE_DIS, 0);</div><div class='add'>+		hubbub-&gt;riommu_active = true;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*static void hubbub35_set_request_limit(struct hubbub *hubbub,</div><div class='hunk'>@@ -587,6 +638,8 @@ static const struct hubbub_funcs hubbub35_funcs = {</div><div class='ctx'> 	.hubbub_read_state = hubbub2_read_state,</div><div class='ctx'> 	.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,</div><div class='ctx'> 	.dchubbub_init = hubbub35_init,</div><div class='add'>+	.hubbub_read_reg_state = hubbub3_read_reg_state,</div><div class='add'>+	.dchvm_init = dcn35_dchvm_init</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void hubbub35_construct(struct dcn20_hubbub *hubbub2,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h<br/>index 54cf00ffceb8..9f65fff1bd4d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h</a></div><div class='hunk'>@@ -152,4 +152,21 @@ void hubbub35_construct(struct dcn20_hubbub *hubbub2,</div><div class='ctx'> 	int det_size_kb,</div><div class='ctx'> 	int pixel_chunk_size_kb,</div><div class='ctx'> 	int config_return_buffer_size_kb);</div><div class='add'>+</div><div class='add'>+void hubbub35_wm_read_state(struct hubbub *hubbub,</div><div class='add'>+	struct dcn_hubbub_wm *wm);</div><div class='add'>+void hubbub35_get_dchub_ref_freq(struct hubbub *hubbub,</div><div class='add'>+	unsigned int dccg_ref_freq_inKhz,</div><div class='add'>+	unsigned int *dchub_ref_freq_inKhz);</div><div class='add'>+bool hubbub35_program_watermarks(</div><div class='add'>+	struct hubbub *hubbub,</div><div class='add'>+	union dcn_watermark_set *watermarks,</div><div class='add'>+	unsigned int refclk_mhz,</div><div class='add'>+	bool safe_to_lower);</div><div class='add'>+void hubbub35_init_watermarks(struct hubbub *hubbub);</div><div class='add'>+void dcn35_program_compbuf_size(struct hubbub *hubbub,</div><div class='add'>+	unsigned int compbuf_size_kb, bool safe_to_increase);</div><div class='add'>+void dcn35_init_crb(struct hubbub *hubbub);</div><div class='add'>+void hubbub35_init(struct hubbub *hubbub);</div><div class='add'>+void dcn35_dchvm_init(struct hubbub *hubbub);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c<br/>new file mode 100644<br/>index 000000000000..d11afd1ce72a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c</a></div><div class='hunk'>@@ -0,0 +1,1271 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "dcn30/dcn30_hubbub.h"</div><div class='add'>+#include "dcn401_hubbub.h"</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	hubbub2-&gt;base.ctx</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	hubbub2-&gt;base.ctx-&gt;logger</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	hubbub2-&gt;regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	hubbub2-&gt;shifts-&gt;field_name, hubbub2-&gt;masks-&gt;field_name</div><div class='add'>+</div><div class='add'>+static void dcn401_init_crb(struct hubbub *hubbub)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,</div><div class='add'>+		&amp;hubbub2-&gt;det0_size);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,</div><div class='add'>+		&amp;hubbub2-&gt;det1_size);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,</div><div class='add'>+		&amp;hubbub2-&gt;det2_size);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,</div><div class='add'>+		&amp;hubbub2-&gt;det3_size);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,</div><div class='add'>+		&amp;hubbub2-&gt;compbuf_size_segments);</div><div class='add'>+</div><div class='add'>+	REG_SET(COMPBUF_RESERVED_SPACE, 0,</div><div class='add'>+			COMPBUF_RESERVED_SPACE_64B, hubbub2-&gt;pixel_chunk_size / 32); // 256 64Bytes</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_urgent_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	bool wm_pending = false;</div><div class='add'>+</div><div class='add'>+	/* Repeat for water mark set A and B */</div><div class='add'>+	/* clock state A */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.urgent &gt; hubbub2-&gt;watermarks.dcn4x.a.urgent) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.urgent = watermarks-&gt;dcn4x.a.urgent;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, watermarks-&gt;dcn4x.a.urgent);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.urgent, watermarks-&gt;dcn4x.a.urgent);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.urgent &lt; hubbub2-&gt;watermarks.dcn4x.a.urgent)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* determine the transfer time for a quantity of data for a particular requestor.*/</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.frac_urg_bw_flip</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_flip) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_flip = watermarks-&gt;dcn4x.a.frac_urg_bw_flip;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks-&gt;dcn4x.a.frac_urg_bw_flip);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.frac_urg_bw_flip</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_flip)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.frac_urg_bw_nom</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_nom) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_nom = watermarks-&gt;dcn4x.a.frac_urg_bw_nom;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks-&gt;dcn4x.a.frac_urg_bw_nom);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.frac_urg_bw_nom</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_nom)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.frac_urg_bw_mall</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_mall) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_mall = watermarks-&gt;dcn4x.a.frac_urg_bw_mall;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_FRAC_URG_BW_MALL_A, watermarks-&gt;dcn4x.a.frac_urg_bw_mall);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.frac_urg_bw_mall &lt; hubbub2-&gt;watermarks.dcn4x.a.frac_urg_bw_mall)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.refcyc_per_trip_to_mem &gt; hubbub2-&gt;watermarks.dcn4x.a.refcyc_per_trip_to_mem) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.refcyc_per_trip_to_mem = watermarks-&gt;dcn4x.a.refcyc_per_trip_to_mem;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, watermarks-&gt;dcn4x.a.refcyc_per_trip_to_mem);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.refcyc_per_trip_to_mem &lt; hubbub2-&gt;watermarks.dcn4x.a.refcyc_per_trip_to_mem)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.refcyc_per_meta_trip_to_mem &gt; hubbub2-&gt;watermarks.dcn4x.a.refcyc_per_meta_trip_to_mem) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.refcyc_per_meta_trip_to_mem = watermarks-&gt;dcn4x.a.refcyc_per_meta_trip_to_mem;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A, watermarks-&gt;dcn4x.a.refcyc_per_meta_trip_to_mem);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.refcyc_per_meta_trip_to_mem &lt; hubbub2-&gt;watermarks.dcn4x.a.refcyc_per_meta_trip_to_mem)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.urgent &gt; hubbub2-&gt;watermarks.dcn4x.b.urgent) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.urgent = watermarks-&gt;dcn4x.b.urgent;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, watermarks-&gt;dcn4x.b.urgent);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.urgent, watermarks-&gt;dcn4x.b.urgent);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.urgent &lt; hubbub2-&gt;watermarks.dcn4x.b.urgent)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* determine the transfer time for a quantity of data for a particular requestor.*/</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.frac_urg_bw_flip</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_flip) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_flip = watermarks-&gt;dcn4x.b.frac_urg_bw_flip;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks-&gt;dcn4x.b.frac_urg_bw_flip);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.frac_urg_bw_flip</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_flip)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.frac_urg_bw_nom</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_nom) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_nom = watermarks-&gt;dcn4x.b.frac_urg_bw_nom;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks-&gt;dcn4x.b.frac_urg_bw_nom);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.frac_urg_bw_nom</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_nom)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.frac_urg_bw_mall</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_mall) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_mall = watermarks-&gt;dcn4x.b.frac_urg_bw_mall;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, watermarks-&gt;dcn4x.b.frac_urg_bw_mall);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.frac_urg_bw_mall &lt; hubbub2-&gt;watermarks.dcn4x.b.frac_urg_bw_mall)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.refcyc_per_trip_to_mem &gt; hubbub2-&gt;watermarks.dcn4x.b.refcyc_per_trip_to_mem) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.refcyc_per_trip_to_mem = watermarks-&gt;dcn4x.b.refcyc_per_trip_to_mem;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, watermarks-&gt;dcn4x.b.refcyc_per_trip_to_mem);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.refcyc_per_trip_to_mem &lt; hubbub2-&gt;watermarks.dcn4x.b.refcyc_per_trip_to_mem)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.refcyc_per_meta_trip_to_mem &gt; hubbub2-&gt;watermarks.dcn4x.b.refcyc_per_meta_trip_to_mem) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.refcyc_per_meta_trip_to_mem = watermarks-&gt;dcn4x.b.refcyc_per_meta_trip_to_mem;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, watermarks-&gt;dcn4x.b.refcyc_per_meta_trip_to_mem);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.refcyc_per_meta_trip_to_mem &lt; hubbub2-&gt;watermarks.dcn4x.b.refcyc_per_meta_trip_to_mem)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	return wm_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_stutter_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	bool wm_pending = false;</div><div class='add'>+</div><div class='add'>+	/* clock state A */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.sr_enter</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.sr_enter) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.sr_enter =</div><div class='add'>+				watermarks-&gt;dcn4x.a.sr_enter;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, watermarks-&gt;dcn4x.a.sr_enter);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.sr_enter, watermarks-&gt;dcn4x.a.sr_enter);</div><div class='add'>+		// On dGPU Z states are N/A, so program all other 3 Stutter Enter wm A with the same value</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, watermarks-&gt;dcn4x.a.sr_enter);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, watermarks-&gt;dcn4x.a.sr_enter);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, watermarks-&gt;dcn4x.a.sr_enter);</div><div class='add'>+</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.sr_enter</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.sr_enter)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.sr_exit</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.sr_exit) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.sr_exit =</div><div class='add'>+				watermarks-&gt;dcn4x.a.sr_exit;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, watermarks-&gt;dcn4x.a.sr_exit);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.sr_exit, watermarks-&gt;dcn4x.a.sr_exit);</div><div class='add'>+		// On dGPU Z states are N/A, so program all other 3 Stutter Exit wm A with the same value</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, watermarks-&gt;dcn4x.a.sr_exit);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, watermarks-&gt;dcn4x.a.sr_exit);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, watermarks-&gt;dcn4x.a.sr_exit);</div><div class='add'>+</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.sr_exit</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.sr_exit)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.sr_enter</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.sr_enter) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.sr_enter =</div><div class='add'>+				watermarks-&gt;dcn4x.b.sr_enter;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, watermarks-&gt;dcn4x.b.sr_enter);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.sr_enter, watermarks-&gt;dcn4x.b.sr_enter);</div><div class='add'>+		// On dGPU Z states are N/A, so program all other 3 Stutter Enter wm A with the same value</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, watermarks-&gt;dcn4x.b.sr_enter);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, watermarks-&gt;dcn4x.b.sr_enter);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, watermarks-&gt;dcn4x.b.sr_enter);</div><div class='add'>+</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.sr_enter</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.sr_enter)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.sr_exit</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.sr_exit) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.sr_exit =</div><div class='add'>+				watermarks-&gt;dcn4x.b.sr_exit;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, watermarks-&gt;dcn4x.b.sr_exit);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.sr_exit, watermarks-&gt;dcn4x.b.sr_exit);</div><div class='add'>+		// On dGPU Z states are N/A, so program all other 3 Stutter Exit wm A with the same value</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, watermarks-&gt;dcn4x.b.sr_exit);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, watermarks-&gt;dcn4x.b.sr_exit);</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, watermarks-&gt;dcn4x.b.sr_exit);</div><div class='add'>+</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.sr_exit</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.sr_exit)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	return wm_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_pstate_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	bool wm_pending = false;</div><div class='add'>+</div><div class='add'>+	/* Section for UCLK_PSTATE_CHANGE_WATERMARKS */</div><div class='add'>+	/* clock state A */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.uclk_pstate</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.uclk_pstate) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.uclk_pstate =</div><div class='add'>+				watermarks-&gt;dcn4x.a.uclk_pstate;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, watermarks-&gt;dcn4x.a.uclk_pstate);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.uclk_pstate, watermarks-&gt;dcn4x.a.uclk_pstate);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.uclk_pstate</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.uclk_pstate)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.uclk_pstate</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.uclk_pstate) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.uclk_pstate =</div><div class='add'>+				watermarks-&gt;dcn4x.b.uclk_pstate;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, watermarks-&gt;dcn4x.b.uclk_pstate);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.uclk_pstate, watermarks-&gt;dcn4x.b.uclk_pstate);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.uclk_pstate</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.uclk_pstate)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* Section for UCLK_PSTATE_CHANGE_WATERMARKS1 (DUMMY_PSTATE/TEMP_READ/PPT) */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.temp_read_or_ppt</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.temp_read_or_ppt) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.temp_read_or_ppt =</div><div class='add'>+				watermarks-&gt;dcn4x.a.temp_read_or_ppt;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A, watermarks-&gt;dcn4x.a.temp_read_or_ppt);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK1_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.temp_read_or_ppt, watermarks-&gt;dcn4x.a.temp_read_or_ppt);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.temp_read_or_ppt</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.temp_read_or_ppt)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.temp_read_or_ppt</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.temp_read_or_ppt) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.temp_read_or_ppt =</div><div class='add'>+				watermarks-&gt;dcn4x.b.temp_read_or_ppt;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, watermarks-&gt;dcn4x.b.temp_read_or_ppt);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK1_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.temp_read_or_ppt, watermarks-&gt;dcn4x.b.temp_read_or_ppt);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.temp_read_or_ppt</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.temp_read_or_ppt)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* Section for FCLK_PSTATE_CHANGE_WATERMARKS */</div><div class='add'>+	/* clock state A */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.fclk_pstate</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.fclk_pstate) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.fclk_pstate =</div><div class='add'>+				watermarks-&gt;dcn4x.a.fclk_pstate;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, watermarks-&gt;dcn4x.a.fclk_pstate);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.fclk_pstate, watermarks-&gt;dcn4x.a.fclk_pstate);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.fclk_pstate</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.fclk_pstate)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.fclk_pstate</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.fclk_pstate) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.fclk_pstate =</div><div class='add'>+				watermarks-&gt;dcn4x.b.fclk_pstate;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, watermarks-&gt;dcn4x.b.fclk_pstate);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.fclk_pstate, watermarks-&gt;dcn4x.b.fclk_pstate);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.fclk_pstate</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.fclk_pstate)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* Section for FCLK_CHANGE_WATERMARKS1 (DUMMY_PSTATE/TEMP_READ/PPT) */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.temp_read_or_ppt</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.temp_read_or_ppt) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.temp_read_or_ppt =</div><div class='add'>+				watermarks-&gt;dcn4x.a.temp_read_or_ppt;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A, watermarks-&gt;dcn4x.a.temp_read_or_ppt);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK1_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.temp_read_or_ppt, watermarks-&gt;dcn4x.a.temp_read_or_ppt);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.temp_read_or_ppt</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.temp_read_or_ppt)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.temp_read_or_ppt</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.temp_read_or_ppt) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.temp_read_or_ppt =</div><div class='add'>+				watermarks-&gt;dcn4x.b.temp_read_or_ppt;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, watermarks-&gt;dcn4x.b.temp_read_or_ppt);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("FCLK_CHANGE_WATERMARK1_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.temp_read_or_ppt, watermarks-&gt;dcn4x.b.temp_read_or_ppt);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.temp_read_or_ppt</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.temp_read_or_ppt)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	return wm_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_usr_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	bool wm_pending = false;</div><div class='add'>+</div><div class='add'>+	/* clock state A */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.a.usr</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.a.usr) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.a.usr = watermarks-&gt;dcn4x.a.usr;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0,</div><div class='add'>+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, watermarks-&gt;dcn4x.a.usr);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_A calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.a.usr, watermarks-&gt;dcn4x.a.usr);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.a.usr</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.a.usr)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/* clock state B */</div><div class='add'>+	if (safe_to_lower || watermarks-&gt;dcn4x.b.usr</div><div class='add'>+			&gt; hubbub2-&gt;watermarks.dcn4x.b.usr) {</div><div class='add'>+		hubbub2-&gt;watermarks.dcn4x.b.usr = watermarks-&gt;dcn4x.b.usr;</div><div class='add'>+		REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0,</div><div class='add'>+				DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, watermarks-&gt;dcn4x.b.usr);</div><div class='add'>+		DC_LOG_BANDWIDTH_CALCS("USR_RETRAINING_WATERMARK_B calculated =%d\n"</div><div class='add'>+			"HW register value = 0x%x\n\n",</div><div class='add'>+			watermarks-&gt;dcn4x.b.usr, watermarks-&gt;dcn4x.b.usr);</div><div class='add'>+	} else if (watermarks-&gt;dcn4x.b.usr</div><div class='add'>+			&lt; hubbub2-&gt;watermarks.dcn4x.b.usr)</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	return wm_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool hubbub401_program_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	bool wm_pending = false;</div><div class='add'>+</div><div class='add'>+	if (hubbub401_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (hubbub401_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (hubbub401_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	if (hubbub401_program_usr_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))</div><div class='add'>+		wm_pending = true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.</div><div class='add'>+	 * If the memory controller is fully utilized and the DCHub requestors are</div><div class='add'>+	 * well ahead of their amortized schedule, then it is safe to prevent the next winner</div><div class='add'>+	 * from being committed and sent to the fabric.</div><div class='add'>+	 * The utilization of the memory controller is approximated by ensuring that</div><div class='add'>+	 * the number of outstanding requests is greater than a threshold specified</div><div class='add'>+	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized</div><div class='add'>+	 * schedule, the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.</div><div class='add'>+	 *</div><div class='add'>+	 * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet,</div><div class='add'>+	 *  set maximum value (0x1FF) to turn off it for now.</div><div class='add'>+	 */</div><div class='add'>+	/*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,</div><div class='add'>+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);</div><div class='add'>+		REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,</div><div class='add'>+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);</div><div class='add'>+	*/</div><div class='add'>+</div><div class='add'>+	hubbub1_allow_self_refresh_control(hubbub, !hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='add'>+</div><div class='add'>+	hubbub32_force_usr_retraining_allow(hubbub, hubbub-&gt;ctx-&gt;dc-&gt;debug.force_usr_allow);</div><div class='add'>+</div><div class='add'>+	return wm_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Copy values from WM set A to all other sets */</div><div class='add'>+static void hubbub401_init_watermarks(struct hubbub *hubbub)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	uint32_t reg;</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, reg);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, reg);</div><div class='add'>+</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);</div><div class='add'>+	reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A);</div><div class='add'>+	REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hubbub401_wm_read_state(struct hubbub *hubbub,</div><div class='add'>+		struct dcn_hubbub_wm *wm)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+	struct dcn_hubbub_wm_set *s;</div><div class='add'>+</div><div class='add'>+	memset(wm, 0, sizeof(struct dcn_hubbub_wm));</div><div class='add'>+</div><div class='add'>+	s = &amp;wm-&gt;sets[0];</div><div class='add'>+	s-&gt;wm_set = 0;</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,</div><div class='add'>+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &amp;s-&gt;data_urgent);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,</div><div class='add'>+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &amp;s-&gt;sr_enter);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,</div><div class='add'>+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &amp;s-&gt;sr_exit);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,</div><div class='add'>+			 DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &amp;s-&gt;dram_clk_change);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,</div><div class='add'>+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &amp;s-&gt;usr_retrain);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,</div><div class='add'>+			 DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &amp;s-&gt;fclk_pstate_change);</div><div class='add'>+</div><div class='add'>+	s = &amp;wm-&gt;sets[1];</div><div class='add'>+	s-&gt;wm_set = 1;</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,</div><div class='add'>+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &amp;s-&gt;data_urgent);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,</div><div class='add'>+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &amp;s-&gt;sr_enter);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,</div><div class='add'>+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &amp;s-&gt;sr_exit);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,</div><div class='add'>+			DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &amp;s-&gt;dram_clk_change);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,</div><div class='add'>+			 DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &amp;s-&gt;usr_retrain);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,</div><div class='add'>+			DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &amp;s-&gt;fclk_pstate_change);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool hubbub401_dcc_support_swizzle(</div><div class='add'>+		enum swizzle_mode_addr3_values swizzle,</div><div class='add'>+		unsigned int plane_pitch,</div><div class='add'>+		unsigned int bytes_per_element,</div><div class='add'>+		enum segment_order *segment_order_horz,</div><div class='add'>+		enum segment_order *segment_order_vert)</div><div class='add'>+{</div><div class='add'>+	bool swizzle_supported = false;</div><div class='add'>+</div><div class='add'>+	switch (swizzle) {</div><div class='add'>+	case DC_ADDR3_SW_LINEAR:</div><div class='add'>+		if ((plane_pitch * bytes_per_element) % 256 == 0)</div><div class='add'>+			swizzle_supported = true;</div><div class='add'>+		break;</div><div class='add'>+	case DC_ADDR3_SW_64KB_2D:</div><div class='add'>+	case DC_ADDR3_SW_256KB_2D:</div><div class='add'>+		swizzle_supported = true;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		swizzle_supported = false;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (swizzle_supported) {</div><div class='add'>+		if (bytes_per_element == 1) {</div><div class='add'>+			*segment_order_horz = segment_order__contiguous;</div><div class='add'>+			*segment_order_vert = segment_order__non_contiguous;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+		if (bytes_per_element == 2) {</div><div class='add'>+			*segment_order_horz = segment_order__non_contiguous;</div><div class='add'>+			*segment_order_vert = segment_order__contiguous;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+		if (bytes_per_element == 4) {</div><div class='add'>+			*segment_order_horz = segment_order__contiguous;</div><div class='add'>+			*segment_order_vert = segment_order__non_contiguous;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+		if (bytes_per_element == 8) {</div><div class='add'>+			*segment_order_horz = segment_order__contiguous;</div><div class='add'>+			*segment_order_vert = segment_order__non_contiguous;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool hubbub401_dcc_support_pixel_format(</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		unsigned int *plane0_bpe,</div><div class='add'>+		unsigned int *plane1_bpe)</div><div class='add'>+{</div><div class='add'>+	switch (format) {</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:</div><div class='add'>+		*plane0_bpe = 2;</div><div class='add'>+		*plane1_bpe = 0;</div><div class='add'>+		return true;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:</div><div class='add'>+		*plane0_bpe = 1;</div><div class='add'>+		*plane1_bpe = 2;</div><div class='add'>+		return true;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:</div><div class='add'>+		*plane0_bpe = 4;</div><div class='add'>+		*plane1_bpe = 0;</div><div class='add'>+		return true;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:</div><div class='add'>+		*plane0_bpe = 4;</div><div class='add'>+		*plane1_bpe = 1;</div><div class='add'>+		return true;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:</div><div class='add'>+		*plane0_bpe = 2;</div><div class='add'>+		*plane1_bpe = 4;</div><div class='add'>+		return true;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:</div><div class='add'>+		*plane0_bpe = 4;</div><div class='add'>+		*plane1_bpe = 0;</div><div class='add'>+		return true;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:</div><div class='add'>+		*plane0_bpe = 8;</div><div class='add'>+		*plane1_bpe = 0;</div><div class='add'>+		return true;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubbub401_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,</div><div class='add'>+		unsigned int bytes_per_element)</div><div class='add'>+{</div><div class='add'>+	if (bytes_per_element == 1) {</div><div class='add'>+		*blk256_width = 16;</div><div class='add'>+		*blk256_height = 16;</div><div class='add'>+	} else if (bytes_per_element == 2) {</div><div class='add'>+		*blk256_width = 16;</div><div class='add'>+		*blk256_height = 8;</div><div class='add'>+	} else if (bytes_per_element == 4) {</div><div class='add'>+		*blk256_width = 8;</div><div class='add'>+		*blk256_height = 8;</div><div class='add'>+	} else if (bytes_per_element == 8) {</div><div class='add'>+		*blk256_width = 8;</div><div class='add'>+		*blk256_height = 4;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubbub401_det_request_size(</div><div class='add'>+		unsigned int detile_buf_size,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		unsigned int p0_height,</div><div class='add'>+		unsigned int p0_width,</div><div class='add'>+		unsigned int p0_bpe,</div><div class='add'>+		unsigned int p1_height,</div><div class='add'>+		unsigned int p1_width,</div><div class='add'>+		unsigned int p1_bpe,</div><div class='add'>+		bool *p0_req128_horz_wc,</div><div class='add'>+		bool *p0_req128_vert_wc,</div><div class='add'>+		bool *p1_req128_horz_wc,</div><div class='add'>+		bool *p1_req128_vert_wc)</div><div class='add'>+{</div><div class='add'>+	unsigned int blk256_height = 0;</div><div class='add'>+	unsigned int blk256_width = 0;</div><div class='add'>+	unsigned int p0_swath_bytes_horz_wc, p0_swath_bytes_vert_wc;</div><div class='add'>+	unsigned int p1_swath_bytes_horz_wc, p1_swath_bytes_vert_wc;</div><div class='add'>+</div><div class='add'>+	//For plane0</div><div class='add'>+	hubbub401_get_blk256_size(&amp;blk256_width, &amp;blk256_height, p0_bpe);</div><div class='add'>+</div><div class='add'>+	p0_swath_bytes_horz_wc = p0_width * blk256_height * p0_bpe;</div><div class='add'>+	p0_swath_bytes_vert_wc = p0_height * blk256_width * p0_bpe;</div><div class='add'>+</div><div class='add'>+	*p0_req128_horz_wc = (2 * p0_swath_bytes_horz_wc &lt;= detile_buf_size) ?</div><div class='add'>+			false : /* full 256B request */</div><div class='add'>+			true; /* half 128b request */</div><div class='add'>+</div><div class='add'>+	*p0_req128_vert_wc = (2 * p0_swath_bytes_vert_wc &lt;= detile_buf_size) ?</div><div class='add'>+			false : /* full 256B request */</div><div class='add'>+			true; /* half 128b request */</div><div class='add'>+</div><div class='add'>+	/*For dual planes needs to be considered together */</div><div class='add'>+	if (p1_bpe) {</div><div class='add'>+		hubbub401_get_blk256_size(&amp;blk256_width, &amp;blk256_height, p1_bpe);</div><div class='add'>+</div><div class='add'>+		p1_swath_bytes_horz_wc = p1_width * blk256_height * p1_bpe;</div><div class='add'>+		p1_swath_bytes_vert_wc = p1_height * blk256_width * p1_bpe;</div><div class='add'>+</div><div class='add'>+		switch (format) {</div><div class='add'>+		default:</div><div class='add'>+			/* No any adjustment needed*/</div><div class='add'>+			break;</div><div class='add'>+		case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:</div><div class='add'>+		case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:</div><div class='add'>+			/* Packing at the ratio of 3:2 is supported before the detile buffer</div><div class='add'>+			 * for YUV420 video with 10bpc (P010). Need to adjust for that.</div><div class='add'>+			 */</div><div class='add'>+			p0_swath_bytes_horz_wc = (((p0_swath_bytes_horz_wc * 2) / 3 + 255) / 256) * 256;</div><div class='add'>+			p0_swath_bytes_vert_wc = (((p0_swath_bytes_vert_wc * 2) / 3 + 255) / 256) * 256;</div><div class='add'>+			p1_swath_bytes_horz_wc = (((p1_swath_bytes_horz_wc * 2) / 3 + 255) / 256) * 256;</div><div class='add'>+			p1_swath_bytes_vert_wc = (((p1_swath_bytes_vert_wc * 2) / 3 + 255) / 256) * 256;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*p0_req128_horz_wc = *p1_req128_horz_wc = (2 * p0_swath_bytes_horz_wc +</div><div class='add'>+			2 * p1_swath_bytes_horz_wc &lt;= detile_buf_size) ?</div><div class='add'>+				false : /* full 256B request */</div><div class='add'>+				true; /* half 128B request */</div><div class='add'>+</div><div class='add'>+		*p0_req128_vert_wc = *p1_req128_vert_wc = (2 * p0_swath_bytes_vert_wc +</div><div class='add'>+			2 * p1_swath_bytes_vert_wc &lt;= detile_buf_size) ?</div><div class='add'>+				false : /* full 256B request */</div><div class='add'>+				true; /* half 128B request */</div><div class='add'>+</div><div class='add'>+		/* If 128B requests are true, meaning 2 full swaths of data cannot fit</div><div class='add'>+		 * in de-tile buffer, check if one plane can use 256B request while</div><div class='add'>+		 * the other plane is using 128B requests</div><div class='add'>+		 */</div><div class='add'>+		if (*p0_req128_horz_wc) {</div><div class='add'>+			// If ratio around 1:1 between p0 and p1 try to recalulate if p0 can use 256B</div><div class='add'>+			if (p0_swath_bytes_horz_wc &lt;= p1_swath_bytes_horz_wc + p1_swath_bytes_horz_wc / 2) {</div><div class='add'>+</div><div class='add'>+				*p0_req128_horz_wc = (2 * p0_swath_bytes_horz_wc + p1_swath_bytes_horz_wc &lt;= detile_buf_size) ?</div><div class='add'>+					false : /* full 256B request */</div><div class='add'>+					true; /* half 128b request */</div><div class='add'>+</div><div class='add'>+			} else {</div><div class='add'>+				/* ratio about 2:1 between p0 and p1, try to recalulate if p1 can use 256B */</div><div class='add'>+				*p1_req128_horz_wc = (p0_swath_bytes_horz_wc + 2 * p1_swath_bytes_horz_wc &lt;= detile_buf_size) ?</div><div class='add'>+					false : /* full 256B request */</div><div class='add'>+					true; /* half 128b request */</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (*p0_req128_vert_wc) {</div><div class='add'>+			// If ratio around 1:1 between p0 and p1 try to recalulate if p0 can use 256B</div><div class='add'>+			if (p0_swath_bytes_vert_wc &lt;= p1_swath_bytes_vert_wc + p1_swath_bytes_vert_wc / 2) {</div><div class='add'>+</div><div class='add'>+				*p0_req128_vert_wc = (2 * p0_swath_bytes_vert_wc + p1_swath_bytes_vert_wc &lt;= detile_buf_size) ?</div><div class='add'>+					false : /* full 256B request */</div><div class='add'>+					true; /* half 128b request */</div><div class='add'>+</div><div class='add'>+			} else {</div><div class='add'>+				/* ratio about 2:1 between p0 and p1, try to recalulate if p1 can use 256B */</div><div class='add'>+				*p1_req128_vert_wc = (p0_swath_bytes_vert_wc + 2 * p1_swath_bytes_vert_wc &lt;= detile_buf_size) ?</div><div class='add'>+					false : /* full 256B request */</div><div class='add'>+					true; /* half 128b request */</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,</div><div class='add'>+		const struct dc_dcc_surface_param *input,</div><div class='add'>+		struct dc_surface_dcc_cap *output)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = hubbub-&gt;ctx-&gt;dc;</div><div class='add'>+	const unsigned int max_dcc_plane_width = dc-&gt;caps.dcc_plane_width_limit;</div><div class='add'>+	/* DCN4_Programming_Guide_DCHUB.docx, Section 5.11.2.2 */</div><div class='add'>+	enum dcc_control dcc_control;</div><div class='add'>+	unsigned int plane0_bpe, plane1_bpe;</div><div class='add'>+	enum segment_order segment_order_horz, segment_order_vert;</div><div class='add'>+	enum segment_order p1_segment_order_horz, p1_segment_order_vert;</div><div class='add'>+	bool req128_horz_wc, req128_vert_wc;</div><div class='add'>+	unsigned int plane0_width = 0, plane0_height = 0, plane1_width = 0, plane1_height = 0;</div><div class='add'>+	bool p1_req128_horz_wc, p1_req128_vert_wc, is_dual_plane;</div><div class='add'>+</div><div class='add'>+	memset(output, 0, sizeof(*output));</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.disable_dcc == DCC_DISABLE)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Conservatively disable DCC for cases where ODM4:1 may be required. */</div><div class='add'>+	if (max_dcc_plane_width != 0 &amp;&amp;</div><div class='add'>+			(input-&gt;surface_size.width &gt; max_dcc_plane_width || input-&gt;plane1_size.width &gt; max_dcc_plane_width))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	switch (input-&gt;format) {</div><div class='add'>+	default:</div><div class='add'>+		is_dual_plane = false;</div><div class='add'>+</div><div class='add'>+		plane1_width = 0;</div><div class='add'>+		plane1_height = 0;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;surface_size.width &gt; 6144 + 16)</div><div class='add'>+			plane0_width = 6160;</div><div class='add'>+		else</div><div class='add'>+			plane0_width = input-&gt;surface_size.width;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;surface_size.height &gt; 6144 + 16)</div><div class='add'>+			plane0_height = 6160;</div><div class='add'>+		else</div><div class='add'>+			plane0_height = input-&gt;surface_size.height;</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:</div><div class='add'>+		is_dual_plane = true;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;surface_size.width &gt; 7680 + 16)</div><div class='add'>+			plane0_width = 7696;</div><div class='add'>+		else</div><div class='add'>+			plane0_width = input-&gt;surface_size.width;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;surface_size.height &gt; 4320 + 16)</div><div class='add'>+			plane0_height = 4336;</div><div class='add'>+		else</div><div class='add'>+			plane0_height = input-&gt;surface_size.height;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;plane1_size.width &gt; 7680 + 16)</div><div class='add'>+			plane1_width = 7696 / 2;</div><div class='add'>+		else</div><div class='add'>+			plane1_width = input-&gt;plane1_size.width;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;plane1_size.height &gt; 4320 + 16)</div><div class='add'>+			plane1_height = 4336 / 2;</div><div class='add'>+		else</div><div class='add'>+			plane1_height = input-&gt;plane1_size.height;</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:</div><div class='add'>+		is_dual_plane = true;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;surface_size.width &gt; 5120 + 16)</div><div class='add'>+			plane0_width = 5136;</div><div class='add'>+		else</div><div class='add'>+			plane0_width = input-&gt;surface_size.width;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;surface_size.height &gt; 5120 + 16)</div><div class='add'>+			plane0_height = 5136;</div><div class='add'>+		else</div><div class='add'>+			plane0_height = input-&gt;surface_size.height;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;plane1_size.width &gt; 5120 + 16)</div><div class='add'>+			plane1_width = 5136;</div><div class='add'>+		else</div><div class='add'>+			plane1_width = input-&gt;plane1_size.width;</div><div class='add'>+</div><div class='add'>+		if (input-&gt;plane1_size.height &gt; 5120 + 16)</div><div class='add'>+			plane1_height = 5136;</div><div class='add'>+		else</div><div class='add'>+			plane1_height = input-&gt;plane1_size.height;</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!hubbub-&gt;funcs-&gt;dcc_support_pixel_format_plane0_plane1(input-&gt;format,</div><div class='add'>+			&amp;plane0_bpe, &amp;plane1_bpe))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Find plane0 DCC Controls */</div><div class='add'>+	if (!is_dual_plane) {</div><div class='add'>+</div><div class='add'>+		if (!hubbub-&gt;funcs-&gt;dcc_support_swizzle_addr3(input-&gt;swizzle_mode_addr3,</div><div class='add'>+				input-&gt;plane0_pitch, plane0_bpe,</div><div class='add'>+				&amp;segment_order_horz, &amp;segment_order_vert))</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		hubbub401_det_request_size(TO_DCN20_HUBBUB(hubbub)-&gt;detile_buf_size, input-&gt;format,</div><div class='add'>+				plane0_height, plane0_width, plane0_bpe,</div><div class='add'>+				plane1_height, plane1_width, plane1_bpe,</div><div class='add'>+				&amp;req128_horz_wc, &amp;req128_vert_wc, &amp;p1_req128_horz_wc, &amp;p1_req128_vert_wc);</div><div class='add'>+</div><div class='add'>+		if (!req128_horz_wc &amp;&amp; !req128_vert_wc) {</div><div class='add'>+			dcc_control = dcc_control__256_256;</div><div class='add'>+		} else if (input-&gt;scan == SCAN_DIRECTION_HORIZONTAL) {</div><div class='add'>+			if (!req128_horz_wc)</div><div class='add'>+				dcc_control = dcc_control__256_256;</div><div class='add'>+			else if (segment_order_horz == segment_order__contiguous)</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+			else</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+		} else if (input-&gt;scan == SCAN_DIRECTION_VERTICAL) {</div><div class='add'>+			if (!req128_vert_wc)</div><div class='add'>+				dcc_control = dcc_control__256_256;</div><div class='add'>+			else if (segment_order_vert == segment_order__contiguous)</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+			else</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+		} else {</div><div class='add'>+			if ((req128_horz_wc &amp;&amp;</div><div class='add'>+				segment_order_horz == segment_order__non_contiguous) ||</div><div class='add'>+				(req128_vert_wc &amp;&amp;</div><div class='add'>+				segment_order_vert == segment_order__non_contiguous))</div><div class='add'>+				/* access_dir not known, must use most constraining */</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+			else</div><div class='add'>+				/* req128 is true for either horz and vert</div><div class='add'>+				 * but segment_order is contiguous</div><div class='add'>+				 */</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;debug.disable_dcc == DCC_HALF_REQ_DISALBE &amp;&amp;</div><div class='add'>+			dcc_control != dcc_control__256_256)</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		switch (dcc_control) {</div><div class='add'>+		case dcc_control__256_256:</div><div class='add'>+			output-&gt;grph.rgb.dcc_controls.dcc_256_256 = 1;</div><div class='add'>+			output-&gt;grph.rgb.dcc_controls.dcc_256_128 = 1;</div><div class='add'>+			output-&gt;grph.rgb.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case dcc_control__256_128:</div><div class='add'>+			output-&gt;grph.rgb.dcc_controls.dcc_256_128 = 1;</div><div class='add'>+			output-&gt;grph.rgb.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case dcc_control__256_64:</div><div class='add'>+			output-&gt;grph.rgb.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			/* Shouldn't get here */</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* For dual plane cases, need to examine both planes together */</div><div class='add'>+		if (!hubbub-&gt;funcs-&gt;dcc_support_swizzle_addr3(input-&gt;swizzle_mode_addr3,</div><div class='add'>+				input-&gt;plane0_pitch, plane0_bpe,</div><div class='add'>+				&amp;segment_order_horz, &amp;segment_order_vert))</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		if (!hubbub-&gt;funcs-&gt;dcc_support_swizzle_addr3(input-&gt;swizzle_mode_addr3,</div><div class='add'>+			input-&gt;plane1_pitch, plane1_bpe,</div><div class='add'>+			&amp;p1_segment_order_horz, &amp;p1_segment_order_vert))</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		hubbub401_det_request_size(TO_DCN20_HUBBUB(hubbub)-&gt;detile_buf_size, input-&gt;format,</div><div class='add'>+				plane0_height, plane0_width, plane0_bpe,</div><div class='add'>+				plane1_height, plane1_width, plane1_bpe,</div><div class='add'>+				&amp;req128_horz_wc, &amp;req128_vert_wc, &amp;p1_req128_horz_wc, &amp;p1_req128_vert_wc);</div><div class='add'>+</div><div class='add'>+		/* Determine Plane 0 DCC Controls */</div><div class='add'>+		if (!req128_horz_wc &amp;&amp; !req128_vert_wc) {</div><div class='add'>+			dcc_control = dcc_control__256_256;</div><div class='add'>+		} else if (input-&gt;scan == SCAN_DIRECTION_HORIZONTAL) {</div><div class='add'>+			if (!req128_horz_wc)</div><div class='add'>+				dcc_control = dcc_control__256_256;</div><div class='add'>+			else if (segment_order_horz == segment_order__contiguous)</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+			else</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+		} else if (input-&gt;scan == SCAN_DIRECTION_VERTICAL) {</div><div class='add'>+			if (!req128_vert_wc)</div><div class='add'>+				dcc_control = dcc_control__256_256;</div><div class='add'>+			else if (segment_order_vert == segment_order__contiguous)</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+			else</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+		} else {</div><div class='add'>+			if ((req128_horz_wc &amp;&amp;</div><div class='add'>+				segment_order_horz == segment_order__non_contiguous) ||</div><div class='add'>+				(req128_vert_wc &amp;&amp;</div><div class='add'>+				segment_order_vert == segment_order__non_contiguous))</div><div class='add'>+				/* access_dir not known, must use most constraining */</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+			else</div><div class='add'>+				/* req128 is true for either horz and vert</div><div class='add'>+				 * but segment_order is contiguous</div><div class='add'>+				 */</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (dcc_control) {</div><div class='add'>+		case dcc_control__256_256:</div><div class='add'>+			output-&gt;video.luma.dcc_controls.dcc_256_256 = 1;</div><div class='add'>+			output-&gt;video.luma.dcc_controls.dcc_256_128 = 1;</div><div class='add'>+			output-&gt;video.luma.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case dcc_control__256_128:</div><div class='add'>+			output-&gt;video.luma.dcc_controls.dcc_256_128 = 1;</div><div class='add'>+			output-&gt;video.luma.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case dcc_control__256_64:</div><div class='add'>+			output-&gt;video.luma.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Determine Plane 1 DCC Controls */</div><div class='add'>+		if (!p1_req128_horz_wc &amp;&amp; !p1_req128_vert_wc) {</div><div class='add'>+			dcc_control = dcc_control__256_256;</div><div class='add'>+		} else if (input-&gt;scan == SCAN_DIRECTION_HORIZONTAL) {</div><div class='add'>+			if (!p1_req128_horz_wc)</div><div class='add'>+				dcc_control = dcc_control__256_256;</div><div class='add'>+			else if (p1_segment_order_horz == segment_order__contiguous)</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+			else</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+		} else if (input-&gt;scan == SCAN_DIRECTION_VERTICAL) {</div><div class='add'>+			if (!p1_req128_vert_wc)</div><div class='add'>+				dcc_control = dcc_control__256_256;</div><div class='add'>+			else if (p1_segment_order_vert == segment_order__contiguous)</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+			else</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+		} else {</div><div class='add'>+			if ((p1_req128_horz_wc &amp;&amp;</div><div class='add'>+				p1_segment_order_horz == segment_order__non_contiguous) ||</div><div class='add'>+				(p1_req128_vert_wc &amp;&amp;</div><div class='add'>+				p1_segment_order_vert == segment_order__non_contiguous))</div><div class='add'>+				/* access_dir not known, must use most constraining */</div><div class='add'>+				dcc_control = dcc_control__256_64;</div><div class='add'>+			else</div><div class='add'>+				/* req128 is true for either horz and vert</div><div class='add'>+				 * but segment_order is contiguous</div><div class='add'>+				 */</div><div class='add'>+				dcc_control = dcc_control__256_128;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (dcc_control) {</div><div class='add'>+		case dcc_control__256_256:</div><div class='add'>+			output-&gt;video.chroma.dcc_controls.dcc_256_256 = 1;</div><div class='add'>+			output-&gt;video.chroma.dcc_controls.dcc_256_128 = 1;</div><div class='add'>+			output-&gt;video.chroma.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case dcc_control__256_128:</div><div class='add'>+			output-&gt;video.chroma.dcc_controls.dcc_256_128 = 1;</div><div class='add'>+			output-&gt;video.chroma.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case dcc_control__256_64:</div><div class='add'>+			output-&gt;video.chroma.dcc_controls.dcc_256_64 = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	output-&gt;capable = true;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	switch (hubp_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE(DCHUBBUB_DET0_CTRL,</div><div class='add'>+					DET0_SIZE, det_buffer_size_seg);</div><div class='add'>+		hubbub2-&gt;det0_size = det_buffer_size_seg;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE(DCHUBBUB_DET1_CTRL,</div><div class='add'>+					DET1_SIZE, det_buffer_size_seg);</div><div class='add'>+		hubbub2-&gt;det1_size = det_buffer_size_seg;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE(DCHUBBUB_DET2_CTRL,</div><div class='add'>+					DET2_SIZE, det_buffer_size_seg);</div><div class='add'>+		hubbub2-&gt;det2_size = det_buffer_size_seg;</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE(DCHUBBUB_DET3_CTRL,</div><div class='add'>+					DET3_SIZE, det_buffer_size_seg);</div><div class='add'>+		hubbub2-&gt;det3_size = det_buffer_size_seg;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	if (hubbub2-&gt;det0_size + hubbub2-&gt;det1_size + hubbub2-&gt;det2_size</div><div class='add'>+			+ hubbub2-&gt;det3_size + hubbub2-&gt;compbuf_size_segments &gt; hubbub2-&gt;crb_size_segs) {</div><div class='add'>+		/* This may happen during seamless transition from ODM 2:1 to ODM4:1 */</div><div class='add'>+		DC_LOG_WARNING("CRB Config Warning: DET size (%d,%d,%d,%d) + Compbuf size (%d) &gt;  CRB segments (%d)\n",</div><div class='add'>+						hubbub2-&gt;det0_size, hubbub2-&gt;det1_size, hubbub2-&gt;det2_size, hubbub2-&gt;det3_size,</div><div class='add'>+						hubbub2-&gt;compbuf_size_segments, hubbub2-&gt;crb_size_segs);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	unsigned int cur_compbuf_size_seg = 0;</div><div class='add'>+</div><div class='add'>+	if (safe_to_increase || compbuf_size_seg &lt;= hubbub2-&gt;compbuf_size_segments) {</div><div class='add'>+		if (compbuf_size_seg &gt; hubbub2-&gt;compbuf_size_segments) {</div><div class='add'>+			REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2-&gt;det0_size, 1, 100);</div><div class='add'>+			REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2-&gt;det1_size, 1, 100);</div><div class='add'>+			REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2-&gt;det2_size, 1, 100);</div><div class='add'>+			REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2-&gt;det3_size, 1, 100);</div><div class='add'>+		}</div><div class='add'>+		/* Should never be hit, if it is we have an erroneous hw config*/</div><div class='add'>+		ASSERT(hubbub2-&gt;det0_size + hubbub2-&gt;det1_size + hubbub2-&gt;det2_size</div><div class='add'>+				+ hubbub2-&gt;det3_size + compbuf_size_seg &lt;= hubbub2-&gt;crb_size_segs);</div><div class='add'>+		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_seg);</div><div class='add'>+		hubbub2-&gt;compbuf_size_segments = compbuf_size_seg;</div><div class='add'>+</div><div class='add'>+		ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &amp;cur_compbuf_size_seg) &amp;&amp; !cur_compbuf_size_seg);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	switch (hubp_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2-&gt;det0_size, 1, 100000); /* 1 vupdate at 10hz */</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2-&gt;det1_size, 1, 100000);</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2-&gt;det2_size, 1, 100000);</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2-&gt;det3_size, 1, 100000);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);</div><div class='add'>+</div><div class='add'>+	bool wm_pending = false;</div><div class='add'>+	uint32_t temp;</div><div class='add'>+</div><div class='add'>+	/* request backpressure and outstanding return threshold (unused)*/</div><div class='add'>+	//REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs-&gt;req_stall_threshold);</div><div class='add'>+</div><div class='add'>+	/* P-State stall threshold */</div><div class='add'>+	REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs-&gt;pstate_stall_threshold);</div><div class='add'>+</div><div class='add'>+	if (safe_to_lower || arb_regs-&gt;allow_sdpif_rate_limit_when_cstate_req &gt; hubbub2-&gt;allow_sdpif_rate_limit_when_cstate_req) {</div><div class='add'>+		hubbub2-&gt;allow_sdpif_rate_limit_when_cstate_req = arb_regs-&gt;allow_sdpif_rate_limit_when_cstate_req;</div><div class='add'>+</div><div class='add'>+		/* only update the required bits */</div><div class='add'>+		REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &amp;temp);</div><div class='add'>+		if (hubbub2-&gt;allow_sdpif_rate_limit_when_cstate_req) {</div><div class='add'>+			temp |= (1 &lt;&lt; 5);</div><div class='add'>+		} else {</div><div class='add'>+			temp &amp;= ~(1 &lt;&lt; 5);</div><div class='add'>+		}</div><div class='add'>+		REG_UPDATE(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, temp);</div><div class='add'>+	} else {</div><div class='add'>+		wm_pending = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return wm_pending;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hubbub_funcs hubbub4_01_funcs = {</div><div class='add'>+	.update_dchub = hubbub2_update_dchub,</div><div class='add'>+	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,</div><div class='add'>+	.init_vm_ctx = hubbub2_init_vm_ctx,</div><div class='add'>+	.dcc_support_swizzle_addr3 = hubbub401_dcc_support_swizzle,</div><div class='add'>+	.dcc_support_pixel_format_plane0_plane1 = hubbub401_dcc_support_pixel_format,</div><div class='add'>+	.get_dcc_compression_cap = hubbub401_get_dcc_compression_cap,</div><div class='add'>+	.wm_read_state = hubbub401_wm_read_state,</div><div class='add'>+	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,</div><div class='add'>+	.program_watermarks = hubbub401_program_watermarks,</div><div class='add'>+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,</div><div class='add'>+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,</div><div class='add'>+	.verify_allow_pstate_change_high = NULL,</div><div class='add'>+	.force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes,</div><div class='add'>+	.force_pstate_change_control = hubbub3_force_pstate_change_control,</div><div class='add'>+	.init_watermarks = hubbub401_init_watermarks,</div><div class='add'>+	.init_crb = dcn401_init_crb,</div><div class='add'>+	.hubbub_read_state = hubbub2_read_state,</div><div class='add'>+	.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,</div><div class='add'>+	.set_request_limit = hubbub32_set_request_limit,</div><div class='add'>+	.program_det_segments = dcn401_program_det_segments,</div><div class='add'>+	.program_compbuf_segments = dcn401_program_compbuf_segments,</div><div class='add'>+	.wait_for_det_update = dcn401_wait_for_det_update,</div><div class='add'>+	.program_arbiter = dcn401_program_arbiter,</div><div class='add'>+	.hubbub_read_reg_state = hubbub3_read_reg_state</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void hubbub401_construct(struct dcn20_hubbub *hubbub2,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dcn_hubbub_registers *hubbub_regs,</div><div class='add'>+	const struct dcn_hubbub_shift *hubbub_shift,</div><div class='add'>+	const struct dcn_hubbub_mask *hubbub_mask,</div><div class='add'>+	int det_size_kb,</div><div class='add'>+	int pixel_chunk_size_kb,</div><div class='add'>+	int config_return_buffer_size_kb)</div><div class='add'>+{</div><div class='add'>+	hubbub2-&gt;base.ctx = ctx;</div><div class='add'>+	hubbub2-&gt;base.funcs = &amp;hubbub4_01_funcs;</div><div class='add'>+	hubbub2-&gt;regs = hubbub_regs;</div><div class='add'>+	hubbub2-&gt;shifts = hubbub_shift;</div><div class='add'>+	hubbub2-&gt;masks = hubbub_mask;</div><div class='add'>+</div><div class='add'>+	hubbub2-&gt;detile_buf_size = det_size_kb * 1024;</div><div class='add'>+	hubbub2-&gt;pixel_chunk_size = pixel_chunk_size_kb * 1024;</div><div class='add'>+	hubbub2-&gt;crb_size_segs = config_return_buffer_size_kb / DCN4_01_CRB_SEGMENT_SIZE_KB;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h<br/>new file mode 100644<br/>index 000000000000..b1d9ea9d1c3d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h</a></div><div class='hunk'>@@ -0,0 +1,206 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_HUBBUB_DCN401_H__</div><div class='add'>+#define __DC_HUBBUB_DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "dcn32/dcn32_hubbub.h"</div><div class='add'>+</div><div class='add'>+#define DCN4_01_CRB_SIZE_KB 1344</div><div class='add'>+#define DCN4_01_DEFAULT_DET_SIZE 320</div><div class='add'>+#define DCN4_01_CRB_SEGMENT_SIZE_KB 64</div><div class='add'>+</div><div class='add'>+#define HUBBUB_MASK_SH_LIST_DCN4_01(mask_sh)\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MAX_REQ_OUTSTAND, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A, DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\</div><div class='add'>+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A, DCHUBBUB_ARB_FRAC_URG_BW_MALL_A, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \</div><div class='add'>+	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh),\</div><div class='add'>+	HUBBUB_SF(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DISPCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_ERROR_STATUS, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_UNDERFLOW_STATUS, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_STATUS, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_CLEAR, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, mask_sh),\</div><div class='add'>+	HUBBUB_SF(DCHUBBUB_CTRL_STATUS, CSTATE_SWATH_CHK_GOOD_MODE, mask_sh)</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_urgent_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower);</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_stutter_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower);</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_pstate_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower);</div><div class='add'>+</div><div class='add'>+bool hubbub401_program_usr_watermarks(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		union dcn_watermark_set *watermarks,</div><div class='add'>+		unsigned int refclk_mhz,</div><div class='add'>+		bool safe_to_lower);</div><div class='add'>+</div><div class='add'>+bool hubbub401_dcc_support_swizzle(</div><div class='add'>+		enum swizzle_mode_addr3_values swizzle,</div><div class='add'>+		unsigned int plane_pitch,</div><div class='add'>+		unsigned int bytes_per_element,</div><div class='add'>+		enum segment_order *segment_order_horz,</div><div class='add'>+		enum segment_order *segment_order_vert);</div><div class='add'>+</div><div class='add'>+bool hubbub401_dcc_support_pixel_format(</div><div class='add'>+			enum surface_pixel_format format,</div><div class='add'>+			unsigned int *plane0_bpe,</div><div class='add'>+			unsigned int *plane1_bpe);</div><div class='add'>+</div><div class='add'>+void hubbub401_get_blk256_size(</div><div class='add'>+		unsigned int *blk256_width,</div><div class='add'>+		unsigned int *blk256_height,</div><div class='add'>+		unsigned int bytes_per_element);</div><div class='add'>+</div><div class='add'>+void hubbub401_det_request_size(</div><div class='add'>+		unsigned int detile_buf_size,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		unsigned int p0_height,</div><div class='add'>+		unsigned int p0_width,</div><div class='add'>+		unsigned int p0_bpe,</div><div class='add'>+		unsigned int p1_height,</div><div class='add'>+		unsigned int p1_width,</div><div class='add'>+		unsigned int p1_bpe,</div><div class='add'>+		bool *p0_req128_horz_wc,</div><div class='add'>+		bool *p0_req128_vert_wc,</div><div class='add'>+		bool *p1_req128_horz_wc,</div><div class='add'>+		bool *p1_req128_vert_wc);</div><div class='add'>+bool hubbub401_get_dcc_compression_cap(</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		const struct dc_dcc_surface_param *input,</div><div class='add'>+		struct dc_surface_dcc_cap *output);</div><div class='add'>+</div><div class='add'>+void hubbub401_construct(struct dcn20_hubbub *hubbub2,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dcn_hubbub_registers *hubbub_regs,</div><div class='add'>+	const struct dcn_hubbub_shift *hubbub_shift,</div><div class='add'>+	const struct dcn_hubbub_mask *hubbub_mask,</div><div class='add'>+	int det_size_kb,</div><div class='add'>+	int pixel_chunk_size_kb,</div><div class='add'>+	int config_return_buffer_size_kb);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hubp/Makefile b/drivers/gpu/drm/amd/display/dc/hubp/Makefile<br/>new file mode 100644<br/>index 000000000000..a2d1128de7a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/Makefile</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+</div><div class='add'>+# Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'hubp' sub-component of DAL.</div><div class='add'>+#</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN10 = dcn10_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN10 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn10/,$(HUBP_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN10)</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN20 = dcn20_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN20 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn20/,$(HUBP_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN201 = dcn201_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN201 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn201/,$(HUBP_DCN201))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN201)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN21 = dcn21_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN21 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn21/,$(HUBP_DCN21))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN21)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+HUBP_DCN30 = dcn30_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN30 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn30/,$(HUBP_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN31 = dcn31_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN31 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn31/,$(HUBP_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN31)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN32 = dcn32_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN32 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn32/,$(HUBP_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN35 = dcn35_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN35 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn35/,$(HUBP_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HUBP_DCN401 = dcn401_hubp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN401)</div><div class='add'>+</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c<br/>index bf399819ca80..6378e3fd7249 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c</a></div><div class='hunk'>@@ -140,7 +140,7 @@ void hubp1_vready_workaround(struct hubp *hubp,</div><div class='ctx'> </div><div class='ctx'> void hubp1_program_tiling(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='del'>-	const union dc_tiling_info *info,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='ctx'> 	const enum surface_pixel_format pixel_format)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);</div><div class='hunk'>@@ -518,6 +518,20 @@ bool hubp1_program_surface_flip_and_addr(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hubp1_clear_tiling(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);</div><div class='add'>+	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,</div><div class='add'>+		     PRIMARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		     PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,</div><div class='add'>+		     SECONDARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		     SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hubp1_dcc_control(struct hubp *hubp, bool enable,</div><div class='ctx'> 		enum hubp_ind_block_size independent_64b_blks)</div><div class='ctx'> {</div><div class='hunk'>@@ -532,10 +546,17 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,</div><div class='ctx'> 			SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hubp_reset(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	memset(&amp;hubp-&gt;pos, 0, sizeof(hubp-&gt;pos));</div><div class='add'>+	memset(&amp;hubp-&gt;att, 0, sizeof(hubp-&gt;att));</div><div class='add'>+	hubp-&gt;cursor_offload = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hubp1_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -749,7 +770,8 @@ bool hubp1_is_flip_pending(struct hubp *hubp)</div><div class='ctx'> 	if (flip_pending)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='del'>-	if (earliest_inuse_address.grph.addr.quad_part != hubp-&gt;request_address.grph.addr.quad_part)</div><div class='add'>+	if (hubp &amp;&amp;</div><div class='add'>+	    earliest_inuse_address.grph.addr.quad_part != hubp-&gt;request_address.grph.addr.quad_part)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -1336,8 +1358,9 @@ static void hubp1_wait_pipe_read_start(struct hubp *hubp)</div><div class='ctx'> </div><div class='ctx'> void hubp1_init(struct hubp *hubp)</div><div class='ctx'> {</div><div class='del'>-	//do nothing</div><div class='add'>+	hubp_reset(hubp);</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> static const struct hubp_funcs dcn10_hubp_funcs = {</div><div class='ctx'> 	.hubp_program_surface_flip_and_addr =</div><div class='ctx'> 			hubp1_program_surface_flip_and_addr,</div><div class='hunk'>@@ -1350,6 +1373,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {</div><div class='ctx'> 	.hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,</div><div class='ctx'> 	.set_blank = hubp1_set_blank,</div><div class='ctx'> 	.dcc_control = hubp1_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.set_hubp_blank_en = hubp1_set_hubp_blank_en,</div><div class='ctx'> 	.set_cursor_attributes	= hubp1_cursor_set_attributes,</div><div class='hunk'>@@ -1362,6 +1386,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = {</div><div class='ctx'> 	.hubp_disable_control =  hubp1_disable_control,</div><div class='ctx'> 	.hubp_get_underflow_status = hubp1_get_underflow_status,</div><div class='ctx'> 	.hubp_init = hubp1_init,</div><div class='add'>+	.hubp_clear_tiling = hubp1_clear_tiling,</div><div class='ctx'> </div><div class='ctx'> 	.dmdata_set_attributes = NULL,</div><div class='ctx'> 	.dmdata_load = NULL,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h<br/>index 09784222cc03..f2571076fc50 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h</a></div><div class='hunk'>@@ -104,7 +104,10 @@</div><div class='ctx'> 	SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\</div><div class='ctx'> 	SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\</div><div class='ctx'> 	SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\</div><div class='del'>-	SRI(HUBP_CLK_CNTL, HUBP, id)</div><div class='add'>+	SRI(HUBP_CLK_CNTL, HUBP, id),\</div><div class='add'>+	SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id),\</div><div class='add'>+	SRI(HUBP_MEASURE_WIN_CTRL_DCFCLK, HUBP, id),\</div><div class='add'>+	SRI(HUBP_MEASURE_WIN_CTRL_DPPCLK, HUBP, id)</div><div class='ctx'> </div><div class='ctx'> /* Register address initialization macro for ASICs with VM */</div><div class='ctx'> #define HUBP_REG_LIST_DCN_VM(id)\</div><div class='hunk'>@@ -249,7 +252,20 @@</div><div class='ctx'> 	uint32_t CURSOR_POSITION; \</div><div class='ctx'> 	uint32_t CURSOR_HOT_SPOT; \</div><div class='ctx'> 	uint32_t CURSOR_DST_OFFSET; \</div><div class='del'>-	uint32_t HUBP_CLK_CNTL</div><div class='add'>+	uint32_t HUBP_CLK_CNTL; \</div><div class='add'>+	uint32_t HUBPRET_READ_LINE_VALUE; \</div><div class='add'>+	uint32_t HUBP_MEASURE_WIN_CTRL_DCFCLK; \</div><div class='add'>+	uint32_t HUBP_MEASURE_WIN_CTRL_DPPCLK; \</div><div class='add'>+	uint32_t HUBPRET_INTERRUPT; \</div><div class='add'>+	uint32_t HUBPRET_MEM_PWR_CTRL; \</div><div class='add'>+	uint32_t HUBPRET_MEM_PWR_STATUS; \</div><div class='add'>+	uint32_t HUBPRET_READ_LINE_CTRL0; \</div><div class='add'>+	uint32_t HUBPRET_READ_LINE_CTRL1; \</div><div class='add'>+	uint32_t HUBPRET_READ_LINE0; \</div><div class='add'>+	uint32_t HUBPRET_READ_LINE1; \</div><div class='add'>+	uint32_t HUBPREQ_MEM_PWR_CTRL; \</div><div class='add'>+	uint32_t HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> #define HUBP_SF(reg_name, field_name, post_fix)\</div><div class='ctx'> 	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='hunk'>@@ -622,6 +638,8 @@</div><div class='ctx'> 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\</div><div class='ctx'> 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\</div><div class='ctx'> 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\</div><div class='add'>+	type PIPE_READ_LINE;\</div><div class='add'>+	type HUBP_SEG_ALLOC_ERR_STATUS;\</div><div class='ctx'> 	/* todo:  get these from GVM instead of reading registers ourselves */\</div><div class='ctx'> 	type PAGE_DIRECTORY_ENTRY_HI32;\</div><div class='ctx'> 	type PAGE_DIRECTORY_ENTRY_LO32;\</div><div class='hunk'>@@ -666,10 +684,147 @@ struct dcn_mi_mask {</div><div class='ctx'> 	DCN_HUBP_REG_FIELD_LIST(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn_fl_regs_st {</div><div class='add'>+	uint32_t lut_enable;</div><div class='add'>+	uint32_t lut_done;</div><div class='add'>+	uint32_t lut_addr_mode;</div><div class='add'>+	uint32_t lut_width;</div><div class='add'>+	uint32_t lut_mpc_width;</div><div class='add'>+	uint32_t lut_tmz;</div><div class='add'>+	uint32_t lut_crossbar_sel_r;</div><div class='add'>+	uint32_t lut_crossbar_sel_g;</div><div class='add'>+	uint32_t lut_crossbar_sel_b;</div><div class='add'>+	uint32_t lut_addr_hi;</div><div class='add'>+	uint32_t lut_addr_lo;</div><div class='add'>+	uint32_t refcyc_3dlut_group;</div><div class='add'>+	uint32_t lut_fl_bias;</div><div class='add'>+	uint32_t lut_fl_scale;</div><div class='add'>+	uint32_t lut_fl_mode;</div><div class='add'>+	uint32_t lut_fl_format;</div><div class='add'>+};</div><div class='add'>+struct dcn_hubp_reg_state {</div><div class='add'>+	uint32_t hubp_cntl;</div><div class='add'>+	uint32_t mall_config;</div><div class='add'>+	uint32_t mall_sub_vp;</div><div class='add'>+	uint32_t hubp_req_size_config;</div><div class='add'>+	uint32_t hubp_req_size_config_c;</div><div class='add'>+	uint32_t vmpg_config;</div><div class='add'>+	uint32_t addr_config;</div><div class='add'>+	uint32_t pri_viewport_dimension;</div><div class='add'>+	uint32_t pri_viewport_dimension_c;</div><div class='add'>+	uint32_t pri_viewport_start;</div><div class='add'>+	uint32_t pri_viewport_start_c;</div><div class='add'>+	uint32_t sec_viewport_dimension;</div><div class='add'>+	uint32_t sec_viewport_dimension_c;</div><div class='add'>+	uint32_t sec_viewport_start;</div><div class='add'>+	uint32_t sec_viewport_start_c;</div><div class='add'>+	uint32_t surface_config;</div><div class='add'>+	uint32_t tiling_config;</div><div class='add'>+	uint32_t clk_cntl;</div><div class='add'>+	uint32_t mall_status;</div><div class='add'>+	uint32_t measure_win_ctrl_dcfclk;</div><div class='add'>+	uint32_t measure_win_ctrl_dppclk;</div><div class='add'>+</div><div class='add'>+	uint32_t blank_offset_0;</div><div class='add'>+	uint32_t blank_offset_1;</div><div class='add'>+	uint32_t cursor_settings;</div><div class='add'>+	uint32_t dcn_cur0_ttu_cntl0;</div><div class='add'>+	uint32_t dcn_cur0_ttu_cntl1;</div><div class='add'>+	uint32_t dcn_cur1_ttu_cntl0;</div><div class='add'>+	uint32_t dcn_cur1_ttu_cntl1;</div><div class='add'>+	uint32_t dcn_dmdat_vm_cntl;</div><div class='add'>+	uint32_t dcn_expansion_mode;</div><div class='add'>+	uint32_t dcn_global_ttu_cntl;</div><div class='add'>+	uint32_t dcn_surf0_ttu_cntl0;</div><div class='add'>+	uint32_t dcn_surf0_ttu_cntl1;</div><div class='add'>+	uint32_t dcn_surf1_ttu_cntl0;</div><div class='add'>+	uint32_t dcn_surf1_ttu_cntl1;</div><div class='add'>+	uint32_t dcn_ttu_qos_wm;</div><div class='add'>+	uint32_t dcn_vm_mx_l1_tlb_cntl;</div><div class='add'>+	uint32_t dcn_vm_system_aperture_high_addr;</div><div class='add'>+	uint32_t dcn_vm_system_aperture_low_addr;</div><div class='add'>+	uint32_t dcsurf_flip_control;</div><div class='add'>+	uint32_t dcsurf_flip_control2;</div><div class='add'>+	uint32_t dcsurf_primary_meta_surface_address;</div><div class='add'>+	uint32_t dcsurf_primary_meta_surface_address_c;</div><div class='add'>+	uint32_t dcsurf_primary_meta_surface_address_high;</div><div class='add'>+	uint32_t dcsurf_primary_meta_surface_address_high_c;</div><div class='add'>+	uint32_t dcsurf_primary_surface_address;</div><div class='add'>+	uint32_t dcsurf_primary_surface_address_c;</div><div class='add'>+	uint32_t dcsurf_primary_surface_address_high;</div><div class='add'>+	uint32_t dcsurf_primary_surface_address_high_c;</div><div class='add'>+	uint32_t dcsurf_secondary_meta_surface_address;</div><div class='add'>+	uint32_t dcsurf_secondary_meta_surface_address_c;</div><div class='add'>+	uint32_t dcsurf_secondary_meta_surface_address_high;</div><div class='add'>+	uint32_t dcsurf_secondary_meta_surface_address_high_c;</div><div class='add'>+	uint32_t dcsurf_secondary_surface_address;</div><div class='add'>+	uint32_t dcsurf_secondary_surface_address_c;</div><div class='add'>+	uint32_t dcsurf_secondary_surface_address_high;</div><div class='add'>+	uint32_t dcsurf_secondary_surface_address_high_c;</div><div class='add'>+	uint32_t dcsurf_surface_control;</div><div class='add'>+	uint32_t dcsurf_surface_earliest_inuse;</div><div class='add'>+	uint32_t dcsurf_surface_earliest_inuse_c;</div><div class='add'>+	uint32_t dcsurf_surface_earliest_inuse_high;</div><div class='add'>+	uint32_t dcsurf_surface_earliest_inuse_high_c;</div><div class='add'>+	uint32_t dcsurf_surface_flip_interrupt;</div><div class='add'>+	uint32_t dcsurf_surface_inuse;</div><div class='add'>+	uint32_t dcsurf_surface_inuse_c;</div><div class='add'>+	uint32_t dcsurf_surface_inuse_high;</div><div class='add'>+	uint32_t dcsurf_surface_inuse_high_c;</div><div class='add'>+	uint32_t dcsurf_surface_pitch;</div><div class='add'>+	uint32_t dcsurf_surface_pitch_c;</div><div class='add'>+	uint32_t dst_after_scaler;</div><div class='add'>+	uint32_t dst_dimensions;</div><div class='add'>+	uint32_t dst_y_delta_drq_limit;</div><div class='add'>+	uint32_t flip_parameters_0;</div><div class='add'>+	uint32_t flip_parameters_1;</div><div class='add'>+	uint32_t flip_parameters_2;</div><div class='add'>+	uint32_t flip_parameters_3;</div><div class='add'>+	uint32_t flip_parameters_4;</div><div class='add'>+	uint32_t flip_parameters_5;</div><div class='add'>+	uint32_t flip_parameters_6;</div><div class='add'>+	uint32_t hubpreq_mem_pwr_ctrl;</div><div class='add'>+	uint32_t hubpreq_mem_pwr_status;</div><div class='add'>+	uint32_t nom_parameters_0;</div><div class='add'>+	uint32_t nom_parameters_1;</div><div class='add'>+	uint32_t nom_parameters_2;</div><div class='add'>+	uint32_t nom_parameters_3;</div><div class='add'>+	uint32_t nom_parameters_4;</div><div class='add'>+	uint32_t nom_parameters_5;</div><div class='add'>+	uint32_t nom_parameters_6;</div><div class='add'>+	uint32_t nom_parameters_7;</div><div class='add'>+	uint32_t per_line_delivery;</div><div class='add'>+	uint32_t per_line_delivery_pre;</div><div class='add'>+	uint32_t prefetch_settings;</div><div class='add'>+	uint32_t prefetch_settings_c;</div><div class='add'>+	uint32_t ref_freq_to_pix_freq;</div><div class='add'>+	uint32_t uclk_pstate_force;</div><div class='add'>+	uint32_t vblank_parameters_0;</div><div class='add'>+	uint32_t vblank_parameters_1;</div><div class='add'>+	uint32_t vblank_parameters_2;</div><div class='add'>+	uint32_t vblank_parameters_3;</div><div class='add'>+	uint32_t vblank_parameters_4;</div><div class='add'>+	uint32_t vblank_parameters_5;</div><div class='add'>+	uint32_t vblank_parameters_6;</div><div class='add'>+	uint32_t vmid_settings_0;</div><div class='add'>+</div><div class='add'>+	uint32_t hubpret_control;</div><div class='add'>+	uint32_t hubpret_interrupt;</div><div class='add'>+	uint32_t hubpret_mem_pwr_ctrl;</div><div class='add'>+	uint32_t hubpret_mem_pwr_status;</div><div class='add'>+	uint32_t hubpret_read_line_ctrl0;</div><div class='add'>+	uint32_t hubpret_read_line_ctrl1;</div><div class='add'>+	uint32_t hubpret_read_line_status;</div><div class='add'>+	uint32_t hubpret_read_line_value;</div><div class='add'>+	uint32_t hubpret_read_line0;</div><div class='add'>+	uint32_t hubpret_read_line1;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dcn_hubp_state {</div><div class='ctx'> 	struct _vcs_dpi_display_dlg_regs_st dlg_attr;</div><div class='ctx'> 	struct _vcs_dpi_display_ttu_regs_st ttu_attr;</div><div class='ctx'> 	struct _vcs_dpi_display_rq_regs_st rq_regs;</div><div class='add'>+	struct dcn_fl_regs_st fl_regs;</div><div class='ctx'> 	uint32_t pixel_format;</div><div class='ctx'> 	uint32_t inuse_addr_hi;</div><div class='ctx'> 	uint32_t inuse_addr_lo;</div><div class='hunk'>@@ -692,8 +847,8 @@ struct dcn_hubp_state {</div><div class='ctx'> 	uint32_t primary_meta_addr_hi;</div><div class='ctx'> 	uint32_t uclk_pstate_force;</div><div class='ctx'> 	uint32_t hubp_cntl;</div><div class='add'>+	uint32_t flip_control;</div><div class='ctx'> };</div><div class='del'>-</div><div class='ctx'> struct dcn10_hubp {</div><div class='ctx'> 	struct hubp base;</div><div class='ctx'> 	struct dcn_hubp_state state;</div><div class='hunk'>@@ -705,7 +860,7 @@ struct dcn10_hubp {</div><div class='ctx'> void hubp1_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -738,13 +893,15 @@ void hubp1_program_rotation(</div><div class='ctx'> </div><div class='ctx'> void hubp1_program_tiling(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='del'>-	const union dc_tiling_info *info,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='ctx'> 	const enum surface_pixel_format pixel_format);</div><div class='ctx'> </div><div class='ctx'> void hubp1_dcc_control(struct hubp *hubp,</div><div class='ctx'> 		bool enable,</div><div class='ctx'> 		enum hubp_ind_block_size independent_64b_blks);</div><div class='ctx'> </div><div class='add'>+void hubp_reset(struct hubp *hubp);</div><div class='add'>+</div><div class='ctx'> bool hubp1_program_surface_flip_and_addr(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	const struct dc_plane_address *address,</div><div class='hunk'>@@ -793,4 +950,6 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset);</div><div class='ctx'> </div><div class='ctx'> void hubp1_set_flip_int(struct hubp *hubp);</div><div class='ctx'> </div><div class='add'>+void hubp1_clear_tiling(struct hubp *hubp);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c<br/>index 89c3bf0fe0c9..92288de4cc10 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c</a></div><div class='hunk'>@@ -310,7 +310,7 @@ void hubp2_setup_interdependent(</div><div class='ctx'>  */</div><div class='ctx'> static void hubp2_program_tiling(</div><div class='ctx'> 	struct dcn20_hubp *hubp2,</div><div class='del'>-	const union dc_tiling_info *info,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='ctx'> 	const enum surface_pixel_format pixel_format)</div><div class='ctx'> {</div><div class='ctx'> 	REG_UPDATE_3(DCSURF_ADDR_CONFIG,</div><div class='hunk'>@@ -406,6 +406,20 @@ void hubp2_program_rotation(</div><div class='ctx'> 				H_MIRROR_EN, mirror);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hubp2_clear_tiling(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);</div><div class='add'>+	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,</div><div class='add'>+		     PRIMARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		     PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,</div><div class='add'>+		     SECONDARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		     SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hubp2_dcc_control(struct hubp *hubp, bool enable,</div><div class='ctx'> 		enum hubp_ind_block_size independent_64b_blks)</div><div class='ctx'> {</div><div class='hunk'>@@ -536,7 +550,7 @@ void hubp2_program_pixel_format(</div><div class='ctx'> void hubp2_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -599,26 +613,28 @@ void hubp2_cursor_set_attributes(</div><div class='ctx'> </div><div class='ctx'> 	hubp-&gt;curs_attr = *attr;</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,</div><div class='del'>-			CURSOR_SURFACE_ADDRESS_HIGH, attr-&gt;address.high_part);</div><div class='del'>-	REG_UPDATE(CURSOR_SURFACE_ADDRESS,</div><div class='del'>-			CURSOR_SURFACE_ADDRESS, attr-&gt;address.low_part);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE_2(CURSOR_SIZE,</div><div class='del'>-			CURSOR_WIDTH, attr-&gt;width,</div><div class='del'>-			CURSOR_HEIGHT, attr-&gt;height);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE_4(CURSOR_CONTROL,</div><div class='del'>-			CURSOR_MODE, attr-&gt;color_format,</div><div class='del'>-			CURSOR_2X_MAGNIFY, attr-&gt;attribute_flags.bits.ENABLE_MAGNIFICATION,</div><div class='del'>-			CURSOR_PITCH, hw_pitch,</div><div class='del'>-			CURSOR_LINES_PER_CHUNK, lpc);</div><div class='del'>-</div><div class='del'>-	REG_SET_2(CURSOR_SETTINGS, 0,</div><div class='del'>-			/* no shift of the cursor HDL schedule */</div><div class='del'>-			CURSOR0_DST_Y_OFFSET, 0,</div><div class='del'>-			 /* used to shift the cursor chunk request deadline */</div><div class='del'>-			CURSOR0_CHUNK_HDL_ADJUST, 3);</div><div class='add'>+	if (!hubp-&gt;cursor_offload) {</div><div class='add'>+		REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				CURSOR_SURFACE_ADDRESS_HIGH, attr-&gt;address.high_part);</div><div class='add'>+		REG_UPDATE(CURSOR_SURFACE_ADDRESS,</div><div class='add'>+				CURSOR_SURFACE_ADDRESS, attr-&gt;address.low_part);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(CURSOR_SIZE,</div><div class='add'>+				CURSOR_WIDTH, attr-&gt;width,</div><div class='add'>+				CURSOR_HEIGHT, attr-&gt;height);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_4(CURSOR_CONTROL,</div><div class='add'>+				CURSOR_MODE, attr-&gt;color_format,</div><div class='add'>+				CURSOR_2X_MAGNIFY, attr-&gt;attribute_flags.bits.ENABLE_MAGNIFICATION,</div><div class='add'>+				CURSOR_PITCH, hw_pitch,</div><div class='add'>+				CURSOR_LINES_PER_CHUNK, lpc);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(CURSOR_SETTINGS, 0,</div><div class='add'>+				/* no shift of the cursor HDL schedule */</div><div class='add'>+				CURSOR0_DST_Y_OFFSET, 0,</div><div class='add'>+				/* used to shift the cursor chunk request deadline */</div><div class='add'>+				CURSOR0_CHUNK_HDL_ADJUST, 3);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	hubp-&gt;att.SURFACE_ADDR_HIGH  = attr-&gt;address.high_part;</div><div class='ctx'> 	hubp-&gt;att.SURFACE_ADDR       = attr-&gt;address.low_part;</div><div class='hunk'>@@ -927,7 +943,8 @@ bool hubp2_is_flip_pending(struct hubp *hubp)</div><div class='ctx'> 	if (flip_pending)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='del'>-	if (earliest_inuse_address.grph.addr.quad_part != hubp-&gt;request_address.grph.addr.quad_part)</div><div class='add'>+	if (hubp &amp;&amp;</div><div class='add'>+	    earliest_inuse_address.grph.addr.quad_part != hubp-&gt;request_address.grph.addr.quad_part)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -1043,22 +1060,29 @@ void hubp2_cursor_set_position(</div><div class='ctx'> 	if (src_y_offset + cursor_height &lt;= 0)</div><div class='ctx'> 		cur_en = 0;  /* not visible beyond top edge*/</div><div class='ctx'> </div><div class='del'>-	if (cur_en &amp;&amp; REG_READ(CURSOR_SURFACE_ADDRESS) == 0)</div><div class='del'>-		hubp-&gt;funcs-&gt;set_cursor_attributes(hubp, &amp;hubp-&gt;curs_attr);</div><div class='add'>+	if (hubp-&gt;pos.cur_ctl.bits.cur_enable != cur_en) {</div><div class='add'>+		bool cursor_not_programmed = hubp-&gt;att.SURFACE_ADDR == 0 &amp;&amp; hubp-&gt;att.SURFACE_ADDR_HIGH == 0;</div><div class='add'>+</div><div class='add'>+		if (cur_en &amp;&amp; cursor_not_programmed)</div><div class='add'>+			hubp-&gt;funcs-&gt;set_cursor_attributes(hubp, &amp;hubp-&gt;curs_attr);</div><div class='add'>+</div><div class='add'>+		if (!hubp-&gt;cursor_offload)</div><div class='add'>+			REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, cur_en);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(CURSOR_CONTROL,</div><div class='del'>-			CURSOR_ENABLE, cur_en);</div><div class='add'>+	if (!hubp-&gt;cursor_offload) {</div><div class='add'>+		REG_SET_2(CURSOR_POSITION, 0,</div><div class='add'>+				CURSOR_X_POSITION, pos-&gt;x,</div><div class='add'>+				CURSOR_Y_POSITION, pos-&gt;y);</div><div class='ctx'> </div><div class='del'>-	REG_SET_2(CURSOR_POSITION, 0,</div><div class='del'>-			CURSOR_X_POSITION, pos-&gt;x,</div><div class='del'>-			CURSOR_Y_POSITION, pos-&gt;y);</div><div class='add'>+		REG_SET_2(CURSOR_HOT_SPOT, 0,</div><div class='add'>+				CURSOR_HOT_SPOT_X, pos-&gt;x_hotspot,</div><div class='add'>+				CURSOR_HOT_SPOT_Y, pos-&gt;y_hotspot);</div><div class='ctx'> </div><div class='del'>-	REG_SET_2(CURSOR_HOT_SPOT, 0,</div><div class='del'>-			CURSOR_HOT_SPOT_X, pos-&gt;x_hotspot,</div><div class='del'>-			CURSOR_HOT_SPOT_Y, pos-&gt;y_hotspot);</div><div class='add'>+		REG_SET(CURSOR_DST_OFFSET, 0,</div><div class='add'>+				CURSOR_DST_X_OFFSET, dst_x_offset);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	REG_SET(CURSOR_DST_OFFSET, 0,</div><div class='del'>-			CURSOR_DST_X_OFFSET, dst_x_offset);</div><div class='ctx'> 	/* TODO Handle surface pixel formats other than 4:4:4 */</div><div class='ctx'> 	/* Cursor Position Register Config */</div><div class='ctx'> 	hubp-&gt;pos.cur_ctl.bits.cur_enable = cur_en;</div><div class='hunk'>@@ -1331,6 +1355,12 @@ void hubp2_read_state(struct hubp *hubp)</div><div class='ctx'> 		SWATH_HEIGHT_C, &amp;rq_regs-&gt;rq_regs_c.swath_height,</div><div class='ctx'> 		PTE_ROW_HEIGHT_LINEAR_C, &amp;rq_regs-&gt;rq_regs_c.pte_row_height_linear);</div><div class='ctx'> </div><div class='add'>+	if (REG(DCHUBP_CNTL))</div><div class='add'>+		s-&gt;hubp_cntl = REG_READ(DCHUBP_CNTL);</div><div class='add'>+</div><div class='add'>+	if (REG(DCSURF_FLIP_CONTROL))</div><div class='add'>+		s-&gt;flip_control = REG_READ(DCSURF_FLIP_CONTROL);</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hubp2_validate_dml_output(struct hubp *hubp,</div><div class='hunk'>@@ -1653,6 +1683,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {</div><div class='ctx'> 	.set_blank = hubp2_set_blank,</div><div class='ctx'> 	.set_blank_regs = hubp2_set_blank_regs,</div><div class='ctx'> 	.dcc_control = hubp2_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.set_cursor_attributes	= hubp2_cursor_set_attributes,</div><div class='ctx'> 	.set_cursor_position	= hubp2_cursor_set_position,</div><div class='hunk'>@@ -1669,6 +1700,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {</div><div class='ctx'> 	.hubp_in_blank = hubp1_in_blank,</div><div class='ctx'> 	.hubp_soft_reset = hubp1_soft_reset,</div><div class='ctx'> 	.hubp_set_flip_int = hubp1_set_flip_int,</div><div class='add'>+	.hubp_clear_tiling = hubp2_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h<br/>index efa2adf4f83d..7062e6653062 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h</a></div><div class='hunk'>@@ -145,9 +145,10 @@</div><div class='ctx'> 	uint32_t FLIP_PARAMETERS_2;\</div><div class='ctx'> 	uint32_t DCN_CUR1_TTU_CNTL0;\</div><div class='ctx'> 	uint32_t DCN_CUR1_TTU_CNTL1;\</div><div class='del'>-	uint32_t VMID_SETTINGS_0</div><div class='del'>-</div><div class='add'>+	uint32_t VMID_SETTINGS_0;\</div><div class='add'>+	uint32_t DST_Y_DELTA_DRQ_LIMIT</div><div class='ctx'> </div><div class='add'>+/*shared with dcn3.x*/</div><div class='ctx'> #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \</div><div class='ctx'> 	DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \</div><div class='ctx'> 	uint32_t FLIP_PARAMETERS_3;\</div><div class='hunk'>@@ -167,6 +168,20 @@</div><div class='ctx'> 	uint32_t DCHUBP_VMPG_CONFIG;\</div><div class='ctx'> 	uint32_t UCLK_PSTATE_FORCE</div><div class='ctx'> </div><div class='add'>+#define DCN401_HUBP_REG_COMMON_VARIABLE_LIST \</div><div class='add'>+	DCN32_HUBP_REG_COMMON_VARIABLE_LIST;\</div><div class='add'>+	uint32_t _3DLUT_FL_BIAS_SCALE;\</div><div class='add'>+	uint32_t _3DLUT_FL_CONFIG;\</div><div class='add'>+	uint32_t HUBP_3DLUT_ADDRESS_HIGH;\</div><div class='add'>+	uint32_t HUBP_3DLUT_ADDRESS_LOW;\</div><div class='add'>+	uint32_t HUBP_3DLUT_CONTROL;\</div><div class='add'>+	uint32_t HUBP_3DLUT_DLG_PARAM;\</div><div class='add'>+	uint32_t DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE;\</div><div class='add'>+	uint32_t DCHUBP_MCACHEID_CONFIG;\</div><div class='add'>+	uint32_t DCHUBP_MALL_SUB_VP;\</div><div class='add'>+	uint32_t DCHUBP_ADDR_CONFIG;\</div><div class='add'>+	uint32_t HUBP_MALL_STATUS</div><div class='add'>+</div><div class='ctx'> #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \</div><div class='ctx'> 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \</div><div class='ctx'> 	type DMDATA_ADDRESS_HIGH;\</div><div class='hunk'>@@ -241,16 +256,48 @@</div><div class='ctx'> 	type CURSOR_UCLK_PSTATE_FORCE_EN; \</div><div class='ctx'> 	type CURSOR_UCLK_PSTATE_FORCE_VALUE</div><div class='ctx'> </div><div class='add'>+#define DCN401_HUBP_REG_FIELD_VARIABLE_LIST(type) \</div><div class='add'>+	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type);\</div><div class='add'>+	type MALL_PREF_CMD_TYPE; \</div><div class='add'>+	type MALL_PREF_MODE; \</div><div class='add'>+	type HUBP0_3DLUT_FL_MODE; \</div><div class='add'>+	type HUBP0_3DLUT_FL_FORMAT; \</div><div class='add'>+	type HUBP0_3DLUT_FL_SCALE; \</div><div class='add'>+	type HUBP0_3DLUT_FL_BIAS; \</div><div class='add'>+	type HUBP_3DLUT_ENABLE;\</div><div class='add'>+	type HUBP_3DLUT_DONE;\</div><div class='add'>+	type HUBP_3DLUT_ADDRESSING_MODE;\</div><div class='add'>+	type HUBP_3DLUT_WIDTH;\</div><div class='add'>+	type HUBP_3DLUT_MPC_WIDTH;\</div><div class='add'>+	type HUBP_3DLUT_TMZ;\</div><div class='add'>+	type HUBP_3DLUT_CROSSBAR_SELECT_Y_G;\</div><div class='add'>+	type HUBP_3DLUT_CROSSBAR_SELECT_CB_B;\</div><div class='add'>+	type HUBP_3DLUT_CROSSBAR_SELECT_CR_R;\</div><div class='add'>+	type HUBP_3DLUT_ADDRESS_HIGH;\</div><div class='add'>+	type HUBP_3DLUT_ADDRESS_LOW;\</div><div class='add'>+	type REFCYC_PER_3DLUT_GROUP;\</div><div class='add'>+	type VIEWPORT_MCACHE_SPLIT_COORDINATE;\</div><div class='add'>+	type VIEWPORT_MCACHE_SPLIT_COORDINATE_C;\</div><div class='add'>+	type MCACHEID_REG_READ_1H_P0;\</div><div class='add'>+	type MCACHEID_REG_READ_2H_P0;\</div><div class='add'>+	type MCACHEID_REG_READ_1H_P1;\</div><div class='add'>+	type MCACHEID_REG_READ_2H_P1;\</div><div class='add'>+	type MCACHEID_MALL_PREF_1H_P0;\</div><div class='add'>+	type MCACHEID_MALL_PREF_2H_P0;\</div><div class='add'>+	type MCACHEID_MALL_PREF_1H_P1;\</div><div class='add'>+	type MCACHEID_MALL_PREF_2H_P1;\</div><div class='add'>+	type HUBP_FGCG_REP_DIS</div><div class='add'>+</div><div class='ctx'> struct dcn_hubp2_registers {</div><div class='del'>-	DCN32_HUBP_REG_COMMON_VARIABLE_LIST;</div><div class='add'>+	DCN401_HUBP_REG_COMMON_VARIABLE_LIST;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn_hubp2_shift {</div><div class='del'>-	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);</div><div class='add'>+	DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn_hubp2_mask {</div><div class='del'>-	DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);</div><div class='add'>+	DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn20_hubp {</div><div class='hunk'>@@ -339,7 +386,7 @@ void hubp2_program_pixel_format(</div><div class='ctx'> void hubp2_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -366,6 +413,8 @@ void hubp2_read_state_common(struct hubp *hubp);</div><div class='ctx'> </div><div class='ctx'> void hubp2_read_state(struct hubp *hubp);</div><div class='ctx'> </div><div class='add'>+void hubp2_clear_tiling(struct hubp *hubp);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_MEM_INPUT_DCN20_H__ */</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c<br/>index 35dd4bac242a..ec88ee424a7f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c</a></div><div class='hunk'>@@ -42,7 +42,7 @@</div><div class='ctx'> static void hubp201_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -77,6 +77,7 @@ static void hubp201_program_requestor(struct hubp *hubp,</div><div class='ctx'> 			MRQ_EXPANSION_MODE, rq_regs-&gt;mrq_expansion_mode,</div><div class='ctx'> 			CRQ_EXPANSION_MODE, rq_regs-&gt;crq_expansion_mode);</div><div class='ctx'> </div><div class='add'>+	/* no need to program PTE */</div><div class='ctx'> 	REG_SET_5(DCHUBP_REQ_SIZE_CONFIG, 0,</div><div class='ctx'> 		CHUNK_SIZE, rq_regs-&gt;rq_regs_l.chunk_size,</div><div class='ctx'> 		MIN_CHUNK_SIZE, rq_regs-&gt;rq_regs_l.min_chunk_size,</div><div class='hunk'>@@ -99,6 +100,10 @@ static void hubp201_setup(</div><div class='ctx'> 		struct _vcs_dpi_display_rq_regs_st *rq_regs,</div><div class='ctx'> 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)</div><div class='ctx'> {</div><div class='add'>+	/*</div><div class='add'>+	 * otg is locked when this func is called. Register are double buffered.</div><div class='add'>+	 * disable the requestors is not needed</div><div class='add'>+	 */</div><div class='ctx'> 	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);</div><div class='ctx'> 	hubp201_program_requestor(hubp, rq_regs);</div><div class='ctx'> 	hubp201_program_deadline(hubp, dlg_attr, ttu_attr);</div><div class='hunk'>@@ -116,6 +121,7 @@ static struct hubp_funcs dcn201_hubp_funcs = {</div><div class='ctx'> 	.set_cursor_position	= hubp1_cursor_set_position,</div><div class='ctx'> 	.set_blank = hubp1_set_blank,</div><div class='ctx'> 	.dcc_control = hubp1_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.hubp_clk_cntl = hubp1_clk_cntl,</div><div class='ctx'> 	.hubp_vtg_sel = hubp1_vtg_sel,</div><div class='hunk'>@@ -126,6 +132,7 @@ static struct hubp_funcs dcn201_hubp_funcs = {</div><div class='ctx'> 	.hubp_clear_underflow = hubp1_clear_underflow,</div><div class='ctx'> 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,</div><div class='ctx'> 	.hubp_init = hubp1_init,</div><div class='add'>+	.hubp_clear_tiling = hubp1_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool dcn201_hubp_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h<br/>index a1e3384eed63..a1e3384eed63 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c<br/>index e13d69a22c1c..08ea0a1b9e7f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c</a></div><div class='hunk'>@@ -73,8 +73,6 @@</div><div class='ctx'>  * On any mode switch, if the new reg values are smaller than the current values,</div><div class='ctx'>  * then update the regs with the new values.</div><div class='ctx'>  *</div><div class='del'>- * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142</div><div class='del'>- *</div><div class='ctx'>  */</div><div class='ctx'> void apply_DEDCN21_142_wa_for_hostvm_deadline(</div><div class='ctx'> 		struct hubp *hubp,</div><div class='hunk'>@@ -811,6 +809,8 @@ static void hubp21_init(struct hubp *hubp)</div><div class='ctx'> 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);</div><div class='ctx'> 	//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;</div><div class='ctx'> 	REG_WRITE(HUBPREQ_DEBUG, 1 &lt;&lt; 26);</div><div class='add'>+</div><div class='add'>+	hubp_reset(hubp);</div><div class='ctx'> }</div><div class='ctx'> static struct hubp_funcs dcn21_hubp_funcs = {</div><div class='ctx'> 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,</div><div class='hunk'>@@ -823,6 +823,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {</div><div class='ctx'> 	.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,</div><div class='ctx'> 	.set_blank = hubp1_set_blank,</div><div class='ctx'> 	.dcc_control = hubp1_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = hubp21_set_viewport,</div><div class='ctx'> 	.set_cursor_attributes	= hubp2_cursor_set_attributes,</div><div class='ctx'> 	.set_cursor_position	= hubp1_cursor_set_position,</div><div class='hunk'>@@ -837,6 +838,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {</div><div class='ctx'> 	.hubp_init = hubp21_init,</div><div class='ctx'> 	.validate_dml_output = hubp21_validate_dml_output,</div><div class='ctx'> 	.hubp_set_flip_int = hubp1_set_flip_int,</div><div class='add'>+	.hubp_clear_tiling = hubp1_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool hubp21_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h<br/>index 9873b6cbc5ba..9873b6cbc5ba 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c<br/>index 75547ce86c09..0cc6f4558989 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c</a></div><div class='hunk'>@@ -318,7 +318,7 @@ bool hubp3_program_surface_flip_and_addr(</div><div class='ctx'> </div><div class='ctx'> void hubp3_program_tiling(</div><div class='ctx'> 	struct dcn20_hubp *hubp2,</div><div class='del'>-	const union dc_tiling_info *info,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='ctx'> 	const enum surface_pixel_format pixel_format)</div><div class='ctx'> {</div><div class='ctx'> 	REG_UPDATE_4(DCSURF_ADDR_CONFIG,</div><div class='hunk'>@@ -334,6 +334,22 @@ void hubp3_program_tiling(</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void hubp3_clear_tiling(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);</div><div class='add'>+	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_6(DCSURF_SURFACE_CONTROL,</div><div class='add'>+		PRIMARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		PRIMARY_SURFACE_DCC_IND_BLK, 0,</div><div class='add'>+		PRIMARY_SURFACE_DCC_IND_BLK_C, 0,</div><div class='add'>+		SECONDARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		SECONDARY_SURFACE_DCC_IND_BLK, 0,</div><div class='add'>+		SECONDARY_SURFACE_DCC_IND_BLK_C, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hubp3_dcc_control(struct hubp *hubp, bool enable,</div><div class='ctx'> 		enum hubp_ind_block_size blk_size)</div><div class='ctx'> {</div><div class='hunk'>@@ -395,7 +411,7 @@ void hubp3_dmdata_set_attributes(</div><div class='ctx'> void hubp3_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -455,6 +471,129 @@ void hubp3_read_state(struct hubp *hubp)</div><div class='ctx'> 	if (REG(DCHUBP_CNTL))</div><div class='ctx'> 		s-&gt;hubp_cntl = REG_READ(DCHUBP_CNTL);</div><div class='ctx'> </div><div class='add'>+	if (REG(DCSURF_FLIP_CONTROL))</div><div class='add'>+		s-&gt;flip_control = REG_READ(DCSURF_FLIP_CONTROL);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	reg_state-&gt;hubp_cntl = REG_READ(DCHUBP_CNTL);</div><div class='add'>+	reg_state-&gt;mall_config = REG_READ(DCHUBP_MALL_CONFIG);</div><div class='add'>+	reg_state-&gt;mall_sub_vp = REG_READ(DCHUBP_MALL_SUB_VP);</div><div class='add'>+	reg_state-&gt;hubp_req_size_config = REG_READ(DCHUBP_REQ_SIZE_CONFIG);</div><div class='add'>+	reg_state-&gt;hubp_req_size_config_c = REG_READ(DCHUBP_REQ_SIZE_CONFIG_C);</div><div class='add'>+	reg_state-&gt;vmpg_config = REG_READ(DCHUBP_VMPG_CONFIG);</div><div class='add'>+	reg_state-&gt;addr_config = REG_READ(DCSURF_ADDR_CONFIG);</div><div class='add'>+	reg_state-&gt;pri_viewport_dimension = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION);</div><div class='add'>+	reg_state-&gt;pri_viewport_dimension_c = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION_C);</div><div class='add'>+	reg_state-&gt;pri_viewport_start = REG_READ(DCSURF_PRI_VIEWPORT_START);</div><div class='add'>+	reg_state-&gt;pri_viewport_start_c = REG_READ(DCSURF_PRI_VIEWPORT_START_C);</div><div class='add'>+	reg_state-&gt;sec_viewport_dimension = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION);</div><div class='add'>+	reg_state-&gt;sec_viewport_dimension_c = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION_C);</div><div class='add'>+	reg_state-&gt;sec_viewport_start = REG_READ(DCSURF_SEC_VIEWPORT_START);</div><div class='add'>+	reg_state-&gt;sec_viewport_start_c = REG_READ(DCSURF_SEC_VIEWPORT_START_C);</div><div class='add'>+	reg_state-&gt;surface_config = REG_READ(DCSURF_SURFACE_CONFIG);</div><div class='add'>+	reg_state-&gt;tiling_config = REG_READ(DCSURF_TILING_CONFIG);</div><div class='add'>+	reg_state-&gt;clk_cntl = REG_READ(HUBP_CLK_CNTL);</div><div class='add'>+	reg_state-&gt;mall_status = REG_READ(HUBP_MALL_STATUS);</div><div class='add'>+	reg_state-&gt;measure_win_ctrl_dcfclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DCFCLK);</div><div class='add'>+	reg_state-&gt;measure_win_ctrl_dppclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DPPCLK);</div><div class='add'>+</div><div class='add'>+	reg_state-&gt;blank_offset_0 = REG_READ(BLANK_OFFSET_0);</div><div class='add'>+	reg_state-&gt;blank_offset_1 = REG_READ(BLANK_OFFSET_1);</div><div class='add'>+	reg_state-&gt;cursor_settings = REG_READ(CURSOR_SETTINGS);</div><div class='add'>+	reg_state-&gt;dcn_cur0_ttu_cntl0 = REG_READ(DCN_CUR0_TTU_CNTL0);</div><div class='add'>+	reg_state-&gt;dcn_cur0_ttu_cntl1 = REG_READ(DCN_CUR0_TTU_CNTL1);</div><div class='add'>+	reg_state-&gt;dcn_cur1_ttu_cntl0 = REG_READ(DCN_CUR1_TTU_CNTL0);</div><div class='add'>+	reg_state-&gt;dcn_cur1_ttu_cntl1 = REG_READ(DCN_CUR1_TTU_CNTL1);</div><div class='add'>+	reg_state-&gt;dcn_dmdat_vm_cntl = REG_READ(DCN_DMDATA_VM_CNTL);</div><div class='add'>+	reg_state-&gt;dcn_expansion_mode = REG_READ(DCN_EXPANSION_MODE);</div><div class='add'>+	reg_state-&gt;dcn_global_ttu_cntl = REG_READ(DCN_GLOBAL_TTU_CNTL);</div><div class='add'>+	reg_state-&gt;dcn_surf0_ttu_cntl0 = REG_READ(DCN_SURF0_TTU_CNTL0);</div><div class='add'>+	reg_state-&gt;dcn_surf0_ttu_cntl1 = REG_READ(DCN_SURF0_TTU_CNTL1);</div><div class='add'>+	reg_state-&gt;dcn_surf1_ttu_cntl0 = REG_READ(DCN_SURF1_TTU_CNTL0);</div><div class='add'>+	reg_state-&gt;dcn_surf1_ttu_cntl1 = REG_READ(DCN_SURF1_TTU_CNTL1);</div><div class='add'>+	reg_state-&gt;dcn_ttu_qos_wm = REG_READ(DCN_TTU_QOS_WM);</div><div class='add'>+	reg_state-&gt;dcn_vm_mx_l1_tlb_cntl = REG_READ(DCN_VM_MX_L1_TLB_CNTL);</div><div class='add'>+	reg_state-&gt;dcn_vm_system_aperture_high_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR);</div><div class='add'>+	reg_state-&gt;dcn_vm_system_aperture_low_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_LOW_ADDR);</div><div class='add'>+	reg_state-&gt;dcsurf_flip_control = REG_READ(DCSURF_FLIP_CONTROL);</div><div class='add'>+	reg_state-&gt;dcsurf_flip_control2 = REG_READ(DCSURF_FLIP_CONTROL2);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_meta_surface_address = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_meta_surface_address_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_meta_surface_address_high = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_meta_surface_address_high_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_surface_address = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_surface_address_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_C);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_surface_address_high = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH);</div><div class='add'>+	reg_state-&gt;dcsurf_primary_surface_address_high_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_meta_surface_address = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_meta_surface_address_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_meta_surface_address_high = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_meta_surface_address_high_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_surface_address = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_surface_address_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_C);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_surface_address_high = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH);</div><div class='add'>+	reg_state-&gt;dcsurf_secondary_surface_address_high_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_control = REG_READ(DCSURF_SURFACE_CONTROL);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_earliest_inuse = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_earliest_inuse_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_C);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_earliest_inuse_high = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_earliest_inuse_high_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_flip_interrupt = REG_READ(DCSURF_SURFACE_FLIP_INTERRUPT);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_inuse = REG_READ(DCSURF_SURFACE_INUSE);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_inuse_c = REG_READ(DCSURF_SURFACE_INUSE_C);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_inuse_high = REG_READ(DCSURF_SURFACE_INUSE_HIGH);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_inuse_high_c = REG_READ(DCSURF_SURFACE_INUSE_HIGH_C);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_pitch = REG_READ(DCSURF_SURFACE_PITCH);</div><div class='add'>+	reg_state-&gt;dcsurf_surface_pitch_c = REG_READ(DCSURF_SURFACE_PITCH_C);</div><div class='add'>+	reg_state-&gt;dst_after_scaler = REG_READ(DST_AFTER_SCALER);</div><div class='add'>+	reg_state-&gt;dst_dimensions = REG_READ(DST_DIMENSIONS);</div><div class='add'>+	reg_state-&gt;dst_y_delta_drq_limit = REG_READ(DST_Y_DELTA_DRQ_LIMIT);</div><div class='add'>+	reg_state-&gt;flip_parameters_0 = REG_READ(FLIP_PARAMETERS_0);</div><div class='add'>+	reg_state-&gt;flip_parameters_1 = REG_READ(FLIP_PARAMETERS_1);</div><div class='add'>+	reg_state-&gt;flip_parameters_2 = REG_READ(FLIP_PARAMETERS_2);</div><div class='add'>+	reg_state-&gt;flip_parameters_3 = REG_READ(FLIP_PARAMETERS_3);</div><div class='add'>+	reg_state-&gt;flip_parameters_4 = REG_READ(FLIP_PARAMETERS_4);</div><div class='add'>+	reg_state-&gt;flip_parameters_5 = REG_READ(FLIP_PARAMETERS_5);</div><div class='add'>+	reg_state-&gt;flip_parameters_6 = REG_READ(FLIP_PARAMETERS_6);</div><div class='add'>+	reg_state-&gt;hubpreq_mem_pwr_ctrl = REG_READ(HUBPREQ_MEM_PWR_CTRL);</div><div class='add'>+	reg_state-&gt;hubpreq_mem_pwr_status = REG_READ(HUBPREQ_MEM_PWR_STATUS);</div><div class='add'>+	reg_state-&gt;nom_parameters_0 = REG_READ(NOM_PARAMETERS_0);</div><div class='add'>+	reg_state-&gt;nom_parameters_1 = REG_READ(NOM_PARAMETERS_1);</div><div class='add'>+	reg_state-&gt;nom_parameters_2 = REG_READ(NOM_PARAMETERS_2);</div><div class='add'>+	reg_state-&gt;nom_parameters_3 = REG_READ(NOM_PARAMETERS_3);</div><div class='add'>+	reg_state-&gt;nom_parameters_4 = REG_READ(NOM_PARAMETERS_4);</div><div class='add'>+	reg_state-&gt;nom_parameters_5 = REG_READ(NOM_PARAMETERS_5);</div><div class='add'>+	reg_state-&gt;nom_parameters_6 = REG_READ(NOM_PARAMETERS_6);</div><div class='add'>+	reg_state-&gt;nom_parameters_7 = REG_READ(NOM_PARAMETERS_7);</div><div class='add'>+	reg_state-&gt;per_line_delivery = REG_READ(PER_LINE_DELIVERY);</div><div class='add'>+	reg_state-&gt;per_line_delivery_pre = REG_READ(PER_LINE_DELIVERY_PRE);</div><div class='add'>+	reg_state-&gt;prefetch_settings = REG_READ(PREFETCH_SETTINGS);</div><div class='add'>+	reg_state-&gt;prefetch_settings_c = REG_READ(PREFETCH_SETTINGS_C);</div><div class='add'>+	reg_state-&gt;ref_freq_to_pix_freq = REG_READ(REF_FREQ_TO_PIX_FREQ);</div><div class='add'>+	reg_state-&gt;uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);</div><div class='add'>+	reg_state-&gt;vblank_parameters_0 = REG_READ(VBLANK_PARAMETERS_0);</div><div class='add'>+	reg_state-&gt;vblank_parameters_1 = REG_READ(VBLANK_PARAMETERS_1);</div><div class='add'>+	reg_state-&gt;vblank_parameters_2 = REG_READ(VBLANK_PARAMETERS_2);</div><div class='add'>+	reg_state-&gt;vblank_parameters_3 = REG_READ(VBLANK_PARAMETERS_3);</div><div class='add'>+	reg_state-&gt;vblank_parameters_4 = REG_READ(VBLANK_PARAMETERS_4);</div><div class='add'>+	reg_state-&gt;vblank_parameters_5 = REG_READ(VBLANK_PARAMETERS_5);</div><div class='add'>+	reg_state-&gt;vblank_parameters_6 = REG_READ(VBLANK_PARAMETERS_6);</div><div class='add'>+	reg_state-&gt;vmid_settings_0 = REG_READ(VMID_SETTINGS_0);</div><div class='add'>+	reg_state-&gt;hubpret_control = REG_READ(HUBPRET_CONTROL);</div><div class='add'>+	reg_state-&gt;hubpret_interrupt = REG_READ(HUBPRET_INTERRUPT);</div><div class='add'>+	reg_state-&gt;hubpret_mem_pwr_ctrl = REG_READ(HUBPRET_MEM_PWR_CTRL);</div><div class='add'>+	reg_state-&gt;hubpret_mem_pwr_status = REG_READ(HUBPRET_MEM_PWR_STATUS);</div><div class='add'>+	reg_state-&gt;hubpret_read_line_ctrl0 = REG_READ(HUBPRET_READ_LINE_CTRL0);</div><div class='add'>+	reg_state-&gt;hubpret_read_line_ctrl1 = REG_READ(HUBPRET_READ_LINE_CTRL1);</div><div class='add'>+	reg_state-&gt;hubpret_read_line_status = REG_READ(HUBPRET_READ_LINE_STATUS);</div><div class='add'>+	reg_state-&gt;hubpret_read_line_value = REG_READ(HUBPRET_READ_LINE_VALUE);</div><div class='add'>+	reg_state-&gt;hubpret_read_line0 = REG_READ(HUBPRET_READ_LINE0);</div><div class='add'>+	reg_state-&gt;hubpret_read_line1 = REG_READ(HUBPRET_READ_LINE1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hubp3_setup(</div><div class='hunk'>@@ -480,6 +619,10 @@ void hubp3_init(struct hubp *hubp)</div><div class='ctx'> 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='ctx'> 	//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;</div><div class='ctx'> 	REG_WRITE(HUBPREQ_DEBUG, 1 &lt;&lt; 26);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);</div><div class='add'>+</div><div class='add'>+	hubp_reset(hubp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct hubp_funcs dcn30_hubp_funcs = {</div><div class='hunk'>@@ -494,6 +637,7 @@ static struct hubp_funcs dcn30_hubp_funcs = {</div><div class='ctx'> 	.set_blank = hubp2_set_blank,</div><div class='ctx'> 	.set_blank_regs = hubp2_set_blank_regs,</div><div class='ctx'> 	.dcc_control = hubp3_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.set_cursor_attributes	= hubp2_cursor_set_attributes,</div><div class='ctx'> 	.set_cursor_position	= hubp2_cursor_set_position,</div><div class='hunk'>@@ -509,6 +653,8 @@ static struct hubp_funcs dcn30_hubp_funcs = {</div><div class='ctx'> 	.hubp_in_blank = hubp1_in_blank,</div><div class='ctx'> 	.hubp_soft_reset = hubp1_soft_reset,</div><div class='ctx'> 	.hubp_set_flip_int = hubp1_set_flip_int,</div><div class='add'>+	.hubp_clear_tiling = hubp3_clear_tiling,</div><div class='add'>+	.hubp_read_reg_state = hubp3_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool hubp3_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h<br/>index b010531a7fe8..c767e9f4f9b3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h</a></div><div class='hunk'>@@ -243,7 +243,8 @@</div><div class='ctx'> 	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\</div><div class='ctx'> 	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\</div><div class='ctx'> 	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\</div><div class='del'>-	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh)</div><div class='ctx'> </div><div class='ctx'> bool hubp3_construct(</div><div class='ctx'> 		struct dcn20_hubp *hubp2,</div><div class='hunk'>@@ -264,7 +265,7 @@ bool hubp3_program_surface_flip_and_addr(</div><div class='ctx'> void hubp3_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -280,7 +281,7 @@ void hubp3_setup(</div><div class='ctx'> </div><div class='ctx'> void hubp3_program_tiling(</div><div class='ctx'> 		struct dcn20_hubp *hubp2,</div><div class='del'>-		const union dc_tiling_info *info,</div><div class='add'>+		const struct dc_tiling_info *info,</div><div class='ctx'> 		const enum surface_pixel_format pixel_format);</div><div class='ctx'> </div><div class='ctx'> void hubp3_dcc_control(struct hubp *hubp, bool enable,</div><div class='hunk'>@@ -295,8 +296,17 @@ void hubp3_dmdata_set_attributes(</div><div class='ctx'> </div><div class='ctx'> void hubp3_read_state(struct hubp *hubp);</div><div class='ctx'> </div><div class='add'>+void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);</div><div class='add'>+</div><div class='ctx'> void hubp3_init(struct hubp *hubp);</div><div class='ctx'> </div><div class='add'>+void hubp3_clear_tiling(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+uint32_t hubp3_get_current_read_line(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+uint32_t hubp3_get_underflow_status(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HUBP_DCN30_H__ */</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c<br/>index 8394e8c06919..189045f85039 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c</a></div><div class='hunk'>@@ -44,7 +44,7 @@ void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)</div><div class='ctx'> 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);</div><div class='del'>-	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);</div><div class='add'>+	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hubp31_soft_reset(struct hubp *hubp, bool reset)</div><div class='hunk'>@@ -68,6 +68,18 @@ void hubp31_program_extended_blank_value(</div><div class='ctx'> 	hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+uint32_t hubp31_get_det_config_error(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	uint32_t config_error = 0;</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBP_CNTL,</div><div class='add'>+		HUBP_SEG_ALLOC_ERR_STATUS,</div><div class='add'>+		&amp;config_error);</div><div class='add'>+</div><div class='add'>+	return config_error;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct hubp_funcs dcn31_hubp_funcs = {</div><div class='ctx'> 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,</div><div class='ctx'> 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,</div><div class='hunk'>@@ -79,6 +91,7 @@ static struct hubp_funcs dcn31_hubp_funcs = {</div><div class='ctx'> 	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,</div><div class='ctx'> 	.set_blank = hubp2_set_blank,</div><div class='ctx'> 	.dcc_control = hubp3_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.set_cursor_attributes	= hubp2_cursor_set_attributes,</div><div class='ctx'> 	.set_cursor_position	= hubp2_cursor_set_position,</div><div class='hunk'>@@ -96,6 +109,8 @@ static struct hubp_funcs dcn31_hubp_funcs = {</div><div class='ctx'> 	.hubp_set_flip_int = hubp1_set_flip_int,</div><div class='ctx'> 	.hubp_in_blank = hubp1_in_blank,</div><div class='ctx'> 	.program_extended_blank = hubp31_program_extended_blank,</div><div class='add'>+	.hubp_clear_tiling = hubp3_clear_tiling,</div><div class='add'>+	.hubp_read_reg_state = hubp3_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool hubp31_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h<br/>index d688db79b750..5952c4671507 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h</a></div><div class='hunk'>@@ -228,7 +228,9 @@</div><div class='ctx'> 	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\</div><div class='ctx'> 	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\</div><div class='ctx'> 	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\</div><div class='del'>-	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> bool hubp31_construct(</div><div class='hunk'>@@ -246,4 +248,6 @@ void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);</div><div class='ctx'> void hubp31_program_extended_blank_value(</div><div class='ctx'> 	struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);</div><div class='ctx'> </div><div class='add'>+uint32_t hubp31_get_det_config_error(struct hubp *hubp);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HUBP_DCN31_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c<br/>index ca5b4b28a664..a781085b046b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c</a></div><div class='hunk'>@@ -118,29 +118,7 @@ void hubp32_cursor_set_attributes(</div><div class='ctx'> 	uint32_t cursor_width = ((attr-&gt;width + 63) / 64) * 64;</div><div class='ctx'> 	uint32_t cursor_height = attr-&gt;height;</div><div class='ctx'> 	uint32_t cursor_size = cursor_width * cursor_height;</div><div class='del'>-</div><div class='del'>-	hubp-&gt;curs_attr = *attr;</div><div class='del'>-</div><div class='del'>-	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,</div><div class='del'>-			CURSOR_SURFACE_ADDRESS_HIGH, attr-&gt;address.high_part);</div><div class='del'>-	REG_UPDATE(CURSOR_SURFACE_ADDRESS,</div><div class='del'>-			CURSOR_SURFACE_ADDRESS, attr-&gt;address.low_part);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE_2(CURSOR_SIZE,</div><div class='del'>-			CURSOR_WIDTH, attr-&gt;width,</div><div class='del'>-			CURSOR_HEIGHT, attr-&gt;height);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE_4(CURSOR_CONTROL,</div><div class='del'>-			CURSOR_MODE, attr-&gt;color_format,</div><div class='del'>-			CURSOR_2X_MAGNIFY, attr-&gt;attribute_flags.bits.ENABLE_MAGNIFICATION,</div><div class='del'>-			CURSOR_PITCH, hw_pitch,</div><div class='del'>-			CURSOR_LINES_PER_CHUNK, lpc);</div><div class='del'>-</div><div class='del'>-	REG_SET_2(CURSOR_SETTINGS, 0,</div><div class='del'>-			/* no shift of the cursor HDL schedule */</div><div class='del'>-			CURSOR0_DST_Y_OFFSET, 0,</div><div class='del'>-			 /* used to shift the cursor chunk request deadline */</div><div class='del'>-			CURSOR0_CHUNK_HDL_ADJUST, 3);</div><div class='add'>+	bool use_mall_for_cursor;</div><div class='ctx'> </div><div class='ctx'> 	switch (attr-&gt;color_format) {</div><div class='ctx'> 	case CURSOR_MODE_MONO:</div><div class='hunk'>@@ -158,16 +136,56 @@ void hubp32_cursor_set_attributes(</div><div class='ctx'> 		cursor_size *= 8;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+	use_mall_for_cursor = cursor_size &gt; 16384 ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	hubp-&gt;curs_attr = *attr;</div><div class='ctx'> </div><div class='del'>-	if (cursor_size &gt; 16384)</div><div class='del'>-		REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);</div><div class='del'>-	else</div><div class='del'>-		REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);</div><div class='add'>+	if (!hubp-&gt;cursor_offload) {</div><div class='add'>+		REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				CURSOR_SURFACE_ADDRESS_HIGH, attr-&gt;address.high_part);</div><div class='add'>+		REG_UPDATE(CURSOR_SURFACE_ADDRESS,</div><div class='add'>+				CURSOR_SURFACE_ADDRESS, attr-&gt;address.low_part);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(CURSOR_SIZE,</div><div class='add'>+				CURSOR_WIDTH, attr-&gt;width,</div><div class='add'>+				CURSOR_HEIGHT, attr-&gt;height);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_4(CURSOR_CONTROL,</div><div class='add'>+				CURSOR_MODE, attr-&gt;color_format,</div><div class='add'>+				CURSOR_2X_MAGNIFY, attr-&gt;attribute_flags.bits.ENABLE_MAGNIFICATION,</div><div class='add'>+				CURSOR_PITCH, hw_pitch,</div><div class='add'>+				CURSOR_LINES_PER_CHUNK, lpc);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(CURSOR_SETTINGS, 0,</div><div class='add'>+				/* no shift of the cursor HDL schedule */</div><div class='add'>+				CURSOR0_DST_Y_OFFSET, 0,</div><div class='add'>+				 /* used to shift the cursor chunk request deadline */</div><div class='add'>+				CURSOR0_CHUNK_HDL_ADJUST, 3);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, use_mall_for_cursor);</div><div class='add'>+	}</div><div class='add'>+	hubp-&gt;att.SURFACE_ADDR_HIGH  = attr-&gt;address.high_part;</div><div class='add'>+	hubp-&gt;att.SURFACE_ADDR       = attr-&gt;address.low_part;</div><div class='add'>+	hubp-&gt;att.size.bits.width    = attr-&gt;width;</div><div class='add'>+	hubp-&gt;att.size.bits.height   = attr-&gt;height;</div><div class='add'>+	hubp-&gt;att.cur_ctl.bits.mode  = attr-&gt;color_format;</div><div class='add'>+</div><div class='add'>+	hubp-&gt;cur_rect.w = attr-&gt;width;</div><div class='add'>+	hubp-&gt;cur_rect.h = attr-&gt;height;</div><div class='add'>+</div><div class='add'>+	hubp-&gt;att.cur_ctl.bits.pitch = hw_pitch;</div><div class='add'>+	hubp-&gt;att.cur_ctl.bits.line_per_chunk = lpc;</div><div class='add'>+	hubp-&gt;att.cur_ctl.bits.cur_2x_magnify = attr-&gt;attribute_flags.bits.ENABLE_MAGNIFICATION;</div><div class='add'>+	hubp-&gt;att.settings.bits.dst_y_offset  = 0;</div><div class='add'>+	hubp-&gt;att.settings.bits.chunk_hdl_adjust = 3;</div><div class='add'>+	hubp-&gt;use_mall_for_cursor = use_mall_for_cursor;</div><div class='ctx'> }</div><div class='ctx'> void hubp32_init(struct hubp *hubp)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='ctx'> 	REG_WRITE(HUBPREQ_DEBUG_DB, 1 &lt;&lt; 8);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);</div><div class='ctx'> }</div><div class='ctx'> static struct hubp_funcs dcn32_hubp_funcs = {</div><div class='ctx'> 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,</div><div class='hunk'>@@ -181,6 +199,7 @@ static struct hubp_funcs dcn32_hubp_funcs = {</div><div class='ctx'> 	.set_blank = hubp2_set_blank,</div><div class='ctx'> 	.set_blank_regs = hubp2_set_blank_regs,</div><div class='ctx'> 	.dcc_control = hubp3_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.set_cursor_attributes	= hubp32_cursor_set_attributes,</div><div class='ctx'> 	.set_cursor_position	= hubp2_cursor_set_position,</div><div class='hunk'>@@ -201,7 +220,9 @@ static struct hubp_funcs dcn32_hubp_funcs = {</div><div class='ctx'> 	.hubp_update_force_cursor_pstate_disallow = hubp32_update_force_cursor_pstate_disallow,</div><div class='ctx'> 	.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,</div><div class='ctx'> 	.hubp_update_mall_sel = hubp32_update_mall_sel,</div><div class='del'>-	.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering</div><div class='add'>+	.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,</div><div class='add'>+	.hubp_clear_tiling = hubp3_clear_tiling,</div><div class='add'>+	.hubp_read_reg_state = hubp3_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool hubp32_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h<br/>index d2acbc129609..d2acbc129609 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c<br/>index 771fcd0d3b99..79c583e258c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c</a></div><div class='hunk'>@@ -45,7 +45,7 @@ void hubp35_set_fgcg(struct hubp *hubp, bool enable)</div><div class='ctx'> 	REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void hubp35_init(struct hubp *hubp)</div><div class='add'>+void hubp35_init(struct hubp *hubp)</div><div class='ctx'> {</div><div class='ctx'> 	hubp3_init(hubp);</div><div class='ctx'> </div><div class='hunk'>@@ -172,7 +172,7 @@ void hubp35_program_pixel_format(</div><div class='ctx'> void hubp35_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -188,7 +188,7 @@ void hubp35_program_surface_config(</div><div class='ctx'> 	hubp35_program_pixel_format(hubp, format);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct hubp_funcs dcn35_hubp_funcs = {</div><div class='add'>+static struct hubp_funcs dcn35_hubp_funcs = {</div><div class='ctx'> 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,</div><div class='ctx'> 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,</div><div class='ctx'> 	.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,</div><div class='hunk'>@@ -199,6 +199,7 @@ struct hubp_funcs dcn35_hubp_funcs = {</div><div class='ctx'> 	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,</div><div class='ctx'> 	.set_blank = hubp2_set_blank,</div><div class='ctx'> 	.dcc_control = hubp3_dcc_control,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='ctx'> 	.mem_program_viewport = min_set_viewport,</div><div class='ctx'> 	.set_cursor_attributes	= hubp2_cursor_set_attributes,</div><div class='ctx'> 	.set_cursor_position	= hubp2_cursor_set_position,</div><div class='hunk'>@@ -208,6 +209,7 @@ struct hubp_funcs dcn35_hubp_funcs = {</div><div class='ctx'> 	.dmdata_load = hubp2_dmdata_load,</div><div class='ctx'> 	.dmdata_status_done = hubp2_dmdata_status_done,</div><div class='ctx'> 	.hubp_read_state = hubp3_read_state,</div><div class='add'>+	.hubp_read_reg_state = hubp3_read_reg_state,</div><div class='ctx'> 	.hubp_clear_underflow = hubp2_clear_underflow,</div><div class='ctx'> 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,</div><div class='ctx'> 	.hubp_init = hubp35_init,</div><div class='hunk'>@@ -216,6 +218,7 @@ struct hubp_funcs dcn35_hubp_funcs = {</div><div class='ctx'> 	.hubp_set_flip_int = hubp1_set_flip_int,</div><div class='ctx'> 	.hubp_in_blank = hubp1_in_blank,</div><div class='ctx'> 	.program_extended_blank = hubp31_program_extended_blank_value,</div><div class='add'>+	.hubp_clear_tiling = hubp3_clear_tiling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool hubp35_construct(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h<br/>index 586b43aa5834..934836717f32 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h</a></div><div class='hunk'>@@ -65,11 +65,12 @@ void hubp35_program_pixel_format(</div><div class='ctx'> void hubp35_program_surface_config(</div><div class='ctx'> 	struct hubp *hubp,</div><div class='ctx'> 	enum surface_pixel_format format,</div><div class='del'>-	union dc_tiling_info *tiling_info,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='ctx'> 	struct plane_size *plane_size,</div><div class='ctx'> 	enum dc_rotation_angle rotation,</div><div class='ctx'> 	struct dc_plane_dcc_param *dcc,</div><div class='ctx'> 	bool horizontal_mirror,</div><div class='ctx'> 	unsigned int compat_level);</div><div class='ctx'> </div><div class='add'>+void hubp35_init(struct hubp *hubp);</div><div class='ctx'> #endif /* __DC_HUBP_DCN35_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c<br/>new file mode 100644<br/>index 000000000000..f01eae50d02f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c</a></div><div class='hunk'>@@ -0,0 +1,1097 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "dce_calcs.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "basics/conversion.h"</div><div class='add'>+#include "dcn401_hubp.h"</div><div class='add'>+#include "dal_asic_id.h"</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	hubp2-&gt;hubp_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	hubp2-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	hubp2-&gt;hubp_shift-&gt;field_name, hubp2-&gt;hubp_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_addr(struct hubp *hubp,</div><div class='add'>+	const struct dc_plane_address address)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part);</div><div class='add'>+	REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, refcyc_per_3dlut_group);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int hubp401_get_3dlut_fl_done(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &amp;ret);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,</div><div class='add'>+			enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,</div><div class='add'>+			enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,</div><div class='add'>+			enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_3(HUBP_3DLUT_CONTROL,</div><div class='add'>+			HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g,</div><div class='add'>+			HUBP_3DLUT_CROSSBAR_SELECT_CB_B, bit_slice_cb_b,</div><div class='add'>+			HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_config(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	struct hubp_fl_3dlut_config *cfg)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	uint32_t mpc_width = {(cfg-&gt;width == 17) ? 0 : 1};</div><div class='add'>+	uint32_t width = {cfg-&gt;width};</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR)</div><div class='add'>+		width = (cfg-&gt;width == 17) ? 4916 : 35940;</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(_3DLUT_FL_CONFIG,</div><div class='add'>+		HUBP0_3DLUT_FL_MODE, cfg-&gt;mode,</div><div class='add'>+		HUBP0_3DLUT_FL_FORMAT, cfg-&gt;format);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE,</div><div class='add'>+		HUBP0_3DLUT_FL_BIAS, cfg-&gt;bias,</div><div class='add'>+		HUBP0_3DLUT_FL_SCALE, cfg-&gt;scale);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH,</div><div class='add'>+		HUBP_3DLUT_ADDRESS_HIGH, cfg-&gt;address.lut3d.addr.high_part);</div><div class='add'>+	REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW,</div><div class='add'>+		HUBP_3DLUT_ADDRESS_LOW, cfg-&gt;address.lut3d.addr.low_part);</div><div class='add'>+</div><div class='add'>+	//cross bar</div><div class='add'>+	REG_UPDATE_8(HUBP_3DLUT_CONTROL,</div><div class='add'>+		HUBP_3DLUT_MPC_WIDTH, mpc_width,</div><div class='add'>+		HUBP_3DLUT_WIDTH, width,</div><div class='add'>+		HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg-&gt;crossbar_bit_slice_cr_r,</div><div class='add'>+		HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg-&gt;crossbar_bit_slice_y_g,</div><div class='add'>+		HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg-&gt;crossbar_bit_slice_cb_b,</div><div class='add'>+		HUBP_3DLUT_ADDRESSING_MODE, cfg-&gt;addr_mode,</div><div class='add'>+		HUBP_3DLUT_TMZ, cfg-&gt;protection_bits,</div><div class='add'>+		HUBP_3DLUT_ENABLE, cfg-&gt;enabled ? 1 : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	// Also cache cursor in MALL if using MALL for SS</div><div class='add'>+	REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel,</div><div class='add'>+			USE_MALL_FOR_CURSOR, c_cursor);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, 1, MALL_PREF_MODE, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void hubp401_init(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	hubp_reset(hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_vready_at_or_After_vsync(struct hubp *hubp,</div><div class='add'>+	union dml2_global_sync_programming *pipe_global_sync,</div><div class='add'>+	struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	unsigned int vstartup_lines = pipe_global_sync-&gt;dcn4x.vstartup_lines;</div><div class='add'>+	unsigned int vupdate_offset_pixels = pipe_global_sync-&gt;dcn4x.vupdate_offset_pixels;</div><div class='add'>+	unsigned int vupdate_width_pixels = pipe_global_sync-&gt;dcn4x.vupdate_vupdate_width_pixels;</div><div class='add'>+	unsigned int vready_offset_pixels = pipe_global_sync-&gt;dcn4x.vready_offset_pixels;</div><div class='add'>+	unsigned int htotal = timing-&gt;h_total;</div><div class='add'>+	unsigned int vblank_start = 0;</div><div class='add'>+	unsigned int vblank_end = 0;</div><div class='add'>+	unsigned int pixel_width = 0;</div><div class='add'>+	uint32_t reg_value = 0;</div><div class='add'>+	bool is_vready_at_or_after_vsync = false;</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) &lt;= OTG_V_BLANK_END</div><div class='add'>+	 *	Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1</div><div class='add'>+	 * else</div><div class='add'>+	 *	Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0</div><div class='add'>+	 */</div><div class='add'>+	if (htotal != 0) {</div><div class='add'>+		vblank_start = timing-&gt;v_total - timing-&gt;v_front_porch;</div><div class='add'>+		vblank_end = vblank_start - timing-&gt;v_addressable - timing-&gt;v_border_top - timing-&gt;v_border_bottom;</div><div class='add'>+		pixel_width = vready_offset_pixels + vupdate_width_pixels + vupdate_offset_pixels;</div><div class='add'>+</div><div class='add'>+		is_vready_at_or_after_vsync = (vstartup_lines - pixel_width / htotal) &lt;= vblank_end;</div><div class='add'>+</div><div class='add'>+		if (is_vready_at_or_after_vsync)</div><div class='add'>+			reg_value = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, reg_value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_requestor(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_display_rq_regs *rq_regs)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(HUBPRET_CONTROL,</div><div class='add'>+			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs-&gt;plane1_base_address);</div><div class='add'>+	REG_SET_4(DCN_EXPANSION_MODE, 0,</div><div class='add'>+			DRQ_EXPANSION_MODE, rq_regs-&gt;drq_expansion_mode,</div><div class='add'>+			PRQ_EXPANSION_MODE, rq_regs-&gt;prq_expansion_mode,</div><div class='add'>+			MRQ_EXPANSION_MODE, rq_regs-&gt;mrq_expansion_mode,</div><div class='add'>+			CRQ_EXPANSION_MODE, rq_regs-&gt;crq_expansion_mode);</div><div class='add'>+	REG_SET_6(DCHUBP_REQ_SIZE_CONFIG, 0,</div><div class='add'>+		CHUNK_SIZE, rq_regs-&gt;rq_regs_l.chunk_size,</div><div class='add'>+		MIN_CHUNK_SIZE, rq_regs-&gt;rq_regs_l.min_chunk_size,</div><div class='add'>+		DPTE_GROUP_SIZE, rq_regs-&gt;rq_regs_l.dpte_group_size,</div><div class='add'>+		VM_GROUP_SIZE, rq_regs-&gt;rq_regs_l.mpte_group_size,</div><div class='add'>+		SWATH_HEIGHT, rq_regs-&gt;rq_regs_l.swath_height,</div><div class='add'>+		PTE_ROW_HEIGHT_LINEAR, rq_regs-&gt;rq_regs_l.pte_row_height_linear);</div><div class='add'>+	REG_SET_5(DCHUBP_REQ_SIZE_CONFIG_C, 0,</div><div class='add'>+		CHUNK_SIZE_C, rq_regs-&gt;rq_regs_c.chunk_size,</div><div class='add'>+		MIN_CHUNK_SIZE_C, rq_regs-&gt;rq_regs_c.min_chunk_size,</div><div class='add'>+		DPTE_GROUP_SIZE_C, rq_regs-&gt;rq_regs_c.dpte_group_size,</div><div class='add'>+		SWATH_HEIGHT_C, rq_regs-&gt;rq_regs_c.swath_height,</div><div class='add'>+		PTE_ROW_HEIGHT_LINEAR_C, rq_regs-&gt;rq_regs_c.pte_row_height_linear);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_deadline(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_display_dlg_regs *dlg_attr,</div><div class='add'>+		struct dml2_display_ttu_regs *ttu_attr)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	/* put DLG in mission mode */</div><div class='add'>+	REG_WRITE(HUBPREQ_DEBUG_DB, 1 &lt;&lt; 8);</div><div class='add'>+</div><div class='add'>+	/* DLG - Per hubp */</div><div class='add'>+	REG_SET_2(BLANK_OFFSET_0, 0,</div><div class='add'>+		REFCYC_H_BLANK_END, dlg_attr-&gt;refcyc_h_blank_end,</div><div class='add'>+		DLG_V_BLANK_END, dlg_attr-&gt;dlg_vblank_end);</div><div class='add'>+</div><div class='add'>+	REG_SET(BLANK_OFFSET_1, 0,</div><div class='add'>+		MIN_DST_Y_NEXT_START, dlg_attr-&gt;min_dst_y_next_start);</div><div class='add'>+</div><div class='add'>+	REG_SET(DST_DIMENSIONS, 0,</div><div class='add'>+		REFCYC_PER_HTOTAL, dlg_attr-&gt;refcyc_per_htotal);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DST_AFTER_SCALER, 0,</div><div class='add'>+		REFCYC_X_AFTER_SCALER, dlg_attr-&gt;refcyc_x_after_scaler,</div><div class='add'>+		DST_Y_AFTER_SCALER, dlg_attr-&gt;dst_y_after_scaler);</div><div class='add'>+</div><div class='add'>+	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,</div><div class='add'>+		REF_FREQ_TO_PIX_FREQ, dlg_attr-&gt;ref_freq_to_pix_freq);</div><div class='add'>+</div><div class='add'>+	/* DLG - Per luma/chroma */</div><div class='add'>+	REG_SET(VBLANK_PARAMETERS_1, 0,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr-&gt;refcyc_per_pte_group_vblank_l);</div><div class='add'>+</div><div class='add'>+	if (REG(NOM_PARAMETERS_0))</div><div class='add'>+		REG_SET(NOM_PARAMETERS_0, 0,</div><div class='add'>+			DST_Y_PER_PTE_ROW_NOM_L, dlg_attr-&gt;dst_y_per_pte_row_nom_l);</div><div class='add'>+</div><div class='add'>+	if (REG(NOM_PARAMETERS_1))</div><div class='add'>+		REG_SET(NOM_PARAMETERS_1, 0,</div><div class='add'>+			REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr-&gt;refcyc_per_pte_group_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_SET(NOM_PARAMETERS_4, 0,</div><div class='add'>+		DST_Y_PER_META_ROW_NOM_L, dlg_attr-&gt;dst_y_per_meta_row_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_SET(NOM_PARAMETERS_5, 0,</div><div class='add'>+		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr-&gt;refcyc_per_meta_chunk_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(PER_LINE_DELIVERY, 0,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_L, dlg_attr-&gt;refcyc_per_line_delivery_l,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_C, dlg_attr-&gt;refcyc_per_line_delivery_c);</div><div class='add'>+</div><div class='add'>+	REG_SET(VBLANK_PARAMETERS_2, 0,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr-&gt;refcyc_per_pte_group_vblank_c);</div><div class='add'>+</div><div class='add'>+	if (REG(NOM_PARAMETERS_2))</div><div class='add'>+		REG_SET(NOM_PARAMETERS_2, 0,</div><div class='add'>+			DST_Y_PER_PTE_ROW_NOM_C, dlg_attr-&gt;dst_y_per_pte_row_nom_c);</div><div class='add'>+</div><div class='add'>+	if (REG(NOM_PARAMETERS_3))</div><div class='add'>+		REG_SET(NOM_PARAMETERS_3, 0,</div><div class='add'>+			REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr-&gt;refcyc_per_pte_group_nom_c);</div><div class='add'>+</div><div class='add'>+	REG_SET(NOM_PARAMETERS_6, 0,</div><div class='add'>+		DST_Y_PER_META_ROW_NOM_C, dlg_attr-&gt;dst_y_per_meta_row_nom_c);</div><div class='add'>+</div><div class='add'>+	REG_SET(NOM_PARAMETERS_7, 0,</div><div class='add'>+		REFCYC_PER_META_CHUNK_NOM_C, dlg_attr-&gt;refcyc_per_meta_chunk_nom_c);</div><div class='add'>+</div><div class='add'>+	/* TTU - per hubp */</div><div class='add'>+	REG_SET_2(DCN_TTU_QOS_WM, 0,</div><div class='add'>+		QoS_LEVEL_LOW_WM, ttu_attr-&gt;qos_level_low_wm,</div><div class='add'>+		QoS_LEVEL_HIGH_WM, ttu_attr-&gt;qos_level_high_wm);</div><div class='add'>+</div><div class='add'>+	/* TTU - per luma/chroma */</div><div class='add'>+	/* Assumed surf0 is luma and 1 is chroma */</div><div class='add'>+</div><div class='add'>+	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY, ttu_attr-&gt;refcyc_per_req_delivery_l,</div><div class='add'>+		QoS_LEVEL_FIXED, ttu_attr-&gt;qos_level_fixed_l,</div><div class='add'>+		QoS_RAMP_DISABLE, ttu_attr-&gt;qos_ramp_disable_l);</div><div class='add'>+</div><div class='add'>+	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY, ttu_attr-&gt;refcyc_per_req_delivery_c,</div><div class='add'>+		QoS_LEVEL_FIXED, ttu_attr-&gt;qos_level_fixed_c,</div><div class='add'>+		QoS_RAMP_DISABLE, ttu_attr-&gt;qos_ramp_disable_c);</div><div class='add'>+</div><div class='add'>+	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY, ttu_attr-&gt;refcyc_per_req_delivery_cur0,</div><div class='add'>+		QoS_LEVEL_FIXED, ttu_attr-&gt;qos_level_fixed_cur0,</div><div class='add'>+		QoS_RAMP_DISABLE, ttu_attr-&gt;qos_ramp_disable_cur0);</div><div class='add'>+</div><div class='add'>+	REG_SET(FLIP_PARAMETERS_1, 0,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr-&gt;refcyc_per_pte_group_flip_l);</div><div class='add'>+	REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr-&gt;refcyc_per_tdlut_group);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCN_DMDATA_VM_CNTL,</div><div class='add'>+			REFCYC_PER_VM_DMDATA, dlg_attr-&gt;refcyc_per_vm_dmdata);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_setup(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+	    struct dml2_dchub_per_pipe_register_set *pipe_regs,</div><div class='add'>+		union dml2_global_sync_programming *pipe_global_sync,</div><div class='add'>+		struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	/* otg is locked when this func is called. Register are double buffered.</div><div class='add'>+	 * disable the requestors is not needed</div><div class='add'>+	 */</div><div class='add'>+	hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);</div><div class='add'>+	hubp401_program_requestor(hubp, &amp;pipe_regs-&gt;rq_regs);</div><div class='add'>+	hubp401_program_deadline(hubp, &amp;pipe_regs-&gt;dlg_regs, &amp;pipe_regs-&gt;ttu_regs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_setup_interdependent(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *pipe_regs)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(PREFETCH_SETTINGS, 0,</div><div class='add'>+			DST_Y_PREFETCH, pipe_regs-&gt;dlg_regs.dst_y_prefetch,</div><div class='add'>+			VRATIO_PREFETCH, pipe_regs-&gt;dlg_regs.vratio_prefetch);</div><div class='add'>+</div><div class='add'>+	REG_SET(PREFETCH_SETTINGS_C, 0,</div><div class='add'>+			VRATIO_PREFETCH_C, pipe_regs-&gt;dlg_regs.vratio_prefetch_c);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(VBLANK_PARAMETERS_0, 0,</div><div class='add'>+		DST_Y_PER_VM_VBLANK, pipe_regs-&gt;dlg_regs.dst_y_per_vm_vblank,</div><div class='add'>+		DST_Y_PER_ROW_VBLANK, pipe_regs-&gt;dlg_regs.dst_y_per_row_vblank);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(FLIP_PARAMETERS_0, 0,</div><div class='add'>+		DST_Y_PER_VM_FLIP, pipe_regs-&gt;dlg_regs.dst_y_per_vm_flip,</div><div class='add'>+		DST_Y_PER_ROW_FLIP, pipe_regs-&gt;dlg_regs.dst_y_per_row_flip);</div><div class='add'>+</div><div class='add'>+	REG_SET(VBLANK_PARAMETERS_3, 0,</div><div class='add'>+		REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs-&gt;dlg_regs.refcyc_per_meta_chunk_vblank_l);</div><div class='add'>+</div><div class='add'>+	REG_SET(VBLANK_PARAMETERS_4, 0,</div><div class='add'>+		REFCYC_PER_META_CHUNK_VBLANK_C, pipe_regs-&gt;dlg_regs.refcyc_per_meta_chunk_vblank_c);</div><div class='add'>+</div><div class='add'>+	REG_SET(FLIP_PARAMETERS_2, 0,</div><div class='add'>+		REFCYC_PER_META_CHUNK_FLIP_L, pipe_regs-&gt;dlg_regs.refcyc_per_meta_chunk_flip_l);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(PER_LINE_DELIVERY_PRE, 0,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_PRE_L, pipe_regs-&gt;dlg_regs.refcyc_per_line_delivery_pre_l,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_PRE_C, pipe_regs-&gt;dlg_regs.refcyc_per_line_delivery_pre_c);</div><div class='add'>+</div><div class='add'>+	REG_SET(DCN_SURF0_TTU_CNTL1, 0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY_PRE,</div><div class='add'>+		pipe_regs-&gt;ttu_regs.refcyc_per_req_delivery_pre_l);</div><div class='add'>+	REG_SET(DCN_SURF1_TTU_CNTL1, 0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY_PRE,</div><div class='add'>+		pipe_regs-&gt;ttu_regs.refcyc_per_req_delivery_pre_c);</div><div class='add'>+	REG_SET(DCN_CUR0_TTU_CNTL1, 0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY_PRE, pipe_regs-&gt;ttu_regs.refcyc_per_req_delivery_pre_cur0);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,</div><div class='add'>+		MIN_TTU_VBLANK, pipe_regs-&gt;ttu_regs.min_ttu_vblank,</div><div class='add'>+		QoS_LEVEL_FLIP, pipe_regs-&gt;ttu_regs.qos_level_flip);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+bool hubp401_program_surface_flip_and_addr(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	const struct dc_plane_address *address,</div><div class='add'>+	bool flip_immediate)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	//program flip type</div><div class='add'>+	REG_UPDATE(DCSURF_FLIP_CONTROL,</div><div class='add'>+			SURFACE_FLIP_TYPE, flip_immediate);</div><div class='add'>+</div><div class='add'>+	// Program VMID reg</div><div class='add'>+	if (flip_immediate == 0)</div><div class='add'>+		REG_UPDATE(VMID_SETTINGS_0,</div><div class='add'>+			VMID, address-&gt;vmid);</div><div class='add'>+</div><div class='add'>+	if (address-&gt;type == PLN_ADDR_TYPE_GRPH_STEREO) {</div><div class='add'>+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);</div><div class='add'>+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		// turn off stereo if not in stereo</div><div class='add'>+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);</div><div class='add'>+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* HW automatically latch rest of address register on write to</div><div class='add'>+	 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used</div><div class='add'>+	 *</div><div class='add'>+	 * program high first and then the low addr, order matters!</div><div class='add'>+	 */</div><div class='add'>+	switch (address-&gt;type) {</div><div class='add'>+	case PLN_ADDR_TYPE_GRAPHICS:</div><div class='add'>+		if (address-&gt;grph.addr.quad_part == 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DCSURF_SURFACE_CONTROL,</div><div class='add'>+				PRIMARY_SURFACE_TMZ, address-&gt;tmz_surface);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				address-&gt;grph.addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS,</div><div class='add'>+				address-&gt;grph.addr.low_part);</div><div class='add'>+		break;</div><div class='add'>+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:</div><div class='add'>+		if (address-&gt;video_progressive.luma_addr.quad_part == 0</div><div class='add'>+				|| address-&gt;video_progressive.chroma_addr.quad_part == 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(DCSURF_SURFACE_CONTROL,</div><div class='add'>+				PRIMARY_SURFACE_TMZ, address-&gt;tmz_surface,</div><div class='add'>+				PRIMARY_SURFACE_TMZ_C, address-&gt;tmz_surface);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH_C,</div><div class='add'>+				address-&gt;video_progressive.chroma_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_C,</div><div class='add'>+				address-&gt;video_progressive.chroma_addr.low_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				address-&gt;video_progressive.luma_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS,</div><div class='add'>+				address-&gt;video_progressive.luma_addr.low_part);</div><div class='add'>+		break;</div><div class='add'>+	case PLN_ADDR_TYPE_GRPH_STEREO:</div><div class='add'>+		if (address-&gt;grph_stereo.left_addr.quad_part == 0)</div><div class='add'>+			break;</div><div class='add'>+		if (address-&gt;grph_stereo.right_addr.quad_part == 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_4(DCSURF_SURFACE_CONTROL,</div><div class='add'>+				PRIMARY_SURFACE_TMZ, address-&gt;tmz_surface,</div><div class='add'>+				PRIMARY_SURFACE_TMZ_C, address-&gt;tmz_surface,</div><div class='add'>+				SECONDARY_SURFACE_TMZ, address-&gt;tmz_surface,</div><div class='add'>+				SECONDARY_SURFACE_TMZ_C, address-&gt;tmz_surface);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,</div><div class='add'>+				SECONDARY_SURFACE_ADDRESS_HIGH_C,</div><div class='add'>+				address-&gt;grph_stereo.right_alpha_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,</div><div class='add'>+				SECONDARY_SURFACE_ADDRESS_C,</div><div class='add'>+				address-&gt;grph_stereo.right_alpha_addr.low_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,</div><div class='add'>+				SECONDARY_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				address-&gt;grph_stereo.right_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,</div><div class='add'>+				SECONDARY_SURFACE_ADDRESS,</div><div class='add'>+				address-&gt;grph_stereo.right_addr.low_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH_C,</div><div class='add'>+				address-&gt;grph_stereo.left_alpha_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_C,</div><div class='add'>+				address-&gt;grph_stereo.left_alpha_addr.low_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				address-&gt;grph_stereo.left_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS,</div><div class='add'>+				address-&gt;grph_stereo.left_addr.low_part);</div><div class='add'>+		break;</div><div class='add'>+	case PLN_ADDR_TYPE_RGBEA:</div><div class='add'>+		if (address-&gt;rgbea.addr.quad_part == 0</div><div class='add'>+				|| address-&gt;rgbea.alpha_addr.quad_part == 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_2(DCSURF_SURFACE_CONTROL,</div><div class='add'>+				PRIMARY_SURFACE_TMZ, address-&gt;tmz_surface,</div><div class='add'>+				PRIMARY_SURFACE_TMZ_C, address-&gt;tmz_surface);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH_C,</div><div class='add'>+				address-&gt;rgbea.alpha_addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_C,</div><div class='add'>+				address-&gt;rgbea.alpha_addr.low_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS_HIGH,</div><div class='add'>+				address-&gt;rgbea.addr.high_part);</div><div class='add'>+</div><div class='add'>+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,</div><div class='add'>+				PRIMARY_SURFACE_ADDRESS,</div><div class='add'>+				address-&gt;rgbea.addr.low_part);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hubp-&gt;request_address = *address;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_clear_tiling(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);</div><div class='add'>+	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(DCSURF_SURFACE_CONTROL,</div><div class='add'>+		     PRIMARY_SURFACE_DCC_EN, 0,</div><div class='add'>+		     SECONDARY_SURFACE_DCC_EN, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_dcc_control(struct hubp *hubp,</div><div class='add'>+		struct dc_plane_dcc_param *dcc)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_2(DCSURF_SURFACE_CONTROL,</div><div class='add'>+		PRIMARY_SURFACE_DCC_EN, dcc-&gt;enable,</div><div class='add'>+		SECONDARY_SURFACE_DCC_EN, dcc-&gt;enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_tiling(</div><div class='add'>+	struct dcn20_hubp *hubp2,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='add'>+	const enum surface_pixel_format pixel_format)</div><div class='add'>+{</div><div class='add'>+	/* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x</div><div class='add'>+	 * All 4 fields NUM_PIPES, PIPE_INTERLEAVE, MAX_COMPRESSED_FRAGS and NUM_PKRS are irrelevant.</div><div class='add'>+	 *</div><div class='add'>+	 * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default.</div><div class='add'>+	 */</div><div class='add'>+	 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info-&gt;gfx_addr3.swizzle);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_size(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	enum surface_pixel_format format,</div><div class='add'>+	const struct plane_size *plane_size,</div><div class='add'>+	struct dc_plane_dcc_param *dcc)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+	uint32_t pitch, pitch_c;</div><div class='add'>+	bool use_pitch_c = false;</div><div class='add'>+</div><div class='add'>+	/* Program data pitch (calculation from addrlib)</div><div class='add'>+	 * 444 or 420 luma</div><div class='add'>+	 */</div><div class='add'>+	use_pitch_c = format &gt;= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN</div><div class='add'>+		&amp;&amp; format &lt; SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;</div><div class='add'>+	use_pitch_c = use_pitch_c</div><div class='add'>+		|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);</div><div class='add'>+	if (use_pitch_c) {</div><div class='add'>+		ASSERT(plane_size-&gt;chroma_pitch != 0);</div><div class='add'>+		/* Chroma pitch zero can cause system hang! */</div><div class='add'>+</div><div class='add'>+		pitch = plane_size-&gt;surface_pitch - 1;</div><div class='add'>+		pitch_c = plane_size-&gt;chroma_pitch - 1;</div><div class='add'>+	} else {</div><div class='add'>+		pitch = plane_size-&gt;surface_pitch - 1;</div><div class='add'>+		pitch_c = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCSURF_SURFACE_PITCH, PITCH, pitch);</div><div class='add'>+</div><div class='add'>+	if (use_pitch_c)</div><div class='add'>+		REG_UPDATE(DCSURF_SURFACE_PITCH_C, PITCH_C, pitch_c);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_surface_config(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	enum surface_pixel_format format,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='add'>+	struct plane_size *plane_size,</div><div class='add'>+	enum dc_rotation_angle rotation,</div><div class='add'>+	struct dc_plane_dcc_param *dcc,</div><div class='add'>+	bool horizontal_mirror,</div><div class='add'>+	unsigned int compat_level)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	hubp401_dcc_control(hubp, dcc);</div><div class='add'>+	hubp401_program_tiling(hubp2, tiling_info, format);</div><div class='add'>+	hubp401_program_size(hubp, format, plane_size, dcc);</div><div class='add'>+	hubp2_program_rotation(hubp, rotation, horizontal_mirror);</div><div class='add'>+	hubp2_program_pixel_format(hubp, format);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_set_viewport(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	const struct rect *viewport,</div><div class='add'>+	const struct rect *viewport_c)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,</div><div class='add'>+		  PRI_VIEWPORT_WIDTH, viewport-&gt;width,</div><div class='add'>+		  PRI_VIEWPORT_HEIGHT, viewport-&gt;height);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,</div><div class='add'>+		  PRI_VIEWPORT_X_START, viewport-&gt;x,</div><div class='add'>+		  PRI_VIEWPORT_Y_START, viewport-&gt;y);</div><div class='add'>+</div><div class='add'>+	/*for stereo*/</div><div class='add'>+	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,</div><div class='add'>+		  SEC_VIEWPORT_WIDTH, viewport-&gt;width,</div><div class='add'>+		  SEC_VIEWPORT_HEIGHT, viewport-&gt;height);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,</div><div class='add'>+		  SEC_VIEWPORT_X_START, viewport-&gt;x,</div><div class='add'>+		  SEC_VIEWPORT_Y_START, viewport-&gt;y);</div><div class='add'>+</div><div class='add'>+	/* DC supports NV12 only at the moment */</div><div class='add'>+	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,</div><div class='add'>+		  PRI_VIEWPORT_WIDTH_C, viewport_c-&gt;width,</div><div class='add'>+		  PRI_VIEWPORT_HEIGHT_C, viewport_c-&gt;height);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,</div><div class='add'>+		  PRI_VIEWPORT_X_START_C, viewport_c-&gt;x,</div><div class='add'>+		  PRI_VIEWPORT_Y_START_C, viewport_c-&gt;y);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,</div><div class='add'>+		  SEC_VIEWPORT_WIDTH_C, viewport_c-&gt;width,</div><div class='add'>+		  SEC_VIEWPORT_HEIGHT_C, viewport_c-&gt;height);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,</div><div class='add'>+		  SEC_VIEWPORT_X_START_C, viewport_c-&gt;x,</div><div class='add'>+		  SEC_VIEWPORT_Y_START_C, viewport_c-&gt;y);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_program_mcache_id_and_split_coordinate(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs *mcache_regs)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_SET_8(DCHUBP_MCACHEID_CONFIG, 0,</div><div class='add'>+		MCACHEID_REG_READ_1H_P0, mcache_regs-&gt;main.p0.mcache_id_first,</div><div class='add'>+		MCACHEID_REG_READ_2H_P0, mcache_regs-&gt;main.p0.mcache_id_second,</div><div class='add'>+		MCACHEID_REG_READ_1H_P1, mcache_regs-&gt;main.p1.mcache_id_first,</div><div class='add'>+		MCACHEID_REG_READ_2H_P1, mcache_regs-&gt;main.p1.mcache_id_second,</div><div class='add'>+		MCACHEID_MALL_PREF_1H_P0, mcache_regs-&gt;mall.p0.mcache_id_first,</div><div class='add'>+		MCACHEID_MALL_PREF_2H_P0, mcache_regs-&gt;mall.p0.mcache_id_second,</div><div class='add'>+		MCACHEID_MALL_PREF_1H_P1, mcache_regs-&gt;mall.p1.mcache_id_first,</div><div class='add'>+		MCACHEID_MALL_PREF_2H_P1, mcache_regs-&gt;mall.p1.mcache_id_second);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, 0,</div><div class='add'>+		VIEWPORT_MCACHE_SPLIT_COORDINATE, mcache_regs-&gt;main.p0.split_location,</div><div class='add'>+		VIEWPORT_MCACHE_SPLIT_COORDINATE_C, mcache_regs-&gt;main.p1.split_location);</div><div class='add'>+}</div><div class='add'>+void hubp401_set_flip_int(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,</div><div class='add'>+		SURFACE_FLIP_INT_MASK, 1);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool hubp401_in_blank(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+	uint32_t in_blank;</div><div class='add'>+</div><div class='add'>+	REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &amp;in_blank);</div><div class='add'>+	return in_blank ? true : false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void hubp401_cursor_set_position(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	const struct dc_cursor_position *pos,</div><div class='add'>+	const struct dc_cursor_mi_param *param)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+	int x_pos = pos-&gt;x - param-&gt;recout.x;</div><div class='add'>+	int y_pos = pos-&gt;y - param-&gt;recout.y;</div><div class='add'>+	int rec_x_offset = x_pos - pos-&gt;x_hotspot;</div><div class='add'>+	int rec_y_offset = y_pos - pos-&gt;y_hotspot;</div><div class='add'>+	int dst_x_offset;</div><div class='add'>+	int x_pos_viewport = 0;</div><div class='add'>+	int x_hot_viewport = 0;</div><div class='add'>+	uint32_t cur_en = pos-&gt;enable ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	hubp-&gt;curs_pos = *pos;</div><div class='add'>+</div><div class='add'>+	/* Recout is zero for pipes if the entire dst_rect is contained</div><div class='add'>+	 * within preceeding ODM slices.</div><div class='add'>+	 */</div><div class='add'>+	if (param-&gt;recout.width) {</div><div class='add'>+		x_pos_viewport = x_pos * param-&gt;viewport.width / param-&gt;recout.width;</div><div class='add'>+		x_hot_viewport = pos-&gt;x_hotspot * param-&gt;viewport.width / param-&gt;recout.width;</div><div class='add'>+	} else {</div><div class='add'>+		ASSERT(!cur_en || x_pos == 0);</div><div class='add'>+		ASSERT(!cur_en || pos-&gt;x_hotspot == 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Guard aganst cursor_set_position() from being called with invalid</div><div class='add'>+	 * attributes</div><div class='add'>+	 */</div><div class='add'>+	if (hubp-&gt;curs_attr.address.quad_part == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Translate the x position of the cursor from rect</div><div class='add'>+	 * space into viewport space. CURSOR_DST_X_OFFSET</div><div class='add'>+	 * is the offset relative to viewport start position.</div><div class='add'>+	 */</div><div class='add'>+	dst_x_offset = x_pos_viewport - x_hot_viewport *</div><div class='add'>+			(1 + hubp-&gt;curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION);</div><div class='add'>+	dst_x_offset = (dst_x_offset &gt;= 0) ? dst_x_offset : 0;</div><div class='add'>+	dst_x_offset *= param-&gt;ref_clk_khz;</div><div class='add'>+	dst_x_offset /= param-&gt;pixel_clk_khz;</div><div class='add'>+</div><div class='add'>+	ASSERT(param-&gt;h_scale_ratio.value);</div><div class='add'>+</div><div class='add'>+	if (param-&gt;h_scale_ratio.value)</div><div class='add'>+		dst_x_offset = dc_fixpt_floor(dc_fixpt_div(</div><div class='add'>+			dc_fixpt_from_int(dst_x_offset),</div><div class='add'>+			param-&gt;h_scale_ratio));</div><div class='add'>+</div><div class='add'>+	if (hubp-&gt;pos.cur_ctl.bits.cur_enable != cur_en) {</div><div class='add'>+		if (cur_en &amp;&amp; REG_READ(CURSOR_SURFACE_ADDRESS) == 0)</div><div class='add'>+			hubp-&gt;funcs-&gt;set_cursor_attributes(hubp, &amp;hubp-&gt;curs_attr);</div><div class='add'>+</div><div class='add'>+		if (!hubp-&gt;cursor_offload)</div><div class='add'>+			REG_UPDATE(CURSOR_CONTROL,</div><div class='add'>+				CURSOR_ENABLE, cur_en);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!hubp-&gt;cursor_offload) {</div><div class='add'>+		REG_SET_2(CURSOR_POSITION, 0,</div><div class='add'>+			CURSOR_X_POSITION, x_pos,</div><div class='add'>+			CURSOR_Y_POSITION, y_pos);</div><div class='add'>+</div><div class='add'>+		REG_SET_2(CURSOR_HOT_SPOT, 0,</div><div class='add'>+			CURSOR_HOT_SPOT_X, pos-&gt;x_hotspot,</div><div class='add'>+			CURSOR_HOT_SPOT_Y, pos-&gt;y_hotspot);</div><div class='add'>+</div><div class='add'>+		REG_SET(CURSOR_DST_OFFSET, 0,</div><div class='add'>+			CURSOR_DST_X_OFFSET, dst_x_offset);</div><div class='add'>+	}</div><div class='add'>+	/* Cursor Position Register Config */</div><div class='add'>+	hubp-&gt;pos.cur_ctl.bits.cur_enable = cur_en;</div><div class='add'>+	hubp-&gt;pos.position.bits.x_pos = pos-&gt;x;</div><div class='add'>+	hubp-&gt;pos.position.bits.y_pos = pos-&gt;y;</div><div class='add'>+	hubp-&gt;pos.hot_spot.bits.x_hot = pos-&gt;x_hotspot;</div><div class='add'>+	hubp-&gt;pos.hot_spot.bits.y_hot = pos-&gt;y_hotspot;</div><div class='add'>+	hubp-&gt;pos.dst_offset.bits.dst_x_offset = dst_x_offset;</div><div class='add'>+	/* Cursor Rectangle Cache</div><div class='add'>+	 * Cursor bitmaps have different hotspot values</div><div class='add'>+	 * There's a possibility that the above logic returns a negative value,</div><div class='add'>+	 * so we clamp them to 0</div><div class='add'>+	 */</div><div class='add'>+	if (rec_x_offset &lt; 0)</div><div class='add'>+		rec_x_offset = 0;</div><div class='add'>+	if (rec_y_offset &lt; 0)</div><div class='add'>+		rec_y_offset = 0;</div><div class='add'>+	/* Save necessary cursor info x, y position. w, h is saved in attribute func. */</div><div class='add'>+	hubp-&gt;cur_rect.x = rec_x_offset + param-&gt;recout.x;</div><div class='add'>+	hubp-&gt;cur_rect.y = rec_y_offset + param-&gt;recout.y;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_read_state(struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+	struct dcn_hubp_state *s = &amp;hubp2-&gt;state;</div><div class='add'>+	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &amp;s-&gt;dlg_attr;</div><div class='add'>+	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &amp;s-&gt;ttu_attr;</div><div class='add'>+	struct _vcs_dpi_display_rq_regs_st *rq_regs = &amp;s-&gt;rq_regs;</div><div class='add'>+</div><div class='add'>+	/* Requester */</div><div class='add'>+	REG_GET(HUBPRET_CONTROL,</div><div class='add'>+			DET_BUF_PLANE1_BASE_ADDRESS, &amp;rq_regs-&gt;plane1_base_address);</div><div class='add'>+	REG_GET_4(DCN_EXPANSION_MODE,</div><div class='add'>+			DRQ_EXPANSION_MODE, &amp;rq_regs-&gt;drq_expansion_mode,</div><div class='add'>+			PRQ_EXPANSION_MODE, &amp;rq_regs-&gt;prq_expansion_mode,</div><div class='add'>+			MRQ_EXPANSION_MODE, &amp;rq_regs-&gt;mrq_expansion_mode,</div><div class='add'>+			CRQ_EXPANSION_MODE, &amp;rq_regs-&gt;crq_expansion_mode);</div><div class='add'>+</div><div class='add'>+	REG_GET_5(DCHUBP_REQ_SIZE_CONFIG,</div><div class='add'>+		CHUNK_SIZE, &amp;rq_regs-&gt;rq_regs_l.chunk_size,</div><div class='add'>+		MIN_CHUNK_SIZE, &amp;rq_regs-&gt;rq_regs_l.min_chunk_size,</div><div class='add'>+		DPTE_GROUP_SIZE, &amp;rq_regs-&gt;rq_regs_l.dpte_group_size,</div><div class='add'>+		SWATH_HEIGHT, &amp;rq_regs-&gt;rq_regs_l.swath_height,</div><div class='add'>+		PTE_ROW_HEIGHT_LINEAR, &amp;rq_regs-&gt;rq_regs_l.pte_row_height_linear);</div><div class='add'>+</div><div class='add'>+	REG_GET_5(DCHUBP_REQ_SIZE_CONFIG_C,</div><div class='add'>+		CHUNK_SIZE_C, &amp;rq_regs-&gt;rq_regs_c.chunk_size,</div><div class='add'>+		MIN_CHUNK_SIZE_C, &amp;rq_regs-&gt;rq_regs_c.min_chunk_size,</div><div class='add'>+		DPTE_GROUP_SIZE_C, &amp;rq_regs-&gt;rq_regs_c.dpte_group_size,</div><div class='add'>+		SWATH_HEIGHT_C, &amp;rq_regs-&gt;rq_regs_c.swath_height,</div><div class='add'>+		PTE_ROW_HEIGHT_LINEAR_C, &amp;rq_regs-&gt;rq_regs_c.pte_row_height_linear);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,</div><div class='add'>+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &amp;rq_regs-&gt;aperture_high_addr);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='add'>+			MC_VM_SYSTEM_APERTURE_LOW_ADDR, &amp;rq_regs-&gt;aperture_low_addr);</div><div class='add'>+</div><div class='add'>+	/* DLG - Per hubp */</div><div class='add'>+	REG_GET_2(BLANK_OFFSET_0,</div><div class='add'>+		REFCYC_H_BLANK_END, &amp;dlg_attr-&gt;refcyc_h_blank_end,</div><div class='add'>+		DLG_V_BLANK_END, &amp;dlg_attr-&gt;dlg_vblank_end);</div><div class='add'>+</div><div class='add'>+	REG_GET(BLANK_OFFSET_1,</div><div class='add'>+		MIN_DST_Y_NEXT_START, &amp;dlg_attr-&gt;min_dst_y_next_start);</div><div class='add'>+</div><div class='add'>+	REG_GET(DST_DIMENSIONS,</div><div class='add'>+		REFCYC_PER_HTOTAL, &amp;dlg_attr-&gt;refcyc_per_htotal);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(DST_AFTER_SCALER,</div><div class='add'>+		REFCYC_X_AFTER_SCALER, &amp;dlg_attr-&gt;refcyc_x_after_scaler,</div><div class='add'>+		DST_Y_AFTER_SCALER, &amp;dlg_attr-&gt;dst_y_after_scaler);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(PREFETCH_SETTINGS,</div><div class='add'>+		DST_Y_PREFETCH, &amp;dlg_attr-&gt;dst_y_prefetch,</div><div class='add'>+		VRATIO_PREFETCH, &amp;dlg_attr-&gt;vratio_prefetch);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(VBLANK_PARAMETERS_0,</div><div class='add'>+		DST_Y_PER_VM_VBLANK, &amp;dlg_attr-&gt;dst_y_per_vm_vblank,</div><div class='add'>+		DST_Y_PER_ROW_VBLANK, &amp;dlg_attr-&gt;dst_y_per_row_vblank);</div><div class='add'>+</div><div class='add'>+	REG_GET(REF_FREQ_TO_PIX_FREQ,</div><div class='add'>+		REF_FREQ_TO_PIX_FREQ, &amp;dlg_attr-&gt;ref_freq_to_pix_freq);</div><div class='add'>+</div><div class='add'>+	/* DLG - Per luma/chroma */</div><div class='add'>+	REG_GET(VBLANK_PARAMETERS_1,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_VBLANK_L, &amp;dlg_attr-&gt;refcyc_per_pte_group_vblank_l);</div><div class='add'>+</div><div class='add'>+	REG_GET(VBLANK_PARAMETERS_3,</div><div class='add'>+		REFCYC_PER_META_CHUNK_VBLANK_L, &amp;dlg_attr-&gt;refcyc_per_meta_chunk_vblank_l);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_0,</div><div class='add'>+		DST_Y_PER_PTE_ROW_NOM_L, &amp;dlg_attr-&gt;dst_y_per_pte_row_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_1,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_NOM_L, &amp;dlg_attr-&gt;refcyc_per_pte_group_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_4,</div><div class='add'>+		DST_Y_PER_META_ROW_NOM_L, &amp;dlg_attr-&gt;dst_y_per_meta_row_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_5,</div><div class='add'>+		REFCYC_PER_META_CHUNK_NOM_L, &amp;dlg_attr-&gt;refcyc_per_meta_chunk_nom_l);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(PER_LINE_DELIVERY_PRE,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_PRE_L, &amp;dlg_attr-&gt;refcyc_per_line_delivery_pre_l,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_PRE_C, &amp;dlg_attr-&gt;refcyc_per_line_delivery_pre_c);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(PER_LINE_DELIVERY,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_L, &amp;dlg_attr-&gt;refcyc_per_line_delivery_l,</div><div class='add'>+		REFCYC_PER_LINE_DELIVERY_C, &amp;dlg_attr-&gt;refcyc_per_line_delivery_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(PREFETCH_SETTINGS_C,</div><div class='add'>+		VRATIO_PREFETCH_C, &amp;dlg_attr-&gt;vratio_prefetch_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(VBLANK_PARAMETERS_2,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_VBLANK_C, &amp;dlg_attr-&gt;refcyc_per_pte_group_vblank_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(VBLANK_PARAMETERS_4,</div><div class='add'>+		REFCYC_PER_META_CHUNK_VBLANK_C, &amp;dlg_attr-&gt;refcyc_per_meta_chunk_vblank_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_2,</div><div class='add'>+		DST_Y_PER_PTE_ROW_NOM_C, &amp;dlg_attr-&gt;dst_y_per_pte_row_nom_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_3,</div><div class='add'>+		REFCYC_PER_PTE_GROUP_NOM_C, &amp;dlg_attr-&gt;refcyc_per_pte_group_nom_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_6,</div><div class='add'>+		DST_Y_PER_META_ROW_NOM_C, &amp;dlg_attr-&gt;dst_y_per_meta_row_nom_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(NOM_PARAMETERS_7,</div><div class='add'>+		REFCYC_PER_META_CHUNK_NOM_C, &amp;dlg_attr-&gt;refcyc_per_meta_chunk_nom_c);</div><div class='add'>+</div><div class='add'>+	/* TTU - per hubp */</div><div class='add'>+	REG_GET_2(DCN_TTU_QOS_WM,</div><div class='add'>+		QoS_LEVEL_LOW_WM, &amp;ttu_attr-&gt;qos_level_low_wm,</div><div class='add'>+		QoS_LEVEL_HIGH_WM, &amp;ttu_attr-&gt;qos_level_high_wm);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(DCN_GLOBAL_TTU_CNTL,</div><div class='add'>+		MIN_TTU_VBLANK, &amp;ttu_attr-&gt;min_ttu_vblank,</div><div class='add'>+		QoS_LEVEL_FLIP, &amp;ttu_attr-&gt;qos_level_flip);</div><div class='add'>+</div><div class='add'>+	/* TTU - per luma/chroma */</div><div class='add'>+	/* Assumed surf0 is luma and 1 is chroma */</div><div class='add'>+</div><div class='add'>+	REG_GET_3(DCN_SURF0_TTU_CNTL0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY, &amp;ttu_attr-&gt;refcyc_per_req_delivery_l,</div><div class='add'>+		QoS_LEVEL_FIXED, &amp;ttu_attr-&gt;qos_level_fixed_l,</div><div class='add'>+		QoS_RAMP_DISABLE, &amp;ttu_attr-&gt;qos_ramp_disable_l);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_SURF0_TTU_CNTL1,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY_PRE,</div><div class='add'>+		&amp;ttu_attr-&gt;refcyc_per_req_delivery_pre_l);</div><div class='add'>+</div><div class='add'>+	REG_GET_3(DCN_SURF1_TTU_CNTL0,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY, &amp;ttu_attr-&gt;refcyc_per_req_delivery_c,</div><div class='add'>+		QoS_LEVEL_FIXED, &amp;ttu_attr-&gt;qos_level_fixed_c,</div><div class='add'>+		QoS_RAMP_DISABLE, &amp;ttu_attr-&gt;qos_ramp_disable_c);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_SURF1_TTU_CNTL1,</div><div class='add'>+		REFCYC_PER_REQ_DELIVERY_PRE,</div><div class='add'>+		&amp;ttu_attr-&gt;refcyc_per_req_delivery_pre_c);</div><div class='add'>+</div><div class='add'>+	/* Rest of hubp */</div><div class='add'>+	REG_GET(DCSURF_SURFACE_CONFIG,</div><div class='add'>+			SURFACE_PIXEL_FORMAT, &amp;s-&gt;pixel_format);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,</div><div class='add'>+			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &amp;s-&gt;inuse_addr_hi);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,</div><div class='add'>+			SURFACE_EARLIEST_INUSE_ADDRESS, &amp;s-&gt;inuse_addr_lo);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,</div><div class='add'>+			PRI_VIEWPORT_WIDTH, &amp;s-&gt;viewport_width,</div><div class='add'>+			PRI_VIEWPORT_HEIGHT, &amp;s-&gt;viewport_height);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(DCSURF_SURFACE_CONFIG,</div><div class='add'>+			ROTATION_ANGLE, &amp;s-&gt;rotation_angle,</div><div class='add'>+			H_MIRROR_EN, &amp;s-&gt;h_mirror_en);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCSURF_TILING_CONFIG,</div><div class='add'>+			SW_MODE, &amp;s-&gt;sw_mode);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCSURF_SURFACE_CONTROL,</div><div class='add'>+			PRIMARY_SURFACE_DCC_EN, &amp;s-&gt;dcc_en);</div><div class='add'>+</div><div class='add'>+	REG_GET_3(DCHUBP_CNTL,</div><div class='add'>+			HUBP_BLANK_EN, &amp;s-&gt;blank_en,</div><div class='add'>+			HUBP_TTU_DISABLE, &amp;s-&gt;ttu_disable,</div><div class='add'>+			HUBP_UNDERFLOW_STATUS, &amp;s-&gt;underflow_status);</div><div class='add'>+</div><div class='add'>+	REG_GET(HUBP_CLK_CNTL,</div><div class='add'>+			HUBP_CLOCK_ENABLE, &amp;s-&gt;clock_en);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_GLOBAL_TTU_CNTL,</div><div class='add'>+			MIN_TTU_VBLANK, &amp;s-&gt;min_ttu_vblank);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(DCN_TTU_QOS_WM,</div><div class='add'>+			QoS_LEVEL_LOW_WM, &amp;s-&gt;qos_level_low_wm,</div><div class='add'>+			QoS_LEVEL_HIGH_WM, &amp;s-&gt;qos_level_high_wm);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,</div><div class='add'>+			PRIMARY_SURFACE_ADDRESS, &amp;s-&gt;primary_surface_addr_lo);</div><div class='add'>+</div><div class='add'>+	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,</div><div class='add'>+			PRIMARY_SURFACE_ADDRESS, &amp;s-&gt;primary_surface_addr_hi);</div><div class='add'>+</div><div class='add'>+	s-&gt;uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);</div><div class='add'>+</div><div class='add'>+	s-&gt;hubp_cntl = REG_READ(DCHUBP_CNTL);</div><div class='add'>+	s-&gt;flip_control = REG_READ(DCSURF_FLIP_CONTROL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);</div><div class='add'>+</div><div class='add'>+	/* To ensure that cursor fetching starts as early as possible in</div><div class='add'>+	 * the display prefetch, set CURSOR_REQ_MODE = 1 always.</div><div class='add'>+	 * The setting of CURSOR_REQ_MODE = 0 is no longer supported in</div><div class='add'>+	 * DCN4x as a fall back to legacy behavior of fetching cursor</div><div class='add'>+	 * just before it appears on the screen.</div><div class='add'>+	 */</div><div class='add'>+	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hubp_funcs dcn401_hubp_funcs = {</div><div class='add'>+	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,</div><div class='add'>+	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,</div><div class='add'>+	.hubp_program_surface_flip_and_addr = hubp401_program_surface_flip_and_addr,</div><div class='add'>+	.hubp_program_surface_config = hubp401_program_surface_config,</div><div class='add'>+	.hubp_is_flip_pending = hubp2_is_flip_pending,</div><div class='add'>+	.hubp_setup2 = hubp401_setup,</div><div class='add'>+	.hubp_setup_interdependent2 = hubp401_setup_interdependent,</div><div class='add'>+	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,</div><div class='add'>+	.set_blank = hubp2_set_blank,</div><div class='add'>+	.set_blank_regs = hubp2_set_blank_regs,</div><div class='add'>+	.hubp_reset = hubp_reset,</div><div class='add'>+	.mem_program_viewport = hubp401_set_viewport,</div><div class='add'>+	.set_cursor_attributes	= hubp32_cursor_set_attributes,</div><div class='add'>+	.set_cursor_position	= hubp401_cursor_set_position,</div><div class='add'>+	.hubp_clk_cntl = hubp2_clk_cntl,</div><div class='add'>+	.hubp_vtg_sel = hubp2_vtg_sel,</div><div class='add'>+	.dmdata_set_attributes = hubp3_dmdata_set_attributes,</div><div class='add'>+	.dmdata_load = hubp2_dmdata_load,</div><div class='add'>+	.dmdata_status_done = hubp2_dmdata_status_done,</div><div class='add'>+	.hubp_read_state = hubp401_read_state,</div><div class='add'>+	.hubp_clear_underflow = hubp2_clear_underflow,</div><div class='add'>+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,</div><div class='add'>+	.hubp_init = hubp401_init,</div><div class='add'>+	.set_unbounded_requesting = hubp401_set_unbounded_requesting,</div><div class='add'>+	.hubp_soft_reset = hubp31_soft_reset,</div><div class='add'>+	.hubp_set_flip_int = hubp401_set_flip_int,</div><div class='add'>+	.hubp_in_blank = hubp401_in_blank,</div><div class='add'>+	.phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,</div><div class='add'>+	.hubp_update_mall_sel = hubp401_update_mall_sel,</div><div class='add'>+	.hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering,</div><div class='add'>+	.hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate,</div><div class='add'>+	.hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale,</div><div class='add'>+	.hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode,</div><div class='add'>+	.hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format,</div><div class='add'>+	.hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr,</div><div class='add'>+	.hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param,</div><div class='add'>+	.hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl,</div><div class='add'>+	.hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode,</div><div class='add'>+	.hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width,</div><div class='add'>+	.hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected,</div><div class='add'>+	.hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar,</div><div class='add'>+	.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,</div><div class='add'>+	.hubp_clear_tiling = hubp401_clear_tiling,</div><div class='add'>+	.hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config,</div><div class='add'>+	.hubp_read_reg_state = hubp3_read_reg_state</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool hubp401_construct(</div><div class='add'>+	struct dcn20_hubp *hubp2,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst,</div><div class='add'>+	const struct dcn_hubp2_registers *hubp_regs,</div><div class='add'>+	const struct dcn_hubp2_shift *hubp_shift,</div><div class='add'>+	const struct dcn_hubp2_mask *hubp_mask)</div><div class='add'>+{</div><div class='add'>+	hubp2-&gt;base.funcs = &amp;dcn401_hubp_funcs;</div><div class='add'>+	hubp2-&gt;base.ctx = ctx;</div><div class='add'>+	hubp2-&gt;hubp_regs = hubp_regs;</div><div class='add'>+	hubp2-&gt;hubp_shift = hubp_shift;</div><div class='add'>+	hubp2-&gt;hubp_mask = hubp_mask;</div><div class='add'>+	hubp2-&gt;base.inst = inst;</div><div class='add'>+	hubp2-&gt;base.opp_id = OPP_ID_INVALID;</div><div class='add'>+	hubp2-&gt;base.mpcc_id = 0xf;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h<br/>new file mode 100644<br/>index 000000000000..4570b8016de5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h</a></div><div class='hunk'>@@ -0,0 +1,373 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_HUBP_DCN401_H__</div><div class='add'>+#define __DC_HUBP_DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "dcn20/dcn20_hubp.h"</div><div class='add'>+#include "dcn21/dcn21_hubp.h"</div><div class='add'>+#include "dcn30/dcn30_hubp.h"</div><div class='add'>+#include "dcn31/dcn31_hubp.h"</div><div class='add'>+#include "dcn32/dcn32_hubp.h"</div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"</div><div class='add'>+</div><div class='add'>+#define HUBP_3DLUT_FL_REG_LIST_DCN401(inst)\</div><div class='add'>+	SRI_ARR_US(_3DLUT_FL_CONFIG, HUBP, inst),\</div><div class='add'>+	SRI_ARR_US(_3DLUT_FL_BIAS_SCALE, HUBP, inst),\</div><div class='add'>+	SRI_ARR(HUBP_3DLUT_ADDRESS_HIGH, CURSOR0_, inst),\</div><div class='add'>+	SRI_ARR(HUBP_3DLUT_ADDRESS_LOW, CURSOR0_, inst),\</div><div class='add'>+	SRI_ARR(HUBP_3DLUT_CONTROL, CURSOR0_, inst),\</div><div class='add'>+	SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, inst)</div><div class='add'>+</div><div class='add'>+#define HUBP_MASK_SH_LIST_DCN401(mask_sh)\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\</div><div class='add'>+	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \</div><div class='add'>+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_REQ_MODE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \</div><div class='add'>+	HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_SEL, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, VMPG_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, PTE_BUFFER_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, BIGK_FRAGMENT_SIZE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, DATA_UCLK_PSTATE_FORCE_VALUE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_EN, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPREQ0_UCLK_PSTATE_FORCE, CURSOR_UCLK_PSTATE_FORCE_VALUE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MALL_CONFIG, MALL_PREF_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_SCALE, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_Y_G, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_CB_B, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_CR_R, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW, HUBP_3DLUT_ADDRESS_LOW, mask_sh),\</div><div class='add'>+	HUBP_SF(CURSOR0_0_HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, VIEWPORT_MCACHE_SPLIT_COORDINATE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, VIEWPORT_MCACHE_SPLIT_COORDINATE_C, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_1H_P0, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_2H_P0, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_1H_P1, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_REG_READ_2H_P1, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P0, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P0, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P1, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\</div><div class='add'>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh)</div><div class='add'>+</div><div class='add'>+void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);</div><div class='add'>+</div><div class='add'>+void hubp401_setup(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+	    struct dml2_dchub_per_pipe_register_set *pipe_regs,</div><div class='add'>+		union dml2_global_sync_programming *pipe_global_sync,</div><div class='add'>+		struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='add'>+void hubp401_setup_interdependent(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *pipe_regs);</div><div class='add'>+</div><div class='add'>+bool hubp401_program_surface_flip_and_addr(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	const struct dc_plane_address *address,</div><div class='add'>+	bool flip_immediate);</div><div class='add'>+</div><div class='add'>+void hubp401_dcc_control(struct hubp *hubp,</div><div class='add'>+		struct dc_plane_dcc_param *dcc);</div><div class='add'>+</div><div class='add'>+void hubp401_program_tiling(</div><div class='add'>+	struct dcn20_hubp *hubp2,</div><div class='add'>+	const struct dc_tiling_info *info,</div><div class='add'>+	const enum surface_pixel_format pixel_format);</div><div class='add'>+</div><div class='add'>+void hubp401_program_size(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	enum surface_pixel_format format,</div><div class='add'>+	const struct plane_size *plane_size,</div><div class='add'>+	struct dc_plane_dcc_param *dcc);</div><div class='add'>+</div><div class='add'>+void hubp401_program_surface_config(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	enum surface_pixel_format format,</div><div class='add'>+	struct dc_tiling_info *tiling_info,</div><div class='add'>+	struct plane_size *plane_size,</div><div class='add'>+	enum dc_rotation_angle rotation,</div><div class='add'>+	struct dc_plane_dcc_param *dcc,</div><div class='add'>+	bool horizontal_mirror,</div><div class='add'>+	unsigned int compat_level);</div><div class='add'>+</div><div class='add'>+void hubp401_set_viewport(struct hubp *hubp,</div><div class='add'>+		const struct rect *viewport,</div><div class='add'>+		const struct rect *viewport_c);</div><div class='add'>+void hubp401_program_mcache_id_and_split_coordinate(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs *mcache_regs);</div><div class='add'>+void hubp401_set_flip_int(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+bool hubp401_in_blank(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hubp401_cursor_set_position(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	const struct dc_cursor_position *pos,</div><div class='add'>+	const struct dc_cursor_mi_param *param);</div><div class='add'>+</div><div class='add'>+void hubp401_read_state(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+bool hubp401_construct(</div><div class='add'>+	struct dcn20_hubp *hubp2,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst,</div><div class='add'>+	const struct dcn_hubp2_registers *hubp_regs,</div><div class='add'>+	const struct dcn_hubp2_shift *hubp_shift,</div><div class='add'>+	const struct dcn_hubp2_mask *hubp_mask);</div><div class='add'>+</div><div class='add'>+void hubp401_init(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+int hubp401_get_3dlut_fl_done(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);</div><div class='add'>+</div><div class='add'>+void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);</div><div class='add'>+</div><div class='add'>+void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);</div><div class='add'>+</div><div class='add'>+void hubp401_program_3dlut_fl_config(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	struct hubp_fl_3dlut_config *cfg);</div><div class='add'>+</div><div class='add'>+void hubp401_clear_tiling(struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hubp401_vready_at_or_After_vsync(struct hubp *hubp,</div><div class='add'>+	union dml2_global_sync_programming *pipe_global_sync,</div><div class='add'>+	struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='add'>+void hubp401_program_requestor(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	struct dml2_display_rq_regs *rq_regs);</div><div class='add'>+</div><div class='add'>+void hubp401_program_deadline(</div><div class='add'>+	struct hubp *hubp,</div><div class='add'>+	struct dml2_display_dlg_regs *dlg_attr,</div><div class='add'>+	struct dml2_display_ttu_regs *ttu_attr);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_HUBP_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile<br/>index 9e8e9de51a92..bee617ca0838 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/Makefile</a></div><div class='hunk'>@@ -27,6 +27,24 @@</div><div class='ctx'> #  DCE</div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_SI</div><div class='add'>+HWSS_DCE60 = dce60_hwseq.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HWSS_DCE60 = $(addprefix $(AMDDALPATH)/dc/hwss/dce60/,$(HWSS_DCE60))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCE60)</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+HWSS_DCE80 = dce80_hwseq.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HWSS_DCE80 = $(addprefix $(AMDDALPATH)/dc/hwss/dce80/,$(HWSS_DCE80))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCE80)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='ctx'> HWSS_DCE = dce_hwseq.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCE = $(addprefix $(AMDDALPATH)/dc/hwss/dce/,$(HWSS_DCE))</div><div class='hunk'>@@ -65,14 +83,6 @@ AMD_DAL_HWSS_DCE120 = $(addprefix $(AMDDALPATH)/dc/hwss/dce120/,$(HWSS_DCE120))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCE120)</div><div class='ctx'> </div><div class='del'>-###############################################################################</div><div class='del'>-</div><div class='del'>-HWSS_DCE80 = dce80_hwseq.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_HWSS_DCE80 = $(addprefix $(AMDDALPATH)/dc/hwss/dce80/,$(HWSS_DCE80))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCE80)</div><div class='del'>-</div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> ###############################################################################</div><div class='ctx'> # DCN</div><div class='hunk'>@@ -110,10 +120,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN21)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-###############################################################################</div><div class='del'>-</div><div class='del'>-###############################################################################</div><div class='del'>-</div><div class='ctx'> HWSS_DCN30 = dcn30_hwseq.o dcn30_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN30 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn30/,$(HWSS_DCN30))</div><div class='hunk'>@@ -180,7 +186,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN35)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN351 = dcn351_init.o</div><div class='add'>+HWSS_DCN351 = dcn351_hwseq.o dcn351_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN351 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn351/,$(HWSS_DCN351))</div><div class='ctx'> </div><div class='hunk'>@@ -188,6 +194,9 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN351)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-###############################################################################</div><div class='add'>+HWSS_DCN401 = dcn401_hwseq.o dcn401_init.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_HWSS_DCN401 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn401/,$(HWSS_DCN401))</div><div class='ctx'> </div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN401)</div><div class='ctx'> endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h<br/>index 52f045cfd52a..f66a38f43a09 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h</a></div><div class='hunk'>@@ -644,10 +644,18 @@ struct dce_hwseq_registers {</div><div class='ctx'> 	uint32_t DPP_TOP0_DPP_CRC_CTRL;</div><div class='ctx'> 	uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;</div><div class='ctx'> 	uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;</div><div class='add'>+	uint32_t DPP_TOP0_DPP_CRC_VAL_R;</div><div class='add'>+	uint32_t DPP_TOP0_DPP_CRC_VAL_G;</div><div class='add'>+	uint32_t DPP_TOP0_DPP_CRC_VAL_B;</div><div class='add'>+	uint32_t DPP_TOP0_DPP_CRC_VAL_A;</div><div class='ctx'> 	uint32_t MPC_CRC_CTRL;</div><div class='ctx'> 	uint32_t MPC_CRC_RESULT_GB;</div><div class='ctx'> 	uint32_t MPC_CRC_RESULT_C;</div><div class='ctx'> 	uint32_t MPC_CRC_RESULT_AR;</div><div class='add'>+	uint32_t MPC_CRC_RESULT_R;</div><div class='add'>+	uint32_t MPC_CRC_RESULT_G;</div><div class='add'>+	uint32_t MPC_CRC_RESULT_B;</div><div class='add'>+	uint32_t MPC_CRC_RESULT_A;</div><div class='ctx'> 	uint32_t D1VGA_CONTROL;</div><div class='ctx'> 	uint32_t D2VGA_CONTROL;</div><div class='ctx'> 	uint32_t D3VGA_CONTROL;</div><div class='hunk'>@@ -684,6 +692,14 @@ struct dce_hwseq_registers {</div><div class='ctx'> 	uint32_t DMU_CLK_CNTL;</div><div class='ctx'> 	uint32_t DCCG_GATE_DISABLE_CNTL4;</div><div class='ctx'> 	uint32_t DCCG_GATE_DISABLE_CNTL5;</div><div class='add'>+	uint32_t DOMAIN22_PG_CONFIG;</div><div class='add'>+	uint32_t DOMAIN23_PG_CONFIG;</div><div class='add'>+	uint32_t DOMAIN24_PG_CONFIG;</div><div class='add'>+	uint32_t DOMAIN25_PG_CONFIG;</div><div class='add'>+	uint32_t DOMAIN22_PG_STATUS;</div><div class='add'>+	uint32_t DOMAIN23_PG_STATUS;</div><div class='add'>+	uint32_t DOMAIN24_PG_STATUS;</div><div class='add'>+	uint32_t DOMAIN25_PG_STATUS;</div><div class='ctx'> };</div><div class='ctx'>  /* set field name */</div><div class='ctx'> #define HWS_SF(blk_name, reg_name, field_name, post_fix)\</div><div class='hunk'>@@ -1214,6 +1230,21 @@ struct dce_hwseq_registers {</div><div class='ctx'> 	type DPIASYMCLK2_GATE_DISABLE;\</div><div class='ctx'> 	type DPIASYMCLK3_GATE_DISABLE;</div><div class='ctx'> </div><div class='add'>+#define HWSEQ_DCN401_REG_FIELD_LIST(type) \</div><div class='add'>+	type DOMAIN22_POWER_FORCEON; \</div><div class='add'>+	type DOMAIN22_POWER_GATE; \</div><div class='add'>+	type DOMAIN23_POWER_FORCEON; \</div><div class='add'>+	type DOMAIN23_POWER_GATE; \</div><div class='add'>+	type DOMAIN24_POWER_FORCEON; \</div><div class='add'>+	type DOMAIN24_POWER_GATE; \</div><div class='add'>+	type DOMAIN25_POWER_FORCEON; \</div><div class='add'>+	type DOMAIN25_POWER_GATE; \</div><div class='add'>+	type DOMAIN22_PGFSM_PWR_STATUS; \</div><div class='add'>+	type DOMAIN23_PGFSM_PWR_STATUS; \</div><div class='add'>+	type DOMAIN24_PGFSM_PWR_STATUS; \</div><div class='add'>+	type DOMAIN25_PGFSM_PWR_STATUS; \</div><div class='add'>+	type DOMAIN_DESIRED_PWR_STATE;</div><div class='add'>+</div><div class='ctx'> struct dce_hwseq_shift {</div><div class='ctx'> 	HWSEQ_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> 	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)</div><div class='hunk'>@@ -1221,6 +1252,7 @@ struct dce_hwseq_shift {</div><div class='ctx'> 	HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> 	HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> 	HWSEQ_DCN35_REG_FIELD_LIST(uint8_t)</div><div class='add'>+	HWSEQ_DCN401_REG_FIELD_LIST(uint8_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dce_hwseq_mask {</div><div class='hunk'>@@ -1230,6 +1262,7 @@ struct dce_hwseq_mask {</div><div class='ctx'> 	HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> 	HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> 	HWSEQ_DCN35_REG_FIELD_LIST(uint32_t)</div><div class='add'>+	HWSEQ_DCN401_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c<br/>index f1f14796a3da..0d7e28260db1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c</a></div><div class='hunk'>@@ -138,5 +138,35 @@ void dce100_hw_sequencer_construct(struct dc *dc)</div><div class='ctx'> 	dc-&gt;hwseq-&gt;funcs.enable_display_power_gating = dce100_enable_display_power_gating;</div><div class='ctx'> 	dc-&gt;hwss.prepare_bandwidth = dce100_prepare_bandwidth;</div><div class='ctx'> 	dc-&gt;hwss.optimize_bandwidth = dce100_optimize_bandwidth;</div><div class='add'>+	dc-&gt;hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dce100_reset_surface_dcc_and_tiling - Set DCC and tiling in DCE to their disable mode.</div><div class='add'>+ *</div><div class='add'>+ * @pipe_ctx: Pointer to the pipe context structure.</div><div class='add'>+ * @plane_state: Surface state</div><div class='add'>+ * @clear_tiling: If true set tiling to Linear, otherwise does not change tiling</div><div class='add'>+ *</div><div class='add'>+ * This function is responsible for call the HUBP block to disable DCC and set</div><div class='add'>+ * tiling to the linear mode.</div><div class='add'>+ */</div><div class='add'>+void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,</div><div class='add'>+					struct dc_plane_state *plane_state,</div><div class='add'>+					bool clear_tiling)</div><div class='add'>+{</div><div class='add'>+	struct mem_input *mi = pipe_ctx-&gt;plane_res.mi;</div><div class='add'>+</div><div class='add'>+	if (!mi)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* if framebuffer is tiled, disable tiling */</div><div class='add'>+	if (clear_tiling &amp;&amp; mi-&gt;funcs-&gt;mem_input_clear_tiling)</div><div class='add'>+		mi-&gt;funcs-&gt;mem_input_clear_tiling(mi);</div><div class='add'>+</div><div class='add'>+	/* force page flip to see the new content of the framebuffer */</div><div class='add'>+	mi-&gt;funcs-&gt;mem_input_program_surface_flip_and_addr(mi,</div><div class='add'>+							   &amp;plane_state-&gt;address,</div><div class='add'>+							   true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h<br/>index 34518da20009..fadfa794f96b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.h</a></div><div class='hunk'>@@ -46,5 +46,9 @@ bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,</div><div class='ctx'> 					struct dc_bios *dcb,</div><div class='ctx'> 					enum pipe_gating_control power_gating);</div><div class='ctx'> </div><div class='add'>+void dce100_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,</div><div class='add'>+					struct dc_plane_state *plane_state,</div><div class='add'>+					bool clear_tiling);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCE100_H__ */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c<br/>index 9d5df4c0da59..8fe399939220 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #include "dce110_hwseq.h"</div><div class='ctx'> #include "dce110/dce110_timing_generator.h"</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='add'>+#include "dce100/dce100_hwseq.h"</div><div class='ctx'> #include "gpio_service_interface.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce110/dce110_compressor.h"</div><div class='hunk'>@@ -47,7 +48,7 @@</div><div class='ctx'> #include "link_encoder.h"</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> #include "link_hwss.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dccg.h"</div><div class='ctx'> #include "clock_source.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='hunk'>@@ -57,6 +58,7 @@</div><div class='ctx'> #include "panel_cntl.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='add'>+#include "dsc.h"</div><div class='ctx'> /* include DCE11 register header files */</div><div class='ctx'> #include "dce/dce_11_0_d.h"</div><div class='ctx'> #include "dce/dce_11_0_sh_mask.h"</div><div class='hunk'>@@ -249,7 +251,7 @@ static bool dce110_enable_display_power_gating(</div><div class='ctx'> 		return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void build_prescale_params(struct ipp_prescale_params *prescale_params,</div><div class='add'>+static void dce110_prescale_params(struct ipp_prescale_params *prescale_params,</div><div class='ctx'> 		const struct dc_plane_state *plane_state)</div><div class='ctx'> {</div><div class='ctx'> 	prescale_params-&gt;mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;</div><div class='hunk'>@@ -289,21 +291,16 @@ dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	if (ipp == NULL)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func)</div><div class='del'>-		tf = plane_state-&gt;in_transfer_func;</div><div class='add'>+	tf = &amp;plane_state-&gt;in_transfer_func;</div><div class='ctx'> </div><div class='del'>-	build_prescale_params(&amp;prescale_params, plane_state);</div><div class='add'>+	dce110_prescale_params(&amp;prescale_params, plane_state);</div><div class='ctx'> 	ipp-&gt;funcs-&gt;ipp_program_prescale(ipp, &amp;prescale_params);</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;gamma_correction &amp;&amp;</div><div class='del'>-			!plane_state-&gt;gamma_correction-&gt;is_identity &amp;&amp;</div><div class='add'>+	if (!plane_state-&gt;gamma_correction.is_identity &amp;&amp;</div><div class='ctx'> 			dce_use_lut(plane_state-&gt;format))</div><div class='del'>-		ipp-&gt;funcs-&gt;ipp_program_input_lut(ipp, plane_state-&gt;gamma_correction);</div><div class='add'>+		ipp-&gt;funcs-&gt;ipp_program_input_lut(ipp, &amp;plane_state-&gt;gamma_correction);</div><div class='ctx'> </div><div class='del'>-	if (tf == NULL) {</div><div class='del'>-		/* Default case if no input transfer function specified */</div><div class='del'>-		ipp-&gt;funcs-&gt;ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);</div><div class='del'>-	} else if (tf-&gt;type == TF_TYPE_PREDEFINED) {</div><div class='add'>+	if (tf-&gt;type == TF_TYPE_PREDEFINED) {</div><div class='ctx'> 		switch (tf-&gt;tf) {</div><div class='ctx'> 		case TRANSFER_FUNCTION_SRGB:</div><div class='ctx'> 			ipp-&gt;funcs-&gt;ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);</div><div class='hunk'>@@ -614,11 +611,10 @@ dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	xfm-&gt;funcs-&gt;opp_power_on_regamma_lut(xfm, true);</div><div class='ctx'> 	xfm-&gt;regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;</div><div class='ctx'> </div><div class='del'>-	if (stream-&gt;out_transfer_func &amp;&amp;</div><div class='del'>-	    stream-&gt;out_transfer_func-&gt;type == TF_TYPE_PREDEFINED &amp;&amp;</div><div class='del'>-	    stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_SRGB) {</div><div class='add'>+	if (stream-&gt;out_transfer_func.type == TF_TYPE_PREDEFINED &amp;&amp;</div><div class='add'>+	    stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_SRGB) {</div><div class='ctx'> 		xfm-&gt;funcs-&gt;opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);</div><div class='del'>-	} else if (dce110_translate_regamma_to_hw_format(stream-&gt;out_transfer_func,</div><div class='add'>+	} else if (dce110_translate_regamma_to_hw_format(&amp;stream-&gt;out_transfer_func,</div><div class='ctx'> 							 &amp;xfm-&gt;regamma_params)) {</div><div class='ctx'> 		xfm-&gt;funcs-&gt;opp_program_regamma_pwl(xfm, &amp;xfm-&gt;regamma_params);</div><div class='ctx'> 		xfm-&gt;funcs-&gt;opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);</div><div class='hunk'>@@ -663,6 +659,20 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void</div><div class='add'>+dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+	struct dc_bios *bios = link-&gt;ctx-&gt;dc_bios;</div><div class='add'>+	struct bp_encoder_control encoder_control = {0};</div><div class='add'>+</div><div class='add'>+	encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE;</div><div class='add'>+	encoder_control.engine_id = link-&gt;link_enc-&gt;analog_engine;</div><div class='add'>+	encoder_control.pixel_clock = pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz / 10;</div><div class='add'>+</div><div class='add'>+	bios-&gt;funcs-&gt;encoder_control(bios, &amp;encoder_control);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dce110_enable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_lane_count lane_count =</div><div class='hunk'>@@ -692,6 +702,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		early_control = lane_count;</div><div class='ctx'> </div><div class='ctx'> 	tg-&gt;funcs-&gt;set_early_control(tg, early_control);</div><div class='add'>+</div><div class='add'>+	if (dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		dce110_dac_encoder_control(pipe_ctx, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result link_transmitter_control(</div><div class='hunk'>@@ -748,12 +761,10 @@ void dce110_edp_wait_for_hpd_ready(</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (link != NULL) {</div><div class='del'>-		if (link-&gt;panel_config.pps.extra_t3_ms &gt; 0) {</div><div class='del'>-			int extra_t3_in_ms = link-&gt;panel_config.pps.extra_t3_ms;</div><div class='add'>+	if (link-&gt;panel_config.pps.extra_t3_ms &gt; 0) {</div><div class='add'>+		int extra_t3_in_ms = link-&gt;panel_config.pps.extra_t3_ms;</div><div class='ctx'> </div><div class='del'>-			msleep(extra_t3_in_ms);</div><div class='del'>-		}</div><div class='add'>+		msleep(extra_t3_in_ms);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);</div><div class='hunk'>@@ -957,9 +968,9 @@ void dce110_edp_backlight_control(</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *ctx = link-&gt;ctx;</div><div class='ctx'> 	struct bp_transmitter_control cntl = { 0 };</div><div class='del'>-	uint8_t pwrseq_instance;</div><div class='del'>-	unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;</div><div class='del'>-	unsigned int post_T7_delay = OLED_POST_T7_DELAY;</div><div class='add'>+	uint8_t pwrseq_instance = 0;</div><div class='add'>+	unsigned int pre_T11_delay = (link-&gt;dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0);</div><div class='add'>+	unsigned int post_T7_delay = (link-&gt;dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0);</div><div class='ctx'> </div><div class='ctx'> 	if (dal_graphics_object_id_get_connector_id(link-&gt;link_enc-&gt;connector)</div><div class='ctx'> 		!= CONNECTOR_ID_EDP) {</div><div class='hunk'>@@ -1010,7 +1021,8 @@ void dce110_edp_backlight_control(</div><div class='ctx'> 	 */</div><div class='ctx'> 	/* dc_service_sleep_in_milliseconds(50); */</div><div class='ctx'> 		/*edp 1.2*/</div><div class='del'>-	pwrseq_instance = link-&gt;panel_cntl-&gt;pwrseq_inst;</div><div class='add'>+	if (link-&gt;panel_cntl)</div><div class='add'>+		pwrseq_instance = link-&gt;panel_cntl-&gt;pwrseq_inst;</div><div class='ctx'> </div><div class='ctx'> 	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {</div><div class='ctx'> 		if (!link-&gt;dc-&gt;config.edp_no_power_sequencing)</div><div class='hunk'>@@ -1045,7 +1057,8 @@ void dce110_edp_backlight_control(</div><div class='ctx'> 	link_transmitter_control(ctx-&gt;dc_bios, &amp;cntl);</div><div class='ctx'> </div><div class='ctx'> 	if (enable &amp;&amp; link-&gt;dpcd_sink_ext_caps.bits.oled &amp;&amp;</div><div class='del'>-	    !link-&gt;dc-&gt;config.edp_no_power_sequencing) {</div><div class='add'>+	    !link-&gt;dc-&gt;config.edp_no_power_sequencing &amp;&amp;</div><div class='add'>+	    !link-&gt;local_sink-&gt;edid_caps.panel_patch.oled_optimize_display_on) {</div><div class='ctx'> 		post_T7_delay += link-&gt;panel_config.pps.extra_post_t7_ms;</div><div class='ctx'> 		msleep(post_T7_delay);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1070,9 +1083,11 @@ void dce110_edp_backlight_control(</div><div class='ctx'> 			DC_LOG_DC("edp_receiver_ready_T9 skipped\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!enable &amp;&amp; link-&gt;dpcd_sink_ext_caps.bits.oled) {</div><div class='add'>+	if (!enable) {</div><div class='add'>+		/*follow oem panel config's requirement*/</div><div class='ctx'> 		pre_T11_delay += link-&gt;panel_config.pps.extra_pre_t11_ms;</div><div class='del'>-		msleep(pre_T11_delay);</div><div class='add'>+		if (pre_T11_delay)</div><div class='add'>+			msleep(pre_T11_delay);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1087,6 +1102,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	if (!pipe_ctx-&gt;stream)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	clk_mgr = dc-&gt;clk_mgr;</div><div class='ctx'> 	link_hwss = get_link_hwss(pipe_ctx-&gt;stream-&gt;link, &amp;pipe_ctx-&gt;link_res);</div><div class='hunk'>@@ -1123,6 +1141,9 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	if (!pipe_ctx || !pipe_ctx-&gt;stream)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	clk_mgr = dc-&gt;clk_mgr;</div><div class='ctx'> 	link_hwss = get_link_hwss(pipe_ctx-&gt;stream-&gt;link, &amp;pipe_ctx-&gt;link_res);</div><div class='hunk'>@@ -1157,9 +1178,12 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='ctx'> 	struct dtbclk_dto_params dto_params = {0};</div><div class='ctx'> 	int dp_hpo_inst;</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='ctx'> </div><div class='add'>+	if (!dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='ctx'> 	if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;stop_hdmi_info_packets(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.stream_enc);</div><div class='hunk'>@@ -1185,22 +1209,18 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		if (dccg) {</div><div class='ctx'> 			dccg-&gt;funcs-&gt;disable_symclk32_se(dccg, dp_hpo_inst);</div><div class='ctx'> 			dccg-&gt;funcs-&gt;set_dpstreamclk(dccg, REFCLK, tg-&gt;inst, dp_hpo_inst);</div><div class='del'>-			dccg-&gt;funcs-&gt;set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='add'>+			if (!(dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_3_5)) {</div><div class='add'>+				if (dccg &amp;&amp; dccg-&gt;funcs-&gt;set_dtbclk_dto)</div><div class='add'>+					dccg-&gt;funcs-&gt;set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (dccg &amp;&amp; dccg-&gt;funcs-&gt;disable_symclk_se) {</div><div class='ctx'> 		dccg-&gt;funcs-&gt;disable_symclk_se(dccg, stream_enc-&gt;stream_enc_inst,</div><div class='ctx'> 					       link_enc-&gt;transmitter - TRANSMITTER_UNIPHY_A);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='del'>-		/* TODO: This looks like a bug to me as we are disabling HPO IO when</div><div class='del'>-		 * we are just disabling a single HPO stream. Shouldn't we disable HPO</div><div class='del'>-		 * HW control only when HPOs for all streams are disabled?</div><div class='del'>-		 */</div><div class='del'>-		if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;hwseq-&gt;funcs.setup_hpo_hw_control)</div><div class='del'>-			pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;hwseq-&gt;funcs.setup_hpo_hw_control(</div><div class='del'>-					pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;hwseq, false);</div><div class='del'>-	}</div><div class='add'>+	if (dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		dce110_dac_encoder_control(pipe_ctx, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='hunk'>@@ -1229,8 +1249,11 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='ctx'> 	struct dce_hwseq *hws = link-&gt;dc-&gt;hwseq;</div><div class='ctx'> </div><div class='add'>+	if (hws &amp;&amp; hws-&gt;wa_state.skip_blank_stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;local_sink &amp;&amp; link-&gt;local_sink-&gt;sink_signal == SIGNAL_TYPE_EDP) {</div><div class='del'>-		if (!link-&gt;skip_implict_edp_power_control)</div><div class='add'>+		if (!link-&gt;skip_implict_edp_power_control &amp;&amp; hws)</div><div class='ctx'> 			hws-&gt;funcs.edp_backlight_control(link, false);</div><div class='ctx'> 		link-&gt;dc-&gt;hwss.set_abm_immediate_disable(pipe_ctx);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1248,20 +1271,21 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 			 * has changed or they enter protection state and hang.</div><div class='ctx'> 			 */</div><div class='ctx'> 			msleep(60);</div><div class='del'>-		} else if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_EDP) {</div><div class='del'>-			if (!link-&gt;dc-&gt;config.edp_no_power_sequencing) {</div><div class='del'>-				/*</div><div class='del'>-				 * Sometimes, DP receiver chip power-controlled externally by an</div><div class='del'>-				 * Embedded Controller could be treated and used as eDP,</div><div class='del'>-				 * if it drives mobile display. In this case,</div><div class='del'>-				 * we shouldn't be doing power-sequencing, hence we can skip</div><div class='del'>-				 * waiting for T9-ready.</div><div class='del'>-				 */</div><div class='del'>-				link-&gt;dc-&gt;link_srv-&gt;edp_receiver_ready_T9(link);</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+	    !link-&gt;dc-&gt;config.edp_no_power_sequencing) {</div><div class='add'>+			/*</div><div class='add'>+			 * Sometimes, DP receiver chip power-controlled externally by an</div><div class='add'>+			 * Embedded Controller could be treated and used as eDP,</div><div class='add'>+			 * if it drives mobile display. In this case,</div><div class='add'>+			 * we shouldn't be doing power-sequencing, hence we can skip</div><div class='add'>+			 * waiting for T9-ready.</div><div class='add'>+			 */</div><div class='add'>+		link-&gt;dc-&gt;link_srv-&gt;edp_receiver_ready_T9(link);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -1271,7 +1295,7 @@ void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;set_avmute(pipe_ctx-&gt;stream_res.stream_enc, enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)</div><div class='add'>+enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)</div><div class='ctx'> {</div><div class='ctx'> 	switch (crtc_id) {</div><div class='ctx'> 	case CONTROLLER_ID_D0:</div><div class='hunk'>@@ -1291,7 +1315,7 @@ static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void populate_audio_dp_link_info(</div><div class='add'>+void populate_audio_dp_link_info(</div><div class='ctx'> 	const struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct audio_dp_link_info *dp_link_info)</div><div class='ctx'> {</div><div class='hunk'>@@ -1322,16 +1346,68 @@ static void populate_audio_dp_link_info(</div><div class='ctx'> </div><div class='ctx'> 	dp_link_info-&gt;link_bandwidth_kbps = dc_fixpt_floor(link_bw_kbps);</div><div class='ctx'> </div><div class='del'>-	/* HW minimum for 128b/132b HBlank is 4 frame symbols.</div><div class='del'>-	 * TODO: Plumb the actual programmed HBlank min symbol width to here.</div><div class='add'>+	/* Calculates hblank_min_symbol_width for 128b/132b</div><div class='add'>+	 * Corresponding HBLANK_MIN_SYMBOL_WIDTH register is calculated as:</div><div class='add'>+	 *   floor(h_blank * bits_per_pixel / 128)</div><div class='ctx'> 	 */</div><div class='del'>-	if (dp_link_info-&gt;encoding == DP_128b_132b_ENCODING)</div><div class='del'>-		dp_link_info-&gt;hblank_min_symbol_width = 4;</div><div class='del'>-	else</div><div class='add'>+	if (dp_link_info-&gt;encoding == DP_128b_132b_ENCODING) {</div><div class='add'>+		struct dc_crtc_timing *crtc_timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+</div><div class='add'>+		uint32_t h_active = crtc_timing-&gt;h_addressable + crtc_timing-&gt;h_border_left</div><div class='add'>+				+ crtc_timing-&gt;h_border_right;</div><div class='add'>+		uint32_t h_blank = crtc_timing-&gt;h_total - h_active;</div><div class='add'>+</div><div class='add'>+		uint32_t bpp;</div><div class='add'>+</div><div class='add'>+		if (crtc_timing-&gt;flags.DSC) {</div><div class='add'>+			bpp = crtc_timing-&gt;dsc_cfg.bits_per_pixel;</div><div class='add'>+		} else {</div><div class='add'>+			/* When the timing is using DSC, dsc_cfg.bits_per_pixel is in 16th bits.</div><div class='add'>+			 * The bpp in this path is scaled to 16th bits so the final calculation</div><div class='add'>+			 * is correct for both cases.</div><div class='add'>+			 */</div><div class='add'>+			bpp = 16;</div><div class='add'>+			switch (crtc_timing-&gt;display_color_depth) {</div><div class='add'>+			case COLOR_DEPTH_666:</div><div class='add'>+				bpp *= 18;</div><div class='add'>+				break;</div><div class='add'>+			case COLOR_DEPTH_888:</div><div class='add'>+				bpp *= 24;</div><div class='add'>+				break;</div><div class='add'>+			case COLOR_DEPTH_101010:</div><div class='add'>+				bpp *= 30;</div><div class='add'>+				break;</div><div class='add'>+			case COLOR_DEPTH_121212:</div><div class='add'>+				bpp *= 36;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				bpp = 0;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			switch (crtc_timing-&gt;pixel_encoding) {</div><div class='add'>+			case PIXEL_ENCODING_YCBCR422:</div><div class='add'>+				bpp = bpp * 2 / 3;</div><div class='add'>+				break;</div><div class='add'>+			case PIXEL_ENCODING_YCBCR420:</div><div class='add'>+				bpp /= 2;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Min symbol width = floor(h_blank * (bpp/16) / 128) */</div><div class='add'>+		dp_link_info-&gt;hblank_min_symbol_width = dc_fixpt_floor(</div><div class='add'>+				dc_fixpt_div(dc_fixpt_from_int(h_blank * bpp),</div><div class='add'>+						dc_fixpt_from_int(128 / 16)));</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='ctx'> 		dp_link_info-&gt;hblank_min_symbol_width = 0;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void build_audio_output(</div><div class='add'>+void build_audio_output(</div><div class='ctx'> 	struct dc_state *state,</div><div class='ctx'> 	const struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct audio_output *audio_output)</div><div class='hunk'>@@ -1514,6 +1590,7 @@ static enum dc_status dce110_enable_stream_timing(</div><div class='ctx'> 				0,</div><div class='ctx'> 				0,</div><div class='ctx'> 				0,</div><div class='add'>+				0,</div><div class='ctx'> 				pipe_ctx-&gt;stream-&gt;signal,</div><div class='ctx'> 				true);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1529,6 +1606,51 @@ static enum dc_status dce110_enable_stream_timing(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void</div><div class='add'>+dce110_select_crtc_source(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+	struct dc_bios *bios = link-&gt;ctx-&gt;dc_bios;</div><div class='add'>+	struct bp_crtc_source_select crtc_source_select = {0};</div><div class='add'>+	enum engine_id engine_id = link-&gt;link_enc-&gt;preferred_engine;</div><div class='add'>+	uint8_t bit_depth;</div><div class='add'>+</div><div class='add'>+	if (dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		engine_id = link-&gt;link_enc-&gt;analog_engine;</div><div class='add'>+</div><div class='add'>+	switch (pipe_ctx-&gt;stream-&gt;timing.display_color_depth) {</div><div class='add'>+	case COLOR_DEPTH_UNDEFINED:</div><div class='add'>+		bit_depth = 0;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_666:</div><div class='add'>+		bit_depth = 6;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+	case COLOR_DEPTH_888:</div><div class='add'>+		bit_depth = 8;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_101010:</div><div class='add'>+		bit_depth = 10;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_121212:</div><div class='add'>+		bit_depth = 12;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_141414:</div><div class='add'>+		bit_depth = 14;</div><div class='add'>+		break;</div><div class='add'>+	case COLOR_DEPTH_161616:</div><div class='add'>+		bit_depth = 16;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+	crtc_source_select.bit_depth = bit_depth;</div><div class='add'>+	crtc_source_select.engine_id = engine_id;</div><div class='add'>+	crtc_source_select.sink_signal = pipe_ctx-&gt;stream-&gt;signal;</div><div class='add'>+</div><div class='add'>+	bios-&gt;funcs-&gt;select_crtc_source(bios, &amp;crtc_source_select);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum dc_status dce110_apply_single_controller_ctx_to_hw(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct dc_state *context,</div><div class='hunk'>@@ -1548,8 +1670,12 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(</div><div class='ctx'> 		hws-&gt;funcs.disable_stream_gating(dc, pipe_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_RGB) {</div><div class='add'>+		dce110_select_crtc_source(pipe_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.audio != NULL) {</div><div class='del'>-		struct audio_output audio_output;</div><div class='add'>+		struct audio_output audio_output = {0};</div><div class='ctx'> </div><div class='ctx'> 		build_audio_output(context, pipe_ctx, &amp;audio_output);</div><div class='ctx'> </div><div class='hunk'>@@ -1562,6 +1688,11 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(</div><div class='ctx'> 				&amp;audio_output.crtc_info,</div><div class='ctx'> 				&amp;pipe_ctx-&gt;stream-&gt;audio_info,</div><div class='ctx'> 				&amp;audio_output.dp_link_info);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;config.disable_hbr_audio_dp2)</div><div class='add'>+			if (pipe_ctx-&gt;stream_res.audio-&gt;funcs-&gt;az_disable_hbr_audio &amp;&amp;</div><div class='add'>+					dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx))</div><div class='add'>+				pipe_ctx-&gt;stream_res.audio-&gt;funcs-&gt;az_disable_hbr_audio(pipe_ctx-&gt;stream_res.audio);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* make sure no pipes syncd to the pipe being enabled */</div><div class='hunk'>@@ -1609,9 +1740,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(</div><div class='ctx'> </div><div class='ctx'> 	params.vertical_total_min = stream-&gt;adjust.v_total_min;</div><div class='ctx'> 	params.vertical_total_max = stream-&gt;adjust.v_total_max;</div><div class='del'>-	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg, &amp;params);</div><div class='add'>+	set_drr_and_clear_adjust_pending(pipe_ctx, stream, &amp;params);</div><div class='ctx'> </div><div class='ctx'> 	// DRR should set trigger event to monitor surface update event</div><div class='ctx'> 	if (stream-&gt;adjust.v_total_min != 0 &amp;&amp; stream-&gt;adjust.v_total_max != 0)</div><div class='hunk'>@@ -1624,7 +1753,8 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, event_triggers, 2);</div><div class='ctx'> </div><div class='del'>-	if (!dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+	if (!dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp;</div><div class='add'>+		!dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dig_connect_to_otg(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.stream_enc,</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='hunk'>@@ -1632,6 +1762,19 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(</div><div class='ctx'> 	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 		dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);</div><div class='ctx'> </div><div class='add'>+	/* Temporary workaround to perform DSC programming ahead of stream enablement</div><div class='add'>+	 * for smartmux/SPRS</div><div class='add'>+	 * TODO: Remove SmartMux/SPRS checks once movement of DSC programming is generalized</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;timing.flags.DSC) {</div><div class='add'>+		if ((pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+			((link-&gt;dc-&gt;config.smart_mux_version &amp;&amp; link-&gt;dc-&gt;is_switch_in_progress_dest)</div><div class='add'>+			|| link-&gt;is_dds || link-&gt;skip_implict_edp_power_control)) &amp;&amp;</div><div class='add'>+			(dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal) ||</div><div class='add'>+			dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal)))</div><div class='add'>+			dc-&gt;link_srv-&gt;set_dsc_enable(pipe_ctx, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!stream-&gt;dpms_off)</div><div class='ctx'> 		dc-&gt;link_srv-&gt;set_dpms_on(context, pipe_ctx);</div><div class='ctx'> </div><div class='hunk'>@@ -1780,6 +1923,48 @@ static void get_edp_links_with_sink(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void clean_up_dsc_blocks(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = NULL;</div><div class='add'>+	struct timing_generator *tg = NULL;</div><div class='add'>+	struct stream_encoder *se = NULL;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;caps.is_apu ||</div><div class='add'>+		dc-&gt;ctx-&gt;dce_version &lt; DCN_VERSION_3_15)</div><div class='add'>+		return;</div><div class='add'>+	/*VBIOS supports dsc starts from dcn315*/</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++) {</div><div class='add'>+		struct dcn_dsc_state s  = {0};</div><div class='add'>+</div><div class='add'>+		dsc = dc-&gt;res_pool-&gt;dscs[i];</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;s);</div><div class='add'>+		if (s.dsc_fw_en) {</div><div class='add'>+			/* disable DSC in OPTC */</div><div class='add'>+			if (i &lt; dc-&gt;res_pool-&gt;timing_generator_count) {</div><div class='add'>+				tg = dc-&gt;res_pool-&gt;timing_generators[i];</div><div class='add'>+				tg-&gt;funcs-&gt;set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);</div><div class='add'>+			}</div><div class='add'>+			/* disable DSC in stream encoder */</div><div class='add'>+			if (i &lt; dc-&gt;res_pool-&gt;stream_enc_count) {</div><div class='add'>+				se = dc-&gt;res_pool-&gt;stream_enc[i];</div><div class='add'>+				se-&gt;funcs-&gt;dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);</div><div class='add'>+				se-&gt;funcs-&gt;dp_set_dsc_pps_info_packet(se, false, NULL, true);</div><div class='add'>+			}</div><div class='add'>+			/* disable DSC block */</div><div class='add'>+			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, dsc-&gt;inst);</div><div class='add'>+			dsc-&gt;funcs-&gt;dsc_disable(dsc);</div><div class='add'>+</div><div class='add'>+			/* power down DSC */</div><div class='add'>+			if (pg_cntl != NULL)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, dsc-&gt;inst, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:</div><div class='ctx'>  *  1. Power down all DC HW blocks</div><div class='hunk'>@@ -1794,6 +1979,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	struct dc_stream_state *edp_streams[MAX_NUM_EDP];</div><div class='ctx'> 	struct dc_link *edp_link_with_sink = NULL;</div><div class='ctx'> 	struct dc_link *edp_link = NULL;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = NULL;</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	int edp_with_sink_num;</div><div class='ctx'> 	int edp_num;</div><div class='hunk'>@@ -1802,6 +1988,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	bool can_apply_edp_fast_boot = false;</div><div class='ctx'> 	bool can_apply_seamless_boot = false;</div><div class='ctx'> 	bool keep_edp_vdd_on = false;</div><div class='add'>+	bool should_clean_dsc_block = true;</div><div class='add'>+	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	DC_LOGGER_INIT();</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -1813,10 +2001,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)</div><div class='ctx'> </div><div class='ctx'> 	get_edp_streams(context, edp_streams, &amp;edp_stream_num);</div><div class='ctx'> </div><div class='del'>-	// Check fastboot support, disable on DCE8 because of blank screens</div><div class='del'>-	if (edp_num &amp;&amp; edp_stream_num &amp;&amp; dc-&gt;ctx-&gt;dce_version != DCE_VERSION_8_0 &amp;&amp;</div><div class='del'>-		    dc-&gt;ctx-&gt;dce_version != DCE_VERSION_8_1 &amp;&amp;</div><div class='del'>-		    dc-&gt;ctx-&gt;dce_version != DCE_VERSION_8_3) {</div><div class='add'>+	/* Check fastboot support, disable on DCE 6-8 because of blank screens */</div><div class='add'>+	if (edp_num &amp;&amp; edp_stream_num &amp;&amp; dc-&gt;ctx-&gt;dce_version &lt; DCE_VERSION_10_0) {</div><div class='ctx'> 		for (i = 0; i &lt; edp_num; i++) {</div><div class='ctx'> 			edp_link = edp_links[i];</div><div class='ctx'> 			if (edp_link != edp_streams[0]-&gt;link)</div><div class='hunk'>@@ -1829,10 +2015,34 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)</div><div class='ctx'> </div><div class='ctx'> 				can_apply_edp_fast_boot = dc_validate_boot_timing(dc,</div><div class='ctx'> 					edp_stream-&gt;sink, &amp;edp_stream-&gt;timing);</div><div class='del'>-				edp_stream-&gt;apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;</div><div class='del'>-				if (can_apply_edp_fast_boot)</div><div class='del'>-					DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");</div><div class='ctx'> </div><div class='add'>+				// For Mux-platform, the default value is false.</div><div class='add'>+				// Disable fast boot during mux switching.</div><div class='add'>+				// The flag would be clean after switching done.</div><div class='add'>+				if (dc-&gt;is_switch_in_progress_dest &amp;&amp; edp_link-&gt;is_dds)</div><div class='add'>+					can_apply_edp_fast_boot = false;</div><div class='add'>+</div><div class='add'>+				edp_stream-&gt;apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;</div><div class='add'>+				if (can_apply_edp_fast_boot) {</div><div class='add'>+					DC_LOG_EVENT_LINK_TRAINING("eDP fast boot Enable\n");</div><div class='add'>+</div><div class='add'>+					// Vbios &amp; Driver support different pixel rate div policy.</div><div class='add'>+					pipe_ctx = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, edp_stream);</div><div class='add'>+					if (pipe_ctx &amp;&amp;</div><div class='add'>+						hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy &amp;&amp;</div><div class='add'>+						hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {</div><div class='add'>+						// Get Vbios div factor from register</div><div class='add'>+						dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;get_pixel_rate_div(</div><div class='add'>+							dc-&gt;res_pool-&gt;dccg,</div><div class='add'>+							pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='add'>+							&amp;pipe_ctx-&gt;pixel_rate_divider.div_factor1,</div><div class='add'>+							&amp;pipe_ctx-&gt;pixel_rate_divider.div_factor2);</div><div class='add'>+</div><div class='add'>+						// VBios doesn't support pixel rate div, so force it.</div><div class='add'>+						// If VBios supports it, we check it from reigster or other flags.</div><div class='add'>+						pipe_ctx-&gt;stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1855,19 +2065,38 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	if (edp_with_sink_num)</div><div class='ctx'> 		edp_link_with_sink = edp_links_with_sink[0];</div><div class='ctx'> </div><div class='add'>+	// During a mux switch, powering down the HW blocks and then enabling</div><div class='add'>+	// the link via a DPCD SET_POWER write causes a brief flash</div><div class='add'>+	keep_edp_vdd_on |= dc-&gt;is_switch_in_progress_dest;</div><div class='add'>+</div><div class='ctx'> 	if (!can_apply_edp_fast_boot &amp;&amp; !can_apply_seamless_boot) {</div><div class='ctx'> 		if (edp_link_with_sink &amp;&amp; !keep_edp_vdd_on) {</div><div class='ctx'> 			/*turn off backlight before DP_blank and encoder powered down*/</div><div class='ctx'> 			hws-&gt;funcs.edp_backlight_control(edp_link_with_sink, false);</div><div class='ctx'> 		}</div><div class='ctx'> 		/*resume from S3, no vbios posting, no need to power down again*/</div><div class='del'>-		clk_mgr_exit_optimized_pwr_state(dc, dc-&gt;clk_mgr);</div><div class='add'>+		if (dcb &amp;&amp; dcb-&gt;funcs &amp;&amp; !dcb-&gt;funcs-&gt;is_accelerated_mode(dcb))</div><div class='add'>+			clk_mgr_exit_optimized_pwr_state(dc, dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 		power_down_all_hw_blocks(dc);</div><div class='add'>+</div><div class='add'>+		/* DSC could be enabled on eDP during VBIOS post.</div><div class='add'>+		 * To clean up dsc blocks if all eDP dpms_off is true.</div><div class='add'>+		 */</div><div class='add'>+		for (i = 0; i &lt; edp_stream_num; i++) {</div><div class='add'>+			if (!edp_streams[i]-&gt;dpms_off) {</div><div class='add'>+				should_clean_dsc_block = false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (should_clean_dsc_block)</div><div class='add'>+			clean_up_dsc_blocks(dc);</div><div class='add'>+</div><div class='ctx'> 		disable_vga_and_power_gate_all_controllers(dc);</div><div class='ctx'> 		if (edp_link_with_sink &amp;&amp; !keep_edp_vdd_on)</div><div class='ctx'> 			dc-&gt;hwss.edp_power_control(edp_link_with_sink, false);</div><div class='del'>-		clk_mgr_optimize_pwr_state(dc, dc-&gt;clk_mgr);</div><div class='add'>+		if (dcb &amp;&amp; dcb-&gt;funcs &amp;&amp; !dcb-&gt;funcs-&gt;is_accelerated_mode(dcb))</div><div class='add'>+			clk_mgr_optimize_pwr_state(dc, dc-&gt;clk_mgr);</div><div class='ctx'> 	}</div><div class='ctx'> 	bios_set_scratch_acc_mode_change(dc-&gt;ctx-&gt;dc_bios, 1);</div><div class='ctx'> }</div><div class='hunk'>@@ -1982,13 +2211,19 @@ static void set_drr(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 	 * as well.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; num_pipes; i++) {</div><div class='del'>-		pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-			pipe_ctx[i]-&gt;stream_res.tg, &amp;params);</div><div class='del'>-</div><div class='del'>-		if (adjust.v_total_max != 0 &amp;&amp; adjust.v_total_min != 0)</div><div class='del'>-			pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='del'>-					pipe_ctx[i]-&gt;stream_res.tg,</div><div class='del'>-					event_triggers, num_frames);</div><div class='add'>+		/* dc_state_destruct() might null the stream resources, so fetch tg</div><div class='add'>+		 * here first to avoid a race condition. The lifetime of the pointee</div><div class='add'>+		 * itself (the timing_generator object) is not a problem here.</div><div class='add'>+		 */</div><div class='add'>+		struct timing_generator *tg = pipe_ctx[i]-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+		if ((tg != NULL) &amp;&amp; tg-&gt;funcs) {</div><div class='add'>+			set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]-&gt;stream, &amp;params);</div><div class='add'>+			if (adjust.v_total_max != 0 &amp;&amp; adjust.v_total_min != 0)</div><div class='add'>+				if (tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='add'>+					tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='add'>+						tg, event_triggers, num_frames);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2100,7 +2335,7 @@ static bool should_enable_fbc(struct dc *dc,</div><div class='ctx'> /*</div><div class='ctx'>  *  Enable FBC</div><div class='ctx'>  */</div><div class='del'>-static void enable_fbc(</div><div class='add'>+void enable_fbc(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context)</div><div class='ctx'> {</div><div class='hunk'>@@ -2200,7 +2435,7 @@ static void dce110_setup_audio_dto(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	/* program audio wall clock. use HDMI as clock source if HDMI</div><div class='ctx'> 	 * audio active. Otherwise, use DP as clock source</div><div class='hunk'>@@ -2272,7 +2507,7 @@ static void dce110_setup_audio_dto(</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			if (pipe_ctx-&gt;stream_res.audio != NULL) {</div><div class='del'>-				struct audio_output audio_output;</div><div class='add'>+				struct audio_output audio_output = {0};</div><div class='ctx'> </div><div class='ctx'> 				build_audio_output(context, pipe_ctx, &amp;audio_output);</div><div class='ctx'> </div><div class='hunk'>@@ -2295,6 +2530,8 @@ enum dc_status dce110_apply_ctx_to_hw(</div><div class='ctx'> 	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	enum dc_status status;</div><div class='ctx'> 	int i;</div><div class='add'>+	bool was_hpo_acquired = resource_is_hpo_acquired(dc-&gt;current_state);</div><div class='add'>+	bool is_hpo_acquired = resource_is_hpo_acquired(context);</div><div class='ctx'> </div><div class='ctx'> 	/* reset syncd pipes from disabled pipes */</div><div class='ctx'> 	if (dc-&gt;config.use_pipe_ctx_sync_logic)</div><div class='hunk'>@@ -2337,6 +2574,10 @@ enum dc_status dce110_apply_ctx_to_hw(</div><div class='ctx'> </div><div class='ctx'> 	dce110_setup_audio_dto(dc, context);</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;hwseq-&gt;funcs.setup_hpo_hw_control &amp;&amp; was_hpo_acquired != is_hpo_acquired) {</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.setup_hpo_hw_control(dc-&gt;hwseq, is_hpo_acquired);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx_old =</div><div class='ctx'> 					&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -2366,7 +2607,7 @@ enum dc_status dce110_apply_ctx_to_hw(</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> 		if (hws-&gt;funcs.resync_fifo_dccg_dio)</div><div class='del'>-			hws-&gt;funcs.resync_fifo_dccg_dio(hws, dc, context);</div><div class='add'>+			hws-&gt;funcs.resync_fifo_dccg_dio(hws, dc, context, i);</div><div class='ctx'> #endif</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2633,12 +2874,12 @@ static void dce110_enable_per_frame_crtc_position_reset(</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void init_pipes(struct dc *dc, struct dc_state *context)</div><div class='add'>+static void dce110_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	// Do nothing</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void init_hw(struct dc *dc)</div><div class='add'>+static void dce110_init_hw(struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct dc_bios *bp;</div><div class='hunk'>@@ -3015,9 +3256,10 @@ static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp)</div><div class='add'>+	struct set_backlight_level_params *backlight_level_params)</div><div class='ctx'> {</div><div class='add'>+	uint32_t backlight_pwm_u16_16 = backlight_level_params-&gt;backlight_pwm_u16_16;</div><div class='add'>+	uint32_t frame_ramp = backlight_level_params-&gt;frame_ramp;</div><div class='ctx'> 	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='ctx'> 	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct abm *abm = pipe_ctx-&gt;stream_res.abm;</div><div class='hunk'>@@ -3188,7 +3430,7 @@ void dce110_disable_link_output(struct dc_link *link,</div><div class='ctx'> 	 * from enable/disable link output and only call edp panel control</div><div class='ctx'> 	 * in enable_link_dp and disable_link_dp once.</div><div class='ctx'> 	 */</div><div class='del'>-	if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;lock_phy)</div><div class='add'>+	if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;unlock_phy)</div><div class='ctx'> 		dmcu-&gt;funcs-&gt;unlock_phy(dmcu);</div><div class='ctx'> 	dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);</div><div class='ctx'> }</div><div class='hunk'>@@ -3196,12 +3438,13 @@ void dce110_disable_link_output(struct dc_link *link,</div><div class='ctx'> static const struct hw_sequencer_funcs dce110_funcs = {</div><div class='ctx'> 	.program_gamut_remap = program_gamut_remap,</div><div class='ctx'> 	.program_output_csc = program_output_csc,</div><div class='del'>-	.init_hw = init_hw,</div><div class='add'>+	.init_hw = dce110_init_hw,</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,</div><div class='ctx'> 	.post_unlock_program_front_end = dce110_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = update_plane_addr,</div><div class='ctx'> 	.update_pending_status = dce110_update_pending_status,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.enable_accelerated_mode = dce110_enable_accelerated_mode,</div><div class='ctx'> 	.enable_timing_synchronization = dce110_enable_timing_synchronization,</div><div class='ctx'> 	.enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,</div><div class='hunk'>@@ -3239,8 +3482,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dce110_private_funcs = {</div><div class='del'>-	.init_pipes = init_pipes,</div><div class='del'>-	.update_plane_addr = update_plane_addr,</div><div class='add'>+	.init_pipes = dce110_init_pipes,</div><div class='ctx'> 	.set_input_transfer_func = dce110_set_input_transfer_func,</div><div class='ctx'> 	.set_output_transfer_func = dce110_set_output_transfer_func,</div><div class='ctx'> 	.power_down = dce110_power_down,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h<br/>index ed3cc3648e8e..9c032e449481 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h</a></div><div class='hunk'>@@ -88,8 +88,7 @@ void dce110_edp_wait_for_hpd_ready(</div><div class='ctx'> 		bool power_up);</div><div class='ctx'> </div><div class='ctx'> bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp);</div><div class='add'>+	struct set_backlight_level_params *params);</div><div class='ctx'> void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dce110_set_pipe(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dce110_disable_link_output(struct dc_link *link,</div><div class='hunk'>@@ -111,5 +110,16 @@ void dce110_enable_dp_link_output(</div><div class='ctx'> 		enum signal_type signal,</div><div class='ctx'> 		enum clock_source_id clock_source,</div><div class='ctx'> 		const struct dc_link_settings *link_settings);</div><div class='add'>+void build_audio_output(</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		const struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct audio_output *audio_output);</div><div class='add'>+enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id);</div><div class='add'>+void populate_audio_dp_link_info(</div><div class='add'>+	const struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct audio_dp_link_info *dp_link_info);</div><div class='add'>+void enable_fbc(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_state *context);</div><div class='ctx'> #endif /* __DC_HWSS_DCE110_H__ */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c<br/>index 22ee304ef9cf..2a62f63d0357 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "dce120_hwseq.h"</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='ctx'> </div><div class='add'>+#include "dce100/dce100_hwseq.h"</div><div class='ctx'> #include "dce110/dce110_hwseq.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce/dce_12_0_offset.h"</div><div class='hunk'>@@ -264,5 +265,6 @@ void dce120_hw_sequencer_construct(struct dc *dc)</div><div class='ctx'> 	dce110_hw_sequencer_construct(dc);</div><div class='ctx'> 	dc-&gt;hwseq-&gt;funcs.enable_display_power_gating = dce120_enable_display_power_gating;</div><div class='ctx'> 	dc-&gt;hwss.update_dchub = dce120_update_dchub;</div><div class='add'>+	dc-&gt;hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c<br/>index 1fdeef47e4dc..a08e9f9eec17 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "core_types.h"</div><div class='del'>-#include "dce60_hw_sequencer.h"</div><div class='add'>+#include "dce60_hwseq.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='ctx'> #include "dce110/dce110_hwseq.h"</div><div class='hunk'>@@ -428,5 +428,6 @@ void dce60_hw_sequencer_construct(struct dc *dc)</div><div class='ctx'> 	dc-&gt;hwss.pipe_control_lock = dce60_pipe_control_lock;</div><div class='ctx'> 	dc-&gt;hwss.prepare_bandwidth = dce100_prepare_bandwidth;</div><div class='ctx'> 	dc-&gt;hwss.optimize_bandwidth = dce100_optimize_bandwidth;</div><div class='add'>+	dc-&gt;hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h<br/>index f3b2d8b60d5b..f3b2d8b60d5b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c<br/>index 0a054e880801..76fd45550c5e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c</a></div><div class='hunk'>@@ -50,5 +50,6 @@ void dce80_hw_sequencer_construct(struct dc *dc)</div><div class='ctx'> 	dc-&gt;hwss.pipe_control_lock = dce_pipe_control_lock;</div><div class='ctx'> 	dc-&gt;hwss.prepare_bandwidth = dce100_prepare_bandwidth;</div><div class='ctx'> 	dc-&gt;hwss.optimize_bandwidth = dce100_optimize_bandwidth;</div><div class='add'>+	dc-&gt;hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c<br/>index 314798400b16..fa62e40a9858 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c</a></div><div class='hunk'>@@ -55,7 +55,7 @@</div><div class='ctx'> #include "dce/dmub_hw_lock_mgr.h"</div><div class='ctx'> #include "dc_trace.h"</div><div class='ctx'> #include "dce/dmub_outbox.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='hunk'>@@ -94,6 +94,128 @@ static void print_microsec(struct dc_context *dc_ctx,</div><div class='ctx'> 			us_x10 % frac);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Delay until we passed busy-until-point to which we can</div><div class='add'>+ * do necessary locking/programming on consecutive full updates</div><div class='add'>+ */</div><div class='add'>+void dcn10_wait_for_pipe_update_if_needed(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only)</div><div class='add'>+{</div><div class='add'>+	struct crtc_position position;</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	unsigned int vpos, frame_count;</div><div class='add'>+	uint32_t vupdate_start, vupdate_end, vblank_start;</div><div class='add'>+	unsigned int lines_to_vupdate, us_to_vupdate;</div><div class='add'>+	unsigned int us_per_line, us_vupdate;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;stream ||</div><div class='add'>+		!pipe_ctx-&gt;stream_res.tg ||</div><div class='add'>+		!pipe_ctx-&gt;stream_res.stream_enc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;prev_odm_pipe &amp;&amp;</div><div class='add'>+				pipe_ctx-&gt;stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;wait_is_required)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;is_tg_enabled &amp;&amp; !tg-&gt;funcs-&gt;is_tg_enabled(tg))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dc-&gt;hwss.calc_vupdate_position(dc, pipe_ctx, &amp;vupdate_start,</div><div class='add'>+						&amp;vupdate_end);</div><div class='add'>+</div><div class='add'>+	dc-&gt;hwss.get_position(&amp;pipe_ctx, 1, &amp;position);</div><div class='add'>+	vpos = position.vertical_count;</div><div class='add'>+</div><div class='add'>+	frame_count = tg-&gt;funcs-&gt;get_frame_count(tg);</div><div class='add'>+</div><div class='add'>+	if (frame_count - pipe_ctx-&gt;wait_frame_count &gt; 2)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	vblank_start = pipe_ctx-&gt;pipe_dlg_param.vblank_start;</div><div class='add'>+</div><div class='add'>+	if (vpos &gt;= vupdate_start &amp;&amp; vupdate_start &gt;= vblank_start)</div><div class='add'>+		lines_to_vupdate = stream-&gt;timing.v_total - vpos + vupdate_start;</div><div class='add'>+	else</div><div class='add'>+		lines_to_vupdate = vupdate_start - vpos;</div><div class='add'>+</div><div class='add'>+	us_per_line =</div><div class='add'>+		stream-&gt;timing.h_total * 10000u / stream-&gt;timing.pix_clk_100hz;</div><div class='add'>+	us_to_vupdate = lines_to_vupdate * us_per_line;</div><div class='add'>+</div><div class='add'>+	if (vupdate_end &lt; vupdate_start)</div><div class='add'>+		vupdate_end += stream-&gt;timing.v_total;</div><div class='add'>+</div><div class='add'>+	if (lines_to_vupdate &gt; stream-&gt;timing.v_total - vupdate_end + vupdate_start)</div><div class='add'>+		us_to_vupdate = 0;</div><div class='add'>+</div><div class='add'>+	us_vupdate = (vupdate_end - vupdate_start + 1) * us_per_line;</div><div class='add'>+</div><div class='add'>+	if (is_surface_update_only &amp;&amp; us_to_vupdate + us_vupdate &gt; 200) {</div><div class='add'>+		//surface updates come in at high irql</div><div class='add'>+		pipe_ctx-&gt;wait_is_required = true;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fsleep(us_to_vupdate + us_vupdate);</div><div class='add'>+</div><div class='add'>+	//clear</div><div class='add'>+	pipe_ctx-&gt;next_vupdate = 0;</div><div class='add'>+	pipe_ctx-&gt;wait_frame_count = 0;</div><div class='add'>+	pipe_ctx-&gt;wait_is_required = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * On pipe unlock and programming, indicate pipe will be busy</div><div class='add'>+ * until some frame and line (vupdate), this is required for consecutive</div><div class='add'>+ * full updates, need to wait for updates</div><div class='add'>+ * to latch to try and program the next update</div><div class='add'>+ */</div><div class='add'>+void dcn10_set_wait_for_update_needed_for_pipe(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	uint32_t vupdate_start, vupdate_end;</div><div class='add'>+	struct crtc_position position;</div><div class='add'>+	unsigned int vpos, cur_frame;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;stream ||</div><div class='add'>+		!pipe_ctx-&gt;stream_res.tg ||</div><div class='add'>+		!pipe_ctx-&gt;stream_res.stream_enc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dc-&gt;hwss.get_position(&amp;pipe_ctx, 1, &amp;position);</div><div class='add'>+	vpos = position.vertical_count;</div><div class='add'>+</div><div class='add'>+	dc-&gt;hwss.calc_vupdate_position(dc, pipe_ctx, &amp;vupdate_start,</div><div class='add'>+						&amp;vupdate_end);</div><div class='add'>+</div><div class='add'>+	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(tg);</div><div class='add'>+</div><div class='add'>+	ASSERT(optc1-&gt;max_frame_count != 0);</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;is_tg_enabled &amp;&amp; !tg-&gt;funcs-&gt;is_tg_enabled(tg))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;next_vupdate = vupdate_start;</div><div class='add'>+</div><div class='add'>+	cur_frame = tg-&gt;funcs-&gt;get_frame_count(tg);</div><div class='add'>+</div><div class='add'>+	if (vpos &lt; vupdate_start) {</div><div class='add'>+		pipe_ctx-&gt;wait_frame_count = cur_frame;</div><div class='add'>+	} else {</div><div class='add'>+		if (cur_frame + 1 &gt; optc1-&gt;max_frame_count)</div><div class='add'>+			pipe_ctx-&gt;wait_frame_count = cur_frame + 1 - optc1-&gt;max_frame_count;</div><div class='add'>+		else</div><div class='add'>+			pipe_ctx-&gt;wait_frame_count = cur_frame + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;wait_is_required = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn10_lock_all_pipes(struct dc *dc,</div><div class='ctx'> 	struct dc_state *context,</div><div class='ctx'> 	bool lock)</div><div class='hunk'>@@ -205,6 +327,46 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	DTN_INFO("\n=======HUBP FL======\n");</div><div class='add'>+	static const char * const pLabels[] = {</div><div class='add'>+		"inst", "Enabled ", "Done ", "adr_mode ", "width ", "mpc_width ",</div><div class='add'>+		"tmz", "xbar_sel_R", "xbar_sel_G", "xbar_sel_B", "adr_hi ",</div><div class='add'>+		"adr_low", "REFCYC", "Bias", "Scale", "Mode",</div><div class='add'>+		"Format", "prefetch"};</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct dcn_hubp_state *s = &amp;(TO_DCN10_HUBP(pool-&gt;hubps[i])-&gt;state);</div><div class='add'>+		struct dcn_fl_regs_st *fl_regs = &amp;s-&gt;fl_regs;</div><div class='add'>+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &amp;s-&gt;dlg_attr;</div><div class='add'>+</div><div class='add'>+		if (!s-&gt;blank_en) {</div><div class='add'>+			uint32_t values[] = {</div><div class='add'>+					pool-&gt;hubps[i]-&gt;inst,</div><div class='add'>+					fl_regs-&gt;lut_enable,</div><div class='add'>+					fl_regs-&gt;lut_done,</div><div class='add'>+					fl_regs-&gt;lut_addr_mode,</div><div class='add'>+					fl_regs-&gt;lut_width,</div><div class='add'>+					fl_regs-&gt;lut_mpc_width,</div><div class='add'>+					fl_regs-&gt;lut_tmz,</div><div class='add'>+					fl_regs-&gt;lut_crossbar_sel_r,</div><div class='add'>+					fl_regs-&gt;lut_crossbar_sel_g,</div><div class='add'>+					fl_regs-&gt;lut_crossbar_sel_b,</div><div class='add'>+					fl_regs-&gt;lut_addr_hi,</div><div class='add'>+					fl_regs-&gt;lut_addr_lo,</div><div class='add'>+					fl_regs-&gt;refcyc_3dlut_group,</div><div class='add'>+					fl_regs-&gt;lut_fl_bias,</div><div class='add'>+					fl_regs-&gt;lut_fl_scale,</div><div class='add'>+					fl_regs-&gt;lut_fl_mode,</div><div class='add'>+					fl_regs-&gt;lut_fl_format,</div><div class='add'>+					dlg_regs-&gt;dst_y_prefetch};</div><div class='add'>+</div><div class='add'>+			int num_elements = 18;</div><div class='add'>+</div><div class='add'>+			for (int j = 0; j &lt; num_elements; j++)</div><div class='add'>+				DTN_INFO("%s \t %8xh\n", pLabels[j], values[j]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	DTN_INFO("\n=========RQ========\n");</div><div class='ctx'> 	DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"</div><div class='ctx'> 		"  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"</div><div class='hunk'>@@ -233,7 +395,8 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)</div><div class='ctx'> 			"  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "</div><div class='ctx'> 			"  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "</div><div class='ctx'> 			"  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"</div><div class='del'>-			"  x_rp_dlay  x_rr_sfl\n");</div><div class='add'>+			"  x_rp_dlay  x_rr_sfl  rc_td_grp\n");</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct dcn_hubp_state *s = &amp;(TO_DCN10_HUBP(pool-&gt;hubps[i])-&gt;state);</div><div class='ctx'> 		struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &amp;s-&gt;dlg_attr;</div><div class='hunk'>@@ -241,7 +404,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)</div><div class='ctx'> 		if (!s-&gt;blank_en)</div><div class='ctx'> 			DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"</div><div class='ctx'> 				"  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"</div><div class='del'>-				"  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",</div><div class='add'>+				"  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh %xh\n",</div><div class='ctx'> 				pool-&gt;hubps[i]-&gt;inst, dlg_regs-&gt;refcyc_h_blank_end, dlg_regs-&gt;dlg_vblank_end, dlg_regs-&gt;min_dst_y_next_start,</div><div class='ctx'> 				dlg_regs-&gt;refcyc_per_htotal, dlg_regs-&gt;refcyc_x_after_scaler, dlg_regs-&gt;dst_y_after_scaler,</div><div class='ctx'> 				dlg_regs-&gt;dst_y_prefetch, dlg_regs-&gt;dst_y_per_vm_vblank, dlg_regs-&gt;dst_y_per_row_vblank,</div><div class='hunk'>@@ -259,7 +422,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)</div><div class='ctx'> 				dlg_regs-&gt;refcyc_per_line_delivery_c, dlg_regs-&gt;chunk_hdl_adjust_cur0, dlg_regs-&gt;dst_y_offset_cur1,</div><div class='ctx'> 				dlg_regs-&gt;chunk_hdl_adjust_cur1, dlg_regs-&gt;vready_after_vcount0, dlg_regs-&gt;dst_y_delta_drq_limit,</div><div class='ctx'> 				dlg_regs-&gt;xfc_reg_transfer_delay, dlg_regs-&gt;xfc_reg_precharge_delay,</div><div class='del'>-				dlg_regs-&gt;xfc_reg_remote_surface_flip_latency);</div><div class='add'>+				dlg_regs-&gt;xfc_reg_remote_surface_flip_latency, dlg_regs-&gt;refcyc_per_tdlut_group);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	DTN_INFO("========TTU========\n");</div><div class='hunk'>@@ -288,6 +451,7 @@ static void dcn10_log_color_state(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='add'>+	bool is_gamut_remap_available = false;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	DTN_INFO("DPP:    IGAM format    IGAM mode    DGAM mode    RGAM mode"</div><div class='hunk'>@@ -300,16 +464,15 @@ static void dcn10_log_color_state(struct dc *dc,</div><div class='ctx'> 		struct dcn_dpp_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_read_state(dpp, &amp;s);</div><div class='del'>-		dpp-&gt;funcs-&gt;dpp_get_gamut_remap(dpp, &amp;s.gamut_remap);</div><div class='add'>+		if (dpp-&gt;funcs-&gt;dpp_get_gamut_remap) {</div><div class='add'>+			dpp-&gt;funcs-&gt;dpp_get_gamut_remap(dpp, &amp;s.gamut_remap);</div><div class='add'>+			is_gamut_remap_available = true;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!s.is_enabled)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		DTN_INFO("[%2d]:  %11xh  %11s    %9s    %9s"</div><div class='del'>-			 "  %12s  "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld",</div><div class='add'>+		DTN_INFO("[%2d]:  %11xh  %11s    %9s    %9s",</div><div class='ctx'> 				dpp-&gt;inst,</div><div class='ctx'> 				s.igam_input_format,</div><div class='ctx'> 				(s.igam_lut_mode == 0) ? "BypassFixed" :</div><div class='hunk'>@@ -328,22 +491,27 @@ static void dcn10_log_color_state(struct dc *dc,</div><div class='ctx'> 					((s.rgam_lut_mode == 2) ? "Ycc" :</div><div class='ctx'> 					((s.rgam_lut_mode == 3) ? "RAM" :</div><div class='ctx'> 					((s.rgam_lut_mode == 4) ? "RAM" :</div><div class='del'>-								 "Unknown")))),</div><div class='del'>-				(s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :</div><div class='del'>-					((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :</div><div class='del'>-										  "SW"),</div><div class='del'>-				s.gamut_remap.temperature_matrix[0].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[1].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[2].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[3].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[4].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[5].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[6].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[7].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[8].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[9].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[10].value,</div><div class='del'>-				s.gamut_remap.temperature_matrix[11].value);</div><div class='add'>+								 "Unknown")))));</div><div class='add'>+		if (is_gamut_remap_available)</div><div class='add'>+			DTN_INFO("  %12s  "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld",</div><div class='add'>+				 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :</div><div class='add'>+					((s.gamut_remap.gamut_adjust_type == 1) ? "HW" : "SW"),</div><div class='add'>+				 s.gamut_remap.temperature_matrix[0].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[1].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[2].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[3].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[4].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[5].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[6].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[7].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[8].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[9].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[10].value,</div><div class='add'>+				 s.gamut_remap.temperature_matrix[11].value);</div><div class='add'>+</div><div class='ctx'> 		DTN_INFO("\n");</div><div class='ctx'> 	}</div><div class='ctx'> 	DTN_INFO("\n");</div><div class='hunk'>@@ -367,7 +535,7 @@ static void dcn10_log_color_state(struct dc *dc,</div><div class='ctx'> 		 dc-&gt;caps.color.dpp.ocsc);</div><div class='ctx'> </div><div class='ctx'> 	DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");</div><div class='del'>-	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;mpcc_count; i++) {</div><div class='ctx'> 		struct mpcc_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		pool-&gt;mpc-&gt;funcs-&gt;read_mpcc_state(pool-&gt;mpc, i, &amp;s);</div><div class='hunk'>@@ -383,6 +551,60 @@ static void dcn10_log_color_state(struct dc *dc,</div><div class='ctx'> 		 dc-&gt;caps.color.mpc.num_3dluts,</div><div class='ctx'> 		 dc-&gt;caps.color.mpc.ogam_ram,</div><div class='ctx'> 		 dc-&gt;caps.color.mpc.ocsc);</div><div class='add'>+	DTN_INFO("===== MPC RMCM 3DLUT =====\n");</div><div class='add'>+	static const char * const pLabels[] = {</div><div class='add'>+		"MPCC", "SIZE", "MODE", "MODE_CUR", "RD_SEL",</div><div class='add'>+		"30BIT_EN", "WR_EN_MASK", "RAM_SEL", "OUT_NORM_FACTOR", "FL_SEL",</div><div class='add'>+		"OUT_OFFSET", "OUT_SCALE", "FL_DONE", "SOFT_UNDERFLOW", "HARD_UNDERFLOW",</div><div class='add'>+		"MEM_PWR_ST", "FORCE", "DIS", "MODE"};</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;mpcc_count; i++) {</div><div class='add'>+		struct mpcc_state s = {0};</div><div class='add'>+</div><div class='add'>+		pool-&gt;mpc-&gt;funcs-&gt;read_mpcc_state(pool-&gt;mpc, i, &amp;s);</div><div class='add'>+		if (s.opp_id != 0xf) {</div><div class='add'>+			uint32_t values[] = {</div><div class='add'>+				i,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_size,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_mode,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_mode_cur,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_read_sel,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_30bit_en,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_wr_en_mask,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_ram_sel,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_out_norm_factor,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_fl_sel,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_out_offset_r,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_out_scale_r,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_fl_done,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_fl_soft_underflow,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_fl_hard_underflow,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_mem_pwr_state,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_mem_pwr_force,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_mem_pwr_dis,</div><div class='add'>+				s.rmcm_regs.rmcm_3dlut_mem_pwr_mode};</div><div class='add'>+</div><div class='add'>+			int num_elements = 19;</div><div class='add'>+</div><div class='add'>+			for (int j = 0; j &lt; num_elements; j++)</div><div class='add'>+				DTN_INFO("%s \t %8xh\n", pLabels[j], values[j]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	DTN_INFO("\n");</div><div class='add'>+	DTN_INFO("===== MPC RMCM Shaper =====\n");</div><div class='add'>+	DTN_INFO("MPCC:  CNTL  LUT_MODE  MODE_CUR  WR_EN_MASK  WR_SEL  OFFSET  SCALE  START_B	START_SEG_B	END_B	END_BASE_B	MEM_PWR_ST	FORCE	DIS	MODE\n");</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;mpcc_count; i++) {</div><div class='add'>+		struct mpcc_state s = {0};</div><div class='add'>+</div><div class='add'>+		pool-&gt;mpc-&gt;funcs-&gt;read_mpcc_state(pool-&gt;mpc, i, &amp;s);</div><div class='add'>+		if (s.opp_id != 0xf)</div><div class='add'>+			DTN_INFO("[%2d]:  %4xh  %4xh  %6xh  %4x  %4x  %4x  %4x  %4x %4xh  %4xh  %6xh  %4x  %4x  %4x  %4x\n",</div><div class='add'>+				i, s.rmcm_regs.rmcm_cntl, s.rmcm_regs.rmcm_shaper_lut_mode, s.rmcm_regs.rmcm_shaper_mode_cur,</div><div class='add'>+				s.rmcm_regs.rmcm_shaper_lut_write_en_mask, s.rmcm_regs.rmcm_shaper_lut_write_sel, s.rmcm_regs.rmcm_shaper_offset_b,</div><div class='add'>+				s.rmcm_regs.rmcm_shaper_scale_b, s.rmcm_regs.rmcm_shaper_rama_exp_region_start_b, s.rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b,</div><div class='add'>+				s.rmcm_regs.rmcm_shaper_rama_exp_region_end_b, s.rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b, s.rmcm_regs.rmcm_shaper_mem_pwr_state,</div><div class='add'>+				s.rmcm_regs.rmcm_shaper_mem_pwr_force, s.rmcm_regs.rmcm_shaper_mem_pwr_dis, s.rmcm_regs.rmcm_shaper_mem_pwr_mode);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn10_log_hw_state(struct dc *dc,</div><div class='hunk'>@@ -409,7 +631,8 @@ void dcn10_log_hw_state(struct dc *dc,</div><div class='ctx'> 		struct timing_generator *tg = pool-&gt;timing_generators[i];</div><div class='ctx'> 		struct dcn_otg_state s = {0};</div><div class='ctx'> 		/* Read shared OTG state registers for all DCNx */</div><div class='del'>-		optc1_read_otg_state(DCN10TG_FROM_TG(tg), &amp;s);</div><div class='add'>+		if (tg-&gt;funcs-&gt;read_otg_state)</div><div class='add'>+			tg-&gt;funcs-&gt;read_otg_state(tg, &amp;s);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * For DCN2 and greater, a register on the OPP is used to</div><div class='hunk'>@@ -999,6 +1222,7 @@ enum dc_status dcn10_enable_stream_timing(</div><div class='ctx'> 			pipe_ctx-&gt;pipe_dlg_param.vstartup_start,</div><div class='ctx'> 			pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='ctx'> 			pipe_ctx-&gt;pipe_dlg_param.vupdate_width,</div><div class='add'>+			pipe_ctx-&gt;pipe_dlg_param.pstate_keepout,</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;signal,</div><div class='ctx'> 			true);</div><div class='ctx'> </div><div class='hunk'>@@ -1105,9 +1329,7 @@ static void dcn10_reset_back_end_for_pipe(</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe_ctx-&gt;stream_res.tg);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;enable_optc_clock(pipe_ctx-&gt;stream_res.tg, false);</div><div class='del'>-		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-					pipe_ctx-&gt;stream_res.tg, NULL);</div><div class='add'>+		set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx-&gt;stream, NULL);</div><div class='ctx'> 		if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1128,26 +1350,9 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct hubp *hubp ;</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-	bool need_recover = true;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc-&gt;debug.recovery_enabled)</div><div class='ctx'> 		return false;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe_ctx =</div><div class='del'>-			&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-		if (pipe_ctx != NULL) {</div><div class='del'>-			hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='del'>-			if (hubp != NULL &amp;&amp; hubp-&gt;funcs-&gt;hubp_get_underflow_status) {</div><div class='del'>-				if (hubp-&gt;funcs-&gt;hubp_get_underflow_status(hubp) != 0) {</div><div class='del'>-					/* one pipe underflow, we will reset all the pipes*/</div><div class='del'>-					need_recover = true;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	if (!need_recover)</div><div class='del'>-		return false;</div><div class='ctx'> 	/*</div><div class='ctx'> 	DCHUBP_CNTL:HUBP_BLANK_EN=1</div><div class='ctx'> 	DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1</div><div class='hunk'>@@ -1254,7 +1459,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc,</div><div class='ctx'> 	mpc-&gt;funcs-&gt;remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);</div><div class='ctx'> 	// Phantom pipes have OTG disabled by default, so MPCC_STATUS will never assert idle,</div><div class='ctx'> 	// so don't wait for MPCC_IDLE in the programming sequence</div><div class='del'>-	if (opp != NULL &amp;&amp; dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)</div><div class='ctx'> 		opp-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;optimized_required = true;</div><div class='hunk'>@@ -1296,6 +1501,7 @@ void dcn10_plane_atomic_power_down(struct dc *dc,</div><div class='ctx'> 		if (hws-&gt;funcs.hubp_pg_control)</div><div class='ctx'> 			hws-&gt;funcs.hubp_pg_control(hws, hubp-&gt;inst, false);</div><div class='ctx'> </div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_reset(hubp);</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_reset(dpp);</div><div class='ctx'> </div><div class='ctx'> 		REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='hunk'>@@ -1366,6 +1572,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='ctx'> 	bool can_apply_seamless_boot = false;</div><div class='add'>+	bool tg_enabled[MAX_PIPES] = {false};</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		if (context-&gt;streams[i]-&gt;apply_seamless_boot_optimization) {</div><div class='hunk'>@@ -1412,6 +1619,8 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		if (hubbub &amp;&amp; hubp) {</div><div class='ctx'> 			if (hubbub-&gt;funcs-&gt;program_det_size)</div><div class='ctx'> 				hubbub-&gt;funcs-&gt;program_det_size(hubbub, hubp-&gt;inst, 0);</div><div class='add'>+			if (hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+				hubbub-&gt;funcs-&gt;program_det_segments(hubbub, hubp-&gt;inst, 0);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1447,12 +1656,14 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			// requesting data while in PSR.</div><div class='ctx'> 			tg-&gt;funcs-&gt;tg_init(tg);</div><div class='ctx'> 			hubp-&gt;power_gated = true;</div><div class='add'>+			tg_enabled[i] = true;</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Disable on the current state so the new one isn't cleared. */</div><div class='ctx'> 		pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_reset(hubp);</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_reset(dpp);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg = tg;</div><div class='hunk'>@@ -1488,6 +1699,20 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		tg-&gt;funcs-&gt;tg_init(tg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Clean up MPC tree */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (tg_enabled[i]) {</div><div class='add'>+			if (dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list) {</div><div class='add'>+				if (dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list-&gt;mpcc_bot) {</div><div class='add'>+					int bot_id = dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list-&gt;mpcc_bot-&gt;mpcc_id;</div><div class='add'>+</div><div class='add'>+					if ((bot_id &lt; MAX_MPCC) &amp;&amp; (bot_id &lt; MAX_PIPES) &amp;&amp; (!tg_enabled[bot_id]))</div><div class='add'>+						dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list = NULL;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Power gate DSCs */</div><div class='ctx'> 	if (hws-&gt;funcs.dsc_pg_control != NULL) {</div><div class='ctx'> 		uint32_t num_opps = 0;</div><div class='hunk'>@@ -1547,7 +1772,7 @@ void dcn10_init_hw(struct dc *dc)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	/* Align bw context with hw config when system resume. */</div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;clks.dispclk_khz != 0 &amp;&amp; dc-&gt;clk_mgr-&gt;clks.dppclk_khz != 0) {</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;clks.dispclk_khz != 0 &amp;&amp; dc-&gt;clk_mgr-&gt;clks.dppclk_khz != 0) {</div><div class='ctx'> 		dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk.dispclk_khz = dc-&gt;clk_mgr-&gt;clks.dispclk_khz;</div><div class='ctx'> 		dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk.dppclk_khz = dc-&gt;clk_mgr-&gt;clks.dppclk_khz;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1667,7 +1892,7 @@ void dcn10_init_hw(struct dc *dc)</div><div class='ctx'> 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges(dc-&gt;clk_mgr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1690,10 +1915,10 @@ void dcn10_power_down_on_boot(struct dc *dc)</div><div class='ctx'> 	if (edp_link &amp;&amp; edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 			edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(edp_link-&gt;link_enc) &amp;&amp;</div><div class='ctx'> 			dc-&gt;hwseq-&gt;funcs.edp_backlight_control &amp;&amp;</div><div class='del'>-			dc-&gt;hwss.power_down &amp;&amp;</div><div class='add'>+			dc-&gt;hwseq-&gt;funcs.power_down &amp;&amp;</div><div class='ctx'> 			dc-&gt;hwss.edp_power_control) {</div><div class='ctx'> 		dc-&gt;hwseq-&gt;funcs.edp_backlight_control(edp_link, false);</div><div class='del'>-		dc-&gt;hwss.power_down(dc);</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.power_down(dc);</div><div class='ctx'> 		dc-&gt;hwss.edp_power_control(edp_link, false);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='hunk'>@@ -1701,8 +1926,8 @@ void dcn10_power_down_on_boot(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 			if (link-&gt;link_enc &amp;&amp; link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 					link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc) &amp;&amp;</div><div class='del'>-					dc-&gt;hwss.power_down) {</div><div class='del'>-				dc-&gt;hwss.power_down(dc);</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.power_down) {</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.power_down(dc);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -1813,18 +2038,14 @@ bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	if (dpp_base == NULL)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func)</div><div class='del'>-		tf = plane_state-&gt;in_transfer_func;</div><div class='add'>+	tf = &amp;plane_state-&gt;in_transfer_func;</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;gamma_correction &amp;&amp;</div><div class='del'>-		!dpp_base-&gt;ctx-&gt;dc-&gt;debug.always_use_regamma</div><div class='del'>-		&amp;&amp; !plane_state-&gt;gamma_correction-&gt;is_identity</div><div class='add'>+	if (!dpp_base-&gt;ctx-&gt;dc-&gt;debug.always_use_regamma</div><div class='add'>+		&amp;&amp; !plane_state-&gt;gamma_correction.is_identity</div><div class='ctx'> 			&amp;&amp; dce_use_lut(plane_state-&gt;format))</div><div class='del'>-		dpp_base-&gt;funcs-&gt;dpp_program_input_lut(dpp_base, plane_state-&gt;gamma_correction);</div><div class='add'>+		dpp_base-&gt;funcs-&gt;dpp_program_input_lut(dpp_base, &amp;plane_state-&gt;gamma_correction);</div><div class='ctx'> </div><div class='del'>-	if (tf == NULL)</div><div class='del'>-		dpp_base-&gt;funcs-&gt;dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);</div><div class='del'>-	else if (tf-&gt;type == TF_TYPE_PREDEFINED) {</div><div class='add'>+	if (tf-&gt;type == TF_TYPE_PREDEFINED) {</div><div class='ctx'> 		switch (tf-&gt;tf) {</div><div class='ctx'> 		case TRANSFER_FUNCTION_SRGB:</div><div class='ctx'> 			dpp_base-&gt;funcs-&gt;dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);</div><div class='hunk'>@@ -1861,7 +2082,7 @@ bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> #define MAX_NUM_HW_POINTS 0x200</div><div class='ctx'> </div><div class='ctx'> static void log_tf(struct dc_context *ctx,</div><div class='del'>-				struct dc_transfer_func *tf, uint32_t hw_points_num)</div><div class='add'>+				const struct dc_transfer_func *tf, uint32_t hw_points_num)</div><div class='ctx'> {</div><div class='ctx'> 	// DC_LOG_GAMMA is default logging of all hw points</div><div class='ctx'> 	// DC_LOG_ALL_GAMMA logs all points, not only hw points</div><div class='hunk'>@@ -1898,16 +2119,15 @@ bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> </div><div class='ctx'> 	dpp-&gt;regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;</div><div class='ctx'> </div><div class='del'>-	if (stream-&gt;out_transfer_func &amp;&amp;</div><div class='del'>-	    stream-&gt;out_transfer_func-&gt;type == TF_TYPE_PREDEFINED &amp;&amp;</div><div class='del'>-	    stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_SRGB)</div><div class='add'>+	if (stream-&gt;out_transfer_func.type == TF_TYPE_PREDEFINED &amp;&amp;</div><div class='add'>+	    stream-&gt;out_transfer_func.tf == TRANSFER_FUNCTION_SRGB)</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);</div><div class='ctx'> </div><div class='ctx'> 	/* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full</div><div class='ctx'> 	 * update.</div><div class='ctx'> 	 */</div><div class='ctx'> 	else if (cm_helper_translate_curve_to_hw_format(dc-&gt;ctx,</div><div class='del'>-			stream-&gt;out_transfer_func,</div><div class='add'>+			&amp;stream-&gt;out_transfer_func,</div><div class='ctx'> 			&amp;dpp-&gt;regamma_params, false)) {</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_program_regamma_pwl(</div><div class='ctx'> 				dpp,</div><div class='hunk'>@@ -1915,10 +2135,9 @@ bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	} else</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);</div><div class='ctx'> </div><div class='del'>-	if (stream-&gt;ctx &amp;&amp;</div><div class='del'>-	    stream-&gt;out_transfer_func) {</div><div class='add'>+	if (stream-&gt;ctx) {</div><div class='ctx'> 		log_tf(stream-&gt;ctx,</div><div class='del'>-				stream-&gt;out_transfer_func,</div><div class='add'>+				&amp;stream-&gt;out_transfer_func,</div><div class='ctx'> 				dpp-&gt;regamma_params.hw_points_num);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1988,20 +2207,11 @@ static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	dc-&gt;hwss.get_position(&amp;pipe_ctx, 1, &amp;position);</div><div class='ctx'> 	vpos = position.vertical_count;</div><div class='ctx'> </div><div class='del'>-	/* Avoid wraparound calculation issues */</div><div class='del'>-	vupdate_start += stream-&gt;timing.v_total;</div><div class='del'>-	vupdate_end += stream-&gt;timing.v_total;</div><div class='del'>-	vpos += stream-&gt;timing.v_total;</div><div class='del'>-</div><div class='ctx'> 	if (vpos &lt;= vupdate_start) {</div><div class='ctx'> 		/* VPOS is in VACTIVE or back porch. */</div><div class='ctx'> 		lines_to_vupdate = vupdate_start - vpos;</div><div class='del'>-	} else if (vpos &gt; vupdate_end) {</div><div class='del'>-		/* VPOS is in the front porch. */</div><div class='del'>-		return;</div><div class='ctx'> 	} else {</div><div class='del'>-		/* VPOS is in VUPDATE. */</div><div class='del'>-		lines_to_vupdate = 0;</div><div class='add'>+		lines_to_vupdate = stream-&gt;timing.v_total - vpos + vupdate_start;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate time until VUPDATE in microseconds. */</div><div class='hunk'>@@ -2009,13 +2219,18 @@ static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		stream-&gt;timing.h_total * 10000u / stream-&gt;timing.pix_clk_100hz;</div><div class='ctx'> 	us_to_vupdate = lines_to_vupdate * us_per_line;</div><div class='ctx'> </div><div class='add'>+	/* Stall out until the cursor update completes. */</div><div class='add'>+	if (vupdate_end &lt; vupdate_start)</div><div class='add'>+		vupdate_end += stream-&gt;timing.v_total;</div><div class='add'>+</div><div class='add'>+	/* Position is in the range of vupdate start and end*/</div><div class='add'>+	if (lines_to_vupdate &gt; stream-&gt;timing.v_total - vupdate_end + vupdate_start)</div><div class='add'>+		us_to_vupdate = 0;</div><div class='add'>+</div><div class='ctx'> 	/* 70 us is a conservative estimate of cursor update time*/</div><div class='ctx'> 	if (us_to_vupdate &gt; 70)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	/* Stall out until the cursor update completes. */</div><div class='del'>-	if (vupdate_end &lt; vupdate_start)</div><div class='del'>-		vupdate_end += stream-&gt;timing.v_total;</div><div class='ctx'> 	us_vupdate = (vupdate_end - vupdate_start + 1) * us_per_line;</div><div class='ctx'> 	udelay(us_to_vupdate + us_vupdate);</div><div class='ctx'> }</div><div class='hunk'>@@ -2030,7 +2245,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)</div><div class='ctx'> 	if (lock)</div><div class='ctx'> 		delay_cursor_until_vupdate(dc, pipe);</div><div class='ctx'> </div><div class='del'>-	if (pipe-&gt;stream &amp;&amp; should_use_dmub_lock(pipe-&gt;stream-&gt;link)) {</div><div class='add'>+	if (pipe-&gt;stream &amp;&amp; should_use_dmub_inbox1_lock(dc, pipe-&gt;stream-&gt;link)) {</div><div class='ctx'> 		union dmub_hw_lock_flags hw_locks = { 0 };</div><div class='ctx'> 		struct dmub_hw_lock_inst_flags inst_flags = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -2173,7 +2388,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,</div><div class='ctx'> 	struct dc_crtc_timing *hw_crtc_timing;</div><div class='ctx'> 	uint64_t phase[MAX_PIPES];</div><div class='ctx'> 	uint64_t modulo[MAX_PIPES];</div><div class='del'>-	unsigned int pclk;</div><div class='add'>+	unsigned int pclk = 0;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t embedded_pix_clk_100hz;</div><div class='ctx'> 	uint16_t embedded_h_total;</div><div class='hunk'>@@ -2209,7 +2424,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,</div><div class='ctx'> 					grouped_pipes[i]-&gt;stream-&gt;signal)) {</div><div class='ctx'> 				embedded = i;</div><div class='ctx'> 				master = i;</div><div class='del'>-				phase[i] = embedded_pix_clk_100hz*100;</div><div class='add'>+				phase[i] = embedded_pix_clk_100hz*(uint64_t)100;</div><div class='ctx'> 				modulo[i] = dp_ref_clk_100hz*100;</div><div class='ctx'> 			} else {</div><div class='ctx'> </div><div class='hunk'>@@ -2264,7 +2479,7 @@ void dcn10_enable_vblanks_synchronization(</div><div class='ctx'> 	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct output_pixel_processor *opp;</div><div class='ctx'> 	struct timing_generator *tg;</div><div class='del'>-	int i, width, height, master;</div><div class='add'>+	int i, width = 0, height = 0, master;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(dc_ctx-&gt;logger);</div><div class='ctx'> </div><div class='hunk'>@@ -2330,7 +2545,7 @@ void dcn10_enable_timing_synchronization(</div><div class='ctx'> 	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct output_pixel_processor *opp;</div><div class='ctx'> 	struct timing_generator *tg;</div><div class='del'>-	int i, width, height;</div><div class='add'>+	int i, width = 0, height = 0;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(dc_ctx-&gt;logger);</div><div class='ctx'> </div><div class='hunk'>@@ -2584,8 +2799,11 @@ static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_co</div><div class='ctx'> </div><div class='ctx'> 			while (top-&gt;top_pipe)</div><div class='ctx'> 				top = top-&gt;top_pipe; // Traverse to top pipe_ctx</div><div class='del'>-			if (top-&gt;plane_state &amp;&amp; top-&gt;plane_state-&gt;layer_index == 0)</div><div class='del'>-				return true; // Front MPO plane not hidden</div><div class='add'>+			if (top-&gt;plane_state &amp;&amp; top-&gt;plane_state-&gt;layer_index == 0 &amp;&amp; !top-&gt;plane_state-&gt;global_alpha)</div><div class='add'>+				// Global alpha used by top plane for PIP overlay</div><div class='add'>+				// Pre-multiplied/per-pixel alpha used by MPO</div><div class='add'>+				// Check top plane's global alpha to ensure layer_index &gt; 0 not caused by PIP</div><div class='add'>+				return true; // MPO in use and front plane not hidden</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -2662,7 +2880,6 @@ void dcn10_update_visual_confirm_color(struct dc *dc,</div><div class='ctx'> 	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> </div><div class='ctx'> 	if (mpc-&gt;funcs-&gt;set_bg_color) {</div><div class='del'>-		memcpy(&amp;pipe_ctx-&gt;plane_state-&gt;visual_confirm_color, &amp;(pipe_ctx-&gt;visual_confirm_color), sizeof(struct tg_color));</div><div class='ctx'> 		mpc-&gt;funcs-&gt;set_bg_color(mpc, &amp;(pipe_ctx-&gt;visual_confirm_color), mpcc_id);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -2873,8 +3090,11 @@ static void dcn10_update_dchubp_dpp(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;cursor_attributes.address.quad_part != 0) {</div><div class='del'>-		dc-&gt;hwss.set_cursor_position(pipe_ctx);</div><div class='add'>+		if (dc-&gt;hwss.abort_cursor_offload_update)</div><div class='add'>+			dc-&gt;hwss.abort_cursor_offload_update(dc, pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 		dc-&gt;hwss.set_cursor_attribute(pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.set_cursor_position(pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		if (dc-&gt;hwss.set_cursor_sdr_white_level)</div><div class='ctx'> 			dc-&gt;hwss.set_cursor_sdr_white_level(pipe_ctx);</div><div class='hunk'>@@ -2913,7 +3133,7 @@ static void dcn10_update_dchubp_dpp(</div><div class='ctx'> </div><div class='ctx'> 	hubp-&gt;power_gated = false;</div><div class='ctx'> </div><div class='del'>-	hws-&gt;funcs.update_plane_addr(dc, pipe_ctx);</div><div class='add'>+	dc-&gt;hwss.update_plane_addr(dc, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	if (is_pipe_tree_visible(pipe_ctx))</div><div class='ctx'> 		hubp-&gt;funcs-&gt;set_blank(hubp, false);</div><div class='hunk'>@@ -2996,7 +3216,8 @@ void dcn10_program_pipe(</div><div class='ctx'> 				calculate_vready_offset_for_group(pipe_ctx),</div><div class='ctx'> 				pipe_ctx-&gt;pipe_dlg_param.vstartup_start,</div><div class='ctx'> 				pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='del'>-				pipe_ctx-&gt;pipe_dlg_param.vupdate_width);</div><div class='add'>+				pipe_ctx-&gt;pipe_dlg_param.vupdate_width,</div><div class='add'>+				pipe_ctx-&gt;pipe_dlg_param.pstate_keepout);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, true);</div><div class='hunk'>@@ -3129,7 +3350,7 @@ void dcn10_prepare_bandwidth(</div><div class='ctx'> 			context,</div><div class='ctx'> 			false);</div><div class='ctx'> </div><div class='del'>-	dc-&gt;wm_optimized_required = hubbub-&gt;funcs-&gt;program_watermarks(hubbub,</div><div class='add'>+	dc-&gt;optimized_required = hubbub-&gt;funcs-&gt;program_watermarks(hubbub,</div><div class='ctx'> 			&amp;context-&gt;bw_ctx.bw.dcn.watermarks,</div><div class='ctx'> 			dc-&gt;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000,</div><div class='ctx'> 			true);</div><div class='hunk'>@@ -3206,15 +3427,18 @@ void dcn10_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 	 * as well.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; num_pipes; i++) {</div><div class='del'>-		if ((pipe_ctx[i]-&gt;stream_res.tg != NULL) &amp;&amp; pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs) {</div><div class='del'>-			if (pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-				pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-					pipe_ctx[i]-&gt;stream_res.tg, &amp;params);</div><div class='add'>+		/* dc_state_destruct() might null the stream resources, so fetch tg</div><div class='add'>+		 * here first to avoid a race condition. The lifetime of the pointee</div><div class='add'>+		 * itself (the timing_generator object) is not a problem here.</div><div class='add'>+		 */</div><div class='add'>+		struct timing_generator *tg = pipe_ctx[i]-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+		if ((tg != NULL) &amp;&amp; tg-&gt;funcs) {</div><div class='add'>+			set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]-&gt;stream, &amp;params);</div><div class='ctx'> 			if (adjust.v_total_max != 0 &amp;&amp; adjust.v_total_min != 0)</div><div class='del'>-				if (pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='del'>-					pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='del'>-						pipe_ctx[i]-&gt;stream_res.tg,</div><div class='del'>-						event_triggers, num_frames);</div><div class='add'>+				if (tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='add'>+					tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='add'>+						tg, event_triggers, num_frames);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -3419,53 +3643,6 @@ void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)</div><div class='ctx'> 	hubbub-&gt;funcs-&gt;update_dchub(hubbub, dh_data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)</div><div class='del'>-{</div><div class='del'>-	struct pipe_ctx *test_pipe, *split_pipe;</div><div class='del'>-	const struct scaler_data *scl_data = &amp;pipe_ctx-&gt;plane_res.scl_data;</div><div class='del'>-	struct rect r1 = scl_data-&gt;recout, r2, r2_half;</div><div class='del'>-	int r1_r = r1.x + r1.width, r1_b = r1.y + r1.height, r2_r, r2_b;</div><div class='del'>-	int cur_layer = pipe_ctx-&gt;plane_state-&gt;layer_index;</div><div class='del'>-</div><div class='del'>-	/**</div><div class='del'>-	 * Disable the cursor if there's another pipe above this with a</div><div class='del'>-	 * plane that contains this pipe's viewport to prevent double cursor</div><div class='del'>-	 * and incorrect scaling artifacts.</div><div class='del'>-	 */</div><div class='del'>-	for (test_pipe = pipe_ctx-&gt;top_pipe; test_pipe;</div><div class='del'>-	     test_pipe = test_pipe-&gt;top_pipe) {</div><div class='del'>-		// Skip invisible layer and pipe-split plane on same layer</div><div class='del'>-		if (!test_pipe-&gt;plane_state ||</div><div class='del'>-		    !test_pipe-&gt;plane_state-&gt;visible ||</div><div class='del'>-		    test_pipe-&gt;plane_state-&gt;layer_index == cur_layer)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		r2 = test_pipe-&gt;plane_res.scl_data.recout;</div><div class='del'>-		r2_r = r2.x + r2.width;</div><div class='del'>-		r2_b = r2.y + r2.height;</div><div class='del'>-		split_pipe = test_pipe;</div><div class='del'>-</div><div class='del'>-		/**</div><div class='del'>-		 * There is another half plane on same layer because of</div><div class='del'>-		 * pipe-split, merge together per same height.</div><div class='del'>-		 */</div><div class='del'>-		for (split_pipe = pipe_ctx-&gt;top_pipe; split_pipe;</div><div class='del'>-		     split_pipe = split_pipe-&gt;top_pipe)</div><div class='del'>-			if (split_pipe-&gt;plane_state-&gt;layer_index == test_pipe-&gt;plane_state-&gt;layer_index) {</div><div class='del'>-				r2_half = split_pipe-&gt;plane_res.scl_data.recout;</div><div class='del'>-				r2.x = (r2_half.x &lt; r2.x) ? r2_half.x : r2.x;</div><div class='del'>-				r2.width = r2.width + r2_half.width;</div><div class='del'>-				r2_r = r2.x + r2.width;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-		if (r1.x &gt;= r2.x &amp;&amp; r1.y &gt;= r2.y &amp;&amp; r1_r &lt;= r2_r &amp;&amp; r1_b &lt;= r2_b)</div><div class='del'>-			return true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_cursor_position pos_cpy = pipe_ctx-&gt;stream-&gt;cursor_position;</div><div class='hunk'>@@ -3489,6 +3666,8 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	int y_plane = pipe_ctx-&gt;plane_state-&gt;dst_rect.y;</div><div class='ctx'> 	int x_pos = pos_cpy.x;</div><div class='ctx'> 	int y_pos = pos_cpy.y;</div><div class='add'>+	int clip_x = pipe_ctx-&gt;plane_state-&gt;clip_rect.x;</div><div class='add'>+	int clip_width = pipe_ctx-&gt;plane_state-&gt;clip_rect.width;</div><div class='ctx'> </div><div class='ctx'> 	if ((pipe_ctx-&gt;top_pipe != NULL) || (pipe_ctx-&gt;bottom_pipe != NULL)) {</div><div class='ctx'> 		if ((pipe_ctx-&gt;plane_state-&gt;src_rect.width != pipe_ctx-&gt;plane_res.scl_data.viewport.width) ||</div><div class='hunk'>@@ -3507,7 +3686,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * Translate cursor from stream space to plane space.</div><div class='add'>+	 * Translate cursor and clip offset from stream space to plane space.</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * If the cursor is scaled then we need to scale the position</div><div class='ctx'> 	 * to be in the approximately correct place. We can't do anything</div><div class='hunk'>@@ -3524,6 +3703,10 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 				pipe_ctx-&gt;plane_state-&gt;dst_rect.width;</div><div class='ctx'> 		y_pos = (y_pos - y_plane) * pipe_ctx-&gt;plane_state-&gt;src_rect.height /</div><div class='ctx'> 				pipe_ctx-&gt;plane_state-&gt;dst_rect.height;</div><div class='add'>+		clip_x = (clip_x - x_plane) * pipe_ctx-&gt;plane_state-&gt;src_rect.width /</div><div class='add'>+				pipe_ctx-&gt;plane_state-&gt;dst_rect.width;</div><div class='add'>+		clip_width = clip_width * pipe_ctx-&gt;plane_state-&gt;src_rect.width /</div><div class='add'>+				pipe_ctx-&gt;plane_state-&gt;dst_rect.width;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='hunk'>@@ -3565,35 +3748,23 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 			== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)</div><div class='ctx'> 		pos_cpy.enable = false;</div><div class='ctx'> </div><div class='del'>-	if (pos_cpy.enable &amp;&amp; dcn10_can_pipe_disable_cursor(pipe_ctx))</div><div class='add'>+	if (pos_cpy.enable &amp;&amp; resource_can_pipe_disable_cursor(pipe_ctx))</div><div class='ctx'> 		pos_cpy.enable = false;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	if (param.rotation == ROTATION_ANGLE_0) {</div><div class='del'>-		int viewport_width =</div><div class='del'>-			pipe_ctx-&gt;plane_res.scl_data.viewport.width;</div><div class='del'>-		int viewport_x =</div><div class='del'>-			pipe_ctx-&gt;plane_res.scl_data.viewport.x;</div><div class='ctx'> </div><div class='ctx'> 		if (param.mirror) {</div><div class='del'>-			if (pipe_split_on || odm_combine_on) {</div><div class='del'>-				if (pos_cpy.x &gt;= viewport_width + viewport_x) {</div><div class='del'>-					pos_cpy.x = 2 * viewport_width</div><div class='del'>-							- pos_cpy.x + 2 * viewport_x;</div><div class='del'>-				} else {</div><div class='del'>-					uint32_t temp_x = pos_cpy.x;</div><div class='del'>-</div><div class='del'>-					pos_cpy.x = 2 * viewport_x - pos_cpy.x;</div><div class='del'>-					if (temp_x &gt;= viewport_x +</div><div class='del'>-						(int)hubp-&gt;curs_attr.width || pos_cpy.x</div><div class='del'>-						&lt;= (int)hubp-&gt;curs_attr.width +</div><div class='del'>-						pipe_ctx-&gt;plane_state-&gt;src_rect.x) {</div><div class='del'>-						pos_cpy.x = temp_x + viewport_width;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='del'>-				pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x;</div><div class='del'>-			}</div><div class='add'>+			/*</div><div class='add'>+			 * The plane is split into multiple viewports.</div><div class='add'>+			 * The combination of all viewports span the</div><div class='add'>+			 * entirety of the clip rect.</div><div class='add'>+			 *</div><div class='add'>+			 * For no pipe_split, viewport_width is represents</div><div class='add'>+			 * the full width of the clip_rect, so we can just</div><div class='add'>+			 * mirror it.</div><div class='add'>+			 */</div><div class='add'>+			pos_cpy.x = clip_width - pos_cpy.x + 2 * clip_x;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	// Swap axis and mirror horizontally</div><div class='hunk'>@@ -3663,30 +3834,17 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	}</div><div class='ctx'> 	// Mirror horizontally and vertically</div><div class='ctx'> 	else if (param.rotation == ROTATION_ANGLE_180) {</div><div class='del'>-		int viewport_width =</div><div class='del'>-			pipe_ctx-&gt;plane_res.scl_data.viewport.width;</div><div class='del'>-		int viewport_x =</div><div class='del'>-			pipe_ctx-&gt;plane_res.scl_data.viewport.x;</div><div class='del'>-</div><div class='ctx'> 		if (!param.mirror) {</div><div class='del'>-			if (pipe_split_on || odm_combine_on) {</div><div class='del'>-				if (pos_cpy.x &gt;= viewport_width + viewport_x) {</div><div class='del'>-					pos_cpy.x = 2 * viewport_width</div><div class='del'>-							- pos_cpy.x + 2 * viewport_x;</div><div class='del'>-				} else {</div><div class='del'>-					uint32_t temp_x = pos_cpy.x;</div><div class='del'>-</div><div class='del'>-					pos_cpy.x = 2 * viewport_x - pos_cpy.x;</div><div class='del'>-					if (temp_x &gt;= viewport_x +</div><div class='del'>-						(int)hubp-&gt;curs_attr.width || pos_cpy.x</div><div class='del'>-						&lt;= (int)hubp-&gt;curs_attr.width +</div><div class='del'>-						pipe_ctx-&gt;plane_state-&gt;src_rect.x) {</div><div class='del'>-						pos_cpy.x = 2 * viewport_width - temp_x;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='del'>-				pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x;</div><div class='del'>-			}</div><div class='add'>+			/*</div><div class='add'>+			 * The plane is split into multiple viewports.</div><div class='add'>+			 * The combination of all viewports span the</div><div class='add'>+			 * entirety of the clip rect.</div><div class='add'>+			 *</div><div class='add'>+			 * For no pipe_split, viewport_width is represents</div><div class='add'>+			 * the full width of the clip_rect, so we can just</div><div class='add'>+			 * mirror it.</div><div class='add'>+			 */</div><div class='add'>+			pos_cpy.x = clip_width - pos_cpy.x + 2 * clip_x;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='hunk'>@@ -3958,3 +4116,32 @@ void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)</div><div class='ctx'> 			dcc_en_bits[i] = s-&gt;dcc_en ? 1 : 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcn10_reset_surface_dcc_and_tiling - Set DCC and tiling in DCN to their disable mode.</div><div class='add'>+ *</div><div class='add'>+ * @pipe_ctx: Pointer to the pipe context structure.</div><div class='add'>+ * @plane_state: Surface state</div><div class='add'>+ * @clear_tiling: If true set tiling to Linear, otherwise does not change tiling</div><div class='add'>+ *</div><div class='add'>+ * This function is responsible for call the HUBP block to disable DCC and set</div><div class='add'>+ * tiling to the linear mode.</div><div class='add'>+ */</div><div class='add'>+void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,</div><div class='add'>+					struct dc_plane_state *plane_state,</div><div class='add'>+					bool clear_tiling)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+</div><div class='add'>+	if (!hubp)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* if framebuffer is tiled, disable tiling */</div><div class='add'>+	if (clear_tiling &amp;&amp; hubp-&gt;funcs-&gt;hubp_clear_tiling)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_clear_tiling(hubp);</div><div class='add'>+</div><div class='add'>+	/* force page flip to see the new content of the framebuffer */</div><div class='add'>+	hubp-&gt;funcs-&gt;hubp_program_surface_flip_and_addr(hubp,</div><div class='add'>+							&amp;plane_state-&gt;address,</div><div class='add'>+							true);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h<br/>index bc5dd68a2408..57d30ea225f2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h</a></div><div class='hunk'>@@ -50,6 +50,13 @@ void dcn10_optimize_bandwidth(</div><div class='ctx'> void dcn10_prepare_bandwidth(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context);</div><div class='add'>+void dcn10_wait_for_pipe_update_if_needed(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		bool is_surface_update_only);</div><div class='add'>+void dcn10_set_wait_for_update_needed_for_pipe(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn10_pipe_control_lock(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct pipe_ctx *pipe,</div><div class='hunk'>@@ -207,4 +214,8 @@ void dcn10_update_visual_confirm_color(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		int mpcc_id);</div><div class='ctx'> </div><div class='add'>+void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx,</div><div class='add'>+					struct dc_plane_state *plane_state,</div><div class='add'>+					bool clear_tiling);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCN10_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c<br/>index a5bdac79a744..079c226c1097 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c</a></div><div class='hunk'>@@ -40,6 +40,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {</div><div class='ctx'> 	.update_plane_addr = dcn10_update_plane_addr,</div><div class='ctx'> 	.update_dchub = dcn10_update_dchub,</div><div class='ctx'> 	.update_pending_status = dcn10_update_pending_status,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.program_output_csc = dcn10_program_output_csc,</div><div class='ctx'> 	.enable_accelerated_mode = dce110_enable_accelerated_mode,</div><div class='ctx'> 	.enable_timing_synchronization = dcn10_enable_timing_synchronization,</div><div class='hunk'>@@ -78,7 +79,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {</div><div class='ctx'> 	.get_clock = dcn10_get_clock,</div><div class='ctx'> 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='del'>-	.power_down = dce110_power_down,</div><div class='ctx'> 	.set_backlight_level = dce110_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,</div><div class='ctx'> 	.set_pipe = dce110_set_pipe,</div><div class='hunk'>@@ -92,7 +92,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn10_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn10_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.program_pipe = dcn10_program_pipe,</div><div class='ctx'> 	.update_mpcc = dcn10_update_mpcc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c<br/>index 8b3536c380b8..c8ff8ae85a03 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c</a></div><div class='hunk'>@@ -54,7 +54,7 @@</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "inc/link_enc_cfg.h"</div><div class='ctx'> #include "link_hwss.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='hunk'>@@ -76,6 +76,7 @@ void dcn20_log_color_state(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='add'>+	bool is_gamut_remap_available = false;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	DTN_INFO("DPP:  DGAM mode  SHAPER mode  3DLUT mode  3DLUT bit depth"</div><div class='hunk'>@@ -89,15 +90,15 @@ void dcn20_log_color_state(struct dc *dc,</div><div class='ctx'> 		struct dcn_dpp_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_read_state(dpp, &amp;s);</div><div class='del'>-		dpp-&gt;funcs-&gt;dpp_get_gamut_remap(dpp, &amp;s.gamut_remap);</div><div class='add'>+		if (dpp-&gt;funcs-&gt;dpp_get_gamut_remap) {</div><div class='add'>+			dpp-&gt;funcs-&gt;dpp_get_gamut_remap(dpp, &amp;s.gamut_remap);</div><div class='add'>+			is_gamut_remap_available = true;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!s.is_enabled)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		DTN_INFO("[%2d]:  %8s  %11s  %10s  %15s  %10s  %9s  %12s  "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld",</div><div class='add'>+		DTN_INFO("[%2d]:  %8s  %11s  %10s  %15s  %10s  %9s",</div><div class='ctx'> 			dpp-&gt;inst,</div><div class='ctx'> 			(s.dgam_lut_mode == 0) ? "Bypass" :</div><div class='ctx'> 			 ((s.dgam_lut_mode == 1) ? "sRGB" :</div><div class='hunk'>@@ -114,10 +115,17 @@ void dcn20_log_color_state(struct dc *dc,</div><div class='ctx'> 			(s.lut3d_bit_depth &lt;= 0) ? "12-bit" : "10-bit",</div><div class='ctx'> 			(s.lut3d_size == 0) ? "17x17x17" : "9x9x9",</div><div class='ctx'> 			(s.rgam_lut_mode == 1) ? "RAM A" :</div><div class='del'>-			 ((s.rgam_lut_mode == 1) ? "RAM B" : "Bypass"),</div><div class='add'>+			 ((s.rgam_lut_mode == 1) ? "RAM B" : "Bypass"));</div><div class='add'>+</div><div class='add'>+		if (is_gamut_remap_available) {</div><div class='add'>+			DTN_INFO("  %12s  "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld",</div><div class='add'>+</div><div class='ctx'> 			(s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :</div><div class='del'>-			 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :</div><div class='del'>-								   "SW"),</div><div class='add'>+				((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :</div><div class='add'>+									  "SW"),</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[0].value,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[1].value,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[2].value,</div><div class='hunk'>@@ -130,6 +138,8 @@ void dcn20_log_color_state(struct dc *dc,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[9].value,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[10].value,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[11].value);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		DTN_INFO("\n");</div><div class='ctx'> 	}</div><div class='ctx'> 	DTN_INFO("\n");</div><div class='hunk'>@@ -155,7 +165,7 @@ void dcn20_log_color_state(struct dc *dc,</div><div class='ctx'> 	DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE"</div><div class='ctx'> 		 "  OGAM mode\n");</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;mpcc_count; i++) {</div><div class='ctx'> 		struct mpcc_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		pool-&gt;mpc-&gt;funcs-&gt;read_mpcc_state(pool-&gt;mpc, i, &amp;s);</div><div class='hunk'>@@ -204,7 +214,7 @@ static int find_free_gsl_group(const struct dc *dc)</div><div class='ctx'>  * gsl_0 &lt;=&gt; pipe_ctx-&gt;stream_res.gsl_group == 1</div><div class='ctx'>  * Using a magic value like -1 would require tracking all inits/resets</div><div class='ctx'>  */</div><div class='del'>- void dcn20_setup_gsl_group_as_lock(</div><div class='add'>+void dcn20_setup_gsl_group_as_lock(</div><div class='ctx'> 		const struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		bool enable)</div><div class='hunk'>@@ -273,14 +283,13 @@ static int find_free_gsl_group(const struct dc *dc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* at this point we want to program whether it's to enable or disable */</div><div class='del'>-	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl != NULL &amp;&amp;</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl_source_select != NULL) {</div><div class='add'>+	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl != NULL) {</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 			&amp;gsl);</div><div class='del'>-</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl_source_select(</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg, group_idx,	enable ? 4 : 0);</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl_source_select != NULL)</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_gsl_source_select(</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg, group_idx, enable ? 4 : 0);</div><div class='ctx'> 	} else</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='ctx'> }</div><div class='hunk'>@@ -403,7 +412,7 @@ void dcn20_init_blank(</div><div class='ctx'> 	struct output_pixel_processor *opp = NULL;</div><div class='ctx'> 	struct output_pixel_processor *bottom_opp = NULL;</div><div class='ctx'> 	uint32_t num_opps, opp_id_src0, opp_id_src1;</div><div class='del'>-	uint32_t otg_active_width, otg_active_height;</div><div class='add'>+	uint32_t otg_active_width = 0, otg_active_height = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* program opp dpg blank color */</div><div class='ctx'> 	color_space = COLOR_SPACE_SRGB;</div><div class='hunk'>@@ -605,6 +614,14 @@ void dcn20_dpp_pg_control(</div><div class='ctx'> 		 *		DOMAIN11_PGFSM_PWR_STATUS, pwr_status,</div><div class='ctx'> 		 * 		1, 1000);</div><div class='ctx'> 		 */</div><div class='add'>+</div><div class='add'>+		/* Force disable cursor on plane powerdown on DPP 5 using dpp_force_disable_cursor */</div><div class='add'>+		if (!power_on) {</div><div class='add'>+			struct dpp *dpp5 = hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dpps[dpp_inst];</div><div class='add'>+			if (dpp5 &amp;&amp; dpp5-&gt;funcs-&gt;dpp_force_disable_cursor)</div><div class='add'>+				dpp5-&gt;funcs-&gt;dpp_force_disable_cursor(dpp5);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -758,9 +775,9 @@ void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bla</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,</div><div class='del'>-		int opp_cnt)</div><div class='add'>+		int opp_cnt, bool is_two_pixels_per_container)</div><div class='ctx'> {</div><div class='del'>-	bool hblank_halved = optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing);</div><div class='add'>+	bool hblank_halved = is_two_pixels_per_container;</div><div class='ctx'> 	int flow_ctrl_cnt;</div><div class='ctx'> </div><div class='ctx'> 	if (opp_cnt &gt;= 2)</div><div class='hunk'>@@ -820,25 +837,26 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	struct drr_params params = {0};</div><div class='ctx'> 	unsigned int event_triggers = 0;</div><div class='del'>-	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 1;</div><div class='del'>-	int opp_inst[MAX_PIPES] = { pipe_ctx-&gt;stream_res.opp-&gt;inst };</div><div class='add'>+	int opp_inst[MAX_PIPES] = {0};</div><div class='ctx'> 	bool interlace = stream-&gt;timing.flags.INTERLACE;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct mpc_dwb_flow_control flow_control;</div><div class='ctx'> 	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='del'>-	bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing));</div><div class='del'>-	unsigned int k1_div = PIXEL_RATE_DIV_NA;</div><div class='del'>-	unsigned int k2_div = PIXEL_RATE_DIV_NA;</div><div class='del'>-</div><div class='del'>-	if (hws-&gt;funcs.calculate_dccg_k1_k2_values &amp;&amp; dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div) {</div><div class='del'>-		hws-&gt;funcs.calculate_dccg_k1_k2_values(pipe_ctx, &amp;k1_div, &amp;k2_div);</div><div class='del'>-</div><div class='add'>+	bool is_two_pixels_per_container =</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing);</div><div class='add'>+	bool rate_control_2x_pclk = (interlace || is_two_pixels_per_container);</div><div class='add'>+	int odm_slice_width;</div><div class='add'>+	int last_odm_slice_width;</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div(</div><div class='ctx'> 			dc-&gt;res_pool-&gt;dccg,</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='del'>-			k1_div, k2_div);</div><div class='del'>-	}</div><div class='add'>+			pipe_ctx-&gt;pixel_rate_divider.div_factor1,</div><div class='add'>+			pipe_ctx-&gt;pixel_rate_divider.div_factor2);</div><div class='add'>+</div><div class='ctx'> 	/* by upper caller loop, pipe0 is parent pipe and be called first.</div><div class='ctx'> 	 * back end is set up by for pipe0. Other children pipe share back end</div><div class='ctx'> 	 * with pipe 0. No program is needed.</div><div class='hunk'>@@ -848,16 +866,17 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> </div><div class='ctx'> 	/* TODO check if timing_changed, disable stream if timing changed */</div><div class='ctx'> </div><div class='del'>-	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='del'>-		opp_inst[opp_cnt] = odm_pipe-&gt;stream_res.opp-&gt;inst;</div><div class='del'>-		opp_cnt++;</div><div class='del'>-	}</div><div class='add'>+	opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &amp;context-&gt;res_ctx, opp_heads);</div><div class='add'>+	for (i = 0; i &lt; opp_cnt; i++)</div><div class='add'>+		opp_inst[i] = opp_heads[i]-&gt;stream_res.opp-&gt;inst;</div><div class='ctx'> </div><div class='add'>+	odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);</div><div class='add'>+	last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);</div><div class='ctx'> 	if (opp_cnt &gt; 1)</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg,</div><div class='del'>-				opp_inst, opp_cnt,</div><div class='del'>-				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+				opp_inst, opp_cnt, odm_slice_width,</div><div class='add'>+				last_odm_slice_width);</div><div class='ctx'> </div><div class='ctx'> 	/* HW program guide assume display already disable</div><div class='ctx'> 	 * by unplug sequence. OTG assume stop.</div><div class='hunk'>@@ -873,6 +892,22 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 		return DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='add'>+		struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+		struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+		struct dtbclk_dto_params dto_params = {0};</div><div class='add'>+</div><div class='add'>+		if (dccg-&gt;funcs-&gt;set_dtbclk_p_src)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_dtbclk_p_src(dccg, DTBCLK0, tg-&gt;inst);</div><div class='add'>+</div><div class='add'>+		dto_params.otg_inst = tg-&gt;inst;</div><div class='add'>+		dto_params.pixclk_khz = pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz / 10;</div><div class='add'>+		dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);</div><div class='add'>+		dto_params.timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+		dto_params.ref_dtbclk_khz = dc-&gt;clk_mgr-&gt;funcs-&gt;get_dtb_ref_clk_frequency(dc-&gt;clk_mgr);</div><div class='add'>+		dccg-&gt;funcs-&gt;set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dc_is_hdmi_tmds_signal(stream-&gt;signal)) {</div><div class='ctx'> 		stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 1;</div><div class='ctx'> 		if (stream-&gt;link-&gt;phy_state.symclk_state == SYMCLK_OFF_TX_OFF)</div><div class='hunk'>@@ -891,13 +926,15 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 			pipe_ctx-&gt;pipe_dlg_param.vstartup_start,</div><div class='ctx'> 			pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='ctx'> 			pipe_ctx-&gt;pipe_dlg_param.vupdate_width,</div><div class='add'>+			pipe_ctx-&gt;pipe_dlg_param.pstate_keepout,</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;signal,</div><div class='ctx'> 			true);</div><div class='ctx'> </div><div class='ctx'> 	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt &gt; 1;</div><div class='ctx'> 	flow_control.flow_ctrl_mode = 0;</div><div class='ctx'> 	flow_control.flow_ctrl_cnt0 = 0x80;</div><div class='del'>-	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);</div><div class='add'>+	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt,</div><div class='add'>+			is_two_pixels_per_container);</div><div class='ctx'> 	if (mpc-&gt;funcs-&gt;set_out_rate_control) {</div><div class='ctx'> 		for (i = 0; i &lt; opp_cnt; ++i) {</div><div class='ctx'> 			mpc-&gt;funcs-&gt;set_out_rate_control(</div><div class='hunk'>@@ -908,14 +945,15 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='del'>-		odm_pipe-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='del'>-				odm_pipe-&gt;stream_res.opp,</div><div class='add'>+	for (i = 0; i &lt; opp_cnt; i++) {</div><div class='add'>+		opp_heads[i]-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='add'>+				opp_heads[i]-&gt;stream_res.opp,</div><div class='ctx'> 				true);</div><div class='del'>-</div><div class='del'>-	pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='del'>-			pipe_ctx-&gt;stream_res.opp,</div><div class='del'>-			true);</div><div class='add'>+		opp_heads[i]-&gt;stream_res.opp-&gt;funcs-&gt;opp_program_left_edge_extra_pixel(</div><div class='add'>+				opp_heads[i]-&gt;stream_res.opp,</div><div class='add'>+				stream-&gt;timing.pixel_encoding,</div><div class='add'>+				resource_is_pipe_type(opp_heads[i], OTG_MASTER));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	hws-&gt;funcs.blank_pixel_data(dc, pipe_ctx, true);</div><div class='ctx'> </div><div class='hunk'>@@ -925,15 +963,13 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 		return DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	hws-&gt;funcs.wait_for_blank_complete(pipe_ctx-&gt;stream_res.opp);</div><div class='add'>+	udelay(stream-&gt;timing.v_total * (stream-&gt;timing.h_total * 10000u / stream-&gt;timing.pix_clk_100hz));</div><div class='ctx'> </div><div class='ctx'> 	params.vertical_total_min = stream-&gt;adjust.v_total_min;</div><div class='ctx'> 	params.vertical_total_max = stream-&gt;adjust.v_total_max;</div><div class='ctx'> 	params.vertical_total_mid = stream-&gt;adjust.v_total_mid;</div><div class='ctx'> 	params.vertical_total_mid_frame_num = stream-&gt;adjust.v_total_mid_frame_num;</div><div class='del'>-	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg, &amp;params);</div><div class='add'>+	set_drr_and_clear_adjust_pending(pipe_ctx, stream, &amp;params);</div><div class='ctx'> </div><div class='ctx'> 	// DRR should set trigger event to monitor surface update event</div><div class='ctx'> 	if (stream-&gt;adjust.v_total_min != 0 &amp;&amp; stream-&gt;adjust.v_total_max != 0)</div><div class='hunk'>@@ -954,27 +990,11 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 	/* TODO enable stream if timing changed */</div><div class='ctx'> 	/* TODO unblank stream if DP */</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {</div><div class='del'>-		if (pipe_ctx-&gt;stream_res.tg &amp;&amp; pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable)</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable)</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable(pipe_ctx-&gt;stream_res.tg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='del'>-		struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='del'>-		struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='del'>-		struct dtbclk_dto_params dto_params = {0};</div><div class='del'>-</div><div class='del'>-		if (dccg-&gt;funcs-&gt;set_dtbclk_p_src)</div><div class='del'>-			dccg-&gt;funcs-&gt;set_dtbclk_p_src(dccg, DTBCLK0, tg-&gt;inst);</div><div class='del'>-</div><div class='del'>-		dto_params.otg_inst = tg-&gt;inst;</div><div class='del'>-		dto_params.pixclk_khz = pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz / 10;</div><div class='del'>-		dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);</div><div class='del'>-		dto_params.timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='del'>-		dto_params.ref_dtbclk_khz = dc-&gt;clk_mgr-&gt;funcs-&gt;get_dtb_ref_clk_frequency(dc-&gt;clk_mgr);</div><div class='del'>-		dccg-&gt;funcs-&gt;set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1011,7 +1031,7 @@ bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> {</div><div class='ctx'> 	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='ctx'> 	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='del'>-	struct pwl_params *params = NULL;</div><div class='add'>+	const struct pwl_params *params = NULL;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * program OGAM only for the top pipe</div><div class='ctx'> 	 * if there is a pipe split then fix diagnostic is required:</div><div class='hunk'>@@ -1022,25 +1042,26 @@ bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	if (mpc-&gt;funcs-&gt;power_on_mpc_mem_pwr)</div><div class='ctx'> 		mpc-&gt;funcs-&gt;power_on_mpc_mem_pwr(mpc, mpcc_id, true);</div><div class='ctx'> 	if (pipe_ctx-&gt;top_pipe == NULL</div><div class='del'>-			&amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma &amp;&amp; stream-&gt;out_transfer_func) {</div><div class='del'>-		if (stream-&gt;out_transfer_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			params = &amp;stream-&gt;out_transfer_func-&gt;pwl;</div><div class='del'>-		else if (pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;type ==</div><div class='add'>+			&amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma) {</div><div class='add'>+		if (stream-&gt;out_transfer_func.type == TF_TYPE_HWPWL)</div><div class='add'>+			params = &amp;stream-&gt;out_transfer_func.pwl;</div><div class='add'>+		else if (pipe_ctx-&gt;stream-&gt;out_transfer_func.type ==</div><div class='ctx'> 			TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='ctx'> 			cm_helper_translate_curve_to_hw_format(dc-&gt;ctx,</div><div class='del'>-			stream-&gt;out_transfer_func,</div><div class='add'>+			&amp;stream-&gt;out_transfer_func,</div><div class='ctx'> 			&amp;mpc-&gt;blender_params, false))</div><div class='ctx'> 			params = &amp;mpc-&gt;blender_params;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * there is no ROM</div><div class='ctx'> 		 */</div><div class='del'>-		if (stream-&gt;out_transfer_func-&gt;type == TF_TYPE_PREDEFINED)</div><div class='add'>+		if (stream-&gt;out_transfer_func.type == TF_TYPE_PREDEFINED)</div><div class='ctx'> 			BREAK_TO_DEBUGGER();</div><div class='ctx'> 	}</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * if above if is not executed then 'params' equal to 0 and set in bypass</div><div class='ctx'> 	 */</div><div class='del'>-	mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='add'>+	if (mpc-&gt;funcs-&gt;set_output_gamma)</div><div class='add'>+		mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -1050,17 +1071,15 @@ bool dcn20_set_blend_lut(</div><div class='ctx'> {</div><div class='ctx'> 	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	bool result = true;</div><div class='del'>-	struct pwl_params *blend_lut = NULL;</div><div class='del'>-</div><div class='del'>-	if (plane_state-&gt;blend_tf) {</div><div class='del'>-		if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			blend_lut = &amp;plane_state-&gt;blend_tf-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='del'>-			cm_helper_translate_curve_to_hw_format(plane_state-&gt;ctx,</div><div class='del'>-					plane_state-&gt;blend_tf,</div><div class='del'>-					&amp;dpp_base-&gt;regamma_params, false);</div><div class='del'>-			blend_lut = &amp;dpp_base-&gt;regamma_params;</div><div class='del'>-		}</div><div class='add'>+	const struct pwl_params *blend_lut = NULL;</div><div class='add'>+</div><div class='add'>+	if (plane_state-&gt;blend_tf.type == TF_TYPE_HWPWL)</div><div class='add'>+		blend_lut = &amp;plane_state-&gt;blend_tf.pwl;</div><div class='add'>+	else if (plane_state-&gt;blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		cm_helper_translate_curve_to_hw_format(plane_state-&gt;ctx,</div><div class='add'>+				&amp;plane_state-&gt;blend_tf,</div><div class='add'>+				&amp;dpp_base-&gt;regamma_params, false);</div><div class='add'>+		blend_lut = &amp;dpp_base-&gt;regamma_params;</div><div class='ctx'> 	}</div><div class='ctx'> 	result = dpp_base-&gt;funcs-&gt;dpp_program_blnd_lut(dpp_base, blend_lut);</div><div class='ctx'> </div><div class='hunk'>@@ -1072,24 +1091,21 @@ bool dcn20_set_shaper_3dlut(</div><div class='ctx'> {</div><div class='ctx'> 	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	bool result = true;</div><div class='del'>-	struct pwl_params *shaper_lut = NULL;</div><div class='del'>-</div><div class='del'>-	if (plane_state-&gt;in_shaper_func) {</div><div class='del'>-		if (plane_state-&gt;in_shaper_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			shaper_lut = &amp;plane_state-&gt;in_shaper_func-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;in_shaper_func-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='del'>-			cm_helper_translate_curve_to_hw_format(plane_state-&gt;ctx,</div><div class='del'>-					plane_state-&gt;in_shaper_func,</div><div class='del'>-					&amp;dpp_base-&gt;shaper_params, true);</div><div class='del'>-			shaper_lut = &amp;dpp_base-&gt;shaper_params;</div><div class='del'>-		}</div><div class='add'>+	const struct pwl_params *shaper_lut = NULL;</div><div class='add'>+</div><div class='add'>+	if (plane_state-&gt;in_shaper_func.type == TF_TYPE_HWPWL)</div><div class='add'>+		shaper_lut = &amp;plane_state-&gt;in_shaper_func.pwl;</div><div class='add'>+	else if (plane_state-&gt;in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		cm_helper_translate_curve_to_hw_format(plane_state-&gt;ctx,</div><div class='add'>+				&amp;plane_state-&gt;in_shaper_func,</div><div class='add'>+				&amp;dpp_base-&gt;shaper_params, true);</div><div class='add'>+		shaper_lut = &amp;dpp_base-&gt;shaper_params;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	result = dpp_base-&gt;funcs-&gt;dpp_program_shaper_lut(dpp_base, shaper_lut);</div><div class='del'>-	if (plane_state-&gt;lut3d_func &amp;&amp;</div><div class='del'>-		plane_state-&gt;lut3d_func-&gt;state.bits.initialized == 1)</div><div class='add'>+	if (plane_state-&gt;lut3d_func.state.bits.initialized == 1)</div><div class='ctx'> 		result = dpp_base-&gt;funcs-&gt;dpp_program_3dlut(dpp_base,</div><div class='del'>-								&amp;plane_state-&gt;lut3d_func-&gt;lut_3d);</div><div class='add'>+								&amp;plane_state-&gt;lut3d_func.lut_3d);</div><div class='ctx'> 	else</div><div class='ctx'> 		result = dpp_base-&gt;funcs-&gt;dpp_program_3dlut(dpp_base, NULL);</div><div class='ctx'> </div><div class='hunk'>@@ -1112,15 +1128,7 @@ bool dcn20_set_input_transfer_func(struct dc *dc,</div><div class='ctx'> 	hws-&gt;funcs.set_shaper_3dlut(pipe_ctx, plane_state);</div><div class='ctx'> 	hws-&gt;funcs.set_blend_lut(pipe_ctx, plane_state);</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func)</div><div class='del'>-		tf = plane_state-&gt;in_transfer_func;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	if (tf == NULL) {</div><div class='del'>-		dpp_base-&gt;funcs-&gt;dpp_set_degamma(dpp_base,</div><div class='del'>-				IPP_DEGAMMA_MODE_BYPASS);</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='add'>+	tf = &amp;plane_state-&gt;in_transfer_func;</div><div class='ctx'> </div><div class='ctx'> 	if (tf-&gt;type == TF_TYPE_HWPWL || tf-&gt;type == TF_TYPE_DISTRIBUTED_POINTS)</div><div class='ctx'> 		use_degamma_ram = true;</div><div class='hunk'>@@ -1185,6 +1193,8 @@ void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 1;</div><div class='ctx'> 	int opp_inst[MAX_PIPES] = { pipe_ctx-&gt;stream_res.opp-&gt;inst };</div><div class='add'>+	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);</div><div class='add'>+	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);</div><div class='ctx'> </div><div class='ctx'> 	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 		opp_inst[opp_cnt] = odm_pipe-&gt;stream_res.opp-&gt;inst;</div><div class='hunk'>@@ -1195,7 +1205,7 @@ void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 				opp_inst, opp_cnt,</div><div class='del'>-				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='ctx'> 	else</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='hunk'>@@ -1213,10 +1223,7 @@ void dcn20_blank_pixel_data(</div><div class='ctx'> 	enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;</div><div class='ctx'> 	enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='del'>-	int odm_cnt = 1;</div><div class='del'>-	int h_active = stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right;</div><div class='del'>-	int v_active = stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_bottom + stream-&gt;timing.v_border_top;</div><div class='del'>-	int odm_slice_width, last_odm_slice_width, offset = 0;</div><div class='add'>+	struct rect odm_slice_src;</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;link-&gt;test_pattern_enabled)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1224,11 +1231,6 @@ void dcn20_blank_pixel_data(</div><div class='ctx'> 	/* get opp dpg blank color */</div><div class='ctx'> 	color_space_to_black_color(dc, color_space, &amp;black_color);</div><div class='ctx'> </div><div class='del'>-	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='del'>-		odm_cnt++;</div><div class='del'>-	odm_slice_width = h_active / odm_cnt;</div><div class='del'>-	last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1);</div><div class='del'>-</div><div class='ctx'> 	if (blank) {</div><div class='ctx'> 		dc-&gt;hwss.set_abm_immediate_disable(pipe_ctx);</div><div class='ctx'> </div><div class='hunk'>@@ -1243,28 +1245,29 @@ void dcn20_blank_pixel_data(</div><div class='ctx'> 	odm_pipe = pipe_ctx;</div><div class='ctx'> </div><div class='ctx'> 	while (odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+		odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe);</div><div class='ctx'> 		dc-&gt;hwss.set_disp_pattern_generator(dc,</div><div class='ctx'> 				odm_pipe,</div><div class='ctx'> 				test_pattern,</div><div class='ctx'> 				test_pattern_color_space,</div><div class='ctx'> 				stream-&gt;timing.display_color_depth,</div><div class='ctx'> 				&amp;black_color,</div><div class='del'>-				odm_slice_width,</div><div class='del'>-				v_active,</div><div class='del'>-				offset);</div><div class='del'>-		offset += odm_slice_width;</div><div class='add'>+				odm_slice_src.width,</div><div class='add'>+				odm_slice_src.height,</div><div class='add'>+				odm_slice_src.x);</div><div class='ctx'> 		odm_pipe = odm_pipe-&gt;next_odm_pipe;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe);</div><div class='ctx'> 	dc-&gt;hwss.set_disp_pattern_generator(dc,</div><div class='ctx'> 			odm_pipe,</div><div class='ctx'> 			test_pattern,</div><div class='ctx'> 			test_pattern_color_space,</div><div class='ctx'> 			stream-&gt;timing.display_color_depth,</div><div class='ctx'> 			&amp;black_color,</div><div class='del'>-			last_odm_slice_width,</div><div class='del'>-			v_active,</div><div class='del'>-			offset);</div><div class='add'>+			odm_slice_src.width,</div><div class='add'>+			odm_slice_src.height,</div><div class='add'>+			odm_slice_src.x);</div><div class='ctx'> </div><div class='ctx'> 	if (!blank)</div><div class='ctx'> 		if (stream_res-&gt;abm) {</div><div class='hunk'>@@ -1278,14 +1281,18 @@ static void dcn20_power_on_plane_resources(</div><div class='ctx'> 	struct dce_hwseq *hws,</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='add'>+	uint32_t org_ip_request_cntl = 0;</div><div class='add'>+</div><div class='ctx'> 	DC_LOGGER_INIT(hws-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	if (hws-&gt;funcs.dpp_root_clock_control)</div><div class='ctx'> 		hws-&gt;funcs.dpp_root_clock_control(hws, pipe_ctx-&gt;plane_res.dpp-&gt;inst, true);</div><div class='ctx'> </div><div class='ctx'> 	if (REG(DC_IP_REQUEST_CNTL)) {</div><div class='del'>-		REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='del'>-				IP_REQUEST_EN, 1);</div><div class='add'>+		REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='add'>+		if (org_ip_request_cntl == 0)</div><div class='add'>+			REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='add'>+					IP_REQUEST_EN, 1);</div><div class='ctx'> </div><div class='ctx'> 		if (hws-&gt;funcs.dpp_pg_control)</div><div class='ctx'> 			hws-&gt;funcs.dpp_pg_control(hws, pipe_ctx-&gt;plane_res.dpp-&gt;inst, true);</div><div class='hunk'>@@ -1293,14 +1300,16 @@ static void dcn20_power_on_plane_resources(</div><div class='ctx'> 		if (hws-&gt;funcs.hubp_pg_control)</div><div class='ctx'> 			hws-&gt;funcs.hubp_pg_control(hws, pipe_ctx-&gt;plane_res.hubp-&gt;inst, true);</div><div class='ctx'> </div><div class='del'>-		REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='del'>-				IP_REQUEST_EN, 0);</div><div class='add'>+		if (org_ip_request_cntl == 0)</div><div class='add'>+			REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='add'>+					IP_REQUEST_EN, 0);</div><div class='add'>+</div><div class='ctx'> 		DC_LOG_DEBUG(</div><div class='ctx'> 				"Un-gated front end for pipe %d\n", pipe_ctx-&gt;plane_res.hubp-&gt;inst);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			       struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	//if (dc-&gt;debug.sanity_checks) {</div><div class='hunk'>@@ -1448,7 +1457,7 @@ void dcn20_pipe_control_lock(</div><div class='ctx'> 		!flip_immediate)</div><div class='ctx'> 	    dcn20_setup_gsl_group_as_lock(dc, pipe, false);</div><div class='ctx'> </div><div class='del'>-	if (pipe-&gt;stream &amp;&amp; should_use_dmub_lock(pipe-&gt;stream-&gt;link)) {</div><div class='add'>+	if (pipe-&gt;stream &amp;&amp; should_use_dmub_inbox1_lock(dc, pipe-&gt;stream-&gt;link)) {</div><div class='ctx'> 		union dmub_hw_lock_flags hw_locks = { 0 };</div><div class='ctx'> 		struct dmub_hw_lock_inst_flags inst_flags = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -1470,12 +1479,16 @@ void dcn20_pipe_control_lock(</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (lock)</div><div class='ctx'> 			pipe-&gt;stream_res.tg-&gt;funcs-&gt;lock(pipe-&gt;stream_res.tg);</div><div class='del'>-		else</div><div class='del'>-			pipe-&gt;stream_res.tg-&gt;funcs-&gt;unlock(pipe-&gt;stream_res.tg);</div><div class='add'>+		else {</div><div class='add'>+			if (dc-&gt;hwseq-&gt;funcs.perform_3dlut_wa_unlock)</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.perform_3dlut_wa_unlock(pipe);</div><div class='add'>+			else</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;funcs-&gt;unlock(pipe-&gt;stream_res.tg);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn20_detect_pipe_changes(struct dc_state *old_state,</div><div class='add'>+void dcn20_detect_pipe_changes(struct dc_state *old_state,</div><div class='ctx'> 		struct dc_state *new_state,</div><div class='ctx'> 		struct pipe_ctx *old_pipe,</div><div class='ctx'> 		struct pipe_ctx *new_pipe)</div><div class='hunk'>@@ -1663,7 +1676,7 @@ static void dcn20_detect_pipe_changes(struct dc_state *old_state,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn20_update_dchubp_dpp(</div><div class='add'>+void dcn20_update_dchubp_dpp(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct dc_state *context)</div><div class='hunk'>@@ -1686,25 +1699,41 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.</div><div class='ctx'> 	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG</div><div class='ctx'> 	 */</div><div class='add'>+</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.hubp_rq_dlg_ttu) {</div><div class='ctx'> 		hubp-&gt;funcs-&gt;hubp_vtg_sel(hubp, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='ctx'> </div><div class='del'>-		hubp-&gt;funcs-&gt;hubp_setup(</div><div class='del'>-			hubp,</div><div class='del'>-			&amp;pipe_ctx-&gt;dlg_regs,</div><div class='del'>-			&amp;pipe_ctx-&gt;ttu_regs,</div><div class='del'>-			&amp;pipe_ctx-&gt;rq_regs,</div><div class='del'>-			&amp;pipe_ctx-&gt;pipe_dlg_param);</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_setup2) {</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_setup2(</div><div class='add'>+				hubp,</div><div class='add'>+				&amp;pipe_ctx-&gt;hubp_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;global_sync,</div><div class='add'>+				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+		} else {</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_setup(</div><div class='add'>+				hubp,</div><div class='add'>+				&amp;pipe_ctx-&gt;dlg_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;ttu_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;rq_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;pipe_dlg_param);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.unbounded_req &amp;&amp; hubp-&gt;funcs-&gt;set_unbounded_requesting)</div><div class='ctx'> 		hubp-&gt;funcs-&gt;set_unbounded_requesting(hubp, pipe_ctx-&gt;unbounded_req);</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;update_flags.bits.hubp_interdependent)</div><div class='del'>-		hubp-&gt;funcs-&gt;hubp_setup_interdependent(</div><div class='del'>-			hubp,</div><div class='del'>-			&amp;pipe_ctx-&gt;dlg_regs,</div><div class='del'>-			&amp;pipe_ctx-&gt;ttu_regs);</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.hubp_interdependent) {</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_setup_interdependent2) {</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_setup_interdependent2(</div><div class='add'>+				hubp,</div><div class='add'>+				&amp;pipe_ctx-&gt;hubp_regs);</div><div class='add'>+		} else {</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_setup_interdependent(</div><div class='add'>+				hubp,</div><div class='add'>+				&amp;pipe_ctx-&gt;dlg_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;ttu_regs);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='ctx'> 			pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='hunk'>@@ -1712,7 +1741,7 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 			plane_state-&gt;update_flags.bits.input_csc_change ||</div><div class='ctx'> 			plane_state-&gt;update_flags.bits.color_space_change ||</div><div class='ctx'> 			plane_state-&gt;update_flags.bits.coeff_reduction_change) {</div><div class='del'>-		struct dc_bias_and_scale bns_params = {0};</div><div class='add'>+		struct dc_bias_and_scale bns_params = plane_state-&gt;bias_and_scale;</div><div class='ctx'> </div><div class='ctx'> 		// program the input csc</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_setup(dpp,</div><div class='hunk'>@@ -1722,9 +1751,13 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 				plane_state-&gt;color_space,</div><div class='ctx'> 				NULL);</div><div class='ctx'> </div><div class='add'>+		if (dpp-&gt;funcs-&gt;set_cursor_matrix) {</div><div class='add'>+			dpp-&gt;funcs-&gt;set_cursor_matrix(dpp,</div><div class='add'>+				plane_state-&gt;color_space,</div><div class='add'>+				plane_state-&gt;cursor_csc_color_matrix);</div><div class='add'>+		}</div><div class='ctx'> 		if (dpp-&gt;funcs-&gt;dpp_program_bias_and_scale) {</div><div class='ctx'> 			//TODO :for CNVC set scale and bias registers if necessary</div><div class='del'>-			build_prescale_params(&amp;bns_params, plane_state);</div><div class='ctx'> 			dpp-&gt;funcs-&gt;dpp_program_bias_and_scale(dpp, &amp;bns_params);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1740,7 +1773,6 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.scaler ||</div><div class='ctx'> 			plane_state-&gt;update_flags.bits.scaling_change ||</div><div class='ctx'> 			plane_state-&gt;update_flags.bits.position_change ||</div><div class='del'>-			plane_state-&gt;update_flags.bits.clip_size_change ||</div><div class='ctx'> 			plane_state-&gt;update_flags.bits.per_pixel_alpha_change ||</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;update_flags.bits.scaling) {</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.scl_data.lb_params.alpha_en = pipe_ctx-&gt;plane_state-&gt;per_pixel_alpha;</div><div class='hunk'>@@ -1753,7 +1785,6 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.viewport ||</div><div class='ctx'> 			(context == dc-&gt;current_state &amp;&amp; plane_state-&gt;update_flags.bits.position_change) ||</div><div class='ctx'> 			(context == dc-&gt;current_state &amp;&amp; plane_state-&gt;update_flags.bits.scaling_change) ||</div><div class='del'>-			(context == dc-&gt;current_state &amp;&amp; plane_state-&gt;update_flags.bits.clip_size_change) ||</div><div class='ctx'> 			(context == dc-&gt;current_state &amp;&amp; pipe_ctx-&gt;stream-&gt;update_flags.bits.scaling)) {</div><div class='ctx'> </div><div class='ctx'> 		hubp-&gt;funcs-&gt;mem_program_viewport(</div><div class='hunk'>@@ -1763,12 +1794,18 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 		viewport_changed = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (hubp-&gt;funcs-&gt;hubp_program_mcache_id_and_split_coordinate)</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_program_mcache_id_and_split_coordinate(hubp, &amp;pipe_ctx-&gt;mcache_regs);</div><div class='add'>+</div><div class='ctx'> 	/* Any updates are handled in dc interface, just need to apply existing for plane enable */</div><div class='ctx'> 	if ((pipe_ctx-&gt;update_flags.bits.enable || pipe_ctx-&gt;update_flags.bits.opp_changed ||</div><div class='ctx'> 			pipe_ctx-&gt;update_flags.bits.scaler || viewport_changed == true) &amp;&amp;</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;cursor_attributes.address.quad_part != 0) {</div><div class='del'>-		dc-&gt;hwss.set_cursor_position(pipe_ctx);</div><div class='add'>+		if (dc-&gt;hwss.abort_cursor_offload_update)</div><div class='add'>+			dc-&gt;hwss.abort_cursor_offload_update(dc, pipe_ctx);</div><div class='add'>+</div><div class='ctx'> 		dc-&gt;hwss.set_cursor_attribute(pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.set_cursor_position(pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		if (dc-&gt;hwss.set_cursor_sdr_white_level)</div><div class='ctx'> 			dc-&gt;hwss.set_cursor_sdr_white_level(pipe_ctx);</div><div class='hunk'>@@ -1830,18 +1867,17 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 			params.subvp_save_surf_addr.subvp_index = pipe_ctx-&gt;subvp_index;</div><div class='ctx'> 			hwss_subvp_save_surf_addr(&amp;params);</div><div class='ctx'> 		}</div><div class='del'>-		hws-&gt;funcs.update_plane_addr(dc, pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.update_plane_addr(dc, pipe_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.enable)</div><div class='ctx'> 		hubp-&gt;funcs-&gt;set_blank(hubp, false);</div><div class='ctx'> 	/* If the stream paired with this plane is phantom, the plane is also phantom */</div><div class='del'>-	if (pipe_ctx-&gt;stream &amp;&amp; pipe_mall_type == SUBVP_PHANTOM</div><div class='del'>-			&amp;&amp; hubp-&gt;funcs-&gt;phantom_hubp_post_enable)</div><div class='add'>+	if (pipe_mall_type == SUBVP_PHANTOM &amp;&amp; hubp-&gt;funcs-&gt;phantom_hubp_post_enable)</div><div class='ctx'> 		hubp-&gt;funcs-&gt;phantom_hubp_post_enable(hubp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)</div><div class='add'>+static int dcn20_calculate_vready_offset_for_group(struct pipe_ctx *pipe)</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *other_pipe;</div><div class='ctx'> 	int vready_offset = pipe-&gt;pipe_dlg_param.vready_offset;</div><div class='hunk'>@@ -1867,6 +1903,30 @@ static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)</div><div class='ctx'> 	return vready_offset;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dcn20_program_tg(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct dce_hwseq *hws)</div><div class='add'>+{</div><div class='add'>+	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_global_sync(</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg,</div><div class='add'>+		dcn20_calculate_vready_offset_for_group(pipe_ctx),</div><div class='add'>+		pipe_ctx-&gt;pipe_dlg_param.vstartup_start,</div><div class='add'>+		pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='add'>+		pipe_ctx-&gt;pipe_dlg_param.vupdate_width,</div><div class='add'>+		pipe_ctx-&gt;pipe_dlg_param.pstate_keepout);</div><div class='add'>+</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, true);</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.setup_vupdate_interrupt)</div><div class='add'>+		hws-&gt;funcs.setup_vupdate_interrupt(dc, pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dcn20_program_pipe(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='hunk'>@@ -1877,32 +1937,17 @@ static void dcn20_program_pipe(</div><div class='ctx'> 	/* Only need to unblank on top pipe */</div><div class='ctx'> 	if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {</div><div class='ctx'> 		if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='del'>-				pipe_ctx-&gt;update_flags.bits.odm ||</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;update_flags.bits.abm_level)</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.odm ||</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;update_flags.bits.abm_level)</div><div class='ctx'> 			hws-&gt;funcs.blank_pixel_data(dc, pipe_ctx,</div><div class='del'>-					!pipe_ctx-&gt;plane_state ||</div><div class='del'>-					!pipe_ctx-&gt;plane_state-&gt;visible);</div><div class='add'>+				!pipe_ctx-&gt;plane_state ||</div><div class='add'>+				!pipe_ctx-&gt;plane_state-&gt;visible);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Only update TG on top pipe */</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.global_sync &amp;&amp; !pipe_ctx-&gt;top_pipe</div><div class='del'>-			&amp;&amp; !pipe_ctx-&gt;prev_odm_pipe) {</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_global_sync(</div><div class='del'>-				pipe_ctx-&gt;stream_res.tg,</div><div class='del'>-				calculate_vready_offset_for_group(pipe_ctx),</div><div class='del'>-				pipe_ctx-&gt;pipe_dlg_param.vstartup_start,</div><div class='del'>-				pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='del'>-				pipe_ctx-&gt;pipe_dlg_param.vupdate_width);</div><div class='del'>-</div><div class='del'>-		if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='del'>-</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='del'>-				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, true);</div><div class='del'>-</div><div class='del'>-		if (hws-&gt;funcs.setup_vupdate_interrupt)</div><div class='del'>-			hws-&gt;funcs.setup_vupdate_interrupt(dc, pipe_ctx);</div><div class='del'>-	}</div><div class='add'>+		&amp;&amp; !pipe_ctx-&gt;prev_odm_pipe)</div><div class='add'>+		dcn20_program_tg(dc, pipe_ctx, context, hws);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.odm)</div><div class='ctx'> 		hws-&gt;funcs.update_odm(dc, context, pipe_ctx);</div><div class='hunk'>@@ -1917,21 +1962,30 @@ static void dcn20_program_pipe(</div><div class='ctx'> 			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_wm_propagate_to_pipes(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size &amp;&amp; pipe_ctx-&gt;update_flags.bits.det_size)</div><div class='del'>-		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size(</div><div class='del'>-			dc-&gt;res_pool-&gt;hubbub, pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;det_buffer_size_kb);</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.det_size) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;det_buffer_size_kb);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;hubp_regs.det_size);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;update_flags.raw || pipe_ctx-&gt;plane_state-&gt;update_flags.raw || pipe_ctx-&gt;stream-&gt;update_flags.raw)</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; (pipe_ctx-&gt;update_flags.raw ||</div><div class='add'>+	    pipe_ctx-&gt;plane_state-&gt;update_flags.raw ||</div><div class='add'>+	    pipe_ctx-&gt;stream-&gt;update_flags.raw))</div><div class='ctx'> 		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;update_flags.bits.enable</div><div class='del'>-			|| pipe_ctx-&gt;plane_state-&gt;update_flags.bits.hdr_mult)</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+		pipe_ctx-&gt;plane_state-&gt;update_flags.bits.hdr_mult))</div><div class='ctx'> 		hws-&gt;funcs.set_hdr_multiplier(pipe_ctx);</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='del'>-	    pipe_ctx-&gt;plane_state-&gt;update_flags.bits.in_transfer_func_change ||</div><div class='del'>-	    pipe_ctx-&gt;plane_state-&gt;update_flags.bits.gamma_change ||</div><div class='del'>-	    pipe_ctx-&gt;plane_state-&gt;update_flags.bits.lut_3d)</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp;</div><div class='add'>+		(pipe_ctx-&gt;plane_state-&gt;update_flags.bits.in_transfer_func_change ||</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.gamma_change ||</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.lut_3d ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.enable))</div><div class='ctx'> 		hws-&gt;funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx-&gt;plane_state);</div><div class='ctx'> </div><div class='ctx'> 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish</div><div class='hunk'>@@ -1939,9 +1993,8 @@ static void dcn20_program_pipe(</div><div class='ctx'> 	 * updating on slave planes</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='del'>-			pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='del'>-			pipe_ctx-&gt;stream-&gt;update_flags.bits.out_tf ||</div><div class='del'>-			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.output_tf_change)</div><div class='add'>+	    pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+	    pipe_ctx-&gt;stream-&gt;update_flags.bits.out_tf)</div><div class='ctx'> 		hws-&gt;funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 	/* If the pipe has been enabled or has a different opp, we</div><div class='hunk'>@@ -1950,7 +2003,7 @@ static void dcn20_program_pipe(</div><div class='ctx'> 	 * causes a different pipe to be chosen to odm combine with.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.enable</div><div class='del'>-	    || pipe_ctx-&gt;update_flags.bits.opp_changed) {</div><div class='add'>+		|| pipe_ctx-&gt;update_flags.bits.opp_changed) {</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_set_dyn_expansion(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.opp,</div><div class='hunk'>@@ -1965,7 +2018,7 @@ static void dcn20_program_pipe(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set ABM pipe after other pipe configurations done */</div><div class='del'>-	if (pipe_ctx-&gt;plane_state-&gt;visible) {</div><div class='add'>+	if ((pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_state-&gt;visible)) {</div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.abm) {</div><div class='ctx'> 			dc-&gt;hwss.set_pipe(pipe_ctx);</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.abm-&gt;funcs-&gt;set_abm_level(pipe_ctx-&gt;stream_res.abm,</div><div class='hunk'>@@ -1980,14 +2033,14 @@ static void dcn20_program_pipe(</div><div class='ctx'> 		memset(&amp;params, 0, sizeof(params));</div><div class='ctx'> 		odm_opp-&gt;funcs-&gt;opp_program_bit_depth_reduction(odm_opp, &amp;params);</div><div class='ctx'> 		dc-&gt;hwss.set_disp_pattern_generator(dc,</div><div class='del'>-				pipe_ctx,</div><div class='del'>-				pipe_ctx-&gt;stream_res.test_pattern_params.test_pattern,</div><div class='del'>-				pipe_ctx-&gt;stream_res.test_pattern_params.color_space,</div><div class='del'>-				pipe_ctx-&gt;stream_res.test_pattern_params.color_depth,</div><div class='del'>-				NULL,</div><div class='del'>-				pipe_ctx-&gt;stream_res.test_pattern_params.width,</div><div class='del'>-				pipe_ctx-&gt;stream_res.test_pattern_params.height,</div><div class='del'>-				pipe_ctx-&gt;stream_res.test_pattern_params.offset);</div><div class='add'>+			pipe_ctx,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.test_pattern,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.color_space,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.color_depth,</div><div class='add'>+			NULL,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.width,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.height,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.offset);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1996,11 +2049,12 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 		struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='del'>-	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> 	unsigned int prev_hubp_count = 0;</div><div class='ctx'> 	unsigned int hubp_count = 0;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	if (resource_is_pipe_topology_changed(dc-&gt;current_state, context))</div><div class='ctx'> 		resource_log_pipe_topology_update(dc, context);</div><div class='hunk'>@@ -2009,11 +2063,11 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-			if (!pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe &amp;&amp; pipe-&gt;plane_state) {</div><div class='add'>+			if (pipe-&gt;plane_state) {</div><div class='ctx'> 				ASSERT(!pipe-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='ctx'> 				/*turn off triple buffer for full update*/</div><div class='ctx'> 				dc-&gt;hwss.program_triplebuffer(</div><div class='del'>-						dc, pipe, pipe-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='add'>+					dc, pipe, pipe-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2028,14 +2082,14 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 	if (prev_hubp_count == 0 &amp;&amp; hubp_count &gt; 0) {</div><div class='ctx'> 		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='ctx'> 			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='del'>-					dc-&gt;res_pool-&gt;hubbub, true, false);</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, true, false);</div><div class='ctx'> 		udelay(500);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set pipe update flags and lock pipes */</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		dcn20_detect_pipe_changes(dc-&gt;current_state, context, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i],</div><div class='del'>-				&amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+			&amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> </div><div class='ctx'> 	/* When disabling phantom pipes, turn on phantom OTG first (so we can get double</div><div class='ctx'> 	 * buffer updates properly)</div><div class='hunk'>@@ -2043,19 +2097,16 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct dc_stream_state *stream = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream;</div><div class='ctx'> </div><div class='add'>+		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable &amp;&amp; stream &amp;&amp;</div><div class='del'>-				dc_state_get_pipe_subvp_type(dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {</div><div class='add'>+			dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			struct timing_generator *tg = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream_res.tg;</div><div class='ctx'> </div><div class='ctx'> 			if (tg-&gt;funcs-&gt;enable_crtc) {</div><div class='del'>-				if (dc-&gt;hwss.blank_phantom) {</div><div class='del'>-					int main_pipe_width, main_pipe_height;</div><div class='del'>-					struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(dc-&gt;current_state, dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream);</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.blank_pixel_data)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.blank_pixel_data(dc, pipe, true);</div><div class='ctx'> </div><div class='del'>-					main_pipe_width = phantom_stream-&gt;dst.width;</div><div class='del'>-					main_pipe_height = phantom_stream-&gt;dst.height;</div><div class='del'>-					dc-&gt;hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);</div><div class='del'>-				}</div><div class='ctx'> 				tg-&gt;funcs-&gt;enable_crtc(tg);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2063,15 +2114,15 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 	/* OTG blank before disabling all front ends */</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable</div><div class='del'>-				&amp;&amp; !context-&gt;res_ctx.pipe_ctx[i].top_pipe</div><div class='del'>-				&amp;&amp; !context-&gt;res_ctx.pipe_ctx[i].prev_odm_pipe</div><div class='del'>-				&amp;&amp; context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='add'>+			&amp;&amp; !context-&gt;res_ctx.pipe_ctx[i].top_pipe</div><div class='add'>+			&amp;&amp; !context-&gt;res_ctx.pipe_ctx[i].prev_odm_pipe</div><div class='add'>+			&amp;&amp; context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='ctx'> 			hws-&gt;funcs.blank_pixel_data(dc, &amp;context-&gt;res_ctx.pipe_ctx[i], true);</div><div class='ctx'> </div><div class='ctx'> 	/* Disconnect mpcc */</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable</div><div class='del'>-				|| context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {</div><div class='add'>+			|| context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {</div><div class='ctx'> 			struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='ctx'> </div><div class='ctx'> 			/* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom</div><div class='hunk'>@@ -2080,10 +2131,19 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 			 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with</div><div class='ctx'> 			 * DET allocation.</div><div class='ctx'> 			 */</div><div class='del'>-			if (hubbub-&gt;funcs-&gt;program_det_size &amp;&amp; (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable ||</div><div class='del'>-					(context-&gt;res_ctx.pipe_ctx[i].plane_state &amp;&amp; dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM)))</div><div class='del'>-				hubbub-&gt;funcs-&gt;program_det_size(hubbub, dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;inst, 0);</div><div class='del'>-			hws-&gt;funcs.plane_atomic_disconnect(dc, dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+			if ((context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable ||</div><div class='add'>+				(context-&gt;res_ctx.pipe_ctx[i].plane_state &amp;&amp;</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i])</div><div class='add'>+				== SUBVP_PHANTOM))) {</div><div class='add'>+				if (hubbub-&gt;funcs-&gt;program_det_size)</div><div class='add'>+					hubbub-&gt;funcs-&gt;program_det_size(hubbub,</div><div class='add'>+						dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;inst, 0);</div><div class='add'>+				if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+					dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments(</div><div class='add'>+						hubbub, dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;inst, 0);</div><div class='add'>+			}</div><div class='add'>+			hws-&gt;funcs.plane_atomic_disconnect(dc, dc-&gt;current_state,</div><div class='add'>+				&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> 			DC_LOG_DC("Reset mpcc for pipe %d\n", dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].pipe_idx);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -2091,9 +2151,9 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='del'>-				!resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='del'>-				pipe-&gt;update_flags.bits.odm &amp;&amp;</div><div class='del'>-				hws-&gt;funcs.update_odm)</div><div class='add'>+			!resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='add'>+			pipe-&gt;update_flags.bits.odm &amp;&amp;</div><div class='add'>+			hws-&gt;funcs.update_odm)</div><div class='ctx'> 			hws-&gt;funcs.update_odm(dc, context, pipe);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2111,25 +2171,28 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 				else {</div><div class='ctx'> 					/* Don't program phantom pipes in the regular front end programming sequence.</div><div class='ctx'> 					 * There is an MPO transition case where a pipe being used by a video plane is</div><div class='del'>-					 * transitioned directly to be a phantom pipe when closing the MPO video. However</div><div class='del'>-					 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away),</div><div class='del'>-					 * but the MPO still exists until the double buffered update of the main pipe so we</div><div class='del'>-					 * will get a frame of underflow if the phantom pipe is programmed here.</div><div class='add'>+					 * transitioned directly to be a phantom pipe when closing the MPO video.</div><div class='add'>+					 * However the phantom pipe will program a new HUBP_VTG_SEL (update takes place</div><div class='add'>+					 * right away) but the MPO still exists until the double buffered update of the</div><div class='add'>+					 * main pipe so we will get a frame of underflow if the phantom pipe is</div><div class='add'>+					 * programmed here.</div><div class='ctx'> 					 */</div><div class='del'>-					if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)</div><div class='add'>+					if (pipe-&gt;stream &amp;&amp;</div><div class='add'>+						dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)</div><div class='ctx'> 						dcn20_program_pipe(dc, pipe, context);</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='ctx'> 				pipe = pipe-&gt;bottom_pipe;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='ctx'> 		/* Program secondary blending tree and writeback pipes */</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		if (!pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe</div><div class='del'>-				&amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;num_wb_info &gt; 0</div><div class='del'>-				&amp;&amp; (pipe-&gt;update_flags.raw || (pipe-&gt;plane_state &amp;&amp; pipe-&gt;plane_state-&gt;update_flags.raw)</div><div class='del'>-					|| pipe-&gt;stream-&gt;update_flags.raw)</div><div class='del'>-				&amp;&amp; hws-&gt;funcs.program_all_writeback_pipes_in_tree)</div><div class='add'>+			&amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;num_wb_info &gt; 0</div><div class='add'>+			&amp;&amp; (pipe-&gt;update_flags.raw || (pipe-&gt;plane_state &amp;&amp; pipe-&gt;plane_state-&gt;update_flags.raw)</div><div class='add'>+				|| pipe-&gt;stream-&gt;update_flags.raw)</div><div class='add'>+			&amp;&amp; hws-&gt;funcs.program_all_writeback_pipes_in_tree)</div><div class='ctx'> 			hws-&gt;funcs.program_all_writeback_pipes_in_tree(dc, pipe-&gt;stream, context);</div><div class='ctx'> </div><div class='ctx'> 		/* Avoid underflow by check of pipe line read when adding 2nd plane. */</div><div class='hunk'>@@ -2144,14 +2207,58 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* post_unlock_reset_opp - the function wait for corresponding double</div><div class='add'>+ * buffered pending status clear and reset opp head pipe's none double buffered</div><div class='add'>+ * registers to their initial state.</div><div class='add'>+ */</div><div class='add'>+void dcn20_post_unlock_reset_opp(struct dc *dc,</div><div class='add'>+		struct pipe_ctx *opp_head)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = opp_head-&gt;stream_res.dsc;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * wait for all DPP pipes in current mpc blending tree completes double</div><div class='add'>+	 * buffered disconnection before resetting OPP</div><div class='add'>+	 */</div><div class='add'>+	dc-&gt;hwss.wait_for_mpcc_disconnect(dc, dc-&gt;res_pool, opp_head);</div><div class='add'>+</div><div class='add'>+	if (dsc) {</div><div class='add'>+		bool is_dsc_ungated = false;</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;hwseq-&gt;funcs.dsc_pg_status)</div><div class='add'>+			is_dsc_ungated = dc-&gt;hwseq-&gt;funcs.dsc_pg_status(dc-&gt;hwseq, dsc-&gt;inst);</div><div class='add'>+</div><div class='add'>+		if (is_dsc_ungated) {</div><div class='add'>+			/*</div><div class='add'>+			 * seamless update specific where we will postpone non</div><div class='add'>+			 * double buffered DSCCLK disable logic in post unlock</div><div class='add'>+			 * sequence after DSC is disconnected from OPP but not</div><div class='add'>+			 * yet power gated.</div><div class='add'>+			 */</div><div class='add'>+			dsc-&gt;funcs-&gt;dsc_wait_disconnect_pending_clear(dsc);</div><div class='add'>+			dsc-&gt;funcs-&gt;dsc_disable(dsc);</div><div class='add'>+			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, dsc-&gt;inst);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_US = 100000;</div><div class='add'>+	// Timeout for pipe enable</div><div class='add'>+	unsigned int timeout_us = 100000;</div><div class='ctx'> 	unsigned int polling_interval_us = 1;</div><div class='ctx'> 	struct dce_hwseq *hwseq = dc-&gt;hwseq;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		if (resource_is_pipe_type(&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i], OPP_HEAD) &amp;&amp;</div><div class='add'>+			!resource_is_pipe_type(&amp;context-&gt;res_ctx.pipe_ctx[i], OPP_HEAD))</div><div class='add'>+			dcn20_post_unlock_reset_opp(dc,</div><div class='add'>+				&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable)</div><div class='hunk'>@@ -2167,18 +2274,41 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		// Don't check flip pending on phantom pipes</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; pipe-&gt;update_flags.bits.enable &amp;&amp;</div><div class='del'>-				dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {</div><div class='ctx'> 			struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='ctx'> 			int j = 0;</div><div class='del'>-			for (j = 0; j &lt; TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us</div><div class='del'>-					&amp;&amp; hubp-&gt;funcs-&gt;hubp_is_flip_pending(hubp); j++)</div><div class='add'>+</div><div class='add'>+			for (j = 0; j &lt; timeout_us / polling_interval_us</div><div class='add'>+				&amp;&amp; hubp-&gt;funcs-&gt;hubp_is_flip_pending(hubp); j++)</div><div class='ctx'> 				udelay(polling_interval_us);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		/* When going from a smaller ODM slice count to larger, we must ensure double</div><div class='add'>+		 * buffer update completes before we return to ensure we don't reduce DISPCLK</div><div class='add'>+		 * before we've transitioned to 2:1 or 4:1</div><div class='add'>+		 */</div><div class='add'>+		if (resource_is_pipe_type(old_pipe, OTG_MASTER) &amp;&amp; resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='add'>+			resource_get_odm_slice_count(old_pipe) &lt; resource_get_odm_slice_count(pipe) &amp;&amp;</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {</div><div class='add'>+			int j = 0;</div><div class='add'>+			struct timing_generator *tg = pipe-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+			if (tg-&gt;funcs-&gt;get_optc_double_buffer_pending) {</div><div class='add'>+				for (j = 0; j &lt; timeout_us / polling_interval_us</div><div class='add'>+					&amp;&amp; tg-&gt;funcs-&gt;get_optc_double_buffer_pending(tg); j++)</div><div class='add'>+					udelay(polling_interval_us);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='del'>-				dc-&gt;res_pool-&gt;hubbub, false, false);</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub, false, false);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -2205,14 +2335,17 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!hwseq)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	/* P-State support transitions:</div><div class='del'>-	 * Natural -&gt; FPO: 		P-State disabled in prepare, force disallow anytime is safe</div><div class='del'>-	 * FPO -&gt; Natural: 		Unforce anytime after FW disable is safe (P-State will assert naturally)</div><div class='del'>-	 * Unsupported -&gt; FPO:	P-State enabled in optimize, force disallow anytime is safe</div><div class='del'>-	 * FPO -&gt; Unsupported:	P-State disabled in prepare, unforce disallow anytime is safe</div><div class='del'>-	 * FPO &lt;-&gt; SubVP:		Force disallow is maintained on the FPO / SubVP pipes</div><div class='add'>+	 * Natural -&gt; FPO:      P-State disabled in prepare, force disallow anytime is safe</div><div class='add'>+	 * FPO -&gt; Natural:      Unforce anytime after FW disable is safe (P-State will assert naturally)</div><div class='add'>+	 * Unsupported -&gt; FPO:  P-State enabled in optimize, force disallow anytime is safe</div><div class='add'>+	 * FPO -&gt; Unsupported:  P-State disabled in prepare, unforce disallow anytime is safe</div><div class='add'>+	 * FPO &lt;-&gt; SubVP:       Force disallow is maintained on the FPO / SubVP pipes</div><div class='ctx'> 	 */</div><div class='del'>-	if (hwseq &amp;&amp; hwseq-&gt;funcs.update_force_pstate)</div><div class='add'>+	if (hwseq-&gt;funcs.update_force_pstate)</div><div class='ctx'> 		dc-&gt;hwseq-&gt;funcs.update_force_pstate(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	/* Only program the MALL registers after all the main and phantom pipes</div><div class='hunk'>@@ -2225,12 +2358,11 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 	if (hwseq-&gt;wa.DEGVIDCN21)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;apply_DEDCN21_147_wa(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	/* WA for stutter underflow during MPO transitions when adding 2nd plane */</div><div class='ctx'> 	if (hwseq-&gt;wa.disallow_self_refresh_during_multi_plane_transition) {</div><div class='ctx'> </div><div class='ctx'> 		if (dc-&gt;current_state-&gt;stream_status[0].plane_count == 1 &amp;&amp;</div><div class='del'>-				context-&gt;stream_status[0].plane_count &gt; 1) {</div><div class='add'>+			context-&gt;stream_status[0].plane_count &gt; 1) {</div><div class='ctx'> </div><div class='ctx'> 			struct timing_generator *tg = dc-&gt;res_pool-&gt;timing_generators[0];</div><div class='ctx'> </div><div class='hunk'>@@ -2267,10 +2399,10 @@ void dcn20_prepare_bandwidth(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* program dchubbub watermarks:</div><div class='del'>-	 * For assigning wm_optimized_required, use |= operator since we don't want</div><div class='add'>+	 * For assigning optimized_required, use |= operator since we don't want</div><div class='ctx'> 	 * to clear the value if the optimize has not happened yet</div><div class='ctx'> 	 */</div><div class='del'>-	dc-&gt;wm_optimized_required |= hubbub-&gt;funcs-&gt;program_watermarks(hubbub,</div><div class='add'>+	dc-&gt;optimized_required |= hubbub-&gt;funcs-&gt;program_watermarks(hubbub,</div><div class='ctx'> 					&amp;context-&gt;bw_ctx.bw.dcn.watermarks,</div><div class='ctx'> 					dc-&gt;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000,</div><div class='ctx'> 					false);</div><div class='hunk'>@@ -2283,10 +2415,10 @@ void dcn20_prepare_bandwidth(</div><div class='ctx'> 	if (hubbub-&gt;funcs-&gt;program_compbuf_size) {</div><div class='ctx'> 		if (context-&gt;bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {</div><div class='ctx'> 			compbuf_size_kb = context-&gt;bw_ctx.dml.ip.min_comp_buffer_size_kbytes;</div><div class='del'>-			dc-&gt;wm_optimized_required |= (compbuf_size_kb != dc-&gt;current_state-&gt;bw_ctx.dml.ip.min_comp_buffer_size_kbytes);</div><div class='add'>+			dc-&gt;optimized_required |= (compbuf_size_kb != dc-&gt;current_state-&gt;bw_ctx.dml.ip.min_comp_buffer_size_kbytes);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			compbuf_size_kb = context-&gt;bw_ctx.bw.dcn.compbuf_size_kb;</div><div class='del'>-			dc-&gt;wm_optimized_required |= (compbuf_size_kb != dc-&gt;current_state-&gt;bw_ctx.bw.dcn.compbuf_size_kb);</div><div class='add'>+			dc-&gt;optimized_required |= (compbuf_size_kb != dc-&gt;current_state-&gt;bw_ctx.bw.dcn.compbuf_size_kb);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		hubbub-&gt;funcs-&gt;program_compbuf_size(hubbub, compbuf_size_kb, false);</div><div class='hunk'>@@ -2360,7 +2492,7 @@ bool dcn20_update_bandwidth(</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> </div><div class='ctx'> 	/* recalculate DML parameters */</div><div class='del'>-	if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, false))</div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	/* apply updated bandwidth parameters */</div><div class='hunk'>@@ -2378,10 +2510,11 @@ bool dcn20_update_bandwidth(</div><div class='ctx'> </div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_global_sync(</div><div class='ctx'> 					pipe_ctx-&gt;stream_res.tg,</div><div class='del'>-					calculate_vready_offset_for_group(pipe_ctx),</div><div class='add'>+					dcn20_calculate_vready_offset_for_group(pipe_ctx),</div><div class='ctx'> 					pipe_ctx-&gt;pipe_dlg_param.vstartup_start,</div><div class='ctx'> 					pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='del'>-					pipe_ctx-&gt;pipe_dlg_param.vupdate_width);</div><div class='add'>+					pipe_ctx-&gt;pipe_dlg_param.vupdate_width,</div><div class='add'>+					pipe_ctx-&gt;pipe_dlg_param.pstate_keepout);</div><div class='ctx'> </div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='ctx'> 					pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, false);</div><div class='hunk'>@@ -2451,6 +2584,9 @@ bool dcn20_wait_for_blank_complete(</div><div class='ctx'> {</div><div class='ctx'> 	int counter;</div><div class='ctx'> </div><div class='add'>+	if (!opp)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	for (counter = 0; counter &lt; 1000; counter++) {</div><div class='ctx'> 		if (!opp-&gt;funcs-&gt;dpg_is_pending(opp))</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -2629,8 +2765,11 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='ctx'> 	struct dce_hwseq *hws = link-&gt;dc-&gt;hwseq;</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='add'>+	bool is_two_pixels_per_container =</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing);</div><div class='ctx'> </div><div class='ctx'> 	params.opp_cnt = 1;</div><div class='add'>+</div><div class='ctx'> 	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 		params.opp_cnt++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2645,9 +2784,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.hpo_dp_stream_enc,</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='ctx'> 	} else if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='del'>-		if (optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing) || params.opp_cnt &gt; 1)</div><div class='add'>+		if (is_two_pixels_per_container || params.opp_cnt &gt; 1)</div><div class='ctx'> 			params.timing.pix_clk_100hz /= 2;</div><div class='del'>-		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_odm_combine(</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_odm_combine)</div><div class='add'>+			pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_odm_combine(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.stream_enc, params.opp_cnt &gt; 1);</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_unblank(link, pipe_ctx-&gt;stream_res.stream_enc, &amp;params);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2674,9 +2814,10 @@ void dcn20_reset_back_end_for_pipe(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct dc_state *context)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='ctx'> 	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='ctx'> 	const struct link_hwss *link_hwss = get_link_hwss(link, &amp;pipe_ctx-&gt;link_res);</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+	struct dtbclk_dto_params dto_params = {0};</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.stream_enc == NULL) {</div><div class='hunk'>@@ -2725,9 +2866,7 @@ void dcn20_reset_back_end_for_pipe(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='ctx'> 					pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-					pipe_ctx-&gt;stream_res.tg, NULL);</div><div class='add'>+		set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx-&gt;stream, NULL);</div><div class='ctx'> 		/* TODO - convert symclk_ref_cnts for otg to a bit map to solve</div><div class='ctx'> 		 * the case where the same symclk is shared across multiple otg</div><div class='ctx'> 		 * instances</div><div class='hunk'>@@ -2739,16 +2878,25 @@ void dcn20_reset_back_end_for_pipe(</div><div class='ctx'> 					&amp;pipe_ctx-&gt;link_res, pipe_ctx-&gt;stream-&gt;signal);</div><div class='ctx'> 			link-&gt;phy_state.symclk_state = SYMCLK_OFF_TX_OFF;</div><div class='ctx'> 		}</div><div class='add'>+		if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx) &amp;&amp; dccg</div><div class='add'>+			&amp;&amp; dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_3_5) {</div><div class='add'>+			dto_params.otg_inst = pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='add'>+			dto_params.timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+			if (dccg &amp;&amp; dccg-&gt;funcs-&gt;set_dtbclk_dto)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_dtbclk_dto(dccg, &amp;dto_params);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='del'>-		if (&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i] == pipe_ctx)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-	if (i == dc-&gt;res_pool-&gt;pipe_count)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='add'>+/*</div><div class='add'>+ * In case of a dangling plane, setting this to NULL unconditionally</div><div class='add'>+ * causes failures during reset hw ctx where, if stream is NULL,</div><div class='add'>+ * it is expected that the pipe_ctx pointers to pipes and plane are NULL.</div><div class='add'>+ */</div><div class='ctx'> 	pipe_ctx-&gt;stream = NULL;</div><div class='add'>+	pipe_ctx-&gt;top_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;bottom_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;next_odm_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;prev_odm_pipe = NULL;</div><div class='ctx'> 	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",</div><div class='ctx'> 					pipe_ctx-&gt;pipe_idx, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='ctx'> }</div><div class='hunk'>@@ -2886,16 +3034,12 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='ctx'> 	enum phyd32clk_clock_source phyd32clk;</div><div class='ctx'> 	int dp_hpo_inst;</div><div class='del'>-	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='del'>-	unsigned int k1_div = PIXEL_RATE_DIV_NA;</div><div class='del'>-	unsigned int k2_div = PIXEL_RATE_DIV_NA;</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='del'>-		if (dc-&gt;hwseq-&gt;funcs.setup_hpo_hw_control)</div><div class='del'>-			dc-&gt;hwseq-&gt;funcs.setup_hpo_hw_control(dc-&gt;hwseq, true);</div><div class='del'>-	}</div><div class='add'>+	if (!dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='ctx'> 		dto_params.otg_inst = tg-&gt;inst;</div><div class='hunk'>@@ -2908,20 +3052,23 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		dccg-&gt;funcs-&gt;set_dpstreamclk(dccg, DTBCLK0, tg-&gt;inst, dp_hpo_inst);</div><div class='ctx'> </div><div class='ctx'> 		phyd32clk = get_phyd32clk_src(link);</div><div class='del'>-		dccg-&gt;funcs-&gt;enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);</div><div class='add'>+		if (link-&gt;cur_link_settings.link_rate == LINK_RATE_UNKNOWN) {</div><div class='add'>+			dccg-&gt;funcs-&gt;disable_symclk32_se(dccg, dp_hpo_inst);</div><div class='add'>+		} else {</div><div class='add'>+			dccg-&gt;funcs-&gt;enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (dccg-&gt;funcs-&gt;enable_symclk_se)</div><div class='ctx'> 			dccg-&gt;funcs-&gt;enable_symclk_se(dccg, stream_enc-&gt;stream_enc_inst,</div><div class='ctx'> 						      link_enc-&gt;transmitter - TRANSMITTER_UNIPHY_A);</div><div class='ctx'> 	}</div><div class='del'>-	if (hws-&gt;funcs.calculate_dccg_k1_k2_values &amp;&amp; dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div) {</div><div class='del'>-		hws-&gt;funcs.calculate_dccg_k1_k2_values(pipe_ctx, &amp;k1_div, &amp;k2_div);</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div(</div><div class='ctx'> 			dc-&gt;res_pool-&gt;dccg,</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='del'>-			k1_div, k2_div);</div><div class='del'>-	}</div><div class='add'>+			pipe_ctx-&gt;pixel_rate_divider.div_factor1,</div><div class='add'>+			pipe_ctx-&gt;pixel_rate_divider.div_factor2);</div><div class='ctx'> </div><div class='ctx'> 	link_hwss-&gt;setup_stream_encoder(pipe_ctx);</div><div class='ctx'> </div><div class='hunk'>@@ -2948,9 +3095,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		early_control = lane_count;</div><div class='ctx'> </div><div class='ctx'> 	tg-&gt;funcs-&gt;set_early_control(tg, early_control);</div><div class='del'>-</div><div class='del'>-	if (dc-&gt;hwseq-&gt;funcs.set_pixels_per_cycle)</div><div class='del'>-		dc-&gt;hwseq-&gt;funcs.set_pixels_per_cycle(pipe_ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)</div><div class='hunk'>@@ -2994,7 +3138,8 @@ void dcn20_fpga_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;dccg-&gt;funcs-&gt;dccg_init(res_pool-&gt;dccg);</div><div class='ctx'> </div><div class='ctx'> 	//Enable ability to power gate / don't force power on permanently</div><div class='del'>-	hws-&gt;funcs.enable_power_gating_plane(hws, true);</div><div class='add'>+	if (hws-&gt;funcs.enable_power_gating_plane)</div><div class='add'>+		hws-&gt;funcs.enable_power_gating_plane(hws, true);</div><div class='ctx'> </div><div class='ctx'> 	// Specific to FPGA dccg and registers</div><div class='ctx'> 	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h<br/>index 5c874f7b0683..9d1ad3b29ca5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h</a></div><div class='hunk'>@@ -154,6 +154,21 @@ void dcn20_setup_gsl_group_as_lock(</div><div class='ctx'> 		const struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		bool enable);</div><div class='del'>-</div><div class='add'>+void dcn20_detect_pipe_changes(</div><div class='add'>+		struct dc_state *old_state,</div><div class='add'>+		struct dc_state *new_state,</div><div class='add'>+		struct pipe_ctx *old_pipe,</div><div class='add'>+		struct pipe_ctx *new_pipe);</div><div class='add'>+void dcn20_enable_plane(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+void dcn20_update_dchubp_dpp(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+void dcn20_post_unlock_reset_opp(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *opp_head);</div><div class='ctx'> #endif /* __DC_HWSS_DCN20_H__ */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c<br/>index 884e3e323338..ad253c586ea1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c</a></div><div class='hunk'>@@ -36,6 +36,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -67,6 +68,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {</div><div class='ctx'> 	.setup_stereo = dcn10_setup_stereo,</div><div class='ctx'> 	.set_avmute = dce110_set_avmute,</div><div class='ctx'> 	.log_hw_state = dcn10_log_hw_state,</div><div class='add'>+	.log_color_state = dcn20_log_color_state,</div><div class='ctx'> 	.get_hw_state = dcn10_get_hw_state,</div><div class='ctx'> 	.clear_status_bits = dcn10_clear_status_bits,</div><div class='ctx'> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='hunk'>@@ -104,7 +106,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = {</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn20_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn20_set_input_transfer_func,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c<br/>index d5769f38874f..1635e5a552ad 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c</a></div><div class='hunk'>@@ -95,8 +95,11 @@ static bool gpu_addr_to_uma(struct dce_hwseq *hwseq,</div><div class='ctx'> 	} else if (hwseq-&gt;fb_offset.quad_part &lt;= addr-&gt;quad_part &amp;&amp;</div><div class='ctx'> 			addr-&gt;quad_part &lt;= hwseq-&gt;uma_top.quad_part) {</div><div class='ctx'> 		is_in_uma = true;</div><div class='add'>+	} else if (addr-&gt;quad_part == 0) {</div><div class='add'>+		is_in_uma = false;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		is_in_uma = false;</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='ctx'> 	}</div><div class='ctx'> 	return is_in_uma;</div><div class='ctx'> }</div><div class='hunk'>@@ -167,7 +170,7 @@ void dcn201_init_blank(</div><div class='ctx'> 	struct tg_color black_color = {0};</div><div class='ctx'> 	struct output_pixel_processor *opp = NULL;</div><div class='ctx'> 	uint32_t num_opps, opp_id_src0, opp_id_src1;</div><div class='del'>-	uint32_t otg_active_width, otg_active_height;</div><div class='add'>+	uint32_t otg_active_width = 0, otg_active_height = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* program opp dpg blank color */</div><div class='ctx'> 	color_space = COLOR_SPACE_SRGB;</div><div class='hunk'>@@ -237,7 +240,7 @@ void dcn201_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;ref_clocks.xtalin_clock_inKhz =</div><div class='ctx'> 			dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency;</div><div class='ctx'> </div><div class='del'>-		if (res_pool-&gt;dccg &amp;&amp; res_pool-&gt;hubbub) {</div><div class='add'>+		if (res_pool-&gt;hubbub) {</div><div class='ctx'> 			(res_pool-&gt;dccg-&gt;funcs-&gt;get_dccg_ref_freq)(res_pool-&gt;dccg,</div><div class='ctx'> 					dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency,</div><div class='ctx'> 					&amp;res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz);</div><div class='hunk'>@@ -405,8 +408,7 @@ void dcn201_plane_atomic_disconnect(struct dc *dc,</div><div class='ctx'> 	if (mpcc_removed == false)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (opp != NULL)</div><div class='del'>-		opp-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='add'>+	opp-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;optimized_required = true;</div><div class='ctx'> </div><div class='hunk'>@@ -601,7 +603,7 @@ void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> </div><div class='ctx'> 	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='ctx'> 		/*check whether it is half the rate*/</div><div class='del'>-		if (optc201_is_two_pixels_per_containter(&amp;stream-&gt;timing))</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing))</div><div class='ctx'> 			params.timing.pix_clk_100hz /= 2;</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_unblank(link, pipe_ctx-&gt;stream_res.stream_enc, &amp;params);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c<br/>index a13bf6c9386e..dec57fb4c05c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c</a></div><div class='hunk'>@@ -36,6 +36,7 @@ static const struct hw_sequencer_funcs dcn201_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn201_update_plane_addr,</div><div class='hunk'>@@ -96,7 +97,6 @@ static const struct hw_sequencer_funcs dcn201_funcs = {</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn201_private_funcs = {</div><div class='ctx'> 	.init_pipes = NULL,</div><div class='del'>-	.update_plane_addr = dcn201_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn201_plane_atomic_disconnect,</div><div class='ctx'> 	.program_pipe = dcn10_program_pipe,</div><div class='ctx'> 	.update_mpcc = dcn201_update_mpcc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c<br/>index 7252f5f781f0..e2269211553c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c</a></div><div class='hunk'>@@ -35,7 +35,7 @@</div><div class='ctx'> #include "hw/clk_mgr.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "abm.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -66,7 +66,7 @@ static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *c</div><div class='ctx'> </div><div class='ctx'> int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)</div><div class='ctx'> {</div><div class='del'>-	struct dcn_hubbub_phys_addr_config config;</div><div class='add'>+	struct dcn_hubbub_phys_addr_config config = {0};</div><div class='ctx'> </div><div class='ctx'> 	config.system_aperture.fb_top = pa_config-&gt;system_aperture.fb_top;</div><div class='ctx'> 	config.system_aperture.fb_offset = pa_config-&gt;system_aperture.fb_offset;</div><div class='hunk'>@@ -137,12 +137,12 @@ void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;dpms_off = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,</div><div class='add'>+bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,</div><div class='ctx'> 		uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct dc_context *dc = abm-&gt;ctx;</div><div class='del'>-	uint32_t ramping_boundary = 0xFFFF;</div><div class='add'>+	uint8_t ramping_boundary = 0xFF;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;</div><div class='hunk'>@@ -183,6 +183,12 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct panel_cntl *panel_cntl = pipe_ctx-&gt;stream-&gt;link-&gt;panel_cntl;</div><div class='ctx'> 	struct dmcu *dmcu = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dmcu;</div><div class='ctx'> </div><div class='add'>+	// make a short term w/a for an issue that backlight ramping unexpectedly paused in the middle,</div><div class='add'>+	// will decouple backlight from ABM and redefine DMUB interface, then this w/a could be removed</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;abm_level == 0 || pipe_ctx-&gt;stream-&gt;abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dmcu) {</div><div class='ctx'> 		dce110_set_abm_immediate_disable(pipe_ctx);</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -193,7 +199,7 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 			abm-&gt;funcs-&gt;set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,</div><div class='ctx'> 					panel_cntl-&gt;inst, panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 		} else {</div><div class='del'>-				dmub_abm_set_pipe(abm,</div><div class='add'>+			dcn21_dmub_abm_set_pipe(abm,</div><div class='ctx'> 						otg_inst,</div><div class='ctx'> 						SET_ABM_PIPE_IMMEDIATELY_DISABLE,</div><div class='ctx'> 						panel_cntl-&gt;inst,</div><div class='hunk'>@@ -228,7 +234,7 @@ void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 					panel_cntl-&gt;inst,</div><div class='ctx'> 					panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 	} else {</div><div class='del'>-		dmub_abm_set_pipe(abm, otg_inst,</div><div class='add'>+			dcn21_dmub_abm_set_pipe(abm, otg_inst,</div><div class='ctx'> 				  SET_ABM_PIPE_NORMAL,</div><div class='ctx'> 				  panel_cntl-&gt;inst,</div><div class='ctx'> 				  panel_cntl-&gt;pwrseq_inst);</div><div class='hunk'>@@ -236,14 +242,15 @@ void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp)</div><div class='add'>+	struct set_backlight_level_params *backlight_level_params)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *dc = pipe_ctx-&gt;stream-&gt;ctx;</div><div class='ctx'> 	struct abm *abm = pipe_ctx-&gt;stream_res.abm;</div><div class='ctx'> 	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='ctx'> 	struct panel_cntl *panel_cntl = pipe_ctx-&gt;stream-&gt;link-&gt;panel_cntl;</div><div class='ctx'> 	uint32_t otg_inst;</div><div class='add'>+	uint32_t backlight_pwm_u16_16 = backlight_level_params-&gt;backlight_pwm_u16_16;</div><div class='add'>+	uint32_t frame_ramp = backlight_level_params-&gt;frame_ramp;</div><div class='ctx'> </div><div class='ctx'> 	if (!abm || !tg || !panel_cntl)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -251,7 +258,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	otg_inst = tg-&gt;inst;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;dc-&gt;res_pool-&gt;dmcu) {</div><div class='del'>-		dce110_set_backlight_level(pipe_ctx, backlight_pwm_u16_16, frame_ramp);</div><div class='add'>+		dce110_set_backlight_level(pipe_ctx, backlight_level_params);</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -262,7 +269,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 					panel_cntl-&gt;inst,</div><div class='ctx'> 					panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 	} else {</div><div class='del'>-		dmub_abm_set_pipe(abm,</div><div class='add'>+			dcn21_dmub_abm_set_pipe(abm,</div><div class='ctx'> 				  otg_inst,</div><div class='ctx'> 				  SET_ABM_PIPE_NORMAL,</div><div class='ctx'> 				  panel_cntl-&gt;inst,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h<br/>index 9cee9bdb8de9..f72a27ac1bf1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h</a></div><div class='hunk'>@@ -47,11 +47,12 @@ void dcn21_optimize_pwr_state(</div><div class='ctx'> void dcn21_PLAT_58856_wa(struct dc_state *context,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='add'>+bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,</div><div class='add'>+	uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst);</div><div class='ctx'> void dcn21_set_pipe(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp);</div><div class='add'>+	struct set_backlight_level_params *params);</div><div class='ctx'> bool dcn21_is_abm_supported(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context, struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c<br/>index 18249c6b6d81..c7701a8b574a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c</a></div><div class='hunk'>@@ -37,6 +37,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -68,6 +69,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {</div><div class='ctx'> 	.set_avmute = dce110_set_avmute,</div><div class='ctx'> 	.log_hw_state = dcn10_log_hw_state,</div><div class='ctx'> 	.get_hw_state = dcn10_get_hw_state,</div><div class='add'>+	.log_color_state = dcn20_log_color_state,</div><div class='ctx'> 	.clear_status_bits = dcn10_clear_status_bits,</div><div class='ctx'> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='ctx'> 	.edp_backlight_control = dce110_edp_backlight_control,</div><div class='hunk'>@@ -92,7 +94,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = {</div><div class='ctx'> 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='ctx'> 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='del'>-	.power_down = dce110_power_down,</div><div class='ctx'> 	.set_backlight_level = dcn21_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='ctx'> 	.set_pipe = dcn21_set_pipe,</div><div class='hunk'>@@ -108,7 +109,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = {</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn21_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn20_set_input_transfer_func,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c<br/>index 8bc3d01537bb..81bcadf5e57e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c</a></div><div class='hunk'>@@ -50,10 +50,11 @@</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "dcn20/dcn20_hwseq.h"</div><div class='ctx'> #include "dcn30/dcn30_resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='del'>-</div><div class='add'>+#define TO_DCN_DCCG(dccg)\</div><div class='add'>+	container_of(dccg, struct dcn_dccg, base)</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -74,6 +75,7 @@ void dcn30_log_color_state(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='add'>+	bool is_gamut_remap_available = false;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	DTN_INFO("DPP:  DGAM ROM  DGAM ROM type  DGAM LUT  SHAPER mode"</div><div class='hunk'>@@ -88,16 +90,16 @@ void dcn30_log_color_state(struct dc *dc,</div><div class='ctx'> 		struct dcn_dpp_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_read_state(dpp, &amp;s);</div><div class='del'>-		dpp-&gt;funcs-&gt;dpp_get_gamut_remap(dpp, &amp;s.gamut_remap);</div><div class='add'>+</div><div class='add'>+		if (dpp-&gt;funcs-&gt;dpp_get_gamut_remap) {</div><div class='add'>+			dpp-&gt;funcs-&gt;dpp_get_gamut_remap(dpp, &amp;s.gamut_remap);</div><div class='add'>+			is_gamut_remap_available = true;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!s.is_enabled)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		DTN_INFO("[%2d]:  %7x  %13s  %8s  %11s  %10s  %15s  %10s  %9s"</div><div class='del'>-			 "  %12s  "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld "</div><div class='del'>-			 "%010lld %010lld %010lld %010lld",</div><div class='add'>+		DTN_INFO("[%2d]:  %7x  %13s  %8s  %11s  %10s  %15s  %10s  %9s",</div><div class='ctx'> 			dpp-&gt;inst,</div><div class='ctx'> 			s.pre_dgam_mode,</div><div class='ctx'> 			(s.pre_dgam_select == 0) ? "sRGB" :</div><div class='hunk'>@@ -121,7 +123,14 @@ void dcn30_log_color_state(struct dc *dc,</div><div class='ctx'> 			(s.lut3d_size == 0) ? "17x17x17" : "9x9x9",</div><div class='ctx'> 			(s.rgam_lut_mode == 0) ? "Bypass" :</div><div class='ctx'> 			 ((s.rgam_lut_mode == 1) ? "RAM A" :</div><div class='del'>-						   "RAM B"),</div><div class='add'>+						   "RAM B"));</div><div class='add'>+</div><div class='add'>+		if (is_gamut_remap_available) {</div><div class='add'>+			DTN_INFO("  %12s  "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld "</div><div class='add'>+				 "%010lld %010lld %010lld %010lld",</div><div class='add'>+</div><div class='ctx'> 			(s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :</div><div class='ctx'> 				((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :</div><div class='ctx'> 									  "SW"),</div><div class='hunk'>@@ -137,6 +146,8 @@ void dcn30_log_color_state(struct dc *dc,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[9].value,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[10].value,</div><div class='ctx'> 			s.gamut_remap.temperature_matrix[11].value);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		DTN_INFO("\n");</div><div class='ctx'> 	}</div><div class='ctx'> 	DTN_INFO("\n");</div><div class='hunk'>@@ -166,7 +177,7 @@ void dcn30_log_color_state(struct dc *dc,</div><div class='ctx'> 		 "C21        C22        C23        C24        "</div><div class='ctx'> 		 "C31        C32        C33        C34        \n");</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;mpcc_count; i++) {</div><div class='ctx'> 		struct mpcc_state s = {0};</div><div class='ctx'> </div><div class='ctx'> 		pool-&gt;mpc-&gt;funcs-&gt;read_mpcc_state(pool-&gt;mpc, i, &amp;s);</div><div class='hunk'>@@ -223,16 +234,17 @@ bool dcn30_set_blend_lut(</div><div class='ctx'> {</div><div class='ctx'> 	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	bool result = true;</div><div class='del'>-	struct pwl_params *blend_lut = NULL;</div><div class='del'>-</div><div class='del'>-	if (plane_state-&gt;blend_tf) {</div><div class='del'>-		if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			blend_lut = &amp;plane_state-&gt;blend_tf-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='del'>-			cm3_helper_translate_curve_to_hw_format(</div><div class='del'>-					plane_state-&gt;blend_tf, &amp;dpp_base-&gt;regamma_params, false);</div><div class='del'>-			blend_lut = &amp;dpp_base-&gt;regamma_params;</div><div class='del'>-		}</div><div class='add'>+	const struct pwl_params *blend_lut = NULL;</div><div class='add'>+</div><div class='add'>+	if (plane_state-&gt;blend_tf.type == TF_TYPE_HWPWL)</div><div class='add'>+		blend_lut = &amp;plane_state-&gt;blend_tf.pwl;</div><div class='add'>+	else if (plane_state-&gt;blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		result = cm3_helper_translate_curve_to_hw_format(</div><div class='add'>+				&amp;plane_state-&gt;blend_tf, &amp;dpp_base-&gt;regamma_params, false);</div><div class='add'>+		if (!result)</div><div class='add'>+			return result;</div><div class='add'>+</div><div class='add'>+		blend_lut = &amp;dpp_base-&gt;regamma_params;</div><div class='ctx'> 	}</div><div class='ctx'> 	result = dpp_base-&gt;funcs-&gt;dpp_program_blnd_lut(dpp_base, blend_lut);</div><div class='ctx'> </div><div class='hunk'>@@ -244,6 +256,7 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> {</div><div class='ctx'> 	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> 	bool result = false;</div><div class='ctx'> 	int acquired_rmu = 0;</div><div class='hunk'>@@ -282,8 +295,14 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> </div><div class='ctx'> 		result = mpc-&gt;funcs-&gt;program_3dlut(mpc, &amp;stream-&gt;lut3d_func-&gt;lut_3d,</div><div class='ctx'> 						   stream-&gt;lut3d_func-&gt;state.bits.rmu_mux_num);</div><div class='add'>+		if (!result)</div><div class='add'>+			DC_LOG_ERROR("%s: program_3dlut failed\n", __func__);</div><div class='add'>+</div><div class='ctx'> 		result = mpc-&gt;funcs-&gt;program_shaper(mpc, shaper_lut,</div><div class='ctx'> 						    stream-&gt;lut3d_func-&gt;state.bits.rmu_mux_num);</div><div class='add'>+		if (!result)</div><div class='add'>+			DC_LOG_ERROR("%s: program_shaper failed\n", __func__);</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='ctx'> 		// loop through the available mux and release the requested mpcc_id</div><div class='ctx'> 		mpc-&gt;funcs-&gt;release_rmu(mpc, mpcc_id);</div><div class='hunk'>@@ -300,27 +319,24 @@ bool dcn30_set_input_transfer_func(struct dc *dc,</div><div class='ctx'> 	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	enum dc_transfer_func_predefined tf;</div><div class='ctx'> 	bool result = true;</div><div class='del'>-	struct pwl_params *params = NULL;</div><div class='add'>+	const struct pwl_params *params = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (dpp_base == NULL || plane_state == NULL)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	tf = TRANSFER_FUNCTION_UNITY;</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func &amp;&amp;</div><div class='del'>-		plane_state-&gt;in_transfer_func-&gt;type == TF_TYPE_PREDEFINED)</div><div class='del'>-		tf = plane_state-&gt;in_transfer_func-&gt;tf;</div><div class='add'>+	if (plane_state-&gt;in_transfer_func.type == TF_TYPE_PREDEFINED)</div><div class='add'>+		tf = plane_state-&gt;in_transfer_func.tf;</div><div class='ctx'> </div><div class='ctx'> 	dpp_base-&gt;funcs-&gt;dpp_set_pre_degam(dpp_base, tf);</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func) {</div><div class='del'>-		if (plane_state-&gt;in_transfer_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			params = &amp;plane_state-&gt;in_transfer_func-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;in_transfer_func-&gt;type == TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='del'>-			cm3_helper_translate_curve_to_hw_format(plane_state-&gt;in_transfer_func,</div><div class='del'>-					&amp;dpp_base-&gt;degamma_params, false))</div><div class='del'>-			params = &amp;dpp_base-&gt;degamma_params;</div><div class='del'>-	}</div><div class='add'>+	if (plane_state-&gt;in_transfer_func.type == TF_TYPE_HWPWL)</div><div class='add'>+		params = &amp;plane_state-&gt;in_transfer_func.pwl;</div><div class='add'>+	else if (plane_state-&gt;in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='add'>+		cm3_helper_translate_curve_to_hw_format(&amp;plane_state-&gt;in_transfer_func,</div><div class='add'>+				&amp;dpp_base-&gt;degamma_params, false))</div><div class='add'>+		params = &amp;dpp_base-&gt;degamma_params;</div><div class='ctx'> </div><div class='ctx'> 	result = dpp_base-&gt;funcs-&gt;dpp_program_gamcor_lut(dpp_base, params);</div><div class='ctx'> </div><div class='hunk'>@@ -378,29 +394,33 @@ bool dcn30_set_output_transfer_func(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='ctx'> 	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='del'>-	struct pwl_params *params = NULL;</div><div class='add'>+	const struct pwl_params *params = NULL;</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> </div><div class='ctx'> 	/* program OGAM or 3DLUT only for the top pipe*/</div><div class='ctx'> 	if (pipe_ctx-&gt;top_pipe == NULL) {</div><div class='ctx'> 		/*program rmu shaper and 3dlut in MPC*/</div><div class='ctx'> 		ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);</div><div class='del'>-		if (ret == false &amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma &amp;&amp; stream-&gt;out_transfer_func) {</div><div class='del'>-			if (stream-&gt;out_transfer_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-				params = &amp;stream-&gt;out_transfer_func-&gt;pwl;</div><div class='del'>-			else if (pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;type ==</div><div class='add'>+		if (ret == false &amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma) {</div><div class='add'>+			if (stream-&gt;out_transfer_func.type == TF_TYPE_HWPWL)</div><div class='add'>+				params = &amp;stream-&gt;out_transfer_func.pwl;</div><div class='add'>+			else if (pipe_ctx-&gt;stream-&gt;out_transfer_func.type ==</div><div class='ctx'> 					TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='ctx'> 					cm3_helper_translate_curve_to_hw_format(</div><div class='del'>-					stream-&gt;out_transfer_func,</div><div class='add'>+					&amp;stream-&gt;out_transfer_func,</div><div class='ctx'> 					&amp;mpc-&gt;blender_params, false))</div><div class='ctx'> 				params = &amp;mpc-&gt;blender_params;</div><div class='ctx'> 			 /* there are no ROM LUTs in OUTGAM */</div><div class='del'>-			if (stream-&gt;out_transfer_func-&gt;type == TF_TYPE_PREDEFINED)</div><div class='add'>+			if (stream-&gt;out_transfer_func.type == TF_TYPE_PREDEFINED)</div><div class='ctx'> 				BREAK_TO_DEBUGGER();</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='add'>+	if (mpc-&gt;funcs-&gt;set_output_gamma)</div><div class='add'>+		mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='add'>+	else</div><div class='add'>+		DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -453,7 +473,7 @@ bool dcn30_mmhubbub_warmup(</div><div class='ctx'> 	struct mcif_wb *mcif_wb;</div><div class='ctx'> 	struct mcif_warmup_params warmup_params = {0};</div><div class='ctx'> 	unsigned int  i, i_buf;</div><div class='del'>-	/*make sure there is no active DWB eanbled */</div><div class='add'>+	/* make sure there is no active DWB enabled */</div><div class='ctx'> 	for (i = 0; i &lt; num_dwb; i++) {</div><div class='ctx'> 		dwb = dc-&gt;res_pool-&gt;dwbc[wb_info[i].dwb_pipe_inst];</div><div class='ctx'> 		if (dwb-&gt;dwb_is_efc_transition || dwb-&gt;dwb_is_drc) {</div><div class='hunk'>@@ -484,7 +504,6 @@ bool dcn30_mmhubbub_warmup(</div><div class='ctx'> 	}</div><div class='ctx'> 	/*following is the original: warmup each DWB's mcif buffer*/</div><div class='ctx'> 	for (i = 0; i &lt; num_dwb; i++) {</div><div class='del'>-		dwb = dc-&gt;res_pool-&gt;dwbc[wb_info[i].dwb_pipe_inst];</div><div class='ctx'> 		mcif_wb = dc-&gt;res_pool-&gt;mcif_wb[wb_info[i].dwb_pipe_inst];</div><div class='ctx'> 		/*warmup is for VM mode only*/</div><div class='ctx'> 		if (wb_info[i].mcif_buf_params.p_vmid == 0)</div><div class='hunk'>@@ -627,7 +646,7 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> 	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	// Initialize the dccg</div><div class='hunk'>@@ -661,7 +680,7 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;ref_clocks.xtalin_clock_inKhz =</div><div class='ctx'> 				dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency;</div><div class='ctx'> </div><div class='del'>-		if (res_pool-&gt;dccg &amp;&amp; res_pool-&gt;hubbub) {</div><div class='add'>+		if (res_pool-&gt;hubbub) {</div><div class='ctx'> </div><div class='ctx'> 			(res_pool-&gt;dccg-&gt;funcs-&gt;get_dccg_ref_freq)(res_pool-&gt;dccg,</div><div class='ctx'> 					dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency,</div><div class='hunk'>@@ -733,10 +752,10 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 		if (edp_link &amp;&amp; edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 				edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(edp_link-&gt;link_enc) &amp;&amp;</div><div class='ctx'> 				dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='del'>-				dc-&gt;hwss.power_down &amp;&amp;</div><div class='add'>+				hws-&gt;funcs.power_down &amp;&amp;</div><div class='ctx'> 				dc-&gt;hwss.edp_power_control) {</div><div class='ctx'> 			dc-&gt;hwss.edp_backlight_control(edp_link, false);</div><div class='del'>-			dc-&gt;hwss.power_down(dc);</div><div class='add'>+			hws-&gt;funcs.power_down(dc);</div><div class='ctx'> 			dc-&gt;hwss.edp_power_control(edp_link, false);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='hunk'>@@ -744,8 +763,8 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 				if (link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 						link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc) &amp;&amp;</div><div class='del'>-						dc-&gt;hwss.power_down) {</div><div class='del'>-					dc-&gt;hwss.power_down(dc);</div><div class='add'>+						hws-&gt;funcs.power_down) {</div><div class='add'>+					hws-&gt;funcs.power_down(dc);</div><div class='ctx'> 					break;</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='hunk'>@@ -788,11 +807,12 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 	if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb) &amp;&amp; dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	//if softmax is enabled then hardmax will be set by a different call</div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp;</div><div class='add'>+	    !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='hunk'>@@ -804,7 +824,7 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 	// Get DMCUB capabilities</div><div class='ctx'> 	dc_dmub_srv_query_caps_cmd(dc-&gt;ctx-&gt;dmub_srv);</div><div class='ctx'> 	dc-&gt;caps.dmub_caps.psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.psr;</div><div class='del'>-	dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch;</div><div class='add'>+	dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='hunk'>@@ -818,7 +838,7 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 				enable);</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for two frame to make sure AV mute is sent out */</div><div class='del'>-		if (enable) {</div><div class='add'>+		if (enable &amp;&amp; pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_tg_enabled(pipe_ctx-&gt;stream_res.tg)) {</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VBLANK);</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='hunk'>@@ -890,7 +910,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	uint32_t tmr_delay = 0, tmr_scale = 0;</div><div class='del'>-	struct dc_cursor_attributes cursor_attr;</div><div class='add'>+	struct dc_cursor_attributes cursor_attr = {0};</div><div class='ctx'> 	bool cursor_cache_enable = false;</div><div class='ctx'> 	struct dc_stream_state *stream = NULL;</div><div class='ctx'> 	struct dc_plane_state *plane = NULL;</div><div class='hunk'>@@ -924,6 +944,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 			stream = dc-&gt;current_state-&gt;streams[0];</div><div class='ctx'> 			plane = (stream ? dc-&gt;current_state-&gt;stream_status[0].plane_states[0] : NULL);</div><div class='ctx'> </div><div class='add'>+			if (!stream || !plane)</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='ctx'> 			if (stream &amp;&amp; plane) {</div><div class='ctx'> 				cursor_cache_enable = stream-&gt;cursor_position.enable &amp;&amp;</div><div class='ctx'> 						plane-&gt;address.grph.cursor_cache_addr.quad_part;</div><div class='hunk'>@@ -946,7 +969,8 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 					plane-&gt;format &gt;= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &amp;&amp;</div><div class='ctx'> 					plane-&gt;address.page_table_base.quad_part == 0 &amp;&amp;</div><div class='ctx'> 					dc-&gt;hwss.does_plane_fit_in_mall &amp;&amp;</div><div class='del'>-					dc-&gt;hwss.does_plane_fit_in_mall(dc, plane,</div><div class='add'>+					dc-&gt;hwss.does_plane_fit_in_mall(dc, plane-&gt;plane_size.surface_pitch,</div><div class='add'>+							plane-&gt;plane_size.surface_size.height, plane-&gt;format,</div><div class='ctx'> 							cursor_cache_enable ? &amp;cursor_attr : NULL)) {</div><div class='ctx'> 				unsigned int v_total = stream-&gt;adjust.v_total_max ?</div><div class='ctx'> 						stream-&gt;adjust.v_total_max : stream-&gt;timing.v_total;</div><div class='hunk'>@@ -1042,7 +1066,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> </div><div class='ctx'> 					/* Use copied cursor, and it's okay to not switch back */</div><div class='ctx'> 					cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;</div><div class='del'>-					dc_stream_set_cursor_attributes(stream, &amp;cursor_attr);</div><div class='add'>+					dc_stream_program_cursor_attributes(stream, &amp;cursor_attr);</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='ctx'> 				/* Enable MALL */</div><div class='hunk'>@@ -1076,11 +1100,15 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)</div><div class='add'>+bool dcn30_does_plane_fit_in_mall(struct dc *dc,</div><div class='add'>+		unsigned int pitch,</div><div class='add'>+		unsigned int height,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		struct dc_cursor_attributes *cursor_attr)</div><div class='ctx'> {</div><div class='ctx'> 	// add meta size?</div><div class='del'>-	unsigned int surface_size = plane-&gt;plane_size.surface_pitch * plane-&gt;plane_size.surface_size.height *</div><div class='del'>-			(plane-&gt;format &gt;= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);</div><div class='add'>+	unsigned int surface_size = pitch * height *</div><div class='add'>+			(format &gt;= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);</div><div class='ctx'> 	unsigned int mall_size = dc-&gt;caps.mall_size_total;</div><div class='ctx'> 	unsigned int cursor_size = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1174,3 +1202,81 @@ void dcn30_prepare_bandwidth(struct dc *dc,</div><div class='ctx'> 	if (!dc-&gt;clk_mgr-&gt;clks.fw_based_mclk_switching)</div><div class='ctx'> 		dc_dmub_srv_p_state_delegate(dc, false, context);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+	bool pending_updates = false;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (tg &amp;&amp; tg-&gt;funcs-&gt;is_tg_enabled(tg)) {</div><div class='add'>+		// Poll for 100ms maximum</div><div class='add'>+		for (i = 0; i &lt; 100000; i++) {</div><div class='add'>+			pending_updates = false;</div><div class='add'>+			if (tg-&gt;funcs-&gt;get_optc_double_buffer_pending)</div><div class='add'>+				pending_updates |= tg-&gt;funcs-&gt;get_optc_double_buffer_pending(tg);</div><div class='add'>+</div><div class='add'>+			if (tg-&gt;funcs-&gt;get_otg_double_buffer_pending)</div><div class='add'>+				pending_updates |= tg-&gt;funcs-&gt;get_otg_double_buffer_pending(tg);</div><div class='add'>+</div><div class='add'>+			if (tg-&gt;funcs-&gt;get_pipe_update_pending &amp;&amp; pipe_ctx-&gt;plane_state)</div><div class='add'>+				pending_updates |= tg-&gt;funcs-&gt;get_pipe_update_pending(tg);</div><div class='add'>+</div><div class='add'>+			if (!pending_updates)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			udelay(1);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn30_get_underflow_debug_data(const struct dc *dc,</div><div class='add'>+	struct timing_generator *tg,</div><div class='add'>+	struct dc_underflow_debug_data *out_data)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+</div><div class='add'>+	if (hubbub) {</div><div class='add'>+		if (hubbub-&gt;funcs-&gt;hubbub_read_reg_state) {</div><div class='add'>+			hubbub-&gt;funcs-&gt;hubbub_read_reg_state(hubbub, out_data-&gt;hubbub_reg_state);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		struct hubp *hubp = dc-&gt;res_pool-&gt;hubps[i];</div><div class='add'>+		struct dpp *dpp = dc-&gt;res_pool-&gt;dpps[i];</div><div class='add'>+		struct output_pixel_processor *opp = dc-&gt;res_pool-&gt;opps[i];</div><div class='add'>+		struct display_stream_compressor *dsc = dc-&gt;res_pool-&gt;dscs[i];</div><div class='add'>+		struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+		struct timing_generator *optc = dc-&gt;res_pool-&gt;timing_generators[i];</div><div class='add'>+		struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+</div><div class='add'>+		if (hubp)</div><div class='add'>+			if (hubp-&gt;funcs-&gt;hubp_read_reg_state)</div><div class='add'>+				hubp-&gt;funcs-&gt;hubp_read_reg_state(hubp, out_data-&gt;hubp_reg_state[i]);</div><div class='add'>+</div><div class='add'>+		if (dpp)</div><div class='add'>+			if (dpp-&gt;funcs-&gt;dpp_read_reg_state)</div><div class='add'>+				dpp-&gt;funcs-&gt;dpp_read_reg_state(dpp, out_data-&gt;dpp_reg_state[i]);</div><div class='add'>+</div><div class='add'>+		if (opp)</div><div class='add'>+			if (opp-&gt;funcs-&gt;opp_read_reg_state)</div><div class='add'>+				opp-&gt;funcs-&gt;opp_read_reg_state(opp, out_data-&gt;opp_reg_state[i]);</div><div class='add'>+</div><div class='add'>+		if (dsc)</div><div class='add'>+			if (dsc-&gt;funcs-&gt;dsc_read_reg_state)</div><div class='add'>+				dsc-&gt;funcs-&gt;dsc_read_reg_state(dsc, out_data-&gt;dsc_reg_state[i]);</div><div class='add'>+</div><div class='add'>+		if (mpc)</div><div class='add'>+			if (mpc-&gt;funcs-&gt;mpc_read_reg_state)</div><div class='add'>+				mpc-&gt;funcs-&gt;mpc_read_reg_state(mpc, i, out_data-&gt;mpc_reg_state[i]);</div><div class='add'>+</div><div class='add'>+		if (optc)</div><div class='add'>+			if (optc-&gt;funcs-&gt;optc_read_reg_state)</div><div class='add'>+				optc-&gt;funcs-&gt;optc_read_reg_state(optc, out_data-&gt;optc_reg_state[i]);</div><div class='add'>+</div><div class='add'>+		if (dccg)</div><div class='add'>+			if (dccg-&gt;funcs-&gt;dccg_read_reg_state)</div><div class='add'>+				dccg-&gt;funcs-&gt;dccg_read_reg_state(dccg, out_data-&gt;dccg_reg_state[i]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h<br/>index 638f018a3cb5..40afbbfb5b9c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h</a></div><div class='hunk'>@@ -27,8 +27,9 @@</div><div class='ctx'> #define __DC_HWSS_DCN30_H__</div><div class='ctx'> </div><div class='ctx'> #include "hw_sequencer_private.h"</div><div class='del'>-#include "dcn20/dcn20_hwseq.h"</div><div class='add'>+</div><div class='ctx'> struct dc;</div><div class='add'>+struct dc_underflow_debug_data;</div><div class='ctx'> </div><div class='ctx'> void dcn30_init_hw(struct dc *dc);</div><div class='ctx'> void dcn30_program_all_writeback_pipes_in_tree(</div><div class='hunk'>@@ -71,7 +72,10 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);</div><div class='ctx'> void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='del'>-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,</div><div class='add'>+bool dcn30_does_plane_fit_in_mall(struct dc *dc,</div><div class='add'>+		unsigned int pitch,</div><div class='add'>+		unsigned int height,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='ctx'> 		struct dc_cursor_attributes *cursor_attr);</div><div class='ctx'> </div><div class='ctx'> bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);</div><div class='hunk'>@@ -93,4 +97,10 @@ void dcn30_set_hubp_blank(const struct dc *dc,</div><div class='ctx'> void dcn30_prepare_bandwidth(struct dc *dc,</div><div class='ctx'> 	struct dc_state *context);</div><div class='ctx'> </div><div class='add'>+void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void dcn30_get_underflow_debug_data(const struct dc *dc,</div><div class='add'>+	struct timing_generator *tg,</div><div class='add'>+	struct dc_underflow_debug_data *out_data);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCN30_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c<br/>index ef913445a795..d7ff55669bac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c</a></div><div class='hunk'>@@ -37,6 +37,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -68,6 +69,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {</div><div class='ctx'> 	.setup_stereo = dcn10_setup_stereo,</div><div class='ctx'> 	.set_avmute = dcn30_set_avmute,</div><div class='ctx'> 	.log_hw_state = dcn10_log_hw_state,</div><div class='add'>+	.log_color_state = dcn30_log_color_state,</div><div class='ctx'> 	.get_hw_state = dcn10_get_hw_state,</div><div class='ctx'> 	.clear_status_bits = dcn10_clear_status_bits,</div><div class='ctx'> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='hunk'>@@ -85,7 +87,6 @@ static const struct hw_sequencer_funcs dcn30_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -107,12 +108,13 @@ static const struct hw_sequencer_funcs dcn30_funcs = {</div><div class='ctx'> 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,</div><div class='ctx'> 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,</div><div class='ctx'> 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='del'>-	.is_abm_supported = dcn21_is_abm_supported</div><div class='add'>+	.is_abm_supported = dcn21_is_abm_supported,</div><div class='add'>+	.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn30_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn30_set_input_transfer_func,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c<br/>index 6477009ce065..8d7ceb7b32b8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c</a></div><div class='hunk'>@@ -39,6 +39,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -53,9 +54,6 @@ static const struct hw_sequencer_funcs dcn301_funcs = {</div><div class='ctx'> 	.enable_stream = dcn20_enable_stream,</div><div class='ctx'> 	.disable_stream = dce110_disable_stream,</div><div class='ctx'> 	.unblank_stream = dcn20_unblank_stream,</div><div class='del'>-#ifdef FREESYNC_POWER_OPTIMIZE</div><div class='del'>-	.are_streams_coarse_grain_aligned = dcn20_are_streams_coarse_grain_aligned,</div><div class='del'>-#endif</div><div class='ctx'> 	.blank_stream = dce110_blank_stream,</div><div class='ctx'> 	.enable_audio_stream = dce110_enable_audio_stream,</div><div class='ctx'> 	.disable_audio_stream = dce110_disable_audio_stream,</div><div class='hunk'>@@ -72,6 +70,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {</div><div class='ctx'> 	.setup_stereo = dcn10_setup_stereo,</div><div class='ctx'> 	.set_avmute = dcn30_set_avmute,</div><div class='ctx'> 	.log_hw_state = dcn10_log_hw_state,</div><div class='add'>+	.log_color_state = dcn30_log_color_state,</div><div class='ctx'> 	.get_hw_state = dcn10_get_hw_state,</div><div class='ctx'> 	.clear_status_bits = dcn10_clear_status_bits,</div><div class='ctx'> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='hunk'>@@ -88,7 +87,6 @@ static const struct hw_sequencer_funcs dcn301_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -109,11 +107,11 @@ static const struct hw_sequencer_funcs dcn301_funcs = {</div><div class='ctx'> 	.optimize_pwr_state = dcn21_optimize_pwr_state,</div><div class='ctx'> 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='ctx'> 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='add'>+	.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn301_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn30_set_input_transfer_func,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h<br/>index 0bca48ccbfa2..a6e0115a53ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h</a></div><div class='hunk'>@@ -23,8 +23,8 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#ifndef __DC_DCN30_INIT_H__</div><div class='del'>-#define __DC_DCN30_INIT_H__</div><div class='add'>+#ifndef __DC_DCN301_INIT_H__</div><div class='add'>+#define __DC_DCN301_INIT_H__</div><div class='ctx'> </div><div class='ctx'> struct dc;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c<br/>index a760f0c6fe98..d1ecdb92b072 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c</a></div><div class='hunk'>@@ -45,11 +45,13 @@</div><div class='ctx'> #include "link_hwss.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "dce/dmub_outbox.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn10/dcn10_hwseq.h"</div><div class='add'>+#include "dcn21/dcn21_hwseq.h"</div><div class='ctx'> #include "inc/link_enc_cfg.h"</div><div class='ctx'> #include "dcn30/dcn30_vpg.h"</div><div class='ctx'> #include "dce/dce_i2c_hw.h"</div><div class='add'>+#include "dce/dmub_abm_lcd.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -132,7 +134,7 @@ void dcn31_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;ref_clocks.xtalin_clock_inKhz =</div><div class='ctx'> 				dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency;</div><div class='ctx'> </div><div class='del'>-		if (res_pool-&gt;dccg &amp;&amp; res_pool-&gt;hubbub) {</div><div class='add'>+		if (res_pool-&gt;hubbub) {</div><div class='ctx'> </div><div class='ctx'> 			(res_pool-&gt;dccg-&gt;funcs-&gt;get_dccg_ref_freq)(res_pool-&gt;dccg,</div><div class='ctx'> 					dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency,</div><div class='hunk'>@@ -256,10 +258,10 @@ void dcn31_init_hw(struct dc *dc)</div><div class='ctx'> 	if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb) &amp;&amp; dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='hunk'>@@ -273,7 +275,7 @@ void dcn31_init_hw(struct dc *dc)</div><div class='ctx'> 	// Get DMCUB capabilities</div><div class='ctx'> 	dc_dmub_srv_query_caps_cmd(dc-&gt;ctx-&gt;dmub_srv);</div><div class='ctx'> 	dc-&gt;caps.dmub_caps.psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.psr;</div><div class='del'>-	dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch;</div><div class='add'>+	dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn31_dsc_pg_control(</div><div class='hunk'>@@ -394,6 +396,11 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.stream_enc,</div><div class='ctx'> 			&amp;pipe_ctx-&gt;stream_res.encoder_info_frame);</div><div class='ctx'> 	else if (pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc-&gt;funcs-&gt;update_dp_info_packets_sdp_line_num)</div><div class='add'>+			pipe_ctx-&gt;stream_res.hpo_dp_stream_enc-&gt;funcs-&gt;update_dp_info_packets_sdp_line_num(</div><div class='add'>+				pipe_ctx-&gt;stream_res.hpo_dp_stream_enc,</div><div class='add'>+				&amp;pipe_ctx-&gt;stream_res.encoder_info_frame);</div><div class='add'>+</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.hpo_dp_stream_enc-&gt;funcs-&gt;update_dp_info_packets(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.hpo_dp_stream_enc,</div><div class='ctx'> 				&amp;pipe_ctx-&gt;stream_res.encoder_info_frame);</div><div class='hunk'>@@ -479,7 +486,7 @@ void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool p</div><div class='ctx'> </div><div class='ctx'> int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)</div><div class='ctx'> {</div><div class='del'>-	struct dcn_hubbub_phys_addr_config config;</div><div class='add'>+	struct dcn_hubbub_phys_addr_config config = {0};</div><div class='ctx'> </div><div class='ctx'> 	config.system_aperture.fb_top = pa_config-&gt;system_aperture.fb_top;</div><div class='ctx'> 	config.system_aperture.fb_offset = pa_config-&gt;system_aperture.fb_offset;</div><div class='hunk'>@@ -517,10 +524,24 @@ static void dcn31_reset_back_end_for_pipe(</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;hwss.set_abm_immediate_disable(pipe_ctx);</div><div class='ctx'> </div><div class='add'>+	link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwseq)</div><div class='add'>+		dc-&gt;hwseq-&gt;wa_state.skip_blank_stream = false;</div><div class='add'>+</div><div class='add'>+	if ((!pipe_ctx-&gt;stream-&gt;dpms_off || link-&gt;link_status.link_active) &amp;&amp;</div><div class='add'>+		(link-&gt;connector_signal == SIGNAL_TYPE_EDP)) {</div><div class='add'>+		dc-&gt;hwss.blank_stream(pipe_ctx);</div><div class='add'>+		if (dc-&gt;hwseq)</div><div class='add'>+			dc-&gt;hwseq-&gt;wa_state.skip_blank_stream = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_dsc_config(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 			OPTC_DSC_DISABLED, 0, 0);</div><div class='add'>+</div><div class='ctx'> 	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe_ctx-&gt;stream_res.tg);</div><div class='add'>+</div><div class='ctx'> 	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;enable_optc_clock(pipe_ctx-&gt;stream_res.tg, false);</div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass)</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='hunk'>@@ -528,11 +549,8 @@ static void dcn31_reset_back_end_for_pipe(</div><div class='ctx'> 	if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 		pipe_ctx-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-				pipe_ctx-&gt;stream_res.tg, NULL);</div><div class='add'>+	set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx-&gt;stream, NULL);</div><div class='ctx'> </div><div class='del'>-	link = pipe_ctx-&gt;stream-&gt;link;</div><div class='ctx'> 	/* DPMS may already disable or */</div><div class='ctx'> 	/* dpms_off status is incorrect due to fastboot</div><div class='ctx'> 	 * feature. When system resume from S4 with second</div><div class='hunk'>@@ -544,6 +562,19 @@ static void dcn31_reset_back_end_for_pipe(</div><div class='ctx'> 	else if (pipe_ctx-&gt;stream_res.audio)</div><div class='ctx'> 		dc-&gt;hwss.disable_audio_stream(pipe_ctx);</div><div class='ctx'> </div><div class='add'>+	/* Temporary workaround to perform DSC programming ahead of pipe reset</div><div class='add'>+	 * for smartmux/SPRS</div><div class='add'>+	 * TODO: Remove SmartMux/SPRS checks once movement of DSC programming is generalized</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;timing.flags.DSC) {</div><div class='add'>+		if ((pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+			((link-&gt;dc-&gt;config.smart_mux_version &amp;&amp; link-&gt;dc-&gt;is_switch_in_progress_dest)</div><div class='add'>+			|| link-&gt;is_dds || link-&gt;skip_implict_edp_power_control)) &amp;&amp;</div><div class='add'>+			(dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal) ||</div><div class='add'>+			dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal)))</div><div class='add'>+			dc-&gt;link_srv-&gt;set_dsc_enable(pipe_ctx, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* free acquired resources */</div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.audio) {</div><div class='ctx'> 		/*disable az_endpoint*/</div><div class='hunk'>@@ -558,7 +589,8 @@ static void dcn31_reset_back_end_for_pipe(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.audio = NULL;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	if (dc-&gt;hwseq)</div><div class='add'>+		dc-&gt;hwseq-&gt;wa_state.skip_blank_stream = false;</div><div class='ctx'> 	pipe_ctx-&gt;stream = NULL;</div><div class='ctx'> 	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",</div><div class='ctx'> 					pipe_ctx-&gt;pipe_idx, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='hunk'>@@ -607,7 +639,8 @@ void dcn31_reset_hw_ctx_wrap(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* New dc_state in the process of being applied to hardware. */</div><div class='del'>-	link_enc_cfg_set_transient_mode(dc, dc-&gt;current_state, context);</div><div class='add'>+	if (!dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc_cfg_set_transient_mode(dc, dc-&gt;current_state, context);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)</div><div class='hunk'>@@ -633,3 +666,52 @@ void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 		pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(pipe_ctx[i]-&gt;stream_res.tg,</div><div class='ctx'> 					triggers, params-&gt;num_frames);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static void dmub_abm_set_backlight(struct dc_context *dc,</div><div class='add'>+	struct set_backlight_level_params *backlight_level_params, uint32_t panel_inst)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+	cmd.abm_set_backlight.header.type = DMUB_CMD__ABM;</div><div class='add'>+	cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = backlight_level_params-&gt;frame_ramp;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_level_params-&gt;backlight_pwm_u16_16;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.backlight_control_type =</div><div class='add'>+		(enum dmub_backlight_control_type) backlight_level_params-&gt;control_type;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.min_luminance = backlight_level_params-&gt;min_luminance;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.max_luminance = backlight_level_params-&gt;max_luminance;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.min_backlight_pwm = backlight_level_params-&gt;min_backlight_pwm;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.max_backlight_pwm = backlight_level_params-&gt;max_backlight_pwm;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;</div><div class='add'>+	cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 &lt;&lt; panel_inst);</div><div class='add'>+	cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct set_backlight_level_params *backlight_level_params)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *dc = pipe_ctx-&gt;stream-&gt;ctx;</div><div class='add'>+	struct abm *abm = pipe_ctx-&gt;stream_res.abm;</div><div class='add'>+	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+	struct panel_cntl *panel_cntl = pipe_ctx-&gt;stream-&gt;link-&gt;panel_cntl;</div><div class='add'>+	uint32_t otg_inst;</div><div class='add'>+</div><div class='add'>+	if (!abm || !tg || !panel_cntl)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	otg_inst = tg-&gt;inst;</div><div class='add'>+</div><div class='add'>+		dcn21_dmub_abm_set_pipe(abm,</div><div class='add'>+			otg_inst,</div><div class='add'>+			SET_ABM_PIPE_NORMAL,</div><div class='add'>+			panel_cntl-&gt;inst,</div><div class='add'>+			panel_cntl-&gt;pwrseq_inst);</div><div class='add'>+</div><div class='add'>+	if (backlight_level_params-&gt;control_type != BACKLIGHT_CONTROL_AMD_AUX)</div><div class='add'>+		dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl-&gt;inst);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h<br/>index b8bc939da155..0d09aa8cfb65 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h</a></div><div class='hunk'>@@ -51,6 +51,8 @@ int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_</div><div class='ctx'> void dcn31_reset_hw_ctx_wrap(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context);</div><div class='add'>+bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct set_backlight_level_params *params);</div><div class='ctx'> bool dcn31_is_abm_supported(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context, struct dc_stream_state *stream);</div><div class='ctx'> void dcn31_init_pipes(struct dc *dc, struct dc_state *context);</div><div class='hunk'>@@ -59,5 +61,4 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);</div><div class='ctx'> void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 		int num_pipes, const struct dc_static_screen_params *params);</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> #endif /* __DC_HWSS_DCN31_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c<br/>index c06cc2c5da92..5a6a459da224 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c</a></div><div class='hunk'>@@ -40,6 +40,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -71,6 +72,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {</div><div class='ctx'> 	.setup_stereo = dcn10_setup_stereo,</div><div class='ctx'> 	.set_avmute = dcn30_set_avmute,</div><div class='ctx'> 	.log_hw_state = dcn10_log_hw_state,</div><div class='add'>+	.log_color_state = dcn30_log_color_state,</div><div class='ctx'> 	.get_hw_state = dcn10_get_hw_state,</div><div class='ctx'> 	.clear_status_bits = dcn10_clear_status_bits,</div><div class='ctx'> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='hunk'>@@ -88,7 +90,6 @@ static const struct hw_sequencer_funcs dcn31_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -97,7 +98,6 @@ static const struct hw_sequencer_funcs dcn31_funcs = {</div><div class='ctx'> 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,</div><div class='ctx'> 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='del'>-	.power_down = dce110_power_down,</div><div class='ctx'> 	.set_backlight_level = dcn21_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='ctx'> 	.set_pipe = dcn21_set_pipe,</div><div class='hunk'>@@ -111,11 +111,12 @@ static const struct hw_sequencer_funcs dcn31_funcs = {</div><div class='ctx'> 	.optimize_pwr_state = dcn21_optimize_pwr_state,</div><div class='ctx'> 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='ctx'> 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='add'>+	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn31_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn30_set_input_transfer_func,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c<br/>index 3a9cc8ac0c07..4ee6ed610de0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c</a></div><div class='hunk'>@@ -46,7 +46,7 @@</div><div class='ctx'> #include "link_hwss.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "dce/dmub_outbox.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn10/dcn10_hwseq.h"</div><div class='ctx'> #include "inc/link_enc_cfg.h"</div><div class='ctx'> #include "dcn30/dcn30_vpg.h"</div><div class='hunk'>@@ -69,29 +69,6 @@</div><div class='ctx'> #define FN(reg_name, field_name) \</div><div class='ctx'> 	hws-&gt;shifts-&gt;field_name, hws-&gt;masks-&gt;field_name</div><div class='ctx'> </div><div class='del'>-static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,</div><div class='del'>-		int opp_cnt)</div><div class='del'>-{</div><div class='del'>-	bool hblank_halved = optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing);</div><div class='del'>-	int flow_ctrl_cnt;</div><div class='del'>-</div><div class='del'>-	if (opp_cnt &gt;= 2)</div><div class='del'>-		hblank_halved = true;</div><div class='del'>-</div><div class='del'>-	flow_ctrl_cnt = stream-&gt;timing.h_total - stream-&gt;timing.h_addressable -</div><div class='del'>-			stream-&gt;timing.h_border_left -</div><div class='del'>-			stream-&gt;timing.h_border_right;</div><div class='del'>-</div><div class='del'>-	if (hblank_halved)</div><div class='del'>-		flow_ctrl_cnt /= 2;</div><div class='del'>-</div><div class='del'>-	/* ODM combine 4:1 case */</div><div class='del'>-	if (opp_cnt == 4)</div><div class='del'>-		flow_ctrl_cnt /= 2;</div><div class='del'>-</div><div class='del'>-	return flow_ctrl_cnt;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='hunk'>@@ -105,8 +82,22 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		struct dsc_config dsc_cfg;</div><div class='del'>-		struct dsc_optc_config dsc_optc_cfg;</div><div class='add'>+		struct dsc_optc_config dsc_optc_cfg = {0};</div><div class='ctx'> 		enum optc_dsc_mode optc_dsc_mode;</div><div class='add'>+		struct dcn_dsc_state dsc_state = {0};</div><div class='add'>+</div><div class='add'>+		if (!dsc) {</div><div class='add'>+			DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dsc-&gt;funcs-&gt;dsc_read_state) {</div><div class='add'>+			dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='add'>+			if (!dsc_state.dsc_fw_en) {</div><div class='add'>+				DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		/* Enable DSC hw block */</div><div class='ctx'> 		dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='hunk'>@@ -117,6 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='ctx'> 		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;</div><div class='add'>+		dsc_cfg.dsc_padding = pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='ctx'> </div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='hunk'>@@ -183,8 +175,8 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 0;</div><div class='ctx'> 	int opp_inst[MAX_PIPES] = {0};</div><div class='del'>-	bool rate_control_2x_pclk = (pipe_ctx-&gt;stream-&gt;timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&amp;pipe_ctx-&gt;stream-&gt;timing));</div><div class='del'>-	struct mpc_dwb_flow_control flow_control;</div><div class='add'>+	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);</div><div class='add'>+	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);</div><div class='ctx'> 	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -194,22 +186,18 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 				opp_inst, opp_cnt,</div><div class='del'>-				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='ctx'> 	else</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='ctx'> </div><div class='del'>-	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt &gt; 1;</div><div class='del'>-	flow_control.flow_ctrl_mode = 0;</div><div class='del'>-	flow_control.flow_ctrl_cnt0 = 0x80;</div><div class='del'>-	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx-&gt;stream, opp_cnt);</div><div class='ctx'> 	if (mpc-&gt;funcs-&gt;set_out_rate_control) {</div><div class='ctx'> 		for (i = 0; i &lt; opp_cnt; ++i) {</div><div class='ctx'> 			mpc-&gt;funcs-&gt;set_out_rate_control(</div><div class='ctx'> 					mpc, opp_inst[i],</div><div class='del'>-					true,</div><div class='del'>-					rate_control_2x_pclk,</div><div class='del'>-					&amp;flow_control);</div><div class='add'>+					false,</div><div class='add'>+					0,</div><div class='add'>+					NULL);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -343,7 +331,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig</div><div class='ctx'> 	unsigned int odm_combine_factor = 0;</div><div class='ctx'> 	bool two_pix_per_container = false;</div><div class='ctx'> </div><div class='del'>-	two_pix_per_container = optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing);</div><div class='add'>+	two_pix_per_container = pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing);</div><div class='ctx'> 	odm_combine_factor = get_odm_config(pipe_ctx, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='hunk'>@@ -373,36 +361,62 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig</div><div class='ctx'> 	return odm_combine_factor;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn314_calculate_pix_rate_divider(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='del'>-	uint32_t pix_per_cycle = 1;</div><div class='del'>-	uint32_t odm_combine_factor = 1;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = NULL;</div><div class='add'>+	unsigned int k1_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	unsigned int k2_div = PIXEL_RATE_DIV_NA;</div><div class='ctx'> </div><div class='del'>-	if (!pipe_ctx || !pipe_ctx-&gt;stream || !pipe_ctx-&gt;stream_res.stream_enc)</div><div class='del'>-		return;</div><div class='add'>+	pipe_ctx = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, stream);</div><div class='ctx'> </div><div class='del'>-	odm_combine_factor = get_odm_config(pipe_ctx, NULL);</div><div class='del'>-	if (optc2_is_two_pixels_per_containter(&amp;pipe_ctx-&gt;stream-&gt;timing) || odm_combine_factor &gt; 1)</div><div class='del'>-		pix_per_cycle = 2;</div><div class='add'>+	if (pipe_ctx) {</div><div class='add'>+		if (hws-&gt;funcs.calculate_dccg_k1_k2_values)</div><div class='add'>+			hws-&gt;funcs.calculate_dccg_k1_k2_values(pipe_ctx, &amp;k1_div, &amp;k2_div);</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;pixel_rate_divider.div_factor1 = k1_div;</div><div class='add'>+		pipe_ctx-&gt;pixel_rate_divider.div_factor2 = k2_div;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;set_input_mode)</div><div class='del'>-		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;set_input_mode(pipe_ctx-&gt;stream_res.stream_enc,</div><div class='del'>-				pix_per_cycle);</div><div class='add'>+static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	return pipe &amp;&amp; pipe-&gt;stream</div><div class='add'>+		// Check dig's otg instance.</div><div class='add'>+		&amp;&amp; pipe-&gt;stream_res.stream_enc</div><div class='add'>+		&amp;&amp; pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;dig_source_otg</div><div class='add'>+		&amp;&amp; pipe-&gt;stream_res.tg-&gt;inst == pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;dig_source_otg(pipe-&gt;stream_res.stream_enc)</div><div class='add'>+		&amp;&amp; pipe-&gt;stream-&gt;link &amp;&amp; pipe-&gt;stream-&gt;link-&gt;link_enc</div><div class='add'>+		&amp;&amp; pipe-&gt;stream-&gt;link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled</div><div class='add'>+		&amp;&amp; pipe-&gt;stream-&gt;link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(pipe-&gt;stream-&gt;link-&gt;link_enc)</div><div class='add'>+		&amp;&amp; pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;is_fifo_enabled</div><div class='add'>+		&amp;&amp; pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;is_fifo_enabled(pipe-&gt;stream_res.stream_enc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)</div><div class='add'>+void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	struct pipe_ctx *pipe = NULL;</div><div class='ctx'> 	bool otg_disabled[MAX_PIPES] = {false};</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (i &lt;= current_pipe_idx) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		} else {</div><div class='add'>+			pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;top_pipe || pipe-&gt;prev_odm_pipe)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal))) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal)) &amp;&amp;</div><div class='add'>+			!pipe-&gt;stream-&gt;apply_seamless_boot_optimization &amp;&amp;</div><div class='add'>+			!pipe-&gt;stream-&gt;apply_edp_fast_boot_optimization) {</div><div class='add'>+			if (dcn314_is_pipe_dig_fifo_on(pipe))</div><div class='add'>+				continue;</div><div class='ctx'> 			pipe-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe-&gt;stream_res.tg);</div><div class='ctx'> 			reset_sync_context_for_pipe(dc, context, i);</div><div class='ctx'> 			otg_disabled[i] = true;</div><div class='hunk'>@@ -412,10 +426,30 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc</div><div class='ctx'> 	hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;trigger_dio_fifo_resync(hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (otg_disabled[i])</div><div class='add'>+		if (i &lt;= current_pipe_idx)</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		else</div><div class='add'>+			pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (otg_disabled[i]) {</div><div class='add'>+			int opp_inst[MAX_PIPES] = { pipe-&gt;stream_res.opp-&gt;inst };</div><div class='add'>+			int opp_cnt = 1;</div><div class='add'>+			int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);</div><div class='add'>+			int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);</div><div class='add'>+			struct pipe_ctx *odm_pipe;</div><div class='add'>+</div><div class='add'>+			for (odm_pipe = pipe-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+				opp_inst[opp_cnt] = odm_pipe-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+				opp_cnt++;</div><div class='add'>+			}</div><div class='add'>+			if (opp_cnt &gt; 1)</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='add'>+						pipe-&gt;stream_res.tg,</div><div class='add'>+						opp_inst, opp_cnt,</div><div class='add'>+						odm_slice_width,</div><div class='add'>+						last_odm_slice_width);</div><div class='ctx'> 			pipe-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipe-&gt;stream_res.tg);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -489,9 +523,81 @@ void dcn314_disable_link_output(struct dc_link *link,</div><div class='ctx'> 	 * from enable/disable link output and only call edp panel control</div><div class='ctx'> 	 * in enable_link_dp and disable_link_dp once.</div><div class='ctx'> 	 */</div><div class='del'>-	if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;lock_phy)</div><div class='add'>+	if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;unlock_phy)</div><div class='ctx'> 		dmcu-&gt;funcs-&gt;unlock_phy(dmcu);</div><div class='ctx'> 	dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);</div><div class='ctx'> </div><div class='ctx'> 	apply_symclk_on_tx_off_wa(link);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcn314_dpp_pg_control - DPP power gate control.</div><div class='add'>+ *</div><div class='add'>+ * @hws: dce_hwseq reference.</div><div class='add'>+ * @dpp_inst: DPP instance reference.</div><div class='add'>+ * @power_on: true if we want to enable power gate, false otherwise.</div><div class='add'>+ *</div><div class='add'>+ * Enable or disable power gate in the specific DPP instance.</div><div class='add'>+ * If power gating is disabled, will force disable cursor in the DPP instance.</div><div class='add'>+ */</div><div class='add'>+void dcn314_dpp_pg_control(</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int dpp_inst,</div><div class='add'>+		bool power_on)</div><div class='add'>+{</div><div class='add'>+	uint32_t power_gate = power_on ? 0 : 1;</div><div class='add'>+	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;ctx-&gt;dc-&gt;debug.disable_dpp_power_gate) {</div><div class='add'>+		/* Workaround for DCN314 with disabled power gating */</div><div class='add'>+		if (!power_on) {</div><div class='add'>+</div><div class='add'>+			/* Force disable cursor if power gating is disabled */</div><div class='add'>+			struct dpp *dpp = hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dpps[dpp_inst];</div><div class='add'>+			if (dpp &amp;&amp; dpp-&gt;funcs-&gt;dpp_force_disable_cursor)</div><div class='add'>+				dpp-&gt;funcs-&gt;dpp_force_disable_cursor(dpp);</div><div class='add'>+		}</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	if (REG(DOMAIN1_PG_CONFIG) == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (dpp_inst) {</div><div class='add'>+	case 0: /* DPP0 */</div><div class='add'>+		REG_UPDATE(DOMAIN1_PG_CONFIG,</div><div class='add'>+				DOMAIN1_POWER_GATE, power_gate);</div><div class='add'>+</div><div class='add'>+		REG_WAIT(DOMAIN1_PG_STATUS,</div><div class='add'>+				DOMAIN1_PGFSM_PWR_STATUS, pwr_status,</div><div class='add'>+				1, 1000);</div><div class='add'>+		break;</div><div class='add'>+	case 1: /* DPP1 */</div><div class='add'>+		REG_UPDATE(DOMAIN3_PG_CONFIG,</div><div class='add'>+				DOMAIN3_POWER_GATE, power_gate);</div><div class='add'>+</div><div class='add'>+		REG_WAIT(DOMAIN3_PG_STATUS,</div><div class='add'>+				DOMAIN3_PGFSM_PWR_STATUS, pwr_status,</div><div class='add'>+				1, 1000);</div><div class='add'>+		break;</div><div class='add'>+	case 2: /* DPP2 */</div><div class='add'>+		REG_UPDATE(DOMAIN5_PG_CONFIG,</div><div class='add'>+				DOMAIN5_POWER_GATE, power_gate);</div><div class='add'>+</div><div class='add'>+		REG_WAIT(DOMAIN5_PG_STATUS,</div><div class='add'>+				DOMAIN5_PGFSM_PWR_STATUS, pwr_status,</div><div class='add'>+				1, 1000);</div><div class='add'>+		break;</div><div class='add'>+	case 3: /* DPP3 */</div><div class='add'>+		REG_UPDATE(DOMAIN7_PG_CONFIG,</div><div class='add'>+				DOMAIN7_POWER_GATE, power_gate);</div><div class='add'>+</div><div class='add'>+		REG_WAIT(DOMAIN7_PG_STATUS,</div><div class='add'>+				DOMAIN7_PGFSM_PWR_STATUS, pwr_status,</div><div class='add'>+				1, 1000);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h<br/>index eafcc4ea6d24..6c072d0274ea 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h</a></div><div class='hunk'>@@ -39,12 +39,14 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);</div><div class='ctx'> </div><div class='ctx'> unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);</div><div class='ctx'> </div><div class='del'>-void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn314_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='del'>-void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);</div><div class='add'>+void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);</div><div class='ctx'> </div><div class='ctx'> void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);</div><div class='ctx'> </div><div class='ctx'> void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal);</div><div class='ctx'> </div><div class='add'>+void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCN314_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c<br/>index 542ce3b7f9e4..79faab1125d4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c</a></div><div class='hunk'>@@ -42,6 +42,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -74,6 +75,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {</div><div class='ctx'> 	.set_avmute = dcn30_set_avmute,</div><div class='ctx'> 	.log_hw_state = dcn10_log_hw_state,</div><div class='ctx'> 	.get_hw_state = dcn10_get_hw_state,</div><div class='add'>+	.log_color_state = dcn30_log_color_state,</div><div class='ctx'> 	.clear_status_bits = dcn10_clear_status_bits,</div><div class='ctx'> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='ctx'> 	.edp_backlight_control = dce110_edp_backlight_control,</div><div class='hunk'>@@ -90,7 +92,6 @@ static const struct hw_sequencer_funcs dcn314_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -99,7 +100,6 @@ static const struct hw_sequencer_funcs dcn314_funcs = {</div><div class='ctx'> 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,</div><div class='ctx'> 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='del'>-	.power_down = dce110_power_down,</div><div class='ctx'> 	.set_backlight_level = dcn21_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='ctx'> 	.set_pipe = dcn21_set_pipe,</div><div class='hunk'>@@ -113,11 +113,13 @@ static const struct hw_sequencer_funcs dcn314_funcs = {</div><div class='ctx'> 	.optimize_pwr_state = dcn21_optimize_pwr_state,</div><div class='ctx'> 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='ctx'> 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='add'>+	.calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider,</div><div class='add'>+	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn314_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn30_set_input_transfer_func,</div><div class='hunk'>@@ -140,6 +142,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {</div><div class='ctx'> 	.enable_power_gating_plane = dcn314_enable_power_gating_plane,</div><div class='ctx'> 	.dpp_root_clock_control = dcn314_dpp_root_clock_control,</div><div class='ctx'> 	.hubp_pg_control = dcn31_hubp_pg_control,</div><div class='add'>+	.dpp_pg_control = dcn314_dpp_pg_control,</div><div class='ctx'> 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,</div><div class='ctx'> 	.update_odm = dcn314_update_odm,</div><div class='ctx'> 	.dsc_pg_control = dcn314_dsc_pg_control,</div><div class='hunk'>@@ -151,7 +154,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {</div><div class='ctx'> 	.set_shaper_3dlut = dcn20_set_shaper_3dlut,</div><div class='ctx'> 	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,</div><div class='ctx'> 	.calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,</div><div class='del'>-	.set_pixels_per_cycle = dcn314_set_pixels_per_cycle,</div><div class='ctx'> 	.resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c<br/>index c0b526cf1786..bf19ba65d09a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c</a></div><div class='hunk'>@@ -49,7 +49,7 @@</div><div class='ctx'> #include "dcn20/dcn20_optc.h"</div><div class='ctx'> #include "dce/dmub_hw_lock_mgr.h"</div><div class='ctx'> #include "dcn32/dcn32_resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "../dcn20/dcn20_hwseq.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='hunk'>@@ -60,8 +60,7 @@</div><div class='ctx'> #define REG(reg)\</div><div class='ctx'> 	hws-&gt;regs-&gt;reg</div><div class='ctx'> #define DC_LOGGER \</div><div class='del'>-	stream-&gt;ctx-&gt;logger</div><div class='del'>-</div><div class='add'>+	dc-&gt;ctx-&gt;logger</div><div class='ctx'> </div><div class='ctx'> #undef FN</div><div class='ctx'> #define FN(reg_name, field_name) \</div><div class='hunk'>@@ -75,17 +74,19 @@ void dcn32_dsc_pg_control(</div><div class='ctx'> 	uint32_t power_gate = power_on ? 0 : 1;</div><div class='ctx'> 	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='ctx'> 	uint32_t org_ip_request_cntl = 0;</div><div class='add'>+	struct dc *dc = hws-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='del'>-	if (hws-&gt;ctx-&gt;dc-&gt;debug.disable_dsc_power_gate)</div><div class='add'>+	if (dc-&gt;debug.disable_dsc_power_gate)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (!hws-&gt;ctx-&gt;dc-&gt;debug.enable_double_buffered_dsc_pg_support)</div><div class='add'>+	if (!dc-&gt;debug.enable_double_buffered_dsc_pg_support)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='ctx'> 	if (org_ip_request_cntl == 0)</div><div class='ctx'> 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);</div><div class='ctx'> </div><div class='add'>+	DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst);</div><div class='ctx'> 	switch (dsc_inst) {</div><div class='ctx'> 	case 0: /* DSC0 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN16_PG_CONFIG,</div><div class='hunk'>@@ -239,8 +240,10 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c</div><div class='ctx'> 	// Convert number of cache lines required to number of ways</div><div class='ctx'> 	if (dc-&gt;debug.force_mall_ss_num_ways &gt; 0) {</div><div class='ctx'> 		num_ways = dc-&gt;debug.force_mall_ss_num_ways;</div><div class='add'>+	} else if (dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes) {</div><div class='add'>+		num_ways = dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);</div><div class='ctx'> 	} else {</div><div class='del'>-		num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes);</div><div class='add'>+		num_ways = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return num_ways;</div><div class='hunk'>@@ -261,63 +264,64 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='ctx'> 		/* MALL SS messaging is not supported with PSR at this time */</div><div class='ctx'> 		if (dc-&gt;current_state-&gt;streams[i] != NULL &amp;&amp;</div><div class='del'>-				dc-&gt;current_state-&gt;streams[i]-&gt;link-&gt;psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)</div><div class='add'>+				dc-&gt;current_state-&gt;streams[i]-&gt;link-&gt;psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &amp;&amp;</div><div class='add'>+				(dc-&gt;current_state-&gt;stream_count &gt; 1 || (!dc-&gt;current_state-&gt;streams[i]-&gt;dpms_off &amp;&amp;</div><div class='add'>+						dc-&gt;current_state-&gt;stream_status[i].plane_count &gt; 0)))</div><div class='ctx'> 			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='del'>-		if (dc-&gt;current_state) {</div><div class='add'>+		/* 1. Check no memory request case for CAB.</div><div class='add'>+		 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message</div><div class='add'>+		 */</div><div class='add'>+		if (dcn32_check_no_memory_request_for_cab(dc)) {</div><div class='add'>+			/* Enable no-memory-requests case */</div><div class='add'>+			memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+			cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;</div><div class='add'>+			cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;</div><div class='add'>+			cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='ctx'> </div><div class='del'>-			/* 1. Check no memory request case for CAB.</div><div class='del'>-			 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message</div><div class='del'>-			 */</div><div class='del'>-			if (dcn32_check_no_memory_request_for_cab(dc)) {</div><div class='del'>-				/* Enable no-memory-requests case */</div><div class='del'>-				memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;</div><div class='del'>-				cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;</div><div class='del'>-				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='add'>+			dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='del'>-				dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-				return true;</div><div class='del'>-			}</div><div class='add'>+		/* 2. Check if all surfaces can fit in CAB.</div><div class='add'>+		 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message</div><div class='add'>+		 * and configure HUBP's to fetch from MALL</div><div class='add'>+		 */</div><div class='add'>+		ways = dcn32_calculate_cab_allocation(dc, dc-&gt;current_state);</div><div class='ctx'> </div><div class='del'>-			/* 2. Check if all surfaces can fit in CAB.</div><div class='del'>-			 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message</div><div class='del'>-			 * and configure HUBP's to fetch from MALL</div><div class='del'>-			 */</div><div class='del'>-			ways = dcn32_calculate_cab_allocation(dc, dc-&gt;current_state);</div><div class='add'>+		/* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,</div><div class='add'>+		 * or TMZ surface, don't try to enter MALL.</div><div class='add'>+		 */</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+			for (j = 0; j &lt; dc-&gt;current_state-&gt;stream_status[i].plane_count; j++) {</div><div class='add'>+				plane = dc-&gt;current_state-&gt;stream_status[i].plane_states[j];</div><div class='ctx'> </div><div class='del'>-			/* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,</div><div class='del'>-			 * or TMZ surface, don't try to enter MALL.</div><div class='del'>-			 */</div><div class='del'>-			for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='del'>-				for (j = 0; j &lt; dc-&gt;current_state-&gt;stream_status[i].plane_count; j++) {</div><div class='del'>-					plane = dc-&gt;current_state-&gt;stream_status[i].plane_states[j];</div><div class='del'>-</div><div class='del'>-					if (plane-&gt;address.type == PLN_ADDR_TYPE_GRPH_STEREO ||</div><div class='del'>-							plane-&gt;address.tmz_surface) {</div><div class='del'>-						mall_ss_unsupported = true;</div><div class='del'>-						break;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-				if (mall_ss_unsupported)</div><div class='add'>+				if (plane-&gt;address.type == PLN_ADDR_TYPE_GRPH_STEREO ||</div><div class='add'>+						plane-&gt;address.tmz_surface) {</div><div class='add'>+					mall_ss_unsupported = true;</div><div class='ctx'> 					break;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='del'>-			if (ways &lt;= dc-&gt;caps.cache_num_ways &amp;&amp; !mall_ss_unsupported) {</div><div class='del'>-				memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-				cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;</div><div class='del'>-				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;</div><div class='del'>-				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='del'>-				cmd.cab.cab_alloc_ways = (uint8_t)ways;</div><div class='del'>-</div><div class='del'>-				dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+			if (mall_ss_unsupported)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+		if (ways &lt;= dc-&gt;caps.cache_num_ways &amp;&amp; !mall_ss_unsupported) {</div><div class='add'>+			memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+			cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;</div><div class='add'>+			cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;</div><div class='add'>+			cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='add'>+			cmd.cab.cab_alloc_ways = (uint8_t)ways;</div><div class='ctx'> </div><div class='del'>-				return true;</div><div class='del'>-			}</div><div class='add'>+			dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+			DC_LOG_MALL("enable scanout from MALL");</div><div class='ctx'> </div><div class='add'>+			return true;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		DC_LOG_MALL("surface cannot fit in CAB, disabling scanout from MALL\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -437,6 +441,7 @@ bool dcn32_set_mpc_shaper_3dlut(</div><div class='ctx'> {</div><div class='ctx'> 	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> 	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> 	bool result = false;</div><div class='ctx'> </div><div class='hunk'>@@ -456,13 +461,13 @@ bool dcn32_set_mpc_shaper_3dlut(</div><div class='ctx'> 	if (stream-&gt;lut3d_func &amp;&amp;</div><div class='ctx'> 		stream-&gt;lut3d_func-&gt;state.bits.initialized == 1) {</div><div class='ctx'> </div><div class='del'>-		result = mpc-&gt;funcs-&gt;program_3dlut(mpc,</div><div class='del'>-								&amp;stream-&gt;lut3d_func-&gt;lut_3d,</div><div class='del'>-								mpcc_id);</div><div class='add'>+		result = mpc-&gt;funcs-&gt;program_3dlut(mpc,	&amp;stream-&gt;lut3d_func-&gt;lut_3d, mpcc_id);</div><div class='add'>+		if (!result)</div><div class='add'>+			DC_LOG_ERROR("%s: program_3dlut failed\n", __func__);</div><div class='ctx'> </div><div class='del'>-		result = mpc-&gt;funcs-&gt;program_shaper(mpc,</div><div class='del'>-								shaper_lut,</div><div class='del'>-								mpcc_id);</div><div class='add'>+		result = mpc-&gt;funcs-&gt;program_shaper(mpc, shaper_lut, mpcc_id);</div><div class='add'>+		if (!result)</div><div class='add'>+			DC_LOG_ERROR("%s: program_shaper failed\n", __func__);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='hunk'>@@ -475,39 +480,38 @@ bool dcn32_set_mcm_luts(</div><div class='ctx'> 	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='ctx'> 	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> 	bool result = true;</div><div class='del'>-	struct pwl_params *lut_params = NULL;</div><div class='add'>+	const struct pwl_params *lut_params = NULL;</div><div class='ctx'> </div><div class='ctx'> 	// 1D LUT</div><div class='del'>-	if (plane_state-&gt;blend_tf) {</div><div class='del'>-		if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			lut_params = &amp;plane_state-&gt;blend_tf-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='del'>-			cm3_helper_translate_curve_to_hw_format(plane_state-&gt;blend_tf,</div><div class='del'>-					&amp;dpp_base-&gt;regamma_params, false);</div><div class='del'>-			lut_params = &amp;dpp_base-&gt;regamma_params;</div><div class='del'>-		}</div><div class='add'>+	if (plane_state-&gt;blend_tf.type == TF_TYPE_HWPWL)</div><div class='add'>+		lut_params = &amp;plane_state-&gt;blend_tf.pwl;</div><div class='add'>+	else if (plane_state-&gt;blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		result = cm3_helper_translate_curve_to_hw_format(&amp;plane_state-&gt;blend_tf,</div><div class='add'>+				&amp;dpp_base-&gt;regamma_params, false);</div><div class='add'>+		if (!result)</div><div class='add'>+			return result;</div><div class='add'>+</div><div class='add'>+		lut_params = &amp;dpp_base-&gt;regamma_params;</div><div class='ctx'> 	}</div><div class='del'>-	result = mpc-&gt;funcs-&gt;program_1dlut(mpc, lut_params, mpcc_id);</div><div class='add'>+	mpc-&gt;funcs-&gt;program_1dlut(mpc, lut_params, mpcc_id);</div><div class='ctx'> 	lut_params = NULL;</div><div class='ctx'> </div><div class='ctx'> 	// Shaper</div><div class='del'>-	if (plane_state-&gt;in_shaper_func) {</div><div class='del'>-		if (plane_state-&gt;in_shaper_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			lut_params = &amp;plane_state-&gt;in_shaper_func-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;in_shaper_func-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='del'>-			// TODO: dpp_base replace</div><div class='del'>-			ASSERT(false);</div><div class='del'>-			cm3_helper_translate_curve_to_hw_format(plane_state-&gt;in_shaper_func,</div><div class='del'>-					&amp;dpp_base-&gt;shaper_params, true);</div><div class='del'>-			lut_params = &amp;dpp_base-&gt;shaper_params;</div><div class='del'>-		}</div><div class='add'>+	if (plane_state-&gt;in_shaper_func.type == TF_TYPE_HWPWL)</div><div class='add'>+		lut_params = &amp;plane_state-&gt;in_shaper_func.pwl;</div><div class='add'>+	else if (plane_state-&gt;in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		// TODO: dpp_base replace</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		cm3_helper_translate_curve_to_hw_format(&amp;plane_state-&gt;in_shaper_func,</div><div class='add'>+				&amp;dpp_base-&gt;shaper_params, true);</div><div class='add'>+		lut_params = &amp;dpp_base-&gt;shaper_params;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	result = mpc-&gt;funcs-&gt;program_shaper(mpc, lut_params, mpcc_id);</div><div class='add'>+	mpc-&gt;funcs-&gt;program_shaper(mpc, lut_params, mpcc_id);</div><div class='ctx'> </div><div class='ctx'> 	// 3D</div><div class='del'>-	if (plane_state-&gt;lut3d_func &amp;&amp; plane_state-&gt;lut3d_func-&gt;state.bits.initialized == 1)</div><div class='del'>-		result = mpc-&gt;funcs-&gt;program_3dlut(mpc, &amp;plane_state-&gt;lut3d_func-&gt;lut_3d, mpcc_id);</div><div class='add'>+	if (plane_state-&gt;lut3d_func.state.bits.initialized == 1)</div><div class='add'>+		result = mpc-&gt;funcs-&gt;program_3dlut(mpc, &amp;plane_state-&gt;lut3d_func.lut_3d, mpcc_id);</div><div class='ctx'> 	else</div><div class='ctx'> 		result = mpc-&gt;funcs-&gt;program_3dlut(mpc, NULL, mpcc_id);</div><div class='ctx'> </div><div class='hunk'>@@ -524,27 +528,24 @@ bool dcn32_set_input_transfer_func(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	enum dc_transfer_func_predefined tf;</div><div class='ctx'> 	bool result = true;</div><div class='del'>-	struct pwl_params *params = NULL;</div><div class='add'>+	const struct pwl_params *params = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (mpc == NULL || plane_state == NULL)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	tf = TRANSFER_FUNCTION_UNITY;</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func &amp;&amp;</div><div class='del'>-		plane_state-&gt;in_transfer_func-&gt;type == TF_TYPE_PREDEFINED)</div><div class='del'>-		tf = plane_state-&gt;in_transfer_func-&gt;tf;</div><div class='add'>+	if (plane_state-&gt;in_transfer_func.type == TF_TYPE_PREDEFINED)</div><div class='add'>+		tf = plane_state-&gt;in_transfer_func.tf;</div><div class='ctx'> </div><div class='ctx'> 	dpp_base-&gt;funcs-&gt;dpp_set_pre_degam(dpp_base, tf);</div><div class='ctx'> </div><div class='del'>-	if (plane_state-&gt;in_transfer_func) {</div><div class='del'>-		if (plane_state-&gt;in_transfer_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-			params = &amp;plane_state-&gt;in_transfer_func-&gt;pwl;</div><div class='del'>-		else if (plane_state-&gt;in_transfer_func-&gt;type == TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='del'>-			cm3_helper_translate_curve_to_hw_format(plane_state-&gt;in_transfer_func,</div><div class='del'>-					&amp;dpp_base-&gt;degamma_params, false))</div><div class='del'>-			params = &amp;dpp_base-&gt;degamma_params;</div><div class='del'>-	}</div><div class='add'>+	if (plane_state-&gt;in_transfer_func.type == TF_TYPE_HWPWL)</div><div class='add'>+		params = &amp;plane_state-&gt;in_transfer_func.pwl;</div><div class='add'>+	else if (plane_state-&gt;in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='add'>+		cm3_helper_translate_curve_to_hw_format(&amp;plane_state-&gt;in_transfer_func,</div><div class='add'>+				&amp;dpp_base-&gt;degamma_params, false))</div><div class='add'>+		params = &amp;dpp_base-&gt;degamma_params;</div><div class='ctx'> </div><div class='ctx'> 	dpp_base-&gt;funcs-&gt;dpp_program_gamcor_lut(dpp_base, params);</div><div class='ctx'> </div><div class='hunk'>@@ -562,29 +563,31 @@ bool dcn32_set_output_transfer_func(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='ctx'> 	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='del'>-	struct pwl_params *params = NULL;</div><div class='add'>+	const struct pwl_params *params = NULL;</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> </div><div class='ctx'> 	/* program OGAM or 3DLUT only for the top pipe*/</div><div class='ctx'> 	if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {</div><div class='ctx'> 		/*program shaper and 3dlut in MPC*/</div><div class='ctx'> 		ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);</div><div class='del'>-		if (ret == false &amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma &amp;&amp; stream-&gt;out_transfer_func) {</div><div class='del'>-			if (stream-&gt;out_transfer_func-&gt;type == TF_TYPE_HWPWL)</div><div class='del'>-				params = &amp;stream-&gt;out_transfer_func-&gt;pwl;</div><div class='del'>-			else if (pipe_ctx-&gt;stream-&gt;out_transfer_func-&gt;type ==</div><div class='add'>+		if (ret == false &amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma) {</div><div class='add'>+			if (stream-&gt;out_transfer_func.type == TF_TYPE_HWPWL)</div><div class='add'>+				params = &amp;stream-&gt;out_transfer_func.pwl;</div><div class='add'>+			else if (pipe_ctx-&gt;stream-&gt;out_transfer_func.type ==</div><div class='ctx'> 					TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='ctx'> 					cm3_helper_translate_curve_to_hw_format(</div><div class='del'>-					stream-&gt;out_transfer_func,</div><div class='add'>+					&amp;stream-&gt;out_transfer_func,</div><div class='ctx'> 					&amp;mpc-&gt;blender_params, false))</div><div class='ctx'> 				params = &amp;mpc-&gt;blender_params;</div><div class='ctx'> 			/* there are no ROM LUTs in OUTGAM */</div><div class='del'>-			if (stream-&gt;out_transfer_func-&gt;type == TF_TYPE_PREDEFINED)</div><div class='add'>+			if (stream-&gt;out_transfer_func.type == TF_TYPE_PREDEFINED)</div><div class='ctx'> 				BREAK_TO_DEBUGGER();</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='add'>+	if (mpc-&gt;funcs-&gt;set_output_gamma)</div><div class='add'>+		mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -603,9 +606,13 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+		struct dc_stream_status *stream_status = NULL;</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;stream)</div><div class='add'>+			stream_status = dc_state_get_stream_status(context, pipe-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe-&gt;stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||</div><div class='del'>-		    pipe-&gt;stream-&gt;fpo_in_use)) {</div><div class='add'>+		    (stream_status &amp;&amp; stream_status-&gt;fpo_in_use))) {</div><div class='ctx'> 			if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow)</div><div class='ctx'> 				hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow(hubp, false);</div><div class='ctx'> 			if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_force_cursor_pstate_disallow)</div><div class='hunk'>@@ -617,10 +624,32 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+		struct dc_stream_status *stream_status = NULL;</div><div class='add'>+		struct dc_stream_status *old_stream_status = NULL;</div><div class='add'>+</div><div class='add'>+		/* Today for MED update type we do not call update clocks. However, for FPO</div><div class='add'>+		 * the assumption is that update clocks should be called to disable P-State</div><div class='add'>+		 * switch before any HW programming since FPO in FW and driver are not</div><div class='add'>+		 * synchronized. This causes an issue where on a MED update, an FPO P-State</div><div class='add'>+		 * switch could be taking place, then driver forces P-State disallow in the below</div><div class='add'>+		 * code and prevents FPO from completing the sequence. In this case we add a check</div><div class='add'>+		 * to avoid re-programming (and thus re-setting) the P-State force register by</div><div class='add'>+		 * only reprogramming if the pipe was not previously Subvp or FPO. The assumption</div><div class='add'>+		 * is that the P-State force register should be programmed correctly the first</div><div class='add'>+		 * time SubVP / FPO was enabled, so there's no need to update / reset it if the</div><div class='add'>+		 * pipe config has never exited SubVP / FPO.</div><div class='add'>+		 */</div><div class='add'>+		if (pipe-&gt;stream)</div><div class='add'>+			stream_status = dc_state_get_stream_status(context, pipe-&gt;stream);</div><div class='add'>+		if (old_pipe-&gt;stream)</div><div class='add'>+			old_stream_status = dc_state_get_stream_status(dc-&gt;current_state, old_pipe-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||</div><div class='del'>-				pipe-&gt;stream-&gt;fpo_in_use)) {</div><div class='add'>+				(stream_status &amp;&amp; stream_status-&gt;fpo_in_use)) &amp;&amp;</div><div class='add'>+				(!old_pipe-&gt;stream || (dc_state_get_pipe_subvp_type(dc-&gt;current_state, old_pipe) != SUBVP_MAIN &amp;&amp;</div><div class='add'>+				(old_stream_status &amp;&amp; !old_stream_status-&gt;fpo_in_use)))) {</div><div class='ctx'> 			if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow)</div><div class='ctx'> 				hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow(hubp, true);</div><div class='ctx'> 			if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_force_cursor_pstate_disallow)</div><div class='hunk'>@@ -755,7 +784,7 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> 	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	// Initialize the dccg</div><div class='hunk'>@@ -782,7 +811,7 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;ref_clocks.xtalin_clock_inKhz =</div><div class='ctx'> 				dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency;</div><div class='ctx'> </div><div class='del'>-		if (res_pool-&gt;dccg &amp;&amp; res_pool-&gt;hubbub) {</div><div class='add'>+		if (res_pool-&gt;hubbub) {</div><div class='ctx'> 			(res_pool-&gt;dccg-&gt;funcs-&gt;get_dccg_ref_freq)(res_pool-&gt;dccg,</div><div class='ctx'> 					dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency,</div><div class='ctx'> 					&amp;res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz);</div><div class='hunk'>@@ -877,10 +906,10 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 				if (edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 						edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(edp_link-&gt;link_enc) &amp;&amp;</div><div class='ctx'> 						dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='del'>-						dc-&gt;hwss.power_down &amp;&amp;</div><div class='add'>+						hws-&gt;funcs.power_down &amp;&amp;</div><div class='ctx'> 						dc-&gt;hwss.edp_power_control) {</div><div class='ctx'> 					dc-&gt;hwss.edp_backlight_control(edp_link, false);</div><div class='del'>-					dc-&gt;hwss.power_down(dc);</div><div class='add'>+					hws-&gt;funcs.power_down(dc);</div><div class='ctx'> 					dc-&gt;hwss.edp_power_control(edp_link, false);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -890,8 +919,8 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 				if (link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 						link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc) &amp;&amp;</div><div class='del'>-						dc-&gt;hwss.power_down) {</div><div class='del'>-					dc-&gt;hwss.power_down(dc);</div><div class='add'>+						hws-&gt;funcs.power_down) {</div><div class='add'>+					hws-&gt;funcs.power_down(dc);</div><div class='ctx'> 					break;</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='hunk'>@@ -934,10 +963,11 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 	if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb) &amp;&amp; dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp;</div><div class='add'>+	    !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='hunk'>@@ -956,40 +986,29 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.psr;</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.subvp_psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.subvp_psr_support;</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.gecc_enable = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.gecc_enable;</div><div class='del'>-		dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch;</div><div class='del'>-</div><div class='del'>-		if (dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;fw_version &lt;</div><div class='del'>-		    DMUB_FW_VERSION(7, 0, 35)) {</div><div class='add'>+		dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver;</div><div class='add'>+		dc-&gt;caps.dmub_caps.aux_backlight_support = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.abm_aux_backlight_support;</div><div class='add'>+</div><div class='add'>+		/* for DCN401 testing only */</div><div class='add'>+		dc-&gt;caps.dmub_caps.fams_ver = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver;</div><div class='add'>+		if (dc-&gt;caps.dmub_caps.fams_ver == 2) {</div><div class='add'>+			/* FAMS2 is enabled */</div><div class='add'>+			dc-&gt;debug.fams2_config.bits.enable &amp;= true;</div><div class='add'>+		} else if (dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;fw_version &lt;</div><div class='add'>+				DMUB_FW_VERSION(7, 0, 35)) {</div><div class='add'>+			/* FAMS2 is disabled */</div><div class='add'>+			dc-&gt;debug.fams2_config.bits.enable = false;</div><div class='add'>+			if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;update_bw_bounding_box) {</div><div class='add'>+				/* update bounding box if FAMS2 disabled */</div><div class='add'>+				dc-&gt;res_pool-&gt;funcs-&gt;update_bw_bounding_box(dc, dc-&gt;clk_mgr-&gt;bw_params);</div><div class='add'>+			}</div><div class='ctx'> 			dc-&gt;debug.force_disable_subvp = true;</div><div class='ctx'> 			dc-&gt;debug.disable_fpo_optimizations = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,</div><div class='del'>-		int opp_cnt)</div><div class='del'>-{</div><div class='del'>-	bool hblank_halved = optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing);</div><div class='del'>-	int flow_ctrl_cnt;</div><div class='del'>-</div><div class='del'>-	if (opp_cnt &gt;= 2)</div><div class='del'>-		hblank_halved = true;</div><div class='del'>-</div><div class='del'>-	flow_ctrl_cnt = stream-&gt;timing.h_total - stream-&gt;timing.h_addressable -</div><div class='del'>-			stream-&gt;timing.h_border_left -</div><div class='del'>-			stream-&gt;timing.h_border_right;</div><div class='del'>-</div><div class='del'>-	if (hblank_halved)</div><div class='del'>-		flow_ctrl_cnt /= 2;</div><div class='del'>-</div><div class='del'>-	/* ODM combine 4:1 case */</div><div class='del'>-	if (opp_cnt == 4)</div><div class='del'>-		flow_ctrl_cnt /= 2;</div><div class='del'>-</div><div class='del'>-	return flow_ctrl_cnt;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='add'>+void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='ctx'> 	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='hunk'>@@ -1015,11 +1034,26 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		struct dsc_config dsc_cfg;</div><div class='del'>-		struct dsc_optc_config dsc_optc_cfg;</div><div class='add'>+		struct dsc_optc_config dsc_optc_cfg = {0};</div><div class='ctx'> 		enum optc_dsc_mode optc_dsc_mode;</div><div class='add'>+		struct dcn_dsc_state dsc_state = {0};</div><div class='add'>+</div><div class='add'>+		if (!dsc) {</div><div class='add'>+			DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dsc-&gt;funcs-&gt;dsc_read_state) {</div><div class='add'>+			dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='add'>+			if (!dsc_state.dsc_fw_en) {</div><div class='add'>+				DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		/* Enable DSC hw block */</div><div class='del'>-		dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='add'>+		dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding +</div><div class='add'>+				stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='ctx'> 		dsc_cfg.pic_height = stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_top + stream-&gt;timing.v_border_bottom;</div><div class='ctx'> 		dsc_cfg.pixel_encoding = stream-&gt;timing.pixel_encoding;</div><div class='ctx'> 		dsc_cfg.color_depth = stream-&gt;timing.display_color_depth;</div><div class='hunk'>@@ -1027,25 +1061,24 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='ctx'> 		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;</div><div class='add'>+		dsc_cfg.dsc_padding = pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='ctx'> </div><div class='add'>+		if (should_use_dto_dscclk)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, dsc-&gt;inst, dsc_cfg.dc_dsc_cfg.num_slices_h);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='del'>-		if (should_use_dto_dscclk)</div><div class='del'>-			dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, dsc-&gt;inst);</div><div class='ctx'> 		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 			struct display_stream_compressor *odm_dsc = odm_pipe-&gt;stream_res.dsc;</div><div class='ctx'> </div><div class='ctx'> 			ASSERT(odm_dsc);</div><div class='add'>+			if (!odm_dsc)</div><div class='add'>+				continue;</div><div class='add'>+			if (should_use_dto_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, odm_dsc-&gt;inst, dsc_cfg.dc_dsc_cfg.num_slices_h);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_set_config(odm_dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_enable(odm_dsc, odm_pipe-&gt;stream_res.opp-&gt;inst);</div><div class='del'>-			if (should_use_dto_dscclk)</div><div class='del'>-				dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, odm_dsc-&gt;inst);</div><div class='ctx'> 		}</div><div class='del'>-		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;</div><div class='del'>-		dsc_cfg.pic_width *= opp_cnt;</div><div class='del'>-</div><div class='ctx'> 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;</div><div class='del'>-</div><div class='ctx'> 		/* Enable DSC in OPTC */</div><div class='ctx'> 		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_dsc_config(pipe_ctx-&gt;stream_res.tg,</div><div class='hunk'>@@ -1058,15 +1091,11 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 				OPTC_DSC_DISABLED, 0, 0);</div><div class='ctx'> </div><div class='del'>-		/* disable DSC block */</div><div class='del'>-		if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='del'>-			dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, pipe_ctx-&gt;stream_res.dsc-&gt;inst);</div><div class='del'>-		dsc-&gt;funcs-&gt;dsc_disable(pipe_ctx-&gt;stream_res.dsc);</div><div class='add'>+		/* only disconnect DSC block, DSC is disabled when OPP head pipe is reset */</div><div class='add'>+		dsc-&gt;funcs-&gt;dsc_disconnect(pipe_ctx-&gt;stream_res.dsc);</div><div class='ctx'> 		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 			ASSERT(odm_pipe-&gt;stream_res.dsc);</div><div class='del'>-			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='del'>-				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, odm_pipe-&gt;stream_res.dsc-&gt;inst);</div><div class='del'>-			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(odm_pipe-&gt;stream_res.dsc);</div><div class='add'>+			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disconnect(odm_pipe-&gt;stream_res.dsc);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1103,10 +1132,8 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 0;</div><div class='ctx'> 	int opp_inst[MAX_PIPES] = {0};</div><div class='del'>-	bool rate_control_2x_pclk = (pipe_ctx-&gt;stream-&gt;timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&amp;pipe_ctx-&gt;stream-&gt;timing));</div><div class='del'>-	struct mpc_dwb_flow_control flow_control;</div><div class='del'>-	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='del'>-	int i;</div><div class='add'>+	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);</div><div class='add'>+	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);</div><div class='ctx'> </div><div class='ctx'> 	opp_cnt = get_odm_config(pipe_ctx, opp_inst);</div><div class='ctx'> </div><div class='hunk'>@@ -1114,44 +1141,31 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 				opp_inst, opp_cnt,</div><div class='del'>-				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='ctx'> 	else</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='ctx'> </div><div class='del'>-	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt &gt; 1;</div><div class='del'>-	flow_control.flow_ctrl_mode = 0;</div><div class='del'>-	flow_control.flow_ctrl_cnt0 = 0x80;</div><div class='del'>-	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx-&gt;stream, opp_cnt);</div><div class='del'>-	if (mpc-&gt;funcs-&gt;set_out_rate_control) {</div><div class='del'>-		for (i = 0; i &lt; opp_cnt; ++i) {</div><div class='del'>-			mpc-&gt;funcs-&gt;set_out_rate_control(</div><div class='del'>-					mpc, opp_inst[i],</div><div class='del'>-					true,</div><div class='del'>-					rate_control_2x_pclk,</div><div class='del'>-					&amp;flow_control);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 		odm_pipe-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='ctx'> 				odm_pipe-&gt;stream_res.opp,</div><div class='ctx'> 				true);</div><div class='add'>+		odm_pipe-&gt;stream_res.opp-&gt;funcs-&gt;opp_program_left_edge_extra_pixel(</div><div class='add'>+				odm_pipe-&gt;stream_res.opp,</div><div class='add'>+				pipe_ctx-&gt;stream-&gt;timing.pixel_encoding,</div><div class='add'>+				resource_is_pipe_type(odm_pipe, OTG_MASTER));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.dsc) {</div><div class='ctx'> 		struct pipe_ctx *current_pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[pipe_ctx-&gt;pipe_idx];</div><div class='ctx'> </div><div class='del'>-		update_dsc_on_stream(pipe_ctx, pipe_ctx-&gt;stream-&gt;timing.flags.DSC);</div><div class='add'>+		dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx-&gt;stream-&gt;timing.flags.DSC);</div><div class='ctx'> </div><div class='ctx'> 		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */</div><div class='ctx'> 		if (!pipe_ctx-&gt;next_odm_pipe &amp;&amp; current_pipe_ctx-&gt;next_odm_pipe &amp;&amp;</div><div class='ctx'> 				current_pipe_ctx-&gt;next_odm_pipe-&gt;stream_res.dsc) {</div><div class='ctx'> 			struct display_stream_compressor *dsc = current_pipe_ctx-&gt;next_odm_pipe-&gt;stream_res.dsc;</div><div class='del'>-			struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='ctx'> </div><div class='del'>-			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='del'>-				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, dsc-&gt;inst);</div><div class='ctx'> 			/* disconnect DSC block from stream */</div><div class='ctx'> 			dsc-&gt;funcs-&gt;dsc_disconnect(dsc);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1170,8 +1184,9 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	unsigned int odm_combine_factor = 0;</div><div class='ctx'> 	bool two_pix_per_container = false;</div><div class='add'>+	struct dce_hwseq *hws = stream-&gt;ctx-&gt;dc-&gt;hwseq;</div><div class='ctx'> </div><div class='del'>-	two_pix_per_container = optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing);</div><div class='add'>+	two_pix_per_container = pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing);</div><div class='ctx'> 	odm_combine_factor = get_odm_config(pipe_ctx, NULL);</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='hunk'>@@ -1190,7 +1205,8 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign</div><div class='ctx'> 		} else {</div><div class='ctx'> 			*k1_div = PIXEL_RATE_DIV_BY_1;</div><div class='ctx'> 			*k2_div = PIXEL_RATE_DIV_BY_4;</div><div class='del'>-			if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))</div><div class='add'>+			if ((odm_combine_factor == 2) || (hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy &amp;&amp;</div><div class='add'>+				hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)))</div><div class='ctx'> 				*k2_div = PIXEL_RATE_DIV_BY_2;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1201,38 +1217,49 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign</div><div class='ctx'> 	return odm_combine_factor;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn32_calculate_pix_rate_divider(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='del'>-	uint32_t pix_per_cycle = 1;</div><div class='del'>-	uint32_t odm_combine_factor = 1;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = NULL;</div><div class='add'>+	unsigned int k1_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	unsigned int k2_div = PIXEL_RATE_DIV_NA;</div><div class='ctx'> </div><div class='del'>-	if (!pipe_ctx || !pipe_ctx-&gt;stream || !pipe_ctx-&gt;stream_res.stream_enc)</div><div class='del'>-		return;</div><div class='add'>+	pipe_ctx = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, stream);</div><div class='ctx'> </div><div class='del'>-	odm_combine_factor = get_odm_config(pipe_ctx, NULL);</div><div class='del'>-	if (optc2_is_two_pixels_per_containter(&amp;pipe_ctx-&gt;stream-&gt;timing) || odm_combine_factor &gt; 1</div><div class='del'>-		|| dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))</div><div class='del'>-		pix_per_cycle = 2;</div><div class='add'>+	if (pipe_ctx) {</div><div class='add'>+</div><div class='add'>+		if (hws-&gt;funcs.calculate_dccg_k1_k2_values)</div><div class='add'>+			hws-&gt;funcs.calculate_dccg_k1_k2_values(pipe_ctx, &amp;k1_div, &amp;k2_div);</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;set_input_mode)</div><div class='del'>-		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;set_input_mode(pipe_ctx-&gt;stream_res.stream_enc,</div><div class='del'>-				pix_per_cycle);</div><div class='add'>+		pipe_ctx-&gt;pixel_rate_divider.div_factor1 = k1_div;</div><div class='add'>+		pipe_ctx-&gt;pixel_rate_divider.div_factor2 = k2_div;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)</div><div class='add'>+void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	struct pipe_ctx *pipe = NULL;</div><div class='ctx'> 	bool otg_disabled[MAX_PIPES] = {false};</div><div class='add'>+	struct dc_state *dc_state = NULL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (i &lt;= current_pipe_idx) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			dc_state = context;</div><div class='add'>+		} else {</div><div class='add'>+			pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			dc_state = dc-&gt;current_state;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!resource_is_pipe_type(pipe, OTG_MASTER))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if ((pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal))</div><div class='del'>-			&amp;&amp; dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) != SUBVP_PHANTOM) {</div><div class='add'>+			&amp;&amp; dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {</div><div class='ctx'> 			pipe-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe-&gt;stream_res.tg);</div><div class='ctx'> 			reset_sync_context_for_pipe(dc, context, i);</div><div class='ctx'> 			otg_disabled[i] = true;</div><div class='hunk'>@@ -1242,11 +1269,33 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_</div><div class='ctx'> 	hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;trigger_dio_fifo_resync(hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (otg_disabled[i])</div><div class='add'>+		if (i &lt;= current_pipe_idx)</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		else</div><div class='add'>+			pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (otg_disabled[i]) {</div><div class='add'>+			int opp_inst[MAX_PIPES] = { pipe-&gt;stream_res.opp-&gt;inst };</div><div class='add'>+			int opp_cnt = 1;</div><div class='add'>+			int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);</div><div class='add'>+			int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);</div><div class='add'>+			struct pipe_ctx *odm_pipe;</div><div class='add'>+</div><div class='add'>+			for (odm_pipe = pipe-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+				opp_inst[opp_cnt] = odm_pipe-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+				opp_cnt++;</div><div class='add'>+			}</div><div class='add'>+			if (opp_cnt &gt; 1)</div><div class='add'>+				pipe-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='add'>+						pipe-&gt;stream_res.tg,</div><div class='add'>+						opp_inst, opp_cnt,</div><div class='add'>+						odm_slice_width,</div><div class='add'>+						last_odm_slice_width);</div><div class='ctx'> 			pipe-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipe-&gt;stream_res.tg);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	dc_trigger_sync(dc, dc-&gt;current_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='hunk'>@@ -1257,9 +1306,10 @@ void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='ctx'> 	struct dce_hwseq *hws = link-&gt;dc-&gt;hwseq;</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='del'>-	uint32_t pix_per_cycle = 1;</div><div class='ctx'> </div><div class='ctx'> 	params.opp_cnt = 1;</div><div class='add'>+	params.pix_per_cycle = pipe_ctx-&gt;stream_res.pix_clk_params.dio_se_pix_per_cycle;</div><div class='add'>+</div><div class='ctx'> 	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='ctx'> 		params.opp_cnt++;</div><div class='ctx'> </div><div class='hunk'>@@ -1274,13 +1324,14 @@ void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.hpo_dp_stream_enc,</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='ctx'> 	} else if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='del'>-		if (optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing) || params.opp_cnt &gt; 1</div><div class='del'>-			|| dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing) ||</div><div class='add'>+			params.opp_cnt &gt; 1) {</div><div class='ctx'> 			params.timing.pix_clk_100hz /= 2;</div><div class='del'>-			pix_per_cycle = 2;</div><div class='add'>+			params.pix_per_cycle = 2;</div><div class='ctx'> 		}</div><div class='del'>-		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_odm_combine(</div><div class='del'>-				pipe_ctx-&gt;stream_res.stream_enc, pix_per_cycle &gt; 1);</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_odm_combine)</div><div class='add'>+			pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_odm_combine(</div><div class='add'>+				pipe_ctx-&gt;stream_res.stream_enc, params.pix_per_cycle &gt; 1);</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_unblank(link, pipe_ctx-&gt;stream_res.stream_enc, &amp;params);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1356,12 +1407,12 @@ void dcn32_disable_link_output(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	link_hwss-&gt;disable_link_output(link, link_res, signal);</div><div class='ctx'> 	link-&gt;phy_state.symclk_state = SYMCLK_OFF_TX_OFF;</div><div class='del'>-</div><div class='del'>-	if (signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='del'>-			link-&gt;dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='del'>-			!link-&gt;skip_implict_edp_power_control)</div><div class='del'>-		link-&gt;dc-&gt;hwss.edp_power_control(link, false);</div><div class='del'>-	else if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;lock_phy)</div><div class='add'>+	/*</div><div class='add'>+	 * Add the logic to extract BOTH power up and power down sequences</div><div class='add'>+	 * from enable/disable link output and only call edp panel control</div><div class='add'>+	 * in enable_link_dp and disable_link_dp once.</div><div class='add'>+	 */</div><div class='add'>+	if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;unlock_phy)</div><div class='ctx'> 		dmcu-&gt;funcs-&gt;unlock_phy(dmcu);</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);</div><div class='hunk'>@@ -1570,7 +1621,7 @@ void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> 		if (hws-&gt;funcs.resync_fifo_dccg_dio)</div><div class='del'>-			hws-&gt;funcs.resync_fifo_dccg_dio(hws, dc, context);</div><div class='add'>+			hws-&gt;funcs.resync_fifo_dccg_dio(hws, dc, context, i);</div><div class='ctx'> #endif</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1586,7 +1637,7 @@ void dcn32_init_blank(</div><div class='ctx'> 	struct output_pixel_processor *opp = NULL;</div><div class='ctx'> 	struct output_pixel_processor *bottom_opp = NULL;</div><div class='ctx'> 	uint32_t num_opps, opp_id_src0, opp_id_src1;</div><div class='del'>-	uint32_t otg_active_width, otg_active_height;</div><div class='add'>+	uint32_t otg_active_width = 0, otg_active_height = 0;</div><div class='ctx'> 	uint32_t i;</div><div class='ctx'> </div><div class='ctx'> 	/* program opp dpg blank color */</div><div class='hunk'>@@ -1658,50 +1709,26 @@ void dcn32_init_blank(</div><div class='ctx'> 		hws-&gt;funcs.wait_for_blank_complete(opp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn32_blank_phantom(struct dc *dc,</div><div class='del'>-		struct timing_generator *tg,</div><div class='del'>-		int width,</div><div class='del'>-		int height)</div><div class='add'>+/* phantom stream id's can change often, but can be identical between contexts.</div><div class='add'>+*  This function checks for the condition the streams are identical to avoid</div><div class='add'>+*  redundant pipe transitions.</div><div class='add'>+*/</div><div class='add'>+static bool is_subvp_phantom_topology_transition_seamless(</div><div class='add'>+	const struct dc_state *cur_ctx,</div><div class='add'>+	const struct dc_state *new_ctx,</div><div class='add'>+	const struct pipe_ctx *cur_pipe,</div><div class='add'>+	const struct pipe_ctx *new_pipe)</div><div class='ctx'> {</div><div class='del'>-	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='del'>-	enum dc_color_space color_space;</div><div class='del'>-	struct tg_color black_color = {0};</div><div class='del'>-	struct output_pixel_processor *opp = NULL;</div><div class='del'>-	uint32_t num_opps, opp_id_src0, opp_id_src1;</div><div class='del'>-	uint32_t otg_active_width, otg_active_height;</div><div class='del'>-	uint32_t i;</div><div class='add'>+	enum mall_stream_type cur_pipe_type = dc_state_get_pipe_subvp_type(cur_ctx, cur_pipe);</div><div class='add'>+	enum mall_stream_type new_pipe_type = dc_state_get_pipe_subvp_type(new_ctx, new_pipe);</div><div class='ctx'> </div><div class='del'>-	/* program opp dpg blank color */</div><div class='del'>-	color_space = COLOR_SPACE_SRGB;</div><div class='del'>-	color_space_to_black_color(dc, color_space, &amp;black_color);</div><div class='del'>-</div><div class='del'>-	otg_active_width = width;</div><div class='del'>-	otg_active_height = height;</div><div class='del'>-</div><div class='del'>-	/* get the OPTC source */</div><div class='del'>-	tg-&gt;funcs-&gt;get_optc_source(tg, &amp;num_opps, &amp;opp_id_src0, &amp;opp_id_src1);</div><div class='del'>-	ASSERT(opp_id_src0 &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_opp);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_opp; i++) {</div><div class='del'>-		if (dc-&gt;res_pool-&gt;opps[i] != NULL &amp;&amp; dc-&gt;res_pool-&gt;opps[i]-&gt;inst == opp_id_src0) {</div><div class='del'>-			opp = dc-&gt;res_pool-&gt;opps[i];</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (opp &amp;&amp; opp-&gt;funcs-&gt;opp_set_disp_pattern_generator)</div><div class='del'>-		opp-&gt;funcs-&gt;opp_set_disp_pattern_generator(</div><div class='del'>-				opp,</div><div class='del'>-				CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,</div><div class='del'>-				CONTROLLER_DP_COLOR_SPACE_UDEFINED,</div><div class='del'>-				COLOR_DEPTH_UNDEFINED,</div><div class='del'>-				&amp;black_color,</div><div class='del'>-				otg_active_width,</div><div class='del'>-				otg_active_height,</div><div class='del'>-				0);</div><div class='add'>+	const struct dc_stream_state *cur_paired_stream = dc_state_get_paired_subvp_stream(cur_ctx, cur_pipe-&gt;stream);</div><div class='add'>+	const struct dc_stream_state *new_paired_stream = dc_state_get_paired_subvp_stream(new_ctx, new_pipe-&gt;stream);</div><div class='ctx'> </div><div class='del'>-	if (tg-&gt;funcs-&gt;is_tg_enabled(tg))</div><div class='del'>-		hws-&gt;funcs.wait_for_blank_complete(opp);</div><div class='add'>+	return cur_pipe_type == SUBVP_PHANTOM &amp;&amp;</div><div class='add'>+			cur_pipe_type == new_pipe_type &amp;&amp;</div><div class='add'>+			cur_paired_stream &amp;&amp; new_paired_stream &amp;&amp;</div><div class='add'>+			cur_paired_stream-&gt;stream_id == new_paired_stream-&gt;stream_id;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,</div><div class='hunk'>@@ -1722,7 +1749,8 @@ bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,</div><div class='ctx'> 			continue;</div><div class='ctx'> 		else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {</div><div class='ctx'> 			if (resource_is_pipe_type(new_pipe, OTG_MASTER))</div><div class='del'>-				if (cur_pipe-&gt;stream-&gt;stream_id == new_pipe-&gt;stream-&gt;stream_id)</div><div class='add'>+				if (cur_pipe-&gt;stream-&gt;stream_id == new_pipe-&gt;stream-&gt;stream_id ||</div><div class='add'>+						is_subvp_phantom_topology_transition_seamless(cur_ctx, new_ctx, cur_pipe, new_pipe))</div><div class='ctx'> 				/* OTG master with the same stream is seamless */</div><div class='ctx'> 					continue;</div><div class='ctx'> 		} else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {</div><div class='hunk'>@@ -1808,3 +1836,13 @@ void dcn32_interdependent_update_lock(struct dc *dc,</div><div class='ctx'> 			dc-&gt;hwss.pipe_control_lock(dc, pipe, false);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn32_program_outstanding_updates(struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+</div><div class='add'>+	/* update compbuf if required */</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_compbuf_size)</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_compbuf_size(hubbub, context-&gt;bw_ctx.bw.dcn.compbuf_size_kb, true);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h<br/>index f55c11fc56ec..0303a5953673 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h</a></div><div class='hunk'>@@ -71,11 +71,11 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='ctx'> void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='del'>-unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);</div><div class='add'>+void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);</div><div class='ctx'> </div><div class='del'>-void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);</div><div class='add'>+unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);</div><div class='ctx'> </div><div class='del'>-void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context);</div><div class='add'>+void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);</div><div class='ctx'> </div><div class='ctx'> void dcn32_subvp_pipe_control_lock(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='hunk'>@@ -91,6 +91,8 @@ void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> </div><div class='ctx'> bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='add'>+void dcn32_calculate_pix_rate_divider(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> void dcn32_disable_link_output(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		enum signal_type signal);</div><div class='hunk'>@@ -117,11 +119,6 @@ void dcn32_init_blank(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct timing_generator *tg);</div><div class='ctx'> </div><div class='del'>-void dcn32_blank_phantom(struct dc *dc,</div><div class='del'>-		struct timing_generator *tg,</div><div class='del'>-		int width,</div><div class='del'>-		int height);</div><div class='del'>-</div><div class='ctx'> bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,</div><div class='ctx'> 		const struct dc_state *cur_ctx,</div><div class='ctx'> 		const struct dc_state *new_ctx);</div><div class='hunk'>@@ -131,4 +128,8 @@ void dcn32_prepare_bandwidth(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> void dcn32_interdependent_update_lock(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context, bool lock);</div><div class='add'>+</div><div class='add'>+void dcn32_program_outstanding_updates(struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCN32_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c<br/>index 67d661dbd5b7..c19ef075c882 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c</a></div><div class='hunk'>@@ -30,6 +30,7 @@</div><div class='ctx'> #include "dcn30/dcn30_hwseq.h"</div><div class='ctx'> #include "dcn31/dcn31_hwseq.h"</div><div class='ctx'> #include "dcn32/dcn32_hwseq.h"</div><div class='add'>+#include "dcn401/dcn401_hwseq.h"</div><div class='ctx'> #include "dcn32_init.h"</div><div class='ctx'> </div><div class='ctx'> static const struct hw_sequencer_funcs dcn32_funcs = {</div><div class='hunk'>@@ -38,6 +39,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -86,7 +88,6 @@ static const struct hw_sequencer_funcs dcn32_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -97,7 +98,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='ctx'> 	.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,</div><div class='ctx'> 	.does_plane_fit_in_mall = NULL,</div><div class='del'>-	.set_backlight_level = dcn21_set_backlight_level,</div><div class='add'>+	.set_backlight_level = dcn31_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='ctx'> 	.hardware_release = dcn30_hardware_release,</div><div class='ctx'> 	.set_pipe = dcn21_set_pipe,</div><div class='hunk'>@@ -116,13 +117,15 @@ static const struct hw_sequencer_funcs dcn32_funcs = {</div><div class='ctx'> 	.update_phantom_vp_position = dcn32_update_phantom_vp_position,</div><div class='ctx'> 	.update_dsc_pg = dcn32_update_dsc_pg,</div><div class='ctx'> 	.apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,</div><div class='del'>-	.blank_phantom = dcn32_blank_phantom,</div><div class='ctx'> 	.is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,</div><div class='add'>+	.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,</div><div class='add'>+	.program_outstanding_updates = dcn32_program_outstanding_updates,</div><div class='add'>+	.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn32_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn10_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn32_set_input_transfer_func,</div><div class='hunk'>@@ -157,7 +160,6 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {</div><div class='ctx'> 	.update_force_pstate = dcn32_update_force_pstate,</div><div class='ctx'> 	.update_mall_sel = dcn32_update_mall_sel,</div><div class='ctx'> 	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,</div><div class='del'>-	.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,</div><div class='ctx'> 	.resync_fifo_dccg_dio = dcn32_resync_fifo_dccg_dio,</div><div class='ctx'> 	.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,</div><div class='ctx'> 	.apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c<br/>index 4b92df23ff0d..7aa0f452e8f7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c</a></div><div class='hunk'>@@ -46,7 +46,7 @@</div><div class='ctx'> #include "link_hwss.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "dce/dmub_outbox.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn10/dcn10_hwseq.h"</div><div class='ctx'> #include "inc/link_enc_cfg.h"</div><div class='ctx'> #include "dcn30/dcn30_vpg.h"</div><div class='hunk'>@@ -113,6 +113,14 @@ static void enable_memory_low_power(struct dc *dc)</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log)</div><div class='add'>+{</div><div class='add'>+	if (dc-&gt;debug.enable_pg_cntl_debug_logs &amp;&amp; dc-&gt;res_pool-&gt;pg_cntl) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;print_pg_status)</div><div class='add'>+			dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;print_pg_status(dc-&gt;res_pool-&gt;pg_cntl, debug_func, debug_log);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	REG_UPDATE_3(DMU_CLK_CNTL,</div><div class='hunk'>@@ -137,6 +145,8 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	print_pg_status(dc, __func__, ": start");</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='hunk'>@@ -147,37 +157,6 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 		hws-&gt;funcs.bios_golden_init(dc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!dc-&gt;debug.disable_clock_gate) {</div><div class='del'>-		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);</div><div class='del'>-		REG_WRITE(DCCG_GATE_DISABLE_CNTL2,  0);</div><div class='del'>-</div><div class='del'>-		/* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */</div><div class='del'>-		REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-				PHYBSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-				PHYCSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-				PHYDSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-				PHYESYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='del'>-</div><div class='del'>-		REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL4,</div><div class='del'>-				DPIASYMCLK0_GATE_DISABLE, 0,</div><div class='del'>-				DPIASYMCLK1_GATE_DISABLE, 0,</div><div class='del'>-				DPIASYMCLK2_GATE_DISABLE, 0,</div><div class='del'>-				DPIASYMCLK3_GATE_DISABLE, 0);</div><div class='del'>-</div><div class='del'>-		REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0xFFFFFFFF);</div><div class='del'>-		REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,</div><div class='del'>-				DTBCLK_P0_GATE_DISABLE, 0,</div><div class='del'>-				DTBCLK_P1_GATE_DISABLE, 0,</div><div class='del'>-				DTBCLK_P2_GATE_DISABLE, 0,</div><div class='del'>-				DTBCLK_P3_GATE_DISABLE, 0);</div><div class='del'>-		REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,</div><div class='del'>-				DPSTREAMCLK0_GATE_DISABLE, 0,</div><div class='del'>-				DPSTREAMCLK1_GATE_DISABLE, 0,</div><div class='del'>-				DPSTREAMCLK2_GATE_DISABLE, 0,</div><div class='del'>-				DPSTREAMCLK3_GATE_DISABLE, 0);</div><div class='del'>-</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	// Initialize the dccg</div><div class='ctx'> 	if (res_pool-&gt;dccg-&gt;funcs-&gt;dccg_init)</div><div class='ctx'> 		res_pool-&gt;dccg-&gt;funcs-&gt;dccg_init(res_pool-&gt;dccg);</div><div class='hunk'>@@ -188,7 +167,7 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;ref_clocks.xtalin_clock_inKhz =</div><div class='ctx'> 				dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency;</div><div class='ctx'> </div><div class='del'>-		if (res_pool-&gt;dccg &amp;&amp; res_pool-&gt;hubbub) {</div><div class='add'>+		if (res_pool-&gt;hubbub) {</div><div class='ctx'> </div><div class='ctx'> 			(res_pool-&gt;dccg-&gt;funcs-&gt;get_dccg_ref_freq)(res_pool-&gt;dccg,</div><div class='ctx'> 				dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency,</div><div class='hunk'>@@ -231,11 +210,8 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 	/* we want to turn off all dp displays before doing detection */</div><div class='ctx'> 	dc-&gt;link_srv-&gt;blank_all_dp_displays(dc);</div><div class='del'>-/*</div><div class='del'>-	if (hws-&gt;funcs.enable_power_gating_plane)</div><div class='del'>-		hws-&gt;funcs.enable_power_gating_plane(dc-&gt;hwseq, true);</div><div class='del'>-*/</div><div class='del'>-	if (res_pool-&gt;hubbub-&gt;funcs-&gt;dchubbub_init)</div><div class='add'>+</div><div class='add'>+	if (res_pool-&gt;hubbub &amp;&amp; res_pool-&gt;hubbub-&gt;funcs-&gt;dchubbub_init)</div><div class='ctx'> 		res_pool-&gt;hubbub-&gt;funcs-&gt;dchubbub_init(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> 	/* If taking control over from VBIOS, we may want to optimize our first</div><div class='ctx'> 	 * mode set, so we need to skip powering down pipes until we know which</div><div class='hunk'>@@ -267,11 +243,13 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		hws-&gt;funcs.init_pipes(dc, dc-&gt;current_state);</div><div class='del'>-		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;allow_self_refresh_control)</div><div class='add'>+		print_pg_status(dc, __func__, ": after init_pipes");</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;allow_self_refresh_control &amp;&amp;</div><div class='add'>+			!dc-&gt;res_pool-&gt;hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter)</div><div class='ctx'> 			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;allow_self_refresh_control(dc-&gt;res_pool-&gt;hubbub,</div><div class='ctx'> 					!dc-&gt;res_pool-&gt;hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; res_pool-&gt;audio_count; i++) {</div><div class='ctx'> 		struct audio *audio = res_pool-&gt;audios[i];</div><div class='ctx'> </div><div class='hunk'>@@ -305,20 +283,6 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 	if (!dc-&gt;debug.disable_clock_gate) {</div><div class='ctx'> 		/* enable all DCN clock gating */</div><div class='del'>-		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);</div><div class='del'>-</div><div class='del'>-		REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKB_FE_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKC_FE_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKD_FE_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKE_FE_GATE_DISABLE, 0);</div><div class='del'>-		REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0);</div><div class='del'>-		REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKB_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKC_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKD_GATE_DISABLE, 0,</div><div class='del'>-				SYMCLKE_GATE_DISABLE, 0);</div><div class='del'>-</div><div class='ctx'> 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -328,10 +292,10 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 	if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb) &amp;&amp; dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks(dc-&gt;res_pool-&gt;hubbub);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk &amp;&amp; !dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;set_hard_max_memclk(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -349,36 +313,15 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dmub_srv) {</div><div class='ctx'> 		dc_dmub_srv_query_caps_cmd(dc-&gt;ctx-&gt;dmub_srv);</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.psr;</div><div class='del'>-		dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch;</div><div class='add'>+		dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver;</div><div class='add'>+		dc-&gt;caps.dmub_caps.aux_backlight_support = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.abm_aux_backlight_support;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;pg_cntl) {</div><div class='ctx'> 		if (dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;init_pg_status)</div><div class='ctx'> 			dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;init_pg_status(dc-&gt;res_pool-&gt;pg_cntl);</div><div class='ctx'> 	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,</div><div class='del'>-		int opp_cnt)</div><div class='del'>-{</div><div class='del'>-	bool hblank_halved = optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing);</div><div class='del'>-	int flow_ctrl_cnt;</div><div class='del'>-</div><div class='del'>-	if (opp_cnt &gt;= 2)</div><div class='del'>-		hblank_halved = true;</div><div class='del'>-</div><div class='del'>-	flow_ctrl_cnt = stream-&gt;timing.h_total - stream-&gt;timing.h_addressable -</div><div class='del'>-			stream-&gt;timing.h_border_left -</div><div class='del'>-			stream-&gt;timing.h_border_right;</div><div class='del'>-</div><div class='del'>-	if (hblank_halved)</div><div class='del'>-		flow_ctrl_cnt /= 2;</div><div class='del'>-</div><div class='del'>-	/* ODM combine 4:1 case */</div><div class='del'>-	if (opp_cnt == 4)</div><div class='del'>-		flow_ctrl_cnt /= 2;</div><div class='del'>-</div><div class='del'>-	return flow_ctrl_cnt;</div><div class='add'>+	print_pg_status(dc, __func__, ": after init_pg_status");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='hunk'>@@ -396,9 +339,22 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		struct dsc_config dsc_cfg;</div><div class='del'>-		struct dsc_optc_config dsc_optc_cfg;</div><div class='add'>+		struct dsc_optc_config dsc_optc_cfg = {0};</div><div class='ctx'> 		enum optc_dsc_mode optc_dsc_mode;</div><div class='add'>+		struct dcn_dsc_state dsc_state = {0};</div><div class='ctx'> </div><div class='add'>+		if (!dsc) {</div><div class='add'>+			DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dsc-&gt;funcs-&gt;dsc_read_state) {</div><div class='add'>+			dsc-&gt;funcs-&gt;dsc_read_state(dsc, &amp;dsc_state);</div><div class='add'>+			if (!dsc_state.dsc_fw_en) {</div><div class='add'>+				DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		/* Enable DSC hw block */</div><div class='ctx'> 		dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='ctx'> 		dsc_cfg.pic_height = stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_top + stream-&gt;timing.v_border_bottom;</div><div class='hunk'>@@ -408,6 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='ctx'> 		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;</div><div class='add'>+		dsc_cfg.dsc_padding = pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='ctx'> </div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='hunk'>@@ -474,8 +431,8 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 0;</div><div class='ctx'> 	int opp_inst[MAX_PIPES] = {0};</div><div class='del'>-	bool rate_control_2x_pclk = (pipe_ctx-&gt;stream-&gt;timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&amp;pipe_ctx-&gt;stream-&gt;timing));</div><div class='del'>-	struct mpc_dwb_flow_control flow_control;</div><div class='add'>+	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);</div><div class='add'>+	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);</div><div class='ctx'> 	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -485,22 +442,18 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg,</div><div class='ctx'> 				opp_inst, opp_cnt,</div><div class='del'>-				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='ctx'> 	else</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='ctx'> </div><div class='del'>-	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt &gt; 1;</div><div class='del'>-	flow_control.flow_ctrl_mode = 0;</div><div class='del'>-	flow_control.flow_ctrl_cnt0 = 0x80;</div><div class='del'>-	flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx-&gt;stream, opp_cnt);</div><div class='ctx'> 	if (mpc-&gt;funcs-&gt;set_out_rate_control) {</div><div class='ctx'> 		for (i = 0; i &lt; opp_cnt; ++i) {</div><div class='ctx'> 			mpc-&gt;funcs-&gt;set_out_rate_control(</div><div class='ctx'> 					mpc, opp_inst[i],</div><div class='del'>-					true,</div><div class='del'>-					rate_control_2x_pclk,</div><div class='del'>-					&amp;flow_control);</div><div class='add'>+					false,</div><div class='add'>+					0,</div><div class='add'>+					NULL);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -536,95 +489,26 @@ void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_dsc_pg_control(</div><div class='del'>-		struct dce_hwseq *hws,</div><div class='del'>-		unsigned int dsc_inst,</div><div class='del'>-		bool power_on)</div><div class='add'>+void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on)</div><div class='ctx'> {</div><div class='del'>-	uint32_t power_gate = power_on ? 0 : 1;</div><div class='del'>-	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='del'>-	uint32_t org_ip_request_cntl = 0;</div><div class='del'>-</div><div class='del'>-	if (hws-&gt;ctx-&gt;dc-&gt;debug.disable_dsc_power_gate)</div><div class='del'>-		return;</div><div class='del'>-	if (hws-&gt;ctx-&gt;dc-&gt;debug.ignore_pg)</div><div class='add'>+	if (!hws-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.dpstream)</div><div class='ctx'> 		return;</div><div class='del'>-	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='del'>-	if (org_ip_request_cntl == 0)</div><div class='del'>-		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);</div><div class='del'>-</div><div class='del'>-	switch (dsc_inst) {</div><div class='del'>-	case 0: /* DSC0 */</div><div class='del'>-		REG_UPDATE(DOMAIN16_PG_CONFIG,</div><div class='del'>-				DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-</div><div class='del'>-		REG_WAIT(DOMAIN16_PG_STATUS,</div><div class='del'>-				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='del'>-		break;</div><div class='del'>-	case 1: /* DSC1 */</div><div class='del'>-		REG_UPDATE(DOMAIN17_PG_CONFIG,</div><div class='del'>-				DOMAIN_POWER_GATE, power_gate);</div><div class='ctx'> </div><div class='del'>-		REG_WAIT(DOMAIN17_PG_STATUS,</div><div class='del'>-				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='del'>-		break;</div><div class='del'>-	case 2: /* DSC2 */</div><div class='del'>-		REG_UPDATE(DOMAIN18_PG_CONFIG,</div><div class='del'>-				DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-</div><div class='del'>-		REG_WAIT(DOMAIN18_PG_STATUS,</div><div class='del'>-				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='del'>-		break;</div><div class='del'>-	case 3: /* DSC3 */</div><div class='del'>-		REG_UPDATE(DOMAIN19_PG_CONFIG,</div><div class='del'>-				DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-</div><div class='del'>-		REG_WAIT(DOMAIN19_PG_STATUS,</div><div class='del'>-				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BREAK_TO_DEBUGGER();</div><div class='del'>-		break;</div><div class='add'>+	if (hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dpstreamclk_root_clock_gating) {</div><div class='add'>+		hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dpstreamclk_root_clock_gating(</div><div class='add'>+			hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg, dp_hpo_inst, clock_on);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	if (org_ip_request_cntl == 0)</div><div class='del'>-		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)</div><div class='add'>+void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on)</div><div class='ctx'> {</div><div class='del'>-	bool force_on = true; /* disable power gating */</div><div class='del'>-	uint32_t org_ip_request_cntl = 0;</div><div class='del'>-</div><div class='del'>-	if (hws-&gt;ctx-&gt;dc-&gt;debug.disable_hubp_power_gate)</div><div class='del'>-		return;</div><div class='del'>-	if (hws-&gt;ctx-&gt;dc-&gt;debug.ignore_pg)</div><div class='add'>+	if (!hws-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.physymclk)</div><div class='ctx'> 		return;</div><div class='del'>-	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='del'>-	if (org_ip_request_cntl == 0)</div><div class='del'>-		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);</div><div class='del'>-	/* DCHUBP0/1/2/3/4/5 */</div><div class='del'>-	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-	/* DPP0/1/2/3/4/5 */</div><div class='del'>-	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-</div><div class='del'>-	force_on = true; /* disable power gating */</div><div class='del'>-	if (enable &amp;&amp; !hws-&gt;ctx-&gt;dc-&gt;debug.disable_dsc_power_gate)</div><div class='del'>-		force_on = false;</div><div class='del'>-</div><div class='del'>-	/* DCS0/1/2/3/4 */</div><div class='del'>-	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);</div><div class='del'>-</div><div class='ctx'> </div><div class='add'>+	if (hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_physymclk_root_clock_gating) {</div><div class='add'>+		hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_physymclk_root_clock_gating(</div><div class='add'>+			hws-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg, phy_inst, clock_on);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* In headless boot cases, DIG may be turned</div><div class='hunk'>@@ -646,10 +530,10 @@ void dcn35_power_down_on_boot(struct dc *dc)</div><div class='ctx'> 	if (edp_link &amp;&amp; edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 			edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(edp_link-&gt;link_enc) &amp;&amp;</div><div class='ctx'> 			dc-&gt;hwseq-&gt;funcs.edp_backlight_control &amp;&amp;</div><div class='del'>-			dc-&gt;hwss.power_down &amp;&amp;</div><div class='add'>+			dc-&gt;hwseq-&gt;funcs.power_down &amp;&amp;</div><div class='ctx'> 			dc-&gt;hwss.edp_power_control) {</div><div class='ctx'> 		dc-&gt;hwseq-&gt;funcs.edp_backlight_control(edp_link, false);</div><div class='del'>-		dc-&gt;hwss.power_down(dc);</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.power_down(dc);</div><div class='ctx'> 		dc-&gt;hwss.edp_power_control(edp_link, false);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='hunk'>@@ -657,8 +541,8 @@ void dcn35_power_down_on_boot(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 			if (link-&gt;link_enc &amp;&amp; link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='ctx'> 					link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc) &amp;&amp;</div><div class='del'>-					dc-&gt;hwss.power_down) {</div><div class='del'>-				dc-&gt;hwss.power_down(dc);</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.power_down) {</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.power_down(dc);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='hunk'>@@ -679,22 +563,43 @@ void dcn35_power_down_on_boot(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> {</div><div class='del'>-	struct dc_link *edp_links[MAX_NUM_EDP];</div><div class='del'>-	int i, edp_num;</div><div class='ctx'> 	if (dc-&gt;debug.dmcub_emulation)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='del'>-		dc_get_edp_links(dc, edp_links, &amp;edp_num);</div><div class='del'>-		if (edp_num == 0 || edp_num &gt; 1)</div><div class='del'>-			return false;</div><div class='add'>+		uint32_t num_active_edp = 0;</div><div class='add'>+		int i;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; ++i) {</div><div class='ctx'> 			struct dc_stream_state *stream = dc-&gt;current_state-&gt;streams[i];</div><div class='add'>+			struct dc_link *link = stream-&gt;link;</div><div class='add'>+			bool is_psr = link &amp;&amp; !link-&gt;panel_config.psr.disable_psr &amp;&amp;</div><div class='add'>+				      (link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1 ||</div><div class='add'>+				       link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1);</div><div class='add'>+			bool is_replay = link &amp;&amp; link-&gt;replay_settings.replay_feature_enabled;</div><div class='add'>+</div><div class='add'>+			/* Ignore streams that disabled. */</div><div class='add'>+			if (stream-&gt;dpms_off)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			/* Active external displays block idle optimizations. */</div><div class='add'>+			if (!dc_is_embedded_signal(stream-&gt;signal))</div><div class='add'>+				return false;</div><div class='ctx'> </div><div class='del'>-			if (!stream-&gt;dpms_off &amp;&amp; !dc_is_embedded_signal(stream-&gt;signal))</div><div class='add'>+			/* If not PWRSEQ0 can't enter idle optimizations */</div><div class='add'>+			if (link &amp;&amp; link-&gt;link_index != 0)</div><div class='ctx'> 				return false;</div><div class='add'>+</div><div class='add'>+			/* Check for panel power features required for idle optimizations. */</div><div class='add'>+			if (!is_psr &amp;&amp; !is_replay)</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='add'>+			num_active_edp += 1;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		/* If more than one active eDP then disallow. */</div><div class='add'>+		if (num_active_edp &gt; 1)</div><div class='add'>+			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// TODO: review other cases when idle optimization is allowed</div><div class='hunk'>@@ -720,6 +625,7 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='ctx'> 	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='ctx'> 	bool can_apply_seamless_boot = false;</div><div class='add'>+	bool tg_enabled[MAX_PIPES] = {false};</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		if (context-&gt;streams[i]-&gt;apply_seamless_boot_optimization) {</div><div class='hunk'>@@ -766,6 +672,8 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		if (hubbub &amp;&amp; hubp) {</div><div class='ctx'> 			if (hubbub-&gt;funcs-&gt;program_det_size)</div><div class='ctx'> 				hubbub-&gt;funcs-&gt;program_det_size(hubbub, hubp-&gt;inst, 0);</div><div class='add'>+			if (hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+				hubbub-&gt;funcs-&gt;program_det_segments(hubbub, hubp-&gt;inst, 0);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -801,12 +709,14 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			// requesting data while in PSR.</div><div class='ctx'> 			tg-&gt;funcs-&gt;tg_init(tg);</div><div class='ctx'> 			hubp-&gt;power_gated = true;</div><div class='add'>+			tg_enabled[i] = true;</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Disable on the current state so the new one isn't cleared. */</div><div class='ctx'> 		pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_reset(hubp);</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_reset(dpp);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg = tg;</div><div class='hunk'>@@ -842,11 +752,26 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		tg-&gt;funcs-&gt;tg_init(tg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Clean up MPC tree */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (tg_enabled[i]) {</div><div class='add'>+			if (dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list) {</div><div class='add'>+				if (dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list-&gt;mpcc_bot) {</div><div class='add'>+					int bot_id = dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list-&gt;mpcc_bot-&gt;mpcc_id;</div><div class='add'>+</div><div class='add'>+					if ((bot_id &lt; MAX_MPCC) &amp;&amp; (bot_id &lt; MAX_PIPES) &amp;&amp; (!tg_enabled[bot_id]))</div><div class='add'>+						dc-&gt;res_pool-&gt;opps[i]-&gt;mpc_tree_params.opp_list = NULL;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (pg_cntl != NULL) {</div><div class='ctx'> 		if (pg_cntl-&gt;funcs-&gt;dsc_pg_control != NULL) {</div><div class='ctx'> 			uint32_t num_opps = 0;</div><div class='ctx'> 			uint32_t opp_id_src0 = OPP_ID_INVALID;</div><div class='ctx'> 			uint32_t opp_id_src1 = OPP_ID_INVALID;</div><div class='add'>+			uint32_t optc_dsc_state = 0;</div><div class='ctx'> </div><div class='ctx'> 			// Step 1: To find out which OPTC is running &amp; OPTC DSC is ON</div><div class='ctx'> 			// We can't use res_pool-&gt;res_cap-&gt;num_timing_generator to check</div><div class='hunk'>@@ -855,7 +780,6 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			// Some ASICs would be fused display pipes less than the default setting.</div><div class='ctx'> 			// In dcnxx_resource_construct function, driver would obatin real information.</div><div class='ctx'> 			for (i = 0; i &lt; dc-&gt;res_pool-&gt;timing_generator_count; i++) {</div><div class='del'>-				uint32_t optc_dsc_state = 0;</div><div class='ctx'> 				struct timing_generator *tg = dc-&gt;res_pool-&gt;timing_generators[i];</div><div class='ctx'> </div><div class='ctx'> 				if (tg-&gt;funcs-&gt;is_tg_enabled(tg)) {</div><div class='hunk'>@@ -870,15 +794,18 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			// Step 2: To power down DSC but skip DSC  of running OPTC</div><div class='add'>+			// Step 2: To power down DSC but skip DSC of running OPTC</div><div class='ctx'> 			for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++) {</div><div class='ctx'> 				struct dcn_dsc_state s  = {0};</div><div class='ctx'> </div><div class='del'>-				dc-&gt;res_pool-&gt;dscs[i]-&gt;funcs-&gt;dsc_read_state(dc-&gt;res_pool-&gt;dscs[i], &amp;s);</div><div class='add'>+				/* avoid reading DSC state when it is not in use as it may be power gated */</div><div class='add'>+				if (optc_dsc_state) {</div><div class='add'>+					dc-&gt;res_pool-&gt;dscs[i]-&gt;funcs-&gt;dsc_read_state(dc-&gt;res_pool-&gt;dscs[i], &amp;s);</div><div class='ctx'> </div><div class='del'>-				if ((s.dsc_opp_source == opp_id_src0 || s.dsc_opp_source == opp_id_src1) &amp;&amp;</div><div class='del'>-					s.dsc_clock_en &amp;&amp; s.dsc_fw_en)</div><div class='del'>-					continue;</div><div class='add'>+					if ((s.dsc_opp_source == opp_id_src0 || s.dsc_opp_source == opp_id_src1) &amp;&amp;</div><div class='add'>+						s.dsc_clock_en &amp;&amp; s.dsc_fw_en)</div><div class='add'>+						continue;</div><div class='add'>+				}</div><div class='ctx'> </div><div class='ctx'> 				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, dc-&gt;res_pool-&gt;dscs[i]-&gt;inst, false);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -889,12 +816,15 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			       struct dc_state *context)</div><div class='ctx'> {</div><div class='add'>+	struct dpp *dpp = pipe_ctx-&gt;plane_res.dpp;</div><div class='add'>+</div><div class='ctx'> 	/* enable DCFCLK current DCHUB */</div><div class='ctx'> 	pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_clk_cntl(pipe_ctx-&gt;plane_res.hubp, true);</div><div class='ctx'> </div><div class='ctx'> 	/* initialize HUBP on power up */</div><div class='ctx'> 	pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_init(pipe_ctx-&gt;plane_res.hubp);</div><div class='del'>-</div><div class='add'>+	/*make sure DPPCLK is on*/</div><div class='add'>+	dpp-&gt;funcs-&gt;dpp_dppclk_control(dpp, false, true);</div><div class='ctx'> 	/* make sure OPP_PIPE_CLOCK_EN = 1 */</div><div class='ctx'> 	pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.opp,</div><div class='hunk'>@@ -911,6 +841,7 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		// Program system aperture settings</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_set_vm_system_aperture_settings(pipe_ctx-&gt;plane_res.hubp, &amp;apt);</div><div class='ctx'> 	}</div><div class='add'>+	//DC_LOG_DEBUG("%s: dpp_inst(%d) =\n", __func__, dpp-&gt;inst);</div><div class='ctx'> </div><div class='ctx'> 	if (!pipe_ctx-&gt;top_pipe</div><div class='ctx'> 		&amp;&amp; pipe_ctx-&gt;plane_state</div><div class='hunk'>@@ -927,6 +858,7 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='ctx'> 	struct dpp *dpp = pipe_ctx-&gt;plane_res.dpp;</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> 	dc-&gt;hwss.wait_for_mpcc_disconnect(dc, dc-&gt;res_pool, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	/* In flip immediate with pipe splitting case GSL is used for</div><div class='hunk'>@@ -943,9 +875,10 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	hubp-&gt;funcs-&gt;hubp_clk_cntl(hubp, false);</div><div class='ctx'> </div><div class='ctx'> 	dpp-&gt;funcs-&gt;dpp_dppclk_control(dpp, false, false);</div><div class='del'>-/*to do, need to support both case*/</div><div class='add'>+</div><div class='ctx'> 	hubp-&gt;power_gated = true;</div><div class='ctx'> </div><div class='add'>+	hubp-&gt;funcs-&gt;hubp_reset(hubp);</div><div class='ctx'> 	dpp-&gt;funcs-&gt;dpp_reset(dpp);</div><div class='ctx'> </div><div class='ctx'> 	pipe_ctx-&gt;stream = NULL;</div><div class='hunk'>@@ -954,6 +887,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	pipe_ctx-&gt;top_pipe = NULL;</div><div class='ctx'> 	pipe_ctx-&gt;bottom_pipe = NULL;</div><div class='ctx'> 	pipe_ctx-&gt;plane_state = NULL;</div><div class='add'>+	//DC_LOG_DEBUG("%s: dpp_inst(%d)=\n", __func__, dpp-&gt;inst);</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)</div><div class='hunk'>@@ -1016,19 +951,42 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		if (pipe_ctx-&gt;plane_res.hubp)</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_HUBP][pipe_ctx-&gt;plane_res.hubp-&gt;inst] = false;</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;plane_res.dpp)</div><div class='add'>+		if (pipe_ctx-&gt;plane_res.dpp &amp;&amp; pipe_ctx-&gt;plane_res.hubp)</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_DPP][pipe_ctx-&gt;plane_res.hubp-&gt;inst] = false;</div><div class='ctx'> </div><div class='del'>-		if ((pipe_ctx-&gt;plane_res.dpp || pipe_ctx-&gt;stream_res.opp) &amp;&amp;</div><div class='del'>-			pipe_ctx-&gt;plane_res.mpcc_inst &gt;= 0)</div><div class='add'>+		if (pipe_ctx-&gt;plane_res.dpp || pipe_ctx-&gt;stream_res.opp)</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_MPCC][pipe_ctx-&gt;plane_res.mpcc_inst] = false;</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;stream_res.dsc)</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.dsc) {</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_DSC][pipe_ctx-&gt;stream_res.dsc-&gt;inst] = false;</div><div class='add'>+			if (dc-&gt;caps.sequential_ono) {</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_HUBP][pipe_ctx-&gt;stream_res.dsc-&gt;inst] = false;</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_DPP][pipe_ctx-&gt;stream_res.dsc-&gt;inst] = false;</div><div class='add'>+</div><div class='add'>+				/* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */</div><div class='add'>+				if (!pipe_ctx-&gt;top_pipe &amp;&amp; pipe_ctx-&gt;plane_res.hubp &amp;&amp;</div><div class='add'>+				    pipe_ctx-&gt;plane_res.hubp-&gt;inst != pipe_ctx-&gt;stream_res.dsc-&gt;inst) {</div><div class='add'>+					for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; ++j) {</div><div class='add'>+						update_state-&gt;pg_pipe_res_update[PG_HUBP][j] = false;</div><div class='add'>+						update_state-&gt;pg_pipe_res_update[PG_DPP][j] = false;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.opp)</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_OPP][pipe_ctx-&gt;stream_res.opp-&gt;inst] = false;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc)</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_DPSTREAM][pipe_ctx-&gt;stream_res.hpo_dp_stream_enc-&gt;inst] = false;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='add'>+		update_state-&gt;pg_pipe_res_update[PG_PHYSYMCLK][dc-&gt;links[i]-&gt;link_enc_hw_inst] = true;</div><div class='add'>+		if (dc-&gt;links[i]-&gt;type != dc_connection_none)</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_PHYSYMCLK][dc-&gt;links[i]-&gt;link_enc_hw_inst] = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;timing_generator_count; i++) {</div><div class='ctx'> 		struct timing_generator *tg = dc-&gt;res_pool-&gt;timing_generators[i];</div><div class='hunk'>@@ -1046,6 +1004,19 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		update_state-&gt;pg_pipe_res_update[PG_OPTC][0] = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;caps.sequential_ono) {</div><div class='add'>+		for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='add'>+			if (!update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			    !update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+				for (j = i - 1; j &gt;= 0; j--) {</div><div class='add'>+					update_state-&gt;pg_pipe_res_update[PG_HUBP][j] = false;</div><div class='add'>+					update_state-&gt;pg_pipe_res_update[PG_DPP][j] = false;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='hunk'>@@ -1065,7 +1036,8 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if ((!cur_pipe-&gt;plane_state &amp;&amp; new_pipe-&gt;plane_state) ||</div><div class='del'>-			(!cur_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream)) {</div><div class='add'>+			(!cur_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream) ||</div><div class='add'>+			(cur_pipe-&gt;stream != new_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream)) {</div><div class='ctx'> 			// New pipe addition</div><div class='ctx'> 			for (j = 0; j &lt; PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) {</div><div class='ctx'> 				if (j == PG_HUBP &amp;&amp; new_pipe-&gt;plane_res.hubp)</div><div class='hunk'>@@ -1085,6 +1057,9 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> </div><div class='ctx'> 				if (j == PG_OPTC &amp;&amp; new_pipe-&gt;stream_res.tg)</div><div class='ctx'> 					update_state-&gt;pg_pipe_res_update[j][new_pipe-&gt;stream_res.tg-&gt;inst] = true;</div><div class='add'>+</div><div class='add'>+				if (j == PG_DPSTREAM &amp;&amp; new_pipe-&gt;stream_res.hpo_dp_stream_enc)</div><div class='add'>+					update_state-&gt;pg_pipe_res_update[j][new_pipe-&gt;stream_res.hpo_dp_stream_enc-&gt;inst] = true;</div><div class='ctx'> 			}</div><div class='ctx'> 		} else if (cur_pipe-&gt;plane_state == new_pipe-&gt;plane_state ||</div><div class='ctx'> 				cur_pipe == new_pipe) {</div><div class='hunk'>@@ -1114,10 +1089,19 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 					cur_pipe-&gt;stream_res.tg != new_pipe-&gt;stream_res.tg &amp;&amp;</div><div class='ctx'> 					new_pipe-&gt;stream_res.tg)</div><div class='ctx'> 					update_state-&gt;pg_pipe_res_update[j][new_pipe-&gt;stream_res.tg-&gt;inst] = true;</div><div class='add'>+</div><div class='add'>+				if (j == PG_DPSTREAM &amp;&amp;</div><div class='add'>+					cur_pipe-&gt;stream_res.hpo_dp_stream_enc != new_pipe-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='add'>+					new_pipe-&gt;stream_res.hpo_dp_stream_enc)</div><div class='add'>+					update_state-&gt;pg_pipe_res_update[j][new_pipe-&gt;stream_res.hpo_dp_stream_enc-&gt;inst] = true;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; dc-&gt;link_count; i++)</div><div class='add'>+		if (dc-&gt;links[i]-&gt;type != dc_connection_none)</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_PHYSYMCLK][dc-&gt;links[i]-&gt;link_enc_hw_inst] = true;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;hpo_dp_stream_enc_count; i++) {</div><div class='ctx'> 		if (context-&gt;res_ctx.is_hpo_dp_stream_enc_acquired[i] &amp;&amp;</div><div class='ctx'> 				dc-&gt;res_pool-&gt;hpo_dp_stream_enc[i]) {</div><div class='hunk'>@@ -1129,6 +1113,41 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	if (hpo_frl_stream_enc_acquired || hpo_dp_stream_enc_acquired)</div><div class='ctx'> 		update_state-&gt;pg_res_update[PG_HPO] = true;</div><div class='ctx'> </div><div class='add'>+	if (hpo_frl_stream_enc_acquired)</div><div class='add'>+		update_state-&gt;pg_pipe_res_update[PG_HDMISTREAM][0] = true;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.sequential_ono) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			struct pipe_ctx *new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+			if (new_pipe-&gt;stream_res.dsc &amp;&amp; !new_pipe-&gt;top_pipe &amp;&amp;</div><div class='add'>+			    update_state-&gt;pg_pipe_res_update[PG_DSC][new_pipe-&gt;stream_res.dsc-&gt;inst]) {</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_HUBP][new_pipe-&gt;stream_res.dsc-&gt;inst] = true;</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_DPP][new_pipe-&gt;stream_res.dsc-&gt;inst] = true;</div><div class='add'>+</div><div class='add'>+				/* All HUBP/DPP instances must be powered if the DSC inst != HUBP inst */</div><div class='add'>+				if (new_pipe-&gt;plane_res.hubp &amp;&amp;</div><div class='add'>+				    new_pipe-&gt;plane_res.hubp-&gt;inst != new_pipe-&gt;stream_res.dsc-&gt;inst) {</div><div class='add'>+					for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; ++j) {</div><div class='add'>+						update_state-&gt;pg_pipe_res_update[PG_HUBP][j] = true;</div><div class='add'>+						update_state-&gt;pg_pipe_res_update[PG_DPP][j] = true;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			    update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+				for (j = i - 1; j &gt;= 0; j--) {</div><div class='add'>+					update_state-&gt;pg_pipe_res_update[PG_HUBP][j] = true;</div><div class='add'>+					update_state-&gt;pg_pipe_res_update[PG_DPP][j] = true;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1149,6 +1168,8 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'>  *	ONO Region 2, DCPG 24: mpc opp optc dwb</div><div class='ctx'>  *	ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED. will be pwr dwn after lono timer is armed</div><div class='ctx'>  *</div><div class='add'>+ * If sequential ONO is specified the order is modified from ONO Region 11 -&gt; ONO Region 0 descending.</div><div class='add'>+ *</div><div class='ctx'>  * @dc: Current DC state</div><div class='ctx'>  * @update_state: update PG sequence states for HW block</div><div class='ctx'>  */</div><div class='hunk'>@@ -1168,19 +1189,35 @@ void dcn35_hw_block_power_down(struct dc *dc,</div><div class='ctx'> 			pg_cntl-&gt;funcs-&gt;hpo_pg_control(pg_cntl, false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='del'>-			update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='del'>-			if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, false);</div><div class='add'>+	if (!dc-&gt;caps.sequential_ono) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			    update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+				if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='add'>+					pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, false);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++)</div><div class='del'>-		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='del'>-			if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, false);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+				if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+					pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, false);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='add'>+	} else {</div><div class='add'>+		for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+				if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+					pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, false);</div><div class='add'>+			}</div><div class='ctx'> </div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			    update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+				if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='add'>+					pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, false);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/*this will need all the clients to unregister optc interruts let dmubfw handle this*/</div><div class='ctx'> 	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='hunk'>@@ -1208,6 +1245,8 @@ void dcn35_hw_block_power_down(struct dc *dc,</div><div class='ctx'>  *	ONO Region 10, DCPG 3: dchubp3, dpp3</div><div class='ctx'>  *	ONO Region 3, DCPG 25: hpo - SKIPPED</div><div class='ctx'>  *</div><div class='add'>+ * If sequential ONO is specified the order is modified from ONO Region 0 -&gt; ONO Region 11 ascending.</div><div class='add'>+ *</div><div class='ctx'>  * @dc: Current DC state</div><div class='ctx'>  * @update_state: update PG sequence states for HW block</div><div class='ctx'>  */</div><div class='hunk'>@@ -1226,11 +1265,13 @@ void dcn35_hw_block_power_up(struct dc *dc,</div><div class='ctx'> 	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='ctx'> 		pg_cntl-&gt;funcs-&gt;plane_otg_pg_control(pg_cntl, true);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++)</div><div class='del'>-		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='del'>-			if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, true);</div><div class='del'>-		}</div><div class='add'>+	if (!dc-&gt;caps.sequential_ono) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++)</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+				if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+					pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, true);</div><div class='add'>+			}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='hunk'>@@ -1238,6 +1279,13 @@ void dcn35_hw_block_power_up(struct dc *dc,</div><div class='ctx'> 			if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='ctx'> 				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, true);</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;caps.sequential_ono) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+				if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+					pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, true);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (update_state-&gt;pg_res_update[PG_HPO]) {</div><div class='ctx'> 		if (pg_cntl-&gt;funcs-&gt;hpo_pg_control)</div><div class='hunk'>@@ -1253,14 +1301,24 @@ void dcn35_root_clock_control(struct dc *dc,</div><div class='ctx'> 	if (!pg_cntl)</div><div class='ctx'> 		return;</div><div class='ctx'> 	/*enable root clock first when power up*/</div><div class='del'>-	if (power_on)</div><div class='add'>+	if (power_on) {</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='ctx'> 				update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='ctx'> 				if (dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control)</div><div class='ctx'> 					dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='ctx'> 			}</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_DPSTREAM][i])</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.dpstream_root_clock_control)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.dpstream_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;dig_link_enc_count; i++)</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_PHYSYMCLK][i])</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.physymclk_root_clock_control)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.physymclk_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='add'>+</div><div class='add'>+	}</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++) {</div><div class='ctx'> 		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='ctx'> 			if (power_on) {</div><div class='hunk'>@@ -1273,14 +1331,24 @@ void dcn35_root_clock_control(struct dc *dc,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	/*disable root clock first when power down*/</div><div class='del'>-	if (!power_on)</div><div class='add'>+	if (!power_on) {</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='ctx'> 				update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='ctx'> 				if (dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control)</div><div class='ctx'> 					dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='ctx'> 			}</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_DPSTREAM][i])</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.dpstream_root_clock_control)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.dpstream_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;dig_link_enc_count; i++)</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_PHYSYMCLK][i])</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.physymclk_root_clock_control)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.physymclk_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='add'>+</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_prepare_bandwidth(</div><div class='hunk'>@@ -1300,6 +1368,8 @@ void dcn35_prepare_bandwidth(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dcn20_prepare_bandwidth(dc, context);</div><div class='add'>+</div><div class='add'>+	print_pg_status(dc, __func__, ": after rcg and power up");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_optimize_bandwidth(</div><div class='hunk'>@@ -1308,6 +1378,8 @@ void dcn35_optimize_bandwidth(</div><div class='ctx'> {</div><div class='ctx'> 	struct pg_block_update pg_update_state;</div><div class='ctx'> </div><div class='add'>+	print_pg_status(dc, __func__, ": before rcg and power up");</div><div class='add'>+</div><div class='ctx'> 	dcn20_optimize_bandwidth(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;hwss.calc_blocks_to_gate) {</div><div class='hunk'>@@ -1319,22 +1391,8 @@ void dcn35_optimize_bandwidth(</div><div class='ctx'> 		if (dc-&gt;hwss.root_clock_control)</div><div class='ctx'> 			dc-&gt;hwss.root_clock_control(dc, &amp;pg_update_state, false);</div><div class='ctx'> 	}</div><div class='del'>-}</div><div class='ctx'> </div><div class='del'>-void dcn35_set_idle_state(const struct dc *dc, bool allow_idle)</div><div class='del'>-{</div><div class='del'>-	// TODO: Find a more suitable communcation</div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;set_idle_state)</div><div class='del'>-		dc-&gt;clk_mgr-&gt;funcs-&gt;set_idle_state(dc-&gt;clk_mgr, allow_idle);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-uint32_t dcn35_get_idle_state(const struct dc *dc)</div><div class='del'>-{</div><div class='del'>-	// TODO: Find a more suitable communcation</div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;funcs-&gt;get_idle_state)</div><div class='del'>-		return dc-&gt;clk_mgr-&gt;funcs-&gt;get_idle_state(dc-&gt;clk_mgr);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	print_pg_status(dc, __func__, ": after rcg and power up");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='hunk'>@@ -1353,11 +1411,16 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 	params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_pipes; i++) {</div><div class='del'>-		if ((pipe_ctx[i]-&gt;stream_res.tg != NULL) &amp;&amp; pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs) {</div><div class='del'>-			struct dc_crtc_timing *timing = &amp;pipe_ctx[i]-&gt;stream-&gt;timing;</div><div class='del'>-			struct dc *dc = pipe_ctx[i]-&gt;stream-&gt;ctx-&gt;dc;</div><div class='add'>+		/* dc_state_destruct() might null the stream resources, so fetch tg</div><div class='add'>+		 * here first to avoid a race condition. The lifetime of the pointee</div><div class='add'>+		 * itself (the timing_generator object) is not a problem here.</div><div class='add'>+		 */</div><div class='add'>+		struct timing_generator *tg = pipe_ctx[i]-&gt;stream_res.tg;</div><div class='ctx'> </div><div class='del'>-			if (dc-&gt;debug.static_screen_wait_frames) {</div><div class='add'>+		if ((tg != NULL) &amp;&amp; tg-&gt;funcs) {</div><div class='add'>+			if (pipe_ctx[i]-&gt;stream &amp;&amp; pipe_ctx[i]-&gt;stream-&gt;ctx-&gt;dc-&gt;debug.static_screen_wait_frames) {</div><div class='add'>+				struct dc_crtc_timing *timing = &amp;pipe_ctx[i]-&gt;stream-&gt;timing;</div><div class='add'>+				struct dc *dc = pipe_ctx[i]-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 				unsigned int frame_rate = timing-&gt;pix_clk_100hz / (timing-&gt;h_total * timing-&gt;v_total);</div><div class='ctx'> </div><div class='ctx'> 				if (frame_rate &gt;= 120 &amp;&amp; dc-&gt;caps.ips_support &amp;&amp;</div><div class='hunk'>@@ -1366,14 +1429,11 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 					num_frames = 2 * (frame_rate % 60);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='del'>-			if (pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='del'>-				pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='del'>-					pipe_ctx[i]-&gt;stream_res.tg, &amp;params);</div><div class='add'>+			set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]-&gt;stream, &amp;params);</div><div class='ctx'> 			if (adjust.v_total_max != 0 &amp;&amp; adjust.v_total_min != 0)</div><div class='del'>-				if (pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='del'>-					pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='del'>-						pipe_ctx[i]-&gt;stream_res.tg,</div><div class='del'>-						event_triggers, num_frames);</div><div class='add'>+				if (tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='add'>+					tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='add'>+						tg, event_triggers, num_frames);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1394,3 +1454,275 @@ void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 			set_static_screen_control(pipe_ctx[i]-&gt;stream_res.tg,</div><div class='ctx'> 					triggers, params-&gt;num_frames);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,</div><div class='add'>+		int num_pipes, uint32_t v_total_min, uint32_t v_total_max)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	struct long_vtotal_params params = {0};</div><div class='add'>+</div><div class='add'>+	params.vertical_total_max = v_total_max;</div><div class='add'>+	params.vertical_total_min = v_total_min;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_pipes; i++) {</div><div class='add'>+		if (!pipe_ctx[i])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx[i]-&gt;stream) {</div><div class='add'>+			struct dc_crtc_timing *timing = &amp;pipe_ctx[i]-&gt;stream-&gt;timing;</div><div class='add'>+</div><div class='add'>+			if (timing)</div><div class='add'>+				params.vertical_blank_start = timing-&gt;v_total - timing-&gt;v_front_porch;</div><div class='add'>+			else</div><div class='add'>+				params.vertical_blank_start = 0;</div><div class='add'>+</div><div class='add'>+			if ((pipe_ctx[i]-&gt;stream_res.tg != NULL) &amp;&amp; pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs &amp;&amp;</div><div class='add'>+				pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_long_vtotal)</div><div class='add'>+				pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_long_vtotal(pipe_ctx[i]-&gt;stream_res.tg, &amp;params);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	/* Calculate average pixel count per TU, return false if under ~2.00 to</div><div class='add'>+	 * avoid empty TUs. This is only required for DPIA tunneling as empty TUs</div><div class='add'>+	 * are legal to generate for native DP links. Assume TU size 64 as there</div><div class='add'>+	 * is currently no scenario where it's reprogrammed from HW default.</div><div class='add'>+	 * MTPs have no such limitation, so this does not affect MST use cases.</div><div class='add'>+	 */</div><div class='add'>+	unsigned int pix_clk_mhz;</div><div class='add'>+	unsigned int symclk_mhz;</div><div class='add'>+	unsigned int avg_pix_per_tu_x1000;</div><div class='add'>+	unsigned int tu_size_bytes = 64;</div><div class='add'>+	struct dc_crtc_timing *timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+	struct dc_link_settings *link_settings = &amp;pipe_ctx-&gt;link_config.dp_link_settings;</div><div class='add'>+	const struct dc *dc = pipe_ctx-&gt;stream-&gt;link-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	// Not necessary for MST configurations</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	pix_clk_mhz = timing-&gt;pix_clk_100hz / 10000;</div><div class='add'>+</div><div class='add'>+	// If this is true, can't block due to dynamic ODM</div><div class='add'>+	if (pix_clk_mhz &gt; dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].dispclk_mhz)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	switch (link_settings-&gt;link_rate) {</div><div class='add'>+	case LINK_RATE_LOW:</div><div class='add'>+		symclk_mhz = 162;</div><div class='add'>+		break;</div><div class='add'>+	case LINK_RATE_HIGH:</div><div class='add'>+		symclk_mhz = 270;</div><div class='add'>+		break;</div><div class='add'>+	case LINK_RATE_HIGH2:</div><div class='add'>+		symclk_mhz = 540;</div><div class='add'>+		break;</div><div class='add'>+	case LINK_RATE_HIGH3:</div><div class='add'>+		symclk_mhz = 810;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		// We shouldn't be tunneling any other rates, something is wrong</div><div class='add'>+		ASSERT(0);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	avg_pix_per_tu_x1000 = (1000 * pix_clk_mhz * tu_size_bytes)</div><div class='add'>+		/ (symclk_mhz * link_settings-&gt;lane_count);</div><div class='add'>+</div><div class='add'>+	// Add small empirically-decided margin to account for potential jitter</div><div class='add'>+	return (avg_pix_per_tu_x1000 &lt; 2020);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (!is_h_timing_divisible_by_2(pipe_ctx-&gt;stream))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (should_avoid_empty_tu(pipe_ctx))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp; !dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx) &amp;&amp;</div><div class='add'>+		dc-&gt;debug.enable_dp_dig_pixel_rate_div_policy)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Set powerup to true for every pipe to match pre-OS configuration.</div><div class='add'>+ */</div><div class='add'>+static void dcn35_calc_blocks_to_ungate_for_hw_release(struct dc *dc, struct pg_block_update *update_state)</div><div class='add'>+{</div><div class='add'>+	int i = 0, j = 0;</div><div class='add'>+</div><div class='add'>+	memset(update_state, 0, sizeof(struct pg_block_update));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		for (j = 0; j &lt; PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++)</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[j][i] = true;</div><div class='add'>+</div><div class='add'>+	update_state-&gt;pg_res_update[PG_HPO] = true;</div><div class='add'>+	update_state-&gt;pg_res_update[PG_DWB] = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The purpose is to power up all gatings to restore optimization to pre-OS env.</div><div class='add'>+ * Re-use hwss func and existing PG&amp;RCG flags to decide powerup sequence.</div><div class='add'>+ */</div><div class='add'>+void dcn35_hardware_release(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct pg_block_update pg_update_state;</div><div class='add'>+</div><div class='add'>+	dcn35_calc_blocks_to_ungate_for_hw_release(dc, &amp;pg_update_state);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwss.root_clock_control)</div><div class='add'>+		dc-&gt;hwss.root_clock_control(dc, &amp;pg_update_state, true);</div><div class='add'>+	/*power up required HW block*/</div><div class='add'>+	if (dc-&gt;hwss.hw_block_power_up)</div><div class='add'>+		dc-&gt;hwss.hw_block_power_up(dc, &amp;pg_update_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	if (!dc_dmub_srv_is_cursor_offload_enabled(dc))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Insert a blank update to modify the write index and set pipe_mask to 0.</div><div class='add'>+	 *</div><div class='add'>+	 * While the DMU is interlocked with driver full pipe programming via</div><div class='add'>+	 * the DMU HW lock, if the cursor update begins to execute after a full</div><div class='add'>+	 * pipe programming occurs there are two possible issues:</div><div class='add'>+	 *</div><div class='add'>+	 * 1. Outdated cursor information is programmed, replacing the current update</div><div class='add'>+	 * 2. The cursor update in firmware holds the cursor lock, preventing</div><div class='add'>+	 *    the current update from being latched atomically in the same frame</div><div class='add'>+	 *    as the rest of the update.</div><div class='add'>+	 *</div><div class='add'>+	 * This blank update, treated as a no-op, will allow the firmware to skip</div><div class='add'>+	 * the programming.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwss.begin_cursor_offload_update)</div><div class='add'>+		dc-&gt;hwss.begin_cursor_offload_update(dc, pipe);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwss.commit_cursor_offload_update)</div><div class='add'>+		dc-&gt;hwss.commit_cursor_offload_update(dc, pipe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	volatile struct dmub_cursor_offload_v1 *cs = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;cursor_offload_v1;</div><div class='add'>+	const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);</div><div class='add'>+	uint32_t stream_idx, write_idx, payload_idx;</div><div class='add'>+</div><div class='add'>+	if (!top_pipe)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	stream_idx = top_pipe-&gt;pipe_idx;</div><div class='add'>+	write_idx = cs-&gt;offload_streams[stream_idx].write_idx + 1; /*  new payload (+1) */</div><div class='add'>+	payload_idx = write_idx % ARRAY_SIZE(cs-&gt;offload_streams[stream_idx].payloads);</div><div class='add'>+</div><div class='add'>+	cs-&gt;offload_streams[stream_idx].payloads[payload_idx].write_idx_start = write_idx;</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;plane_res.hubp)</div><div class='add'>+		pipe-&gt;plane_res.hubp-&gt;cursor_offload = true;</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;plane_res.dpp)</div><div class='add'>+		pipe-&gt;plane_res.dpp-&gt;cursor_offload = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	volatile struct dmub_cursor_offload_v1 *cs = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;cursor_offload_v1;</div><div class='add'>+	volatile struct dmub_shared_state_cursor_offload_stream_v1 *shared_stream;</div><div class='add'>+	const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);</div><div class='add'>+	uint32_t stream_idx, write_idx, payload_idx;</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;plane_res.hubp)</div><div class='add'>+		pipe-&gt;plane_res.hubp-&gt;cursor_offload = false;</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;plane_res.dpp)</div><div class='add'>+		pipe-&gt;plane_res.dpp-&gt;cursor_offload = false;</div><div class='add'>+</div><div class='add'>+	if (!top_pipe)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	stream_idx = top_pipe-&gt;pipe_idx;</div><div class='add'>+	write_idx = cs-&gt;offload_streams[stream_idx].write_idx + 1; /*  new payload (+1) */</div><div class='add'>+	payload_idx = write_idx % ARRAY_SIZE(cs-&gt;offload_streams[stream_idx].payloads);</div><div class='add'>+</div><div class='add'>+	shared_stream = &amp;dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1]</div><div class='add'>+				 .data.cursor_offload_v1.offload_streams[stream_idx];</div><div class='add'>+</div><div class='add'>+	shared_stream-&gt;last_write_idx = write_idx;</div><div class='add'>+</div><div class='add'>+	cs-&gt;offload_streams[stream_idx].write_idx = write_idx;</div><div class='add'>+	cs-&gt;offload_streams[stream_idx].payloads[payload_idx].write_idx_finish = write_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	volatile struct dmub_cursor_offload_v1 *cs = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;cursor_offload_v1;</div><div class='add'>+	const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);</div><div class='add'>+	const struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+	const struct dpp *dpp = pipe-&gt;plane_res.dpp;</div><div class='add'>+	volatile struct dmub_cursor_offload_pipe_data_dcn30_v1 *p;</div><div class='add'>+	uint32_t stream_idx, write_idx, payload_idx;</div><div class='add'>+</div><div class='add'>+	if (!top_pipe || !hubp || !dpp)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	stream_idx = top_pipe-&gt;pipe_idx;</div><div class='add'>+	write_idx = cs-&gt;offload_streams[stream_idx].write_idx + 1; /*  new payload (+1) */</div><div class='add'>+	payload_idx = write_idx % ARRAY_SIZE(cs-&gt;offload_streams[stream_idx].payloads);</div><div class='add'>+</div><div class='add'>+	p = &amp;cs-&gt;offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe-&gt;pipe_idx].dcn30;</div><div class='add'>+</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp-&gt;att.SURFACE_ADDR;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp-&gt;att.SURFACE_ADDR_HIGH;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp-&gt;att.size.bits.width;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp-&gt;att.size.bits.height;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp-&gt;pos.position.bits.x_pos;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp-&gt;pos.position.bits.y_pos;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp-&gt;pos.hot_spot.bits.x_hot;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp-&gt;pos.hot_spot.bits.y_hot;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp-&gt;pos.dst_offset.bits.dst_x_offset;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp-&gt;pos.cur_ctl.bits.cur_enable;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp-&gt;att.cur_ctl.bits.mode;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp-&gt;pos.cur_ctl.bits.cur_2x_magnify;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp-&gt;att.cur_ctl.bits.pitch;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp-&gt;att.cur_ctl.bits.line_per_chunk;</div><div class='add'>+</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp-&gt;att.cur0_ctl.bits.cur0_enable;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp-&gt;att.cur0_ctl.bits.mode;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp-&gt;att.cur0_ctl.bits.expansion_mode;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp-&gt;att.cur0_ctl.bits.cur0_rom_en;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 = 0x000000;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 = 0xFFFFFF;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS = dpp-&gt;att.fp_scale_bias.bits.fp_bias;</div><div class='add'>+	p-&gt;CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE = dpp-&gt;att.fp_scale_bias.bits.fp_scale;</div><div class='add'>+</div><div class='add'>+	p-&gt;HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp-&gt;att.settings.bits.dst_y_offset;</div><div class='add'>+	p-&gt;HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp-&gt;att.settings.bits.chunk_hdl_adjust;</div><div class='add'>+</div><div class='add'>+	cs-&gt;offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u &lt;&lt; pipe-&gt;pipe_idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,</div><div class='add'>+					    const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	dc_dmub_srv_control_cursor_offload(dc, context, stream, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	dc_dmub_srv_program_cursor_now(dc, pipe);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h<br/>index c354efa6c1b2..1ff41dba556c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h</a></div><div class='hunk'>@@ -37,6 +37,10 @@ void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool pow</div><div class='ctx'> </div><div class='ctx'> void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);</div><div class='ctx'> </div><div class='add'>+void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on);</div><div class='add'>+</div><div class='add'>+void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);</div><div class='add'>+</div><div class='ctx'> void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);</div><div class='ctx'> </div><div class='ctx'> void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);</div><div class='hunk'>@@ -84,13 +88,25 @@ void dcn35_dsc_pg_control(</div><div class='ctx'> 		unsigned int dsc_inst,</div><div class='ctx'> 		bool power_on);</div><div class='ctx'> </div><div class='del'>-void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);</div><div class='del'>-uint32_t dcn35_get_idle_state(const struct dc *dc);</div><div class='del'>-</div><div class='ctx'> void dcn35_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 		int num_pipes, struct dc_crtc_timing_adjust adjust);</div><div class='ctx'> </div><div class='ctx'> void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,</div><div class='ctx'> 		int num_pipes, const struct dc_static_screen_params *params);</div><div class='ctx'> </div><div class='add'>+void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,</div><div class='add'>+		int num_pipes, uint32_t v_total_min, uint32_t v_total_max);</div><div class='add'>+</div><div class='add'>+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void dcn35_hardware_release(struct dc *dc);</div><div class='add'>+</div><div class='add'>+void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,</div><div class='add'>+					    const struct dc_stream_state *stream);</div><div class='add'>+void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCN35_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c<br/>index a93073055e7b..5a66c9db2670 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #include "dcn30/dcn30_hwseq.h"</div><div class='ctx'> #include "dcn301/dcn301_hwseq.h"</div><div class='ctx'> #include "dcn31/dcn31_hwseq.h"</div><div class='add'>+#include "dcn314/dcn314_hwseq.h"</div><div class='ctx'> #include "dcn32/dcn32_hwseq.h"</div><div class='ctx'> #include "dcn35/dcn35_hwseq.h"</div><div class='ctx'> </div><div class='hunk'>@@ -43,6 +44,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -84,6 +86,12 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.set_cursor_position = dcn10_set_cursor_position,</div><div class='ctx'> 	.set_cursor_attribute = dcn10_set_cursor_attribute,</div><div class='ctx'> 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,</div><div class='add'>+	.abort_cursor_offload_update = dcn35_abort_cursor_offload_update,</div><div class='add'>+	.begin_cursor_offload_update = dcn35_begin_cursor_offload_update,</div><div class='add'>+	.commit_cursor_offload_update = dcn35_commit_cursor_offload_update,</div><div class='add'>+	.update_cursor_offload_pipe = dcn35_update_cursor_offload_pipe,</div><div class='add'>+	.notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update,</div><div class='add'>+	.program_cursor_offload_now = dcn35_program_cursor_offload_now,</div><div class='ctx'> 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,</div><div class='ctx'> 	.set_clock = dcn10_set_clock,</div><div class='ctx'> 	.get_clock = dcn10_get_clock,</div><div class='hunk'>@@ -91,7 +99,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -100,8 +107,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,</div><div class='ctx'> 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='del'>-	.power_down = dce110_power_down,</div><div class='del'>-	.set_backlight_level = dcn21_set_backlight_level,</div><div class='add'>+	.set_backlight_level = dcn31_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='ctx'> 	.set_pipe = dcn21_set_pipe,</div><div class='ctx'> 	.enable_lvds_link_output = dce110_enable_lvds_link_output,</div><div class='hunk'>@@ -115,19 +121,23 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='ctx'> 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='ctx'> 	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,</div><div class='del'>-	.update_dsc_pg = dcn32_update_dsc_pg,</div><div class='ctx'> 	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,</div><div class='ctx'> 	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,</div><div class='ctx'> 	.hw_block_power_up = dcn35_hw_block_power_up,</div><div class='ctx'> 	.hw_block_power_down = dcn35_hw_block_power_down,</div><div class='ctx'> 	.root_clock_control = dcn35_root_clock_control,</div><div class='del'>-	.set_idle_state = dcn35_set_idle_state,</div><div class='del'>-	.get_idle_state = dcn35_get_idle_state</div><div class='add'>+	.set_long_vtotal = dcn35_set_long_vblank,</div><div class='add'>+	.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,</div><div class='add'>+	.hardware_release = dcn35_hardware_release,</div><div class='add'>+	.detect_pipe_changes = dcn20_detect_pipe_changes,</div><div class='add'>+	.enable_plane = dcn20_enable_plane,</div><div class='add'>+	.update_dchubp_dpp = dcn20_update_dchubp_dpp,</div><div class='add'>+	.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn35_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn35_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn32_set_input_transfer_func,</div><div class='hunk'>@@ -146,8 +156,9 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {</div><div class='ctx'> 	.plane_atomic_disable = dcn35_plane_atomic_disable,</div><div class='ctx'> 	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/</div><div class='ctx'> 	//.hubp_pg_control = dcn35_hubp_pg_control,</div><div class='del'>-	.enable_power_gating_plane = dcn35_enable_power_gating_plane,</div><div class='ctx'> 	.dpp_root_clock_control = dcn35_dpp_root_clock_control,</div><div class='add'>+	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,</div><div class='add'>+	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,</div><div class='ctx'> 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,</div><div class='ctx'> 	.update_odm = dcn35_update_odm,</div><div class='ctx'> 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,</div><div class='hunk'>@@ -157,11 +168,12 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {</div><div class='ctx'> 	.set_mcm_luts = dcn32_set_mcm_luts,</div><div class='ctx'> 	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,</div><div class='ctx'> 	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,</div><div class='del'>-	.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,</div><div class='del'>-	.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,</div><div class='del'>-	.dsc_pg_control = dcn35_dsc_pg_control,</div><div class='add'>+	.resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,</div><div class='add'>+	.is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,</div><div class='ctx'> 	.dsc_pg_status = dcn32_dsc_pg_status,</div><div class='ctx'> 	.enable_plane = dcn35_enable_plane,</div><div class='add'>+	.wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,</div><div class='add'>+	.set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn35_hw_sequencer_construct(struct dc *dc)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile<br/>index b24ad27fe6ef..a4b3c1e99ec6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile</a></div><div class='hunk'>@@ -1,16 +1,27 @@</div><div class='ctx'> #</div><div class='del'>-# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved</div><div class='add'>+# Copyright (c) 2022-2024 Advanced Micro Devices, Inc.</div><div class='ctx'> #</div><div class='del'>-#  All rights reserved.  This notice is intended as a precaution against</div><div class='del'>-#  inadvertent publication and does not imply publication or any waiver</div><div class='del'>-#  of confidentiality.  The year included in the foregoing notice is the</div><div class='del'>-#  year of creation of the work.</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='ctx'> #</div><div class='del'>-#  Authors: AMD</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'> #</div><div class='ctx'> # Makefile for DCN351.</div><div class='ctx'> </div><div class='del'>-DCN351 = dcn351_init.o</div><div class='add'>+DCN351 = dcn351_hwseq.o dcn351_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN351 = $(addprefix $(AMDDALPATH)/dc/dcn351/,$(DCN351))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c<br/>new file mode 100644<br/>index 000000000000..93fe5b262a3d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c</a></div><div class='hunk'>@@ -0,0 +1,182 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "dcn351_hwseq.h"</div><div class='add'>+#include "dcn35/dcn35_hwseq.h"</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER_INIT(logger) \</div><div class='add'>+	struct dal_logger *dc_logger = logger</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dc_logger</div><div class='add'>+</div><div class='add'>+void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='add'>+	struct pg_block_update *update_state)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	dcn35_calc_blocks_to_gate(dc, context, update_state);</div><div class='add'>+</div><div class='add'>+	for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='add'>+		if (!update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			!update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+			for (j = i - 1; j &gt;= 0; j--) {</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_HUBP][j] = false;</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_DPP][j] = false;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='add'>+	struct pg_block_update *update_state)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	dcn35_calc_blocks_to_ungate(dc, context, update_state);</div><div class='add'>+</div><div class='add'>+	for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='add'>+		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+			for (j = i - 1; j &gt;= 0; j--) {</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_HUBP][j] = true;</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_DPP][j] = true;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcn351_hw_block_power_down() - power down sequence</div><div class='add'>+ *</div><div class='add'>+ * The following sequence describes the ON-OFF (ONO) for power down:</div><div class='add'>+ *</div><div class='add'>+ *	ONO Region 11, DCPG 19: dsc3</div><div class='add'>+ *	ONO Region 10, DCPG 3: dchubp3, dpp3</div><div class='add'>+ *	ONO Region 9, DCPG 18: dsc2</div><div class='add'>+ *	ONO Region 8, DCPG 2: dchubp2, dpp2</div><div class='add'>+ *	ONO Region 7, DCPG 17: dsc1</div><div class='add'>+ *	ONO Region 6, DCPG 1: dchubp1, dpp1</div><div class='add'>+ *	ONO Region 5, DCPG 16: dsc0</div><div class='add'>+ *	ONO Region 4, DCPG 0: dchubp0, dpp0</div><div class='add'>+ *	ONO Region 3, DCPG 25: hpo - SKIPPED. Should be kept on</div><div class='add'>+ *	ONO Region 2, DCPG 24: mpc opp optc dwb</div><div class='add'>+ *	ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will pwr dwn at IPS2 entry</div><div class='add'>+ *	ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED. will be pwr dwn after lono timer is armed</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current DC state</div><div class='add'>+ * @update_state: update PG sequence states for HW block</div><div class='add'>+ */</div><div class='add'>+void dcn351_hw_block_power_down(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='add'>+</div><div class='add'>+	if (!pg_cntl || dc-&gt;debug.ignore_pg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0; i--) {</div><div class='add'>+		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+			if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, false);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+			if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// domain25 currently always on.</div><div class='add'>+</div><div class='add'>+	/* this will need all the clients to unregister optc interrupts, let dmubfw handle this */</div><div class='add'>+	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='add'>+		pg_cntl-&gt;funcs-&gt;plane_otg_pg_control(pg_cntl, false);</div><div class='add'>+</div><div class='add'>+	// domain23 currently always on.</div><div class='add'>+	// domain22 currently always on.</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcn351_hw_block_power_up() - power up sequence</div><div class='add'>+ *</div><div class='add'>+ * The following sequence describes the ON-OFF (ONO) for power up:</div><div class='add'>+ *</div><div class='add'>+ *	ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED</div><div class='add'>+ *	ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will power up at IPS2 exit</div><div class='add'>+ *	ONO Region 2, DCPG 24: mpc opp optc dwb</div><div class='add'>+ *	ONO Region 3, DCPG 25: hpo - SKIPPED</div><div class='add'>+ *	ONO Region 4, DCPG 0: dchubp0, dpp0</div><div class='add'>+ *	ONO Region 5, DCPG 16: dsc0</div><div class='add'>+ *	ONO Region 6, DCPG 1: dchubp1, dpp1</div><div class='add'>+ *	ONO Region 7, DCPG 17: dsc1</div><div class='add'>+ *	ONO Region 8, DCPG 2: dchubp2, dpp2</div><div class='add'>+ *	ONO Region 9, DCPG 18: dsc2</div><div class='add'>+ *	ONO Region 10, DCPG 3: dchubp3, dpp3</div><div class='add'>+ *	ONO Region 11, DCPG 19: dsc3</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current DC state</div><div class='add'>+ * @update_state: update PG sequence states for HW block</div><div class='add'>+ */</div><div class='add'>+void dcn351_hw_block_power_up(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='add'>+</div><div class='add'>+	if (!pg_cntl || dc-&gt;debug.ignore_pg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	// domain22 currently always on.</div><div class='add'>+	// domain23 currently always on.</div><div class='add'>+</div><div class='add'>+	/* this will need all the clients to unregister optc interrupts, let dmubfw handle this */</div><div class='add'>+	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='add'>+		pg_cntl-&gt;funcs-&gt;plane_otg_pg_control(pg_cntl, true);</div><div class='add'>+</div><div class='add'>+	// domain25 currently always on.</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+			if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, true);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+			if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, true);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h<br/>new file mode 100644<br/>index 000000000000..6d8f3bfb668e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.h</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_HWSS_DCN351_H__</div><div class='add'>+#define __DC_HWSS_DCN351_H__</div><div class='add'>+</div><div class='add'>+#include "hw_sequencer_private.h"</div><div class='add'>+</div><div class='add'>+void dcn351_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='add'>+	struct pg_block_update *update_state);</div><div class='add'>+void dcn351_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='add'>+	struct pg_block_update *update_state);</div><div class='add'>+void dcn351_hw_block_power_up(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state);</div><div class='add'>+void dcn351_hw_block_power_down(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_HWSS_DCN351_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c<br/>index ab17fa1c64e8..09e60158f0b5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include "dcn31/dcn31_hwseq.h"</div><div class='ctx'> #include "dcn32/dcn32_hwseq.h"</div><div class='ctx'> #include "dcn35/dcn35_hwseq.h"</div><div class='add'>+#include "dcn351/dcn351_hwseq.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn351_init.h"</div><div class='ctx'> </div><div class='hunk'>@@ -42,6 +43,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {</div><div class='ctx'> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='ctx'> 	.apply_ctx_for_surface = NULL,</div><div class='ctx'> 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='ctx'> 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='ctx'> 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='ctx'> 	.update_plane_addr = dcn20_update_plane_addr,</div><div class='hunk'>@@ -67,7 +69,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {</div><div class='ctx'> 	.prepare_bandwidth = dcn35_prepare_bandwidth,</div><div class='ctx'> 	.optimize_bandwidth = dcn35_optimize_bandwidth,</div><div class='ctx'> 	.update_bandwidth = dcn20_update_bandwidth,</div><div class='del'>-	.set_drr = dcn10_set_drr,</div><div class='add'>+	.set_drr = dcn35_set_drr,</div><div class='ctx'> 	.get_position = dcn10_get_position,</div><div class='ctx'> 	.set_static_screen_control = dcn35_set_static_screen_control,</div><div class='ctx'> 	.setup_stereo = dcn10_setup_stereo,</div><div class='hunk'>@@ -90,7 +92,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = {</div><div class='ctx'> 	.enable_writeback = dcn30_enable_writeback,</div><div class='ctx'> 	.disable_writeback = dcn30_disable_writeback,</div><div class='ctx'> 	.update_writeback = dcn30_update_writeback,</div><div class='del'>-	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='ctx'> 	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='ctx'> 	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='ctx'> 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='hunk'>@@ -99,8 +100,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {</div><div class='ctx'> 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,</div><div class='ctx'> 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='ctx'> 	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='del'>-	.power_down = dce110_power_down,</div><div class='del'>-	.set_backlight_level = dcn21_set_backlight_level,</div><div class='add'>+	.set_backlight_level = dcn31_set_backlight_level,</div><div class='ctx'> 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='ctx'> 	.set_pipe = dcn21_set_pipe,</div><div class='ctx'> 	.enable_lvds_link_output = dce110_enable_lvds_link_output,</div><div class='hunk'>@@ -114,19 +114,19 @@ static const struct hw_sequencer_funcs dcn351_funcs = {</div><div class='ctx'> 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='ctx'> 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='ctx'> 	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,</div><div class='del'>-	.update_dsc_pg = dcn32_update_dsc_pg,</div><div class='del'>-	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,</div><div class='del'>-	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,</div><div class='del'>-	.hw_block_power_up = dcn35_hw_block_power_up,</div><div class='del'>-	.hw_block_power_down = dcn35_hw_block_power_down,</div><div class='add'>+	.calc_blocks_to_gate = dcn351_calc_blocks_to_gate,</div><div class='add'>+	.calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,</div><div class='add'>+	.hw_block_power_up = dcn351_hw_block_power_up,</div><div class='add'>+	.hw_block_power_down = dcn351_hw_block_power_down,</div><div class='ctx'> 	.root_clock_control = dcn35_root_clock_control,</div><div class='del'>-	.set_idle_state = dcn35_set_idle_state,</div><div class='del'>-	.get_idle_state = dcn35_get_idle_state</div><div class='add'>+	.set_long_vtotal = dcn35_set_long_vblank,</div><div class='add'>+	.calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider,</div><div class='add'>+	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct hwseq_private_funcs dcn351_private_funcs = {</div><div class='ctx'> 	.init_pipes = dcn35_init_pipes,</div><div class='del'>-	.update_plane_addr = dcn20_update_plane_addr,</div><div class='ctx'> 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='ctx'> 	.update_mpcc = dcn20_update_mpcc,</div><div class='ctx'> 	.set_input_transfer_func = dcn32_set_input_transfer_func,</div><div class='hunk'>@@ -145,8 +145,9 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {</div><div class='ctx'> 	.plane_atomic_disable = dcn35_plane_atomic_disable,</div><div class='ctx'> 	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/</div><div class='ctx'> 	//.hubp_pg_control = dcn35_hubp_pg_control,</div><div class='del'>-	.enable_power_gating_plane = dcn35_enable_power_gating_plane,</div><div class='ctx'> 	.dpp_root_clock_control = dcn35_dpp_root_clock_control,</div><div class='add'>+	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,</div><div class='add'>+	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,</div><div class='ctx'> 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,</div><div class='ctx'> 	.update_odm = dcn35_update_odm,</div><div class='ctx'> 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,</div><div class='hunk'>@@ -156,11 +157,11 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {</div><div class='ctx'> 	.set_mcm_luts = dcn32_set_mcm_luts,</div><div class='ctx'> 	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,</div><div class='ctx'> 	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,</div><div class='del'>-	.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,</div><div class='del'>-	.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,</div><div class='del'>-	.dsc_pg_control = dcn35_dsc_pg_control,</div><div class='add'>+	.is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,</div><div class='ctx'> 	.dsc_pg_status = dcn32_dsc_pg_status,</div><div class='ctx'> 	.enable_plane = dcn35_enable_plane,</div><div class='add'>+	.wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,</div><div class='add'>+	.set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn351_hw_sequencer_construct(struct dc *dc)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c<br/>new file mode 100644<br/>index 000000000000..2fbc22afb89c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c</a></div><div class='hunk'>@@ -0,0 +1,4045 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#include "os_types.h"</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "basics/dc_common.h"</div><div class='add'>+#include "dm_helpers.h"</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "dccg.h"</div><div class='add'>+#include "dce/dce_hwseq.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "abm.h"</div><div class='add'>+#include "hubp.h"</div><div class='add'>+#include "dchubbub.h"</div><div class='add'>+#include "timing_generator.h"</div><div class='add'>+#include "opp.h"</div><div class='add'>+#include "ipp.h"</div><div class='add'>+#include "mpc.h"</div><div class='add'>+#include "mcif_wb.h"</div><div class='add'>+#include "dc_dmub_srv.h"</div><div class='add'>+#include "link_hwss.h"</div><div class='add'>+#include "dpcd_defs.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='add'>+#include "dsc.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+#include "custom_float.h"</div><div class='add'>+</div><div class='add'>+#include "dce/dmub_hw_lock_mgr.h"</div><div class='add'>+#include "dcn10/dcn10_cm_common.h"</div><div class='add'>+#include "dcn10/dcn10_hubbub.h"</div><div class='add'>+#include "dcn20/dcn20_optc.h"</div><div class='add'>+#include "dcn30/dcn30_cm_common.h"</div><div class='add'>+#include "dcn32/dcn32_hwseq.h"</div><div class='add'>+#include "dcn401_hwseq.h"</div><div class='add'>+#include "dcn401/dcn401_resource.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+#include "link_enc_cfg.h"</div><div class='add'>+#include "../hw_sequencer.h"</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER_INIT(logger)</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	hws-&gt;ctx</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	hws-&gt;regs-&gt;reg</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dc-&gt;ctx-&gt;logger</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	hws-&gt;shifts-&gt;field_name, hws-&gt;masks-&gt;field_name</div><div class='add'>+</div><div class='add'>+void dcn401_initialize_min_clocks(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dc_clocks *clocks = &amp;dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk;</div><div class='add'>+</div><div class='add'>+	clocks-&gt;dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;</div><div class='add'>+	clocks-&gt;dcfclk_khz = dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].dcfclk_mhz * 1000;</div><div class='add'>+	clocks-&gt;socclk_khz = dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].socclk_mhz * 1000;</div><div class='add'>+	clocks-&gt;dramclk_khz = dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].memclk_mhz * 1000;</div><div class='add'>+	clocks-&gt;dppclk_khz = dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].dppclk_mhz * 1000;</div><div class='add'>+	if (dc-&gt;debug.disable_boot_optimizations) {</div><div class='add'>+		clocks-&gt;dispclk_khz = dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].dispclk_mhz * 1000;</div><div class='add'>+	} else {</div><div class='add'>+		/* Even though DPG_EN = 1 for the connected display, it still requires the</div><div class='add'>+		 * correct timing so we cannot set DISPCLK to min freq or it could cause</div><div class='add'>+		 * audio corruption. Read current DISPCLK from DENTIST and request the same</div><div class='add'>+		 * freq to ensure that the timing is valid and unchanged.</div><div class='add'>+		 */</div><div class='add'>+		clocks-&gt;dispclk_khz = dc-&gt;clk_mgr-&gt;funcs-&gt;get_dispclk_from_dentist(dc-&gt;clk_mgr);</div><div class='add'>+	}</div><div class='add'>+	clocks-&gt;ref_dtbclk_khz = dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[0].dtbclk_mhz * 1000;</div><div class='add'>+	clocks-&gt;fclk_p_state_change_support = true;</div><div class='add'>+	clocks-&gt;p_state_change_support = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;clk_mgr-&gt;funcs-&gt;update_clocks(</div><div class='add'>+			dc-&gt;clk_mgr,</div><div class='add'>+			dc-&gt;current_state,</div><div class='add'>+			true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+	struct mpc_grph_gamut_adjustment mpc_adjust;</div><div class='add'>+	unsigned int mpcc_id = pipe_ctx-&gt;plane_res.mpcc_inst;</div><div class='add'>+	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+</div><div class='add'>+	//For now assert if location is not pre-blend</div><div class='add'>+	if (pipe_ctx-&gt;plane_state)</div><div class='add'>+		ASSERT(pipe_ctx-&gt;plane_state-&gt;mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE);</div><div class='add'>+</div><div class='add'>+	// program MPCC_MCM_FIRST_GAMUT_REMAP</div><div class='add'>+	memset(&amp;mpc_adjust, 0, sizeof(mpc_adjust));</div><div class='add'>+	mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;</div><div class='add'>+	mpc_adjust.mpcc_gamut_remap_block_id = MPCC_MCM_FIRST_GAMUT_REMAP;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp;</div><div class='add'>+		pipe_ctx-&gt;plane_state-&gt;gamut_remap_matrix.enable_remap == true) {</div><div class='add'>+		mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;</div><div class='add'>+		for (i = 0; i &lt; CSC_TEMPERATURE_MATRIX_SIZE; i++)</div><div class='add'>+			mpc_adjust.temperature_matrix[i] =</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;gamut_remap_matrix.matrix[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mpc-&gt;funcs-&gt;set_gamut_remap(mpc, mpcc_id, &amp;mpc_adjust);</div><div class='add'>+</div><div class='add'>+	// program MPCC_MCM_SECOND_GAMUT_REMAP for Bypass / Disable for now</div><div class='add'>+	mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;</div><div class='add'>+	mpc_adjust.mpcc_gamut_remap_block_id = MPCC_MCM_SECOND_GAMUT_REMAP;</div><div class='add'>+</div><div class='add'>+	mpc-&gt;funcs-&gt;set_gamut_remap(mpc, mpcc_id, &amp;mpc_adjust);</div><div class='add'>+</div><div class='add'>+	// program MPCC_OGAM_GAMUT_REMAP same as is currently used on DCN3x</div><div class='add'>+	memset(&amp;mpc_adjust, 0, sizeof(mpc_adjust));</div><div class='add'>+	mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;</div><div class='add'>+	mpc_adjust.mpcc_gamut_remap_block_id = MPCC_OGAM_GAMUT_REMAP;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;top_pipe == NULL) {</div><div class='add'>+		if (pipe_ctx-&gt;stream-&gt;gamut_remap_matrix.enable_remap == true) {</div><div class='add'>+			mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;</div><div class='add'>+			for (i = 0; i &lt; CSC_TEMPERATURE_MATRIX_SIZE; i++)</div><div class='add'>+				mpc_adjust.temperature_matrix[i] =</div><div class='add'>+				pipe_ctx-&gt;stream-&gt;gamut_remap_matrix.matrix[i];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mpc-&gt;funcs-&gt;set_gamut_remap(mpc, mpcc_id, &amp;mpc_adjust);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_init_hw(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct abm **abms = dc-&gt;res_pool-&gt;multiple_abms;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='add'>+	struct resource_pool *res_pool = dc-&gt;res_pool;</div><div class='add'>+	int i;</div><div class='add'>+	int edp_num;</div><div class='add'>+	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	int current_dchub_ref_freq = 0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks) {</div><div class='add'>+		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='add'>+</div><div class='add'>+		// mark dcmode limits present if any clock has distinct AC and DC values from SMU</div><div class='add'>+		dc-&gt;caps.dcmode_power_limits_present = dc-&gt;clk_mgr-&gt;funcs-&gt;is_dc_mode_present &amp;&amp;</div><div class='add'>+				dc-&gt;clk_mgr-&gt;funcs-&gt;is_dc_mode_present(dc-&gt;clk_mgr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Initialize the dccg</div><div class='add'>+	if (res_pool-&gt;dccg-&gt;funcs-&gt;dccg_init)</div><div class='add'>+		res_pool-&gt;dccg-&gt;funcs-&gt;dccg_init(res_pool-&gt;dccg);</div><div class='add'>+</div><div class='add'>+	// Disable DMUB Initialization until IPS state programming is finalized</div><div class='add'>+	//if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb)) {</div><div class='add'>+	//	hws-&gt;funcs.bios_golden_init(dc);</div><div class='add'>+	//}</div><div class='add'>+</div><div class='add'>+	// Set default OPTC memory power states</div><div class='add'>+	if (dc-&gt;debug.enable_mem_low_power.bits.optc) {</div><div class='add'>+		// Shutdown when unassigned and light sleep in VBLANK</div><div class='add'>+		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.enable_mem_low_power.bits.vga) {</div><div class='add'>+		// Power down VGA memory</div><div class='add'>+		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info_valid) {</div><div class='add'>+		res_pool-&gt;ref_clocks.xtalin_clock_inKhz =</div><div class='add'>+				dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency;</div><div class='add'>+</div><div class='add'>+		if (res_pool-&gt;hubbub) {</div><div class='add'>+			(res_pool-&gt;dccg-&gt;funcs-&gt;get_dccg_ref_freq)(res_pool-&gt;dccg,</div><div class='add'>+					dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency,</div><div class='add'>+					&amp;res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz);</div><div class='add'>+</div><div class='add'>+			current_dchub_ref_freq = res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000;</div><div class='add'>+</div><div class='add'>+			(res_pool-&gt;hubbub-&gt;funcs-&gt;get_dchub_ref_freq)(res_pool-&gt;hubbub,</div><div class='add'>+					res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz,</div><div class='add'>+					&amp;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz);</div><div class='add'>+		} else {</div><div class='add'>+			// Not all ASICs have DCCG sw component</div><div class='add'>+			res_pool-&gt;ref_clocks.dccg_ref_clock_inKhz =</div><div class='add'>+					res_pool-&gt;ref_clocks.xtalin_clock_inKhz;</div><div class='add'>+			res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz =</div><div class='add'>+					res_pool-&gt;ref_clocks.xtalin_clock_inKhz;</div><div class='add'>+		}</div><div class='add'>+	} else</div><div class='add'>+		ASSERT_CRITICAL(false);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='add'>+		/* Power up AND update implementation according to the</div><div class='add'>+		 * required signal (which may be different from the</div><div class='add'>+		 * default signal on connector).</div><div class='add'>+		 */</div><div class='add'>+		struct dc_link *link = dc-&gt;links[i];</div><div class='add'>+</div><div class='add'>+		if (link-&gt;ep_type != DISPLAY_ENDPOINT_PHY)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		link-&gt;link_enc-&gt;funcs-&gt;hw_init(link-&gt;link_enc);</div><div class='add'>+</div><div class='add'>+		/* Check for enabled DIG to identify enabled display */</div><div class='add'>+		if (link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='add'>+			link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc)) {</div><div class='add'>+			link-&gt;link_status.link_active = true;</div><div class='add'>+			link-&gt;phy_state.symclk_state = SYMCLK_ON_TX_ON;</div><div class='add'>+			if (link-&gt;link_enc-&gt;funcs-&gt;fec_is_active &amp;&amp;</div><div class='add'>+					link-&gt;link_enc-&gt;funcs-&gt;fec_is_active(link-&gt;link_enc))</div><div class='add'>+				link-&gt;fec_state = dc_link_fec_enabled;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* enable_power_gating_plane before dsc_pg_control because</div><div class='add'>+	 * FORCEON = 1 with hw default value on bootup, resume from s3</div><div class='add'>+	 */</div><div class='add'>+	if (hws-&gt;funcs.enable_power_gating_plane)</div><div class='add'>+		hws-&gt;funcs.enable_power_gating_plane(dc-&gt;hwseq, true);</div><div class='add'>+</div><div class='add'>+	/* we want to turn off all dp displays before doing detection */</div><div class='add'>+	dc-&gt;link_srv-&gt;blank_all_dp_displays(dc);</div><div class='add'>+</div><div class='add'>+	/* If taking control over from VBIOS, we may want to optimize our first</div><div class='add'>+	 * mode set, so we need to skip powering down pipes until we know which</div><div class='add'>+	 * pipes we want to use.</div><div class='add'>+	 * Otherwise, if taking control is not possible, we need to power</div><div class='add'>+	 * everything down.</div><div class='add'>+	 */</div><div class='add'>+	if (dcb-&gt;funcs-&gt;is_accelerated_mode(dcb) || !dc-&gt;config.seamless_boot_edp_requested) {</div><div class='add'>+		/* Disable boot optimizations means power down everything including PHY, DIG,</div><div class='add'>+		 * and OTG (i.e. the boot is not optimized because we do a full power down).</div><div class='add'>+		 */</div><div class='add'>+		if (dc-&gt;hwss.enable_accelerated_mode &amp;&amp; dc-&gt;debug.disable_boot_optimizations)</div><div class='add'>+			dc-&gt;hwss.enable_accelerated_mode(dc, dc-&gt;current_state);</div><div class='add'>+		else</div><div class='add'>+			hws-&gt;funcs.init_pipes(dc, dc-&gt;current_state);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;allow_self_refresh_control)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;allow_self_refresh_control(dc-&gt;res_pool-&gt;hubbub,</div><div class='add'>+					!dc-&gt;res_pool-&gt;hubbub-&gt;ctx-&gt;dc-&gt;debug.disable_stutter);</div><div class='add'>+</div><div class='add'>+		dcn401_initialize_min_clocks(dc);</div><div class='add'>+</div><div class='add'>+		/* On HW init, allow idle optimizations after pipes have been turned off.</div><div class='add'>+		 *</div><div class='add'>+		 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state</div><div class='add'>+		 * is reset (i.e. not in idle at the time hw init is called), but software state</div><div class='add'>+		 * still has idle_optimizations = true, so we must disable idle optimizations first</div><div class='add'>+		 * (i.e. set false), then re-enable (set true).</div><div class='add'>+		 */</div><div class='add'>+		dc_allow_idle_optimizations(dc, false);</div><div class='add'>+		dc_allow_idle_optimizations(dc, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* In headless boot cases, DIG may be turned</div><div class='add'>+	 * on which causes HW/SW discrepancies.</div><div class='add'>+	 * To avoid this, power down hardware on boot</div><div class='add'>+	 * if DIG is turned on and seamless boot not enabled</div><div class='add'>+	 */</div><div class='add'>+	if (!dc-&gt;config.seamless_boot_edp_requested) {</div><div class='add'>+		struct dc_link *edp_links[MAX_NUM_EDP];</div><div class='add'>+		struct dc_link *edp_link;</div><div class='add'>+</div><div class='add'>+		dc_get_edp_links(dc, edp_links, &amp;edp_num);</div><div class='add'>+		if (edp_num) {</div><div class='add'>+			for (i = 0; i &lt; edp_num; i++) {</div><div class='add'>+				edp_link = edp_links[i];</div><div class='add'>+				if (edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='add'>+						edp_link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(edp_link-&gt;link_enc) &amp;&amp;</div><div class='add'>+						dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='add'>+						hws-&gt;funcs.power_down &amp;&amp;</div><div class='add'>+						dc-&gt;hwss.edp_power_control) {</div><div class='add'>+					dc-&gt;hwss.edp_backlight_control(edp_link, false);</div><div class='add'>+					hws-&gt;funcs.power_down(dc);</div><div class='add'>+					dc-&gt;hwss.edp_power_control(edp_link, false);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='add'>+				struct dc_link *link = dc-&gt;links[i];</div><div class='add'>+</div><div class='add'>+				if (link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled &amp;&amp;</div><div class='add'>+						link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc) &amp;&amp;</div><div class='add'>+						hws-&gt;funcs.power_down) {</div><div class='add'>+					hws-&gt;funcs.power_down(dc);</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; res_pool-&gt;audio_count; i++) {</div><div class='add'>+		struct audio *audio = res_pool-&gt;audios[i];</div><div class='add'>+</div><div class='add'>+		audio-&gt;funcs-&gt;hw_init(audio);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='add'>+		struct dc_link *link = dc-&gt;links[i];</div><div class='add'>+</div><div class='add'>+		if (link-&gt;panel_cntl) {</div><div class='add'>+			backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+			user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (abms[i] != NULL &amp;&amp; abms[i]-&gt;funcs != NULL)</div><div class='add'>+			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight, user_level);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/</div><div class='add'>+	REG_WRITE(DIO_MEM_PWR_CTRL, 0);</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;debug.disable_clock_gate) {</div><div class='add'>+		/* enable all DCN clock gating */</div><div class='add'>+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dcn401_setup_hpo_hw_control(hws, true);</div><div class='add'>+</div><div class='add'>+	if (!dcb-&gt;funcs-&gt;is_accelerated_mode(dcb) &amp;&amp; dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_watermarks(dc-&gt;res_pool-&gt;hubbub);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges)</div><div class='add'>+		dc-&gt;clk_mgr-&gt;funcs-&gt;notify_wm_ranges(dc-&gt;clk_mgr);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, false, false);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_crb)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;init_crb(dc-&gt;res_pool-&gt;hubbub);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;set_request_limit &amp;&amp; dc-&gt;config.sdpif_request_limit_words_per_umc &gt; 0)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;set_request_limit(dc-&gt;res_pool-&gt;hubbub, dc-&gt;ctx-&gt;dc_bios-&gt;vram_info.num_chans, dc-&gt;config.sdpif_request_limit_words_per_umc);</div><div class='add'>+</div><div class='add'>+	// Get DMCUB capabilities</div><div class='add'>+	if (dc-&gt;ctx-&gt;dmub_srv) {</div><div class='add'>+		dc_dmub_srv_query_caps_cmd(dc-&gt;ctx-&gt;dmub_srv);</div><div class='add'>+		dc-&gt;caps.dmub_caps.psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.psr;</div><div class='add'>+		dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver &gt; 0;</div><div class='add'>+		dc-&gt;caps.dmub_caps.fams_ver = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch_ver;</div><div class='add'>+		dc-&gt;debug.fams2_config.bits.enable &amp;=</div><div class='add'>+				dc-&gt;caps.dmub_caps.fams_ver == dc-&gt;debug.fams_version.ver; // sw &amp; fw fams versions must match for support</div><div class='add'>+		if ((!dc-&gt;debug.fams2_config.bits.enable &amp;&amp; dc-&gt;res_pool-&gt;funcs-&gt;update_bw_bounding_box)</div><div class='add'>+			|| res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq) {</div><div class='add'>+			/* update bounding box if FAMS2 disabled, or if dchub clk has changed */</div><div class='add'>+			if (dc-&gt;clk_mgr)</div><div class='add'>+				dc-&gt;res_pool-&gt;funcs-&gt;update_bw_bounding_box(dc,</div><div class='add'>+									    dc-&gt;clk_mgr-&gt;bw_params);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		enum MCM_LUT_XABLE *shaper_xable,</div><div class='add'>+		enum MCM_LUT_XABLE *lut3d_xable,</div><div class='add'>+		enum MCM_LUT_XABLE *lut1d_xable)</div><div class='add'>+{</div><div class='add'>+	enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL;</div><div class='add'>+	bool lut1d_enable = false;</div><div class='add'>+	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;plane_state)</div><div class='add'>+		return;</div><div class='add'>+	shaper_3dlut_setting = pipe_ctx-&gt;plane_state-&gt;mcm_shaper_3dlut_setting;</div><div class='add'>+	lut1d_enable = pipe_ctx-&gt;plane_state-&gt;mcm_lut1d_enable;</div><div class='add'>+	mpc-&gt;funcs-&gt;set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);</div><div class='add'>+	pipe_ctx-&gt;plane_state-&gt;mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;</div><div class='add'>+</div><div class='add'>+	*lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE;</div><div class='add'>+</div><div class='add'>+	switch (shaper_3dlut_setting) {</div><div class='add'>+	case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL:</div><div class='add'>+		*lut3d_xable = *shaper_xable = MCM_LUT_DISABLE;</div><div class='add'>+		break;</div><div class='add'>+	case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER:</div><div class='add'>+		*lut3d_xable = MCM_LUT_DISABLE;</div><div class='add'>+		*shaper_xable = MCM_LUT_ENABLE;</div><div class='add'>+		break;</div><div class='add'>+	case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT:</div><div class='add'>+		*lut3d_xable = *shaper_xable = MCM_LUT_ENABLE;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_populate_mcm_luts(struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_cm2_func_luts mcm_luts,</div><div class='add'>+		bool lut_bank_a)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+	int mpcc_id = hubp-&gt;inst;</div><div class='add'>+	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+	union mcm_lut_params m_lut_params;</div><div class='add'>+	enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src;</div><div class='add'>+	enum hubp_3dlut_fl_format format = 0;</div><div class='add'>+	enum hubp_3dlut_fl_mode mode;</div><div class='add'>+	enum hubp_3dlut_fl_width width = 0;</div><div class='add'>+	enum hubp_3dlut_fl_addressing_mode addr_mode;</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0;</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0;</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0;</div><div class='add'>+	enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE;</div><div class='add'>+	enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE;</div><div class='add'>+	enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE;</div><div class='add'>+	bool rval;</div><div class='add'>+</div><div class='add'>+	dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &amp;shaper_xable, &amp;lut3d_xable, &amp;lut1d_xable);</div><div class='add'>+</div><div class='add'>+	/* 1D LUT */</div><div class='add'>+	if (mcm_luts.lut1d_func) {</div><div class='add'>+		memset(&amp;m_lut_params, 0, sizeof(m_lut_params));</div><div class='add'>+		if (mcm_luts.lut1d_func-&gt;type == TF_TYPE_HWPWL)</div><div class='add'>+			m_lut_params.pwl = &amp;mcm_luts.lut1d_func-&gt;pwl;</div><div class='add'>+		else if (mcm_luts.lut1d_func-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+			rval = cm3_helper_translate_curve_to_hw_format(</div><div class='add'>+					mcm_luts.lut1d_func,</div><div class='add'>+					&amp;dpp_base-&gt;regamma_params, false);</div><div class='add'>+			m_lut_params.pwl = rval ? &amp;dpp_base-&gt;regamma_params : NULL;</div><div class='add'>+		}</div><div class='add'>+		if (m_lut_params.pwl) {</div><div class='add'>+			if (mpc-&gt;funcs-&gt;populate_lut)</div><div class='add'>+				mpc-&gt;funcs-&gt;populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id);</div><div class='add'>+		}</div><div class='add'>+		if (mpc-&gt;funcs-&gt;program_lut_mode)</div><div class='add'>+			mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable &amp;&amp; m_lut_params.pwl, lut_bank_a, mpcc_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Shaper */</div><div class='add'>+	if (mcm_luts.shaper &amp;&amp; mcm_luts.lut3d_data.mpc_3dlut_enable) {</div><div class='add'>+		memset(&amp;m_lut_params, 0, sizeof(m_lut_params));</div><div class='add'>+		if (mcm_luts.shaper-&gt;type == TF_TYPE_HWPWL)</div><div class='add'>+			m_lut_params.pwl = &amp;mcm_luts.shaper-&gt;pwl;</div><div class='add'>+		else if (mcm_luts.shaper-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			rval = cm3_helper_translate_curve_to_hw_format(</div><div class='add'>+					mcm_luts.shaper,</div><div class='add'>+					&amp;dpp_base-&gt;regamma_params, true);</div><div class='add'>+			m_lut_params.pwl = rval ? &amp;dpp_base-&gt;regamma_params : NULL;</div><div class='add'>+		}</div><div class='add'>+		if (m_lut_params.pwl) {</div><div class='add'>+			if (mpc-&gt;funcs-&gt;mcm.populate_lut)</div><div class='add'>+				mpc-&gt;funcs-&gt;mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id);</div><div class='add'>+			if (mpc-&gt;funcs-&gt;program_lut_mode)</div><div class='add'>+				mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* 3DLUT */</div><div class='add'>+	switch (lut3d_src) {</div><div class='add'>+	case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM:</div><div class='add'>+		memset(&amp;m_lut_params, 0, sizeof(m_lut_params));</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl(hubp, false);</div><div class='add'>+</div><div class='add'>+		if (mcm_luts.lut3d_data.lut3d_func &amp;&amp; mcm_luts.lut3d_data.lut3d_func-&gt;state.bits.initialized) {</div><div class='add'>+			m_lut_params.lut3d = &amp;mcm_luts.lut3d_data.lut3d_func-&gt;lut_3d;</div><div class='add'>+			if (mpc-&gt;funcs-&gt;populate_lut)</div><div class='add'>+				mpc-&gt;funcs-&gt;populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id);</div><div class='add'>+			if (mpc-&gt;funcs-&gt;program_lut_mode)</div><div class='add'>+				mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a,</div><div class='add'>+						mpcc_id);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+		case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM:</div><div class='add'>+		switch (mcm_luts.lut3d_data.gpu_mem_params.size) {</div><div class='add'>+		case DC_CM2_GPU_MEM_SIZE_171717:</div><div class='add'>+			width = hubp_3dlut_fl_width_17;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_SIZE_TRANSFORMED:</div><div class='add'>+			width = hubp_3dlut_fl_width_transformed;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			//TODO: handle default case</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		//check for support</div><div class='add'>+		if (mpc-&gt;funcs-&gt;mcm.is_config_supported &amp;&amp;</div><div class='add'>+			!mpc-&gt;funcs-&gt;mcm.is_config_supported(width))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (mpc-&gt;funcs-&gt;program_lut_read_write_control)</div><div class='add'>+			mpc-&gt;funcs-&gt;program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id);</div><div class='add'>+		if (mpc-&gt;funcs-&gt;program_lut_mode)</div><div class='add'>+			mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id);</div><div class='add'>+</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_addr)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr);</div><div class='add'>+</div><div class='add'>+		if (mpc-&gt;funcs-&gt;mcm.program_bit_depth)</div><div class='add'>+			mpc-&gt;funcs-&gt;mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id);</div><div class='add'>+</div><div class='add'>+		switch (mcm_luts.lut3d_data.gpu_mem_params.layout) {</div><div class='add'>+		case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB:</div><div class='add'>+			mode = hubp_3dlut_fl_mode_native_1;</div><div class='add'>+			addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR:</div><div class='add'>+			mode = hubp_3dlut_fl_mode_native_2;</div><div class='add'>+			addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR:</div><div class='add'>+			mode = hubp_3dlut_fl_mode_transform;</div><div class='add'>+			addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			mode = hubp_3dlut_fl_mode_disable;</div><div class='add'>+			addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_mode)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_mode(hubp, mode);</div><div class='add'>+</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_addressing_mode)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode);</div><div class='add'>+</div><div class='add'>+		switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) {</div><div class='add'>+		case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB:</div><div class='add'>+			format = hubp_3dlut_fl_format_unorm_12msb_bitslice;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB:</div><div class='add'>+			format = hubp_3dlut_fl_format_unorm_12lsb_bitslice;</div><div class='add'>+			break;</div><div class='add'>+		case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10:</div><div class='add'>+			format = hubp_3dlut_fl_format_float_fp1_5_10;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_format)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_format(hubp, format);</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_update_3dlut_fl_bias_scale &amp;&amp;</div><div class='add'>+				mpc-&gt;funcs-&gt;mcm.program_bias_scale) {</div><div class='add'>+			mpc-&gt;funcs-&gt;mcm.program_bias_scale(mpc,</div><div class='add'>+				mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias,</div><div class='add'>+				mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale,</div><div class='add'>+				mpcc_id);</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_update_3dlut_fl_bias_scale(hubp,</div><div class='add'>+						mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias,</div><div class='add'>+						mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		//navi 4x has a bug and r and blue are swapped and need to be worked around here in</div><div class='add'>+		//TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x</div><div class='add'>+		switch (mcm_luts.lut3d_data.gpu_mem_params.component_order) {</div><div class='add'>+		case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA:</div><div class='add'>+		default:</div><div class='add'>+			crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15;</div><div class='add'>+			crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31;</div><div class='add'>+			crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_crossbar)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_program_3dlut_fl_crossbar(hubp,</div><div class='add'>+					crossbar_bit_slice_cr_r,</div><div class='add'>+					crossbar_bit_slice_y_g,</div><div class='add'>+					crossbar_bit_slice_cb_b);</div><div class='add'>+</div><div class='add'>+		if (mpc-&gt;funcs-&gt;mcm.program_lut_read_write_control)</div><div class='add'>+			mpc-&gt;funcs-&gt;mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id);</div><div class='add'>+</div><div class='add'>+		if (mpc-&gt;funcs-&gt;mcm.program_3dlut_size)</div><div class='add'>+			mpc-&gt;funcs-&gt;mcm.program_3dlut_size(mpc, width, mpcc_id);</div><div class='add'>+</div><div class='add'>+		if (mpc-&gt;funcs-&gt;update_3dlut_fast_load_select)</div><div class='add'>+			mpc-&gt;funcs-&gt;update_3dlut_fast_load_select(mpc, mpcc_id, hubp-&gt;inst);</div><div class='add'>+</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl)</div><div class='add'>+			hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl(hubp, true);</div><div class='add'>+		else {</div><div class='add'>+			if (mpc-&gt;funcs-&gt;program_lut_mode) {</div><div class='add'>+				mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);</div><div class='add'>+				mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);</div><div class='add'>+				mpc-&gt;funcs-&gt;program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+</div><div class='add'>+	if (hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl) {</div><div class='add'>+		hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl(hubp, true);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,</div><div class='add'>+				const struct dc_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	struct dpp *dpp_base = pipe_ctx-&gt;plane_res.dpp;</div><div class='add'>+	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc;</div><div class='add'>+	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+	bool result;</div><div class='add'>+	const struct pwl_params *lut_params = NULL;</div><div class='add'>+	bool rval;</div><div class='add'>+</div><div class='add'>+	if (plane_state-&gt;mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) {</div><div class='add'>+		dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state-&gt;mcm_luts, plane_state-&gt;lut_bank_a);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mpc-&gt;funcs-&gt;set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);</div><div class='add'>+	pipe_ctx-&gt;plane_state-&gt;mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;</div><div class='add'>+	// 1D LUT</div><div class='add'>+	if (plane_state-&gt;blend_tf.type == TF_TYPE_HWPWL)</div><div class='add'>+		lut_params = &amp;plane_state-&gt;blend_tf.pwl;</div><div class='add'>+	else if (plane_state-&gt;blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		rval = cm3_helper_translate_curve_to_hw_format(&amp;plane_state-&gt;blend_tf,</div><div class='add'>+				&amp;dpp_base-&gt;regamma_params, false);</div><div class='add'>+		lut_params = rval ? &amp;dpp_base-&gt;regamma_params : NULL;</div><div class='add'>+	}</div><div class='add'>+	result = mpc-&gt;funcs-&gt;program_1dlut(mpc, lut_params, mpcc_id);</div><div class='add'>+	lut_params = NULL;</div><div class='add'>+</div><div class='add'>+	// Shaper</div><div class='add'>+	if (plane_state-&gt;in_shaper_func.type == TF_TYPE_HWPWL)</div><div class='add'>+		lut_params = &amp;plane_state-&gt;in_shaper_func.pwl;</div><div class='add'>+	else if (plane_state-&gt;in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='add'>+		// TODO: dpp_base replace</div><div class='add'>+		rval = cm3_helper_translate_curve_to_hw_format(&amp;plane_state-&gt;in_shaper_func,</div><div class='add'>+				&amp;dpp_base-&gt;shaper_params, true);</div><div class='add'>+		lut_params = rval ? &amp;dpp_base-&gt;shaper_params : NULL;</div><div class='add'>+	}</div><div class='add'>+	result &amp;= mpc-&gt;funcs-&gt;program_shaper(mpc, lut_params, mpcc_id);</div><div class='add'>+</div><div class='add'>+	// 3D</div><div class='add'>+	if (mpc-&gt;funcs-&gt;program_3dlut) {</div><div class='add'>+		if (plane_state-&gt;lut3d_func.state.bits.initialized == 1)</div><div class='add'>+			result &amp;= mpc-&gt;funcs-&gt;program_3dlut(mpc, &amp;plane_state-&gt;lut3d_func.lut_3d, mpcc_id);</div><div class='add'>+		else</div><div class='add'>+			result &amp;= mpc-&gt;funcs-&gt;program_3dlut(mpc, NULL, mpcc_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_set_output_transfer_func(struct dc *dc,</div><div class='add'>+				struct pipe_ctx *pipe_ctx,</div><div class='add'>+				const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int mpcc_id = pipe_ctx-&gt;plane_res.hubp-&gt;inst;</div><div class='add'>+	struct mpc *mpc = pipe_ctx-&gt;stream_res.opp-&gt;ctx-&gt;dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+	const struct pwl_params *params = NULL;</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	/* program OGAM or 3DLUT only for the top pipe*/</div><div class='add'>+	if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {</div><div class='add'>+		/*program shaper and 3dlut in MPC*/</div><div class='add'>+		ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);</div><div class='add'>+		if (ret == false &amp;&amp; mpc-&gt;funcs-&gt;set_output_gamma) {</div><div class='add'>+			if (stream-&gt;out_transfer_func.type == TF_TYPE_HWPWL)</div><div class='add'>+				params = &amp;stream-&gt;out_transfer_func.pwl;</div><div class='add'>+			else if (pipe_ctx-&gt;stream-&gt;out_transfer_func.type ==</div><div class='add'>+					TF_TYPE_DISTRIBUTED_POINTS &amp;&amp;</div><div class='add'>+					cm3_helper_translate_curve_to_hw_format(</div><div class='add'>+					&amp;stream-&gt;out_transfer_func,</div><div class='add'>+					&amp;mpc-&gt;blender_params, false))</div><div class='add'>+				params = &amp;mpc-&gt;blender_params;</div><div class='add'>+			/* there are no ROM LUTs in OUTGAM */</div><div class='add'>+			if (stream-&gt;out_transfer_func.type == TF_TYPE_PREDEFINED)</div><div class='add'>+				BREAK_TO_DEBUGGER();</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mpc-&gt;funcs-&gt;set_output_gamma)</div><div class='add'>+		mpc-&gt;funcs-&gt;set_output_gamma(mpc, mpcc_id, params);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,</div><div class='add'>+				unsigned int *tmds_div)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+</div><div class='add'>+	if (dc_is_tmds_signal(stream-&gt;signal) || dc_is_virtual_signal(stream-&gt;signal)) {</div><div class='add'>+		if (stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)</div><div class='add'>+			*tmds_div = PIXEL_RATE_DIV_BY_2;</div><div class='add'>+		else</div><div class='add'>+			*tmds_div = PIXEL_RATE_DIV_BY_4;</div><div class='add'>+	} else {</div><div class='add'>+		*tmds_div = PIXEL_RATE_DIV_BY_1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (*tmds_div == PIXEL_RATE_DIV_NA)</div><div class='add'>+		ASSERT(false);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void enable_stream_timing_calc(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		unsigned int *tmds_div,</div><div class='add'>+		int *opp_inst,</div><div class='add'>+		int *opp_cnt,</div><div class='add'>+		struct pipe_ctx *opp_heads[MAX_PIPES],</div><div class='add'>+		bool *manual_mode,</div><div class='add'>+		struct drr_params *params,</div><div class='add'>+		unsigned int *event_triggers)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (dc_is_tmds_signal(stream-&gt;signal) || dc_is_virtual_signal(stream-&gt;signal))</div><div class='add'>+		dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);</div><div class='add'>+</div><div class='add'>+	*opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &amp;context-&gt;res_ctx, opp_heads);</div><div class='add'>+	for (i = 0; i &lt; *opp_cnt; i++)</div><div class='add'>+		opp_inst[i] = opp_heads[i]-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+</div><div class='add'>+	if (dc_is_tmds_signal(stream-&gt;signal)) {</div><div class='add'>+		stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 1;</div><div class='add'>+		if (stream-&gt;link-&gt;phy_state.symclk_state == SYMCLK_OFF_TX_OFF)</div><div class='add'>+			stream-&gt;link-&gt;phy_state.symclk_state = SYMCLK_ON_TX_OFF;</div><div class='add'>+		else</div><div class='add'>+			stream-&gt;link-&gt;phy_state.symclk_state = SYMCLK_ON_TX_ON;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	params-&gt;vertical_total_min = stream-&gt;adjust.v_total_min;</div><div class='add'>+	params-&gt;vertical_total_max = stream-&gt;adjust.v_total_max;</div><div class='add'>+	params-&gt;vertical_total_mid = stream-&gt;adjust.v_total_mid;</div><div class='add'>+	params-&gt;vertical_total_mid_frame_num = stream-&gt;adjust.v_total_mid_frame_num;</div><div class='add'>+</div><div class='add'>+	// DRR should set trigger event to monitor surface update event</div><div class='add'>+	if (stream-&gt;adjust.v_total_min != 0 &amp;&amp; stream-&gt;adjust.v_total_max != 0)</div><div class='add'>+		*event_triggers = 0x80;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dc_status dcn401_enable_stream_timing(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	struct drr_params params = {0};</div><div class='add'>+	unsigned int event_triggers = 0;</div><div class='add'>+	int opp_cnt = 1;</div><div class='add'>+	int opp_inst[MAX_PIPES] = {0};</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES] = {0};</div><div class='add'>+	struct dc_crtc_timing patched_crtc_timing = stream-&gt;timing;</div><div class='add'>+	bool manual_mode = false;</div><div class='add'>+	unsigned int tmds_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	unsigned int unused_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	int odm_slice_width;</div><div class='add'>+	int last_odm_slice_width;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))</div><div class='add'>+		return DC_OK;</div><div class='add'>+</div><div class='add'>+	enable_stream_timing_calc(pipe_ctx, context, dc, &amp;tmds_div, opp_inst,</div><div class='add'>+			&amp;opp_cnt, opp_heads, &amp;manual_mode, &amp;params, &amp;event_triggers);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div) {</div><div class='add'>+		dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div(</div><div class='add'>+			dc-&gt;res_pool-&gt;dccg, pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='add'>+			tmds_div, unused_div);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* TODO check if timing_changed, disable stream if timing changed */</div><div class='add'>+</div><div class='add'>+	if (opp_cnt &gt; 1) {</div><div class='add'>+		odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);</div><div class='add'>+		last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg,</div><div class='add'>+				opp_inst, opp_cnt,</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* set DTBCLK_P */</div><div class='add'>+	if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dtbclk_p_src) {</div><div class='add'>+		if (dc_is_dp_signal(stream-&gt;signal) || dc_is_virtual_signal(stream-&gt;signal)) {</div><div class='add'>+			dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dtbclk_p_src(dc-&gt;res_pool-&gt;dccg, DPREFCLK, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* HW program guide assume display already disable</div><div class='add'>+	 * by unplug sequence. OTG assume stop.</div><div class='add'>+	 */</div><div class='add'>+	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;enable_optc_clock(pipe_ctx-&gt;stream_res.tg, true);</div><div class='add'>+</div><div class='add'>+	if (false == pipe_ctx-&gt;clock_source-&gt;funcs-&gt;program_pix_clk(</div><div class='add'>+			pipe_ctx-&gt;clock_source,</div><div class='add'>+			&amp;pipe_ctx-&gt;stream_res.pix_clk_params,</div><div class='add'>+			dc-&gt;link_srv-&gt;dp_get_encoding_format(&amp;pipe_ctx-&gt;link_config.dp_link_settings),</div><div class='add'>+			&amp;pipe_ctx-&gt;pll_settings)) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwseq-&gt;funcs.PLAT_58856_wa &amp;&amp; (!dc_is_dp_signal(stream-&gt;signal)))</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.PLAT_58856_wa(context, pipe_ctx);</div><div class='add'>+</div><div class='add'>+	/* if we are padding, h_addressable needs to be adjusted */</div><div class='add'>+	if (dc-&gt;debug.enable_hblank_borrow) {</div><div class='add'>+		patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='add'>+		patched_crtc_timing.h_total = patched_crtc_timing.h_total + pipe_ctx-&gt;dsc_padding_params.dsc_htotal_padding;</div><div class='add'>+		patched_crtc_timing.pix_clk_100hz = pipe_ctx-&gt;dsc_padding_params.dsc_pix_clk_100hz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_timing(</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg,</div><div class='add'>+		&amp;patched_crtc_timing,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vready_offset_pixels,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vstartup_lines,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_offset_pixels,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_vupdate_width_pixels,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.pstate_keepout_start_lines,</div><div class='add'>+		pipe_ctx-&gt;stream-&gt;signal,</div><div class='add'>+		true);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; opp_cnt; i++) {</div><div class='add'>+		opp_heads[i]-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='add'>+				opp_heads[i]-&gt;stream_res.opp,</div><div class='add'>+				true);</div><div class='add'>+		opp_heads[i]-&gt;stream_res.opp-&gt;funcs-&gt;opp_program_left_edge_extra_pixel(</div><div class='add'>+				opp_heads[i]-&gt;stream_res.opp,</div><div class='add'>+				stream-&gt;timing.pixel_encoding,</div><div class='add'>+				resource_is_pipe_type(opp_heads[i], OTG_MASTER));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='add'>+			pipe_ctx-&gt;stream_res.opp,</div><div class='add'>+			true);</div><div class='add'>+</div><div class='add'>+	hws-&gt;funcs.blank_pixel_data(dc, pipe_ctx, true);</div><div class='add'>+</div><div class='add'>+	/* VTG is  within DCHUB command block. DCFCLK is always on */</div><div class='add'>+	if (false == pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipe_ctx-&gt;stream_res.tg)) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hws-&gt;funcs.wait_for_blank_complete(pipe_ctx-&gt;stream_res.opp);</div><div class='add'>+	set_drr_and_clear_adjust_pending(pipe_ctx, stream, &amp;params);</div><div class='add'>+</div><div class='add'>+	/* Event triggers and num frames initialized for DRR, but can be</div><div class='add'>+	 * later updated for PSR use. Note DRR trigger events are generated</div><div class='add'>+	 * regardless of whether num frames met.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg, event_triggers, 2);</div><div class='add'>+</div><div class='add'>+	/* TODO program crtc source select for non-virtual signal*/</div><div class='add'>+	/* TODO program FMT */</div><div class='add'>+	/* TODO setup link_enc */</div><div class='add'>+	/* TODO set stream attributes */</div><div class='add'>+	/* TODO program audio */</div><div class='add'>+	/* TODO enable stream if timing changed */</div><div class='add'>+	/* TODO unblank stream if DP */</div><div class='add'>+</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable)</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable(pipe_ctx-&gt;stream_res.tg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return DC_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	switch (link-&gt;link_enc-&gt;transmitter) {</div><div class='add'>+	case TRANSMITTER_UNIPHY_A:</div><div class='add'>+		return PHYD32CLKA;</div><div class='add'>+	case TRANSMITTER_UNIPHY_B:</div><div class='add'>+		return PHYD32CLKB;</div><div class='add'>+	case TRANSMITTER_UNIPHY_C:</div><div class='add'>+		return PHYD32CLKC;</div><div class='add'>+	case TRANSMITTER_UNIPHY_D:</div><div class='add'>+		return PHYD32CLKD;</div><div class='add'>+	case TRANSMITTER_UNIPHY_E:</div><div class='add'>+		return PHYD32CLKE;</div><div class='add'>+	default:</div><div class='add'>+		return PHYD32CLKA;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_enable_stream_calc(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		int *dp_hpo_inst,</div><div class='add'>+		enum phyd32clk_clock_source *phyd32clk,</div><div class='add'>+		unsigned int *tmds_div,</div><div class='add'>+		uint32_t *early_control)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dc_crtc_timing *timing = &amp;pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+	enum dc_lane_count lane_count =</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;link-&gt;cur_link_settings.lane_count;</div><div class='add'>+	uint32_t active_total_with_borders;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx))</div><div class='add'>+		*dp_hpo_inst = pipe_ctx-&gt;stream_res.hpo_dp_stream_enc-&gt;inst;</div><div class='add'>+</div><div class='add'>+	*phyd32clk = get_phyd32clk_src(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+</div><div class='add'>+	if (dc_is_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div);</div><div class='add'>+	else</div><div class='add'>+		*tmds_div = PIXEL_RATE_DIV_BY_1;</div><div class='add'>+</div><div class='add'>+	/* enable early control to avoid corruption on DP monitor*/</div><div class='add'>+	active_total_with_borders =</div><div class='add'>+			timing-&gt;h_addressable</div><div class='add'>+				+ timing-&gt;h_border_left</div><div class='add'>+				+ timing-&gt;h_border_right;</div><div class='add'>+</div><div class='add'>+	if (lane_count != 0)</div><div class='add'>+		*early_control = active_total_with_borders % lane_count;</div><div class='add'>+</div><div class='add'>+	if (*early_control == 0)</div><div class='add'>+		*early_control = lane_count;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	uint32_t early_control = 0;</div><div class='add'>+	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+	const struct link_hwss *link_hwss = get_link_hwss(link, &amp;pipe_ctx-&gt;link_res);</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+	enum phyd32clk_clock_source phyd32clk;</div><div class='add'>+	int dp_hpo_inst = 0;</div><div class='add'>+	unsigned int tmds_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	unsigned int unused_div = PIXEL_RATE_DIV_NA;</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='add'>+	struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='add'>+	dcn401_enable_stream_calc(pipe_ctx, &amp;dp_hpo_inst, &amp;phyd32clk,</div><div class='add'>+				&amp;tmds_div, &amp;early_control);</div><div class='add'>+</div><div class='add'>+	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal) || dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='add'>+		if (dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='add'>+			dccg-&gt;funcs-&gt;set_dpstreamclk(dccg, DPREFCLK, tg-&gt;inst, dp_hpo_inst);</div><div class='add'>+			if (link-&gt;cur_link_settings.link_rate == LINK_RATE_UNKNOWN) {</div><div class='add'>+				dccg-&gt;funcs-&gt;disable_symclk32_se(dccg, dp_hpo_inst);</div><div class='add'>+			} else {</div><div class='add'>+				dccg-&gt;funcs-&gt;enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			dccg-&gt;funcs-&gt;enable_symclk_se(dccg, stream_enc-&gt;stream_enc_inst,</div><div class='add'>+					link_enc-&gt;transmitter - TRANSMITTER_UNIPHY_A);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div) {</div><div class='add'>+		dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_pixel_rate_div(</div><div class='add'>+			dc-&gt;res_pool-&gt;dccg,</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='add'>+			tmds_div,</div><div class='add'>+			unused_div);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	link_hwss-&gt;setup_stream_encoder(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_state-&gt;flip_immediate != 1) {</div><div class='add'>+		if (dc-&gt;hwss.program_dmdata_engine)</div><div class='add'>+			dc-&gt;hwss.program_dmdata_engine(pipe_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc-&gt;hwss.update_info_frame(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);</div><div class='add'>+</div><div class='add'>+	tg-&gt;funcs-&gt;set_early_control(tg, early_control);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy)</div><div class='add'>+{</div><div class='add'>+	if (cursor_width &lt;= 128) {</div><div class='add'>+		pos_cpy-&gt;x_hotspot /= 2;</div><div class='add'>+		pos_cpy-&gt;x_hotspot += 1;</div><div class='add'>+	} else {</div><div class='add'>+		pos_cpy-&gt;x_hotspot /= 2;</div><div class='add'>+		pos_cpy-&gt;x_hotspot += 2;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void disable_link_output_symclk_on_tx_off(struct dc_link *link, enum dp_link_encoding link_encoding)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx = NULL;</div><div class='add'>+	uint8_t i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;link == link &amp;&amp; pipe_ctx-&gt;top_pipe == NULL) {</div><div class='add'>+			pipe_ctx-&gt;clock_source-&gt;funcs-&gt;program_pix_clk(</div><div class='add'>+					pipe_ctx-&gt;clock_source,</div><div class='add'>+					&amp;pipe_ctx-&gt;stream_res.pix_clk_params,</div><div class='add'>+					link_encoding,</div><div class='add'>+					&amp;pipe_ctx-&gt;pll_settings);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_disable_link_output(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='add'>+		enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	const struct link_hwss *link_hwss = get_link_hwss(link, link_res);</div><div class='add'>+	struct dmcu *dmcu = dc-&gt;res_pool-&gt;dmcu;</div><div class='add'>+</div><div class='add'>+	if (signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+			link-&gt;dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='add'>+			!link-&gt;skip_implict_edp_power_control)</div><div class='add'>+		link-&gt;dc-&gt;hwss.edp_backlight_control(link, false);</div><div class='add'>+	else if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;lock_phy)</div><div class='add'>+		dmcu-&gt;funcs-&gt;lock_phy(dmcu);</div><div class='add'>+</div><div class='add'>+	if (dc_is_tmds_signal(signal) &amp;&amp; link-&gt;phy_state.symclk_ref_cnts.otg &gt; 0) {</div><div class='add'>+		disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING);</div><div class='add'>+		link-&gt;phy_state.symclk_state = SYMCLK_ON_TX_OFF;</div><div class='add'>+	} else {</div><div class='add'>+		link_hwss-&gt;disable_link_output(link, link_res, signal);</div><div class='add'>+		link-&gt;phy_state.symclk_state = SYMCLK_OFF_TX_OFF;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+			link-&gt;dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='add'>+			!link-&gt;skip_implict_edp_power_control)</div><div class='add'>+		link-&gt;dc-&gt;hwss.edp_power_control(link, false);</div><div class='add'>+	else if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;lock_phy)</div><div class='add'>+		dmcu-&gt;funcs-&gt;unlock_phy(dmcu);</div><div class='add'>+</div><div class='add'>+	dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct dc_cursor_position pos_cpy = pipe_ctx-&gt;stream-&gt;cursor_position;</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+	struct dpp *dpp = pipe_ctx-&gt;plane_res.dpp;</div><div class='add'>+	struct dc_cursor_mi_param param = {</div><div class='add'>+		.pixel_clk_khz = pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz / 10,</div><div class='add'>+		.ref_clk_khz = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz,</div><div class='add'>+		.viewport = pipe_ctx-&gt;plane_res.scl_data.viewport,</div><div class='add'>+		.recout = pipe_ctx-&gt;plane_res.scl_data.recout,</div><div class='add'>+		.h_scale_ratio = pipe_ctx-&gt;plane_res.scl_data.ratios.horz,</div><div class='add'>+		.v_scale_ratio = pipe_ctx-&gt;plane_res.scl_data.ratios.vert,</div><div class='add'>+		.rotation = pipe_ctx-&gt;plane_state-&gt;rotation,</div><div class='add'>+		.mirror = pipe_ctx-&gt;plane_state-&gt;horizontal_mirror,</div><div class='add'>+		.stream = pipe_ctx-&gt;stream</div><div class='add'>+	};</div><div class='add'>+	struct rect odm_slice_src = { 0 };</div><div class='add'>+	bool odm_combine_on = (pipe_ctx-&gt;next_odm_pipe != NULL) ||</div><div class='add'>+		(pipe_ctx-&gt;prev_odm_pipe != NULL);</div><div class='add'>+	int prev_odm_width = 0;</div><div class='add'>+	struct pipe_ctx *prev_odm_pipe = NULL;</div><div class='add'>+	bool mpc_combine_on = false;</div><div class='add'>+	int  bottom_pipe_x_pos = 0;</div><div class='add'>+</div><div class='add'>+	int x_pos = pos_cpy.x;</div><div class='add'>+	int y_pos = pos_cpy.y;</div><div class='add'>+	int recout_x_pos = 0;</div><div class='add'>+	int recout_y_pos = 0;</div><div class='add'>+</div><div class='add'>+	if ((pipe_ctx-&gt;top_pipe != NULL) || (pipe_ctx-&gt;bottom_pipe != NULL)) {</div><div class='add'>+		if ((pipe_ctx-&gt;plane_state-&gt;src_rect.width != pipe_ctx-&gt;plane_res.scl_data.viewport.width) ||</div><div class='add'>+			(pipe_ctx-&gt;plane_state-&gt;src_rect.height != pipe_ctx-&gt;plane_res.scl_data.viewport.height)) {</div><div class='add'>+			mpc_combine_on = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DCN4 moved cursor composition after Scaler, so in HW it is in</div><div class='add'>+	 * recout space and for HW Cursor position programming need to</div><div class='add'>+	 * translate to recout space.</div><div class='add'>+	 *</div><div class='add'>+	 * Cursor X and Y position programmed into HW can't be negative,</div><div class='add'>+	 * in fact it is X, Y coordinate shifted for the HW Cursor Hot spot</div><div class='add'>+	 * position that goes into HW X and Y coordinates while HW Hot spot</div><div class='add'>+	 * X and Y coordinates are length relative to the cursor top left</div><div class='add'>+	 * corner, hotspot must be smaller than the cursor size.</div><div class='add'>+	 *</div><div class='add'>+	 * DMs/DC interface for Cursor position is in stream-&gt;src space, and</div><div class='add'>+	 * DMs supposed to transform Cursor coordinates to stream-&gt;src space,</div><div class='add'>+	 * then here we need to translate Cursor coordinates to stream-&gt;dst</div><div class='add'>+	 * space, as now in HW, Cursor coordinates are in per pipe recout</div><div class='add'>+	 * space, and for the given pipe valid coordinates are only in range</div><div class='add'>+	 * from 0,0 - recout width, recout height space.</div><div class='add'>+	 * If certain pipe combining is in place, need to further adjust per</div><div class='add'>+	 * pipe to make sure each pipe enabling cursor on its part of the</div><div class='add'>+	 * screen.</div><div class='add'>+	 */</div><div class='add'>+	x_pos = pipe_ctx-&gt;stream-&gt;dst.x + x_pos * pipe_ctx-&gt;stream-&gt;dst.width /</div><div class='add'>+		pipe_ctx-&gt;stream-&gt;src.width;</div><div class='add'>+	y_pos = pipe_ctx-&gt;stream-&gt;dst.y + y_pos * pipe_ctx-&gt;stream-&gt;dst.height /</div><div class='add'>+		pipe_ctx-&gt;stream-&gt;src.height;</div><div class='add'>+</div><div class='add'>+	/* If the cursor's source viewport is clipped then we need to</div><div class='add'>+	 * translate the cursor to appear in the correct position on</div><div class='add'>+	 * the screen.</div><div class='add'>+	 *</div><div class='add'>+	 * This translation isn't affected by scaling so it needs to be</div><div class='add'>+	 * done *after* we adjust the position for the scale factor.</div><div class='add'>+	 *</div><div class='add'>+	 * This is only done by opt-in for now since there are still</div><div class='add'>+	 * some usecases like tiled display that might enable the</div><div class='add'>+	 * cursor on both streams while expecting dc to clip it.</div><div class='add'>+	 */</div><div class='add'>+	if (pos_cpy.translate_by_source) {</div><div class='add'>+		x_pos += pipe_ctx-&gt;plane_state-&gt;src_rect.x;</div><div class='add'>+		y_pos += pipe_ctx-&gt;plane_state-&gt;src_rect.y;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Adjust for ODM Combine</div><div class='add'>+	 * next/prev_odm_offset is to account for scaled modes that have underscan</div><div class='add'>+	 */</div><div class='add'>+	if (odm_combine_on) {</div><div class='add'>+		prev_odm_pipe = pipe_ctx-&gt;prev_odm_pipe;</div><div class='add'>+</div><div class='add'>+		while (prev_odm_pipe != NULL) {</div><div class='add'>+			odm_slice_src = resource_get_odm_slice_src_rect(prev_odm_pipe);</div><div class='add'>+			prev_odm_width += odm_slice_src.width;</div><div class='add'>+			prev_odm_pipe = prev_odm_pipe-&gt;prev_odm_pipe;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		x_pos -= (prev_odm_width);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If the position is negative then we need to add to the hotspot</div><div class='add'>+	 * to fix cursor size between ODM slices</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (x_pos &lt; 0) {</div><div class='add'>+		pos_cpy.x_hotspot -= x_pos;</div><div class='add'>+		if (hubp-&gt;curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)</div><div class='add'>+			adjust_hotspot_between_slices_for_2x_magnify(hubp-&gt;curs_attr.width, &amp;pos_cpy);</div><div class='add'>+		x_pos = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (y_pos &lt; 0) {</div><div class='add'>+		pos_cpy.y_hotspot -= y_pos;</div><div class='add'>+		y_pos = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If the position on bottom MPC pipe is negative then we need to add to the hotspot and</div><div class='add'>+	 * adjust x_pos on bottom pipe to make cursor visible when crossing between MPC slices.</div><div class='add'>+	 */</div><div class='add'>+	if (mpc_combine_on &amp;&amp;</div><div class='add'>+		pipe_ctx-&gt;top_pipe &amp;&amp;</div><div class='add'>+		(pipe_ctx == pipe_ctx-&gt;top_pipe-&gt;bottom_pipe)) {</div><div class='add'>+</div><div class='add'>+		bottom_pipe_x_pos = x_pos - pipe_ctx-&gt;plane_res.scl_data.recout.x;</div><div class='add'>+		if (bottom_pipe_x_pos &lt; 0) {</div><div class='add'>+			x_pos = pipe_ctx-&gt;plane_res.scl_data.recout.x;</div><div class='add'>+			pos_cpy.x_hotspot -= bottom_pipe_x_pos;</div><div class='add'>+			if (hubp-&gt;curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)</div><div class='add'>+				adjust_hotspot_between_slices_for_2x_magnify(hubp-&gt;curs_attr.width, &amp;pos_cpy);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pos_cpy.x = (uint32_t)x_pos;</div><div class='add'>+	pos_cpy.y = (uint32_t)y_pos;</div><div class='add'>+</div><div class='add'>+	if (pos_cpy.enable &amp;&amp; resource_can_pipe_disable_cursor(pipe_ctx))</div><div class='add'>+		pos_cpy.enable = false;</div><div class='add'>+</div><div class='add'>+	x_pos = pos_cpy.x - param.recout.x;</div><div class='add'>+	y_pos = pos_cpy.y - param.recout.y;</div><div class='add'>+</div><div class='add'>+	recout_x_pos = x_pos - pos_cpy.x_hotspot;</div><div class='add'>+	recout_y_pos = y_pos - pos_cpy.y_hotspot;</div><div class='add'>+</div><div class='add'>+	if (recout_x_pos &gt;= (int)param.recout.width)</div><div class='add'>+		pos_cpy.enable = false;  /* not visible beyond right edge*/</div><div class='add'>+</div><div class='add'>+	if (recout_y_pos &gt;= (int)param.recout.height)</div><div class='add'>+		pos_cpy.enable = false;  /* not visible beyond bottom edge*/</div><div class='add'>+</div><div class='add'>+	if (recout_x_pos + (int)hubp-&gt;curs_attr.width &lt;= 0)</div><div class='add'>+		pos_cpy.enable = false;  /* not visible beyond left edge*/</div><div class='add'>+</div><div class='add'>+	if (recout_y_pos + (int)hubp-&gt;curs_attr.height &lt;= 0)</div><div class='add'>+		pos_cpy.enable = false;  /* not visible beyond top edge*/</div><div class='add'>+</div><div class='add'>+	hubp-&gt;funcs-&gt;set_cursor_position(hubp, &amp;pos_cpy, &amp;param);</div><div class='add'>+	dpp-&gt;funcs-&gt;set_cursor_position(dpp, &amp;pos_cpy, &amp;param, hubp-&gt;curs_attr.width, hubp-&gt;curs_attr.height);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_check_no_memory_request_for_cab(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* First, check no-memory-request case */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+		if ((dc-&gt;current_state-&gt;stream_status[i].plane_count) &amp;&amp;</div><div class='add'>+			(dc-&gt;current_state-&gt;streams[i]-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))</div><div class='add'>+			/* Fail eligibility on a visible stream */</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	uint8_t num_ways = 0;</div><div class='add'>+	uint32_t mall_ss_size_bytes = 0;</div><div class='add'>+</div><div class='add'>+	mall_ss_size_bytes = ctx-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes;</div><div class='add'>+	// TODO add additional logic for PSR active stream exclusion optimization</div><div class='add'>+	// mall_ss_psr_active_size_bytes = ctx-&gt;bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;</div><div class='add'>+</div><div class='add'>+	// Include cursor size for CAB allocation</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;ctx-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe-&gt;stream || !pipe-&gt;plane_state)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Convert number of cache lines required to number of ways</div><div class='add'>+	if (dc-&gt;debug.force_mall_ss_num_ways &gt; 0)</div><div class='add'>+		num_ways = dc-&gt;debug.force_mall_ss_num_ways;</div><div class='add'>+	else if (dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes)</div><div class='add'>+		num_ways = dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);</div><div class='add'>+	else</div><div class='add'>+		num_ways = 0;</div><div class='add'>+</div><div class='add'>+	return num_ways;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	uint8_t ways, i;</div><div class='add'>+	int j;</div><div class='add'>+	bool mall_ss_unsupported = false;</div><div class='add'>+	struct dc_plane_state *plane = NULL;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;ctx-&gt;dmub_srv || !dc-&gt;current_state)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+		/* MALL SS messaging is not supported with PSR at this time */</div><div class='add'>+		if (dc-&gt;current_state-&gt;streams[i] != NULL &amp;&amp;</div><div class='add'>+				dc-&gt;current_state-&gt;streams[i]-&gt;link-&gt;psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {</div><div class='add'>+			DC_LOG_MALL("MALL SS not supported with PSR at this time\n");</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+	cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;</div><div class='add'>+	cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (dcn401_check_no_memory_request_for_cab(dc)) {</div><div class='add'>+			/* 1. Check no memory request case for CAB.</div><div class='add'>+			 * If no memory request case, send CAB_ACTION NO_DCN_REQ DMUB message</div><div class='add'>+			 */</div><div class='add'>+			DC_LOG_MALL("sending CAB action NO_DCN_REQ\n");</div><div class='add'>+			cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;</div><div class='add'>+		} else {</div><div class='add'>+			/* 2. Check if all surfaces can fit in CAB.</div><div class='add'>+			 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message</div><div class='add'>+			 * and configure HUBP's to fetch from MALL</div><div class='add'>+			 */</div><div class='add'>+			ways = dcn401_calculate_cab_allocation(dc, dc-&gt;current_state);</div><div class='add'>+</div><div class='add'>+			/* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,</div><div class='add'>+			 * or TMZ surface, don't try to enter MALL.</div><div class='add'>+			 */</div><div class='add'>+			for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+				for (j = 0; j &lt; dc-&gt;current_state-&gt;stream_status[i].plane_count; j++) {</div><div class='add'>+					plane = dc-&gt;current_state-&gt;stream_status[i].plane_states[j];</div><div class='add'>+</div><div class='add'>+					if (plane-&gt;address.type == PLN_ADDR_TYPE_GRPH_STEREO ||</div><div class='add'>+							plane-&gt;address.tmz_surface) {</div><div class='add'>+						mall_ss_unsupported = true;</div><div class='add'>+						break;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+				if (mall_ss_unsupported)</div><div class='add'>+					break;</div><div class='add'>+			}</div><div class='add'>+			if (ways &lt;= dc-&gt;caps.cache_num_ways &amp;&amp; !mall_ss_unsupported) {</div><div class='add'>+				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;</div><div class='add'>+				cmd.cab.cab_alloc_ways = ways;</div><div class='add'>+				DC_LOG_MALL("cab allocation: %d ways. CAB action: DCN_SS_FIT_IN_CAB\n", ways);</div><div class='add'>+			} else {</div><div class='add'>+				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB;</div><div class='add'>+				DC_LOG_MALL("frame does not fit in CAB: %d ways required. CAB action: DCN_SS_NOT_FIT_IN_CAB\n", ways);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* Disable CAB */</div><div class='add'>+		cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;</div><div class='add'>+		DC_LOG_MALL("idle optimization disabled\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,</div><div class='add'>+		const struct pipe_ctx *top_pipe)</div><div class='add'>+{</div><div class='add'>+	bool is_wait_needed = false;</div><div class='add'>+	const struct pipe_ctx *pipe_ctx = top_pipe;</div><div class='add'>+</div><div class='add'>+	/* check if any surfaces are updating address while using flip immediate and dcc */</div><div class='add'>+	while (pipe_ctx != NULL) {</div><div class='add'>+		if (pipe_ctx-&gt;plane_state &amp;&amp;</div><div class='add'>+				pipe_ctx-&gt;plane_state-&gt;dcc.enable &amp;&amp;</div><div class='add'>+				pipe_ctx-&gt;plane_state-&gt;flip_immediate &amp;&amp;</div><div class='add'>+				pipe_ctx-&gt;plane_state-&gt;update_flags.bits.addr_update) {</div><div class='add'>+			is_wait_needed = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* check next pipe */</div><div class='add'>+		pipe_ctx = pipe_ctx-&gt;bottom_pipe;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (is_wait_needed &amp;&amp; dc-&gt;debug.dcc_meta_propagation_delay_us &gt; 0) {</div><div class='add'>+		udelay(dc-&gt;debug.dcc_meta_propagation_delay_us);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_prepare_bandwidth(struct dc *dc,</div><div class='add'>+	struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+	bool p_state_change_support = context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='add'>+	unsigned int compbuf_size = 0;</div><div class='add'>+</div><div class='add'>+	/* Any transition into P-State support should disable MCLK switching first to avoid hangs */</div><div class='add'>+	if (p_state_change_support) {</div><div class='add'>+		dc-&gt;optimized_required = true;</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='add'>+		if (dc-&gt;clk_mgr-&gt;clks.dramclk_khz &lt;= dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk * 1000 &amp;&amp;</div><div class='add'>+				context-&gt;bw_ctx.bw.dcn.clk.dramclk_khz &gt; dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk * 1000)</div><div class='add'>+			dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk(dc-&gt;clk_mgr, dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[dc-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.num_entries - 1].memclk_mhz);</div><div class='add'>+</div><div class='add'>+	/* Increase clocks */</div><div class='add'>+	dc-&gt;clk_mgr-&gt;funcs-&gt;update_clocks(</div><div class='add'>+			dc-&gt;clk_mgr,</div><div class='add'>+			context,</div><div class='add'>+			false);</div><div class='add'>+</div><div class='add'>+	/* program dchubbub watermarks:</div><div class='add'>+	 * For assigning optimized_required, use |= operator since we don't want</div><div class='add'>+	 * to clear the value if the optimize has not happened yet</div><div class='add'>+	 */</div><div class='add'>+	dc-&gt;optimized_required |= hubbub-&gt;funcs-&gt;program_watermarks(hubbub,</div><div class='add'>+					&amp;context-&gt;bw_ctx.bw.dcn.watermarks,</div><div class='add'>+					dc-&gt;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000,</div><div class='add'>+					false);</div><div class='add'>+	/* update timeout thresholds */</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_arbiter) {</div><div class='add'>+		dc-&gt;optimized_required |= hubbub-&gt;funcs-&gt;program_arbiter(hubbub, &amp;context-&gt;bw_ctx.bw.dcn.arb_regs, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* decrease compbuf size */</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_compbuf_segments) {</div><div class='add'>+		compbuf_size = context-&gt;bw_ctx.bw.dcn.arb_regs.compbuf_size;</div><div class='add'>+		dc-&gt;optimized_required |= (compbuf_size != dc-&gt;current_state-&gt;bw_ctx.bw.dcn.arb_regs.compbuf_size);</div><div class='add'>+</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_compbuf_segments(hubbub, compbuf_size, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.fams2_config.bits.enable) {</div><div class='add'>+		dcn401_dmub_hw_control_lock(dc, context, true);</div><div class='add'>+		dcn401_fams2_update_config(dc, context, false);</div><div class='add'>+		dcn401_dmub_hw_control_lock(dc, context, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p_state_change_support != context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support) {</div><div class='add'>+		/* After disabling P-State, restore the original value to ensure we get the correct P-State</div><div class='add'>+		 * on the next optimize. */</div><div class='add'>+		context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_optimize_bandwidth(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+</div><div class='add'>+	/* enable fams2 if needed */</div><div class='add'>+	if (dc-&gt;debug.fams2_config.bits.enable) {</div><div class='add'>+		dcn401_dmub_hw_control_lock(dc, context, true);</div><div class='add'>+		dcn401_fams2_update_config(dc, context, true);</div><div class='add'>+		dcn401_dmub_hw_control_lock(dc, context, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* program dchubbub watermarks */</div><div class='add'>+	hubbub-&gt;funcs-&gt;program_watermarks(hubbub,</div><div class='add'>+					&amp;context-&gt;bw_ctx.bw.dcn.watermarks,</div><div class='add'>+					dc-&gt;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000,</div><div class='add'>+					true);</div><div class='add'>+	/* update timeout thresholds */</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_arbiter) {</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_arbiter(hubbub, &amp;context-&gt;bw_ctx.bw.dcn.arb_regs, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;clk_mgr-&gt;dc_mode_softmax_enabled)</div><div class='add'>+		if (dc-&gt;clk_mgr-&gt;clks.dramclk_khz &gt; dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk * 1000 &amp;&amp;</div><div class='add'>+				context-&gt;bw_ctx.bw.dcn.clk.dramclk_khz &lt;= dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk * 1000)</div><div class='add'>+			dc-&gt;clk_mgr-&gt;funcs-&gt;set_max_memclk(dc-&gt;clk_mgr, dc-&gt;clk_mgr-&gt;bw_params-&gt;dc_mode_softmax_memclk);</div><div class='add'>+</div><div class='add'>+	/* increase compbuf size */</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_compbuf_segments)</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_compbuf_segments(hubbub, context-&gt;bw_ctx.bw.dcn.arb_regs.compbuf_size, true);</div><div class='add'>+</div><div class='add'>+	dc-&gt;clk_mgr-&gt;funcs-&gt;update_clocks(</div><div class='add'>+			dc-&gt;clk_mgr,</div><div class='add'>+			context,</div><div class='add'>+			true);</div><div class='add'>+	if (context-&gt;bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; ++i) {</div><div class='add'>+			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+			if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;program_extended_blank</div><div class='add'>+				&amp;&amp; pipe_ctx-&gt;stream-&gt;adjust.v_total_min == pipe_ctx-&gt;stream-&gt;adjust.v_total_max</div><div class='add'>+				&amp;&amp; pipe_ctx-&gt;stream-&gt;adjust.v_total_max &gt; pipe_ctx-&gt;stream-&gt;timing.v_total)</div><div class='add'>+					pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;program_extended_blank(pipe_ctx-&gt;plane_res.hubp,</div><div class='add'>+						pipe_ctx-&gt;dlg_regs.min_dst_y_next_start);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_dmub_hw_control_lock(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool lock)</div><div class='add'>+{</div><div class='add'>+	/* use always for now */</div><div class='add'>+	union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;debug.fams2_config.bits.enable &amp;&amp; !dc_dmub_srv_is_cursor_offload_enabled(dc))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;</div><div class='add'>+	hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;</div><div class='add'>+	hw_lock_cmd.bits.lock = lock;</div><div class='add'>+	hw_lock_cmd.bits.should_release = !lock;</div><div class='add'>+	dmub_hw_lock_mgr_inbox0_cmd(dc-&gt;ctx-&gt;dmub_srv, hw_lock_cmd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = params-&gt;dmub_hw_control_lock_fast_params.dc;</div><div class='add'>+	bool lock = params-&gt;dmub_hw_control_lock_fast_params.lock;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;dmub_hw_control_lock_fast_params.is_required) {</div><div class='add'>+		union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };</div><div class='add'>+</div><div class='add'>+		hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;</div><div class='add'>+		hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;</div><div class='add'>+		hw_lock_cmd.bits.lock = lock;</div><div class='add'>+		hw_lock_cmd.bits.should_release = !lock;</div><div class='add'>+		dmub_hw_lock_mgr_inbox0_cmd(dc-&gt;ctx-&gt;dmub_srv, hw_lock_cmd);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)</div><div class='add'>+{</div><div class='add'>+	bool fams2_required;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !dc-&gt;debug.fams2_config.bits.enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fams2_required = context-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;</div><div class='add'>+</div><div class='add'>+	dc_dmub_srv_fams2_update_config(dc, context, enable &amp;&amp; fams2_required);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *otg_master)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct pipe_ctx *old_pipe;</div><div class='add'>+	struct pipe_ctx *new_pipe;</div><div class='add'>+	struct pipe_ctx *old_opp_heads[MAX_PIPES];</div><div class='add'>+	struct pipe_ctx *old_otg_master;</div><div class='add'>+	int old_opp_head_count = 0;</div><div class='add'>+</div><div class='add'>+	old_otg_master = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[otg_master-&gt;pipe_idx];</div><div class='add'>+</div><div class='add'>+	if (resource_is_pipe_type(old_otg_master, OTG_MASTER)) {</div><div class='add'>+		old_opp_head_count = resource_get_opp_heads_for_otg_master(old_otg_master,</div><div class='add'>+									   &amp;dc-&gt;current_state-&gt;res_ctx,</div><div class='add'>+									   old_opp_heads);</div><div class='add'>+	} else {</div><div class='add'>+		// DC cannot assume that the current state and the new state</div><div class='add'>+		// share the same OTG pipe since this is not true when called</div><div class='add'>+		// in the context of a commit stream not checked. Hence, set</div><div class='add'>+		// old_otg_master to NULL to skip the DSC configuration.</div><div class='add'>+		old_otg_master = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (otg_master-&gt;stream_res.dsc)</div><div class='add'>+		dcn32_update_dsc_on_stream(otg_master,</div><div class='add'>+				otg_master-&gt;stream-&gt;timing.flags.DSC);</div><div class='add'>+	if (old_otg_master &amp;&amp; old_otg_master-&gt;stream_res.dsc) {</div><div class='add'>+		for (i = 0; i &lt; old_opp_head_count; i++) {</div><div class='add'>+			old_pipe = old_opp_heads[i];</div><div class='add'>+			new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[old_pipe-&gt;pipe_idx];</div><div class='add'>+			if (old_pipe-&gt;stream_res.dsc &amp;&amp; !new_pipe-&gt;stream_res.dsc)</div><div class='add'>+				old_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disconnect(</div><div class='add'>+						old_pipe-&gt;stream_res.dsc);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_odm(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *otg_master)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='add'>+	int opp_inst[MAX_PIPES] = {0};</div><div class='add'>+	int opp_head_count;</div><div class='add'>+	int odm_slice_width = resource_get_odm_slice_dst_width(otg_master, false);</div><div class='add'>+	int last_odm_slice_width = resource_get_odm_slice_dst_width(otg_master, true);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	opp_head_count = resource_get_opp_heads_for_otg_master(</div><div class='add'>+			otg_master, &amp;context-&gt;res_ctx, opp_heads);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; opp_head_count; i++)</div><div class='add'>+		opp_inst[i] = opp_heads[i]-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+	if (opp_head_count &gt; 1)</div><div class='add'>+		otg_master-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_combine(</div><div class='add'>+				otg_master-&gt;stream_res.tg,</div><div class='add'>+				opp_inst, opp_head_count,</div><div class='add'>+				odm_slice_width, last_odm_slice_width);</div><div class='add'>+	else</div><div class='add'>+		otg_master-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='add'>+				otg_master-&gt;stream_res.tg,</div><div class='add'>+				&amp;otg_master-&gt;stream-&gt;timing);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; opp_head_count; i++) {</div><div class='add'>+		opp_heads[i]-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control(</div><div class='add'>+				opp_heads[i]-&gt;stream_res.opp,</div><div class='add'>+				true);</div><div class='add'>+		opp_heads[i]-&gt;stream_res.opp-&gt;funcs-&gt;opp_program_left_edge_extra_pixel(</div><div class='add'>+				opp_heads[i]-&gt;stream_res.opp,</div><div class='add'>+				opp_heads[i]-&gt;stream-&gt;timing.pixel_encoding,</div><div class='add'>+				resource_is_pipe_type(opp_heads[i], OTG_MASTER));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	update_dsc_for_odm_change(dc, context, otg_master);</div><div class='add'>+</div><div class='add'>+	if (!resource_is_pipe_type(otg_master, DPP_PIPE))</div><div class='add'>+		/*</div><div class='add'>+		 * blank pattern is generated by OPP, reprogram blank pattern</div><div class='add'>+		 * due to OPP count change</div><div class='add'>+		 */</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.blank_pixel_data(dc, otg_master, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *old_pipe;</div><div class='add'>+	struct pipe_ctx *new_pipe;</div><div class='add'>+	struct pipe_ctx *old_opp_heads[MAX_PIPES];</div><div class='add'>+	struct pipe_ctx *old_otg_master;</div><div class='add'>+	int old_opp_head_count = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	old_otg_master = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[otg_master-&gt;pipe_idx];</div><div class='add'>+</div><div class='add'>+	if (resource_is_pipe_type(old_otg_master, OTG_MASTER)) {</div><div class='add'>+		old_opp_head_count = resource_get_opp_heads_for_otg_master(old_otg_master,</div><div class='add'>+			&amp;dc-&gt;current_state-&gt;res_ctx,</div><div class='add'>+			old_opp_heads);</div><div class='add'>+	} else {</div><div class='add'>+		old_otg_master = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Process new DSC configuration if DSC is enabled */</div><div class='add'>+	if (otg_master-&gt;stream_res.dsc &amp;&amp; otg_master-&gt;stream-&gt;timing.flags.DSC) {</div><div class='add'>+		struct dc_stream_state *stream = otg_master-&gt;stream;</div><div class='add'>+		struct pipe_ctx *odm_pipe;</div><div class='add'>+		int opp_cnt = 1;</div><div class='add'>+		int last_dsc_calc = 0;</div><div class='add'>+		bool should_use_dto_dscclk = (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dto_dscclk != NULL) &amp;&amp;</div><div class='add'>+				stream-&gt;timing.pix_clk_100hz &gt; 480000;</div><div class='add'>+</div><div class='add'>+		/* Count ODM pipes */</div><div class='add'>+		for (odm_pipe = otg_master-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='add'>+			opp_cnt++;</div><div class='add'>+</div><div class='add'>+		int num_slices_h = stream-&gt;timing.dsc_cfg.num_slices_h / opp_cnt;</div><div class='add'>+</div><div class='add'>+		/* Step 1: Set DTO DSCCLK for main DSC if needed */</div><div class='add'>+		if (should_use_dto_dscclk) {</div><div class='add'>+			hwss_add_dccg_set_dto_dscclk(seq_state, dc-&gt;res_pool-&gt;dccg,</div><div class='add'>+					otg_master-&gt;stream_res.dsc-&gt;inst, num_slices_h);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Step 2: Calculate and set DSC config for main DSC */</div><div class='add'>+		last_dsc_calc = *seq_state-&gt;num_steps;</div><div class='add'>+		hwss_add_dsc_calculate_and_set_config(seq_state, otg_master, true, opp_cnt);</div><div class='add'>+</div><div class='add'>+		/* Step 3: Enable main DSC block */</div><div class='add'>+		hwss_add_dsc_enable_with_opp(seq_state, otg_master);</div><div class='add'>+</div><div class='add'>+		/* Step 4: Configure and enable ODM DSC blocks */</div><div class='add'>+		for (odm_pipe = otg_master-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+			if (!odm_pipe-&gt;stream_res.dsc)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			/* Set DTO DSCCLK for ODM DSC if needed */</div><div class='add'>+			if (should_use_dto_dscclk) {</div><div class='add'>+				hwss_add_dccg_set_dto_dscclk(seq_state, dc-&gt;res_pool-&gt;dccg,</div><div class='add'>+						odm_pipe-&gt;stream_res.dsc-&gt;inst, num_slices_h);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			/* Calculate and set DSC config for ODM DSC */</div><div class='add'>+			last_dsc_calc = *seq_state-&gt;num_steps;</div><div class='add'>+			hwss_add_dsc_calculate_and_set_config(seq_state, odm_pipe, true, opp_cnt);</div><div class='add'>+</div><div class='add'>+			/* Enable ODM DSC block */</div><div class='add'>+			hwss_add_dsc_enable_with_opp(seq_state, odm_pipe);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Step 5: Configure DSC in timing generator */</div><div class='add'>+		hwss_add_tg_set_dsc_config(seq_state, otg_master-&gt;stream_res.tg,</div><div class='add'>+			&amp;seq_state-&gt;steps[last_dsc_calc].params.dsc_calculate_and_set_config_params.dsc_optc_cfg, true);</div><div class='add'>+	} else if (otg_master-&gt;stream_res.dsc &amp;&amp; !otg_master-&gt;stream-&gt;timing.flags.DSC) {</div><div class='add'>+		/* Disable DSC in OPTC */</div><div class='add'>+		hwss_add_tg_set_dsc_config(seq_state, otg_master-&gt;stream_res.tg, NULL, false);</div><div class='add'>+</div><div class='add'>+		hwss_add_dsc_disconnect(seq_state, otg_master-&gt;stream_res.dsc);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Disable DSC for old pipes that no longer need it */</div><div class='add'>+	if (old_otg_master &amp;&amp; old_otg_master-&gt;stream_res.dsc) {</div><div class='add'>+		for (i = 0; i &lt; old_opp_head_count; i++) {</div><div class='add'>+			old_pipe = old_opp_heads[i];</div><div class='add'>+			new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[old_pipe-&gt;pipe_idx];</div><div class='add'>+</div><div class='add'>+			/* If old pipe had DSC but new pipe doesn't, disable the old DSC */</div><div class='add'>+			if (old_pipe-&gt;stream_res.dsc &amp;&amp; !new_pipe-&gt;stream_res.dsc) {</div><div class='add'>+				/* Then disconnect DSC block */</div><div class='add'>+				hwss_add_dsc_disconnect(seq_state, old_pipe-&gt;stream_res.dsc);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='add'>+	int opp_inst[MAX_PIPES] = {0};</div><div class='add'>+	int opp_head_count;</div><div class='add'>+	int odm_slice_width = resource_get_odm_slice_dst_width(otg_master, false);</div><div class='add'>+	int last_odm_slice_width = resource_get_odm_slice_dst_width(otg_master, true);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	opp_head_count = resource_get_opp_heads_for_otg_master(</div><div class='add'>+			otg_master, &amp;context-&gt;res_ctx, opp_heads);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; opp_head_count; i++)</div><div class='add'>+		opp_inst[i] = opp_heads[i]-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+</div><div class='add'>+	/* Add ODM combine/bypass operation to sequence */</div><div class='add'>+	if (opp_head_count &gt; 1) {</div><div class='add'>+		hwss_add_optc_set_odm_combine(seq_state, otg_master-&gt;stream_res.tg, opp_inst,</div><div class='add'>+			opp_head_count, odm_slice_width, last_odm_slice_width);</div><div class='add'>+	} else {</div><div class='add'>+		hwss_add_optc_set_odm_bypass(seq_state, otg_master-&gt;stream_res.tg, &amp;otg_master-&gt;stream-&gt;timing);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Add OPP operations to sequence */</div><div class='add'>+	for (i = 0; i &lt; opp_head_count; i++) {</div><div class='add'>+		/* Add OPP pipe clock control operation */</div><div class='add'>+		hwss_add_opp_pipe_clock_control(seq_state, opp_heads[i]-&gt;stream_res.opp, true);</div><div class='add'>+</div><div class='add'>+		/* Add OPP program left edge extra pixel operation */</div><div class='add'>+		hwss_add_opp_program_left_edge_extra_pixel(seq_state, opp_heads[i]-&gt;stream_res.opp,</div><div class='add'>+			opp_heads[i]-&gt;stream-&gt;timing.pixel_encoding, resource_is_pipe_type(opp_heads[i], OTG_MASTER));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Add DSC update operations to sequence */</div><div class='add'>+	dcn401_add_dsc_sequence_for_odm_change(dc, context, otg_master, seq_state);</div><div class='add'>+</div><div class='add'>+	/* Add blank pixel data operation if needed */</div><div class='add'>+	if (!resource_is_pipe_type(otg_master, DPP_PIPE)) {</div><div class='add'>+		if (dc-&gt;hwseq-&gt;funcs.blank_pixel_data_sequence)</div><div class='add'>+			dc-&gt;hwseq-&gt;funcs.blank_pixel_data_sequence(</div><div class='add'>+				dc, otg_master, true, seq_state);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_link_settings *link_settings)</div><div class='add'>+{</div><div class='add'>+	struct encoder_unblank_param params = {0};</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	struct dc_link *link = stream-&gt;link;</div><div class='add'>+	struct dce_hwseq *hws = link-&gt;dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	/* calculate parameters for unblank */</div><div class='add'>+	params.opp_cnt = resource_get_odm_slice_count(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	params.timing = pipe_ctx-&gt;stream-&gt;timing;</div><div class='add'>+	params.link_settings.link_rate = link_settings-&gt;link_rate;</div><div class='add'>+	params.pix_per_cycle = pipe_ctx-&gt;stream_res.pix_clk_params.dio_se_pix_per_cycle;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='add'>+		pipe_ctx-&gt;stream_res.hpo_dp_stream_enc-&gt;funcs-&gt;dp_unblank(</div><div class='add'>+				pipe_ctx-&gt;stream_res.hpo_dp_stream_enc,</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+	} else if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='add'>+		pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_unblank(link, pipe_ctx-&gt;stream_res.stream_enc, &amp;params);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (link-&gt;local_sink &amp;&amp; link-&gt;local_sink-&gt;sink_signal == SIGNAL_TYPE_EDP)</div><div class='add'>+		hws-&gt;funcs.edp_backlight_control(link, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_hardware_release(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	if (!dc-&gt;debug.disable_force_pstate_allow_on_hw_release) {</div><div class='add'>+		dc_dmub_srv_fams2_update_config(dc, dc-&gt;current_state, false);</div><div class='add'>+</div><div class='add'>+		/* If pstate unsupported, or still supported</div><div class='add'>+		* by firmware, force it supported by dcn</div><div class='add'>+		*/</div><div class='add'>+		if (dc-&gt;current_state) {</div><div class='add'>+			if ((!dc-&gt;clk_mgr-&gt;clks.p_state_change_support ||</div><div class='add'>+					dc-&gt;current_state-&gt;bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) &amp;&amp;</div><div class='add'>+					dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='add'>+						dc-&gt;res_pool-&gt;hubbub, true, true);</div><div class='add'>+</div><div class='add'>+			dc-&gt;current_state-&gt;bw_ctx.bw.dcn.clk.p_state_change_support = true;</div><div class='add'>+			dc-&gt;clk_mgr-&gt;funcs-&gt;update_clocks(dc-&gt;clk_mgr, dc-&gt;current_state, true);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (dc-&gt;current_state) {</div><div class='add'>+			dc-&gt;clk_mgr-&gt;clks.p_state_change_support = false;</div><div class='add'>+			dc-&gt;clk_mgr-&gt;funcs-&gt;update_clocks(dc-&gt;clk_mgr, dc-&gt;current_state, true);</div><div class='add'>+		}</div><div class='add'>+		dc_dmub_srv_fams2_update_config(dc, dc-&gt;current_state, false);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *opp_heads[MAX_PIPES];</div><div class='add'>+	struct pipe_ctx *dpp_pipes[MAX_PIPES];</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+	int dpp_count = 0;</div><div class='add'>+</div><div class='add'>+	if (!otg_master-&gt;stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	int slice_count = resource_get_opp_heads_for_otg_master(otg_master,</div><div class='add'>+			&amp;context-&gt;res_ctx, opp_heads);</div><div class='add'>+</div><div class='add'>+	for (int slice_idx = 0; slice_idx &lt; slice_count; slice_idx++) {</div><div class='add'>+		if (opp_heads[slice_idx]-&gt;plane_state) {</div><div class='add'>+			dpp_count = resource_get_dpp_pipes_for_opp_head(</div><div class='add'>+					opp_heads[slice_idx],</div><div class='add'>+					&amp;context-&gt;res_ctx,</div><div class='add'>+					dpp_pipes);</div><div class='add'>+			for (int dpp_idx = 0; dpp_idx &lt; dpp_count; dpp_idx++) {</div><div class='add'>+				struct pipe_ctx *dpp_pipe = dpp_pipes[dpp_idx];</div><div class='add'>+					if (dpp_pipe &amp;&amp; hubbub &amp;&amp;</div><div class='add'>+						dpp_pipe-&gt;plane_res.hubp &amp;&amp;</div><div class='add'>+						hubbub-&gt;funcs-&gt;wait_for_det_update)</div><div class='add'>+						hubbub-&gt;funcs-&gt;wait_for_det_update(hubbub, dpp_pipe-&gt;plane_res.hubp-&gt;inst);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			if (hubbub &amp;&amp; opp_heads[slice_idx]-&gt;plane_res.hubp &amp;&amp; hubbub-&gt;funcs-&gt;wait_for_det_update)</div><div class='add'>+				hubbub-&gt;funcs-&gt;wait_for_det_update(hubbub, opp_heads[slice_idx]-&gt;plane_res.hubp-&gt;inst);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_interdependent_update_lock(struct dc *dc,</div><div class='add'>+		struct dc_state *context, bool lock)</div><div class='add'>+{</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+	struct timing_generator *tg = NULL;</div><div class='add'>+</div><div class='add'>+	if (lock) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			tg = pipe-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+			if (!resource_is_pipe_type(pipe, OTG_MASTER) ||</div><div class='add'>+					!tg-&gt;funcs-&gt;is_tg_enabled(tg) ||</div><div class='add'>+					dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)</div><div class='add'>+				continue;</div><div class='add'>+			dc-&gt;hwss.pipe_control_lock(dc, pipe, true);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* Need to free DET being used first and have pipe update, then unlock the remaining pipes*/</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			tg = pipe-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+			if (!resource_is_pipe_type(pipe, OTG_MASTER) ||</div><div class='add'>+					!tg-&gt;funcs-&gt;is_tg_enabled(tg) ||</div><div class='add'>+					dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;scratch.pipes_to_unlock_first[i]) {</div><div class='add'>+				struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+				dc-&gt;hwss.pipe_control_lock(dc, pipe, false);</div><div class='add'>+				/* Assumes pipe of the same index in current_state is also an OTG_MASTER pipe*/</div><div class='add'>+				dcn401_wait_for_det_buffer_update_under_otg_master(dc, dc-&gt;current_state, old_pipe);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Unlocking the rest of the pipes */</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			if (dc-&gt;scratch.pipes_to_unlock_first[i])</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			tg = pipe-&gt;stream_res.tg;</div><div class='add'>+			if (!resource_is_pipe_type(pipe, OTG_MASTER) ||</div><div class='add'>+					!tg-&gt;funcs-&gt;is_tg_enabled(tg) ||</div><div class='add'>+					dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			dc-&gt;hwss.pipe_control_lock(dc, pipe, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	/* If 3DLUT FL is enabled and 3DLUT is in use, follow the workaround sequence for pipe unlock to make sure that</div><div class='add'>+	 * HUBP will properly fetch 3DLUT contents after unlock.</div><div class='add'>+	 *</div><div class='add'>+	 * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless</div><div class='add'>+	 * of whether OTG lock is currently being held or not.</div><div class='add'>+	 */</div><div class='add'>+	struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };</div><div class='add'>+	struct pipe_ctx *odm_pipe, *mpc_pipe;</div><div class='add'>+	int i, wa_pipe_ct = 0;</div><div class='add'>+</div><div class='add'>+	for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+		for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe-&gt;bottom_pipe) {</div><div class='add'>+			if (mpc_pipe-&gt;plane_state &amp;&amp; mpc_pipe-&gt;plane_state-&gt;mcm_luts.lut3d_data.lut3d_src</div><div class='add'>+						== DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM</div><div class='add'>+					&amp;&amp; mpc_pipe-&gt;plane_state-&gt;mcm_shaper_3dlut_setting</div><div class='add'>+						== DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT) {</div><div class='add'>+				wa_pipes[wa_pipe_ct++] = mpc_pipe;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (wa_pipe_ct &gt; 0) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vupdate_keepout)</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vupdate_keepout(pipe_ctx-&gt;stream_res.tg, true);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; wa_pipe_ct; ++i) {</div><div class='add'>+			if (wa_pipes[i]-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl)</div><div class='add'>+				wa_pipes[i]-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl(wa_pipes[i]-&gt;plane_res.hubp, true);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;unlock(pipe_ctx-&gt;stream_res.tg);</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_update_lock_status)</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_update_lock_status(pipe_ctx-&gt;stream_res.tg, false);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; wa_pipe_ct; ++i) {</div><div class='add'>+			if (wa_pipes[i]-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl)</div><div class='add'>+				wa_pipes[i]-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_enable_3dlut_fl(wa_pipes[i]-&gt;plane_res.hubp, true);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vupdate_keepout)</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vupdate_keepout(pipe_ctx-&gt;stream_res.tg, false);</div><div class='add'>+	} else {</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;unlock(pipe_ctx-&gt;stream_res.tg);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_program_outstanding_updates(struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+</div><div class='add'>+	/* update compbuf if required */</div><div class='add'>+	if (hubbub-&gt;funcs-&gt;program_compbuf_segments)</div><div class='add'>+		hubbub-&gt;funcs-&gt;program_compbuf_segments(hubbub, context-&gt;bw_ctx.bw.dcn.arb_regs.compbuf_size, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_reset_back_end_for_pipe(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+	const struct link_hwss *link_hwss = get_link_hwss(link, &amp;pipe_ctx-&gt;link_res);</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+	if (pipe_ctx-&gt;stream_res.stream_enc == NULL) {</div><div class='add'>+		pipe_ctx-&gt;stream = NULL;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DPMS may already disable or */</div><div class='add'>+	/* dpms_off status is incorrect due to fastboot</div><div class='add'>+	 * feature. When system resume from S4 with second</div><div class='add'>+	 * screen only, the dpms_off would be true but</div><div class='add'>+	 * VBIOS lit up eDP, so check link status too.</div><div class='add'>+	 */</div><div class='add'>+	if (!pipe_ctx-&gt;stream-&gt;dpms_off || link-&gt;link_status.link_active)</div><div class='add'>+		dc-&gt;link_srv-&gt;set_dpms_off(pipe_ctx);</div><div class='add'>+	else if (pipe_ctx-&gt;stream_res.audio)</div><div class='add'>+		dc-&gt;hwss.disable_audio_stream(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	/* free acquired resources */</div><div class='add'>+	if (pipe_ctx-&gt;stream_res.audio) {</div><div class='add'>+		/*disable az_endpoint*/</div><div class='add'>+		pipe_ctx-&gt;stream_res.audio-&gt;funcs-&gt;az_disable(pipe_ctx-&gt;stream_res.audio);</div><div class='add'>+</div><div class='add'>+		/*free audio*/</div><div class='add'>+		if (dc-&gt;caps.dynamic_audio == true) {</div><div class='add'>+			/*we have to dynamic arbitrate the audio endpoints*/</div><div class='add'>+			/*we free the resource, need reset is_audio_acquired*/</div><div class='add'>+			update_audio_usage(&amp;dc-&gt;current_state-&gt;res_ctx, dc-&gt;res_pool,</div><div class='add'>+					pipe_ctx-&gt;stream_res.audio, false);</div><div class='add'>+			pipe_ctx-&gt;stream_res.audio = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* by upper caller loop, parent pipe: pipe0, will be reset last.</div><div class='add'>+	 * back end share by all pipes and will be disable only when disable</div><div class='add'>+	 * parent pipe.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;top_pipe == NULL) {</div><div class='add'>+</div><div class='add'>+		dc-&gt;hwss.set_abm_immediate_disable(pipe_ctx);</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe_ctx-&gt;stream_res.tg);</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;enable_optc_clock(pipe_ctx-&gt;stream_res.tg, false);</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass)</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='add'>+					pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+</div><div class='add'>+		set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx-&gt;stream, NULL);</div><div class='add'>+</div><div class='add'>+		/* TODO - convert symclk_ref_cnts for otg to a bit map to solve</div><div class='add'>+		 * the case where the same symclk is shared across multiple otg</div><div class='add'>+		 * instances</div><div class='add'>+		 */</div><div class='add'>+		if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+			link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='add'>+		if (link-&gt;phy_state.symclk_state == SYMCLK_ON_TX_OFF) {</div><div class='add'>+			link_hwss-&gt;disable_link_output(link,</div><div class='add'>+					&amp;pipe_ctx-&gt;link_res, pipe_ctx-&gt;stream-&gt;signal);</div><div class='add'>+			link-&gt;phy_state.symclk_state = SYMCLK_OFF_TX_OFF;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* reset DTBCLK_P */</div><div class='add'>+		if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dtbclk_p_src)</div><div class='add'>+			dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_dtbclk_p_src(dc-&gt;res_pool-&gt;dccg, REFCLK, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * In case of a dangling plane, setting this to NULL unconditionally</div><div class='add'>+ * causes failures during reset hw ctx where, if stream is NULL,</div><div class='add'>+ * it is expected that the pipe_ctx pointers to pipes and plane are NULL.</div><div class='add'>+ */</div><div class='add'>+	pipe_ctx-&gt;stream = NULL;</div><div class='add'>+	pipe_ctx-&gt;top_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;bottom_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;next_odm_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;prev_odm_pipe = NULL;</div><div class='add'>+	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",</div><div class='add'>+					pipe_ctx-&gt;pipe_idx, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_reset_hw_ctx_wrap(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	/* Reset Back End*/</div><div class='add'>+	for (i = dc-&gt;res_pool-&gt;pipe_count - 1; i &gt;= 0 ; i--) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx_old =</div><div class='add'>+			&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx_old-&gt;stream)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx_old-&gt;top_pipe || pipe_ctx_old-&gt;prev_odm_pipe)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!pipe_ctx-&gt;stream ||</div><div class='add'>+				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {</div><div class='add'>+			struct clock_source *old_clk = pipe_ctx_old-&gt;clock_source;</div><div class='add'>+</div><div class='add'>+			if (hws-&gt;funcs.reset_back_end_for_pipe)</div><div class='add'>+				hws-&gt;funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc-&gt;current_state);</div><div class='add'>+			if (hws-&gt;funcs.enable_stream_gating)</div><div class='add'>+				hws-&gt;funcs.enable_stream_gating(dc, pipe_ctx_old);</div><div class='add'>+			if (old_clk)</div><div class='add'>+				old_clk-&gt;funcs-&gt;cs_power_down(old_clk);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dcn401_calculate_vready_offset_for_group(struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	struct pipe_ctx *other_pipe;</div><div class='add'>+	unsigned int vready_offset = pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+</div><div class='add'>+	/* Always use the largest vready_offset of all connected pipes */</div><div class='add'>+	for (other_pipe = pipe-&gt;bottom_pipe; other_pipe != NULL; other_pipe = other_pipe-&gt;bottom_pipe) {</div><div class='add'>+		if (other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels &gt; vready_offset)</div><div class='add'>+			vready_offset = other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+	}</div><div class='add'>+	for (other_pipe = pipe-&gt;top_pipe; other_pipe != NULL; other_pipe = other_pipe-&gt;top_pipe) {</div><div class='add'>+		if (other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels &gt; vready_offset)</div><div class='add'>+			vready_offset = other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+	}</div><div class='add'>+	for (other_pipe = pipe-&gt;next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe-&gt;next_odm_pipe) {</div><div class='add'>+		if (other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels &gt; vready_offset)</div><div class='add'>+			vready_offset = other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+	}</div><div class='add'>+	for (other_pipe = pipe-&gt;prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe-&gt;prev_odm_pipe) {</div><div class='add'>+		if (other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels &gt; vready_offset)</div><div class='add'>+			vready_offset = other_pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return vready_offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_program_tg(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct dce_hwseq *hws)</div><div class='add'>+{</div><div class='add'>+	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_global_sync(</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg,</div><div class='add'>+		dcn401_calculate_vready_offset_for_group(pipe_ctx),</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vstartup_lines,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_offset_pixels,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_vupdate_width_pixels,</div><div class='add'>+		(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.pstate_keepout_start_lines);</div><div class='add'>+</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='add'>+		pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, true);</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.setup_vupdate_interrupt)</div><div class='add'>+		hws-&gt;funcs.setup_vupdate_interrupt(dc, pipe_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_program_pipe(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	/* Only need to unblank on top pipe */</div><div class='add'>+	if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {</div><div class='add'>+		if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.odm ||</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;update_flags.bits.abm_level)</div><div class='add'>+			hws-&gt;funcs.blank_pixel_data(dc, pipe_ctx,</div><div class='add'>+				!pipe_ctx-&gt;plane_state ||</div><div class='add'>+				!pipe_ctx-&gt;plane_state-&gt;visible);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Only update TG on top pipe */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.global_sync &amp;&amp; !pipe_ctx-&gt;top_pipe</div><div class='add'>+		&amp;&amp; !pipe_ctx-&gt;prev_odm_pipe)</div><div class='add'>+		dcn401_program_tg(dc, pipe_ctx, context, hws);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.odm)</div><div class='add'>+		hws-&gt;funcs.update_odm(dc, context, pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable) {</div><div class='add'>+		if (hws-&gt;funcs.enable_plane)</div><div class='add'>+			hws-&gt;funcs.enable_plane(dc, pipe_ctx, context);</div><div class='add'>+		else</div><div class='add'>+			dc-&gt;hwss.enable_plane(dc, pipe_ctx, context);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_wm_propagate_to_pipes)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_wm_propagate_to_pipes(dc-&gt;res_pool-&gt;hubbub);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.det_size) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;det_buffer_size_kb);</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;hubp_regs.det_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; (pipe_ctx-&gt;update_flags.raw ||</div><div class='add'>+	    pipe_ctx-&gt;plane_state-&gt;update_flags.raw ||</div><div class='add'>+	    pipe_ctx-&gt;stream-&gt;update_flags.raw))</div><div class='add'>+		dc-&gt;hwss.update_dchubp_dpp(dc, pipe_ctx, context);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+		pipe_ctx-&gt;plane_state-&gt;update_flags.bits.hdr_mult))</div><div class='add'>+		hws-&gt;funcs.set_hdr_multiplier(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp;</div><div class='add'>+		(pipe_ctx-&gt;plane_state-&gt;update_flags.bits.in_transfer_func_change ||</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.gamma_change ||</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.lut_3d ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.enable))</div><div class='add'>+		hws-&gt;funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx-&gt;plane_state);</div><div class='add'>+</div><div class='add'>+	/* dcn10_translate_regamma_to_hw_format takes 750us to finish</div><div class='add'>+	 * only do gamma programming for powering on, internal memcmp to avoid</div><div class='add'>+	 * updating on slave planes</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+	    pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+	    pipe_ctx-&gt;stream-&gt;update_flags.bits.out_tf)</div><div class='add'>+		hws-&gt;funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx-&gt;stream);</div><div class='add'>+</div><div class='add'>+	/* If the pipe has been enabled or has a different opp, we</div><div class='add'>+	 * should reprogram the fmt. This deals with cases where</div><div class='add'>+	 * interation between mpc and odm combine on different streams</div><div class='add'>+	 * causes a different pipe to be chosen to odm combine with.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable</div><div class='add'>+		|| pipe_ctx-&gt;update_flags.bits.opp_changed) {</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_set_dyn_expansion(</div><div class='add'>+			pipe_ctx-&gt;stream_res.opp,</div><div class='add'>+			COLOR_SPACE_YCBCR601,</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;timing.display_color_depth,</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;signal);</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_program_fmt(</div><div class='add'>+			pipe_ctx-&gt;stream_res.opp,</div><div class='add'>+			&amp;pipe_ctx-&gt;stream-&gt;bit_depth_params,</div><div class='add'>+			&amp;pipe_ctx-&gt;stream-&gt;clamping);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set ABM pipe after other pipe configurations done */</div><div class='add'>+	if ((pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_state-&gt;visible)) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.abm) {</div><div class='add'>+			dc-&gt;hwss.set_pipe(pipe_ctx);</div><div class='add'>+			pipe_ctx-&gt;stream_res.abm-&gt;funcs-&gt;set_abm_level(pipe_ctx-&gt;stream_res.abm,</div><div class='add'>+				pipe_ctx-&gt;stream-&gt;abm_level);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.test_pattern_changed) {</div><div class='add'>+		struct output_pixel_processor *odm_opp = pipe_ctx-&gt;stream_res.opp;</div><div class='add'>+		struct bit_depth_reduction_params params;</div><div class='add'>+</div><div class='add'>+		memset(&amp;params, 0, sizeof(params));</div><div class='add'>+		odm_opp-&gt;funcs-&gt;opp_program_bit_depth_reduction(odm_opp, &amp;params);</div><div class='add'>+		dc-&gt;hwss.set_disp_pattern_generator(dc,</div><div class='add'>+			pipe_ctx,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.test_pattern,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.color_space,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.color_depth,</div><div class='add'>+			NULL,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.width,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.height,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.offset);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * dcn401_program_pipe_sequence - Sequence-based version of dcn401_program_pipe</div><div class='add'>+ *</div><div class='add'>+ * This function creates a sequence-based version of the original dcn401_program_pipe</div><div class='add'>+ * function. Instead of directly calling hardware programming functions, it appends</div><div class='add'>+ * sequence steps to the provided block_sequence array that can later be executed</div><div class='add'>+ * as part of hwss_execute_sequence.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void dcn401_program_pipe_sequence(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	/* Only need to unblank on top pipe */</div><div class='add'>+	if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) {</div><div class='add'>+		if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+				pipe_ctx-&gt;update_flags.bits.odm ||</div><div class='add'>+				pipe_ctx-&gt;stream-&gt;update_flags.bits.abm_level) {</div><div class='add'>+			if (dc-&gt;hwseq-&gt;funcs.blank_pixel_data_sequence)</div><div class='add'>+				dc-&gt;hwseq-&gt;funcs.blank_pixel_data_sequence(dc, pipe_ctx,</div><div class='add'>+					 !pipe_ctx-&gt;plane_state || !pipe_ctx-&gt;plane_state-&gt;visible,</div><div class='add'>+					 seq_state);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Only update TG on top pipe */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.global_sync &amp;&amp; !pipe_ctx-&gt;top_pipe</div><div class='add'>+		&amp;&amp; !pipe_ctx-&gt;prev_odm_pipe) {</div><div class='add'>+</div><div class='add'>+		/* Step 1: Program global sync */</div><div class='add'>+		hwss_add_tg_program_global_sync(seq_state, pipe_ctx-&gt;stream_res.tg,</div><div class='add'>+			dcn401_calculate_vready_offset_for_group(pipe_ctx),</div><div class='add'>+			(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vstartup_lines,</div><div class='add'>+			(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_offset_pixels,</div><div class='add'>+			(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_vupdate_width_pixels,</div><div class='add'>+			(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.pstate_keepout_start_lines);</div><div class='add'>+</div><div class='add'>+		/* Step 2: Wait for VACTIVE state (if not phantom pipe) */</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)</div><div class='add'>+			hwss_add_tg_wait_for_state(seq_state, pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='add'>+</div><div class='add'>+		/* Step 3: Set VTG params */</div><div class='add'>+		hwss_add_tg_set_vtg_params(seq_state, pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, true);</div><div class='add'>+</div><div class='add'>+		/* Step 4: Setup vupdate interrupt (if available) */</div><div class='add'>+		if (hws-&gt;funcs.setup_vupdate_interrupt)</div><div class='add'>+			dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.odm) {</div><div class='add'>+		if (hws-&gt;funcs.update_odm_sequence)</div><div class='add'>+			hws-&gt;funcs.update_odm_sequence(dc, context, pipe_ctx, seq_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable) {</div><div class='add'>+		if (dc-&gt;hwss.enable_plane_sequence)</div><div class='add'>+			dc-&gt;hwss.enable_plane_sequence(dc, pipe_ctx, context, seq_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.det_size) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_size) {</div><div class='add'>+			hwss_add_hubp_program_det_size(seq_state, dc-&gt;res_pool-&gt;hubbub,</div><div class='add'>+				pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;det_buffer_size_kb);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments) {</div><div class='add'>+			hwss_add_hubp_program_det_segments(seq_state, dc-&gt;res_pool-&gt;hubbub,</div><div class='add'>+				pipe_ctx-&gt;plane_res.hubp-&gt;inst, pipe_ctx-&gt;hubp_regs.det_size);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; (pipe_ctx-&gt;update_flags.raw ||</div><div class='add'>+	    pipe_ctx-&gt;plane_state-&gt;update_flags.raw ||</div><div class='add'>+	    pipe_ctx-&gt;stream-&gt;update_flags.raw)) {</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;hwss.update_dchubp_dpp_sequence)</div><div class='add'>+			dc-&gt;hwss.update_dchubp_dpp_sequence(dc, pipe_ctx, context, seq_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp; (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+		pipe_ctx-&gt;plane_state-&gt;update_flags.bits.hdr_mult)) {</div><div class='add'>+</div><div class='add'>+		hws-&gt;funcs.set_hdr_multiplier_sequence(pipe_ctx, seq_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state &amp;&amp;</div><div class='add'>+		(pipe_ctx-&gt;plane_state-&gt;update_flags.bits.in_transfer_func_change ||</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.gamma_change ||</div><div class='add'>+			pipe_ctx-&gt;plane_state-&gt;update_flags.bits.lut_3d ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.enable)) {</div><div class='add'>+</div><div class='add'>+		hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx-&gt;plane_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* dcn10_translate_regamma_to_hw_format takes 750us to finish</div><div class='add'>+	 * only do gamma programming for powering on, internal memcmp to avoid</div><div class='add'>+	 * updating on slave planes</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;update_flags.bits.out_tf) {</div><div class='add'>+		hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx-&gt;stream);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If the pipe has been enabled or has a different opp, we</div><div class='add'>+	 * should reprogram the fmt. This deals with cases where</div><div class='add'>+	 * interation between mpc and odm combine on different streams</div><div class='add'>+	 * causes a different pipe to be chosen to odm combine with.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable</div><div class='add'>+		|| pipe_ctx-&gt;update_flags.bits.opp_changed) {</div><div class='add'>+</div><div class='add'>+		hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx-&gt;stream_res.opp, COLOR_SPACE_YCBCR601,</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;timing.display_color_depth, pipe_ctx-&gt;stream-&gt;signal);</div><div class='add'>+</div><div class='add'>+		hwss_add_opp_program_fmt(seq_state, pipe_ctx-&gt;stream_res.opp,</div><div class='add'>+			&amp;pipe_ctx-&gt;stream-&gt;bit_depth_params, &amp;pipe_ctx-&gt;stream-&gt;clamping);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set ABM pipe after other pipe configurations done */</div><div class='add'>+	if ((pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_state-&gt;visible)) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.abm) {</div><div class='add'>+			hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);</div><div class='add'>+</div><div class='add'>+			hwss_add_abm_set_level(seq_state, pipe_ctx-&gt;stream_res.abm, pipe_ctx-&gt;stream-&gt;abm_level);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.test_pattern_changed) {</div><div class='add'>+		struct output_pixel_processor *odm_opp = pipe_ctx-&gt;stream_res.opp;</div><div class='add'>+</div><div class='add'>+		hwss_add_opp_program_bit_depth_reduction(seq_state, odm_opp, true, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		hwss_add_opp_set_disp_pattern_generator(seq_state,</div><div class='add'>+			odm_opp,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.test_pattern,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.color_space,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.color_depth,</div><div class='add'>+			(struct tg_color){0},</div><div class='add'>+			false,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.width,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.height,</div><div class='add'>+			pipe_ctx-&gt;stream_res.test_pattern_params.offset);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_program_front_end_for_ctx(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	unsigned int prev_hubp_count = 0;</div><div class='add'>+	unsigned int hubp_count = 0;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (resource_is_pipe_topology_changed(dc-&gt;current_state, context))</div><div class='add'>+		resource_log_pipe_topology_update(dc, context);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;hwss.program_triplebuffer != NULL &amp;&amp; dc-&gt;debug.enable_tri_buf) {</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+			if (pipe-&gt;plane_state) {</div><div class='add'>+				if (pipe-&gt;plane_state-&gt;triplebuffer_flips)</div><div class='add'>+					BREAK_TO_DEBUGGER();</div><div class='add'>+</div><div class='add'>+				/*turn off triple buffer for full update*/</div><div class='add'>+				dc-&gt;hwss.program_triplebuffer(</div><div class='add'>+					dc, pipe, pipe-&gt;plane_state-&gt;triplebuffer_flips);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='add'>+			prev_hubp_count++;</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='add'>+			hubp_count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (prev_hubp_count == 0 &amp;&amp; hubp_count &gt; 0) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, true, false);</div><div class='add'>+		udelay(500);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set pipe update flags and lock pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		dc-&gt;hwss.detect_pipe_changes(dc-&gt;current_state, context, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i],</div><div class='add'>+			&amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+</div><div class='add'>+	/* When disabling phantom pipes, turn on phantom OTG first (so we can get double</div><div class='add'>+	 * buffer updates properly)</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct dc_stream_state *stream = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream;</div><div class='add'>+</div><div class='add'>+		pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable &amp;&amp; stream &amp;&amp;</div><div class='add'>+			dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+			struct timing_generator *tg = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream_res.tg;</div><div class='add'>+</div><div class='add'>+			if (tg-&gt;funcs-&gt;enable_crtc) {</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.blank_pixel_data)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.blank_pixel_data(dc, pipe, true);</div><div class='add'>+</div><div class='add'>+				tg-&gt;funcs-&gt;enable_crtc(tg);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/* OTG blank before disabling all front ends */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable</div><div class='add'>+			&amp;&amp; !context-&gt;res_ctx.pipe_ctx[i].top_pipe</div><div class='add'>+			&amp;&amp; !context-&gt;res_ctx.pipe_ctx[i].prev_odm_pipe</div><div class='add'>+			&amp;&amp; context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='add'>+			hws-&gt;funcs.blank_pixel_data(dc, &amp;context-&gt;res_ctx.pipe_ctx[i], true);</div><div class='add'>+</div><div class='add'>+	/* Disconnect mpcc */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable</div><div class='add'>+			|| context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {</div><div class='add'>+			struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+</div><div class='add'>+			/* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom</div><div class='add'>+			 * then we want to do the programming here (effectively it's being disabled). If we do</div><div class='add'>+			 * the programming later the DET won't be updated until the OTG for the phantom pipe is</div><div class='add'>+			 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with</div><div class='add'>+			 * DET allocation.</div><div class='add'>+			 */</div><div class='add'>+			if ((context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable ||</div><div class='add'>+				(context-&gt;res_ctx.pipe_ctx[i].plane_state &amp;&amp;</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i]) ==</div><div class='add'>+				SUBVP_PHANTOM))) {</div><div class='add'>+				if (hubbub-&gt;funcs-&gt;program_det_size)</div><div class='add'>+					hubbub-&gt;funcs-&gt;program_det_size(hubbub,</div><div class='add'>+						dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;inst, 0);</div><div class='add'>+				if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments)</div><div class='add'>+					dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;program_det_segments(</div><div class='add'>+						hubbub,	dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;inst, 0);</div><div class='add'>+			}</div><div class='add'>+			hws-&gt;funcs.plane_atomic_disconnect(dc, dc-&gt;current_state,</div><div class='add'>+				&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+			DC_LOG_DC("Reset mpcc for pipe %d\n", dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].pipe_idx);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	/* update ODM for blanked OTG master pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='add'>+			!resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='add'>+			pipe-&gt;update_flags.bits.odm &amp;&amp;</div><div class='add'>+			hws-&gt;funcs.update_odm)</div><div class='add'>+			hws-&gt;funcs.update_odm(dc, context, pipe);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Program all updated pipes, order matters for mpcc setup. Start with</div><div class='add'>+	 * top pipe and program all pipes that follow in order</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe) {</div><div class='add'>+			while (pipe) {</div><div class='add'>+				if (hws-&gt;funcs.program_pipe)</div><div class='add'>+					hws-&gt;funcs.program_pipe(dc, pipe, context);</div><div class='add'>+				else {</div><div class='add'>+					/* Don't program phantom pipes in the regular front end programming sequence.</div><div class='add'>+					 * There is an MPO transition case where a pipe being used by a video plane is</div><div class='add'>+					 * transitioned directly to be a phantom pipe when closing the MPO video.</div><div class='add'>+					 * However the phantom pipe will program a new HUBP_VTG_SEL (update takes place</div><div class='add'>+					 * right away) but the MPO still exists until the double buffered update of the</div><div class='add'>+					 * main pipe so we will get a frame of underflow if the phantom pipe is</div><div class='add'>+					 * programmed here.</div><div class='add'>+					 */</div><div class='add'>+					if (pipe-&gt;stream &amp;&amp;</div><div class='add'>+						dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)</div><div class='add'>+						dcn401_program_pipe(dc, pipe, context);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				pipe = pipe-&gt;bottom_pipe;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Program secondary blending tree and writeback pipes */</div><div class='add'>+		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		if (!pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe</div><div class='add'>+			&amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;num_wb_info &gt; 0</div><div class='add'>+			&amp;&amp; (pipe-&gt;update_flags.raw || (pipe-&gt;plane_state &amp;&amp; pipe-&gt;plane_state-&gt;update_flags.raw)</div><div class='add'>+				|| pipe-&gt;stream-&gt;update_flags.raw)</div><div class='add'>+			&amp;&amp; hws-&gt;funcs.program_all_writeback_pipes_in_tree)</div><div class='add'>+			hws-&gt;funcs.program_all_writeback_pipes_in_tree(dc, pipe-&gt;stream, context);</div><div class='add'>+</div><div class='add'>+		/* Avoid underflow by check of pipe line read when adding 2nd plane. */</div><div class='add'>+		if (hws-&gt;wa.wait_hubpret_read_start_during_mpo_transition &amp;&amp;</div><div class='add'>+				!pipe-&gt;top_pipe &amp;&amp;</div><div class='add'>+				pipe-&gt;stream &amp;&amp;</div><div class='add'>+				pipe-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_wait_pipe_read_start &amp;&amp;</div><div class='add'>+				dc-&gt;current_state-&gt;stream_status[0].plane_count == 1 &amp;&amp;</div><div class='add'>+				context-&gt;stream_status[0].plane_count &gt; 1) {</div><div class='add'>+			pipe-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_wait_pipe_read_start(pipe-&gt;plane_res.hubp);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_post_unlock_program_front_end(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	// Timeout for pipe enable</div><div class='add'>+	unsigned int timeout_us = 100000;</div><div class='add'>+	unsigned int polling_interval_us = 1;</div><div class='add'>+	struct dce_hwseq *hwseq = dc-&gt;hwseq;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		if (resource_is_pipe_type(&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i], OPP_HEAD) &amp;&amp;</div><div class='add'>+			!resource_is_pipe_type(&amp;context-&gt;res_ctx.pipe_ctx[i], OPP_HEAD))</div><div class='add'>+			dc-&gt;hwss.post_unlock_reset_opp(dc,</div><div class='add'>+				&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable)</div><div class='add'>+			dc-&gt;hwss.disable_plane(dc, dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we are enabling a pipe, we need to wait for pending clear as this is a critical</div><div class='add'>+	 * part of the enable operation otherwise, DM may request an immediate flip which</div><div class='add'>+	 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which</div><div class='add'>+	 * is unsupported on DCN.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		// Don't check flip pending on phantom pipes</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; pipe-&gt;update_flags.bits.enable &amp;&amp;</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {</div><div class='add'>+			struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+			int j = 0;</div><div class='add'>+</div><div class='add'>+			for (j = 0; j &lt; timeout_us / polling_interval_us</div><div class='add'>+				&amp;&amp; hubp-&gt;funcs-&gt;hubp_is_flip_pending(hubp); j++)</div><div class='add'>+				udelay(polling_interval_us);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		/* When going from a smaller ODM slice count to larger, we must ensure double</div><div class='add'>+		 * buffer update completes before we return to ensure we don't reduce DISPCLK</div><div class='add'>+		 * before we've transitioned to 2:1 or 4:1</div><div class='add'>+		 */</div><div class='add'>+		if (resource_is_pipe_type(old_pipe, OTG_MASTER) &amp;&amp; resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='add'>+			resource_get_odm_slice_count(old_pipe) &lt; resource_get_odm_slice_count(pipe) &amp;&amp;</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {</div><div class='add'>+			int j = 0;</div><div class='add'>+			struct timing_generator *tg = pipe-&gt;stream_res.tg;</div><div class='add'>+</div><div class='add'>+			if (tg-&gt;funcs-&gt;get_optc_double_buffer_pending) {</div><div class='add'>+				for (j = 0; j &lt; timeout_us / polling_interval_us</div><div class='add'>+					&amp;&amp; tg-&gt;funcs-&gt;get_optc_double_buffer_pending(tg); j++)</div><div class='add'>+					udelay(polling_interval_us);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub, false, false);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe) {</div><div class='add'>+			/* Program phantom pipe here to prevent a frame of underflow in the MPO transition</div><div class='add'>+			 * case (if a pipe being used for a video plane transitions to a phantom pipe, it</div><div class='add'>+			 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end</div><div class='add'>+			 * programming sequence).</div><div class='add'>+			 */</div><div class='add'>+			while (pipe) {</div><div class='add'>+				if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+					/* When turning on the phantom pipe we want to run through the</div><div class='add'>+					 * entire enable sequence, so apply all the "enable" flags.</div><div class='add'>+					 */</div><div class='add'>+					if (dc-&gt;hwss.apply_update_flags_for_phantom)</div><div class='add'>+						dc-&gt;hwss.apply_update_flags_for_phantom(pipe);</div><div class='add'>+					if (dc-&gt;hwss.update_phantom_vp_position)</div><div class='add'>+						dc-&gt;hwss.update_phantom_vp_position(dc, context, pipe);</div><div class='add'>+					dcn401_program_pipe(dc, pipe, context);</div><div class='add'>+				}</div><div class='add'>+				pipe = pipe-&gt;bottom_pipe;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!hwseq)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* P-State support transitions:</div><div class='add'>+	 * Natural -&gt; FPO:      P-State disabled in prepare, force disallow anytime is safe</div><div class='add'>+	 * FPO -&gt; Natural:      Unforce anytime after FW disable is safe (P-State will assert naturally)</div><div class='add'>+	 * Unsupported -&gt; FPO:  P-State enabled in optimize, force disallow anytime is safe</div><div class='add'>+	 * FPO -&gt; Unsupported:  P-State disabled in prepare, unforce disallow anytime is safe</div><div class='add'>+	 * FPO &lt;-&gt; SubVP:       Force disallow is maintained on the FPO / SubVP pipes</div><div class='add'>+	 */</div><div class='add'>+	if (hwseq-&gt;funcs.update_force_pstate)</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.update_force_pstate(dc, context);</div><div class='add'>+	/* Only program the MALL registers after all the main and phantom pipes</div><div class='add'>+	 * are done programming.</div><div class='add'>+	 */</div><div class='add'>+	if (hwseq-&gt;funcs.program_mall_pipe_config)</div><div class='add'>+		hwseq-&gt;funcs.program_mall_pipe_config(dc, context);</div><div class='add'>+</div><div class='add'>+	/* WA to apply WM setting*/</div><div class='add'>+	if (hwseq-&gt;wa.DEGVIDCN21)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;apply_DEDCN21_147_wa(dc-&gt;res_pool-&gt;hubbub);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/* WA for stutter underflow during MPO transitions when adding 2nd plane */</div><div class='add'>+	if (hwseq-&gt;wa.disallow_self_refresh_during_multi_plane_transition) {</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;current_state-&gt;stream_status[0].plane_count == 1 &amp;&amp;</div><div class='add'>+			context-&gt;stream_status[0].plane_count &gt; 1) {</div><div class='add'>+</div><div class='add'>+			struct timing_generator *tg = dc-&gt;res_pool-&gt;timing_generators[0];</div><div class='add'>+</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;allow_self_refresh_control(dc-&gt;res_pool-&gt;hubbub, false);</div><div class='add'>+</div><div class='add'>+			hwseq-&gt;wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;</div><div class='add'>+			hwseq-&gt;wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame =</div><div class='add'>+				tg-&gt;funcs-&gt;get_frame_count(tg);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_update_bandwidth(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	/* recalculate DML parameters */</div><div class='add'>+	if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* apply updated bandwidth parameters */</div><div class='add'>+	dc-&gt;hwss.prepare_bandwidth(dc, context);</div><div class='add'>+</div><div class='add'>+	/* update hubp configs for all pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;plane_state == NULL)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;top_pipe == NULL) {</div><div class='add'>+			bool blank = !is_pipe_tree_visible(pipe_ctx);</div><div class='add'>+</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;program_global_sync(</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg,</div><div class='add'>+				dcn401_calculate_vready_offset_for_group(pipe_ctx),</div><div class='add'>+				(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vstartup_lines,</div><div class='add'>+				(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_offset_pixels,</div><div class='add'>+				(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.vupdate_vupdate_width_pixels,</div><div class='add'>+				(unsigned int)pipe_ctx-&gt;global_sync.dcn4x.pstate_keepout_start_lines);</div><div class='add'>+</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing, false);</div><div class='add'>+</div><div class='add'>+			if (pipe_ctx-&gt;prev_odm_pipe == NULL)</div><div class='add'>+				hws-&gt;funcs.blank_pixel_data(dc, pipe_ctx, blank);</div><div class='add'>+</div><div class='add'>+			if (hws-&gt;funcs.setup_vupdate_interrupt)</div><div class='add'>+				hws-&gt;funcs.setup_vupdate_interrupt(dc, pipe_ctx);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_setup2)</div><div class='add'>+			pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_setup2(</div><div class='add'>+				pipe_ctx-&gt;plane_res.hubp,</div><div class='add'>+				&amp;pipe_ctx-&gt;hubp_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;global_sync,</div><div class='add'>+				&amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_detect_pipe_changes(struct dc_state *old_state,</div><div class='add'>+	struct dc_state *new_state,</div><div class='add'>+	struct pipe_ctx *old_pipe,</div><div class='add'>+	struct pipe_ctx *new_pipe)</div><div class='add'>+{</div><div class='add'>+	bool old_is_phantom = dc_state_get_pipe_subvp_type(old_state, old_pipe) == SUBVP_PHANTOM;</div><div class='add'>+	bool new_is_phantom = dc_state_get_pipe_subvp_type(new_state, new_pipe) == SUBVP_PHANTOM;</div><div class='add'>+</div><div class='add'>+	unsigned int old_pipe_vready_offset_pixels = old_pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+	unsigned int new_pipe_vready_offset_pixels = new_pipe-&gt;global_sync.dcn4x.vready_offset_pixels;</div><div class='add'>+	unsigned int old_pipe_vstartup_lines = old_pipe-&gt;global_sync.dcn4x.vstartup_lines;</div><div class='add'>+	unsigned int new_pipe_vstartup_lines = new_pipe-&gt;global_sync.dcn4x.vstartup_lines;</div><div class='add'>+	unsigned int old_pipe_vupdate_offset_pixels = old_pipe-&gt;global_sync.dcn4x.vupdate_offset_pixels;</div><div class='add'>+	unsigned int new_pipe_vupdate_offset_pixels = new_pipe-&gt;global_sync.dcn4x.vupdate_offset_pixels;</div><div class='add'>+	unsigned int old_pipe_vupdate_width_pixels = old_pipe-&gt;global_sync.dcn4x.vupdate_vupdate_width_pixels;</div><div class='add'>+	unsigned int new_pipe_vupdate_width_pixels = new_pipe-&gt;global_sync.dcn4x.vupdate_vupdate_width_pixels;</div><div class='add'>+</div><div class='add'>+	new_pipe-&gt;update_flags.raw = 0;</div><div class='add'>+</div><div class='add'>+	/* If non-phantom pipe is being transitioned to a phantom pipe,</div><div class='add'>+	 * set disable and return immediately. This is because the pipe</div><div class='add'>+	 * that was previously in use must be fully disabled before we</div><div class='add'>+	 * can "enable" it as a phantom pipe (since the OTG will certainly</div><div class='add'>+	 * be different). The post_unlock sequence will set the correct</div><div class='add'>+	 * update flags to enable the phantom pipe.</div><div class='add'>+	 */</div><div class='add'>+	if (old_pipe-&gt;plane_state &amp;&amp; !old_is_phantom &amp;&amp;</div><div class='add'>+		new_pipe-&gt;plane_state &amp;&amp; new_is_phantom) {</div><div class='add'>+		new_pipe-&gt;update_flags.bits.disable = 1;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (resource_is_pipe_type(new_pipe, OTG_MASTER) &amp;&amp;</div><div class='add'>+		resource_is_odm_topology_changed(new_pipe, old_pipe))</div><div class='add'>+		/* Detect odm changes */</div><div class='add'>+		new_pipe-&gt;update_flags.bits.odm = 1;</div><div class='add'>+</div><div class='add'>+	/* Exit on unchanged, unused pipe */</div><div class='add'>+	if (!old_pipe-&gt;plane_state &amp;&amp; !new_pipe-&gt;plane_state)</div><div class='add'>+		return;</div><div class='add'>+	/* Detect pipe enable/disable */</div><div class='add'>+	if (!old_pipe-&gt;plane_state &amp;&amp; new_pipe-&gt;plane_state) {</div><div class='add'>+		new_pipe-&gt;update_flags.bits.enable = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.mpcc = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.dppclk = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.hubp_interdependent = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.hubp_rq_dlg_ttu = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.unbounded_req = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.gamut_remap = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.scaler = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.viewport = 1;</div><div class='add'>+		new_pipe-&gt;update_flags.bits.det_size = 1;</div><div class='add'>+		if (new_pipe-&gt;stream-&gt;test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE &amp;&amp;</div><div class='add'>+			new_pipe-&gt;stream_res.test_pattern_params.width != 0 &amp;&amp;</div><div class='add'>+			new_pipe-&gt;stream_res.test_pattern_params.height != 0)</div><div class='add'>+			new_pipe-&gt;update_flags.bits.test_pattern_changed = 1;</div><div class='add'>+		if (!new_pipe-&gt;top_pipe &amp;&amp; !new_pipe-&gt;prev_odm_pipe) {</div><div class='add'>+			new_pipe-&gt;update_flags.bits.odm = 1;</div><div class='add'>+			new_pipe-&gt;update_flags.bits.global_sync = 1;</div><div class='add'>+		}</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* For SubVP we need to unconditionally enable because any phantom pipes are</div><div class='add'>+	 * always removed then newly added for every full updates whenever SubVP is in use.</div><div class='add'>+	 * The remove-add sequence of the phantom pipe always results in the pipe</div><div class='add'>+	 * being blanked in enable_stream_timing (DPG).</div><div class='add'>+	 */</div><div class='add'>+	if (new_pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(new_state, new_pipe) == SUBVP_PHANTOM)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.enable = 1;</div><div class='add'>+</div><div class='add'>+	/* Phantom pipes are effectively disabled, if the pipe was previously phantom</div><div class='add'>+	 * we have to enable</div><div class='add'>+	 */</div><div class='add'>+	if (old_pipe-&gt;plane_state &amp;&amp; old_is_phantom &amp;&amp;</div><div class='add'>+		new_pipe-&gt;plane_state &amp;&amp; !new_is_phantom)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.enable = 1;</div><div class='add'>+</div><div class='add'>+	if (old_pipe-&gt;plane_state &amp;&amp; !new_pipe-&gt;plane_state) {</div><div class='add'>+		new_pipe-&gt;update_flags.bits.disable = 1;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Detect plane change */</div><div class='add'>+	if (old_pipe-&gt;plane_state != new_pipe-&gt;plane_state)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.plane_changed = true;</div><div class='add'>+</div><div class='add'>+	/* Detect top pipe only changes */</div><div class='add'>+	if (resource_is_pipe_type(new_pipe, OTG_MASTER)) {</div><div class='add'>+		/* Detect global sync changes */</div><div class='add'>+		if ((old_pipe_vready_offset_pixels != new_pipe_vready_offset_pixels)</div><div class='add'>+			|| (old_pipe_vstartup_lines != new_pipe_vstartup_lines)</div><div class='add'>+			|| (old_pipe_vupdate_offset_pixels != new_pipe_vupdate_offset_pixels)</div><div class='add'>+			|| (old_pipe_vupdate_width_pixels != new_pipe_vupdate_width_pixels))</div><div class='add'>+			new_pipe-&gt;update_flags.bits.global_sync = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (old_pipe-&gt;det_buffer_size_kb != new_pipe-&gt;det_buffer_size_kb)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.det_size = 1;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Detect opp / tg change, only set on change, not on enable</div><div class='add'>+	 * Assume mpcc inst = pipe index, if not this code needs to be updated</div><div class='add'>+	 * since mpcc is what is affected by these. In fact all of our sequence</div><div class='add'>+	 * makes this assumption at the moment with how hubp reset is matched to</div><div class='add'>+	 * same index mpcc reset.</div><div class='add'>+	 */</div><div class='add'>+	if (old_pipe-&gt;stream_res.opp != new_pipe-&gt;stream_res.opp)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.opp_changed = 1;</div><div class='add'>+	if (old_pipe-&gt;stream_res.tg != new_pipe-&gt;stream_res.tg)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.tg_changed = 1;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Detect mpcc blending changes, only dpp inst and opp matter here,</div><div class='add'>+	 * mpccs getting removed/inserted update connected ones during their own</div><div class='add'>+	 * programming</div><div class='add'>+	 */</div><div class='add'>+	if (old_pipe-&gt;plane_res.dpp != new_pipe-&gt;plane_res.dpp</div><div class='add'>+		|| old_pipe-&gt;stream_res.opp != new_pipe-&gt;stream_res.opp)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.mpcc = 1;</div><div class='add'>+</div><div class='add'>+	/* Detect dppclk change */</div><div class='add'>+	if (old_pipe-&gt;plane_res.bw.dppclk_khz != new_pipe-&gt;plane_res.bw.dppclk_khz)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.dppclk = 1;</div><div class='add'>+</div><div class='add'>+	/* Check for scl update */</div><div class='add'>+	if (memcmp(&amp;old_pipe-&gt;plane_res.scl_data, &amp;new_pipe-&gt;plane_res.scl_data, sizeof(struct scaler_data)))</div><div class='add'>+		new_pipe-&gt;update_flags.bits.scaler = 1;</div><div class='add'>+	/* Check for vp update */</div><div class='add'>+	if (memcmp(&amp;old_pipe-&gt;plane_res.scl_data.viewport, &amp;new_pipe-&gt;plane_res.scl_data.viewport, sizeof(struct rect))</div><div class='add'>+		|| memcmp(&amp;old_pipe-&gt;plane_res.scl_data.viewport_c,</div><div class='add'>+			&amp;new_pipe-&gt;plane_res.scl_data.viewport_c, sizeof(struct rect)))</div><div class='add'>+		new_pipe-&gt;update_flags.bits.viewport = 1;</div><div class='add'>+</div><div class='add'>+	/* Detect dlg/ttu/rq updates */</div><div class='add'>+	{</div><div class='add'>+		struct dml2_display_dlg_regs old_dlg_regs = old_pipe-&gt;hubp_regs.dlg_regs;</div><div class='add'>+		struct dml2_display_ttu_regs old_ttu_regs = old_pipe-&gt;hubp_regs.ttu_regs;</div><div class='add'>+		struct dml2_display_rq_regs	 old_rq_regs = old_pipe-&gt;hubp_regs.rq_regs;</div><div class='add'>+		struct dml2_display_dlg_regs *new_dlg_regs = &amp;new_pipe-&gt;hubp_regs.dlg_regs;</div><div class='add'>+		struct dml2_display_ttu_regs *new_ttu_regs = &amp;new_pipe-&gt;hubp_regs.ttu_regs;</div><div class='add'>+		struct dml2_display_rq_regs	 *new_rq_regs = &amp;new_pipe-&gt;hubp_regs.rq_regs;</div><div class='add'>+</div><div class='add'>+		/* Detect pipe interdependent updates */</div><div class='add'>+		if ((old_dlg_regs.dst_y_prefetch != new_dlg_regs-&gt;dst_y_prefetch)</div><div class='add'>+			|| (old_dlg_regs.vratio_prefetch != new_dlg_regs-&gt;vratio_prefetch)</div><div class='add'>+			|| (old_dlg_regs.vratio_prefetch_c != new_dlg_regs-&gt;vratio_prefetch_c)</div><div class='add'>+			|| (old_dlg_regs.dst_y_per_vm_vblank != new_dlg_regs-&gt;dst_y_per_vm_vblank)</div><div class='add'>+			|| (old_dlg_regs.dst_y_per_row_vblank != new_dlg_regs-&gt;dst_y_per_row_vblank)</div><div class='add'>+			|| (old_dlg_regs.dst_y_per_vm_flip != new_dlg_regs-&gt;dst_y_per_vm_flip)</div><div class='add'>+			|| (old_dlg_regs.dst_y_per_row_flip != new_dlg_regs-&gt;dst_y_per_row_flip)</div><div class='add'>+			|| (old_dlg_regs.refcyc_per_meta_chunk_vblank_l != new_dlg_regs-&gt;refcyc_per_meta_chunk_vblank_l)</div><div class='add'>+			|| (old_dlg_regs.refcyc_per_meta_chunk_vblank_c != new_dlg_regs-&gt;refcyc_per_meta_chunk_vblank_c)</div><div class='add'>+			|| (old_dlg_regs.refcyc_per_meta_chunk_flip_l != new_dlg_regs-&gt;refcyc_per_meta_chunk_flip_l)</div><div class='add'>+			|| (old_dlg_regs.refcyc_per_line_delivery_pre_l != new_dlg_regs-&gt;refcyc_per_line_delivery_pre_l)</div><div class='add'>+			|| (old_dlg_regs.refcyc_per_line_delivery_pre_c != new_dlg_regs-&gt;refcyc_per_line_delivery_pre_c)</div><div class='add'>+			|| (old_ttu_regs.refcyc_per_req_delivery_pre_l != new_ttu_regs-&gt;refcyc_per_req_delivery_pre_l)</div><div class='add'>+			|| (old_ttu_regs.refcyc_per_req_delivery_pre_c != new_ttu_regs-&gt;refcyc_per_req_delivery_pre_c)</div><div class='add'>+			|| (old_ttu_regs.refcyc_per_req_delivery_pre_cur0 !=</div><div class='add'>+				new_ttu_regs-&gt;refcyc_per_req_delivery_pre_cur0)</div><div class='add'>+			|| (old_ttu_regs.min_ttu_vblank != new_ttu_regs-&gt;min_ttu_vblank)</div><div class='add'>+			|| (old_ttu_regs.qos_level_flip != new_ttu_regs-&gt;qos_level_flip)) {</div><div class='add'>+			old_dlg_regs.dst_y_prefetch = new_dlg_regs-&gt;dst_y_prefetch;</div><div class='add'>+			old_dlg_regs.vratio_prefetch = new_dlg_regs-&gt;vratio_prefetch;</div><div class='add'>+			old_dlg_regs.vratio_prefetch_c = new_dlg_regs-&gt;vratio_prefetch_c;</div><div class='add'>+			old_dlg_regs.dst_y_per_vm_vblank = new_dlg_regs-&gt;dst_y_per_vm_vblank;</div><div class='add'>+			old_dlg_regs.dst_y_per_row_vblank = new_dlg_regs-&gt;dst_y_per_row_vblank;</div><div class='add'>+			old_dlg_regs.dst_y_per_vm_flip = new_dlg_regs-&gt;dst_y_per_vm_flip;</div><div class='add'>+			old_dlg_regs.dst_y_per_row_flip = new_dlg_regs-&gt;dst_y_per_row_flip;</div><div class='add'>+			old_dlg_regs.refcyc_per_meta_chunk_vblank_l = new_dlg_regs-&gt;refcyc_per_meta_chunk_vblank_l;</div><div class='add'>+			old_dlg_regs.refcyc_per_meta_chunk_vblank_c = new_dlg_regs-&gt;refcyc_per_meta_chunk_vblank_c;</div><div class='add'>+			old_dlg_regs.refcyc_per_meta_chunk_flip_l = new_dlg_regs-&gt;refcyc_per_meta_chunk_flip_l;</div><div class='add'>+			old_dlg_regs.refcyc_per_line_delivery_pre_l = new_dlg_regs-&gt;refcyc_per_line_delivery_pre_l;</div><div class='add'>+			old_dlg_regs.refcyc_per_line_delivery_pre_c = new_dlg_regs-&gt;refcyc_per_line_delivery_pre_c;</div><div class='add'>+			old_ttu_regs.refcyc_per_req_delivery_pre_l = new_ttu_regs-&gt;refcyc_per_req_delivery_pre_l;</div><div class='add'>+			old_ttu_regs.refcyc_per_req_delivery_pre_c = new_ttu_regs-&gt;refcyc_per_req_delivery_pre_c;</div><div class='add'>+			old_ttu_regs.refcyc_per_req_delivery_pre_cur0 = new_ttu_regs-&gt;refcyc_per_req_delivery_pre_cur0;</div><div class='add'>+			old_ttu_regs.min_ttu_vblank = new_ttu_regs-&gt;min_ttu_vblank;</div><div class='add'>+			old_ttu_regs.qos_level_flip = new_ttu_regs-&gt;qos_level_flip;</div><div class='add'>+			new_pipe-&gt;update_flags.bits.hubp_interdependent = 1;</div><div class='add'>+		}</div><div class='add'>+		/* Detect any other updates to ttu/rq/dlg */</div><div class='add'>+		if (memcmp(&amp;old_dlg_regs, new_dlg_regs, sizeof(old_dlg_regs)) ||</div><div class='add'>+			memcmp(&amp;old_ttu_regs, new_ttu_regs, sizeof(old_ttu_regs)) ||</div><div class='add'>+			memcmp(&amp;old_rq_regs, new_rq_regs, sizeof(old_rq_regs)))</div><div class='add'>+			new_pipe-&gt;update_flags.bits.hubp_rq_dlg_ttu = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (old_pipe-&gt;unbounded_req != new_pipe-&gt;unbounded_req)</div><div class='add'>+		new_pipe-&gt;update_flags.bits.unbounded_req = 1;</div><div class='add'>+</div><div class='add'>+	if (memcmp(&amp;old_pipe-&gt;stream_res.test_pattern_params,</div><div class='add'>+		&amp;new_pipe-&gt;stream_res.test_pattern_params, sizeof(struct test_pattern_params))) {</div><div class='add'>+		new_pipe-&gt;update_flags.bits.test_pattern_changed = 1;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_plane_atomic_power_down(struct dc *dc,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		struct hubp *hubp)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	uint32_t org_ip_request_cntl = 0;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (REG(DC_IP_REQUEST_CNTL)) {</div><div class='add'>+		REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='add'>+		if (org_ip_request_cntl == 0)</div><div class='add'>+			REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='add'>+				IP_REQUEST_EN, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.dpp_pg_control)</div><div class='add'>+		hws-&gt;funcs.dpp_pg_control(hws, dpp-&gt;inst, false);</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.hubp_pg_control)</div><div class='add'>+		hws-&gt;funcs.hubp_pg_control(hws, hubp-&gt;inst, false);</div><div class='add'>+</div><div class='add'>+	hubp-&gt;funcs-&gt;hubp_reset(hubp);</div><div class='add'>+	dpp-&gt;funcs-&gt;dpp_reset(dpp);</div><div class='add'>+</div><div class='add'>+	if (org_ip_request_cntl == 0 &amp;&amp; REG(DC_IP_REQUEST_CNTL))</div><div class='add'>+		REG_SET(DC_IP_REQUEST_CNTL, 0,</div><div class='add'>+			IP_REQUEST_EN, 0);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG(</div><div class='add'>+			"Power gated front end %d\n", hubp-&gt;inst);</div><div class='add'>+</div><div class='add'>+	if (hws-&gt;funcs.dpp_root_clock_control)</div><div class='add'>+		hws-&gt;funcs.dpp_root_clock_control(hws, dpp-&gt;inst, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	volatile struct dmub_cursor_offload_v1 *cs = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;cursor_offload_v1;</div><div class='add'>+	const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);</div><div class='add'>+	const struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+	const struct dpp *dpp = pipe-&gt;plane_res.dpp;</div><div class='add'>+	volatile struct dmub_cursor_offload_pipe_data_dcn401_v1 *p;</div><div class='add'>+	uint32_t stream_idx, write_idx, payload_idx;</div><div class='add'>+</div><div class='add'>+	if (!top_pipe || !hubp || !dpp)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	stream_idx = top_pipe-&gt;pipe_idx;</div><div class='add'>+	write_idx = cs-&gt;offload_streams[stream_idx].write_idx + 1; /*  new payload (+1) */</div><div class='add'>+	payload_idx = write_idx % ARRAY_SIZE(cs-&gt;offload_streams[stream_idx].payloads);</div><div class='add'>+</div><div class='add'>+	p = &amp;cs-&gt;offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe-&gt;pipe_idx].dcn401;</div><div class='add'>+</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp-&gt;att.SURFACE_ADDR;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp-&gt;att.SURFACE_ADDR_HIGH;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp-&gt;att.size.bits.width;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp-&gt;att.size.bits.height;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp-&gt;pos.position.bits.x_pos;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp-&gt;pos.position.bits.y_pos;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp-&gt;pos.hot_spot.bits.x_hot;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp-&gt;pos.hot_spot.bits.y_hot;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp-&gt;pos.dst_offset.bits.dst_x_offset;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp-&gt;pos.cur_ctl.bits.cur_enable;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp-&gt;att.cur_ctl.bits.mode;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp-&gt;pos.cur_ctl.bits.cur_2x_magnify;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp-&gt;att.cur_ctl.bits.pitch;</div><div class='add'>+	p-&gt;CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp-&gt;att.cur_ctl.bits.line_per_chunk;</div><div class='add'>+</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp-&gt;att.cur0_ctl.bits.cur0_enable;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp-&gt;att.cur0_ctl.bits.mode;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp-&gt;att.cur0_ctl.bits.expansion_mode;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp-&gt;att.cur0_ctl.bits.cur0_rom_en;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 = 0x000000;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 = 0xFFFFFF;</div><div class='add'>+</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y =</div><div class='add'>+		dpp-&gt;att.fp_scale_bias_g_y.bits.fp_bias_g_y;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y =</div><div class='add'>+		dpp-&gt;att.fp_scale_bias_g_y.bits.fp_scale_g_y;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB =</div><div class='add'>+		dpp-&gt;att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb;</div><div class='add'>+	p-&gt;CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB =</div><div class='add'>+		dpp-&gt;att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb;</div><div class='add'>+</div><div class='add'>+	p-&gt;HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp-&gt;att.settings.bits.dst_y_offset;</div><div class='add'>+	p-&gt;HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp-&gt;att.settings.bits.chunk_hdl_adjust;</div><div class='add'>+	p-&gt;HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp-&gt;use_mall_for_cursor;</div><div class='add'>+</div><div class='add'>+	cs-&gt;offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u &lt;&lt; pipe-&gt;pipe_idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_plane_atomic_power_down_sequence(struct dc *dc,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	uint32_t org_ip_request_cntl = 0;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	/* Check and set DC_IP_REQUEST_CNTL if needed */</div><div class='add'>+	if (REG(DC_IP_REQUEST_CNTL)) {</div><div class='add'>+		REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='add'>+		if (org_ip_request_cntl == 0)</div><div class='add'>+			hwss_add_dc_ip_request_cntl(seq_state, dc, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DPP power gating control */</div><div class='add'>+	hwss_add_dpp_pg_control(seq_state, hws, dpp-&gt;inst, false);</div><div class='add'>+</div><div class='add'>+	/* HUBP power gating control */</div><div class='add'>+	hwss_add_hubp_pg_control(seq_state, hws, hubp-&gt;inst, false);</div><div class='add'>+</div><div class='add'>+	/* HUBP reset */</div><div class='add'>+	hwss_add_hubp_reset(seq_state, hubp);</div><div class='add'>+</div><div class='add'>+	/* DPP reset */</div><div class='add'>+	hwss_add_dpp_reset(seq_state, dpp);</div><div class='add'>+</div><div class='add'>+	/* Restore DC_IP_REQUEST_CNTL if it was originally 0 */</div><div class='add'>+	if (org_ip_request_cntl == 0 &amp;&amp; REG(DC_IP_REQUEST_CNTL))</div><div class='add'>+		hwss_add_dc_ip_request_cntl(seq_state, dc, false);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("Power gated front end %d\n", hubp-&gt;inst);</div><div class='add'>+</div><div class='add'>+	/* DPP root clock control */</div><div class='add'>+	hwss_add_dpp_root_clock_control(seq_state, hws, dpp-&gt;inst, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* trigger HW to start disconnect plane from stream on the next vsync using block sequence */</div><div class='add'>+void dcn401_plane_atomic_disconnect_sequence(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+	int dpp_id = pipe_ctx-&gt;plane_res.dpp-&gt;inst;</div><div class='add'>+	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+	struct mpc_tree *mpc_tree_params;</div><div class='add'>+	struct mpcc *mpcc_to_remove = NULL;</div><div class='add'>+	struct output_pixel_processor *opp = pipe_ctx-&gt;stream_res.opp;</div><div class='add'>+</div><div class='add'>+	mpc_tree_params = &amp;(opp-&gt;mpc_tree_params);</div><div class='add'>+	mpcc_to_remove = mpc-&gt;funcs-&gt;get_mpcc_for_dpp(mpc_tree_params, dpp_id);</div><div class='add'>+</div><div class='add'>+	/*Already reset*/</div><div class='add'>+	if (mpcc_to_remove == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Step 1: Remove MPCC from MPC tree */</div><div class='add'>+	hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, mpcc_to_remove);</div><div class='add'>+</div><div class='add'>+	// Phantom pipes have OTG disabled by default, so MPCC_STATUS will never assert idle,</div><div class='add'>+	// so don't wait for MPCC_IDLE in the programming sequence</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) {</div><div class='add'>+		/* Step 2: Set MPCC disconnect pending flag */</div><div class='add'>+		hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx-&gt;plane_res.mpcc_inst, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 3: Set optimized required flag */</div><div class='add'>+	hwss_add_dc_set_optimized_required(seq_state, dc, true);</div><div class='add'>+</div><div class='add'>+	/* Step 4: Disconnect HUBP if function exists */</div><div class='add'>+	if (hubp-&gt;funcs-&gt;hubp_disconnect)</div><div class='add'>+		hwss_add_hubp_disconnect(seq_state, hubp);</div><div class='add'>+</div><div class='add'>+	/* Step 5: Verify pstate change high if debug sanity checks are enabled */</div><div class='add'>+	if (dc-&gt;debug.sanity_checks)</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.verify_allow_pstate_change_high_sequence(dc, seq_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_blank_pixel_data_sequence(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	bool blank,</div><div class='add'>+	struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct tg_color black_color = {0};</div><div class='add'>+	struct stream_resource *stream_res = &amp;pipe_ctx-&gt;stream_res;</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	enum dc_color_space color_space = stream-&gt;output_color_space;</div><div class='add'>+	enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;</div><div class='add'>+	enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;</div><div class='add'>+	struct pipe_ctx *odm_pipe;</div><div class='add'>+	struct rect odm_slice_src;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;link-&gt;test_pattern_enabled)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* get opp dpg blank color */</div><div class='add'>+	color_space_to_black_color(dc, color_space, &amp;black_color);</div><div class='add'>+</div><div class='add'>+	if (blank) {</div><div class='add'>+		/* Set ABM immediate disable */</div><div class='add'>+		hwss_add_abm_set_immediate_disable(seq_state, dc, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {</div><div class='add'>+			test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;</div><div class='add'>+			test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	odm_pipe = pipe_ctx;</div><div class='add'>+</div><div class='add'>+	/* Set display pattern generator for all ODM pipes */</div><div class='add'>+	while (odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+		odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe);</div><div class='add'>+</div><div class='add'>+		hwss_add_opp_set_disp_pattern_generator(seq_state,</div><div class='add'>+			odm_pipe-&gt;stream_res.opp,</div><div class='add'>+			test_pattern,</div><div class='add'>+			test_pattern_color_space,</div><div class='add'>+			stream-&gt;timing.display_color_depth,</div><div class='add'>+			black_color,</div><div class='add'>+			true,</div><div class='add'>+			odm_slice_src.width,</div><div class='add'>+			odm_slice_src.height,</div><div class='add'>+			odm_slice_src.x);</div><div class='add'>+</div><div class='add'>+		odm_pipe = odm_pipe-&gt;next_odm_pipe;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set display pattern generator for final ODM pipe */</div><div class='add'>+	odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe);</div><div class='add'>+</div><div class='add'>+	hwss_add_opp_set_disp_pattern_generator(seq_state,</div><div class='add'>+		odm_pipe-&gt;stream_res.opp,</div><div class='add'>+		test_pattern,</div><div class='add'>+		test_pattern_color_space,</div><div class='add'>+		stream-&gt;timing.display_color_depth,</div><div class='add'>+		black_color,</div><div class='add'>+		true,</div><div class='add'>+		odm_slice_src.width,</div><div class='add'>+		odm_slice_src.height,</div><div class='add'>+		odm_slice_src.x);</div><div class='add'>+</div><div class='add'>+	/* Handle ABM level setting when not blanking */</div><div class='add'>+	if (!blank) {</div><div class='add'>+		if (stream_res-&gt;abm) {</div><div class='add'>+			/* Set pipe for ABM */</div><div class='add'>+			hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx);</div><div class='add'>+</div><div class='add'>+			/* Set ABM level */</div><div class='add'>+			hwss_add_abm_set_level(seq_state, stream_res-&gt;abm, stream-&gt;abm_level);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_program_all_writeback_pipes_in_tree_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+	int i_wb, i_pipe;</div><div class='add'>+</div><div class='add'>+	if (!stream || stream-&gt;num_wb_info &gt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dwb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* For each writeback pipe */</div><div class='add'>+	for (i_wb = 0; i_wb &lt; stream-&gt;num_wb_info; i_wb++) {</div><div class='add'>+		/* Get direct pointer to writeback info */</div><div class='add'>+		struct dc_writeback_info *wb_info = (struct dc_writeback_info *)&amp;stream-&gt;writeback_info[i_wb];</div><div class='add'>+		int mpcc_inst = -1;</div><div class='add'>+</div><div class='add'>+		if (wb_info-&gt;wb_enabled) {</div><div class='add'>+			/* Get the MPCC instance for writeback_source_plane */</div><div class='add'>+			for (i_pipe = 0; i_pipe &lt; dc-&gt;res_pool-&gt;pipe_count; i_pipe++) {</div><div class='add'>+				struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i_pipe];</div><div class='add'>+</div><div class='add'>+				if (!pipe_ctx-&gt;plane_state)</div><div class='add'>+					continue;</div><div class='add'>+</div><div class='add'>+				if (pipe_ctx-&gt;plane_state == wb_info-&gt;writeback_source_plane) {</div><div class='add'>+					mpcc_inst = pipe_ctx-&gt;plane_res.mpcc_inst;</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (mpcc_inst == -1) {</div><div class='add'>+				/* Disable writeback pipe and disconnect from MPCC</div><div class='add'>+				 * if source plane has been removed</div><div class='add'>+				 */</div><div class='add'>+				dcn401_disable_writeback_sequence(dc, wb_info, seq_state);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			ASSERT(wb_info-&gt;dwb_pipe_inst &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dwb);</div><div class='add'>+			dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+</div><div class='add'>+			if (dwb-&gt;funcs-&gt;is_enabled(dwb)) {</div><div class='add'>+				/* Writeback pipe already enabled, only need to update */</div><div class='add'>+				dcn401_update_writeback_sequence(dc, wb_info, context, seq_state);</div><div class='add'>+			} else {</div><div class='add'>+				/* Enable writeback pipe and connect to MPCC */</div><div class='add'>+				dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* Disable writeback pipe and disconnect from MPCC */</div><div class='add'>+			dcn401_disable_writeback_sequence(dc, wb_info, seq_state);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_enable_writeback_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_writeback_info *wb_info,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		int mpcc_inst,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+</div><div class='add'>+	if (!wb_info-&gt;wb_enabled || wb_info-&gt;dwb_pipe_inst &gt;= dc-&gt;res_pool-&gt;res_cap-&gt;num_dwb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+	mcif_wb = dc-&gt;res_pool-&gt;mcif_wb[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+</div><div class='add'>+	/* Update DWBC with new parameters */</div><div class='add'>+	hwss_add_dwbc_update(seq_state, dwb, &amp;wb_info-&gt;dwb_params);</div><div class='add'>+</div><div class='add'>+	/* Configure MCIF_WB buffer settings */</div><div class='add'>+	hwss_add_mcif_wb_config_buf(seq_state, mcif_wb, &amp;wb_info-&gt;mcif_buf_params, wb_info-&gt;dwb_params.dest_height);</div><div class='add'>+</div><div class='add'>+	/* Configure MCIF_WB arbitration */</div><div class='add'>+	hwss_add_mcif_wb_config_arb(seq_state, mcif_wb, &amp;context-&gt;bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-&gt;dwb_pipe_inst]);</div><div class='add'>+</div><div class='add'>+	/* Enable MCIF_WB */</div><div class='add'>+	hwss_add_mcif_wb_enable(seq_state, mcif_wb);</div><div class='add'>+</div><div class='add'>+	/* Set DWB MUX to connect writeback to MPCC */</div><div class='add'>+	hwss_add_mpc_set_dwb_mux(seq_state, dc-&gt;res_pool-&gt;mpc, wb_info-&gt;dwb_pipe_inst, mpcc_inst);</div><div class='add'>+</div><div class='add'>+	/* Enable DWBC */</div><div class='add'>+	hwss_add_dwbc_enable(seq_state, dwb, &amp;wb_info-&gt;dwb_params);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_disable_writeback_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_writeback_info *wb_info,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+</div><div class='add'>+	if (wb_info-&gt;dwb_pipe_inst &gt;= dc-&gt;res_pool-&gt;res_cap-&gt;num_dwb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+	mcif_wb = dc-&gt;res_pool-&gt;mcif_wb[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+</div><div class='add'>+	/* Disable DWBC */</div><div class='add'>+	hwss_add_dwbc_disable(seq_state, dwb);</div><div class='add'>+</div><div class='add'>+	/* Disable DWB MUX */</div><div class='add'>+	hwss_add_mpc_disable_dwb_mux(seq_state, dc-&gt;res_pool-&gt;mpc, wb_info-&gt;dwb_pipe_inst);</div><div class='add'>+</div><div class='add'>+	/* Disable MCIF_WB */</div><div class='add'>+	hwss_add_mcif_wb_disable(seq_state, mcif_wb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_writeback_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_writeback_info *wb_info,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+</div><div class='add'>+	if (!wb_info-&gt;wb_enabled || wb_info-&gt;dwb_pipe_inst &gt;= dc-&gt;res_pool-&gt;res_cap-&gt;num_dwb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+	mcif_wb = dc-&gt;res_pool-&gt;mcif_wb[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+</div><div class='add'>+	/* Update writeback pipe */</div><div class='add'>+	hwss_add_dwbc_update(seq_state, dwb, &amp;wb_info-&gt;dwb_params);</div><div class='add'>+</div><div class='add'>+	/* Update MCIF_WB buffer settings if needed */</div><div class='add'>+	hwss_add_mcif_wb_config_buf(seq_state, mcif_wb, &amp;wb_info-&gt;mcif_buf_params, wb_info-&gt;dwb_params.dest_height);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int find_free_gsl_group(const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	if (dc-&gt;res_pool-&gt;gsl_groups.gsl_0 == 0)</div><div class='add'>+		return 1;</div><div class='add'>+	if (dc-&gt;res_pool-&gt;gsl_groups.gsl_1 == 0)</div><div class='add'>+		return 2;</div><div class='add'>+	if (dc-&gt;res_pool-&gt;gsl_groups.gsl_2 == 0)</div><div class='add'>+		return 3;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_setup_gsl_group_as_lock_sequence(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		bool enable,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct gsl_params gsl;</div><div class='add'>+	int group_idx;</div><div class='add'>+</div><div class='add'>+	memset(&amp;gsl, 0, sizeof(struct gsl_params));</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		/* return if group already assigned since GSL was set up</div><div class='add'>+		 * for vsync flip, we would unassign so it can't be "left over"</div><div class='add'>+		 */</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.gsl_group &gt; 0)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		group_idx = find_free_gsl_group(dc);</div><div class='add'>+		ASSERT(group_idx != 0);</div><div class='add'>+		pipe_ctx-&gt;stream_res.gsl_group = group_idx;</div><div class='add'>+</div><div class='add'>+		/* set gsl group reg field and mark resource used */</div><div class='add'>+		switch (group_idx) {</div><div class='add'>+		case 1:</div><div class='add'>+			gsl.gsl0_en = 1;</div><div class='add'>+			dc-&gt;res_pool-&gt;gsl_groups.gsl_0 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			gsl.gsl1_en = 1;</div><div class='add'>+			dc-&gt;res_pool-&gt;gsl_groups.gsl_1 = 1;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			gsl.gsl2_en = 1;</div><div class='add'>+			dc-&gt;res_pool-&gt;gsl_groups.gsl_2 = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			return; // invalid case</div><div class='add'>+		}</div><div class='add'>+		gsl.gsl_master_en = 1;</div><div class='add'>+	} else {</div><div class='add'>+		group_idx = pipe_ctx-&gt;stream_res.gsl_group;</div><div class='add'>+		if (group_idx == 0)</div><div class='add'>+			return; // if not in use, just return</div><div class='add'>+</div><div class='add'>+		pipe_ctx-&gt;stream_res.gsl_group = 0;</div><div class='add'>+</div><div class='add'>+		/* unset gsl group reg field and mark resource free */</div><div class='add'>+		switch (group_idx) {</div><div class='add'>+		case 1:</div><div class='add'>+			gsl.gsl0_en = 0;</div><div class='add'>+			dc-&gt;res_pool-&gt;gsl_groups.gsl_0 = 0;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			gsl.gsl1_en = 0;</div><div class='add'>+			dc-&gt;res_pool-&gt;gsl_groups.gsl_1 = 0;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			gsl.gsl2_en = 0;</div><div class='add'>+			dc-&gt;res_pool-&gt;gsl_groups.gsl_2 = 0;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+		gsl.gsl_master_en = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hwss_add_tg_set_gsl(seq_state, pipe_ctx-&gt;stream_res.tg, gsl);</div><div class='add'>+	hwss_add_tg_set_gsl_source_select(seq_state, pipe_ctx-&gt;stream_res.tg, group_idx, enable ? 4 : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_disable_plane_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;</div><div class='add'>+	struct timing_generator *tg = is_phantom ? pipe_ctx-&gt;stream_res.tg : NULL;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;plane_res.hubp || pipe_ctx-&gt;plane_res.hubp-&gt;power_gated)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Wait for MPCC disconnect */</div><div class='add'>+	if (dc-&gt;hwss.wait_for_mpcc_disconnect_sequence)</div><div class='add'>+		dc-&gt;hwss.wait_for_mpcc_disconnect_sequence(dc, dc-&gt;res_pool, pipe_ctx, seq_state);</div><div class='add'>+</div><div class='add'>+	/* In flip immediate with pipe splitting case GSL is used for synchronization</div><div class='add'>+	 * so we must disable it when the plane is disabled.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;stream_res.gsl_group != 0)</div><div class='add'>+		dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state);</div><div class='add'>+</div><div class='add'>+	/* Update HUBP mall sel */</div><div class='add'>+	if (pipe_ctx-&gt;plane_res.hubp &amp;&amp; pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_update_mall_sel)</div><div class='add'>+		hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx-&gt;plane_res.hubp, 0, false);</div><div class='add'>+</div><div class='add'>+	/* Set flip control GSL */</div><div class='add'>+	hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx-&gt;plane_res.hubp, false);</div><div class='add'>+</div><div class='add'>+	/* HUBP clock control */</div><div class='add'>+	hwss_add_hubp_clk_cntl(seq_state, pipe_ctx-&gt;plane_res.hubp, false);</div><div class='add'>+</div><div class='add'>+	/* DPP clock control */</div><div class='add'>+	hwss_add_dpp_dppclk_control(seq_state, pipe_ctx-&gt;plane_res.dpp, false, false);</div><div class='add'>+</div><div class='add'>+	/* Plane atomic power down */</div><div class='add'>+	if (dc-&gt;hwseq-&gt;funcs.plane_atomic_power_down_sequence)</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.plane_atomic_power_down_sequence(dc, pipe_ctx-&gt;plane_res.dpp,</div><div class='add'>+			pipe_ctx-&gt;plane_res.hubp, seq_state);</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;stream = NULL;</div><div class='add'>+	memset(&amp;pipe_ctx-&gt;stream_res, 0, sizeof(pipe_ctx-&gt;stream_res));</div><div class='add'>+	memset(&amp;pipe_ctx-&gt;plane_res, 0, sizeof(pipe_ctx-&gt;plane_res));</div><div class='add'>+	pipe_ctx-&gt;top_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;bottom_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;prev_odm_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;next_odm_pipe = NULL;</div><div class='add'>+	pipe_ctx-&gt;plane_state = NULL;</div><div class='add'>+</div><div class='add'>+	/* Turn back off the phantom OTG after the phantom plane is fully disabled */</div><div class='add'>+	if (is_phantom &amp;&amp; tg &amp;&amp; tg-&gt;funcs-&gt;disable_phantom_crtc)</div><div class='add'>+		hwss_add_disable_phantom_crtc(seq_state, tg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_post_unlock_reset_opp_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *opp_head,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct display_stream_compressor *dsc = opp_head-&gt;stream_res.dsc;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+</div><div class='add'>+	/* Wait for all DPP pipes in current mpc blending tree completes double</div><div class='add'>+	 * buffered disconnection before resetting OPP</div><div class='add'>+	 */</div><div class='add'>+	if (dc-&gt;hwss.wait_for_mpcc_disconnect_sequence)</div><div class='add'>+		dc-&gt;hwss.wait_for_mpcc_disconnect_sequence(dc, dc-&gt;res_pool, opp_head, seq_state);</div><div class='add'>+</div><div class='add'>+	if (dsc) {</div><div class='add'>+		bool *is_ungated = NULL;</div><div class='add'>+		/* Check DSC power gate status */</div><div class='add'>+		if (dc-&gt;hwseq &amp;&amp; dc-&gt;hwseq-&gt;funcs.dsc_pg_status)</div><div class='add'>+			hwss_add_dsc_pg_status(seq_state, dc-&gt;hwseq, dsc-&gt;inst, false);</div><div class='add'>+</div><div class='add'>+		/* Seamless update specific where we will postpone non</div><div class='add'>+		 * double buffered DSCCLK disable logic in post unlock</div><div class='add'>+		 * sequence after DSC is disconnected from OPP but not</div><div class='add'>+		 * yet power gated.</div><div class='add'>+		 */</div><div class='add'>+</div><div class='add'>+		/* DSC wait disconnect pending clear */</div><div class='add'>+		hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc, is_ungated);</div><div class='add'>+</div><div class='add'>+		/* DSC disable */</div><div class='add'>+		hwss_add_dsc_disable(seq_state, dsc, is_ungated);</div><div class='add'>+</div><div class='add'>+		/* Set reference DSCCLK */</div><div class='add'>+		if (dccg &amp;&amp; dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+			hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc-&gt;inst, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+</div><div class='add'>+	if (REG(DC_IP_REQUEST_CNTL))</div><div class='add'>+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+				 struct dc_state *context,</div><div class='add'>+				 struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	uint32_t org_ip_request_cntl = 0;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;plane_res.dpp || !pipe_ctx-&gt;plane_res.hubp || !pipe_ctx-&gt;stream_res.opp)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (REG(DC_IP_REQUEST_CNTL))</div><div class='add'>+		REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='add'>+</div><div class='add'>+	/* Step 1: DPP root clock control - enable clock */</div><div class='add'>+	if (hws-&gt;funcs.dpp_root_clock_control)</div><div class='add'>+		hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx-&gt;plane_res.dpp-&gt;inst, true);</div><div class='add'>+</div><div class='add'>+	/* Step 2: Enable DC IP request (if needed) */</div><div class='add'>+	if (hws-&gt;funcs.dc_ip_request_cntl)</div><div class='add'>+		hwss_add_dc_ip_request_cntl(seq_state, dc, true);</div><div class='add'>+</div><div class='add'>+	/* Step 3: DPP power gating control - power on */</div><div class='add'>+	if (REG(DC_IP_REQUEST_CNTL) &amp;&amp; hws-&gt;funcs.dpp_pg_control)</div><div class='add'>+		hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx-&gt;plane_res.dpp-&gt;inst, true);</div><div class='add'>+</div><div class='add'>+	/* Step 4: HUBP power gating control - power on */</div><div class='add'>+	if (REG(DC_IP_REQUEST_CNTL) &amp;&amp; hws-&gt;funcs.hubp_pg_control)</div><div class='add'>+		hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx-&gt;plane_res.hubp-&gt;inst, true);</div><div class='add'>+</div><div class='add'>+	/* Step 5: Disable DC IP request (restore state) */</div><div class='add'>+	if (org_ip_request_cntl == 0 &amp;&amp; hws-&gt;funcs.dc_ip_request_cntl)</div><div class='add'>+		hwss_add_dc_ip_request_cntl(seq_state, dc, false);</div><div class='add'>+</div><div class='add'>+	/* Step 6: HUBP clock control - enable DCFCLK */</div><div class='add'>+	if (pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_clk_cntl)</div><div class='add'>+		hwss_add_hubp_clk_cntl(seq_state, pipe_ctx-&gt;plane_res.hubp, true);</div><div class='add'>+</div><div class='add'>+	/* Step 7: HUBP initialization */</div><div class='add'>+	if (pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_init)</div><div class='add'>+		hwss_add_hubp_init(seq_state, pipe_ctx-&gt;plane_res.hubp);</div><div class='add'>+</div><div class='add'>+	/* Step 8: OPP pipe clock control - enable */</div><div class='add'>+	if (pipe_ctx-&gt;stream_res.opp-&gt;funcs-&gt;opp_pipe_clock_control)</div><div class='add'>+		hwss_add_opp_pipe_clock_control(seq_state, pipe_ctx-&gt;stream_res.opp, true);</div><div class='add'>+</div><div class='add'>+	/* Step 9: VM system aperture settings */</div><div class='add'>+	if (dc-&gt;vm_pa_config.valid &amp;&amp; pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_set_vm_system_aperture_settings) {</div><div class='add'>+		hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx-&gt;plane_res.hubp, 0,</div><div class='add'>+			dc-&gt;vm_pa_config.system_aperture.start_addr, dc-&gt;vm_pa_config.system_aperture.end_addr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 10: Flip interrupt setup */</div><div class='add'>+	if (!pipe_ctx-&gt;top_pipe</div><div class='add'>+			&amp;&amp; pipe_ctx-&gt;plane_state</div><div class='add'>+			&amp;&amp; pipe_ctx-&gt;plane_state-&gt;flip_int_enabled</div><div class='add'>+			&amp;&amp; pipe_ctx-&gt;plane_res.hubp-&gt;funcs-&gt;hubp_set_flip_int) {</div><div class='add'>+		hwss_add_hubp_set_flip_int(seq_state, pipe_ctx-&gt;plane_res.hubp);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_dchubp_dpp_sequence(struct dc *dc,</div><div class='add'>+				       struct pipe_ctx *pipe_ctx,</div><div class='add'>+				       struct dc_state *context,</div><div class='add'>+				       struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+	struct dpp *dpp = pipe_ctx-&gt;plane_res.dpp;</div><div class='add'>+	struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+	bool viewport_changed = false;</div><div class='add'>+	enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (!hubp || !dpp || !plane_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Step 1: DPP DPPCLK control */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.dppclk)</div><div class='add'>+		hwss_add_dpp_dppclk_control(seq_state, dpp, false, true);</div><div class='add'>+</div><div class='add'>+	/* Step 2: DCCG update DPP DTO */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable)</div><div class='add'>+		hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp-&gt;inst, pipe_ctx-&gt;plane_res.bw.dppclk_khz);</div><div class='add'>+</div><div class='add'>+	/* Step 3: HUBP VTG selection */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.hubp_rq_dlg_ttu) {</div><div class='add'>+		hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx-&gt;stream_res.tg-&gt;inst);</div><div class='add'>+</div><div class='add'>+		/* Step 4: HUBP setup (choose setup2 or setup) */</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_setup2) {</div><div class='add'>+			hwss_add_hubp_setup2(seq_state, hubp, &amp;pipe_ctx-&gt;hubp_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;global_sync, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='add'>+		} else if (hubp-&gt;funcs-&gt;hubp_setup) {</div><div class='add'>+			hwss_add_hubp_setup(seq_state, hubp, &amp;pipe_ctx-&gt;dlg_regs,</div><div class='add'>+				&amp;pipe_ctx-&gt;ttu_regs, &amp;pipe_ctx-&gt;rq_regs, &amp;pipe_ctx-&gt;pipe_dlg_param);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 5: Set unbounded requesting */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.unbounded_req &amp;&amp; hubp-&gt;funcs-&gt;set_unbounded_requesting)</div><div class='add'>+		hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx-&gt;unbounded_req);</div><div class='add'>+</div><div class='add'>+	/* Step 6: HUBP interdependent setup */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.hubp_interdependent) {</div><div class='add'>+		if (hubp-&gt;funcs-&gt;hubp_setup_interdependent2)</div><div class='add'>+			hwss_add_hubp_setup_interdependent2(seq_state, hubp, &amp;pipe_ctx-&gt;hubp_regs);</div><div class='add'>+		else if (hubp-&gt;funcs-&gt;hubp_setup_interdependent)</div><div class='add'>+			hwss_add_hubp_setup_interdependent(seq_state, hubp, &amp;pipe_ctx-&gt;dlg_regs, &amp;pipe_ctx-&gt;ttu_regs);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 7: DPP setup - input CSC and format setup */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.bpp_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.input_csc_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.color_space_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.coeff_reduction_change) {</div><div class='add'>+		hwss_add_dpp_setup_dpp(seq_state, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		/* Step 8: DPP cursor matrix setup */</div><div class='add'>+		if (dpp-&gt;funcs-&gt;set_cursor_matrix) {</div><div class='add'>+			hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state-&gt;color_space,</div><div class='add'>+				&amp;plane_state-&gt;cursor_csc_color_matrix);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Step 9: DPP program bias and scale */</div><div class='add'>+		if (dpp-&gt;funcs-&gt;dpp_program_bias_and_scale)</div><div class='add'>+			hwss_add_dpp_program_bias_and_scale(seq_state, pipe_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 10: MPCC updates */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.mpcc ||</div><div class='add'>+	     pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+	     plane_state-&gt;update_flags.bits.global_alpha_change ||</div><div class='add'>+	     plane_state-&gt;update_flags.bits.per_pixel_alpha_change) {</div><div class='add'>+</div><div class='add'>+		/* Check if update_mpcc_sequence is implemented and prefer it over single MPC_UPDATE_MPCC step */</div><div class='add'>+		if (hws-&gt;funcs.update_mpcc_sequence)</div><div class='add'>+			hws-&gt;funcs.update_mpcc_sequence(dc, pipe_ctx, seq_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 11: DPP scaler setup */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.scaler ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.scaling_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.position_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.per_pixel_alpha_change ||</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;update_flags.bits.scaling) {</div><div class='add'>+		pipe_ctx-&gt;plane_res.scl_data.lb_params.alpha_en = pipe_ctx-&gt;plane_state-&gt;per_pixel_alpha;</div><div class='add'>+		ASSERT(pipe_ctx-&gt;plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP);</div><div class='add'>+		hwss_add_dpp_set_scaler(seq_state, pipe_ctx-&gt;plane_res.dpp, &amp;pipe_ctx-&gt;plane_res.scl_data);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 12: HUBP viewport programming */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.viewport ||</div><div class='add'>+	     (context == dc-&gt;current_state &amp;&amp; plane_state-&gt;update_flags.bits.position_change) ||</div><div class='add'>+	     (context == dc-&gt;current_state &amp;&amp; plane_state-&gt;update_flags.bits.scaling_change) ||</div><div class='add'>+	     (context == dc-&gt;current_state &amp;&amp; pipe_ctx-&gt;stream-&gt;update_flags.bits.scaling)) {</div><div class='add'>+		hwss_add_hubp_mem_program_viewport(seq_state, hubp,</div><div class='add'>+			&amp;pipe_ctx-&gt;plane_res.scl_data.viewport, &amp;pipe_ctx-&gt;plane_res.scl_data.viewport_c);</div><div class='add'>+		viewport_changed = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 13: HUBP program mcache if available */</div><div class='add'>+	if (hubp-&gt;funcs-&gt;hubp_program_mcache_id_and_split_coordinate)</div><div class='add'>+		hwss_add_hubp_program_mcache_id(seq_state, hubp, &amp;pipe_ctx-&gt;mcache_regs);</div><div class='add'>+</div><div class='add'>+	/* Step 14: Cursor attribute setup */</div><div class='add'>+	if ((pipe_ctx-&gt;update_flags.bits.enable || pipe_ctx-&gt;update_flags.bits.opp_changed ||</div><div class='add'>+	     pipe_ctx-&gt;update_flags.bits.scaler || viewport_changed == true) &amp;&amp;</div><div class='add'>+	    pipe_ctx-&gt;stream-&gt;cursor_attributes.address.quad_part != 0) {</div><div class='add'>+</div><div class='add'>+		hwss_add_abort_cursor_offload_update(seq_state, dc, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		/* Step 15: Cursor position setup */</div><div class='add'>+		hwss_add_set_cursor_position(seq_state, dc, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		/* Step 16: Cursor SDR white level */</div><div class='add'>+		if (dc-&gt;hwss.set_cursor_sdr_white_level)</div><div class='add'>+			hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 17: Gamut remap and output CSC */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable || pipe_ctx-&gt;update_flags.bits.opp_changed ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;update_flags.bits.gamut_remap ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.gamut_remap_change ||</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;update_flags.bits.out_csc) {</div><div class='add'>+</div><div class='add'>+		/* Gamut remap */</div><div class='add'>+		hwss_add_dpp_program_gamut_remap(seq_state, pipe_ctx);</div><div class='add'>+</div><div class='add'>+		/* Output CSC */</div><div class='add'>+		hwss_add_program_output_csc(seq_state, dc, pipe_ctx, pipe_ctx-&gt;stream-&gt;output_color_space,</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;csc_color_matrix.matrix, hubp-&gt;opp_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 18: HUBP surface configuration */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+			pipe_ctx-&gt;update_flags.bits.opp_changed ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.pixel_format_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.horizontal_mirror_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.rotation_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.swizzle_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.dcc_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.bpp_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.scaling_change ||</div><div class='add'>+			plane_state-&gt;update_flags.bits.plane_size_change) {</div><div class='add'>+		struct plane_size size = plane_state-&gt;plane_size;</div><div class='add'>+</div><div class='add'>+		size.surface_size = pipe_ctx-&gt;plane_res.scl_data.viewport;</div><div class='add'>+		hwss_add_hubp_program_surface_config(seq_state, hubp,</div><div class='add'>+				plane_state-&gt;format, &amp;plane_state-&gt;tiling_info, size,</div><div class='add'>+				plane_state-&gt;rotation, &amp;plane_state-&gt;dcc,</div><div class='add'>+				plane_state-&gt;horizontal_mirror, 0);</div><div class='add'>+		hubp-&gt;power_gated = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 19: Update plane address (with SubVP support) */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable ||</div><div class='add'>+	     pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='add'>+	     plane_state-&gt;update_flags.bits.addr_update) {</div><div class='add'>+</div><div class='add'>+		/* SubVP save surface address if needed */</div><div class='add'>+		if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &amp;&amp; pipe_mall_type == SUBVP_MAIN) {</div><div class='add'>+			hwss_add_dmub_subvp_save_surf_addr(seq_state, dc-&gt;ctx-&gt;dmub_srv,</div><div class='add'>+				&amp;pipe_ctx-&gt;plane_state-&gt;address, pipe_ctx-&gt;subvp_index);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Update plane address */</div><div class='add'>+		hwss_add_hubp_update_plane_addr(seq_state, dc, pipe_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 20: HUBP set blank - enable plane */</div><div class='add'>+	if (pipe_ctx-&gt;update_flags.bits.enable)</div><div class='add'>+		hwss_add_hubp_set_blank(seq_state, hubp, false);</div><div class='add'>+</div><div class='add'>+	/* Step 21: Phantom HUBP post enable */</div><div class='add'>+	if (pipe_mall_type == SUBVP_PHANTOM &amp;&amp; hubp-&gt;funcs-&gt;phantom_hubp_post_enable)</div><div class='add'>+		hwss_add_phantom_hubp_post_enable(seq_state, hubp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_mpcc_sequence(struct dc *dc,</div><div class='add'>+				struct pipe_ctx *pipe_ctx,</div><div class='add'>+				struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+	struct mpcc_blnd_cfg blnd_cfg = {0};</div><div class='add'>+	bool per_pixel_alpha;</div><div class='add'>+	int mpcc_id;</div><div class='add'>+	struct mpcc *new_mpcc;</div><div class='add'>+	struct mpc *mpc = dc-&gt;res_pool-&gt;mpc;</div><div class='add'>+	struct mpc_tree *mpc_tree_params = &amp;(pipe_ctx-&gt;stream_res.opp-&gt;mpc_tree_params);</div><div class='add'>+</div><div class='add'>+	if (!hubp || !pipe_ctx-&gt;plane_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	per_pixel_alpha = pipe_ctx-&gt;plane_state-&gt;per_pixel_alpha;</div><div class='add'>+</div><div class='add'>+	/* Initialize blend configuration */</div><div class='add'>+	blnd_cfg.overlap_only = false;</div><div class='add'>+	blnd_cfg.global_gain = 0xff;</div><div class='add'>+</div><div class='add'>+	if (per_pixel_alpha) {</div><div class='add'>+		blnd_cfg.pre_multiplied_alpha = pipe_ctx-&gt;plane_state-&gt;pre_multiplied_alpha;</div><div class='add'>+		if (pipe_ctx-&gt;plane_state-&gt;global_alpha) {</div><div class='add'>+			blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;</div><div class='add'>+			blnd_cfg.global_gain = pipe_ctx-&gt;plane_state-&gt;global_alpha_value;</div><div class='add'>+		} else {</div><div class='add'>+			blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		blnd_cfg.pre_multiplied_alpha = false;</div><div class='add'>+		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state-&gt;global_alpha)</div><div class='add'>+		blnd_cfg.global_alpha = pipe_ctx-&gt;plane_state-&gt;global_alpha_value;</div><div class='add'>+	else</div><div class='add'>+		blnd_cfg.global_alpha = 0xff;</div><div class='add'>+</div><div class='add'>+	blnd_cfg.background_color_bpc = 4;</div><div class='add'>+	blnd_cfg.bottom_gain_mode = 0;</div><div class='add'>+	blnd_cfg.top_gain = 0x1f000;</div><div class='add'>+	blnd_cfg.bottom_inside_gain = 0x1f000;</div><div class='add'>+	blnd_cfg.bottom_outside_gain = 0x1f000;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;plane_state-&gt;format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)</div><div class='add'>+		blnd_cfg.pre_multiplied_alpha = false;</div><div class='add'>+</div><div class='add'>+	/* MPCC instance is equal to HUBP instance */</div><div class='add'>+	mpcc_id = hubp-&gt;inst;</div><div class='add'>+</div><div class='add'>+	/* Step 1: Update blending if no full update needed */</div><div class='add'>+	if (!pipe_ctx-&gt;plane_state-&gt;update_flags.bits.full_update &amp;&amp;</div><div class='add'>+	    !pipe_ctx-&gt;update_flags.bits.mpcc) {</div><div class='add'>+</div><div class='add'>+		/* Update blending configuration */</div><div class='add'>+		hwss_add_mpc_update_blending(seq_state, mpc, blnd_cfg, mpcc_id);</div><div class='add'>+</div><div class='add'>+		/* Update visual confirm color */</div><div class='add'>+		hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 2: Get existing MPCC for DPP */</div><div class='add'>+	new_mpcc = mpc-&gt;funcs-&gt;get_mpcc_for_dpp(mpc_tree_params, mpcc_id);</div><div class='add'>+</div><div class='add'>+	/* Step 3: Remove MPCC if being used */</div><div class='add'>+	if (new_mpcc != NULL) {</div><div class='add'>+		hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, new_mpcc);</div><div class='add'>+	} else {</div><div class='add'>+		/* Step 4: Assert MPCC idle (debug only) */</div><div class='add'>+		if (dc-&gt;debug.sanity_checks)</div><div class='add'>+			hwss_add_mpc_assert_idle_mpcc(seq_state, mpc, mpcc_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 5: Insert new plane into MPC tree */</div><div class='add'>+	hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp-&gt;inst, mpcc_id);</div><div class='add'>+</div><div class='add'>+	/* Step 6: Update visual confirm color */</div><div class='add'>+	hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id);</div><div class='add'>+</div><div class='add'>+	/* Step 7: Set HUBP OPP and MPCC IDs */</div><div class='add'>+	hubp-&gt;opp_id = pipe_ctx-&gt;stream_res.opp-&gt;inst;</div><div class='add'>+	hubp-&gt;mpcc_id = mpcc_id;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (res_pool-&gt;hubps[i]-&gt;inst == mpcc_inst)</div><div class='add'>+			return res_pool-&gt;hubps[i];</div><div class='add'>+	}</div><div class='add'>+	ASSERT(false);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_wait_for_mpcc_disconnect_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct resource_pool *res_pool,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	int mpcc_inst;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.sanity_checks)</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.verify_allow_pstate_change_high_sequence(dc, seq_state);</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;stream_res.opp)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (mpcc_inst = 0; mpcc_inst &lt; MAX_PIPES; mpcc_inst++) {</div><div class='add'>+		if (pipe_ctx-&gt;stream_res.opp-&gt;mpcc_disconnect_pending[mpcc_inst]) {</div><div class='add'>+			struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);</div><div class='add'>+</div><div class='add'>+			if (pipe_ctx-&gt;stream_res.tg &amp;&amp;</div><div class='add'>+				pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_tg_enabled(pipe_ctx-&gt;stream_res.tg)) {</div><div class='add'>+				hwss_add_mpc_assert_idle_mpcc(seq_state, res_pool-&gt;mpc, mpcc_inst);</div><div class='add'>+			}</div><div class='add'>+			pipe_ctx-&gt;stream_res.opp-&gt;mpcc_disconnect_pending[mpcc_inst] = false;</div><div class='add'>+			if (hubp)</div><div class='add'>+				hwss_add_hubp_set_blank(seq_state, hubp, true);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.sanity_checks)</div><div class='add'>+		dc-&gt;hwseq-&gt;funcs.verify_allow_pstate_change_high_sequence(dc, seq_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct timing_generator *tg = pipe_ctx-&gt;stream_res.tg;</div><div class='add'>+	int start_line = dc-&gt;hwss.get_vupdate_offset_from_vsync(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (start_line &lt; 0)</div><div class='add'>+		start_line = 0;</div><div class='add'>+</div><div class='add'>+	if (tg-&gt;funcs-&gt;setup_vertical_interrupt2)</div><div class='add'>+		hwss_add_tg_setup_vertical_interrupt2(seq_state, tg, start_line);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct fixed31_32 multiplier = pipe_ctx-&gt;plane_state-&gt;hdr_mult;</div><div class='add'>+	uint32_t hw_mult = 0x1f000; // 1.0 default multiplier</div><div class='add'>+	struct custom_float_format fmt;</div><div class='add'>+</div><div class='add'>+	fmt.exponenta_bits = 6;</div><div class='add'>+	fmt.mantissa_bits = 12;</div><div class='add'>+	fmt.sign = true;</div><div class='add'>+</div><div class='add'>+	if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0</div><div class='add'>+		convert_to_custom_float_format(multiplier, &amp;fmt, &amp;hw_mult);</div><div class='add'>+</div><div class='add'>+	hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx-&gt;plane_res.dpp, hw_mult);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	unsigned int num_ways = dcn401_calculate_cab_allocation(dc, context);</div><div class='add'>+	bool cache_cursor = false;</div><div class='add'>+</div><div class='add'>+	// Don't force p-state disallow -- can't block dummy p-state</div><div class='add'>+</div><div class='add'>+	// Update MALL_SEL register for each pipe (break down update_mall_sel call)</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_mall_sel) {</div><div class='add'>+			int cursor_size = hubp-&gt;curs_attr.pitch * hubp-&gt;curs_attr.height;</div><div class='add'>+</div><div class='add'>+			switch (hubp-&gt;curs_attr.color_format) {</div><div class='add'>+			case CURSOR_MODE_MONO:</div><div class='add'>+				cursor_size /= 2;</div><div class='add'>+				break;</div><div class='add'>+			case CURSOR_MODE_COLOR_1BIT_AND:</div><div class='add'>+			case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:</div><div class='add'>+			case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:</div><div class='add'>+				cursor_size *= 4;</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:</div><div class='add'>+			case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:</div><div class='add'>+			default:</div><div class='add'>+				cursor_size *= 8;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (cursor_size &gt; 16384)</div><div class='add'>+				cache_cursor = true;</div><div class='add'>+</div><div class='add'>+			if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+				hwss_add_hubp_update_mall_sel(seq_state, hubp, 1, false);</div><div class='add'>+			} else {</div><div class='add'>+				// MALL not supported with Stereo3D</div><div class='add'>+				uint32_t mall_sel = (num_ways &lt;= dc-&gt;caps.cache_num_ways &amp;&amp;</div><div class='add'>+					pipe-&gt;stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &amp;&amp;</div><div class='add'>+					pipe-&gt;plane_state-&gt;address.type != PLN_ADDR_TYPE_GRPH_STEREO &amp;&amp;</div><div class='add'>+					!pipe-&gt;plane_state-&gt;address.tmz_surface) ? 2 : 0;</div><div class='add'>+				hwss_add_hubp_update_mall_sel(seq_state, hubp, mall_sel, cache_cursor);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_prepare_subvp_buffering) {</div><div class='add'>+			if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)</div><div class='add'>+				hwss_add_hubp_prepare_subvp_buffering(seq_state, hubp, true);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='add'>+</div><div class='add'>+	if (!hubbub-&gt;funcs-&gt;verify_allow_pstate_change_high)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!hubbub-&gt;funcs-&gt;verify_allow_pstate_change_high(hubbub)) {</div><div class='add'>+		/* Attempt hardware workaround force recovery */</div><div class='add'>+		dcn401_hw_wa_force_recovery_sequence(dc, seq_state);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc,</div><div class='add'>+		struct block_sequence_state *seq_state)</div><div class='add'>+{</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;debug.recovery_enabled)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Step 1: Set HUBP_BLANK_EN=1 for all active pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx != NULL) {</div><div class='add'>+			hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+			if (hubp != NULL &amp;&amp; hubp-&gt;funcs-&gt;set_hubp_blank_en)</div><div class='add'>+				hwss_add_hubp_set_blank_en(seq_state, hubp, true);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 2: DCHUBBUB_GLOBAL_SOFT_RESET=1 */</div><div class='add'>+	hwss_add_hubbub_soft_reset(seq_state, dc-&gt;res_pool-&gt;hubbub, hubbub1_soft_reset, true);</div><div class='add'>+</div><div class='add'>+	/* Step 3: Set HUBP_DISABLE=1 for all active pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx != NULL) {</div><div class='add'>+			hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+			if (hubp != NULL &amp;&amp; hubp-&gt;funcs-&gt;hubp_disable_control)</div><div class='add'>+				hwss_add_hubp_disable_control(seq_state, hubp, true);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 4: Set HUBP_DISABLE=0 for all active pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx != NULL) {</div><div class='add'>+			hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+			if (hubp != NULL &amp;&amp; hubp-&gt;funcs-&gt;hubp_disable_control)</div><div class='add'>+				hwss_add_hubp_disable_control(seq_state, hubp, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Step 5: DCHUBBUB_GLOBAL_SOFT_RESET=0 */</div><div class='add'>+	hwss_add_hubbub_soft_reset(seq_state, dc-&gt;res_pool-&gt;hubbub, hubbub1_soft_reset, false);</div><div class='add'>+</div><div class='add'>+	/* Step 6: Set HUBP_BLANK_EN=0 for all active pipes */</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx != NULL) {</div><div class='add'>+			hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='add'>+			if (hubp != NULL &amp;&amp; hubp-&gt;funcs-&gt;set_hubp_blank_en)</div><div class='add'>+				hwss_add_hubp_set_blank_en(seq_state, hubp, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h<br/>new file mode 100644<br/>index 000000000000..f78162ab859b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h</a></div><div class='hunk'>@@ -0,0 +1,213 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_HWSS_DCN401_H__</div><div class='add'>+#define __DC_HWSS_DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "inc/core_types.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "dc_stream.h"</div><div class='add'>+#include "hw_sequencer_private.h"</div><div class='add'>+#include "hwss/hw_sequencer.h"</div><div class='add'>+#include "dcn401/dcn401_dccg.h"</div><div class='add'>+</div><div class='add'>+struct dc;</div><div class='add'>+</div><div class='add'>+enum ips_ono_state {</div><div class='add'>+	ONO_ON = 0,</div><div class='add'>+	ONO_ON_IN_PROGRESS = 1,</div><div class='add'>+	ONO_OFF = 2,</div><div class='add'>+	ONO_OFF_IN_PROGRESS = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ips_ono_region_state {</div><div class='add'>+	/**</div><div class='add'>+	 * @desire_pwr_state: desired power state based on configured value</div><div class='add'>+	 */</div><div class='add'>+	uint32_t desire_pwr_state;</div><div class='add'>+	/**</div><div class='add'>+	 * @current_pwr_state: current power gate status</div><div class='add'>+	 */</div><div class='add'>+	uint32_t current_pwr_state;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void dcn401_init_hw(struct dc *dc);</div><div class='add'>+</div><div class='add'>+bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,</div><div class='add'>+				const struct dc_plane_state *plane_state);</div><div class='add'>+bool dcn401_set_output_transfer_func(struct dc *dc,</div><div class='add'>+				struct pipe_ctx *pipe_ctx,</div><div class='add'>+				const struct dc_stream_state *stream);</div><div class='add'>+void dcn401_trigger_3dlut_dma_load(struct dc *dc,</div><div class='add'>+				struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,</div><div class='add'>+				unsigned int *tmds_div);</div><div class='add'>+enum dc_status dcn401_enable_stream_timing(</div><div class='add'>+				struct pipe_ctx *pipe_ctx,</div><div class='add'>+				struct dc_state *context,</div><div class='add'>+				struct dc *dc);</div><div class='add'>+void dcn401_enable_stream(struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn401_populate_mcm_luts(struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_cm2_func_luts mcm_luts,</div><div class='add'>+		bool lut_bank_a);</div><div class='add'>+void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);</div><div class='add'>+</div><div class='add'>+void dcn401_disable_link_output(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='add'>+		enum signal_type signal);</div><div class='add'>+</div><div class='add'>+void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable);</div><div class='add'>+</div><div class='add'>+void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc,</div><div class='add'>+		const struct pipe_ctx *top_pipe_to_program);</div><div class='add'>+</div><div class='add'>+void dcn401_prepare_bandwidth(struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void dcn401_optimize_bandwidth(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void dcn401_dmub_hw_control_lock(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		bool lock);</div><div class='add'>+void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);</div><div class='add'>+void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params);</div><div class='add'>+void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);</div><div class='add'>+void dcn401_hardware_release(struct dc *dc);</div><div class='add'>+void dcn401_update_odm(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *otg_master);</div><div class='add'>+void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);</div><div class='add'>+void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy);</div><div class='add'>+void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master);</div><div class='add'>+void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock);</div><div class='add'>+void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context);</div><div class='add'>+void dcn401_reset_back_end_for_pipe(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+void dcn401_reset_hw_ctx_wrap(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+void dcn401_program_pipe(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dc_state *context);</div><div class='add'>+void dcn401_program_pipe_sequence(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct block_sequence_state *seq_state);</div><div class='add'>+void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context);</div><div class='add'>+void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context);</div><div class='add'>+bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context);</div><div class='add'>+void dcn401_detect_pipe_changes(</div><div class='add'>+	struct dc_state *old_state,</div><div class='add'>+	struct dc_state *new_state,</div><div class='add'>+	struct pipe_ctx *old_pipe,</div><div class='add'>+	struct pipe_ctx *new_pipe);</div><div class='add'>+void dcn401_plane_atomic_power_down(struct dc *dc,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+void dcn401_plane_atomic_power_down_sequence(struct dc *dc,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+void dcn401_plane_atomic_disconnect_sequence(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+void dcn401_blank_pixel_data_sequence(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	bool blank,</div><div class='add'>+	struct block_sequence_state *seq_state);</div><div class='add'>+void dcn401_initialize_min_clocks(struct dc *dc);</div><div class='add'>+void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+</div><div class='add'>+void dcn401_program_all_writeback_pipes_in_tree_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		const struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_enable_writeback_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_writeback_info *wb_info,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		int mpcc_inst,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_disable_writeback_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_writeback_info *wb_info,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_update_writeback_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_writeback_info *wb_info,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_setup_gsl_group_as_lock_sequence(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		bool enable,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_disable_plane_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_post_unlock_reset_opp_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *opp_head,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable);</div><div class='add'>+</div><div class='add'>+void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+				 struct dc_state *context,</div><div class='add'>+				 struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_update_dchubp_dpp_sequence(struct dc *dc,</div><div class='add'>+				       struct pipe_ctx *pipe_ctx,</div><div class='add'>+				       struct dc_state *context,</div><div class='add'>+				       struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_update_mpcc_sequence(struct dc *dc,</div><div class='add'>+				struct pipe_ctx *pipe_ctx,</div><div class='add'>+				struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_wait_for_mpcc_disconnect_sequence(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct resource_pool *res_pool,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_HWSS_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c<br/>new file mode 100644<br/>index 000000000000..162096ce0bdf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c</a></div><div class='hunk'>@@ -0,0 +1,177 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dce110/dce110_hwseq.h"</div><div class='add'>+#include "dcn10/dcn10_hwseq.h"</div><div class='add'>+#include "dcn20/dcn20_hwseq.h"</div><div class='add'>+#include "dcn21/dcn21_hwseq.h"</div><div class='add'>+#include "dcn30/dcn30_hwseq.h"</div><div class='add'>+#include "dcn31/dcn31_hwseq.h"</div><div class='add'>+#include "dcn32/dcn32_hwseq.h"</div><div class='add'>+#include "dcn35/dcn35_hwseq.h"</div><div class='add'>+#include "dcn401/dcn401_hwseq.h"</div><div class='add'>+#include "dcn401_init.h"</div><div class='add'>+</div><div class='add'>+static const struct hw_sequencer_funcs dcn401_funcs = {</div><div class='add'>+	.program_gamut_remap = dcn401_program_gamut_remap,</div><div class='add'>+	.init_hw = dcn401_init_hw,</div><div class='add'>+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='add'>+	.apply_ctx_for_surface = NULL,</div><div class='add'>+	.program_front_end_for_ctx = dcn401_program_front_end_for_ctx,</div><div class='add'>+	.clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,</div><div class='add'>+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='add'>+	.post_unlock_program_front_end = dcn401_post_unlock_program_front_end,</div><div class='add'>+	.update_plane_addr = dcn20_update_plane_addr,</div><div class='add'>+	.update_dchub = dcn10_update_dchub,</div><div class='add'>+	.update_pending_status = dcn10_update_pending_status,</div><div class='add'>+	.program_output_csc = dcn20_program_output_csc,</div><div class='add'>+	.trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load,</div><div class='add'>+	.enable_accelerated_mode = dce110_enable_accelerated_mode,</div><div class='add'>+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,</div><div class='add'>+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,</div><div class='add'>+	.update_info_frame = dcn31_update_info_frame,</div><div class='add'>+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,</div><div class='add'>+	.enable_stream = dcn401_enable_stream,</div><div class='add'>+	.disable_stream = dce110_disable_stream,</div><div class='add'>+	.unblank_stream = dcn401_unblank_stream,</div><div class='add'>+	.blank_stream = dce110_blank_stream,</div><div class='add'>+	.enable_audio_stream = dce110_enable_audio_stream,</div><div class='add'>+	.disable_audio_stream = dce110_disable_audio_stream,</div><div class='add'>+	.disable_plane = dcn20_disable_plane,</div><div class='add'>+	.disable_plane_sequence = dcn401_disable_plane_sequence,</div><div class='add'>+	.pipe_control_lock = dcn20_pipe_control_lock,</div><div class='add'>+	.interdependent_update_lock = dcn401_interdependent_update_lock,</div><div class='add'>+	.cursor_lock = dcn10_cursor_lock,</div><div class='add'>+	.prepare_bandwidth = dcn401_prepare_bandwidth,</div><div class='add'>+	.optimize_bandwidth = dcn401_optimize_bandwidth,</div><div class='add'>+	.update_bandwidth = dcn401_update_bandwidth,</div><div class='add'>+	.set_drr = dcn10_set_drr,</div><div class='add'>+	.get_position = dcn10_get_position,</div><div class='add'>+	.set_static_screen_control = dcn31_set_static_screen_control,</div><div class='add'>+	.setup_stereo = dcn10_setup_stereo,</div><div class='add'>+	.set_avmute = dcn30_set_avmute,</div><div class='add'>+	.log_hw_state = dcn10_log_hw_state,</div><div class='add'>+	.get_hw_state = dcn10_get_hw_state,</div><div class='add'>+	.clear_status_bits = dcn10_clear_status_bits,</div><div class='add'>+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='add'>+	.wait_for_mpcc_disconnect_sequence = dcn401_wait_for_mpcc_disconnect_sequence,</div><div class='add'>+	.edp_backlight_control = dce110_edp_backlight_control,</div><div class='add'>+	.edp_power_control = dce110_edp_power_control,</div><div class='add'>+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,</div><div class='add'>+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,</div><div class='add'>+	.set_cursor_position = dcn401_set_cursor_position,</div><div class='add'>+	.set_cursor_attribute = dcn10_set_cursor_attribute,</div><div class='add'>+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,</div><div class='add'>+	.abort_cursor_offload_update = dcn35_abort_cursor_offload_update,</div><div class='add'>+	.begin_cursor_offload_update = dcn35_begin_cursor_offload_update,</div><div class='add'>+	.commit_cursor_offload_update = dcn35_commit_cursor_offload_update,</div><div class='add'>+	.update_cursor_offload_pipe = dcn401_update_cursor_offload_pipe,</div><div class='add'>+	.notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update,</div><div class='add'>+	.program_cursor_offload_now = dcn35_program_cursor_offload_now,</div><div class='add'>+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,</div><div class='add'>+	.set_clock = dcn10_set_clock,</div><div class='add'>+	.get_clock = dcn10_get_clock,</div><div class='add'>+	.program_triplebuffer = dcn20_program_triple_buffer,</div><div class='add'>+	.enable_writeback = dcn30_enable_writeback,</div><div class='add'>+	.disable_writeback = dcn30_disable_writeback,</div><div class='add'>+	.update_writeback = dcn30_update_writeback,</div><div class='add'>+	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='add'>+	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='add'>+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='add'>+	.init_sys_ctx = dcn20_init_sys_ctx,</div><div class='add'>+	.init_vm_ctx = dcn20_init_vm_ctx,</div><div class='add'>+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,</div><div class='add'>+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='add'>+	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='add'>+	.apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations,</div><div class='add'>+	.does_plane_fit_in_mall = NULL,</div><div class='add'>+	.set_backlight_level = dcn31_set_backlight_level,</div><div class='add'>+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='add'>+	.hardware_release = dcn401_hardware_release,</div><div class='add'>+	.set_pipe = dcn21_set_pipe,</div><div class='add'>+	.enable_lvds_link_output = dce110_enable_lvds_link_output,</div><div class='add'>+	.enable_tmds_link_output = dce110_enable_tmds_link_output,</div><div class='add'>+	.enable_dp_link_output = dce110_enable_dp_link_output,</div><div class='add'>+	.disable_link_output = dcn401_disable_link_output,</div><div class='add'>+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,</div><div class='add'>+	.get_dcc_en_bits = dcn10_get_dcc_en_bits,</div><div class='add'>+	.enable_phantom_streams = dcn32_enable_phantom_streams,</div><div class='add'>+	.disable_phantom_streams = dcn32_disable_phantom_streams,</div><div class='add'>+	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='add'>+	.update_phantom_vp_position = dcn32_update_phantom_vp_position,</div><div class='add'>+	.update_dsc_pg = dcn32_update_dsc_pg,</div><div class='add'>+	.apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,</div><div class='add'>+	.wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation,</div><div class='add'>+	.is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,</div><div class='add'>+	.dmub_hw_control_lock = dcn401_dmub_hw_control_lock,</div><div class='add'>+	.fams2_update_config = dcn401_fams2_update_config,</div><div class='add'>+	.dmub_hw_control_lock_fast = dcn401_dmub_hw_control_lock_fast,</div><div class='add'>+	.program_outstanding_updates = dcn401_program_outstanding_updates,</div><div class='add'>+	.wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates,</div><div class='add'>+	.detect_pipe_changes = dcn401_detect_pipe_changes,</div><div class='add'>+	.enable_plane = dcn20_enable_plane,</div><div class='add'>+	.enable_plane_sequence = dcn401_enable_plane_sequence,</div><div class='add'>+	.update_dchubp_dpp = dcn20_update_dchubp_dpp,</div><div class='add'>+	.update_dchubp_dpp_sequence = dcn401_update_dchubp_dpp_sequence,</div><div class='add'>+	.post_unlock_reset_opp = dcn20_post_unlock_reset_opp,</div><div class='add'>+	.post_unlock_reset_opp_sequence = dcn401_post_unlock_reset_opp_sequence,</div><div class='add'>+	.get_underflow_debug_data = dcn30_get_underflow_debug_data,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwseq_private_funcs dcn401_private_funcs = {</div><div class='add'>+	.init_pipes = dcn10_init_pipes,</div><div class='add'>+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='add'>+	.plane_atomic_disconnect_sequence = dcn401_plane_atomic_disconnect_sequence,</div><div class='add'>+	.update_mpcc = dcn20_update_mpcc,</div><div class='add'>+	.update_mpcc_sequence = dcn401_update_mpcc_sequence,</div><div class='add'>+	.set_input_transfer_func = dcn32_set_input_transfer_func,</div><div class='add'>+	.set_output_transfer_func = dcn401_set_output_transfer_func,</div><div class='add'>+	.power_down = dce110_power_down,</div><div class='add'>+	.enable_display_power_gating = dcn10_dummy_display_power_gating,</div><div class='add'>+	.blank_pixel_data = dcn20_blank_pixel_data,</div><div class='add'>+	.blank_pixel_data_sequence = dcn401_blank_pixel_data_sequence,</div><div class='add'>+	.reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap,</div><div class='add'>+	.enable_stream_timing = dcn401_enable_stream_timing,</div><div class='add'>+	.edp_backlight_control = dce110_edp_backlight_control,</div><div class='add'>+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,</div><div class='add'>+	.setup_vupdate_interrupt_sequence = dcn401_setup_vupdate_interrupt_sequence,</div><div class='add'>+	.did_underflow_occur = dcn10_did_underflow_occur,</div><div class='add'>+	.init_blank = dcn32_init_blank,</div><div class='add'>+	.disable_vga = dcn20_disable_vga,</div><div class='add'>+	.bios_golden_init = dcn10_bios_golden_init,</div><div class='add'>+	.plane_atomic_disable = dcn20_plane_atomic_disable,</div><div class='add'>+	.plane_atomic_power_down = dcn401_plane_atomic_power_down,</div><div class='add'>+	.plane_atomic_power_down_sequence = dcn401_plane_atomic_power_down_sequence,</div><div class='add'>+	.enable_power_gating_plane = dcn32_enable_power_gating_plane,</div><div class='add'>+	.hubp_pg_control = dcn32_hubp_pg_control,</div><div class='add'>+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,</div><div class='add'>+	.program_all_writeback_pipes_in_tree_sequence = dcn401_program_all_writeback_pipes_in_tree_sequence,</div><div class='add'>+	.update_odm = dcn401_update_odm,</div><div class='add'>+	.update_odm_sequence = dcn401_update_odm_sequence,</div><div class='add'>+	.dsc_pg_control = dcn32_dsc_pg_control,</div><div class='add'>+	.dsc_pg_status = dcn32_dsc_pg_status,</div><div class='add'>+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,</div><div class='add'>+	.set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence,</div><div class='add'>+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,</div><div class='add'>+	.verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence,</div><div class='add'>+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,</div><div class='add'>+	.dccg_init = dcn20_dccg_init,</div><div class='add'>+	.set_mcm_luts = dcn401_set_mcm_luts,</div><div class='add'>+	.program_mall_pipe_config = dcn32_program_mall_pipe_config,</div><div class='add'>+	.program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence,</div><div class='add'>+	.update_mall_sel = dcn32_update_mall_sel,</div><div class='add'>+	.calculate_dccg_k1_k2_values = NULL,</div><div class='add'>+	.apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,</div><div class='add'>+	.reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe,</div><div class='add'>+	.populate_mcm_luts = NULL,</div><div class='add'>+	.perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock,</div><div class='add'>+	.program_pipe_sequence = dcn401_program_pipe_sequence,</div><div class='add'>+	.dc_ip_request_cntl = dcn401_dc_ip_request_cntl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn401_hw_sequencer_init_functions(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	dc-&gt;hwss = dcn401_funcs;</div><div class='add'>+	dc-&gt;hwseq-&gt;funcs = dcn401_private_funcs;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h<br/>new file mode 100644<br/>index 000000000000..59e6d8525e19<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.h</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_DCN401_INIT_H__</div><div class='add'>+#define __DC_DCN401_INIT_H__</div><div class='add'>+</div><div class='add'>+struct dc;</div><div class='add'>+</div><div class='add'>+void dcn401_hw_sequencer_init_functions(struct dc *dc);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_DCN401_INIT_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h<br/>index f89f205e42a1..8ed9eea40c56 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h</a></div><div class='hunk'>@@ -31,6 +31,8 @@</div><div class='ctx'> #include "inc/hw/opp.h"</div><div class='ctx'> #include "inc/hw/link_encoder.h"</div><div class='ctx'> #include "inc/core_status.h"</div><div class='add'>+#include "inc/hw/hw_shared.h"</div><div class='add'>+#include "dsc/dsc.h"</div><div class='ctx'> </div><div class='ctx'> struct pipe_ctx;</div><div class='ctx'> struct dc_state;</div><div class='hunk'>@@ -46,6 +48,10 @@ struct dce_hwseq;</div><div class='ctx'> struct link_resource;</div><div class='ctx'> struct dc_dmub_cmd;</div><div class='ctx'> struct pg_block_update;</div><div class='add'>+struct drr_params;</div><div class='add'>+struct dc_underflow_debug_data;</div><div class='add'>+struct dsc_optc_config;</div><div class='add'>+struct vm_system_aperture_param;</div><div class='ctx'> </div><div class='ctx'> struct subvp_pipe_control_lock_fast_params {</div><div class='ctx'> 	struct dc *dc;</div><div class='hunk'>@@ -60,7 +66,7 @@ struct pipe_control_lock_params {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct set_flip_control_gsl_params {</div><div class='del'>-	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	struct hubp *hubp;</div><div class='ctx'> 	bool flip_immediate;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -141,6 +147,592 @@ struct subvp_save_surf_addr {</div><div class='ctx'> 	uint8_t subvp_index;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct wait_for_dcc_meta_propagation_params {</div><div class='add'>+	const struct dc *dc;</div><div class='add'>+	const struct pipe_ctx *top_pipe_to_program;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_hw_control_lock_fast_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	bool is_required;</div><div class='add'>+	bool lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_surface_config_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	enum surface_pixel_format format;</div><div class='add'>+	struct dc_tiling_info *tiling_info;</div><div class='add'>+	struct plane_size plane_size;</div><div class='add'>+	enum dc_rotation_angle rotation;</div><div class='add'>+	struct dc_plane_dcc_param *dcc;</div><div class='add'>+	bool horizontal_mirror;</div><div class='add'>+	int compat_level;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_mcache_id_and_split_coordinate {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs *mcache_regs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_cursor_update_now_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_wait_pipe_read_start_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct apply_update_flags_for_phantom_params {</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct update_phantom_vp_position_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	struct dc_state *context;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_odm_combine_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	int opp_inst[MAX_PIPES];</div><div class='add'>+	int opp_head_count;</div><div class='add'>+	int odm_slice_width;</div><div class='add'>+	int last_odm_slice_width;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_odm_bypass_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	const struct dc_crtc_timing *timing;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_pipe_clock_control_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_program_left_edge_extra_pixel_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	enum dc_pixel_encoding pixel_encoding;</div><div class='add'>+	bool is_otg_master;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dccg_set_dto_dscclk_params {</div><div class='add'>+	struct dccg *dccg;</div><div class='add'>+	int inst;</div><div class='add'>+	int num_slices_h;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_set_config_params {</div><div class='add'>+	struct display_stream_compressor *dsc;</div><div class='add'>+	struct dsc_config *dsc_cfg;</div><div class='add'>+	struct dsc_optc_config *dsc_optc_cfg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_enable_params {</div><div class='add'>+	struct display_stream_compressor *dsc;</div><div class='add'>+	int opp_inst;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_set_dsc_config_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	struct dsc_optc_config *dsc_optc_cfg;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_disconnect_params {</div><div class='add'>+	struct display_stream_compressor *dsc;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_read_state_params {</div><div class='add'>+	struct display_stream_compressor *dsc;</div><div class='add'>+	struct dcn_dsc_state *dsc_state;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_calculate_and_set_config_params {</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	struct dsc_optc_config dsc_optc_cfg;</div><div class='add'>+	bool enable;</div><div class='add'>+	int opp_cnt;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_enable_with_opp_params {</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_tg_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	struct dc_state *context;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_program_global_sync_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	int vready_offset;</div><div class='add'>+	unsigned int vstartup_lines;</div><div class='add'>+	unsigned int vupdate_offset_pixels;</div><div class='add'>+	unsigned int vupdate_vupdate_width_pixels;</div><div class='add'>+	unsigned int pstate_keepout_start_lines;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_wait_for_state_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	enum crtc_state state;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_set_vtg_params_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	struct dc_crtc_timing *timing;</div><div class='add'>+	bool program_fp2;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_set_gsl_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	struct gsl_params gsl;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_set_gsl_source_select_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	int group_idx;</div><div class='add'>+	uint32_t gsl_ready_signal;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct setup_vupdate_interrupt_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_setup_vertical_interrupt2_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	int start_line;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_set_hdr_multiplier_params {</div><div class='add'>+	struct dpp *dpp;</div><div class='add'>+	uint32_t hw_mult;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_det_size_params {</div><div class='add'>+	struct hubbub *hubbub;</div><div class='add'>+	unsigned int hubp_inst;</div><div class='add'>+	unsigned int det_buffer_size_kb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_det_segments_params {</div><div class='add'>+	struct hubbub *hubbub;</div><div class='add'>+	unsigned int hubp_inst;</div><div class='add'>+	unsigned int det_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct update_dchubp_dpp_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	struct dc_state *context;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_set_dyn_expansion_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	enum dc_color_space color_space;</div><div class='add'>+	enum dc_color_depth color_depth;</div><div class='add'>+	enum signal_type signal;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_program_fmt_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	struct bit_depth_reduction_params *fmt_bit_depth;</div><div class='add'>+	struct clamping_and_pixel_encoding_params *clamping;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_program_bit_depth_reduction_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	bool use_default_params;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_set_disp_pattern_generator_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	enum controller_dp_test_pattern test_pattern;</div><div class='add'>+	enum controller_dp_color_space color_space;</div><div class='add'>+	enum dc_color_depth color_depth;</div><div class='add'>+	struct tg_color solid_color;</div><div class='add'>+	bool use_solid_color;</div><div class='add'>+	int width;</div><div class='add'>+	int height;</div><div class='add'>+	int offset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_abm_pipe_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_abm_level_params {</div><div class='add'>+	struct abm *abm;</div><div class='add'>+	unsigned int abm_level;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_abm_immediate_disable_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_disp_pattern_generator_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	enum controller_dp_test_pattern test_pattern;</div><div class='add'>+	enum controller_dp_color_space color_space;</div><div class='add'>+	enum dc_color_depth color_depth;</div><div class='add'>+	const struct tg_color *solid_color;</div><div class='add'>+	int width;</div><div class='add'>+	int height;</div><div class='add'>+	int offset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_update_blending_params {</div><div class='add'>+	struct mpc *mpc;</div><div class='add'>+	struct mpcc_blnd_cfg blnd_cfg;</div><div class='add'>+	int mpcc_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_assert_idle_mpcc_params {</div><div class='add'>+	struct mpc *mpc;</div><div class='add'>+	int mpcc_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_insert_plane_params {</div><div class='add'>+	struct mpc *mpc;</div><div class='add'>+	struct mpc_tree *mpc_tree_params;</div><div class='add'>+	struct mpcc_blnd_cfg blnd_cfg;</div><div class='add'>+	struct mpcc_sm_cfg *sm_cfg;</div><div class='add'>+	struct mpcc *insert_above_mpcc;</div><div class='add'>+	int dpp_id;</div><div class='add'>+	int mpcc_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_remove_mpcc_params {</div><div class='add'>+	struct mpc *mpc;</div><div class='add'>+	struct mpc_tree *mpc_tree_params;</div><div class='add'>+	struct mpcc *mpcc_to_remove;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct opp_set_mpcc_disconnect_pending_params {</div><div class='add'>+	struct output_pixel_processor *opp;</div><div class='add'>+	int mpcc_inst;</div><div class='add'>+	bool pending;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_set_optimized_required_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	bool optimized_required;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_disconnect_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubbub_force_pstate_change_control_params {</div><div class='add'>+	struct hubbub *hubbub;</div><div class='add'>+	bool enable;</div><div class='add'>+	bool wait;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_enable_crtc_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_wait_flip_pending_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	unsigned int timeout_us;</div><div class='add'>+	unsigned int polling_interval_us;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_wait_double_buffer_pending_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	unsigned int timeout_us;</div><div class='add'>+	unsigned int polling_interval_us;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct update_force_pstate_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct dc_state *context;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubbub_apply_dedcn21_147_wa_params {</div><div class='add'>+	struct hubbub *hubbub;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubbub_allow_self_refresh_control_params {</div><div class='add'>+	struct hubbub *hubbub;</div><div class='add'>+	bool allow;</div><div class='add'>+	bool *disallow_self_refresh_applied;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tg_get_frame_count_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+	unsigned int *frame_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_set_dwb_mux_params {</div><div class='add'>+	struct mpc *mpc;</div><div class='add'>+	int dwb_id;</div><div class='add'>+	int mpcc_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_disable_dwb_mux_params {</div><div class='add'>+	struct mpc *mpc;</div><div class='add'>+	unsigned int dwb_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcif_wb_config_buf_params {</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+	struct mcif_buf_params *mcif_buf_params;</div><div class='add'>+	unsigned int dest_height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcif_wb_config_arb_params {</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+	struct mcif_arb_params *mcif_arb_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcif_wb_enable_params {</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcif_wb_disable_params {</div><div class='add'>+	struct mcif_wb *mcif_wb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dwbc_enable_params {</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+	struct dc_dwb_params *dwb_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dwbc_disable_params {</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dwbc_update_params {</div><div class='add'>+	struct dwbc *dwb;</div><div class='add'>+	struct dc_dwb_params *dwb_params;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_update_mall_sel_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	uint32_t mall_sel;</div><div class='add'>+	bool cache_cursor;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_prepare_subvp_buffering_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_set_blank_en_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_disable_control_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	bool disable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubbub_soft_reset_params {</div><div class='add'>+	struct hubbub *hubbub;</div><div class='add'>+	void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset);</div><div class='add'>+	bool reset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_clk_cntl_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_init_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_set_vm_system_aperture_settings_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	//struct vm_system_aperture_param apt;</div><div class='add'>+	PHYSICAL_ADDRESS_LOC sys_default;</div><div class='add'>+	PHYSICAL_ADDRESS_LOC sys_low;</div><div class='add'>+	PHYSICAL_ADDRESS_LOC sys_high;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_set_flip_int_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_dppclk_control_params {</div><div class='add'>+	struct dpp *dpp;</div><div class='add'>+	bool dppclk_div;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct disable_phantom_crtc_params {</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_pg_control_params {</div><div class='add'>+	struct dce_hwseq *hws;</div><div class='add'>+	unsigned int dpp_inst;</div><div class='add'>+	bool power_on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_pg_control_params {</div><div class='add'>+	struct dce_hwseq *hws;</div><div class='add'>+	unsigned int hubp_inst;</div><div class='add'>+	bool power_on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_reset_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_reset_params {</div><div class='add'>+	struct dpp *dpp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_root_clock_control_params {</div><div class='add'>+	struct dce_hwseq *hws;</div><div class='add'>+	unsigned int dpp_inst;</div><div class='add'>+	bool clock_on;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dc_ip_request_cntl_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_pg_status_params {</div><div class='add'>+	struct dce_hwseq *hws;</div><div class='add'>+	int dsc_inst;</div><div class='add'>+	bool is_ungated;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_wait_disconnect_pending_clear_params {</div><div class='add'>+	struct display_stream_compressor *dsc;</div><div class='add'>+	bool *is_ungated;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_disable_params {</div><div class='add'>+	struct display_stream_compressor *dsc;</div><div class='add'>+	bool *is_ungated;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dccg_set_ref_dscclk_params {</div><div class='add'>+	struct dccg *dccg;</div><div class='add'>+	int dsc_inst;</div><div class='add'>+	bool *is_ungated;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dccg_update_dpp_dto_params {</div><div class='add'>+	struct dccg *dccg;</div><div class='add'>+	int dpp_inst;</div><div class='add'>+	int dppclk_khz;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_vtg_sel_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	uint32_t otg_inst;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_setup2_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set *hubp_regs;</div><div class='add'>+	union dml2_global_sync_programming *global_sync;</div><div class='add'>+	struct dc_crtc_timing *timing;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_setup_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	struct _vcs_dpi_display_dlg_regs_st *dlg_regs;</div><div class='add'>+	struct _vcs_dpi_display_ttu_regs_st *ttu_regs;</div><div class='add'>+	struct _vcs_dpi_display_rq_regs_st *rq_regs;</div><div class='add'>+	struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_set_unbounded_requesting_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	bool unbounded_req;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_setup_interdependent2_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set *hubp_regs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_setup_interdependent_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	struct _vcs_dpi_display_dlg_regs_st *dlg_regs;</div><div class='add'>+	struct _vcs_dpi_display_ttu_regs_st *ttu_regs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_set_cursor_matrix_params {</div><div class='add'>+	struct dpp *dpp;</div><div class='add'>+	enum dc_color_space color_space;</div><div class='add'>+	struct dc_csc_transform *cursor_csc_color_matrix;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_update_mpcc_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dpp_set_scaler_params {</div><div class='add'>+	struct dpp *dpp;</div><div class='add'>+	const struct scaler_data *scl_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_mem_program_viewport_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	const struct rect *viewport;</div><div class='add'>+	const struct rect *viewport_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_program_mcache_id_and_split_coordinate_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	struct mcache_regs_struct *mcache_regs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct abort_cursor_offload_update_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_cursor_attribute_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_cursor_position_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct set_cursor_sdr_white_level_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct program_output_csc_params {</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	enum dc_color_space colorspace;</div><div class='add'>+	uint16_t *matrix;</div><div class='add'>+	int opp_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_set_blank_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+	bool blank;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct phantom_hubp_post_enable_params {</div><div class='add'>+	struct hubp *hubp;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union block_sequence_params {</div><div class='ctx'> 	struct update_plane_addr_params update_plane_addr_params;</div><div class='ctx'> 	struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params;</div><div class='hunk'>@@ -159,6 +751,109 @@ union block_sequence_params {</div><div class='ctx'> 	struct set_output_csc_params set_output_csc_params;</div><div class='ctx'> 	struct set_ocsc_default_params set_ocsc_default_params;</div><div class='ctx'> 	struct subvp_save_surf_addr subvp_save_surf_addr;</div><div class='add'>+	struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params;</div><div class='add'>+	struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params;</div><div class='add'>+	struct program_surface_config_params program_surface_config_params;</div><div class='add'>+	struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate;</div><div class='add'>+	struct program_cursor_update_now_params program_cursor_update_now_params;</div><div class='add'>+	struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params;</div><div class='add'>+	struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params;</div><div class='add'>+	struct update_phantom_vp_position_params update_phantom_vp_position_params;</div><div class='add'>+	struct set_odm_combine_params set_odm_combine_params;</div><div class='add'>+	struct set_odm_bypass_params set_odm_bypass_params;</div><div class='add'>+	struct opp_pipe_clock_control_params opp_pipe_clock_control_params;</div><div class='add'>+	struct opp_program_left_edge_extra_pixel_params opp_program_left_edge_extra_pixel_params;</div><div class='add'>+	struct dccg_set_dto_dscclk_params dccg_set_dto_dscclk_params;</div><div class='add'>+	struct dsc_set_config_params dsc_set_config_params;</div><div class='add'>+	struct dsc_enable_params dsc_enable_params;</div><div class='add'>+	struct tg_set_dsc_config_params tg_set_dsc_config_params;</div><div class='add'>+	struct dsc_disconnect_params dsc_disconnect_params;</div><div class='add'>+	struct dsc_read_state_params dsc_read_state_params;</div><div class='add'>+	struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params;</div><div class='add'>+	struct dsc_enable_with_opp_params dsc_enable_with_opp_params;</div><div class='add'>+	struct program_tg_params program_tg_params;</div><div class='add'>+	struct tg_program_global_sync_params tg_program_global_sync_params;</div><div class='add'>+	struct tg_wait_for_state_params tg_wait_for_state_params;</div><div class='add'>+	struct tg_set_vtg_params_params tg_set_vtg_params_params;</div><div class='add'>+	struct tg_setup_vertical_interrupt2_params tg_setup_vertical_interrupt2_params;</div><div class='add'>+	struct dpp_set_hdr_multiplier_params dpp_set_hdr_multiplier_params;</div><div class='add'>+	struct tg_set_gsl_params tg_set_gsl_params;</div><div class='add'>+	struct tg_set_gsl_source_select_params tg_set_gsl_source_select_params;</div><div class='add'>+	struct setup_vupdate_interrupt_params setup_vupdate_interrupt_params;</div><div class='add'>+	struct program_det_size_params program_det_size_params;</div><div class='add'>+	struct program_det_segments_params program_det_segments_params;</div><div class='add'>+	struct update_dchubp_dpp_params update_dchubp_dpp_params;</div><div class='add'>+	struct opp_set_dyn_expansion_params opp_set_dyn_expansion_params;</div><div class='add'>+	struct opp_program_fmt_params opp_program_fmt_params;</div><div class='add'>+	struct opp_program_bit_depth_reduction_params opp_program_bit_depth_reduction_params;</div><div class='add'>+	struct opp_set_disp_pattern_generator_params opp_set_disp_pattern_generator_params;</div><div class='add'>+	struct set_abm_pipe_params set_abm_pipe_params;</div><div class='add'>+	struct set_abm_level_params set_abm_level_params;</div><div class='add'>+	struct set_abm_immediate_disable_params set_abm_immediate_disable_params;</div><div class='add'>+	struct set_disp_pattern_generator_params set_disp_pattern_generator_params;</div><div class='add'>+	struct mpc_remove_mpcc_params mpc_remove_mpcc_params;</div><div class='add'>+	struct opp_set_mpcc_disconnect_pending_params opp_set_mpcc_disconnect_pending_params;</div><div class='add'>+	struct dc_set_optimized_required_params dc_set_optimized_required_params;</div><div class='add'>+	struct hubp_disconnect_params hubp_disconnect_params;</div><div class='add'>+	struct hubbub_force_pstate_change_control_params hubbub_force_pstate_change_control_params;</div><div class='add'>+	struct tg_enable_crtc_params tg_enable_crtc_params;</div><div class='add'>+	struct hubp_wait_flip_pending_params hubp_wait_flip_pending_params;</div><div class='add'>+	struct tg_wait_double_buffer_pending_params tg_wait_double_buffer_pending_params;</div><div class='add'>+	struct update_force_pstate_params update_force_pstate_params;</div><div class='add'>+	struct hubbub_apply_dedcn21_147_wa_params hubbub_apply_dedcn21_147_wa_params;</div><div class='add'>+	struct hubbub_allow_self_refresh_control_params hubbub_allow_self_refresh_control_params;</div><div class='add'>+	struct tg_get_frame_count_params tg_get_frame_count_params;</div><div class='add'>+	struct mpc_set_dwb_mux_params mpc_set_dwb_mux_params;</div><div class='add'>+	struct mpc_disable_dwb_mux_params mpc_disable_dwb_mux_params;</div><div class='add'>+	struct mcif_wb_config_buf_params mcif_wb_config_buf_params;</div><div class='add'>+	struct mcif_wb_config_arb_params mcif_wb_config_arb_params;</div><div class='add'>+	struct mcif_wb_enable_params mcif_wb_enable_params;</div><div class='add'>+	struct mcif_wb_disable_params mcif_wb_disable_params;</div><div class='add'>+	struct dwbc_enable_params dwbc_enable_params;</div><div class='add'>+	struct dwbc_disable_params dwbc_disable_params;</div><div class='add'>+	struct dwbc_update_params dwbc_update_params;</div><div class='add'>+	struct hubp_update_mall_sel_params hubp_update_mall_sel_params;</div><div class='add'>+	struct hubp_prepare_subvp_buffering_params hubp_prepare_subvp_buffering_params;</div><div class='add'>+	struct hubp_set_blank_en_params hubp_set_blank_en_params;</div><div class='add'>+	struct hubp_disable_control_params hubp_disable_control_params;</div><div class='add'>+	struct hubbub_soft_reset_params hubbub_soft_reset_params;</div><div class='add'>+	struct hubp_clk_cntl_params hubp_clk_cntl_params;</div><div class='add'>+	struct hubp_init_params hubp_init_params;</div><div class='add'>+	struct hubp_set_vm_system_aperture_settings_params hubp_set_vm_system_aperture_settings_params;</div><div class='add'>+	struct hubp_set_flip_int_params hubp_set_flip_int_params;</div><div class='add'>+	struct dpp_dppclk_control_params dpp_dppclk_control_params;</div><div class='add'>+	struct disable_phantom_crtc_params disable_phantom_crtc_params;</div><div class='add'>+	struct dpp_pg_control_params dpp_pg_control_params;</div><div class='add'>+	struct hubp_pg_control_params hubp_pg_control_params;</div><div class='add'>+	struct hubp_reset_params hubp_reset_params;</div><div class='add'>+	struct dpp_reset_params dpp_reset_params;</div><div class='add'>+	struct dpp_root_clock_control_params dpp_root_clock_control_params;</div><div class='add'>+	struct dc_ip_request_cntl_params dc_ip_request_cntl_params;</div><div class='add'>+	struct dsc_pg_status_params dsc_pg_status_params;</div><div class='add'>+	struct dsc_wait_disconnect_pending_clear_params dsc_wait_disconnect_pending_clear_params;</div><div class='add'>+	struct dsc_disable_params dsc_disable_params;</div><div class='add'>+	struct dccg_set_ref_dscclk_params dccg_set_ref_dscclk_params;</div><div class='add'>+	struct dccg_update_dpp_dto_params dccg_update_dpp_dto_params;</div><div class='add'>+	struct hubp_vtg_sel_params hubp_vtg_sel_params;</div><div class='add'>+	struct hubp_setup2_params hubp_setup2_params;</div><div class='add'>+	struct hubp_setup_params hubp_setup_params;</div><div class='add'>+	struct hubp_set_unbounded_requesting_params hubp_set_unbounded_requesting_params;</div><div class='add'>+	struct hubp_setup_interdependent2_params hubp_setup_interdependent2_params;</div><div class='add'>+	struct hubp_setup_interdependent_params hubp_setup_interdependent_params;</div><div class='add'>+	struct dpp_set_cursor_matrix_params dpp_set_cursor_matrix_params;</div><div class='add'>+	struct mpc_update_mpcc_params mpc_update_mpcc_params;</div><div class='add'>+	struct mpc_update_blending_params mpc_update_blending_params;</div><div class='add'>+	struct mpc_assert_idle_mpcc_params mpc_assert_idle_mpcc_params;</div><div class='add'>+	struct mpc_insert_plane_params mpc_insert_plane_params;</div><div class='add'>+	struct dpp_set_scaler_params dpp_set_scaler_params;</div><div class='add'>+	struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params;</div><div class='add'>+	struct abort_cursor_offload_update_params abort_cursor_offload_update_params;</div><div class='add'>+	struct set_cursor_attribute_params set_cursor_attribute_params;</div><div class='add'>+	struct set_cursor_position_params set_cursor_position_params;</div><div class='add'>+	struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params;</div><div class='add'>+	struct program_output_csc_params program_output_csc_params;</div><div class='add'>+	struct hubp_set_blank_params hubp_set_blank_params;</div><div class='add'>+	struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum block_sequence_func {</div><div class='hunk'>@@ -174,11 +869,113 @@ enum block_sequence_func {</div><div class='ctx'> 	DPP_SETUP_DPP,</div><div class='ctx'> 	DPP_PROGRAM_BIAS_AND_SCALE,</div><div class='ctx'> 	DPP_SET_OUTPUT_TRANSFER_FUNC,</div><div class='add'>+	DPP_SET_HDR_MULTIPLIER,</div><div class='ctx'> 	MPC_UPDATE_VISUAL_CONFIRM,</div><div class='ctx'> 	MPC_POWER_ON_MPC_MEM_PWR,</div><div class='ctx'> 	MPC_SET_OUTPUT_CSC,</div><div class='ctx'> 	MPC_SET_OCSC_DEFAULT,</div><div class='ctx'> 	DMUB_SUBVP_SAVE_SURF_ADDR,</div><div class='add'>+	HUBP_WAIT_FOR_DCC_META_PROP,</div><div class='add'>+	DMUB_HW_CONTROL_LOCK_FAST,</div><div class='add'>+	HUBP_PROGRAM_SURFACE_CONFIG,</div><div class='add'>+	HUBP_PROGRAM_MCACHE_ID,</div><div class='add'>+	PROGRAM_CURSOR_UPDATE_NOW,</div><div class='add'>+	HUBP_WAIT_PIPE_READ_START,</div><div class='add'>+	HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM,</div><div class='add'>+	HWS_UPDATE_PHANTOM_VP_POSITION,</div><div class='add'>+	OPTC_SET_ODM_COMBINE,</div><div class='add'>+	OPTC_SET_ODM_BYPASS,</div><div class='add'>+	OPP_PIPE_CLOCK_CONTROL,</div><div class='add'>+	OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL,</div><div class='add'>+	DCCG_SET_DTO_DSCCLK,</div><div class='add'>+	DSC_SET_CONFIG,</div><div class='add'>+	DSC_ENABLE,</div><div class='add'>+	TG_SET_DSC_CONFIG,</div><div class='add'>+	DSC_DISCONNECT,</div><div class='add'>+	DSC_READ_STATE,</div><div class='add'>+	DSC_CALCULATE_AND_SET_CONFIG,</div><div class='add'>+	DSC_ENABLE_WITH_OPP,</div><div class='add'>+	TG_PROGRAM_GLOBAL_SYNC,</div><div class='add'>+	TG_WAIT_FOR_STATE,</div><div class='add'>+	TG_SET_VTG_PARAMS,</div><div class='add'>+	TG_SETUP_VERTICAL_INTERRUPT2,</div><div class='add'>+	HUBP_PROGRAM_DET_SIZE,</div><div class='add'>+	HUBP_PROGRAM_DET_SEGMENTS,</div><div class='add'>+	OPP_SET_DYN_EXPANSION,</div><div class='add'>+	OPP_PROGRAM_FMT,</div><div class='add'>+	OPP_PROGRAM_BIT_DEPTH_REDUCTION,</div><div class='add'>+	OPP_SET_DISP_PATTERN_GENERATOR,</div><div class='add'>+	ABM_SET_PIPE,</div><div class='add'>+	ABM_SET_LEVEL,</div><div class='add'>+	ABM_SET_IMMEDIATE_DISABLE,</div><div class='add'>+	MPC_REMOVE_MPCC,</div><div class='add'>+	OPP_SET_MPCC_DISCONNECT_PENDING,</div><div class='add'>+	DC_SET_OPTIMIZED_REQUIRED,</div><div class='add'>+	HUBP_DISCONNECT,</div><div class='add'>+	HUBBUB_FORCE_PSTATE_CHANGE_CONTROL,</div><div class='add'>+	TG_ENABLE_CRTC,</div><div class='add'>+	TG_SET_GSL,</div><div class='add'>+	TG_SET_GSL_SOURCE_SELECT,</div><div class='add'>+	HUBP_WAIT_FLIP_PENDING,</div><div class='add'>+	TG_WAIT_DOUBLE_BUFFER_PENDING,</div><div class='add'>+	UPDATE_FORCE_PSTATE,</div><div class='add'>+	PROGRAM_MALL_PIPE_CONFIG,</div><div class='add'>+	HUBBUB_APPLY_DEDCN21_147_WA,</div><div class='add'>+	HUBBUB_ALLOW_SELF_REFRESH_CONTROL,</div><div class='add'>+	TG_GET_FRAME_COUNT,</div><div class='add'>+	MPC_SET_DWB_MUX,</div><div class='add'>+	MPC_DISABLE_DWB_MUX,</div><div class='add'>+	MCIF_WB_CONFIG_BUF,</div><div class='add'>+	MCIF_WB_CONFIG_ARB,</div><div class='add'>+	MCIF_WB_ENABLE,</div><div class='add'>+	MCIF_WB_DISABLE,</div><div class='add'>+	DWBC_ENABLE,</div><div class='add'>+	DWBC_DISABLE,</div><div class='add'>+	DWBC_UPDATE,</div><div class='add'>+	HUBP_UPDATE_MALL_SEL,</div><div class='add'>+	HUBP_PREPARE_SUBVP_BUFFERING,</div><div class='add'>+	HUBP_SET_BLANK_EN,</div><div class='add'>+	HUBP_DISABLE_CONTROL,</div><div class='add'>+	HUBBUB_SOFT_RESET,</div><div class='add'>+	HUBP_CLK_CNTL,</div><div class='add'>+	HUBP_INIT,</div><div class='add'>+	HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS,</div><div class='add'>+	HUBP_SET_FLIP_INT,</div><div class='add'>+	DPP_DPPCLK_CONTROL,</div><div class='add'>+	DISABLE_PHANTOM_CRTC,</div><div class='add'>+	DSC_PG_STATUS,</div><div class='add'>+	DSC_WAIT_DISCONNECT_PENDING_CLEAR,</div><div class='add'>+	DSC_DISABLE,</div><div class='add'>+	DCCG_SET_REF_DSCCLK,</div><div class='add'>+	DPP_PG_CONTROL,</div><div class='add'>+	HUBP_PG_CONTROL,</div><div class='add'>+	HUBP_RESET,</div><div class='add'>+	DPP_RESET,</div><div class='add'>+	DPP_ROOT_CLOCK_CONTROL,</div><div class='add'>+	DC_IP_REQUEST_CNTL,</div><div class='add'>+	DCCG_UPDATE_DPP_DTO,</div><div class='add'>+	HUBP_VTG_SEL,</div><div class='add'>+	HUBP_SETUP2,</div><div class='add'>+	HUBP_SETUP,</div><div class='add'>+	HUBP_SET_UNBOUNDED_REQUESTING,</div><div class='add'>+	HUBP_SETUP_INTERDEPENDENT2,</div><div class='add'>+	HUBP_SETUP_INTERDEPENDENT,</div><div class='add'>+	DPP_SET_CURSOR_MATRIX,</div><div class='add'>+	MPC_UPDATE_BLENDING,</div><div class='add'>+	MPC_ASSERT_IDLE_MPCC,</div><div class='add'>+	MPC_INSERT_PLANE,</div><div class='add'>+	DPP_SET_SCALER,</div><div class='add'>+	HUBP_MEM_PROGRAM_VIEWPORT,</div><div class='add'>+	ABORT_CURSOR_OFFLOAD_UPDATE,</div><div class='add'>+	SET_CURSOR_ATTRIBUTE,</div><div class='add'>+	SET_CURSOR_POSITION,</div><div class='add'>+	SET_CURSOR_SDR_WHITE_LEVEL,</div><div class='add'>+	PROGRAM_OUTPUT_CSC,</div><div class='add'>+	HUBP_SET_LEGACY_TILING_COMPAT_LEVEL,</div><div class='add'>+	HUBP_SET_BLANK,</div><div class='add'>+	PHANTOM_HUBP_POST_ENABLE,</div><div class='add'>+	/* This must be the last value in this enum, add new ones above */</div><div class='add'>+	HWSS_BLOCK_SEQUENCE_FUNC_COUNT</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct block_sequence {</div><div class='hunk'>@@ -186,6 +983,13 @@ struct block_sequence {</div><div class='ctx'> 	enum block_sequence_func func;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct block_sequence_state {</div><div class='add'>+	struct block_sequence *steps;</div><div class='add'>+	unsigned int *num_steps;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES)</div><div class='add'>+</div><div class='ctx'> struct hw_sequencer_funcs {</div><div class='ctx'> 	void (*hardware_release)(struct dc *dc);</div><div class='ctx'> 	/* Embedded Display Related */</div><div class='hunk'>@@ -201,6 +1005,8 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	enum dc_status (*apply_ctx_to_hw)(struct dc *dc,</div><div class='ctx'> 			struct dc_state *context);</div><div class='ctx'> 	void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);</div><div class='ctx'> 	void (*apply_ctx_for_surface)(struct dc *dc,</div><div class='ctx'> 			const struct dc_stream_state *stream,</div><div class='hunk'>@@ -218,14 +1024,18 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	void (*wait_for_mpcc_disconnect)(struct dc *dc,</div><div class='ctx'> 			struct resource_pool *res_pool,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc,</div><div class='add'>+			struct resource_pool *res_pool,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*edp_backlight_control)(</div><div class='ctx'> 			struct dc_link *link,</div><div class='ctx'> 			bool enable);</div><div class='ctx'> 	void (*program_triplebuffer)(const struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);</div><div class='ctx'> 	void (*update_pending_status)(struct pipe_ctx *pipe_ctx);</div><div class='del'>-	void (*power_down)(struct dc *dc);</div><div class='ctx'> 	void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);</div><div class='add'>+	void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);</div><div class='ctx'> </div><div class='ctx'> 	/* Pipe Lock Related */</div><div class='ctx'> 	void (*pipe_control_lock)(struct dc *dc,</div><div class='hunk'>@@ -289,12 +1099,20 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	void (*set_cursor_position)(struct pipe_ctx *pipe);</div><div class='ctx'> 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);</div><div class='ctx'> 	void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);</div><div class='add'>+	void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+	void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+	void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+	void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='add'>+	void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context,</div><div class='add'>+						 const struct dc_stream_state *stream);</div><div class='add'>+	void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe);</div><div class='ctx'> </div><div class='ctx'> 	/* Colour Related */</div><div class='ctx'> 	void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			enum dc_color_space colorspace,</div><div class='ctx'> 			uint16_t *matrix, int opp_id);</div><div class='add'>+	void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	/* VM Related */</div><div class='ctx'> 	int (*init_sys_ctx)(struct dce_hwseq *hws,</div><div class='hunk'>@@ -315,10 +1133,6 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	void (*disable_writeback)(struct dc *dc,</div><div class='ctx'> 			unsigned int dwb_pipe_inst);</div><div class='ctx'> </div><div class='del'>-	bool (*mmhubbub_warmup)(struct dc *dc,</div><div class='del'>-			unsigned int num_dwb,</div><div class='del'>-			struct dc_writeback_info *wb_info);</div><div class='del'>-</div><div class='ctx'> 	/* Clock Related */</div><div class='ctx'> 	enum dc_status (*set_clock)(struct dc *dc,</div><div class='ctx'> 			enum dc_clock_type clock_type,</div><div class='hunk'>@@ -329,6 +1143,9 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 			struct dc_state *context);</div><div class='ctx'> 	void (*exit_optimized_pwr_state)(const struct dc *dc,</div><div class='ctx'> 			struct dc_state *context);</div><div class='add'>+	void (*calculate_pix_rate_divider)(struct dc *dc,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			const struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> 	/* Audio Related */</div><div class='ctx'> 	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);</div><div class='hunk'>@@ -346,8 +1163,7 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	void (*clear_status_bits)(struct dc *dc, unsigned int mask);</div><div class='ctx'> </div><div class='ctx'> 	bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx,</div><div class='del'>-			uint32_t backlight_pwm_u16_16,</div><div class='del'>-			uint32_t frame_ramp);</div><div class='add'>+		struct set_backlight_level_params *params);</div><div class='ctx'> </div><div class='ctx'> 	void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='hunk'>@@ -377,7 +1193,10 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	/* Idle Optimization Related */</div><div class='ctx'> 	bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);</div><div class='ctx'> </div><div class='del'>-	bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane,</div><div class='add'>+	bool (*does_plane_fit_in_mall)(struct dc *dc,</div><div class='add'>+			unsigned int pitch,</div><div class='add'>+			unsigned int height,</div><div class='add'>+			enum surface_pixel_format format,</div><div class='ctx'> 			struct dc_cursor_attributes *cursor_attr);</div><div class='ctx'> 	void (*commit_subvp_config)(struct dc *dc, struct dc_state *context);</div><div class='ctx'> 	void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context);</div><div class='hunk'>@@ -424,11 +1243,50 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 		struct pg_block_update *update_state);</div><div class='ctx'> 	void (*root_clock_control)(struct dc *dc,</div><div class='ctx'> 		struct pg_block_update *update_state, bool power_on);</div><div class='del'>-	void (*set_idle_state)(const struct dc *dc, bool allow_idle);</div><div class='del'>-	uint32_t (*get_idle_state)(const struct dc *dc);</div><div class='ctx'> 	bool (*is_pipe_topology_transition_seamless)(struct dc *dc,</div><div class='ctx'> 			const struct dc_state *cur_ctx,</div><div class='ctx'> 			const struct dc_state *new_ctx);</div><div class='add'>+	void (*wait_for_dcc_meta_propagation)(const struct dc *dc,</div><div class='add'>+		const struct pipe_ctx *top_pipe_to_program);</div><div class='add'>+	void (*dmub_hw_control_lock)(struct dc *dc,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			bool lock);</div><div class='add'>+	void (*fams2_update_config)(struct dc *dc,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			bool enable);</div><div class='add'>+	void (*dmub_hw_control_lock_fast)(union block_sequence_params *params);</div><div class='add'>+	void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max);</div><div class='add'>+	void (*program_outstanding_updates)(struct dc *dc,</div><div class='add'>+			struct dc_state *context);</div><div class='add'>+	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);</div><div class='add'>+	void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*detect_pipe_changes)(struct dc_state *old_state,</div><div class='add'>+			struct dc_state *new_state,</div><div class='add'>+			struct pipe_ctx *old_pipe,</div><div class='add'>+			struct pipe_ctx *new_pipe);</div><div class='add'>+	void (*enable_plane)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct dc_state *context);</div><div class='add'>+	void (*enable_plane_sequence)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='add'>+	void (*update_dchubp_dpp)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct dc_state *context);</div><div class='add'>+	void (*update_dchubp_dpp_sequence)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='add'>+	void (*post_unlock_reset_opp)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *opp_head);</div><div class='add'>+	void (*post_unlock_reset_opp_sequence)(</div><div class='add'>+			struct dc *dc,</div><div class='add'>+			struct pipe_ctx *opp_head,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='add'>+	void (*get_underflow_debug_data)(const struct dc *dc,</div><div class='add'>+			struct timing_generator *tg,</div><div class='add'>+			struct dc_underflow_debug_data *out_data);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void color_space_to_black_color(</div><div class='hunk'>@@ -456,31 +1314,71 @@ void get_hdr_visual_confirm_color(</div><div class='ctx'> void get_mpctree_visual_confirm_color(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color);</div><div class='del'>-</div><div class='add'>+void get_smartmux_visual_confirm_color(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct tg_color *color);</div><div class='add'>+void get_vabc_visual_confirm_color(</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct tg_color *color);</div><div class='ctx'> void get_subvp_visual_confirm_color(</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct tg_color *color);</div><div class='add'>+void get_fams2_visual_confirm_color(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_state *context,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct tg_color *color);</div><div class='ctx'> </div><div class='ctx'> void get_mclk_switch_visual_confirm_color(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color);</div><div class='ctx'> </div><div class='add'>+void get_cursor_visual_confirm_color(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct tg_color *color);</div><div class='add'>+</div><div class='add'>+void get_dcc_visual_confirm_color(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct pipe_ctx *pipe_ctx,</div><div class='add'>+	struct tg_color *color);</div><div class='add'>+</div><div class='ctx'> void set_p_state_switch_method(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='add'>+void set_drr_and_clear_adjust_pending(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct drr_params *params);</div><div class='add'>+</div><div class='ctx'> void hwss_execute_sequence(struct dc *dc,</div><div class='del'>-		struct block_sequence block_sequence[],</div><div class='add'>+		struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],</div><div class='ctx'> 		int num_steps);</div><div class='ctx'> </div><div class='ctx'> void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 		struct dc_dmub_cmd *dc_dmub_cmd,</div><div class='ctx'> 		unsigned int dmub_cmd_count,</div><div class='del'>-		struct block_sequence block_sequence[],</div><div class='del'>-		int *num_steps,</div><div class='add'>+		struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],</div><div class='add'>+		unsigned int *num_steps,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='del'>-		struct dc_stream_status *stream_status);</div><div class='add'>+		struct dc_stream_status *stream_status,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_all_blank_complete(struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_odm_update_pending_complete(struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_no_pipes_pending(struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void hwss_wait_for_outstanding_hw_updates(struct dc *dc,</div><div class='add'>+		struct dc_state *dc_context);</div><div class='add'>+</div><div class='add'>+void hwss_process_outstanding_hw_updates(struct dc *dc,</div><div class='add'>+		struct dc_state *dc_context);</div><div class='ctx'> </div><div class='ctx'> void hwss_send_dmcub_cmd(union block_sequence_params *params);</div><div class='ctx'> </div><div class='hunk'>@@ -498,4 +1396,630 @@ void hwss_set_ocsc_default(union block_sequence_params *params);</div><div class='ctx'> </div><div class='ctx'> void hwss_subvp_save_surf_addr(union block_sequence_params *params);</div><div class='ctx'> </div><div class='add'>+void hwss_program_surface_config(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_odm_combine(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_odm_bypass(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_pipe_clock_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_blank_pixel_data(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dccg_set_dto_dscclk(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_set_config(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_enable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_dsc_config(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_disconnect(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_read_state(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_calculate_and_set_config(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_enable_with_opp(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_program_tg(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_program_global_sync(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_wait_for_state(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_vtg_params(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_program_det_size(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_program_det_segments(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_set_dyn_expansion(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_program_fmt(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_abm_pipe(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_abm_level(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_abm_immediate_disable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_remove_mpcc(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dc_set_optimized_required(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_disconnect(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_enable_crtc(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_gsl(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_set_gsl_source_select(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_wait_flip_pending(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_update_force_pstate(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_tg_get_frame_count(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_set_dwb_mux(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_disable_dwb_mux(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_config_buf(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_config_arb(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_enable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mcif_wb_disable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dwbc_enable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dwbc_disable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dwbc_update(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_update_mall_sel(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_blank_en(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_disable_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubbub_soft_reset(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_clk_cntl(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_init(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_flip_int(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_dppclk_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_disable_phantom_crtc(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_pg_status(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dsc_disable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dccg_set_ref_dscclk(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_pg_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_pg_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_reset(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_reset(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_root_clock_control(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dc_ip_request_cntl(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dccg_update_dpp_dto(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_vtg_sel(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup2(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup_interdependent2(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_setup_interdependent(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_set_cursor_matrix(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_update_mpcc(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_update_blending(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_mpc_insert_plane(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_dpp_set_scaler(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_mem_program_viewport(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_abort_cursor_offload_update(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_cursor_attribute(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_cursor_position(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_set_cursor_sdr_white_level(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_program_output_csc(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_hubp_set_blank(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_phantom_hubp_post_enable(union block_sequence_params *params);</div><div class='add'>+</div><div class='add'>+void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp, bool flip_immediate);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc, int mpcc_id, bool power_on);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode);</div><div class='add'>+</div><div class='add'>+void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);</div><div class='add'>+</div><div class='add'>+void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *top_pipe_to_program);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,</div><div class='add'>+		int odm_slice_width, int last_odm_slice_width);</div><div class='add'>+</div><div class='add'>+void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *optc, struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		int vready_offset,</div><div class='add'>+		unsigned int vstartup_lines,</div><div class='add'>+		unsigned int vupdate_offset_pixels,</div><div class='add'>+		unsigned int vupdate_vupdate_width_pixels,</div><div class='add'>+		unsigned int pstate_keepout_start_lines);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, enum crtc_state state);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, int start_line);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp, uint32_t hw_mult);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_buffer_size_kb);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub, bool enable, bool wait);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_size);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp, enum dc_color_space color_sp,</div><div class='add'>+		enum dc_color_depth color_dpth, enum signal_type signal);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth,</div><div class='add'>+		struct clamping_and_pixel_encoding_params *clamping);</div><div class='add'>+</div><div class='add'>+void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_abm_set_level(struct block_sequence_state *seq_state,</div><div class='add'>+		struct abm *abm, uint32_t abm_level);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg, unsigned int timeout_us, unsigned int polling_interval_us);</div><div class='add'>+</div><div class='add'>+void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dccg *dccg, int inst, int num_slices_h);</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp, int mpcc_inst, bool pending);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state,</div><div class='add'>+		struct display_stream_compressor *dsc);</div><div class='add'>+</div><div class='add'>+void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, bool optimized_required);</div><div class='add'>+</div><div class='add'>+void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		enum controller_dp_test_pattern test_pattern,</div><div class='add'>+		enum controller_dp_color_space color_space,</div><div class='add'>+		enum dc_color_depth color_depth,</div><div class='add'>+		struct tg_color solid_color,</div><div class='add'>+		bool use_solid_color,</div><div class='add'>+		int width,</div><div class='add'>+		int height,</div><div class='add'>+		int offset);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		bool use_default_params,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_dwbc_update(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dwbc *dwb,</div><div class='add'>+		struct dc_dwb_params *dwb_params);</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb,</div><div class='add'>+		struct mcif_buf_params *mcif_buf_params,</div><div class='add'>+		unsigned int dest_height);</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb,</div><div class='add'>+		struct mcif_arb_params *mcif_arb_params);</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb);</div><div class='add'>+</div><div class='add'>+void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mcif_wb *mcif_wb);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int dwb_id,</div><div class='add'>+		int mpcc_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		unsigned int dwb_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_dwbc_enable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dwbc *dwb,</div><div class='add'>+		struct dc_dwb_params *dwb_params);</div><div class='add'>+</div><div class='add'>+void hwss_add_dwbc_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dwbc *dwb);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		struct gsl_params gsl);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		int group_idx,</div><div class='add'>+		uint32_t gsl_ready_signal);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		uint32_t mall_sel,</div><div class='add'>+		bool cache_cursor);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool disable);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset),</div><div class='add'>+		bool reset);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		bool dppclk_div,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg);</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		int dsc_inst,</div><div class='add'>+		bool is_ungated);</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state,</div><div class='add'>+		struct display_stream_compressor *dsc,</div><div class='add'>+		bool *is_ungated);</div><div class='add'>+</div><div class='add'>+void hwss_add_dsc_disable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct display_stream_compressor *dsc,</div><div class='add'>+		bool *is_ungated);</div><div class='add'>+</div><div class='add'>+void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int dsc_inst,</div><div class='add'>+		bool *is_ungated);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int dpp_inst,</div><div class='add'>+		bool clock_on);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int dpp_inst,</div><div class='add'>+		bool power_on);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dce_hwseq *hws,</div><div class='add'>+		unsigned int hubp_inst,</div><div class='add'>+		bool power_on);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool blank);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_init(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_reset(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_reset(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		uint64_t sys_default,</div><div class='add'>+		uint64_t sys_low,</div><div class='add'>+		uint64_t sys_high);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int dpp_inst,</div><div class='add'>+		int dppclk_khz);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		uint32_t otg_inst);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup2(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *hubp_regs,</div><div class='add'>+		union dml2_global_sync_programming *global_sync,</div><div class='add'>+		struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,</div><div class='add'>+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs,</div><div class='add'>+		struct _vcs_dpi_display_rq_regs_st *rq_regs,</div><div class='add'>+		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		bool unbounded_req);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *hubp_regs);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,</div><div class='add'>+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs);</div><div class='add'>+void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		enum surface_pixel_format format,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='add'>+		struct plane_size plane_size,</div><div class='add'>+		enum dc_rotation_angle rotation,</div><div class='add'>+		struct dc_plane_dcc_param *dcc,</div><div class='add'>+		bool horizontal_mirror,</div><div class='add'>+		int compat_level);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		enum dc_color_space color_space,</div><div class='add'>+		struct dc_csc_transform *cursor_csc_color_matrix);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		struct mpcc_blnd_cfg blnd_cfg,</div><div class='add'>+		int mpcc_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int mpcc_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state,</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		struct mpc_tree *mpc_tree_params,</div><div class='add'>+		struct mpcc_blnd_cfg blnd_cfg,</div><div class='add'>+		struct mpcc_sm_cfg *sm_cfg,</div><div class='add'>+		struct mpcc *insert_above_mpcc,</div><div class='add'>+		int dpp_id,</div><div class='add'>+		int mpcc_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dpp *dpp,</div><div class='add'>+		const struct scaler_data *scl_data);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		const struct rect *viewport,</div><div class='add'>+		const struct rect *viewport_c);</div><div class='add'>+</div><div class='add'>+void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+void hwss_add_program_output_csc(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		enum dc_color_space colorspace,</div><div class='add'>+		uint16_t *matrix,</div><div class='add'>+		int opp_id);</div><div class='add'>+</div><div class='add'>+void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubp *hubp);</div><div class='add'>+</div><div class='add'>+void hwss_add_update_force_pstate(struct block_sequence_state *seq_state,</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub);</div><div class='add'>+</div><div class='add'>+void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state,</div><div class='add'>+		struct hubbub *hubbub,</div><div class='add'>+		bool allow,</div><div class='add'>+		bool *disallow_self_refresh_applied);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		unsigned int *frame_count);</div><div class='add'>+</div><div class='add'>+void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state,</div><div class='add'>+		struct timing_generator *tg,</div><div class='add'>+		struct dsc_optc_config *dsc_optc_cfg,</div><div class='add'>+		bool enable);</div><div class='add'>+</div><div class='add'>+void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state,</div><div class='add'>+		struct output_pixel_processor *opp,</div><div class='add'>+		enum dc_pixel_encoding pixel_encoding,</div><div class='add'>+		bool is_otg_master);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HW_SEQUENCER_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h<br/>index 554cfab5ab24..406db231bc72 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> #define __DC_HW_SEQUENCER_PRIVATE_H__</div><div class='ctx'> </div><div class='ctx'> #include "dc_types.h"</div><div class='add'>+#include "hw_sequencer.h"</div><div class='ctx'> </div><div class='ctx'> enum pipe_gating_control {</div><div class='ctx'> 	PIPE_GATING_CONTROL_DISABLE = 0,</div><div class='hunk'>@@ -49,6 +50,7 @@ struct hwseq_wa_state {</div><div class='ctx'> 	bool DEGVIDCN10_253_applied;</div><div class='ctx'> 	bool disallow_self_refresh_during_multi_plane_transition_applied;</div><div class='ctx'> 	unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;</div><div class='add'>+	bool skip_blank_stream;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct pipe_ctx;</div><div class='hunk'>@@ -76,12 +78,16 @@ struct hwseq_private_funcs {</div><div class='ctx'> 	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*init_pipes)(struct dc *dc, struct dc_state *context);</div><div class='ctx'> 	void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);</div><div class='del'>-	void (*update_plane_addr)(const struct dc *dc,</div><div class='del'>-			struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*plane_atomic_disconnect)(struct dc *dc,</div><div class='ctx'> 			struct dc_state *state,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*plane_atomic_disconnect_sequence)(struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	bool (*set_input_transfer_func)(struct dc *dc,</div><div class='ctx'> 				struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 				const struct dc_plane_state *plane_state);</div><div class='hunk'>@@ -98,6 +104,10 @@ struct hwseq_private_funcs {</div><div class='ctx'> 	void (*blank_pixel_data)(struct dc *dc,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			bool blank);</div><div class='add'>+	void (*blank_pixel_data_sequence)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			bool blank,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	enum dc_status (*enable_stream_timing)(</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			struct dc_state *context,</div><div class='hunk'>@@ -106,6 +116,8 @@ struct hwseq_private_funcs {</div><div class='ctx'> 			bool enable);</div><div class='ctx'> 	void (*setup_vupdate_interrupt)(struct dc *dc,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='ctx'> 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*init_blank)(struct dc *dc, struct timing_generator *tg);</div><div class='ctx'> 	void (*disable_vga)(struct dce_hwseq *hws);</div><div class='hunk'>@@ -113,6 +125,10 @@ struct hwseq_private_funcs {</div><div class='ctx'> 	void (*plane_atomic_power_down)(struct dc *dc,</div><div class='ctx'> 			struct dpp *dpp,</div><div class='ctx'> 			struct hubp *hubp);</div><div class='add'>+	void (*plane_atomic_power_down_sequence)(struct dc *dc,</div><div class='add'>+			struct dpp *dpp,</div><div class='add'>+			struct hubp *hubp,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*enable_power_gating_plane)(struct dce_hwseq *hws,</div><div class='ctx'> 		bool enable);</div><div class='hunk'>@@ -120,6 +136,14 @@ struct hwseq_private_funcs {</div><div class='ctx'> 			struct dce_hwseq *hws,</div><div class='ctx'> 			unsigned int dpp_inst,</div><div class='ctx'> 			bool clock_on);</div><div class='add'>+	void (*dpstream_root_clock_control)(</div><div class='add'>+			struct dce_hwseq *hws,</div><div class='add'>+			unsigned int dpp_inst,</div><div class='add'>+			bool clock_on);</div><div class='add'>+	void (*physymclk_root_clock_control)(</div><div class='add'>+			struct dce_hwseq *hws,</div><div class='add'>+			unsigned int phy_inst,</div><div class='add'>+			bool clock_on);</div><div class='ctx'> 	void (*dpp_pg_control)(struct dce_hwseq *hws,</div><div class='ctx'> 			unsigned int dpp_inst,</div><div class='ctx'> 			bool power_on);</div><div class='hunk'>@@ -133,15 +157,31 @@ struct hwseq_private_funcs {</div><div class='ctx'> 			unsigned int dsc_inst);</div><div class='ctx'> 	void (*update_odm)(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*update_odm_sequence)(struct dc *dc, struct dc_state *context,</div><div class='add'>+			struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*program_all_writeback_pipes_in_tree)(struct dc *dc,</div><div class='ctx'> 			const struct dc_stream_state *stream,</div><div class='ctx'> 			struct dc_state *context);</div><div class='add'>+	void (*program_all_writeback_pipes_in_tree_sequence)(</div><div class='add'>+			struct dc *dc,</div><div class='add'>+			const struct dc_stream_state *stream,</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	bool (*s0i3_golden_init_wa)(struct dc *dc);</div><div class='ctx'> 	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*set_hdr_multiplier_sequence)(struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*verify_allow_pstate_change_high)(struct dc *dc);</div><div class='add'>+	void (*verify_allow_pstate_change_high_sequence)(struct dc *dc,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*program_pipe)(struct dc *dc,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			struct dc_state *context);</div><div class='add'>+	void (*program_pipe_sequence)(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct block_sequence_state *seq_state);</div><div class='ctx'> 	bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);</div><div class='ctx'> 	void (*dccg_init)(struct dce_hwseq *hws);</div><div class='ctx'> 	bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,</div><div class='hunk'>@@ -156,14 +196,16 @@ struct hwseq_private_funcs {</div><div class='ctx'> 	void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			       struct dc_state *context);</div><div class='ctx'> 	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);</div><div class='add'>+	void (*program_mall_pipe_config_sequence)(struct dc *dc, struct dc_state *context,</div><div class='add'>+			struct block_sequence_state *seq_state);</div><div class='ctx'> 	void (*update_force_pstate)(struct dc *dc, struct dc_state *context);</div><div class='ctx'> 	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);</div><div class='ctx'> 	unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			unsigned int *k1_div,</div><div class='ctx'> 			unsigned int *k2_div);</div><div class='del'>-	void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,</div><div class='del'>-			struct dc_state *context);</div><div class='add'>+			struct dc_state *context,</div><div class='add'>+			unsigned int current_pipe_idx);</div><div class='ctx'> 	enum dc_status (*apply_single_controller_ctx_to_hw)(</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			struct dc_state *context,</div><div class='hunk'>@@ -172,6 +214,14 @@ struct hwseq_private_funcs {</div><div class='ctx'> 	void (*reset_back_end_for_pipe)(struct dc *dc,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			struct dc_state *context);</div><div class='add'>+	void (*populate_mcm_luts)(struct dc *dc,</div><div class='add'>+			struct pipe_ctx *pipe_ctx,</div><div class='add'>+			struct dc_cm2_func_luts mcm_luts,</div><div class='add'>+			bool lut_bank_a);</div><div class='add'>+	void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only);</div><div class='add'>+	void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*dc_ip_request_cntl)(struct dc *dc, bool enable);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dce_hwseq {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h<br/>index 8f8ac8e29ed0..ed2f8005d85e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/clock_source.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/clock_source.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/clock_source.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/clock_source.h</a></div><div class='hunk'>@@ -96,6 +96,7 @@ struct pixel_clk_params {</div><div class='ctx'> /*&gt; de-spread info, relevant only for on-the-fly tune-up pixel rate*/</div><div class='ctx'> 	enum dc_pixel_encoding pixel_encoding;</div><div class='ctx'> 	struct pixel_clk_flags flags;</div><div class='add'>+	uint32_t dio_se_pix_per_cycle;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h<br/>index fa5edd03d004..82085d9c3f40 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/core_status.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/core_status.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/core_status.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/core_status.h</a></div><div class='hunk'>@@ -26,6 +26,8 @@</div><div class='ctx'> #ifndef _CORE_STATUS_H_</div><div class='ctx'> #define _CORE_STATUS_H_</div><div class='ctx'> </div><div class='add'>+#include "dc_hw_types.h"</div><div class='add'>+</div><div class='ctx'> enum dc_status {</div><div class='ctx'> 	DC_OK = 1,</div><div class='ctx'> </div><div class='hunk'>@@ -56,9 +58,13 @@ enum dc_status {</div><div class='ctx'> 	DC_NO_LINK_ENC_RESOURCE = 26,</div><div class='ctx'> 	DC_FAIL_DP_PAYLOAD_ALLOCATION = 27,</div><div class='ctx'> 	DC_FAIL_DP_LINK_BANDWIDTH = 28,</div><div class='add'>+	DC_FAIL_HW_CURSOR_SUPPORT = 29,</div><div class='add'>+	DC_FAIL_DP_TUNNEL_BW_VALIDATE = 30,</div><div class='ctx'> 	DC_ERROR_UNEXPECTED = -1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> char *dc_status_to_str(enum dc_status status);</div><div class='add'>+char *dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding);</div><div class='add'>+char *dc_color_depth_to_str(enum dc_color_depth color_depth);</div><div class='ctx'> </div><div class='ctx'> #endif /* _CORE_STATUS_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h<br/>index b1b72e688f74..5ed2cd344804 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/core_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/core_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/core_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/core_types.h</a></div><div class='hunk'>@@ -39,14 +39,12 @@</div><div class='ctx'> #include "panel_cntl.h"</div><div class='ctx'> #include "dmub/inc/dmub_cmd.h"</div><div class='ctx'> #include "pg_cntl.h"</div><div class='add'>+#include "sspl/dc_spl.h"</div><div class='ctx'> </div><div class='ctx'> #define MAX_CLOCK_SOURCES 7</div><div class='ctx'> #define MAX_SVP_PHANTOM_STREAMS 2</div><div class='ctx'> #define MAX_SVP_PHANTOM_PLANES 2</div><div class='ctx'> </div><div class='del'>-void enable_surface_flip_reporting(struct dc_plane_state *plane_state,</div><div class='del'>-		uint32_t controller_id);</div><div class='del'>-</div><div class='ctx'> #include "grph_object_id.h"</div><div class='ctx'> #include "link_encoder.h"</div><div class='ctx'> #include "stream_encoder.h"</div><div class='hunk'>@@ -60,10 +58,16 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,</div><div class='ctx'> #include "transform.h"</div><div class='ctx'> #include "dpp.h"</div><div class='ctx'> </div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"</div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_types.h"</div><div class='add'>+</div><div class='ctx'> struct resource_pool;</div><div class='ctx'> struct dc_state;</div><div class='ctx'> struct resource_context;</div><div class='ctx'> struct clk_bw_params;</div><div class='add'>+struct dc_mcache_params;</div><div class='add'>+</div><div class='add'>+#define MAX_RMCM_INST  2</div><div class='ctx'> </div><div class='ctx'> struct resource_funcs {</div><div class='ctx'> 	enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index);</div><div class='hunk'>@@ -77,11 +81,10 @@ struct resource_funcs {</div><div class='ctx'> 	/* Create a minimal link encoder object with no dc_link object</div><div class='ctx'> 	 * associated with it. */</div><div class='ctx'> 	struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);</div><div class='del'>-</div><div class='del'>-	bool (*validate_bandwidth)(</div><div class='add'>+	enum dc_status (*validate_bandwidth)(</div><div class='ctx'> 					struct dc *dc,</div><div class='ctx'> 					struct dc_state *context,</div><div class='del'>-					bool fast_validate);</div><div class='add'>+					enum dc_validate_mode validate_mode);</div><div class='ctx'> 	void (*calculate_wm_and_dlg)(</div><div class='ctx'> 				struct dc *dc, struct dc_state *context,</div><div class='ctx'> 				display_e2e_pipe_params_st *pipes,</div><div class='hunk'>@@ -90,6 +93,12 @@ struct resource_funcs {</div><div class='ctx'> 	void (*update_soc_for_wm_a)(</div><div class='ctx'> 				struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='add'>+	unsigned int (*calculate_mall_ways_from_bytes)(</div><div class='add'>+				const struct dc *dc,</div><div class='add'>+				unsigned int total_size_in_mall_bytes);</div><div class='add'>+	void (*prepare_mcache_programming)(</div><div class='add'>+					struct dc *dc,</div><div class='add'>+					struct dc_state *context);</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * @populate_dml_pipes - Populate pipe data struct</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -100,7 +109,7 @@ struct resource_funcs {</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Algorithm for assigning available link encoders to links.</div><div class='hunk'>@@ -156,6 +165,7 @@ struct resource_funcs {</div><div class='ctx'> 				struct dc *dc,</div><div class='ctx'> 				struct dc_state *new_ctx,</div><div class='ctx'> 				struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> 	enum dc_status (*patch_unknown_plane_state)(</div><div class='ctx'> 			struct dc_plane_state *plane_state);</div><div class='ctx'> </div><div class='hunk'>@@ -163,6 +173,7 @@ struct resource_funcs {</div><div class='ctx'> 			struct resource_context *res_ctx,</div><div class='ctx'> 			const struct resource_pool *pool,</div><div class='ctx'> 			struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> 	void (*populate_dml_writeback_from_context)(</div><div class='ctx'> 			struct dc *dc,</div><div class='ctx'> 			struct resource_context *res_ctx,</div><div class='hunk'>@@ -173,6 +184,7 @@ struct resource_funcs {</div><div class='ctx'> 			struct dc_state *context,</div><div class='ctx'> 			display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 			int pipe_cnt);</div><div class='add'>+</div><div class='ctx'> 	void (*update_bw_bounding_box)(</div><div class='ctx'> 			struct dc *dc,</div><div class='ctx'> 			struct clk_bw_params *bw_params);</div><div class='hunk'>@@ -202,6 +214,22 @@ struct resource_funcs {</div><div class='ctx'> </div><div class='ctx'> 	void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);</div><div class='ctx'> 	void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);</div><div class='add'>+	/*</div><div class='add'>+	 * Get indicator of power from a context that went through full validation</div><div class='add'>+	 */</div><div class='add'>+	int (*get_power_profile)(const struct dc_state *context);</div><div class='add'>+	unsigned int (*get_det_buffer_size)(const struct dc_state *context);</div><div class='add'>+	unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx);</div><div class='add'>+	unsigned int (*get_max_hw_cursor_size)(const struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			const struct dc_stream_state *stream);</div><div class='add'>+	bool (*program_mcache_pipe_config)(struct dc_state *context,</div><div class='add'>+		const struct dc_mcache_params *mcache_params);</div><div class='add'>+	enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link,</div><div class='add'>+		struct dc_link_settings *link_setting,</div><div class='add'>+		uint8_t pipe_count,</div><div class='add'>+		struct pipe_ctx *pipes,</div><div class='add'>+		struct audio_output *audio_output);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct audio_support{</div><div class='hunk'>@@ -246,7 +274,7 @@ struct resource_pool {</div><div class='ctx'> 	/* An array for accessing the link encoder objects that have been created.</div><div class='ctx'> 	 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA</div><div class='ctx'> 	 */</div><div class='del'>-	struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS];</div><div class='add'>+	struct link_encoder *link_encoders[MAX_LINK_ENCODERS];</div><div class='ctx'> 	/* Number of DIG link encoder objects created - i.e. number of valid</div><div class='ctx'> 	 * entries in link_encoders array.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -260,6 +288,7 @@ struct resource_pool {</div><div class='ctx'> 	struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];</div><div class='ctx'> 	struct dc_3dlut *mpc_lut[MAX_PIPES];</div><div class='ctx'> 	struct dc_transfer_func *mpc_shaper[MAX_PIPES];</div><div class='add'>+	struct dc_rmcm_3dlut rmcm_3dlut[MAX_RMCM_INST];</div><div class='ctx'> </div><div class='ctx'> 	struct {</div><div class='ctx'> 		unsigned int xtalin_clock_inKhz;</div><div class='hunk'>@@ -289,7 +318,6 @@ struct resource_pool {</div><div class='ctx'> 	struct abm *abm;</div><div class='ctx'> 	struct dmcu *dmcu;</div><div class='ctx'> 	struct dmub_psr *psr;</div><div class='del'>-</div><div class='ctx'> 	struct dmub_replay *replay;</div><div class='ctx'> </div><div class='ctx'> 	struct abm *multiple_abms[MAX_PIPES];</div><div class='hunk'>@@ -336,7 +364,16 @@ struct stream_resource {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct plane_resource {</div><div class='add'>+	/* scl_data is scratch space required to program a plane */</div><div class='ctx'> 	struct scaler_data scl_data;</div><div class='add'>+	/* Below pointers to hw objects are required to enable the plane */</div><div class='add'>+	/* spl_in and spl_out are the input and output structures for SPL</div><div class='add'>+	 * which are required when using Scaler Programming Library</div><div class='add'>+	 * these are scratch spaces needed when programming a plane</div><div class='add'>+	 */</div><div class='add'>+	struct spl_in spl_in;</div><div class='add'>+	struct spl_out spl_out;</div><div class='add'>+	/* Below pointers to hw objects are required to enable the plane */</div><div class='ctx'> 	struct hubp *hubp;</div><div class='ctx'> 	struct mem_input *mi;</div><div class='ctx'> 	struct input_pixel_processor *ipp;</div><div class='hunk'>@@ -352,12 +389,15 @@ struct plane_resource {</div><div class='ctx'> </div><div class='ctx'> /* all mappable hardware resources used to enable a link */</div><div class='ctx'> struct link_resource {</div><div class='add'>+	struct link_encoder *dio_link_enc;</div><div class='ctx'> 	struct hpo_dp_link_encoder *hpo_dp_link_enc;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct link_config {</div><div class='ctx'> 	struct dc_link_settings dp_link_settings;</div><div class='add'>+	struct dc_tunnel_settings dp_tunnel_settings;</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> union pipe_update_flags {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		uint32_t enable : 1;</div><div class='hunk'>@@ -381,6 +421,11 @@ union pipe_update_flags {</div><div class='ctx'> 	uint32_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct pixel_rate_divider {</div><div class='add'>+	uint32_t div_factor1;</div><div class='add'>+	uint32_t div_factor2;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum p_state_switch_method {</div><div class='ctx'> 	P_STATE_UNKNOWN						= 0,</div><div class='ctx'> 	P_STATE_V_BLANK						= 1,</div><div class='hunk'>@@ -388,7 +433,14 @@ enum p_state_switch_method {</div><div class='ctx'> 	P_STATE_V_ACTIVE,</div><div class='ctx'> 	P_STATE_SUB_VP,</div><div class='ctx'> 	P_STATE_DRR_SUB_VP,</div><div class='del'>-	P_STATE_V_BLANK_SUB_VP</div><div class='add'>+	P_STATE_V_BLANK_SUB_VP,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dsc_padding_params {</div><div class='add'>+	/* pixels borrowed from hblank to hactive */</div><div class='add'>+	uint8_t dsc_hactive_padding;</div><div class='add'>+	uint32_t dsc_htotal_padding;</div><div class='add'>+	uint32_t dsc_pix_clk_100hz;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct pipe_ctx {</div><div class='hunk'>@@ -435,6 +487,9 @@ struct pipe_ctx {</div><div class='ctx'> 	int det_buffer_size_kb;</div><div class='ctx'> 	bool unbounded_req;</div><div class='ctx'> 	unsigned int surface_size_in_mall_bytes;</div><div class='add'>+	struct dml2_dchub_per_pipe_register_set hubp_regs;</div><div class='add'>+	struct dml2_hubp_pipe_mcache_regs mcache_regs;</div><div class='add'>+	union dml2_global_sync_programming global_sync;</div><div class='ctx'> </div><div class='ctx'> 	struct dwbc *dwbc;</div><div class='ctx'> 	struct mcif_wb *mcif_wb;</div><div class='hunk'>@@ -444,6 +499,12 @@ struct pipe_ctx {</div><div class='ctx'> 	bool has_vactive_margin;</div><div class='ctx'> 	/* subvp_index: only valid if the pipe is a SUBVP_MAIN*/</div><div class='ctx'> 	uint8_t subvp_index;</div><div class='add'>+	struct pixel_rate_divider pixel_rate_divider;</div><div class='add'>+	struct dsc_padding_params dsc_padding_params;</div><div class='add'>+	/* next vupdate */</div><div class='add'>+	uint32_t next_vupdate;</div><div class='add'>+	uint32_t wait_frame_count;</div><div class='add'>+	bool wait_is_required;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Data used for dynamic link encoder assignment.</div><div class='hunk'>@@ -453,7 +514,7 @@ struct pipe_ctx {</div><div class='ctx'> struct link_enc_cfg_context {</div><div class='ctx'> 	enum link_enc_cfg_mode mode;</div><div class='ctx'> 	struct link_enc_assignment link_enc_assignments[MAX_PIPES];</div><div class='del'>-	enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];</div><div class='add'>+	enum engine_id link_enc_avail[MAX_LINK_ENCODERS];</div><div class='ctx'> 	struct link_enc_assignment transient_assignments[MAX_PIPES];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -465,11 +526,13 @@ struct resource_context {</div><div class='ctx'> 	uint8_t dp_clock_source_ref_count;</div><div class='ctx'> 	bool is_dsc_acquired[MAX_PIPES];</div><div class='ctx'> 	struct link_enc_cfg_context link_enc_cfg_ctx;</div><div class='add'>+	unsigned int dio_link_enc_to_link_idx[MAX_LINK_ENCODERS];</div><div class='add'>+	int dio_link_enc_ref_cnts[MAX_LINK_ENCODERS];</div><div class='ctx'> 	bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];</div><div class='ctx'> 	unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];</div><div class='ctx'> 	int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];</div><div class='ctx'> 	bool is_mpc_3dlut_acquired[MAX_PIPES];</div><div class='del'>-	/* solely used for build scalar data in dml2 */</div><div class='add'>+	/* used to build scalar data in dml2 and for edp backlight programming */</div><div class='ctx'> 	struct pipe_ctx temp_pipe;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -496,7 +559,7 @@ struct dcn_bw_writeback {</div><div class='ctx'> </div><div class='ctx'> struct dcn_bw_output {</div><div class='ctx'> 	struct dc_clocks clk;</div><div class='del'>-	struct dcn_watermark_set watermarks;</div><div class='add'>+	union dcn_watermark_set watermarks;</div><div class='ctx'> 	struct dcn_bw_writeback bw_writeback;</div><div class='ctx'> 	int compbuf_size_kb;</div><div class='ctx'> 	unsigned int mall_ss_size_bytes;</div><div class='hunk'>@@ -504,6 +567,14 @@ struct dcn_bw_output {</div><div class='ctx'> 	unsigned int mall_subvp_size_bytes;</div><div class='ctx'> 	unsigned int legacy_svp_drr_stream_index;</div><div class='ctx'> 	bool legacy_svp_drr_stream_index_valid;</div><div class='add'>+	struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];</div><div class='add'>+	struct dmub_cmd_fams2_global_config fams2_global_config;</div><div class='add'>+	union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES];</div><div class='add'>+	union {</div><div class='add'>+		union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES];</div><div class='add'>+		union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES];</div><div class='add'>+	};</div><div class='add'>+	struct dml2_display_arb_regs arb_regs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union bw_output {</div><div class='hunk'>@@ -515,6 +586,7 @@ struct bw_context {</div><div class='ctx'> 	union bw_output bw;</div><div class='ctx'> 	struct display_mode_lib dml;</div><div class='ctx'> 	struct dml2_context *dml2;</div><div class='add'>+	struct dml2_context *dml2_dc_power_source;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_dmub_cmd {</div><div class='hunk'>@@ -522,25 +594,6 @@ struct dc_dmub_cmd {</div><div class='ctx'> 	enum dm_dmub_wait_type wait_type;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dc_scratch_space {</div><div class='del'>-	/* used to temporarily backup plane states of a stream during</div><div class='del'>-	 * dc update. The reason is that plane states are overwritten</div><div class='del'>-	 * with surface updates in dc update. Once they are overwritten</div><div class='del'>-	 * current state is no longer valid. We want to temporarily</div><div class='del'>-	 * store current value in plane states so we can still recover</div><div class='del'>-	 * a valid current state during dc update.</div><div class='del'>-	 */</div><div class='del'>-	struct dc_plane_state plane_states[MAX_SURFACE_NUM];</div><div class='del'>-	struct dc_gamma gamma_correction[MAX_SURFACE_NUM];</div><div class='del'>-	struct dc_transfer_func in_transfer_func[MAX_SURFACE_NUM];</div><div class='del'>-	struct dc_3dlut lut3d_func[MAX_SURFACE_NUM];</div><div class='del'>-	struct dc_transfer_func in_shaper_func[MAX_SURFACE_NUM];</div><div class='del'>-	struct dc_transfer_func blend_tf[MAX_SURFACE_NUM];</div><div class='del'>-</div><div class='del'>-	struct dc_stream_state stream_state;</div><div class='del'>-	struct dc_transfer_func out_transfer_func;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * struct dc_state - The full description of a state requested by users</div><div class='ctx'>  */</div><div class='hunk'>@@ -605,7 +658,7 @@ struct dc_state {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct bw_context bw_ctx;</div><div class='ctx'> </div><div class='del'>-	struct block_sequence block_sequence[50];</div><div class='add'>+	struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE];</div><div class='ctx'> 	unsigned int block_sequence_steps;</div><div class='ctx'> 	struct dc_dmub_cmd dc_dmub_cmd[10];</div><div class='ctx'> 	unsigned int dmub_cmd_count;</div><div class='hunk'>@@ -623,8 +676,7 @@ struct dc_state {</div><div class='ctx'> 		unsigned int stutter_period_us;</div><div class='ctx'> 	} perf_params;</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-	struct dc_scratch_space scratch;</div><div class='add'>+	enum dc_power_source_type power_source;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct replay_context {</div><div class='hunk'>@@ -637,6 +689,7 @@ struct replay_context {</div><div class='ctx'> 	/* Controller Id used for Dig Fe source select */</div><div class='ctx'> 	enum controller_id controllerId;</div><div class='ctx'> 	unsigned int line_time_in_ns;</div><div class='add'>+	bool os_request_force_ffu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum dc_replay_enable {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h<br/>index 9e4ddc985240..134091d5842d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h</a></div><div class='hunk'>@@ -31,7 +31,7 @@</div><div class='ctx'> #define __DCN_CALCS_H__</div><div class='ctx'> </div><div class='ctx'> #include "bw_fixed.h"</div><div class='del'>-#include "../dml/display_mode_lib.h"</div><div class='add'>+#include "dml/display_mode_lib.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> struct dc;</div><div class='hunk'>@@ -622,11 +622,7 @@ extern const struct dcn_ip_params dcn10_ip_defaults;</div><div class='ctx'> bool dcn_validate_bandwidth(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate);</div><div class='del'>-</div><div class='del'>-unsigned int dcn_find_dcfclk_suits_all(</div><div class='del'>-	const struct dc *dc,</div><div class='del'>-	struct dc_clocks *clocks);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> void dcn_get_soc_clks(</div><div class='ctx'> 		struct dc *dc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h<br/>index b6203253111c..8c18efc2aa70 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/audio.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/audio.h</a></div><div class='hunk'>@@ -46,6 +46,8 @@ struct audio_funcs {</div><div class='ctx'> 		const struct audio_info *audio_info,</div><div class='ctx'> 		const struct audio_dp_link_info *dp_link_info);</div><div class='ctx'> </div><div class='add'>+	void (*az_disable_hbr_audio)(struct audio *audio);</div><div class='add'>+</div><div class='ctx'> 	void (*wall_dto_setup)(struct audio *audio,</div><div class='ctx'> 		enum signal_type signal,</div><div class='ctx'> 		const struct audio_crtc_info *crtc_info,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h<br/>index 17e014d3bdc8..2c9a4a12bd8a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h</a></div><div class='hunk'>@@ -29,9 +29,6 @@</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "dm_pp_smu.h"</div><div class='ctx'> </div><div class='del'>-#define DCN_MINIMUM_DISPCLK_Khz 100000</div><div class='del'>-#define DCN_MINIMUM_DPPCLK_Khz 100000</div><div class='del'>-</div><div class='ctx'> /* Constants */</div><div class='ctx'> #define DDR4_DRAM_WIDTH   64</div><div class='ctx'> #define WM_A 0</div><div class='hunk'>@@ -39,6 +36,8 @@</div><div class='ctx'> #define WM_C 2</div><div class='ctx'> #define WM_D 3</div><div class='ctx'> #define WM_SET_COUNT 4</div><div class='add'>+#define WM_1A 2</div><div class='add'>+#define WM_1B 3</div><div class='ctx'> </div><div class='ctx'> #define DCN_MINIMUM_DISPCLK_Khz 100000</div><div class='ctx'> #define DCN_MINIMUM_DPPCLK_Khz 100000</div><div class='hunk'>@@ -101,6 +100,17 @@ struct dcn301_clk_internal {</div><div class='ctx'> #define MAX_NUM_DPM_LVL		8</div><div class='ctx'> #define WM_SET_COUNT 		4</div><div class='ctx'> </div><div class='add'>+enum clk_type {</div><div class='add'>+	CLK_TYPE_DCFCLK,</div><div class='add'>+	CLK_TYPE_FCLK,</div><div class='add'>+	CLK_TYPE_MCLK,</div><div class='add'>+	CLK_TYPE_SOCCLK,</div><div class='add'>+	CLK_TYPE_DTBCLK,</div><div class='add'>+	CLK_TYPE_DISPCLK,</div><div class='add'>+	CLK_TYPE_DPPCLK,</div><div class='add'>+	CLK_TYPE_DSCCLK,</div><div class='add'>+	CLK_TYPE_COUNT</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> struct clk_limit_table_entry {</div><div class='ctx'> 	unsigned int voltage; /* milivolts withh 2 fractional bits */</div><div class='hunk'>@@ -178,6 +188,7 @@ struct clk_state_registers_and_bypass {</div><div class='ctx'> 	uint32_t dispclk;</div><div class='ctx'> 	uint32_t dppclk;</div><div class='ctx'> 	uint32_t dtbclk;</div><div class='add'>+	uint32_t fclk;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t dppclk_bypass;</div><div class='ctx'> 	uint32_t dcfclk_bypass;</div><div class='hunk'>@@ -242,14 +253,14 @@ struct wm_table {</div><div class='ctx'> </div><div class='ctx'> struct dummy_pstate_entry {</div><div class='ctx'> 	unsigned int dram_speed_mts;</div><div class='del'>-	double dummy_pstate_latency_us;</div><div class='add'>+	unsigned int dummy_pstate_latency_us;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct clk_bw_params {</div><div class='ctx'> 	unsigned int vram_type;</div><div class='ctx'> 	unsigned int num_channels;</div><div class='ctx'> 	unsigned int dram_channel_width_bytes;</div><div class='del'>- 	unsigned int dispclk_vco_khz;</div><div class='add'>+	unsigned int dispclk_vco_khz;</div><div class='ctx'> 	unsigned int dc_mode_softmax_memclk;</div><div class='ctx'> 	unsigned int max_memclk_mhz;</div><div class='ctx'> 	struct clk_limit_table clk_table;</div><div class='hunk'>@@ -281,8 +292,6 @@ struct clk_mgr_funcs {</div><div class='ctx'> 	void (*set_low_power_state)(struct clk_mgr *clk_mgr);</div><div class='ctx'> 	void (*exit_low_power_state)(struct clk_mgr *clk_mgr);</div><div class='ctx'> 	bool (*is_ips_supported)(struct clk_mgr *clk_mgr);</div><div class='del'>-	void (*set_idle_state)(struct clk_mgr *clk_mgr, bool allow_idle);</div><div class='del'>-	uint32_t (*get_idle_state)(struct clk_mgr *clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	void (*init_clocks)(struct clk_mgr *clk_mgr);</div><div class='ctx'> </div><div class='hunk'>@@ -308,6 +317,9 @@ struct clk_mgr_funcs {</div><div class='ctx'> 	 */</div><div class='ctx'> 	void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);</div><div class='ctx'> </div><div class='add'>+	int (*get_hard_min_memclk)(struct clk_mgr *clk_mgr);</div><div class='add'>+	int (*get_hard_min_fclk)(struct clk_mgr *clk_mgr);</div><div class='add'>+</div><div class='ctx'> 	/* Send message to PMFW to set hard max memclk frequency to highest DPM */</div><div class='ctx'> 	void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);</div><div class='ctx'> </div><div class='hunk'>@@ -323,6 +335,11 @@ struct clk_mgr_funcs {</div><div class='ctx'> </div><div class='ctx'> 	int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);</div><div class='ctx'> </div><div class='add'>+	bool (*is_dc_mode_present)(struct clk_mgr *clk_mgr);</div><div class='add'>+</div><div class='add'>+	uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set);</div><div class='add'>+</div><div class='add'>+	unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct clk_mgr {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h<br/>index f4d4a68c91dc..bac8febad69a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h</a></div><div class='hunk'>@@ -97,11 +97,6 @@ enum dentist_divider_range {</div><div class='ctx'> #define CLK_COMMON_REG_LIST_DCN_BASE() \</div><div class='ctx'> 	SR(DENTIST_DISPCLK_CNTL)</div><div class='ctx'> </div><div class='del'>-#define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \</div><div class='del'>-	.MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \</div><div class='del'>-	.MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \</div><div class='del'>-	.MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67</div><div class='del'>-</div><div class='ctx'> #define CLK_COMMON_REG_LIST_DCN_201() \</div><div class='ctx'> 	SR(DENTIST_DISPCLK_CNTL), \</div><div class='ctx'> 	CLK_SRI(CLK4_CLK_PLL_REQ, CLK4, 0), \</div><div class='hunk'>@@ -113,7 +108,7 @@ enum dentist_divider_range {</div><div class='ctx'> 	CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)</div><div class='ctx'> </div><div class='ctx'> #define CLK_REG_LIST_DCN3()	  \</div><div class='del'>-	CLK_COMMON_REG_LIST_DCN_BASE(), \</div><div class='add'>+	SR(DENTIST_DISPCLK_CNTL), \</div><div class='ctx'> 	CLK_SRI(CLK0_CLK_PLL_REQ,   CLK02, 0), \</div><div class='ctx'> 	CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)</div><div class='ctx'> </div><div class='hunk'>@@ -171,6 +166,42 @@ enum dentist_divider_range {</div><div class='ctx'>     CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \</div><div class='ctx'>     CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT)</div><div class='ctx'> </div><div class='add'>+#define CLK_REG_LIST_DCN35()	  \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK_PLL_REQ), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK0_DFS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK1_DFS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK2_DFS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK3_DFS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK4_DFS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK5_DFS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK0_CURRENT_CNT), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK1_CURRENT_CNT), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK2_CURRENT_CNT), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK3_CURRENT_CNT), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK4_CURRENT_CNT), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK5_CURRENT_CNT), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK0_BYPASS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK1_BYPASS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK2_BYPASS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK3_BYPASS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK4_BYPASS_CNTL),\</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK5_BYPASS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK0_DS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK1_DS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK2_DS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK3_DS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK4_DS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK5_DS_CNTL), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK0_ALLOW_DS), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK1_ALLOW_DS), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK2_ALLOW_DS), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK3_ALLOW_DS), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK4_ALLOW_DS), \</div><div class='add'>+	CLK_SR_DCN35(CLK1_CLK5_ALLOW_DS), \</div><div class='add'>+	CLK_SR_DCN35(CLK5_spll_field_8), \</div><div class='add'>+	CLK_SR_DCN35(CLK6_spll_field_8), \</div><div class='add'>+	SR(DENTIST_DISPCLK_CNTL), \</div><div class='add'>+</div><div class='ctx'> #define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \</div><div class='ctx'> 	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\</div><div class='ctx'> 	CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\</div><div class='hunk'>@@ -190,41 +221,41 @@ enum dentist_divider_range {</div><div class='ctx'> 	CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\</div><div class='ctx'> 	CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)</div><div class='ctx'> </div><div class='add'>+#define CLK_REG_LIST_DCN401()	  \</div><div class='add'>+	SR(DENTIST_DISPCLK_CNTL), \</div><div class='add'>+	CLK_SR_DCN401(CLK0_CLK_PLL_REQ,   CLK01, 0), \</div><div class='add'>+	CLK_SR_DCN401(CLK0_CLK0_DFS_CNTL, CLK01, 0), \</div><div class='add'>+	CLK_SR_DCN401(CLK0_CLK1_DFS_CNTL,  CLK01, 0), \</div><div class='add'>+	CLK_SR_DCN401(CLK0_CLK2_DFS_CNTL,  CLK01, 0), \</div><div class='add'>+	CLK_SR_DCN401(CLK0_CLK3_DFS_CNTL,  CLK01, 0), \</div><div class='add'>+	CLK_SR_DCN401(CLK0_CLK4_DFS_CNTL,  CLK01, 0), \</div><div class='add'>+	CLK_SR_DCN401(CLK2_CLK2_DFS_CNTL,  CLK20, 0)</div><div class='add'>+</div><div class='add'>+#define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \</div><div class='add'>+	CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh)</div><div class='add'>+</div><div class='ctx'> #define CLK_REG_FIELD_LIST(type) \</div><div class='ctx'> 	type DPREFCLK_SRC_SEL; \</div><div class='ctx'> 	type DENTIST_DPREFCLK_WDIVIDER; \</div><div class='ctx'> 	type DENTIST_DISPCLK_WDIVIDER; \</div><div class='ctx'> 	type DENTIST_DISPCLK_CHG_DONE;</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- ***************************************************************************************</div><div class='del'>- ****************** Clock Manager Private Structures ***********************************</div><div class='del'>- ***************************************************************************************</div><div class='del'>- */</div><div class='ctx'> #define CLK20_REG_FIELD_LIST(type) \</div><div class='ctx'> 	type DENTIST_DPPCLK_WDIVIDER; \</div><div class='ctx'> 	type DENTIST_DPPCLK_CHG_DONE; \</div><div class='ctx'> 	type FbMult_int; \</div><div class='ctx'> 	type FbMult_frac;</div><div class='ctx'> </div><div class='del'>-#define VBIOS_SMU_REG_FIELD_LIST(type) \</div><div class='del'>-	type CONTENT;</div><div class='del'>-</div><div class='del'>-struct clk_mgr_shift {</div><div class='del'>-	CLK_REG_FIELD_LIST(uint8_t)</div><div class='del'>-	CLK20_REG_FIELD_LIST(uint8_t)</div><div class='del'>-	VBIOS_SMU_REG_FIELD_LIST(uint32_t)</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct clk_mgr_mask {</div><div class='del'>-	CLK_REG_FIELD_LIST(uint32_t)</div><div class='del'>-	CLK20_REG_FIELD_LIST(uint32_t)</div><div class='del'>-	VBIOS_SMU_REG_FIELD_LIST(uint32_t)</div><div class='del'>-};</div><div class='add'>+/*</div><div class='add'>+ ***************************************************************************************</div><div class='add'>+ ****************** Clock Manager Private Structures ***********************************</div><div class='add'>+ ***************************************************************************************</div><div class='add'>+ */</div><div class='ctx'> </div><div class='ctx'> struct clk_mgr_registers {</div><div class='ctx'> 	uint32_t DPREFCLK_CNTL;</div><div class='ctx'> 	uint32_t DENTIST_DISPCLK_CNTL;</div><div class='add'>+</div><div class='ctx'> 	uint32_t CLK4_CLK2_CURRENT_CNT;</div><div class='ctx'> 	uint32_t CLK4_CLK_PLL_REQ;</div><div class='ctx'> </div><div class='hunk'>@@ -242,21 +273,52 @@ struct clk_mgr_registers {</div><div class='ctx'> 	uint32_t CLK1_CLK2_DFS_CNTL;</div><div class='ctx'> 	uint32_t CLK1_CLK3_DFS_CNTL;</div><div class='ctx'> 	uint32_t CLK1_CLK4_DFS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK5_DFS_CNTL;</div><div class='add'>+	uint32_t CLK2_CLK2_DFS_CNTL;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t CLK1_CLK0_CURRENT_CNT;</div><div class='ctx'>     uint32_t CLK1_CLK1_CURRENT_CNT;</div><div class='ctx'>     uint32_t CLK1_CLK2_CURRENT_CNT;</div><div class='ctx'>     uint32_t CLK1_CLK3_CURRENT_CNT;</div><div class='ctx'>     uint32_t CLK1_CLK4_CURRENT_CNT;</div><div class='add'>+	uint32_t CLK1_CLK5_CURRENT_CNT;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t CLK0_CLK0_DFS_CNTL;</div><div class='ctx'> 	uint32_t CLK0_CLK1_DFS_CNTL;</div><div class='ctx'> 	uint32_t CLK0_CLK3_DFS_CNTL;</div><div class='ctx'> 	uint32_t CLK0_CLK4_DFS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK0_BYPASS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK1_BYPASS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK2_BYPASS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK3_BYPASS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK4_BYPASS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK5_BYPASS_CNTL;</div><div class='add'>+</div><div class='add'>+	uint32_t CLK1_CLK0_DS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK1_DS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK2_DS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK3_DS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK4_DS_CNTL;</div><div class='add'>+	uint32_t CLK1_CLK5_DS_CNTL;</div><div class='add'>+</div><div class='add'>+	uint32_t CLK1_CLK0_ALLOW_DS;</div><div class='add'>+	uint32_t CLK1_CLK1_ALLOW_DS;</div><div class='add'>+	uint32_t CLK1_CLK2_ALLOW_DS;</div><div class='add'>+	uint32_t CLK1_CLK3_ALLOW_DS;</div><div class='add'>+	uint32_t CLK1_CLK4_ALLOW_DS;</div><div class='add'>+	uint32_t CLK1_CLK5_ALLOW_DS;</div><div class='add'>+	uint32_t CLK5_spll_field_8;</div><div class='add'>+	uint32_t CLK6_spll_field_8;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	uint32_t MP1_SMN_C2PMSG_67;</div><div class='del'>-	uint32_t MP1_SMN_C2PMSG_83;</div><div class='del'>-	uint32_t MP1_SMN_C2PMSG_91;</div><div class='add'>+struct clk_mgr_shift {</div><div class='add'>+	CLK_REG_FIELD_LIST(uint8_t)</div><div class='add'>+	CLK20_REG_FIELD_LIST(uint8_t)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct clk_mgr_mask {</div><div class='add'>+	CLK_REG_FIELD_LIST(uint32_t)</div><div class='add'>+	CLK20_REG_FIELD_LIST(uint32_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum clock_type {</div><div class='hunk'>@@ -349,7 +411,7 @@ struct clk_mgr_internal {</div><div class='ctx'> 	enum dm_pp_clocks_state cur_min_clks_state;</div><div class='ctx'> 	bool periodic_retraining_disabled;</div><div class='ctx'> </div><div class='del'>-	unsigned int cur_phyclk_req_table[MAX_PIPES * 2];</div><div class='add'>+	unsigned int cur_phyclk_req_table[MAX_LINKS];</div><div class='ctx'> </div><div class='ctx'> 	bool smu_present;</div><div class='ctx'> 	void *wm_range_table;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h<br/>index 45645f9fd86c..7ce2f417f86a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h</a></div><div class='hunk'>@@ -57,9 +57,9 @@ struct cursor_attribute_cache_hubp {</div><div class='ctx'> 	} size;</div><div class='ctx'> 	union    reg_cursor_settings_cfg {</div><div class='ctx'> 		struct {</div><div class='del'>-			uint32_t     dst_y_offset: 8;</div><div class='del'>-			uint32_t chunk_hdl_adjust: 2;</div><div class='del'>-			uint32_t         reserved: 22;</div><div class='add'>+			uint32_t              dst_y_offset: 8;</div><div class='add'>+			uint32_t          chunk_hdl_adjust: 2;</div><div class='add'>+			uint32_t                  reserved: 22;</div><div class='ctx'> 		} bits;</div><div class='ctx'> 		uint32_t raw;</div><div class='ctx'> 	} settings;</div><div class='hunk'>@@ -83,12 +83,34 @@ union reg_cur0_control_cfg {</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint32_t raw;</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> struct cursor_position_cache_dpp {</div><div class='ctx'> 	union reg_cur0_control_cfg cur0_ctl;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct cursor_attribute_cache_dpp {</div><div class='ctx'> 	union reg_cur0_control_cfg cur0_ctl;</div><div class='add'>+	union reg_cur0_fp_scale_bias {</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t  fp_bias: 16;</div><div class='add'>+			uint32_t fp_scale: 16;</div><div class='add'>+		} bits;</div><div class='add'>+		uint32_t raw;</div><div class='add'>+	} fp_scale_bias;</div><div class='add'>+	union reg_cur0_fp_scale_bias_g_y {</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t  fp_bias_g_y: 16;</div><div class='add'>+			uint32_t fp_scale_g_y: 16;</div><div class='add'>+		} bits;</div><div class='add'>+		uint32_t raw;</div><div class='add'>+	} fp_scale_bias_g_y;</div><div class='add'>+	union reg_cur0_fp_scale_bias_rb_crcb {</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t  fp_bias_rb_crcb: 16;</div><div class='add'>+			uint32_t fp_scale_rb_crcb: 16;</div><div class='add'>+		} bits;</div><div class='add'>+		uint32_t raw;</div><div class='add'>+	} fp_scale_bias_rb_crcb;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct cursor_attributes_cfg {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h<br/>index b9a06bf84cc9..500a601e99b5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h</a></div><div class='hunk'>@@ -59,6 +59,7 @@ enum dentist_dispclk_change_mode {</div><div class='ctx'> struct dp_dto_params {</div><div class='ctx'> 	int otg_inst;</div><div class='ctx'> 	enum signal_type signal;</div><div class='add'>+	enum streamclk_source clk_src;</div><div class='ctx'> 	uint64_t pixclk_hz;</div><div class='ctx'> 	uint64_t refclk_hz;</div><div class='ctx'> };</div><div class='hunk'>@@ -70,6 +71,125 @@ enum pixel_rate_div {</div><div class='ctx'>    PIXEL_RATE_DIV_NA = 0xF</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn_dccg_reg_state {</div><div class='add'>+	uint32_t dc_mem_global_pwr_req_cntl;</div><div class='add'>+	uint32_t dccg_audio_dtbclk_dto_modulo;</div><div class='add'>+	uint32_t dccg_audio_dtbclk_dto_phase;</div><div class='add'>+	uint32_t dccg_audio_dto_source;</div><div class='add'>+	uint32_t dccg_audio_dto0_module;</div><div class='add'>+	uint32_t dccg_audio_dto0_phase;</div><div class='add'>+	uint32_t dccg_audio_dto1_module;</div><div class='add'>+	uint32_t dccg_audio_dto1_phase;</div><div class='add'>+	uint32_t dccg_cac_status;</div><div class='add'>+	uint32_t dccg_cac_status2;</div><div class='add'>+	uint32_t dccg_disp_cntl_reg;</div><div class='add'>+	uint32_t dccg_ds_cntl;</div><div class='add'>+	uint32_t dccg_ds_dto_incr;</div><div class='add'>+	uint32_t dccg_ds_dto_modulo;</div><div class='add'>+	uint32_t dccg_ds_hw_cal_interval;</div><div class='add'>+	uint32_t dccg_gate_disable_cntl;</div><div class='add'>+	uint32_t dccg_gate_disable_cntl2;</div><div class='add'>+	uint32_t dccg_gate_disable_cntl3;</div><div class='add'>+	uint32_t dccg_gate_disable_cntl4;</div><div class='add'>+	uint32_t dccg_gate_disable_cntl5;</div><div class='add'>+	uint32_t dccg_gate_disable_cntl6;</div><div class='add'>+	uint32_t dccg_global_fgcg_rep_cntl;</div><div class='add'>+	uint32_t dccg_gtc_cntl;</div><div class='add'>+	uint32_t dccg_gtc_current;</div><div class='add'>+	uint32_t dccg_gtc_dto_incr;</div><div class='add'>+	uint32_t dccg_gtc_dto_modulo;</div><div class='add'>+	uint32_t dccg_perfmon_cntl;</div><div class='add'>+	uint32_t dccg_perfmon_cntl2;</div><div class='add'>+	uint32_t dccg_soft_reset;</div><div class='add'>+	uint32_t dccg_test_clk_sel;</div><div class='add'>+	uint32_t dccg_vsync_cnt_ctrl;</div><div class='add'>+	uint32_t dccg_vsync_cnt_int_ctrl;</div><div class='add'>+	uint32_t dccg_vsync_otg0_latch_value;</div><div class='add'>+	uint32_t dccg_vsync_otg1_latch_value;</div><div class='add'>+	uint32_t dccg_vsync_otg2_latch_value;</div><div class='add'>+	uint32_t dccg_vsync_otg3_latch_value;</div><div class='add'>+	uint32_t dccg_vsync_otg4_latch_value;</div><div class='add'>+	uint32_t dccg_vsync_otg5_latch_value;</div><div class='add'>+	uint32_t dispclk_cgtt_blk_ctrl_reg;</div><div class='add'>+	uint32_t dispclk_freq_change_cntl;</div><div class='add'>+	uint32_t dp_dto_dbuf_en;</div><div class='add'>+	uint32_t dp_dto0_modulo;</div><div class='add'>+	uint32_t dp_dto0_phase;</div><div class='add'>+	uint32_t dp_dto1_modulo;</div><div class='add'>+	uint32_t dp_dto1_phase;</div><div class='add'>+	uint32_t dp_dto2_modulo;</div><div class='add'>+	uint32_t dp_dto2_phase;</div><div class='add'>+	uint32_t dp_dto3_modulo;</div><div class='add'>+	uint32_t dp_dto3_phase;</div><div class='add'>+	uint32_t dpiaclk_540m_dto_modulo;</div><div class='add'>+	uint32_t dpiaclk_540m_dto_phase;</div><div class='add'>+	uint32_t dpiaclk_810m_dto_modulo;</div><div class='add'>+	uint32_t dpiaclk_810m_dto_phase;</div><div class='add'>+	uint32_t dpiaclk_dto_cntl;</div><div class='add'>+	uint32_t dpiasymclk_cntl;</div><div class='add'>+	uint32_t dppclk_cgtt_blk_ctrl_reg;</div><div class='add'>+	uint32_t dppclk_ctrl;</div><div class='add'>+	uint32_t dppclk_dto_ctrl;</div><div class='add'>+	uint32_t dppclk0_dto_param;</div><div class='add'>+	uint32_t dppclk1_dto_param;</div><div class='add'>+	uint32_t dppclk2_dto_param;</div><div class='add'>+	uint32_t dppclk3_dto_param;</div><div class='add'>+	uint32_t dprefclk_cgtt_blk_ctrl_reg;</div><div class='add'>+	uint32_t dprefclk_cntl;</div><div class='add'>+	uint32_t dpstreamclk_cntl;</div><div class='add'>+	uint32_t dscclk_dto_ctrl;</div><div class='add'>+	uint32_t dscclk0_dto_param;</div><div class='add'>+	uint32_t dscclk1_dto_param;</div><div class='add'>+	uint32_t dscclk2_dto_param;</div><div class='add'>+	uint32_t dscclk3_dto_param;</div><div class='add'>+	uint32_t dtbclk_dto_dbuf_en;</div><div class='add'>+	uint32_t dtbclk_dto0_modulo;</div><div class='add'>+	uint32_t dtbclk_dto0_phase;</div><div class='add'>+	uint32_t dtbclk_dto1_modulo;</div><div class='add'>+	uint32_t dtbclk_dto1_phase;</div><div class='add'>+	uint32_t dtbclk_dto2_modulo;</div><div class='add'>+	uint32_t dtbclk_dto2_phase;</div><div class='add'>+	uint32_t dtbclk_dto3_modulo;</div><div class='add'>+	uint32_t dtbclk_dto3_phase;</div><div class='add'>+	uint32_t dtbclk_p_cntl;</div><div class='add'>+	uint32_t force_symclk_disable;</div><div class='add'>+	uint32_t hdmicharclk0_clock_cntl;</div><div class='add'>+	uint32_t hdmistreamclk_cntl;</div><div class='add'>+	uint32_t hdmistreamclk0_dto_param;</div><div class='add'>+	uint32_t microsecond_time_base_div;</div><div class='add'>+	uint32_t millisecond_time_base_div;</div><div class='add'>+	uint32_t otg_pixel_rate_div;</div><div class='add'>+	uint32_t otg0_phypll_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg0_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg1_phypll_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg1_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg2_phypll_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg2_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg3_phypll_pixel_rate_cntl;</div><div class='add'>+	uint32_t otg3_pixel_rate_cntl;</div><div class='add'>+	uint32_t phyasymclk_clock_cntl;</div><div class='add'>+	uint32_t phybsymclk_clock_cntl;</div><div class='add'>+	uint32_t phycsymclk_clock_cntl;</div><div class='add'>+	uint32_t phydsymclk_clock_cntl;</div><div class='add'>+	uint32_t phyesymclk_clock_cntl;</div><div class='add'>+	uint32_t phyplla_pixclk_resync_cntl;</div><div class='add'>+	uint32_t phypllb_pixclk_resync_cntl;</div><div class='add'>+	uint32_t phypllc_pixclk_resync_cntl;</div><div class='add'>+	uint32_t phyplld_pixclk_resync_cntl;</div><div class='add'>+	uint32_t phyplle_pixclk_resync_cntl;</div><div class='add'>+	uint32_t refclk_cgtt_blk_ctrl_reg;</div><div class='add'>+	uint32_t socclk_cgtt_blk_ctrl_reg;</div><div class='add'>+	uint32_t symclk_cgtt_blk_ctrl_reg;</div><div class='add'>+	uint32_t symclk_psp_cntl;</div><div class='add'>+	uint32_t symclk32_le_cntl;</div><div class='add'>+	uint32_t symclk32_se_cntl;</div><div class='add'>+	uint32_t symclka_clock_enable;</div><div class='add'>+	uint32_t symclkb_clock_enable;</div><div class='add'>+	uint32_t symclkc_clock_enable;</div><div class='add'>+	uint32_t symclkd_clock_enable;</div><div class='add'>+	uint32_t symclke_clock_enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dccg {</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='ctx'> 	const struct dccg_funcs *funcs;</div><div class='hunk'>@@ -80,7 +200,6 @@ struct dccg {</div><div class='ctx'> 	//int audio_dtbclk_khz;/* TODO needs to be removed */</div><div class='ctx'> 	//int ref_dtbclk_khz;/* TODO needs to be removed */</div><div class='ctx'> };</div><div class='del'>-</div><div class='ctx'> struct dtbclk_dto_params {</div><div class='ctx'> 	const struct dc_crtc_timing *timing;</div><div class='ctx'> 	int otg_inst;</div><div class='hunk'>@@ -105,6 +224,10 @@ struct dccg_funcs {</div><div class='ctx'> 	void (*otg_drop_pixel)(struct dccg *dccg,</div><div class='ctx'> 			uint32_t otg_inst);</div><div class='ctx'> 	void (*dccg_init)(struct dccg *dccg);</div><div class='add'>+	void (*set_dpstreamclk_root_clock_gating)(</div><div class='add'>+			struct dccg *dccg,</div><div class='add'>+			int dp_hpo_inst,</div><div class='add'>+			bool enable);</div><div class='ctx'> </div><div class='ctx'> 	void (*set_dpstreamclk)(</div><div class='ctx'> 			struct dccg *dccg,</div><div class='hunk'>@@ -171,6 +294,11 @@ struct dccg_funcs {</div><div class='ctx'> 			enum pixel_rate_div k1,</div><div class='ctx'> 			enum pixel_rate_div k2);</div><div class='ctx'> </div><div class='add'>+	void (*get_pixel_rate_div)(struct dccg *dccg,</div><div class='add'>+			uint32_t otg_inst,</div><div class='add'>+			uint32_t *div_factor1,</div><div class='add'>+			uint32_t *div_factor2);</div><div class='add'>+</div><div class='ctx'> 	void (*set_valid_pixel_rate)(</div><div class='ctx'> 			struct dccg *dccg,</div><div class='ctx'> 			int ref_dtbclk_khz,</div><div class='hunk'>@@ -201,10 +329,10 @@ struct dccg_funcs {</div><div class='ctx'> 			struct dccg *dccg,</div><div class='ctx'> 			enum streamclk_source src,</div><div class='ctx'> 			uint32_t otg_inst);</div><div class='del'>-	void (*set_dto_dscclk)(</div><div class='del'>-			struct dccg *dccg,</div><div class='del'>-			uint32_t dsc_inst);</div><div class='add'>+	void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);</div><div class='ctx'> 	void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);</div><div class='add'>+	void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);</div><div class='add'>+	void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif //__DAL_DCCG_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h<br/>index 2ae7484d18af..1ddfa30411c8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h</a></div><div class='hunk'>@@ -33,11 +33,17 @@</div><div class='ctx'>  * blocks for the Data Fabric Interface that are not clock/power gated.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include "dc/dc_hw_types.h"</div><div class='add'>+</div><div class='ctx'> enum dcc_control {</div><div class='ctx'> 	dcc_control__256_256_xxx,</div><div class='ctx'> 	dcc_control__128_128_xxx,</div><div class='ctx'> 	dcc_control__256_64_64,</div><div class='ctx'> 	dcc_control__256_128_128,</div><div class='add'>+	dcc_control__256_256,</div><div class='add'>+	dcc_control__256_128,</div><div class='add'>+	dcc_control__256_64,</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum segment_order {</div><div class='hunk'>@@ -72,8 +78,15 @@ enum dcn_hubbub_page_table_depth {</div><div class='ctx'> </div><div class='ctx'> enum dcn_hubbub_page_table_block_size {</div><div class='ctx'> 	DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3,</div><div class='ctx'> 	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,</div><div class='del'>-	DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8,</div><div class='add'>+	DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn_hubbub_phys_addr_config {</div><div class='hunk'>@@ -124,6 +137,27 @@ struct dcn_hubbub_state {</div><div class='ctx'> 	uint32_t dram_state_cntl;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn_hubbub_reg_state {</div><div class='add'>+	uint32_t det0_ctrl;</div><div class='add'>+	uint32_t det1_ctrl;</div><div class='add'>+	uint32_t det2_ctrl;</div><div class='add'>+	uint32_t det3_ctrl;</div><div class='add'>+	uint32_t compbuf_ctrl;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubbub_system_latencies {</div><div class='add'>+	uint32_t max_latency_ns;</div><div class='add'>+	uint32_t avg_latency_ns;</div><div class='add'>+	uint32_t min_latency_ns;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubbub_urgent_latency_params {</div><div class='add'>+	uint32_t refclk_mhz;</div><div class='add'>+	uint32_t t_win_ns;</div><div class='add'>+	uint32_t bandwidth_mbps;</div><div class='add'>+	uint32_t bw_factor_x1000;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct hubbub_funcs {</div><div class='ctx'> 	void (*update_dchub)(</div><div class='ctx'> 			struct hubbub *hubbub,</div><div class='hunk'>@@ -147,6 +181,17 @@ struct hubbub_funcs {</div><div class='ctx'> 			enum segment_order *segment_order_horz,</div><div class='ctx'> 			enum segment_order *segment_order_vert);</div><div class='ctx'> </div><div class='add'>+	bool (*dcc_support_swizzle_addr3)(</div><div class='add'>+			enum swizzle_mode_addr3_values swizzle,</div><div class='add'>+			unsigned int plane_pitch,</div><div class='add'>+			unsigned int bytes_per_element,</div><div class='add'>+			enum segment_order *segment_order_horz,</div><div class='add'>+			enum segment_order *segment_order_vert);</div><div class='add'>+</div><div class='add'>+	bool (*dcc_support_pixel_format_plane0_plane1)(</div><div class='add'>+			enum surface_pixel_format format,</div><div class='add'>+			unsigned int *plane0_bpe,</div><div class='add'>+			unsigned int *plane1_bpe);</div><div class='ctx'> 	bool (*dcc_support_pixel_format)(</div><div class='ctx'> 			enum surface_pixel_format format,</div><div class='ctx'> 			unsigned int *bytes_per_element);</div><div class='hunk'>@@ -160,7 +205,7 @@ struct hubbub_funcs {</div><div class='ctx'> </div><div class='ctx'> 	bool (*program_watermarks)(</div><div class='ctx'> 			struct hubbub *hubbub,</div><div class='del'>-			struct dcn_watermark_set *watermarks,</div><div class='add'>+			union dcn_watermark_set *watermarks,</div><div class='ctx'> 			unsigned int refclk_mhz,</div><div class='ctx'> 			bool safe_to_lower);</div><div class='ctx'> </div><div class='hunk'>@@ -179,6 +224,8 @@ struct hubbub_funcs {</div><div class='ctx'> </div><div class='ctx'> 	void (*init_watermarks)(struct hubbub *hubbub);</div><div class='ctx'> </div><div class='add'>+	void (*hubbub_read_reg_state)(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state);</div><div class='add'>+</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * @program_det_size:</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -201,6 +248,43 @@ struct hubbub_funcs {</div><div class='ctx'> 	void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel);</div><div class='ctx'> 	void (*dchubbub_init)(struct hubbub *hubbub);</div><div class='ctx'> 	void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use);</div><div class='add'>+	void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg);</div><div class='add'>+	void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);</div><div class='add'>+	void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst);</div><div class='add'>+	bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower);</div><div class='add'>+	void (*dchvm_init)(struct hubbub *hubbub);</div><div class='add'>+</div><div class='add'>+	struct hubbub_perfmon_funcs {</div><div class='add'>+		void (*reset)(struct hubbub *hubbub);</div><div class='add'>+		void (*start_measuring_max_memory_latency_ns)(</div><div class='add'>+				struct hubbub *hubbub);</div><div class='add'>+		uint32_t (*get_max_memory_latency_ns)(struct hubbub *hubbub,</div><div class='add'>+				uint32_t refclk_mhz, uint32_t *sample_count);</div><div class='add'>+		void (*start_measuring_average_memory_latency_ns)(</div><div class='add'>+				struct hubbub *hubbub);</div><div class='add'>+		uint32_t (*get_average_memory_latency_ns)(struct hubbub *hubbub,</div><div class='add'>+				uint32_t refclk_mhz, uint32_t *sample_count);</div><div class='add'>+		void (*start_measuring_urgent_ramp_latency_ns)(</div><div class='add'>+				struct hubbub *hubbub,</div><div class='add'>+				const struct hubbub_urgent_latency_params *params);</div><div class='add'>+		uint32_t (*get_urgent_ramp_latency_ns)(struct hubbub *hubbub,</div><div class='add'>+				uint32_t refclk_mhz);</div><div class='add'>+		void (*start_measuring_unbounded_bandwidth_mbps)(</div><div class='add'>+				struct hubbub *hubbub);</div><div class='add'>+		uint32_t (*get_unbounded_bandwidth_mbps)(struct hubbub *hubbub,</div><div class='add'>+				uint32_t refclk_mhz, uint32_t *duration_ns);</div><div class='add'>+		void (*start_measuring_average_bandwidth_mbps)(</div><div class='add'>+				struct hubbub *hubbub);</div><div class='add'>+		uint32_t (*get_average_bandwidth_mbps)(struct hubbub *hubbub,</div><div class='add'>+				uint32_t refclk_mhz, uint32_t min_duration_ns,</div><div class='add'>+				uint32_t *duration_ns);</div><div class='add'>+	} perfmon;</div><div class='add'>+</div><div class='add'>+	struct hubbub_qos_funcs {</div><div class='add'>+		void (*force_display_nominal_profile)(struct hubbub *hubbub);</div><div class='add'>+		void (*force_display_urgent_profile)(struct hubbub *hubbub);</div><div class='add'>+		void (*reset_display_qos_profile)(struct hubbub *hubbub);</div><div class='add'>+	} qos;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct hubbub {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h<br/>index 0f24afbf4388..d88b57d4f512 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h</a></div><div class='hunk'>@@ -65,7 +65,6 @@ union defer_reg_writes {</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint32_t raw;</div><div class='ctx'> };</div><div class='del'>-</div><div class='ctx'> struct dpp {</div><div class='ctx'> 	const struct dpp_funcs *funcs;</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='hunk'>@@ -84,6 +83,7 @@ struct dpp {</div><div class='ctx'> </div><div class='ctx'> 	struct pwl_params shaper_params;</div><div class='ctx'> 	bool cm_bypass_mode;</div><div class='add'>+	bool cursor_offload;</div><div class='ctx'> </div><div class='ctx'> 	struct cursor_position_cache_dpp  pos;</div><div class='ctx'> 	struct cursor_attribute_cache_dpp att;</div><div class='hunk'>@@ -119,10 +119,14 @@ static const struct dpp_input_csc_matrix __maybe_unused dpp_input_csc_matrix[] =</div><div class='ctx'> 		{ 0x39a6, 0x2568, 0,      0xe0d6,</div><div class='ctx'> 		  0xeedd, 0x2568, 0xf925, 0x9a8,</div><div class='ctx'> 		  0,      0x2568, 0x43ee, 0xdbb2 } },</div><div class='del'>-	{ COLOR_SPACE_2020_YCBCR,</div><div class='add'>+	{ COLOR_SPACE_2020_YCBCR_FULL,</div><div class='ctx'> 		{ 0x2F30, 0x2000, 0,      0xE869,</div><div class='ctx'> 		  0xEDB7, 0x2000, 0xFABC, 0xBC6,</div><div class='ctx'> 		  0,      0x2000, 0x3C34, 0xE1E6 } },</div><div class='add'>+	{ COLOR_SPACE_2020_YCBCR_LIMITED,</div><div class='add'>+		{ 0x35B9, 0x2543, 0,      0xE2B2,</div><div class='add'>+		  0xEB2F, 0x2543, 0xFA01, 0x0B1F,</div><div class='add'>+		  0,      0x2543, 0x4489, 0xDB42 } },</div><div class='ctx'> 	{ COLOR_SPACE_2020_RGB_LIMITEDRANGE,</div><div class='ctx'> 		{ 0x35E0, 0x255F, 0,      0xE2B3,</div><div class='ctx'> 		  0xEB20, 0x255F, 0xF9FD, 0xB1E,</div><div class='hunk'>@@ -147,16 +151,28 @@ struct cnv_color_keyer_params {</div><div class='ctx'> 	int color_keyer_blue_high;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* new for dcn2: set the 8bit alpha values based on the 2 bit alpha</div><div class='del'>- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0   default: 0b00000000</div><div class='del'>- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1   default: 0b01010101</div><div class='del'>- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2   default: 0b10101010</div><div class='del'>- *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3   default: 0b11111111</div><div class='add'>+/**</div><div class='add'>+ * struct cnv_alpha_2bit_lut - Set the 8bit alpha values based on the 2 bit alpha</div><div class='ctx'>  */</div><div class='ctx'> struct cnv_alpha_2bit_lut {</div><div class='add'>+	/**</div><div class='add'>+	* @lut0: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000</div><div class='add'>+	*/</div><div class='ctx'> 	int lut0;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @lut1: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101</div><div class='add'>+	 */</div><div class='ctx'> 	int lut1;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @lut2: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010</div><div class='add'>+	 */</div><div class='ctx'> 	int lut2;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @lut3: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111</div><div class='add'>+	 */</div><div class='ctx'> 	int lut3;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -186,6 +202,19 @@ struct dcn_dpp_state {</div><div class='ctx'> 	uint32_t gamcor_mode;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn_dpp_reg_state {</div><div class='add'>+	uint32_t recout_start;</div><div class='add'>+	uint32_t recout_size;</div><div class='add'>+	uint32_t scl_horz_filter_scale_ratio;</div><div class='add'>+	uint32_t scl_vert_filter_scale_ratio;</div><div class='add'>+	uint32_t scl_mode;</div><div class='add'>+	uint32_t cm_control;</div><div class='add'>+	uint32_t dpp_control;</div><div class='add'>+	uint32_t dscl_control;</div><div class='add'>+	uint32_t obuf_control;</div><div class='add'>+	uint32_t mpc_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct CM_bias_params {</div><div class='ctx'> 	uint32_t cm_bias_cr_r;</div><div class='ctx'> 	uint32_t cm_bias_y_g;</div><div class='hunk'>@@ -209,6 +238,8 @@ struct dpp_funcs {</div><div class='ctx'> </div><div class='ctx'> 	void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);</div><div class='ctx'> </div><div class='add'>+	void (*dpp_read_reg_state)(struct dpp *dpp, struct dcn_dpp_reg_state *dpp_reg_state);</div><div class='add'>+</div><div class='ctx'> 	void (*dpp_reset)(struct dpp *dpp);</div><div class='ctx'> </div><div class='ctx'> 	void (*dpp_set_scaler)(struct dpp *dpp,</div><div class='hunk'>@@ -322,13 +353,20 @@ struct dpp_funcs {</div><div class='ctx'> 			const struct pwl_params *params);</div><div class='ctx'> 	bool (*dpp_program_3dlut)(</div><div class='ctx'> 			struct dpp *dpp,</div><div class='del'>-			struct tetrahedral_params *params);</div><div class='add'>+			const struct tetrahedral_params *params);</div><div class='ctx'> 	void (*dpp_cnv_set_alpha_keyer)(</div><div class='ctx'> 			struct dpp *dpp_base,</div><div class='ctx'> 			struct cnv_color_keyer_params *color_keyer);</div><div class='ctx'> </div><div class='ctx'> 	void (*dpp_get_gamut_remap)(struct dpp *dpp_base,</div><div class='ctx'> 				    struct dpp_grph_csc_adjustment *adjust);</div><div class='add'>+	void (*set_cursor_matrix)(</div><div class='add'>+		struct dpp *dpp_base,</div><div class='add'>+		enum dc_color_space color_space,</div><div class='add'>+		struct dc_csc_transform cursor_csc_color_matrix);</div><div class='add'>+</div><div class='add'>+	void (*dpp_force_disable_cursor)(struct dpp *dpp_base);</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h<br/>index 729ca0064e94..063efc8128a7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h</a></div><div class='hunk'>@@ -147,9 +147,10 @@ struct dwb_caps {</div><div class='ctx'> 		unsigned int support_ogam	:1;</div><div class='ctx'> 		unsigned int support_wbscl	:1;</div><div class='ctx'> 		unsigned int support_ocsc	:1;</div><div class='del'>-		unsigned int support_stereo :1;</div><div class='add'>+		unsigned int support_stereo	:1;</div><div class='add'>+		unsigned int support_4k_120p	:1;</div><div class='ctx'> 	} caps;</div><div class='del'>-	unsigned int	 reserved2[9];	/* Reserved for future use, MUST BE 0. */</div><div class='add'>+	unsigned int	 reserved2[10];	/* Reserved for future use, MUST BE 0. */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dwbc {</div><div class='hunk'>@@ -166,8 +167,9 @@ struct dwbc {</div><div class='ctx'> 	bool dwb_is_drc;</div><div class='ctx'> 	int wb_src_plane_inst;/*hubp, mpcc, inst*/</div><div class='ctx'> 	uint32_t mask_id;</div><div class='del'>-    int otg_inst;</div><div class='del'>-    bool mvc_cfg;</div><div class='add'>+	int otg_inst;</div><div class='add'>+	bool mvc_cfg;</div><div class='add'>+	struct dc_dwb_params params;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dwbc_funcs {</div><div class='hunk'>@@ -192,6 +194,10 @@ struct dwbc_funcs {</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		enum dwb_frame_capture_enable enable);</div><div class='ctx'> </div><div class='add'>+	void (*dwb_set_scaler)(</div><div class='add'>+		struct dwbc *dwbc,</div><div class='add'>+		struct dc_dwb_params *params);</div><div class='add'>+</div><div class='ctx'> 	void (*set_stereo)(</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		struct dwb_stereo_params *stereo_params);</div><div class='hunk'>@@ -205,9 +211,11 @@ struct dwbc_funcs {</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		struct dwb_warmup_params *warmup_params);</div><div class='ctx'> </div><div class='del'>-</div><div class='add'>+	bool (*dwb_get_mcifbuf_line)(</div><div class='add'>+		struct dwbc *dwbc, unsigned int *buf_idx,</div><div class='add'>+		unsigned int *cur_line,</div><div class='add'>+		unsigned int *over_run);</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='del'>-</div><div class='ctx'> 	void (*dwb_program_output_csc)(</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		enum dc_color_space color_space,</div><div class='hunk'>@@ -216,17 +224,17 @@ struct dwbc_funcs {</div><div class='ctx'> 	bool (*dwb_ogam_set_output_transfer_func)(</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		const struct dc_transfer_func *in_transfer_func_dwb_ogam);</div><div class='del'>-</div><div class='add'>+#endif</div><div class='ctx'> 	//TODO: merge with output_transfer_func?</div><div class='ctx'> 	bool (*dwb_ogam_set_input_transfer_func)(</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		const struct dc_transfer_func *in_transfer_func_dwb_ogam);</div><div class='del'>-#endif</div><div class='add'>+</div><div class='add'>+	void (*get_drr_time_stamp)(</div><div class='add'>+		struct dwbc *dwbc, uint32_t *time_stamp);</div><div class='add'>+</div><div class='ctx'> 	bool (*get_dwb_status)(</div><div class='ctx'> 		struct dwbc *dwbc);</div><div class='del'>-	void (*dwb_set_scaler)(</div><div class='del'>-		struct dwbc *dwbc,</div><div class='del'>-		struct dc_dwb_params *params);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h<br/>index 72610cd7eae0..a79019365af8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h</a></div><div class='hunk'>@@ -41,6 +41,9 @@</div><div class='ctx'> #include "mem_input.h"</div><div class='ctx'> #include "cursor_reg_cache.h"</div><div class='ctx'> </div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"</div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_types.h"</div><div class='add'>+</div><div class='ctx'> #define OPP_ID_INVALID 0xf</div><div class='ctx'> #define MAX_TTU 0xffffff</div><div class='ctx'> </div><div class='hunk'>@@ -65,6 +68,53 @@ enum hubp_ind_block_size {</div><div class='ctx'> 	hubp_ind_block_64b_no_128bcl,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum hubp_3dlut_fl_mode {</div><div class='add'>+	hubp_3dlut_fl_mode_disable = 0,</div><div class='add'>+	hubp_3dlut_fl_mode_native_1 = 1,</div><div class='add'>+	hubp_3dlut_fl_mode_native_2 = 2,</div><div class='add'>+	hubp_3dlut_fl_mode_transform = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hubp_3dlut_fl_format {</div><div class='add'>+	hubp_3dlut_fl_format_unorm_12msb_bitslice = 0,</div><div class='add'>+	hubp_3dlut_fl_format_unorm_12lsb_bitslice = 1,</div><div class='add'>+	hubp_3dlut_fl_format_float_fp1_5_10 = 2</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hubp_3dlut_fl_addressing_mode {</div><div class='add'>+	hubp_3dlut_fl_addressing_mode_sw_linear = 0,</div><div class='add'>+	hubp_3dlut_fl_addressing_mode_simple_linear = 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hubp_3dlut_fl_width {</div><div class='add'>+	hubp_3dlut_fl_width_17 = 17,</div><div class='add'>+	hubp_3dlut_fl_width_33 = 33,</div><div class='add'>+	hubp_3dlut_fl_width_transformed    = 4916, //mpc default</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hubp_3dlut_fl_crossbar_bit_slice {</div><div class='add'>+	hubp_3dlut_fl_crossbar_bit_slice_0_15 = 0,</div><div class='add'>+	hubp_3dlut_fl_crossbar_bit_slice_16_31 = 1,</div><div class='add'>+	hubp_3dlut_fl_crossbar_bit_slice_32_47 = 2,</div><div class='add'>+	hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hubp_fl_3dlut_config {</div><div class='add'>+	bool enabled;</div><div class='add'>+	enum hubp_3dlut_fl_width width;</div><div class='add'>+	enum hubp_3dlut_fl_mode mode;</div><div class='add'>+	enum hubp_3dlut_fl_format format;</div><div class='add'>+	uint16_t bias;</div><div class='add'>+	uint16_t scale;</div><div class='add'>+	struct dc_plane_address address;</div><div class='add'>+	enum hubp_3dlut_fl_addressing_mode addr_mode;</div><div class='add'>+	enum dc_cm2_gpu_mem_layout layout;</div><div class='add'>+	uint8_t protection_bits;</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g;</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b;</div><div class='add'>+	enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct hubp {</div><div class='ctx'> 	const struct hubp_funcs *funcs;</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='hunk'>@@ -76,11 +126,13 @@ struct hubp {</div><div class='ctx'> 	int mpcc_id;</div><div class='ctx'> 	struct dc_cursor_attributes curs_attr;</div><div class='ctx'> 	struct dc_cursor_position curs_pos;</div><div class='add'>+	bool cursor_offload;</div><div class='ctx'> 	bool power_gated;</div><div class='ctx'> </div><div class='ctx'> 	struct cursor_position_cache_hubp  pos;</div><div class='ctx'> 	struct cursor_attribute_cache_hubp att;</div><div class='ctx'> 	struct cursor_rect cur_rect;</div><div class='add'>+	bool use_mall_for_cursor;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct surface_flip_registers {</div><div class='hunk'>@@ -111,14 +163,26 @@ struct hubp_funcs {</div><div class='ctx'> 			struct _vcs_dpi_display_rq_regs_st *rq_regs,</div><div class='ctx'> 			struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);</div><div class='ctx'> </div><div class='add'>+	void (*hubp_setup2)(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *pipe_regs,</div><div class='add'>+		union dml2_global_sync_programming *pipe_global_sync,</div><div class='add'>+		struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='ctx'> 	void (*hubp_setup_interdependent)(</div><div class='ctx'> 			struct hubp *hubp,</div><div class='ctx'> 			struct _vcs_dpi_display_dlg_regs_st *dlg_regs,</div><div class='ctx'> 			struct _vcs_dpi_display_ttu_regs_st *ttu_regs);</div><div class='ctx'> </div><div class='add'>+	void (*hubp_setup_interdependent2)(</div><div class='add'>+		struct hubp *hubp,</div><div class='add'>+		struct dml2_dchub_per_pipe_register_set *pipe_regs);</div><div class='add'>+</div><div class='ctx'> 	void (*dcc_control)(struct hubp *hubp, bool enable,</div><div class='ctx'> 			enum hubp_ind_block_size blk_size);</div><div class='ctx'> </div><div class='add'>+	void (*hubp_reset)(struct hubp *hubp);</div><div class='add'>+</div><div class='ctx'> 	void (*mem_program_viewport)(</div><div class='ctx'> 			struct hubp *hubp,</div><div class='ctx'> 			const struct rect *viewport,</div><div class='hunk'>@@ -132,7 +196,7 @@ struct hubp_funcs {</div><div class='ctx'> 	void (*hubp_program_pte_vm)(</div><div class='ctx'> 		struct hubp *hubp,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		enum dc_rotation_angle rotation);</div><div class='ctx'> </div><div class='ctx'> 	void (*hubp_set_vm_system_aperture_settings)(</div><div class='hunk'>@@ -146,7 +210,7 @@ struct hubp_funcs {</div><div class='ctx'> 	void (*hubp_program_surface_config)(</div><div class='ctx'> 		struct hubp *hubp,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		struct plane_size *plane_size,</div><div class='ctx'> 		enum dc_rotation_angle rotation,</div><div class='ctx'> 		struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -174,6 +238,7 @@ struct hubp_funcs {</div><div class='ctx'> 	void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);</div><div class='ctx'> 	void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);</div><div class='ctx'> 	void (*hubp_read_state)(struct hubp *hubp);</div><div class='add'>+	void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);</div><div class='ctx'> 	void (*hubp_clear_underflow)(struct hubp *hubp);</div><div class='ctx'> 	void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);</div><div class='ctx'> 	unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);</div><div class='hunk'>@@ -211,17 +276,41 @@ struct hubp_funcs {</div><div class='ctx'> 	bool (*hubp_in_blank)(struct hubp *hubp);</div><div class='ctx'> 	void (*hubp_soft_reset)(struct hubp *hubp, bool reset);</div><div class='ctx'> </div><div class='add'>+	void (*hubp_set_flip_int)(struct hubp *hubp);</div><div class='add'>+</div><div class='ctx'> 	void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);</div><div class='ctx'> 	void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);</div><div class='ctx'> 	void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);</div><div class='ctx'> 	void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);</div><div class='del'>-</div><div class='del'>-	void (*hubp_set_flip_int)(struct hubp *hubp);</div><div class='add'>+	void (*hubp_surface_update_lock)(struct hubp *hubp,</div><div class='add'>+			bool lock);</div><div class='ctx'> </div><div class='ctx'> 	void (*program_extended_blank)(struct hubp *hubp,</div><div class='ctx'> 			unsigned int min_dst_y_next_start_optimized);</div><div class='ctx'> </div><div class='ctx'> 	void (*hubp_wait_pipe_read_start)(struct hubp *hubp);</div><div class='add'>+	void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);</div><div class='add'>+	void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale);</div><div class='add'>+	void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp,</div><div class='add'>+			enum hubp_3dlut_fl_mode mode);</div><div class='add'>+	void (*hubp_program_3dlut_fl_format)(struct hubp *hubp,</div><div class='add'>+			enum hubp_3dlut_fl_format format);</div><div class='add'>+	void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp,</div><div class='add'>+		const struct dc_plane_address address);</div><div class='add'>+	void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group);</div><div class='add'>+	void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);</div><div class='add'>+	void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);</div><div class='add'>+	void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width);</div><div class='add'>+	void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits);</div><div class='add'>+	void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp,</div><div class='add'>+			enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,</div><div class='add'>+			enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,</div><div class='add'>+			enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);</div><div class='add'>+	int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);</div><div class='add'>+	void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);</div><div class='add'>+	void (*hubp_clear_tiling)(struct hubp *hubp);</div><div class='add'>+	uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);</div><div class='add'>+	uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h<br/>index dcae23faeee3..a61d12ec61bc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h</a></div><div class='hunk'>@@ -44,10 +44,66 @@</div><div class='ctx'>  */</div><div class='ctx'> #define MAX_PIPES 6</div><div class='ctx'> #define MAX_PHANTOM_PIPES (MAX_PIPES / 2)</div><div class='add'>+</div><div class='add'>+#define MAX_DPIA 6</div><div class='add'>+#define MAX_CONNECTOR 6</div><div class='add'>+#define MAX_VIRTUAL_LINKS 4</div><div class='add'>+</div><div class='add'>+#define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders</div><div class='add'>+ *</div><div class='add'>+ * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7,</div><div class='add'>+ * although not every GPU may have that many.</div><div class='add'>+ */</div><div class='ctx'> #define MAX_DIG_LINK_ENCODERS 7</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders</div><div class='add'>+ *</div><div class='add'>+ * Analog encoders are ENGINE_ID_DACA/B, there are at most 2,</div><div class='add'>+ * although not every GPU may have that many. Modern GPUs typically</div><div class='add'>+ * don't have analog encoders.</div><div class='add'>+ */</div><div class='add'>+#define MAX_DAC_LINK_ENCODERS 2</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * define MAX_LINK_ENCODERS - maximum number link encoders in total</div><div class='add'>+ *</div><div class='add'>+ * This includes both analog and digital encoders.</div><div class='add'>+ */</div><div class='add'>+#define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS)</div><div class='add'>+</div><div class='ctx'> #define MAX_DWB_PIPES	1</div><div class='ctx'> #define MAX_HPO_DP2_ENCODERS	4</div><div class='del'>-#define MAX_HPO_DP2_LINK_ENCODERS	2</div><div class='add'>+#define MAX_HPO_DP2_LINK_ENCODERS	4</div><div class='add'>+</div><div class='add'>+/* Pipe topology snapshot structures */</div><div class='add'>+#define MAX_TOPOLOGY_SNAPSHOTS 4</div><div class='add'>+</div><div class='add'>+struct pipe_topology_line {</div><div class='add'>+	bool is_phantom_pipe;</div><div class='add'>+	int plane_idx;</div><div class='add'>+	int slice_idx;</div><div class='add'>+	int stream_idx;</div><div class='add'>+	int dpp_inst;</div><div class='add'>+	int opp_inst;</div><div class='add'>+	int tg_inst;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct pipe_topology_snapshot {</div><div class='add'>+	struct pipe_topology_line pipe_log_lines[MAX_PIPES];</div><div class='add'>+	int line_count;</div><div class='add'>+	uint64_t timestamp_us;</div><div class='add'>+	int stream_count;</div><div class='add'>+	int phantom_stream_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct pipe_topology_history {</div><div class='add'>+	struct pipe_topology_snapshot snapshots[MAX_TOPOLOGY_SNAPSHOTS];</div><div class='add'>+	int current_snapshot_index;</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> struct gamma_curve {</div><div class='ctx'> 	uint32_t offset;</div><div class='hunk'>@@ -216,12 +272,13 @@ enum optc_dsc_mode {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dc_bias_and_scale {</div><div class='del'>-	uint16_t scale_red;</div><div class='del'>-	uint16_t bias_red;</div><div class='del'>-	uint16_t scale_green;</div><div class='del'>-	uint16_t bias_green;</div><div class='del'>-	uint16_t scale_blue;</div><div class='del'>-	uint16_t bias_blue;</div><div class='add'>+	uint32_t scale_red;</div><div class='add'>+	uint32_t bias_red;</div><div class='add'>+	uint32_t scale_green;</div><div class='add'>+	uint32_t bias_green;</div><div class='add'>+	uint32_t scale_blue;</div><div class='add'>+	uint32_t bias_blue;</div><div class='add'>+	bool bias_and_scale_valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum test_pattern_dyn_range {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h<br/>index dbe7afa9d3a2..df512920a9fa 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h</a></div><div class='hunk'>@@ -47,6 +47,7 @@ struct encoder_init_data {</div><div class='ctx'> 	enum hpd_source_id hpd_source;</div><div class='ctx'> 	/* TODO: in DAL2, here was pointer to EventManagerInterface */</div><div class='ctx'> 	struct graphics_object_id encoder;</div><div class='add'>+	enum engine_id analog_engine;</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='ctx'> 	enum transmitter transmitter;</div><div class='ctx'> };</div><div class='hunk'>@@ -83,6 +84,7 @@ struct link_encoder {</div><div class='ctx'> 	struct graphics_object_id connector;</div><div class='ctx'> 	uint32_t output_signals;</div><div class='ctx'> 	enum engine_id preferred_engine;</div><div class='add'>+	enum engine_id analog_engine;</div><div class='ctx'> 	struct encoder_feature_support features;</div><div class='ctx'> 	enum transmitter transmitter;</div><div class='ctx'> 	enum hpd_source_id hpd_source;</div><div class='hunk'>@@ -163,12 +165,19 @@ struct link_encoder_funcs {</div><div class='ctx'> </div><div class='ctx'> 	enum signal_type (*get_dig_mode)(</div><div class='ctx'> 		struct link_encoder *enc);</div><div class='add'>+</div><div class='ctx'> 	void (*set_dio_phy_mux)(</div><div class='ctx'> 		struct link_encoder *enc,</div><div class='ctx'> 		enum encoder_type_select sel,</div><div class='ctx'> 		uint32_t hpo_inst);</div><div class='del'>-	void (*set_dig_output_mode)(</div><div class='del'>-			struct link_encoder *enc, uint8_t pix_per_container);</div><div class='add'>+	void (*enable_dpia_output)(struct link_encoder *enc,</div><div class='add'>+		const struct dc_link_settings *link_settings,</div><div class='add'>+		uint8_t dpia_id,</div><div class='add'>+		uint8_t digmode,</div><div class='add'>+		uint8_t fec_rdy);</div><div class='add'>+	void (*disable_dpia_output)(struct link_encoder *link_enc,</div><div class='add'>+		uint8_t dpia_id,</div><div class='add'>+		uint8_t digmode);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h<br/>index b72fb314d804..d468bc85566a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "include/grph_object_id.h"</div><div class='ctx'> </div><div class='ctx'> #include "dml/display_mode_structs.h"</div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"</div><div class='ctx'> </div><div class='ctx'> struct dchub_init_data;</div><div class='ctx'> struct cstate_pstate_watermarks_st {</div><div class='hunk'>@@ -45,16 +46,24 @@ struct dcn_watermarks {</div><div class='ctx'> 	uint32_t urgent_ns;</div><div class='ctx'> 	uint32_t frac_urg_bw_nom;</div><div class='ctx'> 	uint32_t frac_urg_bw_flip;</div><div class='del'>-	int32_t urgent_latency_ns;</div><div class='add'>+	uint32_t urgent_latency_ns;</div><div class='ctx'> 	struct cstate_pstate_watermarks_st cstate_pstate;</div><div class='ctx'> 	uint32_t usr_retraining_ns;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dcn_watermark_set {</div><div class='del'>-	struct dcn_watermarks a;</div><div class='del'>-	struct dcn_watermarks b;</div><div class='del'>-	struct dcn_watermarks c;</div><div class='del'>-	struct dcn_watermarks d;</div><div class='add'>+union dcn_watermark_set {</div><div class='add'>+	struct {</div><div class='add'>+		struct dcn_watermarks a;</div><div class='add'>+		struct dcn_watermarks b;</div><div class='add'>+		struct dcn_watermarks c;</div><div class='add'>+		struct dcn_watermarks d;</div><div class='add'>+	}; // legacy</div><div class='add'>+	struct {</div><div class='add'>+		struct dml2_dchub_watermark_regs a;</div><div class='add'>+		struct dml2_dchub_watermark_regs b;</div><div class='add'>+		struct dml2_dchub_watermark_regs c;</div><div class='add'>+		struct dml2_dchub_watermark_regs d;</div><div class='add'>+	} dcn4x; //dcn4+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dce_watermarks {</div><div class='hunk'>@@ -141,7 +150,7 @@ struct mem_input_funcs {</div><div class='ctx'> 	void (*mem_input_program_pte_vm)(</div><div class='ctx'> 		struct mem_input *mem_input,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		enum dc_rotation_angle rotation);</div><div class='ctx'> </div><div class='ctx'> 	void (*mem_input_set_vm_system_aperture_settings)(</div><div class='hunk'>@@ -155,7 +164,7 @@ struct mem_input_funcs {</div><div class='ctx'> 	void (*mem_input_program_surface_config)(</div><div class='ctx'> 		struct mem_input *mem_input,</div><div class='ctx'> 		enum surface_pixel_format format,</div><div class='del'>-		union dc_tiling_info *tiling_info,</div><div class='add'>+		struct dc_tiling_info *tiling_info,</div><div class='ctx'> 		struct plane_size *plane_size,</div><div class='ctx'> 		enum dc_rotation_angle rotation,</div><div class='ctx'> 		struct dc_plane_dcc_param *dcc,</div><div class='hunk'>@@ -178,6 +187,8 @@ struct mem_input_funcs {</div><div class='ctx'> 			const struct dc_cursor_position *pos,</div><div class='ctx'> 			const struct dc_cursor_mi_param *param);</div><div class='ctx'> </div><div class='add'>+	void (*mem_input_clear_tiling)(</div><div class='add'>+		struct mem_input *mem_input);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h<br/>index 34a398f23fc6..a8d1abe20f62 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h</a></div><div class='hunk'>@@ -1,4 +1,5 @@</div><div class='del'>-/* Copyright 2012-15 Advanced Micro Devices, Inc.</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2012-15 Advanced Micro Devices, Inc.</div><div class='ctx'>  *</div><div class='ctx'>  * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='ctx'>  * copy of this software and associated documentation files (the "Software"),</div><div class='hunk'>@@ -96,6 +97,39 @@ enum mpcc_alpha_blend_mode {</div><div class='ctx'> 	MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum mpcc_movable_cm_location {</div><div class='add'>+	MPCC_MOVABLE_CM_LOCATION_BEFORE,</div><div class='add'>+	MPCC_MOVABLE_CM_LOCATION_AFTER,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum MCM_LUT_XABLE {</div><div class='add'>+	MCM_LUT_DISABLE,</div><div class='add'>+	MCM_LUT_DISABLED = MCM_LUT_DISABLE,</div><div class='add'>+	MCM_LUT_ENABLE,</div><div class='add'>+	MCM_LUT_ENABLED = MCM_LUT_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum MCM_LUT_ID {</div><div class='add'>+	MCM_LUT_3DLUT,</div><div class='add'>+	MCM_LUT_1DLUT,</div><div class='add'>+	MCM_LUT_SHAPER</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_fl_3dlut_config {</div><div class='add'>+	bool enabled;</div><div class='add'>+	uint16_t width;</div><div class='add'>+	bool select_lut_bank_a;</div><div class='add'>+	uint16_t bit_depth;</div><div class='add'>+	int hubp_index;</div><div class='add'>+	uint16_t bias;</div><div class='add'>+	uint16_t scale;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union mcm_lut_params {</div><div class='add'>+	const struct pwl_params *pwl;</div><div class='add'>+	const struct tetrahedral_params *lut3d;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct mpcc_blnd_cfg - MPCC blending configuration</div><div class='ctx'>  */</div><div class='hunk'>@@ -163,6 +197,43 @@ struct mpcc_blnd_cfg {</div><div class='ctx'> struct mpc_grph_gamut_adjustment {</div><div class='ctx'> 	struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];</div><div class='ctx'> 	enum graphics_gamut_adjust_type gamut_adjust_type;</div><div class='add'>+	enum mpcc_gamut_remap_id mpcc_gamut_remap_block_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mpc_rmcm_regs {</div><div class='add'>+	uint32_t rmcm_3dlut_mem_pwr_state;</div><div class='add'>+	uint32_t rmcm_3dlut_mem_pwr_force;</div><div class='add'>+	uint32_t rmcm_3dlut_mem_pwr_dis;</div><div class='add'>+	uint32_t rmcm_3dlut_mem_pwr_mode;</div><div class='add'>+	uint32_t rmcm_3dlut_size;</div><div class='add'>+	uint32_t rmcm_3dlut_mode;</div><div class='add'>+	uint32_t rmcm_3dlut_mode_cur;</div><div class='add'>+	uint32_t rmcm_3dlut_read_sel;</div><div class='add'>+	uint32_t rmcm_3dlut_30bit_en;</div><div class='add'>+	uint32_t rmcm_3dlut_wr_en_mask;</div><div class='add'>+	uint32_t rmcm_3dlut_ram_sel;</div><div class='add'>+	uint32_t rmcm_3dlut_out_norm_factor;</div><div class='add'>+	uint32_t rmcm_3dlut_fl_sel;</div><div class='add'>+	uint32_t rmcm_3dlut_out_offset_r;</div><div class='add'>+	uint32_t rmcm_3dlut_out_scale_r;</div><div class='add'>+	uint32_t rmcm_3dlut_fl_done;</div><div class='add'>+	uint32_t rmcm_3dlut_fl_soft_underflow;</div><div class='add'>+	uint32_t rmcm_3dlut_fl_hard_underflow;</div><div class='add'>+	uint32_t rmcm_cntl;</div><div class='add'>+	uint32_t rmcm_shaper_mem_pwr_state;</div><div class='add'>+	uint32_t rmcm_shaper_mem_pwr_force;</div><div class='add'>+	uint32_t rmcm_shaper_mem_pwr_dis;</div><div class='add'>+	uint32_t rmcm_shaper_mem_pwr_mode;</div><div class='add'>+	uint32_t rmcm_shaper_lut_mode;</div><div class='add'>+	uint32_t rmcm_shaper_mode_cur;</div><div class='add'>+	uint32_t rmcm_shaper_lut_write_en_mask;</div><div class='add'>+	uint32_t rmcm_shaper_lut_write_sel;</div><div class='add'>+	uint32_t rmcm_shaper_offset_b;</div><div class='add'>+	uint32_t rmcm_shaper_scale_b;</div><div class='add'>+	uint32_t rmcm_shaper_rama_exp_region_start_b;</div><div class='add'>+	uint32_t rmcm_shaper_rama_exp_region_start_seg_b;</div><div class='add'>+	uint32_t rmcm_shaper_rama_exp_region_end_b;</div><div class='add'>+	uint32_t rmcm_shaper_rama_exp_region_end_base_b;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mpcc_sm_cfg {</div><div class='hunk'>@@ -276,39 +347,82 @@ struct mpcc_state {</div><div class='ctx'> 	uint32_t rgam_mode;</div><div class='ctx'> 	uint32_t rgam_lut;</div><div class='ctx'> 	struct mpc_grph_gamut_adjustment gamut_remap;</div><div class='add'>+	struct mpc_rmcm_regs rmcm_regs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn_mpc_reg_state {</div><div class='add'>+	uint32_t mpcc_bot_sel;</div><div class='add'>+	uint32_t mpcc_control;</div><div class='add'>+	uint32_t mpcc_status;</div><div class='add'>+	uint32_t mpcc_top_sel;</div><div class='add'>+	uint32_t mpcc_opp_id;</div><div class='add'>+	uint32_t mpcc_ogam_control;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct mpc_funcs - funcs</div><div class='ctx'>  */</div><div class='ctx'> struct mpc_funcs {</div><div class='add'>+	/**</div><div class='add'>+	* @read_mpcc_state:</div><div class='add'>+	*</div><div class='add'>+	* Read register content from given MPCC physical instance.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc - MPC context</div><div class='add'>+	* - [in] mpcc_instance - MPC context instance</div><div class='add'>+	* - [in] mpcc_state - MPC context state</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*read_mpcc_state)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int mpcc_inst,</div><div class='ctx'> 			struct mpcc_state *s);</div><div class='add'>+	/**</div><div class='add'>+    * @mpc_read_reg_state:</div><div class='add'>+    *</div><div class='add'>+    * Read MPC register state for debugging underflow purposes.</div><div class='add'>+    *</div><div class='add'>+    * Parameters:</div><div class='add'>+    *</div><div class='add'>+    * - [in] mpc - MPC context</div><div class='add'>+    * - [out] reg_state - MPC register state structure</div><div class='add'>+    *</div><div class='add'>+    * Return:</div><div class='add'>+    *</div><div class='add'>+    * void</div><div class='add'>+    */</div><div class='add'>+	void (*mpc_read_reg_state)(</div><div class='add'>+			struct mpc *mpc,</div><div class='add'>+			int mpcc_inst,</div><div class='add'>+			struct dcn_mpc_reg_state *mpc_reg_state);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @insert_plane:</div><div class='del'>-	 *</div><div class='del'>-	 * Insert DPP into MPC tree based on specified blending position.</div><div class='del'>-	 * Only used for planes that are part of blending chain for OPP output</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in/out] mpc  - MPC context.</div><div class='del'>-	 * - [in/out] tree - MPC tree structure that plane will be added to.</div><div class='del'>-	 * - [in] blnd_cfg - MPCC blending configuration for the new blending layer.</div><div class='del'>-	 * - [in] sm_cfg   - MPCC stereo mix configuration for the new blending layer.</div><div class='del'>-	 *                   stereo mix must disable for the very bottom layer of the tree config.</div><div class='del'>-	 * - [in] insert_above_mpcc - Insert new plane above this MPCC.</div><div class='del'>-	 *                          If NULL, insert as bottom plane.</div><div class='del'>-	 * - [in] dpp_id  - DPP instance for the plane to be added.</div><div class='del'>-	 * - [in] mpcc_id - The MPCC physical instance to use for blending.</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * struct mpcc* - MPCC that was added.</div><div class='del'>-	 */</div><div class='add'>+	* @insert_plane:</div><div class='add'>+	*</div><div class='add'>+	* Insert DPP into MPC tree based on specified blending position.</div><div class='add'>+	* Only used for planes that are part of blending chain for OPP output</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc  - MPC context.</div><div class='add'>+	* - [in/out] tree - MPC tree structure that plane will be added to.</div><div class='add'>+	* - [in] blnd_cfg - MPCC blending configuration for the new blending layer.</div><div class='add'>+	* - [in] sm_cfg   - MPCC stereo mix configuration for the new blending layer.</div><div class='add'>+	*                   stereo mix must disable for the very bottom layer of the tree config.</div><div class='add'>+	* - [in] insert_above_mpcc - Insert new plane above this MPCC.</div><div class='add'>+	*                          If NULL, insert as bottom plane.</div><div class='add'>+	* - [in] dpp_id  - DPP instance for the plane to be added.</div><div class='add'>+	* - [in] mpcc_id - The MPCC physical instance to use for blending.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* struct mpcc* - MPCC that was added.</div><div class='add'>+	*/</div><div class='ctx'> 	struct mpcc* (*insert_plane)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			struct mpc_tree *tree,</div><div class='hunk'>@@ -319,107 +433,117 @@ struct mpc_funcs {</div><div class='ctx'> 			int mpcc_id);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @remove_mpcc:</div><div class='del'>-	 *</div><div class='del'>-	 * Remove a specified MPCC from the MPC tree.</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in/out] mpc   - MPC context.</div><div class='del'>-	 * - [in/out] tree  - MPC tree structure that plane will be removed from.</div><div class='del'>-	 * - [in/out] mpcc  - MPCC to be removed from tree.</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * void</div><div class='del'>-	 */</div><div class='add'>+	* @remove_mpcc:</div><div class='add'>+	*</div><div class='add'>+	* Remove a specified MPCC from the MPC tree.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc   - MPC context.</div><div class='add'>+	* - [in/out] tree  - MPC tree structure that plane will be removed from.</div><div class='add'>+	* - [in/out] mpcc  - MPCC to be removed from tree.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*remove_mpcc)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			struct mpc_tree *tree,</div><div class='ctx'> 			struct mpcc *mpcc);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @mpc_init:</div><div class='del'>-	 *</div><div class='del'>-	 * Reset the MPCC HW status by disconnecting all muxes.</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in/out] mpc - MPC context.</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * void</div><div class='del'>-	 */</div><div class='add'>+	* @mpc_init:</div><div class='add'>+	*</div><div class='add'>+	* Reset the MPCC HW status by disconnecting all muxes.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*mpc_init)(struct mpc *mpc);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	* @mpc_init_single_inst:</div><div class='add'>+	*</div><div class='add'>+	* Initialize given MPCC physical instance.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] mpcc_id - The MPCC physical instance to be initialized.</div><div class='add'>+	*/</div><div class='ctx'> 	void (*mpc_init_single_inst)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			unsigned int mpcc_id);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @update_blending:</div><div class='del'>-	 *</div><div class='del'>-	 * Update the blending configuration for a specified MPCC.</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in/out] mpc - MPC context.</div><div class='del'>-	 * - [in] blnd_cfg - MPCC blending configuration.</div><div class='del'>-	 * - [in] mpcc_id  - The MPCC physical instance.</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * void</div><div class='del'>-	 */</div><div class='add'>+	* @update_blending:</div><div class='add'>+	*</div><div class='add'>+	* Update the blending configuration for a specified MPCC.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] blnd_cfg - MPCC blending configuration.</div><div class='add'>+	* - [in] mpcc_id  - The MPCC physical instance.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*update_blending)(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		struct mpcc_blnd_cfg *blnd_cfg,</div><div class='ctx'> 		int mpcc_id);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @cursor_lock:</div><div class='del'>-	 *</div><div class='del'>-	 * Lock cursor updates for the specified OPP. OPP defines the set of</div><div class='del'>-	 * MPCC that are locked together for cursor.</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in] mpc - MPC context.</div><div class='del'>-	 * - [in] opp_id  - The OPP to lock cursor updates on</div><div class='del'>-	 * - [in] lock - lock/unlock the OPP</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * void</div><div class='del'>-	 */</div><div class='add'>+	* @cursor_lock:</div><div class='add'>+	*</div><div class='add'>+	* Lock cursor updates for the specified OPP. OPP defines the set of</div><div class='add'>+	* MPCC that are locked together for cursor.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id  - The OPP to lock cursor updates on</div><div class='add'>+	* - [in] lock - lock/unlock the OPP</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*cursor_lock)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int opp_id,</div><div class='ctx'> 			bool lock);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @insert_plane_to_secondary:</div><div class='del'>-	 *</div><div class='del'>-	 * Add DPP into secondary MPC tree based on specified blending</div><div class='del'>-	 * position.  Only used for planes that are part of blending chain for</div><div class='del'>-	 * DWB output</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in/out] mpc  - MPC context.</div><div class='del'>-	 * - [in/out] tree - MPC tree structure that plane will be added to.</div><div class='del'>-	 * - [in] blnd_cfg - MPCC blending configuration for the new blending layer.</div><div class='del'>-	 * - [in] sm_cfg   - MPCC stereo mix configuration for the new blending layer.</div><div class='del'>-	 *	    stereo mix must disable for the very bottom layer of the tree config.</div><div class='del'>-	 * - [in] insert_above_mpcc - Insert new plane above this MPCC.  If</div><div class='del'>-	 *          NULL, insert as bottom plane.</div><div class='del'>-	 * - [in] dpp_id - DPP instance for the plane to be added.</div><div class='del'>-	 * - [in] mpcc_id - The MPCC physical instance to use for blending.</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * struct mpcc* - MPCC that was added.</div><div class='del'>-	 */</div><div class='add'>+	* @insert_plane_to_secondary:</div><div class='add'>+	*</div><div class='add'>+	* Add DPP into secondary MPC tree based on specified blending</div><div class='add'>+	* position.  Only used for planes that are part of blending chain for</div><div class='add'>+	* DWB output</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc  - MPC context.</div><div class='add'>+	* - [in/out] tree - MPC tree structure that plane will be added to.</div><div class='add'>+	* - [in] blnd_cfg - MPCC blending configuration for the new blending layer.</div><div class='add'>+	* - [in] sm_cfg   - MPCC stereo mix configuration for the new blending layer.</div><div class='add'>+	*	    stereo mix must disable for the very bottom layer of the tree config.</div><div class='add'>+	* - [in] insert_above_mpcc - Insert new plane above this MPCC.  If</div><div class='add'>+	*          NULL, insert as bottom plane.</div><div class='add'>+	* - [in] dpp_id - DPP instance for the plane to be added.</div><div class='add'>+	* - [in] mpcc_id - The MPCC physical instance to use for blending.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* struct mpcc* - MPCC that was added.</div><div class='add'>+	*/</div><div class='ctx'> 	struct mpcc* (*insert_plane_to_secondary)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			struct mpc_tree *tree,</div><div class='hunk'>@@ -430,81 +554,301 @@ struct mpc_funcs {</div><div class='ctx'> 			int mpcc_id);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * @remove_mpcc_from_secondary:</div><div class='del'>-	 *</div><div class='del'>-	 * Remove a specified DPP from the 'secondary' MPC tree.</div><div class='del'>-	 *</div><div class='del'>-	 * Parameters:</div><div class='del'>-	 *</div><div class='del'>-	 * - [in/out] mpc  - MPC context.</div><div class='del'>-	 * - [in/out] tree - MPC tree structure that plane will be removed from.</div><div class='del'>-	 * - [in]     mpcc - MPCC to be removed from tree.</div><div class='del'>-	 *</div><div class='del'>-	 * Return:</div><div class='del'>-	 *</div><div class='del'>-	 * void</div><div class='del'>-	 */</div><div class='add'>+	* @remove_mpcc_from_secondary:</div><div class='add'>+	*</div><div class='add'>+	* Remove a specified DPP from the 'secondary' MPC tree.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	*</div><div class='add'>+	* - [in/out] mpc  - MPC context.</div><div class='add'>+	* - [in/out] tree - MPC tree structure that plane will be removed from.</div><div class='add'>+	* - [in]     mpcc - MPCC to be removed from tree.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*remove_mpcc_from_secondary)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			struct mpc_tree *tree,</div><div class='ctx'> 			struct mpcc *mpcc);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @get_mpcc_for_dpp_from_secondary:</div><div class='add'>+	*</div><div class='add'>+	* Find, if it exists, a MPCC from a given 'secondary' MPC tree that</div><div class='add'>+	* is associated with specified plane.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] tree - MPC tree structure to search for plane.</div><div class='add'>+	* - [in] dpp_id - DPP to be searched.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* struct mpcc* - pointer to plane or NULL if no plane found.</div><div class='add'>+	*/</div><div class='ctx'> 	struct mpcc* (*get_mpcc_for_dpp_from_secondary)(</div><div class='ctx'> 			struct mpc_tree *tree,</div><div class='ctx'> 			int dpp_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @get_mpcc_for_dpp:</div><div class='add'>+	*</div><div class='add'>+	* Find, if it exists, a MPCC from a given MPC tree that</div><div class='add'>+	* is associated with specified plane.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] tree - MPC tree structure to search for plane.</div><div class='add'>+	* - [in] dpp_id - DPP to be searched.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* struct mpcc* - pointer to plane or NULL if no plane found.</div><div class='add'>+	*/</div><div class='ctx'> 	struct mpcc* (*get_mpcc_for_dpp)(</div><div class='ctx'> 			struct mpc_tree *tree,</div><div class='ctx'> 			int dpp_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @wait_for_idle:</div><div class='add'>+	*</div><div class='add'>+	* Wait for a MPCC in MPC context to enter idle state.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC Context.</div><div class='add'>+	* - [in] id - MPCC to wait for idle state.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*wait_for_idle)(struct mpc *mpc, int id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @assert_mpcc_idle_before_connect:</div><div class='add'>+	*</div><div class='add'>+	* Assert if MPCC in MPC context is in idle state.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] id - MPCC to assert idle state.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @init_mpcc_list_from_hw:</div><div class='add'>+	*</div><div class='add'>+	* Iterate through the MPCC array from a given MPC context struct</div><div class='add'>+	* and configure each MPCC according to its registers' values.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context to initialize MPCC array.</div><div class='add'>+	* - [in/out] tree - MPC tree structure containing MPCC contexts to initialize.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*init_mpcc_list_from_hw)(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		struct mpc_tree *tree);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_denorm:</div><div class='add'>+	*</div><div class='add'>+	* Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode</div><div class='add'>+	* based on given color depth.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id - Corresponding OPP to update register.</div><div class='add'>+	* - [in] output_depth - Arbitrary color depth to set denorm_mode.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_denorm)(struct mpc *mpc,</div><div class='ctx'> 			int opp_id,</div><div class='ctx'> 			enum dc_color_depth output_depth);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_denorm_clamp:</div><div class='add'>+	*</div><div class='add'>+	* Set denorm clamp values on corresponding OPP DENORM CONTROL register.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id - Corresponding OPP to update register.</div><div class='add'>+	* - [in] denorm_clamp - Arbitrary denorm clamp to be set.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_denorm_clamp)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int opp_id,</div><div class='ctx'> 			struct mpc_denorm_clamp denorm_clamp);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_output_csc:</div><div class='add'>+	*</div><div class='add'>+	* Set the Output Color Space Conversion matrix</div><div class='add'>+	* with given values and mode.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id - Corresponding OPP to update register.</div><div class='add'>+	* - [in] regval - Values to set in CSC matrix.</div><div class='add'>+	* - [in] ocsc_mode - Mode to set CSC.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_output_csc)(struct mpc *mpc,</div><div class='ctx'> 			int opp_id,</div><div class='ctx'> 			const uint16_t *regval,</div><div class='ctx'> 			enum mpc_output_csc_mode ocsc_mode);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_ocsc_default:</div><div class='add'>+	*</div><div class='add'>+	* Set the Output Color Space Conversion matrix</div><div class='add'>+	* to default values according to color space.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id - Corresponding OPP to update register.</div><div class='add'>+	* - [in] color_space - OCSC color space.</div><div class='add'>+	* - [in] ocsc_mode - Mode to set CSC.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_ocsc_default)(struct mpc *mpc,</div><div class='ctx'> 			int opp_id,</div><div class='ctx'> 			enum dc_color_space color_space,</div><div class='ctx'> 			enum mpc_output_csc_mode ocsc_mode);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_output_gamma:</div><div class='add'>+	*</div><div class='add'>+	* Set Output Gamma with given curve parameters.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] mpcc_id - Corresponding MPC to update registers.</div><div class='add'>+	* - [in] params - Parameters.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_output_gamma)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int mpcc_id,</div><div class='ctx'> 			const struct pwl_params *params);</div><div class='add'>+	/**</div><div class='add'>+	* @power_on_mpc_mem_pwr:</div><div class='add'>+	*</div><div class='add'>+	* Power on/off memory LUT for given MPCC.</div><div class='add'>+	* Powering on enables LUT to be updated.</div><div class='add'>+	* Powering off allows entering low power mode.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] mpcc_id - MPCC to power on.</div><div class='add'>+	* - [in] power_on</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*power_on_mpc_mem_pwr)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int mpcc_id,</div><div class='ctx'> 			bool power_on);</div><div class='add'>+	/**</div><div class='add'>+	* @set_dwb_mux:</div><div class='add'>+	*</div><div class='add'>+	* Set corresponding Display Writeback mux</div><div class='add'>+	* MPC register field to given MPCC id.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] dwb_id - DWB to be set.</div><div class='add'>+	* - [in] mpcc_id - MPCC id to be stored in DWB mux register.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_dwb_mux)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int dwb_id,</div><div class='ctx'> 			int mpcc_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @disable_dwb_mux:</div><div class='add'>+	*</div><div class='add'>+	* Reset corresponding Display Writeback mux</div><div class='add'>+	* MPC register field.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] dwb_id - DWB to be set.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*disable_dwb_mux)(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		int dwb_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @is_dwb_idle:</div><div class='add'>+	*</div><div class='add'>+	* Check DWB status on MPC_DWB0_MUX_STATUS register field.</div><div class='add'>+	* Return if it is null.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] dwb_id - DWB to be checked.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* bool - wheter DWB is idle or not</div><div class='add'>+	*/</div><div class='ctx'> 	bool (*is_dwb_idle)(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		int dwb_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_out_rate_control:</div><div class='add'>+	*</div><div class='add'>+	* Set display output rate control.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id - OPP to be set.</div><div class='add'>+	* - [in] enable</div><div class='add'>+	* - [in] rate_2x_mode</div><div class='add'>+	* - [in] flow_control</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_out_rate_control)(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		int opp_id,</div><div class='hunk'>@@ -512,38 +856,286 @@ struct mpc_funcs {</div><div class='ctx'> 		bool rate_2x_mode,</div><div class='ctx'> 		struct mpc_dwb_flow_control *flow_control);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_gamut_remap:</div><div class='add'>+	*</div><div class='add'>+	* Set post-blending CTM for given MPCC.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in] mpc - MPC context.</div><div class='add'>+	* - [in] mpcc_id - MPCC to set gamut map.</div><div class='add'>+	* - [in] adjust</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_gamut_remap)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			int mpcc_id,</div><div class='ctx'> 			const struct mpc_grph_gamut_adjustment *adjust);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @program_1dlut:</div><div class='add'>+	*</div><div class='add'>+	* Set 1 dimensional Lookup Table.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context</div><div class='add'>+	* - [in] params - curve parameters for the LUT configuration</div><div class='add'>+	* - [in] rmu_idx</div><div class='add'>+	*</div><div class='add'>+	* bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).</div><div class='add'>+	*/</div><div class='ctx'> 	bool (*program_1dlut)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			const struct pwl_params *params,</div><div class='ctx'> 			uint32_t rmu_idx);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @program_shaper:</div><div class='add'>+	*</div><div class='add'>+	* Set shaper.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context</div><div class='add'>+	* - [in] params - curve parameters to be set</div><div class='add'>+	* - [in] rmu_idx</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled).</div><div class='add'>+	*/</div><div class='ctx'> 	bool (*program_shaper)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			const struct pwl_params *params,</div><div class='ctx'> 			uint32_t rmu_idx);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @acquire_rmu:</div><div class='add'>+	*</div><div class='add'>+	* Set given MPCC to be multiplexed to given RMU unit.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context</div><div class='add'>+	* - [in] mpcc_id - MPCC</div><div class='add'>+	* - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* unit32_t - rmu_idx if operation was successful, -1 else.</div><div class='add'>+	*/</div><div class='ctx'> 	uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @program_3dlut:</div><div class='add'>+	*</div><div class='add'>+	* Set 3 dimensional Lookup Table.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context</div><div class='add'>+	* - [in] params - tetrahedral parameters for the LUT configuration</div><div class='add'>+	* - [in] rmu_idx</div><div class='add'>+	*</div><div class='add'>+	* bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled).</div><div class='add'>+	*/</div><div class='ctx'> 	bool (*program_3dlut)(</div><div class='ctx'> 			struct mpc *mpc,</div><div class='ctx'> 			const struct tetrahedral_params *params,</div><div class='ctx'> 			int rmu_idx);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @release_rmu:</div><div class='add'>+	*</div><div class='add'>+	* For a given MPCC, release the RMU unit it muliplexes to.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context</div><div class='add'>+	* - [in] mpcc_id - MPCC</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release.</div><div class='add'>+	*/</div><div class='ctx'> 	int (*release_rmu)(struct mpc *mpc, int mpcc_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @get_mpc_out_mux:</div><div class='add'>+	*</div><div class='add'>+	* Return MPC out mux.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in] mpc - MPC context.</div><div class='add'>+	* - [in] opp_id - OPP</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* unsigned int - Out Mux</div><div class='add'>+	*/</div><div class='ctx'> 	unsigned int (*get_mpc_out_mux)(</div><div class='del'>-			struct mpc *mpc,</div><div class='del'>-			int opp_id);</div><div class='add'>+				struct mpc *mpc,</div><div class='add'>+				int opp_id);</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	* @set_bg_color:</div><div class='add'>+	*</div><div class='add'>+	* Find corresponding bottommost MPCC and</div><div class='add'>+	* set its bg color.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] bg_color - background color to be set.</div><div class='add'>+	* - [in] mpcc_id</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='ctx'> 	void (*set_bg_color)(struct mpc *mpc,</div><div class='ctx'> 			struct tg_color *bg_color,</div><div class='ctx'> 			int mpcc_id);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	* @set_mpc_mem_lp_mode:</div><div class='add'>+	*</div><div class='add'>+	* Set mpc_mem_lp_mode.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='add'>+</div><div class='ctx'> 	void (*set_mpc_mem_lp_mode)(struct mpc *mpc);</div><div class='add'>+	/**</div><div class='add'>+	* @set_movable_cm_location:</div><div class='add'>+	*</div><div class='add'>+	* Set Movable CM Location.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] location</div><div class='add'>+	* - [in] mpcc_id</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='add'>+</div><div class='add'>+	void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);</div><div class='add'>+	/**</div><div class='add'>+	* @update_3dlut_fast_load_select:</div><div class='add'>+	*</div><div class='add'>+	* Update 3D LUT fast load select.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] mpcc_id</div><div class='add'>+	* - [in] hubp_idx</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='add'>+</div><div class='add'>+	void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	* @populate_lut:</div><div class='add'>+	*</div><div class='add'>+	* Populate LUT with given tetrahedral parameters.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] id</div><div class='add'>+	* - [in] params</div><div class='add'>+	* - [in] lut_bank_a</div><div class='add'>+	* - [in] mpcc_id</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='add'>+	void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,</div><div class='add'>+			bool lut_bank_a, int mpcc_id);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	* @program_lut_read_write_control:</div><div class='add'>+	*</div><div class='add'>+	* Program LUT RW control.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] id</div><div class='add'>+	* - [in] lut_bank_a</div><div class='add'>+	* - [in] mpcc_id</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='add'>+	void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	* @program_lut_mode:</div><div class='add'>+	*</div><div class='add'>+	* Program LUT mode.</div><div class='add'>+	*</div><div class='add'>+	* Parameters:</div><div class='add'>+	* - [in/out] mpc - MPC context.</div><div class='add'>+	* - [in] id</div><div class='add'>+	* - [in] xable</div><div class='add'>+	* - [in] lut_bank_a</div><div class='add'>+	* - [in] mpcc_id</div><div class='add'>+	*</div><div class='add'>+	* Return:</div><div class='add'>+	*</div><div class='add'>+	* void</div><div class='add'>+	*/</div><div class='add'>+	void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable,</div><div class='add'>+			bool lut_bank_a, int mpcc_id);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @mcm:</div><div class='add'>+	 *</div><div class='add'>+	 * MPC MCM new HW sequential programming functions</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);</div><div class='add'>+		void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id);</div><div class='add'>+		void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);</div><div class='add'>+		bool (*is_config_supported)(uint32_t width);</div><div class='add'>+		void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,</div><div class='add'>+			bool lut_bank_a, bool enabled, int mpcc_id);</div><div class='add'>+</div><div class='add'>+		void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params,</div><div class='add'>+			bool lut_bank_a, int mpcc_id);</div><div class='add'>+	} mcm;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @rmcm:</div><div class='add'>+	 *</div><div class='add'>+	 * MPC RMCM new HW sequential programming functions</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id);</div><div class='add'>+		void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id);</div><div class='add'>+		void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);</div><div class='add'>+		void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,</div><div class='add'>+			bool lut_bank_a, bool enabled, int mpcc_id);</div><div class='add'>+		void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable,</div><div class='add'>+			bool lut_bank_a, int mpcc_id);</div><div class='add'>+		void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id);</div><div class='add'>+		void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id);</div><div class='add'>+		void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id);</div><div class='add'>+		bool (*is_config_supported)(uint32_t width);</div><div class='add'>+</div><div class='add'>+		void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on);</div><div class='add'>+		void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params,</div><div class='add'>+			bool lut_bank_a, int mpcc_id);</div><div class='add'>+	} rmcm;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h<br/>index d89c92370d5b..e1428a83ecbc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/opp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/opp.h</a></div><div class='hunk'>@@ -205,9 +205,24 @@ struct gamma_coefficients {</div><div class='ctx'> 	struct fixed31_32 user_brightness;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct pwl_float_data - Fixed point RGB color</div><div class='add'>+ */</div><div class='ctx'> struct pwl_float_data {</div><div class='add'>+	/**</div><div class='add'>+	 * @r: Component Red.</div><div class='add'>+	 */</div><div class='ctx'> 	struct fixed31_32 r;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @g: Component Green.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='ctx'> 	struct fixed31_32 g;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @b: Component Blue.</div><div class='add'>+	 */</div><div class='ctx'> 	struct fixed31_32 b;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -282,6 +297,16 @@ struct oppbuf_params {</div><div class='ctx'> 	uint32_t num_segment_padded_pixels;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn_opp_reg_state {</div><div class='add'>+	uint32_t dpg_control;</div><div class='add'>+	uint32_t fmt_control;</div><div class='add'>+	uint32_t oppbuf_control;</div><div class='add'>+	uint32_t opp_pipe_control;</div><div class='add'>+	uint32_t opp_pipe_crc_control;</div><div class='add'>+	uint32_t opp_abm_control;</div><div class='add'>+	uint32_t dscrm_dsc_forward_config;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct opp_funcs {</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -346,8 +371,16 @@ struct opp_funcs {</div><div class='ctx'> </div><div class='ctx'> 	void (*opp_program_left_edge_extra_pixel)(</div><div class='ctx'> 			struct output_pixel_processor *opp,</div><div class='del'>-			bool count);</div><div class='add'>+			enum dc_pixel_encoding pixel_encoding,</div><div class='add'>+			bool is_primary);</div><div class='add'>+</div><div class='add'>+	uint32_t (*opp_get_left_edge_extra_pixel_count)(</div><div class='add'>+			struct output_pixel_processor *opp,</div><div class='add'>+			enum dc_pixel_encoding pixel_encoding,</div><div class='add'>+			bool is_primary);</div><div class='ctx'> </div><div class='add'>+	void (*opp_read_reg_state)(</div><div class='add'>+			struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h<br/>index 9a8bf6ec70ea..0d5a8358a778 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/optc.h</a></div><div class='hunk'>@@ -65,37 +65,13 @@ struct optc {</div><div class='ctx'> 	int vupdate_offset;</div><div class='ctx'> 	int vupdate_width;</div><div class='ctx'> 	int vready_offset;</div><div class='add'>+	int pstate_keepout;</div><div class='ctx'> 	struct dc_crtc_timing orginal_patched_timing;</div><div class='ctx'> 	enum signal_type signal;</div><div class='add'>+	uint32_t max_frame_count;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dcn_otg_state {</div><div class='del'>-	uint32_t v_blank_start;</div><div class='del'>-	uint32_t v_blank_end;</div><div class='del'>-	uint32_t v_sync_a_pol;</div><div class='del'>-	uint32_t v_total;</div><div class='del'>-	uint32_t v_total_max;</div><div class='del'>-	uint32_t v_total_min;</div><div class='del'>-	uint32_t v_total_min_sel;</div><div class='del'>-	uint32_t v_total_max_sel;</div><div class='del'>-	uint32_t v_sync_a_start;</div><div class='del'>-	uint32_t v_sync_a_end;</div><div class='del'>-	uint32_t h_blank_start;</div><div class='del'>-	uint32_t h_blank_end;</div><div class='del'>-	uint32_t h_sync_a_start;</div><div class='del'>-	uint32_t h_sync_a_end;</div><div class='del'>-	uint32_t h_sync_a_pol;</div><div class='del'>-	uint32_t h_total;</div><div class='del'>-	uint32_t underflow_occurred_status;</div><div class='del'>-	uint32_t otg_enabled;</div><div class='del'>-	uint32_t blank_enabled;</div><div class='del'>-	uint32_t vertical_interrupt1_en;</div><div class='del'>-	uint32_t vertical_interrupt1_line;</div><div class='del'>-	uint32_t vertical_interrupt2_en;</div><div class='del'>-	uint32_t vertical_interrupt2_line;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);</div><div class='add'>+void optc1_read_otg_state(struct timing_generator *optc, struct dcn_otg_state *s);</div><div class='ctx'> </div><div class='ctx'> bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing);</div><div class='ctx'> </div><div class='hunk'>@@ -108,6 +84,7 @@ void optc1_program_timing(struct timing_generator *optc,</div><div class='ctx'> 			  int vstartup_start,</div><div class='ctx'> 			  int vupdate_offset,</div><div class='ctx'> 			  int vupdate_width,</div><div class='add'>+			  int pstate_keepout,</div><div class='ctx'> 			  const enum signal_type signal,</div><div class='ctx'> 			  bool use_vbios);</div><div class='ctx'> </div><div class='hunk'>@@ -125,7 +102,8 @@ void optc1_program_global_sync(struct timing_generator *optc,</div><div class='ctx'> 			       int vready_offset,</div><div class='ctx'> 			       int vstartup_start,</div><div class='ctx'> 			       int vupdate_offset,</div><div class='del'>-			       int vupdate_width);</div><div class='add'>+			       int vupdate_width,</div><div class='add'>+				   int pstate_keepout);</div><div class='ctx'> </div><div class='ctx'> bool optc1_disable_crtc(struct timing_generator *optc);</div><div class='ctx'> </div><div class='hunk'>@@ -205,15 +183,15 @@ void optc1_enable_crtc_reset(struct timing_generator *optc,</div><div class='ctx'> </div><div class='ctx'> bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);</div><div class='ctx'> </div><div class='del'>-bool optc1_get_crc(struct timing_generator *optc,</div><div class='add'>+bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,</div><div class='ctx'> 		   uint32_t *r_cr,</div><div class='ctx'> 		   uint32_t *g_y,</div><div class='ctx'> 		   uint32_t *b_cb);</div><div class='ctx'> </div><div class='del'>-bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);</div><div class='del'>-</div><div class='ctx'> void optc1_set_vtg_params(struct timing_generator *optc,</div><div class='ctx'> 			  const struct dc_crtc_timing *dc_crtc_timing,</div><div class='ctx'> 			  bool program_fp2);</div><div class='ctx'> </div><div class='add'>+bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h<br/>index 00ea3864dd4d..227e3f8d7e5f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h</a></div><div class='hunk'>@@ -46,7 +46,10 @@ struct pg_cntl_funcs {</div><div class='ctx'> 	void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on);</div><div class='ctx'> 	void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);</div><div class='ctx'> 	void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);</div><div class='add'>+	void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on);</div><div class='add'>+	void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on);</div><div class='ctx'> 	void (*init_pg_status)(struct pg_cntl *pg_cntl);</div><div class='add'>+	void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif //__DC_PG_CNTL_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h<br/>index a15efadb9183..27f950ae45ee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h</a></div><div class='hunk'>@@ -99,6 +99,7 @@ struct encoder_unblank_param {</div><div class='ctx'> 	struct dc_link_settings link_settings;</div><div class='ctx'> 	struct dc_crtc_timing timing;</div><div class='ctx'> 	int opp_cnt;</div><div class='add'>+	uint32_t pix_per_cycle;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct encoder_set_dp_phy_pattern_param {</div><div class='hunk'>@@ -116,6 +117,7 @@ struct stream_encoder {</div><div class='ctx'> 	uint32_t stream_enc_inst;</div><div class='ctx'> 	struct vpg *vpg;</div><div class='ctx'> 	struct afmt *afmt;</div><div class='add'>+	struct apg *apg;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct enc_state {</div><div class='hunk'>@@ -178,10 +180,6 @@ struct stream_encoder_funcs {</div><div class='ctx'> 	void (*stop_dp_info_packets)(</div><div class='ctx'> 		struct stream_encoder *enc);</div><div class='ctx'> </div><div class='del'>-	void (*reset_fifo)(</div><div class='del'>-		struct stream_encoder *enc</div><div class='del'>-	);</div><div class='del'>-</div><div class='ctx'> 	void (*dp_blank)(</div><div class='ctx'> 		struct dc_link *link,</div><div class='ctx'> 		struct stream_encoder *enc);</div><div class='hunk'>@@ -226,7 +224,7 @@ struct stream_encoder_funcs {</div><div class='ctx'> 		struct stream_encoder *enc,</div><div class='ctx'> 		int tg_inst);</div><div class='ctx'> </div><div class='del'>-	void (*dig_stream_enable)(</div><div class='add'>+	void (*enable_stream)(</div><div class='ctx'> 		struct stream_encoder *enc,</div><div class='ctx'> 		enum signal_type signal,</div><div class='ctx'> 		bool enable);</div><div class='hunk'>@@ -274,7 +272,9 @@ struct stream_encoder_funcs {</div><div class='ctx'> 		struct stream_encoder *enc, unsigned int pix_per_container);</div><div class='ctx'> 	void (*enable_fifo)(struct stream_encoder *enc);</div><div class='ctx'> 	void (*disable_fifo)(struct stream_encoder *enc);</div><div class='add'>+	bool (*is_fifo_enabled)(struct stream_encoder *enc);</div><div class='ctx'> 	void (*map_stream_to_link)(struct stream_encoder *enc, uint32_t stream_enc_inst, uint32_t link_enc_inst);</div><div class='add'>+	uint32_t (*get_pixels_per_cycle)(struct stream_encoder *enc);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct hpo_dp_stream_encoder_state {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h<br/>index ffad8fe16c54..da7bf59c4b9d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h</a></div><div class='hunk'>@@ -64,6 +64,12 @@ struct drr_params {</div><div class='ctx'> 	bool immediate_flip;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct long_vtotal_params {</div><div class='add'>+	uint32_t vertical_total_min;</div><div class='add'>+	uint32_t vertical_total_max;</div><div class='add'>+	uint32_t vertical_blank_start;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define LEFT_EYE_3D_PRIMARY_SURFACE 1</div><div class='ctx'> #define RIGHT_EYE_3D_PRIMARY_SURFACE 0</div><div class='ctx'> </div><div class='hunk'>@@ -135,6 +141,167 @@ struct crc_params {</div><div class='ctx'> </div><div class='ctx'> 	bool continuous_mode;</div><div class='ctx'> 	bool enable;</div><div class='add'>+</div><div class='add'>+	uint8_t crc_eng_inst;</div><div class='add'>+	bool reset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn_otg_state {</div><div class='add'>+	uint32_t v_blank_start;</div><div class='add'>+	uint32_t v_blank_end;</div><div class='add'>+	uint32_t v_sync_a_pol;</div><div class='add'>+	uint32_t v_total;</div><div class='add'>+	uint32_t v_total_max;</div><div class='add'>+	uint32_t v_total_min;</div><div class='add'>+	uint32_t v_total_min_sel;</div><div class='add'>+	uint32_t v_total_max_sel;</div><div class='add'>+	uint32_t v_sync_a_start;</div><div class='add'>+	uint32_t v_sync_a_end;</div><div class='add'>+	uint32_t h_blank_start;</div><div class='add'>+	uint32_t h_blank_end;</div><div class='add'>+	uint32_t h_sync_a_start;</div><div class='add'>+	uint32_t h_sync_a_end;</div><div class='add'>+	uint32_t h_sync_a_pol;</div><div class='add'>+	uint32_t h_total;</div><div class='add'>+	uint32_t underflow_occurred_status;</div><div class='add'>+	uint32_t otg_enabled;</div><div class='add'>+	uint32_t blank_enabled;</div><div class='add'>+	uint32_t vertical_interrupt1_en;</div><div class='add'>+	uint32_t vertical_interrupt1_line;</div><div class='add'>+	uint32_t vertical_interrupt2_en;</div><div class='add'>+	uint32_t vertical_interrupt2_line;</div><div class='add'>+	uint32_t vertical_interrupt2_dest;</div><div class='add'>+	uint32_t otg_master_update_lock;</div><div class='add'>+	uint32_t otg_double_buffer_control;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn_optc_reg_state {</div><div class='add'>+	uint32_t optc_bytes_per_pixel;</div><div class='add'>+	uint32_t optc_data_format_control;</div><div class='add'>+	uint32_t optc_data_source_select;</div><div class='add'>+	uint32_t optc_input_clock_control;</div><div class='add'>+	uint32_t optc_input_global_control;</div><div class='add'>+	uint32_t optc_input_spare_register;</div><div class='add'>+	uint32_t optc_memory_config;</div><div class='add'>+	uint32_t optc_rsmu_underflow;</div><div class='add'>+	uint32_t optc_underflow_threshold;</div><div class='add'>+	uint32_t optc_width_control;</div><div class='add'>+</div><div class='add'>+	uint32_t otg_3d_structure_control;</div><div class='add'>+	uint32_t otg_clock_control;</div><div class='add'>+	uint32_t otg_control;</div><div class='add'>+	uint32_t otg_count_control;</div><div class='add'>+	uint32_t otg_count_reset;</div><div class='add'>+	uint32_t otg_crc_cntl;</div><div class='add'>+	uint32_t otg_crc_sig_blue_control_mask;</div><div class='add'>+	uint32_t otg_crc_sig_red_green_mask;</div><div class='add'>+	uint32_t otg_crc0_data_b;</div><div class='add'>+	uint32_t otg_crc0_data_rg;</div><div class='add'>+	uint32_t otg_crc0_windowa_x_control;</div><div class='add'>+	uint32_t otg_crc0_windowa_x_control_readback;</div><div class='add'>+	uint32_t otg_crc0_windowa_y_control;</div><div class='add'>+	uint32_t otg_crc0_windowa_y_control_readback;</div><div class='add'>+	uint32_t otg_crc0_windowb_x_control;</div><div class='add'>+	uint32_t otg_crc0_windowb_x_control_readback;</div><div class='add'>+	uint32_t otg_crc0_windowb_y_control;</div><div class='add'>+	uint32_t otg_crc0_windowb_y_control_readback;</div><div class='add'>+	uint32_t otg_crc1_data_b;</div><div class='add'>+	uint32_t otg_crc1_data_rg;</div><div class='add'>+	uint32_t otg_crc1_windowa_x_control;</div><div class='add'>+	uint32_t otg_crc1_windowa_x_control_readback;</div><div class='add'>+	uint32_t otg_crc1_windowa_y_control;</div><div class='add'>+	uint32_t otg_crc1_windowa_y_control_readback;</div><div class='add'>+	uint32_t otg_crc1_windowb_x_control;</div><div class='add'>+	uint32_t otg_crc1_windowb_x_control_readback;</div><div class='add'>+	uint32_t otg_crc1_windowb_y_control;</div><div class='add'>+	uint32_t otg_crc1_windowb_y_control_readback;</div><div class='add'>+	uint32_t otg_crc2_data_b;</div><div class='add'>+	uint32_t otg_crc2_data_rg;</div><div class='add'>+	uint32_t otg_crc3_data_b;</div><div class='add'>+	uint32_t otg_crc3_data_rg;</div><div class='add'>+	uint32_t otg_dlpc_control;</div><div class='add'>+	uint32_t otg_double_buffer_control;</div><div class='add'>+	uint32_t otg_drr_control2;</div><div class='add'>+	uint32_t otg_drr_control;</div><div class='add'>+	uint32_t otg_drr_timing_int_status;</div><div class='add'>+	uint32_t otg_drr_trigger_window;</div><div class='add'>+	uint32_t otg_drr_v_total_change;</div><div class='add'>+	uint32_t otg_drr_v_total_reach_range;</div><div class='add'>+	uint32_t otg_dsc_start_position;</div><div class='add'>+	uint32_t otg_force_count_now_cntl;</div><div class='add'>+	uint32_t otg_global_control0;</div><div class='add'>+	uint32_t otg_global_control1;</div><div class='add'>+	uint32_t otg_global_control2;</div><div class='add'>+	uint32_t otg_global_control3;</div><div class='add'>+	uint32_t otg_global_control4;</div><div class='add'>+	uint32_t otg_global_sync_status;</div><div class='add'>+	uint32_t otg_gsl_control;</div><div class='add'>+	uint32_t otg_gsl_vsync_gap;</div><div class='add'>+	uint32_t otg_gsl_window_x;</div><div class='add'>+	uint32_t otg_gsl_window_y;</div><div class='add'>+	uint32_t otg_h_blank_start_end;</div><div class='add'>+	uint32_t otg_h_sync_a;</div><div class='add'>+	uint32_t otg_h_sync_a_cntl;</div><div class='add'>+	uint32_t otg_h_timing_cntl;</div><div class='add'>+	uint32_t otg_h_total;</div><div class='add'>+	uint32_t otg_interlace_control;</div><div class='add'>+	uint32_t otg_interlace_status;</div><div class='add'>+	uint32_t otg_interrupt_control;</div><div class='add'>+	uint32_t otg_long_vblank_status;</div><div class='add'>+	uint32_t otg_m_const_dto0;</div><div class='add'>+	uint32_t otg_m_const_dto1;</div><div class='add'>+	uint32_t otg_manual_force_vsync_next_line;</div><div class='add'>+	uint32_t otg_master_en;</div><div class='add'>+	uint32_t otg_master_update_lock;</div><div class='add'>+	uint32_t otg_master_update_mode;</div><div class='add'>+	uint32_t otg_nom_vert_position;</div><div class='add'>+	uint32_t otg_pipe_update_status;</div><div class='add'>+	uint32_t otg_pixel_data_readback0;</div><div class='add'>+	uint32_t otg_pixel_data_readback1;</div><div class='add'>+	uint32_t otg_request_control;</div><div class='add'>+	uint32_t otg_snapshot_control;</div><div class='add'>+	uint32_t otg_snapshot_frame;</div><div class='add'>+	uint32_t otg_snapshot_position;</div><div class='add'>+	uint32_t otg_snapshot_status;</div><div class='add'>+	uint32_t otg_spare_register;</div><div class='add'>+	uint32_t otg_static_screen_control;</div><div class='add'>+	uint32_t otg_status;</div><div class='add'>+	uint32_t otg_status_frame_count;</div><div class='add'>+	uint32_t otg_status_hv_count;</div><div class='add'>+	uint32_t otg_status_position;</div><div class='add'>+	uint32_t otg_status_vf_count;</div><div class='add'>+	uint32_t otg_stereo_control;</div><div class='add'>+	uint32_t otg_stereo_force_next_eye;</div><div class='add'>+	uint32_t otg_stereo_status;</div><div class='add'>+	uint32_t otg_trig_manual_control;</div><div class='add'>+	uint32_t otg_triga_cntl;</div><div class='add'>+	uint32_t otg_triga_manual_trig;</div><div class='add'>+	uint32_t otg_trigb_cntl;</div><div class='add'>+	uint32_t otg_trigb_manual_trig;</div><div class='add'>+	uint32_t otg_update_lock;</div><div class='add'>+	uint32_t otg_v_blank_start_end;</div><div class='add'>+	uint32_t otg_v_count_stop_control;</div><div class='add'>+	uint32_t otg_v_count_stop_control2;</div><div class='add'>+	uint32_t otg_v_sync_a;</div><div class='add'>+	uint32_t otg_v_sync_a_cntl;</div><div class='add'>+	uint32_t otg_v_total;</div><div class='add'>+	uint32_t otg_v_total_control;</div><div class='add'>+	uint32_t otg_v_total_int_status;</div><div class='add'>+	uint32_t otg_v_total_max;</div><div class='add'>+	uint32_t otg_v_total_mid;</div><div class='add'>+	uint32_t otg_v_total_min;</div><div class='add'>+	uint32_t otg_vert_sync_control;</div><div class='add'>+	uint32_t otg_vertical_interrupt0_control;</div><div class='add'>+	uint32_t otg_vertical_interrupt0_position;</div><div class='add'>+	uint32_t otg_vertical_interrupt1_control;</div><div class='add'>+	uint32_t otg_vertical_interrupt1_position;</div><div class='add'>+	uint32_t otg_vertical_interrupt2_control;</div><div class='add'>+	uint32_t otg_vertical_interrupt2_position;</div><div class='add'>+	uint32_t otg_vready_param;</div><div class='add'>+	uint32_t otg_vstartup_param;</div><div class='add'>+	uint32_t otg_vsync_nom_int_status;</div><div class='add'>+	uint32_t otg_vupdate_keepout;</div><div class='add'>+	uint32_t otg_vupdate_param;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -166,6 +333,7 @@ struct timing_generator_funcs {</div><div class='ctx'> 							int vstartup_start,</div><div class='ctx'> 							int vupdate_offset,</div><div class='ctx'> 							int vupdate_width,</div><div class='add'>+							int pstate_keepout,</div><div class='ctx'> 							const enum signal_type signal,</div><div class='ctx'> 							bool use_vbios</div><div class='ctx'> 	);</div><div class='hunk'>@@ -250,7 +418,8 @@ struct timing_generator_funcs {</div><div class='ctx'> 			int vready_offset,</div><div class='ctx'> 			int vstartup_start,</div><div class='ctx'> 			int vupdate_offset,</div><div class='del'>-			int vupdate_width);</div><div class='add'>+			int vupdate_width,</div><div class='add'>+			int pstate_keepout);</div><div class='ctx'> 	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);</div><div class='ctx'> 	void (*program_stereo)(struct timing_generator *tg,</div><div class='ctx'> 		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);</div><div class='hunk'>@@ -270,6 +439,7 @@ struct timing_generator_funcs {</div><div class='ctx'> 			uint32_t *num_of_input_segments,</div><div class='ctx'> 			uint32_t *seg0_src_sel,</div><div class='ctx'> 			uint32_t *seg1_src_sel);</div><div class='add'>+	bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Configure CRCs for the given timing generator. Return false if TG is</div><div class='hunk'>@@ -282,7 +452,7 @@ struct timing_generator_funcs {</div><div class='ctx'> 	 * @get_crc: Get CRCs for the given timing generator. Return false if</div><div class='ctx'> 	 * CRCs are not enabled (via configure_crc).</div><div class='ctx'> 	 */</div><div class='del'>-	bool (*get_crc)(struct timing_generator *tg,</div><div class='add'>+	bool (*get_crc)(struct timing_generator *tg, uint8_t idx,</div><div class='ctx'> 			uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);</div><div class='ctx'> </div><div class='ctx'> 	void (*program_manual_trigger)(struct timing_generator *optc);</div><div class='hunk'>@@ -306,7 +476,7 @@ struct timing_generator_funcs {</div><div class='ctx'> 	 * OPP(s) and turn on/off ODM memory.</div><div class='ctx'> 	 */</div><div class='ctx'> 	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-			struct dc_crtc_timing *timing);</div><div class='add'>+			int segment_width, int last_segment_width);</div><div class='ctx'> 	void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments);</div><div class='ctx'> 	void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);</div><div class='ctx'> 	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);</div><div class='hunk'>@@ -331,7 +501,16 @@ struct timing_generator_funcs {</div><div class='ctx'> </div><div class='ctx'> 	void (*init_odm)(struct timing_generator *tg);</div><div class='ctx'> 	void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg);</div><div class='add'>+	void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params);</div><div class='ctx'> 	void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg);</div><div class='add'>+	void (*wait_otg_disable)(struct timing_generator *optc);</div><div class='add'>+	bool (*get_optc_double_buffer_pending)(struct timing_generator *tg);</div><div class='add'>+	bool (*get_otg_double_buffer_pending)(struct timing_generator *tg);</div><div class='add'>+	bool (*get_pipe_update_pending)(struct timing_generator *tg);</div><div class='add'>+	void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable);</div><div class='add'>+	bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);</div><div class='add'>+	void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s);</div><div class='add'>+	void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h<br/>index 9ac9d5e8df8b..5a1d9b708a9d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/hw/transform.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/transform.h</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "hw_shared.h"</div><div class='ctx'> #include "dc_hw_types.h"</div><div class='ctx'> #include "fixed31_32.h"</div><div class='add'>+#include "sspl/dc_spl_types.h"</div><div class='ctx'> </div><div class='ctx'> #define CSC_TEMPERATURE_MATRIX_SIZE 12</div><div class='ctx'> </div><div class='hunk'>@@ -110,22 +111,6 @@ enum graphics_gamut_adjust_type {</div><div class='ctx'> 	GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-enum lb_memory_config {</div><div class='del'>-	/* Enable all 3 pieces of memory */</div><div class='del'>-	LB_MEMORY_CONFIG_0 = 0,</div><div class='del'>-</div><div class='del'>-	/* Enable only the first piece of memory */</div><div class='del'>-	LB_MEMORY_CONFIG_1 = 1,</div><div class='del'>-</div><div class='del'>-	/* Enable only the second piece of memory */</div><div class='del'>-	LB_MEMORY_CONFIG_2 = 2,</div><div class='del'>-</div><div class='del'>-	/* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the</div><div class='del'>-	 * last piece of chroma memory used for the luma storage</div><div class='del'>-	 */</div><div class='del'>-	LB_MEMORY_CONFIG_3 = 3</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct xfm_grph_csc_adjustment {</div><div class='ctx'> 	struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];</div><div class='ctx'> 	enum graphics_gamut_adjust_type gamut_adjust_type;</div><div class='hunk'>@@ -177,6 +162,8 @@ struct scaler_data {</div><div class='ctx'> 	struct sharpness_adj sharpness;</div><div class='ctx'> 	enum pixel_format format;</div><div class='ctx'> 	struct line_buffer_params lb_params;</div><div class='add'>+	// Below struct holds the scaler values to program hw registers</div><div class='add'>+	struct dscl_prog_data dscl_prog_data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct transform_funcs {</div><div class='hunk'>@@ -258,7 +245,6 @@ struct transform_funcs {</div><div class='ctx'> 	void (*set_cursor_attributes)(</div><div class='ctx'> 			struct transform *xfm_base,</div><div class='ctx'> 			const struct dc_cursor_attributes *attr);</div><div class='del'>-</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const uint16_t *get_filter_2tap_16p(void);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h<br/>new file mode 100644<br/>index 000000000000..51da368f5c3e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_VPG_H__</div><div class='add'>+#define __DC_VPG_H__</div><div class='add'>+</div><div class='add'>+struct dc_context;</div><div class='add'>+struct dc_info_packet;</div><div class='add'>+</div><div class='add'>+struct vpg;</div><div class='add'>+</div><div class='add'>+struct vpg_funcs {</div><div class='add'>+	void (*update_generic_info_packet)(</div><div class='add'>+		struct vpg *vpg,</div><div class='add'>+		uint32_t packet_index,</div><div class='add'>+		const struct dc_info_packet *info_packet,</div><div class='add'>+		bool immediate_update);</div><div class='add'>+</div><div class='add'>+	void (*vpg_poweron)(</div><div class='add'>+		struct vpg *vpg);</div><div class='add'>+</div><div class='add'>+	void (*vpg_powerdown)(</div><div class='add'>+		struct vpg *vpg);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpg {</div><div class='add'>+	const struct vpg_funcs *funcs;</div><div class='add'>+	struct dc_context *ctx;</div><div class='add'>+	int inst;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif /* DC_INC_VPG_H_ */
\ No newline at end of file</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h<br/>index dc650be3837e..f1afb31ac70b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h</a></div><div class='hunk'>@@ -96,11 +96,6 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link(</div><div class='ctx'> /* Return next available DIG link encoder. NULL if none available. */</div><div class='ctx'> struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc);</div><div class='ctx'> </div><div class='del'>-/* Return DIG link encoder used by stream. NULL if unused. */</div><div class='del'>-struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		const struct dc_stream_state *stream);</div><div class='del'>-</div><div class='ctx'> /* Return DIG link encoder. NULL if unused. */</div><div class='ctx'> struct link_encoder *link_enc_cfg_get_link_enc(const struct dc_link *link);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h<br/>index bf29fc58ea6a..6f94e48a24d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/link.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/link.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/link_service.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/link_service.h</a></div><div class='hunk'>@@ -42,8 +42,8 @@</div><div class='ctx'>  * dc_link_exports.c or other dc files implement dc.h</div><div class='ctx'>  *</div><div class='ctx'>  * DC to Link:</div><div class='del'>- * dc_link_exports.c or other dc files include link.h</div><div class='del'>- * link_factory.c implements link.h</div><div class='add'>+ * dc_link_exports.c or other dc files include link_service.h</div><div class='add'>+ * link_factory.c implements link_service.h</div><div class='ctx'>  *</div><div class='ctx'>  * Link sub-component to Link sub-component:</div><div class='ctx'>  * link_factory.c includes --&gt; link_xxx.h</div><div class='hunk'>@@ -73,7 +73,7 @@</div><div class='ctx'>  * 2. Implement your function in the suitable link_xxx.c file.</div><div class='ctx'>  * 3. Assign the function to link_service in link_factory.c</div><div class='ctx'>  * 4. NEVER include link_xxx.h headers outside link component.</div><div class='del'>- * 5. NEVER include link.h on DM side.</div><div class='add'>+ * 5. NEVER include link_service.h on DM side.</div><div class='ctx'>  */</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> </div><div class='hunk'>@@ -144,9 +144,13 @@ struct link_service {</div><div class='ctx'> 	uint32_t (*dp_link_bandwidth_kbps)(</div><div class='ctx'> 		const struct dc_link *link,</div><div class='ctx'> 		const struct dc_link_settings *link_settings);</div><div class='del'>-	bool (*validate_dpia_bandwidth)(</div><div class='del'>-			const struct dc_stream_state *stream,</div><div class='del'>-			const unsigned int num_streams);</div><div class='add'>+	enum dc_status (*validate_dp_tunnel_bandwidth)(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_state *new_ctx);</div><div class='add'>+</div><div class='add'>+	uint32_t (*dp_required_hblank_size_bytes)(</div><div class='add'>+		const struct dc_link *link,</div><div class='add'>+		struct dp_audio_bandwidth_params *audio_params);</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	/*************************** DPMS *************************************/</div><div class='hunk'>@@ -203,6 +207,9 @@ struct link_service {</div><div class='ctx'> 	bool (*dp_decide_link_settings)(</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_link_settings *link_setting);</div><div class='add'>+	void (*dp_decide_tunnel_settings)(</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_tunnel_settings *dp_tunnel_setting);</div><div class='ctx'> 	enum dp_link_encoding (*mst_decide_link_encoding_format)(</div><div class='ctx'> 			const struct dc_link *link);</div><div class='ctx'> 	bool (*edp_decide_link_settings)(struct dc_link *link,</div><div class='hunk'>@@ -211,13 +218,14 @@ struct link_service {</div><div class='ctx'> 	bool (*dp_overwrite_extended_receiver_cap)(struct dc_link *link);</div><div class='ctx'> 	enum lttpr_mode (*dp_decide_lttpr_mode)(struct dc_link *link,</div><div class='ctx'> 			struct dc_link_settings *link_setting);</div><div class='del'>-</div><div class='add'>+	uint8_t (*dp_get_lttpr_count)(struct dc_link *link);</div><div class='add'>+	void (*edp_get_alpm_support)(struct dc_link *link,</div><div class='add'>+		bool *auxless_support,</div><div class='add'>+		bool *auxwake_support);</div><div class='ctx'> </div><div class='ctx'> 	/*************************** DP DPIA/PHY ******************************/</div><div class='del'>-	int (*dpia_handle_usb4_bandwidth_allocation_for_link)(</div><div class='add'>+	void (*dpia_handle_usb4_bandwidth_allocation_for_link)(</div><div class='ctx'> 			struct dc_link *link, int peak_bw);</div><div class='del'>-	void (*dpia_handle_bw_alloc_response)(</div><div class='del'>-			struct dc_link *link, uint8_t bw, uint8_t result);</div><div class='ctx'> 	void (*dp_set_drive_settings)(</div><div class='ctx'> 		struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='hunk'>@@ -248,8 +256,7 @@ struct link_service {</div><div class='ctx'> 			uint32_t *backlight_millinits_avg,</div><div class='ctx'> 			uint32_t *backlight_millinits_peak);</div><div class='ctx'> 	bool (*edp_set_backlight_level)(const struct dc_link *link,</div><div class='del'>-			uint32_t backlight_pwm_u16_16,</div><div class='del'>-			uint32_t frame_ramp);</div><div class='add'>+			struct set_backlight_level_params *backlight_level_params);</div><div class='ctx'> 	bool (*edp_set_backlight_level_nits)(struct dc_link *link,</div><div class='ctx'> 			bool isHDR,</div><div class='ctx'> 			uint32_t backlight_millinits,</div><div class='hunk'>@@ -272,7 +279,7 @@ struct link_service {</div><div class='ctx'> 			uint16_t psr_vtotal_idle,</div><div class='ctx'> 			uint16_t psr_vtotal_su);</div><div class='ctx'> 	void (*edp_get_psr_residency)(</div><div class='del'>-			const struct dc_link *link, uint32_t *residency);</div><div class='add'>+			const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode);</div><div class='ctx'> </div><div class='ctx'> 	bool (*edp_get_replay_state)(</div><div class='ctx'> 			const struct dc_link *link, uint64_t *state);</div><div class='hunk'>@@ -285,12 +292,12 @@ struct link_service {</div><div class='ctx'> 			enum replay_FW_Message_type msg,</div><div class='ctx'> 			union dmub_replay_cmd_set *cmd_data);</div><div class='ctx'> 	bool (*edp_set_coasting_vtotal)(</div><div class='del'>-			struct dc_link *link, uint32_t coasting_vtotal);</div><div class='add'>+			struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number);</div><div class='ctx'> 	bool (*edp_replay_residency)(const struct dc_link *link,</div><div class='ctx'> 			unsigned int *residency, const bool is_start,</div><div class='del'>-			const bool is_alpm);</div><div class='add'>+			const enum pr_residency_mode mode);</div><div class='ctx'> 	bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link *link,</div><div class='del'>-			const unsigned int *power_opts, uint32_t coasting_vtotal);</div><div class='add'>+			const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number);</div><div class='ctx'> </div><div class='ctx'> 	bool (*edp_wait_for_t12)(struct dc_link *link);</div><div class='ctx'> 	bool (*edp_is_ilr_optimization_required)(struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h<br/>index a402df225a76..26cb1459b743 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/reg_helper.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/reg_helper.h</a></div><div class='hunk'>@@ -508,6 +508,10 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,</div><div class='ctx'> 				initial_val, \</div><div class='ctx'> 				n, __VA_ARGS__)</div><div class='ctx'> </div><div class='add'>+#define IX_REG_SET_SYNC(index, init_value, f1, v1)	\</div><div class='add'>+		IX_REG_SET_N_SYNC(index, 1, init_value, \</div><div class='add'>+				FN(reg, f1), v1)</div><div class='add'>+</div><div class='ctx'> #define IX_REG_SET_2_SYNC(index, init_value, f1, v1, f2, v2)	\</div><div class='ctx'> 		IX_REG_SET_N_SYNC(index, 2, init_value, \</div><div class='ctx'> 				FN(reg, f1), v1,\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h<br/>index 77a60aa9f27b..79746d931471 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/inc/resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/resource.h</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> </div><div class='ctx'> #define MEMORY_TYPE_MULTIPLIER_CZ 4</div><div class='ctx'> #define MEMORY_TYPE_HBM 2</div><div class='add'>+#define MAX_MCACHES 8</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)-&gt;pipe_idx_syncd) &amp; 0x80)?1:0)</div><div class='hunk'>@@ -44,9 +45,11 @@ enum dce_version resource_parse_asic_id(</div><div class='ctx'> struct resource_caps {</div><div class='ctx'> 	int num_timing_generator;</div><div class='ctx'> 	int num_opp;</div><div class='add'>+	int num_dpp;</div><div class='ctx'> 	int num_video_plane;</div><div class='ctx'> 	int num_audio;</div><div class='ctx'> 	int num_stream_encoder;</div><div class='add'>+	int num_analog_stream_encoder;</div><div class='ctx'> 	int num_pll;</div><div class='ctx'> 	int num_dwb;</div><div class='ctx'> 	int num_ddc;</div><div class='hunk'>@@ -65,6 +68,13 @@ struct resource_straps {</div><div class='ctx'> 	uint32_t audio_stream_number;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dc_mcache_allocations {</div><div class='add'>+	int global_mcache_ids_plane0[MAX_MCACHES + 1];</div><div class='add'>+	int global_mcache_ids_plane1[MAX_MCACHES + 1];</div><div class='add'>+	int global_mcache_ids_mall_plane0[MAX_MCACHES + 1];</div><div class='add'>+	int global_mcache_ids_mall_plane1[MAX_MCACHES + 1];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct resource_create_funcs {</div><div class='ctx'> 	void (*read_dce_straps)(</div><div class='ctx'> 			struct dc_context *ctx, struct resource_straps *straps);</div><div class='hunk'>@@ -77,11 +87,9 @@ struct resource_create_funcs {</div><div class='ctx'> </div><div class='ctx'> 	struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)(</div><div class='ctx'> 			enum engine_id eng_id, struct dc_context *ctx);</div><div class='del'>-</div><div class='ctx'> 	struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)(</div><div class='ctx'> 			uint8_t inst,</div><div class='ctx'> 			struct dc_context *ctx);</div><div class='del'>-</div><div class='ctx'> 	struct dce_hwseq *(*create_hwseq)(</div><div class='ctx'> 			struct dc_context *ctx);</div><div class='ctx'> };</div><div class='hunk'>@@ -153,6 +161,8 @@ bool resource_attach_surfaces_to_context(</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		const struct resource_pool *pool);</div><div class='ctx'> </div><div class='add'>+bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='ctx'> #define FREE_PIPE_INDEX_NOT_FOUND -1</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -443,6 +453,16 @@ int resource_get_odm_slice_count(const struct pipe_ctx *pipe);</div><div class='ctx'> /* Get the ODM slice index counting from 0 from left most slice */</div><div class='ctx'> int resource_get_odm_slice_index(const struct pipe_ctx *opp_head);</div><div class='ctx'> </div><div class='add'>+/* Get ODM slice source rect in timing active as input to OPP block */</div><div class='add'>+struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+/* Get ODM slice destination rect in timing active as output from OPP block */</div><div class='add'>+struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='add'>+/* Get ODM slice destination width in timing active as output from OPP block */</div><div class='add'>+int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,</div><div class='add'>+		bool is_last_segment);</div><div class='add'>+</div><div class='ctx'> /* determine if pipe topology is changed between state a and state b */</div><div class='ctx'> bool resource_is_pipe_topology_changed(const struct dc_state *state_a,</div><div class='ctx'> 		const struct dc_state *state_b);</div><div class='hunk'>@@ -510,6 +530,17 @@ int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Look for a free pipe in new resource context that is used as a secondary DPP</div><div class='add'>+ * pipe in current resource context.</div><div class='add'>+ * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise</div><div class='add'>+ * pipe idx of the free pipe</div><div class='add'>+ */</div><div class='add'>+int resource_find_free_pipe_used_as_cur_sec_dpp(</div><div class='add'>+		const struct resource_context *cur_res_ctx,</div><div class='add'>+		struct resource_context *new_res_ctx,</div><div class='add'>+		const struct resource_pool *pool);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Look for a free pipe in new resource context that is used as a secondary DPP</div><div class='ctx'>  * pipe in any MPCC combine in current resource context.</div><div class='ctx'>  * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise</div><div class='ctx'>  * pipe idx of the free pipe</div><div class='hunk'>@@ -573,13 +604,6 @@ bool get_temp_dp_link_res(struct dc_link *link,</div><div class='ctx'> 		struct link_resource *link_res,</div><div class='ctx'> 		struct dc_link_settings *link_settings);</div><div class='ctx'> </div><div class='del'>-#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='del'>-struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(</div><div class='del'>-		const struct resource_context *res_ctx,</div><div class='del'>-		const struct resource_pool *pool,</div><div class='del'>-		const struct dc_link *link);</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,</div><div class='ctx'> 	struct dc_state *context);</div><div class='ctx'> </div><div class='hunk'>@@ -614,5 +638,26 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='del'>-bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream);</div><div class='add'>+/* Get hw programming parameters container from pipe context</div><div class='add'>+ * @pipe_ctx: pipe context</div><div class='add'>+ * @dscl_prog_data: struct to hold programmable hw reg values</div><div class='add'>+ */</div><div class='add'>+struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx);</div><div class='add'>+/* Setup dc callbacks for dml2</div><div class='add'>+ * @dc: the display core structure</div><div class='add'>+ * @dml2_options: struct to hold callbacks</div><div class='add'>+ */</div><div class='add'>+void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuration_options *dml2_options);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ *Calculate total DET allocated for all pipes for a given OTG_MASTER pipe</div><div class='add'>+ */</div><div class='add'>+int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master);</div><div class='add'>+</div><div class='add'>+bool resource_is_hpo_acquired(struct dc_state *context);</div><div class='add'>+</div><div class='add'>+struct link_encoder *get_temp_dio_link_enc(</div><div class='add'>+		const struct resource_context *res_ctx,</div><div class='add'>+		const struct resource_pool *const pool,</div><div class='add'>+		const struct dc_link *link);</div><div class='ctx'> #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h<br/>new file mode 100644<br/>index 000000000000..23daf98b8aa8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __SOC_AND_IP_TRANSLATOR_H__</div><div class='add'>+#define __SOC_AND_IP_TRANSLATOR_H__</div><div class='add'>+</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "dml_top_soc_parameter_types.h"</div><div class='add'>+</div><div class='add'>+struct soc_and_ip_translator_funcs {</div><div class='add'>+	void (*get_soc_bb)(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);</div><div class='add'>+	void (*get_ip_caps)(struct dml2_ip_capabilities *dml_ip_caps);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct soc_and_ip_translator {</div><div class='add'>+	const struct soc_and_ip_translator_funcs *translator_funcs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct soc_and_ip_translator *dc_create_soc_and_ip_translator(enum dce_version dc_version);</div><div class='add'>+void dc_destroy_soc_and_ip_translator(struct soc_and_ip_translator **soc_and_ip_translator);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#endif // __SOC_AND_IP_TRANSLATOR_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile<br/>index 2d4378780c1a..b5e14d792378 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/Makefile</a></div><div class='hunk'>@@ -180,3 +180,21 @@ IRQ_DCN351 = irq_service_dcn351.o</div><div class='ctx'> AMD_DAL_IRQ_DCN351= $(addprefix $(AMDDALPATH)/dc/irq/dcn351/,$(IRQ_DCN351))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN351)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN 36</div><div class='add'>+###############################################################################</div><div class='add'>+IRQ_DCN36 = irq_service_dcn36.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_IRQ_DCN36= $(addprefix $(AMDDALPATH)/dc/irq/dcn36/,$(IRQ_DCN36))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN36)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN 401</div><div class='add'>+###############################################################################</div><div class='add'>+IRQ_DCN401 = irq_service_dcn401.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_IRQ_DCN401= $(addprefix $(AMDDALPATH)/dc/irq/dcn401/,$(IRQ_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN401)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c<br/>index 1c0d89e675da..bb576a9c5fdb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c</a></div><div class='hunk'>@@ -211,8 +211,12 @@ bool dce110_vblank_set(struct irq_service *irq_service,</div><div class='ctx'> 						   info-&gt;ext_id);</div><div class='ctx'> 	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;</div><div class='ctx'> </div><div class='del'>-	struct timing_generator *tg =</div><div class='del'>-			dc-&gt;current_state-&gt;res_ctx.pipe_ctx[pipe_offset].stream_res.tg;</div><div class='add'>+	struct timing_generator *tg;</div><div class='add'>+</div><div class='add'>+	if (pipe_offset &gt;= MAX_PIPES)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	tg = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[pipe_offset].stream_res.tg;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		if (!tg || !tg-&gt;funcs-&gt;arm_vert_intr(tg, 2)) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c<br/>index 953f4a4dacad..33ce470e4c88 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c</a></div><div class='hunk'>@@ -37,36 +37,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "ivsrcid/ivsrcid_vislands30.h"</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c<br/>index 2c72074310c7..d777b85e70da 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c</a></div><div class='hunk'>@@ -46,36 +46,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "dc_types.h"</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			DC_HPD1_INT_STATUS,</div><div class='del'>-			DC_HPD1_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		DC_HPD1_INT_CONTROL,</div><div class='del'>-		DC_HPD1_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd1_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='hunk'>@@ -391,5 +364,3 @@ struct irq_service *dal_irq_service_dce60_create(</div><div class='ctx'> 	dce60_irq_construct(irq_service, init_data);</div><div class='ctx'> 	return irq_service;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c<br/>index 49317934ef4f..3a9163acb49b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c</a></div><div class='hunk'>@@ -37,36 +37,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "dc_types.h"</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			DC_HPD1_INT_STATUS,</div><div class='del'>-			DC_HPD1_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		DC_HPD1_INT_CONTROL,</div><div class='del'>-		DC_HPD1_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd1_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='hunk'>@@ -303,5 +276,3 @@ struct irq_service *dal_irq_service_dce80_create(</div><div class='ctx'> 	dce80_irq_construct(irq_service, init_data);</div><div class='ctx'> 	return irq_service;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c<br/>index 9ca28565a9d1..4ce9edd16344 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c</a></div><div class='hunk'>@@ -129,36 +129,9 @@ static enum dc_irq_source to_dal_irq_source_dcn10(struct irq_service *irq_servic</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c<br/>index 916f0c974637..5847af0e66cb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c</a></div><div class='hunk'>@@ -130,36 +130,9 @@ static enum dc_irq_source to_dal_irq_source_dcn20(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c b/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c<br/>index 4fb9cd6708d5..6417011d2246 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c</a></div><div class='hunk'>@@ -30,8 +30,8 @@</div><div class='ctx'> #include "../dce110/irq_service_dce110.h"</div><div class='ctx'> #include "irq_service_dcn201.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn/dcn_2_0_3_offset.h"</div><div class='del'>-#include "dcn/dcn_2_0_3_sh_mask.h"</div><div class='add'>+#include "dcn/dcn_2_0_1_offset.h"</div><div class='add'>+#include "dcn/dcn_2_0_1_sh_mask.h"</div><div class='ctx'> </div><div class='ctx'> #include "cyan_skillfish_ip_offset.h"</div><div class='ctx'> #include "soc15_hw_ip.h"</div><div class='hunk'>@@ -80,36 +80,9 @@ static enum dc_irq_source to_dal_irq_source_dcn201(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c<br/>index 42cdfe6c3538..71d2f065140b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c</a></div><div class='hunk'>@@ -132,36 +132,9 @@ static enum dc_irq_source to_dal_irq_source_dcn21(struct irq_service *irq_servic</div><div class='ctx'> 	return DC_IRQ_SOURCE_INVALID;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c<br/>index a443a8abb1ea..2a4080bdcf6b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c</a></div><div class='hunk'>@@ -139,36 +139,9 @@ static enum dc_irq_source to_dal_irq_source_dcn30(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='hunk'>@@ -447,4 +420,3 @@ struct irq_service *dal_irq_service_dcn30_create(</div><div class='ctx'> 	dcn30_irq_construct(irq_service, init_data);</div><div class='ctx'> 	return irq_service;</div><div class='ctx'> }</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c<br/>index 8ffc7e2c681a..624f1ac309f8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c</a></div><div class='hunk'>@@ -126,26 +126,9 @@ static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_servi</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 		.set = NULL,</div><div class='del'>-		.ack = hpd_ack</div><div class='add'>+		.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c b/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c<br/>index 262bb8b74b15..137caffae916 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c</a></div><div class='hunk'>@@ -77,26 +77,9 @@ static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_servi</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 		.set = NULL,</div><div class='del'>-		.ack = hpd_ack</div><div class='add'>+		.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c<br/>index 53e78ae7eecf..921cb167d920 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c</a></div><div class='hunk'>@@ -128,36 +128,9 @@ static enum dc_irq_source to_dal_irq_source_dcn31(struct irq_service *irq_servic</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c b/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c<br/>index e0563e880432..0118fd6e5db0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c</a></div><div class='hunk'>@@ -130,36 +130,9 @@ static enum dc_irq_source to_dal_irq_source_dcn314(struct irq_service *irq_servi</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c b/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c<br/>index 2ef22299101a..adebfc888618 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c</a></div><div class='hunk'>@@ -135,36 +135,9 @@ static enum dc_irq_source to_dal_irq_source_dcn315(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c b/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c<br/>index f0ac0aeeac51..e9e315c75d76 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c</a></div><div class='hunk'>@@ -129,36 +129,9 @@ static enum dc_irq_source to_dal_irq_source_dcn32(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs  = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='hunk'>@@ -191,6 +164,16 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {</div><div class='ctx'> 	.ack = NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct irq_source_info_funcs vline1_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vline2_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #undef BASE_INNER</div><div class='ctx'> #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='ctx'> </div><div class='hunk'>@@ -259,6 +242,13 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {</div><div class='ctx'> 		.funcs = &amp;pflip_irq_info_funcs\</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#define vblank_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\</div><div class='add'>+		.funcs = &amp;vblank_irq_info_funcs\</div><div class='add'>+	}</div><div class='ctx'> /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic</div><div class='ctx'>  * of DCE's DC_IRQ_SOURCE_VUPDATEx.</div><div class='ctx'>  */</div><div class='hunk'>@@ -270,14 +260,6 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {</div><div class='ctx'> 		.funcs = &amp;vupdate_no_lock_irq_info_funcs\</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-#define vblank_int_entry(reg_num)\</div><div class='del'>-	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\</div><div class='del'>-		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='del'>-			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\</div><div class='del'>-			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\</div><div class='del'>-		.funcs = &amp;vblank_irq_info_funcs\</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #define vline0_int_entry(reg_num)\</div><div class='ctx'> 	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\</div><div class='ctx'> 		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='hunk'>@@ -285,6 +267,20 @@ static struct irq_source_info_funcs vline0_irq_info_funcs = {</div><div class='ctx'> 			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\</div><div class='ctx'> 		.funcs = &amp;vline0_irq_info_funcs\</div><div class='ctx'> 	}</div><div class='add'>+#define vline1_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\</div><div class='add'>+		.funcs = &amp;vline1_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+#define vline2_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\</div><div class='add'>+		.funcs = &amp;vline2_irq_info_funcs\</div><div class='add'>+	}</div><div class='ctx'> #define dmub_outbox_int_entry()\</div><div class='ctx'> 	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\</div><div class='ctx'> 		IRQ_REG_ENTRY_DMUB(\</div><div class='hunk'>@@ -387,21 +383,29 @@ irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {</div><div class='ctx'> 	dc_underflow_int_entry(6),</div><div class='ctx'> 	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),</div><div class='ctx'> 	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),</div><div class='del'>-	vupdate_no_lock_int_entry(0),</div><div class='del'>-	vupdate_no_lock_int_entry(1),</div><div class='del'>-	vupdate_no_lock_int_entry(2),</div><div class='del'>-	vupdate_no_lock_int_entry(3),</div><div class='ctx'> 	vblank_int_entry(0),</div><div class='ctx'> 	vblank_int_entry(1),</div><div class='ctx'> 	vblank_int_entry(2),</div><div class='ctx'> 	vblank_int_entry(3),</div><div class='add'>+	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),</div><div class='add'>+	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),</div><div class='add'>+	dmub_outbox_int_entry(),</div><div class='add'>+	vupdate_no_lock_int_entry(0),</div><div class='add'>+	vupdate_no_lock_int_entry(1),</div><div class='add'>+	vupdate_no_lock_int_entry(2),</div><div class='add'>+	vupdate_no_lock_int_entry(3),</div><div class='ctx'> 	vline0_int_entry(0),</div><div class='ctx'> 	vline0_int_entry(1),</div><div class='ctx'> 	vline0_int_entry(2),</div><div class='ctx'> 	vline0_int_entry(3),</div><div class='del'>-	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),</div><div class='del'>-	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),</div><div class='del'>-	dmub_outbox_int_entry(),</div><div class='add'>+	vline1_int_entry(0),</div><div class='add'>+	vline1_int_entry(1),</div><div class='add'>+	vline1_int_entry(2),</div><div class='add'>+	vline1_int_entry(3),</div><div class='add'>+	vline2_int_entry(0),</div><div class='add'>+	vline2_int_entry(1),</div><div class='add'>+	vline2_int_entry(2),</div><div class='add'>+	vline2_int_entry(3)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct irq_service_funcs irq_service_funcs_dcn32 = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c b/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c<br/>index ea8c271171bc..79e5e8c137ca 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c</a></div><div class='hunk'>@@ -127,36 +127,9 @@ static enum dc_irq_source to_dal_irq_source_dcn35(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c b/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c<br/>index 7ec8e0de2f01..163b8ee9ebf7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c</a></div><div class='hunk'>@@ -106,36 +106,9 @@ static enum dc_irq_source to_dal_irq_source_dcn351(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool hpd_ack(</div><div class='del'>-	struct irq_service *irq_service,</div><div class='del'>-	const struct irq_source_info *info)</div><div class='del'>-{</div><div class='del'>-	uint32_t addr = info-&gt;status_reg;</div><div class='del'>-	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='del'>-	uint32_t current_status =</div><div class='del'>-		get_reg_field_value(</div><div class='del'>-			value,</div><div class='del'>-			HPD0_DC_HPD_INT_STATUS,</div><div class='del'>-			DC_HPD_SENSE_DELAYED);</div><div class='del'>-</div><div class='del'>-	dal_irq_service_ack_generic(irq_service, info);</div><div class='del'>-</div><div class='del'>-	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='del'>-</div><div class='del'>-	set_reg_field_value(</div><div class='del'>-		value,</div><div class='del'>-		current_status ? 0 : 1,</div><div class='del'>-		HPD0_DC_HPD_INT_CONTROL,</div><div class='del'>-		DC_HPD_INT_POLARITY);</div><div class='del'>-</div><div class='del'>-	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct irq_source_info_funcs hpd_irq_info_funcs = {</div><div class='ctx'> 	.set = NULL,</div><div class='del'>-	.ack = hpd_ack</div><div class='add'>+	.ack = hpd0_ack</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c b/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c<br/>new file mode 100644<br/>index 000000000000..f716ab0fd30e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c</a></div><div class='hunk'>@@ -0,0 +1,381 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "include/logger_interface.h"</div><div class='add'>+#include "../dce110/irq_service_dce110.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_3_6_0_offset.h"</div><div class='add'>+#include "dcn/dcn_3_6_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#include "irq_service_dcn36.h"</div><div class='add'>+</div><div class='add'>+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"</div><div class='add'>+</div><div class='add'>+static enum dc_irq_source to_dal_irq_source_dcn36(</div><div class='add'>+		struct irq_service *irq_service,</div><div class='add'>+		uint32_t src_id,</div><div class='add'>+		uint32_t ext_id)</div><div class='add'>+{</div><div class='add'>+	switch (src_id) {</div><div class='add'>+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK1;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK2;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK3;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK4;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK5;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK6;</div><div class='add'>+	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC1_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC2_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC3_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC4_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC5_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC6_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP1;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP2;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP3;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP4;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP5;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP6;</div><div class='add'>+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE1;</div><div class='add'>+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE2;</div><div class='add'>+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE3;</div><div class='add'>+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE4;</div><div class='add'>+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE5;</div><div class='add'>+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE6;</div><div class='add'>+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:</div><div class='add'>+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;</div><div class='add'>+	case DCN_1_0__SRCID__DC_HPD1_INT:</div><div class='add'>+		/* generic src_id for all HPD and HPDRX interrupts */</div><div class='add'>+		switch (ext_id) {</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD1_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD1;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD2_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD2;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD3_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD3;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD4_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD4;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD5_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD5;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD6_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD6;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD1RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD2RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD3RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD4RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD5RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD6RX;</div><div class='add'>+		default:</div><div class='add'>+			return DC_IRQ_SOURCE_INVALID;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return DC_IRQ_SOURCE_INVALID;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs hpd_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = hpd0_ack</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs pflip_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vblank_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs outbox_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vline0_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#undef BASE_INNER</div><div class='add'>+#define BASE_INNER(seg) ctx-&gt;dcn_reg_offsets[seg]</div><div class='add'>+</div><div class='add'>+/* compile time expand base address. */</div><div class='add'>+#define BASE(seg) \</div><div class='add'>+	BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SRI(reg_name, block, id)\</div><div class='add'>+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+			reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_DMUB(reg_name)\</div><div class='add'>+	BASE(reg ## reg_name ## _BASE_IDX) + \</div><div class='add'>+			reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\</div><div class='add'>+	REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\</div><div class='add'>+	REG_STRUCT[base + reg_num].enable_mask = \</div><div class='add'>+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+	REG_STRUCT[base + reg_num].enable_value[0] = \</div><div class='add'>+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+	REG_STRUCT[base + reg_num].enable_value[1] = \</div><div class='add'>+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \</div><div class='add'>+	REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\</div><div class='add'>+	REG_STRUCT[base + reg_num].ack_mask = \</div><div class='add'>+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\</div><div class='add'>+	REG_STRUCT[base + reg_num].ack_value = \</div><div class='add'>+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \</div><div class='add'>+</div><div class='add'>+#define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\</div><div class='add'>+	REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\</div><div class='add'>+	REG_STRUCT[base].enable_mask = \</div><div class='add'>+		reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+	REG_STRUCT[base].enable_value[0] = \</div><div class='add'>+		reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+	REG_STRUCT[base].enable_value[1] = \</div><div class='add'>+		~reg1 ## __ ## mask1 ## _MASK, \</div><div class='add'>+	REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\</div><div class='add'>+	REG_STRUCT[base].ack_mask = \</div><div class='add'>+		reg2 ## __ ## mask2 ## _MASK,\</div><div class='add'>+	REG_STRUCT[base].ack_value = \</div><div class='add'>+		reg2 ## __ ## mask2 ## _MASK \</div><div class='add'>+</div><div class='add'>+#define hpd_int_entry(reg_num)\</div><div class='add'>+		IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1, HPD, reg_num,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &amp;hpd_irq_info_funcs;\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\</div><div class='add'>+</div><div class='add'>+#define hpd_rx_int_entry(reg_num)\</div><div class='add'>+		IRQ_REG_ENTRY(DC_IRQ_SOURCE_HPD1RX, HPD, reg_num,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &amp;hpd_rx_irq_info_funcs;\</div><div class='add'>+</div><div class='add'>+#define pflip_int_entry(reg_num)\</div><div class='add'>+		IRQ_REG_ENTRY(DC_IRQ_SOURCE_PFLIP1, HUBPREQ, reg_num,\</div><div class='add'>+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\</div><div class='add'>+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &amp;pflip_irq_info_funcs\</div><div class='add'>+</div><div class='add'>+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic</div><div class='add'>+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.</div><div class='add'>+ */</div><div class='add'>+#define vupdate_no_lock_int_entry(reg_num)\</div><div class='add'>+		IRQ_REG_ENTRY(DC_IRQ_SOURCE_VUPDATE1, OTG, reg_num,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &amp;vupdate_no_lock_irq_info_funcs\</div><div class='add'>+</div><div class='add'>+#define vblank_int_entry(reg_num)\</div><div class='add'>+		IRQ_REG_ENTRY(DC_IRQ_SOURCE_VBLANK1, OTG, reg_num,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &amp;vblank_irq_info_funcs\</div><div class='add'>+</div><div class='add'>+#define vline0_int_entry(reg_num)\</div><div class='add'>+		IRQ_REG_ENTRY(DC_IRQ_SOURCE_DC1_VLINE0, OTG, reg_num,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &amp;vline0_irq_info_funcs\</div><div class='add'>+</div><div class='add'>+#define dmub_outbox_int_entry()\</div><div class='add'>+		IRQ_REG_ENTRY_DMUB(DC_IRQ_SOURCE_DMCUB_OUTBOX, \</div><div class='add'>+			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\</div><div class='add'>+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\</div><div class='add'>+		REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &amp;outbox_irq_info_funcs</div><div class='add'>+</div><div class='add'>+#define dummy_irq_entry(irqno) \</div><div class='add'>+	REG_STRUCT[irqno].funcs = &amp;dummy_irq_info_funcs\</div><div class='add'>+</div><div class='add'>+#define i2c_int_entry(reg_num) \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_I2C_DDC ## reg_num)</div><div class='add'>+</div><div class='add'>+#define dp_sink_int_entry(reg_num) \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_DPSINK ## reg_num)</div><div class='add'>+</div><div class='add'>+#define gpio_pad_int_entry(reg_num) \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_GPIOPAD ## reg_num)</div><div class='add'>+</div><div class='add'>+#define dc_underflow_int_entry(reg_num) \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW)</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs dummy_irq_info_funcs = {</div><div class='add'>+	.set = dal_irq_service_dummy_set,</div><div class='add'>+	.ack = dal_irq_service_dummy_ack</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define dcn36_irq_init_part_1() {\</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_INVALID); \</div><div class='add'>+	hpd_int_entry(0); \</div><div class='add'>+	hpd_int_entry(1); \</div><div class='add'>+	hpd_int_entry(2); \</div><div class='add'>+	hpd_int_entry(3); \</div><div class='add'>+	hpd_int_entry(4); \</div><div class='add'>+	hpd_rx_int_entry(0); \</div><div class='add'>+	hpd_rx_int_entry(1); \</div><div class='add'>+	hpd_rx_int_entry(2); \</div><div class='add'>+	hpd_rx_int_entry(3); \</div><div class='add'>+	hpd_rx_int_entry(4); \</div><div class='add'>+	i2c_int_entry(1); \</div><div class='add'>+	i2c_int_entry(2); \</div><div class='add'>+	i2c_int_entry(3); \</div><div class='add'>+	i2c_int_entry(4); \</div><div class='add'>+	i2c_int_entry(5); \</div><div class='add'>+	i2c_int_entry(6); \</div><div class='add'>+	dp_sink_int_entry(1); \</div><div class='add'>+	dp_sink_int_entry(2); \</div><div class='add'>+	dp_sink_int_entry(3); \</div><div class='add'>+	dp_sink_int_entry(4); \</div><div class='add'>+	dp_sink_int_entry(5); \</div><div class='add'>+	dp_sink_int_entry(6); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_TIMER); \</div><div class='add'>+	pflip_int_entry(0); \</div><div class='add'>+	pflip_int_entry(1); \</div><div class='add'>+	pflip_int_entry(2); \</div><div class='add'>+	pflip_int_entry(3); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_PFLIP5); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_PFLIP6); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_PFLIP_UNDERLAY0); \</div><div class='add'>+	gpio_pad_int_entry(0); \</div><div class='add'>+	gpio_pad_int_entry(1); \</div><div class='add'>+	gpio_pad_int_entry(2); \</div><div class='add'>+	gpio_pad_int_entry(3); \</div><div class='add'>+	gpio_pad_int_entry(4); \</div><div class='add'>+	gpio_pad_int_entry(5); \</div><div class='add'>+	gpio_pad_int_entry(6); \</div><div class='add'>+	gpio_pad_int_entry(7); \</div><div class='add'>+	gpio_pad_int_entry(8); \</div><div class='add'>+	gpio_pad_int_entry(9); \</div><div class='add'>+	gpio_pad_int_entry(10); \</div><div class='add'>+	gpio_pad_int_entry(11); \</div><div class='add'>+	gpio_pad_int_entry(12); \</div><div class='add'>+	gpio_pad_int_entry(13); \</div><div class='add'>+	gpio_pad_int_entry(14); \</div><div class='add'>+	gpio_pad_int_entry(15); \</div><div class='add'>+	gpio_pad_int_entry(16); \</div><div class='add'>+	gpio_pad_int_entry(17); \</div><div class='add'>+	gpio_pad_int_entry(18); \</div><div class='add'>+	gpio_pad_int_entry(19); \</div><div class='add'>+	gpio_pad_int_entry(20); \</div><div class='add'>+	gpio_pad_int_entry(21); \</div><div class='add'>+	gpio_pad_int_entry(22); \</div><div class='add'>+	gpio_pad_int_entry(23); \</div><div class='add'>+	gpio_pad_int_entry(24); \</div><div class='add'>+	gpio_pad_int_entry(25); \</div><div class='add'>+	gpio_pad_int_entry(26); \</div><div class='add'>+	gpio_pad_int_entry(27); \</div><div class='add'>+	gpio_pad_int_entry(28); \</div><div class='add'>+	gpio_pad_int_entry(29); \</div><div class='add'>+	gpio_pad_int_entry(30); \</div><div class='add'>+	dc_underflow_int_entry(1); \</div><div class='add'>+	dc_underflow_int_entry(2); \</div><div class='add'>+	dc_underflow_int_entry(3); \</div><div class='add'>+	dc_underflow_int_entry(4); \</div><div class='add'>+	dc_underflow_int_entry(5); \</div><div class='add'>+	dc_underflow_int_entry(6); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_DMCU_SCP); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_VBIOS_SW); \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define dcn36_irq_init_part_2() {\</div><div class='add'>+	vupdate_no_lock_int_entry(0); \</div><div class='add'>+	vupdate_no_lock_int_entry(1); \</div><div class='add'>+	vupdate_no_lock_int_entry(2); \</div><div class='add'>+	vupdate_no_lock_int_entry(3); \</div><div class='add'>+	vblank_int_entry(0); \</div><div class='add'>+	vblank_int_entry(1); \</div><div class='add'>+	vblank_int_entry(2); \</div><div class='add'>+	vblank_int_entry(3); \</div><div class='add'>+	vline0_int_entry(0); \</div><div class='add'>+	vline0_int_entry(1); \</div><div class='add'>+	vline0_int_entry(2); \</div><div class='add'>+	vline0_int_entry(3); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_DC5_VLINE1); \</div><div class='add'>+	dummy_irq_entry(DC_IRQ_SOURCE_DC6_VLINE1); \</div><div class='add'>+	dmub_outbox_int_entry(); \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define dcn36_irq_init() {\</div><div class='add'>+	dcn36_irq_init_part_1(); \</div><div class='add'>+	dcn36_irq_init_part_2(); \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct irq_source_info irq_source_info_dcn36[DAL_IRQ_SOURCES_NUMBER] = {0};</div><div class='add'>+</div><div class='add'>+static struct irq_service_funcs irq_service_funcs_dcn36 = {</div><div class='add'>+		.to_dal_irq_source = to_dal_irq_source_dcn36</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn36_irq_construct(</div><div class='add'>+	struct irq_service *irq_service,</div><div class='add'>+	struct irq_service_init_data *init_data)</div><div class='add'>+{</div><div class='add'>+	struct dc_context *ctx = init_data-&gt;ctx;</div><div class='add'>+</div><div class='add'>+#define REG_STRUCT irq_source_info_dcn36</div><div class='add'>+	dcn36_irq_init();</div><div class='add'>+</div><div class='add'>+	dal_irq_service_construct(irq_service, init_data);</div><div class='add'>+</div><div class='add'>+	irq_service-&gt;info = irq_source_info_dcn36;</div><div class='add'>+	irq_service-&gt;funcs = &amp;irq_service_funcs_dcn36;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct irq_service *dal_irq_service_dcn36_create(</div><div class='add'>+	struct irq_service_init_data *init_data)</div><div class='add'>+{</div><div class='add'>+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),</div><div class='add'>+						  GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!irq_service)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dcn36_irq_construct(irq_service, init_data);</div><div class='add'>+	return irq_service;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.h b/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.h<br/>new file mode 100644<br/>index 000000000000..21ff95f6562d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.h</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef __DAL_IRQ_SERVICE_DCN36_H__</div><div class='add'>+#define __DAL_IRQ_SERVICE_DCN36_H__</div><div class='add'>+</div><div class='add'>+#include "../irq_service.h"</div><div class='add'>+</div><div class='add'>+struct irq_service *dal_irq_service_dcn36_create(</div><div class='add'>+	struct irq_service_init_data *init_data);</div><div class='add'>+</div><div class='add'>+#endif /* __DAL_IRQ_SERVICE_DCN36_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c<br/>new file mode 100644<br/>index 000000000000..fd9bb1950c20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c</a></div><div class='hunk'>@@ -0,0 +1,414 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "include/logger_interface.h"</div><div class='add'>+#include "../dce110/irq_service_dce110.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_4_1_0_offset.h"</div><div class='add'>+#include "dcn/dcn_4_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#include "irq_service_dcn401.h"</div><div class='add'>+</div><div class='add'>+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"</div><div class='add'>+</div><div class='add'>+#define DCN_BASE__INST0_SEG2                       0x000034C0</div><div class='add'>+</div><div class='add'>+static enum dc_irq_source to_dal_irq_source_dcn401(</div><div class='add'>+		struct irq_service *irq_service,</div><div class='add'>+		uint32_t src_id,</div><div class='add'>+		uint32_t ext_id)</div><div class='add'>+{</div><div class='add'>+	switch (src_id) {</div><div class='add'>+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK1;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK2;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK3;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK4;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK5;</div><div class='add'>+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:</div><div class='add'>+		return DC_IRQ_SOURCE_VBLANK6;</div><div class='add'>+	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC1_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC2_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC3_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC4_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC5_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:</div><div class='add'>+		return DC_IRQ_SOURCE_DC6_VLINE0;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP1;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP2;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP3;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP4;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP5;</div><div class='add'>+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_PFLIP6;</div><div class='add'>+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE1;</div><div class='add'>+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE2;</div><div class='add'>+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE3;</div><div class='add'>+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE4;</div><div class='add'>+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE5;</div><div class='add'>+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:</div><div class='add'>+		return DC_IRQ_SOURCE_VUPDATE6;</div><div class='add'>+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:</div><div class='add'>+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;</div><div class='add'>+</div><div class='add'>+	case DCN_1_0__SRCID__DC_HPD1_INT:</div><div class='add'>+		/* generic src_id for all HPD and HPDRX interrupts */</div><div class='add'>+		switch (ext_id) {</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD1_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD1;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD2_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD2;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD3_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD3;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD4_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD4;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD5_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD5;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD6_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD6;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD1RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD2RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD3RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD4RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD5RX;</div><div class='add'>+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:</div><div class='add'>+			return DC_IRQ_SOURCE_HPD6RX;</div><div class='add'>+		default:</div><div class='add'>+			return DC_IRQ_SOURCE_INVALID;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return DC_IRQ_SOURCE_INVALID;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs hpd_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = hpd0_ack</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs pflip_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vblank_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs outbox_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vline0_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vline1_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs vline2_irq_info_funcs = {</div><div class='add'>+	.set = NULL,</div><div class='add'>+	.ack = NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#undef BASE_INNER</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg</div><div class='add'>+</div><div class='add'>+/* compile time expand base address. */</div><div class='add'>+#define BASE(seg) \</div><div class='add'>+	BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SRI(reg_name, block, id)\</div><div class='add'>+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+			reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_DMUB(reg_name)\</div><div class='add'>+	BASE(reg ## reg_name ## _BASE_IDX) + \</div><div class='add'>+			reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\</div><div class='add'>+	.enable_reg = SRI(reg1, block, reg_num),\</div><div class='add'>+	.enable_mask = \</div><div class='add'>+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+	.enable_value = {\</div><div class='add'>+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \</div><div class='add'>+	},\</div><div class='add'>+	.ack_reg = SRI(reg2, block, reg_num),\</div><div class='add'>+	.ack_mask = \</div><div class='add'>+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\</div><div class='add'>+	.ack_value = \</div><div class='add'>+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \</div><div class='add'>+</div><div class='add'>+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\</div><div class='add'>+	.enable_reg = SRI_DMUB(reg1),\</div><div class='add'>+	.enable_mask = \</div><div class='add'>+		reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+	.enable_value = {\</div><div class='add'>+		reg1 ## __ ## mask1 ## _MASK,\</div><div class='add'>+		~reg1 ## __ ## mask1 ## _MASK \</div><div class='add'>+	},\</div><div class='add'>+	.ack_reg = SRI_DMUB(reg2),\</div><div class='add'>+	.ack_mask = \</div><div class='add'>+		reg2 ## __ ## mask2 ## _MASK,\</div><div class='add'>+	.ack_value = \</div><div class='add'>+		reg2 ## __ ## mask2 ## _MASK \</div><div class='add'>+</div><div class='add'>+#define hpd_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(HPD, reg_num,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\</div><div class='add'>+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\</div><div class='add'>+		.funcs = &amp;hpd_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define hpd_rx_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(HPD, reg_num,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\</div><div class='add'>+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\</div><div class='add'>+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\</div><div class='add'>+		.funcs = &amp;hpd_rx_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+#define pflip_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\</div><div class='add'>+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\</div><div class='add'>+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\</div><div class='add'>+		.funcs = &amp;pflip_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define vblank_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\</div><div class='add'>+		.funcs = &amp;vblank_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic</div><div class='add'>+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.</div><div class='add'>+ */</div><div class='add'>+#define vupdate_no_lock_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\</div><div class='add'>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\</div><div class='add'>+		.funcs = &amp;vupdate_no_lock_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define vline0_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\</div><div class='add'>+		.funcs = &amp;vline0_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+#define vline1_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\</div><div class='add'>+		.funcs = &amp;vline1_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+#define vline2_int_entry(reg_num)\</div><div class='add'>+	[DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\</div><div class='add'>+		IRQ_REG_ENTRY(OTG, reg_num,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\</div><div class='add'>+			OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\</div><div class='add'>+		.funcs = &amp;vline2_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+#define dmub_outbox_int_entry()\</div><div class='add'>+	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\</div><div class='add'>+		IRQ_REG_ENTRY_DMUB(\</div><div class='add'>+			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\</div><div class='add'>+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\</div><div class='add'>+		.funcs = &amp;outbox_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define dummy_irq_entry() \</div><div class='add'>+	{\</div><div class='add'>+		.funcs = &amp;dummy_irq_info_funcs\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define i2c_int_entry(reg_num) \</div><div class='add'>+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()</div><div class='add'>+</div><div class='add'>+#define dp_sink_int_entry(reg_num) \</div><div class='add'>+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()</div><div class='add'>+</div><div class='add'>+#define gpio_pad_int_entry(reg_num) \</div><div class='add'>+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()</div><div class='add'>+</div><div class='add'>+#define dc_underflow_int_entry(reg_num) \</div><div class='add'>+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()</div><div class='add'>+</div><div class='add'>+static struct irq_source_info_funcs dummy_irq_info_funcs = {</div><div class='add'>+	.set = dal_irq_service_dummy_set,</div><div class='add'>+	.ack = dal_irq_service_dummy_ack</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct irq_source_info</div><div class='add'>+irq_source_info_dcn401[DAL_IRQ_SOURCES_NUMBER] = {</div><div class='add'>+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),</div><div class='add'>+	hpd_int_entry(0),</div><div class='add'>+	hpd_int_entry(1),</div><div class='add'>+	hpd_int_entry(2),</div><div class='add'>+	hpd_int_entry(3),</div><div class='add'>+	hpd_rx_int_entry(0),</div><div class='add'>+	hpd_rx_int_entry(1),</div><div class='add'>+	hpd_rx_int_entry(2),</div><div class='add'>+	hpd_rx_int_entry(3),</div><div class='add'>+	i2c_int_entry(1),</div><div class='add'>+	i2c_int_entry(2),</div><div class='add'>+	i2c_int_entry(3),</div><div class='add'>+	i2c_int_entry(4),</div><div class='add'>+	i2c_int_entry(5),</div><div class='add'>+	i2c_int_entry(6),</div><div class='add'>+	dp_sink_int_entry(1),</div><div class='add'>+	dp_sink_int_entry(2),</div><div class='add'>+	dp_sink_int_entry(3),</div><div class='add'>+	dp_sink_int_entry(4),</div><div class='add'>+	dp_sink_int_entry(5),</div><div class='add'>+	dp_sink_int_entry(6),</div><div class='add'>+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),</div><div class='add'>+	pflip_int_entry(0),</div><div class='add'>+	pflip_int_entry(1),</div><div class='add'>+	pflip_int_entry(2),</div><div class='add'>+	pflip_int_entry(3),</div><div class='add'>+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),</div><div class='add'>+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),</div><div class='add'>+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),</div><div class='add'>+	gpio_pad_int_entry(0),</div><div class='add'>+	gpio_pad_int_entry(1),</div><div class='add'>+	gpio_pad_int_entry(2),</div><div class='add'>+	gpio_pad_int_entry(3),</div><div class='add'>+	gpio_pad_int_entry(4),</div><div class='add'>+	gpio_pad_int_entry(5),</div><div class='add'>+	gpio_pad_int_entry(6),</div><div class='add'>+	gpio_pad_int_entry(7),</div><div class='add'>+	gpio_pad_int_entry(8),</div><div class='add'>+	gpio_pad_int_entry(9),</div><div class='add'>+	gpio_pad_int_entry(10),</div><div class='add'>+	gpio_pad_int_entry(11),</div><div class='add'>+	gpio_pad_int_entry(12),</div><div class='add'>+	gpio_pad_int_entry(13),</div><div class='add'>+	gpio_pad_int_entry(14),</div><div class='add'>+	gpio_pad_int_entry(15),</div><div class='add'>+	gpio_pad_int_entry(16),</div><div class='add'>+	gpio_pad_int_entry(17),</div><div class='add'>+	gpio_pad_int_entry(18),</div><div class='add'>+	gpio_pad_int_entry(19),</div><div class='add'>+	gpio_pad_int_entry(20),</div><div class='add'>+	gpio_pad_int_entry(21),</div><div class='add'>+	gpio_pad_int_entry(22),</div><div class='add'>+	gpio_pad_int_entry(23),</div><div class='add'>+	gpio_pad_int_entry(24),</div><div class='add'>+	gpio_pad_int_entry(25),</div><div class='add'>+	gpio_pad_int_entry(26),</div><div class='add'>+	gpio_pad_int_entry(27),</div><div class='add'>+	gpio_pad_int_entry(28),</div><div class='add'>+	gpio_pad_int_entry(29),</div><div class='add'>+	gpio_pad_int_entry(30),</div><div class='add'>+	dc_underflow_int_entry(1),</div><div class='add'>+	dc_underflow_int_entry(2),</div><div class='add'>+	dc_underflow_int_entry(3),</div><div class='add'>+	dc_underflow_int_entry(4),</div><div class='add'>+	dc_underflow_int_entry(5),</div><div class='add'>+	dc_underflow_int_entry(6),</div><div class='add'>+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),</div><div class='add'>+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),</div><div class='add'>+	vblank_int_entry(0),</div><div class='add'>+	vblank_int_entry(1),</div><div class='add'>+	vblank_int_entry(2),</div><div class='add'>+	vblank_int_entry(3),</div><div class='add'>+	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),</div><div class='add'>+	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),</div><div class='add'>+	dmub_outbox_int_entry(),</div><div class='add'>+	vupdate_no_lock_int_entry(0),</div><div class='add'>+	vupdate_no_lock_int_entry(1),</div><div class='add'>+	vupdate_no_lock_int_entry(2),</div><div class='add'>+	vupdate_no_lock_int_entry(3),</div><div class='add'>+	vline0_int_entry(0),</div><div class='add'>+	vline0_int_entry(1),</div><div class='add'>+	vline0_int_entry(2),</div><div class='add'>+	vline0_int_entry(3),</div><div class='add'>+	vline1_int_entry(0),</div><div class='add'>+	vline1_int_entry(1),</div><div class='add'>+	vline1_int_entry(2),</div><div class='add'>+	vline1_int_entry(3),</div><div class='add'>+	vline2_int_entry(0),</div><div class='add'>+	vline2_int_entry(1),</div><div class='add'>+	vline2_int_entry(2),</div><div class='add'>+	vline2_int_entry(3),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct irq_service_funcs irq_service_funcs_dcn401 = {</div><div class='add'>+		.to_dal_irq_source = to_dal_irq_source_dcn401</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn401_irq_construct(</div><div class='add'>+	struct irq_service *irq_service,</div><div class='add'>+	struct irq_service_init_data *init_data)</div><div class='add'>+{</div><div class='add'>+	dal_irq_service_construct(irq_service, init_data);</div><div class='add'>+</div><div class='add'>+	irq_service-&gt;info = irq_source_info_dcn401;</div><div class='add'>+	irq_service-&gt;funcs = &amp;irq_service_funcs_dcn401;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct irq_service *dal_irq_service_dcn401_create(</div><div class='add'>+	struct irq_service_init_data *init_data)</div><div class='add'>+{</div><div class='add'>+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),</div><div class='add'>+						  GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!irq_service)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dcn401_irq_construct(irq_service, init_data);</div><div class='add'>+	return irq_service;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.h b/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.h<br/>new file mode 100644<br/>index 000000000000..221959aa6fc7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DAL_IRQ_SERVICE_DCN401_H__</div><div class='add'>+#define __DAL_IRQ_SERVICE_DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "../irq_service.h"</div><div class='add'>+</div><div class='add'>+struct irq_service *dal_irq_service_dcn401_create(</div><div class='add'>+	struct irq_service_init_data *init_data);</div><div class='add'>+</div><div class='add'>+#endif /* __DAL_IRQ_SERVICE_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c<br/>index d100edaedbbb..b595a11c5eaf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/irq_service.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/irq_service.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/irq_service.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/irq_service.c</a></div><div class='hunk'>@@ -41,6 +41,16 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "irq_service.h"</div><div class='ctx'> </div><div class='add'>+//HPD0_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK		0x00000010L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK		0x00000100L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT		0x4</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT     0x8</div><div class='add'>+//HPD1_DC_HPD_INT_STATUS</div><div class='add'>+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK			0x10</div><div class='add'>+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT		0x4</div><div class='add'>+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK			0x100</div><div class='add'>+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT		0x8</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #define CTX \</div><div class='hunk'>@@ -76,7 +86,7 @@ static const struct irq_source_info *find_irq_source_info(</div><div class='ctx'> 	struct irq_service *irq_service,</div><div class='ctx'> 	enum dc_irq_source source)</div><div class='ctx'> {</div><div class='del'>-	if (source &gt;= DAL_IRQ_SOURCES_NUMBER || source &lt; DC_IRQ_SOURCE_INVALID)</div><div class='add'>+	if (source &gt;= DAL_IRQ_SOURCES_NUMBER)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	return &amp;irq_service-&gt;info[source];</div><div class='hunk'>@@ -177,3 +187,57 @@ enum dc_irq_source dal_irq_service_to_irq_source(</div><div class='ctx'> 		src_id,</div><div class='ctx'> 		ext_id);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool hpd0_ack(</div><div class='add'>+	struct irq_service *irq_service,</div><div class='add'>+	const struct irq_source_info *info)</div><div class='add'>+{</div><div class='add'>+	uint32_t addr = info-&gt;status_reg;</div><div class='add'>+	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='add'>+	uint32_t current_status =</div><div class='add'>+		get_reg_field_value(</div><div class='add'>+			value,</div><div class='add'>+			HPD0_DC_HPD_INT_STATUS,</div><div class='add'>+			DC_HPD_SENSE_DELAYED);</div><div class='add'>+</div><div class='add'>+	dal_irq_service_ack_generic(irq_service, info);</div><div class='add'>+</div><div class='add'>+	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='add'>+</div><div class='add'>+	set_reg_field_value(</div><div class='add'>+		value,</div><div class='add'>+		current_status ? 0 : 1,</div><div class='add'>+		HPD0_DC_HPD_INT_CONTROL,</div><div class='add'>+		DC_HPD_INT_POLARITY);</div><div class='add'>+</div><div class='add'>+	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool hpd1_ack(</div><div class='add'>+	struct irq_service *irq_service,</div><div class='add'>+	const struct irq_source_info *info)</div><div class='add'>+{</div><div class='add'>+	uint32_t addr = info-&gt;status_reg;</div><div class='add'>+	uint32_t value = dm_read_reg(irq_service-&gt;ctx, addr);</div><div class='add'>+	uint32_t current_status =</div><div class='add'>+		get_reg_field_value(</div><div class='add'>+			value,</div><div class='add'>+			DC_HPD1_INT_STATUS,</div><div class='add'>+			DC_HPD1_SENSE_DELAYED);</div><div class='add'>+</div><div class='add'>+	dal_irq_service_ack_generic(irq_service, info);</div><div class='add'>+</div><div class='add'>+	value = dm_read_reg(irq_service-&gt;ctx, info-&gt;enable_reg);</div><div class='add'>+</div><div class='add'>+	set_reg_field_value(</div><div class='add'>+		value,</div><div class='add'>+		current_status ? 0 : 1,</div><div class='add'>+		DC_HPD1_INT_CONTROL,</div><div class='add'>+		DC_HPD1_INT_POLARITY);</div><div class='add'>+</div><div class='add'>+	dm_write_reg(irq_service-&gt;ctx, info-&gt;enable_reg, value);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.h b/drivers/gpu/drm/amd/display/dc/irq/irq_service.h<br/>index b178f85944cd..bbcef3d2fe33 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/irq_service.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq/irq_service.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq/irq_service.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq/irq_service.h</a></div><div class='hunk'>@@ -82,4 +82,12 @@ void dal_irq_service_set_generic(</div><div class='ctx'> 	const struct irq_source_info *info,</div><div class='ctx'> 	bool enable);</div><div class='ctx'> </div><div class='add'>+bool hpd0_ack(</div><div class='add'>+	struct irq_service *irq_service,</div><div class='add'>+	const struct irq_source_info *info);</div><div class='add'>+</div><div class='add'>+bool hpd1_ack(</div><div class='add'>+	struct irq_service *irq_service,</div><div class='add'>+	const struct irq_source_info *info);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h<br/>index 93354bff456a..a2f7b933bebf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/irq_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/irq_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/irq_types.h</a></div><div class='hunk'>@@ -153,6 +153,28 @@ enum dc_irq_source {</div><div class='ctx'> 	DC_IRQ_SOURCE_DMCUB_OUTBOX,</div><div class='ctx'> 	DC_IRQ_SOURCE_DMCUB_OUTBOX0,</div><div class='ctx'> 	DC_IRQ_SOURCE_DMCUB_GENERAL_DATAOUT,</div><div class='add'>+</div><div class='add'>+	DC_IRQ_SOURCE_DPCX_TX_PHYA,</div><div class='add'>+	DC_IRQ_SOURCE_DPCX_TX_PHYB,</div><div class='add'>+	DC_IRQ_SOURCE_DPCX_TX_PHYC,</div><div class='add'>+	DC_IRQ_SOURCE_DPCX_TX_PHYD,</div><div class='add'>+	DC_IRQ_SOURCE_DPCX_TX_PHYE,</div><div class='add'>+	DC_IRQ_SOURCE_DPCX_TX_PHYF,</div><div class='add'>+</div><div class='add'>+	DC_IRQ_SOURCE_DC1_VLINE2,</div><div class='add'>+	DC_IRQ_SOURCE_DC2_VLINE2,</div><div class='add'>+	DC_IRQ_SOURCE_DC3_VLINE2,</div><div class='add'>+	DC_IRQ_SOURCE_DC4_VLINE2,</div><div class='add'>+	DC_IRQ_SOURCE_DC5_VLINE2,</div><div class='add'>+	DC_IRQ_SOURCE_DC6_VLINE2,</div><div class='add'>+</div><div class='add'>+	DC_IRQ_SOURCE_DCI2C_RR_DDC1,</div><div class='add'>+	DC_IRQ_SOURCE_DCI2C_RR_DDC2,</div><div class='add'>+	DC_IRQ_SOURCE_DCI2C_RR_DDC3,</div><div class='add'>+	DC_IRQ_SOURCE_DCI2C_RR_DDC4,</div><div class='add'>+	DC_IRQ_SOURCE_DCI2C_RR_DDC5,</div><div class='add'>+	DC_IRQ_SOURCE_DCI2C_RR_DDC6,</div><div class='add'>+</div><div class='ctx'> 	DAL_IRQ_SOURCES_NUMBER</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -162,6 +184,9 @@ enum irq_type</div><div class='ctx'> 	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,</div><div class='ctx'> 	IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,</div><div class='ctx'> 	IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0,</div><div class='add'>+	IRQ_TYPE_VLINE1 = DC_IRQ_SOURCE_DC1_VLINE1,</div><div class='add'>+	IRQ_TYPE_VLINE2 = DC_IRQ_SOURCE_DC1_VLINE2,</div><div class='add'>+	IRQ_TYPE_DCUNDERFLOW = DC_IRQ_SOURCE_DC1UNDERFLOW,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define DAL_VALID_IRQ_SRC_NUM(src) \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c<br/>index 22b24749c9d2..1045c268672e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "dce/dmub_hw_lock_mgr.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='hunk'>@@ -67,8 +68,20 @@ static void dp_retrain_link_dp_test(struct dc_link *link,</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *pipes[MAX_PIPES];</div><div class='ctx'> 	struct dc_state *state = link-&gt;dc-&gt;current_state;</div><div class='add'>+	struct dc_stream_update stream_update = { 0 };</div><div class='add'>+	bool dpms_off = false;</div><div class='add'>+	bool needs_divider_update = false;</div><div class='add'>+	bool was_hpo_acquired = resource_is_hpo_acquired(link-&gt;dc-&gt;current_state);</div><div class='add'>+	bool is_hpo_acquired;</div><div class='ctx'> 	uint8_t count;</div><div class='ctx'> 	int i;</div><div class='add'>+	struct audio_output audio_output[MAX_PIPES];</div><div class='add'>+	struct dc_stream_state *streams_on_link[MAX_PIPES];</div><div class='add'>+	int num_streams_on_link = 0;</div><div class='add'>+	struct dc *dc = (struct dc *)link-&gt;dc;</div><div class='add'>+</div><div class='add'>+	needs_divider_update = (link-&gt;dc-&gt;link_srv-&gt;dp_get_encoding_format(link_setting) !=</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;dp_get_encoding_format((const struct dc_link_settings *) &amp;link-&gt;cur_link_settings));</div><div class='ctx'> </div><div class='ctx'> 	udelay(100);</div><div class='ctx'> </div><div class='hunk'>@@ -81,10 +94,66 @@ static void dp_retrain_link_dp_test(struct dc_link *link,</div><div class='ctx'> 				link-&gt;dc,</div><div class='ctx'> 				state,</div><div class='ctx'> 				pipes[i]);</div><div class='add'>+</div><div class='add'>+		// Disable OTG and re-enable after updating clocks</div><div class='add'>+		pipes[i]-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipes[i]-&gt;stream_res.tg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (needs_divider_update &amp;&amp; link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;update_dc_state_for_encoder_switch) {</div><div class='add'>+		link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;update_dc_state_for_encoder_switch(link,</div><div class='add'>+				link_setting, count,</div><div class='add'>+				*pipes, &amp;audio_output[0]);</div><div class='add'>+		for (i = 0; i &lt; count; i++) {</div><div class='add'>+			pipes[i]-&gt;clock_source-&gt;funcs-&gt;program_pix_clk(</div><div class='add'>+					pipes[i]-&gt;clock_source,</div><div class='add'>+					&amp;pipes[i]-&gt;stream_res.pix_clk_params,</div><div class='add'>+					link-&gt;dc-&gt;link_srv-&gt;dp_get_encoding_format(&amp;pipes[i]-&gt;link_config.dp_link_settings),</div><div class='add'>+					&amp;pipes[i]-&gt;pll_settings);</div><div class='add'>+</div><div class='add'>+			if (pipes[i]-&gt;stream_res.audio != NULL) {</div><div class='add'>+				const struct link_hwss *link_hwss = get_link_hwss(</div><div class='add'>+					link, &amp;pipes[i]-&gt;link_res);</div><div class='add'>+</div><div class='add'>+				link_hwss-&gt;setup_audio_output(pipes[i], &amp;audio_output[i],</div><div class='add'>+						pipes[i]-&gt;stream_res.audio-&gt;inst);</div><div class='add'>+</div><div class='add'>+				pipes[i]-&gt;stream_res.audio-&gt;funcs-&gt;az_configure(</div><div class='add'>+						pipes[i]-&gt;stream_res.audio,</div><div class='add'>+						pipes[i]-&gt;stream-&gt;signal,</div><div class='add'>+						&amp;audio_output[i].crtc_info,</div><div class='add'>+						&amp;pipes[i]-&gt;stream-&gt;audio_info,</div><div class='add'>+						&amp;audio_output[i].dp_link_info);</div><div class='add'>+</div><div class='add'>+				if (link-&gt;dc-&gt;config.disable_hbr_audio_dp2 &amp;&amp;</div><div class='add'>+						pipes[i]-&gt;stream_res.audio-&gt;funcs-&gt;az_disable_hbr_audio &amp;&amp;</div><div class='add'>+						link-&gt;dc-&gt;link_srv-&gt;dp_is_128b_132b_signal(pipes[i]))</div><div class='add'>+					pipes[i]-&gt;stream_res.audio-&gt;funcs-&gt;az_disable_hbr_audio(pipes[i]-&gt;stream_res.audio);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = count-1; i &gt;= 0; i--)</div><div class='del'>-		link_set_dpms_on(state, pipes[i]);</div><div class='add'>+	// Toggle on HPO I/O if necessary</div><div class='add'>+	is_hpo_acquired = resource_is_hpo_acquired(state);</div><div class='add'>+	if (was_hpo_acquired != is_hpo_acquired &amp;&amp; link-&gt;dc-&gt;hwss.setup_hpo_hw_control)</div><div class='add'>+		link-&gt;dc-&gt;hwss.setup_hpo_hw_control(link-&gt;dc-&gt;hwseq, is_hpo_acquired);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		pipes[i]-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipes[i]-&gt;stream_res.tg);</div><div class='add'>+</div><div class='add'>+	// Set DPMS on with stream update</div><div class='add'>+	// Cache all streams on current link since dc_update_planes_and_stream might kill current_state</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (state-&gt;streams[i] &amp;&amp; state-&gt;streams[i]-&gt;link &amp;&amp; state-&gt;streams[i]-&gt;link == link)</div><div class='add'>+			streams_on_link[num_streams_on_link++] = state-&gt;streams[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_streams_on_link; i++) {</div><div class='add'>+		if (streams_on_link[i] &amp;&amp; streams_on_link[i]-&gt;link &amp;&amp; streams_on_link[i]-&gt;link == link) {</div><div class='add'>+			stream_update.stream = streams_on_link[i];</div><div class='add'>+			stream_update.dpms_off = &amp;dpms_off;</div><div class='add'>+			dc_update_planes_and_stream(dc, NULL, 0, streams_on_link[i], &amp;stream_update);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dp_test_send_link_training(struct dc_link *link)</div><div class='hunk'>@@ -243,7 +312,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	link_training_settings.lttpr_mode = dp_decide_lttpr_mode(link, &amp;link-&gt;cur_link_settings);</div><div class='ctx'> </div><div class='del'>-	if ((link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='add'>+	if (((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='ctx'> 			link_training_settings.lttpr_mode == LTTPR_MODE_TRANSPARENT)</div><div class='ctx'> 		dp_fixed_vs_pe_read_lane_adjust(</div><div class='ctx'> 				link,</div><div class='hunk'>@@ -638,7 +707,7 @@ bool dp_set_test_pattern(</div><div class='ctx'> 	if (IS_DP_PHY_PATTERN(test_pattern)) {</div><div class='ctx'> 		/* Set DPCD Lane Settings before running test pattern */</div><div class='ctx'> 		if (p_link_settings != NULL) {</div><div class='del'>-			if ((link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='add'>+			if (((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='ctx'> 					p_link_settings-&gt;lttpr_mode == LTTPR_MODE_TRANSPARENT) {</div><div class='ctx'> 				dp_fixed_vs_pe_set_retimer_lane_settings(</div><div class='ctx'> 						link,</div><div class='hunk'>@@ -804,8 +873,11 @@ bool dp_set_test_pattern(</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (!pipe_ctx-&gt;stream)</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;lock_doublebuffer_enable) {</div><div class='del'>-			if (pipe_ctx-&gt;stream &amp;&amp; should_use_dmub_lock(pipe_ctx-&gt;stream-&gt;link)) {</div><div class='add'>+			if (should_use_dmub_inbox1_lock(pipe_ctx-&gt;stream-&gt;link-&gt;dc, pipe_ctx-&gt;stream-&gt;link)) {</div><div class='ctx'> 				union dmub_hw_lock_flags hw_locks = { 0 };</div><div class='ctx'> 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -853,7 +925,7 @@ bool dp_set_test_pattern(</div><div class='ctx'> 				CRTC_STATE_VACTIVE);</div><div class='ctx'> </div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;lock_doublebuffer_disable) {</div><div class='del'>-			if (pipe_ctx-&gt;stream &amp;&amp; should_use_dmub_lock(pipe_ctx-&gt;stream-&gt;link)) {</div><div class='add'>+			if (should_use_dmub_inbox1_lock(pipe_ctx-&gt;stream-&gt;link-&gt;dc, pipe_ctx-&gt;stream-&gt;link)) {</div><div class='ctx'> 				union dmub_hw_lock_flags hw_locks = { 0 };</div><div class='ctx'> 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -884,7 +956,7 @@ void dp_set_preferred_link_settings(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='del'>-	struct dc_stream_state *link_stream;</div><div class='add'>+	struct dc_stream_state *link_stream = 0;</div><div class='ctx'> 	struct dc_link_settings store_settings = *link_setting;</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;preferred_link_setting = store_settings;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h<br/>index eae23ea7f6ec..033650cdb811 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #ifndef __LINK_DP_CTS_H__</div><div class='ctx'> #define __LINK_DP_CTS_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> void dp_handle_automated_test(struct dc_link *link);</div><div class='ctx'> bool dp_set_test_pattern(</div><div class='ctx'> 		struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c<br/>index fbcd8fb58ea8..c8c55f196f8d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.c</a></div><div class='hunk'>@@ -24,7 +24,6 @@</div><div class='ctx'>  */</div><div class='ctx'> #include "link_dp_trace.h"</div><div class='ctx'> #include "link/protocols/link_dpcd.h"</div><div class='del'>-#include "link.h"</div><div class='ctx'> </div><div class='ctx'> void dp_trace_init(struct dc_link *link)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h<br/>index ab437a0c9101..9ff4a6c46a2b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #ifndef __LINK_DP_TRACE_H__</div><div class='ctx'> #define __LINK_DP_TRACE_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> void dp_trace_init(struct dc_link *link);</div><div class='ctx'> void dp_trace_reset(struct dc_link *link);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c<br/>index 1328a0ade342..befa67b2b2ae 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c</a></div><div class='hunk'>@@ -26,6 +26,16 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * DOC: overview</div><div class='add'>+ *</div><div class='add'>+ * Display Input Output (DIO), is the display input and output unit in DCN. It</div><div class='add'>+ * includes output encoders to support different display output, like</div><div class='add'>+ * DisplayPort, HDMI, DVI interface, and others. It also includes the control</div><div class='add'>+ * and status channels for these interfaces.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct fixed31_32 throttled_vcp_size)</div><div class='ctx'> {</div><div class='hunk'>@@ -38,33 +48,64 @@ void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> </div><div class='ctx'> void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='ctx'> </div><div class='del'>-	link_enc-&gt;funcs-&gt;connect_dig_be_to_fe(link_enc,</div><div class='del'>-			pipe_ctx-&gt;stream_res.stream_enc-&gt;id, true);</div><div class='add'>+	if (!pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		link_enc-&gt;funcs-&gt;connect_dig_be_to_fe(link_enc,</div><div class='add'>+				pipe_ctx-&gt;stream_res.stream_enc-&gt;id, true);</div><div class='ctx'> 	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 		pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(pipe_ctx-&gt;stream-&gt;link,</div><div class='ctx'> 				DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE);</div><div class='add'>+	if (stream_enc-&gt;funcs-&gt;enable_stream)</div><div class='add'>+		stream_enc-&gt;funcs-&gt;enable_stream(stream_enc,</div><div class='add'>+				pipe_ctx-&gt;stream-&gt;signal, true);</div><div class='ctx'> 	if (stream_enc-&gt;funcs-&gt;map_stream_to_link)</div><div class='ctx'> 		stream_enc-&gt;funcs-&gt;map_stream_to_link(stream_enc,</div><div class='ctx'> 				stream_enc-&gt;stream_enc_inst, link_enc-&gt;transmitter - TRANSMITTER_UNIPHY_A);</div><div class='add'>+	if (stream_enc-&gt;funcs-&gt;set_input_mode)</div><div class='add'>+		stream_enc-&gt;funcs-&gt;set_input_mode(stream_enc,</div><div class='add'>+				pipe_ctx-&gt;stream_res.pix_clk_params.dio_se_pix_per_cycle);</div><div class='ctx'> 	if (stream_enc-&gt;funcs-&gt;enable_fifo)</div><div class='ctx'> 		stream_enc-&gt;funcs-&gt;enable_fifo(stream_enc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='ctx'> </div><div class='del'>-	if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;disable_fifo)</div><div class='add'>+	if (!pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!stream_enc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (stream_enc-&gt;funcs-&gt;disable_fifo)</div><div class='ctx'> 		stream_enc-&gt;funcs-&gt;disable_fifo(stream_enc);</div><div class='add'>+	if (stream_enc-&gt;funcs-&gt;set_input_mode)</div><div class='add'>+		stream_enc-&gt;funcs-&gt;set_input_mode(stream_enc, 0);</div><div class='add'>+	if (stream_enc-&gt;funcs-&gt;enable_stream)</div><div class='add'>+		stream_enc-&gt;funcs-&gt;enable_stream(stream_enc,</div><div class='add'>+				pipe_ctx-&gt;stream-&gt;signal, false);</div><div class='add'>+</div><div class='add'>+	if (!dc_is_rgb_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		link_enc-&gt;funcs-&gt;connect_dig_be_to_fe(</div><div class='add'>+				link_enc,</div><div class='add'>+				pipe_ctx-&gt;stream_res.stream_enc-&gt;id,</div><div class='add'>+				false);</div><div class='ctx'> </div><div class='del'>-	link_enc-&gt;funcs-&gt;connect_dig_be_to_fe(</div><div class='del'>-			link_enc,</div><div class='del'>-			pipe_ctx-&gt;stream_res.stream_enc-&gt;id,</div><div class='del'>-			false);</div><div class='ctx'> 	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 		pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(</div><div class='ctx'> 				pipe_ctx-&gt;stream-&gt;link,</div><div class='hunk'>@@ -78,7 +119,8 @@ void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='ctx'> </div><div class='del'>-	if (!dc_is_virtual_signal(stream-&gt;signal))</div><div class='add'>+	if (!dc_is_virtual_signal(stream-&gt;signal) &amp;&amp;</div><div class='add'>+		!dc_is_rgb_signal(stream-&gt;signal))</div><div class='ctx'> 		stream_encoder-&gt;funcs-&gt;setup_stereo_sync(</div><div class='ctx'> 				stream_encoder,</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg-&gt;inst,</div><div class='hunk'>@@ -101,8 +143,7 @@ void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		stream_encoder-&gt;funcs-&gt;dvi_set_stream_attribute(</div><div class='ctx'> 				stream_encoder,</div><div class='ctx'> 				&amp;stream-&gt;timing,</div><div class='del'>-				(stream-&gt;signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?</div><div class='del'>-						true : false);</div><div class='add'>+				stream-&gt;signal == SIGNAL_TYPE_DVI_DUAL_LINK);</div><div class='ctx'> 	else if (dc_is_lvds_signal(stream-&gt;signal))</div><div class='ctx'> 		stream_encoder-&gt;funcs-&gt;lvds_set_stream_attribute(</div><div class='ctx'> 				stream_encoder,</div><div class='hunk'>@@ -119,7 +160,14 @@ void enable_dio_dp_link_output(struct dc_link *link,</div><div class='ctx'> 		enum clock_source_id clock_source,</div><div class='ctx'> 		const struct dc_link_settings *link_settings)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc_is_dp_sst_signal(signal))</div><div class='ctx'> 		link_enc-&gt;funcs-&gt;enable_dp_output(</div><div class='hunk'>@@ -139,7 +187,14 @@ void disable_dio_link_output(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		enum signal_type signal)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	link_enc-&gt;funcs-&gt;disable_output(link_enc, signal);</div><div class='ctx'> 	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link,</div><div class='hunk'>@@ -150,7 +205,14 @@ void set_dio_dp_link_test_pattern(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		struct encoder_set_dp_phy_pattern_param *tp_params)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	link_enc-&gt;funcs-&gt;dp_set_phy_pattern(link_enc, tp_params);</div><div class='ctx'> 	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);</div><div class='hunk'>@@ -161,7 +223,14 @@ void set_dio_dp_lane_settings(struct dc_link *link,</div><div class='ctx'> 		const struct dc_link_settings *link_settings,</div><div class='ctx'> 		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	link_enc-&gt;funcs-&gt;dp_set_lane_settings(link_enc, link_settings, lane_settings);</div><div class='ctx'> }</div><div class='hunk'>@@ -170,9 +239,15 @@ void update_dio_stream_allocation_table(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		const struct link_mst_stream_allocation_table *table)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link_enc) {</div><div class='add'>+		ASSERT(link_enc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	ASSERT(link_enc);</div><div class='ctx'> 	link_enc-&gt;funcs-&gt;update_mst_stream_allocation_table(link_enc, table);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -244,12 +319,34 @@ static const struct link_hwss dio_link_hwss = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * can_use_dio_link_hwss - Check if the link_hwss is accessible</div><div class='add'>+ *</div><div class='add'>+ * @link: Reference a link struct containing one or more sinks and the</div><div class='add'>+ *	  connective status.</div><div class='add'>+ * @link_res: Mappable hardware resource used to enable a link.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * Return true if the link encoder is accessible from link.</div><div class='add'>+ */</div><div class='ctx'> bool can_use_dio_link_hwss(const struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res)</div><div class='ctx'> {</div><div class='del'>-	return link-&gt;link_enc != NULL;</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		return link-&gt;link_enc != NULL;</div><div class='add'>+	else</div><div class='add'>+		return link_res-&gt;dio_link_enc != NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * get_dio_link_hwss - Return link_hwss reference</div><div class='add'>+ *</div><div class='add'>+ * This function behaves like a get function to return the link_hwss populated</div><div class='add'>+ * in the link_hwss_dio.c file.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * Return the reference to the filled struct of link_hwss.</div><div class='add'>+ */</div><div class='ctx'> const struct link_hwss *get_dio_link_hwss(void)</div><div class='ctx'> {</div><div class='ctx'> 	return &amp;dio_link_hwss;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h<br/>index a1f72fe378ee..4a25210a344f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h</a></div><div class='hunk'>@@ -23,20 +23,11 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * DOC: overview</div><div class='del'>- *</div><div class='del'>- * Display Input Output (DIO), is the display input and output unit in DCN. It</div><div class='del'>- * includes output encoders to support different display output, like</div><div class='del'>- * DisplayPort, HDMI, DVI interface, and others. It also includes the control</div><div class='del'>- * and status channels for these interfaces.</div><div class='del'>- */</div><div class='del'>-</div><div class='ctx'> #ifndef __LINK_HWSS_DIO_H__</div><div class='ctx'> #define __LINK_HWSS_DIO_H__</div><div class='ctx'> </div><div class='ctx'> #include "link_hwss.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> const struct link_hwss *get_dio_link_hwss(void);</div><div class='ctx'> bool can_use_dio_link_hwss(const struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c<br/>index 348ea4cb832d..e1dff4e3f446 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c</a></div><div class='hunk'>@@ -127,7 +127,10 @@ static void set_dio_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		struct encoder_set_dp_phy_pattern_param *tp_params)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> </div><div class='ctx'> 	if (!set_dio_fixed_vs_pe_retimer_dp_link_test_pattern_override(</div><div class='ctx'> 			link, link_res, tp_params, get_dio_link_hwss())) {</div><div class='hunk'>@@ -187,7 +190,7 @@ static const struct link_hwss dio_fixed_vs_pe_retimer_link_hwss = {</div><div class='ctx'> </div><div class='ctx'> bool requires_fixed_vs_pe_retimer_dio_link_hwss(const struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	return (link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN);</div><div class='add'>+	return ((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct link_hwss *get_dio_fixed_vs_pe_retimer_link_hwss(void)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h<br/>index 9ac08a332540..cf578a8662a4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> #ifndef __LINK_HWSS_DIO_FIXED_VS_PE_RETIMER_H__</div><div class='ctx'> #define __LINK_HWSS_DIO_FIXED_VS_PE_RETIMER_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> uint32_t dp_dio_fixed_vs_pe_retimer_get_lttpr_write_address(struct dc_link *link);</div><div class='ctx'> uint8_t dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(struct dc_link *link);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c<br/>index 46fb3649bc86..81bf3c5e1fdf 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c</a></div><div class='hunk'>@@ -35,12 +35,15 @@ static void update_dpia_stream_allocation_table(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		const struct link_mst_stream_allocation_table *table)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='ctx'> 	static enum dc_status status;</div><div class='ctx'> 	uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; table-&gt;stream_count; i++)</div><div class='ctx'> 		mst_alloc_slots += table-&gt;stream_allocations[i].slot_count;</div><div class='ctx'> </div><div class='hunk'>@@ -50,23 +53,110 @@ static void update_dpia_stream_allocation_table(struct dc_link *link,</div><div class='ctx'> 	DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",</div><div class='ctx'> 			status, mst_alloc_slots, prev_mst_slots_in_use);</div><div class='ctx'> </div><div class='del'>-	ASSERT(link_enc);</div><div class='del'>-	link_enc-&gt;funcs-&gt;update_mst_stream_allocation_table(link_enc, table);</div><div class='add'>+	if (link_enc)</div><div class='add'>+		link_enc-&gt;funcs-&gt;update_mst_stream_allocation_table(link_enc, table);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_dio_dpia_link_test_pattern(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='add'>+		struct encoder_set_dp_phy_pattern_param *tp_params)</div><div class='add'>+{</div><div class='add'>+	if (tp_params-&gt;dp_phy_pattern != DP_TEST_PATTERN_VIDEO_MODE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='add'>+	if (!link_enc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	link_enc-&gt;funcs-&gt;dp_set_phy_pattern(link_enc, tp_params);</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_dio_dpia_lane_settings(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='add'>+		const struct dc_link_settings *link_settings,</div><div class='add'>+		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void enable_dpia_link_output(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='add'>+		enum signal_type signal,</div><div class='add'>+		enum clock_source_id clock_source,</div><div class='add'>+		const struct dc_link_settings *link_settings)</div><div class='add'>+{</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='add'>+	if (link_enc != NULL) {</div><div class='add'>+		if (link-&gt;dc-&gt;config.enable_dpia_pre_training || link-&gt;dc-&gt;config.unify_link_enc_assignment) {</div><div class='add'>+			uint8_t fec_rdy = link-&gt;dc-&gt;link_srv-&gt;dp_should_enable_fec(link);</div><div class='add'>+			uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;</div><div class='add'>+</div><div class='add'>+			if (link_enc-&gt;funcs-&gt;enable_dpia_output)</div><div class='add'>+				link_enc-&gt;funcs-&gt;enable_dpia_output(</div><div class='add'>+						link_enc,</div><div class='add'>+						link_settings,</div><div class='add'>+						link-&gt;ddc_hw_inst,</div><div class='add'>+						digmode,</div><div class='add'>+						fec_rdy);</div><div class='add'>+			else</div><div class='add'>+				DC_LOG_ERROR("%s: link encoder does not support enable_dpia_output\n", __func__);</div><div class='add'>+		} else</div><div class='add'>+			enable_dio_dp_link_output(link, link_res, signal, clock_source, link_settings);</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link,</div><div class='add'>+			DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void disable_dpia_link_output(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='add'>+		enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='add'>+	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='add'>+	if (link_enc != NULL) {</div><div class='add'>+		if (link-&gt;dc-&gt;config.enable_dpia_pre_training || link-&gt;dc-&gt;config.unify_link_enc_assignment) {</div><div class='add'>+			uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;</div><div class='add'>+</div><div class='add'>+			if (link_enc-&gt;funcs-&gt;disable_dpia_output)</div><div class='add'>+				link_enc-&gt;funcs-&gt;disable_dpia_output(link_enc, link-&gt;ddc_hw_inst, digmode);</div><div class='add'>+			else</div><div class='add'>+				DC_LOG_ERROR("%s: link encoder does not support disable_dpia_output\n", __func__);</div><div class='add'>+		} else</div><div class='add'>+			link_enc-&gt;funcs-&gt;disable_output(link_enc, signal);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link,</div><div class='add'>+			DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct link_hwss dpia_link_hwss = {</div><div class='ctx'> 	.setup_stream_encoder = setup_dio_stream_encoder,</div><div class='ctx'> 	.reset_stream_encoder = reset_dio_stream_encoder,</div><div class='ctx'> 	.setup_stream_attribute = setup_dio_stream_attribute,</div><div class='del'>-	.disable_link_output = disable_dio_link_output,</div><div class='add'>+	.disable_link_output = disable_dpia_link_output,</div><div class='ctx'> 	.setup_audio_output = setup_dio_audio_output,</div><div class='ctx'> 	.enable_audio_packet = enable_dio_audio_packet,</div><div class='ctx'> 	.disable_audio_packet = disable_dio_audio_packet,</div><div class='ctx'> 	.ext = {</div><div class='ctx'> 		.set_throttled_vcp_size = set_dio_throttled_vcp_size,</div><div class='del'>-		.enable_dp_link_output = enable_dio_dp_link_output,</div><div class='del'>-		.set_dp_link_test_pattern = set_dio_dp_link_test_pattern,</div><div class='del'>-		.set_dp_lane_settings = set_dio_dp_lane_settings,</div><div class='add'>+		.enable_dp_link_output = enable_dpia_link_output,</div><div class='add'>+		.set_dp_link_test_pattern = set_dio_dpia_link_test_pattern,</div><div class='add'>+		.set_dp_lane_settings = set_dio_dpia_lane_settings,</div><div class='ctx'> 		.update_stream_allocation_table = update_dpia_stream_allocation_table,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -74,8 +164,10 @@ static const struct link_hwss dpia_link_hwss = {</div><div class='ctx'> bool can_use_dpia_link_hwss(const struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res)</div><div class='ctx'> {</div><div class='del'>-	return link-&gt;is_dig_mapping_flexible &amp;&amp;</div><div class='del'>-			link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign;</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		return link-&gt;is_dig_mapping_flexible &amp;&amp; link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign;</div><div class='add'>+	else</div><div class='add'>+		return link-&gt;is_dig_mapping_flexible &amp;&amp; link_res-&gt;dio_link_enc != NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct link_hwss *get_dpia_link_hwss(void)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h<br/>index ad16ec5d9bb7..259e0f4775e1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.h</a></div><div class='hunk'>@@ -27,6 +27,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "link_hwss.h"</div><div class='ctx'> </div><div class='add'>+#define DIG_SST_MODE    0</div><div class='add'>+#define DIG_MST_MODE    5</div><div class='add'>+</div><div class='ctx'> const struct link_hwss *get_dpia_link_hwss(void);</div><div class='ctx'> bool can_use_dpia_link_hwss(const struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c<br/>index e1257404357b..cec68c5dba13 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c</a></div><div class='hunk'>@@ -28,6 +28,8 @@</div><div class='ctx'> #include "dccg.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='ctx'> </div><div class='add'>+#define DC_LOGGER link-&gt;ctx-&gt;logger</div><div class='add'>+</div><div class='ctx'> void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct fixed31_32 throttled_vcp_size)</div><div class='ctx'> {</div><div class='hunk'>@@ -108,6 +110,11 @@ void enable_hpo_dp_link_output(struct dc_link *link,</div><div class='ctx'> 		enum clock_source_id clock_source,</div><div class='ctx'> 		const struct dc_link_settings *link_settings)</div><div class='ctx'> {</div><div class='add'>+	if (!link_res-&gt;hpo_dp_link_enc) {</div><div class='add'>+		DC_LOG_ERROR("%s: invalid hpo_dp_link_enc\n", __func__);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_symclk32_le_root_clock_gating)</div><div class='ctx'> 		link-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;set_symclk32_le_root_clock_gating(</div><div class='ctx'> 				link-&gt;dc-&gt;res_pool-&gt;dccg,</div><div class='hunk'>@@ -124,6 +131,11 @@ void disable_hpo_dp_link_output(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res,</div><div class='ctx'> 		enum signal_type signal)</div><div class='ctx'> {</div><div class='add'>+	if (!link_res-&gt;hpo_dp_link_enc) {</div><div class='add'>+		DC_LOG_ERROR("%s: invalid hpo_dp_link_enc\n", __func__);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 		link_res-&gt;hpo_dp_link_enc-&gt;funcs-&gt;link_disable(link_res-&gt;hpo_dp_link_enc);</div><div class='ctx'> 		link_res-&gt;hpo_dp_link_enc-&gt;funcs-&gt;disable_link_phy(</div><div class='ctx'> 				link_res-&gt;hpo_dp_link_enc, signal);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h<br/>index 1d3ed8ca83b5..7c9005bc2587 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #define __LINK_HWSS_HPO_DP_H__</div><div class='ctx'> </div><div class='ctx'> #include "link_hwss.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct fixed31_32 throttled_vcp_size);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c<br/>index 3e6c7be7e278..55c5148de800 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c</a></div><div class='hunk'>@@ -74,7 +74,7 @@ static void dp_hpo_fixed_vs_pe_retimer_set_tx_ffe(struct dc_link *link,</div><div class='ctx'> static void dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern(struct dc_link *link,</div><div class='ctx'> 		struct encoder_set_dp_phy_pattern_param *tp_params)</div><div class='ctx'> {</div><div class='del'>-	uint8_t clk_src = 0x4C;</div><div class='add'>+	uint8_t clk_src = 0xC4;</div><div class='ctx'> 	uint8_t pattern = 0x4F; /* SQ128 */</div><div class='ctx'> </div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_pg0[4] = {0x1, 0x11, 0x0, 0x0};</div><div class='hunk'>@@ -165,7 +165,12 @@ static void set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin</div><div class='ctx'> 		link_res-&gt;hpo_dp_link_enc-&gt;funcs-&gt;set_link_test_pattern(</div><div class='ctx'> 				link_res-&gt;hpo_dp_link_enc, tp_params);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	link-&gt;dc-&gt;link_srv-&gt;dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);</div><div class='add'>+</div><div class='add'>+	// Give retimer extra time to lock before updating DP_TRAINING_PATTERN_SET to TPS1 or phy pattern</div><div class='add'>+	if (tp_params-&gt;dp_phy_pattern != DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE)</div><div class='add'>+		msleep(50);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void set_hpo_fixed_vs_pe_retimer_dp_lane_settings(struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h<br/>index 82301187bc7c..8bf36827ecfb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> #ifndef __LINK_HWSS_HPO_FIXED_VS_PE_RETIMER_DP_H__</div><div class='ctx'> #define __LINK_HWSS_HPO_FIXED_VS_PE_RETIMER_DP_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> bool requires_fixed_vs_pe_retimer_hpo_link_hwss(const struct dc_link *link);</div><div class='ctx'> const struct link_hwss *get_hpo_fixed_vs_pe_retimer_dp_link_hwss(void);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c<br/>index b8c4a04dd175..6d31f4967f1a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_detection.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_detection.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_detection.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_detection.c</a></div><div class='hunk'>@@ -48,6 +48,9 @@</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='ctx'> </div><div class='add'>+ // Offset DPCD 050Eh == 0x5A</div><div class='add'>+#define MST_HUB_ID_0x5A  0x5A</div><div class='add'>+</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='hunk'>@@ -65,7 +68,7 @@</div><div class='ctx'> </div><div class='ctx'> static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";</div><div class='ctx'> </div><div class='del'>-static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";</div><div class='add'>+static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";</div><div class='ctx'> </div><div class='ctx'> static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)</div><div class='ctx'> {</div><div class='hunk'>@@ -267,6 +270,10 @@ static void read_scdc_caps(struct ddc_service *ddc_service,</div><div class='ctx'> 	uint8_t slave_address = HDMI_SCDC_ADDRESS;</div><div class='ctx'> 	uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;</div><div class='ctx'> </div><div class='add'>+	if (ddc_service-&gt;link-&gt;local_sink &amp;&amp;</div><div class='add'>+		!ddc_service-&gt;link-&gt;local_sink-&gt;edid_caps.scdc_present)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	link_query_ddc_data(ddc_service, slave_address, &amp;offset,</div><div class='ctx'> 			sizeof(offset), sink-&gt;scdc_caps.manufacturer_OUI.byte,</div><div class='ctx'> 			sizeof(sink-&gt;scdc_caps.manufacturer_OUI.byte));</div><div class='hunk'>@@ -516,8 +523,8 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)</div><div class='ctx'> static void read_current_link_settings_on_detect(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	union lane_count_set lane_count_set = {0};</div><div class='del'>-	uint8_t link_bw_set;</div><div class='del'>-	uint8_t link_rate_set;</div><div class='add'>+	uint8_t link_bw_set = 0;</div><div class='add'>+	uint8_t link_rate_set = 0;</div><div class='ctx'> 	uint32_t read_dpcd_retry_cnt = 10;</div><div class='ctx'> 	enum dc_status status = DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -590,8 +597,9 @@ static bool detect_dp(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	if (sink_caps-&gt;transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {</div><div class='ctx'> 		sink_caps-&gt;signal = SIGNAL_TYPE_DISPLAY_PORT;</div><div class='del'>-		if (!detect_dp_sink_caps(link))</div><div class='add'>+		if (!detect_dp_sink_caps(link)) {</div><div class='ctx'> 			return false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (is_dp_branch_device(link))</div><div class='ctx'> 			/* DP SST branch */</div><div class='hunk'>@@ -608,6 +616,7 @@ static bool detect_dp(struct dc_link *link,</div><div class='ctx'> 		link-&gt;dpcd_caps.dongle_type = sink_caps-&gt;dongle_type;</div><div class='ctx'> 		link-&gt;dpcd_caps.is_dongle_type_one = sink_caps-&gt;is_dongle_type_one;</div><div class='ctx'> 		link-&gt;dpcd_caps.dpcd_rev.raw = 0;</div><div class='add'>+		link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -651,7 +660,7 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	is_in_alt_mode = link-&gt;link_enc-&gt;funcs-&gt;is_in_alt_mode(link-&gt;link_enc);</div><div class='del'>-	DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode);</div><div class='add'>+	DC_LOG_DC("DP Alt mode state on HPD: %d  Link=%d\n", is_in_alt_mode, link-&gt;link_index);</div><div class='ctx'> </div><div class='ctx'> 	if (is_in_alt_mode)</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -692,6 +701,15 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)</div><div class='ctx'> 			link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &amp;&amp;</div><div class='ctx'> 			!link-&gt;dc-&gt;debug.dpia_debug.bits.disable_mst_dsc_work_around)</div><div class='ctx'> 		link-&gt;wa_flags.dpia_mst_dsc_always_on = true;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp;</div><div class='add'>+		link-&gt;type == dc_connection_mst_branch &amp;&amp;</div><div class='add'>+		link-&gt;dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &amp;&amp;</div><div class='add'>+		link-&gt;dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A &amp;&amp;</div><div class='add'>+		link-&gt;dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &amp;&amp;</div><div class='add'>+		!link-&gt;dc-&gt;debug.dpia_debug.bits.disable_mst_dsc_work_around) {</div><div class='add'>+			link-&gt;wa_flags.dpia_mst_dsc_always_on = true;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)</div><div class='hunk'>@@ -804,7 +822,10 @@ static bool should_verify_link_capability_destructively(struct dc_link *link,</div><div class='ctx'> {</div><div class='ctx'> 	bool destrictive = false;</div><div class='ctx'> 	struct dc_link_settings max_link_cap;</div><div class='del'>-	bool is_link_enc_unavailable = link-&gt;link_enc &amp;&amp;</div><div class='add'>+	bool is_link_enc_unavailable = false;</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		is_link_enc_unavailable = link-&gt;link_enc &amp;&amp;</div><div class='ctx'> 			link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign &amp;&amp;</div><div class='ctx'> 			!link_enc_cfg_is_link_enc_avail(</div><div class='ctx'> 					link-&gt;ctx-&gt;dc,</div><div class='hunk'>@@ -817,7 +838,8 @@ static bool should_verify_link_capability_destructively(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 		if (link-&gt;dc-&gt;debug.skip_detection_link_training ||</div><div class='ctx'> 				dc_is_embedded_signal(link-&gt;local_sink-&gt;sink_signal) ||</div><div class='del'>-				link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {</div><div class='add'>+				(link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp;</div><div class='add'>+				!link-&gt;dc-&gt;config.enable_dpia_pre_training)) {</div><div class='ctx'> 			destrictive = false;</div><div class='ctx'> 		} else if (link_dp_get_encoding_format(&amp;max_link_cap) ==</div><div class='ctx'> 				DP_8b_10b_ENCODING) {</div><div class='hunk'>@@ -840,6 +862,94 @@ static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,</div><div class='ctx'> 		verify_link_capability_non_destructive(link);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable.</div><div class='add'>+ *</div><div class='add'>+ * Evaluates an 8-byte EDID header to check if it's good enough</div><div class='add'>+ * for the purpose of determining whether a display is connected</div><div class='add'>+ * without reading the full EDID.</div><div class='add'>+ *</div><div class='add'>+ * @edid_header: The first 8 bytes of the EDID read from DDC.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the header looks valid (&gt;= 6 of 8 bytes match the</div><div class='add'>+ *         expected 00/FF pattern), false otherwise.</div><div class='add'>+ */</div><div class='add'>+static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])</div><div class='add'>+{</div><div class='add'>+	int edid_header_score = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 8; ++i)</div><div class='add'>+		edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff);</div><div class='add'>+</div><div class='add'>+	return edid_header_score &gt;= 6;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * link_detect_ddc_probe() - Probe the DDC to see if a display is connected.</div><div class='add'>+ *</div><div class='add'>+ * Detect whether a display is connected to DDC without reading full EDID.</div><div class='add'>+ * Reads only the EDID header (the first 8 bytes of EDID) from DDC and</div><div class='add'>+ * evaluates whether that matches.</div><div class='add'>+ *</div><div class='add'>+ * @link: DC link whose DDC/I2C is probed for the EDID header.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the EDID header was read and passes validation,</div><div class='add'>+ *         false otherwise.</div><div class='add'>+ */</div><div class='add'>+static bool link_detect_ddc_probe(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	if (!link-&gt;ddc)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	uint8_t edid_header[8] = {0};</div><div class='add'>+	bool ddc_probed = i2c_read(link-&gt;ddc, 0x50, edid_header, sizeof(edid_header));</div><div class='add'>+</div><div class='add'>+	if (!ddc_probed)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!link_detect_evaluate_edid_header(edid_header))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * link_detect_dac_load_detect() - Performs DAC load detection.</div><div class='add'>+ *</div><div class='add'>+ * Load detection can be used to detect the presence of an</div><div class='add'>+ * analog display when we can't read DDC. This causes a visible</div><div class='add'>+ * visual glitch so it should be used sparingly.</div><div class='add'>+ *</div><div class='add'>+ * @link: DC link to test using the DAC load-detect path.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the VBIOS load-detect call reports OK, false</div><div class='add'>+ *         otherwise.</div><div class='add'>+ */</div><div class='add'>+static bool link_detect_dac_load_detect(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	struct dc_bios *bios = link-&gt;ctx-&gt;dc_bios;</div><div class='add'>+	struct link_encoder *link_enc = link-&gt;link_enc;</div><div class='add'>+	enum engine_id engine_id = link_enc-&gt;preferred_engine;</div><div class='add'>+	enum dal_device_type device_type = DEVICE_TYPE_CRT;</div><div class='add'>+	enum bp_result bp_result;</div><div class='add'>+	uint32_t enum_id;</div><div class='add'>+</div><div class='add'>+	switch (engine_id) {</div><div class='add'>+	case ENGINE_ID_DACB:</div><div class='add'>+		enum_id = 2;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DACA:</div><div class='add'>+	default:</div><div class='add'>+		engine_id = ENGINE_ID_DACA;</div><div class='add'>+		enum_id = 1;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bp_result = bios-&gt;funcs-&gt;dac_load_detection(bios, engine_id, device_type, enum_id);</div><div class='add'>+	return bp_result == BP_RESULT_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * detect_link_and_local_sink() - Detect if a sink is attached to a given link</div><div class='ctx'>  *</div><div class='hunk'>@@ -863,7 +973,6 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 	struct dc_sink *prev_sink = NULL;</div><div class='ctx'> 	struct dpcd_caps prev_dpcd_caps;</div><div class='ctx'> 	enum dc_connection_type new_connection_type = dc_connection_none;</div><div class='del'>-	enum dc_connection_type pre_connection_type = link-&gt;type;</div><div class='ctx'> 	const uint32_t post_oui_delay = 30; // 30ms</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='hunk'>@@ -925,6 +1034,12 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		case SIGNAL_TYPE_RGB: {</div><div class='add'>+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;</div><div class='add'>+			sink_caps.signal = SIGNAL_TYPE_RGB;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		case SIGNAL_TYPE_LVDS: {</div><div class='ctx'> 			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;</div><div class='ctx'> 			sink_caps.signal = SIGNAL_TYPE_LVDS;</div><div class='hunk'>@@ -965,7 +1080,6 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			if (!detect_dp(link, &amp;sink_caps, reason)) {</div><div class='del'>-				link-&gt;type = pre_connection_type;</div><div class='ctx'> </div><div class='ctx'> 				if (prev_sink)</div><div class='ctx'> 					dc_sink_release(prev_sink);</div><div class='hunk'>@@ -993,21 +1107,11 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 					link-&gt;reported_link_cap.link_rate &gt; LINK_RATE_HIGH3)</div><div class='ctx'> 				link-&gt;reported_link_cap.link_rate = LINK_RATE_HIGH3;</div><div class='ctx'> </div><div class='del'>-			/*</div><div class='del'>-			 * If this is DP over USB4 link then we need to:</div><div class='del'>-			 * - Enable BW ALLOC support on DPtx if applicable</div><div class='del'>-			 */</div><div class='del'>-			if (dc-&gt;config.usb4_bw_alloc_support) {</div><div class='del'>-				if (link_dp_dpia_set_dptx_usb4_bw_alloc_support(link)) {</div><div class='del'>-					/* update with non reduced link cap if bw allocation mode is supported */</div><div class='del'>-					if (link-&gt;dpia_bw_alloc_config.nrd_max_link_rate &amp;&amp;</div><div class='del'>-						link-&gt;dpia_bw_alloc_config.nrd_max_lane_count) {</div><div class='del'>-						link-&gt;reported_link_cap.link_rate =</div><div class='del'>-							link-&gt;dpia_bw_alloc_config.nrd_max_link_rate;</div><div class='del'>-						link-&gt;reported_link_cap.lane_count =</div><div class='del'>-							link-&gt;dpia_bw_alloc_config.nrd_max_lane_count;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='add'>+			if (link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling</div><div class='add'>+					&amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc</div><div class='add'>+					&amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {</div><div class='add'>+				if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)</div><div class='add'>+					link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;</div><div class='ctx'> 			}</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1060,7 +1164,30 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 			DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");</div><div class='ctx'> 			break;</div><div class='ctx'> 		case EDID_NO_RESPONSE:</div><div class='add'>+			/* Analog connectors without EDID:</div><div class='add'>+			 * - old monitor that actually doesn't have EDID</div><div class='add'>+			 * - cheap DVI-A cable or adapter that doesn't connect DDC</div><div class='add'>+			 */</div><div class='add'>+			if (dc_connector_supports_analog(link-&gt;link_id.id)) {</div><div class='add'>+				/* If we didn't do DAC load detection yet, do it now</div><div class='add'>+				 * to verify there really is a display connected.</div><div class='add'>+				 */</div><div class='add'>+				if (link-&gt;type != dc_connection_dac_load &amp;&amp;</div><div class='add'>+					!link_detect_dac_load_detect(link)) {</div><div class='add'>+					if (prev_sink)</div><div class='add'>+						dc_sink_release(prev_sink);</div><div class='add'>+					link_disconnect_sink(link);</div><div class='add'>+					return false;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				DC_LOG_INFO("%s detected analog display without EDID\n", __func__);</div><div class='add'>+				link-&gt;type = dc_connection_dac_load;</div><div class='add'>+				sink-&gt;edid_caps.analog = true;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			DC_LOG_ERROR("No EDID read.\n");</div><div class='add'>+</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * Abort detection for non-DP connectors if we have</div><div class='ctx'> 			 * no EDID</div><div class='hunk'>@@ -1127,13 +1254,26 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 				sink = prev_sink;</div><div class='ctx'> 				prev_sink = NULL;</div><div class='ctx'> 			}</div><div class='del'>-			query_hdcp_capability(sink-&gt;sink_signal, link);</div><div class='add'>+</div><div class='add'>+			if (!sink-&gt;edid_caps.analog)</div><div class='add'>+				query_hdcp_capability(sink-&gt;sink_signal, link);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/* DVI-I connector connected to analog display. */</div><div class='add'>+		if ((link-&gt;link_id.id == CONNECTOR_ID_DUAL_LINK_DVII ||</div><div class='add'>+		     link-&gt;link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) &amp;&amp;</div><div class='add'>+			sink-&gt;edid_caps.analog)</div><div class='add'>+			sink-&gt;sink_signal = SIGNAL_TYPE_RGB;</div><div class='add'>+</div><div class='ctx'> 		/* HDMI-DVI Dongle */</div><div class='ctx'> 		if (sink-&gt;sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &amp;&amp;</div><div class='ctx'> 		    !sink-&gt;edid_caps.edid_hdmi)</div><div class='ctx'> 			sink-&gt;sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;</div><div class='add'>+		else if (dc_is_dvi_signal(sink-&gt;sink_signal) &amp;&amp;</div><div class='add'>+			 dc_is_dvi_signal(link-&gt;connector_signal) &amp;&amp;</div><div class='add'>+			 aud_support-&gt;hdmi_audio_native &amp;&amp;</div><div class='add'>+			 sink-&gt;edid_caps.edid_hdmi)</div><div class='add'>+			sink-&gt;sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='ctx'> </div><div class='ctx'> 		if (link-&gt;local_sink &amp;&amp; dc_is_dp_signal(sink_caps.signal))</div><div class='ctx'> 			dp_trace_init(link);</div><div class='hunk'>@@ -1191,8 +1331,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 			//sink only can use supported link rate table, we are foreced to enable it</div><div class='ctx'> 			if (link-&gt;reported_link_cap.link_rate == LINK_RATE_UNKNOWN)</div><div class='ctx'> 				link-&gt;panel_config.ilr.optimize_edp_link_rate = true;</div><div class='del'>-			if (edp_is_ilr_optimization_enabled(link))</div><div class='del'>-				link-&gt;reported_link_cap.link_rate = get_max_link_rate_from_ilr_table(link);</div><div class='add'>+			link-&gt;reported_link_cap.link_rate = get_max_edp_link_rate(link);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1223,6 +1362,36 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * link_detect_analog() - Determines if an analog sink is connected.</div><div class='add'>+ *</div><div class='add'>+ * @link: DC link to evaluate (must support analog signalling).</div><div class='add'>+ * @type: Updated with the detected connection type:</div><div class='add'>+ *        dc_connection_single (analog via DDC),</div><div class='add'>+ *        dc_connection_dac_load (via load-detect),</div><div class='add'>+ *        or dc_connection_none.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if detection completed.</div><div class='add'>+ */</div><div class='add'>+static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *type)</div><div class='add'>+{</div><div class='add'>+	/* Don't care about connectors that don't support an analog signal. */</div><div class='add'>+	ASSERT(dc_connector_supports_analog(link-&gt;link_id.id));</div><div class='add'>+</div><div class='add'>+	if (link_detect_ddc_probe(link)) {</div><div class='add'>+		*type = dc_connection_single;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (link_detect_dac_load_detect(link)) {</div><div class='add'>+		*type = dc_connection_dac_load;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*type = dc_connection_none;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * link_detect_connection_type() - Determine if there is a sink connected</div><div class='ctx'>  *</div><div class='hunk'>@@ -1239,6 +1408,17 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Ignore the HPD pin (if any) for analog connectors.</div><div class='add'>+	 * Instead rely on DDC and DAC.</div><div class='add'>+	 *</div><div class='add'>+	 * - VGA connectors don't have any HPD at all.</div><div class='add'>+	 * - Some DVI-A cables don't connect the HPD pin.</div><div class='add'>+	 * - Some DVI-A cables pull up the HPD pin.</div><div class='add'>+	 *   (So it's high even when no display is connected.)</div><div class='add'>+	 */</div><div class='add'>+	if (dc_connector_supports_analog(link-&gt;link_id.id))</div><div class='add'>+		return link_detect_analog(link, type);</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;connector_signal == SIGNAL_TYPE_EDP) {</div><div class='ctx'> 		/*in case it is not on*/</div><div class='ctx'> 		if (!link-&gt;dc-&gt;config.edp_no_power_sequencing)</div><div class='hunk'>@@ -1299,8 +1479,7 @@ bool link_detect(struct dc_link *link, enum dc_detect_reason reason)</div><div class='ctx'> 			link-&gt;dpcd_caps.is_mst_capable)</div><div class='ctx'> 		is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);</div><div class='ctx'> </div><div class='del'>-	if (is_local_sink_detect_success &amp;&amp;</div><div class='del'>-			pre_link_type == dc_connection_mst_branch &amp;&amp;</div><div class='add'>+	if (pre_link_type == dc_connection_mst_branch &amp;&amp;</div><div class='ctx'> 			link-&gt;type != dc_connection_mst_branch)</div><div class='ctx'> 		is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.h b/drivers/gpu/drm/amd/display/dc/link/link_detection.h<br/>index 7da05078721e..1ab29476060b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_detection.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_detection.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_detection.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_detection.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> #ifndef __DC_LINK_DETECTION_H__</div><div class='ctx'> #define __DC_LINK_DETECTION_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> bool link_detect(struct dc_link *link, enum dc_detect_reason reason);</div><div class='ctx'> bool link_detect_connection_type(struct dc_link *link,</div><div class='ctx'> 		enum dc_connection_type *type);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c<br/>index a72de44a5747..6ae134147617 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_dpms.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_dpms.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_dpms.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_dpms.c</a></div><div class='hunk'>@@ -55,6 +55,8 @@</div><div class='ctx'> #include "dccg.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='ctx'> #include "atomfirmware.h"</div><div class='add'>+#include "vpg.h"</div><div class='add'>+</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dc_logger</div><div class='ctx'> #define DC_LOGGER_INIT(logger) \</div><div class='hunk'>@@ -67,7 +69,6 @@</div><div class='ctx'> #define RETIMER_REDRIVER_INFO(...) \</div><div class='ctx'> 	DC_LOG_RETIMER_REDRIVER(  \</div><div class='ctx'> 		__VA_ARGS__)</div><div class='del'>-#include "dc/dcn30/dcn30_vpg.h"</div><div class='ctx'> </div><div class='ctx'> #define MAX_MTP_SLOT_COUNT 64</div><div class='ctx'> #define LINK_TRAINING_ATTEMPTS 4</div><div class='hunk'>@@ -127,7 +128,7 @@ void link_blank_dp_stream(struct dc_link *link, bool hw_init)</div><div class='ctx'> 		if (link-&gt;ep_type == DISPLAY_ENDPOINT_PHY &amp;&amp;</div><div class='ctx'> 			link-&gt;link_enc-&gt;funcs-&gt;get_dig_frontend &amp;&amp;</div><div class='ctx'> 			link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc)) {</div><div class='del'>-			unsigned int fe = link-&gt;link_enc-&gt;funcs-&gt;get_dig_frontend(link-&gt;link_enc);</div><div class='add'>+			int fe = link-&gt;link_enc-&gt;funcs-&gt;get_dig_frontend(link-&gt;link_enc);</div><div class='ctx'> </div><div class='ctx'> 			if (fe != ENGINE_ID_UNKNOWN)</div><div class='ctx'> 				for (j = 0; j &lt; dc-&gt;res_pool-&gt;stream_enc_count; j++) {</div><div class='hunk'>@@ -139,7 +140,8 @@ void link_blank_dp_stream(struct dc_link *link, bool hw_init)</div><div class='ctx'> 				}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if ((!link-&gt;wa_flags.dp_keep_receiver_powered) || hw_init)</div><div class='add'>+		if (((!dc-&gt;is_switch_in_progress_dest) &amp;&amp; ((!link-&gt;wa_flags.dp_keep_receiver_powered) || hw_init)) &amp;&amp;</div><div class='add'>+			(link-&gt;type != dc_connection_none))</div><div class='ctx'> 			dpcd_write_rx_power_ctrl(link, false);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -147,6 +149,7 @@ void link_blank_dp_stream(struct dc_link *link, bool hw_init)</div><div class='ctx'> void link_set_all_streams_dpms_off_for_link(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *pipes[MAX_PIPES];</div><div class='add'>+	struct dc_stream_state *streams[MAX_PIPES];</div><div class='ctx'> 	struct dc_state *state = link-&gt;dc-&gt;current_state;</div><div class='ctx'> 	uint8_t count;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -159,10 +162,18 @@ void link_set_all_streams_dpms_off_for_link(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	link_get_master_pipes_with_dpms_on(link, state, &amp;count, pipes);</div><div class='ctx'> </div><div class='add'>+	/* The subsequent call to dc_commit_updates_for_stream for a full update</div><div class='add'>+	 * will release the current state and swap to a new state. Releasing the</div><div class='add'>+	 * current state results in the stream pointers in the pipe_ctx structs</div><div class='add'>+	 * to be zero'd. Hence, cache all streams prior to dc_commit_updates_for_stream.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		streams[i] = pipes[i]-&gt;stream;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='del'>-		stream_update.stream = pipes[i]-&gt;stream;</div><div class='add'>+		stream_update.stream = streams[i];</div><div class='ctx'> 		dc_commit_updates_for_stream(link-&gt;ctx-&gt;dc, NULL, 0,</div><div class='del'>-				pipes[i]-&gt;stream, &amp;stream_update,</div><div class='add'>+				streams[i], &amp;stream_update,</div><div class='ctx'> 				state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -651,15 +662,15 @@ static void write_i2c_redriver_setting(</div><div class='ctx'> static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)</div><div class='ctx'> {</div><div class='ctx'> 	struct cp_psp *cp_psp = &amp;pipe_ctx-&gt;stream-&gt;ctx-&gt;cp_psp;</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	struct cp_psp_stream_config config = {0};</div><div class='ctx'> 	enum dp_panel_mode panel_mode =</div><div class='ctx'> 			dp_get_panel_mode(pipe_ctx-&gt;stream-&gt;link);</div><div class='ctx'> </div><div class='ctx'> 	if (cp_psp == NULL || cp_psp-&gt;funcs.update_stream_config == NULL)</div><div class='ctx'> 		return;</div><div class='del'>-</div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='add'>+	if (!pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(pipe_ctx-&gt;stream-&gt;link);</div><div class='ctx'> 	ASSERT(link_enc);</div><div class='ctx'> 	if (link_enc == NULL)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -725,7 +736,7 @@ static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> static void enable_mst_on_sink(struct dc_link *link, bool enable)</div><div class='ctx'> {</div><div class='del'>-	unsigned char mstmCntl;</div><div class='add'>+	unsigned char mstmCntl = 0;</div><div class='ctx'> </div><div class='ctx'> 	core_link_read_dpcd(link, DP_MSTM_CTRL, &amp;mstmCntl, 1);</div><div class='ctx'> 	if (enable)</div><div class='hunk'>@@ -771,6 +782,20 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	bool result = false;</div><div class='add'>+</div><div class='add'>+	if (dc_is_virtual_signal(stream-&gt;signal))</div><div class='add'>+		result = true;</div><div class='add'>+	else</div><div class='add'>+		result = dm_helpers_dp_write_hblank_reduction(dc-&gt;ctx, stream);</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,</div><div class='ctx'>  * i.e. after dp_enable_dsc_on_rx() had been called</div><div class='ctx'>  */</div><div class='hunk'>@@ -803,11 +828,12 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		struct dsc_config dsc_cfg;</div><div class='del'>-		struct dsc_optc_config dsc_optc_cfg;</div><div class='add'>+		struct dsc_optc_config dsc_optc_cfg = {0};</div><div class='ctx'> 		enum optc_dsc_mode optc_dsc_mode;</div><div class='ctx'> </div><div class='ctx'> 		/* Enable DSC hw block */</div><div class='del'>-		dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='add'>+		dsc_cfg.pic_width = (stream-&gt;timing.h_addressable + pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding +</div><div class='add'>+				stream-&gt;timing.h_border_left + stream-&gt;timing.h_border_right) / opp_cnt;</div><div class='ctx'> 		dsc_cfg.pic_height = stream-&gt;timing.v_addressable + stream-&gt;timing.v_border_top + stream-&gt;timing.v_border_bottom;</div><div class='ctx'> 		dsc_cfg.pixel_encoding = stream-&gt;timing.pixel_encoding;</div><div class='ctx'> 		dsc_cfg.color_depth = stream-&gt;timing.display_color_depth;</div><div class='hunk'>@@ -815,18 +841,19 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='ctx'> 		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;</div><div class='add'>+		dsc_cfg.dsc_padding = pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='ctx'> </div><div class='add'>+		if (should_use_dto_dscclk)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, dsc-&gt;inst, dsc_cfg.dc_dsc_cfg.num_slices_h);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='del'>-		if (should_use_dto_dscclk)</div><div class='del'>-			dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, dsc-&gt;inst);</div><div class='ctx'> 		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 			struct display_stream_compressor *odm_dsc = odm_pipe-&gt;stream_res.dsc;</div><div class='ctx'> </div><div class='add'>+			if (should_use_dto_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, odm_dsc-&gt;inst, dsc_cfg.dc_dsc_cfg.num_slices_h);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_set_config(odm_dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_enable(odm_dsc, odm_pipe-&gt;stream_res.opp-&gt;inst);</div><div class='del'>-			if (should_use_dto_dscclk)</div><div class='del'>-				dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, odm_dsc-&gt;inst);</div><div class='ctx'> 		}</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;</div><div class='ctx'> 		dsc_cfg.pic_width *= opp_cnt;</div><div class='hunk'>@@ -837,10 +864,11 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		if (dc_is_dp_signal(stream-&gt;signal) &amp;&amp; !dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='ctx'> 			DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx-&gt;stream_res.stream_enc-&gt;id);</div><div class='ctx'> 			dsc_optc_config_log(dsc, &amp;dsc_optc_cfg);</div><div class='del'>-			pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_config(pipe_ctx-&gt;stream_res.stream_enc,</div><div class='del'>-									optc_dsc_mode,</div><div class='del'>-									dsc_optc_cfg.bytes_per_pixel,</div><div class='del'>-									dsc_optc_cfg.slice_width);</div><div class='add'>+			if (pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_config)</div><div class='add'>+				pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_config(pipe_ctx-&gt;stream_res.stream_enc,</div><div class='add'>+										optc_dsc_mode,</div><div class='add'>+										dsc_optc_cfg.bytes_per_pixel,</div><div class='add'>+										dsc_optc_cfg.slice_width);</div><div class='ctx'> </div><div class='ctx'> 			/* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */</div><div class='ctx'> 		}</div><div class='hunk'>@@ -867,22 +895,42 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 										NULL,</div><div class='ctx'> 										true);</div><div class='ctx'> 			else {</div><div class='del'>-				pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_config(</div><div class='del'>-						pipe_ctx-&gt;stream_res.stream_enc,</div><div class='del'>-						OPTC_DSC_DISABLED, 0, 0);</div><div class='add'>+				if (pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_config)</div><div class='add'>+					pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_config(</div><div class='add'>+							pipe_ctx-&gt;stream_res.stream_enc,</div><div class='add'>+							OPTC_DSC_DISABLED, 0, 0);</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.stream_enc-&gt;funcs-&gt;dp_set_dsc_pps_info_packet(</div><div class='ctx'> 							pipe_ctx-&gt;stream_res.stream_enc, false, NULL, true);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* disable DSC block */</div><div class='del'>-		if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='del'>-			dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, pipe_ctx-&gt;stream_res.dsc-&gt;inst);</div><div class='del'>-		pipe_ctx-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(pipe_ctx-&gt;stream_res.dsc);</div><div class='del'>-		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+		for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disconnect(odm_pipe-&gt;stream_res.dsc);</div><div class='add'>+			/*</div><div class='add'>+			 * TODO - dsc_disconnect is a double buffered register.</div><div class='add'>+			 * by the time we call dsc_disable, dsc may still remain</div><div class='add'>+			 * connected to OPP. In this case OPTC will no longer</div><div class='add'>+			 * get correct pixel data because DSCC is off. However</div><div class='add'>+			 * we also can't wait for the  disconnect pending</div><div class='add'>+			 * complete, because this function can be called</div><div class='add'>+			 * with/without OTG master lock acquired. When the lock</div><div class='add'>+			 * is acquired we will never get pending complete until</div><div class='add'>+			 * we release the lock later. So there is no easy way to</div><div class='add'>+			 * solve this problem especially when the lock is</div><div class='add'>+			 * acquired. DSC is a front end hw block it should be</div><div class='add'>+			 * programmed as part of front end sequence, where the</div><div class='add'>+			 * commit sequence without lock and update sequence</div><div class='add'>+			 * with lock are completely separated. However because</div><div class='add'>+			 * we are programming dsc as part of back end link</div><div class='add'>+			 * programming sequence, we don't know if front end OPTC</div><div class='add'>+			 * master lock is acquired. The back end should be</div><div class='add'>+			 * agnostic to front end lock. DSC programming shouldn't</div><div class='add'>+			 * belong to this sequence.</div><div class='add'>+			 */</div><div class='add'>+			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(odm_pipe-&gt;stream_res.dsc);</div><div class='ctx'> 			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='ctx'> 				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, odm_pipe-&gt;stream_res.dsc-&gt;inst);</div><div class='del'>-			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(odm_pipe-&gt;stream_res.dsc);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -923,6 +971,7 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi</div><div class='ctx'> 		dsc_cfg.color_depth = stream-&gt;timing.display_color_depth;</div><div class='ctx'> 		dsc_cfg.is_odm = pipe_ctx-&gt;next_odm_pipe ? true : false;</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='add'>+		dsc_cfg.dsc_padding = pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='ctx'> </div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_get_packed_pps(dsc, &amp;dsc_cfg, &amp;dsc_packed_pps[0]);</div><div class='ctx'> 		memcpy(&amp;stream-&gt;dsc_packed_pps[0], &amp;dsc_packed_pps[0], sizeof(stream-&gt;dsc_packed_pps));</div><div class='hunk'>@@ -1157,12 +1206,13 @@ static bool poll_for_allocation_change_trigger(struct dc_link *link)</div><div class='ctx'> 	int i;</div><div class='ctx'> 	const int act_retries = 30;</div><div class='ctx'> 	enum act_return_status result = ACT_FAILED;</div><div class='add'>+	enum dc_connection_type display_connected = (link-&gt;type != dc_connection_none);</div><div class='ctx'> 	union payload_table_update_status update_status = {0};</div><div class='ctx'> 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];</div><div class='ctx'> 	union lane_align_status_updated lane_status_updated;</div><div class='ctx'> 	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;aux_access_disabled)</div><div class='add'>+	if (!display_connected || link-&gt;aux_access_disabled)</div><div class='ctx'> 		return true;</div><div class='ctx'> 	for (i = 0; i &lt; act_retries; i++) {</div><div class='ctx'> 		get_lane_status(link, link-&gt;cur_link_settings.lane_count, dpcd_lane_status, &amp;lane_status_updated);</div><div class='hunk'>@@ -1511,6 +1561,7 @@ static bool write_128b_132b_sst_payload_allocation_table(</div><div class='ctx'> 	union payload_table_update_status update_status = { 0 };</div><div class='ctx'> 	const uint32_t max_retries = 30;</div><div class='ctx'> 	uint32_t retries = 0;</div><div class='add'>+	enum dc_connection_type display_connected = (link-&gt;type != dc_connection_none);</div><div class='ctx'> 	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	if (allocate)	{</div><div class='hunk'>@@ -1528,7 +1579,7 @@ static bool write_128b_132b_sst_payload_allocation_table(</div><div class='ctx'> 	proposed_table-&gt;stream_allocations[0].slot_count = req_slot_count;</div><div class='ctx'> 	proposed_table-&gt;stream_allocations[0].vcp_id = vc_id;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;aux_access_disabled)</div><div class='add'>+	if (!display_connected || link-&gt;aux_access_disabled)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/// Write DPCD 2C0 = 1 to start updating</div><div class='hunk'>@@ -1575,7 +1626,7 @@ static bool write_128b_132b_sst_payload_allocation_table(</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			union dpcd_rev dpcdRev;</div><div class='add'>+			union dpcd_rev dpcdRev = {0};</div><div class='ctx'> </div><div class='ctx'> 			if (core_link_read_dpcd(</div><div class='ctx'> 					link,</div><div class='hunk'>@@ -1885,7 +1936,7 @@ static void disable_link_dp(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	if (link_dp_get_encoding_format(&amp;link_settings) ==</div><div class='ctx'> 			DP_8b_10b_ENCODING) {</div><div class='del'>-		dp_set_fec_enable(link, false);</div><div class='add'>+		dp_set_fec_enable(link, link_res, false);</div><div class='ctx'> 		dp_set_fec_ready(link, link_res, false);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1896,7 +1947,9 @@ static void disable_link(struct dc_link *link,</div><div class='ctx'> {</div><div class='ctx'> 	if (dc_is_dp_signal(signal)) {</div><div class='ctx'> 		disable_link_dp(link, link_res, signal);</div><div class='del'>-	} else if (signal != SIGNAL_TYPE_VIRTUAL) {</div><div class='add'>+	} else if (signal == SIGNAL_TYPE_VIRTUAL) {</div><div class='add'>+		link-&gt;dc-&gt;hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT);</div><div class='add'>+	} else {</div><div class='ctx'> 		link-&gt;dc-&gt;hwss.disable_link_output(link, link_res, signal);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1926,11 +1979,15 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		stream-&gt;phy_pix_clk = stream-&gt;timing.pix_clk_100hz / 10;</div><div class='ctx'> 	if (stream-&gt;phy_pix_clk &gt; 340000)</div><div class='ctx'> 		is_over_340mhz = true;</div><div class='add'>+	if (dc_is_tmds_signal(stream-&gt;signal) &amp;&amp; stream-&gt;phy_pix_clk &gt; 6000000UL) {</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc_is_hdmi_signal(pipe_ctx-&gt;stream-&gt;signal)) {</div><div class='ctx'> 		unsigned short masked_chip_caps = pipe_ctx-&gt;stream-&gt;link-&gt;chip_caps &amp;</div><div class='del'>-				EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;</div><div class='del'>-		if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {</div><div class='add'>+				AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;</div><div class='add'>+		if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {</div><div class='ctx'> 			/* DP159, Retimer settings */</div><div class='ctx'> 			eng_id = pipe_ctx-&gt;stream_res.stream_enc-&gt;id;</div><div class='ctx'> </div><div class='hunk'>@@ -1941,7 +1998,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 				write_i2c_default_retimer_setting(pipe_ctx,</div><div class='ctx'> 						is_vga_mode, is_over_340mhz);</div><div class='ctx'> 			}</div><div class='del'>-		} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {</div><div class='add'>+		} else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {</div><div class='ctx'> 			/* PI3EQX1204, Redriver settings */</div><div class='ctx'> 			write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1963,7 +2020,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	/* We need to enable stream encoder for TMDS first to apply 1/4 TMDS</div><div class='ctx'> 	 * character clock in case that beyond 340MHz.</div><div class='ctx'> 	 */</div><div class='del'>-	if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+	if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal) || dc_is_dvi_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='ctx'> 		link_hwss-&gt;setup_stream_encoder(pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;hwss.enable_tmds_link_output(</div><div class='hunk'>@@ -1997,7 +2054,7 @@ static enum dc_status enable_link_dp(struct dc_state *state,</div><div class='ctx'> 	int lt_attempts = LINK_TRAINING_ATTEMPTS;</div><div class='ctx'> </div><div class='ctx'> 	// Increase retry count if attempting DP1.x on FIXED_VS link</div><div class='del'>-	if ((link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='add'>+	if (((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='ctx'> 			link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)</div><div class='ctx'> 		lt_attempts = 10;</div><div class='ctx'> </div><div class='hunk'>@@ -2012,7 +2069,8 @@ static enum dc_status enable_link_dp(struct dc_state *state,</div><div class='ctx'> 	/* Train with fallback when enabling DPIA link. Conventional links are</div><div class='ctx'> 	 * trained with fallback during sink detection.</div><div class='ctx'> 	 */</div><div class='del'>-	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp;</div><div class='add'>+			!link-&gt;dc-&gt;config.enable_dpia_pre_training)</div><div class='ctx'> 		do_fallback = true;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2056,6 +2114,9 @@ static enum dc_status enable_link_dp(struct dc_state *state,</div><div class='ctx'> 	if (link_settings-&gt;link_rate == LINK_RATE_LOW)</div><div class='ctx'> 		skip_video_pattern = false;</div><div class='ctx'> </div><div class='add'>+	if (stream-&gt;sink_patches.oled_optimize_display_on)</div><div class='add'>+		set_default_brightness_aux(link);</div><div class='add'>+</div><div class='ctx'> 	if (perform_link_training_with_retries(link_settings,</div><div class='ctx'> 					       skip_video_pattern,</div><div class='ctx'> 					       lt_attempts,</div><div class='hunk'>@@ -2073,16 +2134,20 @@ static enum dc_status enable_link_dp(struct dc_state *state,</div><div class='ctx'> 		fec_enable = true;</div><div class='ctx'> </div><div class='ctx'> 	if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)</div><div class='del'>-		dp_set_fec_enable(link, fec_enable);</div><div class='add'>+		dp_set_fec_enable(link, &amp;pipe_ctx-&gt;link_res, fec_enable);</div><div class='ctx'> </div><div class='ctx'> 	// during mode set we do DP_SET_POWER off then on, aux writes are lost</div><div class='ctx'> 	if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1 ||</div><div class='ctx'> 		link-&gt;dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||</div><div class='ctx'> 		link-&gt;dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {</div><div class='del'>-		set_default_brightness_aux(link);</div><div class='del'>-		if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1)</div><div class='del'>-			msleep(bl_oled_enable_delay);</div><div class='del'>-		edp_backlight_enable_aux(link, true);</div><div class='add'>+		if (!stream-&gt;sink_patches.oled_optimize_display_on) {</div><div class='add'>+			set_default_brightness_aux(link);</div><div class='add'>+			if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1)</div><div class='add'>+				msleep(bl_oled_enable_delay);</div><div class='add'>+			edp_backlight_enable_aux(link, true);</div><div class='add'>+		} else {</div><div class='add'>+			edp_backlight_enable_aux(link, true);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -2119,7 +2184,7 @@ static enum dc_status enable_link_dp_mst(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='del'>-	unsigned char mstm_cntl;</div><div class='add'>+	unsigned char mstm_cntl = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* sink signal type after MST branch is MST. Multiple MST sinks</div><div class='ctx'> 	 * share one link. Link DP PHY is enable or training only once.</div><div class='hunk'>@@ -2143,13 +2208,29 @@ static enum dc_status enable_link_dp_mst(</div><div class='ctx'> 	return enable_link_dp(state, pipe_ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = pipe_ctx-&gt;stream-&gt;link;</div><div class='add'>+</div><div class='add'>+	link-&gt;dc-&gt;hwss.enable_dp_link_output(link,</div><div class='add'>+			&amp;pipe_ctx-&gt;link_res,</div><div class='add'>+			SIGNAL_TYPE_DISPLAY_PORT,</div><div class='add'>+			pipe_ctx-&gt;clock_source-&gt;id,</div><div class='add'>+			&amp;pipe_ctx-&gt;link_config.dp_link_settings);</div><div class='add'>+	return DC_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum dc_status enable_link(</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_status status = DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='del'>-	struct dc_link *link = stream-&gt;link;</div><div class='add'>+	struct dc_link *link = NULL;</div><div class='add'>+</div><div class='add'>+	if (stream == NULL)</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+	link = stream-&gt;link;</div><div class='ctx'> </div><div class='ctx'> 	/* There's some scenarios where driver is unloaded with display</div><div class='ctx'> 	 * still enabled. When driver is reloaded, it may cause a display</div><div class='hunk'>@@ -2181,9 +2262,12 @@ static enum dc_status enable_link(</div><div class='ctx'> 		enable_link_lvds(pipe_ctx);</div><div class='ctx'> 		status = DC_OK;</div><div class='ctx'> 		break;</div><div class='del'>-	case SIGNAL_TYPE_VIRTUAL:</div><div class='add'>+	case SIGNAL_TYPE_RGB:</div><div class='ctx'> 		status = DC_OK;</div><div class='ctx'> 		break;</div><div class='add'>+	case SIGNAL_TYPE_VIRTUAL:</div><div class='add'>+		status = enable_link_virtual(pipe_ctx);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2222,26 +2306,10 @@ static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, i</div><div class='ctx'> 		link-&gt;dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* get dp overhead for dp tunneling */</div><div class='del'>-	link-&gt;dpia_bw_alloc_config.dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(link);</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link);</div><div class='ctx'> 	req_bw += link-&gt;dpia_bw_alloc_config.dp_overhead;</div><div class='ctx'> </div><div class='del'>-	if (link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw)) {</div><div class='del'>-		if (req_bw &lt;= link-&gt;dpia_bw_alloc_config.allocated_bw) {</div><div class='del'>-			DC_LOG_DEBUG("%s, Success in allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n",</div><div class='del'>-					__func__, link-&gt;link_index, link-&gt;dpia_bw_alloc_config.allocated_bw,</div><div class='del'>-					link-&gt;dpia_bw_alloc_config.dp_overhead);</div><div class='del'>-		} else {</div><div class='del'>-			// Cannot get the required bandwidth.</div><div class='del'>-			DC_LOG_ERROR("%s, Failed to allocate bw for link(%d), allocated_bw(%d), dp_overhead(%d)\n",</div><div class='del'>-					__func__, link-&gt;link_index, link-&gt;dpia_bw_alloc_config.allocated_bw,</div><div class='del'>-					link-&gt;dpia_bw_alloc_config.dp_overhead);</div><div class='del'>-			return false;</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		DC_LOG_DEBUG("%s, usb4 request bw timeout\n", __func__);</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='add'>+	link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw);</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='ctx'> 		int i = 0;</div><div class='hunk'>@@ -2285,6 +2353,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	struct dc_link *link = stream-&gt;sink-&gt;link;</div><div class='ctx'> 	struct vpg *vpg = pipe_ctx-&gt;stream_res.stream_enc-&gt;vpg;</div><div class='add'>+	enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link);</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(pipe_ctx-&gt;stream-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='hunk'>@@ -2298,9 +2367,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;sink) {</div><div class='ctx'> 		if (pipe_ctx-&gt;stream-&gt;sink-&gt;sink_signal != SIGNAL_TYPE_VIRTUAL &amp;&amp;</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;sink-&gt;sink_signal != SIGNAL_TYPE_NONE) {</div><div class='del'>-			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,</div><div class='add'>+			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__,</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;sink-&gt;edid_caps.display_name,</div><div class='del'>-			pipe_ctx-&gt;stream-&gt;signal);</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;signal, link-&gt;link_index);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2314,12 +2383,12 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	update_psp_stream_config(pipe_ctx, true);</div><div class='ctx'> 	dc-&gt;hwss.blank_stream(pipe_ctx);</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream-&gt;link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+	if (pipe_ctx-&gt;link_config.dp_tunnel_settings.should_use_dp_bw_allocation)</div><div class='ctx'> 		deallocate_usb4_bandwidth(pipe_ctx-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 		deallocate_mst_payload(pipe_ctx);</div><div class='del'>-	else if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT &amp;&amp;</div><div class='add'>+	else if (dc_is_dp_sst_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp;</div><div class='ctx'> 			dp_is_128b_132b_signal(pipe_ctx))</div><div class='ctx'> 		update_sst_payload(pipe_ctx, false);</div><div class='ctx'> </div><div class='hunk'>@@ -2328,13 +2397,13 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		enum engine_id eng_id = pipe_ctx-&gt;stream_res.stream_enc-&gt;id;</div><div class='ctx'> </div><div class='ctx'> 		unsigned short masked_chip_caps = link-&gt;chip_caps &amp;</div><div class='del'>-				EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;</div><div class='add'>+				AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;</div><div class='ctx'> 		//Need to inform that sink is going to use legacy HDMI mode.</div><div class='ctx'> 		write_scdc_data(</div><div class='ctx'> 			link-&gt;ddc,</div><div class='ctx'> 			165000,//vbios only handles 165Mhz.</div><div class='ctx'> 			false);</div><div class='del'>-		if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {</div><div class='add'>+		if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {</div><div class='ctx'> 			/* DP159, Retimer settings */</div><div class='ctx'> 			if (get_ext_hdmi_settings(pipe_ctx, eng_id, &amp;settings))</div><div class='ctx'> 				write_i2c_retimer_setting(pipe_ctx,</div><div class='hunk'>@@ -2342,7 +2411,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 			else</div><div class='ctx'> 				write_i2c_default_retimer_setting(pipe_ctx,</div><div class='ctx'> 						false, false);</div><div class='del'>-		} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {</div><div class='add'>+		} else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {</div><div class='ctx'> 			/* PI3EQX1204, Redriver settings */</div><div class='ctx'> 			write_i2c_redriver_setting(pipe_ctx, false);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2364,6 +2433,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		dc-&gt;hwss.disable_stream(pipe_ctx);</div><div class='ctx'> 		disable_link(pipe_ctx-&gt;stream-&gt;link, &amp;pipe_ctx-&gt;link_res, pipe_ctx-&gt;stream-&gt;signal);</div><div class='ctx'> 	}</div><div class='add'>+	edp_set_panel_assr(link, pipe_ctx, &amp;panel_mode_dp, false);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;timing.flags.DSC) {</div><div class='ctx'> 		if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='hunk'>@@ -2381,7 +2451,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	if (link-&gt;connector_signal == SIGNAL_TYPE_EDP &amp;&amp; dc-&gt;debug.psp_disabled_wa) {</div><div class='ctx'> 		/* reset internal save state to default since eDP is  off */</div><div class='ctx'> 		enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx-&gt;stream-&gt;link);</div><div class='del'>-		/* since current psp not loaded, we need to reset it to default*/</div><div class='add'>+		/* since current psp not loaded, we need to reset it to default */</div><div class='ctx'> 		link-&gt;panel_mode = panel_mode;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -2394,7 +2464,7 @@ void link_set_dpms_on(</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	struct dc_link *link = stream-&gt;sink-&gt;link;</div><div class='ctx'> 	enum dc_status status;</div><div class='del'>-	struct link_encoder *link_enc;</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;</div><div class='ctx'> 	struct vpg *vpg = pipe_ctx-&gt;stream_res.stream_enc-&gt;vpg;</div><div class='ctx'> 	const struct link_hwss *link_hwss = get_link_hwss(link, &amp;pipe_ctx-&gt;link_res);</div><div class='hunk'>@@ -2413,28 +2483,23 @@ void link_set_dpms_on(</div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;sink) {</div><div class='ctx'> 		if (pipe_ctx-&gt;stream-&gt;sink-&gt;sink_signal != SIGNAL_TYPE_VIRTUAL &amp;&amp;</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;sink-&gt;sink_signal != SIGNAL_TYPE_NONE) {</div><div class='del'>-			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,</div><div class='add'>+			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__,</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;sink-&gt;edid_caps.display_name,</div><div class='del'>-			pipe_ctx-&gt;stream-&gt;signal);</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;signal,</div><div class='add'>+			link-&gt;link_index);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> 	ASSERT(link_enc);</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal)</div><div class='ctx'> 			&amp;&amp; !dp_is_128b_132b_signal(pipe_ctx)) {</div><div class='del'>-		struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='del'>-</div><div class='ctx'> 		if (link_enc)</div><div class='ctx'> 			link_enc-&gt;funcs-&gt;setup(</div><div class='ctx'> 				link_enc,</div><div class='ctx'> 				pipe_ctx-&gt;stream-&gt;signal);</div><div class='del'>-</div><div class='del'>-		if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;dig_stream_enable)</div><div class='del'>-			stream_enc-&gt;funcs-&gt;dig_stream_enable(</div><div class='del'>-				stream_enc,</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;signal, 1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;link-&gt;link_state_valid = true;</div><div class='hunk'>@@ -2482,12 +2547,29 @@ void link_set_dpms_on(</div><div class='ctx'> 				!pipe_ctx-&gt;next_odm_pipe) {</div><div class='ctx'> 		pipe_ctx-&gt;stream-&gt;dpms_off = false;</div><div class='ctx'> 		update_psp_stream_config(pipe_ctx, false);</div><div class='add'>+</div><div class='add'>+		if (link-&gt;is_dds) {</div><div class='add'>+			uint32_t post_oui_delay = 30; // 30ms</div><div class='add'>+</div><div class='add'>+			dpcd_set_source_specific_data(link);</div><div class='add'>+			msleep(post_oui_delay);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;dpms_off)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	/* For Dp tunneling link, a pending HPD means that we have a race condition between processing</div><div class='add'>+	 * current link and processing the pending HPD. If we enable the link now, we may end up with a</div><div class='add'>+	 * link that is not actually connected to a sink. So we skip enabling the link in this case.</div><div class='add'>+	 */</div><div class='add'>+	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp; link-&gt;is_hpd_pending) {</div><div class='add'>+		DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link-&gt;link_index);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Have to setup DSC before DIG FE and BE are connected (which happens before the</div><div class='ctx'> 	 * link training). This is to make sure the bandwidth sent to DIG BE won't be</div><div class='ctx'> 	 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag</div><div class='hunk'>@@ -2534,18 +2616,12 @@ void link_set_dpms_on(</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!(dc_is_virtual_signal(pipe_ctx-&gt;stream-&gt;signal) ||</div><div class='ctx'> 			dp_is_128b_132b_signal(pipe_ctx))) {</div><div class='del'>-			struct stream_encoder *stream_enc = pipe_ctx-&gt;stream_res.stream_enc;</div><div class='ctx'> </div><div class='ctx'> 			if (link_enc)</div><div class='ctx'> 				link_enc-&gt;funcs-&gt;setup(</div><div class='ctx'> 					link_enc,</div><div class='ctx'> 					pipe_ctx-&gt;stream-&gt;signal);</div><div class='ctx'> </div><div class='del'>-			if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;dig_stream_enable)</div><div class='del'>-				stream_enc-&gt;funcs-&gt;dig_stream_enable(</div><div class='del'>-					stream_enc,</div><div class='del'>-					pipe_ctx-&gt;stream-&gt;signal, 1);</div><div class='del'>-</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;hwss.enable_stream(pipe_ctx);</div><div class='hunk'>@@ -2559,15 +2635,27 @@ void link_set_dpms_on(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream-&gt;link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+	if (dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		dp_set_hblank_reduction_on_rx(pipe_ctx);</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;link_config.dp_tunnel_settings.should_use_dp_bw_allocation)</div><div class='ctx'> 		allocate_usb4_bandwidth(pipe_ctx-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 		allocate_mst_payload(pipe_ctx);</div><div class='del'>-	else if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT &amp;&amp;</div><div class='add'>+	else if (dc_is_dp_sst_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp;</div><div class='ctx'> 			dp_is_128b_132b_signal(pipe_ctx))</div><div class='ctx'> 		update_sst_payload(pipe_ctx, true);</div><div class='ctx'> </div><div class='add'>+	/* Corruption was observed on systems with display mux when stream gets</div><div class='add'>+	 * enabled after the mux switch. Having a small delay between link</div><div class='add'>+	 * training and stream unblank resolves the corruption issue.</div><div class='add'>+	 * This is workaround.</div><div class='add'>+	 */</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='add'>+			link-&gt;is_display_mux_present)</div><div class='add'>+		msleep(20);</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;hwss.unblank_stream(pipe_ctx,</div><div class='ctx'> 		&amp;pipe_ctx-&gt;stream-&gt;link-&gt;cur_link_settings);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.h b/drivers/gpu/drm/amd/display/dc/link/link_dpms.h<br/>index 9398f9c1666a..bd6fc63064a3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_dpms.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_dpms.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_dpms.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_dpms.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #ifndef __DC_LINK_DPMS_H__</div><div class='ctx'> #define __DC_LINK_DPMS_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> void link_set_dpms_on(</div><div class='ctx'> 		struct dc_state *state,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c<br/>index cf22b8f28ba6..a6e2b0821969 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_factory.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_factory.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_factory.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_factory.c</a></div><div class='hunk'>@@ -100,7 +100,8 @@ static void construct_link_service_validation(struct link_service *link_srv)</div><div class='ctx'> {</div><div class='ctx'> 	link_srv-&gt;validate_mode_timing = link_validate_mode_timing;</div><div class='ctx'> 	link_srv-&gt;dp_link_bandwidth_kbps = dp_link_bandwidth_kbps;</div><div class='del'>-	link_srv-&gt;validate_dpia_bandwidth = link_validate_dpia_bandwidth;</div><div class='add'>+	link_srv-&gt;validate_dp_tunnel_bandwidth = link_validate_dp_tunnel_bandwidth;</div><div class='add'>+	link_srv-&gt;dp_required_hblank_size_bytes = dp_required_hblank_size_bytes;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* link dpms owns the programming sequence of stream's dpms state associated</div><div class='hunk'>@@ -155,6 +156,7 @@ static void construct_link_service_dp_capability(struct link_service *link_srv)</div><div class='ctx'> 	link_srv-&gt;dp_get_encoding_format = link_dp_get_encoding_format;</div><div class='ctx'> 	link_srv-&gt;dp_should_enable_fec = dp_should_enable_fec;</div><div class='ctx'> 	link_srv-&gt;dp_decide_link_settings = link_decide_link_settings;</div><div class='add'>+	link_srv-&gt;dp_decide_tunnel_settings = link_decide_dp_tunnel_settings;</div><div class='ctx'> 	link_srv-&gt;mst_decide_link_encoding_format =</div><div class='ctx'> 			mst_decide_link_encoding_format;</div><div class='ctx'> 	link_srv-&gt;edp_decide_link_settings = edp_decide_link_settings;</div><div class='hunk'>@@ -163,6 +165,8 @@ static void construct_link_service_dp_capability(struct link_service *link_srv)</div><div class='ctx'> 	link_srv-&gt;dp_overwrite_extended_receiver_cap =</div><div class='ctx'> 			dp_overwrite_extended_receiver_cap;</div><div class='ctx'> 	link_srv-&gt;dp_decide_lttpr_mode = dp_decide_lttpr_mode;</div><div class='add'>+	link_srv-&gt;dp_get_lttpr_count = dp_get_lttpr_count;</div><div class='add'>+	link_srv-&gt;edp_get_alpm_support = edp_get_alpm_support;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* link dp phy/dpia implements basic dp phy/dpia functionality such as</div><div class='hunk'>@@ -174,7 +178,6 @@ static void construct_link_service_dp_phy_or_dpia(struct link_service *link_srv)</div><div class='ctx'> {</div><div class='ctx'> 	link_srv-&gt;dpia_handle_usb4_bandwidth_allocation_for_link =</div><div class='ctx'> 			dpia_handle_usb4_bandwidth_allocation_for_link;</div><div class='del'>-	link_srv-&gt;dpia_handle_bw_alloc_response = dpia_handle_bw_alloc_response;</div><div class='ctx'> 	link_srv-&gt;dp_set_drive_settings = dp_set_drive_settings;</div><div class='ctx'> 	link_srv-&gt;dpcd_write_rx_power_ctrl = dpcd_write_rx_power_ctrl;</div><div class='ctx'> }</div><div class='hunk'>@@ -385,12 +388,12 @@ static void link_destruct(struct dc_link *link)</div><div class='ctx'> 	if (link-&gt;panel_cntl)</div><div class='ctx'> 		link-&gt;panel_cntl-&gt;funcs-&gt;destroy(&amp;link-&gt;panel_cntl);</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;link_enc) {</div><div class='add'>+	if (link-&gt;link_enc &amp;&amp; !link-&gt;is_dig_mapping_flexible) {</div><div class='ctx'> 		/* Update link encoder resource tracking variables. These are used for</div><div class='ctx'> 		 * the dynamic assignment of link encoders to streams. Virtual links</div><div class='ctx'> 		 * are not assigned encoder resources on creation.</div><div class='ctx'> 		 */</div><div class='del'>-		if (link-&gt;link_id.id != CONNECTOR_ID_VIRTUAL) {</div><div class='add'>+		if (link-&gt;link_id.id != CONNECTOR_ID_VIRTUAL &amp;&amp; link-&gt;eng_id != ENGINE_ID_UNKNOWN) {</div><div class='ctx'> 			link-&gt;dc-&gt;res_pool-&gt;link_encoders[link-&gt;eng_id - ENGINE_ID_DIGA] = NULL;</div><div class='ctx'> 			link-&gt;dc-&gt;res_pool-&gt;dig_link_enc_count--;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -448,6 +451,46 @@ static enum channel_id get_ddc_line(struct dc_link *link)</div><div class='ctx'> 	return channel;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum engine_id find_analog_engine(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	struct dc_bios *bp = link-&gt;ctx-&gt;dc_bios;</div><div class='add'>+	struct graphics_object_id encoder = {0};</div><div class='add'>+	enum bp_result bp_result = BP_RESULT_OK;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 3; i++) {</div><div class='add'>+		bp_result = bp-&gt;funcs-&gt;get_src_obj(bp, link-&gt;link_id, i, &amp;encoder);</div><div class='add'>+</div><div class='add'>+		if (bp_result != BP_RESULT_OK)</div><div class='add'>+			return ENGINE_ID_UNKNOWN;</div><div class='add'>+</div><div class='add'>+		switch (encoder.id) {</div><div class='add'>+		case ENCODER_ID_INTERNAL_DAC1:</div><div class='add'>+		case ENCODER_ID_INTERNAL_KLDSCP_DAC1:</div><div class='add'>+			return ENGINE_ID_DACA;</div><div class='add'>+		case ENCODER_ID_INTERNAL_DAC2:</div><div class='add'>+		case ENCODER_ID_INTERNAL_KLDSCP_DAC2:</div><div class='add'>+			return ENGINE_ID_DACB;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ENGINE_ID_UNKNOWN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool transmitter_supported(const enum transmitter transmitter)</div><div class='add'>+{</div><div class='add'>+	return transmitter != TRANSMITTER_UNKNOWN &amp;&amp;</div><div class='add'>+		transmitter != TRANSMITTER_NUTMEG_CRT &amp;&amp;</div><div class='add'>+		transmitter != TRANSMITTER_TRAVIS_CRT &amp;&amp;</div><div class='add'>+		transmitter != TRANSMITTER_TRAVIS_LCD;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool analog_engine_supported(const enum engine_id engine_id)</div><div class='add'>+{</div><div class='add'>+	return engine_id == ENGINE_ID_DACA ||</div><div class='add'>+		engine_id == ENGINE_ID_DACB;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 			      const struct link_init_data *init_params)</div><div class='ctx'> {</div><div class='hunk'>@@ -456,7 +499,6 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 	struct dc_context *dc_ctx = init_params-&gt;ctx;</div><div class='ctx'> 	struct encoder_init_data enc_init_data = { 0 };</div><div class='ctx'> 	struct panel_cntl_init_data panel_cntl_init_data = { 0 };</div><div class='del'>-	struct integrated_info info = { 0 };</div><div class='ctx'> 	struct dc_bios *bios = init_params-&gt;dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	const struct dc_vbios_funcs *bp_funcs = bios-&gt;funcs;</div><div class='ctx'> 	struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };</div><div class='hunk'>@@ -465,6 +507,7 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;irq_source_hpd = DC_IRQ_SOURCE_INVALID;</div><div class='ctx'> 	link-&gt;irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;</div><div class='add'>+	link-&gt;irq_source_read_request = DC_IRQ_SOURCE_INVALID;</div><div class='ctx'> 	link-&gt;link_status.dpcd_caps = &amp;link-&gt;dpcd_caps;</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;dc = init_params-&gt;dc;</div><div class='hunk'>@@ -479,10 +522,23 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 	link-&gt;link_id =</div><div class='ctx'> 		bios-&gt;funcs-&gt;get_connector_id(bios, init_params-&gt;connector_index);</div><div class='ctx'> </div><div class='add'>+	/* Determine early if the link has any supported encoders,</div><div class='add'>+	 * so that we avoid initializing DDC and HPD, etc.</div><div class='add'>+	 */</div><div class='add'>+	bp_funcs-&gt;get_src_obj(bios, link-&gt;link_id, 0, &amp;enc_init_data.encoder);</div><div class='add'>+	enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder);</div><div class='add'>+	enc_init_data.analog_engine = find_analog_engine(link);</div><div class='add'>+</div><div class='ctx'> 	link-&gt;ep_type = DISPLAY_ENDPOINT_PHY;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_DC("BIOS object table - link_id: %d", link-&gt;link_id.id);</div><div class='ctx'> </div><div class='add'>+	if (!transmitter_supported(enc_init_data.transmitter) &amp;&amp;</div><div class='add'>+	    !analog_engine_supported(enc_init_data.analog_engine)) {</div><div class='add'>+		DC_LOG_WARNING("link_id %d has unsupported encoder\n", link-&gt;link_id.id);</div><div class='add'>+		goto unsupported_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (bios-&gt;funcs-&gt;get_disp_connector_caps_info) {</div><div class='ctx'> 		bios-&gt;funcs-&gt;get_disp_connector_caps_info(bios, link-&gt;link_id, &amp;disp_connect_caps_info);</div><div class='ctx'> 		link-&gt;is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;</div><div class='hunk'>@@ -515,6 +571,9 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 	case CONNECTOR_ID_HDMI_TYPE_A:</div><div class='ctx'> 		link-&gt;connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;</div><div class='ctx'> </div><div class='add'>+		if (link-&gt;hpd_gpio)</div><div class='add'>+			link-&gt;irq_source_read_request =</div><div class='add'>+					dal_irq_get_read_request(link-&gt;hpd_gpio);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CONNECTOR_ID_SINGLE_LINK_DVID:</div><div class='ctx'> 	case CONNECTOR_ID_SINGLE_LINK_DVII:</div><div class='hunk'>@@ -524,7 +583,11 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 	case CONNECTOR_ID_DUAL_LINK_DVII:</div><div class='ctx'> 		link-&gt;connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;</div><div class='ctx'> 		break;</div><div class='add'>+	case CONNECTOR_ID_VGA:</div><div class='add'>+		link-&gt;connector_signal = SIGNAL_TYPE_RGB;</div><div class='add'>+		break;</div><div class='ctx'> 	case CONNECTOR_ID_DISPLAY_PORT:</div><div class='add'>+	case CONNECTOR_ID_MXM:</div><div class='ctx'> 	case CONNECTOR_ID_USBC:</div><div class='ctx'> 		link-&gt;connector_signal = SIGNAL_TYPE_DISPLAY_PORT;</div><div class='ctx'> </div><div class='hunk'>@@ -534,10 +597,16 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	case CONNECTOR_ID_EDP:</div><div class='add'>+		// If smartmux is supported, only create the link on the primary eDP.</div><div class='add'>+		// Dual eDP is not supported with smartmux.</div><div class='add'>+		if (!(!link-&gt;dc-&gt;config.smart_mux_version || dc_ctx-&gt;dc_edp_id_count == 0))</div><div class='add'>+			goto create_fail;</div><div class='add'>+</div><div class='ctx'> 		link-&gt;connector_signal = SIGNAL_TYPE_EDP;</div><div class='ctx'> </div><div class='ctx'> 		if (link-&gt;hpd_gpio) {</div><div class='del'>-			if (!link-&gt;dc-&gt;config.allow_edp_hotplug_detection)</div><div class='add'>+			if (!link-&gt;dc-&gt;config.allow_edp_hotplug_detection</div><div class='add'>+				&amp;&amp; !is_smartmux_suported(link))</div><div class='ctx'> 				link-&gt;irq_source_hpd = DC_IRQ_SOURCE_INVALID;</div><div class='ctx'> </div><div class='ctx'> 			switch (link-&gt;dc-&gt;config.allow_edp_hotplug_detection) {</div><div class='hunk'>@@ -598,27 +667,23 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 		dal_ddc_get_line(get_ddc_pin(link-&gt;ddc));</div><div class='ctx'> </div><div class='ctx'> 	enc_init_data.ctx = dc_ctx;</div><div class='del'>-	bp_funcs-&gt;get_src_obj(dc_ctx-&gt;dc_bios, link-&gt;link_id, 0,</div><div class='del'>-			      &amp;enc_init_data.encoder);</div><div class='ctx'> 	enc_init_data.connector = link-&gt;link_id;</div><div class='ctx'> 	enc_init_data.channel = get_ddc_line(link);</div><div class='ctx'> 	enc_init_data.hpd_source = get_hpd_line(link);</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;hpd_src = enc_init_data.hpd_source;</div><div class='ctx'> </div><div class='del'>-	enc_init_data.transmitter =</div><div class='del'>-		translate_encoder_to_transmitter(enc_init_data.encoder);</div><div class='ctx'> 	link-&gt;link_enc =</div><div class='ctx'> 		link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_enc_create(dc_ctx, &amp;enc_init_data);</div><div class='ctx'> </div><div class='del'>-	DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link-&gt;link_enc-&gt;features.flags.bits.DP_IS_USB_C);</div><div class='del'>-	DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link-&gt;link_enc-&gt;features.flags.bits.IS_DP2_CAPABLE);</div><div class='del'>-</div><div class='ctx'> 	if (!link-&gt;link_enc) {</div><div class='ctx'> 		DC_ERROR("Failed to create link encoder!\n");</div><div class='ctx'> 		goto link_enc_create_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link-&gt;link_enc-&gt;features.flags.bits.DP_IS_USB_C);</div><div class='add'>+	DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link-&gt;link_enc-&gt;features.flags.bits.IS_DP2_CAPABLE);</div><div class='add'>+</div><div class='ctx'> 	/* Update link encoder tracking variables. These are used for the dynamic</div><div class='ctx'> 	 * assignment of link encoders to streams.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -653,7 +718,7 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Look for device tag that matches connector signal,</div><div class='del'>-		 * CRT for rgb, LCD for other supported signal tyes</div><div class='add'>+		 * CRT for rgb, LCD for other supported signal types</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (!bp_funcs-&gt;is_device_id_supported(dc_ctx-&gt;dc_bios,</div><div class='ctx'> 						      link-&gt;device_tag.dev_id))</div><div class='hunk'>@@ -671,42 +736,44 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (bios-&gt;integrated_info)</div><div class='del'>-		info = *bios-&gt;integrated_info;</div><div class='del'>-</div><div class='del'>-	/* Look for channel mapping corresponding to connector and device tag */</div><div class='del'>-	for (i = 0; i &lt; MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {</div><div class='del'>-		struct external_display_path *path =</div><div class='del'>-			&amp;info.ext_disp_conn_info.path[i];</div><div class='del'>-</div><div class='del'>-		if (path-&gt;device_connector_id.enum_id == link-&gt;link_id.enum_id &amp;&amp;</div><div class='del'>-		    path-&gt;device_connector_id.id == link-&gt;link_id.id &amp;&amp;</div><div class='del'>-		    path-&gt;device_connector_id.type == link-&gt;link_id.type) {</div><div class='del'>-			if (link-&gt;device_tag.acpi_device != 0 &amp;&amp;</div><div class='del'>-			    path-&gt;device_acpi_enum == link-&gt;device_tag.acpi_device) {</div><div class='del'>-				link-&gt;ddi_channel_mapping = path-&gt;channel_mapping;</div><div class='del'>-				link-&gt;chip_caps = path-&gt;caps;</div><div class='del'>-				DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link-&gt;ddi_channel_mapping.raw);</div><div class='del'>-				DC_LOG_DC("BIOS object table - chip_caps: %d", link-&gt;chip_caps);</div><div class='del'>-			} else if (path-&gt;device_tag ==</div><div class='del'>-				   link-&gt;device_tag.dev_id.raw_device_tag) {</div><div class='del'>-				link-&gt;ddi_channel_mapping = path-&gt;channel_mapping;</div><div class='del'>-				link-&gt;chip_caps = path-&gt;caps;</div><div class='del'>-				DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link-&gt;ddi_channel_mapping.raw);</div><div class='del'>-				DC_LOG_DC("BIOS object table - chip_caps: %d", link-&gt;chip_caps);</div><div class='del'>-			}</div><div class='add'>+	if (bios-&gt;integrated_info) {</div><div class='add'>+		/* Look for channel mapping corresponding to connector and device tag */</div><div class='add'>+		for (i = 0; i &lt; MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {</div><div class='add'>+			struct external_display_path *path =</div><div class='add'>+				&amp;bios-&gt;integrated_info-&gt;ext_disp_conn_info.path[i];</div><div class='add'>+</div><div class='add'>+			if (path-&gt;device_connector_id.enum_id == link-&gt;link_id.enum_id &amp;&amp;</div><div class='add'>+			    path-&gt;device_connector_id.id == link-&gt;link_id.id &amp;&amp;</div><div class='add'>+			    path-&gt;device_connector_id.type == link-&gt;link_id.type) {</div><div class='add'>+				if (link-&gt;device_tag.acpi_device != 0 &amp;&amp;</div><div class='add'>+				    path-&gt;device_acpi_enum == link-&gt;device_tag.acpi_device) {</div><div class='add'>+					link-&gt;ddi_channel_mapping = path-&gt;channel_mapping;</div><div class='add'>+					link-&gt;chip_caps = path-&gt;caps;</div><div class='add'>+					DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X",</div><div class='add'>+						  link-&gt;ddi_channel_mapping.raw);</div><div class='add'>+					DC_LOG_DC("BIOS object table - chip_caps: %d",</div><div class='add'>+						  link-&gt;chip_caps);</div><div class='add'>+				} else if (path-&gt;device_tag ==</div><div class='add'>+					   link-&gt;device_tag.dev_id.raw_device_tag) {</div><div class='add'>+					link-&gt;ddi_channel_mapping = path-&gt;channel_mapping;</div><div class='add'>+					link-&gt;chip_caps = path-&gt;caps;</div><div class='add'>+					DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X",</div><div class='add'>+						  link-&gt;ddi_channel_mapping.raw);</div><div class='add'>+					DC_LOG_DC("BIOS object table - chip_caps: %d",</div><div class='add'>+						  link-&gt;chip_caps);</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				if ((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {</div><div class='add'>+					link-&gt;bios_forced_drive_settings.VOLTAGE_SWING =</div><div class='add'>+						(bios-&gt;integrated_info-&gt;ext_disp_conn_info.fixdpvoltageswing &amp; 0x3);</div><div class='add'>+					link-&gt;bios_forced_drive_settings.PRE_EMPHASIS =</div><div class='add'>+						((bios-&gt;integrated_info-&gt;ext_disp_conn_info.fixdpvoltageswing &gt;&gt; 2) &amp; 0x3);</div><div class='add'>+				}</div><div class='ctx'> </div><div class='del'>-			if (link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {</div><div class='del'>-				link-&gt;bios_forced_drive_settings.VOLTAGE_SWING =</div><div class='del'>-						(info.ext_disp_conn_info.fixdpvoltageswing &amp; 0x3);</div><div class='del'>-				link-&gt;bios_forced_drive_settings.PRE_EMPHASIS =</div><div class='del'>-						((info.ext_disp_conn_info.fixdpvoltageswing &gt;&gt; 2) &amp; 0x3);</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='del'>-</div><div class='del'>-			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> 	if (bios-&gt;funcs-&gt;get_atom_dc_golden_table)</div><div class='ctx'> 		bios-&gt;funcs-&gt;get_atom_dc_golden_table(bios);</div><div class='ctx'> </div><div class='hunk'>@@ -720,6 +787,7 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;psr_settings.psr_vtotal_control_support = false;</div><div class='ctx'> 	link-&gt;psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;</div><div class='add'>+	link-&gt;replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);</div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -738,6 +806,7 @@ create_fail:</div><div class='ctx'> 		link-&gt;hpd_gpio = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+unsupported_fail:</div><div class='ctx'> 	DC_LOG_DC("BIOS object table - %s failed.\n", __func__);</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -801,9 +870,7 @@ static bool construct_dpia(struct dc_link *link,</div><div class='ctx'> 	/* TODO: Create link encoder */</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;</div><div class='del'>-</div><div class='del'>-	/* Some docks seem to NAK I2C writes to segment pointer with mot=0. */</div><div class='del'>-	link-&gt;wa_flags.dp_mot_reset_segment = true;</div><div class='add'>+	link-&gt;replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.h b/drivers/gpu/drm/amd/display/dc/link/link_factory.h<br/>index e96220d48d03..aad36ca1a31c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_factory.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_factory.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_factory.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_factory.h</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #ifndef __LINK_FACTORY_H__</div><div class='ctx'> #define __LINK_FACTORY_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> struct dc_link *link_create(const struct link_init_data *init_params);</div><div class='ctx'> void link_destroy(struct dc_link **link);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_resource.h b/drivers/gpu/drm/amd/display/dc/link/link_resource.h<br/>index 1907bda3cb6e..f7aa3bc3a93a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_resource.h</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #ifndef __LINK_RESOURCE_H__</div><div class='ctx'> #define __LINK_RESOURCE_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> void link_get_cur_res_map(const struct dc *dc, uint32_t *map);</div><div class='ctx'> void link_restore_res_map(const struct dc *dc, uint32_t *map);</div><div class='ctx'> void link_get_cur_link_res(const struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c<br/>index 1aed55b0ab6a..acdc162de535 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_validation.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_validation.c</a></div><div class='hunk'>@@ -86,6 +86,10 @@ static bool dp_active_dongle_validate_timing(</div><div class='ctx'> 			if (!dongle_caps-&gt;is_dp_hdmi_ycbcr420_pass_through)</div><div class='ctx'> 				return false;</div><div class='ctx'> 			break;</div><div class='add'>+		case PIXEL_ENCODING_UNDEFINED:</div><div class='add'>+			/* These color depths are currently not supported */</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			/* Invalid Pixel Encoding*/</div><div class='ctx'> 			return false;</div><div class='hunk'>@@ -104,6 +108,10 @@ static bool dp_active_dongle_validate_timing(</div><div class='ctx'> 			if (dongle_caps-&gt;dp_hdmi_max_bpc &lt; 12)</div><div class='ctx'> 				return false;</div><div class='ctx'> 			break;</div><div class='add'>+		case COLOR_DEPTH_UNDEFINED:</div><div class='add'>+			/* These color depths are currently not supported */</div><div class='add'>+			ASSERT(false);</div><div class='add'>+			break;</div><div class='ctx'> 		case COLOR_DEPTH_141414:</div><div class='ctx'> 		case COLOR_DEPTH_161616:</div><div class='ctx'> 		default:</div><div class='hunk'>@@ -255,6 +263,14 @@ uint32_t dp_link_bandwidth_kbps(</div><div class='ctx'> 	return link_rate_per_lane_kbps * link_settings-&gt;lane_count / 10000 * total_data_bw_efficiency_x10000;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint32_t dp_get_timing_bandwidth_kbps(</div><div class='add'>+	const struct dc_crtc_timing *timing,</div><div class='add'>+	const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	return dc_bandwidth_in_kbps_from_timing(timing,</div><div class='add'>+			dc_link_get_highest_encoding_format(link));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool dp_validate_mode_timing(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	const struct dc_crtc_timing *timing)</div><div class='hunk'>@@ -287,6 +303,13 @@ static bool dp_validate_mode_timing(</div><div class='ctx'> 	req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link));</div><div class='ctx'> 	max_bw = dp_link_bandwidth_kbps(link, link_setting);</div><div class='ctx'> </div><div class='add'>+	bool is_max_uncompressed_pixel_rate_exceeded = link-&gt;dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid &amp;&amp;</div><div class='add'>+			timing-&gt;pix_clk_100hz &gt; link-&gt;dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000;</div><div class='add'>+</div><div class='add'>+	if (is_max_uncompressed_pixel_rate_exceeded &amp;&amp; !timing-&gt;flags.DSC) {</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (req_bw &lt;= max_bw) {</div><div class='ctx'> 		/* remember the biggest mode here, during</div><div class='ctx'> 		 * initial link training (to get</div><div class='hunk'>@@ -344,61 +367,260 @@ enum dc_status link_validate_mode_timing(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct dc_tunnel_settings *get_dp_tunnel_settings(const struct dc_state *context,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	const struct dc_tunnel_settings *dp_tunnel_settings = NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].stream &amp;&amp; (context-&gt;res_ctx.pipe_ctx[i].stream == stream)) {</div><div class='add'>+			dp_tunnel_settings = &amp;context-&gt;res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dp_tunnel_settings;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='del'>- * This function calculates the bandwidth required for the stream timing</div><div class='del'>- * and aggregates the stream bandwidth for the respective dpia link</div><div class='del'>- *</div><div class='del'>- * @stream: pointer to the dc_stream_state struct instance</div><div class='del'>- * @num_streams: number of streams to be validated</div><div class='add'>+ * Calculates the DP tunneling bandwidth required for the stream timing</div><div class='add'>+ * and aggregates the stream bandwidth for the respective DP tunneling link</div><div class='ctx'>  *</div><div class='del'>- * return: true if validation is succeeded</div><div class='add'>+ * return: dc_status</div><div class='ctx'>  */</div><div class='del'>-bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams)</div><div class='add'>+enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)</div><div class='ctx'> {</div><div class='del'>-	int bw_needed[MAX_DPIA_NUM] = {0};</div><div class='del'>-	struct dc_link *dpia_link[MAX_DPIA_NUM] = {0};</div><div class='del'>-	int num_dpias = 0;</div><div class='del'>-</div><div class='del'>-	for (unsigned int i = 0; i &lt; num_streams; ++i) {</div><div class='del'>-		if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT) {</div><div class='del'>-			/* new dpia sst stream, check whether it exceeds max dpia */</div><div class='del'>-			if (num_dpias &gt;= MAX_DPIA_NUM)</div><div class='del'>-				return false;</div><div class='add'>+	struct dc_validation_dpia_set dpia_link_sets[MAX_DPIA_NUM] = { 0 };</div><div class='add'>+	uint8_t link_count = 0;</div><div class='add'>+	enum dc_status result = DC_OK;</div><div class='add'>+</div><div class='add'>+	// Iterate through streams in the new context</div><div class='add'>+	for (uint8_t i = 0; (i &lt; MAX_PIPES &amp;&amp; i &lt; new_ctx-&gt;stream_count); i++) {</div><div class='add'>+		const struct dc_stream_state *stream = new_ctx-&gt;streams[i];</div><div class='add'>+		const struct dc_link *link;</div><div class='add'>+		const struct dc_tunnel_settings *dp_tunnel_settings;</div><div class='add'>+		uint32_t timing_bw;</div><div class='add'>+</div><div class='add'>+		if (stream == NULL)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		link = stream-&gt;link;</div><div class='add'>+</div><div class='add'>+		if (!(link &amp;&amp; (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT</div><div class='add'>+				|| stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if ((link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) &amp;&amp; (link-&gt;hpd_status == false))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		dp_tunnel_settings = get_dp_tunnel_settings(new_ctx, stream);</div><div class='ctx'> </div><div class='del'>-			dpia_link[num_dpias] = stream[i].link;</div><div class='del'>-			bw_needed[num_dpias] = dc_bandwidth_in_kbps_from_timing(&amp;stream[i].timing,</div><div class='del'>-					dc_link_get_highest_encoding_format(dpia_link[num_dpias]));</div><div class='del'>-			num_dpias++;</div><div class='del'>-		} else if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='del'>-			uint8_t j = 0;</div><div class='del'>-			/* check whether its a known dpia link */</div><div class='del'>-			for (; j &lt; num_dpias; ++j) {</div><div class='del'>-				if (dpia_link[j] == stream[i].link)</div><div class='del'>-					break;</div><div class='add'>+		if ((dp_tunnel_settings == NULL) || (dp_tunnel_settings-&gt;should_use_dp_bw_allocation == false))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		timing_bw = dp_get_timing_bandwidth_kbps(&amp;stream-&gt;timing, link);</div><div class='add'>+</div><div class='add'>+		// Find an existing entry for this 'link' in 'dpia_link_sets'</div><div class='add'>+		for (uint8_t j = 0; j &lt; MAX_DPIA_NUM; j++) {</div><div class='add'>+			bool is_new_slot = false;</div><div class='add'>+</div><div class='add'>+			if (dpia_link_sets[j].link == NULL) {</div><div class='add'>+				is_new_slot = true;</div><div class='add'>+				link_count++;</div><div class='add'>+				dpia_link_sets[j].required_bw = 0;</div><div class='add'>+				dpia_link_sets[j].link = link;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			if (j == num_dpias) {</div><div class='del'>-				/* new dpia mst stream, check whether it exceeds max dpia */</div><div class='del'>-				if (num_dpias &gt;= MAX_DPIA_NUM)</div><div class='del'>-					return false;</div><div class='del'>-				else {</div><div class='del'>-					dpia_link[j] = stream[i].link;</div><div class='del'>-					num_dpias++;</div><div class='del'>-				}</div><div class='add'>+			if (is_new_slot || (dpia_link_sets[j].link == link)) {</div><div class='add'>+				dpia_link_sets[j].tunnel_settings = dp_tunnel_settings;</div><div class='add'>+				dpia_link_sets[j].required_bw += timing_bw;</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (link_count &amp;&amp; link_dpia_validate_dp_tunnel_bandwidth(dpia_link_sets, link_count) == false)</div><div class='add'>+		result = DC_FAIL_DP_TUNNEL_BW_VALIDATE;</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-			bw_needed[j] += dc_bandwidth_in_kbps_from_timing(&amp;stream[i].timing,</div><div class='del'>-				dc_link_get_highest_encoding_format(dpia_link[j]));</div><div class='add'>+struct dp_audio_layout_config {</div><div class='add'>+	uint8_t layouts_per_sample_denom;</div><div class='add'>+	uint8_t symbols_per_layout;</div><div class='add'>+	uint8_t max_layouts_per_audio_sdp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void get_audio_layout_config(</div><div class='add'>+	uint32_t channel_count,</div><div class='add'>+	enum dp_link_encoding encoding,</div><div class='add'>+	struct dp_audio_layout_config *output)</div><div class='add'>+{</div><div class='add'>+	memset(output, 0, sizeof(struct dp_audio_layout_config));</div><div class='add'>+</div><div class='add'>+	/* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP,</div><div class='add'>+	 * with each layout being the same size (8ch layout).</div><div class='add'>+	 */</div><div class='add'>+	if (encoding == DP_8b_10b_ENCODING) {</div><div class='add'>+		if (channel_count == 2) {</div><div class='add'>+			output-&gt;layouts_per_sample_denom = 4;</div><div class='add'>+			output-&gt;symbols_per_layout = 40;</div><div class='add'>+			output-&gt;max_layouts_per_audio_sdp = 1;</div><div class='add'>+		} else if (channel_count == 8 || channel_count == 6) {</div><div class='add'>+			output-&gt;layouts_per_sample_denom = 1;</div><div class='add'>+			output-&gt;symbols_per_layout = 40;</div><div class='add'>+			output-&gt;max_layouts_per_audio_sdp = 1;</div><div class='add'>+		}</div><div class='add'>+	} else if (encoding == DP_128b_132b_ENCODING) {</div><div class='add'>+		if (channel_count == 2) {</div><div class='add'>+			output-&gt;layouts_per_sample_denom = 4;</div><div class='add'>+			output-&gt;symbols_per_layout = 10;</div><div class='add'>+			output-&gt;max_layouts_per_audio_sdp = 1;</div><div class='add'>+		} else if (channel_count == 8 || channel_count == 6) {</div><div class='add'>+			output-&gt;layouts_per_sample_denom = 1;</div><div class='add'>+			output-&gt;symbols_per_layout = 10;</div><div class='add'>+			output-&gt;max_layouts_per_audio_sdp = 1;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t get_av_stream_map_lane_count(</div><div class='add'>+	enum dp_link_encoding encoding,</div><div class='add'>+	enum dc_lane_count lane_count,</div><div class='add'>+	bool is_mst)</div><div class='add'>+{</div><div class='add'>+	uint32_t av_stream_map_lane_count = 0;</div><div class='add'>+</div><div class='add'>+	if (encoding == DP_8b_10b_ENCODING) {</div><div class='add'>+		if (!is_mst)</div><div class='add'>+			av_stream_map_lane_count = lane_count;</div><div class='add'>+		else</div><div class='add'>+			av_stream_map_lane_count = 4;</div><div class='add'>+	} else if (encoding == DP_128b_132b_ENCODING) {</div><div class='add'>+		av_stream_map_lane_count = 4;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ASSERT(av_stream_map_lane_count != 0);</div><div class='add'>+</div><div class='add'>+	return av_stream_map_lane_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t get_audio_sdp_overhead(</div><div class='add'>+	enum dp_link_encoding encoding,</div><div class='add'>+	enum dc_lane_count lane_count,</div><div class='add'>+	bool is_mst)</div><div class='add'>+{</div><div class='add'>+	uint32_t audio_sdp_overhead = 0;</div><div class='add'>+</div><div class='add'>+	if (encoding == DP_8b_10b_ENCODING) {</div><div class='add'>+		if (is_mst)</div><div class='add'>+			audio_sdp_overhead = 16; /* 4 * 2 + 8 */</div><div class='add'>+		else</div><div class='add'>+			audio_sdp_overhead = lane_count * 2 + 8;</div><div class='add'>+	} else if (encoding == DP_128b_132b_ENCODING) {</div><div class='add'>+		audio_sdp_overhead = 10; /* 4 x 2.5 */</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* Include dp overheads */</div><div class='del'>-	for (uint8_t i = 0; i &lt; num_dpias; ++i) {</div><div class='del'>-		int dp_overhead = 0;</div><div class='add'>+	ASSERT(audio_sdp_overhead != 0);</div><div class='ctx'> </div><div class='del'>-		dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(dpia_link[i]);</div><div class='del'>-		bw_needed[i] += dp_overhead;</div><div class='add'>+	return audio_sdp_overhead;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST.</div><div class='add'>+ */</div><div class='add'>+static uint32_t calculate_overhead_hblank_bw_in_symbols(</div><div class='add'>+	uint32_t max_slice_h)</div><div class='add'>+{</div><div class='add'>+	uint32_t overhead_hblank_bw = 0; /* in stream symbols */</div><div class='add'>+</div><div class='add'>+	overhead_hblank_bw += max_slice_h * 4; /* EOC overhead */</div><div class='add'>+	overhead_hblank_bw += 12; /* Main link overhead (VBID, BS/BE) */</div><div class='add'>+</div><div class='add'>+	return overhead_hblank_bw;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dp_required_hblank_size_bytes(</div><div class='add'>+	const struct dc_link *link,</div><div class='add'>+	struct dp_audio_bandwidth_params *audio_params)</div><div class='add'>+{</div><div class='add'>+	/* Main logic from dce_audio is duplicated here, with the main</div><div class='add'>+	 * difference being:</div><div class='add'>+	 * - Pre-determined lane count of 4</div><div class='add'>+	 * - Assumed 16 dsc slices for worst case</div><div class='add'>+	 * - Assumed SDP split disabled for worst case</div><div class='add'>+	 * TODO: Unify logic from dce_audio to prevent duplicated logic.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	const struct dc_crtc_timing *timing = audio_params-&gt;crtc_timing;</div><div class='add'>+	const uint32_t channel_count = audio_params-&gt;channel_count;</div><div class='add'>+	const uint32_t sample_rate_hz = audio_params-&gt;sample_rate_hz;</div><div class='add'>+	const enum dp_link_encoding link_encoding = audio_params-&gt;link_encoding;</div><div class='add'>+</div><div class='add'>+	// 8b/10b MST and 128b/132b are always 4 logical lanes.</div><div class='add'>+	const uint32_t lane_count = 4;</div><div class='add'>+	const bool is_mst = (link-&gt;connector_signal == SIGNAL_TYPE_DISPLAY_PORT);</div><div class='add'>+	// Maximum slice count is with ODM 4:1, 4 slices per DSC</div><div class='add'>+	const uint32_t max_slices_h = 16;</div><div class='add'>+</div><div class='add'>+	const uint32_t av_stream_map_lane_count = get_av_stream_map_lane_count(</div><div class='add'>+			link_encoding, lane_count, is_mst);</div><div class='add'>+	const uint32_t audio_sdp_overhead = get_audio_sdp_overhead(</div><div class='add'>+			link_encoding, lane_count, is_mst);</div><div class='add'>+	struct dp_audio_layout_config layout_config;</div><div class='add'>+</div><div class='add'>+	if (link_encoding == DP_8b_10b_ENCODING &amp;&amp; link-&gt;connector_signal == SIGNAL_TYPE_DISPLAY_PORT)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	get_audio_layout_config(</div><div class='add'>+			channel_count, link_encoding, &amp;layout_config);</div><div class='add'>+</div><div class='add'>+	/* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */</div><div class='add'>+	struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100);</div><div class='add'>+	struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction(</div><div class='add'>+			timing-&gt;pix_clk_100hz, (long long)timing-&gt;h_total * 10);</div><div class='add'>+	struct fixed31_32 samples_per_line;</div><div class='add'>+	struct fixed31_32 layouts_per_line;</div><div class='add'>+	struct fixed31_32 symbols_per_sdp_max_layout;</div><div class='add'>+	struct fixed31_32 remainder;</div><div class='add'>+	uint32_t num_sdp_with_max_layouts;</div><div class='add'>+	uint32_t required_symbols_per_hblank;</div><div class='add'>+	uint32_t required_bytes_per_hblank = 0;</div><div class='add'>+</div><div class='add'>+	samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000);</div><div class='add'>+	samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz);</div><div class='add'>+	layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config.layouts_per_sample_denom);</div><div class='add'>+	// HBlank expansion usage assumes SDP split disabled to allow for worst case.</div><div class='add'>+	layouts_per_line = dc_fixpt_from_int(dc_fixpt_ceil(layouts_per_line));</div><div class='add'>+</div><div class='add'>+	num_sdp_with_max_layouts = dc_fixpt_floor(</div><div class='add'>+			dc_fixpt_div_int(layouts_per_line, layout_config.max_layouts_per_audio_sdp));</div><div class='add'>+	symbols_per_sdp_max_layout = dc_fixpt_from_int(</div><div class='add'>+			layout_config.max_layouts_per_audio_sdp * layout_config.symbols_per_layout);</div><div class='add'>+	symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead);</div><div class='add'>+	symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin);</div><div class='add'>+	required_symbols_per_hblank = num_sdp_with_max_layouts;</div><div class='add'>+	required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) /</div><div class='add'>+			av_stream_map_lane_count) *	av_stream_map_lane_count;</div><div class='add'>+</div><div class='add'>+	if (num_sdp_with_max_layouts !=	dc_fixpt_ceil(</div><div class='add'>+			dc_fixpt_div_int(layouts_per_line, layout_config.max_layouts_per_audio_sdp))) {</div><div class='add'>+		remainder = dc_fixpt_sub_int(layouts_per_line,</div><div class='add'>+				num_sdp_with_max_layouts * layout_config.max_layouts_per_audio_sdp);</div><div class='add'>+		remainder = dc_fixpt_mul_int(remainder, layout_config.symbols_per_layout);</div><div class='add'>+		remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead);</div><div class='add'>+		remainder = dc_fixpt_mul(remainder, audio_sdp_margin);</div><div class='add'>+		required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) /</div><div class='add'>+				av_stream_map_lane_count) * av_stream_map_lane_count;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return dpia_validate_usb4_bw(dpia_link, bw_needed, num_dpias);</div><div class='add'>+	required_symbols_per_hblank += calculate_overhead_hblank_bw_in_symbols(max_slices_h);</div><div class='add'>+</div><div class='add'>+	if (link_encoding == DP_8b_10b_ENCODING)</div><div class='add'>+		required_bytes_per_hblank = required_symbols_per_hblank; // 8 bits per 8b/10b symbol</div><div class='add'>+	else if (link_encoding == DP_128b_132b_ENCODING)</div><div class='add'>+		required_bytes_per_hblank = required_symbols_per_hblank * 4; // 32 bits per 128b/132b symbol</div><div class='add'>+</div><div class='add'>+	return required_bytes_per_hblank;</div><div class='ctx'> }</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.h b/drivers/gpu/drm/amd/display/dc/link/link_validation.h<br/>index 595fb05946e9..595774e76453 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/link_validation.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/link_validation.h</a></div><div class='hunk'>@@ -24,17 +24,22 @@</div><div class='ctx'>  */</div><div class='ctx'> #ifndef __LINK_VALIDATION_H__</div><div class='ctx'> #define __LINK_VALIDATION_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> enum dc_status link_validate_mode_timing(</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_link *link,</div><div class='ctx'> 		const struct dc_crtc_timing *timing);</div><div class='del'>-bool link_validate_dpia_bandwidth(</div><div class='del'>-		const struct dc_stream_state *stream,</div><div class='del'>-		const unsigned int num_streams);</div><div class='add'>+enum dc_status link_validate_dp_tunnel_bandwidth(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		const struct dc_state *new_ctx);</div><div class='ctx'> uint32_t dp_link_bandwidth_kbps(</div><div class='ctx'> 	const struct dc_link *link,</div><div class='ctx'> 	const struct dc_link_settings *link_settings);</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+uint32_t dp_required_hblank_size_bytes(</div><div class='add'>+	const struct dc_link *link,</div><div class='add'>+	struct dp_audio_bandwidth_params *audio_params);</div><div class='add'>+</div><div class='ctx'> #endif /* __LINK_VALIDATION_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c<br/>index c2d40979203e..5d2bcce2f669 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c</a></div><div class='hunk'>@@ -51,10 +51,6 @@ struct i2c_payloads {</div><div class='ctx'> 	struct vector payloads;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct aux_payloads {</div><div class='del'>-	struct vector payloads;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static bool i2c_payloads_create(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct i2c_payloads *payloads,</div><div class='hunk'>@@ -509,7 +505,7 @@ bool try_to_configure_aux_timeout(struct ddc_service *ddc,</div><div class='ctx'> 	bool result = false;</div><div class='ctx'> 	struct ddc *ddc_pin = ddc-&gt;ddc_pin;</div><div class='ctx'> </div><div class='del'>-	if ((ddc-&gt;link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='add'>+	if (((ddc-&gt;link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='ctx'> 			!ddc-&gt;link-&gt;dc-&gt;debug.disable_fixed_vs_aux_timeout_wa &amp;&amp;</div><div class='ctx'> 			ddc-&gt;ctx-&gt;dce_version == DCN_VERSION_3_1) {</div><div class='ctx'> 		/* Fixed VS workaround for AUX timeout */</div><div class='hunk'>@@ -553,7 +549,8 @@ void write_scdc_data(struct ddc_service *ddc_service,</div><div class='ctx'> 	/*Lower than 340 Scramble bit from SCDC caps*/</div><div class='ctx'> </div><div class='ctx'> 	if (ddc_service-&gt;link-&gt;local_sink &amp;&amp;</div><div class='del'>-		ddc_service-&gt;link-&gt;local_sink-&gt;edid_caps.panel_patch.skip_scdc_overwrite)</div><div class='add'>+		(ddc_service-&gt;link-&gt;local_sink-&gt;edid_caps.panel_patch.skip_scdc_overwrite ||</div><div class='add'>+		!ddc_service-&gt;link-&gt;local_sink-&gt;edid_caps.scdc_present))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	link_query_ddc_data(ddc_service, slave_address, &amp;offset,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h<br/>index a3e25e55bed6..d3e6f01a6a90 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #ifndef __DAL_DDC_SERVICE_H__</div><div class='ctx'> #define __DAL_DDC_SERVICE_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #define AUX_POWER_UP_WA_DELAY 500</div><div class='ctx'> #define I2C_OVER_AUX_DEFER_WA_DELAY 70</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c<br/>index 289f5d133342..ad90a0106938 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c</a></div><div class='hunk'>@@ -51,9 +51,10 @@</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "gpio_service_interface.h"</div><div class='ctx'> </div><div class='add'>+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */</div><div class='add'>+</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='del'>-#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */</div><div class='ctx'> </div><div class='ctx'> #ifndef MAX</div><div class='ctx'> #define MAX(X, Y) ((X) &gt; (Y) ? (X) : (Y))</div><div class='hunk'>@@ -157,6 +158,14 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)</div><div class='ctx'> 	return 0; // invalid value</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count)</div><div class='add'>+{</div><div class='add'>+	/* Calculate offset for LTTPR closest to DPTX which is highest in the chain</div><div class='add'>+	 * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1</div><div class='add'>+	 */</div><div class='add'>+	return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)</div><div class='ctx'> {</div><div class='ctx'> 	switch (bw) {</div><div class='hunk'>@@ -209,6 +218,16 @@ static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in</div><div class='ctx'> 	case 8100000:</div><div class='ctx'> 		link_rate = LINK_RATE_HIGH3;	// Rate_9 (HBR3)- 8.10 Gbps/Lane</div><div class='ctx'> 		break;</div><div class='add'>+	case 10000000:</div><div class='add'>+		link_rate = LINK_RATE_UHBR10;	// UHBR10 - 10.0 Gbps/Lane</div><div class='add'>+		break;</div><div class='add'>+	case 13500000:</div><div class='add'>+		link_rate = LINK_RATE_UHBR13_5;	// UHBR13.5 - 13.5 Gbps/Lane</div><div class='add'>+		break;</div><div class='add'>+	case 20000000:</div><div class='add'>+		link_rate = LINK_RATE_UHBR20;	// UHBR20 - 20.0 Gbps/Lane</div><div class='add'>+		break;</div><div class='add'>+</div><div class='ctx'> 	default:</div><div class='ctx'> 		link_rate = LINK_RATE_UNKNOWN;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -239,21 +258,23 @@ static uint32_t intersect_frl_link_bw_support(</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;</div><div class='ctx'> </div><div class='del'>-	// HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)</div><div class='del'>-	if (hdmi_encoded_link_bw.bits.FRL_MODE) {</div><div class='del'>-		if (hdmi_encoded_link_bw.bits.BW_48Gbps)</div><div class='del'>-			supported_bw_in_kbps = 48000000;</div><div class='del'>-		else if (hdmi_encoded_link_bw.bits.BW_40Gbps)</div><div class='del'>-			supported_bw_in_kbps = 40000000;</div><div class='del'>-		else if (hdmi_encoded_link_bw.bits.BW_32Gbps)</div><div class='del'>-			supported_bw_in_kbps = 32000000;</div><div class='del'>-		else if (hdmi_encoded_link_bw.bits.BW_24Gbps)</div><div class='del'>-			supported_bw_in_kbps = 24000000;</div><div class='del'>-		else if (hdmi_encoded_link_bw.bits.BW_18Gbps)</div><div class='del'>-			supported_bw_in_kbps = 18000000;</div><div class='del'>-		else if (hdmi_encoded_link_bw.bits.BW_9Gbps)</div><div class='del'>-			supported_bw_in_kbps = 9000000;</div><div class='del'>-	}</div><div class='add'>+	/* Skip checking FRL_MODE bit, as certain PCON will clear</div><div class='add'>+	 * it despite supporting the link BW indicated in the other bits.</div><div class='add'>+	 */</div><div class='add'>+	if (hdmi_encoded_link_bw.bits.BW_48Gbps)</div><div class='add'>+		supported_bw_in_kbps = 48000000;</div><div class='add'>+	else if (hdmi_encoded_link_bw.bits.BW_40Gbps)</div><div class='add'>+		supported_bw_in_kbps = 40000000;</div><div class='add'>+	else if (hdmi_encoded_link_bw.bits.BW_32Gbps)</div><div class='add'>+		supported_bw_in_kbps = 32000000;</div><div class='add'>+	else if (hdmi_encoded_link_bw.bits.BW_24Gbps)</div><div class='add'>+		supported_bw_in_kbps = 24000000;</div><div class='add'>+	else if (hdmi_encoded_link_bw.bits.BW_18Gbps)</div><div class='add'>+		supported_bw_in_kbps = 18000000;</div><div class='add'>+	else if (hdmi_encoded_link_bw.bits.BW_9Gbps)</div><div class='add'>+		supported_bw_in_kbps = 9000000;</div><div class='add'>+	else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)</div><div class='add'>+		supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */</div><div class='ctx'> </div><div class='ctx'> 	return supported_bw_in_kbps;</div><div class='ctx'> }</div><div class='hunk'>@@ -319,9 +340,12 @@ bool dp_is_fec_supported(const struct dc_link *link)</div><div class='ctx'> 	/* TODO - use asic cap instead of link_enc-&gt;features</div><div class='ctx'> 	 * we no longer know which link enc to use for this link before commit</div><div class='ctx'> 	 */</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='add'>+	struct resource_context *res_ctx = &amp;link-&gt;dc-&gt;current_state-&gt;res_ctx;</div><div class='add'>+	struct resource_pool *res_pool = link-&gt;dc-&gt;res_pool;</div><div class='add'>+	struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> 	ASSERT(link_enc);</div><div class='ctx'> </div><div class='ctx'> 	return (dc_is_dp_signal(link-&gt;connector_signal) &amp;&amp; link_enc &amp;&amp;</div><div class='hunk'>@@ -333,7 +357,9 @@ bool dp_should_enable_fec(const struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	bool force_disable = false;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;fec_state == dc_link_fec_enabled)</div><div class='add'>+	if (link-&gt;dc-&gt;debug.disable_fec)</div><div class='add'>+		force_disable = true;</div><div class='add'>+	else if (link-&gt;fec_state == dc_link_fec_enabled)</div><div class='ctx'> 		force_disable = false;</div><div class='ctx'> 	else if (link-&gt;connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &amp;&amp;</div><div class='ctx'> 			link-&gt;local_sink &amp;&amp;</div><div class='hunk'>@@ -360,10 +386,16 @@ bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> </div><div class='ctx'> bool dp_is_lttpr_present(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	return (dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &amp;&amp;</div><div class='add'>+	/* Some sink devices report invalid LTTPR revision, so don't validate against that cap */</div><div class='add'>+	uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='add'>+	bool is_lttpr_present = (lttpr_count &gt; 0 &amp;&amp;</div><div class='ctx'> 			link-&gt;dpcd_caps.lttpr_caps.max_lane_count &gt; 0 &amp;&amp;</div><div class='del'>-			link-&gt;dpcd_caps.lttpr_caps.max_lane_count &lt;= 4 &amp;&amp;</div><div class='del'>-			link-&gt;dpcd_caps.lttpr_caps.revision.raw &gt;= 0x14);</div><div class='add'>+			link-&gt;dpcd_caps.lttpr_caps.max_lane_count &lt;= 4);</div><div class='add'>+</div><div class='add'>+	if (lttpr_count &gt; 0 &amp;&amp; !is_lttpr_present)</div><div class='add'>+		DC_LOG_ERROR("LTTPR count is nonzero but invalid lane count reported. Assuming no LTTPR present.\n");</div><div class='add'>+</div><div class='add'>+	return is_lttpr_present;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* in DP compliance test, DPR-120 may have</div><div class='hunk'>@@ -394,9 +426,39 @@ static enum dc_link_rate get_link_rate_from_max_link_bw(</div><div class='ctx'> 	return link_rate;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum dc_lane_count get_lttpr_max_lane_count(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	enum dc_lane_count lttpr_max_lane_count = LANE_COUNT_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dpcd_caps.lttpr_caps.max_lane_count &lt;= LANE_COUNT_DP_MAX)</div><div class='add'>+		lttpr_max_lane_count = link-&gt;dpcd_caps.lttpr_caps.max_lane_count;</div><div class='add'>+</div><div class='add'>+	/* if bw_allocation is enabled and nrd_max_lane_count is set, use it */</div><div class='add'>+	if (link-&gt;dpia_bw_alloc_config.bw_alloc_enabled &amp;&amp;</div><div class='add'>+			link-&gt;dpia_bw_alloc_config.nrd_max_lane_count &gt; 0)</div><div class='add'>+		lttpr_max_lane_count = link-&gt;dpia_bw_alloc_config.nrd_max_lane_count;</div><div class='add'>+</div><div class='add'>+	return lttpr_max_lane_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	enum dc_link_rate lttpr_max_link_rate = link-&gt;dpcd_caps.lttpr_caps.max_link_rate;</div><div class='add'>+</div><div class='add'>+	enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	switch (link-&gt;dpcd_caps.lttpr_caps.max_link_rate) {</div><div class='add'>+	case LINK_RATE_LOW:</div><div class='add'>+	case LINK_RATE_HIGH:</div><div class='add'>+	case LINK_RATE_HIGH2:</div><div class='add'>+	case LINK_RATE_HIGH3:</div><div class='add'>+		lttpr_max_link_rate = link-&gt;dpcd_caps.lttpr_caps.max_link_rate;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* if bw_allocation is enabled and nrd_max_link_rate is set, use it */</div><div class='add'>+	if (link-&gt;dpia_bw_alloc_config.bw_alloc_enabled &amp;&amp;</div><div class='add'>+			link-&gt;dpia_bw_alloc_config.nrd_max_link_rate &gt; 0)</div><div class='add'>+		lttpr_max_link_rate = link-&gt;dpia_bw_alloc_config.nrd_max_link_rate;</div><div class='ctx'> </div><div class='ctx'> 	if (link-&gt;dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)</div><div class='ctx'> 		lttpr_max_link_rate = LINK_RATE_UHBR20;</div><div class='hunk'>@@ -528,13 +590,30 @@ static enum dc_link_rate increase_link_rate(struct dc_link *link,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void increase_edp_link_rate(struct dc_link *link,</div><div class='add'>+		struct dc_link_settings *current_link_setting)</div><div class='add'>+{</div><div class='add'>+	if (current_link_setting-&gt;use_link_rate_set) {</div><div class='add'>+		if (current_link_setting-&gt;link_rate_set &lt; link-&gt;dpcd_caps.edp_supported_link_rates_count) {</div><div class='add'>+			current_link_setting-&gt;link_rate_set++;</div><div class='add'>+			current_link_setting-&gt;link_rate =</div><div class='add'>+				link-&gt;dpcd_caps.edp_supported_link_rates[current_link_setting-&gt;link_rate_set];</div><div class='add'>+		} else {</div><div class='add'>+			current_link_setting-&gt;use_link_rate_set = false;</div><div class='add'>+			current_link_setting-&gt;link_rate = LINK_RATE_UHBR10;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		current_link_setting-&gt;link_rate = increase_link_rate(link, current_link_setting-&gt;link_rate);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool decide_fallback_link_setting_max_bw_policy(</div><div class='ctx'> 		struct dc_link *link,</div><div class='ctx'> 		const struct dc_link_settings *max,</div><div class='ctx'> 		struct dc_link_settings *cur,</div><div class='ctx'> 		enum link_training_result training_result)</div><div class='ctx'> {</div><div class='del'>-	uint8_t cur_idx = 0, next_idx;</div><div class='add'>+	uint32_t cur_idx = 0, next_idx;</div><div class='ctx'> 	bool found = false;</div><div class='ctx'> </div><div class='ctx'> 	if (training_result == LINK_TRAINING_ABORT)</div><div class='hunk'>@@ -746,14 +825,7 @@ bool edp_decide_link_settings(struct dc_link *link,</div><div class='ctx'> 					increase_lane_count(</div><div class='ctx'> 							current_link_setting.lane_count);</div><div class='ctx'> 		} else {</div><div class='del'>-			if (current_link_setting.link_rate_set &lt; link-&gt;dpcd_caps.edp_supported_link_rates_count) {</div><div class='del'>-				current_link_setting.link_rate_set++;</div><div class='del'>-				current_link_setting.link_rate =</div><div class='del'>-					link-&gt;dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];</div><div class='del'>-				current_link_setting.lane_count =</div><div class='del'>-									initial_link_setting.lane_count;</div><div class='del'>-			} else</div><div class='del'>-				break;</div><div class='add'>+			increase_edp_link_rate(link, &amp;current_link_setting);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -805,9 +877,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link,</div><div class='ctx'> 			if (policy) {</div><div class='ctx'> 				/* minimize lane */</div><div class='ctx'> 				if (current_link_setting.link_rate &lt; max_link_rate) {</div><div class='del'>-					current_link_setting.link_rate =</div><div class='del'>-							increase_link_rate(link,</div><div class='del'>-									current_link_setting.link_rate);</div><div class='add'>+					increase_edp_link_rate(link, &amp;current_link_setting);</div><div class='ctx'> 				} else {</div><div class='ctx'> 					if (current_link_setting.lane_count &lt;</div><div class='ctx'> 									link-&gt;verified_link_cap.lane_count) {</div><div class='hunk'>@@ -826,9 +896,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link,</div><div class='ctx'> 							increase_lane_count(</div><div class='ctx'> 									current_link_setting.lane_count);</div><div class='ctx'> 				} else {</div><div class='del'>-					current_link_setting.link_rate =</div><div class='del'>-							increase_link_rate(link,</div><div class='del'>-									current_link_setting.link_rate);</div><div class='add'>+					increase_edp_link_rate(link, &amp;current_link_setting);</div><div class='ctx'> 					current_link_setting.lane_count =</div><div class='ctx'> 							initial_link_setting.lane_count;</div><div class='ctx'> 				}</div><div class='hunk'>@@ -861,18 +929,15 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link,</div><div class='ctx'> 		}</div><div class='ctx'> 		if (policy) {</div><div class='ctx'> 			/* minimize lane */</div><div class='del'>-			if (current_link_setting.link_rate_set &lt;</div><div class='del'>-					link-&gt;dpcd_caps.edp_supported_link_rates_count</div><div class='del'>-					&amp;&amp; current_link_setting.link_rate &lt; max_link_rate) {</div><div class='del'>-				current_link_setting.link_rate_set++;</div><div class='del'>-				current_link_setting.link_rate =</div><div class='del'>-					link-&gt;dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];</div><div class='add'>+			if (current_link_setting.link_rate &lt; max_link_rate) {</div><div class='add'>+				increase_edp_link_rate(link, &amp;current_link_setting);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				if (current_link_setting.lane_count &lt; link-&gt;verified_link_cap.lane_count) {</div><div class='ctx'> 					current_link_setting.lane_count =</div><div class='ctx'> 							increase_lane_count(</div><div class='ctx'> 									current_link_setting.lane_count);</div><div class='ctx'> 					current_link_setting.link_rate_set = initial_link_setting.link_rate_set;</div><div class='add'>+					current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set;</div><div class='ctx'> 					current_link_setting.link_rate =</div><div class='ctx'> 						link-&gt;dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];</div><div class='ctx'> 				} else</div><div class='hunk'>@@ -886,13 +951,8 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link,</div><div class='ctx'> 						increase_lane_count(</div><div class='ctx'> 								current_link_setting.lane_count);</div><div class='ctx'> 			} else {</div><div class='del'>-				if (current_link_setting.link_rate_set &lt; link-&gt;dpcd_caps.edp_supported_link_rates_count) {</div><div class='del'>-					current_link_setting.link_rate_set++;</div><div class='del'>-					current_link_setting.link_rate =</div><div class='del'>-						link-&gt;dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];</div><div class='del'>-					current_link_setting.lane_count =</div><div class='del'>-						initial_link_setting.lane_count;</div><div class='del'>-				} else</div><div class='add'>+				increase_edp_link_rate(link, &amp;current_link_setting);</div><div class='add'>+				if (current_link_setting.link_rate == LINK_RATE_UNKNOWN)</div><div class='ctx'> 					break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -914,22 +974,21 @@ bool link_decide_link_settings(struct dc_stream_state *stream,</div><div class='ctx'> </div><div class='ctx'> 	memset(link_setting, 0, sizeof(*link_setting));</div><div class='ctx'> </div><div class='del'>-	/* if preferred is specified through AMDDP, use it, if it's enough</div><div class='del'>-	 * to drive the mode</div><div class='del'>-	 */</div><div class='del'>-	if (link-&gt;preferred_link_setting.lane_count !=</div><div class='del'>-			LANE_COUNT_UNKNOWN &amp;&amp;</div><div class='del'>-			link-&gt;preferred_link_setting.link_rate !=</div><div class='del'>-					LINK_RATE_UNKNOWN) {</div><div class='add'>+	if (dc_is_dp_signal(stream-&gt;signal)  &amp;&amp;</div><div class='add'>+			link-&gt;preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &amp;&amp;</div><div class='add'>+			link-&gt;preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {</div><div class='add'>+		/* if preferred is specified through AMDDP, use it, if it's enough</div><div class='add'>+		 * to drive the mode</div><div class='add'>+		 */</div><div class='ctx'> 		*link_setting = link-&gt;preferred_link_setting;</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* MST doesn't perform link training for now</div><div class='del'>-	 * TODO: add MST specific link training routine</div><div class='del'>-	 */</div><div class='del'>-	if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='add'>+	} else if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='add'>+		/* MST doesn't perform link training for now</div><div class='add'>+		 * TODO: add MST specific link training routine</div><div class='add'>+		 */</div><div class='ctx'> 		decide_mst_link_settings(link, link_setting);</div><div class='add'>+	} else if (stream-&gt;signal == SIGNAL_TYPE_VIRTUAL) {</div><div class='add'>+		link_setting-&gt;lane_count = LANE_COUNT_FOUR;</div><div class='add'>+		link_setting-&gt;link_rate = LINK_RATE_HIGH3;</div><div class='ctx'> 	} else if (link-&gt;connector_signal == SIGNAL_TYPE_EDP) {</div><div class='ctx'> 		/* enable edp link optimization for DSC eDP case */</div><div class='ctx'> 		if (stream-&gt;timing.flags.DSC) {</div><div class='hunk'>@@ -992,7 +1051,7 @@ enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link</div><div class='ctx'> </div><div class='ctx'> static void read_dp_device_vendor_id(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	struct dp_device_vendor_id dp_id;</div><div class='add'>+	struct dp_device_vendor_id dp_id = {0};</div><div class='ctx'> </div><div class='ctx'> 	/* read IEEE branch device id */</div><div class='ctx'> 	core_link_read_dpcd(</div><div class='hunk'>@@ -1054,6 +1113,48 @@ static enum dc_status wake_up_aux_channel(struct dc_link *link)</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void read_and_intersect_post_frl_lt_status(</div><div class='add'>+	struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0};</div><div class='add'>+	union hdmi_tx_link_status hdmi_tx_link_status = {0};</div><div class='add'>+	union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0};</div><div class='add'>+</div><div class='add'>+	/* Check if dongle supports regulated autonomous mode. */</div><div class='add'>+	core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS,</div><div class='add'>+		&amp;autonomous_mode_caps.raw, sizeof(autonomous_mode_caps));</div><div class='add'>+</div><div class='add'>+	link-&gt;dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support =</div><div class='add'>+			autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) {</div><div class='add'>+		DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__);</div><div class='add'>+</div><div class='add'>+		core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS,</div><div class='add'>+				&amp;hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Intersect reported max link bw support with the supported link rate post FRL link training</div><div class='add'>+	if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,</div><div class='add'>+			&amp;hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {</div><div class='add'>+</div><div class='add'>+		if (link-&gt;dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support &amp;&amp;</div><div class='add'>+				(!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS ||</div><div class='add'>+						!hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) {</div><div class='add'>+			DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__);</div><div class='add'>+</div><div class='add'>+			/* Link training not finished, ignore values from this DPCD reg. */</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(</div><div class='add'>+				link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,</div><div class='add'>+				hdmi_encoded_link_bw);</div><div class='add'>+		DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,</div><div class='add'>+			link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void get_active_converter_info(</div><div class='ctx'> 	uint8_t data, struct dc_link *link)</div><div class='ctx'> {</div><div class='hunk'>@@ -1087,7 +1188,7 @@ static void get_active_converter_info(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_11) {</div><div class='del'>-		uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/</div><div class='add'>+		uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/</div><div class='ctx'> 		union dwnstream_port_caps_byte0 *port_caps =</div><div class='ctx'> 			(union dwnstream_port_caps_byte0 *)det_caps;</div><div class='ctx'> 		if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,</div><div class='hunk'>@@ -1142,19 +1243,12 @@ static void get_active_converter_info(</div><div class='ctx'> 							hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);</div><div class='ctx'> </div><div class='ctx'> 					if (link-&gt;dc-&gt;caps.dp_hdmi21_pcon_support) {</div><div class='del'>-						union hdmi_encoded_link_bw hdmi_encoded_link_bw;</div><div class='ctx'> </div><div class='ctx'> 						link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =</div><div class='ctx'> 								link_bw_kbps_from_raw_frl_link_rate_data(</div><div class='ctx'> 										hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);</div><div class='ctx'> </div><div class='del'>-						// Intersect reported max link bw support with the supported link rate post FRL link training</div><div class='del'>-						if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,</div><div class='del'>-								&amp;hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {</div><div class='del'>-							link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(</div><div class='del'>-									link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,</div><div class='del'>-									hdmi_encoded_link_bw);</div><div class='del'>-						}</div><div class='add'>+						read_and_intersect_post_frl_lt_status(link);</div><div class='ctx'> </div><div class='ctx'> 						if (link-&gt;dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps &gt; 0)</div><div class='ctx'> 							link-&gt;dpcd_caps.dongle_caps.extendedCapValid = true;</div><div class='hunk'>@@ -1172,7 +1266,7 @@ static void get_active_converter_info(</div><div class='ctx'> 	set_dongle_type(link-&gt;ddc, link-&gt;dpcd_caps.dongle_type);</div><div class='ctx'> </div><div class='ctx'> 	{</div><div class='del'>-		struct dp_sink_hw_fw_revision dp_hw_fw_revision;</div><div class='add'>+		struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0};</div><div class='ctx'> </div><div class='ctx'> 		core_link_read_dpcd(</div><div class='ctx'> 			link,</div><div class='hunk'>@@ -1188,6 +1282,13 @@ static void get_active_converter_info(</div><div class='ctx'> 			dp_hw_fw_revision.ieee_fw_rev,</div><div class='ctx'> 			sizeof(dp_hw_fw_revision.ieee_fw_rev));</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	core_link_read_dpcd(</div><div class='add'>+		link,</div><div class='add'>+		DP_BRANCH_VENDOR_SPECIFIC_START,</div><div class='add'>+		(uint8_t *)link-&gt;dpcd_caps.branch_vendor_specific_data,</div><div class='add'>+		sizeof(link-&gt;dpcd_caps.branch_vendor_specific_data));</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_14 &amp;&amp;</div><div class='ctx'> 			link-&gt;dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {</div><div class='ctx'> 		union dp_dfp_cap_ext dfp_cap_ext;</div><div class='hunk'>@@ -1242,7 +1343,7 @@ static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> bool dp_overwrite_extended_receiver_cap(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	uint8_t dpcd_data[16];</div><div class='add'>+	uint8_t dpcd_data[16] = {0};</div><div class='ctx'> 	uint32_t read_dpcd_retry_cnt = 3;</div><div class='ctx'> 	enum dc_status status = DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	union dp_downstream_port_present ds_port = { 0 };</div><div class='hunk'>@@ -1309,6 +1410,21 @@ void dpcd_set_source_specific_data(struct dc_link *link)</div><div class='ctx'> 		struct dpcd_amd_signature amd_signature = {0};</div><div class='ctx'> 		struct dpcd_amd_device_id amd_device_id = {0};</div><div class='ctx'> </div><div class='add'>+		if (link-&gt;is_dds) {</div><div class='add'>+			uint8_t dpcd_dp_edp_backlight_mode = 0;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Write 0 to bits 0:1 for dp_edp_backlight_mode_set register</div><div class='add'>+			 * if platform is DDS</div><div class='add'>+			 */</div><div class='add'>+			core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,</div><div class='add'>+				&amp;dpcd_dp_edp_backlight_mode, sizeof(uint8_t));</div><div class='add'>+			dpcd_dp_edp_backlight_mode &amp;= ~0x3;</div><div class='add'>+</div><div class='add'>+			core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,</div><div class='add'>+				&amp;dpcd_dp_edp_backlight_mode, sizeof(uint8_t));</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		amd_device_id.device_id_byte1 =</div><div class='ctx'> 				(uint8_t)(link-&gt;ctx-&gt;asic_id.chip_id);</div><div class='ctx'> 		amd_device_id.device_id_byte2 =</div><div class='hunk'>@@ -1408,7 +1524,7 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)</div><div class='ctx'> </div><div class='ctx'> static void retrieve_cable_id(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	union dp_cable_id usbc_cable_id;</div><div class='add'>+	union dp_cable_id usbc_cable_id = {0};</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;dpcd_caps.cable_id.raw = 0;</div><div class='ctx'> 	core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,</div><div class='hunk'>@@ -1431,8 +1547,8 @@ bool read_is_mst_supported(struct dc_link *link)</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rev.raw  = 0;</div><div class='del'>-	cap.raw  = 0;</div><div class='add'>+	rev.raw = 0;</div><div class='add'>+	cap.raw = 0;</div><div class='ctx'> </div><div class='ctx'> 	st = core_link_read_dpcd(link, DP_DPCD_REV, &amp;rev.raw,</div><div class='ctx'> 			sizeof(rev));</div><div class='hunk'>@@ -1464,6 +1580,10 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;dpcd_sink_ext_caps.raw = dpcd_data;</div><div class='add'>+	if (link-&gt;is_dds &amp;&amp; !link-&gt;dpcd_sink_ext_caps.bits.oled) {</div><div class='add'>+		link-&gt;dpcd_sink_ext_caps.raw = 0;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &amp;edp_general_cap2, 1) != DC_OK)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -1475,9 +1595,11 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	uint8_t lttpr_dpcd_data[8];</div><div class='add'>+	uint8_t lttpr_dpcd_data[10] = {0};</div><div class='ctx'> 	enum dc_status status;</div><div class='ctx'> 	bool is_lttpr_present;</div><div class='add'>+	uint32_t lttpr_count;</div><div class='add'>+	uint32_t closest_lttpr_offset;</div><div class='ctx'> </div><div class='ctx'> 	/* Logic to determine LTTPR support*/</div><div class='ctx'> 	bool vbios_lttpr_interop = link-&gt;dc-&gt;caps.vbios_lttpr_aware;</div><div class='hunk'>@@ -1525,22 +1647,54 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)</div><div class='ctx'> 			lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -</div><div class='ctx'> 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];</div><div class='ctx'> </div><div class='add'>+	link-&gt;dpcd_caps.lttpr_caps.alpm.raw =</div><div class='add'>+			lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES -</div><div class='add'>+							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];</div><div class='add'>+</div><div class='add'>+	lttpr_count = dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='add'>+</div><div class='ctx'> 	/* If this chip cap is set, at least one retimer must exist in the chain</div><div class='ctx'> 	 * Override count to 1 if we receive a known bad count (0 or an invalid value) */</div><div class='del'>-	if ((link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='del'>-			(dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {</div><div class='del'>-		ASSERT(0);</div><div class='add'>+	if (((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='add'>+			lttpr_count == 0) {</div><div class='add'>+		/* If you see this message consistently, either the host platform has FIXED_VS flag</div><div class='add'>+		 * incorrectly configured or the sink device is returning an invalid count.</div><div class='add'>+		 */</div><div class='add'>+		DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",</div><div class='add'>+			     link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='ctx'> 		link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;</div><div class='add'>+		lttpr_count = 1;</div><div class='ctx'> 		DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */</div><div class='ctx'> 	is_lttpr_present = dp_is_lttpr_present(link);</div><div class='ctx'> </div><div class='del'>-	if (is_lttpr_present)</div><div class='add'>+	DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);</div><div class='add'>+</div><div class='add'>+	if (is_lttpr_present) {</div><div class='ctx'> 		CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");</div><div class='ctx'> </div><div class='del'>-	DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);</div><div class='add'>+		// Identify closest LTTPR to determine if workarounds required for known embedded LTTPR</div><div class='add'>+		closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count);</div><div class='add'>+</div><div class='add'>+		core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset),</div><div class='add'>+				link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui));</div><div class='add'>+		core_link_read_dpcd(link, (DP_LTTPR_DEVICE_ID + closest_lttpr_offset),</div><div class='add'>+				link-&gt;dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link-&gt;dpcd_caps.lttpr_caps.lttpr_device_id));</div><div class='add'>+</div><div class='add'>+		if (lttpr_count &gt; 1) {</div><div class='add'>+			CONN_DATA_DETECT(link, link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui),</div><div class='add'>+					"Closest LTTPR To Host's IEEE OUI: ");</div><div class='add'>+			CONN_DATA_DETECT(link, link-&gt;dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link-&gt;dpcd_caps.lttpr_caps.lttpr_device_id),</div><div class='add'>+					"Closest LTTPR To Host's LTTPR Device ID: ");</div><div class='add'>+		} else {</div><div class='add'>+			CONN_DATA_DETECT(link, link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui),</div><div class='add'>+					"LTTPR IEEE OUI: ");</div><div class='add'>+			CONN_DATA_DETECT(link, link-&gt;dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link-&gt;dpcd_caps.lttpr_caps.lttpr_device_id),</div><div class='add'>+					"LTTPR Device ID: ");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1559,7 +1713,7 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 	union edp_configuration_cap edp_config_cap;</div><div class='ctx'> 	union dp_downstream_port_present ds_port = { 0 };</div><div class='ctx'> 	enum dc_status status = DC_ERROR_UNEXPECTED;</div><div class='del'>-	uint32_t read_dpcd_retry_cnt = 3;</div><div class='add'>+	uint32_t read_dpcd_retry_cnt = 20;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;</div><div class='ctx'> 	const uint32_t post_oui_delay = 30; // 30ms</div><div class='hunk'>@@ -1590,19 +1744,25 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dp_is_lttpr_present(link))</div><div class='add'>+	if (dp_is_lttpr_present(link)) {</div><div class='ctx'> 		configure_lttpr_mode_transparent(link);</div><div class='ctx'> </div><div class='del'>-	/* Read DP tunneling information. */</div><div class='del'>-	status = dpcd_get_tunneling_device_data(link);</div><div class='add'>+		// Echo TOTAL_LTTPR_CNT back downstream</div><div class='add'>+		core_link_write_dpcd(</div><div class='add'>+				link,</div><div class='add'>+				DP_TOTAL_LTTPR_CNT,</div><div class='add'>+				&amp;link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt,</div><div class='add'>+				sizeof(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	dpcd_set_source_specific_data(link);</div><div class='del'>-	/* Sink may need to configure internals based on vendor, so allow some</div><div class='del'>-	 * time before proceeding with possibly vendor specific transactions</div><div class='del'>-	 */</div><div class='del'>-	msleep(post_oui_delay);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; read_dpcd_retry_cnt; i++) {</div><div class='add'>+		/*</div><div class='add'>+		 * Sink may need to configure internals based on vendor, so allow some</div><div class='add'>+		 * time before proceeding with possibly vendor specific transactions</div><div class='add'>+		 */</div><div class='add'>+		msleep(post_oui_delay);</div><div class='ctx'> 		status = core_link_read_dpcd(</div><div class='ctx'> 				link,</div><div class='ctx'> 				DP_DPCD_REV,</div><div class='hunk'>@@ -1668,7 +1828,7 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 		link-&gt;dpcd_caps.dprx_feature.raw = dpcd_dprx_data;</div><div class='ctx'> </div><div class='ctx'> 		if (status != DC_OK)</div><div class='del'>-			dm_error("%s: Read DPRX caps data failed.\n", __func__);</div><div class='add'>+			dm_error("%s: Read DPRX feature list failed.\n", __func__);</div><div class='ctx'> </div><div class='ctx'> 		/* AdaptiveSyncCapability  */</div><div class='ctx'> 		dpcd_dprx_data = 0;</div><div class='hunk'>@@ -1683,15 +1843,13 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 		link-&gt;dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;</div><div class='ctx'> </div><div class='ctx'> 		if (status != DC_OK)</div><div class='del'>-			dm_error("%s: Read DPRX caps data failed. Addr:%#x\n",</div><div class='add'>+			dm_error("%s: Read DPRX feature list_1 failed. Addr:%#x\n",</div><div class='ctx'> 					__func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> 	else {</div><div class='ctx'> 		link-&gt;dpcd_caps.dprx_feature.raw = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	/* Error condition checking...</div><div class='ctx'> 	 * It is impossible for Sink to report Max Lane Count = 0.</div><div class='ctx'> 	 * It is possible for Sink to report Max Link Rate = 0, if it is</div><div class='hunk'>@@ -1710,6 +1868,12 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 	link-&gt;dpcd_caps.is_mst_capable = read_is_mst_supported(link);</div><div class='ctx'> 	DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link-&gt;dpcd_caps.is_mst_capable));</div><div class='ctx'> </div><div class='add'>+	/* Some MST docks seem to NAK I2C writes to segment pointer with mot=0. */</div><div class='add'>+	if (link-&gt;dpcd_caps.is_mst_capable)</div><div class='add'>+		link-&gt;wa_flags.dp_mot_reset_segment = true;</div><div class='add'>+	else</div><div class='add'>+		link-&gt;wa_flags.dp_mot_reset_segment = false;</div><div class='add'>+</div><div class='ctx'> 	get_active_converter_info(ds_port.byte, link);</div><div class='ctx'> </div><div class='ctx'> 	dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));</div><div class='hunk'>@@ -1745,6 +1909,11 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 	link-&gt;test_pattern_enabled = false;</div><div class='ctx'> 	link-&gt;compliance_test_state.raw = 0;</div><div class='ctx'> </div><div class='add'>+	link-&gt;dpcd_caps.receive_port0_cap.raw[0] =</div><div class='add'>+			dpcd_data[DP_RECEIVE_PORT_0_CAP_0 - DP_DPCD_REV];</div><div class='add'>+	link-&gt;dpcd_caps.receive_port0_cap.raw[1] =</div><div class='add'>+			dpcd_data[DP_RECEIVE_PORT_0_BUFFER_SIZE - DP_DPCD_REV];</div><div class='add'>+</div><div class='ctx'> 	/* read sink count */</div><div class='ctx'> 	core_link_read_dpcd(link,</div><div class='ctx'> 			DP_SINK_COUNT,</div><div class='hunk'>@@ -1811,6 +1980,9 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 				DP_FEC_CAPABILITY,</div><div class='ctx'> 				&amp;link-&gt;dpcd_caps.fec_cap.raw,</div><div class='ctx'> 				sizeof(link-&gt;dpcd_caps.fec_cap.raw));</div><div class='add'>+		if (status != DC_OK)</div><div class='add'>+			DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_FEC_CAPABILITY) failed\n", __func__, __LINE__);</div><div class='add'>+</div><div class='ctx'> 		status = core_link_read_dpcd(</div><div class='ctx'> 				link,</div><div class='ctx'> 				DP_DSC_SUPPORT,</div><div class='hunk'>@@ -1833,6 +2005,9 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 					DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,</div><div class='ctx'> 					link-&gt;dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,</div><div class='ctx'> 					sizeof(link-&gt;dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));</div><div class='add'>+			if (status != DC_OK)</div><div class='add'>+				DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_DSC_BRANCH_OVERALL_THROUGHPUT_0) failed\n", __func__, __LINE__);</div><div class='add'>+</div><div class='ctx'> 			DC_LOG_DSC("DSC branch decoder capability is read at link %d", link-&gt;link_index);</div><div class='ctx'> 			DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",</div><div class='ctx'> 					link-&gt;dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);</div><div class='hunk'>@@ -1869,6 +2044,7 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 	if (link-&gt;dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {</div><div class='ctx'> 		DC_LOG_DP2("128b/132b encoding is supported at link %d", link-&gt;link_index);</div><div class='ctx'> </div><div class='add'>+		/* Read 128b/132b suppoerted link rates */</div><div class='ctx'> 		core_link_read_dpcd(link,</div><div class='ctx'> 				DP_128B132B_SUPPORTED_LINK_RATES,</div><div class='ctx'> 				&amp;link-&gt;dpcd_caps.dp_128b_132b_supported_link_rates.raw,</div><div class='hunk'>@@ -1911,6 +2087,21 @@ static bool retrieve_link_cap(struct dc_link *link)</div><div class='ctx'> 			DC_LOG_DP2("\tFEC aggregated error counters are supported");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	core_link_read_dpcd(link,</div><div class='add'>+			DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP,</div><div class='add'>+			link-&gt;dpcd_caps.max_uncompressed_pixel_rate_cap.raw,</div><div class='add'>+			sizeof(link-&gt;dpcd_caps.max_uncompressed_pixel_rate_cap.raw));</div><div class='add'>+</div><div class='add'>+	core_link_read_dpcd(link,</div><div class='add'>+			DP_PANEL_REPLAY_CAPABILITY_SUPPORT,</div><div class='add'>+			&amp;link-&gt;dpcd_caps.pr_caps_supported.raw,</div><div class='add'>+			sizeof(link-&gt;dpcd_caps.pr_caps_supported.raw));</div><div class='add'>+</div><div class='add'>+	/* Read DP tunneling information. */</div><div class='add'>+	status = dpcd_get_tunneling_device_data(link);</div><div class='add'>+	if (status != DC_OK)</div><div class='add'>+		DC_LOG_DP2("%s: Read DP tunneling device data failed.\n", __func__);</div><div class='add'>+</div><div class='ctx'> 	retrieve_cable_id(link);</div><div class='ctx'> 	dpcd_write_cable_id_to_dprx(link);</div><div class='ctx'> </div><div class='hunk'>@@ -1931,8 +2122,8 @@ void detect_edp_sink_caps(struct dc_link *link)</div><div class='ctx'> 	uint32_t entry;</div><div class='ctx'> 	uint32_t link_rate_in_khz;</div><div class='ctx'> 	enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;</div><div class='del'>-	uint8_t backlight_adj_cap;</div><div class='del'>-	uint8_t general_edp_cap;</div><div class='add'>+	uint8_t backlight_adj_cap = 0;</div><div class='add'>+	uint8_t general_edp_cap = 0;</div><div class='ctx'> </div><div class='ctx'> 	retrieve_link_cap(link);</div><div class='ctx'> 	link-&gt;dpcd_caps.edp_supported_link_rates_count = 0;</div><div class='hunk'>@@ -1968,13 +2159,13 @@ void detect_edp_sink_caps(struct dc_link *link)</div><div class='ctx'> 						&amp;backlight_adj_cap, sizeof(backlight_adj_cap));</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;dpcd_caps.dynamic_backlight_capable_edp =</div><div class='del'>-				(backlight_adj_cap &amp; DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;</div><div class='add'>+				(backlight_adj_cap &amp; DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true : false;</div><div class='ctx'> </div><div class='ctx'> 	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,</div><div class='ctx'> 						&amp;general_edp_cap, sizeof(general_edp_cap));</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;dpcd_caps.set_power_state_capable_edp =</div><div class='del'>-				(general_edp_cap &amp; DP_EDP_SET_POWER_CAP) ? true:false;</div><div class='add'>+				(general_edp_cap &amp; DP_EDP_SET_POWER_CAP) ? true : false;</div><div class='ctx'> </div><div class='ctx'> 	set_default_brightness_aux(link);</div><div class='ctx'> </div><div class='hunk'>@@ -2019,18 +2210,46 @@ void detect_edp_sink_caps(struct dc_link *link)</div><div class='ctx'> 	core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,</div><div class='ctx'> 			&amp;link-&gt;dpcd_caps.pr_info.max_deviation_line,</div><div class='ctx'> 			sizeof(link-&gt;dpcd_caps.pr_info.max_deviation_line));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * OLED Emission Rate info</div><div class='add'>+	 */</div><div class='add'>+	if (link-&gt;dpcd_sink_ext_caps.bits.emission_output)</div><div class='add'>+		core_link_read_dpcd(link, DP_SINK_EMISSION_RATE,</div><div class='add'>+				(uint8_t *)&amp;link-&gt;dpcd_caps.edp_oled_emission_rate,</div><div class='add'>+				sizeof(link-&gt;dpcd_caps.edp_oled_emission_rate));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Read Multi-SST (Single Stream Transport) capability</div><div class='add'>+	 * for eDP version 1.4 or higher.</div><div class='add'>+	 */</div><div class='add'>+	if (link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DP_EDP_14)</div><div class='add'>+		core_link_read_dpcd(</div><div class='add'>+			link,</div><div class='add'>+			DP_EDP_MSO_LINK_CAPABILITIES,</div><div class='add'>+			(uint8_t *)&amp;link-&gt;dpcd_caps.mso_cap_sst_links_supported,</div><div class='add'>+			sizeof(link-&gt;dpcd_caps.mso_cap_sst_links_supported));</div><div class='add'>+	/*</div><div class='add'>+	 * Read eDP general capability 2</div><div class='add'>+	 */</div><div class='add'>+	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2,</div><div class='add'>+			(uint8_t *)&amp;link-&gt;dpcd_caps.dp_edp_general_cap_2,</div><div class='add'>+			sizeof(link-&gt;dpcd_caps.dp_edp_general_cap_2));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='add'>+	struct resource_context *res_ctx = &amp;link-&gt;dc-&gt;current_state-&gt;res_ctx;</div><div class='add'>+	struct resource_pool *res_pool = link-&gt;dc-&gt;res_pool;</div><div class='add'>+	struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);</div><div class='ctx'> </div><div class='ctx'> 	if (!max_link_enc_cap) {</div><div class='ctx'> 		DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> 	ASSERT(link_enc);</div><div class='ctx'> </div><div class='ctx'> 	if (link_enc &amp;&amp; link_enc-&gt;funcs-&gt;get_max_link_cap) {</div><div class='hunk'>@@ -2056,12 +2275,16 @@ const struct dc_link_settings *dp_get_verified_link_cap(</div><div class='ctx'> struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_link_settings max_link_cap = {0};</div><div class='add'>+	enum dc_lane_count lttpr_max_lane_count;</div><div class='ctx'> 	enum dc_link_rate lttpr_max_link_rate;</div><div class='ctx'> 	enum dc_link_rate cable_max_link_rate;</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='del'>-</div><div class='add'>+	struct resource_context *res_ctx = &amp;link-&gt;dc-&gt;current_state-&gt;res_ctx;</div><div class='add'>+	struct resource_pool *res_pool = link-&gt;dc-&gt;res_pool;</div><div class='add'>+	struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);</div><div class='add'>+	bool is_uhbr13_5_supported = true;</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> 	ASSERT(link_enc);</div><div class='ctx'> </div><div class='ctx'> 	/* get max link encoder capability */</div><div class='hunk'>@@ -2080,6 +2303,9 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)</div><div class='ctx'> 		max_link_cap.link_spread =</div><div class='ctx'> 				link-&gt;reported_link_cap.link_spread;</div><div class='ctx'> </div><div class='add'>+	if (!link-&gt;dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)</div><div class='add'>+		is_uhbr13_5_supported = false;</div><div class='add'>+</div><div class='ctx'> 	/* Lower link settings based on cable attributes</div><div class='ctx'> 	 * Cable ID is a DP2 feature to identify max certified link rate that</div><div class='ctx'> 	 * a cable can carry. The cable identification method requires both</div><div class='hunk'>@@ -2098,20 +2324,35 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)</div><div class='ctx'> 	cable_max_link_rate = get_cable_max_link_rate(link);</div><div class='ctx'> </div><div class='ctx'> 	if (!link-&gt;dc-&gt;debug.ignore_cable_id &amp;&amp;</div><div class='del'>-			cable_max_link_rate != LINK_RATE_UNKNOWN &amp;&amp;</div><div class='del'>-			cable_max_link_rate &lt; max_link_cap.link_rate)</div><div class='del'>-		max_link_cap.link_rate = cable_max_link_rate;</div><div class='add'>+			cable_max_link_rate != LINK_RATE_UNKNOWN) {</div><div class='add'>+		if (cable_max_link_rate &lt; max_link_cap.link_rate)</div><div class='add'>+			max_link_cap.link_rate = cable_max_link_rate;</div><div class='add'>+</div><div class='add'>+		if (!link-&gt;dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &amp;&amp;</div><div class='add'>+				link-&gt;dpcd_caps.cable_id.bits.CABLE_TYPE &gt;= 2)</div><div class='add'>+			is_uhbr13_5_supported = false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* account for lttpr repeaters cap</div><div class='ctx'> 	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (dp_is_lttpr_present(link)) {</div><div class='del'>-		if (link-&gt;dpcd_caps.lttpr_caps.max_lane_count &lt; max_link_cap.lane_count)</div><div class='del'>-			max_link_cap.lane_count = link-&gt;dpcd_caps.lttpr_caps.max_lane_count;</div><div class='del'>-		lttpr_max_link_rate = get_lttpr_max_link_rate(link);</div><div class='ctx'> </div><div class='del'>-		if (lttpr_max_link_rate &lt; max_link_cap.link_rate)</div><div class='del'>-			max_link_cap.link_rate = lttpr_max_link_rate;</div><div class='add'>+		/* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */</div><div class='add'>+		if (link-&gt;dpcd_caps.lttpr_caps.revision.raw &gt;= DPCD_REV_14) {</div><div class='add'>+			lttpr_max_lane_count = get_lttpr_max_lane_count(link);</div><div class='add'>+</div><div class='add'>+			if (lttpr_max_lane_count &lt; max_link_cap.lane_count)</div><div class='add'>+				max_link_cap.lane_count = lttpr_max_lane_count;</div><div class='add'>+</div><div class='add'>+			lttpr_max_link_rate = get_lttpr_max_link_rate(link);</div><div class='add'>+</div><div class='add'>+			if (lttpr_max_link_rate &lt; max_link_cap.link_rate)</div><div class='add'>+				max_link_cap.link_rate = lttpr_max_link_rate;</div><div class='add'>+</div><div class='add'>+			if (!link-&gt;dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)</div><div class='add'>+				is_uhbr13_5_supported = false;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",</div><div class='ctx'> 						__func__,</div><div class='hunk'>@@ -2119,6 +2360,10 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)</div><div class='ctx'> 						max_link_cap.link_rate);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 &amp;&amp;</div><div class='add'>+			!is_uhbr13_5_supported)</div><div class='add'>+		max_link_cap.link_rate = LINK_RATE_UHBR10;</div><div class='add'>+</div><div class='ctx'> 	if (link_dp_get_encoding_format(&amp;max_link_cap) == DP_128b_132b_ENCODING &amp;&amp;</div><div class='ctx'> 			link-&gt;dc-&gt;debug.disable_uhbr)</div><div class='ctx'> 		max_link_cap.link_rate = LINK_RATE_HIGH3;</div><div class='hunk'>@@ -2205,6 +2450,11 @@ bool dp_verify_link_cap_with_retries(</div><div class='ctx'> </div><div class='ctx'> 	dp_trace_detect_lt_init(link);</div><div class='ctx'> </div><div class='add'>+	DC_LOG_HW_LINK_TRAINING("%s: Link[%d]  LinkRate=0x%x LaneCount=%d",</div><div class='add'>+		__func__, link-&gt;link_index,</div><div class='add'>+		known_limit_link_setting-&gt;link_rate,</div><div class='add'>+		known_limit_link_setting-&gt;lane_count);</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;link_enc &amp;&amp; link-&gt;link_enc-&gt;features.flags.bits.DP_IS_USB_C &amp;&amp;</div><div class='ctx'> 			link-&gt;dc-&gt;debug.usbc_combo_phy_reset_wa)</div><div class='ctx'> 		apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);</div><div class='hunk'>@@ -2215,7 +2465,7 @@ bool dp_verify_link_cap_with_retries(</div><div class='ctx'> </div><div class='ctx'> 		memset(&amp;link-&gt;verified_link_cap, 0,</div><div class='ctx'> 				sizeof(struct dc_link_settings));</div><div class='del'>-		if (!link_detect_connection_type(link, &amp;type) || type == dc_connection_none) {</div><div class='add'>+		if (link-&gt;link_enc &amp;&amp; (!link_detect_connection_type(link, &amp;type) || type == dc_connection_none)) {</div><div class='ctx'> 			link-&gt;verified_link_cap = fail_safe_link_settings;</div><div class='ctx'> 			break;</div><div class='ctx'> 		} else if (dp_verify_link_cap(link, known_limit_link_setting, &amp;fail_count)) {</div><div class='hunk'>@@ -2227,12 +2477,25 @@ bool dp_verify_link_cap_with_retries(</div><div class='ctx'> 		} else {</div><div class='ctx'> 			link-&gt;verified_link_cap = last_verified_link_cap;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		/* For Dp tunneling link, a pending HPD means that we have a race condition between processing</div><div class='add'>+		 * current link and processing the pending HPD. Since the training is failed, we should just brak</div><div class='add'>+		 * the loop so that we have chance to process the pending HPD.</div><div class='add'>+		 */</div><div class='add'>+		if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp; link-&gt;is_hpd_pending)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='ctx'> 		fsleep(10 * 1000);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dp_trace_lt_fail_count_update(link, fail_count, true);</div><div class='ctx'> 	dp_trace_set_lt_end_timestamp(link, true);</div><div class='ctx'> </div><div class='add'>+	DC_LOG_HW_LINK_TRAINING("%s: Link[%d]  Exit. is_success=%d  fail_count=%d",</div><div class='add'>+		__func__, link-&gt;link_index,</div><div class='add'>+		success,</div><div class='add'>+		fail_count);</div><div class='add'>+</div><div class='ctx'> 	return success;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2297,3 +2560,40 @@ bool dp_is_sink_present(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	return present;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+uint8_t dp_get_lttpr_count(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	if (dp_is_lttpr_present(link))</div><div class='add'>+		return dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void edp_get_alpm_support(struct dc_link *link,</div><div class='add'>+	bool *auxless_support,</div><div class='add'>+	bool *auxwake_support)</div><div class='add'>+{</div><div class='add'>+	bool lttpr_present = dp_is_lttpr_present(link);</div><div class='add'>+</div><div class='add'>+	if (auxless_support == NULL || auxwake_support == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	*auxless_support = false;</div><div class='add'>+	*auxwake_support = false;</div><div class='add'>+</div><div class='add'>+	if (!dc_is_embedded_signal(link-&gt;connector_signal))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dpcd_caps.alpm_caps.bits.AUX_LESS_ALPM_CAP) {</div><div class='add'>+		if (lttpr_present) {</div><div class='add'>+			if (link-&gt;dpcd_caps.lttpr_caps.alpm.bits.AUX_LESS_ALPM_SUPPORTED)</div><div class='add'>+				*auxless_support = true;</div><div class='add'>+		} else</div><div class='add'>+			*auxless_support = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP) {</div><div class='add'>+		if (!lttpr_present)</div><div class='add'>+			*auxwake_support = true;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h<br/>index 8f0ce97f2362..6e17f72a752f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #ifndef __DC_LINK_DP_CAPABILITY_H__</div><div class='ctx'> #define __DC_LINK_DP_CAPABILITY_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> bool detect_dp_sink_caps(struct dc_link *link);</div><div class='ctx'> </div><div class='hunk'>@@ -48,6 +48,9 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link);</div><div class='ctx'> /* Convert PHY repeater count read from DPCD uint8_t. */</div><div class='ctx'> uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count);</div><div class='ctx'> </div><div class='add'>+/* Calculate embedded LTTPR address offset for vendor-specific behaviour */</div><div class='add'>+uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count);</div><div class='add'>+</div><div class='ctx'> bool dp_is_sink_present(struct dc_link *link);</div><div class='ctx'> </div><div class='ctx'> bool dp_is_lttpr_present(struct dc_link *link);</div><div class='hunk'>@@ -67,6 +70,7 @@ bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> /* Initialize output parameter lt_settings. */</div><div class='ctx'> void dp_decide_training_settings(</div><div class='ctx'> 	struct dc_link *link,</div><div class='add'>+	const struct link_resource *link_res,</div><div class='ctx'> 	const struct dc_link_settings *link_setting,</div><div class='ctx'> 	struct link_training_settings *lt_settings);</div><div class='ctx'> </div><div class='hunk'>@@ -104,4 +108,10 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);</div><div class='ctx'> </div><div class='ctx'> bool dp_overwrite_extended_receiver_cap(struct dc_link *link);</div><div class='ctx'> </div><div class='add'>+uint8_t dp_get_lttpr_count(struct dc_link *link);</div><div class='add'>+</div><div class='add'>+void edp_get_alpm_support(struct dc_link *link,</div><div class='add'>+	bool *auxless_support,</div><div class='add'>+	bool *auxwake_support);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_LINK_DP_CAPABILITY_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c<br/>index 6af42ba9885c..9b2f1a7da1d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c</a></div><div class='hunk'>@@ -59,22 +59,55 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link)</div><div class='ctx'> 			dpcd_dp_tun_data,</div><div class='ctx'> 			sizeof(dpcd_dp_tun_data));</div><div class='ctx'> </div><div class='del'>-	status = core_link_read_dpcd(</div><div class='del'>-			link,</div><div class='del'>-			DP_USB4_ROUTER_TOPOLOGY_ID,</div><div class='del'>-			dpcd_topology_data,</div><div class='del'>-			sizeof(dpcd_topology_data));</div><div class='add'>+	if (status != DC_OK)</div><div class='add'>+		goto err;</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw =</div><div class='ctx'> 			dpcd_dp_tun_data[DP_TUNNELING_CAPABILITIES_SUPPORT - DP_TUNNELING_CAPABILITIES_SUPPORT];</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling == false)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='ctx'> 	link-&gt;dpcd_caps.usb4_dp_tun_info.dpia_info.raw =</div><div class='ctx'> 			dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT];</div><div class='ctx'> 	link-&gt;dpcd_caps.usb4_dp_tun_info.usb4_driver_id =</div><div class='ctx'> 			dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT];</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc) {</div><div class='add'>+		status = core_link_read_dpcd(link, USB4_DRIVER_BW_CAPABILITY,</div><div class='add'>+				dpcd_dp_tun_data, 2);</div><div class='add'>+</div><div class='add'>+		if (status != DC_OK)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		link-&gt;dpcd_caps.usb4_dp_tun_info.driver_bw_cap.raw =</div><div class='add'>+			dpcd_dp_tun_data[USB4_DRIVER_BW_CAPABILITY - USB4_DRIVER_BW_CAPABILITY];</div><div class='add'>+		link-&gt;dpcd_caps.usb4_dp_tun_info.dpia_tunnel_info.raw =</div><div class='add'>+			dpcd_dp_tun_data[DP_IN_ADAPTER_TUNNEL_INFO - USB4_DRIVER_BW_CAPABILITY];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("%s: Link[%d]  DP tunneling support  (RouterId=%d  AdapterId=%d)  "</div><div class='add'>+			"DPIA_BW_Alloc_support=%d "</div><div class='add'>+			"CM_BW_Alloc_support=%d ",</div><div class='add'>+			__func__, link-&gt;link_index,</div><div class='add'>+			link-&gt;dpcd_caps.usb4_dp_tun_info.usb4_driver_id,</div><div class='add'>+			link-&gt;dpcd_caps.usb4_dp_tun_info.dpia_info.bits.dpia_num,</div><div class='add'>+			link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc,</div><div class='add'>+			link-&gt;dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);</div><div class='add'>+</div><div class='add'>+	status = core_link_read_dpcd(</div><div class='add'>+			link,</div><div class='add'>+			DP_USB4_ROUTER_TOPOLOGY_ID,</div><div class='add'>+			dpcd_topology_data,</div><div class='add'>+			sizeof(dpcd_topology_data));</div><div class='add'>+</div><div class='add'>+	if (status != DC_OK)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; DPCD_USB4_TOPOLOGY_ID_LEN; i++)</div><div class='ctx'> 		link-&gt;dpcd_caps.usb4_dp_tun_info.usb4_topology_id[i] = dpcd_topology_data[i];</div><div class='ctx'> </div><div class='add'>+err:</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -85,6 +118,7 @@ bool dpia_query_hpd_status(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	/* prepare QUERY_HPD command */</div><div class='ctx'> 	cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE;</div><div class='add'>+	cmd.query_hpd.header.payload_bytes = sizeof(cmd.query_hpd.data);</div><div class='ctx'> 	cmd.query_hpd.data.instance = link-&gt;link_id.enum_id - ENUM_ID_1;</div><div class='ctx'> 	cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA;</div><div class='ctx'> </div><div class='hunk'>@@ -112,3 +146,26 @@ bool dpia_query_hpd_status(struct dc_link *link)</div><div class='ctx'> 	return link-&gt;hpd_status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void link_decide_dp_tunnel_settings(struct dc_stream_state *stream,</div><div class='add'>+			struct dc_tunnel_settings *dp_tunnel_setting)</div><div class='add'>+{</div><div class='add'>+	struct dc_link *link = stream-&gt;link;</div><div class='add'>+</div><div class='add'>+	memset(dp_tunnel_setting, 0, sizeof(*dp_tunnel_setting));</div><div class='add'>+</div><div class='add'>+	if ((stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT) || (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {</div><div class='add'>+		dp_tunnel_setting-&gt;should_enable_dp_tunneling =</div><div class='add'>+					link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc</div><div class='add'>+				&amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {</div><div class='add'>+			dp_tunnel_setting-&gt;should_use_dp_bw_allocation = true;</div><div class='add'>+			dp_tunnel_setting-&gt;cm_id = link-&gt;dpcd_caps.usb4_dp_tun_info.usb4_driver_id &amp; 0x0F;</div><div class='add'>+			dp_tunnel_setting-&gt;group_id = link-&gt;dpcd_caps.usb4_dp_tun_info.dpia_tunnel_info.bits.group_id;</div><div class='add'>+			dp_tunnel_setting-&gt;estimated_bw = link-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='add'>+			dp_tunnel_setting-&gt;allocated_bw = link-&gt;dpia_bw_alloc_config.allocated_bw;</div><div class='add'>+			dp_tunnel_setting-&gt;bw_granularity = link-&gt;dpia_bw_alloc_config.bw_granularity;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h<br/>index 363f45a1a964..7cd03fa4892b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> #ifndef __DC_LINK_DPIA_H__</div><div class='ctx'> #define __DC_LINK_DPIA_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> /* Read tunneling device capability from DPCD and update link capability</div><div class='ctx'>  * accordingly.</div><div class='hunk'>@@ -38,4 +38,10 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link);</div><div class='ctx'>  * Returns true if HPD high.</div><div class='ctx'>  */</div><div class='ctx'> bool dpia_query_hpd_status(struct dc_link *link);</div><div class='add'>+</div><div class='add'>+/* Decide the DP tunneling settings based on the DPCD capabilities</div><div class='add'>+ */</div><div class='add'>+void link_decide_dp_tunnel_settings(struct dc_stream_state *stream,</div><div class='add'>+			struct dc_tunnel_settings *dp_tunnel_setting);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_LINK_DPIA_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c<br/>index 5491b707cec8..c958d3f600c8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c</a></div><div class='hunk'>@@ -24,7 +24,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> /*********************************************************************/</div><div class='del'>-//				USB4 DPIA BANDWIDTH ALLOCATION LOGIC</div><div class='add'>+// USB4 DPIA BANDWIDTH ALLOCATION LOGIC</div><div class='ctx'> /*********************************************************************/</div><div class='ctx'> #include "link_dp_dpia_bw.h"</div><div class='ctx'> #include "link_dpcd.h"</div><div class='hunk'>@@ -35,8 +35,10 @@</div><div class='ctx'> </div><div class='ctx'> #define Kbps_TO_Gbps (1000 * 1000)</div><div class='ctx'> </div><div class='add'>+#define MST_TIME_SLOT_COUNT 64</div><div class='add'>+</div><div class='ctx'> // ------------------------------------------------------------------</div><div class='del'>-//					PRIVATE FUNCTIONS</div><div class='add'>+// PRIVATE FUNCTIONS</div><div class='ctx'> // ------------------------------------------------------------------</div><div class='ctx'> /*</div><div class='ctx'>  * Always Check the following:</div><div class='hunk'>@@ -44,11 +46,11 @@</div><div class='ctx'>  *  - Is HPD HIGH?</div><div class='ctx'>  *  - Is BW Allocation Support Mode enabled on DP-Tx?</div><div class='ctx'>  */</div><div class='del'>-static bool get_bw_alloc_proceed_flag(struct dc_link *tmp)</div><div class='add'>+static bool link_dp_is_bw_alloc_available(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	return (tmp &amp;&amp; DISPLAY_ENDPOINT_USB4_DPIA == tmp-&gt;ep_type</div><div class='del'>-			&amp;&amp; tmp-&gt;hpd_status</div><div class='del'>-			&amp;&amp; tmp-&gt;dpia_bw_alloc_config.bw_alloc_enabled);</div><div class='add'>+	return (link &amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling</div><div class='add'>+		&amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc</div><div class='add'>+		&amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void reset_bw_alloc_struct(struct dc_link *link)</div><div class='hunk'>@@ -60,7 +62,6 @@ static void reset_bw_alloc_struct(struct dc_link *link)</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.estimated_bw = 0;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.bw_granularity = 0;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.dp_overhead = 0;</div><div class='del'>-	link-&gt;dpia_bw_alloc_config.response_ready = false;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.nrd_max_lane_count = 0;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.nrd_max_link_rate = 0;</div><div class='ctx'> 	for (int i = 0; i &lt; MAX_SINKS_PER_LINK; i++)</div><div class='hunk'>@@ -142,7 +143,7 @@ static int get_non_reduced_max_lane_count(struct dc_link *link)</div><div class='ctx'>  * granuality, Driver_ID, CM_Group, &amp; populate the BW allocation structs</div><div class='ctx'>  * for host router and dpia</div><div class='ctx'>  */</div><div class='del'>-static void init_usb4_bw_struct(struct dc_link *link)</div><div class='add'>+static void retrieve_usb4_dp_bw_allocation_info(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	reset_bw_alloc_struct(link);</div><div class='ctx'> </div><div class='hunk'>@@ -160,78 +161,6 @@ static void init_usb4_bw_struct(struct dc_link *link)</div><div class='ctx'> 		link-&gt;dpia_bw_alloc_config.nrd_max_lane_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static uint8_t get_lowest_dpia_index(struct dc_link *link)</div><div class='del'>-{</div><div class='del'>-	const struct dc *dc_struct = link-&gt;dc;</div><div class='del'>-	uint8_t idx = 0xFF;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES * 2; ++i) {</div><div class='del'>-</div><div class='del'>-		if (!dc_struct-&gt;links[i] ||</div><div class='del'>-				dc_struct-&gt;links[i]-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (idx &gt; dc_struct-&gt;links[i]-&gt;link_index) {</div><div class='del'>-			idx = dc_struct-&gt;links[i]-&gt;link_index;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return idx;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Get the maximum dp tunnel banwidth of host router</div><div class='del'>- *</div><div class='del'>- * @dc: pointer to the dc struct instance</div><div class='del'>- * @hr_index: host router index</div><div class='del'>- *</div><div class='del'>- * return: host router maximum dp tunnel bandwidth</div><div class='del'>- */</div><div class='del'>-static int get_host_router_total_dp_tunnel_bw(const struct dc *dc, uint8_t hr_index)</div><div class='del'>-{</div><div class='del'>-	uint8_t lowest_dpia_index = get_lowest_dpia_index(dc-&gt;links[0]);</div><div class='del'>-	uint8_t hr_index_temp = 0;</div><div class='del'>-	struct dc_link *link_dpia_primary, *link_dpia_secondary;</div><div class='del'>-	int total_bw = 0;</div><div class='del'>-</div><div class='del'>-	for (uint8_t i = 0; i &lt; (MAX_PIPES * 2) - 1; ++i) {</div><div class='del'>-</div><div class='del'>-		if (!dc-&gt;links[i] || dc-&gt;links[i]-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		hr_index_temp = (dc-&gt;links[i]-&gt;link_index - lowest_dpia_index) / 2;</div><div class='del'>-</div><div class='del'>-		if (hr_index_temp == hr_index) {</div><div class='del'>-			link_dpia_primary = dc-&gt;links[i];</div><div class='del'>-			link_dpia_secondary = dc-&gt;links[i + 1];</div><div class='del'>-</div><div class='del'>-			/**</div><div class='del'>-			 * If BW allocation enabled on both DPIAs, then</div><div class='del'>-			 * HR BW = Estimated(dpia_primary) + Allocated(dpia_secondary)</div><div class='del'>-			 * otherwise HR BW = Estimated(bw alloc enabled dpia)</div><div class='del'>-			 */</div><div class='del'>-			if ((link_dpia_primary-&gt;hpd_status &amp;&amp;</div><div class='del'>-				link_dpia_primary-&gt;dpia_bw_alloc_config.bw_alloc_enabled) &amp;&amp;</div><div class='del'>-				(link_dpia_secondary-&gt;hpd_status &amp;&amp;</div><div class='del'>-				link_dpia_secondary-&gt;dpia_bw_alloc_config.bw_alloc_enabled)) {</div><div class='del'>-					total_bw += link_dpia_primary-&gt;dpia_bw_alloc_config.estimated_bw +</div><div class='del'>-						link_dpia_secondary-&gt;dpia_bw_alloc_config.allocated_bw;</div><div class='del'>-			} else if (link_dpia_primary-&gt;hpd_status &amp;&amp;</div><div class='del'>-					link_dpia_primary-&gt;dpia_bw_alloc_config.bw_alloc_enabled) {</div><div class='del'>-				total_bw = link_dpia_primary-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='del'>-			} else if (link_dpia_secondary-&gt;hpd_status &amp;&amp;</div><div class='del'>-				link_dpia_secondary-&gt;dpia_bw_alloc_config.bw_alloc_enabled) {</div><div class='del'>-				total_bw += link_dpia_secondary-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='del'>-			}</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return total_bw;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * Cleanup function for when the dpia is unplugged to reset struct</div><div class='ctx'>  * and perform any required clean up</div><div class='hunk'>@@ -243,315 +172,277 @@ static int get_host_router_total_dp_tunnel_bw(const struct dc *dc, uint8_t hr_in</div><div class='ctx'> static void dpia_bw_alloc_unplug(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	if (link) {</div><div class='del'>-		DC_LOG_DEBUG("%s: resetting bw alloc config for link(%d)\n",</div><div class='add'>+		DC_LOG_DEBUG("%s: resetting BW alloc config for link(%d)\n",</div><div class='ctx'> 			__func__, link-&gt;link_index);</div><div class='ctx'> 		reset_bw_alloc_struct(link);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void set_usb4_req_bw_req(struct dc_link *link, int req_bw)</div><div class='add'>+static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw)</div><div class='ctx'> {</div><div class='del'>-	uint8_t requested_bw;</div><div class='del'>-	uint32_t temp;</div><div class='add'>+	uint8_t request_reg_val;</div><div class='add'>+	uint32_t temp, request_bw;</div><div class='ctx'> </div><div class='del'>-	/* Error check whether request bw greater than allocated */</div><div class='del'>-	if (req_bw &gt; link-&gt;dpia_bw_alloc_config.estimated_bw) {</div><div class='del'>-		DC_LOG_ERROR("%s: Request bw greater than estimated bw for link(%d)\n",</div><div class='del'>-			__func__, link-&gt;link_index);</div><div class='del'>-		req_bw = link-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='add'>+	if (link-&gt;dpia_bw_alloc_config.bw_granularity == 0) {</div><div class='add'>+		DC_LOG_ERROR("%s:  Link[%d]:  bw_granularity is zero!", __func__, link-&gt;link_index);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	temp = req_bw * link-&gt;dpia_bw_alloc_config.bw_granularity;</div><div class='del'>-	requested_bw = temp / Kbps_TO_Gbps;</div><div class='add'>+	request_reg_val = temp / Kbps_TO_Gbps;</div><div class='ctx'> </div><div class='ctx'> 	/* Always make sure to add more to account for floating points */</div><div class='ctx'> 	if (temp % Kbps_TO_Gbps)</div><div class='del'>-		++requested_bw;</div><div class='add'>+		++request_reg_val;</div><div class='ctx'> </div><div class='del'>-	/* Error check whether requested and allocated are equal */</div><div class='del'>-	req_bw = requested_bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='del'>-	if (req_bw == link-&gt;dpia_bw_alloc_config.allocated_bw) {</div><div class='del'>-		DC_LOG_ERROR("%s: Request bw equals to allocated bw for link(%d)\n",</div><div class='del'>-			__func__, link-&gt;link_index);</div><div class='add'>+	request_bw = request_reg_val * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='add'>+</div><div class='add'>+	if (request_bw &gt; link-&gt;dpia_bw_alloc_config.estimated_bw) {</div><div class='add'>+		DC_LOG_ERROR("%s:  Link[%d]:  Request BW (%d --&gt; %d) &gt; Estimated BW (%d)... Set to Estimated BW!",</div><div class='add'>+				__func__, link-&gt;link_index,</div><div class='add'>+				req_bw, request_bw, link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='add'>+		req_bw = link-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='add'>+</div><div class='add'>+		temp = req_bw * link-&gt;dpia_bw_alloc_config.bw_granularity;</div><div class='add'>+		request_reg_val = temp / Kbps_TO_Gbps;</div><div class='add'>+		if (temp % Kbps_TO_Gbps)</div><div class='add'>+			++request_reg_val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	link-&gt;dpia_bw_alloc_config.response_ready = false; // Reset flag</div><div class='del'>-	core_link_write_dpcd(</div><div class='del'>-		link,</div><div class='del'>-		REQUESTED_BW,</div><div class='del'>-		&amp;requested_bw,</div><div class='del'>-		sizeof(uint8_t));</div><div class='del'>-}</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.allocated_bw = request_bw;</div><div class='add'>+	DC_LOG_DC("%s:  Link[%d]:  Request BW:  %d", __func__, link-&gt;link_index, request_bw);</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Return the response_ready flag from dc_link struct</div><div class='del'>- *</div><div class='del'>- * @link: pointer to the dc_link struct instance</div><div class='del'>- *</div><div class='del'>- * return: response_ready flag from dc_link struct</div><div class='del'>- */</div><div class='del'>-static bool get_cm_response_ready_flag(struct dc_link *link)</div><div class='del'>-{</div><div class='del'>-	return link-&gt;dpia_bw_alloc_config.response_ready;</div><div class='add'>+	core_link_write_dpcd(link, REQUESTED_BW,</div><div class='add'>+		&amp;request_reg_val,</div><div class='add'>+		sizeof(uint8_t));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> // ------------------------------------------------------------------</div><div class='del'>-//					PUBLIC FUNCTIONS</div><div class='add'>+// PUBLIC FUNCTIONS</div><div class='ctx'> // ------------------------------------------------------------------</div><div class='del'>-bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link)</div><div class='add'>+bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	bool ret = false;</div><div class='del'>-	uint8_t response = 0,</div><div class='del'>-			bw_support_dpia = 0,</div><div class='del'>-			bw_support_cm = 0;</div><div class='add'>+	uint8_t val;</div><div class='ctx'> </div><div class='del'>-	if (!(link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp; link-&gt;hpd_status))</div><div class='del'>-		goto out;</div><div class='add'>+	val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;</div><div class='ctx'> </div><div class='del'>-	if (core_link_read_dpcd(</div><div class='del'>-			link,</div><div class='del'>-			DP_TUNNELING_CAPABILITIES,</div><div class='del'>-			&amp;response,</div><div class='del'>-			sizeof(uint8_t)) == DC_OK)</div><div class='del'>-		bw_support_dpia = (response &gt;&gt; 7) &amp; 1;</div><div class='del'>-</div><div class='del'>-	if (core_link_read_dpcd(</div><div class='del'>-		link,</div><div class='del'>-		USB4_DRIVER_BW_CAPABILITY,</div><div class='del'>-		&amp;response,</div><div class='del'>-		sizeof(uint8_t)) == DC_OK)</div><div class='del'>-		bw_support_cm = (response &gt;&gt; 7) &amp; 1;</div><div class='del'>-</div><div class='del'>-	/* Send request acknowledgment to Turn ON DPTX support */</div><div class='del'>-	if (bw_support_cm &amp;&amp; bw_support_dpia) {</div><div class='del'>-</div><div class='del'>-		response = 0x80;</div><div class='del'>-		if (core_link_write_dpcd(</div><div class='del'>-				link,</div><div class='del'>-				DPTX_BW_ALLOCATION_MODE_CONTROL,</div><div class='del'>-				&amp;response,</div><div class='del'>-				sizeof(uint8_t)) != DC_OK) {</div><div class='del'>-			DC_LOG_DEBUG("%s: FAILURE Enabling DPtx BW Allocation Mode Support for link(%d)\n",</div><div class='del'>-				__func__, link-&gt;link_index);</div><div class='del'>-		} else {</div><div class='del'>-			// SUCCESS Enabled DPtx BW Allocation Mode Support</div><div class='del'>-			DC_LOG_DEBUG("%s: SUCCESS Enabling DPtx BW Allocation Mode Support for link(%d)\n",</div><div class='del'>-				__func__, link-&gt;link_index);</div><div class='add'>+	if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &amp;val, sizeof(uint8_t)) == DC_OK) {</div><div class='add'>+		DC_LOG_DEBUG("%s:  link[%d] DPTX BW allocation mode enabled", __func__, link-&gt;link_index);</div><div class='add'>+</div><div class='add'>+		retrieve_usb4_dp_bw_allocation_info(link);</div><div class='ctx'> </div><div class='del'>-			ret = true;</div><div class='del'>-			init_usb4_bw_struct(link);</div><div class='del'>-			link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = true;</div><div class='add'>+		if (</div><div class='add'>+				link-&gt;dpia_bw_alloc_config.nrd_max_link_rate</div><div class='add'>+				&amp;&amp; link-&gt;dpia_bw_alloc_config.nrd_max_lane_count) {</div><div class='add'>+			link-&gt;reported_link_cap.link_rate = link-&gt;dpia_bw_alloc_config.nrd_max_link_rate;</div><div class='add'>+			link-&gt;reported_link_cap.lane_count = link-&gt;dpia_bw_alloc_config.nrd_max_lane_count;</div><div class='ctx'> 		}</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-out:</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = true;</div><div class='add'>+		ret = true;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;dc-&gt;debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {</div><div class='add'>+			/*</div><div class='add'>+			 * During DP tunnel creation, the CM preallocates BW</div><div class='add'>+			 * and reduces the estimated BW of other DPIAs.</div><div class='add'>+			 * The CM releases the preallocation only when the allocation is complete.</div><div class='add'>+			 * Perform a zero allocation to make the CM release the preallocation</div><div class='add'>+			 * and correctly update the estimated BW for all DPIAs per host router.</div><div class='add'>+			 */</div><div class='add'>+			link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0);</div><div class='add'>+		}</div><div class='add'>+	} else</div><div class='add'>+		DC_LOG_DEBUG("%s:  link[%d] failed to enable DPTX BW allocation mode", __func__, link-&gt;link_index);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result)</div><div class='add'>+/*</div><div class='add'>+ * Handle DP BW allocation status register</div><div class='add'>+ *</div><div class='add'>+ * @link: pointer to the dc_link struct instance</div><div class='add'>+ * @status: content of DP tunneling status DPCD register</div><div class='add'>+ *</div><div class='add'>+ * return: none</div><div class='add'>+ */</div><div class='add'>+void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status)</div><div class='ctx'> {</div><div class='del'>-	int bw_needed = 0;</div><div class='del'>-	int estimated = 0;</div><div class='del'>-</div><div class='del'>-	if (!get_bw_alloc_proceed_flag((link)))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (result) {</div><div class='del'>-</div><div class='del'>-	case DPIA_BW_REQ_FAILED:</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Ideally, we shouldn't run into this case as we always validate available</div><div class='del'>-		 * bandwidth and request within that limit</div><div class='del'>-		 */</div><div class='del'>-		estimated = bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='del'>-</div><div class='del'>-		DC_LOG_ERROR("%s: BW REQ FAILURE for DP-TX Request for link(%d)\n",</div><div class='del'>-			__func__, link-&gt;link_index);</div><div class='del'>-		DC_LOG_ERROR("%s: current estimated_bw(%d), new estimated_bw(%d)\n",</div><div class='del'>-			__func__, link-&gt;dpia_bw_alloc_config.estimated_bw, estimated);</div><div class='del'>-</div><div class='del'>-		/* Update the new Estimated BW value updated by CM */</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.estimated_bw = estimated;</div><div class='del'>-</div><div class='del'>-		/* Allocate the previously requested bandwidth */</div><div class='del'>-		set_usb4_req_bw_req(link, link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * If FAIL then it is either:</div><div class='del'>-		 * 1. Due to DP-Tx trying to allocate more than available i.e. it failed locally</div><div class='del'>-		 *    =&gt; get estimated and allocate that</div><div class='del'>-		 * 2. Due to the fact that DP-Tx tried to allocated ESTIMATED BW and failed then</div><div class='del'>-		 *    CM will have to update 0xE0023 with new ESTIMATED BW value.</div><div class='del'>-		 */</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case DPIA_BW_REQ_SUCCESS:</div><div class='del'>-</div><div class='del'>-		bw_needed = bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='del'>-</div><div class='del'>-		DC_LOG_DEBUG("%s: BW REQ SUCCESS for DP-TX Request for link(%d)\n",</div><div class='del'>-			__func__, link-&gt;link_index);</div><div class='del'>-		DC_LOG_DEBUG("%s: current allocated_bw(%d), new allocated_bw(%d)\n",</div><div class='del'>-			__func__, link-&gt;dpia_bw_alloc_config.allocated_bw, bw_needed);</div><div class='del'>-</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.allocated_bw = bw_needed;</div><div class='del'>-</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.response_ready = true;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case DPIA_EST_BW_CHANGED:</div><div class='add'>+	if (status &amp; DP_TUNNELING_BW_REQUEST_SUCCEEDED) {</div><div class='add'>+		DC_LOG_DEBUG("%s: BW Allocation request succeeded on link(%d)",</div><div class='add'>+				__func__, link-&gt;link_index);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		estimated = bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='add'>+	if (status &amp; DP_TUNNELING_BW_REQUEST_FAILED) {</div><div class='add'>+		DC_LOG_DEBUG("%s: BW Allocation request failed on link(%d)  allocated/estimated BW=%d",</div><div class='add'>+				__func__, link-&gt;link_index, link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='ctx'> </div><div class='del'>-		DC_LOG_DEBUG("%s: ESTIMATED BW CHANGED for link(%d)\n",</div><div class='del'>-			__func__, link-&gt;link_index);</div><div class='del'>-		DC_LOG_DEBUG("%s: current estimated_bw(%d), new estimated_bw(%d)\n",</div><div class='del'>-			__func__, link-&gt;dpia_bw_alloc_config.estimated_bw, estimated);</div><div class='del'>-</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.estimated_bw = estimated;</div><div class='del'>-		break;</div><div class='add'>+		link_dpia_send_bw_alloc_request(link, link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	case DPIA_BW_ALLOC_CAPS_CHANGED:</div><div class='add'>+	if (status &amp; DP_TUNNELING_BW_ALLOC_CAP_CHANGED) {</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.bw_granularity = get_bw_granularity(link);</div><div class='ctx'> </div><div class='del'>-		DC_LOG_ERROR("%s: BW ALLOC CAPABILITY CHANGED to Disabled for link(%d)\n",</div><div class='del'>-			__func__, link-&gt;link_index);</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = false;</div><div class='del'>-		break;</div><div class='add'>+		DC_LOG_DEBUG("%s: Granularity changed on link(%d)  new granularity=%d",</div><div class='add'>+				__func__, link-&gt;link_index, link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='ctx'> 	}</div><div class='del'>-}</div><div class='del'>-int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw)</div><div class='del'>-{</div><div class='del'>-	int ret = 0;</div><div class='del'>-	uint8_t timeout = 10;</div><div class='ctx'> </div><div class='del'>-	if (!(link &amp;&amp; DISPLAY_ENDPOINT_USB4_DPIA == link-&gt;ep_type</div><div class='del'>-			&amp;&amp; link-&gt;dpia_bw_alloc_config.bw_alloc_enabled))</div><div class='del'>-		goto out;</div><div class='add'>+	if (status &amp; DP_TUNNELING_ESTIMATED_BW_CHANGED) {</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);</div><div class='ctx'> </div><div class='del'>-	//1. Hot Plug</div><div class='del'>-	if (link-&gt;hpd_status &amp;&amp; peak_bw &gt; 0) {</div><div class='del'>-</div><div class='del'>-		// If DP over USB4 then we need to check BW allocation</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.link_max_bw = peak_bw;</div><div class='del'>-		set_usb4_req_bw_req(link, link-&gt;dpia_bw_alloc_config.link_max_bw);</div><div class='add'>+		DC_LOG_DEBUG("%s: Estimated BW changed on link(%d)  new estimated BW=%d",</div><div class='add'>+				__func__, link-&gt;link_index, link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		do {</div><div class='del'>-			if (timeout &gt; 0)</div><div class='del'>-				timeout--;</div><div class='del'>-			else</div><div class='del'>-				break;</div><div class='del'>-			msleep(10);</div><div class='del'>-		} while (!get_cm_response_ready_flag(link));</div><div class='add'>+	core_link_write_dpcd(</div><div class='add'>+		link, DP_TUNNELING_STATUS,</div><div class='add'>+		&amp;status, sizeof(status));</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		if (!timeout)</div><div class='del'>-			ret = 0;// ERROR TIMEOUT waiting for response for allocating bw</div><div class='del'>-		else if (link-&gt;dpia_bw_alloc_config.allocated_bw &gt; 0)</div><div class='del'>-			ret = link-&gt;dpia_bw_alloc_config.allocated_bw;</div><div class='add'>+/*</div><div class='add'>+ * Handle the DP Bandwidth allocation for DPIA</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw)</div><div class='add'>+{</div><div class='add'>+	if (link &amp;&amp; link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling</div><div class='add'>+			&amp;&amp; link-&gt;dpia_bw_alloc_config.bw_alloc_enabled) {</div><div class='add'>+		if (peak_bw &gt; 0) {</div><div class='add'>+			// If DP over USB4 then we need to check BW allocation</div><div class='add'>+			link-&gt;dpia_bw_alloc_config.link_max_bw = peak_bw;</div><div class='add'>+</div><div class='add'>+			link_dpia_send_bw_alloc_request(link, peak_bw);</div><div class='add'>+		} else</div><div class='add'>+			dpia_bw_alloc_unplug(link);</div><div class='ctx'> 	}</div><div class='del'>-	//2. Cold Unplug</div><div class='del'>-	else if (!link-&gt;hpd_status)</div><div class='del'>-		dpia_bw_alloc_unplug(link);</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	return ret;</div><div class='ctx'> }</div><div class='del'>-bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw)</div><div class='add'>+</div><div class='add'>+void link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw)</div><div class='ctx'> {</div><div class='del'>-	bool ret = false;</div><div class='del'>-	uint8_t timeout = 10;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);</div><div class='ctx'> </div><div class='del'>-	DC_LOG_DEBUG("%s: ENTER: link(%d), hpd_status(%d), current allocated_bw(%d), req_bw(%d)\n",</div><div class='add'>+	DC_LOG_DEBUG("%s: ENTER: link[%d] hpd(%d)  Allocated_BW: %d  Estimated_BW: %d  Req_BW: %d",</div><div class='ctx'> 		__func__, link-&gt;link_index, link-&gt;hpd_status,</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.allocated_bw, req_bw);</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.allocated_bw,</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.estimated_bw,</div><div class='add'>+		req_bw);</div><div class='add'>+</div><div class='add'>+	if (link_dp_is_bw_alloc_available(link))</div><div class='add'>+		link_dpia_send_bw_alloc_request(link, req_bw);</div><div class='add'>+	else</div><div class='add'>+		DC_LOG_DEBUG("%s:  BW Allocation mode not available", __func__);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (!get_bw_alloc_proceed_flag(link))</div><div class='del'>-		goto out;</div><div class='add'>+uint32_t link_dpia_get_dp_overhead(const struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	uint32_t link_dp_overhead = 0;</div><div class='ctx'> </div><div class='del'>-	set_usb4_req_bw_req(link, req_bw);</div><div class='del'>-	do {</div><div class='del'>-		if (timeout &gt; 0)</div><div class='del'>-			timeout--;</div><div class='del'>-		else</div><div class='del'>-			break;</div><div class='del'>-		msleep(10);</div><div class='del'>-	} while (!get_cm_response_ready_flag(link));</div><div class='add'>+	if ((link-&gt;type == dc_connection_mst_branch) &amp;&amp;</div><div class='add'>+				!link-&gt;dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {</div><div class='add'>+		/* For 8b/10b encoding: MTP is 64 time slots long, slot 0 is used for MTPH</div><div class='add'>+		 * MST overhead is 1/64 of link bandwidth (excluding any overhead)</div><div class='add'>+		 */</div><div class='add'>+		const struct dc_link_settings *link_cap = dc_link_get_link_cap(link);</div><div class='ctx'> </div><div class='del'>-	if (timeout)</div><div class='del'>-		ret = true;</div><div class='add'>+		if (link_cap) {</div><div class='add'>+			uint32_t link_bw_in_kbps = (uint32_t)link_cap-&gt;link_rate *</div><div class='add'>+					   (uint32_t)link_cap-&gt;lane_count *</div><div class='add'>+					   LINK_RATE_REF_FREQ_IN_KHZ * 8;</div><div class='add'>+			link_dp_overhead = (link_bw_in_kbps / MST_TIME_SLOT_COUNT)</div><div class='add'>+						+ ((link_bw_in_kbps % MST_TIME_SLOT_COUNT) ? 1 : 0);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-out:</div><div class='del'>-	DC_LOG_DEBUG("%s: EXIT: timeout(%d), ret(%d)\n", __func__, timeout, ret);</div><div class='del'>-	return ret;</div><div class='add'>+	return link_dp_overhead;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, const unsigned int num_dpias)</div><div class='add'>+/*</div><div class='add'>+ * Aggregates the DPIA bandwidth usage for the respective USB4 Router.</div><div class='add'>+ * And then validate if the required bandwidth is within the router's capacity.</div><div class='add'>+ *</div><div class='add'>+ * @dc_validation_dpia_set: pointer to the dc_validation_dpia_set</div><div class='add'>+ * @count: number of DPIA validation sets</div><div class='add'>+ *</div><div class='add'>+ * return: true if validation is succeeded</div><div class='add'>+ */</div><div class='add'>+bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count)</div><div class='ctx'> {</div><div class='del'>-	bool ret = true;</div><div class='del'>-	int bw_needed_per_hr[MAX_HR_NUM] = { 0, 0 }, host_router_total_dp_bw = 0;</div><div class='del'>-	uint8_t lowest_dpia_index, i, hr_index;</div><div class='add'>+	uint32_t granularity_Gbps;</div><div class='add'>+	const struct dc_link *link;</div><div class='add'>+	uint32_t link_bw_granularity;</div><div class='add'>+	uint32_t link_required_bw;</div><div class='add'>+	struct usb4_router_validation_set router_sets[MAX_HOST_ROUTERS_NUM] = { 0 };</div><div class='add'>+	uint8_t i;</div><div class='add'>+	bool is_success = true;</div><div class='add'>+	uint8_t router_count = 0;</div><div class='add'>+</div><div class='add'>+	if ((dpia_link_sets == NULL) || (count == 0))</div><div class='add'>+		return is_success;</div><div class='add'>+</div><div class='add'>+	// Iterate through each DP tunneling link (DPIA).</div><div class='add'>+	// Aggregate its bandwidth requirements onto the respective USB4 router.</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		link = dpia_link_sets[i].link;</div><div class='add'>+		link_required_bw = dpia_link_sets[i].required_bw;</div><div class='add'>+		const struct dc_tunnel_settings *dp_tunnel_settings = dpia_link_sets[i].tunnel_settings;</div><div class='add'>+</div><div class='add'>+		if ((link == NULL) || (dp_tunnel_settings == NULL) || dp_tunnel_settings-&gt;bw_granularity == 0)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-	if (!num_dpias || num_dpias &gt; MAX_DPIA_NUM)</div><div class='del'>-		return ret;</div><div class='add'>+		if (link-&gt;type == dc_connection_mst_branch)</div><div class='add'>+			link_required_bw += link_dpia_get_dp_overhead(link);</div><div class='ctx'> </div><div class='del'>-	lowest_dpia_index = get_lowest_dpia_index(link[0]);</div><div class='add'>+		granularity_Gbps = (Kbps_TO_Gbps / dp_tunnel_settings-&gt;bw_granularity);</div><div class='add'>+		link_bw_granularity = (link_required_bw / granularity_Gbps) * granularity_Gbps +</div><div class='add'>+				((link_required_bw % granularity_Gbps) ? granularity_Gbps : 0);</div><div class='ctx'> </div><div class='del'>-	/* get total Host Router BW with granularity for the given modes */</div><div class='del'>-	for (i = 0; i &lt; num_dpias; ++i) {</div><div class='del'>-		int granularity_Gbps = 0;</div><div class='del'>-		int bw_granularity = 0;</div><div class='add'>+		// Find or add the USB4 router associated with the current DPIA link</div><div class='add'>+		for (uint8_t j = 0; j &lt; MAX_HOST_ROUTERS_NUM; j++) {</div><div class='add'>+			if (router_sets[j].is_valid == false) {</div><div class='add'>+				router_sets[j].is_valid = true;</div><div class='add'>+				router_sets[j].cm_id = dp_tunnel_settings-&gt;cm_id;</div><div class='add'>+				router_count++;</div><div class='add'>+			}</div><div class='ctx'> </div><div class='del'>-		if (!link[i]-&gt;dpia_bw_alloc_config.bw_alloc_enabled)</div><div class='del'>-			continue;</div><div class='add'>+			if (router_sets[j].cm_id == dp_tunnel_settings-&gt;cm_id) {</div><div class='add'>+				uint32_t remaining_bw =</div><div class='add'>+					dp_tunnel_settings-&gt;estimated_bw - dp_tunnel_settings-&gt;allocated_bw;</div><div class='ctx'> </div><div class='del'>-		if (link[i]-&gt;link_index &lt; lowest_dpia_index)</div><div class='del'>-			continue;</div><div class='add'>+				router_sets[j].allocated_bw += dp_tunnel_settings-&gt;allocated_bw;</div><div class='ctx'> </div><div class='del'>-		granularity_Gbps = (Kbps_TO_Gbps / link[i]-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='del'>-		bw_granularity = (bw_needed_per_dpia[i] / granularity_Gbps) * granularity_Gbps +</div><div class='del'>-				((bw_needed_per_dpia[i] % granularity_Gbps) ? granularity_Gbps : 0);</div><div class='add'>+				if (remaining_bw &gt; router_sets[j].remaining_bw)</div><div class='add'>+					router_sets[j].remaining_bw = remaining_bw;</div><div class='ctx'> </div><div class='del'>-		hr_index = (link[i]-&gt;link_index - lowest_dpia_index) / 2;</div><div class='del'>-		bw_needed_per_hr[hr_index] += bw_granularity;</div><div class='del'>-	}</div><div class='add'>+				// Get the max estimated BW within the same CM_ID</div><div class='add'>+				if (dp_tunnel_settings-&gt;estimated_bw &gt; router_sets[j].estimated_bw)</div><div class='add'>+					router_sets[j].estimated_bw = dp_tunnel_settings-&gt;estimated_bw;</div><div class='ctx'> </div><div class='del'>-	/* validate against each Host Router max BW */</div><div class='del'>-	for (hr_index = 0; hr_index &lt; MAX_HR_NUM; ++hr_index) {</div><div class='del'>-		if (bw_needed_per_hr[hr_index]) {</div><div class='del'>-			host_router_total_dp_bw = get_host_router_total_dp_tunnel_bw(link[0]-&gt;dc, hr_index);</div><div class='del'>-			if (bw_needed_per_hr[hr_index] &gt; host_router_total_dp_bw) {</div><div class='del'>-				ret = false;</div><div class='add'>+				router_sets[j].required_bw += link_bw_granularity;</div><div class='add'>+				router_sets[j].dpia_count++;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='add'>+	// Validate bandwidth for each unique router found.</div><div class='add'>+	for (i = 0; i &lt; router_count; i++) {</div><div class='add'>+		uint32_t total_bw = 0;</div><div class='ctx'> </div><div class='del'>-int link_dp_dpia_get_dp_overhead_in_dp_tunneling(struct dc_link *link)</div><div class='del'>-{</div><div class='del'>-	int dp_overhead = 0, link_mst_overhead = 0;</div><div class='add'>+		if (router_sets[i].is_valid == false)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-	if (!get_bw_alloc_proceed_flag((link)))</div><div class='del'>-		return dp_overhead;</div><div class='add'>+		// Determine the total available bandwidth for the current router based on aggregated data</div><div class='add'>+		if ((router_sets[i].dpia_count == 1) || (router_sets[i].allocated_bw == 0))</div><div class='add'>+			total_bw = router_sets[i].estimated_bw;</div><div class='add'>+		else</div><div class='add'>+			total_bw = router_sets[i].allocated_bw + router_sets[i].remaining_bw;</div><div class='ctx'> </div><div class='del'>-	/* if its mst link, add MTPH overhead */</div><div class='del'>-	if ((link-&gt;type == dc_connection_mst_branch) &amp;&amp;</div><div class='del'>-		!link-&gt;dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {</div><div class='del'>-		/* For 8b/10b encoding: MTP is 64 time slots long, slot 0 is used for MTPH</div><div class='del'>-		 * MST overhead is 1/64 of link bandwidth (excluding any overhead)</div><div class='del'>-		 */</div><div class='del'>-		const struct dc_link_settings *link_cap =</div><div class='del'>-			dc_link_get_link_cap(link);</div><div class='del'>-		uint32_t link_bw_in_kbps = (uint32_t)link_cap-&gt;link_rate *</div><div class='del'>-					   (uint32_t)link_cap-&gt;lane_count *</div><div class='del'>-					   LINK_RATE_REF_FREQ_IN_KHZ * 8;</div><div class='del'>-		link_mst_overhead = (link_bw_in_kbps / 64) + ((link_bw_in_kbps % 64) ? 1 : 0);</div><div class='add'>+		if (router_sets[i].required_bw &gt; total_bw) {</div><div class='add'>+			is_success = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* add all the overheads */</div><div class='del'>-	dp_overhead = link_mst_overhead;</div><div class='del'>-</div><div class='del'>-	return dp_overhead;</div><div class='add'>+	return is_success;</div><div class='ctx'> }</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h<br/>index 3b6d8494f9d5..30cd8e2b9d35 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h</a></div><div class='hunk'>@@ -26,12 +26,8 @@</div><div class='ctx'> #ifndef DC_INC_LINK_DP_DPIA_BW_H_</div><div class='ctx'> #define DC_INC_LINK_DP_DPIA_BW_H_</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='del'>-/* Number of Host Routers per motherboard is 2 */</div><div class='del'>-#define MAX_HR_NUM			2</div><div class='del'>-/* Number of DPIA per host router is 2 */</div><div class='del'>-#define MAX_DPIA_NUM		(MAX_HR_NUM * 2)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Host Router BW type</div><div class='hunk'>@@ -42,14 +38,24 @@ enum bw_type {</div><div class='ctx'> 	HOST_ROUTER_BW_INVALID,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct usb4_router_validation_set {</div><div class='add'>+	bool is_valid;</div><div class='add'>+	uint8_t cm_id;</div><div class='add'>+	uint8_t dpia_count;</div><div class='add'>+	uint32_t required_bw;</div><div class='add'>+	uint32_t allocated_bw;</div><div class='add'>+	uint32_t estimated_bw;</div><div class='add'>+	uint32_t remaining_bw;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='del'>- * Enable BW Allocation Mode Support from the DP-Tx side</div><div class='add'>+ * Enable USB4 DP BW allocation mode</div><div class='ctx'>  *</div><div class='ctx'>  * @link: pointer to the dc_link struct instance</div><div class='ctx'>  *</div><div class='ctx'>  * return: SUCCESS or FAILURE</div><div class='ctx'>  */</div><div class='del'>-bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link);</div><div class='add'>+bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Allocates only what the stream needs for bw, so if:</div><div class='hunk'>@@ -59,9 +65,8 @@ bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link);</div><div class='ctx'>  * @link: pointer to the dc_link struct instance</div><div class='ctx'>  * @req_bw: Bw requested by the stream</div><div class='ctx'>  *</div><div class='del'>- * return: true if allocated successfully</div><div class='ctx'>  */</div><div class='del'>-bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw);</div><div class='add'>+void link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Handle the USB4 BW Allocation related functionality here:</div><div class='hunk'>@@ -71,41 +76,37 @@ bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int r</div><div class='ctx'>  * @link: pointer to the dc_link struct instance</div><div class='ctx'>  * @peak_bw: Peak bw used by the link/sink</div><div class='ctx'>  *</div><div class='del'>- * return: allocated bw else return 0</div><div class='ctx'>  */</div><div class='del'>-int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw);</div><div class='add'>+void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Handle function for when the status of the Request above is complete.</div><div class='del'>- * We will find out the result of allocating on CM and update structs.</div><div class='add'>+ * Obtain all the DP overheads in dp tunneling for the dpia link</div><div class='ctx'>  *</div><div class='ctx'>  * @link: pointer to the dc_link struct instance</div><div class='del'>- * @bw: Allocated or Estimated BW depending on the result</div><div class='del'>- * @result: Response type</div><div class='ctx'>  *</div><div class='del'>- * return: none</div><div class='add'>+ * return: DP overheads in DP tunneling</div><div class='ctx'>  */</div><div class='del'>-void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result);</div><div class='add'>+uint32_t link_dpia_get_dp_overhead(const struct dc_link *link);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Handle the validation of total BW here and confirm that the bw used by each</div><div class='del'>- * DPIA doesn't exceed available BW for each host router (HR)</div><div class='add'>+ * Handle DP BW allocation status register</div><div class='ctx'>  *</div><div class='del'>- * @link[]: array of link pointer to all possible DPIA links</div><div class='del'>- * @bw_needed[]: bw needed for each DPIA link based on timing</div><div class='del'>- * @num_dpias: Number of DPIAs for the above 2 arrays. Should always be &lt;= MAX_DPIA_NUM</div><div class='add'>+ * @link: pointer to the dc_link struct instance</div><div class='add'>+ * @status: content of DP tunneling status register</div><div class='ctx'>  *</div><div class='del'>- * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE</div><div class='add'>+ * return: none</div><div class='ctx'>  */</div><div class='del'>-bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed, const unsigned int num_dpias);</div><div class='add'>+void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Obtain all the DP overheads in dp tunneling for the dpia link</div><div class='add'>+ * Aggregates the DPIA bandwidth usage for the respective USB4 Router.</div><div class='ctx'>  *</div><div class='del'>- * @link: pointer to the dc_link struct instance</div><div class='add'>+ * @dc_validation_dpia_set: pointer to the dc_validation_dpia_set</div><div class='add'>+ * @count: number of DPIA validation sets</div><div class='ctx'>  *</div><div class='del'>- * return: DP overheads in DP tunneling</div><div class='add'>+ * return: true if validation is succeeded</div><div class='ctx'>  */</div><div class='del'>-int link_dp_dpia_get_dp_overhead_in_dp_tunneling(struct dc_link *link);</div><div class='add'>+bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count);</div><div class='ctx'> </div><div class='ctx'> #endif /* DC_INC_LINK_DP_DPIA_BW_H_ */</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c<br/>index ba69874be5a4..4b01ab0a5a7f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c</a></div><div class='hunk'>@@ -37,6 +37,7 @@</div><div class='ctx'> #include "link/accessories/link_dp_trace.h"</div><div class='ctx'> #include "link/link_dpms.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='add'>+#include "link_dp_dpia_bw.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='hunk'>@@ -120,7 +121,7 @@ bool dp_parse_link_loss_status(</div><div class='ctx'> </div><div class='ctx'> static bool handle_hpd_irq_psr_sink(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	union dpcd_psr_configuration psr_configuration;</div><div class='add'>+	union dpcd_psr_configuration psr_configuration = {0};</div><div class='ctx'> </div><div class='ctx'> 	if (!link-&gt;psr_settings.psr_feature_enabled)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -186,19 +187,33 @@ static bool handle_hpd_irq_psr_sink(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> static void handle_hpd_irq_replay_sink(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	union dpcd_replay_configuration replay_configuration;</div><div class='add'>+	union dpcd_replay_configuration replay_configuration = {0};</div><div class='ctx'> 	/*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR status.*/</div><div class='del'>-	union psr_error_status replay_error_status;</div><div class='add'>+	union psr_error_status replay_error_status = {0};</div><div class='add'>+	bool ret = false;</div><div class='add'>+	int retries = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!link-&gt;replay_settings.replay_feature_enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	dm_helpers_dp_read_dpcd(</div><div class='del'>-		link-&gt;ctx,</div><div class='del'>-		link,</div><div class='del'>-		DP_SINK_PR_REPLAY_STATUS,</div><div class='del'>-		&amp;replay_configuration.raw,</div><div class='del'>-		sizeof(replay_configuration.raw));</div><div class='add'>+	while (retries &lt; 10) {</div><div class='add'>+		ret = dm_helpers_dp_read_dpcd(</div><div class='add'>+			link-&gt;ctx,</div><div class='add'>+			link,</div><div class='add'>+			DP_SINK_PR_REPLAY_STATUS,</div><div class='add'>+			&amp;replay_configuration.raw,</div><div class='add'>+			sizeof(replay_configuration.raw));</div><div class='add'>+</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		retries++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!ret)</div><div class='add'>+		DC_LOG_WARNING("[%s][%d] DPCD read addr.0x%x failed with %d retries\n",</div><div class='add'>+					__func__, __LINE__,</div><div class='add'>+					DP_SINK_PR_REPLAY_STATUS, retries);</div><div class='ctx'> </div><div class='ctx'> 	dm_helpers_dp_read_dpcd(</div><div class='ctx'> 		link-&gt;ctx,</div><div class='hunk'>@@ -207,20 +222,16 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)</div><div class='ctx'> 		&amp;replay_error_status.raw,</div><div class='ctx'> 		sizeof(replay_error_status.raw));</div><div class='ctx'> </div><div class='del'>-	link-&gt;replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR =</div><div class='del'>-		replay_error_status.bits.LINK_CRC_ERROR;</div><div class='del'>-	link-&gt;replay_settings.config.replay_error_status.bits.DESYNC_ERROR =</div><div class='del'>-		replay_configuration.bits.DESYNC_ERROR_STATUS;</div><div class='del'>-	link-&gt;replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR =</div><div class='del'>-		replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS;</div><div class='del'>-</div><div class='del'>-	if (link-&gt;replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR ||</div><div class='del'>-		link-&gt;replay_settings.config.replay_error_status.bits.DESYNC_ERROR ||</div><div class='del'>-		link-&gt;replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR) {</div><div class='add'>+	if (replay_error_status.bits.LINK_CRC_ERROR ||</div><div class='add'>+		replay_configuration.bits.DESYNC_ERROR_STATUS ||</div><div class='add'>+		replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) {</div><div class='ctx'> 		bool allow_active;</div><div class='ctx'> </div><div class='del'>-		if (link-&gt;replay_settings.config.replay_error_status.bits.DESYNC_ERROR)</div><div class='del'>-			link-&gt;replay_settings.config.received_desync_error_hpd = 1;</div><div class='add'>+		link-&gt;replay_settings.config.replay_error_status.raw |= replay_error_status.raw;</div><div class='add'>+</div><div class='add'>+		/* Increment desync error counter if a desync error is detected */</div><div class='add'>+		if (replay_configuration.bits.DESYNC_ERROR_STATUS)</div><div class='add'>+			link-&gt;replay_settings.replay_desync_error_fail_count++;</div><div class='ctx'> </div><div class='ctx'> 		if (link-&gt;replay_settings.config.force_disable_desync_error_check)</div><div class='ctx'> 			return;</div><div class='hunk'>@@ -277,10 +288,34 @@ void dp_handle_link_loss(struct dc_link *link)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dp_handle_tunneling_irq(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	enum dc_status retval;</div><div class='add'>+	uint8_t tunneling_status = 0;</div><div class='add'>+</div><div class='add'>+	retval = core_link_read_dpcd(</div><div class='add'>+			link, DP_TUNNELING_STATUS,</div><div class='add'>+			&amp;tunneling_status,</div><div class='add'>+			sizeof(tunneling_status));</div><div class='add'>+</div><div class='add'>+	if (retval == DC_OK) {</div><div class='add'>+		DC_LOG_HW_HPD_IRQ("%s: Got DP tunneling status on link %d status=0x%x",</div><div class='add'>+				__func__, link-&gt;link_index, tunneling_status);</div><div class='add'>+</div><div class='add'>+		if (tunneling_status &amp; DP_TUNNELING_BW_ALLOC_BITS_MASK)</div><div class='add'>+			link_dp_dpia_handle_bw_alloc_status(link, tunneling_status);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tunneling_status = DP_TUNNELING_IRQ;</div><div class='add'>+	core_link_write_dpcd(</div><div class='add'>+		link, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,</div><div class='add'>+		&amp;tunneling_status, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void read_dpcd204h_on_irq_hpd(struct dc_link *link, union hpd_irq_data *irq_data)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_status retval;</div><div class='del'>-	union lane_align_status_updated dpcd_lane_status_updated;</div><div class='add'>+	union lane_align_status_updated dpcd_lane_status_updated = {0};</div><div class='ctx'> </div><div class='ctx'> 	retval = core_link_read_dpcd(</div><div class='ctx'> 			link,</div><div class='hunk'>@@ -310,17 +345,23 @@ enum dc_status dp_read_hpd_rx_irq_data(</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * For DP 1.4 we need to read those from 2002h range.</div><div class='ctx'> 	 */</div><div class='del'>-	if (link-&gt;dpcd_caps.dpcd_rev.raw &lt; DPCD_REV_14)</div><div class='add'>+	if (link-&gt;dpcd_caps.dpcd_rev.raw &lt; DPCD_REV_14) {</div><div class='ctx'> 		retval = core_link_read_dpcd(</div><div class='ctx'> 			link,</div><div class='ctx'> 			DP_SINK_COUNT,</div><div class='ctx'> 			irq_data-&gt;raw,</div><div class='del'>-			sizeof(union hpd_irq_data));</div><div class='del'>-	else {</div><div class='add'>+			DP_SINK_STATUS - DP_SINK_COUNT + 1);</div><div class='add'>+</div><div class='add'>+		if (link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {</div><div class='add'>+			retval = core_link_read_dpcd(</div><div class='add'>+					link, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,</div><div class='add'>+					&amp;irq_data-&gt;bytes.link_service_irq_esi0.raw, 1);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='ctx'> 		/* Read 14 bytes in a single read and then copy only the required fields.</div><div class='ctx'> 		 * This is more efficient than doing it in two separate AUX reads. */</div><div class='ctx'> </div><div class='del'>-		uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];</div><div class='add'>+		uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1] = {0};</div><div class='ctx'> </div><div class='ctx'> 		retval = core_link_read_dpcd(</div><div class='ctx'> 			link,</div><div class='hunk'>@@ -337,6 +378,7 @@ enum dc_status dp_read_hpd_rx_irq_data(</div><div class='ctx'> 		irq_data-&gt;bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];</div><div class='ctx'> 		irq_data-&gt;bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];</div><div class='ctx'> 		irq_data-&gt;bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];</div><div class='add'>+		irq_data-&gt;bytes.link_service_irq_esi0.raw = tmp[DP_LINK_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * This display doesn't have correct values in DPCD200Eh.</div><div class='hunk'>@@ -356,10 +398,12 @@ bool dp_should_allow_hpd_rx_irq(const struct dc_link *link)</div><div class='ctx'> 	 * Don't handle RX IRQ unless one of following is met:</div><div class='ctx'> 	 * 1) The link is established (cur_link_settings != unknown)</div><div class='ctx'> 	 * 2) We know we're dealing with a branch device, SST or MST</div><div class='add'>+	 * 3) The link is bw_alloc enabled.</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	if ((link-&gt;cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||</div><div class='del'>-		is_dp_branch_device(link))</div><div class='add'>+		is_dp_branch_device(link) ||</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.bw_alloc_enabled)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -404,7 +448,8 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {</div><div class='ctx'> 		// Workaround for DP 1.4a LL Compliance CTS as USB4 has to share encoders unlike DP and USBC</div><div class='del'>-		if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+		if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp;</div><div class='add'>+				!link-&gt;dc-&gt;config.enable_dpia_pre_training)</div><div class='ctx'> 			link-&gt;skip_fallback_on_link_loss = true;</div><div class='ctx'> </div><div class='ctx'> 		device_service_clear.bits.AUTOMATED_TEST = 1;</div><div class='hunk'>@@ -454,7 +499,8 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,</div><div class='ctx'> 	 * If we got sink count changed it means</div><div class='ctx'> 	 * Downstream port status changed,</div><div class='ctx'> 	 * then DM should call DC to do the detection.</div><div class='del'>-	 * NOTE: Do not handle link loss on eDP since it is internal link*/</div><div class='add'>+	 * NOTE: Do not handle link loss on eDP since it is internal link</div><div class='add'>+	 */</div><div class='ctx'> 	if ((link-&gt;connector_signal != SIGNAL_TYPE_EDP) &amp;&amp;</div><div class='ctx'> 			dp_parse_link_loss_status(</div><div class='ctx'> 					link,</div><div class='hunk'>@@ -477,6 +523,11 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,</div><div class='ctx'> 		dp_trace_link_loss_increment(link);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {</div><div class='add'>+		if (hpd_irq_dpcd_data.bytes.link_service_irq_esi0.bits.DP_LINK_TUNNELING_IRQ)</div><div class='add'>+			dp_handle_tunneling_irq(link);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (link-&gt;type == dc_connection_sst_branch &amp;&amp;</div><div class='ctx'> 		hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT</div><div class='ctx'> 			!= link-&gt;dpcd_sink_count)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h<br/>index ac33730fedd4..87516fb3b45a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #ifndef __DC_LINK_DP_IRQ_HANDLER_H__</div><div class='ctx'> #define __DC_LINK_DP_IRQ_HANDLER_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> bool dp_parse_link_loss_status(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	union hpd_irq_data *hpd_irq_dpcd_data);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c<br/>index 2fa4e64e2430..49521ac4b0e8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c</a></div><div class='hunk'>@@ -75,7 +75,8 @@ void dp_disable_link_phy(struct dc_link *link,</div><div class='ctx'> 	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	if (!link-&gt;wa_flags.dp_keep_receiver_powered &amp;&amp;</div><div class='del'>-		!link-&gt;skip_implict_edp_power_control)</div><div class='add'>+			!link-&gt;skip_implict_edp_power_control &amp;&amp;</div><div class='add'>+			link-&gt;type != dc_connection_none)</div><div class='ctx'> 		dpcd_write_rx_power_ctrl(link, false);</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;hwss.disable_link_output(link, link_res, signal);</div><div class='hunk'>@@ -104,7 +105,7 @@ void dp_set_hw_lane_settings(</div><div class='ctx'> 	// Don't return here if using FIXED_VS link HWSS and encoding is 128b/132b</div><div class='ctx'> 	if ((link_settings-&gt;lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) &amp;&amp;</div><div class='ctx'> 			!is_immediate_downstream(link, offset) &amp;&amp;</div><div class='del'>-			(!(link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) ||</div><div class='add'>+			(!((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) ||</div><div class='ctx'> 			link_dp_get_encoding_format(&amp;link_settings-&gt;link_settings) == DP_8b_10b_ENCODING))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -141,38 +142,33 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource</div><div class='ctx'> 	 * if the sink supports it and leave it enabled on link.</div><div class='ctx'> 	 * If FEC is not supported, disable it.</div><div class='ctx'> 	 */</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='ctx'> 	enum dc_status status = DC_OK;</div><div class='ctx'> 	uint8_t fec_config = 0;</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> 	ASSERT(link_enc);</div><div class='add'>+	if (link_enc-&gt;funcs-&gt;fec_set_ready == NULL)</div><div class='add'>+		return DC_NOT_SUPPORTED;</div><div class='ctx'> </div><div class='del'>-	if (!dp_should_enable_fec(link))</div><div class='del'>-		return status;</div><div class='del'>-</div><div class='del'>-	if (link_enc-&gt;funcs-&gt;fec_set_ready &amp;&amp;</div><div class='del'>-			link-&gt;dpcd_caps.fec_cap.bits.FEC_CAPABLE) {</div><div class='del'>-		if (ready) {</div><div class='del'>-			fec_config = 1;</div><div class='del'>-			status = core_link_write_dpcd(link,</div><div class='del'>-					DP_FEC_CONFIGURATION,</div><div class='del'>-					&amp;fec_config,</div><div class='del'>-					sizeof(fec_config));</div><div class='del'>-			if (status == DC_OK) {</div><div class='del'>-				link_enc-&gt;funcs-&gt;fec_set_ready(link_enc, true);</div><div class='del'>-				link-&gt;fec_state = dc_link_fec_ready;</div><div class='del'>-			} else {</div><div class='del'>-				link_enc-&gt;funcs-&gt;fec_set_ready(link_enc, false);</div><div class='del'>-				link-&gt;fec_state = dc_link_fec_not_ready;</div><div class='del'>-				dm_error("dpcd write failed to set fec_ready");</div><div class='del'>-			}</div><div class='del'>-		} else if (link-&gt;fec_state == dc_link_fec_ready) {</div><div class='add'>+	if (ready &amp;&amp; dp_should_enable_fec(link)) {</div><div class='add'>+		fec_config = 1;</div><div class='add'>+</div><div class='add'>+		status = core_link_write_dpcd(link, DP_FEC_CONFIGURATION,</div><div class='add'>+				&amp;fec_config, sizeof(fec_config));</div><div class='add'>+</div><div class='add'>+		if (status == DC_OK) {</div><div class='add'>+			link_enc-&gt;funcs-&gt;fec_set_ready(link_enc, true);</div><div class='add'>+			link-&gt;fec_state = dc_link_fec_ready;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (link-&gt;fec_state == dc_link_fec_ready) {</div><div class='ctx'> 			fec_config = 0;</div><div class='del'>-			status = core_link_write_dpcd(link,</div><div class='del'>-					DP_FEC_CONFIGURATION,</div><div class='del'>-					&amp;fec_config,</div><div class='del'>-					sizeof(fec_config));</div><div class='add'>+			if (link-&gt;type != dc_connection_none)</div><div class='add'>+				core_link_write_dpcd(link, DP_FEC_CONFIGURATION,</div><div class='add'>+					&amp;fec_config, sizeof(fec_config));</div><div class='add'>+</div><div class='ctx'> 			link_enc-&gt;funcs-&gt;fec_set_ready(link_enc, false);</div><div class='ctx'> 			link-&gt;fec_state = dc_link_fec_not_ready;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -181,20 +177,19 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dp_set_fec_enable(struct dc_link *link, bool enable)</div><div class='add'>+void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='del'>-	ASSERT(link_enc);</div><div class='add'>+	if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> </div><div class='del'>-	if (!dp_should_enable_fec(link))</div><div class='add'>+	if (link_enc == NULL || link_enc-&gt;funcs == NULL || link_enc-&gt;funcs-&gt;fec_set_enable == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (link_enc-&gt;funcs-&gt;fec_set_enable &amp;&amp;</div><div class='del'>-			link-&gt;dpcd_caps.fec_cap.bits.FEC_CAPABLE) {</div><div class='del'>-		if (link-&gt;fec_state == dc_link_fec_ready &amp;&amp; enable) {</div><div class='del'>-			/* Accord to DP spec, FEC enable sequence can first</div><div class='add'>+	if (enable &amp;&amp; dp_should_enable_fec(link)) {</div><div class='add'>+		if (link-&gt;fec_state == dc_link_fec_ready) {</div><div class='add'>+			/* According to DP spec, FEC enable sequence can first</div><div class='ctx'> 			 * be transmitted anytime after 1000 LL codes have</div><div class='ctx'> 			 * been transmitted on the link after link training</div><div class='ctx'> 			 * completion. Using 1 lane RBR should have the maximum</div><div class='hunk'>@@ -204,7 +199,9 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)</div><div class='ctx'> 			udelay(7);</div><div class='ctx'> 			link_enc-&gt;funcs-&gt;fec_set_enable(link_enc, true);</div><div class='ctx'> 			link-&gt;fec_state = dc_link_fec_enabled;</div><div class='del'>-		} else if (link-&gt;fec_state == dc_link_fec_enabled &amp;&amp; !enable) {</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (link-&gt;fec_state == dc_link_fec_enabled) {</div><div class='ctx'> 			link_enc-&gt;funcs-&gt;fec_set_enable(link_enc, false);</div><div class='ctx'> 			link-&gt;fec_state = dc_link_fec_ready;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h<br/>index 1eb0619d6710..58e154494582 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #ifndef __DC_LINK_DP_PHY_H__</div><div class='ctx'> #define __DC_LINK_DP_PHY_H__</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> void dp_enable_link_phy(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	const struct link_resource *link_res,</div><div class='hunk'>@@ -52,7 +52,8 @@ void dp_set_drive_settings(</div><div class='ctx'> enum dc_status dp_set_fec_ready(struct dc_link *link,</div><div class='ctx'> 		const struct link_resource *link_res, bool ready);</div><div class='ctx'> </div><div class='del'>-void dp_set_fec_enable(struct dc_link *link, bool enable);</div><div class='add'>+void dp_set_fec_enable(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res, bool enable);</div><div class='ctx'> </div><div class='ctx'> void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c<br/>index e538c67d3ed9..08e2b572e0ff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c</a></div><div class='hunk'>@@ -272,7 +272,7 @@ void dp_wait_for_training_aux_rd_interval(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	uint32_t wait_in_micro_secs)</div><div class='ctx'> {</div><div class='del'>-	fsleep(wait_in_micro_secs);</div><div class='add'>+	usleep_range_state(wait_in_micro_secs, wait_in_micro_secs, TASK_UNINTERRUPTIBLE);</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",</div><div class='ctx'> 		__func__,</div><div class='hunk'>@@ -329,8 +329,12 @@ static void maximize_lane_settings(const struct link_training_settings *lt_setti</div><div class='ctx'> </div><div class='ctx'> 	if (max_requested.PRE_EMPHASIS &gt; PRE_EMPHASIS_MAX_LEVEL)</div><div class='ctx'> 		max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;</div><div class='del'>-	if (max_requested.FFE_PRESET.settings.level &gt; DP_FFE_PRESET_MAX_LEVEL)</div><div class='del'>-		max_requested.FFE_PRESET.settings.level = DP_FFE_PRESET_MAX_LEVEL;</div><div class='add'>+</div><div class='add'>+	/* Note, we are not checking</div><div class='add'>+	 * if max_requested.FFE_PRESET.settings.level &gt;  DP_FFE_PRESET_MAX_LEVEL,</div><div class='add'>+	 * since FFE_PRESET.settings.level is 4 bits and DP_FFE_PRESET_MAX_LEVEL equals 15,</div><div class='add'>+	 * so FFE_PRESET.settings.level will never be greater than 15.</div><div class='add'>+	 */</div><div class='ctx'> </div><div class='ctx'> 	/* make sure the pre-emphasis matches the voltage swing*/</div><div class='ctx'> 	if (max_requested.PRE_EMPHASIS &gt;</div><div class='hunk'>@@ -511,6 +515,41 @@ bool dp_is_interlane_aligned(union lane_align_status_updated align_status)</div><div class='ctx'> 	return align_status.bits.INTERLANE_ALIGN_DONE == 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dp_check_interlane_aligned(union lane_align_status_updated align_status,</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		uint8_t retries)</div><div class='add'>+{</div><div class='add'>+	/* Take into consideration corner case for DP 1.4a LL Compliance CTS as USB4</div><div class='add'>+	 * has to share encoders unlike DP and USBC</div><div class='add'>+	 */</div><div class='add'>+	return (dp_is_interlane_aligned(align_status) ||</div><div class='add'>+			(link-&gt;skip_fallback_on_link_loss &amp;&amp; retries));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dp_get_eq_aux_rd_interval(</div><div class='add'>+		const struct dc_link *link,</div><div class='add'>+		const struct link_training_settings *lt_settings,</div><div class='add'>+		uint32_t offset,</div><div class='add'>+		uint8_t retries)</div><div class='add'>+{</div><div class='add'>+	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {</div><div class='add'>+		if (offset == 0 &amp;&amp; retries == 1 &amp;&amp; lt_settings-&gt;lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)</div><div class='add'>+			return max(lt_settings-&gt;eq_pattern_time, (uint32_t) DPIA_CLK_SYNC_DELAY);</div><div class='add'>+		else</div><div class='add'>+			return dpia_get_eq_aux_rd_interval(link, lt_settings, offset);</div><div class='add'>+	} else if (is_repeater(lt_settings, offset))</div><div class='add'>+		return dp_translate_training_aux_read_interval(</div><div class='add'>+				link-&gt;dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);</div><div class='add'>+	else</div><div class='add'>+		return lt_settings-&gt;eq_pattern_time;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dp_check_dpcd_reqeust_status(const struct dc_link *link,</div><div class='add'>+		enum dc_status status)</div><div class='add'>+{</div><div class='add'>+	return (status != DC_OK &amp;&amp; link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum link_training_result dp_check_link_loss_status(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	const struct link_training_settings *link_training_setting)</div><div class='hunk'>@@ -697,10 +736,12 @@ void override_training_settings(</div><div class='ctx'> 		lt_settings-&gt;pre_emphasis = overrides-&gt;pre_emphasis;</div><div class='ctx'> 	if (overrides-&gt;post_cursor2 != NULL)</div><div class='ctx'> 		lt_settings-&gt;post_cursor2 = overrides-&gt;post_cursor2;</div><div class='add'>+	if (link-&gt;wa_flags.force_dp_ffe_preset &amp;&amp; !dp_is_lttpr_present(link))</div><div class='add'>+		lt_settings-&gt;ffe_preset = &amp;link-&gt;forced_dp_ffe_preset;</div><div class='ctx'> 	if (overrides-&gt;ffe_preset != NULL)</div><div class='ctx'> 		lt_settings-&gt;ffe_preset = overrides-&gt;ffe_preset;</div><div class='ctx'> 	/* Override HW lane settings with BIOS forced values if present */</div><div class='del'>-	if ((link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='add'>+	if ((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp;</div><div class='ctx'> 			lt_settings-&gt;lttpr_mode == LTTPR_MODE_TRANSPARENT) {</div><div class='ctx'> 		lt_settings-&gt;voltage_swing = &amp;link-&gt;bios_forced_drive_settings.VOLTAGE_SWING;</div><div class='ctx'> 		lt_settings-&gt;pre_emphasis = &amp;link-&gt;bios_forced_drive_settings.PRE_EMPHASIS;</div><div class='hunk'>@@ -744,7 +785,6 @@ void override_training_settings(</div><div class='ctx'> 		lt_settings-&gt;lttpr_mode = LTTPR_MODE_NON_LTTPR;</div><div class='ctx'> </div><div class='ctx'> 	dp_get_lttpr_mode_override(link, &amp;lt_settings-&gt;lttpr_mode);</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum dc_dp_training_pattern decide_cr_training_pattern(</div><div class='hunk'>@@ -760,19 +800,23 @@ enum dc_dp_training_pattern decide_cr_training_pattern(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='ctx'> 		const struct dc_link_settings *link_settings)</div><div class='ctx'> {</div><div class='del'>-	struct link_encoder *link_enc;</div><div class='add'>+	struct link_encoder *link_enc = link_res-&gt;dio_link_enc;</div><div class='ctx'> 	struct encoder_feature_support *enc_caps;</div><div class='ctx'> 	struct dpcd_caps *rx_caps = &amp;link-&gt;dpcd_caps;</div><div class='ctx'> 	enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='del'>-	ASSERT(link_enc);</div><div class='del'>-	enc_caps = &amp;link_enc-&gt;features;</div><div class='del'>-</div><div class='ctx'> 	switch (link_dp_get_encoding_format(link_settings)) {</div><div class='ctx'> 	case DP_8b_10b_ENCODING:</div><div class='add'>+		if (!link-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+			link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+</div><div class='add'>+		if (!link_enc)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		enc_caps = &amp;link_enc-&gt;features;</div><div class='ctx'> 		if (enc_caps-&gt;flags.bits.IS_TPS4_CAPABLE &amp;&amp;</div><div class='ctx'> 				rx_caps-&gt;max_down_spread.bits.TPS4_SUPPORTED)</div><div class='ctx'> 			pattern = DP_TRAINING_PATTERN_SEQUENCE_4;</div><div class='hunk'>@@ -845,13 +889,14 @@ void dp_decide_lane_settings(</div><div class='ctx'> </div><div class='ctx'> void dp_decide_training_settings(</div><div class='ctx'> 		struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='ctx'> 		const struct dc_link_settings *link_settings,</div><div class='ctx'> 		struct link_training_settings *lt_settings)</div><div class='ctx'> {</div><div class='ctx'> 	if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)</div><div class='del'>-		decide_8b_10b_training_settings(link, link_settings, lt_settings);</div><div class='add'>+		decide_8b_10b_training_settings(link, link_res, link_settings, lt_settings);</div><div class='ctx'> 	else if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING)</div><div class='del'>-		decide_128b_132b_training_settings(link, link_settings, lt_settings);</div><div class='add'>+		decide_128b_132b_training_settings(link, link_res, link_settings, lt_settings);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -914,10 +959,10 @@ static enum dc_status configure_lttpr_mode_non_transparent(</div><div class='ctx'> 			/* Driver does not need to train the first hop. Skip DPCD read and clear</div><div class='ctx'> 			 * AUX_RD_INTERVAL for DPTX-to-DPIA hop.</div><div class='ctx'> 			 */</div><div class='del'>-			if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+			if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp; repeater_cnt &gt; 0 &amp;&amp; repeater_cnt &lt; MAX_REPEATER_CNT)</div><div class='ctx'> 				link-&gt;dpcd_caps.lttpr_caps.aux_rd_interval[--repeater_cnt] = 0;</div><div class='ctx'> </div><div class='del'>-			for (repeater_id = repeater_cnt; repeater_id &gt; 0; repeater_id--) {</div><div class='add'>+			for (repeater_id = repeater_cnt; repeater_id &gt; 0 &amp;&amp; repeater_id &lt; MAX_REPEATER_CNT; repeater_id--) {</div><div class='ctx'> 				aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +</div><div class='ctx'> 						((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));</div><div class='ctx'> 				core_link_read_dpcd(</div><div class='hunk'>@@ -969,23 +1014,34 @@ void repeater_training_done(struct dc_link *link, uint32_t offset)</div><div class='ctx'> 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding)</div><div class='add'>+static enum link_training_result dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding)</div><div class='ctx'> {</div><div class='add'>+	enum dc_status status;</div><div class='ctx'> 	uint8_t sink_status = 0;</div><div class='del'>-	uint8_t i;</div><div class='add'>+	uint32_t i;</div><div class='add'>+	uint8_t lttpr_count = dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='add'>+	uint32_t intra_hop_disable_time_ms = (lttpr_count &gt; 0 ? lttpr_count * 300 : 10);</div><div class='add'>+</div><div class='add'>+	// Each hop could theoretically take over 256ms (max 128b/132b AUX RD INTERVAL)</div><div class='add'>+	// To be safe, allow 300ms per LTTPR and 10ms for no LTTPR case</div><div class='ctx'> </div><div class='ctx'> 	/* clear training pattern set */</div><div class='del'>-	dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);</div><div class='add'>+	status = dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);</div><div class='add'>+</div><div class='add'>+	if (dp_check_dpcd_reqeust_status(link, status))</div><div class='add'>+		return LINK_TRAINING_ABORT;</div><div class='ctx'> </div><div class='ctx'> 	if (encoding == DP_128b_132b_ENCODING) {</div><div class='ctx'> 		/* poll for intra-hop disable */</div><div class='del'>-		for (i = 0; i &lt; 10; i++) {</div><div class='add'>+		for (i = 0; i &lt; intra_hop_disable_time_ms; i++) {</div><div class='ctx'> 			if ((core_link_read_dpcd(link, DP_SINK_STATUS, &amp;sink_status, 1) == DC_OK) &amp;&amp;</div><div class='ctx'> 					(sink_status &amp; DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)</div><div class='ctx'> 				break;</div><div class='ctx'> 			fsleep(1000);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return LINK_TRAINING_SUCCESS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum dc_status dpcd_configure_channel_coding(struct dc_link *link,</div><div class='hunk'>@@ -1009,17 +1065,18 @@ enum dc_status dpcd_configure_channel_coding(struct dc_link *link,</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dpcd_set_training_pattern(</div><div class='add'>+enum dc_status dpcd_set_training_pattern(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	enum dc_dp_training_pattern training_pattern)</div><div class='ctx'> {</div><div class='add'>+	enum dc_status status;</div><div class='ctx'> 	union dpcd_training_pattern dpcd_pattern = {0};</div><div class='ctx'> </div><div class='ctx'> 	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =</div><div class='ctx'> 			dp_training_pattern_to_dpcd_training_pattern(</div><div class='ctx'> 					link, training_pattern);</div><div class='ctx'> </div><div class='del'>-	core_link_write_dpcd(</div><div class='add'>+	status = core_link_write_dpcd(</div><div class='ctx'> 		link,</div><div class='ctx'> 		DP_TRAINING_PATTERN_SET,</div><div class='ctx'> 		&amp;dpcd_pattern.raw,</div><div class='hunk'>@@ -1029,6 +1086,8 @@ void dpcd_set_training_pattern(</div><div class='ctx'> 		__func__,</div><div class='ctx'> 		DP_TRAINING_PATTERN_SET,</div><div class='ctx'> 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum dc_status dpcd_set_link_settings(</div><div class='hunk'>@@ -1059,9 +1118,13 @@ enum dc_status dpcd_set_link_settings(</div><div class='ctx'> </div><div class='ctx'> 	status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,</div><div class='ctx'> 		&amp;downspread.raw, sizeof(downspread));</div><div class='add'>+	if (status != DC_OK)</div><div class='add'>+		DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_DOWNSPREAD_CTRL) failed\n", __func__, __LINE__);</div><div class='ctx'> </div><div class='ctx'> 	status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,</div><div class='ctx'> 		&amp;lane_count_set.raw, 1);</div><div class='add'>+	if (status != DC_OK)</div><div class='add'>+		DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LANE_COUNT_SET) failed\n", __func__, __LINE__);</div><div class='ctx'> </div><div class='ctx'> 	if (link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_13 &amp;&amp;</div><div class='ctx'> 			lt_settings-&gt;link_settings.use_link_rate_set == true) {</div><div class='hunk'>@@ -1071,18 +1134,25 @@ enum dc_status dpcd_set_link_settings(</div><div class='ctx'> 		 * MUX chip gets link rate set back before link training.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (link-&gt;connector_signal == SIGNAL_TYPE_EDP) {</div><div class='del'>-			uint8_t supported_link_rates[16];</div><div class='add'>+			uint8_t supported_link_rates[16] = {0};</div><div class='ctx'> </div><div class='ctx'> 			core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,</div><div class='ctx'> 					supported_link_rates, sizeof(supported_link_rates));</div><div class='ctx'> 		}</div><div class='ctx'> 		status = core_link_write_dpcd(link, DP_LINK_BW_SET, &amp;rate, 1);</div><div class='add'>+		if (status != DC_OK)</div><div class='add'>+			DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LINK_BW_SET) failed\n", __func__, __LINE__);</div><div class='add'>+</div><div class='ctx'> 		status = core_link_write_dpcd(link, DP_LINK_RATE_SET,</div><div class='ctx'> 				&amp;lt_settings-&gt;link_settings.link_rate_set, 1);</div><div class='add'>+		if (status != DC_OK)</div><div class='add'>+			DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LINK_RATE_SET) failed\n", __func__, __LINE__);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		rate = get_dpcd_link_rate(&amp;lt_settings-&gt;link_settings);</div><div class='ctx'> </div><div class='ctx'> 		status = core_link_write_dpcd(link, DP_LINK_BW_SET, &amp;rate, 1);</div><div class='add'>+		if (status != DC_OK)</div><div class='add'>+			DC_LOG_ERROR("%s:%d: core_link_write_dpcd (DP_LINK_BW_SET) failed\n", __func__, __LINE__);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (rate) {</div><div class='hunk'>@@ -1181,6 +1251,13 @@ void dpcd_set_lt_pattern_and_lane_settings(</div><div class='ctx'> 	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]</div><div class='ctx'> 		= dpcd_pattern.raw;</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+		dpia_set_tps_notification(</div><div class='add'>+			link,</div><div class='add'>+			lt_settings,</div><div class='add'>+			dpcd_pattern.v1_4.TRAINING_PATTERN_SET,</div><div class='add'>+			offset);</div><div class='add'>+</div><div class='ctx'> 	if (is_repeater(lt_settings, offset)) {</div><div class='ctx'> 		DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",</div><div class='ctx'> 			__func__,</div><div class='hunk'>@@ -1451,7 +1528,8 @@ static enum link_training_result dp_transition_to_video_idle(</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (link-&gt;connector_signal != SIGNAL_TYPE_EDP &amp;&amp; status == LINK_TRAINING_SUCCESS) {</div><div class='ctx'> 			msleep(5);</div><div class='del'>-			status = dp_check_link_loss_status(link, lt_settings);</div><div class='add'>+			if (!link-&gt;skip_fallback_on_link_loss)</div><div class='add'>+				status = dp_check_link_loss_status(link, lt_settings);</div><div class='ctx'> 		}</div><div class='ctx'> 		return status;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1487,6 +1565,7 @@ enum link_training_result dp_perform_link_training(</div><div class='ctx'> 	/* decide training settings */</div><div class='ctx'> 	dp_decide_training_settings(</div><div class='ctx'> 			link,</div><div class='add'>+			link_res,</div><div class='ctx'> 			link_settings,</div><div class='ctx'> 			&amp;lt_settings);</div><div class='ctx'> </div><div class='hunk'>@@ -1500,14 +1579,15 @@ enum link_training_result dp_perform_link_training(</div><div class='ctx'> </div><div class='ctx'> 	/* configure link prior to entering training mode */</div><div class='ctx'> 	dpcd_configure_lttpr_mode(link, &amp;lt_settings);</div><div class='del'>-	dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);</div><div class='add'>+	if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)</div><div class='add'>+		dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);</div><div class='ctx'> 	dpcd_configure_channel_coding(link, &amp;lt_settings);</div><div class='ctx'> </div><div class='ctx'> 	/* enter training mode:</div><div class='ctx'> 	 * Per DP specs starting from here, DPTX device shall not issue</div><div class='ctx'> 	 * Non-LT AUX transactions inside training mode.</div><div class='ctx'> 	 */</div><div class='del'>-	if ((link-&gt;chip_caps &amp; EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp; encoding == DP_8b_10b_ENCODING)</div><div class='add'>+	if (((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &amp;&amp; encoding == DP_8b_10b_ENCODING)</div><div class='ctx'> 		status = dp_perform_fixed_vs_pe_training_sequence(link, link_res, &amp;lt_settings);</div><div class='ctx'> 	else if (encoding == DP_8b_10b_ENCODING)</div><div class='ctx'> 		status = dp_perform_8b_10b_link_training(link, link_res, &amp;lt_settings);</div><div class='hunk'>@@ -1517,7 +1597,9 @@ enum link_training_result dp_perform_link_training(</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> </div><div class='ctx'> 	/* exit training mode */</div><div class='del'>-	dpcd_exit_training_mode(link, encoding);</div><div class='add'>+	if ((dpcd_exit_training_mode(link, encoding) != LINK_TRAINING_SUCCESS || status == LINK_TRAINING_ABORT) &amp;&amp;</div><div class='add'>+			link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+		dpia_training_abort(link, &amp;lt_settings, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* switch to video idle */</div><div class='ctx'> 	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)</div><div class='hunk'>@@ -1587,21 +1669,7 @@ bool perform_link_training_with_retries(</div><div class='ctx'> 			msleep(delay_dp_power_up_in_ms);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (panel_mode == DP_PANEL_MODE_EDP) {</div><div class='del'>-			struct cp_psp *cp_psp = &amp;stream-&gt;ctx-&gt;cp_psp;</div><div class='del'>-</div><div class='del'>-			if (cp_psp &amp;&amp; cp_psp-&gt;funcs.enable_assr) {</div><div class='del'>-				/* ASSR is bound to fail with unsigned PSP</div><div class='del'>-				 * verstage used during devlopment phase.</div><div class='del'>-				 * Report and continue with eDP panel mode to</div><div class='del'>-				 * perform eDP link training with right settings</div><div class='del'>-				 */</div><div class='del'>-				bool result;</div><div class='del'>-				result = cp_psp-&gt;funcs.enable_assr(cp_psp-&gt;handle, link);</div><div class='del'>-				if (!result &amp;&amp; link-&gt;panel_mode != DP_PANEL_MODE_EDP)</div><div class='del'>-					panel_mode = DP_PANEL_MODE_DEFAULT;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+		edp_set_panel_assr(link, pipe_ctx, &amp;panel_mode, true);</div><div class='ctx'> </div><div class='ctx'> 		dp_set_panel_mode(link, panel_mode);</div><div class='ctx'> </div><div class='hunk'>@@ -1609,8 +1677,7 @@ bool perform_link_training_with_retries(</div><div class='ctx'> 			dp_perform_link_training_skip_aux(link, &amp;pipe_ctx-&gt;link_res, &amp;cur_link_settings);</div><div class='ctx'> 			return true;</div><div class='ctx'> 		} else {</div><div class='del'>-			/** @todo Consolidate USB4 DP and DPx.x training. */</div><div class='del'>-			if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {</div><div class='add'>+			if (!link-&gt;dc-&gt;config.consolidated_dpia_dp_lt &amp;&amp; link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {</div><div class='ctx'> 				status = dpia_perform_link_training(</div><div class='ctx'> 						link,</div><div class='ctx'> 						&amp;pipe_ctx-&gt;link_res,</div><div class='hunk'>@@ -1639,8 +1706,17 @@ bool perform_link_training_with_retries(</div><div class='ctx'> 			dp_trace_lt_total_count_increment(link, false);</div><div class='ctx'> 			dp_trace_lt_result_update(link, status, false);</div><div class='ctx'> 			dp_trace_set_lt_end_timestamp(link, false);</div><div class='del'>-			if (status == LINK_TRAINING_SUCCESS &amp;&amp; !is_link_bw_low)</div><div class='add'>+			if (status == LINK_TRAINING_SUCCESS &amp;&amp; !is_link_bw_low) {</div><div class='add'>+				// Update verified link settings to current one</div><div class='add'>+				// Because DPIA LT might fallback to lower link setting.</div><div class='add'>+				if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp;</div><div class='add'>+						stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='add'>+					link-&gt;verified_link_cap.link_rate = link-&gt;cur_link_settings.link_rate;</div><div class='add'>+					link-&gt;verified_link_cap.lane_count = link-&gt;cur_link_settings.lane_count;</div><div class='add'>+					dm_helpers_dp_mst_update_branch_bandwidth(link-&gt;ctx, link);</div><div class='add'>+				}</div><div class='ctx'> 				return true;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		fail_count++;</div><div class='hunk'>@@ -1653,6 +1729,15 @@ bool perform_link_training_with_retries(</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp;</div><div class='add'>+				stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST &amp;&amp;</div><div class='add'>+				!link-&gt;dc-&gt;config.enable_dpia_pre_training) {</div><div class='add'>+			if (j == (attempts - 1))</div><div class='add'>+				do_fallback = true;</div><div class='add'>+			else</div><div class='add'>+				do_fallback = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (j == (attempts - 1)) {</div><div class='ctx'> 			DC_LOG_WARNING(</div><div class='ctx'> 				"%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",</div><div class='hunk'>@@ -1673,8 +1758,7 @@ bool perform_link_training_with_retries(</div><div class='ctx'> 		if (status == LINK_TRAINING_ABORT) {</div><div class='ctx'> 			enum dc_connection_type type = dc_connection_none;</div><div class='ctx'> </div><div class='del'>-			link_detect_connection_type(link, &amp;type);</div><div class='del'>-			if (type == dc_connection_none) {</div><div class='add'>+			if (link_detect_connection_type(link, &amp;type) &amp;&amp; type == dc_connection_none) {</div><div class='ctx'> 				DC_LOG_HW_LINK_TRAINING("%s: Aborting training because sink unplugged\n", __func__);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h<br/>index 851bd17317a0..ce52de22ab7a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> #ifndef __DC_LINK_DP_TRAINING_H__</div><div class='ctx'> #define __DC_LINK_DP_TRAINING_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> bool perform_link_training_with_retries(</div><div class='ctx'> 	const struct dc_link_settings *link_setting,</div><div class='hunk'>@@ -55,7 +55,7 @@ void dp_set_hw_test_pattern(</div><div class='ctx'> 		uint8_t *custom_pattern,</div><div class='ctx'> 		uint32_t custom_pattern_size);</div><div class='ctx'> </div><div class='del'>-void dpcd_set_training_pattern(</div><div class='add'>+enum dc_status dpcd_set_training_pattern(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	enum dc_dp_training_pattern training_pattern);</div><div class='ctx'> </div><div class='hunk'>@@ -104,6 +104,7 @@ void start_clock_recovery_pattern_early(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> void dp_decide_training_settings(</div><div class='ctx'> 		struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='ctx'> 		const struct dc_link_settings *link_settings,</div><div class='ctx'> 		struct link_training_settings *lt_settings);</div><div class='ctx'> </div><div class='hunk'>@@ -117,6 +118,7 @@ enum dc_dp_training_pattern decide_cr_training_pattern(</div><div class='ctx'> 		const struct dc_link_settings *link_settings);</div><div class='ctx'> </div><div class='ctx'> enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='ctx'> 		const struct dc_link_settings *link_settings);</div><div class='ctx'> </div><div class='ctx'> enum lttpr_mode dp_decide_lttpr_mode(struct dc_link *link,</div><div class='hunk'>@@ -182,4 +184,18 @@ uint32_t dp_translate_training_aux_read_interval(</div><div class='ctx'> </div><div class='ctx'> uint8_t dp_get_nibble_at_index(const uint8_t *buf,</div><div class='ctx'> 	uint32_t index);</div><div class='add'>+</div><div class='add'>+bool dp_check_interlane_aligned(union lane_align_status_updated align_status,</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		uint8_t retries);</div><div class='add'>+</div><div class='add'>+uint32_t dp_get_eq_aux_rd_interval(</div><div class='add'>+		const struct dc_link *link,</div><div class='add'>+		const struct link_training_settings *lt_settings,</div><div class='add'>+		uint32_t offset,</div><div class='add'>+		uint8_t retries);</div><div class='add'>+</div><div class='add'>+bool dp_check_dpcd_reqeust_status(const struct dc_link *link,</div><div class='add'>+		enum dc_status status);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_LINK_DP_TRAINING_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c<br/>index db87cfe37b5c..11565f187ac7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c</a></div><div class='hunk'>@@ -204,6 +204,7 @@ enum link_training_result dp_perform_128b_132b_link_training(</div><div class='ctx'> 		struct link_training_settings legacy_settings;</div><div class='ctx'> </div><div class='ctx'> 		decide_8b_10b_training_settings(link,</div><div class='add'>+				link_res,</div><div class='ctx'> 				&amp;lt_settings-&gt;link_settings,</div><div class='ctx'> 				&amp;legacy_settings);</div><div class='ctx'> 		return dp_perform_8b_10b_link_training(link, link_res, &amp;legacy_settings);</div><div class='hunk'>@@ -227,6 +228,7 @@ enum link_training_result dp_perform_128b_132b_link_training(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void decide_128b_132b_training_settings(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='ctx'> 		const struct dc_link_settings *link_settings,</div><div class='ctx'> 		struct link_training_settings *lt_settings)</div><div class='ctx'> {</div><div class='hunk'>@@ -238,7 +240,7 @@ void decide_128b_132b_training_settings(struct dc_link *link,</div><div class='ctx'> 			LINK_SPREAD_05_DOWNSPREAD_30KHZ;</div><div class='ctx'> </div><div class='ctx'> 	lt_settings-&gt;pattern_for_cr = decide_cr_training_pattern(link_settings);</div><div class='del'>-	lt_settings-&gt;pattern_for_eq = decide_eq_training_pattern(link, link_settings);</div><div class='add'>+	lt_settings-&gt;pattern_for_eq = decide_eq_training_pattern(link, link_res, link_settings);</div><div class='ctx'> 	lt_settings-&gt;eq_pattern_time = 2500;</div><div class='ctx'> 	lt_settings-&gt;eq_wait_time_limit = 400000;</div><div class='ctx'> 	lt_settings-&gt;eq_loop_count_limit = 20;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h<br/>index 2147f24efc8b..901a42edafa1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.h</a></div><div class='hunk'>@@ -34,6 +34,7 @@ enum link_training_result dp_perform_128b_132b_link_training(</div><div class='ctx'> 		struct link_training_settings *lt_settings);</div><div class='ctx'> </div><div class='ctx'> void decide_128b_132b_training_settings(struct dc_link *link,</div><div class='add'>+		const struct link_resource *link_res,</div><div class='ctx'> 		const struct dc_link_settings *link_settings,</div><div class='ctx'> 		struct link_training_settings *lt_settings);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c<br/>index 2b4c15b0b407..66d0fb1b9b9d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c</a></div><div class='hunk'>@@ -35,22 +35,41 @@</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='ctx'> </div><div class='add'>+static void get_default_8b_10b_lttpr_aux_rd_interval(</div><div class='add'>+		union training_aux_rd_interval *training_rd_interval)</div><div class='add'>+{</div><div class='add'>+	/* LTTPR are required to program DPCD 0000Eh to 0x4 (16ms) upon AUX</div><div class='add'>+	 * read reply to this register. Since old sinks with DPCD rev 1.1</div><div class='add'>+	 * and earlier may not support this register, assume the mandatory</div><div class='add'>+	 * value is programmed by the LTTPR to avoid AUX timeout issues.</div><div class='add'>+	 */</div><div class='add'>+	training_rd_interval-&gt;raw = 0x4;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int32_t get_cr_training_aux_rd_interval(struct dc_link *link,</div><div class='del'>-		const struct dc_link_settings *link_settings)</div><div class='add'>+		const struct dc_link_settings *link_settings,</div><div class='add'>+		enum lttpr_mode lttpr_mode)</div><div class='ctx'> {</div><div class='ctx'> 	union training_aux_rd_interval training_rd_interval;</div><div class='ctx'> 	uint32_t wait_in_micro_secs = 100;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;training_rd_interval, 0, sizeof(training_rd_interval));</div><div class='del'>-	if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &amp;&amp;</div><div class='del'>-			link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_12) {</div><div class='del'>-		core_link_read_dpcd(</div><div class='del'>-				link,</div><div class='del'>-				DP_TRAINING_AUX_RD_INTERVAL,</div><div class='del'>-				(uint8_t *)&amp;training_rd_interval,</div><div class='del'>-				sizeof(training_rd_interval));</div><div class='del'>-		if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)</div><div class='del'>-			wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;</div><div class='add'>+	if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {</div><div class='add'>+		if (link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_12)</div><div class='add'>+			core_link_read_dpcd(</div><div class='add'>+					link,</div><div class='add'>+					DP_TRAINING_AUX_RD_INTERVAL,</div><div class='add'>+					(uint8_t *)&amp;training_rd_interval,</div><div class='add'>+					sizeof(training_rd_interval));</div><div class='add'>+		else if (dp_is_lttpr_present(link))</div><div class='add'>+			get_default_8b_10b_lttpr_aux_rd_interval(&amp;training_rd_interval);</div><div class='add'>+</div><div class='add'>+		if (training_rd_interval.raw != 0) {</div><div class='add'>+			if (lttpr_mode != LTTPR_MODE_NON_TRANSPARENT)</div><div class='add'>+				wait_in_micro_secs = 400;</div><div class='add'>+			if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)</div><div class='add'>+				wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return wait_in_micro_secs;</div><div class='ctx'> }</div><div class='hunk'>@@ -68,13 +87,15 @@ static uint32_t get_eq_training_aux_rd_interval(</div><div class='ctx'> 				DP_128B132B_TRAINING_AUX_RD_INTERVAL,</div><div class='ctx'> 				(uint8_t *)&amp;training_rd_interval,</div><div class='ctx'> 				sizeof(training_rd_interval));</div><div class='del'>-	} else if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &amp;&amp;</div><div class='del'>-			link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_12) {</div><div class='del'>-		core_link_read_dpcd(</div><div class='del'>-				link,</div><div class='del'>-				DP_TRAINING_AUX_RD_INTERVAL,</div><div class='del'>-				(uint8_t *)&amp;training_rd_interval,</div><div class='del'>-				sizeof(training_rd_interval));</div><div class='add'>+	} else if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {</div><div class='add'>+		if (link-&gt;dpcd_caps.dpcd_rev.raw &gt;= DPCD_REV_12)</div><div class='add'>+			core_link_read_dpcd(</div><div class='add'>+					link,</div><div class='add'>+					DP_TRAINING_AUX_RD_INTERVAL,</div><div class='add'>+					(uint8_t *)&amp;training_rd_interval,</div><div class='add'>+					sizeof(training_rd_interval));</div><div class='add'>+		else if (dp_is_lttpr_present(link))</div><div class='add'>+			get_default_8b_10b_lttpr_aux_rd_interval(&amp;training_rd_interval);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) {</div><div class='hunk'>@@ -90,7 +111,8 @@ static uint32_t get_eq_training_aux_rd_interval(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void decide_8b_10b_training_settings(</div><div class='del'>-	 struct dc_link *link,</div><div class='add'>+	struct dc_link *link,</div><div class='add'>+	const struct link_resource *link_res,</div><div class='ctx'> 	const struct dc_link_settings *link_setting,</div><div class='ctx'> 	struct link_training_settings *lt_settings)</div><div class='ctx'> {</div><div class='hunk'>@@ -110,16 +132,24 @@ void decide_8b_10b_training_settings(</div><div class='ctx'> 	 */</div><div class='ctx'> 	lt_settings-&gt;link_settings.link_spread = link-&gt;dp_ss_off ?</div><div class='ctx'> 			LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;</div><div class='del'>-	lt_settings-&gt;cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);</div><div class='ctx'> 	lt_settings-&gt;eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);</div><div class='ctx'> 	lt_settings-&gt;pattern_for_cr = decide_cr_training_pattern(link_setting);</div><div class='del'>-	lt_settings-&gt;pattern_for_eq = decide_eq_training_pattern(link, link_setting);</div><div class='add'>+	lt_settings-&gt;pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting);</div><div class='ctx'> 	lt_settings-&gt;enhanced_framing = 1;</div><div class='ctx'> 	lt_settings-&gt;should_set_fec_ready = true;</div><div class='ctx'> 	lt_settings-&gt;disallow_per_lane_settings = true;</div><div class='ctx'> 	lt_settings-&gt;always_match_dpcd_with_hw_lane_settings = true;</div><div class='ctx'> 	lt_settings-&gt;lttpr_mode = dp_decide_8b_10b_lttpr_mode(link);</div><div class='add'>+	lt_settings-&gt;cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings-&gt;lttpr_mode);</div><div class='ctx'> 	dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings-&gt;hw_lane_settings, lt_settings-&gt;dpcd_lane_settings);</div><div class='add'>+</div><div class='add'>+	/* Some embedded LTTPRs rely on receiving TPS2 before LT to interop reliably with sensitive VGA dongles</div><div class='add'>+	 * This allows these LTTPRs to minimize freq/phase and skew variation during lock and deskew sequences</div><div class='add'>+	 */</div><div class='add'>+	if ((link-&gt;chip_caps &amp; AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) ==</div><div class='add'>+			AMD_EXT_DISPLAY_PATH_CAPS__DP_EARLY_8B10B_TPS2) {</div><div class='add'>+		lt_settings-&gt;lttpr_early_tps2 = true;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link)</div><div class='hunk'>@@ -151,12 +181,49 @@ enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link)</div><div class='ctx'> 	return LTTPR_MODE_NON_LTTPR;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(struct dc_link *link,</div><div class='add'>+	const struct link_resource *link_res,</div><div class='add'>+	struct link_training_settings *lt_settings,</div><div class='add'>+	uint32_t lttpr_count)</div><div class='add'>+{</div><div class='add'>+	/* Vendor-specific LTTPR early TPS2 sequence:</div><div class='add'>+	* 1. Output TPS2</div><div class='add'>+	* 2. Wait 400us</div><div class='add'>+	* 3. Set link settings as usual</div><div class='add'>+	* 4. Write TPS1 to DP_TRAINING_PATTERN_SET_PHY_REPEATERx targeting LTTPR closest to host</div><div class='add'>+	* 5. Wait 1ms</div><div class='add'>+	* 6. Begin link training as usual</div><div class='add'>+	* */</div><div class='add'>+</div><div class='add'>+	uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count);</div><div class='add'>+</div><div class='add'>+	union dpcd_training_pattern dpcd_pattern = {0};</div><div class='add'>+</div><div class='add'>+	dpcd_pattern.v1_4.TRAINING_PATTERN_SET = 1;</div><div class='add'>+	dpcd_pattern.v1_4.SCRAMBLING_DISABLE = 1;</div><div class='add'>+</div><div class='add'>+	DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS2. Wait 400us.\n", __func__);</div><div class='add'>+</div><div class='add'>+	dp_set_hw_training_pattern(link, link_res, DP_TRAINING_PATTERN_SEQUENCE_2, DPRX);</div><div class='add'>+</div><div class='add'>+	dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);</div><div class='add'>+</div><div class='add'>+	udelay(400);</div><div class='add'>+</div><div class='add'>+	dpcd_set_link_settings(link, lt_settings);</div><div class='add'>+</div><div class='add'>+	core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + closest_lttpr_address_offset, &amp;dpcd_pattern.raw, 1);</div><div class='add'>+</div><div class='add'>+	udelay(1000);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> enum link_training_result perform_8b_10b_clock_recovery_sequence(</div><div class='ctx'> 	struct dc_link *link,</div><div class='ctx'> 	const struct link_resource *link_res,</div><div class='ctx'> 	struct link_training_settings *lt_settings,</div><div class='ctx'> 	uint32_t offset)</div><div class='ctx'> {</div><div class='add'>+	enum dc_status status;</div><div class='ctx'> 	uint32_t retries_cr;</div><div class='ctx'> 	uint32_t retry_count;</div><div class='ctx'> 	uint32_t wait_time_microsec;</div><div class='hunk'>@@ -216,7 +283,7 @@ enum link_training_result perform_8b_10b_clock_recovery_sequence(</div><div class='ctx'> 		/* 4. Read lane status and requested drive</div><div class='ctx'> 		* settings as set by the sink</div><div class='ctx'> 		*/</div><div class='del'>-		dp_get_lane_status_and_lane_adjust(</div><div class='add'>+		status = dp_get_lane_status_and_lane_adjust(</div><div class='ctx'> 				link,</div><div class='ctx'> 				lt_settings,</div><div class='ctx'> 				dpcd_lane_status,</div><div class='hunk'>@@ -224,6 +291,9 @@ enum link_training_result perform_8b_10b_clock_recovery_sequence(</div><div class='ctx'> 				dpcd_lane_adjust,</div><div class='ctx'> 				offset);</div><div class='ctx'> </div><div class='add'>+		if (dp_check_dpcd_reqeust_status(link, status))</div><div class='add'>+			return LINK_TRAINING_ABORT;</div><div class='add'>+</div><div class='ctx'> 		/* 5. check CR done*/</div><div class='ctx'> 		if (dp_is_cr_done(lane_count, dpcd_lane_status)) {</div><div class='ctx'> 			DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__);</div><div class='hunk'>@@ -273,6 +343,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(</div><div class='ctx'> 	struct link_training_settings *lt_settings,</div><div class='ctx'> 	uint32_t offset)</div><div class='ctx'> {</div><div class='add'>+	enum dc_status status;</div><div class='ctx'> 	enum dc_dp_training_pattern tr_pattern;</div><div class='ctx'> 	uint32_t retries_ch_eq;</div><div class='ctx'> 	uint32_t wait_time_microsec;</div><div class='hunk'>@@ -308,12 +379,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(</div><div class='ctx'> 			dpcd_set_lane_settings(link, lt_settings, offset);</div><div class='ctx'> </div><div class='ctx'> 		/* 3. wait for receiver to lock-on*/</div><div class='del'>-		wait_time_microsec = lt_settings-&gt;eq_pattern_time;</div><div class='del'>-</div><div class='del'>-		if (is_repeater(lt_settings, offset))</div><div class='del'>-			wait_time_microsec =</div><div class='del'>-					dp_translate_training_aux_read_interval(</div><div class='del'>-						link-&gt;dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);</div><div class='add'>+		wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, retries_ch_eq);</div><div class='ctx'> </div><div class='ctx'> 		dp_wait_for_training_aux_rd_interval(</div><div class='ctx'> 				link,</div><div class='hunk'>@@ -322,7 +388,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(</div><div class='ctx'> 		/* 4. Read lane status and requested</div><div class='ctx'> 		 * drive settings as set by the sink*/</div><div class='ctx'> </div><div class='del'>-		dp_get_lane_status_and_lane_adjust(</div><div class='add'>+		status = dp_get_lane_status_and_lane_adjust(</div><div class='ctx'> 			link,</div><div class='ctx'> 			lt_settings,</div><div class='ctx'> 			dpcd_lane_status,</div><div class='hunk'>@@ -330,6 +396,9 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(</div><div class='ctx'> 			dpcd_lane_adjust,</div><div class='ctx'> 			offset);</div><div class='ctx'> </div><div class='add'>+		if (dp_check_dpcd_reqeust_status(link, status))</div><div class='add'>+			return LINK_TRAINING_ABORT;</div><div class='add'>+</div><div class='ctx'> 		/* 5. check CR done*/</div><div class='ctx'> 		if (!dp_is_cr_done(lane_count, dpcd_lane_status))</div><div class='ctx'> 			return dpcd_lane_status[0].bits.CR_DONE_0 ?</div><div class='hunk'>@@ -339,7 +408,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(</div><div class='ctx'> 		/* 6. check CHEQ done*/</div><div class='ctx'> 		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &amp;&amp;</div><div class='ctx'> 				dp_is_symbol_locked(lane_count, dpcd_lane_status) &amp;&amp;</div><div class='del'>-				dp_is_interlane_aligned(dpcd_lane_status_updated))</div><div class='add'>+				dp_check_interlane_aligned(dpcd_lane_status_updated, link, retries_ch_eq))</div><div class='ctx'> 			return LINK_TRAINING_SUCCESS;</div><div class='ctx'> </div><div class='ctx'> 		/* 7. update VS/PE/PC2 in lt_settings*/</div><div class='hunk'>@@ -358,7 +427,7 @@ enum link_training_result dp_perform_8b_10b_link_training(</div><div class='ctx'> {</div><div class='ctx'> 	enum link_training_result status = LINK_TRAINING_SUCCESS;</div><div class='ctx'> </div><div class='del'>-	uint8_t repeater_cnt;</div><div class='add'>+	uint8_t repeater_cnt = dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='ctx'> 	uint8_t repeater_id;</div><div class='ctx'> 	uint8_t lane = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -366,14 +435,16 @@ enum link_training_result dp_perform_8b_10b_link_training(</div><div class='ctx'> 		start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);</div><div class='ctx'> </div><div class='ctx'> 	/* 1. set link rate, lane count and spread. */</div><div class='del'>-	dpcd_set_link_settings(link, lt_settings);</div><div class='add'>+	if (lt_settings-&gt;lttpr_early_tps2)</div><div class='add'>+		set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(link, link_res, lt_settings, repeater_cnt);</div><div class='add'>+	else</div><div class='add'>+		dpcd_set_link_settings(link, lt_settings);</div><div class='ctx'> </div><div class='ctx'> 	if (lt_settings-&gt;lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {</div><div class='ctx'> </div><div class='ctx'> 		/* 2. perform link training (set link training done</div><div class='ctx'> 		 *  to false is done as well)</div><div class='ctx'> 		 */</div><div class='del'>-		repeater_cnt = dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='ctx'> </div><div class='ctx'> 		for (repeater_id = repeater_cnt; (repeater_id &gt; 0 &amp;&amp; status == LINK_TRAINING_SUCCESS);</div><div class='ctx'> 				repeater_id--) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h<br/>index d26de15ce954..ea0de701d83f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.h</a></div><div class='hunk'>@@ -54,7 +54,8 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(</div><div class='ctx'> enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link);</div><div class='ctx'> </div><div class='ctx'> void decide_8b_10b_training_settings(</div><div class='del'>-	 struct dc_link *link,</div><div class='add'>+	struct dc_link *link,</div><div class='add'>+	const struct link_resource *link_res,</div><div class='ctx'> 	const struct dc_link_settings *link_setting,</div><div class='ctx'> 	struct link_training_settings *lt_settings);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c<br/>index 4c6b886a9da8..f99d26290bc0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c</a></div><div class='hunk'>@@ -39,6 +39,7 @@ bool dp_perform_link_training_skip_aux(</div><div class='ctx'> </div><div class='ctx'> 	dp_decide_training_settings(</div><div class='ctx'> 			link,</div><div class='add'>+			link_res,</div><div class='ctx'> 			link_setting,</div><div class='ctx'> 			&amp;lt_settings);</div><div class='ctx'> 	override_training_settings(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c<br/>index 5d36bab0029c..603537ffd128 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c</a></div><div class='hunk'>@@ -43,9 +43,6 @@</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='ctx'> </div><div class='del'>-/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */</div><div class='del'>-#define DPIA_CLK_SYNC_DELAY 16000</div><div class='del'>-</div><div class='ctx'> /* Extend interval between training status checks for manual testing. */</div><div class='ctx'> #define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US 60000000</div><div class='ctx'> </div><div class='hunk'>@@ -113,6 +110,7 @@ static enum link_training_result dpia_configure_link(</div><div class='ctx'> </div><div class='ctx'> 	dp_decide_training_settings(</div><div class='ctx'> 		link,</div><div class='add'>+		link_res,</div><div class='ctx'> 		link_setting,</div><div class='ctx'> 		lt_settings);</div><div class='ctx'> </div><div class='hunk'>@@ -132,11 +130,14 @@ static enum link_training_result dpia_configure_link(</div><div class='ctx'> 	if (status != DC_OK &amp;&amp; link-&gt;is_hpd_pending)</div><div class='ctx'> 		return LINK_TRAINING_ABORT;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;preferred_training_settings.fec_enable != NULL)</div><div class='del'>-		fec_enable = *link-&gt;preferred_training_settings.fec_enable;</div><div class='del'>-	else</div><div class='del'>-		fec_enable = true;</div><div class='del'>-	status = dp_set_fec_ready(link, link_res, fec_enable);</div><div class='add'>+	if (link_dp_get_encoding_format(link_setting) == DP_8b_10b_ENCODING) {</div><div class='add'>+		if (link-&gt;preferred_training_settings.fec_enable != NULL)</div><div class='add'>+			fec_enable = *link-&gt;preferred_training_settings.fec_enable;</div><div class='add'>+		else</div><div class='add'>+			fec_enable = true;</div><div class='add'>+		status = dp_set_fec_ready(link, link_res, fec_enable);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (status != DC_OK &amp;&amp; link-&gt;is_hpd_pending)</div><div class='ctx'> 		return LINK_TRAINING_ABORT;</div><div class='ctx'> </div><div class='hunk'>@@ -291,7 +292,7 @@ static enum link_training_result dpia_training_cr_non_transparent(</div><div class='ctx'> {</div><div class='ctx'> 	enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;</div><div class='ctx'> 	uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */</div><div class='del'>-	enum dc_status status;</div><div class='add'>+	enum dc_status status = DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	uint32_t retries_cr = 0; /* Number of consecutive attempts with same VS or PE. */</div><div class='ctx'> 	uint32_t retry_count = 0;</div><div class='ctx'> 	uint32_t wait_time_microsec = TRAINING_AUX_RD_INTERVAL; /* From DP spec, CR read interval is always 100us. */</div><div class='hunk'>@@ -430,10 +431,6 @@ static enum link_training_result dpia_training_cr_non_transparent(</div><div class='ctx'> 		retry_count++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Abort link training if clock recovery failed due to HPD unplug. */</div><div class='del'>-	if (link-&gt;is_hpd_pending)</div><div class='del'>-		result = LINK_TRAINING_ABORT;</div><div class='del'>-</div><div class='ctx'> 	DC_LOG_HW_LINK_TRAINING(</div><div class='ctx'> 		"%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n - status(%d)\n",</div><div class='ctx'> 		__func__,</div><div class='hunk'>@@ -537,10 +534,6 @@ static enum link_training_result dpia_training_cr_transparent(</div><div class='ctx'> 		retry_count++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Abort link training if clock recovery failed due to HPD unplug. */</div><div class='del'>-	if (link-&gt;is_hpd_pending)</div><div class='del'>-		result = LINK_TRAINING_ABORT;</div><div class='del'>-</div><div class='ctx'> 	DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) clock recovery\n -hop(%d)\n - result(%d)\n - retries(%d)\n",</div><div class='ctx'> 		__func__,</div><div class='ctx'> 		link-&gt;link_id.enum_id - ENUM_ID_1,</div><div class='hunk'>@@ -574,28 +567,6 @@ static enum link_training_result dpia_training_cr_phase(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* Return status read interval during equalization phase. */</div><div class='del'>-static uint32_t dpia_get_eq_aux_rd_interval(</div><div class='del'>-		const struct dc_link *link,</div><div class='del'>-		const struct link_training_settings *lt_settings,</div><div class='del'>-		uint32_t hop)</div><div class='del'>-{</div><div class='del'>-	uint32_t wait_time_microsec;</div><div class='del'>-</div><div class='del'>-	if (hop == DPRX)</div><div class='del'>-		wait_time_microsec = lt_settings-&gt;eq_pattern_time;</div><div class='del'>-	else</div><div class='del'>-		wait_time_microsec =</div><div class='del'>-				dp_translate_training_aux_read_interval(</div><div class='del'>-					link-&gt;dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);</div><div class='del'>-</div><div class='del'>-	/* Check debug option for extending aux read interval. */</div><div class='del'>-	if (link-&gt;dc-&gt;debug.dpia_debug.bits.extend_aux_rd_interval)</div><div class='del'>-		wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;</div><div class='del'>-</div><div class='del'>-	return wait_time_microsec;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* Execute equalization phase of link training for specified hop in display</div><div class='ctx'>  * path in non-transparent mode:</div><div class='ctx'>  * - driver issues both DPCD and SET_CONFIG transactions.</div><div class='hunk'>@@ -617,7 +588,7 @@ static enum link_training_result dpia_training_eq_non_transparent(</div><div class='ctx'> 	enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;</div><div class='ctx'> 	uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */</div><div class='ctx'> 	uint32_t retries_eq = 0;</div><div class='del'>-	enum dc_status status;</div><div class='add'>+	enum dc_status status = DC_ERROR_UNEXPECTED;</div><div class='ctx'> 	enum dc_dp_training_pattern tr_pattern;</div><div class='ctx'> 	uint32_t wait_time_microsec = 0;</div><div class='ctx'> 	enum dc_lane_count lane_count = lt_settings-&gt;link_settings.lane_count;</div><div class='hunk'>@@ -731,10 +702,6 @@ static enum link_training_result dpia_training_eq_non_transparent(</div><div class='ctx'> 				lt_settings-&gt;hw_lane_settings, lt_settings-&gt;dpcd_lane_settings);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Abort link training if equalization failed due to HPD unplug. */</div><div class='del'>-	if (link-&gt;is_hpd_pending)</div><div class='del'>-		result = LINK_TRAINING_ABORT;</div><div class='del'>-</div><div class='ctx'> 	DC_LOG_HW_LINK_TRAINING(</div><div class='ctx'> 		"%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n - status(%d)\n",</div><div class='ctx'> 		__func__,</div><div class='hunk'>@@ -822,10 +789,6 @@ static enum link_training_result dpia_training_eq_transparent(</div><div class='ctx'> 				lt_settings-&gt;hw_lane_settings, lt_settings-&gt;dpcd_lane_settings);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Abort link training if equalization failed due to HPD unplug. */</div><div class='del'>-	if (link-&gt;is_hpd_pending)</div><div class='del'>-		result = LINK_TRAINING_ABORT;</div><div class='del'>-</div><div class='ctx'> 	DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) equalization\n - hop(%d)\n - result(%d)\n - retries(%d)\n",</div><div class='ctx'> 		__func__,</div><div class='ctx'> 		link-&gt;link_id.enum_id - ENUM_ID_1,</div><div class='hunk'>@@ -952,6 +915,22 @@ static enum link_training_result dpia_training_end(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Return status read interval during equalization phase. */</div><div class='add'>+uint32_t dpia_get_eq_aux_rd_interval(</div><div class='add'>+		const struct dc_link *link,</div><div class='add'>+		const struct link_training_settings *lt_settings,</div><div class='add'>+		uint32_t hop)</div><div class='add'>+{</div><div class='add'>+	/* Check debug option for extending aux read interval. */</div><div class='add'>+	if (link-&gt;dc-&gt;debug.dpia_debug.bits.extend_aux_rd_interval)</div><div class='add'>+		return DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US;</div><div class='add'>+	else if (hop == DPRX)</div><div class='add'>+		return lt_settings-&gt;eq_pattern_time;</div><div class='add'>+	else</div><div class='add'>+		return dp_translate_training_aux_read_interval(</div><div class='add'>+					link-&gt;dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* When aborting training of specified hop in display path, clean up by:</div><div class='ctx'>  * - Attempting to clear DPCD TRAINING_PATTERN_SET, LINK_BW_SET and LANE_COUNT_SET.</div><div class='ctx'>  * - Sending SET_CONFIG(SET_LINK) with lane count and link rate set to 0.</div><div class='hunk'>@@ -959,7 +938,7 @@ static enum link_training_result dpia_training_end(</div><div class='ctx'>  * @param link DPIA link being trained.</div><div class='ctx'>  * @param hop Hop in display path. DPRX = 0.</div><div class='ctx'>  */</div><div class='del'>-static void dpia_training_abort(</div><div class='add'>+void dpia_training_abort(</div><div class='ctx'> 		struct dc_link *link,</div><div class='ctx'> 		struct link_training_settings *lt_settings,</div><div class='ctx'> 		uint32_t hop)</div><div class='hunk'>@@ -984,7 +963,26 @@ static void dpia_training_abort(</div><div class='ctx'> 	core_link_write_dpcd(link, dpcd_tps_offset, &amp;data, 1);</div><div class='ctx'> 	core_link_write_dpcd(link, DP_LINK_BW_SET, &amp;data, 1);</div><div class='ctx'> 	core_link_write_dpcd(link, DP_LANE_COUNT_SET, &amp;data, 1);</div><div class='del'>-	core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data);</div><div class='add'>+</div><div class='add'>+	if (!link-&gt;dc-&gt;config.consolidated_dpia_dp_lt)</div><div class='add'>+		core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dpia_set_tps_notification(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		const struct link_training_settings *lt_settings,</div><div class='add'>+		uint8_t pattern,</div><div class='add'>+		uint32_t hop)</div><div class='add'>+{</div><div class='add'>+	uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */</div><div class='add'>+</div><div class='add'>+	if (lt_settings-&gt;lttpr_mode != LTTPR_MODE_NON_TRANSPARENT || pattern == DPCD_TRAINING_PATTERN_VIDEOIDLE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	repeater_cnt = dp_parse_lttpr_repeater_count(link-&gt;dpcd_caps.lttpr_caps.phy_repeater_cnt);</div><div class='add'>+</div><div class='add'>+	if (hop != repeater_cnt)</div><div class='add'>+		dc_process_dmub_dpia_set_tps_notification(link-&gt;ctx-&gt;dc, link-&gt;link_index, pattern);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum link_training_result dpia_perform_link_training(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h<br/>index b39fb9faf1c2..9f4eceb494c2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h</a></div><div class='hunk'>@@ -28,6 +28,9 @@</div><div class='ctx'> #define __DC_LINK_DP_TRAINING_DPIA_H__</div><div class='ctx'> #include "link_dp_training.h"</div><div class='ctx'> </div><div class='add'>+/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */</div><div class='add'>+#define DPIA_CLK_SYNC_DELAY 16000</div><div class='add'>+</div><div class='ctx'> /* Train DP tunneling link for USB4 DPIA display endpoint.</div><div class='ctx'>  * DPIA equivalent of dc_link_dp_perfrorm_link_training.</div><div class='ctx'>  * Aborts link training upon detection of sink unplug.</div><div class='hunk'>@@ -38,4 +41,20 @@ enum link_training_result dpia_perform_link_training(</div><div class='ctx'> 	const struct dc_link_settings *link_setting,</div><div class='ctx'> 	bool skip_video_pattern);</div><div class='ctx'> </div><div class='add'>+void dpia_training_abort(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		struct link_training_settings *lt_settings,</div><div class='add'>+		uint32_t hop);</div><div class='add'>+</div><div class='add'>+uint32_t dpia_get_eq_aux_rd_interval(</div><div class='add'>+		const struct dc_link *link,</div><div class='add'>+		const struct link_training_settings *lt_settings,</div><div class='add'>+		uint32_t hop);</div><div class='add'>+</div><div class='add'>+void dpia_set_tps_notification(</div><div class='add'>+		struct dc_link *link,</div><div class='add'>+		const struct link_training_settings *lt_settings,</div><div class='add'>+		uint8_t pattern,</div><div class='add'>+		uint32_t offset);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_LINK_DP_TRAINING_DPIA_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c<br/>index b5cf75975fff..ce174ce5579c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c</a></div><div class='hunk'>@@ -270,7 +270,8 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(</div><div class='ctx'> </div><div class='ctx'> 	rate = get_dpcd_link_rate(&amp;lt_settings-&gt;link_settings);</div><div class='ctx'> </div><div class='del'>-	if (!link-&gt;dpcd_caps.lttpr_caps.main_link_channel_coding.bits.DP_128b_132b_SUPPORTED) {</div><div class='add'>+	// Only perform toggle if FIXED_VS LTTPR reports no IEEE OUI</div><div class='add'>+	if (memcmp("\x0,\x0,\x0", &amp;link-&gt;dpcd_caps.lttpr_caps.lttpr_ieee_oui[0], 3) == 0) {</div><div class='ctx'> 		/* Vendor specific: Toggle link rate */</div><div class='ctx'> 		toggle_rate = (rate == 0x6) ? 0xA : 0x6;</div><div class='ctx'> </div><div class='hunk'>@@ -412,7 +413,6 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(</div><div class='ctx'> </div><div class='ctx'> 			/* 5. check CR done*/</div><div class='ctx'> 			if (dp_is_cr_done(lane_count, dpcd_lane_status)) {</div><div class='del'>-				status = LINK_TRAINING_SUCCESS;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c<br/>index c5de6ed5bf58..584b9295a12a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c</a></div><div class='hunk'>@@ -130,7 +130,7 @@ static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint3</div><div class='ctx'>  * XXX: Do not allow any two address ranges in this array to overlap</div><div class='ctx'>  */</div><div class='ctx'> static const struct dpcd_address_range mandatory_dpcd_blocks[] = {</div><div class='del'>-	{ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT }};</div><div class='add'>+	{ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, DP_PHY_REPEATER_128B132B_RATES }};</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * extend addresses to read all mandatory blocks together</div><div class='hunk'>@@ -165,6 +165,7 @@ static void dpcd_extend_address_range(</div><div class='ctx'> 		*out_address = new_addr_range.start;</div><div class='ctx'> 		*out_size = ADDRESS_RANGE_SIZE(new_addr_range.start, new_addr_range.end);</div><div class='ctx'> 		*out_data = kcalloc(*out_size, sizeof(**out_data), GFP_KERNEL);</div><div class='add'>+		ASSERT(*out_data);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h<br/>index 08d787a1e451..c2717c678c72 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> #ifndef __LINK_DPCD_H__</div><div class='ctx'> #define __LINK_DPCD_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> </div><div class='ctx'> enum dc_status core_link_read_dpcd(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c<br/>index 3baa2bdd6dd6..c56e69eb27ef 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c</a></div><div class='hunk'>@@ -38,6 +38,7 @@</div><div class='ctx'> #include "dc/dc_dmub_srv.h"</div><div class='ctx'> #include "dce/dmub_replay.h"</div><div class='ctx'> #include "abm.h"</div><div class='add'>+#include "resource.h"</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	link-&gt;ctx-&gt;logger</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='hunk'>@@ -156,31 +157,16 @@ bool edp_set_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> 		uint32_t backlight_millinits,</div><div class='ctx'> 		uint32_t transition_time_in_ms)</div><div class='ctx'> {</div><div class='del'>-	struct dpcd_source_backlight_set dpcd_backlight_set;</div><div class='del'>-	uint8_t backlight_control = isHDR ? 1 : 0;</div><div class='del'>-</div><div class='ctx'> 	if (!link || (link-&gt;connector_signal != SIGNAL_TYPE_EDP &amp;&amp;</div><div class='ctx'> 			link-&gt;connector_signal != SIGNAL_TYPE_DISPLAY_PORT))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	// OLEDs have no PWM, they can only use AUX</div><div class='del'>-	if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1)</div><div class='del'>-		backlight_control = 1;</div><div class='del'>-</div><div class='del'>-	*(uint32_t *)&amp;dpcd_backlight_set.backlight_level_millinits = backlight_millinits;</div><div class='del'>-	*(uint16_t *)&amp;dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	if (!link-&gt;dpcd_caps.panel_luminance_control) {</div><div class='del'>-		if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,</div><div class='del'>-			(uint8_t *)(&amp;dpcd_backlight_set),</div><div class='del'>-			sizeof(dpcd_backlight_set)) != DC_OK)</div><div class='del'>-			return false;</div><div class='add'>+	if (link-&gt;is_dds &amp;&amp; !link-&gt;dpcd_caps.panel_luminance_control)</div><div class='add'>+		return true;</div><div class='ctx'> </div><div class='del'>-		if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,</div><div class='del'>-			&amp;backlight_control, 1) != DC_OK)</div><div class='del'>-			return false;</div><div class='del'>-	} else {</div><div class='add'>+	// use internal backlight control if dmub capabilities are not present</div><div class='add'>+	if (link-&gt;backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX &amp;&amp;</div><div class='add'>+		!link-&gt;dc-&gt;caps.dmub_caps.aux_backlight_support) {</div><div class='ctx'> 		uint8_t backlight_enable = 0;</div><div class='ctx'> 		struct target_luminance_value *target_luminance = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -190,6 +176,15 @@ bool edp_set_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 		target_luminance = (struct target_luminance_value *)&amp;backlight_millinits;</div><div class='ctx'> </div><div class='add'>+		//make sure we disable AMD ABC first.</div><div class='add'>+		core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,</div><div class='add'>+			&amp;backlight_enable, sizeof(uint8_t));</div><div class='add'>+		if (backlight_enable) {</div><div class='add'>+			backlight_enable = 0;</div><div class='add'>+			core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,</div><div class='add'>+					&amp;backlight_enable, 1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,</div><div class='ctx'> 			&amp;backlight_enable, sizeof(uint8_t));</div><div class='ctx'> </div><div class='hunk'>@@ -204,6 +199,36 @@ bool edp_set_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> 			(uint8_t *)(target_luminance),</div><div class='ctx'> 			sizeof(struct target_luminance_value)) != DC_OK)</div><div class='ctx'> 			return false;</div><div class='add'>+	} else if (link-&gt;backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX) {</div><div class='add'>+		struct dpcd_source_backlight_set dpcd_backlight_set;</div><div class='add'>+		*(uint32_t *)&amp;dpcd_backlight_set.backlight_level_millinits = backlight_millinits;</div><div class='add'>+		*(uint16_t *)&amp;dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;</div><div class='add'>+</div><div class='add'>+		uint8_t backlight_control = isHDR ? 1 : 0;</div><div class='add'>+		uint8_t backlight_enable = 0;</div><div class='add'>+</div><div class='add'>+		// OLEDs have no PWM, they can only use AUX</div><div class='add'>+		if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1)</div><div class='add'>+			backlight_control = 1;</div><div class='add'>+</div><div class='add'>+		//make sure we disable VESA ABC first.</div><div class='add'>+		core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,</div><div class='add'>+			&amp;backlight_enable, sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+		if (backlight_enable &amp; DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE) {</div><div class='add'>+			backlight_enable &amp;= ~DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;</div><div class='add'>+			core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,</div><div class='add'>+					&amp;backlight_enable, sizeof(backlight_enable));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,</div><div class='add'>+			(uint8_t *)(&amp;dpcd_backlight_set),</div><div class='add'>+			sizeof(dpcd_backlight_set)) != DC_OK)</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,</div><div class='add'>+			&amp;backlight_control, 1) != DC_OK)</div><div class='add'>+			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -221,6 +246,8 @@ bool edp_get_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> 			link-&gt;connector_signal != SIGNAL_TYPE_DISPLAY_PORT))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;is_dds)</div><div class='add'>+		return false;</div><div class='ctx'> 	if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,</div><div class='ctx'> 			dpcd_backlight_get.raw,</div><div class='ctx'> 			sizeof(union dpcd_source_backlight_get)))</div><div class='hunk'>@@ -247,6 +274,8 @@ bool edp_backlight_enable_aux(struct dc_link *link, bool enable)</div><div class='ctx'> 		link-&gt;connector_signal != SIGNAL_TYPE_DISPLAY_PORT))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;is_dds)</div><div class='add'>+		return true;</div><div class='ctx'> 	if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,</div><div class='ctx'> 		&amp;backlight_enable, 1) != DC_OK)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -304,24 +333,25 @@ bool edp_is_ilr_optimization_enabled(struct dc_link *link)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link)</div><div class='add'>+enum dc_link_rate get_max_edp_link_rate(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	enum dc_link_rate link_rate = link-&gt;reported_link_cap.link_rate;</div><div class='add'>+	enum dc_link_rate max_ilr_rate = LINK_RATE_UNKNOWN;</div><div class='add'>+	enum dc_link_rate max_non_ilr_rate = dp_get_max_link_cap(link).link_rate;</div><div class='ctx'> </div><div class='ctx'> 	for (int i = 0; i &lt; link-&gt;dpcd_caps.edp_supported_link_rates_count; i++) {</div><div class='del'>-		if (link_rate &lt; link-&gt;dpcd_caps.edp_supported_link_rates[i])</div><div class='del'>-			link_rate = link-&gt;dpcd_caps.edp_supported_link_rates[i];</div><div class='add'>+		if (max_ilr_rate &lt; link-&gt;dpcd_caps.edp_supported_link_rates[i])</div><div class='add'>+			max_ilr_rate = link-&gt;dpcd_caps.edp_supported_link_rates[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return link_rate;</div><div class='add'>+	return (max_ilr_rate &gt; max_non_ilr_rate ? max_ilr_rate : max_non_ilr_rate);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool edp_is_ilr_optimization_required(struct dc_link *link,</div><div class='ctx'> 		struct dc_crtc_timing *crtc_timing)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_link_settings link_setting;</div><div class='del'>-	uint8_t link_bw_set;</div><div class='del'>-	uint8_t link_rate_set;</div><div class='add'>+	uint8_t link_bw_set = 0;</div><div class='add'>+	uint8_t link_rate_set = 0;</div><div class='ctx'> 	uint32_t req_bw;</div><div class='ctx'> 	union lane_count_set lane_count_set = {0};</div><div class='ctx'> </div><div class='hunk'>@@ -517,12 +547,12 @@ static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool edp_set_backlight_level(const struct dc_link *link,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp)</div><div class='add'>+		struct set_backlight_level_params *backlight_level_params)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	uint32_t backlight_pwm_u16_16 = backlight_level_params-&gt;backlight_pwm_u16_16;</div><div class='add'>+	uint32_t frame_ramp = backlight_level_params-&gt;frame_ramp;</div><div class='ctx'> </div><div class='del'>-	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='ctx'> 	DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",</div><div class='ctx'> 			backlight_pwm_u16_16, backlight_pwm_u16_16);</div><div class='ctx'> </div><div class='hunk'>@@ -542,10 +572,11 @@ bool edp_set_backlight_level(const struct dc_link *link,</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		backlight_level_params-&gt;frame_ramp = frame_ramp;</div><div class='add'>+</div><div class='ctx'> 		dc-&gt;hwss.set_backlight_level(</div><div class='ctx'> 				pipe_ctx,</div><div class='del'>-				backlight_pwm_u16_16,</div><div class='del'>-				frame_ramp);</div><div class='add'>+				backlight_level_params);</div><div class='ctx'> 	}</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -672,6 +703,32 @@ bool edp_setup_psr(struct dc_link *link,</div><div class='ctx'> 	if (!link)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	/* This is a workaround: some vendors require the source to</div><div class='add'>+	 * read the PSR cap; otherwise, the vendor's PSR feature will</div><div class='add'>+	 * fall back to its default behavior, causing a misconfiguration</div><div class='add'>+	 * of this feature.</div><div class='add'>+	 */</div><div class='add'>+	if (link-&gt;panel_config.psr.read_psrcap_again) {</div><div class='add'>+		dm_helpers_dp_read_dpcd(</div><div class='add'>+			link-&gt;ctx,</div><div class='add'>+			link,</div><div class='add'>+			DP_PSR_SUPPORT,</div><div class='add'>+			&amp;link-&gt;dpcd_caps.psr_info.psr_version,</div><div class='add'>+			sizeof(link-&gt;dpcd_caps.psr_info.psr_version));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//Clear PSR cfg</div><div class='add'>+	memset(&amp;psr_configuration, 0, sizeof(psr_configuration));</div><div class='add'>+	dm_helpers_dp_write_dpcd(</div><div class='add'>+		link-&gt;ctx,</div><div class='add'>+		link,</div><div class='add'>+		DP_PSR_EN_CFG,</div><div class='add'>+		&amp;psr_configuration.raw,</div><div class='add'>+		sizeof(psr_configuration.raw));</div><div class='add'>+</div><div class='add'>+	if (link-&gt;psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	dmcu = dc-&gt;res_pool-&gt;dmcu;</div><div class='ctx'> 	psr = dc-&gt;res_pool-&gt;psr;</div><div class='hunk'>@@ -682,9 +739,6 @@ bool edp_setup_psr(struct dc_link *link,</div><div class='ctx'> 	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-	memset(&amp;psr_configuration, 0, sizeof(psr_configuration));</div><div class='del'>-</div><div class='ctx'> 	psr_configuration.bits.ENABLE                    = 1;</div><div class='ctx'> 	psr_configuration.bits.CRC_VERIFICATION          = 1;</div><div class='ctx'> 	psr_configuration.bits.FRAME_CAPTURE_INDICATION  =</div><div class='hunk'>@@ -762,7 +816,7 @@ bool edp_setup_psr(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	psr_context-&gt;crtcTimingVerticalTotal = stream-&gt;timing.v_total;</div><div class='ctx'> 	psr_context-&gt;vsync_rate_hz = div64_u64(div64_u64((stream-&gt;</div><div class='del'>-					timing.pix_clk_100hz * 100),</div><div class='add'>+					timing.pix_clk_100hz * (u64)100),</div><div class='ctx'> 					stream-&gt;timing.v_total),</div><div class='ctx'> 					stream-&gt;timing.h_total);</div><div class='ctx'> </div><div class='hunk'>@@ -830,6 +884,8 @@ bool edp_setup_psr(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	psr_context-&gt;dsc_slice_height = psr_config-&gt;dsc_slice_height;</div><div class='ctx'> </div><div class='add'>+	psr_context-&gt;os_request_force_ffu = psr_config-&gt;os_request_force_ffu;</div><div class='add'>+</div><div class='ctx'> 	if (psr) {</div><div class='ctx'> 		link-&gt;psr_settings.psr_feature_enabled = psr-&gt;funcs-&gt;psr_copy_settings(psr,</div><div class='ctx'> 			link, psr_context, panel_inst);</div><div class='hunk'>@@ -849,7 +905,7 @@ bool edp_setup_psr(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency)</div><div class='add'>+void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dmub_psr *psr = dc-&gt;res_pool-&gt;psr;</div><div class='hunk'>@@ -860,7 +916,7 @@ void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency)</div><div class='ctx'> </div><div class='ctx'> 	// PSR residency measurements only supported on DMCUB</div><div class='ctx'> 	if (psr != NULL &amp;&amp; link-&gt;psr_settings.psr_feature_enabled)</div><div class='del'>-		psr-&gt;funcs-&gt;psr_get_residency(psr, residency, panel_inst);</div><div class='add'>+		psr-&gt;funcs-&gt;psr_get_residency(psr, residency, panel_inst, mode);</div><div class='ctx'> 	else</div><div class='ctx'> 		*residency = 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -893,7 +949,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,</div><div class='ctx'> 	/* Set power optimization flag */</div><div class='ctx'> 	if (power_opts &amp;&amp; link-&gt;replay_settings.replay_power_opt_active != *power_opts) {</div><div class='ctx'> 		if (replay != NULL &amp;&amp; link-&gt;replay_settings.replay_feature_enabled &amp;&amp;</div><div class='del'>-		    replay-&gt;funcs-&gt;replay_set_power_opt) {</div><div class='add'>+			replay-&gt;funcs-&gt;replay_set_power_opt) {</div><div class='ctx'> 			replay-&gt;funcs-&gt;replay_set_power_opt(replay, *power_opts, panel_inst);</div><div class='ctx'> 			link-&gt;replay_settings.replay_power_opt_active = *power_opts;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -928,7 +984,7 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)</div><div class='add'>+static bool edp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	/* To-do: Setup Replay */</div><div class='ctx'> 	struct dc *dc;</div><div class='hunk'>@@ -938,8 +994,117 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> 	struct replay_context replay_context = { 0 };</div><div class='ctx'> 	unsigned int lineTimeInNs = 0;</div><div class='ctx'> </div><div class='add'>+	union panel_replay_enable_and_configuration_1 pr_config_1 = { 0 };</div><div class='add'>+	union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 };</div><div class='add'>+</div><div class='add'>+	union dpcd_alpm_configuration alpm_config;</div><div class='add'>+</div><div class='add'>+	replay_context.controllerId = CONTROLLER_ID_UNDEFINED;</div><div class='add'>+</div><div class='add'>+	if (!link)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	//Clear Panel Replay enable &amp; config</div><div class='add'>+	dm_helpers_dp_write_dpcd(link-&gt;ctx, link,</div><div class='add'>+		DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1,</div><div class='add'>+		(uint8_t *)&amp;(pr_config_1.raw), sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+	dm_helpers_dp_write_dpcd(link-&gt;ctx, link,</div><div class='add'>+		DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2,</div><div class='add'>+		(uint8_t *)&amp;(pr_config_2.raw), sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+	if (!(link-&gt;replay_settings.config.replay_supported))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	//not sure should keep or not</div><div class='add'>+	replay = dc-&gt;res_pool-&gt;replay;</div><div class='add'>+</div><div class='add'>+	if (!replay)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	union replay_enable_and_configuration replay_config;</div><div class='add'>+	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	replay_context.aux_inst = link-&gt;ddc-&gt;ddc_pin-&gt;hw_info.ddc_channel;</div><div class='add'>+	replay_context.digbe_inst = link-&gt;link_enc-&gt;transmitter;</div><div class='add'>+	replay_context.digfe_inst = link-&gt;link_enc-&gt;preferred_engine;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream</div><div class='add'>+				== stream) {</div><div class='add'>+			/* dmcu -1 for all controller id values,</div><div class='add'>+			 * therefore +1 here</div><div class='add'>+			 */</div><div class='add'>+			replay_context.controllerId =</div><div class='add'>+				dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream_res.tg-&gt;inst + 1;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lineTimeInNs =</div><div class='add'>+		((stream-&gt;timing.h_total * 1000000) /</div><div class='add'>+			(stream-&gt;timing.pix_clk_100hz / 10)) + 1;</div><div class='add'>+</div><div class='add'>+	replay_context.line_time_in_ns = lineTimeInNs;</div><div class='add'>+</div><div class='add'>+	link-&gt;replay_settings.replay_feature_enabled =</div><div class='add'>+			replay-&gt;funcs-&gt;replay_copy_settings(replay, link, &amp;replay_context, panel_inst);</div><div class='add'>+</div><div class='add'>+	if (link-&gt;replay_settings.replay_feature_enabled) {</div><div class='add'>+		pr_config_1.bits.PANEL_REPLAY_ENABLE = 1;</div><div class='add'>+		pr_config_1.bits.PANEL_REPLAY_CRC_ENABLE = 1;</div><div class='add'>+		pr_config_1.bits.IRQ_HPD_ASSDP_MISSING = 1;</div><div class='add'>+		pr_config_1.bits.IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR = 1;</div><div class='add'>+		pr_config_1.bits.IRQ_HPD_RFB_ERROR = 1;</div><div class='add'>+		pr_config_1.bits.IRQ_HPD_ACTIVE_FRAME_CRC_ERROR = 1;</div><div class='add'>+		pr_config_1.bits.PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE = 1;</div><div class='add'>+		pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1;</div><div class='add'>+</div><div class='add'>+		pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0;</div><div class='add'>+		pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 0;</div><div class='add'>+		pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0;</div><div class='add'>+</div><div class='add'>+		dm_helpers_dp_write_dpcd(link-&gt;ctx, link,</div><div class='add'>+			DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1,</div><div class='add'>+			(uint8_t *)&amp;(pr_config_1.raw), sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+		dm_helpers_dp_write_dpcd(link-&gt;ctx, link,</div><div class='add'>+			DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2,</div><div class='add'>+			(uint8_t *)&amp;(pr_config_2.raw), sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+		//ALPM Setup</div><div class='add'>+		memset(&amp;alpm_config, 0, sizeof(alpm_config));</div><div class='add'>+		alpm_config.bits.ENABLE = link-&gt;replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {</div><div class='add'>+			alpm_config.bits.ALPM_MODE_SEL = 1;</div><div class='add'>+			alpm_config.bits.ACDS_PERIOD_DURATION = 1;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dm_helpers_dp_write_dpcd(</div><div class='add'>+			link-&gt;ctx,</div><div class='add'>+			link,</div><div class='add'>+			DP_RECEIVER_ALPM_CONFIG,</div><div class='add'>+			&amp;alpm_config.raw,</div><div class='add'>+			sizeof(alpm_config.raw));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	/* To-do: Setup Replay */</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct dmub_replay *replay;</div><div class='add'>+	int i;</div><div class='add'>+	unsigned int panel_inst;</div><div class='add'>+	struct replay_context replay_context = { 0 };</div><div class='add'>+	unsigned int lineTimeInNs = 0;</div><div class='add'>+</div><div class='add'>+	union replay_enable_and_configuration replay_config = { 0 };</div><div class='ctx'> </div><div class='ctx'> 	union dpcd_alpm_configuration alpm_config;</div><div class='ctx'> </div><div class='hunk'>@@ -948,6 +1113,16 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> 	if (!link)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	//Clear Replay config</div><div class='add'>+	dm_helpers_dp_write_dpcd(link-&gt;ctx, link,</div><div class='add'>+		DP_SINK_PR_ENABLE_AND_CONFIGURATION,</div><div class='add'>+		(uint8_t *)&amp;(replay_config.raw), sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+	if (!(link-&gt;replay_settings.config.replay_supported))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	link-&gt;replay_settings.config.replay_error_status.raw = 0;</div><div class='add'>+</div><div class='ctx'> 	dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> </div><div class='ctx'> 	replay = dc-&gt;res_pool-&gt;replay;</div><div class='hunk'>@@ -980,6 +1155,8 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> </div><div class='ctx'> 	replay_context.line_time_in_ns = lineTimeInNs;</div><div class='ctx'> </div><div class='add'>+	replay_context.os_request_force_ffu = link-&gt;replay_settings.config.os_request_force_ffu;</div><div class='add'>+</div><div class='ctx'> 	link-&gt;replay_settings.replay_feature_enabled =</div><div class='ctx'> 			replay-&gt;funcs-&gt;replay_copy_settings(replay, link, &amp;replay_context, panel_inst);</div><div class='ctx'> 	if (link-&gt;replay_settings.replay_feature_enabled) {</div><div class='hunk'>@@ -993,7 +1170,13 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> 			(uint8_t *)&amp;(replay_config.raw), sizeof(uint8_t));</div><div class='ctx'> </div><div class='ctx'> 		memset(&amp;alpm_config, 0, sizeof(alpm_config));</div><div class='del'>-		alpm_config.bits.ENABLE = 1;</div><div class='add'>+		alpm_config.bits.ENABLE = link-&gt;replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {</div><div class='add'>+			alpm_config.bits.ALPM_MODE_SEL = 1;</div><div class='add'>+			alpm_config.bits.ACDS_PERIOD_DURATION = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		dm_helpers_dp_write_dpcd(</div><div class='ctx'> 			link-&gt;ctx,</div><div class='ctx'> 			link,</div><div class='hunk'>@@ -1001,9 +1184,24 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> 			&amp;alpm_config.raw,</div><div class='ctx'> 			sizeof(alpm_config.raw));</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	link-&gt;replay_settings.config.replay_video_conferencing_optimization_enabled = false;</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	if (!link)</div><div class='add'>+		return false;</div><div class='add'>+	if (link-&gt;replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY)</div><div class='add'>+		return edp_setup_panel_replay(link, stream);</div><div class='add'>+	else if (link-&gt;replay_settings.config.replay_version == DC_FREESYNC_REPLAY)</div><div class='add'>+		return edp_setup_freesync_replay(link, stream);</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * This is general Interface for Replay to set an 32 bit variable to dmub</div><div class='ctx'>  * replay_FW_Message_type: Indicates which instruction or variable pass to DMUB</div><div class='hunk'>@@ -1034,7 +1232,7 @@ bool edp_send_replay_cmd(struct dc_link *link,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)</div><div class='add'>+bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dmub_replay *replay = dc-&gt;res_pool-&gt;replay;</div><div class='hunk'>@@ -1046,16 +1244,18 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal)</div><div class='ctx'> 	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (coasting_vtotal &amp;&amp; link-&gt;replay_settings.coasting_vtotal != coasting_vtotal) {</div><div class='del'>-		replay-&gt;funcs-&gt;replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst);</div><div class='add'>+	if (coasting_vtotal &amp;&amp; (link-&gt;replay_settings.coasting_vtotal != coasting_vtotal ||</div><div class='add'>+		link-&gt;replay_settings.frame_skip_number != frame_skip_number)) {</div><div class='add'>+		replay-&gt;funcs-&gt;replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number);</div><div class='ctx'> 		link-&gt;replay_settings.coasting_vtotal = coasting_vtotal;</div><div class='add'>+		link-&gt;replay_settings.frame_skip_number = frame_skip_number;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool edp_replay_residency(const struct dc_link *link,</div><div class='del'>-	unsigned int *residency, const bool is_start, const bool is_alpm)</div><div class='add'>+	unsigned int *residency, const bool is_start, const enum pr_residency_mode mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dmub_replay *replay = dc-&gt;res_pool-&gt;replay;</div><div class='hunk'>@@ -1064,8 +1264,11 @@ bool edp_replay_residency(const struct dc_link *link,</div><div class='ctx'> 	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	if (!residency)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	if (replay != NULL &amp;&amp; link-&gt;replay_settings.replay_feature_enabled)</div><div class='del'>-		replay-&gt;funcs-&gt;replay_residency(replay, panel_inst, residency, is_start, is_alpm);</div><div class='add'>+		replay-&gt;funcs-&gt;replay_residency(replay, panel_inst, residency, is_start, mode);</div><div class='ctx'> 	else</div><div class='ctx'> 		*residency = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1073,7 +1276,7 @@ bool edp_replay_residency(const struct dc_link *link,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,</div><div class='del'>-	const unsigned int *power_opts, uint32_t coasting_vtotal)</div><div class='add'>+	const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dmub_replay *replay = dc-&gt;res_pool-&gt;replay;</div><div class='hunk'>@@ -1084,13 +1287,16 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	/* Only both power and coasting vtotal changed, this func could return true */</div><div class='ctx'> 	if (power_opts &amp;&amp; link-&gt;replay_settings.replay_power_opt_active != *power_opts &amp;&amp;</div><div class='del'>-		coasting_vtotal &amp;&amp; link-&gt;replay_settings.coasting_vtotal != coasting_vtotal) {</div><div class='add'>+		(coasting_vtotal &amp;&amp;</div><div class='add'>+		(link-&gt;replay_settings.coasting_vtotal != coasting_vtotal ||</div><div class='add'>+		link-&gt;replay_settings.frame_skip_number != frame_skip_number))) {</div><div class='ctx'> 		if (link-&gt;replay_settings.replay_feature_enabled &amp;&amp;</div><div class='ctx'> 			replay-&gt;funcs-&gt;replay_set_power_opt_and_coasting_vtotal) {</div><div class='ctx'> 			replay-&gt;funcs-&gt;replay_set_power_opt_and_coasting_vtotal(replay,</div><div class='del'>-				*power_opts, panel_inst, coasting_vtotal);</div><div class='add'>+				*power_opts, panel_inst, coasting_vtotal, frame_skip_number);</div><div class='ctx'> 			link-&gt;replay_settings.replay_power_opt_active = *power_opts;</div><div class='ctx'> 			link-&gt;replay_settings.coasting_vtotal = coasting_vtotal;</div><div class='add'>+			link-&gt;replay_settings.frame_skip_number = frame_skip_number;</div><div class='ctx'> 		} else</div><div class='ctx'> 			return false;</div><div class='ctx'> 	} else</div><div class='hunk'>@@ -1106,11 +1312,11 @@ static struct abm *get_abm_from_stream_res(const struct dc_link *link)</div><div class='ctx'> 	struct abm *abm = NULL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-		struct pipe_ctx pipe_ctx = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-		struct dc_stream_state *stream = pipe_ctx.stream;</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> </div><div class='ctx'> 		if (stream &amp;&amp; stream-&gt;link == link) {</div><div class='del'>-			abm = pipe_ctx.stream_res.abm;</div><div class='add'>+			abm = pipe_ctx-&gt;stream_res.abm;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1145,3 +1351,76 @@ int edp_get_target_backlight_pwm(const struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	return (int) abm-&gt;funcs-&gt;get_target_backlight(abm);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool is_smartmux_suported(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	if (link-&gt;dc-&gt;caps.is_apu)</div><div class='add'>+		return false;</div><div class='add'>+	if (!link-&gt;dc-&gt;config.smart_mux_version)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,</div><div class='add'>+		struct link_resource *link_res, bool enable)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	bool use_hpo_dp_link_enc = false;</div><div class='add'>+	uint8_t link_enc_index = 0;</div><div class='add'>+	uint8_t phy_type = 0;</div><div class='add'>+	uint8_t phy_id = 0;</div><div class='add'>+</div><div class='add'>+	if (!pDC-&gt;config.use_assr_psp_message)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+</div><div class='add'>+	link_enc_index = link-&gt;link_enc-&gt;transmitter - TRANSMITTER_UNIPHY_A;</div><div class='add'>+</div><div class='add'>+	if (link_res-&gt;hpo_dp_link_enc) {</div><div class='add'>+		link_enc_index = link_res-&gt;hpo_dp_link_enc-&gt;inst;</div><div class='add'>+		use_hpo_dp_link_enc = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		phy_type = ((dp_get_panel_mode(link) == DP_PANEL_MODE_EDP) ? 1 : 0);</div><div class='add'>+</div><div class='add'>+	phy_id = resource_transmitter_to_phy_idx(pDC, link-&gt;link_enc-&gt;transmitter);</div><div class='add'>+</div><div class='add'>+	cmd.assr_enable.header.type = DMUB_CMD__PSP;</div><div class='add'>+	cmd.assr_enable.header.sub_type = DMUB_CMD__PSP_ASSR_ENABLE;</div><div class='add'>+	cmd.assr_enable.assr_data.enable = enable;</div><div class='add'>+	cmd.assr_enable.assr_data.phy_port_type = phy_type;</div><div class='add'>+	cmd.assr_enable.assr_data.phy_port_id = phy_id;</div><div class='add'>+	cmd.assr_enable.assr_data.link_enc_index = link_enc_index;</div><div class='add'>+	cmd.assr_enable.assr_data.hpo_mode = use_hpo_dp_link_enc;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(pDC-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		enum dp_panel_mode *panel_mode, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct link_resource *link_res = &amp;pipe_ctx-&gt;link_res;</div><div class='add'>+	struct cp_psp *cp_psp = &amp;pipe_ctx-&gt;stream-&gt;ctx-&gt;cp_psp;</div><div class='add'>+</div><div class='add'>+	if (*panel_mode != DP_PANEL_MODE_EDP)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dc-&gt;config.use_assr_psp_message) {</div><div class='add'>+		edp_set_assr_enable(link-&gt;dc, link, link_res, enable);</div><div class='add'>+	} else if (cp_psp &amp;&amp; cp_psp-&gt;funcs.enable_assr &amp;&amp; enable) {</div><div class='add'>+		/* ASSR is bound to fail with unsigned PSP</div><div class='add'>+		 * verstage used during devlopment phase.</div><div class='add'>+		 * Report and continue with eDP panel mode to</div><div class='add'>+		 * perform eDP link training with right settings</div><div class='add'>+		 */</div><div class='add'>+		bool result;</div><div class='add'>+</div><div class='add'>+		result = cp_psp-&gt;funcs.enable_assr(cp_psp-&gt;handle, link);</div><div class='add'>+</div><div class='add'>+		if (!result &amp;&amp; link-&gt;panel_mode != DP_PANEL_MODE_EDP)</div><div class='add'>+			*panel_mode = DP_PANEL_MODE_DEFAULT;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h<br/>index a158c6234d42..dd79c7cd2828 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h</a></div><div class='hunk'>@@ -25,19 +25,19 @@</div><div class='ctx'> </div><div class='ctx'> #ifndef __DC_LINK_EDP_PANEL_CONTROL_H__</div><div class='ctx'> #define __DC_LINK_EDP_PANEL_CONTROL_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);</div><div class='ctx'> void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);</div><div class='ctx'> bool set_default_brightness_aux(struct dc_link *link);</div><div class='add'>+bool is_smartmux_suported(struct dc_link *link);</div><div class='ctx'> void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);</div><div class='ctx'> int edp_get_backlight_level(const struct dc_link *link);</div><div class='ctx'> bool edp_get_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> 		uint32_t *backlight_millinits_avg,</div><div class='ctx'> 		uint32_t *backlight_millinits_peak);</div><div class='ctx'> bool edp_set_backlight_level(const struct dc_link *link,</div><div class='del'>-		uint32_t backlight_pwm_u16_16,</div><div class='del'>-		uint32_t frame_ramp);</div><div class='add'>+		struct set_backlight_level_params *backlight_level_params);</div><div class='ctx'> bool edp_set_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> 		bool isHDR,</div><div class='ctx'> 		uint32_t backlight_millinits,</div><div class='hunk'>@@ -51,7 +51,7 @@ bool edp_setup_psr(struct dc_link *link,</div><div class='ctx'> 		struct psr_context *psr_context);</div><div class='ctx'> bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link,</div><div class='ctx'>        uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);</div><div class='del'>-void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency);</div><div class='add'>+void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode);</div><div class='ctx'> bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,</div><div class='ctx'> 	bool wait, bool force_static, const unsigned int *power_opts);</div><div class='ctx'> bool edp_setup_replay(struct dc_link *link,</div><div class='hunk'>@@ -59,21 +59,23 @@ bool edp_setup_replay(struct dc_link *link,</div><div class='ctx'> bool edp_send_replay_cmd(struct dc_link *link,</div><div class='ctx'> 			enum replay_FW_Message_type msg,</div><div class='ctx'> 			union dmub_replay_cmd_set *cmd_data);</div><div class='del'>-bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal);</div><div class='add'>+bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number);</div><div class='ctx'> bool edp_replay_residency(const struct dc_link *link,</div><div class='del'>-	unsigned int *residency, const bool is_start, const bool is_alpm);</div><div class='add'>+	unsigned int *residency, const bool is_start, const enum pr_residency_mode mode);</div><div class='ctx'> bool edp_get_replay_state(const struct dc_link *link, uint64_t *state);</div><div class='ctx'> bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,</div><div class='del'>-	const unsigned int *power_opts, uint32_t coasting_vtotal);</div><div class='add'>+	const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number);</div><div class='ctx'> bool edp_wait_for_t12(struct dc_link *link);</div><div class='ctx'> bool edp_is_ilr_optimization_required(struct dc_link *link,</div><div class='ctx'>        struct dc_crtc_timing *crtc_timing);</div><div class='ctx'> bool edp_is_ilr_optimization_enabled(struct dc_link *link);</div><div class='del'>-enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link);</div><div class='add'>+enum dc_link_rate get_max_edp_link_rate(struct dc_link *link);</div><div class='ctx'> bool edp_backlight_enable_aux(struct dc_link *link, bool enable);</div><div class='ctx'> void edp_add_delay_for_T9(struct dc_link *link);</div><div class='ctx'> bool edp_receiver_ready_T9(struct dc_link *link);</div><div class='ctx'> bool edp_receiver_ready_T7(struct dc_link *link);</div><div class='ctx'> bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable);</div><div class='ctx'> void edp_set_panel_power(struct dc_link *link, bool powerOn);</div><div class='add'>+void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx,</div><div class='add'>+		enum dp_panel_mode *panel_mode, bool enable);</div><div class='ctx'> #endif /* __DC_LINK_EDP_POWER_CONTROL_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c<br/>index e3d729ab5b9f..caa617883f62 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c</a></div><div class='hunk'>@@ -35,7 +35,7 @@</div><div class='ctx'> </div><div class='ctx'> bool link_get_hpd_state(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	uint32_t state;</div><div class='add'>+	uint32_t state = 0;</div><div class='ctx'> </div><div class='ctx'> 	dal_gpio_lock_pin(link-&gt;hpd_gpio);</div><div class='ctx'> 	dal_gpio_get_value(link-&gt;hpd_gpio, &amp;state);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h<br/>index 4fb526b264f9..af529328ba17 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> #ifndef __DC_LINK_HPD_H__</div><div class='ctx'> #define __DC_LINK_HPD_H__</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> enum hpd_source_id get_hpd_line(struct dc_link *link);</div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile<br/>new file mode 100644<br/>index 000000000000..2d4b7a85847d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile</a></div><div class='hunk'>@@ -0,0 +1,54 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN20</div><div class='add'>+###############################################################################</div><div class='add'>+MMHUBBUB_DCN20 = dcn20_mmhubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MMHUBBUB_DCN20 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn20/,$(MMHUBBUB_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN32</div><div class='add'>+###############################################################################</div><div class='add'>+MMHUBBUB_DCN32 = dcn32_mmhubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MMHUBBUB_DCN32 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn32/,$(MMHUBBUB_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN35</div><div class='add'>+###############################################################################</div><div class='add'>+MMHUBBUB_DCN35 = dcn35_mmhubbub.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MMHUBBUB_DCN35 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn35/,$(MMHUBBUB_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN35)</div><div class='add'>+endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c<br/>index 259a98e4ee2c..2a422e223bf2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c</a></div><div class='hunk'>@@ -284,7 +284,7 @@ void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);</div><div class='ctx'> </div><div class='del'>-	memcpy(dest_luma_buffer,   luma_buffer,   mcif_params-&gt;luma_pitch * dest_height);</div><div class='add'>+	memcpy(dest_luma_buffer,   luma_buffer,   (size_t)mcif_params-&gt;luma_pitch * dest_height);</div><div class='ctx'> 	memcpy(dest_chroma_buffer, chroma_buffer, mcif_params-&gt;chroma_pitch * dest_height / 2);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h<br/>index 5ab32aa51e13..5ab32aa51e13 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c<br/>index c3b089ba511a..c3b089ba511a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h<br/>index ef15b4f1f6b9..ef15b4f1f6b9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mmhubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c<br/>index 4317100564a4..4317100564a4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h<br/>index 098e13e07272..098e13e07272 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/mpc/Makefile b/drivers/gpu/drm/amd/display/dc/mpc/Makefile<br/>new file mode 100644<br/>index 000000000000..5402c3529f5e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/Makefile</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN10</div><div class='add'>+###############################################################################</div><div class='add'>+MPC_DCN10 = dcn10_mpc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MPC_DCN10 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn10/,$(MPC_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN10)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN20</div><div class='add'>+###############################################################################</div><div class='add'>+MPC_DCN20 = dcn20_mpc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MPC_DCN20 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn20/,$(MPC_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN30</div><div class='add'>+###############################################################################</div><div class='add'>+MPC_DCN30 = dcn30_mpc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MPC_DCN30 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn30/,$(MPC_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN32</div><div class='add'>+###############################################################################</div><div class='add'>+MPC_DCN32 = dcn32_mpc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MPC_DCN32 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn32/,$(MPC_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN401</div><div class='add'>+###############################################################################</div><div class='add'>+MPC_DCN401 = dcn401_mpc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_MPC_DCN401 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn401/,$(MPC_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN401)</div><div class='add'>+</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c<br/>index f2f55565e98a..b23c64004dd5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c</a></div><div class='hunk'>@@ -142,22 +142,6 @@ struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)</div><div class='del'>-{</div><div class='del'>-	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);</div><div class='del'>-	unsigned int top_sel;</div><div class='del'>-	unsigned int opp_id;</div><div class='del'>-	unsigned int idle;</div><div class='del'>-</div><div class='del'>-	REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &amp;top_sel);</div><div class='del'>-	REG_GET(MPCC_OPP_ID[mpcc_id],  MPCC_OPP_ID, &amp;opp_id);</div><div class='del'>-	REG_GET(MPCC_STATUS[mpcc_id],  MPCC_IDLE,   &amp;idle);</div><div class='del'>-	if (top_sel == 0xf &amp;&amp; opp_id == 0xf &amp;&amp; idle)</div><div class='del'>-		return true;</div><div class='del'>-	else</div><div class='del'>-		return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h<br/>index dbfffc6383dc..874e36e39e1b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h</a></div><div class='hunk'>@@ -173,10 +173,6 @@ void mpc1_update_stereo_mix(</div><div class='ctx'> 	struct mpcc_sm_cfg *sm_cfg,</div><div class='ctx'> 	int mpcc_id);</div><div class='ctx'> </div><div class='del'>-bool mpc1_is_mpcc_idle(</div><div class='del'>-	struct mpc *mpc,</div><div class='del'>-	int mpcc_id);</div><div class='del'>-</div><div class='ctx'> void mpc1_assert_mpcc_idle_before_connect(</div><div class='ctx'> 	struct mpc *mpc,</div><div class='ctx'> 	int mpcc_id);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c<br/>index 16b5ff208d14..ea73473b970a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c</a></div><div class='hunk'>@@ -395,9 +395,12 @@ static void mpc20_program_ogam_pwl(</div><div class='ctx'> 				MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg);</div><div class='ctx'> 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,</div><div class='ctx'> 				MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg);</div><div class='del'>-</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	REG_SEQ_SUBMIT();</div><div class='add'>+	PERF_TRACE();</div><div class='add'>+	REG_SEQ_WAIT_DONE();</div><div class='add'>+	PERF_TRACE();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,</div><div class='hunk'>@@ -501,11 +504,6 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)</div><div class='ctx'> 		ASSERT(!mpc_disabled);</div><div class='ctx'> 		ASSERT(!mpc_idle);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	REG_SEQ_SUBMIT();</div><div class='del'>-	PERF_TRACE();</div><div class='del'>-	REG_SEQ_WAIT_DONE();</div><div class='del'>-	PERF_TRACE();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h<br/>index 496658f420db..496658f420db 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c<br/>index bf3386cd444d..6bfd2c1294e5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "dcn30_mpc.h"</div><div class='del'>-#include "dcn30_cm_common.h"</div><div class='add'>+#include "dcn30/dcn30_cm_common.h"</div><div class='ctx'> #include "basics/conversion.h"</div><div class='ctx'> #include "dcn10/dcn10_cm_common.h"</div><div class='ctx'> #include "dc.h"</div><div class='hunk'>@@ -44,6 +44,36 @@</div><div class='ctx'> #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))</div><div class='ctx'> </div><div class='ctx'> </div><div class='add'>+void mpc3_mpc_init(struct mpc *mpc)</div><div class='add'>+{</div><div class='add'>+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='add'>+	int opp_id;</div><div class='add'>+</div><div class='add'>+	mpc1_mpc_init(mpc);</div><div class='add'>+</div><div class='add'>+	for (opp_id = 0; opp_id &lt; MAX_OPP; opp_id++) {</div><div class='add'>+		if (REG(MUX[opp_id]))</div><div class='add'>+			/* disable mpc out rate and flow control */</div><div class='add'>+			REG_UPDATE_2(MUX[opp_id], MPC_OUT_RATE_CONTROL_DISABLE,</div><div class='add'>+					1, MPC_OUT_FLOW_CONTROL_COUNT, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc3_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	mpc1_mpc_init_single_inst(mpc, mpcc_id);</div><div class='add'>+</div><div class='add'>+	/* assuming mpc out mux is connected to opp with the same index at this</div><div class='add'>+	 * point in time (e.g. transitioning from vbios to driver)</div><div class='add'>+	 */</div><div class='add'>+	if (mpcc_id &lt; MAX_OPP &amp;&amp; REG(MUX[mpcc_id]))</div><div class='add'>+		/* disable mpc out rate and flow control */</div><div class='add'>+		REG_UPDATE_2(MUX[mpcc_id], MPC_OUT_RATE_CONTROL_DISABLE,</div><div class='add'>+				1, MPC_OUT_FLOW_CONTROL_COUNT, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool mpc3_is_dwb_idle(</div><div class='ctx'> 	struct mpc *mpc,</div><div class='ctx'> 	int dwb_id)</div><div class='hunk'>@@ -89,14 +119,12 @@ void mpc3_set_out_rate_control(</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='ctx'> </div><div class='add'>+	/* Always disable mpc out rate and flow control.</div><div class='add'>+	 * MPC flow rate control is not needed for DCN30 and above.</div><div class='add'>+	 */</div><div class='ctx'> 	REG_UPDATE_2(MUX[opp_id],</div><div class='del'>-			MPC_OUT_RATE_CONTROL_DISABLE, !enable,</div><div class='del'>-			MPC_OUT_RATE_CONTROL, rate_2x_mode);</div><div class='del'>-</div><div class='del'>-	if (flow_control)</div><div class='del'>-		REG_UPDATE_2(MUX[opp_id],</div><div class='del'>-			MPC_OUT_FLOW_CONTROL_MODE, flow_control-&gt;flow_ctrl_mode,</div><div class='del'>-			MPC_OUT_FLOW_CONTROL_COUNT, flow_control-&gt;flow_ctrl_cnt1);</div><div class='add'>+			MPC_OUT_RATE_CONTROL_DISABLE, 1,</div><div class='add'>+			MPC_OUT_RATE_CONTROL, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id)</div><div class='hunk'>@@ -1172,7 +1200,7 @@ void mpc3_get_gamut_remap(struct mpc *mpc,</div><div class='ctx'> 			  struct mpc_grph_gamut_adjustment *adjust)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='del'>-	uint16_t arr_reg_val[12];</div><div class='add'>+	uint16_t arr_reg_val[12] = {0};</div><div class='ctx'> 	int select;</div><div class='ctx'> </div><div class='ctx'> 	read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &amp;select);</div><div class='hunk'>@@ -1481,17 +1509,32 @@ static void mpc3_read_mpcc_state(</div><div class='ctx'> 			MPC_RMU_3DLUT_SIZE, &amp;s-&gt;lut3d_size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-        REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst],</div><div class='add'>+	REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst],</div><div class='ctx'> 		  MPCC_OGAM_MODE_CURRENT, &amp;s-&gt;rgam_mode,</div><div class='ctx'> 		  MPCC_OGAM_SELECT_CURRENT, &amp;s-&gt;rgam_lut);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void mpc3_read_reg_state(</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int mpcc_inst, struct dcn_mpc_reg_state *mpc_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	mpc_reg_state-&gt;mpcc_bot_sel = REG_READ(MPCC_BOT_SEL[mpcc_inst]);</div><div class='add'>+	mpc_reg_state-&gt;mpcc_control = REG_READ(MPCC_CONTROL[mpcc_inst]);</div><div class='add'>+	mpc_reg_state-&gt;mpcc_ogam_control = REG_READ(MPCC_OGAM_CONTROL[mpcc_inst]);</div><div class='add'>+	mpc_reg_state-&gt;mpcc_opp_id = REG_READ(MPCC_OPP_ID[mpcc_inst]);</div><div class='add'>+	mpc_reg_state-&gt;mpcc_status = REG_READ(MPCC_STATUS[mpcc_inst]);</div><div class='add'>+	mpc_reg_state-&gt;mpcc_top_sel = REG_READ(MPCC_TOP_SEL[mpcc_inst]);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct mpc_funcs dcn30_mpc_funcs = {</div><div class='ctx'> 	.read_mpcc_state = mpc3_read_mpcc_state,</div><div class='ctx'> 	.insert_plane = mpc1_insert_plane,</div><div class='ctx'> 	.remove_mpcc = mpc1_remove_mpcc,</div><div class='del'>-	.mpc_init = mpc1_mpc_init,</div><div class='del'>-	.mpc_init_single_inst = mpc1_mpc_init_single_inst,</div><div class='add'>+	.mpc_init = mpc3_mpc_init,</div><div class='add'>+	.mpc_init_single_inst = mpc3_mpc_init_single_inst,</div><div class='ctx'> 	.update_blending = mpc2_update_blending,</div><div class='ctx'> 	.cursor_lock = mpc1_cursor_lock,</div><div class='ctx'> 	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,</div><div class='hunk'>@@ -1516,6 +1559,7 @@ static const struct mpc_funcs dcn30_mpc_funcs = {</div><div class='ctx'> 	.release_rmu = mpcc3_release_rmu,</div><div class='ctx'> 	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,</div><div class='ctx'> 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,</div><div class='add'>+	.mpc_read_reg_state = mpc3_read_reg_state,</div><div class='ctx'> 	.set_bg_color = mpc1_set_bg_color,</div><div class='ctx'> 	.set_mpc_mem_lp_mode = mpc3_set_mpc_mem_lp_mode,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h<br/>index 9cb96ae95a2f..e2f147d17178 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h</a></div><div class='hunk'>@@ -1007,6 +1007,13 @@ void dcn30_mpc_construct(struct dcn30_mpc *mpc30,</div><div class='ctx'> 	int num_mpcc,</div><div class='ctx'> 	int num_rmu);</div><div class='ctx'> </div><div class='add'>+void mpc3_mpc_init(</div><div class='add'>+	struct mpc *mpc);</div><div class='add'>+</div><div class='add'>+void mpc3_mpc_init_single_inst(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	unsigned int mpcc_id);</div><div class='add'>+</div><div class='ctx'> bool mpc3_program_shaper(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		const struct pwl_params *params,</div><div class='hunk'>@@ -1089,6 +1096,11 @@ void mpc3_power_on_ogam_lut(</div><div class='ctx'> 	struct mpc *mpc, int mpcc_id,</div><div class='ctx'> 	bool power_on);</div><div class='ctx'> </div><div class='add'>+void mpc3_read_reg_state(</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		int mpcc_inst,</div><div class='add'>+		struct dcn_mpc_reg_state *mpc_reg_state);</div><div class='add'>+</div><div class='ctx'> void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);</div><div class='ctx'> </div><div class='ctx'> enum dc_lut_mode mpc3_get_ogam_current(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c<br/>index e789e654c387..83bbbf34bcac 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c</a></div><div class='hunk'>@@ -47,7 +47,7 @@ void mpc32_mpc_init(struct mpc *mpc)</div><div class='ctx'> 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='ctx'> 	int mpcc_id;</div><div class='ctx'> </div><div class='del'>-	mpc1_mpc_init(mpc);</div><div class='add'>+	mpc3_mpc_init(mpc);</div><div class='ctx'> </div><div class='ctx'> 	if (mpc-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.mpc) {</div><div class='ctx'> 		if (mpc30-&gt;mpc_mask-&gt;MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE &amp;&amp; mpc30-&gt;mpc_mask-&gt;MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {</div><div class='hunk'>@@ -369,275 +369,279 @@ void mpc32_program_shaper_luta_settings(</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].red.custom_float_y);</div><div class='ctx'> </div><div class='ctx'> 	curve = params-&gt;arr_curve_points;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,</div><div class='add'>+	if (curve) {</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-void mpc32_program_shaper_lutb_settings(</div><div class='del'>-		struct mpc *mpc,</div><div class='del'>-		const struct pwl_params *params,</div><div class='del'>-		uint32_t mpcc_id)</div><div class='del'>-{</div><div class='del'>-	const struct gamma_curve *curve;</div><div class='del'>-	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='del'>-</div><div class='del'>-	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params-&gt;corner_points[0].blue.custom_float_x,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);</div><div class='del'>-	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params-&gt;corner_points[0].green.custom_float_x,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);</div><div class='del'>-	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params-&gt;corner_points[0].red.custom_float_x,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);</div><div class='del'>-</div><div class='del'>-	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params-&gt;corner_points[1].blue.custom_float_x,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].blue.custom_float_y);</div><div class='del'>-	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params-&gt;corner_points[1].green.custom_float_x,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].green.custom_float_y);</div><div class='del'>-	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params-&gt;corner_points[1].red.custom_float_x,</div><div class='del'>-			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].red.custom_float_y);</div><div class='del'>-</div><div class='del'>-	curve = params-&gt;arr_curve_points;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='del'>-		MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void mpc32_program_shaper_lutb_settings(</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		const struct pwl_params *params,</div><div class='add'>+		uint32_t mpcc_id)</div><div class='add'>+{</div><div class='add'>+	const struct gamma_curve *curve;</div><div class='add'>+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,</div><div class='add'>+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params-&gt;corner_points[0].blue.custom_float_x,</div><div class='add'>+		MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);</div><div class='add'>+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params-&gt;corner_points[0].green.custom_float_x,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);</div><div class='add'>+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params-&gt;corner_points[0].red.custom_float_x,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);</div><div class='ctx'> </div><div class='del'>-	curve += 2;</div><div class='del'>-	REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,</div><div class='add'>+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params-&gt;corner_points[1].blue.custom_float_x,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].blue.custom_float_y);</div><div class='add'>+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params-&gt;corner_points[1].green.custom_float_x,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].green.custom_float_y);</div><div class='add'>+	REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params-&gt;corner_points[1].red.custom_float_x,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params-&gt;corner_points[1].red.custom_float_y);</div><div class='add'>+</div><div class='add'>+	curve = params-&gt;arr_curve_points;</div><div class='add'>+	if (curve) {</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='ctx'> 			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+			MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+</div><div class='add'>+		curve += 2;</div><div class='add'>+		REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,</div><div class='add'>+				MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -874,7 +878,7 @@ void mpc32_set3dlut_ram10(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static void mpc32_set_3dlut_mode(</div><div class='add'>+void mpc32_set_3dlut_mode(</div><div class='ctx'> 		struct mpc *mpc,</div><div class='ctx'> 		enum dc_lut_mode mode,</div><div class='ctx'> 		bool is_color_channel_12bits,</div><div class='hunk'>@@ -991,7 +995,7 @@ static const struct mpc_funcs dcn32_mpc_funcs = {</div><div class='ctx'> 	.insert_plane = mpc1_insert_plane,</div><div class='ctx'> 	.remove_mpcc = mpc1_remove_mpcc,</div><div class='ctx'> 	.mpc_init = mpc32_mpc_init,</div><div class='del'>-	.mpc_init_single_inst = mpc1_mpc_init_single_inst,</div><div class='add'>+	.mpc_init_single_inst = mpc3_mpc_init_single_inst,</div><div class='ctx'> 	.update_blending = mpc2_update_blending,</div><div class='ctx'> 	.cursor_lock = mpc1_cursor_lock,</div><div class='ctx'> 	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,</div><div class='hunk'>@@ -1008,7 +1012,6 @@ static const struct mpc_funcs dcn32_mpc_funcs = {</div><div class='ctx'> 	.set_dwb_mux = mpc3_set_dwb_mux,</div><div class='ctx'> 	.disable_dwb_mux = mpc3_disable_dwb_mux,</div><div class='ctx'> 	.is_dwb_idle = mpc3_is_dwb_idle,</div><div class='del'>-	.set_out_rate_control = mpc3_set_out_rate_control,</div><div class='ctx'> 	.set_gamut_remap = mpc3_set_gamut_remap,</div><div class='ctx'> 	.program_shaper = mpc32_program_shaper,</div><div class='ctx'> 	.program_3dlut = mpc32_program_3dlut,</div><div class='hunk'>@@ -1017,6 +1020,7 @@ static const struct mpc_funcs dcn32_mpc_funcs = {</div><div class='ctx'> 	.release_rmu = NULL,</div><div class='ctx'> 	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,</div><div class='ctx'> 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,</div><div class='add'>+	.mpc_read_reg_state = mpc3_read_reg_state,</div><div class='ctx'> 	.set_bg_color = mpc1_set_bg_color,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h<br/>index 9622518826c9..8c9b20bcca85 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.h</a></div><div class='hunk'>@@ -391,4 +391,12 @@ void mpc32_select_3dlut_ram(</div><div class='ctx'> 		enum dc_lut_mode mode,</div><div class='ctx'> 		bool is_color_channel_12bits,</div><div class='ctx'> 		uint32_t mpcc_id);</div><div class='add'>+</div><div class='add'>+void mpc32_set_3dlut_mode(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	enum dc_lut_mode mode,</div><div class='add'>+	bool is_color_channel_12bits,</div><div class='add'>+	bool is_lut_size17x17x17,</div><div class='add'>+	uint32_t mpcc_id);</div><div class='add'>+</div><div class='ctx'> #endif		//__DC_MPCC_DCN32_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c<br/>new file mode 100644<br/>index 000000000000..eeac13fdd6f5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c</a></div><div class='hunk'>@@ -0,0 +1,635 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "dcn401_mpc.h"</div><div class='add'>+#include "dcn10/dcn10_cm_common.h"</div><div class='add'>+#include "basics/conversion.h"</div><div class='add'>+#include "mpc.h"</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	mpc401-&gt;mpc_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	mpc401-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	mpc401-&gt;mpc_shift-&gt;field_name, mpc401-&gt;mpc_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	switch (location) {</div><div class='add'>+	case MPCC_MOVABLE_CM_LOCATION_BEFORE:</div><div class='add'>+		REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id],</div><div class='add'>+				MPCC_MOVABLE_CM_LOCATION_CNTL, 0);</div><div class='add'>+		break;</div><div class='add'>+	case MPCC_MOVABLE_CM_LOCATION_AFTER:</div><div class='add'>+		REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id],</div><div class='add'>+				MPCC_MOVABLE_CM_LOCATION_CNTL, 1);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dc_lut_mode get3dlut_config(</div><div class='add'>+			struct mpc *mpc,</div><div class='add'>+			bool *is_17x17x17,</div><div class='add'>+			bool *is_12bits_color_channel,</div><div class='add'>+			int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	uint32_t i_mode, i_enable_10bits, lut_size;</div><div class='add'>+	enum dc_lut_mode mode;</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],</div><div class='add'>+			MPCC_MCM_3DLUT_MODE_CURRENT,  &amp;i_mode);</div><div class='add'>+</div><div class='add'>+	REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],</div><div class='add'>+			MPCC_MCM_3DLUT_30BIT_EN, &amp;i_enable_10bits);</div><div class='add'>+</div><div class='add'>+	switch (i_mode) {</div><div class='add'>+	case 0:</div><div class='add'>+		mode = LUT_BYPASS;</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		mode = LUT_RAM_A;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		mode = LUT_RAM_B;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		mode = LUT_BYPASS;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	if (i_enable_10bits &gt; 0)</div><div class='add'>+		*is_12bits_color_channel = false;</div><div class='add'>+	else</div><div class='add'>+		*is_12bits_color_channel = true;</div><div class='add'>+</div><div class='add'>+	REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &amp;lut_size);</div><div class='add'>+</div><div class='add'>+	if (lut_size == 0)</div><div class='add'>+		*is_17x17x17 = true;</div><div class='add'>+	else</div><div class='add'>+		*is_17x17x17 = false;</div><div class='add'>+</div><div class='add'>+	return mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B;</div><div class='add'>+	const struct pwl_params *lut1d = params.pwl;</div><div class='add'>+	const struct pwl_params *lut_shaper = params.pwl;</div><div class='add'>+	bool is_17x17x17;</div><div class='add'>+	bool is_12bits_color_channel;</div><div class='add'>+	const struct dc_rgb *lut0;</div><div class='add'>+	const struct dc_rgb *lut1;</div><div class='add'>+	const struct dc_rgb *lut2;</div><div class='add'>+	const struct dc_rgb *lut3;</div><div class='add'>+	int lut_size0;</div><div class='add'>+	int lut_size;</div><div class='add'>+	const struct tetrahedral_params *lut3d = params.lut3d;</div><div class='add'>+</div><div class='add'>+	switch (id) {</div><div class='add'>+	case MCM_LUT_1DLUT:</div><div class='add'>+		if (lut1d == NULL)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		mpc32_power_on_blnd_lut(mpc, mpcc_id, true);</div><div class='add'>+		mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);</div><div class='add'>+</div><div class='add'>+		if (next_mode == LUT_RAM_A)</div><div class='add'>+			mpc32_program_post1dluta_settings(mpc, mpcc_id, lut1d);</div><div class='add'>+		else</div><div class='add'>+			mpc32_program_post1dlutb_settings(mpc, mpcc_id, lut1d);</div><div class='add'>+</div><div class='add'>+		mpc32_program_post1dlut_pwl(</div><div class='add'>+				mpc, mpcc_id, lut1d-&gt;rgb_resulted, lut1d-&gt;hw_points_num);</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	case MCM_LUT_SHAPER:</div><div class='add'>+		if (lut_shaper == NULL)</div><div class='add'>+			return;</div><div class='add'>+		if (mpc-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.mpc)</div><div class='add'>+			mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);</div><div class='add'>+</div><div class='add'>+		mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);</div><div class='add'>+</div><div class='add'>+		if (next_mode == LUT_RAM_A)</div><div class='add'>+			mpc32_program_shaper_luta_settings(mpc, lut_shaper, mpcc_id);</div><div class='add'>+		else</div><div class='add'>+			mpc32_program_shaper_lutb_settings(mpc, lut_shaper, mpcc_id);</div><div class='add'>+</div><div class='add'>+		mpc32_program_shaper_lut(</div><div class='add'>+				mpc, lut_shaper-&gt;rgb_resulted, lut_shaper-&gt;hw_points_num, mpcc_id);</div><div class='add'>+</div><div class='add'>+		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);</div><div class='add'>+		break;</div><div class='add'>+	case MCM_LUT_3DLUT:</div><div class='add'>+		if (lut3d == NULL)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);</div><div class='add'>+</div><div class='add'>+		get3dlut_config(mpc, &amp;is_17x17x17, &amp;is_12bits_color_channel, mpcc_id);</div><div class='add'>+</div><div class='add'>+		is_17x17x17 = !lut3d-&gt;use_tetrahedral_9;</div><div class='add'>+		is_12bits_color_channel = lut3d-&gt;use_12bits;</div><div class='add'>+		if (is_17x17x17) {</div><div class='add'>+			lut0 = lut3d-&gt;tetrahedral_17.lut0;</div><div class='add'>+			lut1 = lut3d-&gt;tetrahedral_17.lut1;</div><div class='add'>+			lut2 = lut3d-&gt;tetrahedral_17.lut2;</div><div class='add'>+			lut3 = lut3d-&gt;tetrahedral_17.lut3;</div><div class='add'>+			lut_size0 = sizeof(lut3d-&gt;tetrahedral_17.lut0)/</div><div class='add'>+						sizeof(lut3d-&gt;tetrahedral_17.lut0[0]);</div><div class='add'>+			lut_size  = sizeof(lut3d-&gt;tetrahedral_17.lut1)/</div><div class='add'>+						sizeof(lut3d-&gt;tetrahedral_17.lut1[0]);</div><div class='add'>+		} else {</div><div class='add'>+			lut0 = lut3d-&gt;tetrahedral_9.lut0;</div><div class='add'>+			lut1 = lut3d-&gt;tetrahedral_9.lut1;</div><div class='add'>+			lut2 = lut3d-&gt;tetrahedral_9.lut2;</div><div class='add'>+			lut3 = lut3d-&gt;tetrahedral_9.lut3;</div><div class='add'>+			lut_size0 = sizeof(lut3d-&gt;tetrahedral_9.lut0)/</div><div class='add'>+					sizeof(lut3d-&gt;tetrahedral_9.lut0[0]);</div><div class='add'>+			lut_size  = sizeof(lut3d-&gt;tetrahedral_9.lut1)/</div><div class='add'>+					sizeof(lut3d-&gt;tetrahedral_9.lut1[0]);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+		mpc32_select_3dlut_ram(mpc, next_mode,</div><div class='add'>+					is_12bits_color_channel, mpcc_id);</div><div class='add'>+		mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);</div><div class='add'>+		if (is_12bits_color_channel)</div><div class='add'>+			mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);</div><div class='add'>+		else</div><div class='add'>+			mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);</div><div class='add'>+</div><div class='add'>+		mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);</div><div class='add'>+		if (is_12bits_color_channel)</div><div class='add'>+			mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);</div><div class='add'>+		else</div><div class='add'>+			mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);</div><div class='add'>+</div><div class='add'>+		mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);</div><div class='add'>+		if (is_12bits_color_channel)</div><div class='add'>+			mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);</div><div class='add'>+		else</div><div class='add'>+			mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);</div><div class='add'>+</div><div class='add'>+		mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);</div><div class='add'>+		if (is_12bits_color_channel)</div><div class='add'>+			mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);</div><div class='add'>+		else</div><div class='add'>+			mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);</div><div class='add'>+</div><div class='add'>+		if (mpc-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.mpc)</div><div class='add'>+			mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc401_program_lut_mode(</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		const enum MCM_LUT_ID id,</div><div class='add'>+		const enum MCM_LUT_XABLE xable,</div><div class='add'>+		bool lut_bank_a,</div><div class='add'>+		int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	switch (id) {</div><div class='add'>+	case MCM_LUT_3DLUT:</div><div class='add'>+		switch (xable) {</div><div class='add'>+		case MCM_LUT_DISABLE:</div><div class='add'>+			REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case MCM_LUT_ENABLE:</div><div class='add'>+			REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case MCM_LUT_SHAPER:</div><div class='add'>+		switch (xable) {</div><div class='add'>+		case MCM_LUT_DISABLE:</div><div class='add'>+			REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case MCM_LUT_ENABLE:</div><div class='add'>+			REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case MCM_LUT_1DLUT:</div><div class='add'>+		switch (xable) {</div><div class='add'>+		case MCM_LUT_DISABLE:</div><div class='add'>+			REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],</div><div class='add'>+					MPCC_MCM_1DLUT_MODE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case MCM_LUT_ENABLE:</div><div class='add'>+			REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],</div><div class='add'>+					MPCC_MCM_1DLUT_MODE, 2);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],</div><div class='add'>+				MPCC_MCM_1DLUT_SELECT, lut_bank_a ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	switch (id) {</div><div class='add'>+	case MCM_LUT_3DLUT:</div><div class='add'>+		mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id);</div><div class='add'>+		REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1);</div><div class='add'>+		break;</div><div class='add'>+	case MCM_LUT_SHAPER:</div><div class='add'>+		mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id);</div><div class='add'>+		break;</div><div class='add'>+	case MCM_LUT_1DLUT:</div><div class='add'>+		mpc32_configure_post1dlut(mpc, lut_bank_a, mpcc_id);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc_program_gamut_remap(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	unsigned int mpcc_id,</div><div class='add'>+	const uint16_t *regval,</div><div class='add'>+	enum mpcc_gamut_remap_id gamut_remap_block_id,</div><div class='add'>+	enum mpcc_gamut_remap_mode_select mode_select)</div><div class='add'>+{</div><div class='add'>+	struct color_matrices_reg gamut_regs;</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	switch (gamut_remap_block_id) {</div><div class='add'>+	case MPCC_OGAM_GAMUT_REMAP:</div><div class='add'>+</div><div class='add'>+		if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {</div><div class='add'>+			REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0,</div><div class='add'>+				MPCC_GAMUT_REMAP_MODE, mode_select);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		gamut_regs.shifts.csc_c11 = mpc401-&gt;mpc_shift-&gt;MPCC_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.masks.csc_c11 = mpc401-&gt;mpc_mask-&gt;MPCC_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.shifts.csc_c12 = mpc401-&gt;mpc_shift-&gt;MPCC_GAMUT_REMAP_C12_A;</div><div class='add'>+		gamut_regs.masks.csc_c12 = mpc401-&gt;mpc_mask-&gt;MPCC_GAMUT_REMAP_C12_A;</div><div class='add'>+</div><div class='add'>+		switch (mode_select) {</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_1:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_2:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cm_helper_program_color_matrices(</div><div class='add'>+			mpc-&gt;ctx,</div><div class='add'>+			regval,</div><div class='add'>+			&amp;gamut_regs);</div><div class='add'>+</div><div class='add'>+		//select coefficient set to use, set A (MODE_1) or set B (MODE_2)</div><div class='add'>+		REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, MPCC_GAMUT_REMAP_MODE, mode_select);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case MPCC_MCM_FIRST_GAMUT_REMAP:</div><div class='add'>+		if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {</div><div class='add'>+			REG_SET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mode_select);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		gamut_regs.shifts.csc_c11 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.masks.csc_c11 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.shifts.csc_c12 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;</div><div class='add'>+		gamut_regs.masks.csc_c12 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;</div><div class='add'>+</div><div class='add'>+		switch (mode_select) {</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_1:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_2:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cm_helper_program_color_matrices(</div><div class='add'>+			mpc-&gt;ctx,</div><div class='add'>+			regval,</div><div class='add'>+			&amp;gamut_regs);</div><div class='add'>+</div><div class='add'>+		//select coefficient set to use, set A (MODE_1) or set B (MODE_2)</div><div class='add'>+		REG_SET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mode_select);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case MPCC_MCM_SECOND_GAMUT_REMAP:</div><div class='add'>+		if (regval == NULL || mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {</div><div class='add'>+			REG_SET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id], 0,</div><div class='add'>+				MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mode_select);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		gamut_regs.shifts.csc_c11 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.masks.csc_c11 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.shifts.csc_c12 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;</div><div class='add'>+		gamut_regs.masks.csc_c12 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;</div><div class='add'>+</div><div class='add'>+		switch (mode_select) {</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_1:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_2:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cm_helper_program_color_matrices(</div><div class='add'>+			mpc-&gt;ctx,</div><div class='add'>+			regval,</div><div class='add'>+			&amp;gamut_regs);</div><div class='add'>+</div><div class='add'>+		//select coefficient set to use, set A (MODE_1) or set B (MODE_2)</div><div class='add'>+		REG_SET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id], 0,</div><div class='add'>+			MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mode_select);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc401_set_gamut_remap(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	const struct mpc_grph_gamut_adjustment *adjust)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+	uint32_t mode_select = 0;</div><div class='add'>+</div><div class='add'>+	if (adjust-&gt;gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) {</div><div class='add'>+		/* Bypass / Disable if type is bypass or hw */</div><div class='add'>+		mpc_program_gamut_remap(mpc, mpcc_id, NULL,</div><div class='add'>+			adjust-&gt;mpcc_gamut_remap_block_id, MPCC_GAMUT_REMAP_MODE_SELECT_0);</div><div class='add'>+	} else {</div><div class='add'>+		struct fixed31_32 arr_matrix[12];</div><div class='add'>+		uint16_t arr_reg_val[12];</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; 12; i++)</div><div class='add'>+			arr_matrix[i] = adjust-&gt;temperature_matrix[i];</div><div class='add'>+</div><div class='add'>+		convert_float_matrix(arr_reg_val, arr_matrix, 12);</div><div class='add'>+</div><div class='add'>+		switch (adjust-&gt;mpcc_gamut_remap_block_id) {</div><div class='add'>+		case MPCC_OGAM_GAMUT_REMAP:</div><div class='add'>+			REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id],</div><div class='add'>+				MPCC_GAMUT_REMAP_MODE_CURRENT, &amp;mode_select);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_MCM_FIRST_GAMUT_REMAP:</div><div class='add'>+			REG_GET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id],</div><div class='add'>+				MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, &amp;mode_select);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_MCM_SECOND_GAMUT_REMAP:</div><div class='add'>+			REG_GET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id],</div><div class='add'>+				MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, &amp;mode_select);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		//If current set in use not set A (MODE_1), then use set A, otherwise use set B</div><div class='add'>+		if (mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_1)</div><div class='add'>+			mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_1;</div><div class='add'>+		else</div><div class='add'>+			mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_2;</div><div class='add'>+</div><div class='add'>+		mpc_program_gamut_remap(mpc, mpcc_id, arr_reg_val,</div><div class='add'>+			adjust-&gt;mpcc_gamut_remap_block_id, mode_select);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc_read_gamut_remap(struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	uint16_t *regval,</div><div class='add'>+	enum mpcc_gamut_remap_id gamut_remap_block_id,</div><div class='add'>+	uint32_t *mode_select)</div><div class='add'>+{</div><div class='add'>+	struct color_matrices_reg gamut_regs = {0};</div><div class='add'>+	struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);</div><div class='add'>+</div><div class='add'>+	switch (gamut_remap_block_id) {</div><div class='add'>+	case MPCC_OGAM_GAMUT_REMAP:</div><div class='add'>+		//current coefficient set in use</div><div class='add'>+		REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, mode_select);</div><div class='add'>+</div><div class='add'>+		gamut_regs.shifts.csc_c11 = mpc401-&gt;mpc_shift-&gt;MPCC_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.masks.csc_c11 = mpc401-&gt;mpc_mask-&gt;MPCC_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.shifts.csc_c12 = mpc401-&gt;mpc_shift-&gt;MPCC_GAMUT_REMAP_C12_A;</div><div class='add'>+		gamut_regs.masks.csc_c12 = mpc401-&gt;mpc_mask-&gt;MPCC_GAMUT_REMAP_C12_A;</div><div class='add'>+</div><div class='add'>+		switch (*mode_select) {</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_1:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_2:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case MPCC_MCM_FIRST_GAMUT_REMAP:</div><div class='add'>+		REG_GET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id],</div><div class='add'>+				MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mode_select);</div><div class='add'>+</div><div class='add'>+		gamut_regs.shifts.csc_c11 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.masks.csc_c11 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.shifts.csc_c12 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;</div><div class='add'>+		gamut_regs.masks.csc_c12 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;</div><div class='add'>+</div><div class='add'>+		switch (*mode_select) {</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_1:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_2:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case MPCC_MCM_SECOND_GAMUT_REMAP:</div><div class='add'>+		REG_GET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id],</div><div class='add'>+				MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mode_select);</div><div class='add'>+</div><div class='add'>+		gamut_regs.shifts.csc_c11 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.masks.csc_c11 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;</div><div class='add'>+		gamut_regs.shifts.csc_c12 = mpc401-&gt;mpc_shift-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;</div><div class='add'>+		gamut_regs.masks.csc_c12 = mpc401-&gt;mpc_mask-&gt;MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;</div><div class='add'>+</div><div class='add'>+		switch (*mode_select) {</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_1:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		case MPCC_GAMUT_REMAP_MODE_SELECT_2:</div><div class='add'>+			gamut_regs.csc_c11_c12 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[mpcc_id]);</div><div class='add'>+			gamut_regs.csc_c33_c34 = REG(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[mpcc_id]);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (*mode_select != MPCC_GAMUT_REMAP_MODE_SELECT_0) {</div><div class='add'>+		cm_helper_read_color_matrices(</div><div class='add'>+			mpc401-&gt;base.ctx,</div><div class='add'>+			regval,</div><div class='add'>+			&amp;gamut_regs);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mpc401_get_gamut_remap(struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	struct mpc_grph_gamut_adjustment *adjust)</div><div class='add'>+{</div><div class='add'>+	uint16_t arr_reg_val[12] = {0};</div><div class='add'>+	uint32_t mode_select = MPCC_GAMUT_REMAP_MODE_SELECT_0;</div><div class='add'>+</div><div class='add'>+	mpc_read_gamut_remap(mpc, mpcc_id, arr_reg_val, adjust-&gt;mpcc_gamut_remap_block_id, &amp;mode_select);</div><div class='add'>+</div><div class='add'>+	if (mode_select == MPCC_GAMUT_REMAP_MODE_SELECT_0) {</div><div class='add'>+		adjust-&gt;gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adjust-&gt;gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;</div><div class='add'>+	convert_hw_matrix(adjust-&gt;temperature_matrix,</div><div class='add'>+		arr_reg_val, ARRAY_SIZE(arr_reg_val));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct mpc_funcs dcn401_mpc_funcs = {</div><div class='add'>+	.read_mpcc_state = mpc1_read_mpcc_state,</div><div class='add'>+	.insert_plane = mpc1_insert_plane,</div><div class='add'>+	.remove_mpcc = mpc1_remove_mpcc,</div><div class='add'>+	.mpc_init = mpc32_mpc_init,</div><div class='add'>+	.mpc_init_single_inst = mpc3_mpc_init_single_inst,</div><div class='add'>+	.update_blending = mpc2_update_blending,</div><div class='add'>+	.cursor_lock = mpc1_cursor_lock,</div><div class='add'>+	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,</div><div class='add'>+	.wait_for_idle = mpc2_assert_idle_mpcc,</div><div class='add'>+	.assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,</div><div class='add'>+	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,</div><div class='add'>+	.set_denorm =  mpc3_set_denorm,</div><div class='add'>+	.set_denorm_clamp = mpc3_set_denorm_clamp,</div><div class='add'>+	.set_output_csc = mpc3_set_output_csc,</div><div class='add'>+	.set_ocsc_default = mpc3_set_ocsc_default,</div><div class='add'>+	.set_output_gamma = mpc3_set_output_gamma,</div><div class='add'>+	.insert_plane_to_secondary = NULL,</div><div class='add'>+	.remove_mpcc_from_secondary =  NULL,</div><div class='add'>+	.set_dwb_mux = mpc3_set_dwb_mux,</div><div class='add'>+	.disable_dwb_mux = mpc3_disable_dwb_mux,</div><div class='add'>+	.is_dwb_idle = mpc3_is_dwb_idle,</div><div class='add'>+	.set_gamut_remap = mpc401_set_gamut_remap,</div><div class='add'>+	.program_shaper = mpc32_program_shaper,</div><div class='add'>+	.program_3dlut = mpc32_program_3dlut,</div><div class='add'>+	.program_1dlut = mpc32_program_post1dlut,</div><div class='add'>+	.acquire_rmu = NULL,</div><div class='add'>+	.release_rmu = NULL,</div><div class='add'>+	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,</div><div class='add'>+	.get_mpc_out_mux = mpc1_get_mpc_out_mux,</div><div class='add'>+	.mpc_read_reg_state = mpc3_read_reg_state,</div><div class='add'>+	.set_bg_color = mpc1_set_bg_color,</div><div class='add'>+	.set_movable_cm_location = mpc401_set_movable_cm_location,</div><div class='add'>+	.update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select,</div><div class='add'>+	.populate_lut = mpc401_populate_lut,</div><div class='add'>+	.program_lut_read_write_control = mpc401_program_lut_read_write_control,</div><div class='add'>+	.program_lut_mode = mpc401_program_lut_mode,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+void dcn401_mpc_construct(struct dcn401_mpc *mpc401,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dcn401_mpc_registers *mpc_regs,</div><div class='add'>+	const struct dcn401_mpc_shift *mpc_shift,</div><div class='add'>+	const struct dcn401_mpc_mask *mpc_mask,</div><div class='add'>+	int num_mpcc,</div><div class='add'>+	int num_rmu)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	mpc401-&gt;base.ctx = ctx;</div><div class='add'>+</div><div class='add'>+	mpc401-&gt;base.funcs = &amp;dcn401_mpc_funcs;</div><div class='add'>+</div><div class='add'>+	mpc401-&gt;mpc_regs = mpc_regs;</div><div class='add'>+	mpc401-&gt;mpc_shift = mpc_shift;</div><div class='add'>+	mpc401-&gt;mpc_mask = mpc_mask;</div><div class='add'>+</div><div class='add'>+	mpc401-&gt;mpcc_in_use_mask = 0;</div><div class='add'>+	mpc401-&gt;num_mpcc = num_mpcc;</div><div class='add'>+	mpc401-&gt;num_rmu = num_rmu;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_MPCC; i++)</div><div class='add'>+		mpc3_init_mpcc(&amp;mpc401-&gt;base.mpcc_array[i], i);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h<br/>new file mode 100644<br/>index 000000000000..fdc42f8ab3ff<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h</a></div><div class='hunk'>@@ -0,0 +1,257 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_MPCC_DCN401_H__</div><div class='add'>+#define __DC_MPCC_DCN401_H__</div><div class='add'>+#include "dcn30/dcn30_mpc.h"</div><div class='add'>+#include "dcn32/dcn32_mpc.h"</div><div class='add'>+</div><div class='add'>+#define TO_DCN401_MPC(mpc_base) \</div><div class='add'>+	container_of(mpc_base, struct dcn401_mpc, base)</div><div class='add'>+</div><div class='add'>+#define MPC_REG_VARIABLE_LIST_DCN4_01 \</div><div class='add'>+	MPC_REG_VARIABLE_LIST_DCN3_0; \</div><div class='add'>+	MPC_REG_VARIABLE_LIST_DCN32; \</div><div class='add'>+	uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_MODE[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_MODE[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPCC_MCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \</div><div class='add'>+	uint32_t MPCC_MCM_3DLUT_FAST_LOAD_STATUS[MAX_MPCC];</div><div class='add'>+</div><div class='add'>+#define MPC_COMMON_MASK_SH_LIST_DCN4_01(mask_sh) \</div><div class='add'>+	MPC_COMMON_MASK_SH_LIST_DCN32(mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C24_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C31_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C32_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C33_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C34_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C11_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C12_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C13_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C14_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C21_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C22_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C23_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C24_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C31_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C32_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C33_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C34_A, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \</div><div class='add'>+	SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define MPC_REG_LIST_DCN4_01_RI(inst) \</div><div class='add'>+	MPC_REG_LIST_DCN3_2_RI(inst),\</div><div class='add'>+	SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst), \</div><div class='add'>+	SRII(MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM, inst),\</div><div class='add'>+	SRII(MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM, inst)</div><div class='add'>+</div><div class='add'>+#define MPC_REG_FIELD_LIST_DCN4_01(type)\</div><div class='add'>+	MPC_REG_FIELD_LIST_DCN3_0(type);\</div><div class='add'>+	MPC_REG_FIELD_LIST_DCN32(type);\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_MODE;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C13_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C14_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C21_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C22_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C23_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C24_A;\</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C31_A; \</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C32_A; \</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C33_A; \</div><div class='add'>+	type MPCC_MCM_FIRST_GAMUT_REMAP_C34_A; \</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_MODE;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C13_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C14_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C21_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C22_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C23_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C24_A;\</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C31_A; \</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C32_A; \</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C33_A; \</div><div class='add'>+	type MPCC_MCM_SECOND_GAMUT_REMAP_C34_A; \</div><div class='add'>+	type MPCC_MCM_3DLUT_FL_SEL;\</div><div class='add'>+	type MPCC_MCM_3DLUT_FL_DONE;\</div><div class='add'>+	type MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW;\</div><div class='add'>+	type MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW</div><div class='add'>+</div><div class='add'>+struct dcn401_mpc_shift {</div><div class='add'>+	MPC_REG_FIELD_LIST_DCN4_01(uint8_t);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_mpc_mask {</div><div class='add'>+	MPC_REG_FIELD_LIST_DCN4_01(uint32_t);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_mpc_registers {</div><div class='add'>+	MPC_REG_VARIABLE_LIST_DCN4_01</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcn401_mpc {</div><div class='add'>+	struct mpc base;</div><div class='add'>+</div><div class='add'>+	int mpcc_in_use_mask;</div><div class='add'>+	int num_mpcc;</div><div class='add'>+	const struct dcn401_mpc_registers *mpc_regs;</div><div class='add'>+	const struct dcn401_mpc_shift *mpc_shift;</div><div class='add'>+	const struct dcn401_mpc_mask *mpc_mask;</div><div class='add'>+	int num_rmu;</div><div class='add'>+};</div><div class='add'>+void dcn401_mpc_construct(struct dcn401_mpc *mpc401,</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct dcn401_mpc_registers *mpc_regs,</div><div class='add'>+	const struct dcn401_mpc_shift *mpc_shift,</div><div class='add'>+	const struct dcn401_mpc_mask *mpc_mask,</div><div class='add'>+	int num_mpcc,</div><div class='add'>+	int num_rmu);</div><div class='add'>+</div><div class='add'>+void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id);</div><div class='add'>+void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params,</div><div class='add'>+		bool lut_bank_a, int mpcc_id);</div><div class='add'>+</div><div class='add'>+void mpc401_program_lut_mode(</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		const enum MCM_LUT_ID id,</div><div class='add'>+		const enum MCM_LUT_XABLE xable,</div><div class='add'>+		bool lut_bank_a,</div><div class='add'>+		int mpcc_id);</div><div class='add'>+</div><div class='add'>+void mpc401_program_lut_read_write_control(</div><div class='add'>+		struct mpc *mpc,</div><div class='add'>+		const enum MCM_LUT_ID id,</div><div class='add'>+		bool lut_bank_a,</div><div class='add'>+		int mpcc_id);</div><div class='add'>+</div><div class='add'>+void mpc401_set_gamut_remap(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	const struct mpc_grph_gamut_adjustment *adjust);</div><div class='add'>+</div><div class='add'>+void mpc401_get_gamut_remap(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	struct mpc_grph_gamut_adjustment *adjust);</div><div class='add'>+</div><div class='add'>+void mpc401_update_3dlut_fast_load_select(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	int hubp_idx);</div><div class='add'>+</div><div class='add'>+void mpc_program_gamut_remap(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	unsigned int mpcc_id,</div><div class='add'>+	const uint16_t *regval,</div><div class='add'>+	enum mpcc_gamut_remap_id gamut_remap_block_id,</div><div class='add'>+	enum mpcc_gamut_remap_mode_select mode_select);</div><div class='add'>+</div><div class='add'>+void mpc_read_gamut_remap(struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	uint16_t *regval,</div><div class='add'>+	enum mpcc_gamut_remap_id gamut_remap_block_id,</div><div class='add'>+	uint32_t *mode_select);</div><div class='add'>+</div><div class='add'>+void mpc401_update_3dlut_fast_load_select(</div><div class='add'>+	struct mpc *mpc,</div><div class='add'>+	int mpcc_id,</div><div class='add'>+	int hubp_idx);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/opp/Makefile b/drivers/gpu/drm/amd/display/dc/opp/Makefile<br/>new file mode 100644<br/>index 000000000000..1be76754db30<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/Makefile</a></div><div class='hunk'>@@ -0,0 +1,51 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN10</div><div class='add'>+###############################################################################</div><div class='add'>+OPP_DCN10 = dcn10_opp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPP_DCN10 = $(addprefix $(AMDDALPATH)/dc/opp/dcn10/,$(OPP_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPP_DCN10)</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN20</div><div class='add'>+###############################################################################</div><div class='add'>+OPP_DCN20 = dcn20_opp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPP_DCN20 = $(addprefix $(AMDDALPATH)/dc/opp/dcn20/,$(OPP_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPP_DCN20)</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN35</div><div class='add'>+###############################################################################</div><div class='add'>+OPP_DCN35 = dcn35_opp.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPP_DCN35 = $(addprefix $(AMDDALPATH)/dc/opp/dcn35/,$(OPP_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPP_DCN35)</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c<br/>index 5838a11efd00..45d418636d0c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c</a></div><div class='hunk'>@@ -168,6 +168,10 @@ static void opp1_set_pixel_encoding(</div><div class='ctx'> </div><div class='ctx'> 	case PIXEL_ENCODING_RGB:</div><div class='ctx'> 	case PIXEL_ENCODING_YCBCR444:</div><div class='add'>+		REG_UPDATE_3(FMT_CONTROL,</div><div class='add'>+				FMT_PIXEL_ENCODING, 0,</div><div class='add'>+				FMT_SUBSAMPLING_MODE, 0,</div><div class='add'>+				FMT_CBCR_BIT_REDUCTION_BYPASS, 0);</div><div class='ctx'> 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case PIXEL_ENCODING_YCBCR422:</div><div class='hunk'>@@ -177,7 +181,10 @@ static void opp1_set_pixel_encoding(</div><div class='ctx'> 				FMT_CBCR_BIT_REDUCTION_BYPASS, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case PIXEL_ENCODING_YCBCR420:</div><div class='del'>-		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);</div><div class='add'>+		REG_UPDATE_3(FMT_CONTROL,</div><div class='add'>+				FMT_PIXEL_ENCODING, 2,</div><div class='add'>+				FMT_SUBSAMPLING_MODE, 2,</div><div class='add'>+				FMT_CBCR_BIT_REDUCTION_BYPASS, 1);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -365,6 +372,17 @@ void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)</div><div class='ctx'> 	REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+void opp1_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);</div><div class='add'>+</div><div class='add'>+	opp_reg_state-&gt;fmt_control = REG_READ(FMT_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;oppbuf_control = REG_READ(OPPBUF_CONTROL);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*****************************************/</div><div class='ctx'> /* Constructor, Destructor               */</div><div class='ctx'> /*****************************************/</div><div class='hunk'>@@ -385,7 +403,8 @@ static const struct opp_funcs dcn10_opp_funcs = {</div><div class='ctx'> 		.opp_program_dpg_dimensions = NULL,</div><div class='ctx'> 		.dpg_is_blanked = NULL,</div><div class='ctx'> 		.dpg_is_pending = NULL,</div><div class='del'>-		.opp_destroy = opp1_destroy</div><div class='add'>+		.opp_destroy = opp1_destroy,</div><div class='add'>+		.opp_read_reg_state = opp1_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn10_opp_construct(struct dcn10_opp *oppn10,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h<br/>index 2c0ecfa5a643..38d0d530a9b7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h</a></div><div class='hunk'>@@ -63,7 +63,8 @@</div><div class='ctx'> 	uint32_t OPPBUF_CONTROL1; \</div><div class='ctx'> 	uint32_t OPPBUF_3D_PARAMETERS_0; \</div><div class='ctx'> 	uint32_t OPPBUF_3D_PARAMETERS_1; \</div><div class='del'>-	uint32_t OPP_PIPE_CONTROL</div><div class='add'>+	uint32_t OPP_PIPE_CONTROL; \</div><div class='add'>+	uint32_t OPP_PIPE_CRC_CONTROL</div><div class='ctx'> </div><div class='ctx'> #define OPP_MASK_SH_LIST_DCN(mask_sh) \</div><div class='ctx'> 	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \</div><div class='hunk'>@@ -79,6 +80,8 @@</div><div class='ctx'> 	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \</div><div class='ctx'> 	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \</div><div class='ctx'> 	OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \</div><div class='add'>+	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh), \</div><div class='add'>+	OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh), \</div><div class='ctx'> 	OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \</div><div class='ctx'> 	OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \</div><div class='ctx'> 	OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \</div><div class='hunk'>@@ -151,7 +154,6 @@ struct dcn10_opp {</div><div class='ctx'> 	const struct dcn10_opp_registers *regs;</div><div class='ctx'> 	const struct dcn10_opp_shift *opp_shift;</div><div class='ctx'> 	const struct dcn10_opp_mask *opp_mask;</div><div class='del'>-</div><div class='ctx'> 	bool is_write_to_ram_a_safe;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -186,4 +188,6 @@ void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);</div><div class='ctx'> </div><div class='ctx'> void opp1_destroy(struct output_pixel_processor **opp);</div><div class='ctx'> </div><div class='add'>+void opp1_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c<br/>index fbf1b6370eb2..ce826a5be4c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include "core_types.h"</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dcn20_opp.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='hunk'>@@ -350,19 +351,44 @@ bool opp2_dpg_is_pending(struct output_pixel_processor *opp)</div><div class='ctx'> 	return (dpg_en == 1 &amp;&amp; double_buffer_pending == 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void opp2_program_left_edge_extra_pixel (</div><div class='add'>+void opp2_program_left_edge_extra_pixel(</div><div class='ctx'> 		struct output_pixel_processor *opp,</div><div class='del'>-		bool count)</div><div class='add'>+		enum dc_pixel_encoding pixel_encoding,</div><div class='add'>+		bool is_primary)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);</div><div class='add'>+	uint32_t count = opp2_get_left_edge_extra_pixel_count(opp, pixel_encoding, is_primary);</div><div class='ctx'> </div><div class='del'>-	/* Specifies the number of extra left edge pixels that are supplied to</div><div class='add'>+	/*</div><div class='add'>+	 * Specifies the number of extra left edge pixels that are supplied to</div><div class='ctx'> 	 * the 422 horizontal chroma sub-sample filter.</div><div class='del'>-	 * Note that when left edge pixel is not "0", fmt pixel encoding can be in either 420 or 422 mode</div><div class='del'>-	 * */</div><div class='add'>+	 */</div><div class='ctx'> 	REG_UPDATE(FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,</div><div class='add'>+		enum dc_pixel_encoding pixel_encoding, bool is_primary)</div><div class='add'>+{</div><div class='add'>+	if ((pixel_encoding == PIXEL_ENCODING_YCBCR422 || pixel_encoding == PIXEL_ENCODING_YCBCR420) &amp;&amp;</div><div class='add'>+			!opp-&gt;ctx-&gt;dc-&gt;debug.force_chroma_subsampling_1tap &amp;&amp;</div><div class='add'>+			!is_primary)</div><div class='add'>+		return 1;</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void opp2_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);</div><div class='add'>+</div><div class='add'>+	opp_reg_state-&gt;dpg_control = REG_READ(DPG_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;fmt_control = REG_READ(FMT_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;oppbuf_control = REG_READ(OPPBUF_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*****************************************/</div><div class='ctx'> /* Constructor, Destructor               */</div><div class='ctx'> /*****************************************/</div><div class='hunk'>@@ -380,6 +406,8 @@ static struct opp_funcs dcn20_opp_funcs = {</div><div class='ctx'> 		.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,</div><div class='ctx'> 		.opp_destroy = opp1_destroy,</div><div class='ctx'> 		.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,</div><div class='add'>+		.opp_get_left_edge_extra_pixel_count = opp2_get_left_edge_extra_pixel_count,</div><div class='add'>+		.opp_read_reg_state = opp2_read_reg_state</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn20_opp_construct(struct dcn20_opp *oppn20,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h<br/>index 8f186abd558d..fb0c047c1788 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h</a></div><div class='hunk'>@@ -59,7 +59,8 @@</div><div class='ctx'> 	uint32_t DPG_COLOUR_G_Y; \</div><div class='ctx'> 	uint32_t DPG_COLOUR_R_CR; \</div><div class='ctx'> 	uint32_t DPG_RAMP_CONTROL; \</div><div class='del'>-	uint32_t DPG_STATUS</div><div class='add'>+	uint32_t DPG_STATUS; \</div><div class='add'>+	uint32_t DSCRM_DSC_FORWARD_CONFIG</div><div class='ctx'> </div><div class='ctx'> #define OPP_DPG_MASK_SH_LIST(mask_sh) \</div><div class='ctx'> 	OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \</div><div class='hunk'>@@ -167,6 +168,11 @@ void opp2_dpg_set_blank_color(</div><div class='ctx'> </div><div class='ctx'> void opp2_program_left_edge_extra_pixel (</div><div class='ctx'> 		struct output_pixel_processor *opp,</div><div class='del'>-		bool count);</div><div class='add'>+		enum dc_pixel_encoding pixel_encoding, bool is_primary);</div><div class='add'>+</div><div class='add'>+uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp,</div><div class='add'>+		enum dc_pixel_encoding pixel_encoding, bool is_primary);</div><div class='add'>+</div><div class='add'>+void opp2_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c<br/>index 3542b51c9aac..e11c4e16402f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c</a></div><div class='hunk'>@@ -51,3 +51,16 @@ void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);</div><div class='add'>+</div><div class='add'>+	opp_reg_state-&gt;dpg_control = REG_READ(DPG_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;fmt_control = REG_READ(FMT_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_abm_control = REG_READ(OPP_ABM_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;oppbuf_control = REG_READ(OPPBUF_CONTROL);</div><div class='add'>+	opp_reg_state-&gt;dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h<br/>index a9a413527801..c6cace90e8f2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h</a></div><div class='hunk'>@@ -31,7 +31,8 @@</div><div class='ctx'> </div><div class='ctx'> #define OPP_REG_VARIABLE_LIST_DCN3_5  \</div><div class='ctx'> 	OPP_REG_VARIABLE_LIST_DCN2_0; \</div><div class='del'>-	uint32_t OPP_TOP_CLK_CONTROL</div><div class='add'>+	uint32_t OPP_TOP_CLK_CONTROL; \</div><div class='add'>+	uint32_t OPP_ABM_CONTROL</div><div class='ctx'> </div><div class='ctx'> #define OPP_MASK_SH_LIST_DCN35(mask_sh)  \</div><div class='ctx'> 	OPP_MASK_SH_LIST_DCN20(mask_sh), \</div><div class='hunk'>@@ -64,4 +65,5 @@ void dcn35_opp_construct(struct dcn20_opp *oppn20,</div><div class='ctx'> </div><div class='ctx'> void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable);</div><div class='ctx'> </div><div class='add'>+void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile<br/>index bb213335fb9f..29fb610c8660 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/Makefile</a></div><div class='hunk'>@@ -105,4 +105,10 @@ AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35)</div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='add'>+OPTC_DCN401 = dcn401_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN401 = $(addprefix $(AMDDALPATH)/dc/optc/dcn401/,$(OPTC_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN401)</div><div class='ctx'> endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c<br/>index 0e8f4f36c87c..6f7b0f816f2a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c</a></div><div class='hunk'>@@ -65,7 +65,8 @@ void optc1_program_global_sync(</div><div class='ctx'> 		int vready_offset,</div><div class='ctx'> 		int vstartup_start,</div><div class='ctx'> 		int vupdate_offset,</div><div class='del'>-		int vupdate_width)</div><div class='add'>+		int vupdate_width,</div><div class='add'>+		int pstate_keepout)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> </div><div class='hunk'>@@ -73,6 +74,7 @@ void optc1_program_global_sync(</div><div class='ctx'> 	optc1-&gt;vstartup_start = vstartup_start;</div><div class='ctx'> 	optc1-&gt;vupdate_offset = vupdate_offset;</div><div class='ctx'> 	optc1-&gt;vupdate_width = vupdate_width;</div><div class='add'>+	optc1-&gt;pstate_keepout = pstate_keepout;</div><div class='ctx'> </div><div class='ctx'> 	if (optc1-&gt;vstartup_start == 0) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -146,6 +148,7 @@ void optc1_setup_vertical_interrupt2(</div><div class='ctx'>  * @vstartup_start: Vstartup period.</div><div class='ctx'>  * @vupdate_offset: Vupdate starting position.</div><div class='ctx'>  * @vupdate_width: Vupdate duration.</div><div class='add'>+ * @pstate_keepout: determines low power mode timing during refresh</div><div class='ctx'>  * @signal: DC signal types.</div><div class='ctx'>  * @use_vbios: to program timings from BIOS command table.</div><div class='ctx'>  *</div><div class='hunk'>@@ -157,6 +160,7 @@ void optc1_program_timing(</div><div class='ctx'> 	int vstartup_start,</div><div class='ctx'> 	int vupdate_offset,</div><div class='ctx'> 	int vupdate_width,</div><div class='add'>+	int pstate_keepout,</div><div class='ctx'> 	const enum signal_type signal,</div><div class='ctx'> 	bool use_vbios)</div><div class='ctx'> {</div><div class='hunk'>@@ -177,6 +181,7 @@ void optc1_program_timing(</div><div class='ctx'> 	optc1-&gt;vstartup_start = vstartup_start;</div><div class='ctx'> 	optc1-&gt;vupdate_offset = vupdate_offset;</div><div class='ctx'> 	optc1-&gt;vupdate_width = vupdate_width;</div><div class='add'>+	optc1-&gt;pstate_keepout = pstate_keepout;</div><div class='ctx'> 	patched_crtc_timing = *dc_crtc_timing;</div><div class='ctx'> 	apply_front_porch_workaround(&amp;patched_crtc_timing);</div><div class='ctx'> 	optc1-&gt;orginal_patched_timing = patched_crtc_timing;</div><div class='hunk'>@@ -282,7 +287,8 @@ void optc1_program_timing(</div><div class='ctx'> 			vready_offset,</div><div class='ctx'> 			vstartup_start,</div><div class='ctx'> 			vupdate_offset,</div><div class='del'>-			vupdate_width);</div><div class='add'>+			vupdate_width,</div><div class='add'>+			pstate_keepout);</div><div class='ctx'> </div><div class='ctx'> 	optc-&gt;funcs-&gt;set_vtg_params(optc, dc_crtc_timing, true);</div><div class='ctx'> </div><div class='hunk'>@@ -296,8 +302,7 @@ void optc1_program_timing(</div><div class='ctx'> 	/* Enable stereo - only when we need to pack 3D frame. Other types</div><div class='ctx'> 	 * of stereo handled in explicit call</div><div class='ctx'> 	 */</div><div class='del'>-</div><div class='del'>-	if (optc1_is_two_pixels_per_containter(&amp;patched_crtc_timing) || optc1-&gt;opp_count == 2)</div><div class='add'>+	if (optc-&gt;funcs-&gt;is_two_pixels_per_container(&amp;patched_crtc_timing) || optc1-&gt;opp_count == 2)</div><div class='ctx'> 		h_div = H_TIMING_DIV_BY2;</div><div class='ctx'> </div><div class='ctx'> 	if (REG(OPTC_DATA_FORMAT_CONTROL) &amp;&amp; optc1-&gt;tg_mask-&gt;OPTC_DATA_FORMAT != 0) {</div><div class='hunk'>@@ -1307,7 +1312,7 @@ bool optc1_get_hw_timing(struct timing_generator *tg,</div><div class='ctx'> 	if (tg == NULL || hw_crtc_timing == NULL)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	optc1_read_otg_state(DCN10TG_FROM_TG(tg), &amp;s);</div><div class='add'>+	optc1_read_otg_state(tg, &amp;s);</div><div class='ctx'> </div><div class='ctx'> 	hw_crtc_timing-&gt;h_total = s.h_total + 1;</div><div class='ctx'> 	hw_crtc_timing-&gt;h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);</div><div class='hunk'>@@ -1323,9 +1328,11 @@ bool optc1_get_hw_timing(struct timing_generator *tg,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-void optc1_read_otg_state(struct optc *optc1,</div><div class='add'>+void optc1_read_otg_state(struct timing_generator *optc,</div><div class='ctx'> 		struct dcn_otg_state *s)</div><div class='ctx'> {</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='ctx'> 	REG_GET(OTG_CONTROL,</div><div class='ctx'> 			OTG_MASTER_EN, &amp;s-&gt;otg_enabled);</div><div class='ctx'> </div><div class='hunk'>@@ -1383,6 +1390,9 @@ void optc1_read_otg_state(struct optc *optc1,</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,</div><div class='ctx'> 			OTG_VERTICAL_INTERRUPT2_LINE_START, &amp;s-&gt;vertical_interrupt2_line);</div><div class='add'>+</div><div class='add'>+	s-&gt;otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);</div><div class='add'>+	s-&gt;otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool optc1_get_otg_active_size(struct timing_generator *optc,</div><div class='hunk'>@@ -1411,8 +1421,8 @@ bool optc1_get_otg_active_size(struct timing_generator *optc,</div><div class='ctx'> 			OTG_H_BLANK_START, &amp;h_blank_start,</div><div class='ctx'> 			OTG_H_BLANK_END, &amp;h_blank_end);</div><div class='ctx'> </div><div class='del'>-	*otg_active_width = v_blank_start - v_blank_end;</div><div class='del'>-	*otg_active_height = h_blank_start - h_blank_end;</div><div class='add'>+	*otg_active_width = h_blank_start - h_blank_end;</div><div class='add'>+	*otg_active_height = v_blank_start - v_blank_end;</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1462,37 +1472,71 @@ bool optc1_configure_crc(struct timing_generator *optc,</div><div class='ctx'> 	if (!optc1_is_tg_enabled(optc))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	REG_WRITE(OTG_CRC_CNTL, 0);</div><div class='add'>+	if (!params-&gt;enable || params-&gt;reset)</div><div class='add'>+		REG_WRITE(OTG_CRC_CNTL, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (!params-&gt;enable)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/* Program frame boundaries */</div><div class='del'>-	/* Window A x axis start and end. */</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='del'>-			OTG_CRC0_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='del'>-</div><div class='del'>-	/* Window A y axis start and end. */</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='del'>-			OTG_CRC0_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='del'>-</div><div class='del'>-	/* Window B x axis start and end. */</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='del'>-			OTG_CRC0_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='del'>-</div><div class='del'>-	/* Window B y axis start and end. */</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='del'>-			OTG_CRC0_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='del'>-</div><div class='del'>-	/* Set crc mode and selection, and enable. Only using CRC0*/</div><div class='del'>-	REG_UPDATE_3(OTG_CRC_CNTL,</div><div class='del'>-			OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='del'>-			OTG_CRC0_SELECT, params-&gt;selection,</div><div class='del'>-			OTG_CRC_EN, 1);</div><div class='add'>+	switch (params-&gt;crc_eng_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='add'>+				OTG_CRC0_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='add'>+				OTG_CRC0_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='add'>+				OTG_CRC0_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='add'>+				OTG_CRC0_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='add'>+</div><div class='add'>+		/* Set crc mode and selection, and enable.*/</div><div class='add'>+		REG_UPDATE_3(OTG_CRC_CNTL,</div><div class='add'>+				OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+				OTG_CRC0_SELECT, params-&gt;selection,</div><div class='add'>+				OTG_CRC_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='add'>+				OTG_CRC1_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='add'>+				OTG_CRC1_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='add'>+				OTG_CRC1_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='add'>+				OTG_CRC1_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='add'>+</div><div class='add'>+		/* Set crc mode and selection, and enable.*/</div><div class='add'>+		REG_UPDATE_3(OTG_CRC_CNTL,</div><div class='add'>+				OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+				OTG_CRC1_SELECT, params-&gt;selection,</div><div class='add'>+				OTG_CRC_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -1501,6 +1545,7 @@ bool optc1_configure_crc(struct timing_generator *optc,</div><div class='ctx'>  * optc1_get_crc - Capture CRC result per component</div><div class='ctx'>  *</div><div class='ctx'>  * @optc: timing_generator instance.</div><div class='add'>+ * @idx: index of crc engine to get CRC from</div><div class='ctx'>  * @r_cr: 16-bit primary CRC signature for red data.</div><div class='ctx'>  * @g_y: 16-bit primary CRC signature for green data.</div><div class='ctx'>  * @b_cb: 16-bit primary CRC signature for blue data.</div><div class='hunk'>@@ -1512,7 +1557,7 @@ bool optc1_configure_crc(struct timing_generator *optc,</div><div class='ctx'>  * If CRC is disabled, return false; otherwise, return true, and the CRC</div><div class='ctx'>  * results in the parameters.</div><div class='ctx'>  */</div><div class='del'>-bool optc1_get_crc(struct timing_generator *optc,</div><div class='add'>+bool optc1_get_crc(struct timing_generator *optc, uint8_t idx,</div><div class='ctx'> 		   uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t field = 0;</div><div class='hunk'>@@ -1524,18 +1569,55 @@ bool optc1_get_crc(struct timing_generator *optc,</div><div class='ctx'> 	if (!field)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	/* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */</div><div class='del'>-	REG_GET_2(OTG_CRC0_DATA_RG,</div><div class='del'>-		  CRC0_R_CR, r_cr,</div><div class='del'>-		  CRC0_G_Y, g_y);</div><div class='add'>+	switch (idx) {</div><div class='add'>+	case 0:</div><div class='add'>+		/* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */</div><div class='add'>+		REG_GET_2(OTG_CRC0_DATA_RG,</div><div class='add'>+			  CRC0_R_CR, r_cr,</div><div class='add'>+			  CRC0_G_Y, g_y);</div><div class='ctx'> </div><div class='del'>-	/* OTG_CRC0_DATA_B has the CRC16 results for the blue component */</div><div class='del'>-	REG_GET(OTG_CRC0_DATA_B,</div><div class='del'>-		CRC0_B_CB, b_cb);</div><div class='add'>+		/* OTG_CRC0_DATA_B has the CRC16 results for the blue component */</div><div class='add'>+		REG_GET(OTG_CRC0_DATA_B,</div><div class='add'>+			CRC0_B_CB, b_cb);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		/* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */</div><div class='add'>+		REG_GET_2(OTG_CRC1_DATA_RG,</div><div class='add'>+			  CRC1_R_CR, r_cr,</div><div class='add'>+			  CRC1_G_Y, g_y);</div><div class='add'>+</div><div class='add'>+		/* OTG_CRC1_DATA_B has the CRC16 results for the blue component */</div><div class='add'>+		REG_GET(OTG_CRC1_DATA_B,</div><div class='add'>+			CRC1_B_CB, b_cb);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* "Container" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:</div><div class='add'>+ *</div><div class='add'>+ * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as</div><div class='add'>+ *   container rate.</div><div class='add'>+ *</div><div class='add'>+ * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be</div><div class='add'>+ *   halved to maintain the correct pixel rate.</div><div class='add'>+ *</div><div class='add'>+ * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied</div><div class='add'>+ *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing)</div><div class='add'>+{</div><div class='add'>+	bool two_pix = timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR420;</div><div class='add'>+</div><div class='add'>+	two_pix = two_pix || (timing-&gt;flags.DSC &amp;&amp; timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422</div><div class='add'>+			&amp;&amp; !timing-&gt;dsc_cfg.ycbcr422_simple);</div><div class='add'>+	return two_pix;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct timing_generator_funcs dcn10_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='hunk'>@@ -1582,6 +1664,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {</div><div class='ctx'> 		.program_manual_trigger = optc1_program_manual_trigger,</div><div class='ctx'> 		.setup_manual_trigger = optc1_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.read_otg_state = optc1_read_otg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn10_timing_generator_init(struct optc *optc1)</div><div class='hunk'>@@ -1597,25 +1681,3 @@ void dcn10_timing_generator_init(struct optc *optc1)</div><div class='ctx'> 	optc1-&gt;min_h_sync_width = 4;</div><div class='ctx'> 	optc1-&gt;min_v_sync_width = 1;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-/* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:</div><div class='del'>- *</div><div class='del'>- * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as</div><div class='del'>- *   containter rate.</div><div class='del'>- *</div><div class='del'>- * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be</div><div class='del'>- *   halved to maintain the correct pixel rate.</div><div class='del'>- *</div><div class='del'>- * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied</div><div class='del'>- *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	bool two_pix = timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR420;</div><div class='del'>-</div><div class='del'>-	two_pix = two_pix || (timing-&gt;flags.DSC &amp;&amp; timing-&gt;pixel_encoding == PIXEL_ENCODING_YCBCR422</div><div class='del'>-			&amp;&amp; !timing-&gt;dsc_cfg.ycbcr422_simple);</div><div class='del'>-	return two_pix;</div><div class='del'>-}</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h<br/>index 6c2e84d3967f..803bcc25601c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h</a></div><div class='hunk'>@@ -86,6 +86,12 @@</div><div class='ctx'> 	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\</div><div class='ctx'> 	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\</div><div class='ctx'> 	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_CRC1_DATA_RG, OTG, inst),\</div><div class='add'>+	SRI(OTG_CRC1_DATA_B, OTG, inst),\</div><div class='add'>+	SRI(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst),\</div><div class='ctx'> 	SR(GSL_SOURCE_SELECT),\</div><div class='ctx'> 	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\</div><div class='ctx'> 	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)</div><div class='hunk'>@@ -98,106 +104,151 @@</div><div class='ctx'> 	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> </div><div class='add'>+#define OPTC_REG_VARIABLE_LIST_DCN \</div><div class='add'>+	uint32_t OTG_GLOBAL_CONTROL1; \</div><div class='add'>+	uint32_t OTG_GLOBAL_CONTROL2; \</div><div class='add'>+	uint32_t OTG_VERT_SYNC_CONTROL; \</div><div class='add'>+	uint32_t OTG_MASTER_UPDATE_MODE; \</div><div class='add'>+	uint32_t OTG_GSL_CONTROL; \</div><div class='add'>+	uint32_t OTG_VSTARTUP_PARAM; \</div><div class='add'>+	uint32_t OTG_VUPDATE_PARAM; \</div><div class='add'>+	uint32_t OTG_VREADY_PARAM; \</div><div class='add'>+	uint32_t OTG_BLANK_CONTROL; \</div><div class='add'>+	uint32_t OTG_MASTER_UPDATE_LOCK; \</div><div class='add'>+	uint32_t OTG_GLOBAL_CONTROL0; \</div><div class='add'>+	uint32_t OTG_DOUBLE_BUFFER_CONTROL; \</div><div class='add'>+	uint32_t OTG_H_TOTAL; \</div><div class='add'>+	uint32_t OTG_H_BLANK_START_END; \</div><div class='add'>+	uint32_t OTG_H_SYNC_A; \</div><div class='add'>+	uint32_t OTG_H_SYNC_A_CNTL; \</div><div class='add'>+	uint32_t OTG_H_TIMING_CNTL; \</div><div class='add'>+	uint32_t OTG_V_TOTAL; \</div><div class='add'>+	uint32_t OTG_V_BLANK_START_END; \</div><div class='add'>+	uint32_t OTG_V_SYNC_A; \</div><div class='add'>+	uint32_t OTG_V_SYNC_A_CNTL; \</div><div class='add'>+	uint32_t OTG_INTERLACE_CONTROL; \</div><div class='add'>+	uint32_t OTG_CONTROL; \</div><div class='add'>+	uint32_t OTG_STEREO_CONTROL; \</div><div class='add'>+	uint32_t OTG_3D_STRUCTURE_CONTROL; \</div><div class='add'>+	uint32_t OTG_STEREO_STATUS; \</div><div class='add'>+	uint32_t OTG_V_TOTAL_MAX; \</div><div class='add'>+	uint32_t OTG_V_TOTAL_MID; \</div><div class='add'>+	uint32_t OTG_V_TOTAL_MIN; \</div><div class='add'>+	uint32_t OTG_V_TOTAL_CONTROL; \</div><div class='add'>+	uint32_t OTG_V_COUNT_STOP_CONTROL; \</div><div class='add'>+	uint32_t OTG_V_COUNT_STOP_CONTROL2; \</div><div class='add'>+	uint32_t OTG_TRIGA_CNTL; \</div><div class='add'>+	uint32_t OTG_TRIGA_MANUAL_TRIG; \</div><div class='add'>+	uint32_t OTG_MANUAL_FLOW_CONTROL; \</div><div class='add'>+	uint32_t OTG_FORCE_COUNT_NOW_CNTL; \</div><div class='add'>+	uint32_t OTG_STATIC_SCREEN_CONTROL; \</div><div class='add'>+	uint32_t OTG_STATUS_FRAME_COUNT; \</div><div class='add'>+	uint32_t OTG_STATUS; \</div><div class='add'>+	uint32_t OTG_STATUS_POSITION; \</div><div class='add'>+	uint32_t OTG_NOM_VERT_POSITION; \</div><div class='add'>+	uint32_t OTG_BLACK_COLOR; \</div><div class='add'>+	uint32_t OTG_TEST_PATTERN_PARAMETERS; \</div><div class='add'>+	uint32_t OTG_TEST_PATTERN_CONTROL; \</div><div class='add'>+	uint32_t OTG_TEST_PATTERN_COLOR; \</div><div class='add'>+	uint32_t OTG_CLOCK_CONTROL; \</div><div class='add'>+	uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; \</div><div class='add'>+	uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; \</div><div class='add'>+	uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; \</div><div class='add'>+	uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; \</div><div class='add'>+	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; \</div><div class='add'>+	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; \</div><div class='add'>+	uint32_t OPTC_INPUT_CLOCK_CONTROL; \</div><div class='add'>+	uint32_t OPTC_DATA_SOURCE_SELECT; \</div><div class='add'>+	uint32_t OPTC_MEMORY_CONFIG; \</div><div class='add'>+	uint32_t OPTC_INPUT_GLOBAL_CONTROL; \</div><div class='add'>+	uint32_t CONTROL; \</div><div class='add'>+	uint32_t OTG_GSL_WINDOW_X; \</div><div class='add'>+	uint32_t OTG_GSL_WINDOW_Y; \</div><div class='add'>+	uint32_t OTG_VUPDATE_KEEPOUT; \</div><div class='add'>+	uint32_t OTG_CRC_CNTL; \</div><div class='add'>+	uint32_t OTG_CRC_CNTL2; \</div><div class='add'>+	uint32_t OTG_CRC0_DATA_RG; \</div><div class='add'>+	uint32_t OTG_CRC0_DATA_B; \</div><div class='add'>+	uint32_t OTG_CRC1_DATA_B; \</div><div class='add'>+	uint32_t OTG_CRC2_DATA_B; \</div><div class='add'>+	uint32_t OTG_CRC3_DATA_B; \</div><div class='add'>+	uint32_t OTG_CRC1_DATA_RG; \</div><div class='add'>+	uint32_t OTG_CRC2_DATA_RG; \</div><div class='add'>+	uint32_t OTG_CRC3_DATA_RG; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWA_X_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWB_X_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWA_X_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWB_X_CONTROL; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; \</div><div class='add'>+	uint32_t GSL_SOURCE_SELECT; \</div><div class='add'>+	uint32_t DWB_SOURCE_SELECT; \</div><div class='add'>+	uint32_t OTG_DSC_START_POSITION; \</div><div class='add'>+	uint32_t OPTC_DATA_FORMAT_CONTROL; \</div><div class='add'>+	uint32_t OPTC_BYTES_PER_PIXEL; \</div><div class='add'>+	uint32_t OPTC_WIDTH_CONTROL; \</div><div class='add'>+	uint32_t OTG_DRR_CONTROL; \</div><div class='add'>+	uint32_t OTG_BLANK_DATA_COLOR; \</div><div class='add'>+	uint32_t OTG_BLANK_DATA_COLOR_EXT; \</div><div class='add'>+	uint32_t OTG_DRR_TRIGGER_WINDOW; \</div><div class='add'>+	uint32_t OTG_M_CONST_DTO0; \</div><div class='add'>+	uint32_t OTG_M_CONST_DTO1; \</div><div class='add'>+	uint32_t OTG_DRR_V_TOTAL_CHANGE; \</div><div class='add'>+	uint32_t OTG_GLOBAL_CONTROL4; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; \</div><div class='add'>+	uint32_t OPTC_CLOCK_CONTROL; \</div><div class='add'>+	uint32_t OPTC_WIDTH_CONTROL2; \</div><div class='add'>+	uint32_t OTG_PSTATE_REGISTER; \</div><div class='add'>+	uint32_t OTG_PIPE_UPDATE_STATUS; \</div><div class='add'>+	uint32_t INTERRUPT_DEST; \</div><div class='add'>+	uint32_t OPTC_INPUT_SPARE_REGISTER; \</div><div class='add'>+	uint32_t OPTC_RSMU_UNDERFLOW; \</div><div class='add'>+	uint32_t OPTC_UNDERFLOW_THRESHOLD; \</div><div class='add'>+	uint32_t OTG_COUNT_CONTROL; \</div><div class='add'>+	uint32_t OTG_COUNT_RESET; \</div><div class='add'>+	uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \</div><div class='add'>+	uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \</div><div class='add'>+	uint32_t OTG_DLPC_CONTROL; \</div><div class='add'>+	uint32_t OTG_DRR_CONTROL2; \</div><div class='add'>+	uint32_t OTG_DRR_TIMING_INT_STATUS; \</div><div class='add'>+	uint32_t OTG_GLOBAL_CONTROL3; \</div><div class='add'>+	uint32_t OTG_GLOBAL_SYNC_STATUS; \</div><div class='add'>+	uint32_t OTG_GSL_VSYNC_GAP; \</div><div class='add'>+	uint32_t OTG_INTERLACE_STATUS; \</div><div class='add'>+	uint32_t OTG_INTERRUPT_CONTROL; \</div><div class='add'>+	uint32_t OTG_LONG_VBLANK_STATUS; \</div><div class='add'>+	uint32_t OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; \</div><div class='add'>+	uint32_t OTG_MASTER_EN; \</div><div class='add'>+	uint32_t OTG_PIXEL_DATA_READBACK0; \</div><div class='add'>+	uint32_t OTG_PIXEL_DATA_READBACK1; \</div><div class='add'>+	uint32_t OTG_REQUEST_CONTROL; \</div><div class='add'>+	uint32_t OTG_SNAPSHOT_CONTROL; \</div><div class='add'>+	uint32_t OTG_SNAPSHOT_FRAME; \</div><div class='add'>+	uint32_t OTG_SNAPSHOT_POSITION; \</div><div class='add'>+	uint32_t OTG_SNAPSHOT_STATUS; \</div><div class='add'>+	uint32_t OTG_SPARE_REGISTER; \</div><div class='add'>+	uint32_t OTG_STATUS_HV_COUNT; \</div><div class='add'>+	uint32_t OTG_STATUS_VF_COUNT; \</div><div class='add'>+	uint32_t OTG_STEREO_FORCE_NEXT_EYE; \</div><div class='add'>+	uint32_t OTG_TRIG_MANUAL_CONTROL; \</div><div class='add'>+	uint32_t OTG_TRIGB_CNTL; \</div><div class='add'>+	uint32_t OTG_TRIGB_MANUAL_TRIG; \</div><div class='add'>+	uint32_t OTG_UPDATE_LOCK; \</div><div class='add'>+	uint32_t OTG_V_TOTAL_INT_STATUS; \</div><div class='add'>+	uint32_t OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> struct dcn_optc_registers {</div><div class='del'>-	uint32_t OTG_GLOBAL_CONTROL1;</div><div class='del'>-	uint32_t OTG_GLOBAL_CONTROL2;</div><div class='del'>-	uint32_t OTG_VERT_SYNC_CONTROL;</div><div class='del'>-	uint32_t OTG_MASTER_UPDATE_MODE;</div><div class='del'>-	uint32_t OTG_GSL_CONTROL;</div><div class='del'>-	uint32_t OTG_VSTARTUP_PARAM;</div><div class='del'>-	uint32_t OTG_VUPDATE_PARAM;</div><div class='del'>-	uint32_t OTG_VREADY_PARAM;</div><div class='del'>-	uint32_t OTG_BLANK_CONTROL;</div><div class='del'>-	uint32_t OTG_MASTER_UPDATE_LOCK;</div><div class='del'>-	uint32_t OTG_GLOBAL_CONTROL0;</div><div class='del'>-	uint32_t OTG_DOUBLE_BUFFER_CONTROL;</div><div class='del'>-	uint32_t OTG_H_TOTAL;</div><div class='del'>-	uint32_t OTG_H_BLANK_START_END;</div><div class='del'>-	uint32_t OTG_H_SYNC_A;</div><div class='del'>-	uint32_t OTG_H_SYNC_A_CNTL;</div><div class='del'>-	uint32_t OTG_H_TIMING_CNTL;</div><div class='del'>-	uint32_t OTG_V_TOTAL;</div><div class='del'>-	uint32_t OTG_V_BLANK_START_END;</div><div class='del'>-	uint32_t OTG_V_SYNC_A;</div><div class='del'>-	uint32_t OTG_V_SYNC_A_CNTL;</div><div class='del'>-	uint32_t OTG_INTERLACE_CONTROL;</div><div class='del'>-	uint32_t OTG_CONTROL;</div><div class='del'>-	uint32_t OTG_STEREO_CONTROL;</div><div class='del'>-	uint32_t OTG_3D_STRUCTURE_CONTROL;</div><div class='del'>-	uint32_t OTG_STEREO_STATUS;</div><div class='del'>-	uint32_t OTG_V_TOTAL_MAX;</div><div class='del'>-	uint32_t OTG_V_TOTAL_MID;</div><div class='del'>-	uint32_t OTG_V_TOTAL_MIN;</div><div class='del'>-	uint32_t OTG_V_TOTAL_CONTROL;</div><div class='del'>-	uint32_t OTG_TRIGA_CNTL;</div><div class='del'>-	uint32_t OTG_TRIGA_MANUAL_TRIG;</div><div class='del'>-	uint32_t OTG_MANUAL_FLOW_CONTROL;</div><div class='del'>-	uint32_t OTG_FORCE_COUNT_NOW_CNTL;</div><div class='del'>-	uint32_t OTG_STATIC_SCREEN_CONTROL;</div><div class='del'>-	uint32_t OTG_STATUS_FRAME_COUNT;</div><div class='del'>-	uint32_t OTG_STATUS;</div><div class='del'>-	uint32_t OTG_STATUS_POSITION;</div><div class='del'>-	uint32_t OTG_NOM_VERT_POSITION;</div><div class='del'>-	uint32_t OTG_BLACK_COLOR;</div><div class='del'>-	uint32_t OTG_TEST_PATTERN_PARAMETERS;</div><div class='del'>-	uint32_t OTG_TEST_PATTERN_CONTROL;</div><div class='del'>-	uint32_t OTG_TEST_PATTERN_COLOR;</div><div class='del'>-	uint32_t OTG_CLOCK_CONTROL;</div><div class='del'>-	uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;</div><div class='del'>-	uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;</div><div class='del'>-	uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL;</div><div class='del'>-	uint32_t OTG_VERTICAL_INTERRUPT1_POSITION;</div><div class='del'>-	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;</div><div class='del'>-	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;</div><div class='del'>-	uint32_t OPTC_INPUT_CLOCK_CONTROL;</div><div class='del'>-	uint32_t OPTC_DATA_SOURCE_SELECT;</div><div class='del'>-	uint32_t OPTC_MEMORY_CONFIG;</div><div class='del'>-	uint32_t OPTC_INPUT_GLOBAL_CONTROL;</div><div class='del'>-	uint32_t CONTROL;</div><div class='del'>-	uint32_t OTG_GSL_WINDOW_X;</div><div class='del'>-	uint32_t OTG_GSL_WINDOW_Y;</div><div class='del'>-	uint32_t OTG_VUPDATE_KEEPOUT;</div><div class='del'>-	uint32_t OTG_CRC_CNTL;</div><div class='del'>-	uint32_t OTG_CRC_CNTL2;</div><div class='del'>-	uint32_t OTG_CRC0_DATA_RG;</div><div class='del'>-	uint32_t OTG_CRC0_DATA_B;</div><div class='del'>-	uint32_t OTG_CRC1_DATA_B;</div><div class='del'>-	uint32_t OTG_CRC2_DATA_B;</div><div class='del'>-	uint32_t OTG_CRC3_DATA_B;</div><div class='del'>-	uint32_t OTG_CRC1_DATA_RG;</div><div class='del'>-	uint32_t OTG_CRC2_DATA_RG;</div><div class='del'>-	uint32_t OTG_CRC3_DATA_RG;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWA_X_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWB_X_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWA_X_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWA_Y_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWB_X_CONTROL;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWB_Y_CONTROL;</div><div class='del'>-	uint32_t GSL_SOURCE_SELECT;</div><div class='del'>-	uint32_t DWB_SOURCE_SELECT;</div><div class='del'>-	uint32_t OTG_DSC_START_POSITION;</div><div class='del'>-	uint32_t OPTC_DATA_FORMAT_CONTROL;</div><div class='del'>-	uint32_t OPTC_BYTES_PER_PIXEL;</div><div class='del'>-	uint32_t OPTC_WIDTH_CONTROL;</div><div class='del'>-	uint32_t OTG_DRR_CONTROL;</div><div class='del'>-	uint32_t OTG_BLANK_DATA_COLOR;</div><div class='del'>-	uint32_t OTG_BLANK_DATA_COLOR_EXT;</div><div class='del'>-	uint32_t OTG_DRR_TRIGGER_WINDOW;</div><div class='del'>-	uint32_t OTG_M_CONST_DTO0;</div><div class='del'>-	uint32_t OTG_M_CONST_DTO1;</div><div class='del'>-	uint32_t OTG_DRR_V_TOTAL_CHANGE;</div><div class='del'>-	uint32_t OTG_GLOBAL_CONTROL4;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK;</div><div class='del'>-	uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;</div><div class='del'>-	uint32_t OPTC_CLOCK_CONTROL;</div><div class='add'>+	OPTC_REG_VARIABLE_LIST_DCN;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\</div><div class='hunk'>@@ -310,6 +361,7 @@ struct dcn_optc_registers {</div><div class='ctx'> 	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC1_SELECT, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\</div><div class='hunk'>@@ -322,13 +374,22 @@ struct dcn_optc_registers {</div><div class='ctx'> 	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\</div><div class='ctx'> 	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\</div><div class='ctx'> 	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\</div><div class='ctx'> 	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\</div><div class='ctx'> 	TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\</div><div class='hunk'>@@ -479,6 +540,7 @@ struct dcn_optc_registers {</div><div class='ctx'> 	type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\</div><div class='ctx'> 	type OTG_CRC_CONT_EN;\</div><div class='ctx'> 	type OTG_CRC0_SELECT;\</div><div class='add'>+	type OTG_CRC1_SELECT;\</div><div class='ctx'> 	type OTG_CRC_EN;\</div><div class='ctx'> 	type CRC0_R_CR;\</div><div class='ctx'> 	type CRC0_G_Y;\</div><div class='hunk'>@@ -515,12 +577,15 @@ struct dcn_optc_registers {</div><div class='ctx'> 	type MANUAL_FLOW_CONTROL;\</div><div class='ctx'> 	type MANUAL_FLOW_CONTROL_SEL;</div><div class='ctx'> </div><div class='add'>+#define V_TOTAL_REGS(type)</div><div class='add'>+</div><div class='ctx'> #define TG_REG_FIELD_LIST(type) \</div><div class='ctx'> 	TG_REG_FIELD_LIST_DCN1_0(type)\</div><div class='ctx'> 	type OTG_V_SYNC_MODE;\</div><div class='ctx'> 	type OTG_DRR_TRIGGER_WINDOW_START_X;\</div><div class='ctx'> 	type OTG_DRR_TRIGGER_WINDOW_END_X;\</div><div class='ctx'> 	type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\</div><div class='add'>+	V_TOTAL_REGS(type)\</div><div class='ctx'> 	type OTG_OUT_MUX;\</div><div class='ctx'> 	type OTG_M_CONST_DTO_PHASE;\</div><div class='ctx'> 	type OTG_M_CONST_DTO_MODULO;\</div><div class='hunk'>@@ -558,12 +623,19 @@ struct dcn_optc_registers {</div><div class='ctx'> 	type OTG_CRC_DATA_FORMAT;\</div><div class='ctx'> 	type OTG_V_TOTAL_LAST_USED_BY_DRR;\</div><div class='ctx'> 	type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;\</div><div class='del'>-	type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;</div><div class='add'>+	type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;\</div><div class='add'>+	type OPTC_DOUBLE_BUFFER_PENDING;\</div><div class='add'>+</div><div class='add'>+#define TG_REG_FIELD_LIST_DCN2_0(type) \</div><div class='add'>+	type OTG_FLIP_PENDING;\</div><div class='add'>+	type OTG_DC_REG_UPDATE_PENDING;\</div><div class='add'>+	type OTG_CURSOR_UPDATE_PENDING;\</div><div class='add'>+	type OTG_VUPDATE_KEEPOUT_STATUS;\</div><div class='add'>+	type OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST;</div><div class='ctx'> </div><div class='ctx'> #define TG_REG_FIELD_LIST_DCN3_2(type) \</div><div class='ctx'> 	type OTG_H_TIMING_DIV_MODE_MANUAL;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> #define TG_REG_FIELD_LIST_DCN3_5(type) \</div><div class='ctx'> 	type OTG_CRC0_WINDOWA_X_START_READBACK;\</div><div class='ctx'> 	type OTG_CRC0_WINDOWA_X_END_READBACK;\</div><div class='hunk'>@@ -581,18 +653,32 @@ struct dcn_optc_registers {</div><div class='ctx'> 	type OTG_CRC1_WINDOWB_X_END_READBACK;\</div><div class='ctx'> 	type OTG_CRC1_WINDOWB_Y_START_READBACK;\</div><div class='ctx'> 	type OTG_CRC1_WINDOWB_Y_END_READBACK;\</div><div class='del'>-	type OPTC_FGCG_REP_DIS;</div><div class='add'>+	type OPTC_FGCG_REP_DIS;\</div><div class='add'>+	type OTG_V_COUNT_STOP;\</div><div class='add'>+	type OTG_V_COUNT_STOP_TIMER;</div><div class='add'>+</div><div class='add'>+#define TG_REG_FIELD_LIST_DCN401(type) \</div><div class='add'>+	type OPTC_SEGMENT_WIDTH_LAST;\</div><div class='add'>+	type OTG_PSTATE_KEEPOUT_START;\</div><div class='add'>+	type OTG_PSTATE_EXTEND;\</div><div class='add'>+	type OTG_UNBLANK;\</div><div class='add'>+	type OTG_PSTATE_ALLOW_WIDTH_MIN;</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> struct dcn_optc_shift {</div><div class='ctx'> 	TG_REG_FIELD_LIST(uint8_t)</div><div class='add'>+	TG_REG_FIELD_LIST_DCN2_0(uint8_t)</div><div class='ctx'> 	TG_REG_FIELD_LIST_DCN3_2(uint8_t)</div><div class='ctx'> 	TG_REG_FIELD_LIST_DCN3_5(uint8_t)</div><div class='add'>+	TG_REG_FIELD_LIST_DCN401(uint8_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dcn_optc_mask {</div><div class='ctx'> 	TG_REG_FIELD_LIST(uint32_t)</div><div class='add'>+	TG_REG_FIELD_LIST_DCN2_0(uint32_t)</div><div class='ctx'> 	TG_REG_FIELD_LIST_DCN3_2(uint32_t)</div><div class='ctx'> 	TG_REG_FIELD_LIST_DCN3_5(uint32_t)</div><div class='add'>+	TG_REG_FIELD_LIST_DCN401(uint32_t)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn10_timing_generator_init(struct optc *optc);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c<br/>index 58bdbd859bf9..e7a90a437fff 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c</a></div><div class='hunk'>@@ -158,13 +158,6 @@ void optc2_get_dsc_status(struct timing_generator *optc,</div><div class='ctx'> 		OPTC_DSC_MODE, dsc_mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-/*TEMP: Need to figure out inheritance model here.*/</div><div class='del'>-bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	return optc1_is_two_pixels_per_containter(timing);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void optc2_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 		const struct dc_crtc_timing *dc_crtc_timing)</div><div class='ctx'> {</div><div class='hunk'>@@ -177,7 +170,7 @@ void optc2_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 			OPTC_SEG1_SRC_SEL, 0xf);</div><div class='ctx'> 	REG_WRITE(OTG_H_TIMING_CNTL, 0);</div><div class='ctx'> </div><div class='del'>-	h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);</div><div class='add'>+	h_div_2 = optc-&gt;funcs-&gt;is_two_pixels_per_container(dc_crtc_timing);</div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='ctx'> 			OTG_H_TIMING_DIV_BY2, h_div_2);</div><div class='ctx'> 	REG_SET(OPTC_MEMORY_CONFIG, 0,</div><div class='hunk'>@@ -186,11 +179,9 @@ void optc2_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing)</div><div class='add'>+		int segment_width, int last_segment_width)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='del'>-	int mpcc_hactive = (timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right)</div><div class='del'>-			/ opp_cnt;</div><div class='ctx'> 	uint32_t memory_mask;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(opp_cnt == 2);</div><div class='hunk'>@@ -220,7 +211,7 @@ void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c</div><div class='ctx'> 			OPTC_SEG1_SRC_SEL, opp_id[1]);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='del'>-			OPTC_SEGMENT_WIDTH, mpcc_hactive);</div><div class='add'>+			OPTC_SEGMENT_WIDTH, segment_width);</div><div class='ctx'> </div><div class='ctx'> 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);</div><div class='ctx'> 	optc1-&gt;opp_count = opp_cnt;</div><div class='hunk'>@@ -511,7 +502,7 @@ void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *ref</div><div class='ctx'> 	REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn20_tg_funcs = {</div><div class='add'>+static const struct timing_generator_funcs dcn20_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -570,6 +561,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {</div><div class='ctx'> 		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='ctx'> 		.align_vblanks = optc2_align_vblanks,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.read_otg_state = optc1_read_otg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn20_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h<br/>index c2e03ced392e..928e110b95fb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h</a></div><div class='hunk'>@@ -43,7 +43,8 @@</div><div class='ctx'> 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\</div><div class='ctx'> 	SR(DWB_SOURCE_SELECT),\</div><div class='ctx'> 	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \</div><div class='del'>-	SRI(OTG_DRR_CONTROL, OTG, inst)</div><div class='add'>+	SRI(OTG_DRR_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\</div><div class='ctx'> 	TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\</div><div class='hunk'>@@ -53,6 +54,10 @@</div><div class='ctx'> 	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \</div><div class='ctx'> 	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\</div><div class='hunk'>@@ -105,7 +110,7 @@ void optc2_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 		const struct dc_crtc_timing *dc_crtc_timing);</div><div class='ctx'> </div><div class='ctx'> void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing);</div><div class='add'>+		int segment_width, int last_segment_width);</div><div class='ctx'> </div><div class='ctx'> void optc2_get_optc_source(struct timing_generator *optc,</div><div class='ctx'> 		uint32_t *num_of_src_opp,</div><div class='hunk'>@@ -118,7 +123,6 @@ void optc2_lock_doublebuffer_disable(struct timing_generator *optc);</div><div class='ctx'> void optc2_lock_doublebuffer_enable(struct timing_generator *optc);</div><div class='ctx'> void optc2_setup_manual_trigger(struct timing_generator *optc);</div><div class='ctx'> void optc2_program_manual_trigger(struct timing_generator *optc);</div><div class='del'>-bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);</div><div class='ctx'> bool optc2_configure_crc(struct timing_generator *optc,</div><div class='ctx'> 			  const struct crc_params *params);</div><div class='ctx'> #endif /* __DC_OPTC_DCN20_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c<br/>index 70fcbec03fb6..772a8bfb949c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c</a></div><div class='hunk'>@@ -38,12 +38,6 @@</div><div class='ctx'> #define FN(reg_name, field_name) \</div><div class='ctx'> 	optc1-&gt;tg_shift-&gt;field_name, optc1-&gt;tg_mask-&gt;field_name</div><div class='ctx'> </div><div class='del'>-/*TEMP: Need to figure out inheritance model here.*/</div><div class='del'>-bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)</div><div class='del'>-{</div><div class='del'>-	return optc1_is_two_pixels_per_containter(timing);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void optc201_triplebuffer_lock(struct timing_generator *optc)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='hunk'>@@ -135,7 +129,7 @@ static void optc201_get_optc_source(struct timing_generator *optc,</div><div class='ctx'> 	*num_of_src_opp = 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn201_tg_funcs = {</div><div class='add'>+static const struct timing_generator_funcs dcn201_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc201_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -185,6 +179,8 @@ static struct timing_generator_funcs dcn201_tg_funcs = {</div><div class='ctx'> 		.program_manual_trigger = optc2_program_manual_trigger,</div><div class='ctx'> 		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.read_otg_state = optc1_read_otg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn201_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h<br/>index e9545b73513a..a9b281abfd44 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h</a></div><div class='hunk'>@@ -68,7 +68,4 @@</div><div class='ctx'> 	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)</div><div class='ctx'> </div><div class='ctx'> void dcn201_timing_generator_init(struct optc *optc);</div><div class='del'>-</div><div class='del'>-bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);</div><div class='del'>-</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c<br/>index b97bdb868a0e..ee4665aa49e9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c</a></div><div class='hunk'>@@ -206,7 +206,7 @@ void optc3_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 			OPTC_SEG3_SRC_SEL, 0xf</div><div class='ctx'> 			);</div><div class='ctx'> </div><div class='del'>-	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);</div><div class='add'>+	h_div = optc-&gt;funcs-&gt;is_two_pixels_per_container(dc_crtc_timing);</div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='ctx'> 			OTG_H_TIMING_DIV_MODE, h_div);</div><div class='ctx'> </div><div class='hunk'>@@ -216,11 +216,9 @@ void optc3_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing)</div><div class='add'>+		int segment_width, int last_segment_width)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='del'>-	int mpcc_hactive = (timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right)</div><div class='del'>-			/ opp_cnt;</div><div class='ctx'> 	uint32_t memory_mask = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic</div><div class='hunk'>@@ -267,12 +265,54 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='del'>-			OPTC_SEGMENT_WIDTH, mpcc_hactive);</div><div class='add'>+			OPTC_SEGMENT_WIDTH, segment_width);</div><div class='ctx'> </div><div class='ctx'> 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);</div><div class='ctx'> 	optc1-&gt;opp_count = opp_cnt;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* OTG status register that indicates OPTC update is pending */</div><div class='add'>+bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	uint32_t update_pending = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET(OPTC_INPUT_GLOBAL_CONTROL,</div><div class='add'>+			OPTC_DOUBLE_BUFFER_PENDING,</div><div class='add'>+			&amp;update_pending);</div><div class='add'>+</div><div class='add'>+	return (update_pending == 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* OTG status register that indicates OTG update is pending */</div><div class='add'>+bool optc3_get_otg_update_pending(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	uint32_t update_pending = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_DOUBLE_BUFFER_CONTROL,</div><div class='add'>+			OTG_UPDATE_PENDING,</div><div class='add'>+			&amp;update_pending);</div><div class='add'>+</div><div class='add'>+	return (update_pending == 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* OTG status register that indicates surface update is pending */</div><div class='add'>+bool optc3_get_pipe_update_pending(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	uint32_t flip_pending = 0;</div><div class='add'>+	uint32_t dc_update_pending = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET_2(OTG_PIPE_UPDATE_STATUS,</div><div class='add'>+			OTG_FLIP_PENDING,</div><div class='add'>+			&amp;flip_pending,</div><div class='add'>+			OTG_DC_REG_UPDATE_PENDING,</div><div class='add'>+			&amp;dc_update_pending);</div><div class='add'>+</div><div class='add'>+	return (flip_pending == 1 || dc_update_pending == 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * optc3_set_timing_double_buffer() - DRR double buffering control</div><div class='ctx'>  *</div><div class='hunk'>@@ -317,7 +357,7 @@ void optc3_tg_init(struct timing_generator *optc)</div><div class='ctx'> 	optc1_clear_optc_underflow(optc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn30_tg_funcs = {</div><div class='add'>+static const struct timing_generator_funcs dcn30_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -376,6 +416,11 @@ static struct timing_generator_funcs dcn30_tg_funcs = {</div><div class='ctx'> 		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='ctx'> 		.wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,</div><div class='add'>+		.get_otg_double_buffer_pending = optc3_get_otg_update_pending,</div><div class='add'>+		.get_pipe_update_pending = optc3_get_pipe_update_pending,</div><div class='add'>+		.read_otg_state = optc1_read_otg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn30_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h<br/>index d3a056c12b0d..e2303f9eaf13 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h</a></div><div class='hunk'>@@ -109,7 +109,8 @@</div><div class='ctx'> 	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\</div><div class='ctx'> 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\</div><div class='ctx'> 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\</div><div class='del'>-	SR(DWB_SOURCE_SELECT)</div><div class='add'>+	SR(DWB_SOURCE_SELECT),\</div><div class='add'>+	SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> #define DCN30_VTOTAL_REGS_SF(mask_sh)</div><div class='ctx'> </div><div class='hunk'>@@ -209,6 +210,7 @@</div><div class='ctx'> 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\</div><div class='ctx'> 	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\</div><div class='ctx'> 	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\</div><div class='ctx'> 	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\</div><div class='ctx'> 	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\</div><div class='ctx'> 	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\</div><div class='hunk'>@@ -319,7 +321,11 @@</div><div class='ctx'> 	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\</div><div class='del'>-	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh)</div><div class='add'>+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='ctx'> </div><div class='ctx'> void dcn30_timing_generator_init(struct optc *optc1);</div><div class='ctx'> </div><div class='hunk'>@@ -352,8 +358,11 @@ void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable);</div><div class='ctx'> void optc3_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 		const struct dc_crtc_timing *dc_crtc_timing);</div><div class='ctx'> void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing);</div><div class='add'>+		int segment_width, int last_segment_width);</div><div class='ctx'> void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc);</div><div class='ctx'> void optc3_tg_init(struct timing_generator *optc);</div><div class='ctx'> void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);</div><div class='add'>+bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc);</div><div class='add'>+bool optc3_get_otg_update_pending(struct timing_generator *optc);</div><div class='add'>+bool optc3_get_pipe_update_pending(struct timing_generator *optc);</div><div class='ctx'> #endif /* __DC_OPTC_DCN30_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c<br/>index b3cfcb887905..38f85bc2681a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c</a></div><div class='hunk'>@@ -109,7 +109,7 @@ void optc301_setup_manual_trigger(struct timing_generator *optc)</div><div class='ctx'> 			OTG_TRIGA_CLEAR, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn30_tg_funcs = {</div><div class='add'>+static const struct timing_generator_funcs dcn30_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -168,6 +168,11 @@ static struct timing_generator_funcs dcn30_tg_funcs = {</div><div class='ctx'> 		.setup_manual_trigger = optc301_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='ctx'> 		.wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,</div><div class='add'>+		.get_otg_double_buffer_pending = optc3_get_otg_update_pending,</div><div class='add'>+		.get_pipe_update_pending = optc3_get_pipe_update_pending,</div><div class='add'>+		.read_otg_state = optc1_read_otg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn301_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c<br/>index 63a677c8ee27..c6417538090f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c</a></div><div class='hunk'>@@ -41,13 +41,11 @@</div><div class='ctx'> 	optc1-&gt;tg_shift-&gt;field_name, optc1-&gt;tg_mask-&gt;field_name</div><div class='ctx'> </div><div class='ctx'> static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing)</div><div class='add'>+		int segment_width, int last_segment_width)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='del'>-	int mpcc_hactive = (timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right)</div><div class='del'>-			/ opp_cnt;</div><div class='ctx'> 	uint32_t memory_mask = 0;</div><div class='del'>-	int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;</div><div class='add'>+	int mem_count_per_opp = (segment_width + 2559) / 2560;</div><div class='ctx'> </div><div class='ctx'> 	/* Assume less than 6 pipes */</div><div class='ctx'> 	if (opp_cnt == 4) {</div><div class='hunk'>@@ -85,7 +83,7 @@ static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, i</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='del'>-			OPTC_SEGMENT_WIDTH, mpcc_hactive);</div><div class='add'>+			OPTC_SEGMENT_WIDTH, segment_width);</div><div class='ctx'> </div><div class='ctx'> 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);</div><div class='ctx'> 	optc1-&gt;opp_count = opp_cnt;</div><div class='hunk'>@@ -123,6 +121,17 @@ static bool optc31_enable_crtc(struct timing_generator *optc)</div><div class='ctx'> static bool optc31_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OPTC_MEMORY_CONFIG,</div><div class='add'>+			OPTC_MEM_SEL, 0);</div><div class='add'>+</div><div class='ctx'> 	/* disable otg request until end of the first line</div><div class='ctx'> 	 * in the vertical blank region</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -140,7 +149,9 @@ static bool optc31_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='del'>-</div><div class='add'>+/*</div><div class='add'>+ * Immediate_Disable_Crtc - this is to temp disable Timing generator without reset ODM.</div><div class='add'>+ */</div><div class='ctx'> bool optc31_immediate_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='hunk'>@@ -153,10 +164,12 @@ bool optc31_immediate_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> 			VTG0_ENABLE, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* CRTC disabled, so disable  clock. */</div><div class='del'>-	REG_WAIT(OTG_CLOCK_CONTROL,</div><div class='add'>+	if (optc-&gt;ctx-&gt;dce_environment != DCE_ENV_DIAG)</div><div class='add'>+		REG_WAIT(OTG_CLOCK_CONTROL,</div><div class='ctx'> 			OTG_BUSY, 0,</div><div class='ctx'> 			1, 100000);</div><div class='ctx'> </div><div class='add'>+</div><div class='ctx'> 	/* clear the false state */</div><div class='ctx'> 	optc1_clear_optc_underflow(optc);</div><div class='ctx'> </div><div class='hunk'>@@ -232,7 +245,207 @@ void optc3_init_odm(struct timing_generator *optc)</div><div class='ctx'> 	optc1-&gt;opp_count = 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn31_tg_funcs = {</div><div class='add'>+void optc31_read_otg_state(struct timing_generator *optc,</div><div class='add'>+		struct dcn_otg_state *s)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_CONTROL,</div><div class='add'>+			OTG_MASTER_EN, &amp;s-&gt;otg_enabled);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(OTG_V_BLANK_START_END,</div><div class='add'>+			OTG_V_BLANK_START, &amp;s-&gt;v_blank_start,</div><div class='add'>+			OTG_V_BLANK_END, &amp;s-&gt;v_blank_end);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_V_SYNC_A_CNTL,</div><div class='add'>+			OTG_V_SYNC_A_POL, &amp;s-&gt;v_sync_a_pol);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_V_TOTAL,</div><div class='add'>+			OTG_V_TOTAL, &amp;s-&gt;v_total);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_V_TOTAL_MAX,</div><div class='add'>+			OTG_V_TOTAL_MAX, &amp;s-&gt;v_total_max);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_V_TOTAL_MIN,</div><div class='add'>+			OTG_V_TOTAL_MIN, &amp;s-&gt;v_total_min);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_V_TOTAL_CONTROL,</div><div class='add'>+			OTG_V_TOTAL_MAX_SEL, &amp;s-&gt;v_total_max_sel);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_V_TOTAL_CONTROL,</div><div class='add'>+			OTG_V_TOTAL_MIN_SEL, &amp;s-&gt;v_total_min_sel);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(OTG_V_SYNC_A,</div><div class='add'>+			OTG_V_SYNC_A_START, &amp;s-&gt;v_sync_a_start,</div><div class='add'>+			OTG_V_SYNC_A_END, &amp;s-&gt;v_sync_a_end);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(OTG_H_BLANK_START_END,</div><div class='add'>+			OTG_H_BLANK_START, &amp;s-&gt;h_blank_start,</div><div class='add'>+			OTG_H_BLANK_END, &amp;s-&gt;h_blank_end);</div><div class='add'>+</div><div class='add'>+	REG_GET_2(OTG_H_SYNC_A,</div><div class='add'>+			OTG_H_SYNC_A_START, &amp;s-&gt;h_sync_a_start,</div><div class='add'>+			OTG_H_SYNC_A_END, &amp;s-&gt;h_sync_a_end);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_H_SYNC_A_CNTL,</div><div class='add'>+			OTG_H_SYNC_A_POL, &amp;s-&gt;h_sync_a_pol);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_H_TOTAL,</div><div class='add'>+			OTG_H_TOTAL, &amp;s-&gt;h_total);</div><div class='add'>+</div><div class='add'>+	REG_GET(OPTC_INPUT_GLOBAL_CONTROL,</div><div class='add'>+			OPTC_UNDERFLOW_OCCURRED_STATUS, &amp;s-&gt;underflow_occurred_status);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,</div><div class='add'>+			OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &amp;s-&gt;vertical_interrupt1_en);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,</div><div class='add'>+				OTG_VERTICAL_INTERRUPT1_LINE_START, &amp;s-&gt;vertical_interrupt1_line);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,</div><div class='add'>+			OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &amp;s-&gt;vertical_interrupt2_en);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,</div><div class='add'>+			OTG_VERTICAL_INTERRUPT2_LINE_START, &amp;s-&gt;vertical_interrupt2_line);</div><div class='add'>+</div><div class='add'>+	REG_GET(INTERRUPT_DEST,</div><div class='add'>+			OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, &amp;s-&gt;vertical_interrupt2_dest);</div><div class='add'>+</div><div class='add'>+	s-&gt;otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);</div><div class='add'>+	s-&gt;otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	optc_reg_state-&gt;optc_bytes_per_pixel = REG_READ(OPTC_BYTES_PER_PIXEL);</div><div class='add'>+	optc_reg_state-&gt;optc_data_format_control = REG_READ(OPTC_DATA_FORMAT_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;optc_data_source_select = REG_READ(OPTC_DATA_SOURCE_SELECT);</div><div class='add'>+	optc_reg_state-&gt;optc_input_clock_control = REG_READ(OPTC_INPUT_CLOCK_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;optc_input_global_control = REG_READ(OPTC_INPUT_GLOBAL_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;optc_input_spare_register = REG_READ(OPTC_INPUT_SPARE_REGISTER);</div><div class='add'>+	optc_reg_state-&gt;optc_memory_config = REG_READ(OPTC_MEMORY_CONFIG);</div><div class='add'>+	optc_reg_state-&gt;optc_rsmu_underflow = REG_READ(OPTC_RSMU_UNDERFLOW);</div><div class='add'>+	optc_reg_state-&gt;optc_underflow_threshold = REG_READ(OPTC_UNDERFLOW_THRESHOLD);</div><div class='add'>+	optc_reg_state-&gt;optc_width_control = REG_READ(OPTC_WIDTH_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_3d_structure_control = REG_READ(OTG_3D_STRUCTURE_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_clock_control = REG_READ(OTG_CLOCK_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_control = REG_READ(OTG_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_count_control = REG_READ(OTG_COUNT_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_count_reset = REG_READ(OTG_COUNT_RESET);</div><div class='add'>+	optc_reg_state-&gt;otg_crc_cntl = REG_READ(OTG_CRC_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc_sig_blue_control_mask = REG_READ(OTG_CRC_SIG_BLUE_CONTROL_MASK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc_sig_red_green_mask = REG_READ(OTG_CRC_SIG_RED_GREEN_MASK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_data_b = REG_READ(OTG_CRC0_DATA_B);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_data_rg = REG_READ(OTG_CRC0_DATA_RG);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowa_x_control = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowa_x_control_readback = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowa_y_control = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowa_y_control_readback = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowb_x_control = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowb_x_control_readback = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowb_y_control = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc0_windowb_y_control_readback = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_data_b = REG_READ(OTG_CRC1_DATA_B);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_data_rg = REG_READ(OTG_CRC1_DATA_RG);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowa_x_control = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowa_x_control_readback = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowa_y_control = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowa_y_control_readback = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowb_x_control = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowb_x_control_readback = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowb_y_control = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_crc1_windowb_y_control_readback = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK);</div><div class='add'>+	optc_reg_state-&gt;otg_crc2_data_b = REG_READ(OTG_CRC2_DATA_B);</div><div class='add'>+	optc_reg_state-&gt;otg_crc2_data_rg = REG_READ(OTG_CRC2_DATA_RG);</div><div class='add'>+	optc_reg_state-&gt;otg_crc3_data_b = REG_READ(OTG_CRC3_DATA_B);</div><div class='add'>+	optc_reg_state-&gt;otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG);</div><div class='add'>+	optc_reg_state-&gt;otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2);</div><div class='add'>+	optc_reg_state-&gt;otg_drr_control = REG_READ(OTG_DRR_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW);</div><div class='add'>+	optc_reg_state-&gt;otg_drr_v_total_change = REG_READ(OTG_DRR_V_TOTAL_CHANGE);</div><div class='add'>+	optc_reg_state-&gt;otg_dsc_start_position = REG_READ(OTG_DSC_START_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_force_count_now_cntl = REG_READ(OTG_FORCE_COUNT_NOW_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_global_control0 = REG_READ(OTG_GLOBAL_CONTROL0);</div><div class='add'>+	optc_reg_state-&gt;otg_global_control1 = REG_READ(OTG_GLOBAL_CONTROL1);</div><div class='add'>+	optc_reg_state-&gt;otg_global_control2 = REG_READ(OTG_GLOBAL_CONTROL2);</div><div class='add'>+	optc_reg_state-&gt;otg_global_control3 = REG_READ(OTG_GLOBAL_CONTROL3);</div><div class='add'>+	optc_reg_state-&gt;otg_global_control4 = REG_READ(OTG_GLOBAL_CONTROL4);</div><div class='add'>+	optc_reg_state-&gt;otg_global_sync_status = REG_READ(OTG_GLOBAL_SYNC_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_gsl_control = REG_READ(OTG_GSL_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_gsl_vsync_gap = REG_READ(OTG_GSL_VSYNC_GAP);</div><div class='add'>+	optc_reg_state-&gt;otg_gsl_window_x = REG_READ(OTG_GSL_WINDOW_X);</div><div class='add'>+	optc_reg_state-&gt;otg_gsl_window_y = REG_READ(OTG_GSL_WINDOW_Y);</div><div class='add'>+	optc_reg_state-&gt;otg_h_blank_start_end = REG_READ(OTG_H_BLANK_START_END);</div><div class='add'>+	optc_reg_state-&gt;otg_h_sync_a = REG_READ(OTG_H_SYNC_A);</div><div class='add'>+	optc_reg_state-&gt;otg_h_sync_a_cntl = REG_READ(OTG_H_SYNC_A_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_h_timing_cntl = REG_READ(OTG_H_TIMING_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_h_total = REG_READ(OTG_H_TOTAL);</div><div class='add'>+	optc_reg_state-&gt;otg_interlace_control = REG_READ(OTG_INTERLACE_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_interlace_status = REG_READ(OTG_INTERLACE_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_interrupt_control = REG_READ(OTG_INTERRUPT_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_long_vblank_status = REG_READ(OTG_LONG_VBLANK_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_m_const_dto0 = REG_READ(OTG_M_CONST_DTO0);</div><div class='add'>+	optc_reg_state-&gt;otg_m_const_dto1 = REG_READ(OTG_M_CONST_DTO1);</div><div class='add'>+	optc_reg_state-&gt;otg_manual_force_vsync_next_line = REG_READ(OTG_MANUAL_FORCE_VSYNC_NEXT_LINE);</div><div class='add'>+	optc_reg_state-&gt;otg_master_en = REG_READ(OTG_MASTER_EN);</div><div class='add'>+	optc_reg_state-&gt;otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);</div><div class='add'>+	optc_reg_state-&gt;otg_master_update_mode = REG_READ(OTG_MASTER_UPDATE_MODE);</div><div class='add'>+	optc_reg_state-&gt;otg_nom_vert_position = REG_READ(OTG_NOM_VERT_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_pipe_update_status = REG_READ(OTG_PIPE_UPDATE_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_pixel_data_readback0 = REG_READ(OTG_PIXEL_DATA_READBACK0);</div><div class='add'>+	optc_reg_state-&gt;otg_pixel_data_readback1 = REG_READ(OTG_PIXEL_DATA_READBACK1);</div><div class='add'>+	optc_reg_state-&gt;otg_request_control = REG_READ(OTG_REQUEST_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_snapshot_control = REG_READ(OTG_SNAPSHOT_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_snapshot_frame = REG_READ(OTG_SNAPSHOT_FRAME);</div><div class='add'>+	optc_reg_state-&gt;otg_snapshot_position = REG_READ(OTG_SNAPSHOT_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_snapshot_status = REG_READ(OTG_SNAPSHOT_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_spare_register = REG_READ(OTG_SPARE_REGISTER);</div><div class='add'>+	optc_reg_state-&gt;otg_static_screen_control = REG_READ(OTG_STATIC_SCREEN_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_status = REG_READ(OTG_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_status_frame_count = REG_READ(OTG_STATUS_FRAME_COUNT);</div><div class='add'>+	optc_reg_state-&gt;otg_status_hv_count = REG_READ(OTG_STATUS_HV_COUNT);</div><div class='add'>+	optc_reg_state-&gt;otg_status_position = REG_READ(OTG_STATUS_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_status_vf_count = REG_READ(OTG_STATUS_VF_COUNT);</div><div class='add'>+	optc_reg_state-&gt;otg_stereo_control = REG_READ(OTG_STEREO_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_stereo_force_next_eye = REG_READ(OTG_STEREO_FORCE_NEXT_EYE);</div><div class='add'>+	optc_reg_state-&gt;otg_stereo_status = REG_READ(OTG_STEREO_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_trig_manual_control = REG_READ(OTG_TRIG_MANUAL_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_triga_cntl = REG_READ(OTG_TRIGA_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_triga_manual_trig = REG_READ(OTG_TRIGA_MANUAL_TRIG);</div><div class='add'>+	optc_reg_state-&gt;otg_trigb_cntl = REG_READ(OTG_TRIGB_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_trigb_manual_trig = REG_READ(OTG_TRIGB_MANUAL_TRIG);</div><div class='add'>+	optc_reg_state-&gt;otg_update_lock = REG_READ(OTG_UPDATE_LOCK);</div><div class='add'>+	optc_reg_state-&gt;otg_v_blank_start_end = REG_READ(OTG_V_BLANK_START_END);</div><div class='add'>+	optc_reg_state-&gt;otg_v_count_stop_control = REG_READ(OTG_V_COUNT_STOP_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_v_count_stop_control2 = REG_READ(OTG_V_COUNT_STOP_CONTROL2);</div><div class='add'>+	optc_reg_state-&gt;otg_v_sync_a = REG_READ(OTG_V_SYNC_A);</div><div class='add'>+	optc_reg_state-&gt;otg_v_sync_a_cntl = REG_READ(OTG_V_SYNC_A_CNTL);</div><div class='add'>+	optc_reg_state-&gt;otg_v_total = REG_READ(OTG_V_TOTAL);</div><div class='add'>+	optc_reg_state-&gt;otg_v_total_control = REG_READ(OTG_V_TOTAL_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_v_total_int_status = REG_READ(OTG_V_TOTAL_INT_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_v_total_max = REG_READ(OTG_V_TOTAL_MAX);</div><div class='add'>+	optc_reg_state-&gt;otg_v_total_mid = REG_READ(OTG_V_TOTAL_MID);</div><div class='add'>+	optc_reg_state-&gt;otg_v_total_min = REG_READ(OTG_V_TOTAL_MIN);</div><div class='add'>+	optc_reg_state-&gt;otg_vert_sync_control = REG_READ(OTG_VERT_SYNC_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_vertical_interrupt0_control = REG_READ(OTG_VERTICAL_INTERRUPT0_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_vertical_interrupt0_position = REG_READ(OTG_VERTICAL_INTERRUPT0_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_vertical_interrupt1_control = REG_READ(OTG_VERTICAL_INTERRUPT1_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_vertical_interrupt1_position = REG_READ(OTG_VERTICAL_INTERRUPT1_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_vertical_interrupt2_control = REG_READ(OTG_VERTICAL_INTERRUPT2_CONTROL);</div><div class='add'>+	optc_reg_state-&gt;otg_vertical_interrupt2_position = REG_READ(OTG_VERTICAL_INTERRUPT2_POSITION);</div><div class='add'>+	optc_reg_state-&gt;otg_vready_param = REG_READ(OTG_VREADY_PARAM);</div><div class='add'>+	optc_reg_state-&gt;otg_vstartup_param = REG_READ(OTG_VSTARTUP_PARAM);</div><div class='add'>+	optc_reg_state-&gt;otg_vsync_nom_int_status = REG_READ(OTG_VSYNC_NOM_INT_STATUS);</div><div class='add'>+	optc_reg_state-&gt;otg_vupdate_keepout = REG_READ(OTG_VUPDATE_KEEPOUT);</div><div class='add'>+	optc_reg_state-&gt;otg_vupdate_param = REG_READ(OTG_VUPDATE_PARAM);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct timing_generator_funcs dcn31_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -292,6 +505,9 @@ static struct timing_generator_funcs dcn31_tg_funcs = {</div><div class='ctx'> 		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='ctx'> 		.init_odm = optc3_init_odm,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.read_otg_state = optc31_read_otg_state,</div><div class='add'>+		.optc_read_reg_state = optc31_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn31_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h<br/>index 30b81a448ce2..98f7d2e299c5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h</a></div><div class='hunk'>@@ -99,7 +99,9 @@</div><div class='ctx'> 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\</div><div class='ctx'> 	SRI(OTG_CRC_CNTL2, OTG, inst),\</div><div class='ctx'> 	SR(DWB_SOURCE_SELECT),\</div><div class='del'>-	SRI(OTG_DRR_CONTROL, OTG, inst)</div><div class='add'>+	SRI(OTG_DRR_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\</div><div class='add'>+	SRI(INTERRUPT_DEST, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\</div><div class='ctx'> 	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\</div><div class='hunk'>@@ -254,7 +256,12 @@</div><div class='ctx'> 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\</div><div class='del'>-	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)</div><div class='add'>+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='add'>+	SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)</div><div class='ctx'> </div><div class='ctx'> void dcn31_timing_generator_init(struct optc *optc1);</div><div class='ctx'> </div><div class='hunk'>@@ -264,4 +271,9 @@ void optc31_set_drr(struct timing_generator *optc, const struct drr_params *para</div><div class='ctx'> </div><div class='ctx'> void optc3_init_odm(struct timing_generator *optc);</div><div class='ctx'> </div><div class='add'>+void optc31_read_otg_state(struct timing_generator *optc,</div><div class='add'>+		struct dcn_otg_state *s);</div><div class='add'>+</div><div class='add'>+void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_OPTC_DCN31_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c<br/>index 0086cafb0f7a..43ff957288b2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c</a></div><div class='hunk'>@@ -48,12 +48,11 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing)</div><div class='add'>+		int segment_width, int last_segment_width)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> 	uint32_t memory_mask = 0;</div><div class='del'>-	int h_active = timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right;</div><div class='del'>-	int mpcc_hactive = h_active / opp_cnt;</div><div class='add'>+	int h_active = segment_width * opp_cnt;</div><div class='ctx'> 	/* Each memory instance is 2048x(314x2) bits to support half line of 4096 */</div><div class='ctx'> 	int odm_mem_count = (h_active + 2047) / 2048;</div><div class='ctx'> </div><div class='hunk'>@@ -96,7 +95,7 @@ static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='del'>-			OPTC_SEGMENT_WIDTH, mpcc_hactive);</div><div class='add'>+			OPTC_SEGMENT_WIDTH, segment_width);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='ctx'> 			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);</div><div class='hunk'>@@ -175,7 +174,7 @@ static void optc314_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 			OPTC_SEG3_SRC_SEL, 0xf</div><div class='ctx'> 			);</div><div class='ctx'> </div><div class='del'>-	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);</div><div class='add'>+	h_div = optc-&gt;funcs-&gt;is_two_pixels_per_container(dc_crtc_timing);</div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='ctx'> 			OTG_H_TIMING_DIV_MODE, h_div);</div><div class='ctx'> </div><div class='hunk'>@@ -193,7 +192,7 @@ static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn314_tg_funcs = {</div><div class='add'>+static const struct timing_generator_funcs dcn314_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -255,6 +254,9 @@ static struct timing_generator_funcs dcn314_tg_funcs = {</div><div class='ctx'> 		.set_odm_bypass = optc314_set_odm_bypass,</div><div class='ctx'> 		.set_odm_combine = optc314_set_odm_combine,</div><div class='ctx'> 		.set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.read_otg_state = optc31_read_otg_state,</div><div class='add'>+		.optc_read_reg_state = optc31_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn314_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h<br/>index 99c098e76116..6bfdee3fcf5f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h</a></div><div class='hunk'>@@ -98,7 +98,9 @@</div><div class='ctx'> 	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\</div><div class='ctx'> 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\</div><div class='ctx'> 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\</div><div class='del'>-	SRI(OTG_DRR_CONTROL, OTG, inst)</div><div class='add'>+	SRI(OTG_DRR_CONTROL, OTG, inst),\</div><div class='add'>+	SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst),\</div><div class='add'>+	SRI(INTERRUPT_DEST, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> #define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\</div><div class='ctx'> 	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\</div><div class='hunk'>@@ -248,7 +250,12 @@</div><div class='ctx'> 	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\</div><div class='del'>-	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)</div><div class='add'>+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='add'>+	SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)</div><div class='ctx'> </div><div class='ctx'> void dcn314_timing_generator_init(struct optc *optc1);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c<br/>index f07a4c7e48bc..3dcb0d0c931c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c</a></div><div class='hunk'>@@ -43,12 +43,11 @@</div><div class='ctx'> 	optc1-&gt;tg_shift-&gt;field_name, optc1-&gt;tg_mask-&gt;field_name</div><div class='ctx'> </div><div class='ctx'> static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing)</div><div class='add'>+		int segment_width, int last_segment_width)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> 	uint32_t memory_mask = 0;</div><div class='del'>-	int h_active = timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right;</div><div class='del'>-	int mpcc_hactive = h_active / opp_cnt;</div><div class='add'>+	int h_active = segment_width * opp_cnt;</div><div class='ctx'> 	/* Each memory instance is 2048x(32x2) bits to support half line of 4096 */</div><div class='ctx'> 	int odm_mem_count = (h_active + 2047) / 2048;</div><div class='ctx'> </div><div class='hunk'>@@ -91,7 +90,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='del'>-			OPTC_SEGMENT_WIDTH, mpcc_hactive);</div><div class='add'>+			OPTC_SEGMENT_WIDTH, segment_width);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='ctx'> 			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);</div><div class='hunk'>@@ -239,7 +238,7 @@ void optc32_set_odm_bypass(struct timing_generator *optc,</div><div class='ctx'> 			OPTC_SEG3_SRC_SEL, 0xf</div><div class='ctx'> 			);</div><div class='ctx'> </div><div class='del'>-	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);</div><div class='add'>+	h_div = optc-&gt;funcs-&gt;is_two_pixels_per_container(dc_crtc_timing);</div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='ctx'> 			OTG_H_TIMING_DIV_MODE, h_div);</div><div class='ctx'> </div><div class='hunk'>@@ -267,9 +266,6 @@ static void optc32_setup_manual_trigger(struct timing_generator *optc)</div><div class='ctx'> 				OTG_V_TOTAL_MAX_SEL, 1,</div><div class='ctx'> 				OTG_FORCE_LOCK_ON_EVENT, 0,</div><div class='ctx'> 				OTG_SET_V_TOTAL_MIN_MASK, (1 &lt;&lt; 1)); /* TRIGA */</div><div class='del'>-</div><div class='del'>-		// Setup manual flow control for EOF via TRIG_A</div><div class='del'>-		optc-&gt;funcs-&gt;setup_manual_trigger(optc);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -301,7 +297,7 @@ static void optc32_set_drr(</div><div class='ctx'> 	optc32_setup_manual_trigger(optc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn32_tg_funcs = {</div><div class='add'>+static const struct timing_generator_funcs dcn32_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -364,6 +360,12 @@ static struct timing_generator_funcs dcn32_tg_funcs = {</div><div class='ctx'> 		.program_manual_trigger = optc2_program_manual_trigger,</div><div class='ctx'> 		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,</div><div class='add'>+		.get_otg_double_buffer_pending = optc3_get_otg_update_pending,</div><div class='add'>+		.get_pipe_update_pending = optc3_get_pipe_update_pending,</div><div class='add'>+		.read_otg_state = optc31_read_otg_state,</div><div class='add'>+		.optc_read_reg_state = optc31_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn32_timing_generator_init(struct optc *optc1)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h<br/>index 0c2c14695561..ead92ad78a23 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h</a></div><div class='hunk'>@@ -62,6 +62,7 @@</div><div class='ctx'> 	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\</div><div class='hunk'>@@ -116,6 +117,7 @@</div><div class='ctx'> 	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\</div><div class='ctx'> 	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\</div><div class='ctx'> 	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\</div><div class='ctx'> 	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\</div><div class='ctx'> 	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\</div><div class='ctx'> 	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\</div><div class='hunk'>@@ -176,7 +178,12 @@</div><div class='ctx'> 	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\</div><div class='del'>-	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)</div><div class='add'>+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='add'>+	SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)</div><div class='ctx'> </div><div class='ctx'> void dcn32_timing_generator_init(struct optc *optc1);</div><div class='ctx'> void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c<br/>index 5b1547508850..f699e95059f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "dcn_calc_math.h"</div><div class='add'>+#include "dc_dmub_srv.h"</div><div class='ctx'> </div><div class='ctx'> #define REG(reg)\</div><div class='ctx'> 	optc1-&gt;tg_regs-&gt;reg</div><div class='hunk'>@@ -49,17 +50,17 @@</div><div class='ctx'>  * @optc: Output Pipe Timing Combine instance reference.</div><div class='ctx'>  * @opp_id: Output Plane Processor instance ID.</div><div class='ctx'>  * @opp_cnt: Output Plane Processor count.</div><div class='del'>- * @timing: Timing parameters used to configure DCN blocks.</div><div class='add'>+ * @segment_width: Width of the segment.</div><div class='add'>+ * @last_segment_width: Width of the last segment.</div><div class='ctx'>  *</div><div class='ctx'>  * Return: void.</div><div class='ctx'>  */</div><div class='ctx'> static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,</div><div class='del'>-		struct dc_crtc_timing *timing)</div><div class='add'>+		int segment_width, int last_segment_width)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> 	uint32_t memory_mask = 0;</div><div class='del'>-	int h_active = timing-&gt;h_addressable + timing-&gt;h_border_left + timing-&gt;h_border_right;</div><div class='del'>-	int mpcc_hactive = h_active / opp_cnt;</div><div class='add'>+	int h_active = segment_width * opp_cnt;</div><div class='ctx'> 	/* Each memory instance is 2048x(314x2) bits to support half line of 4096 */</div><div class='ctx'> 	int odm_mem_count = (h_active + 2047) / 2048;</div><div class='ctx'> </div><div class='hunk'>@@ -102,7 +103,7 @@ static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, i</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='del'>-			OPTC_SEGMENT_WIDTH, mpcc_hactive);</div><div class='add'>+			OPTC_SEGMENT_WIDTH, segment_width);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);</div><div class='ctx'> 	optc1-&gt;opp_count = opp_cnt;</div><div class='hunk'>@@ -161,6 +162,8 @@ static bool optc35_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> 	REG_WAIT(OTG_CLOCK_CONTROL,</div><div class='ctx'> 			OTG_BUSY, 0,</div><div class='ctx'> 			1, 100000);</div><div class='add'>+	REG_WAIT(OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);</div><div class='add'>+</div><div class='ctx'> 	optc1_clear_optc_underflow(optc);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -182,38 +185,267 @@ static bool optc35_configure_crc(struct timing_generator *optc,</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> </div><div class='add'>+	/* Cannot configure crc on a CRTC that is disabled */</div><div class='ctx'> 	if (!optc1_is_tg_enabled(optc))</div><div class='ctx'> 		return false;</div><div class='del'>-	REG_WRITE(OTG_CRC_CNTL, 0);</div><div class='add'>+</div><div class='add'>+	if (!params-&gt;enable || params-&gt;reset)</div><div class='add'>+		REG_WRITE(OTG_CRC_CNTL, 0);</div><div class='add'>+</div><div class='ctx'> 	if (!params-&gt;enable)</div><div class='ctx'> 		return true;</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='del'>-			OTG_CRC0_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='del'>-			OTG_CRC0_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='del'>-			OTG_CRC0_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='del'>-	REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,</div><div class='del'>-			OTG_CRC0_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='del'>-			OTG_CRC0_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='del'>-	if (optc1-&gt;base.ctx-&gt;dc-&gt;debug.otg_crc_db &amp;&amp; optc1-&gt;tg_mask-&gt;OTG_CRC_WINDOW_DB_EN != 0) {</div><div class='del'>-		REG_UPDATE_4(OTG_CRC_CNTL,</div><div class='del'>-				OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='del'>-				OTG_CRC0_SELECT, params-&gt;selection,</div><div class='del'>-				OTG_CRC_EN, 1,</div><div class='del'>-				OTG_CRC_WINDOW_DB_EN, 1);</div><div class='del'>-	} else</div><div class='del'>-		REG_UPDATE_3(OTG_CRC_CNTL,</div><div class='del'>-				OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='del'>-				OTG_CRC0_SELECT, params-&gt;selection,</div><div class='del'>-				OTG_CRC_EN, 1);</div><div class='add'>+</div><div class='add'>+	/* Program frame boundaries */</div><div class='add'>+	switch (params-&gt;crc_eng_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='add'>+				OTG_CRC0_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='add'>+				OTG_CRC0_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='add'>+				OTG_CRC0_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,</div><div class='add'>+				OTG_CRC0_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='add'>+				OTG_CRC0_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='add'>+</div><div class='add'>+		if (optc1-&gt;base.ctx-&gt;dc-&gt;debug.otg_crc_db &amp;&amp; optc1-&gt;tg_mask-&gt;OTG_CRC_WINDOW_DB_EN != 0)</div><div class='add'>+			REG_UPDATE_4(OTG_CRC_CNTL,</div><div class='add'>+					OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+					OTG_CRC0_SELECT, params-&gt;selection,</div><div class='add'>+					OTG_CRC_EN, 1,</div><div class='add'>+					OTG_CRC_WINDOW_DB_EN, 1);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_3(OTG_CRC_CNTL,</div><div class='add'>+					OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+					OTG_CRC0_SELECT, params-&gt;selection,</div><div class='add'>+					OTG_CRC_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		/* Window A x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWA_X_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWA_X_START, params-&gt;windowa_x_start,</div><div class='add'>+				OTG_CRC1_WINDOWA_X_END, params-&gt;windowa_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window A y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWA_Y_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWA_Y_START, params-&gt;windowa_y_start,</div><div class='add'>+				OTG_CRC1_WINDOWA_Y_END, params-&gt;windowa_y_end);</div><div class='add'>+</div><div class='add'>+		/* Window B x axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWB_X_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWB_X_START, params-&gt;windowb_x_start,</div><div class='add'>+				OTG_CRC1_WINDOWB_X_END, params-&gt;windowb_x_end);</div><div class='add'>+</div><div class='add'>+		/* Window B y axis start and end. */</div><div class='add'>+		REG_UPDATE_2(OTG_CRC1_WINDOWB_Y_CONTROL,</div><div class='add'>+				OTG_CRC1_WINDOWB_Y_START, params-&gt;windowb_y_start,</div><div class='add'>+				OTG_CRC1_WINDOWB_Y_END, params-&gt;windowb_y_end);</div><div class='add'>+</div><div class='add'>+		if (optc1-&gt;base.ctx-&gt;dc-&gt;debug.otg_crc_db &amp;&amp; optc1-&gt;tg_mask-&gt;OTG_CRC_WINDOW_DB_EN != 0)</div><div class='add'>+			REG_UPDATE_4(OTG_CRC_CNTL,</div><div class='add'>+					OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+					OTG_CRC1_SELECT, params-&gt;selection,</div><div class='add'>+					OTG_CRC_EN, 1,</div><div class='add'>+					OTG_CRC_WINDOW_DB_EN, 1);</div><div class='add'>+		else</div><div class='add'>+			REG_UPDATE_3(OTG_CRC_CNTL,</div><div class='add'>+					OTG_CRC_CONT_EN, params-&gt;continuous_mode ? 1 : 0,</div><div class='add'>+					OTG_CRC1_SELECT, params-&gt;selection,</div><div class='add'>+					OTG_CRC_EN, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct timing_generator_funcs dcn35_tg_funcs = {</div><div class='add'>+static void optc35_setup_manual_trigger(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	if (!optc || !optc-&gt;ctx)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	struct dc *dc = optc-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.dmub_caps.mclk_sw &amp;&amp; !dc-&gt;debug.disable_fams)</div><div class='add'>+		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc-&gt;inst);</div><div class='add'>+	else {</div><div class='add'>+		/*</div><div class='add'>+		 * MIN_MASK_EN is gone and MASK is now always enabled.</div><div class='add'>+		 *</div><div class='add'>+		 * To get it to it work with manual trigger we need to make sure</div><div class='add'>+		 * we program the correct bit.</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+				OTG_V_TOTAL_MIN_SEL, 1,</div><div class='add'>+				OTG_V_TOTAL_MAX_SEL, 1,</div><div class='add'>+				OTG_FORCE_LOCK_ON_EVENT, 0,</div><div class='add'>+				OTG_SET_V_TOTAL_MIN_MASK, (1 &lt;&lt; 1)); /* TRIGA */</div><div class='add'>+</div><div class='add'>+		// Setup manual flow control for EOF via TRIG_A</div><div class='add'>+		if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;setup_manual_trigger)</div><div class='add'>+			optc-&gt;funcs-&gt;setup_manual_trigger(optc);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc35_set_drr(</div><div class='add'>+	struct timing_generator *optc,</div><div class='add'>+	const struct drr_params *params)</div><div class='add'>+{</div><div class='add'>+	if (!optc || !params)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	uint32_t max_otg_v_total = optc1-&gt;max_v_total - 1;</div><div class='add'>+</div><div class='add'>+	if (params != NULL &amp;&amp;</div><div class='add'>+		params-&gt;vertical_total_max &gt; 0 &amp;&amp;</div><div class='add'>+		params-&gt;vertical_total_min &gt; 0) {</div><div class='add'>+</div><div class='add'>+		if (params-&gt;vertical_total_mid != 0) {</div><div class='add'>+</div><div class='add'>+			REG_SET(OTG_V_TOTAL_MID, 0,</div><div class='add'>+				OTG_V_TOTAL_MID, params-&gt;vertical_total_mid - 1);</div><div class='add'>+</div><div class='add'>+			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,</div><div class='add'>+					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,</div><div class='add'>+					OTG_VTOTAL_MID_FRAME_NUM,</div><div class='add'>+					(uint8_t)params-&gt;vertical_total_mid_frame_num);</div><div class='add'>+</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;set_vtotal_min_max)</div><div class='add'>+			optc-&gt;funcs-&gt;set_vtotal_min_max(optc,</div><div class='add'>+				params-&gt;vertical_total_min - 1, params-&gt;vertical_total_max - 1);</div><div class='add'>+		optc35_setup_manual_trigger(optc);</div><div class='add'>+	} else {</div><div class='add'>+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+				OTG_SET_V_TOTAL_MIN_MASK, 0,</div><div class='add'>+				OTG_V_TOTAL_MIN_SEL, 0,</div><div class='add'>+				OTG_V_TOTAL_MAX_SEL, 0,</div><div class='add'>+				OTG_FORCE_LOCK_ON_EVENT, 0);</div><div class='add'>+</div><div class='add'>+		if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;set_vtotal_min_max)</div><div class='add'>+			optc-&gt;funcs-&gt;set_vtotal_min_max(optc, 0, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);</div><div class='add'>+	REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void optc35_set_long_vtotal(</div><div class='add'>+	struct timing_generator *optc,</div><div class='add'>+	const struct long_vtotal_params *params)</div><div class='add'>+{</div><div class='add'>+	if (!optc || !params)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	uint32_t vcount_stop_timer = 0, vcount_stop = 0;</div><div class='add'>+	uint32_t max_otg_v_total = optc1-&gt;max_v_total - 1;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;vertical_total_min &lt;= max_otg_v_total &amp;&amp; params-&gt;vertical_total_max &lt;= max_otg_v_total)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (params-&gt;vertical_total_max == 0 || params-&gt;vertical_total_min == 0) {</div><div class='add'>+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+						OTG_SET_V_TOTAL_MIN_MASK, 0,</div><div class='add'>+						OTG_V_TOTAL_MIN_SEL, 0,</div><div class='add'>+						OTG_V_TOTAL_MAX_SEL, 0,</div><div class='add'>+						OTG_FORCE_LOCK_ON_EVENT, 0);</div><div class='add'>+</div><div class='add'>+		if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;set_vtotal_min_max)</div><div class='add'>+			optc-&gt;funcs-&gt;set_vtotal_min_max(optc, 0, 0);</div><div class='add'>+	} else if (params-&gt;vertical_total_max == params-&gt;vertical_total_min) {</div><div class='add'>+		vcount_stop = params-&gt;vertical_blank_start;</div><div class='add'>+		vcount_stop_timer = params-&gt;vertical_total_max - max_otg_v_total;</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+				OTG_V_TOTAL_MIN_SEL, 1,</div><div class='add'>+				OTG_V_TOTAL_MAX_SEL, 1,</div><div class='add'>+				OTG_FORCE_LOCK_ON_EVENT, 0,</div><div class='add'>+				OTG_SET_V_TOTAL_MIN_MASK, 0);</div><div class='add'>+</div><div class='add'>+		if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;set_vtotal_min_max)</div><div class='add'>+			optc-&gt;funcs-&gt;set_vtotal_min_max(optc, max_otg_v_total, max_otg_v_total);</div><div class='add'>+</div><div class='add'>+		REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);</div><div class='add'>+		REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);</div><div class='add'>+	} else {</div><div class='add'>+		// Variable rate, keep DRR trigger mask</div><div class='add'>+		if (params-&gt;vertical_total_min &gt; max_otg_v_total) {</div><div class='add'>+			// cannot be supported</div><div class='add'>+			// If MAX_OTG_V_COUNT &lt; DRR trigger &lt; v_total_min &lt; v_total_max,</div><div class='add'>+			// DRR trigger will drop the vtotal counting directly to a new frame.</div><div class='add'>+			// But it should trigger between v_total_min and v_total_max.</div><div class='add'>+			ASSERT(0);</div><div class='add'>+</div><div class='add'>+			REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+				OTG_SET_V_TOTAL_MIN_MASK, 0,</div><div class='add'>+				OTG_V_TOTAL_MIN_SEL, 0,</div><div class='add'>+				OTG_V_TOTAL_MAX_SEL, 0,</div><div class='add'>+				OTG_FORCE_LOCK_ON_EVENT, 0);</div><div class='add'>+</div><div class='add'>+			if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;set_vtotal_min_max)</div><div class='add'>+				optc-&gt;funcs-&gt;set_vtotal_min_max(optc, 0, 0);</div><div class='add'>+</div><div class='add'>+			REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);</div><div class='add'>+			REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);</div><div class='add'>+		} else {</div><div class='add'>+			// For total_min &lt;= MAX_OTG_V_COUNT and total_max &gt; MAX_OTG_V_COUNT</div><div class='add'>+			vcount_stop = params-&gt;vertical_total_min;</div><div class='add'>+			vcount_stop_timer = params-&gt;vertical_total_max - max_otg_v_total;</div><div class='add'>+</div><div class='add'>+			// Example:</div><div class='add'>+			// params-&gt;vertical_total_min 1000</div><div class='add'>+			// params-&gt;vertical_total_max 2000</div><div class='add'>+			// MAX_OTG_V_COUNT_STOP = 1500</div><div class='add'>+			//</div><div class='add'>+			// If DRR event not happened,</div><div class='add'>+			//     time     0,1,2,3,4,...1000,1001,........,1500,1501,1502,     ...1999</div><div class='add'>+			//     vcount   0,1,2,3,4....1000...................,1001,1002,1003,...1399</div><div class='add'>+			//     vcount2                       0,1,2,3,4,..499,</div><div class='add'>+			// else (DRR event happened, ex : at line 1004)</div><div class='add'>+			//     time    0,1,2,3,4,...1000,1001.....1004, 0</div><div class='add'>+			//     vcount  0,1,2,3,4....1000,.............. 0 (new frame)</div><div class='add'>+			//     vcount2                      0,1,2,   3, -</div><div class='add'>+			if (optc-&gt;funcs &amp;&amp; optc-&gt;funcs-&gt;set_vtotal_min_max)</div><div class='add'>+				optc-&gt;funcs-&gt;set_vtotal_min_max(optc,</div><div class='add'>+					params-&gt;vertical_total_min - 1, max_otg_v_total);</div><div class='add'>+			optc35_setup_manual_trigger(optc);</div><div class='add'>+</div><div class='add'>+			REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);</div><div class='add'>+			REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void optc35_wait_otg_disable(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1;</div><div class='add'>+	uint32_t is_master_en;</div><div class='add'>+</div><div class='add'>+	if (!optc || !optc-&gt;ctx)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_CONTROL, OTG_MASTER_EN, &amp;is_master_en);</div><div class='add'>+	if (!is_master_en)</div><div class='add'>+		REG_WAIT(OTG_CLOCK_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct timing_generator_funcs dcn35_tg_funcs = {</div><div class='ctx'> 		.validate_timing = optc1_validate_timing,</div><div class='ctx'> 		.program_timing = optc1_program_timing,</div><div class='ctx'> 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='hunk'>@@ -245,7 +477,7 @@ static struct timing_generator_funcs dcn35_tg_funcs = {</div><div class='ctx'> 		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,</div><div class='ctx'> 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,</div><div class='ctx'> 		.enable_optc_clock = optc1_enable_optc_clock,</div><div class='del'>-		.set_drr = optc31_set_drr,</div><div class='add'>+		.set_drr = optc35_set_drr,</div><div class='ctx'> 		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,</div><div class='ctx'> 		.set_vtotal_min_max = optc1_set_vtotal_min_max,</div><div class='ctx'> 		.set_static_screen_control = optc1_set_static_screen_control,</div><div class='hunk'>@@ -264,6 +496,7 @@ static struct timing_generator_funcs dcn35_tg_funcs = {</div><div class='ctx'> 		.set_odm_bypass = optc32_set_odm_bypass,</div><div class='ctx'> 		.set_odm_combine = optc35_set_odm_combine,</div><div class='ctx'> 		.get_optc_source = optc2_get_optc_source,</div><div class='add'>+		.wait_otg_disable = optc35_wait_otg_disable,</div><div class='ctx'> 		.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,</div><div class='ctx'> 		.set_out_mux = optc3_set_out_mux,</div><div class='ctx'> 		.set_drr_trigger_window = optc3_set_drr_trigger_window,</div><div class='hunk'>@@ -275,6 +508,10 @@ static struct timing_generator_funcs dcn35_tg_funcs = {</div><div class='ctx'> 		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='ctx'> 		.get_hw_timing = optc1_get_hw_timing,</div><div class='ctx'> 		.init_odm = optc3_init_odm,</div><div class='add'>+		.set_long_vtotal = optc35_set_long_vtotal,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.read_otg_state = optc31_read_otg_state,</div><div class='add'>+		.optc_read_reg_state = optc31_read_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dcn35_timing_generator_init(struct optc *optc1)</div><div class='hunk'>@@ -289,6 +526,7 @@ void dcn35_timing_generator_init(struct optc *optc1)</div><div class='ctx'> 	optc1-&gt;min_v_blank_interlace = 5;</div><div class='ctx'> 	optc1-&gt;min_h_sync_width = 4;</div><div class='ctx'> 	optc1-&gt;min_v_sync_width = 1;</div><div class='add'>+	optc1-&gt;max_frame_count = 0xFFFFFF;</div><div class='ctx'> </div><div class='ctx'> 	dcn35_timing_generator_set_fgcg(</div><div class='ctx'> 		optc1, CTX-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.optc);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h<br/>index 1f422e4c468f..733a2f149d9a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h</a></div><div class='hunk'>@@ -65,10 +65,19 @@</div><div class='ctx'> 	SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG_CRC1_WINDOWB_X_END_READBACK, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_START_READBACK, mask_sh),\</div><div class='ctx'> 	SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\</div><div class='del'>-	SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh)</div><div class='add'>+	SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_COUNT_STOP_CONTROL, OTG_V_COUNT_STOP, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='add'>+	SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)</div><div class='ctx'> </div><div class='ctx'> void dcn35_timing_generator_init(struct optc *optc1);</div><div class='ctx'> </div><div class='ctx'> void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);</div><div class='ctx'> </div><div class='add'>+void optc35_set_drr(struct timing_generator *optc, const struct drr_params *params);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_OPTC_DCN35_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c<br/>new file mode 100644<br/>index 000000000000..a8e978d1fae8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c</a></div><div class='hunk'>@@ -0,0 +1,552 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dcn401_optc.h"</div><div class='add'>+#include "dcn30/dcn30_optc.h"</div><div class='add'>+#include "dcn31/dcn31_optc.h"</div><div class='add'>+#include "dcn32/dcn32_optc.h"</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "dcn_calc_math.h"</div><div class='add'>+#include "dc_dmub_srv.h"</div><div class='add'>+</div><div class='add'>+#define REG(reg)\</div><div class='add'>+	optc1-&gt;tg_regs-&gt;reg</div><div class='add'>+</div><div class='add'>+#define CTX \</div><div class='add'>+	optc1-&gt;base.ctx</div><div class='add'>+</div><div class='add'>+#undef FN</div><div class='add'>+#define FN(reg_name, field_name) \</div><div class='add'>+	optc1-&gt;tg_shift-&gt;field_name, optc1-&gt;tg_mask-&gt;field_name</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * OPTC uses ODM_MEM sub block to merge pixel data coming from different OPPs</div><div class='add'>+ * into unified memory location per horizontal line. ODM_MEM contains shared</div><div class='add'>+ * memory resources global to the ASIC. Each memory resource is capable of</div><div class='add'>+ * storing 2048 pixels independent from actual pixel data size. Total number of</div><div class='add'>+ * memory allocated must be even. The memory resource allocation is described in</div><div class='add'>+ * a memory bit map per OPTC instance. Driver has to make sure that there is no</div><div class='add'>+ * double allocation across different OPTC instances. Bit offset in the map</div><div class='add'>+ * represents memory instance id. Driver allocates a memory instance to the</div><div class='add'>+ * current OPTC by setting the bit with offset associated with the desired</div><div class='add'>+ * memory instance to 1 in the current OPTC memory map register.</div><div class='add'>+ *</div><div class='add'>+ * It is upto software to decide how to allocate the shared memory resources</div><div class='add'>+ * across different OPTC instances. Driver understands that the total number</div><div class='add'>+ * of memory available is always 2 times the max number of OPP pipes. So each</div><div class='add'>+ * OPP pipe can be mapped 2 pieces of memory. However there exists cases such as</div><div class='add'>+ * 11520x2160 which could use 6 pieces of memory for 2 OPP pipes i.e. 3 pieces</div><div class='add'>+ * for each OPP pipe.</div><div class='add'>+ *</div><div class='add'>+ * Driver will reserve the first and second preferred memory instances for each</div><div class='add'>+ * OPP pipe. For example, OPP0's first and second preferred memory is ODM_MEM0</div><div class='add'>+ * and ODM_MEM1. OPP1's first and second preferred memory is  ODM_MEM2 and</div><div class='add'>+ * ODM_MEM3 so on so forth.</div><div class='add'>+ *</div><div class='add'>+ * Driver will first allocate from first preferred memory instances associated</div><div class='add'>+ * with current OPP pipes in use. If needed driver will then allocate from</div><div class='add'>+ * second preferred memory instances associated with current OPP pipes in use.</div><div class='add'>+ * Finally if still needed, driver will allocate from second preferred memory</div><div class='add'>+ * instances not associated with current OPP pipes. So if memory instances are</div><div class='add'>+ * enough other OPTCs can still allocate from their OPPs' first preferred memory</div><div class='add'>+ * instances without worrying about double allocation.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active)</div><div class='add'>+{</div><div class='add'>+	bool first_preferred_memory_for_opp[MAX_PIPES] = {0};</div><div class='add'>+	bool second_preferred_memory_for_opp[MAX_PIPES] = {0};</div><div class='add'>+	uint32_t memory_bit_map = 0;</div><div class='add'>+	int total_required = ((h_active + 4095) / 4096) * 2;</div><div class='add'>+	int total_allocated = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; opp_cnt; i++) {</div><div class='add'>+		first_preferred_memory_for_opp[opp_id[i]] = true;</div><div class='add'>+		total_allocated++;</div><div class='add'>+		if (total_required == total_allocated)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (total_required &gt; total_allocated) {</div><div class='add'>+		for (i = 0; i &lt; opp_cnt; i++) {</div><div class='add'>+			second_preferred_memory_for_opp[opp_id[i]] = true;</div><div class='add'>+			total_allocated++;</div><div class='add'>+			if (total_required == total_allocated)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (total_required &gt; total_allocated) {</div><div class='add'>+		for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+			if (second_preferred_memory_for_opp[i] == false) {</div><div class='add'>+				second_preferred_memory_for_opp[i] = true;</div><div class='add'>+				total_allocated++;</div><div class='add'>+				if (total_required == total_allocated)</div><div class='add'>+					break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	ASSERT(total_required == total_allocated);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (first_preferred_memory_for_opp[i])</div><div class='add'>+			memory_bit_map |= 0x1 &lt;&lt; (i * 2);</div><div class='add'>+		if (second_preferred_memory_for_opp[i])</div><div class='add'>+			memory_bit_map |= 0x2 &lt;&lt; (i * 2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return memory_bit_map;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id,</div><div class='add'>+		int opp_cnt, int segment_width, int last_segment_width)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width;</div><div class='add'>+	uint32_t odm_mem_bit_map = decide_odm_mem_bit_map(</div><div class='add'>+			opp_id, opp_cnt, h_active);</div><div class='add'>+</div><div class='add'>+	REG_SET(OPTC_MEMORY_CONFIG, 0,</div><div class='add'>+		OPTC_MEM_SEL, odm_mem_bit_map);</div><div class='add'>+</div><div class='add'>+	switch (opp_cnt) {</div><div class='add'>+	case 2: /* ODM Combine 2:1 */</div><div class='add'>+		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,</div><div class='add'>+				OPTC_NUM_OF_INPUT_SEGMENT, 1,</div><div class='add'>+				OPTC_SEG0_SRC_SEL, opp_id[0],</div><div class='add'>+				OPTC_SEG1_SRC_SEL, opp_id[1]);</div><div class='add'>+		REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='add'>+					OPTC_SEGMENT_WIDTH, segment_width);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='add'>+				OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY2);</div><div class='add'>+		break;</div><div class='add'>+	case 3: /* ODM Combine 3:1 */</div><div class='add'>+		REG_SET_4(OPTC_DATA_SOURCE_SELECT, 0,</div><div class='add'>+				OPTC_NUM_OF_INPUT_SEGMENT, 2,</div><div class='add'>+				OPTC_SEG0_SRC_SEL, opp_id[0],</div><div class='add'>+				OPTC_SEG1_SRC_SEL, opp_id[1],</div><div class='add'>+				OPTC_SEG2_SRC_SEL, opp_id[2]);</div><div class='add'>+		REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='add'>+				OPTC_SEGMENT_WIDTH, segment_width);</div><div class='add'>+		REG_UPDATE(OPTC_WIDTH_CONTROL2,</div><div class='add'>+				OPTC_SEGMENT_WIDTH_LAST,</div><div class='add'>+				last_segment_width);</div><div class='add'>+		/* In ODM combine 3:1 mode ODM packs 4 pixels per data transfer</div><div class='add'>+		 * so OTG_H_TIMING_DIV_MODE should be configured to</div><div class='add'>+		 * H_TIMING_DIV_BY4 even though ODM combines 3 OPP inputs, it</div><div class='add'>+		 * outputs 4 pixels from single OPP at a time.</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='add'>+				OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);</div><div class='add'>+		break;</div><div class='add'>+	case 4: /* ODM Combine 4:1 */</div><div class='add'>+		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,</div><div class='add'>+				OPTC_NUM_OF_INPUT_SEGMENT, 3,</div><div class='add'>+				OPTC_SEG0_SRC_SEL, opp_id[0],</div><div class='add'>+				OPTC_SEG1_SRC_SEL, opp_id[1],</div><div class='add'>+				OPTC_SEG2_SRC_SEL, opp_id[2],</div><div class='add'>+				OPTC_SEG3_SRC_SEL, opp_id[3]);</div><div class='add'>+		REG_UPDATE(OPTC_WIDTH_CONTROL,</div><div class='add'>+					OPTC_SEGMENT_WIDTH, segment_width);</div><div class='add'>+		REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='add'>+				OTG_H_TIMING_DIV_MODE, H_TIMING_DIV_BY4);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ASSERT(false);</div><div class='add'>+	}</div><div class='add'>+;</div><div class='add'>+	optc1-&gt;opp_count = opp_cnt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='add'>+			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);</div><div class='add'>+}</div><div class='add'>+/**</div><div class='add'>+ * optc401_enable_crtc() - Enable CRTC</div><div class='add'>+ * @optc: Pointer to the timing generator structure</div><div class='add'>+ *</div><div class='add'>+ * This function calls ASIC Control Object to enable Timing generator.</div><div class='add'>+ *</div><div class='add'>+ * Return: Always returns true</div><div class='add'>+ */</div><div class='add'>+bool optc401_enable_crtc(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */</div><div class='add'>+	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, optc-&gt;inst);</div><div class='add'>+</div><div class='add'>+	/* VTG enable first is for HW workaround */</div><div class='add'>+	REG_UPDATE(CONTROL,</div><div class='add'>+			VTG0_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	REG_SEQ_START();</div><div class='add'>+</div><div class='add'>+	/* Enable CRTC */</div><div class='add'>+	REG_UPDATE_2(OTG_CONTROL,</div><div class='add'>+			OTG_DISABLE_POINT_CNTL, 2,</div><div class='add'>+			OTG_MASTER_EN, 1);</div><div class='add'>+</div><div class='add'>+	REG_SEQ_SUBMIT();</div><div class='add'>+	REG_SEQ_WAIT_DONE();</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* disable_crtc */</div><div class='add'>+bool optc401_disable_crtc(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OPTC_MEMORY_CONFIG,</div><div class='add'>+			OPTC_MEM_SEL, 0);</div><div class='add'>+</div><div class='add'>+	/* disable otg request until end of the first line</div><div class='add'>+	 * in the vertical blank region</div><div class='add'>+	 */</div><div class='add'>+	REG_UPDATE(OTG_CONTROL,</div><div class='add'>+			OTG_MASTER_EN, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(CONTROL,</div><div class='add'>+			VTG0_ENABLE, 0);</div><div class='add'>+</div><div class='add'>+	// wait until CRTC_CURRENT_MASTER_EN_STATE == 0</div><div class='add'>+	REG_WAIT(OTG_CONTROL,</div><div class='add'>+			 OTG_CURRENT_MASTER_EN_STATE,</div><div class='add'>+			 0, 10, 15000);</div><div class='add'>+</div><div class='add'>+	/* CRTC disabled, so disable  clock. */</div><div class='add'>+	REG_WAIT(OTG_CLOCK_CONTROL,</div><div class='add'>+			OTG_BUSY, 0,</div><div class='add'>+			1, 150000);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_phantom_crtc_post_enable(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	/* Disable immediately. */</div><div class='add'>+	REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);</div><div class='add'>+</div><div class='add'>+	/* CRTC disabled, so disable  clock. */</div><div class='add'>+	REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_disable_phantom_otg(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_odm_bypass(struct timing_generator *optc,</div><div class='add'>+		const struct dc_crtc_timing *dc_crtc_timing)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;</div><div class='add'>+</div><div class='add'>+	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, optc-&gt;inst,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf</div><div class='add'>+			);</div><div class='add'>+</div><div class='add'>+	h_div = optc-&gt;funcs-&gt;is_two_pixels_per_container(dc_crtc_timing);</div><div class='add'>+	REG_UPDATE(OTG_H_TIMING_CNTL,</div><div class='add'>+			OTG_H_TIMING_DIV_MODE, h_div);</div><div class='add'>+</div><div class='add'>+	REG_SET(OPTC_MEMORY_CONFIG, 0,</div><div class='add'>+			OPTC_MEM_SEL, 0);</div><div class='add'>+	optc1-&gt;opp_count = 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* only to be used when FAMS2 is disabled or unsupported */</div><div class='add'>+void optc401_setup_manual_trigger(struct timing_generator *optc)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	struct dc *dc = optc-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.dmub_caps.fams_ver == 1 &amp;&amp; !dc-&gt;debug.disable_fams)</div><div class='add'>+		/* FAMS */</div><div class='add'>+		dc_dmub_srv_set_drr_manual_trigger_cmd(dc, optc-&gt;inst);</div><div class='add'>+	else {</div><div class='add'>+		/*</div><div class='add'>+		 * MIN_MASK_EN is gone and MASK is now always enabled.</div><div class='add'>+		 *</div><div class='add'>+		 * To get it to it work with manual trigger we need to make sure</div><div class='add'>+		 * we program the correct bit.</div><div class='add'>+		 */</div><div class='add'>+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+				OTG_V_TOTAL_MIN_SEL, 1,</div><div class='add'>+				OTG_V_TOTAL_MAX_SEL, 1,</div><div class='add'>+				OTG_FORCE_LOCK_ON_EVENT, 0,</div><div class='add'>+				OTG_SET_V_TOTAL_MIN_MASK, (1 &lt;&lt; 1)); /* TRIGA */</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_drr(</div><div class='add'>+	struct timing_generator *optc,</div><div class='add'>+	const struct drr_params *params)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+	struct dc *dc = optc-&gt;ctx-&gt;dc;</div><div class='add'>+	struct drr_params amended_params = { 0 };</div><div class='add'>+	bool program_manual_trigger = false;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.dmub_caps.fams_ver == dc-&gt;debug.fams_version.ver &amp;&amp; dc-&gt;debug.fams2_config.bits.enable) {</div><div class='add'>+		if (params != NULL &amp;&amp;</div><div class='add'>+				params-&gt;vertical_total_max &gt; 0 &amp;&amp;</div><div class='add'>+				params-&gt;vertical_total_min &gt; 0) {</div><div class='add'>+			amended_params.vertical_total_max = params-&gt;vertical_total_max - 1;</div><div class='add'>+			amended_params.vertical_total_min = params-&gt;vertical_total_min - 1;</div><div class='add'>+			if (params-&gt;vertical_total_mid != 0) {</div><div class='add'>+				amended_params.vertical_total_mid = params-&gt;vertical_total_mid - 1;</div><div class='add'>+				amended_params.vertical_total_mid_frame_num = params-&gt;vertical_total_mid_frame_num;</div><div class='add'>+			}</div><div class='add'>+			program_manual_trigger = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dc_dmub_srv_fams2_drr_update(dc, optc-&gt;inst,</div><div class='add'>+				amended_params.vertical_total_min,</div><div class='add'>+				amended_params.vertical_total_max,</div><div class='add'>+				amended_params.vertical_total_mid,</div><div class='add'>+				amended_params.vertical_total_mid_frame_num,</div><div class='add'>+				program_manual_trigger);</div><div class='add'>+	} else {</div><div class='add'>+		if (params != NULL &amp;&amp;</div><div class='add'>+			params-&gt;vertical_total_max &gt; 0 &amp;&amp;</div><div class='add'>+			params-&gt;vertical_total_min &gt; 0) {</div><div class='add'>+</div><div class='add'>+			if (params-&gt;vertical_total_mid != 0) {</div><div class='add'>+</div><div class='add'>+				REG_SET(OTG_V_TOTAL_MID, 0,</div><div class='add'>+					OTG_V_TOTAL_MID, params-&gt;vertical_total_mid - 1);</div><div class='add'>+</div><div class='add'>+				REG_UPDATE_2(OTG_V_TOTAL_CONTROL,</div><div class='add'>+						OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,</div><div class='add'>+						OTG_VTOTAL_MID_FRAME_NUM,</div><div class='add'>+						(uint8_t)params-&gt;vertical_total_mid_frame_num);</div><div class='add'>+</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			optc-&gt;funcs-&gt;set_vtotal_min_max(optc, params-&gt;vertical_total_min - 1, params-&gt;vertical_total_max - 1);</div><div class='add'>+			optc401_setup_manual_trigger(optc);</div><div class='add'>+		} else {</div><div class='add'>+			REG_UPDATE_4(OTG_V_TOTAL_CONTROL,</div><div class='add'>+					OTG_SET_V_TOTAL_MIN_MASK, 0,</div><div class='add'>+					OTG_V_TOTAL_MIN_SEL, 0,</div><div class='add'>+					OTG_V_TOTAL_MAX_SEL, 0,</div><div class='add'>+					OTG_FORCE_LOCK_ON_EVENT, 0);</div><div class='add'>+</div><div class='add'>+			optc-&gt;funcs-&gt;set_vtotal_min_max(optc, 0, 0);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	/* 00 - OTG_CONTROL_OTG_OUT_MUX_0 : Connects to DIO.</div><div class='add'>+	   01 - OTG_CONTROL_OTG_OUT_MUX_1 : Reserved.</div><div class='add'>+	   02 - OTG_CONTROL_OTG_OUT_MUX_2 : Connects to HPO.</div><div class='add'>+	*/</div><div class='add'>+	REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = optc-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.dmub_caps.fams_ver == dc-&gt;debug.fams_version.ver &amp;&amp; dc-&gt;debug.fams2_config.bits.enable) {</div><div class='add'>+		/* FAMS2 */</div><div class='add'>+		dc_dmub_srv_fams2_drr_update(dc, optc-&gt;inst,</div><div class='add'>+				vtotal_min,</div><div class='add'>+				vtotal_max,</div><div class='add'>+				0,</div><div class='add'>+				0,</div><div class='add'>+				false);</div><div class='add'>+	} else if (dc-&gt;caps.dmub_caps.fams_ver == 1 &amp;&amp; !dc-&gt;debug.disable_fams) {</div><div class='add'>+		/* FAMS */</div><div class='add'>+		dc_dmub_srv_drr_update_cmd(dc, optc-&gt;inst, vtotal_min, vtotal_max);</div><div class='add'>+	} else {</div><div class='add'>+		optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_program_global_sync(</div><div class='add'>+		struct timing_generator *optc,</div><div class='add'>+		int vready_offset,</div><div class='add'>+		int vstartup_start,</div><div class='add'>+		int vupdate_offset,</div><div class='add'>+		int vupdate_width,</div><div class='add'>+		int pstate_keepout)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='add'>+</div><div class='add'>+	optc1-&gt;vready_offset = vready_offset;</div><div class='add'>+	optc1-&gt;vstartup_start = vstartup_start;</div><div class='add'>+	optc1-&gt;vupdate_offset = vupdate_offset;</div><div class='add'>+	optc1-&gt;vupdate_width = vupdate_width;</div><div class='add'>+	optc1-&gt;pstate_keepout = pstate_keepout;</div><div class='add'>+</div><div class='add'>+	if (optc1-&gt;vstartup_start == 0) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_SET(OTG_VSTARTUP_PARAM, 0,</div><div class='add'>+		VSTARTUP_START, optc1-&gt;vstartup_start);</div><div class='add'>+</div><div class='add'>+	REG_SET_2(OTG_VUPDATE_PARAM, 0,</div><div class='add'>+			VUPDATE_OFFSET, optc1-&gt;vupdate_offset,</div><div class='add'>+			VUPDATE_WIDTH, optc1-&gt;vupdate_width);</div><div class='add'>+</div><div class='add'>+	REG_SET(OTG_VREADY_PARAM, 0,</div><div class='add'>+			VREADY_OFFSET, optc1-&gt;vready_offset);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, pstate_keepout);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(tg);</div><div class='add'>+</div><div class='add'>+	REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,</div><div class='add'>+		MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,</div><div class='add'>+		MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, optc1-&gt;vready_offset + 10,</div><div class='add'>+		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, enable);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool optc401_wait_update_lock_status(struct timing_generator *tg, bool locked)</div><div class='add'>+{</div><div class='add'>+	struct optc *optc1 = DCN10TG_FROM_TG(tg);</div><div class='add'>+	uint32_t lock_status = 0;</div><div class='add'>+</div><div class='add'>+	REG_WAIT(OTG_MASTER_UPDATE_LOCK,</div><div class='add'>+			UPDATE_LOCK_STATUS, locked,</div><div class='add'>+			1, 150000);</div><div class='add'>+</div><div class='add'>+	REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &amp;lock_status);</div><div class='add'>+</div><div class='add'>+	if (lock_status != locked)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct timing_generator_funcs dcn401_tg_funcs = {</div><div class='add'>+		.validate_timing = optc1_validate_timing,</div><div class='add'>+		.program_timing = optc1_program_timing,</div><div class='add'>+		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,</div><div class='add'>+		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,</div><div class='add'>+		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,</div><div class='add'>+		.program_global_sync = optc401_program_global_sync,</div><div class='add'>+		.enable_crtc = optc401_enable_crtc,</div><div class='add'>+		.disable_crtc = optc401_disable_crtc,</div><div class='add'>+		.phantom_crtc_post_enable = optc401_phantom_crtc_post_enable,</div><div class='add'>+		.disable_phantom_crtc = optc401_disable_phantom_otg,</div><div class='add'>+		/* used by enable_timing_synchronization. Not need for FPGA */</div><div class='add'>+		.is_counter_moving = optc1_is_counter_moving,</div><div class='add'>+		.get_position = optc1_get_position,</div><div class='add'>+		.get_frame_count = optc1_get_vblank_counter,</div><div class='add'>+		.get_scanoutpos = optc1_get_crtc_scanoutpos,</div><div class='add'>+		.get_otg_active_size = optc1_get_otg_active_size,</div><div class='add'>+		.set_early_control = optc1_set_early_control,</div><div class='add'>+		/* used by enable_timing_synchronization. Not need for FPGA */</div><div class='add'>+		.wait_for_state = optc1_wait_for_state,</div><div class='add'>+		.set_blank_color = optc3_program_blank_color,</div><div class='add'>+		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,</div><div class='add'>+		.triplebuffer_lock = optc3_triplebuffer_lock,</div><div class='add'>+		.triplebuffer_unlock = optc2_triplebuffer_unlock,</div><div class='add'>+		.enable_reset_trigger = optc1_enable_reset_trigger,</div><div class='add'>+		.enable_crtc_reset = optc1_enable_crtc_reset,</div><div class='add'>+		.disable_reset_trigger = optc1_disable_reset_trigger,</div><div class='add'>+		.lock = optc3_lock,</div><div class='add'>+		.unlock = optc1_unlock,</div><div class='add'>+		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,</div><div class='add'>+		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,</div><div class='add'>+		.enable_optc_clock = optc1_enable_optc_clock,</div><div class='add'>+		.set_drr = optc401_set_drr,</div><div class='add'>+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,</div><div class='add'>+		.set_vtotal_min_max = optc401_set_vtotal_min_max,</div><div class='add'>+		.set_static_screen_control = optc1_set_static_screen_control,</div><div class='add'>+		.program_stereo = optc1_program_stereo,</div><div class='add'>+		.is_stereo_left_eye = optc1_is_stereo_left_eye,</div><div class='add'>+		.tg_init = optc3_tg_init,</div><div class='add'>+		.is_tg_enabled = optc1_is_tg_enabled,</div><div class='add'>+		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,</div><div class='add'>+		.clear_optc_underflow = optc1_clear_optc_underflow,</div><div class='add'>+		.setup_global_swap_lock = NULL,</div><div class='add'>+		.get_crc = optc1_get_crc,</div><div class='add'>+		.configure_crc = optc1_configure_crc,</div><div class='add'>+		.set_dsc_config = optc3_set_dsc_config,</div><div class='add'>+		.get_dsc_status = optc2_get_dsc_status,</div><div class='add'>+		.set_dwb_source = NULL,</div><div class='add'>+		.set_odm_bypass = optc401_set_odm_bypass,</div><div class='add'>+		.set_odm_combine = optc401_set_odm_combine,</div><div class='add'>+		.wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear,</div><div class='add'>+		.set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode,</div><div class='add'>+		.get_optc_source = optc2_get_optc_source,</div><div class='add'>+		.set_out_mux = optc401_set_out_mux,</div><div class='add'>+		.set_drr_trigger_window = optc3_set_drr_trigger_window,</div><div class='add'>+		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,</div><div class='add'>+		.set_gsl = optc2_set_gsl,</div><div class='add'>+		.set_gsl_source_select = optc2_set_gsl_source_select,</div><div class='add'>+		.set_vtg_params = optc1_set_vtg_params,</div><div class='add'>+		.program_manual_trigger = optc2_program_manual_trigger,</div><div class='add'>+		.setup_manual_trigger = optc2_setup_manual_trigger,</div><div class='add'>+		.get_hw_timing = optc1_get_hw_timing,</div><div class='add'>+		.is_two_pixels_per_container = optc1_is_two_pixels_per_container,</div><div class='add'>+		.get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending,</div><div class='add'>+		.get_otg_double_buffer_pending = optc3_get_otg_update_pending,</div><div class='add'>+		.get_pipe_update_pending = optc3_get_pipe_update_pending,</div><div class='add'>+		.set_vupdate_keepout = optc401_set_vupdate_keepout,</div><div class='add'>+		.wait_update_lock_status = optc401_wait_update_lock_status,</div><div class='add'>+		.read_otg_state = optc31_read_otg_state,</div><div class='add'>+		.optc_read_reg_state = optc31_read_reg_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn401_timing_generator_init(struct optc *optc1)</div><div class='add'>+{</div><div class='add'>+	optc1-&gt;base.funcs = &amp;dcn401_tg_funcs;</div><div class='add'>+</div><div class='add'>+	optc1-&gt;max_h_total = optc1-&gt;tg_mask-&gt;OTG_H_TOTAL + 1;</div><div class='add'>+	optc1-&gt;max_v_total = optc1-&gt;tg_mask-&gt;OTG_V_TOTAL + 1;</div><div class='add'>+</div><div class='add'>+	optc1-&gt;min_h_blank = 32;</div><div class='add'>+	optc1-&gt;min_v_blank = 3;</div><div class='add'>+	optc1-&gt;min_v_blank_interlace = 5;</div><div class='add'>+	optc1-&gt;min_h_sync_width = 4;</div><div class='add'>+	optc1-&gt;min_v_sync_width = 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h<br/>new file mode 100644<br/>index 000000000000..fa62737b5b1b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h</a></div><div class='hunk'>@@ -0,0 +1,196 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_OPTC_DCN401_H__</div><div class='add'>+#define __DC_OPTC_DCN401_H__</div><div class='add'>+</div><div class='add'>+#include "dcn10/dcn10_optc.h"</div><div class='add'>+</div><div class='add'>+#define OPTC_COMMON_MASK_SH_LIST_DCN401(mask_sh)\</div><div class='add'>+	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\</div><div class='add'>+	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\</div><div class='add'>+	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\</div><div class='add'>+	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\</div><div class='add'>+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\</div><div class='add'>+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\</div><div class='add'>+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \</div><div class='add'>+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \</div><div class='add'>+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \</div><div class='add'>+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \</div><div class='add'>+	SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \</div><div class='add'>+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\</div><div class='add'>+	SF(ODM0_OPTC_WIDTH_CONTROL2, OPTC_SEGMENT_WIDTH_LAST, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\</div><div class='add'>+	SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\</div><div class='add'>+	SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh)</div><div class='add'>+</div><div class='add'>+void dcn401_timing_generator_init(struct optc *optc1);</div><div class='add'>+</div><div class='add'>+void optc401_set_drr(</div><div class='add'>+	struct timing_generator *optc,</div><div class='add'>+	const struct drr_params *params);</div><div class='add'>+void optc401_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);</div><div class='add'>+void optc401_setup_manual_trigger(struct timing_generator *optc);</div><div class='add'>+void optc401_program_global_sync(</div><div class='add'>+		struct timing_generator *optc,</div><div class='add'>+		int vready_offset,</div><div class='add'>+		int vstartup_start,</div><div class='add'>+		int vupdate_offset,</div><div class='add'>+		int vupdate_width,</div><div class='add'>+		int pstate_keepout);</div><div class='add'>+bool optc401_enable_crtc(struct timing_generator *optc);</div><div class='add'>+bool optc401_disable_crtc(struct timing_generator *optc);</div><div class='add'>+void optc401_phantom_crtc_post_enable(struct timing_generator *optc);</div><div class='add'>+void optc401_disable_phantom_otg(struct timing_generator *optc);</div><div class='add'>+void optc401_set_odm_bypass(struct timing_generator *optc,</div><div class='add'>+		const struct dc_crtc_timing *dc_crtc_timing);</div><div class='add'>+void optc401_set_odm_combine(struct timing_generator *optc, int *opp_id,</div><div class='add'>+		int opp_cnt, int segment_width, int last_segment_width);</div><div class='add'>+void optc401_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);</div><div class='add'>+void optc401_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest);</div><div class='add'>+bool optc401_wait_update_lock_status(struct timing_generator *tg, bool locked);</div><div class='add'>+void optc401_set_vupdate_keepout(struct timing_generator *tg, bool enable);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_OPTC_DCN401_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h<br/>index 6c4578d347af..782316348941 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/os_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/os_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/os_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/os_types.h</a></div><div class='hunk'>@@ -29,10 +29,9 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/kgdb.h&gt;</div><div class='del'>-#include &lt;linux/kref.h&gt;</div><div class='del'>-#include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/mm.h&gt;</div><div class='add'>+#include &lt;linux/vmalloc.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/byteorder.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/pg/Makefile b/drivers/gpu/drm/amd/display/dc/pg/Makefile<br/>new file mode 100644<br/>index 000000000000..ec11d3157a57<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/pg/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/pg/Makefile</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Authors: AMD</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN35</div><div class='add'>+###############################################################################</div><div class='add'>+PG_DCN35 = dcn35_pg_cntl.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_PG_DCN35 = $(addprefix $(AMDDALPATH)/dc/pg/dcn35/,$(PG_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN35)</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c<br/>index 53bd0ae4bab5..72bd43f9bbe2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c</a></div><div class='hunk'>@@ -79,16 +79,12 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo</div><div class='ctx'> 	uint32_t power_gate = power_on ? 0 : 1;</div><div class='ctx'> 	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='ctx'> 	uint32_t org_ip_request_cntl = 0;</div><div class='del'>-	bool block_enabled;</div><div class='del'>-</div><div class='del'>-	/*need to enable dscclk regardless DSC_PG*/</div><div class='del'>-	if (pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;enable_dsc &amp;&amp; power_on)</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;enable_dsc(</div><div class='del'>-				pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg, dsc_inst);</div><div class='add'>+	bool block_enabled = false;</div><div class='add'>+	bool skip_pg = pg_cntl-&gt;ctx-&gt;dc-&gt;debug.ignore_pg ||</div><div class='add'>+		       pg_cntl-&gt;ctx-&gt;dc-&gt;debug.disable_dsc_power_gate ||</div><div class='add'>+		       pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed;</div><div class='ctx'> </div><div class='del'>-	if (pg_cntl-&gt;ctx-&gt;dc-&gt;debug.ignore_pg ||</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;debug.disable_dsc_power_gate ||</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed)</div><div class='add'>+	if (skip_pg &amp;&amp; !power_on)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst);</div><div class='hunk'>@@ -111,7 +107,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo</div><div class='ctx'> </div><div class='ctx'> 		REG_WAIT(DOMAIN16_PG_STATUS,</div><div class='ctx'> 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='add'>+				1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 1: /* DSC1 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN17_PG_CONFIG,</div><div class='hunk'>@@ -119,7 +115,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo</div><div class='ctx'> </div><div class='ctx'> 		REG_WAIT(DOMAIN17_PG_STATUS,</div><div class='ctx'> 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='add'>+				1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2: /* DSC2 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN18_PG_CONFIG,</div><div class='hunk'>@@ -127,7 +123,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo</div><div class='ctx'> </div><div class='ctx'> 		REG_WAIT(DOMAIN18_PG_STATUS,</div><div class='ctx'> 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='add'>+				1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 3: /* DSC3 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN19_PG_CONFIG,</div><div class='hunk'>@@ -135,7 +131,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo</div><div class='ctx'> </div><div class='ctx'> 		REG_WAIT(DOMAIN19_PG_STATUS,</div><div class='ctx'> 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,</div><div class='del'>-				1, 1000);</div><div class='add'>+				1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -144,12 +140,6 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo</div><div class='ctx'> </div><div class='ctx'> 	if (dsc_inst &lt; MAX_PIPES)</div><div class='ctx'> 		pg_cntl-&gt;pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on;</div><div class='del'>-</div><div class='del'>-	if (pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;disable_dsc &amp;&amp; !power_on) {</div><div class='del'>-		/*this is to disable dscclk*/</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;disable_dsc(</div><div class='del'>-			pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dccg, dsc_inst);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst)</div><div class='hunk'>@@ -189,11 +179,12 @@ void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dp</div><div class='ctx'> 	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='ctx'> 	uint32_t org_ip_request_cntl;</div><div class='ctx'> 	bool block_enabled;</div><div class='add'>+	bool skip_pg = pg_cntl-&gt;ctx-&gt;dc-&gt;debug.ignore_pg ||</div><div class='add'>+		       pg_cntl-&gt;ctx-&gt;dc-&gt;debug.disable_hubp_power_gate ||</div><div class='add'>+		       pg_cntl-&gt;ctx-&gt;dc-&gt;debug.disable_dpp_power_gate ||</div><div class='add'>+		       pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed;</div><div class='ctx'> </div><div class='del'>-	if (pg_cntl-&gt;ctx-&gt;dc-&gt;debug.ignore_pg ||</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;debug.disable_hubp_power_gate ||</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;debug.disable_dpp_power_gate ||</div><div class='del'>-		pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed)</div><div class='add'>+	if (skip_pg &amp;&amp; !power_on)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst);</div><div class='hunk'>@@ -213,22 +204,22 @@ void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dp</div><div class='ctx'> 	case 0:</div><div class='ctx'> 		/* DPP0 &amp; HUBP0 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);</div><div class='add'>+		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 1:</div><div class='ctx'> 		/* DPP1 &amp; HUBP1 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);</div><div class='add'>+		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='ctx'> 		/* DPP2 &amp; HUBP2 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);</div><div class='add'>+		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 3:</div><div class='ctx'> 		/* DPP3 &amp; HUBP3 */</div><div class='ctx'> 		REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);</div><div class='del'>-		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);</div><div class='add'>+		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -359,7 +350,7 @@ void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,</div><div class='ctx'> 	if (pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (mpcc_inst &gt;= 0 &amp;&amp; mpcc_inst &lt; MAX_PIPES)</div><div class='add'>+	if (mpcc_inst &lt; MAX_PIPES)</div><div class='ctx'> 		pg_cntl-&gt;pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -369,7 +360,7 @@ void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,</div><div class='ctx'> 	if (pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (opp_inst &gt;= 0 &amp;&amp; opp_inst &lt; MAX_PIPES)</div><div class='add'>+	if (opp_inst &lt; MAX_PIPES)</div><div class='ctx'> 		pg_cntl-&gt;pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -379,7 +370,7 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,</div><div class='ctx'> 	if (pg_cntl-&gt;ctx-&gt;dc-&gt;idle_optimizations_allowed)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (optc_inst &gt;= 0 &amp;&amp; optc_inst &lt; MAX_PIPES)</div><div class='add'>+	if (optc_inst &lt; MAX_PIPES)</div><div class='ctx'> 		pg_cntl-&gt;pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -501,6 +492,36 @@ void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl)</div><div class='ctx'> 	pg_cntl-&gt;pg_res_enable[PG_DWB] = block_enabled;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	bool block_enabled = false;</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("%s: %s", debug_func, debug_log);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("PG_CNTL status:\n");</div><div class='add'>+</div><div class='add'>+	block_enabled = pg_cntl35_io_clk_status(pg_cntl);</div><div class='add'>+	DC_LOG_DEBUG("ONO0=%d (DCCG, DIO, DCIO)\n", block_enabled ? 1 : 0);</div><div class='add'>+</div><div class='add'>+	block_enabled = pg_cntl35_mem_status(pg_cntl);</div><div class='add'>+	DC_LOG_DEBUG("ONO1=%d (DCHUBBUB, DCHVM, DCHUBBUBMEM)\n", block_enabled ? 1 : 0);</div><div class='add'>+</div><div class='add'>+	block_enabled = pg_cntl35_plane_otg_status(pg_cntl);</div><div class='add'>+	DC_LOG_DEBUG("ONO2=%d (MPC, OPP, OPTC, DWB)\n", block_enabled ? 1 : 0);</div><div class='add'>+</div><div class='add'>+	block_enabled = pg_cntl35_hpo_pg_status(pg_cntl);</div><div class='add'>+	DC_LOG_DEBUG("ONO3=%d (HPO)\n", block_enabled ? 1 : 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pg_cntl-&gt;ctx-&gt;dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i);</div><div class='add'>+		DC_LOG_DEBUG("ONO%d=%d (DCHUBP%d, DPP%d)\n", 4 + i * 2, block_enabled ? 1 : 0, i, i);</div><div class='add'>+</div><div class='add'>+		block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i);</div><div class='add'>+		DC_LOG_DEBUG("ONO%d=%d (DSC%d)\n", 5 + i * 2, block_enabled ? 1 : 0, i);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct pg_cntl_funcs pg_cntl35_funcs = {</div><div class='ctx'> 	.init_pg_status = pg_cntl35_init_pg_status,</div><div class='ctx'> 	.dsc_pg_control = pg_cntl35_dsc_pg_control,</div><div class='hunk'>@@ -511,7 +532,8 @@ static const struct pg_cntl_funcs pg_cntl35_funcs = {</div><div class='ctx'> 	.mpcc_pg_control = pg_cntl35_mpcc_pg_control,</div><div class='ctx'> 	.opp_pg_control = pg_cntl35_opp_pg_control,</div><div class='ctx'> 	.optc_pg_control = pg_cntl35_optc_pg_control,</div><div class='del'>-	.dwb_pg_control = pg_cntl35_dwb_pg_control</div><div class='add'>+	.dwb_pg_control = pg_cntl35_dwb_pg_control,</div><div class='add'>+	.print_pg_status = pg_cntl35_print_pg_status</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct pg_cntl *pg_cntl35_create(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h<br/>index 3de240884d22..3de240884d22 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/Makefile b/drivers/gpu/drm/amd/display/dc/resource/Makefile<br/>index 184b1f23aa77..5b42da8b79c2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/Makefile</a></div><div class='hunk'>@@ -27,6 +27,24 @@</div><div class='ctx'> #  DCE</div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_SI</div><div class='add'>+RESOURCE_DCE60 = dce60_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE60 = $(addprefix $(AMDDALPATH)/dc/resource/dce60/,$(RESOURCE_DCE60))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE60)</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCE80 = dce80_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE80 = $(addprefix $(AMDDALPATH)/dc/resource/dce80/,$(RESOURCE_DCE80))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE80)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='ctx'> RESOURCE_DCE100 = dce100_resource.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_RESOURCE_DCE100 = $(addprefix $(AMDDALPATH)/dc/resource/dce100/,$(RESOURCE_DCE100))</div><div class='hunk'>@@ -57,14 +75,6 @@ AMD_DAL_RESOURCE_DCE120 = $(addprefix $(AMDDALPATH)/dc/resource/dce120/,$(RESOUR</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE120)</div><div class='ctx'> </div><div class='del'>-###############################################################################</div><div class='del'>-</div><div class='del'>-RESOURCE_DCE80 = dce80_resource.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_RESOURCE_DCE80 = $(addprefix $(AMDDALPATH)/dc/resource/dce80/,$(RESOURCE_DCE80))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE80)</div><div class='del'>-</div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> ###############################################################################</div><div class='ctx'> # DCN</div><div class='hunk'>@@ -102,10 +112,6 @@ AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN21)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-###############################################################################</div><div class='del'>-</div><div class='del'>-###############################################################################</div><div class='del'>-</div><div class='ctx'> RESOURCE_DCN30 = dcn30_resource.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_RESOURCE_DCN30 = $(addprefix $(AMDDALPATH)/dc/resource/dcn30/,$(RESOURCE_DCN30))</div><div class='hunk'>@@ -170,7 +176,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN316)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-RESOURCE_DCN32 = dcn32_resource.o</div><div class='add'>+RESOURCE_DCN32 = dcn32_resource.o dcn32_resource_helpers.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_RESOURCE_DCN32 = $(addprefix $(AMDDALPATH)/dc/resource/dcn32/,$(RESOURCE_DCN32))</div><div class='ctx'> </div><div class='hunk'>@@ -202,6 +208,18 @@ AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN351)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='add'>+RESOURCE_DCN36 = dcn36_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN36 = $(addprefix $(AMDDALPATH)/dc/resource/dcn36/,$(RESOURCE_DCN36))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN36)</div><div class='add'>+</div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='add'>+RESOURCE_DCN401 = dcn401_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN401 = $(addprefix $(AMDDALPATH)/dc/resource/dcn401/,$(RESOURCE_DCN401))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN401)</div><div class='add'>+</div><div class='ctx'> endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c<br/>index 53a5f4cb648c..d40d91ec2035 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "stream_encoder.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='ctx'> #include "virtual/virtual_stream_encoder.h"</div><div class='ctx'> #include "dce110/dce110_resource.h"</div><div class='hunk'>@@ -77,6 +78,7 @@</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #ifndef mmBIOS_SCRATCH_2</div><div class='add'>+	#define mmBIOS_SCRATCH_0 0x05C9</div><div class='ctx'> 	#define mmBIOS_SCRATCH_2 0x05CB</div><div class='ctx'> 	#define mmBIOS_SCRATCH_3 0x05CC</div><div class='ctx'> 	#define mmBIOS_SCRATCH_6 0x05CF</div><div class='hunk'>@@ -224,6 +226,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {</div><div class='ctx'> 	link_regs(4),</div><div class='ctx'> 	link_regs(5),</div><div class='ctx'> 	link_regs(6),</div><div class='add'>+	{ .DAC_ENABLE = mmDAC_ENABLE },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define stream_enc_regs(id)\</div><div class='hunk'>@@ -367,6 +370,7 @@ static const struct dce_abm_mask abm_mask = {</div><div class='ctx'> #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03</div><div class='ctx'> </div><div class='ctx'> static const struct bios_registers bios_regs = {</div><div class='add'>+	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,</div><div class='ctx'> 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,</div><div class='ctx'> 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6</div><div class='ctx'> };</div><div class='hunk'>@@ -374,6 +378,7 @@ static const struct bios_registers bios_regs = {</div><div class='ctx'> static const struct resource_caps res_cap = {</div><div class='ctx'> 	.num_timing_generator = 6,</div><div class='ctx'> 	.num_audio = 6,</div><div class='add'>+	.num_analog_stream_encoder = 1,</div><div class='ctx'> 	.num_stream_encoder = 6,</div><div class='ctx'> 	.num_pll = 3,</div><div class='ctx'> 	.num_ddc = 6,</div><div class='hunk'>@@ -401,8 +406,10 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dc_debug_options debug_defaults = {</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='add'>+static const struct dc_debug_options debug_defaults = { 0 };</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define CTX  ctx</div><div class='hunk'>@@ -483,6 +490,11 @@ static struct stream_encoder *dce100_stream_encoder_create(</div><div class='ctx'> 	if (!enc110)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) {</div><div class='add'>+		dce110_analog_stream_encoder_construct(enc110, ctx, ctx-&gt;dc_bios, eng_id);</div><div class='add'>+		return &amp;enc110-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dce110_stream_encoder_construct(enc110, ctx, ctx-&gt;dc_bios, eng_id,</div><div class='ctx'> 					&amp;stream_enc_regs[eng_id], &amp;se_shift, &amp;se_mask);</div><div class='ctx'> 	return &amp;enc110-&gt;base;</div><div class='hunk'>@@ -626,6 +638,19 @@ static struct link_encoder *dce100_link_encoder_create(</div><div class='ctx'> 	if (!enc110)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (enc_init_data-&gt;connector.id == CONNECTOR_ID_VGA) {</div><div class='add'>+		dce110_link_encoder_construct(enc110,</div><div class='add'>+			enc_init_data,</div><div class='add'>+			&amp;link_enc_feature,</div><div class='add'>+			&amp;link_enc_regs[ENGINE_ID_DACA],</div><div class='add'>+			NULL,</div><div class='add'>+			NULL);</div><div class='add'>+		return &amp;enc110-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	link_regs_id =</div><div class='ctx'> 		map_transmitter_id_to_phy_instance(enc_init_data-&gt;transmitter);</div><div class='ctx'> </div><div class='hunk'>@@ -836,17 +861,24 @@ static enum dc_status build_mapped_resource(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce100_validate_bandwidth(</div><div class='add'>+enum dc_status dce100_validate_bandwidth(</div><div class='ctx'> 	struct dc  *dc,</div><div class='ctx'> 	struct dc_state *context,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	bool at_least_one_pipe = false;</div><div class='add'>+	struct dc_stream_state *stream = NULL;</div><div class='add'>+	const uint32_t max_pix_clk_khz = max(dc-&gt;clk_mgr-&gt;clks.max_supported_dispclk_khz, 400000);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		if (context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='add'>+		stream = context-&gt;res_ctx.pipe_ctx[i].stream;</div><div class='add'>+		if (stream) {</div><div class='ctx'> 			at_least_one_pipe = true;</div><div class='add'>+</div><div class='add'>+			if (stream-&gt;timing.pix_clk_100hz &gt;= max_pix_clk_khz * 10)</div><div class='add'>+				return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (at_least_one_pipe) {</div><div class='hunk'>@@ -854,11 +886,20 @@ static bool dce100_validate_bandwidth(</div><div class='ctx'> 		context-&gt;bw_ctx.bw.dce.dispclk_khz = 681000;</div><div class='ctx'> 		context-&gt;bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;</div><div class='ctx'> 	} else {</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.dispclk_khz = 0;</div><div class='add'>+		/* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and</div><div class='add'>+		 * the DP clock, and shouldn't be turned off. Just select the display</div><div class='add'>+		 * clock value from its low power mode.</div><div class='add'>+		 */</div><div class='add'>+		if (dc-&gt;ctx-&gt;dce_version == DCE_VERSION_6_0 ||</div><div class='add'>+			dc-&gt;ctx-&gt;dce_version == DCE_VERSION_6_4)</div><div class='add'>+			context-&gt;bw_ctx.bw.dce.dispclk_khz = 352000;</div><div class='add'>+		else</div><div class='add'>+			context-&gt;bw_ctx.bw.dce.dispclk_khz = 0;</div><div class='add'>+</div><div class='ctx'> 		context-&gt;bw_ctx.bw.dce.yclk_khz = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return true;</div><div class='add'>+	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool dce100_validate_surface_sets(</div><div class='hunk'>@@ -881,7 +922,7 @@ static bool dce100_validate_surface_sets(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum dc_status dce100_validate_global(</div><div class='add'>+enum dc_status dce100_validate_global(</div><div class='ctx'> 		struct dc  *dc,</div><div class='ctx'> 		struct dc_state *context)</div><div class='ctx'> {</div><div class='hunk'>@@ -935,6 +976,10 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int j = -1;</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='add'>+	enum engine_id preferred_engine = link-&gt;link_enc-&gt;preferred_engine;</div><div class='add'>+</div><div class='add'>+	if (dc_is_rgb_signal(stream-&gt;signal))</div><div class='add'>+		preferred_engine = link-&gt;link_enc-&gt;analog_engine;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;stream_enc_count; i++) {</div><div class='ctx'> 		if (!res_ctx-&gt;is_stream_enc_acquired[i] &amp;&amp;</div><div class='hunk'>@@ -943,8 +988,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(</div><div class='ctx'> 			 * in daisy chain use case</div><div class='ctx'> 			 */</div><div class='ctx'> 			j = i;</div><div class='del'>-			if (pool-&gt;stream_enc[i]-&gt;id ==</div><div class='del'>-					link-&gt;link_enc-&gt;preferred_engine)</div><div class='add'>+			if (pool-&gt;stream_enc[i]-&gt;id == preferred_engine)</div><div class='ctx'> 				return pool-&gt;stream_enc[i];</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1069,13 +1113,14 @@ static bool dce100_resource_construct(</div><div class='ctx'> 	pool-&gt;base.timing_generator_count = pool-&gt;base.res_cap-&gt;num_timing_generator;</div><div class='ctx'> 	dc-&gt;caps.max_downscale_ratio = 200;</div><div class='ctx'> 	dc-&gt;caps.i2c_speed_in_khz = 40;</div><div class='del'>-	dc-&gt;caps.i2c_speed_in_khz = 40;</div><div class='add'>+	dc-&gt;caps.i2c_speed_in_khz_hdcp = 40;</div><div class='ctx'> 	dc-&gt;caps.max_cursor_size = 128;</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.dual_link_dvi = true;</div><div class='ctx'> 	dc-&gt;caps.disable_dp_clk_share = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = false;</div><div class='ctx'> 	dc-&gt;debug = debug_defaults;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;base.pipe_count; i++) {</div><div class='ctx'> 		pool-&gt;base.timing_generators[i] =</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h<br/>index fecab7c560f5..dd150a4b4610 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h</a></div><div class='hunk'>@@ -41,6 +41,15 @@ struct resource_pool *dce100_create_resource_pool(</div><div class='ctx'> </div><div class='ctx'> enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);</div><div class='ctx'> </div><div class='add'>+enum dc_status dce100_validate_global(</div><div class='add'>+		struct dc  *dc,</div><div class='add'>+		struct dc_state *context);</div><div class='add'>+</div><div class='add'>+enum dc_status dce100_validate_bandwidth(</div><div class='add'>+		struct dc  *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='add'>+</div><div class='ctx'> enum dc_status dce100_add_stream_to_ctx(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *new_ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c<br/>index fe518fd27b08..cd54382c0af3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c</a></div><div class='hunk'>@@ -82,6 +82,7 @@</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #ifndef mmBIOS_SCRATCH_2</div><div class='add'>+	#define mmBIOS_SCRATCH_0 0x05C9</div><div class='ctx'> 	#define mmBIOS_SCRATCH_2 0x05CB</div><div class='ctx'> 	#define mmBIOS_SCRATCH_3 0x05CC</div><div class='ctx'> 	#define mmBIOS_SCRATCH_6 0x05CF</div><div class='hunk'>@@ -377,6 +378,7 @@ static const struct dce110_clk_src_mask cs_mask = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct bios_registers bios_regs = {</div><div class='add'>+	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,</div><div class='ctx'> 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,</div><div class='ctx'> 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6</div><div class='ctx'> };</div><div class='hunk'>@@ -424,7 +426,9 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 		64</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dc_debug_options debug_defaults = {</div><div class='add'>+static const struct dc_debug_options debug_defaults = { 0 };</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='ctx'> 		.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -668,7 +672,7 @@ static struct link_encoder *dce110_link_encoder_create(</div><div class='ctx'> 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);</div><div class='ctx'> 	int link_regs_id;</div><div class='ctx'> </div><div class='del'>-	if (!enc110)</div><div class='add'>+	if (!enc110 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	link_regs_id =</div><div class='hunk'>@@ -960,10 +964,10 @@ static enum dc_status build_mapped_resource(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce110_validate_bandwidth(</div><div class='add'>+static enum dc_status dce110_validate_bandwidth(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct dc_state *context,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool result = false;</div><div class='ctx'> </div><div class='hunk'>@@ -1031,7 +1035,7 @@ static bool dce110_validate_bandwidth(</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dce.yclk_khz,</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dce.blackout_recovery_time_us);</div><div class='ctx'> 	}</div><div class='del'>-	return result;</div><div class='add'>+	return result ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,</div><div class='hunk'>@@ -1163,6 +1167,7 @@ static struct pipe_ctx *dce110_acquire_underlay(</div><div class='ctx'> 				0,</div><div class='ctx'> 				0,</div><div class='ctx'> 				0,</div><div class='add'>+				0,</div><div class='ctx'> 				pipe_ctx-&gt;stream-&gt;signal,</div><div class='ctx'> 				false);</div><div class='ctx'> </div><div class='hunk'>@@ -1375,6 +1380,7 @@ static bool dce110_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.is_apu = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = false;</div><div class='ctx'> 	dc-&gt;debug = debug_defaults;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	/*************************************************</div><div class='ctx'> 	 *  Create resources                             *</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c<br/>index d1edac46c9a0..3f0a6bc4dcc2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c</a></div><div class='hunk'>@@ -76,6 +76,7 @@</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> #ifndef mmBIOS_SCRATCH_2</div><div class='add'>+	#define mmBIOS_SCRATCH_0 0x05C9</div><div class='ctx'> 	#define mmBIOS_SCRATCH_2 0x05CB</div><div class='ctx'> 	#define mmBIOS_SCRATCH_3 0x05CC</div><div class='ctx'> 	#define mmBIOS_SCRATCH_6 0x05CF</div><div class='hunk'>@@ -385,6 +386,7 @@ static const struct dce110_clk_src_mask cs_mask = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct bios_registers bios_regs = {</div><div class='add'>+	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,</div><div class='ctx'> 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,</div><div class='ctx'> 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6</div><div class='ctx'> };</div><div class='hunk'>@@ -429,8 +431,10 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 	64</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dc_debug_options debug_defaults = {</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='add'>+static const struct dc_debug_options debug_defaults = { 0 };</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define CTX  ctx</div><div class='hunk'>@@ -629,7 +633,7 @@ static struct link_encoder *dce112_link_encoder_create(</div><div class='ctx'> 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);</div><div class='ctx'> 	int link_regs_id;</div><div class='ctx'> </div><div class='del'>-	if (!enc110)</div><div class='add'>+	if (!enc110 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	link_regs_id =</div><div class='hunk'>@@ -864,8 +868,6 @@ static struct clock_source *find_matching_pll(</div><div class='ctx'> 	default:</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum dc_status build_mapped_resource(</div><div class='hunk'>@@ -885,10 +887,10 @@ static enum dc_status build_mapped_resource(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dce112_validate_bandwidth(</div><div class='add'>+enum dc_status dce112_validate_bandwidth(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct dc_state *context,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool result = false;</div><div class='ctx'> </div><div class='hunk'>@@ -954,7 +956,7 @@ bool dce112_validate_bandwidth(</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dce.yclk_khz,</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dce.blackout_recovery_time_us);</div><div class='ctx'> 	}</div><div class='del'>-	return result;</div><div class='add'>+	return result ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum dc_status resource_map_phy_clock_resources(</div><div class='hunk'>@@ -1069,7 +1071,10 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)</div><div class='ctx'> 	struct dm_pp_clock_levels clks = {0};</div><div class='ctx'> 	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;bw_vbios &amp;&amp; dc-&gt;bw_vbios-&gt;memory_type == bw_def_hbm)</div><div class='add'>+	if (!dc-&gt;bw_vbios)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bw_vbios-&gt;memory_type == bw_def_hbm)</div><div class='ctx'> 		memory_type_multiplier = MEMORY_TYPE_HBM;</div><div class='ctx'> </div><div class='ctx'> 	/*do system clock  TODO PPLIB: after PPLIB implement,</div><div class='hunk'>@@ -1110,12 +1115,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)</div><div class='ctx'> 				&amp;clks);</div><div class='ctx'> </div><div class='ctx'> 		dc-&gt;bw_vbios-&gt;low_yclk = bw_frc_to_fixed(</div><div class='del'>-			clks.clocks_in_khz[0] * memory_type_multiplier, 1000);</div><div class='add'>+			(int64_t)clks.clocks_in_khz[0] * memory_type_multiplier, 1000);</div><div class='ctx'> 		dc-&gt;bw_vbios-&gt;mid_yclk = bw_frc_to_fixed(</div><div class='del'>-			clks.clocks_in_khz[clks.num_levels&gt;&gt;1] * memory_type_multiplier,</div><div class='add'>+			(int64_t)clks.clocks_in_khz[clks.num_levels&gt;&gt;1] * memory_type_multiplier,</div><div class='ctx'> 			1000);</div><div class='ctx'> 		dc-&gt;bw_vbios-&gt;high_yclk = bw_frc_to_fixed(</div><div class='del'>-			clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,</div><div class='add'>+			(int64_t)clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,</div><div class='ctx'> 			1000);</div><div class='ctx'> </div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1151,12 +1156,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)</div><div class='ctx'> 	 * YCLK = UMACLK*m_memoryTypeMultiplier</div><div class='ctx'> 	 */</div><div class='ctx'> 	dc-&gt;bw_vbios-&gt;low_yclk = bw_frc_to_fixed(</div><div class='del'>-		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);</div><div class='add'>+		(int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);</div><div class='ctx'> 	dc-&gt;bw_vbios-&gt;mid_yclk = bw_frc_to_fixed(</div><div class='del'>-		mem_clks.data[mem_clks.num_levels&gt;&gt;1].clocks_in_khz * memory_type_multiplier,</div><div class='add'>+		(int64_t)mem_clks.data[mem_clks.num_levels&gt;&gt;1].clocks_in_khz * memory_type_multiplier,</div><div class='ctx'> 		1000);</div><div class='ctx'> 	dc-&gt;bw_vbios-&gt;high_yclk = bw_frc_to_fixed(</div><div class='del'>-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,</div><div class='add'>+		(int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,</div><div class='ctx'> 		1000);</div><div class='ctx'> </div><div class='ctx'> 	/* Now notify PPLib/SMU about which Watermarks sets they should select</div><div class='hunk'>@@ -1246,6 +1251,7 @@ static bool dce112_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.dual_link_dvi = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = false;</div><div class='ctx'> 	dc-&gt;debug = debug_defaults;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	/*************************************************</div><div class='ctx'> 	 *  Create resources                             *</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h<br/>index 1f57ebc6f9b4..3efc4c55d2d2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h</a></div><div class='hunk'>@@ -42,10 +42,10 @@ enum dc_status dce112_validate_with_context(</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		struct dc_state *old_context);</div><div class='ctx'> </div><div class='del'>-bool dce112_validate_bandwidth(</div><div class='add'>+enum dc_status dce112_validate_bandwidth(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct dc_state *context,</div><div class='del'>-	bool fast_validate);</div><div class='add'>+	enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> enum dc_status dce112_add_stream_to_ctx(</div><div class='ctx'> 		struct dc *dc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c<br/>index 20662edd0ae4..b1570b6b1af3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c</a></div><div class='hunk'>@@ -67,6 +67,7 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce100/dce100_resource.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL</div><div class='ctx'> 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f</div><div class='hunk'>@@ -490,6 +491,7 @@ static struct dce_i2c_hw *dce120_i2c_hw_create(</div><div class='ctx'> 	return dce_i2c_hw;</div><div class='ctx'> }</div><div class='ctx'> static const struct bios_registers bios_regs = {</div><div class='add'>+	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0 + NBIO_BASE(mmBIOS_SCRATCH_0_BASE_IDX),</div><div class='ctx'> 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),</div><div class='ctx'> 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)</div><div class='ctx'> };</div><div class='hunk'>@@ -525,8 +527,11 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dc_debug_options debug_defaults = {</div><div class='del'>-		.disable_clock_gate = true,</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='add'>+	.disable_clock_gate = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clock_source *dce120_clock_source_create(</div><div class='hunk'>@@ -659,6 +664,12 @@ static void dce120_resource_destruct(struct dce110_resource_pool *pool)</div><div class='ctx'> </div><div class='ctx'> 	if (pool-&gt;base.dmcu != NULL)</div><div class='ctx'> 		dce_dmcu_destroy(&amp;pool-&gt;base.dmcu);</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.oem_device != NULL) {</div><div class='add'>+		struct dc *dc = pool-&gt;base.oem_device-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+		dc-&gt;link_srv-&gt;destroy_ddc_service(&amp;pool-&gt;base.oem_device);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void read_dce_straps(</div><div class='hunk'>@@ -706,7 +717,7 @@ static struct link_encoder *dce120_link_encoder_create(</div><div class='ctx'> 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);</div><div class='ctx'> 	int link_regs_id;</div><div class='ctx'> </div><div class='del'>-	if (!enc110)</div><div class='add'>+	if (!enc110 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	link_regs_id =</div><div class='hunk'>@@ -983,12 +994,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)</div><div class='ctx'> 		memory_type_multiplier = MEMORY_TYPE_HBM;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;bw_vbios-&gt;low_yclk = bw_frc_to_fixed(</div><div class='del'>-		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);</div><div class='add'>+		(int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);</div><div class='ctx'> 	dc-&gt;bw_vbios-&gt;mid_yclk = bw_frc_to_fixed(</div><div class='del'>-		mem_clks.data[mem_clks.num_levels&gt;&gt;1].clocks_in_khz * memory_type_multiplier,</div><div class='add'>+		(int64_t)mem_clks.data[mem_clks.num_levels&gt;&gt;1].clocks_in_khz * memory_type_multiplier,</div><div class='ctx'> 		1000);</div><div class='ctx'> 	dc-&gt;bw_vbios-&gt;high_yclk = bw_frc_to_fixed(</div><div class='del'>-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,</div><div class='add'>+		(int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,</div><div class='ctx'> 		1000);</div><div class='ctx'> </div><div class='ctx'> 	/* Now notify PPLib/SMU about which Watermarks sets they should select</div><div class='hunk'>@@ -1054,13 +1065,14 @@ static bool dce120_resource_construct(</div><div class='ctx'> 	struct dc *dc,</div><div class='ctx'> 	struct dce110_resource_pool *pool)</div><div class='ctx'> {</div><div class='add'>+	struct ddc_service_init_data ddc_init_data = {0};</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	int j;</div><div class='ctx'> 	struct dc_context *ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct irq_service_init_data irq_init_data;</div><div class='ctx'> 	static const struct resource_create_funcs *res_funcs;</div><div class='ctx'> 	bool is_vg20 = ASICREV_IS_VEGA20_P(ctx-&gt;asic_id.hw_internal_rev);</div><div class='del'>-	uint32_t pipe_fuses;</div><div class='add'>+	uint32_t pipe_fuses = 0;</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;dc_bios-&gt;regs = &amp;bios_regs;</div><div class='ctx'> </div><div class='hunk'>@@ -1081,6 +1093,7 @@ static bool dce120_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.psp_setup_panel_mode = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = false;</div><div class='ctx'> 	dc-&gt;debug = debug_defaults;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	/*************************************************</div><div class='ctx'> 	 *  Create resources                             *</div><div class='hunk'>@@ -1257,6 +1270,15 @@ static bool dce120_resource_construct(</div><div class='ctx'> </div><div class='ctx'> 	bw_calcs_data_update_from_pplib(dc);</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='add'>+		ddc_init_data.ctx = dc-&gt;ctx;</div><div class='add'>+		ddc_init_data.link = NULL;</div><div class='add'>+		ddc_init_data.id.id = dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_obj_id;</div><div class='add'>+		ddc_init_data.id.enum_id = 0;</div><div class='add'>+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;</div><div class='add'>+		pool-&gt;base.oem_device = dc-&gt;link_srv-&gt;create_ddc_service(&amp;ddc_init_data);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='ctx'> irqs_create_fail:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c<br/>index 8db9f7514466..f0152933bee2 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> #include "stream_encoder.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='ctx'> #include "irq/dce60/irq_service_dce60.h"</div><div class='ctx'> #include "dce110/dce110_timing_generator.h"</div><div class='hunk'>@@ -48,7 +49,7 @@</div><div class='ctx'> #include "dce/dce_clock_source.h"</div><div class='ctx'> #include "dce/dce_audio.h"</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='del'>-#include "dce60/dce60_hw_sequencer.h"</div><div class='add'>+#include "dce60/dce60_hwseq.h"</div><div class='ctx'> #include "dce100/dce100_resource.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='hunk'>@@ -79,6 +80,7 @@</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #ifndef mmBIOS_SCRATCH_2</div><div class='add'>+	#define mmBIOS_SCRATCH_0 0x05C9</div><div class='ctx'> 	#define mmBIOS_SCRATCH_2 0x05CB</div><div class='ctx'> 	#define mmBIOS_SCRATCH_3 0x05CC</div><div class='ctx'> 	#define mmBIOS_SCRATCH_6 0x05CF</div><div class='hunk'>@@ -239,7 +241,9 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {</div><div class='ctx'> 	link_regs(2),</div><div class='ctx'> 	link_regs(3),</div><div class='ctx'> 	link_regs(4),</div><div class='del'>-	link_regs(5)</div><div class='add'>+	link_regs(5),</div><div class='add'>+	{0},</div><div class='add'>+	{ .DAC_ENABLE = mmDAC_ENABLE },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define stream_enc_regs(id)\</div><div class='hunk'>@@ -365,6 +369,7 @@ static const struct dce110_clk_src_mask cs_mask = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct bios_registers bios_regs = {</div><div class='add'>+	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,</div><div class='ctx'> 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,</div><div class='ctx'> 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6</div><div class='ctx'> };</div><div class='hunk'>@@ -372,8 +377,9 @@ static const struct bios_registers bios_regs = {</div><div class='ctx'> static const struct resource_caps res_cap = {</div><div class='ctx'> 		.num_timing_generator = 6,</div><div class='ctx'> 		.num_audio = 6,</div><div class='add'>+		.num_analog_stream_encoder = 1,</div><div class='ctx'> 		.num_stream_encoder = 6,</div><div class='del'>-		.num_pll = 2,</div><div class='add'>+		.num_pll = 3,</div><div class='ctx'> 		.num_ddc = 6,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -381,6 +387,7 @@ static const struct resource_caps res_cap_61 = {</div><div class='ctx'> 		.num_timing_generator = 4,</div><div class='ctx'> 		.num_audio = 6,</div><div class='ctx'> 		.num_stream_encoder = 6,</div><div class='add'>+		.num_analog_stream_encoder = 1,</div><div class='ctx'> 		.num_pll = 3,</div><div class='ctx'> 		.num_ddc = 6,</div><div class='ctx'> };</div><div class='hunk'>@@ -388,8 +395,9 @@ static const struct resource_caps res_cap_61 = {</div><div class='ctx'> static const struct resource_caps res_cap_64 = {</div><div class='ctx'> 		.num_timing_generator = 2,</div><div class='ctx'> 		.num_audio = 2,</div><div class='add'>+		.num_analog_stream_encoder = 1,</div><div class='ctx'> 		.num_stream_encoder = 2,</div><div class='del'>-		.num_pll = 2,</div><div class='add'>+		.num_pll = 3,</div><div class='ctx'> 		.num_ddc = 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -403,13 +411,13 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='ctx'> 	.max_upscale_factor = {</div><div class='del'>-			.argb8888 = 16000,</div><div class='add'>+			.argb8888 = 1,</div><div class='ctx'> 			.nv12 = 1,</div><div class='ctx'> 			.fp16 = 1</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='ctx'> 	.max_downscale_factor = {</div><div class='del'>-			.argb8888 = 250,</div><div class='add'>+			.argb8888 = 1,</div><div class='ctx'> 			.nv12 = 1,</div><div class='ctx'> 			.fp16 = 1</div><div class='ctx'> 	}</div><div class='hunk'>@@ -598,6 +606,11 @@ static struct stream_encoder *dce60_stream_encoder_create(</div><div class='ctx'> 	if (!enc110)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) {</div><div class='add'>+		dce110_analog_stream_encoder_construct(enc110, ctx, ctx-&gt;dc_bios, eng_id);</div><div class='add'>+		return &amp;enc110-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dce110_stream_encoder_construct(enc110, ctx, ctx-&gt;dc_bios, eng_id,</div><div class='ctx'> 					&amp;stream_enc_regs[eng_id],</div><div class='ctx'> 					&amp;se_shift, &amp;se_mask);</div><div class='hunk'>@@ -720,6 +733,19 @@ static struct link_encoder *dce60_link_encoder_create(</div><div class='ctx'> 	if (!enc110)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (enc_init_data-&gt;connector.id == CONNECTOR_ID_VGA) {</div><div class='add'>+		dce110_link_encoder_construct(enc110,</div><div class='add'>+			enc_init_data,</div><div class='add'>+			&amp;link_enc_feature,</div><div class='add'>+			&amp;link_enc_regs[ENGINE_ID_DACA],</div><div class='add'>+			NULL,</div><div class='add'>+			NULL);</div><div class='add'>+		return &amp;enc110-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	link_regs_id =</div><div class='ctx'> 		map_transmitter_id_to_phy_instance(enc_init_data-&gt;transmitter);</div><div class='ctx'> </div><div class='hunk'>@@ -863,61 +889,6 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce60_validate_bandwidth(</div><div class='del'>-	struct dc *dc,</div><div class='del'>-	struct dc_state *context,</div><div class='del'>-	bool fast_validate)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	bool at_least_one_pipe = false;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		if (context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='del'>-			at_least_one_pipe = true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (at_least_one_pipe) {</div><div class='del'>-		/* TODO implement when needed but for now hardcode max value*/</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.dispclk_khz = 681000;</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;</div><div class='del'>-	} else {</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.dispclk_khz = 0;</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.yclk_khz = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dce60_validate_surface_sets(</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='del'>-		if (context-&gt;stream_status[i].plane_count == 0)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (context-&gt;stream_status[i].plane_count &gt; 1)</div><div class='del'>-			return false;</div><div class='del'>-</div><div class='del'>-		if (context-&gt;stream_status[i].plane_states[0]-&gt;format</div><div class='del'>-				&gt;= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='del'>-			return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static enum dc_status dce60_validate_global(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	if (!dce60_validate_surface_sets(context))</div><div class='del'>-		return DC_FAIL_SURFACE_VALIDATE;</div><div class='del'>-</div><div class='del'>-	return DC_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dce60_destroy_resource_pool(struct resource_pool **pool)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);</div><div class='hunk'>@@ -931,10 +902,10 @@ static const struct resource_funcs dce60_res_pool_funcs = {</div><div class='ctx'> 	.destroy = dce60_destroy_resource_pool,</div><div class='ctx'> 	.link_enc_create = dce60_link_encoder_create,</div><div class='ctx'> 	.panel_cntl_create = dce60_panel_cntl_create,</div><div class='del'>-	.validate_bandwidth = dce60_validate_bandwidth,</div><div class='add'>+	.validate_bandwidth = dce100_validate_bandwidth,</div><div class='ctx'> 	.validate_plane = dce100_validate_plane,</div><div class='ctx'> 	.add_stream_to_ctx = dce100_add_stream_to_ctx,</div><div class='del'>-	.validate_global = dce60_validate_global,</div><div class='add'>+	.validate_global = dce100_validate_global,</div><div class='ctx'> 	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -973,21 +944,24 @@ static bool dce60_construct(</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;fw_info_valid &amp;&amp; bp-&gt;fw_info.external_clock_source_frequency_for_dp != 0) {</div><div class='ctx'> 		pool-&gt;base.dp_clock_source =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);</div><div class='ctx'> </div><div class='add'>+		/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */</div><div class='ctx'> 		pool-&gt;base.clock_sources[0] =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &amp;clk_src_regs[0], false);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[1], false);</div><div class='ctx'> 		pool-&gt;base.clock_sources[1] =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[1], false);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &amp;clk_src_regs[2], false);</div><div class='ctx'> 		pool-&gt;base.clk_src_count = 2;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		pool-&gt;base.dp_clock_source =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &amp;clk_src_regs[0], true);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &amp;clk_src_regs[0], true);</div><div class='ctx'> </div><div class='ctx'> 		pool-&gt;base.clock_sources[0] =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[1], false);</div><div class='del'>-		pool-&gt;base.clk_src_count = 1;</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[1], false);</div><div class='add'>+		pool-&gt;base.clock_sources[1] =</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &amp;clk_src_regs[2], false);</div><div class='add'>+		pool-&gt;base.clk_src_count = 2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pool-&gt;base.dp_clock_source == NULL) {</div><div class='hunk'>@@ -1365,21 +1339,24 @@ static bool dce64_construct(</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;fw_info_valid &amp;&amp; bp-&gt;fw_info.external_clock_source_frequency_for_dp != 0) {</div><div class='ctx'> 		pool-&gt;base.dp_clock_source =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);</div><div class='ctx'> </div><div class='add'>+		/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */</div><div class='ctx'> 		pool-&gt;base.clock_sources[0] =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[0], false);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[1], false);</div><div class='ctx'> 		pool-&gt;base.clock_sources[1] =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &amp;clk_src_regs[1], false);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &amp;clk_src_regs[2], false);</div><div class='ctx'> 		pool-&gt;base.clk_src_count = 2;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		pool-&gt;base.dp_clock_source =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[0], true);</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &amp;clk_src_regs[0], true);</div><div class='ctx'> </div><div class='ctx'> 		pool-&gt;base.clock_sources[0] =</div><div class='del'>-				dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &amp;clk_src_regs[1], false);</div><div class='del'>-		pool-&gt;base.clk_src_count = 1;</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &amp;clk_src_regs[1], false);</div><div class='add'>+		pool-&gt;base.clock_sources[1] =</div><div class='add'>+			dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &amp;clk_src_regs[2], false);</div><div class='add'>+		pool-&gt;base.clk_src_count = 2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pool-&gt;base.dp_clock_source == NULL) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h<br/>index 5d653a76b0b0..5d653a76b0b0 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt b/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt<br/>deleted file mode 100644<br/>index 19dd73bc9ab0..000000000000<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,4 +0,0 @@</div><div class='del'>-dal3_subdirectory_sources(</div><div class='del'>-  dce80_resource.c</div><div class='del'>-  dce80_resource.h</div><div class='del'>-  )
\ No newline at end of file</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c<br/>index 35a2cce0c2b8..8687104cabb7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include "stream_encoder.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='ctx'> #include "irq/dce80/irq_service_dce80.h"</div><div class='ctx'> #include "dce110/dce110_timing_generator.h"</div><div class='hunk'>@@ -56,7 +57,6 @@</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='ctx'> #include "dce/dce_abm.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='del'>-/* TODO remove this include */</div><div class='ctx'> </div><div class='ctx'> #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT</div><div class='ctx'> #include "gmc/gmc_7_1_d.h"</div><div class='hunk'>@@ -78,6 +78,7 @@</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #ifndef mmBIOS_SCRATCH_2</div><div class='add'>+	#define mmBIOS_SCRATCH_0 0x05C9</div><div class='ctx'> 	#define mmBIOS_SCRATCH_2 0x05CB</div><div class='ctx'> 	#define mmBIOS_SCRATCH_3 0x05CC</div><div class='ctx'> 	#define mmBIOS_SCRATCH_6 0x05CF</div><div class='hunk'>@@ -241,6 +242,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {</div><div class='ctx'> 	link_regs(4),</div><div class='ctx'> 	link_regs(5),</div><div class='ctx'> 	link_regs(6),</div><div class='add'>+	{ .DAC_ENABLE = mmDAC_ENABLE },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define stream_enc_regs(id)\</div><div class='hunk'>@@ -368,6 +370,7 @@ static const struct dce110_clk_src_mask cs_mask = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct bios_registers bios_regs = {</div><div class='add'>+	.BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,</div><div class='ctx'> 	.BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,</div><div class='ctx'> 	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6</div><div class='ctx'> };</div><div class='hunk'>@@ -375,6 +378,7 @@ static const struct bios_registers bios_regs = {</div><div class='ctx'> static const struct resource_caps res_cap = {</div><div class='ctx'> 		.num_timing_generator = 6,</div><div class='ctx'> 		.num_audio = 6,</div><div class='add'>+		.num_analog_stream_encoder = 1,</div><div class='ctx'> 		.num_stream_encoder = 6,</div><div class='ctx'> 		.num_pll = 3,</div><div class='ctx'> 		.num_ddc = 6,</div><div class='hunk'>@@ -383,6 +387,7 @@ static const struct resource_caps res_cap = {</div><div class='ctx'> static const struct resource_caps res_cap_81 = {</div><div class='ctx'> 		.num_timing_generator = 4,</div><div class='ctx'> 		.num_audio = 7,</div><div class='add'>+		.num_analog_stream_encoder = 1,</div><div class='ctx'> 		.num_stream_encoder = 7,</div><div class='ctx'> 		.num_pll = 3,</div><div class='ctx'> 		.num_ddc = 6,</div><div class='hunk'>@@ -391,6 +396,7 @@ static const struct resource_caps res_cap_81 = {</div><div class='ctx'> static const struct resource_caps res_cap_83 = {</div><div class='ctx'> 		.num_timing_generator = 2,</div><div class='ctx'> 		.num_audio = 6,</div><div class='add'>+		.num_analog_stream_encoder = 1,</div><div class='ctx'> 		.num_stream_encoder = 6,</div><div class='ctx'> 		.num_pll = 2,</div><div class='ctx'> 		.num_ddc = 2,</div><div class='hunk'>@@ -418,8 +424,10 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dc_debug_options debug_defaults = {</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='add'>+static const struct dc_debug_options debug_defaults = { 0 };</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dce_dmcu_registers dmcu_regs = {</div><div class='hunk'>@@ -605,6 +613,11 @@ static struct stream_encoder *dce80_stream_encoder_create(</div><div class='ctx'> 	if (!enc110)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) {</div><div class='add'>+		dce110_analog_stream_encoder_construct(enc110, ctx, ctx-&gt;dc_bios, eng_id);</div><div class='add'>+		return &amp;enc110-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dce110_stream_encoder_construct(enc110, ctx, ctx-&gt;dc_bios, eng_id,</div><div class='ctx'> 					&amp;stream_enc_regs[eng_id],</div><div class='ctx'> 					&amp;se_shift, &amp;se_mask);</div><div class='hunk'>@@ -727,6 +740,19 @@ static struct link_encoder *dce80_link_encoder_create(</div><div class='ctx'> 	if (!enc110)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (enc_init_data-&gt;connector.id == CONNECTOR_ID_VGA) {</div><div class='add'>+		dce110_link_encoder_construct(enc110,</div><div class='add'>+			enc_init_data,</div><div class='add'>+			&amp;link_enc_feature,</div><div class='add'>+			&amp;link_enc_regs[ENGINE_ID_DACA],</div><div class='add'>+			NULL,</div><div class='add'>+			NULL);</div><div class='add'>+		return &amp;enc110-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	link_regs_id =</div><div class='ctx'> 		map_transmitter_id_to_phy_instance(enc_init_data-&gt;transmitter);</div><div class='ctx'> </div><div class='hunk'>@@ -870,61 +896,6 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dce80_validate_bandwidth(</div><div class='del'>-	struct dc *dc,</div><div class='del'>-	struct dc_state *context,</div><div class='del'>-	bool fast_validate)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	bool at_least_one_pipe = false;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		if (context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='del'>-			at_least_one_pipe = true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (at_least_one_pipe) {</div><div class='del'>-		/* TODO implement when needed but for now hardcode max value*/</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.dispclk_khz = 681000;</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;</div><div class='del'>-	} else {</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.dispclk_khz = 0;</div><div class='del'>-		context-&gt;bw_ctx.bw.dce.yclk_khz = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool dce80_validate_surface_sets(</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='del'>-		if (context-&gt;stream_status[i].plane_count == 0)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (context-&gt;stream_status[i].plane_count &gt; 1)</div><div class='del'>-			return false;</div><div class='del'>-</div><div class='del'>-		if (context-&gt;stream_status[i].plane_states[0]-&gt;format</div><div class='del'>-				&gt;= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)</div><div class='del'>-			return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static enum dc_status dce80_validate_global(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	if (!dce80_validate_surface_sets(context))</div><div class='del'>-		return DC_FAIL_SURFACE_VALIDATE;</div><div class='del'>-</div><div class='del'>-	return DC_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dce80_destroy_resource_pool(struct resource_pool **pool)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);</div><div class='hunk'>@@ -938,10 +909,10 @@ static const struct resource_funcs dce80_res_pool_funcs = {</div><div class='ctx'> 	.destroy = dce80_destroy_resource_pool,</div><div class='ctx'> 	.link_enc_create = dce80_link_encoder_create,</div><div class='ctx'> 	.panel_cntl_create = dce80_panel_cntl_create,</div><div class='del'>-	.validate_bandwidth = dce80_validate_bandwidth,</div><div class='add'>+	.validate_bandwidth = dce100_validate_bandwidth,</div><div class='ctx'> 	.validate_plane = dce100_validate_plane,</div><div class='ctx'> 	.add_stream_to_ctx = dce100_add_stream_to_ctx,</div><div class='del'>-	.validate_global = dce80_validate_global,</div><div class='add'>+	.validate_global = dce100_validate_global,</div><div class='ctx'> 	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -974,6 +945,7 @@ static bool dce80_construct(</div><div class='ctx'> 	dc-&gt;caps.dual_link_dvi = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = false;</div><div class='ctx'> 	dc-&gt;debug = debug_defaults;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	/*************************************************</div><div class='ctx'> 	 *  Create resources                             *</div><div class='hunk'>@@ -1375,6 +1347,7 @@ static bool dce83_construct(</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.is_apu = true;</div><div class='ctx'> 	dc-&gt;debug = debug_defaults;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	/*************************************************</div><div class='ctx'> 	 *  Create resources                             *</div><div class='hunk'>@@ -1539,6 +1512,7 @@ struct resource_pool *dce83_create_resource_pool(</div><div class='ctx'> 	if (dce83_construct(num_virtual_links, dc, pool))</div><div class='ctx'> 		return &amp;pool-&gt;base;</div><div class='ctx'> </div><div class='add'>+	kfree(pool);</div><div class='ctx'> 	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c<br/>index d08d10969251..f12367adf145 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include "core_status.h"</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='hunk'>@@ -513,7 +514,7 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 			.argb8888 = true,</div><div class='ctx'> 			.nv12 = true,</div><div class='ctx'> 			.fp16 = true,</div><div class='del'>-			.p010 = true</div><div class='add'>+			.p010 = false</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='ctx'> 	.max_upscale_factor = {</div><div class='hunk'>@@ -533,7 +534,6 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.sanity_checks = true,</div><div class='ctx'> 		.disable_dmcu = false,</div><div class='ctx'> 		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = false,</div><div class='ctx'> 		.clock_trace = true,</div><div class='ctx'> </div><div class='ctx'> 		/* raven smu dones't allow 0 disp clk,</div><div class='hunk'>@@ -556,19 +556,11 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.recovery_enabled = false, /*enable this by default after testing.*/</div><div class='ctx'> 		.max_downscale_src_width = 3840,</div><div class='ctx'> 		.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='ctx'> 		.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dc_debug_options debug_defaults_diags = {</div><div class='del'>-		.disable_dmcu = false,</div><div class='del'>-		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = true,</div><div class='del'>-		.clock_trace = true,</div><div class='del'>-		.disable_stutter = true,</div><div class='del'>-		.disable_pplib_clock_request = true,</div><div class='del'>-		.disable_pplib_wm_range = true,</div><div class='del'>-		.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+		.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void dcn10_dpp_destroy(struct dpp **dpp)</div><div class='hunk'>@@ -750,7 +742,7 @@ static struct link_encoder *dcn10_link_encoder_create(</div><div class='ctx'> 		kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);</div><div class='ctx'> 	int link_regs_id;</div><div class='ctx'> </div><div class='del'>-	if (!enc10)</div><div class='add'>+	if (!enc10 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	link_regs_id =</div><div class='hunk'>@@ -1137,18 +1129,18 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool)</div><div class='ctx'> 	*pool = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dcn10_validate_bandwidth(</div><div class='add'>+static enum dc_status dcn10_validate_bandwidth(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool voltage_supported;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);</div><div class='add'>+	voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	return voltage_supported;</div><div class='add'>+	return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)</div><div class='hunk'>@@ -1257,6 +1249,10 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(</div><div class='ctx'> 			if (link-&gt;ep_type == DISPLAY_ENDPOINT_PHY &amp;&amp; pool-&gt;stream_enc[i]-&gt;id ==</div><div class='ctx'> 					link-&gt;link_enc-&gt;preferred_engine)</div><div class='ctx'> 				return pool-&gt;stream_enc[i];</div><div class='add'>+</div><div class='add'>+			if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA &amp;&amp; pool-&gt;stream_enc[i]-&gt;id ==</div><div class='add'>+					link-&gt;dpia_preferred_eng_id)</div><div class='add'>+				return pool-&gt;stream_enc[i];</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1270,6 +1266,11 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	return pipe_ctx-&gt;pipe_dlg_param.vstartup_start;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct dc_cap_funcs cap_funcs = {</div><div class='ctx'> 	.get_dcc_compression_cap = dcn10_get_dcc_compression_cap</div><div class='ctx'> };</div><div class='hunk'>@@ -1284,7 +1285,8 @@ static const struct resource_funcs dcn10_res_pool_funcs = {</div><div class='ctx'> 	.validate_global = dcn10_validate_global,</div><div class='ctx'> 	.add_stream_to_ctx = dcn10_add_stream_to_ctx,</div><div class='ctx'> 	.patch_unknown_plane_state = dcn10_patch_unknown_plane_state,</div><div class='del'>-	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link</div><div class='add'>+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t read_pipe_fuses(struct dc_context *ctx)</div><div class='hunk'>@@ -1396,11 +1398,11 @@ static bool dcn10_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 0;</div><div class='add'>+	dc-&gt;debug = debug_defaults_drv;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='del'>-	else</div><div class='del'>-		dc-&gt;debug = debug_defaults_diags;</div><div class='ctx'> </div><div class='ctx'> 	/*************************************************</div><div class='ctx'> 	 *  Create resources                             *</div><div class='hunk'>@@ -1631,6 +1633,7 @@ static bool dcn10_resource_construct(</div><div class='ctx'> 	/* valid pipe num */</div><div class='ctx'> 	pool-&gt;base.pipe_count = j;</div><div class='ctx'> 	pool-&gt;base.timing_generator_count = j;</div><div class='add'>+	pool-&gt;base.mpcc_count = j;</div><div class='ctx'> </div><div class='ctx'> 	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,</div><div class='ctx'> 	 * the value may be changed</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h<br/>index bf8e33cd8147..7bc1be53e800 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h</a></div><div class='hunk'>@@ -51,6 +51,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(</div><div class='ctx'> 		const struct resource_pool *pool,</div><div class='ctx'> 		struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='add'>+unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> #endif /* __DC_RESOURCE_DCN10_H__ */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c<br/>index a2387cea1af9..6679c1a14f2f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c</a></div><div class='hunk'>@@ -62,6 +62,9 @@</div><div class='ctx'> #include "dcn20/dcn20_vmid.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='add'>+#include "dcn20/dcn20_dwb.h"</div><div class='add'>+#include "dcn20/dcn20_mmhubbub.h"</div><div class='add'>+</div><div class='ctx'> #include "navi10_ip_offset.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn/dcn_2_0_0_offset.h"</div><div class='hunk'>@@ -71,9 +74,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "nbio/nbio_2_3_offset.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn20/dcn20_dwb.h"</div><div class='del'>-#include "dcn20/dcn20_mmhubbub.h"</div><div class='del'>-</div><div class='ctx'> #include "mmhub/mmhub_2_0_0_offset.h"</div><div class='ctx'> #include "mmhub/mmhub_2_0_0_sh_mask.h"</div><div class='ctx'> </div><div class='hunk'>@@ -83,11 +83,10 @@</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='ctx'> #include "vm_helper.h"</div><div class='del'>-#include "link_enc_cfg.h"</div><div class='ctx'> </div><div class='del'>-#include "amdgpu_socbb.h"</div><div class='add'>+#include "link_enc_cfg.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='ctx'> #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL</div><div class='hunk'>@@ -707,7 +706,6 @@ static const struct resource_caps res_cap_nv14 = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.disable_dmcu = false,</div><div class='ctx'> 		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = false,</div><div class='ctx'> 		.clock_trace = true,</div><div class='ctx'> 		.disable_pplib_clock_request = true,</div><div class='ctx'> 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,</div><div class='hunk'>@@ -720,10 +718,13 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.scl_reset_length10 = true,</div><div class='ctx'> 		.sanity_checks = false,</div><div class='ctx'> 		.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='ctx'> 		.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+		.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> void dcn20_dpp_destroy(struct dpp **dpp)</div><div class='ctx'> {</div><div class='ctx'> 	kfree(TO_DCN20_DPP(*dpp));</div><div class='hunk'>@@ -735,7 +736,7 @@ struct dpp *dcn20_dpp_create(</div><div class='ctx'> 	uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dpp *dpp =</div><div class='del'>-		kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!dpp)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -753,7 +754,7 @@ struct input_pixel_processor *dcn20_ipp_create(</div><div class='ctx'> 	struct dc_context *ctx, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_ipp *ipp =</div><div class='del'>-		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!ipp) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -770,7 +771,7 @@ struct output_pixel_processor *dcn20_opp_create(</div><div class='ctx'> 	struct dc_context *ctx, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_opp *opp =</div><div class='del'>-		kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!opp) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -787,7 +788,7 @@ struct dce_aux *dcn20_aux_engine_create(</div><div class='ctx'> 	uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct aux_engine_dce110 *aux_engine =</div><div class='del'>-		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!aux_engine)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -825,7 +826,7 @@ struct dce_i2c_hw *dcn20_i2c_hw_create(</div><div class='ctx'> 	uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_i2c_hw *dce_i2c_hw =</div><div class='del'>-		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!dce_i2c_hw)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -837,8 +838,7 @@ struct dce_i2c_hw *dcn20_i2c_hw_create(</div><div class='ctx'> }</div><div class='ctx'> struct mpc *dcn20_mpc_create(struct dc_context *ctx)</div><div class='ctx'> {</div><div class='del'>-	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),</div><div class='del'>-					  GFP_ATOMIC);</div><div class='add'>+	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!mpc20)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -855,8 +855,7 @@ struct mpc *dcn20_mpc_create(struct dc_context *ctx)</div><div class='ctx'> struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='del'>-	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),</div><div class='del'>-					  GFP_ATOMIC);</div><div class='add'>+	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!hubbub)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -884,7 +883,7 @@ struct timing_generator *dcn20_timing_generator_create(</div><div class='ctx'> 		uint32_t instance)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *tgn10 =</div><div class='del'>-		kzalloc(sizeof(struct optc), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct optc), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!tgn10)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -921,7 +920,7 @@ struct link_encoder *dcn20_link_encoder_create(</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> 	int link_regs_id;</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	link_regs_id =</div><div class='hunk'>@@ -964,7 +963,7 @@ static struct clock_source *dcn20_clock_source_create(</div><div class='ctx'> 	bool dp_clk_src)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_clk_src *clk_src =</div><div class='del'>-		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!clk_src)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -1063,7 +1062,7 @@ struct display_stream_compressor *dcn20_dsc_create(</div><div class='ctx'> 	struct dc_context *ctx, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_dsc *dsc =</div><div class='del'>-		kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!dsc) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -1200,7 +1199,7 @@ struct hubp *dcn20_hubp_create(</div><div class='ctx'> 	uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_hubp *hubp2 =</div><div class='del'>-		kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!hubp2)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -1222,7 +1221,7 @@ static void get_pixel_clock_parameters(</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 1;</div><div class='ctx'> 	struct dc_link *link = stream-&gt;link;</div><div class='del'>-	struct link_encoder *link_enc = NULL;</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='ctx'> 	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> </div><div class='hunk'>@@ -1231,7 +1230,8 @@ static void get_pixel_clock_parameters(</div><div class='ctx'> </div><div class='ctx'> 	pixel_clk_params-&gt;requested_pix_clk_100hz = stream-&gt;timing.pix_clk_100hz;</div><div class='ctx'> </div><div class='del'>-	link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (!dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='ctx'> 	if (link_enc)</div><div class='ctx'> 		pixel_clk_params-&gt;encoder_object_id = link_enc-&gt;id;</div><div class='ctx'> </div><div class='hunk'>@@ -1252,7 +1252,7 @@ static void get_pixel_clock_parameters(</div><div class='ctx'> </div><div class='ctx'> 	if (opp_cnt == 4)</div><div class='ctx'> 		pixel_clk_params-&gt;requested_pix_clk_100hz /= 4;</div><div class='del'>-	else if (optc2_is_two_pixels_per_containter(&amp;stream-&gt;timing) || opp_cnt == 2)</div><div class='add'>+	else if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;stream-&gt;timing) || opp_cnt == 2)</div><div class='ctx'> 		pixel_clk_params-&gt;requested_pix_clk_100hz /= 2;</div><div class='ctx'> 	else if (hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy) {</div><div class='ctx'> 		if (hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))</div><div class='hunk'>@@ -1262,6 +1262,15 @@ static void get_pixel_clock_parameters(</div><div class='ctx'> 	if (stream-&gt;timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)</div><div class='ctx'> 		pixel_clk_params-&gt;requested_pix_clk_100hz *= 2;</div><div class='ctx'> </div><div class='add'>+	if ((pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container &amp;&amp;</div><div class='add'>+			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;is_two_pixels_per_container(&amp;pipe_ctx-&gt;stream-&gt;timing)) ||</div><div class='add'>+			(hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy &amp;&amp;</div><div class='add'>+			hws-&gt;funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||</div><div class='add'>+			opp_cnt &gt; 1) {</div><div class='add'>+		pixel_clk_params-&gt;dio_se_pix_per_cycle = 2;</div><div class='add'>+	} else {</div><div class='add'>+		pixel_clk_params-&gt;dio_se_pix_per_cycle = 1;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void build_clamping_params(struct dc_stream_state *stream)</div><div class='hunk'>@@ -1282,8 +1291,13 @@ void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> </div><div class='ctx'> static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='add'>+	struct resource_pool *pool = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool;</div><div class='ctx'> </div><div class='del'>-	dcn20_build_pipe_pix_clk_params(pipe_ctx);</div><div class='add'>+	if (pool-&gt;funcs-&gt;build_pipe_pix_clk_params) {</div><div class='add'>+		pool-&gt;funcs-&gt;build_pipe_pix_clk_params(pipe_ctx);</div><div class='add'>+	} else {</div><div class='add'>+		dcn20_build_pipe_pix_clk_params(pipe_ctx);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;clamping.pixel_encoding = pipe_ctx-&gt;stream-&gt;timing.pixel_encoding;</div><div class='ctx'> </div><div class='hunk'>@@ -1497,41 +1511,12 @@ bool dcn20_split_stream_for_odm(</div><div class='ctx'> 	next_odm_pipe-&gt;prev_odm_pipe = prev_odm_pipe;</div><div class='ctx'> </div><div class='ctx'> 	if (prev_odm_pipe-&gt;plane_state) {</div><div class='del'>-		struct scaler_data *sd = &amp;prev_odm_pipe-&gt;plane_res.scl_data;</div><div class='del'>-		int new_width;</div><div class='del'>-</div><div class='del'>-		/* HACTIVE halved for odm combine */</div><div class='del'>-		sd-&gt;h_active /= 2;</div><div class='del'>-		/* Calculate new vp and recout for left pipe */</div><div class='del'>-		/* Need at least 16 pixels width per side */</div><div class='del'>-		if (sd-&gt;recout.x + 16 &gt;= sd-&gt;h_active)</div><div class='del'>-			return false;</div><div class='del'>-		new_width = sd-&gt;h_active - sd-&gt;recout.x;</div><div class='del'>-		sd-&gt;viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(</div><div class='del'>-				sd-&gt;ratios.horz, sd-&gt;recout.width - new_width));</div><div class='del'>-		sd-&gt;viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(</div><div class='del'>-				sd-&gt;ratios.horz_c, sd-&gt;recout.width - new_width));</div><div class='del'>-		sd-&gt;recout.width = new_width;</div><div class='del'>-</div><div class='del'>-		/* Calculate new vp and recout for right pipe */</div><div class='del'>-		sd = &amp;next_odm_pipe-&gt;plane_res.scl_data;</div><div class='del'>-		/* HACTIVE halved for odm combine */</div><div class='del'>-		sd-&gt;h_active /= 2;</div><div class='del'>-		/* Need at least 16 pixels width per side */</div><div class='del'>-		if (new_width &lt;= 16)</div><div class='del'>-			return false;</div><div class='del'>-		new_width = sd-&gt;recout.width + sd-&gt;recout.x - sd-&gt;h_active;</div><div class='del'>-		sd-&gt;viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(</div><div class='del'>-				sd-&gt;ratios.horz, sd-&gt;recout.width - new_width));</div><div class='del'>-		sd-&gt;viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(</div><div class='del'>-				sd-&gt;ratios.horz_c, sd-&gt;recout.width - new_width));</div><div class='del'>-		sd-&gt;recout.width = new_width;</div><div class='del'>-		sd-&gt;viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(</div><div class='del'>-				sd-&gt;ratios.horz, sd-&gt;h_active - sd-&gt;recout.x));</div><div class='del'>-		sd-&gt;viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(</div><div class='del'>-				sd-&gt;ratios.horz_c, sd-&gt;h_active - sd-&gt;recout.x));</div><div class='del'>-		sd-&gt;recout.x = 0;</div><div class='add'>+		if (!resource_build_scaling_params(prev_odm_pipe) ||</div><div class='add'>+			!resource_build_scaling_params(next_odm_pipe)) {</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	if (!next_odm_pipe-&gt;top_pipe)</div><div class='ctx'> 		next_odm_pipe-&gt;stream_res.opp = pool-&gt;opps[next_odm_pipe-&gt;pipe_idx];</div><div class='ctx'> 	else</div><div class='hunk'>@@ -1599,7 +1584,7 @@ unsigned int dcn20_calc_max_scaled_time(</div><div class='ctx'> 	if (time_per_byte == 0)</div><div class='ctx'> 		time_per_byte = 1;</div><div class='ctx'> </div><div class='del'>-	small_free_entry  = (total_y_free_entry &gt; total_c_free_entry) ? total_c_free_entry : total_y_free_entry;</div><div class='add'>+	small_free_entry  = total_c_free_entry;</div><div class='ctx'> 	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;</div><div class='ctx'> 	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */</div><div class='ctx'> 	max_scaled_time   = buf_lh_capability - urgent_watermark;</div><div class='hunk'>@@ -1653,8 +1638,6 @@ void dcn20_set_mcif_arb_params(</div><div class='ctx'> 			if (dwb_pipe &gt;= MAX_DWB_PIPES)</div><div class='ctx'> 				return;</div><div class='ctx'> 		}</div><div class='del'>-		if (dwb_pipe &gt;= MAX_DWB_PIPES)</div><div class='del'>-			return;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1686,6 +1669,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)</div><div class='ctx'> 		dsc_cfg.is_odm = pipe_ctx-&gt;next_odm_pipe ? true : false;</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg = stream-&gt;timing.dsc_cfg;</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;</div><div class='add'>+		dsc_cfg.dsc_padding = pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding;</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe_ctx-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_validate_stream(pipe_ctx-&gt;stream_res.dsc, &amp;dsc_cfg))</div><div class='ctx'> 			return false;</div><div class='hunk'>@@ -2025,10 +2009,11 @@ bool dcn20_fast_validate_bw(</div><div class='ctx'> 		int *pipe_cnt_out,</div><div class='ctx'> 		int *pipe_split_from,</div><div class='ctx'> 		int *vlevel_out,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> 	int split[MAX_PIPES] = { 0 };</div><div class='add'>+	bool merge[MAX_PIPES] = { false };</div><div class='ctx'> 	int pipe_cnt, i, pipe_idx, vlevel;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(pipes);</div><div class='hunk'>@@ -2038,7 +2023,7 @@ bool dcn20_fast_validate_bw(</div><div class='ctx'> 	dcn20_merge_pipes_for_validate(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='add'>+	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	*pipe_cnt_out = pipe_cnt;</div><div class='hunk'>@@ -2053,7 +2038,7 @@ bool dcn20_fast_validate_bw(</div><div class='ctx'> 	if (vlevel &gt; context-&gt;bw_ctx.dml.soc.num_states)</div><div class='ctx'> 		goto validate_fail;</div><div class='ctx'> </div><div class='del'>-	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);</div><div class='add'>+	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);</div><div class='ctx'> </div><div class='ctx'> 	/*initialize pipe_just_split_from to invalid idx*/</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++)</div><div class='hunk'>@@ -2121,6 +2106,7 @@ bool dcn20_fast_validate_bw(</div><div class='ctx'> 			ASSERT(0);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	/* Actual dsc count per stream dsc validation*/</div><div class='ctx'> 	if (!dcn20_validate_dsc(dc, context)) {</div><div class='ctx'> 		context-&gt;bw_ctx.dml.vba.ValidationStatus[context-&gt;bw_ctx.dml.vba.soc.num_states] =</div><div class='hunk'>@@ -2140,22 +2126,22 @@ validate_out:</div><div class='ctx'> 	return out;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool voltage_supported;</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes;</div><div class='ctx'> </div><div class='ctx'> 	pipes = kcalloc(dc-&gt;res_pool-&gt;pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='ctx'> 	if (!pipes)</div><div class='del'>-		return false;</div><div class='add'>+		return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);</div><div class='add'>+	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, validate_mode, pipes);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	kfree(pipes);</div><div class='del'>-	return voltage_supported;</div><div class='add'>+	return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(</div><div class='hunk'>@@ -2189,10 +2175,11 @@ bool dcn20_get_dcc_compression_cap(const struct dc *dc,</div><div class='ctx'> 		const struct dc_dcc_surface_param *input,</div><div class='ctx'> 		struct dc_surface_dcc_cap *output)</div><div class='ctx'> {</div><div class='del'>-	return dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;get_dcc_compression_cap(</div><div class='del'>-			dc-&gt;res_pool-&gt;hubbub,</div><div class='del'>-			input,</div><div class='del'>-			output);</div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;get_dcc_compression_cap)</div><div class='add'>+		return dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;get_dcc_compression_cap(</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub, input, output);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn20_destroy_resource_pool(struct resource_pool **pool)</div><div class='hunk'>@@ -2245,7 +2232,8 @@ static const struct resource_funcs dcn20_res_pool_funcs = {</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,</div><div class='ctx'> 	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,</div><div class='del'>-	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link</div><div class='add'>+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)</div><div class='hunk'>@@ -2300,7 +2288,7 @@ bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)</div><div class='ctx'> </div><div class='ctx'> static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)</div><div class='ctx'> {</div><div class='del'>-	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);</div><div class='add'>+	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!pp_smu)</div><div class='ctx'> 		return pp_smu;</div><div class='hunk'>@@ -2336,7 +2324,6 @@ static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(</div><div class='ctx'> static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(</div><div class='ctx'> 	uint32_t hw_internal_rev)</div><div class='ctx'> {</div><div class='del'>-	/* NV14 */</div><div class='ctx'> 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))</div><div class='ctx'> 		return &amp;dcn2_0_nv14_ip;</div><div class='ctx'> </div><div class='hunk'>@@ -2449,6 +2436,7 @@ static bool dcn20_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.post_blend_color_processing = true;</div><div class='ctx'> 	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='add'>+	dc-&gt;caps.dmcub_support = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -2486,6 +2474,7 @@ static bool dcn20_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;caps.dp_hdmi21_pcon_support = true;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2617,7 +2606,7 @@ static bool dcn20_resource_construct(</div><div class='ctx'> 		ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;</div><div class='ctx'> </div><div class='ctx'> 		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */</div><div class='del'>-		if (pool-&gt;base.pp_smu-&gt;nv_funcs.set_wm_ranges)</div><div class='add'>+		if (pool-&gt;base.pp_smu &amp;&amp; pool-&gt;base.pp_smu-&gt;nv_funcs.set_wm_ranges)</div><div class='ctx'> 			pool-&gt;base.pp_smu-&gt;nv_funcs.set_wm_ranges(&amp;pool-&gt;base.pp_smu-&gt;nv_funcs.pp_smu, &amp;ranges);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2750,6 +2739,8 @@ static bool dcn20_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 2;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='hunk'>@@ -2777,7 +2768,7 @@ struct resource_pool *dcn20_create_resource_pool(</div><div class='ctx'> 		struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_resource_pool *pool =</div><div class='del'>-		kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!pool)</div><div class='ctx'> 		return NULL;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h<br/>index 4cee3fa11a7f..e997d35a8b86 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h</a></div><div class='hunk'>@@ -119,7 +119,7 @@ void dcn20_set_mcif_arb_params(</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 		int pipe_cnt);</div><div class='del'>-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);</div><div class='add'>+enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);</div><div class='ctx'> void dcn20_merge_pipes_for_validate(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context);</div><div class='hunk'>@@ -158,7 +158,7 @@ bool dcn20_fast_validate_bw(</div><div class='ctx'> 		int *pipe_cnt_out,</div><div class='ctx'> 		int *pipe_split_from,</div><div class='ctx'> 		int *vlevel_out,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);</div><div class='ctx'> enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c<br/>index 914b234d7f6b..055107843a70 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c</a></div><div class='hunk'>@@ -55,13 +55,12 @@</div><div class='ctx'> #include "dce110/dce110_resource.h"</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='del'>-#include "dcn201/dcn201_hubbub.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> </div><div class='ctx'> #include "cyan_skillfish_ip_offset.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn/dcn_2_0_3_offset.h"</div><div class='del'>-#include "dcn/dcn_2_0_3_sh_mask.h"</div><div class='add'>+#include "dcn/dcn_2_0_1_offset.h"</div><div class='add'>+#include "dcn/dcn_2_0_1_sh_mask.h"</div><div class='ctx'> #include "dpcs/dpcs_2_0_3_offset.h"</div><div class='ctx'> #include "dpcs/dpcs_2_0_3_sh_mask.h"</div><div class='ctx'> </div><div class='hunk'>@@ -182,6 +181,7 @@ static struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {</div><div class='ctx'> 				.socclk_mhz = 1254.0,</div><div class='ctx'> 				.dram_speed_mts = 14000.0,</div><div class='ctx'> 			},</div><div class='add'>+			/* state4 is not an actual state, just defines unsupported for dml*/</div><div class='ctx'> 			{</div><div class='ctx'> 				.state = 4,</div><div class='ctx'> 				.dscclk_mhz = 400.0,</div><div class='hunk'>@@ -566,6 +566,8 @@ static const struct resource_caps res_cap_dnc201 = {</div><div class='ctx'> 		.num_audio = 2,</div><div class='ctx'> 		.num_stream_encoder = 2,</div><div class='ctx'> 		.num_pll = 2,</div><div class='add'>+		.num_dwb = 0,</div><div class='add'>+		.num_dsc = 0,</div><div class='ctx'> 		.num_ddc = 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -598,7 +600,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.disable_dmcu = true,</div><div class='ctx'> 		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = false,</div><div class='ctx'> 		.clock_trace = true,</div><div class='ctx'> 		.disable_pplib_clock_request = true,</div><div class='ctx'> 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,</div><div class='hunk'>@@ -612,11 +613,14 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.scl_reset_length10 = true,</div><div class='ctx'> 		.sanity_checks = false,</div><div class='ctx'> 		.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='del'>-		.enable_tri_buf = false,</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='add'>+		.enable_tri_buf = true,</div><div class='ctx'> 		.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+		.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void dcn201_dpp_destroy(struct dpp **dpp)</div><div class='ctx'> {</div><div class='ctx'> 	kfree(TO_DCN201_DPP(*dpp));</div><div class='hunk'>@@ -628,7 +632,7 @@ static struct dpp *dcn201_dpp_create(</div><div class='ctx'> 	uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn201_dpp *dpp =</div><div class='del'>-		kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn201_dpp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!dpp)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -645,7 +649,7 @@ static struct input_pixel_processor *dcn201_ipp_create(</div><div class='ctx'> 	struct dc_context *ctx, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_ipp *ipp =</div><div class='del'>-		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!ipp) {</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -661,7 +665,7 @@ static struct output_pixel_processor *dcn201_opp_create(</div><div class='ctx'> 	struct dc_context *ctx, uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn201_opp *opp =</div><div class='del'>-		kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn201_opp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!opp) {</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -676,7 +680,7 @@ static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,</div><div class='ctx'> 						uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct aux_engine_dce110 *aux_engine =</div><div class='del'>-		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!aux_engine)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -709,7 +713,7 @@ static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,</div><div class='ctx'> 					       uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_i2c_hw *dce_i2c_hw =</div><div class='del'>-		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!dce_i2c_hw)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -722,8 +726,7 @@ static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,</div><div class='ctx'> </div><div class='ctx'> static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)</div><div class='ctx'> {</div><div class='del'>-	struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc),</div><div class='del'>-					    GFP_ATOMIC);</div><div class='add'>+	struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!mpc201)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -739,8 +742,7 @@ static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)</div><div class='ctx'> </div><div class='ctx'> static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)</div><div class='ctx'> {</div><div class='del'>-	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),</div><div class='del'>-					  GFP_ATOMIC);</div><div class='add'>+	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!hubbub)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -758,7 +760,7 @@ static struct timing_generator *dcn201_timing_generator_create(</div><div class='ctx'> 		uint32_t instance)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *tgn10 =</div><div class='del'>-		kzalloc(sizeof(struct optc), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct optc), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!tgn10)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -792,12 +794,14 @@ static struct link_encoder *dcn201_link_encoder_create(</div><div class='ctx'> 	const struct encoder_init_data *enc_init_data)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='del'>-		kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);</div><div class='del'>-	struct dcn10_link_encoder *enc10 = &amp;enc20-&gt;enc10;</div><div class='add'>+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='add'>+	struct dcn10_link_encoder *enc10;</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	enc10 = &amp;enc20-&gt;enc10;</div><div class='add'>+</div><div class='ctx'> 	dcn201_link_encoder_construct(enc20,</div><div class='ctx'> 			enc_init_data,</div><div class='ctx'> 			&amp;link_enc_feature,</div><div class='hunk'>@@ -818,7 +822,7 @@ static struct clock_source *dcn201_clock_source_create(</div><div class='ctx'> 	bool dp_clk_src)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce110_clk_src *clk_src =</div><div class='del'>-		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!clk_src)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -853,7 +857,7 @@ static struct stream_encoder *dcn201_stream_encoder_create(</div><div class='ctx'> 	struct dc_context *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn10_stream_encoder *enc1 =</div><div class='del'>-		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!enc1)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -880,7 +884,7 @@ static const struct dce_hwseq_mask hwseq_mask = {</div><div class='ctx'> static struct dce_hwseq *dcn201_hwseq_create(</div><div class='ctx'> 	struct dc_context *ctx)</div><div class='ctx'> {</div><div class='del'>-	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC);</div><div class='add'>+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (hws) {</div><div class='ctx'> 		hws-&gt;ctx = ctx;</div><div class='hunk'>@@ -980,7 +984,7 @@ static struct hubp *dcn201_hubp_create(</div><div class='ctx'> 	uint32_t inst)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn201_hubp *hubp201 =</div><div class='del'>-		kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn201_hubp), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!hubp201)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -1003,8 +1007,10 @@ static struct pipe_ctx *dcn201_acquire_free_pipe_for_layer(</div><div class='ctx'> 	struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe-&gt;stream);</div><div class='ctx'> 	struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);</div><div class='ctx'> </div><div class='del'>-	if (!head_pipe)</div><div class='add'>+	if (!head_pipe) {</div><div class='ctx'> 		ASSERT(0);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (!idle_pipe)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -1074,7 +1080,8 @@ static struct resource_funcs dcn201_res_pool_funcs = {</div><div class='ctx'> 	.populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,</div><div class='del'>-	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link</div><div class='add'>+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn201_resource_construct(</div><div class='hunk'>@@ -1147,6 +1154,7 @@ static bool dcn201_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;debug = debug_defaults_drv;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	/*a0 only, remove later*/</div><div class='ctx'> 	dc-&gt;work_arounds.no_connect_phy_config  = true;</div><div class='hunk'>@@ -1279,6 +1287,8 @@ static bool dcn201_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 2;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -1295,7 +1305,7 @@ struct resource_pool *dcn201_create_resource_pool(</div><div class='ctx'> 		struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn201_resource_pool *pool =</div><div class='del'>-		kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC);</div><div class='add'>+		kzalloc(sizeof(struct dcn201_resource_pool), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!pool)</div><div class='ctx'> 		return NULL;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c<br/>index 65d337731f56..2060acd5ae09 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c</a></div><div class='hunk'>@@ -581,32 +581,6 @@ static const struct resource_caps res_cap_rn = {</div><div class='ctx'> 		.num_dsc = 3,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#ifdef DIAGS_BUILD</div><div class='del'>-static const struct resource_caps res_cap_rn_FPGA_4pipe = {</div><div class='del'>-		.num_timing_generator = 4,</div><div class='del'>-		.num_opp = 4,</div><div class='del'>-		.num_video_plane = 4,</div><div class='del'>-		.num_audio = 7,</div><div class='del'>-		.num_stream_encoder = 4,</div><div class='del'>-		.num_pll = 4,</div><div class='del'>-		.num_dwb = 1,</div><div class='del'>-		.num_ddc = 4,</div><div class='del'>-		.num_dsc = 0,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {</div><div class='del'>-		.num_timing_generator = 2,</div><div class='del'>-		.num_opp = 2,</div><div class='del'>-		.num_video_plane = 2,</div><div class='del'>-		.num_audio = 7,</div><div class='del'>-		.num_stream_encoder = 2,</div><div class='del'>-		.num_pll = 4,</div><div class='del'>-		.num_dwb = 1,</div><div class='del'>-		.num_ddc = 4,</div><div class='del'>-		.num_dsc = 2,</div><div class='del'>-};</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,</div><div class='ctx'> 	.per_pixel_alpha = true,</div><div class='hunk'>@@ -636,7 +610,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.disable_dmcu = false,</div><div class='ctx'> 		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = false,</div><div class='ctx'> 		.clock_trace = true,</div><div class='ctx'> 		.disable_pplib_clock_request = true,</div><div class='ctx'> 		.min_disp_clk_khz = 100000,</div><div class='hunk'>@@ -653,10 +626,13 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.usbc_combo_phy_reset_wa = true,</div><div class='ctx'> 		.dmub_command_table = true,</div><div class='ctx'> 		.use_max_lb = true,</div><div class='del'>-		.enable_legacy_fast_update = true,</div><div class='ctx'> 		.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+		.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 		.psr = {</div><div class='ctx'> 			.disable_psr = false,</div><div class='hunk'>@@ -796,10 +772,11 @@ bool dcn21_fast_validate_bw(struct dc *dc,</div><div class='ctx'> 			    int *pipe_cnt_out,</div><div class='ctx'> 			    int *pipe_split_from,</div><div class='ctx'> 			    int *vlevel_out,</div><div class='del'>-			    bool fast_validate)</div><div class='add'>+			    enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> 	int split[MAX_PIPES] = { 0 };</div><div class='add'>+	bool merge[MAX_PIPES] = { false };</div><div class='ctx'> 	int pipe_cnt, i, pipe_idx, vlevel;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(pipes);</div><div class='hunk'>@@ -809,7 +786,7 @@ bool dcn21_fast_validate_bw(struct dc *dc,</div><div class='ctx'> 	dcn20_merge_pipes_for_validate(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='add'>+	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	*pipe_cnt_out = pipe_cnt;</div><div class='hunk'>@@ -842,7 +819,7 @@ bool dcn21_fast_validate_bw(struct dc *dc,</div><div class='ctx'> 			goto validate_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);</div><div class='add'>+	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -949,22 +926,22 @@ validate_out:</div><div class='ctx'>  * with DC_FP_START()/DC_FP_END(). Use the same approach as for</div><div class='ctx'>  * dcn20_validate_bandwidth in dcn20_resource.c.</div><div class='ctx'>  */</div><div class='del'>-static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool voltage_supported;</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes;</div><div class='ctx'> </div><div class='ctx'> 	pipes = kcalloc(dc-&gt;res_pool-&gt;pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='ctx'> 	if (!pipes)</div><div class='del'>-		return false;</div><div class='add'>+		return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);</div><div class='add'>+	voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	kfree(pipes);</div><div class='del'>-	return voltage_supported;</div><div class='add'>+	return voltage_supported ? DC_OK : DC_NOT_SUPPORTED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn21_destroy_resource_pool(struct resource_pool **pool)</div><div class='hunk'>@@ -1323,7 +1300,7 @@ static struct link_encoder *dcn21_link_encoder_create(</div><div class='ctx'> 		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);</div><div class='ctx'> 	int link_regs_id;</div><div class='ctx'> </div><div class='del'>-	if (!enc21)</div><div class='add'>+	if (!enc21 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	link_regs_id =</div><div class='hunk'>@@ -1404,6 +1381,7 @@ static const struct resource_funcs dcn21_res_pool_funcs = {</div><div class='ctx'> 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,</div><div class='ctx'> 	.update_bw_bounding_box = dcn21_update_bw_bounding_box,</div><div class='ctx'> 	.get_panel_config_defaults = dcn21_get_panel_config_defaults,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn21_resource_construct(</div><div class='hunk'>@@ -1415,16 +1393,11 @@ static bool dcn21_resource_construct(</div><div class='ctx'> 	struct dc_context *ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct irq_service_init_data init_data;</div><div class='ctx'> 	uint32_t pipe_fuses = read_pipe_fuses(ctx);</div><div class='del'>-	uint32_t num_pipes;</div><div class='add'>+	uint32_t num_pipes = 0;</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;dc_bios-&gt;regs = &amp;bios_regs;</div><div class='ctx'> </div><div class='ctx'> 	pool-&gt;base.res_cap = &amp;res_cap_rn;</div><div class='del'>-#ifdef DIAGS_BUILD</div><div class='del'>-	if (IS_FPGA_MAXIMUS_DC(dc-&gt;ctx-&gt;dce_environment))</div><div class='del'>-		//pool-&gt;base.res_cap = &amp;res_cap_nv10_FPGA_2pipe_dsc;</div><div class='del'>-		pool-&gt;base.res_cap = &amp;res_cap_rn_FPGA_4pipe;</div><div class='del'>-#endif</div><div class='ctx'> </div><div class='ctx'> 	pool-&gt;base.funcs = &amp;dcn21_res_pool_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -1443,9 +1416,9 @@ static bool dcn21_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;caps.max_slave_planes = 1;</div><div class='del'>-	dc-&gt;caps.max_slave_yuv_planes = 1;</div><div class='del'>-	dc-&gt;caps.max_slave_rgb_planes = 1;</div><div class='add'>+	dc-&gt;caps.max_slave_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_yuv_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_rgb_planes = 3;</div><div class='ctx'> 	dc-&gt;caps.post_blend_color_processing = true;</div><div class='ctx'> 	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='hunk'>@@ -1488,6 +1461,7 @@ static bool dcn21_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;caps.dp_hdmi21_pcon_support = true;</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -1714,6 +1688,8 @@ static bool dcn21_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 2;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h<br/>index f7ecc002c2f7..a017fd9854d1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h</a></div><div class='hunk'>@@ -51,6 +51,6 @@ bool dcn21_fast_validate_bw(</div><div class='ctx'> 		int *pipe_cnt_out,</div><div class='ctx'> 		int *pipe_split_from,</div><div class='ctx'> 		int *vlevel_out,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> #endif /* _DCN21_RESOURCE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c<br/>index ecc477ef8e3b..d0ebb733e802 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c</a></div><div class='hunk'>@@ -60,7 +60,7 @@</div><div class='ctx'> #include "dml/display_mode_vba.h"</div><div class='ctx'> #include "dcn30/dcn30_dccg.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn30/dcn30_dwb.h"</div><div class='hunk'>@@ -711,7 +711,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true, //No DMCU on DCN30</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = true,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,</div><div class='hunk'>@@ -728,10 +727,13 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.dmub_command_table = true,</div><div class='ctx'> 	.use_max_lb = true,</div><div class='ctx'> 	.exit_idle_opt_for_cursor_updates = true,</div><div class='del'>-	.enable_legacy_fast_update = false,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 	.psr = {</div><div class='ctx'> 		.disable_psr = false,</div><div class='hunk'>@@ -927,7 +929,7 @@ static struct link_encoder *dcn30_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn30_link_encoder_construct(enc20,</div><div class='hunk'>@@ -1320,13 +1322,13 @@ static struct clock_source *dcn30_clock_source_create(</div><div class='ctx'> int dcn30_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -1419,10 +1421,7 @@ void dcn30_set_mcif_arb_params(</div><div class='ctx'> 			if (dwb_pipe &gt;= MAX_DWB_PIPES)</div><div class='ctx'> 				return;</div><div class='ctx'> 		}</div><div class='del'>-		if (dwb_pipe &gt;= MAX_DWB_PIPES)</div><div class='del'>-			return;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct dc_cap_funcs cap_funcs = {</div><div class='hunk'>@@ -1631,7 +1630,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 		int *pipe_cnt_out,</div><div class='ctx'> 		int *vlevel_out,</div><div class='del'>-		bool fast_validate,</div><div class='add'>+		enum dc_validate_mode validate_mode,</div><div class='ctx'> 		bool allow_self_refresh_only)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='hunk'>@@ -1639,7 +1638,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 	int split[MAX_PIPES] = { 0 };</div><div class='ctx'> 	bool merge[MAX_PIPES] = { false };</div><div class='ctx'> 	bool newly_split[MAX_PIPES] = { false };</div><div class='del'>-	int pipe_cnt, i, pipe_idx, vlevel;</div><div class='add'>+	int pipe_cnt, i, pipe_idx, vlevel = 0;</div><div class='ctx'> 	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(pipes);</div><div class='hunk'>@@ -1650,7 +1649,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 	context-&gt;bw_ctx.dml.vba.VoltageLevel = 0;</div><div class='ctx'> 	context-&gt;bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;</div><div class='ctx'> 	dc-&gt;res_pool-&gt;funcs-&gt;update_soc_for_wm_a(dc, context);</div><div class='del'>-	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='add'>+	pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	if (!pipe_cnt) {</div><div class='ctx'> 		out = true;</div><div class='hunk'>@@ -1659,7 +1658,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> </div><div class='ctx'> 	dml_log_pipe_params(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='ctx'> </div><div class='del'>-	if (!fast_validate || !allow_self_refresh_only) {</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING || !allow_self_refresh_only) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * DML favors voltage over p-state, but we're more interested in</div><div class='ctx'> 		 * supporting p-state over voltage. We can't support p-state in</div><div class='hunk'>@@ -1673,7 +1672,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (allow_self_refresh_only &amp;&amp;</div><div class='del'>-	    (fast_validate || vlevel == context-&gt;bw_ctx.dml.soc.num_states ||</div><div class='add'>+	    (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context-&gt;bw_ctx.dml.soc.num_states ||</div><div class='ctx'> 			vba-&gt;DRAMClockChangeSupport[vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_unsupported)) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * If mode is unsupported or there's still no p-state support</div><div class='hunk'>@@ -1682,7 +1681,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 		 * We don't actually support prefetch mode 2, so require that we</div><div class='ctx'> 		 * at least support prefetch mode 1.</div><div class='ctx'> 		 */</div><div class='del'>-		context-&gt;bw_ctx.dml.validate_max_state = fast_validate;</div><div class='add'>+		context-&gt;bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);</div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =</div><div class='ctx'> 			dm_allow_self_refresh;</div><div class='ctx'> </div><div class='hunk'>@@ -1869,7 +1868,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (repopulate_pipes)</div><div class='del'>-		pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='add'>+		pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, validate_mode);</div><div class='ctx'> 	context-&gt;bw_ctx.dml.vba.VoltageLevel = vlevel;</div><div class='ctx'> 	*vlevel_out = vlevel;</div><div class='ctx'> 	*pipe_cnt_out = pipe_cnt;</div><div class='hunk'>@@ -1895,8 +1894,6 @@ static int get_refresh_rate(struct dc_state *context)</div><div class='ctx'> </div><div class='ctx'> 	/* check if refresh rate at least 120hz */</div><div class='ctx'> 	timing = &amp;context-&gt;streams[0]-&gt;timing;</div><div class='del'>-	if (timing == NULL)</div><div class='del'>-		return 0;</div><div class='ctx'> </div><div class='ctx'> 	h_v_total = timing-&gt;h_total * timing-&gt;v_total;</div><div class='ctx'> 	if (h_v_total == 0)</div><div class='hunk'>@@ -1966,6 +1963,7 @@ bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	int refresh_rate = 0;</div><div class='ctx'> 	const int minimum_refreshrate_supported = 120;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (context == NULL || context-&gt;streams[0] == NULL)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -1996,10 +1994,15 @@ bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc,</div><div class='ctx'> 	if (!context-&gt;streams[0]-&gt;allow_freesync)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (context-&gt;streams[0]-&gt;vrr_active_variable &amp;&amp; dc-&gt;debug.disable_fams_gaming)</div><div class='add'>+	if (context-&gt;streams[0]-&gt;vrr_active_variable &amp;&amp; (dc-&gt;debug.disable_fams_gaming == INGAME_FAMS_DISABLE))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	context-&gt;streams[0]-&gt;fpo_in_use = true;</div><div class='add'>+	stream_status = dc_state_get_stream_status(context, context-&gt;streams[0]);</div><div class='add'>+</div><div class='add'>+	if (!stream_status)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	stream_status-&gt;fpo_in_use = true;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -2035,9 +2038,9 @@ void dcn30_calculate_wm_and_dlg(</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dcn30_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn30_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='hunk'>@@ -2045,13 +2048,17 @@ bool dcn30_validate_bandwidth(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	int vlevel = 0;</div><div class='ctx'> 	int pipe_cnt = 0;</div><div class='del'>-	display_e2e_pipe_params_st *pipes = kzalloc(dc-&gt;res_pool-&gt;pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='add'>+	display_e2e_pipe_params_st *pipes = kcalloc(dc-&gt;res_pool-&gt;pipe_count,</div><div class='add'>+			sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_COUNT();</div><div class='ctx'> </div><div class='add'>+	if (!pipes)</div><div class='add'>+		goto validate_fail;</div><div class='add'>+</div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	out = dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, fast_validate, true);</div><div class='add'>+	out = dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, validate_mode, true);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='hunk'>@@ -2062,7 +2069,7 @@ bool dcn30_validate_bandwidth(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2088,7 +2095,7 @@ validate_out:</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_FINISH();</div><div class='ctx'> </div><div class='del'>-	return out;</div><div class='add'>+	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='hunk'>@@ -2188,7 +2195,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params</div><div class='ctx'> 		j = 0;</div><div class='ctx'> 		// create the final dcfclk and uclk table</div><div class='ctx'> 		while (i &lt; num_dcfclk_sta_targets &amp;&amp; j &lt; num_uclk_states &amp;&amp; num_states &lt; DC__VOLTAGE_STATES) {</div><div class='del'>-			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j] &amp;&amp; i &lt; num_dcfclk_sta_targets) {</div><div class='add'>+			if (dcfclk_sta_targets[i] &lt; optimal_dcfclk_for_uclk[j]) {</div><div class='ctx'> 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];</div><div class='ctx'> 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -2245,6 +2252,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = {</div><div class='ctx'> 	.update_bw_bounding_box = dcn30_update_bw_bounding_box,</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn30_get_panel_config_defaults,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define CTX ctx</div><div class='hunk'>@@ -2348,6 +2356,7 @@ static bool dcn30_resource_construct(</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;caps.dp_hdmi21_pcon_support = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='hunk'>@@ -2368,6 +2377,7 @@ static bool dcn30_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) &amp;&amp; !!is_vbios_interop_enabled;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2567,7 +2577,7 @@ static bool dcn30_resource_construct(</div><div class='ctx'> 		pool-&gt;base.sw_i2cs[i] = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */</div><div class='add'>+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */</div><div class='ctx'> 	if (!resource_construct(num_virtual_links, dc, &amp;pool-&gt;base,</div><div class='ctx'> 			&amp;res_create_funcs))</div><div class='ctx'> 		goto create_fail;</div><div class='hunk'>@@ -2580,6 +2590,8 @@ static bool dcn30_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h<br/>index 8e6b8b7368fd..2c967fe55712 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h</a></div><div class='hunk'>@@ -56,15 +56,15 @@ unsigned int dcn30_calc_max_scaled_time(</div><div class='ctx'> 		enum mmhubbub_wbif_mode mode,</div><div class='ctx'> 		unsigned int urgent_watermark);</div><div class='ctx'> </div><div class='del'>-bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> bool dcn30_internal_validate_bw(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 		int *pipe_cnt_out,</div><div class='ctx'> 		int *vlevel_out,</div><div class='del'>-		bool fast_validate,</div><div class='add'>+		enum dc_validate_mode validate_mode,</div><div class='ctx'> 		bool allow_self_refresh_only);</div><div class='ctx'> void dcn30_calculate_wm_and_dlg(</div><div class='ctx'> 		struct dc *dc, struct dc_state *context,</div><div class='hunk'>@@ -78,7 +78,7 @@ void dcn30_populate_dml_writeback_from_context(</div><div class='ctx'> int dcn30_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate);</div><div class='add'>+	enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> bool dcn30_acquire_post_bldn_3dlut(</div><div class='ctx'> 		struct resource_context *res_ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c<br/>index 7538b548c572..3ad6a3d4858e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c</a></div><div class='hunk'>@@ -671,9 +671,9 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> </div><div class='ctx'> 	/* 6:1 downscaling ratio: 1000/6 = 166.666 */</div><div class='ctx'> 	.max_downscale_factor = {</div><div class='del'>-			.argb8888 = 167,</div><div class='del'>-			.nv12 = 167,</div><div class='del'>-			.fp16 = 167 </div><div class='add'>+			.argb8888 = 358,</div><div class='add'>+			.nv12 = 358,</div><div class='add'>+			.fp16 = 358</div><div class='ctx'> 	},</div><div class='ctx'> 	64,</div><div class='ctx'> 	64</div><div class='hunk'>@@ -682,7 +682,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_dpp_power_gate = false,</div><div class='ctx'> 	.disable_hubp_power_gate = false,</div><div class='hunk'>@@ -694,7 +693,7 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dcc = DCC_ENABLE,</div><div class='ctx'> 	.vsr_support = true,</div><div class='ctx'> 	.performance_trace = false,</div><div class='del'>-	.max_downscale_src_width = 7680,/*upto 8K*/</div><div class='add'>+	.max_downscale_src_width = 4096,/*upto true 4k*/</div><div class='ctx'> 	.scl_reset_length10 = true,</div><div class='ctx'> 	.sanity_checks = false,</div><div class='ctx'> 	.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='hunk'>@@ -705,6 +704,10 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void dcn301_dpp_destroy(struct dpp **dpp)</div><div class='ctx'> {</div><div class='ctx'> 	kfree(TO_DCN20_DPP(*dpp));</div><div class='hunk'>@@ -882,7 +885,7 @@ static struct link_encoder *dcn301_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn301_link_encoder_construct(enc20,</div><div class='hunk'>@@ -1363,14 +1366,21 @@ static void set_wm_ranges(</div><div class='ctx'> 	pp_smu-&gt;nv_funcs.set_wm_ranges(&amp;pp_smu-&gt;nv_funcs.pp_smu, &amp;ranges);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn301_calculate_wm_and_dlg(</div><div class='del'>-		struct dc *dc, struct dc_state *context,</div><div class='del'>-		display_e2e_pipe_params_st *pipes,</div><div class='del'>-		int pipe_cnt,</div><div class='del'>-		int vlevel)</div><div class='add'>+static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='add'>+{</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	dcn301_fpu_update_bw_bounding_box(dc, bw_params);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn301_calculate_wm_and_dlg(struct dc *dc,</div><div class='add'>+					struct dc_state *context,</div><div class='add'>+					display_e2e_pipe_params_st *pipes,</div><div class='add'>+					int pipe_cnt,</div><div class='add'>+					int vlevel_req)</div><div class='ctx'> {</div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);</div><div class='add'>+	dcn301_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel_req);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1393,7 +1403,8 @@ static struct resource_funcs dcn301_res_pool_funcs = {</div><div class='ctx'> 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,</div><div class='ctx'> 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,</div><div class='ctx'> 	.update_bw_bounding_box = dcn301_update_bw_bounding_box,</div><div class='del'>-	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state</div><div class='add'>+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn301_resource_construct(</div><div class='hunk'>@@ -1490,6 +1501,7 @@ static bool dcn301_resource_construct(</div><div class='ctx'> 		bp_query_result = ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_interop(ctx-&gt;dc_bios, &amp;is_vbios_interop_enabled);</div><div class='ctx'> 		dc-&gt;caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) &amp;&amp; !!is_vbios_interop_enabled;</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -1698,6 +1710,8 @@ static bool dcn301_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c<br/>index 5791b5cc2875..c0d4a1dc94f8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c</a></div><div class='hunk'>@@ -47,7 +47,8 @@</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+</div><div class='ctx'> #include "dce/dce_abm.h"</div><div class='ctx'> #include "dce/dce_audio.h"</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='hunk'>@@ -81,7 +82,6 @@</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.disable_dmcu = true,</div><div class='ctx'> 		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = false,</div><div class='ctx'> 		.clock_trace = true,</div><div class='ctx'> 		.disable_pplib_clock_request = true,</div><div class='ctx'> 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,</div><div class='hunk'>@@ -98,10 +98,13 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.dmub_command_table = true,</div><div class='ctx'> 		.use_max_lb = true,</div><div class='ctx'> 		.exit_idle_opt_for_cursor_updates = true,</div><div class='del'>-		.enable_legacy_fast_update = false,</div><div class='ctx'> 		.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+		.enable_legacy_fast_update = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 		.psr = {</div><div class='ctx'> 			.disable_psr = false,</div><div class='hunk'>@@ -893,7 +896,7 @@ static struct link_encoder *dcn302_link_encoder_create(</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn30_link_encoder_construct(enc20, enc_init_data, &amp;link_enc_feature,</div><div class='hunk'>@@ -1152,6 +1155,7 @@ static struct resource_funcs dcn302_res_pool_funcs = {</div><div class='ctx'> 		.update_bw_bounding_box = dcn302_update_bw_bounding_box,</div><div class='ctx'> 		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 		.get_panel_config_defaults = dcn302_get_panel_config_defaults,</div><div class='add'>+		.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct dc_cap_funcs cap_funcs = {</div><div class='hunk'>@@ -1234,6 +1238,7 @@ static bool dcn302_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='ctx'> 	dc-&gt;caps.dmcub_support = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -1288,6 +1293,7 @@ static bool dcn302_resource_construct(</div><div class='ctx'> 				&amp;is_vbios_interop_enabled);</div><div class='ctx'> 		dc-&gt;caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) &amp;&amp; !!is_vbios_interop_enabled;</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -1480,6 +1486,8 @@ static bool dcn302_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c<br/>index 25cd6236b054..75e09c2c283e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c</a></div><div class='hunk'>@@ -47,7 +47,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> </div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce/dce_abm.h"</div><div class='ctx'> #include "dce/dce_audio.h"</div><div class='hunk'>@@ -82,7 +82,6 @@</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.disable_dmcu = true,</div><div class='ctx'> 		.force_abm_enable = false,</div><div class='del'>-		.timing_trace = false,</div><div class='ctx'> 		.clock_trace = true,</div><div class='ctx'> 		.disable_pplib_clock_request = true,</div><div class='ctx'> 		.pipe_split_policy = MPC_SPLIT_AVOID,</div><div class='hunk'>@@ -97,11 +96,15 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='ctx'> 		.dwb_fi_phase = -1, // -1 = disable,</div><div class='ctx'> 		.dmub_command_table = true,</div><div class='add'>+		.use_max_lb = true,</div><div class='ctx'> 		.exit_idle_opt_for_cursor_updates = true,</div><div class='del'>-		.disable_idle_power_optimizations = false,</div><div class='ctx'> 		.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+		.enable_legacy_fast_update = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 		.psr = {</div><div class='ctx'> 			.disable_psr = false,</div><div class='hunk'>@@ -145,9 +148,9 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> 				.fp16 = 16000</div><div class='ctx'> 		},</div><div class='ctx'> 		.max_downscale_factor = {</div><div class='del'>-				.argb8888 = 600,</div><div class='del'>-				.nv12 = 600,</div><div class='del'>-				.fp16 = 600</div><div class='add'>+				.argb8888 = 167,</div><div class='add'>+				.nv12 = 167,</div><div class='add'>+				.fp16 = 167</div><div class='ctx'> 		},</div><div class='ctx'> 		16,</div><div class='ctx'> 		16</div><div class='hunk'>@@ -838,7 +841,7 @@ static struct link_encoder *dcn303_link_encoder_create(</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn30_link_encoder_construct(enc20, enc_init_data, &amp;link_enc_feature,</div><div class='hunk'>@@ -1096,6 +1099,7 @@ static struct resource_funcs dcn303_res_pool_funcs = {</div><div class='ctx'> 		.update_bw_bounding_box = dcn303_update_bw_bounding_box,</div><div class='ctx'> 		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 		.get_panel_config_defaults = dcn303_get_panel_config_defaults,</div><div class='add'>+		.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct dc_cap_funcs cap_funcs = {</div><div class='hunk'>@@ -1143,7 +1147,7 @@ static bool dcn303_resource_construct(</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct dc_context *ctx = dc-&gt;ctx;</div><div class='ctx'> 	struct irq_service_init_data init_data;</div><div class='del'>-	struct ddc_service_init_data ddc_init_data;</div><div class='add'>+	struct ddc_service_init_data ddc_init_data = {0};</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;dc_bios-&gt;regs = &amp;bios_regs;</div><div class='ctx'> </div><div class='hunk'>@@ -1171,11 +1175,14 @@ static bool dcn303_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.cursor_cache_size =</div><div class='ctx'> 		dc-&gt;caps.max_cursor_size * dc-&gt;caps.max_cursor_size * 8;</div><div class='ctx'> 	dc-&gt;caps.max_slave_planes = 1;</div><div class='add'>+	dc-&gt;caps.max_slave_yuv_planes = 1;</div><div class='add'>+	dc-&gt;caps.max_slave_rgb_planes = 1;</div><div class='ctx'> 	dc-&gt;caps.post_blend_color_processing = true;</div><div class='ctx'> 	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='ctx'> 	dc-&gt;caps.dmcub_support = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -1230,6 +1237,7 @@ static bool dcn303_resource_construct(</div><div class='ctx'> 		bp_query_result = ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_interop(ctx-&gt;dc_bios, &amp;is_vbios_interop_enabled);</div><div class='ctx'> 		dc-&gt;caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) &amp;&amp; !!is_vbios_interop_enabled;</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -1410,6 +1418,8 @@ static bool dcn303_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c<br/>index 04d142f97474..0d667b54ccf8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c</a></div><div class='hunk'>@@ -75,7 +75,6 @@</div><div class='ctx'> #include "dcn30/dcn30_dwb.h"</div><div class='ctx'> #include "dcn30/dcn30_mmhubbub.h"</div><div class='ctx'> </div><div class='del'>-// TODO: change include headers /amd/include/asic_reg after upstream</div><div class='ctx'> #include "yellow_carp_offset.h"</div><div class='ctx'> #include "dcn/dcn_3_1_2_offset.h"</div><div class='ctx'> #include "dcn/dcn_3_1_2_sh_mask.h"</div><div class='hunk'>@@ -859,7 +858,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,</div><div class='hunk'>@@ -870,7 +868,7 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.max_downscale_src_width = 4096,/*upto true 4K*/</div><div class='ctx'> 	.disable_pplib_wm_range = false,</div><div class='ctx'> 	.scl_reset_length10 = true,</div><div class='del'>-	.sanity_checks = true,</div><div class='add'>+	.sanity_checks = false,</div><div class='ctx'> 	.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='ctx'> 	.dwb_fi_phase = -1, // -1 = disable,</div><div class='ctx'> 	.dmub_command_table = true,</div><div class='hunk'>@@ -890,12 +888,15 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 		}</div><div class='ctx'> 	},</div><div class='ctx'> 	.disable_z10 = true,</div><div class='del'>-	.enable_legacy_fast_update = true,</div><div class='ctx'> 	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/</div><div class='ctx'> 	.dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 	.psr = {</div><div class='ctx'> 		.disable_psr = false,</div><div class='hunk'>@@ -1094,7 +1095,7 @@ static struct link_encoder *dcn31_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn31_link_encoder_construct(enc20,</div><div class='hunk'>@@ -1311,6 +1312,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> 	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,</div><div class='ctx'> 					&amp;hpo_dp_link_enc_regs[inst],</div><div class='hunk'>@@ -1616,14 +1619,14 @@ static bool is_dual_plane(enum surface_pixel_format format)</div><div class='ctx'> int dcn31x_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 					  struct dc_state *context,</div><div class='ctx'> 					  display_e2e_pipe_params_st *pipes,</div><div class='del'>-					  bool fast_validate)</div><div class='add'>+					  enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t pipe_cnt;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='del'>-	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; pipe_cnt; i++) {</div><div class='ctx'> 		pipes[i].pipe.src.gpuvm = 1;</div><div class='hunk'>@@ -1641,15 +1644,15 @@ int dcn31x_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> int dcn31_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct pipe_ctx *pipe = 0;</div><div class='ctx'> 	bool upscaled = false;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -1720,6 +1723,12 @@ int dcn31_populate_dml_pipes_from_context(</div><div class='ctx'> 	return pipe_cnt;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+unsigned int dcn31_get_det_buffer_size(</div><div class='add'>+	const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	return context-&gt;bw_ctx.dml.ip.det_buffer_size_kbytes;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn31_calculate_wm_and_dlg(</div><div class='ctx'> 		struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='hunk'>@@ -1752,9 +1761,9 @@ dcn31_set_mcif_arb_params(struct dc *dc,</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dcn31_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn31_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='hunk'>@@ -1762,25 +1771,29 @@ bool dcn31_validate_bandwidth(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	int vlevel = 0;</div><div class='ctx'> 	int pipe_cnt = 0;</div><div class='del'>-	display_e2e_pipe_params_st *pipes = kzalloc(dc-&gt;res_pool-&gt;pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='add'>+	display_e2e_pipe_params_st *pipes = kcalloc(dc-&gt;res_pool-&gt;pipe_count,</div><div class='add'>+			sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_COUNT();</div><div class='ctx'> </div><div class='add'>+	if (!pipes)</div><div class='add'>+		goto validate_fail;</div><div class='add'>+</div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	out = dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, fast_validate, true);</div><div class='add'>+	out = dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, validate_mode, true);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	// Disable fast_validate to set min dcfclk in alculate_wm_and_dlg</div><div class='add'>+	// Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg</div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='del'>-		fast_validate = false;</div><div class='add'>+		validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;</div><div class='ctx'> </div><div class='ctx'> 	if (!out)</div><div class='ctx'> 		goto validate_fail;</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1803,7 +1816,7 @@ validate_out:</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_FINISH();</div><div class='ctx'> </div><div class='del'>-	return out;</div><div class='add'>+	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)</div><div class='hunk'>@@ -1839,6 +1852,10 @@ static struct resource_funcs dcn31_res_pool_funcs = {</div><div class='ctx'> 	.update_bw_bounding_box = dcn31_update_bw_bounding_box,</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn31_get_panel_config_defaults,</div><div class='add'>+	.get_det_buffer_size = dcn31_get_det_buffer_size,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clock_source *dcn30_clock_source_create(</div><div class='hunk'>@@ -1860,6 +1877,7 @@ static struct clock_source *dcn30_clock_source_create(</div><div class='ctx'> 		return &amp;clk_src-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfree(clk_src);</div><div class='ctx'> 	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='hunk'>@@ -1941,8 +1959,12 @@ static bool dcn31_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.num_of_host_routers = 2;</div><div class='add'>+	dc-&gt;caps.num_of_dpias_per_host_router = 2;</div><div class='add'>+</div><div class='ctx'> 	/* Use pipe context based otg sync logic */</div><div class='ctx'> 	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='add'>+	dc-&gt;config.disable_hbr_audio_dp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='hunk'>@@ -1959,6 +1981,7 @@ static bool dcn31_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2185,6 +2208,8 @@ static bool dcn31_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip-&gt;max_num_dpp = dcn3_1_ip.max_num_dpp;</div><div class='hunk'>@@ -2214,3 +2239,35 @@ struct resource_pool *dcn31_create_resource_pool(</div><div class='ctx'> 	kfree(pool);</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,</div><div class='add'>+	struct dc_link_settings *link_setting,</div><div class='add'>+	uint8_t pipe_count,</div><div class='add'>+	struct pipe_ctx *pipes,</div><div class='add'>+	struct audio_output *audio_output)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *state = link-&gt;dc-&gt;current_state;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		if (state-&gt;streams[i] &amp;&amp; state-&gt;streams[i]-&gt;link &amp;&amp; state-&gt;streams[i]-&gt;link == link)</div><div class='add'>+			link-&gt;dc-&gt;hwss.calculate_pix_rate_divider((struct dc *)link-&gt;dc, state, state-&gt;streams[i]);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pipe_count; i++) {</div><div class='add'>+		link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;build_pipe_pix_clk_params(&amp;pipes[i]);</div><div class='add'>+</div><div class='add'>+		// Setup audio</div><div class='add'>+		if (pipes[i].stream_res.audio != NULL)</div><div class='add'>+			build_audio_output(state, &amp;pipes[i], &amp;audio_output[i]);</div><div class='add'>+	}</div><div class='add'>+#else</div><div class='add'>+	/* This DCN requires rate divider updates and audio reprogramming to allow DP1&lt;--&gt;DP2 link rate switching,</div><div class='add'>+	 * but the above will not compile on architectures without an FPU.</div><div class='add'>+	 */</div><div class='add'>+	DC_LOG_WARNING("%s: DP1&lt;--&gt;DP2 link retraining will not work on this DCN on non-FPU platforms", __func__);</div><div class='add'>+	ASSERT(0);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return DC_OK;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h<br/>index 901436591ed4..c32c85ef0ba4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h</a></div><div class='hunk'>@@ -37,9 +37,9 @@ struct dcn31_resource_pool {</div><div class='ctx'> 	struct resource_pool base;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-bool dcn31_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn31_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> void dcn31_calculate_wm_and_dlg(</div><div class='ctx'> 		struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='hunk'>@@ -48,7 +48,7 @@ void dcn31_calculate_wm_and_dlg(</div><div class='ctx'> int dcn31_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate);</div><div class='add'>+	enum dc_validate_mode validate_mode);</div><div class='ctx'> void</div><div class='ctx'> dcn31_populate_dml_writeback_from_context(struct dc *dc,</div><div class='ctx'> 					  struct resource_context *res_ctx,</div><div class='hunk'>@@ -63,6 +63,15 @@ struct resource_pool *dcn31_create_resource_pool(</div><div class='ctx'> 		const struct dc_init_data *init_data,</div><div class='ctx'> 		struct dc *dc);</div><div class='ctx'> </div><div class='add'>+unsigned int dcn31_get_det_buffer_size(</div><div class='add'>+	const struct dc_state *context);</div><div class='add'>+</div><div class='add'>+enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,</div><div class='add'>+	struct dc_link_settings *link_setting,</div><div class='add'>+	uint8_t pipe_count,</div><div class='add'>+	struct pipe_ctx *pipes,</div><div class='add'>+	struct audio_output *audio_output);</div><div class='add'>+</div><div class='ctx'> /*temp: B0 specific before switch to dcn313 headers*/</div><div class='ctx'> #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL</div><div class='ctx'> #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c<br/>index c97391edb5ff..3ccde75a4ecb 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c</a></div><div class='hunk'>@@ -876,7 +876,6 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.replay_skip_crtc_disabled = true,</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_dpp_power_gate = false,</div><div class='ctx'> 	.disable_hubp_power_gate = false,</div><div class='hunk'>@@ -889,7 +888,7 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.max_downscale_src_width = 4096,/*upto true 4k*/</div><div class='ctx'> 	.disable_pplib_wm_range = false,</div><div class='ctx'> 	.scl_reset_length10 = true,</div><div class='del'>-	.sanity_checks = true,</div><div class='add'>+	.sanity_checks = false,</div><div class='ctx'> 	.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='ctx'> 	.dwb_fi_phase = -1, // -1 = disable,</div><div class='ctx'> 	.dmub_command_table = true,</div><div class='hunk'>@@ -926,24 +925,12 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> </div><div class='ctx'> 	.seamless_boot_odm_combine = true,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='add'>+	.disable_dsc_power_gate = true,</div><div class='add'>+	.min_disp_clk_khz = 100000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dc_debug_options debug_defaults_diags = {</div><div class='del'>-	.disable_dmcu = true,</div><div class='del'>-	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = true,</div><div class='del'>-	.clock_trace = true,</div><div class='del'>-	.disable_dpp_power_gate = true,</div><div class='del'>-	.disable_hubp_power_gate = true,</div><div class='del'>-	.disable_clock_gate = true,</div><div class='del'>-	.disable_pplib_clock_request = true,</div><div class='del'>-	.disable_pplib_wm_range = true,</div><div class='del'>-	.disable_stutter = false,</div><div class='del'>-	.scl_reset_length10 = true,</div><div class='del'>-	.dwb_fi_phase = -1, // -1 = disable</div><div class='del'>-	.dmub_command_table = true,</div><div class='del'>-	.enable_tri_buf = true,</div><div class='del'>-	.use_max_lb = true</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='hunk'>@@ -1166,7 +1153,7 @@ static struct link_encoder *dcn31_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn31_link_encoder_construct(enc20,</div><div class='hunk'>@@ -1384,6 +1371,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> 	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,</div><div class='ctx'> 					&amp;hpo_dp_link_enc_regs[inst],</div><div class='hunk'>@@ -1675,20 +1664,20 @@ static struct clock_source *dcn31_clock_source_create(</div><div class='ctx'> 		return &amp;clk_src-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	kfree(clk_src);</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dcn314_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int pipe_cnt;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);</div><div class='add'>+	pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	return pipe_cnt;</div><div class='hunk'>@@ -1710,28 +1699,9 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi</div><div class='ctx'> 	*panel_config = panel_config_defaults;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool filter_modes_for_single_channel_workaround(struct dc *dc,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	// Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR</div><div class='del'>-	if (dc-&gt;clk_mgr-&gt;bw_params-&gt;vram_type == 34 &amp;&amp;</div><div class='del'>-	    dc-&gt;clk_mgr-&gt;bw_params-&gt;num_channels &lt; 2 &amp;&amp;</div><div class='del'>-	    context-&gt;stream_count &gt; 1) {</div><div class='del'>-		int total_phy_pix_clk = 0;</div><div class='del'>-</div><div class='del'>-		for (int i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='del'>-			if (context-&gt;res_ctx.pipe_ctx[i].stream)</div><div class='del'>-				total_phy_pix_clk += context-&gt;res_ctx.pipe_ctx[i].stream-&gt;phy_pix_clk;</div><div class='del'>-</div><div class='del'>-		if (total_phy_pix_clk &gt;= (1148928+826260)) //2K@240Hz+8K@24fps</div><div class='del'>-			return true;</div><div class='del'>-	}</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool dcn314_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn314_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='hunk'>@@ -1739,29 +1709,30 @@ bool dcn314_validate_bandwidth(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	int vlevel = 0;</div><div class='ctx'> 	int pipe_cnt = 0;</div><div class='del'>-	display_e2e_pipe_params_st *pipes = kzalloc(dc-&gt;res_pool-&gt;pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='add'>+	display_e2e_pipe_params_st *pipes = kcalloc(dc-&gt;res_pool-&gt;pipe_count,</div><div class='add'>+			sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_COUNT();</div><div class='ctx'> </div><div class='del'>-	if (filter_modes_for_single_channel_workaround(dc, context))</div><div class='add'>+	if (!pipes)</div><div class='ctx'> 		goto validate_fail;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='ctx'> 	// do not support self refresh only</div><div class='del'>-	out = dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, fast_validate, false);</div><div class='add'>+	out = dcn30_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, validate_mode, false);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	// Disable fast_validate to set min dcfclk in calculate_wm_and_dlg</div><div class='add'>+	// Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg</div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='del'>-		fast_validate = false;</div><div class='add'>+		validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;</div><div class='ctx'> </div><div class='ctx'> 	if (!out)</div><div class='ctx'> 		goto validate_fail;</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1784,7 +1755,7 @@ validate_out:</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_FINISH();</div><div class='ctx'> </div><div class='del'>-	return out;</div><div class='add'>+	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct resource_funcs dcn314_res_pool_funcs = {</div><div class='hunk'>@@ -1812,6 +1783,10 @@ static struct resource_funcs dcn314_res_pool_funcs = {</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn314_get_panel_config_defaults,</div><div class='ctx'> 	.get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,</div><div class='add'>+	.get_det_buffer_size = dcn31_get_det_buffer_size,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clock_source *dcn30_clock_source_create(</div><div class='hunk'>@@ -1833,8 +1808,8 @@ static struct clock_source *dcn30_clock_source_create(</div><div class='ctx'> 		return &amp;clk_src-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	kfree(clk_src);</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1917,6 +1892,9 @@ static bool dcn314_resource_construct(</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;caps.max_disp_clock_khz_at_vmin = 650000;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.num_of_host_routers = 2;</div><div class='add'>+	dc-&gt;caps.num_of_dpias_per_host_router = 2;</div><div class='add'>+</div><div class='ctx'> 	/* Use pipe context based otg sync logic */</div><div class='ctx'> 	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='ctx'> </div><div class='hunk'>@@ -1935,11 +1913,10 @@ static bool dcn314_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='del'>-	else</div><div class='del'>-		dc-&gt;debug = debug_defaults_diags;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable pipe power gating */</div><div class='ctx'> 	dc-&gt;debug.disable_dpp_power_gate = true;</div><div class='hunk'>@@ -2148,6 +2125,8 @@ static bool dcn314_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip-&gt;max_num_dpp = dcn3_14_ip.max_num_dpp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h<br/>index 49ffe71018df..ac9bb7f097d5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h</a></div><div class='hunk'>@@ -39,9 +39,9 @@ struct dcn314_resource_pool {</div><div class='ctx'> 	struct resource_pool base;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-bool dcn314_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn314_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> struct resource_pool *dcn314_create_resource_pool(</div><div class='ctx'> 		const struct dc_init_data *init_data,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c<br/>index 515ba435f759..4e962f522f1b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c</a></div><div class='hunk'>@@ -125,6 +125,7 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "dce/dmub_abm.h"</div><div class='ctx'> #include "dce/dmub_psr.h"</div><div class='add'>+#include "dce/dmub_replay.h"</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='ctx'> </div><div class='hunk'>@@ -857,7 +858,6 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_z10 = true, /*hw not support it*/</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,</div><div class='hunk'>@@ -887,9 +887,13 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 			.afmt = true,</div><div class='ctx'> 		}</div><div class='ctx'> 	},</div><div class='del'>-	.enable_legacy_fast_update = true,</div><div class='ctx'> 	.psr_power_use_phy_fsm = 0,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='add'>+	.min_disp_clk_khz = 100000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='hunk'>@@ -1090,7 +1094,7 @@ static struct link_encoder *dcn31_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn31_link_encoder_construct(enc20,</div><div class='hunk'>@@ -1309,6 +1313,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> 	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,</div><div class='ctx'> 					&amp;hpo_dp_link_enc_regs[inst],</div><div class='hunk'>@@ -1482,6 +1488,9 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)</div><div class='ctx'> 	if (pool-&gt;base.psr != NULL)</div><div class='ctx'> 		dmub_psr_destroy(&amp;pool-&gt;base.psr);</div><div class='ctx'> </div><div class='add'>+	if (pool-&gt;base.replay != NULL)</div><div class='add'>+		dmub_replay_destroy(&amp;pool-&gt;base.replay);</div><div class='add'>+</div><div class='ctx'> 	if (pool-&gt;base.dccg != NULL)</div><div class='ctx'> 		dcn_dccg_destroy(&amp;pool-&gt;base.dccg);</div><div class='ctx'> }</div><div class='hunk'>@@ -1659,7 +1668,7 @@ static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)</div><div class='ctx'> static int dcn315_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt, crb_idx, crb_pipes;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='hunk'>@@ -1669,7 +1678,7 @@ static int dcn315_populate_dml_pipes_from_context(</div><div class='ctx'> 	bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0, crb_pipes = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -1693,7 +1702,7 @@ static int dcn315_populate_dml_pipes_from_context(</div><div class='ctx'> 		pipes[pipe_cnt].dout.dsc_input_bpc = 0;</div><div class='ctx'> 		DC_FP_START();</div><div class='ctx'> 		dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);</div><div class='del'>-		if (pixel_rate_crb &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe) {</div><div class='add'>+		if (pixel_rate_crb) {</div><div class='ctx'> 			int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);</div><div class='ctx'> 			/* Ceil to crb segment size */</div><div class='ctx'> 			int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate(</div><div class='hunk'>@@ -1750,28 +1759,26 @@ static int dcn315_populate_dml_pipes_from_context(</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			if (!pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe) {</div><div class='del'>-				bool split_required = pipe-&gt;stream-&gt;timing.pix_clk_100hz &gt;= dcn_get_max_non_odm_pix_rate_100hz(&amp;dc-&gt;dml.soc)</div><div class='del'>-						|| (pipe-&gt;plane_state &amp;&amp; pipe-&gt;plane_state-&gt;src_rect.width &gt; 5120);</div><div class='del'>-</div><div class='del'>-				if (remaining_det_segs &gt; MIN_RESERVED_DET_SEGS)</div><div class='del'>-					pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +</div><div class='del'>-							(crb_idx &lt; (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);</div><div class='del'>-				if (pipes[pipe_cnt].pipe.src.det_size_override &gt; 2 * DCN3_15_MAX_DET_SEGS) {</div><div class='del'>-					/* Clamp to 2 pipe split max det segments */</div><div class='del'>-					remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);</div><div class='del'>-					pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;</div><div class='del'>-				}</div><div class='del'>-				if (pipes[pipe_cnt].pipe.src.det_size_override &gt; DCN3_15_MAX_DET_SEGS || split_required) {</div><div class='del'>-					/* If we are splitting we must have an even number of segments */</div><div class='del'>-					remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;</div><div class='del'>-					pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;</div><div class='del'>-				}</div><div class='del'>-				/* Convert segments into size for DML use */</div><div class='del'>-				pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;</div><div class='del'>-</div><div class='del'>-				crb_idx++;</div><div class='add'>+			bool split_required = pipe-&gt;stream-&gt;timing.pix_clk_100hz &gt;= dcn_get_max_non_odm_pix_rate_100hz(&amp;dc-&gt;dml.soc)</div><div class='add'>+					|| (pipe-&gt;plane_state &amp;&amp; pipe-&gt;plane_state-&gt;src_rect.width &gt; 5120);</div><div class='add'>+</div><div class='add'>+			if (remaining_det_segs &gt; MIN_RESERVED_DET_SEGS &amp;&amp; crb_pipes != 0)</div><div class='add'>+				pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +</div><div class='add'>+						(crb_idx &lt; (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);</div><div class='add'>+			if (pipes[pipe_cnt].pipe.src.det_size_override &gt; 2 * DCN3_15_MAX_DET_SEGS) {</div><div class='add'>+				/* Clamp to 2 pipe split max det segments */</div><div class='add'>+				remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);</div><div class='add'>+				pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;</div><div class='ctx'> 			}</div><div class='add'>+			if (pipes[pipe_cnt].pipe.src.det_size_override &gt; DCN3_15_MAX_DET_SEGS || split_required) {</div><div class='add'>+				/* If we are splitting we must have an even number of segments */</div><div class='add'>+				remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;</div><div class='add'>+				pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;</div><div class='add'>+			}</div><div class='add'>+			/* Convert segments into size for DML use */</div><div class='add'>+			pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;</div><div class='add'>+</div><div class='add'>+			crb_idx++;</div><div class='ctx'> 			pipe_cnt++;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1806,6 +1813,11 @@ static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_confi</div><div class='ctx'> 	*panel_config = panel_config_defaults;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dcn315_get_power_profile(const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	return !context-&gt;bw_ctx.bw.dcn.clk.p_state_change_support;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct dc_cap_funcs cap_funcs = {</div><div class='ctx'> 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap</div><div class='ctx'> };</div><div class='hunk'>@@ -1834,6 +1846,11 @@ static struct resource_funcs dcn315_res_pool_funcs = {</div><div class='ctx'> 	.update_bw_bounding_box = dcn315_update_bw_bounding_box,</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn315_get_panel_config_defaults,</div><div class='add'>+	.get_power_profile = dcn315_get_power_profile,</div><div class='add'>+	.get_det_buffer_size = dcn31_get_det_buffer_size,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn315_resource_construct(</div><div class='hunk'>@@ -1926,6 +1943,7 @@ static bool dcn315_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2046,6 +2064,14 @@ static bool dcn315_resource_construct(</div><div class='ctx'> 		goto create_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Replay */</div><div class='add'>+	pool-&gt;base.replay = dmub_replay_create(ctx);</div><div class='add'>+	if (pool-&gt;base.replay == NULL) {</div><div class='add'>+		dm_error("DC: failed to create replay obj!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* ABM */</div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='ctx'> 		pool-&gt;base.multiple_abms[i] = dmub_abm_create(ctx,</div><div class='hunk'>@@ -2121,6 +2147,8 @@ static bool dcn315_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip-&gt;max_num_dpp = dcn3_15_ip.max_num_dpp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c<br/>index b9753d4606f8..5a95dd54cb42 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c</a></div><div class='hunk'>@@ -125,7 +125,6 @@</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> </div><div class='ctx'> #define DCN3_16_MAX_DET_SIZE 384</div><div class='del'>-#define DCN3_16_MIN_COMPBUF_SIZE_KB 128</div><div class='ctx'> #define DCN3_16_CRB_SEGMENT_SIZE_KB 64</div><div class='ctx'> </div><div class='ctx'> enum dcn31_clk_src_array_id {</div><div class='hunk'>@@ -854,7 +853,6 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_z10 = true, /*hw not support it*/</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,</div><div class='hunk'>@@ -884,10 +882,13 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 			.afmt = true,</div><div class='ctx'> 		}</div><div class='ctx'> 	},</div><div class='del'>-	.enable_legacy_fast_update = true,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 	.psr = {</div><div class='ctx'> 		.disable_psr = false,</div><div class='hunk'>@@ -1086,7 +1087,7 @@ static struct link_encoder *dcn31_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	dcn31_link_encoder_construct(enc20,</div><div class='hunk'>@@ -1306,6 +1307,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> 	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,</div><div class='ctx'> 					&amp;hpo_dp_link_enc_regs[inst],</div><div class='hunk'>@@ -1610,15 +1613,15 @@ static bool is_dual_plane(enum surface_pixel_format format)</div><div class='ctx'> static int dcn316_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct pipe_ctx *pipe = 0;</div><div class='ctx'> 	const int max_usable_det = context-&gt;bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -1719,6 +1722,10 @@ static struct resource_funcs dcn316_res_pool_funcs = {</div><div class='ctx'> 	.update_bw_bounding_box = dcn316_update_bw_bounding_box,</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn316_get_panel_config_defaults,</div><div class='add'>+	.get_det_buffer_size = dcn31_get_det_buffer_size,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn316_resource_construct(</div><div class='hunk'>@@ -1811,6 +1818,7 @@ static bool dcn316_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2006,6 +2014,8 @@ static bool dcn316_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip-&gt;max_num_dpp = dcn3_16_ip.max_num_dpp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c<br/>index ce1754cc1f46..b276fec3e479 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include "dc_types.h"</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='hunk'>@@ -68,7 +69,7 @@</div><div class='ctx'> #include "dml/display_mode_vba.h"</div><div class='ctx'> #include "dcn32/dcn32_dccg.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn31/dcn31_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn30/dcn30_dwb.h"</div><div class='hunk'>@@ -91,7 +92,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "dc_state_priv.h"</div><div class='ctx'> </div><div class='del'>-#include "dml2/dml2_wrapper.h"</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -689,7 +690,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore</div><div class='hunk'>@@ -719,6 +719,7 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.force_disable_subvp = false,</div><div class='ctx'> 	.exit_idle_opt_for_cursor_updates = true,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='add'>+	.using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.</div><div class='ctx'> 	.enable_single_display_2to1_odm_policy = true,</div><div class='ctx'> </div><div class='ctx'> 	/* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/</div><div class='hunk'>@@ -737,6 +738,10 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dp_plus_plus_wa = true,</div><div class='ctx'> 	.fpo_vactive_min_active_margin_us = 200,</div><div class='ctx'> 	.fpo_vactive_max_blank_us = 1000,</div><div class='add'>+	.disable_stutter_for_wm_program = true</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='ctx'> 	.enable_legacy_fast_update = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1038,7 +1043,7 @@ static struct link_encoder *dcn32_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='hunk'>@@ -1304,6 +1309,8 @@ static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='ctx'> #define REG_STRUCT hpo_dp_link_enc_regs</div><div class='hunk'>@@ -1648,6 +1655,9 @@ static void dcn32_enable_phantom_plane(struct dc *dc,</div><div class='ctx'> 		else</div><div class='ctx'> 			phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe-&gt;plane_state);</div><div class='ctx'> </div><div class='add'>+		if (!phantom_plane)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		memcpy(&amp;phantom_plane-&gt;address, &amp;curr_pipe-&gt;plane_state-&gt;address, sizeof(phantom_plane-&gt;address));</div><div class='ctx'> 		memcpy(&amp;phantom_plane-&gt;scaling_quality, &amp;curr_pipe-&gt;plane_state-&gt;scaling_quality,</div><div class='ctx'> 				sizeof(phantom_plane-&gt;scaling_quality));</div><div class='hunk'>@@ -1684,6 +1694,8 @@ static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,</div><div class='ctx'> 	struct pipe_ctx *ref_pipe = &amp;context-&gt;res_ctx.pipe_ctx[dc_pipe_idx];</div><div class='ctx'> </div><div class='ctx'> 	phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe-&gt;stream);</div><div class='add'>+	if (!phantom_stream)</div><div class='add'>+		return phantom_stream;</div><div class='ctx'> </div><div class='ctx'> 	/* stream has limited viewport and small timing */</div><div class='ctx'> 	memcpy(&amp;phantom_stream-&gt;timing, &amp;ref_pipe-&gt;stream-&gt;timing, sizeof(phantom_stream-&gt;timing));</div><div class='hunk'>@@ -1712,6 +1724,9 @@ void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	// be a valid candidate for SubVP (i.e. has a plane, stream, doesn't</div><div class='ctx'> 	// already have phantom pipe assigned, etc.) by previous checks.</div><div class='ctx'> 	phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);</div><div class='add'>+	if (!phantom_stream)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	dcn32_enable_phantom_plane(dc, context, phantom_stream, index);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -1731,7 +1746,7 @@ void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate)</div><div class='add'>+static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='hunk'>@@ -1739,7 +1754,8 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_val</div><div class='ctx'> </div><div class='ctx'> 	int vlevel = 0;</div><div class='ctx'> 	int pipe_cnt = 0;</div><div class='del'>-	display_e2e_pipe_params_st *pipes = kzalloc(dc-&gt;res_pool-&gt;pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='add'>+	display_e2e_pipe_params_st *pipes = kcalloc(dc-&gt;res_pool-&gt;pipe_count,</div><div class='add'>+			sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	/* To handle Freesync properly, setting FreeSync DML parameters</div><div class='ctx'> 	 * to its default state for the first stage of validation</div><div class='hunk'>@@ -1751,8 +1767,11 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_val</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_COUNT();</div><div class='ctx'> </div><div class='add'>+	if (!pipes)</div><div class='add'>+		goto validate_fail;</div><div class='add'>+</div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	out = dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, fast_validate);</div><div class='add'>+	out = dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, validate_mode);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='hunk'>@@ -1763,7 +1782,7 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_val</div><div class='ctx'> </div><div class='ctx'> 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate) {</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 		BW_VAL_TRACE_SKIP(fast);</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1792,31 +1811,109 @@ validate_out:</div><div class='ctx'> 	return out;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dcn32_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn32_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='del'>-	bool out = false;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	enum dc_status status;</div><div class='add'>+	const struct dc_stream_state *stream;</div><div class='add'>+</div><div class='add'>+	/* reset cursor limitations on subvp */</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		stream = context-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+		if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {</div><div class='add'>+			dc_state_set_stream_cursor_subvp_limit(stream, context, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;debug.using_dml2)</div><div class='del'>-		out = dml2_validate(dc, context, fast_validate);</div><div class='add'>+		status = dml2_validate(dc, context,</div><div class='add'>+				context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+				validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> 	else</div><div class='del'>-		out = dml1_validate(dc, context, fast_validate);</div><div class='del'>-	return out;</div><div class='add'>+		status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING &amp;&amp; status == DC_OK &amp;&amp; dc_state_is_subvp_in_use(context)) {</div><div class='add'>+		/* check new stream configuration still supports cursor if subvp used */</div><div class='add'>+		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+			stream = context-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+			if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &amp;&amp;</div><div class='add'>+					stream-&gt;cursor_position.enable &amp;&amp;</div><div class='add'>+					!dc_stream_check_cursor_attributes(stream, context, &amp;stream-&gt;cursor_attributes)) {</div><div class='add'>+				/* hw cursor cannot be supported with subvp active, so disable subvp for now */</div><div class='add'>+				dc_state_set_stream_cursor_subvp_limit(stream, context, true);</div><div class='add'>+				status = DC_FAIL_HW_CURSOR_SUPPORT;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING &amp;&amp; status == DC_FAIL_HW_CURSOR_SUPPORT) {</div><div class='add'>+		/* attempt to validate again with subvp disabled due to cursor */</div><div class='add'>+		if (dc-&gt;debug.using_dml2)</div><div class='add'>+			status = dml2_validate(dc, context,</div><div class='add'>+					context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+					validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+		else</div><div class='add'>+			status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate)</div><div class='add'>+	enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='ctx'> 	struct pipe_ctx *pipe = NULL;</div><div class='ctx'> 	bool subvp_in_use = false;</div><div class='ctx'> 	struct dc_crtc_timing *timing;</div><div class='del'>-</div><div class='del'>-	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);</div><div class='add'>+	int subvp_main_pipe_index = -1;</div><div class='add'>+	enum mall_stream_type mall_type;</div><div class='add'>+	bool single_display_subvp = false;</div><div class='add'>+	struct dc_stream_state *stream = NULL;</div><div class='add'>+	int num_subvp_main = 0;</div><div class='add'>+	int num_subvp_phantom = 0;</div><div class='add'>+	int num_subvp_none = 0;</div><div class='add'>+	int odm_slice_count;</div><div class='add'>+</div><div class='add'>+	dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);</div><div class='add'>+</div><div class='add'>+	/* For single display subvp, look for subvp main so if we have phantom</div><div class='add'>+	 *  pipe, we can set odm policy to match main pipe</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		stream = context-&gt;streams[i];</div><div class='add'>+		mall_type = dc_state_get_stream_subvp_type(context, stream);</div><div class='add'>+		if (mall_type == SUBVP_MAIN)</div><div class='add'>+			num_subvp_main++;</div><div class='add'>+		else if (mall_type == SUBVP_PHANTOM)</div><div class='add'>+			num_subvp_phantom++;</div><div class='add'>+		else</div><div class='add'>+			num_subvp_none++;</div><div class='add'>+	}</div><div class='add'>+	if (num_subvp_main == 1 &amp;&amp; num_subvp_phantom == 1 &amp;&amp; num_subvp_none == 0)</div><div class='add'>+		single_display_subvp = true;</div><div class='add'>+</div><div class='add'>+	if (single_display_subvp) {</div><div class='add'>+		for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			pipe = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+			if (!res_ctx-&gt;pipe_ctx[i].stream)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='add'>+			if (mall_type == SUBVP_MAIN) {</div><div class='add'>+				if (resource_is_pipe_type(pipe, OTG_MASTER))</div><div class='add'>+					subvp_main_pipe_index = i;</div><div class='add'>+			}</div><div class='add'>+			pipe_cnt++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> </div><div class='hunk'>@@ -1832,7 +1929,21 @@ int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 		pipes[pipe_cnt].pipe.dest.vfront_porch = timing-&gt;v_front_porch;</div><div class='ctx'> 		if (dc-&gt;config.enable_windowed_mpo_odm &amp;&amp;</div><div class='ctx'> 				dc-&gt;debug.enable_single_display_2to1_odm_policy) {</div><div class='del'>-			switch (resource_get_odm_slice_count(pipe)) {</div><div class='add'>+			/* For single display subvp, if pipe is phantom pipe,</div><div class='add'>+			 *  then copy odm policy from subvp main pipe</div><div class='add'>+			 */</div><div class='add'>+			mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='add'>+			if (single_display_subvp &amp;&amp; (mall_type == SUBVP_PHANTOM)) {</div><div class='add'>+				if (subvp_main_pipe_index &lt; 0) {</div><div class='add'>+					odm_slice_count = -1;</div><div class='add'>+					ASSERT(0);</div><div class='add'>+				} else {</div><div class='add'>+					odm_slice_count = resource_get_odm_slice_count(&amp;res_ctx-&gt;pipe_ctx[subvp_main_pipe_index]);</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				odm_slice_count = resource_get_odm_slice_count(pipe);</div><div class='add'>+			}</div><div class='add'>+			switch (odm_slice_count) {</div><div class='ctx'> 			case 2:</div><div class='ctx'> 				pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;</div><div class='ctx'> 				break;</div><div class='hunk'>@@ -1845,6 +1956,7 @@ int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 		} else {</div><div class='ctx'> 			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='ctx'> 		pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet</div><div class='ctx'> 		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;</div><div class='ctx'> 		pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;</div><div class='hunk'>@@ -1852,7 +1964,7 @@ int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 		/* Only populate DML input with subvp info for full updates.</div><div class='ctx'> 		 * This is just a workaround -- needs a proper fix.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!fast_validate) {</div><div class='add'>+		if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {</div><div class='ctx'> 			switch (dc_state_get_pipe_subvp_type(context, pipe)) {</div><div class='ctx'> 			case SUBVP_MAIN:</div><div class='ctx'> 				pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;</div><div class='hunk'>@@ -1912,6 +2024,30 @@ int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 	return pipe_cnt;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)</div><div class='add'>+{</div><div class='add'>+	uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;</div><div class='add'>+</div><div class='add'>+	if (total_size_in_mall_bytes == 0) {</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;caps.max_cab_allocation_bytes == 0) {</div><div class='add'>+		return 0xffffffff;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* add 2 lines for worst case alignment */</div><div class='add'>+	cache_lines_used = total_size_in_mall_bytes / dc-&gt;caps.cache_line_size + 2;</div><div class='add'>+</div><div class='add'>+	total_cache_lines = dc-&gt;caps.max_cab_allocation_bytes / dc-&gt;caps.cache_line_size;</div><div class='add'>+	lines_per_way = total_cache_lines / dc-&gt;caps.cache_num_ways;</div><div class='add'>+	num_ways = cache_lines_used / lines_per_way;</div><div class='add'>+	if (cache_lines_used % lines_per_way &gt; 0)</div><div class='add'>+		num_ways++;</div><div class='add'>+</div><div class='add'>+	return num_ways;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct dc_cap_funcs cap_funcs = {</div><div class='ctx'> 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,</div><div class='ctx'> 	.get_subvp_en = dcn32_subvp_in_use,</div><div class='hunk'>@@ -1930,12 +2066,30 @@ void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,</div><div class='ctx'> static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='ctx'> {</div><div class='ctx'> 	DC_FP_START();</div><div class='add'>+</div><div class='ctx'> 	dcn32_update_bw_bounding_box_fpu(dc, bw_params);</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;current_state &amp;&amp; dc-&gt;current_state-&gt;bw_ctx.dml2)</div><div class='ctx'> 		dml2_reinit(dc, &amp;dc-&gt;dml2_options, &amp;dc-&gt;current_state-&gt;bw_ctx.dml2);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;current_state &amp;&amp; dc-&gt;current_state-&gt;bw_ctx.dml2_dc_power_source)</div><div class='add'>+		dml2_reinit(dc, &amp;dc-&gt;dml2_dc_power_options, &amp;dc-&gt;current_state-&gt;bw_ctx.dml2_dc_power_source);</div><div class='add'>+</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	bool limit_cur_to_buf;</div><div class='add'>+</div><div class='add'>+	limit_cur_to_buf = dc_state_get_stream_subvp_cursor_limit(stream, state) &amp;&amp;</div><div class='add'>+			!stream-&gt;hw_cursor_req;</div><div class='add'>+</div><div class='add'>+	return limit_cur_to_buf ? dc-&gt;caps.max_buffered_cursor_size : dc-&gt;caps.max_cursor_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct resource_funcs dcn32_res_pool_funcs = {</div><div class='ctx'> 	.destroy = dcn32_destroy_resource_pool,</div><div class='ctx'> 	.link_enc_create = dcn32_link_encoder_create,</div><div class='hunk'>@@ -1960,6 +2114,9 @@ static struct resource_funcs dcn32_res_pool_funcs = {</div><div class='ctx'> 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,</div><div class='ctx'> 	.add_phantom_pipes = dcn32_add_phantom_pipes,</div><div class='ctx'> 	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,</div><div class='add'>+	.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t read_pipe_fuses(struct dc_context *ctx)</div><div class='hunk'>@@ -2006,8 +2163,6 @@ static bool dcn32_resource_construct(</div><div class='ctx'> #define REG_STRUCT dccg_regs</div><div class='ctx'> 	dccg_regs_init();</div><div class='ctx'> </div><div class='del'>-	DC_FP_START();</div><div class='del'>-</div><div class='ctx'> 	ctx-&gt;dc_bios-&gt;regs = &amp;bios_regs;</div><div class='ctx'> </div><div class='ctx'> 	pool-&gt;base.res_cap = &amp;res_cap_dcn32;</div><div class='hunk'>@@ -2045,10 +2200,13 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/</div><div class='ctx'> 	/* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/</div><div class='ctx'> 	dc-&gt;caps.max_cursor_size = 64;</div><div class='add'>+	/* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */</div><div class='add'>+	dc-&gt;caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='ctx'> 	dc-&gt;caps.mall_size_per_mem_channel = 4;</div><div class='del'>-	dc-&gt;caps.mall_size_total = 0;</div><div class='add'>+	/* total size = mall per channel * num channels * 1024 * 1024 */</div><div class='add'>+	dc-&gt;caps.mall_size_total = dc-&gt;caps.mall_size_per_mem_channel * dc-&gt;ctx-&gt;dc_bios-&gt;vram_info.num_chans * 1048576;</div><div class='ctx'> 	dc-&gt;caps.cursor_cache_size = dc-&gt;caps.max_cursor_size * dc-&gt;caps.max_cursor_size * 8;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;caps.cache_line_size = 64;</div><div class='hunk'>@@ -2082,6 +2240,7 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.dmcub_support = true;</div><div class='ctx'> 	dc-&gt;caps.seamless_odm = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -2097,7 +2256,7 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.dpp.gamma_corr = 1;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dgam_rom_for_yuv = 0;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;caps.color.dpp.hw_3d_lut = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.hw_3d_lut = 0;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1</div><div class='ctx'> 	// no OGAM ROM on DCN2 and later ASICs</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_rom_caps.srgb = 0;</div><div class='hunk'>@@ -2116,12 +2275,14 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.preblend = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Use pipe context based otg sync logic */</div><div class='ctx'> 	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;config.dc_mode_clk_limit_support = true;</div><div class='ctx'> 	dc-&gt;config.enable_windowed_mpo_odm = true;</div><div class='add'>+	dc-&gt;config.disable_hbr_audio_dp2 = true;</div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='ctx'> 		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='hunk'>@@ -2137,6 +2298,7 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2344,6 +2506,8 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='hunk'>@@ -2358,34 +2522,13 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.dcn_pipe_count = pool-&gt;base.pipe_count;</div><div class='del'>-	dc-&gt;dml2_options.use_native_pstate_optimization = false;</div><div class='ctx'> 	dc-&gt;dml2_options.use_native_soc_bb_construction = true;</div><div class='ctx'> 	dc-&gt;dml2_options.minimize_dispclk_using_odm = true;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;dml2_options.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='add'>+	resource_init_common_dml2_callbacks(dc, &amp;dc-&gt;dml2_options);</div><div class='ctx'> 	dc-&gt;dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &amp;dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &amp;dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &amp;resource_update_pipes_for_stream_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &amp;resource_update_pipes_for_plane_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_mpc_slice_index = &amp;resource_get_mpc_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_odm_slice_index = &amp;resource_get_odm_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='del'>-</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_plane = &amp;dc_state_add_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_stream = &amp;dc_state_add_phantom_stream;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_plane = &amp;dc_state_create_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_plane = &amp;dc_state_remove_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_stream = &amp;dc_state_remove_phantom_stream;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_stream = &amp;dc_state_create_phantom_stream;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_plane = &amp;dc_state_release_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_stream = &amp;dc_state_release_phantom_stream;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.release_dsc = &amp;dcn20_release_dsc;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.get_pipe_subvp_type = &amp;dc_state_get_pipe_subvp_type;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.get_stream_subvp_type = &amp;dc_state_get_stream_subvp_type;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.get_paired_subvp_stream = &amp;dc_state_get_paired_subvp_stream;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool-&gt;base.funcs-&gt;calculate_mall_ways_from_bytes;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc-&gt;caps.subvp_fw_processing_delay_us;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='hunk'>@@ -2410,14 +2553,14 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	if (ASICREV_IS_GC_11_0_3(dc-&gt;ctx-&gt;asic_id.hw_internal_rev) &amp;&amp; (dc-&gt;config.sdpif_request_limit_words_per_umc == 0))</div><div class='ctx'> 		dc-&gt;config.sdpif_request_limit_words_per_umc = 16;</div><div class='ctx'> </div><div class='del'>-	DC_FP_END();</div><div class='add'>+	/* init DC limited DML2 options */</div><div class='add'>+	memcpy(&amp;dc-&gt;dml2_dc_power_options, &amp;dc-&gt;dml2_options, sizeof(struct dml2_configuration_options));</div><div class='add'>+	dc-&gt;dml2_dc_power_options.use_clock_dc_limits = true;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='ctx'> create_fail:</div><div class='ctx'> </div><div class='del'>-	DC_FP_END();</div><div class='del'>-</div><div class='ctx'> 	dcn32_resource_destruct(pool);</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -2483,7 +2626,7 @@ struct resource_pool *dcn32_create_resource_pool(</div><div class='ctx'>  * full update which delays the flip for 1 frame. If we use the original pipe</div><div class='ctx'>  * we don't have to toggle its power. So we can flip faster.</div><div class='ctx'>  */</div><div class='del'>-static int find_optimal_free_pipe_as_secondary_dpp_pipe(</div><div class='add'>+int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(</div><div class='ctx'> 		const struct resource_context *cur_res_ctx,</div><div class='ctx'> 		struct resource_context *new_res_ctx,</div><div class='ctx'> 		const struct resource_pool *pool,</div><div class='hunk'>@@ -2593,8 +2736,10 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(</div><div class='ctx'> 	struct resource_context *old_ctx = &amp;stream-&gt;ctx-&gt;dc-&gt;current_state-&gt;res_ctx;</div><div class='ctx'> 	int head_index;</div><div class='ctx'> </div><div class='del'>-	if (!head_pipe)</div><div class='add'>+	if (!head_pipe) {</div><div class='ctx'> 		ASSERT(0);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Modified from dcn20_acquire_idle_pipe_for_layer</div><div class='hunk'>@@ -2666,7 +2811,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(</div><div class='ctx'> 		return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(</div><div class='ctx'> 				new_ctx, pool, opp_head_pipe-&gt;stream, opp_head_pipe);</div><div class='ctx'> </div><div class='del'>-	free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe(</div><div class='add'>+	free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(</div><div class='ctx'> 					&amp;cur_ctx-&gt;res_ctx, &amp;new_ctx-&gt;res_ctx,</div><div class='ctx'> 					pool, opp_head_pipe);</div><div class='ctx'> 	if (free_pipe_idx &gt;= 0) {</div><div class='hunk'>@@ -2713,6 +2858,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(</div><div class='ctx'> 		free_pipe-&gt;plane_res.xfm = pool-&gt;transforms[free_pipe_idx];</div><div class='ctx'> 		free_pipe-&gt;plane_res.dpp = pool-&gt;dpps[free_pipe_idx];</div><div class='ctx'> 		free_pipe-&gt;plane_res.mpcc_inst = pool-&gt;dpps[free_pipe_idx]-&gt;inst;</div><div class='add'>+		free_pipe-&gt;dsc_padding_params = otg_master-&gt;dsc_padding_params;</div><div class='ctx'> 		if (free_pipe-&gt;stream-&gt;timing.flags.DSC == 1) {</div><div class='ctx'> 			dcn20_acquire_dsc(free_pipe-&gt;stream-&gt;ctx-&gt;dc,</div><div class='ctx'> 					&amp;new_ctx-&gt;res_ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h<br/>index 2258c5c7212d..99f0432288b4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h</a></div><div class='hunk'>@@ -98,14 +98,14 @@ void dcn32_add_phantom_pipes(struct dc *dc,</div><div class='ctx'> 		unsigned int pipe_cnt,</div><div class='ctx'> 		unsigned int index);</div><div class='ctx'> </div><div class='del'>-bool dcn32_validate_bandwidth(struct dc *dc,</div><div class='add'>+enum dc_status dcn32_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate);</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 	struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes,</div><div class='del'>-	bool fast_validate);</div><div class='add'>+	enum dc_validate_mode validate_mode);</div><div class='ctx'> </div><div class='ctx'> void dcn32_calculate_wm_and_dlg(</div><div class='ctx'> 		struct dc *dc, struct dc_state *context,</div><div class='hunk'>@@ -113,10 +113,6 @@ void dcn32_calculate_wm_and_dlg(</div><div class='ctx'> 		int pipe_cnt,</div><div class='ctx'> 		int vlevel);</div><div class='ctx'> </div><div class='del'>-uint32_t dcn32_helper_mall_bytes_to_ways(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		uint32_t total_size_in_mall_bytes);</div><div class='del'>-</div><div class='ctx'> uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='hunk'>@@ -141,6 +137,12 @@ bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);</div><div class='ctx'> bool dcn32_is_center_timing(struct pipe_ctx *pipe);</div><div class='ctx'> bool dcn32_is_psr_capable(struct pipe_ctx *pipe);</div><div class='ctx'> </div><div class='add'>+int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(</div><div class='add'>+		const struct resource_context *cur_res_ctx,</div><div class='add'>+		struct resource_context *new_res_ctx,</div><div class='add'>+		const struct resource_pool *pool,</div><div class='add'>+		const struct pipe_ctx *new_opp_head);</div><div class='add'>+</div><div class='ctx'> struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(</div><div class='ctx'> 		const struct dc_state *cur_ctx,</div><div class='ctx'> 		struct dc_state *new_ctx,</div><div class='hunk'>@@ -184,6 +186,12 @@ void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc</div><div class='ctx'> </div><div class='ctx'> void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='add'>+unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes);</div><div class='add'>+</div><div class='add'>+unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='ctx'> /* definitions for run time init of reg offsets */</div><div class='ctx'> </div><div class='ctx'> /* CLK SRC */</div><div class='hunk'>@@ -501,6 +509,8 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'>       SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                  \</div><div class='ctx'>       SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                  \</div><div class='ctx'>       SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),           \</div><div class='add'>+      SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id),                                    \</div><div class='add'>+      SRI_ARR(CM_TEST_DEBUG_DATA, CM, id),                                     \</div><div class='ctx'>       SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                   \</div><div class='ctx'>       SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                        \</div><div class='ctx'>       SRI_ARR(CURSOR0_CONTROL, CNVC_CUR, id),                                  \</div><div class='hunk'>@@ -757,6 +767,7 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'>       SRI_ARR(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),         \</div><div class='ctx'>       SRI_ARR(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),         \</div><div class='ctx'>       SRI_ARR(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),         \</div><div class='add'>+      SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),                           \</div><div class='ctx'>       SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id),                                     \</div><div class='ctx'>       SRI_ARR(DSCCIF_CONFIG1, DSCCIF, id),                                     \</div><div class='ctx'>       SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)</div><div class='hunk'>@@ -1047,7 +1058,9 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'>       SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),                                \</div><div class='ctx'>       SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \</div><div class='ctx'>       SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \</div><div class='del'>-      SRI_ARR(OTG_DRR_CONTROL, OTG, inst)</div><div class='add'>+      SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \</div><div class='add'>+      SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),                              \</div><div class='add'>+      SRI_ARR(INTERRUPT_DEST, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> /* HUBP */</div><div class='ctx'> </div><div class='hunk'>@@ -1128,7 +1141,8 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'>       SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),                               \</div><div class='ctx'>       SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),                                \</div><div class='ctx'>       SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),                                \</div><div class='del'>-      SRI_ARR(HUBP_CLK_CNTL, HUBP, id)</div><div class='add'>+      SRI_ARR(HUBP_CLK_CNTL, HUBP, id),                                        \</div><div class='add'>+      SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)</div><div class='ctx'> #define HUBP_REG_LIST_DCN2_COMMON_RI(id)                                       \</div><div class='ctx'>   HUBP_REG_LIST_DCN_RI(id), HUBP_REG_LIST_DCN_VM_RI(id),                       \</div><div class='ctx'>       SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id),                                 \</div><div class='hunk'>@@ -1181,6 +1195,8 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'>       SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),                                  \</div><div class='ctx'>       SR(DCHUBBUB_ARB_DRAM_STATE_CNTL), SR(DCHUBBUB_ARB_SAT_LEVEL),            \</div><div class='ctx'>       SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND), SR(DCHUBBUB_GLOBAL_TIMER_CNTL),        \</div><div class='add'>+      SR(DCHUBBUB_TEST_DEBUG_INDEX),                                           \</div><div class='add'>+      SR(DCHUBBUB_TEST_DEBUG_DATA),                                            \</div><div class='ctx'>       SR(DCHUBBUB_SOFT_RESET), SR(DCHUBBUB_CRC_CTRL),                          \</div><div class='ctx'>       SR(DCN_VM_FB_LOCATION_BASE), SR(DCN_VM_FB_LOCATION_TOP),                 \</div><div class='ctx'>       SR(DCN_VM_FB_OFFSET), SR(DCN_VM_AGP_BOT), SR(DCN_VM_AGP_TOP),            \</div><div class='hunk'>@@ -1214,7 +1230,8 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);</div><div class='ctx'>       SR(DCHUBBUB_ARB_MALL_CNTL),                                              \</div><div class='ctx'>       SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB),                    \</div><div class='ctx'>       SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS),                          \</div><div class='del'>-      SR(SDPIF_REQUEST_RATE_LIMIT)</div><div class='add'>+      SR(SDPIF_REQUEST_RATE_LIMIT),                                            \</div><div class='add'>+      SR(DCHUBBUB_SDPIF_CFG0)</div><div class='ctx'> </div><div class='ctx'> /* DCCG */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c<br/>index f98def6c8c2d..f5a4e97c40ce 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c</a></div><div class='hunk'>@@ -29,31 +29,13 @@</div><div class='ctx'> #include "dml/dcn32/display_mode_vba_util_32.h"</div><div class='ctx'> #include "dml/dcn32/dcn32_fpu.h"</div><div class='ctx'> #include "dc_state_priv.h"</div><div class='add'>+#include "dc_stream_priv.h"</div><div class='ctx'> </div><div class='ctx'> static bool is_dual_plane(enum surface_pixel_format format)</div><div class='ctx'> {</div><div class='ctx'> 	return format &gt;= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-uint32_t dcn32_helper_mall_bytes_to_ways(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		uint32_t total_size_in_mall_bytes)</div><div class='del'>-{</div><div class='del'>-	uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;</div><div class='del'>-</div><div class='del'>-	/* add 2 lines for worst case alignment */</div><div class='del'>-	cache_lines_used = total_size_in_mall_bytes / dc-&gt;caps.cache_line_size + 2;</div><div class='del'>-</div><div class='del'>-	total_cache_lines = dc-&gt;caps.max_cab_allocation_bytes / dc-&gt;caps.cache_line_size;</div><div class='del'>-	lines_per_way = total_cache_lines / dc-&gt;caps.cache_num_ways;</div><div class='del'>-	num_ways = cache_lines_used / lines_per_way;</div><div class='del'>-	if (cache_lines_used % lines_per_way &gt; 0)</div><div class='del'>-		num_ways++;</div><div class='del'>-</div><div class='del'>-	return num_ways;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='hunk'>@@ -112,8 +94,10 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(</div><div class='ctx'> 	if (context-&gt;bw_ctx.bw.dcn.mall_subvp_size_bytes &gt; 0) {</div><div class='ctx'> 		if (dc-&gt;debug.force_subvp_num_ways) {</div><div class='ctx'> 			return dc-&gt;debug.force_subvp_num_ways;</div><div class='add'>+		} else if (dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes) {</div><div class='add'>+			return dc-&gt;res_pool-&gt;funcs-&gt;calculate_mall_ways_from_bytes(dc, context-&gt;bw_ctx.bw.dcn.mall_subvp_size_bytes);</div><div class='ctx'> 		} else {</div><div class='del'>-			return dcn32_helper_mall_bytes_to_ways(dc, context-&gt;bw_ctx.bw.dcn.mall_subvp_size_bytes);</div><div class='add'>+			return 0;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -234,12 +218,12 @@ bool dcn32_is_center_timing(struct pipe_ctx *pipe)</div><div class='ctx'> 				pipe-&gt;stream-&gt;timing.v_addressable != pipe-&gt;stream-&gt;src.height) {</div><div class='ctx'> 			is_center_timing = true;</div><div class='ctx'> 		}</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (pipe-&gt;plane_state) {</div><div class='del'>-		if (pipe-&gt;stream-&gt;timing.v_addressable != pipe-&gt;plane_state-&gt;dst_rect.height &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;timing.v_addressable != pipe-&gt;plane_state-&gt;src_rect.height) {</div><div class='del'>-			is_center_timing = true;</div><div class='add'>+		if (pipe-&gt;plane_state) {</div><div class='add'>+			if (pipe-&gt;stream-&gt;timing.v_addressable != pipe-&gt;plane_state-&gt;dst_rect.height &amp;&amp;</div><div class='add'>+					pipe-&gt;stream-&gt;timing.v_addressable != pipe-&gt;plane_state-&gt;src_rect.height) {</div><div class='add'>+				is_center_timing = true;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -399,7 +383,7 @@ void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,</div><div class='ctx'> {</div><div class='ctx'> 	int i, pipe_cnt;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='del'>-	struct pipe_ctx *pipe;</div><div class='add'>+	struct pipe_ctx *pipe = 0;</div><div class='ctx'> 	bool disable_unbounded_requesting = dc-&gt;debug.disable_z9_mpc || dc-&gt;debug.disable_unbounded_requesting;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -476,7 +460,7 @@ static int get_frame_rate_at_max_stretch_100hz(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(</div><div class='del'>-		struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us)</div><div class='add'>+		struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us, int current_refresh_rate)</div><div class='ctx'> {</div><div class='ctx'> 	int refresh_rate_max_stretch_100hz;</div><div class='ctx'> 	int min_refresh_100hz;</div><div class='hunk'>@@ -490,6 +474,10 @@ static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(</div><div class='ctx'> 	if (refresh_rate_max_stretch_100hz &lt; min_refresh_100hz)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	if (fpo_candidate_stream-&gt;ctx-&gt;dc-&gt;config.enable_fpo_flicker_detection == 1 &amp;&amp;</div><div class='add'>+			!dc_stream_is_refresh_rate_range_flickerless(fpo_candidate_stream, (refresh_rate_max_stretch_100hz / 100), current_refresh_rate, false))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -557,7 +545,7 @@ struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stre</div><div class='ctx'> 		if (fpo_candidate_stream)</div><div class='ctx'> 			fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);</div><div class='ctx'> 		DC_FP_START();</div><div class='del'>-		is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, dc-&gt;debug.fpo_vactive_min_active_margin_us);</div><div class='add'>+		is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, fpo_candidate_stream, dc-&gt;debug.fpo_vactive_min_active_margin_us);</div><div class='ctx'> 		DC_FP_END();</div><div class='ctx'> 		if (!is_fpo_vactive || dc-&gt;debug.disable_fpo_vactive)</div><div class='ctx'> 			return NULL;</div><div class='hunk'>@@ -586,13 +574,15 @@ struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stre</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	fpo_vactive_margin_us = is_fpo_vactive ? dc-&gt;debug.fpo_vactive_margin_us : 0; // For now hardcode the FPO + Vactive stretch margin to be 2000us</div><div class='del'>-	if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(fpo_candidate_stream, fpo_vactive_margin_us))</div><div class='add'>+	if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(fpo_candidate_stream, fpo_vactive_margin_us, refresh_rate))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (!fpo_candidate_stream-&gt;allow_freesync)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	if (fpo_candidate_stream-&gt;vrr_active_variable &amp;&amp; dc-&gt;debug.disable_fams_gaming)</div><div class='add'>+	if (fpo_candidate_stream-&gt;vrr_active_variable &amp;&amp;</div><div class='add'>+	((dc-&gt;debug.disable_fams_gaming == INGAME_FAMS_DISABLE) ||</div><div class='add'>+	(context-&gt;stream_count &gt; 1 &amp;&amp; !(dc-&gt;debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_ENABLE))))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	return fpo_candidate_stream;</div><div class='hunk'>@@ -673,7 +663,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> </div><div class='ctx'> 				subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);</div><div class='ctx'> 				refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='del'>-					pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+					pipe-&gt;stream-&gt;timing.v_total * (unsigned long long)pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -734,7 +724,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int</div><div class='ctx'> </div><div class='ctx'> 				subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);</div><div class='ctx'> 				refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='del'>-					pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+					pipe-&gt;stream-&gt;timing.v_total * (unsigned long long)pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c<br/>index 296a0a8e7145..3466ca34c93f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c</a></div><div class='hunk'>@@ -72,7 +72,7 @@</div><div class='ctx'> #include "dml/display_mode_vba.h"</div><div class='ctx'> #include "dcn32/dcn32_dccg.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn31/dcn31_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn30/dcn30_dwb.h"</div><div class='hunk'>@@ -686,7 +686,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_AVOID,</div><div class='hunk'>@@ -732,11 +731,14 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_subvp_high_refresh = false,</div><div class='ctx'> 	.fpo_vactive_min_active_margin_us = 200,</div><div class='ctx'> 	.fpo_vactive_max_blank_us = 1000,</div><div class='del'>-	.enable_legacy_fast_update = false,</div><div class='ctx'> 	.disable_dc_mode_overwrite = true,</div><div class='ctx'> 	.using_dml2 = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct dce_aux *dcn321_aux_engine_create(</div><div class='ctx'> 	struct dc_context *ctx,</div><div class='ctx'> 	uint32_t inst)</div><div class='hunk'>@@ -1035,7 +1037,7 @@ static struct link_encoder *dcn321_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='hunk'>@@ -1288,6 +1290,8 @@ static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='ctx'> #define REG_STRUCT hpo_dp_link_enc_regs</div><div class='hunk'>@@ -1580,9 +1584,15 @@ static struct dc_cap_funcs cap_funcs = {</div><div class='ctx'> static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='ctx'> {</div><div class='ctx'> 	DC_FP_START();</div><div class='add'>+</div><div class='ctx'> 	dcn321_update_bw_bounding_box_fpu(dc, bw_params);</div><div class='add'>+</div><div class='ctx'> 	if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;current_state &amp;&amp; dc-&gt;current_state-&gt;bw_ctx.dml2)</div><div class='ctx'> 		dml2_reinit(dc, &amp;dc-&gt;dml2_options, &amp;dc-&gt;current_state-&gt;bw_ctx.dml2);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;current_state &amp;&amp; dc-&gt;current_state-&gt;bw_ctx.dml2_dc_power_source)</div><div class='add'>+		dml2_reinit(dc, &amp;dc-&gt;dml2_dc_power_options, &amp;dc-&gt;current_state-&gt;bw_ctx.dml2_dc_power_source);</div><div class='add'>+</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1610,6 +1620,9 @@ static struct resource_funcs dcn321_res_pool_funcs = {</div><div class='ctx'> 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,</div><div class='ctx'> 	.add_phantom_pipes = dcn32_add_phantom_pipes,</div><div class='ctx'> 	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,</div><div class='add'>+	.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t read_pipe_fuses(struct dc_context *ctx)</div><div class='hunk'>@@ -1694,10 +1707,13 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/</div><div class='ctx'> 	/* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/</div><div class='ctx'> 	dc-&gt;caps.max_cursor_size = 64;</div><div class='add'>+	dc-&gt;caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='ctx'> 	dc-&gt;caps.mall_size_per_mem_channel = 4;</div><div class='del'>-	dc-&gt;caps.mall_size_total = 0;</div><div class='add'>+	/* total size = mall per channel * num channels * 1024 * 1024 */</div><div class='add'>+	dc-&gt;caps.mall_size_total = dc-&gt;caps.mall_size_per_mem_channel * dc-&gt;ctx-&gt;dc_bios-&gt;vram_info.num_chans * 1048576;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;caps.cursor_cache_size = dc-&gt;caps.max_cursor_size * dc-&gt;caps.max_cursor_size * 8;</div><div class='ctx'> 	dc-&gt;caps.cache_line_size = 64;</div><div class='ctx'> 	dc-&gt;caps.cache_num_ways = 16;</div><div class='hunk'>@@ -1726,6 +1742,7 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='ctx'> 	dc-&gt;caps.dmcub_support = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -1741,8 +1758,8 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.dpp.gamma_corr = 1;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dgam_rom_for_yuv = 0;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;caps.color.dpp.hw_3d_lut = 1;</div><div class='del'>-	dc-&gt;caps.color.dpp.ogam_ram = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.hw_3d_lut = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_ram = 0;</div><div class='ctx'> 	// no OGAM ROM on DCN2 and later ASICs</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_rom_caps.srgb = 0;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_rom_caps.bt2020 = 0;</div><div class='hunk'>@@ -1760,9 +1777,14 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.preblend = true;</div><div class='add'>+</div><div class='add'>+	/* Use pipe context based otg sync logic */</div><div class='add'>+	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;config.dc_mode_clk_limit_support = true;</div><div class='ctx'> 	dc-&gt;config.enable_windowed_mpo_odm = true;</div><div class='add'>+	dc-&gt;config.disable_hbr_audio_dp2 = true;</div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='ctx'> 		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='hunk'>@@ -1778,6 +1800,7 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -1980,6 +2003,8 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='hunk'>@@ -1994,34 +2019,13 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.dcn_pipe_count = pool-&gt;base.pipe_count;</div><div class='del'>-	dc-&gt;dml2_options.use_native_pstate_optimization = false;</div><div class='ctx'> 	dc-&gt;dml2_options.use_native_soc_bb_construction = true;</div><div class='ctx'> 	dc-&gt;dml2_options.minimize_dispclk_using_odm = true;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;dml2_options.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='add'>+	resource_init_common_dml2_callbacks(dc, &amp;dc-&gt;dml2_options);</div><div class='ctx'> 	dc-&gt;dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &amp;dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &amp;dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &amp;resource_update_pipes_for_stream_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &amp;resource_update_pipes_for_plane_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_mpc_slice_index = &amp;resource_get_mpc_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_odm_slice_index = &amp;resource_get_odm_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='del'>-</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_plane = &amp;dc_state_add_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_stream = &amp;dc_state_add_phantom_stream;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_plane = &amp;dc_state_create_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_plane = &amp;dc_state_remove_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_stream = &amp;dc_state_remove_phantom_stream;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_stream = &amp;dc_state_create_phantom_stream;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_plane = &amp;dc_state_release_phantom_plane;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_stream = &amp;dc_state_release_phantom_stream;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.release_dsc = &amp;dcn20_release_dsc;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.get_pipe_subvp_type = &amp;dc_state_get_pipe_subvp_type;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.get_stream_subvp_type = &amp;dc_state_get_stream_subvp_type;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.get_paired_subvp_stream = &amp;dc_state_get_paired_subvp_stream;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool-&gt;base.funcs-&gt;calculate_mall_ways_from_bytes;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc-&gt;caps.subvp_fw_processing_delay_us;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='hunk'>@@ -2042,6 +2046,10 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	dc-&gt;dml2_options.max_segments_per_hubp = 18;</div><div class='ctx'> 	dc-&gt;dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;</div><div class='ctx'> </div><div class='add'>+	/* init DC limited DML2 options */</div><div class='add'>+	memcpy(&amp;dc-&gt;dml2_dc_power_options, &amp;dc-&gt;dml2_options, sizeof(struct dml2_configuration_options));</div><div class='add'>+	dc-&gt;dml2_dc_power_options.use_clock_dc_limits = true;</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='ctx'> create_fail:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c<br/>index 5d52853cac96..ef69898d2cc5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c</a></div><div class='hunk'>@@ -33,7 +33,7 @@</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='ctx'> #include "dcn35_resource.h"</div><div class='del'>-#include "dml2/dml2_wrapper.h"</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn20/dcn20_resource.h"</div><div class='ctx'> #include "dcn30/dcn30_resource.h"</div><div class='hunk'>@@ -61,7 +61,7 @@</div><div class='ctx'> #include "dcn31/dcn31_hpo_dp_stream_encoder.h"</div><div class='ctx'> #include "dcn31/dcn31_hpo_dp_link_encoder.h"</div><div class='ctx'> #include "dcn32/dcn32_hpo_dp_link_encoder.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn31/dcn31_apg.h"</div><div class='ctx'> #include "dcn32/dcn32_dio_link_encoder.h"</div><div class='ctx'> #include "dcn31/dcn31_vpg.h"</div><div class='hunk'>@@ -712,7 +712,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_AVOID,</div><div class='hunk'>@@ -758,18 +757,17 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 			.symclk32_se = true,</div><div class='ctx'> 			.symclk32_le = true,</div><div class='ctx'> 			.symclk_fe = true,</div><div class='del'>-			.physymclk = true,</div><div class='add'>+			.physymclk = false,</div><div class='ctx'> 			.dpiasymclk = true,</div><div class='ctx'> 		}</div><div class='ctx'> 	},</div><div class='ctx'> 	.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,</div><div class='ctx'> 	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/</div><div class='del'>-	.minimum_z8_residency_time = 2100,</div><div class='add'>+	.minimum_z8_residency_time = 1, /* Always allow when other conditions are met */</div><div class='ctx'> 	.using_dml2 = true,</div><div class='ctx'> 	.support_eDP1_5 = true,</div><div class='ctx'> 	.enable_hpo_pg_support = false,</div><div class='del'>-	.enable_legacy_fast_update = true,</div><div class='del'>-	.enable_single_display_2to1_odm_policy = false,</div><div class='add'>+	.enable_single_display_2to1_odm_policy = true,</div><div class='ctx'> 	.disable_idle_power_optimizations = false,</div><div class='ctx'> 	.dmcub_emulation = false,</div><div class='ctx'> 	.disable_boot_optimizations = false,</div><div class='hunk'>@@ -783,8 +781,14 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.psp_disabled_wa = true,</div><div class='ctx'> 	.ips2_eval_delay_us = 2000,</div><div class='ctx'> 	.ips2_entry_delay_us = 800,</div><div class='del'>-	.disable_dmub_reallow_idle = true,</div><div class='add'>+	.disable_dmub_reallow_idle = false,</div><div class='ctx'> 	.static_screen_wait_frames = 2,</div><div class='add'>+	.disable_timeout = true,</div><div class='add'>+	.min_disp_clk_khz = 50000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='hunk'>@@ -1072,7 +1076,7 @@ static struct link_encoder *dcn35_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='hunk'>@@ -1368,6 +1372,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='ctx'> #define REG_STRUCT hpo_dp_link_enc_regs</div><div class='hunk'>@@ -1714,6 +1720,7 @@ static struct clock_source *dcn35_clock_source_create(</div><div class='ctx'> 		return &amp;clk_src-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfree(clk_src);</div><div class='ctx'> 	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='hunk'>@@ -1728,25 +1735,48 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static bool dcn35_validate_bandwidth(struct dc *dc,</div><div class='add'>+static enum dc_status dcn35_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='del'>-	out = dml2_validate(dc, context, fast_validate);</div><div class='add'>+	out = dml2_validate(dc, context,</div><div class='add'>+			context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+			validate_mode);</div><div class='ctx'> </div><div class='del'>-	if (fast_validate)</div><div class='del'>-		return out;</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='add'>+		return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='ctx'> 	dcn35_decide_zstate_support(dc, context);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	return out;</div><div class='add'>+	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	plane_state-&gt;tiling_info.gfxversion = DcGfxVersion9;</div><div class='add'>+	dcn20_patch_unknown_plane_state(plane_state);</div><div class='add'>+	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='add'>+static int populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='add'>+					       struct dc_state *context,</div><div class='add'>+					       display_e2e_pipe_params_st *pipes,</div><div class='add'>+					       enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct resource_funcs dcn35_res_pool_funcs = {</div><div class='ctx'> 	.destroy = dcn35_destroy_resource_pool,</div><div class='ctx'> 	.link_enc_create = dcn35_link_encoder_create,</div><div class='hunk'>@@ -1757,7 +1787,7 @@ static struct resource_funcs dcn35_res_pool_funcs = {</div><div class='ctx'> 	.validate_bandwidth = dcn35_validate_bandwidth,</div><div class='ctx'> 	.calculate_wm_and_dlg = NULL,</div><div class='ctx'> 	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,</div><div class='del'>-	.populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu,</div><div class='add'>+	.populate_dml_pipes = populate_dml_pipes_from_context_fpu,</div><div class='ctx'> 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,</div><div class='ctx'> 	.release_pipe = dcn20_release_pipe,</div><div class='ctx'> 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,</div><div class='hunk'>@@ -1769,9 +1799,13 @@ static struct resource_funcs dcn35_res_pool_funcs = {</div><div class='ctx'> 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,</div><div class='ctx'> 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,</div><div class='ctx'> 	.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,</div><div class='del'>-	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='add'>+	.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn35_get_panel_config_defaults,</div><div class='ctx'> 	.get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,</div><div class='add'>+	.get_det_buffer_size = dcn31_get_det_buffer_size,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn35_resource_construct(</div><div class='hunk'>@@ -1824,9 +1858,9 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.max_cursor_size = 256;</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='del'>-	dc-&gt;caps.max_slave_planes = 2;</div><div class='del'>-	dc-&gt;caps.max_slave_yuv_planes = 2;</div><div class='del'>-	dc-&gt;caps.max_slave_rgb_planes = 2;</div><div class='add'>+	dc-&gt;caps.max_slave_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_yuv_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_rgb_planes = 3;</div><div class='ctx'> 	dc-&gt;caps.post_blend_color_processing = true;</div><div class='ctx'> 	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='ctx'> 	if (dc-&gt;config.forceHBR2CP2520)</div><div class='hunk'>@@ -1843,6 +1877,7 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.zstate_support = true;</div><div class='ctx'> 	dc-&gt;caps.ips_support = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -1858,7 +1893,7 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.dpp.gamma_corr = 1;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dgam_rom_for_yuv = 0;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;caps.color.dpp.hw_3d_lut = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.hw_3d_lut = 0;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1</div><div class='ctx'> 	// no OGAM ROM on DCN301</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_rom_caps.srgb = 0;</div><div class='hunk'>@@ -1877,6 +1912,10 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.preblend = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.num_of_host_routers = 2;</div><div class='add'>+	dc-&gt;caps.num_of_dpias_per_host_router = 2;</div><div class='ctx'> </div><div class='ctx'> 	/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order</div><div class='ctx'> 	 * to provide some margin.</div><div class='hunk'>@@ -1886,9 +1925,15 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 	 */</div><div class='ctx'> 	dc-&gt;caps.max_disp_clock_khz_at_vmin = 650000;</div><div class='ctx'> </div><div class='add'>+	/* Sequential ONO is based on ASIC. */</div><div class='add'>+	if (dc-&gt;ctx-&gt;asic_id.hw_internal_rev &gt;= 0x40)</div><div class='add'>+		dc-&gt;caps.sequential_ono = true;</div><div class='add'>+</div><div class='ctx'> 	/* Use pipe context based otg sync logic */</div><div class='ctx'> 	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+	dc-&gt;config.disable_hbr_audio_dp2 = true;</div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='ctx'> 		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='hunk'>@@ -1904,6 +1949,7 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='hunk'>@@ -2126,30 +2172,25 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip-&gt;max_num_dpp = pool-&gt;base.pipe_count;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.dcn_pipe_count = pool-&gt;base.pipe_count;</div><div class='del'>-	dc-&gt;dml2_options.use_native_pstate_optimization = true;</div><div class='ctx'> 	dc-&gt;dml2_options.use_native_soc_bb_construction = true;</div><div class='ctx'> 	dc-&gt;dml2_options.minimize_dispclk_using_odm = false;</div><div class='ctx'> 	if (dc-&gt;config.EnableMinDispClkODM)</div><div class='ctx'> 		dc-&gt;dml2_options.minimize_dispclk_using_odm = true;</div><div class='ctx'> 	dc-&gt;dml2_options.enable_windowed_mpo_odm = dc-&gt;config.enable_windowed_mpo_odm;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;dml2_options.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='add'>+	resource_init_common_dml2_callbacks(dc, &amp;dc-&gt;dml2_options);</div><div class='ctx'> 	dc-&gt;dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &amp;dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &amp;dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &amp;resource_update_pipes_for_stream_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &amp;resource_update_pipes_for_plane_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_mpc_slice_index = &amp;resource_get_mpc_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_odm_slice_index = &amp;resource_get_odm_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='del'>-	dc-&gt;dml2_options.max_segments_per_hubp = 24;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;dml2_options.max_segments_per_hubp = 24;</div><div class='ctx'> 	dc-&gt;dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/</div><div class='add'>+	dc-&gt;dml2_options.override_det_buffer_size_kbytes = true;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;config.sdpif_request_limit_words_per_umc == 0)</div><div class='ctx'> 		dc-&gt;config.sdpif_request_limit_words_per_umc = 16;/*todo*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h<br/>index a51c4a9eaafe..9c56ae76e0c7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h</a></div><div class='hunk'>@@ -35,6 +35,7 @@</div><div class='ctx'> </div><div class='ctx'> extern struct _vcs_dpi_ip_params_st dcn3_5_ip;</div><div class='ctx'> extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc;</div><div class='add'>+enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state);</div><div class='ctx'> </div><div class='ctx'> struct dcn35_resource_pool {</div><div class='ctx'> 	struct resource_pool base;</div><div class='hunk'>@@ -240,6 +241,8 @@ struct resource_pool *dcn35_create_resource_pool(</div><div class='ctx'> 	SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),\</div><div class='ctx'> 	SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),\</div><div class='ctx'> 	SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),\</div><div class='add'>+	SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst),\</div><div class='add'>+	SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst),\</div><div class='ctx'> 	SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),\</div><div class='ctx'> 	SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\</div><div class='ctx'> 	SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\</div><div class='hunk'>@@ -302,7 +305,8 @@ struct resource_pool *dcn35_create_resource_pool(</div><div class='ctx'> 	SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),\</div><div class='ctx'> 	SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),\</div><div class='ctx'> 	SRI_ARR(OTG_DRR_CONTROL, OTG, inst),\</div><div class='del'>-	SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst)</div><div class='add'>+	SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\</div><div class='add'>+	SRI_ARR(INTERRUPT_DEST, OTG, inst)</div><div class='ctx'> </div><div class='ctx'> /* DPP */</div><div class='ctx'> #define DPP_REG_LIST_DCN35_RI(id)\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c<br/>index 5b486400dfdb..f3c614c4490c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c</a></div><div class='hunk'>@@ -40,7 +40,7 @@</div><div class='ctx'> #include "dcn31/dcn31_hpo_dp_stream_encoder.h"</div><div class='ctx'> #include "dcn31/dcn31_hpo_dp_link_encoder.h"</div><div class='ctx'> #include "dcn32/dcn32_hpo_dp_link_encoder.h"</div><div class='del'>-#include "link.h"</div><div class='add'>+#include "link_service.h"</div><div class='ctx'> #include "dcn31/dcn31_apg.h"</div><div class='ctx'> #include "dcn32/dcn32_dio_link_encoder.h"</div><div class='ctx'> #include "dcn31/dcn31_vpg.h"</div><div class='hunk'>@@ -83,7 +83,7 @@</div><div class='ctx'> #include "vm_helper.h"</div><div class='ctx'> #include "dcn20/dcn20_vmid.h"</div><div class='ctx'> </div><div class='del'>-#include "dml2/dml2_wrapper.h"</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='hunk'>@@ -692,7 +692,6 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='ctx'> 	.force_abm_enable = false,</div><div class='del'>-	.timing_trace = false,</div><div class='ctx'> 	.clock_trace = true,</div><div class='ctx'> 	.disable_pplib_clock_request = false,</div><div class='ctx'> 	.pipe_split_policy = MPC_SPLIT_AVOID,</div><div class='hunk'>@@ -700,6 +699,8 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dcc = DCC_ENABLE,</div><div class='ctx'> 	.disable_dpp_power_gate = true,</div><div class='ctx'> 	.disable_hubp_power_gate = true,</div><div class='add'>+	.disable_optc_power_gate = true, /*should the same as above two*/</div><div class='add'>+	.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/</div><div class='ctx'> 	.disable_clock_gate = false,</div><div class='ctx'> 	.disable_dsc_power_gate = true,</div><div class='ctx'> 	.vsr_support = true,</div><div class='hunk'>@@ -734,20 +735,20 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 			.hdmichar = true,</div><div class='ctx'> 			.dpstream = true,</div><div class='ctx'> 			.symclk32_se = true,</div><div class='del'>-			.symclk32_le = true,</div><div class='add'>+			.symclk32_le = false,</div><div class='ctx'> 			.symclk_fe = true,</div><div class='del'>-			.physymclk = true,</div><div class='add'>+			.physymclk = false,</div><div class='ctx'> 			.dpiasymclk = true,</div><div class='ctx'> 		}</div><div class='ctx'> 	},</div><div class='ctx'> 	.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,</div><div class='ctx'> 	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/</div><div class='add'>+	.minimum_z8_residency_time = 1,</div><div class='ctx'> 	.using_dml2 = true,</div><div class='ctx'> 	.support_eDP1_5 = true,</div><div class='ctx'> 	.enable_hpo_pg_support = false,</div><div class='del'>-	.enable_legacy_fast_update = true,</div><div class='ctx'> 	.enable_single_display_2to1_odm_policy = true,</div><div class='del'>-	.disable_idle_power_optimizations = true,</div><div class='add'>+	.disable_idle_power_optimizations = false,</div><div class='ctx'> 	.dmcub_emulation = false,</div><div class='ctx'> 	.disable_boot_optimizations = false,</div><div class='ctx'> 	.disable_unbounded_requesting = false,</div><div class='hunk'>@@ -755,11 +756,19 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions</div><div class='ctx'> 	.enable_double_buffered_dsc_pg_support = true,</div><div class='ctx'> 	.enable_dp_dig_pixel_rate_div_policy = 1,</div><div class='del'>-	.disable_z10 = true,</div><div class='add'>+	.disable_z10 = false,</div><div class='ctx'> 	.ignore_pg = true,</div><div class='ctx'> 	.psp_disabled_wa = true,</div><div class='del'>-	.ips2_eval_delay_us = 200,</div><div class='del'>-	.ips2_entry_delay_us = 400</div><div class='add'>+	.ips2_eval_delay_us = 2000,</div><div class='add'>+	.ips2_entry_delay_us = 800,</div><div class='add'>+	.disable_dmub_reallow_idle = false,</div><div class='add'>+	.static_screen_wait_frames = 2,</div><div class='add'>+	.notify_dpia_hr_bw = true,</div><div class='add'>+	.min_disp_clk_khz = 50000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='hunk'>@@ -1047,7 +1056,7 @@ static struct link_encoder *dcn35_link_encoder_create(</div><div class='ctx'> 	struct dcn20_link_encoder *enc20 =</div><div class='ctx'> 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='ctx'> </div><div class='del'>-	if (!enc20)</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='hunk'>@@ -1343,6 +1352,8 @@ static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='ctx'> </div><div class='ctx'> 	/* allocate HPO link encoder */</div><div class='ctx'> 	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='ctx'> </div><div class='ctx'> #undef REG_STRUCT</div><div class='ctx'> #define REG_STRUCT hpo_dp_link_enc_regs</div><div class='hunk'>@@ -1689,6 +1700,7 @@ static struct clock_source *dcn35_clock_source_create(</div><div class='ctx'> 		return &amp;clk_src-&gt;base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfree(clk_src);</div><div class='ctx'> 	BREAK_TO_DEBUGGER();</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='hunk'>@@ -1703,24 +1715,40 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static bool dcn351_validate_bandwidth(struct dc *dc,</div><div class='add'>+static enum dc_status dcn351_validate_bandwidth(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='del'>-		bool fast_validate)</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='ctx'> {</div><div class='ctx'> 	bool out = false;</div><div class='ctx'> </div><div class='del'>-	out = dml2_validate(dc, context, fast_validate);</div><div class='add'>+	out = dml2_validate(dc, context,</div><div class='add'>+			context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+			validate_mode);</div><div class='ctx'> </div><div class='del'>-	if (fast_validate)</div><div class='del'>-		return out;</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='add'>+		return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='del'>-	dcn351_decide_zstate_support(dc, context);</div><div class='add'>+	dcn35_decide_zstate_support(dc, context);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	return out;</div><div class='add'>+	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='add'>+					       struct dc_state *context,</div><div class='add'>+					       display_e2e_pipe_params_st *pipes,</div><div class='add'>+					       enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static struct resource_funcs dcn351_res_pool_funcs = {</div><div class='ctx'> 	.destroy = dcn351_destroy_resource_pool,</div><div class='hunk'>@@ -1732,7 +1760,7 @@ static struct resource_funcs dcn351_res_pool_funcs = {</div><div class='ctx'> 	.validate_bandwidth = dcn351_validate_bandwidth,</div><div class='ctx'> 	.calculate_wm_and_dlg = NULL,</div><div class='ctx'> 	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,</div><div class='del'>-	.populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,</div><div class='add'>+	.populate_dml_pipes = populate_dml_pipes_from_context_fpu,</div><div class='ctx'> 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,</div><div class='ctx'> 	.release_pipe = dcn20_release_pipe,</div><div class='ctx'> 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,</div><div class='hunk'>@@ -1744,9 +1772,13 @@ static struct resource_funcs dcn351_res_pool_funcs = {</div><div class='ctx'> 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,</div><div class='ctx'> 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,</div><div class='ctx'> 	.update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,</div><div class='del'>-	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='add'>+	.patch_unknown_plane_state = dcn35_patch_unknown_plane_state,</div><div class='ctx'> 	.get_panel_config_defaults = dcn35_get_panel_config_defaults,</div><div class='ctx'> 	.get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,</div><div class='add'>+	.get_det_buffer_size = dcn31_get_det_buffer_size,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool dcn351_resource_construct(</div><div class='hunk'>@@ -1799,9 +1831,9 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.max_cursor_size = 256;</div><div class='ctx'> 	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='ctx'> 	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='del'>-	dc-&gt;caps.max_slave_planes = 2;</div><div class='del'>-	dc-&gt;caps.max_slave_yuv_planes = 2;</div><div class='del'>-	dc-&gt;caps.max_slave_rgb_planes = 2;</div><div class='add'>+	dc-&gt;caps.max_slave_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_yuv_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_rgb_planes = 3;</div><div class='ctx'> 	dc-&gt;caps.post_blend_color_processing = true;</div><div class='ctx'> 	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='ctx'> 	if (dc-&gt;config.forceHBR2CP2520)</div><div class='hunk'>@@ -1818,6 +1850,7 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.zstate_support = true;</div><div class='ctx'> 	dc-&gt;caps.ips_support = true;</div><div class='ctx'> 	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Color pipeline capabilities */</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='hunk'>@@ -1833,7 +1866,7 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.dpp.gamma_corr = 1;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.dgam_rom_for_yuv = 0;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;caps.color.dpp.hw_3d_lut = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.hw_3d_lut = 0;</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1</div><div class='ctx'> 	// no OGAM ROM on DCN301</div><div class='ctx'> 	dc-&gt;caps.color.dpp.ogam_rom_caps.srgb = 0;</div><div class='hunk'>@@ -1852,6 +1885,10 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='ctx'> 	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.preblend = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.num_of_host_routers = 2;</div><div class='add'>+	dc-&gt;caps.num_of_dpias_per_host_router = 2;</div><div class='ctx'> </div><div class='ctx'> 	/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order</div><div class='ctx'> 	 * to provide some margin.</div><div class='hunk'>@@ -1864,6 +1901,10 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 	/* Use pipe context based otg sync logic */</div><div class='ctx'> 	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+	/* Use psp mailbox to enable assr */</div><div class='add'>+	dc-&gt;config.use_assr_psp_message = true;</div><div class='add'>+</div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='ctx'> 		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='hunk'>@@ -1879,10 +1920,13 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='ctx'> 		dc-&gt;debug = debug_defaults_drv;</div><div class='ctx'> </div><div class='add'>+	/*HW default is to have all the FGCG enabled, SW no need to program them*/</div><div class='add'>+	dc-&gt;debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;</div><div class='ctx'> 	// Init the vm_helper</div><div class='ctx'> 	if (dc-&gt;vm_helper)</div><div class='ctx'> 		vm_helper_init(dc-&gt;vm_helper, 16);</div><div class='hunk'>@@ -2100,30 +2144,26 @@ static bool dcn351_resource_construct(</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='ctx'> 		dc-&gt;caps.planes[i] = plane_cap;</div><div class='ctx'> </div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;cap_funcs = cap_funcs;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dcn_ip-&gt;max_num_dpp = pool-&gt;base.pipe_count;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.dcn_pipe_count = pool-&gt;base.pipe_count;</div><div class='del'>-	dc-&gt;dml2_options.use_native_pstate_optimization = true;</div><div class='ctx'> 	dc-&gt;dml2_options.use_native_soc_bb_construction = true;</div><div class='ctx'> 	dc-&gt;dml2_options.minimize_dispclk_using_odm = false;</div><div class='ctx'> 	if (dc-&gt;config.EnableMinDispClkODM)</div><div class='ctx'> 		dc-&gt;dml2_options.minimize_dispclk_using_odm = true;</div><div class='ctx'> 	dc-&gt;dml2_options.enable_windowed_mpo_odm = dc-&gt;config.enable_windowed_mpo_odm;</div><div class='ctx'> </div><div class='del'>-	dc-&gt;dml2_options.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='add'>+	resource_init_common_dml2_callbacks(dc, &amp;dc-&gt;dml2_options);</div><div class='ctx'> 	dc-&gt;dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &amp;dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &amp;dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &amp;resource_update_pipes_for_stream_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &amp;resource_update_pipes_for_plane_with_slice_count;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_mpc_slice_index = &amp;resource_get_mpc_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_odm_slice_index = &amp;resource_get_odm_slice_index;</div><div class='del'>-	dc-&gt;dml2_options.callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='add'>+</div><div class='ctx'> 	dc-&gt;dml2_options.max_segments_per_hubp = 24;</div><div class='ctx'> 	dc-&gt;dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/</div><div class='add'>+	dc-&gt;dml2_options.override_det_buffer_size_kbytes = true;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;config.sdpif_request_limit_words_per_umc == 0)</div><div class='ctx'> 		dc-&gt;config.sdpif_request_limit_words_per_umc = 16;/*todo*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c<br/>new file mode 100644<br/>index 000000000000..6469d5fe2e6d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c</a></div><div class='hunk'>@@ -0,0 +1,2196 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+</div><div class='add'>+#include "dcn31/dcn31_init.h"</div><div class='add'>+#include "dcn35/dcn35_init.h"</div><div class='add'>+#include "dcn36/dcn36_resource.h"</div><div class='add'>+</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "include/irq_service_interface.h"</div><div class='add'>+#include "dcn36_resource.h"</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='add'>+</div><div class='add'>+#include "dcn20/dcn20_resource.h"</div><div class='add'>+#include "dcn30/dcn30_resource.h"</div><div class='add'>+#include "dcn31/dcn31_resource.h"</div><div class='add'>+#include "dcn32/dcn32_resource.h"</div><div class='add'>+#include "dcn35/dcn35_resource.h"</div><div class='add'>+</div><div class='add'>+#include "dcn10/dcn10_ipp.h"</div><div class='add'>+#include "dcn30/dcn30_hubbub.h"</div><div class='add'>+#include "dcn31/dcn31_hubbub.h"</div><div class='add'>+#include "dcn35/dcn35_hubbub.h"</div><div class='add'>+#include "dcn32/dcn32_mpc.h"</div><div class='add'>+#include "dcn35/dcn35_hubp.h"</div><div class='add'>+#include "irq/dcn36/irq_service_dcn36.h"</div><div class='add'>+#include "dcn35/dcn35_dpp.h"</div><div class='add'>+#include "dcn35/dcn35_optc.h"</div><div class='add'>+#include "dcn20/dcn20_hwseq.h"</div><div class='add'>+#include "dcn30/dcn30_hwseq.h"</div><div class='add'>+#include "dce110/dce110_hwseq.h"</div><div class='add'>+#include "dcn35/dcn35_opp.h"</div><div class='add'>+#include "dcn35/dcn35_dsc.h"</div><div class='add'>+#include "dcn30/dcn30_vpg.h"</div><div class='add'>+#include "dcn30/dcn30_afmt.h"</div><div class='add'>+#include "dcn31/dcn31_dio_link_encoder.h"</div><div class='add'>+#include "dcn35/dcn35_dio_stream_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_hpo_dp_stream_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_hpo_dp_link_encoder.h"</div><div class='add'>+#include "dcn32/dcn32_hpo_dp_link_encoder.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+#include "dcn31/dcn31_apg.h"</div><div class='add'>+#include "dcn32/dcn32_dio_link_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_vpg.h"</div><div class='add'>+#include "dcn31/dcn31_afmt.h"</div><div class='add'>+#include "dce/dce_clock_source.h"</div><div class='add'>+#include "dce/dce_audio.h"</div><div class='add'>+#include "dce/dce_hwseq.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='add'>+#include "virtual/virtual_stream_encoder.h"</div><div class='add'>+#include "dce110/dce110_resource.h"</div><div class='add'>+#include "dml/display_mode_vba.h"</div><div class='add'>+#include "dcn35/dcn35_dccg.h"</div><div class='add'>+#include "dcn35/dcn35_pg_cntl.h"</div><div class='add'>+#include "dcn10/dcn10_resource.h"</div><div class='add'>+#include "dcn31/dcn31_panel_cntl.h"</div><div class='add'>+#include "dcn35/dcn35_hwseq.h"</div><div class='add'>+#include "dcn35/dcn35_dio_link_encoder.h"</div><div class='add'>+#include "dml/dcn31/dcn31_fpu.h" /*todo*/</div><div class='add'>+#include "dml/dcn35/dcn35_fpu.h"</div><div class='add'>+#include "dcn35/dcn35_dwb.h"</div><div class='add'>+#include "dcn35/dcn35_mmhubbub.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_3_6_0_offset.h"</div><div class='add'>+#include "dcn/dcn_3_6_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#define regBIF_BX2_BIOS_SCRATCH_2                                             0x2ffc004e</div><div class='add'>+#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX                                    5</div><div class='add'>+</div><div class='add'>+#define regBIF_BX2_BIOS_SCRATCH_3                                             0x2ffc004f</div><div class='add'>+#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX                                    5</div><div class='add'>+</div><div class='add'>+#define regBIF_BX2_BIOS_SCRATCH_6                                             0x2ffc0052</div><div class='add'>+#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX                                    5</div><div class='add'>+</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                   0x0</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                     0x0000000FL</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dce/dmub_abm.h"</div><div class='add'>+#include "dce/dmub_psr.h"</div><div class='add'>+#include "dce/dmub_replay.h"</div><div class='add'>+#include "dce/dce_aux.h"</div><div class='add'>+#include "dce/dce_i2c.h"</div><div class='add'>+#include "dml/dcn31/display_mode_vba_31.h" /*temp*/</div><div class='add'>+#include "vm_helper.h"</div><div class='add'>+#include "dcn20/dcn20_vmid.h"</div><div class='add'>+</div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+</div><div class='add'>+#include "link_enc_cfg.h"</div><div class='add'>+#define DC_LOGGER_INIT(logger)</div><div class='add'>+</div><div class='add'>+enum dcn36_clk_src_array_id {</div><div class='add'>+	DCN36_CLK_SRC_PLL0,</div><div class='add'>+	DCN36_CLK_SRC_PLL1,</div><div class='add'>+	DCN36_CLK_SRC_PLL2,</div><div class='add'>+	DCN36_CLK_SRC_PLL3,</div><div class='add'>+	DCN36_CLK_SRC_PLL4,</div><div class='add'>+	DCN36_CLK_SRC_TOTAL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* begin *********************</div><div class='add'>+ * macros to expend register list macro defined in HW object header file</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* DCN */</div><div class='add'>+/* TODO awful hack. fixup dcn20_dwb.h */</div><div class='add'>+#undef BASE_INNER</div><div class='add'>+#define BASE_INNER(seg) ctx-&gt;dcn_reg_offsets[seg]</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SR(reg_name)\</div><div class='add'>+		REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \</div><div class='add'>+					reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define SR_ARR(reg_name, id) \</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name</div><div class='add'>+</div><div class='add'>+#define SR_ARR_INIT(reg_name, id, value) \</div><div class='add'>+	REG_STRUCT[id].reg_name = value</div><div class='add'>+</div><div class='add'>+#define SRI(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+					reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_ARR(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SR_ARR_I2C(reg_name, id) \</div><div class='add'>+	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_ARR_I2C(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_ARR_ALPHABET(reg_name, block, index, id)\</div><div class='add'>+	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI2(reg_name, block, id)\</div><div class='add'>+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \</div><div class='add'>+					reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI2_ARR(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +	\</div><div class='add'>+		reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRIR(var_name, reg_name, block, id)\</div><div class='add'>+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+					reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+					reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII_ARR_2(reg_name, block, id, inst)\</div><div class='add'>+	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII_MPC_RMU(reg_name, block, id)\</div><div class='add'>+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+					reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII_DWB(reg_name, temp_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## temp_name</div><div class='add'>+</div><div class='add'>+#define SF_DWB2(reg_name, block, id, field_name, post_fix) \</div><div class='add'>+	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+#define DCCG_SRII(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define VUPDATE_SRII(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \</div><div class='add'>+		reg ## reg_name ## _ ## block ## id</div><div class='add'>+</div><div class='add'>+/* NBIO */</div><div class='add'>+#define NBIO_BASE_INNER(seg) ctx-&gt;nbio_reg_offsets[seg]</div><div class='add'>+</div><div class='add'>+#define NBIO_BASE(seg) \</div><div class='add'>+	NBIO_BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define NBIO_SR(reg_name)\</div><div class='add'>+	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+				regBIF_BX2_ ## reg_name</div><div class='add'>+</div><div class='add'>+#define NBIO_SR_ARR(reg_name, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		regBIF_BX2_ ## reg_name</div><div class='add'>+</div><div class='add'>+#define bios_regs_init() \</div><div class='add'>+		( \</div><div class='add'>+		NBIO_SR(BIOS_SCRATCH_3),\</div><div class='add'>+		NBIO_SR(BIOS_SCRATCH_6)\</div><div class='add'>+		)</div><div class='add'>+</div><div class='add'>+static struct bios_registers bios_regs;</div><div class='add'>+</div><div class='add'>+#define clk_src_regs_init(index, pllid)\</div><div class='add'>+	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)</div><div class='add'>+</div><div class='add'>+static struct dce110_clk_src_regs clk_src_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dce110_clk_src_shift cs_shift = {</div><div class='add'>+		CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce110_clk_src_mask cs_mask = {</div><div class='add'>+		CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define abm_regs_init(id)\</div><div class='add'>+		ABM_DCN32_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dce_abm_registers abm_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dce_abm_shift abm_shift = {</div><div class='add'>+		ABM_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_abm_mask abm_mask = {</div><div class='add'>+		ABM_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define audio_regs_init(id)\</div><div class='add'>+		AUD_COMMON_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dce_audio_registers audio_regs[7];</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\</div><div class='add'>+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\</div><div class='add'>+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\</div><div class='add'>+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)</div><div class='add'>+</div><div class='add'>+static const struct dce_audio_shift audio_shift = {</div><div class='add'>+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_audio_mask audio_mask = {</div><div class='add'>+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define vpg_regs_init(id)\</div><div class='add'>+	VPG_DCN31_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_vpg_registers vpg_regs[10];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_vpg_shift vpg_shift = {</div><div class='add'>+	DCN31_VPG_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_vpg_mask vpg_mask = {</div><div class='add'>+	DCN31_VPG_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define afmt_regs_init(id)\</div><div class='add'>+	AFMT_DCN31_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_afmt_registers afmt_regs[6];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_afmt_shift afmt_shift = {</div><div class='add'>+	DCN31_AFMT_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_afmt_mask afmt_mask = {</div><div class='add'>+	DCN31_AFMT_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define apg_regs_init(id)\</div><div class='add'>+	APG_DCN31_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_apg_registers apg_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_apg_shift apg_shift = {</div><div class='add'>+	DCN31_APG_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_apg_mask apg_mask = {</div><div class='add'>+	DCN31_APG_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define stream_enc_regs_init(id)\</div><div class='add'>+	SE_DCN35_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_stream_enc_registers stream_enc_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dcn10_stream_encoder_shift se_shift = {</div><div class='add'>+		SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn10_stream_encoder_mask se_mask = {</div><div class='add'>+		SE_COMMON_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define aux_regs_init(id)\</div><div class='add'>+	DCN2_AUX_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];</div><div class='add'>+</div><div class='add'>+#define hpd_regs_init(id)\</div><div class='add'>+	HPD_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static const struct dce110_aux_registers_shift aux_shift = {</div><div class='add'>+	DCN_AUX_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce110_aux_registers_mask aux_mask = {</div><div class='add'>+	DCN_AUX_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define link_regs_init(id, phyid)\</div><div class='add'>+	( \</div><div class='add'>+	LE_DCN35_REG_LIST_RI(id), \</div><div class='add'>+	UNIPHY_DCN2_REG_LIST_RI(id, phyid)\</div><div class='add'>+	)</div><div class='add'>+</div><div class='add'>+static struct dcn10_link_enc_registers link_enc_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dcn10_link_enc_shift le_shift = {</div><div class='add'>+	LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \</div><div class='add'>+	//DPCS_DCN31_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn10_link_enc_mask le_mask = {</div><div class='add'>+	LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \</div><div class='add'>+	//DPCS_DCN31_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define hpo_dp_stream_encoder_reg_init(id)\</div><div class='add'>+	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {</div><div class='add'>+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {</div><div class='add'>+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define hpo_dp_link_encoder_reg_init(id)\</div><div class='add'>+	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {</div><div class='add'>+	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {</div><div class='add'>+	DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define dpp_regs_init(id)\</div><div class='add'>+	DPP_REG_LIST_DCN35_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn3_dpp_registers dpp_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn35_dpp_shift tf_shift = {</div><div class='add'>+		DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn35_dpp_mask tf_mask = {</div><div class='add'>+		DPP_REG_LIST_SH_MASK_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define opp_regs_init(id)\</div><div class='add'>+	OPP_REG_LIST_DCN35_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn35_opp_registers opp_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn35_opp_shift opp_shift = {</div><div class='add'>+	OPP_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn35_opp_mask opp_mask = {</div><div class='add'>+	OPP_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define aux_engine_regs_init(id)\</div><div class='add'>+	( \</div><div class='add'>+	AUX_COMMON_REG_LIST0_RI(id), \</div><div class='add'>+	SR_ARR_INIT(AUXN_IMPCAL, id, 0), \</div><div class='add'>+	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \</div><div class='add'>+	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \</div><div class='add'>+	)</div><div class='add'>+</div><div class='add'>+static struct dce110_aux_registers aux_engine_regs[5];</div><div class='add'>+</div><div class='add'>+#define dwbc_regs_dcn3_init(id)\</div><div class='add'>+	DWBC_COMMON_REG_LIST_DCN30_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn30_dwbc_registers dwbc35_regs[1];</div><div class='add'>+</div><div class='add'>+static const struct dcn35_dwbc_shift dwbc35_shift = {</div><div class='add'>+	DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn35_dwbc_mask dwbc35_mask = {</div><div class='add'>+	DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define mcif_wb_regs_dcn3_init(id)\</div><div class='add'>+	MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];</div><div class='add'>+</div><div class='add'>+static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {</div><div class='add'>+	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {</div><div class='add'>+	MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define dsc_regsDCN35_init(id)\</div><div class='add'>+	DSC_REG_LIST_DCN20_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn20_dsc_registers dsc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn35_dsc_shift dsc_shift = {</div><div class='add'>+	DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn35_dsc_mask dsc_mask = {</div><div class='add'>+	DSC_REG_LIST_SH_MASK_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dcn30_mpc_registers mpc_regs;</div><div class='add'>+</div><div class='add'>+#define dcn_mpc_regs_init() \</div><div class='add'>+	MPC_REG_LIST_DCN3_2_RI(0),\</div><div class='add'>+	MPC_REG_LIST_DCN3_2_RI(1),\</div><div class='add'>+	MPC_REG_LIST_DCN3_2_RI(2),\</div><div class='add'>+	MPC_REG_LIST_DCN3_2_RI(3),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\</div><div class='add'>+	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)</div><div class='add'>+</div><div class='add'>+static const struct dcn30_mpc_shift mpc_shift = {</div><div class='add'>+	MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn30_mpc_mask mpc_mask = {</div><div class='add'>+	MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define optc_regs_init(id)\</div><div class='add'>+	OPTC_COMMON_REG_LIST_DCN3_5_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn_optc_registers optc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn_optc_shift optc_shift = {</div><div class='add'>+	OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn_optc_mask optc_mask = {</div><div class='add'>+	OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define hubp_regs_init(id)\</div><div class='add'>+	HUBP_REG_LIST_DCN30_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn_hubp2_registers hubp_regs[4];</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static const struct dcn35_hubp2_shift hubp_shift = {</div><div class='add'>+		HUBP_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn35_hubp2_mask hubp_mask = {</div><div class='add'>+		HUBP_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dcn_hubbub_registers hubbub_reg;</div><div class='add'>+</div><div class='add'>+#define hubbub_reg_init()\</div><div class='add'>+		HUBBUB_REG_LIST_DCN35(0)</div><div class='add'>+</div><div class='add'>+static const struct dcn_hubbub_shift hubbub_shift = {</div><div class='add'>+		HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn_hubbub_mask hubbub_mask = {</div><div class='add'>+		HUBBUB_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dccg_registers dccg_regs;</div><div class='add'>+</div><div class='add'>+#define dccg_regs_init()\</div><div class='add'>+	DCCG_REG_LIST_DCN35()</div><div class='add'>+</div><div class='add'>+static const struct dccg_shift dccg_shift = {</div><div class='add'>+		DCCG_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dccg_mask dccg_mask = {</div><div class='add'>+		DCCG_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct pg_cntl_registers pg_cntl_regs;</div><div class='add'>+</div><div class='add'>+#define pg_cntl_dcn35_regs_init() \</div><div class='add'>+	PG_CNTL_REG_LIST_DCN35()</div><div class='add'>+</div><div class='add'>+static const struct pg_cntl_shift pg_cntl_shift = {</div><div class='add'>+		PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct pg_cntl_mask pg_cntl_mask = {</div><div class='add'>+		PG_CNTL_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define SRII2(reg_name_pre, reg_name_post, id)\</div><div class='add'>+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \</div><div class='add'>+			## id ## _ ## reg_name_post ## _BASE_IDX) + \</div><div class='add'>+			reg ## reg_name_pre ## id ## _ ## reg_name_post</div><div class='add'>+</div><div class='add'>+static struct dce_hwseq_registers hwseq_reg;</div><div class='add'>+</div><div class='add'>+#define hwseq_reg_init()\</div><div class='add'>+	HWSEQ_DCN36_REG_LIST()</div><div class='add'>+</div><div class='add'>+#define HWSEQ_DCN36_MASK_SH_LIST(mask_sh)\</div><div class='add'>+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \</div><div class='add'>+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \</div><div class='add'>+	HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \</div><div class='add'>+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \</div><div class='add'>+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \</div><div class='add'>+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \</div><div class='add'>+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \</div><div class='add'>+	HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \</div><div class='add'>+	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)</div><div class='add'>+</div><div class='add'>+static const struct dce_hwseq_shift hwseq_shift = {</div><div class='add'>+		HWSEQ_DCN36_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_hwseq_mask hwseq_mask = {</div><div class='add'>+		HWSEQ_DCN36_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define vmid_regs_init(id)\</div><div class='add'>+		DCN20_VMID_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn_vmid_registers vmid_regs[16];</div><div class='add'>+</div><div class='add'>+static const struct dcn20_vmid_shift vmid_shifts = {</div><div class='add'>+		DCN20_VMID_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn20_vmid_mask vmid_masks = {</div><div class='add'>+		DCN20_VMID_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct resource_caps res_cap_dcn36 = {</div><div class='add'>+	.num_timing_generator = 4,</div><div class='add'>+	.num_opp = 4,</div><div class='add'>+	.num_video_plane = 4,</div><div class='add'>+	.num_audio = 5,</div><div class='add'>+	.num_stream_encoder = 5,</div><div class='add'>+	.num_dig_link_enc = 5,</div><div class='add'>+	.num_hpo_dp_stream_encoder = 4,</div><div class='add'>+	.num_hpo_dp_link_encoder = 2,</div><div class='add'>+	.num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/</div><div class='add'>+	.num_dwb = 1,</div><div class='add'>+	.num_ddc = 5,</div><div class='add'>+	.num_vmid = 16,</div><div class='add'>+	.num_mpc_3dlut = 2,</div><div class='add'>+	.num_dsc = 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_plane_cap plane_cap = {</div><div class='add'>+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,</div><div class='add'>+	.per_pixel_alpha = true,</div><div class='add'>+</div><div class='add'>+	.pixel_format_support = {</div><div class='add'>+			.argb8888 = true,</div><div class='add'>+			.nv12 = true,</div><div class='add'>+			.fp16 = true,</div><div class='add'>+			.p010 = true,</div><div class='add'>+			.ayuv = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	.max_upscale_factor = {</div><div class='add'>+			.argb8888 = 16000,</div><div class='add'>+			.nv12 = 16000,</div><div class='add'>+			.fp16 = 16000</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// 6:1 downscaling ratio: 1000/6 = 166.666</div><div class='add'>+	.max_downscale_factor = {</div><div class='add'>+			.argb8888 = 250,</div><div class='add'>+			.nv12 = 167,</div><div class='add'>+			.fp16 = 167</div><div class='add'>+	},</div><div class='add'>+	64,</div><div class='add'>+	64</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_debug_options debug_defaults_drv = {</div><div class='add'>+	.disable_dmcu = true,</div><div class='add'>+	.force_abm_enable = false,</div><div class='add'>+	.clock_trace = true,</div><div class='add'>+	.disable_pplib_clock_request = false,</div><div class='add'>+	.pipe_split_policy = MPC_SPLIT_AVOID,</div><div class='add'>+	.force_single_disp_pipe_split = false,</div><div class='add'>+	.disable_dcc = DCC_ENABLE,</div><div class='add'>+	.disable_dpp_power_gate = true,</div><div class='add'>+	.disable_hubp_power_gate = true,</div><div class='add'>+	.disable_optc_power_gate = true, /*should the same as above two*/</div><div class='add'>+	.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/</div><div class='add'>+	.disable_clock_gate = false,</div><div class='add'>+	.disable_dsc_power_gate = true,</div><div class='add'>+	.vsr_support = true,</div><div class='add'>+	.performance_trace = false,</div><div class='add'>+	.max_downscale_src_width = 4096,/*upto true 4k*/</div><div class='add'>+	.disable_pplib_wm_range = false,</div><div class='add'>+	.scl_reset_length10 = true,</div><div class='add'>+	.sanity_checks = false,</div><div class='add'>+	.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='add'>+	.dwb_fi_phase = -1, // -1 = disable,</div><div class='add'>+	.dmub_command_table = true,</div><div class='add'>+	.pstate_enabled = true,</div><div class='add'>+	.use_max_lb = true,</div><div class='add'>+	.enable_mem_low_power = {</div><div class='add'>+		.bits = {</div><div class='add'>+			.vga = false,</div><div class='add'>+			.i2c = true,</div><div class='add'>+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled</div><div class='add'>+			.dscl = true,</div><div class='add'>+			.cm = true,</div><div class='add'>+			.mpc = true,</div><div class='add'>+			.optc = true,</div><div class='add'>+			.vpg = true,</div><div class='add'>+			.afmt = true,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	.root_clock_optimization = {</div><div class='add'>+		.bits = {</div><div class='add'>+			.dpp = true,</div><div class='add'>+			.dsc = true,/*dscclk and dsc pg*/</div><div class='add'>+			.hdmistream = true,</div><div class='add'>+			.hdmichar = true,</div><div class='add'>+			.dpstream = true,</div><div class='add'>+			.symclk32_se = true,</div><div class='add'>+			.symclk32_le = true,</div><div class='add'>+			.symclk_fe = true,</div><div class='add'>+			.physymclk = false,</div><div class='add'>+			.dpiasymclk = true,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,</div><div class='add'>+	.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/</div><div class='add'>+	.minimum_z8_residency_time = 1, /* Always allow when other conditions are met */</div><div class='add'>+	.using_dml2 = true,</div><div class='add'>+	.support_eDP1_5 = true,</div><div class='add'>+	.enable_hpo_pg_support = false,</div><div class='add'>+	.enable_single_display_2to1_odm_policy = true,</div><div class='add'>+	.disable_idle_power_optimizations = false,</div><div class='add'>+	.dmcub_emulation = false,</div><div class='add'>+	.disable_boot_optimizations = false,</div><div class='add'>+	.disable_unbounded_requesting = false,</div><div class='add'>+	.disable_mem_low_power = false,</div><div class='add'>+	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions</div><div class='add'>+	.enable_double_buffered_dsc_pg_support = true,</div><div class='add'>+	.enable_dp_dig_pixel_rate_div_policy = 1,</div><div class='add'>+	.disable_z10 = false,</div><div class='add'>+	.ignore_pg = true,</div><div class='add'>+	.psp_disabled_wa = true,</div><div class='add'>+	.ips2_eval_delay_us = 2000,</div><div class='add'>+	.ips2_entry_delay_us = 800,</div><div class='add'>+	.disable_dmub_reallow_idle = false,</div><div class='add'>+	.static_screen_wait_frames = 2,</div><div class='add'>+	.disable_timeout = true,</div><div class='add'>+	.min_disp_clk_khz = 50000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_panel_config panel_config_defaults = {</div><div class='add'>+	.psr = {</div><div class='add'>+		.disable_psr = false,</div><div class='add'>+		.disallow_psrsu = false,</div><div class='add'>+		.disallow_replay = false,</div><div class='add'>+	},</div><div class='add'>+	.ilr = {</div><div class='add'>+		.optimize_edp_link_rate = true,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn35_dpp_destroy(struct dpp **dpp)</div><div class='add'>+{</div><div class='add'>+	kfree(TO_DCN20_DPP(*dpp));</div><div class='add'>+	*dpp = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);</div><div class='add'>+	bool success = (dpp != NULL);</div><div class='add'>+</div><div class='add'>+	if (!success)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dpp_regs</div><div class='add'>+	dpp_regs_init(0),</div><div class='add'>+	dpp_regs_init(1),</div><div class='add'>+	dpp_regs_init(2),</div><div class='add'>+	dpp_regs_init(3);</div><div class='add'>+</div><div class='add'>+	success = dpp35_construct(dpp, ctx, inst, &amp;dpp_regs[inst], &amp;tf_shift,</div><div class='add'>+				  &amp;tf_mask);</div><div class='add'>+	if (success) {</div><div class='add'>+		dpp35_set_fgcg(</div><div class='add'>+			dpp,</div><div class='add'>+			ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.dpp);</div><div class='add'>+		return &amp;dpp-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	kfree(dpp);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct output_pixel_processor *dcn35_opp_create(</div><div class='add'>+	struct dc_context *ctx, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_opp *opp =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!opp) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT opp_regs</div><div class='add'>+	opp_regs_init(0),</div><div class='add'>+	opp_regs_init(1),</div><div class='add'>+	opp_regs_init(2),</div><div class='add'>+	opp_regs_init(3);</div><div class='add'>+</div><div class='add'>+	dcn35_opp_construct(opp, ctx, inst,</div><div class='add'>+			&amp;opp_regs[inst], &amp;opp_shift, &amp;opp_mask);</div><div class='add'>+</div><div class='add'>+	dcn35_opp_set_fgcg(opp, ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.opp);</div><div class='add'>+</div><div class='add'>+	return &amp;opp-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dce_aux *dcn31_aux_engine_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct aux_engine_dce110 *aux_engine =</div><div class='add'>+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!aux_engine)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT aux_engine_regs</div><div class='add'>+	aux_engine_regs_init(0),</div><div class='add'>+	aux_engine_regs_init(1),</div><div class='add'>+	aux_engine_regs_init(2),</div><div class='add'>+	aux_engine_regs_init(3),</div><div class='add'>+	aux_engine_regs_init(4);</div><div class='add'>+</div><div class='add'>+	dce110_aux_engine_construct(aux_engine, ctx, inst,</div><div class='add'>+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,</div><div class='add'>+				    &amp;aux_engine_regs[inst],</div><div class='add'>+					&amp;aux_mask,</div><div class='add'>+					&amp;aux_shift,</div><div class='add'>+					ctx-&gt;dc-&gt;caps.extended_aux_timeout_support);</div><div class='add'>+</div><div class='add'>+	return &amp;aux_engine-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define i2c_inst_regs_init(id)\</div><div class='add'>+	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dce_i2c_registers i2c_hw_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dce_i2c_shift i2c_shifts = {</div><div class='add'>+		I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_i2c_mask i2c_masks = {</div><div class='add'>+		I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ========================================================== */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * DPIA index | Preferred Encoder     |    Host Router</div><div class='add'>+ *   0        |      C                |       0</div><div class='add'>+ *   1        |      First Available  |       0</div><div class='add'>+ *   2        |      D                |       1</div><div class='add'>+ *   3        |      First Available  |       1</div><div class='add'>+ */</div><div class='add'>+/* ========================================================== */</div><div class='add'>+static const enum engine_id dpia_to_preferred_enc_id_table[] = {</div><div class='add'>+		ENGINE_ID_DIGC,</div><div class='add'>+		ENGINE_ID_DIGC,</div><div class='add'>+		ENGINE_ID_DIGD,</div><div class='add'>+		ENGINE_ID_DIGD</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static enum engine_id dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index)</div><div class='add'>+{</div><div class='add'>+	return dpia_to_preferred_enc_id_table[dpia_index];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dce_i2c_hw *dcn31_i2c_hw_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dce_i2c_hw *dce_i2c_hw =</div><div class='add'>+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!dce_i2c_hw)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT i2c_hw_regs</div><div class='add'>+	i2c_inst_regs_init(1),</div><div class='add'>+	i2c_inst_regs_init(2),</div><div class='add'>+	i2c_inst_regs_init(3),</div><div class='add'>+	i2c_inst_regs_init(4),</div><div class='add'>+	i2c_inst_regs_init(5);</div><div class='add'>+</div><div class='add'>+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,</div><div class='add'>+				    &amp;i2c_hw_regs[inst], &amp;i2c_shifts, &amp;i2c_masks);</div><div class='add'>+</div><div class='add'>+	return dce_i2c_hw;</div><div class='add'>+}</div><div class='add'>+static struct mpc *dcn35_mpc_create(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		int num_mpcc,</div><div class='add'>+		int num_rmu)</div><div class='add'>+{</div><div class='add'>+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!mpc30)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT mpc_regs</div><div class='add'>+	dcn_mpc_regs_init();</div><div class='add'>+</div><div class='add'>+	dcn32_mpc_construct(mpc30, ctx,</div><div class='add'>+			&amp;mpc_regs,</div><div class='add'>+			&amp;mpc_shift,</div><div class='add'>+			&amp;mpc_mask,</div><div class='add'>+			num_mpcc,</div><div class='add'>+			num_rmu);</div><div class='add'>+</div><div class='add'>+	return &amp;mpc30-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),</div><div class='add'>+					  GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!hubbub3)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hubbub_reg</div><div class='add'>+	hubbub_reg_init();</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT vmid_regs</div><div class='add'>+	vmid_regs_init(0),</div><div class='add'>+	vmid_regs_init(1),</div><div class='add'>+	vmid_regs_init(2),</div><div class='add'>+	vmid_regs_init(3),</div><div class='add'>+	vmid_regs_init(4),</div><div class='add'>+	vmid_regs_init(5),</div><div class='add'>+	vmid_regs_init(6),</div><div class='add'>+	vmid_regs_init(7),</div><div class='add'>+	vmid_regs_init(8),</div><div class='add'>+	vmid_regs_init(9),</div><div class='add'>+	vmid_regs_init(10),</div><div class='add'>+	vmid_regs_init(11),</div><div class='add'>+	vmid_regs_init(12),</div><div class='add'>+	vmid_regs_init(13),</div><div class='add'>+	vmid_regs_init(14),</div><div class='add'>+	vmid_regs_init(15);</div><div class='add'>+</div><div class='add'>+	hubbub35_construct(hubbub3, ctx,</div><div class='add'>+			&amp;hubbub_reg,</div><div class='add'>+			&amp;hubbub_shift,</div><div class='add'>+			&amp;hubbub_mask,</div><div class='add'>+			384,/*ctx-&gt;dc-&gt;dml.ip.det_buffer_size_kbytes,*/</div><div class='add'>+			8, /*ctx-&gt;dc-&gt;dml.ip.pixel_chunk_size_kbytes,*/</div><div class='add'>+			1792 /*ctx-&gt;dc-&gt;dml.ip.config_return_buffer_size_in_kbytes*/);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; res_cap_dcn36.num_vmid; i++) {</div><div class='add'>+		struct dcn20_vmid *vmid = &amp;hubbub3-&gt;vmid[i];</div><div class='add'>+</div><div class='add'>+		vmid-&gt;ctx = ctx;</div><div class='add'>+</div><div class='add'>+		vmid-&gt;regs = &amp;vmid_regs[i];</div><div class='add'>+		vmid-&gt;shifts = &amp;vmid_shifts;</div><div class='add'>+		vmid-&gt;masks = &amp;vmid_masks;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;hubbub3-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct timing_generator *dcn35_timing_generator_create(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		uint32_t instance)</div><div class='add'>+{</div><div class='add'>+	struct optc *tgn10 =</div><div class='add'>+		kzalloc(sizeof(struct optc), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!tgn10)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT optc_regs</div><div class='add'>+	optc_regs_init(0),</div><div class='add'>+	optc_regs_init(1),</div><div class='add'>+	optc_regs_init(2),</div><div class='add'>+	optc_regs_init(3);</div><div class='add'>+</div><div class='add'>+	tgn10-&gt;base.inst = instance;</div><div class='add'>+	tgn10-&gt;base.ctx = ctx;</div><div class='add'>+</div><div class='add'>+	tgn10-&gt;tg_regs = &amp;optc_regs[instance];</div><div class='add'>+	tgn10-&gt;tg_shift = &amp;optc_shift;</div><div class='add'>+	tgn10-&gt;tg_mask = &amp;optc_mask;</div><div class='add'>+</div><div class='add'>+	dcn35_timing_generator_init(tgn10);</div><div class='add'>+</div><div class='add'>+	return &amp;tgn10-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct encoder_feature_support link_enc_feature = {</div><div class='add'>+		.max_hdmi_deep_color = COLOR_DEPTH_121212,</div><div class='add'>+		.max_hdmi_pixel_clock = 600000,</div><div class='add'>+		.hdmi_ycbcr420_supported = true,</div><div class='add'>+		.dp_ycbcr420_supported = true,</div><div class='add'>+		.fec_supported = true,</div><div class='add'>+		.flags.bits.IS_HBR2_CAPABLE = true,</div><div class='add'>+		.flags.bits.IS_HBR3_CAPABLE = true,</div><div class='add'>+		.flags.bits.IS_TPS3_CAPABLE = true,</div><div class='add'>+		.flags.bits.IS_TPS4_CAPABLE = true</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct link_encoder *dcn35_link_encoder_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct encoder_init_data *enc_init_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_link_encoder *enc20 =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT link_enc_aux_regs</div><div class='add'>+	aux_regs_init(0),</div><div class='add'>+	aux_regs_init(1),</div><div class='add'>+	aux_regs_init(2),</div><div class='add'>+	aux_regs_init(3),</div><div class='add'>+	aux_regs_init(4);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT link_enc_hpd_regs</div><div class='add'>+	hpd_regs_init(0),</div><div class='add'>+	hpd_regs_init(1),</div><div class='add'>+	hpd_regs_init(2),</div><div class='add'>+	hpd_regs_init(3),</div><div class='add'>+	hpd_regs_init(4);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT link_enc_regs</div><div class='add'>+	link_regs_init(0, A),</div><div class='add'>+	link_regs_init(1, B),</div><div class='add'>+	link_regs_init(2, C),</div><div class='add'>+	link_regs_init(3, D),</div><div class='add'>+	link_regs_init(4, E);</div><div class='add'>+</div><div class='add'>+	dcn35_link_encoder_construct(enc20,</div><div class='add'>+			enc_init_data,</div><div class='add'>+			&amp;link_enc_feature,</div><div class='add'>+			&amp;link_enc_regs[enc_init_data-&gt;transmitter],</div><div class='add'>+			&amp;link_enc_aux_regs[enc_init_data-&gt;channel - 1],</div><div class='add'>+			&amp;link_enc_hpd_regs[enc_init_data-&gt;hpd_source],</div><div class='add'>+			&amp;le_shift,</div><div class='add'>+			&amp;le_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;enc20-&gt;enc10.base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Create a minimal link encoder object not associated with a particular</div><div class='add'>+ * physical connector.</div><div class='add'>+ * resource_funcs.link_enc_create_minimal</div><div class='add'>+ */</div><div class='add'>+static struct link_encoder *dcn31_link_enc_create_minimal(</div><div class='add'>+		struct dc_context *ctx, enum engine_id eng_id)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_link_encoder *enc20;</div><div class='add'>+</div><div class='add'>+	if ((eng_id - ENGINE_ID_DIGA) &gt; ctx-&gt;dc-&gt;res_pool-&gt;res_cap-&gt;num_dig_link_enc)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!enc20)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dcn31_link_encoder_construct_minimal(</div><div class='add'>+			enc20,</div><div class='add'>+			ctx,</div><div class='add'>+			&amp;link_enc_feature,</div><div class='add'>+			&amp;link_enc_regs[eng_id - ENGINE_ID_DIGA],</div><div class='add'>+			eng_id);</div><div class='add'>+</div><div class='add'>+	return &amp;enc20-&gt;enc10.base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_panel_cntl *panel_cntl =</div><div class='add'>+		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!panel_cntl)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dcn31_panel_cntl_construct(panel_cntl, init_data);</div><div class='add'>+</div><div class='add'>+	return &amp;panel_cntl-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_dce_straps(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct resource_straps *straps)</div><div class='add'>+{</div><div class='add'>+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),</div><div class='add'>+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &amp;straps-&gt;dc_pinstraps_audio);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct audio *dcn31_create_audio(</div><div class='add'>+		struct dc_context *ctx, unsigned int inst)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT audio_regs</div><div class='add'>+	audio_regs_init(0),</div><div class='add'>+	audio_regs_init(1),</div><div class='add'>+	audio_regs_init(2),</div><div class='add'>+	audio_regs_init(3),</div><div class='add'>+	audio_regs_init(4);</div><div class='add'>+	audio_regs_init(5);</div><div class='add'>+	audio_regs_init(6);</div><div class='add'>+</div><div class='add'>+	return dce_audio_create(ctx, inst,</div><div class='add'>+			&amp;audio_regs[inst], &amp;audio_shift, &amp;audio_mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct vpg *dcn31_vpg_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!vpg31)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT vpg_regs</div><div class='add'>+	vpg_regs_init(0),</div><div class='add'>+	vpg_regs_init(1),</div><div class='add'>+	vpg_regs_init(2),</div><div class='add'>+	vpg_regs_init(3),</div><div class='add'>+	vpg_regs_init(4),</div><div class='add'>+	vpg_regs_init(5),</div><div class='add'>+	vpg_regs_init(6),</div><div class='add'>+	vpg_regs_init(7),</div><div class='add'>+	vpg_regs_init(8),</div><div class='add'>+	vpg_regs_init(9);</div><div class='add'>+</div><div class='add'>+	vpg31_construct(vpg31, ctx, inst,</div><div class='add'>+			&amp;vpg_regs[inst],</div><div class='add'>+			&amp;vpg_shift,</div><div class='add'>+			&amp;vpg_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;vpg31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct afmt *dcn31_afmt_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!afmt31)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT afmt_regs</div><div class='add'>+	afmt_regs_init(0),</div><div class='add'>+	afmt_regs_init(1),</div><div class='add'>+	afmt_regs_init(2),</div><div class='add'>+	afmt_regs_init(3),</div><div class='add'>+	afmt_regs_init(4),</div><div class='add'>+	afmt_regs_init(5);</div><div class='add'>+</div><div class='add'>+	afmt31_construct(afmt31, ctx, inst,</div><div class='add'>+			&amp;afmt_regs[inst],</div><div class='add'>+			&amp;afmt_shift,</div><div class='add'>+			&amp;afmt_mask);</div><div class='add'>+</div><div class='add'>+	// Light sleep by default, no need to power down here</div><div class='add'>+</div><div class='add'>+	return &amp;afmt31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct apg *dcn31_apg_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!apg31)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT apg_regs</div><div class='add'>+	apg_regs_init(0),</div><div class='add'>+	apg_regs_init(1),</div><div class='add'>+	apg_regs_init(2),</div><div class='add'>+	apg_regs_init(3);</div><div class='add'>+</div><div class='add'>+	apg31_construct(apg31, ctx, inst,</div><div class='add'>+			&amp;apg_regs[inst],</div><div class='add'>+			&amp;apg_shift,</div><div class='add'>+			&amp;apg_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;apg31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct stream_encoder *dcn35_stream_encoder_create(</div><div class='add'>+	enum engine_id eng_id,</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1;</div><div class='add'>+	struct vpg *vpg;</div><div class='add'>+	struct afmt *afmt;</div><div class='add'>+	int vpg_inst;</div><div class='add'>+	int afmt_inst;</div><div class='add'>+</div><div class='add'>+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */</div><div class='add'>+	if (eng_id &lt;= ENGINE_ID_DIGF) {</div><div class='add'>+		vpg_inst = eng_id;</div><div class='add'>+		afmt_inst = eng_id;</div><div class='add'>+	} else</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);</div><div class='add'>+	vpg = dcn31_vpg_create(ctx, vpg_inst);</div><div class='add'>+	afmt = dcn31_afmt_create(ctx, afmt_inst);</div><div class='add'>+</div><div class='add'>+	if (!enc1 || !vpg || !afmt) {</div><div class='add'>+		kfree(enc1);</div><div class='add'>+		kfree(vpg);</div><div class='add'>+		kfree(afmt);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT stream_enc_regs</div><div class='add'>+	stream_enc_regs_init(0),</div><div class='add'>+	stream_enc_regs_init(1),</div><div class='add'>+	stream_enc_regs_init(2),</div><div class='add'>+	stream_enc_regs_init(3),</div><div class='add'>+	stream_enc_regs_init(4);</div><div class='add'>+</div><div class='add'>+	dcn35_dio_stream_encoder_construct(enc1, ctx, ctx-&gt;dc_bios,</div><div class='add'>+					eng_id, vpg, afmt,</div><div class='add'>+					&amp;stream_enc_regs[eng_id],</div><div class='add'>+					&amp;se_shift, &amp;se_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;enc1-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(</div><div class='add'>+	enum engine_id eng_id,</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;</div><div class='add'>+	struct vpg *vpg;</div><div class='add'>+	struct apg *apg;</div><div class='add'>+	uint32_t hpo_dp_inst;</div><div class='add'>+	uint32_t vpg_inst;</div><div class='add'>+	uint32_t apg_inst;</div><div class='add'>+</div><div class='add'>+	ASSERT((eng_id &gt;= ENGINE_ID_HPO_DP_0) &amp;&amp; (eng_id &lt;= ENGINE_ID_HPO_DP_3));</div><div class='add'>+	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;</div><div class='add'>+</div><div class='add'>+	/* Mapping of VPG register blocks to HPO DP block instance:</div><div class='add'>+	 * VPG[6] -&gt; HPO_DP[0]</div><div class='add'>+	 * VPG[7] -&gt; HPO_DP[1]</div><div class='add'>+	 * VPG[8] -&gt; HPO_DP[2]</div><div class='add'>+	 * VPG[9] -&gt; HPO_DP[3]</div><div class='add'>+	 */</div><div class='add'>+	vpg_inst = hpo_dp_inst + 6;</div><div class='add'>+</div><div class='add'>+	/* Mapping of APG register blocks to HPO DP block instance:</div><div class='add'>+	 * APG[0] -&gt; HPO_DP[0]</div><div class='add'>+	 * APG[1] -&gt; HPO_DP[1]</div><div class='add'>+	 * APG[2] -&gt; HPO_DP[2]</div><div class='add'>+	 * APG[3] -&gt; HPO_DP[3]</div><div class='add'>+	 */</div><div class='add'>+	apg_inst = hpo_dp_inst;</div><div class='add'>+</div><div class='add'>+	/* allocate HPO stream encoder and create VPG sub-block */</div><div class='add'>+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);</div><div class='add'>+	vpg = dcn31_vpg_create(ctx, vpg_inst);</div><div class='add'>+	apg = dcn31_apg_create(ctx, apg_inst);</div><div class='add'>+</div><div class='add'>+	if (!hpo_dp_enc31 || !vpg || !apg) {</div><div class='add'>+		kfree(hpo_dp_enc31);</div><div class='add'>+		kfree(vpg);</div><div class='add'>+		kfree(apg);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hpo_dp_stream_enc_regs</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(0),</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(1),</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(2),</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(3);</div><div class='add'>+</div><div class='add'>+	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx-&gt;dc_bios,</div><div class='add'>+					hpo_dp_inst, eng_id, vpg, apg,</div><div class='add'>+					&amp;hpo_dp_stream_enc_regs[hpo_dp_inst],</div><div class='add'>+					&amp;hpo_dp_se_shift, &amp;hpo_dp_se_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;hpo_dp_enc31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(</div><div class='add'>+	uint8_t inst,</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;</div><div class='add'>+</div><div class='add'>+	/* allocate HPO link encoder */</div><div class='add'>+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hpo_dp_link_enc_regs</div><div class='add'>+	hpo_dp_link_encoder_reg_init(0),</div><div class='add'>+	hpo_dp_link_encoder_reg_init(1);</div><div class='add'>+</div><div class='add'>+	hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,</div><div class='add'>+					&amp;hpo_dp_link_enc_regs[inst],</div><div class='add'>+					&amp;hpo_dp_le_shift, &amp;hpo_dp_le_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;hpo_dp_enc31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dce_hwseq *dcn36_hwseq_create(</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hwseq_reg</div><div class='add'>+	hwseq_reg_init();</div><div class='add'>+</div><div class='add'>+	if (hws) {</div><div class='add'>+		hws-&gt;ctx = ctx;</div><div class='add'>+		hws-&gt;regs = &amp;hwseq_reg;</div><div class='add'>+		hws-&gt;shifts = &amp;hwseq_shift;</div><div class='add'>+		hws-&gt;masks = &amp;hwseq_mask;</div><div class='add'>+	}</div><div class='add'>+	return hws;</div><div class='add'>+}</div><div class='add'>+static const struct resource_create_funcs res_create_funcs = {</div><div class='add'>+	.read_dce_straps = read_dce_straps,</div><div class='add'>+	.create_audio = dcn31_create_audio,</div><div class='add'>+	.create_stream_encoder = dcn35_stream_encoder_create,</div><div class='add'>+	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,</div><div class='add'>+	.create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,</div><div class='add'>+	.create_hwseq = dcn36_hwseq_create,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.stream_enc_count; i++) {</div><div class='add'>+		if (pool-&gt;base.stream_enc[i] != NULL) {</div><div class='add'>+			if (pool-&gt;base.stream_enc[i]-&gt;vpg != NULL) {</div><div class='add'>+				kfree(DCN30_VPG_FROM_VPG(pool-&gt;base.stream_enc[i]-&gt;vpg));</div><div class='add'>+				pool-&gt;base.stream_enc[i]-&gt;vpg = NULL;</div><div class='add'>+			}</div><div class='add'>+			if (pool-&gt;base.stream_enc[i]-&gt;afmt != NULL) {</div><div class='add'>+				kfree(DCN30_AFMT_FROM_AFMT(pool-&gt;base.stream_enc[i]-&gt;afmt));</div><div class='add'>+				pool-&gt;base.stream_enc[i]-&gt;afmt = NULL;</div><div class='add'>+			}</div><div class='add'>+			kfree(DCN10STRENC_FROM_STRENC(pool-&gt;base.stream_enc[i]));</div><div class='add'>+			pool-&gt;base.stream_enc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.hpo_dp_stream_enc_count; i++) {</div><div class='add'>+		if (pool-&gt;base.hpo_dp_stream_enc[i] != NULL) {</div><div class='add'>+			if (pool-&gt;base.hpo_dp_stream_enc[i]-&gt;vpg != NULL) {</div><div class='add'>+				kfree(DCN30_VPG_FROM_VPG(pool-&gt;base.hpo_dp_stream_enc[i]-&gt;vpg));</div><div class='add'>+				pool-&gt;base.hpo_dp_stream_enc[i]-&gt;vpg = NULL;</div><div class='add'>+			}</div><div class='add'>+			if (pool-&gt;base.hpo_dp_stream_enc[i]-&gt;apg != NULL) {</div><div class='add'>+				kfree(DCN31_APG_FROM_APG(pool-&gt;base.hpo_dp_stream_enc[i]-&gt;apg));</div><div class='add'>+				pool-&gt;base.hpo_dp_stream_enc[i]-&gt;apg = NULL;</div><div class='add'>+			}</div><div class='add'>+			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool-&gt;base.hpo_dp_stream_enc[i]));</div><div class='add'>+			pool-&gt;base.hpo_dp_stream_enc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.hpo_dp_link_enc_count; i++) {</div><div class='add'>+		if (pool-&gt;base.hpo_dp_link_enc[i] != NULL) {</div><div class='add'>+			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool-&gt;base.hpo_dp_link_enc[i]));</div><div class='add'>+			pool-&gt;base.hpo_dp_link_enc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_dsc; i++) {</div><div class='add'>+		if (pool-&gt;base.dscs[i] != NULL)</div><div class='add'>+			dcn20_dsc_destroy(&amp;pool-&gt;base.dscs[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.mpc != NULL) {</div><div class='add'>+		kfree(TO_DCN20_MPC(pool-&gt;base.mpc));</div><div class='add'>+		pool-&gt;base.mpc = NULL;</div><div class='add'>+	}</div><div class='add'>+	if (pool-&gt;base.hubbub != NULL) {</div><div class='add'>+		kfree(pool-&gt;base.hubbub);</div><div class='add'>+		pool-&gt;base.hubbub = NULL;</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.pipe_count; i++) {</div><div class='add'>+		if (pool-&gt;base.dpps[i] != NULL)</div><div class='add'>+			dcn35_dpp_destroy(&amp;pool-&gt;base.dpps[i]);</div><div class='add'>+</div><div class='add'>+		if (pool-&gt;base.ipps[i] != NULL)</div><div class='add'>+			pool-&gt;base.ipps[i]-&gt;funcs-&gt;ipp_destroy(&amp;pool-&gt;base.ipps[i]);</div><div class='add'>+</div><div class='add'>+		if (pool-&gt;base.hubps[i] != NULL) {</div><div class='add'>+			kfree(TO_DCN20_HUBP(pool-&gt;base.hubps[i]));</div><div class='add'>+			pool-&gt;base.hubps[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (pool-&gt;base.irqs != NULL) {</div><div class='add'>+			dal_irq_service_destroy(&amp;pool-&gt;base.irqs);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_ddc; i++) {</div><div class='add'>+		if (pool-&gt;base.engines[i] != NULL)</div><div class='add'>+			dce110_engine_destroy(&amp;pool-&gt;base.engines[i]);</div><div class='add'>+		if (pool-&gt;base.hw_i2cs[i] != NULL) {</div><div class='add'>+			kfree(pool-&gt;base.hw_i2cs[i]);</div><div class='add'>+			pool-&gt;base.hw_i2cs[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+		if (pool-&gt;base.sw_i2cs[i] != NULL) {</div><div class='add'>+			kfree(pool-&gt;base.sw_i2cs[i]);</div><div class='add'>+			pool-&gt;base.sw_i2cs[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_opp; i++) {</div><div class='add'>+		if (pool-&gt;base.opps[i] != NULL)</div><div class='add'>+			pool-&gt;base.opps[i]-&gt;funcs-&gt;opp_destroy(&amp;pool-&gt;base.opps[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+		if (pool-&gt;base.timing_generators[i] != NULL)	{</div><div class='add'>+			kfree(DCN10TG_FROM_TG(pool-&gt;base.timing_generators[i]));</div><div class='add'>+			pool-&gt;base.timing_generators[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_dwb; i++) {</div><div class='add'>+		if (pool-&gt;base.dwbc[i] != NULL) {</div><div class='add'>+			kfree(TO_DCN30_DWBC(pool-&gt;base.dwbc[i]));</div><div class='add'>+			pool-&gt;base.dwbc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+		if (pool-&gt;base.mcif_wb[i] != NULL) {</div><div class='add'>+			kfree(TO_DCN30_MMHUBBUB(pool-&gt;base.mcif_wb[i]));</div><div class='add'>+			pool-&gt;base.mcif_wb[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.audio_count; i++) {</div><div class='add'>+		if (pool-&gt;base.audios[i])</div><div class='add'>+			dce_aud_destroy(&amp;pool-&gt;base.audios[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.clk_src_count; i++) {</div><div class='add'>+		if (pool-&gt;base.clock_sources[i] != NULL) {</div><div class='add'>+			dcn20_clock_source_destroy(&amp;pool-&gt;base.clock_sources[i]);</div><div class='add'>+			pool-&gt;base.clock_sources[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_mpc_3dlut; i++) {</div><div class='add'>+		if (pool-&gt;base.mpc_lut[i] != NULL) {</div><div class='add'>+			dc_3dlut_func_release(pool-&gt;base.mpc_lut[i]);</div><div class='add'>+			pool-&gt;base.mpc_lut[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+		if (pool-&gt;base.mpc_shaper[i] != NULL) {</div><div class='add'>+			dc_transfer_func_release(pool-&gt;base.mpc_shaper[i]);</div><div class='add'>+			pool-&gt;base.mpc_shaper[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.dp_clock_source != NULL) {</div><div class='add'>+		dcn20_clock_source_destroy(&amp;pool-&gt;base.dp_clock_source);</div><div class='add'>+		pool-&gt;base.dp_clock_source = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+		if (pool-&gt;base.multiple_abms[i] != NULL)</div><div class='add'>+			dce_abm_destroy(&amp;pool-&gt;base.multiple_abms[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.psr != NULL)</div><div class='add'>+		dmub_psr_destroy(&amp;pool-&gt;base.psr);</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.replay != NULL)</div><div class='add'>+		dmub_replay_destroy(&amp;pool-&gt;base.replay);</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.pg_cntl != NULL)</div><div class='add'>+		dcn_pg_cntl_destroy(&amp;pool-&gt;base.pg_cntl);</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.dccg != NULL)</div><div class='add'>+		dcn_dccg_destroy(&amp;pool-&gt;base.dccg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hubp *dcn35_hubp_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!hubp2)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hubp_regs</div><div class='add'>+	hubp_regs_init(0),</div><div class='add'>+	hubp_regs_init(1),</div><div class='add'>+	hubp_regs_init(2),</div><div class='add'>+	hubp_regs_init(3);</div><div class='add'>+</div><div class='add'>+	if (hubp35_construct(hubp2, ctx, inst,</div><div class='add'>+			&amp;hubp_regs[inst], &amp;hubp_shift, &amp;hubp_mask))</div><div class='add'>+		return &amp;hubp2-&gt;base;</div><div class='add'>+</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	kfree(hubp2);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	dcn35_dwbc_set_fgcg(</div><div class='add'>+		dwbc30, ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.dwb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t pipe_count = pool-&gt;res_cap-&gt;num_dwb;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pipe_count; i++) {</div><div class='add'>+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),</div><div class='add'>+						    GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+		if (!dwbc30) {</div><div class='add'>+			dm_error("DC: failed to create dwbc30!\n");</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dwbc35_regs</div><div class='add'>+		dwbc_regs_dcn3_init(0);</div><div class='add'>+</div><div class='add'>+		dcn35_dwbc_construct(dwbc30, ctx,</div><div class='add'>+				&amp;dwbc35_regs[i],</div><div class='add'>+				&amp;dwbc35_shift,</div><div class='add'>+				&amp;dwbc35_mask,</div><div class='add'>+				i);</div><div class='add'>+</div><div class='add'>+		pool-&gt;dwbc[i] = &amp;dwbc30-&gt;base;</div><div class='add'>+</div><div class='add'>+		dcn35_dwbc_init(dwbc30, ctx);</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,</div><div class='add'>+				struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	dcn35_mmhubbub_set_fgcg(</div><div class='add'>+		mcif_wb30,</div><div class='add'>+		ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.mmhubbub);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t pipe_count = pool-&gt;res_cap-&gt;num_dwb;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pipe_count; i++) {</div><div class='add'>+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),</div><div class='add'>+						    GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+		if (!mcif_wb30) {</div><div class='add'>+			dm_error("DC: failed to create mcif_wb30!\n");</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT mcif_wb35_regs</div><div class='add'>+		mcif_wb_regs_dcn3_init(0);</div><div class='add'>+</div><div class='add'>+		dcn35_mmhubbub_construct(mcif_wb30, ctx,</div><div class='add'>+				&amp;mcif_wb35_regs[i],</div><div class='add'>+				&amp;mcif_wb35_shift,</div><div class='add'>+				&amp;mcif_wb35_mask,</div><div class='add'>+				i);</div><div class='add'>+</div><div class='add'>+		dcn35_mmhubbub_init(mcif_wb30, ctx);</div><div class='add'>+</div><div class='add'>+		pool-&gt;mcif_wb[i] = &amp;mcif_wb30-&gt;base;</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct display_stream_compressor *dcn35_dsc_create(</div><div class='add'>+	struct dc_context *ctx, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_dsc *dsc =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!dsc) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dsc_regs</div><div class='add'>+	dsc_regsDCN35_init(0),</div><div class='add'>+	dsc_regsDCN35_init(1),</div><div class='add'>+	dsc_regsDCN35_init(2),</div><div class='add'>+	dsc_regsDCN35_init(3);</div><div class='add'>+</div><div class='add'>+	dsc35_construct(dsc, ctx, inst, &amp;dsc_regs[inst], &amp;dsc_shift, &amp;dsc_mask);</div><div class='add'>+	dsc35_set_fgcg(dsc,</div><div class='add'>+		       ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.dsc);</div><div class='add'>+	return &amp;dsc-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn36_destroy_resource_pool(struct resource_pool **pool)</div><div class='add'>+{</div><div class='add'>+	struct dcn36_resource_pool *dcn36_pool = TO_DCN36_RES_POOL(*pool);</div><div class='add'>+</div><div class='add'>+	dcn36_resource_destruct(dcn36_pool);</div><div class='add'>+	kfree(dcn36_pool);</div><div class='add'>+	*pool = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct clock_source *dcn35_clock_source_create(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		struct dc_bios *bios,</div><div class='add'>+		enum clock_source_id id,</div><div class='add'>+		const struct dce110_clk_src_regs *regs,</div><div class='add'>+		bool dp_clk_src)</div><div class='add'>+{</div><div class='add'>+	struct dce110_clk_src *clk_src =</div><div class='add'>+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!clk_src)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (dcn31_clk_src_construct(clk_src, ctx, bios, id,</div><div class='add'>+			regs, &amp;cs_shift, &amp;cs_mask)) {</div><div class='add'>+		clk_src-&gt;base.dp_clk_src = dp_clk_src;</div><div class='add'>+		return &amp;clk_src-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kfree(clk_src);</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dc_cap_funcs cap_funcs = {</div><div class='add'>+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)</div><div class='add'>+{</div><div class='add'>+	*panel_config = panel_config_defaults;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static enum dc_status dcn35_validate_bandwidth(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	bool out = false;</div><div class='add'>+</div><div class='add'>+	out = dml2_validate(dc, context,</div><div class='add'>+			context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+			validate_mode);</div><div class='add'>+</div><div class='add'>+	if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)</div><div class='add'>+		return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	dcn35_decide_zstate_support(dc, context);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+</div><div class='add'>+	return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='add'>+					       struct dc_state *context,</div><div class='add'>+					       display_e2e_pipe_params_st *pipes,</div><div class='add'>+					       enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct resource_funcs dcn36_res_pool_funcs = {</div><div class='add'>+	.destroy = dcn36_destroy_resource_pool,</div><div class='add'>+	.link_enc_create = dcn35_link_encoder_create,</div><div class='add'>+	.link_enc_create_minimal = dcn31_link_enc_create_minimal,</div><div class='add'>+	.link_encs_assign = link_enc_cfg_link_encs_assign,</div><div class='add'>+	.link_enc_unassign = link_enc_cfg_link_enc_unassign,</div><div class='add'>+	.panel_cntl_create = dcn31_panel_cntl_create,</div><div class='add'>+	.validate_bandwidth = dcn35_validate_bandwidth,</div><div class='add'>+	.calculate_wm_and_dlg = NULL,</div><div class='add'>+	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,</div><div class='add'>+	.populate_dml_pipes = populate_dml_pipes_from_context_fpu,</div><div class='add'>+	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,</div><div class='add'>+	.release_pipe = dcn20_release_pipe,</div><div class='add'>+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,</div><div class='add'>+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,</div><div class='add'>+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,</div><div class='add'>+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,</div><div class='add'>+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,</div><div class='add'>+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,</div><div class='add'>+	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,</div><div class='add'>+	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,</div><div class='add'>+	.update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,</div><div class='add'>+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='add'>+	.get_panel_config_defaults = dcn35_get_panel_config_defaults,</div><div class='add'>+	.get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia,</div><div class='add'>+	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,</div><div class='add'>+	.update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool dcn36_resource_construct(</div><div class='add'>+	uint8_t num_virtual_links,</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dcn36_resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct dc_context *ctx = dc-&gt;ctx;</div><div class='add'>+	struct irq_service_init_data init_data;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT bios_regs</div><div class='add'>+	bios_regs_init();</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT clk_src_regs</div><div class='add'>+	clk_src_regs_init(0, A),</div><div class='add'>+	clk_src_regs_init(1, B),</div><div class='add'>+	clk_src_regs_init(2, C),</div><div class='add'>+	clk_src_regs_init(3, D),</div><div class='add'>+	clk_src_regs_init(4, E);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT abm_regs</div><div class='add'>+	abm_regs_init(0),</div><div class='add'>+	abm_regs_init(1),</div><div class='add'>+	abm_regs_init(2),</div><div class='add'>+	abm_regs_init(3);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dccg_regs</div><div class='add'>+	dccg_regs_init();</div><div class='add'>+</div><div class='add'>+	ctx-&gt;dc_bios-&gt;regs = &amp;bios_regs;</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.res_cap = &amp;res_cap_dcn36;</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.funcs = &amp;dcn36_res_pool_funcs;</div><div class='add'>+</div><div class='add'>+	/*************************************************</div><div class='add'>+	 *  Resource + asic cap harcoding                *</div><div class='add'>+	 *************************************************/</div><div class='add'>+	pool-&gt;base.underlay_pipe_index = NO_UNDERLAY_PIPE;</div><div class='add'>+	pool-&gt;base.pipe_count = pool-&gt;base.res_cap-&gt;num_timing_generator;</div><div class='add'>+	pool-&gt;base.mpcc_count = pool-&gt;base.res_cap-&gt;num_timing_generator;</div><div class='add'>+	dc-&gt;caps.max_downscale_ratio = 600;</div><div class='add'>+	dc-&gt;caps.i2c_speed_in_khz = 100;</div><div class='add'>+	dc-&gt;caps.i2c_speed_in_khz_hdcp = 100;</div><div class='add'>+	dc-&gt;caps.max_cursor_size = 256;</div><div class='add'>+	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='add'>+	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='add'>+	dc-&gt;caps.max_slave_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_yuv_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_rgb_planes = 3;</div><div class='add'>+	dc-&gt;caps.post_blend_color_processing = true;</div><div class='add'>+	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='add'>+	if (dc-&gt;config.forceHBR2CP2520)</div><div class='add'>+		dc-&gt;caps.force_dp_tps4_for_cp2520 = false;</div><div class='add'>+	dc-&gt;caps.dp_hpo = true;</div><div class='add'>+	dc-&gt;caps.dp_hdmi21_pcon_support = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.edp_dsc_support = true;</div><div class='add'>+	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='add'>+	dc-&gt;caps.dmcub_support = true;</div><div class='add'>+	dc-&gt;caps.is_apu = true;</div><div class='add'>+	dc-&gt;caps.seamless_odm = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.zstate_support = true;</div><div class='add'>+	dc-&gt;caps.ips_support = true;</div><div class='add'>+	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='add'>+</div><div class='add'>+	/* Color pipeline capabilities */</div><div class='add'>+	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.input_lut_shared = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.icsc = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_ram = 0; // must use gamma_corr</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.srgb = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.bt2020 = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.pq = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.hlg = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.post_csc = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.gamma_corr = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_for_yuv = 0;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.color.dpp.hw_3d_lut = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1</div><div class='add'>+	// no OGAM ROM on DCN301</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.srgb = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.bt2020 = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.pq = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.hlg = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ocsc = 0;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.color.mpc.gamut_remap = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.num_3dluts = pool-&gt;base.res_cap-&gt;num_mpc_3dlut; //2</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_ram = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.srgb = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.bt2020 = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.preblend = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.num_of_host_routers = 2;</div><div class='add'>+	dc-&gt;caps.num_of_dpias_per_host_router = 2;</div><div class='add'>+</div><div class='add'>+	/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order</div><div class='add'>+	 * to provide some margin.</div><div class='add'>+	 * It's expected for furture ASIC to have equal or higher value, in order to</div><div class='add'>+	 * have determinstic power improvement from generate to genration.</div><div class='add'>+	 * (i.e., we should not expect new ASIC generation with lower vmin rate)</div><div class='add'>+	 */</div><div class='add'>+	dc-&gt;caps.max_disp_clock_khz_at_vmin = 650000;</div><div class='add'>+</div><div class='add'>+	/* Sequential ONO is based on ASIC. */</div><div class='add'>+	if (dc-&gt;ctx-&gt;asic_id.hw_internal_rev &gt;= 0x40)</div><div class='add'>+		dc-&gt;caps.sequential_ono = true;</div><div class='add'>+</div><div class='add'>+	/* Use pipe context based otg sync logic */</div><div class='add'>+	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;config.disable_hbr_audio_dp2 = true;</div><div class='add'>+	/* read VBIOS LTTPR caps */</div><div class='add'>+	{</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='add'>+			enum bp_result bp_query_result;</div><div class='add'>+			uint8_t is_vbios_lttpr_enable = 0;</div><div class='add'>+</div><div class='add'>+			bp_query_result = ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps(ctx-&gt;dc_bios, &amp;is_vbios_lttpr_enable);</div><div class='add'>+			dc-&gt;caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) &amp;&amp; !!is_vbios_lttpr_enable;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* interop bit is implicit */</div><div class='add'>+		{</div><div class='add'>+			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='add'>+		dc-&gt;debug = debug_defaults_drv;</div><div class='add'>+</div><div class='add'>+	/*HW default is to have all the FGCG enabled, SW no need to program them*/</div><div class='add'>+	dc-&gt;debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;</div><div class='add'>+	// Init the vm_helper</div><div class='add'>+	if (dc-&gt;vm_helper)</div><div class='add'>+		vm_helper_init(dc-&gt;vm_helper, 16);</div><div class='add'>+</div><div class='add'>+	/*************************************************</div><div class='add'>+	 *  Create resources                             *</div><div class='add'>+	 *************************************************/</div><div class='add'>+</div><div class='add'>+	/* Clock Sources for Pixel Clock*/</div><div class='add'>+	pool-&gt;base.clock_sources[DCN36_CLK_SRC_PLL0] =</div><div class='add'>+			dcn35_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL0,</div><div class='add'>+				&amp;clk_src_regs[0], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN36_CLK_SRC_PLL1] =</div><div class='add'>+			dcn35_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL1,</div><div class='add'>+				&amp;clk_src_regs[1], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN36_CLK_SRC_PLL2] =</div><div class='add'>+			dcn35_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL2,</div><div class='add'>+				&amp;clk_src_regs[2], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN36_CLK_SRC_PLL3] =</div><div class='add'>+			dcn35_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL3,</div><div class='add'>+				&amp;clk_src_regs[3], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN36_CLK_SRC_PLL4] =</div><div class='add'>+			dcn35_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL4,</div><div class='add'>+				&amp;clk_src_regs[4], false);</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.clk_src_count = DCN36_CLK_SRC_TOTAL;</div><div class='add'>+</div><div class='add'>+	/* todo: not reuse phy_pll registers */</div><div class='add'>+	pool-&gt;base.dp_clock_source =</div><div class='add'>+			dcn35_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_ID_DP_DTO,</div><div class='add'>+				&amp;clk_src_regs[0], true);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.clk_src_count; i++) {</div><div class='add'>+		if (pool-&gt;base.clock_sources[i] == NULL) {</div><div class='add'>+			dm_error("DC: failed to create clock sources!\n");</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	/*temp till dml2 fully work without dml1*/</div><div class='add'>+	dml_init_instance(&amp;dc-&gt;dml, &amp;dcn3_5_soc, &amp;dcn3_5_ip, DML_PROJECT_DCN31);</div><div class='add'>+</div><div class='add'>+	/* TODO: DCCG */</div><div class='add'>+	pool-&gt;base.dccg = dccg35_create(ctx, &amp;dccg_regs, &amp;dccg_shift, &amp;dccg_mask);</div><div class='add'>+	if (pool-&gt;base.dccg == NULL) {</div><div class='add'>+		dm_error("DC: failed to create dccg!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT pg_cntl_regs</div><div class='add'>+	pg_cntl_dcn35_regs_init();</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.pg_cntl = pg_cntl35_create(ctx, &amp;pg_cntl_regs, &amp;pg_cntl_shift, &amp;pg_cntl_mask);</div><div class='add'>+	if (pool-&gt;base.pg_cntl == NULL) {</div><div class='add'>+		dm_error("DC: failed to create power gate control!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* TODO: IRQ */</div><div class='add'>+	init_data.ctx = dc-&gt;ctx;</div><div class='add'>+	pool-&gt;base.irqs = dal_irq_service_dcn36_create(&amp;init_data);</div><div class='add'>+	if (!pool-&gt;base.irqs)</div><div class='add'>+		goto create_fail;</div><div class='add'>+</div><div class='add'>+	/* HUBBUB */</div><div class='add'>+	pool-&gt;base.hubbub = dcn35_hubbub_create(ctx);</div><div class='add'>+	if (pool-&gt;base.hubbub == NULL) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create hubbub!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* HUBPs, DPPs, OPPs and TGs */</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.pipe_count; i++) {</div><div class='add'>+		pool-&gt;base.hubps[i] = dcn35_hubp_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.hubps[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC: failed to create hubps!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pool-&gt;base.dpps[i] = dcn35_dpp_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.dpps[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC: failed to create dpps!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_opp; i++) {</div><div class='add'>+		pool-&gt;base.opps[i] = dcn35_opp_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.opps[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC: failed to create output pixel processor!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+		pool-&gt;base.timing_generators[i] = dcn35_timing_generator_create(</div><div class='add'>+				ctx, i);</div><div class='add'>+		if (pool-&gt;base.timing_generators[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error("DC: failed to create tg!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	pool-&gt;base.timing_generator_count = i;</div><div class='add'>+</div><div class='add'>+	/* PSR */</div><div class='add'>+	pool-&gt;base.psr = dmub_psr_create(ctx);</div><div class='add'>+	if (pool-&gt;base.psr == NULL) {</div><div class='add'>+		dm_error("DC: failed to create psr obj!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Replay */</div><div class='add'>+	pool-&gt;base.replay = dmub_replay_create(ctx);</div><div class='add'>+	if (pool-&gt;base.replay == NULL) {</div><div class='add'>+		dm_error("DC: failed to create replay obj!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* ABM */</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+		pool-&gt;base.multiple_abms[i] = dmub_abm_create(ctx,</div><div class='add'>+				&amp;abm_regs[i],</div><div class='add'>+				&amp;abm_shift,</div><div class='add'>+				&amp;abm_mask);</div><div class='add'>+		if (pool-&gt;base.multiple_abms[i] == NULL) {</div><div class='add'>+			dm_error("DC: failed to create abm for pipe %d!\n", i);</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* MPC and DSC */</div><div class='add'>+	pool-&gt;base.mpc = dcn35_mpc_create(ctx, pool-&gt;base.mpcc_count, pool-&gt;base.res_cap-&gt;num_mpc_3dlut);</div><div class='add'>+	if (pool-&gt;base.mpc == NULL) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create mpc!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_dsc; i++) {</div><div class='add'>+		pool-&gt;base.dscs[i] = dcn35_dsc_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.dscs[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error("DC: failed to create display stream compressor %d!\n", i);</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DWB and MMHUBBUB */</div><div class='add'>+	if (!dcn35_dwbc_create(ctx, &amp;pool-&gt;base)) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create dwbc!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!dcn35_mmhubbub_create(ctx, &amp;pool-&gt;base)) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create mcif_wb!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* AUX and I2C */</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_ddc; i++) {</div><div class='add'>+		pool-&gt;base.engines[i] = dcn31_aux_engine_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.engines[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC:failed to create aux engine!!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+		pool-&gt;base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.hw_i2cs[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC:failed to create hw i2c!!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+		pool-&gt;base.sw_i2cs[i] = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DCN3.5 has 6 DPIA */</div><div class='add'>+	pool-&gt;base.usb4_dpia_count = 4;</div><div class='add'>+	if (dc-&gt;debug.dpia_debug.bits.disable_dpia)</div><div class='add'>+		pool-&gt;base.usb4_dpia_count = 0;</div><div class='add'>+</div><div class='add'>+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */</div><div class='add'>+	if (!resource_construct(num_virtual_links, dc, &amp;pool-&gt;base,</div><div class='add'>+			&amp;res_create_funcs))</div><div class='add'>+		goto create_fail;</div><div class='add'>+</div><div class='add'>+	/* HW Sequencer and Plane caps */</div><div class='add'>+	dcn35_hw_sequencer_construct(dc);</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.max_planes =  pool-&gt;base.pipe_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='add'>+		dc-&gt;caps.planes[i] = plane_cap;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='add'>+	dc-&gt;cap_funcs = cap_funcs;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dcn_ip-&gt;max_num_dpp = pool-&gt;base.pipe_count;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.dcn_pipe_count = pool-&gt;base.pipe_count;</div><div class='add'>+	dc-&gt;dml2_options.use_native_soc_bb_construction = true;</div><div class='add'>+	dc-&gt;dml2_options.minimize_dispclk_using_odm = false;</div><div class='add'>+	if (dc-&gt;config.EnableMinDispClkODM)</div><div class='add'>+		dc-&gt;dml2_options.minimize_dispclk_using_odm = true;</div><div class='add'>+	dc-&gt;dml2_options.enable_windowed_mpo_odm = dc-&gt;config.enable_windowed_mpo_odm;</div><div class='add'>+</div><div class='add'>+	resource_init_common_dml2_callbacks(dc, &amp;dc-&gt;dml2_options);</div><div class='add'>+	dc-&gt;dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &amp;dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.max_segments_per_hubp = 24;</div><div class='add'>+	dc-&gt;dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/</div><div class='add'>+	dc-&gt;dml2_options.override_det_buffer_size_kbytes = true;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;config.sdpif_request_limit_words_per_umc == 0)</div><div class='add'>+		dc-&gt;config.sdpif_request_limit_words_per_umc = 16;/*todo*/</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+</div><div class='add'>+create_fail:</div><div class='add'>+</div><div class='add'>+	dcn36_resource_destruct(pool);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct resource_pool *dcn36_create_resource_pool(</div><div class='add'>+		const struct dc_init_data *init_data,</div><div class='add'>+		struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dcn36_resource_pool *pool =</div><div class='add'>+		kzalloc(sizeof(struct dcn36_resource_pool), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!pool)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (dcn36_resource_construct(init_data-&gt;num_virtual_links, dc, pool))</div><div class='add'>+		return &amp;pool-&gt;base;</div><div class='add'>+</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	kfree(pool);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h<br/>new file mode 100644<br/>index 000000000000..5490c9975e23<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.h</a></div><div class='hunk'>@@ -0,0 +1,73 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef _DCN36_RESOURCE_H_</div><div class='add'>+#define _DCN36_RESOURCE_H_</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+</div><div class='add'>+extern struct _vcs_dpi_ip_params_st dcn3_6_ip;</div><div class='add'>+extern struct _vcs_dpi_soc_bounding_box_st dcn3_6_soc;</div><div class='add'>+</div><div class='add'>+#define TO_DCN36_RES_POOL(pool)\</div><div class='add'>+	container_of(pool, struct dcn36_resource_pool, base)</div><div class='add'>+</div><div class='add'>+struct dcn36_resource_pool {</div><div class='add'>+	struct resource_pool base;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct resource_pool *dcn36_create_resource_pool(</div><div class='add'>+		const struct dc_init_data *init_data,</div><div class='add'>+		struct dc *dc);</div><div class='add'>+</div><div class='add'>+#define HWSEQ_DCN36_REG_LIST()\</div><div class='add'>+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \</div><div class='add'>+	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \</div><div class='add'>+	SR(DIO_MEM_PWR_CTRL), \</div><div class='add'>+	SR(ODM_MEM_PWR_CTRL3), \</div><div class='add'>+	SR(MMHUBBUB_MEM_PWR_CNTL), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL2), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL4), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL5), \</div><div class='add'>+	SR(DCFCLK_CNTL),\</div><div class='add'>+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 0), \</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 1),\</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 2),\</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 3),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\</div><div class='add'>+	SR(MICROSECOND_TIME_BASE_DIV), \</div><div class='add'>+	SR(MILLISECOND_TIME_BASE_DIV), \</div><div class='add'>+	SR(DISPCLK_FREQ_CHANGE_CNTL), \</div><div class='add'>+	SR(RBBMIF_TIMEOUT_DIS), \</div><div class='add'>+	SR(RBBMIF_TIMEOUT_DIS_2), \</div><div class='add'>+	SR(DCHUBBUB_CRC_CTRL), \</div><div class='add'>+	SR(DPP_TOP0_DPP_CRC_CTRL), \</div><div class='add'>+	SR(MPC_CRC_CTRL), \</div><div class='add'>+	SR(DOMAIN0_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN1_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN2_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN3_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN16_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN17_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN18_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN19_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN0_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN1_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN2_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN3_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN16_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN17_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN18_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN19_PG_STATUS), \</div><div class='add'>+	SR(DC_IP_REQUEST_CNTL), \</div><div class='add'>+	SR(AZALIA_AUDIO_DTO), \</div><div class='add'>+	SR(AZALIA_CONTROLLER_CLOCK_GATING), \</div><div class='add'>+	SR(HPO_TOP_HW_CONTROL),\</div><div class='add'>+	SR(DMU_CLK_CNTL)</div><div class='add'>+</div><div class='add'>+#endif /* _DCN36_RESOURCE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c<br/>new file mode 100644<br/>index 000000000000..875ae97489d3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c</a></div><div class='hunk'>@@ -0,0 +1,2282 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+</div><div class='add'>+#include "dcn32/dcn32_init.h"</div><div class='add'>+#include "dcn401/dcn401_init.h"</div><div class='add'>+</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "include/irq_service_interface.h"</div><div class='add'>+#include "dcn401_resource.h"</div><div class='add'>+</div><div class='add'>+#include "dcn20/dcn20_resource.h"</div><div class='add'>+#include "dcn30/dcn30_resource.h"</div><div class='add'>+#include "dcn32/dcn32_resource.h"</div><div class='add'>+#include "dcn321/dcn321_resource.h"</div><div class='add'>+</div><div class='add'>+#include "dcn10/dcn10_ipp.h"</div><div class='add'>+#include "dcn401/dcn401_hubbub.h"</div><div class='add'>+#include "dcn401/dcn401_mpc.h"</div><div class='add'>+#include "dcn401/dcn401_hubp.h"</div><div class='add'>+#include "irq/dcn401/irq_service_dcn401.h"</div><div class='add'>+#include "dcn401/dcn401_dpp.h"</div><div class='add'>+#include "dcn401/dcn401_optc.h"</div><div class='add'>+#include "dcn20/dcn20_hwseq.h"</div><div class='add'>+#include "dcn30/dcn30_hwseq.h"</div><div class='add'>+#include "dce110/dce110_hwseq.h"</div><div class='add'>+#include "dcn20/dcn20_opp.h"</div><div class='add'>+#include "dcn401/dcn401_dsc.h"</div><div class='add'>+#include "dcn30/dcn30_vpg.h"</div><div class='add'>+#include "dcn31/dcn31_vpg.h"</div><div class='add'>+#include "dcn30/dcn30_afmt.h"</div><div class='add'>+#include "dcn30/dcn30_dio_stream_encoder.h"</div><div class='add'>+#include "dcn401/dcn401_dio_stream_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_hpo_dp_stream_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_hpo_dp_link_encoder.h"</div><div class='add'>+#include "dcn32/dcn32_hpo_dp_link_encoder.h"</div><div class='add'>+#include "dcn31/dcn31_apg.h"</div><div class='add'>+#include "dcn31/dcn31_dio_link_encoder.h"</div><div class='add'>+#include "dcn401/dcn401_dio_link_encoder.h"</div><div class='add'>+#include "dcn10/dcn10_link_encoder.h"</div><div class='add'>+#include "dcn321/dcn321_dio_link_encoder.h"</div><div class='add'>+#include "dce/dce_clock_source.h"</div><div class='add'>+#include "dce/dce_audio.h"</div><div class='add'>+#include "dce/dce_hwseq.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='add'>+#include "virtual/virtual_stream_encoder.h"</div><div class='add'>+#include "dml/display_mode_vba.h"</div><div class='add'>+#include "dcn401/dcn401_dccg.h"</div><div class='add'>+#include "dcn10/dcn10_resource.h"</div><div class='add'>+#include "link_service.h"</div><div class='add'>+#include "link_enc_cfg.h"</div><div class='add'>+#include "dcn31/dcn31_panel_cntl.h"</div><div class='add'>+</div><div class='add'>+#include "dcn30/dcn30_dwb.h"</div><div class='add'>+#include "dcn32/dcn32_mmhubbub.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_4_1_0_offset.h"</div><div class='add'>+#include "dcn/dcn_4_1_0_sh_mask.h"</div><div class='add'>+#include "nbif/nbif_6_3_1_offset.h"</div><div class='add'>+</div><div class='add'>+#include "reg_helper.h"</div><div class='add'>+#include "dce/dmub_abm.h"</div><div class='add'>+#include "dce/dmub_psr.h"</div><div class='add'>+#include "dce/dce_aux.h"</div><div class='add'>+#include "dce/dce_i2c.h"</div><div class='add'>+</div><div class='add'>+#include "dml/dcn30/display_mode_vba_30.h"</div><div class='add'>+#include "vm_helper.h"</div><div class='add'>+#include "dcn20/dcn20_vmid.h"</div><div class='add'>+</div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+</div><div class='add'>+#include "dml2_0/dml2_wrapper.h"</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER_INIT(logger)</div><div class='add'>+</div><div class='add'>+enum dcn401_clk_src_array_id {</div><div class='add'>+	DCN401_CLK_SRC_PLL0,</div><div class='add'>+	DCN401_CLK_SRC_PLL1,</div><div class='add'>+	DCN401_CLK_SRC_PLL2,</div><div class='add'>+	DCN401_CLK_SRC_PLL3,</div><div class='add'>+	//DCN401_CLK_SRC_PLL4,</div><div class='add'>+	DCN401_CLK_SRC_TOTAL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* begin *********************</div><div class='add'>+ * macros to expend register list macro defined in HW object header file</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* DCN */</div><div class='add'>+#define BASE_INNER(seg) ctx-&gt;dcn_reg_offsets[seg]</div><div class='add'>+</div><div class='add'>+#define BASE(seg) BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define SR(reg_name)\</div><div class='add'>+	REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \</div><div class='add'>+		reg ## reg_name</div><div class='add'>+#define SR_ARR(reg_name, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \</div><div class='add'>+		reg ## reg_name</div><div class='add'>+#define SR_ARR_INIT(reg_name, id, value)\</div><div class='add'>+	REG_STRUCT[id].reg_name =  value</div><div class='add'>+</div><div class='add'>+#define SRI(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_ARR(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Used when a reg_name would otherwise begin with an integer</div><div class='add'>+ */</div><div class='add'>+#define SRI_ARR_US(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## reg_name</div><div class='add'>+#define SR_ARR_I2C(reg_name, id) \</div><div class='add'>+	REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_ARR_I2C(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI_ARR_ALPHABET(reg_name, block, index, id)\</div><div class='add'>+	REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRI2(reg_name, block, id)\</div><div class='add'>+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## reg_name</div><div class='add'>+#define SRI2_ARR(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRIR(var_name, reg_name, block, id)\</div><div class='add'>+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII_ARR_2(reg_name, block, id, inst)\</div><div class='add'>+	REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII_MPC_RMU(reg_name, block, id)\</div><div class='add'>+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SRII_DWB(reg_name, temp_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## temp_name</div><div class='add'>+</div><div class='add'>+#define DCCG_SRII(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		reg ## block ## id ## _ ## reg_name</div><div class='add'>+</div><div class='add'>+#define SF_DWB2(reg_name, block, id, field_name, post_fix) \</div><div class='add'>+	.field_name = reg_name ## __ ## field_name ## post_fix</div><div class='add'>+</div><div class='add'>+#define VUPDATE_SRII(reg_name, block, id)\</div><div class='add'>+	REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \</div><div class='add'>+		reg ## reg_name ## _ ## block ## id</div><div class='add'>+</div><div class='add'>+/* NBIO */</div><div class='add'>+#define NBIO_BASE_INNER(seg) ctx-&gt;nbio_reg_offsets[seg]</div><div class='add'>+</div><div class='add'>+#define NBIO_BASE(seg) \</div><div class='add'>+	NBIO_BASE_INNER(seg)</div><div class='add'>+</div><div class='add'>+#define NBIO_SR(reg_name)\</div><div class='add'>+	REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		regBIF_BX0_ ## reg_name</div><div class='add'>+#define NBIO_SR_ARR(reg_name, id)\</div><div class='add'>+	REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \</div><div class='add'>+		regBIF_BX0_ ## reg_name</div><div class='add'>+</div><div class='add'>+#define CTX ctx</div><div class='add'>+#define REG(reg_name) \</div><div class='add'>+	(ctx-&gt;dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)</div><div class='add'>+</div><div class='add'>+static struct bios_registers bios_regs;</div><div class='add'>+</div><div class='add'>+#define bios_regs_init() \</div><div class='add'>+		NBIO_SR(BIOS_SCRATCH_3),\</div><div class='add'>+		NBIO_SR(BIOS_SCRATCH_6)</div><div class='add'>+</div><div class='add'>+#define clk_src_regs_init(index, pllid)\</div><div class='add'>+	CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)</div><div class='add'>+</div><div class='add'>+static struct dce110_clk_src_regs clk_src_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dce110_clk_src_shift cs_shift = {</div><div class='add'>+		CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce110_clk_src_mask cs_mask = {</div><div class='add'>+		CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define abm_regs_init(id)\</div><div class='add'>+		ABM_DCN401_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dce_abm_registers abm_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dce_abm_shift abm_shift = {</div><div class='add'>+		ABM_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_abm_mask abm_mask = {</div><div class='add'>+		ABM_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define audio_regs_init(id)\</div><div class='add'>+		AUD_COMMON_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dce_audio_registers audio_regs[5];</div><div class='add'>+</div><div class='add'>+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\</div><div class='add'>+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\</div><div class='add'>+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\</div><div class='add'>+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)</div><div class='add'>+</div><div class='add'>+static const struct dce_audio_shift audio_shift = {</div><div class='add'>+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_audio_mask audio_mask = {</div><div class='add'>+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define vpg_regs_init(id)\</div><div class='add'>+		VPG_DCN401_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_vpg_registers vpg_regs[9];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_vpg_shift vpg_shift = {</div><div class='add'>+	DCN31_VPG_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_vpg_mask vpg_mask = {</div><div class='add'>+	DCN31_VPG_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define afmt_regs_init(id)\</div><div class='add'>+		AFMT_DCN3_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn30_afmt_registers afmt_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dcn30_afmt_shift afmt_shift = {</div><div class='add'>+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn30_afmt_mask afmt_mask = {</div><div class='add'>+	DCN3_AFMT_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define apg_regs_init(id)\</div><div class='add'>+	APG_DCN31_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_apg_registers apg_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_apg_shift apg_shift = {</div><div class='add'>+	DCN31_APG_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_apg_mask apg_mask = {</div><div class='add'>+		DCN31_APG_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define stream_enc_regs_init(id)\</div><div class='add'>+	SE_DCN4_01_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_stream_enc_registers stream_enc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn10_stream_encoder_shift se_shift = {</div><div class='add'>+		SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn10_stream_encoder_mask se_mask = {</div><div class='add'>+		SE_COMMON_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define aux_regs_init(id)\</div><div class='add'>+	DCN2_AUX_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];</div><div class='add'>+</div><div class='add'>+#define hpd_regs_init(id)\</div><div class='add'>+	HPD_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];</div><div class='add'>+</div><div class='add'>+#define link_regs_init(id, phyid)\</div><div class='add'>+	LE_DCN401_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn10_link_enc_registers link_enc_regs[4];</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static const struct dcn10_link_enc_shift le_shift = {</div><div class='add'>+	LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static const struct dcn10_link_enc_mask le_mask = {</div><div class='add'>+	LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define hpo_dp_stream_encoder_reg_init(id)\</div><div class='add'>+	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {</div><div class='add'>+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {</div><div class='add'>+	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define hpo_dp_link_encoder_reg_init(id)\</div><div class='add'>+	DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)</div><div class='add'>+	/*DCN3_1_RDPCSTX_REG_LIST(0),*/</div><div class='add'>+	/*DCN3_1_RDPCSTX_REG_LIST(1),*/</div><div class='add'>+	/*DCN3_1_RDPCSTX_REG_LIST(2),*/</div><div class='add'>+	/*DCN3_1_RDPCSTX_REG_LIST(3),*/</div><div class='add'>+</div><div class='add'>+static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {</div><div class='add'>+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {</div><div class='add'>+	DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define dpp_regs_init(id)\</div><div class='add'>+	DPP_REG_LIST_DCN401_COMMON_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn401_dpp_registers dpp_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn401_dpp_shift tf_shift = {</div><div class='add'>+		DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn401_dpp_mask tf_mask = {</div><div class='add'>+		DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define opp_regs_init(id)\</div><div class='add'>+	OPP_REG_LIST_DCN401_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn20_opp_registers opp_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn20_opp_shift opp_shift = {</div><div class='add'>+	OPP_MASK_SH_LIST_DCN20(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn20_opp_mask opp_mask = {</div><div class='add'>+	OPP_MASK_SH_LIST_DCN20(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define aux_engine_regs_init(id) \</div><div class='add'>+	AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \</div><div class='add'>+	SR_ARR_INIT(AUXP_IMPCAL, id, 0), \</div><div class='add'>+	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \</div><div class='add'>+	SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)</div><div class='add'>+</div><div class='add'>+static struct dce110_aux_registers aux_engine_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dce110_aux_registers_shift aux_shift = {</div><div class='add'>+	DCN_AUX_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce110_aux_registers_mask aux_mask = {</div><div class='add'>+	DCN_AUX_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define dwbc_regs_dcn401_init(id)\</div><div class='add'>+	DWBC_COMMON_REG_LIST_DCN30_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn30_dwbc_registers dwbc401_regs[1];</div><div class='add'>+</div><div class='add'>+static const struct dcn30_dwbc_shift dwbc401_shift = {</div><div class='add'>+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn30_dwbc_mask dwbc401_mask = {</div><div class='add'>+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define mcif_wb_regs_dcn3_init(id)\</div><div class='add'>+	MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];</div><div class='add'>+</div><div class='add'>+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {</div><div class='add'>+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {</div><div class='add'>+	MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define dsc_regs_init(id)\</div><div class='add'>+	DSC_REG_LIST_DCN401_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn401_dsc_registers dsc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn401_dsc_shift dsc_shift = {</div><div class='add'>+	DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn401_dsc_mask dsc_mask = {</div><div class='add'>+	DSC_REG_LIST_SH_MASK_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dcn401_mpc_registers mpc_regs;</div><div class='add'>+</div><div class='add'>+#define dcn_mpc_regs_init()\</div><div class='add'>+	MPC_REG_LIST_DCN4_01_RI(0),\</div><div class='add'>+	MPC_REG_LIST_DCN4_01_RI(1),\</div><div class='add'>+	MPC_REG_LIST_DCN4_01_RI(2),\</div><div class='add'>+	MPC_REG_LIST_DCN4_01_RI(3),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\</div><div class='add'>+	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)</div><div class='add'>+</div><div class='add'>+static const struct dcn401_mpc_shift mpc_shift = {</div><div class='add'>+	MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn401_mpc_mask mpc_mask = {</div><div class='add'>+	MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define optc_regs_init(id)\</div><div class='add'>+	OPTC_COMMON_REG_LIST_DCN401_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn_optc_registers optc_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn_optc_shift optc_shift = {</div><div class='add'>+	OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn_optc_mask optc_mask = {</div><div class='add'>+	OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define hubp_regs_init(id)\</div><div class='add'>+	HUBP_REG_LIST_DCN401_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn_hubp2_registers hubp_regs[4];</div><div class='add'>+</div><div class='add'>+static const struct dcn_hubp2_shift hubp_shift = {</div><div class='add'>+		HUBP_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn_hubp2_mask hubp_mask = {</div><div class='add'>+		HUBP_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dcn_hubbub_registers hubbub_reg;</div><div class='add'>+#define hubbub_reg_init()\</div><div class='add'>+		HUBBUB_REG_LIST_DCN4_01_RI(0)</div><div class='add'>+</div><div class='add'>+static const struct dcn_hubbub_shift hubbub_shift = {</div><div class='add'>+		HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn_hubbub_mask hubbub_mask = {</div><div class='add'>+		HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dccg_registers dccg_regs;</div><div class='add'>+</div><div class='add'>+#define dccg_regs_init()\</div><div class='add'>+	DCCG_REG_LIST_DCN401_RI()</div><div class='add'>+</div><div class='add'>+static const struct dccg_shift dccg_shift = {</div><div class='add'>+		DCCG_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dccg_mask dccg_mask = {</div><div class='add'>+		DCCG_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define SRII2(reg_name_pre, reg_name_post, id)\</div><div class='add'>+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \</div><div class='add'>+			## id ## _ ## reg_name_post ## _BASE_IDX) + \</div><div class='add'>+			reg ## reg_name_pre ## id ## _ ## reg_name_post</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define HWSEQ_DCN401_REG_LIST()\</div><div class='add'>+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \</div><div class='add'>+	SR(DIO_MEM_PWR_CTRL), \</div><div class='add'>+	SR(ODM_MEM_PWR_CTRL3), \</div><div class='add'>+	SR(MMHUBBUB_MEM_PWR_CNTL), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL2), \</div><div class='add'>+	SR(DCFCLK_CNTL),\</div><div class='add'>+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 0), \</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 1),\</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 2),\</div><div class='add'>+	SRII(PIXEL_RATE_CNTL, OTG, 3),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\</div><div class='add'>+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\</div><div class='add'>+	SR(MICROSECOND_TIME_BASE_DIV), \</div><div class='add'>+	SR(MILLISECOND_TIME_BASE_DIV), \</div><div class='add'>+	SR(DISPCLK_FREQ_CHANGE_CNTL), \</div><div class='add'>+	SR(RBBMIF_TIMEOUT_DIS), \</div><div class='add'>+	SR(RBBMIF_TIMEOUT_DIS_2), \</div><div class='add'>+	SR(DCHUBBUB_CRC_CTRL), \</div><div class='add'>+	SR(DPP_TOP0_DPP_CRC_CTRL), \</div><div class='add'>+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \</div><div class='add'>+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \</div><div class='add'>+	SR(MPC_CRC_CTRL), \</div><div class='add'>+	SR(MPC_CRC_RESULT_GB), \</div><div class='add'>+	SR(MPC_CRC_RESULT_C), \</div><div class='add'>+	SR(MPC_CRC_RESULT_AR), \</div><div class='add'>+	SR(DOMAIN0_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN1_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN2_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN3_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN16_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN17_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN18_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN19_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN22_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN23_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN24_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN25_PG_CONFIG), \</div><div class='add'>+	SR(DOMAIN0_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN1_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN2_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN3_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN16_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN17_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN18_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN19_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN22_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN23_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN24_PG_STATUS), \</div><div class='add'>+	SR(DOMAIN25_PG_STATUS), \</div><div class='add'>+	SR(DC_IP_REQUEST_CNTL), \</div><div class='add'>+	SR(AZALIA_AUDIO_DTO), \</div><div class='add'>+	SR(HPO_TOP_HW_CONTROL),\</div><div class='add'>+	SR(AZALIA_CONTROLLER_CLOCK_GATING)</div><div class='add'>+</div><div class='add'>+static struct dce_hwseq_registers hwseq_reg;</div><div class='add'>+</div><div class='add'>+#define hwseq_reg_init()\</div><div class='add'>+	HWSEQ_DCN401_REG_LIST()</div><div class='add'>+</div><div class='add'>+#define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\</div><div class='add'>+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \</div><div class='add'>+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \</div><div class='add'>+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \</div><div class='add'>+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \</div><div class='add'>+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \</div><div class='add'>+	HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \</div><div class='add'>+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \</div><div class='add'>+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)</div><div class='add'>+</div><div class='add'>+static const struct dce_hwseq_shift hwseq_shift = {</div><div class='add'>+		HWSEQ_DCN401_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_hwseq_mask hwseq_mask = {</div><div class='add'>+		HWSEQ_DCN401_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define vmid_regs_init(id)\</div><div class='add'>+		DCN20_VMID_REG_LIST_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dcn_vmid_registers vmid_regs[16];</div><div class='add'>+</div><div class='add'>+static const struct dcn20_vmid_shift vmid_shifts = {</div><div class='add'>+		DCN20_VMID_MASK_SH_LIST(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcn20_vmid_mask vmid_masks = {</div><div class='add'>+		DCN20_VMID_MASK_SH_LIST(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct resource_caps res_cap_dcn4_01 = {</div><div class='add'>+	.num_timing_generator = 4,</div><div class='add'>+	.num_opp = 4,</div><div class='add'>+	.num_video_plane = 4,</div><div class='add'>+	.num_audio = 4,</div><div class='add'>+	.num_stream_encoder = 4,</div><div class='add'>+	.num_hpo_dp_stream_encoder = 4,</div><div class='add'>+	.num_hpo_dp_link_encoder = 4,</div><div class='add'>+	.num_pll = 4,</div><div class='add'>+	.num_dwb = 1,</div><div class='add'>+	.num_ddc = 4,</div><div class='add'>+	.num_vmid = 16,</div><div class='add'>+	.num_mpc_3dlut = 4,</div><div class='add'>+	.num_dsc = 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_plane_cap plane_cap = {</div><div class='add'>+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,</div><div class='add'>+	.per_pixel_alpha = true,</div><div class='add'>+</div><div class='add'>+	.pixel_format_support = {</div><div class='add'>+			.argb8888 = true,</div><div class='add'>+			.nv12 = true,</div><div class='add'>+			.fp16 = true,</div><div class='add'>+			.p010 = true,</div><div class='add'>+			.ayuv = false,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	.max_upscale_factor = {</div><div class='add'>+			.argb8888 = 16000,</div><div class='add'>+			.nv12 = 16000,</div><div class='add'>+			.fp16 = 16000</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	// 6:1 downscaling ratio: 1000/6 = 166.666</div><div class='add'>+	.max_downscale_factor = {</div><div class='add'>+			.argb8888 = 167,</div><div class='add'>+			.nv12 = 167,</div><div class='add'>+			.fp16 = 167</div><div class='add'>+	},</div><div class='add'>+	64,</div><div class='add'>+	64</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_debug_options debug_defaults_drv = {</div><div class='add'>+	.disable_dmcu = true,</div><div class='add'>+	.force_abm_enable = false,</div><div class='add'>+	.clock_trace = true,</div><div class='add'>+	.disable_pplib_clock_request = false,</div><div class='add'>+	.pipe_split_policy = MPC_SPLIT_AVOID,</div><div class='add'>+	.force_single_disp_pipe_split = false,</div><div class='add'>+	.disable_dcc = DCC_ENABLE,</div><div class='add'>+	.vsr_support = true,</div><div class='add'>+	.performance_trace = false,</div><div class='add'>+	.max_downscale_src_width = 7680,/*upto 8K*/</div><div class='add'>+	.disable_pplib_wm_range = false,</div><div class='add'>+	.scl_reset_length10 = true,</div><div class='add'>+	.sanity_checks = false,</div><div class='add'>+	.underflow_assert_delay_us = 0xFFFFFFFF,</div><div class='add'>+	.dwb_fi_phase = -1, // -1 = disable,</div><div class='add'>+	.dmub_command_table = true,</div><div class='add'>+	.enable_mem_low_power = {</div><div class='add'>+		.bits = {</div><div class='add'>+			.vga = false,</div><div class='add'>+			.i2c = false,</div><div class='add'>+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled</div><div class='add'>+			.dscl = false,</div><div class='add'>+			.cm = false,</div><div class='add'>+			.mpc = false,</div><div class='add'>+			.optc = true,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	.use_max_lb = true,</div><div class='add'>+	.force_disable_subvp = false,</div><div class='add'>+	.disable_force_pstate_allow_on_hw_release = false,</div><div class='add'>+	.exit_idle_opt_for_cursor_updates = true,</div><div class='add'>+	.using_dml2 = true,</div><div class='add'>+	.using_dml21 = true,</div><div class='add'>+	.enable_single_display_2to1_odm_policy = true,</div><div class='add'>+</div><div class='add'>+	//must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions</div><div class='add'>+	.enable_double_buffered_dsc_pg_support = true,</div><div class='add'>+	.enable_dp_dig_pixel_rate_div_policy = 1,</div><div class='add'>+	.allow_sw_cursor_fallback = false,</div><div class='add'>+	.alloc_extra_way_for_cursor = true,</div><div class='add'>+	.min_prefetch_in_strobe_ns = 60000, // 60us</div><div class='add'>+	.disable_unbounded_requesting = false,</div><div class='add'>+	.dcc_meta_propagation_delay_us = 10,</div><div class='add'>+	.fams_version = {</div><div class='add'>+		.minor = 1,</div><div class='add'>+		.major = 2,</div><div class='add'>+	}, //v2.1</div><div class='add'>+	.fams2_config = {</div><div class='add'>+		.bits = {</div><div class='add'>+			.enable = true,</div><div class='add'>+			.enable_offload_flip = true,</div><div class='add'>+			.enable_stall_recovery = true,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	.force_cositing = CHROMA_COSITING_NONE + 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dc_check_config config_defaults = {</div><div class='add'>+	.enable_legacy_fast_update = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dce_aux *dcn401_aux_engine_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct aux_engine_dce110 *aux_engine =</div><div class='add'>+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!aux_engine)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT aux_engine_regs</div><div class='add'>+	aux_engine_regs_init(0),</div><div class='add'>+	aux_engine_regs_init(1),</div><div class='add'>+	aux_engine_regs_init(2),</div><div class='add'>+	aux_engine_regs_init(3);</div><div class='add'>+</div><div class='add'>+	dce110_aux_engine_construct(aux_engine, ctx, inst,</div><div class='add'>+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,</div><div class='add'>+				    &amp;aux_engine_regs[inst],</div><div class='add'>+					&amp;aux_mask,</div><div class='add'>+					&amp;aux_shift,</div><div class='add'>+					ctx-&gt;dc-&gt;caps.extended_aux_timeout_support);</div><div class='add'>+</div><div class='add'>+	return &amp;aux_engine-&gt;base;</div><div class='add'>+}</div><div class='add'>+#define i2c_inst_regs_init(id)\</div><div class='add'>+	I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)</div><div class='add'>+</div><div class='add'>+static struct dce_i2c_registers i2c_hw_regs[5];</div><div class='add'>+</div><div class='add'>+static const struct dce_i2c_shift i2c_shifts = {</div><div class='add'>+		I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dce_i2c_mask i2c_masks = {</div><div class='add'>+		I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct dce_i2c_hw *dcn401_i2c_hw_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dce_i2c_hw *dce_i2c_hw =</div><div class='add'>+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!dce_i2c_hw)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT i2c_hw_regs</div><div class='add'>+		i2c_inst_regs_init(1),</div><div class='add'>+		i2c_inst_regs_init(2),</div><div class='add'>+		i2c_inst_regs_init(3),</div><div class='add'>+		i2c_inst_regs_init(4);</div><div class='add'>+</div><div class='add'>+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,</div><div class='add'>+				    &amp;i2c_hw_regs[inst], &amp;i2c_shifts, &amp;i2c_masks);</div><div class='add'>+</div><div class='add'>+	return dce_i2c_hw;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct clock_source *dcn401_clock_source_create(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		struct dc_bios *bios,</div><div class='add'>+		enum clock_source_id id,</div><div class='add'>+		const struct dce110_clk_src_regs *regs,</div><div class='add'>+		bool dp_clk_src)</div><div class='add'>+{</div><div class='add'>+	struct dce110_clk_src *clk_src =</div><div class='add'>+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!clk_src)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (dcn401_clk_src_construct(clk_src, ctx, bios, id,</div><div class='add'>+			regs, &amp;cs_shift, &amp;cs_mask)) {</div><div class='add'>+		clk_src-&gt;base.dp_clk_src = dp_clk_src;</div><div class='add'>+		return &amp;clk_src-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kfree(clk_src);</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),</div><div class='add'>+					  GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!hubbub2)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hubbub_reg</div><div class='add'>+	hubbub_reg_init();</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT vmid_regs</div><div class='add'>+	vmid_regs_init(0),</div><div class='add'>+	vmid_regs_init(1),</div><div class='add'>+	vmid_regs_init(2),</div><div class='add'>+	vmid_regs_init(3),</div><div class='add'>+	vmid_regs_init(4),</div><div class='add'>+	vmid_regs_init(5),</div><div class='add'>+	vmid_regs_init(6),</div><div class='add'>+	vmid_regs_init(7),</div><div class='add'>+	vmid_regs_init(8),</div><div class='add'>+	vmid_regs_init(9),</div><div class='add'>+	vmid_regs_init(10),</div><div class='add'>+	vmid_regs_init(11),</div><div class='add'>+	vmid_regs_init(12),</div><div class='add'>+	vmid_regs_init(13),</div><div class='add'>+	vmid_regs_init(14),</div><div class='add'>+	vmid_regs_init(15);</div><div class='add'>+</div><div class='add'>+	hubbub401_construct(hubbub2, ctx,</div><div class='add'>+			&amp;hubbub_reg,</div><div class='add'>+			&amp;hubbub_shift,</div><div class='add'>+			&amp;hubbub_mask,</div><div class='add'>+			DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,</div><div class='add'>+			8, //dml2 ip_params_st.pixel_chunk_size_kbytes</div><div class='add'>+			DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; res_cap_dcn4_01.num_vmid; i++) {</div><div class='add'>+		struct dcn20_vmid *vmid = &amp;hubbub2-&gt;vmid[i];</div><div class='add'>+</div><div class='add'>+		vmid-&gt;ctx = ctx;</div><div class='add'>+</div><div class='add'>+		vmid-&gt;regs = &amp;vmid_regs[i];</div><div class='add'>+		vmid-&gt;shifts = &amp;vmid_shifts;</div><div class='add'>+		vmid-&gt;masks = &amp;vmid_masks;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;hubbub2-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hubp *dcn401_hubp_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_hubp *hubp2 =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!hubp2)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hubp_regs</div><div class='add'>+		hubp_regs_init(0),</div><div class='add'>+		hubp_regs_init(1),</div><div class='add'>+		hubp_regs_init(2),</div><div class='add'>+		hubp_regs_init(3);</div><div class='add'>+</div><div class='add'>+	if (hubp401_construct(hubp2, ctx, inst,</div><div class='add'>+			&amp;hubp_regs[inst], &amp;hubp_shift, &amp;hubp_mask))</div><div class='add'>+		return &amp;hubp2-&gt;base;</div><div class='add'>+</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	kfree(hubp2);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_dpp_destroy(struct dpp **dpp)</div><div class='add'>+{</div><div class='add'>+	kfree(TO_DCN401_DPP(*dpp));</div><div class='add'>+	*dpp = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dpp *dcn401_dpp_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dpp *dpp401 =</div><div class='add'>+		kzalloc(sizeof(struct dcn401_dpp), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!dpp401)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dpp_regs</div><div class='add'>+	dpp_regs_init(0),</div><div class='add'>+	dpp_regs_init(1),</div><div class='add'>+	dpp_regs_init(2),</div><div class='add'>+	dpp_regs_init(3);</div><div class='add'>+</div><div class='add'>+	if (dpp401_construct(dpp401, ctx, inst,</div><div class='add'>+			&amp;dpp_regs[inst], &amp;tf_shift, &amp;tf_mask))</div><div class='add'>+		return &amp;dpp401-&gt;base;</div><div class='add'>+</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	kfree(dpp401);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct mpc *dcn401_mpc_create(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		int num_mpcc,</div><div class='add'>+		int num_rmu)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_mpc *mpc401 = kzalloc(sizeof(struct dcn401_mpc),</div><div class='add'>+					  GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!mpc401)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT mpc_regs</div><div class='add'>+	dcn_mpc_regs_init();</div><div class='add'>+</div><div class='add'>+	dcn401_mpc_construct(mpc401, ctx,</div><div class='add'>+			&amp;mpc_regs,</div><div class='add'>+			&amp;mpc_shift,</div><div class='add'>+			&amp;mpc_mask,</div><div class='add'>+			num_mpcc,</div><div class='add'>+			num_rmu);</div><div class='add'>+</div><div class='add'>+	return &amp;mpc401-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct output_pixel_processor *dcn401_opp_create(</div><div class='add'>+	struct dc_context *ctx, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_opp *opp4 =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!opp4) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT opp_regs</div><div class='add'>+	opp_regs_init(0),</div><div class='add'>+	opp_regs_init(1),</div><div class='add'>+	opp_regs_init(2),</div><div class='add'>+	opp_regs_init(3);</div><div class='add'>+</div><div class='add'>+	dcn20_opp_construct(opp4, ctx, inst,</div><div class='add'>+			&amp;opp_regs[inst], &amp;opp_shift, &amp;opp_mask);</div><div class='add'>+	return &amp;opp4-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static struct timing_generator *dcn401_timing_generator_create(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		uint32_t instance)</div><div class='add'>+{</div><div class='add'>+	struct optc *tgn10 =</div><div class='add'>+		kzalloc(sizeof(struct optc), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!tgn10)</div><div class='add'>+		return NULL;</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT optc_regs</div><div class='add'>+	optc_regs_init(0),</div><div class='add'>+	optc_regs_init(1),</div><div class='add'>+	optc_regs_init(2),</div><div class='add'>+	optc_regs_init(3);</div><div class='add'>+</div><div class='add'>+	tgn10-&gt;base.inst = instance;</div><div class='add'>+	tgn10-&gt;base.ctx = ctx;</div><div class='add'>+</div><div class='add'>+	tgn10-&gt;tg_regs = &amp;optc_regs[instance];</div><div class='add'>+	tgn10-&gt;tg_shift = &amp;optc_shift;</div><div class='add'>+	tgn10-&gt;tg_mask = &amp;optc_mask;</div><div class='add'>+</div><div class='add'>+	dcn401_timing_generator_init(tgn10);</div><div class='add'>+</div><div class='add'>+	return &amp;tgn10-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct encoder_feature_support link_enc_feature = {</div><div class='add'>+		.max_hdmi_deep_color = COLOR_DEPTH_121212,</div><div class='add'>+		.max_hdmi_pixel_clock = 600000,</div><div class='add'>+		.hdmi_ycbcr420_supported = true,</div><div class='add'>+		.dp_ycbcr420_supported = true,</div><div class='add'>+		.fec_supported = true,</div><div class='add'>+		.flags.bits.IS_HBR2_CAPABLE = true,</div><div class='add'>+		.flags.bits.IS_HBR3_CAPABLE = true,</div><div class='add'>+		.flags.bits.IS_TPS3_CAPABLE = true,</div><div class='add'>+		.flags.bits.IS_TPS4_CAPABLE = true</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct link_encoder *dcn401_link_encoder_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	const struct encoder_init_data *enc_init_data)</div><div class='add'>+{</div><div class='add'>+	struct dcn20_link_encoder *enc20 =</div><div class='add'>+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!enc20 || enc_init_data-&gt;hpd_source &gt;= ARRAY_SIZE(link_enc_hpd_regs))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT link_enc_aux_regs</div><div class='add'>+	aux_regs_init(0),</div><div class='add'>+	aux_regs_init(1),</div><div class='add'>+	aux_regs_init(2),</div><div class='add'>+	aux_regs_init(3);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT link_enc_hpd_regs</div><div class='add'>+	hpd_regs_init(0),</div><div class='add'>+	hpd_regs_init(1),</div><div class='add'>+	hpd_regs_init(2),</div><div class='add'>+	hpd_regs_init(3);</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT link_enc_regs</div><div class='add'>+	link_regs_init(0, A),</div><div class='add'>+	link_regs_init(1, B),</div><div class='add'>+	link_regs_init(2, C),</div><div class='add'>+	link_regs_init(3, D);</div><div class='add'>+</div><div class='add'>+	dcn401_link_encoder_construct(enc20,</div><div class='add'>+			enc_init_data,</div><div class='add'>+			&amp;link_enc_feature,</div><div class='add'>+			&amp;link_enc_regs[enc_init_data-&gt;transmitter],</div><div class='add'>+			&amp;link_enc_aux_regs[enc_init_data-&gt;channel - 1],</div><div class='add'>+			&amp;link_enc_hpd_regs[enc_init_data-&gt;hpd_source],</div><div class='add'>+			&amp;le_shift,</div><div class='add'>+			&amp;le_mask);</div><div class='add'>+	return &amp;enc20-&gt;enc10.base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_dce_straps(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	struct resource_straps *straps)</div><div class='add'>+{</div><div class='add'>+	generic_reg_get(ctx, ctx-&gt;dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,</div><div class='add'>+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &amp;straps-&gt;dc_pinstraps_audio);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct audio *dcn401_create_audio(</div><div class='add'>+		struct dc_context *ctx, unsigned int inst)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT audio_regs</div><div class='add'>+	audio_regs_init(0),</div><div class='add'>+	audio_regs_init(1),</div><div class='add'>+	audio_regs_init(2),</div><div class='add'>+	audio_regs_init(3),</div><div class='add'>+	audio_regs_init(4);</div><div class='add'>+</div><div class='add'>+	return dce_audio_create(ctx, inst,</div><div class='add'>+			&amp;audio_regs[inst], &amp;audio_shift, &amp;audio_mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct vpg *dcn401_vpg_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!vpg4)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT vpg_regs</div><div class='add'>+	vpg_regs_init(0),</div><div class='add'>+	vpg_regs_init(1),</div><div class='add'>+	vpg_regs_init(2),</div><div class='add'>+	vpg_regs_init(3),</div><div class='add'>+	vpg_regs_init(4),</div><div class='add'>+	vpg_regs_init(5),</div><div class='add'>+	vpg_regs_init(6),</div><div class='add'>+	vpg_regs_init(7),</div><div class='add'>+	vpg_regs_init(8);</div><div class='add'>+</div><div class='add'>+	vpg31_construct(vpg4, ctx, inst,</div><div class='add'>+			&amp;vpg_regs[inst],</div><div class='add'>+			&amp;vpg_shift,</div><div class='add'>+			&amp;vpg_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;vpg4-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct afmt *dcn401_afmt_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn30_afmt *afmt401 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!afmt401)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT afmt_regs</div><div class='add'>+	afmt_regs_init(0),</div><div class='add'>+	afmt_regs_init(1),</div><div class='add'>+	afmt_regs_init(2),</div><div class='add'>+	afmt_regs_init(3),</div><div class='add'>+	afmt_regs_init(4);</div><div class='add'>+</div><div class='add'>+	afmt3_construct(afmt401, ctx, inst,</div><div class='add'>+			&amp;afmt_regs[inst],</div><div class='add'>+			&amp;afmt_shift,</div><div class='add'>+			&amp;afmt_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;afmt401-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct apg *dcn401_apg_create(</div><div class='add'>+	struct dc_context *ctx,</div><div class='add'>+	uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!apg31)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT apg_regs</div><div class='add'>+	apg_regs_init(0),</div><div class='add'>+	apg_regs_init(1),</div><div class='add'>+	apg_regs_init(2),</div><div class='add'>+	apg_regs_init(3);</div><div class='add'>+</div><div class='add'>+	apg31_construct(apg31, ctx, inst,</div><div class='add'>+			&amp;apg_regs[inst],</div><div class='add'>+			&amp;apg_shift,</div><div class='add'>+			&amp;apg_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;apg31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct stream_encoder *dcn401_stream_encoder_create(</div><div class='add'>+	enum engine_id eng_id,</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dcn10_stream_encoder *enc1;</div><div class='add'>+	struct vpg *vpg;</div><div class='add'>+	struct afmt *afmt;</div><div class='add'>+	int vpg_inst;</div><div class='add'>+	int afmt_inst;</div><div class='add'>+</div><div class='add'>+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */</div><div class='add'>+	if (eng_id &lt;= ENGINE_ID_DIGF) {</div><div class='add'>+		vpg_inst = eng_id;</div><div class='add'>+		afmt_inst = eng_id;</div><div class='add'>+	} else</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);</div><div class='add'>+	vpg = dcn401_vpg_create(ctx, vpg_inst);</div><div class='add'>+	afmt = dcn401_afmt_create(ctx, afmt_inst);</div><div class='add'>+</div><div class='add'>+	if (!enc1 || !vpg || !afmt || eng_id &gt;= ARRAY_SIZE(stream_enc_regs)) {</div><div class='add'>+		kfree(enc1);</div><div class='add'>+		kfree(vpg);</div><div class='add'>+		kfree(afmt);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT stream_enc_regs</div><div class='add'>+	stream_enc_regs_init(0),</div><div class='add'>+	stream_enc_regs_init(1),</div><div class='add'>+	stream_enc_regs_init(2),</div><div class='add'>+	stream_enc_regs_init(3);</div><div class='add'>+	//stream_enc_regs_init(4);</div><div class='add'>+</div><div class='add'>+	dcn401_dio_stream_encoder_construct(enc1, ctx, ctx-&gt;dc_bios,</div><div class='add'>+					eng_id, vpg, afmt,</div><div class='add'>+					&amp;stream_enc_regs[eng_id],</div><div class='add'>+					&amp;se_shift, &amp;se_mask);</div><div class='add'>+	return &amp;enc1-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(</div><div class='add'>+	enum engine_id eng_id,</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;</div><div class='add'>+	struct vpg *vpg;</div><div class='add'>+	struct apg *apg;</div><div class='add'>+	uint32_t hpo_dp_inst;</div><div class='add'>+	uint32_t vpg_inst;</div><div class='add'>+	uint32_t apg_inst;</div><div class='add'>+</div><div class='add'>+	ASSERT((eng_id &gt;= ENGINE_ID_HPO_DP_0) &amp;&amp; (eng_id &lt;= ENGINE_ID_HPO_DP_3));</div><div class='add'>+	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;</div><div class='add'>+</div><div class='add'>+	/* Mapping of VPG register blocks to HPO DP block instance:</div><div class='add'>+	 * VPG[6] -&gt; HPO_DP[0]</div><div class='add'>+	 * VPG[7] -&gt; HPO_DP[1]</div><div class='add'>+	 * VPG[8] -&gt; HPO_DP[2]</div><div class='add'>+	 * VPG[9] -&gt; HPO_DP[3]</div><div class='add'>+	 */</div><div class='add'>+	vpg_inst = hpo_dp_inst + 5;</div><div class='add'>+</div><div class='add'>+	/* Mapping of APG register blocks to HPO DP block instance:</div><div class='add'>+	 * APG[0] -&gt; HPO_DP[0]</div><div class='add'>+	 * APG[1] -&gt; HPO_DP[1]</div><div class='add'>+	 * APG[2] -&gt; HPO_DP[2]</div><div class='add'>+	 * APG[3] -&gt; HPO_DP[3]</div><div class='add'>+	 */</div><div class='add'>+	apg_inst = hpo_dp_inst;</div><div class='add'>+</div><div class='add'>+	/* allocate HPO stream encoder and create VPG sub-block */</div><div class='add'>+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);</div><div class='add'>+	vpg = dcn401_vpg_create(ctx, vpg_inst);</div><div class='add'>+	apg = dcn401_apg_create(ctx, apg_inst);</div><div class='add'>+</div><div class='add'>+	if (!hpo_dp_enc31 || !vpg || !apg) {</div><div class='add'>+		kfree(hpo_dp_enc31);</div><div class='add'>+		kfree(vpg);</div><div class='add'>+		kfree(apg);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hpo_dp_stream_enc_regs</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(0),</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(1),</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(2),</div><div class='add'>+	hpo_dp_stream_encoder_reg_init(3);</div><div class='add'>+</div><div class='add'>+	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx-&gt;dc_bios,</div><div class='add'>+					hpo_dp_inst, eng_id, vpg, apg,</div><div class='add'>+					&amp;hpo_dp_stream_enc_regs[hpo_dp_inst],</div><div class='add'>+					&amp;hpo_dp_se_shift, &amp;hpo_dp_se_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;hpo_dp_enc31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(</div><div class='add'>+	uint8_t inst,</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;</div><div class='add'>+</div><div class='add'>+	/* allocate HPO link encoder */</div><div class='add'>+	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);</div><div class='add'>+	if (!hpo_dp_enc31)</div><div class='add'>+		return NULL; /* out of memory */</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hpo_dp_link_enc_regs</div><div class='add'>+	hpo_dp_link_encoder_reg_init(0),</div><div class='add'>+	hpo_dp_link_encoder_reg_init(1),</div><div class='add'>+	hpo_dp_link_encoder_reg_init(2),</div><div class='add'>+	hpo_dp_link_encoder_reg_init(3);</div><div class='add'>+</div><div class='add'>+	hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,</div><div class='add'>+					&amp;hpo_dp_link_enc_regs[inst],</div><div class='add'>+					&amp;hpo_dp_le_shift, &amp;hpo_dp_le_mask);</div><div class='add'>+</div><div class='add'>+	return &amp;hpo_dp_enc31-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_available_chans = 1;</div><div class='add'>+</div><div class='add'>+	/* channels for MALL must be a power of 2 */</div><div class='add'>+	while (num_chans &gt; 1) {</div><div class='add'>+		num_available_chans = (num_available_chans &lt;&lt; 1);</div><div class='add'>+		num_chans = (num_chans &gt;&gt; 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* cannot be odd */</div><div class='add'>+	num_available_chans &amp;= ~1;</div><div class='add'>+</div><div class='add'>+	/* clamp to max available channels for MALL per ASIC */</div><div class='add'>+	if (ASICREV_IS_GC_12_0_0_A0(dc-&gt;ctx-&gt;asic_id.hw_internal_rev)) {</div><div class='add'>+		num_available_chans = num_available_chans &gt; 16 ? 16 : num_available_chans;</div><div class='add'>+	} else if (ASICREV_IS_GC_12_0_1_A0(dc-&gt;ctx-&gt;asic_id.hw_internal_rev)) {</div><div class='add'>+		num_available_chans = num_available_chans &gt; 8 ? 8 : num_available_chans;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return num_available_chans;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dce_hwseq *dcn401_hwseq_create(</div><div class='add'>+	struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT hwseq_reg</div><div class='add'>+	hwseq_reg_init();</div><div class='add'>+</div><div class='add'>+	if (hws) {</div><div class='add'>+		hws-&gt;ctx = ctx;</div><div class='add'>+		hws-&gt;regs = &amp;hwseq_reg;</div><div class='add'>+		hws-&gt;shifts = &amp;hwseq_shift;</div><div class='add'>+		hws-&gt;masks = &amp;hwseq_mask;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return hws;</div><div class='add'>+}</div><div class='add'>+static const struct resource_create_funcs res_create_funcs = {</div><div class='add'>+	.read_dce_straps = read_dce_straps,</div><div class='add'>+	.create_audio = dcn401_create_audio,</div><div class='add'>+	.create_stream_encoder = dcn401_stream_encoder_create,</div><div class='add'>+	.create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,</div><div class='add'>+	.create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,</div><div class='add'>+	.create_hwseq = dcn401_hwseq_create,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)</div><div class='add'>+{</div><div class='add'>+	kfree(container_of(*dsc, struct dcn401_dsc, base));</div><div class='add'>+	*dsc = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.stream_enc_count; i++) {</div><div class='add'>+		if (pool-&gt;base.stream_enc[i] != NULL) {</div><div class='add'>+			if (pool-&gt;base.stream_enc[i]-&gt;vpg != NULL) {</div><div class='add'>+				kfree(DCN31_VPG_FROM_VPG(pool-&gt;base.stream_enc[i]-&gt;vpg));</div><div class='add'>+				pool-&gt;base.stream_enc[i]-&gt;vpg = NULL;</div><div class='add'>+			}</div><div class='add'>+			if (pool-&gt;base.stream_enc[i]-&gt;afmt != NULL) {</div><div class='add'>+				kfree(DCN30_AFMT_FROM_AFMT(pool-&gt;base.stream_enc[i]-&gt;afmt));</div><div class='add'>+				pool-&gt;base.stream_enc[i]-&gt;afmt = NULL;</div><div class='add'>+			}</div><div class='add'>+			kfree(DCN10STRENC_FROM_STRENC(pool-&gt;base.stream_enc[i]));</div><div class='add'>+			pool-&gt;base.stream_enc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.hpo_dp_stream_enc_count; i++) {</div><div class='add'>+		if (pool-&gt;base.hpo_dp_stream_enc[i] != NULL) {</div><div class='add'>+			if (pool-&gt;base.hpo_dp_stream_enc[i]-&gt;vpg != NULL) {</div><div class='add'>+				kfree(DCN31_VPG_FROM_VPG(pool-&gt;base.hpo_dp_stream_enc[i]-&gt;vpg));</div><div class='add'>+				pool-&gt;base.hpo_dp_stream_enc[i]-&gt;vpg = NULL;</div><div class='add'>+			}</div><div class='add'>+			if (pool-&gt;base.hpo_dp_stream_enc[i]-&gt;apg != NULL) {</div><div class='add'>+				kfree(DCN31_APG_FROM_APG(pool-&gt;base.hpo_dp_stream_enc[i]-&gt;apg));</div><div class='add'>+				pool-&gt;base.hpo_dp_stream_enc[i]-&gt;apg = NULL;</div><div class='add'>+			}</div><div class='add'>+			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool-&gt;base.hpo_dp_stream_enc[i]));</div><div class='add'>+			pool-&gt;base.hpo_dp_stream_enc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.hpo_dp_link_enc_count; i++) {</div><div class='add'>+		if (pool-&gt;base.hpo_dp_link_enc[i] != NULL) {</div><div class='add'>+			kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool-&gt;base.hpo_dp_link_enc[i]));</div><div class='add'>+			pool-&gt;base.hpo_dp_link_enc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_dsc; i++) {</div><div class='add'>+		if (pool-&gt;base.dscs[i] != NULL)</div><div class='add'>+			dcn401_dsc_destroy(&amp;pool-&gt;base.dscs[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.mpc != NULL) {</div><div class='add'>+		kfree(TO_DCN20_MPC(pool-&gt;base.mpc));</div><div class='add'>+		pool-&gt;base.mpc = NULL;</div><div class='add'>+	}</div><div class='add'>+	if (pool-&gt;base.hubbub != NULL) {</div><div class='add'>+		kfree(TO_DCN20_HUBBUB(pool-&gt;base.hubbub));</div><div class='add'>+		pool-&gt;base.hubbub = NULL;</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.pipe_count; i++) {</div><div class='add'>+		if (pool-&gt;base.dpps[i] != NULL)</div><div class='add'>+			dcn401_dpp_destroy(&amp;pool-&gt;base.dpps[i]);</div><div class='add'>+</div><div class='add'>+		if (pool-&gt;base.ipps[i] != NULL)</div><div class='add'>+			pool-&gt;base.ipps[i]-&gt;funcs-&gt;ipp_destroy(&amp;pool-&gt;base.ipps[i]);</div><div class='add'>+</div><div class='add'>+		if (pool-&gt;base.hubps[i] != NULL) {</div><div class='add'>+			kfree(TO_DCN20_HUBP(pool-&gt;base.hubps[i]));</div><div class='add'>+			pool-&gt;base.hubps[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (pool-&gt;base.irqs != NULL) {</div><div class='add'>+			dal_irq_service_destroy(&amp;pool-&gt;base.irqs);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_ddc; i++) {</div><div class='add'>+		if (pool-&gt;base.engines[i] != NULL)</div><div class='add'>+			dce110_engine_destroy(&amp;pool-&gt;base.engines[i]);</div><div class='add'>+		if (pool-&gt;base.hw_i2cs[i] != NULL) {</div><div class='add'>+			kfree(pool-&gt;base.hw_i2cs[i]);</div><div class='add'>+			pool-&gt;base.hw_i2cs[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+		if (pool-&gt;base.sw_i2cs[i] != NULL) {</div><div class='add'>+			kfree(pool-&gt;base.sw_i2cs[i]);</div><div class='add'>+			pool-&gt;base.sw_i2cs[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_opp; i++) {</div><div class='add'>+		if (pool-&gt;base.opps[i] != NULL)</div><div class='add'>+			pool-&gt;base.opps[i]-&gt;funcs-&gt;opp_destroy(&amp;pool-&gt;base.opps[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+		if (pool-&gt;base.timing_generators[i] != NULL)	{</div><div class='add'>+			kfree(DCN10TG_FROM_TG(pool-&gt;base.timing_generators[i]));</div><div class='add'>+			pool-&gt;base.timing_generators[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_dwb; i++) {</div><div class='add'>+		if (pool-&gt;base.dwbc[i] != NULL) {</div><div class='add'>+			kfree(TO_DCN30_DWBC(pool-&gt;base.dwbc[i]));</div><div class='add'>+			pool-&gt;base.dwbc[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+		if (pool-&gt;base.mcif_wb[i] != NULL) {</div><div class='add'>+			kfree(TO_DCN30_MMHUBBUB(pool-&gt;base.mcif_wb[i]));</div><div class='add'>+			pool-&gt;base.mcif_wb[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.audio_count; i++) {</div><div class='add'>+		if (pool-&gt;base.audios[i])</div><div class='add'>+			dce_aud_destroy(&amp;pool-&gt;base.audios[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.clk_src_count; i++) {</div><div class='add'>+		if (pool-&gt;base.clock_sources[i] != NULL) {</div><div class='add'>+			dcn20_clock_source_destroy(&amp;pool-&gt;base.clock_sources[i]);</div><div class='add'>+			pool-&gt;base.clock_sources[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_mpc_3dlut; i++) {</div><div class='add'>+		if (pool-&gt;base.mpc_lut[i] != NULL) {</div><div class='add'>+			dc_3dlut_func_release(pool-&gt;base.mpc_lut[i]);</div><div class='add'>+			pool-&gt;base.mpc_lut[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+		if (pool-&gt;base.mpc_shaper[i] != NULL) {</div><div class='add'>+			dc_transfer_func_release(pool-&gt;base.mpc_shaper[i]);</div><div class='add'>+			pool-&gt;base.mpc_shaper[i] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.dp_clock_source != NULL) {</div><div class='add'>+		dcn20_clock_source_destroy(&amp;pool-&gt;base.dp_clock_source);</div><div class='add'>+		pool-&gt;base.dp_clock_source = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+		if (pool-&gt;base.multiple_abms[i] != NULL)</div><div class='add'>+			dce_abm_destroy(&amp;pool-&gt;base.multiple_abms[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.psr != NULL)</div><div class='add'>+		dmub_psr_destroy(&amp;pool-&gt;base.psr);</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.dccg != NULL)</div><div class='add'>+		dcn_dccg_destroy(&amp;pool-&gt;base.dccg);</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;base.oem_device != NULL) {</div><div class='add'>+		struct dc *dc = pool-&gt;base.oem_device-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+		dc-&gt;link_srv-&gt;destroy_ddc_service(&amp;pool-&gt;base.oem_device);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t dwb_count = pool-&gt;res_cap-&gt;num_dwb;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dwb_count; i++) {</div><div class='add'>+		struct dcn30_dwbc *dwbc401 = kzalloc(sizeof(struct dcn30_dwbc),</div><div class='add'>+						    GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+		if (!dwbc401) {</div><div class='add'>+			dm_error("DC: failed to create dwbc401!\n");</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dwbc401_regs</div><div class='add'>+		dwbc_regs_dcn401_init(0);</div><div class='add'>+</div><div class='add'>+		dcn30_dwbc_construct(dwbc401, ctx,</div><div class='add'>+				&amp;dwbc401_regs[i],</div><div class='add'>+				&amp;dwbc401_shift,</div><div class='add'>+				&amp;dwbc401_mask,</div><div class='add'>+				i);</div><div class='add'>+</div><div class='add'>+		pool-&gt;dwbc[i] = &amp;dwbc401-&gt;base;</div><div class='add'>+</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	uint32_t dwb_count = pool-&gt;res_cap-&gt;num_dwb;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dwb_count; i++) {</div><div class='add'>+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),</div><div class='add'>+						    GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+		if (!mcif_wb30) {</div><div class='add'>+			dm_error("DC: failed to create mcif_wb30!\n");</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT mcif_wb30_regs</div><div class='add'>+		mcif_wb_regs_dcn3_init(0);</div><div class='add'>+</div><div class='add'>+		dcn32_mmhubbub_construct(mcif_wb30, ctx,</div><div class='add'>+				&amp;mcif_wb30_regs[i],</div><div class='add'>+				&amp;mcif_wb30_shift,</div><div class='add'>+				&amp;mcif_wb30_mask,</div><div class='add'>+				i);</div><div class='add'>+</div><div class='add'>+		pool-&gt;mcif_wb[i] = &amp;mcif_wb30-&gt;base;</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct display_stream_compressor *dcn401_dsc_create(</div><div class='add'>+	struct dc_context *ctx, uint32_t inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_dsc *dsc =</div><div class='add'>+		kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!dsc) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dsc_regs</div><div class='add'>+	dsc_regs_init(0),</div><div class='add'>+	dsc_regs_init(1),</div><div class='add'>+	dsc_regs_init(2),</div><div class='add'>+	dsc_regs_init(3);</div><div class='add'>+</div><div class='add'>+	dsc401_construct(dsc, ctx, inst, &amp;dsc_regs[inst], &amp;dsc_shift, &amp;dsc_mask);</div><div class='add'>+	dsc401_set_fgcg(dsc,</div><div class='add'>+			       ctx-&gt;dc-&gt;debug.enable_fine_grain_clock_gating.bits.dsc);</div><div class='add'>+</div><div class='add'>+	//dsc-&gt;max_image_width = 6016;</div><div class='add'>+	dsc-&gt;max_image_width = 5760;</div><div class='add'>+</div><div class='add'>+	return &amp;dsc-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_destroy_resource_pool(struct resource_pool **pool)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);</div><div class='add'>+</div><div class='add'>+	dcn401_resource_destruct(dcn401_pool);</div><div class='add'>+	kfree(dcn401_pool);</div><div class='add'>+	*pool = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dc_cap_funcs cap_funcs = {</div><div class='add'>+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,</div><div class='add'>+	.get_subvp_en = dcn32_subvp_in_use,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)</div><div class='add'>+{</div><div class='add'>+	/* re-calculate the available MALL size if required */</div><div class='add'>+	if (bw_params-&gt;num_channels &gt; 0) {</div><div class='add'>+		dc-&gt;caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(</div><div class='add'>+			dc, bw_params-&gt;num_channels) *</div><div class='add'>+			dc-&gt;caps.mall_size_per_mem_channel * 1024 * 1024;</div><div class='add'>+		dc-&gt;caps.mall_size_total = dc-&gt;caps.max_cab_allocation_bytes;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;current_state &amp;&amp; dc-&gt;current_state-&gt;bw_ctx.dml2)</div><div class='add'>+		dml2_reinit(dc, &amp;dc-&gt;dml2_options, &amp;dc-&gt;current_state-&gt;bw_ctx.dml2);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.using_dml2 &amp;&amp; dc-&gt;current_state &amp;&amp; dc-&gt;current_state-&gt;bw_ctx.dml2_dc_power_source)</div><div class='add'>+		dml2_reinit(dc, &amp;dc-&gt;dml2_dc_power_options, &amp;dc-&gt;current_state-&gt;bw_ctx.dml2_dc_power_source);</div><div class='add'>+</div><div class='add'>+	DC_FP_END();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	plane_state-&gt;tiling_info.gfxversion = DcGfxAddr3;</div><div class='add'>+	plane_state-&gt;tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;</div><div class='add'>+	return DC_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dc_status dcn401_validate_bandwidth(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	enum dc_status status = DC_OK;</div><div class='add'>+	const struct dc_stream_state *stream;</div><div class='add'>+</div><div class='add'>+	/* reset cursor limitations on subvp */</div><div class='add'>+	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		stream = context-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+		if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {</div><div class='add'>+			dc_state_set_stream_cursor_subvp_limit(stream, context, false);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;debug.using_dml2)</div><div class='add'>+		status = dml2_validate(dc, context,</div><div class='add'>+				context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+				validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING &amp;&amp; status == DC_OK &amp;&amp; dc_state_is_subvp_in_use(context)) {</div><div class='add'>+		/* check new stream configuration still supports cursor if subvp used */</div><div class='add'>+		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+			stream = context-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+			if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &amp;&amp;</div><div class='add'>+					stream-&gt;cursor_position.enable &amp;&amp;</div><div class='add'>+					!dc_stream_check_cursor_attributes(stream, context, &amp;stream-&gt;cursor_attributes))	{</div><div class='add'>+				/* hw cursor cannot be supported with subvp active, so disable subvp for now */</div><div class='add'>+				dc_state_set_stream_cursor_subvp_limit(stream, context, true);</div><div class='add'>+				status = DC_FAIL_HW_CURSOR_SUPPORT;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING &amp;&amp; status == DC_FAIL_HW_CURSOR_SUPPORT) {</div><div class='add'>+		/* attempt to validate again with subvp disabled due to cursor */</div><div class='add'>+		if (dc-&gt;debug.using_dml2)</div><div class='add'>+			status = dml2_validate(dc, context,</div><div class='add'>+					context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2,</div><div class='add'>+					validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_prepare_mcache_programming(struct dc *dc,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	if (dc-&gt;debug.using_dml21)</div><div class='add'>+		dml2_prepare_mcache_programming(dc, context,</div><div class='add'>+				context-&gt;power_source == DC_POWER_SOURCE_DC ? context-&gt;bw_ctx.dml2_dc_power_source : context-&gt;bw_ctx.dml2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	const struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='add'>+	struct dc_link *link = stream-&gt;link;</div><div class='add'>+	struct link_encoder *link_enc = pipe_ctx-&gt;link_res.dio_link_enc;</div><div class='add'>+	struct pixel_clk_params *pixel_clk_params = &amp;pipe_ctx-&gt;stream_res.pix_clk_params;</div><div class='add'>+</div><div class='add'>+	pixel_clk_params-&gt;requested_pix_clk_100hz = stream-&gt;timing.pix_clk_100hz;</div><div class='add'>+</div><div class='add'>+	if (pipe_ctx-&gt;dsc_padding_params.dsc_hactive_padding != 0)</div><div class='add'>+		pixel_clk_params-&gt;requested_pix_clk_100hz = pipe_ctx-&gt;dsc_padding_params.dsc_pix_clk_100hz;</div><div class='add'>+</div><div class='add'>+	if (!pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;config.unify_link_enc_assignment)</div><div class='add'>+		link_enc = link_enc_cfg_get_link_enc(link);</div><div class='add'>+	if (link_enc)</div><div class='add'>+		pixel_clk_params-&gt;encoder_object_id = link_enc-&gt;id;</div><div class='add'>+</div><div class='add'>+	pixel_clk_params-&gt;signal_type = pipe_ctx-&gt;stream-&gt;signal;</div><div class='add'>+	pixel_clk_params-&gt;controller_id = pipe_ctx-&gt;stream_res.tg-&gt;inst + 1;</div><div class='add'>+	/* TODO: un-hardcode*/</div><div class='add'>+</div><div class='add'>+	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */</div><div class='add'>+</div><div class='add'>+	pixel_clk_params-&gt;requested_sym_clk = LINK_RATE_LOW *</div><div class='add'>+		LINK_RATE_REF_FREQ_IN_KHZ;</div><div class='add'>+	pixel_clk_params-&gt;flags.ENABLE_SS = 0;</div><div class='add'>+	pixel_clk_params-&gt;color_depth =</div><div class='add'>+		stream-&gt;timing.display_color_depth;</div><div class='add'>+	pixel_clk_params-&gt;flags.DISPLAY_BLANKED = 1;</div><div class='add'>+	pixel_clk_params-&gt;pixel_encoding = stream-&gt;timing.pixel_encoding;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)</div><div class='add'>+		pixel_clk_params-&gt;color_depth = COLOR_DEPTH_888;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)</div><div class='add'>+		pixel_clk_params-&gt;requested_pix_clk_100hz *= 2;</div><div class='add'>+	if (dc_is_tmds_signal(stream-&gt;signal) &amp;&amp;</div><div class='add'>+			stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)</div><div class='add'>+		pixel_clk_params-&gt;requested_pix_clk_100hz /= 2;</div><div class='add'>+</div><div class='add'>+	pipe_ctx-&gt;clock_source-&gt;funcs-&gt;get_pix_clk_dividers(</div><div class='add'>+			pipe_ctx-&gt;clock_source,</div><div class='add'>+			&amp;pipe_ctx-&gt;stream_res.pix_clk_params,</div><div class='add'>+			&amp;pipe_ctx-&gt;pll_settings);</div><div class='add'>+</div><div class='add'>+	pixel_clk_params-&gt;dio_se_pix_per_cycle = 1;</div><div class='add'>+	if (dc_is_tmds_signal(stream-&gt;signal) &amp;&amp;</div><div class='add'>+			stream-&gt;timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {</div><div class='add'>+		pixel_clk_params-&gt;dio_se_pix_per_cycle = 2;</div><div class='add'>+	} else if (dc_is_dp_signal(stream-&gt;signal)) {</div><div class='add'>+		/* round up to nearest power of 2, or max at 8 pixels per cycle */</div><div class='add'>+		if (pixel_clk_params-&gt;requested_pix_clk_100hz &gt; 4 * stream-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz * 10) {</div><div class='add'>+			pixel_clk_params-&gt;dio_se_pix_per_cycle = 8;</div><div class='add'>+		} else if (pixel_clk_params-&gt;requested_pix_clk_100hz &gt; 2 * stream-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz * 10) {</div><div class='add'>+			pixel_clk_params-&gt;dio_se_pix_per_cycle = 4;</div><div class='add'>+		} else if (pixel_clk_params-&gt;requested_pix_clk_100hz &gt; stream-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz * 10) {</div><div class='add'>+			pixel_clk_params-&gt;dio_se_pix_per_cycle = 2;</div><div class='add'>+		} else {</div><div class='add'>+			pixel_clk_params-&gt;dio_se_pix_per_cycle = 1;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcn401_get_power_profile(const struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	int uclk_mhz = context-&gt;bw_ctx.bw.dcn.clk.dramclk_khz / 1000;</div><div class='add'>+	int dpm_level = 0;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; context-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.num_entries_per_clk.num_memclk_levels; i++) {</div><div class='add'>+		if (context-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[i].memclk_mhz == 0 ||</div><div class='add'>+			uclk_mhz &lt; context-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[i].memclk_mhz)</div><div class='add'>+			break;</div><div class='add'>+		if (uclk_mhz &gt; context-&gt;clk_mgr-&gt;bw_params-&gt;clk_table.entries[i].memclk_mhz)</div><div class='add'>+			dpm_level++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dpm_level;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	return pipe_ctx-&gt;global_sync.dcn4x.vstartup_lines;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct resource_funcs dcn401_res_pool_funcs = {</div><div class='add'>+	.destroy = dcn401_destroy_resource_pool,</div><div class='add'>+	.link_enc_create = dcn401_link_encoder_create,</div><div class='add'>+	.link_enc_create_minimal = NULL,</div><div class='add'>+	.panel_cntl_create = dcn32_panel_cntl_create,</div><div class='add'>+	.validate_bandwidth = dcn401_validate_bandwidth,</div><div class='add'>+	.calculate_wm_and_dlg = NULL,</div><div class='add'>+	.populate_dml_pipes = NULL,</div><div class='add'>+	.acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,</div><div class='add'>+	.acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,</div><div class='add'>+	.release_pipe = dcn20_release_pipe,</div><div class='add'>+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,</div><div class='add'>+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,</div><div class='add'>+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,</div><div class='add'>+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,</div><div class='add'>+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,</div><div class='add'>+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,</div><div class='add'>+	.acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,</div><div class='add'>+	.release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,</div><div class='add'>+	.update_bw_bounding_box = dcn401_update_bw_bounding_box,</div><div class='add'>+	.patch_unknown_plane_state = dcn401_patch_unknown_plane_state,</div><div class='add'>+	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,</div><div class='add'>+	.add_phantom_pipes = dcn32_add_phantom_pipes,</div><div class='add'>+	.prepare_mcache_programming = dcn401_prepare_mcache_programming,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,</div><div class='add'>+	.calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,</div><div class='add'>+	.get_power_profile = dcn401_get_power_profile,</div><div class='add'>+	.get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,</div><div class='add'>+	.get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static uint32_t read_pipe_fuses(struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	uint32_t value = REG_READ(CC_DC_PIPE_DIS);</div><div class='add'>+	/* DCN401 support max 4 pipes */</div><div class='add'>+	value = value &amp; 0xf;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static bool dcn401_resource_construct(</div><div class='add'>+	uint8_t num_virtual_links,</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dcn401_resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+	struct dc_context *ctx = dc-&gt;ctx;</div><div class='add'>+	struct irq_service_init_data init_data;</div><div class='add'>+	struct ddc_service_init_data ddc_init_data = {0};</div><div class='add'>+	uint32_t pipe_fuses = 0;</div><div class='add'>+	uint32_t num_pipes  = 4;</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT bios_regs</div><div class='add'>+	bios_regs_init();</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT clk_src_regs</div><div class='add'>+	clk_src_regs_init(0, A),</div><div class='add'>+	clk_src_regs_init(1, B),</div><div class='add'>+	clk_src_regs_init(2, C),</div><div class='add'>+	clk_src_regs_init(3, D);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT abm_regs</div><div class='add'>+		abm_regs_init(0),</div><div class='add'>+		abm_regs_init(1),</div><div class='add'>+		abm_regs_init(2),</div><div class='add'>+		abm_regs_init(3);</div><div class='add'>+</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+#define REG_STRUCT dccg_regs</div><div class='add'>+	dccg_regs_init();</div><div class='add'>+</div><div class='add'>+	ctx-&gt;dc_bios-&gt;regs = &amp;bios_regs;</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.res_cap = &amp;res_cap_dcn4_01;</div><div class='add'>+</div><div class='add'>+	/* max number of pipes for ASIC before checking for pipe fuses */</div><div class='add'>+	num_pipes  = pool-&gt;base.res_cap-&gt;num_timing_generator;</div><div class='add'>+	pipe_fuses = read_pipe_fuses(ctx);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++)</div><div class='add'>+		if (pipe_fuses &amp; 1 &lt;&lt; i)</div><div class='add'>+			num_pipes--;</div><div class='add'>+</div><div class='add'>+	if (pipe_fuses &amp; 1)</div><div class='add'>+		ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!</div><div class='add'>+</div><div class='add'>+	if (pipe_fuses &amp; CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)</div><div class='add'>+		ASSERT(0); //Entire DCN is harvested!</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.funcs = &amp;dcn401_res_pool_funcs;</div><div class='add'>+</div><div class='add'>+	/*************************************************</div><div class='add'>+	 *  Resource + asic cap harcoding                *</div><div class='add'>+	 *************************************************/</div><div class='add'>+	pool-&gt;base.underlay_pipe_index = NO_UNDERLAY_PIPE;</div><div class='add'>+	pool-&gt;base.timing_generator_count = num_pipes;</div><div class='add'>+	pool-&gt;base.pipe_count = num_pipes;</div><div class='add'>+	pool-&gt;base.mpcc_count = num_pipes;</div><div class='add'>+	dc-&gt;caps.max_downscale_ratio = 600;</div><div class='add'>+	dc-&gt;caps.i2c_speed_in_khz = 95;</div><div class='add'>+	dc-&gt;caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/</div><div class='add'>+	/* used to set cursor pitch, so must be aligned to power of 2 (HW actually supported 78x78) */</div><div class='add'>+	dc-&gt;caps.max_cursor_size = 64;</div><div class='add'>+	dc-&gt;caps.max_buffered_cursor_size = 64;</div><div class='add'>+	dc-&gt;caps.cursor_not_scaled = true;</div><div class='add'>+	dc-&gt;caps.min_horizontal_blanking_period = 80;</div><div class='add'>+	dc-&gt;caps.dmdata_alloc_size = 2048;</div><div class='add'>+	dc-&gt;caps.mall_size_per_mem_channel = 4;</div><div class='add'>+	dc-&gt;caps.cursor_cache_size = dc-&gt;caps.max_cursor_size * dc-&gt;caps.max_cursor_size * 8;</div><div class='add'>+	dc-&gt;caps.cache_line_size = 64;</div><div class='add'>+	dc-&gt;caps.cache_num_ways = 16;</div><div class='add'>+</div><div class='add'>+	/* Calculate the available MALL space */</div><div class='add'>+	dc-&gt;caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(</div><div class='add'>+		dc, dc-&gt;ctx-&gt;dc_bios-&gt;vram_info.num_chans) *</div><div class='add'>+		dc-&gt;caps.mall_size_per_mem_channel * 1024 * 1024;</div><div class='add'>+	dc-&gt;caps.mall_size_total = dc-&gt;caps.max_cab_allocation_bytes;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.subvp_fw_processing_delay_us = 15;</div><div class='add'>+	dc-&gt;caps.subvp_drr_max_vblank_margin_us = 40;</div><div class='add'>+	dc-&gt;caps.subvp_prefetch_end_to_mall_start_us = 15;</div><div class='add'>+	dc-&gt;caps.subvp_swath_height_margin_lines = 16;</div><div class='add'>+	dc-&gt;caps.subvp_pstate_allow_width_us = 20;</div><div class='add'>+	dc-&gt;caps.subvp_vertical_int_margin_us = 30;</div><div class='add'>+	dc-&gt;caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.max_slave_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_yuv_planes = 3;</div><div class='add'>+	dc-&gt;caps.max_slave_rgb_planes = 3;</div><div class='add'>+	dc-&gt;caps.post_blend_color_processing = true;</div><div class='add'>+	dc-&gt;caps.force_dp_tps4_for_cp2520 = true;</div><div class='add'>+	dc-&gt;caps.dp_hpo = true;</div><div class='add'>+	dc-&gt;caps.dp_hdmi21_pcon_support = true;</div><div class='add'>+	dc-&gt;caps.edp_dsc_support = true;</div><div class='add'>+	dc-&gt;caps.extended_aux_timeout_support = true;</div><div class='add'>+	dc-&gt;caps.dmcub_support = true;</div><div class='add'>+	dc-&gt;caps.max_v_total = (1 &lt;&lt; 15) - 1;</div><div class='add'>+	dc-&gt;caps.vtotal_limited_by_fp2 = true;</div><div class='add'>+</div><div class='add'>+	if (ASICREV_IS_GC_12_0_1_A0(dc-&gt;ctx-&gt;asic_id.hw_internal_rev))</div><div class='add'>+		dc-&gt;caps.dcc_plane_width_limit = 7680;</div><div class='add'>+</div><div class='add'>+	/* Color pipeline capabilities */</div><div class='add'>+	dc-&gt;caps.color.dpp.dcn_arch = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.input_lut_shared = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.icsc = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_ram = 0; // must use gamma_corr</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.srgb = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.bt2020 = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.pq = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_caps.hlg = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.post_csc = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.gamma_corr = 1;</div><div class='add'>+	dc-&gt;caps.color.dpp.dgam_rom_for_yuv = 0;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.color.dpp.hw_3d_lut = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_ram = 0;</div><div class='add'>+	// no OGAM ROM on DCN2 and later ASICs</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.srgb = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.bt2020 = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.pq = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ogam_rom_caps.hlg = 0;</div><div class='add'>+	dc-&gt;caps.color.dpp.ocsc = 0;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.color.mpc.gamut_remap = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.num_3dluts = pool-&gt;base.res_cap-&gt;num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_ram = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.srgb = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.bt2020 = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.pq = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ogam_rom_caps.hlg = 0;</div><div class='add'>+	dc-&gt;caps.color.mpc.ocsc = 1;</div><div class='add'>+	dc-&gt;caps.color.mpc.preblend = true;</div><div class='add'>+	dc-&gt;config.use_spl = true;</div><div class='add'>+	dc-&gt;config.prefer_easf = true;</div><div class='add'>+</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.sdr_rgb_min = 0;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.sdr_rgb_max = 1750;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.sdr_rgb_mid = 750;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.sdr_yuv_min = 0;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.sdr_yuv_max = 3500;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.sdr_yuv_mid = 1500;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.hdr_rgb_min = 0;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.hdr_rgb_max = 2750;</div><div class='add'>+	dc-&gt;config.dcn_sharpness_range.hdr_rgb_mid = 1500;</div><div class='add'>+</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.sdr_rgb_min = 0;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.sdr_rgb_max = 3250;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.sdr_yuv_min = 0;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.sdr_yuv_max = 3500;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.hdr_rgb_min = 0;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.hdr_rgb_max = 2750;</div><div class='add'>+	dc-&gt;config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;</div><div class='add'>+</div><div class='add'>+	dc-&gt;config.dc_mode_clk_limit_support = true;</div><div class='add'>+	dc-&gt;config.enable_windowed_mpo_odm = true;</div><div class='add'>+	dc-&gt;config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */</div><div class='add'>+</div><div class='add'>+	/* read VBIOS LTTPR caps */</div><div class='add'>+	{</div><div class='add'>+		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='add'>+			enum bp_result bp_query_result;</div><div class='add'>+			uint8_t is_vbios_lttpr_enable = 0;</div><div class='add'>+</div><div class='add'>+			bp_query_result = ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps(ctx-&gt;dc_bios, &amp;is_vbios_lttpr_enable);</div><div class='add'>+			dc-&gt;caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) &amp;&amp; !!is_vbios_lttpr_enable;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* interop bit is implicit */</div><div class='add'>+		{</div><div class='add'>+			dc-&gt;caps.vbios_lttpr_aware = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	dc-&gt;check_config = config_defaults;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dce_environment == DCE_ENV_PRODUCTION_DRV)</div><div class='add'>+		dc-&gt;debug = debug_defaults_drv;</div><div class='add'>+</div><div class='add'>+	// Init the vm_helper</div><div class='add'>+	if (dc-&gt;vm_helper)</div><div class='add'>+		vm_helper_init(dc-&gt;vm_helper, 16);</div><div class='add'>+</div><div class='add'>+	/*************************************************</div><div class='add'>+	 *  Create resources                             *</div><div class='add'>+	 *************************************************/</div><div class='add'>+</div><div class='add'>+	/* Clock Sources for Pixel Clock*/</div><div class='add'>+	pool-&gt;base.clock_sources[DCN401_CLK_SRC_PLL0] =</div><div class='add'>+			dcn401_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL0,</div><div class='add'>+				&amp;clk_src_regs[0], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN401_CLK_SRC_PLL1] =</div><div class='add'>+			dcn401_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL1,</div><div class='add'>+				&amp;clk_src_regs[1], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN401_CLK_SRC_PLL2] =</div><div class='add'>+			dcn401_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL2,</div><div class='add'>+				&amp;clk_src_regs[2], false);</div><div class='add'>+	pool-&gt;base.clock_sources[DCN401_CLK_SRC_PLL3] =</div><div class='add'>+			dcn401_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_COMBO_PHY_PLL3,</div><div class='add'>+				&amp;clk_src_regs[3], false);</div><div class='add'>+	// pool-&gt;base.clock_sources[DCN401_CLK_SRC_PLL4] =</div><div class='add'>+	// 		dcn401_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+	// 			CLOCK_SOURCE_COMBO_PHY_PLL4,</div><div class='add'>+	// 			&amp;clk_src_regs[4], false);</div><div class='add'>+</div><div class='add'>+	pool-&gt;base.clk_src_count = DCN401_CLK_SRC_TOTAL;</div><div class='add'>+</div><div class='add'>+	/* todo: not reuse phy_pll registers */</div><div class='add'>+	pool-&gt;base.dp_clock_source =</div><div class='add'>+			dcn401_clock_source_create(ctx, ctx-&gt;dc_bios,</div><div class='add'>+				CLOCK_SOURCE_ID_DP_DTO,</div><div class='add'>+				&amp;clk_src_regs[0], true);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.clk_src_count; i++) {</div><div class='add'>+		if (pool-&gt;base.clock_sources[i] == NULL) {</div><div class='add'>+			dm_error("DC: failed to create clock sources!\n");</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DCCG */</div><div class='add'>+	pool-&gt;base.dccg = dccg401_create(ctx, &amp;dccg_regs, &amp;dccg_shift, &amp;dccg_mask);</div><div class='add'>+	if (pool-&gt;base.dccg == NULL) {</div><div class='add'>+		dm_error("DC: failed to create dccg!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* IRQ Service */</div><div class='add'>+	init_data.ctx = dc-&gt;ctx;</div><div class='add'>+	pool-&gt;base.irqs = dal_irq_service_dcn401_create(&amp;init_data);</div><div class='add'>+	if (!pool-&gt;base.irqs)</div><div class='add'>+		goto create_fail;</div><div class='add'>+</div><div class='add'>+	/* HUBBUB */</div><div class='add'>+	pool-&gt;base.hubbub = dcn401_hubbub_create(ctx);</div><div class='add'>+	if (pool-&gt;base.hubbub == NULL) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create hubbub!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* HUBPs, DPPs, OPPs, TGs, ABMs */</div><div class='add'>+	for (i = 0, j = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='add'>+</div><div class='add'>+		/* if pipe is disabled, skip instance of HW pipe,</div><div class='add'>+		 * i.e, skip ASIC register instance</div><div class='add'>+		 */</div><div class='add'>+		if (pipe_fuses &amp; 1 &lt;&lt; i)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		pool-&gt;base.hubps[j] = dcn401_hubp_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.hubps[j] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC: failed to create hubps!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pool-&gt;base.dpps[j] = dcn401_dpp_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.dpps[j] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC: failed to create dpps!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pool-&gt;base.opps[j] = dcn401_opp_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.opps[j] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC: failed to create output pixel processor!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pool-&gt;base.timing_generators[j] = dcn401_timing_generator_create(</div><div class='add'>+				ctx, i);</div><div class='add'>+		if (pool-&gt;base.timing_generators[j] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error("DC: failed to create tg!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pool-&gt;base.multiple_abms[j] = dmub_abm_create(ctx,</div><div class='add'>+				&amp;abm_regs[i],</div><div class='add'>+				&amp;abm_shift,</div><div class='add'>+				&amp;abm_mask);</div><div class='add'>+		if (pool-&gt;base.multiple_abms[j] == NULL) {</div><div class='add'>+			dm_error("DC: failed to create abm for pipe %d!\n", i);</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* index for resource pool arrays for next valid pipe */</div><div class='add'>+		j++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* PSR */</div><div class='add'>+	pool-&gt;base.psr = dmub_psr_create(ctx);</div><div class='add'>+	if (pool-&gt;base.psr == NULL) {</div><div class='add'>+		dm_error("DC: failed to create psr obj!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* MPCCs */</div><div class='add'>+	pool-&gt;base.mpc = dcn401_mpc_create(ctx,  pool-&gt;base.res_cap-&gt;num_timing_generator, pool-&gt;base.res_cap-&gt;num_mpc_3dlut);</div><div class='add'>+	if (pool-&gt;base.mpc == NULL) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create mpc!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DSCs */</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_dsc; i++) {</div><div class='add'>+		pool-&gt;base.dscs[i] = dcn401_dsc_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.dscs[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error("DC: failed to create display stream compressor %d!\n", i);</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* DWB */</div><div class='add'>+	if (!dcn401_dwbc_create(ctx, &amp;pool-&gt;base)) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create dwbc!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* MMHUBBUB */</div><div class='add'>+	if (!dcn401_mmhubbub_create(ctx, &amp;pool-&gt;base)) {</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		dm_error("DC: failed to create mcif_wb!\n");</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* AUX and I2C */</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_ddc; i++) {</div><div class='add'>+		pool-&gt;base.engines[i] = dcn401_aux_engine_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.engines[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC:failed to create aux engine!!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+		pool-&gt;base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);</div><div class='add'>+		if (pool-&gt;base.hw_i2cs[i] == NULL) {</div><div class='add'>+			BREAK_TO_DEBUGGER();</div><div class='add'>+			dm_error(</div><div class='add'>+				"DC:failed to create hw i2c!!\n");</div><div class='add'>+			goto create_fail;</div><div class='add'>+		}</div><div class='add'>+		pool-&gt;base.sw_i2cs[i] = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */</div><div class='add'>+	if (!resource_construct(num_virtual_links, dc, &amp;pool-&gt;base,</div><div class='add'>+			&amp;res_create_funcs))</div><div class='add'>+		goto create_fail;</div><div class='add'>+</div><div class='add'>+	/* HW Sequencer init functions and Plane caps */</div><div class='add'>+	dcn401_hw_sequencer_init_functions(dc);</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.max_planes =  pool-&gt;base.pipe_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;caps.max_planes; ++i)</div><div class='add'>+		dc-&gt;caps.planes[i] = plane_cap;</div><div class='add'>+</div><div class='add'>+	dc-&gt;caps.max_odm_combine_factor = 4;</div><div class='add'>+</div><div class='add'>+	dc-&gt;cap_funcs = cap_funcs;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_present) {</div><div class='add'>+		ddc_init_data.ctx = dc-&gt;ctx;</div><div class='add'>+		ddc_init_data.link = NULL;</div><div class='add'>+		ddc_init_data.id.id = dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.oem_i2c_obj_id;</div><div class='add'>+		ddc_init_data.id.enum_id = 0;</div><div class='add'>+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;</div><div class='add'>+		pool-&gt;base.oem_device = dc-&gt;link_srv-&gt;create_ddc_service(&amp;ddc_init_data);</div><div class='add'>+	} else {</div><div class='add'>+		pool-&gt;base.oem_device = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	//For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided</div><div class='add'>+	if (dc-&gt;config.sdpif_request_limit_words_per_umc == 0)</div><div class='add'>+		dc-&gt;config.sdpif_request_limit_words_per_umc = 16;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.dcn_pipe_count = pool-&gt;base.pipe_count;</div><div class='add'>+	dc-&gt;dml2_options.use_native_soc_bb_construction = true;</div><div class='add'>+	dc-&gt;dml2_options.minimize_dispclk_using_odm = true;</div><div class='add'>+	dc-&gt;dml2_options.map_dc_pipes_with_callbacks = true;</div><div class='add'>+	dc-&gt;dml2_options.force_tdlut_enable = true;</div><div class='add'>+</div><div class='add'>+	resource_init_common_dml2_callbacks(dc, &amp;dc-&gt;dml2_options);</div><div class='add'>+	dc-&gt;dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &amp;dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.release_dsc = &amp;dcn20_release_dsc;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool-&gt;base.funcs-&gt;calculate_mall_ways_from_bytes;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc-&gt;caps.subvp_fw_processing_delay_us;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc-&gt;caps.subvp_pstate_allow_width_us;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc-&gt;caps.subvp_swath_height_margin_lines;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.force_disable_subvp = dc-&gt;debug.force_disable_subvp;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.force_enable_subvp = dc-&gt;debug.force_subvp_mclk_switch;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.cache_line_size_bytes = dc-&gt;caps.cache_line_size;</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.cache_num_ways = dc-&gt;caps.cache_num_ways;</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.max_cab_allocation_bytes = dc-&gt;caps.max_cab_allocation_bytes;</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;</div><div class='add'>+	dc-&gt;dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.max_segments_per_hubp = 20;</div><div class='add'>+	dc-&gt;dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;</div><div class='add'>+</div><div class='add'>+	/* SPL */</div><div class='add'>+	dc-&gt;caps.scl_caps.sharpener_support = true;</div><div class='add'>+</div><div class='add'>+	/* init DC limited DML2 options */</div><div class='add'>+	memcpy(&amp;dc-&gt;dml2_dc_power_options, &amp;dc-&gt;dml2_options, sizeof(struct dml2_configuration_options));</div><div class='add'>+	dc-&gt;dml2_dc_power_options.use_clock_dc_limits = true;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+</div><div class='add'>+create_fail:</div><div class='add'>+</div><div class='add'>+	dcn401_resource_destruct(pool);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct resource_pool *dcn401_create_resource_pool(</div><div class='add'>+		const struct dc_init_data *init_data,</div><div class='add'>+		struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dcn401_resource_pool *pool =</div><div class='add'>+		kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!pool)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (dcn401_resource_construct(init_data-&gt;num_virtual_links, dc, pool))</div><div class='add'>+		return &amp;pool-&gt;base;</div><div class='add'>+</div><div class='add'>+	BREAK_TO_DEBUGGER();</div><div class='add'>+	kfree(pool);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h<br/>new file mode 100644<br/>index 000000000000..e1fa2e80a15a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h</a></div><div class='hunk'>@@ -0,0 +1,656 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef _DCN401_RESOURCE_H_</div><div class='add'>+#define _DCN401_RESOURCE_H_</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dcn32/dcn32_resource.h"</div><div class='add'>+#include "dcn401/dcn401_hubp.h"</div><div class='add'>+</div><div class='add'>+#define TO_DCN401_RES_POOL(pool)\</div><div class='add'>+	container_of(pool, struct dcn401_resource_pool, base)</div><div class='add'>+</div><div class='add'>+struct dcn401_resource_pool {</div><div class='add'>+	struct resource_pool base;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct resource_pool *dcn401_create_resource_pool(</div><div class='add'>+		const struct dc_init_data *init_data,</div><div class='add'>+		struct dc *dc);</div><div class='add'>+</div><div class='add'>+enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state);</div><div class='add'>+</div><div class='add'>+enum dc_status dcn401_validate_bandwidth(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		enum dc_validate_mode validate_mode);</div><div class='add'>+</div><div class='add'>+void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);</div><div class='add'>+</div><div class='add'>+/* Following are definitions for run time init of reg offsets */</div><div class='add'>+</div><div class='add'>+/* HUBP */</div><div class='add'>+#define HUBP_REG_LIST_DCN401_RI(id)                                             \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),                             \</div><div class='add'>+	SRI_ARR(DCHUBP_CNTL, HUBP, id),                                          \</div><div class='add'>+	SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id),                                     \</div><div class='add'>+	SRI_ARR(HUBPREQ_DEBUG, HUBP, id),                                        \</div><div class='add'>+	SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id),                                   \</div><div class='add'>+	SRI_ARR(DCSURF_TILING_CONFIG, HUBP, id),                                 \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_PITCH, HUBPREQ, id),                              \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),                            \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_CONFIG, HUBP, id),                                \</div><div class='add'>+	SRI_ARR(DCSURF_FLIP_CONTROL, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id),                        \</div><div class='add'>+	SRI_ARR(DCSURF_PRI_VIEWPORT_START, HUBP, id),                            \</div><div class='add'>+	SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id),                        \</div><div class='add'>+	SRI_ARR(DCSURF_SEC_VIEWPORT_START, HUBP, id),                            \</div><div class='add'>+	SRI_ARR(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id),                      \</div><div class='add'>+	SRI_ARR(DCSURF_PRI_VIEWPORT_START_C, HUBP, id),                          \</div><div class='add'>+	SRI_ARR(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id),                      \</div><div class='add'>+	SRI_ARR(DCSURF_SEC_VIEWPORT_START_C, HUBP, id),                          \</div><div class='add'>+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),               \</div><div class='add'>+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),                    \</div><div class='add'>+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),             \</div><div class='add'>+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),                  \</div><div class='add'>+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),             \</div><div class='add'>+	SRI_ARR(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),                  \</div><div class='add'>+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),           \</div><div class='add'>+	SRI_ARR(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),                \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_INUSE, HUBPREQ, id),                              \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),                         \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),                            \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),                       \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),                     \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),                \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),                   \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),              \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_CONTROL, HUBPREQ, id),                            \</div><div class='add'>+	SRI_ARR(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),                     \</div><div class='add'>+	SRI_ARR(HUBPRET_CONTROL, HUBPRET, id),                                   \</div><div class='add'>+	SRI_ARR(HUBPRET_READ_LINE_STATUS, HUBPRET, id),                          \</div><div class='add'>+	SRI_ARR(DCN_EXPANSION_MODE, HUBPREQ, id),                                \</div><div class='add'>+	SRI_ARR(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),                               \</div><div class='add'>+	SRI_ARR(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),                             \</div><div class='add'>+	SRI_ARR(BLANK_OFFSET_0, HUBPREQ, id),                                    \</div><div class='add'>+	SRI_ARR(BLANK_OFFSET_1, HUBPREQ, id),                                    \</div><div class='add'>+	SRI_ARR(DST_DIMENSIONS, HUBPREQ, id),                                    \</div><div class='add'>+	SRI_ARR(DST_AFTER_SCALER, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_0, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),                              \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_1, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_3, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_4, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_5, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(PER_LINE_DELIVERY_PRE, HUBPREQ, id),                             \</div><div class='add'>+	SRI_ARR(PER_LINE_DELIVERY, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_2, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_4, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_6, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(NOM_PARAMETERS_7, HUBPREQ, id),                                  \</div><div class='add'>+	SRI_ARR(DCN_TTU_QOS_WM, HUBPREQ, id),                                    \</div><div class='add'>+	SRI_ARR(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),                                \</div><div class='add'>+	SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),                                \</div><div class='add'>+	SRI_ARR(HUBP_CLK_CNTL, HUBP, id),                                        \</div><div class='add'>+	SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(PREFETCH_SETTINGS_C, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),                   \</div><div class='add'>+	SRI_ARR(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),                  \</div><div class='add'>+	SRI_ARR(CURSOR_SETTINGS, HUBPREQ, id),                                   \</div><div class='add'>+	SRI_ARR(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id),                      \</div><div class='add'>+	SRI_ARR(CURSOR_SURFACE_ADDRESS, CURSOR0_, id),                           \</div><div class='add'>+	SRI_ARR(CURSOR_SIZE, CURSOR0_, id),                                      \</div><div class='add'>+	SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \</div><div class='add'>+	SRI_ARR(CURSOR_POSITION, CURSOR0_, id),                                  \</div><div class='add'>+	SRI_ARR(CURSOR_HOT_SPOT, CURSOR0_, id),                                  \</div><div class='add'>+	SRI_ARR(CURSOR_DST_OFFSET, CURSOR0_, id),                                \</div><div class='add'>+	SRI_ARR(DMDATA_ADDRESS_HIGH, CURSOR0_, id),                              \</div><div class='add'>+	SRI_ARR(DMDATA_ADDRESS_LOW, CURSOR0_, id),                               \</div><div class='add'>+	SRI_ARR(DMDATA_CNTL, CURSOR0_, id),                                      \</div><div class='add'>+	SRI_ARR(DMDATA_SW_CNTL, CURSOR0_, id),                                   \</div><div class='add'>+	SRI_ARR(DMDATA_QOS_CNTL, CURSOR0_, id),                                  \</div><div class='add'>+	SRI_ARR(DMDATA_SW_DATA, CURSOR0_, id),                                   \</div><div class='add'>+	SRI_ARR(DMDATA_STATUS, CURSOR0_, id),                                    \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_0, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_1, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_2, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),                                \</div><div class='add'>+	SRI_ARR(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),                                \</div><div class='add'>+	SRI_ARR(DCSURF_FLIP_CONTROL2, HUBPREQ, id),                              \</div><div class='add'>+	SRI_ARR(VMID_SETTINGS_0, HUBPREQ, id),                                   \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_3, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_4, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_5, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(FLIP_PARAMETERS_6, HUBPREQ, id),                                 \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_5, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(VBLANK_PARAMETERS_6, HUBPREQ, id),                               \</div><div class='add'>+	SRI_ARR(DCN_DMDATA_VM_CNTL, HUBPREQ, id),                                \</div><div class='add'>+	SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id),                                   \</div><div class='add'>+	SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id),                                   \</div><div class='add'>+	SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id),                                 \</div><div class='add'>+	HUBP_3DLUT_FL_REG_LIST_DCN401(id),                                       \</div><div class='add'>+	SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id),              \</div><div class='add'>+	SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id),								 \</div><div class='add'>+	SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id)</div><div class='add'>+</div><div class='add'>+/* ABM */</div><div class='add'>+#define ABM_DCN401_REG_LIST_RI(id)                                            \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id),                                \</div><div class='add'>+	SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id),                                \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id),                                  \</div><div class='add'>+	SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id),                               \</div><div class='add'>+	SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id),                         \</div><div class='add'>+	SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id),                             \</div><div class='add'>+	SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id),                              \</div><div class='add'>+	SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id),                                    \</div><div class='add'>+	SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id),                  \</div><div class='add'>+	SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id),                        \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id),                      \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id),                       \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id),                      \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id),                      \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id),                      \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id),                                \</div><div class='add'>+	SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id),                               \</div><div class='add'>+	SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id),                         \</div><div class='add'>+	SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id),                                  \</div><div class='add'>+	SRI_ARR(DC_ABM1_ACE_THRES_DATA, ABM, id),                                \</div><div class='add'>+	NBIO_SR_ARR(BIOS_SCRATCH_2, id)</div><div class='add'>+</div><div class='add'>+/* VPG */</div><div class='add'>+#define VPG_DCN401_REG_LIST_RI(id)                                             \</div><div class='add'>+	VPG_DCN3_REG_LIST_RI(id),                                                  \</div><div class='add'>+	SRI_ARR(VPG_MEM_PWR, VPG, id)</div><div class='add'>+</div><div class='add'>+/* Stream encoder */</div><div class='add'>+#define SE_DCN4_01_REG_LIST_RI(id)                                               \</div><div class='add'>+	SRI_ARR(AFMT_CNTL, DIG, id), SRI_ARR(DIG_FE_CNTL, DIG, id),                  \</div><div class='add'>+	SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id),       \</div><div class='add'>+	SRI_ARR(HDMI_GC, DIG, id),                                               \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id),                          \</div><div class='add'>+	SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id),                         \</div><div class='add'>+	SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id),                               \</div><div class='add'>+	SRI_ARR(HDMI_INFOFRAME_CONTROL1, DIG, id),                               \</div><div class='add'>+	SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id),                               \</div><div class='add'>+	SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id),                             \</div><div class='add'>+	SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id),                               \</div><div class='add'>+	SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id),        \</div><div class='add'>+	SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id),        \</div><div class='add'>+	SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id),        \</div><div class='add'>+	SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id),               \</div><div class='add'>+	SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id),  \</div><div class='add'>+	SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id),                                   \</div><div class='add'>+	SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id),                                   \</div><div class='add'>+	SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id),                                   \</div><div class='add'>+	SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id),                                   \</div><div class='add'>+	SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id),  \</div><div class='add'>+	SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id),          \</div><div class='add'>+	SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id),            \</div><div class='add'>+	SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id),            \</div><div class='add'>+	SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id),               \</div><div class='add'>+	SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id),          \</div><div class='add'>+	SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id),           \</div><div class='add'>+	SRI_ARR(DP_SEC_TIMESTAMP, DP, id),                                       \</div><div class='add'>+	SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                           \</div><div class='add'>+	SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                          \</div><div class='add'>+	SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id),        \</div><div class='add'>+	SRI_ARR(DME_CONTROL, DME, id),                                           \</div><div class='add'>+	SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id),                           \</div><div class='add'>+	SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id),                          \</div><div class='add'>+	SRI_ARR(DIG_FE_CNTL, DIG, id),                                           \</div><div class='add'>+	SRI_ARR(DIG_FE_EN_CNTL, DIG, id),                                        \</div><div class='add'>+	SRI_ARR(DIG_FE_CLK_CNTL, DIG, id),                                       \</div><div class='add'>+	SRI_ARR(DIG_CLOCK_PATTERN, DIG, id),                                     \</div><div class='add'>+	SRI_ARR(DIG_FIFO_CTRL0, DIG, id),                                        \</div><div class='add'>+	SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)</div><div class='add'>+</div><div class='add'>+/* Link encoder */</div><div class='add'>+#define LE_DCN401_REG_LIST_RI(id)                                            \</div><div class='add'>+	LE_DCN3_REG_LIST_RI(id), \</div><div class='add'>+	SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \</div><div class='add'>+	SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\</div><div class='add'>+	SR_ARR(DIO_CLK_CNTL, id)</div><div class='add'>+</div><div class='add'>+/* DPP */</div><div class='add'>+#define DPP_REG_LIST_DCN401_COMMON_RI(id)                                    \</div><div class='add'>+	SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id),         \</div><div class='add'>+	SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id),        \</div><div class='add'>+	SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id),    \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id),                                  \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                    \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id),                                    \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id),                                     \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),                      \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),                      \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),                      \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id),                              \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id),                                \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id),                                \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id),                                \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),                       \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),                       \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),                       \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),                      \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),                      \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),                      \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),                             \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id),                              \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id),                            \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id),                                \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id),                                \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id),                                \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),                       \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),                       \</div><div class='add'>+	SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),                       \</div><div class='add'>+	SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id),                         \</div><div class='add'>+	SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id),                         \</div><div class='add'>+	SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id),          \</div><div class='add'>+	SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id),          \</div><div class='add'>+	SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id),      \</div><div class='add'>+	SRI_ARR(SCL_TAP_CONTROL, DSCL, id),                                      \</div><div class='add'>+	SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id),                              \</div><div class='add'>+	SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id),                                \</div><div class='add'>+	SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id),       \</div><div class='add'>+	SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id),                          \</div><div class='add'>+	SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id),                          \</div><div class='add'>+	SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id),                        \</div><div class='add'>+	SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id),                        \</div><div class='add'>+	SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id),                                 \</div><div class='add'>+	SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id),                               \</div><div class='add'>+	SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id),                                 \</div><div class='add'>+	SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id),                               \</div><div class='add'>+	SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id),         \</div><div class='add'>+	SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id),  \</div><div class='add'>+	SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id),                                     \</div><div class='add'>+	SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id),                                  \</div><div class='add'>+	SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id),                                  \</div><div class='add'>+	SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id),                                \</div><div class='add'>+	SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id),                                \</div><div class='add'>+	SRI_ARR(CM_POST_CSC_CONTROL, CM, id),                                    \</div><div class='add'>+	SRI_ARR(CM_POST_CSC_C11_C12, CM, id),                                    \</div><div class='add'>+	SRI_ARR(CM_POST_CSC_C33_C34, CM, id),                                    \</div><div class='add'>+	SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id),                                  \</div><div class='add'>+	SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id),                                  \</div><div class='add'>+	SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id),           \</div><div class='add'>+	SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id),                                    \</div><div class='add'>+	SRI_ARR(CM_TEST_DEBUG_DATA, CM, id),                                     \</div><div class='add'>+	SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id),                                   \</div><div class='add'>+	SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id),                        \</div><div class='add'>+	SRI_ARR(CURSOR0_CONTROL, CM_CUR, id),                                    \</div><div class='add'>+	SRI_ARR(CURSOR0_COLOR0, CM_CUR, id),                                     \</div><div class='add'>+	SRI_ARR(CURSOR0_COLOR1, CM_CUR, id),                                     \</div><div class='add'>+	SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id),                          \</div><div class='add'>+	SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id),                      \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id),                                   \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id),                              \</div><div class='add'>+	SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id),    \</div><div class='add'>+	SRI_ARR(CURSOR_CONTROL, CURSOR0_, id),                                   \</div><div class='add'>+	SRI_ARR(ALPHA_2BIT_LUT, CNVC_CFG, id),                                   \</div><div class='add'>+	SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id),                                   \</div><div class='add'>+	SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id),                                   \</div><div class='add'>+	SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id),                                   \</div><div class='add'>+	SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id),                                  \</div><div class='add'>+	SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id),                                  \</div><div class='add'>+	SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id),                                  \</div><div class='add'>+	SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id),                              \</div><div class='add'>+	SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id),                                \</div><div class='add'>+	SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id),                                  \</div><div class='add'>+	SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id),                                \</div><div class='add'>+	SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id),                                 \</div><div class='add'>+	SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id),                                    \</div><div class='add'>+	SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id),                                    \</div><div class='add'>+	SRI_ARR(DSCL_CONTROL, DSCL, id),                                         \</div><div class='add'>+	SRI_ARR(DSCL_SC_MODE, DSCL, id),                                         \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_MODE, DSCL, id),                                     \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id),                   \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id),                     \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id),                         \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_MODE, DSCL, id),                                     \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id),                       \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id),                       \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id),                       \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id),                   \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id),                     \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id),                         \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_MODE, DSCL, id),                                          \</div><div class='add'>+	SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id),                            \</div><div class='add'>+	SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id),                                \</div><div class='add'>+	SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id),                                  \</div><div class='add'>+	SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id),                                    \</div><div class='add'>+	SRI_ARR(ISHARP_DELTA_DATA, DSCL, id),                                    \</div><div class='add'>+	SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id),                                   \</div><div class='add'>+	SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id),                             \</div><div class='add'>+	SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id)</div><div class='add'>+</div><div class='add'>+/* OPP */</div><div class='add'>+#define OPP_REG_LIST_DCN401_RI(id)                                              \</div><div class='add'>+  OPP_REG_LIST_DCN10_RI(id), OPP_DPG_REG_LIST_RI(id),                          \</div><div class='add'>+      SRI_ARR(FMT_422_CONTROL, FMT, id)</div><div class='add'>+</div><div class='add'>+/* DSC */</div><div class='add'>+#define DSC_REG_LIST_DCN401_RI(id)                                          \</div><div class='add'>+	SRI_ARR(DSC_TOP_CONTROL, DSC_TOP, id),                                   \</div><div class='add'>+	SRI_ARR(DSC_DEBUG_CONTROL, DSC_TOP, id),                                 \</div><div class='add'>+	SRI_ARR(DSCC_CONFIG0, DSCC, id), SRI_ARR(DSCC_CONFIG1, DSCC, id),        \</div><div class='add'>+	SRI_ARR(DSCC_STATUS, DSCC, id),                                          \</div><div class='add'>+	SRI_ARR(DSCC_INTERRUPT_CONTROL0, DSCC, id),                              \</div><div class='add'>+	SRI_ARR(DSCC_INTERRUPT_CONTROL1, DSCC, id),                              \</div><div class='add'>+	SRI_ARR(DSCC_INTERRUPT_STATUS0, DSCC, id),                               \</div><div class='add'>+	SRI_ARR(DSCC_INTERRUPT_STATUS1, DSCC, id),                               \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG0, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG1, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG2, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG3, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG4, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG5, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG6, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG7, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG8, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG9, DSCC, id),                                     \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG10, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG11, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG12, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG13, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG14, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG15, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG16, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG17, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG18, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG19, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG20, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG21, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_PPS_CONFIG22, DSCC, id),                                    \</div><div class='add'>+	SRI_ARR(DSCC_MEM_POWER_CONTROL0, DSCC, id),                              \</div><div class='add'>+	SRI_ARR(DSCC_MEM_POWER_CONTROL1, DSCC, id),                              \</div><div class='add'>+	SRI_ARR(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),                         \</div><div class='add'>+	SRI_ARR(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),                         \</div><div class='add'>+	SRI_ARR(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),                        \</div><div class='add'>+	SRI_ARR(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),                        \</div><div class='add'>+	SRI_ARR(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),                        \</div><div class='add'>+	SRI_ARR(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),                        \</div><div class='add'>+	SRI_ARR(DSCC_MAX_ABS_ERROR0, DSCC, id),                                  \</div><div class='add'>+	SRI_ARR(DSCC_MAX_ABS_ERROR1, DSCC, id),                                  \</div><div class='add'>+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC, id),           \</div><div class='add'>+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC, id),           \</div><div class='add'>+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC, id),           \</div><div class='add'>+	SRI_ARR(DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC, id),           \</div><div class='add'>+	SRI_ARR(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),                           \</div><div class='add'>+	SRI_ARR(DSCCIF_CONFIG0, DSCCIF, id),                                     \</div><div class='add'>+	SRI_ARR(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)</div><div class='add'>+</div><div class='add'>+/* MPC */</div><div class='add'>+#define MPC_DWB_MUX_REG_LIST_DCN4_01_RI(inst)                                  \</div><div class='add'>+	MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst)</div><div class='add'>+</div><div class='add'>+#define MPC_OUT_MUX_COMMON_REG_LIST_DCN4_01_RI(inst)                           \</div><div class='add'>+	MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst)</div><div class='add'>+</div><div class='add'>+#define MPC_OUT_MUX_REG_LIST_DCN4_01_RI(inst)                                   \</div><div class='add'>+	MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst)</div><div class='add'>+</div><div class='add'>+/* OPTC */</div><div class='add'>+#define OPTC_COMMON_REG_LIST_DCN401_RI(inst)                                   \</div><div class='add'>+	SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst),                                      \</div><div class='add'>+	SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst),                                   \</div><div class='add'>+	SRI_ARR(OTG_VREADY_PARAM, OTG, inst),                                    \</div><div class='add'>+	SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst),                              \</div><div class='add'>+	SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),                           \</div><div class='add'>+	SRI_ARR(OTG_H_TOTAL, OTG, inst),                                         \</div><div class='add'>+	SRI_ARR(OTG_H_BLANK_START_END, OTG, inst),                               \</div><div class='add'>+	SRI_ARR(OTG_H_SYNC_A, OTG, inst), SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \</div><div class='add'>+	SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst),  \</div><div class='add'>+	SRI_ARR(OTG_V_BLANK_START_END, OTG, inst),                               \</div><div class='add'>+	SRI_ARR(OTG_V_SYNC_A, OTG, inst), SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \</div><div class='add'>+	SRI_ARR(OTG_CONTROL, OTG, inst), SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \</div><div class='add'>+	SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst),                            \</div><div class='add'>+	SRI_ARR(OTG_STEREO_STATUS, OTG, inst),                                   \</div><div class='add'>+	SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst),                                     \</div><div class='add'>+	SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst),                                     \</div><div class='add'>+	SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_TRIGA_CNTL, OTG, inst),                                      \</div><div class='add'>+	SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),                            \</div><div class='add'>+	SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst),                           \</div><div class='add'>+	SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst),                              \</div><div class='add'>+	SRI_ARR(OTG_STATUS, OTG, inst), SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \</div><div class='add'>+	SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst),                               \</div><div class='add'>+	SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),                                    \</div><div class='add'>+	SRI_ARR(OTG_M_CONST_DTO1, OTG, inst),                                    \</div><div class='add'>+	SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst),                                   \</div><div class='add'>+	SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),                     \</div><div class='add'>+	SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),                    \</div><div class='add'>+	SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),                     \</div><div class='add'>+	SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),                    \</div><div class='add'>+	SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),                     \</div><div class='add'>+	SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),                    \</div><div class='add'>+	SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),                            \</div><div class='add'>+	SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst),                             \</div><div class='add'>+	SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),                           \</div><div class='add'>+	SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),  \</div><div class='add'>+	SRI_ARR(OTG_GSL_CONTROL, OTG, inst), SRI_ARR(OTG_CRC_CNTL, OTG, inst),   \</div><div class='add'>+	SRI_ARR(OTG_CRC0_DATA_RG, OTG, inst),                                    \</div><div class='add'>+	SRI_ARR(OTG_CRC0_DATA_B, OTG, inst),                                     \</div><div class='add'>+	SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),                          \</div><div class='add'>+	SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),                          \</div><div class='add'>+	SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),                          \</div><div class='add'>+	SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),                          \</div><div class='add'>+	SR_ARR(GSL_SOURCE_SELECT, inst),                                         \</div><div class='add'>+	SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst),                               \</div><div class='add'>+	SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst),                                    \</div><div class='add'>+	SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst),                                    \</div><div class='add'>+	SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst),                              \</div><div class='add'>+	SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),                              \</div><div class='add'>+	SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst),                            \</div><div class='add'>+	SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst),                                \</div><div class='add'>+	SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst),                                  \</div><div class='add'>+	SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst),                                 \</div><div class='add'>+	SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst),                                  \</div><div class='add'>+	SRI_ARR(OTG_DRR_CONTROL, OTG, inst),                                     \</div><div class='add'>+	SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst),                                 \</div><div class='add'>+	SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),                              \</div><div class='add'>+	SRI_ARR(INTERRUPT_DEST, OTG, inst)</div><div class='add'>+</div><div class='add'>+/* HUBBUB */</div><div class='add'>+#define HUBBUB_REG_LIST_DCN4_01_RI(id)                                       \</div><div class='add'>+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),                               \</div><div class='add'>+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),                               \</div><div class='add'>+	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),                                  \</div><div class='add'>+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),                                        \</div><div class='add'>+	SR(DCHUBBUB_ARB_SAT_LEVEL),                                              \</div><div class='add'>+	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),                                        \</div><div class='add'>+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL),                                          \</div><div class='add'>+	SR(DCHUBBUB_TEST_DEBUG_INDEX),                                           \</div><div class='add'>+	SR(DCHUBBUB_TEST_DEBUG_DATA),                                            \</div><div class='add'>+	SR(DCHUBBUB_SOFT_RESET),                                                 \</div><div class='add'>+	SR(DCHUBBUB_CRC_CTRL),                                                   \</div><div class='add'>+	SR(DCN_VM_FB_LOCATION_BASE),                                             \</div><div class='add'>+	SR(DCN_VM_FB_LOCATION_TOP),                                              \</div><div class='add'>+	SR(DCN_VM_FB_OFFSET),                                                    \</div><div class='add'>+	SR(DCN_VM_AGP_BOT),                                                      \</div><div class='add'>+	SR(DCN_VM_AGP_TOP),                                                      \</div><div class='add'>+	SR(DCN_VM_AGP_BASE),                                                     \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),                              \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),                              \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),                                      \</div><div class='add'>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),                                      \</div><div class='add'>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),                                     \</div><div class='add'>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),                                     \</div><div class='add'>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A),                                     \</div><div class='add'>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B),                                     \</div><div class='add'>+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),                            \</div><div class='add'>+	SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A),                                 \</div><div class='add'>+	SR(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B),                                 \</div><div class='add'>+	SR(DCHUBBUB_DET0_CTRL),                                                  \</div><div class='add'>+	SR(DCHUBBUB_DET1_CTRL),                                                  \</div><div class='add'>+	SR(DCHUBBUB_DET2_CTRL),                                                  \</div><div class='add'>+	SR(DCHUBBUB_DET3_CTRL),                                                  \</div><div class='add'>+	SR(DCHUBBUB_COMPBUF_CTRL),                                               \</div><div class='add'>+	SR(COMPBUF_RESERVED_SPACE),                                              \</div><div class='add'>+	SR(DCHUBBUB_DEBUG_CTRL_0),                                               \</div><div class='add'>+	SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),                                    \</div><div class='add'>+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),                             \</div><div class='add'>+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),                         \</div><div class='add'>+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),                         \</div><div class='add'>+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A),                        \</div><div class='add'>+	SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B),                        \</div><div class='add'>+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),                         \</div><div class='add'>+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),                         \</div><div class='add'>+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A),                        \</div><div class='add'>+	SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B),                        \</div><div class='add'>+	SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB),                    \</div><div class='add'>+	SR(DCN_VM_FAULT_CNTL),                                                   \</div><div class='add'>+	SR(DCN_VM_FAULT_STATUS),                                                 \</div><div class='add'>+	SR(SDPIF_REQUEST_RATE_LIMIT),                                            \</div><div class='add'>+	SR(DCHUBBUB_CLOCK_CNTL),                                                 \</div><div class='add'>+	SR(DCHUBBUB_SDPIF_CFG0),                                                 \</div><div class='add'>+	SR(DCHUBBUB_SDPIF_CFG1),                                                 \</div><div class='add'>+	SR(DCHUBBUB_MEM_PWR_MODE_CTRL),                                          \</div><div class='add'>+	SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1),                                    \</div><div class='add'>+	SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2),									 \</div><div class='add'>+	SR(DCHUBBUB_CTRL_STATUS)</div><div class='add'>+</div><div class='add'>+/* DCCG */</div><div class='add'>+</div><div class='add'>+#define DCCG_REG_LIST_DCN401_RI()                                            \</div><div class='add'>+	SR(DPPCLK_DTO_CTRL), DCCG_SRII(DTO_PARAM, DPPCLK, 0),                        \</div><div class='add'>+	DCCG_SRII(DTO_PARAM, DPPCLK, 1), DCCG_SRII(DTO_PARAM, DPPCLK, 2),        \</div><div class='add'>+	DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),  \</div><div class='add'>+	SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL),                    \</div><div class='add'>+	SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL),                    \</div><div class='add'>+	SR(DPSTREAMCLK_CNTL), SR(HDMISTREAMCLK_CNTL),                            \</div><div class='add'>+	SR(SYMCLK32_SE_CNTL), SR(SYMCLK32_LE_CNTL),                              \</div><div class='add'>+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),  \</div><div class='add'>+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),  \</div><div class='add'>+	SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL),                               \</div><div class='add'>+	SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL),                     \</div><div class='add'>+	SR(DPPCLK_CTRL),							                             \</div><div class='add'>+	DCCG_SRII(MODULO, DP_DTO, 0), DCCG_SRII(MODULO, DP_DTO, 1),      \</div><div class='add'>+	DCCG_SRII(MODULO, DP_DTO, 2), DCCG_SRII(MODULO, DP_DTO, 3),      \</div><div class='add'>+	DCCG_SRII(PHASE, DP_DTO, 0), DCCG_SRII(PHASE, DP_DTO, 1),        \</div><div class='add'>+	DCCG_SRII(PHASE, DP_DTO, 2), DCCG_SRII(PHASE, DP_DTO, 3),        \</div><div class='add'>+	SR(DSCCLK0_DTO_PARAM),\</div><div class='add'>+	SR(DSCCLK1_DTO_PARAM),\</div><div class='add'>+	SR(DSCCLK2_DTO_PARAM),\</div><div class='add'>+	SR(DSCCLK3_DTO_PARAM),\</div><div class='add'>+	SR(DSCCLK_DTO_CTRL),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL2),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL3),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL4),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL5),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL6),\</div><div class='add'>+	SR(SYMCLKA_CLOCK_ENABLE),\</div><div class='add'>+	SR(SYMCLKB_CLOCK_ENABLE),\</div><div class='add'>+	SR(SYMCLKC_CLOCK_ENABLE),\</div><div class='add'>+	SR(SYMCLKD_CLOCK_ENABLE)</div><div class='add'>+</div><div class='add'>+#endif /* _DCN401_RESOURCE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile<br/>new file mode 100644<br/>index 000000000000..bc93356a0b5b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+# SPDX-License-Identifier: MIT</div><div class='add'>+#</div><div class='add'>+# Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+# Makefile for bounding box component.</div><div class='add'>+# Floating point required due to nature of bounding box values</div><div class='add'>+</div><div class='add'>+soc_and_ip_translator_ccflags := $(CC_FLAGS_FPU)</div><div class='add'>+soc_and_ip_translator_rcflags := $(CC_FLAGS_NO_FPU)</div><div class='add'>+</div><div class='add'>+CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags)</div><div class='add'>+</div><div class='add'>+CFLAGS_REMOVE_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_rcflags)</div><div class='add'>+</div><div class='add'>+soc_and_ip_translator := soc_and_ip_translator.o</div><div class='add'>+soc_and_ip_translator += dcn401/dcn401_soc_and_ip_translator.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_soc_and_ip_translator := $(addprefix $(AMDDALPATH)/dc/soc_and_ip_translator/, $(soc_and_ip_translator))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_soc_and_ip_translator)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c<br/>new file mode 100644<br/>index 000000000000..3190c76eb482<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c</a></div><div class='hunk'>@@ -0,0 +1,304 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dcn401_soc_and_ip_translator.h"</div><div class='add'>+#include "bounding_boxes/dcn4_soc_bb.h"</div><div class='add'>+</div><div class='add'>+/* soc_and_ip_translator component used to get up-to-date values for bounding box.</div><div class='add'>+ * Bounding box values are stored in several locations and locations can vary with DCN revision.</div><div class='add'>+ * This component provides an interface to get DCN-specific bounding box values.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static void get_default_soc_bb(struct dml2_soc_bb *soc_bb)</div><div class='add'>+{</div><div class='add'>+	memcpy(soc_bb, &amp;dml2_socbb_dcn401, sizeof(struct dml2_soc_bb));</div><div class='add'>+	memcpy(&amp;soc_bb-&gt;qos_parameters, &amp;dml_dcn4_variant_a_soc_qos_params, sizeof(struct dml2_soc_qos_parameters));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * DC clock table is obtained from SMU during runtime.</div><div class='add'>+ * SMU stands for System Management Unit. It is a power management processor.</div><div class='add'>+ * It owns the initialization of dc's clock table and programming of clock values</div><div class='add'>+ * based on dc's requests.</div><div class='add'>+ * Our clock values in base soc bb is a dummy placeholder. The real clock values</div><div class='add'>+ * are retrieved from SMU firmware to dc clock table at runtime.</div><div class='add'>+ * This function overrides our dummy placeholder values with real values in dc</div><div class='add'>+ * clock table.</div><div class='add'>+ */</div><div class='add'>+static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(</div><div class='add'>+		struct dml2_soc_state_table *dml_clk_table,</div><div class='add'>+		const struct clk_bw_params *dc_bw_params,</div><div class='add'>+		bool use_clock_dc_limits)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	const struct clk_limit_table *dc_clk_table;</div><div class='add'>+</div><div class='add'>+	if (dc_bw_params == NULL)</div><div class='add'>+		/* skip if bw params could not be obtained from smu */</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dc_clk_table = &amp;dc_bw_params-&gt;clk_table;</div><div class='add'>+</div><div class='add'>+	/* dcfclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_dcfclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;dcfclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_dcfclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;dcfclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.dcfclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].dcfclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.dcfclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].dcfclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.dcfclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;dcfclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.dcfclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;dcfclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;dcfclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;dcfclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;dcfclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].dcfclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;dcfclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* fclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_fclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;fclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_fclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;fclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.fclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].fclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.fclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].fclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.fclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;fclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.fclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;fclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;fclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;fclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;fclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].fclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;fclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* uclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_memclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;uclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_memclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;uclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.memclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].memclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.memclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].memclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.memclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;uclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.memclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;uclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;uclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;uclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;uclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].memclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;uclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* dispclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_dispclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;dispclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_dispclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;dispclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.dispclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].dispclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.dispclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].dispclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.dispclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;dispclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.dispclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;dispclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;dispclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;dispclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;dispclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].dispclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;dispclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* dppclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_dppclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;dppclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_dppclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;dppclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.dppclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].dppclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.dppclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].dppclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.dppclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;dppclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.dppclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;dppclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;dppclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;dppclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;dppclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].dppclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;dppclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* dtbclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_dtbclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;dtbclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_dtbclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;dtbclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.dtbclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].dtbclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.dtbclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].dtbclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.dtbclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;dtbclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.dtbclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;dtbclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;dtbclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;dtbclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;dtbclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].dtbclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;dtbclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* socclk */</div><div class='add'>+	if (dc_clk_table-&gt;num_entries_per_clk.num_socclk_levels) {</div><div class='add'>+		dml_clk_table-&gt;socclk.num_clk_values = dc_clk_table-&gt;num_entries_per_clk.num_socclk_levels;</div><div class='add'>+		for (i = 0; i &lt; min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {</div><div class='add'>+			if (i &lt; dml_clk_table-&gt;socclk.num_clk_values) {</div><div class='add'>+				if (use_clock_dc_limits &amp;&amp; dc_bw_params-&gt;dc_mode_limit.socclk_mhz &amp;&amp;</div><div class='add'>+						dc_clk_table-&gt;entries[i].socclk_mhz &gt; dc_bw_params-&gt;dc_mode_limit.socclk_mhz) {</div><div class='add'>+					if (i == 0 || dc_clk_table-&gt;entries[i-1].socclk_mhz &lt; dc_bw_params-&gt;dc_mode_limit.socclk_mhz) {</div><div class='add'>+						dml_clk_table-&gt;socclk.clk_values_khz[i] = dc_bw_params-&gt;dc_mode_limit.socclk_mhz * 1000;</div><div class='add'>+						dml_clk_table-&gt;socclk.num_clk_values = i + 1;</div><div class='add'>+					} else {</div><div class='add'>+						dml_clk_table-&gt;socclk.clk_values_khz[i] = 0;</div><div class='add'>+						dml_clk_table-&gt;socclk.num_clk_values = i;</div><div class='add'>+					}</div><div class='add'>+				} else {</div><div class='add'>+					dml_clk_table-&gt;socclk.clk_values_khz[i] = dc_clk_table-&gt;entries[i].socclk_mhz * 1000;</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='add'>+				dml_clk_table-&gt;socclk.clk_values_khz[i] = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* dram config */</div><div class='add'>+	dml_clk_table-&gt;dram_config.channel_count = dc_bw_params-&gt;num_channels;</div><div class='add'>+	dml_clk_table-&gt;dram_config.channel_width_bytes = dc_bw_params-&gt;dram_channel_width_bytes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	soc_bb-&gt;dprefclk_mhz = dc-&gt;clk_mgr-&gt;dprefclk_khz / 1000;</div><div class='add'>+	soc_bb-&gt;dispclk_dppclk_vco_speed_mhz = dc-&gt;clk_mgr-&gt;dentist_vco_freq_khz / 1000.0;</div><div class='add'>+	soc_bb-&gt;mall_allocated_for_dcn_mbytes = dc-&gt;caps.mall_size_total / (1024 * 1024);</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;clk_mgr-&gt;funcs-&gt;is_smu_present &amp;&amp;</div><div class='add'>+			dc-&gt;clk_mgr-&gt;funcs-&gt;is_smu_present(dc-&gt;clk_mgr)) {</div><div class='add'>+		dcn401_convert_dc_clock_table_to_soc_bb_clock_table(&amp;soc_bb-&gt;clk_table,</div><div class='add'>+			dc-&gt;clk_mgr-&gt;bw_params,</div><div class='add'>+			config-&gt;use_clock_dc_limits);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	soc_bb-&gt;dchub_refclk_mhz = dc-&gt;res_pool-&gt;ref_clocks.dchub_ref_clock_inKhz / 1000;</div><div class='add'>+	soc_bb-&gt;xtalclk_mhz = dc-&gt;ctx-&gt;dc_bios-&gt;fw_info.pll_info.crystal_frequency / 1000;</div><div class='add'>+</div><div class='add'>+	/* latencies in vbios are platform specific and should be used if provided */</div><div class='add'>+	if (dc-&gt;ctx-&gt;dc_bios-&gt;bb_info.dram_clock_change_latency_100ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us =</div><div class='add'>+				dc-&gt;ctx-&gt;dc_bios-&gt;bb_info.dram_clock_change_latency_100ns / 10.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dc_bios-&gt;bb_info.dram_sr_enter_exit_latency_100ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us =</div><div class='add'>+				dc-&gt;ctx-&gt;dc_bios-&gt;bb_info.dram_sr_enter_exit_latency_100ns / 10.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;ctx-&gt;dc_bios-&gt;bb_info.dram_sr_exit_latency_100ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.stutter_exit_latency_us =</div><div class='add'>+			dc-&gt;ctx-&gt;dc_bios-&gt;bb_info.dram_sr_exit_latency_100ns / 10.0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	/* set if the value is provided */</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_exit_time_ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.stutter_exit_latency_us =</div><div class='add'>+				dc-&gt;bb_overrides.sr_exit_time_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_enter_plus_exit_time_ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.stutter_enter_plus_exit_latency_us =</div><div class='add'>+				dc-&gt;bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.dram_clock_change_latency_ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.dram_clk_change_blackout_us =</div><div class='add'>+				dc-&gt;bb_overrides.dram_clock_change_latency_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.fclk_clock_change_latency_ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.fclk_change_blackout_us =</div><div class='add'>+				dc-&gt;bb_overrides.fclk_clock_change_latency_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	//Z8 values not expected nor used on DCN401 but still added for completeness</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_exit_z8_time_ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.z8_stutter_exit_latency_us =</div><div class='add'>+				dc-&gt;bb_overrides.sr_exit_z8_time_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_enter_plus_exit_z8_time_ns)</div><div class='add'>+		soc_bb-&gt;power_management_parameters.z8_stutter_enter_plus_exit_latency_us =</div><div class='add'>+				dc-&gt;bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	/* Individual modification can be overwritten even if it was obtained by a previous function.</div><div class='add'>+	 * Modifications are acquired in order of priority (lowest to highest).</div><div class='add'>+	 */</div><div class='add'>+	dc_assert_fp_enabled();</div><div class='add'>+</div><div class='add'>+	dcn401_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc, config);</div><div class='add'>+	dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc);</div><div class='add'>+	dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)</div><div class='add'>+{</div><div class='add'>+	//get default soc_bb with static values</div><div class='add'>+	get_default_soc_bb(soc_bb);</div><div class='add'>+	//update soc_bb values with more accurate values</div><div class='add'>+	apply_soc_bb_updates(soc_bb, dc, config);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn401_get_ip_caps(struct dml2_ip_capabilities *ip_caps)</div><div class='add'>+{</div><div class='add'>+	*ip_caps = dml2_dcn401_max_ip_caps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct soc_and_ip_translator_funcs dcn401_translator_funcs = {</div><div class='add'>+	.get_soc_bb = dcn401_get_soc_bb,</div><div class='add'>+	.get_ip_caps = dcn401_get_ip_caps,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn401_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator)</div><div class='add'>+{</div><div class='add'>+	soc_and_ip_translator-&gt;translator_funcs = &amp;dcn401_translator_funcs;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h<br/>new file mode 100644<br/>index 000000000000..88c11b6be004<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef _DCN401_SOC_AND_IP_TRANSLATOR_H_</div><div class='add'>+#define _DCN401_SOC_AND_IP_TRANSLATOR_H_</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='add'>+#include "soc_and_ip_translator.h"</div><div class='add'>+#include "dml2_0/dml21/inc/dml_top_soc_parameter_types.h"</div><div class='add'>+</div><div class='add'>+void dcn401_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator);</div><div class='add'>+</div><div class='add'>+/* Functions that can be re-used by higher DCN revisions of this component */</div><div class='add'>+void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);</div><div class='add'>+void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config);</div><div class='add'>+void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc);</div><div class='add'>+void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc);</div><div class='add'>+</div><div class='add'>+#endif /* _DCN401_SOC_AND_IP_TRANSLATOR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c<br/>new file mode 100644<br/>index 000000000000..c9e224d262c9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dcn42_soc_and_ip_translator.h"</div><div class='add'>+#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h"</div><div class='add'>+#include "bounding_boxes/dcn42_soc_bb.h"</div><div class='add'>+</div><div class='add'>+/* soc_and_ip_translator component used to get up-to-date values for bounding box.</div><div class='add'>+ * Bounding box values are stored in several locations and locations can vary with DCN revision.</div><div class='add'>+ * This component provides an interface to get DCN-specific bounding box values.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static void dcn42_get_ip_caps(struct dml2_ip_capabilities *ip_caps)</div><div class='add'>+{</div><div class='add'>+	*ip_caps = dml2_dcn42_max_ip_caps;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct soc_and_ip_translator_funcs dcn42_translator_funcs = {</div><div class='add'>+	.get_soc_bb = dcn401_get_soc_bb,</div><div class='add'>+	.get_ip_caps = dcn42_get_ip_caps,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator)</div><div class='add'>+{</div><div class='add'>+	soc_and_ip_translator-&gt;translator_funcs = &amp;dcn42_translator_funcs;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h<br/>new file mode 100644<br/>index 000000000000..914dcbb369a7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef _DCN42_SOC_AND_IP_TRANSLATOR_H_</div><div class='add'>+#define _DCN42_SOC_AND_IP_TRANSLATOR_H_</div><div class='add'>+</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "clk_mgr.h"</div><div class='add'>+#include "dml_top_soc_parameter_types.h"</div><div class='add'>+#include "soc_and_ip_translator.h"</div><div class='add'>+</div><div class='add'>+void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator);</div><div class='add'>+</div><div class='add'>+#endif /* _DCN42_SOC_AND_IP_TRANSLATOR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c<br/>new file mode 100644<br/>index 000000000000..0fc0e5a6c171<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "soc_and_ip_translator.h"</div><div class='add'>+#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h"</div><div class='add'>+</div><div class='add'>+static void dc_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator,</div><div class='add'>+		enum dce_version dc_version)</div><div class='add'>+{</div><div class='add'>+	switch (dc_version) {</div><div class='add'>+	case DCN_VERSION_4_01:</div><div class='add'>+		dcn401_construct_soc_and_ip_translator(soc_and_ip_translator);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct soc_and_ip_translator *dc_create_soc_and_ip_translator(enum dce_version dc_version)</div><div class='add'>+{</div><div class='add'>+	struct soc_and_ip_translator *soc_and_ip_translator;</div><div class='add'>+</div><div class='add'>+	soc_and_ip_translator = kzalloc(sizeof(*soc_and_ip_translator), GFP_KERNEL);</div><div class='add'>+	if (!soc_and_ip_translator)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dc_construct_soc_and_ip_translator(soc_and_ip_translator, dc_version);</div><div class='add'>+</div><div class='add'>+	return soc_and_ip_translator;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_destroy_soc_and_ip_translator(struct soc_and_ip_translator **soc_and_ip_translator)</div><div class='add'>+{</div><div class='add'>+	kfree(*soc_and_ip_translator);</div><div class='add'>+	*soc_and_ip_translator = NULL;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/Makefile b/drivers/gpu/drm/amd/display/dc/sspl/Makefile<br/>new file mode 100644<br/>index 000000000000..5e3e4aa13820<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/Makefile</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+#</div><div class='add'>+# Copyright 2017 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'spl' sub-component of DAL.</div><div class='add'>+# It provides the scaling library interface.</div><div class='add'>+</div><div class='add'>+SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o spl_fixpt31_32.o spl_custom_float.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_SPL = $(addprefix $(AMDDALPATH)/dc/sspl/,$(SPL))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_SPL)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c<br/>new file mode 100644<br/>index 000000000000..7a839984dbc0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c</a></div><div class='hunk'>@@ -0,0 +1,1925 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dc_spl.h"</div><div class='add'>+#include "dc_spl_scl_easf_filters.h"</div><div class='add'>+#include "dc_spl_isharp_filters.h"</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+</div><div class='add'>+#define IDENTITY_RATIO(ratio) (spl_fixpt_u3d19(ratio) == (1 &lt;&lt; 19))</div><div class='add'>+#define MIN_VIEWPORT_SIZE 12</div><div class='add'>+</div><div class='add'>+static bool spl_is_yuv420(enum spl_pixel_format format)</div><div class='add'>+{</div><div class='add'>+	if ((format &gt;= SPL_PIXEL_FORMAT_420BPP8) &amp;&amp;</div><div class='add'>+		(format &lt;= SPL_PIXEL_FORMAT_420BPP10))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool spl_is_rgb8(enum spl_pixel_format format)</div><div class='add'>+{</div><div class='add'>+	if (format == SPL_PIXEL_FORMAT_ARGB8888)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool spl_is_video_format(enum spl_pixel_format format)</div><div class='add'>+{</div><div class='add'>+	if (format &gt;= SPL_PIXEL_FORMAT_VIDEO_BEGIN</div><div class='add'>+		&amp;&amp; format &lt;= SPL_PIXEL_FORMAT_VIDEO_END)</div><div class='add'>+		return true;</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool spl_is_subsampled_format(enum spl_pixel_format format)</div><div class='add'>+{</div><div class='add'>+	if (format &gt;= SPL_PIXEL_FORMAT_SUBSAMPLED_BEGIN</div><div class='add'>+		&amp;&amp; format &lt;= SPL_PIXEL_FORMAT_SUBSAMPLED_END)</div><div class='add'>+		return true;</div><div class='add'>+	else</div><div class='add'>+		return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct spl_rect intersect_rec(const struct spl_rect *r0, const struct spl_rect *r1)</div><div class='add'>+{</div><div class='add'>+	struct spl_rect rec;</div><div class='add'>+	int r0_x_end = r0-&gt;x + r0-&gt;width;</div><div class='add'>+	int r1_x_end = r1-&gt;x + r1-&gt;width;</div><div class='add'>+	int r0_y_end = r0-&gt;y + r0-&gt;height;</div><div class='add'>+	int r1_y_end = r1-&gt;y + r1-&gt;height;</div><div class='add'>+</div><div class='add'>+	rec.x = r0-&gt;x &gt; r1-&gt;x ? r0-&gt;x : r1-&gt;x;</div><div class='add'>+	rec.width = r0_x_end &gt; r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x;</div><div class='add'>+	rec.y = r0-&gt;y &gt; r1-&gt;y ? r0-&gt;y : r1-&gt;y;</div><div class='add'>+	rec.height = r0_y_end &gt; r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y;</div><div class='add'>+</div><div class='add'>+	/* in case that there is no intersection */</div><div class='add'>+	if (rec.width &lt; 0 || rec.height &lt; 0)</div><div class='add'>+		memset(&amp;rec, 0, sizeof(rec));</div><div class='add'>+</div><div class='add'>+	return rec;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct spl_rect shift_rec(const struct spl_rect *rec_in, int x, int y)</div><div class='add'>+{</div><div class='add'>+	struct spl_rect rec_out = *rec_in;</div><div class='add'>+</div><div class='add'>+	rec_out.x += x;</div><div class='add'>+	rec_out.y += y;</div><div class='add'>+</div><div class='add'>+	return rec_out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_opp_adjust_rect(struct spl_rect *rec, const struct spl_opp_adjust *adjust)</div><div class='add'>+{</div><div class='add'>+	if ((rec-&gt;x + adjust-&gt;x) &gt;= 0)</div><div class='add'>+		rec-&gt;x += adjust-&gt;x;</div><div class='add'>+</div><div class='add'>+	if ((rec-&gt;y + adjust-&gt;y) &gt;= 0)</div><div class='add'>+		rec-&gt;y += adjust-&gt;y;</div><div class='add'>+</div><div class='add'>+	if ((rec-&gt;width + adjust-&gt;width) &gt;= 1)</div><div class='add'>+		rec-&gt;width += adjust-&gt;width;</div><div class='add'>+</div><div class='add'>+	if ((rec-&gt;height + adjust-&gt;height) &gt;= 1)</div><div class='add'>+		rec-&gt;height += adjust-&gt;height;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct spl_rect calculate_plane_rec_in_timing_active(</div><div class='add'>+		struct spl_in *spl_in,</div><div class='add'>+		const struct spl_rect *rec_in)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * The following diagram shows an example where we map a 1920x1200</div><div class='add'>+	 * desktop to a 2560x1440 timing with a plane rect in the middle</div><div class='add'>+	 * of the screen. To map a plane rect from Stream Source to Timing</div><div class='add'>+	 * Active space, we first multiply stream scaling ratios (i.e 2304/1920</div><div class='add'>+	 * horizontal and 1440/1200 vertical) to the plane's x and y, then</div><div class='add'>+	 * we add stream destination offsets (i.e 128 horizontal, 0 vertical).</div><div class='add'>+	 * This will give us a plane rect's position in Timing Active. However</div><div class='add'>+	 * we have to remove the fractional. The rule is that we find left/right</div><div class='add'>+	 * and top/bottom positions and round the value to the adjacent integer.</div><div class='add'>+	 *</div><div class='add'>+	 * Stream Source Space</div><div class='add'>+	 * ------------</div><div class='add'>+	 *        __________________________________________________</div><div class='add'>+	 *       |Stream Source (1920 x 1200) ^                     |</div><div class='add'>+	 *       |                            y                     |</div><div class='add'>+	 *       |         &lt;------- w --------|&gt;                    |</div><div class='add'>+	 *       |          __________________V                     |</div><div class='add'>+	 *       |&lt;-- x --&gt;|Plane//////////////| ^                  |</div><div class='add'>+	 *       |         |(pre scale)////////| |                  |</div><div class='add'>+	 *       |         |///////////////////| |                  |</div><div class='add'>+	 *       |         |///////////////////| h                  |</div><div class='add'>+	 *       |         |///////////////////| |                  |</div><div class='add'>+	 *       |         |///////////////////| |                  |</div><div class='add'>+	 *       |         |///////////////////| V                  |</div><div class='add'>+	 *       |                                                  |</div><div class='add'>+	 *       |                                                  |</div><div class='add'>+	 *       |__________________________________________________|</div><div class='add'>+	 *</div><div class='add'>+	 *</div><div class='add'>+	 * Timing Active Space</div><div class='add'>+	 * ---------------------------------</div><div class='add'>+	 *</div><div class='add'>+	 *       Timing Active (2560 x 1440)</div><div class='add'>+	 *        __________________________________________________</div><div class='add'>+	 *       |*****|  Stteam Destination (2304 x 1440)    |*****|</div><div class='add'>+	 *       |*****|                                      |*****|</div><div class='add'>+	 *       |&lt;128&gt;|                                      |*****|</div><div class='add'>+	 *       |*****|     __________________               |*****|</div><div class='add'>+	 *       |*****|    |Plane/////////////|              |*****|</div><div class='add'>+	 *       |*****|    |(post scale)//////|              |*****|</div><div class='add'>+	 *       |*****|    |//////////////////|              |*****|</div><div class='add'>+	 *       |*****|    |//////////////////|              |*****|</div><div class='add'>+	 *       |*****|    |//////////////////|              |*****|</div><div class='add'>+	 *       |*****|    |//////////////////|              |*****|</div><div class='add'>+	 *       |*****|                                      |*****|</div><div class='add'>+	 *       |*****|                                      |*****|</div><div class='add'>+	 *       |*****|                                      |*****|</div><div class='add'>+	 *       |*****|______________________________________|*****|</div><div class='add'>+	 *</div><div class='add'>+	 * So the resulting formulas are shown below:</div><div class='add'>+	 *</div><div class='add'>+	 * recout_x = 128 + round(plane_x * 2304 / 1920)</div><div class='add'>+	 * recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x</div><div class='add'>+	 * recout_y = 0 + round(plane_y * 1440 / 1200)</div><div class='add'>+	 * recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y</div><div class='add'>+	 *</div><div class='add'>+	 * NOTE: fixed point division is not error free. To reduce errors</div><div class='add'>+	 * introduced by fixed point division, we divide only after</div><div class='add'>+	 * multiplication is complete.</div><div class='add'>+	 */</div><div class='add'>+	const struct spl_rect *stream_src = &amp;spl_in-&gt;basic_out.src_rect;</div><div class='add'>+	const struct spl_rect *stream_dst = &amp;spl_in-&gt;basic_out.dst_rect;</div><div class='add'>+	struct spl_rect rec_out = {0};</div><div class='add'>+	struct spl_fixed31_32 temp;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	temp = spl_fixpt_from_fraction(rec_in-&gt;x * (long long)stream_dst-&gt;width,</div><div class='add'>+			stream_src-&gt;width);</div><div class='add'>+	rec_out.x = stream_dst-&gt;x + spl_fixpt_round(temp);</div><div class='add'>+</div><div class='add'>+	temp = spl_fixpt_from_fraction(</div><div class='add'>+			(rec_in-&gt;x + rec_in-&gt;width) * (long long)stream_dst-&gt;width,</div><div class='add'>+			stream_src-&gt;width);</div><div class='add'>+	rec_out.width = stream_dst-&gt;x + spl_fixpt_round(temp) - rec_out.x;</div><div class='add'>+</div><div class='add'>+	temp = spl_fixpt_from_fraction(rec_in-&gt;y * (long long)stream_dst-&gt;height,</div><div class='add'>+			stream_src-&gt;height);</div><div class='add'>+	rec_out.y = stream_dst-&gt;y + spl_fixpt_round(temp);</div><div class='add'>+</div><div class='add'>+	temp = spl_fixpt_from_fraction(</div><div class='add'>+			(rec_in-&gt;y + rec_in-&gt;height) * (long long)stream_dst-&gt;height,</div><div class='add'>+			stream_src-&gt;height);</div><div class='add'>+	rec_out.height = stream_dst-&gt;y + spl_fixpt_round(temp) - rec_out.y;</div><div class='add'>+</div><div class='add'>+	return rec_out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct spl_rect calculate_mpc_slice_in_timing_active(</div><div class='add'>+		struct spl_in *spl_in,</div><div class='add'>+		struct spl_rect *plane_clip_rec)</div><div class='add'>+{</div><div class='add'>+	bool use_recout_width_aligned =</div><div class='add'>+		spl_in-&gt;basic_in.num_h_slices_recout_width_align.use_recout_width_aligned;</div><div class='add'>+	int mpc_slice_count =</div><div class='add'>+		spl_in-&gt;basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices;</div><div class='add'>+	int recout_width_align =</div><div class='add'>+		spl_in-&gt;basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_recout_width_align;</div><div class='add'>+	int mpc_slice_idx = spl_in-&gt;basic_in.mpc_h_slice_index;</div><div class='add'>+	int epimo = mpc_slice_count - plane_clip_rec-&gt;width % mpc_slice_count - 1;</div><div class='add'>+	struct spl_rect mpc_rec;</div><div class='add'>+</div><div class='add'>+	if (spl_in-&gt;basic_in.custom_width != 0) {</div><div class='add'>+		mpc_rec.width = spl_in-&gt;basic_in.custom_width;</div><div class='add'>+		mpc_rec.x = spl_in-&gt;basic_in.custom_x;</div><div class='add'>+		mpc_rec.height = plane_clip_rec-&gt;height;</div><div class='add'>+		mpc_rec.y = plane_clip_rec-&gt;y;</div><div class='add'>+	} else if (use_recout_width_aligned) {</div><div class='add'>+		mpc_rec.width = recout_width_align;</div><div class='add'>+		if ((mpc_rec.width * (mpc_slice_idx + 1)) &gt; plane_clip_rec-&gt;width) {</div><div class='add'>+			mpc_rec.width = plane_clip_rec-&gt;width % recout_width_align;</div><div class='add'>+			mpc_rec.x = plane_clip_rec-&gt;x + recout_width_align * mpc_slice_idx;</div><div class='add'>+		} else</div><div class='add'>+			mpc_rec.x = plane_clip_rec-&gt;x + mpc_rec.width * mpc_slice_idx;</div><div class='add'>+		mpc_rec.height = plane_clip_rec-&gt;height;</div><div class='add'>+		mpc_rec.y = plane_clip_rec-&gt;y;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		mpc_rec.width = plane_clip_rec-&gt;width / mpc_slice_count;</div><div class='add'>+		mpc_rec.x = plane_clip_rec-&gt;x + mpc_rec.width * mpc_slice_idx;</div><div class='add'>+		mpc_rec.height = plane_clip_rec-&gt;height;</div><div class='add'>+		mpc_rec.y = plane_clip_rec-&gt;y;</div><div class='add'>+	}</div><div class='add'>+	SPL_ASSERT(mpc_slice_count == 1 ||</div><div class='add'>+			spl_in-&gt;basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE ||</div><div class='add'>+			mpc_rec.width % 2 == 0);</div><div class='add'>+</div><div class='add'>+	/* extra pixels in the division remainder need to go to pipes after</div><div class='add'>+	 * the extra pixel index minus one(epimo) defined here as:</div><div class='add'>+	 */</div><div class='add'>+	if (mpc_slice_idx &gt; epimo &amp;&amp; spl_in-&gt;basic_in.custom_width == 0) {</div><div class='add'>+		mpc_rec.x += mpc_slice_idx - epimo - 1;</div><div class='add'>+		mpc_rec.width += 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (spl_in-&gt;basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) {</div><div class='add'>+		SPL_ASSERT(mpc_rec.height % 2 == 0);</div><div class='add'>+		mpc_rec.height /= 2;</div><div class='add'>+	}</div><div class='add'>+	return mpc_rec;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_in)</div><div class='add'>+{</div><div class='add'>+	int odm_slice_count = spl_in-&gt;basic_out.odm_combine_factor;</div><div class='add'>+	int odm_slice_idx = spl_in-&gt;odm_slice_index;</div><div class='add'>+	bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;</div><div class='add'>+	int h_active = spl_in-&gt;basic_out.output_size.width;</div><div class='add'>+	int v_active = spl_in-&gt;basic_out.output_size.height;</div><div class='add'>+	int odm_slice_width;</div><div class='add'>+	struct spl_rect odm_rec;</div><div class='add'>+</div><div class='add'>+	if (spl_in-&gt;basic_out.odm_combine_factor &gt; 0) {</div><div class='add'>+		odm_slice_width = h_active / odm_slice_count;</div><div class='add'>+		/*</div><div class='add'>+		 * deprecated, caller must pass in odm slice rect i.e OPP input</div><div class='add'>+		 * rect in timing active for the new interface.</div><div class='add'>+		 */</div><div class='add'>+		if (spl_in-&gt;basic_out.use_two_pixels_per_container &amp;&amp; (odm_slice_width % 2))</div><div class='add'>+			odm_slice_width++;</div><div class='add'>+</div><div class='add'>+		odm_rec.x = odm_slice_width * odm_slice_idx;</div><div class='add'>+		odm_rec.width = is_last_odm_slice ?</div><div class='add'>+			/* last slice width is the reminder of h_active */</div><div class='add'>+			h_active - odm_slice_width * (odm_slice_count - 1) :</div><div class='add'>+			/* odm slice width is the floor of h_active / count */</div><div class='add'>+			odm_slice_width;</div><div class='add'>+		odm_rec.y = 0;</div><div class='add'>+		odm_rec.height = v_active;</div><div class='add'>+</div><div class='add'>+		return odm_rec;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return spl_in-&gt;basic_out.odm_slice_rect;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_calculate_recout(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * A plane clip represents the desired plane size and position in Stream</div><div class='add'>+	 * Source Space. Stream Source is the destination where all planes are</div><div class='add'>+	 * blended (i.e. positioned, scaled and overlaid). It is a canvas where</div><div class='add'>+	 * all planes associated with the current stream are drawn together.</div><div class='add'>+	 * After Stream Source is completed, we will further scale and</div><div class='add'>+	 * reposition the entire canvas of the stream source to Stream</div><div class='add'>+	 * Destination in Timing Active Space. This could be due to display</div><div class='add'>+	 * overscan adjustment where we will need to rescale and reposition all</div><div class='add'>+	 * the planes so they can fit into a TV with overscan or downscale</div><div class='add'>+	 * upscale features such as GPU scaling or VSR.</div><div class='add'>+	 *</div><div class='add'>+	 * This two step blending is a virtual procedure in software. In</div><div class='add'>+	 * hardware there is no such thing as Stream Source. all planes are</div><div class='add'>+	 * blended once in Timing Active Space. Software virtualizes a Stream</div><div class='add'>+	 * Source space to decouple the math complicity so scaling param</div><div class='add'>+	 * calculation focuses on one step at a time.</div><div class='add'>+	 *</div><div class='add'>+	 * In the following two diagrams, user applied 10% overscan adjustment</div><div class='add'>+	 * so the Stream Source needs to be scaled down a little before mapping</div><div class='add'>+	 * to Timing Active Space. As a result the Plane Clip is also scaled</div><div class='add'>+	 * down by the same ratio, Plane Clip position (i.e. x and y) with</div><div class='add'>+	 * respect to Stream Source is also scaled down. To map it in Timing</div><div class='add'>+	 * Active Space additional x and y offsets from Stream Destination are</div><div class='add'>+	 * added to Plane Clip as well.</div><div class='add'>+	 *</div><div class='add'>+	 * Stream Source Space</div><div class='add'>+	 * ------------</div><div class='add'>+	 *        __________________________________________________</div><div class='add'>+	 *       |Stream Source (3840 x 2160) ^                     |</div><div class='add'>+	 *       |                            y                     |</div><div class='add'>+	 *       |                            |                     |</div><div class='add'>+	 *       |          __________________V                     |</div><div class='add'>+	 *       |&lt;-- x --&gt;|Plane Clip/////////|                    |</div><div class='add'>+	 *       |         |(pre scale)////////|                    |</div><div class='add'>+	 *       |         |///////////////////|                    |</div><div class='add'>+	 *       |         |///////////////////|                    |</div><div class='add'>+	 *       |         |///////////////////|                    |</div><div class='add'>+	 *       |         |///////////////////|                    |</div><div class='add'>+	 *       |         |///////////////////|                    |</div><div class='add'>+	 *       |                                                  |</div><div class='add'>+	 *       |                                                  |</div><div class='add'>+	 *       |__________________________________________________|</div><div class='add'>+	 *</div><div class='add'>+	 *</div><div class='add'>+	 * Timing Active Space (3840 x 2160)</div><div class='add'>+	 * ---------------------------------</div><div class='add'>+	 *</div><div class='add'>+	 *       Timing Active</div><div class='add'>+	 *        __________________________________________________</div><div class='add'>+	 *       | y_____________________________________________   |</div><div class='add'>+	 *       |x |Stream Destination (3456 x 1944)            |  |</div><div class='add'>+	 *       |  |                                            |  |</div><div class='add'>+	 *       |  |        __________________                  |  |</div><div class='add'>+	 *       |  |       |Plane Clip////////|                 |  |</div><div class='add'>+	 *       |  |       |(post scale)//////|                 |  |</div><div class='add'>+	 *       |  |       |//////////////////|                 |  |</div><div class='add'>+	 *       |  |       |//////////////////|                 |  |</div><div class='add'>+	 *       |  |       |//////////////////|                 |  |</div><div class='add'>+	 *       |  |       |//////////////////|                 |  |</div><div class='add'>+	 *       |  |                                            |  |</div><div class='add'>+	 *       |  |                                            |  |</div><div class='add'>+	 *       |  |____________________________________________|  |</div><div class='add'>+	 *       |__________________________________________________|</div><div class='add'>+	 *</div><div class='add'>+	 *</div><div class='add'>+	 * In Timing Active Space a plane clip could be further sliced into</div><div class='add'>+	 * pieces called MPC slices. Each Pipe Context is responsible for</div><div class='add'>+	 * processing only one MPC slice so the plane processing workload can be</div><div class='add'>+	 * distributed to multiple DPP Pipes. MPC slices could be blended</div><div class='add'>+	 * together to a single ODM slice. Each ODM slice is responsible for</div><div class='add'>+	 * processing a portion of Timing Active divided horizontally so the</div><div class='add'>+	 * output pixel processing workload can be distributed to multiple OPP</div><div class='add'>+	 * pipes. All ODM slices are mapped together in ODM block so all MPC</div><div class='add'>+	 * slices belong to different ODM slices could be pieced together to</div><div class='add'>+	 * form a single image in Timing Active. MPC slices must belong to</div><div class='add'>+	 * single ODM slice. If an MPC slice goes across ODM slice boundary, it</div><div class='add'>+	 * needs to be divided into two MPC slices one for each ODM slice.</div><div class='add'>+	 *</div><div class='add'>+	 * In the following diagram the output pixel processing workload is</div><div class='add'>+	 * divided horizontally into two ODM slices one for each OPP blend tree.</div><div class='add'>+	 * OPP0 blend tree is responsible for processing left half of Timing</div><div class='add'>+	 * Active, while OPP2 blend tree is responsible for processing right</div><div class='add'>+	 * half.</div><div class='add'>+	 *</div><div class='add'>+	 * The plane has two MPC slices. However since the right MPC slice goes</div><div class='add'>+	 * across ODM boundary, two DPP pipes are needed one for each OPP blend</div><div class='add'>+	 * tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree).</div><div class='add'>+	 *</div><div class='add'>+	 * Assuming that we have a Pipe Context associated with OPP0 and DPP1</div><div class='add'>+	 * working on processing the plane in the diagram. We want to know the</div><div class='add'>+	 * width and height of the shaded rectangle and its relative position</div><div class='add'>+	 * with respect to the ODM slice0. This is called the recout of the pipe</div><div class='add'>+	 * context.</div><div class='add'>+	 *</div><div class='add'>+	 * Planes can be at arbitrary size and position and there could be an</div><div class='add'>+	 * arbitrary number of MPC and ODM slices. The algorithm needs to take</div><div class='add'>+	 * all scenarios into account.</div><div class='add'>+	 *</div><div class='add'>+	 * Timing Active Space (3840 x 2160)</div><div class='add'>+	 * ---------------------------------</div><div class='add'>+	 *</div><div class='add'>+	 *       Timing Active</div><div class='add'>+	 *        __________________________________________________</div><div class='add'>+	 *       |OPP0(ODM slice0)^        |OPP2(ODM slice1)        |</div><div class='add'>+	 *       |                y        |                        |</div><div class='add'>+	 *       |                |  &lt;- w -&gt;                        |</div><div class='add'>+	 *       |           _____V________|____                    |</div><div class='add'>+	 *       |          |DPP0 ^  |DPP1 |DPP2|                   |</div><div class='add'>+	 *       |&lt;------ x |-----|-&gt;|/////|    |                   |</div><div class='add'>+	 *       |          |     |  |/////|    |                   |</div><div class='add'>+	 *       |          |     h  |/////|    |                   |</div><div class='add'>+	 *       |          |     |  |/////|    |                   |</div><div class='add'>+	 *       |          |_____V__|/////|____|                   |</div><div class='add'>+	 *       |                         |                        |</div><div class='add'>+	 *       |                         |                        |</div><div class='add'>+	 *       |                         |                        |</div><div class='add'>+	 *       |_________________________|________________________|</div><div class='add'>+	 *</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='add'>+	struct spl_rect plane_clip;</div><div class='add'>+	struct spl_rect mpc_slice_of_plane_clip;</div><div class='add'>+	struct spl_rect odm_slice;</div><div class='add'>+	struct spl_rect overlapping_area;</div><div class='add'>+</div><div class='add'>+	plane_clip = calculate_plane_rec_in_timing_active(spl_in,</div><div class='add'>+			&amp;spl_in-&gt;basic_in.clip_rect);</div><div class='add'>+	/* guard plane clip from drawing beyond stream dst here */</div><div class='add'>+	plane_clip = intersect_rec(&amp;plane_clip,</div><div class='add'>+				&amp;spl_in-&gt;basic_out.dst_rect);</div><div class='add'>+	mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(</div><div class='add'>+			spl_in, &amp;plane_clip);</div><div class='add'>+	odm_slice = calculate_odm_slice_in_timing_active(spl_in);</div><div class='add'>+	overlapping_area = intersect_rec(&amp;mpc_slice_of_plane_clip, &amp;odm_slice);</div><div class='add'>+</div><div class='add'>+	if (overlapping_area.height &gt; 0 &amp;&amp;</div><div class='add'>+			overlapping_area.width &gt; 0) {</div><div class='add'>+		/* shift the overlapping area so it is with respect to current</div><div class='add'>+		 * ODM slice's position</div><div class='add'>+		 */</div><div class='add'>+		spl_scratch-&gt;scl_data.recout = shift_rec(</div><div class='add'>+				&amp;overlapping_area,</div><div class='add'>+				-odm_slice.x, -odm_slice.y);</div><div class='add'>+		spl_scratch-&gt;scl_data.recout.height -=</div><div class='add'>+			spl_in-&gt;debug.visual_confirm_base_offset;</div><div class='add'>+		spl_scratch-&gt;scl_data.recout.height -=</div><div class='add'>+			spl_in-&gt;debug.visual_confirm_dpp_offset;</div><div class='add'>+	} else</div><div class='add'>+		/* if there is no overlap, zero recout */</div><div class='add'>+		memset(&amp;spl_scratch-&gt;scl_data.recout, 0,</div><div class='add'>+				sizeof(struct spl_rect));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate scaling ratios */</div><div class='add'>+static void spl_calculate_scaling_ratios(struct spl_in *spl_in,</div><div class='add'>+		struct spl_scratch *spl_scratch,</div><div class='add'>+		struct spl_out *spl_out)</div><div class='add'>+{</div><div class='add'>+	const int in_w = spl_in-&gt;basic_out.src_rect.width;</div><div class='add'>+	const int in_h = spl_in-&gt;basic_out.src_rect.height;</div><div class='add'>+	const int out_w = spl_in-&gt;basic_out.dst_rect.width;</div><div class='add'>+	const int out_h = spl_in-&gt;basic_out.dst_rect.height;</div><div class='add'>+	struct spl_rect surf_src = spl_in-&gt;basic_in.src_rect;</div><div class='add'>+</div><div class='add'>+	/*Swap surf_src height and width since scaling ratios are in recout rotation*/</div><div class='add'>+	if (spl_in-&gt;basic_in.rotation == SPL_ROTATION_ANGLE_90 ||</div><div class='add'>+		spl_in-&gt;basic_in.rotation == SPL_ROTATION_ANGLE_270)</div><div class='add'>+		spl_swap(surf_src.height, surf_src.width);</div><div class='add'>+</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.horz = spl_fixpt_from_fraction(</div><div class='add'>+					surf_src.width,</div><div class='add'>+					spl_in-&gt;basic_in.dst_rect.width);</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.vert = spl_fixpt_from_fraction(</div><div class='add'>+					surf_src.height,</div><div class='add'>+					spl_in-&gt;basic_in.dst_rect.height);</div><div class='add'>+</div><div class='add'>+	if (spl_in-&gt;basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE)</div><div class='add'>+		spl_scratch-&gt;scl_data.ratios.horz.value *= 2;</div><div class='add'>+	else if (spl_in-&gt;basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM)</div><div class='add'>+		spl_scratch-&gt;scl_data.ratios.vert.value *= 2;</div><div class='add'>+</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.vert.value = spl_div64_s64(</div><div class='add'>+		spl_scratch-&gt;scl_data.ratios.vert.value * in_h, out_h);</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.horz.value = spl_div64_s64(</div><div class='add'>+		spl_scratch-&gt;scl_data.ratios.horz.value * in_w, out_w);</div><div class='add'>+</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.horz_c = spl_scratch-&gt;scl_data.ratios.horz;</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.vert_c = spl_scratch-&gt;scl_data.ratios.vert;</div><div class='add'>+</div><div class='add'>+	if (spl_is_yuv420(spl_in-&gt;basic_in.format)) {</div><div class='add'>+		spl_scratch-&gt;scl_data.ratios.horz_c.value /= 2;</div><div class='add'>+		spl_scratch-&gt;scl_data.ratios.vert_c.value /= 2;</div><div class='add'>+	}</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.horz = spl_fixpt_truncate(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.horz, 19);</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.vert = spl_fixpt_truncate(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.vert, 19);</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.horz_c = spl_fixpt_truncate(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.horz_c, 19);</div><div class='add'>+	spl_scratch-&gt;scl_data.ratios.vert_c = spl_fixpt_truncate(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.vert_c, 19);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Coefficient table and some registers are different based on ratio</div><div class='add'>+	 * that is output/input.  Currently we calculate input/output</div><div class='add'>+	 * Store 1/ratio in recip_ratio for those lookups</div><div class='add'>+	 */</div><div class='add'>+	spl_scratch-&gt;scl_data.recip_ratios.horz = spl_fixpt_recip(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.horz);</div><div class='add'>+	spl_scratch-&gt;scl_data.recip_ratios.vert = spl_fixpt_recip(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.vert);</div><div class='add'>+	spl_scratch-&gt;scl_data.recip_ratios.horz_c = spl_fixpt_recip(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.horz_c);</div><div class='add'>+	spl_scratch-&gt;scl_data.recip_ratios.vert_c = spl_fixpt_recip(</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.vert_c);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate Viewport size */</div><div class='add'>+static void spl_calculate_viewport_size(struct spl_in *spl_in, struct spl_scratch *spl_scratch)</div><div class='add'>+{</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch-&gt;scl_data.ratios.horz,</div><div class='add'>+							spl_scratch-&gt;scl_data.recout.width));</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch-&gt;scl_data.ratios.vert,</div><div class='add'>+							spl_scratch-&gt;scl_data.recout.height));</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport_c.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch-&gt;scl_data.ratios.horz_c,</div><div class='add'>+						spl_scratch-&gt;scl_data.recout.width));</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport_c.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch-&gt;scl_data.ratios.vert_c,</div><div class='add'>+						spl_scratch-&gt;scl_data.recout.height));</div><div class='add'>+	if (spl_in-&gt;basic_in.rotation == SPL_ROTATION_ANGLE_90 ||</div><div class='add'>+			spl_in-&gt;basic_in.rotation == SPL_ROTATION_ANGLE_270) {</div><div class='add'>+		spl_swap(spl_scratch-&gt;scl_data.viewport.width, spl_scratch-&gt;scl_data.viewport.height);</div><div class='add'>+		spl_swap(spl_scratch-&gt;scl_data.viewport_c.width, spl_scratch-&gt;scl_data.viewport_c.height);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_get_vp_scan_direction(enum spl_rotation_angle rotation,</div><div class='add'>+			   bool horizontal_mirror,</div><div class='add'>+			   bool *orthogonal_rotation,</div><div class='add'>+			   bool *flip_vert_scan_dir,</div><div class='add'>+			   bool *flip_horz_scan_dir)</div><div class='add'>+{</div><div class='add'>+	*orthogonal_rotation = false;</div><div class='add'>+	*flip_vert_scan_dir = false;</div><div class='add'>+	*flip_horz_scan_dir = false;</div><div class='add'>+	if (rotation == SPL_ROTATION_ANGLE_180) {</div><div class='add'>+		*flip_vert_scan_dir = true;</div><div class='add'>+		*flip_horz_scan_dir = true;</div><div class='add'>+	} else if (rotation == SPL_ROTATION_ANGLE_90) {</div><div class='add'>+		*orthogonal_rotation = true;</div><div class='add'>+		*flip_horz_scan_dir = true;</div><div class='add'>+	} else if (rotation == SPL_ROTATION_ANGLE_270) {</div><div class='add'>+		*orthogonal_rotation = true;</div><div class='add'>+		*flip_vert_scan_dir = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (horizontal_mirror)</div><div class='add'>+		*flip_horz_scan_dir = !*flip_horz_scan_dir;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * We completely calculate vp offset, size and inits here based entirely on scaling</div><div class='add'>+ * ratios and recout for pixel perfect pipe combine.</div><div class='add'>+ */</div><div class='add'>+static void spl_calculate_init_and_vp(bool flip_scan_dir,</div><div class='add'>+				int recout_offset_within_recout_full,</div><div class='add'>+				int recout_size,</div><div class='add'>+				int src_size,</div><div class='add'>+				int taps,</div><div class='add'>+				struct spl_fixed31_32 ratio,</div><div class='add'>+				struct spl_fixed31_32 init_adj,</div><div class='add'>+				struct spl_fixed31_32 *init,</div><div class='add'>+				int *vp_offset,</div><div class='add'>+				int *vp_size)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 temp;</div><div class='add'>+	int int_part;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * First of the taps starts sampling pixel number &lt;init_int_part&gt; corresponding to recout</div><div class='add'>+	 * pixel 1. Next recout pixel samples int part of &lt;init + scaling ratio&gt; and so on.</div><div class='add'>+	 * All following calculations are based on this logic.</div><div class='add'>+	 *</div><div class='add'>+	 * Init calculated according to formula:</div><div class='add'>+	 * init = (scaling_ratio + number_of_taps + 1) / 2</div><div class='add'>+	 * init_bot = init + scaling_ratio</div><div class='add'>+	 * to get pixel perfect combine add the fraction from calculating vp offset</div><div class='add'>+	 */</div><div class='add'>+	temp = spl_fixpt_mul_int(ratio, recout_offset_within_recout_full);</div><div class='add'>+	*vp_offset = spl_fixpt_floor(temp);</div><div class='add'>+	temp.value &amp;= 0xffffffff;</div><div class='add'>+	*init = spl_fixpt_add(spl_fixpt_div_int(spl_fixpt_add_int(ratio, taps + 1), 2), temp);</div><div class='add'>+	*init = spl_fixpt_add(*init, init_adj);</div><div class='add'>+	*init = spl_fixpt_truncate(*init, 19);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If viewport has non 0 offset and there are more taps than covered by init then</div><div class='add'>+	 * we should decrease the offset and increase init so we are never sampling</div><div class='add'>+	 * outside of viewport.</div><div class='add'>+	 */</div><div class='add'>+	int_part = spl_fixpt_floor(*init);</div><div class='add'>+	if (int_part &lt; taps) {</div><div class='add'>+		int_part = taps - int_part;</div><div class='add'>+		if (int_part &gt; *vp_offset)</div><div class='add'>+			int_part = *vp_offset;</div><div class='add'>+		*vp_offset -= int_part;</div><div class='add'>+		*init = spl_fixpt_add_int(*init, int_part);</div><div class='add'>+	}</div><div class='add'>+	/*</div><div class='add'>+	 * If taps are sampling outside of viewport at end of recout and there are more pixels</div><div class='add'>+	 * available in the surface we should increase the viewport size, regardless set vp to</div><div class='add'>+	 * only what is used.</div><div class='add'>+	 */</div><div class='add'>+	temp = spl_fixpt_add(*init, spl_fixpt_mul_int(ratio, recout_size - 1));</div><div class='add'>+	*vp_size = spl_fixpt_floor(temp);</div><div class='add'>+	if (*vp_size + *vp_offset &gt; src_size)</div><div class='add'>+		*vp_size = src_size - *vp_offset;</div><div class='add'>+</div><div class='add'>+	/* We did all the math assuming we are scanning same direction as display does,</div><div class='add'>+	 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction</div><div class='add'>+	 * is flipped we simply need to calculate offset from the other side of plane.</div><div class='add'>+	 * Note that outside of viewport all scaling hardware works in recout space.</div><div class='add'>+	 */</div><div class='add'>+	if (flip_scan_dir)</div><div class='add'>+		*vp_offset = src_size - *vp_offset - *vp_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*Calculate inits and viewport */</div><div class='add'>+static void spl_calculate_inits_and_viewports(struct spl_in *spl_in,</div><div class='add'>+		struct spl_scratch *spl_scratch)</div><div class='add'>+{</div><div class='add'>+	struct spl_rect src = spl_in-&gt;basic_in.src_rect;</div><div class='add'>+	struct spl_rect recout_dst_in_active_timing;</div><div class='add'>+	struct spl_rect recout_clip_in_active_timing;</div><div class='add'>+	struct spl_rect recout_clip_in_recout_dst;</div><div class='add'>+	struct spl_rect overlap_in_active_timing;</div><div class='add'>+	struct spl_rect odm_slice = calculate_odm_slice_in_timing_active(spl_in);</div><div class='add'>+	int vpc_div = spl_is_subsampled_format(spl_in-&gt;basic_in.format) ? 2 : 1;</div><div class='add'>+	bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;</div><div class='add'>+	struct spl_fixed31_32 init_adj_h = spl_fixpt_zero;</div><div class='add'>+	struct spl_fixed31_32 init_adj_v = spl_fixpt_zero;</div><div class='add'>+</div><div class='add'>+	recout_clip_in_active_timing = shift_rec(</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.recout, odm_slice.x, odm_slice.y);</div><div class='add'>+	recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(</div><div class='add'>+			spl_in, &amp;spl_in-&gt;basic_in.dst_rect);</div><div class='add'>+	overlap_in_active_timing = intersect_rec(&amp;recout_clip_in_active_timing,</div><div class='add'>+			&amp;recout_dst_in_active_timing);</div><div class='add'>+	if (overlap_in_active_timing.width &gt; 0 &amp;&amp;</div><div class='add'>+			overlap_in_active_timing.height &gt; 0)</div><div class='add'>+		recout_clip_in_recout_dst = shift_rec(&amp;overlap_in_active_timing,</div><div class='add'>+				-recout_dst_in_active_timing.x,</div><div class='add'>+				-recout_dst_in_active_timing.y);</div><div class='add'>+	else</div><div class='add'>+		memset(&amp;recout_clip_in_recout_dst, 0, sizeof(struct spl_rect));</div><div class='add'>+	/*</div><div class='add'>+	 * Work in recout rotation since that requires less transformations</div><div class='add'>+	 */</div><div class='add'>+	spl_get_vp_scan_direction(</div><div class='add'>+			spl_in-&gt;basic_in.rotation,</div><div class='add'>+			spl_in-&gt;basic_in.horizontal_mirror,</div><div class='add'>+			&amp;orthogonal_rotation,</div><div class='add'>+			&amp;flip_vert_scan_dir,</div><div class='add'>+			&amp;flip_horz_scan_dir);</div><div class='add'>+</div><div class='add'>+	if (spl_is_subsampled_format(spl_in-&gt;basic_in.format)) {</div><div class='add'>+		/* this gives the direction of the cositing (negative will move</div><div class='add'>+		 * left, right otherwise)</div><div class='add'>+		 */</div><div class='add'>+		int h_sign = flip_horz_scan_dir ? -1 : 1;</div><div class='add'>+		int v_sign = flip_vert_scan_dir ? -1 : 1;</div><div class='add'>+</div><div class='add'>+		switch (spl_in-&gt;basic_in.cositing) {</div><div class='add'>+		case CHROMA_COSITING_TOPLEFT:</div><div class='add'>+			init_adj_h = spl_fixpt_from_fraction(h_sign, 4);</div><div class='add'>+			init_adj_v = spl_fixpt_from_fraction(v_sign, 4);</div><div class='add'>+			break;</div><div class='add'>+		case CHROMA_COSITING_LEFT:</div><div class='add'>+			init_adj_h = spl_fixpt_from_fraction(h_sign, 4);</div><div class='add'>+			init_adj_v = spl_fixpt_zero;</div><div class='add'>+			break;</div><div class='add'>+		case CHROMA_COSITING_NONE:</div><div class='add'>+		default:</div><div class='add'>+			init_adj_h = spl_fixpt_zero;</div><div class='add'>+			init_adj_v = spl_fixpt_zero;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (orthogonal_rotation) {</div><div class='add'>+		spl_swap(src.width, src.height);</div><div class='add'>+		spl_swap(flip_vert_scan_dir, flip_horz_scan_dir);</div><div class='add'>+		spl_swap(init_adj_h, init_adj_v);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spl_calculate_init_and_vp(</div><div class='add'>+			flip_horz_scan_dir,</div><div class='add'>+			recout_clip_in_recout_dst.x,</div><div class='add'>+			spl_scratch-&gt;scl_data.recout.width,</div><div class='add'>+			src.width,</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps,</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.horz,</div><div class='add'>+			spl_fixpt_zero,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.inits.h,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport.x,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport.width);</div><div class='add'>+	spl_calculate_init_and_vp(</div><div class='add'>+			flip_horz_scan_dir,</div><div class='add'>+			recout_clip_in_recout_dst.x,</div><div class='add'>+			spl_scratch-&gt;scl_data.recout.width,</div><div class='add'>+			src.width / vpc_div,</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c,</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.horz_c,</div><div class='add'>+			init_adj_h,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.inits.h_c,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport_c.x,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport_c.width);</div><div class='add'>+	spl_calculate_init_and_vp(</div><div class='add'>+			flip_vert_scan_dir,</div><div class='add'>+			recout_clip_in_recout_dst.y,</div><div class='add'>+			spl_scratch-&gt;scl_data.recout.height,</div><div class='add'>+			src.height,</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.vert,</div><div class='add'>+			spl_fixpt_zero,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.inits.v,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport.y,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport.height);</div><div class='add'>+	spl_calculate_init_and_vp(</div><div class='add'>+			flip_vert_scan_dir,</div><div class='add'>+			recout_clip_in_recout_dst.y,</div><div class='add'>+			spl_scratch-&gt;scl_data.recout.height,</div><div class='add'>+			src.height / vpc_div,</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c,</div><div class='add'>+			spl_scratch-&gt;scl_data.ratios.vert_c,</div><div class='add'>+			init_adj_v,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.inits.v_c,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport_c.y,</div><div class='add'>+			&amp;spl_scratch-&gt;scl_data.viewport_c.height);</div><div class='add'>+	if (orthogonal_rotation) {</div><div class='add'>+		spl_swap(spl_scratch-&gt;scl_data.viewport.x, spl_scratch-&gt;scl_data.viewport.y);</div><div class='add'>+		spl_swap(spl_scratch-&gt;scl_data.viewport.width, spl_scratch-&gt;scl_data.viewport.height);</div><div class='add'>+		spl_swap(spl_scratch-&gt;scl_data.viewport_c.x, spl_scratch-&gt;scl_data.viewport_c.y);</div><div class='add'>+		spl_swap(spl_scratch-&gt;scl_data.viewport_c.width, spl_scratch-&gt;scl_data.viewport_c.height);</div><div class='add'>+	}</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport.x += src.x;</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport.y += src.y;</div><div class='add'>+	SPL_ASSERT(src.x % vpc_div == 0 &amp;&amp; src.y % vpc_div == 0);</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport_c.x += src.x / vpc_div;</div><div class='add'>+	spl_scratch-&gt;scl_data.viewport_c.y += src.y / vpc_div;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_handle_3d_recout(struct spl_in *spl_in, struct spl_rect *recout)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Handle side by side and top bottom 3d recout offsets after vp calculation</div><div class='add'>+	 * since 3d is special and needs to calculate vp as if there is no recout offset</div><div class='add'>+	 * This may break with rotation, good thing we aren't mixing hw rotation and 3d</div><div class='add'>+	 */</div><div class='add'>+	if (spl_in-&gt;basic_in.mpc_h_slice_index) {</div><div class='add'>+		SPL_ASSERT(spl_in-&gt;basic_in.rotation == SPL_ROTATION_ANGLE_0 ||</div><div class='add'>+			(spl_in-&gt;basic_out.view_format != SPL_VIEW_3D_TOP_AND_BOTTOM &amp;&amp;</div><div class='add'>+					spl_in-&gt;basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE));</div><div class='add'>+		if (spl_in-&gt;basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM)</div><div class='add'>+			recout-&gt;y += recout-&gt;height;</div><div class='add'>+		else if (spl_in-&gt;basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE)</div><div class='add'>+			recout-&gt;x += recout-&gt;width;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_clamp_viewport(struct spl_rect *viewport, int min_viewport_size)</div><div class='add'>+{</div><div class='add'>+	if (min_viewport_size == 0)</div><div class='add'>+		min_viewport_size = MIN_VIEWPORT_SIZE;</div><div class='add'>+	/* Clamp minimum viewport size */</div><div class='add'>+	if (viewport-&gt;height &lt; min_viewport_size)</div><div class='add'>+		viewport-&gt;height = min_viewport_size;</div><div class='add'>+	if (viewport-&gt;width &lt; min_viewport_size)</div><div class='add'>+		viewport-&gt;width = min_viewport_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in,</div><div class='add'>+				const struct spl_scaler_data *data,</div><div class='add'>+				bool enable_isharp, bool enable_easf)</div><div class='add'>+{</div><div class='add'>+	const long long one = spl_fixpt_one.value;</div><div class='add'>+	enum spl_pixel_format pixel_format = spl_in-&gt;basic_in.format;</div><div class='add'>+</div><div class='add'>+	/* Bypass if ratio is 1:1 with no ISHARP or force scale on */</div><div class='add'>+	if (data-&gt;ratios.horz.value == one</div><div class='add'>+			&amp;&amp; data-&gt;ratios.vert.value == one</div><div class='add'>+			&amp;&amp; data-&gt;ratios.horz_c.value == one</div><div class='add'>+			&amp;&amp; data-&gt;ratios.vert_c.value == one</div><div class='add'>+			&amp;&amp; !spl_in-&gt;basic_out.always_scale</div><div class='add'>+			&amp;&amp; !enable_isharp)</div><div class='add'>+		return SCL_MODE_SCALING_444_BYPASS;</div><div class='add'>+</div><div class='add'>+	if (!spl_is_subsampled_format(pixel_format)) {</div><div class='add'>+		if (spl_is_video_format(pixel_format))</div><div class='add'>+			return SCL_MODE_SCALING_444_YCBCR_ENABLE;</div><div class='add'>+		else</div><div class='add'>+			return SCL_MODE_SCALING_444_RGB_ENABLE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Bypass YUV if Y is 1:1 with no ISHARP</div><div class='add'>+	 * Do not bypass UV at 1:1 for cositing to be applied</div><div class='add'>+	 */</div><div class='add'>+	if (!enable_isharp) {</div><div class='add'>+		if (data-&gt;ratios.horz.value == one &amp;&amp; data-&gt;ratios.vert.value == one &amp;&amp; !spl_in-&gt;basic_out.always_scale)</div><div class='add'>+			return SCL_MODE_SCALING_420_LUMA_BYPASS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return SCL_MODE_SCALING_420_YCBCR_ENABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_choose_lls_policy(enum spl_pixel_format format,</div><div class='add'>+	enum linear_light_scaling *lls_pref)</div><div class='add'>+{</div><div class='add'>+	if (spl_is_subsampled_format(format))</div><div class='add'>+		*lls_pref = LLS_PREF_NO;</div><div class='add'>+	else /* RGB or YUV444 */</div><div class='add'>+		*lls_pref = LLS_PREF_YES;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable EASF ?*/</div><div class='add'>+static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch)</div><div class='add'>+{</div><div class='add'>+	int vratio = 0;</div><div class='add'>+	int hratio = 0;</div><div class='add'>+	bool skip_easf = false;</div><div class='add'>+</div><div class='add'>+	if (spl_in-&gt;disable_easf)</div><div class='add'>+		skip_easf = true;</div><div class='add'>+</div><div class='add'>+	vratio = spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert);</div><div class='add'>+	hratio = spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.horz);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * No EASF support for downscaling &gt; 2:1</div><div class='add'>+	 * EASF support for upscaling or downscaling up to 2:1</div><div class='add'>+	 */</div><div class='add'>+	if ((vratio &gt; 2) || (hratio &gt; 2))</div><div class='add'>+		skip_easf = true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If lls_pref is LLS_PREF_DONT_CARE, then use pixel format</div><div class='add'>+	 *  to determine whether to use LINEAR or NONLINEAR scaling</div><div class='add'>+	 */</div><div class='add'>+	if (spl_in-&gt;lls_pref == LLS_PREF_DONT_CARE)</div><div class='add'>+		spl_choose_lls_policy(spl_in-&gt;basic_in.format,</div><div class='add'>+			&amp;spl_in-&gt;lls_pref);</div><div class='add'>+</div><div class='add'>+	/* Check for linear scaling or EASF preferred */</div><div class='add'>+	if (spl_in-&gt;lls_pref != LLS_PREF_YES &amp;&amp; !spl_in-&gt;prefer_easf)</div><div class='add'>+		skip_easf = true;</div><div class='add'>+</div><div class='add'>+	return skip_easf;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Check if video is in fullscreen mode */</div><div class='add'>+static bool spl_is_video_fullscreen(struct spl_in *spl_in)</div><div class='add'>+{</div><div class='add'>+	if (spl_is_video_format(spl_in-&gt;basic_in.format) &amp;&amp; spl_in-&gt;is_fullscreen)</div><div class='add'>+		return true;</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool spl_get_isharp_en(struct spl_in *spl_in,</div><div class='add'>+	struct spl_scratch *spl_scratch)</div><div class='add'>+{</div><div class='add'>+	bool enable_isharp = false;</div><div class='add'>+	int vratio = 0;</div><div class='add'>+	int hratio = 0;</div><div class='add'>+	struct spl_taps taps = spl_scratch-&gt;scl_data.taps;</div><div class='add'>+	bool fullscreen = spl_is_video_fullscreen(spl_in);</div><div class='add'>+</div><div class='add'>+	/* Return if adaptive sharpness is disabled */</div><div class='add'>+	if (spl_in-&gt;adaptive_sharpness.enable == false)</div><div class='add'>+		return enable_isharp;</div><div class='add'>+</div><div class='add'>+	vratio = spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert);</div><div class='add'>+	hratio = spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.horz);</div><div class='add'>+</div><div class='add'>+	/* No iSHARP support for downscaling */</div><div class='add'>+	if (vratio &gt; 1 || hratio &gt; 1)</div><div class='add'>+		return enable_isharp;</div><div class='add'>+</div><div class='add'>+	// Scaling is up to 1:1 (no scaling) or upscaling</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Apply sharpness to RGB and YUV (NV12/P010)</div><div class='add'>+	 *  surfaces based on policy setting</div><div class='add'>+	 */</div><div class='add'>+	if (!spl_is_video_format(spl_in-&gt;basic_in.format) &amp;&amp;</div><div class='add'>+		(spl_in-&gt;sharpen_policy == SHARPEN_YUV))</div><div class='add'>+		return enable_isharp;</div><div class='add'>+	else if ((spl_is_video_format(spl_in-&gt;basic_in.format) &amp;&amp; !fullscreen) &amp;&amp;</div><div class='add'>+		(spl_in-&gt;sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV))</div><div class='add'>+		return enable_isharp;</div><div class='add'>+	else if (!spl_in-&gt;is_fullscreen &amp;&amp;</div><div class='add'>+			spl_in-&gt;sharpen_policy == SHARPEN_FULLSCREEN_ALL)</div><div class='add'>+		return enable_isharp;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Apply sharpness if supports horizontal taps 4,6 AND</div><div class='add'>+	 *  vertical taps 3, 4, 6</div><div class='add'>+	 */</div><div class='add'>+	if ((taps.h_taps == 4 || taps.h_taps == 6) &amp;&amp;</div><div class='add'>+		(taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6))</div><div class='add'>+		enable_isharp = true;</div><div class='add'>+</div><div class='add'>+	return enable_isharp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate number of tap with adaptive scaling off */</div><div class='add'>+static void spl_get_taps_non_adaptive_scaler(</div><div class='add'>+		struct spl_scratch *spl_scratch,</div><div class='add'>+		const struct spl_taps *in_taps,</div><div class='add'>+		bool is_subsampled)</div><div class='add'>+{</div><div class='add'>+	bool check_max_downscale = false;</div><div class='add'>+</div><div class='add'>+	if (in_taps-&gt;h_taps == 0) {</div><div class='add'>+		if (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.horz) &gt; 1)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil(</div><div class='add'>+				spl_scratch-&gt;scl_data.ratios.horz), 8);</div><div class='add'>+		else</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = 4;</div><div class='add'>+	} else</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.h_taps = in_taps-&gt;h_taps;</div><div class='add'>+</div><div class='add'>+	if (in_taps-&gt;v_taps == 0) {</div><div class='add'>+		if (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert) &gt; 1)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = spl_min(2 * spl_fixpt_ceil(</div><div class='add'>+				spl_scratch-&gt;scl_data.ratios.vert), 8);</div><div class='add'>+		else</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = 4;</div><div class='add'>+	} else</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.v_taps = in_taps-&gt;v_taps;</div><div class='add'>+</div><div class='add'>+	if (in_taps-&gt;v_taps_c == 0) {</div><div class='add'>+		if (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert_c) &gt; 1)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c = spl_min(2 * spl_fixpt_ceil(</div><div class='add'>+				spl_scratch-&gt;scl_data.ratios.vert_c), 8);</div><div class='add'>+		else</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c = 4;</div><div class='add'>+	} else</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.v_taps_c = in_taps-&gt;v_taps_c;</div><div class='add'>+</div><div class='add'>+	if (in_taps-&gt;h_taps_c == 0) {</div><div class='add'>+		if (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.horz_c) &gt; 1)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil(</div><div class='add'>+				spl_scratch-&gt;scl_data.ratios.horz_c), 8);</div><div class='add'>+		else</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c = 4;</div><div class='add'>+	} else if ((in_taps-&gt;h_taps_c % 2) != 0 &amp;&amp; in_taps-&gt;h_taps_c != 1)</div><div class='add'>+		/* Only 1 and even h_taps_c are supported by hw */</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.h_taps_c = in_taps-&gt;h_taps_c - 1;</div><div class='add'>+	else</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.h_taps_c = in_taps-&gt;h_taps_c;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Max downscale supported is 6.0x.  Add ASSERT to catch if go beyond that</div><div class='add'>+	 */</div><div class='add'>+	check_max_downscale = spl_fixpt_le(spl_scratch-&gt;scl_data.ratios.horz,</div><div class='add'>+		spl_fixpt_from_fraction(6, 1));</div><div class='add'>+	SPL_ASSERT(check_max_downscale);</div><div class='add'>+	check_max_downscale = spl_fixpt_le(spl_scratch-&gt;scl_data.ratios.vert,</div><div class='add'>+		spl_fixpt_from_fraction(6, 1));</div><div class='add'>+	SPL_ASSERT(check_max_downscale);</div><div class='add'>+	check_max_downscale = spl_fixpt_le(spl_scratch-&gt;scl_data.ratios.horz_c,</div><div class='add'>+		spl_fixpt_from_fraction(6, 1));</div><div class='add'>+	SPL_ASSERT(check_max_downscale);</div><div class='add'>+	check_max_downscale = spl_fixpt_le(spl_scratch-&gt;scl_data.ratios.vert_c,</div><div class='add'>+		spl_fixpt_from_fraction(6, 1));</div><div class='add'>+	SPL_ASSERT(check_max_downscale);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.horz))</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.h_taps = 1;</div><div class='add'>+	if (IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.vert))</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.v_taps = 1;</div><div class='add'>+	if (IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.horz_c) &amp;&amp; !is_subsampled)</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.h_taps_c = 1;</div><div class='add'>+	if (IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.vert_c) &amp;&amp; !is_subsampled)</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.v_taps_c = 1;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate optimal number of taps */</div><div class='add'>+static bool spl_get_optimal_number_of_taps(</div><div class='add'>+	  int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch,</div><div class='add'>+	  const struct spl_taps *in_taps, bool *enable_easf_v, bool *enable_easf_h,</div><div class='add'>+	  bool *enable_isharp)</div><div class='add'>+{</div><div class='add'>+	int num_part_y, num_part_c;</div><div class='add'>+	unsigned int max_taps_y, max_taps_c;</div><div class='add'>+	unsigned int min_taps_y, min_taps_c;</div><div class='add'>+	enum lb_memory_config lb_config;</div><div class='add'>+	bool skip_easf          = false;</div><div class='add'>+	bool is_subsampled = spl_is_subsampled_format(spl_in-&gt;basic_in.format);</div><div class='add'>+</div><div class='add'>+	if (spl_scratch-&gt;scl_data.viewport.width &gt; spl_scratch-&gt;scl_data.h_active &amp;&amp;</div><div class='add'>+		max_downscale_src_width != 0 &amp;&amp;</div><div class='add'>+		spl_scratch-&gt;scl_data.viewport.width &gt; max_downscale_src_width) {</div><div class='add'>+		spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled);</div><div class='add'>+		*enable_easf_v = false;</div><div class='add'>+		*enable_easf_h = false;</div><div class='add'>+		*enable_isharp = false;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Disable adaptive scaler and sharpener when integer scaling is enabled */</div><div class='add'>+	if (spl_in-&gt;scaling_quality.integer_scaling) {</div><div class='add'>+		spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled);</div><div class='add'>+		*enable_easf_v = false;</div><div class='add'>+		*enable_easf_h = false;</div><div class='add'>+		*enable_isharp = false;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check if we are using EASF or not */</div><div class='add'>+	skip_easf = enable_easf(spl_in, spl_scratch);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set default taps if none are provided</div><div class='add'>+	 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling</div><div class='add'>+	 * taps = 4 for upscaling</div><div class='add'>+	 */</div><div class='add'>+	if (skip_easf) {</div><div class='add'>+		spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled);</div><div class='add'>+	}</div><div class='add'>+	else {</div><div class='add'>+		if (spl_is_video_format(spl_in-&gt;basic_in.format)) {</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = 6;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = 6;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c = 4;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c = 4;</div><div class='add'>+		} else { /* RGB */</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = 6;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = 6;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c = 6;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c = 6;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Override mode: keep EASF enabled but use input taps if valid */</div><div class='add'>+		if (spl_in-&gt;override_easf) {</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = (in_taps-&gt;h_taps != 0) ? in_taps-&gt;h_taps : spl_scratch-&gt;scl_data.taps.h_taps;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = (in_taps-&gt;v_taps != 0) ? in_taps-&gt;v_taps : spl_scratch-&gt;scl_data.taps.v_taps;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c = (in_taps-&gt;h_taps_c != 0) ? in_taps-&gt;h_taps_c : spl_scratch-&gt;scl_data.taps.h_taps_c;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c = (in_taps-&gt;v_taps_c != 0) ? in_taps-&gt;v_taps_c : spl_scratch-&gt;scl_data.taps.v_taps_c;</div><div class='add'>+</div><div class='add'>+			if ((spl_scratch-&gt;scl_data.taps.h_taps &gt; 6) || (spl_scratch-&gt;scl_data.taps.v_taps &gt; 6))</div><div class='add'>+				skip_easf = true;</div><div class='add'>+			if ((spl_scratch-&gt;scl_data.taps.h_taps &gt; 1) &amp;&amp; (spl_scratch-&gt;scl_data.taps.h_taps % 2))</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.h_taps--;</div><div class='add'>+			if ((spl_scratch-&gt;scl_data.taps.h_taps_c &gt; 1) &amp;&amp; (spl_scratch-&gt;scl_data.taps.h_taps_c % 2))</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.h_taps_c--;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*Ensure we can support the requested number of vtaps*/</div><div class='add'>+	min_taps_y = spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert);</div><div class='add'>+	min_taps_c = spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert_c);</div><div class='add'>+</div><div class='add'>+	/* Use LB_MEMORY_CONFIG_3 for 4:2:0 */</div><div class='add'>+	if (spl_is_yuv420(spl_in-&gt;basic_in.format))</div><div class='add'>+		lb_config = LB_MEMORY_CONFIG_3;</div><div class='add'>+	else</div><div class='add'>+		lb_config = LB_MEMORY_CONFIG_0;</div><div class='add'>+	// Determine max vtap support by calculating how much line buffer can fit</div><div class='add'>+	spl_in-&gt;callbacks.spl_calc_lb_num_partitions(spl_in-&gt;basic_out.alpha_en, &amp;spl_scratch-&gt;scl_data,</div><div class='add'>+			lb_config, &amp;num_part_y, &amp;num_part_c);</div><div class='add'>+	/* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */</div><div class='add'>+	if (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert) &gt; 2)</div><div class='add'>+		if ((spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert) - 2) &gt; num_part_y)</div><div class='add'>+			max_taps_y = 0;</div><div class='add'>+		else</div><div class='add'>+			max_taps_y = num_part_y - (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert) - 2);</div><div class='add'>+	else</div><div class='add'>+		max_taps_y = num_part_y;</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert_c) &gt; 2)</div><div class='add'>+		if ((spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert_c) - 2) &gt; num_part_c)</div><div class='add'>+			max_taps_c = 0;</div><div class='add'>+		else</div><div class='add'>+			max_taps_c = num_part_c - (spl_fixpt_ceil(spl_scratch-&gt;scl_data.ratios.vert_c) - 2);</div><div class='add'>+	else</div><div class='add'>+		max_taps_c = num_part_c;</div><div class='add'>+</div><div class='add'>+	if (max_taps_y &lt; min_taps_y)</div><div class='add'>+		return false;</div><div class='add'>+	else if (max_taps_c &lt; min_taps_c)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (spl_scratch-&gt;scl_data.taps.v_taps &gt; max_taps_y)</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.v_taps = max_taps_y;</div><div class='add'>+</div><div class='add'>+	if (spl_scratch-&gt;scl_data.taps.v_taps_c &gt; max_taps_c)</div><div class='add'>+		spl_scratch-&gt;scl_data.taps.v_taps_c = max_taps_c;</div><div class='add'>+</div><div class='add'>+	if (!skip_easf) {</div><div class='add'>+		/*</div><div class='add'>+		 * RGB ( L + NL ) and Linear HDR support 6x6, 6x4, 6x3, 4x4, 4x3</div><div class='add'>+		 * NL YUV420 only supports 6x6, 6x4 for Y and 4x4 for UV</div><div class='add'>+		 *</div><div class='add'>+		 * If LB does not support 3, 4, or 6 taps, then disable EASF_V</div><div class='add'>+		 *  and only enable EASF_H.  So for RGB, support 6x2, 4x2</div><div class='add'>+		 *  and for NL YUV420, support 6x2 for Y and 4x2 for UV</div><div class='add'>+		 *</div><div class='add'>+		 * All other cases, have to disable EASF_V and EASF_H</div><div class='add'>+		 *</div><div class='add'>+		 * If optimal no of taps is 5, then set it to 4</div><div class='add'>+		 * If optimal no of taps is 7 or 8, then fine since max tap is 6</div><div class='add'>+		 *</div><div class='add'>+		 */</div><div class='add'>+		if (spl_scratch-&gt;scl_data.taps.v_taps == 5)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = 4;</div><div class='add'>+</div><div class='add'>+		if (spl_scratch-&gt;scl_data.taps.v_taps_c == 5)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps_c = 4;</div><div class='add'>+</div><div class='add'>+		if (spl_scratch-&gt;scl_data.taps.h_taps == 5)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = 4;</div><div class='add'>+</div><div class='add'>+		if (spl_scratch-&gt;scl_data.taps.h_taps_c == 5)</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps_c = 4;</div><div class='add'>+</div><div class='add'>+		if (spl_is_video_format(spl_in-&gt;basic_in.format)) {</div><div class='add'>+			if (spl_scratch-&gt;scl_data.taps.h_taps &lt;= 4) {</div><div class='add'>+				*enable_easf_v = false;</div><div class='add'>+				*enable_easf_h = false;</div><div class='add'>+			} else if (spl_scratch-&gt;scl_data.taps.v_taps &lt;= 3) {</div><div class='add'>+				*enable_easf_v = false;</div><div class='add'>+				*enable_easf_h = true;</div><div class='add'>+			} else {</div><div class='add'>+				*enable_easf_v = true;</div><div class='add'>+				*enable_easf_h = true;</div><div class='add'>+			}</div><div class='add'>+			SPL_ASSERT((spl_scratch-&gt;scl_data.taps.v_taps &gt; 1) &amp;&amp;</div><div class='add'>+				(spl_scratch-&gt;scl_data.taps.v_taps_c &gt; 1));</div><div class='add'>+		} else { /* RGB */</div><div class='add'>+			if (spl_scratch-&gt;scl_data.taps.h_taps &lt;= 3) {</div><div class='add'>+				*enable_easf_v = false;</div><div class='add'>+				*enable_easf_h = false;</div><div class='add'>+			} else if (spl_scratch-&gt;scl_data.taps.v_taps &lt; 3) {</div><div class='add'>+				*enable_easf_v = false;</div><div class='add'>+				*enable_easf_h = true;</div><div class='add'>+			} else {</div><div class='add'>+				*enable_easf_v = true;</div><div class='add'>+				*enable_easf_h = true;</div><div class='add'>+			}</div><div class='add'>+			SPL_ASSERT(spl_scratch-&gt;scl_data.taps.v_taps &gt; 1);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*enable_easf_v = false;</div><div class='add'>+		*enable_easf_h = false;</div><div class='add'>+	} // end of if prefer_easf</div><div class='add'>+</div><div class='add'>+	/* Sharpener requires scaler to be enabled, including for 1:1</div><div class='add'>+	 * Check if ISHARP can be enabled</div><div class='add'>+	 * If ISHARP is not enabled, set taps to 1 if ratio is 1:1</div><div class='add'>+	 *  except for chroma taps.  Keep previous taps so it can</div><div class='add'>+	 *  handle cositing</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	*enable_isharp = spl_get_isharp_en(spl_in, spl_scratch);</div><div class='add'>+	if (!*enable_isharp &amp;&amp; !spl_in-&gt;basic_out.always_scale)	{</div><div class='add'>+		if ((IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.horz)) &amp;&amp;</div><div class='add'>+			(IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.vert))) {</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.h_taps = 1;</div><div class='add'>+			spl_scratch-&gt;scl_data.taps.v_taps = 1;</div><div class='add'>+			if (IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.horz_c) &amp;&amp; !is_subsampled)</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.h_taps_c = 1;</div><div class='add'>+</div><div class='add'>+			if (IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.vert_c) &amp;&amp; !is_subsampled)</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.v_taps_c = 1;</div><div class='add'>+</div><div class='add'>+			*enable_easf_v = false;</div><div class='add'>+			*enable_easf_h = false;</div><div class='add'>+		} else {</div><div class='add'>+			if ((!*enable_easf_h) &amp;&amp;</div><div class='add'>+				(IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.horz)))</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.h_taps = 1;</div><div class='add'>+</div><div class='add'>+			if ((!*enable_easf_v) &amp;&amp;</div><div class='add'>+				(IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.vert)))</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.v_taps = 1;</div><div class='add'>+</div><div class='add'>+			if ((!*enable_easf_h) &amp;&amp; !is_subsampled &amp;&amp;</div><div class='add'>+				(IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.horz_c)))</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.h_taps_c = 1;</div><div class='add'>+</div><div class='add'>+			if ((!*enable_easf_v) &amp;&amp; !is_subsampled &amp;&amp;</div><div class='add'>+				(IDENTITY_RATIO(spl_scratch-&gt;scl_data.ratios.vert_c)))</div><div class='add'>+				spl_scratch-&gt;scl_data.taps.v_taps_c = 1;</div><div class='add'>+</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_set_black_color_data(enum spl_pixel_format format,</div><div class='add'>+			struct scl_black_color *scl_black_color)</div><div class='add'>+{</div><div class='add'>+	bool ycbcr = spl_is_video_format(format);</div><div class='add'>+	if (ycbcr)	{</div><div class='add'>+		scl_black_color-&gt;offset_rgb_y = BLACK_OFFSET_RGB_Y;</div><div class='add'>+		scl_black_color-&gt;offset_rgb_cbcr = BLACK_OFFSET_CBCR;</div><div class='add'>+	}	else {</div><div class='add'>+		scl_black_color-&gt;offset_rgb_y = 0x0;</div><div class='add'>+		scl_black_color-&gt;offset_rgb_cbcr = 0x0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_set_manual_ratio_init_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+		const struct spl_scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 bot;</div><div class='add'>+</div><div class='add'>+	dscl_prog_data-&gt;ratios.h_scale_ratio = spl_fixpt_u3d19(scl_data-&gt;ratios.horz) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;ratios.v_scale_ratio = spl_fixpt_u3d19(scl_data-&gt;ratios.vert) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;ratios.h_scale_ratio_c = spl_fixpt_u3d19(scl_data-&gt;ratios.horz_c) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;ratios.v_scale_ratio_c = spl_fixpt_u3d19(scl_data-&gt;ratios.vert_c) &lt;&lt; 5;</div><div class='add'>+	/*</div><div class='add'>+	 * 0.24 format for fraction, first five bits zeroed</div><div class='add'>+	 */</div><div class='add'>+	dscl_prog_data-&gt;init.h_filter_init_frac =</div><div class='add'>+			spl_fixpt_u0d19(scl_data-&gt;inits.h) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;init.h_filter_init_int =</div><div class='add'>+			spl_fixpt_floor(scl_data-&gt;inits.h);</div><div class='add'>+	dscl_prog_data-&gt;init.h_filter_init_frac_c =</div><div class='add'>+			spl_fixpt_u0d19(scl_data-&gt;inits.h_c) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;init.h_filter_init_int_c =</div><div class='add'>+			spl_fixpt_floor(scl_data-&gt;inits.h_c);</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_frac =</div><div class='add'>+			spl_fixpt_u0d19(scl_data-&gt;inits.v) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_int =</div><div class='add'>+			spl_fixpt_floor(scl_data-&gt;inits.v);</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_frac_c =</div><div class='add'>+			spl_fixpt_u0d19(scl_data-&gt;inits.v_c) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_int_c =</div><div class='add'>+			spl_fixpt_floor(scl_data-&gt;inits.v_c);</div><div class='add'>+</div><div class='add'>+	bot = spl_fixpt_add(scl_data-&gt;inits.v, scl_data-&gt;ratios.vert);</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_bot_frac = spl_fixpt_u0d19(bot) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_bot_int = spl_fixpt_floor(bot);</div><div class='add'>+	bot = spl_fixpt_add(scl_data-&gt;inits.v_c, scl_data-&gt;ratios.vert_c);</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_bot_frac_c = spl_fixpt_u0d19(bot) &lt;&lt; 5;</div><div class='add'>+	dscl_prog_data-&gt;init.v_filter_init_bot_int_c = spl_fixpt_floor(bot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void spl_set_taps_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+		const struct spl_scaler_data *scl_data)</div><div class='add'>+{</div><div class='add'>+	dscl_prog_data-&gt;taps.v_taps = scl_data-&gt;taps.v_taps - 1;</div><div class='add'>+	dscl_prog_data-&gt;taps.h_taps = scl_data-&gt;taps.h_taps - 1;</div><div class='add'>+	dscl_prog_data-&gt;taps.v_taps_c = scl_data-&gt;taps.v_taps_c - 1;</div><div class='add'>+	dscl_prog_data-&gt;taps.h_taps_c = scl_data-&gt;taps.h_taps_c - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Populate dscl prog data structure from scaler data calculated by SPL */</div><div class='add'>+static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *spl_scratch,</div><div class='add'>+	struct spl_out *spl_out, bool enable_easf_v, bool enable_easf_h, bool enable_isharp)</div><div class='add'>+{</div><div class='add'>+	struct dscl_prog_data *dscl_prog_data = spl_out-&gt;dscl_prog_data;</div><div class='add'>+</div><div class='add'>+	const struct spl_scaler_data *data = &amp;spl_scratch-&gt;scl_data;</div><div class='add'>+</div><div class='add'>+	struct scl_black_color *scl_black_color = &amp;dscl_prog_data-&gt;scl_black_color;</div><div class='add'>+</div><div class='add'>+	bool enable_easf = enable_easf_v || enable_easf_h;</div><div class='add'>+</div><div class='add'>+	// Set values for recout</div><div class='add'>+	dscl_prog_data-&gt;recout = spl_scratch-&gt;scl_data.recout;</div><div class='add'>+	// Set values for MPC Size</div><div class='add'>+	dscl_prog_data-&gt;mpc_size.width = spl_scratch-&gt;scl_data.h_active;</div><div class='add'>+	dscl_prog_data-&gt;mpc_size.height = spl_scratch-&gt;scl_data.v_active;</div><div class='add'>+</div><div class='add'>+	// SCL_MODE - Set SCL_MODE data</div><div class='add'>+	dscl_prog_data-&gt;dscl_mode = spl_get_dscl_mode(spl_in, data, enable_isharp,</div><div class='add'>+		enable_easf);</div><div class='add'>+</div><div class='add'>+	// SCL_BLACK_COLOR</div><div class='add'>+	spl_set_black_color_data(spl_in-&gt;basic_in.format, scl_black_color);</div><div class='add'>+</div><div class='add'>+	/* Manually calculate scale ratio and init values */</div><div class='add'>+	spl_set_manual_ratio_init_data(dscl_prog_data, data);</div><div class='add'>+</div><div class='add'>+	// Set HTaps/VTaps</div><div class='add'>+	spl_set_taps_data(dscl_prog_data, data);</div><div class='add'>+	// Set viewport</div><div class='add'>+	dscl_prog_data-&gt;viewport = spl_scratch-&gt;scl_data.viewport;</div><div class='add'>+	// Set viewport_c</div><div class='add'>+	dscl_prog_data-&gt;viewport_c = spl_scratch-&gt;scl_data.viewport_c;</div><div class='add'>+	// Set filters data</div><div class='add'>+	spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate C0-C3 coefficients based on HDR_mult */</div><div class='add'>+static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t sdr_white_level_nits)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 hdr_mult, c0_mult, c1_mult, c2_mult;</div><div class='add'>+	struct spl_fixed31_32 c0_calc, c1_calc, c2_calc;</div><div class='add'>+	struct spl_custom_float_format fmt;</div><div class='add'>+	uint32_t hdr_multx100_int;</div><div class='add'>+</div><div class='add'>+	if ((sdr_white_level_nits &gt;= 80) &amp;&amp; (sdr_white_level_nits &lt;= 480))</div><div class='add'>+		hdr_multx100_int = sdr_white_level_nits * 100 / 80;</div><div class='add'>+	else</div><div class='add'>+		hdr_multx100_int = 100; /* default for 80 nits otherwise */</div><div class='add'>+</div><div class='add'>+	hdr_mult = spl_fixpt_from_fraction((long long)hdr_multx100_int, 100LL);</div><div class='add'>+	c0_mult = spl_fixpt_from_fraction(2126LL, 10000LL);</div><div class='add'>+	c1_mult = spl_fixpt_from_fraction(7152LL, 10000LL);</div><div class='add'>+	c2_mult = spl_fixpt_from_fraction(722LL, 10000LL);</div><div class='add'>+</div><div class='add'>+	c0_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c0_mult, spl_fixpt_from_fraction(</div><div class='add'>+		16384LL, 125LL)));</div><div class='add'>+	c1_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c1_mult, spl_fixpt_from_fraction(</div><div class='add'>+		16384LL, 125LL)));</div><div class='add'>+	c2_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c2_mult, spl_fixpt_from_fraction(</div><div class='add'>+		16384LL, 125LL)));</div><div class='add'>+</div><div class='add'>+	fmt.exponenta_bits = 5;</div><div class='add'>+	fmt.mantissa_bits = 10;</div><div class='add'>+	fmt.sign = true;</div><div class='add'>+</div><div class='add'>+	// fp1.5.10, C0 coefficient (LN_rec709:  HDR_MULT * 0.212600 * 2^14/125)</div><div class='add'>+	spl_convert_to_custom_float_format(c0_calc, &amp;fmt, &amp;dscl_prog_data-&gt;easf_matrix_c0);</div><div class='add'>+	// fp1.5.10, C1 coefficient (LN_rec709:  HDR_MULT * 0.715200 * 2^14/125)</div><div class='add'>+	spl_convert_to_custom_float_format(c1_calc, &amp;fmt, &amp;dscl_prog_data-&gt;easf_matrix_c1);</div><div class='add'>+	// fp1.5.10, C2 coefficient (LN_rec709:  HDR_MULT * 0.072200 * 2^14/125)</div><div class='add'>+	spl_convert_to_custom_float_format(c2_calc, &amp;fmt, &amp;dscl_prog_data-&gt;easf_matrix_c2);</div><div class='add'>+	dscl_prog_data-&gt;easf_matrix_c3 = 0x0; // fp1.5.10, C3 coefficient</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Set EASF data */</div><div class='add'>+static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v,</div><div class='add'>+	bool enable_easf_h, enum linear_light_scaling lls_pref,</div><div class='add'>+	enum spl_pixel_format format, enum system_setup setup,</div><div class='add'>+	uint32_t sdr_white_level_nits)</div><div class='add'>+{</div><div class='add'>+	struct dscl_prog_data *dscl_prog_data = spl_out-&gt;dscl_prog_data;</div><div class='add'>+	if (enable_easf_v) {</div><div class='add'>+		dscl_prog_data-&gt;easf_v_en = true;</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ring = 0;</div><div class='add'>+		dscl_prog_data-&gt;easf_v_sharp_factor = 1;</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf1_en = 1;	// 1-bit, BF1 calculation enable, 0=disable, 1=enable</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf2_mode = 0xF;	// 4-bit, BF2 calculation mode</div><div class='add'>+		/* 2-bit, BF3 chroma mode correction calculation mode */</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf3_mode = spl_get_v_bf3_mode(</div><div class='add'>+			spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10 [ minCoef ]*/</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_3tap_dntilt_uptilt =</div><div class='add'>+			spl_get_3tap_dntilt_uptilt_offset(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10 [ upTiltMaxVal ]*/</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_3tap_uptilt_max =</div><div class='add'>+			spl_get_3tap_uptilt_maxval(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10 [ dnTiltSlope ]*/</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_3tap_dntilt_slope =</div><div class='add'>+			spl_get_3tap_dntilt_slope(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10 [ upTilt1Slope ]*/</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_3tap_uptilt1_slope =</div><div class='add'>+			spl_get_3tap_uptilt1_slope(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10 [ upTilt2Slope ]*/</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_3tap_uptilt2_slope =</div><div class='add'>+			spl_get_3tap_uptilt2_slope(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10 [ upTilt2Offset ]*/</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_3tap_uptilt2_offset =</div><div class='add'>+			spl_get_3tap_uptilt2_offset(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_eventap_reduceg1 =</div><div class='add'>+			spl_get_reducer_gain4(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_eventap_reduceg2 =</div><div class='add'>+			spl_get_reducer_gain6(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_eventap_gain1 =</div><div class='add'>+			spl_get_gainRing4(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		/* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */</div><div class='add'>+		dscl_prog_data-&gt;easf_v_ringest_eventap_gain2 =</div><div class='add'>+			spl_get_gainRing6(spl_scratch-&gt;scl_data.taps.v_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.vert);</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf_maxa = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 0</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf_maxb = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 1</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf_mina = 0;	//Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 0</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf_minb = 0;	//Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 1</div><div class='add'>+		if (lls_pref == LLS_PREF_YES)	{</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf2_flat1_gain = 4;	// U1.3, BF2 Flat1 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf2_flat2_gain = 8;	// U4.0, BF2 Flat2 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf2_roc_gain = 4;	// U2.2, Rate Of Change control</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg0 = 0x600;	// S0.10, BF1 PWL Segment 0 = -512</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg0 = 0;	// U0.6, BF1 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg0 = 3;	// S7.3, BF1 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg1 = 0x7EC;	// S0.10, BF1 PWL Segment 1 = -20</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg1 = 12;	// U0.6, BF1 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg1 = 326;	// S7.3, BF1 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg2 = 0;	// S0.10, BF1 PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg2 = 63;	// U0.6, BF1 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg2 = 0;	// S7.3, BF1 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg3 = 16;	// S0.10, BF1 PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg3 = 63;	// U0.6, BF1 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg3 = 0x7C8;	// S7.3, BF1 Slope PWL Segment 3 = -56</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg4 = 32;	// S0.10, BF1 PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg4 = 56;	// U0.6, BF1 Base PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg4 = 0x7D0;	// S7.3, BF1 Slope PWL Segment 4 = -48</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg5 = 48;	// S0.10, BF1 PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg5 = 50;	// U0.6, BF1 Base PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg5 = 0x710;	// S7.3, BF1 Slope PWL Segment 5 = -240</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg6 = 64;	// S0.10, BF1 PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg6 = 20;	// U0.6, BF1 Base PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg6 = 0x760;	// S7.3, BF1 Slope PWL Segment 6 = -160</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg7 = 80;	// S0.10, BF1 PWL Segment 7</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg7 = 0;	// U0.6, BF1 Base PWL Segment 7</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set0 = 0x000;	// FP0.6.6, BF3 Input value PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set0 = 63;	// S0.6, BF3 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set0 = 0x12C5;	// FP1.6.6, BF3 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set1 =</div><div class='add'>+				0x0B37; // FP0.6.6, BF3 Input value PWL Segment 1 (0.0078125 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set1 = 62;	// S0.6, BF3 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set1 =</div><div class='add'>+				0x13B8;	// FP1.6.6, BF3 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set2 =</div><div class='add'>+				0x0BB7;	// FP0.6.6, BF3 Input value PWL Segment 2 (0.03125 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set2 = 20;	// S0.6, BF3 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set2 =</div><div class='add'>+				0x1356;	// FP1.6.6, BF3 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set3 =</div><div class='add'>+				0x0BF7;	// FP0.6.6, BF3 Input value PWL Segment 3 (0.0625 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set3 = 0;	// S0.6, BF3 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set3 =</div><div class='add'>+				0x136B;	// FP1.6.6, BF3 Slope PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set4 =</div><div class='add'>+				0x0C37;	// FP0.6.6, BF3 Input value PWL Segment 4 (0.125 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set4 = 0x4E;	// S0.6, BF3 Base PWL Segment 4 = -50</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set4 =</div><div class='add'>+				0x1200;	// FP1.6.6, BF3 Slope PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set5 =</div><div class='add'>+				0x0CF7;	// FP0.6.6, BF3 Input value PWL Segment 5 (1.0 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set5 = 0x41;	// S0.6, BF3 Base PWL Segment 5 = -63</div><div class='add'>+		}	else	{</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf2_flat1_gain = 13;	// U1.3, BF2 Flat1 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf2_flat2_gain = 15;	// U4.0, BF2 Flat2 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf2_roc_gain = 14;	// U2.2, Rate Of Change control</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg0 = 0x440;	// S0.10, BF1 PWL Segment 0 = -960</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg0 = 0;	// U0.6, BF1 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg0 = 2;	// S7.3, BF1 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg1 = 0x7C4;	// S0.10, BF1 PWL Segment 1 = -60</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg1 = 12;	// U0.6, BF1 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg1 = 109;	// S7.3, BF1 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg2 = 0;	// S0.10, BF1 PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg2 = 63;	// U0.6, BF1 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg2 = 0;	// S7.3, BF1 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg3 = 48;	// S0.10, BF1 PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg3 = 63;	// U0.6, BF1 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg3 = 0x7ED;	// S7.3, BF1 Slope PWL Segment 3 = -19</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg4 = 96;	// S0.10, BF1 PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg4 = 56;	// U0.6, BF1 Base PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg4 = 0x7F0;	// S7.3, BF1 Slope PWL Segment 4 = -16</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg5 = 144;	// S0.10, BF1 PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg5 = 50;	// U0.6, BF1 Base PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg5 = 0x7B0;	// S7.3, BF1 Slope PWL Segment 5 = -80</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg6 = 192;	// S0.10, BF1 PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg6 = 20;	// U0.6, BF1 Base PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_slope_seg6 = 0x7CB;	// S7.3, BF1 Slope PWL Segment 6 = -53</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_in_seg7 = 240;	// S0.10, BF1 PWL Segment 7</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf1_pwl_base_seg7 = 0;	// U0.6, BF1 Base PWL Segment 7</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set0 = 0x000;	// FP0.6.6, BF3 Input value PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set0 = 63;	// S0.6, BF3 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set0 = 0x0000;	// FP1.6.6, BF3 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set1 =</div><div class='add'>+				0x06C0; // FP0.6.6, BF3 Input value PWL Segment 1 (0.0625)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set1 = 63;	// S0.6, BF3 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set1 = 0x1896;	// FP1.6.6, BF3 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set2 =</div><div class='add'>+				0x0700;	// FP0.6.6, BF3 Input value PWL Segment 2 (0.125)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set2 = 20;	// S0.6, BF3 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set2 = 0x1810;	// FP1.6.6, BF3 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set3 =</div><div class='add'>+				0x0740;	// FP0.6.6, BF3 Input value PWL Segment 3 (0.25)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set3 = 0;	// S0.6, BF3 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set3 =</div><div class='add'>+				0x1878;	// FP1.6.6, BF3 Slope PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set4 =</div><div class='add'>+				0x0761;	// FP0.6.6, BF3 Input value PWL Segment 4 (0.375)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set4 = 0x44;	// S0.6, BF3 Base PWL Segment 4 = -60</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_slope_set4 = 0x1760;	// FP1.6.6, BF3 Slope PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_in_set5 =</div><div class='add'>+				0x0780;	// FP0.6.6, BF3 Input value PWL Segment 5 (0.5)</div><div class='add'>+			dscl_prog_data-&gt;easf_v_bf3_pwl_base_set5 = 0x41;	// S0.6, BF3 Base PWL Segment 5 = -63</div><div class='add'>+		}</div><div class='add'>+	} else</div><div class='add'>+		dscl_prog_data-&gt;easf_v_en = false;</div><div class='add'>+</div><div class='add'>+	if (enable_easf_h) {</div><div class='add'>+		dscl_prog_data-&gt;easf_h_en = true;</div><div class='add'>+		dscl_prog_data-&gt;easf_h_ring = 0;</div><div class='add'>+		dscl_prog_data-&gt;easf_h_sharp_factor = 1;</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf1_en =</div><div class='add'>+			1;	// 1-bit, BF1 calculation enable, 0=disable, 1=enable</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf2_mode =</div><div class='add'>+			0xF;	// 4-bit, BF2 calculation mode</div><div class='add'>+		/* 2-bit, BF3 chroma mode correction calculation mode */</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf3_mode = spl_get_h_bf3_mode(</div><div class='add'>+			spl_scratch-&gt;scl_data.recip_ratios.horz);</div><div class='add'>+		/* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */</div><div class='add'>+		dscl_prog_data-&gt;easf_h_ringest_eventap_reduceg1 =</div><div class='add'>+			spl_get_reducer_gain4(spl_scratch-&gt;scl_data.taps.h_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.horz);</div><div class='add'>+		/* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */</div><div class='add'>+		dscl_prog_data-&gt;easf_h_ringest_eventap_reduceg2 =</div><div class='add'>+			spl_get_reducer_gain6(spl_scratch-&gt;scl_data.taps.h_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.horz);</div><div class='add'>+		/* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */</div><div class='add'>+		dscl_prog_data-&gt;easf_h_ringest_eventap_gain1 =</div><div class='add'>+			spl_get_gainRing4(spl_scratch-&gt;scl_data.taps.h_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.horz);</div><div class='add'>+		/* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */</div><div class='add'>+		dscl_prog_data-&gt;easf_h_ringest_eventap_gain2 =</div><div class='add'>+			spl_get_gainRing6(spl_scratch-&gt;scl_data.taps.h_taps,</div><div class='add'>+				spl_scratch-&gt;scl_data.recip_ratios.horz);</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf_maxa = 63; //Horz Max BF value A in U0.6 format.Selected if H_FCNTL==0</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf_maxb = 63; //Horz Max BF value B in U0.6 format.Selected if H_FCNTL==1</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf_mina = 0;	//Horz Min BF value B in U0.6 format.Selected if H_FCNTL==0</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf_minb = 0;	//Horz Min BF value B in U0.6 format.Selected if H_FCNTL==1</div><div class='add'>+		if (lls_pref == LLS_PREF_YES)	{</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf2_flat1_gain = 4;	// U1.3, BF2 Flat1 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf2_flat2_gain = 8;	// U4.0, BF2 Flat2 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf2_roc_gain = 4;	// U2.2, Rate Of Change control</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg0 = 0x600;	// S0.10, BF1 PWL Segment 0 = -512</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg0 = 0;	// U0.6, BF1 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg0 = 3;	// S7.3, BF1 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg1 = 0x7EC;	// S0.10, BF1 PWL Segment 1 = -20</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg1 = 12;	// U0.6, BF1 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg1 = 326;	// S7.3, BF1 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg2 = 0;	// S0.10, BF1 PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg2 = 63;	// U0.6, BF1 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg2 = 0;	// S7.3, BF1 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg3 = 16;	// S0.10, BF1 PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg3 = 63;	// U0.6, BF1 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg3 = 0x7C8;	// S7.3, BF1 Slope PWL Segment 3 = -56</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg4 = 32;	// S0.10, BF1 PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg4 = 56;	// U0.6, BF1 Base PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg4 = 0x7D0;	// S7.3, BF1 Slope PWL Segment 4 = -48</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg5 = 48;	// S0.10, BF1 PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg5 = 50;	// U0.6, BF1 Base PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg5 = 0x710;	// S7.3, BF1 Slope PWL Segment 5 = -240</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg6 = 64;	// S0.10, BF1 PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg6 = 20;	// U0.6, BF1 Base PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg6 = 0x760;	// S7.3, BF1 Slope PWL Segment 6 = -160</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg7 = 80;	// S0.10, BF1 PWL Segment 7</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg7 = 0;	// U0.6, BF1 Base PWL Segment 7</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set0 = 0x000;	// FP0.6.6, BF3 Input value PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set0 = 63;	// S0.6, BF3 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set0 = 0x12C5;	// FP1.6.6, BF3 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set1 =</div><div class='add'>+				0x0B37;	// FP0.6.6, BF3 Input value PWL Segment 1 (0.0078125 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set1 = 62;	// S0.6, BF3 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set1 =	0x13B8;	// FP1.6.6, BF3 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set2 =</div><div class='add'>+				0x0BB7;	// FP0.6.6, BF3 Input value PWL Segment 2 (0.03125 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set2 = 20;	// S0.6, BF3 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set2 =	0x1356;	// FP1.6.6, BF3 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set3 =</div><div class='add'>+				0x0BF7;	// FP0.6.6, BF3 Input value PWL Segment 3 (0.0625 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set3 = 0;	// S0.6, BF3 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set3 =	0x136B;	// FP1.6.6, BF3 Slope PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set4 =</div><div class='add'>+				0x0C37;	// FP0.6.6, BF3 Input value PWL Segment 4 (0.125 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set4 = 0x4E;	// S0.6, BF3 Base PWL Segment 4 = -50</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set4 = 0x1200;	// FP1.6.6, BF3 Slope PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set5 =</div><div class='add'>+				0x0CF7;	// FP0.6.6, BF3 Input value PWL Segment 5 (1.0 * 125^3)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set5 = 0x41;	// S0.6, BF3 Base PWL Segment 5 = -63</div><div class='add'>+		} else {</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf2_flat1_gain = 13;	// U1.3, BF2 Flat1 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf2_flat2_gain = 15;	// U4.0, BF2 Flat2 Gain control</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf2_roc_gain = 14;	// U2.2, Rate Of Change control</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg0 = 0x440;	// S0.10, BF1 PWL Segment 0 = -960</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg0 = 0;	// U0.6, BF1 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg0 = 2;	// S7.3, BF1 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg1 = 0x7C4;	// S0.10, BF1 PWL Segment 1 = -60</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg1 = 12;	// U0.6, BF1 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg1 = 109;	// S7.3, BF1 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg2 = 0;	// S0.10, BF1 PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg2 = 63;	// U0.6, BF1 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg2 = 0;	// S7.3, BF1 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg3 = 48;	// S0.10, BF1 PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg3 = 63;	// U0.6, BF1 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg3 = 0x7ED;	// S7.3, BF1 Slope PWL Segment 3 = -19</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg4 = 96;	// S0.10, BF1 PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg4 = 56;	// U0.6, BF1 Base PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg4 = 0x7F0;	// S7.3, BF1 Slope PWL Segment 4 = -16</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg5 = 144;	// S0.10, BF1 PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg5 = 50;	// U0.6, BF1 Base PWL Segment 5</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg5 = 0x7B0;	// S7.3, BF1 Slope PWL Segment 5 = -80</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg6 = 192;	// S0.10, BF1 PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg6 = 20;	// U0.6, BF1 Base PWL Segment 6</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_slope_seg6 = 0x7CB;	// S7.3, BF1 Slope PWL Segment 6 = -53</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_in_seg7 = 240;	// S0.10, BF1 PWL Segment 7</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf1_pwl_base_seg7 = 0;	// U0.6, BF1 Base PWL Segment 7</div><div class='add'>+</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set0 = 0x000;	// FP0.6.6, BF3 Input value PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set0 = 63;	// S0.6, BF3 Base PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set0 = 0x0000;	// FP1.6.6, BF3 Slope PWL Segment 0</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set1 =</div><div class='add'>+				0x06C0;	// FP0.6.6, BF3 Input value PWL Segment 1 (0.0625)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set1 = 63;	// S0.6, BF3 Base PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set1 = 0x1896;	// FP1.6.6, BF3 Slope PWL Segment 1</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set2 =</div><div class='add'>+				0x0700;	// FP0.6.6, BF3 Input value PWL Segment 2 (0.125)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set2 = 20;	// S0.6, BF3 Base PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set2 = 0x1810;	// FP1.6.6, BF3 Slope PWL Segment 2</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set3 =</div><div class='add'>+				0x0740;	// FP0.6.6, BF3 Input value PWL Segment 3 (0.25)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set3 = 0;	// S0.6, BF3 Base PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set3 = 0x1878;	// FP1.6.6, BF3 Slope PWL Segment 3</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set4 =</div><div class='add'>+				0x0761;	// FP0.6.6, BF3 Input value PWL Segment 4 (0.375)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set4 = 0x44;	// S0.6, BF3 Base PWL Segment 4 = -60</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_slope_set4 = 0x1760;	// FP1.6.6, BF3 Slope PWL Segment 4</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_in_set5 =</div><div class='add'>+				0x0780;	// FP0.6.6, BF3 Input value PWL Segment 5 (0.5)</div><div class='add'>+			dscl_prog_data-&gt;easf_h_bf3_pwl_base_set5 = 0x41;	// S0.6, BF3 Base PWL Segment 5 = -63</div><div class='add'>+		} // if (lls_pref == LLS_PREF_YES)</div><div class='add'>+	} else</div><div class='add'>+		dscl_prog_data-&gt;easf_h_en = false;</div><div class='add'>+</div><div class='add'>+	if (lls_pref == LLS_PREF_YES)	{</div><div class='add'>+		dscl_prog_data-&gt;easf_ltonl_en = 1;	// Linear input</div><div class='add'>+		if ((setup == HDR_L) &amp;&amp; (spl_is_rgb8(format))) {</div><div class='add'>+			/* Calculate C0-C3 coefficients based on HDR multiplier */</div><div class='add'>+			spl_calculate_c0_c3_hdr(dscl_prog_data, sdr_white_level_nits);</div><div class='add'>+		} else { // HDR_L ( DWM ) and SDR_L</div><div class='add'>+			dscl_prog_data-&gt;easf_matrix_c0 =</div><div class='add'>+				0x4EF7;	// fp1.5.10, C0 coefficient (LN_rec709:  0.2126 * (2^14)/125 = 27.86590720)</div><div class='add'>+			dscl_prog_data-&gt;easf_matrix_c1 =</div><div class='add'>+				0x55DC;	// fp1.5.10, C1 coefficient (LN_rec709:  0.7152 * (2^14)/125 = 93.74269440)</div><div class='add'>+			dscl_prog_data-&gt;easf_matrix_c2 =</div><div class='add'>+				0x48BB;	// fp1.5.10, C2 coefficient (LN_rec709:  0.0722 * (2^14)/125 = 9.46339840)</div><div class='add'>+			dscl_prog_data-&gt;easf_matrix_c3 =</div><div class='add'>+				0x0;	// fp1.5.10, C3 coefficient</div><div class='add'>+		}</div><div class='add'>+	}	else	{</div><div class='add'>+		dscl_prog_data-&gt;easf_ltonl_en = 0;	// Non-Linear input</div><div class='add'>+		dscl_prog_data-&gt;easf_matrix_c0 =</div><div class='add'>+			0x3434;	// fp1.5.10, C0 coefficient (LN_BT2020:  0.262695312500000)</div><div class='add'>+		dscl_prog_data-&gt;easf_matrix_c1 =</div><div class='add'>+			0x396D;	// fp1.5.10, C1 coefficient (LN_BT2020:  0.678222656250000)</div><div class='add'>+		dscl_prog_data-&gt;easf_matrix_c2 =</div><div class='add'>+			0x2B97;	// fp1.5.10, C2 coefficient (LN_BT2020:  0.059295654296875)</div><div class='add'>+		dscl_prog_data-&gt;easf_matrix_c3 =</div><div class='add'>+			0x0;	// fp1.5.10, C3 coefficient</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (spl_is_subsampled_format(format)) { /* TODO: 0 = RGB, 1 = YUV */</div><div class='add'>+		dscl_prog_data-&gt;easf_matrix_mode = 1;</div><div class='add'>+		/*</div><div class='add'>+		 * 2-bit, BF3 chroma mode correction calculation mode</div><div class='add'>+		 * Needs to be disabled for YUV420 mode</div><div class='add'>+		 * Override lookup value</div><div class='add'>+		 */</div><div class='add'>+		dscl_prog_data-&gt;easf_v_bf3_mode = 0;</div><div class='add'>+		dscl_prog_data-&gt;easf_h_bf3_mode = 0;</div><div class='add'>+	} else</div><div class='add'>+		dscl_prog_data-&gt;easf_matrix_mode = 0;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*Set isharp noise detection */</div><div class='add'>+static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+	const struct spl_scaler_data *data)</div><div class='add'>+{</div><div class='add'>+	// ISHARP_NOISEDET_MODE</div><div class='add'>+	// 0: 3x5 as VxH</div><div class='add'>+	// 1: 4x5 as VxH</div><div class='add'>+	// 2:</div><div class='add'>+	// 3: 5x5 as VxH</div><div class='add'>+	if (data-&gt;taps.v_taps == 6)</div><div class='add'>+		dscl_prog_data-&gt;isharp_noise_det.mode = 3;</div><div class='add'>+	else if (data-&gt;taps.v_taps == 4)</div><div class='add'>+		dscl_prog_data-&gt;isharp_noise_det.mode = 1;</div><div class='add'>+	else if (data-&gt;taps.v_taps == 3)</div><div class='add'>+		dscl_prog_data-&gt;isharp_noise_det.mode = 0;</div><div class='add'>+};</div><div class='add'>+/* Set Sharpener data */</div><div class='add'>+static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+		struct adaptive_sharpness adp_sharpness, bool enable_isharp,</div><div class='add'>+		enum linear_light_scaling lls_pref, enum spl_pixel_format format,</div><div class='add'>+		const struct spl_scaler_data *data, struct spl_fixed31_32 ratio,</div><div class='add'>+		enum system_setup setup, enum scale_to_sharpness_policy scale_to_sharpness_policy)</div><div class='add'>+{</div><div class='add'>+	/* Turn off sharpener if not required */</div><div class='add'>+	if (!enable_isharp) {</div><div class='add'>+		dscl_prog_data-&gt;isharp_en = 0;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness,</div><div class='add'>+		scale_to_sharpness_policy);</div><div class='add'>+	memcpy(dscl_prog_data-&gt;isharp_delta, spl_get_pregen_filter_isharp_1D_lut(setup),</div><div class='add'>+		sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE);</div><div class='add'>+	dscl_prog_data-&gt;sharpness_level = adp_sharpness.sharpness_level;</div><div class='add'>+</div><div class='add'>+	dscl_prog_data-&gt;isharp_en = 1;	// ISHARP_EN</div><div class='add'>+	// Set ISHARP_NOISEDET_MODE if htaps = 6-tap</div><div class='add'>+	if (data-&gt;taps.h_taps == 6) {</div><div class='add'>+		dscl_prog_data-&gt;isharp_noise_det.enable = 1;	/* ISHARP_NOISEDET_EN */</div><div class='add'>+		spl_set_isharp_noise_det_mode(dscl_prog_data, data);	/* ISHARP_NOISEDET_MODE */</div><div class='add'>+	} else</div><div class='add'>+		dscl_prog_data-&gt;isharp_noise_det.enable = 0;	// ISHARP_NOISEDET_EN</div><div class='add'>+	// Program noise detection threshold</div><div class='add'>+	dscl_prog_data-&gt;isharp_noise_det.uthreshold = 24;	// ISHARP_NOISEDET_UTHRE</div><div class='add'>+	dscl_prog_data-&gt;isharp_noise_det.dthreshold = 4;	// ISHARP_NOISEDET_DTHRE</div><div class='add'>+	// Program noise detection gain</div><div class='add'>+	dscl_prog_data-&gt;isharp_noise_det.pwl_start_in = 3;	// ISHARP_NOISEDET_PWL_START_IN</div><div class='add'>+	dscl_prog_data-&gt;isharp_noise_det.pwl_end_in = 13;	// ISHARP_NOISEDET_PWL_END_IN</div><div class='add'>+	dscl_prog_data-&gt;isharp_noise_det.pwl_slope = 1623;	// ISHARP_NOISEDET_PWL_SLOPE</div><div class='add'>+</div><div class='add'>+	if (lls_pref == LLS_PREF_NO) /* ISHARP_FMT_MODE */</div><div class='add'>+		dscl_prog_data-&gt;isharp_fmt.mode = 1;</div><div class='add'>+	else</div><div class='add'>+		dscl_prog_data-&gt;isharp_fmt.mode = 0;</div><div class='add'>+</div><div class='add'>+	dscl_prog_data-&gt;isharp_fmt.norm = 0x3C00;	// ISHARP_FMT_NORM</div><div class='add'>+	dscl_prog_data-&gt;isharp_lba.mode = 0;	// ISHARP_LBA_MODE</div><div class='add'>+</div><div class='add'>+	if (setup == SDR_L) {</div><div class='add'>+		// ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[0] = 0;	// ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[0] = 0;	// ISHARP LBA PWL for Seg 0. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[0] = 62;	// ISHARP LBA for Seg 0. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[1] = 130;	// ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[2] = 450; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[2] = 0x18D; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -115</div><div class='add'>+		// ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[3] = 520; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[4] = 520; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[5] = 520; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[5] = 0;	// ISHARP LBA PWL for Seg 5. BASE value in U0.6 format</div><div class='add'>+	} else if (setup == HDR_L) {</div><div class='add'>+		// ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[0] = 0;	// ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[0] = 0;	// ISHARP LBA PWL for Seg 0. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[0] = 32;	// ISHARP LBA for Seg 0. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[1] = 254;	// ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[2] = 559; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[2] = 0x10C; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -244</div><div class='add'>+		// ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[3] = 592; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[5] = 0;	// ISHARP LBA PWL for Seg 5. BASE value in U0.6 format</div><div class='add'>+	} else {</div><div class='add'>+		// ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[0] = 0;	// ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[0] = 0;	// ISHARP LBA PWL for Seg 0. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[0] = 40;	// ISHARP LBA for Seg 0. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[1] = 204;	// ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[2] = 818; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39</div><div class='add'>+		// ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format</div><div class='add'>+		// ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format</div><div class='add'>+		dscl_prog_data-&gt;isharp_lba.base_seg[5] = 0;	// ISHARP LBA PWL for Seg 5. BASE value in U0.6 format</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Program the nldelta soft clip values</div><div class='add'>+	if (lls_pref == LLS_PREF_YES) {</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.enable_p = 0;	/* ISHARP_NLDELTA_SCLIP_EN_P */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.pivot_p = 0;	/* ISHARP_NLDELTA_SCLIP_PIVOT_P */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.slope_p = 0;	/* ISHARP_NLDELTA_SCLIP_SLOPE_P */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.enable_n = 1;	/* ISHARP_NLDELTA_SCLIP_EN_N */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.pivot_n = 71;	/* ISHARP_NLDELTA_SCLIP_PIVOT_N */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.slope_n = 16;	/* ISHARP_NLDELTA_SCLIP_SLOPE_N */</div><div class='add'>+	} else {</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.enable_p = 1;	/* ISHARP_NLDELTA_SCLIP_EN_P */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.pivot_p = 70;	/* ISHARP_NLDELTA_SCLIP_PIVOT_P */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.slope_p = 24;	/* ISHARP_NLDELTA_SCLIP_SLOPE_P */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.enable_n = 1;	/* ISHARP_NLDELTA_SCLIP_EN_N */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.pivot_n = 70;	/* ISHARP_NLDELTA_SCLIP_PIVOT_N */</div><div class='add'>+		dscl_prog_data-&gt;isharp_nldelta_sclip.slope_n = 24;	/* ISHARP_NLDELTA_SCLIP_SLOPE_N */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Set the values as per lookup table</div><div class='add'>+	spl_set_blur_scale_data(dscl_prog_data, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate recout, scaling ratio, and viewport, then get optimal number of taps */</div><div class='add'>+static bool spl_calculate_number_of_taps(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out,</div><div class='add'>+	bool *enable_easf_v, bool *enable_easf_h, bool *enable_isharp)</div><div class='add'>+{</div><div class='add'>+	bool res = false;</div><div class='add'>+</div><div class='add'>+	memset(spl_scratch, 0, sizeof(struct spl_scratch));</div><div class='add'>+	spl_scratch-&gt;scl_data.h_active = spl_in-&gt;h_active;</div><div class='add'>+	spl_scratch-&gt;scl_data.v_active = spl_in-&gt;v_active;</div><div class='add'>+</div><div class='add'>+	// All SPL calls</div><div class='add'>+	/* recout calculation */</div><div class='add'>+	/* depends on h_active */</div><div class='add'>+	spl_calculate_recout(spl_in, spl_scratch, spl_out);</div><div class='add'>+	/* depends on pixel format */</div><div class='add'>+	spl_calculate_scaling_ratios(spl_in, spl_scratch, spl_out);</div><div class='add'>+	/* Adjust recout for opp if needed */</div><div class='add'>+	spl_opp_adjust_rect(&amp;spl_scratch-&gt;scl_data.recout, &amp;spl_in-&gt;basic_in.opp_recout_adjust);</div><div class='add'>+	/* depends on scaling ratios and recout, does not calculate offset yet */</div><div class='add'>+	spl_calculate_viewport_size(spl_in, spl_scratch);</div><div class='add'>+</div><div class='add'>+	res = spl_get_optimal_number_of_taps(</div><div class='add'>+			  spl_in-&gt;basic_out.max_downscale_src_width, spl_in,</div><div class='add'>+			  spl_scratch, &amp;spl_in-&gt;scaling_quality, enable_easf_v,</div><div class='add'>+			  enable_easf_h, enable_isharp);</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Calculate scaler parameters */</div><div class='add'>+bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out))</div><div class='add'>+{</div><div class='add'>+	bool res = false;</div><div class='add'>+	bool enable_easf_v = false;</div><div class='add'>+	bool enable_easf_h = false;</div><div class='add'>+	int vratio = 0;</div><div class='add'>+	int hratio = 0;</div><div class='add'>+	struct spl_scratch spl_scratch;</div><div class='add'>+	struct spl_fixed31_32 isharp_scale_ratio;</div><div class='add'>+	enum system_setup setup;</div><div class='add'>+	bool enable_isharp = false;</div><div class='add'>+	const struct spl_scaler_data *data = &amp;spl_scratch.scl_data;</div><div class='add'>+</div><div class='add'>+	res = spl_calculate_number_of_taps(spl_in, &amp;spl_scratch, spl_out,</div><div class='add'>+		&amp;enable_easf_v, &amp;enable_easf_h, &amp;enable_isharp);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Depends on recout, scaling ratios, h_active and taps</div><div class='add'>+	 * May need to re-check lb size after this in some obscure scenario</div><div class='add'>+	 */</div><div class='add'>+	if (res)</div><div class='add'>+		spl_calculate_inits_and_viewports(spl_in, &amp;spl_scratch);</div><div class='add'>+	// Handle 3d recout</div><div class='add'>+	spl_handle_3d_recout(spl_in, &amp;spl_scratch.scl_data.recout);</div><div class='add'>+	// Clamp</div><div class='add'>+	spl_clamp_viewport(&amp;spl_scratch.scl_data.viewport, spl_in-&gt;min_viewport_size);</div><div class='add'>+</div><div class='add'>+	// Save all calculated parameters in dscl_prog_data structure to program hw registers</div><div class='add'>+	spl_set_dscl_prog_data(spl_in, &amp;spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp);</div><div class='add'>+</div><div class='add'>+	if (!res)</div><div class='add'>+		return res;</div><div class='add'>+</div><div class='add'>+	if (spl_in-&gt;lls_pref == LLS_PREF_YES) {</div><div class='add'>+		if (spl_in-&gt;is_hdr_on)</div><div class='add'>+			setup = HDR_L;</div><div class='add'>+		else</div><div class='add'>+			setup = SDR_L;</div><div class='add'>+	} else {</div><div class='add'>+		if (spl_in-&gt;is_hdr_on)</div><div class='add'>+			setup = HDR_NL;</div><div class='add'>+		else</div><div class='add'>+			setup = SDR_NL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	// Set EASF</div><div class='add'>+	spl_set_easf_data(&amp;spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in-&gt;lls_pref,</div><div class='add'>+		spl_in-&gt;basic_in.format, setup, spl_in-&gt;sdr_white_level_nits);</div><div class='add'>+</div><div class='add'>+	// Set iSHARP</div><div class='add'>+	vratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.vert);</div><div class='add'>+	hratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.horz);</div><div class='add'>+	if (vratio &lt;= hratio)</div><div class='add'>+		isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.vert;</div><div class='add'>+	else</div><div class='add'>+		isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.horz;</div><div class='add'>+</div><div class='add'>+	spl_set_isharp_data(spl_out-&gt;dscl_prog_data, spl_in-&gt;adaptive_sharpness, enable_isharp,</div><div class='add'>+		spl_in-&gt;lls_pref, spl_in-&gt;basic_in.format, data, isharp_scale_ratio, setup,</div><div class='add'>+		spl_in-&gt;debug.scale_to_sharpness_policy);</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* External interface to get number of taps only */</div><div class='add'>+bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out))</div><div class='add'>+{</div><div class='add'>+	bool res = false;</div><div class='add'>+	bool enable_easf_v = false;</div><div class='add'>+	bool enable_easf_h = false;</div><div class='add'>+	bool enable_isharp = false;</div><div class='add'>+	struct spl_scratch spl_scratch;</div><div class='add'>+	struct dscl_prog_data *dscl_prog_data = spl_out-&gt;dscl_prog_data;</div><div class='add'>+	const struct spl_scaler_data *data = &amp;spl_scratch.scl_data;</div><div class='add'>+</div><div class='add'>+	res = spl_calculate_number_of_taps(spl_in, &amp;spl_scratch, spl_out,</div><div class='add'>+		&amp;enable_easf_v, &amp;enable_easf_h, &amp;enable_isharp);</div><div class='add'>+	spl_set_taps_data(dscl_prog_data, data);</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h<br/>new file mode 100644<br/>index 000000000000..d621c42a237e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_H__</div><div class='add'>+#define __DC_SPL_H__</div><div class='add'>+</div><div class='add'>+#include "dc_spl_types.h"</div><div class='add'>+#define BLACK_OFFSET_RGB_Y 0x0</div><div class='add'>+#define BLACK_OFFSET_CBCR  0x8000</div><div class='add'>+</div><div class='add'>+#ifndef SPL_PFX_</div><div class='add'>+#define SPL_PFX_</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define SPL_EXPAND2(a, b)         a##b</div><div class='add'>+#define SPL_EXPAND(a, b)          SPL_EXPAND2(a, b)</div><div class='add'>+#define SPL_NAMESPACE(symbol)     SPL_EXPAND(SPL_PFX_, symbol)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* SPL interfaces */</div><div class='add'>+</div><div class='add'>+bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out));</div><div class='add'>+</div><div class='add'>+bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out));</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c<br/>new file mode 100644<br/>index 000000000000..99238644e0a1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "dc_spl_filters.h"</div><div class='add'>+</div><div class='add'>+void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter,</div><div class='add'>+	uint16_t *s1_12_filter, int num_taps)</div><div class='add'>+{</div><div class='add'>+	int num_entries = NUM_PHASES_COEFF * num_taps;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++)</div><div class='add'>+		*(s1_12_filter + i) = *(s1_10_filter + i) * 4;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h<br/>new file mode 100644<br/>index 000000000000..20439cdbdb10<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+</div><div class='add'>+/* Copyright 2024 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_FILTERS_H__</div><div class='add'>+#define __DC_SPL_FILTERS_H__</div><div class='add'>+</div><div class='add'>+#include "dc_spl_types.h"</div><div class='add'>+</div><div class='add'>+#define NUM_PHASES_COEFF 33</div><div class='add'>+</div><div class='add'>+void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter,</div><div class='add'>+	uint16_t *s1_12_filter, int num_taps);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_FILTERS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c<br/>new file mode 100644<br/>index 000000000000..12acdd34e6a6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c</a></div><div class='hunk'>@@ -0,0 +1,553 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+#include "dc_spl_filters.h"</div><div class='add'>+#include "dc_spl_isharp_filters.h"</div><div class='add'>+</div><div class='add'>+//========================================</div><div class='add'>+// Delta Gain 1DLUT</div><div class='add'>+// LUT content is packed as 4-bytes into one DWORD/entry</div><div class='add'>+// A_start = 0.000000</div><div class='add'>+// A_end   = 10.000000</div><div class='add'>+// A_gain  = 3.000000</div><div class='add'>+// B_start = 11.000000</div><div class='add'>+// B_end   = 127.000000</div><div class='add'>+// C_start = 40.000000</div><div class='add'>+// C_end   = 127.000000</div><div class='add'>+//========================================</div><div class='add'>+static const uint32_t filter_isharp_1D_lut_3p0x[ISHARP_LUT_TABLE_SIZE] = {</div><div class='add'>+0x03010000,</div><div class='add'>+0x0F0B0805,</div><div class='add'>+0x211E1813,</div><div class='add'>+0x2B292624,</div><div class='add'>+0x3533302E,</div><div class='add'>+0x3E3C3A37,</div><div class='add'>+0x46444240,</div><div class='add'>+0x4D4B4A48,</div><div class='add'>+0x5352504F,</div><div class='add'>+0x59575655,</div><div class='add'>+0x5D5C5B5A,</div><div class='add'>+0x61605F5E,</div><div class='add'>+0x64646362,</div><div class='add'>+0x66666565,</div><div class='add'>+0x68686767,</div><div class='add'>+0x68686868,</div><div class='add'>+0x68686868,</div><div class='add'>+0x67676868,</div><div class='add'>+0x65656666,</div><div class='add'>+0x62636464,</div><div class='add'>+0x5E5F6061,</div><div class='add'>+0x5A5B5C5D,</div><div class='add'>+0x55565759,</div><div class='add'>+0x4F505253,</div><div class='add'>+0x484A4B4D,</div><div class='add'>+0x40424446,</div><div class='add'>+0x373A3C3E,</div><div class='add'>+0x2E303335,</div><div class='add'>+0x2426292B,</div><div class='add'>+0x191B1E21,</div><div class='add'>+0x0D101316,</div><div class='add'>+0x0003060A,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// Blur and scale coefficients</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_BlurScale_coeffs.m</div><div class='add'>+// &lt;date&gt;			25-Apr-2022</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;CoefType&gt;		Blur &amp; Scale LPF</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t filter_isharp_bs_4tap_in_6_64p[198] = {</div><div class='add'>+0x0000, 0x00E5, 0x0237, 0x00E4, 0x0000, 0x0000,</div><div class='add'>+0x0000, 0x00DE, 0x0237, 0x00EB, 0x0000, 0x0000,</div><div class='add'>+0x0000, 0x00D7, 0x0236, 0x00F2, 0x0001, 0x0000,</div><div class='add'>+0x0000, 0x00D0, 0x0235, 0x00FA, 0x0001, 0x0000,</div><div class='add'>+0x0000, 0x00C9, 0x0234, 0x0101, 0x0002, 0x0000,</div><div class='add'>+0x0000, 0x00C2, 0x0233, 0x0108, 0x0003, 0x0000,</div><div class='add'>+0x0000, 0x00BB, 0x0232, 0x0110, 0x0003, 0x0000,</div><div class='add'>+0x0000, 0x00B5, 0x0230, 0x0117, 0x0004, 0x0000,</div><div class='add'>+0x0000, 0x00AE, 0x022E, 0x011F, 0x0005, 0x0000,</div><div class='add'>+0x0000, 0x00A8, 0x022C, 0x0126, 0x0006, 0x0000,</div><div class='add'>+0x0000, 0x00A2, 0x022A, 0x012D, 0x0007, 0x0000,</div><div class='add'>+0x0000, 0x009C, 0x0228, 0x0134, 0x0008, 0x0000,</div><div class='add'>+0x0000, 0x0096, 0x0225, 0x013C, 0x0009, 0x0000,</div><div class='add'>+0x0000, 0x0090, 0x0222, 0x0143, 0x000B, 0x0000,</div><div class='add'>+0x0000, 0x008A, 0x021F, 0x014B, 0x000C, 0x0000,</div><div class='add'>+0x0000, 0x0085, 0x021C, 0x0151, 0x000E, 0x0000,</div><div class='add'>+0x0000, 0x007F, 0x0218, 0x015A, 0x000F, 0x0000,</div><div class='add'>+0x0000, 0x007A, 0x0215, 0x0160, 0x0011, 0x0000,</div><div class='add'>+0x0000, 0x0074, 0x0211, 0x0168, 0x0013, 0x0000,</div><div class='add'>+0x0000, 0x006F, 0x020D, 0x016F, 0x0015, 0x0000,</div><div class='add'>+0x0000, 0x006A, 0x0209, 0x0176, 0x0017, 0x0000,</div><div class='add'>+0x0000, 0x0065, 0x0204, 0x017E, 0x0019, 0x0000,</div><div class='add'>+0x0000, 0x0060, 0x0200, 0x0185, 0x001B, 0x0000,</div><div class='add'>+0x0000, 0x005C, 0x01FB, 0x018C, 0x001D, 0x0000,</div><div class='add'>+0x0000, 0x0057, 0x01F6, 0x0193, 0x0020, 0x0000,</div><div class='add'>+0x0000, 0x0053, 0x01F1, 0x019A, 0x0022, 0x0000,</div><div class='add'>+0x0000, 0x004E, 0x01EC, 0x01A1, 0x0025, 0x0000,</div><div class='add'>+0x0000, 0x004A, 0x01E6, 0x01A8, 0x0028, 0x0000,</div><div class='add'>+0x0000, 0x0046, 0x01E1, 0x01AF, 0x002A, 0x0000,</div><div class='add'>+0x0000, 0x0042, 0x01DB, 0x01B6, 0x002D, 0x0000,</div><div class='add'>+0x0000, 0x003F, 0x01D5, 0x01BB, 0x0031, 0x0000,</div><div class='add'>+0x0000, 0x003B, 0x01CF, 0x01C2, 0x0034, 0x0000,</div><div class='add'>+0x0000, 0x0037, 0x01C9, 0x01C9, 0x0037, 0x0000</div><div class='add'>+};</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_BlurScale_coeffs.m</div><div class='add'>+// &lt;date&gt;			25-Apr-2022</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;CoefType&gt;		Blur &amp; Scale LPF</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t filter_isharp_bs_4tap_64p[132] = {</div><div class='add'>+0x00E5, 0x0237, 0x00E4, 0x0000,</div><div class='add'>+0x00DE, 0x0237, 0x00EB, 0x0000,</div><div class='add'>+0x00D7, 0x0236, 0x00F2, 0x0001,</div><div class='add'>+0x00D0, 0x0235, 0x00FA, 0x0001,</div><div class='add'>+0x00C9, 0x0234, 0x0101, 0x0002,</div><div class='add'>+0x00C2, 0x0233, 0x0108, 0x0003,</div><div class='add'>+0x00BB, 0x0232, 0x0110, 0x0003,</div><div class='add'>+0x00B5, 0x0230, 0x0117, 0x0004,</div><div class='add'>+0x00AE, 0x022E, 0x011F, 0x0005,</div><div class='add'>+0x00A8, 0x022C, 0x0126, 0x0006,</div><div class='add'>+0x00A2, 0x022A, 0x012D, 0x0007,</div><div class='add'>+0x009C, 0x0228, 0x0134, 0x0008,</div><div class='add'>+0x0096, 0x0225, 0x013C, 0x0009,</div><div class='add'>+0x0090, 0x0222, 0x0143, 0x000B,</div><div class='add'>+0x008A, 0x021F, 0x014B, 0x000C,</div><div class='add'>+0x0085, 0x021C, 0x0151, 0x000E,</div><div class='add'>+0x007F, 0x0218, 0x015A, 0x000F,</div><div class='add'>+0x007A, 0x0215, 0x0160, 0x0011,</div><div class='add'>+0x0074, 0x0211, 0x0168, 0x0013,</div><div class='add'>+0x006F, 0x020D, 0x016F, 0x0015,</div><div class='add'>+0x006A, 0x0209, 0x0176, 0x0017,</div><div class='add'>+0x0065, 0x0204, 0x017E, 0x0019,</div><div class='add'>+0x0060, 0x0200, 0x0185, 0x001B,</div><div class='add'>+0x005C, 0x01FB, 0x018C, 0x001D,</div><div class='add'>+0x0057, 0x01F6, 0x0193, 0x0020,</div><div class='add'>+0x0053, 0x01F1, 0x019A, 0x0022,</div><div class='add'>+0x004E, 0x01EC, 0x01A1, 0x0025,</div><div class='add'>+0x004A, 0x01E6, 0x01A8, 0x0028,</div><div class='add'>+0x0046, 0x01E1, 0x01AF, 0x002A,</div><div class='add'>+0x0042, 0x01DB, 0x01B6, 0x002D,</div><div class='add'>+0x003F, 0x01D5, 0x01BB, 0x0031,</div><div class='add'>+0x003B, 0x01CF, 0x01C2, 0x0034,</div><div class='add'>+0x0037, 0x01C9, 0x01C9, 0x0037,</div><div class='add'>+};</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_BlurScale_coeffs.m</div><div class='add'>+// &lt;date&gt;			09-Jun-2022</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;CoefType&gt;		Blur &amp; Scale LPF</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t filter_isharp_bs_3tap_64p[99] = {</div><div class='add'>+0x0200, 0x0200, 0x0000,</div><div class='add'>+0x01F6, 0x0206, 0x0004,</div><div class='add'>+0x01EC, 0x020B, 0x0009,</div><div class='add'>+0x01E2, 0x0211, 0x000D,</div><div class='add'>+0x01D8, 0x0216, 0x0012,</div><div class='add'>+0x01CE, 0x021C, 0x0016,</div><div class='add'>+0x01C4, 0x0221, 0x001B,</div><div class='add'>+0x01BA, 0x0226, 0x0020,</div><div class='add'>+0x01B0, 0x022A, 0x0026,</div><div class='add'>+0x01A6, 0x022F, 0x002B,</div><div class='add'>+0x019C, 0x0233, 0x0031,</div><div class='add'>+0x0192, 0x0238, 0x0036,</div><div class='add'>+0x0188, 0x023C, 0x003C,</div><div class='add'>+0x017E, 0x0240, 0x0042,</div><div class='add'>+0x0174, 0x0244, 0x0048,</div><div class='add'>+0x016A, 0x0248, 0x004E,</div><div class='add'>+0x0161, 0x024A, 0x0055,</div><div class='add'>+0x0157, 0x024E, 0x005B,</div><div class='add'>+0x014D, 0x0251, 0x0062,</div><div class='add'>+0x0144, 0x0253, 0x0069,</div><div class='add'>+0x013A, 0x0256, 0x0070,</div><div class='add'>+0x0131, 0x0258, 0x0077,</div><div class='add'>+0x0127, 0x025B, 0x007E,</div><div class='add'>+0x011E, 0x025C, 0x0086,</div><div class='add'>+0x0115, 0x025E, 0x008D,</div><div class='add'>+0x010B, 0x0260, 0x0095,</div><div class='add'>+0x0102, 0x0262, 0x009C,</div><div class='add'>+0x00F9, 0x0263, 0x00A4,</div><div class='add'>+0x00F0, 0x0264, 0x00AC,</div><div class='add'>+0x00E7, 0x0265, 0x00B4,</div><div class='add'>+0x00DF, 0x0264, 0x00BD,</div><div class='add'>+0x00D6, 0x0265, 0x00C5,</div><div class='add'>+0x00CD, 0x0266, 0x00CD,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Converted Blur &amp; Scale coeff tables from S1.10 to S1.12 */</div><div class='add'>+static const uint16_t filter_isharp_bs_4tap_in_6_64p_s1_12[198] = {</div><div class='add'>+0x0000, 0x0394, 0x08dc, 0x0390, 0x0000, 0x0000,</div><div class='add'>+0x0000, 0x0378, 0x08dc, 0x03ac, 0x0000, 0x0000,</div><div class='add'>+0x0000, 0x035c, 0x08d8, 0x03c8, 0x0004, 0x0000,</div><div class='add'>+0x0000, 0x0340, 0x08d4, 0x03e8, 0x0004, 0x0000,</div><div class='add'>+0x0000, 0x0324, 0x08d0, 0x0404, 0x0008, 0x0000,</div><div class='add'>+0x0000, 0x0308, 0x08cc, 0x0420, 0x000c, 0x0000,</div><div class='add'>+0x0000, 0x02ec, 0x08c8, 0x0440, 0x000c, 0x0000,</div><div class='add'>+0x0000, 0x02d4, 0x08c0, 0x045c, 0x0010, 0x0000,</div><div class='add'>+0x0000, 0x02b8, 0x08b8, 0x047c, 0x0014, 0x0000,</div><div class='add'>+0x0000, 0x02a0, 0x08b0, 0x0498, 0x0018, 0x0000,</div><div class='add'>+0x0000, 0x0288, 0x08a8, 0x04b4, 0x001c, 0x0000,</div><div class='add'>+0x0000, 0x0270, 0x08a0, 0x04d0, 0x0020, 0x0000,</div><div class='add'>+0x0000, 0x0258, 0x0894, 0x04f0, 0x0024, 0x0000,</div><div class='add'>+0x0000, 0x0240, 0x0888, 0x050c, 0x002c, 0x0000,</div><div class='add'>+0x0000, 0x0228, 0x087c, 0x052c, 0x0030, 0x0000,</div><div class='add'>+0x0000, 0x0214, 0x0870, 0x0544, 0x0038, 0x0000,</div><div class='add'>+0x0000, 0x01fc, 0x0860, 0x0568, 0x003c, 0x0000,</div><div class='add'>+0x0000, 0x01e8, 0x0854, 0x0580, 0x0044, 0x0000,</div><div class='add'>+0x0000, 0x01d0, 0x0844, 0x05a0, 0x004c, 0x0000,</div><div class='add'>+0x0000, 0x01bc, 0x0834, 0x05bc, 0x0054, 0x0000,</div><div class='add'>+0x0000, 0x01a8, 0x0824, 0x05d8, 0x005c, 0x0000,</div><div class='add'>+0x0000, 0x0194, 0x0810, 0x05f8, 0x0064, 0x0000,</div><div class='add'>+0x0000, 0x0180, 0x0800, 0x0614, 0x006c, 0x0000,</div><div class='add'>+0x0000, 0x0170, 0x07ec, 0x0630, 0x0074, 0x0000,</div><div class='add'>+0x0000, 0x015c, 0x07d8, 0x064c, 0x0080, 0x0000,</div><div class='add'>+0x0000, 0x014c, 0x07c4, 0x0668, 0x0088, 0x0000,</div><div class='add'>+0x0000, 0x0138, 0x07b0, 0x0684, 0x0094, 0x0000,</div><div class='add'>+0x0000, 0x0128, 0x0798, 0x06a0, 0x00a0, 0x0000,</div><div class='add'>+0x0000, 0x0118, 0x0784, 0x06bc, 0x00a8, 0x0000,</div><div class='add'>+0x0000, 0x0108, 0x076c, 0x06d8, 0x00b4, 0x0000,</div><div class='add'>+0x0000, 0x00fc, 0x0754, 0x06ec, 0x00c4, 0x0000,</div><div class='add'>+0x0000, 0x00ec, 0x073c, 0x0708, 0x00d0, 0x0000,</div><div class='add'>+0x0000, 0x00dc, 0x0724, 0x0724, 0x00dc, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t filter_isharp_bs_4tap_64p_s1_12[132] = {</div><div class='add'>+0x0394, 0x08dc, 0x0390, 0x0000,</div><div class='add'>+0x0378, 0x08dc, 0x03ac, 0x0000,</div><div class='add'>+0x035c, 0x08d8, 0x03c8, 0x0004,</div><div class='add'>+0x0340, 0x08d4, 0x03e8, 0x0004,</div><div class='add'>+0x0324, 0x08d0, 0x0404, 0x0008,</div><div class='add'>+0x0308, 0x08cc, 0x0420, 0x000c,</div><div class='add'>+0x02ec, 0x08c8, 0x0440, 0x000c,</div><div class='add'>+0x02d4, 0x08c0, 0x045c, 0x0010,</div><div class='add'>+0x02b8, 0x08b8, 0x047c, 0x0014,</div><div class='add'>+0x02a0, 0x08b0, 0x0498, 0x0018,</div><div class='add'>+0x0288, 0x08a8, 0x04b4, 0x001c,</div><div class='add'>+0x0270, 0x08a0, 0x04d0, 0x0020,</div><div class='add'>+0x0258, 0x0894, 0x04f0, 0x0024,</div><div class='add'>+0x0240, 0x0888, 0x050c, 0x002c,</div><div class='add'>+0x0228, 0x087c, 0x052c, 0x0030,</div><div class='add'>+0x0214, 0x0870, 0x0544, 0x0038,</div><div class='add'>+0x01fc, 0x0860, 0x0568, 0x003c,</div><div class='add'>+0x01e8, 0x0854, 0x0580, 0x0044,</div><div class='add'>+0x01d0, 0x0844, 0x05a0, 0x004c,</div><div class='add'>+0x01bc, 0x0834, 0x05bc, 0x0054,</div><div class='add'>+0x01a8, 0x0824, 0x05d8, 0x005c,</div><div class='add'>+0x0194, 0x0810, 0x05f8, 0x0064,</div><div class='add'>+0x0180, 0x0800, 0x0614, 0x006c,</div><div class='add'>+0x0170, 0x07ec, 0x0630, 0x0074,</div><div class='add'>+0x015c, 0x07d8, 0x064c, 0x0080,</div><div class='add'>+0x014c, 0x07c4, 0x0668, 0x0088,</div><div class='add'>+0x0138, 0x07b0, 0x0684, 0x0094,</div><div class='add'>+0x0128, 0x0798, 0x06a0, 0x00a0,</div><div class='add'>+0x0118, 0x0784, 0x06bc, 0x00a8,</div><div class='add'>+0x0108, 0x076c, 0x06d8, 0x00b4,</div><div class='add'>+0x00fc, 0x0754, 0x06ec, 0x00c4,</div><div class='add'>+0x00ec, 0x073c, 0x0708, 0x00d0,</div><div class='add'>+0x00dc, 0x0724, 0x0724, 0x00dc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t filter_isharp_bs_3tap_64p_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07d8, 0x0818, 0x0010,</div><div class='add'>+0x07b0, 0x082c, 0x0024,</div><div class='add'>+0x0788, 0x0844, 0x0034,</div><div class='add'>+0x0760, 0x0858, 0x0048,</div><div class='add'>+0x0738, 0x0870, 0x0058,</div><div class='add'>+0x0710, 0x0884, 0x006c,</div><div class='add'>+0x06e8, 0x0898, 0x0080,</div><div class='add'>+0x06c0, 0x08a8, 0x0098,</div><div class='add'>+0x0698, 0x08bc, 0x00ac,</div><div class='add'>+0x0670, 0x08cc, 0x00c4,</div><div class='add'>+0x0648, 0x08e0, 0x00d8,</div><div class='add'>+0x0620, 0x08f0, 0x00f0,</div><div class='add'>+0x05f8, 0x0900, 0x0108,</div><div class='add'>+0x05d0, 0x0910, 0x0120,</div><div class='add'>+0x05a8, 0x0920, 0x0138,</div><div class='add'>+0x0584, 0x0928, 0x0154,</div><div class='add'>+0x055c, 0x0938, 0x016c,</div><div class='add'>+0x0534, 0x0944, 0x0188,</div><div class='add'>+0x0510, 0x094c, 0x01a4,</div><div class='add'>+0x04e8, 0x0958, 0x01c0,</div><div class='add'>+0x04c4, 0x0960, 0x01dc,</div><div class='add'>+0x049c, 0x096c, 0x01f8,</div><div class='add'>+0x0478, 0x0970, 0x0218,</div><div class='add'>+0x0454, 0x0978, 0x0234,</div><div class='add'>+0x042c, 0x0980, 0x0254,</div><div class='add'>+0x0408, 0x0988, 0x0270,</div><div class='add'>+0x03e4, 0x098c, 0x0290,</div><div class='add'>+0x03c0, 0x0990, 0x02b0,</div><div class='add'>+0x039c, 0x0994, 0x02d0,</div><div class='add'>+0x037c, 0x0990, 0x02f4,</div><div class='add'>+0x0358, 0x0994, 0x0314,</div><div class='add'>+0x0334, 0x0998, 0x0334,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Pre-generated 1DLUT for given setup and sharpness level */</div><div class='add'>+struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = {</div><div class='add'>+	{</div><div class='add'>+		0, 0,</div><div class='add'>+		{</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		0, 0,</div><div class='add'>+		{</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		0, 0,</div><div class='add'>+		{</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		0, 0,</div><div class='add'>+		{</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+			0, 0, 0, 0, 0, 0, 0, 0,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = {</div><div class='add'>+	{1125, 1000, 0},</div><div class='add'>+	{11, 10, 1},</div><div class='add'>+	{1075, 1000, 2},</div><div class='add'>+	{105, 100, 3},</div><div class='add'>+	{1025, 1000, 4},</div><div class='add'>+	{1, 1, 5},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static unsigned int spl_calculate_sharpness_level_adj(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	int j;</div><div class='add'>+	struct spl_fixed31_32 ratio_level;</div><div class='add'>+	struct scale_ratio_to_sharpness_level_adj *lookup_ptr;</div><div class='add'>+	unsigned int sharpness_level_down_adj;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Adjust sharpness level based on current scaling ratio</div><div class='add'>+	 *</div><div class='add'>+	 * We have 5 discrete scaling ratios which we will use to adjust the</div><div class='add'>+	 *  sharpness level down by 1 as we pass each ratio.  The ratios</div><div class='add'>+	 *  are</div><div class='add'>+	 *</div><div class='add'>+	 * 1.125 upscale and higher - no adj</div><div class='add'>+	 * 1.100 - under 1.125 - adj level down 1</div><div class='add'>+	 * 1.075 - under 1.100 - adj level down 2</div><div class='add'>+	 * 1.050 - under 1.075 - adj level down 3</div><div class='add'>+	 * 1.025 - under 1.050 - adj level down 4</div><div class='add'>+	 * 1.000 - under 1.025 - adj level down 5</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='add'>+	j = 0;</div><div class='add'>+	sharpness_level_down_adj = 0;</div><div class='add'>+	lookup_ptr = sharpness_level_adj;</div><div class='add'>+	while (j &lt; NUM_SHARPNESS_ADJ_LEVELS) {</div><div class='add'>+		ratio_level = spl_fixpt_from_fraction(lookup_ptr-&gt;ratio_numer,</div><div class='add'>+			lookup_ptr-&gt;ratio_denom);</div><div class='add'>+		if (ratio.value &gt;= ratio_level.value) {</div><div class='add'>+			sharpness_level_down_adj = lookup_ptr-&gt;level_down_adj;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		lookup_ptr++;</div><div class='add'>+		j++;</div><div class='add'>+	}</div><div class='add'>+	return sharpness_level_down_adj;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int spl_calculate_sharpness_level(struct spl_fixed31_32 ratio,</div><div class='add'>+		unsigned int discrete_sharpness_level, enum system_setup setup,</div><div class='add'>+		struct spl_sharpness_range sharpness_range,</div><div class='add'>+		enum scale_to_sharpness_policy scale_to_sharpness_policy)</div><div class='add'>+{</div><div class='add'>+	unsigned int sharpness_level = 0;</div><div class='add'>+	unsigned int sharpness_level_down_adj = 0;</div><div class='add'>+</div><div class='add'>+	int min_sharpness, max_sharpness, mid_sharpness;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Adjust sharpness level if policy requires we adjust it based on</div><div class='add'>+	 *  scale ratio.  Based on scale ratio, we may adjust the sharpness</div><div class='add'>+	 *  level down by a certain number of steps.  We will not select</div><div class='add'>+	 *  a sharpness value of 0 so the lowest sharpness level will be</div><div class='add'>+	 *  0 or 1 depending on what the min_sharpness is</div><div class='add'>+	 *</div><div class='add'>+	 * If the policy is no required, this code maybe removed at a later</div><div class='add'>+	 *  date</div><div class='add'>+	 */</div><div class='add'>+	switch (setup) {</div><div class='add'>+</div><div class='add'>+	case HDR_L:</div><div class='add'>+		min_sharpness = sharpness_range.hdr_rgb_min;</div><div class='add'>+		max_sharpness = sharpness_range.hdr_rgb_max;</div><div class='add'>+		mid_sharpness = sharpness_range.hdr_rgb_mid;</div><div class='add'>+		if (scale_to_sharpness_policy == SCALE_TO_SHARPNESS_ADJ_ALL)</div><div class='add'>+			sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio);</div><div class='add'>+		break;</div><div class='add'>+	case HDR_NL:</div><div class='add'>+		/* currently no use case, use Non-linear SDR values for now */</div><div class='add'>+	case SDR_NL:</div><div class='add'>+		min_sharpness = sharpness_range.sdr_yuv_min;</div><div class='add'>+		max_sharpness = sharpness_range.sdr_yuv_max;</div><div class='add'>+		mid_sharpness = sharpness_range.sdr_yuv_mid;</div><div class='add'>+		if (scale_to_sharpness_policy &gt;= SCALE_TO_SHARPNESS_ADJ_YUV)</div><div class='add'>+			sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio);</div><div class='add'>+		break;</div><div class='add'>+	case SDR_L:</div><div class='add'>+	default:</div><div class='add'>+		min_sharpness = sharpness_range.sdr_rgb_min;</div><div class='add'>+		max_sharpness = sharpness_range.sdr_rgb_max;</div><div class='add'>+		mid_sharpness = sharpness_range.sdr_rgb_mid;</div><div class='add'>+		if (scale_to_sharpness_policy == SCALE_TO_SHARPNESS_ADJ_ALL)</div><div class='add'>+			sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((min_sharpness == 0) &amp;&amp; (sharpness_level_down_adj &gt;= discrete_sharpness_level))</div><div class='add'>+		discrete_sharpness_level = 1;</div><div class='add'>+	else if (sharpness_level_down_adj &gt;= discrete_sharpness_level)</div><div class='add'>+		discrete_sharpness_level = 0;</div><div class='add'>+	else</div><div class='add'>+		discrete_sharpness_level -= sharpness_level_down_adj;</div><div class='add'>+</div><div class='add'>+	int lower_half_step_size = (mid_sharpness - min_sharpness) / 5;</div><div class='add'>+	int upper_half_step_size = (max_sharpness - mid_sharpness) / 5;</div><div class='add'>+</div><div class='add'>+	// lower half linear approximation</div><div class='add'>+	if (discrete_sharpness_level &lt; 5)</div><div class='add'>+		sharpness_level = min_sharpness + (lower_half_step_size * discrete_sharpness_level);</div><div class='add'>+	// upper half linear approximation</div><div class='add'>+	else</div><div class='add'>+		sharpness_level = mid_sharpness + (upper_half_step_size * (discrete_sharpness_level - 5));</div><div class='add'>+</div><div class='add'>+	return sharpness_level;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup,</div><div class='add'>+	struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy)</div><div class='add'>+{</div><div class='add'>+	uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst;</div><div class='add'>+	struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level;</div><div class='add'>+	int j;</div><div class='add'>+	int size_1dlut;</div><div class='add'>+	int sharp_calc_int;</div><div class='add'>+	uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE];</div><div class='add'>+</div><div class='add'>+	/* Custom sharpnessX1000 value */</div><div class='add'>+	unsigned int sharpnessX1000 = spl_calculate_sharpness_level(ratio,</div><div class='add'>+			sharpness.sharpness_level, setup,</div><div class='add'>+			sharpness.sharpness_range, scale_to_sharpness_policy);</div><div class='add'>+	sharp_level = spl_fixpt_from_fraction(sharpnessX1000, 1000);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check if pregen 1dlut table is already precalculated</div><div class='add'>+	 * If numer/denom is different, then recalculate</div><div class='add'>+	 */</div><div class='add'>+	if ((filter_isharp_1D_lut_pregen[setup].sharpness_numer == sharpnessX1000) &amp;&amp;</div><div class='add'>+		(filter_isharp_1D_lut_pregen[setup].sharpness_denom == 1000))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Calculate LUT_128_gained with this equation:</div><div class='add'>+	 *</div><div class='add'>+	 * LUT_128_gained[i] = (uint8)(0.5 + min(255,(double)(LUT_128[i])*sharpLevel/iGain))</div><div class='add'>+	 *  where LUT_128[i] is contents of 3p0x isharp 1dlut</div><div class='add'>+	 *  where sharpLevel is desired sharpness level</div><div class='add'>+	 *  where iGain is base sharpness level 3.0</div><div class='add'>+	 *  where LUT_128_gained[i] is adjusted 1dlut value based on desired sharpness level</div><div class='add'>+	 */</div><div class='add'>+	byte_ptr_1dlut_src = (uint8_t *)filter_isharp_1D_lut_3p0x;</div><div class='add'>+	byte_ptr_1dlut_dst = (uint8_t *)filter_pregen_store;</div><div class='add'>+	size_1dlut = sizeof(filter_isharp_1D_lut_3p0x);</div><div class='add'>+	memset(byte_ptr_1dlut_dst, 0, size_1dlut);</div><div class='add'>+	for (j = 0; j &lt; size_1dlut; j++) {</div><div class='add'>+		sharp_base = spl_fixpt_from_int((int)*byte_ptr_1dlut_src);</div><div class='add'>+		sharp_calc = spl_fixpt_mul(sharp_base, sharp_level);</div><div class='add'>+		sharp_calc = spl_fixpt_div(sharp_calc, spl_fixpt_from_int(3));</div><div class='add'>+		sharp_calc = spl_fixpt_min(spl_fixpt_from_int(255), sharp_calc);</div><div class='add'>+		sharp_calc = spl_fixpt_add(sharp_calc, spl_fixpt_from_fraction(1, 2));</div><div class='add'>+		sharp_calc_int = spl_fixpt_floor(sharp_calc);</div><div class='add'>+		/* Clamp it at 0x7F so it doesn't wrap */</div><div class='add'>+		if (sharp_calc_int &gt; 127)</div><div class='add'>+			sharp_calc_int = 127;</div><div class='add'>+		*byte_ptr_1dlut_dst = (uint8_t)sharp_calc_int;</div><div class='add'>+</div><div class='add'>+		byte_ptr_1dlut_src++;</div><div class='add'>+		byte_ptr_1dlut_dst++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update 1dlut table and sharpness level */</div><div class='add'>+	memcpy((void *)filter_isharp_1D_lut_pregen[setup].value, (void *)filter_pregen_store, size_1dlut);</div><div class='add'>+	filter_isharp_1D_lut_pregen[setup].sharpness_numer = sharpnessX1000;</div><div class='add'>+	filter_isharp_1D_lut_pregen[setup].sharpness_denom = 1000;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup)</div><div class='add'>+{</div><div class='add'>+	return filter_isharp_1D_lut_pregen[setup].value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps)</div><div class='add'>+{</div><div class='add'>+	if (taps == 3)</div><div class='add'>+		return filter_isharp_bs_3tap_64p_s1_12;</div><div class='add'>+	else if (taps == 4)</div><div class='add'>+		return filter_isharp_bs_4tap_64p_s1_12;</div><div class='add'>+	else if (taps == 6)</div><div class='add'>+		return filter_isharp_bs_4tap_in_6_64p_s1_12;</div><div class='add'>+	else {</div><div class='add'>+		/* should never happen, bug */</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps)</div><div class='add'>+{</div><div class='add'>+	if (taps == 3)</div><div class='add'>+		return filter_isharp_bs_3tap_64p;</div><div class='add'>+	else if (taps == 4)</div><div class='add'>+		return filter_isharp_bs_4tap_64p;</div><div class='add'>+	else if (taps == 6)</div><div class='add'>+		return filter_isharp_bs_4tap_in_6_64p;</div><div class='add'>+	else {</div><div class='add'>+		/* should never happen, bug */</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+		const struct spl_scaler_data *data)</div><div class='add'>+{</div><div class='add'>+	dscl_prog_data-&gt;filter_blur_scale_h =</div><div class='add'>+		spl_dscl_get_blur_scale_coeffs_64p(data-&gt;taps.h_taps);</div><div class='add'>+</div><div class='add'>+	dscl_prog_data-&gt;filter_blur_scale_v =</div><div class='add'>+		spl_dscl_get_blur_scale_coeffs_64p(data-&gt;taps.v_taps);</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h<br/>new file mode 100644<br/>index 000000000000..f5e3d3ecc913<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_ISHARP_FILTERS_H__</div><div class='add'>+#define __DC_SPL_ISHARP_FILTERS_H__</div><div class='add'>+</div><div class='add'>+#include "dc_spl_types.h"</div><div class='add'>+</div><div class='add'>+#define NUM_SHARPNESS_ADJ_LEVELS 6</div><div class='add'>+struct scale_ratio_to_sharpness_level_adj {</div><div class='add'>+	unsigned int ratio_numer;</div><div class='add'>+	unsigned int ratio_denom;</div><div class='add'>+	unsigned int level_down_adj; /* adjust sharpness level down */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct isharp_1D_lut_pregen {</div><div class='add'>+	unsigned int sharpness_numer;</div><div class='add'>+	unsigned int sharpness_denom;</div><div class='add'>+	uint32_t value[ISHARP_LUT_TABLE_SIZE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum system_setup {</div><div class='add'>+	SDR_NL = 0,</div><div class='add'>+	SDR_L,</div><div class='add'>+	HDR_NL,</div><div class='add'>+	HDR_L,</div><div class='add'>+	NUM_SHARPNESS_SETUPS</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+	const struct spl_scaler_data *data);</div><div class='add'>+</div><div class='add'>+void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup,</div><div class='add'>+	struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy);</div><div class='add'>+uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup);</div><div class='add'>+</div><div class='add'>+// public API</div><div class='add'>+const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps);</div><div class='add'>+const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_ISHARP_FILTERS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c<br/>new file mode 100644<br/>index 000000000000..0d1bd81ff04a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c</a></div><div class='hunk'>@@ -0,0 +1,2586 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+#include "dc_spl_filters.h"</div><div class='add'>+#include "dc_spl_scl_filters.h"</div><div class='add'>+#include "dc_spl_scl_easf_filters.h"</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.3_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.300000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_30[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01F6, 0x0206, 0x0004,</div><div class='add'>+	0x01EC, 0x020B, 0x0009,</div><div class='add'>+	0x01E2, 0x0211, 0x000D,</div><div class='add'>+	0x01D8, 0x0216, 0x0012,</div><div class='add'>+	0x01CE, 0x021C, 0x0016,</div><div class='add'>+	0x01C4, 0x0221, 0x001B,</div><div class='add'>+	0x01BA, 0x0226, 0x0020,</div><div class='add'>+	0x01B0, 0x022A, 0x0026,</div><div class='add'>+	0x01A6, 0x022F, 0x002B,</div><div class='add'>+	0x019C, 0x0233, 0x0031,</div><div class='add'>+	0x0192, 0x0238, 0x0036,</div><div class='add'>+	0x0188, 0x023C, 0x003C,</div><div class='add'>+	0x017E, 0x0240, 0x0042,</div><div class='add'>+	0x0174, 0x0244, 0x0048,</div><div class='add'>+	0x016A, 0x0248, 0x004E,</div><div class='add'>+	0x0161, 0x024A, 0x0055,</div><div class='add'>+	0x0157, 0x024E, 0x005B,</div><div class='add'>+	0x014D, 0x0251, 0x0062,</div><div class='add'>+	0x0144, 0x0253, 0x0069,</div><div class='add'>+	0x013A, 0x0256, 0x0070,</div><div class='add'>+	0x0131, 0x0258, 0x0077,</div><div class='add'>+	0x0127, 0x025B, 0x007E,</div><div class='add'>+	0x011E, 0x025C, 0x0086,</div><div class='add'>+	0x0115, 0x025E, 0x008D,</div><div class='add'>+	0x010B, 0x0260, 0x0095,</div><div class='add'>+	0x0102, 0x0262, 0x009C,</div><div class='add'>+	0x00F9, 0x0263, 0x00A4,</div><div class='add'>+	0x00F0, 0x0264, 0x00AC,</div><div class='add'>+	0x00E7, 0x0265, 0x00B4,</div><div class='add'>+	0x00DF, 0x0264, 0x00BD,</div><div class='add'>+	0x00D6, 0x0265, 0x00C5,</div><div class='add'>+	0x00CD, 0x0266, 0x00CD,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.4_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.400000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_40[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01F6, 0x0206, 0x0004,</div><div class='add'>+	0x01EB, 0x020E, 0x0007,</div><div class='add'>+	0x01E1, 0x0214, 0x000B,</div><div class='add'>+	0x01D7, 0x021A, 0x000F,</div><div class='add'>+	0x01CD, 0x0220, 0x0013,</div><div class='add'>+	0x01C2, 0x0226, 0x0018,</div><div class='add'>+	0x01B8, 0x022C, 0x001C,</div><div class='add'>+	0x01AE, 0x0231, 0x0021,</div><div class='add'>+	0x01A3, 0x0237, 0x0026,</div><div class='add'>+	0x0199, 0x023C, 0x002B,</div><div class='add'>+	0x018F, 0x0240, 0x0031,</div><div class='add'>+	0x0185, 0x0245, 0x0036,</div><div class='add'>+	0x017A, 0x024A, 0x003C,</div><div class='add'>+	0x0170, 0x024F, 0x0041,</div><div class='add'>+	0x0166, 0x0253, 0x0047,</div><div class='add'>+	0x015C, 0x0257, 0x004D,</div><div class='add'>+	0x0152, 0x025A, 0x0054,</div><div class='add'>+	0x0148, 0x025E, 0x005A,</div><div class='add'>+	0x013E, 0x0261, 0x0061,</div><div class='add'>+	0x0134, 0x0264, 0x0068,</div><div class='add'>+	0x012B, 0x0266, 0x006F,</div><div class='add'>+	0x0121, 0x0269, 0x0076,</div><div class='add'>+	0x0117, 0x026C, 0x007D,</div><div class='add'>+	0x010E, 0x026E, 0x0084,</div><div class='add'>+	0x0104, 0x0270, 0x008C,</div><div class='add'>+	0x00FB, 0x0271, 0x0094,</div><div class='add'>+	0x00F2, 0x0272, 0x009C,</div><div class='add'>+	0x00E9, 0x0273, 0x00A4,</div><div class='add'>+	0x00E0, 0x0274, 0x00AC,</div><div class='add'>+	0x00D7, 0x0275, 0x00B4,</div><div class='add'>+	0x00CE, 0x0275, 0x00BD,</div><div class='add'>+	0x00C5, 0x0276, 0x00C5,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.5_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.500000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_50[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01F5, 0x0209, 0x0002,</div><div class='add'>+	0x01EA, 0x0211, 0x0005,</div><div class='add'>+	0x01DF, 0x021A, 0x0007,</div><div class='add'>+	0x01D4, 0x0222, 0x000A,</div><div class='add'>+	0x01C9, 0x022A, 0x000D,</div><div class='add'>+	0x01BE, 0x0232, 0x0010,</div><div class='add'>+	0x01B3, 0x0239, 0x0014,</div><div class='add'>+	0x01A8, 0x0241, 0x0017,</div><div class='add'>+	0x019D, 0x0248, 0x001B,</div><div class='add'>+	0x0192, 0x024F, 0x001F,</div><div class='add'>+	0x0187, 0x0255, 0x0024,</div><div class='add'>+	0x017C, 0x025C, 0x0028,</div><div class='add'>+	0x0171, 0x0262, 0x002D,</div><div class='add'>+	0x0166, 0x0268, 0x0032,</div><div class='add'>+	0x015B, 0x026E, 0x0037,</div><div class='add'>+	0x0150, 0x0273, 0x003D,</div><div class='add'>+	0x0146, 0x0278, 0x0042,</div><div class='add'>+	0x013B, 0x027D, 0x0048,</div><div class='add'>+	0x0130, 0x0282, 0x004E,</div><div class='add'>+	0x0126, 0x0286, 0x0054,</div><div class='add'>+	0x011B, 0x028A, 0x005B,</div><div class='add'>+	0x0111, 0x028D, 0x0062,</div><div class='add'>+	0x0107, 0x0290, 0x0069,</div><div class='add'>+	0x00FD, 0x0293, 0x0070,</div><div class='add'>+	0x00F3, 0x0296, 0x0077,</div><div class='add'>+	0x00E9, 0x0298, 0x007F,</div><div class='add'>+	0x00DF, 0x029A, 0x0087,</div><div class='add'>+	0x00D5, 0x029C, 0x008F,</div><div class='add'>+	0x00CC, 0x029D, 0x0097,</div><div class='add'>+	0x00C3, 0x029E, 0x009F,</div><div class='add'>+	0x00BA, 0x029E, 0x00A8,</div><div class='add'>+	0x00B1, 0x029E, 0x00B1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.6_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.600000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_60[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01F4, 0x020B, 0x0001,</div><div class='add'>+	0x01E8, 0x0216, 0x0002,</div><div class='add'>+	0x01DC, 0x0221, 0x0003,</div><div class='add'>+	0x01D0, 0x022B, 0x0005,</div><div class='add'>+	0x01C4, 0x0235, 0x0007,</div><div class='add'>+	0x01B8, 0x0240, 0x0008,</div><div class='add'>+	0x01AC, 0x0249, 0x000B,</div><div class='add'>+	0x01A0, 0x0253, 0x000D,</div><div class='add'>+	0x0194, 0x025C, 0x0010,</div><div class='add'>+	0x0188, 0x0265, 0x0013,</div><div class='add'>+	0x017C, 0x026E, 0x0016,</div><div class='add'>+	0x0170, 0x0277, 0x0019,</div><div class='add'>+	0x0164, 0x027F, 0x001D,</div><div class='add'>+	0x0158, 0x0287, 0x0021,</div><div class='add'>+	0x014C, 0x028F, 0x0025,</div><div class='add'>+	0x0140, 0x0297, 0x0029,</div><div class='add'>+	0x0135, 0x029D, 0x002E,</div><div class='add'>+	0x0129, 0x02A4, 0x0033,</div><div class='add'>+	0x011D, 0x02AB, 0x0038,</div><div class='add'>+	0x0112, 0x02B0, 0x003E,</div><div class='add'>+	0x0107, 0x02B5, 0x0044,</div><div class='add'>+	0x00FC, 0x02BA, 0x004A,</div><div class='add'>+	0x00F1, 0x02BF, 0x0050,</div><div class='add'>+	0x00E6, 0x02C3, 0x0057,</div><div class='add'>+	0x00DB, 0x02C7, 0x005E,</div><div class='add'>+	0x00D1, 0x02CA, 0x0065,</div><div class='add'>+	0x00C7, 0x02CC, 0x006D,</div><div class='add'>+	0x00BD, 0x02CE, 0x0075,</div><div class='add'>+	0x00B3, 0x02D0, 0x007D,</div><div class='add'>+	0x00A9, 0x02D2, 0x0085,</div><div class='add'>+	0x00A0, 0x02D2, 0x008E,</div><div class='add'>+	0x0097, 0x02D2, 0x0097,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.7_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.700000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_70[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01F3, 0x020D, 0x0000,</div><div class='add'>+	0x01E5, 0x021B, 0x0000,</div><div class='add'>+	0x01D8, 0x0228, 0x0000,</div><div class='add'>+	0x01CB, 0x0235, 0x0000,</div><div class='add'>+	0x01BD, 0x0243, 0x0000,</div><div class='add'>+	0x01B0, 0x024F, 0x0001,</div><div class='add'>+	0x01A2, 0x025C, 0x0002,</div><div class='add'>+	0x0195, 0x0268, 0x0003,</div><div class='add'>+	0x0187, 0x0275, 0x0004,</div><div class='add'>+	0x017A, 0x0280, 0x0006,</div><div class='add'>+	0x016D, 0x028C, 0x0007,</div><div class='add'>+	0x015F, 0x0298, 0x0009,</div><div class='add'>+	0x0152, 0x02A2, 0x000C,</div><div class='add'>+	0x0145, 0x02AD, 0x000E,</div><div class='add'>+	0x0138, 0x02B7, 0x0011,</div><div class='add'>+	0x012B, 0x02C0, 0x0015,</div><div class='add'>+	0x011E, 0x02CA, 0x0018,</div><div class='add'>+	0x0111, 0x02D3, 0x001C,</div><div class='add'>+	0x0105, 0x02DB, 0x0020,</div><div class='add'>+	0x00F8, 0x02E3, 0x0025,</div><div class='add'>+	0x00EC, 0x02EA, 0x002A,</div><div class='add'>+	0x00E0, 0x02F1, 0x002F,</div><div class='add'>+	0x00D5, 0x02F6, 0x0035,</div><div class='add'>+	0x00C9, 0x02FC, 0x003B,</div><div class='add'>+	0x00BE, 0x0301, 0x0041,</div><div class='add'>+	0x00B3, 0x0305, 0x0048,</div><div class='add'>+	0x00A8, 0x0309, 0x004F,</div><div class='add'>+	0x009E, 0x030C, 0x0056,</div><div class='add'>+	0x0094, 0x030E, 0x005E,</div><div class='add'>+	0x008A, 0x0310, 0x0066,</div><div class='add'>+	0x0081, 0x0310, 0x006F,</div><div class='add'>+	0x0077, 0x0312, 0x0077,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.8_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.800000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_80[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01F1, 0x0210, 0x0FFF,</div><div class='add'>+	0x01E2, 0x0220, 0x0FFE,</div><div class='add'>+	0x01D2, 0x0232, 0x0FFC,</div><div class='add'>+	0x01C3, 0x0241, 0x0FFC,</div><div class='add'>+	0x01B4, 0x0251, 0x0FFB,</div><div class='add'>+	0x01A4, 0x0262, 0x0FFA,</div><div class='add'>+	0x0195, 0x0271, 0x0FFA,</div><div class='add'>+	0x0186, 0x0281, 0x0FF9,</div><div class='add'>+	0x0176, 0x0291, 0x0FF9,</div><div class='add'>+	0x0167, 0x02A0, 0x0FF9,</div><div class='add'>+	0x0158, 0x02AE, 0x0FFA,</div><div class='add'>+	0x0149, 0x02BD, 0x0FFA,</div><div class='add'>+	0x013A, 0x02CB, 0x0FFB,</div><div class='add'>+	0x012C, 0x02D7, 0x0FFD,</div><div class='add'>+	0x011D, 0x02E5, 0x0FFE,</div><div class='add'>+	0x010F, 0x02F1, 0x0000,</div><div class='add'>+	0x0101, 0x02FD, 0x0002,</div><div class='add'>+	0x00F3, 0x0308, 0x0005,</div><div class='add'>+	0x00E5, 0x0313, 0x0008,</div><div class='add'>+	0x00D8, 0x031D, 0x000B,</div><div class='add'>+	0x00CB, 0x0326, 0x000F,</div><div class='add'>+	0x00BE, 0x032F, 0x0013,</div><div class='add'>+	0x00B2, 0x0337, 0x0017,</div><div class='add'>+	0x00A6, 0x033E, 0x001C,</div><div class='add'>+	0x009A, 0x0345, 0x0021,</div><div class='add'>+	0x008F, 0x034A, 0x0027,</div><div class='add'>+	0x0084, 0x034F, 0x002D,</div><div class='add'>+	0x0079, 0x0353, 0x0034,</div><div class='add'>+	0x006F, 0x0356, 0x003B,</div><div class='add'>+	0x0065, 0x0358, 0x0043,</div><div class='add'>+	0x005C, 0x0359, 0x004B,</div><div class='add'>+	0x0053, 0x035A, 0x0053,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_0.9_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.900000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_90[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01EE, 0x0214, 0x0FFE,</div><div class='add'>+	0x01DC, 0x0228, 0x0FFC,</div><div class='add'>+	0x01CA, 0x023C, 0x0FFA,</div><div class='add'>+	0x01B9, 0x024F, 0x0FF8,</div><div class='add'>+	0x01A7, 0x0262, 0x0FF7,</div><div class='add'>+	0x0195, 0x0276, 0x0FF5,</div><div class='add'>+	0x0183, 0x028A, 0x0FF3,</div><div class='add'>+	0x0172, 0x029C, 0x0FF2,</div><div class='add'>+	0x0160, 0x02AF, 0x0FF1,</div><div class='add'>+	0x014F, 0x02C2, 0x0FEF,</div><div class='add'>+	0x013E, 0x02D4, 0x0FEE,</div><div class='add'>+	0x012D, 0x02E5, 0x0FEE,</div><div class='add'>+	0x011C, 0x02F7, 0x0FED,</div><div class='add'>+	0x010C, 0x0307, 0x0FED,</div><div class='add'>+	0x00FB, 0x0318, 0x0FED,</div><div class='add'>+	0x00EC, 0x0327, 0x0FED,</div><div class='add'>+	0x00DC, 0x0336, 0x0FEE,</div><div class='add'>+	0x00CD, 0x0344, 0x0FEF,</div><div class='add'>+	0x00BE, 0x0352, 0x0FF0,</div><div class='add'>+	0x00B0, 0x035E, 0x0FF2,</div><div class='add'>+	0x00A2, 0x036A, 0x0FF4,</div><div class='add'>+	0x0095, 0x0375, 0x0FF6,</div><div class='add'>+	0x0088, 0x037F, 0x0FF9,</div><div class='add'>+	0x007B, 0x0388, 0x0FFD,</div><div class='add'>+	0x006F, 0x0391, 0x0000,</div><div class='add'>+	0x0064, 0x0397, 0x0005,</div><div class='add'>+	0x0059, 0x039D, 0x000A,</div><div class='add'>+	0x004E, 0x03A3, 0x000F,</div><div class='add'>+	0x0045, 0x03A6, 0x0015,</div><div class='add'>+	0x003B, 0x03A9, 0x001C,</div><div class='add'>+	0x0033, 0x03AA, 0x0023,</div><div class='add'>+	0x002A, 0x03AC, 0x002A,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	3t_64p_LanczosEd_p_1_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		3</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 1.000000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_1_00[99] = {</div><div class='add'>+	0x0200, 0x0200, 0x0000,</div><div class='add'>+	0x01EB, 0x0217, 0x0FFE,</div><div class='add'>+	0x01D5, 0x022F, 0x0FFC,</div><div class='add'>+	0x01C0, 0x0247, 0x0FF9,</div><div class='add'>+	0x01AB, 0x025E, 0x0FF7,</div><div class='add'>+	0x0196, 0x0276, 0x0FF4,</div><div class='add'>+	0x0181, 0x028D, 0x0FF2,</div><div class='add'>+	0x016C, 0x02A5, 0x0FEF,</div><div class='add'>+	0x0158, 0x02BB, 0x0FED,</div><div class='add'>+	0x0144, 0x02D1, 0x0FEB,</div><div class='add'>+	0x0130, 0x02E8, 0x0FE8,</div><div class='add'>+	0x011C, 0x02FE, 0x0FE6,</div><div class='add'>+	0x0109, 0x0313, 0x0FE4,</div><div class='add'>+	0x00F6, 0x0328, 0x0FE2,</div><div class='add'>+	0x00E4, 0x033C, 0x0FE0,</div><div class='add'>+	0x00D2, 0x034F, 0x0FDF,</div><div class='add'>+	0x00C0, 0x0363, 0x0FDD,</div><div class='add'>+	0x00B0, 0x0374, 0x0FDC,</div><div class='add'>+	0x009F, 0x0385, 0x0FDC,</div><div class='add'>+	0x0090, 0x0395, 0x0FDB,</div><div class='add'>+	0x0081, 0x03A4, 0x0FDB,</div><div class='add'>+	0x0072, 0x03B3, 0x0FDB,</div><div class='add'>+	0x0064, 0x03C0, 0x0FDC,</div><div class='add'>+	0x0057, 0x03CC, 0x0FDD,</div><div class='add'>+	0x004B, 0x03D6, 0x0FDF,</div><div class='add'>+	0x003F, 0x03E0, 0x0FE1,</div><div class='add'>+	0x0034, 0x03E8, 0x0FE4,</div><div class='add'>+	0x002A, 0x03EF, 0x0FE7,</div><div class='add'>+	0x0020, 0x03F5, 0x0FEB,</div><div class='add'>+	0x0017, 0x03FA, 0x0FEF,</div><div class='add'>+	0x000F, 0x03FD, 0x0FF4,</div><div class='add'>+	0x0007, 0x03FF, 0x0FFA,</div><div class='add'>+	0x0000, 0x0400, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.3_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.300000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_30[132] = {</div><div class='add'>+	0x0104, 0x01F8, 0x0104, 0x0000,</div><div class='add'>+	0x00FE, 0x01F7, 0x010A, 0x0001,</div><div class='add'>+	0x00F8, 0x01F6, 0x010F, 0x0003,</div><div class='add'>+	0x00F2, 0x01F5, 0x0114, 0x0005,</div><div class='add'>+	0x00EB, 0x01F4, 0x011B, 0x0006,</div><div class='add'>+	0x00E5, 0x01F3, 0x0120, 0x0008,</div><div class='add'>+	0x00DF, 0x01F2, 0x0125, 0x000A,</div><div class='add'>+	0x00DA, 0x01F0, 0x012A, 0x000C,</div><div class='add'>+	0x00D4, 0x01EE, 0x0130, 0x000E,</div><div class='add'>+	0x00CE, 0x01ED, 0x0135, 0x0010,</div><div class='add'>+	0x00C8, 0x01EB, 0x013A, 0x0013,</div><div class='add'>+	0x00C2, 0x01E9, 0x0140, 0x0015,</div><div class='add'>+	0x00BD, 0x01E7, 0x0145, 0x0017,</div><div class='add'>+	0x00B7, 0x01E5, 0x014A, 0x001A,</div><div class='add'>+	0x00B1, 0x01E2, 0x0151, 0x001C,</div><div class='add'>+	0x00AC, 0x01E0, 0x0155, 0x001F,</div><div class='add'>+	0x00A7, 0x01DD, 0x015A, 0x0022,</div><div class='add'>+	0x00A1, 0x01DB, 0x015F, 0x0025,</div><div class='add'>+	0x009C, 0x01D8, 0x0165, 0x0027,</div><div class='add'>+	0x0097, 0x01D5, 0x016A, 0x002A,</div><div class='add'>+	0x0092, 0x01D2, 0x016E, 0x002E,</div><div class='add'>+	0x008C, 0x01CF, 0x0174, 0x0031,</div><div class='add'>+	0x0087, 0x01CC, 0x0179, 0x0034,</div><div class='add'>+	0x0083, 0x01C9, 0x017D, 0x0037,</div><div class='add'>+	0x007E, 0x01C5, 0x0182, 0x003B,</div><div class='add'>+	0x0079, 0x01C2, 0x0187, 0x003E,</div><div class='add'>+	0x0074, 0x01BE, 0x018C, 0x0042,</div><div class='add'>+	0x0070, 0x01BA, 0x0190, 0x0046,</div><div class='add'>+	0x006B, 0x01B7, 0x0195, 0x0049,</div><div class='add'>+	0x0066, 0x01B3, 0x019A, 0x004D,</div><div class='add'>+	0x0062, 0x01AF, 0x019E, 0x0051,</div><div class='add'>+	0x005E, 0x01AB, 0x01A2, 0x0055,</div><div class='add'>+	0x005A, 0x01A6, 0x01A6, 0x005A,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.4_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.400000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_40[132] = {</div><div class='add'>+	0x00FB, 0x0209, 0x00FC, 0x0000,</div><div class='add'>+	0x00F5, 0x0209, 0x0101, 0x0001,</div><div class='add'>+	0x00EE, 0x0208, 0x0108, 0x0002,</div><div class='add'>+	0x00E8, 0x0207, 0x010E, 0x0003,</div><div class='add'>+	0x00E2, 0x0206, 0x0114, 0x0004,</div><div class='add'>+	0x00DB, 0x0205, 0x011A, 0x0006,</div><div class='add'>+	0x00D5, 0x0204, 0x0120, 0x0007,</div><div class='add'>+	0x00CF, 0x0203, 0x0125, 0x0009,</div><div class='add'>+	0x00C9, 0x0201, 0x012C, 0x000A,</div><div class='add'>+	0x00C3, 0x01FF, 0x0132, 0x000C,</div><div class='add'>+	0x00BD, 0x01FD, 0x0138, 0x000E,</div><div class='add'>+	0x00B7, 0x01FB, 0x013E, 0x0010,</div><div class='add'>+	0x00B1, 0x01F9, 0x0144, 0x0012,</div><div class='add'>+	0x00AC, 0x01F7, 0x0149, 0x0014,</div><div class='add'>+	0x00A6, 0x01F4, 0x0150, 0x0016,</div><div class='add'>+	0x00A0, 0x01F2, 0x0156, 0x0018,</div><div class='add'>+	0x009B, 0x01EF, 0x015C, 0x001A,</div><div class='add'>+	0x0095, 0x01EC, 0x0162, 0x001D,</div><div class='add'>+	0x0090, 0x01E9, 0x0168, 0x001F,</div><div class='add'>+	0x008B, 0x01E6, 0x016D, 0x0022,</div><div class='add'>+	0x0085, 0x01E3, 0x0173, 0x0025,</div><div class='add'>+	0x0080, 0x01DF, 0x0179, 0x0028,</div><div class='add'>+	0x007B, 0x01DC, 0x017E, 0x002B,</div><div class='add'>+	0x0076, 0x01D8, 0x0184, 0x002E,</div><div class='add'>+	0x0071, 0x01D4, 0x018A, 0x0031,</div><div class='add'>+	0x006D, 0x01D1, 0x018E, 0x0034,</div><div class='add'>+	0x0068, 0x01CD, 0x0193, 0x0038,</div><div class='add'>+	0x0063, 0x01C8, 0x019A, 0x003B,</div><div class='add'>+	0x005F, 0x01C4, 0x019E, 0x003F,</div><div class='add'>+	0x005B, 0x01C0, 0x01A3, 0x0042,</div><div class='add'>+	0x0056, 0x01BB, 0x01A9, 0x0046,</div><div class='add'>+	0x0052, 0x01B7, 0x01AD, 0x004A,</div><div class='add'>+	0x004E, 0x01B2, 0x01B2, 0x004E,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.5_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.500000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_50[132] = {</div><div class='add'>+	0x00E5, 0x0236, 0x00E5, 0x0000,</div><div class='add'>+	0x00DE, 0x0235, 0x00ED, 0x0000,</div><div class='add'>+	0x00D7, 0x0235, 0x00F4, 0x0000,</div><div class='add'>+	0x00D0, 0x0235, 0x00FB, 0x0000,</div><div class='add'>+	0x00C9, 0x0234, 0x0102, 0x0001,</div><div class='add'>+	0x00C2, 0x0233, 0x010A, 0x0001,</div><div class='add'>+	0x00BC, 0x0232, 0x0111, 0x0001,</div><div class='add'>+	0x00B5, 0x0230, 0x0119, 0x0002,</div><div class='add'>+	0x00AE, 0x022F, 0x0121, 0x0002,</div><div class='add'>+	0x00A8, 0x022D, 0x0128, 0x0003,</div><div class='add'>+	0x00A2, 0x022B, 0x012F, 0x0004,</div><div class='add'>+	0x009B, 0x0229, 0x0137, 0x0005,</div><div class='add'>+	0x0095, 0x0226, 0x013F, 0x0006,</div><div class='add'>+	0x008F, 0x0224, 0x0146, 0x0007,</div><div class='add'>+	0x0089, 0x0221, 0x014E, 0x0008,</div><div class='add'>+	0x0083, 0x021E, 0x0155, 0x000A,</div><div class='add'>+	0x007E, 0x021B, 0x015C, 0x000B,</div><div class='add'>+	0x0078, 0x0217, 0x0164, 0x000D,</div><div class='add'>+	0x0072, 0x0213, 0x016D, 0x000E,</div><div class='add'>+	0x006D, 0x0210, 0x0173, 0x0010,</div><div class='add'>+	0x0068, 0x020C, 0x017A, 0x0012,</div><div class='add'>+	0x0063, 0x0207, 0x0182, 0x0014,</div><div class='add'>+	0x005E, 0x0203, 0x0189, 0x0016,</div><div class='add'>+	0x0059, 0x01FE, 0x0191, 0x0018,</div><div class='add'>+	0x0054, 0x01F9, 0x0198, 0x001B,</div><div class='add'>+	0x0050, 0x01F4, 0x019F, 0x001D,</div><div class='add'>+	0x004B, 0x01EF, 0x01A6, 0x0020,</div><div class='add'>+	0x0047, 0x01EA, 0x01AC, 0x0023,</div><div class='add'>+	0x0043, 0x01E4, 0x01B3, 0x0026,</div><div class='add'>+	0x003F, 0x01DF, 0x01B9, 0x0029,</div><div class='add'>+	0x003B, 0x01D9, 0x01C0, 0x002C,</div><div class='add'>+	0x0037, 0x01D3, 0x01C6, 0x0030,</div><div class='add'>+	0x0033, 0x01CD, 0x01CD, 0x0033,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.6_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.600000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_60[132] = {</div><div class='add'>+	0x00C8, 0x026F, 0x00C9, 0x0000,</div><div class='add'>+	0x00C0, 0x0270, 0x00D1, 0x0FFF,</div><div class='add'>+	0x00B8, 0x0270, 0x00D9, 0x0FFF,</div><div class='add'>+	0x00B1, 0x0270, 0x00E1, 0x0FFE,</div><div class='add'>+	0x00A9, 0x026F, 0x00EB, 0x0FFD,</div><div class='add'>+	0x00A2, 0x026E, 0x00F3, 0x0FFD,</div><div class='add'>+	0x009A, 0x026D, 0x00FD, 0x0FFC,</div><div class='add'>+	0x0093, 0x026C, 0x0105, 0x0FFC,</div><div class='add'>+	0x008C, 0x026A, 0x010F, 0x0FFB,</div><div class='add'>+	0x0085, 0x0268, 0x0118, 0x0FFB,</div><div class='add'>+	0x007E, 0x0265, 0x0122, 0x0FFB,</div><div class='add'>+	0x0078, 0x0263, 0x012A, 0x0FFB,</div><div class='add'>+	0x0071, 0x0260, 0x0134, 0x0FFB,</div><div class='add'>+	0x006B, 0x025C, 0x013E, 0x0FFB,</div><div class='add'>+	0x0065, 0x0259, 0x0147, 0x0FFB,</div><div class='add'>+	0x005F, 0x0255, 0x0151, 0x0FFB,</div><div class='add'>+	0x0059, 0x0251, 0x015A, 0x0FFC,</div><div class='add'>+	0x0054, 0x024D, 0x0163, 0x0FFC,</div><div class='add'>+	0x004E, 0x0248, 0x016D, 0x0FFD,</div><div class='add'>+	0x0049, 0x0243, 0x0176, 0x0FFE,</div><div class='add'>+	0x0044, 0x023E, 0x017F, 0x0FFF,</div><div class='add'>+	0x003F, 0x0238, 0x0189, 0x0000,</div><div class='add'>+	0x003A, 0x0232, 0x0193, 0x0001,</div><div class='add'>+	0x0036, 0x022C, 0x019C, 0x0002,</div><div class='add'>+	0x0031, 0x0226, 0x01A5, 0x0004,</div><div class='add'>+	0x002D, 0x021F, 0x01AF, 0x0005,</div><div class='add'>+	0x0029, 0x0218, 0x01B8, 0x0007,</div><div class='add'>+	0x0025, 0x0211, 0x01C1, 0x0009,</div><div class='add'>+	0x0022, 0x020A, 0x01C9, 0x000B,</div><div class='add'>+	0x001E, 0x0203, 0x01D2, 0x000D,</div><div class='add'>+	0x001B, 0x01FB, 0x01DA, 0x0010,</div><div class='add'>+	0x0018, 0x01F3, 0x01E3, 0x0012,</div><div class='add'>+	0x0015, 0x01EB, 0x01EB, 0x0015,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.7_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.700000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_70[132] = {</div><div class='add'>+	0x00A3, 0x02B9, 0x00A4, 0x0000,</div><div class='add'>+	0x009A, 0x02BA, 0x00AD, 0x0FFF,</div><div class='add'>+	0x0092, 0x02BA, 0x00B6, 0x0FFE,</div><div class='add'>+	0x0089, 0x02BA, 0x00C1, 0x0FFC,</div><div class='add'>+	0x0081, 0x02B9, 0x00CB, 0x0FFB,</div><div class='add'>+	0x0079, 0x02B8, 0x00D5, 0x0FFA,</div><div class='add'>+	0x0071, 0x02B7, 0x00DF, 0x0FF9,</div><div class='add'>+	0x0069, 0x02B5, 0x00EA, 0x0FF8,</div><div class='add'>+	0x0062, 0x02B3, 0x00F4, 0x0FF7,</div><div class='add'>+	0x005B, 0x02B0, 0x00FF, 0x0FF6,</div><div class='add'>+	0x0054, 0x02AD, 0x010B, 0x0FF4,</div><div class='add'>+	0x004D, 0x02A9, 0x0117, 0x0FF3,</div><div class='add'>+	0x0046, 0x02A5, 0x0123, 0x0FF2,</div><div class='add'>+	0x0040, 0x02A1, 0x012D, 0x0FF2,</div><div class='add'>+	0x003A, 0x029C, 0x0139, 0x0FF1,</div><div class='add'>+	0x0034, 0x0297, 0x0145, 0x0FF0,</div><div class='add'>+	0x002F, 0x0292, 0x0150, 0x0FEF,</div><div class='add'>+	0x0029, 0x028C, 0x015C, 0x0FEF,</div><div class='add'>+	0x0024, 0x0285, 0x0169, 0x0FEE,</div><div class='add'>+	0x001F, 0x027F, 0x0174, 0x0FEE,</div><div class='add'>+	0x001B, 0x0278, 0x017F, 0x0FEE,</div><div class='add'>+	0x0016, 0x0270, 0x018D, 0x0FED,</div><div class='add'>+	0x0012, 0x0268, 0x0199, 0x0FED,</div><div class='add'>+	0x000E, 0x0260, 0x01A4, 0x0FEE,</div><div class='add'>+	0x000B, 0x0258, 0x01AF, 0x0FEE,</div><div class='add'>+	0x0007, 0x024F, 0x01BC, 0x0FEE,</div><div class='add'>+	0x0004, 0x0246, 0x01C7, 0x0FEF,</div><div class='add'>+	0x0001, 0x023D, 0x01D3, 0x0FEF,</div><div class='add'>+	0x0FFE, 0x0233, 0x01DF, 0x0FF0,</div><div class='add'>+	0x0FFC, 0x0229, 0x01EA, 0x0FF1,</div><div class='add'>+	0x0FFA, 0x021F, 0x01F4, 0x0FF3,</div><div class='add'>+	0x0FF8, 0x0215, 0x01FF, 0x0FF4,</div><div class='add'>+	0x0FF6, 0x020A, 0x020A, 0x0FF6,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.8_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.800000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_80[132] = {</div><div class='add'>+	0x0075, 0x0315, 0x0076, 0x0000,</div><div class='add'>+	0x006C, 0x0316, 0x007F, 0x0FFF,</div><div class='add'>+	0x0062, 0x0316, 0x008A, 0x0FFE,</div><div class='add'>+	0x0059, 0x0315, 0x0096, 0x0FFC,</div><div class='add'>+	0x0050, 0x0314, 0x00A1, 0x0FFB,</div><div class='add'>+	0x0048, 0x0312, 0x00AD, 0x0FF9,</div><div class='add'>+	0x0040, 0x0310, 0x00B8, 0x0FF8,</div><div class='add'>+	0x0038, 0x030D, 0x00C5, 0x0FF6,</div><div class='add'>+	0x0030, 0x030A, 0x00D1, 0x0FF5,</div><div class='add'>+	0x0029, 0x0306, 0x00DE, 0x0FF3,</div><div class='add'>+	0x0022, 0x0301, 0x00EB, 0x0FF2,</div><div class='add'>+	0x001C, 0x02FC, 0x00F8, 0x0FF0,</div><div class='add'>+	0x0015, 0x02F7, 0x0106, 0x0FEE,</div><div class='add'>+	0x0010, 0x02F1, 0x0112, 0x0FED,</div><div class='add'>+	0x000A, 0x02EA, 0x0121, 0x0FEB,</div><div class='add'>+	0x0005, 0x02E3, 0x012F, 0x0FE9,</div><div class='add'>+	0x0000, 0x02DB, 0x013D, 0x0FE8,</div><div class='add'>+	0x0FFB, 0x02D3, 0x014C, 0x0FE6,</div><div class='add'>+	0x0FF7, 0x02CA, 0x015A, 0x0FE5,</div><div class='add'>+	0x0FF3, 0x02C1, 0x0169, 0x0FE3,</div><div class='add'>+	0x0FF0, 0x02B7, 0x0177, 0x0FE2,</div><div class='add'>+	0x0FEC, 0x02AD, 0x0186, 0x0FE1,</div><div class='add'>+	0x0FE9, 0x02A2, 0x0196, 0x0FDF,</div><div class='add'>+	0x0FE7, 0x0297, 0x01A4, 0x0FDE,</div><div class='add'>+	0x0FE4, 0x028C, 0x01B3, 0x0FDD,</div><div class='add'>+	0x0FE2, 0x0280, 0x01C2, 0x0FDC,</div><div class='add'>+	0x0FE0, 0x0274, 0x01D0, 0x0FDC,</div><div class='add'>+	0x0FDF, 0x0268, 0x01DE, 0x0FDB,</div><div class='add'>+	0x0FDD, 0x025B, 0x01EE, 0x0FDA,</div><div class='add'>+	0x0FDC, 0x024E, 0x01FC, 0x0FDA,</div><div class='add'>+	0x0FDB, 0x0241, 0x020A, 0x0FDA,</div><div class='add'>+	0x0FDB, 0x0233, 0x0218, 0x0FDA,</div><div class='add'>+	0x0FDA, 0x0226, 0x0226, 0x0FDA,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_0.9_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.900000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_90[132] = {</div><div class='add'>+	0x003F, 0x0383, 0x003E, 0x0000,</div><div class='add'>+	0x0034, 0x0383, 0x004A, 0x0FFF,</div><div class='add'>+	0x002B, 0x0383, 0x0054, 0x0FFE,</div><div class='add'>+	0x0021, 0x0381, 0x0061, 0x0FFD,</div><div class='add'>+	0x0019, 0x037F, 0x006C, 0x0FFC,</div><div class='add'>+	0x0010, 0x037C, 0x0079, 0x0FFB,</div><div class='add'>+	0x0008, 0x0378, 0x0086, 0x0FFA,</div><div class='add'>+	0x0001, 0x0374, 0x0093, 0x0FF8,</div><div class='add'>+	0x0FFA, 0x036E, 0x00A1, 0x0FF7,</div><div class='add'>+	0x0FF3, 0x0368, 0x00B0, 0x0FF5,</div><div class='add'>+	0x0FED, 0x0361, 0x00BF, 0x0FF3,</div><div class='add'>+	0x0FE8, 0x035A, 0x00CD, 0x0FF1,</div><div class='add'>+	0x0FE2, 0x0352, 0x00DC, 0x0FF0,</div><div class='add'>+	0x0FDE, 0x0349, 0x00EB, 0x0FEE,</div><div class='add'>+	0x0FD9, 0x033F, 0x00FC, 0x0FEC,</div><div class='add'>+	0x0FD5, 0x0335, 0x010D, 0x0FE9,</div><div class='add'>+	0x0FD2, 0x032A, 0x011D, 0x0FE7,</div><div class='add'>+	0x0FCF, 0x031E, 0x012E, 0x0FE5,</div><div class='add'>+	0x0FCC, 0x0312, 0x013F, 0x0FE3,</div><div class='add'>+	0x0FCA, 0x0305, 0x0150, 0x0FE1,</div><div class='add'>+	0x0FC8, 0x02F8, 0x0162, 0x0FDE,</div><div class='add'>+	0x0FC6, 0x02EA, 0x0174, 0x0FDC,</div><div class='add'>+	0x0FC5, 0x02DC, 0x0185, 0x0FDA,</div><div class='add'>+	0x0FC4, 0x02CD, 0x0197, 0x0FD8,</div><div class='add'>+	0x0FC3, 0x02BE, 0x01AA, 0x0FD5,</div><div class='add'>+	0x0FC3, 0x02AF, 0x01BB, 0x0FD3,</div><div class='add'>+	0x0FC3, 0x029F, 0x01CD, 0x0FD1,</div><div class='add'>+	0x0FC3, 0x028E, 0x01E0, 0x0FCF,</div><div class='add'>+	0x0FC3, 0x027E, 0x01F2, 0x0FCD,</div><div class='add'>+	0x0FC4, 0x026D, 0x0203, 0x0FCC,</div><div class='add'>+	0x0FC5, 0x025C, 0x0215, 0x0FCA,</div><div class='add'>+	0x0FC6, 0x024B, 0x0227, 0x0FC8,</div><div class='add'>+	0x0FC7, 0x0239, 0x0239, 0x0FC7,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			03-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	4t_64p_LanczosEd_p_1_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		4</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 1.000000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_1_00[132] = {</div><div class='add'>+	0x0000, 0x0400, 0x0000, 0x0000,</div><div class='add'>+	0x0FF6, 0x03FF, 0x000B, 0x0000,</div><div class='add'>+	0x0FED, 0x03FE, 0x0015, 0x0000,</div><div class='add'>+	0x0FE4, 0x03FB, 0x0022, 0x0FFF,</div><div class='add'>+	0x0FDC, 0x03F7, 0x002E, 0x0FFF,</div><div class='add'>+	0x0FD5, 0x03F2, 0x003B, 0x0FFE,</div><div class='add'>+	0x0FCE, 0x03EC, 0x0048, 0x0FFE,</div><div class='add'>+	0x0FC8, 0x03E5, 0x0056, 0x0FFD,</div><div class='add'>+	0x0FC3, 0x03DC, 0x0065, 0x0FFC,</div><div class='add'>+	0x0FBE, 0x03D3, 0x0075, 0x0FFA,</div><div class='add'>+	0x0FB9, 0x03C9, 0x0085, 0x0FF9,</div><div class='add'>+	0x0FB6, 0x03BE, 0x0094, 0x0FF8,</div><div class='add'>+	0x0FB2, 0x03B2, 0x00A6, 0x0FF6,</div><div class='add'>+	0x0FB0, 0x03A5, 0x00B7, 0x0FF4,</div><div class='add'>+	0x0FAD, 0x0397, 0x00CA, 0x0FF2,</div><div class='add'>+	0x0FAB, 0x0389, 0x00DC, 0x0FF0,</div><div class='add'>+	0x0FAA, 0x0379, 0x00EF, 0x0FEE,</div><div class='add'>+	0x0FA9, 0x0369, 0x0102, 0x0FEC,</div><div class='add'>+	0x0FA9, 0x0359, 0x0115, 0x0FE9,</div><div class='add'>+	0x0FA9, 0x0348, 0x0129, 0x0FE6,</div><div class='add'>+	0x0FA9, 0x0336, 0x013D, 0x0FE4,</div><div class='add'>+	0x0FA9, 0x0323, 0x0153, 0x0FE1,</div><div class='add'>+	0x0FAA, 0x0310, 0x0168, 0x0FDE,</div><div class='add'>+	0x0FAC, 0x02FD, 0x017C, 0x0FDB,</div><div class='add'>+	0x0FAD, 0x02E9, 0x0192, 0x0FD8,</div><div class='add'>+	0x0FAF, 0x02D5, 0x01A7, 0x0FD5,</div><div class='add'>+	0x0FB1, 0x02C0, 0x01BD, 0x0FD2,</div><div class='add'>+	0x0FB3, 0x02AC, 0x01D2, 0x0FCF,</div><div class='add'>+	0x0FB5, 0x0296, 0x01E9, 0x0FCC,</div><div class='add'>+	0x0FB8, 0x0281, 0x01FE, 0x0FC9,</div><div class='add'>+	0x0FBA, 0x026C, 0x0214, 0x0FC6,</div><div class='add'>+	0x0FBD, 0x0256, 0x022A, 0x0FC3,</div><div class='add'>+	0x0FC0, 0x0240, 0x0240, 0x0FC0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.3_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.300000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_30[198] = {</div><div class='add'>+	0x004B, 0x0100, 0x0169, 0x0101, 0x004B, 0x0000,</div><div class='add'>+	0x0049, 0x00FD, 0x0169, 0x0103, 0x004E, 0x0000,</div><div class='add'>+	0x0047, 0x00FA, 0x0169, 0x0106, 0x0050, 0x0000,</div><div class='add'>+	0x0045, 0x00F7, 0x0168, 0x0109, 0x0052, 0x0001,</div><div class='add'>+	0x0043, 0x00F5, 0x0168, 0x010B, 0x0054, 0x0001,</div><div class='add'>+	0x0040, 0x00F2, 0x0168, 0x010E, 0x0057, 0x0001,</div><div class='add'>+	0x003E, 0x00EF, 0x0168, 0x0110, 0x0059, 0x0002,</div><div class='add'>+	0x003C, 0x00EC, 0x0167, 0x0113, 0x005C, 0x0002,</div><div class='add'>+	0x003A, 0x00E9, 0x0167, 0x0116, 0x005E, 0x0002,</div><div class='add'>+	0x0038, 0x00E6, 0x0166, 0x0118, 0x0061, 0x0003,</div><div class='add'>+	0x0036, 0x00E3, 0x0165, 0x011C, 0x0063, 0x0003,</div><div class='add'>+	0x0034, 0x00E0, 0x0165, 0x011D, 0x0066, 0x0004,</div><div class='add'>+	0x0033, 0x00DD, 0x0164, 0x0120, 0x0068, 0x0004,</div><div class='add'>+	0x0031, 0x00DA, 0x0163, 0x0122, 0x006B, 0x0005,</div><div class='add'>+	0x002F, 0x00D7, 0x0163, 0x0125, 0x006D, 0x0005,</div><div class='add'>+	0x002D, 0x00D3, 0x0162, 0x0128, 0x0070, 0x0006,</div><div class='add'>+	0x002B, 0x00D0, 0x0161, 0x012A, 0x0073, 0x0007,</div><div class='add'>+	0x002A, 0x00CD, 0x0160, 0x012D, 0x0075, 0x0007,</div><div class='add'>+	0x0028, 0x00CA, 0x015F, 0x012F, 0x0078, 0x0008,</div><div class='add'>+	0x0026, 0x00C7, 0x015E, 0x0131, 0x007B, 0x0009,</div><div class='add'>+	0x0025, 0x00C4, 0x015D, 0x0133, 0x007E, 0x0009,</div><div class='add'>+	0x0023, 0x00C1, 0x015C, 0x0136, 0x0080, 0x000A,</div><div class='add'>+	0x0022, 0x00BE, 0x015A, 0x0138, 0x0083, 0x000B,</div><div class='add'>+	0x0020, 0x00BB, 0x0159, 0x013A, 0x0086, 0x000C,</div><div class='add'>+	0x001F, 0x00B8, 0x0158, 0x013B, 0x0089, 0x000D,</div><div class='add'>+	0x001E, 0x00B5, 0x0156, 0x013E, 0x008C, 0x000D,</div><div class='add'>+	0x001C, 0x00B2, 0x0155, 0x0140, 0x008F, 0x000E,</div><div class='add'>+	0x001B, 0x00AF, 0x0153, 0x0143, 0x0091, 0x000F,</div><div class='add'>+	0x0019, 0x00AC, 0x0152, 0x0145, 0x0094, 0x0010,</div><div class='add'>+	0x0018, 0x00A9, 0x0150, 0x0147, 0x0097, 0x0011,</div><div class='add'>+	0x0017, 0x00A6, 0x014F, 0x0148, 0x009A, 0x0012,</div><div class='add'>+	0x0016, 0x00A3, 0x014D, 0x0149, 0x009D, 0x0014,</div><div class='add'>+	0x0015, 0x00A0, 0x014B, 0x014B, 0x00A0, 0x0015,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.4_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.400000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_40[198] = {</div><div class='add'>+	0x0028, 0x0106, 0x01A3, 0x0107, 0x0028, 0x0000,</div><div class='add'>+	0x0026, 0x0102, 0x01A3, 0x010A, 0x002B, 0x0000,</div><div class='add'>+	0x0024, 0x00FE, 0x01A3, 0x010F, 0x002D, 0x0FFF,</div><div class='add'>+	0x0022, 0x00FA, 0x01A3, 0x0113, 0x002F, 0x0FFF,</div><div class='add'>+	0x0021, 0x00F6, 0x01A3, 0x0116, 0x0031, 0x0FFF,</div><div class='add'>+	0x001F, 0x00F2, 0x01A2, 0x011B, 0x0034, 0x0FFE,</div><div class='add'>+	0x001D, 0x00EE, 0x01A2, 0x011F, 0x0036, 0x0FFE,</div><div class='add'>+	0x001B, 0x00EA, 0x01A1, 0x0123, 0x0039, 0x0FFE,</div><div class='add'>+	0x0019, 0x00E6, 0x01A1, 0x0127, 0x003B, 0x0FFE,</div><div class='add'>+	0x0018, 0x00E2, 0x01A0, 0x012A, 0x003E, 0x0FFE,</div><div class='add'>+	0x0016, 0x00DE, 0x01A0, 0x012E, 0x0041, 0x0FFD,</div><div class='add'>+	0x0015, 0x00DA, 0x019F, 0x0132, 0x0043, 0x0FFD,</div><div class='add'>+	0x0013, 0x00D6, 0x019E, 0x0136, 0x0046, 0x0FFD,</div><div class='add'>+	0x0012, 0x00D2, 0x019D, 0x0139, 0x0049, 0x0FFD,</div><div class='add'>+	0x0010, 0x00CE, 0x019C, 0x013D, 0x004C, 0x0FFD,</div><div class='add'>+	0x000F, 0x00CA, 0x019A, 0x0141, 0x004F, 0x0FFD,</div><div class='add'>+	0x000E, 0x00C6, 0x0199, 0x0144, 0x0052, 0x0FFD,</div><div class='add'>+	0x000D, 0x00C2, 0x0197, 0x0148, 0x0055, 0x0FFD,</div><div class='add'>+	0x000B, 0x00BE, 0x0196, 0x014C, 0x0058, 0x0FFD,</div><div class='add'>+	0x000A, 0x00BA, 0x0195, 0x014F, 0x005B, 0x0FFD,</div><div class='add'>+	0x0009, 0x00B6, 0x0193, 0x0153, 0x005E, 0x0FFD,</div><div class='add'>+	0x0008, 0x00B2, 0x0191, 0x0157, 0x0061, 0x0FFD,</div><div class='add'>+	0x0007, 0x00AE, 0x0190, 0x015A, 0x0064, 0x0FFD,</div><div class='add'>+	0x0006, 0x00AA, 0x018E, 0x015D, 0x0068, 0x0FFD,</div><div class='add'>+	0x0005, 0x00A6, 0x018C, 0x0161, 0x006B, 0x0FFD,</div><div class='add'>+	0x0005, 0x00A2, 0x0189, 0x0164, 0x006F, 0x0FFD,</div><div class='add'>+	0x0004, 0x009E, 0x0187, 0x0167, 0x0072, 0x0FFE,</div><div class='add'>+	0x0003, 0x009A, 0x0185, 0x016B, 0x0075, 0x0FFE,</div><div class='add'>+	0x0002, 0x0096, 0x0183, 0x016E, 0x0079, 0x0FFE,</div><div class='add'>+	0x0002, 0x0093, 0x0180, 0x016F, 0x007D, 0x0FFF,</div><div class='add'>+	0x0001, 0x008F, 0x017E, 0x0173, 0x0080, 0x0FFF,</div><div class='add'>+	0x0001, 0x008B, 0x017B, 0x0175, 0x0084, 0x0000,</div><div class='add'>+	0x0000, 0x0087, 0x0179, 0x0179, 0x0087, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.5_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.500000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_50[198] = {</div><div class='add'>+	0x0000, 0x0107, 0x01F3, 0x0106, 0x0000, 0x0000,</div><div class='add'>+	0x0FFE, 0x0101, 0x01F3, 0x010D, 0x0002, 0x0FFF,</div><div class='add'>+	0x0FFD, 0x00FB, 0x01F3, 0x0113, 0x0003, 0x0FFF,</div><div class='add'>+	0x0FFC, 0x00F6, 0x01F3, 0x0118, 0x0005, 0x0FFE,</div><div class='add'>+	0x0FFA, 0x00F0, 0x01F3, 0x011E, 0x0007, 0x0FFE,</div><div class='add'>+	0x0FF9, 0x00EB, 0x01F2, 0x0124, 0x0009, 0x0FFD,</div><div class='add'>+	0x0FF8, 0x00E5, 0x01F2, 0x0129, 0x000B, 0x0FFD,</div><div class='add'>+	0x0FF7, 0x00E0, 0x01F1, 0x012F, 0x000D, 0x0FFC,</div><div class='add'>+	0x0FF6, 0x00DA, 0x01F0, 0x0135, 0x0010, 0x0FFB,</div><div class='add'>+	0x0FF5, 0x00D4, 0x01EF, 0x013B, 0x0012, 0x0FFB,</div><div class='add'>+	0x0FF4, 0x00CF, 0x01EE, 0x0141, 0x0014, 0x0FFA,</div><div class='add'>+	0x0FF3, 0x00C9, 0x01ED, 0x0147, 0x0017, 0x0FF9,</div><div class='add'>+	0x0FF2, 0x00C4, 0x01EB, 0x014C, 0x001A, 0x0FF9,</div><div class='add'>+	0x0FF1, 0x00BF, 0x01EA, 0x0152, 0x001C, 0x0FF8,</div><div class='add'>+	0x0FF1, 0x00B9, 0x01E8, 0x0157, 0x001F, 0x0FF8,</div><div class='add'>+	0x0FF0, 0x00B4, 0x01E6, 0x015D, 0x0022, 0x0FF7,</div><div class='add'>+	0x0FF0, 0x00AE, 0x01E4, 0x0163, 0x0025, 0x0FF6,</div><div class='add'>+	0x0FEF, 0x00A9, 0x01E2, 0x0168, 0x0028, 0x0FF6,</div><div class='add'>+	0x0FEF, 0x00A4, 0x01DF, 0x016E, 0x002B, 0x0FF5,</div><div class='add'>+	0x0FEF, 0x009F, 0x01DD, 0x0172, 0x002E, 0x0FF5,</div><div class='add'>+	0x0FEE, 0x009A, 0x01DA, 0x0178, 0x0032, 0x0FF4,</div><div class='add'>+	0x0FEE, 0x0094, 0x01D8, 0x017E, 0x0035, 0x0FF3,</div><div class='add'>+	0x0FEE, 0x008F, 0x01D5, 0x0182, 0x0039, 0x0FF3,</div><div class='add'>+	0x0FEE, 0x008A, 0x01D2, 0x0188, 0x003C, 0x0FF2,</div><div class='add'>+	0x0FEE, 0x0085, 0x01CF, 0x018C, 0x0040, 0x0FF2,</div><div class='add'>+	0x0FEE, 0x0081, 0x01CB, 0x0191, 0x0044, 0x0FF1,</div><div class='add'>+	0x0FEE, 0x007C, 0x01C8, 0x0196, 0x0047, 0x0FF1,</div><div class='add'>+	0x0FEE, 0x0077, 0x01C4, 0x019C, 0x004B, 0x0FF0,</div><div class='add'>+	0x0FEE, 0x0072, 0x01C1, 0x01A0, 0x004F, 0x0FF0,</div><div class='add'>+	0x0FEE, 0x006E, 0x01BD, 0x01A4, 0x0053, 0x0FF0,</div><div class='add'>+	0x0FEE, 0x0069, 0x01B9, 0x01A9, 0x0058, 0x0FEF,</div><div class='add'>+	0x0FEE, 0x0065, 0x01B5, 0x01AD, 0x005C, 0x0FEF,</div><div class='add'>+	0x0FEF, 0x0060, 0x01B1, 0x01B1, 0x0060, 0x0FEF,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.6_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.600000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_60[198] = {</div><div class='add'>+	0x0FD9, 0x00FB, 0x0258, 0x00FB, 0x0FD9, 0x0000,</div><div class='add'>+	0x0FD9, 0x00F3, 0x0258, 0x0102, 0x0FDA, 0x0000,</div><div class='add'>+	0x0FD8, 0x00EB, 0x0258, 0x010B, 0x0FDB, 0x0FFF,</div><div class='add'>+	0x0FD8, 0x00E3, 0x0258, 0x0112, 0x0FDC, 0x0FFF,</div><div class='add'>+	0x0FD8, 0x00DC, 0x0257, 0x011B, 0x0FDC, 0x0FFE,</div><div class='add'>+	0x0FD7, 0x00D4, 0x0256, 0x0123, 0x0FDE, 0x0FFE,</div><div class='add'>+	0x0FD7, 0x00CD, 0x0255, 0x012B, 0x0FDF, 0x0FFD,</div><div class='add'>+	0x0FD7, 0x00C5, 0x0254, 0x0133, 0x0FE0, 0x0FFD,</div><div class='add'>+	0x0FD7, 0x00BE, 0x0252, 0x013C, 0x0FE1, 0x0FFC,</div><div class='add'>+	0x0FD7, 0x00B6, 0x0251, 0x0143, 0x0FE3, 0x0FFC,</div><div class='add'>+	0x0FD8, 0x00AF, 0x024F, 0x014B, 0x0FE4, 0x0FFB,</div><div class='add'>+	0x0FD8, 0x00A8, 0x024C, 0x0154, 0x0FE6, 0x0FFA,</div><div class='add'>+	0x0FD8, 0x00A1, 0x024A, 0x015B, 0x0FE8, 0x0FFA,</div><div class='add'>+	0x0FD9, 0x009A, 0x0247, 0x0163, 0x0FEA, 0x0FF9,</div><div class='add'>+	0x0FD9, 0x0093, 0x0244, 0x016C, 0x0FEC, 0x0FF8,</div><div class='add'>+	0x0FD9, 0x008C, 0x0241, 0x0174, 0x0FEF, 0x0FF7,</div><div class='add'>+	0x0FDA, 0x0085, 0x023E, 0x017B, 0x0FF1, 0x0FF7,</div><div class='add'>+	0x0FDB, 0x007F, 0x023A, 0x0183, 0x0FF3, 0x0FF6,</div><div class='add'>+	0x0FDB, 0x0078, 0x0237, 0x018B, 0x0FF6, 0x0FF5,</div><div class='add'>+	0x0FDC, 0x0072, 0x0233, 0x0192, 0x0FF9, 0x0FF4,</div><div class='add'>+	0x0FDD, 0x006C, 0x022F, 0x0199, 0x0FFC, 0x0FF3,</div><div class='add'>+	0x0FDD, 0x0065, 0x022A, 0x01A3, 0x0FFF, 0x0FF2,</div><div class='add'>+	0x0FDE, 0x005F, 0x0226, 0x01AA, 0x0002, 0x0FF1,</div><div class='add'>+	0x0FDF, 0x005A, 0x0221, 0x01B0, 0x0006, 0x0FF0,</div><div class='add'>+	0x0FE0, 0x0054, 0x021C, 0x01B7, 0x0009, 0x0FF0,</div><div class='add'>+	0x0FE1, 0x004E, 0x0217, 0x01BE, 0x000D, 0x0FEF,</div><div class='add'>+	0x0FE2, 0x0048, 0x0212, 0x01C6, 0x0010, 0x0FEE,</div><div class='add'>+	0x0FE3, 0x0043, 0x020C, 0x01CD, 0x0014, 0x0FED,</div><div class='add'>+	0x0FE4, 0x003E, 0x0207, 0x01D3, 0x0018, 0x0FEC,</div><div class='add'>+	0x0FE5, 0x0039, 0x0200, 0x01DA, 0x001D, 0x0FEB,</div><div class='add'>+	0x0FE6, 0x0034, 0x01FA, 0x01E1, 0x0021, 0x0FEA,</div><div class='add'>+	0x0FE7, 0x002F, 0x01F5, 0x01E7, 0x0025, 0x0FE9,</div><div class='add'>+	0x0FE8, 0x002A, 0x01EE, 0x01EE, 0x002A, 0x0FE8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.7_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.700000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_70[198] = {</div><div class='add'>+	0x0FC0, 0x00DA, 0x02CC, 0x00DA, 0x0FC0, 0x0000,</div><div class='add'>+	0x0FC1, 0x00D0, 0x02CC, 0x00E4, 0x0FBF, 0x0000,</div><div class='add'>+	0x0FC2, 0x00C6, 0x02CB, 0x00EF, 0x0FBE, 0x0000,</div><div class='add'>+	0x0FC3, 0x00BC, 0x02CA, 0x00F9, 0x0FBE, 0x0000,</div><div class='add'>+	0x0FC4, 0x00B2, 0x02C9, 0x0104, 0x0FBD, 0x0000,</div><div class='add'>+	0x0FC5, 0x00A8, 0x02C7, 0x010F, 0x0FBD, 0x0000,</div><div class='add'>+	0x0FC7, 0x009F, 0x02C5, 0x0119, 0x0FBC, 0x0000,</div><div class='add'>+	0x0FC8, 0x0095, 0x02C3, 0x0124, 0x0FBC, 0x0000,</div><div class='add'>+	0x0FC9, 0x008C, 0x02C0, 0x012F, 0x0FBC, 0x0000,</div><div class='add'>+	0x0FCB, 0x0083, 0x02BD, 0x0139, 0x0FBC, 0x0000,</div><div class='add'>+	0x0FCC, 0x007A, 0x02BA, 0x0144, 0x0FBC, 0x0000,</div><div class='add'>+	0x0FCE, 0x0072, 0x02B6, 0x014D, 0x0FBD, 0x0000,</div><div class='add'>+	0x0FD0, 0x0069, 0x02B2, 0x0159, 0x0FBD, 0x0FFF,</div><div class='add'>+	0x0FD1, 0x0061, 0x02AD, 0x0164, 0x0FBE, 0x0FFF,</div><div class='add'>+	0x0FD3, 0x0059, 0x02A9, 0x016E, 0x0FBF, 0x0FFE,</div><div class='add'>+	0x0FD4, 0x0051, 0x02A4, 0x017A, 0x0FBF, 0x0FFE,</div><div class='add'>+	0x0FD6, 0x0049, 0x029E, 0x0184, 0x0FC1, 0x0FFE,</div><div class='add'>+	0x0FD8, 0x0042, 0x0299, 0x018E, 0x0FC2, 0x0FFD,</div><div class='add'>+	0x0FD9, 0x003A, 0x0293, 0x019B, 0x0FC3, 0x0FFC,</div><div class='add'>+	0x0FDB, 0x0033, 0x028D, 0x01A4, 0x0FC5, 0x0FFC,</div><div class='add'>+	0x0FDC, 0x002D, 0x0286, 0x01AF, 0x0FC7, 0x0FFB,</div><div class='add'>+	0x0FDE, 0x0026, 0x0280, 0x01BA, 0x0FC8, 0x0FFA,</div><div class='add'>+	0x0FE0, 0x001F, 0x0279, 0x01C4, 0x0FCB, 0x0FF9,</div><div class='add'>+	0x0FE1, 0x0019, 0x0272, 0x01CE, 0x0FCD, 0x0FF9,</div><div class='add'>+	0x0FE3, 0x0013, 0x026A, 0x01D9, 0x0FCF, 0x0FF8,</div><div class='add'>+	0x0FE4, 0x000D, 0x0263, 0x01E3, 0x0FD2, 0x0FF7,</div><div class='add'>+	0x0FE6, 0x0008, 0x025B, 0x01EC, 0x0FD5, 0x0FF6,</div><div class='add'>+	0x0FE7, 0x0002, 0x0253, 0x01F7, 0x0FD8, 0x0FF5,</div><div class='add'>+	0x0FE9, 0x0FFD, 0x024A, 0x0202, 0x0FDB, 0x0FF3,</div><div class='add'>+	0x0FEA, 0x0FF8, 0x0242, 0x020B, 0x0FDF, 0x0FF2,</div><div class='add'>+	0x0FEC, 0x0FF3, 0x0239, 0x0215, 0x0FE2, 0x0FF1,</div><div class='add'>+	0x0FED, 0x0FEF, 0x0230, 0x021E, 0x0FE6, 0x0FF0,</div><div class='add'>+	0x0FEF, 0x0FEB, 0x0226, 0x0226, 0x0FEB, 0x0FEF,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.8_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.800000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_80[198] = {</div><div class='add'>+	0x0FBF, 0x00A1, 0x0340, 0x00A1, 0x0FBF, 0x0000,</div><div class='add'>+	0x0FC1, 0x0095, 0x0340, 0x00AD, 0x0FBC, 0x0001,</div><div class='add'>+	0x0FC4, 0x0089, 0x033E, 0x00BA, 0x0FBA, 0x0001,</div><div class='add'>+	0x0FC6, 0x007D, 0x033D, 0x00C6, 0x0FB8, 0x0002,</div><div class='add'>+	0x0FC9, 0x0072, 0x033A, 0x00D3, 0x0FB6, 0x0002,</div><div class='add'>+	0x0FCC, 0x0067, 0x0338, 0x00DF, 0x0FB3, 0x0003,</div><div class='add'>+	0x0FCE, 0x005C, 0x0334, 0x00EE, 0x0FB1, 0x0003,</div><div class='add'>+	0x0FD1, 0x0051, 0x0331, 0x00FA, 0x0FAF, 0x0004,</div><div class='add'>+	0x0FD3, 0x0047, 0x032D, 0x0108, 0x0FAD, 0x0004,</div><div class='add'>+	0x0FD6, 0x003D, 0x0328, 0x0116, 0x0FAB, 0x0004,</div><div class='add'>+	0x0FD8, 0x0033, 0x0323, 0x0123, 0x0FAA, 0x0005,</div><div class='add'>+	0x0FDB, 0x002A, 0x031D, 0x0131, 0x0FA8, 0x0005,</div><div class='add'>+	0x0FDD, 0x0021, 0x0317, 0x013F, 0x0FA7, 0x0005,</div><div class='add'>+	0x0FDF, 0x0018, 0x0311, 0x014D, 0x0FA5, 0x0006,</div><div class='add'>+	0x0FE2, 0x0010, 0x030A, 0x015A, 0x0FA4, 0x0006,</div><div class='add'>+	0x0FE4, 0x0008, 0x0302, 0x0169, 0x0FA3, 0x0006,</div><div class='add'>+	0x0FE6, 0x0000, 0x02FB, 0x0177, 0x0FA2, 0x0006,</div><div class='add'>+	0x0FE8, 0x0FF9, 0x02F3, 0x0185, 0x0FA1, 0x0006,</div><div class='add'>+	0x0FEB, 0x0FF1, 0x02EA, 0x0193, 0x0FA1, 0x0006,</div><div class='add'>+	0x0FED, 0x0FEB, 0x02E1, 0x01A1, 0x0FA0, 0x0006,</div><div class='add'>+	0x0FEE, 0x0FE4, 0x02D8, 0x01B0, 0x0FA0, 0x0006,</div><div class='add'>+	0x0FF0, 0x0FDE, 0x02CE, 0x01BE, 0x0FA0, 0x0006,</div><div class='add'>+	0x0FF2, 0x0FD8, 0x02C5, 0x01CB, 0x0FA0, 0x0006,</div><div class='add'>+	0x0FF4, 0x0FD3, 0x02BA, 0x01D8, 0x0FA1, 0x0006,</div><div class='add'>+	0x0FF6, 0x0FCD, 0x02B0, 0x01E7, 0x0FA1, 0x0005,</div><div class='add'>+	0x0FF7, 0x0FC8, 0x02A5, 0x01F5, 0x0FA2, 0x0005,</div><div class='add'>+	0x0FF9, 0x0FC4, 0x029A, 0x0202, 0x0FA3, 0x0004,</div><div class='add'>+	0x0FFA, 0x0FC0, 0x028E, 0x0210, 0x0FA4, 0x0004,</div><div class='add'>+	0x0FFB, 0x0FBC, 0x0283, 0x021D, 0x0FA6, 0x0003,</div><div class='add'>+	0x0FFD, 0x0FB8, 0x0276, 0x022A, 0x0FA8, 0x0003,</div><div class='add'>+	0x0FFE, 0x0FB4, 0x026B, 0x0237, 0x0FAA, 0x0002,</div><div class='add'>+	0x0FFF, 0x0FB1, 0x025E, 0x0245, 0x0FAC, 0x0001,</div><div class='add'>+	0x0000, 0x0FAE, 0x0252, 0x0252, 0x0FAE, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_0.9_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 0.900000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_90[198] = {</div><div class='add'>+	0x0FD8, 0x0055, 0x03A7, 0x0054, 0x0FD8, 0x0000,</div><div class='add'>+	0x0FDB, 0x0047, 0x03A7, 0x0063, 0x0FD4, 0x0000,</div><div class='add'>+	0x0FDF, 0x003B, 0x03A5, 0x006F, 0x0FD1, 0x0001,</div><div class='add'>+	0x0FE2, 0x002E, 0x03A3, 0x007E, 0x0FCD, 0x0002,</div><div class='add'>+	0x0FE5, 0x0022, 0x03A0, 0x008D, 0x0FCA, 0x0002,</div><div class='add'>+	0x0FE8, 0x0017, 0x039D, 0x009B, 0x0FC6, 0x0003,</div><div class='add'>+	0x0FEB, 0x000C, 0x0398, 0x00AC, 0x0FC2, 0x0003,</div><div class='add'>+	0x0FEE, 0x0001, 0x0394, 0x00BA, 0x0FBF, 0x0004,</div><div class='add'>+	0x0FF1, 0x0FF7, 0x038E, 0x00CA, 0x0FBB, 0x0005,</div><div class='add'>+	0x0FF4, 0x0FED, 0x0388, 0x00DA, 0x0FB8, 0x0005,</div><div class='add'>+	0x0FF6, 0x0FE4, 0x0381, 0x00EB, 0x0FB4, 0x0006,</div><div class='add'>+	0x0FF9, 0x0FDB, 0x037A, 0x00FA, 0x0FB1, 0x0007,</div><div class='add'>+	0x0FFB, 0x0FD3, 0x0372, 0x010B, 0x0FAD, 0x0008,</div><div class='add'>+	0x0FFD, 0x0FCB, 0x0369, 0x011D, 0x0FAA, 0x0008,</div><div class='add'>+	0x0000, 0x0FC3, 0x0360, 0x012E, 0x0FA6, 0x0009,</div><div class='add'>+	0x0002, 0x0FBC, 0x0356, 0x013F, 0x0FA3, 0x000A,</div><div class='add'>+	0x0003, 0x0FB6, 0x034C, 0x0150, 0x0FA0, 0x000B,</div><div class='add'>+	0x0005, 0x0FB0, 0x0341, 0x0162, 0x0F9D, 0x000B,</div><div class='add'>+	0x0007, 0x0FAA, 0x0336, 0x0173, 0x0F9A, 0x000C,</div><div class='add'>+	0x0008, 0x0FA5, 0x032A, 0x0185, 0x0F97, 0x000D,</div><div class='add'>+	0x000A, 0x0FA0, 0x031E, 0x0197, 0x0F94, 0x000D,</div><div class='add'>+	0x000B, 0x0F9B, 0x0311, 0x01A9, 0x0F92, 0x000E,</div><div class='add'>+	0x000C, 0x0F97, 0x0303, 0x01BC, 0x0F8F, 0x000F,</div><div class='add'>+	0x000D, 0x0F94, 0x02F6, 0x01CD, 0x0F8D, 0x000F,</div><div class='add'>+	0x000E, 0x0F91, 0x02E8, 0x01DE, 0x0F8B, 0x0010,</div><div class='add'>+	0x000F, 0x0F8E, 0x02D9, 0x01F1, 0x0F89, 0x0010,</div><div class='add'>+	0x0010, 0x0F8B, 0x02CA, 0x0202, 0x0F88, 0x0011,</div><div class='add'>+	0x0010, 0x0F89, 0x02BB, 0x0214, 0x0F87, 0x0011,</div><div class='add'>+	0x0011, 0x0F87, 0x02AB, 0x0226, 0x0F86, 0x0011,</div><div class='add'>+	0x0011, 0x0F86, 0x029C, 0x0236, 0x0F85, 0x0012,</div><div class='add'>+	0x0011, 0x0F85, 0x028B, 0x0249, 0x0F84, 0x0012,</div><div class='add'>+	0x0012, 0x0F84, 0x027B, 0x0259, 0x0F84, 0x0012,</div><div class='add'>+	0x0012, 0x0F84, 0x026A, 0x026A, 0x0F84, 0x0012,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//========================================================</div><div class='add'>+// &lt;using&gt;			gen_scaler_coeffs_cnf_file.m</div><div class='add'>+// &lt;using&gt;			make_test_script.m</div><div class='add'>+// &lt;date&gt;			02-Apr-2024</div><div class='add'>+// &lt;coeffDescrip&gt;	6t_64p_LanczosEd_p_1_p_10qb_</div><div class='add'>+// &lt;num_taps&gt;		6</div><div class='add'>+// &lt;num_phases&gt;		64</div><div class='add'>+// &lt;scale_ratio&gt;	 input/output = 1.000000000000</div><div class='add'>+// &lt;CoefType&gt;		LanczosEd</div><div class='add'>+// &lt;CoefQuant&gt;		S1.10</div><div class='add'>+//========================================================</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_1_00[198] = {</div><div class='add'>+	0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000,</div><div class='add'>+	0x0003, 0x0FF3, 0x0400, 0x000D, 0x0FFD, 0x0000,</div><div class='add'>+	0x0006, 0x0FE7, 0x03FE, 0x001C, 0x0FF9, 0x0000,</div><div class='add'>+	0x0009, 0x0FDB, 0x03FC, 0x002B, 0x0FF5, 0x0000,</div><div class='add'>+	0x000C, 0x0FD0, 0x03F9, 0x003A, 0x0FF1, 0x0000,</div><div class='add'>+	0x000E, 0x0FC5, 0x03F5, 0x004A, 0x0FED, 0x0001,</div><div class='add'>+	0x0011, 0x0FBB, 0x03F0, 0x005A, 0x0FE9, 0x0001,</div><div class='add'>+	0x0013, 0x0FB2, 0x03EB, 0x006A, 0x0FE5, 0x0001,</div><div class='add'>+	0x0015, 0x0FA9, 0x03E4, 0x007B, 0x0FE1, 0x0002,</div><div class='add'>+	0x0017, 0x0FA1, 0x03DD, 0x008D, 0x0FDC, 0x0002,</div><div class='add'>+	0x0018, 0x0F99, 0x03D4, 0x00A0, 0x0FD8, 0x0003,</div><div class='add'>+	0x001A, 0x0F92, 0x03CB, 0x00B2, 0x0FD3, 0x0004,</div><div class='add'>+	0x001B, 0x0F8C, 0x03C1, 0x00C6, 0x0FCE, 0x0004,</div><div class='add'>+	0x001C, 0x0F86, 0x03B7, 0x00D9, 0x0FC9, 0x0005,</div><div class='add'>+	0x001D, 0x0F80, 0x03AB, 0x00EE, 0x0FC4, 0x0006,</div><div class='add'>+	0x001E, 0x0F7C, 0x039F, 0x0101, 0x0FBF, 0x0007,</div><div class='add'>+	0x001F, 0x0F78, 0x0392, 0x0115, 0x0FBA, 0x0008,</div><div class='add'>+	0x001F, 0x0F74, 0x0385, 0x012B, 0x0FB5, 0x0008,</div><div class='add'>+	0x0020, 0x0F71, 0x0376, 0x0140, 0x0FB0, 0x0009,</div><div class='add'>+	0x0020, 0x0F6E, 0x0367, 0x0155, 0x0FAB, 0x000B,</div><div class='add'>+	0x0020, 0x0F6C, 0x0357, 0x016B, 0x0FA6, 0x000C,</div><div class='add'>+	0x0020, 0x0F6A, 0x0347, 0x0180, 0x0FA2, 0x000D,</div><div class='add'>+	0x0020, 0x0F69, 0x0336, 0x0196, 0x0F9D, 0x000E,</div><div class='add'>+	0x0020, 0x0F69, 0x0325, 0x01AB, 0x0F98, 0x000F,</div><div class='add'>+	0x001F, 0x0F68, 0x0313, 0x01C3, 0x0F93, 0x0010,</div><div class='add'>+	0x001F, 0x0F69, 0x0300, 0x01D8, 0x0F8F, 0x0011,</div><div class='add'>+	0x001E, 0x0F69, 0x02ED, 0x01EF, 0x0F8B, 0x0012,</div><div class='add'>+	0x001D, 0x0F6A, 0x02D9, 0x0205, 0x0F87, 0x0014,</div><div class='add'>+	0x001D, 0x0F6C, 0x02C5, 0x021A, 0x0F83, 0x0015,</div><div class='add'>+	0x001C, 0x0F6E, 0x02B1, 0x0230, 0x0F7F, 0x0016,</div><div class='add'>+	0x001B, 0x0F70, 0x029C, 0x0247, 0x0F7B, 0x0017,</div><div class='add'>+	0x001A, 0x0F72, 0x0287, 0x025D, 0x0F78, 0x0018,</div><div class='add'>+	0x0019, 0x0F75, 0x0272, 0x0272, 0x0F75, 0x0019,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Converted scaler coeff tables from S1.10 to S1.12 */</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_30_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07d8, 0x0818, 0x0010,</div><div class='add'>+0x07b0, 0x082c, 0x0024,</div><div class='add'>+0x0788, 0x0844, 0x0034,</div><div class='add'>+0x0760, 0x0858, 0x0048,</div><div class='add'>+0x0738, 0x0870, 0x0058,</div><div class='add'>+0x0710, 0x0884, 0x006c,</div><div class='add'>+0x06e8, 0x0898, 0x0080,</div><div class='add'>+0x06c0, 0x08a8, 0x0098,</div><div class='add'>+0x0698, 0x08bc, 0x00ac,</div><div class='add'>+0x0670, 0x08cc, 0x00c4,</div><div class='add'>+0x0648, 0x08e0, 0x00d8,</div><div class='add'>+0x0620, 0x08f0, 0x00f0,</div><div class='add'>+0x05f8, 0x0900, 0x0108,</div><div class='add'>+0x05d0, 0x0910, 0x0120,</div><div class='add'>+0x05a8, 0x0920, 0x0138,</div><div class='add'>+0x0584, 0x0928, 0x0154,</div><div class='add'>+0x055c, 0x0938, 0x016c,</div><div class='add'>+0x0534, 0x0944, 0x0188,</div><div class='add'>+0x0510, 0x094c, 0x01a4,</div><div class='add'>+0x04e8, 0x0958, 0x01c0,</div><div class='add'>+0x04c4, 0x0960, 0x01dc,</div><div class='add'>+0x049c, 0x096c, 0x01f8,</div><div class='add'>+0x0478, 0x0970, 0x0218,</div><div class='add'>+0x0454, 0x0978, 0x0234,</div><div class='add'>+0x042c, 0x0980, 0x0254,</div><div class='add'>+0x0408, 0x0988, 0x0270,</div><div class='add'>+0x03e4, 0x098c, 0x0290,</div><div class='add'>+0x03c0, 0x0990, 0x02b0,</div><div class='add'>+0x039c, 0x0994, 0x02d0,</div><div class='add'>+0x037c, 0x0990, 0x02f4,</div><div class='add'>+0x0358, 0x0994, 0x0314,</div><div class='add'>+0x0334, 0x0998, 0x0334,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_40_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07d8, 0x0818, 0x0010,</div><div class='add'>+0x07ac, 0x0838, 0x001c,</div><div class='add'>+0x0784, 0x0850, 0x002c,</div><div class='add'>+0x075c, 0x0868, 0x003c,</div><div class='add'>+0x0734, 0x0880, 0x004c,</div><div class='add'>+0x0708, 0x0898, 0x0060,</div><div class='add'>+0x06e0, 0x08b0, 0x0070,</div><div class='add'>+0x06b8, 0x08c4, 0x0084,</div><div class='add'>+0x068c, 0x08dc, 0x0098,</div><div class='add'>+0x0664, 0x08f0, 0x00ac,</div><div class='add'>+0x063c, 0x0900, 0x00c4,</div><div class='add'>+0x0614, 0x0914, 0x00d8,</div><div class='add'>+0x05e8, 0x0928, 0x00f0,</div><div class='add'>+0x05c0, 0x093c, 0x0104,</div><div class='add'>+0x0598, 0x094c, 0x011c,</div><div class='add'>+0x0570, 0x095c, 0x0134,</div><div class='add'>+0x0548, 0x0968, 0x0150,</div><div class='add'>+0x0520, 0x0978, 0x0168,</div><div class='add'>+0x04f8, 0x0984, 0x0184,</div><div class='add'>+0x04d0, 0x0990, 0x01a0,</div><div class='add'>+0x04ac, 0x0998, 0x01bc,</div><div class='add'>+0x0484, 0x09a4, 0x01d8,</div><div class='add'>+0x045c, 0x09b0, 0x01f4,</div><div class='add'>+0x0438, 0x09b8, 0x0210,</div><div class='add'>+0x0410, 0x09c0, 0x0230,</div><div class='add'>+0x03ec, 0x09c4, 0x0250,</div><div class='add'>+0x03c8, 0x09c8, 0x0270,</div><div class='add'>+0x03a4, 0x09cc, 0x0290,</div><div class='add'>+0x0380, 0x09d0, 0x02b0,</div><div class='add'>+0x035c, 0x09d4, 0x02d0,</div><div class='add'>+0x0338, 0x09d4, 0x02f4,</div><div class='add'>+0x0314, 0x09d8, 0x0314,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_50_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07d4, 0x0824, 0x0008,</div><div class='add'>+0x07a8, 0x0844, 0x0014,</div><div class='add'>+0x077c, 0x0868, 0x001c,</div><div class='add'>+0x0750, 0x0888, 0x0028,</div><div class='add'>+0x0724, 0x08a8, 0x0034,</div><div class='add'>+0x06f8, 0x08c8, 0x0040,</div><div class='add'>+0x06cc, 0x08e4, 0x0050,</div><div class='add'>+0x06a0, 0x0904, 0x005c,</div><div class='add'>+0x0674, 0x0920, 0x006c,</div><div class='add'>+0x0648, 0x093c, 0x007c,</div><div class='add'>+0x061c, 0x0954, 0x0090,</div><div class='add'>+0x05f0, 0x0970, 0x00a0,</div><div class='add'>+0x05c4, 0x0988, 0x00b4,</div><div class='add'>+0x0598, 0x09a0, 0x00c8,</div><div class='add'>+0x056c, 0x09b8, 0x00dc,</div><div class='add'>+0x0540, 0x09cc, 0x00f4,</div><div class='add'>+0x0518, 0x09e0, 0x0108,</div><div class='add'>+0x04ec, 0x09f4, 0x0120,</div><div class='add'>+0x04c0, 0x0a08, 0x0138,</div><div class='add'>+0x0498, 0x0a18, 0x0150,</div><div class='add'>+0x046c, 0x0a28, 0x016c,</div><div class='add'>+0x0444, 0x0a34, 0x0188,</div><div class='add'>+0x041c, 0x0a40, 0x01a4,</div><div class='add'>+0x03f4, 0x0a4c, 0x01c0,</div><div class='add'>+0x03cc, 0x0a58, 0x01dc,</div><div class='add'>+0x03a4, 0x0a60, 0x01fc,</div><div class='add'>+0x037c, 0x0a68, 0x021c,</div><div class='add'>+0x0354, 0x0a70, 0x023c,</div><div class='add'>+0x0330, 0x0a74, 0x025c,</div><div class='add'>+0x030c, 0x0a78, 0x027c,</div><div class='add'>+0x02e8, 0x0a78, 0x02a0,</div><div class='add'>+0x02c4, 0x0a78, 0x02c4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_60_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07d0, 0x082c, 0x0004,</div><div class='add'>+0x07a0, 0x0858, 0x0008,</div><div class='add'>+0x0770, 0x0884, 0x000c,</div><div class='add'>+0x0740, 0x08ac, 0x0014,</div><div class='add'>+0x0710, 0x08d4, 0x001c,</div><div class='add'>+0x06e0, 0x0900, 0x0020,</div><div class='add'>+0x06b0, 0x0924, 0x002c,</div><div class='add'>+0x0680, 0x094c, 0x0034,</div><div class='add'>+0x0650, 0x0970, 0x0040,</div><div class='add'>+0x0620, 0x0994, 0x004c,</div><div class='add'>+0x05f0, 0x09b8, 0x0058,</div><div class='add'>+0x05c0, 0x09dc, 0x0064,</div><div class='add'>+0x0590, 0x09fc, 0x0074,</div><div class='add'>+0x0560, 0x0a1c, 0x0084,</div><div class='add'>+0x0530, 0x0a3c, 0x0094,</div><div class='add'>+0x0500, 0x0a5c, 0x00a4,</div><div class='add'>+0x04d4, 0x0a74, 0x00b8,</div><div class='add'>+0x04a4, 0x0a90, 0x00cc,</div><div class='add'>+0x0474, 0x0aac, 0x00e0,</div><div class='add'>+0x0448, 0x0ac0, 0x00f8,</div><div class='add'>+0x041c, 0x0ad4, 0x0110,</div><div class='add'>+0x03f0, 0x0ae8, 0x0128,</div><div class='add'>+0x03c4, 0x0afc, 0x0140,</div><div class='add'>+0x0398, 0x0b0c, 0x015c,</div><div class='add'>+0x036c, 0x0b1c, 0x0178,</div><div class='add'>+0x0344, 0x0b28, 0x0194,</div><div class='add'>+0x031c, 0x0b30, 0x01b4,</div><div class='add'>+0x02f4, 0x0b38, 0x01d4,</div><div class='add'>+0x02cc, 0x0b40, 0x01f4,</div><div class='add'>+0x02a4, 0x0b48, 0x0214,</div><div class='add'>+0x0280, 0x0b48, 0x0238,</div><div class='add'>+0x025c, 0x0b48, 0x025c,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_70_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07cc, 0x0834, 0x0000,</div><div class='add'>+0x0794, 0x086c, 0x0000,</div><div class='add'>+0x0760, 0x08a0, 0x0000,</div><div class='add'>+0x072c, 0x08d4, 0x0000,</div><div class='add'>+0x06f4, 0x090c, 0x0000,</div><div class='add'>+0x06c0, 0x093c, 0x0004,</div><div class='add'>+0x0688, 0x0970, 0x0008,</div><div class='add'>+0x0654, 0x09a0, 0x000c,</div><div class='add'>+0x061c, 0x09d4, 0x0010,</div><div class='add'>+0x05e8, 0x0a00, 0x0018,</div><div class='add'>+0x05b4, 0x0a30, 0x001c,</div><div class='add'>+0x057c, 0x0a60, 0x0024,</div><div class='add'>+0x0548, 0x0a88, 0x0030,</div><div class='add'>+0x0514, 0x0ab4, 0x0038,</div><div class='add'>+0x04e0, 0x0adc, 0x0044,</div><div class='add'>+0x04ac, 0x0b00, 0x0054,</div><div class='add'>+0x0478, 0x0b28, 0x0060,</div><div class='add'>+0x0444, 0x0b4c, 0x0070,</div><div class='add'>+0x0414, 0x0b6c, 0x0080,</div><div class='add'>+0x03e0, 0x0b8c, 0x0094,</div><div class='add'>+0x03b0, 0x0ba8, 0x00a8,</div><div class='add'>+0x0380, 0x0bc4, 0x00bc,</div><div class='add'>+0x0354, 0x0bd8, 0x00d4,</div><div class='add'>+0x0324, 0x0bf0, 0x00ec,</div><div class='add'>+0x02f8, 0x0c04, 0x0104,</div><div class='add'>+0x02cc, 0x0c14, 0x0120,</div><div class='add'>+0x02a0, 0x0c24, 0x013c,</div><div class='add'>+0x0278, 0x0c30, 0x0158,</div><div class='add'>+0x0250, 0x0c38, 0x0178,</div><div class='add'>+0x0228, 0x0c40, 0x0198,</div><div class='add'>+0x0204, 0x0c40, 0x01bc,</div><div class='add'>+0x01dc, 0x0c48, 0x01dc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_80_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07c4, 0x0840, 0x3ffc,</div><div class='add'>+0x0788, 0x0880, 0x3ff8,</div><div class='add'>+0x0748, 0x08c8, 0x3ff0,</div><div class='add'>+0x070c, 0x0904, 0x3ff0,</div><div class='add'>+0x06d0, 0x0944, 0x3fec,</div><div class='add'>+0x0690, 0x0988, 0x3fe8,</div><div class='add'>+0x0654, 0x09c4, 0x3fe8,</div><div class='add'>+0x0618, 0x0a04, 0x3fe4,</div><div class='add'>+0x05d8, 0x0a44, 0x3fe4,</div><div class='add'>+0x059c, 0x0a80, 0x3fe4,</div><div class='add'>+0x0560, 0x0ab8, 0x3fe8,</div><div class='add'>+0x0524, 0x0af4, 0x3fe8,</div><div class='add'>+0x04e8, 0x0b2c, 0x3fec,</div><div class='add'>+0x04b0, 0x0b5c, 0x3ff4,</div><div class='add'>+0x0474, 0x0b94, 0x3ff8,</div><div class='add'>+0x043c, 0x0bc4, 0x0000,</div><div class='add'>+0x0404, 0x0bf4, 0x0008,</div><div class='add'>+0x03cc, 0x0c20, 0x0014,</div><div class='add'>+0x0394, 0x0c4c, 0x0020,</div><div class='add'>+0x0360, 0x0c74, 0x002c,</div><div class='add'>+0x032c, 0x0c98, 0x003c,</div><div class='add'>+0x02f8, 0x0cbc, 0x004c,</div><div class='add'>+0x02c8, 0x0cdc, 0x005c,</div><div class='add'>+0x0298, 0x0cf8, 0x0070,</div><div class='add'>+0x0268, 0x0d14, 0x0084,</div><div class='add'>+0x023c, 0x0d28, 0x009c,</div><div class='add'>+0x0210, 0x0d3c, 0x00b4,</div><div class='add'>+0x01e4, 0x0d4c, 0x00d0,</div><div class='add'>+0x01bc, 0x0d58, 0x00ec,</div><div class='add'>+0x0194, 0x0d60, 0x010c,</div><div class='add'>+0x0170, 0x0d64, 0x012c,</div><div class='add'>+0x014c, 0x0d68, 0x014c,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_0_90_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07b8, 0x0850, 0x3ff8,</div><div class='add'>+0x0770, 0x08a0, 0x3ff0,</div><div class='add'>+0x0728, 0x08f0, 0x3fe8,</div><div class='add'>+0x06e4, 0x093c, 0x3fe0,</div><div class='add'>+0x069c, 0x0988, 0x3fdc,</div><div class='add'>+0x0654, 0x09d8, 0x3fd4,</div><div class='add'>+0x060c, 0x0a28, 0x3fcc,</div><div class='add'>+0x05c8, 0x0a70, 0x3fc8,</div><div class='add'>+0x0580, 0x0abc, 0x3fc4,</div><div class='add'>+0x053c, 0x0b08, 0x3fbc,</div><div class='add'>+0x04f8, 0x0b50, 0x3fb8,</div><div class='add'>+0x04b4, 0x0b94, 0x3fb8,</div><div class='add'>+0x0470, 0x0bdc, 0x3fb4,</div><div class='add'>+0x0430, 0x0c1c, 0x3fb4,</div><div class='add'>+0x03ec, 0x0c60, 0x3fb4,</div><div class='add'>+0x03b0, 0x0c9c, 0x3fb4,</div><div class='add'>+0x0370, 0x0cd8, 0x3fb8,</div><div class='add'>+0x0334, 0x0d10, 0x3fbc,</div><div class='add'>+0x02f8, 0x0d48, 0x3fc0,</div><div class='add'>+0x02c0, 0x0d78, 0x3fc8,</div><div class='add'>+0x0288, 0x0da8, 0x3fd0,</div><div class='add'>+0x0254, 0x0dd4, 0x3fd8,</div><div class='add'>+0x0220, 0x0dfc, 0x3fe4,</div><div class='add'>+0x01ec, 0x0e20, 0x3ff4,</div><div class='add'>+0x01bc, 0x0e44, 0x0000,</div><div class='add'>+0x0190, 0x0e5c, 0x0014,</div><div class='add'>+0x0164, 0x0e74, 0x0028,</div><div class='add'>+0x0138, 0x0e8c, 0x003c,</div><div class='add'>+0x0114, 0x0e98, 0x0054,</div><div class='add'>+0x00ec, 0x0ea4, 0x0070,</div><div class='add'>+0x00cc, 0x0ea8, 0x008c,</div><div class='add'>+0x00a8, 0x0eb0, 0x00a8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_3tap_64p_ratio_1_00_s1_12[99] = {</div><div class='add'>+0x0800, 0x0800, 0x0000,</div><div class='add'>+0x07ac, 0x085c, 0x3ff8,</div><div class='add'>+0x0754, 0x08bc, 0x3ff0,</div><div class='add'>+0x0700, 0x091c, 0x3fe4,</div><div class='add'>+0x06ac, 0x0978, 0x3fdc,</div><div class='add'>+0x0658, 0x09d8, 0x3fd0,</div><div class='add'>+0x0604, 0x0a34, 0x3fc8,</div><div class='add'>+0x05b0, 0x0a94, 0x3fbc,</div><div class='add'>+0x0560, 0x0aec, 0x3fb4,</div><div class='add'>+0x0510, 0x0b44, 0x3fac,</div><div class='add'>+0x04c0, 0x0ba0, 0x3fa0,</div><div class='add'>+0x0470, 0x0bf8, 0x3f98,</div><div class='add'>+0x0424, 0x0c4c, 0x3f90,</div><div class='add'>+0x03d8, 0x0ca0, 0x3f88,</div><div class='add'>+0x0390, 0x0cf0, 0x3f80,</div><div class='add'>+0x0348, 0x0d3c, 0x3f7c,</div><div class='add'>+0x0300, 0x0d8c, 0x3f74,</div><div class='add'>+0x02c0, 0x0dd0, 0x3f70,</div><div class='add'>+0x027c, 0x0e14, 0x3f70,</div><div class='add'>+0x0240, 0x0e54, 0x3f6c,</div><div class='add'>+0x0204, 0x0e90, 0x3f6c,</div><div class='add'>+0x01c8, 0x0ecc, 0x3f6c,</div><div class='add'>+0x0190, 0x0f00, 0x3f70,</div><div class='add'>+0x015c, 0x0f30, 0x3f74,</div><div class='add'>+0x012c, 0x0f58, 0x3f7c,</div><div class='add'>+0x00fc, 0x0f80, 0x3f84,</div><div class='add'>+0x00d0, 0x0fa0, 0x3f90,</div><div class='add'>+0x00a8, 0x0fbc, 0x3f9c,</div><div class='add'>+0x0080, 0x0fd4, 0x3fac,</div><div class='add'>+0x005c, 0x0fe8, 0x3fbc,</div><div class='add'>+0x003c, 0x0ff4, 0x3fd0,</div><div class='add'>+0x001c, 0x0ffc, 0x3fe8,</div><div class='add'>+0x0000, 0x1000, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_30_s1_12[132] = {</div><div class='add'>+0x0410, 0x07e0, 0x0410, 0x0000,</div><div class='add'>+0x03f8, 0x07dc, 0x0428, 0x0004,</div><div class='add'>+0x03e0, 0x07d8, 0x043c, 0x000c,</div><div class='add'>+0x03c8, 0x07d4, 0x0450, 0x0014,</div><div class='add'>+0x03ac, 0x07d0, 0x046c, 0x0018,</div><div class='add'>+0x0394, 0x07cc, 0x0480, 0x0020,</div><div class='add'>+0x037c, 0x07c8, 0x0494, 0x0028,</div><div class='add'>+0x0368, 0x07c0, 0x04a8, 0x0030,</div><div class='add'>+0x0350, 0x07b8, 0x04c0, 0x0038,</div><div class='add'>+0x0338, 0x07b4, 0x04d4, 0x0040,</div><div class='add'>+0x0320, 0x07ac, 0x04e8, 0x004c,</div><div class='add'>+0x0308, 0x07a4, 0x0500, 0x0054,</div><div class='add'>+0x02f4, 0x079c, 0x0514, 0x005c,</div><div class='add'>+0x02dc, 0x0794, 0x0528, 0x0068,</div><div class='add'>+0x02c4, 0x0788, 0x0544, 0x0070,</div><div class='add'>+0x02b0, 0x0780, 0x0554, 0x007c,</div><div class='add'>+0x029c, 0x0774, 0x0568, 0x0088,</div><div class='add'>+0x0284, 0x076c, 0x057c, 0x0094,</div><div class='add'>+0x0270, 0x0760, 0x0594, 0x009c,</div><div class='add'>+0x025c, 0x0754, 0x05a8, 0x00a8,</div><div class='add'>+0x0248, 0x0748, 0x05b8, 0x00b8,</div><div class='add'>+0x0230, 0x073c, 0x05d0, 0x00c4,</div><div class='add'>+0x021c, 0x0730, 0x05e4, 0x00d0,</div><div class='add'>+0x020c, 0x0724, 0x05f4, 0x00dc,</div><div class='add'>+0x01f8, 0x0714, 0x0608, 0x00ec,</div><div class='add'>+0x01e4, 0x0708, 0x061c, 0x00f8,</div><div class='add'>+0x01d0, 0x06f8, 0x0630, 0x0108,</div><div class='add'>+0x01c0, 0x06e8, 0x0640, 0x0118,</div><div class='add'>+0x01ac, 0x06dc, 0x0654, 0x0124,</div><div class='add'>+0x0198, 0x06cc, 0x0668, 0x0134,</div><div class='add'>+0x0188, 0x06bc, 0x0678, 0x0144,</div><div class='add'>+0x0178, 0x06ac, 0x0688, 0x0154,</div><div class='add'>+0x0168, 0x0698, 0x0698, 0x0168,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_40_s1_12[132] = {</div><div class='add'>+0x03ec, 0x0824, 0x03f0, 0x0000,</div><div class='add'>+0x03d4, 0x0824, 0x0404, 0x0004,</div><div class='add'>+0x03b8, 0x0820, 0x0420, 0x0008,</div><div class='add'>+0x03a0, 0x081c, 0x0438, 0x000c,</div><div class='add'>+0x0388, 0x0818, 0x0450, 0x0010,</div><div class='add'>+0x036c, 0x0814, 0x0468, 0x0018,</div><div class='add'>+0x0354, 0x0810, 0x0480, 0x001c,</div><div class='add'>+0x033c, 0x080c, 0x0494, 0x0024,</div><div class='add'>+0x0324, 0x0804, 0x04b0, 0x0028,</div><div class='add'>+0x030c, 0x07fc, 0x04c8, 0x0030,</div><div class='add'>+0x02f4, 0x07f4, 0x04e0, 0x0038,</div><div class='add'>+0x02dc, 0x07ec, 0x04f8, 0x0040,</div><div class='add'>+0x02c4, 0x07e4, 0x0510, 0x0048,</div><div class='add'>+0x02b0, 0x07dc, 0x0524, 0x0050,</div><div class='add'>+0x0298, 0x07d0, 0x0540, 0x0058,</div><div class='add'>+0x0280, 0x07c8, 0x0558, 0x0060,</div><div class='add'>+0x026c, 0x07bc, 0x0570, 0x0068,</div><div class='add'>+0x0254, 0x07b0, 0x0588, 0x0074,</div><div class='add'>+0x0240, 0x07a4, 0x05a0, 0x007c,</div><div class='add'>+0x022c, 0x0798, 0x05b4, 0x0088,</div><div class='add'>+0x0214, 0x078c, 0x05cc, 0x0094,</div><div class='add'>+0x0200, 0x077c, 0x05e4, 0x00a0,</div><div class='add'>+0x01ec, 0x0770, 0x05f8, 0x00ac,</div><div class='add'>+0x01d8, 0x0760, 0x0610, 0x00b8,</div><div class='add'>+0x01c4, 0x0750, 0x0628, 0x00c4,</div><div class='add'>+0x01b4, 0x0744, 0x0638, 0x00d0,</div><div class='add'>+0x01a0, 0x0734, 0x064c, 0x00e0,</div><div class='add'>+0x018c, 0x0720, 0x0668, 0x00ec,</div><div class='add'>+0x017c, 0x0710, 0x0678, 0x00fc,</div><div class='add'>+0x016c, 0x0700, 0x068c, 0x0108,</div><div class='add'>+0x0158, 0x06ec, 0x06a4, 0x0118,</div><div class='add'>+0x0148, 0x06dc, 0x06b4, 0x0128,</div><div class='add'>+0x0138, 0x06c8, 0x06c8, 0x0138,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_50_s1_12[132] = {</div><div class='add'>+0x0394, 0x08d8, 0x0394, 0x0000,</div><div class='add'>+0x0378, 0x08d4, 0x03b4, 0x0000,</div><div class='add'>+0x035c, 0x08d4, 0x03d0, 0x0000,</div><div class='add'>+0x0340, 0x08d4, 0x03ec, 0x0000,</div><div class='add'>+0x0324, 0x08d0, 0x0408, 0x0004,</div><div class='add'>+0x0308, 0x08cc, 0x0428, 0x0004,</div><div class='add'>+0x02f0, 0x08c8, 0x0444, 0x0004,</div><div class='add'>+0x02d4, 0x08c0, 0x0464, 0x0008,</div><div class='add'>+0x02b8, 0x08bc, 0x0484, 0x0008,</div><div class='add'>+0x02a0, 0x08b4, 0x04a0, 0x000c,</div><div class='add'>+0x0288, 0x08ac, 0x04bc, 0x0010,</div><div class='add'>+0x026c, 0x08a4, 0x04dc, 0x0014,</div><div class='add'>+0x0254, 0x0898, 0x04fc, 0x0018,</div><div class='add'>+0x023c, 0x0890, 0x0518, 0x001c,</div><div class='add'>+0x0224, 0x0884, 0x0538, 0x0020,</div><div class='add'>+0x020c, 0x0878, 0x0554, 0x0028,</div><div class='add'>+0x01f8, 0x086c, 0x0570, 0x002c,</div><div class='add'>+0x01e0, 0x085c, 0x0590, 0x0034,</div><div class='add'>+0x01c8, 0x084c, 0x05b4, 0x0038,</div><div class='add'>+0x01b4, 0x0840, 0x05cc, 0x0040,</div><div class='add'>+0x01a0, 0x0830, 0x05e8, 0x0048,</div><div class='add'>+0x018c, 0x081c, 0x0608, 0x0050,</div><div class='add'>+0x0178, 0x080c, 0x0624, 0x0058,</div><div class='add'>+0x0164, 0x07f8, 0x0644, 0x0060,</div><div class='add'>+0x0150, 0x07e4, 0x0660, 0x006c,</div><div class='add'>+0x0140, 0x07d0, 0x067c, 0x0074,</div><div class='add'>+0x012c, 0x07bc, 0x0698, 0x0080,</div><div class='add'>+0x011c, 0x07a8, 0x06b0, 0x008c,</div><div class='add'>+0x010c, 0x0790, 0x06cc, 0x0098,</div><div class='add'>+0x00fc, 0x077c, 0x06e4, 0x00a4,</div><div class='add'>+0x00ec, 0x0764, 0x0700, 0x00b0,</div><div class='add'>+0x00dc, 0x074c, 0x0718, 0x00c0,</div><div class='add'>+0x00cc, 0x0734, 0x0734, 0x00cc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_60_s1_12[132] = {</div><div class='add'>+0x0320, 0x09bc, 0x0324, 0x0000,</div><div class='add'>+0x0300, 0x09c0, 0x0344, 0x3ffc,</div><div class='add'>+0x02e0, 0x09c0, 0x0364, 0x3ffc,</div><div class='add'>+0x02c4, 0x09c0, 0x0384, 0x3ff8,</div><div class='add'>+0x02a4, 0x09bc, 0x03ac, 0x3ff4,</div><div class='add'>+0x0288, 0x09b8, 0x03cc, 0x3ff4,</div><div class='add'>+0x0268, 0x09b4, 0x03f4, 0x3ff0,</div><div class='add'>+0x024c, 0x09b0, 0x0414, 0x3ff0,</div><div class='add'>+0x0230, 0x09a8, 0x043c, 0x3fec,</div><div class='add'>+0x0214, 0x09a0, 0x0460, 0x3fec,</div><div class='add'>+0x01f8, 0x0994, 0x0488, 0x3fec,</div><div class='add'>+0x01e0, 0x098c, 0x04a8, 0x3fec,</div><div class='add'>+0x01c4, 0x0980, 0x04d0, 0x3fec,</div><div class='add'>+0x01ac, 0x0970, 0x04f8, 0x3fec,</div><div class='add'>+0x0194, 0x0964, 0x051c, 0x3fec,</div><div class='add'>+0x017c, 0x0954, 0x0544, 0x3fec,</div><div class='add'>+0x0164, 0x0944, 0x0568, 0x3ff0,</div><div class='add'>+0x0150, 0x0934, 0x058c, 0x3ff0,</div><div class='add'>+0x0138, 0x0920, 0x05b4, 0x3ff4,</div><div class='add'>+0x0124, 0x090c, 0x05d8, 0x3ff8,</div><div class='add'>+0x0110, 0x08f8, 0x05fc, 0x3ffc,</div><div class='add'>+0x00fc, 0x08e0, 0x0624, 0x0000,</div><div class='add'>+0x00e8, 0x08c8, 0x064c, 0x0004,</div><div class='add'>+0x00d8, 0x08b0, 0x0670, 0x0008,</div><div class='add'>+0x00c4, 0x0898, 0x0694, 0x0010,</div><div class='add'>+0x00b4, 0x087c, 0x06bc, 0x0014,</div><div class='add'>+0x00a4, 0x0860, 0x06e0, 0x001c,</div><div class='add'>+0x0094, 0x0844, 0x0704, 0x0024,</div><div class='add'>+0x0088, 0x0828, 0x0724, 0x002c,</div><div class='add'>+0x0078, 0x080c, 0x0748, 0x0034,</div><div class='add'>+0x006c, 0x07ec, 0x0768, 0x0040,</div><div class='add'>+0x0060, 0x07cc, 0x078c, 0x0048,</div><div class='add'>+0x0054, 0x07ac, 0x07ac, 0x0054,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_70_s1_12[132] = {</div><div class='add'>+0x028c, 0x0ae4, 0x0290, 0x0000,</div><div class='add'>+0x0268, 0x0ae8, 0x02b4, 0x3ffc,</div><div class='add'>+0x0248, 0x0ae8, 0x02d8, 0x3ff8,</div><div class='add'>+0x0224, 0x0ae8, 0x0304, 0x3ff0,</div><div class='add'>+0x0204, 0x0ae4, 0x032c, 0x3fec,</div><div class='add'>+0x01e4, 0x0ae0, 0x0354, 0x3fe8,</div><div class='add'>+0x01c4, 0x0adc, 0x037c, 0x3fe4,</div><div class='add'>+0x01a4, 0x0ad4, 0x03a8, 0x3fe0,</div><div class='add'>+0x0188, 0x0acc, 0x03d0, 0x3fdc,</div><div class='add'>+0x016c, 0x0ac0, 0x03fc, 0x3fd8,</div><div class='add'>+0x0150, 0x0ab4, 0x042c, 0x3fd0,</div><div class='add'>+0x0134, 0x0aa4, 0x045c, 0x3fcc,</div><div class='add'>+0x0118, 0x0a94, 0x048c, 0x3fc8,</div><div class='add'>+0x0100, 0x0a84, 0x04b4, 0x3fc8,</div><div class='add'>+0x00e8, 0x0a70, 0x04e4, 0x3fc4,</div><div class='add'>+0x00d0, 0x0a5c, 0x0514, 0x3fc0,</div><div class='add'>+0x00bc, 0x0a48, 0x0540, 0x3fbc,</div><div class='add'>+0x00a4, 0x0a30, 0x0570, 0x3fbc,</div><div class='add'>+0x0090, 0x0a14, 0x05a4, 0x3fb8,</div><div class='add'>+0x007c, 0x09fc, 0x05d0, 0x3fb8,</div><div class='add'>+0x006c, 0x09e0, 0x05fc, 0x3fb8,</div><div class='add'>+0x0058, 0x09c0, 0x0634, 0x3fb4,</div><div class='add'>+0x0048, 0x09a0, 0x0664, 0x3fb4,</div><div class='add'>+0x0038, 0x0980, 0x0690, 0x3fb8,</div><div class='add'>+0x002c, 0x0960, 0x06bc, 0x3fb8,</div><div class='add'>+0x001c, 0x093c, 0x06f0, 0x3fb8,</div><div class='add'>+0x0010, 0x0918, 0x071c, 0x3fbc,</div><div class='add'>+0x0004, 0x08f4, 0x074c, 0x3fbc,</div><div class='add'>+0x3ff8, 0x08cc, 0x077c, 0x3fc0,</div><div class='add'>+0x3ff0, 0x08a4, 0x07a8, 0x3fc4,</div><div class='add'>+0x3fe8, 0x087c, 0x07d0, 0x3fcc,</div><div class='add'>+0x3fe0, 0x0854, 0x07fc, 0x3fd0,</div><div class='add'>+0x3fd8, 0x0828, 0x0828, 0x3fd8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_80_s1_12[132] = {</div><div class='add'>+0x01d4, 0x0c54, 0x01d8, 0x0000,</div><div class='add'>+0x01b0, 0x0c58, 0x01fc, 0x3ffc,</div><div class='add'>+0x0188, 0x0c58, 0x0228, 0x3ff8,</div><div class='add'>+0x0164, 0x0c54, 0x0258, 0x3ff0,</div><div class='add'>+0x0140, 0x0c50, 0x0284, 0x3fec,</div><div class='add'>+0x0120, 0x0c48, 0x02b4, 0x3fe4,</div><div class='add'>+0x0100, 0x0c40, 0x02e0, 0x3fe0,</div><div class='add'>+0x00e0, 0x0c34, 0x0314, 0x3fd8,</div><div class='add'>+0x00c0, 0x0c28, 0x0344, 0x3fd4,</div><div class='add'>+0x00a4, 0x0c18, 0x0378, 0x3fcc,</div><div class='add'>+0x0088, 0x0c04, 0x03ac, 0x3fc8,</div><div class='add'>+0x0070, 0x0bf0, 0x03e0, 0x3fc0,</div><div class='add'>+0x0054, 0x0bdc, 0x0418, 0x3fb8,</div><div class='add'>+0x0040, 0x0bc4, 0x0448, 0x3fb4,</div><div class='add'>+0x0028, 0x0ba8, 0x0484, 0x3fac,</div><div class='add'>+0x0014, 0x0b8c, 0x04bc, 0x3fa4,</div><div class='add'>+0x0000, 0x0b6c, 0x04f4, 0x3fa0,</div><div class='add'>+0x3fec, 0x0b4c, 0x0530, 0x3f98,</div><div class='add'>+0x3fdc, 0x0b28, 0x0568, 0x3f94,</div><div class='add'>+0x3fcc, 0x0b04, 0x05a4, 0x3f8c,</div><div class='add'>+0x3fc0, 0x0adc, 0x05dc, 0x3f88,</div><div class='add'>+0x3fb0, 0x0ab4, 0x0618, 0x3f84,</div><div class='add'>+0x3fa4, 0x0a88, 0x0658, 0x3f7c,</div><div class='add'>+0x3f9c, 0x0a5c, 0x0690, 0x3f78,</div><div class='add'>+0x3f90, 0x0a30, 0x06cc, 0x3f74,</div><div class='add'>+0x3f88, 0x0a00, 0x0708, 0x3f70,</div><div class='add'>+0x3f80, 0x09d0, 0x0740, 0x3f70,</div><div class='add'>+0x3f7c, 0x09a0, 0x0778, 0x3f6c,</div><div class='add'>+0x3f74, 0x096c, 0x07b8, 0x3f68,</div><div class='add'>+0x3f70, 0x0938, 0x07f0, 0x3f68,</div><div class='add'>+0x3f6c, 0x0904, 0x0828, 0x3f68,</div><div class='add'>+0x3f6c, 0x08cc, 0x0860, 0x3f68,</div><div class='add'>+0x3f68, 0x0898, 0x0898, 0x3f68,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_0_90_s1_12[132] = {</div><div class='add'>+0x00fc, 0x0e0c, 0x00f8, 0x0000,</div><div class='add'>+0x00d0, 0x0e0c, 0x0128, 0x3ffc,</div><div class='add'>+0x00ac, 0x0e0c, 0x0150, 0x3ff8,</div><div class='add'>+0x0084, 0x0e04, 0x0184, 0x3ff4,</div><div class='add'>+0x0064, 0x0dfc, 0x01b0, 0x3ff0,</div><div class='add'>+0x0040, 0x0df0, 0x01e4, 0x3fec,</div><div class='add'>+0x0020, 0x0de0, 0x0218, 0x3fe8,</div><div class='add'>+0x0004, 0x0dd0, 0x024c, 0x3fe0,</div><div class='add'>+0x3fe8, 0x0db8, 0x0284, 0x3fdc,</div><div class='add'>+0x3fcc, 0x0da0, 0x02c0, 0x3fd4,</div><div class='add'>+0x3fb4, 0x0d84, 0x02fc, 0x3fcc,</div><div class='add'>+0x3fa0, 0x0d68, 0x0334, 0x3fc4,</div><div class='add'>+0x3f88, 0x0d48, 0x0370, 0x3fc0,</div><div class='add'>+0x3f78, 0x0d24, 0x03ac, 0x3fb8,</div><div class='add'>+0x3f64, 0x0cfc, 0x03f0, 0x3fb0,</div><div class='add'>+0x3f54, 0x0cd4, 0x0434, 0x3fa4,</div><div class='add'>+0x3f48, 0x0ca8, 0x0474, 0x3f9c,</div><div class='add'>+0x3f3c, 0x0c78, 0x04b8, 0x3f94,</div><div class='add'>+0x3f30, 0x0c48, 0x04fc, 0x3f8c,</div><div class='add'>+0x3f28, 0x0c14, 0x0540, 0x3f84,</div><div class='add'>+0x3f20, 0x0be0, 0x0588, 0x3f78,</div><div class='add'>+0x3f18, 0x0ba8, 0x05d0, 0x3f70,</div><div class='add'>+0x3f14, 0x0b70, 0x0614, 0x3f68,</div><div class='add'>+0x3f10, 0x0b34, 0x065c, 0x3f60,</div><div class='add'>+0x3f0c, 0x0af8, 0x06a8, 0x3f54,</div><div class='add'>+0x3f0c, 0x0abc, 0x06ec, 0x3f4c,</div><div class='add'>+0x3f0c, 0x0a7c, 0x0734, 0x3f44,</div><div class='add'>+0x3f0c, 0x0a38, 0x0780, 0x3f3c,</div><div class='add'>+0x3f0c, 0x09f8, 0x07c8, 0x3f34,</div><div class='add'>+0x3f10, 0x09b4, 0x080c, 0x3f30,</div><div class='add'>+0x3f14, 0x0970, 0x0854, 0x3f28,</div><div class='add'>+0x3f18, 0x092c, 0x089c, 0x3f20,</div><div class='add'>+0x3f1c, 0x08e4, 0x08e4, 0x3f1c,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_4tap_64p_ratio_1_00_s1_12[132] = {</div><div class='add'>+0x0000, 0x1000, 0x0000, 0x0000,</div><div class='add'>+0x3fd8, 0x0ffc, 0x002c, 0x0000,</div><div class='add'>+0x3fb4, 0x0ff8, 0x0054, 0x0000,</div><div class='add'>+0x3f90, 0x0fec, 0x0088, 0x3ffc,</div><div class='add'>+0x3f70, 0x0fdc, 0x00b8, 0x3ffc,</div><div class='add'>+0x3f54, 0x0fc8, 0x00ec, 0x3ff8,</div><div class='add'>+0x3f38, 0x0fb0, 0x0120, 0x3ff8,</div><div class='add'>+0x3f20, 0x0f94, 0x0158, 0x3ff4,</div><div class='add'>+0x3f0c, 0x0f70, 0x0194, 0x3ff0,</div><div class='add'>+0x3ef8, 0x0f4c, 0x01d4, 0x3fe8,</div><div class='add'>+0x3ee4, 0x0f24, 0x0214, 0x3fe4,</div><div class='add'>+0x3ed8, 0x0ef8, 0x0250, 0x3fe0,</div><div class='add'>+0x3ec8, 0x0ec8, 0x0298, 0x3fd8,</div><div class='add'>+0x3ec0, 0x0e94, 0x02dc, 0x3fd0,</div><div class='add'>+0x3eb4, 0x0e5c, 0x0328, 0x3fc8,</div><div class='add'>+0x3eac, 0x0e24, 0x0370, 0x3fc0,</div><div class='add'>+0x3ea8, 0x0de4, 0x03bc, 0x3fb8,</div><div class='add'>+0x3ea4, 0x0da4, 0x0408, 0x3fb0,</div><div class='add'>+0x3ea4, 0x0d64, 0x0454, 0x3fa4,</div><div class='add'>+0x3ea4, 0x0d20, 0x04a4, 0x3f98,</div><div class='add'>+0x3ea4, 0x0cd8, 0x04f4, 0x3f90,</div><div class='add'>+0x3ea4, 0x0c8c, 0x054c, 0x3f84,</div><div class='add'>+0x3ea8, 0x0c40, 0x05a0, 0x3f78,</div><div class='add'>+0x3eb0, 0x0bf4, 0x05f0, 0x3f6c,</div><div class='add'>+0x3eb4, 0x0ba4, 0x0648, 0x3f60,</div><div class='add'>+0x3ebc, 0x0b54, 0x069c, 0x3f54,</div><div class='add'>+0x3ec4, 0x0b00, 0x06f4, 0x3f48,</div><div class='add'>+0x3ecc, 0x0ab0, 0x0748, 0x3f3c,</div><div class='add'>+0x3ed4, 0x0a58, 0x07a4, 0x3f30,</div><div class='add'>+0x3ee0, 0x0a04, 0x07f8, 0x3f24,</div><div class='add'>+0x3ee8, 0x09b0, 0x0850, 0x3f18,</div><div class='add'>+0x3ef4, 0x0958, 0x08a8, 0x3f0c,</div><div class='add'>+0x3f00, 0x0900, 0x0900, 0x3f00,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_30_s1_12[198] = {</div><div class='add'>+0x012c, 0x0400, 0x05a4, 0x0404, 0x012c, 0x0000,</div><div class='add'>+0x0124, 0x03f4, 0x05a4, 0x040c, 0x0138, 0x0000,</div><div class='add'>+0x011c, 0x03e8, 0x05a4, 0x0418, 0x0140, 0x0000,</div><div class='add'>+0x0114, 0x03dc, 0x05a0, 0x0424, 0x0148, 0x0004,</div><div class='add'>+0x010c, 0x03d4, 0x05a0, 0x042c, 0x0150, 0x0004,</div><div class='add'>+0x0100, 0x03c8, 0x05a0, 0x0438, 0x015c, 0x0004,</div><div class='add'>+0x00f8, 0x03bc, 0x05a0, 0x0440, 0x0164, 0x0008,</div><div class='add'>+0x00f0, 0x03b0, 0x059c, 0x044c, 0x0170, 0x0008,</div><div class='add'>+0x00e8, 0x03a4, 0x059c, 0x0458, 0x0178, 0x0008,</div><div class='add'>+0x00e0, 0x0398, 0x0598, 0x0460, 0x0184, 0x000c,</div><div class='add'>+0x00d8, 0x038c, 0x0594, 0x0470, 0x018c, 0x000c,</div><div class='add'>+0x00d0, 0x0380, 0x0594, 0x0474, 0x0198, 0x0010,</div><div class='add'>+0x00cc, 0x0374, 0x0590, 0x0480, 0x01a0, 0x0010,</div><div class='add'>+0x00c4, 0x0368, 0x058c, 0x0488, 0x01ac, 0x0014,</div><div class='add'>+0x00bc, 0x035c, 0x058c, 0x0494, 0x01b4, 0x0014,</div><div class='add'>+0x00b4, 0x034c, 0x0588, 0x04a0, 0x01c0, 0x0018,</div><div class='add'>+0x00ac, 0x0340, 0x0584, 0x04a8, 0x01cc, 0x001c,</div><div class='add'>+0x00a8, 0x0334, 0x0580, 0x04b4, 0x01d4, 0x001c,</div><div class='add'>+0x00a0, 0x0328, 0x057c, 0x04bc, 0x01e0, 0x0020,</div><div class='add'>+0x0098, 0x031c, 0x0578, 0x04c4, 0x01ec, 0x0024,</div><div class='add'>+0x0094, 0x0310, 0x0574, 0x04cc, 0x01f8, 0x0024,</div><div class='add'>+0x008c, 0x0304, 0x0570, 0x04d8, 0x0200, 0x0028,</div><div class='add'>+0x0088, 0x02f8, 0x0568, 0x04e0, 0x020c, 0x002c,</div><div class='add'>+0x0080, 0x02ec, 0x0564, 0x04e8, 0x0218, 0x0030,</div><div class='add'>+0x007c, 0x02e0, 0x0560, 0x04ec, 0x0224, 0x0034,</div><div class='add'>+0x0078, 0x02d4, 0x0558, 0x04f8, 0x0230, 0x0034,</div><div class='add'>+0x0070, 0x02c8, 0x0554, 0x0500, 0x023c, 0x0038,</div><div class='add'>+0x006c, 0x02bc, 0x054c, 0x050c, 0x0244, 0x003c,</div><div class='add'>+0x0064, 0x02b0, 0x0548, 0x0514, 0x0250, 0x0040,</div><div class='add'>+0x0060, 0x02a4, 0x0540, 0x051c, 0x025c, 0x0044,</div><div class='add'>+0x005c, 0x0298, 0x053c, 0x0520, 0x0268, 0x0048,</div><div class='add'>+0x0058, 0x028c, 0x0534, 0x0524, 0x0274, 0x0050,</div><div class='add'>+0x0054, 0x0280, 0x052c, 0x052c, 0x0280, 0x0054,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_40_s1_12[198] = {</div><div class='add'>+0x00a0, 0x0418, 0x068c, 0x041c, 0x00a0, 0x0000,</div><div class='add'>+0x0098, 0x0408, 0x068c, 0x0428, 0x00ac, 0x0000,</div><div class='add'>+0x0090, 0x03f8, 0x068c, 0x043c, 0x00b4, 0x3ffc,</div><div class='add'>+0x0088, 0x03e8, 0x068c, 0x044c, 0x00bc, 0x3ffc,</div><div class='add'>+0x0084, 0x03d8, 0x068c, 0x0458, 0x00c4, 0x3ffc,</div><div class='add'>+0x007c, 0x03c8, 0x0688, 0x046c, 0x00d0, 0x3ff8,</div><div class='add'>+0x0074, 0x03b8, 0x0688, 0x047c, 0x00d8, 0x3ff8,</div><div class='add'>+0x006c, 0x03a8, 0x0684, 0x048c, 0x00e4, 0x3ff8,</div><div class='add'>+0x0064, 0x0398, 0x0684, 0x049c, 0x00ec, 0x3ff8,</div><div class='add'>+0x0060, 0x0388, 0x0680, 0x04a8, 0x00f8, 0x3ff8,</div><div class='add'>+0x0058, 0x0378, 0x0680, 0x04b8, 0x0104, 0x3ff4,</div><div class='add'>+0x0054, 0x0368, 0x067c, 0x04c8, 0x010c, 0x3ff4,</div><div class='add'>+0x004c, 0x0358, 0x0678, 0x04d8, 0x0118, 0x3ff4,</div><div class='add'>+0x0048, 0x0348, 0x0674, 0x04e4, 0x0124, 0x3ff4,</div><div class='add'>+0x0040, 0x0338, 0x0670, 0x04f4, 0x0130, 0x3ff4,</div><div class='add'>+0x003c, 0x0328, 0x0668, 0x0504, 0x013c, 0x3ff4,</div><div class='add'>+0x0038, 0x0318, 0x0664, 0x0510, 0x0148, 0x3ff4,</div><div class='add'>+0x0034, 0x0308, 0x065c, 0x0520, 0x0154, 0x3ff4,</div><div class='add'>+0x002c, 0x02f8, 0x0658, 0x0530, 0x0160, 0x3ff4,</div><div class='add'>+0x0028, 0x02e8, 0x0654, 0x053c, 0x016c, 0x3ff4,</div><div class='add'>+0x0024, 0x02d8, 0x064c, 0x054c, 0x0178, 0x3ff4,</div><div class='add'>+0x0020, 0x02c8, 0x0644, 0x055c, 0x0184, 0x3ff4,</div><div class='add'>+0x001c, 0x02b8, 0x0640, 0x0568, 0x0190, 0x3ff4,</div><div class='add'>+0x0018, 0x02a8, 0x0638, 0x0574, 0x01a0, 0x3ff4,</div><div class='add'>+0x0014, 0x0298, 0x0630, 0x0584, 0x01ac, 0x3ff4,</div><div class='add'>+0x0014, 0x0288, 0x0624, 0x0590, 0x01bc, 0x3ff4,</div><div class='add'>+0x0010, 0x0278, 0x061c, 0x059c, 0x01c8, 0x3ff8,</div><div class='add'>+0x000c, 0x0268, 0x0614, 0x05ac, 0x01d4, 0x3ff8,</div><div class='add'>+0x0008, 0x0258, 0x060c, 0x05b8, 0x01e4, 0x3ff8,</div><div class='add'>+0x0008, 0x024c, 0x0600, 0x05bc, 0x01f4, 0x3ffc,</div><div class='add'>+0x0004, 0x023c, 0x05f8, 0x05cc, 0x0200, 0x3ffc,</div><div class='add'>+0x0004, 0x022c, 0x05ec, 0x05d4, 0x0210, 0x0000,</div><div class='add'>+0x0000, 0x021c, 0x05e4, 0x05e4, 0x021c, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_50_s1_12[198] = {</div><div class='add'>+0x0000, 0x041c, 0x07cc, 0x0418, 0x0000, 0x0000,</div><div class='add'>+0x3ff8, 0x0404, 0x07cc, 0x0434, 0x0008, 0x3ffc,</div><div class='add'>+0x3ff4, 0x03ec, 0x07cc, 0x044c, 0x000c, 0x3ffc,</div><div class='add'>+0x3ff0, 0x03d8, 0x07cc, 0x0460, 0x0014, 0x3ff8,</div><div class='add'>+0x3fe8, 0x03c0, 0x07cc, 0x0478, 0x001c, 0x3ff8,</div><div class='add'>+0x3fe4, 0x03ac, 0x07c8, 0x0490, 0x0024, 0x3ff4,</div><div class='add'>+0x3fe0, 0x0394, 0x07c8, 0x04a4, 0x002c, 0x3ff4,</div><div class='add'>+0x3fdc, 0x0380, 0x07c4, 0x04bc, 0x0034, 0x3ff0,</div><div class='add'>+0x3fd8, 0x0368, 0x07c0, 0x04d4, 0x0040, 0x3fec,</div><div class='add'>+0x3fd4, 0x0350, 0x07bc, 0x04ec, 0x0048, 0x3fec,</div><div class='add'>+0x3fd0, 0x033c, 0x07b8, 0x0504, 0x0050, 0x3fe8,</div><div class='add'>+0x3fcc, 0x0324, 0x07b4, 0x051c, 0x005c, 0x3fe4,</div><div class='add'>+0x3fc8, 0x0310, 0x07ac, 0x0530, 0x0068, 0x3fe4,</div><div class='add'>+0x3fc4, 0x02fc, 0x07a8, 0x0548, 0x0070, 0x3fe0,</div><div class='add'>+0x3fc4, 0x02e4, 0x07a0, 0x055c, 0x007c, 0x3fe0,</div><div class='add'>+0x3fc0, 0x02d0, 0x0798, 0x0574, 0x0088, 0x3fdc,</div><div class='add'>+0x3fc0, 0x02b8, 0x0790, 0x058c, 0x0094, 0x3fd8,</div><div class='add'>+0x3fbc, 0x02a4, 0x0788, 0x05a0, 0x00a0, 0x3fd8,</div><div class='add'>+0x3fbc, 0x0290, 0x077c, 0x05b8, 0x00ac, 0x3fd4,</div><div class='add'>+0x3fbc, 0x027c, 0x0774, 0x05c8, 0x00b8, 0x3fd4,</div><div class='add'>+0x3fb8, 0x0268, 0x0768, 0x05e0, 0x00c8, 0x3fd0,</div><div class='add'>+0x3fb8, 0x0250, 0x0760, 0x05f8, 0x00d4, 0x3fcc,</div><div class='add'>+0x3fb8, 0x023c, 0x0754, 0x0608, 0x00e4, 0x3fcc,</div><div class='add'>+0x3fb8, 0x0228, 0x0748, 0x0620, 0x00f0, 0x3fc8,</div><div class='add'>+0x3fb8, 0x0214, 0x073c, 0x0630, 0x0100, 0x3fc8,</div><div class='add'>+0x3fb8, 0x0204, 0x072c, 0x0644, 0x0110, 0x3fc4,</div><div class='add'>+0x3fb8, 0x01f0, 0x0720, 0x0658, 0x011c, 0x3fc4,</div><div class='add'>+0x3fb8, 0x01dc, 0x0710, 0x0670, 0x012c, 0x3fc0,</div><div class='add'>+0x3fb8, 0x01c8, 0x0704, 0x0680, 0x013c, 0x3fc0,</div><div class='add'>+0x3fb8, 0x01b8, 0x06f4, 0x0690, 0x014c, 0x3fc0,</div><div class='add'>+0x3fb8, 0x01a4, 0x06e4, 0x06a4, 0x0160, 0x3fbc,</div><div class='add'>+0x3fb8, 0x0194, 0x06d4, 0x06b4, 0x0170, 0x3fbc,</div><div class='add'>+0x3fbc, 0x0180, 0x06c4, 0x06c4, 0x0180, 0x3fbc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_60_s1_12[198] = {</div><div class='add'>+0x3f64, 0x03ec, 0x0960, 0x03ec, 0x3f64, 0x0000,</div><div class='add'>+0x3f64, 0x03cc, 0x0960, 0x0408, 0x3f68, 0x0000,</div><div class='add'>+0x3f60, 0x03ac, 0x0960, 0x042c, 0x3f6c, 0x3ffc,</div><div class='add'>+0x3f60, 0x038c, 0x0960, 0x0448, 0x3f70, 0x3ffc,</div><div class='add'>+0x3f60, 0x0370, 0x095c, 0x046c, 0x3f70, 0x3ff8,</div><div class='add'>+0x3f5c, 0x0350, 0x0958, 0x048c, 0x3f78, 0x3ff8,</div><div class='add'>+0x3f5c, 0x0334, 0x0954, 0x04ac, 0x3f7c, 0x3ff4,</div><div class='add'>+0x3f5c, 0x0314, 0x0950, 0x04cc, 0x3f80, 0x3ff4,</div><div class='add'>+0x3f5c, 0x02f8, 0x0948, 0x04f0, 0x3f84, 0x3ff0,</div><div class='add'>+0x3f5c, 0x02d8, 0x0944, 0x050c, 0x3f8c, 0x3ff0,</div><div class='add'>+0x3f60, 0x02bc, 0x093c, 0x052c, 0x3f90, 0x3fec,</div><div class='add'>+0x3f60, 0x02a0, 0x0930, 0x0550, 0x3f98, 0x3fe8,</div><div class='add'>+0x3f60, 0x0284, 0x0928, 0x056c, 0x3fa0, 0x3fe8,</div><div class='add'>+0x3f64, 0x0268, 0x091c, 0x058c, 0x3fa8, 0x3fe4,</div><div class='add'>+0x3f64, 0x024c, 0x0910, 0x05b0, 0x3fb0, 0x3fe0,</div><div class='add'>+0x3f64, 0x0230, 0x0904, 0x05d0, 0x3fbc, 0x3fdc,</div><div class='add'>+0x3f68, 0x0214, 0x08f8, 0x05ec, 0x3fc4, 0x3fdc,</div><div class='add'>+0x3f6c, 0x01fc, 0x08e8, 0x060c, 0x3fcc, 0x3fd8,</div><div class='add'>+0x3f6c, 0x01e0, 0x08dc, 0x062c, 0x3fd8, 0x3fd4,</div><div class='add'>+0x3f70, 0x01c8, 0x08cc, 0x0648, 0x3fe4, 0x3fd0,</div><div class='add'>+0x3f74, 0x01b0, 0x08bc, 0x0664, 0x3ff0, 0x3fcc,</div><div class='add'>+0x3f74, 0x0194, 0x08a8, 0x068c, 0x3ffc, 0x3fc8,</div><div class='add'>+0x3f78, 0x017c, 0x0898, 0x06a8, 0x0008, 0x3fc4,</div><div class='add'>+0x3f7c, 0x0168, 0x0884, 0x06c0, 0x0018, 0x3fc0,</div><div class='add'>+0x3f80, 0x0150, 0x0870, 0x06dc, 0x0024, 0x3fc0,</div><div class='add'>+0x3f84, 0x0138, 0x085c, 0x06f8, 0x0034, 0x3fbc,</div><div class='add'>+0x3f88, 0x0120, 0x0848, 0x0718, 0x0040, 0x3fb8,</div><div class='add'>+0x3f8c, 0x010c, 0x0830, 0x0734, 0x0050, 0x3fb4,</div><div class='add'>+0x3f90, 0x00f8, 0x081c, 0x074c, 0x0060, 0x3fb0,</div><div class='add'>+0x3f94, 0x00e4, 0x0800, 0x0768, 0x0074, 0x3fac,</div><div class='add'>+0x3f98, 0x00d0, 0x07e8, 0x0784, 0x0084, 0x3fa8,</div><div class='add'>+0x3f9c, 0x00bc, 0x07d4, 0x079c, 0x0094, 0x3fa4,</div><div class='add'>+0x3fa0, 0x00a8, 0x07b8, 0x07b8, 0x00a8, 0x3fa0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_70_s1_12[198] = {</div><div class='add'>+0x3f00, 0x0368, 0x0b30, 0x0368, 0x3f00, 0x0000,</div><div class='add'>+0x3f04, 0x0340, 0x0b30, 0x0390, 0x3efc, 0x0000,</div><div class='add'>+0x3f08, 0x0318, 0x0b2c, 0x03bc, 0x3ef8, 0x0000,</div><div class='add'>+0x3f0c, 0x02f0, 0x0b28, 0x03e4, 0x3ef8, 0x0000,</div><div class='add'>+0x3f10, 0x02c8, 0x0b24, 0x0410, 0x3ef4, 0x0000,</div><div class='add'>+0x3f14, 0x02a0, 0x0b1c, 0x043c, 0x3ef4, 0x0000,</div><div class='add'>+0x3f1c, 0x027c, 0x0b14, 0x0464, 0x3ef0, 0x0000,</div><div class='add'>+0x3f20, 0x0254, 0x0b0c, 0x0490, 0x3ef0, 0x0000,</div><div class='add'>+0x3f24, 0x0230, 0x0b00, 0x04bc, 0x3ef0, 0x0000,</div><div class='add'>+0x3f2c, 0x020c, 0x0af4, 0x04e4, 0x3ef0, 0x0000,</div><div class='add'>+0x3f30, 0x01e8, 0x0ae8, 0x0510, 0x3ef0, 0x0000,</div><div class='add'>+0x3f38, 0x01c8, 0x0ad8, 0x0534, 0x3ef4, 0x0000,</div><div class='add'>+0x3f40, 0x01a4, 0x0ac8, 0x0564, 0x3ef4, 0x3ffc,</div><div class='add'>+0x3f44, 0x0184, 0x0ab4, 0x0590, 0x3ef8, 0x3ffc,</div><div class='add'>+0x3f4c, 0x0164, 0x0aa4, 0x05b8, 0x3efc, 0x3ff8,</div><div class='add'>+0x3f50, 0x0144, 0x0a90, 0x05e8, 0x3efc, 0x3ff8,</div><div class='add'>+0x3f58, 0x0124, 0x0a78, 0x0610, 0x3f04, 0x3ff8,</div><div class='add'>+0x3f60, 0x0108, 0x0a64, 0x0638, 0x3f08, 0x3ff4,</div><div class='add'>+0x3f64, 0x00e8, 0x0a4c, 0x066c, 0x3f0c, 0x3ff0,</div><div class='add'>+0x3f6c, 0x00cc, 0x0a34, 0x0690, 0x3f14, 0x3ff0,</div><div class='add'>+0x3f70, 0x00b4, 0x0a18, 0x06bc, 0x3f1c, 0x3fec,</div><div class='add'>+0x3f78, 0x0098, 0x0a00, 0x06e8, 0x3f20, 0x3fe8,</div><div class='add'>+0x3f80, 0x007c, 0x09e4, 0x0710, 0x3f2c, 0x3fe4,</div><div class='add'>+0x3f84, 0x0064, 0x09c8, 0x0738, 0x3f34, 0x3fe4,</div><div class='add'>+0x3f8c, 0x004c, 0x09a8, 0x0764, 0x3f3c, 0x3fe0,</div><div class='add'>+0x3f90, 0x0034, 0x098c, 0x078c, 0x3f48, 0x3fdc,</div><div class='add'>+0x3f98, 0x0020, 0x096c, 0x07b0, 0x3f54, 0x3fd8,</div><div class='add'>+0x3f9c, 0x0008, 0x094c, 0x07dc, 0x3f60, 0x3fd4,</div><div class='add'>+0x3fa4, 0x3ff4, 0x0928, 0x0808, 0x3f6c, 0x3fcc,</div><div class='add'>+0x3fa8, 0x3fe0, 0x0908, 0x082c, 0x3f7c, 0x3fc8,</div><div class='add'>+0x3fb0, 0x3fcc, 0x08e4, 0x0854, 0x3f88, 0x3fc4,</div><div class='add'>+0x3fb4, 0x3fbc, 0x08c0, 0x0878, 0x3f98, 0x3fc0,</div><div class='add'>+0x3fbc, 0x3fac, 0x0898, 0x0898, 0x3fac, 0x3fbc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_80_s1_12[198] = {</div><div class='add'>+0x3efc, 0x0284, 0x0d00, 0x0284, 0x3efc, 0x0000,</div><div class='add'>+0x3f04, 0x0254, 0x0d00, 0x02b4, 0x3ef0, 0x0004,</div><div class='add'>+0x3f10, 0x0224, 0x0cf8, 0x02e8, 0x3ee8, 0x0004,</div><div class='add'>+0x3f18, 0x01f4, 0x0cf4, 0x0318, 0x3ee0, 0x0008,</div><div class='add'>+0x3f24, 0x01c8, 0x0ce8, 0x034c, 0x3ed8, 0x0008,</div><div class='add'>+0x3f30, 0x019c, 0x0ce0, 0x037c, 0x3ecc, 0x000c,</div><div class='add'>+0x3f38, 0x0170, 0x0cd0, 0x03b8, 0x3ec4, 0x000c,</div><div class='add'>+0x3f44, 0x0144, 0x0cc4, 0x03e8, 0x3ebc, 0x0010,</div><div class='add'>+0x3f4c, 0x011c, 0x0cb4, 0x0420, 0x3eb4, 0x0010,</div><div class='add'>+0x3f58, 0x00f4, 0x0ca0, 0x0458, 0x3eac, 0x0010,</div><div class='add'>+0x3f60, 0x00cc, 0x0c8c, 0x048c, 0x3ea8, 0x0014,</div><div class='add'>+0x3f6c, 0x00a8, 0x0c74, 0x04c4, 0x3ea0, 0x0014,</div><div class='add'>+0x3f74, 0x0084, 0x0c5c, 0x04fc, 0x3e9c, 0x0014,</div><div class='add'>+0x3f7c, 0x0060, 0x0c44, 0x0534, 0x3e94, 0x0018,</div><div class='add'>+0x3f88, 0x0040, 0x0c28, 0x0568, 0x3e90, 0x0018,</div><div class='add'>+0x3f90, 0x0020, 0x0c08, 0x05a4, 0x3e8c, 0x0018,</div><div class='add'>+0x3f98, 0x0000, 0x0bec, 0x05dc, 0x3e88, 0x0018,</div><div class='add'>+0x3fa0, 0x3fe4, 0x0bcc, 0x0614, 0x3e84, 0x0018,</div><div class='add'>+0x3fac, 0x3fc4, 0x0ba8, 0x064c, 0x3e84, 0x0018,</div><div class='add'>+0x3fb4, 0x3fac, 0x0b84, 0x0684, 0x3e80, 0x0018,</div><div class='add'>+0x3fb8, 0x3f90, 0x0b60, 0x06c0, 0x3e80, 0x0018,</div><div class='add'>+0x3fc0, 0x3f78, 0x0b38, 0x06f8, 0x3e80, 0x0018,</div><div class='add'>+0x3fc8, 0x3f60, 0x0b14, 0x072c, 0x3e80, 0x0018,</div><div class='add'>+0x3fd0, 0x3f4c, 0x0ae8, 0x0760, 0x3e84, 0x0018,</div><div class='add'>+0x3fd8, 0x3f34, 0x0ac0, 0x079c, 0x3e84, 0x0014,</div><div class='add'>+0x3fdc, 0x3f20, 0x0a94, 0x07d4, 0x3e88, 0x0014,</div><div class='add'>+0x3fe4, 0x3f10, 0x0a68, 0x0808, 0x3e8c, 0x0010,</div><div class='add'>+0x3fe8, 0x3f00, 0x0a38, 0x0840, 0x3e90, 0x0010,</div><div class='add'>+0x3fec, 0x3ef0, 0x0a0c, 0x0874, 0x3e98, 0x000c,</div><div class='add'>+0x3ff4, 0x3ee0, 0x09d8, 0x08a8, 0x3ea0, 0x000c,</div><div class='add'>+0x3ff8, 0x3ed0, 0x09ac, 0x08dc, 0x3ea8, 0x0008,</div><div class='add'>+0x3ffc, 0x3ec4, 0x0978, 0x0914, 0x3eb0, 0x0004,</div><div class='add'>+0x0000, 0x3eb8, 0x0948, 0x0948, 0x3eb8, 0x0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_0_90_s1_12[198] = {</div><div class='add'>+0x3f60, 0x0154, 0x0e9c, 0x0150, 0x3f60, 0x0000,</div><div class='add'>+0x3f6c, 0x011c, 0x0e9c, 0x018c, 0x3f50, 0x0000,</div><div class='add'>+0x3f7c, 0x00ec, 0x0e94, 0x01bc, 0x3f44, 0x0004,</div><div class='add'>+0x3f88, 0x00b8, 0x0e8c, 0x01f8, 0x3f34, 0x0008,</div><div class='add'>+0x3f94, 0x0088, 0x0e80, 0x0234, 0x3f28, 0x0008,</div><div class='add'>+0x3fa0, 0x005c, 0x0e74, 0x026c, 0x3f18, 0x000c,</div><div class='add'>+0x3fac, 0x0030, 0x0e60, 0x02b0, 0x3f08, 0x000c,</div><div class='add'>+0x3fb8, 0x0004, 0x0e50, 0x02e8, 0x3efc, 0x0010,</div><div class='add'>+0x3fc4, 0x3fdc, 0x0e38, 0x0328, 0x3eec, 0x0014,</div><div class='add'>+0x3fd0, 0x3fb4, 0x0e20, 0x0368, 0x3ee0, 0x0014,</div><div class='add'>+0x3fd8, 0x3f90, 0x0e04, 0x03ac, 0x3ed0, 0x0018,</div><div class='add'>+0x3fe4, 0x3f6c, 0x0de8, 0x03e8, 0x3ec4, 0x001c,</div><div class='add'>+0x3fec, 0x3f4c, 0x0dc8, 0x042c, 0x3eb4, 0x0020,</div><div class='add'>+0x3ff4, 0x3f2c, 0x0da4, 0x0474, 0x3ea8, 0x0020,</div><div class='add'>+0x0000, 0x3f0c, 0x0d80, 0x04b8, 0x3e98, 0x0024,</div><div class='add'>+0x0008, 0x3ef0, 0x0d58, 0x04fc, 0x3e8c, 0x0028,</div><div class='add'>+0x000c, 0x3ed8, 0x0d30, 0x0540, 0x3e80, 0x002c,</div><div class='add'>+0x0014, 0x3ec0, 0x0d04, 0x0588, 0x3e74, 0x002c,</div><div class='add'>+0x001c, 0x3ea8, 0x0cd8, 0x05cc, 0x3e68, 0x0030,</div><div class='add'>+0x0020, 0x3e94, 0x0ca8, 0x0614, 0x3e5c, 0x0034,</div><div class='add'>+0x0028, 0x3e80, 0x0c78, 0x065c, 0x3e50, 0x0034,</div><div class='add'>+0x002c, 0x3e6c, 0x0c44, 0x06a4, 0x3e48, 0x0038,</div><div class='add'>+0x0030, 0x3e5c, 0x0c0c, 0x06f0, 0x3e3c, 0x003c,</div><div class='add'>+0x0034, 0x3e50, 0x0bd8, 0x0734, 0x3e34, 0x003c,</div><div class='add'>+0x0038, 0x3e44, 0x0ba0, 0x0778, 0x3e2c, 0x0040,</div><div class='add'>+0x003c, 0x3e38, 0x0b64, 0x07c4, 0x3e24, 0x0040,</div><div class='add'>+0x0040, 0x3e2c, 0x0b28, 0x0808, 0x3e20, 0x0044,</div><div class='add'>+0x0040, 0x3e24, 0x0aec, 0x0850, 0x3e1c, 0x0044,</div><div class='add'>+0x0044, 0x3e1c, 0x0aac, 0x0898, 0x3e18, 0x0044,</div><div class='add'>+0x0044, 0x3e18, 0x0a70, 0x08d8, 0x3e14, 0x0048,</div><div class='add'>+0x0044, 0x3e14, 0x0a2c, 0x0924, 0x3e10, 0x0048,</div><div class='add'>+0x0048, 0x3e10, 0x09ec, 0x0964, 0x3e10, 0x0048,</div><div class='add'>+0x0048, 0x3e10, 0x09a8, 0x09a8, 0x3e10, 0x0048,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t easf_filter_6tap_64p_ratio_1_00_s1_12[198] = {</div><div class='add'>+0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000,</div><div class='add'>+0x000c, 0x3fcc, 0x1000, 0x0034, 0x3ff4, 0x0000,</div><div class='add'>+0x0018, 0x3f9c, 0x0ff8, 0x0070, 0x3fe4, 0x0000,</div><div class='add'>+0x0024, 0x3f6c, 0x0ff0, 0x00ac, 0x3fd4, 0x0000,</div><div class='add'>+0x0030, 0x3f40, 0x0fe4, 0x00e8, 0x3fc4, 0x0000,</div><div class='add'>+0x0038, 0x3f14, 0x0fd4, 0x0128, 0x3fb4, 0x0004,</div><div class='add'>+0x0044, 0x3eec, 0x0fc0, 0x0168, 0x3fa4, 0x0004,</div><div class='add'>+0x004c, 0x3ec8, 0x0fac, 0x01a8, 0x3f94, 0x0004,</div><div class='add'>+0x0054, 0x3ea4, 0x0f90, 0x01ec, 0x3f84, 0x0008,</div><div class='add'>+0x005c, 0x3e84, 0x0f74, 0x0234, 0x3f70, 0x0008,</div><div class='add'>+0x0060, 0x3e64, 0x0f50, 0x0280, 0x3f60, 0x000c,</div><div class='add'>+0x0068, 0x3e48, 0x0f2c, 0x02c8, 0x3f4c, 0x0010,</div><div class='add'>+0x006c, 0x3e30, 0x0f04, 0x0318, 0x3f38, 0x0010,</div><div class='add'>+0x0070, 0x3e18, 0x0edc, 0x0364, 0x3f24, 0x0014,</div><div class='add'>+0x0074, 0x3e00, 0x0eac, 0x03b8, 0x3f10, 0x0018,</div><div class='add'>+0x0078, 0x3df0, 0x0e7c, 0x0404, 0x3efc, 0x001c,</div><div class='add'>+0x007c, 0x3de0, 0x0e48, 0x0454, 0x3ee8, 0x0020,</div><div class='add'>+0x007c, 0x3dd0, 0x0e14, 0x04ac, 0x3ed4, 0x0020,</div><div class='add'>+0x0080, 0x3dc4, 0x0dd8, 0x0500, 0x3ec0, 0x0024,</div><div class='add'>+0x0080, 0x3db8, 0x0d9c, 0x0554, 0x3eac, 0x002c,</div><div class='add'>+0x0080, 0x3db0, 0x0d5c, 0x05ac, 0x3e98, 0x0030,</div><div class='add'>+0x0080, 0x3da8, 0x0d1c, 0x0600, 0x3e88, 0x0034,</div><div class='add'>+0x0080, 0x3da4, 0x0cd8, 0x0658, 0x3e74, 0x0038,</div><div class='add'>+0x0080, 0x3da4, 0x0c94, 0x06ac, 0x3e60, 0x003c,</div><div class='add'>+0x007c, 0x3da0, 0x0c4c, 0x070c, 0x3e4c, 0x0040,</div><div class='add'>+0x007c, 0x3da4, 0x0c00, 0x0760, 0x3e3c, 0x0044,</div><div class='add'>+0x0078, 0x3da4, 0x0bb4, 0x07bc, 0x3e2c, 0x0048,</div><div class='add'>+0x0074, 0x3da8, 0x0b64, 0x0814, 0x3e1c, 0x0050,</div><div class='add'>+0x0074, 0x3db0, 0x0b14, 0x0868, 0x3e0c, 0x0054,</div><div class='add'>+0x0070, 0x3db8, 0x0ac4, 0x08c0, 0x3dfc, 0x0058,</div><div class='add'>+0x006c, 0x3dc0, 0x0a70, 0x091c, 0x3dec, 0x005c,</div><div class='add'>+0x0068, 0x3dc8, 0x0a1c, 0x0974, 0x3de0, 0x0060,</div><div class='add'>+0x0064, 0x3dd4, 0x09c8, 0x09c8, 0x3dd4, 0x0064,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_v_bf3_mode_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x0000},</div><div class='add'>+	{9, 10, 0x0000},</div><div class='add'>+	{1, 1, 0x0000},</div><div class='add'>+	{-1, -1, 0x0002},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_h_bf3_mode_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x0000},</div><div class='add'>+	{9, 10, 0x0000},</div><div class='add'>+	{1, 1, 0x0000},</div><div class='add'>+	{-1, -1, 0x0002},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_reducer_gain6_6tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x4100},</div><div class='add'>+	{4, 10, 0x4100},</div><div class='add'>+	{5, 10, 0x4100},</div><div class='add'>+	{6, 10, 0x4100},</div><div class='add'>+	{7, 10, 0x4100},</div><div class='add'>+	{8, 10, 0x4100},</div><div class='add'>+	{9, 10, 0x4100},</div><div class='add'>+	{1, 1, 0x4100},</div><div class='add'>+	{-1, -1, 0x4100},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_reducer_gain4_6tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x4000},</div><div class='add'>+	{4, 10, 0x4000},</div><div class='add'>+	{5, 10, 0x4000},</div><div class='add'>+	{6, 10, 0x4000},</div><div class='add'>+	{7, 10, 0x4000},</div><div class='add'>+	{8, 10, 0x4000},</div><div class='add'>+	{9, 10, 0x4000},</div><div class='add'>+	{1, 1, 0x4000},</div><div class='add'>+	{-1, -1, 0x4000},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_gain_ring6_6tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x251F},</div><div class='add'>+	{5, 10, 0x291F},</div><div class='add'>+	{6, 10, 0xA51F},</div><div class='add'>+	{7, 10, 0xA51F},</div><div class='add'>+	{8, 10, 0xAA66},</div><div class='add'>+	{9, 10, 0xA51F},</div><div class='add'>+	{1, 1, 0xA640},</div><div class='add'>+	{-1, -1, 0xA640},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_gain_ring4_6tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x9600},</div><div class='add'>+	{5, 10, 0xA460},</div><div class='add'>+	{6, 10, 0xA8E0},</div><div class='add'>+	{7, 10, 0xAC00},</div><div class='add'>+	{8, 10, 0xAD20},</div><div class='add'>+	{9, 10, 0xAFC0},</div><div class='add'>+	{1, 1, 0xB058},</div><div class='add'>+	{-1, -1, 0xB058},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_reducer_gain6_4tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x4100},</div><div class='add'>+	{4, 10, 0x4100},</div><div class='add'>+	{5, 10, 0x4100},</div><div class='add'>+	{6, 10, 0x4100},</div><div class='add'>+	{7, 10, 0x4100},</div><div class='add'>+	{8, 10, 0x4100},</div><div class='add'>+	{9, 10, 0x4100},</div><div class='add'>+	{1, 1, 0x4100},</div><div class='add'>+	{-1, -1, 0x4100},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_reducer_gain4_4tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x4000},</div><div class='add'>+	{4, 10, 0x4000},</div><div class='add'>+	{5, 10, 0x4000},</div><div class='add'>+	{6, 10, 0x4000},</div><div class='add'>+	{7, 10, 0x4000},</div><div class='add'>+	{8, 10, 0x4000},</div><div class='add'>+	{9, 10, 0x4000},</div><div class='add'>+	{1, 1, 0x4000},</div><div class='add'>+	{-1, -1, 0x4000},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_gain_ring6_4tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x0000},</div><div class='add'>+	{9, 10, 0x0000},</div><div class='add'>+	{1, 1, 0x0000},</div><div class='add'>+	{-1, -1, 0x0000},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_gain_ring4_4tap_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x9900},</div><div class='add'>+	{7, 10, 0xA100},</div><div class='add'>+	{8, 10, 0xA8C0},</div><div class='add'>+	{9, 10, 0xAB20},</div><div class='add'>+	{1, 1, 0xAC00},</div><div class='add'>+	{-1, -1, 0xAC00},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_3tap_dntilt_uptilt_offset_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x4100},</div><div class='add'>+	{9, 10, 0x9F00},</div><div class='add'>+	{1, 1, 0xA4C0},</div><div class='add'>+	{-1, -1, 0xA8D8},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt_maxval_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x4000},</div><div class='add'>+	{9, 10, 0x24FE},</div><div class='add'>+	{1, 1, 0x2D64},</div><div class='add'>+	{-1, -1, 0x3ADB},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_3tap_dntilt_slope_lookup[] = {</div><div class='add'>+	{3, 10, 0x3800},</div><div class='add'>+	{4, 10, 0x3800},</div><div class='add'>+	{5, 10, 0x3800},</div><div class='add'>+	{6, 10, 0x3800},</div><div class='add'>+	{7, 10, 0x3800},</div><div class='add'>+	{8, 10, 0x3886},</div><div class='add'>+	{9, 10, 0x3940},</div><div class='add'>+	{1, 1, 0x3A4E},</div><div class='add'>+	{-1, -1, 0x3B66},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt1_slope_lookup[] = {</div><div class='add'>+	{3, 10, 0x3800},</div><div class='add'>+	{4, 10, 0x3800},</div><div class='add'>+	{5, 10, 0x3800},</div><div class='add'>+	{6, 10, 0x3800},</div><div class='add'>+	{7, 10, 0x3800},</div><div class='add'>+	{8, 10, 0x36F4},</div><div class='add'>+	{9, 10, 0x359C},</div><div class='add'>+	{1, 1, 0x3360},</div><div class='add'>+	{-1, -1, 0x2F20},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_slope_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x0000},</div><div class='add'>+	{9, 10, 0x359C},</div><div class='add'>+	{1, 1, 0x31F0},</div><div class='add'>+	{-1, -1, 0x1F00},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_offset_lookup[] = {</div><div class='add'>+	{3, 10, 0x0000},</div><div class='add'>+	{4, 10, 0x0000},</div><div class='add'>+	{5, 10, 0x0000},</div><div class='add'>+	{6, 10, 0x0000},</div><div class='add'>+	{7, 10, 0x0000},</div><div class='add'>+	{8, 10, 0x0000},</div><div class='add'>+	{9, 10, 0x9F00},</div><div class='add'>+	{1, 1, 0xA400},</div><div class='add'>+	{-1, -1, 0x9E00},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_from_fraction(3, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_30_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_40_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_50_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(6, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_60_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(7, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_70_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(8, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_80_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(9, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_90_s1_12;</div><div class='add'>+	else</div><div class='add'>+		return easf_filter_3tap_64p_ratio_1_00_s1_12;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_from_fraction(3, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_30_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_40_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_50_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(6, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_60_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(7, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_70_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(8, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_80_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(9, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_90_s1_12;</div><div class='add'>+	else</div><div class='add'>+		return easf_filter_4tap_64p_ratio_1_00_s1_12;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_easf_filter_6tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_from_fraction(3, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_30_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_40_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_50_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(6, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_60_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(7, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_70_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(8, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_80_s1_12;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(9, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_90_s1_12;</div><div class='add'>+	else</div><div class='add'>+		return easf_filter_6tap_64p_ratio_1_00_s1_12;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (taps == 6)</div><div class='add'>+		return spl_get_easf_filter_6tap_64p(ratio);</div><div class='add'>+	else if (taps == 4)</div><div class='add'>+		return spl_get_easf_filter_4tap_64p(ratio);</div><div class='add'>+	else if (taps == 3)</div><div class='add'>+		return spl_get_easf_filter_3tap_64p(ratio);</div><div class='add'>+	else {</div><div class='add'>+		/* should never happen, bug */</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_easf_filter_3tap_64p_s1_10(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_from_fraction(3, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_30;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_40;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_50;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(6, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_60;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(7, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_70;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(8, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_80;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(9, 10).value)</div><div class='add'>+		return easf_filter_3tap_64p_ratio_0_90;</div><div class='add'>+	else</div><div class='add'>+		return easf_filter_3tap_64p_ratio_1_00;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_easf_filter_4tap_64p_s1_10(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_from_fraction(3, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_30;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_40;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_50;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(6, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_60;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(7, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_70;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(8, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_80;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(9, 10).value)</div><div class='add'>+		return easf_filter_4tap_64p_ratio_0_90;</div><div class='add'>+	else</div><div class='add'>+		return easf_filter_4tap_64p_ratio_1_00;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_easf_filter_6tap_64p_s1_10(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_from_fraction(3, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_30;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_40;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_50;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(6, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_60;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(7, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_70;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(8, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_80;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(9, 10).value)</div><div class='add'>+		return easf_filter_6tap_64p_ratio_0_90;</div><div class='add'>+	else</div><div class='add'>+		return easf_filter_6tap_64p_ratio_1_00;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const uint16_t *spl_dscl_get_easf_filter_coeffs_64p_s1_10(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (taps == 6)</div><div class='add'>+		return spl_get_easf_filter_6tap_64p_s1_10(ratio);</div><div class='add'>+	else if (taps == 4)</div><div class='add'>+		return spl_get_easf_filter_4tap_64p_s1_10(ratio);</div><div class='add'>+	else if (taps == 3)</div><div class='add'>+		return spl_get_easf_filter_3tap_64p_s1_10(ratio);</div><div class='add'>+	else {</div><div class='add'>+		/* should never happen, bug */</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+		const struct spl_scaler_data *data, bool enable_easf_v,</div><div class='add'>+		bool enable_easf_h)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Old coefficients calculated scaling ratio = input / output</div><div class='add'>+	 * New coefficients are calculated based on = output / input</div><div class='add'>+	 */</div><div class='add'>+	if (enable_easf_h) {</div><div class='add'>+		dscl_prog_data-&gt;filter_h = spl_dscl_get_easf_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.h_taps, data-&gt;recip_ratios.horz);</div><div class='add'>+</div><div class='add'>+		dscl_prog_data-&gt;filter_h_c = spl_dscl_get_easf_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.h_taps_c, data-&gt;recip_ratios.horz_c);</div><div class='add'>+	} else {</div><div class='add'>+		dscl_prog_data-&gt;filter_h = spl_dscl_get_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.h_taps, data-&gt;ratios.horz);</div><div class='add'>+</div><div class='add'>+		dscl_prog_data-&gt;filter_h_c = spl_dscl_get_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.h_taps_c, data-&gt;ratios.horz_c);</div><div class='add'>+	}</div><div class='add'>+	if (enable_easf_v) {</div><div class='add'>+		dscl_prog_data-&gt;filter_v = spl_dscl_get_easf_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.v_taps, data-&gt;recip_ratios.vert);</div><div class='add'>+</div><div class='add'>+		dscl_prog_data-&gt;filter_v_c = spl_dscl_get_easf_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.v_taps_c, data-&gt;recip_ratios.vert_c);</div><div class='add'>+	} else {</div><div class='add'>+		dscl_prog_data-&gt;filter_v = spl_dscl_get_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.v_taps, data-&gt;ratios.vert);</div><div class='add'>+</div><div class='add'>+		dscl_prog_data-&gt;filter_v_c = spl_dscl_get_filter_coeffs_64p(</div><div class='add'>+			data-&gt;taps.v_taps_c, data-&gt;ratios.vert_c);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint32_t spl_easf_get_scale_ratio_to_reg_value(struct spl_fixed31_32 ratio,</div><div class='add'>+	struct scale_ratio_to_reg_value_lookup *lookup_table_base_ptr,</div><div class='add'>+	unsigned int num_entries)</div><div class='add'>+{</div><div class='add'>+	unsigned int count = 0;</div><div class='add'>+	uint32_t value = 0;</div><div class='add'>+	struct scale_ratio_to_reg_value_lookup *lookup_table_index_ptr;</div><div class='add'>+</div><div class='add'>+	lookup_table_index_ptr = (lookup_table_base_ptr + num_entries - 1);</div><div class='add'>+	value = lookup_table_index_ptr-&gt;reg_value;</div><div class='add'>+</div><div class='add'>+	while (count &lt; num_entries) {</div><div class='add'>+</div><div class='add'>+		lookup_table_index_ptr = (lookup_table_base_ptr + count);</div><div class='add'>+		if (lookup_table_index_ptr-&gt;numer &lt; 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (ratio.value &lt; spl_fixpt_from_fraction(</div><div class='add'>+			lookup_table_index_ptr-&gt;numer,</div><div class='add'>+			lookup_table_index_ptr-&gt;denom).value) {</div><div class='add'>+			value = lookup_table_index_ptr-&gt;reg_value;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		count++;</div><div class='add'>+	}</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries = sizeof(easf_v_bf3_mode_lookup) /</div><div class='add'>+		sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+	value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+		easf_v_bf3_mode_lookup, num_entries);</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries = sizeof(easf_h_bf3_mode_lookup) /</div><div class='add'>+		sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+	value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+		easf_h_bf3_mode_lookup, num_entries);</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 4) {</div><div class='add'>+		num_entries = sizeof(easf_reducer_gain6_4tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_reducer_gain6_4tap_lookup, num_entries);</div><div class='add'>+	} else if (taps == 6) {</div><div class='add'>+		num_entries = sizeof(easf_reducer_gain6_6tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_reducer_gain6_6tap_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 4) {</div><div class='add'>+		num_entries = sizeof(easf_reducer_gain4_4tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_reducer_gain4_4tap_lookup, num_entries);</div><div class='add'>+	} else if (taps == 6) {</div><div class='add'>+		num_entries = sizeof(easf_reducer_gain4_6tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_reducer_gain4_6tap_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 4) {</div><div class='add'>+		num_entries = sizeof(easf_gain_ring6_4tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_gain_ring6_4tap_lookup, num_entries);</div><div class='add'>+	} else if (taps == 6) {</div><div class='add'>+		num_entries = sizeof(easf_gain_ring6_6tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_gain_ring6_6tap_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 4) {</div><div class='add'>+		num_entries = sizeof(easf_gain_ring4_4tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_gain_ring4_4tap_lookup, num_entries);</div><div class='add'>+	} else if (taps == 6) {</div><div class='add'>+		num_entries = sizeof(easf_gain_ring4_6tap_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_gain_ring4_6tap_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 3) {</div><div class='add'>+		num_entries = sizeof(easf_3tap_dntilt_uptilt_offset_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_3tap_dntilt_uptilt_offset_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 3) {</div><div class='add'>+		num_entries = sizeof(easf_3tap_uptilt_maxval_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_3tap_uptilt_maxval_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 3) {</div><div class='add'>+		num_entries = sizeof(easf_3tap_dntilt_slope_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_3tap_dntilt_slope_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 3) {</div><div class='add'>+		num_entries = sizeof(easf_3tap_uptilt1_slope_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_3tap_uptilt1_slope_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 3) {</div><div class='add'>+		num_entries = sizeof(easf_3tap_uptilt2_slope_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_3tap_uptilt2_slope_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='add'>+uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	uint32_t value;</div><div class='add'>+	unsigned int num_entries;</div><div class='add'>+</div><div class='add'>+	if (taps == 3) {</div><div class='add'>+		num_entries = sizeof(easf_3tap_uptilt2_offset_lookup) /</div><div class='add'>+			sizeof(struct scale_ratio_to_reg_value_lookup);</div><div class='add'>+		value = spl_easf_get_scale_ratio_to_reg_value(ratio,</div><div class='add'>+			easf_3tap_uptilt2_offset_lookup, num_entries);</div><div class='add'>+	} else</div><div class='add'>+		value = 0;</div><div class='add'>+	return value;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h<br/>new file mode 100644<br/>index 000000000000..321ae22a04d4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+</div><div class='add'>+/* Copyright 2024 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_SCL_EASF_FILTERS_H__</div><div class='add'>+#define __DC_SPL_SCL_EASF_FILTERS_H__</div><div class='add'>+</div><div class='add'>+#include "dc_spl_types.h"</div><div class='add'>+</div><div class='add'>+struct scale_ratio_to_reg_value_lookup {</div><div class='add'>+	int numer;</div><div class='add'>+	int denom;</div><div class='add'>+	const uint32_t reg_value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,</div><div class='add'>+	const struct spl_scaler_data *data, bool enable_easf_v,</div><div class='add'>+	bool enable_easf_h);</div><div class='add'>+</div><div class='add'>+uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+</div><div class='add'>+/* public API */</div><div class='add'>+const uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+const uint16_t *spl_dscl_get_easf_filter_coeffs_64p_s1_10(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_SCL_EASF_FILTERS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c<br/>new file mode 100644<br/>index 000000000000..5e52bdf1ad44<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c</a></div><div class='hunk'>@@ -0,0 +1,1233 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+#include "dc_spl_scl_filters.h"</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 2</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.833333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt; = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt; = s1.10</div><div class='add'>+// &lt;CoefOut&gt; = s1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_2tap_64p[66] = {</div><div class='add'>+		0x1000, 0x0000,</div><div class='add'>+		0x1000, 0x0000,</div><div class='add'>+		0x0FFC, 0x0004,</div><div class='add'>+		0x0FF8, 0x0008,</div><div class='add'>+		0x0FF0, 0x0010,</div><div class='add'>+		0x0FE4, 0x001C,</div><div class='add'>+		0x0FD8, 0x0028,</div><div class='add'>+		0x0FC4, 0x003C,</div><div class='add'>+		0x0FB0, 0x0050,</div><div class='add'>+		0x0F98, 0x0068,</div><div class='add'>+		0x0F7C, 0x0084,</div><div class='add'>+		0x0F58, 0x00A8,</div><div class='add'>+		0x0F34, 0x00CC,</div><div class='add'>+		0x0F08, 0x00F8,</div><div class='add'>+		0x0ED8, 0x0128,</div><div class='add'>+		0x0EA4, 0x015C,</div><div class='add'>+		0x0E68, 0x0198,</div><div class='add'>+		0x0E28, 0x01D8,</div><div class='add'>+		0x0DE4, 0x021C,</div><div class='add'>+		0x0D98, 0x0268,</div><div class='add'>+		0x0D44, 0x02BC,</div><div class='add'>+		0x0CEC, 0x0314,</div><div class='add'>+		0x0C90, 0x0370,</div><div class='add'>+		0x0C2C, 0x03D4,</div><div class='add'>+		0x0BC4, 0x043C,</div><div class='add'>+		0x0B58, 0x04A8,</div><div class='add'>+		0x0AE8, 0x0518,</div><div class='add'>+		0x0A74, 0x058C,</div><div class='add'>+		0x09FC, 0x0604,</div><div class='add'>+		0x0980, 0x0680,</div><div class='add'>+		0x0900, 0x0700,</div><div class='add'>+		0x0880, 0x0780,</div><div class='add'>+		0x0800, 0x0800</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 3</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.83333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_3tap_64p_upscale[99] = {</div><div class='add'>+		0x0804, 0x07FC, 0x0000,</div><div class='add'>+		0x07A8, 0x0860, 0x3FF8,</div><div class='add'>+		0x0754, 0x08BC, 0x3FF0,</div><div class='add'>+		0x0700, 0x0918, 0x3FE8,</div><div class='add'>+		0x06AC, 0x0978, 0x3FDC,</div><div class='add'>+		0x0654, 0x09D8, 0x3FD4,</div><div class='add'>+		0x0604, 0x0A34, 0x3FC8,</div><div class='add'>+		0x05B0, 0x0A90, 0x3FC0,</div><div class='add'>+		0x055C, 0x0AF0, 0x3FB4,</div><div class='add'>+		0x050C, 0x0B48, 0x3FAC,</div><div class='add'>+		0x04BC, 0x0BA0, 0x3FA4,</div><div class='add'>+		0x0470, 0x0BF4, 0x3F9C,</div><div class='add'>+		0x0420, 0x0C50, 0x3F90,</div><div class='add'>+		0x03D8, 0x0C9C, 0x3F8C,</div><div class='add'>+		0x038C, 0x0CF0, 0x3F84,</div><div class='add'>+		0x0344, 0x0D40, 0x3F7C,</div><div class='add'>+		0x0300, 0x0D88, 0x3F78,</div><div class='add'>+		0x02BC, 0x0DD0, 0x3F74,</div><div class='add'>+		0x027C, 0x0E14, 0x3F70,</div><div class='add'>+		0x023C, 0x0E54, 0x3F70,</div><div class='add'>+		0x0200, 0x0E90, 0x3F70,</div><div class='add'>+		0x01C8, 0x0EC8, 0x3F70,</div><div class='add'>+		0x0190, 0x0EFC, 0x3F74,</div><div class='add'>+		0x015C, 0x0F2C, 0x3F78,</div><div class='add'>+		0x0128, 0x0F5C, 0x3F7C,</div><div class='add'>+		0x00FC, 0x0F7C, 0x3F88,</div><div class='add'>+		0x00CC, 0x0FA4, 0x3F90,</div><div class='add'>+		0x00A4, 0x0FC0, 0x3F9C,</div><div class='add'>+		0x007C, 0x0FD8, 0x3FAC,</div><div class='add'>+		0x0058, 0x0FE8, 0x3FC0,</div><div class='add'>+		0x0038, 0x0FF4, 0x3FD4,</div><div class='add'>+		0x0018, 0x1000, 0x3FE8,</div><div class='add'>+		0x0000, 0x1000, 0x0000</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 3</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.16666 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_3tap_64p_116[99] = {</div><div class='add'>+		0x0804, 0x07FC, 0x0000,</div><div class='add'>+		0x07C0, 0x0844, 0x3FFC,</div><div class='add'>+		0x0780, 0x0888, 0x3FF8,</div><div class='add'>+		0x0740, 0x08D0, 0x3FF0,</div><div class='add'>+		0x0700, 0x0914, 0x3FEC,</div><div class='add'>+		0x06C0, 0x0958, 0x3FE8,</div><div class='add'>+		0x0684, 0x0998, 0x3FE4,</div><div class='add'>+		0x0644, 0x09DC, 0x3FE0,</div><div class='add'>+		0x0604, 0x0A1C, 0x3FE0,</div><div class='add'>+		0x05C4, 0x0A5C, 0x3FE0,</div><div class='add'>+		0x0588, 0x0A9C, 0x3FDC,</div><div class='add'>+		0x0548, 0x0ADC, 0x3FDC,</div><div class='add'>+		0x050C, 0x0B14, 0x3FE0,</div><div class='add'>+		0x04CC, 0x0B54, 0x3FE0,</div><div class='add'>+		0x0490, 0x0B8C, 0x3FE4,</div><div class='add'>+		0x0458, 0x0BC0, 0x3FE8,</div><div class='add'>+		0x041C, 0x0BF4, 0x3FF0,</div><div class='add'>+		0x03E0, 0x0C28, 0x3FF8,</div><div class='add'>+		0x03A8, 0x0C58, 0x0000,</div><div class='add'>+		0x0374, 0x0C88, 0x0004,</div><div class='add'>+		0x0340, 0x0CB0, 0x0010,</div><div class='add'>+		0x0308, 0x0CD8, 0x0020,</div><div class='add'>+		0x02D8, 0x0CFC, 0x002C,</div><div class='add'>+		0x02A0, 0x0D20, 0x0040,</div><div class='add'>+		0x0274, 0x0D3C, 0x0050,</div><div class='add'>+		0x0244, 0x0D58, 0x0064,</div><div class='add'>+		0x0214, 0x0D70, 0x007C,</div><div class='add'>+		0x01E8, 0x0D84, 0x0094,</div><div class='add'>+		0x01C0, 0x0D94, 0x00AC,</div><div class='add'>+		0x0198, 0x0DA0, 0x00C8,</div><div class='add'>+		0x0170, 0x0DAC, 0x00E4,</div><div class='add'>+		0x014C, 0x0DB0, 0x0104,</div><div class='add'>+		0x0128, 0x0DB4, 0x0124</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 3</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.49999 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_3tap_64p_149[99] = {</div><div class='add'>+		0x0804, 0x07FC, 0x0000,</div><div class='add'>+		0x07CC, 0x0834, 0x0000,</div><div class='add'>+		0x0798, 0x0868, 0x0000,</div><div class='add'>+		0x0764, 0x089C, 0x0000,</div><div class='add'>+		0x0730, 0x08CC, 0x0004,</div><div class='add'>+		0x0700, 0x08FC, 0x0004,</div><div class='add'>+		0x06CC, 0x092C, 0x0008,</div><div class='add'>+		0x0698, 0x095C, 0x000C,</div><div class='add'>+		0x0660, 0x098C, 0x0014,</div><div class='add'>+		0x062C, 0x09B8, 0x001C,</div><div class='add'>+		0x05FC, 0x09E4, 0x0020,</div><div class='add'>+		0x05C4, 0x0A10, 0x002C,</div><div class='add'>+		0x0590, 0x0A3C, 0x0034,</div><div class='add'>+		0x055C, 0x0A64, 0x0040,</div><div class='add'>+		0x0528, 0x0A8C, 0x004C,</div><div class='add'>+		0x04F8, 0x0AB0, 0x0058,</div><div class='add'>+		0x04C4, 0x0AD4, 0x0068,</div><div class='add'>+		0x0490, 0x0AF8, 0x0078,</div><div class='add'>+		0x0460, 0x0B18, 0x0088,</div><div class='add'>+		0x0430, 0x0B38, 0x0098,</div><div class='add'>+		0x0400, 0x0B54, 0x00AC,</div><div class='add'>+		0x03D0, 0x0B6C, 0x00C4,</div><div class='add'>+		0x03A0, 0x0B88, 0x00D8,</div><div class='add'>+		0x0374, 0x0B9C, 0x00F0,</div><div class='add'>+		0x0348, 0x0BB0, 0x0108,</div><div class='add'>+		0x0318, 0x0BC4, 0x0124,</div><div class='add'>+		0x02EC, 0x0BD4, 0x0140,</div><div class='add'>+		0x02C4, 0x0BE0, 0x015C,</div><div class='add'>+		0x029C, 0x0BEC, 0x0178,</div><div class='add'>+		0x0274, 0x0BF4, 0x0198,</div><div class='add'>+		0x024C, 0x0BFC, 0x01B8,</div><div class='add'>+		0x0228, 0x0BFC, 0x01DC,</div><div class='add'>+		0x0200, 0x0C00, 0x0200</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 3</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.83332 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_3tap_64p_183[99] = {</div><div class='add'>+		0x0804, 0x07FC, 0x0000,</div><div class='add'>+		0x07D4, 0x0824, 0x0008,</div><div class='add'>+		0x07AC, 0x0840, 0x0014,</div><div class='add'>+		0x0780, 0x0860, 0x0020,</div><div class='add'>+		0x0754, 0x0880, 0x002C,</div><div class='add'>+		0x0728, 0x089C, 0x003C,</div><div class='add'>+		0x0700, 0x08B8, 0x0048,</div><div class='add'>+		0x06D4, 0x08D4, 0x0058,</div><div class='add'>+		0x06A8, 0x08F0, 0x0068,</div><div class='add'>+		0x067C, 0x090C, 0x0078,</div><div class='add'>+		0x0650, 0x0924, 0x008C,</div><div class='add'>+		0x0628, 0x093C, 0x009C,</div><div class='add'>+		0x05FC, 0x0954, 0x00B0,</div><div class='add'>+		0x05D0, 0x096C, 0x00C4,</div><div class='add'>+		0x05A8, 0x0980, 0x00D8,</div><div class='add'>+		0x0578, 0x0998, 0x00F0,</div><div class='add'>+		0x0550, 0x09AC, 0x0104,</div><div class='add'>+		0x0528, 0x09BC, 0x011C,</div><div class='add'>+		0x04FC, 0x09D0, 0x0134,</div><div class='add'>+		0x04D4, 0x09E0, 0x014C,</div><div class='add'>+		0x04A8, 0x09F0, 0x0168,</div><div class='add'>+		0x0480, 0x09FC, 0x0184,</div><div class='add'>+		0x045C, 0x0A08, 0x019C,</div><div class='add'>+		0x0434, 0x0A14, 0x01B8,</div><div class='add'>+		0x0408, 0x0A20, 0x01D8,</div><div class='add'>+		0x03E0, 0x0A2C, 0x01F4,</div><div class='add'>+		0x03B8, 0x0A34, 0x0214,</div><div class='add'>+		0x0394, 0x0A38, 0x0234,</div><div class='add'>+		0x036C, 0x0A40, 0x0254,</div><div class='add'>+		0x0348, 0x0A44, 0x0274,</div><div class='add'>+		0x0324, 0x0A48, 0x0294,</div><div class='add'>+		0x0300, 0x0A48, 0x02B8,</div><div class='add'>+		0x02DC, 0x0A48, 0x02DC</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 4</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.83333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_4tap_64p_upscale[132] = {</div><div class='add'>+		0x0000, 0x1000, 0x0000, 0x0000,</div><div class='add'>+		0x3FDC, 0x0FFC, 0x0028, 0x0000,</div><div class='add'>+		0x3FB4, 0x0FF8, 0x0054, 0x0000,</div><div class='add'>+		0x3F94, 0x0FE8, 0x0084, 0x0000,</div><div class='add'>+		0x3F74, 0x0FDC, 0x00B4, 0x3FFC,</div><div class='add'>+		0x3F58, 0x0FC4, 0x00E8, 0x3FFC,</div><div class='add'>+		0x3F3C, 0x0FAC, 0x0120, 0x3FF8,</div><div class='add'>+		0x3F24, 0x0F90, 0x0158, 0x3FF4,</div><div class='add'>+		0x3F0C, 0x0F70, 0x0194, 0x3FF0,</div><div class='add'>+		0x3EF8, 0x0F4C, 0x01D0, 0x3FEC,</div><div class='add'>+		0x3EE8, 0x0F20, 0x0210, 0x3FE8,</div><div class='add'>+		0x3ED8, 0x0EF4, 0x0254, 0x3FE0,</div><div class='add'>+		0x3ECC, 0x0EC4, 0x0298, 0x3FD8,</div><div class='add'>+		0x3EC0, 0x0E90, 0x02DC, 0x3FD4,</div><div class='add'>+		0x3EB8, 0x0E58, 0x0324, 0x3FCC,</div><div class='add'>+		0x3EB0, 0x0E20, 0x036C, 0x3FC4,</div><div class='add'>+		0x3EAC, 0x0DE4, 0x03B8, 0x3FB8,</div><div class='add'>+		0x3EA8, 0x0DA4, 0x0404, 0x3FB0,</div><div class='add'>+		0x3EA4, 0x0D60, 0x0454, 0x3FA8,</div><div class='add'>+		0x3EA4, 0x0D1C, 0x04A4, 0x3F9C,</div><div class='add'>+		0x3EA4, 0x0CD8, 0x04F4, 0x3F90,</div><div class='add'>+		0x3EA8, 0x0C88, 0x0548, 0x3F88,</div><div class='add'>+		0x3EAC, 0x0C3C, 0x059C, 0x3F7C,</div><div class='add'>+		0x3EB0, 0x0BF0, 0x05F0, 0x3F70,</div><div class='add'>+		0x3EB8, 0x0BA0, 0x0644, 0x3F64,</div><div class='add'>+		0x3EBC, 0x0B54, 0x0698, 0x3F58,</div><div class='add'>+		0x3EC4, 0x0B00, 0x06F0, 0x3F4C,</div><div class='add'>+		0x3ECC, 0x0AAC, 0x0748, 0x3F40,</div><div class='add'>+		0x3ED8, 0x0A54, 0x07A0, 0x3F34,</div><div class='add'>+		0x3EE0, 0x0A04, 0x07F8, 0x3F24,</div><div class='add'>+		0x3EEC, 0x09AC, 0x0850, 0x3F18,</div><div class='add'>+		0x3EF8, 0x0954, 0x08A8, 0x3F0C,</div><div class='add'>+		0x3F00, 0x08FC, 0x0900, 0x3F04</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 4</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.16666 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_4tap_64p_116[132] = {</div><div class='add'>+		0x01A8, 0x0CB4, 0x01A4, 0x0000,</div><div class='add'>+		0x017C, 0x0CB8, 0x01D0, 0x3FFC,</div><div class='add'>+		0x0158, 0x0CB8, 0x01F8, 0x3FF8,</div><div class='add'>+		0x0130, 0x0CB4, 0x0228, 0x3FF4,</div><div class='add'>+		0x0110, 0x0CB0, 0x0254, 0x3FEC,</div><div class='add'>+		0x00EC, 0x0CA8, 0x0284, 0x3FE8,</div><div class='add'>+		0x00CC, 0x0C9C, 0x02B4, 0x3FE4,</div><div class='add'>+		0x00AC, 0x0C90, 0x02E8, 0x3FDC,</div><div class='add'>+		0x0090, 0x0C80, 0x031C, 0x3FD4,</div><div class='add'>+		0x0070, 0x0C70, 0x0350, 0x3FD0,</div><div class='add'>+		0x0058, 0x0C5C, 0x0384, 0x3FC8,</div><div class='add'>+		0x003C, 0x0C48, 0x03BC, 0x3FC0,</div><div class='add'>+		0x0024, 0x0C2C, 0x03F4, 0x3FBC,</div><div class='add'>+		0x0010, 0x0C10, 0x042C, 0x3FB4,</div><div class='add'>+		0x3FFC, 0x0BF4, 0x0464, 0x3FAC,</div><div class='add'>+		0x3FE8, 0x0BD4, 0x04A0, 0x3FA4,</div><div class='add'>+		0x3FD8, 0x0BAC, 0x04DC, 0x3FA0,</div><div class='add'>+		0x3FC4, 0x0B8C, 0x0518, 0x3F98,</div><div class='add'>+		0x3FB4, 0x0B68, 0x0554, 0x3F90,</div><div class='add'>+		0x3FA8, 0x0B40, 0x0590, 0x3F88,</div><div class='add'>+		0x3F9C, 0x0B14, 0x05CC, 0x3F84,</div><div class='add'>+		0x3F90, 0x0AEC, 0x0608, 0x3F7C,</div><div class='add'>+		0x3F84, 0x0ABC, 0x0648, 0x3F78,</div><div class='add'>+		0x3F7C, 0x0A90, 0x0684, 0x3F70,</div><div class='add'>+		0x3F70, 0x0A60, 0x06C4, 0x3F6C,</div><div class='add'>+		0x3F6C, 0x0A2C, 0x0700, 0x3F68,</div><div class='add'>+		0x3F64, 0x09F8, 0x0740, 0x3F64,</div><div class='add'>+		0x3F60, 0x09C4, 0x077C, 0x3F60,</div><div class='add'>+		0x3F5C, 0x098C, 0x07BC, 0x3F5C,</div><div class='add'>+		0x3F58, 0x0958, 0x07F8, 0x3F58,</div><div class='add'>+		0x3F58, 0x091C, 0x0834, 0x3F58,</div><div class='add'>+		0x3F54, 0x08E4, 0x0870, 0x3F58,</div><div class='add'>+		0x3F54, 0x08AC, 0x08AC, 0x3F54</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 4</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.49999 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_4tap_64p_149[132] = {</div><div class='add'>+		0x02B8, 0x0A90, 0x02B8, 0x0000,</div><div class='add'>+		0x0294, 0x0A94, 0x02DC, 0x3FFC,</div><div class='add'>+		0x0274, 0x0A94, 0x0300, 0x3FF8,</div><div class='add'>+		0x0250, 0x0A94, 0x0328, 0x3FF4,</div><div class='add'>+		0x0230, 0x0A90, 0x0350, 0x3FF0,</div><div class='add'>+		0x0214, 0x0A8C, 0x0374, 0x3FEC,</div><div class='add'>+		0x01F0, 0x0A88, 0x03A0, 0x3FE8,</div><div class='add'>+		0x01D4, 0x0A80, 0x03C8, 0x3FE4,</div><div class='add'>+		0x01B8, 0x0A78, 0x03F0, 0x3FE0,</div><div class='add'>+		0x0198, 0x0A70, 0x041C, 0x3FDC,</div><div class='add'>+		0x0180, 0x0A64, 0x0444, 0x3FD8,</div><div class='add'>+		0x0164, 0x0A54, 0x0470, 0x3FD8,</div><div class='add'>+		0x0148, 0x0A48, 0x049C, 0x3FD4,</div><div class='add'>+		0x0130, 0x0A38, 0x04C8, 0x3FD0,</div><div class='add'>+		0x0118, 0x0A24, 0x04F4, 0x3FD0,</div><div class='add'>+		0x0100, 0x0A14, 0x0520, 0x3FCC,</div><div class='add'>+		0x00E8, 0x0A00, 0x054C, 0x3FCC,</div><div class='add'>+		0x00D4, 0x09E8, 0x057C, 0x3FC8,</div><div class='add'>+		0x00C0, 0x09D0, 0x05A8, 0x3FC8,</div><div class='add'>+		0x00AC, 0x09B8, 0x05D4, 0x3FC8,</div><div class='add'>+		0x0098, 0x09A0, 0x0600, 0x3FC8,</div><div class='add'>+		0x0084, 0x0984, 0x0630, 0x3FC8,</div><div class='add'>+		0x0074, 0x0964, 0x065C, 0x3FCC,</div><div class='add'>+		0x0064, 0x0948, 0x0688, 0x3FCC,</div><div class='add'>+		0x0054, 0x0928, 0x06B4, 0x3FD0,</div><div class='add'>+		0x0044, 0x0908, 0x06E0, 0x3FD4,</div><div class='add'>+		0x0038, 0x08E8, 0x070C, 0x3FD4,</div><div class='add'>+		0x002C, 0x08C4, 0x0738, 0x3FD8,</div><div class='add'>+		0x001C, 0x08A4, 0x0760, 0x3FE0,</div><div class='add'>+		0x0014, 0x087C, 0x078C, 0x3FE4,</div><div class='add'>+		0x0008, 0x0858, 0x07B4, 0x3FEC,</div><div class='add'>+		0x0000, 0x0830, 0x07DC, 0x3FF4,</div><div class='add'>+		0x3FFC, 0x0804, 0x0804, 0x3FFC</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 4</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.83332 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_4tap_64p_183[132] = {</div><div class='add'>+		0x03B0, 0x08A0, 0x03B0, 0x0000,</div><div class='add'>+		0x0394, 0x08A0, 0x03CC, 0x0000,</div><div class='add'>+		0x037C, 0x089C, 0x03E8, 0x0000,</div><div class='add'>+		0x0360, 0x089C, 0x0400, 0x0004,</div><div class='add'>+		0x0348, 0x0898, 0x041C, 0x0004,</div><div class='add'>+		0x032C, 0x0894, 0x0438, 0x0008,</div><div class='add'>+		0x0310, 0x0890, 0x0454, 0x000C,</div><div class='add'>+		0x02F8, 0x0888, 0x0474, 0x000C,</div><div class='add'>+		0x02DC, 0x0884, 0x0490, 0x0010,</div><div class='add'>+		0x02C4, 0x087C, 0x04AC, 0x0014,</div><div class='add'>+		0x02AC, 0x0874, 0x04C8, 0x0018,</div><div class='add'>+		0x0290, 0x086C, 0x04E4, 0x0020,</div><div class='add'>+		0x0278, 0x0864, 0x0500, 0x0024,</div><div class='add'>+		0x0264, 0x0858, 0x051C, 0x0028,</div><div class='add'>+		0x024C, 0x084C, 0x0538, 0x0030,</div><div class='add'>+		0x0234, 0x0844, 0x0554, 0x0034,</div><div class='add'>+		0x021C, 0x0838, 0x0570, 0x003C,</div><div class='add'>+		0x0208, 0x0828, 0x058C, 0x0044,</div><div class='add'>+		0x01F0, 0x081C, 0x05A8, 0x004C,</div><div class='add'>+		0x01DC, 0x080C, 0x05C4, 0x0054,</div><div class='add'>+		0x01C8, 0x07FC, 0x05E0, 0x005C,</div><div class='add'>+		0x01B4, 0x07EC, 0x05FC, 0x0064,</div><div class='add'>+		0x019C, 0x07DC, 0x0618, 0x0070,</div><div class='add'>+		0x018C, 0x07CC, 0x0630, 0x0078,</div><div class='add'>+		0x0178, 0x07B8, 0x064C, 0x0084,</div><div class='add'>+		0x0164, 0x07A8, 0x0664, 0x0090,</div><div class='add'>+		0x0150, 0x0794, 0x0680, 0x009C,</div><div class='add'>+		0x0140, 0x0780, 0x0698, 0x00A8,</div><div class='add'>+		0x0130, 0x076C, 0x06B0, 0x00B4,</div><div class='add'>+		0x0120, 0x0758, 0x06C8, 0x00C0,</div><div class='add'>+		0x0110, 0x0740, 0x06E0, 0x00D0,</div><div class='add'>+		0x0100, 0x072C, 0x06F8, 0x00DC,</div><div class='add'>+		0x00F0, 0x0714, 0x0710, 0x00EC</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 5</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.83333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_5tap_64p_upscale[165] = {</div><div class='add'>+		0x3E40, 0x09C0, 0x09C0, 0x3E40, 0x0000,</div><div class='add'>+		0x3E50, 0x0964, 0x0A18, 0x3E34, 0x0000,</div><div class='add'>+		0x3E5C, 0x0908, 0x0A6C, 0x3E2C, 0x0004,</div><div class='add'>+		0x3E6C, 0x08AC, 0x0AC0, 0x3E20, 0x0008,</div><div class='add'>+		0x3E78, 0x0850, 0x0B14, 0x3E18, 0x000C,</div><div class='add'>+		0x3E88, 0x07F4, 0x0B60, 0x3E14, 0x0010,</div><div class='add'>+		0x3E98, 0x0798, 0x0BB0, 0x3E0C, 0x0014,</div><div class='add'>+		0x3EA8, 0x073C, 0x0C00, 0x3E08, 0x0014,</div><div class='add'>+		0x3EB8, 0x06E4, 0x0C48, 0x3E04, 0x0018,</div><div class='add'>+		0x3ECC, 0x0684, 0x0C90, 0x3E04, 0x001C,</div><div class='add'>+		0x3EDC, 0x062C, 0x0CD4, 0x3E04, 0x0020,</div><div class='add'>+		0x3EEC, 0x05D4, 0x0D1C, 0x3E04, 0x0020,</div><div class='add'>+		0x3EFC, 0x057C, 0x0D5C, 0x3E08, 0x0024,</div><div class='add'>+		0x3F0C, 0x0524, 0x0D98, 0x3E10, 0x0028,</div><div class='add'>+		0x3F20, 0x04CC, 0x0DD8, 0x3E14, 0x0028,</div><div class='add'>+		0x3F30, 0x0478, 0x0E14, 0x3E1C, 0x0028,</div><div class='add'>+		0x3F40, 0x0424, 0x0E48, 0x3E28, 0x002C,</div><div class='add'>+		0x3F50, 0x03D4, 0x0E7C, 0x3E34, 0x002C,</div><div class='add'>+		0x3F60, 0x0384, 0x0EAC, 0x3E44, 0x002C,</div><div class='add'>+		0x3F6C, 0x0338, 0x0EDC, 0x3E54, 0x002C,</div><div class='add'>+		0x3F7C, 0x02E8, 0x0F08, 0x3E68, 0x002C,</div><div class='add'>+		0x3F8C, 0x02A0, 0x0F2C, 0x3E7C, 0x002C,</div><div class='add'>+		0x3F98, 0x0258, 0x0F50, 0x3E94, 0x002C,</div><div class='add'>+		0x3FA4, 0x0210, 0x0F74, 0x3EB0, 0x0028,</div><div class='add'>+		0x3FB0, 0x01CC, 0x0F90, 0x3ECC, 0x0028,</div><div class='add'>+		0x3FC0, 0x018C, 0x0FA8, 0x3EE8, 0x0024,</div><div class='add'>+		0x3FC8, 0x014C, 0x0FC0, 0x3F0C, 0x0020,</div><div class='add'>+		0x3FD4, 0x0110, 0x0FD4, 0x3F2C, 0x001C,</div><div class='add'>+		0x3FE0, 0x00D4, 0x0FE0, 0x3F54, 0x0018,</div><div class='add'>+		0x3FE8, 0x009C, 0x0FF0, 0x3F7C, 0x0010,</div><div class='add'>+		0x3FF0, 0x0064, 0x0FFC, 0x3FA4, 0x000C,</div><div class='add'>+		0x3FFC, 0x0030, 0x0FFC, 0x3FD4, 0x0004,</div><div class='add'>+		0x0000, 0x0000, 0x1000, 0x0000, 0x0000</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 5</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.16666 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_5tap_64p_116[165] = {</div><div class='add'>+		0x3EDC, 0x0924, 0x0924, 0x3EDC, 0x0000,</div><div class='add'>+		0x3ED8, 0x08EC, 0x095C, 0x3EE0, 0x0000,</div><div class='add'>+		0x3ED4, 0x08B0, 0x0994, 0x3EE8, 0x0000,</div><div class='add'>+		0x3ED0, 0x0878, 0x09C8, 0x3EF0, 0x0000,</div><div class='add'>+		0x3ED0, 0x083C, 0x09FC, 0x3EF8, 0x0000,</div><div class='add'>+		0x3ED0, 0x0800, 0x0A2C, 0x3F04, 0x0000,</div><div class='add'>+		0x3ED0, 0x07C4, 0x0A5C, 0x3F10, 0x0000,</div><div class='add'>+		0x3ED0, 0x0788, 0x0A8C, 0x3F1C, 0x0000,</div><div class='add'>+		0x3ED0, 0x074C, 0x0AC0, 0x3F28, 0x3FFC,</div><div class='add'>+		0x3ED4, 0x0710, 0x0AE8, 0x3F38, 0x3FFC,</div><div class='add'>+		0x3ED8, 0x06D0, 0x0B18, 0x3F48, 0x3FF8,</div><div class='add'>+		0x3EDC, 0x0694, 0x0B3C, 0x3F5C, 0x3FF8,</div><div class='add'>+		0x3EE0, 0x0658, 0x0B68, 0x3F6C, 0x3FF4,</div><div class='add'>+		0x3EE4, 0x061C, 0x0B90, 0x3F80, 0x3FF0,</div><div class='add'>+		0x3EEC, 0x05DC, 0x0BB4, 0x3F98, 0x3FEC,</div><div class='add'>+		0x3EF0, 0x05A0, 0x0BD8, 0x3FB0, 0x3FE8,</div><div class='add'>+		0x3EF8, 0x0564, 0x0BF8, 0x3FC8, 0x3FE4,</div><div class='add'>+		0x3EFC, 0x0528, 0x0C1C, 0x3FE0, 0x3FE0,</div><div class='add'>+		0x3F04, 0x04EC, 0x0C38, 0x3FFC, 0x3FDC,</div><div class='add'>+		0x3F0C, 0x04B4, 0x0C54, 0x0014, 0x3FD8,</div><div class='add'>+		0x3F14, 0x047C, 0x0C70, 0x0030, 0x3FD0,</div><div class='add'>+		0x3F1C, 0x0440, 0x0C88, 0x0050, 0x3FCC,</div><div class='add'>+		0x3F24, 0x0408, 0x0CA0, 0x0070, 0x3FC4,</div><div class='add'>+		0x3F2C, 0x03D0, 0x0CB0, 0x0094, 0x3FC0,</div><div class='add'>+		0x3F34, 0x0398, 0x0CC4, 0x00B8, 0x3FB8,</div><div class='add'>+		0x3F3C, 0x0364, 0x0CD4, 0x00DC, 0x3FB0,</div><div class='add'>+		0x3F48, 0x032C, 0x0CE0, 0x0100, 0x3FAC,</div><div class='add'>+		0x3F50, 0x02F8, 0x0CEC, 0x0128, 0x3FA4,</div><div class='add'>+		0x3F58, 0x02C4, 0x0CF8, 0x0150, 0x3F9C,</div><div class='add'>+		0x3F60, 0x0290, 0x0D00, 0x017C, 0x3F94,</div><div class='add'>+		0x3F68, 0x0260, 0x0D04, 0x01A8, 0x3F8C,</div><div class='add'>+		0x3F74, 0x0230, 0x0D04, 0x01D4, 0x3F84,</div><div class='add'>+		0x3F7C, 0x0200, 0x0D08, 0x0200, 0x3F7C</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 5</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.49999 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_5tap_64p_149[165] = {</div><div class='add'>+		0x3FF4, 0x080C, 0x080C, 0x3FF4, 0x0000,</div><div class='add'>+		0x3FE8, 0x07E8, 0x0830, 0x0000, 0x0000,</div><div class='add'>+		0x3FDC, 0x07C8, 0x0850, 0x0010, 0x3FFC,</div><div class='add'>+		0x3FD0, 0x07A4, 0x0878, 0x001C, 0x3FF8,</div><div class='add'>+		0x3FC4, 0x0780, 0x0898, 0x0030, 0x3FF4,</div><div class='add'>+		0x3FB8, 0x075C, 0x08B8, 0x0040, 0x3FF4,</div><div class='add'>+		0x3FB0, 0x0738, 0x08D8, 0x0050, 0x3FF0,</div><div class='add'>+		0x3FA8, 0x0710, 0x08F8, 0x0064, 0x3FEC,</div><div class='add'>+		0x3FA0, 0x06EC, 0x0914, 0x0078, 0x3FE8,</div><div class='add'>+		0x3F98, 0x06C4, 0x0934, 0x008C, 0x3FE4,</div><div class='add'>+		0x3F90, 0x06A0, 0x094C, 0x00A4, 0x3FE0,</div><div class='add'>+		0x3F8C, 0x0678, 0x0968, 0x00B8, 0x3FDC,</div><div class='add'>+		0x3F84, 0x0650, 0x0984, 0x00D0, 0x3FD8,</div><div class='add'>+		0x3F80, 0x0628, 0x099C, 0x00E8, 0x3FD4,</div><div class='add'>+		0x3F7C, 0x0600, 0x09B8, 0x0100, 0x3FCC,</div><div class='add'>+		0x3F78, 0x05D8, 0x09D0, 0x0118, 0x3FC8,</div><div class='add'>+		0x3F74, 0x05B0, 0x09E4, 0x0134, 0x3FC4,</div><div class='add'>+		0x3F70, 0x0588, 0x09F8, 0x0150, 0x3FC0,</div><div class='add'>+		0x3F70, 0x0560, 0x0A08, 0x016C, 0x3FBC,</div><div class='add'>+		0x3F6C, 0x0538, 0x0A20, 0x0188, 0x3FB4,</div><div class='add'>+		0x3F6C, 0x0510, 0x0A30, 0x01A4, 0x3FB0,</div><div class='add'>+		0x3F6C, 0x04E8, 0x0A3C, 0x01C4, 0x3FAC,</div><div class='add'>+		0x3F6C, 0x04C0, 0x0A48, 0x01E4, 0x3FA8,</div><div class='add'>+		0x3F6C, 0x0498, 0x0A58, 0x0200, 0x3FA4,</div><div class='add'>+		0x3F6C, 0x0470, 0x0A60, 0x0224, 0x3FA0,</div><div class='add'>+		0x3F6C, 0x0448, 0x0A70, 0x0244, 0x3F98,</div><div class='add'>+		0x3F70, 0x0420, 0x0A78, 0x0264, 0x3F94,</div><div class='add'>+		0x3F70, 0x03F8, 0x0A80, 0x0288, 0x3F90,</div><div class='add'>+		0x3F74, 0x03D4, 0x0A84, 0x02A8, 0x3F8C,</div><div class='add'>+		0x3F74, 0x03AC, 0x0A8C, 0x02CC, 0x3F88,</div><div class='add'>+		0x3F78, 0x0384, 0x0A90, 0x02F0, 0x3F84,</div><div class='add'>+		0x3F7C, 0x0360, 0x0A90, 0x0314, 0x3F80,</div><div class='add'>+		0x3F7C, 0x033C, 0x0A90, 0x033C, 0x3F7C</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 5</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.83332 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_5tap_64p_183[165] = {</div><div class='add'>+		0x0168, 0x069C, 0x0698, 0x0164, 0x0000,</div><div class='add'>+		0x0154, 0x068C, 0x06AC, 0x0174, 0x0000,</div><div class='add'>+		0x0144, 0x0674, 0x06C0, 0x0188, 0x0000,</div><div class='add'>+		0x0138, 0x0664, 0x06D0, 0x0198, 0x3FFC,</div><div class='add'>+		0x0128, 0x0654, 0x06E0, 0x01A8, 0x3FFC,</div><div class='add'>+		0x0118, 0x0640, 0x06F0, 0x01BC, 0x3FFC,</div><div class='add'>+		0x010C, 0x0630, 0x0700, 0x01CC, 0x3FF8,</div><div class='add'>+		0x00FC, 0x061C, 0x0710, 0x01E0, 0x3FF8,</div><div class='add'>+		0x00F0, 0x060C, 0x071C, 0x01F0, 0x3FF8,</div><div class='add'>+		0x00E4, 0x05F4, 0x072C, 0x0204, 0x3FF8,</div><div class='add'>+		0x00D8, 0x05E4, 0x0738, 0x0218, 0x3FF4,</div><div class='add'>+		0x00CC, 0x05D0, 0x0744, 0x022C, 0x3FF4,</div><div class='add'>+		0x00C0, 0x05B8, 0x0754, 0x0240, 0x3FF4,</div><div class='add'>+		0x00B4, 0x05A4, 0x0760, 0x0254, 0x3FF4,</div><div class='add'>+		0x00A8, 0x0590, 0x076C, 0x0268, 0x3FF4,</div><div class='add'>+		0x009C, 0x057C, 0x0778, 0x027C, 0x3FF4,</div><div class='add'>+		0x0094, 0x0564, 0x0780, 0x0294, 0x3FF4,</div><div class='add'>+		0x0088, 0x0550, 0x0788, 0x02A8, 0x3FF8,</div><div class='add'>+		0x0080, 0x0538, 0x0794, 0x02BC, 0x3FF8,</div><div class='add'>+		0x0074, 0x0524, 0x079C, 0x02D4, 0x3FF8,</div><div class='add'>+		0x006C, 0x0510, 0x07A4, 0x02E8, 0x3FF8,</div><div class='add'>+		0x0064, 0x04F4, 0x07AC, 0x0300, 0x3FFC,</div><div class='add'>+		0x005C, 0x04E4, 0x07B0, 0x0314, 0x3FFC,</div><div class='add'>+		0x0054, 0x04C8, 0x07B8, 0x032C, 0x0000,</div><div class='add'>+		0x004C, 0x04B4, 0x07C0, 0x0340, 0x0000,</div><div class='add'>+		0x0044, 0x04A0, 0x07C4, 0x0358, 0x0000,</div><div class='add'>+		0x003C, 0x0488, 0x07C8, 0x0370, 0x0004,</div><div class='add'>+		0x0038, 0x0470, 0x07CC, 0x0384, 0x0008,</div><div class='add'>+		0x0030, 0x045C, 0x07D0, 0x039C, 0x0008,</div><div class='add'>+		0x002C, 0x0444, 0x07D0, 0x03B4, 0x000C,</div><div class='add'>+		0x0024, 0x042C, 0x07D4, 0x03CC, 0x0010,</div><div class='add'>+		0x0020, 0x0414, 0x07D4, 0x03E0, 0x0018,</div><div class='add'>+		0x001C, 0x03FC, 0x07D4, 0x03F8, 0x001C</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 6</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.83333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_6tap_64p_upscale[198] = {</div><div class='add'>+		0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000,</div><div class='add'>+		0x000C, 0x3FD0, 0x0FFC, 0x0034, 0x3FF4, 0x0000,</div><div class='add'>+		0x0018, 0x3F9C, 0x0FF8, 0x006C, 0x3FE8, 0x0000,</div><div class='add'>+		0x0024, 0x3F6C, 0x0FF0, 0x00A8, 0x3FD8, 0x0000,</div><div class='add'>+		0x002C, 0x3F44, 0x0FE4, 0x00E4, 0x3FC8, 0x0000,</div><div class='add'>+		0x0038, 0x3F18, 0x0FD4, 0x0124, 0x3FB8, 0x0000,</div><div class='add'>+		0x0040, 0x3EF0, 0x0FC0, 0x0164, 0x3FA8, 0x0004,</div><div class='add'>+		0x0048, 0x3EC8, 0x0FAC, 0x01A8, 0x3F98, 0x0004,</div><div class='add'>+		0x0050, 0x3EA8, 0x0F94, 0x01EC, 0x3F84, 0x0004,</div><div class='add'>+		0x0058, 0x3E84, 0x0F74, 0x0234, 0x3F74, 0x0008,</div><div class='add'>+		0x0060, 0x3E68, 0x0F54, 0x027C, 0x3F60, 0x0008,</div><div class='add'>+		0x0064, 0x3E4C, 0x0F30, 0x02C8, 0x3F4C, 0x000C,</div><div class='add'>+		0x006C, 0x3E30, 0x0F04, 0x0314, 0x3F3C, 0x0010,</div><div class='add'>+		0x0070, 0x3E18, 0x0EDC, 0x0360, 0x3F28, 0x0014,</div><div class='add'>+		0x0074, 0x3E04, 0x0EB0, 0x03B0, 0x3F14, 0x0014,</div><div class='add'>+		0x0078, 0x3DF0, 0x0E80, 0x0400, 0x3F00, 0x0018,</div><div class='add'>+		0x0078, 0x3DE0, 0x0E4C, 0x0454, 0x3EEC, 0x001C,</div><div class='add'>+		0x007C, 0x3DD0, 0x0E14, 0x04A8, 0x3ED8, 0x0020,</div><div class='add'>+		0x007C, 0x3DC4, 0x0DDC, 0x04FC, 0x3EC4, 0x0024,</div><div class='add'>+		0x007C, 0x3DBC, 0x0DA0, 0x0550, 0x3EB0, 0x0028,</div><div class='add'>+		0x0080, 0x3DB4, 0x0D5C, 0x05A8, 0x3E9C, 0x002C,</div><div class='add'>+		0x0080, 0x3DAC, 0x0D1C, 0x0600, 0x3E88, 0x0030,</div><div class='add'>+		0x007C, 0x3DA8, 0x0CDC, 0x0658, 0x3E74, 0x0034,</div><div class='add'>+		0x007C, 0x3DA4, 0x0C94, 0x06B0, 0x3E64, 0x0038,</div><div class='add'>+		0x007C, 0x3DA4, 0x0C48, 0x0708, 0x3E50, 0x0040,</div><div class='add'>+		0x0078, 0x3DA4, 0x0C00, 0x0760, 0x3E40, 0x0044,</div><div class='add'>+		0x0078, 0x3DA8, 0x0BB4, 0x07B8, 0x3E2C, 0x0048,</div><div class='add'>+		0x0074, 0x3DAC, 0x0B68, 0x0810, 0x3E1C, 0x004C,</div><div class='add'>+		0x0070, 0x3DB4, 0x0B18, 0x0868, 0x3E0C, 0x0050,</div><div class='add'>+		0x006C, 0x3DBC, 0x0AC4, 0x08C4, 0x3DFC, 0x0054,</div><div class='add'>+		0x0068, 0x3DC4, 0x0A74, 0x0918, 0x3DF0, 0x0058,</div><div class='add'>+		0x0068, 0x3DCC, 0x0A20, 0x0970, 0x3DE0, 0x005C,</div><div class='add'>+		0x0064, 0x3DD4, 0x09C8, 0x09C8, 0x3DD4, 0x0064</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 6</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.16666 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_6tap_64p_116[198] = {</div><div class='add'>+		0x3F0C, 0x0240, 0x0D68, 0x0240, 0x3F0C, 0x0000,</div><div class='add'>+		0x3F18, 0x0210, 0x0D64, 0x0274, 0x3F00, 0x0000,</div><div class='add'>+		0x3F24, 0x01E0, 0x0D58, 0x02A8, 0x3EF8, 0x0004,</div><div class='add'>+		0x3F2C, 0x01B0, 0x0D58, 0x02DC, 0x3EEC, 0x0004,</div><div class='add'>+		0x3F38, 0x0180, 0x0D50, 0x0310, 0x3EE0, 0x0008,</div><div class='add'>+		0x3F44, 0x0154, 0x0D40, 0x0348, 0x3ED8, 0x0008,</div><div class='add'>+		0x3F50, 0x0128, 0x0D34, 0x037C, 0x3ECC, 0x000C,</div><div class='add'>+		0x3F5C, 0x00FC, 0x0D20, 0x03B4, 0x3EC4, 0x0010,</div><div class='add'>+		0x3F64, 0x00D4, 0x0D14, 0x03EC, 0x3EB8, 0x0010,</div><div class='add'>+		0x3F70, 0x00AC, 0x0CFC, 0x0424, 0x3EB0, 0x0014,</div><div class='add'>+		0x3F78, 0x0084, 0x0CE8, 0x0460, 0x3EA8, 0x0014,</div><div class='add'>+		0x3F84, 0x0060, 0x0CCC, 0x0498, 0x3EA0, 0x0018,</div><div class='add'>+		0x3F90, 0x003C, 0x0CB4, 0x04D0, 0x3E98, 0x0018,</div><div class='add'>+		0x3F98, 0x0018, 0x0C9C, 0x050C, 0x3E90, 0x0018,</div><div class='add'>+		0x3FA0, 0x3FFC, 0x0C78, 0x0548, 0x3E88, 0x001C,</div><div class='add'>+		0x3FAC, 0x3FDC, 0x0C54, 0x0584, 0x3E84, 0x001C,</div><div class='add'>+		0x3FB4, 0x3FBC, 0x0C3C, 0x05BC, 0x3E7C, 0x001C,</div><div class='add'>+		0x3FBC, 0x3FA0, 0x0C14, 0x05F8, 0x3E78, 0x0020,</div><div class='add'>+		0x3FC4, 0x3F84, 0x0BF0, 0x0634, 0x3E74, 0x0020,</div><div class='add'>+		0x3FCC, 0x3F68, 0x0BCC, 0x0670, 0x3E70, 0x0020,</div><div class='add'>+		0x3FD4, 0x3F50, 0x0BA4, 0x06AC, 0x3E6C, 0x0020,</div><div class='add'>+		0x3FDC, 0x3F38, 0x0B78, 0x06E8, 0x3E6C, 0x0020,</div><div class='add'>+		0x3FE0, 0x3F24, 0x0B50, 0x0724, 0x3E68, 0x0020,</div><div class='add'>+		0x3FE8, 0x3F0C, 0x0B24, 0x0760, 0x3E68, 0x0020,</div><div class='add'>+		0x3FF0, 0x3EFC, 0x0AF4, 0x0798, 0x3E68, 0x0020,</div><div class='add'>+		0x3FF4, 0x3EE8, 0x0AC8, 0x07D4, 0x3E68, 0x0020,</div><div class='add'>+		0x3FFC, 0x3ED8, 0x0A94, 0x0810, 0x3E6C, 0x001C,</div><div class='add'>+		0x0000, 0x3EC8, 0x0A64, 0x0848, 0x3E70, 0x001C,</div><div class='add'>+		0x0000, 0x3EB8, 0x0A38, 0x0880, 0x3E74, 0x001C,</div><div class='add'>+		0x0004, 0x3EAC, 0x0A04, 0x08BC, 0x3E78, 0x0018,</div><div class='add'>+		0x0008, 0x3EA4, 0x09D0, 0x08F4, 0x3E7C, 0x0014,</div><div class='add'>+		0x000C, 0x3E98, 0x0998, 0x092C, 0x3E84, 0x0014,</div><div class='add'>+		0x0010, 0x3E90, 0x0964, 0x0960, 0x3E8C, 0x0010</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 6</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.49999 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_6tap_64p_149[198] = {</div><div class='add'>+		0x3F14, 0x0394, 0x0AB0, 0x0394, 0x3F14, 0x0000,</div><div class='add'>+		0x3F18, 0x036C, 0x0AB0, 0x03B8, 0x3F14, 0x0000,</div><div class='add'>+		0x3F18, 0x0348, 0x0AAC, 0x03E0, 0x3F14, 0x0000,</div><div class='add'>+		0x3F1C, 0x0320, 0x0AAC, 0x0408, 0x3F10, 0x0000,</div><div class='add'>+		0x3F20, 0x02FC, 0x0AA8, 0x042C, 0x3F10, 0x0000,</div><div class='add'>+		0x3F24, 0x02D8, 0x0AA0, 0x0454, 0x3F10, 0x0000,</div><div class='add'>+		0x3F28, 0x02B4, 0x0A98, 0x047C, 0x3F10, 0x0000,</div><div class='add'>+		0x3F28, 0x0290, 0x0A90, 0x04A4, 0x3F14, 0x0000,</div><div class='add'>+		0x3F30, 0x026C, 0x0A84, 0x04CC, 0x3F14, 0x0000,</div><div class='add'>+		0x3F34, 0x024C, 0x0A7C, 0x04F4, 0x3F14, 0x3FFC,</div><div class='add'>+		0x3F38, 0x0228, 0x0A70, 0x051C, 0x3F18, 0x3FFC,</div><div class='add'>+		0x3F3C, 0x0208, 0x0A64, 0x0544, 0x3F1C, 0x3FF8,</div><div class='add'>+		0x3F40, 0x01E8, 0x0A54, 0x056C, 0x3F20, 0x3FF8,</div><div class='add'>+		0x3F44, 0x01C8, 0x0A48, 0x0594, 0x3F24, 0x3FF4,</div><div class='add'>+		0x3F4C, 0x01A8, 0x0A34, 0x05BC, 0x3F28, 0x3FF4,</div><div class='add'>+		0x3F50, 0x0188, 0x0A28, 0x05E4, 0x3F2C, 0x3FF0,</div><div class='add'>+		0x3F54, 0x016C, 0x0A10, 0x060C, 0x3F34, 0x3FF0,</div><div class='add'>+		0x3F5C, 0x014C, 0x09FC, 0x0634, 0x3F3C, 0x3FEC,</div><div class='add'>+		0x3F60, 0x0130, 0x09EC, 0x065C, 0x3F40, 0x3FE8,</div><div class='add'>+		0x3F68, 0x0114, 0x09D0, 0x0684, 0x3F48, 0x3FE8,</div><div class='add'>+		0x3F6C, 0x00F8, 0x09B8, 0x06AC, 0x3F54, 0x3FE4,</div><div class='add'>+		0x3F74, 0x00E0, 0x09A0, 0x06D0, 0x3F5C, 0x3FE0,</div><div class='add'>+		0x3F78, 0x00C4, 0x098C, 0x06F8, 0x3F64, 0x3FDC,</div><div class='add'>+		0x3F7C, 0x00AC, 0x0970, 0x0720, 0x3F70, 0x3FD8,</div><div class='add'>+		0x3F84, 0x0094, 0x0954, 0x0744, 0x3F7C, 0x3FD4,</div><div class='add'>+		0x3F88, 0x007C, 0x093C, 0x0768, 0x3F88, 0x3FD0,</div><div class='add'>+		0x3F90, 0x0064, 0x091C, 0x0790, 0x3F94, 0x3FCC,</div><div class='add'>+		0x3F94, 0x0050, 0x08FC, 0x07B4, 0x3FA4, 0x3FC8,</div><div class='add'>+		0x3F98, 0x003C, 0x08E0, 0x07D8, 0x3FB0, 0x3FC4,</div><div class='add'>+		0x3FA0, 0x0024, 0x08C0, 0x07FC, 0x3FC0, 0x3FC0,</div><div class='add'>+		0x3FA4, 0x0014, 0x08A4, 0x081C, 0x3FD0, 0x3FB8,</div><div class='add'>+		0x3FAC, 0x0000, 0x0880, 0x0840, 0x3FE0, 0x3FB4,</div><div class='add'>+		0x3FB0, 0x3FF0, 0x0860, 0x0860, 0x3FF0, 0x3FB0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 6</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.83332 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_6tap_64p_183[198] = {</div><div class='add'>+		0x002C, 0x0420, 0x076C, 0x041C, 0x002C, 0x0000,</div><div class='add'>+		0x0028, 0x040C, 0x0768, 0x0430, 0x0034, 0x0000,</div><div class='add'>+		0x0020, 0x03F8, 0x0768, 0x0448, 0x003C, 0x3FFC,</div><div class='add'>+		0x0018, 0x03E4, 0x0768, 0x045C, 0x0044, 0x3FFC,</div><div class='add'>+		0x0014, 0x03D0, 0x0768, 0x0470, 0x004C, 0x3FF8,</div><div class='add'>+		0x000C, 0x03BC, 0x0764, 0x0484, 0x0058, 0x3FF8,</div><div class='add'>+		0x0008, 0x03A4, 0x0764, 0x049C, 0x0060, 0x3FF4,</div><div class='add'>+		0x0004, 0x0390, 0x0760, 0x04B0, 0x0068, 0x3FF4,</div><div class='add'>+		0x0000, 0x037C, 0x0760, 0x04C4, 0x0070, 0x3FF0,</div><div class='add'>+		0x3FFC, 0x0364, 0x075C, 0x04D8, 0x007C, 0x3FF0,</div><div class='add'>+		0x3FF8, 0x0350, 0x0758, 0x04F0, 0x0084, 0x3FEC,</div><div class='add'>+		0x3FF4, 0x033C, 0x0750, 0x0504, 0x0090, 0x3FEC,</div><div class='add'>+		0x3FF0, 0x0328, 0x074C, 0x0518, 0x009C, 0x3FE8,</div><div class='add'>+		0x3FEC, 0x0314, 0x0744, 0x052C, 0x00A8, 0x3FE8,</div><div class='add'>+		0x3FE8, 0x0304, 0x0740, 0x0540, 0x00B0, 0x3FE4,</div><div class='add'>+		0x3FE4, 0x02EC, 0x073C, 0x0554, 0x00BC, 0x3FE4,</div><div class='add'>+		0x3FE0, 0x02DC, 0x0734, 0x0568, 0x00C8, 0x3FE0,</div><div class='add'>+		0x3FE0, 0x02C4, 0x072C, 0x057C, 0x00D4, 0x3FE0,</div><div class='add'>+		0x3FDC, 0x02B4, 0x0724, 0x058C, 0x00E4, 0x3FDC,</div><div class='add'>+		0x3FDC, 0x02A0, 0x0718, 0x05A0, 0x00F0, 0x3FDC,</div><div class='add'>+		0x3FD8, 0x028C, 0x0714, 0x05B4, 0x00FC, 0x3FD8,</div><div class='add'>+		0x3FD8, 0x0278, 0x0704, 0x05C8, 0x010C, 0x3FD8,</div><div class='add'>+		0x3FD4, 0x0264, 0x0700, 0x05D8, 0x0118, 0x3FD8,</div><div class='add'>+		0x3FD4, 0x0254, 0x06F0, 0x05EC, 0x0128, 0x3FD4,</div><div class='add'>+		0x3FD0, 0x0244, 0x06E8, 0x05FC, 0x0134, 0x3FD4,</div><div class='add'>+		0x3FD0, 0x0230, 0x06DC, 0x060C, 0x0144, 0x3FD4,</div><div class='add'>+		0x3FD0, 0x021C, 0x06D0, 0x0620, 0x0154, 0x3FD0,</div><div class='add'>+		0x3FD0, 0x0208, 0x06C4, 0x0630, 0x0164, 0x3FD0,</div><div class='add'>+		0x3FD0, 0x01F8, 0x06B8, 0x0640, 0x0170, 0x3FD0,</div><div class='add'>+		0x3FCC, 0x01E8, 0x06AC, 0x0650, 0x0180, 0x3FD0,</div><div class='add'>+		0x3FCC, 0x01D8, 0x069C, 0x0660, 0x0190, 0x3FD0,</div><div class='add'>+		0x3FCC, 0x01C4, 0x068C, 0x0670, 0x01A4, 0x3FD0,</div><div class='add'>+		0x3FCC, 0x01B8, 0x0680, 0x067C, 0x01B4, 0x3FCC</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 7</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.83333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_7tap_64p_upscale[231] = {</div><div class='add'>+		0x00B0, 0x3D98, 0x09BC, 0x09B8, 0x3D94, 0x00B0, 0x0000,</div><div class='add'>+		0x00AC, 0x3DA0, 0x0968, 0x0A10, 0x3D88, 0x00B4, 0x0000,</div><div class='add'>+		0x00A8, 0x3DAC, 0x0914, 0x0A60, 0x3D80, 0x00B8, 0x0000,</div><div class='add'>+		0x00A4, 0x3DB8, 0x08C0, 0x0AB4, 0x3D78, 0x00BC, 0x3FFC,</div><div class='add'>+		0x00A0, 0x3DC8, 0x0868, 0x0B00, 0x3D74, 0x00C0, 0x3FFC,</div><div class='add'>+		0x0098, 0x3DD8, 0x0818, 0x0B54, 0x3D6C, 0x00C0, 0x3FF8,</div><div class='add'>+		0x0094, 0x3DE8, 0x07C0, 0x0B9C, 0x3D6C, 0x00C4, 0x3FF8,</div><div class='add'>+		0x008C, 0x3DFC, 0x0768, 0x0BEC, 0x3D68, 0x00C4, 0x3FF8,</div><div class='add'>+		0x0088, 0x3E0C, 0x0714, 0x0C38, 0x3D68, 0x00C4, 0x3FF4,</div><div class='add'>+		0x0080, 0x3E20, 0x06BC, 0x0C80, 0x3D6C, 0x00C4, 0x3FF4,</div><div class='add'>+		0x0078, 0x3E34, 0x0668, 0x0CC4, 0x3D70, 0x00C4, 0x3FF4,</div><div class='add'>+		0x0074, 0x3E48, 0x0610, 0x0D08, 0x3D78, 0x00C4, 0x3FF0,</div><div class='add'>+		0x006C, 0x3E5C, 0x05BC, 0x0D48, 0x3D80, 0x00C4, 0x3FF0,</div><div class='add'>+		0x0068, 0x3E74, 0x0568, 0x0D84, 0x3D88, 0x00C0, 0x3FF0,</div><div class='add'>+		0x0060, 0x3E88, 0x0514, 0x0DC8, 0x3D94, 0x00BC, 0x3FEC,</div><div class='add'>+		0x0058, 0x3E9C, 0x04C0, 0x0E04, 0x3DA4, 0x00B8, 0x3FEC,</div><div class='add'>+		0x0054, 0x3EB4, 0x046C, 0x0E38, 0x3DB4, 0x00B4, 0x3FEC,</div><div class='add'>+		0x004C, 0x3ECC, 0x0418, 0x0E6C, 0x3DC8, 0x00B0, 0x3FEC,</div><div class='add'>+		0x0044, 0x3EE0, 0x03C8, 0x0EA4, 0x3DDC, 0x00A8, 0x3FEC,</div><div class='add'>+		0x0040, 0x3EF8, 0x0378, 0x0ED0, 0x3DF4, 0x00A0, 0x3FEC,</div><div class='add'>+		0x0038, 0x3F0C, 0x032C, 0x0EFC, 0x3E10, 0x0098, 0x3FEC,</div><div class='add'>+		0x0034, 0x3F24, 0x02DC, 0x0F24, 0x3E2C, 0x0090, 0x3FEC,</div><div class='add'>+		0x002C, 0x3F38, 0x0294, 0x0F4C, 0x3E48, 0x0088, 0x3FEC,</div><div class='add'>+		0x0028, 0x3F50, 0x0248, 0x0F68, 0x3E6C, 0x007C, 0x3FF0,</div><div class='add'>+		0x0020, 0x3F64, 0x0200, 0x0F88, 0x3E90, 0x0074, 0x3FF0,</div><div class='add'>+		0x001C, 0x3F7C, 0x01B8, 0x0FA4, 0x3EB4, 0x0068, 0x3FF0,</div><div class='add'>+		0x0018, 0x3F90, 0x0174, 0x0FBC, 0x3EDC, 0x0058, 0x3FF4,</div><div class='add'>+		0x0014, 0x3FA4, 0x0130, 0x0FD0, 0x3F08, 0x004C, 0x3FF4,</div><div class='add'>+		0x000C, 0x3FB8, 0x00F0, 0x0FE4, 0x3F34, 0x003C, 0x3FF8,</div><div class='add'>+		0x0008, 0x3FCC, 0x00B0, 0x0FF0, 0x3F64, 0x0030, 0x3FF8,</div><div class='add'>+		0x0004, 0x3FDC, 0x0070, 0x0FFC, 0x3F98, 0x0020, 0x3FFC,</div><div class='add'>+		0x0000, 0x3FF0, 0x0038, 0x0FFC, 0x3FCC, 0x0010, 0x0000,</div><div class='add'>+		0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 7</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.16666 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_7tap_64p_116[231] = {</div><div class='add'>+		0x0020, 0x3E58, 0x0988, 0x0988, 0x3E58, 0x0020, 0x0000,</div><div class='add'>+		0x0024, 0x3E4C, 0x0954, 0x09C0, 0x3E64, 0x0018, 0x0000,</div><div class='add'>+		0x002C, 0x3E44, 0x091C, 0x09F4, 0x3E70, 0x0010, 0x0000,</div><div class='add'>+		0x0030, 0x3E3C, 0x08E8, 0x0A24, 0x3E80, 0x0008, 0x0000,</div><div class='add'>+		0x0034, 0x3E34, 0x08AC, 0x0A5C, 0x3E90, 0x0000, 0x0000,</div><div class='add'>+		0x003C, 0x3E30, 0x0870, 0x0A84, 0x3EA0, 0x3FFC, 0x0004,</div><div class='add'>+		0x0040, 0x3E28, 0x0838, 0x0AB4, 0x3EB4, 0x3FF4, 0x0004,</div><div class='add'>+		0x0044, 0x3E24, 0x07FC, 0x0AE4, 0x3EC8, 0x3FEC, 0x0004,</div><div class='add'>+		0x0048, 0x3E24, 0x07C4, 0x0B08, 0x3EDC, 0x3FE4, 0x0008,</div><div class='add'>+		0x0048, 0x3E20, 0x0788, 0x0B3C, 0x3EF4, 0x3FD8, 0x0008,</div><div class='add'>+		0x004C, 0x3E20, 0x074C, 0x0B60, 0x3F0C, 0x3FD0, 0x000C,</div><div class='add'>+		0x0050, 0x3E20, 0x0710, 0x0B8C, 0x3F24, 0x3FC4, 0x000C,</div><div class='add'>+		0x0050, 0x3E20, 0x06D4, 0x0BB0, 0x3F40, 0x3FBC, 0x0010,</div><div class='add'>+		0x0054, 0x3E24, 0x0698, 0x0BD4, 0x3F5C, 0x3FB0, 0x0010,</div><div class='add'>+		0x0054, 0x3E24, 0x065C, 0x0BFC, 0x3F78, 0x3FA4, 0x0014,</div><div class='add'>+		0x0054, 0x3E28, 0x0624, 0x0C1C, 0x3F98, 0x3F98, 0x0014,</div><div class='add'>+		0x0058, 0x3E2C, 0x05E4, 0x0C3C, 0x3FB8, 0x3F8C, 0x0018,</div><div class='add'>+		0x0058, 0x3E34, 0x05A8, 0x0C58, 0x3FD8, 0x3F80, 0x001C,</div><div class='add'>+		0x0058, 0x3E38, 0x0570, 0x0C78, 0x3FF8, 0x3F74, 0x001C,</div><div class='add'>+		0x0058, 0x3E40, 0x0534, 0x0C94, 0x0018, 0x3F68, 0x0020,</div><div class='add'>+		0x0058, 0x3E48, 0x04F4, 0x0CAC, 0x0040, 0x3F5C, 0x0024,</div><div class='add'>+		0x0058, 0x3E50, 0x04BC, 0x0CC4, 0x0064, 0x3F50, 0x0024,</div><div class='add'>+		0x0054, 0x3E58, 0x0484, 0x0CD8, 0x008C, 0x3F44, 0x0028,</div><div class='add'>+		0x0054, 0x3E60, 0x0448, 0x0CEC, 0x00B4, 0x3F38, 0x002C,</div><div class='add'>+		0x0054, 0x3E68, 0x0410, 0x0CFC, 0x00E0, 0x3F28, 0x0030,</div><div class='add'>+		0x0054, 0x3E74, 0x03D4, 0x0D0C, 0x010C, 0x3F1C, 0x0030,</div><div class='add'>+		0x0050, 0x3E7C, 0x03A0, 0x0D18, 0x0138, 0x3F10, 0x0034,</div><div class='add'>+		0x0050, 0x3E88, 0x0364, 0x0D24, 0x0164, 0x3F04, 0x0038,</div><div class='add'>+		0x004C, 0x3E94, 0x0330, 0x0D30, 0x0194, 0x3EF4, 0x0038,</div><div class='add'>+		0x004C, 0x3EA0, 0x02F8, 0x0D34, 0x01C4, 0x3EE8, 0x003C,</div><div class='add'>+		0x0048, 0x3EAC, 0x02C0, 0x0D3C, 0x01F4, 0x3EDC, 0x0040,</div><div class='add'>+		0x0048, 0x3EB8, 0x0290, 0x0D3C, 0x0224, 0x3ED0, 0x0040,</div><div class='add'>+		0x0044, 0x3EC4, 0x0258, 0x0D40, 0x0258, 0x3EC4, 0x0044</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 7</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.49999 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_7tap_64p_149[231] = {</div><div class='add'>+		0x3F68, 0x3FEC, 0x08A8, 0x08AC, 0x3FF0, 0x3F68, 0x0000,</div><div class='add'>+		0x3F70, 0x3FDC, 0x0888, 0x08CC, 0x0000, 0x3F60, 0x0000,</div><div class='add'>+		0x3F74, 0x3FC8, 0x0868, 0x08F0, 0x0014, 0x3F58, 0x0000,</div><div class='add'>+		0x3F7C, 0x3FB4, 0x0844, 0x0908, 0x002C, 0x3F54, 0x0004,</div><div class='add'>+		0x3F84, 0x3FA4, 0x0820, 0x0924, 0x0044, 0x3F4C, 0x0004,</div><div class='add'>+		0x3F88, 0x3F90, 0x0800, 0x0944, 0x005C, 0x3F44, 0x0004,</div><div class='add'>+		0x3F90, 0x3F80, 0x07D8, 0x095C, 0x0074, 0x3F40, 0x0008,</div><div class='add'>+		0x3F98, 0x3F70, 0x07B0, 0x097C, 0x008C, 0x3F38, 0x0008,</div><div class='add'>+		0x3F9C, 0x3F60, 0x0790, 0x0994, 0x00A8, 0x3F30, 0x0008,</div><div class='add'>+		0x3FA4, 0x3F54, 0x0764, 0x09B0, 0x00C4, 0x3F28, 0x0008,</div><div class='add'>+		0x3FA8, 0x3F48, 0x0740, 0x09C4, 0x00DC, 0x3F24, 0x000C,</div><div class='add'>+		0x3FB0, 0x3F38, 0x0718, 0x09DC, 0x00FC, 0x3F1C, 0x000C,</div><div class='add'>+		0x3FB4, 0x3F2C, 0x06F0, 0x09F4, 0x0118, 0x3F18, 0x000C,</div><div class='add'>+		0x3FBC, 0x3F24, 0x06C8, 0x0A08, 0x0134, 0x3F10, 0x000C,</div><div class='add'>+		0x3FC0, 0x3F18, 0x06A0, 0x0A1C, 0x0154, 0x3F08, 0x0010,</div><div class='add'>+		0x3FC8, 0x3F10, 0x0678, 0x0A2C, 0x0170, 0x3F04, 0x0010,</div><div class='add'>+		0x3FCC, 0x3F04, 0x0650, 0x0A40, 0x0190, 0x3F00, 0x0010,</div><div class='add'>+		0x3FD0, 0x3EFC, 0x0628, 0x0A54, 0x01B0, 0x3EF8, 0x0010,</div><div class='add'>+		0x3FD4, 0x3EF4, 0x0600, 0x0A64, 0x01D0, 0x3EF4, 0x0010,</div><div class='add'>+		0x3FDC, 0x3EEC, 0x05D8, 0x0A6C, 0x01F4, 0x3EF0, 0x0010,</div><div class='add'>+		0x3FE0, 0x3EE8, 0x05B0, 0x0A7C, 0x0214, 0x3EE8, 0x0010,</div><div class='add'>+		0x3FE4, 0x3EE0, 0x0588, 0x0A88, 0x0238, 0x3EE4, 0x0010,</div><div class='add'>+		0x3FE8, 0x3EDC, 0x055C, 0x0A98, 0x0258, 0x3EE0, 0x0010,</div><div class='add'>+		0x3FEC, 0x3ED8, 0x0534, 0x0AA0, 0x027C, 0x3EDC, 0x0010,</div><div class='add'>+		0x3FF0, 0x3ED4, 0x050C, 0x0AAC, 0x02A0, 0x3ED8, 0x000C,</div><div class='add'>+		0x3FF4, 0x3ED0, 0x04E4, 0x0AB4, 0x02C4, 0x3ED4, 0x000C,</div><div class='add'>+		0x3FF4, 0x3ECC, 0x04C0, 0x0ABC, 0x02E8, 0x3ED0, 0x000C,</div><div class='add'>+		0x3FF8, 0x3ECC, 0x0494, 0x0AC0, 0x030C, 0x3ED0, 0x000C,</div><div class='add'>+		0x3FFC, 0x3EC8, 0x046C, 0x0AC8, 0x0334, 0x3ECC, 0x0008,</div><div class='add'>+		0x0000, 0x3EC8, 0x0444, 0x0AC8, 0x0358, 0x3ECC, 0x0008,</div><div class='add'>+		0x0000, 0x3EC8, 0x041C, 0x0ACC, 0x0380, 0x3EC8, 0x0008,</div><div class='add'>+		0x0000, 0x3EC8, 0x03F4, 0x0AD0, 0x03A8, 0x3EC8, 0x0004,</div><div class='add'>+		0x0004, 0x3EC8, 0x03CC, 0x0AD0, 0x03CC, 0x3EC8, 0x0004</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 7</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.83332 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_7tap_64p_183[231] = {</div><div class='add'>+		0x3FA4, 0x01E8, 0x0674, 0x0674, 0x01E8, 0x3FA4, 0x0000,</div><div class='add'>+		0x3FA4, 0x01D4, 0x0668, 0x0684, 0x01F8, 0x3FA4, 0x0000,</div><div class='add'>+		0x3FA4, 0x01C4, 0x0658, 0x0690, 0x0208, 0x3FA8, 0x0000,</div><div class='add'>+		0x3FA0, 0x01B4, 0x064C, 0x06A0, 0x021C, 0x3FA8, 0x3FFC,</div><div class='add'>+		0x3FA0, 0x01A4, 0x063C, 0x06AC, 0x022C, 0x3FAC, 0x3FFC,</div><div class='add'>+		0x3FA0, 0x0194, 0x0630, 0x06B4, 0x0240, 0x3FAC, 0x3FFC,</div><div class='add'>+		0x3FA0, 0x0184, 0x0620, 0x06C4, 0x0250, 0x3FB0, 0x3FF8,</div><div class='add'>+		0x3FA0, 0x0174, 0x0614, 0x06CC, 0x0264, 0x3FB0, 0x3FF8,</div><div class='add'>+		0x3FA0, 0x0164, 0x0604, 0x06D8, 0x0278, 0x3FB4, 0x3FF4,</div><div class='add'>+		0x3FA0, 0x0154, 0x05F4, 0x06E4, 0x0288, 0x3FB8, 0x3FF4,</div><div class='add'>+		0x3FA0, 0x0148, 0x05E4, 0x06EC, 0x029C, 0x3FBC, 0x3FF0,</div><div class='add'>+		0x3FA0, 0x0138, 0x05D4, 0x06F4, 0x02B0, 0x3FC0, 0x3FF0,</div><div class='add'>+		0x3FA0, 0x0128, 0x05C4, 0x0704, 0x02C4, 0x3FC0, 0x3FEC,</div><div class='add'>+		0x3FA0, 0x011C, 0x05B4, 0x0708, 0x02D8, 0x3FC4, 0x3FEC,</div><div class='add'>+		0x3FA4, 0x010C, 0x05A4, 0x0714, 0x02E8, 0x3FC8, 0x3FE8,</div><div class='add'>+		0x3FA4, 0x0100, 0x0590, 0x0718, 0x02FC, 0x3FD0, 0x3FE8,</div><div class='add'>+		0x3FA4, 0x00F0, 0x0580, 0x0724, 0x0310, 0x3FD4, 0x3FE4,</div><div class='add'>+		0x3FA4, 0x00E4, 0x056C, 0x072C, 0x0324, 0x3FD8, 0x3FE4,</div><div class='add'>+		0x3FA8, 0x00D8, 0x055C, 0x0730, 0x0338, 0x3FDC, 0x3FE0,</div><div class='add'>+		0x3FA8, 0x00CC, 0x0548, 0x0738, 0x034C, 0x3FE4, 0x3FDC,</div><div class='add'>+		0x3FA8, 0x00BC, 0x0538, 0x0740, 0x0360, 0x3FE8, 0x3FDC,</div><div class='add'>+		0x3FAC, 0x00B0, 0x0528, 0x0744, 0x0374, 0x3FEC, 0x3FD8,</div><div class='add'>+		0x3FAC, 0x00A4, 0x0514, 0x0748, 0x0388, 0x3FF4, 0x3FD8,</div><div class='add'>+		0x3FB0, 0x0098, 0x0500, 0x074C, 0x039C, 0x3FFC, 0x3FD4,</div><div class='add'>+		0x3FB0, 0x0090, 0x04EC, 0x0750, 0x03B0, 0x0000, 0x3FD4,</div><div class='add'>+		0x3FB0, 0x0084, 0x04DC, 0x0758, 0x03C4, 0x0004, 0x3FD0,</div><div class='add'>+		0x3FB4, 0x0078, 0x04CC, 0x0758, 0x03D8, 0x000C, 0x3FCC,</div><div class='add'>+		0x3FB4, 0x006C, 0x04B8, 0x075C, 0x03EC, 0x0014, 0x3FCC,</div><div class='add'>+		0x3FB8, 0x0064, 0x04A0, 0x0760, 0x0400, 0x001C, 0x3FC8,</div><div class='add'>+		0x3FB8, 0x0058, 0x0490, 0x0760, 0x0414, 0x0024, 0x3FC8,</div><div class='add'>+		0x3FBC, 0x0050, 0x047C, 0x0760, 0x0428, 0x002C, 0x3FC4,</div><div class='add'>+		0x3FBC, 0x0048, 0x0464, 0x0764, 0x043C, 0x0034, 0x3FC4,</div><div class='add'>+		0x3FC0, 0x003C, 0x0454, 0x0764, 0x0450, 0x003C, 0x3FC0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 8</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 0.83333 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_8tap_64p_upscale[264] = {</div><div class='add'>+		0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000,</div><div class='add'>+		0x3FFC, 0x0014, 0x3FC8, 0x1000, 0x0038, 0x3FEC, 0x0004, 0x0000,</div><div class='add'>+		0x3FF4, 0x0024, 0x3F94, 0x0FFC, 0x0074, 0x3FD8, 0x000C, 0x0000,</div><div class='add'>+		0x3FF0, 0x0038, 0x3F60, 0x0FEC, 0x00B4, 0x3FC4, 0x0014, 0x0000,</div><div class='add'>+		0x3FEC, 0x004C, 0x3F2C, 0x0FE4, 0x00F4, 0x3FAC, 0x0018, 0x0000,</div><div class='add'>+		0x3FE4, 0x005C, 0x3F00, 0x0FD4, 0x0138, 0x3F94, 0x0020, 0x0000,</div><div class='add'>+		0x3FE0, 0x006C, 0x3ED0, 0x0FC4, 0x017C, 0x3F7C, 0x0028, 0x0000,</div><div class='add'>+		0x3FDC, 0x007C, 0x3EA8, 0x0FA4, 0x01C4, 0x3F68, 0x0030, 0x0000,</div><div class='add'>+		0x3FD8, 0x0088, 0x3E80, 0x0F90, 0x020C, 0x3F50, 0x0038, 0x3FFC,</div><div class='add'>+		0x3FD4, 0x0098, 0x3E58, 0x0F70, 0x0258, 0x3F38, 0x0040, 0x3FFC,</div><div class='add'>+		0x3FD0, 0x00A4, 0x3E34, 0x0F54, 0x02A0, 0x3F1C, 0x004C, 0x3FFC,</div><div class='add'>+		0x3FD0, 0x00B0, 0x3E14, 0x0F28, 0x02F0, 0x3F04, 0x0054, 0x3FFC,</div><div class='add'>+		0x3FCC, 0x00BC, 0x3DF4, 0x0F08, 0x033C, 0x3EEC, 0x005C, 0x3FF8,</div><div class='add'>+		0x3FC8, 0x00C8, 0x3DD8, 0x0EDC, 0x038C, 0x3ED4, 0x0064, 0x3FF8,</div><div class='add'>+		0x3FC8, 0x00D0, 0x3DC0, 0x0EAC, 0x03E0, 0x3EBC, 0x006C, 0x3FF4,</div><div class='add'>+		0x3FC4, 0x00D8, 0x3DA8, 0x0E7C, 0x0430, 0x3EA4, 0x0078, 0x3FF4,</div><div class='add'>+		0x3FC4, 0x00E0, 0x3D94, 0x0E48, 0x0484, 0x3E8C, 0x0080, 0x3FF0,</div><div class='add'>+		0x3FC4, 0x00E8, 0x3D80, 0x0E10, 0x04D8, 0x3E74, 0x0088, 0x3FF0,</div><div class='add'>+		0x3FC4, 0x00F0, 0x3D70, 0x0DD8, 0x052C, 0x3E5C, 0x0090, 0x3FEC,</div><div class='add'>+		0x3FC0, 0x00F4, 0x3D60, 0x0DA0, 0x0584, 0x3E44, 0x0098, 0x3FEC,</div><div class='add'>+		0x3FC0, 0x00F8, 0x3D54, 0x0D68, 0x05D8, 0x3E2C, 0x00A0, 0x3FE8,</div><div class='add'>+		0x3FC0, 0x00FC, 0x3D48, 0x0D20, 0x0630, 0x3E18, 0x00AC, 0x3FE8,</div><div class='add'>+		0x3FC0, 0x0100, 0x3D40, 0x0CE0, 0x0688, 0x3E00, 0x00B4, 0x3FE4,</div><div class='add'>+		0x3FC4, 0x0100, 0x3D3C, 0x0C98, 0x06DC, 0x3DEC, 0x00BC, 0x3FE4,</div><div class='add'>+		0x3FC4, 0x0100, 0x3D38, 0x0C58, 0x0734, 0x3DD8, 0x00C0, 0x3FE0,</div><div class='add'>+		0x3FC4, 0x0104, 0x3D38, 0x0C0C, 0x078C, 0x3DC4, 0x00C8, 0x3FDC,</div><div class='add'>+		0x3FC4, 0x0100, 0x3D38, 0x0BC4, 0x07E4, 0x3DB0, 0x00D0, 0x3FDC,</div><div class='add'>+		0x3FC4, 0x0100, 0x3D38, 0x0B78, 0x083C, 0x3DA0, 0x00D8, 0x3FD8,</div><div class='add'>+		0x3FC8, 0x0100, 0x3D3C, 0x0B28, 0x0890, 0x3D90, 0x00DC, 0x3FD8,</div><div class='add'>+		0x3FC8, 0x00FC, 0x3D40, 0x0ADC, 0x08E8, 0x3D80, 0x00E4, 0x3FD4,</div><div class='add'>+		0x3FCC, 0x00FC, 0x3D48, 0x0A84, 0x093C, 0x3D74, 0x00E8, 0x3FD4,</div><div class='add'>+		0x3FCC, 0x00F8, 0x3D50, 0x0A38, 0x0990, 0x3D64, 0x00F0, 0x3FD0,</div><div class='add'>+		0x3FD0, 0x00F4, 0x3D58, 0x09E0, 0x09E4, 0x3D5C, 0x00F4, 0x3FD0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 8</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.16666 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_8tap_64p_116[264] = {</div><div class='add'>+		0x0080, 0x3E90, 0x0268, 0x0D14, 0x0264, 0x3E90, 0x0080, 0x0000,</div><div class='add'>+		0x007C, 0x3E9C, 0x0238, 0x0D14, 0x0298, 0x3E84, 0x0080, 0x0000,</div><div class='add'>+		0x0078, 0x3EAC, 0x0200, 0x0D10, 0x02D0, 0x3E78, 0x0084, 0x0000,</div><div class='add'>+		0x0078, 0x3EB8, 0x01D0, 0x0D0C, 0x0304, 0x3E6C, 0x0084, 0x0000,</div><div class='add'>+		0x0074, 0x3EC8, 0x01A0, 0x0D00, 0x033C, 0x3E60, 0x0088, 0x0000,</div><div class='add'>+		0x0070, 0x3ED4, 0x0170, 0x0D00, 0x0374, 0x3E54, 0x0088, 0x3FFC,</div><div class='add'>+		0x006C, 0x3EE4, 0x0140, 0x0CF8, 0x03AC, 0x3E48, 0x0088, 0x3FFC,</div><div class='add'>+		0x006C, 0x3EF0, 0x0114, 0x0CE8, 0x03E4, 0x3E3C, 0x008C, 0x3FFC,</div><div class='add'>+		0x0068, 0x3F00, 0x00E8, 0x0CD8, 0x041C, 0x3E34, 0x008C, 0x3FFC,</div><div class='add'>+		0x0064, 0x3F10, 0x00BC, 0x0CCC, 0x0454, 0x3E28, 0x008C, 0x3FFC,</div><div class='add'>+		0x0060, 0x3F1C, 0x0090, 0x0CBC, 0x0490, 0x3E20, 0x008C, 0x3FFC,</div><div class='add'>+		0x005C, 0x3F2C, 0x0068, 0x0CA4, 0x04CC, 0x3E18, 0x008C, 0x3FFC,</div><div class='add'>+		0x0058, 0x3F38, 0x0040, 0x0C94, 0x0504, 0x3E10, 0x008C, 0x3FFC,</div><div class='add'>+		0x0054, 0x3F48, 0x001C, 0x0C7C, 0x0540, 0x3E08, 0x0088, 0x3FFC,</div><div class='add'>+		0x0050, 0x3F54, 0x3FF8, 0x0C60, 0x057C, 0x3E04, 0x0088, 0x3FFC,</div><div class='add'>+		0x004C, 0x3F64, 0x3FD4, 0x0C44, 0x05B8, 0x3DFC, 0x0088, 0x3FFC,</div><div class='add'>+		0x0048, 0x3F70, 0x3FB4, 0x0C28, 0x05F4, 0x3DF8, 0x0084, 0x3FFC,</div><div class='add'>+		0x0044, 0x3F80, 0x3F90, 0x0C0C, 0x0630, 0x3DF4, 0x0080, 0x3FFC,</div><div class='add'>+		0x0040, 0x3F8C, 0x3F70, 0x0BE8, 0x066C, 0x3DF4, 0x0080, 0x3FFC,</div><div class='add'>+		0x003C, 0x3F9C, 0x3F50, 0x0BC8, 0x06A8, 0x3DF0, 0x007C, 0x3FFC,</div><div class='add'>+		0x0038, 0x3FA8, 0x3F34, 0x0BA0, 0x06E4, 0x3DF0, 0x0078, 0x0000,</div><div class='add'>+		0x0034, 0x3FB4, 0x3F18, 0x0B80, 0x071C, 0x3DF0, 0x0074, 0x0000,</div><div class='add'>+		0x0030, 0x3FC0, 0x3EFC, 0x0B5C, 0x0758, 0x3DF0, 0x0070, 0x0000,</div><div class='add'>+		0x002C, 0x3FCC, 0x3EE4, 0x0B34, 0x0794, 0x3DF4, 0x0068, 0x0000,</div><div class='add'>+		0x002C, 0x3FDC, 0x3ECC, 0x0B08, 0x07CC, 0x3DF4, 0x0064, 0x0000,</div><div class='add'>+		0x0028, 0x3FE4, 0x3EB4, 0x0AE0, 0x0808, 0x3DF8, 0x0060, 0x0000,</div><div class='add'>+		0x0024, 0x3FF0, 0x3EA0, 0x0AB0, 0x0840, 0x3E00, 0x0058, 0x0004,</div><div class='add'>+		0x0020, 0x3FFC, 0x3E90, 0x0A84, 0x0878, 0x3E04, 0x0050, 0x0004,</div><div class='add'>+		0x001C, 0x0004, 0x3E7C, 0x0A54, 0x08B0, 0x3E0C, 0x004C, 0x0008,</div><div class='add'>+		0x0018, 0x000C, 0x3E68, 0x0A28, 0x08E8, 0x3E18, 0x0044, 0x0008,</div><div class='add'>+		0x0018, 0x0018, 0x3E54, 0x09F4, 0x0920, 0x3E20, 0x003C, 0x000C,</div><div class='add'>+		0x0014, 0x0020, 0x3E48, 0x09C0, 0x0954, 0x3E2C, 0x0034, 0x0010,</div><div class='add'>+		0x0010, 0x002C, 0x3E3C, 0x098C, 0x0988, 0x3E38, 0x002C, 0x0010</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 8</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.49999 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_8tap_64p_149[264] = {</div><div class='add'>+		0x0008, 0x3E8C, 0x03F8, 0x0AE8, 0x03F8, 0x3E8C, 0x0008, 0x0000,</div><div class='add'>+		0x000C, 0x3E8C, 0x03D0, 0x0AE8, 0x0420, 0x3E90, 0x0000, 0x0000,</div><div class='add'>+		0x000C, 0x3E8C, 0x03AC, 0x0AE8, 0x0444, 0x3E90, 0x0000, 0x0000,</div><div class='add'>+		0x0010, 0x3E90, 0x0384, 0x0AE0, 0x046C, 0x3E94, 0x3FFC, 0x0000,</div><div class='add'>+		0x0014, 0x3E90, 0x035C, 0x0ADC, 0x0494, 0x3E94, 0x3FF8, 0x0004,</div><div class='add'>+		0x0018, 0x3E90, 0x0334, 0x0AD8, 0x04BC, 0x3E98, 0x3FF4, 0x0004,</div><div class='add'>+		0x001C, 0x3E94, 0x0310, 0x0AD0, 0x04E4, 0x3E9C, 0x3FEC, 0x0004,</div><div class='add'>+		0x0020, 0x3E98, 0x02E8, 0x0AC4, 0x050C, 0x3EA0, 0x3FE8, 0x0008,</div><div class='add'>+		0x0020, 0x3E98, 0x02C4, 0x0AC0, 0x0534, 0x3EA4, 0x3FE4, 0x0008,</div><div class='add'>+		0x0024, 0x3E9C, 0x02A0, 0x0AB4, 0x055C, 0x3EAC, 0x3FDC, 0x0008,</div><div class='add'>+		0x0024, 0x3EA0, 0x027C, 0x0AA8, 0x0584, 0x3EB0, 0x3FD8, 0x000C,</div><div class='add'>+		0x0028, 0x3EA4, 0x0258, 0x0A9C, 0x05AC, 0x3EB8, 0x3FD0, 0x000C,</div><div class='add'>+		0x0028, 0x3EA8, 0x0234, 0x0A90, 0x05D4, 0x3EC0, 0x3FC8, 0x0010,</div><div class='add'>+		0x002C, 0x3EAC, 0x0210, 0x0A80, 0x05FC, 0x3EC8, 0x3FC4, 0x0010,</div><div class='add'>+		0x002C, 0x3EB4, 0x01F0, 0x0A70, 0x0624, 0x3ED0, 0x3FBC, 0x0010,</div><div class='add'>+		0x002C, 0x3EB8, 0x01CC, 0x0A60, 0x064C, 0x3EDC, 0x3FB4, 0x0014,</div><div class='add'>+		0x0030, 0x3EBC, 0x01A8, 0x0A50, 0x0674, 0x3EE4, 0x3FB0, 0x0014,</div><div class='add'>+		0x0030, 0x3EC4, 0x0188, 0x0A38, 0x069C, 0x3EF0, 0x3FA8, 0x0018,</div><div class='add'>+		0x0030, 0x3ECC, 0x0168, 0x0A28, 0x06C0, 0x3EFC, 0x3FA0, 0x0018,</div><div class='add'>+		0x0030, 0x3ED0, 0x0148, 0x0A14, 0x06E8, 0x3F08, 0x3F98, 0x001C,</div><div class='add'>+		0x0030, 0x3ED8, 0x012C, 0x0A00, 0x070C, 0x3F14, 0x3F90, 0x001C,</div><div class='add'>+		0x0034, 0x3EE0, 0x0108, 0x09E4, 0x0734, 0x3F24, 0x3F8C, 0x001C,</div><div class='add'>+		0x0034, 0x3EE4, 0x00EC, 0x09CC, 0x0758, 0x3F34, 0x3F84, 0x0020,</div><div class='add'>+		0x0034, 0x3EEC, 0x00D0, 0x09B8, 0x077C, 0x3F40, 0x3F7C, 0x0020,</div><div class='add'>+		0x0034, 0x3EF4, 0x00B4, 0x0998, 0x07A4, 0x3F50, 0x3F74, 0x0024,</div><div class='add'>+		0x0030, 0x3EFC, 0x0098, 0x0980, 0x07C8, 0x3F64, 0x3F6C, 0x0024,</div><div class='add'>+		0x0030, 0x3F04, 0x0080, 0x0968, 0x07E8, 0x3F74, 0x3F64, 0x0024,</div><div class='add'>+		0x0030, 0x3F0C, 0x0060, 0x094C, 0x080C, 0x3F88, 0x3F5C, 0x0028,</div><div class='add'>+		0x0030, 0x3F14, 0x0048, 0x0930, 0x0830, 0x3F98, 0x3F54, 0x0028,</div><div class='add'>+		0x0030, 0x3F1C, 0x0030, 0x0914, 0x0850, 0x3FAC, 0x3F4C, 0x0028,</div><div class='add'>+		0x0030, 0x3F24, 0x0018, 0x08F0, 0x0874, 0x3FC0, 0x3F44, 0x002C,</div><div class='add'>+		0x002C, 0x3F2C, 0x0000, 0x08D4, 0x0894, 0x3FD8, 0x3F3C, 0x002C,</div><div class='add'>+		0x002C, 0x3F34, 0x3FEC, 0x08B4, 0x08B4, 0x3FEC, 0x3F34, 0x002C</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+//=========================================</div><div class='add'>+// &lt;num_taps&gt;    = 8</div><div class='add'>+// &lt;num_phases&gt;  = 64</div><div class='add'>+// &lt;scale_ratio&gt; = 1.83332 (input/output)</div><div class='add'>+// &lt;sharpness&gt;   = 0</div><div class='add'>+// &lt;CoefType&gt;    = ModifiedLanczos</div><div class='add'>+// &lt;CoefQuant&gt;   = 1.10</div><div class='add'>+// &lt;CoefOut&gt;     = 1.12</div><div class='add'>+//=========================================</div><div class='add'>+static const uint16_t filter_8tap_64p_183[264] = {</div><div class='add'>+		0x3F88, 0x0048, 0x047C, 0x0768, 0x047C, 0x0048, 0x3F88, 0x0000,</div><div class='add'>+		0x3F88, 0x003C, 0x0468, 0x076C, 0x0490, 0x0054, 0x3F84, 0x0000,</div><div class='add'>+		0x3F8C, 0x0034, 0x0454, 0x0768, 0x04A4, 0x005C, 0x3F84, 0x0000,</div><div class='add'>+		0x3F8C, 0x0028, 0x0444, 0x076C, 0x04B4, 0x0068, 0x3F80, 0x0000,</div><div class='add'>+		0x3F90, 0x0020, 0x042C, 0x0768, 0x04C8, 0x0074, 0x3F80, 0x0000,</div><div class='add'>+		0x3F90, 0x0018, 0x041C, 0x0764, 0x04DC, 0x0080, 0x3F7C, 0x0000,</div><div class='add'>+		0x3F94, 0x0010, 0x0408, 0x075C, 0x04F0, 0x008C, 0x3F7C, 0x0000,</div><div class='add'>+		0x3F94, 0x0004, 0x03F8, 0x0760, 0x0500, 0x0098, 0x3F7C, 0x3FFC,</div><div class='add'>+		0x3F98, 0x0000, 0x03E0, 0x075C, 0x0514, 0x00A4, 0x3F78, 0x3FFC,</div><div class='add'>+		0x3F9C, 0x3FF8, 0x03CC, 0x0754, 0x0528, 0x00B0, 0x3F78, 0x3FFC,</div><div class='add'>+		0x3F9C, 0x3FF0, 0x03B8, 0x0754, 0x0538, 0x00BC, 0x3F78, 0x3FFC,</div><div class='add'>+		0x3FA0, 0x3FE8, 0x03A4, 0x0750, 0x054C, 0x00CC, 0x3F74, 0x3FF8,</div><div class='add'>+		0x3FA4, 0x3FE0, 0x0390, 0x074C, 0x055C, 0x00D8, 0x3F74, 0x3FF8,</div><div class='add'>+		0x3FA4, 0x3FDC, 0x037C, 0x0744, 0x0570, 0x00E4, 0x3F74, 0x3FF8,</div><div class='add'>+		0x3FA8, 0x3FD4, 0x0368, 0x0740, 0x0580, 0x00F4, 0x3F74, 0x3FF4,</div><div class='add'>+		0x3FA8, 0x3FCC, 0x0354, 0x073C, 0x0590, 0x0104, 0x3F74, 0x3FF4,</div><div class='add'>+		0x3FAC, 0x3FC8, 0x0340, 0x0730, 0x05A4, 0x0110, 0x3F74, 0x3FF4,</div><div class='add'>+		0x3FB0, 0x3FC0, 0x0330, 0x0728, 0x05B4, 0x0120, 0x3F74, 0x3FF0,</div><div class='add'>+		0x3FB0, 0x3FBC, 0x031C, 0x0724, 0x05C4, 0x0130, 0x3F70, 0x3FF0,</div><div class='add'>+		0x3FB4, 0x3FB4, 0x0308, 0x0720, 0x05D4, 0x013C, 0x3F70, 0x3FF0,</div><div class='add'>+		0x3FB8, 0x3FB0, 0x02F4, 0x0714, 0x05E4, 0x014C, 0x3F74, 0x3FEC,</div><div class='add'>+		0x3FB8, 0x3FAC, 0x02E0, 0x0708, 0x05F8, 0x015C, 0x3F74, 0x3FEC,</div><div class='add'>+		0x3FBC, 0x3FA8, 0x02CC, 0x0704, 0x0604, 0x016C, 0x3F74, 0x3FE8,</div><div class='add'>+		0x3FC0, 0x3FA0, 0x02BC, 0x06F8, 0x0614, 0x017C, 0x3F74, 0x3FE8,</div><div class='add'>+		0x3FC0, 0x3F9C, 0x02A8, 0x06F4, 0x0624, 0x018C, 0x3F74, 0x3FE4,</div><div class='add'>+		0x3FC4, 0x3F98, 0x0294, 0x06E8, 0x0634, 0x019C, 0x3F74, 0x3FE4,</div><div class='add'>+		0x3FC8, 0x3F94, 0x0284, 0x06D8, 0x0644, 0x01AC, 0x3F78, 0x3FE0,</div><div class='add'>+		0x3FC8, 0x3F90, 0x0270, 0x06D4, 0x0650, 0x01BC, 0x3F78, 0x3FE0,</div><div class='add'>+		0x3FCC, 0x3F8C, 0x025C, 0x06C8, 0x0660, 0x01D0, 0x3F78, 0x3FDC,</div><div class='add'>+		0x3FCC, 0x3F8C, 0x024C, 0x06B8, 0x066C, 0x01E0, 0x3F7C, 0x3FDC,</div><div class='add'>+		0x3FD0, 0x3F88, 0x0238, 0x06B0, 0x067C, 0x01F0, 0x3F7C, 0x3FD8,</div><div class='add'>+		0x3FD4, 0x3F84, 0x0228, 0x069C, 0x0688, 0x0204, 0x3F80, 0x3FD8,</div><div class='add'>+		0x3FD4, 0x3F84, 0x0214, 0x0694, 0x0694, 0x0214, 0x3F84, 0x3FD4</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_3tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_one.value)</div><div class='add'>+		return filter_3tap_64p_upscale;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 3).value)</div><div class='add'>+		return filter_3tap_64p_116;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 3).value)</div><div class='add'>+		return filter_3tap_64p_149;</div><div class='add'>+	else</div><div class='add'>+		return filter_3tap_64p_183;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_4tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_one.value)</div><div class='add'>+		return filter_4tap_64p_upscale;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 3).value)</div><div class='add'>+		return filter_4tap_64p_116;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 3).value)</div><div class='add'>+		return filter_4tap_64p_149;</div><div class='add'>+	else</div><div class='add'>+		return filter_4tap_64p_183;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_5tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_one.value)</div><div class='add'>+		return filter_5tap_64p_upscale;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 3).value)</div><div class='add'>+		return filter_5tap_64p_116;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 3).value)</div><div class='add'>+		return filter_5tap_64p_149;</div><div class='add'>+	else</div><div class='add'>+		return filter_5tap_64p_183;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_6tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_one.value)</div><div class='add'>+		return filter_6tap_64p_upscale;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 3).value)</div><div class='add'>+		return filter_6tap_64p_116;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 3).value)</div><div class='add'>+		return filter_6tap_64p_149;</div><div class='add'>+	else</div><div class='add'>+		return filter_6tap_64p_183;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_7tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_one.value)</div><div class='add'>+		return filter_7tap_64p_upscale;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 3).value)</div><div class='add'>+		return filter_7tap_64p_116;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 3).value)</div><div class='add'>+		return filter_7tap_64p_149;</div><div class='add'>+	else</div><div class='add'>+		return filter_7tap_64p_183;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_8tap_64p(struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (ratio.value &lt; spl_fixpt_one.value)</div><div class='add'>+		return filter_8tap_64p_upscale;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(4, 3).value)</div><div class='add'>+		return filter_8tap_64p_116;</div><div class='add'>+	else if (ratio.value &lt; spl_fixpt_from_fraction(5, 3).value)</div><div class='add'>+		return filter_8tap_64p_149;</div><div class='add'>+	else</div><div class='add'>+		return filter_8tap_64p_183;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const uint16_t *spl_get_filter_2tap_64p(void)</div><div class='add'>+{</div><div class='add'>+	return filter_2tap_64p;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio)</div><div class='add'>+{</div><div class='add'>+	if (taps == 8)</div><div class='add'>+		return spl_get_filter_8tap_64p(ratio);</div><div class='add'>+	else if (taps == 7)</div><div class='add'>+		return spl_get_filter_7tap_64p(ratio);</div><div class='add'>+	else if (taps == 6)</div><div class='add'>+		return spl_get_filter_6tap_64p(ratio);</div><div class='add'>+	else if (taps == 5)</div><div class='add'>+		return spl_get_filter_5tap_64p(ratio);</div><div class='add'>+	else if (taps == 4)</div><div class='add'>+		return spl_get_filter_4tap_64p(ratio);</div><div class='add'>+	else if (taps == 3)</div><div class='add'>+		return spl_get_filter_3tap_64p(ratio);</div><div class='add'>+	else if (taps == 2)</div><div class='add'>+		return spl_get_filter_2tap_64p();</div><div class='add'>+	else if (taps == 1)</div><div class='add'>+		return NULL;</div><div class='add'>+	else {</div><div class='add'>+		/* should never happen, bug */</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h<br/>new file mode 100644<br/>index 000000000000..c315a438d064<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_SCL_FILTERS_H__</div><div class='add'>+#define __DC_SPL_SCL_FILTERS_H__</div><div class='add'>+</div><div class='add'>+#include "dc_spl_types.h"</div><div class='add'>+</div><div class='add'>+/* public API */</div><div class='add'>+const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_SCL_FILTERS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h<br/>new file mode 100644<br/>index 000000000000..20e4e52a77ac<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h</a></div><div class='hunk'>@@ -0,0 +1,560 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef __DC_SPL_TYPES_H__</div><div class='add'>+#define __DC_SPL_TYPES_H__</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+#include "spl_os_types.h"   // swap</div><div class='add'>+#include "spl_fixpt31_32.h"	// fixed31_32 and related functions</div><div class='add'>+#include "spl_custom_float.h" // custom float and related functions</div><div class='add'>+</div><div class='add'>+struct spl_size {</div><div class='add'>+	uint32_t width;</div><div class='add'>+	uint32_t height;</div><div class='add'>+};</div><div class='add'>+struct spl_rect	{</div><div class='add'>+	int x;</div><div class='add'>+	int y;</div><div class='add'>+	int width;</div><div class='add'>+	int height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct spl_ratios {</div><div class='add'>+	struct spl_fixed31_32 horz;</div><div class='add'>+	struct spl_fixed31_32 vert;</div><div class='add'>+	struct spl_fixed31_32 horz_c;</div><div class='add'>+	struct spl_fixed31_32 vert_c;</div><div class='add'>+};</div><div class='add'>+struct spl_inits {</div><div class='add'>+	struct spl_fixed31_32 h;</div><div class='add'>+	struct spl_fixed31_32 h_c;</div><div class='add'>+	struct spl_fixed31_32 v;</div><div class='add'>+	struct spl_fixed31_32 v_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct spl_taps	{</div><div class='add'>+	uint32_t v_taps;</div><div class='add'>+	uint32_t h_taps;</div><div class='add'>+	uint32_t v_taps_c;</div><div class='add'>+	uint32_t h_taps_c;</div><div class='add'>+	bool integer_scaling;</div><div class='add'>+};</div><div class='add'>+enum spl_view_3d {</div><div class='add'>+	SPL_VIEW_3D_NONE = 0,</div><div class='add'>+	SPL_VIEW_3D_FRAME_SEQUENTIAL,</div><div class='add'>+	SPL_VIEW_3D_SIDE_BY_SIDE,</div><div class='add'>+	SPL_VIEW_3D_TOP_AND_BOTTOM,</div><div class='add'>+	SPL_VIEW_3D_COUNT,</div><div class='add'>+	SPL_VIEW_3D_FIRST = SPL_VIEW_3D_FRAME_SEQUENTIAL</div><div class='add'>+};</div><div class='add'>+/* Pixel format */</div><div class='add'>+enum spl_pixel_format {</div><div class='add'>+	/*graph*/</div><div class='add'>+	SPL_PIXEL_FORMAT_UNINITIALIZED,</div><div class='add'>+	SPL_PIXEL_FORMAT_INDEX8,</div><div class='add'>+	SPL_PIXEL_FORMAT_RGB565,</div><div class='add'>+	SPL_PIXEL_FORMAT_ARGB8888,</div><div class='add'>+	SPL_PIXEL_FORMAT_ARGB2101010,</div><div class='add'>+	SPL_PIXEL_FORMAT_ARGB2101010_XRBIAS,</div><div class='add'>+	SPL_PIXEL_FORMAT_FP16,</div><div class='add'>+	/*video*/</div><div class='add'>+	SPL_PIXEL_FORMAT_420BPP8,</div><div class='add'>+	SPL_PIXEL_FORMAT_420BPP10,</div><div class='add'>+	/*end of pixel format definition*/</div><div class='add'>+	SPL_PIXEL_FORMAT_GRPH_BEGIN = SPL_PIXEL_FORMAT_INDEX8,</div><div class='add'>+	SPL_PIXEL_FORMAT_GRPH_END = SPL_PIXEL_FORMAT_FP16,</div><div class='add'>+	SPL_PIXEL_FORMAT_SUBSAMPLED_BEGIN = SPL_PIXEL_FORMAT_420BPP8,</div><div class='add'>+	SPL_PIXEL_FORMAT_SUBSAMPLED_END = SPL_PIXEL_FORMAT_420BPP10,</div><div class='add'>+	SPL_PIXEL_FORMAT_VIDEO_BEGIN = SPL_PIXEL_FORMAT_420BPP8,</div><div class='add'>+	SPL_PIXEL_FORMAT_VIDEO_END = SPL_PIXEL_FORMAT_420BPP10,</div><div class='add'>+	SPL_PIXEL_FORMAT_INVALID,</div><div class='add'>+	SPL_PIXEL_FORMAT_UNKNOWN</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum lb_memory_config {</div><div class='add'>+	/* Enable all 3 pieces of memory */</div><div class='add'>+	LB_MEMORY_CONFIG_0 = 0,</div><div class='add'>+</div><div class='add'>+	/* Enable only the first piece of memory */</div><div class='add'>+	LB_MEMORY_CONFIG_1 = 1,</div><div class='add'>+</div><div class='add'>+	/* Enable only the second piece of memory */</div><div class='add'>+	LB_MEMORY_CONFIG_2 = 2,</div><div class='add'>+</div><div class='add'>+	/* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the</div><div class='add'>+	 * last piece of chroma memory used for the luma storage</div><div class='add'>+	 */</div><div class='add'>+	LB_MEMORY_CONFIG_3 = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Rotation angle */</div><div class='add'>+enum spl_rotation_angle {</div><div class='add'>+	SPL_ROTATION_ANGLE_0 = 0,</div><div class='add'>+	SPL_ROTATION_ANGLE_90,</div><div class='add'>+	SPL_ROTATION_ANGLE_180,</div><div class='add'>+	SPL_ROTATION_ANGLE_270,</div><div class='add'>+	SPL_ROTATION_ANGLE_COUNT</div><div class='add'>+};</div><div class='add'>+enum spl_color_space {</div><div class='add'>+	SPL_COLOR_SPACE_UNKNOWN,</div><div class='add'>+	SPL_COLOR_SPACE_SRGB,</div><div class='add'>+	SPL_COLOR_SPACE_XR_RGB,</div><div class='add'>+	SPL_COLOR_SPACE_SRGB_LIMITED,</div><div class='add'>+	SPL_COLOR_SPACE_MSREF_SCRGB,</div><div class='add'>+	SPL_COLOR_SPACE_YCBCR601,</div><div class='add'>+	SPL_COLOR_SPACE_YCBCR709,</div><div class='add'>+	SPL_COLOR_SPACE_XV_YCC_709,</div><div class='add'>+	SPL_COLOR_SPACE_XV_YCC_601,</div><div class='add'>+	SPL_COLOR_SPACE_YCBCR601_LIMITED,</div><div class='add'>+	SPL_COLOR_SPACE_YCBCR709_LIMITED,</div><div class='add'>+	SPL_COLOR_SPACE_2020_RGB_FULLRANGE,</div><div class='add'>+	SPL_COLOR_SPACE_2020_RGB_LIMITEDRANGE,</div><div class='add'>+	SPL_COLOR_SPACE_2020_YCBCR,</div><div class='add'>+	SPL_COLOR_SPACE_ADOBERGB,</div><div class='add'>+	SPL_COLOR_SPACE_DCIP3,</div><div class='add'>+	SPL_COLOR_SPACE_DISPLAYNATIVE,</div><div class='add'>+	SPL_COLOR_SPACE_DOLBYVISION,</div><div class='add'>+	SPL_COLOR_SPACE_APPCTRL,</div><div class='add'>+	SPL_COLOR_SPACE_CUSTOMPOINTS,</div><div class='add'>+	SPL_COLOR_SPACE_YCBCR709_BLACK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum chroma_cositing {</div><div class='add'>+	CHROMA_COSITING_NONE,</div><div class='add'>+	CHROMA_COSITING_LEFT,</div><div class='add'>+	CHROMA_COSITING_TOPLEFT,</div><div class='add'>+	CHROMA_COSITING_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// Scratch space for calculating scaler params</div><div class='add'>+struct spl_scaler_data {</div><div class='add'>+	int h_active;</div><div class='add'>+	int v_active;</div><div class='add'>+	struct spl_taps taps;</div><div class='add'>+	struct spl_rect viewport;</div><div class='add'>+	struct spl_rect viewport_c;</div><div class='add'>+	struct spl_rect recout;</div><div class='add'>+	struct spl_ratios ratios;</div><div class='add'>+	struct spl_ratios recip_ratios;</div><div class='add'>+	struct spl_inits inits;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum spl_transfer_func_type {</div><div class='add'>+	SPL_TF_TYPE_PREDEFINED,</div><div class='add'>+	SPL_TF_TYPE_DISTRIBUTED_POINTS,</div><div class='add'>+	SPL_TF_TYPE_BYPASS,</div><div class='add'>+	SPL_TF_TYPE_HWPWL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum spl_transfer_func_predefined {</div><div class='add'>+	SPL_TRANSFER_FUNCTION_SRGB,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_BT709,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_PQ,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_LINEAR,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_UNITY,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_HLG,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_HLG12,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_GAMMA22,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_GAMMA24,</div><div class='add'>+	SPL_TRANSFER_FUNCTION_GAMMA26</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*==============================================================*/</div><div class='add'>+/* Below structs are defined to hold hw register data */</div><div class='add'>+</div><div class='add'>+// SPL output is used to set below registers</div><div class='add'>+</div><div class='add'>+// MPC_SIZE - set based on scl_data h_active and v_active</div><div class='add'>+struct mpc_size	{</div><div class='add'>+	uint32_t width;</div><div class='add'>+	uint32_t height;</div><div class='add'>+};</div><div class='add'>+// SCL_MODE - set based on scl_data.ratios and always_scale</div><div class='add'>+enum scl_mode {</div><div class='add'>+	SCL_MODE_SCALING_444_BYPASS = 0,</div><div class='add'>+	SCL_MODE_SCALING_444_RGB_ENABLE = 1,</div><div class='add'>+	SCL_MODE_SCALING_444_YCBCR_ENABLE = 2,</div><div class='add'>+	SCL_MODE_SCALING_420_YCBCR_ENABLE = 3,</div><div class='add'>+	SCL_MODE_SCALING_420_LUMA_BYPASS = 4,</div><div class='add'>+	SCL_MODE_SCALING_420_CHROMA_BYPASS = 5,</div><div class='add'>+	SCL_MODE_DSCL_BYPASS = 6</div><div class='add'>+};</div><div class='add'>+// SCL_BLACK_COLOR - set based on scl_data.format</div><div class='add'>+struct scl_black_color	{</div><div class='add'>+	uint32_t offset_rgb_y;</div><div class='add'>+	uint32_t offset_rgb_cbcr;</div><div class='add'>+};</div><div class='add'>+// RATIO - set based on scl_data.ratios</div><div class='add'>+struct ratio	{</div><div class='add'>+	uint32_t h_scale_ratio;</div><div class='add'>+	uint32_t v_scale_ratio;</div><div class='add'>+	uint32_t h_scale_ratio_c;</div><div class='add'>+	uint32_t v_scale_ratio_c;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// INIT - set based on scl_data.init</div><div class='add'>+struct init	{</div><div class='add'>+	// SCL_HORZ_FILTER_INIT</div><div class='add'>+	uint32_t h_filter_init_frac;	//	SCL_H_INIT_FRAC</div><div class='add'>+	uint32_t h_filter_init_int;	//	SCL_H_INIT_INT</div><div class='add'>+	// SCL_HORZ_FILTER_INIT_C</div><div class='add'>+	uint32_t h_filter_init_frac_c;	//	SCL_H_INIT_FRAC_C</div><div class='add'>+	uint32_t h_filter_init_int_c;	//	SCL_H_INIT_INT_C</div><div class='add'>+	// SCL_VERT_FILTER_INIT</div><div class='add'>+	uint32_t v_filter_init_frac;	//	SCL_V_INIT_FRAC</div><div class='add'>+	uint32_t v_filter_init_int;	//	SCL_V_INIT_INT</div><div class='add'>+	//	SCL_VERT_FILTER_INIT_C</div><div class='add'>+	uint32_t v_filter_init_frac_c;	//	SCL_V_INIT_FRAC_C</div><div class='add'>+	uint32_t v_filter_init_int_c;	//	SCL_V_INIT_INT_C</div><div class='add'>+	//	SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+	uint32_t v_filter_init_bot_frac;	//	SCL_V_INIT_FRAC_BOT</div><div class='add'>+	uint32_t v_filter_init_bot_int;	//	SCL_V_INIT_INT_BOT</div><div class='add'>+	//	SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+	uint32_t v_filter_init_bot_frac_c;	//	SCL_V_INIT_FRAC_BOT_C</div><div class='add'>+	uint32_t v_filter_init_bot_int_c;	//	SCL_V_INIT_INT_BOT_C</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// FILTER - calculated based on scl_data ratios and taps</div><div class='add'>+</div><div class='add'>+// iSHARP</div><div class='add'>+struct isharp_noise_det {</div><div class='add'>+	uint32_t enable;	// ISHARP_NOISEDET_EN</div><div class='add'>+	uint32_t mode;		// ISHARP_NOISEDET_MODE</div><div class='add'>+	uint32_t uthreshold;	// ISHARP_NOISEDET_UTHRE</div><div class='add'>+	uint32_t dthreshold;	// ISHARP_NOISEDET_DTHRE</div><div class='add'>+	uint32_t pwl_start_in;	// ISHARP_NOISEDET_PWL_START_IN</div><div class='add'>+	uint32_t pwl_end_in;	// ISHARP_NOISEDET_PWL_END_IN</div><div class='add'>+	uint32_t pwl_slope;	// ISHARP_NOISEDET_PWL_SLOPE</div><div class='add'>+};</div><div class='add'>+struct isharp_lba	{</div><div class='add'>+	uint32_t mode;	// ISHARP_LBA_MODE</div><div class='add'>+	uint32_t in_seg[6];</div><div class='add'>+	uint32_t base_seg[6];</div><div class='add'>+	uint32_t slope_seg[6];</div><div class='add'>+};</div><div class='add'>+struct isharp_fmt	{</div><div class='add'>+	uint32_t mode;	// ISHARP_FMT_MODE</div><div class='add'>+	uint32_t norm;	// ISHARP_FMT_NORM</div><div class='add'>+};</div><div class='add'>+struct isharp_nldelta_sclip	{</div><div class='add'>+	uint32_t enable_p;	// ISHARP_NLDELTA_SCLIP_EN_P</div><div class='add'>+	uint32_t pivot_p;	// ISHARP_NLDELTA_SCLIP_PIVOT_P</div><div class='add'>+	uint32_t slope_p;	// ISHARP_NLDELTA_SCLIP_SLOPE_P</div><div class='add'>+	uint32_t enable_n;	// ISHARP_NLDELTA_SCLIP_EN_N</div><div class='add'>+	uint32_t pivot_n;	// ISHARP_NLDELTA_SCLIP_PIVOT_N</div><div class='add'>+	uint32_t slope_n;	// ISHARP_NLDELTA_SCLIP_SLOPE_N</div><div class='add'>+};</div><div class='add'>+enum isharp_en	{</div><div class='add'>+	ISHARP_DISABLE,</div><div class='add'>+	ISHARP_ENABLE</div><div class='add'>+};</div><div class='add'>+#define ISHARP_LUT_TABLE_SIZE 32</div><div class='add'>+// Below struct holds values that can be directly used to program</div><div class='add'>+// hardware registers. No conversion/clamping is required</div><div class='add'>+struct dscl_prog_data {</div><div class='add'>+	struct spl_rect recout; // RECOUT - set based on scl_data.recout</div><div class='add'>+	struct mpc_size mpc_size;</div><div class='add'>+	uint32_t dscl_mode;</div><div class='add'>+	struct scl_black_color scl_black_color;</div><div class='add'>+	struct ratio ratios;</div><div class='add'>+	struct init init;</div><div class='add'>+	struct spl_taps taps;	// TAPS - set based on scl_data.taps</div><div class='add'>+	struct spl_rect viewport;</div><div class='add'>+	struct spl_rect viewport_c;</div><div class='add'>+	// raw filter</div><div class='add'>+	const uint16_t *filter_h;</div><div class='add'>+	const uint16_t *filter_v;</div><div class='add'>+	const uint16_t *filter_h_c;</div><div class='add'>+	const uint16_t *filter_v_c;</div><div class='add'>+	// EASF registers</div><div class='add'>+	uint32_t easf_matrix_mode;</div><div class='add'>+	uint32_t easf_ltonl_en;</div><div class='add'>+	uint32_t easf_v_en;</div><div class='add'>+	uint32_t easf_v_sharp_factor;</div><div class='add'>+	uint32_t easf_v_ring;</div><div class='add'>+	uint32_t easf_v_bf1_en;</div><div class='add'>+	uint32_t easf_v_bf2_mode;</div><div class='add'>+	uint32_t easf_v_bf3_mode;</div><div class='add'>+	uint32_t easf_v_bf2_flat1_gain;</div><div class='add'>+	uint32_t easf_v_bf2_flat2_gain;</div><div class='add'>+	uint32_t easf_v_bf2_roc_gain;</div><div class='add'>+	uint32_t easf_v_ringest_3tap_dntilt_uptilt;</div><div class='add'>+	uint32_t easf_v_ringest_3tap_uptilt_max;</div><div class='add'>+	uint32_t easf_v_ringest_3tap_dntilt_slope;</div><div class='add'>+	uint32_t easf_v_ringest_3tap_uptilt1_slope;</div><div class='add'>+	uint32_t easf_v_ringest_3tap_uptilt2_slope;</div><div class='add'>+	uint32_t easf_v_ringest_3tap_uptilt2_offset;</div><div class='add'>+	uint32_t easf_v_ringest_eventap_reduceg1;</div><div class='add'>+	uint32_t easf_v_ringest_eventap_reduceg2;</div><div class='add'>+	uint32_t easf_v_ringest_eventap_gain1;</div><div class='add'>+	uint32_t easf_v_ringest_eventap_gain2;</div><div class='add'>+	uint32_t easf_v_bf_maxa;</div><div class='add'>+	uint32_t easf_v_bf_maxb;</div><div class='add'>+	uint32_t easf_v_bf_mina;</div><div class='add'>+	uint32_t easf_v_bf_minb;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg0;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg0;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg0;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg1;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg1;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg1;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg2;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg2;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg2;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg3;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg3;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg3;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg4;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg4;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg4;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg5;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg5;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg5;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg6;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg6;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_slope_seg6;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_in_seg7;</div><div class='add'>+	uint32_t easf_v_bf1_pwl_base_seg7;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_in_set0;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_base_set0;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_slope_set0;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_in_set1;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_base_set1;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_slope_set1;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_in_set2;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_base_set2;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_slope_set2;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_in_set3;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_base_set3;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_slope_set3;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_in_set4;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_base_set4;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_slope_set4;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_in_set5;</div><div class='add'>+	uint32_t easf_v_bf3_pwl_base_set5;</div><div class='add'>+	uint32_t easf_h_en;</div><div class='add'>+	uint32_t easf_h_sharp_factor;</div><div class='add'>+	uint32_t easf_h_ring;</div><div class='add'>+	uint32_t easf_h_bf1_en;</div><div class='add'>+	uint32_t easf_h_bf2_mode;</div><div class='add'>+	uint32_t easf_h_bf3_mode;</div><div class='add'>+	uint32_t easf_h_bf2_flat1_gain;</div><div class='add'>+	uint32_t easf_h_bf2_flat2_gain;</div><div class='add'>+	uint32_t easf_h_bf2_roc_gain;</div><div class='add'>+	uint32_t easf_h_ringest_eventap_reduceg1;</div><div class='add'>+	uint32_t easf_h_ringest_eventap_reduceg2;</div><div class='add'>+	uint32_t easf_h_ringest_eventap_gain1;</div><div class='add'>+	uint32_t easf_h_ringest_eventap_gain2;</div><div class='add'>+	uint32_t easf_h_bf_maxa;</div><div class='add'>+	uint32_t easf_h_bf_maxb;</div><div class='add'>+	uint32_t easf_h_bf_mina;</div><div class='add'>+	uint32_t easf_h_bf_minb;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg0;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg0;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg0;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg1;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg1;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg1;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg2;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg2;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg2;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg3;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg3;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg3;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg4;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg4;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg4;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg5;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg5;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg5;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg6;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg6;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_slope_seg6;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_in_seg7;</div><div class='add'>+	uint32_t easf_h_bf1_pwl_base_seg7;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_in_set0;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_base_set0;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_slope_set0;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_in_set1;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_base_set1;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_slope_set1;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_in_set2;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_base_set2;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_slope_set2;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_in_set3;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_base_set3;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_slope_set3;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_in_set4;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_base_set4;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_slope_set4;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_in_set5;</div><div class='add'>+	uint32_t easf_h_bf3_pwl_base_set5;</div><div class='add'>+	uint32_t easf_matrix_c0;</div><div class='add'>+	uint32_t easf_matrix_c1;</div><div class='add'>+	uint32_t easf_matrix_c2;</div><div class='add'>+	uint32_t easf_matrix_c3;</div><div class='add'>+	// iSharp</div><div class='add'>+	uint32_t isharp_en;     //      ISHARP_EN</div><div class='add'>+	struct isharp_noise_det isharp_noise_det;       //      ISHARP_NOISEDET</div><div class='add'>+	uint32_t isharp_nl_en;  //      ISHARP_NL_EN ? TODO:check this</div><div class='add'>+	struct isharp_lba isharp_lba;   //      ISHARP_LBA</div><div class='add'>+	struct isharp_fmt isharp_fmt;   //      ISHARP_FMT</div><div class='add'>+	uint32_t isharp_delta[ISHARP_LUT_TABLE_SIZE];</div><div class='add'>+	struct isharp_nldelta_sclip isharp_nldelta_sclip;       //      ISHARP_NLDELTA_SCLIP</div><div class='add'>+	/* blur and scale filter */</div><div class='add'>+	const uint16_t *filter_blur_scale_v;</div><div class='add'>+	const uint16_t *filter_blur_scale_h;</div><div class='add'>+	int sharpness_level; /* Track sharpness level */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPL input and output definitions */</div><div class='add'>+// SPL scratch struct</div><div class='add'>+struct spl_scratch {</div><div class='add'>+	// Pack all SPL outputs in scl_data</div><div class='add'>+	struct spl_scaler_data scl_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SPL input and output definitions */</div><div class='add'>+// SPL outputs struct</div><div class='add'>+struct spl_out	{</div><div class='add'>+	// Pack all output need to program hw registers</div><div class='add'>+	struct dscl_prog_data *dscl_prog_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// end of SPL outputs</div><div class='add'>+</div><div class='add'>+// SPL inputs</div><div class='add'>+</div><div class='add'>+// opp extra adjustment for rect</div><div class='add'>+struct spl_opp_adjust {</div><div class='add'>+	int x;</div><div class='add'>+	int y;</div><div class='add'>+	int width;</div><div class='add'>+	int height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// Basic input information</div><div class='add'>+struct basic_in	{</div><div class='add'>+	enum spl_pixel_format format; // Pixel Format</div><div class='add'>+	enum chroma_cositing cositing; /* Chroma Subsampling Offset */</div><div class='add'>+	struct spl_rect src_rect; // Source rect</div><div class='add'>+	struct spl_rect dst_rect; // Destination Rect</div><div class='add'>+	struct spl_rect clip_rect; // Clip rect</div><div class='add'>+	enum spl_rotation_angle rotation;  // Rotation</div><div class='add'>+	bool horizontal_mirror;  // Horizontal mirror</div><div class='add'>+	struct { // previous mpc_combine_h - split count</div><div class='add'>+		bool use_recout_width_aligned;</div><div class='add'>+		union {</div><div class='add'>+			int mpc_num_h_slices;</div><div class='add'>+			int mpc_recout_width_align;</div><div class='add'>+		} num_slices_recout_width;</div><div class='add'>+	} num_h_slices_recout_width_align;</div><div class='add'>+	int mpc_h_slice_index; // previous mpc_combine_v - split_idx</div><div class='add'>+	struct spl_opp_adjust opp_recout_adjust;</div><div class='add'>+	// Inputs for adaptive scaler - TODO</div><div class='add'>+	enum spl_transfer_func_type tf_type; /* Transfer function type */</div><div class='add'>+	enum spl_transfer_func_predefined tf_predefined_type; /* Transfer function predefined type */</div><div class='add'>+	// enum dc_transfer_func_predefined tf;</div><div class='add'>+	enum spl_color_space color_space;	//	Color Space</div><div class='add'>+	unsigned int max_luminance;	//	Max Luminance TODO: Is determined in dc_hw_sequencer.c is_sdr</div><div class='add'>+	bool film_grain_applied;	//	Film Grain Applied // TODO: To check from where to get this?</div><div class='add'>+	int custom_width; // Width for non-standard segmentation - used when != 0</div><div class='add'>+	int custom_x;     // Start x for non-standard segmentation - used when custom_width != 0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// Basic output information</div><div class='add'>+struct basic_out {</div><div class='add'>+	struct spl_size output_size; // Output Size</div><div class='add'>+	struct spl_rect dst_rect;	// Destination Rect</div><div class='add'>+	struct spl_rect src_rect;	// Source rect</div><div class='add'>+	int odm_combine_factor;	// deprecated</div><div class='add'>+	struct spl_rect odm_slice_rect; // OPP input rect in timing active</div><div class='add'>+	enum spl_view_3d view_format;	// TODO: View format Check if it is chroma subsampling</div><div class='add'>+	bool always_scale;	// Is always scale enabled? Required for getting SCL_MODE</div><div class='add'>+	int max_downscale_src_width; // Required to get optimal no of taps</div><div class='add'>+	bool alpha_en;</div><div class='add'>+	bool use_two_pixels_per_container;</div><div class='add'>+};</div><div class='add'>+enum sharpness_setting	{</div><div class='add'>+	SHARPNESS_HW_OFF = 0,</div><div class='add'>+	SHARPNESS_ZERO,</div><div class='add'>+	SHARPNESS_CUSTOM</div><div class='add'>+};</div><div class='add'>+enum sharpness_range_source	{</div><div class='add'>+	SHARPNESS_RANGE_DCN = 0,</div><div class='add'>+	SHARPNESS_RANGE_DCN_OVERRIDE</div><div class='add'>+};</div><div class='add'>+struct spl_sharpness_range {</div><div class='add'>+	int sdr_rgb_min;</div><div class='add'>+	int sdr_rgb_max;</div><div class='add'>+	int sdr_rgb_mid;</div><div class='add'>+	int sdr_yuv_min;</div><div class='add'>+	int sdr_yuv_max;</div><div class='add'>+	int sdr_yuv_mid;</div><div class='add'>+	int hdr_rgb_min;</div><div class='add'>+	int hdr_rgb_max;</div><div class='add'>+	int hdr_rgb_mid;</div><div class='add'>+};</div><div class='add'>+struct adaptive_sharpness {</div><div class='add'>+	bool enable;</div><div class='add'>+	unsigned int sharpness_level;</div><div class='add'>+	struct spl_sharpness_range sharpness_range;</div><div class='add'>+};</div><div class='add'>+enum linear_light_scaling	{	// convert it in translation logic</div><div class='add'>+	LLS_PREF_DONT_CARE = 0,</div><div class='add'>+	LLS_PREF_YES,</div><div class='add'>+	LLS_PREF_NO</div><div class='add'>+};</div><div class='add'>+enum sharpen_policy {</div><div class='add'>+	SHARPEN_ALWAYS = 0,</div><div class='add'>+	SHARPEN_YUV = 1,</div><div class='add'>+	SHARPEN_RGB_FULLSCREEN_YUV = 2,</div><div class='add'>+	SHARPEN_FULLSCREEN_ALL = 3</div><div class='add'>+};</div><div class='add'>+enum scale_to_sharpness_policy {</div><div class='add'>+	NO_SCALE_TO_SHARPNESS_ADJ = 0,</div><div class='add'>+	SCALE_TO_SHARPNESS_ADJ_YUV = 1,</div><div class='add'>+	SCALE_TO_SHARPNESS_ADJ_ALL = 2</div><div class='add'>+};</div><div class='add'>+struct spl_callbacks {</div><div class='add'>+	void (*spl_calc_lb_num_partitions)</div><div class='add'>+		(bool alpha_en,</div><div class='add'>+		const struct spl_scaler_data *scl_data,</div><div class='add'>+		enum lb_memory_config lb_config,</div><div class='add'>+		int *num_part_y,</div><div class='add'>+		int *num_part_c);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct spl_debug {</div><div class='add'>+	int visual_confirm_base_offset;</div><div class='add'>+	int visual_confirm_dpp_offset;</div><div class='add'>+	enum scale_to_sharpness_policy scale_to_sharpness_policy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct spl_in	{</div><div class='add'>+	struct basic_out basic_out;</div><div class='add'>+	struct basic_in basic_in;</div><div class='add'>+	// Basic slice information</div><div class='add'>+	int odm_slice_index;	// ODM Slice Index using get_odm_split_index</div><div class='add'>+	struct spl_taps scaling_quality; // Explicit Scaling Quality</div><div class='add'>+	struct spl_callbacks callbacks;</div><div class='add'>+	// Inputs for isharp and EASF</div><div class='add'>+	struct adaptive_sharpness adaptive_sharpness;	//	Adaptive Sharpness</div><div class='add'>+	enum linear_light_scaling lls_pref;	//	Linear Light Scaling</div><div class='add'>+	bool prefer_easf;</div><div class='add'>+	bool disable_easf;</div><div class='add'>+	bool override_easf; /* If true, keep EASF enabled but use provided in_taps */</div><div class='add'>+	struct spl_debug debug;</div><div class='add'>+	bool is_fullscreen;</div><div class='add'>+	bool is_hdr_on;</div><div class='add'>+	int h_active;</div><div class='add'>+	int v_active;</div><div class='add'>+	int min_viewport_size;</div><div class='add'>+	int sdr_white_level_nits;</div><div class='add'>+	enum sharpen_policy sharpen_policy;</div><div class='add'>+};</div><div class='add'>+// end of SPL inputs</div><div class='add'>+</div><div class='add'>+#endif /* __DC_SPL_TYPES_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c b/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c<br/>new file mode 100644<br/>index 000000000000..be2f34d034c5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c</a></div><div class='hunk'>@@ -0,0 +1,151 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+#include "spl_custom_float.h"</div><div class='add'>+</div><div class='add'>+static bool spl_build_custom_float(struct spl_fixed31_32 value,</div><div class='add'>+			       const struct spl_custom_float_format *format,</div><div class='add'>+			       bool *negative,</div><div class='add'>+			       uint32_t *mantissa,</div><div class='add'>+			       uint32_t *exponenta)</div><div class='add'>+{</div><div class='add'>+	uint32_t exp_offset = (1 &lt;&lt; (format-&gt;exponenta_bits - 1)) - 1;</div><div class='add'>+</div><div class='add'>+	const struct spl_fixed31_32 mantissa_constant_plus_max_fraction =</div><div class='add'>+		spl_fixpt_from_fraction((1LL &lt;&lt; (format-&gt;mantissa_bits + 1)) - 1,</div><div class='add'>+				       1LL &lt;&lt; format-&gt;mantissa_bits);</div><div class='add'>+</div><div class='add'>+	struct spl_fixed31_32 mantiss;</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_eq(value, spl_fixpt_zero)) {</div><div class='add'>+		*negative = false;</div><div class='add'>+		*mantissa = 0;</div><div class='add'>+		*exponenta = 0;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_lt(value, spl_fixpt_zero)) {</div><div class='add'>+		*negative = format-&gt;sign;</div><div class='add'>+		value = spl_fixpt_neg(value);</div><div class='add'>+	} else {</div><div class='add'>+		*negative = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_lt(value, spl_fixpt_one)) {</div><div class='add'>+		uint32_t i = 1;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			value = spl_fixpt_shl(value, 1);</div><div class='add'>+			++i;</div><div class='add'>+		} while (spl_fixpt_lt(value, spl_fixpt_one));</div><div class='add'>+</div><div class='add'>+		--i;</div><div class='add'>+</div><div class='add'>+		if (exp_offset &lt;= i) {</div><div class='add'>+			*mantissa = 0;</div><div class='add'>+			*exponenta = 0;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*exponenta = exp_offset - i;</div><div class='add'>+	} else if (spl_fixpt_le(mantissa_constant_plus_max_fraction, value)) {</div><div class='add'>+		uint32_t i = 1;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			value = spl_fixpt_shr(value, 1);</div><div class='add'>+			++i;</div><div class='add'>+		} while (spl_fixpt_lt(mantissa_constant_plus_max_fraction, value));</div><div class='add'>+</div><div class='add'>+		*exponenta = exp_offset + i - 1;</div><div class='add'>+	} else {</div><div class='add'>+		*exponenta = exp_offset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mantiss = spl_fixpt_sub(value, spl_fixpt_one);</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_lt(mantiss, spl_fixpt_zero) ||</div><div class='add'>+	    spl_fixpt_lt(spl_fixpt_one, mantiss))</div><div class='add'>+		mantiss = spl_fixpt_zero;</div><div class='add'>+	else</div><div class='add'>+		mantiss = spl_fixpt_shl(mantiss, format-&gt;mantissa_bits);</div><div class='add'>+</div><div class='add'>+	*mantissa = spl_fixpt_floor(mantiss);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool spl_setup_custom_float(const struct spl_custom_float_format *format,</div><div class='add'>+			       bool negative,</div><div class='add'>+			       uint32_t mantissa,</div><div class='add'>+			       uint32_t exponenta,</div><div class='add'>+			       uint32_t *result)</div><div class='add'>+{</div><div class='add'>+	uint32_t i = 0;</div><div class='add'>+	uint32_t j = 0;</div><div class='add'>+	uint32_t value = 0;</div><div class='add'>+</div><div class='add'>+	/* verification code:</div><div class='add'>+	 * once calculation is ok we can remove it</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	const uint32_t mantissa_mask =</div><div class='add'>+		(1 &lt;&lt; (format-&gt;mantissa_bits + 1)) - 1;</div><div class='add'>+</div><div class='add'>+	const uint32_t exponenta_mask =</div><div class='add'>+		(1 &lt;&lt; (format-&gt;exponenta_bits + 1)) - 1;</div><div class='add'>+</div><div class='add'>+	if (mantissa &amp; ~mantissa_mask) {</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		mantissa = mantissa_mask;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (exponenta &amp; ~exponenta_mask) {</div><div class='add'>+		SPL_BREAK_TO_DEBUGGER();</div><div class='add'>+		exponenta = exponenta_mask;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* end of verification code */</div><div class='add'>+</div><div class='add'>+	while (i &lt; format-&gt;mantissa_bits) {</div><div class='add'>+		uint32_t mask = 1 &lt;&lt; i;</div><div class='add'>+</div><div class='add'>+		if (mantissa &amp; mask)</div><div class='add'>+			value |= mask;</div><div class='add'>+</div><div class='add'>+		++i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	while (j &lt; format-&gt;exponenta_bits) {</div><div class='add'>+		uint32_t mask = 1 &lt;&lt; j;</div><div class='add'>+</div><div class='add'>+		if (exponenta &amp; mask)</div><div class='add'>+			value |= mask &lt;&lt; i;</div><div class='add'>+</div><div class='add'>+		++j;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (negative &amp;&amp; format-&gt;sign)</div><div class='add'>+		value |= 1 &lt;&lt; (i + j);</div><div class='add'>+</div><div class='add'>+	*result = value;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool spl_convert_to_custom_float_format(struct spl_fixed31_32 value,</div><div class='add'>+				    const struct spl_custom_float_format *format,</div><div class='add'>+				    uint32_t *result)</div><div class='add'>+{</div><div class='add'>+	uint32_t mantissa;</div><div class='add'>+	uint32_t exponenta;</div><div class='add'>+	bool negative;</div><div class='add'>+</div><div class='add'>+	return spl_build_custom_float(value, format, &amp;negative, &amp;mantissa, &amp;exponenta) &amp;&amp;</div><div class='add'>+				  spl_setup_custom_float(format,</div><div class='add'>+						     negative,</div><div class='add'>+						     mantissa,</div><div class='add'>+						     exponenta,</div><div class='add'>+						     result);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h<br/>new file mode 100644<br/>index 000000000000..cdc4e107b9de<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+</div><div class='add'>+/* Copyright 2024 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef SPL_CUSTOM_FLOAT_H_</div><div class='add'>+#define SPL_CUSTOM_FLOAT_H_</div><div class='add'>+</div><div class='add'>+#include "spl_os_types.h"</div><div class='add'>+#include "spl_fixpt31_32.h"</div><div class='add'>+</div><div class='add'>+struct spl_custom_float_format {</div><div class='add'>+	uint32_t mantissa_bits;</div><div class='add'>+	uint32_t exponenta_bits;</div><div class='add'>+	bool sign;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct spl_custom_float_value {</div><div class='add'>+	uint32_t mantissa;</div><div class='add'>+	uint32_t exponenta;</div><div class='add'>+	uint32_t value;</div><div class='add'>+	bool negative;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool spl_convert_to_custom_float_format(</div><div class='add'>+	struct spl_fixed31_32 value,</div><div class='add'>+	const struct spl_custom_float_format *format,</div><div class='add'>+	uint32_t *result);</div><div class='add'>+</div><div class='add'>+#endif //SPL_CUSTOM_FLOAT_H_</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h<br/>new file mode 100644<br/>index 000000000000..a6f6132df241<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/spl_debug.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+</div><div class='add'>+/* Copyright 2024 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef SPL_DEBUG_H</div><div class='add'>+#define SPL_DEBUG_H</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)</div><div class='add'>+#define SPL_ASSERT_CRITICAL(expr) do {	\</div><div class='add'>+	if (WARN_ON(!(expr))) { \</div><div class='add'>+		kgdb_breakpoint(); \</div><div class='add'>+	} \</div><div class='add'>+} while (0)</div><div class='add'>+#else</div><div class='add'>+#define SPL_ASSERT_CRITICAL(expr) do {	\</div><div class='add'>+	if (WARN_ON(!(expr))) { \</div><div class='add'>+		; \</div><div class='add'>+	} \</div><div class='add'>+} while (0)</div><div class='add'>+#endif /* CONFIG_HAVE_KGDB || CONFIG_KGDB */</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DEBUG_KERNEL_DC)</div><div class='add'>+#define SPL_ASSERT(expr) SPL_ASSERT_CRITICAL(expr)</div><div class='add'>+#else</div><div class='add'>+#define SPL_ASSERT(expr) WARN_ON(!(expr))</div><div class='add'>+#endif /* CONFIG_DEBUG_KERNEL_DC */</div><div class='add'>+</div><div class='add'>+#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT(0)</div><div class='add'>+</div><div class='add'>+#endif  // SPL_DEBUG_H</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c<br/>new file mode 100644<br/>index 000000000000..ebf0287417e0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c</a></div><div class='hunk'>@@ -0,0 +1,493 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "spl_fixpt31_32.h"</div><div class='add'>+</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_two_pi = { 26986075409LL };</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_ln2 = { 2977044471LL };</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_ln2_div_2 = { 1488522236LL };</div><div class='add'>+</div><div class='add'>+static inline unsigned long long abs_i64(</div><div class='add'>+	long long arg)</div><div class='add'>+{</div><div class='add'>+	if (arg &gt; 0)</div><div class='add'>+		return (unsigned long long)arg;</div><div class='add'>+	else</div><div class='add'>+		return (unsigned long long)(-arg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = dividend / divisor</div><div class='add'>+ * *remainder = dividend % divisor</div><div class='add'>+ */</div><div class='add'>+static inline unsigned long long spl_complete_integer_division_u64(</div><div class='add'>+	unsigned long long dividend,</div><div class='add'>+	unsigned long long divisor,</div><div class='add'>+	unsigned long long *remainder)</div><div class='add'>+{</div><div class='add'>+	unsigned long long result;</div><div class='add'>+</div><div class='add'>+	result = spl_div64_u64_rem(dividend, divisor, remainder);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define FRACTIONAL_PART_MASK \</div><div class='add'>+	((1ULL &lt;&lt; FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)</div><div class='add'>+</div><div class='add'>+#define GET_INTEGER_PART(x) \</div><div class='add'>+	((x) &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART)</div><div class='add'>+</div><div class='add'>+#define GET_FRACTIONAL_PART(x) \</div><div class='add'>+	(FRACTIONAL_PART_MASK &amp; (x))</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long denominator)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	bool arg1_negative = numerator &lt; 0;</div><div class='add'>+	bool arg2_negative = denominator &lt; 0;</div><div class='add'>+</div><div class='add'>+	unsigned long long arg1_value = arg1_negative ? -numerator : numerator;</div><div class='add'>+	unsigned long long arg2_value = arg2_negative ? -denominator : denominator;</div><div class='add'>+</div><div class='add'>+	unsigned long long remainder;</div><div class='add'>+</div><div class='add'>+	/* determine integer part */</div><div class='add'>+</div><div class='add'>+	unsigned long long res_value = spl_complete_integer_division_u64(</div><div class='add'>+		arg1_value, arg2_value, &amp;remainder);</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(res_value &lt;= (unsigned long long)LONG_MAX);</div><div class='add'>+</div><div class='add'>+	/* determine fractional part */</div><div class='add'>+	{</div><div class='add'>+		unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			remainder &lt;&lt;= 1;</div><div class='add'>+</div><div class='add'>+			res_value &lt;&lt;= 1;</div><div class='add'>+</div><div class='add'>+			if (remainder &gt;= arg2_value) {</div><div class='add'>+				res_value |= 1;</div><div class='add'>+				remainder -= arg2_value;</div><div class='add'>+			}</div><div class='add'>+		} while (--i != 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* round up LSB */</div><div class='add'>+	{</div><div class='add'>+		unsigned long long summand = (remainder &lt;&lt; 1) &gt;= arg2_value;</div><div class='add'>+</div><div class='add'>+		SPL_ASSERT(res_value &lt;= (unsigned long long)LLONG_MAX - summand);</div><div class='add'>+</div><div class='add'>+		res_value += summand;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	res.value = (long long)res_value;</div><div class='add'>+</div><div class='add'>+	if (arg1_negative ^ arg2_negative)</div><div class='add'>+		res.value = -res.value;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	bool arg1_negative = arg1.value &lt; 0;</div><div class='add'>+	bool arg2_negative = arg2.value &lt; 0;</div><div class='add'>+</div><div class='add'>+	unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value;</div><div class='add'>+	unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value;</div><div class='add'>+</div><div class='add'>+	unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);</div><div class='add'>+	unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);</div><div class='add'>+</div><div class='add'>+	unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);</div><div class='add'>+	unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);</div><div class='add'>+</div><div class='add'>+	unsigned long long tmp;</div><div class='add'>+</div><div class='add'>+	res.value = arg1_int * arg2_int;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(res.value &lt;= (long long)LONG_MAX);</div><div class='add'>+</div><div class='add'>+	res.value &lt;&lt;= FIXED31_32_BITS_PER_FRACTIONAL_PART;</div><div class='add'>+</div><div class='add'>+	tmp = arg1_int * arg2_fra;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(tmp &lt;= (unsigned long long)(LLONG_MAX - res.value));</div><div class='add'>+</div><div class='add'>+	res.value += tmp;</div><div class='add'>+</div><div class='add'>+	tmp = arg2_int * arg1_fra;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(tmp &lt;= (unsigned long long)(LLONG_MAX - res.value));</div><div class='add'>+</div><div class='add'>+	res.value += tmp;</div><div class='add'>+</div><div class='add'>+	tmp = arg1_fra * arg2_fra;</div><div class='add'>+</div><div class='add'>+	tmp = (tmp &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART) +</div><div class='add'>+		(tmp &gt;= (unsigned long long)spl_fixpt_half.value);</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(tmp &lt;= (unsigned long long)(LLONG_MAX - res.value));</div><div class='add'>+</div><div class='add'>+	res.value += tmp;</div><div class='add'>+</div><div class='add'>+	if (arg1_negative ^ arg2_negative)</div><div class='add'>+		res.value = -res.value;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	unsigned long long arg_value = abs_i64(arg.value);</div><div class='add'>+</div><div class='add'>+	unsigned long long arg_int = GET_INTEGER_PART(arg_value);</div><div class='add'>+</div><div class='add'>+	unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value);</div><div class='add'>+</div><div class='add'>+	unsigned long long tmp;</div><div class='add'>+</div><div class='add'>+	res.value = arg_int * arg_int;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(res.value &lt;= (long long)LONG_MAX);</div><div class='add'>+</div><div class='add'>+	res.value &lt;&lt;= FIXED31_32_BITS_PER_FRACTIONAL_PART;</div><div class='add'>+</div><div class='add'>+	tmp = arg_int * arg_fra;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(tmp &lt;= (unsigned long long)(LLONG_MAX - res.value));</div><div class='add'>+</div><div class='add'>+	res.value += tmp;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(tmp &lt;= (unsigned long long)(LLONG_MAX - res.value));</div><div class='add'>+</div><div class='add'>+	res.value += tmp;</div><div class='add'>+</div><div class='add'>+	tmp = arg_fra * arg_fra;</div><div class='add'>+</div><div class='add'>+	tmp = (tmp &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART) +</div><div class='add'>+		(tmp &gt;= (unsigned long long)spl_fixpt_half.value);</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(tmp &lt;= (unsigned long long)(LLONG_MAX - res.value));</div><div class='add'>+</div><div class='add'>+	res.value += tmp;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * @note</div><div class='add'>+	 * Good idea to use Newton's method</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	return spl_fixpt_from_fraction(</div><div class='add'>+		spl_fixpt_one.value,</div><div class='add'>+		arg.value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 square;</div><div class='add'>+</div><div class='add'>+	struct spl_fixed31_32 res = spl_fixpt_one;</div><div class='add'>+</div><div class='add'>+	int n = 27;</div><div class='add'>+</div><div class='add'>+	struct spl_fixed31_32 arg_norm = arg;</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_le(</div><div class='add'>+		spl_fixpt_two_pi,</div><div class='add'>+		spl_fixpt_abs(arg))) {</div><div class='add'>+		arg_norm = spl_fixpt_sub(</div><div class='add'>+			arg_norm,</div><div class='add'>+			spl_fixpt_mul_int(</div><div class='add'>+				spl_fixpt_two_pi,</div><div class='add'>+				(int)spl_div64_s64(</div><div class='add'>+					arg_norm.value,</div><div class='add'>+					spl_fixpt_two_pi.value)));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	square = spl_fixpt_sqr(arg_norm);</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		res = spl_fixpt_sub(</div><div class='add'>+			spl_fixpt_one,</div><div class='add'>+			spl_fixpt_div_int(</div><div class='add'>+				spl_fixpt_mul(</div><div class='add'>+					square,</div><div class='add'>+					res),</div><div class='add'>+				n * (n - 1)));</div><div class='add'>+</div><div class='add'>+		n -= 2;</div><div class='add'>+	} while (n &gt; 2);</div><div class='add'>+</div><div class='add'>+	if (arg.value != arg_norm.value)</div><div class='add'>+		res = spl_fixpt_div(</div><div class='add'>+			spl_fixpt_mul(res, arg_norm),</div><div class='add'>+			arg);</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_fixpt_mul(</div><div class='add'>+		arg,</div><div class='add'>+		spl_fixpt_sinc(arg));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	/* TODO implement argument normalization */</div><div class='add'>+</div><div class='add'>+	const struct spl_fixed31_32 square = spl_fixpt_sqr(arg);</div><div class='add'>+</div><div class='add'>+	struct spl_fixed31_32 res = spl_fixpt_one;</div><div class='add'>+</div><div class='add'>+	int n = 26;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		res = spl_fixpt_sub(</div><div class='add'>+			spl_fixpt_one,</div><div class='add'>+			spl_fixpt_div_int(</div><div class='add'>+				spl_fixpt_mul(</div><div class='add'>+					square,</div><div class='add'>+					res),</div><div class='add'>+				n * (n - 1)));</div><div class='add'>+</div><div class='add'>+		n -= 2;</div><div class='add'>+	} while (n != 0);</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = exp(arg),</div><div class='add'>+ * where abs(arg) &lt; 1</div><div class='add'>+ *</div><div class='add'>+ * Calculated as Taylor series.</div><div class='add'>+ */</div><div class='add'>+static struct spl_fixed31_32 spl_fixed31_32_exp_from_taylor_series(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	unsigned int n = 9;</div><div class='add'>+</div><div class='add'>+	struct spl_fixed31_32 res = spl_fixpt_from_fraction(</div><div class='add'>+		n + 2,</div><div class='add'>+		n + 1);</div><div class='add'>+	/* TODO find correct res */</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(spl_fixpt_lt(arg, spl_fixpt_one));</div><div class='add'>+</div><div class='add'>+	do</div><div class='add'>+		res = spl_fixpt_add(</div><div class='add'>+			spl_fixpt_one,</div><div class='add'>+			spl_fixpt_div_int(</div><div class='add'>+				spl_fixpt_mul(</div><div class='add'>+					arg,</div><div class='add'>+					res),</div><div class='add'>+				n));</div><div class='add'>+	while (--n != 1);</div><div class='add'>+</div><div class='add'>+	return spl_fixpt_add(</div><div class='add'>+		spl_fixpt_one,</div><div class='add'>+		spl_fixpt_mul(</div><div class='add'>+			arg,</div><div class='add'>+			res));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * @brief</div><div class='add'>+	 * Main equation is:</div><div class='add'>+	 * exp(x) = exp(r + m * ln(2)) = (1 &lt;&lt; m) * exp(r),</div><div class='add'>+	 * where m = round(x / ln(2)), r = x - m * ln(2)</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (spl_fixpt_le(</div><div class='add'>+		spl_fixpt_ln2_div_2,</div><div class='add'>+		spl_fixpt_abs(arg))) {</div><div class='add'>+		int m = spl_fixpt_round(</div><div class='add'>+			spl_fixpt_div(</div><div class='add'>+				arg,</div><div class='add'>+				spl_fixpt_ln2));</div><div class='add'>+</div><div class='add'>+		struct spl_fixed31_32 r = spl_fixpt_sub(</div><div class='add'>+			arg,</div><div class='add'>+			spl_fixpt_mul_int(</div><div class='add'>+				spl_fixpt_ln2,</div><div class='add'>+				m));</div><div class='add'>+</div><div class='add'>+		SPL_ASSERT(m != 0);</div><div class='add'>+</div><div class='add'>+		SPL_ASSERT(spl_fixpt_lt(</div><div class='add'>+			spl_fixpt_abs(r),</div><div class='add'>+			spl_fixpt_one));</div><div class='add'>+</div><div class='add'>+		if (m &gt; 0)</div><div class='add'>+			return spl_fixpt_shl(</div><div class='add'>+				spl_fixed31_32_exp_from_taylor_series(r),</div><div class='add'>+				(unsigned int)m);</div><div class='add'>+		else</div><div class='add'>+			return spl_fixpt_div_int(</div><div class='add'>+				spl_fixed31_32_exp_from_taylor_series(r),</div><div class='add'>+				1LL &lt;&lt; -m);</div><div class='add'>+	} else if (arg.value != 0)</div><div class='add'>+		return spl_fixed31_32_exp_from_taylor_series(arg);</div><div class='add'>+	else</div><div class='add'>+		return spl_fixpt_one;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res = spl_fixpt_neg(spl_fixpt_one);</div><div class='add'>+	/* TODO improve 1st estimation */</div><div class='add'>+</div><div class='add'>+	struct spl_fixed31_32 error;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(arg.value &gt; 0);</div><div class='add'>+	/* TODO if arg is negative, return NaN */</div><div class='add'>+	/* TODO if arg is zero, return -INF */</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		struct spl_fixed31_32 res1 = spl_fixpt_add(</div><div class='add'>+			spl_fixpt_sub(</div><div class='add'>+				res,</div><div class='add'>+				spl_fixpt_one),</div><div class='add'>+			spl_fixpt_div(</div><div class='add'>+				arg,</div><div class='add'>+				spl_fixpt_exp(res)));</div><div class='add'>+</div><div class='add'>+		error = spl_fixpt_sub(</div><div class='add'>+			res,</div><div class='add'>+			res1);</div><div class='add'>+</div><div class='add'>+		res = res1;</div><div class='add'>+		/* TODO determine max_allowed_error based on quality of exp() */</div><div class='add'>+	} while (abs_i64(error.value) &gt; 100ULL);</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/* this function is a generic helper to translate fixed point value to</div><div class='add'>+ * specified integer format that will consist of integer_bits integer part and</div><div class='add'>+ * fractional_bits fractional part. For example it is used in</div><div class='add'>+ * spl_fixpt_u2d19 to receive 2 bits integer part and 19 bits fractional</div><div class='add'>+ * part in 32 bits. It is used in hw programming (scaler)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static inline unsigned int spl_ux_dy(</div><div class='add'>+	long long value,</div><div class='add'>+	unsigned int integer_bits,</div><div class='add'>+	unsigned int fractional_bits)</div><div class='add'>+{</div><div class='add'>+	/* 1. create mask of integer part */</div><div class='add'>+	unsigned int result = (1 &lt;&lt; integer_bits) - 1;</div><div class='add'>+	/* 2. mask out fractional part */</div><div class='add'>+	unsigned int fractional_part = FRACTIONAL_PART_MASK &amp; value;</div><div class='add'>+	/* 3. shrink fixed point integer part to be of integer_bits width*/</div><div class='add'>+	result &amp;= GET_INTEGER_PART(value);</div><div class='add'>+	/* 4. make space for fractional part to be filled in after integer */</div><div class='add'>+	result &lt;&lt;= fractional_bits;</div><div class='add'>+	/* 5. shrink fixed point fractional part to of fractional_bits width*/</div><div class='add'>+	fractional_part &gt;&gt;= FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits;</div><div class='add'>+	/* 6. merge the result */</div><div class='add'>+	return result | fractional_part;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline unsigned int spl_clamp_ux_dy(</div><div class='add'>+	long long value,</div><div class='add'>+	unsigned int integer_bits,</div><div class='add'>+	unsigned int fractional_bits,</div><div class='add'>+	unsigned int min_clamp)</div><div class='add'>+{</div><div class='add'>+	unsigned int truncated_val = spl_ux_dy(value, integer_bits, fractional_bits);</div><div class='add'>+</div><div class='add'>+	if (value &gt;= (1LL &lt;&lt; (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))</div><div class='add'>+		return (1 &lt;&lt; (integer_bits + fractional_bits)) - 1;</div><div class='add'>+	else if (truncated_val &gt; min_clamp)</div><div class='add'>+		return truncated_val;</div><div class='add'>+	else</div><div class='add'>+		return min_clamp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_ux_dy(arg.value, 4, 19);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_ux_dy(arg.value, 3, 19);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_ux_dy(arg.value, 2, 19);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_ux_dy(arg.value, 0, 19);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_clamp_ux_dy(arg.value, 0, 14, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	return spl_clamp_ux_dy(arg.value, 0, 10, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int spl_fixpt_s4d19(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	if (arg.value &lt; 0)</div><div class='add'>+		return -(int)spl_ux_dy(spl_fixpt_abs(arg).value, 4, 19);</div><div class='add'>+	else</div><div class='add'>+		return spl_ux_dy(arg.value, 4, 19);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value,</div><div class='add'>+	unsigned int integer_bits,</div><div class='add'>+	unsigned int fractional_bits)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 fixpt_value = spl_fixpt_zero;</div><div class='add'>+	struct spl_fixed31_32 fixpt_int_value = spl_fixpt_zero;</div><div class='add'>+	long long frac_mask = ((long long)1 &lt;&lt; (long long)integer_bits) - 1;</div><div class='add'>+</div><div class='add'>+	fixpt_value.value = (long long)value &lt;&lt; (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);</div><div class='add'>+	frac_mask = frac_mask &lt;&lt; fractional_bits;</div><div class='add'>+	fixpt_int_value.value = value &amp; frac_mask;</div><div class='add'>+	fixpt_int_value.value &lt;&lt;= (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);</div><div class='add'>+	fixpt_value.value |= fixpt_int_value.value;</div><div class='add'>+	return fixpt_value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_from_int_dy(unsigned int int_value,</div><div class='add'>+	unsigned int frac_value,</div><div class='add'>+	unsigned int integer_bits,</div><div class='add'>+	unsigned int fractional_bits)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 fixpt_value = spl_fixpt_from_int(int_value);</div><div class='add'>+</div><div class='add'>+	fixpt_value.value |= (long long)frac_value &lt;&lt; (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits);</div><div class='add'>+	return fixpt_value;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h<br/>new file mode 100644<br/>index 000000000000..9f349ffe9148<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h</a></div><div class='hunk'>@@ -0,0 +1,522 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+</div><div class='add'>+/* Copyright 2024 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef __SPL_FIXED31_32_H__</div><div class='add'>+#define __SPL_FIXED31_32_H__</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+#include "spl_os_types.h"   // swap</div><div class='add'>+</div><div class='add'>+#ifndef LLONG_MAX</div><div class='add'>+#define LLONG_MAX 9223372036854775807ll</div><div class='add'>+#endif</div><div class='add'>+#ifndef LLONG_MIN</div><div class='add'>+#define LLONG_MIN (-LLONG_MAX - 1ll)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32</div><div class='add'>+#ifndef LLONG_MIN</div><div class='add'>+#define LLONG_MIN (1LL&lt;&lt;63)</div><div class='add'>+#endif</div><div class='add'>+#ifndef LLONG_MAX</div><div class='add'>+#define LLONG_MAX (-1LL&gt;&gt;1)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Arithmetic operations on real numbers</div><div class='add'>+ * represented as fixed-point numbers.</div><div class='add'>+ * There are: 1 bit for sign,</div><div class='add'>+ * 31 bit for integer part,</div><div class='add'>+ * 32 bits for fractional part.</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Currently, overflows and underflows are asserted;</div><div class='add'>+ * no special result returned.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 {</div><div class='add'>+	long long value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Useful constants</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_zero = { 0 };</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_epsilon = { 1LL };</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_half = { 0x80000000LL };</div><div class='add'>+static const struct spl_fixed31_32 spl_fixpt_one = { 0x100000000LL };</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Initialization routines</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = numerator / denominator</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long denominator);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_from_int(int arg)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	res.value = (long long) arg &lt;&lt; FIXED31_32_BITS_PER_FRACTIONAL_PART;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Unary operators</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = -arg</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_neg(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	res.value = -arg.value;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = abs(arg) := (arg &gt;= 0) ? arg : -arg</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_abs(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	if (arg.value &lt; 0)</div><div class='add'>+		return spl_fixpt_neg(arg);</div><div class='add'>+	else</div><div class='add'>+		return arg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Binary relational operators</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 &lt; arg2</div><div class='add'>+ */</div><div class='add'>+static inline bool spl_fixpt_lt(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	return arg1.value &lt; arg2.value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 &lt;= arg2</div><div class='add'>+ */</div><div class='add'>+static inline bool spl_fixpt_le(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	return arg1.value &lt;= arg2.value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 == arg2</div><div class='add'>+ */</div><div class='add'>+static inline bool spl_fixpt_eq(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	return arg1.value == arg2.value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = min(arg1, arg2) := (arg1 &lt;= arg2) ? arg1 : arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_min(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	if (arg1.value &lt;= arg2.value)</div><div class='add'>+		return arg1;</div><div class='add'>+	else</div><div class='add'>+		return arg2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = max(arg1, arg2) := (arg1 &lt;= arg2) ? arg2 : arg1</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_max(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	if (arg1.value &lt;= arg2.value)</div><div class='add'>+		return arg2;</div><div class='add'>+	else</div><div class='add'>+		return arg1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ *          | min_value, when arg &lt;= min_value</div><div class='add'>+ * result = | arg, when min_value &lt; arg &lt; max_value</div><div class='add'>+ *          | max_value, when arg &gt;= max_value</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_clamp(</div><div class='add'>+	struct spl_fixed31_32 arg,</div><div class='add'>+	struct spl_fixed31_32 min_value,</div><div class='add'>+	struct spl_fixed31_32 max_value)</div><div class='add'>+{</div><div class='add'>+	if (spl_fixpt_le(arg, min_value))</div><div class='add'>+		return min_value;</div><div class='add'>+	else if (spl_fixpt_le(max_value, arg))</div><div class='add'>+		return max_value;</div><div class='add'>+	else</div><div class='add'>+		return arg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Binary shift operators</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg &lt;&lt; shift</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_shl(struct spl_fixed31_32 arg, unsigned int shift)</div><div class='add'>+{</div><div class='add'>+	SPL_ASSERT(((arg.value &gt;= 0) &amp;&amp; (arg.value &lt;= LLONG_MAX &gt;&gt; shift)) ||</div><div class='add'>+		((arg.value &lt; 0) &amp;&amp; (arg.value &gt;= ~(LLONG_MAX &gt;&gt; shift))));</div><div class='add'>+</div><div class='add'>+	arg.value = arg.value &lt;&lt; shift;</div><div class='add'>+</div><div class='add'>+	return arg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg &gt;&gt; shift</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_shr(struct spl_fixed31_32 arg, unsigned int shift)</div><div class='add'>+{</div><div class='add'>+	bool negative = arg.value &lt; 0;</div><div class='add'>+</div><div class='add'>+	if (negative)</div><div class='add'>+		arg.value = -arg.value;</div><div class='add'>+	arg.value = arg.value &gt;&gt; shift;</div><div class='add'>+	if (negative)</div><div class='add'>+		arg.value = -arg.value;</div><div class='add'>+	return arg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Binary additive operators</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 + arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_add(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(((arg1.value &gt;= 0) &amp;&amp; (LLONG_MAX - arg1.value &gt;= arg2.value)) ||</div><div class='add'>+		((arg1.value &lt; 0) &amp;&amp; (LLONG_MIN - arg1.value &lt;= arg2.value)));</div><div class='add'>+</div><div class='add'>+	res.value = arg1.value + arg2.value;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 + arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_add_int(struct spl_fixed31_32 arg1, int arg2)</div><div class='add'>+{</div><div class='add'>+	return spl_fixpt_add(arg1, spl_fixpt_from_int(arg2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 - arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_sub(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	struct spl_fixed31_32 res;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(((arg2.value &gt;= 0) &amp;&amp; (LLONG_MIN + arg2.value &lt;= arg1.value)) ||</div><div class='add'>+		((arg2.value &lt; 0) &amp;&amp; (LLONG_MAX + arg2.value &gt;= arg1.value)));</div><div class='add'>+</div><div class='add'>+	res.value = arg1.value - arg2.value;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 - arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_sub_int(struct spl_fixed31_32 arg1, int arg2)</div><div class='add'>+{</div><div class='add'>+	return spl_fixpt_sub(arg1, spl_fixpt_from_int(arg2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Binary multiplicative operators</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 * arg2</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 * arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_mul_int(struct spl_fixed31_32 arg1, int arg2)</div><div class='add'>+{</div><div class='add'>+	return spl_fixpt_mul(arg1, spl_fixpt_from_int(arg2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = square(arg) := arg * arg</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 / arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_div_int(struct spl_fixed31_32 arg1, long long arg2)</div><div class='add'>+{</div><div class='add'>+	return spl_fixpt_from_fraction(arg1.value, spl_fixpt_from_int((int)arg2).value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = arg1 / arg2</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_div(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	return spl_fixpt_from_fraction(arg1.value, arg2.value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Reciprocal function</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = reciprocal(arg) := 1 / arg</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * No special actions taken in case argument is zero.</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Trigonometric functions</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = sinc(arg) := sin(arg) / arg</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Argument specified in radians,</div><div class='add'>+ * internally it's normalized to [-2pi...2pi] range.</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = sin(arg)</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Argument specified in radians,</div><div class='add'>+ * internally it's normalized to [-2pi...2pi] range.</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = cos(arg)</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Argument specified in radians</div><div class='add'>+ * and should be in [-2pi...2pi] range -</div><div class='add'>+ * passing arguments outside that range</div><div class='add'>+ * will cause incorrect result!</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Transcendent functions</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = exp(arg)</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Currently, function is verified for abs(arg) &lt;= 1.</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = log(arg)</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Currently, abs(arg) should be less than 1.</div><div class='add'>+ * No normalization is done.</div><div class='add'>+ * Currently, no special actions taken</div><div class='add'>+ * in case of invalid argument(s). Take care!</div><div class='add'>+ */</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Power function</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = pow(arg1, arg2)</div><div class='add'>+ *</div><div class='add'>+ * @note</div><div class='add'>+ * Currently, abs(arg1) should be less than 1. Take care!</div><div class='add'>+ */</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_pow(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)</div><div class='add'>+{</div><div class='add'>+	if (arg1.value == 0)</div><div class='add'>+		return arg2.value == 0 ? spl_fixpt_one : spl_fixpt_zero;</div><div class='add'>+</div><div class='add'>+	return spl_fixpt_exp(</div><div class='add'>+		spl_fixpt_mul(</div><div class='add'>+			spl_fixpt_log(arg1),</div><div class='add'>+			arg2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * Rounding functions</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = floor(arg) := greatest integer lower than or equal to arg</div><div class='add'>+ */</div><div class='add'>+static inline int spl_fixpt_floor(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	unsigned long long arg_value = arg.value &gt; 0 ? arg.value : -arg.value;</div><div class='add'>+</div><div class='add'>+	if (arg.value &gt;= 0)</div><div class='add'>+		return (int)(arg_value &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+	else</div><div class='add'>+		return -(int)(arg_value &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = round(arg) := integer nearest to arg</div><div class='add'>+ */</div><div class='add'>+static inline int spl_fixpt_round(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	unsigned long long arg_value = arg.value &gt; 0 ? arg.value : -arg.value;</div><div class='add'>+</div><div class='add'>+	const long long summand = spl_fixpt_half.value;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(LLONG_MAX - (long long)arg_value &gt;= summand);</div><div class='add'>+</div><div class='add'>+	arg_value += summand;</div><div class='add'>+</div><div class='add'>+	if (arg.value &gt;= 0)</div><div class='add'>+		return (int)(arg_value &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+	else</div><div class='add'>+		return -(int)(arg_value &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * @brief</div><div class='add'>+ * result = ceil(arg) := lowest integer greater than or equal to arg</div><div class='add'>+ */</div><div class='add'>+static inline int spl_fixpt_ceil(struct spl_fixed31_32 arg)</div><div class='add'>+{</div><div class='add'>+	unsigned long long arg_value = arg.value &gt; 0 ? arg.value : -arg.value;</div><div class='add'>+</div><div class='add'>+	const long long summand = spl_fixpt_one.value -</div><div class='add'>+		spl_fixpt_epsilon.value;</div><div class='add'>+</div><div class='add'>+	SPL_ASSERT(LLONG_MAX - (long long)arg_value &gt;= summand);</div><div class='add'>+</div><div class='add'>+	arg_value += summand;</div><div class='add'>+</div><div class='add'>+	if (arg.value &gt;= 0)</div><div class='add'>+		return (int)(arg_value &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+	else</div><div class='add'>+		return -(int)(arg_value &gt;&gt; FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* the following two function are used in scaler hw programming to convert fixed</div><div class='add'>+ * point value to format 2 bits from integer part and 19 bits from fractional</div><div class='add'>+ * part. The same applies for u0d19, 0 bits from integer part and 19 bits from</div><div class='add'>+ * fractional</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+int spl_fixpt_s4d19(struct spl_fixed31_32 arg);</div><div class='add'>+</div><div class='add'>+static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg, unsigned int frac_bits)</div><div class='add'>+{</div><div class='add'>+	bool negative = arg.value &lt; 0;</div><div class='add'>+</div><div class='add'>+	if (frac_bits &gt;= FIXED31_32_BITS_PER_FRACTIONAL_PART) {</div><div class='add'>+		SPL_ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART);</div><div class='add'>+		return arg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (negative)</div><div class='add'>+		arg.value = -arg.value;</div><div class='add'>+	arg.value &amp;= (~0ULL) &lt;&lt; (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits);</div><div class='add'>+	if (negative)</div><div class='add'>+		arg.value = -arg.value;</div><div class='add'>+	return arg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value, unsigned int integer_bits, unsigned int fractional_bits);</div><div class='add'>+struct spl_fixed31_32 spl_fixpt_from_int_dy(unsigned int int_value,</div><div class='add'>+		unsigned int frac_value,</div><div class='add'>+		unsigned int integer_bits,</div><div class='add'>+		unsigned int fractional_bits);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h<br/>new file mode 100644<br/>index 000000000000..2e6ba71960ac<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h</a></div><div class='hunk'>@@ -0,0 +1,56 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+</div><div class='add'>+/* Copyright 2024 Advanced Micro Devices, Inc. */</div><div class='add'>+/* Copyright 2019 Raptor Engineering, LLC */</div><div class='add'>+</div><div class='add'>+#ifndef _SPL_OS_TYPES_H_</div><div class='add'>+#define _SPL_OS_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "spl_debug.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/kgdb.h&gt;</div><div class='add'>+#include &lt;linux/kref.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/mm.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ *</div><div class='add'>+ * general debug capabilities</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)</div><div class='add'>+{</div><div class='add'>+	return div_u64_rem(dividend, divisor, remainder);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline uint64_t spl_div_u64(uint64_t dividend, uint32_t divisor)</div><div class='add'>+{</div><div class='add'>+	return div_u64(dividend, divisor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline uint64_t spl_div64_u64(uint64_t dividend, uint64_t divisor)</div><div class='add'>+{</div><div class='add'>+	return div64_u64(dividend, divisor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline uint64_t spl_div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder)</div><div class='add'>+{</div><div class='add'>+	return div64_u64_rem(dividend, divisor, remainder);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int64_t spl_div64_s64(int64_t dividend, int64_t divisor)</div><div class='add'>+{</div><div class='add'>+	return div64_s64(dividend, divisor);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define spl_swap(a, b) \</div><div class='add'>+	do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)</div><div class='add'>+</div><div class='add'>+#ifndef spl_min</div><div class='add'>+#define spl_min(a, b)    (((a) &lt; (b)) ? (a):(b))</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#endif /* _SPL_OS_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h<br/>index 7785908a6676..9d0168986fe7 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/dmub_srv.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/dmub_srv.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/dmub_srv.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/dmub_srv.h</a></div><div class='hunk'>@@ -51,8 +51,8 @@</div><div class='ctx'>  * for the cache windows.</div><div class='ctx'>  *</div><div class='ctx'>  * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare</div><div class='del'>- * for command submission. Commands can be queued via dmub_srv_cmd_queue()</div><div class='del'>- * and executed via dmub_srv_cmd_execute().</div><div class='add'>+ * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue()</div><div class='add'>+ * and executed via dmub_srv_fb_cmd_execute().</div><div class='ctx'>  *</div><div class='ctx'>  * If the queue is full the dmub_srv_wait_for_idle() call can be used to</div><div class='ctx'>  * wait until the queue has been cleared.</div><div class='hunk'>@@ -67,9 +67,10 @@</div><div class='ctx'> #include "inc/dmub_cmd.h"</div><div class='ctx'> #include "dc/dc_types.h"</div><div class='ctx'> </div><div class='del'>-#if defined(__cplusplus)</div><div class='del'>-extern "C" {</div><div class='del'>-#endif</div><div class='add'>+#define DMUB_PC_SNAPSHOT_COUNT 10</div><div class='add'>+</div><div class='add'>+/* Default tracebuffer size if meta is absent. */</div><div class='add'>+#define DMUB_TRACE_BUFFER_SIZE (64 * 1024)</div><div class='ctx'> </div><div class='ctx'> /* Forward declarations */</div><div class='ctx'> struct dmub_srv;</div><div class='hunk'>@@ -113,6 +114,8 @@ enum dmub_asic {</div><div class='ctx'> 	DMUB_ASIC_DCN321,</div><div class='ctx'> 	DMUB_ASIC_DCN35,</div><div class='ctx'> 	DMUB_ASIC_DCN351,</div><div class='add'>+	DMUB_ASIC_DCN36,</div><div class='add'>+	DMUB_ASIC_DCN401,</div><div class='ctx'> 	DMUB_ASIC_MAX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -126,7 +129,10 @@ enum dmub_window_id {</div><div class='ctx'> 	DMUB_WINDOW_5_TRACEBUFF,</div><div class='ctx'> 	DMUB_WINDOW_6_FW_STATE,</div><div class='ctx'> 	DMUB_WINDOW_7_SCRATCH_MEM,</div><div class='add'>+	DMUB_WINDOW_IB_MEM,</div><div class='ctx'> 	DMUB_WINDOW_SHARED_STATE,</div><div class='add'>+	DMUB_WINDOW_LSDMA_BUFFER,</div><div class='add'>+	DMUB_WINDOW_CURSOR_OFFLOAD,</div><div class='ctx'> 	DMUB_WINDOW_TOTAL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -138,6 +144,8 @@ enum dmub_notification_type {</div><div class='ctx'> 	DMUB_NOTIFICATION_HPD_IRQ,</div><div class='ctx'> 	DMUB_NOTIFICATION_SET_CONFIG_REPLY,</div><div class='ctx'> 	DMUB_NOTIFICATION_DPIA_NOTIFICATION,</div><div class='add'>+	DMUB_NOTIFICATION_HPD_SENSE_NOTIFY,</div><div class='add'>+	DMUB_NOTIFICATION_FUSED_IO,</div><div class='ctx'> 	DMUB_NOTIFICATION_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -166,6 +174,13 @@ enum dmub_srv_power_state_type {</div><div class='ctx'> 	DMUB_POWER_STATE_D3 = 8</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* enum dmub_inbox_cmd_interface type - defines default interface for host-&gt;dmub commands */</div><div class='add'>+enum dmub_inbox_cmd_interface_type {</div><div class='add'>+	DMUB_CMD_INTERFACE_DEFAULT = 0,</div><div class='add'>+	DMUB_CMD_INTERFACE_FB = 1,</div><div class='add'>+	DMUB_CMD_INTERFACE_REG = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct dmub_region - dmub hw memory region</div><div class='ctx'>  * @base: base address for region, must be 256 byte aligned</div><div class='hunk'>@@ -295,8 +310,26 @@ struct dmub_srv_hw_params {</div><div class='ctx'> 	bool dpia_hpd_int_enable_supported;</div><div class='ctx'> 	bool disable_clock_gate;</div><div class='ctx'> 	bool disallow_dispclk_dppclk_ds;</div><div class='add'>+	bool ips_sequential_ono;</div><div class='ctx'> 	enum dmub_memory_access_type mem_access_type;</div><div class='ctx'> 	enum dmub_ips_disable_type disable_ips;</div><div class='add'>+	bool disallow_phy_access;</div><div class='add'>+	bool disable_sldo_opt;</div><div class='add'>+	bool enable_non_transparent_setconfig;</div><div class='add'>+	bool lower_hbr3_phy_ssc;</div><div class='add'>+	bool override_hbr3_pll_vco;</div><div class='add'>+	bool disable_dpia_bw_allocation;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_srv_debug - Debug info for dmub_srv</div><div class='add'>+ * @timeout_occured: Indicates a timeout occured on any message from driver to dmub</div><div class='add'>+ * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored</div><div class='add'>+ */</div><div class='add'>+struct dmub_timeout_info {</div><div class='add'>+	bool timeout_occured;</div><div class='add'>+	union dmub_rb_cmd timeout_cmd;</div><div class='add'>+	unsigned long long timestamp;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -306,7 +339,7 @@ struct dmub_srv_hw_params {</div><div class='ctx'> struct dmub_diagnostic_data {</div><div class='ctx'> 	uint32_t dmcub_version;</div><div class='ctx'> 	uint32_t scratch[17];</div><div class='del'>-	uint32_t pc;</div><div class='add'>+	uint32_t pc[DMUB_PC_SNAPSHOT_COUNT];</div><div class='ctx'> 	uint32_t undefined_address_fault_addr;</div><div class='ctx'> 	uint32_t inst_fetch_fault_addr;</div><div class='ctx'> 	uint32_t data_write_fault_addr;</div><div class='hunk'>@@ -316,13 +349,46 @@ struct dmub_diagnostic_data {</div><div class='ctx'> 	uint32_t inbox0_rptr;</div><div class='ctx'> 	uint32_t inbox0_wptr;</div><div class='ctx'> 	uint32_t inbox0_size;</div><div class='add'>+	uint32_t outbox1_rptr;</div><div class='add'>+	uint32_t outbox1_wptr;</div><div class='add'>+	uint32_t outbox1_size;</div><div class='ctx'> 	uint32_t gpint_datain0;</div><div class='add'>+	struct dmub_timeout_info timeout_info;</div><div class='ctx'> 	uint8_t is_dmcub_enabled : 1;</div><div class='ctx'> 	uint8_t is_dmcub_soft_reset : 1;</div><div class='ctx'> 	uint8_t is_dmcub_secure_reset : 1;</div><div class='ctx'> 	uint8_t is_traceport_en : 1;</div><div class='ctx'> 	uint8_t is_cw0_enabled : 1;</div><div class='ctx'> 	uint8_t is_cw6_enabled : 1;</div><div class='add'>+	uint8_t is_pwait : 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_preos_info - preos fw info before loading post os fw.</div><div class='add'>+ */</div><div class='add'>+struct dmub_preos_info {</div><div class='add'>+	uint64_t fb_base;</div><div class='add'>+	uint64_t fb_offset;</div><div class='add'>+	uint64_t trace_buffer_phy_addr;</div><div class='add'>+	uint32_t trace_buffer_size;</div><div class='add'>+	uint32_t fw_version;</div><div class='add'>+	uint32_t boot_status;</div><div class='add'>+	uint32_t boot_options;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_srv_inbox {</div><div class='add'>+	/* generic status */</div><div class='add'>+	uint64_t num_submitted;</div><div class='add'>+	uint64_t num_reported;</div><div class='add'>+	union {</div><div class='add'>+		/* frame buffer mailbox status */</div><div class='add'>+		struct dmub_rb rb;</div><div class='add'>+		/* register mailbox status */</div><div class='add'>+		struct {</div><div class='add'>+			bool is_pending;</div><div class='add'>+			bool is_multi_pending;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -398,6 +464,8 @@ struct dmub_srv_hw_funcs {</div><div class='ctx'> </div><div class='ctx'> 	uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='add'>+	uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='ctx'> 	void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);</div><div class='ctx'> </div><div class='ctx'> 	bool (*is_supported)(struct dmub_srv *dmub);</div><div class='hunk'>@@ -432,12 +500,29 @@ struct dmub_srv_hw_funcs {</div><div class='ctx'> 	void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);</div><div class='ctx'> 	uint32_t (*get_current_time)(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='del'>-	void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);</div><div class='add'>+	void (*get_diagnostic_data)(struct dmub_srv *dmub);</div><div class='add'>+	bool (*get_preos_fw_info)(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> 	bool (*should_detect)(struct dmub_srv *dmub);</div><div class='ctx'> 	void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);</div><div class='ctx'> </div><div class='ctx'> 	void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);</div><div class='add'>+</div><div class='add'>+	void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub,</div><div class='add'>+			union dmub_rb_cmd *cmd);</div><div class='add'>+	uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub);</div><div class='add'>+	void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub,</div><div class='add'>+			union dmub_rb_cmd *cmd);</div><div class='add'>+	void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);</div><div class='add'>+	void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);</div><div class='add'>+	void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);</div><div class='add'>+</div><div class='add'>+	uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub);</div><div class='add'>+	void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub);</div><div class='add'>+	void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg);</div><div class='add'>+	void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp);</div><div class='add'>+	uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub);</div><div class='add'>+	void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -456,6 +541,7 @@ struct dmub_srv_create_params {</div><div class='ctx'> 	enum dmub_asic asic;</div><div class='ctx'> 	uint32_t fw_version;</div><div class='ctx'> 	bool is_virtual;</div><div class='add'>+	enum dmub_inbox_cmd_interface_type inbox_type;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -465,7 +551,8 @@ struct dmub_srv_create_params {</div><div class='ctx'>  * @fw_version: the current firmware version, if any</div><div class='ctx'>  * @is_virtual: false if hardware support only</div><div class='ctx'>  * @shared_state: dmub shared state between firmware and driver</div><div class='del'>- * @fw_state: dmub firmware state pointer</div><div class='add'>+ * @cursor_offload_v1: Cursor offload state</div><div class='add'>+ * @fw_state: dmub firmware state pointer (debug purpose only)</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_srv {</div><div class='ctx'> 	enum dmub_asic asic;</div><div class='hunk'>@@ -473,7 +560,10 @@ struct dmub_srv {</div><div class='ctx'> 	uint32_t fw_version;</div><div class='ctx'> 	bool is_virtual;</div><div class='ctx'> 	struct dmub_fb scratch_mem_fb;</div><div class='add'>+	struct dmub_fb ib_mem_gart;</div><div class='add'>+	struct dmub_fb cursor_offload_fb;</div><div class='ctx'> 	volatile struct dmub_shared_state_feature_block *shared_state;</div><div class='add'>+	volatile struct dmub_cursor_offload_v1 *cursor_offload_v1;</div><div class='ctx'> 	volatile const struct dmub_fw_state *fw_state;</div><div class='ctx'> </div><div class='ctx'> 	/* private: internal use only */</div><div class='hunk'>@@ -481,11 +571,12 @@ struct dmub_srv {</div><div class='ctx'> 	const struct dmub_srv_dcn31_regs *regs_dcn31;</div><div class='ctx'> 	struct dmub_srv_dcn32_regs *regs_dcn32;</div><div class='ctx'> 	struct dmub_srv_dcn35_regs *regs_dcn35;</div><div class='del'>-</div><div class='add'>+	const struct dmub_srv_dcn401_regs *regs_dcn401;</div><div class='ctx'> 	struct dmub_srv_base_funcs funcs;</div><div class='ctx'> 	struct dmub_srv_hw_funcs hw_funcs;</div><div class='del'>-	struct dmub_rb inbox1_rb;</div><div class='add'>+	struct dmub_srv_inbox inbox1;</div><div class='ctx'> 	uint32_t inbox1_last_wptr;</div><div class='add'>+	struct dmub_srv_inbox reg_inbox0;</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * outbox1_rb is accessed without locks (dal &amp; dc)</div><div class='ctx'> 	 * and to be used only in dmub_srv_stat_get_notification()</div><div class='hunk'>@@ -496,16 +587,22 @@ struct dmub_srv {</div><div class='ctx'> </div><div class='ctx'> 	bool sw_init;</div><div class='ctx'> 	bool hw_init;</div><div class='add'>+	bool dpia_supported;</div><div class='ctx'> </div><div class='ctx'> 	uint64_t fb_base;</div><div class='ctx'> 	uint64_t fb_offset;</div><div class='ctx'> 	uint32_t psp_version;</div><div class='ctx'> </div><div class='ctx'> 	/* Feature capabilities reported by fw */</div><div class='add'>+	struct dmub_fw_meta_info meta_info;</div><div class='ctx'> 	struct dmub_feature_caps feature_caps;</div><div class='ctx'> 	struct dmub_visual_confirm_color visual_confirm_color;</div><div class='add'>+	enum dmub_inbox_cmd_interface_type inbox_type;</div><div class='ctx'> </div><div class='ctx'> 	enum dmub_srv_power_state_type power_state;</div><div class='add'>+	struct dmub_diagnostic_data debug;</div><div class='add'>+	struct dmub_fb lsdma_rb_fb;</div><div class='add'>+	struct dmub_preos_info preos_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -522,15 +619,15 @@ struct dmub_notification {</div><div class='ctx'> 	enum dmub_notification_type type;</div><div class='ctx'> 	uint8_t link_index;</div><div class='ctx'> 	uint8_t result;</div><div class='add'>+	/* notify instance from DMUB */</div><div class='add'>+	uint8_t instance;</div><div class='ctx'> 	bool pending_notification;</div><div class='ctx'> 	union {</div><div class='ctx'> 		struct aux_reply_data aux_reply;</div><div class='ctx'> 		enum dp_hpd_status hpd_status;</div><div class='ctx'> 		enum set_config_status sc_status;</div><div class='del'>-		/**</div><div class='del'>-		 * DPIA notification command.</div><div class='del'>-		 */</div><div class='del'>-		struct dmub_rb_cmd_dpia_notification dpia_notification;</div><div class='add'>+		struct dmub_rb_cmd_hpd_sense_notify_data hpd_sense_notify;</div><div class='add'>+		struct dmub_cmd_fused_request fused_request;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -651,19 +748,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * dmub_srv_sync_inbox1() - sync sw state with hw state</div><div class='del'>- * @dmub: the dmub service</div><div class='del'>- *</div><div class='del'>- * Sync sw state with hw state when resume from S0i3</div><div class='del'>- *</div><div class='del'>- * Return:</div><div class='del'>- *   DMUB_STATUS_OK - success</div><div class='del'>- *   DMUB_STATUS_INVALID - unspecified error</div><div class='del'>- */</div><div class='del'>-enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dmub_srv_cmd_queue() - queues a command to the DMUB</div><div class='add'>+ * dmub_srv_fb_cmd_queue() - queues a command to the DMUB</div><div class='ctx'>  * @dmub: the dmub service</div><div class='ctx'>  * @cmd: the command to queue</div><div class='ctx'>  *</div><div class='hunk'>@@ -675,11 +760,11 @@ enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub);</div><div class='ctx'>  *   DMUB_STATUS_QUEUE_FULL - no remaining room in queue</div><div class='ctx'>  *   DMUB_STATUS_INVALID - unspecified error</div><div class='ctx'>  */</div><div class='del'>-enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,</div><div class='add'>+enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,</div><div class='ctx'> 				    const union dmub_rb_cmd *cmd);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * dmub_srv_cmd_execute() - Executes a queued sequence to the dmub</div><div class='add'>+ * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub</div><div class='ctx'>  * @dmub: the dmub service</div><div class='ctx'>  *</div><div class='ctx'>  * Begins execution of queued commands on the dmub.</div><div class='hunk'>@@ -688,7 +773,7 @@ enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,</div><div class='ctx'>  *   DMUB_STATUS_OK - success</div><div class='ctx'>  *   DMUB_STATUS_INVALID - unspecified error</div><div class='ctx'>  */</div><div class='del'>-enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub);</div><div class='add'>+enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed</div><div class='hunk'>@@ -747,6 +832,23 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,</div><div class='ctx'> 					    uint32_t timeout_us);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ * @timeout_us: the maximum number of microseconds to wait</div><div class='add'>+ *</div><div class='add'>+ * Waits until the commands queued prior to this call are complete.</div><div class='add'>+ * If interfaces remain busy due to additional work being submitted</div><div class='add'>+ * concurrently, this function will not continue to wait.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   DMUB_STATUS_OK - success</div><div class='add'>+ *   DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out</div><div class='add'>+ *   DMUB_STATUS_INVALID - unspecified error</div><div class='add'>+ */</div><div class='add'>+enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,</div><div class='add'>+					uint32_t timeout_us);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle</div><div class='ctx'>  * @dmub: the dmub service</div><div class='ctx'>  * @timeout_us: the maximum number of microseconds to wait</div><div class='hunk'>@@ -844,15 +946,12 @@ enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,</div><div class='ctx'> enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,</div><div class='ctx'> 					     union dmub_fw_boot_options *option);</div><div class='ctx'> </div><div class='del'>-enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,</div><div class='del'>-					      union dmub_rb_cmd *cmd);</div><div class='del'>-</div><div class='ctx'> enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,</div><div class='ctx'> 					     bool skip);</div><div class='ctx'> </div><div class='ctx'> bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);</div><div class='ctx'> </div><div class='del'>-bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);</div><div class='add'>+bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> bool dmub_srv_should_detect(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='hunk'>@@ -922,8 +1021,81 @@ void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_</div><div class='ctx'>  */</div><div class='ctx'> void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state);</div><div class='ctx'> </div><div class='del'>-#if defined(__cplusplus)</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ * @cmd: the command packet to be executed</div><div class='add'>+ *</div><div class='add'>+ * Executes a single command for the dmub.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   DMUB_STATUS_OK - success</div><div class='add'>+ *   DMUB_STATUS_INVALID - unspecified error</div><div class='add'>+ */</div><div class='add'>+enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_cmd_get_response() - Copies return data for command into buffer</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ * @cmd_rsp: response buffer</div><div class='add'>+ *</div><div class='add'>+ * Copies return data for command into buffer</div><div class='add'>+ */</div><div class='add'>+void dmub_srv_cmd_get_response(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_rb_cmd *cmd_rsp);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_sync_inboxes() - Sync inbox state</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ *</div><div class='add'>+ * Sync inbox state</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   DMUB_STATUS_OK - success</div><div class='add'>+ *   DMUB_STATUS_INVALID - unspecified error</div><div class='add'>+ */</div><div class='add'>+enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ * @timeout_us: the maximum number of microseconds to wait</div><div class='add'>+ * @num_free_required: number of free entries required</div><div class='add'>+ *</div><div class='add'>+ * Waits until the DMUB buffer is freed to the specified number.</div><div class='add'>+ *  The maximum wait time is given in microseconds to prevent spinning</div><div class='add'>+ * forever.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   DMUB_STATUS_OK - success</div><div class='add'>+ *   DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out</div><div class='add'>+ *   DMUB_STATUS_INVALID - unspecified error</div><div class='add'>+ */</div><div class='add'>+enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,</div><div class='add'>+		uint32_t timeout_us,</div><div class='add'>+		uint32_t num_free_required);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_update_inbox_status() - Updates pending status for inbox &amp; reg inbox0</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   DMUB_STATUS_OK - success</div><div class='add'>+ *   DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out</div><div class='add'>+ *   DMUB_STATUS_HW_FAILURE - issue with HW programming</div><div class='add'>+ *   DMUB_STATUS_INVALID - unspecified error</div><div class='add'>+ */</div><div class='add'>+enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_get_preos_info() - retrieves preos fw info</div><div class='add'>+ * @dmub: the dmub service</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   true - preos fw info retrieved successfully</div><div class='add'>+ *   false - preos fw info not retrieved successfully</div><div class='add'>+ */</div><div class='add'>+bool dmub_srv_get_preos_info(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> #endif /* _DMUB_SRV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h<br/>index af3fe8bb0728..3f2a0ed02c59 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h</a></div><div class='hunk'>@@ -36,6 +36,9 @@</div><div class='ctx'> //&lt;DMUB_TYPES&gt;==================================================================</div><div class='ctx'> /* Basic type definitions. */</div><div class='ctx'> </div><div class='add'>+#ifdef __forceinline</div><div class='add'>+#undef __forceinline</div><div class='add'>+#endif</div><div class='ctx'> #define __forceinline inline</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -81,6 +84,16 @@</div><div class='ctx'>  */</div><div class='ctx'> #define NUM_BL_CURVE_SEGS               16</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * Maximum number of segments in ABM ACE curve.</div><div class='add'>+ */</div><div class='add'>+#define ABM_MAX_NUM_OF_ACE_SEGMENTS         64</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Maximum number of bins in ABM histogram.</div><div class='add'>+ */</div><div class='add'>+#define ABM_MAX_NUM_OF_HG_BINS              64</div><div class='add'>+</div><div class='ctx'> /* Maximum number of SubVP streams */</div><div class='ctx'> #define DMUB_MAX_SUBVP_STREAMS 2</div><div class='ctx'> </div><div class='hunk'>@@ -91,14 +104,25 @@</div><div class='ctx'>  */</div><div class='ctx'> #define DMUB_MAX_FPO_STREAMS 4</div><div class='ctx'> </div><div class='add'>+/* Define to ensure that the "common" members always appear in the same</div><div class='add'>+ * order in different structs for back compat purposes</div><div class='add'>+ */</div><div class='add'>+#define COMMON_STREAM_STATIC_SUB_STATE \</div><div class='add'>+    struct dmub_fams2_cmd_legacy_stream_static_state legacy; \</div><div class='add'>+    struct dmub_fams2_cmd_subvp_stream_static_state subvp; \</div><div class='add'>+    struct dmub_fams2_cmd_drr_stream_static_state drr;</div><div class='add'>+</div><div class='ctx'> /* Maximum number of streams on any ASIC. */</div><div class='ctx'> #define DMUB_MAX_STREAMS 6</div><div class='ctx'> </div><div class='ctx'> /* Maximum number of planes on any ASIC. */</div><div class='ctx'> #define DMUB_MAX_PLANES 6</div><div class='ctx'> </div><div class='add'>+/* Maximum number of phantom planes on any ASIC */</div><div class='add'>+#define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)</div><div class='add'>+</div><div class='ctx'> /* Trace buffer offset for entry */</div><div class='del'>-#define TRACE_BUFFER_ENTRY_OFFSET  16</div><div class='add'>+#define TRACE_BUFFER_ENTRY_OFFSET 16</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * Maximum number of dirty rects supported by FW.</div><div class='hunk'>@@ -147,8 +171,11 @@</div><div class='ctx'> #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-#if defined(__cplusplus)</div><div class='del'>-extern "C" {</div><div class='add'>+/**</div><div class='add'>+ * OS/FW agnostic memcmp</div><div class='add'>+ */</div><div class='add'>+#ifndef dmub_memcmp</div><div class='add'>+#define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes))</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -161,6 +188,11 @@ extern "C" {</div><div class='ctx'> #pragma pack(push, 1)</div><div class='ctx'> #define ABM_NUM_OF_ACE_SEGMENTS         5</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * Debug FW state offset</div><div class='add'>+ */</div><div class='add'>+#define DMUB_DEBUG_FW_STATE_OFFSET 0x300</div><div class='add'>+</div><div class='ctx'> union abm_flags {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		/**</div><div class='hunk'>@@ -194,6 +226,16 @@ union abm_flags {</div><div class='ctx'> 		 * of user backlight level.</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned int abm_gradual_bl_change : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady</div><div class='add'>+		 */</div><div class='add'>+		unsigned int abm_new_frame : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @vb_scaling_enabled: Indicates variBright Scaling Enable</div><div class='add'>+		 */</div><div class='add'>+		unsigned int vb_scaling_enabled : 1;</div><div class='ctx'> 	} bitfields;</div><div class='ctx'> </div><div class='ctx'> 	unsigned int u32All;</div><div class='hunk'>@@ -257,6 +299,31 @@ union dmub_addr {</div><div class='ctx'> 	} u; /*&lt;&lt; Low/high bit access */</div><div class='ctx'> 	uint64_t quad_part; /*&lt;&lt; 64 bit address */</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+/* Flattened structure containing SOC BB parameters stored in the VBIOS</div><div class='add'>+ * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters.</div><div class='add'>+ * This also prevents alighment issues when new parameters are added to the SoC BB.</div><div class='add'>+ * The following parameters should be added since these values can't be obtained elsewhere:</div><div class='add'>+ * -dml2_soc_power_management_parameters</div><div class='add'>+ * -dml2_soc_vmin_clock_limits</div><div class='add'>+ */</div><div class='add'>+struct dmub_soc_bb_params {</div><div class='add'>+	uint32_t dram_clk_change_blackout_ns;</div><div class='add'>+	uint32_t dram_clk_change_read_only_ns;</div><div class='add'>+	uint32_t dram_clk_change_write_only_ns;</div><div class='add'>+	uint32_t fclk_change_blackout_ns;</div><div class='add'>+	uint32_t g7_ppt_blackout_ns;</div><div class='add'>+	uint32_t stutter_enter_plus_exit_latency_ns;</div><div class='add'>+	uint32_t stutter_exit_latency_ns;</div><div class='add'>+	uint32_t z8_stutter_enter_plus_exit_latency_ns;</div><div class='add'>+	uint32_t z8_stutter_exit_latency_ns;</div><div class='add'>+	uint32_t z8_min_idle_time_ns;</div><div class='add'>+	uint32_t type_b_dram_clk_change_blackout_ns;</div><div class='add'>+	uint32_t type_b_ppt_blackout_ns;</div><div class='add'>+	uint32_t vmin_limit_dispclk_khz;</div><div class='add'>+	uint32_t vmin_limit_dcfclk_khz;</div><div class='add'>+	uint32_t g7_temperature_read_blackout_ns;</div><div class='add'>+};</div><div class='ctx'> #pragma pack(pop)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -317,6 +384,10 @@ union dmub_psr_debug_flags {</div><div class='ctx'> 		 */</div><div class='ctx'> 		uint32_t back_to_back_flip : 1;</div><div class='ctx'> </div><div class='add'>+		/**</div><div class='add'>+		 * Enable visual confirm for IPS</div><div class='add'>+		 */</div><div class='add'>+		uint32_t enable_ips_visual_confirm : 1;</div><div class='ctx'> 	} bitfields;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='hunk'>@@ -403,7 +474,80 @@ union replay_debug_flags {</div><div class='ctx'> 		 */</div><div class='ctx'> 		uint32_t enable_ips_residency_profiling : 1;</div><div class='ctx'> </div><div class='del'>-		uint32_t reserved : 20;</div><div class='add'>+		/**</div><div class='add'>+		 * 0x1000 (bit 12)</div><div class='add'>+		 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check</div><div class='add'>+		 */</div><div class='add'>+		uint32_t enable_coasting_vtotal_check : 1;</div><div class='add'>+		/**</div><div class='add'>+		 * 0x2000 (bit 13)</div><div class='add'>+		 * @enable_visual_confirm_debug: Enable Visual Confirm Debug</div><div class='add'>+		 */</div><div class='add'>+		uint32_t enable_visual_confirm_debug : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x4000 (bit 14)</div><div class='add'>+		 * @debug_log_enabled: Debug Log Enabled</div><div class='add'>+		 */</div><div class='add'>+		uint32_t debug_log_enabled : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x8000 (bit 15)</div><div class='add'>+		 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm</div><div class='add'>+		 */</div><div class='add'>+		uint32_t enable_sub_feature_visual_confirm : 1;</div><div class='add'>+</div><div class='add'>+		uint32_t reserved : 16;</div><div class='add'>+	} bitfields;</div><div class='add'>+</div><div class='add'>+	uint32_t u32All;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Flags record error state.</div><div class='add'>+ */</div><div class='add'>+union replay_visual_confirm_error_state_flags {</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * 0x1 (bit 0) - Desync Error flag.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t desync_error : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x2 (bit 1) - State Transition Error flag.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t state_transition_error : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x4 (bit 2) - Crc Error flag</div><div class='add'>+		 */</div><div class='add'>+		uint32_t crc_error : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x8 (bit 3) - Reserved</div><div class='add'>+		 */</div><div class='add'>+		uint32_t reserved_3 : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --&gt; use debug flag to control DPCD write.</div><div class='add'>+		 * Added new debug flag to control DPCD.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t incorrect_vtotal_in_static_screen : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x20 (bit 5) - No doubled Refresh Rate.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t no_double_rr : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * Reserved bit 6-7</div><div class='add'>+		 */</div><div class='add'>+		uint32_t reserved_6_7 : 2;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * Reserved bit 9-31</div><div class='add'>+		 */</div><div class='add'>+		uint32_t reserved_9_31 : 24;</div><div class='ctx'> 	} bitfields;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t u32All;</div><div class='hunk'>@@ -447,12 +591,127 @@ union replay_hw_flags {</div><div class='ctx'> 		 * Use TPS3 signal when restore main link.</div><div class='ctx'> 		 */</div><div class='ctx'> 		uint32_t force_wakeup_by_tps3 : 1;</div><div class='add'>+		/**</div><div class='add'>+		 * @is_alpm_initialized: Indicates whether ALPM is initialized</div><div class='add'>+		 */</div><div class='add'>+		uint32_t is_alpm_initialized : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @alpm_mode: Indicates ALPM mode selected</div><div class='add'>+		 */</div><div class='add'>+		uint32_t alpm_mode : 2;</div><div class='ctx'> 	} bitfields;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t u32All;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Flags that can be set by driver to change some Panel Replay behaviour.</div><div class='add'>+ */</div><div class='add'>+union pr_debug_flags {</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * 0x1 (bit 0)</div><div class='add'>+		 * Enable visual confirm in FW.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t visual_confirm : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x2 (bit 1)</div><div class='add'>+		 * @skip_crc: Set if need to skip CRC.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t skip_crc : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x4 (bit 2)</div><div class='add'>+		 * @force_link_power_on: Force disable ALPM control</div><div class='add'>+		 */</div><div class='add'>+		uint32_t force_link_power_on : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x8 (bit 3)</div><div class='add'>+		 * @force_phy_power_on: Force phy power on</div><div class='add'>+		 */</div><div class='add'>+		uint32_t force_phy_power_on : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * 0x10 (bit 4)</div><div class='add'>+		 * @skip_crtc_disabled: CRTC disable skipped</div><div class='add'>+		 */</div><div class='add'>+		uint32_t skip_crtc_disabled : 1;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 0x20 (bit 5)</div><div class='add'>+		 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection</div><div class='add'>+		 */</div><div class='add'>+		uint32_t visual_confirm_rate_control : 1;</div><div class='add'>+</div><div class='add'>+		uint32_t reserved : 26;</div><div class='add'>+	} bitfields;</div><div class='add'>+</div><div class='add'>+	uint32_t u32All;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union pr_hw_flags {</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * @allow_alpm_fw_standby_mode: To indicate whether the</div><div class='add'>+		 * ALPM FW standby mode is allowed</div><div class='add'>+		 */</div><div class='add'>+		uint32_t allow_alpm_fw_standby_mode : 1;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * @dsc_enable_status: DSC enable status in driver</div><div class='add'>+		 */</div><div class='add'>+		uint32_t dsc_enable_status : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @fec_enable_status: receive fec enable/disable status from driver</div><div class='add'>+		 */</div><div class='add'>+		uint32_t fec_enable_status : 1;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * @smu_optimizations_en: SMU power optimization.</div><div class='add'>+		 * Only when active display is Replay capable and display enters Replay.</div><div class='add'>+		 * Trigger interrupt to SMU to powerup/down.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t smu_optimizations_en : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @phy_power_state: Indicates current phy power state</div><div class='add'>+		 */</div><div class='add'>+		uint32_t phy_power_state : 1;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @link_power_state: Indicates current link power state</div><div class='add'>+		 */</div><div class='add'>+		uint32_t link_power_state : 1;</div><div class='add'>+		/**</div><div class='add'>+		 * Use TPS3 signal when restore main link.</div><div class='add'>+		 */</div><div class='add'>+		uint32_t force_wakeup_by_tps3 : 1;</div><div class='add'>+		/**</div><div class='add'>+		 * @is_alpm_initialized: Indicates whether ALPM is initialized</div><div class='add'>+		 */</div><div class='add'>+		uint32_t is_alpm_initialized : 1;</div><div class='add'>+		/**</div><div class='add'>+		 * @alpm_mode: Indicates ALPM mode selected</div><div class='add'>+		 */</div><div class='add'>+		uint32_t alpm_mode : 2;</div><div class='add'>+	} bitfields;</div><div class='add'>+</div><div class='add'>+	uint32_t u32All;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union fw_assisted_mclk_switch_version {</div><div class='add'>+	struct {</div><div class='add'>+		uint8_t minor : 5;</div><div class='add'>+		uint8_t major : 3;</div><div class='add'>+	};</div><div class='add'>+	uint8_t ver;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DMUB feature capabilities.</div><div class='ctx'>  * After DMUB init, driver will query FW capabilities prior to enabling certain features.</div><div class='ctx'>  */</div><div class='hunk'>@@ -461,12 +720,14 @@ struct dmub_feature_caps {</div><div class='ctx'> 	 * Max PSR version supported by FW.</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint8_t psr;</div><div class='del'>-	uint8_t fw_assisted_mclk_switch;</div><div class='add'>+	uint8_t fw_assisted_mclk_switch_ver;</div><div class='ctx'> 	uint8_t reserved[4];</div><div class='ctx'> 	uint8_t subvp_psr_support;</div><div class='ctx'> 	uint8_t gecc_enable;</div><div class='ctx'> 	uint8_t replay_supported;</div><div class='ctx'> 	uint8_t replay_reserved[3];</div><div class='add'>+	uint8_t abm_aux_backlight_support;</div><div class='add'>+	uint8_t lsdma_support_in_dmu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dmub_visual_confirm_color {</div><div class='hunk'>@@ -479,9 +740,111 @@ struct dmub_visual_confirm_color {</div><div class='ctx'> 	uint16_t panel_inst;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#if defined(__cplusplus)</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cursor_offload_pipe_data_dcn30_v1 {</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;</div><div class='add'>+	uint32_t reserved0[4];</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16;</div><div class='add'>+	uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16;</div><div class='add'>+	uint32_t reserved1[5];</div><div class='add'>+	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;</div><div class='add'>+	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;</div><div class='add'>+	uint32_t reserved2[3];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cursor_offload_pipe_data_dcn401_v1 {</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;</div><div class='add'>+	uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;</div><div class='add'>+	uint32_t reserved0[4];</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16;</div><div class='add'>+	uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16;</div><div class='add'>+	uint32_t reserved1[4];</div><div class='add'>+	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;</div><div class='add'>+	uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;</div><div class='add'>+	uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1;</div><div class='add'>+	uint32_t reserved2[3];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cursor_offload_pipe_data_v1 {</div><div class='add'>+	union {</div><div class='add'>+		struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**&lt; DCN30 cursor data. */</div><div class='add'>+		struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**&lt; DCN401 cursor data. */</div><div class='add'>+		uint8_t payload[96]; /**&lt; Guarantees the cursor pipe data size per-pipe. */</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cursor_offload_payload_data_v1 {</div><div class='add'>+	uint32_t write_idx_start; /**&lt; Write index, updated before pipe_data is written. */</div><div class='add'>+	uint32_t write_idx_finish; /**&lt; Write index, updated after pipe_data is written. */</div><div class='add'>+	uint32_t pipe_mask; /**&lt; Mask of pipes to update. */</div><div class='add'>+	uint32_t reserved; /**&lt; Reserved for future use. */</div><div class='add'>+	struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**&lt; Per-pipe cursor data. */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cursor_offload_stream_v1 {</div><div class='add'>+	struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**&lt; A small buffer of cursor payloads. */</div><div class='add'>+	uint32_t write_idx; /**&lt; The index of the last written payload. */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cursor_offload_v1 - Cursor offload feature state.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cursor_offload_v1 {</div><div class='add'>+	struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**&lt; Per-stream cursor offload data */</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> //==============================================================================</div><div class='ctx'> //&lt;/DMUB_TYPES&gt;=================================================================</div><div class='hunk'>@@ -497,6 +860,18 @@ struct dmub_visual_confirm_color {</div><div class='ctx'> #define DMUB_FW_META_OFFSET 0x24</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization</div><div class='add'>+ */</div><div class='add'>+union dmub_fw_meta_feature_bits {</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t shared_state_link_detection : 1; /**&lt; 1 supports link detection via shared state */</div><div class='add'>+		uint32_t cursor_offload_v1_support: 1; /**&lt; 1 supports cursor offload */</div><div class='add'>+		uint32_t reserved : 30;</div><div class='add'>+	} bits; /**&lt; status bits */</div><div class='add'>+	uint32_t all; /**&lt; 32-bit access to status bits */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * struct dmub_fw_meta_info - metadata associated with fw binary</div><div class='ctx'>  *</div><div class='ctx'>  * NOTE: This should be considered a stable API. Fields should</div><div class='hunk'>@@ -521,6 +896,7 @@ struct dmub_fw_meta_info {</div><div class='ctx'> 	uint32_t shared_state_size; /**&lt; size of the shared state region in bytes */</div><div class='ctx'> 	uint16_t shared_state_features; /**&lt; number of shared state features */</div><div class='ctx'> 	uint16_t reserved2; /**&lt; padding bytes */</div><div class='add'>+	union dmub_fw_meta_feature_bits feature_bits; /**&lt; static feature bits */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -536,6 +912,7 @@ union dmub_fw_meta {</div><div class='ctx'> //==============================================================================</div><div class='ctx'> //&lt; DMUB Trace Buffer&gt;================================================================</div><div class='ctx'> //==============================================================================</div><div class='add'>+#if !defined(TENSILICA) &amp;&amp; !defined(DMUB_TRACE_ENTRY_DEFINED)</div><div class='ctx'> /**</div><div class='ctx'>  * dmub_trace_code_t - firmware trace code, 32-bits</div><div class='ctx'>  */</div><div class='hunk'>@@ -550,6 +927,7 @@ struct dmcub_trace_buf_entry {</div><div class='ctx'> 	uint32_t param0; /**&lt; trace defined parameter 0 */</div><div class='ctx'> 	uint32_t param1; /**&lt; trace defined parameter 1 */</div><div class='ctx'> };</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> //==============================================================================</div><div class='ctx'> //&lt; DMUB_STATUS&gt;================================================================</div><div class='hunk'>@@ -619,6 +997,22 @@ enum dmub_ips_disable_type {</div><div class='ctx'> 	DMUB_IPS_DISABLE_IPS2 = 3,</div><div class='ctx'> 	DMUB_IPS_DISABLE_IPS2_Z10 = 4,</div><div class='ctx'> 	DMUB_IPS_DISABLE_DYNAMIC = 5,</div><div class='add'>+	DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,</div><div class='add'>+	DMUB_IPS_DISABLE_Z8_RETENTION = 7,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dmub_ips_rcg_disable_type {</div><div class='add'>+	DMUB_IPS_RCG_ENABLE = 0,</div><div class='add'>+	DMUB_IPS0_RCG_DISABLE = 1,</div><div class='add'>+	DMUB_IPS1_RCG_DISABLE = 2,</div><div class='add'>+	DMUB_IPS_RCG_DISABLE = 3</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dmub_ips_in_vpb_disable_type {</div><div class='add'>+	DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour</div><div class='add'>+	DMUB_IPS_VPB_DISABLE_ALL = 1,</div><div class='add'>+	DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2,</div><div class='add'>+	DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define DMUB_IPS1_ALLOW_MASK 0x00000001</div><div class='hunk'>@@ -626,6 +1020,39 @@ enum dmub_ips_disable_type {</div><div class='ctx'> #define DMUB_IPS1_COMMIT_MASK 0x00000004</div><div class='ctx'> #define DMUB_IPS2_COMMIT_MASK 0x00000008</div><div class='ctx'> </div><div class='add'>+enum dmub_ips_comand_type {</div><div class='add'>+	/**</div><div class='add'>+	 * Start/stop IPS residency measurements for a given IPS mode</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__IPS_RESIDENCY_CNTL = 0,</div><div class='add'>+	/**</div><div class='add'>+	 * Query IPS residency information for a given IPS mode</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * enum dmub_cursor_offload_comand_type - Cursor offload subcommands.</div><div class='add'>+ */</div><div class='add'>+enum dmub_cursor_offload_comand_type {</div><div class='add'>+	/**</div><div class='add'>+	 * Initializes the cursor offload feature.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__CURSOR_OFFLOAD_INIT = 0,</div><div class='add'>+	/**</div><div class='add'>+	 * Enables cursor offloading for a stream and updates the timing parameters.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1,</div><div class='add'>+	/**</div><div class='add'>+	 * Disables cursor offloading for a given stream.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2,</div><div class='add'>+	/**</div><div class='add'>+	 * Programs the latest data for a given stream.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * union dmub_fw_boot_options - Boot option definitions for SCRATCH14</div><div class='ctx'>  */</div><div class='hunk'>@@ -648,12 +1075,17 @@ union dmub_fw_boot_options {</div><div class='ctx'> 		uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/</div><div class='ctx'> 		uint32_t usb4_cm_version: 1; /**&lt; 1 CM support */</div><div class='ctx'> 		uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */</div><div class='del'>-		uint32_t reserved0: 1;</div><div class='add'>+		uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/</div><div class='ctx'> 		uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/</div><div class='ctx'> 		uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */</div><div class='ctx'> 		uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/</div><div class='ctx'> 		uint32_t ips_disable: 3; /* options to disable ips support*/</div><div class='del'>-		uint32_t reserved : 9; /**&lt; reserved */</div><div class='add'>+		uint32_t ips_sequential_ono: 1; /**&lt; 1 to enable sequential ONO IPS sequence */</div><div class='add'>+		uint32_t disable_sldo_opt: 1; /**&lt; 1 to disable SLDO optimizations */</div><div class='add'>+		uint32_t lower_hbr3_phy_ssc: 1; /**&lt; 1 to lower hbr3 phy ssc to 0.125 percent */</div><div class='add'>+		uint32_t override_hbr3_pll_vco: 1; /**&lt; 1 to override the hbr3 pll vco to 0 */</div><div class='add'>+		uint32_t disable_dpia_bw_allocation: 1; /**&lt; 1 to disable the USB4 DPIA BW allocation */</div><div class='add'>+		uint32_t reserved : 4; /**&lt; reserved */</div><div class='ctx'> 	} bits; /**&lt; boot bits */</div><div class='ctx'> 	uint32_t all; /**&lt; 32-bit access to bits */</div><div class='ctx'> };</div><div class='hunk'>@@ -685,6 +1117,8 @@ enum dmub_shared_state_feature_id {</div><div class='ctx'> 	DMUB_SHARED_SHARE_FEATURE__INVALID = 0,</div><div class='ctx'> 	DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,</div><div class='ctx'> 	DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,</div><div class='add'>+	DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3,</div><div class='add'>+	DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4,</div><div class='ctx'> 	DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -693,9 +1127,12 @@ enum dmub_shared_state_feature_id {</div><div class='ctx'>  */</div><div class='ctx'> union dmub_shared_state_ips_fw_signals {</div><div class='ctx'> 	struct {</div><div class='del'>-		uint32_t ips1_commit : 1;  /**&lt; 1 if in IPS1 */</div><div class='add'>+		uint32_t ips1_commit : 1;  /**&lt; 1 if in IPS1 or IPS0 RCG */</div><div class='ctx'> 		uint32_t ips2_commit : 1; /**&lt; 1 if in IPS2 */</div><div class='del'>-		uint32_t reserved_bits : 30; /**&lt; Reversed */</div><div class='add'>+		uint32_t in_idle : 1; /**&lt; 1 if DMCUB is in idle */</div><div class='add'>+		uint32_t detection_required : 1; /**&lt; 1 if detection is required */</div><div class='add'>+		uint32_t ips1z8_commit: 1; /**&lt; 1 if in IPS1 Z8 Retention */</div><div class='add'>+		uint32_t reserved_bits : 27; /**&lt; Reversed */</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint32_t all;</div><div class='ctx'> };</div><div class='hunk'>@@ -709,7 +1146,13 @@ union dmub_shared_state_ips_driver_signals {</div><div class='ctx'> 		uint32_t allow_ips1 : 1; /**&lt; 1 is IPS1 is allowed */</div><div class='ctx'> 		uint32_t allow_ips2 : 1; /**&lt; 1 is IPS1 is allowed */</div><div class='ctx'> 		uint32_t allow_z10 : 1; /**&lt; 1 if Z10 is allowed */</div><div class='del'>-		uint32_t reserved_bits : 28; /**&lt; Reversed bits */</div><div class='add'>+		uint32_t allow_idle: 1; /**&lt; 1 if driver is allowing idle */</div><div class='add'>+		uint32_t allow_ips0_rcg : 1; /**&lt; 1 is IPS0 RCG is allowed */</div><div class='add'>+		uint32_t allow_ips1_rcg : 1; /**&lt; 1 is IPS1 RCG is allowed */</div><div class='add'>+		uint32_t allow_ips1z8 : 1; /**&lt; 1 is IPS1 Z8 Retention is allowed */</div><div class='add'>+		uint32_t allow_dynamic_ips1 : 1; /**&lt; 1 if IPS1 is allowed in dynamic use cases such as VPB */</div><div class='add'>+		uint32_t allow_dynamic_ips1_z8: 1; /**&lt; 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */</div><div class='add'>+		uint32_t reserved_bits : 22; /**&lt; Reversed bits */</div><div class='ctx'> 	} bits;</div><div class='ctx'> 	uint32_t all;</div><div class='ctx'> };</div><div class='hunk'>@@ -719,12 +1162,28 @@ union dmub_shared_state_ips_driver_signals {</div><div class='ctx'>  */</div><div class='ctx'> #define DMUB_SHARED_STATE__IPS_FW_VERSION 1</div><div class='ctx'> </div><div class='add'>+struct dmub_shared_state_debug_setup {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t exclude_points[62];</div><div class='add'>+		} profile_mode;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct dmub_shared_state_ips_fw - Firmware state for IPS.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_shared_state_ips_fw {</div><div class='ctx'> 	union dmub_shared_state_ips_fw_signals signals; /**&lt; 4 bytes, IPS signal bits */</div><div class='del'>-	uint32_t reserved[61]; /**&lt; Reversed, to be updated when adding new fields. */</div><div class='add'>+	uint32_t rcg_entry_count; /**&lt; Entry counter for RCG */</div><div class='add'>+	uint32_t rcg_exit_count; /**&lt; Exit counter for RCG */</div><div class='add'>+	uint32_t ips1_entry_count; /**&lt; Entry counter for IPS1 */</div><div class='add'>+	uint32_t ips1_exit_count; /**&lt; Exit counter for IPS1 */</div><div class='add'>+	uint32_t ips2_entry_count; /**&lt; Entry counter for IPS2 */</div><div class='add'>+	uint32_t ips2_exit_count; /**&lt; Exit counter for IPS2 */</div><div class='add'>+	uint32_t ips1_z8ret_entry_count; /**&lt; Entry counter for IPS1 Z8 Retention */</div><div class='add'>+	uint32_t ips1_z8ret_exit_count; /**&lt; Exit counter for IPS1 Z8 Retention */</div><div class='add'>+	uint32_t reserved[53]; /**&lt; Reversed, to be updated when adding new fields. */</div><div class='ctx'> }; /* 248-bytes, fixed */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -741,6 +1200,22 @@ struct dmub_shared_state_ips_driver {</div><div class='ctx'> }; /* 248-bytes, fixed */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload.</div><div class='add'>+ */</div><div class='add'>+struct dmub_shared_state_cursor_offload_stream_v1 {</div><div class='add'>+	uint32_t last_write_idx; /**&lt; Last write index */</div><div class='add'>+	uint8_t reserved[28]; /**&lt; Reserved bytes. */</div><div class='add'>+}; /* 32-bytes, fixed */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload.</div><div class='add'>+ */</div><div class='add'>+struct dmub_shared_state_cursor_offload_v1 {</div><div class='add'>+	struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**&lt; stream state, 32-bytes each */</div><div class='add'>+	uint8_t reserved[56]; /**&lt; reserved for future use */</div><div class='add'>+}; /* 248-bytes, fixed */</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * enum dmub_shared_state_feature_common - Generic payload.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_shared_state_feature_common {</div><div class='hunk'>@@ -765,6 +1240,8 @@ struct dmub_shared_state_feature_block {</div><div class='ctx'> 		struct dmub_shared_state_feature_common common; /**&lt; Generic data */</div><div class='ctx'> 		struct dmub_shared_state_ips_fw ips_fw; /**&lt; IPS firmware state */</div><div class='ctx'> 		struct dmub_shared_state_ips_driver ips_driver; /**&lt; IPS driver state */</div><div class='add'>+		struct dmub_shared_state_debug_setup debug_setup; /**&lt; Debug setup */</div><div class='add'>+		struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**&lt; Cursor offload */</div><div class='ctx'> 	} data; /**&lt; Shared state data. */</div><div class='ctx'> }; /* 256-bytes, fixed */</div><div class='ctx'> </div><div class='hunk'>@@ -812,6 +1289,10 @@ enum dmub_cmd_vbios_type {</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT  = 26,</div><div class='ctx'> 	/**</div><div class='add'>+	 * Control PHY FSM</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM  = 29,</div><div class='add'>+	/**</div><div class='ctx'> 	 * Controls domain power gating</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,</div><div class='hunk'>@@ -917,6 +1398,37 @@ enum dmub_gpint_command {</div><div class='ctx'> 	DMUB_GPINT__REPLAY_RESIDENCY = 14,</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * DESC: Copy bounding box to the host.</div><div class='add'>+	 * ARGS: Version of bounding box to copy</div><div class='add'>+	 * RETURN: Result of copying bounding box</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__BB_COPY = 96,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the host addresses bit48~bit63 for bounding box.</div><div class='add'>+	 * ARGS: The word3 for the 64 bit address</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the host addresses bit32~bit47 for bounding box.</div><div class='add'>+	 * ARGS: The word2 for the 64 bit address</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the host addresses bit16~bit31 for bounding box.</div><div class='add'>+	 * ARGS: The word1 for the 64 bit address</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the host addresses bit0~bit15 for bounding box.</div><div class='add'>+	 * ARGS: The word0 for the 64 bit address</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * DESC: Updates the trace buffer lower 32-bit mask.</div><div class='ctx'> 	 * ARGS: The new mask</div><div class='ctx'> 	 * RETURN: Lower 32-bit mask.</div><div class='hunk'>@@ -972,11 +1484,114 @@ enum dmub_gpint_command {</div><div class='ctx'> 	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * DESC: Set IPS residency measurement</div><div class='add'>+	 * ARGS: 0 - Disable ips measurement</div><div class='add'>+	 *       1 - Enable ips measurement</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__IPS_RESIDENCY = 121,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * DESC: Enable measurements for various task duration</div><div class='ctx'> 	 * ARGS: 0 - Disable measurement</div><div class='ctx'> 	 *       1 - Enable measurement</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS residency in microseconds</div><div class='add'>+	 * ARGS: 0 - Return IPS1 residency</div><div class='add'>+	 *       1 - Return IPS2 residency</div><div class='add'>+	 *       2 - Return IPS1_RCG residency</div><div class='add'>+	 *       3 - Return IPS1_ONO2_ON residency</div><div class='add'>+	 * RETURN: Total residency in microseconds - lower 32 bits</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS1 histogram counts</div><div class='add'>+	 * ARGS: Bucket index</div><div class='add'>+	 * RETURN: Total count for the bucket</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS2 histogram counts</div><div class='add'>+	 * ARGS: Bucket index</div><div class='add'>+	 * RETURN: Total count for the bucket</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS residency</div><div class='add'>+	 * ARGS: 0 - Return IPS1 residency</div><div class='add'>+	 *       1 - Return IPS2 residency</div><div class='add'>+	 *       2 - Return IPS1_RCG residency</div><div class='add'>+	 *       3 - Return IPS1_ONO2_ON residency</div><div class='add'>+	 * RETURN: Total residency in milli-percent.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS1_RCG histogram counts</div><div class='add'>+	 * ARGS: Bucket index</div><div class='add'>+	 * RETURN: Total count for the bucket</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS1_ONO2_ON histogram counts</div><div class='add'>+	 * ARGS: Bucket index</div><div class='add'>+	 * RETURN: Total count for the bucket</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS entry counter during residency measurement</div><div class='add'>+	 * ARGS: 0 - Return IPS1 entry counts</div><div class='add'>+	 *       1 - Return IPS2 entry counts</div><div class='add'>+	 *       2 - Return IPS1_RCG entry counts</div><div class='add'>+	 *       3 - Return IPS2_ONO2_ON entry counts</div><div class='add'>+	 * RETURN: Entry counter for selected IPS mode</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS inactive residency in microseconds</div><div class='add'>+	 * ARGS: 0 - Return IPS1_MAX residency</div><div class='add'>+	 *       1 - Return IPS2 residency</div><div class='add'>+	 *       2 - Return IPS1_RCG residency</div><div class='add'>+	 *       3 - Return IPS1_ONO2_ON residency</div><div class='add'>+	 * RETURN: Total inactive residency in microseconds - lower 32 bits</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS inactive residency in microseconds</div><div class='add'>+	 * ARGS: 0 - Return IPS1_MAX residency</div><div class='add'>+	 *       1 - Return IPS2 residency</div><div class='add'>+	 *       2 - Return IPS1_RCG residency</div><div class='add'>+	 *       3 - Return IPS1_ONO2_ON residency</div><div class='add'>+	 * RETURN: Total inactive residency in microseconds - upper 32 bits</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Gets IPS residency in microseconds</div><div class='add'>+	 * ARGS: 0 - Return IPS1 residency</div><div class='add'>+	 *       1 - Return IPS2 residency</div><div class='add'>+	 *       2 - Return IPS1_RCG residency</div><div class='add'>+	 *       3 - Return IPS1_ONO2_ON residency</div><div class='add'>+	 * RETURN: Total residency in microseconds - upper 32 bits</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133,</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Setup debug configs.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SETUP_DEBUG_MODE = 136,</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Initiates IPS wake sequence.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__IPS_DEBUG_WAKE = 137,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1056,6 +1671,16 @@ enum dmub_inbox0_command {</div><div class='ctx'> #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer.</div><div class='add'>+ */</div><div class='add'>+#define DMUB_REG_INBOX0_RB_MAX_ENTRY 16</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Ringbuffer size in bytes.</div><div class='add'>+ */</div><div class='add'>+#define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY)</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * REG_SET mask for reg offload.</div><div class='ctx'>  */</div><div class='ctx'> #define REG_SET_MASK 0xFFFF</div><div class='hunk'>@@ -1186,6 +1811,45 @@ enum dmub_cmd_type {</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,</div><div class='ctx'> </div><div class='add'>+	/**</div><div class='add'>+	 * Command type used for all PSP commands.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__PSP = 88,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type used for all Fused IO commands.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__FUSED_IO = 89,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type used for all LSDMA commands.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA = 90,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type use for all IPS commands.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__IPS = 91,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type use for Cursor offload.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__CURSOR_OFFLOAD = 92,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type used for all SMART_POWER_OLED commands.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__SMART_POWER_OLED = 93,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type use for all Panel Replay commands.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__PR = 94,</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Command type use for VBIOS shared commands.</div><div class='add'>+	 */</div><div class='ctx'> 	DMUB_CMD__VBIOS = 128,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1213,13 +1877,23 @@ enum dmub_out_cmd_type {</div><div class='ctx'> 	 * Command type used for USB4 DPIA notification</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,</div><div class='add'>+	/**</div><div class='add'>+	 * Command type used for HPD redetect notification</div><div class='add'>+	 */</div><div class='add'>+	DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,</div><div class='add'>+	/**</div><div class='add'>+	 * Command type used for Fused IO notification</div><div class='add'>+	 */</div><div class='add'>+	DMUB_OUT_CMD__FUSED_IO = 7,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* DMUB_CMD__DPIA command sub-types. */</div><div class='ctx'> enum dmub_cmd_dpia_type {</div><div class='ctx'> 	DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,</div><div class='del'>-	DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,</div><div class='add'>+	DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST</div><div class='ctx'> 	DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,</div><div class='add'>+	DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,</div><div class='add'>+	DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */</div><div class='hunk'>@@ -1237,7 +1911,8 @@ struct dmub_cmd_header {</div><div class='ctx'> 	unsigned int sub_type : 8; /**&lt; command sub type */</div><div class='ctx'> 	unsigned int ret_status : 1; /**&lt; 1 if returned data, 0 otherwise */</div><div class='ctx'> 	unsigned int multi_cmd_pending : 1; /**&lt; 1 if multiple commands chained together */</div><div class='del'>-	unsigned int reserved0 : 6; /**&lt; reserved bits */</div><div class='add'>+	unsigned int is_reg_based : 1; /**&lt; 1 if register based mailbox cmd, 0 if FB based cmd */</div><div class='add'>+	unsigned int reserved0 : 5; /**&lt; reserved bits */</div><div class='ctx'> 	unsigned int payload_bytes : 6;  /* payload excluding header - up to 60 bytes */</div><div class='ctx'> 	unsigned int reserved1 : 2; /**&lt; reserved bits */</div><div class='ctx'> };</div><div class='hunk'>@@ -1556,6 +2231,459 @@ struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {</div><div class='ctx'> 	struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dmub_flip_addr_info {</div><div class='add'>+	uint32_t surf_addr_lo;</div><div class='add'>+	uint32_t surf_addr_c_lo;</div><div class='add'>+	uint32_t meta_addr_lo;</div><div class='add'>+	uint32_t meta_addr_c_lo;</div><div class='add'>+	uint16_t surf_addr_hi;</div><div class='add'>+	uint16_t surf_addr_c_hi;</div><div class='add'>+	uint16_t meta_addr_hi;</div><div class='add'>+	uint16_t meta_addr_c_hi;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_flip_info {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint8_t is_immediate: 1;</div><div class='add'>+		} bits;</div><div class='add'>+		uint8_t all;</div><div class='add'>+	} config;</div><div class='add'>+	uint8_t otg_inst;</div><div class='add'>+	uint8_t pipe_mask;</div><div class='add'>+	uint8_t pad;</div><div class='add'>+	struct dmub_flip_addr_info addr_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rb_cmd_fams2_flip {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_fams2_flip_info flip_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_lsdma_data {</div><div class='add'>+	union {</div><div class='add'>+		struct lsdma_init_data {</div><div class='add'>+			union dmub_addr gpu_addr_base;</div><div class='add'>+			uint32_t ring_size;</div><div class='add'>+		} init_data;</div><div class='add'>+		struct lsdma_tiled_copy_data {</div><div class='add'>+			uint32_t src_addr_lo;</div><div class='add'>+			uint32_t src_addr_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_addr_lo;</div><div class='add'>+			uint32_t dst_addr_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t src_x            : 16;</div><div class='add'>+			uint32_t src_y            : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_x            : 16;</div><div class='add'>+			uint32_t dst_y            : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t src_width        : 16;</div><div class='add'>+			uint32_t src_height       : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_width        : 16;</div><div class='add'>+			uint32_t dst_height       : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t rect_x           : 16;</div><div class='add'>+			uint32_t rect_y           : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t src_swizzle_mode : 5;</div><div class='add'>+			uint32_t src_mip_max      : 5;</div><div class='add'>+			uint32_t src_mip_id       : 5;</div><div class='add'>+			uint32_t dst_mip_max      : 5;</div><div class='add'>+			uint32_t dst_swizzle_mode : 5;</div><div class='add'>+			uint32_t dst_mip_id       : 5;</div><div class='add'>+			uint32_t tmz              : 1;</div><div class='add'>+			uint32_t dcc              : 1;</div><div class='add'>+</div><div class='add'>+			uint32_t data_format      : 6;</div><div class='add'>+			uint32_t padding1         : 4;</div><div class='add'>+			uint32_t dst_element_size : 3;</div><div class='add'>+			uint32_t num_type         : 3;</div><div class='add'>+			uint32_t src_element_size : 3;</div><div class='add'>+			uint32_t write_compress   : 2;</div><div class='add'>+			uint32_t cache_policy_dst : 2;</div><div class='add'>+			uint32_t cache_policy_src : 2;</div><div class='add'>+			uint32_t read_compress    : 2;</div><div class='add'>+			uint32_t src_dim          : 2;</div><div class='add'>+			uint32_t dst_dim          : 2;</div><div class='add'>+			uint32_t max_uncom        : 1;</div><div class='add'>+</div><div class='add'>+			uint32_t max_com          : 2;</div><div class='add'>+			uint32_t padding          : 30;</div><div class='add'>+		} tiled_copy_data;</div><div class='add'>+		struct lsdma_linear_copy_data {</div><div class='add'>+			uint32_t src_lo;</div><div class='add'>+			uint32_t src_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_lo;</div><div class='add'>+			uint32_t dst_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t count            : 30;</div><div class='add'>+			uint32_t cache_policy_dst : 2;</div><div class='add'>+</div><div class='add'>+			uint32_t tmz              : 1;</div><div class='add'>+			uint32_t cache_policy_src : 2;</div><div class='add'>+			uint32_t padding          : 29;</div><div class='add'>+		} linear_copy_data;</div><div class='add'>+		struct lsdma_linear_sub_window_copy_data {</div><div class='add'>+			uint32_t src_lo;</div><div class='add'>+			uint32_t src_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_lo;</div><div class='add'>+			uint32_t dst_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t src_x        : 16;</div><div class='add'>+			uint32_t src_y        : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_x        : 16;</div><div class='add'>+			uint32_t dst_y        : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t rect_x       : 16;</div><div class='add'>+			uint32_t rect_y       : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t src_pitch    : 16;</div><div class='add'>+			uint32_t dst_pitch    : 16;</div><div class='add'>+</div><div class='add'>+			uint32_t src_slice_pitch;</div><div class='add'>+			uint32_t dst_slice_pitch;</div><div class='add'>+</div><div class='add'>+			uint32_t tmz              : 1;</div><div class='add'>+			uint32_t element_size     : 3;</div><div class='add'>+			uint32_t src_cache_policy : 3;</div><div class='add'>+			uint32_t dst_cache_policy : 3;</div><div class='add'>+			uint32_t reserved0        : 22;</div><div class='add'>+		} linear_sub_window_copy_data;</div><div class='add'>+		struct lsdma_reg_write_data {</div><div class='add'>+			uint32_t reg_addr;</div><div class='add'>+			uint32_t reg_data;</div><div class='add'>+		} reg_write_data;</div><div class='add'>+		struct lsdma_pio_copy_data {</div><div class='add'>+			uint32_t src_lo;</div><div class='add'>+			uint32_t src_hi;</div><div class='add'>+</div><div class='add'>+			uint32_t dst_lo;</div><div class='add'>+			uint32_t dst_hi;</div><div class='add'>+</div><div class='add'>+			union {</div><div class='add'>+				struct {</div><div class='add'>+					uint32_t byte_count      : 26;</div><div class='add'>+					uint32_t src_loc         : 1;</div><div class='add'>+					uint32_t dst_loc         : 1;</div><div class='add'>+					uint32_t src_addr_inc    : 1;</div><div class='add'>+					uint32_t dst_addr_inc    : 1;</div><div class='add'>+					uint32_t overlap_disable : 1;</div><div class='add'>+					uint32_t constant_fill   : 1;</div><div class='add'>+				} fields;</div><div class='add'>+				uint32_t raw;</div><div class='add'>+			} packet;</div><div class='add'>+		} pio_copy_data;</div><div class='add'>+		struct lsdma_pio_constfill_data {</div><div class='add'>+			uint32_t dst_lo;</div><div class='add'>+			uint32_t dst_hi;</div><div class='add'>+</div><div class='add'>+			union {</div><div class='add'>+				struct {</div><div class='add'>+					uint32_t byte_count      : 26;</div><div class='add'>+					uint32_t src_loc         : 1;</div><div class='add'>+					uint32_t dst_loc         : 1;</div><div class='add'>+					uint32_t src_addr_inc    : 1;</div><div class='add'>+					uint32_t dst_addr_inc    : 1;</div><div class='add'>+					uint32_t overlap_disable : 1;</div><div class='add'>+					uint32_t constant_fill   : 1;</div><div class='add'>+				} fields;</div><div class='add'>+				uint32_t raw;</div><div class='add'>+			} packet;</div><div class='add'>+</div><div class='add'>+			uint32_t data;</div><div class='add'>+		} pio_constfill_data;</div><div class='add'>+</div><div class='add'>+		uint32_t all[14];</div><div class='add'>+	} u;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rb_cmd_lsdma {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_cmd_lsdma_data lsdma_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_optc_state_v2 {</div><div class='add'>+	uint32_t v_total_min;</div><div class='add'>+	uint32_t v_total_max;</div><div class='add'>+	uint32_t v_total_mid;</div><div class='add'>+	uint32_t v_total_mid_frame_num;</div><div class='add'>+	uint8_t program_manual_trigger;</div><div class='add'>+	uint8_t tg_inst;</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_optc_position {</div><div class='add'>+	uint32_t vpos;</div><div class='add'>+	uint32_t hpos;</div><div class='add'>+	uint32_t frame;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rb_cmd_fams2_drr_update {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_optc_state_v2 dmub_optc_state_req;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* HW and FW global configuration data for FAMS2 */</div><div class='add'>+/* FAMS2 types and structs */</div><div class='add'>+enum fams2_stream_type {</div><div class='add'>+	FAMS2_STREAM_TYPE_NONE = 0,</div><div class='add'>+	FAMS2_STREAM_TYPE_VBLANK = 1,</div><div class='add'>+	FAMS2_STREAM_TYPE_VACTIVE = 2,</div><div class='add'>+	FAMS2_STREAM_TYPE_DRR = 3,</div><div class='add'>+	FAMS2_STREAM_TYPE_SUBVP = 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rect16 {</div><div class='add'>+	/**</div><div class='add'>+	 * Dirty rect x offset.</div><div class='add'>+	 */</div><div class='add'>+	uint16_t x;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Dirty rect y offset.</div><div class='add'>+	 */</div><div class='add'>+	uint16_t y;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Dirty rect width.</div><div class='add'>+	 */</div><div class='add'>+	uint16_t width;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Dirty rect height.</div><div class='add'>+	 */</div><div class='add'>+	uint16_t height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* static stream state */</div><div class='add'>+struct dmub_fams2_legacy_stream_static_state {</div><div class='add'>+	uint8_t vactive_det_fill_delay_otg_vlines;</div><div class='add'>+	uint8_t programming_delay_otg_vlines;</div><div class='add'>+}; //v0</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_subvp_stream_static_state {</div><div class='add'>+	uint16_t vratio_numerator;</div><div class='add'>+	uint16_t vratio_denominator;</div><div class='add'>+	uint16_t phantom_vtotal;</div><div class='add'>+	uint16_t phantom_vactive;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint8_t is_multi_planar : 1;</div><div class='add'>+			uint8_t is_yuv420 : 1;</div><div class='add'>+		} bits;</div><div class='add'>+		uint8_t all;</div><div class='add'>+	} config;</div><div class='add'>+	uint8_t programming_delay_otg_vlines;</div><div class='add'>+	uint8_t prefetch_to_mall_otg_vlines;</div><div class='add'>+	uint8_t phantom_otg_inst;</div><div class='add'>+	uint8_t phantom_pipe_mask;</div><div class='add'>+	uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)</div><div class='add'>+}; //v0</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_drr_stream_static_state {</div><div class='add'>+	uint16_t nom_stretched_vtotal;</div><div class='add'>+	uint8_t programming_delay_otg_vlines;</div><div class='add'>+	uint8_t only_stretch_if_required;</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+}; //v0</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_cmd_legacy_stream_static_state {</div><div class='add'>+	uint16_t vactive_det_fill_delay_otg_vlines;</div><div class='add'>+	uint16_t programming_delay_otg_vlines;</div><div class='add'>+}; //v1</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_cmd_subvp_stream_static_state {</div><div class='add'>+	uint16_t vratio_numerator;</div><div class='add'>+	uint16_t vratio_denominator;</div><div class='add'>+	uint16_t phantom_vtotal;</div><div class='add'>+	uint16_t phantom_vactive;</div><div class='add'>+	uint16_t programming_delay_otg_vlines;</div><div class='add'>+	uint16_t prefetch_to_mall_otg_vlines;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint8_t is_multi_planar : 1;</div><div class='add'>+			uint8_t is_yuv420 : 1;</div><div class='add'>+		} bits;</div><div class='add'>+		uint8_t all;</div><div class='add'>+	} config;</div><div class='add'>+	uint8_t phantom_otg_inst;</div><div class='add'>+	uint8_t phantom_pipe_mask;</div><div class='add'>+	uint8_t pad0;</div><div class='add'>+	uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)</div><div class='add'>+	uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];</div><div class='add'>+}; //v1</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_cmd_drr_stream_static_state {</div><div class='add'>+	uint16_t nom_stretched_vtotal;</div><div class='add'>+	uint16_t programming_delay_otg_vlines;</div><div class='add'>+	uint8_t only_stretch_if_required;</div><div class='add'>+	uint8_t pad[3];</div><div class='add'>+}; //v1</div><div class='add'>+</div><div class='add'>+union dmub_fams2_stream_static_sub_state {</div><div class='add'>+	struct dmub_fams2_legacy_stream_static_state legacy;</div><div class='add'>+	struct dmub_fams2_subvp_stream_static_state subvp;</div><div class='add'>+	struct dmub_fams2_drr_stream_static_state drr;</div><div class='add'>+}; //v0</div><div class='add'>+</div><div class='add'>+union dmub_fams2_cmd_stream_static_sub_state {</div><div class='add'>+	COMMON_STREAM_STATIC_SUB_STATE</div><div class='add'>+}; //v1</div><div class='add'>+</div><div class='add'>+union dmub_fams2_stream_static_sub_state_v2 {</div><div class='add'>+	COMMON_STREAM_STATIC_SUB_STATE</div><div class='add'>+}; //v2</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_stream_static_state {</div><div class='add'>+	enum fams2_stream_type type;</div><div class='add'>+	uint32_t otg_vline_time_ns;</div><div class='add'>+	uint32_t otg_vline_time_ticks;</div><div class='add'>+	uint16_t htotal;</div><div class='add'>+	uint16_t vtotal; // nominal vtotal</div><div class='add'>+	uint16_t vblank_start;</div><div class='add'>+	uint16_t vblank_end;</div><div class='add'>+	uint16_t max_vtotal;</div><div class='add'>+	uint16_t allow_start_otg_vline;</div><div class='add'>+	uint16_t allow_end_otg_vline;</div><div class='add'>+	uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed</div><div class='add'>+	uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start</div><div class='add'>+	uint8_t contention_delay_otg_vlines; // time to budget for contention on execution</div><div class='add'>+	uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing</div><div class='add'>+	uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint8_t is_drr: 1; // stream is DRR enabled</div><div class='add'>+			uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal</div><div class='add'>+			uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank</div><div class='add'>+		} bits;</div><div class='add'>+		uint8_t all;</div><div class='add'>+	} config;</div><div class='add'>+	uint8_t otg_inst;</div><div class='add'>+	uint8_t pipe_mask; // pipe mask for the whole config</div><div class='add'>+	uint8_t num_planes;</div><div class='add'>+	uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)</div><div class='add'>+	uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];</div><div class='add'>+	union dmub_fams2_stream_static_sub_state sub_state;</div><div class='add'>+}; //v0</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_cmd_stream_static_base_state {</div><div class='add'>+	enum fams2_stream_type type;</div><div class='add'>+	uint32_t otg_vline_time_ns;</div><div class='add'>+	uint32_t otg_vline_time_ticks;</div><div class='add'>+	uint16_t htotal;</div><div class='add'>+	uint16_t vtotal; // nominal vtotal</div><div class='add'>+	uint16_t vblank_start;</div><div class='add'>+	uint16_t vblank_end;</div><div class='add'>+	uint16_t max_vtotal;</div><div class='add'>+	uint16_t allow_start_otg_vline;</div><div class='add'>+	uint16_t allow_end_otg_vline;</div><div class='add'>+	uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed</div><div class='add'>+	uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start</div><div class='add'>+	uint16_t contention_delay_otg_vlines; // time to budget for contention on execution</div><div class='add'>+	uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing</div><div class='add'>+	uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint8_t is_drr : 1; // stream is DRR enabled</div><div class='add'>+			uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal</div><div class='add'>+			uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank</div><div class='add'>+		} bits;</div><div class='add'>+		uint8_t all;</div><div class='add'>+	} config;</div><div class='add'>+	uint8_t otg_inst;</div><div class='add'>+	uint8_t pipe_mask; // pipe mask for the whole config</div><div class='add'>+	uint8_t num_planes;</div><div class='add'>+	uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)</div><div class='add'>+	uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];</div><div class='add'>+}; //v1</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_stream_static_state_v1 {</div><div class='add'>+	struct dmub_fams2_cmd_stream_static_base_state base;</div><div class='add'>+	union dmub_fams2_stream_static_sub_state_v2 sub_state;</div><div class='add'>+}; //v1</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive</div><div class='add'>+ * p-state request to allow latency</div><div class='add'>+ */</div><div class='add'>+enum dmub_fams2_allow_delay_check_mode {</div><div class='add'>+	/* No check for request to allow delay */</div><div class='add'>+	FAMS2_ALLOW_DELAY_CHECK_NONE = 0,</div><div class='add'>+	/* Check for request to allow delay */</div><div class='add'>+	FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,</div><div class='add'>+	/* Check for prepare to allow delay */</div><div class='add'>+	FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union dmub_fams2_global_feature_config {</div><div class='add'>+	struct {</div><div class='add'>+		uint32_t enable: 1;</div><div class='add'>+		uint32_t enable_ppt_check: 1;</div><div class='add'>+		uint32_t enable_stall_recovery: 1;</div><div class='add'>+		uint32_t enable_debug: 1;</div><div class='add'>+		uint32_t enable_offload_flip: 1;</div><div class='add'>+		uint32_t enable_visual_confirm: 1;</div><div class='add'>+		uint32_t allow_delay_check_mode: 2;</div><div class='add'>+		uint32_t reserved: 24;</div><div class='add'>+	} bits;</div><div class='add'>+	uint32_t all;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_fams2_global_config {</div><div class='add'>+	uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin</div><div class='add'>+	uint32_t lock_wait_time_us; // time to forecast acquisition of lock</div><div class='add'>+	uint32_t num_streams;</div><div class='add'>+	union dmub_fams2_global_feature_config features;</div><div class='add'>+	uint32_t recovery_timeout_us;</div><div class='add'>+	uint32_t hwfq_flip_programming_delay_us;</div><div class='add'>+	uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+union dmub_cmd_fams2_config {</div><div class='add'>+	struct dmub_cmd_fams2_global_config global;</div><div class='add'>+// coverity[cert_dcl37_c_violation:FALSE]  errno.h, stddef.h, stdint.h not included in atombios.h</div><div class='add'>+	struct dmub_fams2_stream_static_state stream; //v0</div><div class='add'>+	union {</div><div class='add'>+		struct dmub_fams2_cmd_stream_static_base_state base;</div><div class='add'>+		union dmub_fams2_cmd_stream_static_sub_state sub_state;</div><div class='add'>+	} stream_v1; //v1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_fams2_config_v2 {</div><div class='add'>+	struct dmub_cmd_fams2_global_config global;</div><div class='add'>+	struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_fams2 {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	union dmub_cmd_fams2_config config;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Indirect buffer descriptor</div><div class='add'>+ */</div><div class='add'>+struct dmub_ib_data {</div><div class='add'>+	union dmub_addr src; // location of indirect buffer in memory</div><div class='add'>+	uint16_t size; // indirect buffer size in bytes</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DMUB rb command definition for commands passed over indirect buffer</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_ib {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_ib_data ib_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * enum dmub_cmd_idle_opt_type - Idle optimization command type.</div><div class='ctx'>  */</div><div class='hunk'>@@ -1573,7 +2701,17 @@ enum dmub_cmd_idle_opt_type {</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * DCN hardware notify idle.</div><div class='ctx'> 	 */</div><div class='del'>-	DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2</div><div class='add'>+	DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DCN hardware notify power state.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DCN notify to release HW.</div><div class='add'>+	 */</div><div class='add'>+	 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1588,7 +2726,8 @@ struct dmub_rb_cmd_idle_opt_dcn_restore {</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_dcn_notify_idle_cntl_data {</div><div class='ctx'> 	uint8_t driver_idle;</div><div class='del'>-	uint8_t pad[1];</div><div class='add'>+	uint8_t skip_otg_disable;</div><div class='add'>+	uint8_t reserved[58];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1600,6 +2739,33 @@ struct dmub_rb_cmd_idle_opt_dcn_notify_idle {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * enum dmub_idle_opt_dc_power_state - DC power states.</div><div class='add'>+ */</div><div class='add'>+enum dmub_idle_opt_dc_power_state {</div><div class='add'>+	DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,</div><div class='add'>+	DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,</div><div class='add'>+	DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,</div><div class='add'>+	DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,</div><div class='add'>+	DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_idle_opt_set_dc_power_state_data {</div><div class='add'>+	uint8_t power_state; /**&lt; power state */</div><div class='add'>+	uint8_t pad[3]; /**&lt; padding */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_idle_opt_set_dc_power_state {</div><div class='add'>+	struct dmub_cmd_header header; /**&lt; header */</div><div class='add'>+	struct dmub_idle_opt_set_dc_power_state_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * struct dmub_clocks - Clock update notification.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_clocks {</div><div class='hunk'>@@ -1691,7 +2857,8 @@ struct dmub_dig_transmitter_control_data_v1_7 {</div><div class='ctx'> 	uint8_t connobj_id; /**&lt; Connector Object Id defined in ObjectId.h */</div><div class='ctx'> 	uint8_t HPO_instance; /**&lt; HPO instance (0: inst0, 1: inst1) */</div><div class='ctx'> 	uint8_t reserved1; /**&lt; For future use */</div><div class='del'>-	uint8_t reserved2[3]; /**&lt; For future use */</div><div class='add'>+	uint8_t skip_phy_ssc_reduction;</div><div class='add'>+	uint8_t reserved2[2]; /**&lt; For future use */</div><div class='ctx'> 	uint32_t reserved3[11]; /**&lt; For future use */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1757,7 +2924,7 @@ struct dmub_rb_cmd_dig1_dpia_control {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * SET_CONFIG Command Payload</div><div class='add'>+ * SET_CONFIG Command Payload (deprecated)</div><div class='ctx'>  */</div><div class='ctx'> struct set_config_cmd_payload {</div><div class='ctx'> 	uint8_t msg_type; /* set config message type */</div><div class='hunk'>@@ -1765,7 +2932,7 @@ struct set_config_cmd_payload {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated)</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_cmd_set_config_control_data {</div><div class='ctx'> 	struct set_config_cmd_payload cmd_pkt;</div><div class='hunk'>@@ -1774,6 +2941,17 @@ struct dmub_cmd_set_config_control_data {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * SET_CONFIG Request Command Payload</div><div class='add'>+ */</div><div class='add'>+struct set_config_request_cmd_payload {</div><div class='add'>+	uint8_t instance; /* DPIA instance */</div><div class='add'>+	uint8_t immed_status; /* Immediate status returned in case of error */</div><div class='add'>+	uint8_t msg_type; /* set config message type */</div><div class='add'>+	uint8_t reserved;</div><div class='add'>+	uint32_t msg_data; /* set config message data */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DMUB command structure for SET_CONFIG command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_rb_cmd_set_config_access {</div><div class='hunk'>@@ -1782,6 +2960,14 @@ struct dmub_rb_cmd_set_config_access {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * DMUB command structure for SET_CONFIG request command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_set_config_request {</div><div class='add'>+	struct dmub_cmd_header header; /* header */</div><div class='add'>+	struct set_config_request_cmd_payload payload; /* set config request payload */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_cmd_mst_alloc_slots_control_data {</div><div class='hunk'>@@ -1800,6 +2986,24 @@ struct dmub_rb_cmd_set_mst_alloc_slots {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_tps_notification_data {</div><div class='add'>+	uint8_t instance; /* DPIA instance */</div><div class='add'>+	uint8_t tps; /* requested training pattern */</div><div class='add'>+	uint8_t reserved1;</div><div class='add'>+	uint8_t reserved2;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DMUB command structure for SET_TPS_NOTIFICATION command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_set_tps_notification {</div><div class='add'>+	struct dmub_cmd_header header; /* header */</div><div class='add'>+	struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * DMUB command structure for DPIA HPD int enable control.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_rb_cmd_dpia_hpd_int_enable {</div><div class='hunk'>@@ -2001,7 +3205,11 @@ enum dp_hpd_type {</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * DP HPD short pulse</div><div class='ctx'> 	 */</div><div class='del'>-	DP_IRQ</div><div class='add'>+	DP_IRQ = 1,</div><div class='add'>+	/**</div><div class='add'>+	 * Failure to acquire DP HPD state</div><div class='add'>+	 */</div><div class='add'>+	DP_NONE_HPD = 2</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2179,6 +3387,22 @@ struct dmub_rb_cmd_query_hpd_state {</div><div class='ctx'> 	struct dmub_cmd_hpd_state_query_data data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_hpd_sense_notify_data {</div><div class='add'>+	uint32_t old_hpd_sense_mask; /**&lt; Old HPD sense mask */</div><div class='add'>+	uint32_t new_hpd_sense_mask; /**&lt; New HPD sense mask */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_hpd_sense_notify {</div><div class='add'>+	struct dmub_cmd_header header; /**&lt; header */</div><div class='add'>+	struct dmub_rb_cmd_hpd_sense_notify_data data; /**&lt; payload */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Command IDs should be treated as stable ABI.</div><div class='ctx'>  * Do not reuse or modify IDs.</div><div class='hunk'>@@ -2227,6 +3451,18 @@ enum dmub_cmd_psr_type {</div><div class='ctx'> 	DMUB_CMD__SET_PSR_POWER_OPT = 7,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * Different PSR residency modes.</div><div class='add'>+ * Different modes change the definition of PSR residency.</div><div class='add'>+ */</div><div class='add'>+enum psr_residency_mode {</div><div class='add'>+	PSR_RESIDENCY_MODE_PHY = 0,</div><div class='add'>+	PSR_RESIDENCY_MODE_ALPM,</div><div class='add'>+	PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,</div><div class='add'>+	/* Do not add below. */</div><div class='add'>+	PSR_RESIDENCY_MODE_LAST_ELEMENT,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum dmub_cmd_fams_type {</div><div class='ctx'> 	DMUB_CMD__FAMS_SETUP_FW_CTRL	= 0,</div><div class='ctx'> 	DMUB_CMD__FAMS_DRR_UPDATE		= 1,</div><div class='hunk'>@@ -2237,6 +3473,10 @@ enum dmub_cmd_fams_type {</div><div class='ctx'> 	 * on (for any SubVP cases that use a DRR display)</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,</div><div class='add'>+	DMUB_CMD__FAMS2_CONFIG = 4,</div><div class='add'>+	DMUB_CMD__FAMS2_DRR_UPDATE = 5,</div><div class='add'>+	DMUB_CMD__FAMS2_FLIP = 6,</div><div class='add'>+	DMUB_CMD__FAMS2_IB_CONFIG = 7,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2309,6 +3549,11 @@ enum phy_link_rate {</div><div class='ctx'> 	 * UHBR10 - 20.0 Gbps/Lane</div><div class='ctx'> 	 */</div><div class='ctx'> 	PHY_RATE_2000 = 11,</div><div class='add'>+</div><div class='add'>+	PHY_RATE_675 = 12,</div><div class='add'>+	/**</div><div class='add'>+	 * Rate 12 - 6.75 Gbps/Lane</div><div class='add'>+	 */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2327,6 +3572,7 @@ enum dmub_phy_fsm_state {</div><div class='ctx'> 	DMUB_PHY_FSM_POWER_DOWN,</div><div class='ctx'> 	DMUB_PHY_FSM_PLL_EN,</div><div class='ctx'> 	DMUB_PHY_FSM_TX_EN,</div><div class='add'>+	DMUB_PHY_FSM_TX_EN_TEST_MODE,</div><div class='ctx'> 	DMUB_PHY_FSM_FAST_LP,</div><div class='ctx'> 	DMUB_PHY_FSM_P2_PLL_OFF_CPM,</div><div class='ctx'> 	DMUB_PHY_FSM_P2_PLL_OFF_PG,</div><div class='hunk'>@@ -2462,9 +3708,9 @@ struct dmub_cmd_psr_copy_settings_data {</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint8_t relock_delay_frame_cnt;</div><div class='ctx'> 	/**</div><div class='del'>-	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 * esd recovery indicate.</div><div class='ctx'> 	 */</div><div class='del'>-	uint8_t pad3;</div><div class='add'>+	uint8_t esd_recovery;</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * DSC Slice height.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -2473,6 +3719,12 @@ struct dmub_cmd_psr_copy_settings_data {</div><div class='ctx'> 	 * Some panels request main link off before xth vertical line</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint16_t poweroff_before_vertical_line;</div><div class='add'>+	/**</div><div class='add'>+	 * Some panels cannot handle idle pattern during PSR entry.</div><div class='add'>+	 * To power down phy before disable stream to avoid sending</div><div class='add'>+	 * idle pattern.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t power_down_phy_before_disable_stream;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2931,23 +4183,61 @@ struct dmub_rb_cmd_psr_set_power_opt {</div><div class='ctx'> 	struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dmub_alpm_mode {</div><div class='add'>+	ALPM_AUXWAKE = 0,</div><div class='add'>+	ALPM_AUXLESS = 1,</div><div class='add'>+	ALPM_UNSUPPORTED = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of Replay Residency GPINT command.</div><div class='add'>+ * Bit[0] - Residency mode for Revision 0</div><div class='add'>+ * Bit[1] - Enable/Disable state</div><div class='add'>+ * Bit[2-3] - Revision number</div><div class='add'>+ * Bit[4-7] - Residency mode for Revision 1</div><div class='add'>+ * Bit[8] - Panel instance</div><div class='add'>+ * Bit[9-15] - Reserved</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+enum pr_residency_mode {</div><div class='add'>+	PR_RESIDENCY_MODE_PHY = 0x0,</div><div class='add'>+	PR_RESIDENCY_MODE_ALPM,</div><div class='add'>+	PR_RESIDENCY_MODE_IPS2,</div><div class='add'>+	PR_RESIDENCY_MODE_FRAME_CNT,</div><div class='add'>+	PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define REPLAY_RESIDENCY_MODE_SHIFT            (0)</div><div class='ctx'> #define REPLAY_RESIDENCY_ENABLE_SHIFT          (1)</div><div class='add'>+#define REPLAY_RESIDENCY_REVISION_SHIFT        (2)</div><div class='add'>+#define REPLAY_RESIDENCY_MODE2_SHIFT           (4)</div><div class='ctx'> </div><div class='ctx'> #define REPLAY_RESIDENCY_MODE_MASK             (0x1 &lt;&lt; REPLAY_RESIDENCY_MODE_SHIFT)</div><div class='del'>-# define REPLAY_RESIDENCY_MODE_PHY             (0x0 &lt;&lt; REPLAY_RESIDENCY_MODE_SHIFT)</div><div class='del'>-# define REPLAY_RESIDENCY_MODE_ALPM            (0x1 &lt;&lt; REPLAY_RESIDENCY_MODE_SHIFT)</div><div class='del'>-# define REPLAY_RESIDENCY_MODE_IPS             0x10</div><div class='add'>+# define REPLAY_RESIDENCY_FIELD_MODE_PHY       (0x0 &lt;&lt; REPLAY_RESIDENCY_MODE_SHIFT)</div><div class='add'>+# define REPLAY_RESIDENCY_FIELD_MODE_ALPM      (0x1 &lt;&lt; REPLAY_RESIDENCY_MODE_SHIFT)</div><div class='add'>+</div><div class='add'>+#define REPLAY_RESIDENCY_MODE2_MASK            (0xF &lt;&lt; REPLAY_RESIDENCY_MODE2_SHIFT)</div><div class='add'>+# define REPLAY_RESIDENCY_FIELD_MODE2_IPS      (0x1 &lt;&lt; REPLAY_RESIDENCY_MODE2_SHIFT)</div><div class='add'>+# define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT    (0x2 &lt;&lt; REPLAY_RESIDENCY_MODE2_SHIFT)</div><div class='add'>+# define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD	(0x3 &lt;&lt; REPLAY_RESIDENCY_MODE2_SHIFT)</div><div class='ctx'> </div><div class='ctx'> #define REPLAY_RESIDENCY_ENABLE_MASK           (0x1 &lt;&lt; REPLAY_RESIDENCY_ENABLE_SHIFT)</div><div class='ctx'> # define REPLAY_RESIDENCY_DISABLE              (0x0 &lt;&lt; REPLAY_RESIDENCY_ENABLE_SHIFT)</div><div class='ctx'> # define REPLAY_RESIDENCY_ENABLE               (0x1 &lt;&lt; REPLAY_RESIDENCY_ENABLE_SHIFT)</div><div class='ctx'> </div><div class='add'>+#define REPLAY_RESIDENCY_REVISION_MASK         (0x3 &lt;&lt; REPLAY_RESIDENCY_REVISION_SHIFT)</div><div class='add'>+# define REPLAY_RESIDENCY_REVISION_0           (0x0 &lt;&lt; REPLAY_RESIDENCY_REVISION_SHIFT)</div><div class='add'>+# define REPLAY_RESIDENCY_REVISION_1           (0x1 &lt;&lt; REPLAY_RESIDENCY_REVISION_SHIFT)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a replay_state.</div><div class='add'>+ */</div><div class='ctx'> enum replay_state {</div><div class='ctx'> 	REPLAY_STATE_0			= 0x0,</div><div class='ctx'> 	REPLAY_STATE_1			= 0x10,</div><div class='ctx'> 	REPLAY_STATE_1A			= 0x11,</div><div class='ctx'> 	REPLAY_STATE_2			= 0x20,</div><div class='add'>+	REPLAY_STATE_2A			= 0x21,</div><div class='ctx'> 	REPLAY_STATE_3			= 0x30,</div><div class='ctx'> 	REPLAY_STATE_3INIT		= 0x31,</div><div class='ctx'> 	REPLAY_STATE_4			= 0x40,</div><div class='hunk'>@@ -2955,6 +4245,7 @@ enum replay_state {</div><div class='ctx'> 	REPLAY_STATE_4B			= 0x42,</div><div class='ctx'> 	REPLAY_STATE_4C			= 0x43,</div><div class='ctx'> 	REPLAY_STATE_4D			= 0x44,</div><div class='add'>+	REPLAY_STATE_4E			= 0x45,</div><div class='ctx'> 	REPLAY_STATE_4B_LOCKED		= 0x4A,</div><div class='ctx'> 	REPLAY_STATE_4C_UNLOCKED	= 0x4B,</div><div class='ctx'> 	REPLAY_STATE_5			= 0x50,</div><div class='hunk'>@@ -2969,6 +4260,33 @@ enum replay_state {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Definition of a panel replay state</div><div class='add'>+ */</div><div class='add'>+enum pr_state {</div><div class='add'>+	PR_STATE_0									= 0x00, // State 0 steady state</div><div class='add'>+	// Pending SDP and Unlock before back to State 0</div><div class='add'>+	PR_STATE_0_PENDING_SDP_AND_UNLOCK			= 0x01,</div><div class='add'>+	PR_STATE_1									= 0x10, // State 1</div><div class='add'>+	PR_STATE_2									= 0x20, // State 2 steady state</div><div class='add'>+	// Pending frame transmission before transition to State 2</div><div class='add'>+	PR_STATE_2_PENDING_FRAME_TRANSMISSION		= 0x30,</div><div class='add'>+	// Active and Powered Up</div><div class='add'>+	PR_STATE_2_POWERED							= 0x31,</div><div class='add'>+	// Active and Powered Down, but need to blank HUBP after DPG_EN latch</div><div class='add'>+	PR_STATE_2_PENDING_HUBP_BLANK				= 0x32,</div><div class='add'>+	// Active and Pending Power Up</div><div class='add'>+	PR_STATE_2_PENDING_POWER_UP					= 0x33,</div><div class='add'>+	// Active and Powered Up, Pending DPG latch</div><div class='add'>+	PR_STATE_2_PENDING_LOCK_FOR_DPG_POWER_ON	= 0x34,</div><div class='add'>+	// Active and Powered Up, Pending SDP and Unlock</div><div class='add'>+	PR_STATE_2_PENDING_SDP_AND_UNLOCK			= 0x35,</div><div class='add'>+	// Pending transmission of AS SDP for timing sync, but no rfb update</div><div class='add'>+	PR_STATE_2_PENDING_AS_SDP					= 0x36,</div><div class='add'>+	// Invalid</div><div class='add'>+	PR_STATE_INVALID							= 0xFF,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Replay command sub-types.</div><div class='ctx'>  */</div><div class='ctx'> enum dmub_cmd_replay_type {</div><div class='hunk'>@@ -3004,6 +4322,68 @@ enum dmub_cmd_replay_type {</div><div class='ctx'> 	 * Set pseudo vtotal</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,</div><div class='add'>+	/**</div><div class='add'>+	 * Set adaptive sync sdp enabled</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,</div><div class='add'>+	/**</div><div class='add'>+	 * Set version</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__REPLAY_SET_VERSION = 9,</div><div class='add'>+	/**</div><div class='add'>+	 * Set Replay General command.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Panel Replay sub-types</div><div class='add'>+ */</div><div class='add'>+enum dmub_cmd_panel_replay_type {</div><div class='add'>+	DMUB_CMD__PR_ENABLE = 0,</div><div class='add'>+	DMUB_CMD__PR_COPY_SETTINGS = 1,</div><div class='add'>+	DMUB_CMD__PR_UPDATE_STATE = 2,</div><div class='add'>+	DMUB_CMD__PR_GENERAL_CMD = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dmub_cmd_panel_replay_state_update_subtype {</div><div class='add'>+	PR_STATE_UPDATE_COASTING_VTOTAL = 0x1,</div><div class='add'>+	PR_STATE_UPDATE_SYNC_MODE = 0x2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dmub_cmd_panel_replay_general_subtype {</div><div class='add'>+	PR_GENERAL_CMD_DEBUG_OPTION = 0x1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Replay general command sub-types.</div><div class='add'>+ */</div><div class='add'>+enum dmub_cmd_replay_general_subtype {</div><div class='add'>+	REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,</div><div class='add'>+	/**</div><div class='add'>+	 * TODO: For backward compatible, allow new command only.</div><div class='add'>+	 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,</div><div class='add'>+	 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,</div><div class='add'>+	 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,</div><div class='add'>+	 */</div><div class='add'>+	REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,</div><div class='add'>+	REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,</div><div class='add'>+	REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS,</div><div class='add'>+	REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE,</div><div class='add'>+	REPLAY_GENERAL_CMD_VIDEO_CONFERENCING,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_alpm_auxless_data {</div><div class='add'>+	uint16_t lfps_setup_ns;</div><div class='add'>+	uint16_t lfps_period_ns;</div><div class='add'>+	uint16_t lfps_silence_ns;</div><div class='add'>+	uint16_t lfps_t1_t2_override_us;</div><div class='add'>+	short lfps_t1_t2_offset_us;</div><div class='add'>+	uint8_t lttpr_count;</div><div class='add'>+	/*</div><div class='add'>+	 * Padding to align structure to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[1];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3076,6 +4456,79 @@ struct dmub_cmd_replay_copy_settings_data {</div><div class='ctx'> 	 * Use FSM state for Replay power up/down</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint8_t use_phy_fsm;</div><div class='add'>+	/**</div><div class='add'>+	 * Use for AUX-less ALPM LFPS wake operation</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_alpm_auxless_data auxless_alpm_data;</div><div class='add'>+	/**</div><div class='add'>+	 * @hpo_stream_enc_inst: HPO stream encoder instance</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_stream_enc_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * @hpo_link_enc_inst: HPO link encoder instance</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_link_enc_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Determines if fast resync in ultra sleep mode is enabled/disabled.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t replay_support_fast_resync_in_ultra_sleep_mode;</div><div class='add'>+	/**</div><div class='add'>+	 * @pad: Align structure to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[1];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Replay versions.</div><div class='add'>+ */</div><div class='add'>+enum replay_version {</div><div class='add'>+	/**</div><div class='add'>+	 * FreeSync Replay</div><div class='add'>+	 */</div><div class='add'>+	REPLAY_VERSION_FREESYNC_REPLAY	= 0,</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Replay</div><div class='add'>+	 */</div><div class='add'>+	REPLAY_VERSION_PANEL_REPLAY		= 1,</div><div class='add'>+	/**</div><div class='add'>+	 * Replay not supported.</div><div class='add'>+	 */</div><div class='add'>+	REPLAY_VERSION_UNSUPPORTED		= 0xFF,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_replay_set_version_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel instance to identify which psr_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Replay version that FW should implement.</div><div class='add'>+	 */</div><div class='add'>+	enum replay_version version;</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[3];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__REPLAY_SET_VERSION command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_replay_set_version {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_set_version_data replay_set_version_data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3107,6 +4560,45 @@ enum replay_enable {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_smart_power_oled_enable_data {</div><div class='add'>+	/**</div><div class='add'>+	 * SMART_POWER_OLED enable or disable.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t enable;</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+</div><div class='add'>+	uint16_t peak_nits;</div><div class='add'>+	/**</div><div class='add'>+	 * OTG HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t otg_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * DIG FE HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t digfe_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * DIG BE HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t digbe_inst;</div><div class='add'>+	uint8_t debugcontrol;</div><div class='add'>+	/*</div><div class='add'>+	 * vertical interrupt trigger line</div><div class='add'>+	 */</div><div class='add'>+	uint32_t triggerline;</div><div class='add'>+</div><div class='add'>+	uint16_t fixed_max_cll;</div><div class='add'>+</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_rb_cmd_replay_enable_data {</div><div class='hunk'>@@ -3205,6 +4697,40 @@ struct dmub_cmd_replay_set_pseudo_vtotal {</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint8_t pad;</div><div class='ctx'> };</div><div class='add'>+struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * enabled: set adaptive sync sdp enabled</div><div class='add'>+	 */</div><div class='add'>+	uint8_t force_disabled;</div><div class='add'>+</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+struct dmub_cmd_replay_set_general_cmd_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * subtype: replay general cmd sub type</div><div class='add'>+	 */</div><div class='add'>+	uint8_t subtype;</div><div class='add'>+</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+	/**</div><div class='add'>+	 * config data with param1 and param2</div><div class='add'>+	 */</div><div class='add'>+	uint32_t param1;</div><div class='add'>+</div><div class='add'>+	uint32_t param2;</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.</div><div class='hunk'>@@ -3243,9 +4769,9 @@ struct dmub_cmd_replay_set_coasting_vtotal_data {</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint16_t coasting_vtotal_high;</div><div class='ctx'> 	/**</div><div class='del'>-	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 * frame skip number.</div><div class='ctx'> 	 */</div><div class='del'>-	uint8_t pad[2];</div><div class='add'>+	uint16_t frame_skip_number;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3309,6 +4835,34 @@ struct dmub_rb_cmd_replay_set_pseudo_vtotal {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_replay_set_general_cmd {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_set_general_cmd_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Data passed from driver to FW in  DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_cmd_replay_frameupdate_timer_data {</div><div class='hunk'>@@ -3363,6 +4917,70 @@ union dmub_replay_cmd_set {</div><div class='ctx'> 	 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_SET_VERSION command data.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_set_version_data version_data;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * SMART POWER OLED command sub-types.</div><div class='add'>+ */</div><div class='add'>+enum dmub_cmd_smart_power_oled_type {</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Enable/Disable SMART_POWER_OLED.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__SMART_POWER_OLED_ENABLE = 1,</div><div class='add'>+	/**</div><div class='add'>+	 * Get current MaxCLL value if SMART POWER OLED is enabled.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__SMART_POWER_OLED command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_smart_power_oled_enable {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_smart_power_oled_enable_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_smart_power_oled_getmaxcll_input {</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	uint8_t pad[3];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_smart_power_oled_getmaxcll_output {</div><div class='add'>+	uint16_t current_max_cll;</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__SMART_POWER_OLED command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_smart_power_oled_getmaxcll {</div><div class='add'>+	struct dmub_cmd_header header; /**&lt; Command header */</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.</div><div class='add'>+	 */</div><div class='add'>+	union dmub_cmd_smart_power_oled_getmaxcll_data {</div><div class='add'>+		struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**&lt; Input */</div><div class='add'>+		struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**&lt; Output */</div><div class='add'>+		uint32_t output_raw; /**&lt; Raw data output */</div><div class='add'>+	} data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3445,7 +5063,9 @@ enum hw_lock_client {</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Replay is the client of HW Lock Manager.</div><div class='ctx'> 	 */</div><div class='del'>-	HW_LOCK_CLIENT_REPLAY           = 4,</div><div class='add'>+	HW_LOCK_CLIENT_REPLAY		= 4,</div><div class='add'>+	HW_LOCK_CLIENT_FAMS2 = 5,</div><div class='add'>+	HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6,</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Invalid client.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -3538,6 +5158,132 @@ enum dmub_cmd_abm_type {</div><div class='ctx'> 	 * on restore we update state with passed in data.</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__ABM_SAVE_RESTORE	= 7,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Query ABM caps.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__ABM_QUERY_CAPS	= 8,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Set ABM Events</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__ABM_SET_EVENT	= 9,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Get the current ACE curve.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__ABM_GET_ACE_CURVE = 10,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Get current histogram data</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * LSDMA command sub-types.</div><div class='add'>+ */</div><div class='add'>+enum dmub_cmd_lsdma_type {</div><div class='add'>+	/**</div><div class='add'>+	 * Initialize parameters for LSDMA.</div><div class='add'>+	 * Ring buffer is mapped to the ring buffer</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA_INIT_CONFIG	= 0,</div><div class='add'>+	/**</div><div class='add'>+	 * LSDMA copies data from source to destination linearly</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA_LINEAR_COPY = 1,</div><div class='add'>+	/**</div><div class='add'>+	* LSDMA copies data from source to destination linearly in sub window</div><div class='add'>+	*/</div><div class='add'>+	DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2,</div><div class='add'>+	/**</div><div class='add'>+	 * Send the tiled-to-tiled copy command</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3,</div><div class='add'>+	/**</div><div class='add'>+	 * Send the poll reg write command</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA_POLL_REG_WRITE = 4,</div><div class='add'>+	/**</div><div class='add'>+	 * Send the pio copy command</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA_PIO_COPY = 5,</div><div class='add'>+	/**</div><div class='add'>+	 * Send the pio constfill command</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__LSDMA_PIO_CONSTFILL = 6,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct abm_ace_curve {</div><div class='add'>+	/**</div><div class='add'>+	 * @offsets: ACE curve offsets.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @thresholds: ACE curve thresholds.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @slopes: ACE curve slopes.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct fixed_pt_format {</div><div class='add'>+	/**</div><div class='add'>+	 * @sign_bit: Indicates whether one bit is reserved for the sign.</div><div class='add'>+	 */</div><div class='add'>+	bool sign_bit;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @num_int_bits: Number of bits used for integer part.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t num_int_bits;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @num_frac_bits: Number of bits used for fractional part.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t num_frac_bits;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @pad: Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct abm_caps {</div><div class='add'>+	/**</div><div class='add'>+	 * @num_hg_bins: Number of histogram bins.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t num_hg_bins;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @num_ace_segments: Number of ACE curve segments.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t num_ace_segments;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @pad: Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.</div><div class='add'>+	 */</div><div class='add'>+	struct fixed_pt_format ace_thresholds_format;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.</div><div class='add'>+	 */</div><div class='add'>+	struct fixed_pt_format ace_offsets_format;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @ace_slopes_format: Format of the ACE slopes.</div><div class='add'>+	 */</div><div class='add'>+	struct fixed_pt_format ace_slopes_format;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3682,6 +5428,24 @@ struct dmub_rb_cmd_abm_set_pipe {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Type of backlight control method to be used by ABM module</div><div class='add'>+ */</div><div class='add'>+enum dmub_backlight_control_type {</div><div class='add'>+	/**</div><div class='add'>+	 * PWM Backlight control</div><div class='add'>+	 */</div><div class='add'>+	DMU_BACKLIGHT_CONTROL_PWM = 0,</div><div class='add'>+	/**</div><div class='add'>+	 * VESA Aux-based backlight control</div><div class='add'>+	 */</div><div class='add'>+	DMU_BACKLIGHT_CONTROL_VESA_AUX = 1,</div><div class='add'>+	/**</div><div class='add'>+	 * AMD DPCD Aux-based backlight control</div><div class='add'>+	 */</div><div class='add'>+	DMU_BACKLIGHT_CONTROL_AMD_AUX = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_cmd_abm_set_backlight_data {</div><div class='hunk'>@@ -3708,9 +5472,42 @@ struct dmub_cmd_abm_set_backlight_data {</div><div class='ctx'> 	uint8_t panel_mask;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * AUX HW Instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t aux_inst;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * Explicit padding to 4 byte boundary.</div><div class='ctx'> 	 */</div><div class='del'>-	uint8_t pad[2];</div><div class='add'>+	uint8_t pad[1];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Backlight control type.</div><div class='add'>+	 * Value 0 is PWM backlight control.</div><div class='add'>+	 * Value 1 is VAUX backlight control.</div><div class='add'>+	 * Value 2 is AMD DPCD AUX backlight control.</div><div class='add'>+	 */</div><div class='add'>+	enum dmub_backlight_control_type backlight_control_type;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Minimum luminance in nits.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t min_luminance;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Maximum luminance in nits.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t max_luminance;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Minimum backlight in pwm.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t min_backlight_pwm;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Maximum backlight in pwm.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t max_backlight_pwm;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3948,6 +5745,152 @@ struct dmub_rb_cmd_abm_pause {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_abm_query_caps_in {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[3];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_abm_query_caps_out {</div><div class='add'>+	/**</div><div class='add'>+	 * SW Algorithm caps.</div><div class='add'>+	 */</div><div class='add'>+	struct abm_caps sw_caps;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * ABM HW caps.</div><div class='add'>+	 */</div><div class='add'>+	struct abm_caps hw_caps;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_abm_query_caps {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.</div><div class='add'>+	 */</div><div class='add'>+	union {</div><div class='add'>+		struct dmub_cmd_abm_query_caps_in  abm_query_caps_in;</div><div class='add'>+		struct dmub_cmd_abm_query_caps_out abm_query_caps_out;</div><div class='add'>+	} data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * enum dmub_abm_ace_curve_type - ACE curve type.</div><div class='add'>+ */</div><div class='add'>+enum dmub_abm_ace_curve_type {</div><div class='add'>+	/**</div><div class='add'>+	 * ACE curve as defined by the SW layer.</div><div class='add'>+	 */</div><div class='add'>+	ABM_ACE_CURVE_TYPE__SW = 0,</div><div class='add'>+	/**</div><div class='add'>+	 * ACE curve as defined by the SW to HW translation interface layer.</div><div class='add'>+	 */</div><div class='add'>+	ABM_ACE_CURVE_TYPE__SW_IF = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * enum dmub_abm_histogram_type - Histogram type.</div><div class='add'>+ */</div><div class='add'>+enum dmub_abm_histogram_type {</div><div class='add'>+	/**</div><div class='add'>+	 * ACE curve as defined by the SW layer.</div><div class='add'>+	 */</div><div class='add'>+	ABM_HISTOGRAM_TYPE__SW = 0,</div><div class='add'>+	/**</div><div class='add'>+	 * ACE curve as defined by the SW to HW translation interface layer.</div><div class='add'>+	 */</div><div class='add'>+	ABM_HISTOGRAM_TYPE__SW_IF = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_abm_get_ace_curve {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Address where ACE curve should be copied.</div><div class='add'>+	 */</div><div class='add'>+	union dmub_addr dest;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Type of ACE curve being queried.</div><div class='add'>+	 */</div><div class='add'>+	enum dmub_abm_ace_curve_type ace_type;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Indirect buffer length.</div><div class='add'>+	 */</div><div class='add'>+	uint16_t bytes;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * eDP panel instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_abm_get_histogram {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Address where Histogram should be copied.</div><div class='add'>+	 */</div><div class='add'>+	union dmub_addr dest;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Type of Histogram being queried.</div><div class='add'>+	 */</div><div class='add'>+	enum dmub_abm_histogram_type histogram_type;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Indirect buffer length.</div><div class='add'>+	 */</div><div class='add'>+	uint16_t bytes;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * eDP panel instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_rb_cmd_abm_save_restore {</div><div class='hunk'>@@ -3978,6 +5921,52 @@ struct dmub_rb_cmd_abm_save_restore {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_abm_set_event_data {</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * VB Scaling Init. Strength Mapping</div><div class='add'>+	 * Byte 0: 0~255 for VB level 0</div><div class='add'>+	 * Byte 1: 0~255 for VB level 1</div><div class='add'>+	 * Byte 2: 0~255 for VB level 2</div><div class='add'>+	 * Byte 3: 0~255 for VB level 3</div><div class='add'>+	 */</div><div class='add'>+	uint32_t vb_scaling_strength_mapping;</div><div class='add'>+	/**</div><div class='add'>+	 * VariBright Scaling Enable</div><div class='add'>+	 */</div><div class='add'>+	uint8_t vb_scaling_enable;</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Control HW instance mask.</div><div class='add'>+	 * Bit 0 is Panel Control HW instance 0.</div><div class='add'>+	 * Bit 1 is Panel Control HW instance 1.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_mask;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__ABM_SET_EVENT command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_abm_set_event {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_abm_set_event_data abm_set_event_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_cmd_query_feature_caps_data {</div><div class='hunk'>@@ -4038,6 +6027,10 @@ enum dmub_cmd_panel_cntl_type {</div><div class='ctx'> 	 * Queries backlight info for the embedded panel.</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,</div><div class='add'>+	/**</div><div class='add'>+	 * Sets the PWM Freq as per user's requirement.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -4139,6 +6132,34 @@ struct dmub_rb_cmd_transmitter_query_dp_alt {</div><div class='ctx'> 	struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**&lt; payload */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct phy_test_mode {</div><div class='add'>+	uint8_t mode;</div><div class='add'>+	uint8_t pat0;</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_transmitter_set_phy_fsm_data {</div><div class='add'>+	uint8_t phy_id; /**&lt; 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */</div><div class='add'>+	uint8_t mode; /**&lt; HDMI/DP/DP2 etc */</div><div class='add'>+	uint8_t lane_num; /**&lt; Number of lanes */</div><div class='add'>+	uint32_t symclk_100Hz; /**&lt; PLL symclock in 100hz */</div><div class='add'>+	struct phy_test_mode test_mode;</div><div class='add'>+	enum dmub_phy_fsm_state state;</div><div class='add'>+	uint32_t status;</div><div class='add'>+	uint8_t pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_transmitter_set_phy_fsm {</div><div class='add'>+	struct dmub_cmd_header header; /**&lt; header */</div><div class='add'>+	struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**&lt; payload */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * Maximum number of bytes a chunk sent to DMUB for parsing</div><div class='ctx'>  */</div><div class='hunk'>@@ -4233,13 +6254,98 @@ struct dmub_rb_cmd_get_usbc_cable_id {</div><div class='ctx'> 	} data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dmub_cmd_fused_io_sub_type {</div><div class='add'>+	DMUB_CMD__FUSED_IO_EXECUTE = 0,</div><div class='add'>+	DMUB_CMD__FUSED_IO_ABORT = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dmub_cmd_fused_request_type {</div><div class='add'>+	FUSED_REQUEST_READ,</div><div class='add'>+	FUSED_REQUEST_WRITE,</div><div class='add'>+	FUSED_REQUEST_POLL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dmub_cmd_fused_request_status {</div><div class='add'>+	FUSED_REQUEST_STATUS_SUCCESS,</div><div class='add'>+	FUSED_REQUEST_STATUS_BEGIN,</div><div class='add'>+	FUSED_REQUEST_STATUS_SUBMIT,</div><div class='add'>+	FUSED_REQUEST_STATUS_REPLY,</div><div class='add'>+	FUSED_REQUEST_STATUS_POLL,</div><div class='add'>+	FUSED_REQUEST_STATUS_ABORTED,</div><div class='add'>+	FUSED_REQUEST_STATUS_FAILED = 0x80,</div><div class='add'>+	FUSED_REQUEST_STATUS_INVALID,</div><div class='add'>+	FUSED_REQUEST_STATUS_BUSY,</div><div class='add'>+	FUSED_REQUEST_STATUS_TIMEOUT,</div><div class='add'>+	FUSED_REQUEST_STATUS_POLL_TIMEOUT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_fused_request {</div><div class='add'>+	uint8_t status;</div><div class='add'>+	uint8_t type : 2;</div><div class='add'>+	uint8_t _reserved0 : 3;</div><div class='add'>+	uint8_t poll_mask_msb : 3;  // Number of MSB to zero out from last byte before comparing</div><div class='add'>+	uint8_t identifier;</div><div class='add'>+	uint8_t _reserved1;</div><div class='add'>+	uint32_t timeout_us;</div><div class='add'>+	union dmub_cmd_fused_request_location {</div><div class='add'>+		struct dmub_cmd_fused_request_location_i2c {</div><div class='add'>+			uint8_t is_aux : 1;  // False</div><div class='add'>+			uint8_t ddc_line : 3;</div><div class='add'>+			uint8_t over_aux : 1;</div><div class='add'>+			uint8_t _reserved0 : 3;</div><div class='add'>+			uint8_t address;</div><div class='add'>+			uint8_t offset;</div><div class='add'>+			uint8_t length;</div><div class='add'>+		} i2c;</div><div class='add'>+		struct dmub_cmd_fused_request_location_aux {</div><div class='add'>+			uint32_t is_aux : 1;  // True</div><div class='add'>+			uint32_t ddc_line : 3;</div><div class='add'>+			uint32_t address : 20;</div><div class='add'>+			uint32_t length : 8;  // Automatically split into 16B transactions</div><div class='add'>+		} aux;</div><div class='add'>+	} u;</div><div class='add'>+	uint8_t buffer[0x30];  // Read: out, write: in, poll: expected</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rb_cmd_fused_io {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_cmd_fused_request request;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * Command type of a DMUB_CMD__SECURE_DISPLAY command</div><div class='ctx'>  */</div><div class='ctx'> enum dmub_cmd_secure_display_type {</div><div class='ctx'> 	DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0,		/* test command to only check if inbox message works */</div><div class='ctx'> 	DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,</div><div class='del'>-	DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY</div><div class='add'>+	DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY,</div><div class='add'>+	DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE,</div><div class='add'>+	DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_ROI_NUM	2</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_roi_info {</div><div class='add'>+	uint16_t x_start;</div><div class='add'>+	uint16_t x_end;</div><div class='add'>+	uint16_t y_start;</div><div class='add'>+	uint16_t y_end;</div><div class='add'>+	uint8_t otg_id;</div><div class='add'>+	uint8_t phy_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_roi_window_ctl {</div><div class='add'>+	uint16_t x_start;</div><div class='add'>+	uint16_t x_end;</div><div class='add'>+	uint16_t y_start;</div><div class='add'>+	uint16_t y_end;</div><div class='add'>+	bool enable;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_roi_ctl_info {</div><div class='add'>+	uint8_t otg_id;</div><div class='add'>+	uint8_t phy_id;</div><div class='add'>+	struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -4250,14 +6356,376 @@ struct dmub_rb_cmd_secure_display {</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Data passed from driver to dmub firmware.</div><div class='ctx'> 	 */</div><div class='del'>-	struct dmub_cmd_roi_info {</div><div class='del'>-		uint16_t x_start;</div><div class='del'>-		uint16_t x_end;</div><div class='del'>-		uint16_t y_start;</div><div class='del'>-		uint16_t y_end;</div><div class='del'>-		uint8_t otg_id;</div><div class='del'>-		uint8_t phy_id;</div><div class='del'>-	} roi_info;</div><div class='add'>+	struct dmub_cmd_roi_info roi_info;</div><div class='add'>+	struct dmub_cmd_roi_ctl_info mul_roi_ctl;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Command type of a DMUB_CMD__PSP command</div><div class='add'>+ */</div><div class='add'>+enum dmub_cmd_psp_type {</div><div class='add'>+	DMUB_CMD__PSP_ASSR_ENABLE = 0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_assr_enable_data {</div><div class='add'>+	/**</div><div class='add'>+	 * ASSR enable or disable.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t enable;</div><div class='add'>+	/**</div><div class='add'>+	 * PHY port type.</div><div class='add'>+	 * Indicates eDP / non-eDP port type</div><div class='add'>+	 */</div><div class='add'>+	uint8_t phy_port_type;</div><div class='add'>+	/**</div><div class='add'>+	 * PHY port ID.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t phy_port_id;</div><div class='add'>+	/**</div><div class='add'>+	 * Link encoder index.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t link_enc_index;</div><div class='add'>+	/**</div><div class='add'>+	 * HPO mode.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_mode;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Reserved field.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t reserved[7];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_assr_enable {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Assr data.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_assr_enable_data assr_data;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Reserved field.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t reserved[3];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Current definition of "ips_mode" from driver</div><div class='add'>+ */</div><div class='add'>+enum ips_residency_mode {</div><div class='add'>+	IPS_RESIDENCY__IPS1_MAX,</div><div class='add'>+	IPS_RESIDENCY__IPS2,</div><div class='add'>+	IPS_RESIDENCY__IPS1_RCG,</div><div class='add'>+	IPS_RESIDENCY__IPS1_ONO2_ON,</div><div class='add'>+	IPS_RESIDENCY__IPS1_Z8_RETENTION,</div><div class='add'>+	IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS,</div><div class='add'>+	IPS_RESIDENCY__PG_ONO_CURRENT_STATE</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define NUM_IPS_HISTOGRAM_BUCKETS 16</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats</div><div class='add'>+ */</div><div class='add'>+struct dmub_ips_residency_info {</div><div class='add'>+	uint32_t residency_millipercent;</div><div class='add'>+	uint32_t entry_counter;</div><div class='add'>+	uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS];</div><div class='add'>+	uint64_t total_time_us;</div><div class='add'>+	uint64_t total_inactive_time_us;</div><div class='add'>+	uint32_t ono_pg_state_at_collection;</div><div class='add'>+	uint32_t ono_pg_state_last_seen_in_ips;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_ips_residency_cntl_data {</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	uint8_t start_measurement;</div><div class='add'>+	uint8_t padding[2]; // align to 4-byte boundary</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rb_cmd_ips_residency_cntl {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_cmd_ips_residency_cntl_data cntl_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_ips_query_residency_info_data {</div><div class='add'>+	union dmub_addr dest;</div><div class='add'>+	uint32_t size;</div><div class='add'>+	uint32_t ips_mode;</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	uint8_t padding[3]; // align to 4-byte boundary</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_rb_cmd_ips_query_residency_info {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_cmd_ips_query_residency_info_data info_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_cursor_offload_init_data {</div><div class='add'>+	union dmub_addr state_addr; /**&lt; State address for dmub_cursor_offload */</div><div class='add'>+	uint32_t state_size; /**&lt; State size for dmub_cursor_offload */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_cursor_offload_init {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_cmd_cursor_offload_init_data init_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_cursor_offload_stream_data {</div><div class='add'>+	uint32_t otg_inst: 4; /**&lt; OTG instance to control  */</div><div class='add'>+	uint32_t reserved: 28; /**&lt; Reserved for future use */</div><div class='add'>+	uint32_t line_time_in_ns; /**&lt; Line time in ns for the OTG */</div><div class='add'>+	uint32_t v_total_max; /**&lt; OTG v_total_max */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_cursor_offload_stream_cntl {</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	struct dmub_cmd_cursor_offload_stream_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_pr_enable_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Replay enable or disable.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t enable;</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Phy state to enter.</div><div class='add'>+	 * Values to use are defined in dmub_phy_fsm_state</div><div class='add'>+	 */</div><div class='add'>+	uint8_t phy_fsm_state;</div><div class='add'>+	/**</div><div class='add'>+	 * Phy rate for DP - RBR/HBR/HBR2/HBR3.</div><div class='add'>+	 * Set this using enum phy_link_rate.</div><div class='add'>+	 * This does not support HDMI/DP2 for now.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t phy_rate;</div><div class='add'>+	/**</div><div class='add'>+	 * @hpo_stream_enc_inst: HPO stream encoder instance</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_stream_enc_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * @hpo_link_enc_inst: HPO link encoder instance</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_link_enc_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * @pad: Align structure to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__PR_ENABLE command.</div><div class='add'>+ * Panel Replay enable/disable is controlled using action in data.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_pr_enable {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+</div><div class='add'>+	struct dmub_cmd_pr_enable_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_pr_copy_settings_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Flags that can be set by driver to change some replay behaviour.</div><div class='add'>+	 */</div><div class='add'>+	union pr_debug_flags debug;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @flags: Flags used to determine feature functionality.</div><div class='add'>+	 */</div><div class='add'>+	union pr_hw_flags flags;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DPP HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t dpp_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * OTG HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t otg_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * DIG FE HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t digfe_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * DIG BE HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t digbe_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * AUX HW instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t aux_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which psr_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Length of each horizontal line in ns.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t line_time_in_ns;</div><div class='add'>+	/**</div><div class='add'>+	 * PHY instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t dpphy_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Determines if SMU optimzations are enabled/disabled.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t smu_optimizations_en;</div><div class='add'>+	/*</div><div class='add'>+	 * Use FSM state for Replay power up/down</div><div class='add'>+	 */</div><div class='add'>+	uint8_t use_phy_fsm;</div><div class='add'>+	/*</div><div class='add'>+	 * Use FSFT afftet pixel clk</div><div class='add'>+	 */</div><div class='add'>+	uint32_t pix_clk_100hz;</div><div class='add'>+	/*</div><div class='add'>+	 * Use Original pixel clock</div><div class='add'>+	 */</div><div class='add'>+	uint32_t sink_pix_clk_100hz;</div><div class='add'>+	/**</div><div class='add'>+	 * Use for AUX-less ALPM LFPS wake operation</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_alpm_auxless_data auxless_alpm_data;</div><div class='add'>+	/**</div><div class='add'>+	 * @hpo_stream_enc_inst: HPO stream encoder instance</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_stream_enc_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * @hpo_link_enc_inst: HPO link encoder instance</div><div class='add'>+	 */</div><div class='add'>+	uint8_t hpo_link_enc_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * @pad: Align structure to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__PR_COPY_SETTINGS command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_pr_copy_settings {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_pr_copy_settings_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_pr_update_state_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which psr_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+</div><div class='add'>+	uint8_t pad[3]; // align to 4-byte boundary</div><div class='add'>+	/*</div><div class='add'>+	 * Update flags to control the update behavior.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t update_flag;</div><div class='add'>+	/**</div><div class='add'>+	 * state/data to set.</div><div class='add'>+	 */</div><div class='add'>+	uint32_t coasting_vtotal;</div><div class='add'>+	uint32_t sync_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_cmd_pr_general_cmd_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which psr_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * subtype: PR general cmd sub type</div><div class='add'>+	 */</div><div class='add'>+	uint8_t subtype;</div><div class='add'>+</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+	/**</div><div class='add'>+	 * config data by different subtypes</div><div class='add'>+	 */</div><div class='add'>+	union {</div><div class='add'>+		uint32_t u32All;</div><div class='add'>+	} data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__PR_UPDATE_STATE command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_pr_update_state {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_pr_update_state_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition of a DMUB_CMD__PR_GENERAL_CMD command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_pr_general_cmd {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_pr_general_cmd_data data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -4421,6 +6889,26 @@ union dmub_rb_cmd {</div><div class='ctx'> 	struct dmub_rb_cmd_abm_save_restore abm_save_restore;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_abm_query_caps abm_query_caps;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_abm_get_histogram abm_get_histogram;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__ABM_SET_EVENT command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_abm_set_event abm_set_event;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_dp_aux_access dp_aux_access;</div><div class='hunk'>@@ -4451,18 +6939,30 @@ union dmub_rb_cmd {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;</div><div class='ctx'> 	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;</div><div class='add'>+	/**</div><div class='ctx'> 	 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.</div><div class='ctx'> 	 */</div><div class='del'>-	struct dmub_rb_cmd_set_config_access set_config_access;</div><div class='add'>+	struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated)</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_set_config_request set_config_request;</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;</div><div class='ctx'> 	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_set_tps_notification set_tps_notification;</div><div class='add'>+	/**</div><div class='ctx'> 	 * Definition of a DMUB_CMD__EDID_CEA command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_edid_cea edid_cea;</div><div class='hunk'>@@ -4488,6 +6988,14 @@ union dmub_rb_cmd {</div><div class='ctx'> 	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__REPLAY_SET_VERSION command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_replay_set_version replay_set_version;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -4518,6 +7026,69 @@ union dmub_rb_cmd {</div><div class='ctx'> 	 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_assr_enable assr_enable;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_fams2 fams2_config;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_ib ib_fams2_config;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_fams2_flip fams2_flip;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_fused_io fused_io;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__LSDMA command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_lsdma lsdma;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_cursor_offload_init cursor_offload_init;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands.</div><div class='add'>+	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE</div><div class='add'>+	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE</div><div class='add'>+	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM</div><div class='add'>+	 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll;</div><div class='add'>+	/*</div><div class='add'>+	 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_pr_copy_settings pr_copy_settings;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__REPLAY_ENABLE command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_pr_enable pr_enable;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_pr_update_state pr_update_state;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_pr_general_cmd pr_general_cmd;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -4544,6 +7115,11 @@ union dmub_rb_out_cmd {</div><div class='ctx'> 	 * DPIA notification command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_dpia_notification dpia_notification;</div><div class='add'>+	/**</div><div class='add'>+	 * HPD sense notification command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;</div><div class='add'>+	struct dmub_rb_cmd_fused_io fused_io;</div><div class='ctx'> };</div><div class='ctx'> #pragma pack(pop)</div><div class='ctx'> </div><div class='hunk'>@@ -4554,10 +7130,6 @@ union dmub_rb_out_cmd {</div><div class='ctx'> //&lt; DMUB_RB&gt;====================================================================</div><div class='ctx'> //==============================================================================</div><div class='ctx'> </div><div class='del'>-#if defined(__cplusplus)</div><div class='del'>-extern "C" {</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer</div><div class='ctx'>  */</div><div class='hunk'>@@ -4595,6 +7167,45 @@ static inline bool dmub_rb_empty(struct dmub_rb *rb)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * @brief gets number of outstanding requests in the RB</div><div class='add'>+ *</div><div class='add'>+ * @param rb DMUB Ringbuffer</div><div class='add'>+ * @return true if full</div><div class='add'>+ */</div><div class='add'>+static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb)</div><div class='add'>+{</div><div class='add'>+	uint32_t data_count;</div><div class='add'>+</div><div class='add'>+	if (rb-&gt;wrpt &gt;= rb-&gt;rptr)</div><div class='add'>+		data_count = rb-&gt;wrpt - rb-&gt;rptr;</div><div class='add'>+	else</div><div class='add'>+		data_count = rb-&gt;capacity - (rb-&gt;rptr - rb-&gt;wrpt);</div><div class='add'>+</div><div class='add'>+	return data_count / DMUB_RB_CMD_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * @brief gets number of free buffers in the RB</div><div class='add'>+ *</div><div class='add'>+ * @param rb DMUB Ringbuffer</div><div class='add'>+ * @return true if full</div><div class='add'>+ */</div><div class='add'>+static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb)</div><div class='add'>+{</div><div class='add'>+	uint32_t data_count;</div><div class='add'>+</div><div class='add'>+	if (rb-&gt;wrpt &gt;= rb-&gt;rptr)</div><div class='add'>+		data_count = rb-&gt;wrpt - rb-&gt;rptr;</div><div class='add'>+	else</div><div class='add'>+		data_count = rb-&gt;capacity - (rb-&gt;rptr - rb-&gt;wrpt);</div><div class='add'>+</div><div class='add'>+	/* +1 because 1 entry is always unusable */</div><div class='add'>+	data_count += DMUB_RB_CMD_SIZE;</div><div class='add'>+</div><div class='add'>+	return (rb-&gt;capacity - data_count) / DMUB_RB_CMD_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * @brief Checks if the ringbuffer is full</div><div class='ctx'>  *</div><div class='ctx'>  * @param rb DMUB Ringbuffer</div><div class='hunk'>@@ -4610,6 +7221,7 @@ static inline bool dmub_rb_full(struct dmub_rb *rb)</div><div class='ctx'> 	else</div><div class='ctx'> 		data_count = rb-&gt;capacity - (rb-&gt;rptr - rb-&gt;wrpt);</div><div class='ctx'> </div><div class='add'>+	/* -1 because 1 entry is always unusable */</div><div class='ctx'> 	return (data_count == (rb-&gt;capacity - DMUB_RB_CMD_SIZE));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4624,15 +7236,18 @@ static inline bool dmub_rb_full(struct dmub_rb *rb)</div><div class='ctx'> static inline bool dmub_rb_push_front(struct dmub_rb *rb,</div><div class='ctx'> 				      const union dmub_rb_cmd *cmd)</div><div class='ctx'> {</div><div class='del'>-	uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb-&gt;base_address) + rb-&gt;wrpt);</div><div class='del'>-	const uint64_t *src = (const uint64_t *)cmd;</div><div class='add'>+	uint8_t *dst = (uint8_t *)(rb-&gt;base_address) + rb-&gt;wrpt;</div><div class='add'>+	const uint8_t *src = (const uint8_t *)cmd;</div><div class='ctx'> 	uint8_t i;</div><div class='ctx'> </div><div class='add'>+	if (rb-&gt;capacity == 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	if (dmub_rb_full(rb))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	// copying data</div><div class='del'>-	for (i = 0; i &lt; DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)</div><div class='add'>+	for (i = 0; i &lt; DMUB_RB_CMD_SIZE; i++)</div><div class='ctx'> 		*dst++ = *src++;</div><div class='ctx'> </div><div class='ctx'> 	rb-&gt;wrpt += DMUB_RB_CMD_SIZE;</div><div class='hunk'>@@ -4657,6 +7272,9 @@ static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,</div><div class='ctx'> 	uint8_t *dst = (uint8_t *)(rb-&gt;base_address) + rb-&gt;wrpt;</div><div class='ctx'> 	const uint8_t *src = (const uint8_t *)cmd;</div><div class='ctx'> </div><div class='add'>+	if (rb-&gt;capacity == 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	if (dmub_rb_full(rb))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='hunk'>@@ -4702,6 +7320,9 @@ static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,</div><div class='ctx'> 				  uint32_t num_cmds,</div><div class='ctx'> 				  uint32_t *next_rptr)</div><div class='ctx'> {</div><div class='add'>+	if (rb-&gt;capacity == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	*next_rptr = rb-&gt;rptr + DMUB_RB_CMD_SIZE * num_cmds;</div><div class='ctx'> </div><div class='ctx'> 	if (*next_rptr &gt;= rb-&gt;capacity)</div><div class='hunk'>@@ -4765,6 +7386,9 @@ static inline bool dmub_rb_out_front(struct dmub_rb *rb,</div><div class='ctx'>  */</div><div class='ctx'> static inline bool dmub_rb_pop_front(struct dmub_rb *rb)</div><div class='ctx'> {</div><div class='add'>+	if (rb-&gt;capacity == 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	if (dmub_rb_empty(rb))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='hunk'>@@ -4789,6 +7413,9 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)</div><div class='ctx'> 	uint32_t rptr = rb-&gt;rptr;</div><div class='ctx'> 	uint32_t wptr = rb-&gt;wrpt;</div><div class='ctx'> </div><div class='add'>+	if (rb-&gt;capacity == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	while (rptr != wptr) {</div><div class='ctx'> 		uint64_t *data = (uint64_t *)((uint8_t *)(rb-&gt;base_address) + rptr);</div><div class='ctx'> 		uint8_t i;</div><div class='hunk'>@@ -4834,10 +7461,6 @@ static inline void dmub_rb_get_return_data(struct dmub_rb *rb,</div><div class='ctx'> 	dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#if defined(__cplusplus)</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> //==============================================================================</div><div class='ctx'> //&lt;/DMUB_RB&gt;====================================================================</div><div class='ctx'> //==============================================================================</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile<br/>index 50a98448e2e8..468b768c11ae 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/Makefile?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/Makefile</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/Makefile?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/Makefile</a></div><div class='hunk'>@@ -26,6 +26,8 @@ DMUB += dmub_dcn31.o dmub_dcn314.o dmub_dcn315.o dmub_dcn316.o</div><div class='ctx'> DMUB += dmub_dcn32.o</div><div class='ctx'> DMUB += dmub_dcn35.o</div><div class='ctx'> DMUB += dmub_dcn351.o</div><div class='add'>+DMUB += dmub_dcn36.o</div><div class='add'>+DMUB += dmub_dcn401.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c<br/>index cae96fba6349..73888c1bea93 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c</a></div><div class='hunk'>@@ -414,62 +414,66 @@ uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)</div><div class='ctx'> 	return REG_READ(DMCUB_TIMER_CURRENT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)</div><div class='add'>+void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;</div><div class='ctx'> 	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;</div><div class='add'>+	struct dmub_timeout_info timeout = {0};</div><div class='ctx'> </div><div class='del'>-	if (!dmub || !diag_data)</div><div class='add'>+	if (!dmub)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	memset(diag_data, 0, sizeof(*diag_data));</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;dmcub_version = dmub-&gt;fw_version;</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='del'>-	diag_data-&gt;scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='del'>-	diag_data-&gt;scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='del'>-	diag_data-&gt;scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='del'>-	diag_data-&gt;scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='del'>-	diag_data-&gt;scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='del'>-	diag_data-&gt;scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='del'>-	diag_data-&gt;scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='del'>-	diag_data-&gt;scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='del'>-	diag_data-&gt;scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='del'>-	diag_data-&gt;scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='del'>-	diag_data-&gt;scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='del'>-	diag_data-&gt;scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='del'>-	diag_data-&gt;scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='del'>-	diag_data-&gt;scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='del'>-	diag_data-&gt;scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='del'>-	diag_data-&gt;inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='del'>-	diag_data-&gt;inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='del'>-	diag_data-&gt;inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='del'>-	diag_data-&gt;inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+	/* timeout data filled externally, cache before resetting memory */</div><div class='add'>+	timeout = dmub-&gt;debug.timeout_info;</div><div class='add'>+	memset(&amp;dmub-&gt;debug, 0, sizeof(dmub-&gt;debug));</div><div class='add'>+	dmub-&gt;debug.timeout_info = timeout;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.dmcub_version = dmub-&gt;fw_version;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	dmub-&gt;debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	dmub-&gt;debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='add'>+	dmub-&gt;debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='add'>+	dmub-&gt;debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='add'>+	dmub-&gt;debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='add'>+	dmub-&gt;debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='add'>+	dmub-&gt;debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+	dmub-&gt;debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='add'>+	dmub-&gt;debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='add'>+	dmub-&gt;debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='add'>+	dmub-&gt;debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='add'>+	dmub-&gt;debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='add'>+	dmub-&gt;debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='add'>+	dmub-&gt;debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	dmub-&gt;debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_dmub_enabled);</div><div class='del'>-	diag_data-&gt;is_dmcub_enabled = is_dmub_enabled;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_enabled = is_dmub_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_soft_reset = is_soft_reset;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_soft_reset = is_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &amp;is_sec_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_secure_reset = is_sec_reset;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_secure_reset = is_sec_reset;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &amp;is_traceport_enabled);</div><div class='del'>-	diag_data-&gt;is_traceport_en  = is_traceport_enabled;</div><div class='add'>+	dmub-&gt;debug.is_traceport_en  = is_traceport_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &amp;is_cw0_enabled);</div><div class='del'>-	diag_data-&gt;is_cw0_enabled = is_cw0_enabled;</div><div class='add'>+	dmub-&gt;debug.is_cw0_enabled = is_cw0_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &amp;is_cw6_enabled);</div><div class='del'>-	diag_data-&gt;is_cw6_enabled = is_cw6_enabled;</div><div class='add'>+	dmub-&gt;debug.is_cw6_enabled = is_cw6_enabled;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h<br/>index de287b101848..42c1fb4bc73f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h</a></div><div class='hunk'>@@ -247,6 +247,6 @@ bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='del'>-void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);</div><div class='add'>+void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> #endif /* _DMUB_DCN20_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c<br/>index 2bcf5fb87dd9..cd04d7c756c3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c</a></div><div class='hunk'>@@ -83,8 +83,8 @@ static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,</div><div class='ctx'> void dmub_dcn31_reset(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_gpint_data_register cmd;</div><div class='del'>-	const uint32_t timeout = 100;</div><div class='del'>-	uint32_t in_reset, scratch, i, pwait_mode;</div><div class='add'>+	const uint32_t timeout = 100000;</div><div class='add'>+	uint32_t in_reset, is_enabled, scratch, i, pwait_mode;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;in_reset);</div><div class='ctx'> </div><div class='hunk'>@@ -108,7 +108,7 @@ void dmub_dcn31_reset(struct dmub_srv *dmub)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; timeout; ++i) {</div><div class='del'>-			scratch = dmub-&gt;hw_funcs.get_gpint_response(dmub);</div><div class='add'>+			scratch = REG_READ(DMCUB_SCRATCH7);</div><div class='ctx'> 			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='hunk'>@@ -125,9 +125,14 @@ void dmub_dcn31_reset(struct dmub_srv *dmub)</div><div class='ctx'> 		/* Force reset in case we timed out, DMCUB is likely hung. */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='del'>-	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='del'>-	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_enabled);</div><div class='add'>+</div><div class='add'>+	if (is_enabled) {</div><div class='add'>+		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='add'>+		REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);</div><div class='add'>+		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	REG_WRITE(DMCUB_INBOX1_RPTR, 0);</div><div class='ctx'> 	REG_WRITE(DMCUB_INBOX1_WPTR, 0);</div><div class='ctx'> 	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);</div><div class='hunk'>@@ -371,8 +376,11 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu</div><div class='ctx'> 	boot_options.bits.usb4_cm_version = params-&gt;usb4_cm_version;</div><div class='ctx'> 	boot_options.bits.dpia_hpd_int_enable_supported = params-&gt;dpia_hpd_int_enable_supported;</div><div class='ctx'> 	boot_options.bits.power_optimization = params-&gt;power_optimization;</div><div class='add'>+	boot_options.bits.lower_hbr3_phy_ssc = params-&gt;lower_hbr3_phy_ssc;</div><div class='add'>+	boot_options.bits.override_hbr3_pll_vco = params-&gt;override_hbr3_pll_vco;</div><div class='ctx'> </div><div class='ctx'> 	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub-&gt;asic == DMUB_ASIC_DCN31B) ? 1 : 0;</div><div class='add'>+	boot_options.bits.disable_dpia_bw_allocation = params-&gt;disable_dpia_bw_allocation;</div><div class='ctx'> </div><div class='ctx'> 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);</div><div class='ctx'> }</div><div class='hunk'>@@ -408,64 +416,75 @@ uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)</div><div class='ctx'> 	return REG_READ(DMCUB_TIMER_CURRENT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)</div><div class='add'>+void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='del'>-	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;</div><div class='add'>+	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;</div><div class='ctx'> 	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;</div><div class='add'>+	struct dmub_timeout_info timeout = {0};</div><div class='ctx'> </div><div class='del'>-	if (!dmub || !diag_data)</div><div class='add'>+	if (!dmub)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	memset(diag_data, 0, sizeof(*diag_data));</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;dmcub_version = dmub-&gt;fw_version;</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='del'>-	diag_data-&gt;scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='del'>-	diag_data-&gt;scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='del'>-	diag_data-&gt;scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='del'>-	diag_data-&gt;scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='del'>-	diag_data-&gt;scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='del'>-	diag_data-&gt;scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='del'>-	diag_data-&gt;scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='del'>-	diag_data-&gt;scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='del'>-	diag_data-&gt;scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='del'>-	diag_data-&gt;scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='del'>-	diag_data-&gt;scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='del'>-	diag_data-&gt;scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='del'>-	diag_data-&gt;scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='del'>-	diag_data-&gt;scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='del'>-	diag_data-&gt;scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='del'>-	diag_data-&gt;inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='del'>-	diag_data-&gt;inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='del'>-	diag_data-&gt;inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='del'>-	diag_data-&gt;inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+	/* timeout data filled externally, cache before resetting memory */</div><div class='add'>+	timeout = dmub-&gt;debug.timeout_info;</div><div class='add'>+	memset(&amp;dmub-&gt;debug, 0, sizeof(dmub-&gt;debug));</div><div class='add'>+	dmub-&gt;debug.timeout_info = timeout;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.dmcub_version = dmub-&gt;fw_version;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	dmub-&gt;debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	dmub-&gt;debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='add'>+	dmub-&gt;debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='add'>+	dmub-&gt;debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='add'>+	dmub-&gt;debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='add'>+	dmub-&gt;debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='add'>+	dmub-&gt;debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+	dmub-&gt;debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='add'>+	dmub-&gt;debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='add'>+	dmub-&gt;debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='add'>+	dmub-&gt;debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='add'>+	dmub-&gt;debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='add'>+	dmub-&gt;debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='add'>+	dmub-&gt;debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	dmub-&gt;debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_dmub_enabled);</div><div class='del'>-	diag_data-&gt;is_dmcub_enabled = is_dmub_enabled;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_enabled = is_dmub_enabled;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &amp;is_pwait);</div><div class='add'>+	dmub-&gt;debug.is_pwait = is_pwait;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_soft_reset = is_soft_reset;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_soft_reset = is_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &amp;is_sec_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_secure_reset = is_sec_reset;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_secure_reset = is_sec_reset;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &amp;is_traceport_enabled);</div><div class='del'>-	diag_data-&gt;is_traceport_en  = is_traceport_enabled;</div><div class='add'>+	dmub-&gt;debug.is_traceport_en  = is_traceport_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &amp;is_cw0_enabled);</div><div class='del'>-	diag_data-&gt;is_cw0_enabled = is_cw0_enabled;</div><div class='add'>+	dmub-&gt;debug.is_cw0_enabled = is_cw0_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &amp;is_cw6_enabled);</div><div class='del'>-	diag_data-&gt;is_cw6_enabled = is_cw6_enabled;</div><div class='add'>+	dmub-&gt;debug.is_cw6_enabled = is_cw6_enabled;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dmub_dcn31_should_detect(struct dmub_srv *dmub)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h<br/>index eccdab4986ce..1c43ef2bca66 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h</a></div><div class='hunk'>@@ -251,7 +251,7 @@ void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);</div><div class='ctx'> </div><div class='ctx'> uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='del'>-void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);</div><div class='add'>+void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> bool dmub_dcn31_should_detect(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c<br/>index 0d521eeda050..7e9856289910 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c</a></div><div class='hunk'>@@ -89,44 +89,58 @@ static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,</div><div class='ctx'> void dmub_dcn32_reset(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_gpint_data_register cmd;</div><div class='del'>-	const uint32_t timeout = 30;</div><div class='del'>-	uint32_t in_reset, scratch, i;</div><div class='add'>+	const uint32_t timeout_us = 1 * 1000 * 1000; //1s</div><div class='add'>+	const uint32_t poll_delay_us = 1; //1us</div><div class='add'>+	uint32_t i = 0;</div><div class='add'>+	uint32_t enabled, in_reset, scratch, pwait_mode;</div><div class='ctx'> </div><div class='del'>-	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;in_reset);</div><div class='add'>+	REG_GET(DMCUB_CNTL,</div><div class='add'>+			DMCUB_ENABLE, &amp;enabled);</div><div class='add'>+	REG_GET(DMCUB_CNTL2,</div><div class='add'>+			DMCUB_SOFT_RESET, &amp;in_reset);</div><div class='ctx'> </div><div class='del'>-	if (in_reset == 0) {</div><div class='add'>+	if (enabled &amp;&amp; in_reset == 0) {</div><div class='ctx'> 		cmd.bits.status = 1;</div><div class='ctx'> 		cmd.bits.command_code = DMUB_GPINT__STOP_FW;</div><div class='ctx'> 		cmd.bits.param = 0;</div><div class='ctx'> </div><div class='ctx'> 		dmub-&gt;hw_funcs.set_gpint(dmub, cmd);</div><div class='ctx'> </div><div class='del'>-		/**</div><div class='del'>-		 * Timeout covers both the ACK and the wait</div><div class='del'>-		 * for remaining work to finish.</div><div class='del'>-		 *</div><div class='del'>-		 * This is mostly bound by the PHY disable sequence.</div><div class='del'>-		 * Each register check will be greater than 1us, so</div><div class='del'>-		 * don't bother using udelay.</div><div class='del'>-		 */</div><div class='del'>-</div><div class='del'>-		for (i = 0; i &lt; timeout; ++i) {</div><div class='del'>-			if (dmub-&gt;hw_funcs.is_gpint_acked(dmub, cmd))</div><div class='add'>+		for (; i &lt; timeout_us; i++) {</div><div class='add'>+			scratch = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)</div><div class='ctx'> 				break;</div><div class='add'>+</div><div class='add'>+			udelay(poll_delay_us);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; timeout; ++i) {</div><div class='del'>-			scratch = dmub-&gt;hw_funcs.get_gpint_response(dmub);</div><div class='del'>-			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)</div><div class='add'>+		for (; i &lt; timeout_us; i++) {</div><div class='add'>+			REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &amp;pwait_mode);</div><div class='add'>+			if (pwait_mode &amp; (1 &lt;&lt; 0))</div><div class='ctx'> 				break;</div><div class='add'>+</div><div class='add'>+			udelay(poll_delay_us);</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		/* Force reset in case we timed out, DMCUB is likely hung. */</div><div class='add'>+	if (enabled) {</div><div class='add'>+		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='add'>+		udelay(1);</div><div class='add'>+		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='del'>-	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='del'>-	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);</div><div class='add'>+	if (i &gt;= timeout_us) {</div><div class='add'>+		/* timeout should never occur */</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0);</div><div class='add'>+</div><div class='ctx'> 	REG_WRITE(DMCUB_INBOX1_RPTR, 0);</div><div class='ctx'> 	REG_WRITE(DMCUB_INBOX1_WPTR, 0);</div><div class='ctx'> 	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);</div><div class='hunk'>@@ -157,7 +171,9 @@ void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,</div><div class='ctx'> </div><div class='ctx'> 	dmub_dcn32_get_fb_base_offset(dmub, &amp;fb_base, &amp;fb_offset);</div><div class='ctx'> </div><div class='add'>+	/* reset and disable DMCUB and MMHUBBUB DMUIF */</div><div class='ctx'> 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);</div><div class='add'>+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='ctx'> </div><div class='ctx'> 	dmub_dcn32_translate_addr(&amp;cw0-&gt;offset, fb_base, fb_offset, &amp;offset);</div><div class='ctx'> </div><div class='hunk'>@@ -187,7 +203,9 @@ void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_addr offset;</div><div class='ctx'> </div><div class='add'>+	/* reset and disable DMCUB and MMHUBBUB DMUIF */</div><div class='ctx'> 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);</div><div class='add'>+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='ctx'> </div><div class='ctx'> 	offset = cw0-&gt;offset;</div><div class='ctx'> </div><div class='hunk'>@@ -417,67 +435,72 @@ uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)</div><div class='ctx'> 	return REG_READ(DMCUB_TIMER_CURRENT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)</div><div class='add'>+void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='del'>-	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;</div><div class='del'>-	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;</div><div class='add'>+	uint32_t is_dmub_enabled, is_soft_reset, is_pwait;</div><div class='add'>+	uint32_t is_traceport_enabled, is_cw6_enabled;</div><div class='add'>+	struct dmub_timeout_info timeout = {0};</div><div class='ctx'> </div><div class='del'>-	if (!dmub || !diag_data)</div><div class='add'>+	if (!dmub)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	memset(diag_data, 0, sizeof(*diag_data));</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;dmcub_version = dmub-&gt;fw_version;</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='del'>-	diag_data-&gt;scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='del'>-	diag_data-&gt;scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='del'>-	diag_data-&gt;scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='del'>-	diag_data-&gt;scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='del'>-	diag_data-&gt;scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='del'>-	diag_data-&gt;scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='del'>-	diag_data-&gt;scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='del'>-	diag_data-&gt;scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='del'>-	diag_data-&gt;scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='del'>-	diag_data-&gt;scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='del'>-	diag_data-&gt;scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='del'>-	diag_data-&gt;scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='del'>-	diag_data-&gt;scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='del'>-	diag_data-&gt;scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='del'>-	diag_data-&gt;scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='del'>-	diag_data-&gt;scratch[16] = REG_READ(DMCUB_SCRATCH16);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='del'>-	diag_data-&gt;inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='del'>-	diag_data-&gt;inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='del'>-	diag_data-&gt;inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='del'>-	diag_data-&gt;inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+	/* timeout data filled externally, cache before resetting memory */</div><div class='add'>+	timeout = dmub-&gt;debug.timeout_info;</div><div class='add'>+	memset(&amp;dmub-&gt;debug, 0, sizeof(dmub-&gt;debug));</div><div class='add'>+	dmub-&gt;debug.timeout_info = timeout;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.dmcub_version = dmub-&gt;fw_version;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	dmub-&gt;debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	dmub-&gt;debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='add'>+	dmub-&gt;debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='add'>+	dmub-&gt;debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='add'>+	dmub-&gt;debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='add'>+	dmub-&gt;debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='add'>+	dmub-&gt;debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+	dmub-&gt;debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='add'>+	dmub-&gt;debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='add'>+	dmub-&gt;debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='add'>+	dmub-&gt;debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='add'>+	dmub-&gt;debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='add'>+	dmub-&gt;debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='add'>+	dmub-&gt;debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	dmub-&gt;debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='add'>+	dmub-&gt;debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_dmub_enabled);</div><div class='del'>-	diag_data-&gt;is_dmcub_enabled = is_dmub_enabled;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_enabled = is_dmub_enabled;</div><div class='ctx'> </div><div class='del'>-	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_soft_reset = is_soft_reset;</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &amp;is_pwait);</div><div class='add'>+	dmub-&gt;debug.is_pwait = is_pwait;</div><div class='ctx'> </div><div class='del'>-	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &amp;is_sec_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_secure_reset = is_sec_reset;</div><div class='add'>+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='add'>+	dmub-&gt;debug.is_dmcub_soft_reset = is_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &amp;is_traceport_enabled);</div><div class='del'>-	diag_data-&gt;is_traceport_en  = is_traceport_enabled;</div><div class='del'>-</div><div class='del'>-	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &amp;is_cw0_enabled);</div><div class='del'>-	diag_data-&gt;is_cw0_enabled = is_cw0_enabled;</div><div class='add'>+	dmub-&gt;debug.is_traceport_en  = is_traceport_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &amp;is_cw6_enabled);</div><div class='del'>-	diag_data-&gt;is_cw6_enabled = is_cw6_enabled;</div><div class='add'>+	dmub-&gt;debug.is_cw6_enabled = is_cw6_enabled;</div><div class='ctx'> </div><div class='del'>-	diag_data-&gt;gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);</div><div class='add'>+	dmub-&gt;debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);</div><div class='ctx'> }</div><div class='ctx'> void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h<br/>index 29c1132951af..daf81027d663 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h</a></div><div class='hunk'>@@ -89,6 +89,9 @@ struct dmub_srv;</div><div class='ctx'> 	DMUB_SR(DMCUB_REGION5_OFFSET) \</div><div class='ctx'> 	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \</div><div class='ctx'> 	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION6_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \</div><div class='ctx'> 	DMUB_SR(DMCUB_SCRATCH0) \</div><div class='ctx'> 	DMUB_SR(DMCUB_SCRATCH1) \</div><div class='ctx'> 	DMUB_SR(DMCUB_SCRATCH2) \</div><div class='hunk'>@@ -155,6 +158,8 @@ struct dmub_srv;</div><div class='ctx'> 	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \</div><div class='ctx'> 	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \</div><div class='ctx'> 	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \</div><div class='ctx'> 	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \</div><div class='ctx'> 	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \</div><div class='ctx'> 	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \</div><div class='hunk'>@@ -162,7 +167,8 @@ struct dmub_srv;</div><div class='ctx'> 	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \</div><div class='ctx'> 	DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \</div><div class='ctx'> 	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \</div><div class='del'>-	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK)</div><div class='add'>+	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \</div><div class='add'>+	DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS)</div><div class='ctx'> </div><div class='ctx'> struct dmub_srv_dcn32_reg_offset {</div><div class='ctx'> #define DMUB_SR(reg) uint32_t reg;</div><div class='hunk'>@@ -254,7 +260,7 @@ void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);</div><div class='ctx'> </div><div class='ctx'> uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='del'>-void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);</div><div class='add'>+void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);</div><div class='ctx'> void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c<br/>index 53f359f3fae2..e13557ed97be 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c</a></div><div class='hunk'>@@ -88,23 +88,19 @@ static inline void dmub_dcn35_translate_addr(const union dmub_addr *addr_in,</div><div class='ctx'> void dmub_dcn35_reset(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_gpint_data_register cmd;</div><div class='del'>-	const uint32_t timeout = 100;</div><div class='add'>+	const uint32_t timeout = 100000;</div><div class='ctx'> 	uint32_t in_reset, is_enabled, scratch, i, pwait_mode;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;in_reset);</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_enabled);</div><div class='ctx'> </div><div class='del'>-	if (in_reset == 0) {</div><div class='add'>+	if (in_reset == 0 &amp;&amp; is_enabled != 0) {</div><div class='ctx'> 		cmd.bits.status = 1;</div><div class='ctx'> 		cmd.bits.command_code = DMUB_GPINT__STOP_FW;</div><div class='ctx'> 		cmd.bits.param = 0;</div><div class='ctx'> </div><div class='ctx'> 		dmub-&gt;hw_funcs.set_gpint(dmub, cmd);</div><div class='ctx'> </div><div class='del'>-		/**</div><div class='del'>-		 * Timeout covers both the ACK and the wait</div><div class='del'>-		 * for remaining work to finish.</div><div class='del'>-		 */</div><div class='del'>-</div><div class='ctx'> 		for (i = 0; i &lt; timeout; ++i) {</div><div class='ctx'> 			if (dmub-&gt;hw_funcs.is_gpint_acked(dmub, cmd))</div><div class='ctx'> 				break;</div><div class='hunk'>@@ -113,7 +109,7 @@ void dmub_dcn35_reset(struct dmub_srv *dmub)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; timeout; ++i) {</div><div class='del'>-			scratch = dmub-&gt;hw_funcs.get_gpint_response(dmub);</div><div class='add'>+			scratch = REG_READ(DMCUB_SCRATCH7);</div><div class='ctx'> 			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='hunk'>@@ -130,11 +126,9 @@ void dmub_dcn35_reset(struct dmub_srv *dmub)</div><div class='ctx'> 		/* Force reset in case we timed out, DMCUB is likely hung. */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_enabled);</div><div class='del'>-</div><div class='ctx'> 	if (is_enabled) {</div><div class='ctx'> 		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='del'>-		REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);</div><div class='add'>+		udelay(1);</div><div class='ctx'> 		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -160,11 +154,7 @@ void dmub_dcn35_reset_release(struct dmub_srv *dmub)</div><div class='ctx'> 		     LONO_SOCCLK_GATE_DISABLE, 1,</div><div class='ctx'> 		     LONO_DMCUBCLK_GATE_DISABLE, 1);</div><div class='ctx'> </div><div class='del'>-	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);</div><div class='del'>-	udelay(1);</div><div class='ctx'> 	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);</div><div class='del'>-	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='del'>-	udelay(1);</div><div class='ctx'> 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);</div><div class='ctx'> 	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);</div><div class='ctx'> }</div><div class='hunk'>@@ -411,15 +401,24 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_fw_boot_options boot_options = {0};</div><div class='ctx'> </div><div class='add'>+	if (!dmub-&gt;dpia_supported) {</div><div class='add'>+		dmub-&gt;dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	boot_options.bits.z10_disable = params-&gt;disable_z10;</div><div class='ctx'> 	boot_options.bits.dpia_supported = params-&gt;dpia_supported;</div><div class='del'>-	boot_options.bits.enable_dpia = params-&gt;disable_dpia == true ? 0:1;</div><div class='add'>+	boot_options.bits.enable_dpia = dmub-&gt;dpia_supported &amp;&amp; !params-&gt;disable_dpia;</div><div class='ctx'> 	boot_options.bits.usb4_cm_version = params-&gt;usb4_cm_version;</div><div class='ctx'> 	boot_options.bits.dpia_hpd_int_enable_supported = params-&gt;dpia_hpd_int_enable_supported;</div><div class='ctx'> 	boot_options.bits.power_optimization = params-&gt;power_optimization;</div><div class='ctx'> 	boot_options.bits.disable_clk_ds = params-&gt;disallow_dispclk_dppclk_ds;</div><div class='ctx'> 	boot_options.bits.disable_clk_gate = params-&gt;disable_clock_gate;</div><div class='ctx'> 	boot_options.bits.ips_disable = params-&gt;disable_ips;</div><div class='add'>+	boot_options.bits.ips_sequential_ono = params-&gt;ips_sequential_ono;</div><div class='add'>+	boot_options.bits.disable_sldo_opt = params-&gt;disable_sldo_opt;</div><div class='add'>+	boot_options.bits.enable_non_transparent_setconfig = params-&gt;enable_non_transparent_setconfig;</div><div class='add'>+	boot_options.bits.lower_hbr3_phy_ssc = params-&gt;lower_hbr3_phy_ssc;</div><div class='add'>+	boot_options.bits.disable_dpia_bw_allocation = params-&gt;disable_dpia_bw_allocation;</div><div class='ctx'> </div><div class='ctx'> 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);</div><div class='ctx'> }</div><div class='hunk'>@@ -455,68 +454,112 @@ uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)</div><div class='ctx'> 	return REG_READ(DMCUB_TIMER_CURRENT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)</div><div class='add'>+void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='del'>-	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;</div><div class='del'>-	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;</div><div class='add'>+	uint32_t is_dmub_enabled, is_soft_reset, is_pwait;</div><div class='add'>+	uint32_t is_traceport_enabled, is_cw6_enabled;</div><div class='add'>+	struct dmub_timeout_info timeout = {0};</div><div class='ctx'> </div><div class='del'>-	if (!dmub || !diag_data)</div><div class='add'>+	if (!dmub)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	memset(diag_data, 0, sizeof(*diag_data));</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;dmcub_version = dmub-&gt;fw_version;</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='del'>-	diag_data-&gt;scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='del'>-	diag_data-&gt;scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='del'>-	diag_data-&gt;scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='del'>-	diag_data-&gt;scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='del'>-	diag_data-&gt;scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='del'>-	diag_data-&gt;scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='del'>-	diag_data-&gt;scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='del'>-	diag_data-&gt;scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='del'>-	diag_data-&gt;scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='del'>-	diag_data-&gt;scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='del'>-	diag_data-&gt;scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='del'>-	diag_data-&gt;scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='del'>-	diag_data-&gt;scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='del'>-	diag_data-&gt;scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='del'>-	diag_data-&gt;scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='del'>-	diag_data-&gt;scratch[16] = REG_READ(DMCUB_SCRATCH16);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='del'>-	diag_data-&gt;data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='del'>-	diag_data-&gt;inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='del'>-	diag_data-&gt;inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='del'>-</div><div class='del'>-	diag_data-&gt;inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='del'>-	diag_data-&gt;inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='del'>-	diag_data-&gt;inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+	/* timeout data filled externally, cache before resetting memory */</div><div class='add'>+	timeout = dmub-&gt;debug.timeout_info;</div><div class='add'>+	memset(&amp;dmub-&gt;debug, 0, sizeof(dmub-&gt;debug));</div><div class='add'>+	dmub-&gt;debug.timeout_info = timeout;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.dmcub_version = dmub-&gt;fw_version;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	dmub-&gt;debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	dmub-&gt;debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='add'>+	dmub-&gt;debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='add'>+	dmub-&gt;debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='add'>+	dmub-&gt;debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='add'>+	dmub-&gt;debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='add'>+	dmub-&gt;debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+	dmub-&gt;debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='add'>+	dmub-&gt;debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='add'>+	dmub-&gt;debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='add'>+	dmub-&gt;debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='add'>+	dmub-&gt;debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='add'>+	dmub-&gt;debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='add'>+	dmub-&gt;debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	dmub-&gt;debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='add'>+	dmub-&gt;debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_dmub_enabled);</div><div class='del'>-	diag_data-&gt;is_dmcub_enabled = is_dmub_enabled;</div><div class='add'>+	dmub-&gt;debug.is_dmcub_enabled = is_dmub_enabled;</div><div class='ctx'> </div><div class='del'>-	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_soft_reset = is_soft_reset;</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &amp;is_pwait);</div><div class='add'>+	dmub-&gt;debug.is_pwait = is_pwait;</div><div class='ctx'> </div><div class='del'>-	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &amp;is_sec_reset);</div><div class='del'>-	diag_data-&gt;is_dmcub_secure_reset = is_sec_reset;</div><div class='add'>+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='add'>+	dmub-&gt;debug.is_dmcub_soft_reset = is_soft_reset;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &amp;is_traceport_enabled);</div><div class='del'>-	diag_data-&gt;is_traceport_en  = is_traceport_enabled;</div><div class='del'>-</div><div class='del'>-	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &amp;is_cw0_enabled);</div><div class='del'>-	diag_data-&gt;is_cw0_enabled = is_cw0_enabled;</div><div class='add'>+	dmub-&gt;debug.is_traceport_en  = is_traceport_enabled;</div><div class='ctx'> </div><div class='ctx'> 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &amp;is_cw6_enabled);</div><div class='del'>-	diag_data-&gt;is_cw6_enabled = is_cw6_enabled;</div><div class='add'>+	dmub-&gt;debug.is_cw6_enabled = is_cw6_enabled;</div><div class='ctx'> </div><div class='del'>-	diag_data-&gt;gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);</div><div class='add'>+	dmub-&gt;debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint64_t region3_cw5_offset;</div><div class='add'>+	uint32_t top_addr, top_addr_enable, offset_low;</div><div class='add'>+	uint32_t offset_high, base_addr, fw_version;</div><div class='add'>+	bool is_vbios_fw = false;</div><div class='add'>+</div><div class='add'>+	memset(&amp;dmub-&gt;preos_info, 0, sizeof(dmub-&gt;preos_info));</div><div class='add'>+</div><div class='add'>+	fw_version = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	is_vbios_fw = ((fw_version &gt;&gt; 6) &amp; 0x01) ? true : false;</div><div class='add'>+	if (!is_vbios_fw)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;preos_info.boot_status = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	dmub-&gt;preos_info.fw_version = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	dmub-&gt;preos_info.boot_options = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,</div><div class='add'>+		DMCUB_REGION3_CW5_ENABLE, &amp;top_addr_enable);</div><div class='add'>+	if (top_addr_enable) {</div><div class='add'>+		dmub_dcn35_get_fb_base_offset(dmub,</div><div class='add'>+			&amp;dmub-&gt;preos_info.fb_base, &amp;dmub-&gt;preos_info.fb_offset);</div><div class='add'>+		offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET);</div><div class='add'>+		offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH);</div><div class='add'>+		region3_cw5_offset = ((uint64_t)offset_high &lt;&lt; 32) | offset_low;</div><div class='add'>+		dmub-&gt;preos_info.trace_buffer_phy_addr = region3_cw5_offset</div><div class='add'>+			- dmub-&gt;preos_info.fb_base + dmub-&gt;preos_info.fb_offset;</div><div class='add'>+</div><div class='add'>+		REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS,</div><div class='add'>+			DMCUB_REGION3_CW5_TOP_ADDRESS, &amp;top_addr);</div><div class='add'>+		base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) &amp; 0x1FFFFFFF;</div><div class='add'>+		dmub-&gt;preos_info.trace_buffer_size =</div><div class='add'>+			(top_addr &gt; base_addr) ? (top_addr - base_addr + 1) : 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	/* DMCUB_REGION3_TMR_AXI_SPACE values:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h<br/>index 686e97c00ccc..92e6695a2c9b 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h</a></div><div class='hunk'>@@ -269,7 +269,7 @@ void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);</div><div class='ctx'> </div><div class='ctx'> uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='del'>-void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);</div><div class='add'>+void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='hunk'>@@ -285,4 +285,6 @@ bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub);</div><div class='ctx'> </div><div class='ctx'> void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);</div><div class='ctx'> </div><div class='add'>+bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='ctx'> #endif /* _DMUB_DCN35_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c<br/>new file mode 100644<br/>index 000000000000..b1ce09d48920<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#include "../dmub_srv.h"</div><div class='add'>+#include "dmub_reg.h"</div><div class='add'>+#include "dmub_dcn36.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_3_6_0_offset.h"</div><div class='add'>+#include "dcn/dcn_3_6_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#define BASE_INNER(seg) ctx-&gt;dcn_reg_offsets[seg]</div><div class='add'>+#define CTX dmub</div><div class='add'>+#define REGS dmub-&gt;regs_dcn35</div><div class='add'>+#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name</div><div class='add'>+</div><div class='add'>+void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dmub_srv_dcn35_regs *regs = dmub-&gt;regs_dcn35;</div><div class='add'>+#define REG_STRUCT regs</div><div class='add'>+</div><div class='add'>+#define DMUB_SR(reg) REG_STRUCT-&gt;offset.reg = REG_OFFSET_EXP(reg);</div><div class='add'>+	DMUB_DCN35_REGS()</div><div class='add'>+	DMCUB_INTERNAL_REGS()</div><div class='add'>+#undef DMUB_SR</div><div class='add'>+</div><div class='add'>+#define DMUB_SF(reg, field) REG_STRUCT-&gt;mask.reg##__##field = FD_MASK(reg, field);</div><div class='add'>+	DMUB_DCN35_FIELDS()</div><div class='add'>+#undef DMUB_SF</div><div class='add'>+</div><div class='add'>+#define DMUB_SF(reg, field) REG_STRUCT-&gt;shift.reg##__##field = FD_SHIFT(reg, field);</div><div class='add'>+	DMUB_DCN35_FIELDS()</div><div class='add'>+#undef DMUB_SF</div><div class='add'>+#undef REG_STRUCT</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h<br/>new file mode 100644<br/>index 000000000000..57850550f682<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+#ifndef _DMUB_DCN36_H_</div><div class='add'>+#define _DMUB_DCN36_H_</div><div class='add'>+</div><div class='add'>+#include "dmub_dcn35.h"</div><div class='add'>+</div><div class='add'>+struct dmub_srv;</div><div class='add'>+</div><div class='add'>+void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);</div><div class='add'>+</div><div class='add'>+#endif /* _DMUB_DCN36_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c<br/>new file mode 100644<br/>index 000000000000..95542299e3b3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c</a></div><div class='hunk'>@@ -0,0 +1,678 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#include "../dmub_srv.h"</div><div class='add'>+#include "dmub_reg.h"</div><div class='add'>+#include "dmub_dcn401.h"</div><div class='add'>+</div><div class='add'>+#include "dcn/dcn_4_1_0_offset.h"</div><div class='add'>+#include "dcn/dcn_4_1_0_sh_mask.h"</div><div class='add'>+</div><div class='add'>+#define DCN_BASE__INST0_SEG2                       0x000034C0</div><div class='add'>+</div><div class='add'>+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg</div><div class='add'>+#define CTX dmub</div><div class='add'>+#define REGS dmub-&gt;regs_dcn401</div><div class='add'>+#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)</div><div class='add'>+</div><div class='add'>+const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs = {</div><div class='add'>+#define DMUB_SR(reg) REG_OFFSET_EXP(reg),</div><div class='add'>+	{</div><div class='add'>+		DMUB_DCN401_REGS()</div><div class='add'>+		DMCUB_INTERNAL_REGS()</div><div class='add'>+	},</div><div class='add'>+#undef DMUB_SR</div><div class='add'>+</div><div class='add'>+#define DMUB_SF(reg, field) FD_MASK(reg, field),</div><div class='add'>+		{ DMUB_DCN401_FIELDS() },</div><div class='add'>+#undef DMUB_SF</div><div class='add'>+</div><div class='add'>+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),</div><div class='add'>+		{ DMUB_DCN401_FIELDS() },</div><div class='add'>+#undef DMUB_SF</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,</div><div class='add'>+		uint64_t *fb_base,</div><div class='add'>+		uint64_t *fb_offset)</div><div class='add'>+{</div><div class='add'>+	uint32_t tmp;</div><div class='add'>+</div><div class='add'>+	if (dmub-&gt;fb_base || dmub-&gt;fb_offset) {</div><div class='add'>+		*fb_base = dmub-&gt;fb_base;</div><div class='add'>+		*fb_offset = dmub-&gt;fb_offset;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &amp;tmp);</div><div class='add'>+	*fb_base = (uint64_t)tmp &lt;&lt; 24;</div><div class='add'>+</div><div class='add'>+	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &amp;tmp);</div><div class='add'>+	*fb_offset = (uint64_t)tmp &lt;&lt; 24;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void dmub_dcn401_translate_addr(const union dmub_addr *addr_in,</div><div class='add'>+		uint64_t fb_base,</div><div class='add'>+		uint64_t fb_offset,</div><div class='add'>+		union dmub_addr *addr_out)</div><div class='add'>+{</div><div class='add'>+	addr_out-&gt;quad_part = addr_in-&gt;quad_part - fb_base + fb_offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_reset(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	union dmub_gpint_data_register cmd;</div><div class='add'>+	const uint32_t timeout_us = 1 * 1000 * 1000; //1s</div><div class='add'>+	const uint32_t poll_delay_us = 1; //1us</div><div class='add'>+	uint32_t i = 0;</div><div class='add'>+	uint32_t enabled, in_reset, scratch, pwait_mode;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_CNTL,</div><div class='add'>+			DMCUB_ENABLE, &amp;enabled);</div><div class='add'>+	REG_GET(DMCUB_CNTL2,</div><div class='add'>+			DMCUB_SOFT_RESET, &amp;in_reset);</div><div class='add'>+</div><div class='add'>+	if (enabled &amp;&amp; in_reset == 0) {</div><div class='add'>+		cmd.bits.status = 1;</div><div class='add'>+		cmd.bits.command_code = DMUB_GPINT__STOP_FW;</div><div class='add'>+		cmd.bits.param = 0;</div><div class='add'>+</div><div class='add'>+		dmub-&gt;hw_funcs.set_gpint(dmub, cmd);</div><div class='add'>+</div><div class='add'>+		for (; i &lt; timeout_us; i++) {</div><div class='add'>+			scratch = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			udelay(poll_delay_us);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (; i &lt; timeout_us; i++) {</div><div class='add'>+			REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &amp;pwait_mode);</div><div class='add'>+			if (pwait_mode &amp; (1 &lt;&lt; 0))</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			udelay(poll_delay_us);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (enabled) {</div><div class='add'>+		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);</div><div class='add'>+		udelay(1);</div><div class='add'>+		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= timeout_us) {</div><div class='add'>+		/* timeout should never occur */</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_INBOX1_RPTR, 0);</div><div class='add'>+	REG_WRITE(DMCUB_INBOX1_WPTR, 0);</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);</div><div class='add'>+	REG_WRITE(DMCUB_SCRATCH0, 0);</div><div class='add'>+</div><div class='add'>+	/* Clear the GPINT command manually so we don't reset again. */</div><div class='add'>+	cmd.all = 0;</div><div class='add'>+	dmub-&gt;hw_funcs.set_gpint(dmub, cmd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_reset_release(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);</div><div class='add'>+	REG_WRITE(DMCUB_SCRATCH15, dmub-&gt;psp_version &amp; 0x001100FF);</div><div class='add'>+	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);</div><div class='add'>+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,</div><div class='add'>+		const struct dmub_window *cw0,</div><div class='add'>+		const struct dmub_window *cw1)</div><div class='add'>+{</div><div class='add'>+	union dmub_addr offset;</div><div class='add'>+	uint64_t fb_base, fb_offset;</div><div class='add'>+</div><div class='add'>+	dmub_dcn401_get_fb_base_offset(dmub, &amp;fb_base, &amp;fb_offset);</div><div class='add'>+</div><div class='add'>+	/* reset and disable DMCUB and MMHUBBUB DMUIF */</div><div class='add'>+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);</div><div class='add'>+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='add'>+</div><div class='add'>+	dmub_dcn401_translate_addr(&amp;cw0-&gt;offset, fb_base, fb_offset, &amp;offset);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW0_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	dmub_dcn401_translate_addr(&amp;cw1-&gt;offset, fb_base, fb_offset, &amp;offset);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW1_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	/* release DMCUB reset only to prevent premature execution */</div><div class='add'>+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,</div><div class='add'>+			0x20);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,</div><div class='add'>+		      const struct dmub_window *cw0,</div><div class='add'>+		      const struct dmub_window *cw1)</div><div class='add'>+{</div><div class='add'>+	union dmub_addr offset;</div><div class='add'>+</div><div class='add'>+	/* reset and disable DMCUB and MMHUBBUB DMUIF */</div><div class='add'>+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);</div><div class='add'>+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);</div><div class='add'>+</div><div class='add'>+	offset = cw0-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW0_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	offset = cw1-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW1_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	/* release DMCUB reset only to prevent premature execution */</div><div class='add'>+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,</div><div class='add'>+			0x20);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_windows(struct dmub_srv *dmub,</div><div class='add'>+		const struct dmub_window *cw2,</div><div class='add'>+		const struct dmub_window *cw3,</div><div class='add'>+		const struct dmub_window *cw4,</div><div class='add'>+		const struct dmub_window *cw5,</div><div class='add'>+		const struct dmub_window *cw6,</div><div class='add'>+		const struct dmub_window *region6)</div><div class='add'>+{</div><div class='add'>+	union dmub_addr offset;</div><div class='add'>+</div><div class='add'>+	offset = cw3-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW3_TOP_ADDRESS, cw3-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW3_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	offset = cw4-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW4_TOP_ADDRESS, cw4-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW4_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	offset = cw5-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW5_TOP_ADDRESS, cw5-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW5_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION5_TOP_ADDRESS,</div><div class='add'>+			cw5-&gt;region.top - cw5-&gt;region.base - 1,</div><div class='add'>+			DMCUB_REGION5_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	offset = cw6-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6-&gt;region.base);</div><div class='add'>+	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,</div><div class='add'>+			DMCUB_REGION3_CW6_TOP_ADDRESS, cw6-&gt;region.top,</div><div class='add'>+			DMCUB_REGION3_CW6_ENABLE, 1);</div><div class='add'>+</div><div class='add'>+	offset = region6-&gt;offset;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);</div><div class='add'>+	REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);</div><div class='add'>+	REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0,</div><div class='add'>+		  DMCUB_REGION6_TOP_ADDRESS,</div><div class='add'>+		  region6-&gt;region.top - region6-&gt;region.base - 1,</div><div class='add'>+		  DMCUB_REGION6_ENABLE, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,</div><div class='add'>+		const struct dmub_region *inbox1)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1-&gt;base);</div><div class='add'>+	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1-&gt;top - inbox1-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	return REG_READ(DMCUB_INBOX1_WPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	return REG_READ(DMCUB_INBOX1_RPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,</div><div class='add'>+		const struct dmub_region *outbox1)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1-&gt;base);</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1-&gt;top - outbox1-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	/**</div><div class='add'>+	 * outbox1 wptr register is accessed without locks (dal &amp; dc)</div><div class='add'>+	 * and to be called only by dmub_srv_stat_get_notification()</div><div class='add'>+	 */</div><div class='add'>+	return REG_READ(DMCUB_OUTBOX1_WPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)</div><div class='add'>+{</div><div class='add'>+	/**</div><div class='add'>+	 * outbox1 rptr register is accessed without locks (dal &amp; dc)</div><div class='add'>+	 * and to be called only by dmub_srv_stat_get_notification()</div><div class='add'>+	 */</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	union dmub_fw_boot_status status;</div><div class='add'>+	uint32_t is_hw_init;</div><div class='add'>+</div><div class='add'>+	status.all = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_hw_init);</div><div class='add'>+</div><div class='add'>+	return is_hw_init != 0 &amp;&amp; status.bits.dal_fw;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_dcn401_is_supported(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t supported = 0;</div><div class='add'>+</div><div class='add'>+	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &amp;supported);</div><div class='add'>+</div><div class='add'>+	return supported;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_gpint(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_gpint_data_register reg)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_gpint_data_register reg)</div><div class='add'>+{</div><div class='add'>+	union dmub_gpint_data_register test;</div><div class='add'>+</div><div class='add'>+	reg.bits.status = 0;</div><div class='add'>+	test.all = REG_READ(DMCUB_GPINT_DATAIN1);</div><div class='add'>+</div><div class='add'>+	return test.all == reg.all;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	return REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);</div><div class='add'>+	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);</div><div class='add'>+	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);</div><div class='add'>+</div><div class='add'>+	return dataout;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	union dmub_fw_boot_status status;</div><div class='add'>+</div><div class='add'>+	status.all = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)</div><div class='add'>+{</div><div class='add'>+	union dmub_fw_boot_options boot_options = {0};</div><div class='add'>+</div><div class='add'>+	boot_options.bits.z10_disable = params-&gt;disable_z10;</div><div class='add'>+</div><div class='add'>+	boot_options.bits.skip_phy_access = params-&gt;disallow_phy_access;</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)</div><div class='add'>+{</div><div class='add'>+	union dmub_fw_boot_options boot_options;</div><div class='add'>+	boot_options.all = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	boot_options.bits.skip_phy_init_panel_sequence = skip;</div><div class='add'>+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,</div><div class='add'>+		const struct dmub_region *outbox0)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0-&gt;base);</div><div class='add'>+</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0-&gt;top - outbox0-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	return REG_READ(DMCUB_OUTBOX0_WPTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	return REG_READ(DMCUB_TIMER_CURRENT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait;</div><div class='add'>+	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;</div><div class='add'>+	struct dmub_timeout_info timeout = {0};</div><div class='add'>+</div><div class='add'>+	if (!dmub)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* timeout data filled externally, cache before resetting memory */</div><div class='add'>+	timeout = dmub-&gt;debug.timeout_info;</div><div class='add'>+	memset(&amp;dmub-&gt;debug, 0, sizeof(dmub-&gt;debug));</div><div class='add'>+	dmub-&gt;debug.timeout_info = timeout;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.dmcub_version = dmub-&gt;fw_version;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);</div><div class='add'>+	dmub-&gt;debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);</div><div class='add'>+	dmub-&gt;debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);</div><div class='add'>+	dmub-&gt;debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);</div><div class='add'>+	dmub-&gt;debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);</div><div class='add'>+	dmub-&gt;debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);</div><div class='add'>+	dmub-&gt;debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);</div><div class='add'>+	dmub-&gt;debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);</div><div class='add'>+	dmub-&gt;debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);</div><div class='add'>+	dmub-&gt;debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);</div><div class='add'>+	dmub-&gt;debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);</div><div class='add'>+	dmub-&gt;debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);</div><div class='add'>+	dmub-&gt;debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);</div><div class='add'>+	dmub-&gt;debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);</div><div class='add'>+	dmub-&gt;debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);</div><div class='add'>+	dmub-&gt;debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);</div><div class='add'>+	dmub-&gt;debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);</div><div class='add'>+	dmub-&gt;debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);</div><div class='add'>+	dmub-&gt;debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);</div><div class='add'>+	dmub-&gt;debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &amp;is_dmub_enabled);</div><div class='add'>+	dmub-&gt;debug.is_dmcub_enabled = is_dmub_enabled;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &amp;is_pwait);</div><div class='add'>+	dmub-&gt;debug.is_pwait = is_pwait;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &amp;is_soft_reset);</div><div class='add'>+	dmub-&gt;debug.is_dmcub_soft_reset = is_soft_reset;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &amp;is_sec_reset);</div><div class='add'>+	dmub-&gt;debug.is_dmcub_secure_reset = is_sec_reset;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &amp;is_traceport_enabled);</div><div class='add'>+	dmub-&gt;debug.is_traceport_en  = is_traceport_enabled;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &amp;is_cw0_enabled);</div><div class='add'>+	dmub-&gt;debug.is_cw0_enabled = is_cw0_enabled;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &amp;is_cw6_enabled);</div><div class='add'>+	dmub-&gt;debug.is_cw6_enabled = is_cw6_enabled;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);</div><div class='add'>+}</div><div class='add'>+void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	/* DMCUB_REGION3_TMR_AXI_SPACE values:</div><div class='add'>+	 * 0b011 (0x3) - FB physical address</div><div class='add'>+	 * 0b100 (0x4) - GPU virtual address</div><div class='add'>+	 *</div><div class='add'>+	 * Default value is 0x3 (FB Physical address for TMR). When programming</div><div class='add'>+	 * DMUB to be in system memory, change to 0x4. The system memory allocated</div><div class='add'>+	 * is accessible by both GPU and CPU, so we use GPU virtual address.</div><div class='add'>+	 */</div><div class='add'>+	REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_SCRATCH17, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	return REG_READ(DMCUB_SCRATCH17);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_rb_cmd *cmd)</div><div class='add'>+{</div><div class='add'>+	uint32_t *dwords = (uint32_t *)cmd;</div><div class='add'>+	int32_t payload_size_bytes = cmd-&gt;cmd_common.header.payload_bytes;</div><div class='add'>+	uint32_t msg_index;</div><div class='add'>+	static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");</div><div class='add'>+</div><div class='add'>+	/* read remaining data based on payload size */</div><div class='add'>+	for (msg_index = 0; msg_index &lt; 15; msg_index++) {</div><div class='add'>+		if (payload_size_bytes &lt;= msg_index * 4) {</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (msg_index) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 4:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 5:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 6:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 7:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 8:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 9:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 10:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 11:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 12:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 13:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		case 14:</div><div class='add'>+			REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY</div><div class='add'>+	 * interrupt.</div><div class='add'>+	 */</div><div class='add'>+	REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t status;</div><div class='add'>+</div><div class='add'>+	REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &amp;status);</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_rb_cmd *cmd)</div><div class='add'>+{</div><div class='add'>+	uint32_t *dwords = (uint32_t *)cmd;</div><div class='add'>+</div><div class='add'>+	static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");</div><div class='add'>+</div><div class='add'>+	dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);</div><div class='add'>+	dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);</div><div class='add'>+	dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);</div><div class='add'>+	dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);</div><div class='add'>+	dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);</div><div class='add'>+	dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);</div><div class='add'>+	dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);</div><div class='add'>+	dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);</div><div class='add'>+	dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);</div><div class='add'>+	dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);</div><div class='add'>+	dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);</div><div class='add'>+	dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);</div><div class='add'>+	dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);</div><div class='add'>+	dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);</div><div class='add'>+	dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);</div><div class='add'>+	dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);</div><div class='add'>+	REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)</div><div class='add'>+{</div><div class='add'>+	*msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)</div><div class='add'>+{</div><div class='add'>+	REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t status;</div><div class='add'>+</div><div class='add'>+	REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &amp;status);</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)</div><div class='add'>+{</div><div class='add'>+	REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t status;</div><div class='add'>+</div><div class='add'>+	REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &amp;status);</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h<br/>new file mode 100644<br/>index 000000000000..88c3a44d67d9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h</a></div><div class='hunk'>@@ -0,0 +1,290 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef _DMUB_DCN401_H_</div><div class='add'>+#define _DMUB_DCN401_H_</div><div class='add'>+</div><div class='add'>+#include "dmub_dcn31.h"</div><div class='add'>+</div><div class='add'>+struct dmub_srv;</div><div class='add'>+</div><div class='add'>+/* DCN401 register definitions. */</div><div class='add'>+</div><div class='add'>+#define DMUB_DCN401_REGS() \</div><div class='add'>+	DMUB_SR(DMCUB_CNTL) \</div><div class='add'>+	DMUB_SR(DMCUB_CNTL2) \</div><div class='add'>+	DMUB_SR(DMCUB_SEC_CNTL) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX0_SIZE) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX0_RPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX0_WPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX1_SIZE) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX1_RPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_INBOX1_WPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX0_SIZE) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX0_RPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX0_WPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX1_SIZE) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX1_RPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_OUTBOX1_WPTR) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION4_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION5_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION6_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH0) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH1) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH2) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH3) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH4) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH5) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH6) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH7) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH8) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH9) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH10) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH11) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH12) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH13) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH14) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH15) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH16) \</div><div class='add'>+	DMUB_SR(DMCUB_SCRATCH17) \</div><div class='add'>+	DMUB_SR(DMCUB_GPINT_DATAIN0) \</div><div class='add'>+	DMUB_SR(DMCUB_GPINT_DATAIN1) \</div><div class='add'>+	DMUB_SR(DMCUB_GPINT_DATAOUT) \</div><div class='add'>+	DMUB_SR(CC_DC_PIPE_DIS) \</div><div class='add'>+	DMUB_SR(MMHUBBUB_SOFT_RESET) \</div><div class='add'>+	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \</div><div class='add'>+	DMUB_SR(DCN_VM_FB_OFFSET) \</div><div class='add'>+	DMUB_SR(DMCUB_TIMER_CURRENT) \</div><div class='add'>+	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \</div><div class='add'>+	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \</div><div class='add'>+	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \</div><div class='add'>+	DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \</div><div class='add'>+	DMUB_SR(DMCUB_INTERRUPT_ENABLE) \</div><div class='add'>+	DMUB_SR(DMCUB_INTERRUPT_ACK) \</div><div class='add'>+	DMUB_SR(DMCUB_INTERRUPT_STATUS) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_RDY) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG0) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG1) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG2) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG3) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG4) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG5) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG6) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG7) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG8) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG9) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG10) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG11) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG12) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG13) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_MSG14) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_INBOX0_RSP) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \</div><div class='add'>+	DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \</div><div class='add'>+	DMUB_SR(HOST_INTERRUPT_CSR)</div><div class='add'>+</div><div class='add'>+#define DMUB_DCN401_FIELDS() \</div><div class='add'>+	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \</div><div class='add'>+	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \</div><div class='add'>+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \</div><div class='add'>+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \</div><div class='add'>+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \</div><div class='add'>+	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \</div><div class='add'>+	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \</div><div class='add'>+	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \</div><div class='add'>+	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \</div><div class='add'>+	DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \</div><div class='add'>+	DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \</div><div class='add'>+	DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \</div><div class='add'>+	DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \</div><div class='add'>+	DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \</div><div class='add'>+	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \</div><div class='add'>+	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \</div><div class='add'>+	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \</div><div class='add'>+	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \</div><div class='add'>+	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \</div><div class='add'>+	DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN) \</div><div class='add'>+	DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS)</div><div class='add'>+</div><div class='add'>+struct dmub_srv_dcn401_reg_offset {</div><div class='add'>+#define DMUB_SR(reg) uint32_t reg;</div><div class='add'>+	DMUB_DCN401_REGS()</div><div class='add'>+	DMCUB_INTERNAL_REGS()</div><div class='add'>+#undef DMUB_SR</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_srv_dcn401_reg_shift {</div><div class='add'>+#define DMUB_SF(reg, field) uint8_t reg##__##field;</div><div class='add'>+	DMUB_DCN401_FIELDS()</div><div class='add'>+#undef DMUB_SF</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_srv_dcn401_reg_mask {</div><div class='add'>+#define DMUB_SF(reg, field) uint32_t reg##__##field;</div><div class='add'>+	DMUB_DCN401_FIELDS()</div><div class='add'>+#undef DMUB_SF</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dmub_srv_dcn401_regs {</div><div class='add'>+	const struct dmub_srv_dcn401_reg_offset offset;</div><div class='add'>+	const struct dmub_srv_dcn401_reg_mask mask;</div><div class='add'>+	const struct dmub_srv_dcn401_reg_shift shift;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs;</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_reset(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_reset_release(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,</div><div class='add'>+			      const struct dmub_window *cw0,</div><div class='add'>+			      const struct dmub_window *cw1);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,</div><div class='add'>+		      const struct dmub_window *cw0,</div><div class='add'>+		      const struct dmub_window *cw1);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_windows(struct dmub_srv *dmub,</div><div class='add'>+			      const struct dmub_window *cw2,</div><div class='add'>+			      const struct dmub_window *cw3,</div><div class='add'>+			      const struct dmub_window *cw4,</div><div class='add'>+			      const struct dmub_window *cw5,</div><div class='add'>+			      const struct dmub_window *cw6,</div><div class='add'>+			      const struct dmub_window *region6);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,</div><div class='add'>+			      const struct dmub_region *inbox1);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,</div><div class='add'>+			      const struct dmub_region *outbox1);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);</div><div class='add'>+</div><div class='add'>+bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+bool dmub_dcn401_is_supported(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_gpint(struct dmub_srv *dmub,</div><div class='add'>+			  union dmub_gpint_data_register reg);</div><div class='add'>+</div><div class='add'>+bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,</div><div class='add'>+			       union dmub_gpint_data_register reg);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);</div><div class='add'>+</div><div class='add'>+union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,</div><div class='add'>+			      const struct dmub_region *outbox0);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);</div><div class='add'>+</div><div class='add'>+uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub);</div><div class='add'>+void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);</div><div class='add'>+void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub);</div><div class='add'>+uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_rb_cmd *cmd);</div><div class='add'>+uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);</div><div class='add'>+void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_rb_cmd *cmd);</div><div class='add'>+void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);</div><div class='add'>+void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);</div><div class='add'>+void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);</div><div class='add'>+</div><div class='add'>+void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);</div><div class='add'>+void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);</div><div class='add'>+void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg);</div><div class='add'>+uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);</div><div class='add'>+void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);</div><div class='add'>+uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);</div><div class='add'>+</div><div class='add'>+#endif /* _DMUB_DCN401_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h<br/>index 96603d07c23d..123d1704670e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h</a></div><div class='hunk'>@@ -108,7 +108,6 @@ struct dmub_srv;</div><div class='ctx'> 				FN(reg, f4), v4)</div><div class='ctx'> </div><div class='ctx'> /* Register field getting. */</div><div class='del'>-</div><div class='ctx'> #define REG_GET(reg_name, field, val) \</div><div class='ctx'> 	dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c<br/>index 90e878195d95..a6ae1d2e9685 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c</a></div><div class='hunk'>@@ -38,6 +38,8 @@</div><div class='ctx'> #include "dmub_dcn32.h"</div><div class='ctx'> #include "dmub_dcn35.h"</div><div class='ctx'> #include "dmub_dcn351.h"</div><div class='add'>+#include "dmub_dcn36.h"</div><div class='add'>+#include "dmub_dcn401.h"</div><div class='ctx'> #include "os_types.h"</div><div class='ctx'> /*</div><div class='ctx'>  * Note: the DMUB service is standalone. No additional headers should be</div><div class='hunk'>@@ -60,13 +62,15 @@</div><div class='ctx'> /* Default state size if meta is absent. */</div><div class='ctx'> #define DMUB_FW_STATE_SIZE (64 * 1024)</div><div class='ctx'> </div><div class='del'>-/* Default tracebuffer size if meta is absent. */</div><div class='del'>-#define DMUB_TRACE_BUFFER_SIZE (64 * 1024)</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> /* Default scratch mem size. */</div><div class='ctx'> #define DMUB_SCRATCH_MEM_SIZE (1024)</div><div class='ctx'> </div><div class='add'>+/* Default indirect buffer size. */</div><div class='add'>+#define DMUB_IB_MEM_SIZE (2560)</div><div class='add'>+</div><div class='add'>+/* Default LSDMA ring buffer size. */</div><div class='add'>+#define DMUB_LSDMA_RB_SIZE (64 * 1024)</div><div class='add'>+</div><div class='ctx'> /* Number of windows in use. */</div><div class='ctx'> #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)</div><div class='ctx'> /* Base addresses. */</div><div class='hunk'>@@ -159,6 +163,9 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmub_srv_hw_funcs *funcs = &amp;dmub-&gt;hw_funcs;</div><div class='ctx'> </div><div class='add'>+	/* default to specifying now inbox type */</div><div class='add'>+	enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT;</div><div class='add'>+</div><div class='ctx'> 	switch (asic) {</div><div class='ctx'> 	case DMUB_ASIC_DCN20:</div><div class='ctx'> 	case DMUB_ASIC_DCN21:</div><div class='hunk'>@@ -317,6 +324,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)</div><div class='ctx'> </div><div class='ctx'> 	case DMUB_ASIC_DCN35:</div><div class='ctx'> 	case DMUB_ASIC_DCN351:</div><div class='add'>+	case DMUB_ASIC_DCN36:</div><div class='ctx'> 			dmub-&gt;regs_dcn35 = &amp;dmub_srv_dcn35_regs;</div><div class='ctx'> 			funcs-&gt;configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory;</div><div class='ctx'> 			funcs-&gt;send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd;</div><div class='hunk'>@@ -351,19 +359,87 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)</div><div class='ctx'> </div><div class='ctx'> 			funcs-&gt;get_current_time = dmub_dcn35_get_current_time;</div><div class='ctx'> 			funcs-&gt;get_diagnostic_data = dmub_dcn35_get_diagnostic_data;</div><div class='add'>+			funcs-&gt;get_preos_fw_info = dmub_dcn35_get_preos_fw_info;</div><div class='ctx'> </div><div class='ctx'> 			funcs-&gt;init_reg_offsets = dmub_srv_dcn35_regs_init;</div><div class='ctx'> 			if (asic == DMUB_ASIC_DCN351)</div><div class='del'>-                                funcs-&gt;init_reg_offsets = dmub_srv_dcn351_regs_init;</div><div class='add'>+				funcs-&gt;init_reg_offsets = dmub_srv_dcn351_regs_init;</div><div class='add'>+			if (asic == DMUB_ASIC_DCN36)</div><div class='add'>+				funcs-&gt;init_reg_offsets = dmub_srv_dcn36_regs_init;</div><div class='ctx'> </div><div class='ctx'> 			funcs-&gt;is_hw_powered_up = dmub_dcn35_is_hw_powered_up;</div><div class='ctx'> 			funcs-&gt;should_detect = dmub_dcn35_should_detect;</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='add'>+	case DMUB_ASIC_DCN401:</div><div class='add'>+		dmub-&gt;regs_dcn401 = &amp;dmub_srv_dcn401_regs;</div><div class='add'>+		funcs-&gt;configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory;</div><div class='add'>+		funcs-&gt;send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd;</div><div class='add'>+		funcs-&gt;clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register;</div><div class='add'>+		funcs-&gt;read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register;</div><div class='add'>+		funcs-&gt;reset = dmub_dcn401_reset;</div><div class='add'>+		funcs-&gt;reset_release = dmub_dcn401_reset_release;</div><div class='add'>+		funcs-&gt;backdoor_load = dmub_dcn401_backdoor_load;</div><div class='add'>+		funcs-&gt;backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode;</div><div class='add'>+		funcs-&gt;setup_windows = dmub_dcn401_setup_windows;</div><div class='add'>+		funcs-&gt;setup_mailbox = dmub_dcn401_setup_mailbox;</div><div class='add'>+		funcs-&gt;get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr;</div><div class='add'>+		funcs-&gt;get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr;</div><div class='add'>+		funcs-&gt;set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr;</div><div class='add'>+		funcs-&gt;setup_out_mailbox = dmub_dcn401_setup_out_mailbox;</div><div class='add'>+		funcs-&gt;get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr;</div><div class='add'>+		funcs-&gt;set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr;</div><div class='add'>+		funcs-&gt;is_supported = dmub_dcn401_is_supported;</div><div class='add'>+		funcs-&gt;is_hw_init = dmub_dcn401_is_hw_init;</div><div class='add'>+		funcs-&gt;set_gpint = dmub_dcn401_set_gpint;</div><div class='add'>+		funcs-&gt;is_gpint_acked = dmub_dcn401_is_gpint_acked;</div><div class='add'>+		funcs-&gt;get_gpint_response = dmub_dcn401_get_gpint_response;</div><div class='add'>+		funcs-&gt;get_gpint_dataout = dmub_dcn401_get_gpint_dataout;</div><div class='add'>+		funcs-&gt;get_fw_status = dmub_dcn401_get_fw_boot_status;</div><div class='add'>+		funcs-&gt;enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options;</div><div class='add'>+		funcs-&gt;skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence;</div><div class='add'>+		//outbox0 call stacks</div><div class='add'>+		funcs-&gt;setup_outbox0 = dmub_dcn401_setup_outbox0;</div><div class='add'>+		funcs-&gt;get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr;</div><div class='add'>+		funcs-&gt;set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr;</div><div class='add'>+</div><div class='add'>+		funcs-&gt;get_current_time = dmub_dcn401_get_current_time;</div><div class='add'>+		funcs-&gt;get_diagnostic_data = dmub_dcn401_get_diagnostic_data;</div><div class='add'>+</div><div class='add'>+		funcs-&gt;send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg;</div><div class='add'>+		funcs-&gt;read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status;</div><div class='add'>+		funcs-&gt;read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp;</div><div class='add'>+		funcs-&gt;write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack;</div><div class='add'>+		funcs-&gt;clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack;</div><div class='add'>+		funcs-&gt;enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int;</div><div class='add'>+		default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now</div><div class='add'>+</div><div class='add'>+		funcs-&gt;write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack;</div><div class='add'>+		funcs-&gt;read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg;</div><div class='add'>+		funcs-&gt;write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp;</div><div class='add'>+		funcs-&gt;read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status;</div><div class='add'>+		funcs-&gt;read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status;</div><div class='add'>+		funcs-&gt;enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int;</div><div class='add'>+		funcs-&gt;enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* set default inbox type if not overriden */</div><div class='add'>+	if (dmub-&gt;inbox_type == DMUB_CMD_INTERFACE_DEFAULT) {</div><div class='add'>+		if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) {</div><div class='add'>+			/* use default inbox type as specified by DCN rev */</div><div class='add'>+			dmub-&gt;inbox_type = default_inbox_type;</div><div class='add'>+		} else if (funcs-&gt;send_reg_inbox0_cmd_msg) {</div><div class='add'>+			/* prefer reg as default inbox type if present */</div><div class='add'>+			dmub-&gt;inbox_type = DMUB_CMD_INTERFACE_REG;</div><div class='add'>+		} else {</div><div class='add'>+			/* use fb as fallback */</div><div class='add'>+			dmub-&gt;inbox_type = DMUB_CMD_INTERFACE_FB;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -379,6 +455,7 @@ enum dmub_status dmub_srv_create(struct dmub_srv *dmub,</div><div class='ctx'> 	dmub-&gt;asic = params-&gt;asic;</div><div class='ctx'> 	dmub-&gt;fw_version = params-&gt;fw_version;</div><div class='ctx'> 	dmub-&gt;is_virtual = params-&gt;is_virtual;</div><div class='add'>+	dmub-&gt;inbox_type = params-&gt;inbox_type;</div><div class='ctx'> </div><div class='ctx'> 	/* Setup asic dependent hardware funcs. */</div><div class='ctx'> 	if (!dmub_srv_hw_setup(dmub, params-&gt;asic)) {</div><div class='hunk'>@@ -450,6 +527,7 @@ enum dmub_status</div><div class='ctx'> 	const struct dmub_fw_meta_info *fw_info;</div><div class='ctx'> 	uint32_t fw_state_size = DMUB_FW_STATE_SIZE;</div><div class='ctx'> 	uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;</div><div class='add'>+	uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE;</div><div class='ctx'> 	uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 };</div><div class='ctx'> </div><div class='ctx'> 	if (!dmub-&gt;sw_init)</div><div class='hunk'>@@ -463,8 +541,11 @@ enum dmub_status</div><div class='ctx'> 	fw_info = dmub_get_fw_meta_info(params);</div><div class='ctx'> </div><div class='ctx'> 	if (fw_info) {</div><div class='add'>+		memcpy(&amp;dmub-&gt;meta_info, fw_info, sizeof(*fw_info));</div><div class='add'>+</div><div class='ctx'> 		fw_state_size = fw_info-&gt;fw_region_size;</div><div class='ctx'> 		trace_buffer_size = fw_info-&gt;trace_buffer_size;</div><div class='add'>+		shared_state_size = fw_info-&gt;shared_state_size;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='ctx'> 		 * If DM didn't fill in a version, then fill it in based on</div><div class='hunk'>@@ -484,8 +565,11 @@ enum dmub_status</div><div class='ctx'> 	window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE;</div><div class='ctx'> 	window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size;</div><div class='ctx'> 	window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size;</div><div class='del'>-	window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE;</div><div class='del'>-	window_sizes[DMUB_WINDOW_SHARED_STATE] = DMUB_FW_HEADER_SHARED_STATE_SIZE;</div><div class='add'>+	window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = dmub_align(DMUB_SCRATCH_MEM_SIZE, 64);</div><div class='add'>+	window_sizes[DMUB_WINDOW_IB_MEM] = DMUB_IB_MEM_SIZE;</div><div class='add'>+	window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size);</div><div class='add'>+	window_sizes[DMUB_WINDOW_LSDMA_BUFFER] = DMUB_LSDMA_RB_SIZE;</div><div class='add'>+	window_sizes[DMUB_WINDOW_CURSOR_OFFLOAD] = dmub_align(sizeof(struct dmub_cursor_offload_v1), 64);</div><div class='ctx'> </div><div class='ctx'> 	out-&gt;fb_size =</div><div class='ctx'> 		dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB);</div><div class='hunk'>@@ -570,20 +654,22 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> 	struct dmub_fb *mail_fb = params-&gt;fb[DMUB_WINDOW_4_MAILBOX];</div><div class='ctx'> 	struct dmub_fb *tracebuff_fb = params-&gt;fb[DMUB_WINDOW_5_TRACEBUFF];</div><div class='ctx'> 	struct dmub_fb *fw_state_fb = params-&gt;fb[DMUB_WINDOW_6_FW_STATE];</div><div class='del'>-	struct dmub_fb *scratch_mem_fb = params-&gt;fb[DMUB_WINDOW_7_SCRATCH_MEM];</div><div class='ctx'> 	struct dmub_fb *shared_state_fb = params-&gt;fb[DMUB_WINDOW_SHARED_STATE];</div><div class='ctx'> </div><div class='ctx'> 	struct dmub_rb_init_params rb_params, outbox0_rb_params;</div><div class='ctx'> 	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6;</div><div class='ctx'> 	struct dmub_region inbox1, outbox1, outbox0;</div><div class='ctx'> </div><div class='add'>+	uint32_t i;</div><div class='add'>+</div><div class='ctx'> 	if (!dmub-&gt;sw_init)</div><div class='ctx'> 		return DMUB_STATUS_INVALID;</div><div class='ctx'> </div><div class='del'>-	if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||</div><div class='del'>-		!tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {</div><div class='del'>-		ASSERT(0);</div><div class='del'>-		return DMUB_STATUS_INVALID;</div><div class='add'>+	for (i = 0; i &lt; DMUB_WINDOW_TOTAL; ++i) {</div><div class='add'>+		if (!params-&gt;fb[i]) {</div><div class='add'>+			ASSERT(0);</div><div class='add'>+			return DMUB_STATUS_INVALID;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dmub-&gt;fb_base = params-&gt;fb_base;</div><div class='hunk'>@@ -644,7 +730,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> 	inbox1.base = cw4.region.base;</div><div class='ctx'> 	inbox1.top = cw4.region.base + DMUB_RB_SIZE;</div><div class='ctx'> 	outbox1.base = inbox1.top;</div><div class='del'>-	outbox1.top = cw4.region.top;</div><div class='add'>+	outbox1.top = inbox1.top + DMUB_RB_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	cw5.offset.quad_part = tracebuff_fb-&gt;gpu_addr;</div><div class='ctx'> 	cw5.region.base = DMUB_CW5_BASE;</div><div class='hunk'>@@ -657,7 +743,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> 	cw6.region.base = DMUB_CW6_BASE;</div><div class='ctx'> 	cw6.region.top = cw6.region.base + fw_state_fb-&gt;size;</div><div class='ctx'> </div><div class='del'>-	dmub-&gt;fw_state = fw_state_fb-&gt;cpu_addr;</div><div class='add'>+	dmub-&gt;fw_state = (void *)((uintptr_t)(fw_state_fb-&gt;cpu_addr) + DMUB_DEBUG_FW_STATE_OFFSET);</div><div class='ctx'> </div><div class='ctx'> 	region6.offset.quad_part = shared_state_fb-&gt;gpu_addr;</div><div class='ctx'> 	region6.region.base = DMUB_CW6_BASE;</div><div class='hunk'>@@ -665,7 +751,11 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> </div><div class='ctx'> 	dmub-&gt;shared_state = shared_state_fb-&gt;cpu_addr;</div><div class='ctx'> </div><div class='del'>-	dmub-&gt;scratch_mem_fb = *scratch_mem_fb;</div><div class='add'>+	dmub-&gt;scratch_mem_fb = *params-&gt;fb[DMUB_WINDOW_7_SCRATCH_MEM];</div><div class='add'>+	dmub-&gt;ib_mem_gart = *params-&gt;fb[DMUB_WINDOW_IB_MEM];</div><div class='add'>+</div><div class='add'>+	dmub-&gt;cursor_offload_fb = *params-&gt;fb[DMUB_WINDOW_CURSOR_OFFLOAD];</div><div class='add'>+	dmub-&gt;cursor_offload_v1 = (struct dmub_cursor_offload_v1 *)dmub-&gt;cursor_offload_fb.cpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	if (dmub-&gt;hw_funcs.setup_windows)</div><div class='ctx'> 		dmub-&gt;hw_funcs.setup_windows(dmub, &amp;cw2, &amp;cw3, &amp;cw4, &amp;cw5, &amp;cw6, &amp;region6);</div><div class='hunk'>@@ -677,12 +767,16 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> 		dmub-&gt;hw_funcs.setup_mailbox(dmub, &amp;inbox1);</div><div class='ctx'> 	if (dmub-&gt;hw_funcs.setup_out_mailbox)</div><div class='ctx'> 		dmub-&gt;hw_funcs.setup_out_mailbox(dmub, &amp;outbox1);</div><div class='add'>+	if (dmub-&gt;hw_funcs.enable_reg_inbox0_rsp_int)</div><div class='add'>+		dmub-&gt;hw_funcs.enable_reg_inbox0_rsp_int(dmub, true);</div><div class='add'>+	if (dmub-&gt;hw_funcs.enable_reg_outbox0_rdy_int)</div><div class='add'>+		dmub-&gt;hw_funcs.enable_reg_outbox0_rdy_int(dmub, true);</div><div class='ctx'> </div><div class='ctx'> 	dmub_memset(&amp;rb_params, 0, sizeof(rb_params));</div><div class='ctx'> 	rb_params.ctx = dmub;</div><div class='ctx'> 	rb_params.base_address = mail_fb-&gt;cpu_addr;</div><div class='ctx'> 	rb_params.capacity = DMUB_RB_SIZE;</div><div class='del'>-	dmub_rb_init(&amp;dmub-&gt;inbox1_rb, &amp;rb_params);</div><div class='add'>+	dmub_rb_init(&amp;dmub-&gt;inbox1.rb, &amp;rb_params);</div><div class='ctx'> </div><div class='ctx'> 	// Initialize outbox1 ring buffer</div><div class='ctx'> 	rb_params.ctx = dmub;</div><div class='hunk'>@@ -713,27 +807,6 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> 	return DMUB_STATUS_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)</div><div class='del'>-{</div><div class='del'>-	if (!dmub-&gt;sw_init)</div><div class='del'>-		return DMUB_STATUS_INVALID;</div><div class='del'>-</div><div class='del'>-	if (dmub-&gt;hw_funcs.get_inbox1_rptr &amp;&amp; dmub-&gt;hw_funcs.get_inbox1_wptr) {</div><div class='del'>-		uint32_t rptr = dmub-&gt;hw_funcs.get_inbox1_rptr(dmub);</div><div class='del'>-		uint32_t wptr = dmub-&gt;hw_funcs.get_inbox1_wptr(dmub);</div><div class='del'>-</div><div class='del'>-		if (rptr &gt; dmub-&gt;inbox1_rb.capacity || wptr &gt; dmub-&gt;inbox1_rb.capacity) {</div><div class='del'>-			return DMUB_STATUS_HW_FAILURE;</div><div class='del'>-		} else {</div><div class='del'>-			dmub-&gt;inbox1_rb.rptr = rptr;</div><div class='del'>-			dmub-&gt;inbox1_rb.wrpt = wptr;</div><div class='del'>-			dmub-&gt;inbox1_last_wptr = dmub-&gt;inbox1_rb.wrpt;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return DMUB_STATUS_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	if (!dmub-&gt;sw_init)</div><div class='hunk'>@@ -744,8 +817,13 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)</div><div class='ctx'> </div><div class='ctx'> 	/* mailboxes have been reset in hw, so reset the sw state as well */</div><div class='ctx'> 	dmub-&gt;inbox1_last_wptr = 0;</div><div class='del'>-	dmub-&gt;inbox1_rb.wrpt = 0;</div><div class='del'>-	dmub-&gt;inbox1_rb.rptr = 0;</div><div class='add'>+	dmub-&gt;inbox1.rb.wrpt = 0;</div><div class='add'>+	dmub-&gt;inbox1.rb.rptr = 0;</div><div class='add'>+	dmub-&gt;inbox1.num_reported = 0;</div><div class='add'>+	dmub-&gt;inbox1.num_submitted = 0;</div><div class='add'>+	dmub-&gt;reg_inbox0.num_reported = 0;</div><div class='add'>+	dmub-&gt;reg_inbox0.num_submitted = 0;</div><div class='add'>+	dmub-&gt;reg_inbox0.is_pending = 0;</div><div class='ctx'> 	dmub-&gt;outbox0_rb.wrpt = 0;</div><div class='ctx'> 	dmub-&gt;outbox0_rb.rptr = 0;</div><div class='ctx'> 	dmub-&gt;outbox1_rb.wrpt = 0;</div><div class='hunk'>@@ -756,7 +834,7 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)</div><div class='ctx'> 	return DMUB_STATUS_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,</div><div class='add'>+enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,</div><div class='ctx'> 				    const union dmub_rb_cmd *cmd)</div><div class='ctx'> {</div><div class='ctx'> 	if (!dmub-&gt;hw_init)</div><div class='hunk'>@@ -765,18 +843,20 @@ enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,</div><div class='ctx'> 	if (dmub-&gt;power_state != DMUB_POWER_STATE_D0)</div><div class='ctx'> 		return DMUB_STATUS_POWER_STATE_D3;</div><div class='ctx'> </div><div class='del'>-	if (dmub-&gt;inbox1_rb.rptr &gt; dmub-&gt;inbox1_rb.capacity ||</div><div class='del'>-	    dmub-&gt;inbox1_rb.wrpt &gt; dmub-&gt;inbox1_rb.capacity) {</div><div class='add'>+	if (dmub-&gt;inbox1.rb.rptr &gt; dmub-&gt;inbox1.rb.capacity ||</div><div class='add'>+	    dmub-&gt;inbox1.rb.wrpt &gt; dmub-&gt;inbox1.rb.capacity) {</div><div class='ctx'> 		return DMUB_STATUS_HW_FAILURE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dmub_rb_push_front(&amp;dmub-&gt;inbox1_rb, cmd))</div><div class='add'>+	if (dmub_rb_push_front(&amp;dmub-&gt;inbox1.rb, cmd)) {</div><div class='add'>+		dmub-&gt;inbox1.num_submitted++;</div><div class='ctx'> 		return DMUB_STATUS_OK;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return DMUB_STATUS_QUEUE_FULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)</div><div class='add'>+enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmub_rb flush_rb;</div><div class='ctx'> </div><div class='hunk'>@@ -791,13 +871,13 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)</div><div class='ctx'> 	 * been flushed to framebuffer memory. Otherwise DMCUB might</div><div class='ctx'> 	 * read back stale, fully invalid or partially invalid data.</div><div class='ctx'> 	 */</div><div class='del'>-	flush_rb = dmub-&gt;inbox1_rb;</div><div class='add'>+	flush_rb = dmub-&gt;inbox1.rb;</div><div class='ctx'> 	flush_rb.rptr = dmub-&gt;inbox1_last_wptr;</div><div class='ctx'> 	dmub_rb_flush_pending(&amp;flush_rb);</div><div class='ctx'> </div><div class='del'>-	dmub-&gt;hw_funcs.set_inbox1_wptr(dmub, dmub-&gt;inbox1_rb.wrpt);</div><div class='add'>+		dmub-&gt;hw_funcs.set_inbox1_wptr(dmub, dmub-&gt;inbox1.rb.wrpt);</div><div class='ctx'> </div><div class='del'>-	dmub-&gt;inbox1_last_wptr = dmub-&gt;inbox1_rb.wrpt;</div><div class='add'>+	dmub-&gt;inbox1_last_wptr = dmub-&gt;inbox1.rb.wrpt;</div><div class='ctx'> </div><div class='ctx'> 	return DMUB_STATUS_OK;</div><div class='ctx'> }</div><div class='hunk'>@@ -855,26 +935,84 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,</div><div class='ctx'> 	return DMUB_STATUS_TIMEOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	if (dmub-&gt;reg_inbox0.is_pending) {</div><div class='add'>+		dmub-&gt;reg_inbox0.is_pending = dmub-&gt;hw_funcs.read_reg_inbox0_rsp_int_status &amp;&amp;</div><div class='add'>+				!dmub-&gt;hw_funcs.read_reg_inbox0_rsp_int_status(dmub);</div><div class='add'>+</div><div class='add'>+		if (!dmub-&gt;reg_inbox0.is_pending) {</div><div class='add'>+			/* ack the rsp interrupt */</div><div class='add'>+			if (dmub-&gt;hw_funcs.write_reg_inbox0_rsp_int_ack)</div><div class='add'>+				dmub-&gt;hw_funcs.write_reg_inbox0_rsp_int_ack(dmub);</div><div class='add'>+</div><div class='add'>+			/* only update the reported count if commands aren't being batched */</div><div class='add'>+			if (!dmub-&gt;reg_inbox0.is_pending &amp;&amp; !dmub-&gt;reg_inbox0.is_multi_pending) {</div><div class='add'>+				dmub-&gt;reg_inbox0.num_reported = dmub-&gt;reg_inbox0.num_submitted;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,</div><div class='add'>+					uint32_t timeout_us)</div><div class='add'>+{</div><div class='add'>+	uint32_t i;</div><div class='add'>+	const uint32_t polling_interval_us = 1;</div><div class='add'>+	struct dmub_srv_inbox scratch_reg_inbox0 = dmub-&gt;reg_inbox0;</div><div class='add'>+	struct dmub_srv_inbox scratch_inbox1 = dmub-&gt;inbox1;</div><div class='add'>+	const volatile struct dmub_srv_inbox *reg_inbox0 = &amp;dmub-&gt;reg_inbox0;</div><div class='add'>+	const volatile struct dmub_srv_inbox *inbox1 = &amp;dmub-&gt;inbox1;</div><div class='add'>+</div><div class='add'>+	if (!dmub-&gt;hw_init ||</div><div class='add'>+			!dmub-&gt;hw_funcs.get_inbox1_wptr)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt;= timeout_us; i += polling_interval_us) {</div><div class='add'>+			scratch_inbox1.rb.wrpt = dmub-&gt;hw_funcs.get_inbox1_wptr(dmub);</div><div class='add'>+			scratch_inbox1.rb.rptr = dmub-&gt;hw_funcs.get_inbox1_rptr(dmub);</div><div class='add'>+</div><div class='add'>+		scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending &amp;&amp;</div><div class='add'>+				dmub-&gt;hw_funcs.read_reg_inbox0_rsp_int_status &amp;&amp;</div><div class='add'>+				!dmub-&gt;hw_funcs.read_reg_inbox0_rsp_int_status(dmub);</div><div class='add'>+</div><div class='add'>+		if (scratch_inbox1.rb.rptr &gt; dmub-&gt;inbox1.rb.capacity)</div><div class='add'>+			return DMUB_STATUS_HW_FAILURE;</div><div class='add'>+</div><div class='add'>+		/* check current HW state first, but use command submission vs reported as a fallback */</div><div class='add'>+		if ((dmub_rb_empty(&amp;scratch_inbox1.rb) ||</div><div class='add'>+				inbox1-&gt;num_reported &gt;= scratch_inbox1.num_submitted) &amp;&amp;</div><div class='add'>+				(!scratch_reg_inbox0.is_pending ||</div><div class='add'>+				reg_inbox0-&gt;num_reported &gt;= scratch_reg_inbox0.num_submitted))</div><div class='add'>+			return DMUB_STATUS_OK;</div><div class='add'>+</div><div class='add'>+		udelay(polling_interval_us);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_TIMEOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,</div><div class='ctx'> 					uint32_t timeout_us)</div><div class='ctx'> {</div><div class='del'>-	uint32_t i, rptr;</div><div class='add'>+	enum dmub_status status;</div><div class='add'>+	uint32_t i;</div><div class='add'>+	const uint32_t polling_interval_us = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (!dmub-&gt;hw_init)</div><div class='ctx'> 		return DMUB_STATUS_INVALID;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt;= timeout_us; ++i) {</div><div class='del'>-		rptr = dmub-&gt;hw_funcs.get_inbox1_rptr(dmub);</div><div class='del'>-</div><div class='del'>-		if (rptr &gt; dmub-&gt;inbox1_rb.capacity)</div><div class='del'>-			return DMUB_STATUS_HW_FAILURE;</div><div class='add'>+	for (i = 0; i &lt; timeout_us; i += polling_interval_us) {</div><div class='add'>+		status = dmub_srv_update_inbox_status(dmub);</div><div class='ctx'> </div><div class='del'>-		dmub-&gt;inbox1_rb.rptr = rptr;</div><div class='add'>+		if (status != DMUB_STATUS_OK)</div><div class='add'>+			return status;</div><div class='ctx'> </div><div class='del'>-		if (dmub_rb_empty(&amp;dmub-&gt;inbox1_rb))</div><div class='add'>+		/* check for idle */</div><div class='add'>+		if (dmub_rb_empty(&amp;dmub-&gt;inbox1.rb) &amp;&amp; !dmub-&gt;reg_inbox0.is_pending)</div><div class='ctx'> 			return DMUB_STATUS_OK;</div><div class='ctx'> </div><div class='del'>-		udelay(1);</div><div class='add'>+		udelay(polling_interval_us);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return DMUB_STATUS_TIMEOUT;</div><div class='hunk'>@@ -985,35 +1123,6 @@ enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,</div><div class='ctx'> 	return DMUB_STATUS_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,</div><div class='del'>-					      union dmub_rb_cmd *cmd)</div><div class='del'>-{</div><div class='del'>-	enum dmub_status status = DMUB_STATUS_OK;</div><div class='del'>-</div><div class='del'>-	// Queue command</div><div class='del'>-	status = dmub_srv_cmd_queue(dmub, cmd);</div><div class='del'>-</div><div class='del'>-	if (status != DMUB_STATUS_OK)</div><div class='del'>-		return status;</div><div class='del'>-</div><div class='del'>-	// Execute command</div><div class='del'>-	status = dmub_srv_cmd_execute(dmub);</div><div class='del'>-</div><div class='del'>-	if (status != DMUB_STATUS_OK)</div><div class='del'>-		return status;</div><div class='del'>-</div><div class='del'>-	// Wait for DMUB to process command</div><div class='del'>-	status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='del'>-</div><div class='del'>-	if (status != DMUB_STATUS_OK)</div><div class='del'>-		return status;</div><div class='del'>-</div><div class='del'>-	// Copy data back from ring buffer into command</div><div class='del'>-	dmub_rb_get_return_data(&amp;dmub-&gt;inbox1_rb, cmd);</div><div class='del'>-</div><div class='del'>-	return status;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,</div><div class='ctx'> 				 void *entry)</div><div class='ctx'> {</div><div class='hunk'>@@ -1044,11 +1153,11 @@ bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entr</div><div class='ctx'> 	return dmub_rb_out_trace_buffer_front(&amp;dmub-&gt;outbox0_rb, (void *)entry);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)</div><div class='add'>+bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub)</div><div class='ctx'> {</div><div class='del'>-	if (!dmub || !dmub-&gt;hw_funcs.get_diagnostic_data || !diag_data)</div><div class='add'>+	if (!dmub || !dmub-&gt;hw_funcs.get_diagnostic_data)</div><div class='ctx'> 		return false;</div><div class='del'>-	dmub-&gt;hw_funcs.get_diagnostic_data(dmub, diag_data);</div><div class='add'>+	dmub-&gt;hw_funcs.get_diagnostic_data(dmub);</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1112,3 +1221,163 @@ void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_t</div><div class='ctx'> </div><div class='ctx'> 	dmub-&gt;power_state = dmub_srv_power_state;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd)</div><div class='add'>+{</div><div class='add'>+	uint32_t num_pending = 0;</div><div class='add'>+</div><div class='add'>+	if (!dmub-&gt;hw_init)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	if (dmub-&gt;power_state != DMUB_POWER_STATE_D0)</div><div class='add'>+		return DMUB_STATUS_POWER_STATE_D3;</div><div class='add'>+</div><div class='add'>+	if (!dmub-&gt;hw_funcs.send_reg_inbox0_cmd_msg ||</div><div class='add'>+			!dmub-&gt;hw_funcs.clear_reg_inbox0_rsp_int_ack)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	if (dmub-&gt;reg_inbox0.num_submitted &gt;= dmub-&gt;reg_inbox0.num_reported)</div><div class='add'>+		num_pending = dmub-&gt;reg_inbox0.num_submitted - dmub-&gt;reg_inbox0.num_reported;</div><div class='add'>+	else</div><div class='add'>+		/* num_submitted wrapped */</div><div class='add'>+		num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY -</div><div class='add'>+				(dmub-&gt;reg_inbox0.num_reported - dmub-&gt;reg_inbox0.num_submitted);</div><div class='add'>+</div><div class='add'>+	if (num_pending &gt;= DMUB_REG_INBOX0_RB_MAX_ENTRY)</div><div class='add'>+		return DMUB_STATUS_QUEUE_FULL;</div><div class='add'>+</div><div class='add'>+	/* clear last rsp ack and send message */</div><div class='add'>+	dmub-&gt;hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub);</div><div class='add'>+	dmub-&gt;hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd);</div><div class='add'>+</div><div class='add'>+	dmub-&gt;reg_inbox0.num_submitted++;</div><div class='add'>+	dmub-&gt;reg_inbox0.is_pending = true;</div><div class='add'>+	dmub-&gt;reg_inbox0.is_multi_pending = cmd-&gt;cmd_common.header.multi_cmd_pending;</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dmub_srv_cmd_get_response(struct dmub_srv *dmub,</div><div class='add'>+		union dmub_rb_cmd *cmd_rsp)</div><div class='add'>+{</div><div class='add'>+	if (dmub) {</div><div class='add'>+		if (dmub-&gt;inbox_type == DMUB_CMD_INTERFACE_REG &amp;&amp;</div><div class='add'>+				dmub-&gt;hw_funcs.read_reg_inbox0_cmd_rsp) {</div><div class='add'>+			dmub-&gt;hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp);</div><div class='add'>+		} else {</div><div class='add'>+			dmub_rb_get_return_data(&amp;dmub-&gt;inbox1.rb, cmd_rsp);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	if (!dmub || !dmub-&gt;sw_init)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;reg_inbox0.is_pending = 0;</div><div class='add'>+	dmub-&gt;reg_inbox0.is_multi_pending = 0;</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	if (!dmub-&gt;sw_init)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	if (dmub-&gt;hw_funcs.get_inbox1_rptr &amp;&amp; dmub-&gt;hw_funcs.get_inbox1_wptr) {</div><div class='add'>+		uint32_t rptr = dmub-&gt;hw_funcs.get_inbox1_rptr(dmub);</div><div class='add'>+		uint32_t wptr = dmub-&gt;hw_funcs.get_inbox1_wptr(dmub);</div><div class='add'>+</div><div class='add'>+		if (rptr &gt; dmub-&gt;inbox1.rb.capacity || wptr &gt; dmub-&gt;inbox1.rb.capacity) {</div><div class='add'>+			return DMUB_STATUS_HW_FAILURE;</div><div class='add'>+		} else {</div><div class='add'>+			dmub-&gt;inbox1.rb.rptr = rptr;</div><div class='add'>+			dmub-&gt;inbox1.rb.wrpt = wptr;</div><div class='add'>+			dmub-&gt;inbox1_last_wptr = dmub-&gt;inbox1.rb.wrpt;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	enum dmub_status status;</div><div class='add'>+</div><div class='add'>+	status = dmub_srv_sync_reg_inbox0(dmub);</div><div class='add'>+	if (status != DMUB_STATUS_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='add'>+	status = dmub_srv_sync_inbox1(dmub);</div><div class='add'>+	if (status != DMUB_STATUS_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,</div><div class='add'>+		uint32_t timeout_us,</div><div class='add'>+		uint32_t num_free_required)</div><div class='add'>+{</div><div class='add'>+	enum dmub_status status;</div><div class='add'>+	uint32_t i;</div><div class='add'>+	const uint32_t polling_interval_us = 1;</div><div class='add'>+</div><div class='add'>+	if (!dmub-&gt;hw_init)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; timeout_us; i += polling_interval_us) {</div><div class='add'>+		status = dmub_srv_update_inbox_status(dmub);</div><div class='add'>+</div><div class='add'>+		if (status != DMUB_STATUS_OK)</div><div class='add'>+			return status;</div><div class='add'>+</div><div class='add'>+		/* check for space in inbox1 */</div><div class='add'>+		if (dmub_rb_num_free(&amp;dmub-&gt;inbox1.rb) &gt;= num_free_required)</div><div class='add'>+			return DMUB_STATUS_OK;</div><div class='add'>+</div><div class='add'>+		udelay(polling_interval_us);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_TIMEOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	uint32_t rptr;</div><div class='add'>+</div><div class='add'>+	if (!dmub-&gt;hw_init)</div><div class='add'>+		return DMUB_STATUS_INVALID;</div><div class='add'>+</div><div class='add'>+	if (dmub-&gt;power_state != DMUB_POWER_STATE_D0)</div><div class='add'>+		return DMUB_STATUS_POWER_STATE_D3;</div><div class='add'>+</div><div class='add'>+	/* update inbox1 state */</div><div class='add'>+	rptr = dmub-&gt;hw_funcs.get_inbox1_rptr(dmub);</div><div class='add'>+</div><div class='add'>+	if (rptr &gt; dmub-&gt;inbox1.rb.capacity)</div><div class='add'>+		return DMUB_STATUS_HW_FAILURE;</div><div class='add'>+</div><div class='add'>+	if (dmub-&gt;inbox1.rb.rptr &gt; rptr) {</div><div class='add'>+		/* rb wrapped */</div><div class='add'>+		dmub-&gt;inbox1.num_reported += (rptr + dmub-&gt;inbox1.rb.capacity - dmub-&gt;inbox1.rb.rptr) / DMUB_RB_CMD_SIZE;</div><div class='add'>+	} else {</div><div class='add'>+		dmub-&gt;inbox1.num_reported += (rptr - dmub-&gt;inbox1.rb.rptr) / DMUB_RB_CMD_SIZE;</div><div class='add'>+	}</div><div class='add'>+	dmub-&gt;inbox1.rb.rptr = rptr;</div><div class='add'>+</div><div class='add'>+	/* update reg_inbox0 */</div><div class='add'>+	dmub_srv_update_reg_inbox0_status(dmub);</div><div class='add'>+</div><div class='add'>+	return DMUB_STATUS_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dmub_srv_get_preos_info(struct dmub_srv *dmub)</div><div class='add'>+{</div><div class='add'>+	if (!dmub || !dmub-&gt;hw_funcs.get_preos_fw_info)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return dmub-&gt;hw_funcs.get_preos_fw_info(dmub);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c<br/>index 74189102eaec..e7a58b140388 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c</a></div><div class='hunk'>@@ -71,7 +71,7 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,</div><div class='ctx'> 	switch (cmd.cmd_common.header.type) {</div><div class='ctx'> 	case DMUB_OUT_CMD__DP_AUX_REPLY:</div><div class='ctx'> 		notify-&gt;type = DMUB_NOTIFICATION_AUX_REPLY;</div><div class='del'>-		notify-&gt;link_index = cmd.dp_aux_reply.control.instance;</div><div class='add'>+		notify-&gt;instance = cmd.dp_aux_reply.control.instance;</div><div class='ctx'> 		notify-&gt;result = cmd.dp_aux_reply.control.result;</div><div class='ctx'> 		dmub_memcpy((void *)&amp;notify-&gt;aux_reply,</div><div class='ctx'> 			(void *)&amp;cmd.dp_aux_reply.reply_data, sizeof(struct aux_reply_data));</div><div class='hunk'>@@ -84,34 +84,27 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,</div><div class='ctx'> 			notify-&gt;type = DMUB_NOTIFICATION_HPD_IRQ;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		notify-&gt;link_index = cmd.dp_hpd_notify.hpd_data.instance;</div><div class='add'>+		notify-&gt;instance = cmd.dp_hpd_notify.hpd_data.instance;</div><div class='ctx'> 		notify-&gt;result = AUX_RET_SUCCESS;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DMUB_OUT_CMD__SET_CONFIG_REPLY:</div><div class='ctx'> 		notify-&gt;type = DMUB_NOTIFICATION_SET_CONFIG_REPLY;</div><div class='del'>-		notify-&gt;link_index = cmd.set_config_reply.set_config_reply_control.instance;</div><div class='add'>+		notify-&gt;instance = cmd.set_config_reply.set_config_reply_control.instance;</div><div class='ctx'> 		notify-&gt;sc_status = cmd.set_config_reply.set_config_reply_control.status;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DMUB_OUT_CMD__DPIA_NOTIFICATION:</div><div class='ctx'> 		notify-&gt;type = DMUB_NOTIFICATION_DPIA_NOTIFICATION;</div><div class='del'>-		notify-&gt;link_index = cmd.dpia_notification.payload.header.instance;</div><div class='del'>-</div><div class='del'>-		if (cmd.dpia_notification.payload.header.type == DPIA_NOTIFY__BW_ALLOCATION) {</div><div class='del'>-</div><div class='del'>-			notify-&gt;dpia_notification.payload.data.dpia_bw_alloc.estimated_bw =</div><div class='del'>-					cmd.dpia_notification.payload.data.dpia_bw_alloc.estimated_bw;</div><div class='del'>-			notify-&gt;dpia_notification.payload.data.dpia_bw_alloc.allocated_bw =</div><div class='del'>-					cmd.dpia_notification.payload.data.dpia_bw_alloc.allocated_bw;</div><div class='del'>-</div><div class='del'>-			if (cmd.dpia_notification.payload.data.dpia_bw_alloc.bits.bw_request_failed)</div><div class='del'>-				notify-&gt;result = DPIA_BW_REQ_FAILED;</div><div class='del'>-			else if (cmd.dpia_notification.payload.data.dpia_bw_alloc.bits.bw_request_succeeded)</div><div class='del'>-				notify-&gt;result = DPIA_BW_REQ_SUCCESS;</div><div class='del'>-			else if (cmd.dpia_notification.payload.data.dpia_bw_alloc.bits.est_bw_changed)</div><div class='del'>-				notify-&gt;result = DPIA_EST_BW_CHANGED;</div><div class='del'>-			else if (cmd.dpia_notification.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed)</div><div class='del'>-				notify-&gt;result = DPIA_BW_ALLOC_CAPS_CHANGED;</div><div class='del'>-		}</div><div class='add'>+		notify-&gt;instance = cmd.dpia_notification.payload.header.instance;</div><div class='add'>+		break;</div><div class='add'>+	case DMUB_OUT_CMD__HPD_SENSE_NOTIFY:</div><div class='add'>+		notify-&gt;type = DMUB_NOTIFICATION_HPD_SENSE_NOTIFY;</div><div class='add'>+		dmub_memcpy(&amp;notify-&gt;hpd_sense_notify,</div><div class='add'>+			    &amp;cmd.hpd_sense_notify.data,</div><div class='add'>+			    sizeof(cmd.hpd_sense_notify.data));</div><div class='add'>+		break;</div><div class='add'>+	case DMUB_OUT_CMD__FUSED_IO:</div><div class='add'>+		notify-&gt;type = DMUB_NOTIFICATION_FUSED_IO;</div><div class='add'>+		dmub_memcpy(&amp;notify-&gt;fused_request, &amp;cmd.fused_io.request, sizeof(cmd.fused_io.request));</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		notify-&gt;type = DMUB_NOTIFICATION_NO_DATA;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h<br/>index 812377d9e48f..973b6bdbac63 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/bios_parser_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/bios_parser_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/bios_parser_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/bios_parser_types.h</a></div><div class='hunk'>@@ -135,12 +135,8 @@ struct bp_external_encoder_control {</div><div class='ctx'> struct bp_crtc_source_select {</div><div class='ctx'> 	enum engine_id engine_id;</div><div class='ctx'> 	enum controller_id controller_id;</div><div class='del'>-	/* from GPU Tx aka asic_signal */</div><div class='del'>-	enum signal_type signal;</div><div class='del'>-	/* sink_signal may differ from asicSignal if Translator encoder */</div><div class='ctx'> 	enum signal_type sink_signal;</div><div class='del'>-	enum display_output_bit_depth display_output_bit_depth;</div><div class='del'>-	bool enable_dp_audio;</div><div class='add'>+	uint8_t bit_depth;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct bp_transmitter_control {</div><div class='hunk'>@@ -166,6 +162,11 @@ struct bp_transmitter_control {</div><div class='ctx'> 	bool single_pll_mode;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct bp_load_detection_parameters {</div><div class='add'>+	enum engine_id engine_id;</div><div class='add'>+	uint16_t device_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct bp_hw_crtc_timing_parameters {</div><div class='ctx'> 	enum controller_id controller_id;</div><div class='ctx'> 	/* horizontal part */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h<br/>index c9ec46c6b4c6..8aea50aa9533 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/dal_asic_id.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/dal_asic_id.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/dal_asic_id.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/dal_asic_id.h</a></div><div class='hunk'>@@ -213,6 +213,11 @@ enum {</div><div class='ctx'> #endif</div><div class='ctx'> #define DEVICE_ID_NV_13FE 0x13FE  // CYAN_SKILLFISH</div><div class='ctx'> #define DEVICE_ID_NV_143F 0x143F</div><div class='add'>+#define DEVICE_ID_NV_13F9 0x13F9</div><div class='add'>+#define DEVICE_ID_NV_13FA 0x13FA</div><div class='add'>+#define DEVICE_ID_NV_13FB 0x13FB</div><div class='add'>+#define DEVICE_ID_NV_13FC 0x13FC</div><div class='add'>+#define DEVICE_ID_NV_13DB 0x13DB</div><div class='ctx'> #define FAMILY_VGH 144</div><div class='ctx'> #define DEVICE_ID_VGH_163F 0x163F</div><div class='ctx'> #define DEVICE_ID_VGH_1435 0x1435</div><div class='hunk'>@@ -257,6 +262,21 @@ enum {</div><div class='ctx'> #define ASICREV_IS_GC_11_0_2(eChipRev) (eChipRev &gt;= GC_11_0_2_A0 &amp;&amp; eChipRev &lt; GC_11_0_3_A0)</div><div class='ctx'> #define ASICREV_IS_GC_11_0_3(eChipRev) (eChipRev &gt;= GC_11_0_3_A0 &amp;&amp; eChipRev &lt; GC_11_UNKNOWN)</div><div class='ctx'> #define ASICREV_IS_GC_11_0_4(eChipRev) (eChipRev &gt;= GC_11_0_4_A0 &amp;&amp; eChipRev &lt; GC_11_UNKNOWN)</div><div class='add'>+#define ASICREV_IS_DCN36(eChipRev) ((eChipRev) &gt;= 0x50 &amp;&amp; (eChipRev) &lt; 0xC0)</div><div class='add'>+</div><div class='add'>+#define AMDGPU_FAMILY_GC_12_0_0         152 /* GC 12.0.0 */</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	GC_12_0_0_A0 = 0x50,</div><div class='add'>+	GC_12_0_1_A0 = 0x40,</div><div class='add'>+	GC_12_UNKNOWN = 0xFF,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ASICREV_IS_GC_12_0_1_A0(eChipRev)        (eChipRev &gt;= GC_12_0_1_A0 &amp;&amp; eChipRev &lt; GC_12_0_0_A0)</div><div class='add'>+#define ASICREV_IS_GC_12_0_0_A0(eChipRev)        (eChipRev &gt;= GC_12_0_0_A0 &amp;&amp; eChipRev &lt; 0xFF)</div><div class='add'>+</div><div class='add'>+#define ASICREV_IS_DCN4(eChipRev)	(eChipRev &gt;= GC_12_0_1_A0 &amp;&amp; eChipRev &lt; GC_12_0_0_A0)</div><div class='add'>+#define ASICREV_IS_DCN401(eChipRev)	(eChipRev &gt;= GC_12_0_0_A0 &amp;&amp; eChipRev &lt; GC_12_UNKNOWN)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * ASIC chip ID</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h<br/>index 1c6f24cb1d2f..a021d12acd74 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/dal_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/dal_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/dal_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/dal_types.h</a></div><div class='hunk'>@@ -27,7 +27,6 @@</div><div class='ctx'> #define __DAL_TYPES_H__</div><div class='ctx'> </div><div class='ctx'> #include "signal_types.h"</div><div class='del'>-#include "dc_types.h"</div><div class='ctx'> </div><div class='ctx'> struct dal_logger;</div><div class='ctx'> struct dc_bios;</div><div class='hunk'>@@ -64,6 +63,8 @@ enum dce_version {</div><div class='ctx'> 	DCN_VERSION_3_21,</div><div class='ctx'> 	DCN_VERSION_3_5,</div><div class='ctx'> 	DCN_VERSION_3_51,</div><div class='add'>+	DCN_VERSION_3_6,</div><div class='add'>+	DCN_VERSION_4_01,</div><div class='ctx'> 	DCN_VERSION_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h<br/>index 914f28e9f224..07b937b92efc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/dpcd_defs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/dpcd_defs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/dpcd_defs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/dpcd_defs.h</a></div><div class='hunk'>@@ -30,6 +30,22 @@</div><div class='ctx'> #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h</div><div class='ctx'> #define DP_SINK_HW_REVISION_START 0x409</div><div class='ctx'> #endif</div><div class='add'>+/* Panel Replay*/</div><div class='add'>+#ifndef DP_PANEL_REPLAY_CAPABILITY_SUPPORT // can remove this once the define gets into linux drm_dp_helper.h</div><div class='add'>+#define DP_PANEL_REPLAY_CAPABILITY_SUPPORT 0x0b0</div><div class='add'>+#endif /* DP_PANEL_REPLAY_CAPABILITY_SUPPORT */</div><div class='add'>+#ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h</div><div class='add'>+#define DP_PANEL_REPLAY_CAPABILITY 0x0b1</div><div class='add'>+#endif /* DP_PANEL_REPLAY_CAPABILITY */</div><div class='add'>+#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  // can remove this once the define gets into linux drm_dp_helper.h</div><div class='add'>+#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  0x1b0</div><div class='add'>+#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */</div><div class='add'>+#ifndef DP_PANEL_REPLAY_ENABLE // can remove this once the define gets into linux drm_dp_helper.h</div><div class='add'>+#define DP_PANEL_REPLAY_ENABLE (1 &lt;&lt; 0)</div><div class='add'>+#endif /* DP_PANEL_REPLAY_ENABLE */</div><div class='add'>+#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h</div><div class='add'>+#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1</div><div class='add'>+#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */</div><div class='ctx'> </div><div class='ctx'> enum dpcd_revision {</div><div class='ctx'> 	DPCD_REV_10 = 0x10,</div><div class='hunk'>@@ -164,17 +180,23 @@ enum dpcd_psr_sink_states {</div><div class='ctx'> 	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define DP_SOURCE_SEQUENCE    		    0x30c</div><div class='del'>-#define DP_SOURCE_TABLE_REVISION	    0x310</div><div class='del'>-#define DP_SOURCE_PAYLOAD_SIZE		    0x311</div><div class='del'>-#define DP_SOURCE_SINK_CAP		    0x317</div><div class='del'>-#define DP_SOURCE_BACKLIGHT_LEVEL	    0x320</div><div class='del'>-#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK    0x326</div><div class='del'>-#define DP_SOURCE_BACKLIGHT_CONTROL	    0x32E</div><div class='del'>-#define DP_SOURCE_BACKLIGHT_ENABLE	    0x32F</div><div class='del'>-#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED     0x340</div><div class='add'>+#define DP_SOURCE_SEQUENCE                      0x30C</div><div class='add'>+#define DP_SOURCE_TABLE_REVISION                0x310</div><div class='add'>+#define DP_SOURCE_PAYLOAD_SIZE                  0x311</div><div class='add'>+#define DP_SOURCE_SINK_CAP                      0x317</div><div class='add'>+#define DP_SOURCE_BACKLIGHT_LEVEL               0x320</div><div class='add'>+#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK        0x326</div><div class='add'>+#define DP_SOURCE_BACKLIGHT_CONTROL             0x32E</div><div class='add'>+#define DP_SOURCE_BACKLIGHT_ENABLE              0x32F</div><div class='add'>+#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED      0x340</div><div class='ctx'> #define DP_SINK_PR_REPLAY_STATUS                0x378</div><div class='ctx'> #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE     0x379</div><div class='ctx'> #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A</div><div class='add'>+#define DP_SINK_EMISSION_RATE                   0x37E</div><div class='add'>+</div><div class='add'>+/* Remove once drm_dp_helper.h is updated upstream */</div><div class='add'>+#ifndef DP_TOTAL_LTTPR_CNT</div><div class='add'>+#define DP_TOTAL_LTTPR_CNT                                  0xF000A /* 2.1 */</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> #endif /* __DAL_DPCD_DEFS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h<br/>index d4cf7ead1d87..990fa1f19c22 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/fixed31_32.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/fixed31_32.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/fixed31_32.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/fixed31_32.h</a></div><div class='hunk'>@@ -531,4 +531,10 @@ static inline struct fixed31_32 dc_fixpt_truncate(struct fixed31_32 arg, unsigne</div><div class='ctx'> 	return arg;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+struct fixed31_32 dc_fixpt_from_ux_dy(unsigned int value, unsigned int integer_bits, unsigned int fractional_bits);</div><div class='add'>+struct fixed31_32 dc_fixpt_from_int_dy(unsigned int int_value,</div><div class='add'>+		unsigned int frac_value,</div><div class='add'>+		unsigned int integer_bits,</div><div class='add'>+		unsigned int fractional_bits);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h<br/>index 7e3240e73c1f..63813009a3a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/gpio_service_interface.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/gpio_service_interface.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/gpio_service_interface.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/gpio_service_interface.h</a></div><div class='hunk'>@@ -86,6 +86,9 @@ enum dc_irq_source dal_irq_get_source(</div><div class='ctx'> enum dc_irq_source dal_irq_get_rx_source(</div><div class='ctx'> 	const struct gpio *irq);</div><div class='ctx'> </div><div class='add'>+enum dc_irq_source dal_irq_get_read_request(</div><div class='add'>+	const struct gpio *irq);</div><div class='add'>+</div><div class='ctx'> enum gpio_result dal_irq_setup_hpd_filter(</div><div class='ctx'> 	struct gpio *irq,</div><div class='ctx'> 	struct gpio_hpd_config *config);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h<br/>index 813463ffe15c..38a77fa9b4af 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h</a></div><div class='hunk'>@@ -169,6 +169,7 @@ struct dc_firmware_info {</div><div class='ctx'> 		uint32_t engine_clk_ss_percentage;</div><div class='ctx'> 	} feature;</div><div class='ctx'> </div><div class='add'>+	uint32_t max_pixel_clock; /* in KHz */</div><div class='ctx'> 	uint32_t default_display_engine_pll_frequency; /* in KHz */</div><div class='ctx'> 	uint32_t external_clock_source_frequency_for_dp; /* in KHz */</div><div class='ctx'> 	uint32_t smu_gpu_pll_output_freq; /* in KHz */</div><div class='hunk'>@@ -424,7 +425,7 @@ struct integrated_info {</div><div class='ctx'> /*</div><div class='ctx'>  * DFS-bypass flag</div><div class='ctx'>  */</div><div class='del'>-/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */</div><div class='add'>+/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */</div><div class='ctx'> enum {</div><div class='ctx'> 	DFS_BYPASS_ENABLE = 0x10</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h<br/>index c6bbd262f1ac..1386fa124e85 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/grph_object_id.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/grph_object_id.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/grph_object_id.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/grph_object_id.h</a></div><div class='hunk'>@@ -226,8 +226,8 @@ enum dp_alt_mode {</div><div class='ctx'> </div><div class='ctx'> struct graphics_object_id {</div><div class='ctx'> 	uint32_t  id:8;</div><div class='del'>-	uint32_t  enum_id:4;</div><div class='del'>-	uint32_t  type:4;</div><div class='add'>+	enum object_enum_id  enum_id :4;</div><div class='add'>+	enum object_type  type :4;</div><div class='ctx'> 	uint32_t  reserved:16; /* for padding. total size should be u32 */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -310,4 +310,11 @@ static inline bool dal_graphics_object_id_equal(</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static inline bool dc_connector_supports_analog(const enum connector_id conn)</div><div class='add'>+{</div><div class='add'>+	return conn == CONNECTOR_ID_VGA ||</div><div class='add'>+		conn == CONNECTOR_ID_SINGLE_LINK_DVII ||</div><div class='add'>+		conn == CONNECTOR_ID_DUAL_LINK_DVII;</div><div class='add'>+}</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h<br/>index 92dbff22a7c6..da74ed66c8f9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/link_service_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/link_service_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/link_service_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/link_service_types.h</a></div><div class='hunk'>@@ -73,7 +73,6 @@ struct link_training_settings {</div><div class='ctx'> 	enum dc_pre_emphasis *pre_emphasis;</div><div class='ctx'> 	enum dc_post_cursor2 *post_cursor2;</div><div class='ctx'> 	bool should_set_fec_ready;</div><div class='del'>-	/* TODO - factor lane_settings out because it changes during LT */</div><div class='ctx'> 	union dc_dp_ffe_preset *ffe_preset;</div><div class='ctx'> </div><div class='ctx'> 	uint16_t cr_pattern_time;</div><div class='hunk'>@@ -90,6 +89,8 @@ struct link_training_settings {</div><div class='ctx'> 	bool enhanced_framing;</div><div class='ctx'> 	enum lttpr_mode lttpr_mode;</div><div class='ctx'> </div><div class='add'>+	bool lttpr_early_tps2;</div><div class='add'>+</div><div class='ctx'> 	/* disallow different lanes to have different lane settings */</div><div class='ctx'> 	bool disallow_per_lane_settings;</div><div class='ctx'> 	/* dpcd lane settings will always use the same hw lane settings</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h<br/>index 02c23b04d34b..4c01514b926c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/logger_interface.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/logger_interface.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/logger_interface.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/logger_interface.h</a></div><div class='hunk'>@@ -40,11 +40,6 @@ struct dc_state;</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-void pre_surface_trace(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		const struct dc_plane_state *const *plane_states,</div><div class='del'>-		int surface_count);</div><div class='del'>-</div><div class='ctx'> void update_surface_trace(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		const struct dc_surface_update *updates,</div><div class='hunk'>@@ -52,10 +47,6 @@ void update_surface_trace(</div><div class='ctx'> </div><div class='ctx'> void post_surface_trace(struct dc *dc);</div><div class='ctx'> </div><div class='del'>-void context_timing_trace(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct resource_context *res_ctx);</div><div class='del'>-</div><div class='ctx'> void context_clock_trace(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h<br/>index f39e2785e618..177acb0574f1 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/logger_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/logger_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/logger_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/logger_types.h</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #define DC_LOG_WARNING(...) drm_warn((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='ctx'> #define DC_LOG_DEBUG(...) drm_dbg((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='ctx'> #define DC_LOG_DC(...) drm_dbg((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='add'>+#define DC_LOG_INFO(...) drm_info((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='ctx'> #define DC_LOG_SURFACE(...) pr_debug("[SURFACE]:"__VA_ARGS__)</div><div class='ctx'> #define DC_LOG_HW_HOTPLUG(...) drm_dbg((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='ctx'> #define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__)</div><div class='hunk'>@@ -64,6 +65,10 @@</div><div class='ctx'> #define DC_LOG_DWB(...) drm_dbg((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='ctx'> #define DC_LOG_DP2(...) drm_dbg_dp((DC_LOGGER)-&gt;dev, __VA_ARGS__)</div><div class='ctx'> #define DC_LOG_AUTO_DPM_TEST(...) pr_debug("[AutoDPMTest]: "__VA_ARGS__)</div><div class='add'>+#define DC_LOG_IPS(...) pr_debug("[IPS]: "__VA_ARGS__)</div><div class='add'>+#define DC_LOG_MALL(...) pr_debug("[MALL]:"__VA_ARGS__)</div><div class='add'>+#define DC_LOG_REGISTER_READ(...) pr_debug("[REGISTER_READ]: "__VA_ARGS__)</div><div class='add'>+#define DC_LOG_REGISTER_WRITE(...) pr_debug("[REGISTER_WRITE]: "__VA_ARGS__)</div><div class='ctx'> </div><div class='ctx'> struct dc_log_buffer_ctx {</div><div class='ctx'> 	char *buf;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h<br/>index 1b14b17a79c7..3a2c2d2fb629 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/signal_types.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/include/signal_types.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/include/signal_types.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/include/signal_types.h</a></div><div class='hunk'>@@ -118,6 +118,31 @@ static inline bool dc_is_dvi_signal(enum signal_type signal)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * dc_is_rgb_signal() - Whether the signal is analog RGB.</div><div class='add'>+ *</div><div class='add'>+ * Returns whether the given signal type is an analog RGB signal</div><div class='add'>+ * that is used with a DAC on VGA or DVI-I connectors.</div><div class='add'>+ * Not to be confused with other uses of "RGB", such as RGB color space.</div><div class='add'>+ */</div><div class='add'>+static inline bool dc_is_rgb_signal(enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	return (signal == SIGNAL_TYPE_RGB);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool dc_is_tmds_signal(enum signal_type signal)</div><div class='add'>+{</div><div class='add'>+	switch (signal) {</div><div class='add'>+	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='add'>+	case SIGNAL_TYPE_DVI_DUAL_LINK:</div><div class='add'>+	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='add'>+		return true;</div><div class='add'>+	break;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline bool dc_is_dvi_single_link_signal(enum signal_type signal)</div><div class='ctx'> {</div><div class='ctx'> 	return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c<br/>index 8b5c27857671..a71df052cf25 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/color/color_gamma.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/color/color_gamma.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/color/color_gamma.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/color/color_gamma.c</a></div><div class='hunk'>@@ -1059,7 +1059,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,</div><div class='ctx'> 	struct fixed31_32 min_display;</div><div class='ctx'> 	struct fixed31_32 max_content;</div><div class='ctx'> 	struct fixed31_32 clip = dc_fixpt_one;</div><div class='del'>-	struct fixed31_32 output;</div><div class='add'>+	struct fixed31_32 output = dc_fixpt_zero;</div><div class='ctx'> 	bool use_eetf = false;</div><div class='ctx'> 	bool is_clipped = false;</div><div class='ctx'> 	struct fixed31_32 sdr_white_level;</div><div class='hunk'>@@ -1399,71 +1399,6 @@ static void scale_gamma_dx(struct pwl_float_data *pwl_rgb,</div><div class='ctx'> 				pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* todo: all these scale_gamma functions are inherently the same but</div><div class='del'>- *  take different structures as params or different format for ramp</div><div class='del'>- *  values. We could probably implement it in a more generic fashion</div><div class='del'>- */</div><div class='del'>-static void scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb,</div><div class='del'>-		const struct regamma_ramp *ramp,</div><div class='del'>-		struct dividers dividers)</div><div class='del'>-{</div><div class='del'>-	unsigned short max_driver = 0xFFFF;</div><div class='del'>-	unsigned short max_os = 0xFF00;</div><div class='del'>-	unsigned short scaler = max_os;</div><div class='del'>-	uint32_t i;</div><div class='del'>-	struct pwl_float_data *rgb = pwl_rgb;</div><div class='del'>-	struct pwl_float_data *rgb_last = rgb + GAMMA_RGB_256_ENTRIES - 1;</div><div class='del'>-</div><div class='del'>-	i = 0;</div><div class='del'>-	do {</div><div class='del'>-		if (ramp-&gt;gamma[i] &gt; max_os ||</div><div class='del'>-				ramp-&gt;gamma[i + 256] &gt; max_os ||</div><div class='del'>-				ramp-&gt;gamma[i + 512] &gt; max_os) {</div><div class='del'>-			scaler = max_driver;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-		i++;</div><div class='del'>-	} while (i != GAMMA_RGB_256_ENTRIES);</div><div class='del'>-</div><div class='del'>-	i = 0;</div><div class='del'>-	do {</div><div class='del'>-		rgb-&gt;r = dc_fixpt_from_fraction(</div><div class='del'>-				ramp-&gt;gamma[i], scaler);</div><div class='del'>-		rgb-&gt;g = dc_fixpt_from_fraction(</div><div class='del'>-				ramp-&gt;gamma[i + 256], scaler);</div><div class='del'>-		rgb-&gt;b = dc_fixpt_from_fraction(</div><div class='del'>-				ramp-&gt;gamma[i + 512], scaler);</div><div class='del'>-</div><div class='del'>-		++rgb;</div><div class='del'>-		++i;</div><div class='del'>-	} while (i != GAMMA_RGB_256_ENTRIES);</div><div class='del'>-</div><div class='del'>-	rgb-&gt;r = dc_fixpt_mul(rgb_last-&gt;r,</div><div class='del'>-			dividers.divider1);</div><div class='del'>-	rgb-&gt;g = dc_fixpt_mul(rgb_last-&gt;g,</div><div class='del'>-			dividers.divider1);</div><div class='del'>-	rgb-&gt;b = dc_fixpt_mul(rgb_last-&gt;b,</div><div class='del'>-			dividers.divider1);</div><div class='del'>-</div><div class='del'>-	++rgb;</div><div class='del'>-</div><div class='del'>-	rgb-&gt;r = dc_fixpt_mul(rgb_last-&gt;r,</div><div class='del'>-			dividers.divider2);</div><div class='del'>-	rgb-&gt;g = dc_fixpt_mul(rgb_last-&gt;g,</div><div class='del'>-			dividers.divider2);</div><div class='del'>-	rgb-&gt;b = dc_fixpt_mul(rgb_last-&gt;b,</div><div class='del'>-			dividers.divider2);</div><div class='del'>-</div><div class='del'>-	++rgb;</div><div class='del'>-</div><div class='del'>-	rgb-&gt;r = dc_fixpt_mul(rgb_last-&gt;r,</div><div class='del'>-			dividers.divider3);</div><div class='del'>-	rgb-&gt;g = dc_fixpt_mul(rgb_last-&gt;g,</div><div class='del'>-			dividers.divider3);</div><div class='del'>-	rgb-&gt;b = dc_fixpt_mul(rgb_last-&gt;b,</div><div class='del'>-			dividers.divider3);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * RS3+ color transform DDI - 1D LUT adjustment is composed with regamma here</div><div class='ctx'>  * Input is evenly distributed in the output color space as specified in</div><div class='hunk'>@@ -1663,106 +1598,6 @@ static bool calculate_interpolated_hardware_curve(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* The "old" interpolation uses a complicated scheme to build an array of</div><div class='del'>- * coefficients while also using an array of 0-255 normalized to 0-1</div><div class='del'>- * Then there's another loop using both of the above + new scaled user ramp</div><div class='del'>- * and we concatenate them. It also searches for points of interpolation and</div><div class='del'>- * uses enums for positions.</div><div class='del'>- *</div><div class='del'>- * This function uses a different approach:</div><div class='del'>- * user ramp is always applied on X with 0/255, 1/255, 2/255, ..., 255/255</div><div class='del'>- * To find index for hwX , we notice the following:</div><div class='del'>- * i/255 &lt;= hwX &lt; (i+1)/255  &lt;=&gt; i &lt;= 255*hwX &lt; i+1</div><div class='del'>- * See apply_lut_1d which is the same principle, but on 4K entry 1D LUT</div><div class='del'>- *</div><div class='del'>- * Once the index is known, combined Y is simply:</div><div class='del'>- * user_ramp(index) + (hwX-index/255)*(user_ramp(index+1) - user_ramp(index)</div><div class='del'>- *</div><div class='del'>- * We should switch to this method in all cases, it's simpler and faster</div><div class='del'>- * ToDo one day - for now this only applies to ADL regamma to avoid regression</div><div class='del'>- * for regular use cases (sRGB and PQ)</div><div class='del'>- */</div><div class='del'>-static void interpolate_user_regamma(uint32_t hw_points_num,</div><div class='del'>-		struct pwl_float_data *rgb_user,</div><div class='del'>-		bool apply_degamma,</div><div class='del'>-		struct dc_transfer_func_distributed_points *tf_pts)</div><div class='del'>-{</div><div class='del'>-	uint32_t i;</div><div class='del'>-	uint32_t color = 0;</div><div class='del'>-	int32_t index;</div><div class='del'>-	int32_t index_next;</div><div class='del'>-	struct fixed31_32 *tf_point;</div><div class='del'>-	struct fixed31_32 hw_x;</div><div class='del'>-	struct fixed31_32 norm_factor =</div><div class='del'>-			dc_fixpt_from_int(255);</div><div class='del'>-	struct fixed31_32 norm_x;</div><div class='del'>-	struct fixed31_32 index_f;</div><div class='del'>-	struct fixed31_32 lut1;</div><div class='del'>-	struct fixed31_32 lut2;</div><div class='del'>-	struct fixed31_32 delta_lut;</div><div class='del'>-	struct fixed31_32 delta_index;</div><div class='del'>-	const struct fixed31_32 one = dc_fixpt_from_int(1);</div><div class='del'>-</div><div class='del'>-	i = 0;</div><div class='del'>-	/* fixed_pt library has problems handling too small values */</div><div class='del'>-	while (i != 32) {</div><div class='del'>-		tf_pts-&gt;red[i] = dc_fixpt_zero;</div><div class='del'>-		tf_pts-&gt;green[i] = dc_fixpt_zero;</div><div class='del'>-		tf_pts-&gt;blue[i] = dc_fixpt_zero;</div><div class='del'>-		++i;</div><div class='del'>-	}</div><div class='del'>-	while (i &lt;= hw_points_num + 1) {</div><div class='del'>-		for (color = 0; color &lt; 3; color++) {</div><div class='del'>-			if (color == 0)</div><div class='del'>-				tf_point = &amp;tf_pts-&gt;red[i];</div><div class='del'>-			else if (color == 1)</div><div class='del'>-				tf_point = &amp;tf_pts-&gt;green[i];</div><div class='del'>-			else</div><div class='del'>-				tf_point = &amp;tf_pts-&gt;blue[i];</div><div class='del'>-</div><div class='del'>-			if (apply_degamma) {</div><div class='del'>-				if (color == 0)</div><div class='del'>-					hw_x = coordinates_x[i].regamma_y_red;</div><div class='del'>-				else if (color == 1)</div><div class='del'>-					hw_x = coordinates_x[i].regamma_y_green;</div><div class='del'>-				else</div><div class='del'>-					hw_x = coordinates_x[i].regamma_y_blue;</div><div class='del'>-			} else</div><div class='del'>-				hw_x = coordinates_x[i].x;</div><div class='del'>-</div><div class='del'>-			if (dc_fixpt_le(one, hw_x))</div><div class='del'>-				hw_x = one;</div><div class='del'>-</div><div class='del'>-			norm_x = dc_fixpt_mul(norm_factor, hw_x);</div><div class='del'>-			index = dc_fixpt_floor(norm_x);</div><div class='del'>-			if (index &lt; 0 || index &gt; 255)</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			index_f = dc_fixpt_from_int(index);</div><div class='del'>-			index_next = (index == 255) ? index : index + 1;</div><div class='del'>-</div><div class='del'>-			if (color == 0) {</div><div class='del'>-				lut1 = rgb_user[index].r;</div><div class='del'>-				lut2 = rgb_user[index_next].r;</div><div class='del'>-			} else if (color == 1) {</div><div class='del'>-				lut1 = rgb_user[index].g;</div><div class='del'>-				lut2 = rgb_user[index_next].g;</div><div class='del'>-			} else {</div><div class='del'>-				lut1 = rgb_user[index].b;</div><div class='del'>-				lut2 = rgb_user[index_next].b;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			// we have everything now, so interpolate</div><div class='del'>-			delta_lut = dc_fixpt_sub(lut2, lut1);</div><div class='del'>-			delta_index = dc_fixpt_sub(norm_x, index_f);</div><div class='del'>-</div><div class='del'>-			*tf_point = dc_fixpt_add(lut1,</div><div class='del'>-				dc_fixpt_mul(delta_index, delta_lut));</div><div class='del'>-		}</div><div class='del'>-		++i;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void build_new_custom_resulted_curve(</div><div class='ctx'> 	uint32_t hw_points_num,</div><div class='ctx'> 	struct dc_transfer_func_distributed_points *tf_pts)</div><div class='hunk'>@@ -1784,29 +1619,6 @@ static void build_new_custom_resulted_curve(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void apply_degamma_for_user_regamma(struct pwl_float_data_ex *rgb_regamma,</div><div class='del'>-		uint32_t hw_points_num, struct calculate_buffer *cal_buffer)</div><div class='del'>-{</div><div class='del'>-	uint32_t i;</div><div class='del'>-</div><div class='del'>-	struct gamma_coefficients coeff;</div><div class='del'>-	struct pwl_float_data_ex *rgb = rgb_regamma;</div><div class='del'>-	const struct hw_x_point *coord_x = coordinates_x;</div><div class='del'>-</div><div class='del'>-	build_coefficients(&amp;coeff, TRANSFER_FUNCTION_SRGB);</div><div class='del'>-</div><div class='del'>-	i = 0;</div><div class='del'>-	while (i != hw_points_num + 1) {</div><div class='del'>-		rgb-&gt;r = translate_from_linear_space_ex(</div><div class='del'>-				coord_x-&gt;x, &amp;coeff, 0, cal_buffer);</div><div class='del'>-		rgb-&gt;g = rgb-&gt;r;</div><div class='del'>-		rgb-&gt;b = rgb-&gt;r;</div><div class='del'>-		++coord_x;</div><div class='del'>-		++rgb;</div><div class='del'>-		++i;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool map_regamma_hw_to_x_user(</div><div class='ctx'> 	const struct dc_gamma *ramp,</div><div class='ctx'> 	struct pixel_gamma_point *coeff128,</div><div class='hunk'>@@ -1855,125 +1667,6 @@ static bool map_regamma_hw_to_x_user(</div><div class='ctx'> </div><div class='ctx'> #define _EXTRA_POINTS 3</div><div class='ctx'> </div><div class='del'>-bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,</div><div class='del'>-		const struct regamma_lut *regamma,</div><div class='del'>-		struct calculate_buffer *cal_buffer,</div><div class='del'>-		const struct dc_gamma *ramp)</div><div class='del'>-{</div><div class='del'>-	struct gamma_coefficients coeff;</div><div class='del'>-	const struct hw_x_point *coord_x = coordinates_x;</div><div class='del'>-	uint32_t i = 0;</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-		coeff.a0[i] = dc_fixpt_from_fraction(</div><div class='del'>-				regamma-&gt;coeff.A0[i], 10000000);</div><div class='del'>-		coeff.a1[i] = dc_fixpt_from_fraction(</div><div class='del'>-				regamma-&gt;coeff.A1[i], 1000);</div><div class='del'>-		coeff.a2[i] = dc_fixpt_from_fraction(</div><div class='del'>-				regamma-&gt;coeff.A2[i], 1000);</div><div class='del'>-		coeff.a3[i] = dc_fixpt_from_fraction(</div><div class='del'>-				regamma-&gt;coeff.A3[i], 1000);</div><div class='del'>-		coeff.user_gamma[i] = dc_fixpt_from_fraction(</div><div class='del'>-				regamma-&gt;coeff.gamma[i], 1000);</div><div class='del'>-</div><div class='del'>-		++i;</div><div class='del'>-	} while (i != 3);</div><div class='del'>-</div><div class='del'>-	i = 0;</div><div class='del'>-	/* fixed_pt library has problems handling too small values */</div><div class='del'>-	while (i != 32) {</div><div class='del'>-		output_tf-&gt;tf_pts.red[i] = dc_fixpt_zero;</div><div class='del'>-		output_tf-&gt;tf_pts.green[i] = dc_fixpt_zero;</div><div class='del'>-		output_tf-&gt;tf_pts.blue[i] = dc_fixpt_zero;</div><div class='del'>-		++coord_x;</div><div class='del'>-		++i;</div><div class='del'>-	}</div><div class='del'>-	while (i != MAX_HW_POINTS + 1) {</div><div class='del'>-		output_tf-&gt;tf_pts.red[i] = translate_from_linear_space_ex(</div><div class='del'>-				coord_x-&gt;x, &amp;coeff, 0, cal_buffer);</div><div class='del'>-		output_tf-&gt;tf_pts.green[i] = translate_from_linear_space_ex(</div><div class='del'>-				coord_x-&gt;x, &amp;coeff, 1, cal_buffer);</div><div class='del'>-		output_tf-&gt;tf_pts.blue[i] = translate_from_linear_space_ex(</div><div class='del'>-				coord_x-&gt;x, &amp;coeff, 2, cal_buffer);</div><div class='del'>-		++coord_x;</div><div class='del'>-		++i;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (ramp &amp;&amp; ramp-&gt;type == GAMMA_CS_TFM_1D)</div><div class='del'>-		apply_lut_1d(ramp, MAX_HW_POINTS, &amp;output_tf-&gt;tf_pts);</div><div class='del'>-</div><div class='del'>-	// this function just clamps output to 0-1</div><div class='del'>-	build_new_custom_resulted_curve(MAX_HW_POINTS, &amp;output_tf-&gt;tf_pts);</div><div class='del'>-	output_tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,</div><div class='del'>-		const struct regamma_lut *regamma,</div><div class='del'>-		struct calculate_buffer *cal_buffer,</div><div class='del'>-		const struct dc_gamma *ramp)</div><div class='del'>-{</div><div class='del'>-	struct dc_transfer_func_distributed_points *tf_pts = &amp;output_tf-&gt;tf_pts;</div><div class='del'>-	struct dividers dividers;</div><div class='del'>-</div><div class='del'>-	struct pwl_float_data *rgb_user = NULL;</div><div class='del'>-	struct pwl_float_data_ex *rgb_regamma = NULL;</div><div class='del'>-	bool ret = false;</div><div class='del'>-</div><div class='del'>-	if (regamma == NULL)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	output_tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='del'>-</div><div class='del'>-	rgb_user = kcalloc(GAMMA_RGB_256_ENTRIES + _EXTRA_POINTS,</div><div class='del'>-			   sizeof(*rgb_user),</div><div class='del'>-			   GFP_KERNEL);</div><div class='del'>-	if (!rgb_user)</div><div class='del'>-		goto rgb_user_alloc_fail;</div><div class='del'>-</div><div class='del'>-	rgb_regamma = kcalloc(MAX_HW_POINTS + _EXTRA_POINTS,</div><div class='del'>-			      sizeof(*rgb_regamma),</div><div class='del'>-			      GFP_KERNEL);</div><div class='del'>-	if (!rgb_regamma)</div><div class='del'>-		goto rgb_regamma_alloc_fail;</div><div class='del'>-</div><div class='del'>-	dividers.divider1 = dc_fixpt_from_fraction(3, 2);</div><div class='del'>-	dividers.divider2 = dc_fixpt_from_int(2);</div><div class='del'>-	dividers.divider3 = dc_fixpt_from_fraction(5, 2);</div><div class='del'>-</div><div class='del'>-	scale_user_regamma_ramp(rgb_user, &amp;regamma-&gt;ramp, dividers);</div><div class='del'>-</div><div class='del'>-	if (regamma-&gt;flags.bits.applyDegamma == 1) {</div><div class='del'>-		apply_degamma_for_user_regamma(rgb_regamma, MAX_HW_POINTS, cal_buffer);</div><div class='del'>-		copy_rgb_regamma_to_coordinates_x(coordinates_x,</div><div class='del'>-				MAX_HW_POINTS, rgb_regamma);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	interpolate_user_regamma(MAX_HW_POINTS, rgb_user,</div><div class='del'>-			regamma-&gt;flags.bits.applyDegamma, tf_pts);</div><div class='del'>-</div><div class='del'>-	// no custom HDR curves!</div><div class='del'>-	tf_pts-&gt;end_exponent = 0;</div><div class='del'>-	tf_pts-&gt;x_point_at_y1_red = 1;</div><div class='del'>-	tf_pts-&gt;x_point_at_y1_green = 1;</div><div class='del'>-	tf_pts-&gt;x_point_at_y1_blue = 1;</div><div class='del'>-</div><div class='del'>-	if (ramp &amp;&amp; ramp-&gt;type == GAMMA_CS_TFM_1D)</div><div class='del'>-		apply_lut_1d(ramp, MAX_HW_POINTS, &amp;output_tf-&gt;tf_pts);</div><div class='del'>-</div><div class='del'>-	// this function just clamps output to 0-1</div><div class='del'>-	build_new_custom_resulted_curve(MAX_HW_POINTS, tf_pts);</div><div class='del'>-</div><div class='del'>-	ret = true;</div><div class='del'>-</div><div class='del'>-	kfree(rgb_regamma);</div><div class='del'>-rgb_regamma_alloc_fail:</div><div class='del'>-	kfree(rgb_user);</div><div class='del'>-rgb_user_alloc_fail:</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,</div><div class='ctx'> 		struct dc_transfer_func *input_tf,</div><div class='ctx'> 		const struct dc_gamma *ramp, bool map_user_ramp)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h<br/>index ee5c466613de..97e55278940e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/color/color_gamma.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/color/color_gamma.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/color/color_gamma.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/color/color_gamma.h</a></div><div class='hunk'>@@ -115,15 +115,4 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,</div><div class='ctx'> 		struct dc_transfer_func *output_tf,</div><div class='ctx'> 		const struct dc_gamma *ramp, bool mapUserRamp);</div><div class='ctx'> </div><div class='del'>-bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,</div><div class='del'>-		const struct regamma_lut *regamma,</div><div class='del'>-		struct calculate_buffer *cal_buffer,</div><div class='del'>-		const struct dc_gamma *ramp);</div><div class='del'>-</div><div class='del'>-bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,</div><div class='del'>-		const struct regamma_lut *regamma,</div><div class='del'>-		struct calculate_buffer *cal_buffer,</div><div class='del'>-		const struct dc_gamma *ramp);</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> #endif /* COLOR_MOD_COLOR_GAMMA_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c<br/>index 3955b7e4b2e2..1aae46d703ba 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/freesync/freesync.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/freesync/freesync.c</a></div><div class='hunk'>@@ -48,6 +48,7 @@</div><div class='ctx'> #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2</div><div class='ctx'> #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5</div><div class='ctx'> #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500</div><div class='add'>+#define MICRO_HZ_TO_HZ(x) (x / 1000000)</div><div class='ctx'> </div><div class='ctx'> struct core_freesync {</div><div class='ctx'> 	struct mod_freesync public;</div><div class='hunk'>@@ -121,6 +122,17 @@ static unsigned int calc_duration_in_us_from_v_total(</div><div class='ctx'> 	return duration_in_us;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	unsigned int max_hw_v_total = stream-&gt;ctx-&gt;dc-&gt;caps.max_v_total;</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;ctx-&gt;dc-&gt;caps.vtotal_limited_by_fp2) {</div><div class='add'>+		max_hw_v_total -= stream-&gt;timing.v_front_porch + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return max_hw_v_total;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> unsigned int mod_freesync_calc_v_total_from_refresh(</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		unsigned int refresh_in_uhz)</div><div class='hunk'>@@ -128,13 +140,34 @@ unsigned int mod_freesync_calc_v_total_from_refresh(</div><div class='ctx'> 	unsigned int v_total;</div><div class='ctx'> 	unsigned int frame_duration_in_ns;</div><div class='ctx'> </div><div class='add'>+	if (refresh_in_uhz == 0)</div><div class='add'>+		return stream-&gt;timing.v_total;</div><div class='add'>+</div><div class='ctx'> 	frame_duration_in_ns =</div><div class='ctx'> 			((unsigned int)(div64_u64((1000000000ULL * 1000000),</div><div class='ctx'> 					refresh_in_uhz)));</div><div class='ctx'> </div><div class='del'>-	v_total = div64_u64(div64_u64(((unsigned long long)(</div><div class='del'>-			frame_duration_in_ns) * (stream-&gt;timing.pix_clk_100hz / 10)),</div><div class='del'>-			stream-&gt;timing.h_total), 1000000);</div><div class='add'>+	if (refresh_in_uhz &lt;= stream-&gt;timing.min_refresh_in_uhz) {</div><div class='add'>+		/* When the target refresh rate is the minimum panel refresh rate,</div><div class='add'>+		 * round down the vtotal value to avoid stretching vblank over</div><div class='add'>+		 * panel's vtotal boundary.</div><div class='add'>+		 */</div><div class='add'>+		v_total = div64_u64(div64_u64(((unsigned long long)(</div><div class='add'>+				frame_duration_in_ns) * (stream-&gt;timing.pix_clk_100hz / 10)),</div><div class='add'>+				stream-&gt;timing.h_total), 1000000);</div><div class='add'>+	} else if (refresh_in_uhz &gt;= stream-&gt;timing.max_refresh_in_uhz) {</div><div class='add'>+		/* When the target refresh rate is the maximum panel refresh rate</div><div class='add'>+		 * round up the vtotal value to prevent off-by-one error causing</div><div class='add'>+		 * v_total_min to be below the panel's lower bound</div><div class='add'>+		 */</div><div class='add'>+		v_total = div64_u64(div64_u64(((unsigned long long)(</div><div class='add'>+				frame_duration_in_ns) * (stream-&gt;timing.pix_clk_100hz / 10)),</div><div class='add'>+				stream-&gt;timing.h_total) + (1000000 - 1), 1000000);</div><div class='add'>+	} else {</div><div class='add'>+		v_total = div64_u64(div64_u64(((unsigned long long)(</div><div class='add'>+				frame_duration_in_ns) * (stream-&gt;timing.pix_clk_100hz / 10)),</div><div class='add'>+				stream-&gt;timing.h_total) + 500000, 1000000);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* v_total cannot be less than nominal */</div><div class='ctx'> 	if (v_total &lt; stream-&gt;timing.v_total) {</div><div class='hunk'>@@ -158,13 +191,13 @@ static unsigned int calc_v_total_from_duration(</div><div class='ctx'> 	if (duration_in_us &gt; vrr-&gt;max_duration_in_us)</div><div class='ctx'> 		duration_in_us = vrr-&gt;max_duration_in_us;</div><div class='ctx'> </div><div class='del'>-	if (dc_is_hdmi_signal(stream-&gt;signal)) {</div><div class='add'>+	if (dc_is_hdmi_signal(stream-&gt;signal)) { // change for HDMI to comply with spec</div><div class='ctx'> 		uint32_t h_total_up_scaled;</div><div class='ctx'> </div><div class='ctx'> 		h_total_up_scaled = stream-&gt;timing.h_total * 10000;</div><div class='ctx'> 		v_total = div_u64((unsigned long long)duration_in_us</div><div class='ctx'> 					* stream-&gt;timing.pix_clk_100hz + (h_total_up_scaled - 1),</div><div class='del'>-					h_total_up_scaled);</div><div class='add'>+					h_total_up_scaled); //ceiling for MMax and MMin for MVRR</div><div class='ctx'> 	} else {</div><div class='ctx'> 		v_total = div64_u64(div64_u64(((unsigned long long)(</div><div class='ctx'> 					duration_in_us) * (stream-&gt;timing.pix_clk_100hz / 10)),</div><div class='hunk'>@@ -193,8 +226,8 @@ static void update_v_total_for_static_ramp(</div><div class='ctx'> 	unsigned int target_duration_in_us =</div><div class='ctx'> 			calc_duration_in_us_from_refresh_in_uhz(</div><div class='ctx'> 				in_out_vrr-&gt;fixed.target_refresh_in_uhz);</div><div class='del'>-	bool ramp_direction_is_up = (current_duration_in_us &gt;</div><div class='del'>-				target_duration_in_us) ? true : false;</div><div class='add'>+	bool ramp_direction_is_up = current_duration_in_us &gt;</div><div class='add'>+				target_duration_in_us;</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate ratio between new and current frame duration with 3 digit */</div><div class='ctx'> 	unsigned int frame_duration_ratio = div64_u64(1000000,</div><div class='hunk'>@@ -527,43 +560,6 @@ static bool vrr_settings_require_update(struct core_freesync *core_freesync,</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,</div><div class='del'>-		const struct dc_stream_state *stream,</div><div class='del'>-		unsigned int *vmin,</div><div class='del'>-		unsigned int *vmax)</div><div class='del'>-{</div><div class='del'>-	*vmin = stream-&gt;adjust.v_total_min;</div><div class='del'>-	*vmax = stream-&gt;adjust.v_total_max;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		unsigned int *nom_v_pos,</div><div class='del'>-		unsigned int *v_pos)</div><div class='del'>-{</div><div class='del'>-	struct core_freesync *core_freesync = NULL;</div><div class='del'>-	struct crtc_position position;</div><div class='del'>-</div><div class='del'>-	if (mod_freesync == NULL)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);</div><div class='del'>-</div><div class='del'>-	if (dc_stream_get_crtc_position(core_freesync-&gt;dc, &amp;stream, 1,</div><div class='del'>-					&amp;position.vertical_count,</div><div class='del'>-					&amp;position.nominal_vcount)) {</div><div class='del'>-</div><div class='del'>-		*nom_v_pos = position.nominal_vcount;</div><div class='del'>-		*v_pos = position.vertical_count;</div><div class='del'>-</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,</div><div class='ctx'> 		struct dc_info_packet *infopacket,</div><div class='ctx'> 		bool freesync_on_desktop)</div><div class='hunk'>@@ -1002,7 +998,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;ctx-&gt;dc-&gt;caps.max_v_total != 0 &amp;&amp; stream-&gt;timing.h_total != 0) {</div><div class='ctx'> 		min_hardware_refresh_in_uhz = div64_u64((stream-&gt;timing.pix_clk_100hz * 100000000ULL),</div><div class='del'>-			(stream-&gt;timing.h_total * stream-&gt;ctx-&gt;dc-&gt;caps.max_v_total));</div><div class='add'>+			(stream-&gt;timing.h_total * (long long)calc_max_hardware_v_total(stream)));</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Limit minimum refresh rate to what can be supported by hardware */</div><div class='ctx'> 	min_refresh_in_uhz = min_hardware_refresh_in_uhz &gt; in_config-&gt;min_refresh_in_uhz ?</div><div class='hunk'>@@ -1057,7 +1053,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,</div><div class='ctx'> 			in_out_vrr-&gt;fixed_refresh_in_uhz = 0;</div><div class='ctx'> </div><div class='ctx'> 		refresh_range = div_u64(in_out_vrr-&gt;max_refresh_in_uhz + 500000, 1000000) -</div><div class='del'>-+				div_u64(in_out_vrr-&gt;min_refresh_in_uhz + 500000, 1000000);</div><div class='add'>+				div_u64(in_out_vrr-&gt;min_refresh_in_uhz + 500000, 1000000);</div><div class='ctx'> </div><div class='ctx'> 		in_out_vrr-&gt;supported = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1126,6 +1122,8 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,</div><div class='ctx'> 		in_out_vrr-&gt;adjust.v_total_min = stream-&gt;timing.v_total;</div><div class='ctx'> 		in_out_vrr-&gt;adjust.v_total_max = stream-&gt;timing.v_total;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	in_out_vrr-&gt;adjust.allow_otg_v_count_halt = (in_config-&gt;state == VRR_STATE_ACTIVE_FIXED) ? true : false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,</div><div class='hunk'>@@ -1262,27 +1260,16 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,</div><div class='ctx'> 		update_v_total_for_static_ramp(</div><div class='ctx'> 				core_freesync, stream, in_out_vrr);</div><div class='ctx'> 	}</div><div class='del'>-}</div><div class='ctx'> </div><div class='del'>-void mod_freesync_get_settings(struct mod_freesync *mod_freesync,</div><div class='del'>-		const struct mod_vrr_params *vrr,</div><div class='del'>-		unsigned int *v_total_min, unsigned int *v_total_max,</div><div class='del'>-		unsigned int *event_triggers,</div><div class='del'>-		unsigned int *window_min, unsigned int *window_max,</div><div class='del'>-		unsigned int *lfc_mid_point_in_us,</div><div class='del'>-		unsigned int *inserted_frames,</div><div class='del'>-		unsigned int *inserted_duration_in_us)</div><div class='del'>-{</div><div class='del'>-	if (mod_freesync == NULL)</div><div class='add'>+	/*</div><div class='add'>+	 * If VRR is inactive, set vtotal min and max to nominal vtotal</div><div class='add'>+	 */</div><div class='add'>+	 if (in_out_vrr-&gt;state == VRR_STATE_INACTIVE) {</div><div class='add'>+		in_out_vrr-&gt;adjust.v_total_min =</div><div class='add'>+			mod_freesync_calc_v_total_from_refresh(stream,</div><div class='add'>+				in_out_vrr-&gt;max_refresh_in_uhz);</div><div class='add'>+		in_out_vrr-&gt;adjust.v_total_max = in_out_vrr-&gt;adjust.v_total_min;</div><div class='ctx'> 		return;</div><div class='del'>-</div><div class='del'>-	if (vrr-&gt;supported) {</div><div class='del'>-		*v_total_min = vrr-&gt;adjust.v_total_min;</div><div class='del'>-		*v_total_max = vrr-&gt;adjust.v_total_max;</div><div class='del'>-		*event_triggers = 0;</div><div class='del'>-		*lfc_mid_point_in_us = vrr-&gt;btr.mid_point_in_us;</div><div class='del'>-		*inserted_frames = vrr-&gt;btr.frames_to_insert;</div><div class='del'>-		*inserted_duration_in_us = vrr-&gt;btr.inserted_duration_in_us;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1301,85 +1288,7 @@ unsigned long long mod_freesync_calc_nominal_field_rate(</div><div class='ctx'> 	return nominal_field_rate_in_uhz;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-unsigned long long mod_freesync_calc_field_rate_from_timing(</div><div class='del'>-		unsigned int vtotal, unsigned int htotal, unsigned int pix_clk)</div><div class='del'>-{</div><div class='del'>-	unsigned long long field_rate_in_uhz = 0;</div><div class='del'>-	unsigned int total = htotal * vtotal;</div><div class='del'>-</div><div class='del'>-	/* Calculate nominal field rate for stream, rounded up to nearest integer */</div><div class='del'>-	field_rate_in_uhz = pix_clk;</div><div class='del'>-	field_rate_in_uhz *= 1000000ULL;</div><div class='del'>-</div><div class='del'>-	field_rate_in_uhz =	div_u64(field_rate_in_uhz, total);</div><div class='del'>-</div><div class='del'>-	return field_rate_in_uhz;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)</div><div class='ctx'> {</div><div class='ctx'> 	return (pVrr-&gt;state != VRR_STATE_UNSUPPORTED) &amp;&amp; (pVrr-&gt;state != VRR_STATE_DISABLED);</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,</div><div class='del'>-		uint32_t max_refresh_cap_in_uhz,</div><div class='del'>-		uint32_t nominal_field_rate_in_uhz)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-	/* Typically nominal refresh calculated can have some fractional part.</div><div class='del'>-	 * Allow for some rounding error of actual video timing by taking floor</div><div class='del'>-	 * of caps and request. Round the nominal refresh rate.</div><div class='del'>-	 *</div><div class='del'>-	 * Dividing will convert everything to units in Hz although input</div><div class='del'>-	 * variable name is in uHz!</div><div class='del'>-	 *</div><div class='del'>-	 * Also note, this takes care of rounding error on the nominal refresh</div><div class='del'>-	 * so by rounding error we only expect it to be off by a small amount,</div><div class='del'>-	 * such as &lt; 0.1 Hz. i.e. 143.9xxx or 144.1xxx.</div><div class='del'>-	 *</div><div class='del'>-	 * Example 1. Caps    Min = 40 Hz, Max = 144 Hz</div><div class='del'>-	 *            Request Min = 40 Hz, Max = 144 Hz</div><div class='del'>-	 *                    Nominal = 143.5x Hz rounded to 144 Hz</div><div class='del'>-	 *            This function should allow this as valid request</div><div class='del'>-	 *</div><div class='del'>-	 * Example 2. Caps    Min = 40 Hz, Max = 144 Hz</div><div class='del'>-	 *            Request Min = 40 Hz, Max = 144 Hz</div><div class='del'>-	 *                    Nominal = 144.4x Hz rounded to 144 Hz</div><div class='del'>-	 *            This function should allow this as valid request</div><div class='del'>-	 *</div><div class='del'>-	 * Example 3. Caps    Min = 40 Hz, Max = 144 Hz</div><div class='del'>-	 *            Request Min = 40 Hz, Max = 144 Hz</div><div class='del'>-	 *                    Nominal = 120.xx Hz rounded to 120 Hz</div><div class='del'>-	 *            This function should return NOT valid since the requested</div><div class='del'>-	 *            max is greater than current timing's nominal</div><div class='del'>-	 *</div><div class='del'>-	 * Example 4. Caps    Min = 40 Hz, Max = 120 Hz</div><div class='del'>-	 *            Request Min = 40 Hz, Max = 120 Hz</div><div class='del'>-	 *                    Nominal = 144.xx Hz rounded to 144 Hz</div><div class='del'>-	 *            This function should return NOT valid since the nominal</div><div class='del'>-	 *            is greater than the capability's max refresh</div><div class='del'>-	 */</div><div class='del'>-	nominal_field_rate_in_uhz =</div><div class='del'>-			div_u64(nominal_field_rate_in_uhz + 500000, 1000000);</div><div class='del'>-	min_refresh_cap_in_uhz /= 1000000;</div><div class='del'>-	max_refresh_cap_in_uhz /= 1000000;</div><div class='del'>-</div><div class='del'>-	/* Check nominal is within range */</div><div class='del'>-	if (nominal_field_rate_in_uhz &gt; max_refresh_cap_in_uhz ||</div><div class='del'>-		nominal_field_rate_in_uhz &lt; min_refresh_cap_in_uhz)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	/* If nominal is less than max, limit the max allowed refresh rate */</div><div class='del'>-	if (nominal_field_rate_in_uhz &lt; max_refresh_cap_in_uhz)</div><div class='del'>-		max_refresh_cap_in_uhz = nominal_field_rate_in_uhz;</div><div class='del'>-</div><div class='del'>-	/* Check min is within range */</div><div class='del'>-	if (min_refresh_cap_in_uhz &gt; max_refresh_cap_in_uhz)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	/* For variable range, check for at least 10 Hz range */</div><div class='del'>-	if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz &lt; 10)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c<br/>index 5e01c6e24cbc..ca402ddcdacc 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@ static void push_error_status(struct mod_hdcp *hdcp,</div><div class='ctx'> 		enum mod_hdcp_status status)</div><div class='ctx'> {</div><div class='ctx'> 	struct mod_hdcp_trace *trace = &amp;hdcp-&gt;connection.trace;</div><div class='add'>+	const uint8_t retry_limit = hdcp-&gt;connection.link.adjust.retry_limit;</div><div class='ctx'> </div><div class='ctx'> 	if (trace-&gt;error_count &lt; MAX_NUM_OF_ERROR_TRACE) {</div><div class='ctx'> 		trace-&gt;errors[trace-&gt;error_count].status = status;</div><div class='hunk'>@@ -39,11 +40,11 @@ static void push_error_status(struct mod_hdcp *hdcp,</div><div class='ctx'> </div><div class='ctx'> 	if (is_hdcp1(hdcp)) {</div><div class='ctx'> 		hdcp-&gt;connection.hdcp1_retry_count++;</div><div class='del'>-		if (hdcp-&gt;connection.hdcp1_retry_count == MAX_NUM_OF_ATTEMPTS)</div><div class='add'>+		if (hdcp-&gt;connection.hdcp1_retry_count == retry_limit)</div><div class='ctx'> 			hdcp-&gt;connection.link.adjust.hdcp1.disable = 1;</div><div class='ctx'> 	} else if (is_hdcp2(hdcp)) {</div><div class='ctx'> 		hdcp-&gt;connection.hdcp2_retry_count++;</div><div class='del'>-		if (hdcp-&gt;connection.hdcp2_retry_count == MAX_NUM_OF_ATTEMPTS)</div><div class='add'>+		if (hdcp-&gt;connection.hdcp2_retry_count == retry_limit)</div><div class='ctx'> 			hdcp-&gt;connection.link.adjust.hdcp2.disable = 1;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -353,7 +354,7 @@ enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp,</div><div class='ctx'> 	/* reset retry counters */</div><div class='ctx'> 	reset_retry_counts(hdcp);</div><div class='ctx'> </div><div class='del'>-	/* reset error trace */</div><div class='add'>+	/* reset trace */</div><div class='ctx'> 	memset(&amp;hdcp-&gt;connection.trace, 0, sizeof(hdcp-&gt;connection.trace));</div><div class='ctx'> </div><div class='ctx'> 	/* add display to connection */</div><div class='hunk'>@@ -399,7 +400,7 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp,</div><div class='ctx'> 	/* clear retry counters */</div><div class='ctx'> 	reset_retry_counts(hdcp);</div><div class='ctx'> </div><div class='del'>-	/* reset error trace */</div><div class='add'>+	/* reset trace */</div><div class='ctx'> 	memset(&amp;hdcp-&gt;connection.trace, 0, sizeof(hdcp-&gt;connection.trace));</div><div class='ctx'> </div><div class='ctx'> 	/* remove display */</div><div class='hunk'>@@ -463,7 +464,7 @@ enum mod_hdcp_status mod_hdcp_update_display(struct mod_hdcp *hdcp,</div><div class='ctx'> 	/* clear retry counters */</div><div class='ctx'> 	reset_retry_counts(hdcp);</div><div class='ctx'> </div><div class='del'>-	/* reset error trace */</div><div class='add'>+	/* reset trace */</div><div class='ctx'> 	memset(&amp;hdcp-&gt;connection.trace, 0, sizeof(hdcp-&gt;connection.trace));</div><div class='ctx'> </div><div class='ctx'> 	/* set new adjustment */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h<br/>index 55c7d873175f..26a351a184f3 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h</a></div><div class='hunk'>@@ -88,6 +88,7 @@ struct mod_hdcp_transition_input_hdcp2 {</div><div class='ctx'> 	uint8_t lc_init_write;</div><div class='ctx'> 	uint8_t l_prime_available_poll;</div><div class='ctx'> 	uint8_t l_prime_read;</div><div class='add'>+	uint8_t l_prime_combo_read;</div><div class='ctx'> 	uint8_t l_prime_validation;</div><div class='ctx'> 	uint8_t eks_prepare;</div><div class='ctx'> 	uint8_t eks_write;</div><div class='hunk'>@@ -386,6 +387,7 @@ enum mod_hdcp_status mod_hdcp_write_repeater_auth_ack(struct mod_hdcp *hdcp);</div><div class='ctx'> enum mod_hdcp_status mod_hdcp_write_stream_manage(struct mod_hdcp *hdcp);</div><div class='ctx'> enum mod_hdcp_status mod_hdcp_write_content_type(struct mod_hdcp *hdcp);</div><div class='ctx'> enum mod_hdcp_status mod_hdcp_clear_cp_irq_status(struct mod_hdcp *hdcp);</div><div class='add'>+enum mod_hdcp_status mod_hdcp_write_poll_read_lc_fw(struct mod_hdcp *hdcp);</div><div class='ctx'> </div><div class='ctx'> /* hdcp version helpers */</div><div class='ctx'> static inline uint8_t is_dp_hdcp(struct mod_hdcp *hdcp)</div><div class='hunk'>@@ -507,7 +509,7 @@ static inline void set_auth_complete(struct mod_hdcp *hdcp,</div><div class='ctx'> 		struct mod_hdcp_output *output)</div><div class='ctx'> {</div><div class='ctx'> 	output-&gt;auth_complete = 1;</div><div class='del'>-	mod_hdcp_log_ddc_trace(hdcp);</div><div class='add'>+	HDCP_AUTH_COMPLETE_TRACE(hdcp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* connection topology helpers */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c<br/>index 182e7532dda8..1bbd728d4345 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	uint64_t n = 0;</div><div class='ctx'> 	uint8_t count = 0;</div><div class='add'>+	enum mod_hdcp_status status;</div><div class='ctx'> 	u8 bksv[sizeof(n)] = { };</div><div class='ctx'> </div><div class='ctx'> 	memcpy(bksv, hdcp-&gt;auth.msg.hdcp1.bksv, sizeof(hdcp-&gt;auth.msg.hdcp1.bksv));</div><div class='hunk'>@@ -38,8 +39,14 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)</div><div class='ctx'> 		count++;</div><div class='ctx'> 		n &amp;= (n - 1);</div><div class='ctx'> 	}</div><div class='del'>-	return (count == 20) ? MOD_HDCP_STATUS_SUCCESS :</div><div class='del'>-			MOD_HDCP_STATUS_HDCP1_INVALID_BKSV;</div><div class='add'>+</div><div class='add'>+	if (count == 20) {</div><div class='add'>+		hdcp-&gt;connection.trace.hdcp1.attempt_count++;</div><div class='add'>+		status = MOD_HDCP_STATUS_SUCCESS;</div><div class='add'>+	} else {</div><div class='add'>+		status = MOD_HDCP_STATUS_HDCP1_INVALID_BKSV;</div><div class='add'>+	}</div><div class='add'>+	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline enum mod_hdcp_status check_ksv_ready(struct mod_hdcp *hdcp)</div><div class='hunk'>@@ -135,6 +142,8 @@ static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> 	if (get_device_count(hdcp) == 0)</div><div class='ctx'> 		return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;</div><div class='ctx'> </div><div class='add'>+	hdcp-&gt;connection.trace.hdcp1.downstream_device_count = get_device_count(hdcp);</div><div class='add'>+</div><div class='ctx'> 	/* Some MST display may choose to report the internal panel as an HDCP RX.</div><div class='ctx'> 	 * To update this condition with 1(because the immediate repeater's internal</div><div class='ctx'> 	 * panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp).</div><div class='hunk'>@@ -432,18 +441,18 @@ static enum mod_hdcp_status authenticated_dp(struct mod_hdcp *hdcp,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (status == MOD_HDCP_STATUS_SUCCESS)</div><div class='del'>-		mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,</div><div class='del'>-				&amp;input-&gt;bstatus_read, &amp;status,</div><div class='del'>-				hdcp, "bstatus_read");</div><div class='del'>-	if (status == MOD_HDCP_STATUS_SUCCESS)</div><div class='del'>-		mod_hdcp_execute_and_set(check_link_integrity_dp,</div><div class='del'>-				&amp;input-&gt;link_integrity_check, &amp;status,</div><div class='del'>-				hdcp, "link_integrity_check");</div><div class='del'>-	if (status == MOD_HDCP_STATUS_SUCCESS)</div><div class='del'>-		mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,</div><div class='del'>-				&amp;input-&gt;reauth_request_check, &amp;status,</div><div class='del'>-				hdcp, "reauth_request_check");</div><div class='add'>+	mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,</div><div class='add'>+			&amp;input-&gt;bstatus_read, &amp;status,</div><div class='add'>+			hdcp, "bstatus_read");</div><div class='add'>+</div><div class='add'>+	mod_hdcp_execute_and_set(check_link_integrity_dp,</div><div class='add'>+			&amp;input-&gt;link_integrity_check, &amp;status,</div><div class='add'>+			hdcp, "link_integrity_check");</div><div class='add'>+</div><div class='add'>+	mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,</div><div class='add'>+			&amp;input-&gt;reauth_request_check, &amp;status,</div><div class='add'>+			hdcp, "reauth_request_check");</div><div class='add'>+</div><div class='ctx'> out:</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c<br/>index 733f22bed021..27500abf9fee 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c</a></div><div class='hunk'>@@ -27,6 +27,11 @@</div><div class='ctx'> </div><div class='ctx'> #include "hdcp.h"</div><div class='ctx'> </div><div class='add'>+static inline uint16_t get_hdmi_rxstatus_msg_size(const uint8_t rxstatus[2])</div><div class='add'>+{</div><div class='add'>+	return HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rxstatus[1]) &lt;&lt; 8 | rxstatus[0];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t is_ready = 0;</div><div class='hunk'>@@ -35,8 +40,7 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp</div><div class='ctx'> 		is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp-&gt;auth.msg.hdcp2.rxstatus_dp) ? 1 : 0;</div><div class='ctx'> 	else</div><div class='ctx'> 		is_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &amp;&amp;</div><div class='del'>-				(HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-						hdcp-&gt;auth.msg.hdcp2.rxstatus[0])) ? 1 : 0;</div><div class='add'>+				get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus) != 0) ? 1 : 0;</div><div class='ctx'> 	return is_ready ? MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 			MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;</div><div class='ctx'> }</div><div class='hunk'>@@ -44,6 +48,7 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp</div><div class='ctx'> static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	enum mod_hdcp_status status;</div><div class='add'>+	struct mod_hdcp_trace *trace = &amp;hdcp-&gt;connection.trace;</div><div class='ctx'> </div><div class='ctx'> 	if (is_dp_hdcp(hdcp))</div><div class='ctx'> 		status = (hdcp-&gt;auth.msg.hdcp2.rxcaps_dp[0] == HDCP_2_2_RX_CAPS_VERSION_VAL) &amp;&amp;</div><div class='hunk'>@@ -51,9 +56,14 @@ static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)</div><div class='ctx'> 				MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 				MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;</div><div class='ctx'> 	else</div><div class='del'>-		status = (hdcp-&gt;auth.msg.hdcp2.hdcp2version_hdmi &amp; HDCP_2_2_HDMI_SUPPORT_MASK) ?</div><div class='del'>-				MOD_HDCP_STATUS_SUCCESS :</div><div class='del'>-				MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;</div><div class='add'>+		status = (hdcp-&gt;auth.msg.hdcp2.hdcp2version_hdmi</div><div class='add'>+				 &amp; HDCP_2_2_HDMI_SUPPORT_MASK)</div><div class='add'>+				? MOD_HDCP_STATUS_SUCCESS</div><div class='add'>+				: MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;</div><div class='add'>+</div><div class='add'>+	if (status == MOD_HDCP_STATUS_SUCCESS)</div><div class='add'>+		trace-&gt;hdcp2.attempt_count++;</div><div class='add'>+</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -84,15 +94,13 @@ static inline enum mod_hdcp_status check_link_integrity_failure_dp(</div><div class='ctx'> static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	enum mod_hdcp_status status;</div><div class='del'>-	uint16_t size;</div><div class='ctx'> </div><div class='ctx'> 	if (is_dp_hdcp(hdcp)) {</div><div class='ctx'> 		status = MOD_HDCP_STATUS_SUCCESS;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		status = mod_hdcp_read_rxstatus(hdcp);</div><div class='ctx'> 		if (status == MOD_HDCP_STATUS_SUCCESS) {</div><div class='del'>-			size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-			       hdcp-&gt;auth.msg.hdcp2.rxstatus[0];</div><div class='add'>+			const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus);</div><div class='ctx'> 			status = (size == sizeof(hdcp-&gt;auth.msg.hdcp2.ake_cert)) ?</div><div class='ctx'> 					MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 					MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING;</div><div class='hunk'>@@ -104,7 +112,6 @@ static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp)</div><div class='ctx'> static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	enum mod_hdcp_status status;</div><div class='del'>-	uint8_t size;</div><div class='ctx'> </div><div class='ctx'> 	status = mod_hdcp_read_rxstatus(hdcp);</div><div class='ctx'> 	if (status != MOD_HDCP_STATUS_SUCCESS)</div><div class='hunk'>@@ -115,8 +122,7 @@ static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)</div><div class='ctx'> 				MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;</div><div class='ctx'> 	} else {</div><div class='del'>-		size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-		       hdcp-&gt;auth.msg.hdcp2.rxstatus[0];</div><div class='add'>+		const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus);</div><div class='ctx'> 		status = (size == sizeof(hdcp-&gt;auth.msg.hdcp2.ake_h_prime)) ?</div><div class='ctx'> 				MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;</div><div class='hunk'>@@ -128,7 +134,6 @@ out:</div><div class='ctx'> static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	enum mod_hdcp_status status;</div><div class='del'>-	uint8_t size;</div><div class='ctx'> </div><div class='ctx'> 	status = mod_hdcp_read_rxstatus(hdcp);</div><div class='ctx'> 	if (status != MOD_HDCP_STATUS_SUCCESS)</div><div class='hunk'>@@ -139,8 +144,7 @@ static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)</div><div class='ctx'> 				MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;</div><div class='ctx'> 	} else {</div><div class='del'>-		size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-		       hdcp-&gt;auth.msg.hdcp2.rxstatus[0];</div><div class='add'>+		const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus);</div><div class='ctx'> 		status = (size == sizeof(hdcp-&gt;auth.msg.hdcp2.ake_pairing_info)) ?</div><div class='ctx'> 				MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;</div><div class='hunk'>@@ -151,8 +155,7 @@ out:</div><div class='ctx'> </div><div class='ctx'> static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='del'>-	enum mod_hdcp_status status;</div><div class='del'>-	uint8_t size;</div><div class='add'>+	enum mod_hdcp_status status = MOD_HDCP_STATUS_FAILURE;</div><div class='ctx'> 	uint16_t max_wait = 20; // units of ms</div><div class='ctx'> 	uint16_t num_polls = 5;</div><div class='ctx'> 	uint16_t wait_time = max_wait / num_polls;</div><div class='hunk'>@@ -167,8 +170,7 @@ static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)</div><div class='ctx'> 			if (status != MOD_HDCP_STATUS_SUCCESS)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='del'>-			size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-			       hdcp-&gt;auth.msg.hdcp2.rxstatus[0];</div><div class='add'>+			const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus);</div><div class='ctx'> 			status = (size == sizeof(hdcp-&gt;auth.msg.hdcp2.lc_l_prime)) ?</div><div class='ctx'> 					MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 					MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING;</div><div class='hunk'>@@ -181,7 +183,6 @@ static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)</div><div class='ctx'> static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	enum mod_hdcp_status status;</div><div class='del'>-	uint8_t size;</div><div class='ctx'> </div><div class='ctx'> 	if (is_dp_hdcp(hdcp)) {</div><div class='ctx'> 		status = MOD_HDCP_STATUS_INVALID_OPERATION;</div><div class='hunk'>@@ -189,8 +190,7 @@ static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)</div><div class='ctx'> 		status = mod_hdcp_read_rxstatus(hdcp);</div><div class='ctx'> 		if (status != MOD_HDCP_STATUS_SUCCESS)</div><div class='ctx'> 			goto out;</div><div class='del'>-		size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-		       hdcp-&gt;auth.msg.hdcp2.rxstatus[0];</div><div class='add'>+		const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus);</div><div class='ctx'> 		status = (size == sizeof(hdcp-&gt;auth.msg.hdcp2.repeater_auth_stream_ready)) ?</div><div class='ctx'> 				MOD_HDCP_STATUS_SUCCESS :</div><div class='ctx'> 				MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING;</div><div class='hunk'>@@ -207,10 +207,17 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> </div><div class='ctx'> static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='add'>+	struct mod_hdcp_trace *trace = &amp;hdcp-&gt;connection.trace;</div><div class='add'>+</div><div class='ctx'> 	/* Avoid device count == 0 to do authentication */</div><div class='ctx'> 	if (get_device_count(hdcp) == 0)</div><div class='ctx'> 		return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;</div><div class='ctx'> </div><div class='add'>+	trace-&gt;hdcp2.downstream_device_count = get_device_count(hdcp);</div><div class='add'>+	trace-&gt;hdcp2.hdcp1_device_downstream =</div><div class='add'>+			HDCP_2_2_HDCP1_DEVICE_CONNECTED(hdcp-&gt;auth.msg.hdcp2.rx_id_list[2]);</div><div class='add'>+	trace-&gt;hdcp2.hdcp2_legacy_device_downstream =</div><div class='add'>+			HDCP_2_2_HDCP_2_0_REP_CONNECTED(hdcp-&gt;auth.msg.hdcp2.rx_id_list[2]);</div><div class='ctx'> 	/* Some MST display may choose to report the internal panel as an HDCP RX.   */</div><div class='ctx'> 	/* To update this condition with 1(because the immediate repeater's internal */</div><div class='ctx'> 	/* panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). */</div><div class='hunk'>@@ -249,8 +256,7 @@ static uint8_t process_rxstatus(struct mod_hdcp *hdcp,</div><div class='ctx'> 						sizeof(hdcp-&gt;auth.msg.hdcp2.rx_id_list);</div><div class='ctx'> 			else</div><div class='ctx'> 				hdcp-&gt;auth.msg.hdcp2.rx_id_list_size =</div><div class='del'>-					HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp-&gt;auth.msg.hdcp2.rxstatus[1]) &lt;&lt; 8 |</div><div class='del'>-					hdcp-&gt;auth.msg.hdcp2.rxstatus[0];</div><div class='add'>+					get_hdmi_rxstatus_msg_size(hdcp-&gt;auth.msg.hdcp2.rxstatus);</div><div class='ctx'> 		}</div><div class='ctx'> out:</div><div class='ctx'> 	return (*status == MOD_HDCP_STATUS_SUCCESS);</div><div class='hunk'>@@ -474,21 +480,30 @@ static enum mod_hdcp_status locality_check(struct mod_hdcp *hdcp,</div><div class='ctx'> 			&amp;input-&gt;lc_init_prepare, &amp;status,</div><div class='ctx'> 			hdcp, "lc_init_prepare"))</div><div class='ctx'> 		goto out;</div><div class='del'>-	if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init,</div><div class='del'>-			&amp;input-&gt;lc_init_write, &amp;status,</div><div class='del'>-			 hdcp, "lc_init_write"))</div><div class='del'>-		goto out;</div><div class='del'>-	if (is_dp_hdcp(hdcp))</div><div class='del'>-		msleep(16);</div><div class='del'>-	else</div><div class='del'>-		if (!mod_hdcp_execute_and_set(poll_l_prime_available,</div><div class='del'>-				&amp;input-&gt;l_prime_available_poll, &amp;status,</div><div class='del'>-				hdcp, "l_prime_available_poll"))</div><div class='add'>+</div><div class='add'>+	if (hdcp-&gt;connection.link.adjust.hdcp2.use_fw_locality_check) {</div><div class='add'>+		if (!mod_hdcp_execute_and_set(mod_hdcp_write_poll_read_lc_fw,</div><div class='add'>+				&amp;input-&gt;l_prime_combo_read, &amp;status,</div><div class='add'>+				hdcp, "l_prime_combo_read"))</div><div class='ctx'> 			goto out;</div><div class='del'>-	if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime,</div><div class='del'>-			&amp;input-&gt;l_prime_read, &amp;status,</div><div class='del'>-			hdcp, "l_prime_read"))</div><div class='del'>-		goto out;</div><div class='add'>+	} else {</div><div class='add'>+		if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init,</div><div class='add'>+				&amp;input-&gt;lc_init_write, &amp;status,</div><div class='add'>+				hdcp, "lc_init_write"))</div><div class='add'>+			goto out;</div><div class='add'>+		if (is_dp_hdcp(hdcp))</div><div class='add'>+			msleep(16);</div><div class='add'>+		else</div><div class='add'>+			if (!mod_hdcp_execute_and_set(poll_l_prime_available,</div><div class='add'>+					&amp;input-&gt;l_prime_available_poll, &amp;status,</div><div class='add'>+					hdcp, "l_prime_available_poll"))</div><div class='add'>+				goto out;</div><div class='add'>+		if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime,</div><div class='add'>+				&amp;input-&gt;l_prime_read, &amp;status,</div><div class='add'>+				hdcp, "l_prime_read"))</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_l_prime,</div><div class='ctx'> 			&amp;input-&gt;l_prime_validation, &amp;status,</div><div class='ctx'> 			hdcp, "l_prime_validation"))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c<br/>index c5f6c11de7e5..9316312a4df5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c</a></div><div class='hunk'>@@ -185,19 +185,32 @@ enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp,</div><div class='ctx'> 		set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case H2_A2_LOCALITY_CHECK:</div><div class='add'>+		/* 1A-05: consider disconnection after LC init a failure */</div><div class='ctx'> 		if (hdcp-&gt;state.stay_count &gt; 10 ||</div><div class='del'>-				input-&gt;lc_init_prepare != PASS ||</div><div class='del'>-				input-&gt;lc_init_write != PASS ||</div><div class='del'>-				input-&gt;l_prime_available_poll != PASS ||</div><div class='del'>-				input-&gt;l_prime_read != PASS) {</div><div class='del'>-			/*</div><div class='del'>-			 * 1A-05: consider disconnection after LC init a failure</div><div class='del'>-			 * 1A-13-1: consider invalid l' a failure</div><div class='del'>-			 * 1A-13-2: consider l' timeout a failure</div><div class='del'>-			 */</div><div class='add'>+				input-&gt;lc_init_prepare != PASS) {</div><div class='add'>+			fail_and_restart_in_ms(0, &amp;status, output);</div><div class='add'>+			break;</div><div class='add'>+		} else if (adjust-&gt;hdcp2.use_fw_locality_check &amp;&amp;</div><div class='add'>+				input-&gt;l_prime_combo_read != PASS) {</div><div class='add'>+			/* 1A-13-2: consider l' timeout a failure */</div><div class='add'>+			if (adjust-&gt;hdcp2.use_sw_locality_fallback) {</div><div class='add'>+				/* switch to software locality check */</div><div class='add'>+				adjust-&gt;hdcp2.use_fw_locality_check = 0;</div><div class='add'>+				callback_in_ms(0, output);</div><div class='add'>+				increment_stay_counter(hdcp);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			fail_and_restart_in_ms(0, &amp;status, output);</div><div class='add'>+			break;</div><div class='add'>+		} else if (!adjust-&gt;hdcp2.use_fw_locality_check &amp;&amp;</div><div class='add'>+					(input-&gt;lc_init_write != PASS ||</div><div class='add'>+					input-&gt;l_prime_available_poll != PASS ||</div><div class='add'>+					input-&gt;l_prime_read != PASS)) {</div><div class='add'>+			/* 1A-13-2: consider l' timeout a failure */</div><div class='ctx'> 			fail_and_restart_in_ms(0, &amp;status, output);</div><div class='ctx'> 			break;</div><div class='ctx'> 		} else if (input-&gt;l_prime_validation != PASS) {</div><div class='add'>+			/* 1A-13-1: consider invalid l' a failure */</div><div class='ctx'> 			callback_in_ms(0, output);</div><div class='ctx'> 			increment_stay_counter(hdcp);</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -500,13 +513,27 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case D2_A2_LOCALITY_CHECK:</div><div class='ctx'> 		if (hdcp-&gt;state.stay_count &gt; 10 ||</div><div class='del'>-				input-&gt;lc_init_prepare != PASS ||</div><div class='del'>-				input-&gt;lc_init_write != PASS ||</div><div class='del'>-				input-&gt;l_prime_read != PASS) {</div><div class='del'>-			/* 1A-12: consider invalid l' a failure */</div><div class='add'>+				input-&gt;lc_init_prepare != PASS) {</div><div class='add'>+			fail_and_restart_in_ms(0, &amp;status, output);</div><div class='add'>+			break;</div><div class='add'>+		} else if (adjust-&gt;hdcp2.use_fw_locality_check &amp;&amp;</div><div class='add'>+				input-&gt;l_prime_combo_read != PASS) {</div><div class='add'>+			if (adjust-&gt;hdcp2.use_sw_locality_fallback) {</div><div class='add'>+				/* switch to software locality check */</div><div class='add'>+				adjust-&gt;hdcp2.use_fw_locality_check = 0;</div><div class='add'>+				callback_in_ms(0, output);</div><div class='add'>+				increment_stay_counter(hdcp);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			fail_and_restart_in_ms(0, &amp;status, output);</div><div class='add'>+			break;</div><div class='add'>+		} else if (!adjust-&gt;hdcp2.use_fw_locality_check &amp;&amp;</div><div class='add'>+					(input-&gt;lc_init_write != PASS ||</div><div class='add'>+					input-&gt;l_prime_read != PASS)) {</div><div class='ctx'> 			fail_and_restart_in_ms(0, &amp;status, output);</div><div class='ctx'> 			break;</div><div class='ctx'> 		} else if (input-&gt;l_prime_validation != PASS) {</div><div class='add'>+			/* 1A-12: consider invalid l' a failure */</div><div class='ctx'> 			callback_in_ms(0, output);</div><div class='ctx'> 			increment_stay_counter(hdcp);</div><div class='ctx'> 			break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c<br/>index f7b5583ee609..0ca39873f807 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c</a></div><div class='hunk'>@@ -25,7 +25,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "hdcp.h"</div><div class='ctx'> </div><div class='add'>+#ifndef MIN</div><div class='ctx'> #define MIN(a, b) ((a) &lt; (b) ? (a) : (b))</div><div class='add'>+#endif</div><div class='ctx'> #define HDCP_I2C_ADDR 0x3a	/* 0x74 &gt;&gt; 1*/</div><div class='ctx'> #define KSV_READ_SIZE 0xf	/* 0x6803b - 0x6802c */</div><div class='ctx'> #define HDCP_MAX_AUX_TRANSACTION_SIZE 16</div><div class='hunk'>@@ -156,7 +158,15 @@ static enum mod_hdcp_status read(struct mod_hdcp *hdcp,</div><div class='ctx'> 	uint32_t cur_size = 0;</div><div class='ctx'> 	uint32_t data_offset = 0;</div><div class='ctx'> </div><div class='add'>+	if (msg_id == MOD_HDCP_MESSAGE_ID_INVALID ||</div><div class='add'>+		msg_id &gt;= MOD_HDCP_MESSAGE_ID_MAX)</div><div class='add'>+		return MOD_HDCP_STATUS_DDC_FAILURE;</div><div class='add'>+</div><div class='ctx'> 	if (is_dp_hdcp(hdcp)) {</div><div class='add'>+		int num_dpcd_addrs = ARRAY_SIZE(hdcp_dpcd_addrs);</div><div class='add'>+		if (msg_id &gt;= num_dpcd_addrs)</div><div class='add'>+			return MOD_HDCP_STATUS_DDC_FAILURE;</div><div class='add'>+</div><div class='ctx'> 		while (buf_len &gt; 0) {</div><div class='ctx'> 			cur_size = MIN(buf_len, HDCP_MAX_AUX_TRANSACTION_SIZE);</div><div class='ctx'> 			success = hdcp-&gt;config.ddc.funcs.read_dpcd(hdcp-&gt;config.ddc.handle,</div><div class='hunk'>@@ -171,6 +181,10 @@ static enum mod_hdcp_status read(struct mod_hdcp *hdcp,</div><div class='ctx'> 			data_offset += cur_size;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='add'>+		int num_i2c_offsets = ARRAY_SIZE(hdcp_i2c_offsets);</div><div class='add'>+		if (msg_id &gt;= num_i2c_offsets)</div><div class='add'>+			return MOD_HDCP_STATUS_DDC_FAILURE;</div><div class='add'>+</div><div class='ctx'> 		success = hdcp-&gt;config.ddc.funcs.read_i2c(</div><div class='ctx'> 				hdcp-&gt;config.ddc.handle,</div><div class='ctx'> 				HDCP_I2C_ADDR,</div><div class='hunk'>@@ -215,7 +229,15 @@ static enum mod_hdcp_status write(struct mod_hdcp *hdcp,</div><div class='ctx'> 	uint32_t cur_size = 0;</div><div class='ctx'> 	uint32_t data_offset = 0;</div><div class='ctx'> </div><div class='add'>+	if (msg_id == MOD_HDCP_MESSAGE_ID_INVALID ||</div><div class='add'>+		msg_id &gt;= MOD_HDCP_MESSAGE_ID_MAX)</div><div class='add'>+		return MOD_HDCP_STATUS_DDC_FAILURE;</div><div class='add'>+</div><div class='ctx'> 	if (is_dp_hdcp(hdcp)) {</div><div class='add'>+		int num_dpcd_addrs = ARRAY_SIZE(hdcp_dpcd_addrs);</div><div class='add'>+		if (msg_id &gt;= num_dpcd_addrs)</div><div class='add'>+			return MOD_HDCP_STATUS_DDC_FAILURE;</div><div class='add'>+</div><div class='ctx'> 		while (buf_len &gt; 0) {</div><div class='ctx'> 			cur_size = MIN(buf_len, HDCP_MAX_AUX_TRANSACTION_SIZE);</div><div class='ctx'> 			success = hdcp-&gt;config.ddc.funcs.write_dpcd(</div><div class='hunk'>@@ -231,6 +253,10 @@ static enum mod_hdcp_status write(struct mod_hdcp *hdcp,</div><div class='ctx'> 			data_offset += cur_size;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='add'>+		int num_i2c_offsets = ARRAY_SIZE(hdcp_i2c_offsets);</div><div class='add'>+		if (msg_id &gt;= num_i2c_offsets)</div><div class='add'>+			return MOD_HDCP_STATUS_DDC_FAILURE;</div><div class='add'>+</div><div class='ctx'> 		hdcp-&gt;buf[0] = hdcp_i2c_offsets[msg_id];</div><div class='ctx'> 		memmove(&amp;hdcp-&gt;buf[1], buf, buf_len);</div><div class='ctx'> 		success = hdcp-&gt;config.ddc.funcs.write_i2c(</div><div class='hunk'>@@ -662,3 +688,76 @@ enum mod_hdcp_status mod_hdcp_clear_cp_irq_status(struct mod_hdcp *hdcp)</div><div class='ctx'> </div><div class='ctx'> 	return MOD_HDCP_STATUS_INVALID_OPERATION;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static bool write_stall_read_lc_fw_aux(struct mod_hdcp *hdcp)</div><div class='add'>+{</div><div class='add'>+	struct mod_hdcp_message_hdcp2 *hdcp2 = &amp;hdcp-&gt;auth.msg.hdcp2;</div><div class='add'>+</div><div class='add'>+	struct mod_hdcp_atomic_op_aux write = {</div><div class='add'>+		hdcp_dpcd_addrs[MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT],</div><div class='add'>+		hdcp2-&gt;lc_init + 1,</div><div class='add'>+		sizeof(hdcp2-&gt;lc_init) - 1,</div><div class='add'>+	};</div><div class='add'>+	struct mod_hdcp_atomic_op_aux stall = { 0, NULL, 0, };</div><div class='add'>+	struct mod_hdcp_atomic_op_aux read = {</div><div class='add'>+		hdcp_dpcd_addrs[MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME],</div><div class='add'>+		hdcp2-&gt;lc_l_prime + 1,</div><div class='add'>+		sizeof(hdcp2-&gt;lc_l_prime) - 1,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	hdcp2-&gt;lc_l_prime[0] = HDCP_2_2_LC_SEND_LPRIME;</div><div class='add'>+</div><div class='add'>+	return hdcp-&gt;config.ddc.funcs.atomic_write_poll_read_aux(</div><div class='add'>+			hdcp-&gt;config.ddc.handle,</div><div class='add'>+			&amp;write,</div><div class='add'>+			&amp;stall,</div><div class='add'>+			&amp;read,</div><div class='add'>+			16 * 1000,</div><div class='add'>+			0</div><div class='add'>+	);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool write_poll_read_lc_fw_i2c(struct mod_hdcp *hdcp)</div><div class='add'>+{</div><div class='add'>+	struct mod_hdcp_message_hdcp2 *hdcp2 = &amp;hdcp-&gt;auth.msg.hdcp2;</div><div class='add'>+	uint8_t expected_rxstatus[2] = { sizeof(hdcp2-&gt;lc_l_prime) };</div><div class='add'>+</div><div class='add'>+	hdcp-&gt;buf[0] = hdcp_i2c_offsets[MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT];</div><div class='add'>+	memmove(&amp;hdcp-&gt;buf[1], hdcp2-&gt;lc_init, sizeof(hdcp2-&gt;lc_init));</div><div class='add'>+</div><div class='add'>+	struct mod_hdcp_atomic_op_i2c write = {</div><div class='add'>+		HDCP_I2C_ADDR,</div><div class='add'>+		0,</div><div class='add'>+		hdcp-&gt;buf,</div><div class='add'>+		sizeof(hdcp2-&gt;lc_init) + 1,</div><div class='add'>+	};</div><div class='add'>+	struct mod_hdcp_atomic_op_i2c poll = {</div><div class='add'>+		HDCP_I2C_ADDR,</div><div class='add'>+		hdcp_i2c_offsets[MOD_HDCP_MESSAGE_ID_READ_RXSTATUS],</div><div class='add'>+		expected_rxstatus,</div><div class='add'>+		sizeof(expected_rxstatus),</div><div class='add'>+	};</div><div class='add'>+	struct mod_hdcp_atomic_op_i2c read = {</div><div class='add'>+		HDCP_I2C_ADDR,</div><div class='add'>+		hdcp_i2c_offsets[MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME],</div><div class='add'>+		hdcp2-&gt;lc_l_prime,</div><div class='add'>+		sizeof(hdcp2-&gt;lc_l_prime),</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return hdcp-&gt;config.ddc.funcs.atomic_write_poll_read_i2c(</div><div class='add'>+			hdcp-&gt;config.ddc.handle,</div><div class='add'>+			&amp;write,</div><div class='add'>+			&amp;poll,</div><div class='add'>+			&amp;read,</div><div class='add'>+			20 * 1000,</div><div class='add'>+			6</div><div class='add'>+	);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum mod_hdcp_status mod_hdcp_write_poll_read_lc_fw(struct mod_hdcp *hdcp)</div><div class='add'>+{</div><div class='add'>+	const bool success = (is_dp_hdcp(hdcp) ? write_stall_read_lc_fw_aux : write_poll_read_lc_fw_i2c)(hdcp);</div><div class='add'>+</div><div class='add'>+	return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE;</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c<br/>index 6b3b5f610907..5cb979c2cf8c 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c</a></div><div class='hunk'>@@ -125,129 +125,11 @@ void mod_hdcp_log_ddc_trace(struct mod_hdcp *hdcp)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define CASE_FORMAT(entry) case entry: return #entry;</div><div class='ctx'> char *mod_hdcp_status_to_str(int32_t status)</div><div class='ctx'> {</div><div class='ctx'> 	switch (status) {</div><div class='del'>-	case MOD_HDCP_STATUS_SUCCESS:</div><div class='del'>-		return "MOD_HDCP_STATUS_SUCCESS";</div><div class='del'>-	case MOD_HDCP_STATUS_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_RESET_NEEDED:</div><div class='del'>-		return "MOD_HDCP_STATUS_RESET_NEEDED";</div><div class='del'>-	case MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND:</div><div class='del'>-		return "MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND";</div><div class='del'>-	case MOD_HDCP_STATUS_DISPLAY_NOT_FOUND:</div><div class='del'>-		return "MOD_HDCP_STATUS_DISPLAY_NOT_FOUND";</div><div class='del'>-	case MOD_HDCP_STATUS_INVALID_STATE:</div><div class='del'>-		return "MOD_HDCP_STATUS_INVALID_STATE";</div><div class='del'>-	case MOD_HDCP_STATUS_NOT_IMPLEMENTED:</div><div class='del'>-		return "MOD_HDCP_STATUS_NOT_IMPLEMENTED";</div><div class='del'>-	case MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP1_INVALID_BKSV:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP1_INVALID_BKSV";</div><div class='del'>-	case MOD_HDCP_STATUS_DDC_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_DDC_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_INVALID_OPERATION:</div><div class='del'>-		return "MOD_HDCP_STATUS_INVALID_OPERATION";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";</div><div class='del'>-	case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE:</div><div class='del'>-		return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE";</div><div class='add'>+	MOD_HDCP_STATUS_LIST(CASE_FORMAT)</div><div class='ctx'> 	default:</div><div class='ctx'> 		return "MOD_HDCP_STATUS_UNKNOWN";</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h<br/>index 1d83c1b9da10..26553aa4c5ca 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)</div><div class='ctx'> #define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__)</div><div class='ctx'> #define HDCP_LOG_DDC(hdcp, ...) pr_debug("[HDCP_DDC]:"__VA_ARGS__)</div><div class='add'>+#define HDCP_LOG_TRA(hdcp) do {} while (0)</div><div class='ctx'> </div><div class='ctx'> /* default logs */</div><div class='ctx'> #define HDCP_ERROR_TRACE(hdcp, status) \</div><div class='hunk'>@@ -131,4 +132,9 @@</div><div class='ctx'> 		HDCP_LOG_TOP(hdcp, "[Link %d] %s display %d", hdcp-&gt;config.index, __func__, i); \</div><div class='ctx'> } while (0)</div><div class='ctx'> </div><div class='add'>+#define HDCP_AUTH_COMPLETE_TRACE(hdcp) do { \</div><div class='add'>+		mod_hdcp_log_ddc_trace(hdcp); \</div><div class='add'>+		HDCP_LOG_TRA(hdcp); \</div><div class='add'>+} while (0)</div><div class='add'>+</div><div class='ctx'> #endif // MOD_HDCP_LOG_H_</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c<br/>index 7c9805705fd3..6b7db8ec9a53 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c</a></div><div class='hunk'>@@ -260,6 +260,9 @@ enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp)</div><div class='ctx'> 		return MOD_HDCP_STATUS_FAILURE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!display)</div><div class='add'>+		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;</div><div class='add'>+</div><div class='ctx'> 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp-&gt;hdcp_context.context.mem_context.shared_buf;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;psp-&gt;hdcp_context.mutex);</div><div class='hunk'>@@ -368,6 +371,9 @@ enum mod_hdcp_status mod_hdcp_hdcp1_enable_encryption(struct mod_hdcp *hdcp)</div><div class='ctx'> 	struct mod_hdcp_display *display = get_first_active_display(hdcp);</div><div class='ctx'> 	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;</div><div class='ctx'> </div><div class='add'>+	if (!display)</div><div class='add'>+		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;psp-&gt;hdcp_context.mutex);</div><div class='ctx'> 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp-&gt;hdcp_context.context.mem_context.shared_buf;</div><div class='ctx'> 	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));</div><div class='hunk'>@@ -513,9 +519,6 @@ enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)</div><div class='ctx'> 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp-&gt;hdcp_context.context.mem_context.shared_buf;</div><div class='ctx'> 	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));</div><div class='ctx'> </div><div class='del'>-	if (!display)</div><div class='del'>-		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;</div><div class='del'>-</div><div class='ctx'> 	hdcp_cmd-&gt;in_msg.hdcp2_create_session_v2.display_handle = display-&gt;index;</div><div class='ctx'> </div><div class='ctx'> 	if (hdcp-&gt;connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_0)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h<br/>index cc3dc9b589f6..57916ed98c86 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h</a></div><div class='hunk'>@@ -110,25 +110,6 @@ struct mod_vrr_params {</div><div class='ctx'> struct mod_freesync *mod_freesync_create(struct dc *dc);</div><div class='ctx'> void mod_freesync_destroy(struct mod_freesync *mod_freesync);</div><div class='ctx'> </div><div class='del'>-bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,</div><div class='del'>-		const struct dc_stream_state *stream,</div><div class='del'>-		unsigned int *vmin,</div><div class='del'>-		unsigned int *vmax);</div><div class='del'>-</div><div class='del'>-bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		unsigned int *nom_v_pos,</div><div class='del'>-		unsigned int *v_pos);</div><div class='del'>-</div><div class='del'>-void mod_freesync_get_settings(struct mod_freesync *mod_freesync,</div><div class='del'>-		const struct mod_vrr_params *vrr,</div><div class='del'>-		unsigned int *v_total_min, unsigned int *v_total_max,</div><div class='del'>-		unsigned int *event_triggers,</div><div class='del'>-		unsigned int *window_min, unsigned int *window_max,</div><div class='del'>-		unsigned int *lfc_mid_point_in_us,</div><div class='del'>-		unsigned int *inserted_frames,</div><div class='del'>-		unsigned int *inserted_duration_in_us);</div><div class='del'>-</div><div class='ctx'> void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		const struct mod_vrr_params *vrr,</div><div class='hunk'>@@ -155,13 +136,6 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,</div><div class='ctx'> unsigned long long mod_freesync_calc_nominal_field_rate(</div><div class='ctx'> 			const struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='del'>-unsigned long long mod_freesync_calc_field_rate_from_timing(</div><div class='del'>-		unsigned int vtotal, unsigned int htotal, unsigned int pix_clk);</div><div class='del'>-</div><div class='del'>-bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,</div><div class='del'>-		uint32_t max_refresh_cap_in_uhz,</div><div class='del'>-		uint32_t nominal_field_rate_in_uhz);</div><div class='del'>-</div><div class='ctx'> unsigned int mod_freesync_calc_v_total_from_refresh(</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		unsigned int refresh_in_uhz);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h<br/>index a4d344a4db9e..835467225458 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h</a></div><div class='hunk'>@@ -35,69 +35,74 @@ struct mod_hdcp;</div><div class='ctx'> #define MAX_NUM_OF_DISPLAYS 6</div><div class='ctx'> #define MAX_NUM_OF_ATTEMPTS 4</div><div class='ctx'> #define MAX_NUM_OF_ERROR_TRACE 10</div><div class='add'>+#define MOD_HDCP_STATUS_LIST(FORMAT) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_SUCCESS) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_RESET_NEEDED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_DISPLAY_NOT_FOUND) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_INVALID_STATE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_NOT_IMPLEMENTED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP1_INVALID_BKSV) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_DDC_FAILURE) /* TODO: specific errors */ \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_INVALID_OPERATION) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE) \</div><div class='add'>+	FORMAT(MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE)</div><div class='add'>+</div><div class='add'>+#define ENUM_FORMAT(entry) entry,</div><div class='ctx'> </div><div class='ctx'> /* detailed return status */</div><div class='ctx'> enum mod_hdcp_status {</div><div class='del'>-	MOD_HDCP_STATUS_SUCCESS = 0,</div><div class='del'>-	MOD_HDCP_STATUS_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_RESET_NEEDED,</div><div class='del'>-	MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND,</div><div class='del'>-	MOD_HDCP_STATUS_DISPLAY_NOT_FOUND,</div><div class='del'>-	MOD_HDCP_STATUS_INVALID_STATE,</div><div class='del'>-	MOD_HDCP_STATUS_NOT_IMPLEMENTED,</div><div class='del'>-	MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP1_INVALID_BKSV,</div><div class='del'>-	MOD_HDCP_STATUS_DDC_FAILURE, /* TODO: specific errors */</div><div class='del'>-	MOD_HDCP_STATUS_INVALID_OPERATION,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,</div><div class='del'>-	MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE,</div><div class='add'>+	MOD_HDCP_STATUS_LIST(ENUM_FORMAT)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mod_hdcp_displayport {</div><div class='hunk'>@@ -133,9 +138,22 @@ enum mod_hdcp_display_disable_option {</div><div class='ctx'> 	MOD_HDCP_DISPLAY_DISABLE_ENCRYPTION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mod_hdcp_atomic_op_i2c {</div><div class='add'>+	uint8_t address;</div><div class='add'>+	uint8_t offset;</div><div class='add'>+	uint8_t *data;</div><div class='add'>+	uint32_t size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mod_hdcp_atomic_op_aux {</div><div class='add'>+	uint32_t address;</div><div class='add'>+	uint8_t *data;</div><div class='add'>+	uint32_t size;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mod_hdcp_ddc {</div><div class='ctx'> 	void *handle;</div><div class='del'>-	struct {</div><div class='add'>+	struct mod_hdcp_ddc_funcs {</div><div class='ctx'> 		bool (*read_i2c)(void *handle,</div><div class='ctx'> 				uint32_t address,</div><div class='ctx'> 				uint8_t offset,</div><div class='hunk'>@@ -153,6 +171,22 @@ struct mod_hdcp_ddc {</div><div class='ctx'> 				uint32_t address,</div><div class='ctx'> 				const uint8_t *data,</div><div class='ctx'> 				uint32_t size);</div><div class='add'>+		bool (*atomic_write_poll_read_i2c)(</div><div class='add'>+				void *handle,</div><div class='add'>+				const struct mod_hdcp_atomic_op_i2c *write,</div><div class='add'>+				const struct mod_hdcp_atomic_op_i2c *poll,</div><div class='add'>+				struct mod_hdcp_atomic_op_i2c *read,</div><div class='add'>+				uint32_t poll_timeout_us,</div><div class='add'>+				uint8_t poll_mask_msb</div><div class='add'>+		);</div><div class='add'>+		bool (*atomic_write_poll_read_aux)(</div><div class='add'>+				void *handle,</div><div class='add'>+				const struct mod_hdcp_atomic_op_aux *write,</div><div class='add'>+				const struct mod_hdcp_atomic_op_aux *poll,</div><div class='add'>+				struct mod_hdcp_atomic_op_aux *read,</div><div class='add'>+				uint32_t poll_timeout_us,</div><div class='add'>+				uint8_t poll_mask_msb</div><div class='add'>+		);</div><div class='ctx'> 	} funcs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -185,11 +219,14 @@ struct mod_hdcp_link_adjustment_hdcp2 {</div><div class='ctx'> 	uint8_t force_type		: 2;</div><div class='ctx'> 	uint8_t force_no_stored_km	: 1;</div><div class='ctx'> 	uint8_t increase_h_prime_timeout: 1;</div><div class='del'>-	uint8_t reserved		: 3;</div><div class='add'>+	uint8_t use_fw_locality_check 	: 1;</div><div class='add'>+	uint8_t use_sw_locality_fallback: 1;</div><div class='add'>+	uint8_t reserved		: 1;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mod_hdcp_link_adjustment {</div><div class='ctx'> 	uint8_t auth_delay;</div><div class='add'>+	uint8_t retry_limit;</div><div class='ctx'> 	struct mod_hdcp_link_adjustment_hdcp1 hdcp1;</div><div class='ctx'> 	struct mod_hdcp_link_adjustment_hdcp2 hdcp2;</div><div class='ctx'> };</div><div class='hunk'>@@ -199,9 +236,23 @@ struct mod_hdcp_error {</div><div class='ctx'> 	uint8_t state_id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mod_hdcp1_trace {</div><div class='add'>+	uint8_t attempt_count;</div><div class='add'>+	uint8_t downstream_device_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mod_hdcp2_trace {</div><div class='add'>+	uint8_t attempt_count;</div><div class='add'>+	uint8_t downstream_device_count;</div><div class='add'>+	uint8_t hdcp1_device_downstream;</div><div class='add'>+	uint8_t hdcp2_legacy_device_downstream;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mod_hdcp_trace {</div><div class='ctx'> 	struct mod_hdcp_error errors[MAX_NUM_OF_ERROR_TRACE];</div><div class='ctx'> 	uint8_t error_count;</div><div class='add'>+	struct mod_hdcp1_trace hdcp1;</div><div class='add'>+	struct mod_hdcp2_trace hdcp2;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum mod_hdcp_encryption_status {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c<br/>index 738ee763f24a..b3d55cac3569 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c</a></div><div class='hunk'>@@ -147,15 +147,12 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */</div><div class='del'>-	if (stream-&gt;link-&gt;psr_settings.psr_feature_enabled) {</div><div class='del'>-		if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1)</div><div class='del'>-			vsc_packet_revision = vsc_packet_rev4;</div><div class='del'>-		else if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1)</div><div class='del'>-			vsc_packet_revision = vsc_packet_rev2;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (stream-&gt;link-&gt;replay_settings.config.replay_supported)</div><div class='add'>+	if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1)</div><div class='add'>+		vsc_packet_revision = vsc_packet_rev4;</div><div class='add'>+	else if (stream-&gt;link-&gt;replay_settings.config.replay_supported)</div><div class='ctx'> 		vsc_packet_revision = vsc_packet_rev4;</div><div class='add'>+	else if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1)</div><div class='add'>+		vsc_packet_revision = vsc_packet_rev2;</div><div class='ctx'> </div><div class='ctx'> 	/* Update to revision 5 for extended colorimetry support */</div><div class='ctx'> 	if (stream-&gt;use_vsc_sdp_for_colorimetry)</div><div class='hunk'>@@ -386,10 +383,10 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,</div><div class='ctx'> 				colorimetryFormat = ColorimetryYCC_DP_ITU709;</div><div class='ctx'> 			else if (cs == COLOR_SPACE_ADOBERGB)</div><div class='ctx'> 				colorimetryFormat = ColorimetryYCC_DP_AdobeYCC;</div><div class='del'>-			else if (cs == COLOR_SPACE_2020_YCBCR)</div><div class='add'>+			else if (cs == COLOR_SPACE_2020_YCBCR_LIMITED)</div><div class='ctx'> 				colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr;</div><div class='ctx'> </div><div class='del'>-			if (cs == COLOR_SPACE_2020_YCBCR &amp;&amp; tf == TRANSFER_FUNC_GAMMA_22)</div><div class='add'>+			if (cs == COLOR_SPACE_2020_YCBCR_LIMITED &amp;&amp; tf == TRANSFER_FUNC_GAMMA_22)</div><div class='ctx'> 				colorimetryFormat = ColorimetryYCC_DP_ITU709;</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='hunk'>@@ -539,8 +536,6 @@ void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream,</div><div class='ctx'> 			mod_build_adaptive_sync_infopacket_v2(stream, param, info_packet);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case FREESYNC_TYPE_PCON_IN_WHITELIST:</div><div class='del'>-		mod_build_adaptive_sync_infopacket_v1(info_packet);</div><div class='del'>-		break;</div><div class='ctx'> 	case ADAPTIVE_SYNC_TYPE_EDP:</div><div class='ctx'> 		mod_build_adaptive_sync_infopacket_v1(info_packet);</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c<br/>index 2a3698fd2dc2..fd139b219bf9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.c?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/power/power_helpers.c</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.c?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/power/power_helpers.c</a></div><div class='hunk'>@@ -841,6 +841,8 @@ bool is_psr_su_specific_panel(struct dc_link *link)</div><div class='ctx'> 				isPSRSUSupported = false;</div><div class='ctx'> 			else if (dpcd_caps-&gt;sink_dev_id_str[1] == 0x08 &amp;&amp; dpcd_caps-&gt;sink_dev_id_str[0] == 0x03)</div><div class='ctx'> 				isPSRSUSupported = false;</div><div class='add'>+			else if (dpcd_caps-&gt;sink_dev_id_str[1] == 0x08 &amp;&amp; dpcd_caps-&gt;sink_dev_id_str[0] == 0x01)</div><div class='add'>+				isPSRSUSupported = false;</div><div class='ctx'> 			else if (dpcd_caps-&gt;psr_info.force_psrsu_cap == 0x1)</div><div class='ctx'> 				isPSRSUSupported = true;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -973,6 +975,50 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void set_replay_frame_skip_number(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type,</div><div class='add'>+	uint32_t coasting_vtotal_refresh_rate_mhz,</div><div class='add'>+	uint32_t flicker_free_refresh_rate_mhz,</div><div class='add'>+	bool is_defer)</div><div class='add'>+{</div><div class='add'>+	uint32_t *frame_skip_number_array = NULL;</div><div class='add'>+	uint32_t frame_skip_number = 0;</div><div class='add'>+</div><div class='add'>+	if (link == NULL || flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (is_defer)</div><div class='add'>+		frame_skip_number_array = link-&gt;replay_settings.defer_frame_skip_number_table;</div><div class='add'>+	else</div><div class='add'>+		frame_skip_number_array = link-&gt;replay_settings.frame_skip_number_table;</div><div class='add'>+</div><div class='add'>+	if (frame_skip_number_array == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz;</div><div class='add'>+</div><div class='add'>+	if (frame_skip_number &gt;= 1)</div><div class='add'>+		frame_skip_number_array[type] = frame_skip_number - 1;</div><div class='add'>+	else</div><div class='add'>+		frame_skip_number_array[type] = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void set_replay_defer_update_coasting_vtotal(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type,</div><div class='add'>+	uint32_t vtotal)</div><div class='add'>+{</div><div class='add'>+	link-&gt;replay_settings.defer_update_coasting_vtotal_table[type] = vtotal;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_replay_coasting_vtotal_from_defer(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type)</div><div class='add'>+{</div><div class='add'>+	link-&gt;replay_settings.coasting_vtotal_table[type] =</div><div class='add'>+		link-&gt;replay_settings.defer_update_coasting_vtotal_table[type];</div><div class='add'>+	link-&gt;replay_settings.frame_skip_number_table[type] =</div><div class='add'>+		link-&gt;replay_settings.defer_frame_skip_number_table[type];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void set_replay_coasting_vtotal(struct dc_link *link,</div><div class='ctx'> 	enum replay_coasting_vtotal_type type,</div><div class='ctx'> 	uint32_t vtotal)</div><div class='hunk'>@@ -980,9 +1026,9 @@ void set_replay_coasting_vtotal(struct dc_link *link,</div><div class='ctx'> 	link-&gt;replay_settings.coasting_vtotal_table[type] = vtotal;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void set_replay_ips_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal)</div><div class='add'>+void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal)</div><div class='ctx'> {</div><div class='del'>-	link-&gt;replay_settings.abm_with_ips_on_full_screen_video_pseudo_vtotal = vtotal;</div><div class='add'>+	link-&gt;replay_settings.low_rr_full_screen_video_pseudo_vtotal = vtotal;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void calculate_replay_link_off_frame_count(struct dc_link *link,</div><div class='hunk'>@@ -991,19 +1037,18 @@ void calculate_replay_link_off_frame_count(struct dc_link *link,</div><div class='ctx'> 	uint8_t max_link_off_frame_count = 0;</div><div class='ctx'> 	uint16_t max_deviation_line = 0,  pixel_deviation_per_line = 0;</div><div class='ctx'> </div><div class='add'>+	if (!link || link-&gt;replay_settings.config.replay_version != DC_FREESYNC_REPLAY)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	max_deviation_line = link-&gt;dpcd_caps.pr_info.max_deviation_line;</div><div class='ctx'> 	pixel_deviation_per_line = link-&gt;dpcd_caps.pr_info.pixel_deviation_per_line;</div><div class='ctx'> </div><div class='del'>-	if (htotal != 0 &amp;&amp; vtotal != 0)</div><div class='add'>+	if (htotal != 0 &amp;&amp; vtotal != 0 &amp;&amp; pixel_deviation_per_line != 0)</div><div class='ctx'> 		max_link_off_frame_count = htotal * max_deviation_line / (pixel_deviation_per_line * vtotal);</div><div class='ctx'> 	else</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> </div><div class='del'>-	link-&gt;replay_settings.link_off_frame_count_level =</div><div class='del'>-		max_link_off_frame_count &gt;= PR_LINK_OFF_FRAME_COUNT_BEST ? PR_LINK_OFF_FRAME_COUNT_BEST :</div><div class='del'>-		max_link_off_frame_count &gt;= PR_LINK_OFF_FRAME_COUNT_GOOD ? PR_LINK_OFF_FRAME_COUNT_GOOD :</div><div class='del'>-		PR_LINK_OFF_FRAME_COUNT_FAIL;</div><div class='del'>-</div><div class='add'>+	link-&gt;replay_settings.link_off_frame_count = max_link_off_frame_count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps)</div><div class='hunk'>@@ -1027,3 +1072,8 @@ bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_back</div><div class='ctx'> 	memcpy(caps-&gt;data_points, custom_backlight_profiles[config_no].data_points, data_points_size);</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void reset_replay_dsync_error_count(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	link-&gt;replay_settings.replay_desync_error_fail_count = 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h<br/>index ff7e6f3cd6be..87d31d9dce5a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/display/modules/power/power_helpers.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/display/modules/power/power_helpers.h</a></div><div class='hunk'>@@ -57,7 +57,17 @@ void init_replay_config(struct dc_link *link, struct replay_config *pr_config);</div><div class='ctx'> void set_replay_coasting_vtotal(struct dc_link *link,</div><div class='ctx'> 	enum replay_coasting_vtotal_type type,</div><div class='ctx'> 	uint32_t vtotal);</div><div class='del'>-void set_replay_ips_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal);</div><div class='add'>+void set_replay_defer_update_coasting_vtotal(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type,</div><div class='add'>+	uint32_t vtotal);</div><div class='add'>+void set_replay_frame_skip_number(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type,</div><div class='add'>+	uint32_t coasting_vtotal_refresh_rate_Mhz,</div><div class='add'>+	uint32_t flicker_free_refresh_rate_Mhz,</div><div class='add'>+	bool is_defer);</div><div class='add'>+void update_replay_coasting_vtotal_from_defer(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type);</div><div class='add'>+void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal);</div><div class='ctx'> void calculate_replay_link_off_frame_count(struct dc_link *link,</div><div class='ctx'> 	uint16_t vtotal, uint16_t htotal);</div><div class='ctx'> </div><div class='hunk'>@@ -73,4 +83,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> bool fill_custom_backlight_caps(unsigned int config_no,</div><div class='ctx'> 		struct dm_acpi_atif_backlight_caps *caps);</div><div class='add'>+void reset_replay_dsync_error_count(struct dc_link *link);</div><div class='add'>+void change_replay_to_psr(struct dc_link *link);</div><div class='add'>+void change_psr_to_replay(struct dc_link *link);</div><div class='ctx'> #endif /* MODULES_POWER_POWER_HELPERS_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h<br/>index 2d089d30518f..06badbf0c5b9 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_acpi.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_acpi.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_acpi.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/amd_acpi.h</a></div><div class='hunk'>@@ -61,7 +61,7 @@ struct atif_qbtc_arguments {</div><div class='ctx'> </div><div class='ctx'> struct atif_qbtc_data_point {</div><div class='ctx'> 	u8 luminance;		/* luminance in percent */</div><div class='del'>-	u8 ipnut_signal;	/* input signal in range 0-255 */</div><div class='add'>+	u8 input_signal;	/* input signal in range 0-255 */</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='ctx'> struct atif_qbtc_output {</div><div class='hunk'>@@ -75,6 +75,8 @@ struct atif_qbtc_output {</div><div class='ctx'> 	u8 number_of_points;	/* number of data points */</div><div class='ctx'> 	struct atif_qbtc_data_point data_points[ATIF_QBTC_MAX_DATA_POINTS];</div><div class='ctx'> } __packed;</div><div class='add'>+static_assert(ATIF_QBTC_MAX_DATA_POINTS == MAX_LUMINANCE_DATA_POINTS);</div><div class='add'>+static_assert(sizeof(struct atif_qbtc_data_point) == sizeof(struct amdgpu_dm_luminance_data));</div><div class='ctx'> </div><div class='ctx'> #define ATIF_NOTIFY_MASK	0x3</div><div class='ctx'> #define ATIF_NOTIFY_NONE	0</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/amd_cper.h b/drivers/gpu/drm/amd/include/amd_cper.h<br/>new file mode 100644<br/>index 000000000000..a252ee4c7874<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_cper.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/amd_cper.h</a></div><div class='hunk'>@@ -0,0 +1,269 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2025 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#ifndef __AMD_CPER_H__</div><div class='add'>+#define __AMD_CPER_H__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/uuid.h&gt;</div><div class='add'>+</div><div class='add'>+#define CPER_HDR_REV_1          (0x100)</div><div class='add'>+#define CPER_SEC_MINOR_REV_1    (0x01)</div><div class='add'>+#define CPER_SEC_MAJOR_REV_22   (0x22)</div><div class='add'>+#define CPER_MAX_OAM_COUNT      (8)</div><div class='add'>+</div><div class='add'>+#define CPER_CTX_TYPE_CRASH     (1)</div><div class='add'>+#define CPER_CTX_TYPE_BOOT      (9)</div><div class='add'>+</div><div class='add'>+#define CPER_CREATOR_ID_AMDGPU	"amdgpu"</div><div class='add'>+</div><div class='add'>+#define CPER_NOTIFY_MCE                                               \</div><div class='add'>+	GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \</div><div class='add'>+		  0xE1, 0x49, 0x13, 0xBB)</div><div class='add'>+#define CPER_NOTIFY_CMC                                               \</div><div class='add'>+	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \</div><div class='add'>+		  0xEB, 0xD4, 0xF8, 0x90)</div><div class='add'>+#define BOOT_TYPE                                                     \</div><div class='add'>+	GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \</div><div class='add'>+		  0xD4, 0x64, 0xB3, 0x8F)</div><div class='add'>+</div><div class='add'>+#define AMD_CRASHDUMP                                                 \</div><div class='add'>+	GUID_INIT(0x32AC0C78, 0x2623, 0x48F6, 0xB0, 0xD0, 0x73, 0x65, \</div><div class='add'>+		  0x72, 0x5F, 0xD6, 0xAE)</div><div class='add'>+#define AMD_GPU_NONSTANDARD_ERROR                                     \</div><div class='add'>+	GUID_INIT(0x32AC0C78, 0x2623, 0x48F6, 0x81, 0xA2, 0xAC, 0x69, \</div><div class='add'>+		  0x17, 0x80, 0x55, 0x1D)</div><div class='add'>+#define PROC_ERR_SECTION_TYPE                                         \</div><div class='add'>+	GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \</div><div class='add'>+		  0x24, 0x2B, 0x6E, 0x1D)</div><div class='add'>+</div><div class='add'>+enum cper_error_severity {</div><div class='add'>+	CPER_SEV_NON_FATAL_UNCORRECTED = 0,</div><div class='add'>+	CPER_SEV_FATAL                 = 1,</div><div class='add'>+	CPER_SEV_NON_FATAL_CORRECTED   = 2,</div><div class='add'>+	CPER_SEV_NUM                   = 3,</div><div class='add'>+</div><div class='add'>+	CPER_SEV_UNUSED = 10,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum cper_aca_reg {</div><div class='add'>+	CPER_ACA_REG_CTL_LO    = 0,</div><div class='add'>+	CPER_ACA_REG_CTL_HI    = 1,</div><div class='add'>+	CPER_ACA_REG_STATUS_LO = 2,</div><div class='add'>+	CPER_ACA_REG_STATUS_HI = 3,</div><div class='add'>+	CPER_ACA_REG_ADDR_LO   = 4,</div><div class='add'>+	CPER_ACA_REG_ADDR_HI   = 5,</div><div class='add'>+	CPER_ACA_REG_MISC0_LO  = 6,</div><div class='add'>+	CPER_ACA_REG_MISC0_HI  = 7,</div><div class='add'>+	CPER_ACA_REG_CONFIG_LO = 8,</div><div class='add'>+	CPER_ACA_REG_CONFIG_HI = 9,</div><div class='add'>+	CPER_ACA_REG_IPID_LO   = 10,</div><div class='add'>+	CPER_ACA_REG_IPID_HI   = 11,</div><div class='add'>+	CPER_ACA_REG_SYND_LO   = 12,</div><div class='add'>+	CPER_ACA_REG_SYND_HI   = 13,</div><div class='add'>+</div><div class='add'>+	CPER_ACA_REG_COUNT     = 32,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#pragma pack(push, 1)</div><div class='add'>+</div><div class='add'>+struct cper_timestamp {</div><div class='add'>+	uint8_t seconds;</div><div class='add'>+	uint8_t minutes;</div><div class='add'>+	uint8_t hours;</div><div class='add'>+	uint8_t flag;</div><div class='add'>+	uint8_t day;</div><div class='add'>+	uint8_t month;</div><div class='add'>+	uint8_t year;</div><div class='add'>+	uint8_t century;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_hdr {</div><div class='add'>+	char                     signature[4];  /* "CPER"  */</div><div class='add'>+	uint16_t                 revision;</div><div class='add'>+	uint32_t                 signature_end; /* 0xFFFFFFFF */</div><div class='add'>+	uint16_t                 sec_cnt;</div><div class='add'>+	enum cper_error_severity error_severity;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t platform_id	: 1;</div><div class='add'>+			uint32_t timestamp	: 1;</div><div class='add'>+			uint32_t partition_id	: 1;</div><div class='add'>+			uint32_t reserved	: 29;</div><div class='add'>+		} valid_bits;</div><div class='add'>+		uint32_t valid_mask;</div><div class='add'>+	};</div><div class='add'>+	uint32_t		record_length;    /* Total size of CPER Entry */</div><div class='add'>+	struct cper_timestamp	timestamp;</div><div class='add'>+	char			platform_id[16];</div><div class='add'>+	guid_t			partition_id;     /* Reserved */</div><div class='add'>+	char			creator_id[16];</div><div class='add'>+	guid_t			notify_type;      /* CMC, MCE */</div><div class='add'>+	char			record_id[8];     /* Unique CPER Entry ID */</div><div class='add'>+	uint32_t		flags;            /* Reserved */</div><div class='add'>+	uint64_t		persistence_info; /* Reserved */</div><div class='add'>+	uint8_t			reserved[12];     /* Reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_desc {</div><div class='add'>+	uint32_t sec_offset;     /* Offset from the start of CPER entry */</div><div class='add'>+	uint32_t sec_length;</div><div class='add'>+	uint8_t  revision_minor; /* CPER_SEC_MINOR_REV_1 */</div><div class='add'>+	uint8_t  revision_major; /* CPER_SEC_MAJOR_REV_22 */</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint8_t fru_id		: 1;</div><div class='add'>+			uint8_t fru_text	: 1;</div><div class='add'>+			uint8_t reserved	: 6;</div><div class='add'>+		} valid_bits;</div><div class='add'>+		uint8_t valid_mask;</div><div class='add'>+	};</div><div class='add'>+	uint8_t reserved;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint32_t primary		: 1;</div><div class='add'>+			uint32_t reserved1		: 2;</div><div class='add'>+			uint32_t exceed_err_threshold	: 1;</div><div class='add'>+			uint32_t latent_err		: 1;</div><div class='add'>+			uint32_t reserved2		: 27;</div><div class='add'>+		} flag_bits;</div><div class='add'>+		uint32_t flag_mask;</div><div class='add'>+	};</div><div class='add'>+	guid_t				sec_type;</div><div class='add'>+	char				fru_id[16];</div><div class='add'>+	enum cper_error_severity	severity;</div><div class='add'>+	char				fru_text[20];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_nonstd_err_hdr {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint64_t apic_id		: 1;</div><div class='add'>+			uint64_t fw_id			: 1;</div><div class='add'>+			uint64_t err_info_cnt		: 6;</div><div class='add'>+			uint64_t err_context_cnt	: 6;</div><div class='add'>+		} valid_bits;</div><div class='add'>+		uint64_t valid_mask;</div><div class='add'>+	};</div><div class='add'>+	uint64_t apic_id;</div><div class='add'>+	char     fw_id[48];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_nonstd_err_info {</div><div class='add'>+	guid_t error_type;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint64_t ms_chk			: 1;</div><div class='add'>+			uint64_t target_addr_id		: 1;</div><div class='add'>+			uint64_t req_id			: 1;</div><div class='add'>+			uint64_t resp_id		: 1;</div><div class='add'>+			uint64_t instr_ptr		: 1;</div><div class='add'>+			uint64_t reserved		: 59;</div><div class='add'>+		} valid_bits;</div><div class='add'>+		uint64_t        valid_mask;</div><div class='add'>+	};</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			uint64_t err_type_valid		: 1;</div><div class='add'>+			uint64_t pcc_valid		: 1;</div><div class='add'>+			uint64_t uncorr_valid		: 1;</div><div class='add'>+			uint64_t precise_ip_valid	: 1;</div><div class='add'>+			uint64_t restartable_ip_valid	: 1;</div><div class='add'>+			uint64_t overflow_valid		: 1;</div><div class='add'>+			uint64_t reserved1		: 10;</div><div class='add'>+			uint64_t err_type		: 2;</div><div class='add'>+			uint64_t pcc			: 1;</div><div class='add'>+			uint64_t uncorr			: 1;</div><div class='add'>+			uint64_t precised_ip		: 1;</div><div class='add'>+			uint64_t restartable_ip		: 1;</div><div class='add'>+			uint64_t overflow		: 1;</div><div class='add'>+			uint64_t reserved2		: 41;</div><div class='add'>+		} ms_chk_bits;</div><div class='add'>+		uint64_t ms_chk_mask;</div><div class='add'>+	};</div><div class='add'>+	uint64_t target_addr_id;</div><div class='add'>+	uint64_t req_id;</div><div class='add'>+	uint64_t resp_id;</div><div class='add'>+	uint64_t instr_ptr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_nonstd_err_ctx {</div><div class='add'>+	uint16_t reg_ctx_type;</div><div class='add'>+	uint16_t reg_arr_size;</div><div class='add'>+	uint32_t msr_addr;</div><div class='add'>+	uint64_t mm_reg_addr;</div><div class='add'>+	uint32_t reg_dump[CPER_ACA_REG_COUNT];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_nonstd_err {</div><div class='add'>+	struct cper_sec_nonstd_err_hdr  hdr;</div><div class='add'>+	struct cper_sec_nonstd_err_info info;</div><div class='add'>+	struct cper_sec_nonstd_err_ctx  ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_crashdump_hdr {</div><div class='add'>+	uint64_t reserved1;</div><div class='add'>+	uint64_t reserved2;</div><div class='add'>+	char     fw_id[48];</div><div class='add'>+	uint64_t reserved3[8];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_crashdump_reg_data {</div><div class='add'>+	uint32_t status_lo;</div><div class='add'>+	uint32_t status_hi;</div><div class='add'>+	uint32_t addr_lo;</div><div class='add'>+	uint32_t addr_hi;</div><div class='add'>+	uint32_t ipid_lo;</div><div class='add'>+	uint32_t ipid_hi;</div><div class='add'>+	uint32_t synd_lo;</div><div class='add'>+	uint32_t synd_hi;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_crashdump_body_fatal {</div><div class='add'>+	uint16_t                           reg_ctx_type;</div><div class='add'>+	uint16_t                           reg_arr_size;</div><div class='add'>+	uint32_t                           reserved1;</div><div class='add'>+	uint64_t                           reserved2;</div><div class='add'>+	struct cper_sec_crashdump_reg_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_crashdump_body_boot {</div><div class='add'>+	uint16_t reg_ctx_type;</div><div class='add'>+	uint16_t reg_arr_size;</div><div class='add'>+	uint32_t reserved1;</div><div class='add'>+	uint64_t reserved2;</div><div class='add'>+	uint64_t msg[CPER_MAX_OAM_COUNT];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_crashdump_fatal {</div><div class='add'>+	struct cper_sec_crashdump_hdr        hdr;</div><div class='add'>+	struct cper_sec_crashdump_body_fatal body;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cper_sec_crashdump_boot {</div><div class='add'>+	struct cper_sec_crashdump_hdr       hdr;</div><div class='add'>+	struct cper_sec_crashdump_body_boot body;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#pragma pack(pop)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/amd_pcie.h b/drivers/gpu/drm/amd/include/amd_pcie.h<br/>index a1ece3eecdf5..a08611cb8041 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_pcie.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_pcie.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_pcie.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/amd_pcie.h</a></div><div class='hunk'>@@ -49,6 +49,17 @@</div><div class='ctx'> 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)</div><div class='ctx'> </div><div class='ctx'> /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */</div><div class='add'>+</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1          0x00000001</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2          0x00000002</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4          0x00000004</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8          0x00000008</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12         0x00000010</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16         0x00000020</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32         0x00000040</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_MASK        0x0000FFFF</div><div class='add'>+#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_SHIFT       0</div><div class='add'>+</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000</div><div class='hunk'>@@ -56,6 +67,7 @@</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000</div><div class='add'>+#define CAIL_PCIE_LINK_WIDTH_SUPPORT_MASK        0xFFFF0000</div><div class='ctx'> #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16</div><div class='ctx'> </div><div class='ctx'> /* 1/2/4/8/16 lanes */</div><div class='hunk'>@@ -65,4 +77,10 @@</div><div class='ctx'> 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \</div><div class='ctx'> 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)</div><div class='ctx'> </div><div class='add'>+#define AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 \</div><div class='add'>+					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 \</div><div class='add'>+					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 \</div><div class='add'>+					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 \</div><div class='add'>+					   | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16)</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h<br/>index b0a6256e89f4..17945094a138 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_shared.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/amd_shared.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/amd_shared.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/amd_shared.h</a></div><div class='hunk'>@@ -24,9 +24,12 @@</div><div class='ctx'> #define __AMD_SHARED_H__</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/amd_asic_type.h&gt;</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> #define AMD_MAX_USEC_TIMEOUT		1000000  /* 1000 ms */</div><div class='add'>+struct amdgpu_ip_block;</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Chip flags</div><div class='hunk'>@@ -60,7 +63,7 @@ enum amd_apu_flags {</div><div class='ctx'> * acquires the list of IP blocks for the GPU in use on initialization.</div><div class='ctx'> * It can then operate on this list to perform standard driver operations</div><div class='ctx'> * such as: init, fini, suspend, resume, etc.</div><div class='del'>-* </div><div class='add'>+*</div><div class='ctx'> *</div><div class='ctx'> * IP block implementations are named using the following convention:</div><div class='ctx'> * &lt;functionality&gt;_v&lt;version&gt; (E.g.: gfx_v6_0).</div><div class='hunk'>@@ -84,7 +87,8 @@ enum amd_apu_flags {</div><div class='ctx'> * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler</div><div class='ctx'> * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine</div><div class='ctx'> * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine</div><div class='del'>-* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia</div><div class='add'>+* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia</div><div class='add'>+* @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor</div><div class='ctx'> * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types</div><div class='ctx'> */</div><div class='ctx'> enum amd_ip_block_type {</div><div class='hunk'>@@ -104,6 +108,8 @@ enum amd_ip_block_type {</div><div class='ctx'> 	AMD_IP_BLOCK_TYPE_JPEG,</div><div class='ctx'> 	AMD_IP_BLOCK_TYPE_VPE,</div><div class='ctx'> 	AMD_IP_BLOCK_TYPE_UMSCH_MM,</div><div class='add'>+	AMD_IP_BLOCK_TYPE_ISP,</div><div class='add'>+	AMD_IP_BLOCK_TYPE_RAS,</div><div class='ctx'> 	AMD_IP_BLOCK_TYPE_NUM,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -234,33 +240,177 @@ enum amd_harvest_ip_mask {</div><div class='ctx'>     AMD_HARVEST_IP_DMU_MASK = 0x4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * enum DC_FEATURE_MASK - Bits that control DC feature defaults</div><div class='add'>+ */</div><div class='ctx'> enum DC_FEATURE_MASK {</div><div class='ctx'> 	//Default value can be found at "uint amdgpu_dc_feature_mask"</div><div class='del'>-	DC_FBC_MASK = (1 &lt;&lt; 0), //0x1, disabled by default</div><div class='del'>-	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 &lt;&lt; 1), //0x2, enabled by default</div><div class='del'>-	DC_DISABLE_FRACTIONAL_PWM_MASK = (1 &lt;&lt; 2), //0x4, disabled by default</div><div class='del'>-	DC_PSR_MASK = (1 &lt;&lt; 3), //0x8, disabled by default for dcn &lt; 3.1</div><div class='del'>-	DC_EDP_NO_POWER_SEQUENCING = (1 &lt;&lt; 4), //0x10, disabled by default</div><div class='del'>-	DC_DISABLE_LTTPR_DP1_4A = (1 &lt;&lt; 5), //0x20, disabled by default</div><div class='del'>-	DC_DISABLE_LTTPR_DP2_0 = (1 &lt;&lt; 6), //0x40, disabled by default</div><div class='del'>-	DC_PSR_ALLOW_SMU_OPT = (1 &lt;&lt; 7), //0x80, disabled by default</div><div class='del'>-	DC_PSR_ALLOW_MULTI_DISP_OPT = (1 &lt;&lt; 8), //0x100, disabled by default</div><div class='del'>-	DC_REPLAY_MASK = (1 &lt;&lt; 9), //0x200, disabled by default for dcn &lt; 3.1.4</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_FBC_MASK: (0x1) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_FBC_MASK = (1 &lt;&lt; 0),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_MULTI_MON_PP_MCLK_SWITCH_MASK: (0x2) enabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 &lt;&lt; 1),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_FRACTIONAL_PWM_MASK: (0x4) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_FRACTIONAL_PWM_MASK = (1 &lt;&lt; 2),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_PSR_MASK: (0x8) disabled by default for DCN &lt; 3.1</div><div class='add'>+	 */</div><div class='add'>+	DC_PSR_MASK = (1 &lt;&lt; 3),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_EDP_NO_POWER_SEQUENCING: (0x10) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_EDP_NO_POWER_SEQUENCING = (1 &lt;&lt; 4),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_LTTPR_DP1_4A: (0x20) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_LTTPR_DP1_4A = (1 &lt;&lt; 5),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_LTTPR_DP2_0: (0x40) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_LTTPR_DP2_0 = (1 &lt;&lt; 6),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_PSR_ALLOW_SMU_OPT: (0x80) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_PSR_ALLOW_SMU_OPT = (1 &lt;&lt; 7),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_PSR_ALLOW_MULTI_DISP_OPT: (0x100) disabled by default</div><div class='add'>+	 */</div><div class='add'>+	DC_PSR_ALLOW_MULTI_DISP_OPT = (1 &lt;&lt; 8),</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_REPLAY_MASK: (0x200) disabled by default for DCN &lt; 3.1.4</div><div class='add'>+	 */</div><div class='add'>+	DC_REPLAY_MASK = (1 &lt;&lt; 9),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP</div><div class='add'>+ */</div><div class='ctx'> enum DC_DEBUG_MASK {</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_PIPE_SPLIT: (0x1) If set, disable pipe-splitting</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_PIPE_SPLIT = 0x1,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_STUTTER: (0x2) If set, disable memory stutter mode</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_STUTTER = 0x2,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_DSC: (0x4) If set, disable display stream compression</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_DSC = 0x4,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_CLOCK_GATING: (0x8) If set, disable clock gating optimizations</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_CLOCK_GATING = 0x8,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_PSR: (0x10) If set, disable Panel self refresh v1 and PSR-SU</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_PSR = 0x10,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_FORCE_SUBVP_MCLK_SWITCH: (0x20) If set, force mclk switch in subvp, even</div><div class='add'>+	 * if mclk switch in vblank is possible</div><div class='add'>+	 */</div><div class='ctx'> 	DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_MPO: (0x40) If set, disable multi-plane offloading</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_MPO = 0x40,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_ENABLE_DPIA_TRACE: (0x80) If set, enable trace logging for DPIA</div><div class='add'>+	 */</div><div class='ctx'> 	DC_ENABLE_DPIA_TRACE = 0x80,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_ENABLE_DML2: (0x100) If set, force usage of DML2, even if the DCN version</div><div class='add'>+	 * does not default to it.</div><div class='add'>+	 */</div><div class='ctx'> 	DC_ENABLE_DML2 = 0x100,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_PSR_SU: (0x200) If set, disable PSR SU</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_PSR_SU = 0x200,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_REPLAY: (0x400) If set, disable Panel Replay</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_REPLAY = 0x400,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_IPS: (0x800) If set, disable all Idle Power States, all the time.</div><div class='add'>+	 * If more than one IPS debug bit is set, the lowest bit takes</div><div class='add'>+	 * precedence. For example, if DC_FORCE_IPS_ENABLE and</div><div class='add'>+	 * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes</div><div class='add'>+	 * precedence.</div><div class='add'>+	 */</div><div class='ctx'> 	DC_DISABLE_IPS = 0x800,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_IPS_DYNAMIC: (0x1000) If set, disable all IPS, all the time,</div><div class='add'>+	 * *except* when driver goes into suspend.</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_IPS_DYNAMIC = 0x1000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_IPS2_DYNAMIC: (0x2000) If set, disable IPS2 (IPS1 allowed) if</div><div class='add'>+	 * there is an enabled display. Otherwise, enable all IPS.</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_IPS2_DYNAMIC = 0x2000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_FORCE_IPS_ENABLE: (0x4000) If set, force enable all IPS, all the time.</div><div class='add'>+	 */</div><div class='add'>+	DC_FORCE_IPS_ENABLE = 0x4000,</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_ACPI_EDID: (0x8000) If set, don't attempt to fetch EDID for</div><div class='add'>+	 * eDP display from ACPI _DDC method.</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_ACPI_EDID = 0x8000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_HDMI_CEC: (0x10000) If set, disable HDMI-CEC feature in amdgpu driver.</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_HDMI_CEC = 0x10000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_SUBVP_FAMS: (0x20000) If set, disable DCN Sub-Viewport &amp; Firmware Assisted</div><div class='add'>+	 * Memory Clock Switching (FAMS) feature in amdgpu driver.</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_SUBVP_FAMS = 0x20000,</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE: (0x40000) If set, disable support for custom</div><div class='add'>+	 * brightness curves</div><div class='add'>+	 */</div><div class='add'>+	DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE = 0x40000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_HDCP_LC_FORCE_FW_ENABLE: (0x80000) If set, use HDCP Locality Check FW</div><div class='add'>+	 * path regardless of reported HW capabilities.</div><div class='add'>+	 */</div><div class='add'>+	DC_HDCP_LC_FORCE_FW_ENABLE = 0x80000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_HDCP_LC_ENABLE_SW_FALLBACK: (0x100000) If set, upon HDCP Locality Check FW</div><div class='add'>+	 * path failure, retry using legacy SW path.</div><div class='add'>+	 */</div><div class='add'>+	DC_HDCP_LC_ENABLE_SW_FALLBACK = 0x100000,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @DC_SKIP_DETECTION_LT: (0x200000) If set, skip detection link training</div><div class='add'>+	 */</div><div class='add'>+	DC_SKIP_DETECTION_LT = 0x200000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum amd_dpm_forced_level;</div><div class='hunk'>@@ -281,6 +431,7 @@ enum amd_dpm_forced_level;</div><div class='ctx'>  *                   (such as allocating any required memory)</div><div class='ctx'>  * @suspend: handles IP specific hw/sw changes for suspend</div><div class='ctx'>  * @resume: handles IP specific hw/sw changes for resume</div><div class='add'>+ * @complete: handles IP specific changes after resume</div><div class='ctx'>  * @is_idle: returns current IP block idle status</div><div class='ctx'>  * @wait_for_idle: poll for idle</div><div class='ctx'>  * @check_soft_reset: check soft reset the IP block</div><div class='hunk'>@@ -290,6 +441,8 @@ enum amd_dpm_forced_level;</div><div class='ctx'>  * @set_clockgating_state: enable/disable cg for the IP block</div><div class='ctx'>  * @set_powergating_state: enable/disable pg for the IP block</div><div class='ctx'>  * @get_clockgating_state: get current clockgating status</div><div class='add'>+ * @dump_ip_state: dump the IP state of the ASIC during a gpu hang</div><div class='add'>+ * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC</div><div class='ctx'>  *</div><div class='ctx'>  * These hooks provide an interface for controlling the operational state</div><div class='ctx'>  * of IP blocks. After acquiring a list of IP blocks for the GPU in use,</div><div class='hunk'>@@ -299,28 +452,31 @@ enum amd_dpm_forced_level;</div><div class='ctx'>  */</div><div class='ctx'> struct amd_ip_funcs {</div><div class='ctx'> 	char *name;</div><div class='del'>-	int (*early_init)(void *handle);</div><div class='del'>-	int (*late_init)(void *handle);</div><div class='del'>-	int (*sw_init)(void *handle);</div><div class='del'>-	int (*sw_fini)(void *handle);</div><div class='del'>-	int (*early_fini)(void *handle);</div><div class='del'>-	int (*hw_init)(void *handle);</div><div class='del'>-	int (*hw_fini)(void *handle);</div><div class='del'>-	void (*late_fini)(void *handle);</div><div class='del'>-	int (*prepare_suspend)(void *handle);</div><div class='del'>-	int (*suspend)(void *handle);</div><div class='del'>-	int (*resume)(void *handle);</div><div class='del'>-	bool (*is_idle)(void *handle);</div><div class='del'>-	int (*wait_for_idle)(void *handle);</div><div class='del'>-	bool (*check_soft_reset)(void *handle);</div><div class='del'>-	int (*pre_soft_reset)(void *handle);</div><div class='del'>-	int (*soft_reset)(void *handle);</div><div class='del'>-	int (*post_soft_reset)(void *handle);</div><div class='del'>-	int (*set_clockgating_state)(void *handle,</div><div class='add'>+	int (*early_init)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*late_init)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*sw_init)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*sw_fini)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*early_fini)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*hw_init)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*hw_fini)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	void (*late_fini)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*suspend)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*resume)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	void (*complete)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	bool (*is_idle)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*soft_reset)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_clockgating_state state);</div><div class='del'>-	int (*set_powergating_state)(void *handle,</div><div class='add'>+	int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,</div><div class='ctx'> 				     enum amd_powergating_state state);</div><div class='del'>-	void (*get_clockgating_state)(void *handle, u64 *flags);</div><div class='add'>+	void (*get_clockgating_state)(struct amdgpu_ip_block *ip_block, u64 *flags);</div><div class='add'>+	void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);</div><div class='add'>+	void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h<br/>index 9de01ae574c0..067eddd9c62d 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h</a></div><div class='hunk'>@@ -4115,6 +4115,7 @@</div><div class='ctx'> #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55</div><div class='ctx'> #define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40</div><div class='ctx'> #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41</div><div class='add'>+#define mmSCL0_SCL_SCALER_ENABLE 0x1B42</div><div class='ctx'> #define mmSCL0_SCL_CONTROL 0x1B44</div><div class='ctx'> #define mmSCL0_SCL_DEBUG 0x1B6A</div><div class='ctx'> #define mmSCL0_SCL_DEBUG2 0x1B69</div><div class='hunk'>@@ -4144,6 +4145,7 @@</div><div class='ctx'> #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55</div><div class='ctx'> #define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40</div><div class='ctx'> #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41</div><div class='add'>+#define mmSCL1_SCL_SCALER_ENABLE 0x1E42</div><div class='ctx'> #define mmSCL1_SCL_CONTROL 0x1E44</div><div class='ctx'> #define mmSCL1_SCL_DEBUG 0x1E6A</div><div class='ctx'> #define mmSCL1_SCL_DEBUG2 0x1E69</div><div class='hunk'>@@ -4173,6 +4175,7 @@</div><div class='ctx'> #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155</div><div class='ctx'> #define mmSCL2_SCL_COEF_RAM_SELECT 0x4140</div><div class='ctx'> #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141</div><div class='add'>+#define mmSCL2_SCL_SCALER_ENABLE 0x4142</div><div class='ctx'> #define mmSCL2_SCL_CONTROL 0x4144</div><div class='ctx'> #define mmSCL2_SCL_DEBUG 0x416A</div><div class='ctx'> #define mmSCL2_SCL_DEBUG2 0x4169</div><div class='hunk'>@@ -4202,6 +4205,7 @@</div><div class='ctx'> #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455</div><div class='ctx'> #define mmSCL3_SCL_COEF_RAM_SELECT 0x4440</div><div class='ctx'> #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441</div><div class='add'>+#define mmSCL3_SCL_SCALER_ENABLE 0x4442</div><div class='ctx'> #define mmSCL3_SCL_CONTROL 0x4444</div><div class='ctx'> #define mmSCL3_SCL_DEBUG 0x446A</div><div class='ctx'> #define mmSCL3_SCL_DEBUG2 0x4469</div><div class='hunk'>@@ -4231,6 +4235,7 @@</div><div class='ctx'> #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755</div><div class='ctx'> #define mmSCL4_SCL_COEF_RAM_SELECT 0x4740</div><div class='ctx'> #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741</div><div class='add'>+#define mmSCL4_SCL_SCALER_ENABLE 0x4742</div><div class='ctx'> #define mmSCL4_SCL_CONTROL 0x4744</div><div class='ctx'> #define mmSCL4_SCL_DEBUG 0x476A</div><div class='ctx'> #define mmSCL4_SCL_DEBUG2 0x4769</div><div class='hunk'>@@ -4260,6 +4265,7 @@</div><div class='ctx'> #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55</div><div class='ctx'> #define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40</div><div class='ctx'> #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41</div><div class='add'>+#define mmSCL5_SCL_SCALER_ENABLE 0x4A42</div><div class='ctx'> #define mmSCL5_SCL_CONTROL 0x4A44</div><div class='ctx'> #define mmSCL5_SCL_DEBUG 0x4A6A</div><div class='ctx'> #define mmSCL5_SCL_DEBUG2 0x4A69</div><div class='hunk'>@@ -4287,6 +4293,7 @@</div><div class='ctx'> #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55</div><div class='ctx'> #define mmSCL_COEF_RAM_SELECT 0x1B40</div><div class='ctx'> #define mmSCL_COEF_RAM_TAP_DATA 0x1B41</div><div class='add'>+#define mmSCL_SCALER_ENABLE 0x1B42</div><div class='ctx'> #define mmSCL_CONTROL 0x1B44</div><div class='ctx'> #define mmSCL_DEBUG 0x1B6A</div><div class='ctx'> #define mmSCL_DEBUG2 0x1B69</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h<br/>index bd8085ec54ed..9317a7afa621 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h</a></div><div class='hunk'>@@ -5242,6 +5242,8 @@</div><div class='ctx'> #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c</div><div class='ctx'> #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L</div><div class='ctx'> #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000</div><div class='add'>+#define DEGAMMA_CONTROL__ICON_DEGAMMA_MODE_MASK 0x00000300L</div><div class='add'>+#define DEGAMMA_CONTROL__ICON_DEGAMMA_MODE__SHIFT 0x00000008</div><div class='ctx'> #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L</div><div class='ctx'> #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004</div><div class='ctx'> #define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L</div><div class='hunk'>@@ -8648,6 +8650,8 @@</div><div class='ctx'> #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000</div><div class='ctx'> #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L</div><div class='ctx'> #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000</div><div class='add'>+#define SCL_SCALER_ENABLE__SCL_SCALE_EN_MASK 0x00000001L</div><div class='add'>+#define SCL_SCALER_ENABLE__SCL_SCALE_EN__SHIFT 0x00000000</div><div class='ctx'> #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L</div><div class='ctx'> #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000</div><div class='ctx'> #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h<br/>index cae1a7e74323..73c5dd5e83d4 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h</a></div><div class='hunk'>@@ -19,8 +19,8 @@</div><div class='ctx'>  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#ifndef _dcn_2_0_3_OFFSET_HEADER</div><div class='del'>-#define _dcn_2_0_3_OFFSET_HEADER</div><div class='add'>+#ifndef _dcn_2_0_1_OFFSET_HEADER</div><div class='add'>+#define _dcn_2_0_1_OFFSET_HEADER</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dccg_dccg_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_sh_mask.h<br/>index ca1e1eb39256..290d807800a6 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_sh_mask.h</a></div><div class='hunk'>@@ -18,8 +18,8 @@</div><div class='ctx'>  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN</div><div class='ctx'>  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  */</div><div class='del'>-#ifndef _dcn_2_0_3_SH_MASK_HEADER</div><div class='del'>-#define _dcn_2_0_3_SH_MASK_HEADER</div><div class='add'>+#ifndef _dcn_2_0_1_SH_MASK_HEADER</div><div class='add'>+#define _dcn_2_0_1_SH_MASK_HEADER</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dccg_dccg_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h<br/>index f2f8f9b39c6b..f32649047374 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h</a></div><div class='hunk'>@@ -311,6 +311,10 @@</div><div class='ctx'> #define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='ctx'> #define mmPHYFSYMCLK_CLOCK_CNTL                                                                        0x0057</div><div class='ctx'> #define mmPHYFSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define mmHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a</div><div class='add'>+#define mmHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dccg_dccg_dfs_dispdec</div><div class='hunk'>@@ -4513,6 +4517,10 @@</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -5201,6 +5209,10 @@</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -5888,6 +5900,10 @@</div><div class='ctx'> #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee</div><div class='ctx'> #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10ef</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10f0</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -6576,6 +6592,10 @@</div><div class='ctx'> #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259</div><div class='ctx'> #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x125a</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x125b</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -7264,6 +7284,10 @@</div><div class='ctx'> #define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM4_CM_3DLUT_OUT_OFFSET_B                                                                    0x13c4</div><div class='ctx'> #define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_INDEX                                                                      0x13c5</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_DATA                                                                       0x13c6</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -7952,6 +7976,10 @@</div><div class='ctx'> #define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM5_CM_3DLUT_OUT_OFFSET_B                                                                    0x152f</div><div class='ctx'> #define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM5_CM_TEST_DEBUG_INDEX                                                                      0x1530</div><div class='add'>+#define mmCM5_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM5_CM_TEST_DEBUG_DATA                                                                       0x1531</div><div class='add'>+#define mmCM5_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -12827,6 +12855,24 @@</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0                                                                 0x3036</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1                                                                 0x3037</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2                                                                 0x3038</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3                                                                 0x3039</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x303b</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA1                                                                  0x303c</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA2                                                                  0x303d</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA3                                                                  0x303e</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -12957,6 +13003,24 @@</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0                                                                 0x3092</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1                                                                 0x3093</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2                                                                 0x3094</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3                                                                 0x3095</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x3097</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA1                                                                  0x3098</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA2                                                                  0x3099</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA3                                                                  0x309a</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -13087,6 +13151,24 @@</div><div class='ctx'> #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed</div><div class='ctx'> #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0                                                                 0x30ee</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1                                                                 0x30ef</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2                                                                 0x30f0</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3                                                                 0x30f1</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA0                                                                  0x30f3</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA1                                                                  0x30f4</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA2                                                                  0x30f5</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA3                                                                  0x30f6</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -13217,6 +13299,24 @@</div><div class='ctx'> #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149</div><div class='ctx'> #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0                                                                 0x314a</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1                                                                 0x314b</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2                                                                 0x314c</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3                                                                 0x314d</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA0                                                                  0x314f</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA1                                                                  0x3150</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA2                                                                  0x3151</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA3                                                                  0x3152</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -13347,6 +13447,24 @@</div><div class='ctx'> #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x31a5</div><div class='ctx'> #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0                                                                 0x31a6</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1                                                                 0x31a7</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2                                                                 0x31a8</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3                                                                 0x31a9</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x31aa</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA0                                                                  0x31ab</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA1                                                                  0x31ac</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA2                                                                  0x31ad</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA3                                                                  0x31ae</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -13476,6 +13594,24 @@</div><div class='ctx'> #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3201</div><div class='ctx'> #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX0                                                                 0x3202</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX1                                                                 0x3203</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX2                                                                 0x3204</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX3                                                                 0x3205</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3206</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA0                                                                  0x3207</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA1                                                                  0x3208</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA2                                                                  0x3209</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA3                                                                  0x320a</div><div class='add'>+#define mmDSCC5_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h<br/>index e0a447351623..4005c73c2c9f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h</a></div><div class='hunk'>@@ -1189,6 +1189,11 @@</div><div class='ctx'> #define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4</div><div class='ctx'> #define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_FORCE_EN_MASK                                                       0x00000001L</div><div class='ctx'> #define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L</div><div class='add'>+//HDMICHARCLK0_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dccg_dccg_dfs_dispdec</div><div class='hunk'>@@ -16739,6 +16744,15 @@</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='ctx'> //DC_PERFMON12_PERFCOUNTER_CNTL</div><div class='hunk'>@@ -18934,6 +18948,15 @@</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM1_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='ctx'> //DC_PERFMON13_PERFCOUNTER_CNTL</div><div class='hunk'>@@ -21128,6 +21151,15 @@</div><div class='ctx'> #define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM2_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM2_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='ctx'> //DC_PERFMON14_PERFCOUNTER_CNTL</div><div class='hunk'>@@ -23323,6 +23355,15 @@</div><div class='ctx'> #define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM3_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM3_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='ctx'> //DC_PERFMON15_PERFCOUNTER_CNTL</div><div class='hunk'>@@ -25517,6 +25558,15 @@</div><div class='ctx'> #define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM4_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM4_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='ctx'> //DC_PERFMON16_PERFCOUNTER_CNTL</div><div class='hunk'>@@ -27712,6 +27762,15 @@</div><div class='ctx'> #define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM5_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM5_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM5_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM5_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM5_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM5_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='ctx'> //DC_PERFMON17_PERFCOUNTER_CNTL</div><div class='hunk'>@@ -50276,7 +50335,9 @@</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='ctx'> //DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -50648,6 +50709,15 @@</div><div class='ctx'> //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h<br/>index b45a35aae241..b2962b5ce31e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h</a></div><div class='hunk'>@@ -4466,6 +4466,10 @@</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -5154,6 +5158,10 @@</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -5841,6 +5849,10 @@</div><div class='ctx'> #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee</div><div class='ctx'> #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10ef</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10f0</div><div class='add'>+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -6529,6 +6541,10 @@</div><div class='ctx'> #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259</div><div class='ctx'> #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x125a</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x125b</div><div class='add'>+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -7217,6 +7233,10 @@</div><div class='ctx'> #define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM4_CM_3DLUT_OUT_OFFSET_B                                                                    0x13c4</div><div class='ctx'> #define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_INDEX                                                                      0x13c5</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_DATA                                                                       0x13c6</div><div class='add'>+#define mmCM4_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -11671,6 +11691,24 @@</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0                                                                 0x3036</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1                                                                 0x3037</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2                                                                 0x3038</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3                                                                 0x3039</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x303b</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA1                                                                  0x303c</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA2                                                                  0x303d</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA3                                                                  0x303e</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -11801,6 +11839,24 @@</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0                                                                 0x3092</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1                                                                 0x3093</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2                                                                 0x3094</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3                                                                 0x3095</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x3097</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA1                                                                  0x3098</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA2                                                                  0x3099</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA3                                                                  0x309a</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -11931,6 +11987,24 @@</div><div class='ctx'> #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed</div><div class='ctx'> #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0                                                                 0x30ee</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1                                                                 0x30ef</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2                                                                 0x30f0</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3                                                                 0x30f1</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA0                                                                  0x30f3</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA1                                                                  0x30f4</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA2                                                                  0x30f5</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA3                                                                  0x30f6</div><div class='add'>+#define mmDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -12061,6 +12135,24 @@</div><div class='ctx'> #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149</div><div class='ctx'> #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0                                                                 0x314a</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1                                                                 0x314b</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2                                                                 0x314c</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3                                                                 0x314d</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA0                                                                  0x314f</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA1                                                                  0x3150</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA2                                                                  0x3151</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA3                                                                  0x3152</div><div class='add'>+#define mmDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -12191,6 +12283,24 @@</div><div class='ctx'> #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x31a5</div><div class='ctx'> #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0                                                                 0x31a6</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1                                                                 0x31a7</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2                                                                 0x31a8</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3                                                                 0x31a9</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x31aa</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA0                                                                  0x31ab</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA1                                                                  0x31ac</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA2                                                                  0x31ad</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA3                                                                  0x31ae</div><div class='add'>+#define mmDSCC4_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h<br/>index 3dae29f9581e..7f8f0a646422 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h</a></div><div class='hunk'>@@ -15676,6 +15676,14 @@</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -17876,6 +17884,14 @@</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM1_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -20076,6 +20092,14 @@</div><div class='ctx'> #define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM2_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM2_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -22276,6 +22300,14 @@</div><div class='ctx'> #define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM3_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM3_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -24476,6 +24508,14 @@</div><div class='ctx'> #define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM4_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM4_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM4_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM4_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM4_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -43642,7 +43682,9 @@</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='ctx'> //DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -44015,6 +44057,15 @@</div><div class='ctx'> //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -44165,6 +44216,7 @@</div><div class='ctx'> #define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='ctx'> //DSC_TOP1_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='ctx'> #define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h<br/>index daa8130636f0..a3373d1e1736 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h</a></div><div class='hunk'>@@ -3110,6 +3110,10 @@</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18</div><div class='ctx'> #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a</div><div class='add'>+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -3798,6 +3802,10 @@</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83</div><div class='ctx'> #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85</div><div class='add'>+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -5687,6 +5695,24 @@</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035</div><div class='ctx'> #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0                                                                 0x3036</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1                                                                 0x3037</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2                                                                 0x3038</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3                                                                 0x3039</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x303b</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA1                                                                  0x303c</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA2                                                                  0x303d</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA3                                                                  0x303e</div><div class='add'>+#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -5817,6 +5843,24 @@</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091</div><div class='ctx'> #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0                                                                 0x3092</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1                                                                 0x3093</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2                                                                 0x3094</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3                                                                 0x3095</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x3097</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA1                                                                  0x3098</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA2                                                                  0x3099</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA3                                                                  0x309a</div><div class='add'>+#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h<br/>index 5c469cf635e5..9549494b65b5 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h</a></div><div class='hunk'>@@ -10701,6 +10701,13 @@</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+</div><div class='ctx'> //CM0_CM_SHAPER_CONTROL</div><div class='ctx'> #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0</div><div class='ctx'> #define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2</div><div class='hunk'>@@ -11159,6 +11166,14 @@</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -13359,6 +13374,14 @@</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL</div><div class='ctx'> #define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L</div><div class='add'>+//CM1_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='hunk'>@@ -22258,7 +22281,9 @@</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='ctx'> //DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -22631,6 +22656,15 @@</div><div class='ctx'> //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h<br/>index f268d33c4744..7fd906f10803 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h</a></div><div class='hunk'>@@ -424,6 +424,8 @@</div><div class='ctx'> #define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2</div><div class='ctx'> #define regDTBCLK_DTO3_MODULO                                                                           0x0022</div><div class='ctx'> #define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='ctx'> #define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052</div><div class='ctx'> #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='ctx'> #define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053</div><div class='hunk'>@@ -434,6 +436,8 @@</div><div class='ctx'> #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='ctx'> #define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056</div><div class='ctx'> #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regHDMISTREAMCLK_CNTL                                                                           0x0059</div><div class='add'>+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2</div><div class='ctx'> #define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a</div><div class='ctx'> #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2</div><div class='ctx'> #define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h<br/>index cf3398f15666..07fbfafe6056 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h</a></div><div class='hunk'>@@ -1372,6 +1372,11 @@</div><div class='ctx'> //DTBCLK_DTO3_MODULO</div><div class='ctx'> #define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0</div><div class='ctx'> #define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//HDMICHARCLK0_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L</div><div class='ctx'> //PHYASYMCLK_CLOCK_CNTL</div><div class='ctx'> #define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0</div><div class='ctx'> #define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4</div><div class='hunk'>@@ -1397,6 +1402,13 @@</div><div class='ctx'> #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4</div><div class='ctx'> #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L</div><div class='ctx'> #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L</div><div class='add'>+//HDMISTREAMCLK_CNTL</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT                                               0x4</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK                                                 0x00000010L</div><div class='ctx'> //DCCG_GATE_DISABLE_CNTL3</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1</div><div class='hunk'>@@ -46978,6 +46990,13 @@</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+//DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='ctx'> //DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h<br/>index 50c34d88c17c..16a69d17bb1e 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h</a></div><div class='hunk'>@@ -213,6 +213,8 @@</div><div class='ctx'> #define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2</div><div class='ctx'> #define regDTBCLK_DTO3_MODULO                                                                           0x0022</div><div class='ctx'> #define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='ctx'> #define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052</div><div class='ctx'> #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='ctx'> #define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053</div><div class='hunk'>@@ -233,6 +235,8 @@</div><div class='ctx'> #define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2</div><div class='ctx'> #define regDTBCLK_DTO_DBUF_EN                                                                           0x0063</div><div class='ctx'> #define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regHDMISTREAMCLK_CNTL                                                                           0x0059</div><div class='add'>+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h<br/>index 295e0dac9ffa..6473362e39a8 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h</a></div><div class='hunk'>@@ -886,6 +886,11 @@</div><div class='ctx'> //DTBCLK_DTO3_MODULO</div><div class='ctx'> #define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0</div><div class='ctx'> #define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//HDMICHARCLK0_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L</div><div class='ctx'> //PHYASYMCLK_CLOCK_CNTL</div><div class='ctx'> #define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0</div><div class='ctx'> #define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4</div><div class='hunk'>@@ -911,6 +916,11 @@</div><div class='ctx'> #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4</div><div class='ctx'> #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L</div><div class='ctx'> #define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L</div><div class='add'>+//HDMISTREAMCLK_CNTL</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS__SHIFT                                               0x10</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000003L</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_DTO_FORCE_DIS_MASK                                                 0x00010000L</div><div class='ctx'> //DCCG_GATE_DISABLE_CNTL3</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h<br/>index 14c29ce4c7b3..78cb61d5800a 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h</a></div><div class='hunk'>@@ -1719,6 +1719,10 @@</div><div class='ctx'> #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2</div><div class='ctx'> #define regFMON_CTRL                                                                                    0x0541</div><div class='ctx'> #define regFMON_CTRL_BASE_IDX                                                                           2</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x0542</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x0543</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dchubbubl_hubbub_sdpif_dispdec</div><div class='hunk'>@@ -3574,6 +3578,10 @@</div><div class='ctx'> #define regCM0_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM0_CM_COEF_FORMAT                                                                           0x0d8c</div><div class='ctx'> #define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0d8d</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0d8e</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -3960,6 +3968,10 @@</div><div class='ctx'> #define regCM1_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM1_CM_COEF_FORMAT                                                                           0x0ef7</div><div class='ctx'> #define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0ef8</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0ef9</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -4346,6 +4358,10 @@</div><div class='ctx'> #define regCM2_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM2_CM_COEF_FORMAT                                                                           0x1062</div><div class='ctx'> #define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x1063</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x1064</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -4732,6 +4748,10 @@</div><div class='ctx'> #define regCM3_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM3_CM_COEF_FORMAT                                                                           0x11cd</div><div class='ctx'> #define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x11ce</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x11cf</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -11780,6 +11800,16 @@</div><div class='ctx'> #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035</div><div class='ctx'> #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x303b</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA1                                                                  0x303c</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA2                                                                  0x303d</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA3                                                                  0x303e</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -11888,6 +11918,16 @@</div><div class='ctx'> #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091</div><div class='ctx'> #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x3097</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA1                                                                  0x3098</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA2                                                                  0x3099</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA3                                                                  0x309a</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dsc1_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -11996,6 +12036,16 @@</div><div class='ctx'> #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed</div><div class='ctx'> #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA0                                                                  0x30f3</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA1                                                                  0x30f4</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA2                                                                  0x30f5</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA3                                                                  0x30f6</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dsc2_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -12104,6 +12154,16 @@</div><div class='ctx'> #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149</div><div class='ctx'> #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA0                                                                  0x314f</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA1                                                                  0x3150</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA2                                                                  0x3151</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA3                                                                  0x3152</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dsc3_dispdec_dsccif_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h<br/>index 0691e328d0f0..c20bf730dc55 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h</a></div><div class='hunk'>@@ -11544,6 +11544,14 @@</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp0_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -12678,6 +12686,14 @@</div><div class='ctx'> #define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='ctx'> #define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='ctx'> #define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp1_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -13812,6 +13828,14 @@</div><div class='ctx'> #define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='ctx'> #define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='ctx'> #define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM2_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM2_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp2_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -14946,6 +14970,14 @@</div><div class='ctx'> #define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='ctx'> #define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='ctx'> #define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM3_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM3_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dpp3_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -42267,6 +42299,18 @@</div><div class='ctx'> //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_INDEX2</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT                                           0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK                                             0x000000FFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -42300,7 +42344,18 @@</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='ctx'> //DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+//DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+//DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dcn_dc_dsc1_dispdec_dscc_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h<br/>index 3bd8792fd7b3..a04b8c32c564 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h</a></div><div class='hunk'>@@ -1719,6 +1719,10 @@</div><div class='ctx'> #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2</div><div class='ctx'> #define regFMON_CTRL                                                                                    0x0541</div><div class='ctx'> #define regFMON_CTRL_BASE_IDX                                                                           2</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x0542</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x0543</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec</div><div class='hunk'>@@ -3573,6 +3577,10 @@</div><div class='ctx'> #define regCM0_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM0_CM_COEF_FORMAT                                                                           0x0d8c</div><div class='ctx'> #define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0d8d</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0d8e</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -3959,6 +3967,10 @@</div><div class='ctx'> #define regCM1_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM1_CM_COEF_FORMAT                                                                           0x0ef7</div><div class='ctx'> #define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0ef8</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0ef9</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -4345,6 +4357,10 @@</div><div class='ctx'> #define regCM2_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM2_CM_COEF_FORMAT                                                                           0x1062</div><div class='ctx'> #define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x1063</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x1064</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -4731,6 +4747,10 @@</div><div class='ctx'> #define regCM3_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='ctx'> #define regCM3_CM_COEF_FORMAT                                                                           0x11cd</div><div class='ctx'> #define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x11ce</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x11cf</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -11789,6 +11809,10 @@</div><div class='ctx'> #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035</div><div class='ctx'> #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x303b</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -11897,6 +11921,10 @@</div><div class='ctx'> #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091</div><div class='ctx'> #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x3097</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -12005,7 +12033,10 @@</div><div class='ctx'> #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed</div><div class='ctx'> #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='del'>-</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA0                                                                  0x30f3</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec</div><div class='ctx'> // base address: 0x2e0</div><div class='hunk'>@@ -12113,6 +12144,10 @@</div><div class='ctx'> #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='ctx'> #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149</div><div class='ctx'> #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA0                                                                  0x314f</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h<br/>index e82dffc2b9b0..ce773fca621f 100644<br/>--- a/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h?id=1e0fb113646182e073539db96016b00cfeb18ecc'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h</a></div><div class='hunk'>@@ -11547,6 +11547,11 @@</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='ctx'> #define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec</div><div class='hunk'>@@ -42315,6 +42320,15 @@</div><div class='ctx'> //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='ctx'> #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='hunk'>@@ -42348,7 +42362,9 @@</div><div class='ctx'> #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='ctx'> //DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='ctx'> #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h<br/>new file mode 100644<br/>index 000000000000..b070f9b91f17<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_offset.h</a></div><div class='hunk'>@@ -0,0 +1,15485 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifndef _dcn_3_6_0_OFFSET_HEADER</div><div class='add'>+#define _dcn_3_6_0_OFFSET_HEADER</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azcontroller_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regGLOBAL_CAPABILITIES                                                                          0x4b7000</div><div class='add'>+#define regGLOBAL_CAPABILITIES_BASE_IDX                                                                 3</div><div class='add'>+#define regMINOR_VERSION                                                                                0x4b7000</div><div class='add'>+#define regMINOR_VERSION_BASE_IDX                                                                       3</div><div class='add'>+#define regMAJOR_VERSION                                                                                0x4b7000</div><div class='add'>+#define regMAJOR_VERSION_BASE_IDX                                                                       3</div><div class='add'>+#define regOUTPUT_PAYLOAD_CAPABILITY                                                                    0x4b7001</div><div class='add'>+#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                           3</div><div class='add'>+#define regINPUT_PAYLOAD_CAPABILITY                                                                     0x4b7001</div><div class='add'>+#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                            3</div><div class='add'>+#define regGLOBAL_CONTROL                                                                               0x4b7002</div><div class='add'>+#define regGLOBAL_CONTROL_BASE_IDX                                                                      3</div><div class='add'>+#define regWAKE_ENABLE                                                                                  0x4b7003</div><div class='add'>+#define regWAKE_ENABLE_BASE_IDX                                                                         3</div><div class='add'>+#define regSTATE_CHANGE_STATUS                                                                          0x4b7003</div><div class='add'>+#define regSTATE_CHANGE_STATUS_BASE_IDX                                                                 3</div><div class='add'>+#define regGLOBAL_STATUS                                                                                0x4b7004</div><div class='add'>+#define regGLOBAL_STATUS_BASE_IDX                                                                       3</div><div class='add'>+#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY                                                             0x4b7006</div><div class='add'>+#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                    3</div><div class='add'>+#define regINPUT_STREAM_PAYLOAD_CAPABILITY                                                              0x4b7006</div><div class='add'>+#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                     3</div><div class='add'>+#define regINTERRUPT_CONTROL                                                                            0x4b7008</div><div class='add'>+#define regINTERRUPT_CONTROL_BASE_IDX                                                                   3</div><div class='add'>+#define regINTERRUPT_STATUS                                                                             0x4b7009</div><div class='add'>+#define regINTERRUPT_STATUS_BASE_IDX                                                                    3</div><div class='add'>+#define regWALL_CLOCK_COUNTER                                                                           0x4b700c</div><div class='add'>+#define regWALL_CLOCK_COUNTER_BASE_IDX                                                                  3</div><div class='add'>+#define regSTREAM_SYNCHRONIZATION                                                                       0x4b700e</div><div class='add'>+#define regSTREAM_SYNCHRONIZATION_BASE_IDX                                                              3</div><div class='add'>+#define regCORB_LOWER_BASE_ADDRESS                                                                      0x4b7010</div><div class='add'>+#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX                                                             3</div><div class='add'>+#define regCORB_UPPER_BASE_ADDRESS                                                                      0x4b7011</div><div class='add'>+#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX                                                             3</div><div class='add'>+#define regAZCONTROLLER0_CORB_WRITE_POINTER                                                             0x4b7012</div><div class='add'>+#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX                                                    3</div><div class='add'>+#define regAZCONTROLLER0_CORB_READ_POINTER                                                              0x4b7012</div><div class='add'>+#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX                                                     3</div><div class='add'>+#define regAZCONTROLLER0_CORB_CONTROL                                                                   0x4b7013</div><div class='add'>+#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regAZCONTROLLER0_CORB_STATUS                                                                    0x4b7013</div><div class='add'>+#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX                                                           3</div><div class='add'>+#define regAZCONTROLLER0_CORB_SIZE                                                                      0x4b7013</div><div class='add'>+#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX                                                             3</div><div class='add'>+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS                                                        0x4b7014</div><div class='add'>+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               3</div><div class='add'>+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS                                                        0x4b7015</div><div class='add'>+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               3</div><div class='add'>+#define regAZCONTROLLER0_RIRB_WRITE_POINTER                                                             0x4b7016</div><div class='add'>+#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX                                                    3</div><div class='add'>+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT                                                       0x4b7016</div><div class='add'>+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              3</div><div class='add'>+#define regAZCONTROLLER0_RIRB_CONTROL                                                                   0x4b7017</div><div class='add'>+#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regAZCONTROLLER0_RIRB_STATUS                                                                    0x4b7017</div><div class='add'>+#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX                                                           3</div><div class='add'>+#define regAZCONTROLLER0_RIRB_SIZE                                                                      0x4b7017</div><div class='add'>+#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX                                                             3</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x4b7018</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    3</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x4b7018</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               3</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x4b7018</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              3</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x4b7019</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    3</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS                                                       0x4b701a</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              3</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x4b701c</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       3</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x4b701d</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       3</div><div class='add'>+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS                                                       0x4b780c</div><div class='add'>+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azendpoint_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x4b7018</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      3</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x4b7018</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azinputendpoint_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x4b7018</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  3</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x4b7018</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azcontroller_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZCONTROLLER1_CORB_WRITE_POINTER                                                             0x0000</div><div class='add'>+#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX                                                    0</div><div class='add'>+#define regAZCONTROLLER1_CORB_READ_POINTER                                                              0x0000</div><div class='add'>+#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX                                                     0</div><div class='add'>+#define regAZCONTROLLER1_CORB_CONTROL                                                                   0x0001</div><div class='add'>+#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX                                                          0</div><div class='add'>+#define regAZCONTROLLER1_CORB_STATUS                                                                    0x0001</div><div class='add'>+#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX                                                           0</div><div class='add'>+#define regAZCONTROLLER1_CORB_SIZE                                                                      0x0001</div><div class='add'>+#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX                                                             0</div><div class='add'>+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS                                                        0x0002</div><div class='add'>+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               0</div><div class='add'>+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS                                                        0x0003</div><div class='add'>+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               0</div><div class='add'>+#define regAZCONTROLLER1_RIRB_WRITE_POINTER                                                             0x0004</div><div class='add'>+#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX                                                    0</div><div class='add'>+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT                                                       0x0004</div><div class='add'>+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              0</div><div class='add'>+#define regAZCONTROLLER1_RIRB_CONTROL                                                                   0x0005</div><div class='add'>+#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX                                                          0</div><div class='add'>+#define regAZCONTROLLER1_RIRB_STATUS                                                                    0x0005</div><div class='add'>+#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX                                                           0</div><div class='add'>+#define regAZCONTROLLER1_RIRB_SIZE                                                                      0x0005</div><div class='add'>+#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX                                                             0</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x0006</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    0</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x0006</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               0</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x0006</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              0</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x0007</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    0</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS                                                       0x0008</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              0</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x000a</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       0</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x000b</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       0</div><div class='add'>+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS                                                       0x074c</div><div class='add'>+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azendpoint_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x0006</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      0</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x0006</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azinputendpoint_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x0006</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  0</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x0006</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040</div><div class='add'>+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041</div><div class='add'>+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042</div><div class='add'>+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043</div><div class='add'>+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regDP_DTO_DBUF_EN                                                                               0x0044</div><div class='add'>+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1</div><div class='add'>+#define regDSCCLK3_DTO_PARAM                                                                            0x0045</div><div class='add'>+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048</div><div class='add'>+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1</div><div class='add'>+#define regDPSTREAMCLK_CNTL                                                                             0x004a</div><div class='add'>+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1</div><div class='add'>+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b</div><div class='add'>+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c</div><div class='add'>+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regDCCG_PERFMON_CNTL2                                                                           0x004e</div><div class='add'>+#define regDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1</div><div class='add'>+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050</div><div class='add'>+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1</div><div class='add'>+#define regDCCG_DS_DTO_INCR                                                                             0x0053</div><div class='add'>+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1</div><div class='add'>+#define regDCCG_DS_DTO_MODULO                                                                           0x0054</div><div class='add'>+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1</div><div class='add'>+#define regDCCG_DS_CNTL                                                                                 0x0055</div><div class='add'>+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1</div><div class='add'>+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056</div><div class='add'>+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1</div><div class='add'>+#define regDPREFCLK_CNTL                                                                                0x0058</div><div class='add'>+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1</div><div class='add'>+#define regDCE_VERSION                                                                                  0x005e</div><div class='add'>+#define regDCE_VERSION_BASE_IDX                                                                         1</div><div class='add'>+#define regDCCG_GTC_CNTL                                                                                0x0060</div><div class='add'>+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1</div><div class='add'>+#define regDCCG_GTC_DTO_INCR                                                                            0x0061</div><div class='add'>+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1</div><div class='add'>+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062</div><div class='add'>+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1</div><div class='add'>+#define regDCCG_GTC_CURRENT                                                                             0x0063</div><div class='add'>+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1</div><div class='add'>+#define regSYMCLK32_SE_CNTL                                                                             0x0065</div><div class='add'>+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1</div><div class='add'>+#define regSYMCLK32_LE_CNTL                                                                             0x0066</div><div class='add'>+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1</div><div class='add'>+#define regDTBCLK_P_CNTL                                                                                0x0068</div><div class='add'>+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1</div><div class='add'>+#define regDSCCLK0_DTO_PARAM                                                                            0x006c</div><div class='add'>+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDSCCLK1_DTO_PARAM                                                                            0x006d</div><div class='add'>+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDSCCLK2_DTO_PARAM                                                                            0x006e</div><div class='add'>+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f</div><div class='add'>+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1</div><div class='add'>+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070</div><div class='add'>+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1</div><div class='add'>+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071</div><div class='add'>+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1</div><div class='add'>+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072</div><div class='add'>+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regDCCG_PERFMON_CNTL                                                                            0x0073</div><div class='add'>+#define regDCCG_PERFMON_CNTL_BASE_IDX                                                                   1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1</div><div class='add'>+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075</div><div class='add'>+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1</div><div class='add'>+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076</div><div class='add'>+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regDCCG_CAC_STATUS                                                                              0x0077</div><div class='add'>+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1</div><div class='add'>+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b</div><div class='add'>+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1</div><div class='add'>+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d</div><div class='add'>+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regDCCG_DISP_CNTL_REG                                                                           0x007f</div><div class='add'>+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1</div><div class='add'>+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080</div><div class='add'>+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO0_PHASE                                                                                0x0081</div><div class='add'>+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO0_MODULO                                                                               0x0082</div><div class='add'>+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083</div><div class='add'>+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084</div><div class='add'>+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO1_PHASE                                                                                0x0085</div><div class='add'>+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO1_MODULO                                                                               0x0086</div><div class='add'>+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087</div><div class='add'>+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088</div><div class='add'>+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO2_PHASE                                                                                0x0089</div><div class='add'>+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO2_MODULO                                                                               0x008a</div><div class='add'>+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b</div><div class='add'>+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c</div><div class='add'>+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO3_PHASE                                                                                0x008d</div><div class='add'>+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO3_MODULO                                                                               0x008e</div><div class='add'>+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f</div><div class='add'>+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098</div><div class='add'>+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regDPPCLK0_DTO_PARAM                                                                            0x0099</div><div class='add'>+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK1_DTO_PARAM                                                                            0x009a</div><div class='add'>+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK2_DTO_PARAM                                                                            0x009b</div><div class='add'>+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK3_DTO_PARAM                                                                            0x009c</div><div class='add'>+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDCCG_CAC_STATUS2                                                                             0x009f</div><div class='add'>+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1</div><div class='add'>+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0</div><div class='add'>+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1</div><div class='add'>+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2</div><div class='add'>+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3</div><div class='add'>+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4</div><div class='add'>+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regDCCG_SOFT_RESET                                                                              0x00a6</div><div class='add'>+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1</div><div class='add'>+#define regDSCCLK_DTO_CTRL                                                                              0x00a7</div><div class='add'>+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1</div><div class='add'>+#define regDPPCLK_CTRL                                                                                  0x00a8</div><div class='add'>+#define regDPPCLK_CTRL_BASE_IDX                                                                         1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL6                                                                      0x00a9</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX                                                             1</div><div class='add'>+#define regSYMCLK_PSP_CNTL                                                                              0x00aa</div><div class='add'>+#define regSYMCLK_PSP_CNTL_BASE_IDX                                                                     1</div><div class='add'>+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab</div><div class='add'>+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac</div><div class='add'>+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad</div><div class='add'>+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1</div><div class='add'>+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae</div><div class='add'>+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af</div><div class='add'>+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1</div><div class='add'>+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0</div><div class='add'>+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1</div><div class='add'>+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2</div><div class='add'>+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3</div><div class='add'>+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4</div><div class='add'>+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5</div><div class='add'>+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDPPCLK_DTO_CTRL                                                                              0x00b6</div><div class='add'>+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1</div><div class='add'>+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8</div><div class='add'>+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1</div><div class='add'>+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9</div><div class='add'>+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1</div><div class='add'>+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba</div><div class='add'>+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1</div><div class='add'>+#define regDTBCLK_DTO0_PHASE                                                                            0x0018</div><div class='add'>+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2</div><div class='add'>+#define regDTBCLK_DTO1_PHASE                                                                            0x0019</div><div class='add'>+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2</div><div class='add'>+#define regDTBCLK_DTO2_PHASE                                                                            0x001a</div><div class='add'>+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2</div><div class='add'>+#define regDTBCLK_DTO3_PHASE                                                                            0x001b</div><div class='add'>+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2</div><div class='add'>+#define regDTBCLK_DTO0_MODULO                                                                           0x001f</div><div class='add'>+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2</div><div class='add'>+#define regDTBCLK_DTO1_MODULO                                                                           0x0020</div><div class='add'>+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2</div><div class='add'>+#define regDTBCLK_DTO2_MODULO                                                                           0x0021</div><div class='add'>+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2</div><div class='add'>+#define regDTBCLK_DTO3_MODULO                                                                           0x0022</div><div class='add'>+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052</div><div class='add'>+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053</div><div class='add'>+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054</div><div class='add'>+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055</div><div class='add'>+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056</div><div class='add'>+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regHDMISTREAMCLK_CNTL                                                                           0x0059</div><div class='add'>+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2</div><div class='add'>+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b</div><div class='add'>+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2</div><div class='add'>+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061</div><div class='add'>+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2</div><div class='add'>+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062</div><div class='add'>+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2</div><div class='add'>+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063</div><div class='add'>+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000</div><div class='add'>+#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001</div><div class='add'>+#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002</div><div class='add'>+#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CNTL                                                                     0x0003</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006</div><div class='add'>+#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON0_PERFMON_HI                                                                       0x0007</div><div class='add'>+#define regDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON0_PERFMON_LOW                                                                      0x0008</div><div class='add'>+#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c</div><div class='add'>+#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d</div><div class='add'>+#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e</div><div class='add'>+#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CNTL                                                                     0x000f</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012</div><div class='add'>+#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON1_PERFMON_HI                                                                       0x0013</div><div class='add'>+#define regDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON1_PERFMON_LOW                                                                      0x0014</div><div class='add'>+#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_fgsec_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a</div><div class='add'>+#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_rbbmif_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regRBBMIF_TIMEOUT                                                                               0x017f</div><div class='add'>+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2</div><div class='add'>+#define regRBBMIF_STATUS                                                                                0x0180</div><div class='add'>+#define regRBBMIF_STATUS_BASE_IDX                                                                       2</div><div class='add'>+#define regRBBMIF_STATUS_2                                                                              0x0181</div><div class='add'>+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2</div><div class='add'>+#define regRBBMIF_INT_STATUS                                                                            0x0182</div><div class='add'>+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2</div><div class='add'>+#define regRBBMIF_STATUS_FLAG                                                                           0x0185</div><div class='add'>+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x2f8</div><div class='add'>+#define regDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be</div><div class='add'>+#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf</div><div class='add'>+#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0</div><div class='add'>+#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4</div><div class='add'>+#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_HI                                                                       0x00c5</div><div class='add'>+#define regDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON2_PERFMON_LOW                                                                      0x00c6</div><div class='add'>+#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_ihc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2</div><div class='add'>+#define regDC_GPU_TIMER_READ                                                                            0x0128</div><div class='add'>+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129</div><div class='add'>+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS                                                                        0x012a</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2</div><div class='add'>+#define regDCCG_INTERRUPT_DEST                                                                          0x0148</div><div class='add'>+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDMU_INTERRUPT_DEST                                                                           0x0149</div><div class='add'>+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regDMU_INTERRUPT_DEST2                                                                          0x014a</div><div class='add'>+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2</div><div class='add'>+#define regDCPG_INTERRUPT_DEST                                                                          0x014b</div><div class='add'>+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c</div><div class='add'>+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2</div><div class='add'>+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d</div><div class='add'>+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2</div><div class='add'>+#define regWB_INTERRUPT_DEST                                                                            0x014e</div><div class='add'>+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2</div><div class='add'>+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150</div><div class='add'>+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152</div><div class='add'>+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2</div><div class='add'>+#define regMPC_INTERRUPT_DEST                                                                           0x0153</div><div class='add'>+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regOPP_INTERRUPT_DEST                                                                           0x0154</div><div class='add'>+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regOPTC_INTERRUPT_DEST                                                                          0x0155</div><div class='add'>+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG0_INTERRUPT_DEST                                                                          0x0156</div><div class='add'>+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG1_INTERRUPT_DEST                                                                          0x0157</div><div class='add'>+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG2_INTERRUPT_DEST                                                                          0x0158</div><div class='add'>+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG3_INTERRUPT_DEST                                                                          0x0159</div><div class='add'>+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG4_INTERRUPT_DEST                                                                          0x015a</div><div class='add'>+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG5_INTERRUPT_DEST                                                                          0x015b</div><div class='add'>+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG_INTERRUPT_DEST                                                                           0x015c</div><div class='add'>+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d</div><div class='add'>+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2</div><div class='add'>+#define regDIO_INTERRUPT_DEST                                                                           0x015f</div><div class='add'>+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regDCIO_INTERRUPT_DEST                                                                          0x0160</div><div class='add'>+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD_INTERRUPT_DEST                                                                           0x0161</div><div class='add'>+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regAZ_INTERRUPT_DEST                                                                            0x0162</div><div class='add'>+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2</div><div class='add'>+#define regAUX_INTERRUPT_DEST                                                                           0x0163</div><div class='add'>+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regDSC_INTERRUPT_DEST                                                                           0x0164</div><div class='add'>+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regHPO_INTERRUPT_DEST                                                                           0x0165</div><div class='add'>+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dmu_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCC_DC_PIPE_DIS                                                                               0x00ca</div><div class='add'>+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2</div><div class='add'>+#define regDMU_CLK_CNTL                                                                                 0x00cb</div><div class='add'>+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd</div><div class='add'>+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce</div><div class='add'>+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regZSC_CNTL                                                                                     0x00cf</div><div class='add'>+#define regZSC_CNTL_BASE_IDX                                                                            2</div><div class='add'>+#define regZSC_CNTL2                                                                                    0x00d0</div><div class='add'>+#define regZSC_CNTL2_BASE_IDX                                                                           2</div><div class='add'>+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6</div><div class='add'>+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2</div><div class='add'>+#define regZSC_STATUS                                                                                   0x00d7</div><div class='add'>+#define regZSC_STATUS_BASE_IDX                                                                          2</div><div class='add'>+#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG                                                                0x00d8</div><div class='add'>+#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                       2</div><div class='add'>+#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG                                                                 0x00d9</div><div class='add'>+#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                        2</div><div class='add'>+#define regZPR_CLK_UNGATE_DELAY                                                                         0x00da</div><div class='add'>+#define regZPR_CLK_UNGATE_DELAY_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dc_pg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDOMAIN0_PG_CONFIG                                                                            0x0080</div><div class='add'>+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN0_PG_STATUS                                                                            0x0081</div><div class='add'>+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN1_PG_CONFIG                                                                            0x0082</div><div class='add'>+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN1_PG_STATUS                                                                            0x0083</div><div class='add'>+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN2_PG_CONFIG                                                                            0x0084</div><div class='add'>+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN2_PG_STATUS                                                                            0x0085</div><div class='add'>+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN3_PG_CONFIG                                                                            0x0086</div><div class='add'>+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN3_PG_STATUS                                                                            0x0087</div><div class='add'>+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN16_PG_CONFIG                                                                           0x0089</div><div class='add'>+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN16_PG_STATUS                                                                           0x008a</div><div class='add'>+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN17_PG_CONFIG                                                                           0x008b</div><div class='add'>+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN17_PG_STATUS                                                                           0x008c</div><div class='add'>+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN18_PG_CONFIG                                                                           0x008d</div><div class='add'>+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN18_PG_STATUS                                                                           0x008e</div><div class='add'>+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN19_PG_CONFIG                                                                           0x008f</div><div class='add'>+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN19_PG_STATUS                                                                           0x0090</div><div class='add'>+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN22_PG_CONFIG                                                                           0x0092</div><div class='add'>+#define regDOMAIN22_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN22_PG_STATUS                                                                           0x0093</div><div class='add'>+#define regDOMAIN22_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN23_PG_CONFIG                                                                           0x0094</div><div class='add'>+#define regDOMAIN23_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN23_PG_STATUS                                                                           0x0095</div><div class='add'>+#define regDOMAIN23_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN24_PG_CONFIG                                                                           0x0096</div><div class='add'>+#define regDOMAIN24_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN24_PG_STATUS                                                                           0x0097</div><div class='add'>+#define regDOMAIN24_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN25_PG_CONFIG                                                                           0x0098</div><div class='add'>+#define regDOMAIN25_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN25_PG_STATUS                                                                           0x0099</div><div class='add'>+#define regDOMAIN25_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS                                                                        0x009a</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x009b</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_3                                                                      0x009c</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX                                                             2</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x009d</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_2                                                                     0x009e</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x009f</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2</div><div class='add'>+#define regDC_IP_REQUEST_CNTL                                                                           0x00a0</div><div class='add'>+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regLONO_MEM_PWR_REQ_CNTL                                                                        0x00a4</div><div class='add'>+#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dmcub_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDMCUB_REGION0_OFFSET                                                                         0x018e</div><div class='add'>+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f</div><div class='add'>+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION1_OFFSET                                                                         0x0190</div><div class='add'>+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191</div><div class='add'>+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION2_OFFSET                                                                         0x0192</div><div class='add'>+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193</div><div class='add'>+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION4_OFFSET                                                                         0x0196</div><div class='add'>+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197</div><div class='add'>+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION5_OFFSET                                                                         0x0198</div><div class='add'>+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199</div><div class='add'>+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION6_OFFSET                                                                         0x019a</div><div class='add'>+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b</div><div class='add'>+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION7_OFFSET                                                                         0x019c</div><div class='add'>+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d</div><div class='add'>+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e</div><div class='add'>+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f</div><div class='add'>+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0</div><div class='add'>+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1</div><div class='add'>+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2</div><div class='add'>+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3</div><div class='add'>+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4</div><div class='add'>+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5</div><div class='add'>+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6</div><div class='add'>+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7</div><div class='add'>+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8</div><div class='add'>+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9</div><div class='add'>+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa</div><div class='add'>+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab</div><div class='add'>+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac</div><div class='add'>+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad</div><div class='add'>+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae</div><div class='add'>+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af</div><div class='add'>+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0</div><div class='add'>+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1</div><div class='add'>+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2</div><div class='add'>+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3</div><div class='add'>+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4</div><div class='add'>+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5</div><div class='add'>+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6</div><div class='add'>+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7</div><div class='add'>+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8</div><div class='add'>+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2</div><div class='add'>+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc</div><div class='add'>+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd</div><div class='add'>+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDMCUB_SEC_CNTL                                                                               0x01ce</div><div class='add'>+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_MEM_CNTL                                                                               0x01cf</div><div class='add'>+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0</div><div class='add'>+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1</div><div class='add'>+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2</div><div class='add'>+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3</div><div class='add'>+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4</div><div class='add'>+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5</div><div class='add'>+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6</div><div class='add'>+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7</div><div class='add'>+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8</div><div class='add'>+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2</div><div class='add'>+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9</div><div class='add'>+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da</div><div class='add'>+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db</div><div class='add'>+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc</div><div class='add'>+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2</div><div class='add'>+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd</div><div class='add'>+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de</div><div class='add'>+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df</div><div class='add'>+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2</div><div class='add'>+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_SCRATCH0                                                                               0x01e3</div><div class='add'>+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH1                                                                               0x01e4</div><div class='add'>+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH2                                                                               0x01e5</div><div class='add'>+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH3                                                                               0x01e6</div><div class='add'>+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH4                                                                               0x01e7</div><div class='add'>+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH5                                                                               0x01e8</div><div class='add'>+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH6                                                                               0x01e9</div><div class='add'>+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH7                                                                               0x01ea</div><div class='add'>+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH8                                                                               0x01eb</div><div class='add'>+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH9                                                                               0x01ec</div><div class='add'>+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH10                                                                              0x01ed</div><div class='add'>+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH11                                                                              0x01ee</div><div class='add'>+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH12                                                                              0x01ef</div><div class='add'>+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH13                                                                              0x01f0</div><div class='add'>+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH14                                                                              0x01f1</div><div class='add'>+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH15                                                                              0x01f2</div><div class='add'>+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH16                                                                              0x01f3</div><div class='add'>+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH17                                                                              0x01f4</div><div class='add'>+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH18                                                                              0x01f5</div><div class='add'>+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_CNTL                                                                                   0x01f6</div><div class='add'>+#define regDMCUB_CNTL_BASE_IDX                                                                          2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7</div><div class='add'>+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8</div><div class='add'>+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9</div><div class='add'>+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa</div><div class='add'>+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2</div><div class='add'>+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb</div><div class='add'>+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc</div><div class='add'>+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd</div><div class='add'>+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_PROC_ID                                                                                0x01ff</div><div class='add'>+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2</div><div class='add'>+#define regDMCUB_CNTL2                                                                                  0x0200</div><div class='add'>+#define regDMCUB_CNTL2_BASE_IDX                                                                         2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215</div><div class='add'>+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216</div><div class='add'>+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217</div><div class='add'>+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218</div><div class='add'>+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219</div><div class='add'>+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a</div><div class='add'>+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2</div><div class='add'>+#define regDMCUB_SCRATCH19                                                                              0x022e</div><div class='add'>+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH20                                                                              0x022f</div><div class='add'>+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH21                                                                              0x0230</div><div class='add'>+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH22                                                                              0x0231</div><div class='add'>+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH23                                                                              0x0232</div><div class='add'>+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228</div><div class='add'>+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regDWB_MEM_PWR_CTRL                                                                             0x3229</div><div class='add'>+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2</div><div class='add'>+#define regFC_MODE_CTRL                                                                                 0x322a</div><div class='add'>+#define regFC_MODE_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regFC_FLOW_CTRL                                                                                 0x322b</div><div class='add'>+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regFC_WINDOW_START                                                                              0x322c</div><div class='add'>+#define regFC_WINDOW_START_BASE_IDX                                                                     2</div><div class='add'>+#define regFC_WINDOW_SIZE                                                                               0x322d</div><div class='add'>+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regFC_SOURCE_SIZE                                                                               0x322e</div><div class='add'>+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDWB_UPDATE_CTRL                                                                              0x322f</div><div class='add'>+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2</div><div class='add'>+#define regDWB_CRC_CTRL                                                                                 0x3230</div><div class='add'>+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regDWB_CRC_MASK_R_G                                                                             0x3231</div><div class='add'>+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2</div><div class='add'>+#define regDWB_CRC_MASK_B_A                                                                             0x3232</div><div class='add'>+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2</div><div class='add'>+#define regDWB_CRC_VAL_R_G                                                                              0x3233</div><div class='add'>+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2</div><div class='add'>+#define regDWB_CRC_VAL_B_A                                                                              0x3234</div><div class='add'>+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2</div><div class='add'>+#define regDWB_OUT_CTRL                                                                                 0x3235</div><div class='add'>+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2</div><div class='add'>+#define regDWB_HOST_READ_CONTROL                                                                        0x3238</div><div class='add'>+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDWB_OVERFLOW_STATUS                                                                          0x3239</div><div class='add'>+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2</div><div class='add'>+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a</div><div class='add'>+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2</div><div class='add'>+#define regDWB_SOFT_RESET                                                                               0x323b</div><div class='add'>+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDWB_HDR_MULT_COEF                                                                            0x3294</div><div class='add'>+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2</div><div class='add'>+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295</div><div class='add'>+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2</div><div class='add'>+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296</div><div class='add'>+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_CONTROL                                                                             0x32a3</div><div class='add'>+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4</div><div class='add'>+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2</div><div class='add'>+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5</div><div class='add'>+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2</div><div class='add'>+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6</div><div class='add'>+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xca20</div><div class='add'>+#define regDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x3288</div><div class='add'>+#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x3289</div><div class='add'>+#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON3_PERFCOUNTER_STATE                                                                0x328a</div><div class='add'>+#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CNTL                                                                     0x328b</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CNTL2                                                                    0x328c</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x328d</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x328e</div><div class='add'>+#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON3_PERFMON_HI                                                                       0x328f</div><div class='add'>+#define regDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON3_PERFMON_LOW                                                                      0x3290</div><div class='add'>+#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272</div><div class='add'>+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274</div><div class='add'>+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_PITCH                                                                            0x0275</div><div class='add'>+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e</div><div class='add'>+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f</div><div class='add'>+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292</div><div class='add'>+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294</div><div class='add'>+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296</div><div class='add'>+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297</div><div class='add'>+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298</div><div class='add'>+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2</div><div class='add'>+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299</div><div class='add'>+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a</div><div class='add'>+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3</div><div class='add'>+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4</div><div class='add'>+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5</div><div class='add'>+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6</div><div class='add'>+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7</div><div class='add'>+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2</div><div class='add'>+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8</div><div class='add'>+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_MIN_TTO                                                                              0x02a9</div><div class='add'>+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xd48</div><div class='add'>+#define regDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352</div><div class='add'>+#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353</div><div class='add'>+#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354</div><div class='add'>+#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CNTL                                                                     0x0355</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358</div><div class='add'>+#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON4_PERFMON_HI                                                                       0x0359</div><div class='add'>+#define regDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON4_PERFMON_LOW                                                                      0x035a</div><div class='add'>+#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2</div><div class='add'>+#define regMCIF_WB_WATERMARK                                                                            0x02ab</div><div class='add'>+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2</div><div class='add'>+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0</div><div class='add'>+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2</div><div class='add'>+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1</div><div class='add'>+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2</div><div class='add'>+#define regMMHUBBUB_CTRL                                                                                0x0333</div><div class='add'>+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2</div><div class='add'>+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334</div><div class='add'>+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regWBIF0_MISC_CTRL                                                                              0x0335</div><div class='add'>+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2</div><div class='add'>+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336</div><div class='add'>+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2</div><div class='add'>+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337</div><div class='add'>+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0340</div><div class='add'>+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regMMHUBBUB_SOFT_RESET                                                                          0x0341</div><div class='add'>+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2</div><div class='add'>+#define regDMU_IF_ERR_STATUS                                                                            0x0345</div><div class='add'>+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346</div><div class='add'>+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2</div><div class='add'>+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348</div><div class='add'>+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0controller_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2</div><div class='add'>+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2</div><div class='add'>+#define regAZALIA_AUDIO_DTO                                                                             0x03c3</div><div class='add'>+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2</div><div class='add'>+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4</div><div class='add'>+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5</div><div class='add'>+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6</div><div class='add'>+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2</div><div class='add'>+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7</div><div class='add'>+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8</div><div class='add'>+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9</div><div class='add'>+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca</div><div class='add'>+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3</div><div class='add'>+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4</div><div class='add'>+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2</div><div class='add'>+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5</div><div class='add'>+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6</div><div class='add'>+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd</div><div class='add'>+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3</div><div class='add'>+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4</div><div class='add'>+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5</div><div class='add'>+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6</div><div class='add'>+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_RESULT                                                                           0x03e7</div><div class='add'>+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8</div><div class='add'>+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9</div><div class='add'>+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea</div><div class='add'>+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb</div><div class='add'>+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_RESULT                                                                           0x03ec</div><div class='add'>+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2</div><div class='add'>+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee</div><div class='add'>+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef</div><div class='add'>+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0root_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2</div><div class='add'>+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408</div><div class='add'>+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2</div><div class='add'>+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409</div><div class='add'>+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2</div><div class='add'>+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412</div><div class='add'>+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2</div><div class='add'>+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413</div><div class='add'>+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b</div><div class='add'>+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2</div><div class='add'>+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c</div><div class='add'>+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2</div><div class='add'>+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d</div><div class='add'>+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_az_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZ_CLOCK_CNTL                                                                                0x0372</div><div class='add'>+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2</div><div class='add'>+#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0373</div><div class='add'>+#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xde8</div><div class='add'>+#define regDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a</div><div class='add'>+#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b</div><div class='add'>+#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c</div><div class='add'>+#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CNTL                                                                     0x037d</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380</div><div class='add'>+#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON5_PERFMON_HI                                                                       0x0381</div><div class='add'>+#define regDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON5_PERFMON_LOW                                                                      0x0382</div><div class='add'>+#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream1_dispdec</div><div class='add'>+// base address: 0x8</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream2_dispdec</div><div class='add'>+// base address: 0x10</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream3_dispdec</div><div class='add'>+// base address: 0x18</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream4_dispdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream5_dispdec</div><div class='add'>+// base address: 0x28</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream6_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream7_dispdec</div><div class='add'>+// base address: 0x38</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream8_dispdec</div><div class='add'>+// base address: 0x320</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream9_dispdec</div><div class='add'>+// base address: 0x328</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream10_dispdec</div><div class='add'>+// base address: 0x330</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream11_dispdec</div><div class='add'>+// base address: 0x338</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream12_dispdec</div><div class='add'>+// base address: 0x340</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream13_dispdec</div><div class='add'>+// base address: 0x348</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream14_dispdec</div><div class='add'>+// base address: 0x350</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream15_dispdec</div><div class='add'>+// base address: 0x358</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec</div><div class='add'>+// base address: 0x18</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec</div><div class='add'>+// base address: 0x48</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec</div><div class='add'>+// base address: 0x78</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec</div><div class='add'>+// base address: 0x90</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec</div><div class='add'>+// base address: 0xa8</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec</div><div class='add'>+// base address: 0x10</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec</div><div class='add'>+// base address: 0x50</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec</div><div class='add'>+// base address: 0x70</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9</div><div class='add'>+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa</div><div class='add'>+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb</div><div class='add'>+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc</div><div class='add'>+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0501</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A                                                   0x0502</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX                                          2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0503</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A                                                    0x0504</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX                                           2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0505</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x0506</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0507</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0508</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0509</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x050a</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050b</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x050c</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B                                                   0x050d</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX                                          2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050e</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B                                                    0x050f</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX                                           2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x0510</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x0511</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0512</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0513</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0514</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C                                                      0x0515</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0516</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0517</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C                                                   0x0518</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX                                          2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0519</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C                                                    0x051a</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX                                           2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x051b</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C                                                  0x051c</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x051d</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x051e</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x051f</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D                                                      0x0520</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0521</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x0522</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D                                                   0x0523</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX                                          2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x0524</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D                                                    0x0525</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX                                           2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x0526</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D                                                  0x0527</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0528</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0529</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x052a</div><div class='add'>+#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x052b</div><div class='add'>+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x052c</div><div class='add'>+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x052d</div><div class='add'>+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x052e</div><div class='add'>+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x052f</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0530</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0531</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0532</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0533</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0534</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0535</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0536</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regVTG0_CONTROL                                                                                 0x0537</div><div class='add'>+#define regVTG0_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regVTG1_CONTROL                                                                                 0x0538</div><div class='add'>+#define regVTG1_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regVTG2_CONTROL                                                                                 0x0539</div><div class='add'>+#define regVTG2_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regVTG3_CONTROL                                                                                 0x053a</div><div class='add'>+#define regVTG3_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regDCHUBBUB_SOFT_RESET                                                                          0x053b</div><div class='add'>+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x053c</div><div class='add'>+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDCFCLK_CNTL                                                                                  0x053d</div><div class='add'>+#define regDCFCLK_CNTL_BASE_IDX                                                                         2</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x053e</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x053f</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0540</div><div class='add'>+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2</div><div class='add'>+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0541</div><div class='add'>+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x0547</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x0548</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0549</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regFMON_CTRL                                                                                    0x054a</div><div class='add'>+#define regFMON_CTRL_BASE_IDX                                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2</div><div class='add'>+#define regVM_REQUEST_PHYSICAL                                                                          0x0472</div><div class='add'>+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2</div><div class='add'>+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475</div><div class='add'>+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2</div><div class='add'>+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476</div><div class='add'>+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2</div><div class='add'>+#define regDCN_VM_FB_OFFSET                                                                             0x0477</div><div class='add'>+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2</div><div class='add'>+#define regDCN_VM_AGP_BOT                                                                               0x0478</div><div class='add'>+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2</div><div class='add'>+#define regDCN_VM_AGP_TOP                                                                               0x0479</div><div class='add'>+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2</div><div class='add'>+#define regDCN_VM_AGP_BASE                                                                              0x047a</div><div class='add'>+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL                                                          0x0481</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0482</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2</div><div class='add'>+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0484</div><div class='add'>+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0485</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0486</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1</div><div class='add'>+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_R                                                                          0x04b2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_R_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_G                                                                          0x04b3</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_G_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_B                                                                          0x04b4</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_B_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_A                                                                          0x04b5</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_A_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6</div><div class='add'>+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7</div><div class='add'>+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8</div><div class='add'>+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9</div><div class='add'>+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba</div><div class='add'>+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb</div><div class='add'>+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc</div><div class='add'>+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd</div><div class='add'>+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be</div><div class='add'>+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4</div><div class='add'>+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c5</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_R                                                                          0x04ca</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_R_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_G                                                                          0x04cb</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_G_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_B                                                                          0x04cc</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_B_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_A                                                                          0x04cd</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_A_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559</div><div class='add'>+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560</div><div class='add'>+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567</div><div class='add'>+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e</div><div class='add'>+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575</div><div class='add'>+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c</div><div class='add'>+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583</div><div class='add'>+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a</div><div class='add'>+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591</div><div class='add'>+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598</div><div class='add'>+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f</div><div class='add'>+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6</div><div class='add'>+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad</div><div class='add'>+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4</div><div class='add'>+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb</div><div class='add'>+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2</div><div class='add'>+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2</div><div class='add'>+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb</div><div class='add'>+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc</div><div class='add'>+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x1534</div><div class='add'>+#define regDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d</div><div class='add'>+#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e</div><div class='add'>+#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f</div><div class='add'>+#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CNTL                                                                     0x0550</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553</div><div class='add'>+#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON6_PERFMON_HI                                                                       0x0554</div><div class='add'>+#define regDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON6_PERFMON_LOW                                                                      0x0555</div><div class='add'>+#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5</div><div class='add'>+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6</div><div class='add'>+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7</div><div class='add'>+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3</div><div class='add'>+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4</div><div class='add'>+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5</div><div class='add'>+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f6</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP                                                                     0x05f7</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f8</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f9</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fd</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fe</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x05ff</div><div class='add'>+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609</div><div class='add'>+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x061f</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0620</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0621</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0622</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0623</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0624</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0625</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0626</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0627</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0628</div><div class='add'>+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0629</div><div class='add'>+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062a</div><div class='add'>+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062b</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062c</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062d</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062e</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x062f</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0630</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0631</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0632</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0633</div><div class='add'>+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0634</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0635</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0642</div><div class='add'>+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0643</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0644</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0645</div><div class='add'>+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0646</div><div class='add'>+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0647</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0648</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0649</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064a</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064b</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064c</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064d</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064e</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x064f</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0650</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0651</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0652</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0653</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0654</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0655</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0656</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0657</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0658</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0659</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065a</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065b</div><div class='add'>+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065c</div><div class='add'>+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065d</div><div class='add'>+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065e</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x065f</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0662</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0663</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0664</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0665</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0666</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0667</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0668</div><div class='add'>+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0669</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x066a</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x066b</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c</div><div class='add'>+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673</div><div class='add'>+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678</div><div class='add'>+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b</div><div class='add'>+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c</div><div class='add'>+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d</div><div class='add'>+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e</div><div class='add'>+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f</div><div class='add'>+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684</div><div class='add'>+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685</div><div class='add'>+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686</div><div class='add'>+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x1a74</div><div class='add'>+#define regDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d</div><div class='add'>+#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e</div><div class='add'>+#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f</div><div class='add'>+#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3</div><div class='add'>+#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_HI                                                                       0x06a4</div><div class='add'>+#define regDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON7_PERFMON_LOW                                                                      0x06a5</div><div class='add'>+#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1</div><div class='add'>+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2</div><div class='add'>+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3</div><div class='add'>+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf</div><div class='add'>+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0</div><div class='add'>+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1</div><div class='add'>+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP                                                                     0x06d3</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d4</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d5</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d9</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06da</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06db</div><div class='add'>+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5</div><div class='add'>+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fb</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fc</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fd</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06fe</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06ff</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0700</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0701</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0702</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0703</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0704</div><div class='add'>+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0705</div><div class='add'>+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0706</div><div class='add'>+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0707</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0708</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0709</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070a</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070b</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070c</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070d</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070e</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x070f</div><div class='add'>+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0710</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0711</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071e</div><div class='add'>+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x071f</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0720</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0721</div><div class='add'>+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0722</div><div class='add'>+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0723</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0724</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0725</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0726</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0727</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0728</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0729</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072a</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072b</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072c</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072d</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072e</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x072f</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0730</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0731</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0732</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0733</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0734</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0735</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0736</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0737</div><div class='add'>+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0738</div><div class='add'>+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0739</div><div class='add'>+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073a</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073b</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073e</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x073f</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0740</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0741</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0742</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0743</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x0744</div><div class='add'>+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x0745</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x0746</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x0747</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748</div><div class='add'>+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f</div><div class='add'>+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754</div><div class='add'>+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757</div><div class='add'>+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758</div><div class='add'>+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759</div><div class='add'>+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a</div><div class='add'>+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b</div><div class='add'>+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760</div><div class='add'>+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761</div><div class='add'>+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762</div><div class='add'>+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x1de4</div><div class='add'>+#define regDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779</div><div class='add'>+#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a</div><div class='add'>+#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b</div><div class='add'>+#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CNTL                                                                     0x077c</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f</div><div class='add'>+#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON8_PERFMON_HI                                                                       0x0780</div><div class='add'>+#define regDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON8_PERFMON_LOW                                                                      0x0781</div><div class='add'>+#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d</div><div class='add'>+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e</div><div class='add'>+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f</div><div class='add'>+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab</div><div class='add'>+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac</div><div class='add'>+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad</div><div class='add'>+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07ae</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP                                                                     0x07af</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b0</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b1</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b5</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b6</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07b7</div><div class='add'>+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1</div><div class='add'>+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d7</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d8</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d9</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07da</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07db</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dc</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07dd</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07de</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07df</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e0</div><div class='add'>+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e1</div><div class='add'>+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e2</div><div class='add'>+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e3</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e4</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e5</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e6</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e7</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e8</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e9</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ea</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07eb</div><div class='add'>+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ec</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ed</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fa</div><div class='add'>+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fb</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fc</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fd</div><div class='add'>+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07fe</div><div class='add'>+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07ff</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0800</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0801</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0802</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0803</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0804</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0805</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0806</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0807</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0808</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0809</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080a</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080b</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080c</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080d</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080e</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x080f</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0810</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0811</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0812</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0813</div><div class='add'>+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0814</div><div class='add'>+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0815</div><div class='add'>+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0816</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0817</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081a</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081b</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081c</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081d</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081e</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x081f</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0820</div><div class='add'>+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0821</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x0822</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x0823</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824</div><div class='add'>+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b</div><div class='add'>+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830</div><div class='add'>+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833</div><div class='add'>+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834</div><div class='add'>+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835</div><div class='add'>+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836</div><div class='add'>+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837</div><div class='add'>+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c</div><div class='add'>+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d</div><div class='add'>+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e</div><div class='add'>+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x2154</div><div class='add'>+#define regDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855</div><div class='add'>+#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856</div><div class='add'>+#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857</div><div class='add'>+#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CNTL                                                                     0x0858</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b</div><div class='add'>+#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON9_PERFMON_HI                                                                       0x085c</div><div class='add'>+#define regDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2</div><div class='add'>+#define regDC_PERFMON9_PERFMON_LOW                                                                      0x085d</div><div class='add'>+#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879</div><div class='add'>+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a</div><div class='add'>+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b</div><div class='add'>+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887</div><div class='add'>+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888</div><div class='add'>+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889</div><div class='add'>+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088a</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP                                                                     0x088b</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088c</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088d</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0891</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0892</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0893</div><div class='add'>+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d</div><div class='add'>+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b3</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b4</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b5</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b6</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b7</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b8</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b9</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08ba</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bb</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bc</div><div class='add'>+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08bd</div><div class='add'>+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08be</div><div class='add'>+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08bf</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c0</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c1</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c3</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c4</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c5</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c6</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c7</div><div class='add'>+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c8</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c9</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d6</div><div class='add'>+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d7</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d8</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d9</div><div class='add'>+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08da</div><div class='add'>+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08db</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dc</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08dd</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08de</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08df</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e0</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e1</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e3</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e4</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e5</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e6</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e7</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e8</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e9</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ea</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08eb</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ec</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ed</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ee</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08ef</div><div class='add'>+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f0</div><div class='add'>+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f1</div><div class='add'>+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f3</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f6</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f7</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f8</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f9</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fa</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fb</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08fc</div><div class='add'>+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08fd</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08fe</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08ff</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900</div><div class='add'>+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907</div><div class='add'>+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c</div><div class='add'>+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f</div><div class='add'>+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910</div><div class='add'>+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911</div><div class='add'>+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912</div><div class='add'>+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913</div><div class='add'>+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918</div><div class='add'>+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919</div><div class='add'>+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a</div><div class='add'>+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x24c4</div><div class='add'>+#define regDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931</div><div class='add'>+#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932</div><div class='add'>+#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933</div><div class='add'>+#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CNTL                                                                    0x0934</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937</div><div class='add'>+#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON10_PERFMON_HI                                                                      0x0938</div><div class='add'>+#define regDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON10_PERFMON_LOW                                                                     0x0939</div><div class='add'>+#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf</div><div class='add'>+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0</div><div class='add'>+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd</div><div class='add'>+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde</div><div class='add'>+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec</div><div class='add'>+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced</div><div class='add'>+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee</div><div class='add'>+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4</div><div class='add'>+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL0_SCL_MODE                                                                               0x0cfb</div><div class='add'>+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc</div><div class='add'>+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd</div><div class='add'>+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe</div><div class='add'>+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff</div><div class='add'>+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a</div><div class='add'>+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b</div><div class='add'>+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c</div><div class='add'>+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f</div><div class='add'>+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10</div><div class='add'>+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_RECOUT_START                                                                           0x0d11</div><div class='add'>+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12</div><div class='add'>+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_MPC_SIZE                                                                               0x0d13</div><div class='add'>+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14</div><div class='add'>+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15</div><div class='add'>+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16</div><div class='add'>+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19</div><div class='add'>+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a</div><div class='add'>+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCM0_CM_CONTROL                                                                               0x0d20</div><div class='add'>+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21</div><div class='add'>+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22</div><div class='add'>+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23</div><div class='add'>+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24</div><div class='add'>+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25</div><div class='add'>+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26</div><div class='add'>+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27</div><div class='add'>+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a</div><div class='add'>+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2</div><div class='add'>+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b</div><div class='add'>+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c</div><div class='add'>+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d</div><div class='add'>+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0d87</div><div class='add'>+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0d88</div><div class='add'>+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0d89</div><div class='add'>+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM0_CM_DEALPHA                                                                               0x0d8b</div><div class='add'>+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM0_CM_COEF_FORMAT                                                                           0x0d8c</div><div class='add'>+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0d8d</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0d8e</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM0_DPP_CRC_VAL_R                                                                            0x0d8f</div><div class='add'>+#define regCM0_DPP_CRC_VAL_R_BASE_IDX                                                                   2</div><div class='add'>+#define regCM0_DPP_CRC_VAL_G                                                                            0x0d90</div><div class='add'>+#define regCM0_DPP_CRC_VAL_G_BASE_IDX                                                                   2</div><div class='add'>+#define regCM0_DPP_CRC_VAL_B                                                                            0x0d91</div><div class='add'>+#define regCM0_DPP_CRC_VAL_B_BASE_IDX                                                                   2</div><div class='add'>+#define regCM0_DPP_CRC_VAL_A                                                                            0x0d92</div><div class='add'>+#define regCM0_DPP_CRC_VAL_A_BASE_IDX                                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5</div><div class='add'>+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6</div><div class='add'>+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca</div><div class='add'>+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x3890</div><div class='add'>+#define regDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24</div><div class='add'>+#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25</div><div class='add'>+#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26</div><div class='add'>+#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a</div><div class='add'>+#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON11_PERFMON_HI                                                                      0x0e2b</div><div class='add'>+#define regDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c</div><div class='add'>+#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a</div><div class='add'>+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b</div><div class='add'>+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48</div><div class='add'>+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49</div><div class='add'>+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57</div><div class='add'>+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58</div><div class='add'>+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59</div><div class='add'>+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f</div><div class='add'>+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL1_SCL_MODE                                                                               0x0e66</div><div class='add'>+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67</div><div class='add'>+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68</div><div class='add'>+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69</div><div class='add'>+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a</div><div class='add'>+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75</div><div class='add'>+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76</div><div class='add'>+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77</div><div class='add'>+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a</div><div class='add'>+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b</div><div class='add'>+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_RECOUT_START                                                                           0x0e7c</div><div class='add'>+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d</div><div class='add'>+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_MPC_SIZE                                                                               0x0e7e</div><div class='add'>+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f</div><div class='add'>+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80</div><div class='add'>+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81</div><div class='add'>+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84</div><div class='add'>+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85</div><div class='add'>+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regCM1_CM_CONTROL                                                                               0x0e8b</div><div class='add'>+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c</div><div class='add'>+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d</div><div class='add'>+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e</div><div class='add'>+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f</div><div class='add'>+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90</div><div class='add'>+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91</div><div class='add'>+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92</div><div class='add'>+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5</div><div class='add'>+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2</div><div class='add'>+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6</div><div class='add'>+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7</div><div class='add'>+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8</div><div class='add'>+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0ef2</div><div class='add'>+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0ef3</div><div class='add'>+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0ef4</div><div class='add'>+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM1_CM_DEALPHA                                                                               0x0ef6</div><div class='add'>+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM1_CM_COEF_FORMAT                                                                           0x0ef7</div><div class='add'>+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0ef8</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0ef9</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM1_DPP_CRC_VAL_R                                                                            0x0efa</div><div class='add'>+#define regCM1_DPP_CRC_VAL_R_BASE_IDX                                                                   2</div><div class='add'>+#define regCM1_DPP_CRC_VAL_G                                                                            0x0efb</div><div class='add'>+#define regCM1_DPP_CRC_VAL_G_BASE_IDX                                                                   2</div><div class='add'>+#define regCM1_DPP_CRC_VAL_B                                                                            0x0efc</div><div class='add'>+#define regCM1_DPP_CRC_VAL_B_BASE_IDX                                                                   2</div><div class='add'>+#define regCM1_DPP_CRC_VAL_A                                                                            0x0efd</div><div class='add'>+#define regCM1_DPP_CRC_VAL_A_BASE_IDX                                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30</div><div class='add'>+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31</div><div class='add'>+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35</div><div class='add'>+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x3e3c</div><div class='add'>+#define regDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f</div><div class='add'>+#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90</div><div class='add'>+#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91</div><div class='add'>+#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95</div><div class='add'>+#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON12_PERFMON_HI                                                                      0x0f96</div><div class='add'>+#define regDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON12_PERFMON_LOW                                                                     0x0f97</div><div class='add'>+#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5</div><div class='add'>+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6</div><div class='add'>+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3</div><div class='add'>+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4</div><div class='add'>+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2</div><div class='add'>+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3</div><div class='add'>+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4</div><div class='add'>+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca</div><div class='add'>+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL2_SCL_MODE                                                                               0x0fd1</div><div class='add'>+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2</div><div class='add'>+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3</div><div class='add'>+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4</div><div class='add'>+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5</div><div class='add'>+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0</div><div class='add'>+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1</div><div class='add'>+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2</div><div class='add'>+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5</div><div class='add'>+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6</div><div class='add'>+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_RECOUT_START                                                                           0x0fe7</div><div class='add'>+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8</div><div class='add'>+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_MPC_SIZE                                                                               0x0fe9</div><div class='add'>+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea</div><div class='add'>+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb</div><div class='add'>+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec</div><div class='add'>+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef</div><div class='add'>+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0</div><div class='add'>+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regCM2_CM_CONTROL                                                                               0x0ff6</div><div class='add'>+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7</div><div class='add'>+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8</div><div class='add'>+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9</div><div class='add'>+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa</div><div class='add'>+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb</div><div class='add'>+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc</div><div class='add'>+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd</div><div class='add'>+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010</div><div class='add'>+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2</div><div class='add'>+#define regCM2_CM_BIAS_CR_R                                                                             0x1011</div><div class='add'>+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012</div><div class='add'>+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013</div><div class='add'>+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_HDR_MULT_COEF                                                                         0x105d</div><div class='add'>+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x105e</div><div class='add'>+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x105f</div><div class='add'>+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM2_CM_DEALPHA                                                                               0x1061</div><div class='add'>+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM2_CM_COEF_FORMAT                                                                           0x1062</div><div class='add'>+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x1063</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x1064</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM2_DPP_CRC_VAL_R                                                                            0x1065</div><div class='add'>+#define regCM2_DPP_CRC_VAL_R_BASE_IDX                                                                   2</div><div class='add'>+#define regCM2_DPP_CRC_VAL_G                                                                            0x1066</div><div class='add'>+#define regCM2_DPP_CRC_VAL_G_BASE_IDX                                                                   2</div><div class='add'>+#define regCM2_DPP_CRC_VAL_B                                                                            0x1067</div><div class='add'>+#define regCM2_DPP_CRC_VAL_B_BASE_IDX                                                                   2</div><div class='add'>+#define regCM2_DPP_CRC_VAL_A                                                                            0x1068</div><div class='add'>+#define regCM2_DPP_CRC_VAL_A_BASE_IDX                                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b</div><div class='add'>+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c</div><div class='add'>+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0</div><div class='add'>+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x43e8</div><div class='add'>+#define regDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa</div><div class='add'>+#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb</div><div class='add'>+#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc</div><div class='add'>+#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100</div><div class='add'>+#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON13_PERFMON_HI                                                                      0x1101</div><div class='add'>+#define regDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON13_PERFMON_LOW                                                                     0x1102</div><div class='add'>+#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110</div><div class='add'>+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111</div><div class='add'>+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e</div><div class='add'>+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f</div><div class='add'>+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d</div><div class='add'>+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e</div><div class='add'>+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f</div><div class='add'>+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135</div><div class='add'>+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL3_SCL_MODE                                                                               0x113c</div><div class='add'>+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d</div><div class='add'>+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL3_DSCL_CONTROL                                                                           0x113e</div><div class='add'>+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f</div><div class='add'>+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140</div><div class='add'>+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b</div><div class='add'>+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL3_DSCL_UPDATE                                                                            0x114c</div><div class='add'>+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d</div><div class='add'>+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_OTG_H_BLANK                                                                            0x1150</div><div class='add'>+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_OTG_V_BLANK                                                                            0x1151</div><div class='add'>+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_RECOUT_START                                                                           0x1152</div><div class='add'>+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_RECOUT_SIZE                                                                            0x1153</div><div class='add'>+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_MPC_SIZE                                                                               0x1154</div><div class='add'>+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155</div><div class='add'>+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156</div><div class='add'>+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL3_LB_V_COUNTER                                                                           0x1157</div><div class='add'>+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_OBUF_CONTROL                                                                           0x115a</div><div class='add'>+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b</div><div class='add'>+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regCM3_CM_CONTROL                                                                               0x1161</div><div class='add'>+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162</div><div class='add'>+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163</div><div class='add'>+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164</div><div class='add'>+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165</div><div class='add'>+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166</div><div class='add'>+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167</div><div class='add'>+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168</div><div class='add'>+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b</div><div class='add'>+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2</div><div class='add'>+#define regCM3_CM_BIAS_CR_R                                                                             0x117c</div><div class='add'>+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d</div><div class='add'>+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e</div><div class='add'>+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_HDR_MULT_COEF                                                                         0x11c8</div><div class='add'>+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x11c9</div><div class='add'>+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x11ca</div><div class='add'>+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM3_CM_DEALPHA                                                                               0x11cc</div><div class='add'>+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM3_CM_COEF_FORMAT                                                                           0x11cd</div><div class='add'>+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x11ce</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x11cf</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM3_DPP_CRC_VAL_R                                                                            0x11d0</div><div class='add'>+#define regCM3_DPP_CRC_VAL_R_BASE_IDX                                                                   2</div><div class='add'>+#define regCM3_DPP_CRC_VAL_G                                                                            0x11d1</div><div class='add'>+#define regCM3_DPP_CRC_VAL_G_BASE_IDX                                                                   2</div><div class='add'>+#define regCM3_DPP_CRC_VAL_B                                                                            0x11d2</div><div class='add'>+#define regCM3_DPP_CRC_VAL_B_BASE_IDX                                                                   2</div><div class='add'>+#define regCM3_DPP_CRC_VAL_A                                                                            0x11d3</div><div class='add'>+#define regCM3_DPP_CRC_VAL_A_BASE_IDX                                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106</div><div class='add'>+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107</div><div class='add'>+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b</div><div class='add'>+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x4994</div><div class='add'>+#define regDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265</div><div class='add'>+#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266</div><div class='add'>+#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267</div><div class='add'>+#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CNTL                                                                    0x1268</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b</div><div class='add'>+#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON14_PERFMON_HI                                                                      0x126c</div><div class='add'>+#define regDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON14_PERFMON_LOW                                                                     0x126d</div><div class='add'>+#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000</div><div class='add'>+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001</div><div class='add'>+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002</div><div class='add'>+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC0_MPCC_CONTROL                                                                           0x0003</div><div class='add'>+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004</div><div class='add'>+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005</div><div class='add'>+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006</div><div class='add'>+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009</div><div class='add'>+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a</div><div class='add'>+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b</div><div class='add'>+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c</div><div class='add'>+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d</div><div class='add'>+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC0_MPCC_STATUS                                                                            0x000e</div><div class='add'>+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc1_dispdec</div><div class='add'>+// base address: 0x54</div><div class='add'>+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015</div><div class='add'>+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016</div><div class='add'>+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017</div><div class='add'>+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC1_MPCC_CONTROL                                                                           0x0018</div><div class='add'>+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019</div><div class='add'>+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a</div><div class='add'>+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b</div><div class='add'>+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e</div><div class='add'>+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f</div><div class='add'>+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020</div><div class='add'>+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021</div><div class='add'>+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022</div><div class='add'>+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC1_MPCC_STATUS                                                                            0x0023</div><div class='add'>+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc2_dispdec</div><div class='add'>+// base address: 0xa8</div><div class='add'>+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a</div><div class='add'>+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b</div><div class='add'>+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c</div><div class='add'>+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC2_MPCC_CONTROL                                                                           0x002d</div><div class='add'>+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e</div><div class='add'>+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f</div><div class='add'>+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030</div><div class='add'>+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033</div><div class='add'>+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034</div><div class='add'>+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035</div><div class='add'>+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036</div><div class='add'>+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037</div><div class='add'>+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC2_MPCC_STATUS                                                                            0x0038</div><div class='add'>+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc3_dispdec</div><div class='add'>+// base address: 0xfc</div><div class='add'>+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f</div><div class='add'>+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040</div><div class='add'>+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041</div><div class='add'>+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC3_MPCC_CONTROL                                                                           0x0042</div><div class='add'>+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043</div><div class='add'>+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044</div><div class='add'>+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045</div><div class='add'>+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048</div><div class='add'>+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049</div><div class='add'>+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a</div><div class='add'>+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b</div><div class='add'>+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c</div><div class='add'>+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC3_MPCC_STATUS                                                                            0x004d</div><div class='add'>+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPC_CLOCK_CONTROL                                                                            0x0398</div><div class='add'>+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_SOFT_RESET                                                                               0x0399</div><div class='add'>+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3</div><div class='add'>+#define regMPC_CRC_CTRL                                                                                 0x039a</div><div class='add'>+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_CRC_SEL_CONTROL                                                                          0x039b</div><div class='add'>+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3</div><div class='add'>+#define regMPC_PERFMON_EVENT_CTRL                                                                       0x03a1</div><div class='add'>+#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_BYPASS_BG_AR                                                                             0x03a2</div><div class='add'>+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_BYPASS_BG_GB                                                                             0x03a3</div><div class='add'>+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_HOST_READ_CONTROL                                                                        0x03a4</div><div class='add'>+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPC_DPP_PENDING_STATUS                                                                       0x03a5</div><div class='add'>+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_PENDING_STATUS_MISC                                                                      0x03a6</div><div class='add'>+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x03a7</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x03a8</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET0                                                                        0x03a9</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x03aa</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x03ab</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x03ac</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x03ad</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET1                                                                        0x03ae</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x03af</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x03b0</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x03b1</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x03b2</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET2                                                                        0x03b3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x03b4</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x03b5</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x03b6</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x03b7</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET3                                                                        0x03b8</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x03b9</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x03ba</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3</div><div class='add'>+#define regMPC_CRC_RESULT_A                                                                             0x03c0</div><div class='add'>+#define regMPC_CRC_RESULT_A_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_CRC_RESULT_R                                                                             0x03c1</div><div class='add'>+#define regMPC_CRC_RESULT_R_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_CRC_RESULT_G                                                                             0x03c2</div><div class='add'>+#define regMPC_CRC_RESULT_G_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_CRC_RESULT_B                                                                             0x03c3</div><div class='add'>+#define regMPC_CRC_RESULT_B_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_DWB0_MUX                                                                                 0x03c6</div><div class='add'>+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x17e1c</div><div class='add'>+#define regDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x0447</div><div class='add'>+#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       3</div><div class='add'>+#define regDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x0448</div><div class='add'>+#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      3</div><div class='add'>+#define regDC_PERFMON15_PERFCOUNTER_STATE                                                               0x0449</div><div class='add'>+#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      3</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CNTL                                                                    0x044a</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           3</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CNTL2                                                                   0x044b</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          3</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x044c</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x044d</div><div class='add'>+#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     3</div><div class='add'>+#define regDC_PERFMON15_PERFMON_HI                                                                      0x044e</div><div class='add'>+#define regDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             3</div><div class='add'>+#define regDC_PERFMON15_PERFMON_LOW                                                                     0x044f</div><div class='add'>+#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x00a8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x00a9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x00aa</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x00ab</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00ac</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00ad</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00ae</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00af</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00b0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00b1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00b2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00b3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00b4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00b5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00b6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00b7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00b8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00b9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ba</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00bb</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00bc</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00bd</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00be</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00bf</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00c0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00c1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00c2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00c3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00c4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00c5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00c6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00c7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00c8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00c9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00ca</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00cb</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00cc</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00cd</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00ce</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00cf</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00d0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00d1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00d2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00d3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00d4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00d5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00d6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00d7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00d8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00d9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00da</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00db</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00dc</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00dd</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00de</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00df</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00e0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00e1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00e2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00e3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00e4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00e5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00e6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00e7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00e8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00e9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00ea</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00eb</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00ec</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00ed</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00ee</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00ef</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00f0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00f1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00f2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00f3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00f4</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00f5</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00f6</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00f7</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00f8</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00f9</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00fa</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00fb</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00fc</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00fd</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00fe</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00ff</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec</div><div class='add'>+// base address: 0x178</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0106</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0107</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0108</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0109</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x010a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x010b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x010c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x010d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x010e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x010f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0110</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0111</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0112</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0113</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0114</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0115</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0116</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0117</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0118</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0119</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x011a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x011b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x011c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x011d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x011e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x011f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0120</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0121</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0122</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0123</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0124</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0125</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0126</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0127</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0128</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0129</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x012a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x012b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x012c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x012d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x012e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x012f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0130</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0131</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0132</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0133</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0134</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0135</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0136</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0137</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0138</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0139</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x013a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x013b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x013c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x013d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x013e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x013f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0140</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0141</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0142</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0143</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0144</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0145</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0146</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0147</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0148</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0149</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x014a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x014b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x014c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x014d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x014e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x014f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0150</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0151</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0152</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0153</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0154</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0155</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0156</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0157</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0158</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0159</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x015a</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x015b</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x015c</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x015d</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec</div><div class='add'>+// base address: 0x2f0</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0164</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0165</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0166</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0167</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0168</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0169</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x016a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x016b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x016c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x016d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x016e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x016f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0170</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0171</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0172</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0173</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0174</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0175</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0176</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0177</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0178</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0179</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x017a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x017b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x017c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x017d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x017e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x017f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0180</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0181</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0182</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0183</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0184</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0185</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0186</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0187</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0188</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0189</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x018a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x018b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x018c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x018d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x018e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x018f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0190</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0191</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0192</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0193</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0194</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0195</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0196</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0197</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0198</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0199</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x019a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x019b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x019c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x019d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x019e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x019f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01a0</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01a1</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01a2</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01a3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01a4</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01a5</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01a6</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01a7</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01a8</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01a9</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01aa</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01ab</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01ac</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01ad</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ae</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x01af</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01b0</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01b1</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01b2</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01b3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01b4</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01b5</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01b6</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01b7</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01b8</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01b9</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ba</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01bb</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec</div><div class='add'>+// base address: 0x468</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x01c2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x01c3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x01c4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x01c5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x01c6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x01c7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x01c8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x01c9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01ca</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01cb</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01cc</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01cd</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01ce</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01cf</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01d0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01d1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01d2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01d3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01d4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01d5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01d6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01d7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01d8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01d9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01da</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01db</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01dc</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01dd</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01de</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01df</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01e0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01e1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01e2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01e3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01e4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01e5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01e6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01e7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01e8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01e9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01ea</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01eb</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01ec</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ed</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ee</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ef</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01f0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01f1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01f2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01f3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01f4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01f5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01f6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01f7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01f8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01f9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01fa</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01fb</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01fc</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01fd</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01fe</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01ff</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0200</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0201</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0202</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0203</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0204</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0205</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0206</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0207</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0208</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0209</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x020a</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x020b</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x020c</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x020d</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x020e</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x020f</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0210</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0211</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0212</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0213</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0214</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0215</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0216</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0217</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0218</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0219</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04dd</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec</div><div class='add'>+// base address: 0x240</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x04e3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x04e4</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x04e5</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x04e6</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x04e7</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x04e8</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x04e9</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x04ea</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x04eb</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x04ec</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x04ed</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x04ee</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x04ef</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x04f0</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x04f1</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x04f2</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x04f3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x04f4</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x04f5</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x04f6</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x04f7</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x04f8</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x04f9</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x04fa</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x04fb</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x04fc</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x04fd</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x04fe</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x04ff</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0500</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0501</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0502</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0503</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0504</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0505</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0506</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0507</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0508</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0509</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x050a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x050b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x050c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x050d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x050e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x050f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0510</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0511</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0512</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0513</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0514</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0515</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0516</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0517</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0518</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0519</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x051a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x051b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x051c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x051d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x051e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x051f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0520</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0521</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0522</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0523</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0524</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0525</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0526</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0527</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0528</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0529</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x052a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x052b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x052c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x052d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x052e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x052f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0530</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0531</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0532</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0533</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0534</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0535</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0536</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0537</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0538</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0539</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x053a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x053b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x053c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x053d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x053e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x053f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0540</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0541</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0542</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0543</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0544</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0545</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0546</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0547</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0548</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0549</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x054a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x054b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x054c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x054d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x054e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x054f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0550</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0551</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0552</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0553</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0554</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0555</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0556</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0557</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0558</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0559</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x055a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x055b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x055c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x055d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x055e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x055f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0560</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0561</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0562</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0563</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0564</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0565</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0566</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0567</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0568</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0569</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x056a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x056b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x056c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x056d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec</div><div class='add'>+// base address: 0x480</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x0573</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0574</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0575</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0576</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x0577</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0578</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0579</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x057a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x057b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x057c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x057d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x057e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x057f</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0580</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0581</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0582</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0583</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0584</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0585</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0586</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0587</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0588</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0589</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x058a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x058b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x058c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x058d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x058e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x058f</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0590</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0591</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0592</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0593</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0594</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0595</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0596</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0597</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0598</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0599</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x059a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x059b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x059c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x059d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x059e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x059f</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05a0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05a1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05a2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05a3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05a4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05a5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05a6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05a7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05a8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05a9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05aa</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05ab</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ac</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ad</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ae</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05af</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05b0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05b1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05b2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05b3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05b4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05b5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05b6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05b7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05b8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05b9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05ba</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05bb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05bc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05bd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05be</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05bf</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x05c0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x05c1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x05c2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x05c3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x05c4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x05c5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x05c6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x05c7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x05c8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x05c9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x05ca</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x05cb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x05cc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x05cd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x05ce</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x05cf</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x05d0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x05d1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x05d2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x05d3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x05d4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x05d5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x05d6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x05d7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x05d8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x05d9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x05da</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x05db</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x05dc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x05dd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x05de</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x05df</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x05e0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x05e1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x05e2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x05e3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x05e4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x05e5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x05e6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x05e7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x05e8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x05e9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x05ea</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x05eb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x05ec</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x05ed</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x05ee</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x05ef</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x05f0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x05f1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x05f2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x05f3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x05f4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x05f5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x05f6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x05f7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x05f8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x05f9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x05fa</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x05fb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x05fc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x05fd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec</div><div class='add'>+// base address: 0x6c0</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0603</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0604</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0605</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0606</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0607</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0608</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0609</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x060a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x060b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x060c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x060d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x060e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x060f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0610</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0611</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0612</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0613</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0614</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0615</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0616</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0617</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0618</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0619</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x061a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x061b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x061c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x061d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x061e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x061f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0620</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0621</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0622</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0623</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0624</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0625</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0626</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0627</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0628</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0629</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x062a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x062b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x062c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x062d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x062e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x062f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0630</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0631</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0632</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0633</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0634</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0635</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0636</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0637</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0638</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0639</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x063a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x063b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x063c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x063d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x063e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x063f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0640</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0641</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0642</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x0643</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0644</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0645</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0646</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0647</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0648</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0649</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x064a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x064b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x064c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x064d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x064e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x064f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0650</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0651</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0652</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0653</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0654</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0655</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0656</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0657</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0658</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0659</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x065a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x065b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x065c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x065d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x065e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x065f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0660</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0661</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0662</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0663</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0664</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0665</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0666</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0667</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0668</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0669</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x066a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x066b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x066c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x066d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x066e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x066f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0670</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0671</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0672</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0673</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0674</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0675</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0676</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0677</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0678</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0679</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x067a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x067b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x067c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x067d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x067e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x067f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0680</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0681</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0682</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0683</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0684</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0685</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0686</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0687</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0688</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0689</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x068a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x068b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x068c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x068d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPC_OUT0_MUX                                                                                 0x03d8</div><div class='add'>+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x03d9</div><div class='add'>+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x03da</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x03db</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT1_MUX                                                                                 0x03dc</div><div class='add'>+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x03dd</div><div class='add'>+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x03de</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x03df</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT2_MUX                                                                                 0x03e0</div><div class='add'>+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x03e1</div><div class='add'>+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x03e2</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x03e3</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT3_MUX                                                                                 0x03e4</div><div class='add'>+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x03e5</div><div class='add'>+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x03e6</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x03e7</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x03f0</div><div class='add'>+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT0_CSC_MODE                                                                            0x03f1</div><div class='add'>+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x03f2</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x03f3</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x03f4</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x03f5</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x03f6</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x03f7</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x03f8</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x03f9</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x03fa</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x03fb</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x03fc</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x03fd</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_MODE                                                                            0x03fe</div><div class='add'>+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x03ff</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x0400</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x0401</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x0402</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x0403</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x0404</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x0405</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0406</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0407</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0408</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0409</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x040a</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_MODE                                                                            0x040b</div><div class='add'>+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x040c</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x040d</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x040e</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x040f</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x0410</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x0411</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x0412</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x0413</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x0414</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x0415</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0416</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0417</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_MODE                                                                            0x0418</div><div class='add'>+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0419</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x041a</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x041b</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x041c</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x041d</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x041e</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x041f</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x0420</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x0421</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x0422</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x0423</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x0424</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a</div><div class='add'>+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b</div><div class='add'>+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c</div><div class='add'>+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d</div><div class='add'>+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e</div><div class='add'>+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f</div><div class='add'>+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80</div><div class='add'>+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81</div><div class='add'>+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82</div><div class='add'>+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83</div><div class='add'>+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84</div><div class='add'>+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a</div><div class='add'>+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b</div><div class='add'>+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c</div><div class='add'>+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e</div><div class='add'>+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f</div><div class='add'>+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90</div><div class='add'>+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92</div><div class='add'>+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93</div><div class='add'>+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96</div><div class='add'>+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97</div><div class='add'>+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98</div><div class='add'>+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6</div><div class='add'>+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm1_dispdec</div><div class='add'>+// base address: 0x104</div><div class='add'>+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb</div><div class='add'>+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc</div><div class='add'>+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd</div><div class='add'>+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe</div><div class='add'>+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf</div><div class='add'>+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0</div><div class='add'>+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1</div><div class='add'>+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2</div><div class='add'>+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3</div><div class='add'>+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4</div><div class='add'>+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5</div><div class='add'>+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb</div><div class='add'>+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc</div><div class='add'>+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd</div><div class='add'>+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf</div><div class='add'>+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0</div><div class='add'>+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1</div><div class='add'>+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3</div><div class='add'>+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4</div><div class='add'>+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7</div><div class='add'>+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8</div><div class='add'>+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9</div><div class='add'>+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7</div><div class='add'>+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm2_dispdec</div><div class='add'>+// base address: 0x208</div><div class='add'>+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc</div><div class='add'>+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd</div><div class='add'>+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe</div><div class='add'>+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff</div><div class='add'>+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00</div><div class='add'>+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01</div><div class='add'>+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02</div><div class='add'>+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03</div><div class='add'>+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04</div><div class='add'>+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05</div><div class='add'>+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06</div><div class='add'>+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c</div><div class='add'>+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d</div><div class='add'>+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e</div><div class='add'>+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10</div><div class='add'>+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11</div><div class='add'>+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12</div><div class='add'>+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14</div><div class='add'>+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15</div><div class='add'>+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18</div><div class='add'>+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19</div><div class='add'>+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a</div><div class='add'>+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38</div><div class='add'>+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm3_dispdec</div><div class='add'>+// base address: 0x30c</div><div class='add'>+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d</div><div class='add'>+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e</div><div class='add'>+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f</div><div class='add'>+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40</div><div class='add'>+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41</div><div class='add'>+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42</div><div class='add'>+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43</div><div class='add'>+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44</div><div class='add'>+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45</div><div class='add'>+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46</div><div class='add'>+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47</div><div class='add'>+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d</div><div class='add'>+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e</div><div class='add'>+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f</div><div class='add'>+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51</div><div class='add'>+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52</div><div class='add'>+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53</div><div class='add'>+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55</div><div class='add'>+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56</div><div class='add'>+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59</div><div class='add'>+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a</div><div class='add'>+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b</div><div class='add'>+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79</div><div class='add'>+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDPG0_DPG_CONTROL                                                                             0x1854</div><div class='add'>+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855</div><div class='add'>+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856</div><div class='add'>+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857</div><div class='add'>+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858</div><div class='add'>+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859</div><div class='add'>+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a</div><div class='add'>+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG0_DPG_STATUS                                                                              0x185b</div><div class='add'>+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTA                                                                    0x185e</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTA_BASE_IDX                                                           2</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTR                                                                    0x185f</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTR_BASE_IDX                                                           2</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTG                                                                    0x1860</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTG_BASE_IDX                                                           2</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTB                                                                    0x1861</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTB_BASE_IDX                                                           2</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTC                                                                    0x1862</div><div class='add'>+#define regDPG0_OPP_PIPE_CRC_RESULTC_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f</div><div class='add'>+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT0_FMT_CONTROL                                                                             0x1840</div><div class='add'>+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841</div><div class='add'>+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845</div><div class='add'>+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846</div><div class='add'>+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847</div><div class='add'>+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT0_FMT_422_CONTROL                                                                         0x1849</div><div class='add'>+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c</div><div class='add'>+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regDPG1_DPG_CONTROL                                                                             0x18ae</div><div class='add'>+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af</div><div class='add'>+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0</div><div class='add'>+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1</div><div class='add'>+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2</div><div class='add'>+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3</div><div class='add'>+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4</div><div class='add'>+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG1_DPG_STATUS                                                                              0x18b5</div><div class='add'>+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTA                                                                    0x18b8</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTA_BASE_IDX                                                           2</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTR                                                                    0x18b9</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTR_BASE_IDX                                                           2</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTG                                                                    0x18ba</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTG_BASE_IDX                                                           2</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTB                                                                    0x18bb</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTB_BASE_IDX                                                           2</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTC                                                                    0x18bc</div><div class='add'>+#define regDPG1_OPP_PIPE_CRC_RESULTC_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899</div><div class='add'>+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT1_FMT_CONTROL                                                                             0x189a</div><div class='add'>+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b</div><div class='add'>+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f</div><div class='add'>+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0</div><div class='add'>+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1</div><div class='add'>+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3</div><div class='add'>+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6</div><div class='add'>+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regDPG2_DPG_CONTROL                                                                             0x1908</div><div class='add'>+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909</div><div class='add'>+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a</div><div class='add'>+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b</div><div class='add'>+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c</div><div class='add'>+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d</div><div class='add'>+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e</div><div class='add'>+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG2_DPG_STATUS                                                                              0x190f</div><div class='add'>+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTA                                                                    0x1912</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTA_BASE_IDX                                                           2</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTR                                                                    0x1913</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTR_BASE_IDX                                                           2</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTG                                                                    0x1914</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTG_BASE_IDX                                                           2</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTB                                                                    0x1915</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTB_BASE_IDX                                                           2</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTC                                                                    0x1916</div><div class='add'>+#define regDPG2_OPP_PIPE_CRC_RESULTC_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3</div><div class='add'>+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT2_FMT_CONTROL                                                                             0x18f4</div><div class='add'>+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5</div><div class='add'>+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9</div><div class='add'>+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa</div><div class='add'>+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb</div><div class='add'>+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd</div><div class='add'>+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940</div><div class='add'>+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regDPG3_DPG_CONTROL                                                                             0x1962</div><div class='add'>+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963</div><div class='add'>+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964</div><div class='add'>+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965</div><div class='add'>+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966</div><div class='add'>+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967</div><div class='add'>+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968</div><div class='add'>+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG3_DPG_STATUS                                                                              0x1969</div><div class='add'>+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTA                                                                    0x196c</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTA_BASE_IDX                                                           2</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTR                                                                    0x196d</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTR_BASE_IDX                                                           2</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTG                                                                    0x196e</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTG_BASE_IDX                                                           2</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTB                                                                    0x196f</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTB_BASE_IDX                                                           2</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTC                                                                    0x1970</div><div class='add'>+#define regDPG3_OPP_PIPE_CRC_RESULTC_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d</div><div class='add'>+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT3_FMT_CONTROL                                                                             0x194e</div><div class='add'>+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f</div><div class='add'>+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953</div><div class='add'>+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954</div><div class='add'>+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955</div><div class='add'>+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT3_FMT_422_CONTROL                                                                         0x1957</div><div class='add'>+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a</div><div class='add'>+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64</div><div class='add'>+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm1_dispdec</div><div class='add'>+// base address: 0x4</div><div class='add'>+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65</div><div class='add'>+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm2_dispdec</div><div class='add'>+// base address: 0x8</div><div class='add'>+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66</div><div class='add'>+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm3_dispdec</div><div class='add'>+// base address: 0xc</div><div class='add'>+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67</div><div class='add'>+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e</div><div class='add'>+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regOPP_ABM_CONTROL                                                                              0x1a60</div><div class='add'>+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x6af8</div><div class='add'>+#define regDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe</div><div class='add'>+#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf</div><div class='add'>+#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0</div><div class='add'>+#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4</div><div class='add'>+#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_HI                                                                      0x1ac5</div><div class='add'>+#define regDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6</div><div class='add'>+#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca</div><div class='add'>+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb</div><div class='add'>+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc</div><div class='add'>+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd</div><div class='add'>+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace</div><div class='add'>+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf</div><div class='add'>+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0</div><div class='add'>+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1</div><div class='add'>+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+#define regODM0_OPTC_UNDERFLOW_THRESHOLD                                                                0x1ad5</div><div class='add'>+#define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm1_dispdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada</div><div class='add'>+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb</div><div class='add'>+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc</div><div class='add'>+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add</div><div class='add'>+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade</div><div class='add'>+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf</div><div class='add'>+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0</div><div class='add'>+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1</div><div class='add'>+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+#define regODM1_OPTC_UNDERFLOW_THRESHOLD                                                                0x1ae5</div><div class='add'>+#define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm2_dispdec</div><div class='add'>+// base address: 0x80</div><div class='add'>+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea</div><div class='add'>+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb</div><div class='add'>+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec</div><div class='add'>+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed</div><div class='add'>+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee</div><div class='add'>+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef</div><div class='add'>+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0</div><div class='add'>+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1</div><div class='add'>+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+#define regODM2_OPTC_UNDERFLOW_THRESHOLD                                                                0x1af5</div><div class='add'>+#define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm3_dispdec</div><div class='add'>+// base address: 0xc0</div><div class='add'>+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa</div><div class='add'>+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb</div><div class='add'>+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc</div><div class='add'>+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd</div><div class='add'>+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe</div><div class='add'>+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff</div><div class='add'>+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00</div><div class='add'>+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01</div><div class='add'>+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+#define regODM3_OPTC_UNDERFLOW_THRESHOLD                                                                0x1b05</div><div class='add'>+#define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a</div><div class='add'>+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b</div><div class='add'>+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e</div><div class='add'>+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL                                                                0x1b34</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL2                                                               0x1b35</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b36</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b37</div><div class='add'>+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b38</div><div class='add'>+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b39</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b3a</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b3b</div><div class='add'>+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3c</div><div class='add'>+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3d</div><div class='add'>+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3e</div><div class='add'>+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3f</div><div class='add'>+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b41</div><div class='add'>+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_CONTROL                                                                             0x1b43</div><div class='add'>+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG0_OTG_DLPC_CONTROL                                                                        0x1b44</div><div class='add'>+#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b45</div><div class='add'>+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b46</div><div class='add'>+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_STATUS                                                                              0x1b49</div><div class='add'>+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a</div><div class='add'>+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_LONG_VBLANK_STATUS                                                                  0x1b4b</div><div class='add'>+#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4c</div><div class='add'>+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4d</div><div class='add'>+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4e</div><div class='add'>+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4f</div><div class='add'>+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b50</div><div class='add'>+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b51</div><div class='add'>+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b52</div><div class='add'>+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b53</div><div class='add'>+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b54</div><div class='add'>+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b55</div><div class='add'>+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b56</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b57</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b58</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b59</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b5a</div><div class='add'>+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5b</div><div class='add'>+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5c</div><div class='add'>+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5d</div><div class='add'>+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b5f</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b60</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b61</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b62</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b63</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b64</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b65</div><div class='add'>+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b66</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b67</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b68</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b69</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6a</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6b</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6c</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b6d</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b6e</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b6f</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b70</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b71</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b72</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b73</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b74</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b75</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b76</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b77</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1b78</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1b79</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1b7a</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7b</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1b7c</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1b7d</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1b7e</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7f</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b80</div><div class='add'>+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b81</div><div class='add'>+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b82</div><div class='add'>+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b83</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b84</div><div class='add'>+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b85</div><div class='add'>+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b86</div><div class='add'>+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b87</div><div class='add'>+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b88</div><div class='add'>+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b89</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8a</div><div class='add'>+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8b</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8c</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8d</div><div class='add'>+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8e</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b8f</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b90</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b91</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b92</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b93</div><div class='add'>+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b95</div><div class='add'>+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b96</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b97</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b98</div><div class='add'>+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b99</div><div class='add'>+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_DRR_CONTOL2                                                                         0x1b9a</div><div class='add'>+#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d</div><div class='add'>+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9e</div><div class='add'>+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9f</div><div class='add'>+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba0</div><div class='add'>+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg1_dispdec</div><div class='add'>+// base address: 0x200</div><div class='add'>+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa</div><div class='add'>+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab</div><div class='add'>+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae</div><div class='add'>+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL                                                                0x1bb4</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL2                                                               0x1bb5</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb6</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb7</div><div class='add'>+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb8</div><div class='add'>+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb9</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bba</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bbb</div><div class='add'>+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bbc</div><div class='add'>+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbd</div><div class='add'>+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbe</div><div class='add'>+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbf</div><div class='add'>+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bc1</div><div class='add'>+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_CONTROL                                                                             0x1bc3</div><div class='add'>+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG1_OTG_DLPC_CONTROL                                                                        0x1bc4</div><div class='add'>+#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc5</div><div class='add'>+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc6</div><div class='add'>+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_STATUS                                                                              0x1bc9</div><div class='add'>+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca</div><div class='add'>+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_LONG_VBLANK_STATUS                                                                  0x1bcb</div><div class='add'>+#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcc</div><div class='add'>+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcd</div><div class='add'>+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bce</div><div class='add'>+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bcf</div><div class='add'>+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bd0</div><div class='add'>+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd1</div><div class='add'>+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd2</div><div class='add'>+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd3</div><div class='add'>+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd4</div><div class='add'>+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd5</div><div class='add'>+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd6</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd7</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd8</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd9</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bda</div><div class='add'>+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bdb</div><div class='add'>+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdc</div><div class='add'>+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdd</div><div class='add'>+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1bdf</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be0</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be1</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be3</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be4</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be5</div><div class='add'>+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be6</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1be7</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1be8</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1be9</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bea</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1beb</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bec</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bed</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bee</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bef</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf0</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf1</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf2</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf3</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf4</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf5</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf6</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bf7</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1bf8</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1bf9</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1bfa</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1bfb</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1bfc</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1bfd</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1bfe</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1bff</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c00</div><div class='add'>+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c01</div><div class='add'>+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c02</div><div class='add'>+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c03</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c04</div><div class='add'>+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c05</div><div class='add'>+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c06</div><div class='add'>+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c07</div><div class='add'>+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c08</div><div class='add'>+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c09</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0a</div><div class='add'>+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0b</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0c</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0d</div><div class='add'>+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0e</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c0f</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c10</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c11</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c12</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c13</div><div class='add'>+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c15</div><div class='add'>+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c16</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c17</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c18</div><div class='add'>+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c19</div><div class='add'>+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_DRR_CONTOL2                                                                         0x1c1a</div><div class='add'>+#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d</div><div class='add'>+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1e</div><div class='add'>+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1f</div><div class='add'>+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c20</div><div class='add'>+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg2_dispdec</div><div class='add'>+// base address: 0x400</div><div class='add'>+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a</div><div class='add'>+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b</div><div class='add'>+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e</div><div class='add'>+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL                                                                0x1c34</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL2                                                               0x1c35</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c36</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c37</div><div class='add'>+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c38</div><div class='add'>+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c39</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c3a</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c3b</div><div class='add'>+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3c</div><div class='add'>+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3d</div><div class='add'>+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3e</div><div class='add'>+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3f</div><div class='add'>+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c41</div><div class='add'>+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_CONTROL                                                                             0x1c43</div><div class='add'>+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG2_OTG_DLPC_CONTROL                                                                        0x1c44</div><div class='add'>+#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c45</div><div class='add'>+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c46</div><div class='add'>+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_STATUS                                                                              0x1c49</div><div class='add'>+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a</div><div class='add'>+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_LONG_VBLANK_STATUS                                                                  0x1c4b</div><div class='add'>+#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4c</div><div class='add'>+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4d</div><div class='add'>+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4e</div><div class='add'>+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4f</div><div class='add'>+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c50</div><div class='add'>+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c51</div><div class='add'>+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c52</div><div class='add'>+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c53</div><div class='add'>+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c54</div><div class='add'>+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c55</div><div class='add'>+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c56</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c57</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c58</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c59</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c5a</div><div class='add'>+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5b</div><div class='add'>+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5c</div><div class='add'>+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5d</div><div class='add'>+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c5f</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c60</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c61</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c62</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c63</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c64</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c65</div><div class='add'>+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c66</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c67</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c68</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c69</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6a</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6b</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6c</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c6d</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c6e</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c6f</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c70</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c71</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c72</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c73</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c74</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c75</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c76</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c77</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1c78</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1c79</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1c7a</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7b</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1c7c</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1c7d</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1c7e</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7f</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c80</div><div class='add'>+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c81</div><div class='add'>+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c82</div><div class='add'>+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c83</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c84</div><div class='add'>+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c85</div><div class='add'>+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c86</div><div class='add'>+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c87</div><div class='add'>+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c88</div><div class='add'>+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c89</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8a</div><div class='add'>+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8b</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8c</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8d</div><div class='add'>+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8e</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c8f</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c90</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c91</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c92</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c93</div><div class='add'>+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c95</div><div class='add'>+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c96</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c97</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c98</div><div class='add'>+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c99</div><div class='add'>+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_DRR_CONTOL2                                                                         0x1c9a</div><div class='add'>+#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d</div><div class='add'>+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9e</div><div class='add'>+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9f</div><div class='add'>+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca0</div><div class='add'>+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg3_dispdec</div><div class='add'>+// base address: 0x600</div><div class='add'>+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa</div><div class='add'>+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab</div><div class='add'>+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae</div><div class='add'>+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL                                                                0x1cb4</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL2                                                               0x1cb5</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb6</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb7</div><div class='add'>+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb8</div><div class='add'>+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb9</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cba</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cbb</div><div class='add'>+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cbc</div><div class='add'>+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbd</div><div class='add'>+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbe</div><div class='add'>+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbf</div><div class='add'>+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cc1</div><div class='add'>+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_CONTROL                                                                             0x1cc3</div><div class='add'>+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG3_OTG_DLPC_CONTROL                                                                        0x1cc4</div><div class='add'>+#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc5</div><div class='add'>+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc6</div><div class='add'>+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_STATUS                                                                              0x1cc9</div><div class='add'>+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca</div><div class='add'>+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_LONG_VBLANK_STATUS                                                                  0x1ccb</div><div class='add'>+#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccc</div><div class='add'>+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccd</div><div class='add'>+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1cce</div><div class='add'>+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1ccf</div><div class='add'>+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1cd0</div><div class='add'>+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd1</div><div class='add'>+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd2</div><div class='add'>+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd3</div><div class='add'>+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd4</div><div class='add'>+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd5</div><div class='add'>+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd6</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd7</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd8</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd9</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cda</div><div class='add'>+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cdb</div><div class='add'>+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdc</div><div class='add'>+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdd</div><div class='add'>+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1cdf</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce0</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce1</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce3</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce4</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce5</div><div class='add'>+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce6</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ce7</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ce8</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ce9</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1cea</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1ceb</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cec</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1ced</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cee</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cef</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf0</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf1</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf2</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf3</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf4</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf5</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf6</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cf7</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1cf8</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1cf9</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1cfa</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1cfb</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1cfc</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1cfd</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1cfe</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1cff</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d00</div><div class='add'>+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d01</div><div class='add'>+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d02</div><div class='add'>+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d03</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d04</div><div class='add'>+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d05</div><div class='add'>+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d06</div><div class='add'>+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d07</div><div class='add'>+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d08</div><div class='add'>+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d09</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0a</div><div class='add'>+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0b</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0c</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0d</div><div class='add'>+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0e</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d0f</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d10</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d11</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d12</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d13</div><div class='add'>+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d15</div><div class='add'>+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d16</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d17</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d18</div><div class='add'>+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d19</div><div class='add'>+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_DRR_CONTOL2                                                                         0x1d1a</div><div class='add'>+#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d</div><div class='add'>+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1e</div><div class='add'>+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1f</div><div class='add'>+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d20</div><div class='add'>+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc320_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_R32                                                                 0x1dd2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_G32                                                                 0x1dd3</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_B32                                                                 0x1dd4</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_C32                                                                 0x1dd5</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_AES                                                                 0x1dd6</div><div class='add'>+#define regOTG_CRC320_OTG_CRC0_DATA_AES_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_R32                                                                 0x1dd7</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_G32                                                                 0x1dd8</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_B32                                                                 0x1dd9</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_C32                                                                 0x1dda</div><div class='add'>+#define regOTG_CRC320_OTG_CRC1_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_R32                                                                 0x1ddb</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_G32                                                                 0x1ddc</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_B32                                                                 0x1ddd</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_C32                                                                 0x1dde</div><div class='add'>+#define regOTG_CRC320_OTG_CRC2_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_R32                                                                 0x1ddf</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_G32                                                                 0x1de0</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_B32                                                                 0x1de1</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_C32                                                                 0x1de2</div><div class='add'>+#define regOTG_CRC320_OTG_CRC3_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc321_dispdec</div><div class='add'>+// base address: 0x50</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_R32                                                                 0x1de6</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_G32                                                                 0x1de7</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_B32                                                                 0x1de8</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_C32                                                                 0x1de9</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_AES                                                                 0x1dea</div><div class='add'>+#define regOTG_CRC321_OTG_CRC0_DATA_AES_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_R32                                                                 0x1deb</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_G32                                                                 0x1dec</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_B32                                                                 0x1ded</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_C32                                                                 0x1dee</div><div class='add'>+#define regOTG_CRC321_OTG_CRC1_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_R32                                                                 0x1def</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_G32                                                                 0x1df0</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_B32                                                                 0x1df1</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_C32                                                                 0x1df2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC2_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_R32                                                                 0x1df3</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_G32                                                                 0x1df4</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_B32                                                                 0x1df5</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_C32                                                                 0x1df6</div><div class='add'>+#define regOTG_CRC321_OTG_CRC3_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc322_dispdec</div><div class='add'>+// base address: 0xa0</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_R32                                                                 0x1dfa</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_G32                                                                 0x1dfb</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_B32                                                                 0x1dfc</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_C32                                                                 0x1dfd</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_AES                                                                 0x1dfe</div><div class='add'>+#define regOTG_CRC322_OTG_CRC0_DATA_AES_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_R32                                                                 0x1dff</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_G32                                                                 0x1e00</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_B32                                                                 0x1e01</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_C32                                                                 0x1e02</div><div class='add'>+#define regOTG_CRC322_OTG_CRC1_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_R32                                                                 0x1e03</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_G32                                                                 0x1e04</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_B32                                                                 0x1e05</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_C32                                                                 0x1e06</div><div class='add'>+#define regOTG_CRC322_OTG_CRC2_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_R32                                                                 0x1e07</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_G32                                                                 0x1e08</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_B32                                                                 0x1e09</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_C32                                                                 0x1e0a</div><div class='add'>+#define regOTG_CRC322_OTG_CRC3_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc323_dispdec</div><div class='add'>+// base address: 0xf0</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_R32                                                                 0x1e0e</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_G32                                                                 0x1e0f</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_B32                                                                 0x1e10</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_C32                                                                 0x1e11</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_AES                                                                 0x1e12</div><div class='add'>+#define regOTG_CRC323_OTG_CRC0_DATA_AES_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_R32                                                                 0x1e13</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_G32                                                                 0x1e14</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_B32                                                                 0x1e15</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_C32                                                                 0x1e16</div><div class='add'>+#define regOTG_CRC323_OTG_CRC1_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_R32                                                                 0x1e17</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_G32                                                                 0x1e18</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_B32                                                                 0x1e19</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_C32                                                                 0x1e1a</div><div class='add'>+#define regOTG_CRC323_OTG_CRC2_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_R32                                                                 0x1e1b</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_R32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_G32                                                                 0x1e1c</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_G32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_B32                                                                 0x1e1d</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_B32_BASE_IDX                                                        2</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_C32                                                                 0x1e1e</div><div class='add'>+#define regOTG_CRC323_OTG_CRC3_DATA_C32_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_optc_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regGSL_SOURCE_SELECT                                                                            0x1e2b</div><div class='add'>+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2</div><div class='add'>+#define regOPTC_DLPC_CONTROL                                                                            0x1e2c</div><div class='add'>+#define regOPTC_DLPC_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2d</div><div class='add'>+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regODM_MEM_PWR_CTRL                                                                             0x1e2e</div><div class='add'>+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2</div><div class='add'>+#define regODM_MEM_PWR_CTRL3                                                                            0x1e30</div><div class='add'>+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2</div><div class='add'>+#define regODM_MEM_PWR_STATUS                                                                           0x1e31</div><div class='add'>+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e32</div><div class='add'>+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x79a8</div><div class='add'>+#define regDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a</div><div class='add'>+#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b</div><div class='add'>+#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c</div><div class='add'>+#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70</div><div class='add'>+#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON17_PERFMON_HI                                                                      0x1e71</div><div class='add'>+#define regDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON17_PERFMON_LOW                                                                     0x1e72</div><div class='add'>+#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14</div><div class='add'>+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15</div><div class='add'>+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16</div><div class='add'>+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17</div><div class='add'>+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18</div><div class='add'>+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd1_dispdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c</div><div class='add'>+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d</div><div class='add'>+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e</div><div class='add'>+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f</div><div class='add'>+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20</div><div class='add'>+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd2_dispdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24</div><div class='add'>+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25</div><div class='add'>+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26</div><div class='add'>+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27</div><div class='add'>+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28</div><div class='add'>+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd3_dispdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c</div><div class='add'>+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d</div><div class='add'>+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e</div><div class='add'>+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f</div><div class='add'>+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30</div><div class='add'>+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd4_dispdec</div><div class='add'>+// base address: 0x80</div><div class='add'>+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34</div><div class='add'>+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35</div><div class='add'>+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36</div><div class='add'>+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37</div><div class='add'>+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38</div><div class='add'>+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDP0_DP_LINK_CNTL                                                                             0x211e</div><div class='add'>+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_PIXEL_FORMAT                                                                          0x211f</div><div class='add'>+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x2120</div><div class='add'>+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_CONFIG                                                                                0x2121</div><div class='add'>+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x2122</div><div class='add'>+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_STEER_FIFO                                                                            0x2123</div><div class='add'>+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_MSA_MISC                                                                              0x2124</div><div class='add'>+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x2125</div><div class='add'>+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_VID_TIMING                                                                            0x2126</div><div class='add'>+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_VID_N                                                                                 0x2127</div><div class='add'>+#define regDP0_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP0_DP_VID_M                                                                                 0x2128</div><div class='add'>+#define regDP0_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2129</div><div class='add'>+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x212a</div><div class='add'>+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_VID_MSA_VBID                                                                          0x212b</div><div class='add'>+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x212c</div><div class='add'>+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_DPHY_CNTL                                                                             0x212d</div><div class='add'>+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x212e</div><div class='add'>+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_SYM0                                                                             0x212f</div><div class='add'>+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_SYM1                                                                             0x2130</div><div class='add'>+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_SYM2                                                                             0x2131</div><div class='add'>+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x2132</div><div class='add'>+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x2133</div><div class='add'>+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x2134</div><div class='add'>+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_CONTROL0                                                                     0x2135</div><div class='add'>+#define regDP0_DP_DPHY_CRC_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_CONTROL1                                                                     0x2136</div><div class='add'>+#define regDP0_DP_DPHY_CRC_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT0                                                                      0x2137</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT0_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT1                                                                      0x2138</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT1_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_STATUS                                                                       0x2139</div><div class='add'>+#define regDP0_DP_DPHY_CRC_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x213a</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x213b</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT2                                                                      0x213c</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT2_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT3                                                                      0x213d</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT3_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_SEC_CNTL                                                                              0x2141</div><div class='add'>+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_SEC_CNTL1                                                                             0x2142</div><div class='add'>+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING1                                                                          0x2143</div><div class='add'>+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING2                                                                          0x2144</div><div class='add'>+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING3                                                                          0x2145</div><div class='add'>+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING4                                                                          0x2146</div><div class='add'>+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_AUD_N                                                                             0x2147</div><div class='add'>+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2148</div><div class='add'>+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_SEC_AUD_M                                                                             0x2149</div><div class='add'>+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x214a</div><div class='add'>+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x214b</div><div class='add'>+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x214c</div><div class='add'>+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x214d</div><div class='add'>+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x214f</div><div class='add'>+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_SAT0                                                                              0x2150</div><div class='add'>+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSE_SAT1                                                                              0x2151</div><div class='add'>+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSE_SAT2                                                                              0x2152</div><div class='add'>+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x2153</div><div class='add'>+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x2154</div><div class='add'>+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x2155</div><div class='add'>+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x215a</div><div class='add'>+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x215b</div><div class='add'>+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x215d</div><div class='add'>+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x215e</div><div class='add'>+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x215f</div><div class='add'>+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPIA_SPARE                                                                            0x2160</div><div class='add'>+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x2162</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x2163</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x2164</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x2165</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSO_CNTL                                                                              0x2166</div><div class='add'>+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSO_CNTL1                                                                             0x2167</div><div class='add'>+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DSC_CNTL                                                                              0x2168</div><div class='add'>+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_SEC_CNTL2                                                                             0x2169</div><div class='add'>+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL3                                                                             0x216a</div><div class='add'>+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL4                                                                             0x216b</div><div class='add'>+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL5                                                                             0x216c</div><div class='add'>+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL6                                                                             0x216d</div><div class='add'>+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL7                                                                             0x216e</div><div class='add'>+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DB_CNTL                                                                               0x216f</div><div class='add'>+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP0_DP_MSA_VBID_MISC                                                                         0x2170</div><div class='add'>+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x2171</div><div class='add'>+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_ALPM_CNTL                                                                             0x2173</div><div class='add'>+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_GSP8_CNTL                                                                             0x2174</div><div class='add'>+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_GSP9_CNTL                                                                             0x2175</div><div class='add'>+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_GSP10_CNTL                                                                            0x2176</div><div class='add'>+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_GSP11_CNTL                                                                            0x2177</div><div class='add'>+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2178</div><div class='add'>+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2179</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x217a</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x217b</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x217c</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x217d</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x217e</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x217f</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2180</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2181</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2182</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDIG0_DIG_FE_CNTL                                                                             0x2093</div><div class='add'>+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG0_DIG_FE_CLK_CNTL                                                                         0x2094</div><div class='add'>+#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG0_DIG_FE_EN_CNTL                                                                          0x2095</div><div class='add'>+#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2096</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x2097</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x2098</div><div class='add'>+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_DIG_TEST_PATTERN                                                                        0x2099</div><div class='add'>+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x209a</div><div class='add'>+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x209b</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x209c</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x209d</div><div class='add'>+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_CONTROL                                                                            0x209e</div><div class='add'>+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG0_HDMI_STATUS                                                                             0x209f</div><div class='add'>+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x20a0</div><div class='add'>+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x20a1</div><div class='add'>+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x20a2</div><div class='add'>+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x20a3</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x20a4</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x20a5</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x20a6</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20a7</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GC                                                                                 0x20a8</div><div class='add'>+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x20a9</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20aa</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20ab</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20ac</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20ad</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20ae</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20af</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20b0</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20b1</div><div class='add'>+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG0_HDMI_ACR_32_0                                                                           0x20b2</div><div class='add'>+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_32_1                                                                           0x20b3</div><div class='add'>+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_44_0                                                                           0x20b4</div><div class='add'>+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_44_1                                                                           0x20b5</div><div class='add'>+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_48_0                                                                           0x20b6</div><div class='add'>+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_48_1                                                                           0x20b7</div><div class='add'>+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20b8</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20b9</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_AFMT_CNTL                                                                               0x20ba</div><div class='add'>+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG0_DIG_BE_CLK_CNTL                                                                         0x20bb</div><div class='add'>+#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG0_DIG_BE_CNTL                                                                             0x20bc</div><div class='add'>+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20bd</div><div class='add'>+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_TMDS_CNTL                                                                               0x20e4</div><div class='add'>+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20e5</div><div class='add'>+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20e6</div><div class='add'>+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20e7</div><div class='add'>+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20e8</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20e9</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG0_TMDS_CTL_BITS                                                                           0x20eb</div><div class='add'>+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20ec</div><div class='add'>+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20ed</div><div class='add'>+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20ee</div><div class='add'>+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20ef</div><div class='add'>+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG0_DIG_VERSION                                                                             0x20f1</div><div class='add'>+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp1_dispdec</div><div class='add'>+// base address: 0x490</div><div class='add'>+#define regDP1_DP_LINK_CNTL                                                                             0x2242</div><div class='add'>+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2243</div><div class='add'>+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x2244</div><div class='add'>+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_CONFIG                                                                                0x2245</div><div class='add'>+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x2246</div><div class='add'>+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_STEER_FIFO                                                                            0x2247</div><div class='add'>+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_MSA_MISC                                                                              0x2248</div><div class='add'>+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x2249</div><div class='add'>+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_VID_TIMING                                                                            0x224a</div><div class='add'>+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_VID_N                                                                                 0x224b</div><div class='add'>+#define regDP1_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP1_DP_VID_M                                                                                 0x224c</div><div class='add'>+#define regDP1_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x224d</div><div class='add'>+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x224e</div><div class='add'>+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_VID_MSA_VBID                                                                          0x224f</div><div class='add'>+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2250</div><div class='add'>+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_DPHY_CNTL                                                                             0x2251</div><div class='add'>+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2252</div><div class='add'>+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_SYM0                                                                             0x2253</div><div class='add'>+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_SYM1                                                                             0x2254</div><div class='add'>+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_SYM2                                                                             0x2255</div><div class='add'>+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x2256</div><div class='add'>+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x2257</div><div class='add'>+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x2258</div><div class='add'>+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_CONTROL0                                                                     0x2259</div><div class='add'>+#define regDP1_DP_DPHY_CRC_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_CONTROL1                                                                     0x225a</div><div class='add'>+#define regDP1_DP_DPHY_CRC_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT0                                                                      0x225b</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT0_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT1                                                                      0x225c</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT1_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_STATUS                                                                       0x225d</div><div class='add'>+#define regDP1_DP_DPHY_CRC_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x225e</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x225f</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT2                                                                      0x2260</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT2_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT3                                                                      0x2261</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT3_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_SEC_CNTL                                                                              0x2265</div><div class='add'>+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_SEC_CNTL1                                                                             0x2266</div><div class='add'>+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING1                                                                          0x2267</div><div class='add'>+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING2                                                                          0x2268</div><div class='add'>+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING3                                                                          0x2269</div><div class='add'>+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING4                                                                          0x226a</div><div class='add'>+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_AUD_N                                                                             0x226b</div><div class='add'>+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x226c</div><div class='add'>+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_SEC_AUD_M                                                                             0x226d</div><div class='add'>+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x226e</div><div class='add'>+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x226f</div><div class='add'>+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2270</div><div class='add'>+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2271</div><div class='add'>+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2273</div><div class='add'>+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_SAT0                                                                              0x2274</div><div class='add'>+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSE_SAT1                                                                              0x2275</div><div class='add'>+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSE_SAT2                                                                              0x2276</div><div class='add'>+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x2277</div><div class='add'>+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x2278</div><div class='add'>+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x2279</div><div class='add'>+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x227e</div><div class='add'>+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x227f</div><div class='add'>+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2281</div><div class='add'>+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2282</div><div class='add'>+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2283</div><div class='add'>+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPIA_SPARE                                                                            0x2284</div><div class='add'>+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x2286</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x2287</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x2288</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x2289</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSO_CNTL                                                                              0x228a</div><div class='add'>+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSO_CNTL1                                                                             0x228b</div><div class='add'>+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DSC_CNTL                                                                              0x228c</div><div class='add'>+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_SEC_CNTL2                                                                             0x228d</div><div class='add'>+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL3                                                                             0x228e</div><div class='add'>+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL4                                                                             0x228f</div><div class='add'>+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL5                                                                             0x2290</div><div class='add'>+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL6                                                                             0x2291</div><div class='add'>+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL7                                                                             0x2292</div><div class='add'>+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DB_CNTL                                                                               0x2293</div><div class='add'>+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP1_DP_MSA_VBID_MISC                                                                         0x2294</div><div class='add'>+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x2295</div><div class='add'>+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_ALPM_CNTL                                                                             0x2297</div><div class='add'>+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_GSP8_CNTL                                                                             0x2298</div><div class='add'>+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_GSP9_CNTL                                                                             0x2299</div><div class='add'>+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_GSP10_CNTL                                                                            0x229a</div><div class='add'>+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_GSP11_CNTL                                                                            0x229b</div><div class='add'>+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x229c</div><div class='add'>+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x229d</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x229e</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x229f</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x22a0</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x22a1</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x22a2</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x22a3</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x22a4</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x22a5</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x22a6</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_dispdec</div><div class='add'>+// base address: 0x490</div><div class='add'>+#define regDIG1_DIG_FE_CNTL                                                                             0x21b7</div><div class='add'>+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG1_DIG_FE_CLK_CNTL                                                                         0x21b8</div><div class='add'>+#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG1_DIG_FE_EN_CNTL                                                                          0x21b9</div><div class='add'>+#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x21ba</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x21bb</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x21bc</div><div class='add'>+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_DIG_TEST_PATTERN                                                                        0x21bd</div><div class='add'>+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x21be</div><div class='add'>+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x21bf</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x21c0</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x21c1</div><div class='add'>+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_CONTROL                                                                            0x21c2</div><div class='add'>+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG1_HDMI_STATUS                                                                             0x21c3</div><div class='add'>+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x21c4</div><div class='add'>+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x21c5</div><div class='add'>+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x21c6</div><div class='add'>+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x21c7</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x21c8</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x21c9</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x21ca</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21cb</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GC                                                                                 0x21cc</div><div class='add'>+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x21cd</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21ce</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21cf</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21d0</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21d1</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21d2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21d3</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21d4</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21d5</div><div class='add'>+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG1_HDMI_ACR_32_0                                                                           0x21d6</div><div class='add'>+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_32_1                                                                           0x21d7</div><div class='add'>+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_44_0                                                                           0x21d8</div><div class='add'>+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_44_1                                                                           0x21d9</div><div class='add'>+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_48_0                                                                           0x21da</div><div class='add'>+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_48_1                                                                           0x21db</div><div class='add'>+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21dc</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21dd</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_AFMT_CNTL                                                                               0x21de</div><div class='add'>+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG1_DIG_BE_CLK_CNTL                                                                         0x21df</div><div class='add'>+#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG1_DIG_BE_CNTL                                                                             0x21e0</div><div class='add'>+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21e1</div><div class='add'>+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_TMDS_CNTL                                                                               0x2208</div><div class='add'>+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x2209</div><div class='add'>+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x220a</div><div class='add'>+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x220b</div><div class='add'>+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x220c</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x220d</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG1_TMDS_CTL_BITS                                                                           0x220f</div><div class='add'>+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x2210</div><div class='add'>+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2211</div><div class='add'>+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x2212</div><div class='add'>+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x2213</div><div class='add'>+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG1_DIG_VERSION                                                                             0x2215</div><div class='add'>+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp2_dispdec</div><div class='add'>+// base address: 0x920</div><div class='add'>+#define regDP2_DP_LINK_CNTL                                                                             0x2366</div><div class='add'>+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2367</div><div class='add'>+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x2368</div><div class='add'>+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_CONFIG                                                                                0x2369</div><div class='add'>+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x236a</div><div class='add'>+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_STEER_FIFO                                                                            0x236b</div><div class='add'>+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_MSA_MISC                                                                              0x236c</div><div class='add'>+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x236d</div><div class='add'>+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_VID_TIMING                                                                            0x236e</div><div class='add'>+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_VID_N                                                                                 0x236f</div><div class='add'>+#define regDP2_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP2_DP_VID_M                                                                                 0x2370</div><div class='add'>+#define regDP2_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2371</div><div class='add'>+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2372</div><div class='add'>+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_VID_MSA_VBID                                                                          0x2373</div><div class='add'>+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2374</div><div class='add'>+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_DPHY_CNTL                                                                             0x2375</div><div class='add'>+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2376</div><div class='add'>+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_SYM0                                                                             0x2377</div><div class='add'>+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_SYM1                                                                             0x2378</div><div class='add'>+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_SYM2                                                                             0x2379</div><div class='add'>+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x237a</div><div class='add'>+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x237b</div><div class='add'>+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x237c</div><div class='add'>+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_CONTROL0                                                                     0x237d</div><div class='add'>+#define regDP2_DP_DPHY_CRC_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_CONTROL1                                                                     0x237e</div><div class='add'>+#define regDP2_DP_DPHY_CRC_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT0                                                                      0x237f</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT0_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT1                                                                      0x2380</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT1_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_STATUS                                                                       0x2381</div><div class='add'>+#define regDP2_DP_DPHY_CRC_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2382</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2383</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT2                                                                      0x2384</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT2_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT3                                                                      0x2385</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT3_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_SEC_CNTL                                                                              0x2389</div><div class='add'>+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_SEC_CNTL1                                                                             0x238a</div><div class='add'>+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING1                                                                          0x238b</div><div class='add'>+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING2                                                                          0x238c</div><div class='add'>+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING3                                                                          0x238d</div><div class='add'>+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING4                                                                          0x238e</div><div class='add'>+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_AUD_N                                                                             0x238f</div><div class='add'>+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2390</div><div class='add'>+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_SEC_AUD_M                                                                             0x2391</div><div class='add'>+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2392</div><div class='add'>+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2393</div><div class='add'>+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2394</div><div class='add'>+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2395</div><div class='add'>+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2397</div><div class='add'>+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_SAT0                                                                              0x2398</div><div class='add'>+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSE_SAT1                                                                              0x2399</div><div class='add'>+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSE_SAT2                                                                              0x239a</div><div class='add'>+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x239b</div><div class='add'>+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x239c</div><div class='add'>+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x239d</div><div class='add'>+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x23a2</div><div class='add'>+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x23a3</div><div class='add'>+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x23a5</div><div class='add'>+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x23a6</div><div class='add'>+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x23a7</div><div class='add'>+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPIA_SPARE                                                                            0x23a8</div><div class='add'>+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x23aa</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x23ab</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x23ac</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x23ad</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSO_CNTL                                                                              0x23ae</div><div class='add'>+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSO_CNTL1                                                                             0x23af</div><div class='add'>+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DSC_CNTL                                                                              0x23b0</div><div class='add'>+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_SEC_CNTL2                                                                             0x23b1</div><div class='add'>+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL3                                                                             0x23b2</div><div class='add'>+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL4                                                                             0x23b3</div><div class='add'>+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL5                                                                             0x23b4</div><div class='add'>+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL6                                                                             0x23b5</div><div class='add'>+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL7                                                                             0x23b6</div><div class='add'>+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DB_CNTL                                                                               0x23b7</div><div class='add'>+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP2_DP_MSA_VBID_MISC                                                                         0x23b8</div><div class='add'>+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x23b9</div><div class='add'>+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_ALPM_CNTL                                                                             0x23bb</div><div class='add'>+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_GSP8_CNTL                                                                             0x23bc</div><div class='add'>+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_GSP9_CNTL                                                                             0x23bd</div><div class='add'>+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_GSP10_CNTL                                                                            0x23be</div><div class='add'>+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_GSP11_CNTL                                                                            0x23bf</div><div class='add'>+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x23c0</div><div class='add'>+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x23c1</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x23c2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x23c3</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x23c4</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x23c5</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x23c6</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x23c7</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x23c8</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x23c9</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x23ca</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_dispdec</div><div class='add'>+// base address: 0x920</div><div class='add'>+#define regDIG2_DIG_FE_CNTL                                                                             0x22db</div><div class='add'>+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG2_DIG_FE_CLK_CNTL                                                                         0x22dc</div><div class='add'>+#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG2_DIG_FE_EN_CNTL                                                                          0x22dd</div><div class='add'>+#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x22de</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x22df</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x22e0</div><div class='add'>+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_DIG_TEST_PATTERN                                                                        0x22e1</div><div class='add'>+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x22e2</div><div class='add'>+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x22e3</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x22e4</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x22e5</div><div class='add'>+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_CONTROL                                                                            0x22e6</div><div class='add'>+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG2_HDMI_STATUS                                                                             0x22e7</div><div class='add'>+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x22e8</div><div class='add'>+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x22e9</div><div class='add'>+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x22ea</div><div class='add'>+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x22eb</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x22ec</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x22ed</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x22ee</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22ef</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GC                                                                                 0x22f0</div><div class='add'>+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x22f1</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22f2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22f3</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22f4</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22f5</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22f6</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22f7</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22f8</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22f9</div><div class='add'>+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG2_HDMI_ACR_32_0                                                                           0x22fa</div><div class='add'>+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_32_1                                                                           0x22fb</div><div class='add'>+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_44_0                                                                           0x22fc</div><div class='add'>+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_44_1                                                                           0x22fd</div><div class='add'>+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_48_0                                                                           0x22fe</div><div class='add'>+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ff</div><div class='add'>+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x2300</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x2301</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_AFMT_CNTL                                                                               0x2302</div><div class='add'>+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG2_DIG_BE_CLK_CNTL                                                                         0x2303</div><div class='add'>+#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG2_DIG_BE_CNTL                                                                             0x2304</div><div class='add'>+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x2305</div><div class='add'>+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_TMDS_CNTL                                                                               0x232c</div><div class='add'>+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x232d</div><div class='add'>+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x232e</div><div class='add'>+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x232f</div><div class='add'>+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2330</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2331</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG2_TMDS_CTL_BITS                                                                           0x2333</div><div class='add'>+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x2334</div><div class='add'>+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2335</div><div class='add'>+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x2336</div><div class='add'>+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x2337</div><div class='add'>+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG2_DIG_VERSION                                                                             0x2339</div><div class='add'>+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp3_dispdec</div><div class='add'>+// base address: 0xdb0</div><div class='add'>+#define regDP3_DP_LINK_CNTL                                                                             0x248a</div><div class='add'>+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_PIXEL_FORMAT                                                                          0x248b</div><div class='add'>+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x248c</div><div class='add'>+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_CONFIG                                                                                0x248d</div><div class='add'>+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x248e</div><div class='add'>+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_STEER_FIFO                                                                            0x248f</div><div class='add'>+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_MSA_MISC                                                                              0x2490</div><div class='add'>+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x2491</div><div class='add'>+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_VID_TIMING                                                                            0x2492</div><div class='add'>+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_VID_N                                                                                 0x2493</div><div class='add'>+#define regDP3_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP3_DP_VID_M                                                                                 0x2494</div><div class='add'>+#define regDP3_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2495</div><div class='add'>+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2496</div><div class='add'>+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_VID_MSA_VBID                                                                          0x2497</div><div class='add'>+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2498</div><div class='add'>+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_DPHY_CNTL                                                                             0x2499</div><div class='add'>+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x249a</div><div class='add'>+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_SYM0                                                                             0x249b</div><div class='add'>+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_SYM1                                                                             0x249c</div><div class='add'>+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_SYM2                                                                             0x249d</div><div class='add'>+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x249e</div><div class='add'>+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x249f</div><div class='add'>+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x24a0</div><div class='add'>+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_CONTROL0                                                                     0x24a1</div><div class='add'>+#define regDP3_DP_DPHY_CRC_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_CONTROL1                                                                     0x24a2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT0                                                                      0x24a3</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT0_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT1                                                                      0x24a4</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT1_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_STATUS                                                                       0x24a5</div><div class='add'>+#define regDP3_DP_DPHY_CRC_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x24a6</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x24a7</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT2                                                                      0x24a8</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT2_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT3                                                                      0x24a9</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT3_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_SEC_CNTL                                                                              0x24ad</div><div class='add'>+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_SEC_CNTL1                                                                             0x24ae</div><div class='add'>+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING1                                                                          0x24af</div><div class='add'>+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING2                                                                          0x24b0</div><div class='add'>+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING3                                                                          0x24b1</div><div class='add'>+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING4                                                                          0x24b2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_AUD_N                                                                             0x24b3</div><div class='add'>+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x24b4</div><div class='add'>+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_SEC_AUD_M                                                                             0x24b5</div><div class='add'>+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x24b6</div><div class='add'>+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x24b7</div><div class='add'>+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x24b8</div><div class='add'>+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x24b9</div><div class='add'>+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x24bb</div><div class='add'>+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_SAT0                                                                              0x24bc</div><div class='add'>+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSE_SAT1                                                                              0x24bd</div><div class='add'>+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSE_SAT2                                                                              0x24be</div><div class='add'>+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x24bf</div><div class='add'>+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x24c0</div><div class='add'>+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x24c1</div><div class='add'>+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x24c6</div><div class='add'>+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x24c7</div><div class='add'>+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x24c9</div><div class='add'>+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x24ca</div><div class='add'>+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x24cb</div><div class='add'>+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPIA_SPARE                                                                            0x24cc</div><div class='add'>+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x24ce</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x24cf</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x24d0</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x24d1</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSO_CNTL                                                                              0x24d2</div><div class='add'>+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSO_CNTL1                                                                             0x24d3</div><div class='add'>+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DSC_CNTL                                                                              0x24d4</div><div class='add'>+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_SEC_CNTL2                                                                             0x24d5</div><div class='add'>+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL3                                                                             0x24d6</div><div class='add'>+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL4                                                                             0x24d7</div><div class='add'>+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL5                                                                             0x24d8</div><div class='add'>+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL6                                                                             0x24d9</div><div class='add'>+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL7                                                                             0x24da</div><div class='add'>+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DB_CNTL                                                                               0x24db</div><div class='add'>+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP3_DP_MSA_VBID_MISC                                                                         0x24dc</div><div class='add'>+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x24dd</div><div class='add'>+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_ALPM_CNTL                                                                             0x24df</div><div class='add'>+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_GSP8_CNTL                                                                             0x24e0</div><div class='add'>+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_GSP9_CNTL                                                                             0x24e1</div><div class='add'>+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_GSP10_CNTL                                                                            0x24e2</div><div class='add'>+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_GSP11_CNTL                                                                            0x24e3</div><div class='add'>+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x24e4</div><div class='add'>+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x24e5</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x24e6</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x24e7</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x24e8</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x24e9</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x24ea</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x24eb</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x24ec</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x24ed</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x24ee</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_dispdec</div><div class='add'>+// base address: 0xdb0</div><div class='add'>+#define regDIG3_DIG_FE_CNTL                                                                             0x23ff</div><div class='add'>+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG3_DIG_FE_CLK_CNTL                                                                         0x2400</div><div class='add'>+#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG3_DIG_FE_EN_CNTL                                                                          0x2401</div><div class='add'>+#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2402</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x2403</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x2404</div><div class='add'>+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_DIG_TEST_PATTERN                                                                        0x2405</div><div class='add'>+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2406</div><div class='add'>+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2407</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2408</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2409</div><div class='add'>+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_CONTROL                                                                            0x240a</div><div class='add'>+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG3_HDMI_STATUS                                                                             0x240b</div><div class='add'>+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x240c</div><div class='add'>+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x240d</div><div class='add'>+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x240e</div><div class='add'>+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x240f</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2410</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2411</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2412</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2413</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GC                                                                                 0x2414</div><div class='add'>+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2415</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2416</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2417</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2418</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x2419</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x241a</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x241b</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x241c</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG3_HDMI_DB_CONTROL                                                                         0x241d</div><div class='add'>+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG3_HDMI_ACR_32_0                                                                           0x241e</div><div class='add'>+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_32_1                                                                           0x241f</div><div class='add'>+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_44_0                                                                           0x2420</div><div class='add'>+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_44_1                                                                           0x2421</div><div class='add'>+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_48_0                                                                           0x2422</div><div class='add'>+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_48_1                                                                           0x2423</div><div class='add'>+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x2424</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x2425</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_AFMT_CNTL                                                                               0x2426</div><div class='add'>+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG3_DIG_BE_CLK_CNTL                                                                         0x2427</div><div class='add'>+#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG3_DIG_BE_CNTL                                                                             0x2428</div><div class='add'>+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x2429</div><div class='add'>+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_TMDS_CNTL                                                                               0x2450</div><div class='add'>+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x2451</div><div class='add'>+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x2452</div><div class='add'>+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2453</div><div class='add'>+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2454</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2455</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG3_TMDS_CTL_BITS                                                                           0x2457</div><div class='add'>+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x2458</div><div class='add'>+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2459</div><div class='add'>+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x245a</div><div class='add'>+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x245b</div><div class='add'>+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG3_DIG_VERSION                                                                             0x245d</div><div class='add'>+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp4_dispdec</div><div class='add'>+// base address: 0x1240</div><div class='add'>+#define regDP4_DP_LINK_CNTL                                                                             0x25ae</div><div class='add'>+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_PIXEL_FORMAT                                                                          0x25af</div><div class='add'>+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x25b0</div><div class='add'>+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_CONFIG                                                                                0x25b1</div><div class='add'>+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x25b2</div><div class='add'>+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_STEER_FIFO                                                                            0x25b3</div><div class='add'>+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP4_DP_MSA_MISC                                                                              0x25b4</div><div class='add'>+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x25b5</div><div class='add'>+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_VID_TIMING                                                                            0x25b6</div><div class='add'>+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP4_DP_VID_N                                                                                 0x25b7</div><div class='add'>+#define regDP4_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP4_DP_VID_M                                                                                 0x25b8</div><div class='add'>+#define regDP4_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x25b9</div><div class='add'>+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x25ba</div><div class='add'>+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP4_DP_VID_MSA_VBID                                                                          0x25bb</div><div class='add'>+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x25bc</div><div class='add'>+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_DPHY_CNTL                                                                             0x25bd</div><div class='add'>+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x25be</div><div class='add'>+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP4_DP_DPHY_SYM0                                                                             0x25bf</div><div class='add'>+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_DPHY_SYM1                                                                             0x25c0</div><div class='add'>+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_DPHY_SYM2                                                                             0x25c1</div><div class='add'>+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x25c2</div><div class='add'>+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x25c3</div><div class='add'>+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x25c4</div><div class='add'>+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_CONTROL0                                                                     0x25c5</div><div class='add'>+#define regDP4_DP_DPHY_CRC_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_CONTROL1                                                                     0x25c6</div><div class='add'>+#define regDP4_DP_DPHY_CRC_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT0                                                                      0x25c7</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT0_BASE_IDX                                                             2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT1                                                                      0x25c8</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT1_BASE_IDX                                                             2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_STATUS                                                                       0x25c9</div><div class='add'>+#define regDP4_DP_DPHY_CRC_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x25ca</div><div class='add'>+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x25cb</div><div class='add'>+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT2                                                                      0x25cc</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT2_BASE_IDX                                                             2</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT3                                                                      0x25cd</div><div class='add'>+#define regDP4_DP_DPHY_CRC_RESULT3_BASE_IDX                                                             2</div><div class='add'>+#define regDP4_DP_SEC_CNTL                                                                              0x25d1</div><div class='add'>+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_SEC_CNTL1                                                                             0x25d2</div><div class='add'>+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_FRAMING1                                                                          0x25d3</div><div class='add'>+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP4_DP_SEC_FRAMING2                                                                          0x25d4</div><div class='add'>+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP4_DP_SEC_FRAMING3                                                                          0x25d5</div><div class='add'>+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP4_DP_SEC_FRAMING4                                                                          0x25d6</div><div class='add'>+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP4_DP_SEC_AUD_N                                                                             0x25d7</div><div class='add'>+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x25d8</div><div class='add'>+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_SEC_AUD_M                                                                             0x25d9</div><div class='add'>+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x25da</div><div class='add'>+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x25db</div><div class='add'>+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x25dc</div><div class='add'>+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x25dd</div><div class='add'>+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x25df</div><div class='add'>+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_MSE_SAT0                                                                              0x25e0</div><div class='add'>+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_MSE_SAT1                                                                              0x25e1</div><div class='add'>+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_MSE_SAT2                                                                              0x25e2</div><div class='add'>+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x25e3</div><div class='add'>+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x25e4</div><div class='add'>+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x25e5</div><div class='add'>+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x25ea</div><div class='add'>+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x25eb</div><div class='add'>+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x25ed</div><div class='add'>+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x25ee</div><div class='add'>+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x25ef</div><div class='add'>+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP4_DP_DPIA_SPARE                                                                            0x25f0</div><div class='add'>+#define regDP4_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x25f2</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x25f3</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x25f4</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x25f5</div><div class='add'>+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP4_DP_MSO_CNTL                                                                              0x25f6</div><div class='add'>+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_MSO_CNTL1                                                                             0x25f7</div><div class='add'>+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_DSC_CNTL                                                                              0x25f8</div><div class='add'>+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP4_DP_SEC_CNTL2                                                                             0x25f9</div><div class='add'>+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_CNTL3                                                                             0x25fa</div><div class='add'>+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_CNTL4                                                                             0x25fb</div><div class='add'>+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_CNTL5                                                                             0x25fc</div><div class='add'>+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_CNTL6                                                                             0x25fd</div><div class='add'>+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_SEC_CNTL7                                                                             0x25fe</div><div class='add'>+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_DB_CNTL                                                                               0x25ff</div><div class='add'>+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP4_DP_MSA_VBID_MISC                                                                         0x2600</div><div class='add'>+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x2601</div><div class='add'>+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP4_DP_ALPM_CNTL                                                                             0x2603</div><div class='add'>+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_GSP8_CNTL                                                                             0x2604</div><div class='add'>+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_GSP9_CNTL                                                                             0x2605</div><div class='add'>+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP4_DP_GSP10_CNTL                                                                            0x2606</div><div class='add'>+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP4_DP_GSP11_CNTL                                                                            0x2607</div><div class='add'>+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2608</div><div class='add'>+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL1                                                                    0x2609</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL2                                                                    0x260a</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL3                                                                    0x260b</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL4                                                                    0x260c</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL5                                                                    0x260d</div><div class='add'>+#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x260e</div><div class='add'>+#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x260f</div><div class='add'>+#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2610</div><div class='add'>+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2611</div><div class='add'>+#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2612</div><div class='add'>+#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_dispdec</div><div class='add'>+// base address: 0x1240</div><div class='add'>+#define regDIG4_DIG_FE_CNTL                                                                             0x2523</div><div class='add'>+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG4_DIG_FE_CLK_CNTL                                                                         0x2524</div><div class='add'>+#define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG4_DIG_FE_EN_CNTL                                                                          0x2525</div><div class='add'>+#define regDIG4_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x2526</div><div class='add'>+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x2527</div><div class='add'>+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x2528</div><div class='add'>+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG4_DIG_TEST_PATTERN                                                                        0x2529</div><div class='add'>+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x252a</div><div class='add'>+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_DIG_FIFO_CTRL0                                                                          0x252b</div><div class='add'>+#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG4_DIG_FIFO_CTRL1                                                                          0x252c</div><div class='add'>+#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x252d</div><div class='add'>+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_CONTROL                                                                            0x252e</div><div class='add'>+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG4_HDMI_STATUS                                                                             0x252f</div><div class='add'>+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2530</div><div class='add'>+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2531</div><div class='add'>+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2532</div><div class='add'>+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2533</div><div class='add'>+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2534</div><div class='add'>+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2535</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2536</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2537</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GC                                                                                 0x2538</div><div class='add'>+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2539</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x253a</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x253b</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x253c</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x253d</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x253e</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x253f</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x2540</div><div class='add'>+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG4_HDMI_DB_CONTROL                                                                         0x2541</div><div class='add'>+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG4_HDMI_ACR_32_0                                                                           0x2542</div><div class='add'>+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_HDMI_ACR_32_1                                                                           0x2543</div><div class='add'>+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_HDMI_ACR_44_0                                                                           0x2544</div><div class='add'>+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_HDMI_ACR_44_1                                                                           0x2545</div><div class='add'>+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_HDMI_ACR_48_0                                                                           0x2546</div><div class='add'>+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_HDMI_ACR_48_1                                                                           0x2547</div><div class='add'>+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x2548</div><div class='add'>+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x2549</div><div class='add'>+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG4_AFMT_CNTL                                                                               0x254a</div><div class='add'>+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG4_DIG_BE_CLK_CNTL                                                                         0x254b</div><div class='add'>+#define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG4_DIG_BE_CNTL                                                                             0x254c</div><div class='add'>+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x254d</div><div class='add'>+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG4_TMDS_CNTL                                                                               0x2574</div><div class='add'>+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x2575</div><div class='add'>+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x2576</div><div class='add'>+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2577</div><div class='add'>+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2578</div><div class='add'>+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2579</div><div class='add'>+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG4_TMDS_CTL_BITS                                                                           0x257b</div><div class='add'>+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x257c</div><div class='add'>+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x257d</div><div class='add'>+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x257e</div><div class='add'>+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x257f</div><div class='add'>+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG4_DIG_VERSION                                                                             0x2581</div><div class='add'>+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x154cc</div><div class='add'>+#define regAFMT0_AFMT_ACP                                                                               0x2073</div><div class='add'>+#define regAFMT0_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074</div><div class='add'>+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT0_AFMT_60958_0                                                                           0x2078</div><div class='add'>+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT0_AFMT_60958_1                                                                           0x2079</div><div class='add'>+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_60958_2                                                                           0x207f</div><div class='add'>+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT0_AFMT_STATUS                                                                            0x2081</div><div class='add'>+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083</div><div class='add'>+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084</div><div class='add'>+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087</div><div class='add'>+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x1595c</div><div class='add'>+#define regAFMT1_AFMT_ACP                                                                               0x2197</div><div class='add'>+#define regAFMT1_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2198</div><div class='add'>+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2199</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x219a</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x219b</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT1_AFMT_60958_0                                                                           0x219c</div><div class='add'>+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT1_AFMT_60958_1                                                                           0x219d</div><div class='add'>+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x219e</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x219f</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x21a0</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x21a1</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x21a2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_60958_2                                                                           0x21a3</div><div class='add'>+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x21a4</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT1_AFMT_STATUS                                                                            0x21a5</div><div class='add'>+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x21a6</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x21a7</div><div class='add'>+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x21a8</div><div class='add'>+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x21a9</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT1_AFMT_MEM_PWR                                                                           0x21ab</div><div class='add'>+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x15dec</div><div class='add'>+#define regAFMT2_AFMT_ACP                                                                               0x22bb</div><div class='add'>+#define regAFMT2_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x22bc</div><div class='add'>+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x22bd</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x22be</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x22bf</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT2_AFMT_60958_0                                                                           0x22c0</div><div class='add'>+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT2_AFMT_60958_1                                                                           0x22c1</div><div class='add'>+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x22c2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x22c3</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x22c4</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x22c5</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x22c6</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_60958_2                                                                           0x22c7</div><div class='add'>+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x22c8</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT2_AFMT_STATUS                                                                            0x22c9</div><div class='add'>+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x22ca</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x22cb</div><div class='add'>+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x22cc</div><div class='add'>+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x22cd</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT2_AFMT_MEM_PWR                                                                           0x22cf</div><div class='add'>+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x1627c</div><div class='add'>+#define regAFMT3_AFMT_ACP                                                                               0x23df</div><div class='add'>+#define regAFMT3_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x23e0</div><div class='add'>+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x23e1</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x23e2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x23e3</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT3_AFMT_60958_0                                                                           0x23e4</div><div class='add'>+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT3_AFMT_60958_1                                                                           0x23e5</div><div class='add'>+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x23e6</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x23e7</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x23e8</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x23e9</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x23ea</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_60958_2                                                                           0x23eb</div><div class='add'>+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x23ec</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT3_AFMT_STATUS                                                                            0x23ed</div><div class='add'>+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x23ee</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x23ef</div><div class='add'>+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x23f0</div><div class='add'>+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x23f1</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT3_AFMT_MEM_PWR                                                                           0x23f3</div><div class='add'>+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x1670c</div><div class='add'>+#define regAFMT4_AFMT_ACP                                                                               0x2503</div><div class='add'>+#define regAFMT4_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2504</div><div class='add'>+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2505</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2506</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2507</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT4_AFMT_60958_0                                                                           0x2508</div><div class='add'>+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT4_AFMT_60958_1                                                                           0x2509</div><div class='add'>+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x250a</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x250b</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x250c</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x250d</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x250e</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT4_AFMT_60958_2                                                                           0x250f</div><div class='add'>+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2510</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT4_AFMT_STATUS                                                                            0x2511</div><div class='add'>+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2512</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2513</div><div class='add'>+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2514</div><div class='add'>+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2515</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2517</div><div class='add'>+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec</div><div class='add'>+// base address: 0x15544</div><div class='add'>+#define regDME0_DME_CONTROL                                                                             0x2091</div><div class='add'>+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME0_DME_MEMORY_CONTROL                                                                      0x2092</div><div class='add'>+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x154a0</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a</div><div class='add'>+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b</div><div class='add'>+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c</div><div class='add'>+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG0_VPG_MEM_PWR                                                                             0x206d</div><div class='add'>+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec</div><div class='add'>+// base address: 0x159d4</div><div class='add'>+#define regDME1_DME_CONTROL                                                                             0x21b5</div><div class='add'>+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME1_DME_MEMORY_CONTROL                                                                      0x21b6</div><div class='add'>+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x15930</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x218c</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x218d</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x218e</div><div class='add'>+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x218f</div><div class='add'>+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x2190</div><div class='add'>+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG1_VPG_MEM_PWR                                                                             0x2191</div><div class='add'>+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x2192</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x2193</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2194</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2195</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec</div><div class='add'>+// base address: 0x15e64</div><div class='add'>+#define regDME2_DME_CONTROL                                                                             0x22d9</div><div class='add'>+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME2_DME_MEMORY_CONTROL                                                                      0x22da</div><div class='add'>+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x15dc0</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x22b0</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x22b1</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x22b2</div><div class='add'>+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x22b3</div><div class='add'>+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x22b4</div><div class='add'>+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG2_VPG_MEM_PWR                                                                             0x22b5</div><div class='add'>+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x22b6</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x22b7</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO0                                                                          0x22b8</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO1                                                                          0x22b9</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec</div><div class='add'>+// base address: 0x162f4</div><div class='add'>+#define regDME3_DME_CONTROL                                                                             0x23fd</div><div class='add'>+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME3_DME_MEMORY_CONTROL                                                                      0x23fe</div><div class='add'>+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x16250</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x23d4</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x23d5</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x23d6</div><div class='add'>+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x23d7</div><div class='add'>+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x23d8</div><div class='add'>+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG3_VPG_MEM_PWR                                                                             0x23d9</div><div class='add'>+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x23da</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x23db</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO0                                                                          0x23dc</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO1                                                                          0x23dd</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec</div><div class='add'>+// base address: 0x16784</div><div class='add'>+#define regDME4_DME_CONTROL                                                                             0x2521</div><div class='add'>+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME4_DME_MEMORY_CONTROL                                                                      0x2522</div><div class='add'>+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x166e0</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x24f8</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x24f9</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x24fa</div><div class='add'>+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x24fb</div><div class='add'>+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x24fc</div><div class='add'>+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG4_VPG_MEM_PWR                                                                             0x24fd</div><div class='add'>+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x24fe</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x24ff</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2500</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2501</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50</div><div class='add'>+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51</div><div class='add'>+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52</div><div class='add'>+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53</div><div class='add'>+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54</div><div class='add'>+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55</div><div class='add'>+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56</div><div class='add'>+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57</div><div class='add'>+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61</div><div class='add'>+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66</div><div class='add'>+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux1_dispdec</div><div class='add'>+// base address: 0x70</div><div class='add'>+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c</div><div class='add'>+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d</div><div class='add'>+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e</div><div class='add'>+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f</div><div class='add'>+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70</div><div class='add'>+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71</div><div class='add'>+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72</div><div class='add'>+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73</div><div class='add'>+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d</div><div class='add'>+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82</div><div class='add'>+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux2_dispdec</div><div class='add'>+// base address: 0xe0</div><div class='add'>+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88</div><div class='add'>+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89</div><div class='add'>+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a</div><div class='add'>+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b</div><div class='add'>+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c</div><div class='add'>+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d</div><div class='add'>+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e</div><div class='add'>+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f</div><div class='add'>+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99</div><div class='add'>+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e</div><div class='add'>+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux3_dispdec</div><div class='add'>+// base address: 0x150</div><div class='add'>+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4</div><div class='add'>+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5</div><div class='add'>+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6</div><div class='add'>+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7</div><div class='add'>+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8</div><div class='add'>+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9</div><div class='add'>+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa</div><div class='add'>+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab</div><div class='add'>+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5</div><div class='add'>+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba</div><div class='add'>+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux4_dispdec</div><div class='add'>+// base address: 0x1c0</div><div class='add'>+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0</div><div class='add'>+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1</div><div class='add'>+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2</div><div class='add'>+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3</div><div class='add'>+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4</div><div class='add'>+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5</div><div class='add'>+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6</div><div class='add'>+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7</div><div class='add'>+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd</div><div class='add'>+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1</div><div class='add'>+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6</div><div class='add'>+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux0_dispdec</div><div class='add'>+// base address: 0x14de0</div><div class='add'>+#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL                                                           0x1eb8</div><div class='add'>+#define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux1_dispdec</div><div class='add'>+// base address: 0x14de4</div><div class='add'>+#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL                                                           0x1eb9</div><div class='add'>+#define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux2_dispdec</div><div class='add'>+// base address: 0x14de8</div><div class='add'>+#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL                                                           0x1eba</div><div class='add'>+#define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux3_dispdec</div><div class='add'>+// base address: 0x14dec</div><div class='add'>+#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL                                                           0x1ebb</div><div class='add'>+#define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dout_i2c_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_I2C_CONTROL                                                                               0x1e98</div><div class='add'>+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_I2C_ARBITRATION                                                                           0x1e99</div><div class='add'>+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a</div><div class='add'>+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_I2C_SW_STATUS                                                                             0x1e9b</div><div class='add'>+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c</div><div class='add'>+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d</div><div class='add'>+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e</div><div class='add'>+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f</div><div class='add'>+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0</div><div class='add'>+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2</div><div class='add'>+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3</div><div class='add'>+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4</div><div class='add'>+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5</div><div class='add'>+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6</div><div class='add'>+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7</div><div class='add'>+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8</div><div class='add'>+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9</div><div class='add'>+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa</div><div class='add'>+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab</div><div class='add'>+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_TRANSACTION0                                                                          0x1eae</div><div class='add'>+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf</div><div class='add'>+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0</div><div class='add'>+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1</div><div class='add'>+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_DATA                                                                                  0x1eb2</div><div class='add'>+#define regDC_I2C_DATA_BASE_IDX                                                                         2</div><div class='add'>+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6</div><div class='add'>+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7</div><div class='add'>+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDIO_DCN_STATUS                                                                               0x1ec3</div><div class='add'>+#define regDIO_DCN_STATUS_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_SCRATCH0                                                                                 0x1eca</div><div class='add'>+#define regDIO_SCRATCH0_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH1                                                                                 0x1ecb</div><div class='add'>+#define regDIO_SCRATCH1_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH2                                                                                 0x1ecc</div><div class='add'>+#define regDIO_SCRATCH2_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH3                                                                                 0x1ecd</div><div class='add'>+#define regDIO_SCRATCH3_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH4                                                                                 0x1ece</div><div class='add'>+#define regDIO_SCRATCH4_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH5                                                                                 0x1ecf</div><div class='add'>+#define regDIO_SCRATCH5_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH6                                                                                 0x1ed0</div><div class='add'>+#define regDIO_SCRATCH6_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH7                                                                                 0x1ed1</div><div class='add'>+#define regDIO_SCRATCH7_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3</div><div class='add'>+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd</div><div class='add'>+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede</div><div class='add'>+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf</div><div class='add'>+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2</div><div class='add'>+#define regDIO_CLK_CNTL                                                                                 0x1ee0</div><div class='add'>+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4</div><div class='add'>+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff</div><div class='add'>+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00</div><div class='add'>+#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01</div><div class='add'>+#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2</div><div class='add'>+#define regDIO_STATUS                                                                                   0x1f02</div><div class='add'>+#define regDIO_STATUS_BASE_IDX                                                                          2</div><div class='add'>+#define regDIO_LINKA_CNTL                                                                               0x1f04</div><div class='add'>+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_LINKB_CNTL                                                                               0x1f05</div><div class='add'>+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_LINKC_CNTL                                                                               0x1f06</div><div class='add'>+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_LINKD_CNTL                                                                               0x1f07</div><div class='add'>+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_LINKE_CNTL                                                                               0x1f08</div><div class='add'>+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_LINKF_CNTL                                                                               0x1f09</div><div class='add'>+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDIG0_STREAM_MAPPER_CONTROL                                                                   0x1f0d</div><div class='add'>+#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG1_STREAM_MAPPER_CONTROL                                                                   0x1f0e</div><div class='add'>+#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG2_STREAM_MAPPER_CONTROL                                                                   0x1f0f</div><div class='add'>+#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG3_STREAM_MAPPER_CONTROL                                                                   0x1f10</div><div class='add'>+#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG4_STREAM_MAPPER_CONTROL                                                                   0x1f11</div><div class='add'>+#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x7d10</div><div class='add'>+#define regDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44</div><div class='add'>+#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45</div><div class='add'>+#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46</div><div class='add'>+#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a</div><div class='add'>+#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON18_PERFMON_HI                                                                      0x1f4b</div><div class='add'>+#define regDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c</div><div class='add'>+#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GENERICA                                                                                  0x2868</div><div class='add'>+#define regDC_GENERICA_BASE_IDX                                                                         2</div><div class='add'>+#define regDC_GENERICB                                                                                  0x2869</div><div class='add'>+#define regDC_GENERICB_BASE_IDX                                                                         2</div><div class='add'>+#define regDCIO_CLOCK_CNTL                                                                              0x286a</div><div class='add'>+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_REF_CLK_CNTL                                                                              0x286b</div><div class='add'>+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regUNIPHYA_LINK_CNTL                                                                            0x286d</div><div class='add'>+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e</div><div class='add'>+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYB_LINK_CNTL                                                                            0x286f</div><div class='add'>+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870</div><div class='add'>+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYC_LINK_CNTL                                                                            0x2871</div><div class='add'>+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872</div><div class='add'>+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874</div><div class='add'>+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876</div><div class='add'>+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDCIO_WRCMD_DELAY                                                                             0x287e</div><div class='add'>+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_PINSTRAPS                                                                                 0x2880</div><div class='add'>+#define regDC_PINSTRAPS_BASE_IDX                                                                        2</div><div class='add'>+#define regDCIO_SPARE                                                                                   0x2882</div><div class='add'>+#define regDCIO_SPARE_BASE_IDX                                                                          2</div><div class='add'>+#define regINTERCEPT_STATE                                                                              0x2884</div><div class='add'>+#define regINTERCEPT_STATE_BASE_IDX                                                                     2</div><div class='add'>+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886</div><div class='add'>+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2</div><div class='add'>+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887</div><div class='add'>+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2</div><div class='add'>+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b</div><div class='add'>+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c</div><div class='add'>+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d</div><div class='add'>+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regDCIO_SOFT_RESET                                                                              0x289e</div><div class='add'>+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_chip_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8</div><div class='add'>+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2</div><div class='add'>+#define regDC_GPIO_GENERIC_A                                                                            0x28c9</div><div class='add'>+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca</div><div class='add'>+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb</div><div class='add'>+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0</div><div class='add'>+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC1_A                                                                               0x28d1</div><div class='add'>+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC1_EN                                                                              0x28d2</div><div class='add'>+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC1_Y                                                                               0x28d3</div><div class='add'>+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4</div><div class='add'>+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC2_A                                                                               0x28d5</div><div class='add'>+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC2_EN                                                                              0x28d6</div><div class='add'>+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC2_Y                                                                               0x28d7</div><div class='add'>+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8</div><div class='add'>+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC3_A                                                                               0x28d9</div><div class='add'>+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC3_EN                                                                              0x28da</div><div class='add'>+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC3_Y                                                                               0x28db</div><div class='add'>+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc</div><div class='add'>+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC4_A                                                                               0x28dd</div><div class='add'>+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC4_EN                                                                              0x28de</div><div class='add'>+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC4_Y                                                                               0x28df</div><div class='add'>+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0</div><div class='add'>+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC5_A                                                                               0x28e1</div><div class='add'>+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC5_EN                                                                              0x28e2</div><div class='add'>+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC5_Y                                                                               0x28e3</div><div class='add'>+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8</div><div class='add'>+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9</div><div class='add'>+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea</div><div class='add'>+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb</div><div class='add'>+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0</div><div class='add'>+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_GENLK_A                                                                              0x28f1</div><div class='add'>+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_GENLK_EN                                                                             0x28f2</div><div class='add'>+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_GENLK_Y                                                                              0x28f3</div><div class='add'>+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_HPD_MASK                                                                             0x28f4</div><div class='add'>+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_HPD_A                                                                                0x28f5</div><div class='add'>+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2</div><div class='add'>+#define regDC_GPIO_HPD_EN                                                                               0x28f6</div><div class='add'>+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_HPD_Y                                                                                0x28f7</div><div class='add'>+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2</div><div class='add'>+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa</div><div class='add'>+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc</div><div class='add'>+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2</div><div class='add'>+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd</div><div class='add'>+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2</div><div class='add'>+#define regPHY_AUX_CNTL                                                                                 0x28ff</div><div class='add'>+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900</div><div class='add'>+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2</div><div class='add'>+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902</div><div class='add'>+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_TX12_EN                                                                              0x2915</div><div class='add'>+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_RXEN                                                                                 0x2919</div><div class='add'>+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2</div><div class='add'>+#define regDC_GPIO_PULLUPEN                                                                             0x291a</div><div class='add'>+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2</div><div class='add'>+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e</div><div class='add'>+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec</div><div class='add'>+// base address: 0x360</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec</div><div class='add'>+// base address: 0x6c0</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec</div><div class='add'>+// base address: 0xa20</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec</div><div class='add'>+// base address: 0xd80</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1</div><div class='add'>+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13</div><div class='add'>+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2</div><div class='add'>+#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19</div><div class='add'>+#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a</div><div class='add'>+#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2</div><div class='add'>+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b</div><div class='add'>+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c</div><div class='add'>+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d</div><div class='add'>+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2</div><div class='add'>+#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21</div><div class='add'>+#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec</div><div class='add'>+// base address: 0x1b0</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f</div><div class='add'>+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2</div><div class='add'>+#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85</div><div class='add'>+#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86</div><div class='add'>+#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2</div><div class='add'>+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87</div><div class='add'>+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88</div><div class='add'>+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89</div><div class='add'>+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2</div><div class='add'>+#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d</div><div class='add'>+#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a</div><div class='add'>+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b</div><div class='add'>+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC0_DSCC_STATUS                                                                            0x300c</div><div class='add'>+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025</div><div class='add'>+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035</div><div class='add'>+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005</div><div class='add'>+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006</div><div class='add'>+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001</div><div class='add'>+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xc140</div><div class='add'>+#define regDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050</div><div class='add'>+#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051</div><div class='add'>+#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052</div><div class='add'>+#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CNTL                                                                    0x3053</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056</div><div class='add'>+#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON19_PERFMON_HI                                                                      0x3057</div><div class='add'>+#define regDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON19_PERFMON_LOW                                                                     0x3058</div><div class='add'>+#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x170</div><div class='add'>+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066</div><div class='add'>+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067</div><div class='add'>+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC1_DSCC_STATUS                                                                            0x3068</div><div class='add'>+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081</div><div class='add'>+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091</div><div class='add'>+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x170</div><div class='add'>+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061</div><div class='add'>+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062</div><div class='add'>+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x170</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d</div><div class='add'>+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xc2b0</div><div class='add'>+#define regDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac</div><div class='add'>+#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad</div><div class='add'>+#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae</div><div class='add'>+#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CNTL                                                                    0x30af</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_HI                                                                      0x30b3</div><div class='add'>+#define regDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON20_PERFMON_LOW                                                                     0x30b4</div><div class='add'>+#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x2e0</div><div class='add'>+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2</div><div class='add'>+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3</div><div class='add'>+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC2_DSCC_STATUS                                                                            0x30c4</div><div class='add'>+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd</div><div class='add'>+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed</div><div class='add'>+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x2e0</div><div class='add'>+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd</div><div class='add'>+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be</div><div class='add'>+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x2e0</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9</div><div class='add'>+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xc420</div><div class='add'>+#define regDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108</div><div class='add'>+#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109</div><div class='add'>+#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a</div><div class='add'>+#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CNTL                                                                    0x310b</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e</div><div class='add'>+#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON21_PERFMON_HI                                                                      0x310f</div><div class='add'>+#define regDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON21_PERFMON_LOW                                                                     0x3110</div><div class='add'>+#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x450</div><div class='add'>+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e</div><div class='add'>+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f</div><div class='add'>+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC3_DSCC_STATUS                                                                            0x3120</div><div class='add'>+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139</div><div class='add'>+#define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149</div><div class='add'>+#define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x450</div><div class='add'>+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119</div><div class='add'>+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a</div><div class='add'>+#define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x450</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115</div><div class='add'>+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0xc590</div><div class='add'>+#define regDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164</div><div class='add'>+#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165</div><div class='add'>+#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166</div><div class='add'>+#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CNTL                                                                    0x3167</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a</div><div class='add'>+#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2</div><div class='add'>+#define regDC_PERFMON22_PERFMON_HI                                                                      0x316b</div><div class='add'>+#define regDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2</div><div class='add'>+#define regDC_PERFMON22_PERFMON_LOW                                                                     0x316c</div><div class='add'>+#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hpo_top_dispdec</div><div class='add'>+// base address: 0x2790c</div><div class='add'>+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43</div><div class='add'>+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a</div><div class='add'>+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec</div><div class='add'>+// base address: 0x27958</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+// base address: 0x1a698</div><div class='add'>+#define regDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x0e66</div><div class='add'>+#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       3</div><div class='add'>+#define regDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x0e67</div><div class='add'>+#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      3</div><div class='add'>+#define regDC_PERFMON23_PERFCOUNTER_STATE                                                               0x0e68</div><div class='add'>+#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      3</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CNTL                                                                    0x0e69</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           3</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CNTL2                                                                   0x0e6a</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          3</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x0e6b</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x0e6c</div><div class='add'>+#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     3</div><div class='add'>+#define regDC_PERFMON23_PERFMON_HI                                                                      0x0e6d</div><div class='add'>+#define regDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             3</div><div class='add'>+#define regDC_PERFMON23_PERFMON_LOW                                                                     0x0e6e</div><div class='add'>+#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec</div><div class='add'>+// base address: 0x2656c</div><div class='add'>+#define regHDMI_LINK_ENC_CONTROL                                                                        0x095b</div><div class='add'>+#define regHDMI_LINK_ENC_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regHDMI_LINK_ENC_CLK_CTRL                                                                       0x095c</div><div class='add'>+#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX                                                              3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec</div><div class='add'>+// base address: 0x26594</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG                                                                          0x0965</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG_BASE_IDX                                                                 3</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG2                                                                         0x0966</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_FRL_ENC_METER_BUFFER_STATUS                                                             0x0967</div><div class='add'>+#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX                                                    3</div><div class='add'>+#define regHDMI_FRL_ENC_MEM_CTRL                                                                        0x0968</div><div class='add'>+#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX                                                               3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec</div><div class='add'>+// base address: 0x2634c</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_CONTROL                                                                0x08d3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                                       3</div><div class='add'>+#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL                                                            0x08d5</div><div class='add'>+#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                                     0x08d6</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX                            3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                                     0x08d7</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX                            3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2                                     0x08d8</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX                            3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x2646c</div><div class='add'>+#define regAFMT5_AFMT_ACP                                                                               0x091b</div><div class='add'>+#define regAFMT5_AFMT_ACP_BASE_IDX                                                                      3</div><div class='add'>+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c</div><div class='add'>+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3</div><div class='add'>+#define regAFMT5_AFMT_60958_0                                                                           0x0920</div><div class='add'>+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3</div><div class='add'>+#define regAFMT5_AFMT_60958_1                                                                           0x0921</div><div class='add'>+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926</div><div class='add'>+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT5_AFMT_60958_2                                                                           0x0927</div><div class='add'>+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3</div><div class='add'>+#define regAFMT5_AFMT_STATUS                                                                            0x0929</div><div class='add'>+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3</div><div class='add'>+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b</div><div class='add'>+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3</div><div class='add'>+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c</div><div class='add'>+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d</div><div class='add'>+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f</div><div class='add'>+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec</div><div class='add'>+// base address: 0x264f0</div><div class='add'>+#define regDME5_DME_CONTROL                                                                             0x093c</div><div class='add'>+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3</div><div class='add'>+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d</div><div class='add'>+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x264c4</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3</div><div class='add'>+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933</div><div class='add'>+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3</div><div class='add'>+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934</div><div class='add'>+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3</div><div class='add'>+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935</div><div class='add'>+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3</div><div class='add'>+#define regVPG5_VPG_MEM_PWR                                                                             0x0936</div><div class='add'>+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec</div><div class='add'>+// base address: 0x2637c</div><div class='add'>+#define regHDMI_TB_ENC_CONTROL                                                                          0x08df</div><div class='add'>+#define regHDMI_TB_ENC_CONTROL_BASE_IDX                                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_PIXEL_FORMAT                                                                     0x08e0</div><div class='add'>+#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_PACKET_CONTROL                                                                   0x08e1</div><div class='add'>+#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_PACKET_CONTROL                                                               0x08e2</div><div class='add'>+#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX                                                      3</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1                                                              0x08e3</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX                                                     3</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2                                                              0x08e4</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX                                                     3</div><div class='add'>+#define regHDMI_TB_ENC_GC_CONTROL                                                                       0x08e5</div><div class='add'>+#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX                                                              3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0                                                          0x08e6</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1                                                          0x08e7</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2                                                          0x08e8</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE                                                           0x08e9</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE                                                           0x08ea</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE                                                           0x08eb</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE                                                           0x08ec</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE                                                           0x08ed</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE                                                         0x08ee</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX                                                3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE                                                         0x08ef</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX                                                3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE                                                            0x08f0</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX                                                   3</div><div class='add'>+#define regHDMI_TB_ENC_DB_CONTROL                                                                       0x08f1</div><div class='add'>+#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX                                                              3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_0                                                                         0x08f2</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_1                                                                         0x08f3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_0                                                                         0x08f4</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_1                                                                         0x08f5</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_0                                                                         0x08f6</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_1                                                                         0x08f7</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_0                                                                     0x08f8</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_1                                                                     0x08f9</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_BUFFER_CONTROL                                                                   0x08fb</div><div class='add'>+#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regHDMI_TB_ENC_MEM_CTRL                                                                         0x08fe</div><div class='add'>+#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL                                                          0x08ff</div><div class='add'>+#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_H_ACTIVE_BLANK                                                                   0x0900</div><div class='add'>+#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX                                                          3</div><div class='add'>+#define regHDMI_TB_ENC_HC_ACTIVE_BLANK                                                                  0x0901</div><div class='add'>+#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX                                                         3</div><div class='add'>+#define regHDMI_TB_ENC_CRC_CNTL                                                                         0x0903</div><div class='add'>+#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_0                                                                     0x0904</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_ENCRYPTION_CONTROL                                                               0x0907</div><div class='add'>+#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX                                                      3</div><div class='add'>+#define regHDMI_TB_ENC_MODE                                                                             0x0908</div><div class='add'>+#define regHDMI_TB_ENC_MODE_BASE_IDX                                                                    3</div><div class='add'>+#define regHDMI_TB_ENC_INPUT_FIFO_STATUS                                                                0x0909</div><div class='add'>+#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX                                                       3</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_1                                                                     0x090a</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX                                                            3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec</div><div class='add'>+// base address: 0x1ab8c</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec</div><div class='add'>+// base address: 0x1abc0</div><div class='add'>+#define regAPG0_APG_CONTROL                                                                             0x3630</div><div class='add'>+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_CONTROL2                                                                            0x3631</div><div class='add'>+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632</div><div class='add'>+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633</div><div class='add'>+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG0_APG_STATUS                                                                              0x3641</div><div class='add'>+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG0_APG_STATUS2                                                                             0x3642</div><div class='add'>+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_MEM_PWR                                                                             0x3644</div><div class='add'>+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_SPARE                                                                               0x3646</div><div class='add'>+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec</div><div class='add'>+// base address: 0x1ac38</div><div class='add'>+#define regDME6_DME_CONTROL                                                                             0x364e</div><div class='add'>+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f</div><div class='add'>+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1ac44</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653</div><div class='add'>+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654</div><div class='add'>+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655</div><div class='add'>+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG6_VPG_MEM_PWR                                                                             0x3656</div><div class='add'>+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec</div><div class='add'>+// base address: 0x1ac74</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x368b</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x368c</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2                                                   0x3693</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3                                                   0x3694</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec</div><div class='add'>+// base address: 0x1aedc</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec</div><div class='add'>+// base address: 0x1af10</div><div class='add'>+#define regAPG1_APG_CONTROL                                                                             0x3704</div><div class='add'>+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_CONTROL2                                                                            0x3705</div><div class='add'>+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706</div><div class='add'>+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707</div><div class='add'>+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG1_APG_STATUS                                                                              0x3715</div><div class='add'>+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG1_APG_STATUS2                                                                             0x3716</div><div class='add'>+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_MEM_PWR                                                                             0x3718</div><div class='add'>+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_SPARE                                                                               0x371a</div><div class='add'>+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec</div><div class='add'>+// base address: 0x1af88</div><div class='add'>+#define regDME7_DME_CONTROL                                                                             0x3722</div><div class='add'>+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723</div><div class='add'>+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1af94</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727</div><div class='add'>+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728</div><div class='add'>+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729</div><div class='add'>+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG7_VPG_MEM_PWR                                                                             0x372a</div><div class='add'>+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec</div><div class='add'>+// base address: 0x1afc4</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x375f</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3760</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3761</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3762</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2                                                   0x3767</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3                                                   0x3768</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec</div><div class='add'>+// base address: 0x1b22c</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec</div><div class='add'>+// base address: 0x1b260</div><div class='add'>+#define regAPG2_APG_CONTROL                                                                             0x37d8</div><div class='add'>+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_CONTROL2                                                                            0x37d9</div><div class='add'>+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da</div><div class='add'>+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db</div><div class='add'>+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG2_APG_STATUS                                                                              0x37e9</div><div class='add'>+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG2_APG_STATUS2                                                                             0x37ea</div><div class='add'>+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_MEM_PWR                                                                             0x37ec</div><div class='add'>+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_SPARE                                                                               0x37ee</div><div class='add'>+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec</div><div class='add'>+// base address: 0x1b2d8</div><div class='add'>+#define regDME8_DME_CONTROL                                                                             0x37f6</div><div class='add'>+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7</div><div class='add'>+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1b2e4</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb</div><div class='add'>+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc</div><div class='add'>+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd</div><div class='add'>+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe</div><div class='add'>+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec</div><div class='add'>+// base address: 0x1b314</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3833</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3834</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3835</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3836</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2                                                   0x383b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3                                                   0x383c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec</div><div class='add'>+// base address: 0x1b57c</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec</div><div class='add'>+// base address: 0x1b5b0</div><div class='add'>+#define regAPG3_APG_CONTROL                                                                             0x38ac</div><div class='add'>+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_CONTROL2                                                                            0x38ad</div><div class='add'>+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae</div><div class='add'>+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af</div><div class='add'>+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG3_APG_STATUS                                                                              0x38bd</div><div class='add'>+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG3_APG_STATUS2                                                                             0x38be</div><div class='add'>+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_MEM_PWR                                                                             0x38c0</div><div class='add'>+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_SPARE                                                                               0x38c2</div><div class='add'>+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec</div><div class='add'>+// base address: 0x1b628</div><div class='add'>+#define regDME9_DME_CONTROL                                                                             0x38ca</div><div class='add'>+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb</div><div class='add'>+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1b634</div><div class='add'>+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd</div><div class='add'>+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce</div><div class='add'>+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf</div><div class='add'>+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0</div><div class='add'>+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1</div><div class='add'>+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2</div><div class='add'>+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3</div><div class='add'>+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4</div><div class='add'>+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5</div><div class='add'>+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6</div><div class='add'>+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec</div><div class='add'>+// base address: 0x1b664</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3907</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3908</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3909</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x390a</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2                                                   0x390f</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3                                                   0x3910</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec</div><div class='add'>+// base address: 0x1ad5c</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec</div><div class='add'>+// base address: 0x1ae00</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x36eb</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x36ec</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x36ed</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36ee</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ef</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36f0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36f1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec</div><div class='add'>+// base address: 0x1b0ac</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec</div><div class='add'>+// base address: 0x1b150</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x37bf</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x37c0</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x37c1</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37c2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c3</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c4</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c5</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchvm_hvm_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHVM_CTRL0                                                                                  0x3603</div><div class='add'>+#define regDCHVM_CTRL0_BASE_IDX                                                                         2</div><div class='add'>+#define regDCHVM_CTRL1                                                                                  0x3604</div><div class='add'>+#define regDCHVM_CTRL1_BASE_IDX                                                                         2</div><div class='add'>+#define regDCHVM_CLK_CTRL                                                                               0x3605</div><div class='add'>+#define regDCHVM_CLK_CTRL_BASE_IDX                                                                      2</div><div class='add'>+#define regDCHVM_MEM_CTRL                                                                               0x3606</div><div class='add'>+#define regDCHVM_MEM_CTRL_BASE_IDX                                                                      2</div><div class='add'>+#define regDCHVM_RIOMMU_CTRL0                                                                           0x3607</div><div class='add'>+#define regDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHVM_RIOMMU_STAT0                                                                           0x3608</div><div class='add'>+#define regDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dlpc_dlpc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDLPC_ENABLE                                                                                  0x2fe8</div><div class='add'>+#define regDLPC_ENABLE_BASE_IDX                                                                         2</div><div class='add'>+#define regDLPC_CURRENT_COUNT                                                                           0x2fe9</div><div class='add'>+#define regDLPC_CURRENT_COUNT_BASE_IDX                                                                  2</div><div class='add'>+#define regDLPC_OPTC_SNAPSHOT                                                                           0x2fea</div><div class='add'>+#define regDLPC_OPTC_SNAPSHOT_BASE_IDX                                                                  2</div><div class='add'>+#define regDLPC_PWRUP                                                                                   0x2feb</div><div class='add'>+#define regDLPC_PWRUP_BASE_IDX                                                                          2</div><div class='add'>+#define regDLPC_OTG_RESYNC                                                                              0x2fec</div><div class='add'>+#define regDLPC_OTG_RESYNC_BASE_IDX                                                                     2</div><div class='add'>+#define regDLPC_DCN_ZSC_LONO_PWRUP                                                                      0x2fed</div><div class='add'>+#define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX                                                             2</div><div class='add'>+#define regDLPC_SPARE                                                                                   0x2fee</div><div class='add'>+#define regDLPC_SPARE_BASE_IDX                                                                          2</div><div class='add'>+#define regDLPC_COUNTER_INIT_VALUE                                                                      0x2fef</div><div class='add'>+#define regDLPC_COUNTER_INIT_VALUE_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dpia_dpia_mu0_dpiadec</div><div class='add'>+// base address: 0x72000</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL                                                                           0x13800</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_BASE_IDX                                                                  3</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0                                                                0x13801</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT0                                                                0x13802</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1                                                                0x13803</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT1                                                                0x13804</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2                                                                0x13805</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT2                                                                0x13806</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3                                                                0x13807</div><div class='add'>+#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT3                                                                0x13808</div><div class='add'>+#define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT0                                                                0x13811</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT1                                                                0x13812</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT2                                                                0x13813</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT3                                                                0x13814</div><div class='add'>+#define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX                                                       3</div><div class='add'>+#define regDPIA_MU_TPI_MAX_CREDIT_COUNT                                                                 0x13819</div><div class='add'>+#define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX                                                        3</div><div class='add'>+#define regDPIA_MU_INTERRUPT_STATUS                                                                     0x1381a</div><div class='add'>+#define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_MU_INTERRUPT_CTRL                                                                       0x1381b</div><div class='add'>+#define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX                                                              3</div><div class='add'>+#define regDPIA_MU_LOCAL_INTERRUPT_CTRL                                                                 0x1381c</div><div class='add'>+#define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX                                                        3</div><div class='add'>+#define regDPIA_MU_LOCAL_INTERRUPT_ACK                                                                  0x1381d</div><div class='add'>+#define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX                                                         3</div><div class='add'>+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL                                                                  0x1381e</div><div class='add'>+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX                                                         3</div><div class='add'>+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2                                                                 0x1381f</div><div class='add'>+#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX                                                        3</div><div class='add'>+#define regDPIA_MU_RBBMIF_STATUS                                                                        0x13820</div><div class='add'>+#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX                                                               3</div><div class='add'>+#define regDPIA_MU_MICROSECOND_REF_CTRL                                                                 0x13821</div><div class='add'>+#define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX                                                        3</div><div class='add'>+#define regDPIA_MU_PORT_ADP_STATUS                                                                      0x13822</div><div class='add'>+#define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX                                                             3</div><div class='add'>+#define regDPIA_GLUE_CTRL                                                                               0x13823</div><div class='add'>+#define regDPIA_GLUE_CTRL_BASE_IDX                                                                      3</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL0                                                                     0x13825</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL1                                                                     0x13826</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL2                                                                     0x13827</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL3                                                                     0x13828</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL4                                                                     0x13829</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL5                                                                     0x1382a</div><div class='add'>+#define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX                                                            3</div><div class='add'>+#define regDPIA_PERF_COUNT_INDEX                                                                        0x1382b</div><div class='add'>+#define regDPIA_PERF_COUNT_INDEX_BASE_IDX                                                               3</div><div class='add'>+#define regDPIA_PERF_COUNT_DATA_LO                                                                      0x1382c</div><div class='add'>+#define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX                                                             3</div><div class='add'>+#define regDPIA_MU_SPARE                                                                                0x1382d</div><div class='add'>+#define regDPIA_MU_SPARE_BASE_IDX                                                                       3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_f2codecind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_descriptorind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001</div><div class='add'>+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002</div><div class='add'>+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003</div><div class='add'>+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004</div><div class='add'>+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005</div><div class='add'>+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006</div><div class='add'>+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007</div><div class='add'>+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008</div><div class='add'>+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009</div><div class='add'>+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a</div><div class='add'>+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b</div><div class='add'>+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c</div><div class='add'>+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d</div><div class='add'>+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_sinkinfoind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004</div><div class='add'>+#define ixSINK_DESCRIPTION0                                                                            0x0005</div><div class='add'>+#define ixSINK_DESCRIPTION1                                                                            0x0006</div><div class='add'>+#define ixSINK_DESCRIPTION2                                                                            0x0007</div><div class='add'>+#define ixSINK_DESCRIPTION3                                                                            0x0008</div><div class='add'>+#define ixSINK_DESCRIPTION4                                                                            0x0009</div><div class='add'>+#define ixSINK_DESCRIPTION5                                                                            0x000a</div><div class='add'>+#define ixSINK_DESCRIPTION6                                                                            0x000b</div><div class='add'>+#define ixSINK_DESCRIPTION7                                                                            0x000c</div><div class='add'>+#define ixSINK_DESCRIPTION8                                                                            0x000d</div><div class='add'>+#define ixSINK_DESCRIPTION9                                                                            0x000e</div><div class='add'>+#define ixSINK_DESCRIPTION10                                                                           0x000f</div><div class='add'>+#define ixSINK_DESCRIPTION11                                                                           0x0010</div><div class='add'>+#define ixSINK_DESCRIPTION12                                                                           0x0011</div><div class='add'>+#define ixSINK_DESCRIPTION13                                                                           0x0012</div><div class='add'>+#define ixSINK_DESCRIPTION14                                                                           0x0013</div><div class='add'>+#define ixSINK_DESCRIPTION15                                                                           0x0014</div><div class='add'>+#define ixSINK_DESCRIPTION16                                                                           0x0015</div><div class='add'>+#define ixSINK_DESCRIPTION17                                                                           0x0016</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc0resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc1resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc0resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc1resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azinputendpoint_f2codecind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azroot_f2codecind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00</div><div class='add'>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02</div><div class='add'>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream0_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream1_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream2_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream3_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream4_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream5_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream6_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream7_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream8_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream9_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream10_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream11_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream12_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream13_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream14_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream15_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint0_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint1_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint2_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint3_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint4_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint5_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint6_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint7_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint0_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint1_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint2_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint3_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint4_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint5_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint6_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint7_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h<br/>new file mode 100644<br/>index 000000000000..3ffb6ec8b40a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h</a></div><div class='hunk'>@@ -0,0 +1,61940 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/* Copyright 2025 Advanced Micro Devices, Inc. */</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#ifndef _dcn_3_6_0_SH_MASK_HEADER</div><div class='add'>+#define _dcn_3_6_0_SH_MASK_HEADER</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azcontroller_azdec</div><div class='add'>+//GLOBAL_CAPABILITIES</div><div class='add'>+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                                          0x0</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                                      0x1</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                                 0x3</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                                         0x8</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                                        0xc</div><div class='add'>+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                                            0x0001L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                        0x0006L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                                   0x00F8L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                                           0x0F00L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                                          0xF000L</div><div class='add'>+//MINOR_VERSION</div><div class='add'>+#define MINOR_VERSION__MINOR_VERSION__SHIFT                                                                   0x0</div><div class='add'>+#define MINOR_VERSION__MINOR_VERSION_MASK                                                                     0xFFL</div><div class='add'>+//MAJOR_VERSION</div><div class='add'>+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                                   0x0</div><div class='add'>+#define MAJOR_VERSION__MAJOR_VERSION_MASK                                                                     0xFFL</div><div class='add'>+//OUTPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                           0x0</div><div class='add'>+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                             0xFFFFL</div><div class='add'>+//INPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                             0x0</div><div class='add'>+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                               0xFFFFL</div><div class='add'>+//GLOBAL_CONTROL</div><div class='add'>+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                               0x0</div><div class='add'>+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                                  0x1</div><div class='add'>+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                                             0x8</div><div class='add'>+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                                 0x00000001L</div><div class='add'>+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                                    0x00000002L</div><div class='add'>+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                               0x00000100L</div><div class='add'>+//WAKE_ENABLE</div><div class='add'>+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                                             0x0</div><div class='add'>+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                               0x0001L</div><div class='add'>+//STATE_CHANGE_STATUS</div><div class='add'>+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                                       0x0</div><div class='add'>+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                                         0x0001L</div><div class='add'>+//GLOBAL_STATUS</div><div class='add'>+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                                    0x1</div><div class='add'>+#define GLOBAL_STATUS__FLUSH_STATUS_MASK                                                                      0x00000002L</div><div class='add'>+//OUTPUT_STREAM_PAYLOAD_CAPABILITY</div><div class='add'>+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x0</div><div class='add'>+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFFL</div><div class='add'>+//INPUT_STREAM_PAYLOAD_CAPABILITY</div><div class='add'>+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x0</div><div class='add'>+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFFL</div><div class='add'>+//INTERRUPT_CONTROL</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                                   0x1</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                                   0x2</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                                   0x3</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                                   0x4</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                                   0x5</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                                   0x6</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                                   0x7</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                                   0x8</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                                   0x9</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                                  0xa</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                                  0xb</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                                  0xc</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                                  0xd</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                                  0xe</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                                  0xf</div><div class='add'>+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                                 0x1e</div><div class='add'>+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                                     0x1f</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                                     0x00000002L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                                     0x00000004L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                                     0x00000008L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                                     0x00000010L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                                     0x00000020L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                                     0x00000040L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                                     0x00000080L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                                     0x00000100L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                                     0x00000200L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                                    0x00000400L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                                    0x00000800L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                                    0x00001000L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                                    0x00002000L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                                    0x00004000L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                                    0x00008000L</div><div class='add'>+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                                   0x40000000L</div><div class='add'>+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                                       0x80000000L</div><div class='add'>+//INTERRUPT_STATUS</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                                    0x0</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                                    0x1</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT                                                    0x2</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT                                                    0x3</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT                                                    0x4</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT                                                    0x5</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT                                                    0x6</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT                                                    0x7</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT                                                    0x8</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT                                                    0x9</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT                                                   0xa</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT                                                   0xc</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT                                                   0xd</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT                                                   0xe</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT                                                   0xf</div><div class='add'>+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT                                                  0x1e</div><div class='add'>+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT                                                      0x1f</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK                                                      0x00000002L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK                                                      0x00000004L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK                                                      0x00000008L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK                                                      0x00000010L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK                                                      0x00000020L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK                                                      0x00000040L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK                                                      0x00000080L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK                                                      0x00000100L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK                                                      0x00000200L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK                                                     0x00000400L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK                                                     0x00001000L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK                                                     0x00002000L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK                                                     0x00004000L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK                                                     0x00008000L</div><div class='add'>+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK                                                    0x40000000L</div><div class='add'>+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK                                                        0x80000000L</div><div class='add'>+//WALL_CLOCK_COUNTER</div><div class='add'>+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT                                                         0x0</div><div class='add'>+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//STREAM_SYNCHRONIZATION</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT                                               0x0</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT                                               0x1</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT                                               0x2</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT                                               0x3</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT                                               0x4</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT                                               0x5</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT                                               0x6</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT                                               0x7</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT                                               0x8</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT                                               0x9</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT                                              0xa</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT                                              0xb</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT                                              0xc</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT                                              0xd</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT                                              0xe</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT                                              0xf</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK                                                 0x00000001L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK                                                 0x00000002L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK                                                 0x00000004L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK                                                 0x00000008L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK                                                 0x00000010L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK                                                 0x00000020L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK                                                 0x00000040L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK                                                 0x00000080L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK                                                 0x00000100L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK                                                 0x00000200L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK                                                0x00000400L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK                                                0x00000800L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK                                                0x00001000L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK                                                0x00002000L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK                                                0x00004000L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK                                                0x00008000L</div><div class='add'>+//CORB_LOWER_BASE_ADDRESS</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT                                               0x7</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L</div><div class='add'>+//CORB_UPPER_BASE_ADDRESS</div><div class='add'>+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT                                               0x0</div><div class='add'>+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_CORB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+//AZCONTROLLER0_CORB_READ_POINTER</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L</div><div class='add'>+//AZCONTROLLER0_CORB_CONTROL</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L</div><div class='add'>+//AZCONTROLLER0_CORB_STATUS</div><div class='add'>+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L</div><div class='add'>+//AZCONTROLLER0_CORB_SIZE</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_RIRB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L</div><div class='add'>+//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT</div><div class='add'>+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0</div><div class='add'>+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL</div><div class='add'>+//AZCONTROLLER0_RIRB_CONTROL</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L</div><div class='add'>+//AZCONTROLLER0_RIRB_STATUS</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L</div><div class='add'>+//AZCONTROLLER0_RIRB_SIZE</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L</div><div class='add'>+//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS</div><div class='add'>+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0</div><div class='add'>+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azendpoint_azdec</div><div class='add'>+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL</div><div class='add'>+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azinputendpoint_azdec</div><div class='add'>+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL</div><div class='add'>+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azcontroller_azdec</div><div class='add'>+//AZCONTROLLER1_CORB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+//AZCONTROLLER1_CORB_READ_POINTER</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L</div><div class='add'>+//AZCONTROLLER1_CORB_CONTROL</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L</div><div class='add'>+//AZCONTROLLER1_CORB_STATUS</div><div class='add'>+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L</div><div class='add'>+//AZCONTROLLER1_CORB_SIZE</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_RIRB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L</div><div class='add'>+//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT</div><div class='add'>+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0</div><div class='add'>+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL</div><div class='add'>+//AZCONTROLLER1_RIRB_CONTROL</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L</div><div class='add'>+//AZCONTROLLER1_RIRB_STATUS</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L</div><div class='add'>+//AZCONTROLLER1_RIRB_SIZE</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L</div><div class='add'>+//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS</div><div class='add'>+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0</div><div class='add'>+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azendpoint_azdec</div><div class='add'>+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL</div><div class='add'>+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azinputendpoint_azdec</div><div class='add'>+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL</div><div class='add'>+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec</div><div class='add'>+//DENTIST_DISPCLK_CNTL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dispdec</div><div class='add'>+//PHYPLLA_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//PHYPLLB_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//PHYPLLC_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//PHYPLLD_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//DP_DTO_DBUF_EN</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L</div><div class='add'>+//DSCCLK3_DTO_PARAM</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPREFCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE__SHIFT                                              0x17</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE__SHIFT                                              0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE__SHIFT                                              0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE__SHIFT                                              0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE_MASK                                                0x00800000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE_MASK                                                0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE_MASK                                                0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE_MASK                                                0x04000000L</div><div class='add'>+//DPSTREAMCLK_CNTL</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT                                                              0x7</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT                                                         0x8</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT                                                              0xb</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT                                                         0xc</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT                                                              0xf</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK                                                           0x00000007L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK                                                                0x00000008L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK                                                           0x00000070L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK                                                                0x00000080L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK                                                                0x00000800L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK                                                           0x00007000L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK                                                                0x00008000L</div><div class='add'>+//REFCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//PHYPLLE_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//DCCG_PERFMON_CNTL2</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT                                                   0x9</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L</div><div class='add'>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK                                                     0x00000200L</div><div class='add'>+//DCCG_GLOBAL_FGCG_REP_CNTL</div><div class='add'>+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT                                            0x0</div><div class='add'>+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK                                              0x00000001L</div><div class='add'>+//DCCG_DS_DTO_INCR</div><div class='add'>+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0</div><div class='add'>+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//DCCG_DS_DTO_MODULO</div><div class='add'>+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0</div><div class='add'>+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DCCG_DS_CNTL</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L</div><div class='add'>+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L</div><div class='add'>+//DCCG_DS_HW_CAL_INTERVAL</div><div class='add'>+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPREFCLK_CNTL</div><div class='add'>+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0</div><div class='add'>+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L</div><div class='add'>+//DCE_VERSION</div><div class='add'>+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0</div><div class='add'>+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8</div><div class='add'>+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL</div><div class='add'>+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L</div><div class='add'>+//DCCG_GTC_CNTL</div><div class='add'>+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0</div><div class='add'>+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L</div><div class='add'>+//DCCG_GTC_DTO_INCR</div><div class='add'>+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0</div><div class='add'>+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DCCG_GTC_DTO_MODULO</div><div class='add'>+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0</div><div class='add'>+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DCCG_GTC_CURRENT</div><div class='add'>+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0</div><div class='add'>+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//SYMCLK32_SE_CNTL</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L</div><div class='add'>+//SYMCLK32_LE_CNTL</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L</div><div class='add'>+//DTBCLK_P_CNTL</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT                                                               0x0</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT                                                                    0x2</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT                                                               0x3</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT                                                                    0x5</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT                                                               0x6</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT                                                                    0x8</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT                                                               0x9</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT                                                                    0xb</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK                                                                 0x00000003L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK                                                                      0x00000004L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK                                                                 0x00000018L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK                                                                      0x00000020L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK                                                                 0x000000C0L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK                                                                      0x00000100L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK                                                                 0x00000600L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK                                                                      0x00000800L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL5</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT                                                0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT                                                0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT                                                0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT                                                0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT                                             0x7</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT                                        0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT                                        0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT                                        0xc</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT                                             0xd</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE__SHIFT                                             0x12</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE__SHIFT                                             0x13</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE__SHIFT                                             0x14</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE__SHIFT                                             0x15</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE__SHIFT                                             0x16</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE__SHIFT                                          0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE__SHIFT                                          0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1c</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK                                                  0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK                                                  0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK                                                  0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK                                                  0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK                                          0x00000040L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK                                               0x00000080L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK                                          0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK                                          0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK                                          0x00001000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK                                               0x00002000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE_MASK                                               0x00040000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE_MASK                                               0x00080000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE_MASK                                               0x00100000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE_MASK                                               0x00200000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE_MASK                                               0x00400000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE_MASK                                            0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE_MASK                                            0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE_MASK                                            0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE_MASK                                            0x08000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE_MASK                                            0x10000000L</div><div class='add'>+//DSCCLK0_DTO_PARAM</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DSCCLK1_DTO_PARAM</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DSCCLK2_DTO_PARAM</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//OTG_PIXEL_RATE_DIV</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1__SHIFT                                                      0x0</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2__SHIFT                                                      0x1</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1__SHIFT                                                      0x3</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2__SHIFT                                                      0x4</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1__SHIFT                                                      0x6</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2__SHIFT                                                      0x7</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1__SHIFT                                                      0x9</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2__SHIFT                                                      0xa</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK1_MASK                                                        0x00000001L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG0_PIXEL_RATE_DIVK2_MASK                                                        0x00000006L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK1_MASK                                                        0x00000008L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG1_PIXEL_RATE_DIVK2_MASK                                                        0x00000030L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK1_MASK                                                        0x00000040L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG2_PIXEL_RATE_DIVK2_MASK                                                        0x00000180L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK1_MASK                                                        0x00000200L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG3_PIXEL_RATE_DIVK2_MASK                                                        0x00000C00L</div><div class='add'>+//MILLISECOND_TIME_BASE_DIV</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L</div><div class='add'>+//DISPCLK_FREQ_CHANGE_CNTL</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L</div><div class='add'>+//DC_MEM_GLOBAL_PWR_REQ_CNTL</div><div class='add'>+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0</div><div class='add'>+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L</div><div class='add'>+//DCCG_PERFMON_CNTL</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L</div><div class='add'>+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L</div><div class='add'>+//DISPCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L</div><div class='add'>+//SOCCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//DCCG_CAC_STATUS</div><div class='add'>+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0</div><div class='add'>+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//MICROSECOND_TIME_BASE_DIV</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1c</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE_MASK                                            0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x08000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE_MASK                                            0x10000000L</div><div class='add'>+//SYMCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//DCCG_DISP_CNTL_REG</div><div class='add'>+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8</div><div class='add'>+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L</div><div class='add'>+//OTG0_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00003000L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO0_PHASE</div><div class='add'>+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO0_MODULO</div><div class='add'>+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG0_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG1_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00003000L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO1_PHASE</div><div class='add'>+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO1_MODULO</div><div class='add'>+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG1_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG2_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00003000L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO2_PHASE</div><div class='add'>+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO2_MODULO</div><div class='add'>+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG2_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG3_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00003000L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO3_PHASE</div><div class='add'>+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO3_MODULO</div><div class='add'>+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG3_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//DPPCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//DPPCLK0_DTO_PARAM</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK1_DTO_PARAM</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK2_DTO_PARAM</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK3_DTO_PARAM</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DCCG_CAC_STATUS2</div><div class='add'>+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0</div><div class='add'>+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL</div><div class='add'>+//SYMCLKA_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL__SHIFT                                                          0x5</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL_MASK                                                            0x000000E0L</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKB_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL__SHIFT                                                          0x5</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL_MASK                                                            0x000000E0L</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKC_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL__SHIFT                                                          0x5</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL_MASK                                                            0x000000E0L</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKD_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL__SHIFT                                                          0x5</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL_MASK                                                            0x000000E0L</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKE_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL__SHIFT                                                          0x5</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL_MASK                                                            0x000000E0L</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//DCCG_SOFT_RESET</div><div class='add'>+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0</div><div class='add'>+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2</div><div class='add'>+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3</div><div class='add'>+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4</div><div class='add'>+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd</div><div class='add'>+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe</div><div class='add'>+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf</div><div class='add'>+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10</div><div class='add'>+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11</div><div class='add'>+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12</div><div class='add'>+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13</div><div class='add'>+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14</div><div class='add'>+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15</div><div class='add'>+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L</div><div class='add'>+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L</div><div class='add'>+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L</div><div class='add'>+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L</div><div class='add'>+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L</div><div class='add'>+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L</div><div class='add'>+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L</div><div class='add'>+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L</div><div class='add'>+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L</div><div class='add'>+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L</div><div class='add'>+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L</div><div class='add'>+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L</div><div class='add'>+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L</div><div class='add'>+//DSCCLK_DTO_CTRL</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_EN__SHIFT                                                                    0x1</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_EN__SHIFT                                                                    0x2</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_EN__SHIFT                                                                    0x3</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_EN__SHIFT                                                                    0x4</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_EN__SHIFT                                                                    0x5</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_EN_MASK                                                                      0x00000002L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_EN_MASK                                                                      0x00000004L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_EN_MASK                                                                      0x00000008L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_EN_MASK                                                                      0x00000010L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_EN_MASK                                                                      0x00000020L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L</div><div class='add'>+//DPPCLK_CTRL</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK0_EN__SHIFT                                                                        0x0</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK1_EN__SHIFT                                                                        0x3</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK2_EN__SHIFT                                                                        0x6</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK3_EN__SHIFT                                                                        0x9</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK0_EN_MASK                                                                          0x00000001L</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK1_EN_MASK                                                                          0x00000008L</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK2_EN_MASK                                                                          0x00000040L</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK3_EN_MASK                                                                          0x00000200L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE__SHIFT                                             0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE__SHIFT                                             0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE__SHIFT                                             0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE__SHIFT                                             0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE__SHIFT                                             0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE__SHIFT                                             0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                      0xf</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE_MASK                                               0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE_MASK                                               0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE_MASK                                               0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE_MASK                                               0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE_MASK                                               0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE_MASK                                               0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE_MASK                                        0x00008000L</div><div class='add'>+//SYMCLK_PSP_CNTL</div><div class='add'>+#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON__SHIFT                                                           0x0</div><div class='add'>+#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON_MASK                                                             0x00000001L</div><div class='add'>+//DCCG_AUDIO_DTO_SOURCE</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L</div><div class='add'>+//DCCG_AUDIO_DTO0_PHASE</div><div class='add'>+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO0_MODULE</div><div class='add'>+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0</div><div class='add'>+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO1_PHASE</div><div class='add'>+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO1_MODULE</div><div class='add'>+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0</div><div class='add'>+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG0_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG1_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG2_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG3_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG4_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG5_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DPPCLK_DTO_CTRL</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L</div><div class='add'>+//DCCG_VSYNC_CNT_CTRL</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L</div><div class='add'>+//DCCG_VSYNC_CNT_INT_CTRL</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L</div><div class='add'>+//FORCE_SYMCLK_DISABLE</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L</div><div class='add'>+//DTBCLK_DTO0_PHASE</div><div class='add'>+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO1_PHASE</div><div class='add'>+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO2_PHASE</div><div class='add'>+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO3_PHASE</div><div class='add'>+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO0_MODULO</div><div class='add'>+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0</div><div class='add'>+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO1_MODULO</div><div class='add'>+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0</div><div class='add'>+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO2_MODULO</div><div class='add'>+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0</div><div class='add'>+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO3_MODULO</div><div class='add'>+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0</div><div class='add'>+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//HDMICHARCLK0_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//PHYASYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYBSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYCSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYDSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYESYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//HDMISTREAMCLK_CNTL</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L</div><div class='add'>+//HDMISTREAMCLK0_DTO_PARAM</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L</div><div class='add'>+//DCCG_AUDIO_DTBCLK_DTO_PHASE</div><div class='add'>+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0</div><div class='add'>+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTBCLK_DTO_MODULO</div><div class='add'>+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0</div><div class='add'>+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL</div><div class='add'>+//DTBCLK_DTO_DBUF_EN</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L</div><div class='add'>+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON0_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON0_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON0_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON0_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON0_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON0_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON0_PERFMON_HI</div><div class='add'>+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON0_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON1_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON1_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON1_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON1_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON1_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON1_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON1_PERFMON_HI</div><div class='add'>+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON1_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+//DMCUB_RBBMIF_SEC_CNTL</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT                                                  0x4</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT                                                  0x8</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL_MASK                                                      0x00000007L</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK                                                    0x00000070L</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK                                                    0x01FFFF00L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_rbbmif_dispdec</div><div class='add'>+//RBBMIF_TIMEOUT</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L</div><div class='add'>+//RBBMIF_STATUS</div><div class='add'>+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0</div><div class='add'>+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//RBBMIF_STATUS_2</div><div class='add'>+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0</div><div class='add'>+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL</div><div class='add'>+//RBBMIF_INT_STATUS</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L</div><div class='add'>+//RBBMIF_TIMEOUT_DIS</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L</div><div class='add'>+//RBBMIF_TIMEOUT_DIS_2</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L</div><div class='add'>+//RBBMIF_STATUS_FLAG</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON2_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON2_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON2_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON2_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON2_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON2_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON2_PERFMON_HI</div><div class='add'>+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON2_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_ihc_dispdec</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_V_UPDATE</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_VSTARTUP</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L</div><div class='add'>+//DC_GPU_TIMER_READ</div><div class='add'>+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0</div><div class='add'>+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DC_GPU_TIMER_READ_CNTL</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L</div><div class='add'>+//DISP_INTERRUPT_STATUS</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT                                                      0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK                                                        0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE20</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE21</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE22</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_VREADY</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_FLIP</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE23</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT__SHIFT                         0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT__SHIFT                         0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT__SHIFT                         0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT__SHIFT                         0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT__SHIFT                       0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT__SHIFT                       0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT__SHIFT                       0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT__SHIFT                       0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_MASK                           0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_MASK                           0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_MASK                           0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_MASK                           0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_MASK                         0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_MASK                         0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_MASK                         0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_MASK                         0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE24</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT                              0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT                              0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT                              0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT                              0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT                              0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK                                0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK                                0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK                                0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK                                0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK                                0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE25</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT                                               0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT                     0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK                                                 0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK                       0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L</div><div class='add'>+//DCCG_INTERRUPT_DEST</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L</div><div class='add'>+//DMU_INTERRUPT_DEST</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x4</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT                                                  0x5</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT                                                  0x6</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT                                                  0x7</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT                                                  0x8</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT                                                0x9</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0xa</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0xb</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0xc</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0xd</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0xe</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0xf</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0x10</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0x11</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0x12</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0x13</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x1a</div><div class='add'>+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1b</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x00000010L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK                                                    0x00000020L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK                                                    0x00000040L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK                                                    0x00000080L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK                                                    0x00000100L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK                                                  0x00000200L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000400L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000800L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00001000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00002000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00004000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00008000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00010000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00040000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00080000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x04000000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x08000000L</div><div class='add'>+//DMU_INTERRUPT_DEST2</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT                                                   0xc</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT                         0xd</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK                                                     0x00001000L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK                           0x00002000L</div><div class='add'>+//DCPG_INTERRUPT_DEST</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L</div><div class='add'>+//DCPG_INTERRUPT_DEST2</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST__SHIFT                                0x6</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST__SHIFT                                0x7</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST__SHIFT                                0x8</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST__SHIFT                                0x9</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xc</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xd</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xe</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xf</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x10</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x11</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x12</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x13</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00008000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00010000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00020000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00040000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00080000L</div><div class='add'>+//MMHUBBUB_INTERRUPT_DEST</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L</div><div class='add'>+//WB_INTERRUPT_DEST</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb</div><div class='add'>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc</div><div class='add'>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd</div><div class='add'>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe</div><div class='add'>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf</div><div class='add'>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10</div><div class='add'>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L</div><div class='add'>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L</div><div class='add'>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L</div><div class='add'>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L</div><div class='add'>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L</div><div class='add'>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L</div><div class='add'>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L</div><div class='add'>+//DCHUB_INTERRUPT_DEST</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L</div><div class='add'>+//DCHUB_PERFCOUNTER_INTERRUPT_DEST</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L</div><div class='add'>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L</div><div class='add'>+//DCHUB_INTERRUPT_DEST2</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L</div><div class='add'>+//DPP_PERFCOUNTER_INTERRUPT_DEST</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L</div><div class='add'>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L</div><div class='add'>+//MPC_INTERRUPT_DEST</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L</div><div class='add'>+//OPP_INTERRUPT_DEST</div><div class='add'>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc</div><div class='add'>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd</div><div class='add'>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L</div><div class='add'>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L</div><div class='add'>+//OPTC_INTERRUPT_DEST</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L</div><div class='add'>+//OTG0_INTERRUPT_DEST</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG1_INTERRUPT_DEST</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG2_INTERRUPT_DEST</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG3_INTERRUPT_DEST</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG4_INTERRUPT_DEST</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG5_INTERRUPT_DEST</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//DIG_INTERRUPT_DEST</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L</div><div class='add'>+//I2C_DDC_HPD_INTERRUPT_DEST</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L</div><div class='add'>+//HDCP_INTERRUPT_DEST</div><div class='add'>+//DIO_INTERRUPT_DEST</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT                                                    0x4</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK                                                      0x00000010L</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L</div><div class='add'>+//DCIO_INTERRUPT_DEST</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L</div><div class='add'>+//HPD_INTERRUPT_DEST</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L</div><div class='add'>+//AZ_INTERRUPT_DEST</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L</div><div class='add'>+//AUX_INTERRUPT_DEST</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L</div><div class='add'>+//DSC_INTERRUPT_DEST</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L</div><div class='add'>+//HPO_INTERRUPT_DEST</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0x2</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0x3</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00000004L</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dmu_misc_dispdec</div><div class='add'>+//CC_DC_PIPE_DIS</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT                                                                    0xc</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK                                                                      0x00001000L</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L</div><div class='add'>+//DMU_CLK_CNTL</div><div class='add'>+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x5</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x6</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0x7</div><div class='add'>+#define DMU_CLK_CNTL__RIOMMU_CLK_SEL__SHIFT                                                                   0x8</div><div class='add'>+#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS__SHIFT                                                              0xc</div><div class='add'>+#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL__SHIFT                                                           0xd</div><div class='add'>+#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP__SHIFT                                                        0x10</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP__SHIFT                                                         0x12</div><div class='add'>+#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x14</div><div class='add'>+#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x16</div><div class='add'>+#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x18</div><div class='add'>+#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP__SHIFT                                                         0x1a</div><div class='add'>+#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS__SHIFT                                                                0x1c</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE__SHIFT                                                        0x1d</div><div class='add'>+#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE__SHIFT                                                         0x1e</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE__SHIFT                                                       0x1f</div><div class='add'>+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000020L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000040L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000080L</div><div class='add'>+#define DMU_CLK_CNTL__RIOMMU_CLK_SEL_MASK                                                                     0x00000100L</div><div class='add'>+#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS_MASK                                                                0x00001000L</div><div class='add'>+#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL_MASK                                                             0x00006000L</div><div class='add'>+#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP_MASK                                                          0x00030000L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP_MASK                                                           0x000C0000L</div><div class='add'>+#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x00300000L</div><div class='add'>+#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x00C00000L</div><div class='add'>+#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x03000000L</div><div class='add'>+#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP_MASK                                                           0x0C000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS_MASK                                                                  0x10000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE_MASK                                                          0x20000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE_MASK                                                           0x40000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE_MASK                                                         0x80000000L</div><div class='add'>+//DMCUB_SMU_INTERRUPT_CNTL</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT                                                        0x10</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK                                                      0x00000001L</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK                                                          0xFFFF0000L</div><div class='add'>+//SMU_INTERRUPT_CONTROL</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L</div><div class='add'>+//ZSC_CNTL</div><div class='add'>+#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT                                                                     0x0</div><div class='add'>+#define ZSC_CNTL__LONO_PWR_DN__SHIFT                                                                          0x8</div><div class='add'>+#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK                                                                       0x00000003L</div><div class='add'>+#define ZSC_CNTL__LONO_PWR_DN_MASK                                                                            0x00000100L</div><div class='add'>+//ZSC_CNTL2</div><div class='add'>+#define ZSC_CNTL2__ALLOW_Z10__SHIFT                                                                           0x0</div><div class='add'>+#define ZSC_CNTL2__ALLOW_Z10_MASK                                                                             0x00000001L</div><div class='add'>+//DMU_MISC_ALLOW_DS_FORCE</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L</div><div class='add'>+//ZSC_STATUS</div><div class='add'>+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT                                                          0x0</div><div class='add'>+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT                                                   0x4</div><div class='add'>+#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT                                                                   0x8</div><div class='add'>+#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT                                                                   0x9</div><div class='add'>+#define ZSC_STATUS__FENCE_STATUS__SHIFT                                                                       0xa</div><div class='add'>+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK                                                            0x00000007L</div><div class='add'>+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK                                                     0x00000070L</div><div class='add'>+#define ZSC_STATUS__FENCE_REQ_STATUS_MASK                                                                     0x00000100L</div><div class='add'>+#define ZSC_STATUS__FENCE_ACK_STATUS_MASK                                                                     0x00000200L</div><div class='add'>+#define ZSC_STATUS__FENCE_STATUS_MASK                                                                         0x00000C00L</div><div class='add'>+//DMU_DISPCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY__SHIFT                                      0x0</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY__SHIFT                                     0x4</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY_MASK                                        0x0000000FL</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY_MASK                                       0x00000FF0L</div><div class='add'>+//DMU_SOCCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY__SHIFT                                        0x0</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY__SHIFT                                       0x4</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY_MASK                                          0x0000000FL</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY_MASK                                         0x00000FF0L</div><div class='add'>+//ZPR_CLK_UNGATE_DELAY</div><div class='add'>+#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY_MASK                                                       0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dc_pg_dispdec</div><div class='add'>+//DOMAIN0_PG_CONFIG</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN0_PG_STATUS</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN1_PG_CONFIG</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN1_PG_STATUS</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN2_PG_CONFIG</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN2_PG_STATUS</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN3_PG_CONFIG</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN3_PG_STATUS</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN16_PG_CONFIG</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN16_PG_STATUS</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN17_PG_CONFIG</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN17_PG_STATUS</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN18_PG_CONFIG</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN18_PG_STATUS</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN19_PG_CONFIG</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN19_PG_STATUS</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN22_PG_CONFIG</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN22_PG_STATUS</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN23_PG_CONFIG</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN23_PG_STATUS</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN24_PG_CONFIG</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN24_PG_STATUS</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN25_PG_CONFIG</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN25_PG_STATUS</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DCPG_INTERRUPT_STATUS</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L</div><div class='add'>+//DCPG_INTERRUPT_STATUS_2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L</div><div class='add'>+//DCPG_INTERRUPT_STATUS_3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED__SHIFT                                        0x0</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED__SHIFT                                        0x2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED__SHIFT                                        0x4</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED__SHIFT                                        0x6</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L</div><div class='add'>+//DCPG_INTERRUPT_CONTROL_1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L</div><div class='add'>+//DCPG_INTERRUPT_CONTROL_2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L</div><div class='add'>+//DCPG_INTERRUPT_CONTROL_3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK__SHIFT                                           0x0</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR__SHIFT                                          0x1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK__SHIFT                                         0x2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK__SHIFT                                           0x4</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR__SHIFT                                          0x5</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK__SHIFT                                         0x6</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK__SHIFT                                           0x8</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK__SHIFT                                         0xa</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK__SHIFT                                           0xc</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR__SHIFT                                          0xd</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK__SHIFT                                         0xe</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK_MASK                                             0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR_MASK                                            0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK_MASK                                           0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK_MASK                                             0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR_MASK                                            0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK_MASK                                           0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK_MASK                                             0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK_MASK                                           0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK_MASK                                             0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR_MASK                                            0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK_MASK                                           0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L</div><div class='add'>+//DC_IP_REQUEST_CNTL</div><div class='add'>+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0</div><div class='add'>+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L</div><div class='add'>+//LONO_MEM_PWR_REQ_CNTL</div><div class='add'>+#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS__SHIFT                                                    0x0</div><div class='add'>+#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS_MASK                                                      0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dmu_dmcub_dispdec</div><div class='add'>+//DMCUB_REGION0_OFFSET</div><div class='add'>+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION0_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION1_OFFSET</div><div class='add'>+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION1_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION2_OFFSET</div><div class='add'>+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION2_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION4_OFFSET</div><div class='add'>+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION4_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION5_OFFSET</div><div class='add'>+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION5_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION6_OFFSET</div><div class='add'>+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION6_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION7_OFFSET</div><div class='add'>+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION7_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION0_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION1_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION2_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION4_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION5_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION6_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION7_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW0_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW1_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW2_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW3_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW4_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW5_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW6_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW7_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW0_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW1_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW2_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW3_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW4_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW5_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW6_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW7_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW0_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW0_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW1_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW1_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW2_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW2_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW3_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW3_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW4_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW4_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW5_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW5_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW6_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW6_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW7_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW7_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_INTERRUPT_ENABLE</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT                                                    0xd</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT                                                    0xe</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT                                                    0xf</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT                                                    0x10</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT                                                  0x11</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0x12</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK                                                      0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK                                                      0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK                                                      0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK                                                      0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK                                                    0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00040000L</div><div class='add'>+//DMCUB_INTERRUPT_ACK</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT                                                      0xd</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT                                                      0xe</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT                                                      0xf</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT                                                      0x10</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT                                                    0x11</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0x12</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK                                                        0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK                                                        0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK                                                        0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK                                                        0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK                                                      0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00040000L</div><div class='add'>+//DMCUB_INTERRUPT_STATUS</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT                                                  0xd</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT                                                  0xe</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT                                                  0xf</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT                                                  0x10</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT                                                0x11</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0x12</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0x13</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0x14</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT__SHIFT                                             0x15</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT__SHIFT                                         0x16</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK                                                    0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK                                                    0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK                                                    0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK                                                    0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK                                                  0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00040000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00080000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00100000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT_MASK                                               0x00200000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT_MASK                                           0x00400000L</div><div class='add'>+//DMCUB_INTERRUPT_TYPE</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT                                                    0xd</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT                                                    0xe</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT                                                    0xf</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT                                                    0x10</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT                                                  0x11</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0x12</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK                                                      0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK                                                      0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK                                                      0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK                                                      0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK                                                    0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00040000L</div><div class='add'>+//DMCUB_EXT_INTERRUPT_STATUS</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L</div><div class='add'>+//DMCUB_EXT_INTERRUPT_CTXID</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL</div><div class='add'>+//DMCUB_EXT_INTERRUPT_ACK</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L</div><div class='add'>+//DMCUB_INST_FETCH_FAULT_ADDR</div><div class='add'>+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0</div><div class='add'>+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_DATA_WRITE_FAULT_ADDR</div><div class='add'>+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0</div><div class='add'>+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_SEC_CNTL</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L</div><div class='add'>+//DMCUB_MEM_CNTL</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L</div><div class='add'>+//DMCUB_INBOX0_BASE_ADDRESS</div><div class='add'>+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX0_SIZE</div><div class='add'>+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX0_WPTR</div><div class='add'>+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX0_RPTR</div><div class='add'>+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_BASE_ADDRESS</div><div class='add'>+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_SIZE</div><div class='add'>+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_WPTR</div><div class='add'>+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_RPTR</div><div class='add'>+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_BASE_ADDRESS</div><div class='add'>+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_SIZE</div><div class='add'>+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_WPTR</div><div class='add'>+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_RPTR</div><div class='add'>+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_BASE_ADDRESS</div><div class='add'>+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_SIZE</div><div class='add'>+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_WPTR</div><div class='add'>+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_RPTR</div><div class='add'>+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_TIMER_TRIGGER0</div><div class='add'>+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0</div><div class='add'>+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_TIMER_TRIGGER1</div><div class='add'>+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0</div><div class='add'>+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_TIMER_WINDOW</div><div class='add'>+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L</div><div class='add'>+//DMCUB_SCRATCH0</div><div class='add'>+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH1</div><div class='add'>+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH2</div><div class='add'>+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH3</div><div class='add'>+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH4</div><div class='add'>+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH5</div><div class='add'>+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH6</div><div class='add'>+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH7</div><div class='add'>+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH8</div><div class='add'>+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH9</div><div class='add'>+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH10</div><div class='add'>+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH11</div><div class='add'>+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH12</div><div class='add'>+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH13</div><div class='add'>+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH14</div><div class='add'>+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH15</div><div class='add'>+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH16</div><div class='add'>+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH17</div><div class='add'>+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH18</div><div class='add'>+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_CNTL</div><div class='add'>+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0</div><div class='add'>+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8</div><div class='add'>+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10</div><div class='add'>+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12</div><div class='add'>+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13</div><div class='add'>+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14</div><div class='add'>+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL</div><div class='add'>+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L</div><div class='add'>+//DMCUB_GPINT_DATAIN0</div><div class='add'>+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN1</div><div class='add'>+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAOUT</div><div class='add'>+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR</div><div class='add'>+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0</div><div class='add'>+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_LS_WAKE_INT_ENABLE</div><div class='add'>+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0</div><div class='add'>+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DMCUB_MEM_PWR_CNTL</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L</div><div class='add'>+//DMCUB_TIMER_CURRENT</div><div class='add'>+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_DBG_BUS_SELECT</div><div class='add'>+//DMCUB_PROC_ID</div><div class='add'>+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL</div><div class='add'>+//DMCUB_CNTL2</div><div class='add'>+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0</div><div class='add'>+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L</div><div class='add'>+//DMCUB_GPINT_DATAIN2</div><div class='add'>+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN3</div><div class='add'>+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN4</div><div class='add'>+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN5</div><div class='add'>+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN6</div><div class='add'>+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_REGION3_TMR_AXI_SPACE</div><div class='add'>+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT                                       0x0</div><div class='add'>+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK                                         0x07L</div><div class='add'>+//DMCUB_SCRATCH19</div><div class='add'>+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH20</div><div class='add'>+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH21</div><div class='add'>+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH22</div><div class='add'>+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH23</div><div class='add'>+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec</div><div class='add'>+//DWB_ENABLE_CLK_CTRL</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS__SHIFT                                                          0x18</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS_MASK                                                            0x01000000L</div><div class='add'>+//DWB_MEM_PWR_CTRL</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L</div><div class='add'>+//FC_MODE_CTRL</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4</div><div class='add'>+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8</div><div class='add'>+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc</div><div class='add'>+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10</div><div class='add'>+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L</div><div class='add'>+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L</div><div class='add'>+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L</div><div class='add'>+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L</div><div class='add'>+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L</div><div class='add'>+//FC_FLOW_CTRL</div><div class='add'>+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL</div><div class='add'>+//FC_WINDOW_START</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L</div><div class='add'>+//FC_WINDOW_SIZE</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L</div><div class='add'>+//FC_SOURCE_SIZE</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L</div><div class='add'>+//DWB_UPDATE_CTRL</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L</div><div class='add'>+//DWB_CRC_CTRL</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L</div><div class='add'>+//DWB_CRC_MASK_R_G</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L</div><div class='add'>+//DWB_CRC_MASK_B_A</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L</div><div class='add'>+//DWB_CRC_VAL_R_G</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L</div><div class='add'>+//DWB_CRC_VAL_B_A</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L</div><div class='add'>+//DWB_OUT_CTRL</div><div class='add'>+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0</div><div class='add'>+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14</div><div class='add'>+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L</div><div class='add'>+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L</div><div class='add'>+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L</div><div class='add'>+//DWB_MMHUBBUB_BACKPRESSURE_CNT</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL</div><div class='add'>+//DWB_HOST_READ_CONTROL</div><div class='add'>+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL</div><div class='add'>+//DWB_OVERFLOW_STATUS</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L</div><div class='add'>+//DWB_OVERFLOW_COUNTER</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L</div><div class='add'>+//DWB_SOFT_RESET</div><div class='add'>+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0</div><div class='add'>+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec</div><div class='add'>+//DWB_HDR_MULT_COEF</div><div class='add'>+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0</div><div class='add'>+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL</div><div class='add'>+//DWB_GAMUT_REMAP_MODE</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L</div><div class='add'>+//DWB_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0</div><div class='add'>+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L</div><div class='add'>+//DWB_GAMUT_REMAPA_C11_C12</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C13_C14</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C21_C22</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C23_C24</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C31_C32</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C33_C34</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C11_C12</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C13_C14</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C21_C22</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C23_C24</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C31_C32</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C33_C34</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_OGAM_CONTROL</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L</div><div class='add'>+//DWB_OGAM_LUT_INDEX</div><div class='add'>+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0</div><div class='add'>+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL</div><div class='add'>+//DWB_OGAM_LUT_DATA</div><div class='add'>+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0</div><div class='add'>+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL</div><div class='add'>+//DWB_OGAM_LUT_CONTROL</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L</div><div class='add'>+//DWB_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON3_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON3_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON3_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON3_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON3_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON3_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON3_PERFMON_HI</div><div class='add'>+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON3_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec</div><div class='add'>+//MCIF_WB_BUFMGR_SW_CONTROL</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L</div><div class='add'>+//MCIF_WB_BUFMGR_STATUS</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x0</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x1</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000001L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000002L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L</div><div class='add'>+//MCIF_WB_BUF_PITCH</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L</div><div class='add'>+//MCIF_WB_BUF_1_STATUS</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_1_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_BUF_2_STATUS</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_2_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_BUF_3_STATUS</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_3_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_BUF_4_STATUS</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_4_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_ARBITRATION_CONTROL</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L</div><div class='add'>+//MCIF_WB_SCLK_CHANGE</div><div class='add'>+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0</div><div class='add'>+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUFMGR_VCE_CONTROL</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L</div><div class='add'>+//MCIF_WB_NB_PSTATE_CONTROL</div><div class='add'>+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1</div><div class='add'>+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L</div><div class='add'>+//MCIF_WB_CLOCK_GATER_CONTROL</div><div class='add'>+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0</div><div class='add'>+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L</div><div class='add'>+//MCIF_WB_SELF_REFRESH_CONTROL</div><div class='add'>+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1</div><div class='add'>+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L</div><div class='add'>+//MULTI_LEVEL_QOS_CTRL</div><div class='add'>+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0</div><div class='add'>+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL</div><div class='add'>+//MCIF_WB_SECURITY_LEVEL</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                                 0x0</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT                                                          0x4</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                                   0x00000007L</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK                                                            0x00000070L</div><div class='add'>+//MCIF_WB_BUF_LUMA_SIZE</div><div class='add'>+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0</div><div class='add'>+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL</div><div class='add'>+//MCIF_WB_BUF_CHROMA_SIZE</div><div class='add'>+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0</div><div class='add'>+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_1_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_2_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_3_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_4_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_PSTATE_CHANGE_DURATION_VBI</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x0</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x10</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0x0000FFFFL</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0xFFFF0000L</div><div class='add'>+//MCIF_WB_VMID_CONTROL</div><div class='add'>+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0</div><div class='add'>+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL</div><div class='add'>+//MCIF_WB_MIN_TTO</div><div class='add'>+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0</div><div class='add'>+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON4_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON4_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON4_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON4_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON4_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON4_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON4_PERFMON_HI</div><div class='add'>+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON4_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec</div><div class='add'>+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT                           0x1f</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK                             0x80000000L</div><div class='add'>+//MCIF_WB_WATERMARK</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L</div><div class='add'>+//MMHUBBUB_WARMUP_CONFIG</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L</div><div class='add'>+//MMHUBBUB_WARMUP_CONTROL_STATUS</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L</div><div class='add'>+//MMHUBBUB_WARMUP_BASE_ADDR_LOW</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL</div><div class='add'>+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL</div><div class='add'>+//MMHUBBUB_WARMUP_ADDR_REGION</div><div class='add'>+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL</div><div class='add'>+//MMHUBBUB_MIN_TTO</div><div class='add'>+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0</div><div class='add'>+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL</div><div class='add'>+//MMHUBBUB_CTRL</div><div class='add'>+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0</div><div class='add'>+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L</div><div class='add'>+//WBIF_SMU_WM_CONTROL</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L</div><div class='add'>+//WBIF0_MISC_CTRL</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L</div><div class='add'>+//WBIF0_PHASE0_OUTSTANDING_COUNTER</div><div class='add'>+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0</div><div class='add'>+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL</div><div class='add'>+//WBIF0_PHASE1_OUTSTANDING_COUNTER</div><div class='add'>+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0</div><div class='add'>+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL</div><div class='add'>+//MMHUBBUB_MEM_PWR_STATUS</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L</div><div class='add'>+//MMHUBBUB_MEM_PWR_CNTL</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L</div><div class='add'>+//MMHUBBUB_CLOCK_CNTL</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x11</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK                                                       0x00020000L</div><div class='add'>+//MMHUBBUB_SOFT_RESET</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L</div><div class='add'>+//DMU_IF_ERR_STATUS</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L</div><div class='add'>+//MMHUBBUB_CLIENT_UNIT_ID</div><div class='add'>+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8</div><div class='add'>+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L</div><div class='add'>+//MMHUBBUB_WARMUP_VMID_CONTROL</div><div class='add'>+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0controller_dispdec</div><div class='add'>+//AZALIA_CONTROLLER_CLOCK_GATING</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L</div><div class='add'>+//AZALIA_AUDIO_DTO</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L</div><div class='add'>+//AZALIA_AUDIO_DTO_CONTROL</div><div class='add'>+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8</div><div class='add'>+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L</div><div class='add'>+//AZALIA_SOCCLK_CONTROL</div><div class='add'>+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1</div><div class='add'>+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L</div><div class='add'>+//AZALIA_UNDERFLOW_FILLER_SAMPLE</div><div class='add'>+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0</div><div class='add'>+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_DATA_DMA_CONTROL</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L</div><div class='add'>+//AZALIA_BDL_DMA_CONTROL</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L</div><div class='add'>+//AZALIA_RIRB_AND_DP_CONTROL</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L</div><div class='add'>+//AZALIA_CORB_DMA_CONTROL</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L</div><div class='add'>+//AZALIA_GLOBAL_CAPABILITIES</div><div class='add'>+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1</div><div class='add'>+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L</div><div class='add'>+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L</div><div class='add'>+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L</div><div class='add'>+//AZALIA_INPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L</div><div class='add'>+//AZALIA_CONTROLLER_DEBUG</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL1</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL2</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL3</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC0_RESULT</div><div class='add'>+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL1</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL2</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL3</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC1_RESULT</div><div class='add'>+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CONTROL0</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L</div><div class='add'>+//AZALIA_CRC0_CONTROL1</div><div class='add'>+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CONTROL2</div><div class='add'>+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL</div><div class='add'>+//AZALIA_CRC0_CONTROL3</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L</div><div class='add'>+//AZALIA_CRC0_RESULT</div><div class='add'>+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0</div><div class='add'>+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CONTROL0</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L</div><div class='add'>+//AZALIA_CRC1_CONTROL1</div><div class='add'>+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CONTROL2</div><div class='add'>+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL</div><div class='add'>+//AZALIA_CRC1_CONTROL3</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L</div><div class='add'>+//AZALIA_CRC1_RESULT</div><div class='add'>+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0</div><div class='add'>+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_MEM_PWR_CTRL</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L</div><div class='add'>+//AZALIA_MEM_PWR_STATUS</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0root_dispdec</div><div class='add'>+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L</div><div class='add'>+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL</div><div class='add'>+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0</div><div class='add'>+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL</div><div class='add'>+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L</div><div class='add'>+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET1</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET2</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET3</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET4</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET5</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_GTC_GROUP_OFFSET6</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//REG_DC_AUDIO_PORT_CONNECTIVITY</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L</div><div class='add'>+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_az_misc_dispdec</div><div class='add'>+//AZ_CLOCK_CNTL</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0</div><div class='add'>+#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS__SHIFT                                                          0x1</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x4</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x8</div><div class='add'>+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0xc</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_GATE_DIS__SHIFT                                                                   0x10</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY__SHIFT                                                              0x14</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY__SHIFT                                                             0x18</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L</div><div class='add'>+#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS_MASK                                                            0x00000002L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000010L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00000100L</div><div class='add'>+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x0000F000L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_GATE_DIS_MASK                                                                     0x00010000L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY_MASK                                                                0x00F00000L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY_MASK                                                               0xFF000000L</div><div class='add'>+//AZ_MEM_GLOBAL_PWR_REQ_CNTL</div><div class='add'>+#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0</div><div class='add'>+#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON5_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON5_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON5_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON5_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON5_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON5_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON5_PERFMON_HI</div><div class='add'>+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON5_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream0_dispdec</div><div class='add'>+//AZF0STREAM0_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM0_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream1_dispdec</div><div class='add'>+//AZF0STREAM1_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM1_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream2_dispdec</div><div class='add'>+//AZF0STREAM2_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM2_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream3_dispdec</div><div class='add'>+//AZF0STREAM3_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM3_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream4_dispdec</div><div class='add'>+//AZF0STREAM4_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM4_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream5_dispdec</div><div class='add'>+//AZF0STREAM5_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM5_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream6_dispdec</div><div class='add'>+//AZF0STREAM6_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM6_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream7_dispdec</div><div class='add'>+//AZF0STREAM7_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM7_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream8_dispdec</div><div class='add'>+//AZF0STREAM8_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM8_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream9_dispdec</div><div class='add'>+//AZF0STREAM9_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM9_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream10_dispdec</div><div class='add'>+//AZF0STREAM10_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM10_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream11_dispdec</div><div class='add'>+//AZF0STREAM11_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM11_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream12_dispdec</div><div class='add'>+//AZF0STREAM12_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM12_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream13_dispdec</div><div class='add'>+//AZF0STREAM13_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM13_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream14_dispdec</div><div class='add'>+//AZF0STREAM14_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM14_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0stream15_dispdec</div><div class='add'>+//AZF0STREAM15_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM15_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec</div><div class='add'>+//DCHUBBUB_ARB_DF_REQ_OUTSTAND</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xa</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x16</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x0007FC00L</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0x7FC00000L</div><div class='add'>+//DCHUBBUB_ARB_SAT_LEVEL</div><div class='add'>+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_ARB_QOS_FORCE</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT         0x9</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT                                          0xc</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK           0x00000200L</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK                                            0x0000F000L</div><div class='add'>+//DCHUBBUB_ARB_DRAM_STATE_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0x2</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT                                          0x7</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE__SHIFT                  0xd</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP__SHIFT                           0xf</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE__SHIFT                 0x10</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE__SHIFT                0x11</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY__SHIFT                0x12</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS__SHIFT                        0x18</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000004L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK                                            0x00000080L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE_MASK                    0x00002000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP_MASK                             0x00008000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE_MASK                   0x00010000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE_MASK                  0x00020000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY_MASK                  0x00040000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS_MASK                          0xFF000000L</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT                                         0x1</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT                0x8</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT               0x9</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0xa</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT  0xb</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK                                         0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK                                           0x00000002L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK                  0x00000100L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK                 0x00000200L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000400L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK  0x00000800L</div><div class='add'>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK                 0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT         0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK           0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT           0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK             0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK                 0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT         0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK           0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT           0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK             0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK                 0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT         0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK           0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT           0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK             0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK                 0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT         0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK           0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT           0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK             0x000FFFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_HOSTVM_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING__SHIFT                            0x2</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x3</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x4</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x5</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x6</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x7</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING_MASK                              0x00000004L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000008L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000020L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000040L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000080L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L</div><div class='add'>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L</div><div class='add'>+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT                    0x10</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT                                         0x18</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK                      0x00010000L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK                                           0x01000000L</div><div class='add'>+//DCHUBBUB_ARB_MALL_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK                                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+//DCHUBBUB_ARB_TIMEOUT_ENABLE</div><div class='add'>+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L</div><div class='add'>+//DCHUBBUB_GLOBAL_TIMER_CNTL</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L</div><div class='add'>+//SURFACE_CHECK0_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK0_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//SURFACE_CHECK1_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK1_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//SURFACE_CHECK2_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK2_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//SURFACE_CHECK3_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK3_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//VTG0_CONTROL</div><div class='add'>+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//VTG1_CONTROL</div><div class='add'>+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//VTG2_CONTROL</div><div class='add'>+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//VTG3_CONTROL</div><div class='add'>+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//DCHUBBUB_SOFT_RESET</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L</div><div class='add'>+//DCHUBBUB_CLOCK_CNTL</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x7</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK                                                       0x00000080L</div><div class='add'>+//DCFCLK_CNTL</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L</div><div class='add'>+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x003FF800L</div><div class='add'>+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x14</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF00000L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L</div><div class='add'>+//DCHUBBUB_VLINE_SNAPSHOT</div><div class='add'>+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0</div><div class='add'>+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L</div><div class='add'>+//DCHUBBUB_CTRL_STATUS</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L</div><div class='add'>+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L</div><div class='add'>+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L</div><div class='add'>+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L</div><div class='add'>+//FMON_CTRL</div><div class='add'>+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0</div><div class='add'>+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1</div><div class='add'>+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4</div><div class='add'>+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5</div><div class='add'>+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7</div><div class='add'>+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9</div><div class='add'>+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc</div><div class='add'>+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16</div><div class='add'>+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b</div><div class='add'>+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L</div><div class='add'>+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L</div><div class='add'>+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L</div><div class='add'>+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L</div><div class='add'>+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L</div><div class='add'>+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L</div><div class='add'>+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L</div><div class='add'>+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L</div><div class='add'>+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec</div><div class='add'>+//DCHUBBUB_SDPIF_CFG0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW__SHIFT                                                        0x10</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW_MASK                                                          0x00010000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L</div><div class='add'>+//DCHUBBUB_SDPIF_CFG1</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT                                                 0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK                                                   0x00000200L</div><div class='add'>+//DCHUBBUB_SDPIF_CFG2</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000F00L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L</div><div class='add'>+//VM_REQUEST_PHYSICAL</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L</div><div class='add'>+//DCHUBBUB_FORCE_IO_STATUS_0</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L</div><div class='add'>+//DCHUBBUB_FORCE_IO_STATUS_1</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL</div><div class='add'>+//DCN_VM_FB_LOCATION_BASE</div><div class='add'>+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0</div><div class='add'>+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL</div><div class='add'>+//DCN_VM_FB_LOCATION_TOP</div><div class='add'>+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0</div><div class='add'>+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DCN_VM_FB_OFFSET</div><div class='add'>+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0</div><div class='add'>+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL</div><div class='add'>+//DCN_VM_AGP_BOT</div><div class='add'>+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0</div><div class='add'>+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL</div><div class='add'>+//DCN_VM_AGP_TOP</div><div class='add'>+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0</div><div class='add'>+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL</div><div class='add'>+//DCN_VM_AGP_BASE</div><div class='add'>+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0</div><div class='add'>+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL</div><div class='add'>+//DCN_VM_LOCAL_HBM_ADDRESS_START</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL</div><div class='add'>+//DCN_VM_LOCAL_HBM_ADDRESS_END</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL</div><div class='add'>+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x0000000FL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x000000F0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x00000F00L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x0000F000L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_NOALLOC</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT                                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT                                               0x1</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT                                               0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT                                               0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK                                                 0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK                                                 0x00000002L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK                                                 0x00000004L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK                                                 0x00000008L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x0000000FL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x000000F0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x00000F00L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x0000F000L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT                               0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT                               0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT                               0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK                                 0x0000000FL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK                                 0x000000F0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK                                 0x00000F00L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK                                 0x0000F000L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT                               0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT                               0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x0000000FL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x000000F0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK                                 0x00000F00L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK                                 0x0000F000L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT                                   0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT                                   0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x0000000FL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x000000F0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK                                     0x00000F00L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK                                     0x0000F000L</div><div class='add'>+//SDPIF_REQUEST_RATE_LIMIT</div><div class='add'>+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT                                             0x0</div><div class='add'>+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK                                               0x00000FFFL</div><div class='add'>+//DCHUBBUB_SDPIF_MEM_PWR_CTRL</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L</div><div class='add'>+//DCHUBBUB_SDPIF_MEM_PWR_STATUS</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec</div><div class='add'>+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L</div><div class='add'>+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L</div><div class='add'>+//DCHUBBUB_CRC_CTRL</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L</div><div class='add'>+//DCHUBBUB_CRC0_VAL_R</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_R__DCHUBBUB_CRC0_R_CR__SHIFT                                                        0x0</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_R__DCHUBBUB_CRC0_R_CR_MASK                                                          0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_CRC0_VAL_G</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                         0x0</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_G__DCHUBBUB_CRC0_G_Y_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_CRC0_VAL_B</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_B__DCHUBBUB_CRC0_B_CB__SHIFT                                                        0x0</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_B__DCHUBBUB_CRC0_B_CB_MASK                                                          0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_CRC0_VAL_A</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                       0x0</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_A__DCHUBBUB_CRC0_ALPHA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_DCC_STAT_CNTL</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L</div><div class='add'>+//DCHUBBUB_DCC_STAT0</div><div class='add'>+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_DCC_STAT1</div><div class='add'>+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_DCC_STAT2</div><div class='add'>+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_COMPBUF_CTRL</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L</div><div class='add'>+//DCHUBBUB_DET0_CTRL</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_DET1_CTRL</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_DET2_CTRL</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_DET3_CTRL</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_MEM_PWR_MODE_CTRL</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L</div><div class='add'>+//COMPBUF_MEM_PWR_CTRL_1</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L</div><div class='add'>+//COMPBUF_MEM_PWR_CTRL_2</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY__SHIFT                                           0x8</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY__SHIFT                                             0xc</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY_MASK                                             0x00000F00L</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY_MASK                                               0x0000F000L</div><div class='add'>+//DCHUBBUB_MEM_PWR_STATUS</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L</div><div class='add'>+//COMPBUF_RESERVED_SPACE</div><div class='add'>+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0</div><div class='add'>+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10</div><div class='add'>+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL</div><div class='add'>+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L</div><div class='add'>+//DCHUBBUB_DEBUG_CTRL_0</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH__SHIFT                                                          0x0</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH__SHIFT                                                       0x8</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH__SHIFT                                                           0xc</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                                                               0x10</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE__SHIFT                               0x1b</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE__SHIFT                                         0x1c</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE__SHIFT                                     0x1d</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE__SHIFT                                         0x1e</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE__SHIFT                                       0x1f</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH_MASK                                                            0x000000FFL</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH_MASK                                                         0x00000F00L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH_MASK                                                             0x0000F000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                                                 0x07FF0000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE_MASK                                 0x08000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE_MASK                                           0x10000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE_MASK                                       0x20000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE_MASK                                           0x40000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE_MASK                                         0x80000000L</div><div class='add'>+//DCHUBBUB_CRC1_VAL_R</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_R__DCHUBBUB_CRC1_R_CR__SHIFT                                                        0x0</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_R__DCHUBBUB_CRC1_R_CR_MASK                                                          0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_CRC1_VAL_G</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                         0x0</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_G__DCHUBBUB_CRC1_G_Y_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_CRC1_VAL_B</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_B__DCHUBBUB_CRC1_B_CB__SHIFT                                                        0x0</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_B__DCHUBBUB_CRC1_B_CB_MASK                                                          0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_CRC1_VAL_A</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                       0x0</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_A__DCHUBBUB_CRC1_ALPHA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec</div><div class='add'>+//DCN_VM_CONTEXT0_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_DEFAULT_ADDR_MSB</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L</div><div class='add'>+//DCN_VM_DEFAULT_ADDR_LSB</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_FAULT_CNTL</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L</div><div class='add'>+//DCN_VM_FAULT_STATUS</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L</div><div class='add'>+//DCN_VM_FAULT_ADDR_MSB</div><div class='add'>+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0</div><div class='add'>+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL</div><div class='add'>+//DCN_VM_FAULT_ADDR_LSB</div><div class='add'>+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0</div><div class='add'>+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON6_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON6_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON6_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON6_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON6_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON6_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON6_PERFMON_HI</div><div class='add'>+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON6_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec</div><div class='add'>+//HUBP0_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP0_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP0_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP0_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP0_DCHUBP_CNTL</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP0_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP0_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP0_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+//HUBP0_DCHUBP_MALL_SUB_VP</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L</div><div class='add'>+//HUBP0_HUBPREQ_DEBUG_DB</div><div class='add'>+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0</div><div class='add'>+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//HUBP0_HUBPREQ_DEBUG</div><div class='add'>+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0</div><div class='add'>+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f</div><div class='add'>+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL</div><div class='add'>+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L</div><div class='add'>+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L</div><div class='add'>+//HUBP0_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L</div><div class='add'>+//HUBPREQ0_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L</div><div class='add'>+//HUBPREQ0_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ0_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ0_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ0_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ0_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ0_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ0_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ0_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ0_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ0_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ0_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ0_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ0_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ0_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L</div><div class='add'>+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET0_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET0_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET0_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_0_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L</div><div class='add'>+//CURSOR0_0_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_0_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_0_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L</div><div class='add'>+//CURSOR0_0_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_0_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_0_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL</div><div class='add'>+//CURSOR0_0_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_0_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_0_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_0_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_0_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_0_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_0_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_0_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_0_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON7_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON7_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON7_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON7_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON7_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON7_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON7_PERFMON_HI</div><div class='add'>+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON7_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec</div><div class='add'>+//HUBP1_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP1_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP1_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP1_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP1_DCHUBP_CNTL</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP1_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP1_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP1_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+//HUBP1_DCHUBP_MALL_SUB_VP</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L</div><div class='add'>+//HUBP1_HUBPREQ_DEBUG_DB</div><div class='add'>+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0</div><div class='add'>+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//HUBP1_HUBPREQ_DEBUG</div><div class='add'>+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0</div><div class='add'>+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f</div><div class='add'>+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL</div><div class='add'>+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L</div><div class='add'>+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L</div><div class='add'>+//HUBP1_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L</div><div class='add'>+//HUBPREQ1_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L</div><div class='add'>+//HUBPREQ1_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ1_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ1_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ1_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ1_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ1_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ1_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ1_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ1_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ1_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ1_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ1_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ1_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ1_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L</div><div class='add'>+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET1_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET1_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET1_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_1_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L</div><div class='add'>+//CURSOR0_1_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_1_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_1_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L</div><div class='add'>+//CURSOR0_1_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_1_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_1_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL</div><div class='add'>+//CURSOR0_1_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_1_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_1_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_1_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_1_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_1_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_1_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_1_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_1_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON8_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON8_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON8_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON8_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON8_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON8_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON8_PERFMON_HI</div><div class='add'>+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON8_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec</div><div class='add'>+//HUBP2_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP2_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP2_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP2_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP2_DCHUBP_CNTL</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP2_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP2_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP2_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+//HUBP2_DCHUBP_MALL_SUB_VP</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L</div><div class='add'>+//HUBP2_HUBPREQ_DEBUG_DB</div><div class='add'>+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0</div><div class='add'>+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//HUBP2_HUBPREQ_DEBUG</div><div class='add'>+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0</div><div class='add'>+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f</div><div class='add'>+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL</div><div class='add'>+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L</div><div class='add'>+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L</div><div class='add'>+//HUBP2_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L</div><div class='add'>+//HUBPREQ2_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L</div><div class='add'>+//HUBPREQ2_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ2_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ2_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ2_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ2_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ2_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ2_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ2_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ2_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ2_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ2_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ2_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ2_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ2_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L</div><div class='add'>+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET2_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET2_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET2_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_2_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L</div><div class='add'>+//CURSOR0_2_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_2_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_2_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L</div><div class='add'>+//CURSOR0_2_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_2_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_2_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL</div><div class='add'>+//CURSOR0_2_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_2_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_2_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_2_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_2_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_2_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_2_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_2_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_2_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON9_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L</div><div class='add'>+//DC_PERFMON9_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L</div><div class='add'>+//DC_PERFMON9_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L</div><div class='add'>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L</div><div class='add'>+//DC_PERFMON9_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L</div><div class='add'>+//DC_PERFMON9_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL</div><div class='add'>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L</div><div class='add'>+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L</div><div class='add'>+//DC_PERFMON9_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0</div><div class='add'>+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON9_PERFMON_HI</div><div class='add'>+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0</div><div class='add'>+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L</div><div class='add'>+//DC_PERFMON9_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0</div><div class='add'>+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec</div><div class='add'>+//HUBP3_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP3_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP3_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP3_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP3_DCHUBP_CNTL</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP3_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP3_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP3_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+//HUBP3_DCHUBP_MALL_SUB_VP</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT                                                 0x1</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT                                                 0xf</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK                                                 0x00000001L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK                                                   0x00007FFEL</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK                                                   0x1FFF8000L</div><div class='add'>+//HUBP3_HUBPREQ_DEBUG_DB</div><div class='add'>+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0</div><div class='add'>+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//HUBP3_HUBPREQ_DEBUG</div><div class='add'>+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0</div><div class='add'>+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT                                 0x1f</div><div class='add'>+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0x7FFFFFFFL</div><div class='add'>+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK                                   0x80000000L</div><div class='add'>+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L</div><div class='add'>+//HUBP3_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT                                                     0xd</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x14</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT                                            0x15</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT                                                   0x16</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT                                              0x17</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK                                                       0x00002000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK                                              0x00100000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK                                              0x00200000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK                                                     0x00400000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK                                                0x00800000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L</div><div class='add'>+//HUBPREQ3_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L</div><div class='add'>+//HUBPREQ3_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ3_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ3_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ3_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ3_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ3_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ3_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ3_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ3_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ3_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ3_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ3_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ3_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ3_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L</div><div class='add'>+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x00003FFFL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET3_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET3_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET3_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_3_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L</div><div class='add'>+//CURSOR0_3_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_3_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_3_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L</div><div class='add'>+//CURSOR0_3_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_3_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_3_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL</div><div class='add'>+//CURSOR0_3_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_3_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_3_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_3_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_3_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_3_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_3_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_3_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_3_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON10_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON10_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON10_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON10_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON10_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON10_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON10_PERFMON_HI</div><div class='add'>+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON10_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG0_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG0_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG0_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG0_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG0_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec</div><div class='add'>+//CNVC_CUR0_CURSOR0_CONTROL</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L</div><div class='add'>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L</div><div class='add'>+//CNVC_CUR0_CURSOR0_COLOR0</div><div class='add'>+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR0_CURSOR0_COLOR1</div><div class='add'>+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS</div><div class='add'>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10</div><div class='add'>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec</div><div class='add'>+//DSCL0_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L</div><div class='add'>+//DSCL0_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL0_SCL_MODE</div><div class='add'>+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL0_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL0_DSCL_CONTROL</div><div class='add'>+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL0_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL0_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_UPDATE</div><div class='add'>+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL0_DSCL_AUTOCAL</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L</div><div class='add'>+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L</div><div class='add'>+//DSCL0_OTG_H_BLANK</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL0_OTG_V_BLANK</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL0_RECOUT_START</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L</div><div class='add'>+//DSCL0_RECOUT_SIZE</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL0_MPC_SIZE</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL0_LB_DATA_FORMAT</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL0_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL0_LB_V_COUNTER</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL0_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL0_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL0_OBUF_CONTROL</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL0_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec</div><div class='add'>+//CM0_CM_CONTROL</div><div class='add'>+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM0_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM0_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_CONTROL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL</div><div class='add'>+//CM0_CM_GAMUT_REMAP_C11_C12</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_C13_C14</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_C21_C22</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_C23_C24</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_C31_C32</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_C33_C34</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_B_C11_C12</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_B_C13_C14</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_B_C21_C22</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_B_C23_C24</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_B_C31_C32</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMUT_REMAP_B_C33_C34</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_BIAS_CR_R</div><div class='add'>+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM0_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM0_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM0_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_HDR_MULT_COEF</div><div class='add'>+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM0_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM0_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM0_CM_DEALPHA</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM0_CM_COEF_FORMAT</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//CM0_DPP_CRC_VAL_R</div><div class='add'>+#define CM0_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT                                                                0x0</div><div class='add'>+#define CM0_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM0_DPP_CRC_VAL_G</div><div class='add'>+#define CM0_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define CM0_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//CM0_DPP_CRC_VAL_B</div><div class='add'>+#define CM0_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define CM0_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM0_DPP_CRC_VAL_A</div><div class='add'>+#define CM0_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT                                                               0x0</div><div class='add'>+#define CM0_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP0_DPP_CONTROL</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP0_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP0_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP0_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON11_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON11_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON11_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON11_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON11_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON11_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON11_PERFMON_HI</div><div class='add'>+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON11_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG1_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG1_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG1_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG1_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG1_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec</div><div class='add'>+//CNVC_CUR1_CURSOR0_CONTROL</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L</div><div class='add'>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L</div><div class='add'>+//CNVC_CUR1_CURSOR0_COLOR0</div><div class='add'>+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR1_CURSOR0_COLOR1</div><div class='add'>+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS</div><div class='add'>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10</div><div class='add'>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec</div><div class='add'>+//DSCL1_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L</div><div class='add'>+//DSCL1_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL1_SCL_MODE</div><div class='add'>+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL1_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL1_DSCL_CONTROL</div><div class='add'>+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL1_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL1_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_UPDATE</div><div class='add'>+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL1_DSCL_AUTOCAL</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L</div><div class='add'>+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L</div><div class='add'>+//DSCL1_OTG_H_BLANK</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL1_OTG_V_BLANK</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL1_RECOUT_START</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L</div><div class='add'>+//DSCL1_RECOUT_SIZE</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL1_MPC_SIZE</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL1_LB_DATA_FORMAT</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL1_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL1_LB_V_COUNTER</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL1_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL1_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL1_OBUF_CONTROL</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL1_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec</div><div class='add'>+//CM1_CM_CONTROL</div><div class='add'>+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM1_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM1_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_CONTROL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL</div><div class='add'>+//CM1_CM_GAMUT_REMAP_C11_C12</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_C13_C14</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_C21_C22</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_C23_C24</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_C31_C32</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_C33_C34</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_B_C11_C12</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_B_C13_C14</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_B_C21_C22</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_B_C23_C24</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_B_C31_C32</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMUT_REMAP_B_C33_C34</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_BIAS_CR_R</div><div class='add'>+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM1_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM1_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM1_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_HDR_MULT_COEF</div><div class='add'>+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM1_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM1_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM1_CM_DEALPHA</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM1_CM_COEF_FORMAT</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM1_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//CM1_DPP_CRC_VAL_R</div><div class='add'>+#define CM1_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT                                                                0x0</div><div class='add'>+#define CM1_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM1_DPP_CRC_VAL_G</div><div class='add'>+#define CM1_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define CM1_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//CM1_DPP_CRC_VAL_B</div><div class='add'>+#define CM1_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define CM1_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM1_DPP_CRC_VAL_A</div><div class='add'>+#define CM1_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT                                                               0x0</div><div class='add'>+#define CM1_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP1_DPP_CONTROL</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP1_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP1_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP1_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON12_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON12_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON12_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON12_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON12_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON12_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON12_PERFMON_HI</div><div class='add'>+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON12_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG2_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG2_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG2_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG2_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG2_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec</div><div class='add'>+//CNVC_CUR2_CURSOR0_CONTROL</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L</div><div class='add'>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L</div><div class='add'>+//CNVC_CUR2_CURSOR0_COLOR0</div><div class='add'>+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR2_CURSOR0_COLOR1</div><div class='add'>+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS</div><div class='add'>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10</div><div class='add'>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec</div><div class='add'>+//DSCL2_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L</div><div class='add'>+//DSCL2_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL2_SCL_MODE</div><div class='add'>+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL2_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL2_DSCL_CONTROL</div><div class='add'>+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL2_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL2_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_UPDATE</div><div class='add'>+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL2_DSCL_AUTOCAL</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L</div><div class='add'>+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L</div><div class='add'>+//DSCL2_OTG_H_BLANK</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL2_OTG_V_BLANK</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL2_RECOUT_START</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L</div><div class='add'>+//DSCL2_RECOUT_SIZE</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL2_MPC_SIZE</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL2_LB_DATA_FORMAT</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL2_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL2_LB_V_COUNTER</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL2_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL2_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL2_OBUF_CONTROL</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL2_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec</div><div class='add'>+//CM2_CM_CONTROL</div><div class='add'>+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM2_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM2_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_CONTROL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL</div><div class='add'>+//CM2_CM_GAMUT_REMAP_C11_C12</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_C13_C14</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_C21_C22</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_C23_C24</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_C31_C32</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_C33_C34</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_B_C11_C12</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_B_C13_C14</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_B_C21_C22</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_B_C23_C24</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_B_C31_C32</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMUT_REMAP_B_C33_C34</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_BIAS_CR_R</div><div class='add'>+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM2_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM2_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM2_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_HDR_MULT_COEF</div><div class='add'>+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM2_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM2_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM2_CM_DEALPHA</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM2_CM_COEF_FORMAT</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM2_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM2_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//CM2_DPP_CRC_VAL_R</div><div class='add'>+#define CM2_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT                                                                0x0</div><div class='add'>+#define CM2_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM2_DPP_CRC_VAL_G</div><div class='add'>+#define CM2_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define CM2_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//CM2_DPP_CRC_VAL_B</div><div class='add'>+#define CM2_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define CM2_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM2_DPP_CRC_VAL_A</div><div class='add'>+#define CM2_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT                                                               0x0</div><div class='add'>+#define CM2_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP2_DPP_CONTROL</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP2_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP2_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP2_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON13_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON13_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON13_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON13_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON13_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON13_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON13_PERFMON_HI</div><div class='add'>+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON13_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG3_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG3_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG3_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG3_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG3_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec</div><div class='add'>+//CNVC_CUR3_CURSOR0_CONTROL</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L</div><div class='add'>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L</div><div class='add'>+//CNVC_CUR3_CURSOR0_COLOR0</div><div class='add'>+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR3_CURSOR0_COLOR1</div><div class='add'>+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL</div><div class='add'>+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS</div><div class='add'>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10</div><div class='add'>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec</div><div class='add'>+//DSCL3_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00030000L</div><div class='add'>+//DSCL3_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL3_SCL_MODE</div><div class='add'>+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL3_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL3_DSCL_CONTROL</div><div class='add'>+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL3_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL3_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_UPDATE</div><div class='add'>+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL3_DSCL_AUTOCAL</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L</div><div class='add'>+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L</div><div class='add'>+//DSCL3_OTG_H_BLANK</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL3_OTG_V_BLANK</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL3_RECOUT_START</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L</div><div class='add'>+//DSCL3_RECOUT_SIZE</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL3_MPC_SIZE</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL3_LB_DATA_FORMAT</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL3_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL3_LB_V_COUNTER</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL3_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL3_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL3_OBUF_CONTROL</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL3_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec</div><div class='add'>+//CM3_CM_CONTROL</div><div class='add'>+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM3_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM3_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_CONTROL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL</div><div class='add'>+//CM3_CM_GAMUT_REMAP_C11_C12</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_C13_C14</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_C21_C22</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_C23_C24</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_C31_C32</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_C33_C34</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_B_C11_C12</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_B_C13_C14</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_B_C21_C22</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_B_C23_C24</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_B_C31_C32</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMUT_REMAP_B_C33_C34</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_BIAS_CR_R</div><div class='add'>+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM3_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM3_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM3_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_HDR_MULT_COEF</div><div class='add'>+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM3_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM3_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM3_CM_DEALPHA</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM3_CM_COEF_FORMAT</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L</div><div class='add'>+//CM3_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM3_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//CM3_DPP_CRC_VAL_R</div><div class='add'>+#define CM3_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT                                                                0x0</div><div class='add'>+#define CM3_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM3_DPP_CRC_VAL_G</div><div class='add'>+#define CM3_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define CM3_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//CM3_DPP_CRC_VAL_B</div><div class='add'>+#define CM3_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define CM3_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK                                                                  0xFFFFFFFFL</div><div class='add'>+//CM3_DPP_CRC_VAL_A</div><div class='add'>+#define CM3_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT                                                               0x0</div><div class='add'>+#define CM3_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP3_DPP_CONTROL</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP3_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP3_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP3_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON14_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON14_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON14_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON14_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON14_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON14_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON14_PERFMON_HI</div><div class='add'>+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON14_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc0_dispdec</div><div class='add'>+//MPCC0_MPCC_TOP_SEL</div><div class='add'>+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC0_MPCC_BOT_SEL</div><div class='add'>+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC0_MPCC_OPP_ID</div><div class='add'>+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC0_MPCC_CONTROL</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC0_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC0_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC0_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC0_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC0_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC0_MPCC_BG_R_CR</div><div class='add'>+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC0_MPCC_BG_G_Y</div><div class='add'>+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC0_MPCC_BG_B_CB</div><div class='add'>+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC0_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC0_MPCC_STATUS</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc1_dispdec</div><div class='add'>+//MPCC1_MPCC_TOP_SEL</div><div class='add'>+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC1_MPCC_BOT_SEL</div><div class='add'>+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC1_MPCC_OPP_ID</div><div class='add'>+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC1_MPCC_CONTROL</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC1_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC1_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC1_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC1_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC1_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC1_MPCC_BG_R_CR</div><div class='add'>+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC1_MPCC_BG_G_Y</div><div class='add'>+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC1_MPCC_BG_B_CB</div><div class='add'>+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC1_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC1_MPCC_STATUS</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc2_dispdec</div><div class='add'>+//MPCC2_MPCC_TOP_SEL</div><div class='add'>+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC2_MPCC_BOT_SEL</div><div class='add'>+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC2_MPCC_OPP_ID</div><div class='add'>+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC2_MPCC_CONTROL</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC2_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC2_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC2_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC2_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC2_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC2_MPCC_BG_R_CR</div><div class='add'>+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC2_MPCC_BG_G_Y</div><div class='add'>+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC2_MPCC_BG_B_CB</div><div class='add'>+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC2_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC2_MPCC_STATUS</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc3_dispdec</div><div class='add'>+//MPCC3_MPCC_TOP_SEL</div><div class='add'>+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC3_MPCC_BOT_SEL</div><div class='add'>+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC3_MPCC_OPP_ID</div><div class='add'>+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC3_MPCC_CONTROL</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC3_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC3_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC3_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC3_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC3_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC3_MPCC_BG_R_CR</div><div class='add'>+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC3_MPCC_BG_G_Y</div><div class='add'>+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC3_MPCC_BG_B_CB</div><div class='add'>+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC3_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC3_MPCC_STATUS</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec</div><div class='add'>+//MPC_CLOCK_CONTROL</div><div class='add'>+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1</div><div class='add'>+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4</div><div class='add'>+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L</div><div class='add'>+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L</div><div class='add'>+//MPC_SOFT_RESET</div><div class='add'>+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0</div><div class='add'>+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1</div><div class='add'>+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2</div><div class='add'>+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f</div><div class='add'>+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L</div><div class='add'>+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L</div><div class='add'>+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L</div><div class='add'>+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L</div><div class='add'>+//MPC_CRC_CTRL</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L</div><div class='add'>+//MPC_CRC_SEL_CONTROL</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L</div><div class='add'>+//MPC_PERFMON_EVENT_CTRL</div><div class='add'>+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0</div><div class='add'>+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L</div><div class='add'>+//MPC_BYPASS_BG_AR</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L</div><div class='add'>+//MPC_BYPASS_BG_GB</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L</div><div class='add'>+//MPC_HOST_READ_CONTROL</div><div class='add'>+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0</div><div class='add'>+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL</div><div class='add'>+//MPC_DPP_PENDING_STATUS</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L</div><div class='add'>+//MPC_PENDING_STATUS_MISC</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET1</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET1</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET1</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET1</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET1</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET2</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET2</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET2</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET2</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET2</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET3</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET3</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET3</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET3</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET3</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//MPC_CRC_RESULT_A</div><div class='add'>+#define MPC_CRC_RESULT_A__MPC_CRC_RESULT_A__SHIFT                                                             0x0</div><div class='add'>+#define MPC_CRC_RESULT_A__MPC_CRC_RESULT_A_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//MPC_CRC_RESULT_R</div><div class='add'>+#define MPC_CRC_RESULT_R__MPC_CRC_RESULT_R__SHIFT                                                             0x0</div><div class='add'>+#define MPC_CRC_RESULT_R__MPC_CRC_RESULT_R_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//MPC_CRC_RESULT_G</div><div class='add'>+#define MPC_CRC_RESULT_G__MPC_CRC_RESULT_G__SHIFT                                                             0x0</div><div class='add'>+#define MPC_CRC_RESULT_G__MPC_CRC_RESULT_G_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//MPC_CRC_RESULT_B</div><div class='add'>+#define MPC_CRC_RESULT_B__MPC_CRC_RESULT_B__SHIFT                                                             0x0</div><div class='add'>+#define MPC_CRC_RESULT_B__MPC_CRC_RESULT_B_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//MPC_DWB0_MUX</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON15_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON15_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON15_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON15_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON15_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON15_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON15_PERFMON_HI</div><div class='add'>+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON15_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec</div><div class='add'>+//MPC_OUT0_MUX</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT0_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT0_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT0_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT1_MUX</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT1_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT1_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT1_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT2_MUX</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT2_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT2_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT2_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT3_MUX</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT3_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT3_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT3_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT_CSC_COEF_FORMAT</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L</div><div class='add'>+//MPC_OUT0_CSC_MODE</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT0_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_MODE</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT1_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_MODE</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT2_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_MODE</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT3_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm0_dispdec</div><div class='add'>+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM0_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_CNTL</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM0_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_THRES_12</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_THRES_34</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM0_DC_ABM1_DEBUG_MISC</div><div class='add'>+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM0_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_1</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_2</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_3</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_4</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_5</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_6</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_7</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_8</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_9</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_10</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_11</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_12</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_13</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_14</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_15</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_16</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_17</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_18</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_19</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_20</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_21</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_22</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_23</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_24</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm1_dispdec</div><div class='add'>+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM1_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_CNTL</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM1_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_THRES_12</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_THRES_34</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM1_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_1</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_2</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_3</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_4</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_5</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_6</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_7</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_8</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_9</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_10</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_11</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_12</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_13</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_14</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_15</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_16</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_17</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_18</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_19</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_20</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_21</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_22</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_23</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_24</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm2_dispdec</div><div class='add'>+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM2_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_CNTL</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM2_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_THRES_12</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_THRES_34</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM2_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_1</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_2</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_3</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_4</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_5</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_6</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_7</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_8</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_9</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_10</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_11</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_12</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_13</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_14</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_15</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_16</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_17</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_18</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_19</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_20</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_21</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_22</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_23</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_24</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_abm3_dispdec</div><div class='add'>+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM3_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_CNTL</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM3_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_THRES_12</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_THRES_34</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM3_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_1</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_2</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_3</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_4</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_5</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_6</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_7</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_8</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_9</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_10</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_11</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_12</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_13</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_14</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_15</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_16</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_17</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_18</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_19</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_20</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_21</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_22</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_23</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_24</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg0_dispdec</div><div class='add'>+//DPG0_DPG_CONTROL</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG0_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG0_DPG_DIMENSIONS</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG0_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG0_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG0_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG0_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG0_DPG_STATUS</div><div class='add'>+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+//DPG0_OPP_PIPE_CRC_RESULTA</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT                                               0x0</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG0_OPP_PIPE_CRC_RESULTR</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT                                               0x0</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG0_OPP_PIPE_CRC_RESULTG</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT                                               0x0</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG0_OPP_PIPE_CRC_RESULTB</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT                                               0x0</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG0_OPP_PIPE_CRC_RESULTC</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT                                               0x0</div><div class='add'>+#define DPG0_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt0_dispdec</div><div class='add'>+//FMT0_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT0_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT0_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT0_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT0_FMT_CONTROL</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT0_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT0_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT0_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT0_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT0_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT0_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT0_FMT_422_CONTROL</div><div class='add'>+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf0_dispdec</div><div class='add'>+//OPPBUF0_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF0_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF0_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF0_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe0_dispdec</div><div class='add'>+//OPP_PIPE0_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg1_dispdec</div><div class='add'>+//DPG1_DPG_CONTROL</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG1_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG1_DPG_DIMENSIONS</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG1_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG1_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG1_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG1_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG1_DPG_STATUS</div><div class='add'>+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+//DPG1_OPP_PIPE_CRC_RESULTA</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT                                               0x0</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG1_OPP_PIPE_CRC_RESULTR</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT                                               0x0</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG1_OPP_PIPE_CRC_RESULTG</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT                                               0x0</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG1_OPP_PIPE_CRC_RESULTB</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT                                               0x0</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG1_OPP_PIPE_CRC_RESULTC</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT                                               0x0</div><div class='add'>+#define DPG1_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt1_dispdec</div><div class='add'>+//FMT1_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT1_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT1_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT1_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT1_FMT_CONTROL</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT1_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT1_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT1_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT1_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT1_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT1_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT1_FMT_422_CONTROL</div><div class='add'>+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf1_dispdec</div><div class='add'>+//OPPBUF1_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF1_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF1_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF1_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe1_dispdec</div><div class='add'>+//OPP_PIPE1_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg2_dispdec</div><div class='add'>+//DPG2_DPG_CONTROL</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG2_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG2_DPG_DIMENSIONS</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG2_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG2_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG2_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG2_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG2_DPG_STATUS</div><div class='add'>+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+//DPG2_OPP_PIPE_CRC_RESULTA</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT                                               0x0</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG2_OPP_PIPE_CRC_RESULTR</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT                                               0x0</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG2_OPP_PIPE_CRC_RESULTG</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT                                               0x0</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG2_OPP_PIPE_CRC_RESULTB</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT                                               0x0</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG2_OPP_PIPE_CRC_RESULTC</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT                                               0x0</div><div class='add'>+#define DPG2_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt2_dispdec</div><div class='add'>+//FMT2_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT2_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT2_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT2_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT2_FMT_CONTROL</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT2_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT2_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT2_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT2_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT2_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT2_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT2_FMT_422_CONTROL</div><div class='add'>+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf2_dispdec</div><div class='add'>+//OPPBUF2_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF2_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF2_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF2_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe2_dispdec</div><div class='add'>+//OPP_PIPE2_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dpg3_dispdec</div><div class='add'>+//DPG3_DPG_CONTROL</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG3_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG3_DPG_DIMENSIONS</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG3_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG3_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG3_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG3_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG3_DPG_STATUS</div><div class='add'>+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+//DPG3_OPP_PIPE_CRC_RESULTA</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT                                               0x0</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG3_OPP_PIPE_CRC_RESULTR</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT                                               0x0</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG3_OPP_PIPE_CRC_RESULTG</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT                                               0x0</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG3_OPP_PIPE_CRC_RESULTB</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT                                               0x0</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DPG3_OPP_PIPE_CRC_RESULTC</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT                                               0x0</div><div class='add'>+#define DPG3_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_fmt3_dispdec</div><div class='add'>+//FMT3_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT3_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT3_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT3_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT3_FMT_CONTROL</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT3_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT3_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT3_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT3_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT3_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT3_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT3_FMT_422_CONTROL</div><div class='add'>+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_oppbuf3_dispdec</div><div class='add'>+//OPPBUF3_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF3_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF3_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF3_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe3_dispdec</div><div class='add'>+//OPP_PIPE3_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm0_dispdec</div><div class='add'>+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm1_dispdec</div><div class='add'>+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm2_dispdec</div><div class='add'>+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_dscrm3_dispdec</div><div class='add'>+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_top_dispdec</div><div class='add'>+//OPP_TOP_CLK_CONTROL</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS__SHIFT                                                          0x18</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS_MASK                                                            0x01000000L</div><div class='add'>+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0</div><div class='add'>+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON16_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON16_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON16_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON16_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON16_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON16_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON16_PERFMON_HI</div><div class='add'>+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON16_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm0_dispdec</div><div class='add'>+//ODM0_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM0_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM0_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM0_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM0_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM0_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM0_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM0_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+//ODM0_OPTC_UNDERFLOW_THRESHOLD</div><div class='add'>+#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT                                        0x0</div><div class='add'>+#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK                                          0x01FFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm1_dispdec</div><div class='add'>+//ODM1_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM1_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM1_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM1_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM1_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM1_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM1_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM1_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+//ODM1_OPTC_UNDERFLOW_THRESHOLD</div><div class='add'>+#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT                                        0x0</div><div class='add'>+#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK                                          0x01FFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm2_dispdec</div><div class='add'>+//ODM2_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM2_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM2_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM2_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM2_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM2_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM2_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM2_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+//ODM2_OPTC_UNDERFLOW_THRESHOLD</div><div class='add'>+#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT                                        0x0</div><div class='add'>+#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK                                          0x01FFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_odm3_dispdec</div><div class='add'>+//ODM3_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM3_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM3_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM3_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM3_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM3_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM3_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM3_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+//ODM3_OPTC_UNDERFLOW_THRESHOLD</div><div class='add'>+#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT                                        0x0</div><div class='add'>+#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK                                          0x01FFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg0_dispdec</div><div class='add'>+//OTG0_OTG_H_TOTAL</div><div class='add'>+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG0_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_H_SYNC_A</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG0_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG0_OTG_V_TOTAL</div><div class='add'>+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG0_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG0_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG0_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_V_SYNC_A</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG0_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG0_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG0_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG0_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG0_OTG_CONTROL</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG0_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG0_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG0_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG0_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG0_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG0_OTG_STATUS</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG0_OTG_STATUS_POSITION</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG0_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG0_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG0_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG0_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG0_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG0_OTG_COUNT_RESET</div><div class='add'>+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG0_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG0_OTG_STEREO_STATUS</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG0_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG0_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG0_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG0_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG0_OTG_MASTER_EN</div><div class='add'>+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG0_OTG_CRC_CNTL</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT                                                            0x2</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK                                                              0x00000004L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG0_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG0_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG0_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG0_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG0_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG0_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG0_OTG_VREADY_PARAM</div><div class='add'>+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG0_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG0_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG0_OTG_GSL_CONTROL</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG0_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG0_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG0_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_DRR_CONTROL</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG0_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG0_OTG_DSC_START_POSITION</div><div class='add'>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL</div><div class='add'>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L</div><div class='add'>+//OTG0_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG0_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg1_dispdec</div><div class='add'>+//OTG1_OTG_H_TOTAL</div><div class='add'>+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG1_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_H_SYNC_A</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG1_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG1_OTG_V_TOTAL</div><div class='add'>+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG1_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG1_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG1_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_V_SYNC_A</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG1_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG1_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG1_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG1_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG1_OTG_CONTROL</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG1_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG1_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG1_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG1_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG1_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG1_OTG_STATUS</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG1_OTG_STATUS_POSITION</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG1_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG1_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG1_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG1_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG1_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG1_OTG_COUNT_RESET</div><div class='add'>+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG1_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG1_OTG_STEREO_STATUS</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG1_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG1_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG1_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG1_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG1_OTG_MASTER_EN</div><div class='add'>+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG1_OTG_CRC_CNTL</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT                                                            0x2</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK                                                              0x00000004L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG1_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG1_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG1_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG1_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG1_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG1_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG1_OTG_VREADY_PARAM</div><div class='add'>+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG1_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG1_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG1_OTG_GSL_CONTROL</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG1_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG1_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG1_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_DRR_CONTROL</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG1_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG1_OTG_DSC_START_POSITION</div><div class='add'>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL</div><div class='add'>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L</div><div class='add'>+//OTG1_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG1_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg2_dispdec</div><div class='add'>+//OTG2_OTG_H_TOTAL</div><div class='add'>+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG2_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_H_SYNC_A</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG2_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG2_OTG_V_TOTAL</div><div class='add'>+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG2_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG2_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG2_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_V_SYNC_A</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG2_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG2_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG2_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG2_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG2_OTG_CONTROL</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG2_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG2_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG2_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG2_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG2_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG2_OTG_STATUS</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG2_OTG_STATUS_POSITION</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG2_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG2_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG2_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG2_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG2_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG2_OTG_COUNT_RESET</div><div class='add'>+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG2_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG2_OTG_STEREO_STATUS</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG2_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG2_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG2_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG2_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG2_OTG_MASTER_EN</div><div class='add'>+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG2_OTG_CRC_CNTL</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT                                                            0x2</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK                                                              0x00000004L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG2_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG2_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG2_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG2_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG2_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG2_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG2_OTG_VREADY_PARAM</div><div class='add'>+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG2_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG2_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG2_OTG_GSL_CONTROL</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG2_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG2_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG2_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_DRR_CONTROL</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG2_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG2_OTG_DSC_START_POSITION</div><div class='add'>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL</div><div class='add'>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L</div><div class='add'>+//OTG2_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG2_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg3_dispdec</div><div class='add'>+//OTG3_OTG_H_TOTAL</div><div class='add'>+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG3_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_H_SYNC_A</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG3_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG3_OTG_V_TOTAL</div><div class='add'>+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG3_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG3_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG3_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_V_SYNC_A</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG3_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG3_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG3_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG3_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG3_OTG_CONTROL</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG3_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG3_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG3_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG3_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG3_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG3_OTG_STATUS</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG3_OTG_STATUS_POSITION</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG3_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG3_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG3_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG3_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG3_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG3_OTG_COUNT_RESET</div><div class='add'>+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG3_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG3_OTG_STEREO_STATUS</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG3_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG3_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG3_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG3_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG3_OTG_MASTER_EN</div><div class='add'>+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG3_OTG_CRC_CNTL</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT                                                            0x2</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK                                                              0x00000004L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG3_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG3_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG3_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG3_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG3_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG3_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG3_OTG_VREADY_PARAM</div><div class='add'>+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG3_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG3_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG3_OTG_GSL_CONTROL</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG3_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG3_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG3_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_DRR_CONTROL</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG3_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG3_OTG_DSC_START_POSITION</div><div class='add'>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL</div><div class='add'>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L</div><div class='add'>+//OTG3_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG3_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc320_dispdec</div><div class='add'>+//OTG_CRC320_OTG_CRC0_DATA_R32</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_R32__CRC0_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_R32__CRC0_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC0_DATA_G32</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_G32__CRC0_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_G32__CRC0_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC0_DATA_B32</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_B32__CRC0_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_B32__CRC0_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC0_DATA_C32</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_C32__CRC0_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_C32__CRC0_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC0_DATA_AES</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC0_DATA_AES__CRC0_AES_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC1_DATA_R32</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_R32__CRC1_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_R32__CRC1_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC1_DATA_G32</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_G32__CRC1_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_G32__CRC1_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC1_DATA_B32</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_B32__CRC1_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_B32__CRC1_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC1_DATA_C32</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_C32__CRC1_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC1_DATA_C32__CRC1_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC2_DATA_R32</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_R32__CRC2_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_R32__CRC2_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC2_DATA_G32</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_G32__CRC2_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_G32__CRC2_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC2_DATA_B32</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_B32__CRC2_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_B32__CRC2_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC2_DATA_C32</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_C32__CRC2_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC2_DATA_C32__CRC2_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC3_DATA_R32</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_R32__CRC3_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_R32__CRC3_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC3_DATA_G32</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_G32__CRC3_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_G32__CRC3_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC3_DATA_B32</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_B32__CRC3_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_B32__CRC3_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC320_OTG_CRC3_DATA_C32</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_C32__CRC3_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC320_OTG_CRC3_DATA_C32__CRC3_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc321_dispdec</div><div class='add'>+//OTG_CRC321_OTG_CRC0_DATA_R32</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_R32__CRC0_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_R32__CRC0_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC0_DATA_G32</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_G32__CRC0_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_G32__CRC0_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC0_DATA_B32</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_B32__CRC0_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_B32__CRC0_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC0_DATA_C32</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_C32__CRC0_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_C32__CRC0_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC0_DATA_AES</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC0_DATA_AES__CRC0_AES_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC1_DATA_R32</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_R32__CRC1_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_R32__CRC1_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC1_DATA_G32</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_G32__CRC1_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_G32__CRC1_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC1_DATA_B32</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_B32__CRC1_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_B32__CRC1_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC1_DATA_C32</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_C32__CRC1_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC1_DATA_C32__CRC1_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC2_DATA_R32</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_R32__CRC2_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_R32__CRC2_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC2_DATA_G32</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_G32__CRC2_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_G32__CRC2_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC2_DATA_B32</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_B32__CRC2_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_B32__CRC2_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC2_DATA_C32</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_C32__CRC2_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC2_DATA_C32__CRC2_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC3_DATA_R32</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_R32__CRC3_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_R32__CRC3_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC3_DATA_G32</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_G32__CRC3_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_G32__CRC3_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC3_DATA_B32</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_B32__CRC3_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_B32__CRC3_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC321_OTG_CRC3_DATA_C32</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_C32__CRC3_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC321_OTG_CRC3_DATA_C32__CRC3_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc322_dispdec</div><div class='add'>+//OTG_CRC322_OTG_CRC0_DATA_R32</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_R32__CRC0_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_R32__CRC0_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC0_DATA_G32</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_G32__CRC0_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_G32__CRC0_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC0_DATA_B32</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_B32__CRC0_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_B32__CRC0_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC0_DATA_C32</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_C32__CRC0_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_C32__CRC0_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC0_DATA_AES</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC0_DATA_AES__CRC0_AES_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC1_DATA_R32</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_R32__CRC1_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_R32__CRC1_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC1_DATA_G32</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_G32__CRC1_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_G32__CRC1_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC1_DATA_B32</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_B32__CRC1_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_B32__CRC1_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC1_DATA_C32</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_C32__CRC1_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC1_DATA_C32__CRC1_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC2_DATA_R32</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_R32__CRC2_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_R32__CRC2_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC2_DATA_G32</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_G32__CRC2_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_G32__CRC2_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC2_DATA_B32</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_B32__CRC2_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_B32__CRC2_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC2_DATA_C32</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_C32__CRC2_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC2_DATA_C32__CRC2_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC3_DATA_R32</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_R32__CRC3_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_R32__CRC3_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC3_DATA_G32</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_G32__CRC3_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_G32__CRC3_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC3_DATA_B32</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_B32__CRC3_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_B32__CRC3_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC322_OTG_CRC3_DATA_C32</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_C32__CRC3_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC322_OTG_CRC3_DATA_C32__CRC3_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_otg_crc323_dispdec</div><div class='add'>+//OTG_CRC323_OTG_CRC0_DATA_R32</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_R32__CRC0_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_R32__CRC0_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC0_DATA_G32</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_G32__CRC0_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_G32__CRC0_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC0_DATA_B32</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_B32__CRC0_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_B32__CRC0_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC0_DATA_C32</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_C32__CRC0_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_C32__CRC0_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC0_DATA_AES</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC0_DATA_AES__CRC0_AES_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC1_DATA_R32</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_R32__CRC1_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_R32__CRC1_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC1_DATA_G32</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_G32__CRC1_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_G32__CRC1_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC1_DATA_B32</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_B32__CRC1_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_B32__CRC1_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC1_DATA_C32</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_C32__CRC1_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC1_DATA_C32__CRC1_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC2_DATA_R32</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_R32__CRC2_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_R32__CRC2_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC2_DATA_G32</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_G32__CRC2_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_G32__CRC2_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC2_DATA_B32</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_B32__CRC2_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_B32__CRC2_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC2_DATA_C32</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_C32__CRC2_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC2_DATA_C32__CRC2_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC3_DATA_R32</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_R32__CRC3_R_CR32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_R32__CRC3_R_CR32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC3_DATA_G32</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_G32__CRC3_G_Y32__SHIFT                                                       0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_G32__CRC3_G_Y32_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC3_DATA_B32</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_B32__CRC3_B_CB32__SHIFT                                                      0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_B32__CRC3_B_CB32_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//OTG_CRC323_OTG_CRC3_DATA_C32</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_C32__CRC3_C32__SHIFT                                                         0x0</div><div class='add'>+#define OTG_CRC323_OTG_CRC3_DATA_C32__CRC3_C32_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_optc_misc_dispdec</div><div class='add'>+//GSL_SOURCE_SELECT</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L</div><div class='add'>+//OPTC_DLPC_CONTROL</div><div class='add'>+#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX__SHIFT                                                      0x0</div><div class='add'>+#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX_MASK                                                        0x00000007L</div><div class='add'>+//OPTC_CLOCK_CONTROL</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT                                                          0xf</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK                                                            0x00008000L</div><div class='add'>+//ODM_MEM_PWR_CTRL</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L</div><div class='add'>+//ODM_MEM_PWR_CTRL3</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL</div><div class='add'>+//ODM_MEM_PWR_STATUS</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L</div><div class='add'>+//OPTC_MISC_SPARE_REGISTER</div><div class='add'>+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0</div><div class='add'>+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON17_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON17_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON17_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON17_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON17_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON17_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON17_PERFMON_HI</div><div class='add'>+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON17_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd0_dispdec</div><div class='add'>+//HPD0_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD0_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD0_DC_HPD_CONTROL</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD0_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD0_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd1_dispdec</div><div class='add'>+//HPD1_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD1_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD1_DC_HPD_CONTROL</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD1_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD1_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd2_dispdec</div><div class='add'>+//HPD2_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD2_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD2_DC_HPD_CONTROL</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD2_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD2_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd3_dispdec</div><div class='add'>+//HPD3_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD3_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD3_DC_HPD_CONTROL</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD3_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD3_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_hpd4_dispdec</div><div class='add'>+//HPD4_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD4_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD4_DC_HPD_CONTROL</div><div class='add'>+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD4_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD4_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp0_dispdec</div><div class='add'>+//DP0_DP_LINK_CNTL</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP0_DP_PIXEL_FORMAT</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L</div><div class='add'>+//DP0_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP0_DP_CONFIG</div><div class='add'>+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP0_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP0_DP_STEER_FIFO</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L</div><div class='add'>+//DP0_DP_MSA_MISC</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP0_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP0_DP_VID_TIMING</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP0_DP_VID_N</div><div class='add'>+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP0_DP_VID_M</div><div class='add'>+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP0_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP0_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP0_DP_VID_MSA_VBID</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP0_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP0_DP_DPHY_CNTL</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP0_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP0_DP_DPHY_SYM0</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP0_DP_DPHY_SYM1</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP0_DP_DPHY_SYM2</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP0_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP0_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP0_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP0_DP_DPHY_CRC_CONTROL0</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT                                                          0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT                                                     0x4</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT                                                       0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK                                                       0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK                                                         0x00000100L</div><div class='add'>+//DP0_DP_DPHY_CRC_CONTROL1</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP0_DP_DPHY_CRC_RESULT0</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP0_DP_DPHY_CRC_RESULT1</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP0_DP_DPHY_CRC_STATUS</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT                                                  0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT                                              0x4</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                                0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                               0xc</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                           0x10</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK                                                    0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK                                                0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                                  0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                                 0x00001000L</div><div class='add'>+#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                             0x00010000L</div><div class='add'>+//DP0_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP0_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP0_DP_DPHY_CRC_RESULT2</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP0_DP_DPHY_CRC_RESULT3</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP0_DP_SEC_CNTL</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP0_DP_SEC_CNTL1</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING1</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING2</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING3</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING4</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP0_DP_SEC_AUD_N</div><div class='add'>+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_AUD_M</div><div class='add'>+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP0_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP0_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP0_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP0_DP_MSE_SAT0</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT1</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT2</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP0_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP0_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP0_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP0_DP_CP_ENCRYPTION_CONTROL</div><div class='add'>+//DP0_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP0_DP_DPIA_SPARE</div><div class='add'>+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_MSO_CNTL</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP0_DP_MSO_CNTL1</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP0_DP_DSC_CNTL</div><div class='add'>+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0</div><div class='add'>+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L</div><div class='add'>+//DP0_DP_SEC_CNTL2</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP0_DP_SEC_CNTL3</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_CNTL4</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_CNTL5</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_CNTL6</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP0_DP_SEC_CNTL7</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP0_DP_DB_CNTL</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP0_DP_MSA_VBID_MISC</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP0_DP_ALPM_CNTL</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP8_CNTL</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP9_CNTL</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP10_CNTL</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP11_CNTL</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP0_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP0_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP0_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP0_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP0_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_dispdec</div><div class='add'>+//DIG0_DIG_FE_CNTL</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG0_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG0_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG0_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG0_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG0_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG0_DIG_TEST_PATTERN</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG0_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG0_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG0_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG0_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_CONTROL</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG0_HDMI_STATUS</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG0_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG0_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG0_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG0_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG0_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG0_HDMI_GC</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG0_HDMI_DB_CONTROL</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG0_HDMI_ACR_32_0</div><div class='add'>+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_32_1</div><div class='add'>+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG0_HDMI_ACR_44_0</div><div class='add'>+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_44_1</div><div class='add'>+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG0_HDMI_ACR_48_0</div><div class='add'>+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_48_1</div><div class='add'>+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG0_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG0_AFMT_CNTL</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG0_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT                                                          0x6</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON__SHIFT                                            0xc</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK                                                            0x00000040L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON_MASK                                              0x00001000L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG0_DIG_BE_CNTL</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG0_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG0_TMDS_CNTL</div><div class='add'>+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG0_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG0_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG0_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG0_TMDS_CTL_BITS</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG0_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG0_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG0_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG0_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG0_DIG_VERSION</div><div class='add'>+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp1_dispdec</div><div class='add'>+//DP1_DP_LINK_CNTL</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP1_DP_PIXEL_FORMAT</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L</div><div class='add'>+//DP1_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP1_DP_CONFIG</div><div class='add'>+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP1_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP1_DP_STEER_FIFO</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L</div><div class='add'>+//DP1_DP_MSA_MISC</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP1_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP1_DP_VID_TIMING</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP1_DP_VID_N</div><div class='add'>+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP1_DP_VID_M</div><div class='add'>+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP1_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP1_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP1_DP_VID_MSA_VBID</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP1_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP1_DP_DPHY_CNTL</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP1_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP1_DP_DPHY_SYM0</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP1_DP_DPHY_SYM1</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP1_DP_DPHY_SYM2</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP1_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP1_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP1_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP1_DP_DPHY_CRC_CONTROL0</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT                                                          0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT                                                     0x4</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT                                                       0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK                                                       0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK                                                         0x00000100L</div><div class='add'>+//DP1_DP_DPHY_CRC_CONTROL1</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP1_DP_DPHY_CRC_RESULT0</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP1_DP_DPHY_CRC_RESULT1</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP1_DP_DPHY_CRC_STATUS</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT                                                  0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT                                              0x4</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                                0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                               0xc</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                           0x10</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK                                                    0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK                                                0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                                  0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                                 0x00001000L</div><div class='add'>+#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                             0x00010000L</div><div class='add'>+//DP1_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP1_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP1_DP_DPHY_CRC_RESULT2</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP1_DP_DPHY_CRC_RESULT3</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP1_DP_SEC_CNTL</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP1_DP_SEC_CNTL1</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING1</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING2</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING3</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING4</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP1_DP_SEC_AUD_N</div><div class='add'>+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_AUD_M</div><div class='add'>+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP1_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP1_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP1_DP_CP_MSE_STATUS</div><div class='add'>+//DP1_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP1_DP_MSE_SAT0</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT1</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT2</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP1_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP1_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP1_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP1_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP1_DP_DPIA_SPARE</div><div class='add'>+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_MSO_CNTL</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP1_DP_MSO_CNTL1</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP1_DP_DSC_CNTL</div><div class='add'>+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0</div><div class='add'>+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L</div><div class='add'>+//DP1_DP_SEC_CNTL2</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP1_DP_SEC_CNTL3</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_CNTL4</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_CNTL5</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_CNTL6</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP1_DP_SEC_CNTL7</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP1_DP_DB_CNTL</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP1_DP_MSA_VBID_MISC</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP1_DP_ALPM_CNTL</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP8_CNTL</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP9_CNTL</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP10_CNTL</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP11_CNTL</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP1_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP1_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP1_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP1_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP1_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_dispdec</div><div class='add'>+//DIG1_DIG_FE_CNTL</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG1_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG1_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG1_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG1_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG1_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG1_DIG_TEST_PATTERN</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG1_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG1_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG1_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG1_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_CONTROL</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG1_HDMI_STATUS</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG1_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG1_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG1_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG1_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG1_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG1_HDMI_GC</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG1_HDMI_DB_CONTROL</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG1_HDMI_ACR_32_0</div><div class='add'>+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_32_1</div><div class='add'>+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG1_HDMI_ACR_44_0</div><div class='add'>+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_44_1</div><div class='add'>+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG1_HDMI_ACR_48_0</div><div class='add'>+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_48_1</div><div class='add'>+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG1_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG1_AFMT_CNTL</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG1_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG1_DIG_BE_CNTL</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG1_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG1_TMDS_CNTL</div><div class='add'>+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG1_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG1_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG1_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG1_TMDS_CTL_BITS</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG1_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG1_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG1_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG1_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG1_DIG_DEBUG</div><div class='add'>+//DIG1_DIG_VERSION</div><div class='add'>+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp2_dispdec</div><div class='add'>+//DP2_DP_LINK_CNTL</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP2_DP_PIXEL_FORMAT</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L</div><div class='add'>+//DP2_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP2_DP_CONFIG</div><div class='add'>+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP2_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP2_DP_STEER_FIFO</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L</div><div class='add'>+//DP2_DP_MSA_MISC</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP2_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP2_DP_VID_TIMING</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP2_DP_VID_N</div><div class='add'>+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP2_DP_VID_M</div><div class='add'>+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP2_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP2_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP2_DP_VID_MSA_VBID</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP2_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP2_DP_DPHY_CNTL</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP2_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP2_DP_DPHY_SYM0</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP2_DP_DPHY_SYM1</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP2_DP_DPHY_SYM2</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP2_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP2_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP2_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP2_DP_DPHY_CRC_CONTROL0</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT                                                          0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT                                                     0x4</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT                                                       0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK                                                       0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK                                                         0x00000100L</div><div class='add'>+//DP2_DP_DPHY_CRC_CONTROL1</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP2_DP_DPHY_CRC_RESULT0</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP2_DP_DPHY_CRC_RESULT1</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP2_DP_DPHY_CRC_STATUS</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT                                                  0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT                                              0x4</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                                0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                               0xc</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                           0x10</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK                                                    0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK                                                0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                                  0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                                 0x00001000L</div><div class='add'>+#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                             0x00010000L</div><div class='add'>+//DP2_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP2_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP2_DP_DPHY_CRC_RESULT2</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP2_DP_DPHY_CRC_RESULT3</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP2_DP_SEC_CNTL</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP2_DP_SEC_CNTL1</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING1</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING2</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING3</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING4</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP2_DP_SEC_AUD_N</div><div class='add'>+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_AUD_M</div><div class='add'>+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP2_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP2_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP2_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP2_DP_MSE_SAT0</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT1</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT2</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP2_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP2_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP2_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP2_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP2_DP_DPIA_SPARE</div><div class='add'>+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_MSO_CNTL</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP2_DP_MSO_CNTL1</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP2_DP_DSC_CNTL</div><div class='add'>+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0</div><div class='add'>+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L</div><div class='add'>+//DP2_DP_SEC_CNTL2</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP2_DP_SEC_CNTL3</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_CNTL4</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_CNTL5</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_CNTL6</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP2_DP_SEC_CNTL7</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP2_DP_DB_CNTL</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP2_DP_MSA_VBID_MISC</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP2_DP_ALPM_CNTL</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP8_CNTL</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP9_CNTL</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP10_CNTL</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP11_CNTL</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP2_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP2_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP2_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP2_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP2_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_dispdec</div><div class='add'>+//DIG2_DIG_FE_CNTL</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG2_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG2_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG2_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG2_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG2_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG2_DIG_TEST_PATTERN</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG2_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG2_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG2_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG2_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_CONTROL</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG2_HDMI_STATUS</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG2_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG2_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG2_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG2_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG2_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG2_HDMI_GC</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG2_HDMI_DB_CONTROL</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG2_HDMI_ACR_32_0</div><div class='add'>+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_32_1</div><div class='add'>+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG2_HDMI_ACR_44_0</div><div class='add'>+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_44_1</div><div class='add'>+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG2_HDMI_ACR_48_0</div><div class='add'>+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_48_1</div><div class='add'>+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG2_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG2_AFMT_CNTL</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG2_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG2_DIG_BE_CNTL</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG2_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG2_TMDS_CNTL</div><div class='add'>+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG2_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG2_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG2_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG2_TMDS_CTL_BITS</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG2_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG2_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG2_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG2_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG2_DIG_VERSION</div><div class='add'>+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp3_dispdec</div><div class='add'>+//DP3_DP_LINK_CNTL</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP3_DP_PIXEL_FORMAT</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L</div><div class='add'>+//DP3_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP3_DP_CONFIG</div><div class='add'>+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP3_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP3_DP_STEER_FIFO</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L</div><div class='add'>+//DP3_DP_MSA_MISC</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP3_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP3_DP_VID_TIMING</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP3_DP_VID_N</div><div class='add'>+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP3_DP_VID_M</div><div class='add'>+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP3_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP3_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP3_DP_VID_MSA_VBID</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP3_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP3_DP_DPHY_CNTL</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP3_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP3_DP_DPHY_SYM0</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP3_DP_DPHY_SYM1</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP3_DP_DPHY_SYM2</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP3_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP3_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP3_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP3_DP_DPHY_CRC_CONTROL0</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT                                                          0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT                                                     0x4</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT                                                       0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK                                                       0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK                                                         0x00000100L</div><div class='add'>+//DP3_DP_DPHY_CRC_CONTROL1</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP3_DP_DPHY_CRC_RESULT0</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP3_DP_DPHY_CRC_RESULT1</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP3_DP_DPHY_CRC_STATUS</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT                                                  0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT                                              0x4</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                                0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                               0xc</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                           0x10</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK                                                    0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK                                                0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                                  0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                                 0x00001000L</div><div class='add'>+#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                             0x00010000L</div><div class='add'>+//DP3_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP3_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP3_DP_DPHY_CRC_RESULT2</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP3_DP_DPHY_CRC_RESULT3</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP3_DP_SEC_CNTL</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP3_DP_SEC_CNTL1</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING1</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING2</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING3</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING4</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP3_DP_SEC_AUD_N</div><div class='add'>+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_AUD_M</div><div class='add'>+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP3_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP3_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP3_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP3_DP_MSE_SAT0</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT1</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT2</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP3_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP3_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP3_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP3_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP3_DP_DPIA_SPARE</div><div class='add'>+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_MSO_CNTL</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP3_DP_MSO_CNTL1</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP3_DP_DSC_CNTL</div><div class='add'>+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0</div><div class='add'>+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L</div><div class='add'>+//DP3_DP_SEC_CNTL2</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP3_DP_SEC_CNTL3</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_CNTL4</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_CNTL5</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_CNTL6</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP3_DP_SEC_CNTL7</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP3_DP_DB_CNTL</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP3_DP_MSA_VBID_MISC</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP3_DP_ALPM_CNTL</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP8_CNTL</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP9_CNTL</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP10_CNTL</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP11_CNTL</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP3_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP3_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP3_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP3_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP3_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_dispdec</div><div class='add'>+//DIG3_DIG_FE_CNTL</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG3_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG3_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG3_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG3_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG3_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG3_DIG_TEST_PATTERN</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG3_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG3_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG3_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG3_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_CONTROL</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG3_HDMI_STATUS</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG3_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG3_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG3_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG3_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG3_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG3_HDMI_GC</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG3_HDMI_DB_CONTROL</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG3_HDMI_ACR_32_0</div><div class='add'>+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_32_1</div><div class='add'>+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG3_HDMI_ACR_44_0</div><div class='add'>+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_44_1</div><div class='add'>+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG3_HDMI_ACR_48_0</div><div class='add'>+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_48_1</div><div class='add'>+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG3_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG3_AFMT_CNTL</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG3_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG3_DIG_BE_CNTL</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG3_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG3_TMDS_CNTL</div><div class='add'>+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG3_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG3_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG3_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG3_TMDS_CTL_BITS</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG3_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG3_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG3_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG3_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG3_DIG_VERSION</div><div class='add'>+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp4_dispdec</div><div class='add'>+//DP4_DP_LINK_CNTL</div><div class='add'>+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP4_DP_PIXEL_FORMAT</div><div class='add'>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18</div><div class='add'>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE__SHIFT                                        0x1e</div><div class='add'>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L</div><div class='add'>+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L</div><div class='add'>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_PER_CYCLE_PROCESSING_MODE_MASK                                          0x40000000L</div><div class='add'>+//DP4_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP4_DP_CONFIG</div><div class='add'>+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP4_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP4_DP_STEER_FIFO</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_TU_SIZE__SHIFT                                                                  0x18</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L</div><div class='add'>+#define DP4_DP_STEER_FIFO__DP_TU_SIZE_MASK                                                                    0x3F000000L</div><div class='add'>+//DP4_DP_MSA_MISC</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP4_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP4_DP_VID_TIMING</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP4_DP_VID_N</div><div class='add'>+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP4_DP_VID_M</div><div class='add'>+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP4_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP4_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP4_DP_VID_MSA_VBID</div><div class='add'>+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP4_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP4_DP_DPHY_CNTL</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP4_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP4_DP_DPHY_SYM0</div><div class='add'>+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP4_DP_DPHY_SYM1</div><div class='add'>+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP4_DP_DPHY_SYM2</div><div class='add'>+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP4_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP4_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP4_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP4_DP_DPHY_CRC_CONTROL0</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT                                                          0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT                                                     0x4</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT                                                       0x8</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK                                                       0x00000010L</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK                                                         0x00000100L</div><div class='add'>+//DP4_DP_DPHY_CRC_CONTROL1</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP4_DP_DPHY_CRC_RESULT0</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP4_DP_DPHY_CRC_RESULT1</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP4_DP_DPHY_CRC_STATUS</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT                                                  0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT                                              0x4</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                                0x8</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                               0xc</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                           0x10</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK                                                    0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK                                                0x00000010L</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                                  0x00000100L</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                                 0x00001000L</div><div class='add'>+#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                             0x00010000L</div><div class='add'>+//DP4_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP4_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP4_DP_DPHY_CRC_RESULT2</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP4_DP_DPHY_CRC_RESULT3</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DP4_DP_SEC_CNTL</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP4_DP_SEC_CNTL1</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_FRAMING1</div><div class='add'>+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_FRAMING2</div><div class='add'>+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_FRAMING3</div><div class='add'>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_FRAMING4</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP4_DP_SEC_AUD_N</div><div class='add'>+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP4_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP4_DP_SEC_AUD_M</div><div class='add'>+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP4_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP4_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP4_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP4_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP4_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP4_DP_MSE_SAT0</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT                                                   0x5</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT                                                   0x15</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK                                                     0x00000020L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK                                                     0x00200000L</div><div class='add'>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP4_DP_MSE_SAT1</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT                                                   0x5</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT                                                   0x15</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK                                                     0x00000020L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK                                                     0x00200000L</div><div class='add'>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP4_DP_MSE_SAT2</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT                                                   0x5</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT                                                   0x15</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK                                                     0x00000020L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK                                                     0x00200000L</div><div class='add'>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP4_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP4_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP4_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP4_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP4_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP4_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP4_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT                                     0x5</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT                                     0x15</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK                                       0x00000020L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK                                       0x00200000L</div><div class='add'>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP4_DP_DPIA_SPARE</div><div class='add'>+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP4_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP4_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP4_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP4_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP4_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP4_DP_MSO_CNTL</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP4_DP_MSO_CNTL1</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP4_DP_DSC_CNTL</div><div class='add'>+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0</div><div class='add'>+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000001L</div><div class='add'>+//DP4_DP_SEC_CNTL2</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP4_DP_SEC_CNTL3</div><div class='add'>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_CNTL4</div><div class='add'>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_CNTL5</div><div class='add'>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_CNTL6</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP4_DP_SEC_CNTL7</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP4_DP_DB_CNTL</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP4_DP_MSA_VBID_MISC</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP4_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP4_DP_ALPM_CNTL</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP4_DP_GSP8_CNTL</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP4_DP_GSP9_CNTL</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP4_DP_GSP10_CNTL</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP4_DP_GSP11_CNTL</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP4_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP4_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP4_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP4_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP4_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP4_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP4_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP4_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP4_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP4_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP4_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_dispdec</div><div class='add'>+//DIG4_DIG_FE_CNTL</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING__SHIFT                                                0xf</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_SPLIT_LINK_PIXEL_GROUPING_MASK                                                  0x00008000L</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L</div><div class='add'>+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG4_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG4_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG4_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG4_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG4_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG4_DIG_TEST_PATTERN</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG4_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG4_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE__SHIFT                                                0x8</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_MODE_MASK                                                  0x00000100L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG4_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG4_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_CONTROL</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG4_HDMI_STATUS</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG4_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG4_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG4_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG4_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG4_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG4_HDMI_GC</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG4_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG4_HDMI_DB_CONTROL</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG4_HDMI_ACR_32_0</div><div class='add'>+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG4_HDMI_ACR_32_1</div><div class='add'>+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG4_HDMI_ACR_44_0</div><div class='add'>+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG4_HDMI_ACR_44_1</div><div class='add'>+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG4_HDMI_ACR_48_0</div><div class='add'>+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG4_HDMI_ACR_48_1</div><div class='add'>+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG4_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG4_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG4_AFMT_CNTL</div><div class='add'>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG4_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG4_DIG_BE_CNTL</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG4_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG4_TMDS_CNTL</div><div class='add'>+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG4_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG4_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG4_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG4_TMDS_CTL_BITS</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG4_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG4_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG4_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG4_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG4_DIG_DEBUG</div><div class='add'>+//DIG4_DIG_VERSION</div><div class='add'>+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec</div><div class='add'>+//AFMT0_AFMT_ACP</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT0_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT0_AFMT_60958_0</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT0_AFMT_60958_1</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT0_AFMT_60958_2</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT0_AFMT_STATUS</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT0_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT0_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT0_AFMT_MEM_PWR</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec</div><div class='add'>+//AFMT1_AFMT_ACP</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT1_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT1_AFMT_60958_0</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT1_AFMT_60958_1</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT1_AFMT_60958_2</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT1_AFMT_STATUS</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT1_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT1_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT1_AFMT_MEM_PWR</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec</div><div class='add'>+//AFMT2_AFMT_ACP</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT2_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT2_AFMT_60958_0</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT2_AFMT_60958_1</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT2_AFMT_60958_2</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT2_AFMT_STATUS</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT2_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT2_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT2_AFMT_MEM_PWR</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec</div><div class='add'>+//AFMT3_AFMT_ACP</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT3_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT3_AFMT_60958_0</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT3_AFMT_60958_1</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT3_AFMT_60958_2</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT3_AFMT_STATUS</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT3_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT3_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT3_AFMT_MEM_PWR</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec</div><div class='add'>+//AFMT4_AFMT_ACP</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT4_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT4_AFMT_60958_0</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT4_AFMT_60958_1</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT4_AFMT_60958_2</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT4_AFMT_STATUS</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT4_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT4_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT4_AFMT_MEM_PWR</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec</div><div class='add'>+//DME0_DME_CONTROL</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME0_DME_MEMORY_CONTROL</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec</div><div class='add'>+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG0_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG0_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG0_VPG_MEM_PWR</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG0_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG0_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG0_VPG_MPEG_INFO0</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG0_VPG_MPEG_INFO1</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec</div><div class='add'>+//DME1_DME_CONTROL</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME1_DME_MEMORY_CONTROL</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec</div><div class='add'>+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG1_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG1_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG1_VPG_MEM_PWR</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG1_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG1_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG1_VPG_MPEG_INFO0</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG1_VPG_MPEG_INFO1</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec</div><div class='add'>+//DME2_DME_CONTROL</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME2_DME_MEMORY_CONTROL</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec</div><div class='add'>+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG2_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG2_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG2_VPG_MEM_PWR</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG2_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG2_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG2_VPG_MPEG_INFO0</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG2_VPG_MPEG_INFO1</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec</div><div class='add'>+//DME3_DME_CONTROL</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME3_DME_MEMORY_CONTROL</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec</div><div class='add'>+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG3_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG3_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG3_VPG_MEM_PWR</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG3_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG3_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG3_VPG_MPEG_INFO0</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG3_VPG_MPEG_INFO1</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec</div><div class='add'>+//DME4_DME_CONTROL</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME4_DME_MEMORY_CONTROL</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec</div><div class='add'>+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG4_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG4_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG4_VPG_MEM_PWR</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG4_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG4_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG4_VPG_MPEG_INFO0</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG4_VPG_MPEG_INFO1</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux0_dispdec</div><div class='add'>+//DP_AUX0_AUX_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX0_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX0_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX0_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L</div><div class='add'>+//DP_AUX0_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L</div><div class='add'>+//DP_AUX0_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX0_AUX_SW_DATA</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX0_AUX_LS_DATA</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX0_AUX_GTC_SYNC_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L</div><div class='add'>+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX0_AUX_GTC_SYNC_STATUS</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L</div><div class='add'>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L</div><div class='add'>+//DP_AUX0_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux1_dispdec</div><div class='add'>+//DP_AUX1_AUX_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX1_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX1_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX1_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L</div><div class='add'>+//DP_AUX1_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L</div><div class='add'>+//DP_AUX1_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX1_AUX_SW_DATA</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX1_AUX_LS_DATA</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX1_AUX_GTC_SYNC_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L</div><div class='add'>+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX1_AUX_GTC_SYNC_STATUS</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L</div><div class='add'>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L</div><div class='add'>+//DP_AUX1_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux2_dispdec</div><div class='add'>+//DP_AUX2_AUX_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX2_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX2_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX2_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L</div><div class='add'>+//DP_AUX2_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L</div><div class='add'>+//DP_AUX2_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX2_AUX_SW_DATA</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX2_AUX_LS_DATA</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX2_AUX_GTC_SYNC_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L</div><div class='add'>+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX2_AUX_GTC_SYNC_STATUS</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L</div><div class='add'>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L</div><div class='add'>+//DP_AUX2_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux3_dispdec</div><div class='add'>+//DP_AUX3_AUX_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX3_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX3_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX3_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L</div><div class='add'>+//DP_AUX3_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L</div><div class='add'>+//DP_AUX3_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX3_AUX_SW_DATA</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX3_AUX_LS_DATA</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX3_AUX_GTC_SYNC_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L</div><div class='add'>+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX3_AUX_GTC_SYNC_STATUS</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L</div><div class='add'>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L</div><div class='add'>+//DP_AUX3_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dp_aux4_dispdec</div><div class='add'>+//DP_AUX4_AUX_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX4_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX4_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX4_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L</div><div class='add'>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L</div><div class='add'>+//DP_AUX4_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L</div><div class='add'>+//DP_AUX4_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX4_AUX_SW_DATA</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX4_AUX_LS_DATA</div><div class='add'>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX4_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX4_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX4_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX4_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX4_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX4_AUX_GTC_SYNC_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L</div><div class='add'>+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L</div><div class='add'>+//DP_AUX4_AUX_GTC_SYNC_STATUS</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L</div><div class='add'>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L</div><div class='add'>+//DP_AUX4_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux0_dispdec</div><div class='add'>+//DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL</div><div class='add'>+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4</div><div class='add'>+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8</div><div class='add'>+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L</div><div class='add'>+#define DIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux1_dispdec</div><div class='add'>+//DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL</div><div class='add'>+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4</div><div class='add'>+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8</div><div class='add'>+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L</div><div class='add'>+#define DIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux2_dispdec</div><div class='add'>+//DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL</div><div class='add'>+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4</div><div class='add'>+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8</div><div class='add'>+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L</div><div class='add'>+#define DIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dpia_mux3_dispdec</div><div class='add'>+//DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL</div><div class='add'>+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__RESET__SHIFT                                                      0x4</div><div class='add'>+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT                                       0x8</div><div class='add'>+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__RESET_MASK                                                        0x00000010L</div><div class='add'>+#define DIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK                                         0x00000F00L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dout_i2c_dispdec</div><div class='add'>+//DC_I2C_CONTROL</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L</div><div class='add'>+//DC_I2C_ARBITRATION</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L</div><div class='add'>+//DC_I2C_INTERRUPT_CONTROL</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L</div><div class='add'>+//DC_I2C_SW_STATUS</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L</div><div class='add'>+//DC_I2C_DDC1_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC2_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC3_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC4_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC5_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC1_SPEED</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC1_SETUP</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC2_SPEED</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC2_SETUP</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC3_SPEED</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC3_SETUP</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC4_SPEED</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC4_SETUP</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC5_SPEED</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC5_SETUP</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_TRANSACTION0</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_TRANSACTION1</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_TRANSACTION2</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_TRANSACTION3</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_DATA</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L</div><div class='add'>+//DC_I2C_EDID_DETECT_CTRL</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L</div><div class='add'>+//DC_I2C_READ_REQUEST_INTERRUPT</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_misc_dispdec</div><div class='add'>+//DIO_DCN_STATUS</div><div class='add'>+#define DIO_DCN_STATUS__DCN_ACTIVE__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_DCN_STATUS__DCN_ACTIVE_MASK                                                                       0x00000001L</div><div class='add'>+//DIO_SCRATCH0</div><div class='add'>+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH1</div><div class='add'>+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH2</div><div class='add'>+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH3</div><div class='add'>+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH4</div><div class='add'>+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH5</div><div class='add'>+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH6</div><div class='add'>+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH7</div><div class='add'>+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x0</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x1</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x2</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x3</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x4</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x5</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x6</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000001L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000002L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000004L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000008L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000010L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000020L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000040L</div><div class='add'>+//DIO_MEM_PWR_STATUS</div><div class='add'>+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9</div><div class='add'>+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L</div><div class='add'>+//DIO_MEM_PWR_CTRL</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L</div><div class='add'>+//DIO_MEM_PWR_CTRL2</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L</div><div class='add'>+//DIO_CLK_CNTL</div><div class='add'>+#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL__SHIFT                                                                 0x0</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS__SHIFT                                                               0x9</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS__SHIFT                                                               0xa</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS__SHIFT                                                                0xb</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS__SHIFT                                                                0xc</div><div class='add'>+#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS__SHIFT                                                                0xd</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS__SHIFT                                                             0xe</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS__SHIFT                                                             0xf</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS__SHIFT                                                                0x10</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS__SHIFT                                                                0x11</div><div class='add'>+#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS__SHIFT                                                                 0x14</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS__SHIFT                                                          0x15</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS__SHIFT                                                          0x16</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS__SHIFT                                                          0x17</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS__SHIFT                                                          0x18</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS__SHIFT                                                          0x19</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS__SHIFT                                                          0x1a</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS__SHIFT                                                          0x1b</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS__SHIFT                                                          0x1c</div><div class='add'>+#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL_MASK                                                                   0x0000007FL</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS_MASK                                                                 0x00000200L</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS_MASK                                                                 0x00000400L</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS_MASK                                                                  0x00000800L</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS_MASK                                                                  0x00001000L</div><div class='add'>+#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS_MASK                                                                  0x00002000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS_MASK                                                               0x00004000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS_MASK                                                               0x00008000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS_MASK                                                                  0x00010000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS_MASK                                                                  0x00020000L</div><div class='add'>+#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS_MASK                                                                   0x00100000L</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS_MASK                                                            0x00200000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS_MASK                                                            0x00400000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS_MASK                                                            0x00800000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS_MASK                                                            0x01000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS_MASK                                                            0x02000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS_MASK                                                            0x04000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS_MASK                                                            0x08000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS_MASK                                                            0x10000000L</div><div class='add'>+//DIO_POWER_MANAGEMENT_CNTL</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L</div><div class='add'>+//DIO_HDMI_RXSTATUS_TIMER_CONTROL</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L</div><div class='add'>+//DIO_PSP_INTERRUPT_STATUS</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT                                             0x0</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT                                            0x1</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK                                               0x00000001L</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK                                              0xFFFFFFFEL</div><div class='add'>+//DIO_PSP_INTERRUPT_CLEAR</div><div class='add'>+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT                                               0x0</div><div class='add'>+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK                                                 0x00000001L</div><div class='add'>+//DIO_STATUS</div><div class='add'>+#define DIO_STATUS__DIO_EN__SHIFT                                                                             0x0</div><div class='add'>+#define DIO_STATUS__DIO_EN_MASK                                                                               0x00000001L</div><div class='add'>+//DIO_LINKA_CNTL</div><div class='add'>+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0</div><div class='add'>+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4</div><div class='add'>+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8</div><div class='add'>+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L</div><div class='add'>+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L</div><div class='add'>+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L</div><div class='add'>+//DIO_LINKB_CNTL</div><div class='add'>+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0</div><div class='add'>+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4</div><div class='add'>+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8</div><div class='add'>+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L</div><div class='add'>+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L</div><div class='add'>+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L</div><div class='add'>+//DIO_LINKC_CNTL</div><div class='add'>+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0</div><div class='add'>+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4</div><div class='add'>+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8</div><div class='add'>+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L</div><div class='add'>+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L</div><div class='add'>+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L</div><div class='add'>+//DIO_LINKD_CNTL</div><div class='add'>+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0</div><div class='add'>+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4</div><div class='add'>+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8</div><div class='add'>+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L</div><div class='add'>+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L</div><div class='add'>+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L</div><div class='add'>+//DIO_LINKE_CNTL</div><div class='add'>+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0</div><div class='add'>+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4</div><div class='add'>+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8</div><div class='add'>+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L</div><div class='add'>+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L</div><div class='add'>+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L</div><div class='add'>+//DIO_LINKF_CNTL</div><div class='add'>+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0</div><div class='add'>+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4</div><div class='add'>+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8</div><div class='add'>+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L</div><div class='add'>+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L</div><div class='add'>+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec</div><div class='add'>+//DIG0_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG1_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG2_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG3_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG4_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON18_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON18_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON18_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON18_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON18_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON18_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON18_PERFMON_HI</div><div class='add'>+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON18_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_dispdec</div><div class='add'>+//DC_GENERICA</div><div class='add'>+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7</div><div class='add'>+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L</div><div class='add'>+//DC_GENERICB</div><div class='add'>+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8</div><div class='add'>+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L</div><div class='add'>+//DCIO_CLOCK_CNTL</div><div class='add'>+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0</div><div class='add'>+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5</div><div class='add'>+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL</div><div class='add'>+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L</div><div class='add'>+//DC_REF_CLK_CNTL</div><div class='add'>+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8</div><div class='add'>+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L</div><div class='add'>+//UNIPHYA_LINK_CNTL</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYA_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYB_LINK_CNTL</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYB_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYC_LINK_CNTL</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYC_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYD_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYE_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//DCIO_WRCMD_DELAY</div><div class='add'>+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18</div><div class='add'>+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L</div><div class='add'>+//DC_PINSTRAPS</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L</div><div class='add'>+//DCIO_SPARE</div><div class='add'>+#define DCIO_SPARE__DCIO_SPARE__SHIFT                                                                         0x0</div><div class='add'>+#define DCIO_SPARE__DCIO_SPARE_MASK                                                                           0xFFFFFFFFL</div><div class='add'>+//INTERCEPT_STATE</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1</div><div class='add'>+#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT                                                         0x2</div><div class='add'>+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4</div><div class='add'>+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5</div><div class='add'>+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6</div><div class='add'>+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7</div><div class='add'>+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8</div><div class='add'>+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9</div><div class='add'>+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L</div><div class='add'>+#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK                                                           0x00000004L</div><div class='add'>+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L</div><div class='add'>+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L</div><div class='add'>+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L</div><div class='add'>+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L</div><div class='add'>+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L</div><div class='add'>+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L</div><div class='add'>+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L</div><div class='add'>+//DCIO_PATTERN_GEN_PAT</div><div class='add'>+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT                                                     0x0</div><div class='add'>+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DCIO_PATTERN_GEN_EN</div><div class='add'>+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT                                                       0x0</div><div class='add'>+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK                                                         0x00000001L</div><div class='add'>+//DCIO_BL_PWM_FRAME_START_DISP_SEL</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L</div><div class='add'>+//DCIO_GSL_GENLK_PAD_CNTL</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L</div><div class='add'>+//DCIO_GSL_SWAPLOCK_PAD_CNTL</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L</div><div class='add'>+//DCIO_SOFT_RESET</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x8</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x9</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0xa</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0xb</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0xc</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xd</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xe</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11</div><div class='add'>+#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT                                                               0x14</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000100L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000200L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000400L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000800L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00001000L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00002000L</div><div class='add'>+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00004000L</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L</div><div class='add'>+#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK                                                                 0x00100000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_chip_dispdec</div><div class='add'>+//DC_GPIO_GENERIC_MASK</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L</div><div class='add'>+//DC_GPIO_GENERIC_A</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L</div><div class='add'>+//DC_GPIO_GENERIC_EN</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L</div><div class='add'>+//DC_GPIO_GENERIC_Y</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L</div><div class='add'>+//DC_GPIO_DDC1_MASK</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L</div><div class='add'>+//DC_GPIO_DDC1_A</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC1_EN</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC1_Y</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC2_MASK</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L</div><div class='add'>+//DC_GPIO_DDC2_A</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC2_EN</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC2_Y</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC3_MASK</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L</div><div class='add'>+//DC_GPIO_DDC3_A</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC3_EN</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC3_Y</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC4_MASK</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L</div><div class='add'>+//DC_GPIO_DDC4_A</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC4_EN</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC4_Y</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC5_MASK</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L</div><div class='add'>+//DC_GPIO_DDC5_A</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC5_EN</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC5_Y</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDCVGA_MASK</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT                                              0x4</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK                                                0x00000010L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L</div><div class='add'>+//DC_GPIO_DDCVGA_A</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L</div><div class='add'>+//DC_GPIO_DDCVGA_EN</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L</div><div class='add'>+//DC_GPIO_DDCVGA_Y</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L</div><div class='add'>+//DC_GPIO_GENLK_MASK</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L</div><div class='add'>+//DC_GPIO_GENLK_A</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L</div><div class='add'>+//DC_GPIO_GENLK_EN</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L</div><div class='add'>+//DC_GPIO_GENLK_Y</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L</div><div class='add'>+//DC_GPIO_HPD_MASK</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L</div><div class='add'>+//DC_GPIO_HPD_A</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L</div><div class='add'>+//DC_GPIO_HPD_EN</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L</div><div class='add'>+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L</div><div class='add'>+//DC_GPIO_HPD_Y</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L</div><div class='add'>+//DC_GPIO_DRIVE_STRENGTH_S0</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT                                                 0x0</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT                                                 0x1</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT                                                 0x2</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT                                                 0x3</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT                                                 0x4</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT                                                 0x5</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT                                                 0x6</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT                                                0x8</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT                                              0x9</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT                                               0xa</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT                                               0xb</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK                                                   0x00000001L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK                                                   0x00000002L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK                                                   0x00000004L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK                                                   0x00000008L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK                                                   0x00000010L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK                                                   0x00000020L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK                                                   0x00000040L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK                                                  0x00000100L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK                                                0x00000200L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK                                                 0x00000400L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK                                                 0x00000800L</div><div class='add'>+//DC_GPIO_DRIVE_STRENGTH_S1</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT                                                 0x0</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT                                                 0x1</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT                                                 0x2</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT                                                 0x3</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT                                                 0x4</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT                                                 0x5</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT                                                 0x6</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT                                                0x8</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT                                              0x9</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT                                               0xa</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT                                               0xb</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK                                                   0x00000001L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK                                                   0x00000002L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK                                                   0x00000004L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK                                                   0x00000008L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK                                                   0x00000010L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK                                                   0x00000020L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK                                                   0x00000040L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK                                                  0x00000100L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK                                                0x00000200L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK                                                 0x00000400L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK                                                 0x00000800L</div><div class='add'>+//DC_GPIO_PWRSEQ0_EN</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L</div><div class='add'>+//DC_GPIO_PAD_STRENGTH_1</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L</div><div class='add'>+//DC_GPIO_PAD_STRENGTH_2</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L</div><div class='add'>+//PHY_AUX_CNTL</div><div class='add'>+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9</div><div class='add'>+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa</div><div class='add'>+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc</div><div class='add'>+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe</div><div class='add'>+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10</div><div class='add'>+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12</div><div class='add'>+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14</div><div class='add'>+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L</div><div class='add'>+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L</div><div class='add'>+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L</div><div class='add'>+//DC_GPIO_DRIVE_TXIMPSEL</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT                                              0x0</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT                                              0x1</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT                                              0x2</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT                                              0x3</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT                                              0x4</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT                                              0x5</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT                                              0x6</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT                                             0x8</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT                                           0x9</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT                                            0xa</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT                                            0xb</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT                                                  0xc</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT                                                  0xd</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT                                                  0xe</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT                                                  0xf</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT                                                  0x10</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT                                                  0x11</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK                                                0x00000002L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK                                                0x00000004L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK                                                0x00000008L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK                                                0x00000010L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK                                                0x00000020L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK                                                0x00000040L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK                                               0x00000100L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK                                             0x00000200L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK                                              0x00000400L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK                                              0x00000800L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK                                                    0x00001000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK                                                    0x00002000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK                                                    0x00004000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK                                                    0x00008000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK                                                    0x00010000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK                                                    0x00020000L</div><div class='add'>+//DC_GPIO_PWRSEQ1_EN</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L</div><div class='add'>+//DC_GPIO_TX12_EN</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L</div><div class='add'>+//DC_GPIO_AUX_CTRL_0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00C00000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0xC0000000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_1</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00001800L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00030000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x000C0000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0xC0000000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L</div><div class='add'>+//DC_GPIO_RXEN</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L</div><div class='add'>+//DC_GPIO_PULLUPEN</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_3</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_5</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L</div><div class='add'>+//AUXI2C_PAD_ALL_PWR_OK</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec</div><div class='add'>+//PWRSEQ0_DC_GPIO_PWRSEQ_EN</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L</div><div class='add'>+//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                          0x0</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                            0x1</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                             0x2</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                0x10</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                0x14</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                  0x15</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                   0x16</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                            0x00000001L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                              0x00000002L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                               0x00000004L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                  0x00010000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                  0x00100000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                    0x00200000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                     0x00400000L</div><div class='add'>+//PWRSEQ0_DC_GPIO_PWRSEQ_MASK</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L</div><div class='add'>+//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L</div><div class='add'>+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L</div><div class='add'>+//PWRSEQ0_PANEL_PWRSEQ_CNTL</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L</div><div class='add'>+//PWRSEQ0_PANEL_PWRSEQ_STATE</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L</div><div class='add'>+//PWRSEQ0_PANEL_PWRSEQ_DELAY1</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L</div><div class='add'>+//PWRSEQ0_PANEL_PWRSEQ_DELAY2</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L</div><div class='add'>+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L</div><div class='add'>+//PWRSEQ0_BL_PWM_CNTL</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L</div><div class='add'>+//PWRSEQ0_BL_PWM_CNTL2</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L</div><div class='add'>+//PWRSEQ0_BL_PWM_PERIOD_CNTL</div><div class='add'>+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0</div><div class='add'>+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10</div><div class='add'>+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL</div><div class='add'>+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L</div><div class='add'>+//PWRSEQ0_BL_PWM_GRP1_REG_LOCK</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L</div><div class='add'>+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L</div><div class='add'>+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L</div><div class='add'>+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L</div><div class='add'>+//PWRSEQ0_PWRSEQ_SPARE</div><div class='add'>+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0</div><div class='add'>+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec</div><div class='add'>+//PWRSEQ1_DC_GPIO_PWRSEQ_EN</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L</div><div class='add'>+//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                          0x0</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                            0x1</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                             0x2</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                0x10</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                0x14</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                  0x15</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                   0x16</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                            0x00000001L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                              0x00000002L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                               0x00000004L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                  0x00010000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                  0x00100000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                    0x00200000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                     0x00400000L</div><div class='add'>+//PWRSEQ1_DC_GPIO_PWRSEQ_MASK</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L</div><div class='add'>+//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L</div><div class='add'>+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L</div><div class='add'>+//PWRSEQ1_PANEL_PWRSEQ_CNTL</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L</div><div class='add'>+//PWRSEQ1_PANEL_PWRSEQ_STATE</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L</div><div class='add'>+//PWRSEQ1_PANEL_PWRSEQ_DELAY1</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L</div><div class='add'>+//PWRSEQ1_PANEL_PWRSEQ_DELAY2</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L</div><div class='add'>+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L</div><div class='add'>+//PWRSEQ1_BL_PWM_CNTL</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L</div><div class='add'>+//PWRSEQ1_BL_PWM_CNTL2</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L</div><div class='add'>+//PWRSEQ1_BL_PWM_PERIOD_CNTL</div><div class='add'>+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0</div><div class='add'>+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10</div><div class='add'>+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL</div><div class='add'>+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L</div><div class='add'>+//PWRSEQ1_BL_PWM_GRP1_REG_LOCK</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L</div><div class='add'>+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L</div><div class='add'>+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L</div><div class='add'>+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L</div><div class='add'>+//PWRSEQ1_PWRSEQ_SPARE</div><div class='add'>+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0</div><div class='add'>+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec</div><div class='add'>+//DSCC0_DSCC_CONFIG0</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_CONFIG1</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC0_DSCC_STATUS</div><div class='add'>+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC0_DSCC_MEM_POWER_CONTROL</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L</div><div class='add'>+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF0_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+//DSCCIF0_DSCCIF_CONFIG1</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP0_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+//DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON19_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON19_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON19_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON19_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON19_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON19_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON19_PERFMON_HI</div><div class='add'>+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON19_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec</div><div class='add'>+//DSCC1_DSCC_CONFIG0</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_CONFIG1</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC1_DSCC_STATUS</div><div class='add'>+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC1_DSCC_MEM_POWER_CONTROL</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L</div><div class='add'>+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF1_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+//DSCCIF1_DSCCIF_CONFIG1</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP1_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+//DSC_TOP1_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON20_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON20_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON20_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON20_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON20_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON20_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON20_PERFMON_HI</div><div class='add'>+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON20_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec</div><div class='add'>+//DSCC2_DSCC_CONFIG0</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_CONFIG1</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC2_DSCC_STATUS</div><div class='add'>+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC2_DSCC_MEM_POWER_CONTROL</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L</div><div class='add'>+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF2_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+//DSCCIF2_DSCCIF_CONFIG1</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP2_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+//DSC_TOP2_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON21_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON21_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON21_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON21_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON21_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON21_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON21_PERFMON_HI</div><div class='add'>+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON21_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec</div><div class='add'>+//DSCC3_DSCC_CONFIG0</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_CONFIG1</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC3_DSCC_STATUS</div><div class='add'>+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                    0xc</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT             0x1c</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                      0x00001000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK               0x10000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC3_DSCC_MEM_POWER_CONTROL</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L</div><div class='add'>+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF3_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+//DSCCIF3_DSCCIF_CONFIG1</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP3_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+//DSC_TOP3_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON22_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON22_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON22_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON22_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON22_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON22_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON22_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON22_PERFMON_HI</div><div class='add'>+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON22_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hpo_top_dispdec</div><div class='add'>+//HPO_TOP_CLOCK_CONTROL</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0xFF000000L</div><div class='add'>+//HPO_TOP_HW_CONTROL</div><div class='add'>+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0</div><div class='add'>+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL1</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL2</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL3</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+//DC_PERFMON23_PERFCOUNTER_CNTL</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L</div><div class='add'>+//DC_PERFMON23_PERFCOUNTER_CNTL2</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L</div><div class='add'>+//DC_PERFMON23_PERFCOUNTER_STATE</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L</div><div class='add'>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L</div><div class='add'>+//DC_PERFMON23_PERFMON_CNTL</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L</div><div class='add'>+//DC_PERFMON23_PERFMON_CNTL2</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL</div><div class='add'>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L</div><div class='add'>+//DC_PERFMON23_PERFMON_CVALUE_INT_MISC</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L</div><div class='add'>+//DC_PERFMON23_PERFMON_CVALUE_LOW</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0</div><div class='add'>+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DC_PERFMON23_PERFMON_HI</div><div class='add'>+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0</div><div class='add'>+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d</div><div class='add'>+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L</div><div class='add'>+//DC_PERFMON23_PERFMON_LOW</div><div class='add'>+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0</div><div class='add'>+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec</div><div class='add'>+//HDMI_LINK_ENC_CONTROL</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT                                                    0x0</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT                                                0x4</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK                                                      0x00000001L</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK                                                  0x00000010L</div><div class='add'>+//HDMI_LINK_ENC_CLK_CTRL</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT                                                 0x0</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT                                     0x1</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK                                                   0x00000001L</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK                                       0x00000002L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec</div><div class='add'>+//HDMI_FRL_ENC_CONFIG</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT                                                      0x0</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT                                               0x2</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT                                          0x10</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT                                          0x14</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT                                          0x18</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT                                          0x1c</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK                                                        0x00000001L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK                                                 0x00000004L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK                                            0x000F0000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK                                            0x00F00000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK                                            0x0F000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK                                            0xF0000000L</div><div class='add'>+//HDMI_FRL_ENC_CONFIG2</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT                                               0x0</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT                                               0xc</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT                                                  0x18</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT                                            0x19</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT                                            0x1a</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT                                         0x1c</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT                                           0x1d</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT                                   0x1e</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK                                                 0x000001FFL</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK                                                 0x001FF000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK                                                    0x01000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK                                              0x02000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK                                              0x0C000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK                                           0x10000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK                                             0x20000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK                                     0x40000000L</div><div class='add'>+//HDMI_FRL_ENC_METER_BUFFER_STATUS</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT                             0x0</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT                       0x1f</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK                               0x0000007FL</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK                         0x80000000L</div><div class='add'>+//HDMI_FRL_ENC_MEM_CTRL</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT                                                 0x0</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT                                               0x1</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT                                               0x4</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                             0x8</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK                                                   0x00000001L</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK                                                 0x00000006L</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK                                                 0x00000030L</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                               0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT                                        0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                                0x4</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                                 0x8</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT                          0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK                                          0x00000001L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                                  0x00000010L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                                   0x00000100L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK                            0x00001000L</div><div class='add'>+//HDMI_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT                        0x0</div><div class='add'>+#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK                          0x00000007L</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT                          0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT                           0x4</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT                  0x8</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT                0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT                        0x10</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT                      0x14</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT             0x18</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT                           0x1c</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK                            0x00000001L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                             0x00000010L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK                    0x00000300L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK                  0x00003000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK                          0x00030000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK                        0x00100000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK               0x01000000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                             0x30000000L</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT             0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT             0x1</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT             0x2</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT                 0x4</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT                   0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT                   0x10</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT               0x18</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT                      0x1f</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK               0x00000001L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK               0x00000002L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK               0x00000004L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK                   0x000003F0L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK                     0x0000F000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK                     0x001F0000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK                 0x3F000000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK                        0x80000000L</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT                0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT                  0x5</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT                      0x8</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT                      0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK                  0x0000001FL</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK                    0x00000020L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK                        0x00000100L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK                        0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec</div><div class='add'>+//AFMT5_AFMT_ACP</div><div class='add'>+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT5_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT5_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT5_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT5_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT5_AFMT_60958_0</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT5_AFMT_60958_1</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT5_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT5_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT5_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT5_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT5_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT5_AFMT_60958_2</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT5_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT5_AFMT_STATUS</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT5_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT5_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT5_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT5_AFMT_MEM_PWR</div><div class='add'>+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec</div><div class='add'>+//DME5_DME_CONTROL</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME5_DME_MEMORY_CONTROL</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG5_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG5_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG5_VPG_MEM_PWR</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG5_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG5_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG5_VPG_MPEG_INFO0</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG5_VPG_MPEG_INFO1</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec</div><div class='add'>+//HDMI_TB_ENC_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT                                                                0x4</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT                                                           0x8</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK                                                              0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK                                                                  0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK                                                             0x00000100L</div><div class='add'>+//HDMI_TB_ENC_PIXEL_FORMAT</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                0x8</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT                                                  0x10</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT                                                        0x18</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK                                                  0x00000300L</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK                                                    0x00030000L</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK                                                          0x03000000L</div><div class='add'>+//HDMI_TB_ENC_PACKET_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT                                          0x0</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT                                          0x8</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT                                        0xc</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT                                     0x10</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK                                            0x0000001FL</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK                                            0x00000300L</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK                                          0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK                                       0x00010000L</div><div class='add'>+//HDMI_TB_ENC_ACR_PACKET_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                  0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                  0x1</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                0x4</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                0x8</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                             0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                            0x10</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                        0x1f</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                    0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                    0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                  0x00000030L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                  0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                               0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                              0x00070000L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                          0x80000000L</div><div class='add'>+//HDMI_TB_ENC_VBI_PACKET_CONTROL1</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT                                                  0x0</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT                                                  0x1</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT                                                0x4</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT                                                0x5</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT                                      0x6</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT                                                 0x8</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT                                       0x9</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT                                          0xd</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                          0x10</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK                                                    0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK                                                    0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK                                                  0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK                                                  0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK                                        0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK                                                   0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK                                         0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK                                            0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK                                            0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                            0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_VBI_PACKET_CONTROL2</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT                                                0x0</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT                                                 0x10</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK                                                  0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK                                                   0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_GC_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT                                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT                                                    0x2</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT                                                     0x4</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK                                                           0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK                                                      0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK                                                       0x00000010L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                        0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                        0x1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT                                     0x2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                              0x3</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                        0x4</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                        0x5</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT                                     0x6</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                              0x7</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                        0x8</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                        0x9</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT                                     0xa</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                              0xb</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                        0xc</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                        0xd</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT                                     0xe</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                              0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                        0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                        0x11</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT                                     0x12</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                              0x13</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                        0x14</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                        0x15</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT                                     0x16</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                              0x17</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                        0x18</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                        0x19</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT                                     0x1a</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                              0x1b</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                        0x1c</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                        0x1d</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT                                     0x1e</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                              0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                          0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                          0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK                                       0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                0x00000008L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                          0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                          0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK                                       0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                0x00000080L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                          0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                          0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK                                       0x00000400L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                0x00000800L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                          0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                          0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK                                       0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                          0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                          0x00020000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK                                       0x00040000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                0x00080000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                          0x00100000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                          0x00200000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK                                       0x00400000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                0x00800000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                          0x01000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                          0x02000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK                                       0x04000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                0x08000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                          0x10000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                          0x20000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK                                       0x40000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT                                        0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT                                        0x1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT                                     0x2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                              0x3</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT                                        0x4</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT                                        0x5</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT                                     0x6</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                              0x7</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT                                       0x8</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT                                       0x9</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT                                    0xa</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                             0xb</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT                                       0xc</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT                                       0xd</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT                                    0xe</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                             0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT                                       0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT                                       0x11</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT                                    0x12</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                             0x13</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT                                       0x14</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT                                       0x15</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT                                    0x16</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                             0x17</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT                                       0x18</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT                                       0x19</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT                                    0x1a</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                             0x1b</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK                                          0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK                                          0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK                                       0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK                                0x00000008L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK                                          0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK                                          0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK                                       0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK                                0x00000080L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK                                         0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK                                         0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK                                      0x00000400L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK                               0x00000800L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK                                         0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK                                         0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK                                      0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK                               0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK                                         0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK                                         0x00020000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK                                      0x00040000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK                               0x00080000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK                                         0x00100000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK                                         0x00200000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK                                      0x00400000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK                               0x00800000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK                                         0x01000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK                                         0x02000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK                                      0x04000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK                               0x08000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                              0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                      0x1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                              0x2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                      0x3</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                              0x4</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                      0x5</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                              0x6</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                      0x7</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                              0x8</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                      0x9</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                              0xa</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                      0xb</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                              0xc</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                      0xd</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                              0xe</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                      0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                              0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                      0x11</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                              0x12</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                      0x13</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                             0x14</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                     0x15</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                             0x16</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                     0x17</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                             0x18</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                     0x19</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                             0x1a</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                     0x1b</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                             0x1c</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                     0x1d</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                        0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                        0x00000008L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                        0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                        0x00000080L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                        0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                0x00000400L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                        0x00000800L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                        0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                        0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                        0x00020000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                0x00040000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                        0x00080000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                               0x00100000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                       0x00200000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                               0x00400000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                       0x00800000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                               0x01000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                       0x02000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                               0x04000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                       0x08000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                               0x10000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                       0x20000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT                                      0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT                                       0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT                                      0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT                                       0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK                                        0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK                                         0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK                                        0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK                                         0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT                                      0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT                                       0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT                                      0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT                                       0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK                                        0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK                                         0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK                                        0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK                                         0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET14_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK                                            0x00008000L</div><div class='add'>+//HDMI_TB_ENC_DB_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                        0x0</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                        0xc</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                     0xf</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK                                                          0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                          0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                       0x00008000L</div><div class='add'>+//HDMI_TB_ENC_ACR_32_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                            0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_32_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK                                                              0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_ACR_44_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                            0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_44_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK                                                              0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_ACR_48_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                            0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_48_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK                                                              0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_ACR_STATUS_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                         0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                           0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_STATUS_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                           0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK                                                             0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_BUFFER_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT                              0x0</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT                               0x1</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT                              0x4</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT                           0x8</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT                            0x18</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK                                0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK                                 0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK                                0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK                             0x0000FF00L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK                              0x1F000000L</div><div class='add'>+//HDMI_TB_ENC_MEM_CTRL</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT                                                 0x0</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT                                               0x1</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT                                               0x4</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                             0x8</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK                                                   0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK                                                 0x00000006L</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK                                                 0x00000030L</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                               0x00000300L</div><div class='add'>+//HDMI_TB_ENC_METADATA_PACKET_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                               0x0</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                       0x4</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                               0x8</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                 0x10</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                         0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                 0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                   0xFFFF0000L</div><div class='add'>+//HDMI_TB_ENC_H_ACTIVE_BLANK</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT                                                       0x10</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK                                                        0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK                                                         0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_HC_ACTIVE_BLANK</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT                                                    0x0</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT                                                     0x10</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK                                                      0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK                                                       0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_CRC_CNTL</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT                                                            0x8</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT                                                         0xa</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT                                                    0x10</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT                                                  0x11</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK                                                              0x00000300L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK                                                           0x00000C00L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK                                                      0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK                                                    0x00060000L</div><div class='add'>+//HDMI_TB_ENC_CRC_RESULT_0</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT                                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT                                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK                                                           0x0000FFFFL</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK                                                           0xFFFF0000L</div><div class='add'>+//HDMI_TB_ENC_ENCRYPTION_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT                                          0x4</div><div class='add'>+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK                                            0x00000010L</div><div class='add'>+//HDMI_TB_ENC_MODE</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT                                                             0x0</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT                                                       0x8</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK                                                               0x00000003L</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK                                                         0x00000100L</div><div class='add'>+//HDMI_TB_ENC_INPUT_FIFO_STATUS</div><div class='add'>+#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT                                                0x0</div><div class='add'>+#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK                                                  0x00000001L</div><div class='add'>+//HDMI_TB_ENC_CRC_RESULT_1</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT                                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK                                                           0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec</div><div class='add'>+//APG0_APG_CONTROL</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG0_APG_CONTROL2</div><div class='add'>+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG0_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG0_APG_PACKET_CONTROL</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG0_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG0_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG0_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG0_APG_STATUS</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG0_APG_STATUS2</div><div class='add'>+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG0_APG_MEM_PWR</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG0_APG_SPARE</div><div class='add'>+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec</div><div class='add'>+//DME6_DME_CONTROL</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME6_DME_MEMORY_CONTROL</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG6_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG6_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG6_VPG_MEM_PWR</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG6_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG6_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG6_VPG_MPEG_INFO0</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG6_VPG_MPEG_INFO1</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT                                       0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK                                         0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec</div><div class='add'>+//APG1_APG_CONTROL</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG1_APG_CONTROL2</div><div class='add'>+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG1_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG1_APG_PACKET_CONTROL</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG1_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG1_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG1_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG1_APG_STATUS</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG1_APG_STATUS2</div><div class='add'>+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG1_APG_MEM_PWR</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG1_APG_SPARE</div><div class='add'>+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec</div><div class='add'>+//DME7_DME_CONTROL</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME7_DME_MEMORY_CONTROL</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec</div><div class='add'>+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG7_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG7_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG7_VPG_MEM_PWR</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG7_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG7_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG7_VPG_MPEG_INFO0</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG7_VPG_MPEG_INFO1</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT                                       0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK                                         0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec</div><div class='add'>+//APG2_APG_CONTROL</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG2_APG_CONTROL2</div><div class='add'>+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG2_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG2_APG_PACKET_CONTROL</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG2_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG2_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG2_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG2_APG_STATUS</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG2_APG_STATUS2</div><div class='add'>+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG2_APG_MEM_PWR</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG2_APG_SPARE</div><div class='add'>+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec</div><div class='add'>+//DME8_DME_CONTROL</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME8_DME_MEMORY_CONTROL</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec</div><div class='add'>+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG8_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG8_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG8_VPG_MEM_PWR</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG8_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG8_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG8_VPG_MPEG_INFO0</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG8_VPG_MPEG_INFO1</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT                                       0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK                                         0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec</div><div class='add'>+//APG3_APG_CONTROL</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG3_APG_CONTROL2</div><div class='add'>+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG3_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG3_APG_PACKET_CONTROL</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG3_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG3_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG3_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG3_APG_STATUS</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG3_APG_STATUS2</div><div class='add'>+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG3_APG_MEM_PWR</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG3_APG_SPARE</div><div class='add'>+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec</div><div class='add'>+//DME9_DME_CONTROL</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME9_DME_MEMORY_CONTROL</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec</div><div class='add'>+//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG9_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG9_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG9_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG9_VPG_MEM_PWR</div><div class='add'>+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG9_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG9_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG9_VPG_MPEG_INFO0</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG9_VPG_MPEG_INFO1</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT                                       0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK                                         0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec</div><div class='add'>+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L</div><div class='add'>+//DP_LINK_ENC0_DP_LINK_ENC_SPARE</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK                                          0x00000100L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec</div><div class='add'>+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L</div><div class='add'>+//DP_LINK_ENC1_DP_LINK_ENC_SPARE</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK                                          0x00000100L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT                                    0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT                                      0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK                                      0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK                                        0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT                             0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK                               0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dchvm_hvm_dispdec</div><div class='add'>+//DCHVM_CTRL0</div><div class='add'>+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0</div><div class='add'>+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L</div><div class='add'>+//DCHVM_CTRL1</div><div class='add'>+#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0</div><div class='add'>+#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL</div><div class='add'>+//DCHVM_CLK_CTRL</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5</div><div class='add'>+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8</div><div class='add'>+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS__SHIFT                                                               0xc</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L</div><div class='add'>+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L</div><div class='add'>+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L</div><div class='add'>+#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS_MASK                                                                 0x00001000L</div><div class='add'>+//DCHVM_MEM_CTRL</div><div class='add'>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0</div><div class='add'>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2</div><div class='add'>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4</div><div class='add'>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L</div><div class='add'>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL</div><div class='add'>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L</div><div class='add'>+//DCHVM_RIOMMU_CTRL0</div><div class='add'>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0</div><div class='add'>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1</div><div class='add'>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L</div><div class='add'>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L</div><div class='add'>+//DCHVM_RIOMMU_STAT0</div><div class='add'>+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0</div><div class='add'>+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1</div><div class='add'>+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L</div><div class='add'>+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dc_dlpc_dlpc_dispdec</div><div class='add'>+//DLPC_ENABLE</div><div class='add'>+#define DLPC_ENABLE__DLPC_EN__SHIFT                                                                           0x0</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_CLR__SHIFT                                                                 0x5</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_STATUS__SHIFT                                                              0x6</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_EN__SHIFT                                                             0x8</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_CLR__SHIFT                                                            0x9</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_STATUS__SHIFT                                                         0xa</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_EN__SHIFT                                                     0xc</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_CLR__SHIFT                                                    0xd</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_STATUS__SHIFT                                                 0xe</div><div class='add'>+#define DLPC_ENABLE__DLPC_EN_MASK                                                                             0x00000001L</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_CLR_MASK                                                                   0x00000020L</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_STATUS_MASK                                                                0x00000040L</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_EN_MASK                                                               0x00000100L</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_CLR_MASK                                                              0x00000200L</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_STATUS_MASK                                                           0x00000400L</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_CLR_MASK                                                      0x00002000L</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_STATUS_MASK                                                   0x00004000L</div><div class='add'>+//DLPC_CURRENT_COUNT</div><div class='add'>+#define DLPC_CURRENT_COUNT__VALUE__SHIFT                                                                      0x0</div><div class='add'>+#define DLPC_CURRENT_COUNT__VALUE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+//DLPC_OPTC_SNAPSHOT</div><div class='add'>+#define DLPC_OPTC_SNAPSHOT__VALUE__SHIFT                                                                      0x0</div><div class='add'>+#define DLPC_OPTC_SNAPSHOT__VALUE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+//DLPC_PWRUP</div><div class='add'>+#define DLPC_PWRUP__VALUE__SHIFT                                                                              0x0</div><div class='add'>+#define DLPC_PWRUP__VALUE_MASK                                                                                0xFFFFFFFFL</div><div class='add'>+//DLPC_OTG_RESYNC</div><div class='add'>+#define DLPC_OTG_RESYNC__VALUE__SHIFT                                                                         0x0</div><div class='add'>+#define DLPC_OTG_RESYNC__VALUE_MASK                                                                           0xFFFFFFFFL</div><div class='add'>+//DLPC_DCN_ZSC_LONO_PWRUP</div><div class='add'>+#define DLPC_DCN_ZSC_LONO_PWRUP__VALUE__SHIFT                                                                 0x0</div><div class='add'>+#define DLPC_DCN_ZSC_LONO_PWRUP__VALUE_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DLPC_SPARE</div><div class='add'>+#define DLPC_SPARE__SPARE__SHIFT                                                                              0x0</div><div class='add'>+#define DLPC_SPARE__SPARE_MASK                                                                                0xFFFFFFFFL</div><div class='add'>+//DLPC_COUNTER_INIT_VALUE</div><div class='add'>+#define DLPC_COUNTER_INIT_VALUE__DLPC_COUNTER_INIT_VALUE__SHIFT                                               0x0</div><div class='add'>+#define DLPC_COUNTER_INIT_VALUE__DLPC_COUNTER_INIT_VALUE_MASK                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dce_dpia_dpia_mu0_dpiadec</div><div class='add'>+//DPIA_MU_CLOCK_CTRL</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS__SHIFT                                                       0x0</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS__SHIFT                                                     0x2</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS__SHIFT                                                  0x8</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS__SHIFT                                                0xb</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS__SHIFT                                             0xc</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS__SHIFT                                            0xd</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS__SHIFT                                                  0xe</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL__SHIFT                                                       0x18</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS_MASK                                                         0x00000001L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS_MASK                                                       0x00000004L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS_MASK                                                    0x00000100L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS_MASK                                                  0x00000800L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS_MASK                                               0x00001000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS_MASK                                              0x00002000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS_MASK                                                    0x00004000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL_MASK                                                         0xFF000000L</div><div class='add'>+//DPIA_MU_CLOCK_CTRL_DPIA_PORT0</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC__SHIFT                                                         0x0</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN__SHIFT                                                       0x1</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN__SHIFT                                                      0x2</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON__SHIFT                                                 0xa</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC_MASK                                                           0x00000001L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN_MASK                                                        0x00000004L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L</div><div class='add'>+//DPIA_MU_RESET_CTRL_DPIA_PORT0</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST__SHIFT                                                     0x0</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST__SHIFT                                                   0x1</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST__SHIFT                                                  0x2</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST__SHIFT                                                   0x3</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE__SHIFT                                               0x8</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE__SHIFT                                                 0x9</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST_MASK                                                       0x00000001L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST_MASK                                                     0x00000002L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST_MASK                                                    0x00000004L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST_MASK                                                     0x00000008L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE_MASK                                                 0x00000100L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE_MASK                                                   0x00000200L</div><div class='add'>+//DPIA_MU_CLOCK_CTRL_DPIA_PORT1</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC__SHIFT                                                         0x0</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN__SHIFT                                                       0x1</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN__SHIFT                                                      0x2</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON__SHIFT                                                 0xa</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC_MASK                                                           0x00000001L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN_MASK                                                        0x00000004L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L</div><div class='add'>+//DPIA_MU_RESET_CTRL_DPIA_PORT1</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST__SHIFT                                                     0x0</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST__SHIFT                                                   0x1</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST__SHIFT                                                  0x2</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST__SHIFT                                                   0x3</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE__SHIFT                                               0x8</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE__SHIFT                                                 0x9</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST_MASK                                                       0x00000001L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST_MASK                                                     0x00000002L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST_MASK                                                    0x00000004L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST_MASK                                                     0x00000008L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE_MASK                                                 0x00000100L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE_MASK                                                   0x00000200L</div><div class='add'>+//DPIA_MU_CLOCK_CTRL_DPIA_PORT2</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC__SHIFT                                                         0x0</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN__SHIFT                                                       0x1</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN__SHIFT                                                      0x2</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON__SHIFT                                                 0xa</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC_MASK                                                           0x00000001L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN_MASK                                                        0x00000004L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L</div><div class='add'>+//DPIA_MU_RESET_CTRL_DPIA_PORT2</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST__SHIFT                                                     0x0</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST__SHIFT                                                   0x1</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST__SHIFT                                                  0x2</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST__SHIFT                                                   0x3</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE__SHIFT                                               0x8</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE__SHIFT                                                 0x9</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST_MASK                                                       0x00000001L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST_MASK                                                     0x00000002L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST_MASK                                                    0x00000004L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST_MASK                                                     0x00000008L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE_MASK                                                 0x00000100L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE_MASK                                                   0x00000200L</div><div class='add'>+//DPIA_MU_CLOCK_CTRL_DPIA_PORT3</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC__SHIFT                                                         0x0</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN__SHIFT                                                       0x1</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN__SHIFT                                                      0x2</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON__SHIFT                                               0x9</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON__SHIFT                                                 0xa</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON__SHIFT                                            0x11</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON__SHIFT                                           0x12</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC_MASK                                                           0x00000001L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN_MASK                                                        0x00000004L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON_MASK                                                 0x00000200L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON_MASK                                                   0x00000400L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON_MASK                                              0x00020000L</div><div class='add'>+#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON_MASK                                             0x00040000L</div><div class='add'>+//DPIA_MU_RESET_CTRL_DPIA_PORT3</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST__SHIFT                                                     0x0</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST__SHIFT                                                   0x1</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST__SHIFT                                                  0x2</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST__SHIFT                                                   0x3</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE__SHIFT                                               0x8</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE__SHIFT                                                 0x9</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST_MASK                                                       0x00000001L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST_MASK                                                     0x00000002L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST_MASK                                                    0x00000004L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST_MASK                                                     0x00000008L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE_MASK                                                 0x00000100L</div><div class='add'>+#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE_MASK                                                   0x00000200L</div><div class='add'>+//DPIA_MU_TPI_STATUS_DPIA_PORT0</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT__SHIFT                                              0x10</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L</div><div class='add'>+//DPIA_MU_TPI_STATUS_DPIA_PORT1</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT__SHIFT                                              0x10</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L</div><div class='add'>+//DPIA_MU_TPI_STATUS_DPIA_PORT2</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT__SHIFT                                              0x10</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L</div><div class='add'>+//DPIA_MU_TPI_STATUS_DPIA_PORT3</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT__SHIFT                                             0x8</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT__SHIFT                                              0x10</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT                                 0x18</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT                                    0x19</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT                                    0x1a</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT_MASK                                            0x0000007FL</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT_MASK                                               0x00000F00L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT_MASK                                                0x000F0000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK                                   0x01000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK                                      0x02000000L</div><div class='add'>+#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK                                      0x04000000L</div><div class='add'>+//DPIA_MU_TPI_MAX_CREDIT_COUNT</div><div class='add'>+#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT__SHIFT                                        0x0</div><div class='add'>+#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT_MASK                                          0x0000003FL</div><div class='add'>+//DPIA_MU_INTERRUPT_STATUS</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS__SHIFT                                                0x0</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS__SHIFT                                                0x3</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS__SHIFT                                                0x6</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS__SHIFT                                             0x1f</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS_MASK                                                  0x00000007L</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS_MASK                                                  0x00000038L</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS_MASK                                                  0x000001C0L</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS_MASK                                                  0x00000E00L</div><div class='add'>+#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS_MASK                                               0x80000000L</div><div class='add'>+//DPIA_MU_INTERRUPT_CTRL</div><div class='add'>+#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN__SHIFT                                                        0x0</div><div class='add'>+#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK__SHIFT                                                0x18</div><div class='add'>+#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN_MASK                                                          0x00000001L</div><div class='add'>+#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK_MASK                                                  0x01000000L</div><div class='add'>+//DPIA_MU_LOCAL_INTERRUPT_CTRL</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS__SHIFT                                        0x0</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR__SHIFT                                              0x2</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP__SHIFT                                                0x14</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS__SHIFT                                         0x18</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS_MASK                                          0x00000001L</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR_MASK                                                0x000FFFFCL</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP_MASK                                                  0x00100000L</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS_MASK                                           0x01000000L</div><div class='add'>+//DPIA_MU_LOCAL_INTERRUPT_ACK</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK__SHIFT                                            0x0</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK__SHIFT                                             0x1</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK_MASK                                              0x00000001L</div><div class='add'>+#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK_MASK                                               0x00000002L</div><div class='add'>+//DPIA_MU_RBBMIF_TIMEOUT_CTRL</div><div class='add'>+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY__SHIFT                                              0x0</div><div class='add'>+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD__SHIFT                                               0x14</div><div class='add'>+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY_MASK                                                0x000FFFFFL</div><div class='add'>+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD_MASK                                                 0xFFF00000L</div><div class='add'>+//DPIA_MU_RBBMIF_TIMEOUT_CTRL2</div><div class='add'>+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS__SHIFT                                               0x0</div><div class='add'>+#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS_MASK                                                 0x00000001L</div><div class='add'>+//DPIA_MU_RBBMIF_STATUS</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                              0x0</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                              0x1</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                              0x5</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK__SHIFT                                          0x18</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR__SHIFT                                      0x1f</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                0x00000001L</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                0x00000006L</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                0x007FFFE0L</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK_MASK                                            0x01000000L</div><div class='add'>+#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR_MASK                                        0x80000000L</div><div class='add'>+//DPIA_MU_MICROSECOND_REF_CTRL</div><div class='add'>+#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV__SHIFT                                        0x0</div><div class='add'>+#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV_MASK                                          0x0000007FL</div><div class='add'>+//DPIA_MU_PORT_ADP_STATUS</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS__SHIFT                                              0x0</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS__SHIFT                                              0x2</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS__SHIFT                                              0x3</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS_MASK                                                0x00000001L</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS_MASK                                                0x00000004L</div><div class='add'>+#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS_MASK                                                0x00000008L</div><div class='add'>+//DPIA_GLUE_CTRL</div><div class='add'>+#define DPIA_GLUE_CTRL__DPIA_IO_EN__SHIFT                                                                     0x0</div><div class='add'>+#define DPIA_GLUE_CTRL__DPIA_IO_EN_MASK                                                                       0x00000001L</div><div class='add'>+//DPIA_DEBUG_CONTROL</div><div class='add'>+//DPIA_PERF_COUNT_CONTROL0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__ENABLE__SHIFT                                                               0x0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__MODE__SHIFT                                                                 0x1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__STATUS__SHIFT                                                               0x4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT__SHIFT                                                          0x5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT__SHIFT                                                          0x8</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT__SHIFT                                                          0xc</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__ENABLE_MASK                                                                 0x00000001L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__MODE_MASK                                                                   0x0000000EL</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__STATUS_MASK                                                                 0x00000010L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT_MASK                                                            0x000000E0L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT_MASK                                                            0x00000300L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT_MASK                                                            0xFFFFF000L</div><div class='add'>+//DPIA_PERF_COUNT_CONTROL1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__ENABLE__SHIFT                                                               0x0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__MODE__SHIFT                                                                 0x1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__STATUS__SHIFT                                                               0x4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT__SHIFT                                                          0x5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT__SHIFT                                                          0x8</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT__SHIFT                                                          0xc</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__ENABLE_MASK                                                                 0x00000001L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__MODE_MASK                                                                   0x0000000EL</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__STATUS_MASK                                                                 0x00000010L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT_MASK                                                            0x000000E0L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT_MASK                                                            0x00000300L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT_MASK                                                            0xFFFFF000L</div><div class='add'>+//DPIA_PERF_COUNT_CONTROL2</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__ENABLE__SHIFT                                                               0x0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__MODE__SHIFT                                                                 0x1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__STATUS__SHIFT                                                               0x4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT__SHIFT                                                          0x5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT__SHIFT                                                          0x8</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT__SHIFT                                                          0xc</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__ENABLE_MASK                                                                 0x00000001L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__MODE_MASK                                                                   0x0000000EL</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__STATUS_MASK                                                                 0x00000010L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT_MASK                                                            0x000000E0L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT_MASK                                                            0x00000300L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT_MASK                                                            0xFFFFF000L</div><div class='add'>+//DPIA_PERF_COUNT_CONTROL3</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__ENABLE__SHIFT                                                               0x0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__MODE__SHIFT                                                                 0x1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__STATUS__SHIFT                                                               0x4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT__SHIFT                                                          0x5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT__SHIFT                                                          0x8</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT__SHIFT                                                          0xc</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__ENABLE_MASK                                                                 0x00000001L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__MODE_MASK                                                                   0x0000000EL</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__STATUS_MASK                                                                 0x00000010L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT_MASK                                                            0x000000E0L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT_MASK                                                            0x00000300L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT_MASK                                                            0xFFFFF000L</div><div class='add'>+//DPIA_PERF_COUNT_CONTROL4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__ENABLE__SHIFT                                                               0x0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__MODE__SHIFT                                                                 0x1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__STATUS__SHIFT                                                               0x4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT__SHIFT                                                          0x5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT__SHIFT                                                          0x8</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT__SHIFT                                                          0xc</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__ENABLE_MASK                                                                 0x00000001L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__MODE_MASK                                                                   0x0000000EL</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__STATUS_MASK                                                                 0x00000010L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT_MASK                                                            0x000000E0L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT_MASK                                                            0x00000300L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT_MASK                                                            0xFFFFF000L</div><div class='add'>+//DPIA_PERF_COUNT_CONTROL5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__ENABLE__SHIFT                                                               0x0</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__MODE__SHIFT                                                                 0x1</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__STATUS__SHIFT                                                               0x4</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT__SHIFT                                                          0x5</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT__SHIFT                                                          0x8</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT__SHIFT                                                          0xc</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__ENABLE_MASK                                                                 0x00000001L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__MODE_MASK                                                                   0x0000000EL</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__STATUS_MASK                                                                 0x00000010L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT_MASK                                                            0x000000E0L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT_MASK                                                            0x00000300L</div><div class='add'>+#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT_MASK                                                            0xFFFFF000L</div><div class='add'>+//DPIA_PERF_COUNT_INDEX</div><div class='add'>+#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT__SHIFT                                                          0x0</div><div class='add'>+#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT__SHIFT                                                             0x4</div><div class='add'>+#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT_MASK                                                            0x00000007L</div><div class='add'>+#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT_MASK                                                               0x00000070L</div><div class='add'>+//DPIA_PERF_COUNT_DATA_LO</div><div class='add'>+#define DPIA_PERF_COUNT_DATA_LO__VALUE__SHIFT                                                                 0x0</div><div class='add'>+#define DPIA_PERF_COUNT_DATA_LO__VALUE_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DPIA_MU_SPARE</div><div class='add'>+#define DPIA_MU_SPARE__DPIA_MU_SPARE__SHIFT                                                                   0x0</div><div class='add'>+#define DPIA_MU_SPARE__DPIA_MU_SPARE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_f2codecind</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX__SHIFT                                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI__SHIFT                                             0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE__SHIFT                                       0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX_MASK                                                 0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI_MASK                                               0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE_MASK                                         0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA_MASK                                                   0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_HBR</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_descriptorind</div><div class='add'>+//AUDIO_DESCRIPTOR0</div><div class='add'>+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR1</div><div class='add'>+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR2</div><div class='add'>+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR3</div><div class='add'>+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR4</div><div class='add'>+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR5</div><div class='add'>+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR6</div><div class='add'>+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR7</div><div class='add'>+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR8</div><div class='add'>+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR9</div><div class='add'>+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR10</div><div class='add'>+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR11</div><div class='add'>+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR12</div><div class='add'>+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR13</div><div class='add'>+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_sinkinfoind</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//SINK_DESCRIPTION0</div><div class='add'>+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION1</div><div class='add'>+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION2</div><div class='add'>+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION3</div><div class='add'>+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION4</div><div class='add'>+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION5</div><div class='add'>+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION6</div><div class='add'>+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION7</div><div class='add'>+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION8</div><div class='add'>+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION9</div><div class='add'>+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION10</div><div class='add'>+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION11</div><div class='add'>+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION12</div><div class='add'>+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION13</div><div class='add'>+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION14</div><div class='add'>+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION15</div><div class='add'>+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION16</div><div class='add'>+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION17</div><div class='add'>+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc0resultind</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL1</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL2</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL3</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL4</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL5</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL6</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL7</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc1resultind</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL1</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL2</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL3</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL4</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL5</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL6</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL7</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc0resultind</div><div class='add'>+//AZALIA_CRC0_CHANNEL0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL1</div><div class='add'>+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL2</div><div class='add'>+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL3</div><div class='add'>+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL4</div><div class='add'>+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL5</div><div class='add'>+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL6</div><div class='add'>+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL7</div><div class='add'>+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc1resultind</div><div class='add'>+//AZALIA_CRC1_CHANNEL0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL1</div><div class='add'>+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL2</div><div class='add'>+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL3</div><div class='add'>+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL4</div><div class='add'>+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL5</div><div class='add'>+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL6</div><div class='add'>+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL7</div><div class='add'>+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azinputendpoint_f2codecind</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azroot_f2codecind</div><div class='add'>+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream0_streamind</div><div class='add'>+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream1_streamind</div><div class='add'>+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream2_streamind</div><div class='add'>+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream3_streamind</div><div class='add'>+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream4_streamind</div><div class='add'>+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream5_streamind</div><div class='add'>+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream6_streamind</div><div class='add'>+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream7_streamind</div><div class='add'>+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream8_streamind</div><div class='add'>+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream9_streamind</div><div class='add'>+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream10_streamind</div><div class='add'>+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream11_streamind</div><div class='add'>+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream12_streamind</div><div class='add'>+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream13_streamind</div><div class='add'>+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream14_streamind</div><div class='add'>+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream15_streamind</div><div class='add'>+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint0_endpointind</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint1_endpointind</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint2_endpointind</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint3_endpointind</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint4_endpointind</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint5_endpointind</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint6_endpointind</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint7_endpointind</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint0_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint1_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint2_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint3_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint4_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint5_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint6_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint7_inputendpointind</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h<br/>new file mode 100644<br/>index 000000000000..70ee6be94a9b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_offset.h</a></div><div class='hunk'>@@ -0,0 +1,16662 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+//</div><div class='add'>+// Copyright 2024 Advanced Micro Devices, Inc.</div><div class='add'>+</div><div class='add'>+#ifndef _dcn_4_1_0_OFFSET_HEADER</div><div class='add'>+#define _dcn_4_1_0_OFFSET_HEADER</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dccg_dccg_dfs_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064</div><div class='add'>+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dccg_dccg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040</div><div class='add'>+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041</div><div class='add'>+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042</div><div class='add'>+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043</div><div class='add'>+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regDP_DTO_DBUF_EN                                                                               0x0044</div><div class='add'>+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1</div><div class='add'>+#define regDSCCLK3_DTO_PARAM                                                                            0x0045</div><div class='add'>+#define regDSCCLK3_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDSCCLK4_DTO_PARAM                                                                            0x0046</div><div class='add'>+#define regDSCCLK4_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDSCCLK5_DTO_PARAM                                                                            0x0047</div><div class='add'>+#define regDSCCLK5_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048</div><div class='add'>+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1</div><div class='add'>+#define regDPSTREAMCLK_CNTL                                                                             0x004a</div><div class='add'>+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1</div><div class='add'>+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b</div><div class='add'>+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c</div><div class='add'>+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1                                                               1</div><div class='add'>+#define regDCCG_GLOBAL_FGCG_REP_CNTL                                                                    0x0050</div><div class='add'>+#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX                                                           1</div><div class='add'>+#define regSYMCLKG_CLOCK_ENABLE                                                                         0x0057</div><div class='add'>+#define regSYMCLKG_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regDPREFCLK_CNTL                                                                                0x0058</div><div class='add'>+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1</div><div class='add'>+#define regAOMCLK0_CNTL                                                                                 0x0059</div><div class='add'>+#define regAOMCLK0_CNTL_BASE_IDX                                                                        1</div><div class='add'>+#define regAOMCLK1_CNTL                                                                                 0x005a</div><div class='add'>+#define regAOMCLK1_CNTL_BASE_IDX                                                                        1</div><div class='add'>+#define regAOMCLK2_CNTL                                                                                 0x005b</div><div class='add'>+#define regAOMCLK2_CNTL_BASE_IDX                                                                        1</div><div class='add'>+#define regDCCG_AUDIO_DTO2_PHASE                                                                        0x005c</div><div class='add'>+#define regDCCG_AUDIO_DTO2_PHASE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO2_MODULO                                                                       0x005d</div><div class='add'>+#define regDCCG_AUDIO_DTO2_MODULO_BASE_IDX                                                              1</div><div class='add'>+#define regDCE_VERSION                                                                                  0x005e</div><div class='add'>+#define regDCE_VERSION_BASE_IDX                                                                         1</div><div class='add'>+#define regPHYPLLG_PIXCLK_RESYNC_CNTL                                                                   0x005f</div><div class='add'>+#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regSYMCLK32_SE_CNTL                                                                             0x0065</div><div class='add'>+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1</div><div class='add'>+#define regSYMCLK32_LE_CNTL                                                                             0x0066</div><div class='add'>+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1</div><div class='add'>+#define regDTBCLK_P_CNTL                                                                                0x0068</div><div class='add'>+#define regDTBCLK_P_CNTL_BASE_IDX                                                                       1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL5                                                                      0x0069</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX                                                             1</div><div class='add'>+#define regDSCCLK0_DTO_PARAM                                                                            0x006c</div><div class='add'>+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDSCCLK1_DTO_PARAM                                                                            0x006d</div><div class='add'>+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDSCCLK2_DTO_PARAM                                                                            0x006e</div><div class='add'>+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regOTG_PIXEL_RATE_DIV                                                                           0x006f</div><div class='add'>+#define regOTG_PIXEL_RATE_DIV_BASE_IDX                                                                  1</div><div class='add'>+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070</div><div class='add'>+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1</div><div class='add'>+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071</div><div class='add'>+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1</div><div class='add'>+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072</div><div class='add'>+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1</div><div class='add'>+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075</div><div class='add'>+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1</div><div class='add'>+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076</div><div class='add'>+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regDCCG_CAC_STATUS                                                                              0x0077</div><div class='add'>+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1</div><div class='add'>+#define regPIXCLK1_RESYNC_CNTL                                                                          0x0078</div><div class='add'>+#define regPIXCLK1_RESYNC_CNTL_BASE_IDX                                                                 1</div><div class='add'>+#define regPIXCLK2_RESYNC_CNTL                                                                          0x0079</div><div class='add'>+#define regPIXCLK2_RESYNC_CNTL_BASE_IDX                                                                 1</div><div class='add'>+#define regPIXCLK0_RESYNC_CNTL                                                                          0x007a</div><div class='add'>+#define regPIXCLK0_RESYNC_CNTL_BASE_IDX                                                                 1</div><div class='add'>+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b</div><div class='add'>+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1</div><div class='add'>+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d</div><div class='add'>+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regPHYPLLF_PIXCLK_RESYNC_CNTL                                                                   0x007e</div><div class='add'>+#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1</div><div class='add'>+#define regDCCG_DISP_CNTL_REG                                                                           0x007f</div><div class='add'>+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1</div><div class='add'>+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080</div><div class='add'>+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO0_PHASE                                                                                0x0081</div><div class='add'>+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO0_MODULO                                                                               0x0082</div><div class='add'>+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083</div><div class='add'>+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084</div><div class='add'>+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO1_PHASE                                                                                0x0085</div><div class='add'>+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO1_MODULO                                                                               0x0086</div><div class='add'>+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087</div><div class='add'>+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088</div><div class='add'>+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO2_PHASE                                                                                0x0089</div><div class='add'>+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO2_MODULO                                                                               0x008a</div><div class='add'>+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b</div><div class='add'>+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c</div><div class='add'>+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO3_PHASE                                                                                0x008d</div><div class='add'>+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO3_MODULO                                                                               0x008e</div><div class='add'>+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f</div><div class='add'>+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG4_PIXEL_RATE_CNTL                                                                         0x0090</div><div class='add'>+#define regOTG4_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO4_PHASE                                                                                0x0091</div><div class='add'>+#define regDP_DTO4_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO4_MODULO                                                                               0x0092</div><div class='add'>+#define regDP_DTO4_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG4_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0093</div><div class='add'>+#define regOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regOTG5_PIXEL_RATE_CNTL                                                                         0x0094</div><div class='add'>+#define regOTG5_PIXEL_RATE_CNTL_BASE_IDX                                                                1</div><div class='add'>+#define regDP_DTO5_PHASE                                                                                0x0095</div><div class='add'>+#define regDP_DTO5_PHASE_BASE_IDX                                                                       1</div><div class='add'>+#define regDP_DTO5_MODULO                                                                               0x0096</div><div class='add'>+#define regDP_DTO5_MODULO_BASE_IDX                                                                      1</div><div class='add'>+#define regOTG5_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0097</div><div class='add'>+#define regOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1</div><div class='add'>+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098</div><div class='add'>+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1</div><div class='add'>+#define regDPPCLK0_DTO_PARAM                                                                            0x0099</div><div class='add'>+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK1_DTO_PARAM                                                                            0x009a</div><div class='add'>+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK2_DTO_PARAM                                                                            0x009b</div><div class='add'>+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK3_DTO_PARAM                                                                            0x009c</div><div class='add'>+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK4_DTO_PARAM                                                                            0x009d</div><div class='add'>+#define regDPPCLK4_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDPPCLK5_DTO_PARAM                                                                            0x009e</div><div class='add'>+#define regDPPCLK5_DTO_PARAM_BASE_IDX                                                                   1</div><div class='add'>+#define regDCCG_CAC_STATUS2                                                                             0x009f</div><div class='add'>+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1</div><div class='add'>+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0</div><div class='add'>+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1</div><div class='add'>+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2</div><div class='add'>+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3</div><div class='add'>+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4</div><div class='add'>+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regSYMCLKF_CLOCK_ENABLE                                                                         0x00a5</div><div class='add'>+#define regSYMCLKF_CLOCK_ENABLE_BASE_IDX                                                                1</div><div class='add'>+#define regDCCG_SOFT_RESET                                                                              0x00a6</div><div class='add'>+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1</div><div class='add'>+#define regDSCCLK_DTO_CTRL                                                                              0x00a7</div><div class='add'>+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1</div><div class='add'>+#define regDPPCLK_CTRL                                                                                  0x00a8</div><div class='add'>+#define regDPPCLK_CTRL_BASE_IDX                                                                         1</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL6                                                                      0x00a9</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX                                                             1</div><div class='add'>+#define regSYMCLK_PSP_CNTL                                                                              0x00aa</div><div class='add'>+#define regSYMCLK_PSP_CNTL_BASE_IDX                                                                     1</div><div class='add'>+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab</div><div class='add'>+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac</div><div class='add'>+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad</div><div class='add'>+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1</div><div class='add'>+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae</div><div class='add'>+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1</div><div class='add'>+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af</div><div class='add'>+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1</div><div class='add'>+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0</div><div class='add'>+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1</div><div class='add'>+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2</div><div class='add'>+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3</div><div class='add'>+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4</div><div class='add'>+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5</div><div class='add'>+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1</div><div class='add'>+#define regDPPCLK_DTO_CTRL                                                                              0x00b6</div><div class='add'>+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1</div><div class='add'>+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8</div><div class='add'>+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1</div><div class='add'>+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9</div><div class='add'>+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1</div><div class='add'>+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba</div><div class='add'>+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1</div><div class='add'>+#define regDCCG_TEST_CLK_SEL                                                                            0x00be</div><div class='add'>+#define regDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL                                                                      0x004a</div><div class='add'>+#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regHDMICHARCLK1_CLOCK_CNTL                                                                      0x004b</div><div class='add'>+#define regHDMICHARCLK1_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regHDMICHARCLK2_CLOCK_CNTL                                                                      0x004c</div><div class='add'>+#define regHDMICHARCLK2_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regHDMICHARCLK3_CLOCK_CNTL                                                                      0x004d</div><div class='add'>+#define regHDMICHARCLK3_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regHDMICHARCLK4_CLOCK_CNTL                                                                      0x004e</div><div class='add'>+#define regHDMICHARCLK4_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regHDMICHARCLK5_CLOCK_CNTL                                                                      0x004f</div><div class='add'>+#define regHDMICHARCLK5_CLOCK_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052</div><div class='add'>+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053</div><div class='add'>+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054</div><div class='add'>+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055</div><div class='add'>+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056</div><div class='add'>+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYFSYMCLK_CLOCK_CNTL                                                                        0x0057</div><div class='add'>+#define regPHYFSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regPHYGSYMCLK_CLOCK_CNTL                                                                        0x0058</div><div class='add'>+#define regPHYGSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regHDMISTREAMCLK_CNTL                                                                           0x0059</div><div class='add'>+#define regHDMISTREAMCLK_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a</div><div class='add'>+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2</div><div class='add'>+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b</div><div class='add'>+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+// base address: 0x0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// base address: 0x30</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_fgsec_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a</div><div class='add'>+#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_rbbmif_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regRBBMIF_TIMEOUT                                                                               0x017f</div><div class='add'>+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2</div><div class='add'>+#define regRBBMIF_STATUS                                                                                0x0180</div><div class='add'>+#define regRBBMIF_STATUS_BASE_IDX                                                                       2</div><div class='add'>+#define regRBBMIF_STATUS_2                                                                              0x0181</div><div class='add'>+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2</div><div class='add'>+#define regRBBMIF_INT_STATUS                                                                            0x0182</div><div class='add'>+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184</div><div class='add'>+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2</div><div class='add'>+#define regRBBMIF_STATUS_FLAG                                                                           0x0185</div><div class='add'>+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_ihc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2</div><div class='add'>+#define regDC_GPU_TIMER_READ                                                                            0x0128</div><div class='add'>+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129</div><div class='add'>+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS                                                                        0x012a</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144</div><div class='add'>+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147</div><div class='add'>+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2</div><div class='add'>+#define regDCCG_INTERRUPT_DEST                                                                          0x0148</div><div class='add'>+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDMU_INTERRUPT_DEST                                                                           0x0149</div><div class='add'>+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regDMU_INTERRUPT_DEST2                                                                          0x014a</div><div class='add'>+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2</div><div class='add'>+#define regDCPG_INTERRUPT_DEST                                                                          0x014b</div><div class='add'>+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c</div><div class='add'>+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2</div><div class='add'>+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d</div><div class='add'>+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2</div><div class='add'>+#define regWB_INTERRUPT_DEST                                                                            0x014e</div><div class='add'>+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2</div><div class='add'>+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150</div><div class='add'>+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151</div><div class='add'>+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152</div><div class='add'>+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2</div><div class='add'>+#define regMPC_INTERRUPT_DEST                                                                           0x0153</div><div class='add'>+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regOPP_INTERRUPT_DEST                                                                           0x0154</div><div class='add'>+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regOPTC_INTERRUPT_DEST                                                                          0x0155</div><div class='add'>+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG0_INTERRUPT_DEST                                                                          0x0156</div><div class='add'>+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG1_INTERRUPT_DEST                                                                          0x0157</div><div class='add'>+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG2_INTERRUPT_DEST                                                                          0x0158</div><div class='add'>+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG3_INTERRUPT_DEST                                                                          0x0159</div><div class='add'>+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG4_INTERRUPT_DEST                                                                          0x015a</div><div class='add'>+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG5_INTERRUPT_DEST                                                                          0x015b</div><div class='add'>+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG_INTERRUPT_DEST                                                                           0x015c</div><div class='add'>+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d</div><div class='add'>+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2</div><div class='add'>+#define regHDCP_INTERRUPT_DEST                                                                          0x015e</div><div class='add'>+#define regHDCP_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regDIO_INTERRUPT_DEST                                                                           0x015f</div><div class='add'>+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regDCIO_INTERRUPT_DEST                                                                          0x0160</div><div class='add'>+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD_INTERRUPT_DEST                                                                           0x0161</div><div class='add'>+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regAZ_INTERRUPT_DEST                                                                            0x0162</div><div class='add'>+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2</div><div class='add'>+#define regAUX_INTERRUPT_DEST                                                                           0x0163</div><div class='add'>+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regDSC_INTERRUPT_DEST                                                                           0x0164</div><div class='add'>+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+#define regHPO_INTERRUPT_DEST                                                                           0x0165</div><div class='add'>+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dmu_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCC_DC_PIPE_DIS                                                                               0x00ca</div><div class='add'>+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2</div><div class='add'>+#define regDMU_CLK_CNTL                                                                                 0x00cb</div><div class='add'>+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDMCUB_SMU_INTERRUPT_CNTL                                                                     0x00cd</div><div class='add'>+#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce</div><div class='add'>+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6</div><div class='add'>+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2</div><div class='add'>+#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG                                                                0x00d8</div><div class='add'>+#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                       2</div><div class='add'>+#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG                                                                 0x00d9</div><div class='add'>+#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dc_pg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDOMAIN0_PG_CONFIG                                                                            0x0080</div><div class='add'>+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN0_PG_STATUS                                                                            0x0081</div><div class='add'>+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN1_PG_CONFIG                                                                            0x0082</div><div class='add'>+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN1_PG_STATUS                                                                            0x0083</div><div class='add'>+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN2_PG_CONFIG                                                                            0x0084</div><div class='add'>+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN2_PG_STATUS                                                                            0x0085</div><div class='add'>+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN3_PG_CONFIG                                                                            0x0086</div><div class='add'>+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN3_PG_STATUS                                                                            0x0087</div><div class='add'>+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDOMAIN16_PG_CONFIG                                                                           0x0089</div><div class='add'>+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN16_PG_STATUS                                                                           0x008a</div><div class='add'>+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN17_PG_CONFIG                                                                           0x008b</div><div class='add'>+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN17_PG_STATUS                                                                           0x008c</div><div class='add'>+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN18_PG_CONFIG                                                                           0x008d</div><div class='add'>+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN18_PG_STATUS                                                                           0x008e</div><div class='add'>+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN19_PG_CONFIG                                                                           0x008f</div><div class='add'>+#define regDOMAIN19_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN19_PG_STATUS                                                                           0x0090</div><div class='add'>+#define regDOMAIN19_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN22_PG_CONFIG                                                                           0x0092</div><div class='add'>+#define regDOMAIN22_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN22_PG_STATUS                                                                           0x0093</div><div class='add'>+#define regDOMAIN22_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN23_PG_CONFIG                                                                           0x0094</div><div class='add'>+#define regDOMAIN23_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN23_PG_STATUS                                                                           0x0095</div><div class='add'>+#define regDOMAIN23_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN24_PG_CONFIG                                                                           0x0096</div><div class='add'>+#define regDOMAIN24_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN24_PG_STATUS                                                                           0x0097</div><div class='add'>+#define regDOMAIN24_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN25_PG_CONFIG                                                                           0x0098</div><div class='add'>+#define regDOMAIN25_PG_CONFIG_BASE_IDX                                                                  2</div><div class='add'>+#define regDOMAIN25_PG_STATUS                                                                           0x0099</div><div class='add'>+#define regDOMAIN25_PG_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS                                                                        0x009a</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x009b</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_3                                                                      0x009c</div><div class='add'>+#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX                                                             2</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x009d</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_2                                                                     0x009e</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x009f</div><div class='add'>+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2</div><div class='add'>+#define regDC_IP_REQUEST_CNTL                                                                           0x00a0</div><div class='add'>+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_PGCNTL_STATUS_REG                                                                         0x00a1</div><div class='add'>+#define regDC_PGCNTL_STATUS_REG_BASE_IDX                                                                2</div><div class='add'>+#define regLONO_MEM_PWR_REQ_CNTL                                                                        0x00a4</div><div class='add'>+#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dmcub_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDMCUB_REGION0_OFFSET                                                                         0x018e</div><div class='add'>+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f</div><div class='add'>+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION1_OFFSET                                                                         0x0190</div><div class='add'>+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191</div><div class='add'>+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION2_OFFSET                                                                         0x0192</div><div class='add'>+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193</div><div class='add'>+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION4_OFFSET                                                                         0x0196</div><div class='add'>+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197</div><div class='add'>+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION5_OFFSET                                                                         0x0198</div><div class='add'>+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199</div><div class='add'>+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION6_OFFSET                                                                         0x019a</div><div class='add'>+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b</div><div class='add'>+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION7_OFFSET                                                                         0x019c</div><div class='add'>+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d</div><div class='add'>+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e</div><div class='add'>+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f</div><div class='add'>+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0</div><div class='add'>+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1</div><div class='add'>+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2</div><div class='add'>+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3</div><div class='add'>+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4</div><div class='add'>+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5</div><div class='add'>+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6</div><div class='add'>+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7</div><div class='add'>+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8</div><div class='add'>+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9</div><div class='add'>+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa</div><div class='add'>+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab</div><div class='add'>+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac</div><div class='add'>+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2</div><div class='add'>+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad</div><div class='add'>+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae</div><div class='add'>+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af</div><div class='add'>+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0</div><div class='add'>+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1</div><div class='add'>+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2</div><div class='add'>+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3</div><div class='add'>+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4</div><div class='add'>+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6</div><div class='add'>+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8</div><div class='add'>+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba</div><div class='add'>+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc</div><div class='add'>+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be</div><div class='add'>+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0</div><div class='add'>+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2</div><div class='add'>+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4</div><div class='add'>+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5</div><div class='add'>+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6</div><div class='add'>+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7</div><div class='add'>+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8</div><div class='add'>+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb</div><div class='add'>+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2</div><div class='add'>+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc</div><div class='add'>+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd</div><div class='add'>+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDMCUB_SEC_CNTL                                                                               0x01ce</div><div class='add'>+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_MEM_CNTL                                                                               0x01cf</div><div class='add'>+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0</div><div class='add'>+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1</div><div class='add'>+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2</div><div class='add'>+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3</div><div class='add'>+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4</div><div class='add'>+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2</div><div class='add'>+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5</div><div class='add'>+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6</div><div class='add'>+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7</div><div class='add'>+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2</div><div class='add'>+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8</div><div class='add'>+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2</div><div class='add'>+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9</div><div class='add'>+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da</div><div class='add'>+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db</div><div class='add'>+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc</div><div class='add'>+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2</div><div class='add'>+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd</div><div class='add'>+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de</div><div class='add'>+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df</div><div class='add'>+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1</div><div class='add'>+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2</div><div class='add'>+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_SCRATCH0                                                                               0x01e3</div><div class='add'>+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH1                                                                               0x01e4</div><div class='add'>+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH2                                                                               0x01e5</div><div class='add'>+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH3                                                                               0x01e6</div><div class='add'>+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH4                                                                               0x01e7</div><div class='add'>+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH5                                                                               0x01e8</div><div class='add'>+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH6                                                                               0x01e9</div><div class='add'>+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH7                                                                               0x01ea</div><div class='add'>+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH8                                                                               0x01eb</div><div class='add'>+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH9                                                                               0x01ec</div><div class='add'>+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2</div><div class='add'>+#define regDMCUB_SCRATCH10                                                                              0x01ed</div><div class='add'>+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH11                                                                              0x01ee</div><div class='add'>+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH12                                                                              0x01ef</div><div class='add'>+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH13                                                                              0x01f0</div><div class='add'>+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH14                                                                              0x01f1</div><div class='add'>+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH15                                                                              0x01f2</div><div class='add'>+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH16                                                                              0x01f3</div><div class='add'>+#define regDMCUB_SCRATCH16_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH17                                                                              0x01f4</div><div class='add'>+#define regDMCUB_SCRATCH17_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH18                                                                              0x01f5</div><div class='add'>+#define regDMCUB_SCRATCH18_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_CNTL                                                                                   0x01f6</div><div class='add'>+#define regDMCUB_CNTL_BASE_IDX                                                                          2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7</div><div class='add'>+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8</div><div class='add'>+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9</div><div class='add'>+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa</div><div class='add'>+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2</div><div class='add'>+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb</div><div class='add'>+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2</div><div class='add'>+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc</div><div class='add'>+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd</div><div class='add'>+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_PROC_ID                                                                                0x01ff</div><div class='add'>+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2</div><div class='add'>+#define regDMCUB_CNTL2                                                                                  0x0200</div><div class='add'>+#define regDMCUB_CNTL2_BASE_IDX                                                                         2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN2                                                                          0x0215</div><div class='add'>+#define regDMCUB_GPINT_DATAIN2_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN3                                                                          0x0216</div><div class='add'>+#define regDMCUB_GPINT_DATAIN3_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN4                                                                          0x0217</div><div class='add'>+#define regDMCUB_GPINT_DATAIN4_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN5                                                                          0x0218</div><div class='add'>+#define regDMCUB_GPINT_DATAIN5_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_GPINT_DATAIN6                                                                          0x0219</div><div class='add'>+#define regDMCUB_GPINT_DATAIN6_BASE_IDX                                                                 2</div><div class='add'>+#define regDMCUB_REGION3_TMR_AXI_SPACE                                                                  0x021a</div><div class='add'>+#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX                                                         2</div><div class='add'>+#define regDMCUB_SCRATCH19                                                                              0x021b</div><div class='add'>+#define regDMCUB_SCRATCH19_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH20                                                                              0x021c</div><div class='add'>+#define regDMCUB_SCRATCH20_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH21                                                                              0x021d</div><div class='add'>+#define regDMCUB_SCRATCH21_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH22                                                                              0x021e</div><div class='add'>+#define regDMCUB_SCRATCH22_BASE_IDX                                                                     2</div><div class='add'>+#define regDMCUB_SCRATCH23                                                                              0x021f</div><div class='add'>+#define regDMCUB_SCRATCH23_BASE_IDX                                                                     2</div><div class='add'>+#define regHOST_INTERRUPT_CSR                                                                           0x0222</div><div class='add'>+#define regHOST_INTERRUPT_CSR_BASE_IDX                                                                  2</div><div class='add'>+#define regDMCUB_REG_INBOX0_RDY                                                                         0x0223</div><div class='add'>+#define regDMCUB_REG_INBOX0_RDY_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG0                                                                        0x0224</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG0_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG1                                                                        0x0225</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG1_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG2                                                                        0x0226</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG2_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG3                                                                        0x0227</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG3_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG4                                                                        0x0228</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG4_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG5                                                                        0x0229</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG5_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG6                                                                        0x022a</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG6_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG7                                                                        0x022b</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG7_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG8                                                                        0x022c</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG8_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG9                                                                        0x022d</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG9_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG10                                                                       0x022e</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG10_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG11                                                                       0x022f</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG11_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG12                                                                       0x0230</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG12_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG13                                                                       0x0231</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG13_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG14                                                                       0x0232</div><div class='add'>+#define regDMCUB_REG_INBOX0_MSG14_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_REG_INBOX0_RSP                                                                         0x0233</div><div class='add'>+#define regDMCUB_REG_INBOX0_RSP_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_OUTBOX0_RDY                                                                        0x0234</div><div class='add'>+#define regDMCUB_REG_OUTBOX0_RDY_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_OUTBOX0_MSG0                                                                       0x0235</div><div class='add'>+#define regDMCUB_REG_OUTBOX0_MSG0_BASE_IDX                                                              2</div><div class='add'>+#define regDMCUB_REG_OUTBOX0_RSP                                                                        0x0236</div><div class='add'>+#define regDMCUB_REG_OUTBOX0_RSP_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX1_RDY                                                                         0x0237</div><div class='add'>+#define regDMCUB_REG_INBOX1_RDY_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX1_MSG0                                                                        0x0238</div><div class='add'>+#define regDMCUB_REG_INBOX1_MSG0_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX1_MSG1                                                                        0x0239</div><div class='add'>+#define regDMCUB_REG_INBOX1_MSG1_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX1_RSP                                                                         0x023a</div><div class='add'>+#define regDMCUB_REG_INBOX1_RSP_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX2_RDY                                                                         0x023b</div><div class='add'>+#define regDMCUB_REG_INBOX2_RDY_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX2_MSG0                                                                        0x023c</div><div class='add'>+#define regDMCUB_REG_INBOX2_MSG0_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX2_MSG1                                                                        0x023d</div><div class='add'>+#define regDMCUB_REG_INBOX2_MSG1_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX2_RSP                                                                         0x023e</div><div class='add'>+#define regDMCUB_REG_INBOX2_RSP_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX3_RDY                                                                         0x023f</div><div class='add'>+#define regDMCUB_REG_INBOX3_RDY_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX3_MSG0                                                                        0x0240</div><div class='add'>+#define regDMCUB_REG_INBOX3_MSG0_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX3_MSG1                                                                        0x0241</div><div class='add'>+#define regDMCUB_REG_INBOX3_MSG1_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX3_RSP                                                                         0x0242</div><div class='add'>+#define regDMCUB_REG_INBOX3_RSP_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX4_RDY                                                                         0x0243</div><div class='add'>+#define regDMCUB_REG_INBOX4_RDY_BASE_IDX                                                                2</div><div class='add'>+#define regDMCUB_REG_INBOX4_MSG0                                                                        0x0244</div><div class='add'>+#define regDMCUB_REG_INBOX4_MSG0_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX4_MSG1                                                                        0x0245</div><div class='add'>+#define regDMCUB_REG_INBOX4_MSG1_BASE_IDX                                                               2</div><div class='add'>+#define regDMCUB_REG_INBOX4_RSP                                                                         0x0246</div><div class='add'>+#define regDMCUB_REG_INBOX4_RSP_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_wb0_dispdec_dwb_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228</div><div class='add'>+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regDWB_MEM_PWR_CTRL                                                                             0x3229</div><div class='add'>+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2</div><div class='add'>+#define regFC_MODE_CTRL                                                                                 0x322a</div><div class='add'>+#define regFC_MODE_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regFC_FLOW_CTRL                                                                                 0x322b</div><div class='add'>+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regFC_WINDOW_START                                                                              0x322c</div><div class='add'>+#define regFC_WINDOW_START_BASE_IDX                                                                     2</div><div class='add'>+#define regFC_WINDOW_SIZE                                                                               0x322d</div><div class='add'>+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regFC_SOURCE_SIZE                                                                               0x322e</div><div class='add'>+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDWB_UPDATE_CTRL                                                                              0x322f</div><div class='add'>+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2</div><div class='add'>+#define regDWB_CRC_CTRL                                                                                 0x3230</div><div class='add'>+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regDWB_CRC_MASK_R_G                                                                             0x3231</div><div class='add'>+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2</div><div class='add'>+#define regDWB_CRC_MASK_B_A                                                                             0x3232</div><div class='add'>+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2</div><div class='add'>+#define regDWB_CRC_VAL_R_G                                                                              0x3233</div><div class='add'>+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2</div><div class='add'>+#define regDWB_CRC_VAL_B_A                                                                              0x3234</div><div class='add'>+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2</div><div class='add'>+#define regDWB_OUT_CTRL                                                                                 0x3235</div><div class='add'>+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237</div><div class='add'>+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2</div><div class='add'>+#define regDWB_HOST_READ_CONTROL                                                                        0x3238</div><div class='add'>+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDWB_OVERFLOW_STATUS                                                                          0x3239</div><div class='add'>+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2</div><div class='add'>+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a</div><div class='add'>+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2</div><div class='add'>+#define regDWB_SOFT_RESET                                                                               0x323b</div><div class='add'>+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2</div><div class='add'>+#define regDWB_DEBUG_CTRL                                                                               0x323c</div><div class='add'>+#define regDWB_DEBUG_CTRL_BASE_IDX                                                                      2</div><div class='add'>+#define regDWB_DEBUG                                                                                    0x323d</div><div class='add'>+#define regDWB_DEBUG_BASE_IDX                                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_wb0_dispdec_dwbcp_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDWB_HDR_MULT_COEF                                                                            0x3294</div><div class='add'>+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2</div><div class='add'>+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295</div><div class='add'>+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2</div><div class='add'>+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296</div><div class='add'>+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c</div><div class='add'>+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2</div><div class='add'>+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_CONTROL                                                                             0x32a3</div><div class='add'>+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4</div><div class='add'>+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2</div><div class='add'>+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5</div><div class='add'>+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2</div><div class='add'>+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6</div><div class='add'>+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9</div><div class='add'>+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae</div><div class='add'>+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af</div><div class='add'>+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5</div><div class='add'>+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8</div><div class='add'>+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9</div><div class='add'>+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc</div><div class='add'>+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1</div><div class='add'>+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2</div><div class='add'>+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8</div><div class='add'>+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db</div><div class='add'>+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec</div><div class='add'>+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mmhubbub_mcif_wb0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272</div><div class='add'>+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274</div><div class='add'>+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_PITCH                                                                            0x0275</div><div class='add'>+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277</div><div class='add'>+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279</div><div class='add'>+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b</div><div class='add'>+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d</div><div class='add'>+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e</div><div class='add'>+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f</div><div class='add'>+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2</div><div class='add'>+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280</div><div class='add'>+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281</div><div class='add'>+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292</div><div class='add'>+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294</div><div class='add'>+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296</div><div class='add'>+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297</div><div class='add'>+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_SECURITY_LEVEL                                                                       0x0298</div><div class='add'>+#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX                                                              2</div><div class='add'>+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299</div><div class='add'>+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a</div><div class='add'>+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c</div><div class='add'>+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e</div><div class='add'>+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0</div><div class='add'>+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2</div><div class='add'>+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2</div><div class='add'>+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3</div><div class='add'>+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4</div><div class='add'>+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5</div><div class='add'>+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6</div><div class='add'>+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2</div><div class='add'>+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI                                                           0x02a7</div><div class='add'>+#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX                                                  2</div><div class='add'>+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8</div><div class='add'>+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regMCIF_WB_MIN_TTO                                                                              0x02a9</div><div class='add'>+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mmhubbub_mmhubbub_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa</div><div class='add'>+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2</div><div class='add'>+#define regMCIF_WB_WATERMARK                                                                            0x02ab</div><div class='add'>+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad</div><div class='add'>+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af</div><div class='add'>+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2</div><div class='add'>+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0</div><div class='add'>+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2</div><div class='add'>+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1</div><div class='add'>+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2</div><div class='add'>+#define regMMHUBBUB_CTRL                                                                                0x0333</div><div class='add'>+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2</div><div class='add'>+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334</div><div class='add'>+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regWBIF0_MISC_CTRL                                                                              0x0335</div><div class='add'>+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2</div><div class='add'>+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336</div><div class='add'>+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2</div><div class='add'>+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337</div><div class='add'>+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f</div><div class='add'>+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0340</div><div class='add'>+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regMMHUBBUB_SOFT_RESET                                                                          0x0341</div><div class='add'>+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2</div><div class='add'>+#define regDMU_IF_ERR_STATUS                                                                            0x0345</div><div class='add'>+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346</div><div class='add'>+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2</div><div class='add'>+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348</div><div class='add'>+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0controller_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2</div><div class='add'>+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2</div><div class='add'>+#define regAZALIA_AUDIO_DTO                                                                             0x03c3</div><div class='add'>+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2</div><div class='add'>+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4</div><div class='add'>+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5</div><div class='add'>+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6</div><div class='add'>+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2</div><div class='add'>+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7</div><div class='add'>+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8</div><div class='add'>+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9</div><div class='add'>+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca</div><div class='add'>+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3</div><div class='add'>+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4</div><div class='add'>+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2</div><div class='add'>+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5</div><div class='add'>+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6</div><div class='add'>+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc</div><div class='add'>+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd</div><div class='add'>+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1</div><div class='add'>+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2</div><div class='add'>+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3</div><div class='add'>+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4</div><div class='add'>+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5</div><div class='add'>+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6</div><div class='add'>+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC0_RESULT                                                                           0x03e7</div><div class='add'>+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8</div><div class='add'>+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9</div><div class='add'>+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea</div><div class='add'>+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb</div><div class='add'>+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2</div><div class='add'>+#define regAZALIA_CRC1_RESULT                                                                           0x03ec</div><div class='add'>+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2</div><div class='add'>+#define regAZALIA_SOFT_RESET                                                                            0x03ed</div><div class='add'>+#define regAZALIA_SOFT_RESET_BASE_IDX                                                                   2</div><div class='add'>+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee</div><div class='add'>+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef</div><div class='add'>+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0root_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407</div><div class='add'>+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2</div><div class='add'>+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408</div><div class='add'>+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2</div><div class='add'>+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409</div><div class='add'>+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411</div><div class='add'>+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2</div><div class='add'>+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412</div><div class='add'>+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2</div><div class='add'>+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413</div><div class='add'>+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2</div><div class='add'>+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c</div><div class='add'>+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2</div><div class='add'>+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d</div><div class='add'>+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_az_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZ_CLOCK_CNTL                                                                                0x0372</div><div class='add'>+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2</div><div class='add'>+#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0373</div><div class='add'>+#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regAZ_STRAPS                                                                                    0x0374</div><div class='add'>+#define regAZ_STRAPS_BASE_IDX                                                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f</div><div class='add'>+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream1_dispdec</div><div class='add'>+// base address: 0x8</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361</div><div class='add'>+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream2_dispdec</div><div class='add'>+// base address: 0x10</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363</div><div class='add'>+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream3_dispdec</div><div class='add'>+// base address: 0x18</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365</div><div class='add'>+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream4_dispdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367</div><div class='add'>+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream5_dispdec</div><div class='add'>+// base address: 0x28</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369</div><div class='add'>+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream6_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b</div><div class='add'>+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream7_dispdec</div><div class='add'>+// base address: 0x38</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d</div><div class='add'>+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream8_dispdec</div><div class='add'>+// base address: 0x320</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427</div><div class='add'>+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream9_dispdec</div><div class='add'>+// base address: 0x328</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429</div><div class='add'>+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream10_dispdec</div><div class='add'>+// base address: 0x330</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b</div><div class='add'>+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream11_dispdec</div><div class='add'>+// base address: 0x338</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d</div><div class='add'>+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream12_dispdec</div><div class='add'>+// base address: 0x340</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f</div><div class='add'>+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream13_dispdec</div><div class='add'>+// base address: 0x348</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431</div><div class='add'>+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream14_dispdec</div><div class='add'>+// base address: 0x350</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433</div><div class='add'>+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream15_dispdec</div><div class='add'>+// base address: 0x358</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435</div><div class='add'>+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387</div><div class='add'>+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint1_dispdec</div><div class='add'>+// base address: 0x18</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d</div><div class='add'>+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint2_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393</div><div class='add'>+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint3_dispdec</div><div class='add'>+// base address: 0x48</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399</div><div class='add'>+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint4_dispdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f</div><div class='add'>+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint5_dispdec</div><div class='add'>+// base address: 0x78</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5</div><div class='add'>+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint6_dispdec</div><div class='add'>+// base address: 0x90</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab</div><div class='add'>+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint7_dispdec</div><div class='add'>+// base address: 0xa8</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1</div><div class='add'>+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b</div><div class='add'>+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint1_dispdec</div><div class='add'>+// base address: 0x10</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f</div><div class='add'>+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint2_dispdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443</div><div class='add'>+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint3_dispdec</div><div class='add'>+// base address: 0x30</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447</div><div class='add'>+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint4_dispdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b</div><div class='add'>+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint5_dispdec</div><div class='add'>+// base address: 0x50</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f</div><div class='add'>+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint6_dispdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453</div><div class='add'>+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint7_dispdec</div><div class='add'>+// base address: 0x70</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457</div><div class='add'>+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9</div><div class='add'>+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa</div><div class='add'>+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb</div><div class='add'>+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc</div><div class='add'>+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL                                                             0x04fd</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fe</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A                                                      0x04ff</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x0500</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A                                                          0x0501</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A_BASE_IDX                                                 2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x0502</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0503</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A                                                     0x0504</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A                                                      0x0505</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A                                                     0x0506</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A                                                      0x0507</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A                                                     0x0508</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A                                                      0x0509</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x050a</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A                                                 0x050b</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A                                                  0x050c</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A                                                 0x050d</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x050e</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x050f</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A                                                              0x0510</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0511</div><div class='add'>+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B                                                      0x0512</div><div class='add'>+#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0513</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B                                                          0x0514</div><div class='add'>+#define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B_BASE_IDX                                                 2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0515</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0516</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B                                                     0x0517</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B                                                      0x0518</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B                                                     0x0519</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B                                                      0x051a</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B                                                     0x051b</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B_BASE_IDX                                            2</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B                                                      0x051c</div><div class='add'>+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B_BASE_IDX                                             2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x051d</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B                                                 0x051e</div><div class='add'>+#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B                                                  0x051f</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX                                         2</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B                                                 0x0520</div><div class='add'>+#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX                                        2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0521</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0522</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B                                                              0x0523</div><div class='add'>+#define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B_BASE_IDX                                                     2</div><div class='add'>+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0524</div><div class='add'>+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_ARB_MALL_CNTL                                                                       0x0525</div><div class='add'>+#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0526</div><div class='add'>+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0527</div><div class='add'>+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0528</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0529</div><div class='add'>+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x052a</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x052b</div><div class='add'>+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x052c</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052d</div><div class='add'>+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052e</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052f</div><div class='add'>+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2</div><div class='add'>+#define regVTG0_CONTROL                                                                                 0x0530</div><div class='add'>+#define regVTG0_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regVTG1_CONTROL                                                                                 0x0531</div><div class='add'>+#define regVTG1_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regVTG2_CONTROL                                                                                 0x0532</div><div class='add'>+#define regVTG2_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regVTG3_CONTROL                                                                                 0x0533</div><div class='add'>+#define regVTG3_CONTROL_BASE_IDX                                                                        2</div><div class='add'>+#define regDCHUBBUB_SOFT_RESET                                                                          0x0534</div><div class='add'>+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0535</div><div class='add'>+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDCFCLK_CNTL                                                                                  0x0536</div><div class='add'>+#define regDCFCLK_CNTL_BASE_IDX                                                                         2</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0537</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0538</div><div class='add'>+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2</div><div class='add'>+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0539</div><div class='add'>+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2</div><div class='add'>+#define regDCHUBBUB_CTRL_STATUS                                                                         0x053a</div><div class='add'>+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x0540</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x0541</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x0542</div><div class='add'>+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regFMON_CTRL                                                                                    0x0543</div><div class='add'>+#define regFMON_CTRL_BASE_IDX                                                                           2</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x0544</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x0545</div><div class='add'>+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_sdpif_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471</div><div class='add'>+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2</div><div class='add'>+#define regVM_REQUEST_PHYSICAL                                                                          0x0472</div><div class='add'>+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474</div><div class='add'>+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2</div><div class='add'>+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475</div><div class='add'>+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2</div><div class='add'>+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476</div><div class='add'>+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2</div><div class='add'>+#define regDCN_VM_FB_OFFSET                                                                             0x0477</div><div class='add'>+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2</div><div class='add'>+#define regDCN_VM_AGP_BOT                                                                               0x0478</div><div class='add'>+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2</div><div class='add'>+#define regDCN_VM_AGP_TOP                                                                               0x0479</div><div class='add'>+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2</div><div class='add'>+#define regDCN_VM_AGP_BASE                                                                              0x047a</div><div class='add'>+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d</div><div class='add'>+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x047e</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC                                                                  0x047f</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x0480</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL                                                          0x0481</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX                                                 2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL                                                            0x0482</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL_BASE_IDX                                                   2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL                                                            0x0483</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX                                                   2</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DATAFETCH                                                                0x0484</div><div class='add'>+#define regDCHUBBUB_SDPIF_PIPE_DATAFETCH_BASE_IDX                                                       2</div><div class='add'>+#define regSDPIF_REQUEST_RATE_LIMIT                                                                     0x0485</div><div class='add'>+#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX                                                            2</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0486</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0487</div><div class='add'>+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL                                                       0x0488</div><div class='add'>+#define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL_BASE_IDX                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_ret_path_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04af</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04b0</div><div class='add'>+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDCHUBBUB_CRC_CTRL                                                                            0x04b1</div><div class='add'>+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04b2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04b3</div><div class='add'>+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04b4</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04b5</div><div class='add'>+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04b6</div><div class='add'>+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT0                                                                           0x04b7</div><div class='add'>+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT1                                                                           0x04b8</div><div class='add'>+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DCC_STAT2                                                                           0x04b9</div><div class='add'>+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04ba</div><div class='add'>+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_DET0_CTRL                                                                           0x04bb</div><div class='add'>+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DET1_CTRL                                                                           0x04bc</div><div class='add'>+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DET2_CTRL                                                                           0x04bd</div><div class='add'>+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_DET3_CTRL                                                                           0x04be</div><div class='add'>+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2</div><div class='add'>+#define regDCHUBBUB_STAT                                                                                0x04bf</div><div class='add'>+#define regDCHUBBUB_STAT_BASE_IDX                                                                       2</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04c0</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04c1</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04c2</div><div class='add'>+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04c3</div><div class='add'>+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04c4</div><div class='add'>+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2</div><div class='add'>+#define regDCN_DECOMP_STATUS                                                                            0x04c5</div><div class='add'>+#define regDCN_DECOMP_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_0                                                                        0x04c6</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_1                                                                        0x04c7</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_1_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_2                                                                        0x04c8</div><div class='add'>+#define regDCHUBBUB_DEBUG_CTRL_2_BASE_IDX                                                               2</div><div class='add'>+#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX                                                           0x04c9</div><div class='add'>+#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_BASE_IDX                                                  2</div><div class='add'>+#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA                                                            0x04ca</div><div class='add'>+#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_vmrq_if_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559</div><div class='add'>+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f</div><div class='add'>+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560</div><div class='add'>+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566</div><div class='add'>+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567</div><div class='add'>+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d</div><div class='add'>+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e</div><div class='add'>+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574</div><div class='add'>+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575</div><div class='add'>+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b</div><div class='add'>+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c</div><div class='add'>+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582</div><div class='add'>+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583</div><div class='add'>+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589</div><div class='add'>+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a</div><div class='add'>+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590</div><div class='add'>+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591</div><div class='add'>+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597</div><div class='add'>+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598</div><div class='add'>+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e</div><div class='add'>+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2</div><div class='add'>+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f</div><div class='add'>+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5</div><div class='add'>+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6</div><div class='add'>+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac</div><div class='add'>+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad</div><div class='add'>+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3</div><div class='add'>+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4</div><div class='add'>+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba</div><div class='add'>+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb</div><div class='add'>+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1</div><div class='add'>+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2</div><div class='add'>+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8</div><div class='add'>+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca</div><div class='add'>+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2</div><div class='add'>+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb</div><div class='add'>+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc</div><div class='add'>+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce</div><div class='add'>+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5</div><div class='add'>+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6</div><div class='add'>+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7</div><div class='add'>+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE                                                0x05ea</div><div class='add'>+#define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX                                       2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05eb</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05ec</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ed</div><div class='add'>+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ee</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ef</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05f0</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f1</div><div class='add'>+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f2</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f3</div><div class='add'>+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f4</div><div class='add'>+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f5</div><div class='add'>+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f6</div><div class='add'>+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_CONFIG                                                                     0x05f7</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP0                                                                    0x05f8</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP1                                                                    0x05f9</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP2                                                                    0x05fa</div><div class='add'>+#define regHUBP0_DCHUBP_MALL_SUB_VP2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP0_DCHUBP_MCACHEID_CONFIG                                                                 0x05fb</div><div class='add'>+#define regHUBP0_DCHUBP_MCACHEID_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05fc</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05fd</div><div class='add'>+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP0_HUBP_DEBUG_CTRL                                                                        0x05fe</div><div class='add'>+#define regHUBP0_HUBP_DEBUG_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK                                                                  0x05ff</div><div class='add'>+#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK                                                                  0x0600</div><div class='add'>+#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0601</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0602</div><div class='add'>+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP0_HUBP_MALL_STATUS                                                                       0x0603</div><div class='add'>+#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609</div><div class='add'>+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d</div><div class='add'>+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611</div><div class='add'>+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x0612</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x0613</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x0614</div><div class='add'>+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0617</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0618</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0619</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x061a</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x061b</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x061c</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x061d</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x061e</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x061f</div><div class='add'>+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0620</div><div class='add'>+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x0621</div><div class='add'>+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x0622</div><div class='add'>+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x0623</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x0624</div><div class='add'>+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x0625</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x0626</div><div class='add'>+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0627</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0628</div><div class='add'>+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0629</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x062a</div><div class='add'>+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x062b</div><div class='add'>+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x062c</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x062d</div><div class='add'>+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x063a</div><div class='add'>+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x063b</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x063c</div><div class='add'>+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x063d</div><div class='add'>+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x063e</div><div class='add'>+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x063f</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0640</div><div class='add'>+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x0641</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x0642</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x0643</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x0644</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x0645</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x0646</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0647</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0648</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0649</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x064a</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x064b</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x064c</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x064d</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x064e</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x064f</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0650</div><div class='add'>+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x0651</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x0652</div><div class='add'>+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x0653</div><div class='add'>+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x0654</div><div class='add'>+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x0655</div><div class='add'>+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x0656</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0657</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x065a</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x065b</div><div class='add'>+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x065c</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x065d</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x065e</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x065f</div><div class='add'>+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_UCLK_PSTATE_FORCE                                                                   0x0660</div><div class='add'>+#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG0                                                                 0x0661</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG1                                                                 0x0662</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG2                                                                 0x0663</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG3                                                                 0x0664</div><div class='add'>+#define regHUBPREQ0_HUBPREQ_STATUS_REG3_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066d</div><div class='add'>+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066e</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066f</div><div class='add'>+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x0670</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0671</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0672</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0673</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0674</div><div class='add'>+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0675</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0676</div><div class='add'>+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0679</div><div class='add'>+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x067a</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067b</div><div class='add'>+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067c</div><div class='add'>+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067d</div><div class='add'>+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067e</div><div class='add'>+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067f</div><div class='add'>+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x0680</div><div class='add'>+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0681</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0682</div><div class='add'>+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0683</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0684</div><div class='add'>+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0685</div><div class='add'>+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0686</div><div class='add'>+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0687</div><div class='add'>+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0688</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0689</div><div class='add'>+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_CONTROL                                                                 0x068a</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW                                                             0x068b</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH                                                            0x068c</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX                                                   2</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM                                                               0x068d</div><div class='add'>+#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1</div><div class='add'>+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2</div><div class='add'>+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3</div><div class='add'>+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE                                                0x06c6</div><div class='add'>+#define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX                                       2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c7</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c8</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c9</div><div class='add'>+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06ca</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06cb</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cc</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cd</div><div class='add'>+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06ce</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06cf</div><div class='add'>+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP1_DCHUBP_CNTL                                                                            0x06d0</div><div class='add'>+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d1</div><div class='add'>+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d2</div><div class='add'>+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_CONFIG                                                                     0x06d3</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP0                                                                    0x06d4</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP1                                                                    0x06d5</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP2                                                                    0x06d6</div><div class='add'>+#define regHUBP1_DCHUBP_MALL_SUB_VP2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP1_DCHUBP_MCACHEID_CONFIG                                                                 0x06d7</div><div class='add'>+#define regHUBP1_DCHUBP_MCACHEID_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d8</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d9</div><div class='add'>+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP1_HUBP_DEBUG_CTRL                                                                        0x06da</div><div class='add'>+#define regHUBP1_HUBP_DEBUG_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK                                                                  0x06db</div><div class='add'>+#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK                                                                  0x06dc</div><div class='add'>+#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06dd</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06de</div><div class='add'>+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP1_HUBP_MALL_STATUS                                                                       0x06df</div><div class='add'>+#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5</div><div class='add'>+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9</div><div class='add'>+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed</div><div class='add'>+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06ee</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06ef</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f0</div><div class='add'>+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06f3</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06f4</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06f5</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06f6</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x06f7</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x06f8</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x06f9</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x06fa</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x06fb</div><div class='add'>+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x06fc</div><div class='add'>+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x06fd</div><div class='add'>+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x06fe</div><div class='add'>+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x06ff</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0700</div><div class='add'>+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x0701</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x0702</div><div class='add'>+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x0703</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x0704</div><div class='add'>+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x0705</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x0706</div><div class='add'>+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0707</div><div class='add'>+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0708</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0709</div><div class='add'>+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x0716</div><div class='add'>+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x0717</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0718</div><div class='add'>+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0719</div><div class='add'>+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x071a</div><div class='add'>+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x071b</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x071c</div><div class='add'>+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x071d</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x071e</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x071f</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0720</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x0721</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x0722</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x0723</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x0724</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x0725</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x0726</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0727</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0728</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0729</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x072a</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x072b</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x072c</div><div class='add'>+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x072d</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x072e</div><div class='add'>+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x072f</div><div class='add'>+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0730</div><div class='add'>+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x0731</div><div class='add'>+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x0732</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x0733</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x0736</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0737</div><div class='add'>+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0738</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0739</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x073a</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x073b</div><div class='add'>+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_UCLK_PSTATE_FORCE                                                                   0x073c</div><div class='add'>+#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG0                                                                 0x073d</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG1                                                                 0x073e</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG2                                                                 0x073f</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG3                                                                 0x0740</div><div class='add'>+#define regHUBPREQ1_HUBPREQ_STATUS_REG3_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0749</div><div class='add'>+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x074a</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074b</div><div class='add'>+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074c</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074d</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074e</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074f</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x0750</div><div class='add'>+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0751</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0752</div><div class='add'>+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0x370</div><div class='add'>+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0755</div><div class='add'>+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0756</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0757</div><div class='add'>+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0758</div><div class='add'>+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0759</div><div class='add'>+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x075a</div><div class='add'>+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075b</div><div class='add'>+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075c</div><div class='add'>+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075d</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075e</div><div class='add'>+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075f</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x0760</div><div class='add'>+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0761</div><div class='add'>+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0762</div><div class='add'>+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0763</div><div class='add'>+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0764</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0765</div><div class='add'>+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_CONTROL                                                                 0x0766</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW                                                             0x0767</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH                                                            0x0768</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX                                                   2</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM                                                               0x0769</div><div class='add'>+#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d</div><div class='add'>+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e</div><div class='add'>+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f</div><div class='add'>+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE                                                0x07a2</div><div class='add'>+#define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX                                       2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a3</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a4</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a5</div><div class='add'>+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a6</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a7</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a8</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a9</div><div class='add'>+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07aa</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07ab</div><div class='add'>+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ac</div><div class='add'>+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ad</div><div class='add'>+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ae</div><div class='add'>+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_CONFIG                                                                     0x07af</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP0                                                                    0x07b0</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP1                                                                    0x07b1</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP2                                                                    0x07b2</div><div class='add'>+#define regHUBP2_DCHUBP_MALL_SUB_VP2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP2_DCHUBP_MCACHEID_CONFIG                                                                 0x07b3</div><div class='add'>+#define regHUBP2_DCHUBP_MCACHEID_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07b4</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07b5</div><div class='add'>+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP2_HUBP_DEBUG_CTRL                                                                        0x07b6</div><div class='add'>+#define regHUBP2_HUBP_DEBUG_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK                                                                  0x07b7</div><div class='add'>+#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK                                                                  0x07b8</div><div class='add'>+#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b9</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07ba</div><div class='add'>+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP2_HUBP_MALL_STATUS                                                                       0x07bb</div><div class='add'>+#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1</div><div class='add'>+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5</div><div class='add'>+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9</div><div class='add'>+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07ca</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07cb</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07cc</div><div class='add'>+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07cf</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d0</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07d1</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07d2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07d3</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07d4</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07d5</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07d6</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07d7</div><div class='add'>+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07d8</div><div class='add'>+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07d9</div><div class='add'>+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07da</div><div class='add'>+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07db</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07dc</div><div class='add'>+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07dd</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07de</div><div class='add'>+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07df</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e0</div><div class='add'>+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07e1</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07e2</div><div class='add'>+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07e3</div><div class='add'>+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07e4</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07e5</div><div class='add'>+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07f2</div><div class='add'>+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07f3</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07f4</div><div class='add'>+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07f5</div><div class='add'>+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07f6</div><div class='add'>+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x07f7</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x07f8</div><div class='add'>+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x07f9</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x07fa</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x07fb</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x07fc</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x07fd</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x07fe</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x07ff</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0800</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x0801</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x0802</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x0803</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x0804</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x0805</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x0806</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0807</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0808</div><div class='add'>+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0809</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x080a</div><div class='add'>+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x080b</div><div class='add'>+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x080c</div><div class='add'>+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x080d</div><div class='add'>+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x080e</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x080f</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x0812</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x0813</div><div class='add'>+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x0814</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x0815</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x0816</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0817</div><div class='add'>+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_UCLK_PSTATE_FORCE                                                                   0x0818</div><div class='add'>+#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG0                                                                 0x0819</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG1                                                                 0x081a</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG2                                                                 0x081b</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG3                                                                 0x081c</div><div class='add'>+#define regHUBPREQ2_HUBPREQ_STATUS_REG3_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0825</div><div class='add'>+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0826</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0827</div><div class='add'>+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0828</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0829</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x082a</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082b</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082c</div><div class='add'>+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082d</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082e</div><div class='add'>+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0x6e0</div><div class='add'>+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0831</div><div class='add'>+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0832</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0833</div><div class='add'>+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0834</div><div class='add'>+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0835</div><div class='add'>+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0836</div><div class='add'>+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0837</div><div class='add'>+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0838</div><div class='add'>+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0839</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x083a</div><div class='add'>+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083b</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083c</div><div class='add'>+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083d</div><div class='add'>+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083e</div><div class='add'>+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083f</div><div class='add'>+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x0840</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0841</div><div class='add'>+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_CONTROL                                                                 0x0842</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW                                                             0x0843</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH                                                            0x0844</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX                                                   2</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM                                                               0x0845</div><div class='add'>+#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubp_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879</div><div class='add'>+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a</div><div class='add'>+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b</div><div class='add'>+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE                                                0x087e</div><div class='add'>+#define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX                                       2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087f</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x0880</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0881</div><div class='add'>+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0882</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0883</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0884</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0885</div><div class='add'>+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0886</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0887</div><div class='add'>+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2</div><div class='add'>+#define regHUBP3_DCHUBP_CNTL                                                                            0x0888</div><div class='add'>+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0889</div><div class='add'>+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x088a</div><div class='add'>+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_CONFIG                                                                     0x088b</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX                                                            2</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP0                                                                    0x088c</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP1                                                                    0x088d</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP2                                                                    0x088e</div><div class='add'>+#define regHUBP3_DCHUBP_MALL_SUB_VP2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBP3_DCHUBP_MCACHEID_CONFIG                                                                 0x088f</div><div class='add'>+#define regHUBP3_DCHUBP_MCACHEID_CONFIG_BASE_IDX                                                        2</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x0890</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x0891</div><div class='add'>+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2</div><div class='add'>+#define regHUBP3_HUBP_DEBUG_CTRL                                                                        0x0892</div><div class='add'>+#define regHUBP3_HUBP_DEBUG_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK                                                                  0x0893</div><div class='add'>+#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK                                                                  0x0894</div><div class='add'>+#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX                                                         2</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x0895</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0896</div><div class='add'>+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2</div><div class='add'>+#define regHUBP3_HUBP_MALL_STATUS                                                                       0x0897</div><div class='add'>+#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubpreq_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d</div><div class='add'>+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1</div><div class='add'>+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5</div><div class='add'>+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08a6</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08a7</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08a8</div><div class='add'>+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08ab</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08ac</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08ad</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08ae</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08af</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b0</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08b1</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08b2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08b3</div><div class='add'>+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2</div><div class='add'>+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08b4</div><div class='add'>+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08b5</div><div class='add'>+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08b6</div><div class='add'>+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08b7</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08b8</div><div class='add'>+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08b9</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08ba</div><div class='add'>+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08bb</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08bc</div><div class='add'>+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08bd</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08be</div><div class='add'>+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08bf</div><div class='add'>+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c0</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08c1</div><div class='add'>+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2</div><div class='add'>+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08ce</div><div class='add'>+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08cf</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d0</div><div class='add'>+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08d1</div><div class='add'>+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2</div><div class='add'>+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08d2</div><div class='add'>+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08d3</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08d4</div><div class='add'>+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08d5</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08d6</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08d7</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08d8</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08d9</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08da</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08db</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08dc</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08dd</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08de</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08df</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e0</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08e1</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08e2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08e3</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08e4</div><div class='add'>+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08e5</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08e6</div><div class='add'>+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08e7</div><div class='add'>+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08e8</div><div class='add'>+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08e9</div><div class='add'>+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08ea</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08eb</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08ee</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08ef</div><div class='add'>+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f0</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08f1</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08f2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08f3</div><div class='add'>+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_UCLK_PSTATE_FORCE                                                                   0x08f4</div><div class='add'>+#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG0                                                                 0x08f5</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG1                                                                 0x08f6</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG2                                                                 0x08f7</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX                                                        2</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG3                                                                 0x08f8</div><div class='add'>+#define regHUBPREQ3_HUBPREQ_STATUS_REG3_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubpret_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0901</div><div class='add'>+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0902</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0903</div><div class='add'>+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0904</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0905</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0906</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0907</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2</div><div class='add'>+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0908</div><div class='add'>+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0909</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x090a</div><div class='add'>+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_cursor0_dispdec</div><div class='add'>+// base address: 0xa50</div><div class='add'>+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090d</div><div class='add'>+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090e</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090f</div><div class='add'>+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2</div><div class='add'>+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x0910</div><div class='add'>+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0911</div><div class='add'>+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0912</div><div class='add'>+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0913</div><div class='add'>+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0914</div><div class='add'>+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0915</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0916</div><div class='add'>+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0917</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0918</div><div class='add'>+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0919</div><div class='add'>+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x091a</div><div class='add'>+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091b</div><div class='add'>+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091c</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091d</div><div class='add'>+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_CONTROL                                                                 0x091e</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW                                                             0x091f</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX                                                    2</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH                                                            0x0920</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX                                                   2</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM                                                               0x0921</div><div class='add'>+#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf</div><div class='add'>+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0</div><div class='add'>+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6</div><div class='add'>+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb</div><div class='add'>+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd</div><div class='add'>+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde</div><div class='add'>+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb</div><div class='add'>+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec</div><div class='add'>+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced</div><div class='add'>+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee</div><div class='add'>+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_cm_cur_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCM_CUR0_CURSOR0_CONTROL                                                                      0x0cf1</div><div class='add'>+#define regCM_CUR0_CURSOR0_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM_CUR0_CURSOR0_COLOR0                                                                       0x0cf2</div><div class='add'>+#define regCM_CUR0_CURSOR0_COLOR0_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR0_CURSOR0_COLOR1                                                                       0x0cf3</div><div class='add'>+#define regCM_CUR0_CURSOR0_COLOR1_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y                                                            0x0cf4</div><div class='add'>+#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX                                                   2</div><div class='add'>+#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB                                                        0x0cf5</div><div class='add'>+#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX                                               2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_MODE                                                                     0x0cf6</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_MODE_BASE_IDX                                                            2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C11_C12_A                                                                0x0cf7</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C11_C12_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C13_C14_A                                                                0x0cf8</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C13_C14_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C21_C22_A                                                                0x0cf9</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C21_C22_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C23_C24_A                                                                0x0cfa</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C23_C24_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C31_C32_A                                                                0x0cfb</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C31_C32_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C33_C34_A                                                                0x0cfc</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C33_C34_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C11_C12_B                                                                0x0cfd</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C11_C12_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C13_C14_B                                                                0x0cfe</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C13_C14_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C21_C22_B                                                                0x0cff</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C21_C22_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C23_C24_B                                                                0x0d00</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C23_C24_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C31_C32_B                                                                0x0d01</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C31_C32_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C33_C34_B                                                                0x0d02</div><div class='add'>+#define regCM_CUR0_CUR0_MATRIX_C33_C34_B_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0d06</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0d07</div><div class='add'>+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL0_SCL_MODE                                                                               0x0d08</div><div class='add'>+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0d09</div><div class='add'>+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL0_DSCL_CONTROL                                                                           0x0d0a</div><div class='add'>+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0d0b</div><div class='add'>+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0d0c</div><div class='add'>+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d0d</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d0e</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d0f</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d10</div><div class='add'>+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d11</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d12</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d13</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d14</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d15</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d16</div><div class='add'>+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d17</div><div class='add'>+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL0_DSCL_UPDATE                                                                            0x0d18</div><div class='add'>+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d19</div><div class='add'>+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d1a</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d1b</div><div class='add'>+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_OTG_H_BLANK                                                                            0x0d1c</div><div class='add'>+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_OTG_V_BLANK                                                                            0x0d1d</div><div class='add'>+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_RECOUT_START                                                                           0x0d1e</div><div class='add'>+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_RECOUT_SIZE                                                                            0x0d1f</div><div class='add'>+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_MPC_SIZE                                                                               0x0d20</div><div class='add'>+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d21</div><div class='add'>+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d22</div><div class='add'>+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL0_LB_V_COUNTER                                                                           0x0d23</div><div class='add'>+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d24</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d25</div><div class='add'>+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_OBUF_CONTROL                                                                           0x0d26</div><div class='add'>+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d27</div><div class='add'>+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_MODE                                                                       0x0d28</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_MODE                                                                       0x0d29</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL0_DSCL_SC_MODE                                                                           0x0d2a</div><div class='add'>+#define regDSCL0_DSCL_SC_MODE_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL0_DSCL_SC_MATRIX_C0C1                                                                    0x0d2b</div><div class='add'>+#define regDSCL0_DSCL_SC_MATRIX_C0C1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_DSCL_SC_MATRIX_C2C3                                                                    0x0d2c</div><div class='add'>+#define regDSCL0_DSCL_SC_MATRIX_C2C3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN                                                       0x0d2d</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE                                                     0x0d2e</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN                                                       0x0d2f</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE                                                     0x0d30</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1                                                         0x0d31</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX                                                2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2                                                         0x0d32</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX                                                2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3                                                         0x0d33</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX                                                2</div><div class='add'>+#define regDSCL0_DSCL_EASF_RINGEST_FORCE                                                                0x0d34</div><div class='add'>+#define regDSCL0_DSCL_EASF_RINGEST_FORCE_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF_CNTL                                                                    0x0d35</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN                                                           0x0d36</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF_CNTL                                                                    0x0d37</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN                                                           0x0d38</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0                                                               0x0d39</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1                                                               0x0d3a</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2                                                               0x0d3b</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3                                                               0x0d3c</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4                                                               0x0d3d</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5                                                               0x0d3e</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6                                                               0x0d3f</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7                                                               0x0d40</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0                                                               0x0d41</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1                                                               0x0d42</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2                                                               0x0d43</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3                                                               0x0d44</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4                                                               0x0d45</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5                                                               0x0d46</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6                                                               0x0d47</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7                                                               0x0d48</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0                                                               0x0d49</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1                                                               0x0d4a</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2                                                               0x0d4b</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3                                                               0x0d4c</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4                                                               0x0d4d</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5                                                               0x0d4e</div><div class='add'>+#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0                                                               0x0d4f</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1                                                               0x0d50</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2                                                               0x0d51</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3                                                               0x0d52</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4                                                               0x0d53</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5                                                               0x0d54</div><div class='add'>+#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_ISHARP_MODE                                                                            0x0d55</div><div class='add'>+#define regDSCL0_ISHARP_MODE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_CTRL                                                                      0x0d56</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_INDEX                                                                     0x0d57</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_INDEX_BASE_IDX                                                            2</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_DATA                                                                      0x0d58</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_DATA_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP                                                               0x0d59</div><div class='add'>+#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL0_ISHARP_NOISEDET_THRESHOLD                                                              0x0d5a</div><div class='add'>+#define regDSCL0_ISHARP_NOISEDET_THRESHOLD_BASE_IDX                                                     2</div><div class='add'>+#define regDSCL0_ISHARP_NOISE_GAIN_PWL                                                                  0x0d5b</div><div class='add'>+#define regDSCL0_ISHARP_NOISE_GAIN_PWL_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG0                                                                    0x0d5c</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG1                                                                    0x0d5d</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG2                                                                    0x0d5e</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG2_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG3                                                                    0x0d5f</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG4                                                                    0x0d60</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG4_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG5                                                                    0x0d61</div><div class='add'>+#define regDSCL0_ISHARP_LBA_PWL_SEG5_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL                                                          0x0d62</div><div class='add'>+#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_cm_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regCM0_CM_CONTROL                                                                               0x0d67</div><div class='add'>+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d68</div><div class='add'>+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d69</div><div class='add'>+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d6a</div><div class='add'>+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d6b</div><div class='add'>+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d6c</div><div class='add'>+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d6d</div><div class='add'>+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d6e</div><div class='add'>+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d6f</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d70</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d71</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d72</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d73</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d74</div><div class='add'>+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_BIAS_CR_R                                                                             0x0d75</div><div class='add'>+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d76</div><div class='add'>+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d77</div><div class='add'>+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d78</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d79</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d7a</div><div class='add'>+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d7b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d7c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d7d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d7e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d7f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d80</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d81</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d82</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d83</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d84</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d85</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d86</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d87</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d88</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d89</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d8a</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d8b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d8c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d8d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d8e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d8f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d90</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d91</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d92</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d93</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d94</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d95</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d96</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d97</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d98</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d99</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d9a</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d9b</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d9c</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d9d</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d9e</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d9f</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0da0</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0da1</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0da2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0da3</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0da4</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0da5</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0da6</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0da7</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0da8</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0da9</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0daa</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0dab</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0dac</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0dad</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0dae</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0daf</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0db0</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0db1</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0db2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0db3</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0db4</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0db5</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0db6</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0db7</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0db8</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0db9</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0dba</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0dbb</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0dbc</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0dbd</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0dbe</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0dbf</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0dc0</div><div class='add'>+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0dc1</div><div class='add'>+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0dc2</div><div class='add'>+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0dc3</div><div class='add'>+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM0_CM_DEALPHA                                                                               0x0dc5</div><div class='add'>+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM0_CM_COEF_FORMAT                                                                           0x0dc6</div><div class='add'>+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0dc7</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0dc8</div><div class='add'>+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5</div><div class='add'>+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6</div><div class='add'>+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9</div><div class='add'>+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca</div><div class='add'>+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a</div><div class='add'>+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b</div><div class='add'>+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41</div><div class='add'>+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46</div><div class='add'>+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48</div><div class='add'>+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49</div><div class='add'>+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56</div><div class='add'>+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57</div><div class='add'>+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58</div><div class='add'>+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59</div><div class='add'>+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_cm_cur_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regCM_CUR1_CURSOR0_CONTROL                                                                      0x0e5c</div><div class='add'>+#define regCM_CUR1_CURSOR0_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM_CUR1_CURSOR0_COLOR0                                                                       0x0e5d</div><div class='add'>+#define regCM_CUR1_CURSOR0_COLOR0_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR1_CURSOR0_COLOR1                                                                       0x0e5e</div><div class='add'>+#define regCM_CUR1_CURSOR0_COLOR1_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y                                                            0x0e5f</div><div class='add'>+#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX                                                   2</div><div class='add'>+#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB                                                        0x0e60</div><div class='add'>+#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX                                               2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_MODE                                                                     0x0e61</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_MODE_BASE_IDX                                                            2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C11_C12_A                                                                0x0e62</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C11_C12_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C13_C14_A                                                                0x0e63</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C13_C14_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C21_C22_A                                                                0x0e64</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C21_C22_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C23_C24_A                                                                0x0e65</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C23_C24_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C31_C32_A                                                                0x0e66</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C31_C32_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C33_C34_A                                                                0x0e67</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C33_C34_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C11_C12_B                                                                0x0e68</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C11_C12_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C13_C14_B                                                                0x0e69</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C13_C14_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C21_C22_B                                                                0x0e6a</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C21_C22_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C23_C24_B                                                                0x0e6b</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C23_C24_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C31_C32_B                                                                0x0e6c</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C31_C32_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C33_C34_B                                                                0x0e6d</div><div class='add'>+#define regCM_CUR1_CUR0_MATRIX_C33_C34_B_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e71</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e72</div><div class='add'>+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL1_SCL_MODE                                                                               0x0e73</div><div class='add'>+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e74</div><div class='add'>+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL1_DSCL_CONTROL                                                                           0x0e75</div><div class='add'>+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e76</div><div class='add'>+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e77</div><div class='add'>+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e78</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e79</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e7a</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e7b</div><div class='add'>+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e7c</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e7d</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e7e</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e7f</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e80</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e81</div><div class='add'>+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e82</div><div class='add'>+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL1_DSCL_UPDATE                                                                            0x0e83</div><div class='add'>+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e84</div><div class='add'>+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e85</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e86</div><div class='add'>+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_OTG_H_BLANK                                                                            0x0e87</div><div class='add'>+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_OTG_V_BLANK                                                                            0x0e88</div><div class='add'>+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_RECOUT_START                                                                           0x0e89</div><div class='add'>+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_RECOUT_SIZE                                                                            0x0e8a</div><div class='add'>+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_MPC_SIZE                                                                               0x0e8b</div><div class='add'>+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e8c</div><div class='add'>+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e8d</div><div class='add'>+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL1_LB_V_COUNTER                                                                           0x0e8e</div><div class='add'>+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e8f</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e90</div><div class='add'>+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_OBUF_CONTROL                                                                           0x0e91</div><div class='add'>+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e92</div><div class='add'>+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_MODE                                                                       0x0e93</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_MODE                                                                       0x0e94</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL1_DSCL_SC_MODE                                                                           0x0e95</div><div class='add'>+#define regDSCL1_DSCL_SC_MODE_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL1_DSCL_SC_MATRIX_C0C1                                                                    0x0e96</div><div class='add'>+#define regDSCL1_DSCL_SC_MATRIX_C0C1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_DSCL_SC_MATRIX_C2C3                                                                    0x0e97</div><div class='add'>+#define regDSCL1_DSCL_SC_MATRIX_C2C3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN                                                       0x0e98</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE                                                     0x0e99</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN                                                       0x0e9a</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE                                                     0x0e9b</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1                                                         0x0e9c</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX                                                2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2                                                         0x0e9d</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX                                                2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3                                                         0x0e9e</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX                                                2</div><div class='add'>+#define regDSCL1_DSCL_EASF_RINGEST_FORCE                                                                0x0e9f</div><div class='add'>+#define regDSCL1_DSCL_EASF_RINGEST_FORCE_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF_CNTL                                                                    0x0ea0</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN                                                           0x0ea1</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF_CNTL                                                                    0x0ea2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN                                                           0x0ea3</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0                                                               0x0ea4</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1                                                               0x0ea5</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2                                                               0x0ea6</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3                                                               0x0ea7</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4                                                               0x0ea8</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5                                                               0x0ea9</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6                                                               0x0eaa</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7                                                               0x0eab</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0                                                               0x0eac</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1                                                               0x0ead</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2                                                               0x0eae</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3                                                               0x0eaf</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4                                                               0x0eb0</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5                                                               0x0eb1</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6                                                               0x0eb2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7                                                               0x0eb3</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0                                                               0x0eb4</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1                                                               0x0eb5</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2                                                               0x0eb6</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3                                                               0x0eb7</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4                                                               0x0eb8</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5                                                               0x0eb9</div><div class='add'>+#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0                                                               0x0eba</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1                                                               0x0ebb</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2                                                               0x0ebc</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3                                                               0x0ebd</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4                                                               0x0ebe</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5                                                               0x0ebf</div><div class='add'>+#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_ISHARP_MODE                                                                            0x0ec0</div><div class='add'>+#define regDSCL1_ISHARP_MODE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_CTRL                                                                      0x0ec1</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_INDEX                                                                     0x0ec2</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_INDEX_BASE_IDX                                                            2</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_DATA                                                                      0x0ec3</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_DATA_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP                                                               0x0ec4</div><div class='add'>+#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL1_ISHARP_NOISEDET_THRESHOLD                                                              0x0ec5</div><div class='add'>+#define regDSCL1_ISHARP_NOISEDET_THRESHOLD_BASE_IDX                                                     2</div><div class='add'>+#define regDSCL1_ISHARP_NOISE_GAIN_PWL                                                                  0x0ec6</div><div class='add'>+#define regDSCL1_ISHARP_NOISE_GAIN_PWL_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG0                                                                    0x0ec7</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG1                                                                    0x0ec8</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG2                                                                    0x0ec9</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG2_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG3                                                                    0x0eca</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG4                                                                    0x0ecb</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG4_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG5                                                                    0x0ecc</div><div class='add'>+#define regDSCL1_ISHARP_LBA_PWL_SEG5_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL                                                          0x0ecd</div><div class='add'>+#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_cm_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regCM1_CM_CONTROL                                                                               0x0ed2</div><div class='add'>+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0ed3</div><div class='add'>+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0ed4</div><div class='add'>+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0ed5</div><div class='add'>+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0ed6</div><div class='add'>+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0ed7</div><div class='add'>+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0ed8</div><div class='add'>+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0ed9</div><div class='add'>+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0eda</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0edb</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0edc</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0edd</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0ede</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0edf</div><div class='add'>+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_BIAS_CR_R                                                                             0x0ee0</div><div class='add'>+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ee1</div><div class='add'>+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ee2</div><div class='add'>+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ee3</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0ee4</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0ee5</div><div class='add'>+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0ee6</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ee7</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0ee8</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0ee9</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eea</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eeb</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eec</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eed</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eee</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eef</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0ef0</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0ef1</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0ef2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0ef3</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0ef4</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ef5</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ef6</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ef7</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ef8</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ef9</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0efa</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0efb</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0efc</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0efd</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0efe</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0eff</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0f00</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0f01</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0f02</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0f03</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0f04</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0f05</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0f06</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0f07</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0f08</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0f09</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0f0a</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0f0b</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0f0c</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0f0d</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0f0e</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0f0f</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0f10</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0f11</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0f12</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0f13</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0f14</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0f15</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0f16</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0f17</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0f18</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0f19</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0f1a</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0f1b</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0f1c</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0f1d</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0f1e</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0f1f</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0f20</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0f21</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0f22</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0f23</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0f24</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0f25</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0f26</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0f27</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0f28</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0f29</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0f2a</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0f2b</div><div class='add'>+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0f2c</div><div class='add'>+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0f2d</div><div class='add'>+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0f2e</div><div class='add'>+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM1_CM_DEALPHA                                                                               0x0f30</div><div class='add'>+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM1_CM_COEF_FORMAT                                                                           0x0f31</div><div class='add'>+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f32</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0f33</div><div class='add'>+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0x5ac</div><div class='add'>+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30</div><div class='add'>+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31</div><div class='add'>+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34</div><div class='add'>+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35</div><div class='add'>+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5</div><div class='add'>+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6</div><div class='add'>+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac</div><div class='add'>+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1</div><div class='add'>+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3</div><div class='add'>+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4</div><div class='add'>+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1</div><div class='add'>+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2</div><div class='add'>+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3</div><div class='add'>+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4</div><div class='add'>+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_cm_cur_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regCM_CUR2_CURSOR0_CONTROL                                                                      0x0fc7</div><div class='add'>+#define regCM_CUR2_CURSOR0_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM_CUR2_CURSOR0_COLOR0                                                                       0x0fc8</div><div class='add'>+#define regCM_CUR2_CURSOR0_COLOR0_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR2_CURSOR0_COLOR1                                                                       0x0fc9</div><div class='add'>+#define regCM_CUR2_CURSOR0_COLOR1_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y                                                            0x0fca</div><div class='add'>+#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX                                                   2</div><div class='add'>+#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB                                                        0x0fcb</div><div class='add'>+#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX                                               2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_MODE                                                                     0x0fcc</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_MODE_BASE_IDX                                                            2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C11_C12_A                                                                0x0fcd</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C11_C12_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C13_C14_A                                                                0x0fce</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C13_C14_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C21_C22_A                                                                0x0fcf</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C21_C22_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C23_C24_A                                                                0x0fd0</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C23_C24_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C31_C32_A                                                                0x0fd1</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C31_C32_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C33_C34_A                                                                0x0fd2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C33_C34_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C11_C12_B                                                                0x0fd3</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C11_C12_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C13_C14_B                                                                0x0fd4</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C13_C14_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C21_C22_B                                                                0x0fd5</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C21_C22_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C23_C24_B                                                                0x0fd6</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C23_C24_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C31_C32_B                                                                0x0fd7</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C31_C32_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C33_C34_B                                                                0x0fd8</div><div class='add'>+#define regCM_CUR2_CUR0_MATRIX_C33_C34_B_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fdc</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fdd</div><div class='add'>+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL2_SCL_MODE                                                                               0x0fde</div><div class='add'>+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fdf</div><div class='add'>+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL2_DSCL_CONTROL                                                                           0x0fe0</div><div class='add'>+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fe1</div><div class='add'>+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fe2</div><div class='add'>+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fe3</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fe4</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fe5</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fe6</div><div class='add'>+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fe7</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fe8</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fe9</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fea</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0feb</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fec</div><div class='add'>+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fed</div><div class='add'>+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL2_DSCL_UPDATE                                                                            0x0fee</div><div class='add'>+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fef</div><div class='add'>+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0ff0</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0ff1</div><div class='add'>+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_OTG_H_BLANK                                                                            0x0ff2</div><div class='add'>+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_OTG_V_BLANK                                                                            0x0ff3</div><div class='add'>+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_RECOUT_START                                                                           0x0ff4</div><div class='add'>+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_RECOUT_SIZE                                                                            0x0ff5</div><div class='add'>+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_MPC_SIZE                                                                               0x0ff6</div><div class='add'>+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0ff7</div><div class='add'>+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0ff8</div><div class='add'>+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL2_LB_V_COUNTER                                                                           0x0ff9</div><div class='add'>+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0ffa</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0ffb</div><div class='add'>+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_OBUF_CONTROL                                                                           0x0ffc</div><div class='add'>+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ffd</div><div class='add'>+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_MODE                                                                       0x0ffe</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_MODE                                                                       0x0fff</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL2_DSCL_SC_MODE                                                                           0x1000</div><div class='add'>+#define regDSCL2_DSCL_SC_MODE_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL2_DSCL_SC_MATRIX_C0C1                                                                    0x1001</div><div class='add'>+#define regDSCL2_DSCL_SC_MATRIX_C0C1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_DSCL_SC_MATRIX_C2C3                                                                    0x1002</div><div class='add'>+#define regDSCL2_DSCL_SC_MATRIX_C2C3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN                                                       0x1003</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE                                                     0x1004</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN                                                       0x1005</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE                                                     0x1006</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1                                                         0x1007</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX                                                2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2                                                         0x1008</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX                                                2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3                                                         0x1009</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX                                                2</div><div class='add'>+#define regDSCL2_DSCL_EASF_RINGEST_FORCE                                                                0x100a</div><div class='add'>+#define regDSCL2_DSCL_EASF_RINGEST_FORCE_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF_CNTL                                                                    0x100b</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN                                                           0x100c</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF_CNTL                                                                    0x100d</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN                                                           0x100e</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0                                                               0x100f</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1                                                               0x1010</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2                                                               0x1011</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3                                                               0x1012</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4                                                               0x1013</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5                                                               0x1014</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6                                                               0x1015</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7                                                               0x1016</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0                                                               0x1017</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1                                                               0x1018</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2                                                               0x1019</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3                                                               0x101a</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4                                                               0x101b</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5                                                               0x101c</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6                                                               0x101d</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7                                                               0x101e</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0                                                               0x101f</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1                                                               0x1020</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2                                                               0x1021</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3                                                               0x1022</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4                                                               0x1023</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5                                                               0x1024</div><div class='add'>+#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0                                                               0x1025</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1                                                               0x1026</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2                                                               0x1027</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3                                                               0x1028</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4                                                               0x1029</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5                                                               0x102a</div><div class='add'>+#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_ISHARP_MODE                                                                            0x102b</div><div class='add'>+#define regDSCL2_ISHARP_MODE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_CTRL                                                                      0x102c</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_INDEX                                                                     0x102d</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_INDEX_BASE_IDX                                                            2</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_DATA                                                                      0x102e</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_DATA_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP                                                               0x102f</div><div class='add'>+#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL2_ISHARP_NOISEDET_THRESHOLD                                                              0x1030</div><div class='add'>+#define regDSCL2_ISHARP_NOISEDET_THRESHOLD_BASE_IDX                                                     2</div><div class='add'>+#define regDSCL2_ISHARP_NOISE_GAIN_PWL                                                                  0x1031</div><div class='add'>+#define regDSCL2_ISHARP_NOISE_GAIN_PWL_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG0                                                                    0x1032</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG1                                                                    0x1033</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG2                                                                    0x1034</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG2_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG3                                                                    0x1035</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG4                                                                    0x1036</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG4_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG5                                                                    0x1037</div><div class='add'>+#define regDSCL2_ISHARP_LBA_PWL_SEG5_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL                                                          0x1038</div><div class='add'>+#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_cm_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regCM2_CM_CONTROL                                                                               0x103d</div><div class='add'>+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x103e</div><div class='add'>+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x103f</div><div class='add'>+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x1040</div><div class='add'>+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x1041</div><div class='add'>+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x1042</div><div class='add'>+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x1043</div><div class='add'>+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x1044</div><div class='add'>+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x1045</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x1046</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1047</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1048</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1049</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x104a</div><div class='add'>+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_BIAS_CR_R                                                                             0x104b</div><div class='add'>+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x104c</div><div class='add'>+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x104d</div><div class='add'>+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x104e</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x104f</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1050</div><div class='add'>+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1051</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1052</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1053</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1054</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1055</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1056</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1057</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1058</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x1059</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x105a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x105b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x105c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x105d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x105e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x105f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1060</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1061</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1062</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1063</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1064</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1065</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1066</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1067</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1068</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x1069</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x106a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x106b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x106c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x106d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x106e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x106f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1070</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1071</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1072</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1073</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x1074</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x1075</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x1076</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x1077</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x1078</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x1079</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x107a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x107b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x107c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x107d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x107e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x107f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1080</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1081</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1082</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1083</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x1084</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x1085</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x1086</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x1087</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x1088</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x1089</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x108a</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x108b</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x108c</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x108d</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x108e</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x108f</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1090</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1091</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1092</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1093</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x1094</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x1095</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x1096</div><div class='add'>+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM2_CM_HDR_MULT_COEF                                                                         0x1097</div><div class='add'>+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x1098</div><div class='add'>+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x1099</div><div class='add'>+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM2_CM_DEALPHA                                                                               0x109b</div><div class='add'>+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM2_CM_COEF_FORMAT                                                                           0x109c</div><div class='add'>+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x109d</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x109e</div><div class='add'>+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0xb58</div><div class='add'>+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b</div><div class='add'>+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c</div><div class='add'>+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f</div><div class='add'>+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0</div><div class='add'>+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_cnvc_cfg_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110</div><div class='add'>+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2</div><div class='add'>+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111</div><div class='add'>+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117</div><div class='add'>+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c</div><div class='add'>+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e</div><div class='add'>+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2</div><div class='add'>+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f</div><div class='add'>+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c</div><div class='add'>+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2</div><div class='add'>+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d</div><div class='add'>+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2</div><div class='add'>+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e</div><div class='add'>+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2</div><div class='add'>+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f</div><div class='add'>+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_cm_cur_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regCM_CUR3_CURSOR0_CONTROL                                                                      0x1132</div><div class='add'>+#define regCM_CUR3_CURSOR0_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM_CUR3_CURSOR0_COLOR0                                                                       0x1133</div><div class='add'>+#define regCM_CUR3_CURSOR0_COLOR0_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR3_CURSOR0_COLOR1                                                                       0x1134</div><div class='add'>+#define regCM_CUR3_CURSOR0_COLOR1_BASE_IDX                                                              2</div><div class='add'>+#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y                                                            0x1135</div><div class='add'>+#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX                                                   2</div><div class='add'>+#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB                                                        0x1136</div><div class='add'>+#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX                                               2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_MODE                                                                     0x1137</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_MODE_BASE_IDX                                                            2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C11_C12_A                                                                0x1138</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C11_C12_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C13_C14_A                                                                0x1139</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C13_C14_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C21_C22_A                                                                0x113a</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C21_C22_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C23_C24_A                                                                0x113b</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C23_C24_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C31_C32_A                                                                0x113c</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C31_C32_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C33_C34_A                                                                0x113d</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C33_C34_A_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C11_C12_B                                                                0x113e</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C11_C12_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C13_C14_B                                                                0x113f</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C13_C14_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C21_C22_B                                                                0x1140</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C21_C22_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C23_C24_B                                                                0x1141</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C23_C24_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C31_C32_B                                                                0x1142</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C31_C32_B_BASE_IDX                                                       2</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C33_C34_B                                                                0x1143</div><div class='add'>+#define regCM_CUR3_CUR0_MATRIX_C33_C34_B_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_dscl_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x1147</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x1148</div><div class='add'>+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL3_SCL_MODE                                                                               0x1149</div><div class='add'>+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x114a</div><div class='add'>+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL3_DSCL_CONTROL                                                                           0x114b</div><div class='add'>+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x114c</div><div class='add'>+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x114d</div><div class='add'>+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x114e</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x114f</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1150</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1151</div><div class='add'>+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1152</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1153</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1154</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1155</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1156</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x1157</div><div class='add'>+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2</div><div class='add'>+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x1158</div><div class='add'>+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2</div><div class='add'>+#define regDSCL3_DSCL_UPDATE                                                                            0x1159</div><div class='add'>+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_DSCL_AUTOCAL                                                                           0x115a</div><div class='add'>+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x115b</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x115c</div><div class='add'>+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_OTG_H_BLANK                                                                            0x115d</div><div class='add'>+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_OTG_V_BLANK                                                                            0x115e</div><div class='add'>+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_RECOUT_START                                                                           0x115f</div><div class='add'>+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_RECOUT_SIZE                                                                            0x1160</div><div class='add'>+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_MPC_SIZE                                                                               0x1161</div><div class='add'>+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2</div><div class='add'>+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1162</div><div class='add'>+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1163</div><div class='add'>+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2</div><div class='add'>+#define regDSCL3_LB_V_COUNTER                                                                           0x1164</div><div class='add'>+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1165</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1166</div><div class='add'>+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_OBUF_CONTROL                                                                           0x1167</div><div class='add'>+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x1168</div><div class='add'>+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_MODE                                                                       0x1169</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_MODE                                                                       0x116a</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_MODE_BASE_IDX                                                              2</div><div class='add'>+#define regDSCL3_DSCL_SC_MODE                                                                           0x116b</div><div class='add'>+#define regDSCL3_DSCL_SC_MODE_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCL3_DSCL_SC_MATRIX_C0C1                                                                    0x116c</div><div class='add'>+#define regDSCL3_DSCL_SC_MATRIX_C0C1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_DSCL_SC_MATRIX_C2C3                                                                    0x116d</div><div class='add'>+#define regDSCL3_DSCL_SC_MATRIX_C2C3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN                                                       0x116e</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE                                                     0x116f</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN                                                       0x1170</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX                                              2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE                                                     0x1171</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX                                            2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1                                                         0x1172</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX                                                2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2                                                         0x1173</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX                                                2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3                                                         0x1174</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX                                                2</div><div class='add'>+#define regDSCL3_DSCL_EASF_RINGEST_FORCE                                                                0x1175</div><div class='add'>+#define regDSCL3_DSCL_EASF_RINGEST_FORCE_BASE_IDX                                                       2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF_CNTL                                                                    0x1176</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN                                                           0x1177</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF_CNTL                                                                    0x1178</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN                                                           0x1179</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX                                                  2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0                                                               0x117a</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1                                                               0x117b</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2                                                               0x117c</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3                                                               0x117d</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4                                                               0x117e</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5                                                               0x117f</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6                                                               0x1180</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7                                                               0x1181</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0                                                               0x1182</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1                                                               0x1183</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2                                                               0x1184</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3                                                               0x1185</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4                                                               0x1186</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5                                                               0x1187</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6                                                               0x1188</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7                                                               0x1189</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0                                                               0x118a</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1                                                               0x118b</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2                                                               0x118c</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3                                                               0x118d</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4                                                               0x118e</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5                                                               0x118f</div><div class='add'>+#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0                                                               0x1190</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1                                                               0x1191</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2                                                               0x1192</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3                                                               0x1193</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4                                                               0x1194</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5                                                               0x1195</div><div class='add'>+#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_ISHARP_MODE                                                                            0x1196</div><div class='add'>+#define regDSCL3_ISHARP_MODE_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_CTRL                                                                      0x1197</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_INDEX                                                                     0x1198</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_INDEX_BASE_IDX                                                            2</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_DATA                                                                      0x1199</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_DATA_BASE_IDX                                                             2</div><div class='add'>+#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP                                                               0x119a</div><div class='add'>+#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX                                                      2</div><div class='add'>+#define regDSCL3_ISHARP_NOISEDET_THRESHOLD                                                              0x119b</div><div class='add'>+#define regDSCL3_ISHARP_NOISEDET_THRESHOLD_BASE_IDX                                                     2</div><div class='add'>+#define regDSCL3_ISHARP_NOISE_GAIN_PWL                                                                  0x119c</div><div class='add'>+#define regDSCL3_ISHARP_NOISE_GAIN_PWL_BASE_IDX                                                         2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG0                                                                    0x119d</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG1                                                                    0x119e</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG2                                                                    0x119f</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG2_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG3                                                                    0x11a0</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG3_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG4                                                                    0x11a1</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG4_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG5                                                                    0x11a2</div><div class='add'>+#define regDSCL3_ISHARP_LBA_PWL_SEG5_BASE_IDX                                                           2</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL                                                          0x11a3</div><div class='add'>+#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_cm_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regCM3_CM_CONTROL                                                                               0x11a8</div><div class='add'>+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x11a9</div><div class='add'>+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x11aa</div><div class='add'>+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x11ab</div><div class='add'>+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x11ac</div><div class='add'>+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x11ad</div><div class='add'>+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x11ae</div><div class='add'>+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x11af</div><div class='add'>+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x11b0</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x11b1</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x11b2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x11b3</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x11b4</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x11b5</div><div class='add'>+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_BIAS_CR_R                                                                             0x11b6</div><div class='add'>+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2</div><div class='add'>+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x11b7</div><div class='add'>+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x11b8</div><div class='add'>+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x11b9</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x11ba</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x11bb</div><div class='add'>+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x11bc</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x11bd</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x11be</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x11bf</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x11c0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x11c1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x11c2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x11c3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x11c4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x11c5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x11c6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x11c7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x11c8</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x11c9</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x11ca</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x11cb</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x11cc</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x11cd</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x11ce</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x11cf</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x11d0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x11d1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x11d2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x11d3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x11d4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x11d5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x11d6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x11d7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x11d8</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x11d9</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11da</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11db</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11dc</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11dd</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11de</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11df</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11e0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11e1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11e2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11e3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11e4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11e5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11e6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11e7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11e8</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11e9</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11ea</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11eb</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11ec</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11ed</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11ee</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11ef</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11f0</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11f1</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11f2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11f3</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11f4</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11f5</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11f6</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11f7</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11f8</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11f9</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11fa</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11fb</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11fc</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11fd</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11fe</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11ff</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x1200</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x1201</div><div class='add'>+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2</div><div class='add'>+#define regCM3_CM_HDR_MULT_COEF                                                                         0x1202</div><div class='add'>+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2</div><div class='add'>+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x1203</div><div class='add'>+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x1204</div><div class='add'>+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regCM3_CM_DEALPHA                                                                               0x1206</div><div class='add'>+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2</div><div class='add'>+#define regCM3_CM_COEF_FORMAT                                                                           0x1207</div><div class='add'>+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x1208</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x1209</div><div class='add'>+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_dpp_top_dispdec</div><div class='add'>+// base address: 0x1104</div><div class='add'>+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106</div><div class='add'>+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107</div><div class='add'>+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a</div><div class='add'>+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2</div><div class='add'>+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b</div><div class='add'>+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000</div><div class='add'>+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001</div><div class='add'>+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002</div><div class='add'>+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC0_MPCC_CONTROL                                                                           0x0003</div><div class='add'>+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004</div><div class='add'>+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005</div><div class='add'>+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006</div><div class='add'>+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008</div><div class='add'>+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0009</div><div class='add'>+#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC0_MPCC_BG_R_CR                                                                           0x000a</div><div class='add'>+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000b</div><div class='add'>+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000c</div><div class='add'>+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000d</div><div class='add'>+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC0_MPCC_STATUS                                                                            0x000e</div><div class='add'>+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc1_dispdec</div><div class='add'>+// base address: 0x54</div><div class='add'>+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0015</div><div class='add'>+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0016</div><div class='add'>+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_OPP_ID                                                                            0x0017</div><div class='add'>+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC1_MPCC_CONTROL                                                                           0x0018</div><div class='add'>+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0019</div><div class='add'>+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x001a</div><div class='add'>+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x001b</div><div class='add'>+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x001c</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x001d</div><div class='add'>+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x001e</div><div class='add'>+#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC1_MPCC_BG_R_CR                                                                           0x001f</div><div class='add'>+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_BG_G_Y                                                                            0x0020</div><div class='add'>+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC1_MPCC_BG_B_CB                                                                           0x0021</div><div class='add'>+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x0022</div><div class='add'>+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC1_MPCC_STATUS                                                                            0x0023</div><div class='add'>+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc2_dispdec</div><div class='add'>+// base address: 0xa8</div><div class='add'>+#define regMPCC2_MPCC_TOP_SEL                                                                           0x002a</div><div class='add'>+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_BOT_SEL                                                                           0x002b</div><div class='add'>+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_OPP_ID                                                                            0x002c</div><div class='add'>+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC2_MPCC_CONTROL                                                                           0x002d</div><div class='add'>+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x002e</div><div class='add'>+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x002f</div><div class='add'>+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0030</div><div class='add'>+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0031</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0032</div><div class='add'>+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0033</div><div class='add'>+#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0034</div><div class='add'>+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_BG_G_Y                                                                            0x0035</div><div class='add'>+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC2_MPCC_BG_B_CB                                                                           0x0036</div><div class='add'>+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x0037</div><div class='add'>+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC2_MPCC_STATUS                                                                            0x0038</div><div class='add'>+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc3_dispdec</div><div class='add'>+// base address: 0xfc</div><div class='add'>+#define regMPCC3_MPCC_TOP_SEL                                                                           0x003f</div><div class='add'>+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0040</div><div class='add'>+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_OPP_ID                                                                            0x0041</div><div class='add'>+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC3_MPCC_CONTROL                                                                           0x0042</div><div class='add'>+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0043</div><div class='add'>+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0044</div><div class='add'>+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0045</div><div class='add'>+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0046</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0047</div><div class='add'>+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3</div><div class='add'>+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL                                                       0x0048</div><div class='add'>+#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX                                              3</div><div class='add'>+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0049</div><div class='add'>+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_BG_G_Y                                                                            0x004a</div><div class='add'>+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3</div><div class='add'>+#define regMPCC3_MPCC_BG_B_CB                                                                           0x004b</div><div class='add'>+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3</div><div class='add'>+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x004c</div><div class='add'>+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3</div><div class='add'>+#define regMPCC3_MPCC_STATUS                                                                            0x004d</div><div class='add'>+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpc_cfg_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPC_CLOCK_CONTROL                                                                            0x02b2</div><div class='add'>+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_SOFT_RESET                                                                               0x02b3</div><div class='add'>+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3</div><div class='add'>+#define regMPC_CRC_CTRL                                                                                 0x02b4</div><div class='add'>+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_CRC_SEL_CONTROL                                                                          0x02b5</div><div class='add'>+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3</div><div class='add'>+#define regMPC_CRC_RESULT_AR                                                                            0x02b6</div><div class='add'>+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_CRC_RESULT_GB                                                                            0x02b7</div><div class='add'>+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_CRC_RESULT_C                                                                             0x02b8</div><div class='add'>+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_BYPASS_BG_AR                                                                             0x02bc</div><div class='add'>+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_BYPASS_BG_GB                                                                             0x02bd</div><div class='add'>+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3</div><div class='add'>+#define regMPC_HOST_READ_CONTROL                                                                        0x02be</div><div class='add'>+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regMPC_DPP_PENDING_STATUS                                                                       0x02bf</div><div class='add'>+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_PENDING_STATUS_MISC                                                                      0x02c0</div><div class='add'>+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x02c1</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x02c2</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET0                                                                        0x02c3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x02c4</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x02c5</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x02c6</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x02c7</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET1                                                                        0x02c8</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x02c9</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x02ca</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x02cb</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x02cc</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET2                                                                        0x02cd</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x02ce</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x02cf</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x02d0</div><div class='add'>+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x02d1</div><div class='add'>+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET3                                                                        0x02d2</div><div class='add'>+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x02d3</div><div class='add'>+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x02d4</div><div class='add'>+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3</div><div class='add'>+#define regHUBP0_3DLUT_FL_CONFIG                                                                        0x02d5</div><div class='add'>+#define regHUBP0_3DLUT_FL_CONFIG_BASE_IDX                                                               3</div><div class='add'>+#define regHUBP0_3DLUT_FL_BIAS_SCALE                                                                    0x02d6</div><div class='add'>+#define regHUBP0_3DLUT_FL_BIAS_SCALE_BASE_IDX                                                           3</div><div class='add'>+#define regHUBP1_3DLUT_FL_CONFIG                                                                        0x02d7</div><div class='add'>+#define regHUBP1_3DLUT_FL_CONFIG_BASE_IDX                                                               3</div><div class='add'>+#define regHUBP1_3DLUT_FL_BIAS_SCALE                                                                    0x02d8</div><div class='add'>+#define regHUBP1_3DLUT_FL_BIAS_SCALE_BASE_IDX                                                           3</div><div class='add'>+#define regHUBP2_3DLUT_FL_CONFIG                                                                        0x02d9</div><div class='add'>+#define regHUBP2_3DLUT_FL_CONFIG_BASE_IDX                                                               3</div><div class='add'>+#define regHUBP2_3DLUT_FL_BIAS_SCALE                                                                    0x02da</div><div class='add'>+#define regHUBP2_3DLUT_FL_BIAS_SCALE_BASE_IDX                                                           3</div><div class='add'>+#define regHUBP3_3DLUT_FL_CONFIG                                                                        0x02db</div><div class='add'>+#define regHUBP3_3DLUT_FL_CONFIG_BASE_IDX                                                               3</div><div class='add'>+#define regHUBP3_3DLUT_FL_BIAS_SCALE                                                                    0x02dc</div><div class='add'>+#define regHUBP3_3DLUT_FL_BIAS_SCALE_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_DWB0_MUX                                                                                 0x02ee</div><div class='add'>+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x007e</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x007f</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0080</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0081</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0082</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0083</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0084</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0085</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0086</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0087</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0088</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0089</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x008a</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x008b</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x008c</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x008d</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x008e</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x008f</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0090</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0091</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0092</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0093</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0094</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0095</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0096</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0097</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0098</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0099</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x009a</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x009b</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x009c</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x009d</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x009e</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x009f</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00a0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00a1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x00a2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x00a3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x00a4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x00a5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x00a6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x00a7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x00a8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x00a9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x00aa</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x00ab</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x00ac</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x00ad</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x00ae</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x00af</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x00b0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x00b1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x00b2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x00b3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x00b4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x00b5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x00b6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x00b7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x00b8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x00b9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x00ba</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x00bb</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x00bc</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x00bd</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x00be</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x00bf</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x00c0</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x00c1</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x00c2</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x00c3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x00c4</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x00c5</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x00c6</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x00c7</div><div class='add'>+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x00c8</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x00c9</div><div class='add'>+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x00ca</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x00cb</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x00cc</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x00cd</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x00ce</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x00cf</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x00d0</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x00d1</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x00d2</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x00d3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x00d4</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x00d5</div><div class='add'>+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam1_dispdec</div><div class='add'>+// base address: 0x178</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x00dc</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x00dd</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x00de</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x00df</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x00e0</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x00e1</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x00e2</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x00e3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x00e4</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x00e5</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x00e6</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x00e7</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x00e8</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x00e9</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x00ea</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x00eb</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x00ec</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x00ed</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x00ee</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x00ef</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x00f0</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x00f1</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x00f2</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x00f3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x00f4</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x00f5</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x00f6</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x00f7</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x00f8</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x00f9</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x00fa</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x00fb</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x00fc</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x00fd</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x00fe</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x00ff</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0100</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0101</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0102</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0103</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0104</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0105</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0106</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0107</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0108</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0109</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x010a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x010b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x010c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x010d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x010e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x010f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0110</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0111</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0112</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0113</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0114</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0115</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0116</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0117</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0118</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0119</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x011a</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x011b</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x011c</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x011d</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x011e</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x011f</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0120</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0121</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0122</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0123</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0124</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0125</div><div class='add'>+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0126</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x0127</div><div class='add'>+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0128</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0129</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x012a</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x012b</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x012c</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x012d</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x012e</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x012f</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0130</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0131</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0132</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0133</div><div class='add'>+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam2_dispdec</div><div class='add'>+// base address: 0x2f0</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x013a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x013b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x013c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x013d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x013e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x013f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0140</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0141</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0142</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0143</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x0144</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x0145</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x0146</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x0147</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x0148</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x0149</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x014a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x014b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x014c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x014d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x014e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x014f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0150</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0151</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0152</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0153</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x0154</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x0155</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x0156</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x0157</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x0158</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x0159</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x015a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x015b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x015c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x015d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x015e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x015f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0160</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0161</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0162</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0163</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x0164</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x0165</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x0166</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x0167</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x0168</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x0169</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x016a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x016b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x016c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x016d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x016e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x016f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0170</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0171</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0172</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0173</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x0174</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x0175</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x0176</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x0177</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x0178</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x0179</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x017a</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x017b</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x017c</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x017d</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x017e</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x017f</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0180</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0181</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0182</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0183</div><div class='add'>+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x0184</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x0185</div><div class='add'>+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x0186</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x0187</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x0188</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x0189</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x018a</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x018b</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x018c</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x018d</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x018e</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x018f</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0190</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0191</div><div class='add'>+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam3_dispdec</div><div class='add'>+// base address: 0x468</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x0198</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x0199</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x019a</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x019b</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x019c</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x019d</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x019e</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x019f</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x01a0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x01a1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x01a2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x01a3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x01a4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x01a5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x01a6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x01a7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x01a8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x01a9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x01aa</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x01ab</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x01ac</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x01ad</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x01ae</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x01af</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x01b0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x01b1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x01b2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x01b3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x01b4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x01b5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x01b6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x01b7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01b8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01b9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01ba</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01bb</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01bc</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01bd</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01be</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01bf</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01c0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01c1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01c2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01c3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01c4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01c5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01c6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01c7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01c8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01c9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01ca</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01cb</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01cc</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01cd</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01ce</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01cf</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01d0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01d1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01d2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01d3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01d4</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01d5</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01d6</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01d7</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01d8</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01d9</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01da</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01db</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01dc</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01dd</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01de</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01df</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01e0</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01e1</div><div class='add'>+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01e2</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x01e3</div><div class='add'>+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01e4</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01e5</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01e6</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01e7</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01e8</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01e9</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01ea</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01eb</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01ec</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01ed</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01ee</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01ef</div><div class='add'>+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL                                                            0x0453</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0454</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0455</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0456</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R                                                            0x0457</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0458</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0459</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA                                                           0x045a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x045b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x045c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x045d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x045e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x045f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0460</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0461</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0462</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0463</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0464</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0465</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0466</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0467</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0468</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0469</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x046a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x046b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x046c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x046d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x046e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x046f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0470</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0471</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0472</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0473</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0474</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0475</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0476</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0477</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0478</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0479</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x047a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x047b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x047c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x047d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x047e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x047f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0480</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0481</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0482</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0483</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0484</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0485</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0486</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0487</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0488</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0489</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE                                                                0x048a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX                                                               0x048b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA                                                                0x048c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x048d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x048e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x048f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0490</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0491</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0492</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL                                                             0x0493</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0494</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0495</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0496</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0497</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0498</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0499</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x049a</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x049b</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x049c</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x049d</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x049e</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x049f</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x04a0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x04a1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x04a2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x04a3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x04a4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x04a5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x04a6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x04a7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x04a8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x04a9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x04aa</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x04ab</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x04ac</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x04ad</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x04ae</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x04af</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x04b0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x04b1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x04b2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x04b3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x04b4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x04b5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x04b6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x04b7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x04b8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x04b9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x04ba</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x04bb</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x04bc</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x04bd</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x04be</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x04bf</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x04c0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x04c1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x04c2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x04c3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x04c4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x04c5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x04c6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x04c7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x04c8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x04c9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x04ca</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x04cb</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x04cc</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x04cd</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x04ce</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x04cf</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x04d0</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x04d1</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x04d2</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x04d3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x04d4</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x04d5</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x04d6</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x04d7</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x04d8</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x04d9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x04da</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x04db</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x04dc</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT                                             0x04dd</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE                                                    0x04de</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A                                                0x04df</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A                                                0x04e0</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A                                                0x04e1</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A                                                0x04e2</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A                                                0x04e3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A                                                0x04e4</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B                                                0x04e5</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B                                                0x04e6</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B                                                0x04e7</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B                                                0x04e8</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B                                                0x04e9</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B                                                0x04ea</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT                                            0x04eb</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                   3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE                                                   0x04ec</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A                                               0x04ed</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A                                               0x04ee</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A                                               0x04ef</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A                                               0x04f0</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A                                               0x04f1</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A                                               0x04f2</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B                                               0x04f3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B                                               0x04f4</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B                                               0x04f5</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B                                               0x04f6</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B                                               0x04f7</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B                                               0x04f8</div><div class='add'>+#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL                                                              0x04f9</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT                                                    0x04fa</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS                                                    0x04fb</div><div class='add'>+#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX                                           3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm1_dispdec</div><div class='add'>+// base address: 0x2c0</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL                                                            0x0503</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0504</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0505</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0506</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R                                                            0x0507</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0508</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0509</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA                                                           0x050a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x050b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x050c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x050d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x050e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x050f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0510</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0511</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0512</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0513</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0514</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0515</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0516</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0517</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0518</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0519</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x051a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x051b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x051c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x051d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x051e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x051f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0520</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0521</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0522</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0523</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0524</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0525</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0526</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0527</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0528</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0529</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x052a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x052b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x052c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x052d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x052e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x052f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0530</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0531</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0532</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0533</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0534</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0535</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0536</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0537</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0538</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0539</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE                                                                0x053a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX                                                               0x053b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA                                                                0x053c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x053d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x053e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x053f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x0540</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x0541</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x0542</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL                                                             0x0543</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x0544</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA                                                            0x0545</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x0546</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x0547</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x0548</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x0549</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x054a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x054b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x054c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x054d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x054e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x054f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0550</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0551</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0552</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0553</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0554</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0555</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0556</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0557</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0558</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0559</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x055a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x055b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x055c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x055d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x055e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x055f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0560</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0561</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0562</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0563</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0564</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0565</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0566</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0567</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0568</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0569</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x056a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x056b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x056c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x056d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x056e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x056f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0570</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0571</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0572</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0573</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0574</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0575</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0576</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0577</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0578</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0579</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x057a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x057b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x057c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x057d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x057e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x057f</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0580</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0581</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0582</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0583</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0584</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0585</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0586</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0587</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0588</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0589</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x058a</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x058b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x058c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT                                             0x058d</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE                                                    0x058e</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A                                                0x058f</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A                                                0x0590</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A                                                0x0591</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A                                                0x0592</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A                                                0x0593</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A                                                0x0594</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B                                                0x0595</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B                                                0x0596</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B                                                0x0597</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B                                                0x0598</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B                                                0x0599</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B                                                0x059a</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT                                            0x059b</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                   3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE                                                   0x059c</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A                                               0x059d</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A                                               0x059e</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A                                               0x059f</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A                                               0x05a0</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A                                               0x05a1</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A                                               0x05a2</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B                                               0x05a3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B                                               0x05a4</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B                                               0x05a5</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B                                               0x05a6</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B                                               0x05a7</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B                                               0x05a8</div><div class='add'>+#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL                                                              0x05a9</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT                                                    0x05aa</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS                                                    0x05ab</div><div class='add'>+#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX                                           3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm2_dispdec</div><div class='add'>+// base address: 0x580</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL                                                            0x05b3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R                                                           0x05b4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G                                                           0x05b5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B                                                           0x05b6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R                                                            0x05b7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x05b8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x05b9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA                                                           0x05ba</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x05bb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x05bc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x05bd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x05be</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x05bf</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x05c0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x05c1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x05c2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x05c3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x05c4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x05c5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x05c6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x05c7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x05c8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x05c9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x05ca</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x05cb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x05cc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x05cd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x05ce</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x05cf</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x05d0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x05d1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x05d2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x05d3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x05d4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x05d5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x05d6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x05d7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x05d8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x05d9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x05da</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x05db</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x05dc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x05dd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x05de</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x05df</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x05e0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x05e1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x05e2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x05e3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x05e4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x05e5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x05e6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x05e7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x05e8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x05e9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE                                                                0x05ea</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX                                                               0x05eb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA                                                                0x05ec</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x05ed</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x05ee</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x05ef</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x05f0</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x05f1</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x05f2</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL                                                             0x05f3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x05f4</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA                                                            0x05f5</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x05f6</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x05f7</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x05f8</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x05f9</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x05fa</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x05fb</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x05fc</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x05fd</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x05fe</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x05ff</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x0600</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x0601</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x0602</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x0603</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x0604</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x0605</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x0606</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x0607</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x0608</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x0609</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x060a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x060b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x060c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x060d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x060e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x060f</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x0610</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x0611</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x0612</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x0613</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x0614</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x0615</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x0616</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x0617</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x0618</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x0619</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x061a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x061b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x061c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x061d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x061e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x061f</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x0620</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x0621</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x0622</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x0623</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x0624</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x0625</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x0626</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x0627</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x0628</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x0629</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x062a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x062b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x062c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x062d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x062e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x062f</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x0630</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x0631</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x0632</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x0633</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x0634</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x0635</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x0636</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x0637</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x0638</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x0639</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x063a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x063b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x063c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT                                             0x063d</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE                                                    0x063e</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A                                                0x063f</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A                                                0x0640</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A                                                0x0641</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A                                                0x0642</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A                                                0x0643</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A                                                0x0644</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B                                                0x0645</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B                                                0x0646</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B                                                0x0647</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B                                                0x0648</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B                                                0x0649</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B                                                0x064a</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT                                            0x064b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                   3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE                                                   0x064c</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A                                               0x064d</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A                                               0x064e</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A                                               0x064f</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A                                               0x0650</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A                                               0x0651</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A                                               0x0652</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B                                               0x0653</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B                                               0x0654</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B                                               0x0655</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B                                               0x0656</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B                                               0x0657</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B                                               0x0658</div><div class='add'>+#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL                                                              0x0659</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT                                                    0x065a</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS                                                    0x065b</div><div class='add'>+#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX                                           3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm3_dispdec</div><div class='add'>+// base address: 0x840</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL                                                            0x0663</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R                                                           0x0664</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G                                                           0x0665</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B                                                           0x0666</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R                                                            0x0667</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B                                                          0x0668</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX                                                          0x0669</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA                                                           0x066a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK                                                  0x066b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B                                                  0x066c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G                                                  0x066d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R                                                  0x066e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B                                                    0x066f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G                                                    0x0670</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R                                                    0x0671</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1                                                    0x0672</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3                                                    0x0673</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5                                                    0x0674</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7                                                    0x0675</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9                                                    0x0676</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11                                                  0x0677</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13                                                  0x0678</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15                                                  0x0679</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17                                                  0x067a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19                                                  0x067b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21                                                  0x067c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23                                                  0x067d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25                                                  0x067e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27                                                  0x067f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29                                                  0x0680</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31                                                  0x0681</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33                                                  0x0682</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B                                                  0x0683</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G                                                  0x0684</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R                                                  0x0685</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B                                                    0x0686</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G                                                    0x0687</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R                                                    0x0688</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1                                                    0x0689</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3                                                    0x068a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5                                                    0x068b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7                                                    0x068c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9                                                    0x068d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11                                                  0x068e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13                                                  0x068f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15                                                  0x0690</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17                                                  0x0691</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19                                                  0x0692</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21                                                  0x0693</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23                                                  0x0694</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25                                                  0x0695</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27                                                  0x0696</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29                                                  0x0697</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31                                                  0x0698</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33                                                  0x0699</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE                                                                0x069a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX                                                               0x069b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX                                                      3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA                                                                0x069c</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX                                                       3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT                                                          0x069d</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX                                                 3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL                                                  0x069e</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                         3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR                                                     0x069f</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R                                                        0x06a0</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G                                                        0x06a1</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B                                                        0x06a2</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX                                               3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL                                                             0x06a3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX                                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX                                                           0x06a4</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX                                                  3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA                                                            0x06a5</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX                                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL                                                         0x06a6</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX                                                3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B                                                   0x06a7</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G                                                   0x06a8</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R                                                   0x06a9</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B                                             0x06aa</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G                                             0x06ab</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R                                             0x06ac</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B                                              0x06ad</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G                                              0x06ae</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R                                              0x06af</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B                                                    0x06b0</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B                                                    0x06b1</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G                                                    0x06b2</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G                                                    0x06b3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R                                                    0x06b4</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R                                                    0x06b5</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B                                                       0x06b6</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G                                                       0x06b7</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R                                                       0x06b8</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1                                                     0x06b9</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3                                                     0x06ba</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5                                                     0x06bb</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7                                                     0x06bc</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9                                                     0x06bd</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11                                                   0x06be</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13                                                   0x06bf</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15                                                   0x06c0</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17                                                   0x06c1</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19                                                   0x06c2</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21                                                   0x06c3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23                                                   0x06c4</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25                                                   0x06c5</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27                                                   0x06c6</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29                                                   0x06c7</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31                                                   0x06c8</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33                                                   0x06c9</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B                                                   0x06ca</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G                                                   0x06cb</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R                                                   0x06cc</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B                                             0x06cd</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G                                             0x06ce</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R                                             0x06cf</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B                                              0x06d0</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G                                              0x06d1</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R                                              0x06d2</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B                                                    0x06d3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B                                                    0x06d4</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G                                                    0x06d5</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G                                                    0x06d6</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R                                                    0x06d7</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R                                                    0x06d8</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B                                                       0x06d9</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G                                                       0x06da</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R                                                       0x06db</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX                                              3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1                                                     0x06dc</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3                                                     0x06dd</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5                                                     0x06de</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7                                                     0x06df</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9                                                     0x06e0</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX                                            3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11                                                   0x06e1</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13                                                   0x06e2</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15                                                   0x06e3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17                                                   0x06e4</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19                                                   0x06e5</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21                                                   0x06e6</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23                                                   0x06e7</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25                                                   0x06e8</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27                                                   0x06e9</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29                                                   0x06ea</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31                                                   0x06eb</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33                                                   0x06ec</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT                                             0x06ed</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                    3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE                                                    0x06ee</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A                                                0x06ef</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A                                                0x06f0</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A                                                0x06f1</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A                                                0x06f2</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A                                                0x06f3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A                                                0x06f4</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B                                                0x06f5</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B                                                0x06f6</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B                                                0x06f7</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B                                                0x06f8</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B                                                0x06f9</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B                                                0x06fa</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX                                       3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT                                            0x06fb</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                   3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE                                                   0x06fc</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX                                          3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A                                               0x06fd</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A                                               0x06fe</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A                                               0x06ff</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A                                               0x0700</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A                                               0x0701</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A                                               0x0702</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B                                               0x0703</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B                                               0x0704</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B                                               0x0705</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B                                               0x0706</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B                                               0x0707</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B                                               0x0708</div><div class='add'>+#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX                                      3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL                                                              0x0709</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX                                                     3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT                                                    0x070a</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX                                           3</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS                                                    0x070b</div><div class='add'>+#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX                                           3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpc_ocsc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regMPC_OUT0_MUX                                                                                 0x02f2</div><div class='add'>+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x02f3</div><div class='add'>+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x02f4</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x02f5</div><div class='add'>+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT1_MUX                                                                                 0x02f6</div><div class='add'>+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x02f7</div><div class='add'>+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x02f8</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x02f9</div><div class='add'>+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT2_MUX                                                                                 0x02fa</div><div class='add'>+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x02fb</div><div class='add'>+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x02fc</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x02fd</div><div class='add'>+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT3_MUX                                                                                 0x02fe</div><div class='add'>+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3</div><div class='add'>+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x02ff</div><div class='add'>+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x0300</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x0301</div><div class='add'>+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3</div><div class='add'>+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x030a</div><div class='add'>+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3</div><div class='add'>+#define regMPC_OUT0_CSC_MODE                                                                            0x030b</div><div class='add'>+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x030c</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x030d</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x030e</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x030f</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x0310</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x0311</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x0312</div><div class='add'>+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x0313</div><div class='add'>+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x0314</div><div class='add'>+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x0315</div><div class='add'>+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x0316</div><div class='add'>+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x0317</div><div class='add'>+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_MODE                                                                            0x0318</div><div class='add'>+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x0319</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x031a</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x031b</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x031c</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x031d</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x031e</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x031f</div><div class='add'>+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x0320</div><div class='add'>+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x0321</div><div class='add'>+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x0322</div><div class='add'>+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x0323</div><div class='add'>+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x0324</div><div class='add'>+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_MODE                                                                            0x0325</div><div class='add'>+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x0326</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x0327</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x0328</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x0329</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x032a</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x032b</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x032c</div><div class='add'>+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x032d</div><div class='add'>+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x032e</div><div class='add'>+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x032f</div><div class='add'>+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x0330</div><div class='add'>+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x0331</div><div class='add'>+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_MODE                                                                            0x0332</div><div class='add'>+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x0333</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x0334</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x0335</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x0336</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x0337</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x0338</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x0339</div><div class='add'>+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x033a</div><div class='add'>+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x033b</div><div class='add'>+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x033c</div><div class='add'>+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x033d</div><div class='add'>+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x033e</div><div class='add'>+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3</div><div class='add'>+#define regMPC_OCSC_TEST_DEBUG_INDEX                                                                    0x035b</div><div class='add'>+#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX                                                           3</div><div class='add'>+#define regMPC_OCSC_TEST_DEBUG_DATA                                                                     0x035c</div><div class='add'>+#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX                                                            3</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a</div><div class='add'>+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b</div><div class='add'>+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c</div><div class='add'>+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d</div><div class='add'>+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e</div><div class='add'>+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f</div><div class='add'>+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80</div><div class='add'>+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81</div><div class='add'>+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82</div><div class='add'>+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83</div><div class='add'>+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84</div><div class='add'>+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_PWL_CNTL                                                                    0x0e85</div><div class='add'>+#define regABM0_DC_ABM1_ACE_PWL_CNTL_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA                                                           0x0e86</div><div class='add'>+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_THRES_DATA                                                                  0x0e87</div><div class='add'>+#define regABM0_DC_ABM1_ACE_THRES_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e88</div><div class='add'>+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8a</div><div class='add'>+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8b</div><div class='add'>+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e8c</div><div class='add'>+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e8d</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e8e</div><div class='add'>+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e8f</div><div class='add'>+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e90</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e91</div><div class='add'>+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e92</div><div class='add'>+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e93</div><div class='add'>+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e94</div><div class='add'>+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e95</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG                                                         0x0e96</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX                                                3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e97</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e98</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e99</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9a</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX                                                        0x0e9b</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX                                                        0x0e9c</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX                                                        0x0e9d</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX                                                        0x0e9e</div><div class='add'>+#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_INDEX                                                                 0x0e9f</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_INDEX_BASE_IDX                                                        3</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_DATA                                                                  0x0ea0</div><div class='add'>+#define regABM0_DC_ABM1_HG_RESULT_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ea1</div><div class='add'>+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm1_dispdec</div><div class='add'>+// base address: 0x104</div><div class='add'>+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb</div><div class='add'>+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc</div><div class='add'>+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd</div><div class='add'>+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe</div><div class='add'>+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf</div><div class='add'>+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0</div><div class='add'>+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1</div><div class='add'>+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2</div><div class='add'>+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3</div><div class='add'>+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4</div><div class='add'>+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5</div><div class='add'>+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_PWL_CNTL                                                                    0x0ec6</div><div class='add'>+#define regABM1_DC_ABM1_ACE_PWL_CNTL_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA                                                           0x0ec7</div><div class='add'>+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_THRES_DATA                                                                  0x0ec8</div><div class='add'>+#define regABM1_DC_ABM1_ACE_THRES_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ec9</div><div class='add'>+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecb</div><div class='add'>+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ecc</div><div class='add'>+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ecd</div><div class='add'>+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ece</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ecf</div><div class='add'>+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed0</div><div class='add'>+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed1</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed2</div><div class='add'>+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed3</div><div class='add'>+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed4</div><div class='add'>+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed5</div><div class='add'>+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0ed6</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG                                                         0x0ed7</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX                                                3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0ed8</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0ed9</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0eda</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0edb</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX                                                        0x0edc</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX                                                        0x0edd</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX                                                        0x0ede</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX                                                        0x0edf</div><div class='add'>+#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_INDEX                                                                 0x0ee0</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_INDEX_BASE_IDX                                                        3</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_DATA                                                                  0x0ee1</div><div class='add'>+#define regABM1_DC_ABM1_HG_RESULT_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ee2</div><div class='add'>+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm2_dispdec</div><div class='add'>+// base address: 0x208</div><div class='add'>+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc</div><div class='add'>+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd</div><div class='add'>+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe</div><div class='add'>+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff</div><div class='add'>+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00</div><div class='add'>+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01</div><div class='add'>+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02</div><div class='add'>+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03</div><div class='add'>+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04</div><div class='add'>+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05</div><div class='add'>+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06</div><div class='add'>+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_PWL_CNTL                                                                    0x0f07</div><div class='add'>+#define regABM2_DC_ABM1_ACE_PWL_CNTL_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA                                                           0x0f08</div><div class='add'>+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_THRES_DATA                                                                  0x0f09</div><div class='add'>+#define regABM2_DC_ABM1_ACE_THRES_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0a</div><div class='add'>+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f0c</div><div class='add'>+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f0d</div><div class='add'>+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f0e</div><div class='add'>+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f0f</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f10</div><div class='add'>+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f11</div><div class='add'>+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f12</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f13</div><div class='add'>+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f14</div><div class='add'>+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f15</div><div class='add'>+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f16</div><div class='add'>+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f17</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG                                                         0x0f18</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX                                                3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f19</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1a</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1b</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1c</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX                                                        0x0f1d</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX                                                        0x0f1e</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX                                                        0x0f1f</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX                                                        0x0f20</div><div class='add'>+#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_INDEX                                                                 0x0f21</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_INDEX_BASE_IDX                                                        3</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_DATA                                                                  0x0f22</div><div class='add'>+#define regABM2_DC_ABM1_HG_RESULT_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f23</div><div class='add'>+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm3_dispdec</div><div class='add'>+// base address: 0x30c</div><div class='add'>+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d</div><div class='add'>+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3</div><div class='add'>+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e</div><div class='add'>+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3</div><div class='add'>+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f</div><div class='add'>+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3</div><div class='add'>+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40</div><div class='add'>+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3</div><div class='add'>+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41</div><div class='add'>+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3</div><div class='add'>+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42</div><div class='add'>+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3</div><div class='add'>+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43</div><div class='add'>+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3</div><div class='add'>+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44</div><div class='add'>+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3</div><div class='add'>+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45</div><div class='add'>+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3</div><div class='add'>+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46</div><div class='add'>+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3</div><div class='add'>+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47</div><div class='add'>+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_PWL_CNTL                                                                    0x0f48</div><div class='add'>+#define regABM3_DC_ABM1_ACE_PWL_CNTL_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA                                                           0x0f49</div><div class='add'>+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX                                                  3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_THRES_DATA                                                                  0x0f4a</div><div class='add'>+#define regABM3_DC_ABM1_ACE_THRES_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4b</div><div class='add'>+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3</div><div class='add'>+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f4d</div><div class='add'>+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3</div><div class='add'>+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f4e</div><div class='add'>+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3</div><div class='add'>+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f4f</div><div class='add'>+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f50</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3</div><div class='add'>+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f51</div><div class='add'>+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f52</div><div class='add'>+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f53</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f54</div><div class='add'>+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f55</div><div class='add'>+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f56</div><div class='add'>+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f57</div><div class='add'>+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f58</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG                                                         0x0f59</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX                                                3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5a</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5b</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5c</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f5d</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX                                                        0x0f5e</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX                                                        0x0f5f</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX                                                        0x0f60</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX                                                        0x0f61</div><div class='add'>+#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX                                               3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_INDEX                                                                 0x0f62</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_INDEX_BASE_IDX                                                        3</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_DATA                                                                  0x0f63</div><div class='add'>+#define regABM3_DC_ABM1_HG_RESULT_DATA_BASE_IDX                                                         3</div><div class='add'>+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f64</div><div class='add'>+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDPG0_DPG_CONTROL                                                                             0x1854</div><div class='add'>+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855</div><div class='add'>+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856</div><div class='add'>+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857</div><div class='add'>+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858</div><div class='add'>+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859</div><div class='add'>+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a</div><div class='add'>+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG0_DPG_STATUS                                                                              0x185b</div><div class='add'>+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e</div><div class='add'>+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f</div><div class='add'>+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT0_FMT_CONTROL                                                                             0x1840</div><div class='add'>+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841</div><div class='add'>+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844</div><div class='add'>+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845</div><div class='add'>+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846</div><div class='add'>+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847</div><div class='add'>+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT0_FMT_422_CONTROL                                                                         0x1849</div><div class='add'>+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886</div><div class='add'>+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889</div><div class='add'>+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c</div><div class='add'>+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895</div><div class='add'>+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regDPG1_DPG_CONTROL                                                                             0x18ae</div><div class='add'>+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af</div><div class='add'>+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0</div><div class='add'>+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1</div><div class='add'>+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2</div><div class='add'>+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3</div><div class='add'>+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4</div><div class='add'>+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG1_DPG_STATUS                                                                              0x18b5</div><div class='add'>+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898</div><div class='add'>+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899</div><div class='add'>+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT1_FMT_CONTROL                                                                             0x189a</div><div class='add'>+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b</div><div class='add'>+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e</div><div class='add'>+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f</div><div class='add'>+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0</div><div class='add'>+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1</div><div class='add'>+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3</div><div class='add'>+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0</div><div class='add'>+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3</div><div class='add'>+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6</div><div class='add'>+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc1_dispdec</div><div class='add'>+// base address: 0x168</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef</div><div class='add'>+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regDPG2_DPG_CONTROL                                                                             0x1908</div><div class='add'>+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909</div><div class='add'>+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a</div><div class='add'>+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b</div><div class='add'>+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c</div><div class='add'>+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d</div><div class='add'>+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e</div><div class='add'>+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG2_DPG_STATUS                                                                              0x190f</div><div class='add'>+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2</div><div class='add'>+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3</div><div class='add'>+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT2_FMT_CONTROL                                                                             0x18f4</div><div class='add'>+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5</div><div class='add'>+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8</div><div class='add'>+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9</div><div class='add'>+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa</div><div class='add'>+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb</div><div class='add'>+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd</div><div class='add'>+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a</div><div class='add'>+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d</div><div class='add'>+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940</div><div class='add'>+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc2_dispdec</div><div class='add'>+// base address: 0x2d0</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949</div><div class='add'>+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regDPG3_DPG_CONTROL                                                                             0x1962</div><div class='add'>+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963</div><div class='add'>+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964</div><div class='add'>+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965</div><div class='add'>+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2</div><div class='add'>+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966</div><div class='add'>+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967</div><div class='add'>+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2</div><div class='add'>+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968</div><div class='add'>+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2</div><div class='add'>+#define regDPG3_DPG_STATUS                                                                              0x1969</div><div class='add'>+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c</div><div class='add'>+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d</div><div class='add'>+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regFMT3_FMT_CONTROL                                                                             0x194e</div><div class='add'>+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f</div><div class='add'>+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952</div><div class='add'>+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2</div><div class='add'>+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953</div><div class='add'>+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954</div><div class='add'>+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955</div><div class='add'>+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regFMT3_FMT_422_CONTROL                                                                         0x1957</div><div class='add'>+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994</div><div class='add'>+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997</div><div class='add'>+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a</div><div class='add'>+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc3_dispdec</div><div class='add'>+// base address: 0x438</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3</div><div class='add'>+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64</div><div class='add'>+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm1_dispdec</div><div class='add'>+// base address: 0x4</div><div class='add'>+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65</div><div class='add'>+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm2_dispdec</div><div class='add'>+// base address: 0x8</div><div class='add'>+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66</div><div class='add'>+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm3_dispdec</div><div class='add'>+// base address: 0xc</div><div class='add'>+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67</div><div class='add'>+#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e</div><div class='add'>+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regOPP_ABM_CONTROL                                                                              0x1a60</div><div class='add'>+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca</div><div class='add'>+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb</div><div class='add'>+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc</div><div class='add'>+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd</div><div class='add'>+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace</div><div class='add'>+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM0_OPTC_WIDTH_CONTROL2                                                                     0x1acf</div><div class='add'>+#define regODM0_OPTC_WIDTH_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1ad0</div><div class='add'>+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad1</div><div class='add'>+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad2</div><div class='add'>+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm1_dispdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada</div><div class='add'>+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb</div><div class='add'>+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc</div><div class='add'>+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add</div><div class='add'>+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade</div><div class='add'>+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM1_OPTC_WIDTH_CONTROL2                                                                     0x1adf</div><div class='add'>+#define regODM1_OPTC_WIDTH_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1ae0</div><div class='add'>+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae1</div><div class='add'>+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae2</div><div class='add'>+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm2_dispdec</div><div class='add'>+// base address: 0x80</div><div class='add'>+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea</div><div class='add'>+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb</div><div class='add'>+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec</div><div class='add'>+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed</div><div class='add'>+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee</div><div class='add'>+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM2_OPTC_WIDTH_CONTROL2                                                                     0x1aef</div><div class='add'>+#define regODM2_OPTC_WIDTH_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1af0</div><div class='add'>+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af1</div><div class='add'>+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af2</div><div class='add'>+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm3_dispdec</div><div class='add'>+// base address: 0xc0</div><div class='add'>+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa</div><div class='add'>+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb</div><div class='add'>+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2</div><div class='add'>+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc</div><div class='add'>+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd</div><div class='add'>+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2</div><div class='add'>+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe</div><div class='add'>+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regODM3_OPTC_WIDTH_CONTROL2                                                                     0x1aff</div><div class='add'>+#define regODM3_OPTC_WIDTH_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b00</div><div class='add'>+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b01</div><div class='add'>+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2</div><div class='add'>+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b02</div><div class='add'>+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a</div><div class='add'>+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b</div><div class='add'>+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d</div><div class='add'>+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e</div><div class='add'>+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL                                                                0x1b34</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL2                                                               0x1b35</div><div class='add'>+#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b36</div><div class='add'>+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b37</div><div class='add'>+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b38</div><div class='add'>+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b39</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b3a</div><div class='add'>+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b3b</div><div class='add'>+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3c</div><div class='add'>+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3d</div><div class='add'>+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3e</div><div class='add'>+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3f</div><div class='add'>+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b40</div><div class='add'>+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b41</div><div class='add'>+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_CONTROL                                                                             0x1b43</div><div class='add'>+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG0_OTG_DLPC_CONTROL                                                                        0x1b44</div><div class='add'>+#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b45</div><div class='add'>+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b46</div><div class='add'>+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48</div><div class='add'>+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_STATUS                                                                              0x1b49</div><div class='add'>+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a</div><div class='add'>+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_LONG_VBLANK_STATUS                                                                  0x1b4b</div><div class='add'>+#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4c</div><div class='add'>+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4d</div><div class='add'>+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4e</div><div class='add'>+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4f</div><div class='add'>+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b50</div><div class='add'>+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b51</div><div class='add'>+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b52</div><div class='add'>+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b53</div><div class='add'>+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b54</div><div class='add'>+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b55</div><div class='add'>+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b56</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b57</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b58</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b59</div><div class='add'>+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b5a</div><div class='add'>+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5b</div><div class='add'>+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5c</div><div class='add'>+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5d</div><div class='add'>+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b5f</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b60</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b61</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b62</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b63</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b64</div><div class='add'>+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b65</div><div class='add'>+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b66</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b67</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b68</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b69</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6a</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6b</div><div class='add'>+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b6c</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b6d</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b6e</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b6f</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b70</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b71</div><div class='add'>+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b72</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b73</div><div class='add'>+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b74</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b75</div><div class='add'>+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b76</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b77</div><div class='add'>+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1b78</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1b79</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1b7a</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7b</div><div class='add'>+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1b7c</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1b7d</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1b7e</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1b7f</div><div class='add'>+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b80</div><div class='add'>+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b81</div><div class='add'>+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b82</div><div class='add'>+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b83</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b84</div><div class='add'>+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b85</div><div class='add'>+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b86</div><div class='add'>+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b87</div><div class='add'>+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b88</div><div class='add'>+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b89</div><div class='add'>+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8a</div><div class='add'>+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8b</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8c</div><div class='add'>+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8d</div><div class='add'>+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b8e</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b8f</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b90</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b91</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b92</div><div class='add'>+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b93</div><div class='add'>+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b94</div><div class='add'>+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b95</div><div class='add'>+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b96</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b97</div><div class='add'>+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b98</div><div class='add'>+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b99</div><div class='add'>+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_DRR_CONTOL2                                                                         0x1b9a</div><div class='add'>+#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9b</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9c</div><div class='add'>+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9d</div><div class='add'>+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9e</div><div class='add'>+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG0_OTG_PSTATE_REGISTER                                                                     0x1b9f</div><div class='add'>+#define regOTG0_OTG_PSTATE_REGISTER_BASE_IDX                                                            2</div><div class='add'>+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba1</div><div class='add'>+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg1_dispdec</div><div class='add'>+// base address: 0x200</div><div class='add'>+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa</div><div class='add'>+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab</div><div class='add'>+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad</div><div class='add'>+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae</div><div class='add'>+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL                                                                0x1bb4</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL2                                                               0x1bb5</div><div class='add'>+#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb6</div><div class='add'>+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb7</div><div class='add'>+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb8</div><div class='add'>+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb9</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bba</div><div class='add'>+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bbb</div><div class='add'>+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bbc</div><div class='add'>+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbd</div><div class='add'>+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbe</div><div class='add'>+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbf</div><div class='add'>+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bc0</div><div class='add'>+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bc1</div><div class='add'>+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_CONTROL                                                                             0x1bc3</div><div class='add'>+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG1_OTG_DLPC_CONTROL                                                                        0x1bc4</div><div class='add'>+#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc5</div><div class='add'>+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc6</div><div class='add'>+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8</div><div class='add'>+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_STATUS                                                                              0x1bc9</div><div class='add'>+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca</div><div class='add'>+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_LONG_VBLANK_STATUS                                                                  0x1bcb</div><div class='add'>+#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcc</div><div class='add'>+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcd</div><div class='add'>+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bce</div><div class='add'>+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bcf</div><div class='add'>+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bd0</div><div class='add'>+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd1</div><div class='add'>+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd2</div><div class='add'>+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd3</div><div class='add'>+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd4</div><div class='add'>+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd5</div><div class='add'>+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd6</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd7</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd8</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd9</div><div class='add'>+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bda</div><div class='add'>+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bdb</div><div class='add'>+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdc</div><div class='add'>+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdd</div><div class='add'>+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1bdf</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be0</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be1</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be3</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be4</div><div class='add'>+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be5</div><div class='add'>+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1be6</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1be7</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1be8</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1be9</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bea</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1beb</div><div class='add'>+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bec</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bed</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bee</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bef</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf0</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf1</div><div class='add'>+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf2</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf3</div><div class='add'>+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf4</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf5</div><div class='add'>+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bf6</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bf7</div><div class='add'>+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1bf8</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1bf9</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1bfa</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1bfb</div><div class='add'>+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1bfc</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1bfd</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1bfe</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1bff</div><div class='add'>+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c00</div><div class='add'>+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c01</div><div class='add'>+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c02</div><div class='add'>+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c03</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c04</div><div class='add'>+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c05</div><div class='add'>+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c06</div><div class='add'>+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c07</div><div class='add'>+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c08</div><div class='add'>+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c09</div><div class='add'>+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0a</div><div class='add'>+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0b</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0c</div><div class='add'>+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0d</div><div class='add'>+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c0e</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c0f</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c10</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c11</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c12</div><div class='add'>+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c13</div><div class='add'>+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c14</div><div class='add'>+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c15</div><div class='add'>+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c16</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c17</div><div class='add'>+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c18</div><div class='add'>+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c19</div><div class='add'>+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_DRR_CONTOL2                                                                         0x1c1a</div><div class='add'>+#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1b</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1c</div><div class='add'>+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1d</div><div class='add'>+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1e</div><div class='add'>+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG1_OTG_PSTATE_REGISTER                                                                     0x1c1f</div><div class='add'>+#define regOTG1_OTG_PSTATE_REGISTER_BASE_IDX                                                            2</div><div class='add'>+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c21</div><div class='add'>+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg2_dispdec</div><div class='add'>+// base address: 0x400</div><div class='add'>+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a</div><div class='add'>+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b</div><div class='add'>+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d</div><div class='add'>+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e</div><div class='add'>+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL                                                                0x1c34</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL2                                                               0x1c35</div><div class='add'>+#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c36</div><div class='add'>+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c37</div><div class='add'>+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c38</div><div class='add'>+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c39</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c3a</div><div class='add'>+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c3b</div><div class='add'>+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3c</div><div class='add'>+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3d</div><div class='add'>+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3e</div><div class='add'>+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3f</div><div class='add'>+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c40</div><div class='add'>+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c41</div><div class='add'>+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_CONTROL                                                                             0x1c43</div><div class='add'>+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG2_OTG_DLPC_CONTROL                                                                        0x1c44</div><div class='add'>+#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c45</div><div class='add'>+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c46</div><div class='add'>+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48</div><div class='add'>+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_STATUS                                                                              0x1c49</div><div class='add'>+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a</div><div class='add'>+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_LONG_VBLANK_STATUS                                                                  0x1c4b</div><div class='add'>+#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4c</div><div class='add'>+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4d</div><div class='add'>+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4e</div><div class='add'>+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4f</div><div class='add'>+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c50</div><div class='add'>+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c51</div><div class='add'>+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c52</div><div class='add'>+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c53</div><div class='add'>+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c54</div><div class='add'>+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c55</div><div class='add'>+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c56</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c57</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c58</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c59</div><div class='add'>+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c5a</div><div class='add'>+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5b</div><div class='add'>+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5c</div><div class='add'>+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5d</div><div class='add'>+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c5f</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c60</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c61</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c62</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c63</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c64</div><div class='add'>+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c65</div><div class='add'>+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c66</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c67</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c68</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c69</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6a</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6b</div><div class='add'>+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c6c</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c6d</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c6e</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c6f</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c70</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c71</div><div class='add'>+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c72</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c73</div><div class='add'>+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c74</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c75</div><div class='add'>+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c76</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c77</div><div class='add'>+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1c78</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1c79</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1c7a</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7b</div><div class='add'>+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1c7c</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1c7d</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1c7e</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1c7f</div><div class='add'>+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c80</div><div class='add'>+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c81</div><div class='add'>+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c82</div><div class='add'>+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c83</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c84</div><div class='add'>+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c85</div><div class='add'>+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c86</div><div class='add'>+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c87</div><div class='add'>+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c88</div><div class='add'>+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c89</div><div class='add'>+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8a</div><div class='add'>+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8b</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8c</div><div class='add'>+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8d</div><div class='add'>+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c8e</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c8f</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c90</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c91</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c92</div><div class='add'>+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c93</div><div class='add'>+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c94</div><div class='add'>+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c95</div><div class='add'>+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c96</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c97</div><div class='add'>+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c98</div><div class='add'>+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c99</div><div class='add'>+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_DRR_CONTOL2                                                                         0x1c9a</div><div class='add'>+#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9b</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9c</div><div class='add'>+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9d</div><div class='add'>+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9e</div><div class='add'>+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG2_OTG_PSTATE_REGISTER                                                                     0x1c9f</div><div class='add'>+#define regOTG2_OTG_PSTATE_REGISTER_BASE_IDX                                                            2</div><div class='add'>+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca1</div><div class='add'>+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg3_dispdec</div><div class='add'>+// base address: 0x600</div><div class='add'>+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa</div><div class='add'>+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab</div><div class='add'>+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad</div><div class='add'>+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae</div><div class='add'>+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL                                                                0x1cb4</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL2                                                               0x1cb5</div><div class='add'>+#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb6</div><div class='add'>+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb7</div><div class='add'>+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb8</div><div class='add'>+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb9</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cba</div><div class='add'>+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cbb</div><div class='add'>+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cbc</div><div class='add'>+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbd</div><div class='add'>+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbe</div><div class='add'>+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbf</div><div class='add'>+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cc0</div><div class='add'>+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cc1</div><div class='add'>+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_CONTROL                                                                             0x1cc3</div><div class='add'>+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regOTG3_OTG_DLPC_CONTROL                                                                        0x1cc4</div><div class='add'>+#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc5</div><div class='add'>+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc6</div><div class='add'>+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8</div><div class='add'>+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_STATUS                                                                              0x1cc9</div><div class='add'>+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca</div><div class='add'>+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_LONG_VBLANK_STATUS                                                                  0x1ccb</div><div class='add'>+#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccc</div><div class='add'>+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccd</div><div class='add'>+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1cce</div><div class='add'>+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1ccf</div><div class='add'>+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1cd0</div><div class='add'>+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd1</div><div class='add'>+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd2</div><div class='add'>+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd3</div><div class='add'>+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd4</div><div class='add'>+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd5</div><div class='add'>+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd6</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd7</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd8</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd9</div><div class='add'>+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2</div><div class='add'>+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cda</div><div class='add'>+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cdb</div><div class='add'>+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdc</div><div class='add'>+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdd</div><div class='add'>+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1cdf</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce0</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce1</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce3</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce4</div><div class='add'>+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce5</div><div class='add'>+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1ce6</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ce7</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1ce8</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ce9</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1cea</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1ceb</div><div class='add'>+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cec</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1ced</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cee</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cef</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf0</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf1</div><div class='add'>+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf2</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf3</div><div class='add'>+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf4</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf5</div><div class='add'>+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cf6</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cf7</div><div class='add'>+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK                                                     0x1cf8</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK                                                     0x1cf9</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK                                                     0x1cfa</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK                                                     0x1cfb</div><div class='add'>+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK                                                     0x1cfc</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK                                                     0x1cfd</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK                                                     0x1cfe</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK                                                     0x1cff</div><div class='add'>+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX                                            2</div><div class='add'>+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d00</div><div class='add'>+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d01</div><div class='add'>+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d02</div><div class='add'>+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d03</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d04</div><div class='add'>+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d05</div><div class='add'>+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2</div><div class='add'>+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d06</div><div class='add'>+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2</div><div class='add'>+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d07</div><div class='add'>+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d08</div><div class='add'>+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d09</div><div class='add'>+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0a</div><div class='add'>+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0b</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0c</div><div class='add'>+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0d</div><div class='add'>+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d0e</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d0f</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d10</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d11</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d12</div><div class='add'>+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d13</div><div class='add'>+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d14</div><div class='add'>+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d15</div><div class='add'>+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d16</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d17</div><div class='add'>+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d18</div><div class='add'>+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d19</div><div class='add'>+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_DRR_CONTOL2                                                                         0x1d1a</div><div class='add'>+#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX                                                                2</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1b</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1c</div><div class='add'>+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2</div><div class='add'>+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1d</div><div class='add'>+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1e</div><div class='add'>+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regOTG3_OTG_PSTATE_REGISTER                                                                     0x1d1f</div><div class='add'>+#define regOTG3_OTG_PSTATE_REGISTER_BASE_IDX                                                            2</div><div class='add'>+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d21</div><div class='add'>+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_optc_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regGSL_SOURCE_SELECT                                                                            0x1e2b</div><div class='add'>+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2</div><div class='add'>+#define regOPTC_DLPC_CONTROL                                                                            0x1e2c</div><div class='add'>+#define regOPTC_DLPC_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2d</div><div class='add'>+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2</div><div class='add'>+#define regODM_MEM_PWR_CTRL                                                                             0x1e2e</div><div class='add'>+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2</div><div class='add'>+#define regODM_MEM_PWR_CTRL2                                                                            0x1e2f</div><div class='add'>+#define regODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2</div><div class='add'>+#define regODM_MEM_PWR_CTRL3                                                                            0x1e30</div><div class='add'>+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2</div><div class='add'>+#define regODM_MEM_PWR_STATUS                                                                           0x1e31</div><div class='add'>+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e32</div><div class='add'>+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDP0_DP_LINK_CNTL                                                                             0x211e</div><div class='add'>+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_PIXEL_FORMAT                                                                          0x211f</div><div class='add'>+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x2120</div><div class='add'>+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_CONFIG                                                                                0x2121</div><div class='add'>+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x2122</div><div class='add'>+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_STEER_FIFO                                                                            0x2123</div><div class='add'>+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_MSA_MISC                                                                              0x2124</div><div class='add'>+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x2125</div><div class='add'>+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_VID_TIMING                                                                            0x2126</div><div class='add'>+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_VID_N                                                                                 0x2127</div><div class='add'>+#define regDP0_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP0_DP_VID_M                                                                                 0x2128</div><div class='add'>+#define regDP0_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2129</div><div class='add'>+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x212a</div><div class='add'>+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_VID_MSA_VBID                                                                          0x212b</div><div class='add'>+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x212c</div><div class='add'>+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_DPHY_CNTL                                                                             0x212d</div><div class='add'>+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x212e</div><div class='add'>+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_SYM0                                                                             0x212f</div><div class='add'>+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_SYM1                                                                             0x2130</div><div class='add'>+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_SYM2                                                                             0x2131</div><div class='add'>+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x2132</div><div class='add'>+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x2133</div><div class='add'>+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x2134</div><div class='add'>+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_EN                                                                           0x2135</div><div class='add'>+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2136</div><div class='add'>+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2137</div><div class='add'>+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2138</div><div class='add'>+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2139</div><div class='add'>+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x213a</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x213b</div><div class='add'>+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_TU_CNTL                                                                               0x213c</div><div class='add'>+#define regDP0_DP_TU_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP0_DP_PIXEL_FORMAT_DB_CNTL                                                                  0x213d</div><div class='add'>+#define regDP0_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP0_DP_CP_LINK_VERIFICATION_PATTERN                                                          0x213e</div><div class='add'>+#define regDP0_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX                                                 2</div><div class='add'>+#define regDP0_DP_SEC_CNTL                                                                              0x2141</div><div class='add'>+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_SEC_CNTL1                                                                             0x2142</div><div class='add'>+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING1                                                                          0x2143</div><div class='add'>+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING2                                                                          0x2144</div><div class='add'>+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING3                                                                          0x2145</div><div class='add'>+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_FRAMING4                                                                          0x2146</div><div class='add'>+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP0_DP_SEC_AUD_N                                                                             0x2147</div><div class='add'>+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2148</div><div class='add'>+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_SEC_AUD_M                                                                             0x2149</div><div class='add'>+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x214a</div><div class='add'>+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x214b</div><div class='add'>+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x214c</div><div class='add'>+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x214d</div><div class='add'>+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_CP_MSE_STATUS                                                                         0x214e</div><div class='add'>+#define regDP0_DP_CP_MSE_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x214f</div><div class='add'>+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_SAT0                                                                              0x2150</div><div class='add'>+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSE_SAT1                                                                              0x2151</div><div class='add'>+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSE_SAT2                                                                              0x2152</div><div class='add'>+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x2153</div><div class='add'>+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x2154</div><div class='add'>+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x2155</div><div class='add'>+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x215a</div><div class='add'>+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x215b</div><div class='add'>+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x215d</div><div class='add'>+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x215e</div><div class='add'>+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x215f</div><div class='add'>+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_DPIA_SPARE                                                                            0x2160</div><div class='add'>+#define regDP0_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_HBLANK_CONTROL                                                                        0x2161</div><div class='add'>+#define regDP0_DP_HBLANK_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x2162</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x2163</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x2164</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x2165</div><div class='add'>+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP0_DP_MSO_CNTL                                                                              0x2166</div><div class='add'>+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP0_DP_MSO_CNTL1                                                                             0x2167</div><div class='add'>+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_STEER_FIFO_CNTL                                                                       0x2168</div><div class='add'>+#define regDP0_DP_STEER_FIFO_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP0_DP_SEC_CNTL2                                                                             0x2169</div><div class='add'>+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL3                                                                             0x216a</div><div class='add'>+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL4                                                                             0x216b</div><div class='add'>+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL5                                                                             0x216c</div><div class='add'>+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL6                                                                             0x216d</div><div class='add'>+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_SEC_CNTL7                                                                             0x216e</div><div class='add'>+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_DB_CNTL                                                                               0x216f</div><div class='add'>+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP0_DP_MSA_VBID_MISC                                                                         0x2170</div><div class='add'>+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x2171</div><div class='add'>+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_ALPM_CNTL                                                                             0x2173</div><div class='add'>+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_GSP8_CNTL                                                                             0x2174</div><div class='add'>+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_GSP9_CNTL                                                                             0x2175</div><div class='add'>+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP0_DP_GSP10_CNTL                                                                            0x2176</div><div class='add'>+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_GSP11_CNTL                                                                            0x2177</div><div class='add'>+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2178</div><div class='add'>+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL1                                                                    0x2179</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL2                                                                    0x217a</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL3                                                                    0x217b</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL4                                                                    0x217c</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL5                                                                    0x217d</div><div class='add'>+#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x217e</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x217f</div><div class='add'>+#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x2180</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x2181</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x2182</div><div class='add'>+#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL                                                     0x2183</div><div class='add'>+#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDIG0_DIG_FE_CNTL                                                                             0x2093</div><div class='add'>+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG0_DIG_FE_CLK_CNTL                                                                         0x2094</div><div class='add'>+#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG0_DIG_FE_EN_CNTL                                                                          0x2095</div><div class='add'>+#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2096</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x2097</div><div class='add'>+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x2098</div><div class='add'>+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_DIG_TEST_PATTERN                                                                        0x2099</div><div class='add'>+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x209a</div><div class='add'>+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL0                                                                          0x209b</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL1                                                                          0x209c</div><div class='add'>+#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x209d</div><div class='add'>+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_CONTROL                                                                            0x209e</div><div class='add'>+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG0_HDMI_STATUS                                                                             0x209f</div><div class='add'>+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x20a0</div><div class='add'>+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x20a1</div><div class='add'>+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x20a2</div><div class='add'>+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x20a3</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x20a4</div><div class='add'>+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x20a5</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x20a6</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20a7</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GC                                                                                 0x20a8</div><div class='add'>+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x20a9</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x20aa</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20ab</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20ac</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20ad</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20ae</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20af</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20b0</div><div class='add'>+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20b1</div><div class='add'>+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG0_HDMI_ACR_32_0                                                                           0x20b2</div><div class='add'>+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_32_1                                                                           0x20b3</div><div class='add'>+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_44_0                                                                           0x20b4</div><div class='add'>+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_44_1                                                                           0x20b5</div><div class='add'>+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_48_0                                                                           0x20b6</div><div class='add'>+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_48_1                                                                           0x20b7</div><div class='add'>+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20b8</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20b9</div><div class='add'>+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_AFMT_CNTL                                                                               0x20ba</div><div class='add'>+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG0_DIG_BE_CLK_CNTL                                                                         0x20bb</div><div class='add'>+#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG0_DIG_BE_CNTL                                                                             0x20bc</div><div class='add'>+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20bd</div><div class='add'>+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG0_HDCP_INT_CONTROL                                                                        0x20c0</div><div class='add'>+#define regDIG0_HDCP_INT_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDIG0_HDCP_LINK0_STATUS                                                                       0x20c1</div><div class='add'>+#define regDIG0_HDCP_LINK0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_HDCP_I2C_CONTROL_0                                                                      0x20c2</div><div class='add'>+#define regDIG0_HDCP_I2C_CONTROL_0_BASE_IDX                                                             2</div><div class='add'>+#define regDIG0_HDCP_I2C_CONTROL_1                                                                      0x20c3</div><div class='add'>+#define regDIG0_HDCP_I2C_CONTROL_1_BASE_IDX                                                             2</div><div class='add'>+#define regDIG0_TMDS_CNTL                                                                               0x20e4</div><div class='add'>+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20e5</div><div class='add'>+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20e6</div><div class='add'>+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20e7</div><div class='add'>+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20e8</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20e9</div><div class='add'>+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG0_TMDS_CTL_BITS                                                                           0x20eb</div><div class='add'>+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20ec</div><div class='add'>+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20ed</div><div class='add'>+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20ee</div><div class='add'>+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20ef</div><div class='add'>+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG0_DIG_VERSION                                                                             0x20f1</div><div class='add'>+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp1_dispdec</div><div class='add'>+// base address: 0x490</div><div class='add'>+#define regDP1_DP_LINK_CNTL                                                                             0x2242</div><div class='add'>+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2243</div><div class='add'>+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x2244</div><div class='add'>+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_CONFIG                                                                                0x2245</div><div class='add'>+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x2246</div><div class='add'>+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_STEER_FIFO                                                                            0x2247</div><div class='add'>+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_MSA_MISC                                                                              0x2248</div><div class='add'>+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x2249</div><div class='add'>+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_VID_TIMING                                                                            0x224a</div><div class='add'>+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_VID_N                                                                                 0x224b</div><div class='add'>+#define regDP1_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP1_DP_VID_M                                                                                 0x224c</div><div class='add'>+#define regDP1_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x224d</div><div class='add'>+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x224e</div><div class='add'>+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_VID_MSA_VBID                                                                          0x224f</div><div class='add'>+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2250</div><div class='add'>+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_DPHY_CNTL                                                                             0x2251</div><div class='add'>+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2252</div><div class='add'>+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_SYM0                                                                             0x2253</div><div class='add'>+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_SYM1                                                                             0x2254</div><div class='add'>+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_SYM2                                                                             0x2255</div><div class='add'>+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x2256</div><div class='add'>+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x2257</div><div class='add'>+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x2258</div><div class='add'>+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_EN                                                                           0x2259</div><div class='add'>+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x225a</div><div class='add'>+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x225b</div><div class='add'>+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x225c</div><div class='add'>+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x225d</div><div class='add'>+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x225e</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x225f</div><div class='add'>+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_TU_CNTL                                                                               0x2260</div><div class='add'>+#define regDP1_DP_TU_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP1_DP_PIXEL_FORMAT_DB_CNTL                                                                  0x2261</div><div class='add'>+#define regDP1_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP1_DP_CP_LINK_VERIFICATION_PATTERN                                                          0x2262</div><div class='add'>+#define regDP1_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX                                                 2</div><div class='add'>+#define regDP1_DP_SEC_CNTL                                                                              0x2265</div><div class='add'>+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_SEC_CNTL1                                                                             0x2266</div><div class='add'>+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING1                                                                          0x2267</div><div class='add'>+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING2                                                                          0x2268</div><div class='add'>+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING3                                                                          0x2269</div><div class='add'>+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_FRAMING4                                                                          0x226a</div><div class='add'>+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP1_DP_SEC_AUD_N                                                                             0x226b</div><div class='add'>+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x226c</div><div class='add'>+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_SEC_AUD_M                                                                             0x226d</div><div class='add'>+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x226e</div><div class='add'>+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x226f</div><div class='add'>+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2270</div><div class='add'>+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2271</div><div class='add'>+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_CP_MSE_STATUS                                                                         0x2272</div><div class='add'>+#define regDP1_DP_CP_MSE_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2273</div><div class='add'>+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_SAT0                                                                              0x2274</div><div class='add'>+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSE_SAT1                                                                              0x2275</div><div class='add'>+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSE_SAT2                                                                              0x2276</div><div class='add'>+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x2277</div><div class='add'>+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x2278</div><div class='add'>+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x2279</div><div class='add'>+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x227e</div><div class='add'>+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x227f</div><div class='add'>+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2281</div><div class='add'>+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2282</div><div class='add'>+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2283</div><div class='add'>+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_DPIA_SPARE                                                                            0x2284</div><div class='add'>+#define regDP1_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_HBLANK_CONTROL                                                                        0x2285</div><div class='add'>+#define regDP1_DP_HBLANK_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x2286</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x2287</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x2288</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x2289</div><div class='add'>+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP1_DP_MSO_CNTL                                                                              0x228a</div><div class='add'>+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP1_DP_MSO_CNTL1                                                                             0x228b</div><div class='add'>+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_STEER_FIFO_CNTL                                                                       0x228c</div><div class='add'>+#define regDP1_DP_STEER_FIFO_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP1_DP_SEC_CNTL2                                                                             0x228d</div><div class='add'>+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL3                                                                             0x228e</div><div class='add'>+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL4                                                                             0x228f</div><div class='add'>+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL5                                                                             0x2290</div><div class='add'>+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL6                                                                             0x2291</div><div class='add'>+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_SEC_CNTL7                                                                             0x2292</div><div class='add'>+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_DB_CNTL                                                                               0x2293</div><div class='add'>+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP1_DP_MSA_VBID_MISC                                                                         0x2294</div><div class='add'>+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x2295</div><div class='add'>+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_ALPM_CNTL                                                                             0x2297</div><div class='add'>+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_GSP8_CNTL                                                                             0x2298</div><div class='add'>+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_GSP9_CNTL                                                                             0x2299</div><div class='add'>+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP1_DP_GSP10_CNTL                                                                            0x229a</div><div class='add'>+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_GSP11_CNTL                                                                            0x229b</div><div class='add'>+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x229c</div><div class='add'>+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL1                                                                    0x229d</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL2                                                                    0x229e</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL3                                                                    0x229f</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL4                                                                    0x22a0</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL5                                                                    0x22a1</div><div class='add'>+#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x22a2</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x22a3</div><div class='add'>+#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x22a4</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x22a5</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x22a6</div><div class='add'>+#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL                                                     0x22a7</div><div class='add'>+#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_dispdec</div><div class='add'>+// base address: 0x490</div><div class='add'>+#define regDIG1_DIG_FE_CNTL                                                                             0x21b7</div><div class='add'>+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG1_DIG_FE_CLK_CNTL                                                                         0x21b8</div><div class='add'>+#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG1_DIG_FE_EN_CNTL                                                                          0x21b9</div><div class='add'>+#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x21ba</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x21bb</div><div class='add'>+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x21bc</div><div class='add'>+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_DIG_TEST_PATTERN                                                                        0x21bd</div><div class='add'>+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x21be</div><div class='add'>+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL0                                                                          0x21bf</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL1                                                                          0x21c0</div><div class='add'>+#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x21c1</div><div class='add'>+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_CONTROL                                                                            0x21c2</div><div class='add'>+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG1_HDMI_STATUS                                                                             0x21c3</div><div class='add'>+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x21c4</div><div class='add'>+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x21c5</div><div class='add'>+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x21c6</div><div class='add'>+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x21c7</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x21c8</div><div class='add'>+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x21c9</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x21ca</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21cb</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GC                                                                                 0x21cc</div><div class='add'>+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x21cd</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x21ce</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21cf</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21d0</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21d1</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21d2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21d3</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21d4</div><div class='add'>+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21d5</div><div class='add'>+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG1_HDMI_ACR_32_0                                                                           0x21d6</div><div class='add'>+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_32_1                                                                           0x21d7</div><div class='add'>+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_44_0                                                                           0x21d8</div><div class='add'>+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_44_1                                                                           0x21d9</div><div class='add'>+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_48_0                                                                           0x21da</div><div class='add'>+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_48_1                                                                           0x21db</div><div class='add'>+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21dc</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21dd</div><div class='add'>+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_AFMT_CNTL                                                                               0x21de</div><div class='add'>+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG1_DIG_BE_CLK_CNTL                                                                         0x21df</div><div class='add'>+#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG1_DIG_BE_CNTL                                                                             0x21e0</div><div class='add'>+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21e1</div><div class='add'>+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG1_HDCP_INT_CONTROL                                                                        0x21e4</div><div class='add'>+#define regDIG1_HDCP_INT_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDIG1_HDCP_I2C_CONTROL_0                                                                      0x21e6</div><div class='add'>+#define regDIG1_HDCP_I2C_CONTROL_0_BASE_IDX                                                             2</div><div class='add'>+#define regDIG1_HDCP_I2C_CONTROL_1                                                                      0x21e7</div><div class='add'>+#define regDIG1_HDCP_I2C_CONTROL_1_BASE_IDX                                                             2</div><div class='add'>+#define regDIG1_TMDS_CNTL                                                                               0x2208</div><div class='add'>+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x2209</div><div class='add'>+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x220a</div><div class='add'>+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x220b</div><div class='add'>+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x220c</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x220d</div><div class='add'>+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG1_TMDS_CTL_BITS                                                                           0x220f</div><div class='add'>+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x2210</div><div class='add'>+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2211</div><div class='add'>+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x2212</div><div class='add'>+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x2213</div><div class='add'>+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG1_DIG_VERSION                                                                             0x2215</div><div class='add'>+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp2_dispdec</div><div class='add'>+// base address: 0x920</div><div class='add'>+#define regDP2_DP_LINK_CNTL                                                                             0x2366</div><div class='add'>+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2367</div><div class='add'>+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x2368</div><div class='add'>+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_CONFIG                                                                                0x2369</div><div class='add'>+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x236a</div><div class='add'>+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_STEER_FIFO                                                                            0x236b</div><div class='add'>+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_MSA_MISC                                                                              0x236c</div><div class='add'>+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x236d</div><div class='add'>+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_VID_TIMING                                                                            0x236e</div><div class='add'>+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_VID_N                                                                                 0x236f</div><div class='add'>+#define regDP2_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP2_DP_VID_M                                                                                 0x2370</div><div class='add'>+#define regDP2_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2371</div><div class='add'>+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2372</div><div class='add'>+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_VID_MSA_VBID                                                                          0x2373</div><div class='add'>+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2374</div><div class='add'>+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_DPHY_CNTL                                                                             0x2375</div><div class='add'>+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2376</div><div class='add'>+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_SYM0                                                                             0x2377</div><div class='add'>+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_SYM1                                                                             0x2378</div><div class='add'>+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_SYM2                                                                             0x2379</div><div class='add'>+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x237a</div><div class='add'>+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x237b</div><div class='add'>+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x237c</div><div class='add'>+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_EN                                                                           0x237d</div><div class='add'>+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x237e</div><div class='add'>+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x237f</div><div class='add'>+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2380</div><div class='add'>+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2381</div><div class='add'>+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2382</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2383</div><div class='add'>+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_TU_CNTL                                                                               0x2384</div><div class='add'>+#define regDP2_DP_TU_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP2_DP_PIXEL_FORMAT_DB_CNTL                                                                  0x2385</div><div class='add'>+#define regDP2_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP2_DP_CP_LINK_VERIFICATION_PATTERN                                                          0x2386</div><div class='add'>+#define regDP2_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX                                                 2</div><div class='add'>+#define regDP2_DP_SEC_CNTL                                                                              0x2389</div><div class='add'>+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_SEC_CNTL1                                                                             0x238a</div><div class='add'>+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING1                                                                          0x238b</div><div class='add'>+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING2                                                                          0x238c</div><div class='add'>+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING3                                                                          0x238d</div><div class='add'>+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_FRAMING4                                                                          0x238e</div><div class='add'>+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP2_DP_SEC_AUD_N                                                                             0x238f</div><div class='add'>+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2390</div><div class='add'>+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_SEC_AUD_M                                                                             0x2391</div><div class='add'>+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2392</div><div class='add'>+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2393</div><div class='add'>+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2394</div><div class='add'>+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2395</div><div class='add'>+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_CP_MSE_STATUS                                                                         0x2396</div><div class='add'>+#define regDP2_DP_CP_MSE_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2397</div><div class='add'>+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_SAT0                                                                              0x2398</div><div class='add'>+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSE_SAT1                                                                              0x2399</div><div class='add'>+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSE_SAT2                                                                              0x239a</div><div class='add'>+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x239b</div><div class='add'>+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x239c</div><div class='add'>+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x239d</div><div class='add'>+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x23a2</div><div class='add'>+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x23a3</div><div class='add'>+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x23a5</div><div class='add'>+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x23a6</div><div class='add'>+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x23a7</div><div class='add'>+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_DPIA_SPARE                                                                            0x23a8</div><div class='add'>+#define regDP2_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_HBLANK_CONTROL                                                                        0x23a9</div><div class='add'>+#define regDP2_DP_HBLANK_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x23aa</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x23ab</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x23ac</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x23ad</div><div class='add'>+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP2_DP_MSO_CNTL                                                                              0x23ae</div><div class='add'>+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP2_DP_MSO_CNTL1                                                                             0x23af</div><div class='add'>+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_STEER_FIFO_CNTL                                                                       0x23b0</div><div class='add'>+#define regDP2_DP_STEER_FIFO_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP2_DP_SEC_CNTL2                                                                             0x23b1</div><div class='add'>+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL3                                                                             0x23b2</div><div class='add'>+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL4                                                                             0x23b3</div><div class='add'>+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL5                                                                             0x23b4</div><div class='add'>+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL6                                                                             0x23b5</div><div class='add'>+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_SEC_CNTL7                                                                             0x23b6</div><div class='add'>+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_DB_CNTL                                                                               0x23b7</div><div class='add'>+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP2_DP_MSA_VBID_MISC                                                                         0x23b8</div><div class='add'>+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x23b9</div><div class='add'>+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_ALPM_CNTL                                                                             0x23bb</div><div class='add'>+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_GSP8_CNTL                                                                             0x23bc</div><div class='add'>+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_GSP9_CNTL                                                                             0x23bd</div><div class='add'>+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP2_DP_GSP10_CNTL                                                                            0x23be</div><div class='add'>+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_GSP11_CNTL                                                                            0x23bf</div><div class='add'>+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x23c0</div><div class='add'>+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL1                                                                    0x23c1</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL2                                                                    0x23c2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL3                                                                    0x23c3</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL4                                                                    0x23c4</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL5                                                                    0x23c5</div><div class='add'>+#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x23c6</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x23c7</div><div class='add'>+#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x23c8</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x23c9</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x23ca</div><div class='add'>+#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL                                                     0x23cb</div><div class='add'>+#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_dispdec</div><div class='add'>+// base address: 0x920</div><div class='add'>+#define regDIG2_DIG_FE_CNTL                                                                             0x22db</div><div class='add'>+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG2_DIG_FE_CLK_CNTL                                                                         0x22dc</div><div class='add'>+#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG2_DIG_FE_EN_CNTL                                                                          0x22dd</div><div class='add'>+#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x22de</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x22df</div><div class='add'>+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x22e0</div><div class='add'>+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_DIG_TEST_PATTERN                                                                        0x22e1</div><div class='add'>+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x22e2</div><div class='add'>+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL0                                                                          0x22e3</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL1                                                                          0x22e4</div><div class='add'>+#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x22e5</div><div class='add'>+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_CONTROL                                                                            0x22e6</div><div class='add'>+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG2_HDMI_STATUS                                                                             0x22e7</div><div class='add'>+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x22e8</div><div class='add'>+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x22e9</div><div class='add'>+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x22ea</div><div class='add'>+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x22eb</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x22ec</div><div class='add'>+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x22ed</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x22ee</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22ef</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GC                                                                                 0x22f0</div><div class='add'>+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x22f1</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x22f2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22f3</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22f4</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22f5</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22f6</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22f7</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22f8</div><div class='add'>+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22f9</div><div class='add'>+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG2_HDMI_ACR_32_0                                                                           0x22fa</div><div class='add'>+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_32_1                                                                           0x22fb</div><div class='add'>+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_44_0                                                                           0x22fc</div><div class='add'>+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_44_1                                                                           0x22fd</div><div class='add'>+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_48_0                                                                           0x22fe</div><div class='add'>+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ff</div><div class='add'>+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x2300</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x2301</div><div class='add'>+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_AFMT_CNTL                                                                               0x2302</div><div class='add'>+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG2_DIG_BE_CLK_CNTL                                                                         0x2303</div><div class='add'>+#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG2_DIG_BE_CNTL                                                                             0x2304</div><div class='add'>+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x2305</div><div class='add'>+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG2_HDCP_INT_CONTROL                                                                        0x2308</div><div class='add'>+#define regDIG2_HDCP_INT_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDIG2_HDCP_I2C_CONTROL_0                                                                      0x230a</div><div class='add'>+#define regDIG2_HDCP_I2C_CONTROL_0_BASE_IDX                                                             2</div><div class='add'>+#define regDIG2_HDCP_I2C_CONTROL_1                                                                      0x230b</div><div class='add'>+#define regDIG2_HDCP_I2C_CONTROL_1_BASE_IDX                                                             2</div><div class='add'>+#define regDIG2_TMDS_CNTL                                                                               0x232c</div><div class='add'>+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x232d</div><div class='add'>+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x232e</div><div class='add'>+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x232f</div><div class='add'>+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2330</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2331</div><div class='add'>+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG2_TMDS_CTL_BITS                                                                           0x2333</div><div class='add'>+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x2334</div><div class='add'>+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2335</div><div class='add'>+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x2336</div><div class='add'>+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x2337</div><div class='add'>+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG2_DIG_VERSION                                                                             0x2339</div><div class='add'>+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp3_dispdec</div><div class='add'>+// base address: 0xdb0</div><div class='add'>+#define regDP3_DP_LINK_CNTL                                                                             0x248a</div><div class='add'>+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_PIXEL_FORMAT                                                                          0x248b</div><div class='add'>+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x248c</div><div class='add'>+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_CONFIG                                                                                0x248d</div><div class='add'>+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2</div><div class='add'>+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x248e</div><div class='add'>+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_STEER_FIFO                                                                            0x248f</div><div class='add'>+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_MSA_MISC                                                                              0x2490</div><div class='add'>+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x2491</div><div class='add'>+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_VID_TIMING                                                                            0x2492</div><div class='add'>+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_VID_N                                                                                 0x2493</div><div class='add'>+#define regDP3_DP_VID_N_BASE_IDX                                                                        2</div><div class='add'>+#define regDP3_DP_VID_M                                                                                 0x2494</div><div class='add'>+#define regDP3_DP_VID_M_BASE_IDX                                                                        2</div><div class='add'>+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2495</div><div class='add'>+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2496</div><div class='add'>+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_VID_MSA_VBID                                                                          0x2497</div><div class='add'>+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2498</div><div class='add'>+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_DPHY_CNTL                                                                             0x2499</div><div class='add'>+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x249a</div><div class='add'>+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_SYM0                                                                             0x249b</div><div class='add'>+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_SYM1                                                                             0x249c</div><div class='add'>+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_SYM2                                                                             0x249d</div><div class='add'>+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x249e</div><div class='add'>+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x249f</div><div class='add'>+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x24a0</div><div class='add'>+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_EN                                                                           0x24a1</div><div class='add'>+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x24a2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x24a3</div><div class='add'>+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x24a4</div><div class='add'>+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x24a5</div><div class='add'>+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x24a6</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x24a7</div><div class='add'>+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_TU_CNTL                                                                               0x24a8</div><div class='add'>+#define regDP3_DP_TU_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP3_DP_PIXEL_FORMAT_DB_CNTL                                                                  0x24a9</div><div class='add'>+#define regDP3_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP3_DP_CP_LINK_VERIFICATION_PATTERN                                                          0x24aa</div><div class='add'>+#define regDP3_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX                                                 2</div><div class='add'>+#define regDP3_DP_SEC_CNTL                                                                              0x24ad</div><div class='add'>+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_SEC_CNTL1                                                                             0x24ae</div><div class='add'>+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING1                                                                          0x24af</div><div class='add'>+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING2                                                                          0x24b0</div><div class='add'>+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING3                                                                          0x24b1</div><div class='add'>+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING4                                                                          0x24b2</div><div class='add'>+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2</div><div class='add'>+#define regDP3_DP_SEC_AUD_N                                                                             0x24b3</div><div class='add'>+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x24b4</div><div class='add'>+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_SEC_AUD_M                                                                             0x24b5</div><div class='add'>+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x24b6</div><div class='add'>+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x24b7</div><div class='add'>+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x24b8</div><div class='add'>+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x24b9</div><div class='add'>+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_CP_MSE_STATUS                                                                         0x24ba</div><div class='add'>+#define regDP3_DP_CP_MSE_STATUS_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x24bb</div><div class='add'>+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_SAT0                                                                              0x24bc</div><div class='add'>+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSE_SAT1                                                                              0x24bd</div><div class='add'>+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSE_SAT2                                                                              0x24be</div><div class='add'>+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x24bf</div><div class='add'>+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2</div><div class='add'>+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x24c0</div><div class='add'>+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x24c1</div><div class='add'>+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x24c6</div><div class='add'>+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x24c7</div><div class='add'>+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x24c9</div><div class='add'>+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x24ca</div><div class='add'>+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x24cb</div><div class='add'>+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_DPIA_SPARE                                                                            0x24cc</div><div class='add'>+#define regDP3_DP_DPIA_SPARE_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_HBLANK_CONTROL                                                                        0x24cd</div><div class='add'>+#define regDP3_DP_HBLANK_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x24ce</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x24cf</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x24d0</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x24d1</div><div class='add'>+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2</div><div class='add'>+#define regDP3_DP_MSO_CNTL                                                                              0x24d2</div><div class='add'>+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDP3_DP_MSO_CNTL1                                                                             0x24d3</div><div class='add'>+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_STEER_FIFO_CNTL                                                                       0x24d4</div><div class='add'>+#define regDP3_DP_STEER_FIFO_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regDP3_DP_SEC_CNTL2                                                                             0x24d5</div><div class='add'>+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL3                                                                             0x24d6</div><div class='add'>+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL4                                                                             0x24d7</div><div class='add'>+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL5                                                                             0x24d8</div><div class='add'>+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL6                                                                             0x24d9</div><div class='add'>+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_SEC_CNTL7                                                                             0x24da</div><div class='add'>+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_DB_CNTL                                                                               0x24db</div><div class='add'>+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDP3_DP_MSA_VBID_MISC                                                                         0x24dc</div><div class='add'>+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2</div><div class='add'>+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x24dd</div><div class='add'>+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_ALPM_CNTL                                                                             0x24df</div><div class='add'>+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_GSP8_CNTL                                                                             0x24e0</div><div class='add'>+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_GSP9_CNTL                                                                             0x24e1</div><div class='add'>+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDP3_DP_GSP10_CNTL                                                                            0x24e2</div><div class='add'>+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_GSP11_CNTL                                                                            0x24e3</div><div class='add'>+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x24e4</div><div class='add'>+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL1                                                                    0x24e5</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL2                                                                    0x24e6</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL3                                                                    0x24e7</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL4                                                                    0x24e8</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL5                                                                    0x24e9</div><div class='add'>+#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX                                                           2</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS                                                            0x24ea</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX                                                   2</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL                                                           0x24eb</div><div class='add'>+#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0                                                             0x24ec</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1                                                             0x24ed</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL                                                             0x24ee</div><div class='add'>+#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX                                                    2</div><div class='add'>+#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL                                                     0x24ef</div><div class='add'>+#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                            2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_dispdec</div><div class='add'>+// base address: 0xdb0</div><div class='add'>+#define regDIG3_DIG_FE_CNTL                                                                             0x23ff</div><div class='add'>+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG3_DIG_FE_CLK_CNTL                                                                         0x2400</div><div class='add'>+#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG3_DIG_FE_EN_CNTL                                                                          0x2401</div><div class='add'>+#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2402</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x2403</div><div class='add'>+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2</div><div class='add'>+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x2404</div><div class='add'>+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_DIG_TEST_PATTERN                                                                        0x2405</div><div class='add'>+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2</div><div class='add'>+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2406</div><div class='add'>+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL0                                                                          0x2407</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL1                                                                          0x2408</div><div class='add'>+#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2409</div><div class='add'>+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_CONTROL                                                                            0x240a</div><div class='add'>+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2</div><div class='add'>+#define regDIG3_HDMI_STATUS                                                                             0x240b</div><div class='add'>+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x240c</div><div class='add'>+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2</div><div class='add'>+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x240d</div><div class='add'>+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x240e</div><div class='add'>+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x240f</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2410</div><div class='add'>+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2411</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x2412</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x2413</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GC                                                                                 0x2414</div><div class='add'>+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2415</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2416</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2417</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2418</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x2419</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x241a</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x241b</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x241c</div><div class='add'>+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2</div><div class='add'>+#define regDIG3_HDMI_DB_CONTROL                                                                         0x241d</div><div class='add'>+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG3_HDMI_ACR_32_0                                                                           0x241e</div><div class='add'>+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_32_1                                                                           0x241f</div><div class='add'>+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_44_0                                                                           0x2420</div><div class='add'>+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_44_1                                                                           0x2421</div><div class='add'>+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_48_0                                                                           0x2422</div><div class='add'>+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_48_1                                                                           0x2423</div><div class='add'>+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x2424</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x2425</div><div class='add'>+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_AFMT_CNTL                                                                               0x2426</div><div class='add'>+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG3_DIG_BE_CLK_CNTL                                                                         0x2427</div><div class='add'>+#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX                                                                2</div><div class='add'>+#define regDIG3_DIG_BE_CNTL                                                                             0x2428</div><div class='add'>+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x2429</div><div class='add'>+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2</div><div class='add'>+#define regDIG3_HDCP_INT_CONTROL                                                                        0x242c</div><div class='add'>+#define regDIG3_HDCP_INT_CONTROL_BASE_IDX                                                               2</div><div class='add'>+#define regDIG3_HDCP_I2C_CONTROL_0                                                                      0x242e</div><div class='add'>+#define regDIG3_HDCP_I2C_CONTROL_0_BASE_IDX                                                             2</div><div class='add'>+#define regDIG3_HDCP_I2C_CONTROL_1                                                                      0x242f</div><div class='add'>+#define regDIG3_HDCP_I2C_CONTROL_1_BASE_IDX                                                             2</div><div class='add'>+#define regDIG3_TMDS_CNTL                                                                               0x2450</div><div class='add'>+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2</div><div class='add'>+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x2451</div><div class='add'>+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2</div><div class='add'>+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x2452</div><div class='add'>+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2</div><div class='add'>+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x2453</div><div class='add'>+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x2454</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x2455</div><div class='add'>+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2</div><div class='add'>+#define regDIG3_TMDS_CTL_BITS                                                                           0x2457</div><div class='add'>+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x2458</div><div class='add'>+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x2459</div><div class='add'>+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2</div><div class='add'>+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x245a</div><div class='add'>+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x245b</div><div class='add'>+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIG3_DIG_VERSION                                                                             0x245d</div><div class='add'>+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x154cc</div><div class='add'>+#define regAFMT0_AFMT_ACP                                                                               0x2073</div><div class='add'>+#define regAFMT0_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074</div><div class='add'>+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT0_AFMT_60958_0                                                                           0x2078</div><div class='add'>+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT0_AFMT_60958_1                                                                           0x2079</div><div class='add'>+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e</div><div class='add'>+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT0_AFMT_60958_2                                                                           0x207f</div><div class='add'>+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT0_AFMT_STATUS                                                                            0x2081</div><div class='add'>+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083</div><div class='add'>+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084</div><div class='add'>+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL                                                                0x2086</div><div class='add'>+#define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087</div><div class='add'>+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x1595c</div><div class='add'>+#define regAFMT1_AFMT_ACP                                                                               0x2197</div><div class='add'>+#define regAFMT1_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2198</div><div class='add'>+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2199</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x219a</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x219b</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT1_AFMT_60958_0                                                                           0x219c</div><div class='add'>+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT1_AFMT_60958_1                                                                           0x219d</div><div class='add'>+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x219e</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x219f</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x21a0</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x21a1</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x21a2</div><div class='add'>+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT1_AFMT_60958_2                                                                           0x21a3</div><div class='add'>+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x21a4</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT1_AFMT_STATUS                                                                            0x21a5</div><div class='add'>+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x21a6</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x21a7</div><div class='add'>+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x21a8</div><div class='add'>+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x21a9</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL                                                                0x21aa</div><div class='add'>+#define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT1_AFMT_MEM_PWR                                                                           0x21ab</div><div class='add'>+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x15dec</div><div class='add'>+#define regAFMT2_AFMT_ACP                                                                               0x22bb</div><div class='add'>+#define regAFMT2_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x22bc</div><div class='add'>+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x22bd</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x22be</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x22bf</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT2_AFMT_60958_0                                                                           0x22c0</div><div class='add'>+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT2_AFMT_60958_1                                                                           0x22c1</div><div class='add'>+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x22c2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x22c3</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x22c4</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x22c5</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x22c6</div><div class='add'>+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT2_AFMT_60958_2                                                                           0x22c7</div><div class='add'>+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x22c8</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT2_AFMT_STATUS                                                                            0x22c9</div><div class='add'>+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x22ca</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x22cb</div><div class='add'>+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x22cc</div><div class='add'>+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x22cd</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL                                                                0x22ce</div><div class='add'>+#define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT2_AFMT_MEM_PWR                                                                           0x22cf</div><div class='add'>+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x1627c</div><div class='add'>+#define regAFMT3_AFMT_ACP                                                                               0x23df</div><div class='add'>+#define regAFMT3_AFMT_ACP_BASE_IDX                                                                      2</div><div class='add'>+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x23e0</div><div class='add'>+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x23e1</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x23e2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x23e3</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2</div><div class='add'>+#define regAFMT3_AFMT_60958_0                                                                           0x23e4</div><div class='add'>+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT3_AFMT_60958_1                                                                           0x23e5</div><div class='add'>+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x23e6</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x23e7</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x23e8</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x23e9</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x23ea</div><div class='add'>+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2</div><div class='add'>+#define regAFMT3_AFMT_60958_2                                                                           0x23eb</div><div class='add'>+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x23ec</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT3_AFMT_STATUS                                                                            0x23ed</div><div class='add'>+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x23ee</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x23ef</div><div class='add'>+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x23f0</div><div class='add'>+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x23f1</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL                                                                0x23f2</div><div class='add'>+#define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX                                                       2</div><div class='add'>+#define regAFMT3_AFMT_MEM_PWR                                                                           0x23f3</div><div class='add'>+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_dme_dme_dispdec</div><div class='add'>+// base address: 0x15544</div><div class='add'>+#define regDME0_DME_CONTROL                                                                             0x2091</div><div class='add'>+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME0_DME_MEMORY_CONTROL                                                                      0x2092</div><div class='add'>+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x154a0</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069</div><div class='add'>+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a</div><div class='add'>+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b</div><div class='add'>+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c</div><div class='add'>+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG0_VPG_MEM_PWR                                                                             0x206d</div><div class='add'>+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f</div><div class='add'>+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071</div><div class='add'>+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_dme_dme_dispdec</div><div class='add'>+// base address: 0x159d4</div><div class='add'>+#define regDME1_DME_CONTROL                                                                             0x21b5</div><div class='add'>+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME1_DME_MEMORY_CONTROL                                                                      0x21b6</div><div class='add'>+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x15930</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x218c</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x218d</div><div class='add'>+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x218e</div><div class='add'>+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x218f</div><div class='add'>+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x2190</div><div class='add'>+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG1_VPG_MEM_PWR                                                                             0x2191</div><div class='add'>+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x2192</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x2193</div><div class='add'>+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2194</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2195</div><div class='add'>+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_dme_dme_dispdec</div><div class='add'>+// base address: 0x15e64</div><div class='add'>+#define regDME2_DME_CONTROL                                                                             0x22d9</div><div class='add'>+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME2_DME_MEMORY_CONTROL                                                                      0x22da</div><div class='add'>+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x15dc0</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x22b0</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x22b1</div><div class='add'>+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x22b2</div><div class='add'>+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x22b3</div><div class='add'>+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x22b4</div><div class='add'>+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG2_VPG_MEM_PWR                                                                             0x22b5</div><div class='add'>+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x22b6</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x22b7</div><div class='add'>+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO0                                                                          0x22b8</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO1                                                                          0x22b9</div><div class='add'>+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_dme_dme_dispdec</div><div class='add'>+// base address: 0x162f4</div><div class='add'>+#define regDME3_DME_CONTROL                                                                             0x23fd</div><div class='add'>+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME3_DME_MEMORY_CONTROL                                                                      0x23fe</div><div class='add'>+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x16250</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x23d4</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x23d5</div><div class='add'>+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x23d6</div><div class='add'>+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x23d7</div><div class='add'>+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x23d8</div><div class='add'>+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG3_VPG_MEM_PWR                                                                             0x23d9</div><div class='add'>+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x23da</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x23db</div><div class='add'>+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO0                                                                          0x23dc</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO1                                                                          0x23dd</div><div class='add'>+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_hdcp1kp_dispdec</div><div class='add'>+// base address: 0x14cd8</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dout_i2c_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_I2C_CONTROL                                                                               0x1e98</div><div class='add'>+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_I2C_ARBITRATION                                                                           0x1e99</div><div class='add'>+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a</div><div class='add'>+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDC_I2C_SW_STATUS                                                                             0x1e9b</div><div class='add'>+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c</div><div class='add'>+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d</div><div class='add'>+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e</div><div class='add'>+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f</div><div class='add'>+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0</div><div class='add'>+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC6_HW_STATUS                                                                        0x1ea1</div><div class='add'>+#define regDC_I2C_DDC6_HW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2</div><div class='add'>+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3</div><div class='add'>+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4</div><div class='add'>+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5</div><div class='add'>+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6</div><div class='add'>+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7</div><div class='add'>+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8</div><div class='add'>+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9</div><div class='add'>+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa</div><div class='add'>+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab</div><div class='add'>+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC6_SPEED                                                                            0x1eac</div><div class='add'>+#define regDC_I2C_DDC6_SPEED_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_DDC6_SETUP                                                                            0x1ead</div><div class='add'>+#define regDC_I2C_DDC6_SETUP_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_I2C_TRANSACTION0                                                                          0x1eae</div><div class='add'>+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf</div><div class='add'>+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0</div><div class='add'>+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1</div><div class='add'>+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_DATA                                                                                  0x1eb2</div><div class='add'>+#define regDC_I2C_DATA_BASE_IDX                                                                         2</div><div class='add'>+#define regDC_I2C_DDCVGA_HW_STATUS                                                                      0x1eb3</div><div class='add'>+#define regDC_I2C_DDCVGA_HW_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regDC_I2C_DDCVGA_SPEED                                                                          0x1eb4</div><div class='add'>+#define regDC_I2C_DDCVGA_SPEED_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_DDCVGA_SETUP                                                                          0x1eb5</div><div class='add'>+#define regDC_I2C_DDCVGA_SETUP_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6</div><div class='add'>+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2</div><div class='add'>+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7</div><div class='add'>+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dio_misc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDIO_DCN_STATUS                                                                               0x1ec3</div><div class='add'>+#define regDIO_DCN_STATUS_BASE_IDX                                                                      2</div><div class='add'>+#define regDIO_SCRATCH0                                                                                 0x1eca</div><div class='add'>+#define regDIO_SCRATCH0_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH1                                                                                 0x1ecb</div><div class='add'>+#define regDIO_SCRATCH1_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH2                                                                                 0x1ecc</div><div class='add'>+#define regDIO_SCRATCH2_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH3                                                                                 0x1ecd</div><div class='add'>+#define regDIO_SCRATCH3_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH4                                                                                 0x1ece</div><div class='add'>+#define regDIO_SCRATCH4_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH5                                                                                 0x1ecf</div><div class='add'>+#define regDIO_SCRATCH5_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH6                                                                                 0x1ed0</div><div class='add'>+#define regDIO_SCRATCH6_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_SCRATCH7                                                                                 0x1ed1</div><div class='add'>+#define regDIO_SCRATCH7_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS                                                          0x1ed3</div><div class='add'>+#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd</div><div class='add'>+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2</div><div class='add'>+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede</div><div class='add'>+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2</div><div class='add'>+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf</div><div class='add'>+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2</div><div class='add'>+#define regDIO_CLK_CNTL                                                                                 0x1ee0</div><div class='add'>+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4</div><div class='add'>+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDIO_STEREOSYNC_SEL                                                                           0x1eea</div><div class='add'>+#define regDIO_STEREOSYNC_SEL_BASE_IDX                                                                  2</div><div class='add'>+#define regDIO_SOFT_RESET                                                                               0x1eed</div><div class='add'>+#define regDIO_SOFT_RESET_BASE_IDX                                                                      2</div><div class='add'>+#define regHDCP_CLK_STATUS                                                                              0x1ef4</div><div class='add'>+#define regHDCP_CLK_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff</div><div class='add'>+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00</div><div class='add'>+#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2</div><div class='add'>+#define regDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01</div><div class='add'>+#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2</div><div class='add'>+#define regDIO_STATUS                                                                                   0x1f02</div><div class='add'>+#define regDIO_STATUS_BASE_IDX                                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig_stream_mapper_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDIG0_STREAM_MAPPER_CONTROL                                                                   0x1f0d</div><div class='add'>+#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG1_STREAM_MAPPER_CONTROL                                                                   0x1f0e</div><div class='add'>+#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG2_STREAM_MAPPER_CONTROL                                                                   0x1f0f</div><div class='add'>+#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG3_STREAM_MAPPER_CONTROL                                                                   0x1f10</div><div class='add'>+#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG4_STREAM_MAPPER_CONTROL                                                                   0x1f11</div><div class='add'>+#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG5_STREAM_MAPPER_CONTROL                                                                   0x1f12</div><div class='add'>+#define regDIG5_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDIG6_STREAM_MAPPER_CONTROL                                                                   0x1f13</div><div class='add'>+#define regDIG6_STREAM_MAPPER_CONTROL_BASE_IDX                                                          2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GENERICA                                                                                  0x2868</div><div class='add'>+#define regDC_GENERICA_BASE_IDX                                                                         2</div><div class='add'>+#define regDC_GENERICB                                                                                  0x2869</div><div class='add'>+#define regDC_GENERICB_BASE_IDX                                                                         2</div><div class='add'>+#define regDCIO_CLOCK_CNTL                                                                              0x286a</div><div class='add'>+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_REF_CLK_CNTL                                                                              0x286b</div><div class='add'>+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2</div><div class='add'>+#define regUNIPHYA_LINK_CNTL                                                                            0x286d</div><div class='add'>+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e</div><div class='add'>+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYB_LINK_CNTL                                                                            0x286f</div><div class='add'>+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870</div><div class='add'>+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYC_LINK_CNTL                                                                            0x2871</div><div class='add'>+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872</div><div class='add'>+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYD_LINK_CNTL                                                                            0x2873</div><div class='add'>+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874</div><div class='add'>+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYE_LINK_CNTL                                                                            0x2875</div><div class='add'>+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876</div><div class='add'>+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYF_LINK_CNTL                                                                            0x2877</div><div class='add'>+#define regUNIPHYF_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYF_CHANNEL_XBAR_CNTL                                                                    0x2878</div><div class='add'>+#define regUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regUNIPHYG_LINK_CNTL                                                                            0x2879</div><div class='add'>+#define regUNIPHYG_LINK_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regUNIPHYG_CHANNEL_XBAR_CNTL                                                                    0x287a</div><div class='add'>+#define regUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDCIO_WRCMD_DELAY                                                                             0x287e</div><div class='add'>+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_PINSTRAPS                                                                                 0x2880</div><div class='add'>+#define regDC_PINSTRAPS_BASE_IDX                                                                        2</div><div class='add'>+#define regCC_DC_MISC_STRAPS                                                                            0x2881</div><div class='add'>+#define regCC_DC_MISC_STRAPS_BASE_IDX                                                                   2</div><div class='add'>+#define regDCIO_SPARE                                                                                   0x2882</div><div class='add'>+#define regDCIO_SPARE_BASE_IDX                                                                          2</div><div class='add'>+#define regINTERCEPT_STATE                                                                              0x2884</div><div class='add'>+#define regINTERCEPT_STATE_BASE_IDX                                                                     2</div><div class='add'>+#define regDCIO_PATTERN_GEN_PAT                                                                         0x2886</div><div class='add'>+#define regDCIO_PATTERN_GEN_PAT_BASE_IDX                                                                2</div><div class='add'>+#define regDCIO_PATTERN_GEN_EN                                                                          0x2887</div><div class='add'>+#define regDCIO_PATTERN_GEN_EN_BASE_IDX                                                                 2</div><div class='add'>+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b</div><div class='add'>+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2</div><div class='add'>+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c</div><div class='add'>+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2</div><div class='add'>+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d</div><div class='add'>+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2</div><div class='add'>+#define regDBG_OUT_CNTL                                                                                 0x289c</div><div class='add'>+#define regDBG_OUT_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDCIO_SOFT_RESET                                                                              0x289e</div><div class='add'>+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_chip_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8</div><div class='add'>+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2</div><div class='add'>+#define regDC_GPIO_GENERIC_A                                                                            0x28c9</div><div class='add'>+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca</div><div class='add'>+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb</div><div class='add'>+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0</div><div class='add'>+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC1_A                                                                               0x28d1</div><div class='add'>+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC1_EN                                                                              0x28d2</div><div class='add'>+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC1_Y                                                                               0x28d3</div><div class='add'>+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4</div><div class='add'>+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC2_A                                                                               0x28d5</div><div class='add'>+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC2_EN                                                                              0x28d6</div><div class='add'>+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC2_Y                                                                               0x28d7</div><div class='add'>+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8</div><div class='add'>+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC3_A                                                                               0x28d9</div><div class='add'>+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC3_EN                                                                              0x28da</div><div class='add'>+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC3_Y                                                                               0x28db</div><div class='add'>+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc</div><div class='add'>+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC4_A                                                                               0x28dd</div><div class='add'>+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC4_EN                                                                              0x28de</div><div class='add'>+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC4_Y                                                                               0x28df</div><div class='add'>+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0</div><div class='add'>+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC5_A                                                                               0x28e1</div><div class='add'>+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC5_EN                                                                              0x28e2</div><div class='add'>+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC5_Y                                                                               0x28e3</div><div class='add'>+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC6_MASK                                                                            0x28e4</div><div class='add'>+#define regDC_GPIO_DDC6_MASK_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDC6_A                                                                               0x28e5</div><div class='add'>+#define regDC_GPIO_DDC6_A_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDC6_EN                                                                              0x28e6</div><div class='add'>+#define regDC_GPIO_DDC6_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_DDC6_Y                                                                               0x28e7</div><div class='add'>+#define regDC_GPIO_DDC6_Y_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8</div><div class='add'>+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9</div><div class='add'>+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea</div><div class='add'>+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb</div><div class='add'>+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_SYNCA_MASK                                                                           0x28ec</div><div class='add'>+#define regDC_GPIO_SYNCA_MASK_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0</div><div class='add'>+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_GENLK_A                                                                              0x28f1</div><div class='add'>+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_GENLK_EN                                                                             0x28f2</div><div class='add'>+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_GENLK_Y                                                                              0x28f3</div><div class='add'>+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_HPD_MASK                                                                             0x28f4</div><div class='add'>+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_HPD_A                                                                                0x28f5</div><div class='add'>+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2</div><div class='add'>+#define regDC_GPIO_HPD_EN                                                                               0x28f6</div><div class='add'>+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2</div><div class='add'>+#define regDC_GPIO_HPD_Y                                                                                0x28f7</div><div class='add'>+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S0                                                                    0x28f8</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX                                                           2</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S1                                                                    0x28f9</div><div class='add'>+#define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX                                                           2</div><div class='add'>+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa</div><div class='add'>+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc</div><div class='add'>+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2</div><div class='add'>+#define regDC_GPIO_RESERVED                                                                             0x28fe</div><div class='add'>+#define regDC_GPIO_RESERVED_BASE_IDX                                                                    2</div><div class='add'>+#define regPHY_AUX_CNTL                                                                                 0x28ff</div><div class='add'>+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2</div><div class='add'>+#define regDC_GPIO_DRIVE_TXIMPSEL                                                                       0x2900</div><div class='add'>+#define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX                                                              2</div><div class='add'>+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902</div><div class='add'>+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_MASK                                                                       0x2910</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_MASK_BASE_IDX                                                              2</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_A                                                                          0x2911</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_A_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_EN                                                                         0x2912</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_EN_BASE_IDX                                                                2</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_Y                                                                          0x2913</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_Y_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_STRENGTH                                                                   0x2914</div><div class='add'>+#define regDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX                                                          2</div><div class='add'>+#define regDC_GPIO_TX12_EN                                                                              0x2915</div><div class='add'>+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_RXEN                                                                                 0x2919</div><div class='add'>+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2</div><div class='add'>+#define regDC_GPIO_PULLUPEN                                                                             0x291a</div><div class='add'>+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d</div><div class='add'>+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2</div><div class='add'>+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e</div><div class='add'>+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2928</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2929</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x292a</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x292b</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x292c</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x292d</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x292e</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x292f</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2930</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2931</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2932</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2933</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2934</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2935</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2936</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2937</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2938</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2939</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x293a</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x293b</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x293c</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x293d</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x293e</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x293f</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2940</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2941</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2942</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2943</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2944</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2945</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2946</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2947</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2948</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2949</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x294a</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x294b</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x294c</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x294d</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x294e</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x294f</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2950</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2951</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2952</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2953</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2954</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2955</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2956</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2957</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2958</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2959</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x295a</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x295b</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x295c</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x295d</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x295e</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x295f</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2960</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2961</div><div class='add'>+#define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy1_dispdec</div><div class='add'>+// base address: 0x360</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39</div><div class='add'>+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy2_dispdec</div><div class='add'>+// base address: 0x6c0</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11</div><div class='add'>+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy3_dispdec</div><div class='add'>+// base address: 0xa20</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9</div><div class='add'>+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_pwrseq0_dispdec_pwrseq_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDC_GPIO_PWRSEQ_EN                                                                            0x2f10</div><div class='add'>+#define regDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2</div><div class='add'>+#define regDC_GPIO_PWRSEQ_CTRL                                                                          0x2f11</div><div class='add'>+#define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_GPIO_PWRSEQ_MASK                                                                          0x2f12</div><div class='add'>+#define regDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2</div><div class='add'>+#define regDC_GPIO_PWRSEQ_A_Y                                                                           0x2f13</div><div class='add'>+#define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                                  2</div><div class='add'>+#define regPANEL_PWRSEQ_CNTL                                                                            0x2f14</div><div class='add'>+#define regPANEL_PWRSEQ_CNTL_BASE_IDX                                                                   2</div><div class='add'>+#define regPANEL_PWRSEQ_STATE                                                                           0x2f15</div><div class='add'>+#define regPANEL_PWRSEQ_STATE_BASE_IDX                                                                  2</div><div class='add'>+#define regPANEL_PWRSEQ_DELAY1                                                                          0x2f16</div><div class='add'>+#define regPANEL_PWRSEQ_DELAY1_BASE_IDX                                                                 2</div><div class='add'>+#define regPANEL_PWRSEQ_DELAY2                                                                          0x2f17</div><div class='add'>+#define regPANEL_PWRSEQ_DELAY2_BASE_IDX                                                                 2</div><div class='add'>+#define regPANEL_PWRSEQ_REF_DIV1                                                                        0x2f18</div><div class='add'>+#define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                               2</div><div class='add'>+#define regBL_PWM_CNTL                                                                                  0x2f19</div><div class='add'>+#define regBL_PWM_CNTL_BASE_IDX                                                                         2</div><div class='add'>+#define regBL_PWM_CNTL2                                                                                 0x2f1a</div><div class='add'>+#define regBL_PWM_CNTL2_BASE_IDX                                                                        2</div><div class='add'>+#define regBL_PWM_PERIOD_CNTL                                                                           0x2f1b</div><div class='add'>+#define regBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2</div><div class='add'>+#define regBL_PWM_GRP1_REG_LOCK                                                                         0x2f1c</div><div class='add'>+#define regBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2</div><div class='add'>+#define regPANEL_PWRSEQ_REF_DIV2                                                                        0x2f1d</div><div class='add'>+#define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                               2</div><div class='add'>+#define regPWRSEQ_DBG_SEL                                                                               0x2f20</div><div class='add'>+#define regPWRSEQ_DBG_SEL_BASE_IDX                                                                      2</div><div class='add'>+#define regPWRSEQ_SPARE                                                                                 0x2f21</div><div class='add'>+#define regPWRSEQ_SPARE_BASE_IDX                                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a</div><div class='add'>+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b</div><div class='add'>+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC0_DSCC_CONFIG2                                                                           0x300c</div><div class='add'>+#define regDSCC0_DSCC_CONFIG2_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC0_DSCC_STATUS                                                                            0x300d</div><div class='add'>+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_CONTROL0                                                                0x300e</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_CONTROL1                                                                0x300f</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_STATUS0                                                                 0x3010</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_STATUS0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_STATUS1                                                                 0x3011</div><div class='add'>+#define regDSCC0_DSCC_INTERRUPT_STATUS1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x3012</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x3013</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3014</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3015</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3016</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3017</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3018</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3019</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x301a</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x301b</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x301c</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x301d</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301e</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301f</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x3020</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x3021</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x3022</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x3023</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3024</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3025</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3026</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3027</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3028</div><div class='add'>+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC0_DSCC_MEM_POWER_CONTROL0                                                                0x3029</div><div class='add'>+#define regDSCC0_DSCC_MEM_POWER_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC0_DSCC_MEM_POWER_CONTROL1                                                                0x302a</div><div class='add'>+#define regDSCC0_DSCC_MEM_POWER_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x302b</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x302c</div><div class='add'>+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x302d</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x302e</div><div class='add'>+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302f</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3030</div><div class='add'>+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x3031</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x3032</div><div class='add'>+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0                                                 0x3033</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX                                        2</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1                                                 0x3034</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX                                        2</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2                                                 0x3035</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX                                        2</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3                                                 0x3036</div><div class='add'>+#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX                                        2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0                                             0x3037</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX                                    2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1                                             0x3038</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX                                    2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2                                             0x3039</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX                                    2</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3                                             0x303a</div><div class='add'>+#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX                                    2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX0                                                                 0x303b</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX1                                                                 0x303c</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX2                                                                 0x303d</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX3                                                                 0x303e</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303f</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x3040</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA1                                                                  0x3041</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA2                                                                  0x3042</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA3                                                                  0x3043</div><div class='add'>+#define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0                                                         0x3044</div><div class='add'>+#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX                                                2</div><div class='add'>+#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0                                                          0x3045</div><div class='add'>+#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005</div><div class='add'>+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001</div><div class='add'>+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDSC_TOP0_DSC_SPARE_DEBUG                                                                     0x3002</div><div class='add'>+#define regDSC_TOP0_DSC_SPARE_DEBUG_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX                                                            0x3003</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX                                                   2</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA                                                             0x3004</div><div class='add'>+#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x170</div><div class='add'>+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066</div><div class='add'>+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067</div><div class='add'>+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC1_DSCC_CONFIG2                                                                           0x3068</div><div class='add'>+#define regDSCC1_DSCC_CONFIG2_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC1_DSCC_STATUS                                                                            0x3069</div><div class='add'>+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_CONTROL0                                                                0x306a</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_CONTROL1                                                                0x306b</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_STATUS0                                                                 0x306c</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_STATUS0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_STATUS1                                                                 0x306d</div><div class='add'>+#define regDSCC1_DSCC_INTERRUPT_STATUS1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306e</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306f</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x3070</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x3071</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x3072</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x3073</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3074</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3075</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3076</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3077</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3078</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3079</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x307a</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x307b</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x307c</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x307d</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307e</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307f</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x3080</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x3081</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x3082</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x3083</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3084</div><div class='add'>+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC1_DSCC_MEM_POWER_CONTROL0                                                                0x3085</div><div class='add'>+#define regDSCC1_DSCC_MEM_POWER_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC1_DSCC_MEM_POWER_CONTROL1                                                                0x3086</div><div class='add'>+#define regDSCC1_DSCC_MEM_POWER_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3087</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3088</div><div class='add'>+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3089</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x308a</div><div class='add'>+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x308b</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x308c</div><div class='add'>+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x308d</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x308e</div><div class='add'>+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0                                                 0x308f</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX                                        2</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1                                                 0x3090</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX                                        2</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2                                                 0x3091</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX                                        2</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3                                                 0x3092</div><div class='add'>+#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX                                        2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0                                             0x3093</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX                                    2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1                                             0x3094</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX                                    2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2                                             0x3095</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX                                    2</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3                                             0x3096</div><div class='add'>+#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX                                    2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX0                                                                 0x3097</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX1                                                                 0x3098</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX2                                                                 0x3099</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX3                                                                 0x309a</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x309b</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x309c</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA1                                                                  0x309d</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA2                                                                  0x309e</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA3                                                                  0x309f</div><div class='add'>+#define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0                                                         0x30a0</div><div class='add'>+#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX                                                2</div><div class='add'>+#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0                                                          0x30a1</div><div class='add'>+#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x170</div><div class='add'>+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061</div><div class='add'>+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x170</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d</div><div class='add'>+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDSC_TOP1_DSC_SPARE_DEBUG                                                                     0x305e</div><div class='add'>+#define regDSC_TOP1_DSC_SPARE_DEBUG_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX                                                            0x305f</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX                                                   2</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA                                                             0x3060</div><div class='add'>+#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x2e0</div><div class='add'>+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2</div><div class='add'>+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3</div><div class='add'>+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC2_DSCC_CONFIG2                                                                           0x30c4</div><div class='add'>+#define regDSCC2_DSCC_CONFIG2_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC2_DSCC_STATUS                                                                            0x30c5</div><div class='add'>+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_CONTROL0                                                                0x30c6</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_CONTROL1                                                                0x30c7</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_STATUS0                                                                 0x30c8</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_STATUS0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_STATUS1                                                                 0x30c9</div><div class='add'>+#define regDSCC2_DSCC_INTERRUPT_STATUS1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30ca</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30cb</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30cc</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30cd</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ce</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cf</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30d0</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30d1</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30d2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30d3</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d4</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d5</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d6</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d7</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d8</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d9</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30da</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30db</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30dc</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30dd</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30de</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30df</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30e0</div><div class='add'>+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC2_DSCC_MEM_POWER_CONTROL0                                                                0x30e1</div><div class='add'>+#define regDSCC2_DSCC_MEM_POWER_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC2_DSCC_MEM_POWER_CONTROL1                                                                0x30e2</div><div class='add'>+#define regDSCC2_DSCC_MEM_POWER_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30e3</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30e4</div><div class='add'>+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e5</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e6</div><div class='add'>+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e7</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e8</div><div class='add'>+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e9</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30ea</div><div class='add'>+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0                                                 0x30eb</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX                                        2</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1                                                 0x30ec</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX                                        2</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2                                                 0x30ed</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX                                        2</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3                                                 0x30ee</div><div class='add'>+#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX                                        2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0                                             0x30ef</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX                                    2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1                                             0x30f0</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX                                    2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2                                             0x30f1</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX                                    2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3                                             0x30f2</div><div class='add'>+#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX                                    2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX0                                                                 0x30f3</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX1                                                                 0x30f4</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX2                                                                 0x30f5</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX3                                                                 0x30f6</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f7</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA0                                                                  0x30f8</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA1                                                                  0x30f9</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA2                                                                  0x30fa</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA3                                                                  0x30fb</div><div class='add'>+#define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0                                                         0x30fc</div><div class='add'>+#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX                                                2</div><div class='add'>+#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0                                                          0x30fd</div><div class='add'>+#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x2e0</div><div class='add'>+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd</div><div class='add'>+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x2e0</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9</div><div class='add'>+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDSC_TOP2_DSC_SPARE_DEBUG                                                                     0x30ba</div><div class='add'>+#define regDSC_TOP2_DSC_SPARE_DEBUG_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX                                                            0x30bb</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX                                                   2</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA                                                             0x30bc</div><div class='add'>+#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dscc_dispdec</div><div class='add'>+// base address: 0x450</div><div class='add'>+#define regDSCC3_DSCC_CONFIG0                                                                           0x311e</div><div class='add'>+#define regDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC3_DSCC_CONFIG1                                                                           0x311f</div><div class='add'>+#define regDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC3_DSCC_CONFIG2                                                                           0x3120</div><div class='add'>+#define regDSCC3_DSCC_CONFIG2_BASE_IDX                                                                  2</div><div class='add'>+#define regDSCC3_DSCC_STATUS                                                                            0x3121</div><div class='add'>+#define regDSCC3_DSCC_STATUS_BASE_IDX                                                                   2</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_CONTROL0                                                                0x3122</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_CONTROL1                                                                0x3123</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_STATUS0                                                                 0x3124</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_STATUS0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_STATUS1                                                                 0x3125</div><div class='add'>+#define regDSCC3_DSCC_INTERRUPT_STATUS1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG0                                                                       0x3126</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG1                                                                       0x3127</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG2                                                                       0x3128</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG3                                                                       0x3129</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG4                                                                       0x312a</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG5                                                                       0x312b</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG6                                                                       0x312c</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG7                                                                       0x312d</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG8                                                                       0x312e</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG9                                                                       0x312f</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG10                                                                      0x3130</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG11                                                                      0x3131</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG12                                                                      0x3132</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG13                                                                      0x3133</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG14                                                                      0x3134</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG15                                                                      0x3135</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG16                                                                      0x3136</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG17                                                                      0x3137</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG18                                                                      0x3138</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG19                                                                      0x3139</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG20                                                                      0x313a</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG21                                                                      0x313b</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG22                                                                      0x313c</div><div class='add'>+#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2</div><div class='add'>+#define regDSCC3_DSCC_MEM_POWER_CONTROL0                                                                0x313d</div><div class='add'>+#define regDSCC3_DSCC_MEM_POWER_CONTROL0_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC3_DSCC_MEM_POWER_CONTROL1                                                                0x313e</div><div class='add'>+#define regDSCC3_DSCC_MEM_POWER_CONTROL1_BASE_IDX                                                       2</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313f</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3140</div><div class='add'>+#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3141</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3142</div><div class='add'>+#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3143</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3144</div><div class='add'>+#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3145</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3146</div><div class='add'>+#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0                                                 0x3147</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX                                        2</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1                                                 0x3148</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX                                        2</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2                                                 0x3149</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX                                        2</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3                                                 0x314a</div><div class='add'>+#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX                                        2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0                                             0x314b</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX                                    2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1                                             0x314c</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX                                    2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2                                             0x314d</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX                                    2</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3                                             0x314e</div><div class='add'>+#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX                                    2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX0                                                                 0x314f</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX1                                                                 0x3150</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX2                                                                 0x3151</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX3                                                                 0x3152</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX                                                        2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3153</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA0                                                                  0x3154</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA1                                                                  0x3155</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA2                                                                  0x3156</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA3                                                                  0x3157</div><div class='add'>+#define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX                                                         2</div><div class='add'>+#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0                                                         0x3158</div><div class='add'>+#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX                                                2</div><div class='add'>+#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0                                                          0x3159</div><div class='add'>+#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dsccif_dispdec</div><div class='add'>+// base address: 0x450</div><div class='add'>+#define regDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119</div><div class='add'>+#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dsc_top_dispdec</div><div class='add'>+// base address: 0x450</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115</div><div class='add'>+#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regDSC_TOP3_DSC_SPARE_DEBUG                                                                     0x3116</div><div class='add'>+#define regDSC_TOP3_DSC_SPARE_DEBUG_BASE_IDX                                                            2</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX                                                            0x3117</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX                                                   2</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA                                                             0x3118</div><div class='add'>+#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dcoh_top_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDCOH_TOP_CLOCK_CONTROL                                                                       0x17af</div><div class='add'>+#define regDCOH_TOP_CLOCK_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDCOH_TOP_SPARE                                                                               0x17b3</div><div class='add'>+#define regDCOH_TOP_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux0_dispdec</div><div class='add'>+// base address: 0x13168</div><div class='add'>+#define regPHY_MUX0_PHY_MUX_CONTROL                                                                     0x179a</div><div class='add'>+#define regPHY_MUX0_PHY_MUX_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regPHY_MUX0_PORT_TYPE                                                                           0x179b</div><div class='add'>+#define regPHY_MUX0_PORT_TYPE_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux1_dispdec</div><div class='add'>+// base address: 0x13174</div><div class='add'>+#define regPHY_MUX1_PHY_MUX_CONTROL                                                                     0x179d</div><div class='add'>+#define regPHY_MUX1_PHY_MUX_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regPHY_MUX1_PORT_TYPE                                                                           0x179e</div><div class='add'>+#define regPHY_MUX1_PORT_TYPE_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux2_dispdec</div><div class='add'>+// base address: 0x13180</div><div class='add'>+#define regPHY_MUX2_PHY_MUX_CONTROL                                                                     0x17a0</div><div class='add'>+#define regPHY_MUX2_PHY_MUX_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regPHY_MUX2_PORT_TYPE                                                                           0x17a1</div><div class='add'>+#define regPHY_MUX2_PORT_TYPE_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux3_dispdec</div><div class='add'>+// base address: 0x1318c</div><div class='add'>+#define regPHY_MUX3_PHY_MUX_CONTROL                                                                     0x17a3</div><div class='add'>+#define regPHY_MUX3_PHY_MUX_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regPHY_MUX3_PORT_TYPE                                                                           0x17a4</div><div class='add'>+#define regPHY_MUX3_PORT_TYPE_BASE_IDX                                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDP_AUX0_AUX_CONTROL                                                                          0x16b2</div><div class='add'>+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x16b3</div><div class='add'>+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x16b4</div><div class='add'>+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x16b5</div><div class='add'>+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x16b6</div><div class='add'>+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x16b7</div><div class='add'>+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX0_AUX_SW_DATA                                                                          0x16b8</div><div class='add'>+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX0_AUX_LS_DATA                                                                          0x16b9</div><div class='add'>+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x16ba</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x16bb</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x16bc</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x16bd</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x16be</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x16bf</div><div class='add'>+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x16c1</div><div class='add'>+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP_AUX0_AUX_PHY_WAKE_STATUS                                                                  0x16c2</div><div class='add'>+#define regDP_AUX0_AUX_PHY_WAKE_STATUS_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux1_dispdec</div><div class='add'>+// base address: 0x70</div><div class='add'>+#define regDP_AUX1_AUX_CONTROL                                                                          0x16ce</div><div class='add'>+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x16cf</div><div class='add'>+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x16d0</div><div class='add'>+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x16d1</div><div class='add'>+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x16d2</div><div class='add'>+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x16d3</div><div class='add'>+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX1_AUX_SW_DATA                                                                          0x16d4</div><div class='add'>+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX1_AUX_LS_DATA                                                                          0x16d5</div><div class='add'>+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x16d6</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x16d7</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x16d8</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x16d9</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x16da</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x16db</div><div class='add'>+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x16dd</div><div class='add'>+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP_AUX1_AUX_PHY_WAKE_STATUS                                                                  0x16de</div><div class='add'>+#define regDP_AUX1_AUX_PHY_WAKE_STATUS_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux2_dispdec</div><div class='add'>+// base address: 0xe0</div><div class='add'>+#define regDP_AUX2_AUX_CONTROL                                                                          0x16ea</div><div class='add'>+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x16eb</div><div class='add'>+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x16ec</div><div class='add'>+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x16ed</div><div class='add'>+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x16ee</div><div class='add'>+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x16ef</div><div class='add'>+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX2_AUX_SW_DATA                                                                          0x16f0</div><div class='add'>+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX2_AUX_LS_DATA                                                                          0x16f1</div><div class='add'>+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x16f2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x16f3</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x16f4</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x16f5</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x16f6</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x16f7</div><div class='add'>+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x16f9</div><div class='add'>+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP_AUX2_AUX_PHY_WAKE_STATUS                                                                  0x16fa</div><div class='add'>+#define regDP_AUX2_AUX_PHY_WAKE_STATUS_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux3_dispdec</div><div class='add'>+// base address: 0x150</div><div class='add'>+#define regDP_AUX3_AUX_CONTROL                                                                          0x1706</div><div class='add'>+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1707</div><div class='add'>+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2</div><div class='add'>+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1708</div><div class='add'>+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1709</div><div class='add'>+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2</div><div class='add'>+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x170a</div><div class='add'>+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x170b</div><div class='add'>+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2</div><div class='add'>+#define regDP_AUX3_AUX_SW_DATA                                                                          0x170c</div><div class='add'>+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX3_AUX_LS_DATA                                                                          0x170d</div><div class='add'>+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x170e</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x170f</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1710</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1711</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1712</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1713</div><div class='add'>+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2</div><div class='add'>+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1715</div><div class='add'>+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2</div><div class='add'>+#define regDP_AUX3_AUX_PHY_WAKE_STATUS                                                                  0x1716</div><div class='add'>+#define regDP_AUX3_AUX_PHY_WAKE_STATUS_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x175a</div><div class='add'>+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x175b</div><div class='add'>+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD0_DC_HPD_CONTROL                                                                          0x175c</div><div class='add'>+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x175d</div><div class='add'>+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x175e</div><div class='add'>+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd1_dispdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1762</div><div class='add'>+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1763</div><div class='add'>+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD1_DC_HPD_CONTROL                                                                          0x1764</div><div class='add'>+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1765</div><div class='add'>+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1766</div><div class='add'>+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd2_dispdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x176a</div><div class='add'>+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x176b</div><div class='add'>+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD2_DC_HPD_CONTROL                                                                          0x176c</div><div class='add'>+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x176d</div><div class='add'>+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x176e</div><div class='add'>+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd3_dispdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1772</div><div class='add'>+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2</div><div class='add'>+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1773</div><div class='add'>+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regHPD3_DC_HPD_CONTROL                                                                          0x1774</div><div class='add'>+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2</div><div class='add'>+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1775</div><div class='add'>+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1776</div><div class='add'>+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hpo_top_dispdec</div><div class='add'>+// base address: 0x2790c</div><div class='add'>+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43</div><div class='add'>+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regHPO_TOP_HW_CONTROL                                                                           0x0e44</div><div class='add'>+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_mapper_dispdec</div><div class='add'>+// base address: 0x27958</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL4                                                                    0x0e5a</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL4_BASE_IDX                                                           3</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL5                                                                    0x0e5b</div><div class='add'>+#define regDP_STREAM_MAPPER_CONTROL5_BASE_IDX                                                           3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec</div><div class='add'>+// base address: 0x2656c</div><div class='add'>+#define regHDMI_LINK_ENC_CONTROL                                                                        0x095b</div><div class='add'>+#define regHDMI_LINK_ENC_CONTROL_BASE_IDX                                                               3</div><div class='add'>+#define regHDMI_LINK_ENC_CLK_CTRL                                                                       0x095c</div><div class='add'>+#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX                                                              3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec</div><div class='add'>+// base address: 0x26594</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG                                                                          0x0965</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG_BASE_IDX                                                                 3</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG2                                                                         0x0966</div><div class='add'>+#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_FRL_ENC_METER_BUFFER_STATUS                                                             0x0967</div><div class='add'>+#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX                                                    3</div><div class='add'>+#define regHDMI_FRL_ENC_MEM_CTRL                                                                        0x0968</div><div class='add'>+#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX                                                               3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec</div><div class='add'>+// base address: 0x2634c</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_CONTROL                                                                0x08d3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                                       3</div><div class='add'>+#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL                                                            0x08d5</div><div class='add'>+#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                                   3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                                     0x08d6</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX                            3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                                     0x08d7</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX                            3</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2                                     0x08d8</div><div class='add'>+#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX                            3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_afmt_afmt_dispdec</div><div class='add'>+// base address: 0x2646c</div><div class='add'>+#define regAFMT4_AFMT_ACP                                                                               0x091b</div><div class='add'>+#define regAFMT4_AFMT_ACP_BASE_IDX                                                                      3</div><div class='add'>+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x091c</div><div class='add'>+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x091e</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x091f</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              3</div><div class='add'>+#define regAFMT4_AFMT_60958_0                                                                           0x0920</div><div class='add'>+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  3</div><div class='add'>+#define regAFMT4_AFMT_60958_1                                                                           0x0921</div><div class='add'>+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x0923</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x0924</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x0925</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x0926</div><div class='add'>+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3</div><div class='add'>+#define regAFMT4_AFMT_60958_2                                                                           0x0927</div><div class='add'>+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x0928</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3</div><div class='add'>+#define regAFMT4_AFMT_STATUS                                                                            0x0929</div><div class='add'>+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3</div><div class='add'>+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x092b</div><div class='add'>+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3</div><div class='add'>+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x092c</div><div class='add'>+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL                                                                0x092e</div><div class='add'>+#define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX                                                       3</div><div class='add'>+#define regAFMT4_AFMT_MEM_PWR                                                                           0x092f</div><div class='add'>+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dme_dme_dispdec</div><div class='add'>+// base address: 0x264f0</div><div class='add'>+#define regDME4_DME_CONTROL                                                                             0x093c</div><div class='add'>+#define regDME4_DME_CONTROL_BASE_IDX                                                                    3</div><div class='add'>+#define regDME4_DME_MEMORY_CONTROL                                                                      0x093d</div><div class='add'>+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x264c4</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x0932</div><div class='add'>+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3</div><div class='add'>+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933</div><div class='add'>+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3</div><div class='add'>+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934</div><div class='add'>+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3</div><div class='add'>+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x0935</div><div class='add'>+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             3</div><div class='add'>+#define regVPG4_VPG_MEM_PWR                                                                             0x0936</div><div class='add'>+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    3</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x0938</div><div class='add'>+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               3</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO0                                                                          0x0939</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 3</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO1                                                                          0x093a</div><div class='add'>+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 3</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec</div><div class='add'>+// base address: 0x2637c</div><div class='add'>+#define regHDMI_TB_ENC_CONTROL                                                                          0x08df</div><div class='add'>+#define regHDMI_TB_ENC_CONTROL_BASE_IDX                                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_PIXEL_FORMAT                                                                     0x08e0</div><div class='add'>+#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_PACKET_CONTROL                                                                   0x08e1</div><div class='add'>+#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_PACKET_CONTROL                                                               0x08e2</div><div class='add'>+#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX                                                      3</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1                                                              0x08e3</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX                                                     3</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2                                                              0x08e4</div><div class='add'>+#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX                                                     3</div><div class='add'>+#define regHDMI_TB_ENC_GC_CONTROL                                                                       0x08e5</div><div class='add'>+#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX                                                              3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0                                                          0x08e6</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1                                                          0x08e7</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2                                                          0x08e8</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE                                                           0x08e9</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE                                                           0x08ea</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE                                                           0x08eb</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE                                                           0x08ec</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE                                                           0x08ed</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX                                                  3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE                                                         0x08ee</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX                                                3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE                                                         0x08ef</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX                                                3</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE                                                            0x08f0</div><div class='add'>+#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX                                                   3</div><div class='add'>+#define regHDMI_TB_ENC_DB_CONTROL                                                                       0x08f1</div><div class='add'>+#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX                                                              3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_0                                                                         0x08f2</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_1                                                                         0x08f3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_0                                                                         0x08f4</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_1                                                                         0x08f5</div><div class='add'>+#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_0                                                                         0x08f6</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_1                                                                         0x08f7</div><div class='add'>+#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_0                                                                     0x08f8</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_1                                                                     0x08f9</div><div class='add'>+#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_BUFFER_CONTROL                                                                   0x08fb</div><div class='add'>+#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regHDMI_TB_ENC_MEM_CTRL                                                                         0x08fe</div><div class='add'>+#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL                                                          0x08ff</div><div class='add'>+#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX                                                 3</div><div class='add'>+#define regHDMI_TB_ENC_H_ACTIVE_BLANK                                                                   0x0900</div><div class='add'>+#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX                                                          3</div><div class='add'>+#define regHDMI_TB_ENC_HC_ACTIVE_BLANK                                                                  0x0901</div><div class='add'>+#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX                                                         3</div><div class='add'>+#define regHDMI_TB_ENC_CRC_CNTL                                                                         0x0903</div><div class='add'>+#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX                                                                3</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_0                                                                     0x0904</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX                                                            3</div><div class='add'>+#define regHDMI_TB_ENC_ENCRYPTION_CONTROL                                                               0x0907</div><div class='add'>+#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX                                                      3</div><div class='add'>+#define regHDMI_TB_ENC_MODE                                                                             0x0908</div><div class='add'>+#define regHDMI_TB_ENC_MODE_BASE_IDX                                                                    3</div><div class='add'>+#define regHDMI_TB_ENC_INPUT_FIFO_STATUS                                                                0x0909</div><div class='add'>+#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX                                                       3</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_1                                                                     0x090a</div><div class='add'>+#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX                                                            3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_dispdec</div><div class='add'>+// base address: 0x1ab8c</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628</div><div class='add'>+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_apg_apg_dispdec</div><div class='add'>+// base address: 0x1abc0</div><div class='add'>+#define regAPG0_APG_CONTROL                                                                             0x3630</div><div class='add'>+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_CONTROL2                                                                            0x3631</div><div class='add'>+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632</div><div class='add'>+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633</div><div class='add'>+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG0_APG_DBG_ACP                                                                             0x3634</div><div class='add'>+#define regAPG0_APG_DBG_ACP_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_AUDIO_INFO                                                                          0x3635</div><div class='add'>+#define regAPG0_APG_AUDIO_INFO_BASE_IDX                                                                 2</div><div class='add'>+#define regAPG0_APG_DBG_AUDIO_INFO                                                                      0x3636</div><div class='add'>+#define regAPG0_APG_DBG_AUDIO_INFO_BASE_IDX                                                             2</div><div class='add'>+#define regAPG0_APG_DBG_60958_0                                                                         0x3637</div><div class='add'>+#define regAPG0_APG_DBG_60958_0_BASE_IDX                                                                2</div><div class='add'>+#define regAPG0_APG_DBG_60958_1                                                                         0x3638</div><div class='add'>+#define regAPG0_APG_DBG_60958_1_BASE_IDX                                                                2</div><div class='add'>+#define regAPG0_APG_DBG_60958_2                                                                         0x3639</div><div class='add'>+#define regAPG0_APG_DBG_60958_2_BASE_IDX                                                                2</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c</div><div class='add'>+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL0                                                                   0x363d</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL1                                                                   0x363e</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL2                                                                   0x363f</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL3                                                                   0x3640</div><div class='add'>+#define regAPG0_APG_DBG_RAMP_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAPG0_APG_STATUS                                                                              0x3641</div><div class='add'>+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG0_APG_STATUS2                                                                             0x3642</div><div class='add'>+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_DBG_AUDIO_DTO_CNTL                                                                  0x3643</div><div class='add'>+#define regAPG0_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regAPG0_APG_MEM_PWR                                                                             0x3644</div><div class='add'>+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG0_APG_SPARE                                                                               0x3646</div><div class='add'>+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_dme_dme_dispdec</div><div class='add'>+// base address: 0x1ac38</div><div class='add'>+#define regDME5_DME_CONTROL                                                                             0x364e</div><div class='add'>+#define regDME5_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME5_DME_MEMORY_CONTROL                                                                      0x364f</div><div class='add'>+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1ac44</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x3652</div><div class='add'>+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653</div><div class='add'>+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654</div><div class='add'>+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x3655</div><div class='add'>+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG5_VPG_MEM_PWR                                                                             0x3656</div><div class='add'>+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x3658</div><div class='add'>+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO0                                                                          0x3659</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO1                                                                          0x365a</div><div class='add'>+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc0_dispdec</div><div class='add'>+// base address: 0x1ac74</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING                                                       0x367f</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0                                                  0x3680</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1                                                  0x3681</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL                                              0x3682</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x368b</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x368c</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL                                                0x368d</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL                                                 0x368e</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET                                               0x368f</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL                                                0x3690</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL                                        0x3691</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS                                                       0x3692</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL                                                0x3693</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL                                       0x3694</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS                                        0x3695</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3696</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x3697</div><div class='add'>+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_dispdec</div><div class='add'>+// base address: 0x1aedc</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc</div><div class='add'>+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_apg_apg_dispdec</div><div class='add'>+// base address: 0x1af10</div><div class='add'>+#define regAPG1_APG_CONTROL                                                                             0x3704</div><div class='add'>+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_CONTROL2                                                                            0x3705</div><div class='add'>+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706</div><div class='add'>+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707</div><div class='add'>+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG1_APG_DBG_ACP                                                                             0x3708</div><div class='add'>+#define regAPG1_APG_DBG_ACP_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_AUDIO_INFO                                                                          0x3709</div><div class='add'>+#define regAPG1_APG_AUDIO_INFO_BASE_IDX                                                                 2</div><div class='add'>+#define regAPG1_APG_DBG_AUDIO_INFO                                                                      0x370a</div><div class='add'>+#define regAPG1_APG_DBG_AUDIO_INFO_BASE_IDX                                                             2</div><div class='add'>+#define regAPG1_APG_DBG_60958_0                                                                         0x370b</div><div class='add'>+#define regAPG1_APG_DBG_60958_0_BASE_IDX                                                                2</div><div class='add'>+#define regAPG1_APG_DBG_60958_1                                                                         0x370c</div><div class='add'>+#define regAPG1_APG_DBG_60958_1_BASE_IDX                                                                2</div><div class='add'>+#define regAPG1_APG_DBG_60958_2                                                                         0x370d</div><div class='add'>+#define regAPG1_APG_DBG_60958_2_BASE_IDX                                                                2</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710</div><div class='add'>+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL0                                                                   0x3711</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL1                                                                   0x3712</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL2                                                                   0x3713</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL3                                                                   0x3714</div><div class='add'>+#define regAPG1_APG_DBG_RAMP_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAPG1_APG_STATUS                                                                              0x3715</div><div class='add'>+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG1_APG_STATUS2                                                                             0x3716</div><div class='add'>+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_DBG_AUDIO_DTO_CNTL                                                                  0x3717</div><div class='add'>+#define regAPG1_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regAPG1_APG_MEM_PWR                                                                             0x3718</div><div class='add'>+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG1_APG_SPARE                                                                               0x371a</div><div class='add'>+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_dme_dme_dispdec</div><div class='add'>+// base address: 0x1af88</div><div class='add'>+#define regDME6_DME_CONTROL                                                                             0x3722</div><div class='add'>+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME6_DME_MEMORY_CONTROL                                                                      0x3723</div><div class='add'>+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1af94</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3726</div><div class='add'>+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727</div><div class='add'>+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728</div><div class='add'>+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3729</div><div class='add'>+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG6_VPG_MEM_PWR                                                                             0x372a</div><div class='add'>+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x372c</div><div class='add'>+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO0                                                                          0x372d</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO1                                                                          0x372e</div><div class='add'>+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc1_dispdec</div><div class='add'>+// base address: 0x1afc4</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING                                                       0x3753</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0                                                  0x3754</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1                                                  0x3755</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL                                              0x3756</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x375f</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3760</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL                                                0x3761</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL                                                 0x3762</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET                                               0x3763</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL                                                0x3764</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL                                        0x3765</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS                                                       0x3766</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL                                                0x3767</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL                                       0x3768</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS                                        0x3769</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x376a</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x376b</div><div class='add'>+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_dispdec</div><div class='add'>+// base address: 0x1b22c</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0</div><div class='add'>+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_apg_apg_dispdec</div><div class='add'>+// base address: 0x1b260</div><div class='add'>+#define regAPG2_APG_CONTROL                                                                             0x37d8</div><div class='add'>+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_CONTROL2                                                                            0x37d9</div><div class='add'>+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da</div><div class='add'>+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db</div><div class='add'>+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG2_APG_DBG_ACP                                                                             0x37dc</div><div class='add'>+#define regAPG2_APG_DBG_ACP_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_AUDIO_INFO                                                                          0x37dd</div><div class='add'>+#define regAPG2_APG_AUDIO_INFO_BASE_IDX                                                                 2</div><div class='add'>+#define regAPG2_APG_DBG_AUDIO_INFO                                                                      0x37de</div><div class='add'>+#define regAPG2_APG_DBG_AUDIO_INFO_BASE_IDX                                                             2</div><div class='add'>+#define regAPG2_APG_DBG_60958_0                                                                         0x37df</div><div class='add'>+#define regAPG2_APG_DBG_60958_0_BASE_IDX                                                                2</div><div class='add'>+#define regAPG2_APG_DBG_60958_1                                                                         0x37e0</div><div class='add'>+#define regAPG2_APG_DBG_60958_1_BASE_IDX                                                                2</div><div class='add'>+#define regAPG2_APG_DBG_60958_2                                                                         0x37e1</div><div class='add'>+#define regAPG2_APG_DBG_60958_2_BASE_IDX                                                                2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4</div><div class='add'>+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL0                                                                   0x37e5</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL1                                                                   0x37e6</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL2                                                                   0x37e7</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL3                                                                   0x37e8</div><div class='add'>+#define regAPG2_APG_DBG_RAMP_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAPG2_APG_STATUS                                                                              0x37e9</div><div class='add'>+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG2_APG_STATUS2                                                                             0x37ea</div><div class='add'>+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_DBG_AUDIO_DTO_CNTL                                                                  0x37eb</div><div class='add'>+#define regAPG2_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regAPG2_APG_MEM_PWR                                                                             0x37ec</div><div class='add'>+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG2_APG_SPARE                                                                               0x37ee</div><div class='add'>+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_dme_dme_dispdec</div><div class='add'>+// base address: 0x1b2d8</div><div class='add'>+#define regDME7_DME_CONTROL                                                                             0x37f6</div><div class='add'>+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME7_DME_MEMORY_CONTROL                                                                      0x37f7</div><div class='add'>+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1b2e4</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x37fa</div><div class='add'>+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb</div><div class='add'>+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc</div><div class='add'>+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x37fd</div><div class='add'>+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG7_VPG_MEM_PWR                                                                             0x37fe</div><div class='add'>+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x3800</div><div class='add'>+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO0                                                                          0x3801</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO1                                                                          0x3802</div><div class='add'>+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc2_dispdec</div><div class='add'>+// base address: 0x1b314</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING                                                       0x3827</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0                                                  0x3828</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1                                                  0x3829</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL                                              0x382a</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3833</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3834</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL                                                0x3835</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL                                                 0x3836</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET                                               0x3837</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL                                                0x3838</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL                                        0x3839</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS                                                       0x383a</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL                                                0x383b</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL                                       0x383c</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS                                        0x383d</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x383e</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x383f</div><div class='add'>+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_dispdec</div><div class='add'>+// base address: 0x1b57c</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4</div><div class='add'>+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_apg_apg_dispdec</div><div class='add'>+// base address: 0x1b5b0</div><div class='add'>+#define regAPG3_APG_CONTROL                                                                             0x38ac</div><div class='add'>+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_CONTROL2                                                                            0x38ad</div><div class='add'>+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2</div><div class='add'>+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae</div><div class='add'>+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2</div><div class='add'>+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af</div><div class='add'>+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2</div><div class='add'>+#define regAPG3_APG_DBG_ACP                                                                             0x38b0</div><div class='add'>+#define regAPG3_APG_DBG_ACP_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_AUDIO_INFO                                                                          0x38b1</div><div class='add'>+#define regAPG3_APG_AUDIO_INFO_BASE_IDX                                                                 2</div><div class='add'>+#define regAPG3_APG_DBG_AUDIO_INFO                                                                      0x38b2</div><div class='add'>+#define regAPG3_APG_DBG_AUDIO_INFO_BASE_IDX                                                             2</div><div class='add'>+#define regAPG3_APG_DBG_60958_0                                                                         0x38b3</div><div class='add'>+#define regAPG3_APG_DBG_60958_0_BASE_IDX                                                                2</div><div class='add'>+#define regAPG3_APG_DBG_60958_1                                                                         0x38b4</div><div class='add'>+#define regAPG3_APG_DBG_60958_1_BASE_IDX                                                                2</div><div class='add'>+#define regAPG3_APG_DBG_60958_2                                                                         0x38b5</div><div class='add'>+#define regAPG3_APG_DBG_60958_2_BASE_IDX                                                                2</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8</div><div class='add'>+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL0                                                                   0x38b9</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL0_BASE_IDX                                                          2</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL1                                                                   0x38ba</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL1_BASE_IDX                                                          2</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL2                                                                   0x38bb</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL2_BASE_IDX                                                          2</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL3                                                                   0x38bc</div><div class='add'>+#define regAPG3_APG_DBG_RAMP_CONTROL3_BASE_IDX                                                          2</div><div class='add'>+#define regAPG3_APG_STATUS                                                                              0x38bd</div><div class='add'>+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2</div><div class='add'>+#define regAPG3_APG_STATUS2                                                                             0x38be</div><div class='add'>+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_DBG_AUDIO_DTO_CNTL                                                                  0x38bf</div><div class='add'>+#define regAPG3_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regAPG3_APG_MEM_PWR                                                                             0x38c0</div><div class='add'>+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regAPG3_APG_SPARE                                                                               0x38c2</div><div class='add'>+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_dme_dme_dispdec</div><div class='add'>+// base address: 0x1b628</div><div class='add'>+#define regDME8_DME_CONTROL                                                                             0x38ca</div><div class='add'>+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2</div><div class='add'>+#define regDME8_DME_MEMORY_CONTROL                                                                      0x38cb</div><div class='add'>+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_vpg_vpg_dispdec</div><div class='add'>+// base address: 0x1b634</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x38ce</div><div class='add'>+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2</div><div class='add'>+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf</div><div class='add'>+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2</div><div class='add'>+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0</div><div class='add'>+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2</div><div class='add'>+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x38d1</div><div class='add'>+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2</div><div class='add'>+#define regVPG8_VPG_MEM_PWR                                                                             0x38d2</div><div class='add'>+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x38d4</div><div class='add'>+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO0                                                                          0x38d5</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO1                                                                          0x38d6</div><div class='add'>+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc3_dispdec</div><div class='add'>+// base address: 0x1b664</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING                                                       0x38fb</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0                                                  0x38fc</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1                                                  0x38fd</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL                                              0x38fe</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS                                               0x3907</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL                                              0x3908</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX                                     2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL                                                0x3909</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL                                                 0x390a</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET                                               0x390b</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX                                      2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL                                                0x390c</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL                                        0x390d</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS                                                       0x390e</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX                                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL                                                0x390f</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX                                       2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL                                       0x3910</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX                              2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS                                        0x3911</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX                               2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3912</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3913</div><div class='add'>+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc0_dispdec</div><div class='add'>+// base address: 0x1ad7c</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x369f</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x36a0</div><div class='add'>+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym320_dispdec</div><div class='add'>+// base address: 0x1add0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36b4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36b5</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0                                                 0x36b6</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1                                                 0x36b7</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36b8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36b9</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36ba</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36bb</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36bc</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4                                                   0x36bd</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5                                                   0x36be</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36bf</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36c0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36c1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36c2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4                                                         0x36c3</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5                                                         0x36c4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36c5</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36c6</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36c7</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36c8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4                                                  0x36c9</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5                                                  0x36ca</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0                                                     0x36cb</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0                                                       0x36cc</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1                                                       0x36cd</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2                                                       0x36ce</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3                                                       0x36cf</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0                                              0x36d0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX                                     2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0                                               0x36d1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1                                               0x36d2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL                                                    0x36d3</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d5</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d6</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36d7</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36d8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36d9</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36da</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36db</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36dc</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36dd</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36de</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36df</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e0</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e1</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e3</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e4</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e5</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0                                               0x36e6</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x36e8</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x36e9</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x36ea</div><div class='add'>+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc1_dispdec</div><div class='add'>+// base address: 0x1b0cc</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3773</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x3774</div><div class='add'>+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym321_dispdec</div><div class='add'>+// base address: 0x1b120</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3788</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3789</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0                                                 0x378a</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1                                                 0x378b</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x378c</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x378d</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x378e</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x378f</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x3790</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4                                                   0x3791</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5                                                   0x3792</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x3793</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x3794</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x3795</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x3796</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4                                                         0x3797</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5                                                         0x3798</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x3799</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x379a</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x379b</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x379c</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4                                                  0x379d</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5                                                  0x379e</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0                                                     0x379f</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0                                                       0x37a0</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1                                                       0x37a1</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2                                                       0x37a2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3                                                       0x37a3</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0                                              0x37a4</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX                                     2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0                                               0x37a5</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1                                               0x37a6</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL                                                    0x37a7</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37a8</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37a9</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37aa</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ab</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37ac</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37ad</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37ae</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37af</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b0</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b1</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b3</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b4</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b5</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b6</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37b7</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37b8</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37b9</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0                                               0x37ba</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x37bc</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x37bd</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x37be</div><div class='add'>+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc2_dispdec</div><div class='add'>+// base address: 0x1b41c</div><div class='add'>+#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3847</div><div class='add'>+#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE                                                               0x3848</div><div class='add'>+#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym322_dispdec</div><div class='add'>+// base address: 0x1b470</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL                                                         0x385c</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS                                                          0x385d</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0                                                 0x385e</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1                                                 0x385f</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3860</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3861</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x3862</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x3863</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x3864</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4                                                   0x3865</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5                                                   0x3866</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0                                                         0x3867</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1                                                         0x3868</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2                                                         0x3869</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3                                                         0x386a</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4                                                         0x386b</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5                                                         0x386c</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x386d</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x386e</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x386f</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x3870</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4                                                  0x3871</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5                                                  0x3872</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0                                                     0x3873</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0                                                       0x3874</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1                                                       0x3875</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2                                                       0x3876</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3                                                       0x3877</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0                                              0x3878</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX                                     2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0                                               0x3879</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1                                               0x387a</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL                                                    0x387b</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG                                                       0x387c</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x387d</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x387e</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x387f</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x3880</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x3881</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x3882</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x3883</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x3884</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x3885</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x3886</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x3887</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x3888</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x3889</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x388a</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x388b</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x388c</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS                                                    0x388d</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0                                               0x388e</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x3890</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x3891</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x3892</div><div class='add'>+#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc3_dispdec</div><div class='add'>+// base address: 0x1b76c</div><div class='add'>+#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL                                                       0x391b</div><div class='add'>+#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2</div><div class='add'>+#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE                                                               0x391c</div><div class='add'>+#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE_BASE_IDX                                                      2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym323_dispdec</div><div class='add'>+// base address: 0x1b7c0</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL                                                         0x3930</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS                                                          0x3931</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0                                                 0x3932</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1                                                 0x3933</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX                                        2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3934</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3935</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x3936</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x3937</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x3938</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4                                                   0x3939</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5                                                   0x393a</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0                                                         0x393b</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1                                                         0x393c</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2                                                         0x393d</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3                                                         0x393e</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4                                                         0x393f</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5                                                         0x3940</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5_BASE_IDX                                                2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x3941</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x3942</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x3943</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x3944</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4                                                  0x3945</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5                                                  0x3946</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX                                         2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0                                                     0x3947</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0                                                       0x3948</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1                                                       0x3949</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2                                                       0x394a</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3                                                       0x394b</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0                                              0x394c</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX                                     2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0                                               0x394d</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1                                               0x394e</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL                                                    0x394f</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG                                                       0x3950</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x3951</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x3952</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x3953</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x3954</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x3955</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x3956</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x3957</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x3958</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x3959</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x395a</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x395b</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x395c</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x395d</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x395e</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x395f</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x3960</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS                                                    0x3961</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0                                               0x3962</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX                                      2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0                                            0x3964</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1                                            0x3965</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX                                   2</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL                                            0x3966</div><div class='add'>+#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX                                   2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dlpc_dlpc_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDLPC_ENABLE                                                                                  0x2fe8</div><div class='add'>+#define regDLPC_ENABLE_BASE_IDX                                                                         2</div><div class='add'>+#define regDLPC_CURRENT_COUNT                                                                           0x2fe9</div><div class='add'>+#define regDLPC_CURRENT_COUNT_BASE_IDX                                                                  2</div><div class='add'>+#define regDLPC_OPTC_SNAPSHOT                                                                           0x2fea</div><div class='add'>+#define regDLPC_OPTC_SNAPSHOT_BASE_IDX                                                                  2</div><div class='add'>+#define regDLPC_PWRUP                                                                                   0x2feb</div><div class='add'>+#define regDLPC_PWRUP_BASE_IDX                                                                          2</div><div class='add'>+#define regDLPC_OTG_RESYNC                                                                              0x2fec</div><div class='add'>+#define regDLPC_OTG_RESYNC_BASE_IDX                                                                     2</div><div class='add'>+#define regDLPC_DCN_ZSC_LONO_PWRUP                                                                      0x2fed</div><div class='add'>+#define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX                                                             2</div><div class='add'>+#define regDLPC_SPARE                                                                                   0x2fee</div><div class='add'>+#define regDLPC_SPARE_BASE_IDX                                                                          2</div><div class='add'>+#define regDLPC_COUNTER_INIT_VALUE                                                                      0x2fef</div><div class='add'>+#define regDLPC_COUNTER_INIT_VALUE_BASE_IDX                                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934</div><div class='add'>+#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935</div><div class='add'>+#define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr1_dispdec</div><div class='add'>+// base address: 0x360</div><div class='add'>+#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c</div><div class='add'>+#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d</div><div class='add'>+#define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr2_dispdec</div><div class='add'>+// base address: 0x6c0</div><div class='add'>+#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4</div><div class='add'>+#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5</div><div class='add'>+#define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr3_dispdec</div><div class='add'>+// base address: 0xa20</div><div class='add'>+#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc</div><div class='add'>+#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2</div><div class='add'>+#define regDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd</div><div class='add'>+#define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx0_dispdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2933</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SCRATCH0                                                                    0x2937</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SCRATCH0_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE                                                            0x293a</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL                                                         0x293b</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX                                                2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CNTL4                                                                       0x293c</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_CNTL4_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SCRATCH1                                                                    0x2954</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SCRATCH1_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SCRATCH2                                                                    0x2955</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_SCRATCH2_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2                                                               0x295b</div><div class='add'>+#define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX0_RDPCS_CNTL3                                                                         0x295c</div><div class='add'>+#define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX                                                                2</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x295d</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x295e</div><div class='add'>+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx1_dispdec</div><div class='add'>+// base address: 0x360</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2a0b</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SCRATCH0                                                                    0x2a0f</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SCRATCH0_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE                                                            0x2a12</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL                                                         0x2a13</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX                                                2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CNTL4                                                                       0x2a14</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_CNTL4_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SCRATCH1                                                                    0x2a2c</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SCRATCH1_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SCRATCH2                                                                    0x2a2d</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_SCRATCH2_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2                                                               0x2a33</div><div class='add'>+#define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX1_RDPCS_CNTL3                                                                         0x2a34</div><div class='add'>+#define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX                                                                2</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2a35</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2a36</div><div class='add'>+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx2_dispdec</div><div class='add'>+// base address: 0x6c0</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2ae3</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SCRATCH0                                                                    0x2ae7</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SCRATCH0_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE                                                            0x2aea</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL                                                         0x2aeb</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX                                                2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CNTL4                                                                       0x2aec</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_CNTL4_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SCRATCH1                                                                    0x2b04</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SCRATCH1_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SCRATCH2                                                                    0x2b05</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_SCRATCH2_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2                                                               0x2b0b</div><div class='add'>+#define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX2_RDPCS_CNTL3                                                                         0x2b0c</div><div class='add'>+#define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX                                                                2</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2b0d</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2b0e</div><div class='add'>+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx3_dispdec</div><div class='add'>+// base address: 0xa20</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2bbb</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SCRATCH0                                                                    0x2bbf</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SCRATCH0_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE                                                            0x2bc2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX                                                   2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL                                                         0x2bc3</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX                                                2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CNTL4                                                                       0x2bc4</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_CNTL4_BASE_IDX                                                              2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SCRATCH1                                                                    0x2bdc</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SCRATCH1_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SCRATCH2                                                                    0x2bdd</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_SCRATCH2_BASE_IDX                                                           2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2                                                               0x2be3</div><div class='add'>+#define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2</div><div class='add'>+#define regRDPCSTX3_RDPCS_CNTL3                                                                         0x2be4</div><div class='add'>+#define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX                                                                2</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2be5</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2be6</div><div class='add'>+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azcontroller_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZCONTROLLER0_CORB_WRITE_POINTER                                                             0x0000</div><div class='add'>+#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX                                                    0</div><div class='add'>+#define regAZCONTROLLER0_CORB_READ_POINTER                                                              0x0000</div><div class='add'>+#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX                                                     0</div><div class='add'>+#define regAZCONTROLLER0_CORB_CONTROL                                                                   0x0001</div><div class='add'>+#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX                                                          0</div><div class='add'>+#define regAZCONTROLLER0_CORB_STATUS                                                                    0x0001</div><div class='add'>+#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX                                                           0</div><div class='add'>+#define regAZCONTROLLER0_CORB_SIZE                                                                      0x0001</div><div class='add'>+#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX                                                             0</div><div class='add'>+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS                                                        0x0002</div><div class='add'>+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               0</div><div class='add'>+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS                                                        0x0003</div><div class='add'>+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               0</div><div class='add'>+#define regAZCONTROLLER0_RIRB_WRITE_POINTER                                                             0x0004</div><div class='add'>+#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX                                                    0</div><div class='add'>+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT                                                       0x0004</div><div class='add'>+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              0</div><div class='add'>+#define regAZCONTROLLER0_RIRB_CONTROL                                                                   0x0005</div><div class='add'>+#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX                                                          0</div><div class='add'>+#define regAZCONTROLLER0_RIRB_STATUS                                                                    0x0005</div><div class='add'>+#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX                                                           0</div><div class='add'>+#define regAZCONTROLLER0_RIRB_SIZE                                                                      0x0005</div><div class='add'>+#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX                                                             0</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x0006</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    0</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x0006</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               0</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x0006</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              0</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x0007</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    0</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS                                                       0x0008</div><div class='add'>+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              0</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x000a</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       0</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x000b</div><div class='add'>+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       0</div><div class='add'>+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS                                                       0x074c</div><div class='add'>+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azendpoint_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x0006</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      0</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x0006</div><div class='add'>+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azinputendpoint_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x0006</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  0</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x0006</div><div class='add'>+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azroot_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                       0x0006</div><div class='add'>+#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                              0</div><div class='add'>+#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                      0x0006</div><div class='add'>+#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                             0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream0_azdec</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x000e</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x000f</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0010</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0011</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x0012</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x0012</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x0014</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x0015</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0761</div><div class='add'>+#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream1_azdec</div><div class='add'>+// base address: 0x20</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x0016</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x0017</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0018</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0019</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x001a</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x001a</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x001c</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x001d</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0769</div><div class='add'>+#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream2_azdec</div><div class='add'>+// base address: 0x40</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x001e</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x001f</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0020</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0021</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x0022</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x0022</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x0024</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x0025</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0771</div><div class='add'>+#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream3_azdec</div><div class='add'>+// base address: 0x60</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x0026</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x0027</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0028</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0029</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x002a</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x002a</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x002c</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x002d</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0779</div><div class='add'>+#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream4_azdec</div><div class='add'>+// base address: 0x80</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x002e</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x002f</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0030</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0031</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x0032</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x0032</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x0034</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x0035</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0781</div><div class='add'>+#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream5_azdec</div><div class='add'>+// base address: 0xa0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x0036</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x0037</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0038</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0039</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x003a</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x003a</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x003c</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x003d</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0789</div><div class='add'>+#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream6_azdec</div><div class='add'>+// base address: 0xc0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x003e</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x003f</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0040</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0041</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x0042</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x0042</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x0044</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x0045</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0791</div><div class='add'>+#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream7_azdec</div><div class='add'>+// base address: 0xe0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x0046</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x0047</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x0048</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x0049</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x004a</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x004a</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x004c</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x004d</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 0</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x0799</div><div class='add'>+#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azcontroller_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regGLOBAL_CAPABILITIES                                                                          0x4b7000</div><div class='add'>+#define regGLOBAL_CAPABILITIES_BASE_IDX                                                                 3</div><div class='add'>+#define regMINOR_VERSION                                                                                0x4b7000</div><div class='add'>+#define regMINOR_VERSION_BASE_IDX                                                                       3</div><div class='add'>+#define regMAJOR_VERSION                                                                                0x4b7000</div><div class='add'>+#define regMAJOR_VERSION_BASE_IDX                                                                       3</div><div class='add'>+#define regOUTPUT_PAYLOAD_CAPABILITY                                                                    0x4b7001</div><div class='add'>+#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                           3</div><div class='add'>+#define regINPUT_PAYLOAD_CAPABILITY                                                                     0x4b7001</div><div class='add'>+#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                            3</div><div class='add'>+#define regGLOBAL_CONTROL                                                                               0x4b7002</div><div class='add'>+#define regGLOBAL_CONTROL_BASE_IDX                                                                      3</div><div class='add'>+#define regWAKE_ENABLE                                                                                  0x4b7003</div><div class='add'>+#define regWAKE_ENABLE_BASE_IDX                                                                         3</div><div class='add'>+#define regSTATE_CHANGE_STATUS                                                                          0x4b7003</div><div class='add'>+#define regSTATE_CHANGE_STATUS_BASE_IDX                                                                 3</div><div class='add'>+#define regGLOBAL_STATUS                                                                                0x4b7004</div><div class='add'>+#define regGLOBAL_STATUS_BASE_IDX                                                                       3</div><div class='add'>+#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY                                                             0x4b7006</div><div class='add'>+#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                    3</div><div class='add'>+#define regINPUT_STREAM_PAYLOAD_CAPABILITY                                                              0x4b7006</div><div class='add'>+#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                                     3</div><div class='add'>+#define regINTERRUPT_CONTROL                                                                            0x4b7008</div><div class='add'>+#define regINTERRUPT_CONTROL_BASE_IDX                                                                   3</div><div class='add'>+#define regINTERRUPT_STATUS                                                                             0x4b7009</div><div class='add'>+#define regINTERRUPT_STATUS_BASE_IDX                                                                    3</div><div class='add'>+#define regWALL_CLOCK_COUNTER                                                                           0x4b700c</div><div class='add'>+#define regWALL_CLOCK_COUNTER_BASE_IDX                                                                  3</div><div class='add'>+#define regSTREAM_SYNCHRONIZATION                                                                       0x4b700e</div><div class='add'>+#define regSTREAM_SYNCHRONIZATION_BASE_IDX                                                              3</div><div class='add'>+#define regCORB_LOWER_BASE_ADDRESS                                                                      0x4b7010</div><div class='add'>+#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX                                                             3</div><div class='add'>+#define regCORB_UPPER_BASE_ADDRESS                                                                      0x4b7011</div><div class='add'>+#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX                                                             3</div><div class='add'>+#define regAZCONTROLLER1_CORB_WRITE_POINTER                                                             0x4b7012</div><div class='add'>+#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX                                                    3</div><div class='add'>+#define regAZCONTROLLER1_CORB_READ_POINTER                                                              0x4b7012</div><div class='add'>+#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX                                                     3</div><div class='add'>+#define regAZCONTROLLER1_CORB_CONTROL                                                                   0x4b7013</div><div class='add'>+#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regAZCONTROLLER1_CORB_STATUS                                                                    0x4b7013</div><div class='add'>+#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX                                                           3</div><div class='add'>+#define regAZCONTROLLER1_CORB_SIZE                                                                      0x4b7013</div><div class='add'>+#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX                                                             3</div><div class='add'>+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS                                                        0x4b7014</div><div class='add'>+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               3</div><div class='add'>+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS                                                        0x4b7015</div><div class='add'>+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               3</div><div class='add'>+#define regAZCONTROLLER1_RIRB_WRITE_POINTER                                                             0x4b7016</div><div class='add'>+#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX                                                    3</div><div class='add'>+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT                                                       0x4b7016</div><div class='add'>+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              3</div><div class='add'>+#define regAZCONTROLLER1_RIRB_CONTROL                                                                   0x4b7017</div><div class='add'>+#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX                                                          3</div><div class='add'>+#define regAZCONTROLLER1_RIRB_STATUS                                                                    0x4b7017</div><div class='add'>+#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX                                                           3</div><div class='add'>+#define regAZCONTROLLER1_RIRB_SIZE                                                                      0x4b7017</div><div class='add'>+#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX                                                             3</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x4b7018</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    3</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x4b7018</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               3</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x4b7018</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              3</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x4b7019</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    3</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS                                                       0x4b701a</div><div class='add'>+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              3</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x4b701c</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       3</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x4b701d</div><div class='add'>+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       3</div><div class='add'>+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS                                                       0x4b780c</div><div class='add'>+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azendpoint_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x4b7018</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      3</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x4b7018</div><div class='add'>+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azinputendpoint_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x4b7018</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  3</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x4b7018</div><div class='add'>+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azroot_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                       0x4b7018</div><div class='add'>+#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                              3</div><div class='add'>+#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                      0x4b7018</div><div class='add'>+#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                             3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream0_azdec</div><div class='add'>+// base address: 0x1300000</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7020</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7021</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b7022</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b7023</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b7024</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b7024</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b7026</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b7027</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7821</div><div class='add'>+#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream1_azdec</div><div class='add'>+// base address: 0x1300020</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7028</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7029</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b702a</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b702b</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b702c</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b702c</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b702e</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b702f</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7829</div><div class='add'>+#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream2_azdec</div><div class='add'>+// base address: 0x1300040</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7030</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7031</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b7032</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b7033</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b7034</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b7034</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b7036</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b7037</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7831</div><div class='add'>+#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream3_azdec</div><div class='add'>+// base address: 0x1300060</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7038</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7039</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b703a</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b703b</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b703c</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b703c</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b703e</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b703f</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7839</div><div class='add'>+#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream4_azdec</div><div class='add'>+// base address: 0x1300080</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7040</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7041</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b7042</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b7043</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b7044</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b7044</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b7046</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b7047</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7841</div><div class='add'>+#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream5_azdec</div><div class='add'>+// base address: 0x13000a0</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7048</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7049</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b704a</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b704b</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b704c</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b704c</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b704e</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b704f</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7849</div><div class='add'>+#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream6_azdec</div><div class='add'>+// base address: 0x13000c0</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7050</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7051</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b7052</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b7053</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b7054</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b7054</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b7056</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b7057</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7851</div><div class='add'>+#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream7_azdec</div><div class='add'>+// base address: 0x13000e0</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS                                      0x4b7058</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX                             3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER                         0x4b7059</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX                3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH                                    0x4b705a</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX                           3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX                                        0x4b705b</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX                               3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE                                               0x4b705c</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX                                      3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT                                                  0x4b705c</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX                                         3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS                          0x4b705e</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS                          0x4b705f</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX                 3</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS                   0x4b7859</div><div class='add'>+#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX          3</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_hdcp1kp_pkdbdec</div><div class='add'>+// base address: 0x32000000</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: cnvc_cfg_cnvc_cfgdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixID2_CNVC_FLOW_CONTROL                                                                        0x0002</div><div class='add'>+#define ixID4_CNVC_FLOW_CONTROL_2                                                                      0x0004</div><div class='add'>+#define ixID5_CNVC_REG_TO_FP_INPUT                                                                     0x0005</div><div class='add'>+#define ixID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0                                                            0x0006</div><div class='add'>+#define ixID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0                                                            0x0007</div><div class='add'>+#define ixID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1                                                            0x0008</div><div class='add'>+#define ixID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1                                                            0x0009</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: cm_cmdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixID1_CM_FLOW_CONTROL                                                                          0x0001</div><div class='add'>+#define ixID2_CM_BYPASS                                                                                0x0002</div><div class='add'>+#define ixID3_CM_REG_TO_FP_CSC_INPUT                                                                   0x0003</div><div class='add'>+#define ixID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0                                                          0x0004</div><div class='add'>+#define ixID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0                                                          0x0005</div><div class='add'>+#define ixID6_CM_REG_TO_FP_BIAS_INPUT                                                                  0x0006</div><div class='add'>+#define ixID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0                                                         0x0007</div><div class='add'>+#define ixID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0                                                         0x0008</div><div class='add'>+#define ixID9_CM_STATUS                                                                                0x0009</div><div class='add'>+#define ixIDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1                                                          0x000a</div><div class='add'>+#define ixIDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1                                                          0x000b</div><div class='add'>+#define ixIDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1                                                         0x000c</div><div class='add'>+#define ixIDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1                                                         0x000d</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mcif_wb0_mcif_wbdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixID01_WB_FMT_DBG                                                                              0x0001</div><div class='add'>+#define ixID02_WB_FMT_DBG                                                                              0x0002</div><div class='add'>+#define ixID03_WB_FMT_DBG                                                                              0x0003</div><div class='add'>+#define ixID04_WB_MGR_DBG                                                                              0x0004</div><div class='add'>+#define ixID05_WB_MGR_DBG                                                                              0x0005</div><div class='add'>+#define ixID06_WB_MGR_DBG                                                                              0x0006</div><div class='add'>+#define ixID07_WB_MGR_DBG                                                                              0x0007</div><div class='add'>+#define ixID08_WB_ARB_DBG                                                                              0x0008</div><div class='add'>+#define ixID09_WB_ARB_DBG                                                                              0x0009</div><div class='add'>+#define ixID0A_WB_ARB_DBG                                                                              0x000a</div><div class='add'>+#define ixID0B_WB_ARB_DBG                                                                              0x000b</div><div class='add'>+#define ixID0C_WB_ARB_DBG                                                                              0x000c</div><div class='add'>+#define ixID0D_WB_ARB_DBG                                                                              0x000d</div><div class='add'>+#define ixID0E_WB_ARB_DBG                                                                              0x000e</div><div class='add'>+#define ixID0F_P010_WB_FMT_DBG_Y                                                                       0x000f</div><div class='add'>+#define ixID10_P010_WB_FMT_DBG_C                                                                       0x0010</div><div class='add'>+#define ixID11_WB_ARB_P010_DBG                                                                         0x0011</div><div class='add'>+#define ixID12_WB_ARB_P010_DBG                                                                         0x0012</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpc_ocsc_mpc_ocscdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixID1_MPC_OUT0_CSC_MODE_DB                                                                     0x0001</div><div class='add'>+#define ixID2_MPC_OUT1_CSC_MODE_DB                                                                     0x0002</div><div class='add'>+#define ixID3_MPC_OUT2_CSC_MODE_DB                                                                     0x0003</div><div class='add'>+#define ixID4_MPC_OUT3_CSC_MODE_DB                                                                     0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc0_mpccdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC0_ID01_MPCC_SEL_DB                                                                       0x0001</div><div class='add'>+#define ixMPCC0_ID02_MPCC_TOP_GAIN_DB                                                                  0x0002</div><div class='add'>+#define ixMPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB                                                           0x0003</div><div class='add'>+#define ixMPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB                                                          0x0004</div><div class='add'>+#define ixMPCC0_ID05_MPCC_BG_R_CR_DB                                                                   0x0005</div><div class='add'>+#define ixMPCC0_ID06_MPCC_BG_G_Y_DB                                                                    0x0006</div><div class='add'>+#define ixMPCC0_ID07_MPCC_BG_B_CB_DB                                                                   0x0007</div><div class='add'>+#define ixMPCC0_ID08_MPCC_CONTROL_DB                                                                   0x0008</div><div class='add'>+#define ixMPCC0_ID09_MPCC_SM_CONTROL_DB                                                                0x0009</div><div class='add'>+#define ixMPCC0_ID17_MPCC_TOP_PIX                                                                      0x0011</div><div class='add'>+#define ixMPCC0_ID18_MPCC_recout_start                                                                 0x0012</div><div class='add'>+#define ixMPCC0_ID19_MPCC_recout_size                                                                  0x0013</div><div class='add'>+#define ixMPCC0_ID20_MPCC_mpc_size                                                                     0x0014</div><div class='add'>+#define ixMPCC0_ID21_MPCC_TOP_sideband                                                                 0x0015</div><div class='add'>+#define ixMPCC0_ID22_MPCC_BOT_PIX                                                                      0x0016</div><div class='add'>+#define ixMPCC0_ID23_MPCC_BOT_sideband                                                                 0x0017</div><div class='add'>+#define ixMPCC0_ID24_MPCC_OPP_PIX                                                                      0x0018</div><div class='add'>+#define ixMPCC0_ID25_MPCC_OPP_sideband                                                                 0x0019</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc1_mpccdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC1_ID01_MPCC_SEL_DB                                                                       0x0001</div><div class='add'>+#define ixMPCC1_ID02_MPCC_TOP_GAIN_DB                                                                  0x0002</div><div class='add'>+#define ixMPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB                                                           0x0003</div><div class='add'>+#define ixMPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB                                                          0x0004</div><div class='add'>+#define ixMPCC1_ID05_MPCC_BG_R_CR_DB                                                                   0x0005</div><div class='add'>+#define ixMPCC1_ID06_MPCC_BG_G_Y_DB                                                                    0x0006</div><div class='add'>+#define ixMPCC1_ID07_MPCC_BG_B_CB_DB                                                                   0x0007</div><div class='add'>+#define ixMPCC1_ID08_MPCC_CONTROL_DB                                                                   0x0008</div><div class='add'>+#define ixMPCC1_ID09_MPCC_SM_CONTROL_DB                                                                0x0009</div><div class='add'>+#define ixMPCC1_ID17_MPCC_TOP_PIX                                                                      0x0011</div><div class='add'>+#define ixMPCC1_ID18_MPCC_recout_start                                                                 0x0012</div><div class='add'>+#define ixMPCC1_ID19_MPCC_recout_size                                                                  0x0013</div><div class='add'>+#define ixMPCC1_ID20_MPCC_mpc_size                                                                     0x0014</div><div class='add'>+#define ixMPCC1_ID21_MPCC_TOP_sideband                                                                 0x0015</div><div class='add'>+#define ixMPCC1_ID22_MPCC_BOT_PIX                                                                      0x0016</div><div class='add'>+#define ixMPCC1_ID23_MPCC_BOT_sideband                                                                 0x0017</div><div class='add'>+#define ixMPCC1_ID24_MPCC_OPP_PIX                                                                      0x0018</div><div class='add'>+#define ixMPCC1_ID25_MPCC_OPP_sideband                                                                 0x0019</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc2_mpccdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC2_ID01_MPCC_SEL_DB                                                                       0x0001</div><div class='add'>+#define ixMPCC2_ID02_MPCC_TOP_GAIN_DB                                                                  0x0002</div><div class='add'>+#define ixMPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB                                                           0x0003</div><div class='add'>+#define ixMPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB                                                          0x0004</div><div class='add'>+#define ixMPCC2_ID05_MPCC_BG_R_CR_DB                                                                   0x0005</div><div class='add'>+#define ixMPCC2_ID06_MPCC_BG_G_Y_DB                                                                    0x0006</div><div class='add'>+#define ixMPCC2_ID07_MPCC_BG_B_CB_DB                                                                   0x0007</div><div class='add'>+#define ixMPCC2_ID08_MPCC_CONTROL_DB                                                                   0x0008</div><div class='add'>+#define ixMPCC2_ID09_MPCC_SM_CONTROL_DB                                                                0x0009</div><div class='add'>+#define ixMPCC2_ID17_MPCC_TOP_PIX                                                                      0x0011</div><div class='add'>+#define ixMPCC2_ID18_MPCC_recout_start                                                                 0x0012</div><div class='add'>+#define ixMPCC2_ID19_MPCC_recout_size                                                                  0x0013</div><div class='add'>+#define ixMPCC2_ID20_MPCC_mpc_size                                                                     0x0014</div><div class='add'>+#define ixMPCC2_ID21_MPCC_TOP_sideband                                                                 0x0015</div><div class='add'>+#define ixMPCC2_ID22_MPCC_BOT_PIX                                                                      0x0016</div><div class='add'>+#define ixMPCC2_ID23_MPCC_BOT_sideband                                                                 0x0017</div><div class='add'>+#define ixMPCC2_ID24_MPCC_OPP_PIX                                                                      0x0018</div><div class='add'>+#define ixMPCC2_ID25_MPCC_OPP_sideband                                                                 0x0019</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc3_mpccdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC3_ID01_MPCC_SEL_DB                                                                       0x0001</div><div class='add'>+#define ixMPCC3_ID02_MPCC_TOP_GAIN_DB                                                                  0x0002</div><div class='add'>+#define ixMPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB                                                           0x0003</div><div class='add'>+#define ixMPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB                                                          0x0004</div><div class='add'>+#define ixMPCC3_ID05_MPCC_BG_R_CR_DB                                                                   0x0005</div><div class='add'>+#define ixMPCC3_ID06_MPCC_BG_G_Y_DB                                                                    0x0006</div><div class='add'>+#define ixMPCC3_ID07_MPCC_BG_B_CB_DB                                                                   0x0007</div><div class='add'>+#define ixMPCC3_ID08_MPCC_CONTROL_DB                                                                   0x0008</div><div class='add'>+#define ixMPCC3_ID09_MPCC_SM_CONTROL_DB                                                                0x0009</div><div class='add'>+#define ixMPCC3_ID17_MPCC_TOP_PIX                                                                      0x0011</div><div class='add'>+#define ixMPCC3_ID18_MPCC_recout_start                                                                 0x0012</div><div class='add'>+#define ixMPCC3_ID19_MPCC_recout_size                                                                  0x0013</div><div class='add'>+#define ixMPCC3_ID20_MPCC_mpc_size                                                                     0x0014</div><div class='add'>+#define ixMPCC3_ID21_MPCC_TOP_sideband                                                                 0x0015</div><div class='add'>+#define ixMPCC3_ID22_MPCC_BOT_PIX                                                                      0x0016</div><div class='add'>+#define ixMPCC3_ID23_MPCC_BOT_sideband                                                                 0x0017</div><div class='add'>+#define ixMPCC3_ID24_MPCC_OPP_PIX                                                                      0x0018</div><div class='add'>+#define ixMPCC3_ID25_MPCC_OPP_sideband                                                                 0x0019</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam0_mpcc_ogamdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_OGAM0_ID01_MPCC_OGAM_CONTROL                                                            0x0001</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm0_mpcc_mcmdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER                                              0x0008</div><div class='add'>+#define ixMPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER                                              0x0009</div><div class='add'>+#define ixMPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT                                                            0x000a</div><div class='add'>+#define ixMPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP                                                    0x000b</div><div class='add'>+#define ixMPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP                                                   0x000c</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam1_mpcc_ogamdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_OGAM1_ID01_MPCC_OGAM_CONTROL                                                            0x0001</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm1_mpcc_mcmdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER                                              0x0008</div><div class='add'>+#define ixMPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER                                              0x0009</div><div class='add'>+#define ixMPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT                                                            0x000a</div><div class='add'>+#define ixMPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP                                                    0x000b</div><div class='add'>+#define ixMPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP                                                   0x000c</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam2_mpcc_ogamdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_OGAM2_ID01_MPCC_OGAM_CONTROL                                                            0x0001</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm2_mpcc_mcmdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER                                              0x0008</div><div class='add'>+#define ixMPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER                                              0x0009</div><div class='add'>+#define ixMPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT                                                            0x000a</div><div class='add'>+#define ixMPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP                                                    0x000b</div><div class='add'>+#define ixMPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP                                                   0x000c</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam3_mpcc_ogamdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_OGAM3_ID01_MPCC_OGAM_CONTROL                                                            0x0001</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm3_mpcc_mcmdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixMPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER                                              0x0008</div><div class='add'>+#define ixMPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER                                              0x0009</div><div class='add'>+#define ixMPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT                                                            0x000a</div><div class='add'>+#define ixMPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP                                                    0x000b</div><div class='add'>+#define ixMPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP                                                   0x000c</div><div class='add'>+</div><div class='add'>+// addressBlock: otg0_otgdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA1                                                                           0x0001</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA2                                                                           0x0002</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA3                                                                           0x0003</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA4                                                                           0x0004</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA5                                                                           0x0005</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA6                                                                           0x0006</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA7                                                                           0x0007</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA8                                                                           0x0008</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA9                                                                           0x0009</div><div class='add'>+#define ixOTG0_OTG_DBG_DATA10                                                                          0x000a</div><div class='add'>+#define ixOTG0_OTG_SCL_INTERFACE                                                                       0x0042</div><div class='add'>+#define ixOTG0_OTG_DOUT_INTERFACE_01_A                                                                 0x0043</div><div class='add'>+#define ixOTG0_OTG_DOUT_INTERFACE_01_B                                                                 0x0044</div><div class='add'>+#define ixOTG0_OTG_DOUT_INTERFACE_02                                                                   0x0045</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg1_otgdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA1                                                                           0x0001</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA2                                                                           0x0002</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA3                                                                           0x0003</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA4                                                                           0x0004</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA5                                                                           0x0005</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA6                                                                           0x0006</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA7                                                                           0x0007</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA8                                                                           0x0008</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA9                                                                           0x0009</div><div class='add'>+#define ixOTG1_OTG_DBG_DATA10                                                                          0x000a</div><div class='add'>+#define ixOTG1_OTG_SCL_INTERFACE                                                                       0x0042</div><div class='add'>+#define ixOTG1_OTG_DOUT_INTERFACE_01_A                                                                 0x0043</div><div class='add'>+#define ixOTG1_OTG_DOUT_INTERFACE_01_B                                                                 0x0044</div><div class='add'>+#define ixOTG1_OTG_DOUT_INTERFACE_02                                                                   0x0045</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg2_otgdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA1                                                                           0x0001</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA2                                                                           0x0002</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA3                                                                           0x0003</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA4                                                                           0x0004</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA5                                                                           0x0005</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA6                                                                           0x0006</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA7                                                                           0x0007</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA8                                                                           0x0008</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA9                                                                           0x0009</div><div class='add'>+#define ixOTG2_OTG_DBG_DATA10                                                                          0x000a</div><div class='add'>+#define ixOTG2_OTG_SCL_INTERFACE                                                                       0x0042</div><div class='add'>+#define ixOTG2_OTG_DOUT_INTERFACE_01_A                                                                 0x0043</div><div class='add'>+#define ixOTG2_OTG_DOUT_INTERFACE_01_B                                                                 0x0044</div><div class='add'>+#define ixOTG2_OTG_DOUT_INTERFACE_02                                                                   0x0045</div><div class='add'>+#define ixDCIO_DEBUG_ID                                                                                0x0000</div><div class='add'>+#define ixDCIO_DEBUG1B                                                                                 0x001b</div><div class='add'>+#define ixDCIO_DEBUG1C                                                                                 0x001c</div><div class='add'>+#define ixDCIO_DEBUG1D                                                                                 0x001d</div><div class='add'>+#define ixDCIO_DEBUG1E                                                                                 0x001e</div><div class='add'>+#define ixDCIO_DEBUG1F                                                                                 0x001f</div><div class='add'>+#define ixDCIO_DEBUG20                                                                                 0x0020</div><div class='add'>+#define ixDCIO_DEBUG21                                                                                 0x0021</div><div class='add'>+#define ixDCIO_DEBUG22                                                                                 0x0022</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg3_otgdebugind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA1                                                                           0x0001</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA2                                                                           0x0002</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA3                                                                           0x0003</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA4                                                                           0x0004</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA5                                                                           0x0005</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA6                                                                           0x0006</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA7                                                                           0x0007</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA8                                                                           0x0008</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA9                                                                           0x0009</div><div class='add'>+#define ixOTG3_OTG_DBG_DATA10                                                                          0x000a</div><div class='add'>+#define ixOTG3_OTG_SCL_INTERFACE                                                                       0x0042</div><div class='add'>+#define ixOTG3_OTG_DOUT_INTERFACE_01_A                                                                 0x0043</div><div class='add'>+#define ixOTG3_OTG_DOUT_INTERFACE_01_B                                                                 0x0044</div><div class='add'>+#define ixOTG3_OTG_DOUT_INTERFACE_02                                                                   0x0045</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_f2codecind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a</div><div class='add'>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX                                                        0x3774</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA                                                         0x3775</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791</div><div class='add'>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_descriptorind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001</div><div class='add'>+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002</div><div class='add'>+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003</div><div class='add'>+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004</div><div class='add'>+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005</div><div class='add'>+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006</div><div class='add'>+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007</div><div class='add'>+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008</div><div class='add'>+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009</div><div class='add'>+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a</div><div class='add'>+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b</div><div class='add'>+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c</div><div class='add'>+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d</div><div class='add'>+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_sinkinfoind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003</div><div class='add'>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004</div><div class='add'>+#define ixSINK_DESCRIPTION0                                                                            0x0005</div><div class='add'>+#define ixSINK_DESCRIPTION1                                                                            0x0006</div><div class='add'>+#define ixSINK_DESCRIPTION2                                                                            0x0007</div><div class='add'>+#define ixSINK_DESCRIPTION3                                                                            0x0008</div><div class='add'>+#define ixSINK_DESCRIPTION4                                                                            0x0009</div><div class='add'>+#define ixSINK_DESCRIPTION5                                                                            0x000a</div><div class='add'>+#define ixSINK_DESCRIPTION6                                                                            0x000b</div><div class='add'>+#define ixSINK_DESCRIPTION7                                                                            0x000c</div><div class='add'>+#define ixSINK_DESCRIPTION8                                                                            0x000d</div><div class='add'>+#define ixSINK_DESCRIPTION9                                                                            0x000e</div><div class='add'>+#define ixSINK_DESCRIPTION10                                                                           0x000f</div><div class='add'>+#define ixSINK_DESCRIPTION11                                                                           0x0010</div><div class='add'>+#define ixSINK_DESCRIPTION12                                                                           0x0011</div><div class='add'>+#define ixSINK_DESCRIPTION13                                                                           0x0012</div><div class='add'>+#define ixSINK_DESCRIPTION14                                                                           0x0013</div><div class='add'>+#define ixSINK_DESCRIPTION15                                                                           0x0014</div><div class='add'>+#define ixSINK_DESCRIPTION16                                                                           0x0015</div><div class='add'>+#define ixSINK_DESCRIPTION17                                                                           0x0016</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc0resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006</div><div class='add'>+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc1resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006</div><div class='add'>+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc0resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006</div><div class='add'>+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc1resultind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006</div><div class='add'>+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azinputendpoint_f2codecind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09</div><div class='add'>+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azroot_f2codecind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00</div><div class='add'>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02</div><div class='add'>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b</div><div class='add'>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream0_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream1_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream2_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream3_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream4_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream5_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream6_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream7_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream8_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream9_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003</div><div class='add'>+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream10_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream11_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream12_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream13_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream14_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream15_streamind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003</div><div class='add'>+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint0_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint1_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint2_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint3_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint4_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint5_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint6_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint7_endpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA                                           0x0027</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e</div><div class='add'>+#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS                                                0x0070</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint0_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint1_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint2_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint3_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint4_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint5_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint6_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0inputendpoint7_inputendpointind</div><div class='add'>+// base address: 0x0</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067</div><div class='add'>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h<br/>new file mode 100644<br/>index 000000000000..e3d841b2e9af<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux-arm.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h?id=c9b47175e9131118e6f221cc8fb81397d62e7c91'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h</a></div><div class='hunk'>@@ -0,0 +1,145870 @@</div><div class='add'>+#ifndef _dcn_4_1_0_SH_MASK_HEADER</div><div class='add'>+#define _dcn_4_1_0_SH_MASK_HEADER</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dccg_dccg_dfs_dispdec</div><div class='add'>+//DENTIST_DISPCLK_CNTL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L</div><div class='add'>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dccg_dccg_dispdec</div><div class='add'>+//PHYPLLA_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//PHYPLLB_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//PHYPLLC_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//PHYPLLD_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//DP_DTO_DBUF_EN</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L</div><div class='add'>+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L</div><div class='add'>+//DSCCLK3_DTO_PARAM</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DSCCLK4_DTO_PARAM</div><div class='add'>+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK4_DTO_PARAM__DSCCLK4_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DSCCLK5_DTO_PARAM</div><div class='add'>+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK5_DTO_PARAM__DSCCLK5_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPREFCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL</div><div class='add'>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L</div><div class='add'>+//DPSTREAMCLK_CNTL</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT                                                              0x7</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT                                                         0x8</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT                                                              0xb</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT                                                         0xc</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT                                                              0xf</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK                                                           0x00000007L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK                                                                0x00000008L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK                                                           0x00000070L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK                                                                0x00000080L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK                                                                0x00000800L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK                                                           0x00007000L</div><div class='add'>+#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK                                                                0x00008000L</div><div class='add'>+//REFCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//PHYPLLE_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//DCCG_GLOBAL_FGCG_REP_CNTL</div><div class='add'>+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT                                            0x0</div><div class='add'>+#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK                                              0x00000001L</div><div class='add'>+//SYMCLKG_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//DPREFCLK_CNTL</div><div class='add'>+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0</div><div class='add'>+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L</div><div class='add'>+//AOMCLK0_CNTL</div><div class='add'>+#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT                                                                 0x0</div><div class='add'>+#define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK                                                                   0x00000001L</div><div class='add'>+//AOMCLK1_CNTL</div><div class='add'>+#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT                                                                 0x0</div><div class='add'>+#define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK                                                                   0x00000001L</div><div class='add'>+//AOMCLK2_CNTL</div><div class='add'>+#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT                                                                 0x0</div><div class='add'>+#define AOMCLK2_CNTL__AOMCLK2_SOURCE_SEL__SHIFT                                                               0x10</div><div class='add'>+#define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK                                                                   0x00000001L</div><div class='add'>+#define AOMCLK2_CNTL__AOMCLK2_SOURCE_SEL_MASK                                                                 0x00010000L</div><div class='add'>+//DCCG_AUDIO_DTO2_PHASE</div><div class='add'>+#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO2_MODULO</div><div class='add'>+#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT                                                 0x0</div><div class='add'>+#define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCE_VERSION</div><div class='add'>+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0</div><div class='add'>+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8</div><div class='add'>+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL</div><div class='add'>+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L</div><div class='add'>+//PHYPLLG_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//SYMCLK32_SE_CNTL</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L</div><div class='add'>+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L</div><div class='add'>+//SYMCLK32_LE_CNTL</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_SRC_SEL__SHIFT                                                         0x8</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_EN__SHIFT                                                              0xb</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_SRC_SEL__SHIFT                                                         0xc</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_EN__SHIFT                                                              0xf</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_SRC_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_EN_MASK                                                                0x00000800L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_SRC_SEL_MASK                                                           0x00007000L</div><div class='add'>+#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_EN_MASK                                                                0x00008000L</div><div class='add'>+//DTBCLK_P_CNTL</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT                                                               0x0</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT                                                                    0x2</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT                                                               0x3</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT                                                                    0x5</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT                                                               0x6</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT                                                                    0x8</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT                                                               0x9</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT                                                                    0xb</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK                                                                 0x00000003L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK                                                                      0x00000004L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK                                                                 0x00000018L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK                                                                      0x00000020L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK                                                                 0x000000C0L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK                                                                      0x00000100L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK                                                                 0x00000600L</div><div class='add'>+#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK                                                                      0x00000800L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL5</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT                                                0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT                                                0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT                                                0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT                                                0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT                                             0x7</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT                                        0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT                                        0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT                                        0xc</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT                                             0xd</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE__SHIFT                                             0x12</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE__SHIFT                                             0x13</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE__SHIFT                                             0x14</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE__SHIFT                                             0x15</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE__SHIFT                                          0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE__SHIFT                                          0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE__SHIFT                                          0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK                                                  0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK                                                  0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK                                                  0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK                                                  0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK                                          0x00000040L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK                                               0x00000080L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK                                          0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK                                          0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK                                          0x00001000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK                                               0x00002000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE_MASK                                               0x00040000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE_MASK                                               0x00080000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE_MASK                                               0x00100000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE_MASK                                               0x00200000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE_MASK                                            0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE_MASK                                            0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE_MASK                                            0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE_MASK                                            0x08000000L</div><div class='add'>+//DSCCLK0_DTO_PARAM</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DSCCLK1_DTO_PARAM</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DSCCLK2_DTO_PARAM</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//OTG_PIXEL_RATE_DIV</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG0_TMDS_PIXEL_RATE_DIV__SHIFT                                                   0x0</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO0_INT__SHIFT                                                                 0x1</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG1_TMDS_PIXEL_RATE_DIV__SHIFT                                                   0x5</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO1_INT__SHIFT                                                                 0x6</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG2_TMDS_PIXEL_RATE_DIV__SHIFT                                                   0xa</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO2_INT__SHIFT                                                                 0xb</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG3_TMDS_PIXEL_RATE_DIV__SHIFT                                                   0xf</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO3_INT__SHIFT                                                                 0x10</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG0_TMDS_PIXEL_RATE_DIV_MASK                                                     0x00000001L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO0_INT_MASK                                                                   0x0000001EL</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG1_TMDS_PIXEL_RATE_DIV_MASK                                                     0x00000020L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO1_INT_MASK                                                                   0x000003C0L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG2_TMDS_PIXEL_RATE_DIV_MASK                                                     0x00000400L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO2_INT_MASK                                                                   0x00007800L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__OTG3_TMDS_PIXEL_RATE_DIV_MASK                                                     0x00008000L</div><div class='add'>+#define OTG_PIXEL_RATE_DIV__DPDTO3_INT_MASK                                                                   0x000F0000L</div><div class='add'>+//MILLISECOND_TIME_BASE_DIV</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL</div><div class='add'>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L</div><div class='add'>+//DISPCLK_FREQ_CHANGE_CNTL</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L</div><div class='add'>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L</div><div class='add'>+//DC_MEM_GLOBAL_PWR_REQ_CNTL</div><div class='add'>+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0</div><div class='add'>+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L</div><div class='add'>+//DISPCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL</div><div class='add'>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L</div><div class='add'>+//SOCCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//DCCG_CAC_STATUS</div><div class='add'>+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0</div><div class='add'>+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//PIXCLK1_RESYNC_CNTL</div><div class='add'>+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT                                                     0x4</div><div class='add'>+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK                                                       0x00000030L</div><div class='add'>+//PIXCLK2_RESYNC_CNTL</div><div class='add'>+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT                                                     0x4</div><div class='add'>+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK                                                       0x00000030L</div><div class='add'>+//PIXCLK0_RESYNC_CNTL</div><div class='add'>+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT                                                     0x4</div><div class='add'>+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK                                                       0x00000030L</div><div class='add'>+//MICROSECOND_TIME_BASE_DIV</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L</div><div class='add'>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE__SHIFT                                          0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE_MASK                                            0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE_MASK                                            0x08000000L</div><div class='add'>+//SYMCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//PHYPLLF_PIXCLK_RESYNC_CNTL</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L</div><div class='add'>+#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK                                                0x00000100L</div><div class='add'>+//DCCG_DISP_CNTL_REG</div><div class='add'>+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8</div><div class='add'>+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L</div><div class='add'>+//OTG0_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00001000L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO0_PHASE</div><div class='add'>+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO0_MODULO</div><div class='add'>+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG0_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG1_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00001000L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO1_PHASE</div><div class='add'>+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO1_MODULO</div><div class='add'>+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG1_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG2_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00001000L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO2_PHASE</div><div class='add'>+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO2_MODULO</div><div class='add'>+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG2_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG3_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00001000L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO3_PHASE</div><div class='add'>+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO3_MODULO</div><div class='add'>+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG3_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG4_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__DPDTO4_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__PIPE4_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__DPDTO4_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__PIPE4_DTO_SRC_SEL_MASK                                                          0x00001000L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG4_PIXEL_RATE_CNTL__OTG4_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO4_PHASE</div><div class='add'>+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO4_MODULO</div><div class='add'>+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG4_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//OTG5_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE__SHIFT                                                   0x0</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT                                                       0x5</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__DPDTO5_ENABLE_STATUS__SHIFT                                                     0x7</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL__SHIFT                                                           0x8</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL__SHIFT                                                          0x9</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__PIPE5_DTO_SRC_SEL__SHIFT                                                        0xc</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_FIFO_ERROR__SHIFT                                                      0xe</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_ERROR_COUNT__SHIFT                                                     0x10</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK                                                         0x00000020L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__DPDTO5_ENABLE_STATUS_MASK                                                       0x00000080L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL_MASK                                                             0x00000100L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL_MASK                                                            0x00000200L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__PIPE5_DTO_SRC_SEL_MASK                                                          0x00001000L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_FIFO_ERROR_MASK                                                        0x0000C000L</div><div class='add'>+#define OTG5_PIXEL_RATE_CNTL__OTG5_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L</div><div class='add'>+//DP_DTO5_PHASE</div><div class='add'>+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT                                                                   0x0</div><div class='add'>+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DP_DTO5_MODULO</div><div class='add'>+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT                                                                 0x0</div><div class='add'>+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//OTG5_PHYPLL_PIXEL_RATE_CNTL</div><div class='add'>+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0</div><div class='add'>+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4</div><div class='add'>+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L</div><div class='add'>+#define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L</div><div class='add'>+//DPPCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL</div><div class='add'>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L</div><div class='add'>+//DPPCLK0_DTO_PARAM</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK1_DTO_PARAM</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK2_DTO_PARAM</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK3_DTO_PARAM</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK4_DTO_PARAM</div><div class='add'>+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK4_DTO_PARAM__DPPCLK4_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DPPCLK5_DTO_PARAM</div><div class='add'>+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_PHASE__SHIFT                                                           0x0</div><div class='add'>+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_MODULO__SHIFT                                                          0x10</div><div class='add'>+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_PHASE_MASK                                                             0x000000FFL</div><div class='add'>+#define DPPCLK5_DTO_PARAM__DPPCLK5_DTO_MODULO_MASK                                                            0x00FF0000L</div><div class='add'>+//DCCG_CAC_STATUS2</div><div class='add'>+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0</div><div class='add'>+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL</div><div class='add'>+//SYMCLKA_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKB_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKC_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKD_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKE_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//SYMCLKF_CLOCK_ENABLE</div><div class='add'>+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_EN__SHIFT                                                            0x4</div><div class='add'>+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_SRC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_EN_MASK                                                              0x00000010L</div><div class='add'>+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_SRC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//DCCG_SOFT_RESET</div><div class='add'>+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0</div><div class='add'>+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2</div><div class='add'>+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3</div><div class='add'>+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4</div><div class='add'>+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd</div><div class='add'>+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe</div><div class='add'>+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf</div><div class='add'>+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10</div><div class='add'>+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11</div><div class='add'>+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12</div><div class='add'>+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13</div><div class='add'>+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14</div><div class='add'>+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15</div><div class='add'>+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L</div><div class='add'>+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L</div><div class='add'>+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L</div><div class='add'>+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L</div><div class='add'>+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L</div><div class='add'>+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L</div><div class='add'>+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L</div><div class='add'>+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L</div><div class='add'>+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L</div><div class='add'>+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L</div><div class='add'>+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L</div><div class='add'>+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L</div><div class='add'>+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L</div><div class='add'>+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L</div><div class='add'>+//DSCCLK_DTO_CTRL</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_EN__SHIFT                                                                    0x1</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_EN__SHIFT                                                                    0x2</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_EN__SHIFT                                                                    0x3</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_EN__SHIFT                                                                    0x4</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_EN__SHIFT                                                                    0x5</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_EN_MASK                                                                      0x00000002L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_EN_MASK                                                                      0x00000004L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_EN_MASK                                                                      0x00000008L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_EN_MASK                                                                      0x00000010L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_EN_MASK                                                                      0x00000020L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L</div><div class='add'>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L</div><div class='add'>+//DPPCLK_CTRL</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK0_EN__SHIFT                                                                        0x0</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK1_EN__SHIFT                                                                        0x3</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK2_EN__SHIFT                                                                        0x6</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK3_EN__SHIFT                                                                        0x9</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK0_EN_MASK                                                                          0x00000001L</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK1_EN_MASK                                                                          0x00000008L</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK2_EN_MASK                                                                          0x00000040L</div><div class='add'>+#define DPPCLK_CTRL__DPPCLK3_EN_MASK                                                                          0x00000200L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL6</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE__SHIFT                                             0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE__SHIFT                                             0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE__SHIFT                                             0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE__SHIFT                                             0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE__SHIFT                                             0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE__SHIFT                                             0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE__SHIFT                                      0xf</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPREFCLK_DIO_GATE_DISABLE__SHIFT                                             0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE_MASK                                               0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE_MASK                                               0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE_MASK                                               0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE_MASK                                               0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE_MASK                                               0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE_MASK                                               0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE_MASK                                        0x00008000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL6__DPREFCLK_DIO_GATE_DISABLE_MASK                                               0x01000000L</div><div class='add'>+//SYMCLK_PSP_CNTL</div><div class='add'>+#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON__SHIFT                                                           0x0</div><div class='add'>+#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON_MASK                                                             0x00000001L</div><div class='add'>+//DCCG_AUDIO_DTO_SOURCE</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000030L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L</div><div class='add'>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L</div><div class='add'>+//DCCG_AUDIO_DTO0_PHASE</div><div class='add'>+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO0_MODULE</div><div class='add'>+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0</div><div class='add'>+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO1_PHASE</div><div class='add'>+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_AUDIO_DTO1_MODULE</div><div class='add'>+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0</div><div class='add'>+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG0_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG1_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG2_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG3_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG4_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DCCG_VSYNC_OTG5_LATCH_VALUE</div><div class='add'>+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DPPCLK_DTO_CTRL</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L</div><div class='add'>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L</div><div class='add'>+//DCCG_VSYNC_CNT_CTRL</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L</div><div class='add'>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L</div><div class='add'>+//DCCG_VSYNC_CNT_INT_CTRL</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L</div><div class='add'>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L</div><div class='add'>+//FORCE_SYMCLK_DISABLE</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L</div><div class='add'>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L</div><div class='add'>+//DCCG_TEST_CLK_SEL</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_OR_DATA_GENERICA__SHIFT                                              0x9</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT                                                  0xc</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT                                              0xe</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK                                                    0x000001FFL</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_OR_DATA_GENERICA_MASK                                                0x00000200L</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK                                                    0x00001000L</div><div class='add'>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK                                                0x0000C000L</div><div class='add'>+//HDMICHARCLK0_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//HDMICHARCLK1_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK1_CLOCK_CNTL__HDMICHARCLK1_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK1_CLOCK_CNTL__HDMICHARCLK1_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK1_CLOCK_CNTL__HDMICHARCLK1_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK1_CLOCK_CNTL__HDMICHARCLK1_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//HDMICHARCLK2_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK2_CLOCK_CNTL__HDMICHARCLK2_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK2_CLOCK_CNTL__HDMICHARCLK2_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK2_CLOCK_CNTL__HDMICHARCLK2_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK2_CLOCK_CNTL__HDMICHARCLK2_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//HDMICHARCLK3_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK3_CLOCK_CNTL__HDMICHARCLK3_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK3_CLOCK_CNTL__HDMICHARCLK3_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK3_CLOCK_CNTL__HDMICHARCLK3_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK3_CLOCK_CNTL__HDMICHARCLK3_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//HDMICHARCLK4_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK4_CLOCK_CNTL__HDMICHARCLK4_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK4_CLOCK_CNTL__HDMICHARCLK4_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK4_CLOCK_CNTL__HDMICHARCLK4_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK4_CLOCK_CNTL__HDMICHARCLK4_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//HDMICHARCLK5_CLOCK_CNTL</div><div class='add'>+#define HDMICHARCLK5_CLOCK_CNTL__HDMICHARCLK5_EN__SHIFT                                                       0x0</div><div class='add'>+#define HDMICHARCLK5_CLOCK_CNTL__HDMICHARCLK5_SRC_SEL__SHIFT                                                  0x4</div><div class='add'>+#define HDMICHARCLK5_CLOCK_CNTL__HDMICHARCLK5_EN_MASK                                                         0x00000001L</div><div class='add'>+#define HDMICHARCLK5_CLOCK_CNTL__HDMICHARCLK5_SRC_SEL_MASK                                                    0x00000070L</div><div class='add'>+//PHYASYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYBSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYCSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYDSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYESYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYFSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYFSYMCLK_CLOCK_CNTL__PHYFSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//PHYGSYMCLK_CLOCK_CNTL</div><div class='add'>+#define PHYGSYMCLK_CLOCK_CNTL__PHYGSYMCLK_EN__SHIFT                                                           0x0</div><div class='add'>+#define PHYGSYMCLK_CLOCK_CNTL__PHYGSYMCLK_SRC_SEL__SHIFT                                                      0x4</div><div class='add'>+#define PHYGSYMCLK_CLOCK_CNTL__PHYGSYMCLK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define PHYGSYMCLK_CLOCK_CNTL__PHYGSYMCLK_SRC_SEL_MASK                                                        0x00000030L</div><div class='add'>+//HDMISTREAMCLK_CNTL</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT                                                     0x0</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT                                                          0x3</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK                                                       0x00000007L</div><div class='add'>+#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK                                                            0x00000008L</div><div class='add'>+//DCCG_GATE_DISABLE_CNTL3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE2_GATE_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE2_GATE_DISABLE__SHIFT                                             0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE3_GATE_DISABLE__SHIFT                                        0x1a</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE3_GATE_DISABLE__SHIFT                                             0x1b</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE2_GATE_DISABLE_MASK                                          0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE2_GATE_DISABLE_MASK                                               0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE3_GATE_DISABLE_MASK                                          0x04000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE3_GATE_DISABLE_MASK                                               0x08000000L</div><div class='add'>+//HDMISTREAMCLK0_DTO_PARAM</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L</div><div class='add'>+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dccg_dccg_dcperfmon0_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dccg_dccg_dcperfmon1_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_fgsec_dispdec</div><div class='add'>+//SECURE_GROUP0_CONFIG</div><div class='add'>+#define SECURE_GROUP0_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP0_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP0_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP0_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP1_CONFIG</div><div class='add'>+#define SECURE_GROUP1_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP1_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP1_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP1_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP2_CONFIG</div><div class='add'>+#define SECURE_GROUP2_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP2_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP2_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP2_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP3_CONFIG</div><div class='add'>+#define SECURE_GROUP3_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP3_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP3_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP3_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP4_CONFIG</div><div class='add'>+#define SECURE_GROUP4_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP4_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP4_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP4_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP5_CONFIG</div><div class='add'>+#define SECURE_GROUP5_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP5_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP5_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP5_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP6_CONFIG</div><div class='add'>+#define SECURE_GROUP6_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP6_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP6_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP6_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_GROUP7_CONFIG</div><div class='add'>+#define SECURE_GROUP7_CONFIG__WRITE_SECURE_LEVEL__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_GROUP7_CONFIG__READ_SECURE_LEVEL__SHIFT                                                        0x4</div><div class='add'>+#define SECURE_GROUP7_CONFIG__WRITE_SECURE_LEVEL_MASK                                                         0x00000007L</div><div class='add'>+#define SECURE_GROUP7_CONFIG__READ_SECURE_LEVEL_MASK                                                          0x00000070L</div><div class='add'>+//SECURE_INTERRUPT0_INFO0</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_STATUS__SHIFT                                                        0x1</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_SROUCE_ID__SHIFT                                                     0x3</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_TRUST_LEVEL__SHIFT                                                   0x14</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_SECURE_LEVEL__SHIFT                                                  0x17</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_OP__SHIFT                                                            0x1a</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_STATUS_MASK                                                          0x00000002L</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_SROUCE_ID_MASK                                                       0x000FFFF8L</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_TRUST_LEVEL_MASK                                                     0x00700000L</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_SECURE_LEVEL_MASK                                                    0x03800000L</div><div class='add'>+#define SECURE_INTERRUPT0_INFO0__SEC_INT_OP_MASK                                                              0x04000000L</div><div class='add'>+//SECURE_INTERRUPT0_INFO1</div><div class='add'>+#define SECURE_INTERRUPT0_INFO1__SEC_INT_ADDRESS__SHIFT                                                       0x0</div><div class='add'>+#define SECURE_INTERRUPT0_INFO1__SEC_INT_ADDRESS_MASK                                                         0x000FFFFFL</div><div class='add'>+//DMCUB_RBBMIF_SEC_CNTL</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT                                                  0x4</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT                                                  0x8</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL_MASK                                                      0x00000007L</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK                                                    0x00000070L</div><div class='add'>+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK                                                    0x01FFFF00L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_rbbmif_dispdec</div><div class='add'>+//RBBMIF_TIMEOUT</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL</div><div class='add'>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L</div><div class='add'>+//RBBMIF_STATUS</div><div class='add'>+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0</div><div class='add'>+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//RBBMIF_STATUS_2</div><div class='add'>+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0</div><div class='add'>+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x000000FFL</div><div class='add'>+//RBBMIF_INT_STATUS</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L</div><div class='add'>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L</div><div class='add'>+//RBBMIF_TIMEOUT_DIS</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L</div><div class='add'>+//RBBMIF_TIMEOUT_DIS_2</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT39_TIMEOUT_DIS__SHIFT                                                     0x7</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT39_TIMEOUT_DIS_MASK                                                       0x00000080L</div><div class='add'>+//RBBMIF_STATUS_FLAG</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L</div><div class='add'>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dmu_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_ihc_dispdec</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_V_UPDATE</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_VSTARTUP</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L</div><div class='add'>+//DC_GPU_TIMER_READ</div><div class='add'>+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0</div><div class='add'>+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DC_GPU_TIMER_READ_CNTL</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L</div><div class='add'>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L</div><div class='add'>+//DISP_INTERRUPT_STATUS</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                                        0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                           0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                                        0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                                       0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT                                                      0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                                          0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_AUTH_FAIL_INTERRUPT_MASK                                             0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                                          0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                                         0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK                                                        0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                               0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                  0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                               0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                              0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                                 0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_AUTH_FAIL_INTERRUPT_MASK                                    0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                                 0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                                0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                              0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                 0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                              0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                             0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                                0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_AUTH_FAIL_INTERRUPT_MASK                                   0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                                0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                               0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                              0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                 0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                              0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                             0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                                0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_AUTH_FAIL_INTERRUPT_MASK                                   0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                                0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                               0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                              0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                 0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                              0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                             0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                                0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_AUTH_FAIL_INTERRUPT_MASK                                   0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                                0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                               0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                              0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                 0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                              0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                             0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                                0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_AUTH_FAIL_INTERRUPT_MASK                                   0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                                0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                               0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT__SHIFT                               0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT__SHIFT                               0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT__SHIFT                               0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT__SHIFT                               0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT__SHIFT                               0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT__SHIFT                               0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_MASK                                 0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_MASK                                 0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_MASK                                 0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_MASK                                 0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_MASK                                 0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_MASK                                 0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                             0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                             0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                            0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                               0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_AUTH_FAIL_INTERRUPT_MASK                                  0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                               0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                              0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE20</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE21</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_AUTH_SUCCESS_INTERRUPT__SHIFT                             0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_AUTH_FAIL_INTERRUPT__SHIFT                                0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_I2C_XFER_REQ_INTERRUPT__SHIFT                             0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_I2C_XFER_DONE_INTERRUPT__SHIFT                            0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_AUTH_SUCCESS_INTERRUPT_MASK                               0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_AUTH_FAIL_INTERRUPT_MASK                                  0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_I2C_XFER_REQ_INTERRUPT_MASK                               0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_HDCP_I2C_XFER_DONE_INTERRUPT_MASK                              0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE22</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_VREADY</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_FLIP</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L</div><div class='add'>+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L</div><div class='add'>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE23</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT__SHIFT                         0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT__SHIFT                         0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT__SHIFT                         0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT__SHIFT                         0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT__SHIFT                       0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT__SHIFT                       0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT__SHIFT                       0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT__SHIFT                       0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_MASK                           0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_MASK                           0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_MASK                           0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_MASK                           0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_MASK                         0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_MASK                         0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_MASK                         0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_MASK                         0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE24</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT                              0x18</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT                              0x19</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT                              0x1a</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT                              0x1b</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT                              0x1c</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x1d</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK                                0x01000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK                                0x02000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK                                0x04000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK                                0x08000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK                                0x10000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x20000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x40000000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L</div><div class='add'>+//DISP_INTERRUPT_STATUS_CONTINUE25</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x6</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x7</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x8</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x9</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0xa</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0xb</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT                                               0xc</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT                     0xd</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX0_RDY_INTERRUPT__SHIFT                               0x10</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX1_RDY_INTERRUPT__SHIFT                               0x11</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX2_RDY_INTERRUPT__SHIFT                               0x12</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX3_RDY_INTERRUPT__SHIFT                               0x13</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX4_RDY_INTERRUPT__SHIFT                               0x14</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_OUTBOX0_RSP_INTERRUPT__SHIFT                              0x15</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_INBOX0_RSP_INTERRUPT__SHIFT                          0x16</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_OUTBOX0_RDY_INTERRUPT__SHIFT                         0x17</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000040L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000080L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000100L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000200L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000400L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00000800L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK                                                 0x00001000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK                       0x00002000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX0_RDY_INTERRUPT_MASK                                 0x00010000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX1_RDY_INTERRUPT_MASK                                 0x00020000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX2_RDY_INTERRUPT_MASK                                 0x00040000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX3_RDY_INTERRUPT_MASK                                 0x00080000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX4_RDY_INTERRUPT_MASK                                 0x00100000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_OUTBOX0_RSP_INTERRUPT_MASK                                0x00200000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_INBOX0_RSP_INTERRUPT_MASK                            0x00400000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_OUTBOX0_RDY_INTERRUPT_MASK                           0x00800000L</div><div class='add'>+#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L</div><div class='add'>+//DCCG_INTERRUPT_DEST</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L</div><div class='add'>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L</div><div class='add'>+//DMU_INTERRUPT_DEST</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x4</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT                                                  0x5</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT                                                  0x6</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT                                                  0x7</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT                                                  0x8</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT                                                0x9</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0xa</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0xb</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0xc</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0xd</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0xe</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0xf</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0x10</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0x11</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x1a</div><div class='add'>+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1b</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x00000010L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK                                                    0x00000020L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK                                                    0x00000040L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK                                                    0x00000080L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK                                                    0x00000100L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK                                                  0x00000200L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000400L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000800L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00001000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00002000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00004000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00008000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00010000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x04000000L</div><div class='add'>+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x08000000L</div><div class='add'>+//DMU_INTERRUPT_DEST2</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX0_RDY_INT_DEST__SHIFT                                         0x0</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX1_RDY_INT_DEST__SHIFT                                         0x1</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX2_RDY_INT_DEST__SHIFT                                         0x2</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX3_RDY_INT_DEST__SHIFT                                         0x3</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX4_RDY_INT_DEST__SHIFT                                         0x4</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_OUTBOX0_RSP_INT_DEST__SHIFT                                        0x5</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_INBOX0_RSP_INT_DEST__SHIFT                                    0x6</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_OUTBOX0_RDY_INT_DEST__SHIFT                                   0x7</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT                                                   0xc</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT                         0xd</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX0_RDY_INT_DEST_MASK                                           0x00000001L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX1_RDY_INT_DEST_MASK                                           0x00000002L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX2_RDY_INT_DEST_MASK                                           0x00000004L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX3_RDY_INT_DEST_MASK                                           0x00000008L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX4_RDY_INT_DEST_MASK                                           0x00000010L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_OUTBOX0_RSP_INT_DEST_MASK                                          0x00000020L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_INBOX0_RSP_INT_DEST_MASK                                      0x00000040L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_OUTBOX0_RDY_INT_DEST_MASK                                     0x00000080L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK                                                     0x00001000L</div><div class='add'>+#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK                           0x00002000L</div><div class='add'>+//DCPG_INTERRUPT_DEST</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L</div><div class='add'>+//DCPG_INTERRUPT_DEST2</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST__SHIFT                                0x6</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST__SHIFT                                0x7</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST__SHIFT                                0x8</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST__SHIFT                                0x9</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xc</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xd</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xe</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xf</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x10</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x11</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x12</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x13</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00008000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00010000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00020000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00040000L</div><div class='add'>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00080000L</div><div class='add'>+//MMHUBBUB_INTERRUPT_DEST</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L</div><div class='add'>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L</div><div class='add'>+//WB_INTERRUPT_DEST</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L</div><div class='add'>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L</div><div class='add'>+//DCHUB_INTERRUPT_DEST</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L</div><div class='add'>+//DCHUB_PERFCOUNTER_INTERRUPT_DEST</div><div class='add'>+//DCHUB_INTERRUPT_DEST2</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L</div><div class='add'>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L</div><div class='add'>+//DPP_PERFCOUNTER_INTERRUPT_DEST</div><div class='add'>+//MPC_INTERRUPT_DEST</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L</div><div class='add'>+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L</div><div class='add'>+//OPP_INTERRUPT_DEST</div><div class='add'>+//OPTC_INTERRUPT_DEST</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L</div><div class='add'>+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L</div><div class='add'>+//OTG0_INTERRUPT_DEST</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG1_INTERRUPT_DEST</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG2_INTERRUPT_DEST</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG3_INTERRUPT_DEST</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG4_INTERRUPT_DEST</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//OTG5_INTERRUPT_DEST</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L</div><div class='add'>+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L</div><div class='add'>+//DIG_INTERRUPT_DEST</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L</div><div class='add'>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L</div><div class='add'>+//I2C_DDC_HPD_INTERRUPT_DEST</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L</div><div class='add'>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L</div><div class='add'>+//HDCP_INTERRUPT_DEST</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x0</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x1</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0x2</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0x3</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x4</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x5</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0x6</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0x7</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x8</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x9</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0xa</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0xb</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0xc</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0xd</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0xe</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0xf</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x10</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x11</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0x12</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0x13</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x14</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x15</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0x16</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0x17</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x18</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x19</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0x1a</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0x1b</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_AUTH_SUCCESS_INTERRUPT_DEST__SHIFT                                0x1c</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_AUTH_FAIL_INTERRUPT_DEST__SHIFT                                   0x1d</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_I2C_XFER_REQ_INTERRUPT_DEST__SHIFT                                0x1e</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_I2C_XFER_DONE_INTERRUPT_DEST__SHIFT                               0x1f</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x00000001L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x00000002L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x00000004L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP0_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x00000008L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x00000010L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x00000020L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x00000040L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP1_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x00000080L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x00000100L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x00000200L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x00000400L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP2_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x00000800L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x00001000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x00002000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x00004000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP3_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x00008000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x00010000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x00020000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x00040000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP4_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x00080000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x00100000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x00200000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x00400000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP5_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x00800000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x01000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x02000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x04000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP6_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x08000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_AUTH_SUCCESS_INTERRUPT_DEST_MASK                                  0x10000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_AUTH_FAIL_INTERRUPT_DEST_MASK                                     0x20000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_I2C_XFER_REQ_INTERRUPT_DEST_MASK                                  0x40000000L</div><div class='add'>+#define HDCP_INTERRUPT_DEST__DOUT_IHC_HDCP7_I2C_XFER_DONE_INTERRUPT_DEST_MASK                                 0x80000000L</div><div class='add'>+//DIO_INTERRUPT_DEST</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT                                                    0x4</div><div class='add'>+#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK                                                      0x00000010L</div><div class='add'>+//DCIO_INTERRUPT_DEST</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L</div><div class='add'>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L</div><div class='add'>+//HPD_INTERRUPT_DEST</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L</div><div class='add'>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L</div><div class='add'>+//AZ_INTERRUPT_DEST</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L</div><div class='add'>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L</div><div class='add'>+//AUX_INTERRUPT_DEST</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L</div><div class='add'>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L</div><div class='add'>+//DSC_INTERRUPT_DEST</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L</div><div class='add'>+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L</div><div class='add'>+//HPO_INTERRUPT_DEST</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_DEST__SHIFT                                       0x4</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_DEST__SHIFT                                       0x5</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_DEST__SHIFT                                       0x6</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_DEST__SHIFT                                       0x7</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_DEST__SHIFT                                       0x8</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_DEST__SHIFT                                       0x9</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_DEST_MASK                                         0x00000010L</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_DEST_MASK                                         0x00000020L</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_DEST_MASK                                         0x00000040L</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_DEST_MASK                                         0x00000080L</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_DEST_MASK                                         0x00000100L</div><div class='add'>+#define HPO_INTERRUPT_DEST__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_DEST_MASK                                         0x00000200L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dmu_misc_dispdec</div><div class='add'>+//CC_DC_PIPE_DIS</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT                                                                    0xc</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK                                                                      0x00001000L</div><div class='add'>+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L</div><div class='add'>+//DMU_CLK_CNTL</div><div class='add'>+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x5</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x6</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0x7</div><div class='add'>+#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS__SHIFT                                                              0xc</div><div class='add'>+#define DMU_CLK_CNTL__IHC_FGCG_REP_DIS__SHIFT                                                                 0xd</div><div class='add'>+#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL__SHIFT                                                           0xe</div><div class='add'>+#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP__SHIFT                                                        0x10</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP__SHIFT                                                         0x12</div><div class='add'>+#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x14</div><div class='add'>+#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x16</div><div class='add'>+#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP__SHIFT                                                          0x18</div><div class='add'>+#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP__SHIFT                                                         0x1a</div><div class='add'>+#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS__SHIFT                                                                0x1c</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE__SHIFT                                                        0x1d</div><div class='add'>+#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE__SHIFT                                                         0x1e</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE__SHIFT                                                       0x1f</div><div class='add'>+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000020L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000040L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000080L</div><div class='add'>+#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS_MASK                                                                0x00001000L</div><div class='add'>+#define DMU_CLK_CNTL__IHC_FGCG_REP_DIS_MASK                                                                   0x00002000L</div><div class='add'>+#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL_MASK                                                             0x0000C000L</div><div class='add'>+#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP_MASK                                                          0x00030000L</div><div class='add'>+#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP_MASK                                                           0x000C0000L</div><div class='add'>+#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x00300000L</div><div class='add'>+#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x00C00000L</div><div class='add'>+#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP_MASK                                                            0x03000000L</div><div class='add'>+#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP_MASK                                                           0x0C000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS_MASK                                                                  0x10000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE_MASK                                                          0x20000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE_MASK                                                           0x40000000L</div><div class='add'>+#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE_MASK                                                         0x80000000L</div><div class='add'>+//DMCUB_SMU_INTERRUPT_CNTL</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT                                                        0x10</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK                                                      0x00000001L</div><div class='add'>+#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK                                                          0xFFFF0000L</div><div class='add'>+//SMU_INTERRUPT_CONTROL</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L</div><div class='add'>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L</div><div class='add'>+//DMU_SPARE</div><div class='add'>+//DMU_MISC_ALLOW_DS_FORCE</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L</div><div class='add'>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L</div><div class='add'>+//DMU_DISPCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY__SHIFT                                      0x0</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY__SHIFT                                     0x4</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY_MASK                                        0x0000000FL</div><div class='add'>+#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY_MASK                                       0x00000FF0L</div><div class='add'>+//DMU_SOCCLK_CGTT_BLK_CTRL_REG</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY__SHIFT                                        0x0</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY__SHIFT                                       0x4</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY_MASK                                          0x0000000FL</div><div class='add'>+#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY_MASK                                         0x00000FF0L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dc_pg_dispdec</div><div class='add'>+//DOMAIN0_PG_CONFIG</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN0_PG_STATUS</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN1_PG_CONFIG</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN1_PG_STATUS</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN2_PG_CONFIG</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN2_PG_STATUS</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN3_PG_CONFIG</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L</div><div class='add'>+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L</div><div class='add'>+//DOMAIN3_PG_STATUS</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L</div><div class='add'>+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L</div><div class='add'>+//DOMAIN16_PG_CONFIG</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN16_PG_STATUS</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN17_PG_CONFIG</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN17_PG_STATUS</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN18_PG_CONFIG</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN18_PG_STATUS</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN19_PG_CONFIG</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN19_PG_STATUS</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN22_PG_CONFIG</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN22_PG_STATUS</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN23_PG_CONFIG</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN23_PG_STATUS</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN24_PG_CONFIG</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN24_PG_STATUS</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DOMAIN25_PG_CONFIG</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L</div><div class='add'>+#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L</div><div class='add'>+//DOMAIN25_PG_STATUS</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L</div><div class='add'>+#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L</div><div class='add'>+//DCPG_INTERRUPT_STATUS</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L</div><div class='add'>+//DCPG_INTERRUPT_STATUS_2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L</div><div class='add'>+//DCPG_INTERRUPT_STATUS_3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED__SHIFT                                        0x0</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED__SHIFT                                        0x2</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED__SHIFT                                        0x4</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED__SHIFT                                        0x6</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L</div><div class='add'>+//DCPG_INTERRUPT_CONTROL_1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L</div><div class='add'>+//DCPG_INTERRUPT_CONTROL_2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L</div><div class='add'>+//DCPG_INTERRUPT_CONTROL_3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK__SHIFT                                           0x0</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR__SHIFT                                          0x1</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK__SHIFT                                         0x2</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK__SHIFT                                           0x4</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR__SHIFT                                          0x5</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK__SHIFT                                         0x6</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK__SHIFT                                           0x8</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK__SHIFT                                         0xa</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK__SHIFT                                           0xc</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR__SHIFT                                          0xd</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK__SHIFT                                         0xe</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK_MASK                                             0x00000001L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR_MASK                                            0x00000002L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK_MASK                                           0x00000004L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK_MASK                                             0x00000010L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR_MASK                                            0x00000020L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK_MASK                                           0x00000040L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK_MASK                                             0x00000100L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK_MASK                                           0x00000400L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK_MASK                                             0x00001000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR_MASK                                            0x00002000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK_MASK                                           0x00004000L</div><div class='add'>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L</div><div class='add'>+//DC_IP_REQUEST_CNTL</div><div class='add'>+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0</div><div class='add'>+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L</div><div class='add'>+//DC_PGCNTL_STATUS_REG</div><div class='add'>+//LONO_MEM_PWR_REQ_CNTL</div><div class='add'>+#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS__SHIFT                                                    0x0</div><div class='add'>+#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS_MASK                                                      0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dmu_dmcub_dispdec</div><div class='add'>+//DMCUB_REGION0_OFFSET</div><div class='add'>+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION0_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION1_OFFSET</div><div class='add'>+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION1_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION2_OFFSET</div><div class='add'>+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION2_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION4_OFFSET</div><div class='add'>+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION4_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION5_OFFSET</div><div class='add'>+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION5_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION6_OFFSET</div><div class='add'>+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION6_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION7_OFFSET</div><div class='add'>+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8</div><div class='add'>+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION7_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL</div><div class='add'>+//DMCUB_REGION0_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION1_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION2_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION4_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION5_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION6_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION7_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW0_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW1_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW2_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW3_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW4_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW5_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW6_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW7_BASE_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL</div><div class='add'>+//DMCUB_REGION3_CW0_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW1_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW2_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW3_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW4_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW5_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW6_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW7_TOP_ADDRESS</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL</div><div class='add'>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L</div><div class='add'>+//DMCUB_REGION3_CW0_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW0_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW1_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW1_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW2_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW2_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW3_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW3_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW4_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW4_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW5_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW5_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW6_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW6_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_REGION3_CW7_OFFSET</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L</div><div class='add'>+//DMCUB_REGION3_CW7_OFFSET_HIGH</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0</div><div class='add'>+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL</div><div class='add'>+//DMCUB_INTERRUPT_ENABLE</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT                                                    0xd</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT                                                    0xe</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT                                                    0xf</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT                                                    0x10</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT                                                  0x11</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0x12</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX0_RDY_INT_EN__SHIFT                                            0x13</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX1_RDY_INT_EN__SHIFT                                            0x14</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX2_RDY_INT_EN__SHIFT                                            0x15</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX3_RDY_INT_EN__SHIFT                                            0x16</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX4_RDY_INT_EN__SHIFT                                            0x17</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_OUTBOX0_RSP_INT_EN__SHIFT                                           0x18</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK                                                      0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK                                                      0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK                                                      0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK                                                      0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK                                                    0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00040000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX0_RDY_INT_EN_MASK                                              0x00080000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX1_RDY_INT_EN_MASK                                              0x00100000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX2_RDY_INT_EN_MASK                                              0x00200000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX3_RDY_INT_EN_MASK                                              0x00400000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX4_RDY_INT_EN_MASK                                              0x00800000L</div><div class='add'>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_OUTBOX0_RSP_INT_EN_MASK                                             0x01000000L</div><div class='add'>+//DMCUB_INTERRUPT_ACK</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT                                                      0xd</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT                                                      0xe</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT                                                      0xf</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT                                                      0x10</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT                                                    0x11</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0x12</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX0_RDY_INT_ACK__SHIFT                                              0x13</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX1_RDY_INT_ACK__SHIFT                                              0x14</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX2_RDY_INT_ACK__SHIFT                                              0x15</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX3_RDY_INT_ACK__SHIFT                                              0x16</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX4_RDY_INT_ACK__SHIFT                                              0x17</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_OUTBOX0_RSP_INT_ACK__SHIFT                                             0x18</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK                                                        0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK                                                        0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK                                                        0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK                                                        0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK                                                      0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00040000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX0_RDY_INT_ACK_MASK                                                0x00080000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX1_RDY_INT_ACK_MASK                                                0x00100000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX2_RDY_INT_ACK_MASK                                                0x00200000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX3_RDY_INT_ACK_MASK                                                0x00400000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX4_RDY_INT_ACK_MASK                                                0x00800000L</div><div class='add'>+#define DMCUB_INTERRUPT_ACK__DMCUB_REG_OUTBOX0_RSP_INT_ACK_MASK                                               0x01000000L</div><div class='add'>+//DMCUB_INTERRUPT_STATUS</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT                                                  0xd</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT                                                  0xe</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT                                                  0xf</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT                                                  0x10</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT                                                0x11</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0x12</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0x13</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0x14</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT__SHIFT                                             0x15</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT__SHIFT                                         0x16</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX0_RDY_INT_STAT__SHIFT                                          0x17</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX1_RDY_INT_STAT__SHIFT                                          0x18</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX2_RDY_INT_STAT__SHIFT                                          0x19</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX3_RDY_INT_STAT__SHIFT                                          0x1a</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX4_RDY_INT_STAT__SHIFT                                          0x1b</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_OUTBOX0_RSP_INT_STAT__SHIFT                                         0x1c</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK                                                    0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK                                                    0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK                                                    0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK                                                    0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK                                                  0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00040000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00080000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00100000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT_MASK                                               0x00200000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT_MASK                                           0x00400000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX0_RDY_INT_STAT_MASK                                            0x00800000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX1_RDY_INT_STAT_MASK                                            0x01000000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX2_RDY_INT_STAT_MASK                                            0x02000000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX3_RDY_INT_STAT_MASK                                            0x04000000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX4_RDY_INT_STAT_MASK                                            0x08000000L</div><div class='add'>+#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_OUTBOX0_RSP_INT_STAT_MASK                                           0x10000000L</div><div class='add'>+//DMCUB_INTERRUPT_TYPE</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT                                                    0xd</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT                                                    0xe</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT                                                    0xf</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT                                                    0x10</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT                                                  0x11</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0x12</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK                                                      0x00002000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK                                                      0x00004000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK                                                      0x00008000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK                                                      0x00010000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK                                                    0x00020000L</div><div class='add'>+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00040000L</div><div class='add'>+//DMCUB_EXT_INTERRUPT_STATUS</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L</div><div class='add'>+//DMCUB_EXT_INTERRUPT_CTXID</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL</div><div class='add'>+//DMCUB_EXT_INTERRUPT_ACK</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0</div><div class='add'>+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L</div><div class='add'>+//DMCUB_INST_FETCH_FAULT_ADDR</div><div class='add'>+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0</div><div class='add'>+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_DATA_WRITE_FAULT_ADDR</div><div class='add'>+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0</div><div class='add'>+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_SEC_CNTL</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L</div><div class='add'>+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L</div><div class='add'>+//DMCUB_MEM_CNTL</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL</div><div class='add'>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L</div><div class='add'>+//DMCUB_INBOX0_BASE_ADDRESS</div><div class='add'>+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX0_SIZE</div><div class='add'>+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX0_WPTR</div><div class='add'>+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX0_RPTR</div><div class='add'>+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_BASE_ADDRESS</div><div class='add'>+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_SIZE</div><div class='add'>+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_WPTR</div><div class='add'>+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_INBOX1_RPTR</div><div class='add'>+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0</div><div class='add'>+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_BASE_ADDRESS</div><div class='add'>+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_SIZE</div><div class='add'>+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_WPTR</div><div class='add'>+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX0_RPTR</div><div class='add'>+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_BASE_ADDRESS</div><div class='add'>+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_SIZE</div><div class='add'>+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_WPTR</div><div class='add'>+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_OUTBOX1_RPTR</div><div class='add'>+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_TIMER_TRIGGER0</div><div class='add'>+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0</div><div class='add'>+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_TIMER_TRIGGER1</div><div class='add'>+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0</div><div class='add'>+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_TIMER_WINDOW</div><div class='add'>+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0</div><div class='add'>+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L</div><div class='add'>+//DMCUB_SCRATCH0</div><div class='add'>+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH1</div><div class='add'>+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH2</div><div class='add'>+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH3</div><div class='add'>+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH4</div><div class='add'>+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH5</div><div class='add'>+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH6</div><div class='add'>+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH7</div><div class='add'>+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH8</div><div class='add'>+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH9</div><div class='add'>+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0</div><div class='add'>+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH10</div><div class='add'>+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH11</div><div class='add'>+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH12</div><div class='add'>+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH13</div><div class='add'>+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH14</div><div class='add'>+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH15</div><div class='add'>+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH16</div><div class='add'>+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH17</div><div class='add'>+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH18</div><div class='add'>+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_CNTL</div><div class='add'>+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0</div><div class='add'>+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8</div><div class='add'>+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10</div><div class='add'>+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12</div><div class='add'>+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13</div><div class='add'>+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14</div><div class='add'>+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL</div><div class='add'>+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L</div><div class='add'>+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L</div><div class='add'>+//DMCUB_GPINT_DATAIN0</div><div class='add'>+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN1</div><div class='add'>+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAOUT</div><div class='add'>+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR</div><div class='add'>+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0</div><div class='add'>+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL</div><div class='add'>+//DMCUB_LS_WAKE_INT_ENABLE</div><div class='add'>+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0</div><div class='add'>+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DMCUB_MEM_PWR_CNTL</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L</div><div class='add'>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L</div><div class='add'>+//DMCUB_TIMER_CURRENT</div><div class='add'>+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_DBG_BUS_SELECT</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_DMCUBCLK_SEL__SHIFT                                               0x0</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_DMCUBCLK_SEL2__SHIFT                                              0x5</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_DISPCLK_SEL__SHIFT                                                0xa</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_SOCCLK_SEL__SHIFT                                                 0xe</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_DMCUBCLK_SEL_MASK                                                 0x0000001FL</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_DMCUBCLK_SEL2_MASK                                                0x000003E0L</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_DISPCLK_SEL_MASK                                                  0x00001C00L</div><div class='add'>+#define DMCUB_DBG_BUS_SELECT__DMCUB_DBG_BUS_SOCCLK_SEL_MASK                                                   0x0001C000L</div><div class='add'>+//DMCUB_PROC_ID</div><div class='add'>+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL</div><div class='add'>+//DMCUB_CNTL2</div><div class='add'>+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0</div><div class='add'>+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L</div><div class='add'>+//DMCUB_GPINT_DATAIN2</div><div class='add'>+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN3</div><div class='add'>+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN4</div><div class='add'>+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN5</div><div class='add'>+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_GPINT_DATAIN6</div><div class='add'>+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT                                                       0x0</div><div class='add'>+#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//DMCUB_REGION3_TMR_AXI_SPACE</div><div class='add'>+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT                                       0x0</div><div class='add'>+#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK                                         0x07L</div><div class='add'>+//DMCUB_SCRATCH19</div><div class='add'>+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH20</div><div class='add'>+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH21</div><div class='add'>+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH22</div><div class='add'>+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//DMCUB_SCRATCH23</div><div class='add'>+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT                                                               0x0</div><div class='add'>+#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//HOST_INTERRUPT_CSR</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_EN__SHIFT                                                 0x0</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_EN__SHIFT                                                0x1</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_ACK__SHIFT                                                0x8</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_ACK__SHIFT                                               0x9</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_STAT__SHIFT                                               0xc</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_STAT__SHIFT                                              0xd</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_EN_MASK                                                  0x00000002L</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_ACK_MASK                                                  0x00000100L</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_ACK_MASK                                                 0x00000200L</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_STAT_MASK                                                 0x00001000L</div><div class='add'>+#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_STAT_MASK                                                0x00002000L</div><div class='add'>+//DMCUB_REG_INBOX0_RDY</div><div class='add'>+#define DMCUB_REG_INBOX0_RDY__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_RDY__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG0__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG0__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG1</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG1__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG1__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG2</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG2__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG2__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG3</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG3__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG3__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG4</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG4__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG4__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG5</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG5__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG5__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG6</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG6__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG6__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG7</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG7__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG7__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG8</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG8__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG8__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG9</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG9__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG9__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG10</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG10__DATA__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG10__DATA_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG11</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG11__DATA__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG11__DATA_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG12</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG12__DATA__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG12__DATA_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG13</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG13__DATA__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG13__DATA_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_MSG14</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG14__DATA__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_MSG14__DATA_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX0_RSP</div><div class='add'>+#define DMCUB_REG_INBOX0_RSP__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX0_RSP__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_OUTBOX0_RDY</div><div class='add'>+#define DMCUB_REG_OUTBOX0_RDY__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_OUTBOX0_RDY__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_OUTBOX0_MSG0</div><div class='add'>+#define DMCUB_REG_OUTBOX0_MSG0__DATA__SHIFT                                                                   0x0</div><div class='add'>+#define DMCUB_REG_OUTBOX0_MSG0__DATA_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_OUTBOX0_RSP</div><div class='add'>+#define DMCUB_REG_OUTBOX0_RSP__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_OUTBOX0_RSP__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX1_RDY</div><div class='add'>+#define DMCUB_REG_INBOX1_RDY__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX1_RDY__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX1_MSG0</div><div class='add'>+#define DMCUB_REG_INBOX1_MSG0__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX1_MSG0__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX1_MSG1</div><div class='add'>+#define DMCUB_REG_INBOX1_MSG1__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX1_MSG1__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX1_RSP</div><div class='add'>+#define DMCUB_REG_INBOX1_RSP__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX1_RSP__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX2_RDY</div><div class='add'>+#define DMCUB_REG_INBOX2_RDY__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX2_RDY__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX2_MSG0</div><div class='add'>+#define DMCUB_REG_INBOX2_MSG0__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX2_MSG0__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX2_MSG1</div><div class='add'>+#define DMCUB_REG_INBOX2_MSG1__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX2_MSG1__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX2_RSP</div><div class='add'>+#define DMCUB_REG_INBOX2_RSP__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX2_RSP__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX3_RDY</div><div class='add'>+#define DMCUB_REG_INBOX3_RDY__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX3_RDY__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX3_MSG0</div><div class='add'>+#define DMCUB_REG_INBOX3_MSG0__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX3_MSG0__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX3_MSG1</div><div class='add'>+#define DMCUB_REG_INBOX3_MSG1__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX3_MSG1__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX3_RSP</div><div class='add'>+#define DMCUB_REG_INBOX3_RSP__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX3_RSP__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX4_RDY</div><div class='add'>+#define DMCUB_REG_INBOX4_RDY__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX4_RDY__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX4_MSG0</div><div class='add'>+#define DMCUB_REG_INBOX4_MSG0__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX4_MSG0__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX4_MSG1</div><div class='add'>+#define DMCUB_REG_INBOX4_MSG1__DATA__SHIFT                                                                    0x0</div><div class='add'>+#define DMCUB_REG_INBOX4_MSG1__DATA_MASK                                                                      0xFFFFFFFFL</div><div class='add'>+//DMCUB_REG_INBOX4_RSP</div><div class='add'>+#define DMCUB_REG_INBOX4_RSP__DATA__SHIFT                                                                     0x0</div><div class='add'>+#define DMCUB_REG_INBOX4_RSP__DATA_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_wb0_dispdec_dwb_top_dispdec</div><div class='add'>+//DWB_ENABLE_CLK_CTRL</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS__SHIFT                                                          0x18</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L</div><div class='add'>+#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS_MASK                                                            0x01000000L</div><div class='add'>+//DWB_MEM_PWR_CTRL</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L</div><div class='add'>+//FC_MODE_CTRL</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4</div><div class='add'>+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8</div><div class='add'>+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc</div><div class='add'>+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10</div><div class='add'>+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L</div><div class='add'>+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L</div><div class='add'>+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L</div><div class='add'>+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L</div><div class='add'>+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L</div><div class='add'>+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L</div><div class='add'>+//FC_FLOW_CTRL</div><div class='add'>+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL</div><div class='add'>+//FC_WINDOW_START</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL</div><div class='add'>+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L</div><div class='add'>+//FC_WINDOW_SIZE</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL</div><div class='add'>+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L</div><div class='add'>+//FC_SOURCE_SIZE</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL</div><div class='add'>+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L</div><div class='add'>+//DWB_UPDATE_CTRL</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L</div><div class='add'>+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L</div><div class='add'>+//DWB_CRC_CTRL</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L</div><div class='add'>+//DWB_CRC_MASK_R_G</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL</div><div class='add'>+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L</div><div class='add'>+//DWB_CRC_MASK_B_A</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L</div><div class='add'>+//DWB_CRC_VAL_R_G</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L</div><div class='add'>+//DWB_CRC_VAL_B_A</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L</div><div class='add'>+//DWB_OUT_CTRL</div><div class='add'>+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0</div><div class='add'>+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14</div><div class='add'>+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L</div><div class='add'>+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L</div><div class='add'>+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L</div><div class='add'>+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L</div><div class='add'>+//DWB_MMHUBBUB_BACKPRESSURE_CNT</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0</div><div class='add'>+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL</div><div class='add'>+//DWB_HOST_READ_CONTROL</div><div class='add'>+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL</div><div class='add'>+//DWB_OVERFLOW_STATUS</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L</div><div class='add'>+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L</div><div class='add'>+//DWB_OVERFLOW_COUNTER</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L</div><div class='add'>+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L</div><div class='add'>+//DWB_SOFT_RESET</div><div class='add'>+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0</div><div class='add'>+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_wb0_dispdec_dwbcp_dispdec</div><div class='add'>+//DWB_HDR_MULT_COEF</div><div class='add'>+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0</div><div class='add'>+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL</div><div class='add'>+//DWB_GAMUT_REMAP_MODE</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L</div><div class='add'>+//DWB_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0</div><div class='add'>+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L</div><div class='add'>+//DWB_GAMUT_REMAPA_C11_C12</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C13_C14</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C21_C22</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C23_C24</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C31_C32</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPA_C33_C34</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C11_C12</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C13_C14</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C21_C22</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C23_C24</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C31_C32</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_GAMUT_REMAPB_C33_C34</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL</div><div class='add'>+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L</div><div class='add'>+//DWB_OGAM_CONTROL</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L</div><div class='add'>+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L</div><div class='add'>+//DWB_OGAM_LUT_INDEX</div><div class='add'>+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0</div><div class='add'>+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL</div><div class='add'>+//DWB_OGAM_LUT_DATA</div><div class='add'>+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0</div><div class='add'>+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL</div><div class='add'>+//DWB_OGAM_LUT_CONTROL</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L</div><div class='add'>+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L</div><div class='add'>+//DWB_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L</div><div class='add'>+//DWB_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0</div><div class='add'>+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL</div><div class='add'>+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L</div><div class='add'>+//DWB_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL</div><div class='add'>+//DWB_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+//DWB_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L</div><div class='add'>+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mmhubbub_mcif_wb0_dispdec</div><div class='add'>+//MCIF_WB_BUFMGR_SW_CONTROL</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L</div><div class='add'>+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L</div><div class='add'>+//MCIF_WB_BUFMGR_STATUS</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x0</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x1</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000001L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000002L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L</div><div class='add'>+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L</div><div class='add'>+//MCIF_WB_BUF_PITCH</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L</div><div class='add'>+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L</div><div class='add'>+//MCIF_WB_BUF_1_STATUS</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_1_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_BUF_2_STATUS</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_2_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_BUF_3_STATUS</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_3_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_BUF_4_STATUS</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_4_STATUS2</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L</div><div class='add'>+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L</div><div class='add'>+//MCIF_WB_ARBITRATION_CONTROL</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L</div><div class='add'>+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L</div><div class='add'>+//MCIF_WB_SCLK_CHANGE</div><div class='add'>+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0</div><div class='add'>+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_Y</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_C</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//MCIF_WB_BUFMGR_VCE_CONTROL</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L</div><div class='add'>+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L</div><div class='add'>+//MCIF_WB_NB_PSTATE_CONTROL</div><div class='add'>+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1</div><div class='add'>+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L</div><div class='add'>+//MCIF_WB_CLOCK_GATER_CONTROL</div><div class='add'>+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0</div><div class='add'>+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L</div><div class='add'>+//MCIF_WB_SELF_REFRESH_CONTROL</div><div class='add'>+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1</div><div class='add'>+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L</div><div class='add'>+//MULTI_LEVEL_QOS_CTRL</div><div class='add'>+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0</div><div class='add'>+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL</div><div class='add'>+//MCIF_WB_SECURITY_LEVEL</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                                 0x0</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT                                                          0x4</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                                   0x00000007L</div><div class='add'>+#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK                                                            0x00000070L</div><div class='add'>+//MCIF_WB_BUF_LUMA_SIZE</div><div class='add'>+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0</div><div class='add'>+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL</div><div class='add'>+//MCIF_WB_BUF_CHROMA_SIZE</div><div class='add'>+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0</div><div class='add'>+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_1_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_2_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_3_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_Y_HIGH</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_4_ADDR_C_HIGH</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0</div><div class='add'>+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL</div><div class='add'>+//MCIF_WB_BUF_1_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_2_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_3_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_BUF_4_RESOLUTION</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL</div><div class='add'>+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L</div><div class='add'>+//MCIF_WB_PSTATE_CHANGE_DURATION_VBI</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x0</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT                    0x10</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0x0000FFFFL</div><div class='add'>+#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK                      0xFFFF0000L</div><div class='add'>+//MCIF_WB_VMID_CONTROL</div><div class='add'>+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0</div><div class='add'>+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL</div><div class='add'>+//MCIF_WB_MIN_TTO</div><div class='add'>+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0</div><div class='add'>+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mmhubbub_mmhubbub_dispdec</div><div class='add'>+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT                           0x1f</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L</div><div class='add'>+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK                             0x80000000L</div><div class='add'>+//MCIF_WB_WATERMARK</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL</div><div class='add'>+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L</div><div class='add'>+//MMHUBBUB_WARMUP_CONFIG</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L</div><div class='add'>+//MMHUBBUB_WARMUP_CONTROL_STATUS</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L</div><div class='add'>+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L</div><div class='add'>+//MMHUBBUB_WARMUP_BASE_ADDR_LOW</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL</div><div class='add'>+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL</div><div class='add'>+//MMHUBBUB_WARMUP_ADDR_REGION</div><div class='add'>+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL</div><div class='add'>+//MMHUBBUB_MIN_TTO</div><div class='add'>+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0</div><div class='add'>+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL</div><div class='add'>+//MMHUBBUB_CTRL</div><div class='add'>+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0</div><div class='add'>+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L</div><div class='add'>+//WBIF_SMU_WM_CONTROL</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L</div><div class='add'>+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L</div><div class='add'>+//WBIF0_MISC_CTRL</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L</div><div class='add'>+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L</div><div class='add'>+//WBIF0_PHASE0_OUTSTANDING_COUNTER</div><div class='add'>+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0</div><div class='add'>+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL</div><div class='add'>+//WBIF0_PHASE1_OUTSTANDING_COUNTER</div><div class='add'>+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0</div><div class='add'>+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL</div><div class='add'>+//MMHUBBUB_MEM_PWR_STATUS</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L</div><div class='add'>+//MMHUBBUB_MEM_PWR_CNTL</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L</div><div class='add'>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L</div><div class='add'>+//MMHUBBUB_CLOCK_CNTL</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x11</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L</div><div class='add'>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK                                                       0x00020000L</div><div class='add'>+//MMHUBBUB_SOFT_RESET</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L</div><div class='add'>+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L</div><div class='add'>+//DMU_IF_ERR_STATUS</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L</div><div class='add'>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L</div><div class='add'>+//MMHUBBUB_CLIENT_UNIT_ID</div><div class='add'>+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8</div><div class='add'>+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L</div><div class='add'>+//MMHUBBUB_WARMUP_VMID_CONTROL</div><div class='add'>+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0</div><div class='add'>+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0controller_dispdec</div><div class='add'>+//AZALIA_CONTROLLER_CLOCK_GATING</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L</div><div class='add'>+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L</div><div class='add'>+//AZALIA_AUDIO_DTO</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL</div><div class='add'>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L</div><div class='add'>+//AZALIA_AUDIO_DTO_CONTROL</div><div class='add'>+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8</div><div class='add'>+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L</div><div class='add'>+//AZALIA_SOCCLK_CONTROL</div><div class='add'>+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1</div><div class='add'>+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L</div><div class='add'>+//AZALIA_UNDERFLOW_FILLER_SAMPLE</div><div class='add'>+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0</div><div class='add'>+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_DATA_DMA_CONTROL</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L</div><div class='add'>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L</div><div class='add'>+//AZALIA_BDL_DMA_CONTROL</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L</div><div class='add'>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L</div><div class='add'>+//AZALIA_RIRB_AND_DP_CONTROL</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L</div><div class='add'>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L</div><div class='add'>+//AZALIA_CORB_DMA_CONTROL</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L</div><div class='add'>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L</div><div class='add'>+//AZALIA_GLOBAL_CAPABILITIES</div><div class='add'>+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1</div><div class='add'>+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L</div><div class='add'>+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL</div><div class='add'>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L</div><div class='add'>+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L</div><div class='add'>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L</div><div class='add'>+//AZALIA_INPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL</div><div class='add'>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL1</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL2</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CONTROL3</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC0_RESULT</div><div class='add'>+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL1</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL2</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CONTROL3</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L</div><div class='add'>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L</div><div class='add'>+//AZALIA_INPUT_CRC1_RESULT</div><div class='add'>+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CONTROL0</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L</div><div class='add'>+//AZALIA_CRC0_CONTROL1</div><div class='add'>+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CONTROL2</div><div class='add'>+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL</div><div class='add'>+//AZALIA_CRC0_CONTROL3</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L</div><div class='add'>+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L</div><div class='add'>+//AZALIA_CRC0_RESULT</div><div class='add'>+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0</div><div class='add'>+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CONTROL0</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L</div><div class='add'>+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L</div><div class='add'>+//AZALIA_CRC1_CONTROL1</div><div class='add'>+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CONTROL2</div><div class='add'>+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL</div><div class='add'>+//AZALIA_CRC1_CONTROL3</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L</div><div class='add'>+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L</div><div class='add'>+//AZALIA_CRC1_RESULT</div><div class='add'>+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0</div><div class='add'>+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_SOFT_RESET</div><div class='add'>+#define AZALIA_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                           0x0</div><div class='add'>+#define AZALIA_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                             0x00000001L</div><div class='add'>+//AZALIA_MEM_PWR_CTRL</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L</div><div class='add'>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L</div><div class='add'>+//AZALIA_MEM_PWR_STATUS</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L</div><div class='add'>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0root_dispdec</div><div class='add'>+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0</div><div class='add'>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L</div><div class='add'>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L</div><div class='add'>+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL</div><div class='add'>+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0</div><div class='add'>+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L</div><div class='add'>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0</div><div class='add'>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL</div><div class='add'>+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L</div><div class='add'>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L</div><div class='add'>+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L</div><div class='add'>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L</div><div class='add'>+//REG_DC_AUDIO_PORT_CONNECTIVITY</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L</div><div class='add'>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L</div><div class='add'>+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L</div><div class='add'>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_az_misc_dispdec</div><div class='add'>+//AZ_CLOCK_CNTL</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0</div><div class='add'>+#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS__SHIFT                                                          0x1</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x4</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x8</div><div class='add'>+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0xc</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_GATE_DIS__SHIFT                                                                   0x10</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY__SHIFT                                                              0x14</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY__SHIFT                                                             0x18</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L</div><div class='add'>+#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS_MASK                                                            0x00000002L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000010L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00000100L</div><div class='add'>+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x0000F000L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_GATE_DIS_MASK                                                                     0x00010000L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY_MASK                                                                0x00F00000L</div><div class='add'>+#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY_MASK                                                               0xFF000000L</div><div class='add'>+//AZ_MEM_GLOBAL_PWR_REQ_CNTL</div><div class='add'>+#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0</div><div class='add'>+#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L</div><div class='add'>+//AZ_STRAPS</div><div class='add'>+#define AZ_STRAPS__AUDIO_PORT_CONNECTIVITY__SHIFT                                                             0x0</div><div class='add'>+#define AZ_STRAPS__AUDIO_STREAM_NUMBER__SHIFT                                                                 0x4</div><div class='add'>+#define AZ_STRAPS__AUDIO_PORT_CONNECTIVITY_MASK                                                               0x00000007L</div><div class='add'>+#define AZ_STRAPS__AUDIO_STREAM_NUMBER_MASK                                                                   0x00000070L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_az_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream0_dispdec</div><div class='add'>+//AZF0STREAM0_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM0_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream1_dispdec</div><div class='add'>+//AZF0STREAM1_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM1_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream2_dispdec</div><div class='add'>+//AZF0STREAM2_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM2_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream3_dispdec</div><div class='add'>+//AZF0STREAM3_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM3_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream4_dispdec</div><div class='add'>+//AZF0STREAM4_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM4_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream5_dispdec</div><div class='add'>+//AZF0STREAM5_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM5_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream6_dispdec</div><div class='add'>+//AZF0STREAM6_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM6_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream7_dispdec</div><div class='add'>+//AZF0STREAM7_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM7_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream8_dispdec</div><div class='add'>+//AZF0STREAM8_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM8_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream9_dispdec</div><div class='add'>+//AZF0STREAM9_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L</div><div class='add'>+//AZF0STREAM9_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream10_dispdec</div><div class='add'>+//AZF0STREAM10_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM10_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream11_dispdec</div><div class='add'>+//AZF0STREAM11_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM11_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream12_dispdec</div><div class='add'>+//AZF0STREAM12_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM12_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream13_dispdec</div><div class='add'>+//AZF0STREAM13_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM13_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream14_dispdec</div><div class='add'>+//AZF0STREAM14_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM14_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0stream15_dispdec</div><div class='add'>+//AZF0STREAM15_AZALIA_STREAM_INDEX</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L</div><div class='add'>+//AZF0STREAM15_AZALIA_STREAM_DATA</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint0_dispdec</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint1_dispdec</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint2_dispdec</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint3_dispdec</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint4_dispdec</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint5_dispdec</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint6_dispdec</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0endpoint7_dispdec</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL</div><div class='add'>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint0_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint1_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint2_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint3_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint4_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint5_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint6_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azf0inputendpoint7_dispdec</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL</div><div class='add'>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0</div><div class='add'>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_dispdec</div><div class='add'>+//DCHUBBUB_ARB_DF_REQ_OUTSTAND</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xb</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000003FFL</div><div class='add'>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF800L</div><div class='add'>+//DCHUBBUB_ARB_SAT_LEVEL</div><div class='add'>+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_ARB_QOS_FORCE</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT         0x9</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L</div><div class='add'>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK           0x00000200L</div><div class='add'>+//DCHUBBUB_ARB_DRAM_STATE_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0x2</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT                                          0x7</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE__SHIFT                  0xd</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DISABL_EXIT_DEEPSLEEP_WHEN_PREFETCH_START_PENDING__SHIFT   0xe</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE__SHIFT                 0x10</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE__SHIFT                0x11</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY__SHIFT                0x12</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS__SHIFT                        0x18</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000004L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK                                            0x00000080L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE_MASK                    0x00002000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DISABL_EXIT_DEEPSLEEP_WHEN_PREFETCH_START_PENDING_MASK     0x00004000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE_MASK                   0x00010000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE_MASK                  0x00020000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY_MASK                  0x00040000L</div><div class='add'>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS_MASK                          0xFF000000L</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT                                         0x1</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT                0x8</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT               0x9</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT  0xa</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT  0xb</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK                                         0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK                                           0x00000002L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK                  0x00000100L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK                 0x00000200L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK  0x00000400L</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK  0x00000800L</div><div class='add'>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK                 0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A__DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A__SHIFT                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A__DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A_MASK                         0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A_MASK               0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A_MASK               0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A_MASK               0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A__SHIFT     0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A_MASK       0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A__SHIFT     0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A_MASK       0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_MALL_A</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_MALL_A__DCHUBBUB_ARB_FRAC_URG_BW_MALL_A__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_MALL_A__DCHUBBUB_ARB_FRAC_URG_BW_MALL_A_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0</div><div class='add'>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK                 0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B__DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B__SHIFT                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B__DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B_MASK                         0x00003FFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B_MASK               0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B_MASK               0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B__SHIFT             0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B_MASK               0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B__SHIFT               0x0</div><div class='add'>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B_MASK                 0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B__SHIFT     0x0</div><div class='add'>+#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B_MASK       0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT       0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK         0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B__SHIFT     0x0</div><div class='add'>+#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B_MASK       0x0000FFFFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_FRAC_URG_BW_MALL_B</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_MALL_B__DCHUBBUB_ARB_FRAC_URG_BW_MALL_B__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_ARB_FRAC_URG_BW_MALL_B__DCHUBBUB_ARB_FRAC_URG_BW_MALL_B_MASK                                 0x000003FFL</div><div class='add'>+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__Z_STUTTER_WATERMARK_SELECT__SHIFT                                 0x11</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT                                         0x18</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__UCLK_PSTATE_CHANGE_WATERMARK_SELECT__SHIFT                        0x19</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__FCLK_PSTATE_CHANGE_WATERMARK_SELECT__SHIFT                        0x1a</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__Z_STUTTER_WATERMARK_SELECT_MASK                                   0x00060000L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK                                           0x01000000L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__UCLK_PSTATE_CHANGE_WATERMARK_SELECT_MASK                          0x02000000L</div><div class='add'>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__FCLK_PSTATE_CHANGE_WATERMARK_SELECT_MASK                          0x04000000L</div><div class='add'>+//DCHUBBUB_ARB_MALL_CNTL</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK                                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+//DCHUBBUB_ARB_TIMEOUT_ENABLE</div><div class='add'>+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L</div><div class='add'>+//DCHUBBUB_GLOBAL_TIMER_CNTL</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L</div><div class='add'>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L</div><div class='add'>+//SURFACE_CHECK0_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK0_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//SURFACE_CHECK1_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK1_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//SURFACE_CHECK2_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK2_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//SURFACE_CHECK3_ADDRESS_LSB</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL</div><div class='add'>+//SURFACE_CHECK3_ADDRESS_MSB</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL</div><div class='add'>+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L</div><div class='add'>+//VTG0_CONTROL</div><div class='add'>+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//VTG1_CONTROL</div><div class='add'>+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//VTG2_CONTROL</div><div class='add'>+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//VTG3_CONTROL</div><div class='add'>+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0</div><div class='add'>+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10</div><div class='add'>+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f</div><div class='add'>+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL</div><div class='add'>+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L</div><div class='add'>+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L</div><div class='add'>+//DCHUBBUB_SOFT_RESET</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L</div><div class='add'>+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L</div><div class='add'>+//DCHUBBUB_CLOCK_CNTL</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT                                                     0x7</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L</div><div class='add'>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK                                                       0x00000080L</div><div class='add'>+//DCFCLK_CNTL</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L</div><div class='add'>+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L</div><div class='add'>+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L</div><div class='add'>+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L</div><div class='add'>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L</div><div class='add'>+//DCHUBBUB_VLINE_SNAPSHOT</div><div class='add'>+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0</div><div class='add'>+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L</div><div class='add'>+//DCHUBBUB_CTRL_STATUS</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS__SHIFT                                                     0x1</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG__SHIFT                                                        0x4</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS_MASK                                                       0x00000002L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG_MASK                                                          0x3FFFFFF0L</div><div class='add'>+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L</div><div class='add'>+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L</div><div class='add'>+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L</div><div class='add'>+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L</div><div class='add'>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L</div><div class='add'>+//FMON_CTRL</div><div class='add'>+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0</div><div class='add'>+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1</div><div class='add'>+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4</div><div class='add'>+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5</div><div class='add'>+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7</div><div class='add'>+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9</div><div class='add'>+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc</div><div class='add'>+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16</div><div class='add'>+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b</div><div class='add'>+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L</div><div class='add'>+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L</div><div class='add'>+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L</div><div class='add'>+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L</div><div class='add'>+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L</div><div class='add'>+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L</div><div class='add'>+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L</div><div class='add'>+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L</div><div class='add'>+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L</div><div class='add'>+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_sdpif_dispdec</div><div class='add'>+//DCHUBBUB_SDPIF_CFG0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW__SHIFT                                                        0x10</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_DECODE_STATUS__SHIFT                                              0x11</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_SKIP_VDCI_EMPTY_CHECK__SHIFT                                               0x1f</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW_MASK                                                          0x00010000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_DECODE_STATUS_MASK                                                0x000E0000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_SKIP_VDCI_EMPTY_CHECK_MASK                                                 0x80000000L</div><div class='add'>+//DCHUBBUB_SDPIF_CFG1</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_DRQ_ERROR_DETECT_EN__SHIFT                                                 0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_DRQ_ERROR_STATUS__SHIFT                                                    0x5</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_DRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT                                                 0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_READ_UNCOMPRESSED__SHIFT                                             0xa</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_DRQ_ERROR_DETECT_EN_MASK                                                   0x00000010L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_DRQ_ERROR_STATUS_MASK                                                      0x00000020L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_DRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000040L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK                                                   0x00000200L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_READ_UNCOMPRESSED_MASK                                               0x00000400L</div><div class='add'>+//DCHUBBUB_SDPIF_CFG2</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L</div><div class='add'>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L</div><div class='add'>+//VM_REQUEST_PHYSICAL</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L</div><div class='add'>+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L</div><div class='add'>+//DCHUBBUB_FORCE_IO_STATUS_0</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L</div><div class='add'>+//DCHUBBUB_FORCE_IO_STATUS_1</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0</div><div class='add'>+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL</div><div class='add'>+//DCN_VM_FB_LOCATION_BASE</div><div class='add'>+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0</div><div class='add'>+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL</div><div class='add'>+//DCN_VM_FB_LOCATION_TOP</div><div class='add'>+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0</div><div class='add'>+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DCN_VM_FB_OFFSET</div><div class='add'>+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0</div><div class='add'>+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL</div><div class='add'>+//DCN_VM_AGP_BOT</div><div class='add'>+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0</div><div class='add'>+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL</div><div class='add'>+//DCN_VM_AGP_TOP</div><div class='add'>+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0</div><div class='add'>+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL</div><div class='add'>+//DCN_VM_AGP_BASE</div><div class='add'>+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0</div><div class='add'>+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL</div><div class='add'>+//DCN_VM_LOCAL_HBM_ADDRESS_START</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL</div><div class='add'>+//DCN_VM_LOCAL_HBM_ADDRESS_END</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL</div><div class='add'>+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0</div><div class='add'>+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x000001C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x00000E00L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_NOALLOC</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT                                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT                                               0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT                                               0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT                                               0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK                                                 0x00000003L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK                                                 0x0000000CL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK                                                 0x00000030L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK                                                 0x000000C0L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x000001C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x00000E00L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT                               0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT                               0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT                               0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT                               0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK                                 0x00000007L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK                                 0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK                                 0x000001C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK                                 0x00000E00L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE0_3DLUT_SEC_LVL__SHIFT                                   0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE1_3DLUT_SEC_LVL__SHIFT                                   0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE2_3DLUT_SEC_LVL__SHIFT                                   0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE3_3DLUT_SEC_LVL__SHIFT                                   0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE0_3DLUT_SEC_LVL_MASK                                     0x00000007L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE1_3DLUT_SEC_LVL_MASK                                     0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE2_3DLUT_SEC_LVL_MASK                                     0x000001C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE3_3DLUT_SEC_LVL_MASK                                     0x00000E00L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT                                   0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT                                   0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT                                   0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT                                   0x9</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK                                     0x00000007L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK                                     0x00000038L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK                                     0x000001C0L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK                                     0x00000E00L</div><div class='add'>+//DCHUBBUB_SDPIF_PIPE_DATAFETCH</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE0_DATAFETCH__SHIFT                                           0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE1_DATAFETCH__SHIFT                                           0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE2_DATAFETCH__SHIFT                                           0x4</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE3_DATAFETCH__SHIFT                                           0x6</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE0_DATAFETCH_MASK                                             0x00000003L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE1_DATAFETCH_MASK                                             0x0000000CL</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE2_DATAFETCH_MASK                                             0x00000030L</div><div class='add'>+#define DCHUBBUB_SDPIF_PIPE_DATAFETCH__SDPIF_PIPE3_DATAFETCH_MASK                                             0x000000C0L</div><div class='add'>+//SDPIF_REQUEST_RATE_LIMIT</div><div class='add'>+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT                                             0x0</div><div class='add'>+#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK                                               0x00000FFFL</div><div class='add'>+//DCHUBBUB_SDPIF_MEM_PWR_CTRL</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L</div><div class='add'>+//DCHUBBUB_SDPIF_MEM_PWR_STATUS</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L</div><div class='add'>+//DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE0__SHIFT                 0x0</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE1__SHIFT                 0x1</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE2__SHIFT                 0x2</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE3__SHIFT                 0x3</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE0__SHIFT            0xc</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE1__SHIFT            0xd</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE2__SHIFT            0xe</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE3__SHIFT            0xf</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_ENABLE__SHIFT                 0x1c</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_VREADY_MODE__SHIFT                0x1f</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE0_MASK                   0x00000001L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE1_MASK                   0x00000002L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE2_MASK                   0x00000004L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_FLIP_AWAY_MISSING_PIPE3_MASK                   0x00000008L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE0_MASK              0x00001000L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE1_MASK              0x00002000L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE2_MASK              0x00004000L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_CLEAR_PIPE3_MASK              0x00008000L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_ERR_ENABLE_MASK                   0x10000000L</div><div class='add'>+#define DCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL__DCHUBBUB_SDPIF_MCACHEID_INV_VREADY_MODE_MASK                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_ret_path_dispdec</div><div class='add'>+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L</div><div class='add'>+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0</div><div class='add'>+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L</div><div class='add'>+//DCHUBBUB_CRC_CTRL</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L</div><div class='add'>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L</div><div class='add'>+//DCHUBBUB_CRC0_VAL_R_G</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L</div><div class='add'>+//DCHUBBUB_CRC0_VAL_B_A</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL</div><div class='add'>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L</div><div class='add'>+//DCHUBBUB_CRC1_VAL_R_G</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L</div><div class='add'>+//DCHUBBUB_CRC1_VAL_B_A</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL</div><div class='add'>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L</div><div class='add'>+//DCHUBBUB_DCC_STAT_CNTL</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L</div><div class='add'>+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L</div><div class='add'>+//DCHUBBUB_DCC_STAT0</div><div class='add'>+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_DCC_STAT1</div><div class='add'>+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_DCC_STAT2</div><div class='add'>+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0</div><div class='add'>+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_COMPBUF_CTRL</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L</div><div class='add'>+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L</div><div class='add'>+//DCHUBBUB_DET0_CTRL</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_DET1_CTRL</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_DET2_CTRL</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_DET3_CTRL</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x0000001FL</div><div class='add'>+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00001F00L</div><div class='add'>+//DCHUBBUB_STAT</div><div class='add'>+#define DCHUBBUB_STAT__PIPE0_OUTSTANDING__SHIFT                                                               0x0</div><div class='add'>+#define DCHUBBUB_STAT__PIPE1_OUTSTANDING__SHIFT                                                               0x1</div><div class='add'>+#define DCHUBBUB_STAT__PIPE2_OUTSTANDING__SHIFT                                                               0x2</div><div class='add'>+#define DCHUBBUB_STAT__PIPE3_OUTSTANDING__SHIFT                                                               0x3</div><div class='add'>+#define DCHUBBUB_STAT__PIPE0_OUTSTANDING_MASK                                                                 0x00000001L</div><div class='add'>+#define DCHUBBUB_STAT__PIPE1_OUTSTANDING_MASK                                                                 0x00000002L</div><div class='add'>+#define DCHUBBUB_STAT__PIPE2_OUTSTANDING_MASK                                                                 0x00000004L</div><div class='add'>+#define DCHUBBUB_STAT__PIPE3_OUTSTANDING_MASK                                                                 0x00000008L</div><div class='add'>+//DCHUBBUB_MEM_PWR_MODE_CTRL</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L</div><div class='add'>+//COMPBUF_MEM_PWR_CTRL_1</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L</div><div class='add'>+//COMPBUF_MEM_PWR_CTRL_2</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY__SHIFT                                           0x8</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY__SHIFT                                             0xc</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY_MASK                                             0x00000F00L</div><div class='add'>+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY_MASK                                               0x0000F000L</div><div class='add'>+//DCHUBBUB_MEM_PWR_STATUS</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L</div><div class='add'>+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L</div><div class='add'>+//COMPBUF_RESERVED_SPACE</div><div class='add'>+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0</div><div class='add'>+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL</div><div class='add'>+//DCN_DECOMP_STATUS</div><div class='add'>+#define DCN_DECOMP_STATUS__DECOMP_OUT_STATUS__SHIFT                                                           0x0</div><div class='add'>+#define DCN_DECOMP_STATUS__DECOMP_OUT_STATUS_CLEAR__SHIFT                                                     0x10</div><div class='add'>+#define DCN_DECOMP_STATUS__DECOMP_OUT_STATUS_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DCN_DECOMP_STATUS__DECOMP_OUT_STATUS_CLEAR_MASK                                                       0x00010000L</div><div class='add'>+//DCHUBBUB_DEBUG_CTRL_0</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH__SHIFT                                                          0x0</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH__SHIFT                                                       0x8</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH__SHIFT                                                           0xc</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                                                               0x10</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE__SHIFT                               0x1b</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE__SHIFT                                         0x1c</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE__SHIFT                                     0x1d</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE__SHIFT                                         0x1e</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE__SHIFT                                       0x1f</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH_MASK                                                            0x000000FFL</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH_MASK                                                         0x00000F00L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH_MASK                                                             0x0000F000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                                                 0x07FF0000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE_MASK                                 0x08000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE_MASK                                           0x10000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE_MASK                                       0x20000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE_MASK                                           0x40000000L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE_MASK                                         0x80000000L</div><div class='add'>+//DCHUBBUB_DEBUG_CTRL_1</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__DCHUBBUB_DEBUG_CTRL_PIXPATH_INDEX__SHIFT                                       0x0</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__DCHUBBUB_DEBUG_DCC_RATIO_MONITOR_PIPE_VECTOR__SHIFT                            0x3</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__SWATH_CHK_GOOD_SEL__SHIFT                                                      0xb</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__SPARE__SHIFT                                                                   0xd</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__DCHUBBUB_DEBUG_CTRL_PIXPATH_INDEX_MASK                                         0x00000007L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__DCHUBBUB_DEBUG_DCC_RATIO_MONITOR_PIPE_VECTOR_MASK                              0x000007F8L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__SWATH_CHK_GOOD_SEL_MASK                                                        0x00001800L</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_1__SPARE_MASK                                                                     0xFFFFE000L</div><div class='add'>+//DCHUBBUB_DEBUG_CTRL_2</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_2__SPARE__SHIFT                                                                   0x0</div><div class='add'>+#define DCHUBBUB_DEBUG_CTRL_2__SPARE_MASK                                                                     0xFFFFFFFFL</div><div class='add'>+//DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX</div><div class='add'>+#define DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__SHIFT                         0x0</div><div class='add'>+#define DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_MASK                           0x000000FFL</div><div class='add'>+//DCHUBBUB_RET_PATH_TEST_DEBUG_DATA</div><div class='add'>+#define DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__SHIFT                           0x0</div><div class='add'>+#define DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__DCHUBBUB_RET_PATH_TEST_DEBUG_DATA_MASK                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_hubbub_vmrq_if_dispdec</div><div class='add'>+//DCN_VM_CONTEXT0_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_CNTL</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L</div><div class='add'>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL</div><div class='add'>+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0</div><div class='add'>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL</div><div class='add'>+//DCN_VM_DEFAULT_ADDR_MSB</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L</div><div class='add'>+//DCN_VM_DEFAULT_ADDR_LSB</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0</div><div class='add'>+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DCN_VM_FAULT_CNTL</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L</div><div class='add'>+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L</div><div class='add'>+//DCN_VM_FAULT_STATUS</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L</div><div class='add'>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L</div><div class='add'>+//DCN_VM_FAULT_ADDR_MSB</div><div class='add'>+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0</div><div class='add'>+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL</div><div class='add'>+//DCN_VM_FAULT_ADDR_LSB</div><div class='add'>+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0</div><div class='add'>+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubp_dispdec</div><div class='add'>+//HUBP0_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP0_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP0_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE</div><div class='add'>+#define HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE__SHIFT                0x0</div><div class='add'>+#define HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C__SHIFT              0x10</div><div class='add'>+#define HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_MASK                  0x0000FFFFL</div><div class='add'>+#define HUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C_MASK                0xFFFF0000L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP0_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP0_DCHUBP_CNTL</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP0_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT                                                   0x5</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT                                                   0x19</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK                                                     0x00000020L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK                                                     0x02000000L</div><div class='add'>+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP0_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP0_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE__SHIFT                                                   0x3</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__MALL_PREF_MODE__SHIFT                                                       0x4</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE_MASK                                                     0x00000008L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_CONFIG__MALL_PREF_MODE_MASK                                                         0x00000010L</div><div class='add'>+//HUBP0_DCHUBP_MALL_SUB_VP0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE__SHIFT                                              0x0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION__SHIFT                                               0x1</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0__SHIFT                                               0x2</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0__SHIFT                                               0xe</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE_MASK                                                0x00000001L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION_MASK                                                 0x00000002L</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0_MASK                                                 0x00003FFCL</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0_MASK                                                 0x03FFC000L</div><div class='add'>+//HUBP0_DCHUBP_MALL_SUB_VP1</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0__SHIFT                                                0x0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1__SHIFT                                                0x10</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0_MASK                                                  0x0000FFFFL</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP0_DCHUBP_MALL_SUB_VP2</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1__SHIFT                                               0x0</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1__SHIFT                                               0xc</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1_MASK                                                 0x00000FFFL</div><div class='add'>+#define HUBP0_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1_MASK                                                 0x00FFF000L</div><div class='add'>+//HUBP0_DCHUBP_MCACHEID_CONFIG</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0__SHIFT                                          0x0</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0__SHIFT                                          0x4</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1__SHIFT                                          0x8</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1__SHIFT                                          0xc</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0__SHIFT                                         0x10</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0__SHIFT                                         0x14</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1__SHIFT                                         0x18</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1__SHIFT                                         0x1c</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0_MASK                                            0x0000000FL</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0_MASK                                            0x000000F0L</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1_MASK                                            0x00000F00L</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1_MASK                                            0x0000F000L</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0_MASK                                           0x000F0000L</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0_MASK                                           0x00F00000L</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1_MASK                                           0x0F000000L</div><div class='add'>+#define HUBP0_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1_MASK                                           0xF0000000L</div><div class='add'>+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+//HUBP0_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH__SHIFT                                           0xd</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM__SHIFT                                                  0x14</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH_MASK                                             0x00002000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x0000FFFFL</div><div class='add'>+//HUBPREQ0_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+//HUBPREQ0_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ0_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ0_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ0_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ0_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ0_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ0_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ0_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ0_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ0_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ0_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ0_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ0_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ0_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ0_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ0_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0x8</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xa</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00000300L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00000400L</div><div class='add'>+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x00000030L</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ0_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ0_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x0000FFFFL</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0xFFFF0000L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+//HUBPREQ0_HUBPREQ_STATUS_REG3</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL_MASK                                              0x00000001L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ0_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL_MASK                                              0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET0_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET0_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET0_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x0000FFFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x0000FFFFL</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBPRET0_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_0_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+//CURSOR0_0_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_0_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_0_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0xf</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00007FFFL</div><div class='add'>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF8000L</div><div class='add'>+//CURSOR0_0_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_0_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_0_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00003FFFL</div><div class='add'>+//CURSOR0_0_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_0_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_0_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_0_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_0_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_0_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_0_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_0_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_0_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_0_HUBP_3DLUT_CONTROL</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT                                                0x0</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT                                       0x1</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT                                                 0x2</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B__SHIFT                                   0x11</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G__SHIFT                                  0x13</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R__SHIFT                                  0x15</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT                                                  0x1f</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK                                                  0x00000001L</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK                                         0x00000002L</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK                                                   0x0000FFFCL</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK                                                     0x00010000L</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B_MASK                                     0x00060000L</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G_MASK                                    0x00180000L</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R_MASK                                    0x00600000L</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK                                                    0x80000000L</div><div class='add'>+//CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT                                     0x0</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK                                       0x0000FFFFL</div><div class='add'>+//CURSOR0_0_HUBP_3DLUT_DLG_PARAM</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT                                         0x0</div><div class='add'>+#define CURSOR0_0_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK                                           0x007FFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubp_dispdec</div><div class='add'>+//HUBP1_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP1_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP1_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE</div><div class='add'>+#define HUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE__SHIFT                0x0</div><div class='add'>+#define HUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C__SHIFT              0x10</div><div class='add'>+#define HUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_MASK                  0x0000FFFFL</div><div class='add'>+#define HUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C_MASK                0xFFFF0000L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP1_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP1_DCHUBP_CNTL</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP1_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT                                                   0x5</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT                                                   0x19</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK                                                     0x00000020L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK                                                     0x02000000L</div><div class='add'>+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP1_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP1_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE__SHIFT                                                   0x3</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__MALL_PREF_MODE__SHIFT                                                       0x4</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE_MASK                                                     0x00000008L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_CONFIG__MALL_PREF_MODE_MASK                                                         0x00000010L</div><div class='add'>+//HUBP1_DCHUBP_MALL_SUB_VP0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE__SHIFT                                              0x0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION__SHIFT                                               0x1</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0__SHIFT                                               0x2</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0__SHIFT                                               0xe</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE_MASK                                                0x00000001L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION_MASK                                                 0x00000002L</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0_MASK                                                 0x00003FFCL</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0_MASK                                                 0x03FFC000L</div><div class='add'>+//HUBP1_DCHUBP_MALL_SUB_VP1</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0__SHIFT                                                0x0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1__SHIFT                                                0x10</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0_MASK                                                  0x0000FFFFL</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP1_DCHUBP_MALL_SUB_VP2</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1__SHIFT                                               0x0</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1__SHIFT                                               0xc</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1_MASK                                                 0x00000FFFL</div><div class='add'>+#define HUBP1_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1_MASK                                                 0x00FFF000L</div><div class='add'>+//HUBP1_DCHUBP_MCACHEID_CONFIG</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0__SHIFT                                          0x0</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0__SHIFT                                          0x4</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1__SHIFT                                          0x8</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1__SHIFT                                          0xc</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0__SHIFT                                         0x10</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0__SHIFT                                         0x14</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1__SHIFT                                         0x18</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1__SHIFT                                         0x1c</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0_MASK                                            0x0000000FL</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0_MASK                                            0x000000F0L</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1_MASK                                            0x00000F00L</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1_MASK                                            0x0000F000L</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0_MASK                                           0x000F0000L</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0_MASK                                           0x00F00000L</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1_MASK                                           0x0F000000L</div><div class='add'>+#define HUBP1_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1_MASK                                           0xF0000000L</div><div class='add'>+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+//HUBP1_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH__SHIFT                                           0xd</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM__SHIFT                                                  0x14</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH_MASK                                             0x00002000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x0000FFFFL</div><div class='add'>+//HUBPREQ1_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+//HUBPREQ1_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ1_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ1_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ1_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ1_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ1_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ1_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ1_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ1_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ1_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ1_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ1_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ1_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ1_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ1_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ1_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0x8</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xa</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00000300L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00000400L</div><div class='add'>+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x00000030L</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ1_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ1_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x0000FFFFL</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0xFFFF0000L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+//HUBPREQ1_HUBPREQ_STATUS_REG3</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL_MASK                                              0x00000001L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ1_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL_MASK                                              0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET1_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET1_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET1_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x0000FFFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x0000FFFFL</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBPRET1_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_1_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+//CURSOR0_1_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_1_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_1_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0xf</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00007FFFL</div><div class='add'>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF8000L</div><div class='add'>+//CURSOR0_1_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_1_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_1_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00003FFFL</div><div class='add'>+//CURSOR0_1_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_1_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_1_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_1_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_1_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_1_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_1_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_1_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_1_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_1_HUBP_3DLUT_CONTROL</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT                                                0x0</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT                                       0x1</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT                                                 0x2</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B__SHIFT                                   0x11</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G__SHIFT                                  0x13</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R__SHIFT                                  0x15</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT                                                  0x1f</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK                                                  0x00000001L</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK                                         0x00000002L</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK                                                   0x0000FFFCL</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK                                                     0x00010000L</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B_MASK                                     0x00060000L</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G_MASK                                    0x00180000L</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R_MASK                                    0x00600000L</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK                                                    0x80000000L</div><div class='add'>+//CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT                                     0x0</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK                                       0x0000FFFFL</div><div class='add'>+//CURSOR0_1_HUBP_3DLUT_DLG_PARAM</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT                                         0x0</div><div class='add'>+#define CURSOR0_1_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK                                           0x007FFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubp_dispdec</div><div class='add'>+//HUBP2_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP2_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP2_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE</div><div class='add'>+#define HUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE__SHIFT                0x0</div><div class='add'>+#define HUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C__SHIFT              0x10</div><div class='add'>+#define HUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_MASK                  0x0000FFFFL</div><div class='add'>+#define HUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C_MASK                0xFFFF0000L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP2_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP2_DCHUBP_CNTL</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP2_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT                                                   0x5</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT                                                   0x19</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK                                                     0x00000020L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK                                                     0x02000000L</div><div class='add'>+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP2_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP2_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE__SHIFT                                                   0x3</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__MALL_PREF_MODE__SHIFT                                                       0x4</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE_MASK                                                     0x00000008L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_CONFIG__MALL_PREF_MODE_MASK                                                         0x00000010L</div><div class='add'>+//HUBP2_DCHUBP_MALL_SUB_VP0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE__SHIFT                                              0x0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION__SHIFT                                               0x1</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0__SHIFT                                               0x2</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0__SHIFT                                               0xe</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE_MASK                                                0x00000001L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION_MASK                                                 0x00000002L</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0_MASK                                                 0x00003FFCL</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0_MASK                                                 0x03FFC000L</div><div class='add'>+//HUBP2_DCHUBP_MALL_SUB_VP1</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0__SHIFT                                                0x0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1__SHIFT                                                0x10</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0_MASK                                                  0x0000FFFFL</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP2_DCHUBP_MALL_SUB_VP2</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1__SHIFT                                               0x0</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1__SHIFT                                               0xc</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1_MASK                                                 0x00000FFFL</div><div class='add'>+#define HUBP2_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1_MASK                                                 0x00FFF000L</div><div class='add'>+//HUBP2_DCHUBP_MCACHEID_CONFIG</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0__SHIFT                                          0x0</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0__SHIFT                                          0x4</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1__SHIFT                                          0x8</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1__SHIFT                                          0xc</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0__SHIFT                                         0x10</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0__SHIFT                                         0x14</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1__SHIFT                                         0x18</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1__SHIFT                                         0x1c</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0_MASK                                            0x0000000FL</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0_MASK                                            0x000000F0L</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1_MASK                                            0x00000F00L</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1_MASK                                            0x0000F000L</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0_MASK                                           0x000F0000L</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0_MASK                                           0x00F00000L</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1_MASK                                           0x0F000000L</div><div class='add'>+#define HUBP2_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1_MASK                                           0xF0000000L</div><div class='add'>+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+//HUBP2_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH__SHIFT                                           0xd</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM__SHIFT                                                  0x14</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH_MASK                                             0x00002000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x0000FFFFL</div><div class='add'>+//HUBPREQ2_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+//HUBPREQ2_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ2_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ2_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ2_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ2_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ2_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ2_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ2_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ2_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ2_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ2_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ2_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ2_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ2_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ2_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ2_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0x8</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xa</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00000300L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00000400L</div><div class='add'>+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x00000030L</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ2_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ2_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x0000FFFFL</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0xFFFF0000L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+//HUBPREQ2_HUBPREQ_STATUS_REG3</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL_MASK                                              0x00000001L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ2_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL_MASK                                              0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET2_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET2_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET2_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x0000FFFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x0000FFFFL</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBPRET2_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_2_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+//CURSOR0_2_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_2_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_2_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0xf</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00007FFFL</div><div class='add'>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF8000L</div><div class='add'>+//CURSOR0_2_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_2_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_2_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00003FFFL</div><div class='add'>+//CURSOR0_2_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_2_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_2_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_2_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_2_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_2_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_2_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_2_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_2_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_2_HUBP_3DLUT_CONTROL</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT                                                0x0</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT                                       0x1</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT                                                 0x2</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B__SHIFT                                   0x11</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G__SHIFT                                  0x13</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R__SHIFT                                  0x15</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT                                                  0x1f</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK                                                  0x00000001L</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK                                         0x00000002L</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK                                                   0x0000FFFCL</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK                                                     0x00010000L</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B_MASK                                     0x00060000L</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G_MASK                                    0x00180000L</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R_MASK                                    0x00600000L</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK                                                    0x80000000L</div><div class='add'>+//CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT                                     0x0</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK                                       0x0000FFFFL</div><div class='add'>+//CURSOR0_2_HUBP_3DLUT_DLG_PARAM</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT                                         0x0</div><div class='add'>+#define CURSOR0_2_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK                                           0x007FFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubp_dispdec</div><div class='add'>+//HUBP3_DCSURF_SURFACE_CONFIG</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L</div><div class='add'>+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L</div><div class='add'>+//HUBP3_DCSURF_ADDR_CONFIG</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L</div><div class='add'>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L</div><div class='add'>+//HUBP3_DCSURF_TILING_CONFIG</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x00000007L</div><div class='add'>+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_START</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE</div><div class='add'>+#define HUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE__SHIFT                0x0</div><div class='add'>+#define HUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C__SHIFT              0x10</div><div class='add'>+#define HUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_MASK                  0x0000FFFFL</div><div class='add'>+#define HUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE__VIEWPORT_MCACHE_SPLIT_COORDINATE_C_MASK                0xFFFF0000L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_START_C</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_START</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x0000FFFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0xFFFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_START_C</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x0000FFFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL</div><div class='add'>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L</div><div class='add'>+//HUBP3_DCHUBP_REQ_SIZE_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L</div><div class='add'>+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L</div><div class='add'>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L</div><div class='add'>+//HUBP3_DCHUBP_CNTL</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L</div><div class='add'>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L</div><div class='add'>+//HUBP3_HUBP_CLK_CNTL</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT                                                   0x5</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT                                                   0x19</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK                                                     0x00000020L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK                                                     0x02000000L</div><div class='add'>+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L</div><div class='add'>+//HUBP3_DCHUBP_VMPG_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT                                                      0x1</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT                                                   0x2</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT                                              0x7</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK                                                        0x00000002L</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK                                                     0x0000007CL</div><div class='add'>+#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK                                                0x00000080L</div><div class='add'>+//HUBP3_DCHUBP_MALL_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT                                                         0x0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT                                                  0x2</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE__SHIFT                                                   0x3</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__MALL_PREF_MODE__SHIFT                                                       0x4</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK                                                    0x00000004L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__MALL_PREF_CMD_TYPE_MASK                                                     0x00000008L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_CONFIG__MALL_PREF_MODE_MASK                                                         0x00000010L</div><div class='add'>+//HUBP3_DCHUBP_MALL_SUB_VP0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE__SHIFT                                              0x0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION__SHIFT                                               0x1</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0__SHIFT                                               0x2</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0__SHIFT                                               0xe</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__USE_MALL_AT_START_LINE_MASK                                                0x00000001L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__PSTATE_ALLOW_POSITION_MASK                                                 0x00000002L</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_CURR_S0_MASK                                                 0x00003FFCL</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP0__SUB_VP_HEIGHT_NEXT_S0_MASK                                                 0x03FFC000L</div><div class='add'>+//HUBP3_DCHUBP_MALL_SUB_VP1</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0__SHIFT                                                0x0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1__SHIFT                                                0x10</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S0_MASK                                                  0x0000FFFFL</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP1__SUB_VP_START_LINE_S1_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP3_DCHUBP_MALL_SUB_VP2</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1__SHIFT                                               0x0</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1__SHIFT                                               0xc</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_CURR_S1_MASK                                                 0x00000FFFL</div><div class='add'>+#define HUBP3_DCHUBP_MALL_SUB_VP2__SUB_VP_HEIGHT_NEXT_S1_MASK                                                 0x00FFF000L</div><div class='add'>+//HUBP3_DCHUBP_MCACHEID_CONFIG</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0__SHIFT                                          0x0</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0__SHIFT                                          0x4</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1__SHIFT                                          0x8</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1__SHIFT                                          0xc</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0__SHIFT                                         0x10</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0__SHIFT                                         0x14</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1__SHIFT                                         0x18</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1__SHIFT                                         0x1c</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P0_MASK                                            0x0000000FL</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P0_MASK                                            0x000000F0L</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_1H_P1_MASK                                            0x00000F00L</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_REG_READ_2H_P1_MASK                                            0x0000F000L</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P0_MASK                                           0x000F0000L</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P0_MASK                                           0x00F00000L</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_1H_P1_MASK                                           0x0F000000L</div><div class='add'>+#define HUBP3_DCHUBP_MCACHEID_CONFIG__MCACHEID_MALL_PREF_2H_P1_MASK                                           0xF0000000L</div><div class='add'>+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L</div><div class='add'>+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L</div><div class='add'>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L</div><div class='add'>+//HUBP3_HUBP_MALL_STATUS</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT                                         0x0</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT                                         0x1</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT                                                       0x2</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT                                                      0x3</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT                                                            0x4</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT                                                 0x5</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT                                                   0x6</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT                                                  0x7</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT                                                  0x8</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT                                                  0x9</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT                                                    0xa</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT                                                    0xb</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT                                                     0xc</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH__SHIFT                                           0xd</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT                                                     0xe</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT                                                  0xf</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT                                   0x10</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT                                            0x11</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT                                                   0x12</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT                                                      0x13</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM__SHIFT                                                  0x14</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT                                                   0x18</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT                                                  0x19</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK                                           0x00000001L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK                                           0x00000002L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK                                                         0x00000004L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK                                                        0x00000008L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK                                                              0x00000010L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK                                                   0x00000020L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK                                                     0x00000040L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK                                                    0x00000080L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK                                                    0x00000100L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK                                                    0x00000200L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK                                                      0x00000400L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK                                                      0x00000800L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK                                                       0x00001000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_IMALL_PREFETCH_MASK                                             0x00002000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK                                                       0x00004000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK                                                    0x00008000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK                                     0x00010000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK                                              0x00020000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK                                                     0x00040000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK                                                        0x00080000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__SUB_VP_IMALL_CASE_NUM_MASK                                                    0x00700000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK                                                     0x01000000L</div><div class='add'>+#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK                                                    0x02000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubpreq_dispdec</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_PITCH</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_PITCH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x0000FFFFL</div><div class='add'>+//HUBPREQ3_VMID_SETTINGS_0</div><div class='add'>+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0</div><div class='add'>+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_CONTROL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L</div><div class='add'>+//HUBPREQ3_DCSURF_FLIP_CONTROL</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L</div><div class='add'>+//HUBPREQ3_DCSURF_FLIP_CONTROL2</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L</div><div class='add'>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL</div><div class='add'>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L</div><div class='add'>+//HUBPREQ3_DCN_EXPANSION_MODE</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L</div><div class='add'>+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L</div><div class='add'>+//HUBPREQ3_DCN_TTU_QOS_WM</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL</div><div class='add'>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L</div><div class='add'>+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L</div><div class='add'>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L</div><div class='add'>+//HUBPREQ3_DCN_SURF0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_SURF0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_SURF1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_SURF1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_CUR0_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_CUR0_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_CUR1_TTU_CNTL0</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L</div><div class='add'>+//HUBPREQ3_DCN_CUR1_TTU_CNTL1</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_DCN_DMDATA_VM_CNTL</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L</div><div class='add'>+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L</div><div class='add'>+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL</div><div class='add'>+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0</div><div class='add'>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL</div><div class='add'>+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L</div><div class='add'>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L</div><div class='add'>+//HUBPREQ3_BLANK_OFFSET_0</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L</div><div class='add'>+//HUBPREQ3_BLANK_OFFSET_1</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL</div><div class='add'>+//HUBPREQ3_DST_DIMENSIONS</div><div class='add'>+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0</div><div class='add'>+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL</div><div class='add'>+//HUBPREQ3_DST_AFTER_SCALER</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL</div><div class='add'>+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L</div><div class='add'>+//HUBPREQ3_PREFETCH_SETTINGS</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L</div><div class='add'>+//HUBPREQ3_PREFETCH_SETTINGS_C</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0</div><div class='add'>+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_1</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_2</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_3</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_4</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_1</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_2</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_1</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_2</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_3</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_4</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_5</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_6</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL</div><div class='add'>+//HUBPREQ3_NOM_PARAMETERS_7</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ3_PER_LINE_DELIVERY_PRE</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L</div><div class='add'>+//HUBPREQ3_PER_LINE_DELIVERY</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL</div><div class='add'>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L</div><div class='add'>+//HUBPREQ3_CURSOR_SETTINGS</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L</div><div class='add'>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L</div><div class='add'>+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ</div><div class='add'>+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL</div><div class='add'>+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT</div><div class='add'>+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL</div><div class='add'>+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT                                          0x4</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT                                            0x6</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0x8</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xa</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK                                            0x00000030L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK                                              0x00000040L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00000300L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00000400L</div><div class='add'>+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x4</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK                                          0x0000000CL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x00000030L</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_5</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_VBLANK_PARAMETERS_6</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_3</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_4</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_5</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL</div><div class='add'>+//HUBPREQ3_FLIP_PARAMETERS_6</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL</div><div class='add'>+//HUBPREQ3_UCLK_PSTATE_FORCE</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT                                          0x0</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT                                       0x1</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT                                        0x2</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT                                     0x3</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK                                            0x00000001L</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK                                         0x00000002L</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK                                          0x00000004L</div><div class='add'>+#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK                                       0x00000008L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0__SHIFT                                         0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1__SHIFT                                         0x8</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT                                                 0x10</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S0_MASK                                           0x0000001FL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_TPTE_ROW_READY_S1_MASK                                           0x00001F00L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK                                                   0x7FFF0000L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG1</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT                                       0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT                                       0x10</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK                                         0x0000FFFFL</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK                                         0xFFFF0000L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT                                      0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT                               0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT                               0x3</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT                                   0x4</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT                                             0x5</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT                                      0x8</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT                                     0x9</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT                               0xa</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT                               0xb</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT                                   0xc</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT                                             0xd</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT                                     0x10</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT                                    0x11</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT                              0x12</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT                              0x13</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT                                  0x14</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT                                            0x15</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT                                                    0x1a</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT                                                   0x1b</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT                                          0x1c</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT                                             0x1d</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT                                            0x1e</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT                                            0x1f</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK                                        0x00000001L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK                                 0x00000004L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK                                 0x00000008L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK                                     0x00000010L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK                                               0x00000020L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK                                        0x00000100L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK                                       0x00000200L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK                                 0x00000400L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK                                 0x00000800L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK                                     0x00001000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK                                               0x00002000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK                                       0x00010000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK                                      0x00020000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK                                0x00040000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK                                0x00080000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK                                    0x00100000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK                                              0x00200000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK                                                      0x04000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK                                                     0x08000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK                                            0x10000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK                                               0x20000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK                                              0x40000000L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK                                              0x80000000L</div><div class='add'>+//HUBPREQ3_HUBPREQ_STATUS_REG3</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL__SHIFT                                            0x0</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE__SHIFT                                     0x1</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL__SHIFT                                            0x2</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG3__STATUS_TDLUT_EN_LOCAL_MASK                                              0x00000001L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG3__STATUS_TDLUT_DELIVERY_ACTIVE_MASK                                       0x00000002L</div><div class='add'>+#define HUBPREQ3_HUBPREQ_STATUS_REG3__STATUS_TDLUT_PIX_CTRL_MASK                                              0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubpret_dispdec</div><div class='add'>+//HUBPRET3_HUBPRET_CONTROL</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00007FF0L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L</div><div class='add'>+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L</div><div class='add'>+//HUBPRET3_HUBPRET_MEM_PWR_CTRL</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L</div><div class='add'>+//HUBPRET3_HUBPRET_MEM_PWR_STATUS</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL</div><div class='add'>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_CTRL0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_CTRL1</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x0000FFFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE1</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x0000FFFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0xFFFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_INTERRUPT</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L</div><div class='add'>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_VALUE</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x0000FFFFL</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0xFFFF0000L</div><div class='add'>+//HUBPRET3_HUBPRET_READ_LINE_STATUS</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L</div><div class='add'>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_cursor0_dispdec</div><div class='add'>+//CURSOR0_3_CURSOR_CONTROL</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L</div><div class='add'>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L</div><div class='add'>+//CURSOR0_3_CURSOR_SURFACE_ADDRESS</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL</div><div class='add'>+//CURSOR0_3_CURSOR_SIZE</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL</div><div class='add'>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L</div><div class='add'>+//CURSOR0_3_CURSOR_POSITION</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0xf</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00007FFFL</div><div class='add'>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF8000L</div><div class='add'>+//CURSOR0_3_CURSOR_HOT_SPOT</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL</div><div class='add'>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L</div><div class='add'>+//CURSOR0_3_CURSOR_STEREO_CONTROL</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L</div><div class='add'>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L</div><div class='add'>+//CURSOR0_3_CURSOR_DST_OFFSET</div><div class='add'>+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00003FFFL</div><div class='add'>+//CURSOR0_3_CURSOR_MEM_PWR_CTRL</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L</div><div class='add'>+//CURSOR0_3_CURSOR_MEM_PWR_STATUS</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0</div><div class='add'>+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L</div><div class='add'>+//CURSOR0_3_DMDATA_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L</div><div class='add'>+//CURSOR0_3_DMDATA_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//CURSOR0_3_DMDATA_CNTL</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L</div><div class='add'>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L</div><div class='add'>+//CURSOR0_3_DMDATA_QOS_CNTL</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L</div><div class='add'>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L</div><div class='add'>+//CURSOR0_3_DMDATA_STATUS</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L</div><div class='add'>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L</div><div class='add'>+//CURSOR0_3_DMDATA_SW_CNTL</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L</div><div class='add'>+//CURSOR0_3_DMDATA_SW_DATA</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0</div><div class='add'>+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_3_HUBP_3DLUT_CONTROL</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT                                                0x0</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT                                       0x1</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT                                                 0x2</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT                                                   0x10</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B__SHIFT                                   0x11</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G__SHIFT                                  0x13</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R__SHIFT                                  0x15</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT                                                  0x1f</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK                                                  0x00000001L</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK                                         0x00000002L</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK                                                   0x0000FFFCL</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK                                                     0x00010000L</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CB_B_MASK                                     0x00060000L</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_Y_G_MASK                                    0x00180000L</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SELECT_CR_R_MASK                                    0x00600000L</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK                                                    0x80000000L</div><div class='add'>+//CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT                                       0x0</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK                                         0xFFFFFFFFL</div><div class='add'>+//CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT                                     0x0</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK                                       0x0000FFFFL</div><div class='add'>+//CURSOR0_3_HUBP_3DLUT_DLG_PARAM</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT                                         0x0</div><div class='add'>+#define CURSOR0_3_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK                                           0x007FFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG0_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG0_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT                                                   0x1</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK                                                     0x00000002L</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG0_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG0_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG0_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG0_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_cm_cur_dispdec</div><div class='add'>+//CM_CUR0_CURSOR0_CONTROL</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                   0x1</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                     0x2</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                           0x3</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                             0x4</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                               0x7</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                   0x10</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                     0x00000002L</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                       0x00000004L</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                             0x00000008L</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                               0x00000070L</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                                 0x00000080L</div><div class='add'>+#define CM_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                     0x00010000L</div><div class='add'>+//CM_CUR0_CURSOR0_COLOR0</div><div class='add'>+#define CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR0_CURSOR0_COLOR1</div><div class='add'>+#define CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT                                           0x0</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT                                            0x10</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK                                             0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK                                              0xFFFF0000L</div><div class='add'>+//CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT                                   0x0</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT                                    0x10</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK                                     0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK                                      0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_MODE</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT                                             0x2</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT                                              0x4</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK                                               0x0000000CL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK                                                0x00000010L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C11_C12_A</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C13_C14_A</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C21_C22_A</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C23_C24_A</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C31_C32_A</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C33_C34_A</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C11_C12_B</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C13_C14_B</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C21_C22_B</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C23_C24_B</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C31_C32_B</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR0_CUR0_MATRIX_C33_C34_B</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK                                                 0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_dscl_dispdec</div><div class='add'>+//DSCL0_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L</div><div class='add'>+//DSCL0_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL0_SCL_MODE</div><div class='add'>+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL0_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL0_DSCL_CONTROL</div><div class='add'>+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL0_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL0_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_UPDATE</div><div class='add'>+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL0_DSCL_AUTOCAL</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00003FFFL</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x3FFF0000L</div><div class='add'>+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x3FFF0000L</div><div class='add'>+//DSCL0_OTG_H_BLANK</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL0_OTG_V_BLANK</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL0_RECOUT_START</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00003FFFL</div><div class='add'>+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL0_RECOUT_SIZE</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL0_MPC_SIZE</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL0_LB_DATA_FORMAT</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL0_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL0_LB_V_COUNTER</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL0_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL0_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL0_OBUF_CONTROL</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL0_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_MODE</div><div class='add'>+#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL0_DSCL_EASF_V_MODE</div><div class='add'>+#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL0_DSCL_SC_MODE</div><div class='add'>+#define DSCL0_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT                                                         0x0</div><div class='add'>+#define DSCL0_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT                                                            0x8</div><div class='add'>+#define DSCL0_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define DSCL0_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK                                                              0x00000100L</div><div class='add'>+//DSCL0_DSCL_SC_MATRIX_C0C1</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT                                                    0x10</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_SC_MATRIX_C2C3</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT                                                    0x0</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT                                                    0x10</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT                    0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT                    0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT                    0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK                       0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT                    0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT                   0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK                     0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_RINGEST_FORCE</div><div class='add'>+#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT                                        0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT                                        0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK                                          0xFFFF0000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF_CNTL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF_CNTL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG1</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG2</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG3</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG4</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG5</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG6</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF1_PWL_SEG7</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG1</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG2</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG3</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG4</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG5</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG6</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF1_PWL_SEG7</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF3_PWL_SEG0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF3_PWL_SEG1</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF3_PWL_SEG2</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF3_PWL_SEG3</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF3_PWL_SEG4</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_H_BF3_PWL_SEG5</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF3_PWL_SEG0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF3_PWL_SEG1</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF3_PWL_SEG2</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF3_PWL_SEG3</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF3_PWL_SEG4</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL0_DSCL_EASF_V_BF3_PWL_SEG5</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL0_ISHARP_MODE</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_EN__SHIFT                                                                   0x0</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT                                                          0x4</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT                                                        0x5</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT                                                             0x9</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT                                                     0xa</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT                                                             0xb</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT                                                             0xc</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT                                             0x1c</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK                                                            0x00000010L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK                                                          0x00000060L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_LBA_MODE_MASK                                                               0x00000200L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_FMT_MODE_MASK                                                               0x00000800L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_FMT_NORM_MASK                                                               0x0FFFF000L</div><div class='add'>+#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK                                               0x10000000L</div><div class='add'>+//DSCL0_ISHARP_DELTA_CTRL</div><div class='add'>+#define DSCL0_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT                                          0x0</div><div class='add'>+#define DSCL0_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK                                            0x00000001L</div><div class='add'>+//DSCL0_ISHARP_DELTA_INDEX</div><div class='add'>+#define DSCL0_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define DSCL0_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK                                                     0x0000001FL</div><div class='add'>+//DSCL0_ISHARP_DELTA_DATA</div><div class='add'>+#define DSCL0_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT                                                     0x0</div><div class='add'>+#define DSCL0_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DSCL0_ISHARP_NLDELTA_SOFT_CLIP</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT                                      0x0</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT                                   0x1</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT                                   0x8</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT                                      0x10</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT                                   0x11</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT                                   0x18</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK                                        0x00000001L</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK                                     0x000000FEL</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK                                     0x0000FF00L</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK                                        0x00010000L</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK                                     0x00FE0000L</div><div class='add'>+#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK                                     0xFF000000L</div><div class='add'>+//DSCL0_ISHARP_NOISEDET_THRESHOLD</div><div class='add'>+#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT                                         0x0</div><div class='add'>+#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT                                         0x10</div><div class='add'>+#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK                                           0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK                                           0x03FF0000L</div><div class='add'>+//DSCL0_ISHARP_NOISE_GAIN_PWL</div><div class='add'>+#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT                                      0x0</div><div class='add'>+#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT                                        0x8</div><div class='add'>+#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT                                         0x10</div><div class='add'>+#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK                                        0x0000001FL</div><div class='add'>+#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK                                          0x00001F00L</div><div class='add'>+#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK                                           0x3FFF0000L</div><div class='add'>+//DSCL0_ISHARP_LBA_PWL_SEG0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT                                              0x0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT                                            0xc</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL0_ISHARP_LBA_PWL_SEG1</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT                                              0x0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT                                            0xc</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL0_ISHARP_LBA_PWL_SEG2</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT                                              0x0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT                                            0xc</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL0_ISHARP_LBA_PWL_SEG3</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT                                              0x0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT                                            0xc</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL0_ISHARP_LBA_PWL_SEG4</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT                                              0x0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT                                            0xc</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT                                           0x14</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL0_ISHARP_LBA_PWL_SEG5</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT                                              0x0</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT                                            0xc</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK                                              0x0003F000L</div><div class='add'>+//DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL</div><div class='add'>+#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT                            0x0</div><div class='add'>+#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT                              0x2</div><div class='add'>+#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT                            0x4</div><div class='add'>+#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK                              0x00000003L</div><div class='add'>+#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK                                0x00000004L</div><div class='add'>+#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK                              0x00000030L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_cm_dispdec</div><div class='add'>+//CM0_CM_CONTROL</div><div class='add'>+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM0_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM0_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM0_CM_BIAS_CR_R</div><div class='add'>+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM0_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM0_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM0_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM0_CM_HDR_MULT_COEF</div><div class='add'>+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM0_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM0_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM0_CM_DEALPHA</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM0_CM_COEF_FORMAT</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+//CM0_CM_TEST_DEBUG_INDEX</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL</div><div class='add'>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L</div><div class='add'>+//CM0_CM_TEST_DEBUG_DATA</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP0_DPP_CONTROL</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP0_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP0_DPP_CRC_VAL_R_G</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L</div><div class='add'>+//DPP_TOP0_DPP_CRC_VAL_B_A</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L</div><div class='add'>+//DPP_TOP0_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP0_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG1_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG1_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT                                                   0x1</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK                                                     0x00000002L</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG1_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG1_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG1_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG1_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_cm_cur_dispdec</div><div class='add'>+//CM_CUR1_CURSOR0_CONTROL</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                   0x1</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                     0x2</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                           0x3</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                             0x4</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                               0x7</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                   0x10</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                     0x00000002L</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                       0x00000004L</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                             0x00000008L</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                               0x00000070L</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                                 0x00000080L</div><div class='add'>+#define CM_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                     0x00010000L</div><div class='add'>+//CM_CUR1_CURSOR0_COLOR0</div><div class='add'>+#define CM_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR1_CURSOR0_COLOR1</div><div class='add'>+#define CM_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT                                           0x0</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT                                            0x10</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK                                             0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK                                              0xFFFF0000L</div><div class='add'>+//CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT                                   0x0</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT                                    0x10</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK                                     0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK                                      0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_MODE</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT                                             0x2</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT                                              0x4</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK                                               0x0000000CL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK                                                0x00000010L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C11_C12_A</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C13_C14_A</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C21_C22_A</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C23_C24_A</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C31_C32_A</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C33_C34_A</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C11_C12_B</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C13_C14_B</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C21_C22_B</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C23_C24_B</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C31_C32_B</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR1_CUR0_MATRIX_C33_C34_B</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK                                                 0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_dscl_dispdec</div><div class='add'>+//DSCL1_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L</div><div class='add'>+//DSCL1_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL1_SCL_MODE</div><div class='add'>+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL1_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL1_DSCL_CONTROL</div><div class='add'>+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL1_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL1_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_UPDATE</div><div class='add'>+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL1_DSCL_AUTOCAL</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00003FFFL</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x3FFF0000L</div><div class='add'>+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x3FFF0000L</div><div class='add'>+//DSCL1_OTG_H_BLANK</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL1_OTG_V_BLANK</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL1_RECOUT_START</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00003FFFL</div><div class='add'>+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL1_RECOUT_SIZE</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL1_MPC_SIZE</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL1_LB_DATA_FORMAT</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL1_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL1_LB_V_COUNTER</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL1_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL1_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL1_OBUF_CONTROL</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL1_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_MODE</div><div class='add'>+#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL1_DSCL_EASF_V_MODE</div><div class='add'>+#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL1_DSCL_SC_MODE</div><div class='add'>+#define DSCL1_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT                                                         0x0</div><div class='add'>+#define DSCL1_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT                                                            0x8</div><div class='add'>+#define DSCL1_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define DSCL1_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK                                                              0x00000100L</div><div class='add'>+//DSCL1_DSCL_SC_MATRIX_C0C1</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT                                                    0x10</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_SC_MATRIX_C2C3</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT                                                    0x0</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT                                                    0x10</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT                    0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT                    0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT                    0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK                       0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT                    0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT                   0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK                     0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_RINGEST_FORCE</div><div class='add'>+#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT                                        0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT                                        0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK                                          0xFFFF0000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF_CNTL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF_CNTL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG1</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG2</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG3</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG4</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG5</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG6</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF1_PWL_SEG7</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG1</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG2</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG3</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG4</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG5</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG6</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF1_PWL_SEG7</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF3_PWL_SEG0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF3_PWL_SEG1</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF3_PWL_SEG2</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF3_PWL_SEG3</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF3_PWL_SEG4</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_H_BF3_PWL_SEG5</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF3_PWL_SEG0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF3_PWL_SEG1</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF3_PWL_SEG2</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF3_PWL_SEG3</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF3_PWL_SEG4</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL1_DSCL_EASF_V_BF3_PWL_SEG5</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL1_ISHARP_MODE</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_EN__SHIFT                                                                   0x0</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT                                                          0x4</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT                                                        0x5</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT                                                             0x9</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT                                                     0xa</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT                                                             0xb</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT                                                             0xc</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT                                             0x1c</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK                                                            0x00000010L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK                                                          0x00000060L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_LBA_MODE_MASK                                                               0x00000200L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_FMT_MODE_MASK                                                               0x00000800L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_FMT_NORM_MASK                                                               0x0FFFF000L</div><div class='add'>+#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK                                               0x10000000L</div><div class='add'>+//DSCL1_ISHARP_DELTA_CTRL</div><div class='add'>+#define DSCL1_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT                                          0x0</div><div class='add'>+#define DSCL1_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK                                            0x00000001L</div><div class='add'>+//DSCL1_ISHARP_DELTA_INDEX</div><div class='add'>+#define DSCL1_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define DSCL1_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK                                                     0x0000001FL</div><div class='add'>+//DSCL1_ISHARP_DELTA_DATA</div><div class='add'>+#define DSCL1_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT                                                     0x0</div><div class='add'>+#define DSCL1_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DSCL1_ISHARP_NLDELTA_SOFT_CLIP</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT                                      0x0</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT                                   0x1</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT                                   0x8</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT                                      0x10</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT                                   0x11</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT                                   0x18</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK                                        0x00000001L</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK                                     0x000000FEL</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK                                     0x0000FF00L</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK                                        0x00010000L</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK                                     0x00FE0000L</div><div class='add'>+#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK                                     0xFF000000L</div><div class='add'>+//DSCL1_ISHARP_NOISEDET_THRESHOLD</div><div class='add'>+#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT                                         0x0</div><div class='add'>+#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT                                         0x10</div><div class='add'>+#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK                                           0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK                                           0x03FF0000L</div><div class='add'>+//DSCL1_ISHARP_NOISE_GAIN_PWL</div><div class='add'>+#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT                                      0x0</div><div class='add'>+#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT                                        0x8</div><div class='add'>+#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT                                         0x10</div><div class='add'>+#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK                                        0x0000001FL</div><div class='add'>+#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK                                          0x00001F00L</div><div class='add'>+#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK                                           0x3FFF0000L</div><div class='add'>+//DSCL1_ISHARP_LBA_PWL_SEG0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT                                              0x0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT                                            0xc</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL1_ISHARP_LBA_PWL_SEG1</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT                                              0x0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT                                            0xc</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL1_ISHARP_LBA_PWL_SEG2</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT                                              0x0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT                                            0xc</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL1_ISHARP_LBA_PWL_SEG3</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT                                              0x0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT                                            0xc</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL1_ISHARP_LBA_PWL_SEG4</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT                                              0x0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT                                            0xc</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT                                           0x14</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL1_ISHARP_LBA_PWL_SEG5</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT                                              0x0</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT                                            0xc</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK                                              0x0003F000L</div><div class='add'>+//DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL</div><div class='add'>+#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT                            0x0</div><div class='add'>+#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT                              0x2</div><div class='add'>+#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT                            0x4</div><div class='add'>+#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK                              0x00000003L</div><div class='add'>+#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK                                0x00000004L</div><div class='add'>+#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK                              0x00000030L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_cm_dispdec</div><div class='add'>+//CM1_CM_CONTROL</div><div class='add'>+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM1_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM1_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM1_CM_BIAS_CR_R</div><div class='add'>+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM1_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM1_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM1_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM1_CM_HDR_MULT_COEF</div><div class='add'>+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM1_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM1_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM1_CM_DEALPHA</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM1_CM_COEF_FORMAT</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP1_DPP_CONTROL</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP1_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP1_DPP_CRC_VAL_R_G</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L</div><div class='add'>+//DPP_TOP1_DPP_CRC_VAL_B_A</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L</div><div class='add'>+//DPP_TOP1_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP1_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG2_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG2_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT                                                   0x1</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK                                                     0x00000002L</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG2_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG2_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG2_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG2_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_cm_cur_dispdec</div><div class='add'>+//CM_CUR2_CURSOR0_CONTROL</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                   0x1</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                     0x2</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                           0x3</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                             0x4</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                               0x7</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                   0x10</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                     0x00000002L</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                       0x00000004L</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                             0x00000008L</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                               0x00000070L</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                                 0x00000080L</div><div class='add'>+#define CM_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                     0x00010000L</div><div class='add'>+//CM_CUR2_CURSOR0_COLOR0</div><div class='add'>+#define CM_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR2_CURSOR0_COLOR1</div><div class='add'>+#define CM_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT                                           0x0</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT                                            0x10</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK                                             0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK                                              0xFFFF0000L</div><div class='add'>+//CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT                                   0x0</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT                                    0x10</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK                                     0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK                                      0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_MODE</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT                                             0x2</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT                                              0x4</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK                                               0x0000000CL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK                                                0x00000010L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C11_C12_A</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C13_C14_A</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C21_C22_A</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C23_C24_A</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C31_C32_A</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C33_C34_A</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C11_C12_B</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C13_C14_B</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C21_C22_B</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C23_C24_B</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C31_C32_B</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR2_CUR0_MATRIX_C33_C34_B</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK                                                 0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_dscl_dispdec</div><div class='add'>+//DSCL2_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L</div><div class='add'>+//DSCL2_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL2_SCL_MODE</div><div class='add'>+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL2_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL2_DSCL_CONTROL</div><div class='add'>+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL2_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL2_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_UPDATE</div><div class='add'>+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL2_DSCL_AUTOCAL</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00003FFFL</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x3FFF0000L</div><div class='add'>+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x3FFF0000L</div><div class='add'>+//DSCL2_OTG_H_BLANK</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL2_OTG_V_BLANK</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL2_RECOUT_START</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00003FFFL</div><div class='add'>+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL2_RECOUT_SIZE</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL2_MPC_SIZE</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL2_LB_DATA_FORMAT</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL2_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL2_LB_V_COUNTER</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL2_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL2_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL2_OBUF_CONTROL</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL2_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_MODE</div><div class='add'>+#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL2_DSCL_EASF_V_MODE</div><div class='add'>+#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL2_DSCL_SC_MODE</div><div class='add'>+#define DSCL2_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT                                                         0x0</div><div class='add'>+#define DSCL2_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT                                                            0x8</div><div class='add'>+#define DSCL2_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define DSCL2_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK                                                              0x00000100L</div><div class='add'>+//DSCL2_DSCL_SC_MATRIX_C0C1</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT                                                    0x10</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_SC_MATRIX_C2C3</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT                                                    0x0</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT                                                    0x10</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT                    0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT                    0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT                    0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK                       0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT                    0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT                   0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK                     0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_RINGEST_FORCE</div><div class='add'>+#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT                                        0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT                                        0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK                                          0xFFFF0000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF_CNTL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF_CNTL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG1</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG2</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG3</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG4</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG5</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG6</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF1_PWL_SEG7</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG1</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG2</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG3</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG4</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG5</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG6</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF1_PWL_SEG7</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF3_PWL_SEG0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF3_PWL_SEG1</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF3_PWL_SEG2</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF3_PWL_SEG3</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF3_PWL_SEG4</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_H_BF3_PWL_SEG5</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF3_PWL_SEG0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF3_PWL_SEG1</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF3_PWL_SEG2</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF3_PWL_SEG3</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF3_PWL_SEG4</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL2_DSCL_EASF_V_BF3_PWL_SEG5</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL2_ISHARP_MODE</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_EN__SHIFT                                                                   0x0</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT                                                          0x4</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT                                                        0x5</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT                                                             0x9</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT                                                     0xa</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT                                                             0xb</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT                                                             0xc</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT                                             0x1c</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK                                                            0x00000010L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK                                                          0x00000060L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_LBA_MODE_MASK                                                               0x00000200L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_FMT_MODE_MASK                                                               0x00000800L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_FMT_NORM_MASK                                                               0x0FFFF000L</div><div class='add'>+#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK                                               0x10000000L</div><div class='add'>+//DSCL2_ISHARP_DELTA_CTRL</div><div class='add'>+#define DSCL2_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT                                          0x0</div><div class='add'>+#define DSCL2_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK                                            0x00000001L</div><div class='add'>+//DSCL2_ISHARP_DELTA_INDEX</div><div class='add'>+#define DSCL2_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define DSCL2_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK                                                     0x0000001FL</div><div class='add'>+//DSCL2_ISHARP_DELTA_DATA</div><div class='add'>+#define DSCL2_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT                                                     0x0</div><div class='add'>+#define DSCL2_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DSCL2_ISHARP_NLDELTA_SOFT_CLIP</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT                                      0x0</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT                                   0x1</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT                                   0x8</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT                                      0x10</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT                                   0x11</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT                                   0x18</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK                                        0x00000001L</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK                                     0x000000FEL</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK                                     0x0000FF00L</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK                                        0x00010000L</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK                                     0x00FE0000L</div><div class='add'>+#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK                                     0xFF000000L</div><div class='add'>+//DSCL2_ISHARP_NOISEDET_THRESHOLD</div><div class='add'>+#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT                                         0x0</div><div class='add'>+#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT                                         0x10</div><div class='add'>+#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK                                           0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK                                           0x03FF0000L</div><div class='add'>+//DSCL2_ISHARP_NOISE_GAIN_PWL</div><div class='add'>+#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT                                      0x0</div><div class='add'>+#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT                                        0x8</div><div class='add'>+#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT                                         0x10</div><div class='add'>+#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK                                        0x0000001FL</div><div class='add'>+#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK                                          0x00001F00L</div><div class='add'>+#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK                                           0x3FFF0000L</div><div class='add'>+//DSCL2_ISHARP_LBA_PWL_SEG0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT                                              0x0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT                                            0xc</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL2_ISHARP_LBA_PWL_SEG1</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT                                              0x0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT                                            0xc</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL2_ISHARP_LBA_PWL_SEG2</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT                                              0x0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT                                            0xc</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL2_ISHARP_LBA_PWL_SEG3</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT                                              0x0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT                                            0xc</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL2_ISHARP_LBA_PWL_SEG4</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT                                              0x0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT                                            0xc</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT                                           0x14</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL2_ISHARP_LBA_PWL_SEG5</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT                                              0x0</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT                                            0xc</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK                                              0x0003F000L</div><div class='add'>+//DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL</div><div class='add'>+#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT                            0x0</div><div class='add'>+#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT                              0x2</div><div class='add'>+#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT                            0x4</div><div class='add'>+#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK                              0x00000003L</div><div class='add'>+#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK                                0x00000004L</div><div class='add'>+#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK                              0x00000030L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_cm_dispdec</div><div class='add'>+//CM2_CM_CONTROL</div><div class='add'>+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM2_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM2_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM2_CM_BIAS_CR_R</div><div class='add'>+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM2_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM2_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM2_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM2_CM_HDR_MULT_COEF</div><div class='add'>+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM2_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM2_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM2_CM_DEALPHA</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM2_CM_COEF_FORMAT</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP2_DPP_CONTROL</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP2_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP2_DPP_CRC_VAL_R_G</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L</div><div class='add'>+//DPP_TOP2_DPP_CRC_VAL_B_A</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L</div><div class='add'>+//DPP_TOP2_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP2_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_cnvc_cfg_dispdec</div><div class='add'>+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL</div><div class='add'>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L</div><div class='add'>+//CNVC_CFG3_FORMAT_CONTROL</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L</div><div class='add'>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L</div><div class='add'>+//CNVC_CFG3_FCNV_FP_BIAS_R</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_BIAS_G</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_BIAS_B</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_SCALE_R</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_SCALE_G</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_FCNV_FP_SCALE_B</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_CONTROL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT                                                   0x1</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK                                                     0x00000002L</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_ALPHA</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_RED</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_GREEN</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_COLOR_KEYER_BLUE</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_ALPHA_2BIT_LUT</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L</div><div class='add'>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L</div><div class='add'>+//CNVC_CFG3_PRE_DEALPHA</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_MODE</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C11_C12</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C13_C14</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C21_C22</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C23_C24</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C31_C32</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_C33_C34</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C11_C12</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C13_C14</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C21_C22</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C23_C24</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C31_C32</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_PRE_CSC_B_C33_C34</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL</div><div class='add'>+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L</div><div class='add'>+//CNVC_CFG3_CNVC_COEF_FORMAT</div><div class='add'>+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L</div><div class='add'>+//CNVC_CFG3_PRE_DEGAM</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L</div><div class='add'>+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L</div><div class='add'>+//CNVC_CFG3_PRE_REALPHA</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L</div><div class='add'>+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_cm_cur_dispdec</div><div class='add'>+//CM_CUR3_CURSOR0_CONTROL</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                   0x1</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                     0x2</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                           0x3</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                             0x4</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                               0x7</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                   0x10</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                     0x00000002L</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                       0x00000004L</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                             0x00000008L</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                               0x00000070L</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                                 0x00000080L</div><div class='add'>+#define CM_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                     0x00010000L</div><div class='add'>+//CM_CUR3_CURSOR0_COLOR0</div><div class='add'>+#define CM_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR3_CURSOR0_COLOR1</div><div class='add'>+#define CM_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                            0x0</div><div class='add'>+#define CM_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                              0x00FFFFFFL</div><div class='add'>+//CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT                                           0x0</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT                                            0x10</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK                                             0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK                                              0xFFFF0000L</div><div class='add'>+//CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT                                   0x0</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT                                    0x10</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK                                     0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK                                      0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_MODE</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT                                                     0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT                                             0x2</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT                                              0x4</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK                                               0x0000000CL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK                                                0x00000010L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C11_C12_A</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C13_C14_A</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C21_C22_A</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C23_C24_A</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C31_C32_A</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C33_C34_A</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C11_C12_B</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C13_C14_B</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C21_C22_B</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C23_C24_B</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C31_C32_B</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK                                                 0xFFFF0000L</div><div class='add'>+//CM_CUR3_CUR0_MATRIX_C33_C34_B</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT                                               0x0</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT                                               0x10</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK                                                 0x0000FFFFL</div><div class='add'>+#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK                                                 0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_dscl_dispdec</div><div class='add'>+//DSCL3_SCL_COEF_RAM_TAP_SELECT</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L</div><div class='add'>+//DSCL3_SCL_COEF_RAM_TAP_DATA</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L</div><div class='add'>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L</div><div class='add'>+//DSCL3_SCL_MODE</div><div class='add'>+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18</div><div class='add'>+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L</div><div class='add'>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L</div><div class='add'>+//DSCL3_SCL_TAP_CONTROL</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L</div><div class='add'>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L</div><div class='add'>+//DSCL3_DSCL_CONTROL</div><div class='add'>+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L</div><div class='add'>+//DSCL3_DSCL_2TAP_CONTROL</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L</div><div class='add'>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L</div><div class='add'>+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL</div><div class='add'>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_INIT</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_HORZ_FILTER_INIT_C</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT_BOT</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT_C</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L</div><div class='add'>+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL</div><div class='add'>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L</div><div class='add'>+//DSCL3_SCL_BLACK_COLOR</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL</div><div class='add'>+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_UPDATE</div><div class='add'>+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L</div><div class='add'>+//DSCL3_DSCL_AUTOCAL</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L</div><div class='add'>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L</div><div class='add'>+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00003FFFL</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x3FFF0000L</div><div class='add'>+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00003FFFL</div><div class='add'>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x3FFF0000L</div><div class='add'>+//DSCL3_OTG_H_BLANK</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL3_OTG_V_BLANK</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL</div><div class='add'>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL3_RECOUT_START</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00003FFFL</div><div class='add'>+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x3FFF0000L</div><div class='add'>+//DSCL3_RECOUT_SIZE</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL</div><div class='add'>+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L</div><div class='add'>+//DSCL3_MPC_SIZE</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL</div><div class='add'>+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L</div><div class='add'>+//DSCL3_LB_DATA_FORMAT</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L</div><div class='add'>+//DSCL3_LB_MEMORY_CTRL</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L</div><div class='add'>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L</div><div class='add'>+//DSCL3_LB_V_COUNTER</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL</div><div class='add'>+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L</div><div class='add'>+//DSCL3_DSCL_MEM_PWR_CTRL</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L</div><div class='add'>+//DSCL3_DSCL_MEM_PWR_STATUS</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L</div><div class='add'>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L</div><div class='add'>+//DSCL3_OBUF_CONTROL</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L</div><div class='add'>+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L</div><div class='add'>+//DSCL3_OBUF_MEM_PWR_CTRL</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L</div><div class='add'>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_MODE</div><div class='add'>+#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL3_DSCL_EASF_V_MODE</div><div class='add'>+#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT                                                          0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT                                            0x4</div><div class='add'>+#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT                                           0x8</div><div class='add'>+#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK                                              0x00000010L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK                                             0x00003F00L</div><div class='add'>+//DSCL3_DSCL_SC_MODE</div><div class='add'>+#define DSCL3_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT                                                         0x0</div><div class='add'>+#define DSCL3_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT                                                            0x8</div><div class='add'>+#define DSCL3_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define DSCL3_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK                                                              0x00000100L</div><div class='add'>+//DSCL3_DSCL_SC_MATRIX_C0C1</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT                                                    0x10</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_SC_MATRIX_C2C3</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT                                                    0x0</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT                                                    0x10</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK                                                      0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK                                                      0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT                       0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT                       0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK                         0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK                         0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT                  0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT                  0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK                    0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK                    0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT                    0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT                    0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT                    0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK                       0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK                      0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT                    0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT                   0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK                      0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK                     0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_RINGEST_FORCE</div><div class='add'>+#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT                                        0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT                                        0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK                                          0xFFFF0000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF_CNTL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF_CNTL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT                                                 0x8</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT                                                 0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT                                           0x18</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT                                             0x1c</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK                                                   0x00000F00L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK                                                   0x00030000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK                                             0x00F00000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK                                             0x0F000000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK                                               0xF0000000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT                                         0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT                                         0x8</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT                                         0x10</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT                                         0x18</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK                                           0x0000003FL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK                                           0x00003F00L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK                                           0x003F0000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK                                           0x3F000000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG1</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG2</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG3</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG4</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG5</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG6</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF1_PWL_SEG7</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG1</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG2</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG3</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG4</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG5</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG6</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT                                  0x14</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK                                     0x0003F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK                                    0x7FF00000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF1_PWL_SEG7</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK                                       0x000007FFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK                                     0x0003F000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF3_PWL_SEG0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF3_PWL_SEG1</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF3_PWL_SEG2</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF3_PWL_SEG3</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF3_PWL_SEG4</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_H_BF3_PWL_SEG5</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF3_PWL_SEG0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF3_PWL_SEG1</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF3_PWL_SEG2</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF3_PWL_SEG3</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF3_PWL_SEG4</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT                                  0x13</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK                                     0x0007F000L</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK                                    0xFFF80000L</div><div class='add'>+//DSCL3_DSCL_EASF_V_BF3_PWL_SEG5</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT                                     0x0</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT                                   0xc</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK                                       0x00000FFFL</div><div class='add'>+#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK                                     0x0007F000L</div><div class='add'>+//DSCL3_ISHARP_MODE</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_EN__SHIFT                                                                   0x0</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT                                                          0x4</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT                                                        0x5</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT                                                             0x9</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT                                                     0xa</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT                                                             0xb</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT                                                             0xc</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT                                             0x1c</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_EN_MASK                                                                     0x00000001L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK                                                            0x00000010L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK                                                          0x00000060L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_LBA_MODE_MASK                                                               0x00000200L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK                                                       0x00000400L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_FMT_MODE_MASK                                                               0x00000800L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_FMT_NORM_MASK                                                               0x0FFFF000L</div><div class='add'>+#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK                                               0x10000000L</div><div class='add'>+//DSCL3_ISHARP_DELTA_CTRL</div><div class='add'>+#define DSCL3_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT                                          0x0</div><div class='add'>+#define DSCL3_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK                                            0x00000001L</div><div class='add'>+//DSCL3_ISHARP_DELTA_INDEX</div><div class='add'>+#define DSCL3_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define DSCL3_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK                                                     0x0000001FL</div><div class='add'>+//DSCL3_ISHARP_DELTA_DATA</div><div class='add'>+#define DSCL3_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT                                                     0x0</div><div class='add'>+#define DSCL3_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DSCL3_ISHARP_NLDELTA_SOFT_CLIP</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT                                      0x0</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT                                   0x1</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT                                   0x8</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT                                      0x10</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT                                   0x11</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT                                   0x18</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK                                        0x00000001L</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK                                     0x000000FEL</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK                                     0x0000FF00L</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK                                        0x00010000L</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK                                     0x00FE0000L</div><div class='add'>+#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK                                     0xFF000000L</div><div class='add'>+//DSCL3_ISHARP_NOISEDET_THRESHOLD</div><div class='add'>+#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT                                         0x0</div><div class='add'>+#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT                                         0x10</div><div class='add'>+#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK                                           0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK                                           0x03FF0000L</div><div class='add'>+//DSCL3_ISHARP_NOISE_GAIN_PWL</div><div class='add'>+#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT                                      0x0</div><div class='add'>+#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT                                        0x8</div><div class='add'>+#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT                                         0x10</div><div class='add'>+#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK                                        0x0000001FL</div><div class='add'>+#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK                                          0x00001F00L</div><div class='add'>+#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK                                           0x3FFF0000L</div><div class='add'>+//DSCL3_ISHARP_LBA_PWL_SEG0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT                                              0x0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT                                            0xc</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL3_ISHARP_LBA_PWL_SEG1</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT                                              0x0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT                                            0xc</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL3_ISHARP_LBA_PWL_SEG2</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT                                              0x0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT                                            0xc</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL3_ISHARP_LBA_PWL_SEG3</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT                                              0x0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT                                            0xc</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL3_ISHARP_LBA_PWL_SEG4</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT                                              0x0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT                                            0xc</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT                                           0x14</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK                                              0x0003F000L</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK                                             0x1FF00000L</div><div class='add'>+//DSCL3_ISHARP_LBA_PWL_SEG5</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT                                              0x0</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT                                            0xc</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK                                                0x000003FFL</div><div class='add'>+#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK                                              0x0003F000L</div><div class='add'>+//DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL</div><div class='add'>+#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT                            0x0</div><div class='add'>+#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT                              0x2</div><div class='add'>+#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT                            0x4</div><div class='add'>+#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK                              0x00000003L</div><div class='add'>+#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK                                0x00000004L</div><div class='add'>+#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK                              0x00000030L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_cm_dispdec</div><div class='add'>+//CM3_CM_CONTROL</div><div class='add'>+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0</div><div class='add'>+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8</div><div class='add'>+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L</div><div class='add'>+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L</div><div class='add'>+//CM3_CM_POST_CSC_CONTROL</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L</div><div class='add'>+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL</div><div class='add'>+//CM3_CM_POST_CSC_C11_C12</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C13_C14</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C21_C22</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C23_C24</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C31_C32</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_C33_C34</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C11_C12</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C13_C14</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C21_C22</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C23_C24</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C31_C32</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_POST_CSC_B_C33_C34</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL</div><div class='add'>+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L</div><div class='add'>+//CM3_CM_BIAS_CR_R</div><div class='add'>+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0</div><div class='add'>+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL</div><div class='add'>+//CM3_CM_BIAS_Y_G_CB_B</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL</div><div class='add'>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_CONTROL</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L</div><div class='add'>+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L</div><div class='add'>+//CM3_CM_GAMCOR_LUT_INDEX</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL</div><div class='add'>+//CM3_CM_GAMCOR_LUT_DATA</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_LUT_CONTROL</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L</div><div class='add'>+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_OFFSET_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_OFFSET_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_OFFSET_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_0_1</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_2_3</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_4_5</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_6_7</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_8_9</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_10_11</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_12_13</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_14_15</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_16_17</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_18_19</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_20_21</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_22_23</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_24_25</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_26_27</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_28_29</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_30_31</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMA_REGION_32_33</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_OFFSET_B</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_OFFSET_G</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_OFFSET_R</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_0_1</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_2_3</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_4_5</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_6_7</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_8_9</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_10_11</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_12_13</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_14_15</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_16_17</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_18_19</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_20_21</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_22_23</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_24_25</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_26_27</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_28_29</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_30_31</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_GAMCOR_RAMB_REGION_32_33</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L</div><div class='add'>+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L</div><div class='add'>+//CM3_CM_HDR_MULT_COEF</div><div class='add'>+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0</div><div class='add'>+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL</div><div class='add'>+//CM3_CM_MEM_PWR_CTRL</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L</div><div class='add'>+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L</div><div class='add'>+//CM3_CM_MEM_PWR_STATUS</div><div class='add'>+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0</div><div class='add'>+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L</div><div class='add'>+//CM3_CM_DEALPHA</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L</div><div class='add'>+//CM3_CM_COEF_FORMAT</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L</div><div class='add'>+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_dpp_top_dispdec</div><div class='add'>+//DPP_TOP3_DPP_CONTROL</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT                                                         0x18</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK                                                           0x01000000L</div><div class='add'>+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L</div><div class='add'>+//DPP_TOP3_DPP_SOFT_RESET</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L</div><div class='add'>+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L</div><div class='add'>+//DPP_TOP3_DPP_CRC_VAL_R_G</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L</div><div class='add'>+//DPP_TOP3_DPP_CRC_VAL_B_A</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L</div><div class='add'>+//DPP_TOP3_DPP_CRC_CTRL</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L</div><div class='add'>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L</div><div class='add'>+//DPP_TOP3_HOST_READ_CONTROL</div><div class='add'>+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0</div><div class='add'>+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc0_dispdec</div><div class='add'>+//MPCC0_MPCC_TOP_SEL</div><div class='add'>+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC0_MPCC_BOT_SEL</div><div class='add'>+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC0_MPCC_OPP_ID</div><div class='add'>+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC0_MPCC_CONTROL</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC0_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC0_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC0_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC0_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC0_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC0_MPCC_BG_R_CR</div><div class='add'>+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC0_MPCC_BG_G_Y</div><div class='add'>+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC0_MPCC_BG_B_CB</div><div class='add'>+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC0_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC0_MPCC_STATUS</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc1_dispdec</div><div class='add'>+//MPCC1_MPCC_TOP_SEL</div><div class='add'>+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC1_MPCC_BOT_SEL</div><div class='add'>+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC1_MPCC_OPP_ID</div><div class='add'>+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC1_MPCC_CONTROL</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC1_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC1_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC1_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC1_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC1_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC1_MPCC_BG_R_CR</div><div class='add'>+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC1_MPCC_BG_G_Y</div><div class='add'>+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC1_MPCC_BG_B_CB</div><div class='add'>+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC1_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC1_MPCC_STATUS</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc2_dispdec</div><div class='add'>+//MPCC2_MPCC_TOP_SEL</div><div class='add'>+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC2_MPCC_BOT_SEL</div><div class='add'>+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC2_MPCC_OPP_ID</div><div class='add'>+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC2_MPCC_CONTROL</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC2_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC2_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC2_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC2_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC2_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC2_MPCC_BG_R_CR</div><div class='add'>+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC2_MPCC_BG_G_Y</div><div class='add'>+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC2_MPCC_BG_B_CB</div><div class='add'>+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC2_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC2_MPCC_STATUS</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc3_dispdec</div><div class='add'>+//MPCC3_MPCC_TOP_SEL</div><div class='add'>+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC3_MPCC_BOT_SEL</div><div class='add'>+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL</div><div class='add'>+//MPCC3_MPCC_OPP_ID</div><div class='add'>+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL</div><div class='add'>+//MPCC3_MPCC_CONTROL</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L</div><div class='add'>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L</div><div class='add'>+//MPCC3_MPCC_SM_CONTROL</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L</div><div class='add'>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L</div><div class='add'>+//MPCC3_MPCC_UPDATE_LOCK_SEL</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL</div><div class='add'>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L</div><div class='add'>+//MPCC3_MPCC_TOP_GAIN</div><div class='add'>+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0</div><div class='add'>+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL</div><div class='add'>+//MPCC3_MPCC_BOT_GAIN_INSIDE</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL</div><div class='add'>+//MPCC3_MPCC_BOT_GAIN_OUTSIDE</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0</div><div class='add'>+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT                          0x0</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT                  0x4</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK                            0x00000001L</div><div class='add'>+#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK                    0x00000010L</div><div class='add'>+//MPCC3_MPCC_BG_R_CR</div><div class='add'>+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC3_MPCC_BG_G_Y</div><div class='add'>+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0</div><div class='add'>+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL</div><div class='add'>+//MPCC3_MPCC_BG_B_CB</div><div class='add'>+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0</div><div class='add'>+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL</div><div class='add'>+//MPCC3_MPCC_MEM_PWR_CTRL</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L</div><div class='add'>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L</div><div class='add'>+//MPCC3_MPCC_STATUS</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L</div><div class='add'>+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpc_cfg_dispdec</div><div class='add'>+//MPC_CLOCK_CONTROL</div><div class='add'>+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1</div><div class='add'>+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4</div><div class='add'>+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L</div><div class='add'>+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L</div><div class='add'>+//MPC_SOFT_RESET</div><div class='add'>+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0</div><div class='add'>+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1</div><div class='add'>+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2</div><div class='add'>+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f</div><div class='add'>+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L</div><div class='add'>+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L</div><div class='add'>+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L</div><div class='add'>+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L</div><div class='add'>+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L</div><div class='add'>+//MPC_CRC_CTRL</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L</div><div class='add'>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L</div><div class='add'>+//MPC_CRC_SEL_CONTROL</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L</div><div class='add'>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L</div><div class='add'>+//MPC_CRC_RESULT_AR</div><div class='add'>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0</div><div class='add'>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10</div><div class='add'>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL</div><div class='add'>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L</div><div class='add'>+//MPC_CRC_RESULT_GB</div><div class='add'>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0</div><div class='add'>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10</div><div class='add'>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL</div><div class='add'>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L</div><div class='add'>+//MPC_CRC_RESULT_C</div><div class='add'>+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0</div><div class='add'>+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL</div><div class='add'>+//MPC_BYPASS_BG_AR</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL</div><div class='add'>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L</div><div class='add'>+//MPC_BYPASS_BG_GB</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL</div><div class='add'>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L</div><div class='add'>+//MPC_HOST_READ_CONTROL</div><div class='add'>+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0</div><div class='add'>+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL</div><div class='add'>+//MPC_DPP_PENDING_STATUS</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L</div><div class='add'>+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L</div><div class='add'>+//MPC_PENDING_STATUS_MISC</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L</div><div class='add'>+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET1</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET1</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET1</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET1</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET1</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET2</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET2</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET2</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET2</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET2</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//ADR_CFG_CUR_VUPDATE_LOCK_SET3</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0</div><div class='add'>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L</div><div class='add'>+//ADR_CFG_VUPDATE_LOCK_SET3</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0</div><div class='add'>+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L</div><div class='add'>+//ADR_VUPDATE_LOCK_SET3</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CFG_VUPDATE_LOCK_SET3</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//CUR_VUPDATE_LOCK_SET3</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0</div><div class='add'>+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L</div><div class='add'>+//HUBP0_3DLUT_FL_CONFIG</div><div class='add'>+#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_MODE__SHIFT                                                     0x0</div><div class='add'>+#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_FORMAT__SHIFT                                                   0x4</div><div class='add'>+#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_FORMAT_MASK                                                     0x00000030L</div><div class='add'>+//HUBP0_3DLUT_FL_BIAS_SCALE</div><div class='add'>+#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_BIAS__SHIFT                                                 0x0</div><div class='add'>+#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_SCALE__SHIFT                                                0x10</div><div class='add'>+#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_BIAS_MASK                                                   0x0000FFFFL</div><div class='add'>+#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_SCALE_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP1_3DLUT_FL_CONFIG</div><div class='add'>+#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_MODE__SHIFT                                                     0x0</div><div class='add'>+#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_FORMAT__SHIFT                                                   0x4</div><div class='add'>+#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_FORMAT_MASK                                                     0x00000030L</div><div class='add'>+//HUBP1_3DLUT_FL_BIAS_SCALE</div><div class='add'>+#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_BIAS__SHIFT                                                 0x0</div><div class='add'>+#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_SCALE__SHIFT                                                0x10</div><div class='add'>+#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_BIAS_MASK                                                   0x0000FFFFL</div><div class='add'>+#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_SCALE_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP2_3DLUT_FL_CONFIG</div><div class='add'>+#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_MODE__SHIFT                                                     0x0</div><div class='add'>+#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_FORMAT__SHIFT                                                   0x4</div><div class='add'>+#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_FORMAT_MASK                                                     0x00000030L</div><div class='add'>+//HUBP2_3DLUT_FL_BIAS_SCALE</div><div class='add'>+#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_BIAS__SHIFT                                                 0x0</div><div class='add'>+#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_SCALE__SHIFT                                                0x10</div><div class='add'>+#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_BIAS_MASK                                                   0x0000FFFFL</div><div class='add'>+#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_SCALE_MASK                                                  0xFFFF0000L</div><div class='add'>+//HUBP3_3DLUT_FL_CONFIG</div><div class='add'>+#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_MODE__SHIFT                                                     0x0</div><div class='add'>+#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_FORMAT__SHIFT                                                   0x4</div><div class='add'>+#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_MODE_MASK                                                       0x00000003L</div><div class='add'>+#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_FORMAT_MASK                                                     0x00000030L</div><div class='add'>+//HUBP3_3DLUT_FL_BIAS_SCALE</div><div class='add'>+#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_BIAS__SHIFT                                                 0x0</div><div class='add'>+#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_SCALE__SHIFT                                                0x10</div><div class='add'>+#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_BIAS_MASK                                                   0x0000FFFFL</div><div class='add'>+#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_SCALE_MASK                                                  0xFFFF0000L</div><div class='add'>+//MPC_DWB0_MUX</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL</div><div class='add'>+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam0_dispdec</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam1_dispdec</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam2_dispdec</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_ogam3_dispdec</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L</div><div class='add'>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L</div><div class='add'>+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L</div><div class='add'>+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L</div><div class='add'>+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm0_dispdec</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT       0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK         0x00000001L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT             0x7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK                       0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK               0x00000180L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT     0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK       0x00000001L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT           0x7</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK                     0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK             0x00000180L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT                               0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK                                 0x0000000FL</div><div class='add'>+//MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT                              0x0</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT                    0x1</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT                    0x2</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK                                0x00000001L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK                      0x00000002L</div><div class='add'>+#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK                      0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm1_dispdec</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT       0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK         0x00000001L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT             0x7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK                       0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK               0x00000180L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT     0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK       0x00000001L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT           0x7</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK                     0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK             0x00000180L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT                               0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK                                 0x0000000FL</div><div class='add'>+//MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT                              0x0</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT                    0x1</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT                    0x2</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK                                0x00000001L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK                      0x00000002L</div><div class='add'>+#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK                      0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm2_dispdec</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT       0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK         0x00000001L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT             0x7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK                       0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK               0x00000180L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT     0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK       0x00000001L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT           0x7</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK                     0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK             0x00000180L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT                               0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK                                 0x0000000FL</div><div class='add'>+//MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT                              0x0</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT                    0x1</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT                    0x2</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK                                0x00000001L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK                      0x00000002L</div><div class='add'>+#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK                      0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpcc_mcm3_dispdec</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT                                    0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT                                0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK                                      0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK                                  0x0000000CL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK                                     0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK                                       0x0000FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT                                   0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK                                     0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK                                     0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK                                   0x000000FFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK                                     0x00FFFFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                 0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT                     0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK                   0x00000007L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK                       0x00000010L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT   0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK             0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK     0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK                 0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK            0x3FFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT       0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT         0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT       0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK           0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK         0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK           0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK         0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT    0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT      0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT    0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK        0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK      0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK        0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK      0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_MODE</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT                                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT                                             0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT                                     0x8</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK                                               0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK                                               0x00000010L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK                                       0x00000300L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT                                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK                                             0x000007FFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT                                            0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT                                            0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK                                              0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK                                              0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT                                 0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK                                   0xFFFFFFFCL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT                            0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT                           0x8</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT                           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK                        0x0000000FL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK                              0x00000010L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK                             0x00000100L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK                             0x00030000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT                       0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK                         0x0000FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT                             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT                              0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK                               0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK                                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT                                          0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT                                        0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT                                   0x3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT                                  0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT                                0x6</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK                                            0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK                                          0x00000004L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK                                     0x00000008L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK                                    0x00000030L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK                                  0x00000040L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT                                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK                                     0x000001FFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK                                       0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT                      0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT                        0x3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT                              0x5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT                              0x6</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT                           0x7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK                        0x00000007L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK                          0x00000018L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK                                0x00000020L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK                                0x00000040L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK                             0x00000080L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT             0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT     0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK               0x0003FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK       0x07F00000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT  0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK   0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK     0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK             0x0003FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT          0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK            0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT                           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK                             0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT           0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT         0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT           0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT         0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK             0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK           0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK             0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK           0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT        0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT      0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT        0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT      0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK          0x000001FFL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK        0x00007000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK          0x01FF0000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK        0x70000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT       0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK         0x00000001L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT             0x7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK                       0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK               0x00000180L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT                0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT                0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK                  0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK                  0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT     0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK       0x00000001L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT           0x7</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK                     0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK             0x00000180L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT              0x0</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT              0x10</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK                0x0000FFFFL</div><div class='add'>+#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK                0xFFFF0000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT                                 0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT                                   0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT                              0x4</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT                                  0x8</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT                                    0xa</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT                               0xc</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT                                  0x10</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT                                    0x12</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT                               0x14</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT                                 0x18</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT                                  0x1a</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT                                  0x1c</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK                                   0x00000003L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK                                     0x00000004L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK                                0x00000030L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK                                    0x00000300L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK                                      0x00000400L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00003000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK                                    0x00030000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK                                      0x00040000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK                                 0x00300000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK                                   0x03000000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK                                    0x0C000000L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK                                    0x30000000L</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT                               0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK                                 0x0000000FL</div><div class='add'>+//MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT                              0x0</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT                    0x1</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT                    0x2</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK                                0x00000001L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK                      0x00000002L</div><div class='add'>+#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK                      0x00000004L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_mpc_mpc_ocsc_dispdec</div><div class='add'>+//MPC_OUT0_MUX</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT0_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT0_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT0_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT1_MUX</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT1_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT1_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT1_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT2_MUX</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT2_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT2_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT2_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT3_MUX</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L</div><div class='add'>+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L</div><div class='add'>+//MPC_OUT3_DENORM_CONTROL</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L</div><div class='add'>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L</div><div class='add'>+//MPC_OUT3_DENORM_CLAMP_G_Y</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L</div><div class='add'>+//MPC_OUT3_DENORM_CLAMP_B_CB</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL</div><div class='add'>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L</div><div class='add'>+//MPC_OUT_CSC_COEF_FORMAT</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L</div><div class='add'>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L</div><div class='add'>+//MPC_OUT0_CSC_MODE</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT0_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT0_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_MODE</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT1_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT1_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_MODE</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT2_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT2_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_MODE</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L</div><div class='add'>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L</div><div class='add'>+//MPC_OUT3_CSC_C11_C12_A</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C13_C14_A</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C21_C22_A</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C23_C24_A</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C31_C32_A</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C33_C34_A</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C11_C12_B</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C13_C14_B</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C21_C22_B</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C23_C24_B</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C31_C32_B</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L</div><div class='add'>+//MPC_OUT3_CSC_C33_C34_B</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL</div><div class='add'>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm0_dispdec</div><div class='add'>+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM0_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM0_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_CNTL</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM0_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0xa</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x14</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x000001FFL</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x0007FC00L</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x1FF00000L</div><div class='add'>+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_PWL_CNTL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT                                         0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX__SHIFT                                                0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK                                           0x0000003FL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX_MASK                                                  0x001F0000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT                                        0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT                                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK                                          0x00007FFFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK                                         0x07FF0000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_THRES_DATA</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1__SHIFT                                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2__SHIFT                                             0x10</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1_MASK                                               0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2_MASK                                               0x03FF0000L</div><div class='add'>+//ABM0_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM0_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_INDEX</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT                                             0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK                                               0x0000003FL</div><div class='add'>+//ABM0_DC_ABM1_HG_RESULT_DATA</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT                                               0x0</div><div class='add'>+#define ABM0_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM0_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm1_dispdec</div><div class='add'>+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM1_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM1_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_CNTL</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM1_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0xa</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x14</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x000001FFL</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x0007FC00L</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x1FF00000L</div><div class='add'>+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_PWL_CNTL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT                                         0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX__SHIFT                                                0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK                                           0x0000003FL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX_MASK                                                  0x001F0000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT                                        0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT                                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK                                          0x00007FFFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK                                         0x07FF0000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_THRES_DATA</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1__SHIFT                                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2__SHIFT                                             0x10</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1_MASK                                               0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2_MASK                                               0x03FF0000L</div><div class='add'>+//ABM1_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM1_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_INDEX</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT                                             0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK                                               0x0000003FL</div><div class='add'>+//ABM1_DC_ABM1_HG_RESULT_DATA</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT                                               0x0</div><div class='add'>+#define ABM1_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM1_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm2_dispdec</div><div class='add'>+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM2_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM2_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_CNTL</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM2_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0xa</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x14</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x000001FFL</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x0007FC00L</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x1FF00000L</div><div class='add'>+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_PWL_CNTL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT                                         0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX__SHIFT                                                0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK                                           0x0000003FL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX_MASK                                                  0x001F0000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT                                        0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT                                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK                                          0x00007FFFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK                                         0x07FF0000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_THRES_DATA</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1__SHIFT                                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2__SHIFT                                             0x10</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1_MASK                                               0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2_MASK                                               0x03FF0000L</div><div class='add'>+//ABM2_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM2_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_INDEX</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT                                             0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK                                               0x0000003FL</div><div class='add'>+//ABM2_DC_ABM1_HG_RESULT_DATA</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT                                               0x0</div><div class='add'>+#define ABM2_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM2_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_abm3_dispdec</div><div class='add'>+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_USER_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0</div><div class='add'>+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_TARGET_ABM_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0</div><div class='add'>+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL</div><div class='add'>+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0</div><div class='add'>+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE</div><div class='add'>+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0</div><div class='add'>+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE</div><div class='add'>+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0</div><div class='add'>+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL</div><div class='add'>+//ABM3_BL1_PWM_ABM_CNTL</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L</div><div class='add'>+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L</div><div class='add'>+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L</div><div class='add'>+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L</div><div class='add'>+//ABM3_BL1_PWM_GRP2_REG_LOCK</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L</div><div class='add'>+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_CNTL</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L</div><div class='add'>+//ABM3_DC_ABM1_IPCSC_COEFF_SEL</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0xa</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x14</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x000001FFL</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x0007FC00L</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x1FF00000L</div><div class='add'>+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_PWL_CNTL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT                                         0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX__SHIFT                                                0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT                                                       0x1f</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK                                           0x0000003FL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_THRES_INDEX_MASK                                                  0x001F0000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK                                                         0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT                                        0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT                                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK                                          0x00007FFFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK                                         0x07FF0000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_THRES_DATA</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1__SHIFT                                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2__SHIFT                                             0x10</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_1_MASK                                               0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_ACE_THRES_DATA__ABM1_ACE_THRES_DATA_2_MASK                                               0x03FF0000L</div><div class='add'>+//ABM3_DC_ABM1_ACE_CNTL_MISC</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L</div><div class='add'>+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L</div><div class='add'>+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_HG_MISC_CTRL</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_SUM_OF_LUMA</div><div class='add'>+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L</div><div class='add'>+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L</div><div class='add'>+//ABM3_DC_ABM1_LS_PIXEL_COUNT</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT</div><div class='add'>+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_SAMPLE_RATE</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_LS_SAMPLE_RATE</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L</div><div class='add'>+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT                           0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK                             0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_INDEX</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT                                             0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK                                               0x0000003FL</div><div class='add'>+//ABM3_DC_ABM1_HG_RESULT_DATA</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT                                               0x0</div><div class='add'>+#define ABM3_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//ABM3_DC_ABM1_BL_MASTER_LOCK</div><div class='add'>+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f</div><div class='add'>+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg0_dispdec</div><div class='add'>+//DPG0_DPG_CONTROL</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG0_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG0_DPG_DIMENSIONS</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG0_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG0_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG0_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG0_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG0_DPG_STATUS</div><div class='add'>+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt0_dispdec</div><div class='add'>+//FMT0_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT0_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT0_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT0_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT0_FMT_CONTROL</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT0_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT0_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT0_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT0_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT0_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT0_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT0_FMT_422_CONTROL</div><div class='add'>+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf0_dispdec</div><div class='add'>+//OPPBUF0_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF0_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF0_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF0_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe0_dispdec</div><div class='add'>+//OPP_PIPE0_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc0_dispdec</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg1_dispdec</div><div class='add'>+//DPG1_DPG_CONTROL</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG1_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG1_DPG_DIMENSIONS</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG1_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG1_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG1_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG1_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG1_DPG_STATUS</div><div class='add'>+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt1_dispdec</div><div class='add'>+//FMT1_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT1_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT1_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT1_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT1_FMT_CONTROL</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT1_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT1_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT1_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT1_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT1_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT1_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT1_FMT_422_CONTROL</div><div class='add'>+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf1_dispdec</div><div class='add'>+//OPPBUF1_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF1_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF1_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF1_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe1_dispdec</div><div class='add'>+//OPP_PIPE1_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc1_dispdec</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg2_dispdec</div><div class='add'>+//DPG2_DPG_CONTROL</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG2_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG2_DPG_DIMENSIONS</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG2_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG2_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG2_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG2_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG2_DPG_STATUS</div><div class='add'>+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt2_dispdec</div><div class='add'>+//FMT2_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT2_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT2_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT2_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT2_FMT_CONTROL</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT2_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT2_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT2_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT2_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT2_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT2_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT2_FMT_422_CONTROL</div><div class='add'>+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf2_dispdec</div><div class='add'>+//OPPBUF2_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF2_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF2_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF2_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe2_dispdec</div><div class='add'>+//OPP_PIPE2_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc2_dispdec</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dpg3_dispdec</div><div class='add'>+//DPG3_DPG_CONTROL</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L</div><div class='add'>+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L</div><div class='add'>+//DPG3_DPG_RAMP_CONTROL</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L</div><div class='add'>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L</div><div class='add'>+//DPG3_DPG_DIMENSIONS</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL</div><div class='add'>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L</div><div class='add'>+//DPG3_DPG_COLOUR_R_CR</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG3_DPG_COLOUR_G_Y</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L</div><div class='add'>+//DPG3_DPG_COLOUR_B_CB</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L</div><div class='add'>+//DPG3_DPG_OFFSET_SEGMENT</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL</div><div class='add'>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L</div><div class='add'>+//DPG3_DPG_STATUS</div><div class='add'>+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0</div><div class='add'>+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_fmt3_dispdec</div><div class='add'>+//FMT3_FMT_CLAMP_COMPONENT_R</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT3_FMT_CLAMP_COMPONENT_G</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT3_FMT_CLAMP_COMPONENT_B</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL</div><div class='add'>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L</div><div class='add'>+//FMT3_FMT_DYNAMIC_EXP_CNTL</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L</div><div class='add'>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L</div><div class='add'>+//FMT3_FMT_CONTROL</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L</div><div class='add'>+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L</div><div class='add'>+//FMT3_FMT_BIT_DEPTH_CONTROL</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L</div><div class='add'>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L</div><div class='add'>+//FMT3_FMT_DITHER_RAND_R_SEED</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT3_FMT_DITHER_RAND_G_SEED</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L</div><div class='add'>+//FMT3_FMT_DITHER_RAND_B_SEED</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL</div><div class='add'>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L</div><div class='add'>+//FMT3_FMT_CLAMP_CNTL</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L</div><div class='add'>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L</div><div class='add'>+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL</div><div class='add'>+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0</div><div class='add'>+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL</div><div class='add'>+//FMT3_FMT_MAP420_MEMORY_CONTROL</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L</div><div class='add'>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L</div><div class='add'>+//FMT3_FMT_422_CONTROL</div><div class='add'>+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0</div><div class='add'>+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_oppbuf3_dispdec</div><div class='add'>+//OPPBUF3_OPPBUF_CONTROL</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L</div><div class='add'>+//OPPBUF3_OPPBUF_3D_PARAMETERS_0</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L</div><div class='add'>+//OPPBUF3_OPPBUF_3D_PARAMETERS_1</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL</div><div class='add'>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L</div><div class='add'>+//OPPBUF3_OPPBUF_CONTROL1</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0</div><div class='add'>+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe3_dispdec</div><div class='add'>+//OPP_PIPE3_OPP_PIPE_CONTROL</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L</div><div class='add'>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_pipe_crc3_dispdec</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L</div><div class='add'>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0</div><div class='add'>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm0_dispdec</div><div class='add'>+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm1_dispdec</div><div class='add'>+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm2_dispdec</div><div class='add'>+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_dscrm3_dispdec</div><div class='add'>+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L</div><div class='add'>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_top_dispdec</div><div class='add'>+//OPP_TOP_CLK_CONTROL</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS__SHIFT                                                          0x18</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L</div><div class='add'>+#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS_MASK                                                            0x01000000L</div><div class='add'>+//OPP_ABM_CONTROL</div><div class='add'>+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0</div><div class='add'>+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_opp_opp_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm0_dispdec</div><div class='add'>+//ODM0_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM0_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM0_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM0_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM0_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM0_OPTC_WIDTH_CONTROL2</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT                                              0x0</div><div class='add'>+#define ODM0_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK                                                0x00001FFFL</div><div class='add'>+//ODM0_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM0_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM0_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm1_dispdec</div><div class='add'>+//ODM1_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM1_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM1_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM1_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM1_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM1_OPTC_WIDTH_CONTROL2</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT                                              0x0</div><div class='add'>+#define ODM1_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK                                                0x00001FFFL</div><div class='add'>+//ODM1_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM1_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM1_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm2_dispdec</div><div class='add'>+//ODM2_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM2_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM2_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM2_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM2_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM2_OPTC_WIDTH_CONTROL2</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT                                              0x0</div><div class='add'>+#define ODM2_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK                                                0x00001FFFL</div><div class='add'>+//ODM2_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM2_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM2_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_odm3_dispdec</div><div class='add'>+//ODM3_OPTC_INPUT_GLOBAL_CONTROL</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L</div><div class='add'>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L</div><div class='add'>+//ODM3_OPTC_DATA_SOURCE_SELECT</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L</div><div class='add'>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L</div><div class='add'>+//ODM3_OPTC_DATA_FORMAT_CONTROL</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L</div><div class='add'>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L</div><div class='add'>+//ODM3_OPTC_BYTES_PER_PIXEL</div><div class='add'>+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0</div><div class='add'>+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL</div><div class='add'>+//ODM3_OPTC_WIDTH_CONTROL</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L</div><div class='add'>+//ODM3_OPTC_WIDTH_CONTROL2</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT                                              0x0</div><div class='add'>+#define ODM3_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK                                                0x00001FFFL</div><div class='add'>+//ODM3_OPTC_INPUT_CLOCK_CONTROL</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L</div><div class='add'>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L</div><div class='add'>+//ODM3_OPTC_MEMORY_CONFIG</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL</div><div class='add'>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L</div><div class='add'>+//ODM3_OPTC_INPUT_SPARE_REGISTER</div><div class='add'>+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0</div><div class='add'>+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg0_dispdec</div><div class='add'>+//OTG0_OTG_H_TOTAL</div><div class='add'>+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG0_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_H_SYNC_A</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG0_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG0_OTG_V_TOTAL</div><div class='add'>+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG0_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG0_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG0_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG0_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_V_SYNC_A</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG0_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG0_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG0_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG0_OTG_FLOW_CONTROL</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L</div><div class='add'>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L</div><div class='add'>+//OTG0_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG0_OTG_CONTROL</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG0_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG0_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG0_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG0_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG0_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG0_OTG_STATUS</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG0_OTG_STATUS_POSITION</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG0_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG0_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG0_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG0_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG0_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG0_OTG_COUNT_RESET</div><div class='add'>+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG0_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG0_OTG_STEREO_STATUS</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG0_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG0_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG0_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG0_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG0_OTG_MASTER_EN</div><div class='add'>+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG0_OTG_CRC_CNTL</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG0_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG0_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG0_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG0_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG0_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG0_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG0_OTG_VREADY_PARAM</div><div class='add'>+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG0_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG0_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG0_OTG_GSL_CONTROL</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG0_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG0_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG0_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG0_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_MANUAL_FLOW_CONTROL</div><div class='add'>+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG0_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG0_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG0_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG0_OTG_DRR_CONTROL</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG0_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG0_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG0_OTG_PSTATE_REGISTER</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT                                                    0x10</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT                                                          0x14</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT                                           0x18</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK                                               0x00007FFFL</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK                                                      0x00010000L</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK                                                            0x00100000L</div><div class='add'>+#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK                                             0xFF000000L</div><div class='add'>+//OTG0_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg1_dispdec</div><div class='add'>+//OTG1_OTG_H_TOTAL</div><div class='add'>+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG1_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_H_SYNC_A</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG1_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG1_OTG_V_TOTAL</div><div class='add'>+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG1_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG1_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG1_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG1_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_V_SYNC_A</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG1_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG1_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG1_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG1_OTG_FLOW_CONTROL</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L</div><div class='add'>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L</div><div class='add'>+//OTG1_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG1_OTG_CONTROL</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG1_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG1_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG1_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG1_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG1_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG1_OTG_STATUS</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG1_OTG_STATUS_POSITION</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG1_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG1_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG1_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG1_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG1_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG1_OTG_COUNT_RESET</div><div class='add'>+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG1_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG1_OTG_STEREO_STATUS</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG1_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG1_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG1_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG1_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG1_OTG_MASTER_EN</div><div class='add'>+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG1_OTG_CRC_CNTL</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG1_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG1_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG1_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG1_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG1_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG1_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG1_OTG_VREADY_PARAM</div><div class='add'>+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG1_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG1_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG1_OTG_GSL_CONTROL</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG1_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG1_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG1_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG1_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_MANUAL_FLOW_CONTROL</div><div class='add'>+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG1_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG1_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG1_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG1_OTG_DRR_CONTROL</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG1_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG1_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG1_OTG_PSTATE_REGISTER</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT                                                    0x10</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT                                                          0x14</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT                                           0x18</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK                                               0x00007FFFL</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK                                                      0x00010000L</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK                                                            0x00100000L</div><div class='add'>+#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK                                             0xFF000000L</div><div class='add'>+//OTG1_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg2_dispdec</div><div class='add'>+//OTG2_OTG_H_TOTAL</div><div class='add'>+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG2_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_H_SYNC_A</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG2_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG2_OTG_V_TOTAL</div><div class='add'>+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG2_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG2_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG2_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG2_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_V_SYNC_A</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG2_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG2_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG2_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG2_OTG_FLOW_CONTROL</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L</div><div class='add'>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L</div><div class='add'>+//OTG2_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG2_OTG_CONTROL</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG2_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG2_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG2_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG2_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG2_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG2_OTG_STATUS</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG2_OTG_STATUS_POSITION</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG2_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG2_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG2_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG2_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG2_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG2_OTG_COUNT_RESET</div><div class='add'>+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG2_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG2_OTG_STEREO_STATUS</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG2_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG2_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG2_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG2_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG2_OTG_MASTER_EN</div><div class='add'>+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG2_OTG_CRC_CNTL</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG2_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG2_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG2_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG2_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG2_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG2_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG2_OTG_VREADY_PARAM</div><div class='add'>+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG2_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG2_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG2_OTG_GSL_CONTROL</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG2_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG2_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG2_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG2_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_MANUAL_FLOW_CONTROL</div><div class='add'>+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG2_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG2_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG2_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG2_OTG_DRR_CONTROL</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG2_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG2_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG2_OTG_PSTATE_REGISTER</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT                                                    0x10</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT                                                          0x14</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT                                           0x18</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK                                               0x00007FFFL</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK                                                      0x00010000L</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK                                                            0x00100000L</div><div class='add'>+#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK                                             0xFF000000L</div><div class='add'>+//OTG2_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_otg3_dispdec</div><div class='add'>+//OTG3_OTG_H_TOTAL</div><div class='add'>+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG3_OTG_H_BLANK_START_END</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_H_SYNC_A</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_H_SYNC_A_CNTL</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L</div><div class='add'>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L</div><div class='add'>+//OTG3_OTG_H_TIMING_CNTL</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT                                           0x8</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK                                             0x00000100L</div><div class='add'>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK                                               0x00030000L</div><div class='add'>+//OTG3_OTG_V_TOTAL</div><div class='add'>+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_MIN</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_MAX</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_MID</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_CONTROL</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG3_OTG_V_COUNT_STOP_CONTROL</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK                                                  0x00007FFFL</div><div class='add'>+//OTG3_OTG_V_COUNT_STOP_CONTROL2</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT                                         0x0</div><div class='add'>+#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK                                           0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_V_TOTAL_INT_STATUS</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L</div><div class='add'>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L</div><div class='add'>+//OTG3_OTG_VSYNC_NOM_INT_STATUS</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L</div><div class='add'>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L</div><div class='add'>+//OTG3_OTG_V_BLANK_START_END</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_V_SYNC_A</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL</div><div class='add'>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_V_SYNC_A_CNTL</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L</div><div class='add'>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L</div><div class='add'>+//OTG3_OTG_TRIGA_CNTL</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG3_OTG_TRIGA_MANUAL_TRIG</div><div class='add'>+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_TRIGB_CNTL</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L</div><div class='add'>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L</div><div class='add'>+//OTG3_OTG_TRIGB_MANUAL_TRIG</div><div class='add'>+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_FORCE_COUNT_NOW_CNTL</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L</div><div class='add'>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L</div><div class='add'>+//OTG3_OTG_FLOW_CONTROL</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L</div><div class='add'>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L</div><div class='add'>+//OTG3_OTG_STEREO_FORCE_NEXT_EYE</div><div class='add'>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L</div><div class='add'>+//OTG3_OTG_CONTROL</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L</div><div class='add'>+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L</div><div class='add'>+//OTG3_OTG_DLPC_CONTROL</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT                                              0x10</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT                                               0x1f</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK                                                           0x00000001L</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK                                                0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK                                                 0x80000000L</div><div class='add'>+//OTG3_OTG_INTERLACE_CONTROL</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L</div><div class='add'>+//OTG3_OTG_INTERLACE_STATUS</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L</div><div class='add'>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L</div><div class='add'>+//OTG3_OTG_PIXEL_DATA_READBACK0</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L</div><div class='add'>+//OTG3_OTG_PIXEL_DATA_READBACK1</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0</div><div class='add'>+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL</div><div class='add'>+//OTG3_OTG_STATUS</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L</div><div class='add'>+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L</div><div class='add'>+//OTG3_OTG_STATUS_POSITION</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT                                                 0xf</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK                                                   0x00008000L</div><div class='add'>+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L</div><div class='add'>+//OTG3_OTG_LONG_VBLANK_STATUS</div><div class='add'>+#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK                                              0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_NOM_VERT_POSITION</div><div class='add'>+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0</div><div class='add'>+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL</div><div class='add'>+//OTG3_OTG_STATUS_FRAME_COUNT</div><div class='add'>+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL</div><div class='add'>+//OTG3_OTG_STATUS_VF_COUNT</div><div class='add'>+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG3_OTG_STATUS_HV_COUNT</div><div class='add'>+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL</div><div class='add'>+//OTG3_OTG_COUNT_CONTROL</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL</div><div class='add'>+//OTG3_OTG_COUNT_RESET</div><div class='add'>+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0</div><div class='add'>+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L</div><div class='add'>+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE</div><div class='add'>+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0</div><div class='add'>+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L</div><div class='add'>+//OTG3_OTG_VERT_SYNC_CONTROL</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L</div><div class='add'>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L</div><div class='add'>+//OTG3_OTG_STEREO_STATUS</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L</div><div class='add'>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L</div><div class='add'>+//OTG3_OTG_STEREO_CONTROL</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L</div><div class='add'>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_STATUS</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_CONTROL</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_POSITION</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_SNAPSHOT_FRAME</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL</div><div class='add'>+//OTG3_OTG_INTERRUPT_CONTROL</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L</div><div class='add'>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L</div><div class='add'>+//OTG3_OTG_UPDATE_LOCK</div><div class='add'>+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0</div><div class='add'>+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L</div><div class='add'>+//OTG3_OTG_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L</div><div class='add'>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L</div><div class='add'>+//OTG3_OTG_MASTER_EN</div><div class='add'>+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL</div><div class='add'>+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L</div><div class='add'>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L</div><div class='add'>+//OTG3_OTG_CRC_CNTL</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT                                                        0x1</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT                                                           0xa</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK                                                          0x00000002L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK                                                             0x00000400L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L</div><div class='add'>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC2_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC2_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC3_DATA_RG</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC3_DATA_B</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT                    0x0</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT                      0x10</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_STATIC_SCREEN_CONTROL</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L</div><div class='add'>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L</div><div class='add'>+//OTG3_OTG_3D_STRUCTURE_CONTROL</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L</div><div class='add'>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L</div><div class='add'>+//OTG3_OTG_GSL_VSYNC_GAP</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L</div><div class='add'>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L</div><div class='add'>+//OTG3_OTG_MASTER_UPDATE_MODE</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L</div><div class='add'>+//OTG3_OTG_CLOCK_CONTROL</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L</div><div class='add'>+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L</div><div class='add'>+//OTG3_OTG_VSTARTUP_PARAM</div><div class='add'>+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0</div><div class='add'>+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL</div><div class='add'>+//OTG3_OTG_VUPDATE_PARAM</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L</div><div class='add'>+//OTG3_OTG_VREADY_PARAM</div><div class='add'>+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0</div><div class='add'>+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL</div><div class='add'>+//OTG3_OTG_GLOBAL_SYNC_STATUS</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L</div><div class='add'>+//OTG3_OTG_MASTER_UPDATE_LOCK</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L</div><div class='add'>+//OTG3_OTG_GSL_CONTROL</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L</div><div class='add'>+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L</div><div class='add'>+//OTG3_OTG_GSL_WINDOW_X</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_GSL_WINDOW_Y</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L</div><div class='add'>+//OTG3_OTG_VUPDATE_KEEPOUT</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L</div><div class='add'>+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL1</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL2</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL3</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L</div><div class='add'>+//OTG3_OTG_GLOBAL_CONTROL4</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L</div><div class='add'>+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L</div><div class='add'>+//OTG3_OTG_TRIG_MANUAL_CONTROL</div><div class='add'>+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_MANUAL_FLOW_CONTROL</div><div class='add'>+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L</div><div class='add'>+//OTG3_OTG_DRR_TIMING_INT_STATUS</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L</div><div class='add'>+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L</div><div class='add'>+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L</div><div class='add'>+//OTG3_OTG_DRR_V_TOTAL_CHANGE</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0</div><div class='add'>+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL</div><div class='add'>+//OTG3_OTG_DRR_TRIGGER_WINDOW</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL</div><div class='add'>+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L</div><div class='add'>+//OTG3_OTG_DRR_CONTROL</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L</div><div class='add'>+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L</div><div class='add'>+//OTG3_OTG_DRR_CONTOL2</div><div class='add'>+#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK                                               0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_M_CONST_DTO0</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_M_CONST_DTO1</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_REQUEST_CONTROL</div><div class='add'>+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0</div><div class='add'>+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L</div><div class='add'>+//OTG3_OTG_PIPE_UPDATE_STATUS</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L</div><div class='add'>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L</div><div class='add'>+//OTG3_OTG_PSTATE_REGISTER</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT                                                    0x10</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT                                                          0x14</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT                                           0x18</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK                                               0x00007FFFL</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK                                                      0x00010000L</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK                                                            0x00100000L</div><div class='add'>+#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK                                             0xFF000000L</div><div class='add'>+//OTG3_OTG_SPARE_REGISTER</div><div class='add'>+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0</div><div class='add'>+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_optc_misc_dispdec</div><div class='add'>+//GSL_SOURCE_SELECT</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L</div><div class='add'>+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L</div><div class='add'>+//OPTC_DLPC_CONTROL</div><div class='add'>+#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX__SHIFT                                                      0x0</div><div class='add'>+#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX_MASK                                                        0x00000007L</div><div class='add'>+//OPTC_CLOCK_CONTROL</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT                                                          0xf</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L</div><div class='add'>+#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK                                                            0x00008000L</div><div class='add'>+//ODM_MEM_PWR_CTRL</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L</div><div class='add'>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L</div><div class='add'>+//ODM_MEM_PWR_CTRL2</div><div class='add'>+//ODM_MEM_PWR_CTRL3</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L</div><div class='add'>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL</div><div class='add'>+//ODM_MEM_PWR_STATUS</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L</div><div class='add'>+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L</div><div class='add'>+//OPTC_MISC_SPARE_REGISTER</div><div class='add'>+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0</div><div class='add'>+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_optc_optc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp0_dispdec</div><div class='add'>+//DP0_DP_LINK_CNTL</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP0_DP_PIXEL_FORMAT</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT                                                 0x4</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                                              0x8</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT                                                   0x10</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                                         0x00000001L</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK                                                   0x00000030L</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                                                0x00000700L</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK                                                     0x00010000L</div><div class='add'>+//DP0_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP0_DP_CONFIG</div><div class='add'>+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP0_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP0_DP_STEER_FIFO</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x1</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT                                                    0x2</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000002L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK                                                      0x00000004L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+//DP0_DP_MSA_MISC</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP0_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP0_DP_VID_TIMING</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT                                                           0xe</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK                                                             0x0000C000L</div><div class='add'>+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP0_DP_VID_N</div><div class='add'>+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP0_DP_VID_M</div><div class='add'>+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP0_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP0_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP0_DP_VID_MSA_VBID</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP0_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP0_DP_DPHY_CNTL</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP0_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP0_DP_DPHY_SYM0</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP0_DP_DPHY_SYM1</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP0_DP_DPHY_SYM2</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP0_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP0_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP0_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP0_DP_DPHY_CRC_EN</div><div class='add'>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L</div><div class='add'>+//DP0_DP_DPHY_CRC_CNTL</div><div class='add'>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4</div><div class='add'>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L</div><div class='add'>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L</div><div class='add'>+//DP0_DP_DPHY_CRC_RESULT</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L</div><div class='add'>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L</div><div class='add'>+//DP0_DP_DPHY_CRC_MST_CNTL</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP0_DP_DPHY_CRC_MST_STATUS</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L</div><div class='add'>+//DP0_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP0_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP0_DP_TU_CNTL</div><div class='add'>+#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT                                                            0x8</div><div class='add'>+#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT                                                             0xc</div><div class='add'>+#define DP0_DP_TU_CNTL__DP_TU_SIZE__SHIFT                                                                     0x18</div><div class='add'>+#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK                                                              0x00000100L</div><div class='add'>+#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK                                                               0x00001000L</div><div class='add'>+#define DP0_DP_TU_CNTL__DP_TU_SIZE_MASK                                                                       0x3F000000L</div><div class='add'>+//DP0_DP_PIXEL_FORMAT_DB_CNTL</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT                                           0x4</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK                                              0x00000001L</div><div class='add'>+#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK                                             0x00000010L</div><div class='add'>+//DP0_DP_CP_LINK_VERIFICATION_PATTERN</div><div class='add'>+#define DP0_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN__SHIFT                           0x0</div><div class='add'>+#define DP0_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN_MASK                             0x0000FFFFL</div><div class='add'>+//DP0_DP_SEC_CNTL</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP0_DP_SEC_CNTL1</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING1</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING2</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING3</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_FRAMING4</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP0_DP_SEC_AUD_N</div><div class='add'>+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_AUD_M</div><div class='add'>+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP0_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP0_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP0_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP0_DP_CP_MSE_STATUS</div><div class='add'>+#define DP0_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT_MASK                                                      0x00000001L</div><div class='add'>+//DP0_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP0_DP_MSE_SAT0</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT1</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT2</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP0_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP0_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP0_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP0_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP0_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP0_DP_DPIA_SPARE</div><div class='add'>+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP0_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP0_DP_HBLANK_CONTROL</div><div class='add'>+#define DP0_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                                          0x0</div><div class='add'>+#define DP0_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                                            0x0000FFFFL</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP0_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_MSO_CNTL</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP0_DP_MSO_CNTL1</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP0_DP_STEER_FIFO_CNTL</div><div class='add'>+#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT                       0x8</div><div class='add'>+#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                        0x10</div><div class='add'>+#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK                         0x00000100L</div><div class='add'>+#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK                                          0x00030000L</div><div class='add'>+//DP0_DP_SEC_CNTL2</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP0_DP_SEC_CNTL3</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_CNTL4</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_CNTL5</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_CNTL6</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP0_DP_SEC_CNTL7</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP0_DP_DB_CNTL</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP0_DP_MSA_VBID_MISC</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP0_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP0_DP_ALPM_CNTL</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT                                                       0xf</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK                                                         0x00008000L</div><div class='add'>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP8_CNTL</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP9_CNTL</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP10_CNTL</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP11_CNTL</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP0_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP0_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP0_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP0_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP0_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP0_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP0_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+//DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT           0x0</div><div class='add'>+#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT  0x8</div><div class='add'>+#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK             0x00000001L</div><div class='add'>+#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK  0x00000100L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_dispdec</div><div class='add'>+//DIG0_DIG_FE_CNTL</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG0_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG0_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG0_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG0_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG0_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG0_DIG_TEST_PATTERN</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG0_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG0_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                           0x8</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK                                             0x00000300L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG0_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG0_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_CONTROL</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG0_HDMI_STATUS</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG0_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG0_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG0_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG0_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG0_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG0_HDMI_GC</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG0_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG0_HDMI_DB_CONTROL</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG0_HDMI_ACR_32_0</div><div class='add'>+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_32_1</div><div class='add'>+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG0_HDMI_ACR_44_0</div><div class='add'>+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_44_1</div><div class='add'>+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG0_HDMI_ACR_48_0</div><div class='add'>+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_48_1</div><div class='add'>+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG0_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG0_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG0_AFMT_CNTL</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG0_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT                                                          0x6</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON__SHIFT                                            0xc</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK                                                            0x00000040L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON_MASK                                              0x00001000L</div><div class='add'>+#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG0_DIG_BE_CNTL</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG0_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG0_HDCP_INT_CONTROL</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT__SHIFT                                                   0x0</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK__SHIFT                                                   0x1</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK__SHIFT                                                  0x2</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT__SHIFT                                                      0x4</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK__SHIFT                                                      0x5</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK__SHIFT                                                     0x6</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK__SHIFT                                                 0x7</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT__SHIFT                                                   0x8</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK__SHIFT                                                   0x9</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK__SHIFT                                                  0xa</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT__SHIFT                                                  0xc</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK__SHIFT                                                  0xd</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK__SHIFT                                                 0xe</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT_MASK                                                     0x00000001L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK_MASK                                                     0x00000002L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK_MASK                                                    0x00000004L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT_MASK                                                        0x00000010L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK_MASK                                                        0x00000020L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK_MASK                                                       0x00000040L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK_MASK                                                   0x00000080L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT_MASK                                                     0x00000100L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK_MASK                                                     0x00000200L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK_MASK                                                    0x00000400L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT_MASK                                                    0x00001000L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK_MASK                                                    0x00002000L</div><div class='add'>+#define DIG0_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK_MASK                                                   0x00004000L</div><div class='add'>+//DIG0_HDCP_LINK0_STATUS</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES__SHIFT                                                   0x14</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES_MASK                                                     0x00100000L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG0_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG0_HDCP_I2C_CONTROL_0</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE__SHIFT                                                      0x0</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET__SHIFT                                                   0x2</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT__SHIFT                                                   0x8</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE_MASK                                                        0x00000001L</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET_MASK                                                     0x00000004L</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT_MASK                                                     0x00000700L</div><div class='add'>+//DIG0_HDCP_I2C_CONTROL_1</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK__SHIFT                                                   0x0</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE__SHIFT                                                   0x1</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE__SHIFT                                               0x8</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT__SHIFT                                                  0x14</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY__SHIFT                                                  0x18</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK_MASK                                                     0x00000001L</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE_MASK                                                     0x00000002L</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE_MASK                                                 0x00000100L</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT_MASK                                                    0x00F00000L</div><div class='add'>+#define DIG0_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY_MASK                                                    0xFF000000L</div><div class='add'>+//DIG0_HDCP_I2C_STATUS</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED__SHIFT                                                   0x2</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ__SHIFT                                                        0x4</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG__SHIFT                                                    0x5</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1__SHIFT                                             0x6</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0__SHIFT                                             0x8</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE__SHIFT                                                       0xa</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_ABORTED__SHIFT                                                         0xc</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT__SHIFT                                                         0xd</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_NACK0__SHIFT                                                           0xe</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_NACK1__SHIFT                                                           0xf</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_FAILED__SHIFT                                                          0x10</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_RETRIES__SHIFT                                                         0x14</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ__SHIFT                                              0x18</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED_MASK                                                     0x00000004L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_MASK                                                          0x00000010L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG_MASK                                                      0x00000020L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1_MASK                                               0x000000C0L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0_MASK                                               0x00000300L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE_MASK                                                         0x00000400L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_ABORTED_MASK                                                           0x00001000L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT_MASK                                                           0x00002000L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_NACK0_MASK                                                             0x00004000L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_NACK1_MASK                                                             0x00008000L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_FAILED_MASK                                                            0x00010000L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_I2C_RETRIES_MASK                                                           0x00F00000L</div><div class='add'>+#define DIG0_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ_MASK                                                0xFF000000L</div><div class='add'>+//DIG0_HDCP_LINK1_STATUS</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG0_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG0_HDCP_RESET</div><div class='add'>+#define DIG0_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE__SHIFT                                                     0x0</div><div class='add'>+#define DIG0_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE__SHIFT                                                     0x1</div><div class='add'>+#define DIG0_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE_MASK                                                       0x00000001L</div><div class='add'>+#define DIG0_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE_MASK                                                       0x00000002L</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA1</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1_MASK                                               0x000000FFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA2_0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI__SHIFT                                               0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI_MASK                                                 0x0000FFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA2_1</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ__SHIFT                                               0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ_MASK                                                 0x000000FFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA3</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA4</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO__SHIFT                                              0x8</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1_MASK                                               0x000000FFL</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO_MASK                                                0x0000FF00L</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA5</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0__SHIFT                                               0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA6</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1__SHIFT                                               0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA7</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0__SHIFT                                                     0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA8</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1__SHIFT                                                     0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA9</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2__SHIFT                                                     0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA10</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA11</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA12</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS__SHIFT                                                   0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS__SHIFT                                                 0x8</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS_MASK                                                     0x000000FFL</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS_MASK                                                   0x00FFFF00L</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA13</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA14</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1_MASK                                              0x000000FFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA15_0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI__SHIFT                                              0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI_MASK                                                0x0000FFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA15_1</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ__SHIFT                                              0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ_MASK                                                0x000000FFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA16</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA17</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO__SHIFT                                             0x8</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1_MASK                                              0x000000FFL</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO_MASK                                               0x0000FF00L</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA18</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0__SHIFT                                              0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA19</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1__SHIFT                                              0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG0_HDCP_RECV_PORT_LOCAL_DATA20</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO__SHIFT                                                0x0</div><div class='add'>+#define DIG0_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO_MASK                                                  0x0000FFFFL</div><div class='add'>+//DIG0_HDCP_DP_STATUS</div><div class='add'>+#define DIG0_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK__SHIFT                                                0x1</div><div class='add'>+#define DIG0_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_MASK                                                      0x00000001L</div><div class='add'>+#define DIG0_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK_MASK                                                  0x00000002L</div><div class='add'>+//DIG0_HDCP_CLK_CNTL</div><div class='add'>+#define DIG0_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE__SHIFT                                                        0x1</div><div class='add'>+#define DIG0_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE__SHIFT                                                         0x2</div><div class='add'>+#define DIG0_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE_MASK                                                          0x00000002L</div><div class='add'>+#define DIG0_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE_MASK                                                           0x00000004L</div><div class='add'>+//DIG0_HDCP_ENGINE_SELECT</div><div class='add'>+#define DIG0_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT__SHIFT                                                    0x0</div><div class='add'>+#define DIG0_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT_MASK                                                      0x00000001L</div><div class='add'>+//DIG0_TMDS_CNTL</div><div class='add'>+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG0_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG0_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG0_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG0_TMDS_CTL_BITS</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG0_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG0_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG0_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG0_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG0_DIG_VERSION</div><div class='add'>+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp1_dispdec</div><div class='add'>+//DP1_DP_LINK_CNTL</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP1_DP_PIXEL_FORMAT</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT                                                 0x4</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                                              0x8</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT                                                   0x10</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                                         0x00000001L</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK                                                   0x00000030L</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                                                0x00000700L</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK                                                     0x00010000L</div><div class='add'>+//DP1_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP1_DP_CONFIG</div><div class='add'>+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP1_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP1_DP_STEER_FIFO</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x1</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT                                                    0x2</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000002L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK                                                      0x00000004L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+//DP1_DP_MSA_MISC</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP1_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP1_DP_VID_TIMING</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT                                                           0xe</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK                                                             0x0000C000L</div><div class='add'>+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP1_DP_VID_N</div><div class='add'>+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP1_DP_VID_M</div><div class='add'>+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP1_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP1_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP1_DP_VID_MSA_VBID</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP1_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP1_DP_DPHY_CNTL</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP1_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP1_DP_DPHY_SYM0</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP1_DP_DPHY_SYM1</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP1_DP_DPHY_SYM2</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP1_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP1_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP1_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP1_DP_DPHY_CRC_EN</div><div class='add'>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L</div><div class='add'>+//DP1_DP_DPHY_CRC_CNTL</div><div class='add'>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4</div><div class='add'>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L</div><div class='add'>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L</div><div class='add'>+//DP1_DP_DPHY_CRC_RESULT</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L</div><div class='add'>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L</div><div class='add'>+//DP1_DP_DPHY_CRC_MST_CNTL</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP1_DP_DPHY_CRC_MST_STATUS</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L</div><div class='add'>+//DP1_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP1_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP1_DP_TU_CNTL</div><div class='add'>+#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT                                                            0x8</div><div class='add'>+#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT                                                             0xc</div><div class='add'>+#define DP1_DP_TU_CNTL__DP_TU_SIZE__SHIFT                                                                     0x18</div><div class='add'>+#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK                                                              0x00000100L</div><div class='add'>+#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK                                                               0x00001000L</div><div class='add'>+#define DP1_DP_TU_CNTL__DP_TU_SIZE_MASK                                                                       0x3F000000L</div><div class='add'>+//DP1_DP_PIXEL_FORMAT_DB_CNTL</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT                                           0x4</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK                                              0x00000001L</div><div class='add'>+#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK                                             0x00000010L</div><div class='add'>+//DP1_DP_CP_LINK_VERIFICATION_PATTERN</div><div class='add'>+#define DP1_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN__SHIFT                           0x0</div><div class='add'>+#define DP1_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN_MASK                             0x0000FFFFL</div><div class='add'>+//DP1_DP_SEC_CNTL</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP1_DP_SEC_CNTL1</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING1</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING2</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING3</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_FRAMING4</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP1_DP_SEC_AUD_N</div><div class='add'>+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_AUD_M</div><div class='add'>+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP1_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP1_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP1_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP1_DP_CP_MSE_STATUS</div><div class='add'>+#define DP1_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT_MASK                                                      0x00000001L</div><div class='add'>+//DP1_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP1_DP_MSE_SAT0</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT1</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT2</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP1_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP1_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP1_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP1_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP1_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP1_DP_DPIA_SPARE</div><div class='add'>+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP1_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP1_DP_HBLANK_CONTROL</div><div class='add'>+#define DP1_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                                          0x0</div><div class='add'>+#define DP1_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                                            0x0000FFFFL</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP1_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_MSO_CNTL</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP1_DP_MSO_CNTL1</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP1_DP_STEER_FIFO_CNTL</div><div class='add'>+#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT                       0x8</div><div class='add'>+#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                        0x10</div><div class='add'>+#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK                         0x00000100L</div><div class='add'>+#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK                                          0x00030000L</div><div class='add'>+//DP1_DP_SEC_CNTL2</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP1_DP_SEC_CNTL3</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_CNTL4</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_CNTL5</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_CNTL6</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP1_DP_SEC_CNTL7</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP1_DP_DB_CNTL</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP1_DP_MSA_VBID_MISC</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP1_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP1_DP_ALPM_CNTL</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT                                                       0xf</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK                                                         0x00008000L</div><div class='add'>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP8_CNTL</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP9_CNTL</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP10_CNTL</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP11_CNTL</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP1_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP1_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP1_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP1_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP1_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP1_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP1_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+//DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT           0x0</div><div class='add'>+#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT  0x8</div><div class='add'>+#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK             0x00000001L</div><div class='add'>+#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK  0x00000100L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_dispdec</div><div class='add'>+//DIG1_DIG_FE_CNTL</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG1_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG1_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG1_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG1_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG1_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG1_DIG_TEST_PATTERN</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG1_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG1_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                           0x8</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK                                             0x00000300L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG1_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG1_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_CONTROL</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG1_HDMI_STATUS</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG1_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG1_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG1_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG1_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG1_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG1_HDMI_GC</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG1_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG1_HDMI_DB_CONTROL</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG1_HDMI_ACR_32_0</div><div class='add'>+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_32_1</div><div class='add'>+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG1_HDMI_ACR_44_0</div><div class='add'>+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_44_1</div><div class='add'>+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG1_HDMI_ACR_48_0</div><div class='add'>+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_48_1</div><div class='add'>+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG1_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG1_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG1_AFMT_CNTL</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG1_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT                                                          0x6</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK                                                            0x00000040L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG1_DIG_BE_CNTL</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG1_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG1_HDCP_INT_CONTROL</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT__SHIFT                                                   0x0</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK__SHIFT                                                   0x1</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK__SHIFT                                                  0x2</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT__SHIFT                                                      0x4</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK__SHIFT                                                      0x5</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK__SHIFT                                                     0x6</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK__SHIFT                                                 0x7</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT__SHIFT                                                   0x8</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK__SHIFT                                                   0x9</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK__SHIFT                                                  0xa</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT__SHIFT                                                  0xc</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK__SHIFT                                                  0xd</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK__SHIFT                                                 0xe</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT_MASK                                                     0x00000001L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK_MASK                                                     0x00000002L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK_MASK                                                    0x00000004L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT_MASK                                                        0x00000010L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK_MASK                                                        0x00000020L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK_MASK                                                       0x00000040L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK_MASK                                                   0x00000080L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT_MASK                                                     0x00000100L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK_MASK                                                     0x00000200L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK_MASK                                                    0x00000400L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT_MASK                                                    0x00001000L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK_MASK                                                    0x00002000L</div><div class='add'>+#define DIG1_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK_MASK                                                   0x00004000L</div><div class='add'>+//DIG1_HDCP_LINK0_STATUS</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES__SHIFT                                                   0x14</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES_MASK                                                     0x00100000L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG1_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG1_HDCP_I2C_CONTROL_0</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE__SHIFT                                                      0x0</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET__SHIFT                                                   0x2</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT__SHIFT                                                   0x8</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE_MASK                                                        0x00000001L</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET_MASK                                                     0x00000004L</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT_MASK                                                     0x00000700L</div><div class='add'>+//DIG1_HDCP_I2C_CONTROL_1</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK__SHIFT                                                   0x0</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE__SHIFT                                                   0x1</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE__SHIFT                                               0x8</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT__SHIFT                                                  0x14</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY__SHIFT                                                  0x18</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK_MASK                                                     0x00000001L</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE_MASK                                                     0x00000002L</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE_MASK                                                 0x00000100L</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT_MASK                                                    0x00F00000L</div><div class='add'>+#define DIG1_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY_MASK                                                    0xFF000000L</div><div class='add'>+//DIG1_HDCP_I2C_STATUS</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED__SHIFT                                                   0x2</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ__SHIFT                                                        0x4</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG__SHIFT                                                    0x5</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1__SHIFT                                             0x6</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0__SHIFT                                             0x8</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE__SHIFT                                                       0xa</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_ABORTED__SHIFT                                                         0xc</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT__SHIFT                                                         0xd</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_NACK0__SHIFT                                                           0xe</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_NACK1__SHIFT                                                           0xf</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_FAILED__SHIFT                                                          0x10</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_RETRIES__SHIFT                                                         0x14</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ__SHIFT                                              0x18</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED_MASK                                                     0x00000004L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_MASK                                                          0x00000010L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG_MASK                                                      0x00000020L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1_MASK                                               0x000000C0L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0_MASK                                               0x00000300L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE_MASK                                                         0x00000400L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_ABORTED_MASK                                                           0x00001000L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT_MASK                                                           0x00002000L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_NACK0_MASK                                                             0x00004000L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_NACK1_MASK                                                             0x00008000L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_FAILED_MASK                                                            0x00010000L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_I2C_RETRIES_MASK                                                           0x00F00000L</div><div class='add'>+#define DIG1_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ_MASK                                                0xFF000000L</div><div class='add'>+//DIG1_HDCP_LINK1_STATUS</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG1_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG1_HDCP_RESET</div><div class='add'>+#define DIG1_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE__SHIFT                                                     0x0</div><div class='add'>+#define DIG1_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE__SHIFT                                                     0x1</div><div class='add'>+#define DIG1_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE_MASK                                                       0x00000001L</div><div class='add'>+#define DIG1_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE_MASK                                                       0x00000002L</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA1</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1_MASK                                               0x000000FFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA2_0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI__SHIFT                                               0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI_MASK                                                 0x0000FFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA2_1</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ__SHIFT                                               0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ_MASK                                                 0x000000FFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA3</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA4</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO__SHIFT                                              0x8</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1_MASK                                               0x000000FFL</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO_MASK                                                0x0000FF00L</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA5</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0__SHIFT                                               0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA6</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1__SHIFT                                               0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA7</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0__SHIFT                                                     0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA8</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1__SHIFT                                                     0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA9</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2__SHIFT                                                     0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA10</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA11</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA12</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS__SHIFT                                                   0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS__SHIFT                                                 0x8</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS_MASK                                                     0x000000FFL</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS_MASK                                                   0x00FFFF00L</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA13</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA14</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1_MASK                                              0x000000FFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA15_0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI__SHIFT                                              0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI_MASK                                                0x0000FFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA15_1</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ__SHIFT                                              0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ_MASK                                                0x000000FFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA16</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA17</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO__SHIFT                                             0x8</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1_MASK                                              0x000000FFL</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO_MASK                                               0x0000FF00L</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA18</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0__SHIFT                                              0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA19</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1__SHIFT                                              0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG1_HDCP_RECV_PORT_LOCAL_DATA20</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO__SHIFT                                                0x0</div><div class='add'>+#define DIG1_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO_MASK                                                  0x0000FFFFL</div><div class='add'>+//DIG1_HDCP_DP_STATUS</div><div class='add'>+#define DIG1_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK__SHIFT                                                0x1</div><div class='add'>+#define DIG1_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_MASK                                                      0x00000001L</div><div class='add'>+#define DIG1_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK_MASK                                                  0x00000002L</div><div class='add'>+//DIG1_HDCP_CLK_CNTL</div><div class='add'>+#define DIG1_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE__SHIFT                                                        0x1</div><div class='add'>+#define DIG1_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE__SHIFT                                                         0x2</div><div class='add'>+#define DIG1_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE_MASK                                                          0x00000002L</div><div class='add'>+#define DIG1_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE_MASK                                                           0x00000004L</div><div class='add'>+//DIG1_HDCP_ENGINE_SELECT</div><div class='add'>+#define DIG1_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT__SHIFT                                                    0x0</div><div class='add'>+#define DIG1_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT_MASK                                                      0x00000001L</div><div class='add'>+//DIG1_TMDS_CNTL</div><div class='add'>+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG1_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG1_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG1_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG1_TMDS_CTL_BITS</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG1_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG1_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG1_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG1_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG1_DIG_VERSION</div><div class='add'>+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp2_dispdec</div><div class='add'>+//DP2_DP_LINK_CNTL</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP2_DP_PIXEL_FORMAT</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT                                                 0x4</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                                              0x8</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT                                                   0x10</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                                         0x00000001L</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK                                                   0x00000030L</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                                                0x00000700L</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK                                                     0x00010000L</div><div class='add'>+//DP2_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP2_DP_CONFIG</div><div class='add'>+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP2_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP2_DP_STEER_FIFO</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x1</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT                                                    0x2</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000002L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK                                                      0x00000004L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+//DP2_DP_MSA_MISC</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP2_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP2_DP_VID_TIMING</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT                                                           0xe</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK                                                             0x0000C000L</div><div class='add'>+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP2_DP_VID_N</div><div class='add'>+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP2_DP_VID_M</div><div class='add'>+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP2_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP2_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP2_DP_VID_MSA_VBID</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP2_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP2_DP_DPHY_CNTL</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP2_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP2_DP_DPHY_SYM0</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP2_DP_DPHY_SYM1</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP2_DP_DPHY_SYM2</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP2_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP2_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP2_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP2_DP_DPHY_CRC_EN</div><div class='add'>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L</div><div class='add'>+//DP2_DP_DPHY_CRC_CNTL</div><div class='add'>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4</div><div class='add'>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L</div><div class='add'>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L</div><div class='add'>+//DP2_DP_DPHY_CRC_RESULT</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L</div><div class='add'>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L</div><div class='add'>+//DP2_DP_DPHY_CRC_MST_CNTL</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP2_DP_DPHY_CRC_MST_STATUS</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L</div><div class='add'>+//DP2_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP2_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP2_DP_TU_CNTL</div><div class='add'>+#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT                                                            0x8</div><div class='add'>+#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT                                                             0xc</div><div class='add'>+#define DP2_DP_TU_CNTL__DP_TU_SIZE__SHIFT                                                                     0x18</div><div class='add'>+#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK                                                              0x00000100L</div><div class='add'>+#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK                                                               0x00001000L</div><div class='add'>+#define DP2_DP_TU_CNTL__DP_TU_SIZE_MASK                                                                       0x3F000000L</div><div class='add'>+//DP2_DP_PIXEL_FORMAT_DB_CNTL</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT                                           0x4</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK                                              0x00000001L</div><div class='add'>+#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK                                             0x00000010L</div><div class='add'>+//DP2_DP_CP_LINK_VERIFICATION_PATTERN</div><div class='add'>+#define DP2_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN__SHIFT                           0x0</div><div class='add'>+#define DP2_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN_MASK                             0x0000FFFFL</div><div class='add'>+//DP2_DP_SEC_CNTL</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP2_DP_SEC_CNTL1</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING1</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING2</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING3</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_FRAMING4</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP2_DP_SEC_AUD_N</div><div class='add'>+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_AUD_M</div><div class='add'>+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP2_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP2_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP2_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP2_DP_CP_MSE_STATUS</div><div class='add'>+#define DP2_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT_MASK                                                      0x00000001L</div><div class='add'>+//DP2_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP2_DP_MSE_SAT0</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT1</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT2</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP2_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP2_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP2_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP2_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP2_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP2_DP_DPIA_SPARE</div><div class='add'>+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP2_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP2_DP_HBLANK_CONTROL</div><div class='add'>+#define DP2_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                                          0x0</div><div class='add'>+#define DP2_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                                            0x0000FFFFL</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP2_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_MSO_CNTL</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP2_DP_MSO_CNTL1</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP2_DP_STEER_FIFO_CNTL</div><div class='add'>+#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT                       0x8</div><div class='add'>+#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                        0x10</div><div class='add'>+#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK                         0x00000100L</div><div class='add'>+#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK                                          0x00030000L</div><div class='add'>+//DP2_DP_SEC_CNTL2</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP2_DP_SEC_CNTL3</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_CNTL4</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_CNTL5</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_CNTL6</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP2_DP_SEC_CNTL7</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP2_DP_DB_CNTL</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP2_DP_MSA_VBID_MISC</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP2_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP2_DP_ALPM_CNTL</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT                                                       0xf</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK                                                         0x00008000L</div><div class='add'>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP8_CNTL</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP9_CNTL</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP10_CNTL</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP11_CNTL</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP2_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP2_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP2_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP2_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP2_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP2_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP2_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+//DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT           0x0</div><div class='add'>+#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT  0x8</div><div class='add'>+#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK             0x00000001L</div><div class='add'>+#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK  0x00000100L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_dispdec</div><div class='add'>+//DIG2_DIG_FE_CNTL</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG2_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG2_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG2_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG2_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG2_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG2_DIG_TEST_PATTERN</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG2_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG2_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                           0x8</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK                                             0x00000300L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG2_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG2_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_CONTROL</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG2_HDMI_STATUS</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG2_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG2_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG2_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG2_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG2_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG2_HDMI_GC</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG2_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG2_HDMI_DB_CONTROL</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG2_HDMI_ACR_32_0</div><div class='add'>+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_32_1</div><div class='add'>+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG2_HDMI_ACR_44_0</div><div class='add'>+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_44_1</div><div class='add'>+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG2_HDMI_ACR_48_0</div><div class='add'>+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_48_1</div><div class='add'>+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG2_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG2_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG2_AFMT_CNTL</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG2_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT                                                          0x6</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK                                                            0x00000040L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG2_DIG_BE_CNTL</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG2_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG2_HDCP_INT_CONTROL</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT__SHIFT                                                   0x0</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK__SHIFT                                                   0x1</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK__SHIFT                                                  0x2</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT__SHIFT                                                      0x4</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK__SHIFT                                                      0x5</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK__SHIFT                                                     0x6</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK__SHIFT                                                 0x7</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT__SHIFT                                                   0x8</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK__SHIFT                                                   0x9</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK__SHIFT                                                  0xa</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT__SHIFT                                                  0xc</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK__SHIFT                                                  0xd</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK__SHIFT                                                 0xe</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT_MASK                                                     0x00000001L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK_MASK                                                     0x00000002L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK_MASK                                                    0x00000004L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT_MASK                                                        0x00000010L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK_MASK                                                        0x00000020L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK_MASK                                                       0x00000040L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK_MASK                                                   0x00000080L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT_MASK                                                     0x00000100L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK_MASK                                                     0x00000200L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK_MASK                                                    0x00000400L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT_MASK                                                    0x00001000L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK_MASK                                                    0x00002000L</div><div class='add'>+#define DIG2_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK_MASK                                                   0x00004000L</div><div class='add'>+//DIG2_HDCP_LINK0_STATUS</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES__SHIFT                                                   0x14</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES_MASK                                                     0x00100000L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG2_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG2_HDCP_I2C_CONTROL_0</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE__SHIFT                                                      0x0</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET__SHIFT                                                   0x2</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT__SHIFT                                                   0x8</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE_MASK                                                        0x00000001L</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET_MASK                                                     0x00000004L</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT_MASK                                                     0x00000700L</div><div class='add'>+//DIG2_HDCP_I2C_CONTROL_1</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK__SHIFT                                                   0x0</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE__SHIFT                                                   0x1</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE__SHIFT                                               0x8</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT__SHIFT                                                  0x14</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY__SHIFT                                                  0x18</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK_MASK                                                     0x00000001L</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE_MASK                                                     0x00000002L</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE_MASK                                                 0x00000100L</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT_MASK                                                    0x00F00000L</div><div class='add'>+#define DIG2_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY_MASK                                                    0xFF000000L</div><div class='add'>+//DIG2_HDCP_I2C_STATUS</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED__SHIFT                                                   0x2</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ__SHIFT                                                        0x4</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG__SHIFT                                                    0x5</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1__SHIFT                                             0x6</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0__SHIFT                                             0x8</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE__SHIFT                                                       0xa</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_ABORTED__SHIFT                                                         0xc</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT__SHIFT                                                         0xd</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_NACK0__SHIFT                                                           0xe</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_NACK1__SHIFT                                                           0xf</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_FAILED__SHIFT                                                          0x10</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_RETRIES__SHIFT                                                         0x14</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ__SHIFT                                              0x18</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED_MASK                                                     0x00000004L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_MASK                                                          0x00000010L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG_MASK                                                      0x00000020L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1_MASK                                               0x000000C0L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0_MASK                                               0x00000300L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE_MASK                                                         0x00000400L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_ABORTED_MASK                                                           0x00001000L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT_MASK                                                           0x00002000L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_NACK0_MASK                                                             0x00004000L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_NACK1_MASK                                                             0x00008000L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_FAILED_MASK                                                            0x00010000L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_I2C_RETRIES_MASK                                                           0x00F00000L</div><div class='add'>+#define DIG2_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ_MASK                                                0xFF000000L</div><div class='add'>+//DIG2_HDCP_LINK1_STATUS</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG2_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG2_HDCP_RESET</div><div class='add'>+#define DIG2_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE__SHIFT                                                     0x0</div><div class='add'>+#define DIG2_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE__SHIFT                                                     0x1</div><div class='add'>+#define DIG2_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE_MASK                                                       0x00000001L</div><div class='add'>+#define DIG2_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE_MASK                                                       0x00000002L</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA1</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1_MASK                                               0x000000FFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA2_0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI__SHIFT                                               0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI_MASK                                                 0x0000FFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA2_1</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ__SHIFT                                               0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ_MASK                                                 0x000000FFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA3</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA4</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO__SHIFT                                              0x8</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1_MASK                                               0x000000FFL</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO_MASK                                                0x0000FF00L</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA5</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0__SHIFT                                               0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA6</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1__SHIFT                                               0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA7</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0__SHIFT                                                     0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA8</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1__SHIFT                                                     0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA9</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2__SHIFT                                                     0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA10</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA11</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA12</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS__SHIFT                                                   0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS__SHIFT                                                 0x8</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS_MASK                                                     0x000000FFL</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS_MASK                                                   0x00FFFF00L</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA13</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA14</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1_MASK                                              0x000000FFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA15_0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI__SHIFT                                              0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI_MASK                                                0x0000FFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA15_1</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ__SHIFT                                              0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ_MASK                                                0x000000FFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA16</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA17</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO__SHIFT                                             0x8</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1_MASK                                              0x000000FFL</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO_MASK                                               0x0000FF00L</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA18</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0__SHIFT                                              0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA19</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1__SHIFT                                              0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG2_HDCP_RECV_PORT_LOCAL_DATA20</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO__SHIFT                                                0x0</div><div class='add'>+#define DIG2_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO_MASK                                                  0x0000FFFFL</div><div class='add'>+//DIG2_HDCP_DP_STATUS</div><div class='add'>+#define DIG2_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK__SHIFT                                                0x1</div><div class='add'>+#define DIG2_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_MASK                                                      0x00000001L</div><div class='add'>+#define DIG2_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK_MASK                                                  0x00000002L</div><div class='add'>+//DIG2_HDCP_CLK_CNTL</div><div class='add'>+#define DIG2_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE__SHIFT                                                        0x1</div><div class='add'>+#define DIG2_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE__SHIFT                                                         0x2</div><div class='add'>+#define DIG2_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE_MASK                                                          0x00000002L</div><div class='add'>+#define DIG2_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE_MASK                                                           0x00000004L</div><div class='add'>+//DIG2_HDCP_ENGINE_SELECT</div><div class='add'>+#define DIG2_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT__SHIFT                                                    0x0</div><div class='add'>+#define DIG2_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT_MASK                                                      0x00000001L</div><div class='add'>+//DIG2_TMDS_CNTL</div><div class='add'>+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG2_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG2_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG2_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG2_TMDS_CTL_BITS</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG2_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG2_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG2_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG2_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG2_DIG_VERSION</div><div class='add'>+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dp3_dispdec</div><div class='add'>+//DP3_DP_LINK_CNTL</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L</div><div class='add'>+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L</div><div class='add'>+//DP3_DP_PIXEL_FORMAT</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT                                                 0x4</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                                              0x8</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT                                                   0x10</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                                         0x00000001L</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK                                                   0x00000030L</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                                                0x00000700L</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK                                                     0x00010000L</div><div class='add'>+//DP3_DP_MSA_COLORIMETRY</div><div class='add'>+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18</div><div class='add'>+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L</div><div class='add'>+//DP3_DP_CONFIG</div><div class='add'>+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L</div><div class='add'>+//DP3_DP_VID_STREAM_CNTL</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L</div><div class='add'>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L</div><div class='add'>+//DP3_DP_STEER_FIFO</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x1</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT                                                    0x2</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK                                                          0x00000001L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000002L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK                                                      0x00000004L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L</div><div class='add'>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L</div><div class='add'>+//DP3_DP_MSA_MISC</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L</div><div class='add'>+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L</div><div class='add'>+//DP3_DP_DPHY_INTERNAL_CTRL</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L</div><div class='add'>+//DP3_DP_VID_TIMING</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT                                                           0xe</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK                                                             0x0000C000L</div><div class='add'>+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L</div><div class='add'>+//DP3_DP_VID_N</div><div class='add'>+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0</div><div class='add'>+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP3_DP_VID_M</div><div class='add'>+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0</div><div class='add'>+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL</div><div class='add'>+//DP3_DP_LINK_FRAMING_CNTL</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT                                  0x14</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                                    0x00100000L</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L</div><div class='add'>+//DP3_DP_HBR2_EYE_PATTERN</div><div class='add'>+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L</div><div class='add'>+//DP3_DP_VID_MSA_VBID</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT                                            0xc</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK                                              0x00001000L</div><div class='add'>+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L</div><div class='add'>+//DP3_DP_VID_INTERRUPT_CNTL</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L</div><div class='add'>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L</div><div class='add'>+//DP3_DP_DPHY_CNTL</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT                                               0x7</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK                                                 0x00000080L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L</div><div class='add'>+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L</div><div class='add'>+//DP3_DP_DPHY_TRAINING_PATTERN_SEL</div><div class='add'>+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L</div><div class='add'>+//DP3_DP_DPHY_SYM0</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP3_DP_DPHY_SYM1</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L</div><div class='add'>+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L</div><div class='add'>+//DP3_DP_DPHY_SYM2</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L</div><div class='add'>+//DP3_DP_DPHY_8B10B_CNTL</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L</div><div class='add'>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L</div><div class='add'>+//DP3_DP_DPHY_PRBS_CNTL</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L</div><div class='add'>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L</div><div class='add'>+//DP3_DP_DPHY_SCRAM_CNTL</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L</div><div class='add'>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L</div><div class='add'>+//DP3_DP_DPHY_CRC_EN</div><div class='add'>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L</div><div class='add'>+//DP3_DP_DPHY_CRC_CNTL</div><div class='add'>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4</div><div class='add'>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L</div><div class='add'>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L</div><div class='add'>+//DP3_DP_DPHY_CRC_RESULT</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L</div><div class='add'>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L</div><div class='add'>+//DP3_DP_DPHY_CRC_MST_CNTL</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L</div><div class='add'>+//DP3_DP_DPHY_CRC_MST_STATUS</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L</div><div class='add'>+//DP3_DP_DPHY_FAST_TRAINING</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L</div><div class='add'>+//DP3_DP_DPHY_FAST_TRAINING_STATUS</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L</div><div class='add'>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L</div><div class='add'>+//DP3_DP_TU_CNTL</div><div class='add'>+#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT                                                            0x8</div><div class='add'>+#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT                                                             0xc</div><div class='add'>+#define DP3_DP_TU_CNTL__DP_TU_SIZE__SHIFT                                                                     0x18</div><div class='add'>+#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK                                                              0x00000100L</div><div class='add'>+#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK                                                               0x00001000L</div><div class='add'>+#define DP3_DP_TU_CNTL__DP_TU_SIZE_MASK                                                                       0x3F000000L</div><div class='add'>+//DP3_DP_PIXEL_FORMAT_DB_CNTL</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT                                            0x0</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT                                           0x4</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK                                              0x00000001L</div><div class='add'>+#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK                                             0x00000010L</div><div class='add'>+//DP3_DP_CP_LINK_VERIFICATION_PATTERN</div><div class='add'>+#define DP3_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN__SHIFT                           0x0</div><div class='add'>+#define DP3_DP_CP_LINK_VERIFICATION_PATTERN__DP_CP_LINK_VERIFICATION_PATTERN_MASK                             0x0000FFFFL</div><div class='add'>+//DP3_DP_SEC_CNTL</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L</div><div class='add'>+//DP3_DP_SEC_CNTL1</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L</div><div class='add'>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING1</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL</div><div class='add'>+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING2</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING3</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL</div><div class='add'>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_FRAMING4</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L</div><div class='add'>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L</div><div class='add'>+//DP3_DP_SEC_AUD_N</div><div class='add'>+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_AUD_N_READBACK</div><div class='add'>+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_AUD_M</div><div class='add'>+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_AUD_M_READBACK</div><div class='add'>+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0</div><div class='add'>+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL</div><div class='add'>+//DP3_DP_SEC_TIMESTAMP</div><div class='add'>+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L</div><div class='add'>+//DP3_DP_SEC_PACKET_CNTL</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L</div><div class='add'>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L</div><div class='add'>+//DP3_DP_MSE_RATE_CNTL</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL</div><div class='add'>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L</div><div class='add'>+//DP3_DP_CP_MSE_STATUS</div><div class='add'>+#define DP3_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_CP_MSE_STATUS__DP_CP_MSE_RDY_ENCRYPT_MASK                                                      0x00000001L</div><div class='add'>+//DP3_DP_MSE_RATE_UPDATE</div><div class='add'>+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L</div><div class='add'>+//DP3_DP_MSE_SAT0</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT                                                           0x14</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK                                                             0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT1</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT                                                           0x14</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK                                                             0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT2</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT                                                           0x14</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK                                                             0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT_UPDATE</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L</div><div class='add'>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L</div><div class='add'>+//DP3_DP_MSE_LINK_TIMING</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL</div><div class='add'>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L</div><div class='add'>+//DP3_DP_MSE_MISC_CNTL</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L</div><div class='add'>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L</div><div class='add'>+//DP3_DP_DPHY_BS_SR_SWAP_CNTL</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L</div><div class='add'>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L</div><div class='add'>+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL</div><div class='add'>+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0</div><div class='add'>+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L</div><div class='add'>+//DP3_DP_MSE_SAT0_STATUS</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT1_STATUS</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP3_DP_MSE_SAT2_STATUS</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT                                             0x14</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK                                               0x00100000L</div><div class='add'>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L</div><div class='add'>+//DP3_DP_DPIA_SPARE</div><div class='add'>+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE__SHIFT                                                               0x0</div><div class='add'>+#define DP3_DP_DPIA_SPARE__DP_DPIA_SPARE_MASK                                                                 0x00000003L</div><div class='add'>+//DP3_DP_HBLANK_CONTROL</div><div class='add'>+#define DP3_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                                          0x0</div><div class='add'>+#define DP3_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                                            0x0000FFFFL</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM1</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM2</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM3</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L</div><div class='add'>+//DP3_DP_MSA_TIMING_PARAM4</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL</div><div class='add'>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_MSO_CNTL</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L</div><div class='add'>+//DP3_DP_MSO_CNTL1</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L</div><div class='add'>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L</div><div class='add'>+//DP3_DP_STEER_FIFO_CNTL</div><div class='add'>+#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT                       0x8</div><div class='add'>+#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                        0x10</div><div class='add'>+#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK                         0x00000100L</div><div class='add'>+#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK                                          0x00030000L</div><div class='add'>+//DP3_DP_SEC_CNTL2</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L</div><div class='add'>+//DP3_DP_SEC_CNTL3</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_CNTL4</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_CNTL5</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_CNTL6</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L</div><div class='add'>+//DP3_DP_SEC_CNTL7</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L</div><div class='add'>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L</div><div class='add'>+//DP3_DP_DB_CNTL</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L</div><div class='add'>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L</div><div class='add'>+//DP3_DP_MSA_VBID_MISC</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L</div><div class='add'>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L</div><div class='add'>+//DP3_DP_SEC_METADATA_TRANSMISSION</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L</div><div class='add'>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L</div><div class='add'>+//DP3_DP_ALPM_CNTL</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT                                                  0x6</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT                                     0x7</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT                                                  0x8</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT                                   0xb</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT                                       0xc</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT                                                       0xf</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK                                                    0x00000040L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK                                       0x00000080L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK                                                    0x00000300L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK                                     0x00000800L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK                                         0x00001000L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK                                                         0x00008000L</div><div class='add'>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP8_CNTL</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP9_CNTL</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L</div><div class='add'>+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP10_CNTL</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP11_CNTL</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L</div><div class='add'>+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L</div><div class='add'>+//DP3_DP_GSP_EN_DB_STATUS</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L</div><div class='add'>+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL1</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT                                              0x4</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT                                               0x8</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT                                            0x14</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT                                     0x1f</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK                                                0x000000F0L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK                                                 0x0007FF00L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK                                              0x1FF00000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK                                       0x80000000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL2</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT                                           0x0</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT                                                 0x7</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT                                            0x10</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT                                              0x11</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT                                            0x12</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT                                              0x13</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT                                          0x14</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK                                             0x0000007FL</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK                                                   0x00000080L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK                                              0x00010000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK                                                0x00020000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK                                              0x00040000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK                                                0x00080000L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK                                            0x3FF00000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL3</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT                                             0x10</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK                                               0x0000FFFFL</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK                                               0xFFFF0000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL4</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT                                                  0x1</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT                                   0x2</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT                                     0x3</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT                                       0x4</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT                                           0x5</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT                                               0x6</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT                                                   0x18</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK                                                    0x00000002L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK                                     0x00000004L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK                                       0x00000008L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK                                         0x00000010L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK                                             0x00000020L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK                                                 0x00000040L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK                                                     0xFF000000L</div><div class='add'>+//DP3_DP_AUXLESS_ALPM_CNTL5</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT                                       0x0</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT                                   0x1</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                                     0x2</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT                                      0x3</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT                                  0x8</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT                                   0x10</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK                                         0x00000001L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK                                     0x00000002L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                                       0x00000004L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK                                        0x00000008L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK                                    0x0000FF00L</div><div class='add'>+#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK                                     0xFFFF0000L</div><div class='add'>+//DP3_DP_STREAM_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK                                            0x0000FFFFL</div><div class='add'>+//DP3_DP_STREAM_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT                                   0x4</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK                                     0x00000010L</div><div class='add'>+//DP3_DP_LINK_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT                                             0x0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK                                               0x0000FFFFL</div><div class='add'>+//DP3_DP_LINK_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT                                          0x0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK                                            0xFFFFFFFFL</div><div class='add'>+//DP3_DP_LINK_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT                                       0x4</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT                                   0x8</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT                                    0xc</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK                                         0x00000010L</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK                                     0x00000100L</div><div class='add'>+#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK                                      0x00001000L</div><div class='add'>+//DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT           0x0</div><div class='add'>+#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT  0x8</div><div class='add'>+#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK             0x00000001L</div><div class='add'>+#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK  0x00000100L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_dispdec</div><div class='add'>+//DIG3_DIG_FE_CNTL</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT                                                        0x14</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L</div><div class='add'>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK                                                          0x00100000L</div><div class='add'>+//DIG3_DIG_FE_CLK_CNTL</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT                                                0xa</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT                                              0xb</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON__SHIFT                                         0xc</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT                                         0xd</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK                                                  0x00000400L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK                                                0x00000800L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON_MASK                                           0x00001000L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK                                           0x00002000L</div><div class='add'>+#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_AFMT_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+//DIG3_DIG_FE_EN_CNTL</div><div class='add'>+#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG3_DIG_OUTPUT_CRC_CNTL</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L</div><div class='add'>+//DIG3_DIG_OUTPUT_CRC_RESULT</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0</div><div class='add'>+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL</div><div class='add'>+//DIG3_DIG_CLOCK_PATTERN</div><div class='add'>+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0</div><div class='add'>+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL</div><div class='add'>+//DIG3_DIG_TEST_PATTERN</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L</div><div class='add'>+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L</div><div class='add'>+//DIG3_DIG_RANDOM_PATTERN_SEED</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL</div><div class='add'>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L</div><div class='add'>+//DIG3_DIG_FIFO_CTRL0</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT                                                           0x0</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT                                                 0x2</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                   0x7</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT                                           0x8</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT                                                       0x14</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT                                                            0x1c</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK                                                   0x0000007CL</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK                                                     0x00000080L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK                                             0x00000300L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK                                                         0x00100000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK                                                              0x30000000L</div><div class='add'>+//DIG3_DIG_FIFO_CTRL1</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                              0x1</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                  0x2</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                                0xa</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                    0x10</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                    0x16</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT                                                       0x1d</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                              0x1e</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                              0x1f</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                                0x00000002L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                    0x000000FCL</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                  0x0000FC00L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                      0x001F0000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK                                                      0x03C00000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK                                                         0x20000000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                                0x40000000L</div><div class='add'>+#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                                0x80000000L</div><div class='add'>+//DIG3_HDMI_METADATA_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L</div><div class='add'>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_CONTROL</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT                                                             0xa</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                         0xb</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT                                                         0xc</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT                                                           0xd</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN_MASK                                                               0x00000400L</div><div class='add'>+#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                           0x00000800L</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK                                                           0x00001000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK                                                             0x00006000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L</div><div class='add'>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L</div><div class='add'>+//DIG3_HDMI_STATUS</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L</div><div class='add'>+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L</div><div class='add'>+//DIG3_HDMI_AUDIO_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4</div><div class='add'>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L</div><div class='add'>+//DIG3_HDMI_ACR_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L</div><div class='add'>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L</div><div class='add'>+//DIG3_HDMI_VBI_PACKET_CONTROL</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT                                                    0xc</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT                                                    0x18</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK                                                      0x00001000L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L</div><div class='add'>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK                                                      0x3F000000L</div><div class='add'>+//DIG3_HDMI_INFOFRAME_CONTROL0</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L</div><div class='add'>+//DIG3_HDMI_INFOFRAME_CONTROL1</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L</div><div class='add'>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L</div><div class='add'>+//DIG3_HDMI_GC</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L</div><div class='add'>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL3</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL4</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL7</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL8</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL9</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L</div><div class='add'>+//DIG3_HDMI_GENERIC_PACKET_CONTROL10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L</div><div class='add'>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L</div><div class='add'>+//DIG3_HDMI_DB_CONTROL</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L</div><div class='add'>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L</div><div class='add'>+//DIG3_HDMI_ACR_32_0</div><div class='add'>+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc</div><div class='add'>+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_32_1</div><div class='add'>+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG3_HDMI_ACR_44_0</div><div class='add'>+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc</div><div class='add'>+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_44_1</div><div class='add'>+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG3_HDMI_ACR_48_0</div><div class='add'>+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc</div><div class='add'>+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_48_1</div><div class='add'>+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL</div><div class='add'>+//DIG3_HDMI_ACR_STATUS_0</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L</div><div class='add'>+//DIG3_HDMI_ACR_STATUS_1</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0</div><div class='add'>+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL</div><div class='add'>+//DIG3_AFMT_CNTL</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L</div><div class='add'>+//DIG3_DIG_BE_CLK_CNTL</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT                                                              0x0</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT                                                            0x4</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT                                                        0x5</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT                                                          0x6</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT                                                 0xb</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT                                            0xd</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK                                                                0x00000007L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK                                                              0x00000010L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK                                                          0x00000020L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK                                                            0x00000040L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK                                                   0x00000800L</div><div class='add'>+#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK                                              0x00002000L</div><div class='add'>+//DIG3_DIG_BE_CNTL</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L</div><div class='add'>+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L</div><div class='add'>+//DIG3_DIG_BE_EN_CNTL</div><div class='add'>+#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT                                                             0x0</div><div class='add'>+#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK                                                               0x00000001L</div><div class='add'>+//DIG3_HDCP_INT_CONTROL</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT__SHIFT                                                   0x0</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK__SHIFT                                                   0x1</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK__SHIFT                                                  0x2</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT__SHIFT                                                      0x4</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK__SHIFT                                                      0x5</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK__SHIFT                                                     0x6</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK__SHIFT                                                 0x7</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT__SHIFT                                                   0x8</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK__SHIFT                                                   0x9</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK__SHIFT                                                  0xa</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT__SHIFT                                                  0xc</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK__SHIFT                                                  0xd</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK__SHIFT                                                 0xe</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_INT_MASK                                                     0x00000001L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_ACK_MASK                                                     0x00000002L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_SUCCESS_MASK_MASK                                                    0x00000004L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INT_MASK                                                        0x00000010L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_ACK_MASK                                                        0x00000020L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_MASK_MASK                                                       0x00000040L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_AUTH_FAIL_INFO_ACK_MASK                                                   0x00000080L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_INT_MASK                                                     0x00000100L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_ACK_MASK                                                     0x00000200L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_REQ_MASK_MASK                                                    0x00000400L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_INT_MASK                                                    0x00001000L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_ACK_MASK                                                    0x00002000L</div><div class='add'>+#define DIG3_HDCP_INT_CONTROL__HDCP_I2C_XFER_DONE_MASK_MASK                                                   0x00004000L</div><div class='add'>+//DIG3_HDCP_LINK0_STATUS</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES__SHIFT                                                   0x14</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_V_MATCHES_MASK                                                     0x00100000L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG3_HDCP_LINK0_STATUS__HDCP_LINK0_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG3_HDCP_I2C_CONTROL_0</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE__SHIFT                                                      0x0</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET__SHIFT                                                   0x2</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT__SHIFT                                                   0x8</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_0__HDCP_I2C_DISABLE_MASK                                                        0x00000001L</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_0__HDCP_I2C_SEND_RESET_MASK                                                     0x00000004L</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_0__HDCP_I2C_DDC_SELECT_MASK                                                     0x00000700L</div><div class='add'>+//DIG3_HDCP_I2C_CONTROL_1</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK__SHIFT                                                   0x0</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE__SHIFT                                                   0x1</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE__SHIFT                                               0x8</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT__SHIFT                                                  0x14</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY__SHIFT                                                  0x18</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_FAILED_ACK_MASK                                                     0x00000001L</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_XFER_IN_DE_MASK                                                     0x00000002L</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_SHORT_READ_DISABLE_MASK                                                 0x00000100L</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_COUNT_MASK                                                    0x00F00000L</div><div class='add'>+#define DIG3_HDCP_I2C_CONTROL_1__HDCP_I2C_RETRY_DELAY_MASK                                                    0xFF000000L</div><div class='add'>+//DIG3_HDCP_I2C_STATUS</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED__SHIFT                                                   0x2</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ__SHIFT                                                        0x4</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG__SHIFT                                                    0x5</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1__SHIFT                                             0x6</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0__SHIFT                                             0x8</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE__SHIFT                                                       0xa</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_ABORTED__SHIFT                                                         0xc</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT__SHIFT                                                         0xd</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_NACK0__SHIFT                                                           0xe</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_NACK1__SHIFT                                                           0xf</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_FAILED__SHIFT                                                          0x10</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_RETRIES__SHIFT                                                         0x14</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ__SHIFT                                              0x18</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQUIRED_MASK                                                     0x00000004L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_MASK                                                          0x00000010L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_URG_MASK                                                      0x00000020L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK1_MASK                                               0x000000C0L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_REQ_TYPE_LINK0_MASK                                               0x00000300L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_XFER_DONE_MASK                                                         0x00000400L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_ABORTED_MASK                                                           0x00001000L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_TIMEOUT_MASK                                                           0x00002000L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_NACK0_MASK                                                             0x00004000L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_NACK1_MASK                                                             0x00008000L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_FAILED_MASK                                                            0x00010000L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_I2C_RETRIES_MASK                                                           0x00F00000L</div><div class='add'>+#define DIG3_HDCP_I2C_STATUS__HDCP_FRAMES_TO_NEXT_I2C_REQ_MASK                                                0xFF000000L</div><div class='add'>+//DIG3_HDCP_LINK1_STATUS</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS__SHIFT                                                0x0</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL__SHIFT                                                   0x2</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO__SHIFT                                              0x4</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY__SHIFT                                                  0x8</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY__SHIFT                                                  0x9</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES__SHIFT                                                  0xc</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT__SHIFT                                           0x10</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE__SHIFT                                         0x18</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE__SHIFT                                                  0x1c</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_SUCCESS_MASK                                                  0x00000001L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_MASK                                                     0x00000004L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AUTH_FAIL_INFO_MASK                                                0x000000F0L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AN_0_READY_MASK                                                    0x00000100L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_AN_1_READY_MASK                                                    0x00000200L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_RI_MATCHES_MASK                                                    0x00001000L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_PJ_MISMATCH_COUNT_MASK                                             0x00030000L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_R0_COMPUTATION_DONE_MASK                                           0x01000000L</div><div class='add'>+#define DIG3_HDCP_LINK1_STATUS__HDCP_LINK1_KEYS_STATE_MASK                                                    0x70000000L</div><div class='add'>+//DIG3_HDCP_RESET</div><div class='add'>+#define DIG3_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE__SHIFT                                                     0x0</div><div class='add'>+#define DIG3_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE__SHIFT                                                     0x1</div><div class='add'>+#define DIG3_HDCP_RESET__HDCP_LINK0_DEAUTHENTICATE_MASK                                                       0x00000001L</div><div class='add'>+#define DIG3_HDCP_RESET__HDCP_LINK1_DEAUTHENTICATE_MASK                                                       0x00000002L</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA0__HDCP_LINK0_BKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA1</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA1__HDCP_LINK0_BKSV_1_MASK                                               0x000000FFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA2_0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI__SHIFT                                               0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA2_0__HDCP_LINK0_RI_MASK                                                 0x0000FFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA2_1</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ__SHIFT                                               0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA2_1__HDCP_LINK0_PJ_MASK                                                 0x000000FFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA3</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0__SHIFT                                             0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA3__HDCP_LINK0_AKSV_0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA4</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1__SHIFT                                             0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO__SHIFT                                              0x8</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AKSV_1_MASK                                               0x000000FFL</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA4__HDCP_LINK0_AINFO_MASK                                                0x0000FF00L</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA5</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0__SHIFT                                               0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA5__HDCP_LINK0_AN_0_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA6</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1__SHIFT                                               0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA6__HDCP_LINK0_AN_1_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA7</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0__SHIFT                                                     0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA7__HDCP_V_H0_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA8</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1__SHIFT                                                     0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA8__HDCP_V_H1_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA9</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2__SHIFT                                                     0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA9__HDCP_V_H2_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA10</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA10__HDCP_V_H3_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA11</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA11__HDCP_V_H4_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA12</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS__SHIFT                                                   0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS__SHIFT                                                 0x8</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BCAPS_MASK                                                     0x000000FFL</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA12__HDCP_BSTATUS_MASK                                                   0x00FFFF00L</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA13</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA13__HDCP_LINK1_BKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA14</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA14__HDCP_LINK1_BKSV_1_MASK                                              0x000000FFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA15_0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI__SHIFT                                              0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA15_0__HDCP_LINK1_RI_MASK                                                0x0000FFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA15_1</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ__SHIFT                                              0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA15_1__HDCP_LINK1_PJ_MASK                                                0x000000FFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA16</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0__SHIFT                                            0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA16__HDCP_LINK1_AKSV_0_MASK                                              0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA17</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1__SHIFT                                            0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO__SHIFT                                             0x8</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AKSV_1_MASK                                              0x000000FFL</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA17__HDCP_LINK1_AINFO_MASK                                               0x0000FF00L</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA18</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0__SHIFT                                              0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA18__HDCP_LINK1_AN_0_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA19</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1__SHIFT                                              0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA19__HDCP_LINK1_AN_1_MASK                                                0xFFFFFFFFL</div><div class='add'>+//DIG3_HDCP_RECV_PORT_LOCAL_DATA20</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO__SHIFT                                                0x0</div><div class='add'>+#define DIG3_HDCP_RECV_PORT_LOCAL_DATA20__HDCP_DP_BINFO_MASK                                                  0x0000FFFFL</div><div class='add'>+//DIG3_HDCP_DP_STATUS</div><div class='add'>+#define DIG3_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK__SHIFT                                                0x1</div><div class='add'>+#define DIG3_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_MASK                                                      0x00000001L</div><div class='add'>+#define DIG3_HDCP_DP_STATUS__HDCP_DP_BOOTSTRAP_DONE_ACK_MASK                                                  0x00000002L</div><div class='add'>+//DIG3_HDCP_CLK_CNTL</div><div class='add'>+#define DIG3_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE__SHIFT                                                        0x1</div><div class='add'>+#define DIG3_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE__SHIFT                                                         0x2</div><div class='add'>+#define DIG3_HDCP_CLK_CNTL__HDCP_DISPCLK_ENABLE_MASK                                                          0x00000002L</div><div class='add'>+#define DIG3_HDCP_CLK_CNTL__HDCP_SYMCLK_ENABLE_MASK                                                           0x00000004L</div><div class='add'>+//DIG3_HDCP_ENGINE_SELECT</div><div class='add'>+#define DIG3_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT__SHIFT                                                    0x0</div><div class='add'>+#define DIG3_HDCP_ENGINE_SELECT__HDCP_ENGINE_SELECT_MASK                                                      0x00000001L</div><div class='add'>+//DIG3_TMDS_CNTL</div><div class='add'>+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0</div><div class='add'>+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L</div><div class='add'>+//DIG3_TMDS_CONTROL_CHAR</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L</div><div class='add'>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L</div><div class='add'>+//DIG3_TMDS_CONTROL0_FEEDBACK</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L</div><div class='add'>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L</div><div class='add'>+//DIG3_TMDS_STEREOSYNC_CTL_SEL</div><div class='add'>+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0</div><div class='add'>+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L</div><div class='add'>+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L</div><div class='add'>+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL</div><div class='add'>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L</div><div class='add'>+//DIG3_TMDS_CTL_BITS</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L</div><div class='add'>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L</div><div class='add'>+//DIG3_TMDS_DCBALANCER_CONTROL</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L</div><div class='add'>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L</div><div class='add'>+//DIG3_TMDS_SYNC_DCBALANCE_CHAR</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL</div><div class='add'>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L</div><div class='add'>+//DIG3_TMDS_CTL0_1_GEN_CNTL</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L</div><div class='add'>+//DIG3_TMDS_CTL2_3_GEN_CNTL</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L</div><div class='add'>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L</div><div class='add'>+//DIG3_DIG_VERSION</div><div class='add'>+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0</div><div class='add'>+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_afmt_afmt_dispdec</div><div class='add'>+//AFMT0_AFMT_ACP</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT0_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT0_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT0_AFMT_60958_0</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT0_AFMT_60958_1</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT0_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT0_AFMT_60958_2</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT0_AFMT_STATUS</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT0_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT0_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT0_AFMT_INTERRUPT_STATUS</div><div class='add'>+//AFMT0_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT0_AFMT_AUDIO_DBG_DTO_CNTL</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT                                       0x0</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT                                         0x8</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT                                        0xc</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT                                          0x10</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK                                         0x00000007L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK                                           0x00000100L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK                                          0x00007000L</div><div class='add'>+#define AFMT0_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK                                            0x00070000L</div><div class='add'>+//AFMT0_AFMT_MEM_PWR</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_afmt_afmt_dispdec</div><div class='add'>+//AFMT1_AFMT_ACP</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT1_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT1_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT1_AFMT_60958_0</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT1_AFMT_60958_1</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT1_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT1_AFMT_60958_2</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT1_AFMT_STATUS</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT1_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT1_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT1_AFMT_INTERRUPT_STATUS</div><div class='add'>+//AFMT1_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT1_AFMT_AUDIO_DBG_DTO_CNTL</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT                                       0x0</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT                                         0x8</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT                                        0xc</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT                                          0x10</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK                                         0x00000007L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK                                           0x00000100L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK                                          0x00007000L</div><div class='add'>+#define AFMT1_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK                                            0x00070000L</div><div class='add'>+//AFMT1_AFMT_MEM_PWR</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_afmt_afmt_dispdec</div><div class='add'>+//AFMT2_AFMT_ACP</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT2_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT2_AFMT_60958_0</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT2_AFMT_60958_1</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT2_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT2_AFMT_60958_2</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT2_AFMT_STATUS</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT2_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT2_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT2_AFMT_INTERRUPT_STATUS</div><div class='add'>+//AFMT2_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT2_AFMT_AUDIO_DBG_DTO_CNTL</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT                                       0x0</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT                                         0x8</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT                                        0xc</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT                                          0x10</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK                                         0x00000007L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK                                           0x00000100L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK                                          0x00007000L</div><div class='add'>+#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK                                            0x00070000L</div><div class='add'>+//AFMT2_AFMT_MEM_PWR</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_afmt_afmt_dispdec</div><div class='add'>+//AFMT3_AFMT_ACP</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT3_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT3_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT3_AFMT_60958_0</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT3_AFMT_60958_1</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT3_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT3_AFMT_60958_2</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT3_AFMT_STATUS</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT3_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT3_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT3_AFMT_INTERRUPT_STATUS</div><div class='add'>+//AFMT3_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT3_AFMT_AUDIO_DBG_DTO_CNTL</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT                                       0x0</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT                                         0x8</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT                                        0xc</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT                                          0x10</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK                                         0x00000007L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK                                           0x00000100L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK                                          0x00007000L</div><div class='add'>+#define AFMT3_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK                                            0x00070000L</div><div class='add'>+//AFMT3_AFMT_MEM_PWR</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_dme_dme_dispdec</div><div class='add'>+//DME0_DME_CONTROL</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME0_DME_MEMORY_CONTROL</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_vpg_vpg_dispdec</div><div class='add'>+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG0_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG0_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG0_VPG_MEM_PWR</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG0_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG0_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG0_VPG_MPEG_INFO0</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG0_VPG_MPEG_INFO1</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_dme_dme_dispdec</div><div class='add'>+//DME1_DME_CONTROL</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME1_DME_MEMORY_CONTROL</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_vpg_vpg_dispdec</div><div class='add'>+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG1_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG1_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG1_VPG_MEM_PWR</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG1_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG1_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG1_VPG_MPEG_INFO0</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG1_VPG_MPEG_INFO1</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_dme_dme_dispdec</div><div class='add'>+//DME2_DME_CONTROL</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME2_DME_MEMORY_CONTROL</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_vpg_vpg_dispdec</div><div class='add'>+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG2_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG2_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG2_VPG_MEM_PWR</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG2_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG2_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG2_VPG_MPEG_INFO0</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG2_VPG_MPEG_INFO1</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_dme_dme_dispdec</div><div class='add'>+//DME3_DME_CONTROL</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME3_DME_MEMORY_CONTROL</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_vpg_vpg_dispdec</div><div class='add'>+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG3_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG3_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG3_VPG_MEM_PWR</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG3_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG3_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG3_VPG_MPEG_INFO0</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG3_VPG_MPEG_INFO1</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_hdcp_sha_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_hdcp1kp_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dout_i2c_dispdec</div><div class='add'>+//DC_I2C_CONTROL</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT                                                             0x1f</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L</div><div class='add'>+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK                                                               0x80000000L</div><div class='add'>+//DC_I2C_ARBITRATION</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L</div><div class='add'>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L</div><div class='add'>+//DC_I2C_INTERRUPT_CONTROL</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L</div><div class='add'>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L</div><div class='add'>+//DC_I2C_SW_STATUS</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L</div><div class='add'>+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L</div><div class='add'>+//DC_I2C_DDC1_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC2_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC3_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC4_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC5_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC6_HW_STATUS</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT                                                     0x3</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT                                                      0x10</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT                                                      0x11</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT                                          0x14</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT                                           0x1c</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK                                                       0x00000008L</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK                                                        0x00010000L</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK                                                        0x00020000L</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK                                            0x00100000L</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L</div><div class='add'>+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK                                             0x70000000L</div><div class='add'>+//DC_I2C_DDC1_SPEED</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC1_SETUP</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC2_SPEED</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC2_SETUP</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC3_SPEED</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC3_SETUP</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC4_SPEED</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC4_SETUP</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC5_SPEED</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC5_SETUP</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_DDC6_SPEED</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT                                                       0x0</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT                                          0x8</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT                                                        0x10</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK                                                         0x00000003L</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK                                            0x00000300L</div><div class='add'>+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK                                                          0xFFFF0000L</div><div class='add'>+//DC_I2C_DDC6_SETUP</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT                                                  0x1</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_SEND_RESET_LENGTH__SHIFT                                               0x2</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_EN__SHIFT                                                          0x3</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT                                                0x5</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT                                                          0x6</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT                                                    0x7</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT                                                0x8</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT                                                      0x18</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK                                                     0x00000001L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK                                                    0x00000002L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_SEND_RESET_LENGTH_MASK                                                 0x00000004L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_EN_MASK                                                            0x00000008L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK                                                0x00000010L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK                                                  0x00000020L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK                                                            0x00000040L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK                                                      0x00000080L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L</div><div class='add'>+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK                                                        0xFF000000L</div><div class='add'>+//DC_I2C_TRANSACTION0</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_TRANSACTION1</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_TRANSACTION2</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_TRANSACTION3</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L</div><div class='add'>+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L</div><div class='add'>+//DC_I2C_DATA</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L</div><div class='add'>+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L</div><div class='add'>+//DC_I2C_DDCVGA_HW_STATUS</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT                                               0x0</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT                                                 0x3</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT                                                  0x10</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT                                                  0x11</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT                                      0x14</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT                             0x18</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT                                       0x1c</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK                                                 0x00000003L</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK                                                   0x00000008L</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK                                                    0x00010000L</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK                                                    0x00020000L</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK                                        0x00100000L</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK                               0x0F000000L</div><div class='add'>+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK                                         0x70000000L</div><div class='add'>+//DC_I2C_DDCVGA_SPEED</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT                                                   0x0</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT                                 0x4</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT                                      0x8</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT                                                    0x10</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK                                                     0x00000003L</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK                                   0x00000010L</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK                                        0x00000300L</div><div class='add'>+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK                                                      0xFFFF0000L</div><div class='add'>+//DC_I2C_DDCVGA_SETUP</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT                                               0x0</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT                                              0x1</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_SEND_RESET_LENGTH__SHIFT                                           0x2</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_EN__SHIFT                                                      0x3</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT                                          0x4</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT                                            0x5</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT                                                      0x6</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT                                                0x7</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT                                            0x8</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT                                     0x10</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT                                                  0x18</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK                                                 0x00000001L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK                                                0x00000002L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_SEND_RESET_LENGTH_MASK                                             0x00000004L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_EN_MASK                                                        0x00000008L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK                                            0x00000010L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK                                              0x00000020L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK                                                        0x00000040L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK                                                  0x00000080L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK                                              0x0000FF00L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK                                       0x00FF0000L</div><div class='add'>+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK                                                    0xFF000000L</div><div class='add'>+//DC_I2C_EDID_DETECT_CTRL</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L</div><div class='add'>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L</div><div class='add'>+//DC_I2C_READ_REQUEST_INTERRUPT</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L</div><div class='add'>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dio_misc_dispdec</div><div class='add'>+//DIO_DCN_STATUS</div><div class='add'>+#define DIO_DCN_STATUS__DCN_ACTIVE__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_DCN_STATUS__DCN_ACTIVE_MASK                                                                       0x00000001L</div><div class='add'>+//DIO_SCRATCH0</div><div class='add'>+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH1</div><div class='add'>+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH2</div><div class='add'>+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH3</div><div class='add'>+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH4</div><div class='add'>+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH5</div><div class='add'>+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH6</div><div class='add'>+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_SCRATCH7</div><div class='add'>+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0</div><div class='add'>+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x0</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x1</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x2</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x3</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x4</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x5</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT                      0x6</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000001L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000002L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000004L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000008L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000010L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000020L</div><div class='add'>+#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK                        0x00000040L</div><div class='add'>+//DIO_MEM_PWR_STATUS</div><div class='add'>+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9</div><div class='add'>+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L</div><div class='add'>+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L</div><div class='add'>+//DIO_MEM_PWR_CTRL</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L</div><div class='add'>+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L</div><div class='add'>+//DIO_MEM_PWR_CTRL2</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L</div><div class='add'>+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L</div><div class='add'>+//DIO_CLK_CNTL</div><div class='add'>+#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL__SHIFT                                                                 0x0</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS__SHIFT                                                               0x9</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS__SHIFT                                                               0xa</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS__SHIFT                                                                0xb</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS__SHIFT                                                                0xc</div><div class='add'>+#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS__SHIFT                                                                0xd</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS__SHIFT                                                             0xe</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS__SHIFT                                                             0xf</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS__SHIFT                                                                0x10</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS__SHIFT                                                                0x11</div><div class='add'>+#define DIO_CLK_CNTL__DPREFCLK_R_GATE_DIS__SHIFT                                                              0x12</div><div class='add'>+#define DIO_CLK_CNTL__DPREFCLK_G_GATE_DIS__SHIFT                                                              0x13</div><div class='add'>+#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS__SHIFT                                                                 0x14</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS__SHIFT                                                          0x15</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS__SHIFT                                                          0x16</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS__SHIFT                                                          0x17</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS__SHIFT                                                          0x18</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS__SHIFT                                                          0x19</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS__SHIFT                                                          0x1a</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS__SHIFT                                                          0x1b</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS__SHIFT                                                          0x1c</div><div class='add'>+#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL_MASK                                                                   0x0000007FL</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS_MASK                                                                 0x00000200L</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS_MASK                                                                 0x00000400L</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS_MASK                                                                  0x00000800L</div><div class='add'>+#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS_MASK                                                                  0x00001000L</div><div class='add'>+#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS_MASK                                                                  0x00002000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS_MASK                                                               0x00004000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS_MASK                                                               0x00008000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS_MASK                                                                  0x00010000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS_MASK                                                                  0x00020000L</div><div class='add'>+#define DIO_CLK_CNTL__DPREFCLK_R_GATE_DIS_MASK                                                                0x00040000L</div><div class='add'>+#define DIO_CLK_CNTL__DPREFCLK_G_GATE_DIS_MASK                                                                0x00080000L</div><div class='add'>+#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS_MASK                                                                   0x00100000L</div><div class='add'>+#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS_MASK                                                            0x00200000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS_MASK                                                            0x00400000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS_MASK                                                            0x00800000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS_MASK                                                            0x01000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS_MASK                                                            0x02000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS_MASK                                                            0x04000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS_MASK                                                            0x08000000L</div><div class='add'>+#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS_MASK                                                            0x10000000L</div><div class='add'>+//DIO_POWER_MANAGEMENT_CNTL</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L</div><div class='add'>+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L</div><div class='add'>+//DIO_STEREOSYNC_SEL</div><div class='add'>+#define DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT                                                    0x0</div><div class='add'>+#define DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT                                                    0x10</div><div class='add'>+#define DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK                                                      0x00000007L</div><div class='add'>+#define DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK                                                      0x00070000L</div><div class='add'>+//DIO_SOFT_RESET</div><div class='add'>+#define DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT                                                         0x4</div><div class='add'>+#define DIO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT                                                                0x5</div><div class='add'>+#define DIO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT                                                              0x6</div><div class='add'>+#define DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK                                                           0x00000010L</div><div class='add'>+#define DIO_SOFT_RESET__I2S1_SOFT_RESET_MASK                                                                  0x00000020L</div><div class='add'>+#define DIO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK                                                                0x00000040L</div><div class='add'>+//HDCP_CLK_STATUS</div><div class='add'>+//DIO_HDMI_RXSTATUS_TIMER_CONTROL</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L</div><div class='add'>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L</div><div class='add'>+//DIO_PSP_INTERRUPT_STATUS</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT                                             0x0</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT                                            0x1</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK                                               0x00000001L</div><div class='add'>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK                                              0xFFFFFFFEL</div><div class='add'>+//DIO_PSP_INTERRUPT_CLEAR</div><div class='add'>+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT                                               0x0</div><div class='add'>+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK                                                 0x00000001L</div><div class='add'>+//DIO_STATUS</div><div class='add'>+#define DIO_STATUS__DIO_EN__SHIFT                                                                             0x0</div><div class='add'>+#define DIO_STATUS__DIO_EN_MASK                                                                               0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig_stream_mapper_dispdec</div><div class='add'>+//DIG0_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG1_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG2_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG3_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG4_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG5_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG5_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG5_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+//DIG6_STREAM_MAPPER_CONTROL</div><div class='add'>+#define DIG6_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT                                             0x0</div><div class='add'>+#define DIG6_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK                                               0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dio_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_dispdec</div><div class='add'>+//DC_GENERICA</div><div class='add'>+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7</div><div class='add'>+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L</div><div class='add'>+//DC_GENERICB</div><div class='add'>+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0</div><div class='add'>+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8</div><div class='add'>+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L</div><div class='add'>+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L</div><div class='add'>+//DCIO_CLOCK_CNTL</div><div class='add'>+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0</div><div class='add'>+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5</div><div class='add'>+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL</div><div class='add'>+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L</div><div class='add'>+//DC_REF_CLK_CNTL</div><div class='add'>+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8</div><div class='add'>+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L</div><div class='add'>+//UNIPHYA_LINK_CNTL</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYA_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYB_LINK_CNTL</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYB_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYC_LINK_CNTL</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYC_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYD_LINK_CNTL</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYD_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYE_LINK_CNTL</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYE_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYF_LINK_CNTL</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYF_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYF_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//UNIPHYG_LINK_CNTL</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L</div><div class='add'>+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L</div><div class='add'>+//UNIPHYG_CHANNEL_XBAR_CNTL</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT                                                0x1c</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT                                                0x1d</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT                                                0x1e</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT                                                0x1f</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK                                                  0x10000000L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK                                                  0x20000000L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK                                                  0x40000000L</div><div class='add'>+#define UNIPHYG_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK                                                  0x80000000L</div><div class='add'>+//DCIO_WRCMD_DELAY</div><div class='add'>+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18</div><div class='add'>+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L</div><div class='add'>+//DC_PINSTRAPS</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L</div><div class='add'>+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L</div><div class='add'>+//CC_DC_MISC_STRAPS</div><div class='add'>+#define CC_DC_MISC_STRAPS__DC_WRITE_DIS__SHIFT                                                                0x0</div><div class='add'>+#define CC_DC_MISC_STRAPS__SPARE__SHIFT                                                                       0x1</div><div class='add'>+#define CC_DC_MISC_STRAPS__HDCP_DIS__SHIFT                                                                    0x3</div><div class='add'>+#define CC_DC_MISC_STRAPS__HDCP_KEYS_INVALID__SHIFT                                                           0x5</div><div class='add'>+#define CC_DC_MISC_STRAPS__HDMI_DISABLE__SHIFT                                                                0x6</div><div class='add'>+#define CC_DC_MISC_STRAPS__DC_WRITE_DIS_MASK                                                                  0x00000001L</div><div class='add'>+#define CC_DC_MISC_STRAPS__SPARE_MASK                                                                         0x00000006L</div><div class='add'>+#define CC_DC_MISC_STRAPS__HDCP_DIS_MASK                                                                      0x00000008L</div><div class='add'>+#define CC_DC_MISC_STRAPS__HDCP_KEYS_INVALID_MASK                                                             0x00000020L</div><div class='add'>+#define CC_DC_MISC_STRAPS__HDMI_DISABLE_MASK                                                                  0x00000040L</div><div class='add'>+//DCIO_SPARE</div><div class='add'>+#define DCIO_SPARE__DCIO_SPARE__SHIFT                                                                         0x0</div><div class='add'>+#define DCIO_SPARE__DCIO_SPARE_MASK                                                                           0xFFFFFFFFL</div><div class='add'>+//INTERCEPT_STATE</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1</div><div class='add'>+#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT                                                         0x2</div><div class='add'>+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4</div><div class='add'>+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5</div><div class='add'>+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6</div><div class='add'>+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7</div><div class='add'>+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8</div><div class='add'>+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9</div><div class='add'>+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L</div><div class='add'>+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L</div><div class='add'>+#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK                                                           0x00000004L</div><div class='add'>+#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L</div><div class='add'>+#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L</div><div class='add'>+#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L</div><div class='add'>+#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L</div><div class='add'>+#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L</div><div class='add'>+#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L</div><div class='add'>+#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L</div><div class='add'>+//DCIO_PATTERN_GEN_PAT</div><div class='add'>+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT                                                     0x0</div><div class='add'>+#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//DCIO_PATTERN_GEN_EN</div><div class='add'>+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT                                                       0x0</div><div class='add'>+#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK                                                         0x00000001L</div><div class='add'>+//DCIO_BL_PWM_FRAME_START_DISP_SEL</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L</div><div class='add'>+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L</div><div class='add'>+//DCIO_GSL_GENLK_PAD_CNTL</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L</div><div class='add'>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L</div><div class='add'>+//DCIO_GSL_SWAPLOCK_PAD_CNTL</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L</div><div class='add'>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L</div><div class='add'>+//DBG_OUT_CNTL</div><div class='add'>+#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL__SHIFT                                                                  0x0</div><div class='add'>+#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL__SHIFT                                                                 0x5</div><div class='add'>+#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA__SHIFT                                                          0xc</div><div class='add'>+#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL_MASK                                                                    0x00000003L</div><div class='add'>+#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL_MASK                                                                   0x000000E0L</div><div class='add'>+#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA_MASK                                                            0x00FFF000L</div><div class='add'>+//DCIO_SOFT_RESET</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11</div><div class='add'>+#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT                                                               0x14</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L</div><div class='add'>+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L</div><div class='add'>+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L</div><div class='add'>+#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK                                                                 0x00100000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_chip_dispdec</div><div class='add'>+//DC_GPIO_GENERIC_MASK</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L</div><div class='add'>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L</div><div class='add'>+//DC_GPIO_GENERIC_A</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L</div><div class='add'>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L</div><div class='add'>+//DC_GPIO_GENERIC_EN</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L</div><div class='add'>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L</div><div class='add'>+//DC_GPIO_GENERIC_Y</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L</div><div class='add'>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L</div><div class='add'>+//DC_GPIO_DDC1_MASK</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+//DC_GPIO_DDC1_A</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC1_EN</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC1_Y</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC2_MASK</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+//DC_GPIO_DDC2_A</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC2_EN</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC2_Y</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC3_MASK</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+//DC_GPIO_DDC3_A</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC3_EN</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC3_Y</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC4_MASK</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+//DC_GPIO_DDC4_A</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC4_EN</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC4_Y</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC5_MASK</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+//DC_GPIO_DDC5_A</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC5_EN</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC5_Y</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC6_MASK</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT                                                               0x10</div><div class='add'>+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT                                                                    0x14</div><div class='add'>+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK                                                          0x00000040L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK                                                         0x00004000L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK                                                                 0x00010000L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK                                                                      0x00100000L</div><div class='add'>+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK                                                           0x00400000L</div><div class='add'>+//DC_GPIO_DDC6_A</div><div class='add'>+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDC6_EN</div><div class='add'>+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT                                                           0x8</div><div class='add'>+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK                                                             0x00000100L</div><div class='add'>+//DC_GPIO_DDC6_Y</div><div class='add'>+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT                                                             0x8</div><div class='add'>+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK                                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK                                                               0x00000100L</div><div class='add'>+//DC_GPIO_DDCVGA_MASK</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT                                              0x4</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK                                                0x00000010L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L</div><div class='add'>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L</div><div class='add'>+//DC_GPIO_DDCVGA_A</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L</div><div class='add'>+//DC_GPIO_DDCVGA_EN</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L</div><div class='add'>+//DC_GPIO_DDCVGA_Y</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L</div><div class='add'>+//DC_GPIO_SYNCA_MASK</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT                                                      0x4</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT                                                        0x6</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT                                                        0xe</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK                                                        0x00000010L</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK                                                          0x000000C0L</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK                                                          0x0000C000L</div><div class='add'>+//DC_GPIO_GENLK_MASK</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L</div><div class='add'>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L</div><div class='add'>+//DC_GPIO_GENLK_A</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L</div><div class='add'>+//DC_GPIO_GENLK_EN</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L</div><div class='add'>+//DC_GPIO_GENLK_Y</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L</div><div class='add'>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L</div><div class='add'>+//DC_GPIO_HPD_MASK</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L</div><div class='add'>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L</div><div class='add'>+//DC_GPIO_HPD_A</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L</div><div class='add'>+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L</div><div class='add'>+//DC_GPIO_HPD_EN</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L</div><div class='add'>+//DC_GPIO_HPD_Y</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L</div><div class='add'>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L</div><div class='add'>+//DC_GPIO_DRIVE_STRENGTH_S0</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0__SHIFT                                                 0x0</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0__SHIFT                                                 0x1</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0__SHIFT                                                 0x2</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0__SHIFT                                                 0x3</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0__SHIFT                                                 0x4</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0__SHIFT                                                 0x5</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0__SHIFT                                                 0x6</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0__SHIFT                                                0x8</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0__SHIFT                                              0x9</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0__SHIFT                                               0xa</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0__SHIFT                                               0xb</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICA_S0_MASK                                                   0x00000001L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICB_S0_MASK                                                   0x00000002L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICC_S0_MASK                                                   0x00000004L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICD_S0_MASK                                                   0x00000008L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICE_S0_MASK                                                   0x00000010L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICF_S0_MASK                                                   0x00000020L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENERICG_S0_MASK                                                   0x00000040L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_CLK_S0_MASK                                                  0x00000100L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_GENLK_VSYNC_S0_MASK                                                0x00000200L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_A_S0_MASK                                                 0x00000400L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S0__DC_GPIO_SWAPLOCK_B_S0_MASK                                                 0x00000800L</div><div class='add'>+//DC_GPIO_DRIVE_STRENGTH_S1</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1__SHIFT                                                 0x0</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1__SHIFT                                                 0x1</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1__SHIFT                                                 0x2</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1__SHIFT                                                 0x3</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1__SHIFT                                                 0x4</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1__SHIFT                                                 0x5</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1__SHIFT                                                 0x6</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1__SHIFT                                                0x8</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1__SHIFT                                              0x9</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1__SHIFT                                               0xa</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1__SHIFT                                               0xb</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICA_S1_MASK                                                   0x00000001L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICB_S1_MASK                                                   0x00000002L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICC_S1_MASK                                                   0x00000004L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICD_S1_MASK                                                   0x00000008L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICE_S1_MASK                                                   0x00000010L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICF_S1_MASK                                                   0x00000020L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENERICG_S1_MASK                                                   0x00000040L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_CLK_S1_MASK                                                  0x00000100L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_GENLK_VSYNC_S1_MASK                                                0x00000200L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_A_S1_MASK                                                 0x00000400L</div><div class='add'>+#define DC_GPIO_DRIVE_STRENGTH_S1__DC_GPIO_SWAPLOCK_B_S1_MASK                                                 0x00000800L</div><div class='add'>+//DC_GPIO_PWRSEQ0_EN</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L</div><div class='add'>+//DC_GPIO_PAD_STRENGTH_1</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L</div><div class='add'>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L</div><div class='add'>+//DC_GPIO_RESERVED</div><div class='add'>+#define DC_GPIO_RESERVED__DC_GPIO_RESERVED__SHIFT                                                             0x0</div><div class='add'>+#define DC_GPIO_RESERVED__DC_GPIO_RESERVED_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//PHY_AUX_CNTL</div><div class='add'>+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9</div><div class='add'>+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa</div><div class='add'>+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc</div><div class='add'>+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe</div><div class='add'>+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10</div><div class='add'>+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12</div><div class='add'>+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14</div><div class='add'>+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L</div><div class='add'>+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L</div><div class='add'>+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L</div><div class='add'>+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L</div><div class='add'>+//DC_GPIO_DRIVE_TXIMPSEL</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL__SHIFT                                              0x0</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL__SHIFT                                              0x1</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL__SHIFT                                              0x2</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL__SHIFT                                              0x3</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL__SHIFT                                              0x4</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL__SHIFT                                              0x5</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL__SHIFT                                              0x6</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL__SHIFT                                             0x8</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL__SHIFT                                           0x9</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL__SHIFT                                            0xa</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL__SHIFT                                            0xb</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL__SHIFT                                                  0xc</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL__SHIFT                                                  0xd</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL__SHIFT                                                  0xe</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL__SHIFT                                                  0xf</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL__SHIFT                                                  0x10</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL__SHIFT                                                  0x11</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICA_TXIMPSEL_MASK                                                0x00000001L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICB_TXIMPSEL_MASK                                                0x00000002L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICC_TXIMPSEL_MASK                                                0x00000004L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICD_TXIMPSEL_MASK                                                0x00000008L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICE_TXIMPSEL_MASK                                                0x00000010L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICF_TXIMPSEL_MASK                                                0x00000020L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENERICG_TXIMPSEL_MASK                                                0x00000040L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_CLK_TXIMPSEL_MASK                                               0x00000100L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_GENLK_VSYNC_TXIMPSEL_MASK                                             0x00000200L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_A_TXIMPSEL_MASK                                              0x00000400L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_SWAPLOCK_B_TXIMPSEL_MASK                                              0x00000800L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD1_TXIMPSEL_MASK                                                    0x00001000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD2_TXIMPSEL_MASK                                                    0x00002000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD3_TXIMPSEL_MASK                                                    0x00004000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD4_TXIMPSEL_MASK                                                    0x00008000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD5_TXIMPSEL_MASK                                                    0x00010000L</div><div class='add'>+#define DC_GPIO_DRIVE_TXIMPSEL__DC_GPIO_HPD6_TXIMPSEL_MASK                                                    0x00020000L</div><div class='add'>+//DC_GPIO_PWRSEQ1_EN</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L</div><div class='add'>+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L</div><div class='add'>+//DC_GPIO_I2S_SPDIF_MASK</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT                                                  0x0</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT                                                     0x4</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT                                                     0x5</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT                                                     0x6</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT                                                    0x7</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT                                                  0x8</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT                                                     0x9</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT                                                     0xa</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT                                                     0xb</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT                                                    0xc</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK                                                    0x0000000FL</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK                                                       0x00000010L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK                                                       0x00000020L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK                                                       0x00000040L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK                                                      0x00000080L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK                                                    0x00000100L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK                                                       0x00000200L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK                                                       0x00000400L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK                                                       0x00000800L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK                                                      0x00001000L</div><div class='add'>+//DC_GPIO_I2S_SPDIF_A</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT                                                           0x4</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT                                                           0x5</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT                                                           0x6</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT                                                          0x7</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT                                                        0x8</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT                                                           0x9</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT                                                           0xa</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT                                                           0xb</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT                                                          0xc</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK                                                          0x0000000FL</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK                                                             0x00000010L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK                                                             0x00000020L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK                                                             0x00000040L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK                                                            0x00000080L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK                                                          0x00000100L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK                                                             0x00000200L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK                                                             0x00000400L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK                                                             0x00000800L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK                                                            0x00001000L</div><div class='add'>+//DC_GPIO_I2S_SPDIF_EN</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT                                                      0x0</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT                                                         0x4</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT                                                         0x5</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT                                                         0x6</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT                                                        0x7</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT                                                      0x8</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT                                                         0x9</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT                                                         0xa</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT                                                         0xb</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT                                                        0xc</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_PU__SHIFT                                                        0xe</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_RXSEL__SHIFT                                                     0x10</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_RXEN__SHIFT                                                      0x14</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK                                                        0x0000000FL</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK                                                           0x00000010L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK                                                           0x00000020L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK                                                           0x00000040L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK                                                          0x00000080L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK                                                        0x00000100L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK                                                           0x00000200L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK                                                           0x00000400L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK                                                           0x00000800L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK                                                          0x00001000L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_PU_MASK                                                          0x00004000L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_RXSEL_MASK                                                       0x00030000L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_RXEN_MASK                                                        0x00100000L</div><div class='add'>+//DC_GPIO_I2S_SPDIF_Y</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT                                                        0x0</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT                                                           0x4</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT                                                           0x5</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT                                                           0x6</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT                                                          0x7</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT                                                        0x8</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT                                                           0x9</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT                                                           0xa</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT                                                           0xb</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT                                                          0xc</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK                                                          0x0000000FL</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK                                                             0x00000010L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK                                                             0x00000020L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK                                                             0x00000040L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK                                                            0x00000080L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK                                                          0x00000100L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK                                                             0x00000200L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK                                                             0x00000400L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK                                                             0x00000800L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK                                                            0x00001000L</div><div class='add'>+//DC_GPIO_I2S_SPDIF_STRENGTH</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT                                                   0x0</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT                                              0x8</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT                                              0xb</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT                                                   0x10</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__DC_GPIO_SPDIF1_STRENGTH__SHIFT                                            0x18</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK                                                     0x00000007L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK                                                0x00000700L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK                                                0x00003800L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK                                                     0x00070000L</div><div class='add'>+#define DC_GPIO_I2S_SPDIF_STRENGTH__DC_GPIO_SPDIF1_STRENGTH_MASK                                              0x01000000L</div><div class='add'>+//DC_GPIO_TX12_EN</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L</div><div class='add'>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L</div><div class='add'>+//DC_GPIO_AUX_CTRL_0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00C00000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0xC0000000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_1</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00001800L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00030000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x000C0000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0xC0000000L</div><div class='add'>+//DC_GPIO_RXEN</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L</div><div class='add'>+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L</div><div class='add'>+//DC_GPIO_PULLUPEN</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_3</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L</div><div class='add'>+//DC_GPIO_AUX_CTRL_5</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L</div><div class='add'>+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L</div><div class='add'>+//AUXI2C_PAD_ALL_PWR_OK</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L</div><div class='add'>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy0_dispdec</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy1_dispdec</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy2_dispdec</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcio_dcio_uniphy3_dispdec</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0</div><div class='add'>+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_pwrseq0_dispdec_pwrseq_dispdec</div><div class='add'>+//DC_GPIO_PWRSEQ_EN</div><div class='add'>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8</div><div class='add'>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x10</div><div class='add'>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00010000L</div><div class='add'>+//DC_GPIO_PWRSEQ_CTRL</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL__SHIFT                                                  0x0</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL__SHIFT                                                    0x1</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL__SHIFT                                                     0x2</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                                      0x3</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                        0x4</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                         0x5</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                                     0x6</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                                       0x7</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                        0x8</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0__SHIFT                                                        0x10</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1__SHIFT                                                        0x14</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1__SHIFT                                                          0x15</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1__SHIFT                                                           0x16</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TXIMPSEL_MASK                                                    0x00000001L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TXIMPSEL_MASK                                                      0x00000002L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TXIMPSEL_MASK                                                       0x00000004L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                        0x00000008L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                          0x00000010L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                           0x00000020L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                                       0x00000040L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                         0x00000080L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                          0x00000100L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_S0_MASK                                                          0x00010000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_S1_MASK                                                          0x00100000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_S1_MASK                                                            0x00200000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_S1_MASK                                                             0x00400000L</div><div class='add'>+//DC_GPIO_PWRSEQ_MASK</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                                      0x0</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                                    0x4</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                                      0x6</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x10</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x14</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x16</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                        0x00000001L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                                      0x00000010L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                        0x000000C0L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00010000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00100000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x00C00000L</div><div class='add'>+//DC_GPIO_PWRSEQ_A_Y</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                          0x0</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                          0x1</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                            0x8</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                            0x9</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                             0x10</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                             0x11</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                            0x00000001L</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                            0x00000002L</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                              0x00000100L</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                              0x00000200L</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                               0x00010000L</div><div class='add'>+#define DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                               0x00020000L</div><div class='add'>+//PANEL_PWRSEQ_CNTL</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                             0x0</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                                0x8</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                           0x9</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                            0xa</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                                 0x10</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                            0x11</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                             0x12</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                                  0x18</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                             0x19</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                              0x1a</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                               0x00000001L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                                  0x00000100L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                             0x00000200L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                              0x00000400L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                                   0x00010000L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                              0x00020000L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                               0x00040000L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                                    0x01000000L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                               0x02000000L</div><div class='add'>+#define PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                                0x04000000L</div><div class='add'>+//PANEL_PWRSEQ_STATE</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                         0x1</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                        0x2</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                          0x3</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                          0x4</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                         0x8</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                           0x00000002L</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                          0x00000004L</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                            0x00000008L</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                            0x00000010L</div><div class='add'>+#define PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                           0x00000F00L</div><div class='add'>+//PANEL_PWRSEQ_DELAY1</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                        0x0</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                        0x8</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                        0x10</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                        0x18</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                          0x000000FFL</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                          0x0000FF00L</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                          0x00FF0000L</div><div class='add'>+#define PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                          0xFF000000L</div><div class='add'>+//PANEL_PWRSEQ_DELAY2</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                                    0x0</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                        0x8</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                        0x10</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                          0x0000FF00L</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                          0x00FF0000L</div><div class='add'>+#define PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L</div><div class='add'>+//PANEL_PWRSEQ_REF_DIV1</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                                    0x0</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                          0x10</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                                      0x00000FFFL</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                            0xFFFF0000L</div><div class='add'>+//BL_PWM_CNTL</div><div class='add'>+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0</div><div class='add'>+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                                 0x13</div><div class='add'>+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                                      0x14</div><div class='add'>+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                    0x15</div><div class='add'>+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e</div><div class='add'>+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f</div><div class='add'>+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL</div><div class='add'>+#define BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                                   0x00080000L</div><div class='add'>+#define BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                        0x00100000L</div><div class='add'>+#define BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                      0x00200000L</div><div class='add'>+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L</div><div class='add'>+#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L</div><div class='add'>+//BL_PWM_CNTL2</div><div class='add'>+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                                   0x1c</div><div class='add'>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e</div><div class='add'>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                                  0x1f</div><div class='add'>+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL</div><div class='add'>+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                                     0x30000000L</div><div class='add'>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L</div><div class='add'>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                                    0x80000000L</div><div class='add'>+//BL_PWM_PERIOD_CNTL</div><div class='add'>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0</div><div class='add'>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10</div><div class='add'>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL</div><div class='add'>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L</div><div class='add'>+//BL_PWM_GRP1_REG_LOCK</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L</div><div class='add'>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L</div><div class='add'>+//PANEL_PWRSEQ_REF_DIV2</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                            0x0</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                               0x8</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                        0x10</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                              0x0000007FL</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                                 0x00007F00L</div><div class='add'>+#define PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                          0x00010000L</div><div class='add'>+//PWRSEQ_DBG_SEL</div><div class='add'>+#define PWRSEQ_DBG_SEL__PWRSEQ_DBG_DATA_SEL__SHIFT                                                            0x0</div><div class='add'>+#define PWRSEQ_DBG_SEL__PWRSEQ_DBG_CLK_SEL__SHIFT                                                             0x3</div><div class='add'>+#define PWRSEQ_DBG_SEL__PWRSEQ_DBG_DATA_SEL_MASK                                                              0x00000007L</div><div class='add'>+#define PWRSEQ_DBG_SEL__PWRSEQ_DBG_CLK_SEL_MASK                                                               0x00000008L</div><div class='add'>+//PWRSEQ_SPARE</div><div class='add'>+#define PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                                     0x0</div><div class='add'>+#define PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dscc_dispdec</div><div class='add'>+//DSCC0_DSCC_CONFIG0</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_CONFIG1</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC0_DSCC_CONFIG2</div><div class='add'>+#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT                                         0x0</div><div class='add'>+#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK                                    0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_STATUS</div><div class='add'>+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC0_DSCC_INTERRUPT_CONTROL0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT        0x0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT        0x1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT        0x2</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT        0x3</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK          0x00000001L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK          0x00000002L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK          0x00000004L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK          0x00000008L</div><div class='add'>+//DSCC0_DSCC_INTERRUPT_CONTROL1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT                    0x0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT                    0x1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT                    0x2</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT                    0x3</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT                   0x4</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT                   0x5</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT                   0x6</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT                   0x7</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT                   0x8</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK                      0x00000001L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK                      0x00000002L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK                      0x00000004L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK                      0x00000008L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK                     0x00000010L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK                     0x00000020L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK                     0x00000040L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK                     0x00000080L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK                     0x00000100L</div><div class='add'>+//DSCC0_DSCC_INTERRUPT_STATUS0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT                0x0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT                0x1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT                0x2</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT                0x3</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT                   0x10</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT                   0x11</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT                   0x12</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT                   0x13</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK                  0x00000001L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK                  0x00000002L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK                  0x00000004L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK                  0x00000008L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK                     0x00010000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK                     0x00020000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK                     0x00040000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK                     0x00080000L</div><div class='add'>+//DSCC0_DSCC_INTERRUPT_STATUS1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT                            0x0</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT                            0x1</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT                            0x2</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT                            0x3</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT                           0x4</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT                           0x5</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT                           0x6</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT                           0x7</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                           0x8</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT                               0x10</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT                               0x11</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT                               0x12</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT                               0x13</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT                              0x14</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT                              0x15</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT                              0x16</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT                              0x17</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT                              0x18</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK                              0x00000001L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK                              0x00000002L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK                              0x00000004L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK                              0x00000008L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK                             0x00000010L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK                             0x00000020L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK                             0x00000040L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK                             0x00000080L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                             0x00000100L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK                                 0x00010000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK                                 0x00020000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK                                 0x00040000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK                                 0x00080000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK                                0x00100000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK                                0x00200000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK                                0x00400000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK                                0x00800000L</div><div class='add'>+#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK                                0x01000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC0_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC0_DSCC_MEM_POWER_CONTROL0</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC0_DSCC_MEM_POWER_CONTROL1</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC0_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT           0x0</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK             0x00007FFFL</div><div class='add'>+//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT           0x0</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK             0x00007FFFL</div><div class='add'>+//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT           0x0</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK             0x00007FFFL</div><div class='add'>+//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT           0x0</div><div class='add'>+#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK             0x00007FFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT   0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK     0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT   0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK     0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT   0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK     0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT   0x0</div><div class='add'>+#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK     0x0003FFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_INDEX0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT                                           0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK                                             0x000000FFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_INDEX1</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT                                           0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK                                             0x000000FFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_INDEX2</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT                                           0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK                                             0x000000FFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_INDEX3</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT                                           0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK                                             0x000000FFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_DATA0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT                                             0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_DATA1</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT                                             0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_DATA2</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT                                             0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_TEST_DEBUG_DATA3</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT                                             0x0</div><div class='add'>+#define DSCC0_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK                                               0xFFFFFFFFL</div><div class='add'>+//DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0</div><div class='add'>+#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT                           0x0</div><div class='add'>+#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK                             0x000000FFL</div><div class='add'>+//DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0</div><div class='add'>+#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT                             0x0</div><div class='add'>+#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF0_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP0_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+//DSC_TOP0_DSC_DEBUG_CONTROL</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L</div><div class='add'>+//DSC_TOP0_DSC_SPARE_DEBUG</div><div class='add'>+#define DSC_TOP0_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT                                                      0x0</div><div class='add'>+#define DSC_TOP0_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK                                                        0xFFFFFFFFL</div><div class='add'>+//DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX</div><div class='add'>+#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT                                    0x0</div><div class='add'>+#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT                               0x8</div><div class='add'>+#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK                                      0x000000FFL</div><div class='add'>+#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK                                 0x00001F00L</div><div class='add'>+//DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA</div><div class='add'>+#define DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT                                      0x0</div><div class='add'>+#define DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dscc_dispdec</div><div class='add'>+//DSCC1_DSCC_CONFIG0</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_CONFIG1</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC1_DSCC_CONFIG2</div><div class='add'>+#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT                                         0x0</div><div class='add'>+#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT                                  0x10</div><div class='add'>+#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK                                    0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_STATUS</div><div class='add'>+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC1_DSCC_INTERRUPT_CONTROL0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT        0x0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT        0x1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT        0x2</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT        0x3</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK          0x00000001L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK          0x00000002L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK          0x00000004L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK          0x00000008L</div><div class='add'>+//DSCC1_DSCC_INTERRUPT_CONTROL1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT                    0x0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT                    0x1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT                    0x2</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT                    0x3</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT                   0x4</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT                   0x5</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT                   0x6</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT                   0x7</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT                   0x8</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK                      0x00000001L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK                      0x00000002L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK                      0x00000004L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK                      0x00000008L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK                     0x00000010L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK                     0x00000020L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK                     0x00000040L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK                     0x00000080L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK                     0x00000100L</div><div class='add'>+//DSCC1_DSCC_INTERRUPT_STATUS0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT                0x0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT                0x1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT                0x2</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT                0x3</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT                   0x10</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT                   0x11</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT                   0x12</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT                   0x13</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK                  0x00000001L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK                  0x00000002L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK                  0x00000004L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK                  0x00000008L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK                     0x00010000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK                     0x00020000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK                     0x00040000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK                     0x00080000L</div><div class='add'>+//DSCC1_DSCC_INTERRUPT_STATUS1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT                            0x0</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT                            0x1</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT                            0x2</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT                            0x3</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT                           0x4</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT                           0x5</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT                           0x6</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT                           0x7</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                           0x8</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT                               0x10</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT                               0x11</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT                               0x12</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT                               0x13</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT                              0x14</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT                              0x15</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT                              0x16</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT                              0x17</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT                              0x18</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK                              0x00000001L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK                              0x00000002L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK                              0x00000004L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK                              0x00000008L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK                             0x00000010L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK                             0x00000020L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK                             0x00000040L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK                             0x00000080L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                             0x00000100L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK                                 0x00010000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK                                 0x00020000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK                                 0x00040000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK                                 0x00080000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK                                0x00100000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK                                0x00200000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK                                0x00400000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK                                0x00800000L</div><div class='add'>+#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK                                0x01000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC1_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC1_DSCC_MEM_POWER_CONTROL0</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC1_DSCC_MEM_POWER_CONTROL1</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC1_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC1_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT           0x0</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK             0x00007FFFL</div><div class='add'>+//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT           0x0</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK             0x00007FFFL</div><div class='add'>+//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT           0x0</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK             0x00007FFFL</div><div class='add'>+//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT           0x0</div><div class='add'>+#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK             0x00007FFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT   0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK     0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT   0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK     0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT   0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK     0x0003FFFFL</div><div class='add'>+//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT   0x0</div><div class='add'>+#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK     0x0003FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF1_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP1_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dscc_dispdec</div><div class='add'>+//DSCC2_DSCC_CONFIG0</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_CONFIG1</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC2_DSCC_CONFIG2</div><div class='add'>+#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT                                         0x0</div><div class='add'>+#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT                                  0x10</div><div class='add'>+#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK                                    0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_STATUS</div><div class='add'>+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC2_DSCC_INTERRUPT_CONTROL0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT        0x0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT        0x1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT        0x2</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT        0x3</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK          0x00000001L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK          0x00000002L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK          0x00000004L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK          0x00000008L</div><div class='add'>+//DSCC2_DSCC_INTERRUPT_CONTROL1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT                    0x0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT                    0x1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT                    0x2</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT                    0x3</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT                   0x4</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT                   0x5</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT                   0x6</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT                   0x7</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT                   0x8</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK                      0x00000001L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK                      0x00000002L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK                      0x00000004L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK                      0x00000008L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK                     0x00000010L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK                     0x00000020L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK                     0x00000040L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK                     0x00000080L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK                     0x00000100L</div><div class='add'>+//DSCC2_DSCC_INTERRUPT_STATUS0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT                0x0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT                0x1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT                0x2</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT                0x3</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT                   0x10</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT                   0x11</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT                   0x12</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT                   0x13</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK                  0x00000001L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK                  0x00000002L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK                  0x00000004L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK                  0x00000008L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK                     0x00010000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK                     0x00020000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK                     0x00040000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK                     0x00080000L</div><div class='add'>+//DSCC2_DSCC_INTERRUPT_STATUS1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT                            0x0</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT                            0x1</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT                            0x2</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT                            0x3</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT                           0x4</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT                           0x5</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT                           0x6</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT                           0x7</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                           0x8</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT                               0x10</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT                               0x11</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT                               0x12</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT                               0x13</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT                              0x14</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT                              0x15</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT                              0x16</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT                              0x17</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT                              0x18</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK                              0x00000001L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK                              0x00000002L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK                              0x00000004L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK                              0x00000008L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK                             0x00000010L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK                             0x00000020L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK                             0x00000040L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK                             0x00000080L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                             0x00000100L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK                                 0x00010000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK                                 0x00020000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK                                 0x00040000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK                                 0x00080000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK                                0x00100000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK                                0x00200000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK                                0x00400000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK                                0x00800000L</div><div class='add'>+#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK                                0x01000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC2_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC2_DSCC_MEM_POWER_CONTROL0</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC2_DSCC_MEM_POWER_CONTROL1</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC2_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC2_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT           0x0</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK             0x00007FFFL</div><div class='add'>+//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT           0x0</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK             0x00007FFFL</div><div class='add'>+//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT           0x0</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK             0x00007FFFL</div><div class='add'>+//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT           0x0</div><div class='add'>+#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK             0x00007FFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT   0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK     0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT   0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK     0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT   0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK     0x0003FFFFL</div><div class='add'>+//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT   0x0</div><div class='add'>+#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK     0x0003FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF2_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP2_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dscc_dispdec</div><div class='add'>+//DSCC3_DSCC_CONFIG0</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L</div><div class='add'>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_CONFIG1</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL</div><div class='add'>+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L</div><div class='add'>+//DSCC3_DSCC_CONFIG2</div><div class='add'>+#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT                                         0x0</div><div class='add'>+#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT                                  0x10</div><div class='add'>+#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK                                    0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_STATUS</div><div class='add'>+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0</div><div class='add'>+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L</div><div class='add'>+//DSCC3_DSCC_INTERRUPT_CONTROL0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT        0x0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT        0x1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT        0x2</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT        0x3</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK          0x00000001L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK          0x00000002L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK          0x00000004L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK          0x00000008L</div><div class='add'>+//DSCC3_DSCC_INTERRUPT_CONTROL1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT                    0x0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT                    0x1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT                    0x2</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT                    0x3</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT                   0x4</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT                   0x5</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT                   0x6</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT                   0x7</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT                   0x8</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK                      0x00000001L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK                      0x00000002L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK                      0x00000004L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK                      0x00000008L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK                     0x00000010L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK                     0x00000020L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK                     0x00000040L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK                     0x00000080L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK                     0x00000100L</div><div class='add'>+//DSCC3_DSCC_INTERRUPT_STATUS0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT                0x0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT                0x1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT                0x2</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT                0x3</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT                   0x10</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT                   0x11</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT                   0x12</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT                   0x13</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK                  0x00000001L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK                  0x00000002L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK                  0x00000004L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK                  0x00000008L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK                     0x00010000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK                     0x00020000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK                     0x00040000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK                     0x00080000L</div><div class='add'>+//DSCC3_DSCC_INTERRUPT_STATUS1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT                            0x0</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT                            0x1</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT                            0x2</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT                            0x3</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT                           0x4</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT                           0x5</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT                           0x6</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT                           0x7</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT                           0x8</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT                               0x10</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT                               0x11</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT                               0x12</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT                               0x13</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT                              0x14</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT                              0x15</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT                              0x16</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT                              0x17</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT                              0x18</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK                              0x00000001L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK                              0x00000002L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK                              0x00000004L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK                              0x00000008L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK                             0x00000010L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK                             0x00000020L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK                             0x00000040L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK                             0x00000080L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK                             0x00000100L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK                                 0x00010000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK                                 0x00020000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK                                 0x00040000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK                                 0x00080000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK                                0x00100000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK                                0x00200000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK                                0x00400000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK                                0x00800000L</div><div class='add'>+#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK                                0x01000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG1</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG2</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG3</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG4</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG6</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG7</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG9</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG11</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG12</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG13</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG14</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG16</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG17</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG18</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG19</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG20</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG21</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC3_DSCC_PPS_CONFIG22</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L</div><div class='add'>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L</div><div class='add'>+//DSCC3_DSCC_MEM_POWER_CONTROL0</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC3_DSCC_MEM_POWER_CONTROL1</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0x0</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT                                              0x4</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT                                              0x10</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00000003L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK                                                0x00000030L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK                                                0x00030000L</div><div class='add'>+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0</div><div class='add'>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0</div><div class='add'>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL</div><div class='add'>+//DSCC3_DSCC_MAX_ABS_ERROR0</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L</div><div class='add'>+//DSCC3_DSCC_MAX_ABS_ERROR1</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0</div><div class='add'>+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL</div><div class='add'>+//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT           0x0</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK             0x00007FFFL</div><div class='add'>+//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT           0x0</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK             0x00007FFFL</div><div class='add'>+//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT           0x0</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK             0x00007FFFL</div><div class='add'>+//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT           0x0</div><div class='add'>+#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK             0x00007FFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT   0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK     0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT   0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK     0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT   0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK     0x0003FFFFL</div><div class='add'>+//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT   0x0</div><div class='add'>+#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK     0x0003FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dsccif_dispdec</div><div class='add'>+//DSCCIF3_DSCCIF_CONFIG0</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L</div><div class='add'>+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dsc_top_dispdec</div><div class='add'>+//DSC_TOP3_DSC_TOP_CONTROL</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT                                                     0xc</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT                                     0x10</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK                                                       0x00001000L</div><div class='add'>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK                                       0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dcoh_top_dispdec</div><div class='add'>+//DCOH_TOP_CLOCK_CONTROL</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_G_GATE_DIS__SHIFT                                                0x0</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_R_GATE_DIS__SHIFT                                                0x4</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_G_GATE_DIS__SHIFT                                                 0x8</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_R_GATE_DIS__SHIFT                                                 0xc</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_FGCG_REP_DIS__SHIFT                                                      0x10</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_G_GATE_DIS_MASK                                                  0x00000001L</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_R_GATE_DIS_MASK                                                  0x00000010L</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_G_GATE_DIS_MASK                                                   0x00000100L</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_R_GATE_DIS_MASK                                                   0x00001000L</div><div class='add'>+#define DCOH_TOP_CLOCK_CONTROL__DCOH_FGCG_REP_DIS_MASK                                                        0x00010000L</div><div class='add'>+//DCOH_TOP_SPARE</div><div class='add'>+#define DCOH_TOP_SPARE__DCOH_TOP_SPARE__SHIFT                                                                 0x0</div><div class='add'>+#define DCOH_TOP_SPARE__DCOH_TOP_SPARE_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux0_dispdec</div><div class='add'>+//PHY_MUX0_PHY_MUX_CONTROL</div><div class='add'>+#define PHY_MUX0_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT                                                         0x0</div><div class='add'>+#define PHY_MUX0_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT                                                     0x4</div><div class='add'>+#define PHY_MUX0_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define PHY_MUX0_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define PHY_MUX0_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK                                                       0x00000070L</div><div class='add'>+#define PHY_MUX0_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//PHY_MUX0_PORT_TYPE</div><div class='add'>+#define PHY_MUX0_PORT_TYPE__PORT_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define PHY_MUX0_PORT_TYPE__PORT_TYPE_MASK                                                                    0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux1_dispdec</div><div class='add'>+//PHY_MUX1_PHY_MUX_CONTROL</div><div class='add'>+#define PHY_MUX1_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT                                                         0x0</div><div class='add'>+#define PHY_MUX1_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT                                                     0x4</div><div class='add'>+#define PHY_MUX1_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define PHY_MUX1_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define PHY_MUX1_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK                                                       0x00000070L</div><div class='add'>+#define PHY_MUX1_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//PHY_MUX1_PORT_TYPE</div><div class='add'>+#define PHY_MUX1_PORT_TYPE__PORT_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define PHY_MUX1_PORT_TYPE__PORT_TYPE_MASK                                                                    0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux2_dispdec</div><div class='add'>+//PHY_MUX2_PHY_MUX_CONTROL</div><div class='add'>+#define PHY_MUX2_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT                                                         0x0</div><div class='add'>+#define PHY_MUX2_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT                                                     0x4</div><div class='add'>+#define PHY_MUX2_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define PHY_MUX2_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define PHY_MUX2_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK                                                       0x00000070L</div><div class='add'>+#define PHY_MUX2_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//PHY_MUX2_PORT_TYPE</div><div class='add'>+#define PHY_MUX2_PORT_TYPE__PORT_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define PHY_MUX2_PORT_TYPE__PORT_TYPE_MASK                                                                    0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_phy_mux3_dispdec</div><div class='add'>+//PHY_MUX3_PHY_MUX_CONTROL</div><div class='add'>+#define PHY_MUX3_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT                                                         0x0</div><div class='add'>+#define PHY_MUX3_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT                                                     0x4</div><div class='add'>+#define PHY_MUX3_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT                                                       0x8</div><div class='add'>+#define PHY_MUX3_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK                                                           0x00000003L</div><div class='add'>+#define PHY_MUX3_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK                                                       0x00000070L</div><div class='add'>+#define PHY_MUX3_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK                                                         0x00000700L</div><div class='add'>+//PHY_MUX3_PORT_TYPE</div><div class='add'>+#define PHY_MUX3_PORT_TYPE__PORT_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define PHY_MUX3_PORT_TYPE__PORT_TYPE_MASK                                                                    0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux0_dispdec</div><div class='add'>+//DP_AUX0_AUX_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX0_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX0_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX0_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+//DP_AUX0_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0x60000000L</div><div class='add'>+//DP_AUX0_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX0_AUX_SW_DATA</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX0_AUX_LS_DATA</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX0_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX0_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+//DP_AUX0_AUX_PHY_WAKE_STATUS</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT                                    0x4</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT                                          0x7</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT                                   0xc</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT                                   0x11</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT                                   0x12</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT                                      0x14</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT                                   0x16</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT                                   0x17</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK                                      0x00000070L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK                                            0x00000080L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK                                     0x00001000L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK                                       0x00004000L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK                                     0x00020000L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK                                     0x00040000L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK                                        0x00100000L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK                                     0x00400000L</div><div class='add'>+#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK                                     0x00800000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux1_dispdec</div><div class='add'>+//DP_AUX1_AUX_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX1_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX1_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX1_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+//DP_AUX1_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0x60000000L</div><div class='add'>+//DP_AUX1_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX1_AUX_SW_DATA</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX1_AUX_LS_DATA</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX1_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX1_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+//DP_AUX1_AUX_PHY_WAKE_STATUS</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT                                    0x4</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT                                          0x7</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT                                   0xc</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT                                   0x11</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT                                   0x12</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT                                      0x14</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT                                   0x16</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT                                   0x17</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK                                      0x00000070L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK                                            0x00000080L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK                                     0x00001000L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK                                       0x00004000L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK                                     0x00020000L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK                                     0x00040000L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK                                        0x00100000L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK                                     0x00400000L</div><div class='add'>+#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK                                     0x00800000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux2_dispdec</div><div class='add'>+//DP_AUX2_AUX_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX2_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX2_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX2_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+//DP_AUX2_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0x60000000L</div><div class='add'>+//DP_AUX2_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX2_AUX_SW_DATA</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX2_AUX_LS_DATA</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX2_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX2_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+//DP_AUX2_AUX_PHY_WAKE_STATUS</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT                                    0x4</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT                                          0x7</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT                                   0xc</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT                                   0x11</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT                                   0x12</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT                                      0x14</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT                                   0x16</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT                                   0x17</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK                                      0x00000070L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK                                            0x00000080L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK                                     0x00001000L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK                                       0x00004000L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK                                     0x00020000L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK                                     0x00040000L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK                                        0x00100000L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK                                     0x00400000L</div><div class='add'>+#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK                                     0x00800000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_dp_aux3_dispdec</div><div class='add'>+//DP_AUX3_AUX_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L</div><div class='add'>+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L</div><div class='add'>+//DP_AUX3_AUX_SW_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L</div><div class='add'>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L</div><div class='add'>+//DP_AUX3_AUX_ARB_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L</div><div class='add'>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L</div><div class='add'>+//DP_AUX3_AUX_INTERRUPT_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L</div><div class='add'>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L</div><div class='add'>+//DP_AUX3_AUX_SW_STATUS</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0x60000000L</div><div class='add'>+//DP_AUX3_AUX_LS_STATUS</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L</div><div class='add'>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L</div><div class='add'>+//DP_AUX3_AUX_SW_DATA</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L</div><div class='add'>+//DP_AUX3_AUX_LS_DATA</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L</div><div class='add'>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_TX_CONTROL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_RX_CONTROL0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_RX_CONTROL1</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_TX_STATUS</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L</div><div class='add'>+//DP_AUX3_AUX_DPHY_RX_STATUS</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L</div><div class='add'>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L</div><div class='add'>+//DP_AUX3_AUX_PHY_WAKE_CNTL</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L</div><div class='add'>+//DP_AUX3_AUX_PHY_WAKE_STATUS</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT                                    0x4</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT                                          0x7</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT                                           0x9</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT                                         0xb</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT                                   0xc</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT                                     0xe</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT                                   0x11</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT                                   0x12</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT                                      0x14</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT                                   0x16</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT                                   0x17</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK                                      0x00000070L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK                                            0x00000080L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK                                             0x00000200L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK                                           0x00000800L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK                                     0x00001000L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK                                       0x00004000L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK                                     0x00020000L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK                                     0x00040000L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK                                        0x00100000L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK                                     0x00400000L</div><div class='add'>+#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK                                     0x00800000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd0_dispdec</div><div class='add'>+//HPD0_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD0_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD0_DC_HPD_CONTROL</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD0_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD0_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd1_dispdec</div><div class='add'>+//HPD1_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD1_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD1_DC_HPD_CONTROL</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD1_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD1_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd2_dispdec</div><div class='add'>+//HPD2_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD2_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD2_DC_HPD_CONTROL</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD2_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD2_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dcoh_hpd3_dispdec</div><div class='add'>+//HPD3_DC_HPD_INT_STATUS</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L</div><div class='add'>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L</div><div class='add'>+//HPD3_DC_HPD_INT_CONTROL</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L</div><div class='add'>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L</div><div class='add'>+//HPD3_DC_HPD_CONTROL</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L</div><div class='add'>+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L</div><div class='add'>+//HPD3_DC_HPD_FAST_TRAIN_CNTL</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L</div><div class='add'>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L</div><div class='add'>+//HPD3_DC_HPD_TOGGLE_FILT_CNTL</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL</div><div class='add'>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hpo_top_dispdec</div><div class='add'>+//HPO_TOP_CLOCK_CONTROL</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_FGCG_REP_DIS__SHIFT                                                        0x17</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_FGCG_REP_DIS_MASK                                                          0x00800000L</div><div class='add'>+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0xFF000000L</div><div class='add'>+//HPO_TOP_HW_CONTROL</div><div class='add'>+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0</div><div class='add'>+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_mapper_dispdec</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL1</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL2</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL3</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL4</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL4__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL4__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+//DP_STREAM_MAPPER_CONTROL5</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL5__DP_STREAM_LINK_TARGET__SHIFT                                               0x0</div><div class='add'>+#define DP_STREAM_MAPPER_CONTROL5__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hpo_dcperfmon_dc_perfmon_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec</div><div class='add'>+//HDMI_LINK_ENC_CONTROL</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT                                                    0x0</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT                                                0x4</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK                                                      0x00000001L</div><div class='add'>+#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK                                                  0x00000010L</div><div class='add'>+//HDMI_LINK_ENC_CLK_CTRL</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT                                                 0x0</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT                                     0x1</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK                                                   0x00000001L</div><div class='add'>+#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK                                       0x00000002L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec</div><div class='add'>+//HDMI_FRL_ENC_CONFIG</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT                                                      0x0</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT                                                 0x1</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT                                               0x2</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT                                          0x10</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT                                          0x14</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT                                          0x18</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT                                          0x1c</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK                                                        0x00000001L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK                                                   0x00000002L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK                                                 0x00000004L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK                                            0x000F0000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK                                            0x00F00000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK                                            0x0F000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK                                            0xF0000000L</div><div class='add'>+//HDMI_FRL_ENC_CONFIG2</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT                                               0x0</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT                                               0xc</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT                                                  0x18</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT                                            0x19</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT                                            0x1a</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT                                         0x1c</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT                                           0x1d</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT                                   0x1e</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK                                                 0x000001FFL</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK                                                 0x001FF000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK                                                    0x01000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK                                              0x02000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK                                              0x0C000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK                                           0x10000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK                                             0x20000000L</div><div class='add'>+#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK                                     0x40000000L</div><div class='add'>+//HDMI_FRL_ENC_METER_BUFFER_STATUS</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT                             0x0</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT                       0x1f</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK                               0x0000007FL</div><div class='add'>+#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK                         0x80000000L</div><div class='add'>+//HDMI_FRL_ENC_MEM_CTRL</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT                                                 0x0</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT                                               0x1</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT                                               0x4</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                             0x8</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK                                                   0x00000001L</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK                                                 0x00000006L</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK                                                 0x00000030L</div><div class='add'>+#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                               0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT                                        0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                                0x4</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                                 0x8</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT                          0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK                                          0x00000001L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                                  0x00000010L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                                   0x00000100L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK                            0x00001000L</div><div class='add'>+//HDMI_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT                        0x0</div><div class='add'>+#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK                          0x00000007L</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT                          0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT                           0x4</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT             0x8</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_UNCOMPRESSED_PIXEL_FORMAT__SHIFT       0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_COMPRESSED_PIXEL_FORMAT__SHIFT         0x10</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT                      0x14</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT             0x18</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT                           0x1c</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK                            0x00000001L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                             0x00000010L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK               0x00000100L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_UNCOMPRESSED_PIXEL_FORMAT_MASK         0x00001000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_COMPRESSED_PIXEL_FORMAT_MASK           0x00010000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK                        0x00100000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK               0x01000000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                             0x30000000L</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT             0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT             0x1</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT             0x2</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT                 0x4</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT                   0xc</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT                   0x10</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT               0x18</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT                      0x1f</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK               0x00000001L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK               0x00000002L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK               0x00000004L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK                   0x000003F0L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK                     0x0000F000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK                     0x001F0000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK                 0x3F000000L</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK                        0x80000000L</div><div class='add'>+//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT                0x0</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT                  0x5</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK                  0x0000001FL</div><div class='add'>+#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK                    0x00000020L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_afmt_afmt_dispdec</div><div class='add'>+//AFMT4_AFMT_ACP</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE__SHIFT                                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                                  0x8</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                                  0x10</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_MASK                                                                    0x00000003L</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK                                                    0x0000FF00L</div><div class='add'>+#define AFMT4_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK                                                    0x00FF0000L</div><div class='add'>+//AFMT4_AFMT_VBI_PACKET_CONTROL</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT                                                 0xd</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK                                                   0x00002000L</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L</div><div class='add'>+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_INFO0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_INFO1</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L</div><div class='add'>+//AFMT4_AFMT_60958_0</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L</div><div class='add'>+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L</div><div class='add'>+//AFMT4_AFMT_60958_1</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L</div><div class='add'>+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_CRC_CONTROL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL1</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL2</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT4_AFMT_RAMP_CONTROL3</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL</div><div class='add'>+//AFMT4_AFMT_60958_2</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L</div><div class='add'>+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_CRC_RESULT</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L</div><div class='add'>+//AFMT4_AFMT_STATUS</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L</div><div class='add'>+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L</div><div class='add'>+//AFMT4_AFMT_AUDIO_PACKET_CONTROL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                               0x1f</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                 0x80000000L</div><div class='add'>+//AFMT4_AFMT_INFOFRAME_CONTROL0</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L</div><div class='add'>+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L</div><div class='add'>+//AFMT4_AFMT_INTERRUPT_STATUS</div><div class='add'>+//AFMT4_AFMT_AUDIO_SRC_CONTROL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L</div><div class='add'>+//AFMT4_AFMT_AUDIO_DBG_DTO_CNTL</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT                                       0x0</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT                                         0x8</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT                                        0xc</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT                                          0x10</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK                                         0x00000007L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK                                           0x00000100L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK                                          0x00007000L</div><div class='add'>+#define AFMT4_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK                                            0x00070000L</div><div class='add'>+//AFMT4_AFMT_MEM_PWR</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L</div><div class='add'>+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dme_dme_dispdec</div><div class='add'>+//DME4_DME_CONTROL</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME4_DME_MEMORY_CONTROL</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG4_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG4_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG4_VPG_MEM_PWR</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG4_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG4_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG4_VPG_MPEG_INFO0</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG4_VPG_MPEG_INFO1</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec</div><div class='add'>+//HDMI_TB_ENC_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT                                                                0x4</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT                                                           0x8</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK                                                              0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK                                                                  0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK                                                             0x00000100L</div><div class='add'>+//HDMI_TB_ENC_PIXEL_FORMAT</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT                                               0x0</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                0x8</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT                                                  0x10</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT                                                        0x18</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK                                                 0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK                                                  0x00000300L</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK                                                    0x00030000L</div><div class='add'>+#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK                                                          0x03000000L</div><div class='add'>+//HDMI_TB_ENC_PACKET_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT                                          0x0</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT                                          0x8</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT                                        0xc</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT                                     0x10</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK                                            0x0000001FL</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK                                            0x00000300L</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK                                          0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK                                       0x00010000L</div><div class='add'>+//HDMI_TB_ENC_ACR_PACKET_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                  0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                  0x1</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                0x4</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                0x8</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                             0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                            0x10</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                        0x1f</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                    0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                    0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                  0x00000030L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                  0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                               0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                              0x00070000L</div><div class='add'>+#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                          0x80000000L</div><div class='add'>+//HDMI_TB_ENC_VBI_PACKET_CONTROL1</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT                                                  0x0</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT                                                  0x1</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT                                                0x4</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT                                                0x5</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT                                      0x6</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT                                                 0x8</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT                                       0x9</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT                                          0xd</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT                                0xe</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                          0x10</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK                                                    0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK                                                    0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK                                                  0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK                                                  0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK                                        0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK                                                   0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK                                         0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK                                            0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK                                            0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK                                  0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                            0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_VBI_PACKET_CONTROL2</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT                                                0x0</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT                                                 0x10</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK                                                  0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK                                                   0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_GC_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT                                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT                                                    0x2</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT                                                     0x4</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK                                                           0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK                                                      0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK                                                       0x00000010L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                        0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                        0x1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT                                     0x2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                              0x3</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                        0x4</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                        0x5</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT                                     0x6</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                              0x7</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                        0x8</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                        0x9</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT                                     0xa</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                              0xb</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                        0xc</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                        0xd</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT                                     0xe</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                              0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                        0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                        0x11</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT                                     0x12</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                              0x13</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                        0x14</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                        0x15</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT                                     0x16</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                              0x17</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                        0x18</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                        0x19</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT                                     0x1a</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                              0x1b</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                        0x1c</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                        0x1d</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT                                     0x1e</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                              0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                          0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                          0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK                                       0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                0x00000008L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                          0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                          0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK                                       0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                0x00000080L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                          0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                          0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK                                       0x00000400L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                0x00000800L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                          0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                          0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK                                       0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                          0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                          0x00020000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK                                       0x00040000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                0x00080000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                          0x00100000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                          0x00200000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK                                       0x00400000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                0x00800000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                          0x01000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                          0x02000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK                                       0x04000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                0x08000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                          0x10000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                          0x20000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK                                       0x40000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT                                        0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT                                        0x1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT                                     0x2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                              0x3</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT                                        0x4</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT                                        0x5</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT                                     0x6</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                              0x7</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT                                       0x8</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT                                       0x9</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT                                    0xa</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                             0xb</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT                                       0xc</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT                                       0xd</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT                                    0xe</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                             0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT                                       0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT                                       0x11</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT                                    0x12</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                             0x13</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT                                       0x14</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT                                       0x15</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT                                    0x16</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                             0x17</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT                                       0x18</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT                                       0x19</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT                                    0x1a</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                             0x1b</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK                                          0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK                                          0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK                                       0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK                                0x00000008L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK                                          0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK                                          0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK                                       0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK                                0x00000080L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK                                         0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK                                         0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK                                      0x00000400L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK                               0x00000800L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK                                         0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK                                         0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK                                      0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK                               0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK                                         0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK                                         0x00020000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK                                      0x00040000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK                               0x00080000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK                                         0x00100000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK                                         0x00200000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK                                      0x00400000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK                               0x00800000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK                                         0x01000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK                                         0x02000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK                                      0x04000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK                               0x08000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                              0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                      0x1</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                              0x2</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                      0x3</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                              0x4</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                      0x5</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                              0x6</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                      0x7</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                              0x8</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                      0x9</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                              0xa</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                      0xb</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                              0xc</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                      0xd</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                              0xe</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                      0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                              0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                      0x11</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                              0x12</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                      0x13</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                             0x14</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                     0x15</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                             0x16</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                     0x17</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                             0x18</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                     0x19</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                             0x1a</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                     0x1b</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                             0x1c</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                     0x1d</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                        0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                0x00000004L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                        0x00000008L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                        0x00000020L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                0x00000040L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                        0x00000080L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                        0x00000200L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                0x00000400L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                        0x00000800L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                        0x00002000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                0x00004000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                        0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                        0x00020000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                0x00040000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                        0x00080000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                               0x00100000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                       0x00200000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                               0x00400000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                       0x00800000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                               0x01000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                       0x02000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                               0x04000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                       0x08000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                               0x10000000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                       0x20000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT                                          0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK                                            0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK                                           0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK                                            0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT                                      0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT                                       0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT                                      0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT                                       0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK                                        0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK                                         0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK                                        0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK                                         0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT                                      0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT                                       0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT                                      0x10</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT                                       0x1f</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK                                        0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK                                         0x00008000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK                                        0x7FFF0000L</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK                                         0x80000000L</div><div class='add'>+//HDMI_TB_ENC_GENERIC_PACKET14_LINE</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT                                          0xf</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK                                           0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK                                            0x00008000L</div><div class='add'>+//HDMI_TB_ENC_DB_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                        0x0</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                        0xc</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                     0xf</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK                                                          0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                          0x00001000L</div><div class='add'>+#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                       0x00008000L</div><div class='add'>+//HDMI_TB_ENC_ACR_32_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                            0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_32_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK                                                              0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_ACR_44_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                            0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_44_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK                                                              0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_ACR_48_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                          0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                            0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_48_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                            0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK                                                              0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_ACR_STATUS_0</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                         0xc</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                           0xFFFFF000L</div><div class='add'>+//HDMI_TB_ENC_ACR_STATUS_1</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                           0x0</div><div class='add'>+#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK                                                             0x000FFFFFL</div><div class='add'>+//HDMI_TB_ENC_BUFFER_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT                              0x0</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT                               0x1</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT                              0x4</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT                           0x8</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT                            0x18</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK                                0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK                                 0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK                                0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK                             0x0000FF00L</div><div class='add'>+#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK                              0x1F000000L</div><div class='add'>+//HDMI_TB_ENC_MEM_CTRL</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT                                                 0x0</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT                                               0x1</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT                                               0x4</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                             0x8</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK                                                   0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK                                                 0x00000006L</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK                                                 0x00000030L</div><div class='add'>+#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                               0x00000300L</div><div class='add'>+//HDMI_TB_ENC_METADATA_PACKET_CONTROL</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                               0x0</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                       0x4</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                               0x8</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                 0x10</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                         0x00000010L</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                 0x00000100L</div><div class='add'>+#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                   0xFFFF0000L</div><div class='add'>+//HDMI_TB_ENC_H_ACTIVE_BLANK</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT                                                      0x0</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT                                                       0x10</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK                                                        0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK                                                         0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_HC_ACTIVE_BLANK</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT                                                    0x0</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT                                                     0x10</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK                                                      0x00007FFFL</div><div class='add'>+#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK                                                       0x7FFF0000L</div><div class='add'>+//HDMI_TB_ENC_CRC_CNTL</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT                                                              0x0</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT                                                         0x1</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT                                                            0x8</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT                                                         0xa</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT                                                    0x10</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT                                                  0x11</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK                                                                0x00000001L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK                                                           0x00000002L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK                                                              0x00000300L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK                                                           0x00000C00L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK                                                      0x00010000L</div><div class='add'>+#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK                                                    0x00060000L</div><div class='add'>+//HDMI_TB_ENC_CRC_RESULT_0</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT                                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT                                                         0x10</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK                                                           0x0000FFFFL</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK                                                           0xFFFF0000L</div><div class='add'>+//HDMI_TB_ENC_MODE</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT                                                             0x0</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT                                                       0x8</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK                                                               0x00000003L</div><div class='add'>+#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK                                                         0x00000100L</div><div class='add'>+//HDMI_TB_ENC_INPUT_FIFO_STATUS</div><div class='add'>+#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT                                                0x0</div><div class='add'>+#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK                                                  0x00000001L</div><div class='add'>+//HDMI_TB_ENC_CRC_RESULT_1</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT                                                         0x0</div><div class='add'>+#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK                                                           0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_dispdec</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_apg_apg_dispdec</div><div class='add'>+//APG0_APG_CONTROL</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG0_APG_CONTROL2</div><div class='add'>+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG0_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG0_APG_PACKET_CONTROL</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG0_APG_DBG_ACP</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT                                                             0x0</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                             0x8</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                             0x10</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT                                                         0x18</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK                                                               0x00000003L</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK                                               0x0000FF00L</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK                                               0x00FF0000L</div><div class='add'>+#define APG0_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK                                                           0x01000000L</div><div class='add'>+//APG0_APG_AUDIO_INFO</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                            0x0</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AUDIO_INFO_CT__SHIFT                                                         0x10</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT__SHIFT                                                        0x14</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER__SHIFT                                                    0x19</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                              0x000000FFL</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AUDIO_INFO_CT_MASK                                                           0x000F0000L</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT_MASK                                                          0x01F00000L</div><div class='add'>+#define APG0_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER_MASK                                                      0x7E000000L</div><div class='add'>+//APG0_APG_DBG_AUDIO_INFO</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT                                                 0x0</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT                                                 0x8</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT                                                0xb</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT                                             0xf</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT                                             0x10</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK                                                   0x000000FFL</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK                                                   0x00000700L</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK                                                  0x00007800L</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK                                               0x00008000L</div><div class='add'>+#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK                                               0x00030000L</div><div class='add'>+//APG0_APG_DBG_60958_0</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT                                                       0x0</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT                                                       0x1</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT                                                       0x2</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT                                                       0x3</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT                                                    0x6</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT                                           0x8</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT                                           0x10</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT                                        0x14</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT                                      0x18</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT                                          0x1c</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK                                                         0x00000001L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK                                                         0x00000002L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK                                                         0x00000004L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK                                                         0x00000038L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK                                                      0x000000C0L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK                                             0x0000FF00L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK                                             0x000F0000L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK                                          0x00F00000L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK                                        0x0F000000L</div><div class='add'>+#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK                                            0x30000000L</div><div class='add'>+//APG0_APG_DBG_60958_1</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT                                             0x0</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                             0x4</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT                                                      0x10</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT                                        0x14</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK                                               0x0000000FL</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                               0x000000F0L</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK                                                        0x00010000L</div><div class='add'>+#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK                                          0x00F00000L</div><div class='add'>+//APG0_APG_DBG_60958_2</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT                                        0x0</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT                                        0x4</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT                                        0x8</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT                                        0xc</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT                                        0x10</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT                                        0x14</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK                                          0x0000000FL</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK                                          0x000000F0L</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK                                          0x00000F00L</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK                                          0x0000F000L</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK                                          0x000F0000L</div><div class='add'>+#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK                                          0x00F00000L</div><div class='add'>+//APG0_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG0_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG0_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG0_APG_DBG_RAMP_CONTROL0</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT                                             0x1f</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK                                               0x80000000L</div><div class='add'>+//APG0_APG_DBG_RAMP_CONTROL1</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG0_APG_DBG_RAMP_CONTROL2</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG0_APG_DBG_RAMP_CONTROL3</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG0_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG0_APG_STATUS</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG0_APG_STATUS2</div><div class='add'>+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG0_APG_DBG_AUDIO_DTO_CNTL</div><div class='add'>+#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT                                            0x8</div><div class='add'>+#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT                                           0xc</div><div class='add'>+#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT                                             0x10</div><div class='add'>+#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK                                              0x00000100L</div><div class='add'>+#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK                                             0x00007000L</div><div class='add'>+#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK                                               0x00070000L</div><div class='add'>+//APG0_APG_MEM_PWR</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG0_APG_SPARE</div><div class='add'>+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_dme_dme_dispdec</div><div class='add'>+//DME5_DME_CONTROL</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME5_DME_MEMORY_CONTROL</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc0_vpg_vpg_dispdec</div><div class='add'>+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG5_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG5_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG5_VPG_MEM_PWR</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG5_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG5_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG5_VPG_MPEG_INFO0</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG5_VPG_MPEG_INFO1</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc0_dispdec</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION__SHIFT                               0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE_MASK                                      0x00003FFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION_MASK                                 0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE__SHIFT                                0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE_MASK                                  0x00010000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL__SHIFT                              0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT              0x14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL_MASK                                0x0003FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                0x00100000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT                                  0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT                                         0x14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT                                            0x18</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT                                         0x1c</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK                                       0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK                                    0x00010000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK                                           0x00100000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK                                              0x01000000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK                                           0x10000000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT                                   0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT                                          0x14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT                                             0x18</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT                                          0x1c</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK                                        0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK                                     0x00010000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK                                            0x00100000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK                                               0x01000000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK                                            0x10000000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT                                    0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK                                      0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK                                  0x00000001L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK                              0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT                                          0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK                                      0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK                                            0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK                                       0x00000001L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT                            0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT                         0x10</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT                           0x14</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT                                 0x1c</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK                              0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK                           0x00010000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK                             0x0FF00000L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK                                   0x10000000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT                                   0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK                                     0x00000010L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_dispdec</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_apg_apg_dispdec</div><div class='add'>+//APG1_APG_CONTROL</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG1_APG_CONTROL2</div><div class='add'>+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG1_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG1_APG_PACKET_CONTROL</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG1_APG_DBG_ACP</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT                                                             0x0</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                             0x8</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                             0x10</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT                                                         0x18</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK                                                               0x00000003L</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK                                               0x0000FF00L</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK                                               0x00FF0000L</div><div class='add'>+#define APG1_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK                                                           0x01000000L</div><div class='add'>+//APG1_APG_AUDIO_INFO</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                            0x0</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AUDIO_INFO_CT__SHIFT                                                         0x10</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT__SHIFT                                                        0x14</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER__SHIFT                                                    0x19</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                              0x000000FFL</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AUDIO_INFO_CT_MASK                                                           0x000F0000L</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT_MASK                                                          0x01F00000L</div><div class='add'>+#define APG1_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER_MASK                                                      0x7E000000L</div><div class='add'>+//APG1_APG_DBG_AUDIO_INFO</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT                                                 0x0</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT                                                 0x8</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT                                                0xb</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT                                             0xf</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT                                             0x10</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK                                                   0x000000FFL</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK                                                   0x00000700L</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK                                                  0x00007800L</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK                                               0x00008000L</div><div class='add'>+#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK                                               0x00030000L</div><div class='add'>+//APG1_APG_DBG_60958_0</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT                                                       0x0</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT                                                       0x1</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT                                                       0x2</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT                                                       0x3</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT                                                    0x6</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT                                           0x8</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT                                           0x10</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT                                        0x14</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT                                      0x18</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT                                          0x1c</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK                                                         0x00000001L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK                                                         0x00000002L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK                                                         0x00000004L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK                                                         0x00000038L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK                                                      0x000000C0L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK                                             0x0000FF00L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK                                             0x000F0000L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK                                          0x00F00000L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK                                        0x0F000000L</div><div class='add'>+#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK                                            0x30000000L</div><div class='add'>+//APG1_APG_DBG_60958_1</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT                                             0x0</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                             0x4</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT                                                      0x10</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT                                        0x14</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK                                               0x0000000FL</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                               0x000000F0L</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK                                                        0x00010000L</div><div class='add'>+#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK                                          0x00F00000L</div><div class='add'>+//APG1_APG_DBG_60958_2</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT                                        0x0</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT                                        0x4</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT                                        0x8</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT                                        0xc</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT                                        0x10</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT                                        0x14</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK                                          0x0000000FL</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK                                          0x000000F0L</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK                                          0x00000F00L</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK                                          0x0000F000L</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK                                          0x000F0000L</div><div class='add'>+#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK                                          0x00F00000L</div><div class='add'>+//APG1_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG1_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG1_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG1_APG_DBG_RAMP_CONTROL0</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT                                             0x1f</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK                                               0x80000000L</div><div class='add'>+//APG1_APG_DBG_RAMP_CONTROL1</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG1_APG_DBG_RAMP_CONTROL2</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG1_APG_DBG_RAMP_CONTROL3</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG1_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG1_APG_STATUS</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG1_APG_STATUS2</div><div class='add'>+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG1_APG_DBG_AUDIO_DTO_CNTL</div><div class='add'>+#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT                                            0x8</div><div class='add'>+#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT                                           0xc</div><div class='add'>+#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT                                             0x10</div><div class='add'>+#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK                                              0x00000100L</div><div class='add'>+#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK                                             0x00007000L</div><div class='add'>+#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK                                               0x00070000L</div><div class='add'>+//APG1_APG_MEM_PWR</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG1_APG_SPARE</div><div class='add'>+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_dme_dme_dispdec</div><div class='add'>+//DME6_DME_CONTROL</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME6_DME_MEMORY_CONTROL</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc1_vpg_vpg_dispdec</div><div class='add'>+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG6_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG6_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG6_VPG_MEM_PWR</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG6_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG6_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG6_VPG_MPEG_INFO0</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG6_VPG_MPEG_INFO1</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc1_dispdec</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION__SHIFT                               0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE_MASK                                      0x00003FFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION_MASK                                 0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE__SHIFT                                0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE_MASK                                  0x00010000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL__SHIFT                              0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT              0x14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL_MASK                                0x0003FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                0x00100000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT                                  0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT                                         0x14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT                                            0x18</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT                                         0x1c</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK                                       0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK                                    0x00010000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK                                           0x00100000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK                                              0x01000000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK                                           0x10000000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT                                   0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT                                          0x14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT                                             0x18</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT                                          0x1c</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK                                        0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK                                     0x00010000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK                                            0x00100000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK                                               0x01000000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK                                            0x10000000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT                                    0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK                                      0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK                                  0x00000001L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK                              0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT                                          0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK                                      0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK                                            0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK                                       0x00000001L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT                            0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT                         0x10</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT                           0x14</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT                                 0x1c</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK                              0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK                           0x00010000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK                             0x0FF00000L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK                                   0x10000000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT                                   0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK                                     0x00000010L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_dispdec</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_apg_apg_dispdec</div><div class='add'>+//APG2_APG_CONTROL</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG2_APG_CONTROL2</div><div class='add'>+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG2_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG2_APG_PACKET_CONTROL</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG2_APG_DBG_ACP</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT                                                             0x0</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                             0x8</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                             0x10</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT                                                         0x18</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK                                                               0x00000003L</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK                                               0x0000FF00L</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK                                               0x00FF0000L</div><div class='add'>+#define APG2_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK                                                           0x01000000L</div><div class='add'>+//APG2_APG_AUDIO_INFO</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                            0x0</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AUDIO_INFO_CT__SHIFT                                                         0x10</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT__SHIFT                                                        0x14</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER__SHIFT                                                    0x19</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                              0x000000FFL</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AUDIO_INFO_CT_MASK                                                           0x000F0000L</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT_MASK                                                          0x01F00000L</div><div class='add'>+#define APG2_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER_MASK                                                      0x7E000000L</div><div class='add'>+//APG2_APG_DBG_AUDIO_INFO</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT                                                 0x0</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT                                                 0x8</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT                                                0xb</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT                                             0xf</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT                                             0x10</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK                                                   0x000000FFL</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK                                                   0x00000700L</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK                                                  0x00007800L</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK                                               0x00008000L</div><div class='add'>+#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK                                               0x00030000L</div><div class='add'>+//APG2_APG_DBG_60958_0</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT                                                       0x0</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT                                                       0x1</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT                                                       0x2</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT                                                       0x3</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT                                                    0x6</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT                                           0x8</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT                                           0x10</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT                                        0x14</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT                                      0x18</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT                                          0x1c</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK                                                         0x00000001L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK                                                         0x00000002L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK                                                         0x00000004L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK                                                         0x00000038L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK                                                      0x000000C0L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK                                             0x0000FF00L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK                                             0x000F0000L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK                                          0x00F00000L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK                                        0x0F000000L</div><div class='add'>+#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK                                            0x30000000L</div><div class='add'>+//APG2_APG_DBG_60958_1</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT                                             0x0</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                             0x4</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT                                                      0x10</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT                                        0x14</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK                                               0x0000000FL</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                               0x000000F0L</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK                                                        0x00010000L</div><div class='add'>+#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK                                          0x00F00000L</div><div class='add'>+//APG2_APG_DBG_60958_2</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT                                        0x0</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT                                        0x4</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT                                        0x8</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT                                        0xc</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT                                        0x10</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT                                        0x14</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK                                          0x0000000FL</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK                                          0x000000F0L</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK                                          0x00000F00L</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK                                          0x0000F000L</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK                                          0x000F0000L</div><div class='add'>+#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK                                          0x00F00000L</div><div class='add'>+//APG2_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG2_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG2_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG2_APG_DBG_RAMP_CONTROL0</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT                                             0x1f</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK                                               0x80000000L</div><div class='add'>+//APG2_APG_DBG_RAMP_CONTROL1</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG2_APG_DBG_RAMP_CONTROL2</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG2_APG_DBG_RAMP_CONTROL3</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG2_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG2_APG_STATUS</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG2_APG_STATUS2</div><div class='add'>+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG2_APG_DBG_AUDIO_DTO_CNTL</div><div class='add'>+#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT                                            0x8</div><div class='add'>+#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT                                           0xc</div><div class='add'>+#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT                                             0x10</div><div class='add'>+#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK                                              0x00000100L</div><div class='add'>+#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK                                             0x00007000L</div><div class='add'>+#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK                                               0x00070000L</div><div class='add'>+//APG2_APG_MEM_PWR</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG2_APG_SPARE</div><div class='add'>+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_dme_dme_dispdec</div><div class='add'>+//DME7_DME_CONTROL</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME7_DME_MEMORY_CONTROL</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc2_vpg_vpg_dispdec</div><div class='add'>+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG7_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG7_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG7_VPG_MEM_PWR</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG7_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG7_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG7_VPG_MPEG_INFO0</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG7_VPG_MPEG_INFO1</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc2_dispdec</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION__SHIFT                               0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE_MASK                                      0x00003FFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION_MASK                                 0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE__SHIFT                                0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE_MASK                                  0x00010000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL__SHIFT                              0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT              0x14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL_MASK                                0x0003FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                0x00100000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT                                  0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT                                         0x14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT                                            0x18</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT                                         0x1c</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK                                       0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK                                    0x00010000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK                                           0x00100000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK                                              0x01000000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK                                           0x10000000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT                                   0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT                                          0x14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT                                             0x18</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT                                          0x1c</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK                                        0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK                                     0x00010000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK                                            0x00100000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK                                               0x01000000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK                                            0x10000000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT                                    0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK                                      0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK                                  0x00000001L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK                              0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT                                          0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK                                      0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK                                            0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK                                       0x00000001L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT                            0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT                         0x10</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT                           0x14</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT                                 0x1c</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK                              0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK                           0x00010000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK                             0x0FF00000L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK                                   0x10000000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT                                   0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK                                     0x00000010L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_dispdec</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT      0x10</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK        0x001F0000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L</div><div class='add'>+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0</div><div class='add'>+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_apg_apg_dispdec</div><div class='add'>+//APG3_APG_CONTROL</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L</div><div class='add'>+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L</div><div class='add'>+//APG3_APG_CONTROL2</div><div class='add'>+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18</div><div class='add'>+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L</div><div class='add'>+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L</div><div class='add'>+//APG3_APG_DBG_GEN_CONTROL</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L</div><div class='add'>+#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L</div><div class='add'>+//APG3_APG_PACKET_CONTROL</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT                                                       0x0</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT                                                        0x1</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK                                                         0x00000001L</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK                                                          0x00000002L</div><div class='add'>+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L</div><div class='add'>+//APG3_APG_DBG_ACP</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT                                                             0x0</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT                                             0x8</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT                                             0x10</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT                                                         0x18</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK                                                               0x00000003L</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK                                               0x0000FF00L</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK                                               0x00FF0000L</div><div class='add'>+#define APG3_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK                                                           0x01000000L</div><div class='add'>+//APG3_APG_AUDIO_INFO</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                            0x0</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AUDIO_INFO_CT__SHIFT                                                         0x10</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT__SHIFT                                                        0x14</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER__SHIFT                                                    0x19</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                              0x000000FFL</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AUDIO_INFO_CT_MASK                                                           0x000F0000L</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AUDIO_INFO_CXT_MASK                                                          0x01F00000L</div><div class='add'>+#define APG3_APG_AUDIO_INFO__APG_AIP_VERSION_NUMBER_MASK                                                      0x7E000000L</div><div class='add'>+//APG3_APG_DBG_AUDIO_INFO</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT                                                 0x0</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT                                                 0x8</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT                                                0xb</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT                                             0xf</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT                                             0x10</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK                                                   0x000000FFL</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK                                                   0x00000700L</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK                                                  0x00007800L</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK                                               0x00008000L</div><div class='add'>+#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK                                               0x00030000L</div><div class='add'>+//APG3_APG_DBG_60958_0</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT                                                       0x0</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT                                                       0x1</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT                                                       0x2</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT                                                       0x3</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT                                                    0x6</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT                                           0x8</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT                                           0x10</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT                                        0x14</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT                                      0x18</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT                                          0x1c</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK                                                         0x00000001L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK                                                         0x00000002L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK                                                         0x00000004L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK                                                         0x00000038L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK                                                      0x000000C0L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK                                             0x0000FF00L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK                                             0x000F0000L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK                                          0x00F00000L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK                                        0x0F000000L</div><div class='add'>+#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK                                            0x30000000L</div><div class='add'>+//APG3_APG_DBG_60958_1</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT                                             0x0</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                             0x4</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT                                                      0x10</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT                                        0x14</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK                                               0x0000000FL</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                               0x000000F0L</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK                                                        0x00010000L</div><div class='add'>+#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK                                          0x00F00000L</div><div class='add'>+//APG3_APG_DBG_60958_2</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT                                        0x0</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT                                        0x4</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT                                        0x8</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT                                        0xc</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT                                        0x10</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT                                        0x14</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK                                          0x0000000FL</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK                                          0x000000F0L</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK                                          0x00000F00L</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK                                          0x0000F000L</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK                                          0x000F0000L</div><div class='add'>+#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK                                          0x00F00000L</div><div class='add'>+//APG3_APG_AUDIO_CRC_CONTROL</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L</div><div class='add'>+//APG3_APG_AUDIO_CRC_CONTROL2</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0</div><div class='add'>+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL</div><div class='add'>+//APG3_APG_AUDIO_CRC_RESULT</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L</div><div class='add'>+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L</div><div class='add'>+//APG3_APG_DBG_RAMP_CONTROL0</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT                                             0x1f</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK                                               0x80000000L</div><div class='add'>+//APG3_APG_DBG_RAMP_CONTROL1</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG3_APG_DBG_RAMP_CONTROL2</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG3_APG_DBG_RAMP_CONTROL3</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT                                             0x0</div><div class='add'>+#define APG3_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK                                               0x00FFFFFFL</div><div class='add'>+//APG3_APG_STATUS</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4</div><div class='add'>+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L</div><div class='add'>+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L</div><div class='add'>+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L</div><div class='add'>+//APG3_APG_STATUS2</div><div class='add'>+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0</div><div class='add'>+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L</div><div class='add'>+//APG3_APG_DBG_AUDIO_DTO_CNTL</div><div class='add'>+#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT                                            0x8</div><div class='add'>+#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT                                           0xc</div><div class='add'>+#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT                                             0x10</div><div class='add'>+#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK                                              0x00000100L</div><div class='add'>+#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK                                             0x00007000L</div><div class='add'>+#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK                                               0x00070000L</div><div class='add'>+//APG3_APG_MEM_PWR</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L</div><div class='add'>+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L</div><div class='add'>+//APG3_APG_SPARE</div><div class='add'>+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0</div><div class='add'>+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_dme_dme_dispdec</div><div class='add'>+//DME8_DME_CONTROL</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L</div><div class='add'>+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L</div><div class='add'>+//DME8_DME_MEMORY_CONTROL</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L</div><div class='add'>+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_stream_enc3_vpg_vpg_dispdec</div><div class='add'>+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL</div><div class='add'>+//VPG8_VPG_GENERIC_PACKET_DATA</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L</div><div class='add'>+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L</div><div class='add'>+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L</div><div class='add'>+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L</div><div class='add'>+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L</div><div class='add'>+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L</div><div class='add'>+//VPG8_VPG_GENERIC_STATUS</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L</div><div class='add'>+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L</div><div class='add'>+//VPG8_VPG_MEM_PWR</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L</div><div class='add'>+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L</div><div class='add'>+//VPG8_VPG_ISRC1_2_ACCESS_CTRL</div><div class='add'>+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0</div><div class='add'>+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL</div><div class='add'>+//VPG8_VPG_ISRC1_2_DATA</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L</div><div class='add'>+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L</div><div class='add'>+//VPG8_VPG_MPEG_INFO0</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L</div><div class='add'>+//VPG8_VPG_MPEG_INFO1</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L</div><div class='add'>+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_sym32_enc3_dispdec</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION__SHIFT                               0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING__SDP_IDLE_FRAME_SIZE_MASK                                      0x00003FFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING__SDP_FRAME_START_LOCATION_MASK                                 0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0__ATP_AFREQ_LOWER_MASK                                     0xFFFFFFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE__SHIFT                                0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_UPPER_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1__ATP_AFREQ_OVERRIDE_MASK                                  0x00010000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL__SHIFT                              0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT              0x14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__IDLE_BS_INTERVAL_MASK                                0x0003FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL__BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK                0x00100000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK                              0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT                                       0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK                                         0x0000FFFFL</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT                               0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT                                0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK                                 0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK                                  0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT                                  0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT                                         0x14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT                                            0x18</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT                                         0x1c</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK                                       0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK                                    0x00010000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK                                           0x00100000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK                                              0x01000000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK                                           0x10000000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT                                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT                                   0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT                                          0x14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT                                             0x18</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT                                          0x1c</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK                                        0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK                                     0x00010000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK                                            0x00100000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK                                               0x01000000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK                                            0x10000000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT                                   0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT                                    0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK                                     0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK                                      0xFFFF0000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK                                  0x00000001L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT                                  0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT                            0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK                                    0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK                              0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT                                    0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT                            0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT                                          0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK                                      0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK                              0x00000010L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK                                            0x0000FF00L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT                                     0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK                                       0x00000001L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT                            0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT                         0x10</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT                           0x14</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT                                 0x1c</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK                              0x0000FFFFL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK                           0x00010000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK                             0x0FF00000L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK                                   0x10000000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT                                0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT                                   0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK                                  0x00000001L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK                                     0x00000010L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L</div><div class='add'>+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0</div><div class='add'>+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc0_dispdec</div><div class='add'>+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L</div><div class='add'>+//DP_LINK_ENC0_DP_LINK_ENC_SPARE</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0</div><div class='add'>+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym320_dispdec</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT                                              0xa</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT                                         0xd</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK                                                0x00000400L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK                                           0x00002000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT                                          0x12</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT                                                0x14</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK                                            0x000C0000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK                                                  0x00100000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE__SHIFT                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE__SHIFT                            0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE_MASK                               0x0000FFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE_MASK                              0xFFFF0000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT                           0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK                             0x00000030L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT                              0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT                                    0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT                                     0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK                                    0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK                                0x00000FF0L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK                                      0x0000F000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK                                       0x00FF0000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK                                      0x0003FFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD__SHIFT                                 0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD_MASK                                      0x00000FFFL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD_MASK                                   0x3FFFF000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT                                         0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK                                           0x0000007FL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK                                      0x000FFF00L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT                                 0x9</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK                                   0x00000200L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN__SHIFT                       0x4</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN__SHIFT                        0x5</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL_MASK                                   0x0000000FL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN_MASK                         0x00000010L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN_MASK                          0x00000020L</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc0_sym32_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc1_dispdec</div><div class='add'>+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L</div><div class='add'>+//DP_LINK_ENC1_DP_LINK_ENC_SPARE</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0</div><div class='add'>+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym321_dispdec</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT                                              0xa</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT                                         0xd</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK                                                0x00000400L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK                                           0x00002000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT                                          0x12</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT                                                0x14</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK                                            0x000C0000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK                                                  0x00100000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE__SHIFT                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE__SHIFT                            0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE_MASK                               0x0000FFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE_MASK                              0xFFFF0000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT                           0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK                             0x00000030L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT                              0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT                                    0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT                                     0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK                                    0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK                                0x00000FF0L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK                                      0x0000F000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK                                       0x00FF0000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK                                      0x0003FFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD__SHIFT                                 0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD_MASK                                      0x00000FFFL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD_MASK                                   0x3FFFF000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT                                         0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK                                           0x0000007FL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK                                      0x000FFF00L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT                                 0x9</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK                                   0x00000200L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN__SHIFT                       0x4</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN__SHIFT                        0x5</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL_MASK                                   0x0000000FL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN_MASK                         0x00000010L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN_MASK                          0x00000020L</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc1_sym32_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc2_dispdec</div><div class='add'>+//DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0</div><div class='add'>+#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4</div><div class='add'>+#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L</div><div class='add'>+#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L</div><div class='add'>+//DP_LINK_ENC2_DP_LINK_ENC_SPARE</div><div class='add'>+#define DP_LINK_ENC2_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0</div><div class='add'>+#define DP_LINK_ENC2_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym322_dispdec</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT                                              0xa</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT                                         0xd</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK                                                0x00000400L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK                                           0x00002000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT                                          0x12</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT                                                0x14</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK                                            0x000C0000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK                                                  0x00100000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE__SHIFT                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE__SHIFT                            0x10</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE_MASK                               0x0000FFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE_MASK                              0xFFFF0000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT                           0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK                             0x00000030L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT                              0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT                                    0xc</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT                                     0x10</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK                                    0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK                                0x00000FF0L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK                                      0x0000F000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK                                       0x00FF0000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK                                      0x0003FFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD__SHIFT                                 0xc</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD_MASK                                      0x00000FFFL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD_MASK                                   0x3FFFF000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT                                         0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK                                           0x0000007FL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK                                      0x000FFF00L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT                                 0x9</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK                                   0x00000200L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN__SHIFT                       0x4</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN__SHIFT                        0x5</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL_MASK                                   0x0000000FL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN_MASK                         0x00000010L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN_MASK                          0x00000020L</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc2_sym32_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc3_dispdec</div><div class='add'>+//DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL</div><div class='add'>+#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0</div><div class='add'>+#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4</div><div class='add'>+#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L</div><div class='add'>+#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L</div><div class='add'>+//DP_LINK_ENC3_DP_LINK_ENC_SPARE</div><div class='add'>+#define DP_LINK_ENC3_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0</div><div class='add'>+#define DP_LINK_ENC3_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_dphy_sym323_dispdec</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT                                              0xa</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT                                   0xc</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT                                         0xd</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK                                                0x00000400L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK                                     0x00001000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK                                           0x00002000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT                                          0x12</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT                                                0x14</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK                                            0x000C0000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK                                                  0x00100000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE__SHIFT                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE__SHIFT                            0x10</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_EN_VALUE_MASK                               0x0000FFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0__LVP_ENCRYPT_DIS_VALUE_MASK                              0xFFFF0000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y__SHIFT                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X__SHIFT                                   0x19</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5__STREAM_VC_RATE_X_MASK                                     0xFE000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE__SHIFT                                        0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT__SHIFT                                           0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5__SAT_STREAM_SOURCE_MASK                                          0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5__SAT_SLOT_COUNT_MASK                                             0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_STREAM_SOURCE_MASK                                   0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5__SAT_SLOT_COUNT_MASK                                      0x00007F00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT                                      0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT                           0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK                                        0x00000001L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK                             0x00000030L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT                                                   0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK                                                     0x007FFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT                              0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT                                    0xc</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT                                     0x10</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK                                    0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK                                0x00000FF0L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK                                      0x0000F000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK                                       0x00FF0000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK                                      0x0003FFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD__SHIFT                                 0xc</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__LFPS_PERIOD_MASK                                      0x00000FFFL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1__CDS_END_PERIOD_MASK                                   0x3FFFF000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT                                         0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT                                    0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK                                           0x0000007FL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK                                      0x000FFF00L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT                                        0x8</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT                                 0x9</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK                                          0x00000100L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK                                   0x00000200L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN__SHIFT                       0x4</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN__SHIFT                        0x5</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__FRAME_INTERVAL_MASK                                   0x0000000FL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_SLEEP_EN_MASK                         0x00000010L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0__PARTIAL_PACKETS_WAKE_EN_MASK                          0x00000020L</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT                                  0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK                                    0x0000FFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT                                 0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK                                   0xFFFFFFFFL</div><div class='add'>+//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT                           0x0</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT                            0x1</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT                          0x2</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT                           0x3</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK                             0x00000001L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK                              0x00000002L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK                            0x00000004L</div><div class='add'>+#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK                             0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc3_sym32_hdcp2_hdcp2_dispdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dlpc_dlpc_dispdec</div><div class='add'>+//DLPC_ENABLE</div><div class='add'>+#define DLPC_ENABLE__DLPC_EN__SHIFT                                                                           0x0</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_EN__SHIFT                                                                  0x4</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_CLR__SHIFT                                                                 0x5</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_STATUS__SHIFT                                                              0x6</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_EN__SHIFT                                                             0x8</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_CLR__SHIFT                                                            0x9</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_STATUS__SHIFT                                                         0xa</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_EN__SHIFT                                                     0xc</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_CLR__SHIFT                                                    0xd</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_STATUS__SHIFT                                                 0xe</div><div class='add'>+#define DLPC_ENABLE__DLPC_EN_MASK                                                                             0x00000001L</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_EN_MASK                                                                    0x00000010L</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_CLR_MASK                                                                   0x00000020L</div><div class='add'>+#define DLPC_ENABLE__PWRUP_TRIGGER_STATUS_MASK                                                                0x00000040L</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_EN_MASK                                                               0x00000100L</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_CLR_MASK                                                              0x00000200L</div><div class='add'>+#define DLPC_ENABLE__OTG_RESYNC_TRIGGER_STATUS_MASK                                                           0x00000400L</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_EN_MASK                                                       0x00001000L</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_CLR_MASK                                                      0x00002000L</div><div class='add'>+#define DLPC_ENABLE__DCN_ZSC_LONO_PWRUP_TRIGGER_STATUS_MASK                                                   0x00004000L</div><div class='add'>+//DLPC_CURRENT_COUNT</div><div class='add'>+#define DLPC_CURRENT_COUNT__VALUE__SHIFT                                                                      0x0</div><div class='add'>+#define DLPC_CURRENT_COUNT__VALUE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+//DLPC_OPTC_SNAPSHOT</div><div class='add'>+#define DLPC_OPTC_SNAPSHOT__VALUE__SHIFT                                                                      0x0</div><div class='add'>+#define DLPC_OPTC_SNAPSHOT__VALUE_MASK                                                                        0xFFFFFFFFL</div><div class='add'>+//DLPC_PWRUP</div><div class='add'>+#define DLPC_PWRUP__VALUE__SHIFT                                                                              0x0</div><div class='add'>+#define DLPC_PWRUP__VALUE_MASK                                                                                0xFFFFFFFFL</div><div class='add'>+//DLPC_OTG_RESYNC</div><div class='add'>+#define DLPC_OTG_RESYNC__VALUE__SHIFT                                                                         0x0</div><div class='add'>+#define DLPC_OTG_RESYNC__VALUE_MASK                                                                           0xFFFFFFFFL</div><div class='add'>+//DLPC_DCN_ZSC_LONO_PWRUP</div><div class='add'>+#define DLPC_DCN_ZSC_LONO_PWRUP__VALUE__SHIFT                                                                 0x0</div><div class='add'>+#define DLPC_DCN_ZSC_LONO_PWRUP__VALUE_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//DLPC_SPARE</div><div class='add'>+#define DLPC_SPARE__SPARE__SHIFT                                                                              0x0</div><div class='add'>+#define DLPC_SPARE__SPARE_MASK                                                                                0xFFFFFFFFL</div><div class='add'>+//DLPC_COUNTER_INIT_VALUE</div><div class='add'>+#define DLPC_COUNTER_INIT_VALUE__DLPC_COUNTER_INIT_VALUE__SHIFT                                               0x0</div><div class='add'>+#define DLPC_COUNTER_INIT_VALUE__DLPC_COUNTER_INIT_VALUE_MASK                                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr0_dispdec</div><div class='add'>+//DPCSSYS_CR0_DPCSSYS_CR_ADDR</div><div class='add'>+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL</div><div class='add'>+//DPCSSYS_CR0_DPCSSYS_CR_DATA</div><div class='add'>+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr1_dispdec</div><div class='add'>+//DPCSSYS_CR1_DPCSSYS_CR_ADDR</div><div class='add'>+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL</div><div class='add'>+//DPCSSYS_CR1_DPCSSYS_CR_DATA</div><div class='add'>+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr2_dispdec</div><div class='add'>+//DPCSSYS_CR2_DPCSSYS_CR_ADDR</div><div class='add'>+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL</div><div class='add'>+//DPCSSYS_CR2_DPCSSYS_CR_DATA</div><div class='add'>+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcssys_cr3_dispdec</div><div class='add'>+//DPCSSYS_CR3_DPCSSYS_CR_ADDR</div><div class='add'>+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL</div><div class='add'>+//DPCSSYS_CR3_DPCSSYS_CR_DATA</div><div class='add'>+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0</div><div class='add'>+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx0_dispdec</div><div class='add'>+//RDPCSTX0_RDPCSTX_CNTL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE__SHIFT                                          0x3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY__SHIFT                                                   0xb</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB__SHIFT                                            0x1b</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_MASK                                                   0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE_MASK                                            0x00000008L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY_MASK                                                     0x00000800L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB_MASK                                              0x08000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_CLOCK_CNTL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS_MASK                                         0x01000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED__SHIFT                                     0x19</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK__SHIFT                                0x1a</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK                                       0x02000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK_MASK                                  0x04000000L</div><div class='add'>+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L</div><div class='add'>+//RDPCSTX0_RDPCS_TX_CR_ADDR</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX0_RDPCS_TX_CR_DATA</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX0_RDPCS_TX_SRAM_CNTL</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG__SHIFT                                            0x10</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG_MASK                                              0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_SCRATCH0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_SPARE</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_CNTL2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL</div><div class='add'>+//RDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE</div><div class='add'>+#define RDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE_MASK                                      0xFFFFFFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN__SHIFT                                0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL__SHIFT                          0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR__SHIFT                           0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN_MASK                                  0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL_MASK                            0x00000006L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR_MASK                             0x00000010L</div><div class='add'>+//RDPCSTX0_RDPCSTX_CNTL4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY__SHIFT                                              0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY__SHIFT                                            0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY_MASK                                                0x000003FFL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY_MASK                                              0x000FFC00L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY_MASK                                               0x3FF00000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00000E00L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN__SHIFT                                       0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN_MASK                                         0x00001000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL5</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL9</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL13</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN__SHIFT                                        0x4</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN__SHIFT                                        0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN__SHIFT                                        0xa</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN__SHIFT                                        0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN__SHIFT                                        0xd</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN__SHIFT                                        0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN_MASK                                          0x00000030L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN_MASK                                          0x000000C0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN_MASK                                          0x00000300L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN_MASK                                          0x00000C00L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN_MASK                                          0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN_MASK                                          0x00002000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN_MASK                                          0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_FUSE0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_FUSE1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_FUSE2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_FUSE3</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL__SHIFT                                            0x1a</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL_MASK                                              0x1C000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L</div><div class='add'>+//RDPCSTX0_RDPCSTX_SCRATCH1</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_SCRATCH2</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL15</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP__SHIFT                                   0xd</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP__SHIFT                                   0xe</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP__SHIFT                                   0xf</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN__SHIFT                                                 0x1e</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP_MASK                                     0x00001000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP_MASK                                     0x00002000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP_MASK                                     0x00004000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP_MASK                                     0x00008000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL_MASK                                                 0x3F000000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN_MASK                                                   0x40000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL16</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L</div><div class='add'>+//RDPCSTX0_RDPCSTX_PHY_CNTL17</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L</div><div class='add'>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L</div><div class='add'>+//RDPCSTX0_RDPCS_CNTL3</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L</div><div class='add'>+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L</div><div class='add'>+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL</div><div class='add'>+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx1_dispdec</div><div class='add'>+//RDPCSTX1_RDPCSTX_CNTL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE__SHIFT                                          0x3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY__SHIFT                                                   0xb</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB__SHIFT                                            0x1b</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_MASK                                                   0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE_MASK                                            0x00000008L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY_MASK                                                     0x00000800L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB_MASK                                              0x08000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_CLOCK_CNTL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS_MASK                                         0x01000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED__SHIFT                                     0x19</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK__SHIFT                                0x1a</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK                                       0x02000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK_MASK                                  0x04000000L</div><div class='add'>+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L</div><div class='add'>+//RDPCSTX1_RDPCS_TX_CR_ADDR</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX1_RDPCS_TX_CR_DATA</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX1_RDPCS_TX_SRAM_CNTL</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG__SHIFT                                            0x10</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG_MASK                                              0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_SCRATCH0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_SPARE</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_CNTL2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL</div><div class='add'>+//RDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE</div><div class='add'>+#define RDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE_MASK                                      0xFFFFFFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN__SHIFT                                0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL__SHIFT                          0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR__SHIFT                           0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN_MASK                                  0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL_MASK                            0x00000006L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR_MASK                             0x00000010L</div><div class='add'>+//RDPCSTX1_RDPCSTX_CNTL4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY__SHIFT                                              0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY__SHIFT                                            0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY_MASK                                                0x000003FFL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY_MASK                                              0x000FFC00L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY_MASK                                               0x3FF00000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00000E00L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN__SHIFT                                       0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN_MASK                                         0x00001000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL5</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL9</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL13</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN__SHIFT                                        0x4</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN__SHIFT                                        0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN__SHIFT                                        0xa</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN__SHIFT                                        0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN__SHIFT                                        0xd</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN__SHIFT                                        0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN_MASK                                          0x00000030L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN_MASK                                          0x000000C0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN_MASK                                          0x00000300L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN_MASK                                          0x00000C00L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN_MASK                                          0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN_MASK                                          0x00002000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN_MASK                                          0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_FUSE0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_FUSE1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_FUSE2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_FUSE3</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL__SHIFT                                            0x1a</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL_MASK                                              0x1C000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L</div><div class='add'>+//RDPCSTX1_RDPCSTX_SCRATCH1</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_SCRATCH2</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL15</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP__SHIFT                                   0xd</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP__SHIFT                                   0xe</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP__SHIFT                                   0xf</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN__SHIFT                                                 0x1e</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP_MASK                                     0x00001000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP_MASK                                     0x00002000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP_MASK                                     0x00004000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP_MASK                                     0x00008000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL_MASK                                                 0x3F000000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN_MASK                                                   0x40000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL16</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L</div><div class='add'>+//RDPCSTX1_RDPCSTX_PHY_CNTL17</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L</div><div class='add'>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L</div><div class='add'>+//RDPCSTX1_RDPCS_CNTL3</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L</div><div class='add'>+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L</div><div class='add'>+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL</div><div class='add'>+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx2_dispdec</div><div class='add'>+//RDPCSTX2_RDPCSTX_CNTL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE__SHIFT                                          0x3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY__SHIFT                                                   0xb</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB__SHIFT                                            0x1b</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_MASK                                                   0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE_MASK                                            0x00000008L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY_MASK                                                     0x00000800L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB_MASK                                              0x08000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_CLOCK_CNTL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS_MASK                                         0x01000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED__SHIFT                                     0x19</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK__SHIFT                                0x1a</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK                                       0x02000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK_MASK                                  0x04000000L</div><div class='add'>+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L</div><div class='add'>+//RDPCSTX2_RDPCS_TX_CR_ADDR</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX2_RDPCS_TX_CR_DATA</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX2_RDPCS_TX_SRAM_CNTL</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG__SHIFT                                            0x10</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG_MASK                                              0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_SCRATCH0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_SPARE</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_CNTL2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL</div><div class='add'>+//RDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE</div><div class='add'>+#define RDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE_MASK                                      0xFFFFFFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN__SHIFT                                0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL__SHIFT                          0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR__SHIFT                           0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN_MASK                                  0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL_MASK                            0x00000006L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR_MASK                             0x00000010L</div><div class='add'>+//RDPCSTX2_RDPCSTX_CNTL4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY__SHIFT                                              0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY__SHIFT                                            0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY_MASK                                                0x000003FFL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY_MASK                                              0x000FFC00L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY_MASK                                               0x3FF00000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00000E00L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN__SHIFT                                       0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN_MASK                                         0x00001000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL5</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL9</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL13</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN__SHIFT                                        0x4</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN__SHIFT                                        0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN__SHIFT                                        0xa</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN__SHIFT                                        0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN__SHIFT                                        0xd</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN__SHIFT                                        0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN_MASK                                          0x00000030L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN_MASK                                          0x000000C0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN_MASK                                          0x00000300L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN_MASK                                          0x00000C00L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN_MASK                                          0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN_MASK                                          0x00002000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN_MASK                                          0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_FUSE0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_FUSE1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_FUSE2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_FUSE3</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL__SHIFT                                            0x1a</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL_MASK                                              0x1C000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L</div><div class='add'>+//RDPCSTX2_RDPCSTX_SCRATCH1</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_SCRATCH2</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL15</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP__SHIFT                                   0xd</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP__SHIFT                                   0xe</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP__SHIFT                                   0xf</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN__SHIFT                                                 0x1e</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP_MASK                                     0x00001000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP_MASK                                     0x00002000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP_MASK                                     0x00004000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP_MASK                                     0x00008000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL_MASK                                                 0x3F000000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN_MASK                                                   0x40000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL16</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L</div><div class='add'>+//RDPCSTX2_RDPCSTX_PHY_CNTL17</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L</div><div class='add'>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L</div><div class='add'>+//RDPCSTX2_RDPCS_CNTL3</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L</div><div class='add'>+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L</div><div class='add'>+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL</div><div class='add'>+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dpcssys_dpcs0_rdpcstx3_dispdec</div><div class='add'>+//RDPCSTX3_RDPCSTX_CNTL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE__SHIFT                                          0x3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY__SHIFT                                                   0xb</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB__SHIFT                                            0x1b</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_MASK                                                   0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_CM_MODE_EN_OVR_ENABLE_MASK                                            0x00000008L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__ENFORCE_REQ_ACK_4_WAY_MASK                                                     0x00000800L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_VCM_BITS_PACK_FROM_MSB_MASK                                              0x08000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_CLOCK_CNTL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_PHY_CLOCKS_GATE_DIS_MASK                                           0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__ANTIGLITCH_CFG_CLK_GATE_DIS_MASK                                         0x01000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED__SHIFT                                     0x19</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK__SHIFT                                0x1a</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK                                       0x02000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_DISABLED_MASK_MASK                                  0x04000000L</div><div class='add'>+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L</div><div class='add'>+//RDPCSTX3_RDPCS_TX_CR_ADDR</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX3_RDPCS_TX_CR_DATA</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL</div><div class='add'>+//RDPCSTX3_RDPCS_TX_SRAM_CNTL</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG__SHIFT                                            0x10</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__MEM_PWR_CTRL_SNAP_TRIG_MASK                                              0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_SCRATCH0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SCRATCH0__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_SPARE</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_CNTL2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL</div><div class='add'>+//RDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE</div><div class='add'>+#define RDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE__RDPCSTX_DPALT_CNTL_SPARE_MASK                                      0xFFFFFFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN__SHIFT                                0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL__SHIFT                          0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR__SHIFT                           0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_EN_MASK                                  0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_PATTERN_DETECT_LANE_SEL_MASK                            0x00000006L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL__RDPCSTX_TX_DATA_LANE_SSB_ERROR_MASK                             0x00000010L</div><div class='add'>+//RDPCSTX3_RDPCSTX_CNTL4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY__SHIFT                                              0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY__SHIFT                                            0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL4__RDPCS_BEACON_EN_SET_DELAY_MASK                                                0x000003FFL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL4__RDPCS_BEACON_EN_RESET_DELAY_MASK                                              0x000FFC00L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_CNTL4__RDPCS_TX_DATA_EN_SET_DELAY_MASK                                               0x3FF00000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00000E00L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN__SHIFT                                       0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_TEST_TX_REF_CLK_EN_MASK                                         0x00001000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL5</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL9</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL13</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN__SHIFT                                        0x4</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN__SHIFT                                        0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN__SHIFT                                        0xa</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN__SHIFT                                        0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN__SHIFT                                        0xd</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN__SHIFT                                        0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN__SHIFT                                        0xf</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_RBOOST_EN_MASK                                          0x00000030L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_RBOOST_EN_MASK                                          0x000000C0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_RBOOST_EN_MASK                                          0x00000300L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_RBOOST_EN_MASK                                          0x00000C00L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX0_IBOOST_EN_MASK                                          0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX1_IBOOST_EN_MASK                                          0x00002000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX2_IBOOST_EN_MASK                                          0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_TX3_IBOOST_EN_MASK                                          0x00008000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_FUSE0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_FUSE1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_FUSE2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_FUSE3</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL__SHIFT                                            0x1a</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VSWING_LVL_MASK                                              0x1C000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L</div><div class='add'>+//RDPCSTX3_RDPCSTX_SCRATCH1</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SCRATCH1__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_SCRATCH2</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH__SHIFT                                                     0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_SCRATCH2__RDPCSTX_SCRATCH_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL15</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP__SHIFT                                   0xd</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP__SHIFT                                   0xe</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP__SHIFT                                   0xf</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN__SHIFT                                                 0x1e</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_DCC_BYP_AC_CAP_MASK                                     0x00001000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_DCC_BYP_AC_CAP_MASK                                     0x00002000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_DCC_BYP_AC_CAP_MASK                                     0x00004000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_DCC_BYP_AC_CAP_MASK                                     0x00008000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_CTRL_MASK                                                 0x3F000000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_REXT_EN_MASK                                                   0x40000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL16</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L</div><div class='add'>+//RDPCSTX3_RDPCSTX_PHY_CNTL17</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L</div><div class='add'>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L</div><div class='add'>+//RDPCSTX3_RDPCS_CNTL3</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L</div><div class='add'>+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L</div><div class='add'>+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL</div><div class='add'>+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0</div><div class='add'>+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azcontroller_azdec</div><div class='add'>+//AZCONTROLLER0_CORB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+//AZCONTROLLER0_CORB_READ_POINTER</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL</div><div class='add'>+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L</div><div class='add'>+//AZCONTROLLER0_CORB_CONTROL</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L</div><div class='add'>+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L</div><div class='add'>+//AZCONTROLLER0_CORB_STATUS</div><div class='add'>+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L</div><div class='add'>+//AZCONTROLLER0_CORB_SIZE</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL</div><div class='add'>+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_RIRB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L</div><div class='add'>+//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT</div><div class='add'>+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0</div><div class='add'>+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL</div><div class='add'>+//AZCONTROLLER0_RIRB_CONTROL</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L</div><div class='add'>+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L</div><div class='add'>+//AZCONTROLLER0_RIRB_STATUS</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L</div><div class='add'>+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L</div><div class='add'>+//AZCONTROLLER0_RIRB_SIZE</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L</div><div class='add'>+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L</div><div class='add'>+//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS</div><div class='add'>+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0</div><div class='add'>+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azendpoint_azdec</div><div class='add'>+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL</div><div class='add'>+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0</div><div class='add'>+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azinputendpoint_azdec</div><div class='add'>+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL</div><div class='add'>+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0</div><div class='add'>+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azroot_azdec</div><div class='add'>+//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0</div><div class='add'>+#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT               0x0</div><div class='add'>+#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                 0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream0_azdec</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream1_azdec</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream2_azdec</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream3_azdec</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream4_azdec</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream5_azdec</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream6_azdec</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_host_hda_azstream7_azdec</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azcontroller_azdec</div><div class='add'>+//GLOBAL_CAPABILITIES</div><div class='add'>+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                                          0x0</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                                      0x1</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                                 0x3</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                                         0x8</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                                        0xc</div><div class='add'>+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                                            0x0001L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                        0x0006L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                                   0x00F8L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                                           0x0F00L</div><div class='add'>+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                                          0xF000L</div><div class='add'>+//MINOR_VERSION</div><div class='add'>+#define MINOR_VERSION__MINOR_VERSION__SHIFT                                                                   0x0</div><div class='add'>+#define MINOR_VERSION__MINOR_VERSION_MASK                                                                     0xFFL</div><div class='add'>+//MAJOR_VERSION</div><div class='add'>+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                                   0x0</div><div class='add'>+#define MAJOR_VERSION__MAJOR_VERSION_MASK                                                                     0xFFL</div><div class='add'>+//OUTPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                           0x0</div><div class='add'>+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                             0xFFFFL</div><div class='add'>+//INPUT_PAYLOAD_CAPABILITY</div><div class='add'>+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                             0x0</div><div class='add'>+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                               0xFFFFL</div><div class='add'>+//GLOBAL_CONTROL</div><div class='add'>+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                               0x0</div><div class='add'>+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                                  0x1</div><div class='add'>+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                                             0x8</div><div class='add'>+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                                 0x00000001L</div><div class='add'>+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                                    0x00000002L</div><div class='add'>+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                               0x00000100L</div><div class='add'>+//WAKE_ENABLE</div><div class='add'>+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                                             0x0</div><div class='add'>+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                               0x0001L</div><div class='add'>+//STATE_CHANGE_STATUS</div><div class='add'>+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                                       0x0</div><div class='add'>+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                                         0x0001L</div><div class='add'>+//GLOBAL_STATUS</div><div class='add'>+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                                    0x1</div><div class='add'>+#define GLOBAL_STATUS__FLUSH_STATUS_MASK                                                                      0x00000002L</div><div class='add'>+//OUTPUT_STREAM_PAYLOAD_CAPABILITY</div><div class='add'>+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x0</div><div class='add'>+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFFL</div><div class='add'>+//INPUT_STREAM_PAYLOAD_CAPABILITY</div><div class='add'>+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x0</div><div class='add'>+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFFL</div><div class='add'>+//INTERRUPT_CONTROL</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                                   0x0</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                                   0x1</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                                   0x2</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                                   0x3</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                                   0x4</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                                   0x5</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                                   0x6</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                                   0x7</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                                   0x8</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                                   0x9</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                                  0xa</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                                  0xb</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                                  0xc</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                                  0xd</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                                  0xe</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                                  0xf</div><div class='add'>+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                                 0x1e</div><div class='add'>+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                                     0x1f</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                                     0x00000001L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                                     0x00000002L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                                     0x00000004L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                                     0x00000008L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                                     0x00000010L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                                     0x00000020L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                                     0x00000040L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                                     0x00000080L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                                     0x00000100L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                                     0x00000200L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                                    0x00000400L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                                    0x00000800L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                                    0x00001000L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                                    0x00002000L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                                    0x00004000L</div><div class='add'>+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                                    0x00008000L</div><div class='add'>+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                                   0x40000000L</div><div class='add'>+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                                       0x80000000L</div><div class='add'>+//INTERRUPT_STATUS</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                                    0x0</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                                    0x1</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT                                                    0x2</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT                                                    0x3</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT                                                    0x4</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT                                                    0x5</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT                                                    0x6</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT                                                    0x7</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT                                                    0x8</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT                                                    0x9</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT                                                   0xa</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT                                                   0xb</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT                                                   0xc</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT                                                   0xd</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT                                                   0xe</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT                                                   0xf</div><div class='add'>+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT                                                  0x1e</div><div class='add'>+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT                                                      0x1f</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK                                                      0x00000001L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK                                                      0x00000002L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK                                                      0x00000004L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK                                                      0x00000008L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK                                                      0x00000010L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK                                                      0x00000020L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK                                                      0x00000040L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK                                                      0x00000080L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK                                                      0x00000100L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK                                                      0x00000200L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK                                                     0x00000400L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK                                                     0x00000800L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK                                                     0x00001000L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK                                                     0x00002000L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK                                                     0x00004000L</div><div class='add'>+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK                                                     0x00008000L</div><div class='add'>+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK                                                    0x40000000L</div><div class='add'>+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK                                                        0x80000000L</div><div class='add'>+//WALL_CLOCK_COUNTER</div><div class='add'>+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT                                                         0x0</div><div class='add'>+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//STREAM_SYNCHRONIZATION</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT                                               0x0</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT                                               0x1</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT                                               0x2</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT                                               0x3</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT                                               0x4</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT                                               0x5</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT                                               0x6</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT                                               0x7</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT                                               0x8</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT                                               0x9</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT                                              0xa</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT                                              0xb</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT                                              0xc</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT                                              0xd</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT                                              0xe</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT                                              0xf</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK                                                 0x00000001L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK                                                 0x00000002L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK                                                 0x00000004L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK                                                 0x00000008L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK                                                 0x00000010L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK                                                 0x00000020L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK                                                 0x00000040L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK                                                 0x00000080L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK                                                 0x00000100L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK                                                 0x00000200L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK                                                0x00000400L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK                                                0x00000800L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK                                                0x00001000L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK                                                0x00002000L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK                                                0x00004000L</div><div class='add'>+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK                                                0x00008000L</div><div class='add'>+//CORB_LOWER_BASE_ADDRESS</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT                                               0x7</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL</div><div class='add'>+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L</div><div class='add'>+//CORB_UPPER_BASE_ADDRESS</div><div class='add'>+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT                                               0x0</div><div class='add'>+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_CORB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+//AZCONTROLLER1_CORB_READ_POINTER</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL</div><div class='add'>+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L</div><div class='add'>+//AZCONTROLLER1_CORB_CONTROL</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L</div><div class='add'>+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L</div><div class='add'>+//AZCONTROLLER1_CORB_STATUS</div><div class='add'>+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L</div><div class='add'>+//AZCONTROLLER1_CORB_SIZE</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL</div><div class='add'>+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_RIRB_WRITE_POINTER</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL</div><div class='add'>+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L</div><div class='add'>+//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT</div><div class='add'>+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0</div><div class='add'>+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL</div><div class='add'>+//AZCONTROLLER1_RIRB_CONTROL</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L</div><div class='add'>+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L</div><div class='add'>+//AZCONTROLLER1_RIRB_STATUS</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L</div><div class='add'>+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L</div><div class='add'>+//AZCONTROLLER1_RIRB_SIZE</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L</div><div class='add'>+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L</div><div class='add'>+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L</div><div class='add'>+//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L</div><div class='add'>+//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0</div><div class='add'>+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL</div><div class='add'>+//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS</div><div class='add'>+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0</div><div class='add'>+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azendpoint_azdec</div><div class='add'>+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL</div><div class='add'>+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0</div><div class='add'>+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azinputendpoint_azdec</div><div class='add'>+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL</div><div class='add'>+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0</div><div class='add'>+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azroot_azdec</div><div class='add'>+//AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA</div><div class='add'>+#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0</div><div class='add'>+#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX</div><div class='add'>+#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT               0x0</div><div class='add'>+#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                 0x0001FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream0_azdec</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream1_azdec</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream2_azdec</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream3_azdec</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream4_azdec</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream5_azdec</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream6_azdec</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hda_azstream7_azdec</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT                          0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT                            0x1</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT        0x2</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT           0x3</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT     0x4</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT                        0x10</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT                      0x12</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT                         0x14</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT    0x1a</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT                            0x1b</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT                      0x1c</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT                            0x1d</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK                            0x00000001L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK                              0x00000002L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK          0x00000004L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK             0x00000008L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK       0x00000010L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK                          0x00030000L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK                        0x00040000L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK                           0x00F00000L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK      0x04000000L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK                              0x08000000L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK                        0x10000000L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK                              0x20000000L</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK    0xFFFFFFFFL</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT                0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK                  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT                        0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK                          0x000000FFL</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT                                      0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK                                        0xFFFFL</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT                                0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT                                   0x4</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                               0x8</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                              0xb</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT                                  0xe</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK                                  0x000FL</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK                                     0x0070L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK                                 0x0700L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                                0x3800L</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK                                    0x4000L</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT  0x7</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK  0x0000007FL</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK  0xFFFFFF80L</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT  0x0</div><div class='add'>+#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK  0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_hdcp1kp_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig0_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig1_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig2_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_dio_dig3_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc0_sym32_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc1_sym32_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc2_sym32_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcn_dcec_hpo_dp_link_enc3_sym32_hdcp2_hdcp2_pkdbdec</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: cnvc_cfg_cnvc_cfgdebugind</div><div class='add'>+//ID2_CNVC_FLOW_CONTROL</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_VREADY__SHIFT                                                         0x0</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_VSTARUP__SHIFT                                                        0x1</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_DYN_CLK_ON__SHIFT                                                     0x2</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_ISEND__SHIFT                                                          0x3</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_OFREE__SHIFT                                                          0x4</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_ISEND_C__SHIFT                                                        0x5</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_OFREE_C__SHIFT                                                        0x6</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_IRTR__SHIFT                                                            0x7</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_ORTS__SHIFT                                                            0x8</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_IRTR_C__SHIFT                                                          0x9</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_ORTS_C__SHIFT                                                          0xa</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_IRTR__SHIFT                                                           0xb</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_ORTS__SHIFT                                                           0xc</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_IRTR_C__SHIFT                                                         0xd</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_ORTS_C__SHIFT                                                         0xe</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_IRTR__SHIFT                                                           0xf</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_ORTS__SHIFT                                                           0x10</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_IRTR_C__SHIFT                                                         0x11</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_ORTS_C__SHIFT                                                         0x12</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_IRTR__SHIFT                                                         0x13</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_ORTS__SHIFT                                                         0x14</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_IRTR_C__SHIFT                                                       0x15</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_ORTS_C__SHIFT                                                       0x16</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_VREADY_MASK                                                           0x00000001L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_VSTARUP_MASK                                                          0x00000002L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_DYN_CLK_ON_MASK                                                       0x00000004L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_ISEND_MASK                                                            0x00000008L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_OFREE_MASK                                                            0x00000010L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_ISEND_C_MASK                                                          0x00000020L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_CNVC_OFREE_C_MASK                                                          0x00000040L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_IRTR_MASK                                                              0x00000080L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_ORTS_MASK                                                              0x00000100L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_IRTR_C_MASK                                                            0x00000200L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_SFR_ORTS_C_MASK                                                            0x00000400L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_IRTR_MASK                                                             0x00000800L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_ORTS_MASK                                                             0x00001000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_IRTR_C_MASK                                                           0x00002000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_INTF_ORTS_C_MASK                                                           0x00004000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_IRTR_MASK                                                             0x00008000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_ORTS_MASK                                                             0x00010000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_IRTR_C_MASK                                                           0x00020000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_FCNV_ORTS_C_MASK                                                           0x00040000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_IRTR_MASK                                                           0x00080000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_ORTS_MASK                                                           0x00100000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_IRTR_C_MASK                                                         0x00200000L</div><div class='add'>+#define ID2_CNVC_FLOW_CONTROL__ID2_PRE_CM_ORTS_C_MASK                                                         0x00400000L</div><div class='add'>+//ID4_CNVC_FLOW_CONTROL_2</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_CNVC_VREADY__SHIFT                                                       0x0</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_CNVC_VSTARUP__SHIFT                                                      0x1</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_CNVC_DYN_CLK_ON__SHIFT                                                   0x2</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_IRTR__SHIFT                                                          0xb</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_ORTS__SHIFT                                                          0xc</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_IRTR_C__SHIFT                                                        0xd</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_ORTS_C__SHIFT                                                        0xe</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_CNVC_VREADY_MASK                                                         0x00000001L</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_CNVC_VSTARUP_MASK                                                        0x00000002L</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_CNVC_DYN_CLK_ON_MASK                                                     0x00000004L</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_IRTR_MASK                                                            0x00000800L</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_ORTS_MASK                                                            0x00001000L</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_IRTR_C_MASK                                                          0x00002000L</div><div class='add'>+#define ID4_CNVC_FLOW_CONTROL_2__ID4_OUT_ORTS_C_MASK                                                          0x00004000L</div><div class='add'>+//ID5_CNVC_REG_TO_FP_INPUT</div><div class='add'>+#define ID5_CNVC_REG_TO_FP_INPUT__ID5_PREVIOUS_INPUT_UPPER__SHIFT                                             0x0</div><div class='add'>+#define ID5_CNVC_REG_TO_FP_INPUT__ID5_PREVIOUS_INPUT_LOWER__SHIFT                                             0x10</div><div class='add'>+#define ID5_CNVC_REG_TO_FP_INPUT__ID5_PREVIOUS_INPUT_UPPER_MASK                                               0x0000FFFFL</div><div class='add'>+#define ID5_CNVC_REG_TO_FP_INPUT__ID5_PREVIOUS_INPUT_LOWER_MASK                                               0xFFFF0000L</div><div class='add'>+//ID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0</div><div class='add'>+#define ID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0__ID6_PREVIOUS_OUTPUT_UPPER_0__SHIFT                                 0x0</div><div class='add'>+#define ID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0__ID6_PREVIOUS_OUTPUT_UPPER_0_MASK                                   0x0007FFFFL</div><div class='add'>+//ID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0</div><div class='add'>+#define ID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0__ID7_PREVIOUS_OUTPUT_LOWER_0__SHIFT                                 0x0</div><div class='add'>+#define ID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0__ID7_PREVIOUS_OUTPUT_LOWER_0_MASK                                   0x0007FFFFL</div><div class='add'>+//ID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1</div><div class='add'>+#define ID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1__ID8_PREVIOUS_OUTPUT_UPPER_1__SHIFT                                 0x0</div><div class='add'>+#define ID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1__ID8_PREVIOUS_OUTPUT_UPPER_1_MASK                                   0x0007FFFFL</div><div class='add'>+//ID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1</div><div class='add'>+#define ID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1__ID9_PREVIOUS_OUTPUT_LOWER_1__SHIFT                                 0x0</div><div class='add'>+#define ID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1__ID9_PREVIOUS_OUTPUT_LOWER_1_MASK                                   0x0007FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: cm_cur_cm_cur0debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dscl_dscldebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: cm_cmdebugind</div><div class='add'>+//ID1_CM_FLOW_CONTROL</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_VREADY__SHIFT                                                             0x0</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_VSTARTUP__SHIFT                                                           0x1</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_DYN_CLK_ON__SHIFT                                                         0x2</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_ORTR__SHIFT                                                               0x3</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_IRTS__SHIFT                                                               0x4</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_DEALPHA_IRTR__SHIFT                                                          0x5</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_DEALPHA_ORTS__SHIFT                                                          0x6</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMIN_IRTR__SHIFT                                                             0x7</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMIN_ORTS__SHIFT                                                             0x8</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BNS_IRTR__SHIFT                                                              0x9</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BNS_ORTS__SHIFT                                                              0xa</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_POST_CSC_IRTR__SHIFT                                                         0xb</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_POST_CSC_ORTS__SHIFT                                                         0xc</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_GAMCOR_IRTR__SHIFT                                                           0xd</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_GAMCOR_ORTS__SHIFT                                                           0xe</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_HDR_IRTR__SHIFT                                                              0xf</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_HDR_ORTS__SHIFT                                                              0x10</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BREAK_IRTR__SHIFT                                                            0x15</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BREAK_ORTS__SHIFT                                                            0x16</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMOUT_IRTR__SHIFT                                                            0x1b</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMOUT_ORTS__SHIFT                                                            0x1c</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_IRTR__SHIFT                                                               0x1d</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_ORTS__SHIFT                                                               0x1e</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_VREADY_MASK                                                               0x00000001L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_VSTARTUP_MASK                                                             0x00000002L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_DYN_CLK_ON_MASK                                                           0x00000004L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_ORTR_MASK                                                                 0x00000008L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_IRTS_MASK                                                                 0x00000010L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_DEALPHA_IRTR_MASK                                                            0x00000020L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_DEALPHA_ORTS_MASK                                                            0x00000040L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMIN_IRTR_MASK                                                               0x00000080L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMIN_ORTS_MASK                                                               0x00000100L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BNS_IRTR_MASK                                                                0x00000200L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BNS_ORTS_MASK                                                                0x00000400L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_POST_CSC_IRTR_MASK                                                           0x00000800L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_POST_CSC_ORTS_MASK                                                           0x00001000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_GAMCOR_IRTR_MASK                                                             0x00002000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_GAMCOR_ORTS_MASK                                                             0x00004000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_HDR_IRTR_MASK                                                                0x00008000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_HDR_ORTS_MASK                                                                0x00010000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BREAK_IRTR_MASK                                                              0x00200000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_BREAK_ORTS_MASK                                                              0x00400000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMOUT_IRTR_MASK                                                              0x08000000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CMOUT_ORTS_MASK                                                              0x10000000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_IRTR_MASK                                                                 0x20000000L</div><div class='add'>+#define ID1_CM_FLOW_CONTROL__ID1_CM_ORTS_MASK                                                                 0x40000000L</div><div class='add'>+//ID2_CM_BYPASS</div><div class='add'>+#define ID2_CM_BYPASS__ID2_VUPDATE_CFG__SHIFT                                                                 0x0</div><div class='add'>+#define ID2_CM_BYPASS__ID2_CM_BYPASS__SHIFT                                                                   0x1</div><div class='add'>+#define ID2_CM_BYPASS__ID2_DEALPHA_BYPASS__SHIFT                                                              0x2</div><div class='add'>+#define ID2_CM_BYPASS__ID2_BIAS_BYPASS__SHIFT                                                                 0x3</div><div class='add'>+#define ID2_CM_BYPASS__ID2_POST_CSC_BYPASS__SHIFT                                                             0x4</div><div class='add'>+#define ID2_CM_BYPASS__ID2_GAMCOR_BYPASS__SHIFT                                                               0x5</div><div class='add'>+#define ID2_CM_BYPASS__ID2_HDR_BYPASS__SHIFT                                                                  0x6</div><div class='add'>+#define ID2_CM_BYPASS__ID2_VUPDATE_CFG_MASK                                                                   0x00000001L</div><div class='add'>+#define ID2_CM_BYPASS__ID2_CM_BYPASS_MASK                                                                     0x00000002L</div><div class='add'>+#define ID2_CM_BYPASS__ID2_DEALPHA_BYPASS_MASK                                                                0x00000004L</div><div class='add'>+#define ID2_CM_BYPASS__ID2_BIAS_BYPASS_MASK                                                                   0x00000008L</div><div class='add'>+#define ID2_CM_BYPASS__ID2_POST_CSC_BYPASS_MASK                                                               0x00000010L</div><div class='add'>+#define ID2_CM_BYPASS__ID2_GAMCOR_BYPASS_MASK                                                                 0x00000020L</div><div class='add'>+#define ID2_CM_BYPASS__ID2_HDR_BYPASS_MASK                                                                    0x00000040L</div><div class='add'>+//ID3_CM_REG_TO_FP_CSC_INPUT</div><div class='add'>+#define ID3_CM_REG_TO_FP_CSC_INPUT__ID3_PREVIOUS_INPUT_UPPER__SHIFT                                           0x0</div><div class='add'>+#define ID3_CM_REG_TO_FP_CSC_INPUT__ID3_PREVIOUS_INPUT_LOWER__SHIFT                                           0x10</div><div class='add'>+#define ID3_CM_REG_TO_FP_CSC_INPUT__ID3_PREVIOUS_INPUT_UPPER_MASK                                             0x0000FFFFL</div><div class='add'>+#define ID3_CM_REG_TO_FP_CSC_INPUT__ID3_PREVIOUS_INPUT_LOWER_MASK                                             0xFFFF0000L</div><div class='add'>+//ID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0</div><div class='add'>+#define ID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0__ID4_PREVIOUS_OUTPUT_UPPER_0__SHIFT                               0x0</div><div class='add'>+#define ID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0__ID4_PREVIOUS_OUTPUT_UPPER_0_MASK                                 0x0007FFFFL</div><div class='add'>+//ID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0</div><div class='add'>+#define ID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0__ID5_PREVIOUS_OUTPUT_LOWER_0__SHIFT                               0x0</div><div class='add'>+#define ID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0__ID5_PREVIOUS_OUTPUT_LOWER_0_MASK                                 0x0007FFFFL</div><div class='add'>+//ID6_CM_REG_TO_FP_BIAS_INPUT</div><div class='add'>+#define ID6_CM_REG_TO_FP_BIAS_INPUT__ID6_PREVIOUS_INPUT_UPPER__SHIFT                                          0x0</div><div class='add'>+#define ID6_CM_REG_TO_FP_BIAS_INPUT__ID6_PREVIOUS_INPUT_LOWER__SHIFT                                          0x10</div><div class='add'>+#define ID6_CM_REG_TO_FP_BIAS_INPUT__ID6_PREVIOUS_INPUT_UPPER_MASK                                            0x0000FFFFL</div><div class='add'>+#define ID6_CM_REG_TO_FP_BIAS_INPUT__ID6_PREVIOUS_INPUT_LOWER_MASK                                            0xFFFF0000L</div><div class='add'>+//ID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0</div><div class='add'>+#define ID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0__ID7_PREVIOUS_OUTPUT_UPPER_0__SHIFT                              0x0</div><div class='add'>+#define ID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0__ID7_PREVIOUS_OUTPUT_UPPER_0_MASK                                0x0007FFFFL</div><div class='add'>+//ID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0</div><div class='add'>+#define ID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0__ID8_PREVIOUS_OUTPUT_LOWER_0__SHIFT                              0x0</div><div class='add'>+#define ID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0__ID8_PREVIOUS_OUTPUT_LOWER_0_MASK                                0x0007FFFFL</div><div class='add'>+//ID9_CM_STATUS</div><div class='add'>+#define ID9_CM_STATUS__ID9_VUPDATE_CFG__SHIFT                                                                 0x0</div><div class='add'>+#define ID9_CM_STATUS__ID9_DEALPHA_BYPASS__SHIFT                                                              0x1</div><div class='add'>+#define ID9_CM_STATUS__ID9_BIAS_BYPASS__SHIFT                                                                 0x2</div><div class='add'>+#define ID9_CM_STATUS__ID9_POST_CSC_MODE__SHIFT                                                               0x3</div><div class='add'>+#define ID9_CM_STATUS__ID9_GAMCOR_MODE__SHIFT                                                                 0x5</div><div class='add'>+#define ID9_CM_STATUS__ID9_HDR_BYPASS__SHIFT                                                                  0x8</div><div class='add'>+#define ID9_CM_STATUS__ID9_VUPDATE_CFG_MASK                                                                   0x00000001L</div><div class='add'>+#define ID9_CM_STATUS__ID9_DEALPHA_BYPASS_MASK                                                                0x00000002L</div><div class='add'>+#define ID9_CM_STATUS__ID9_BIAS_BYPASS_MASK                                                                   0x00000004L</div><div class='add'>+#define ID9_CM_STATUS__ID9_POST_CSC_MODE_MASK                                                                 0x00000018L</div><div class='add'>+#define ID9_CM_STATUS__ID9_GAMCOR_MODE_MASK                                                                   0x00000060L</div><div class='add'>+#define ID9_CM_STATUS__ID9_HDR_BYPASS_MASK                                                                    0x00000100L</div><div class='add'>+//IDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1</div><div class='add'>+#define IDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1__IDA_PREVIOUS_OUTPUT_UPPER_1__SHIFT                               0x0</div><div class='add'>+#define IDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1__IDA_PREVIOUS_OUTPUT_UPPER_1_MASK                                 0x0007FFFFL</div><div class='add'>+//IDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1</div><div class='add'>+#define IDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1__IDB_PREVIOUS_OUTPUT_LOWER_1__SHIFT                               0x0</div><div class='add'>+#define IDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1__IDB_PREVIOUS_OUTPUT_LOWER_1_MASK                                 0x0007FFFFL</div><div class='add'>+//IDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1</div><div class='add'>+#define IDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1__IDC_PREVIOUS_OUTPUT_UPPER_1__SHIFT                              0x0</div><div class='add'>+#define IDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1__IDC_PREVIOUS_OUTPUT_UPPER_1_MASK                                0x0007FFFFL</div><div class='add'>+//IDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1</div><div class='add'>+#define IDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1__IDD_PREVIOUS_OUTPUT_LOWER_1__SHIFT                              0x0</div><div class='add'>+#define IDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1__IDD_PREVIOUS_OUTPUT_LOWER_1_MASK                                0x0007FFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dpp_top_dppdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dc_perfmon_dc_perfmondebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubp_hubpdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubpreq_hubpreqdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubpret_hubpretdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mmhubbub_mmhubbubdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mcif_wb0_mcif_wbdebugind</div><div class='add'>+//ID01_WB_FMT_DBG</div><div class='add'>+#define ID01_WB_FMT_DBG__ID01_WB_FMT_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID01_WB_FMT_DBG__ID01_WB_FMT_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID02_WB_FMT_DBG</div><div class='add'>+#define ID02_WB_FMT_DBG__ID02_WB_FMT_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID02_WB_FMT_DBG__ID02_WB_FMT_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID03_WB_FMT_DBG</div><div class='add'>+#define ID03_WB_FMT_DBG__ID03_WB_FMT_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID03_WB_FMT_DBG__ID03_WB_FMT_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID04_WB_MGR_DBG</div><div class='add'>+#define ID04_WB_MGR_DBG__ID04_WB_MGR_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID04_WB_MGR_DBG__ID04_WB_MGR_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID05_WB_MGR_DBG</div><div class='add'>+#define ID05_WB_MGR_DBG__ID05_WB_MGR_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID05_WB_MGR_DBG__ID05_WB_MGR_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID06_WB_MGR_DBG</div><div class='add'>+#define ID06_WB_MGR_DBG__ID06_WB_MGR_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID06_WB_MGR_DBG__ID06_WB_MGR_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID07_WB_MGR_DBG</div><div class='add'>+#define ID07_WB_MGR_DBG__ID07_WB_MGR_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID07_WB_MGR_DBG__ID07_WB_MGR_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID08_WB_ARB_DBG</div><div class='add'>+#define ID08_WB_ARB_DBG__ID08_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID08_WB_ARB_DBG__ID08_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID09_WB_ARB_DBG</div><div class='add'>+#define ID09_WB_ARB_DBG__ID09_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID09_WB_ARB_DBG__ID09_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID0A_WB_ARB_DBG</div><div class='add'>+#define ID0A_WB_ARB_DBG__ID0A_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID0A_WB_ARB_DBG__ID0A_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID0B_WB_ARB_DBG</div><div class='add'>+#define ID0B_WB_ARB_DBG__ID0B_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID0B_WB_ARB_DBG__ID0B_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID0C_WB_ARB_DBG</div><div class='add'>+#define ID0C_WB_ARB_DBG__ID0C_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID0C_WB_ARB_DBG__ID0C_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID0D_WB_ARB_DBG</div><div class='add'>+#define ID0D_WB_ARB_DBG__ID0D_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID0D_WB_ARB_DBG__ID0D_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID0E_WB_ARB_DBG</div><div class='add'>+#define ID0E_WB_ARB_DBG__ID0E_WB_ARB_DBG__SHIFT                                                               0x0</div><div class='add'>+#define ID0E_WB_ARB_DBG__ID0E_WB_ARB_DBG_MASK                                                                 0xFFFFFFFFL</div><div class='add'>+//ID0F_P010_WB_FMT_DBG_Y</div><div class='add'>+#define ID0F_P010_WB_FMT_DBG_Y__ID0F_P010_WB_FMT_DBG_Y__SHIFT                                                 0x0</div><div class='add'>+#define ID0F_P010_WB_FMT_DBG_Y__ID0F_P010_WB_FMT_DBG_Y_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//ID10_P010_WB_FMT_DBG_C</div><div class='add'>+#define ID10_P010_WB_FMT_DBG_C__ID10_P010_WB_FMT_DBG_C__SHIFT                                                 0x0</div><div class='add'>+#define ID10_P010_WB_FMT_DBG_C__ID10_P010_WB_FMT_DBG_C_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//ID11_WB_ARB_P010_DBG</div><div class='add'>+#define ID11_WB_ARB_P010_DBG__ID11_WB_ARB_P010_DBG__SHIFT                                                     0x0</div><div class='add'>+#define ID11_WB_ARB_P010_DBG__ID11_WB_ARB_P010_DBG_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//ID12_WB_ARB_P010_DBG</div><div class='add'>+#define ID12_WB_ARB_P010_DBG__ID12_WB_ARB_P010_DBG__SHIFT                                                     0x0</div><div class='add'>+#define ID12_WB_ARB_P010_DBG__ID12_WB_ARB_P010_DBG_MASK                                                       0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubbub_dchubbubdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubbub_sdpif_dchubbubsdpifdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubbub_ret_path_dchubbubretpathdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hubbub_vmrq_if_dchubbubvmrqifdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpc_cfg_mpc_cfgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpc_ocsc_mpc_ocscdebugind</div><div class='add'>+//ID1_MPC_OUT0_CSC_MODE_DB</div><div class='add'>+#define ID1_MPC_OUT0_CSC_MODE_DB__ID1_MPC_OUT0_CSC_MODE_MPC_OCSC_MODE_DB__SHIFT                               0x0</div><div class='add'>+#define ID1_MPC_OUT0_CSC_MODE_DB__ID1_MPC_OUT0_CSC_MODE_MPC_OCSC_COEF_FORMAT__SHIFT                           0x3</div><div class='add'>+#define ID1_MPC_OUT0_CSC_MODE_DB__ID1_MPC_OUT0_CSC_MODE_MPC_OCSC_MODE_DB_MASK                                 0x00000003L</div><div class='add'>+#define ID1_MPC_OUT0_CSC_MODE_DB__ID1_MPC_OUT0_CSC_MODE_MPC_OCSC_COEF_FORMAT_MASK                             0x00000008L</div><div class='add'>+//ID2_MPC_OUT1_CSC_MODE_DB</div><div class='add'>+#define ID2_MPC_OUT1_CSC_MODE_DB__ID2_MPC_OUT1_CSC_MODE_MPC_OCSC_MODE_DB__SHIFT                               0x0</div><div class='add'>+#define ID2_MPC_OUT1_CSC_MODE_DB__ID2_MPC_OUT1_CSC_MODE_MPC_OCSC_COEF_FORMAT__SHIFT                           0x3</div><div class='add'>+#define ID2_MPC_OUT1_CSC_MODE_DB__ID2_MPC_OUT1_CSC_MODE_MPC_OCSC_MODE_DB_MASK                                 0x00000003L</div><div class='add'>+#define ID2_MPC_OUT1_CSC_MODE_DB__ID2_MPC_OUT1_CSC_MODE_MPC_OCSC_COEF_FORMAT_MASK                             0x00000008L</div><div class='add'>+//ID3_MPC_OUT2_CSC_MODE_DB</div><div class='add'>+#define ID3_MPC_OUT2_CSC_MODE_DB__ID3_MPC_OUT2_CSC_MODE_MPC_OCSC_MODE_DB__SHIFT                               0x0</div><div class='add'>+#define ID3_MPC_OUT2_CSC_MODE_DB__ID3_MPC_OUT2_CSC_MODE_MPC_OCSC_COEF_FORMAT__SHIFT                           0x3</div><div class='add'>+#define ID3_MPC_OUT2_CSC_MODE_DB__ID3_MPC_OUT2_CSC_MODE_MPC_OCSC_MODE_DB_MASK                                 0x00000003L</div><div class='add'>+#define ID3_MPC_OUT2_CSC_MODE_DB__ID3_MPC_OUT2_CSC_MODE_MPC_OCSC_COEF_FORMAT_MASK                             0x00000008L</div><div class='add'>+//ID4_MPC_OUT3_CSC_MODE_DB</div><div class='add'>+#define ID4_MPC_OUT3_CSC_MODE_DB__ID4_MPC_OUT3_CSC_MODE_MPC_OCSC_MODE_DB__SHIFT                               0x0</div><div class='add'>+#define ID4_MPC_OUT3_CSC_MODE_DB__ID4_MPC_OUT3_CSC_MODE_MPC_OCSC_COEF_FORMAT__SHIFT                           0x3</div><div class='add'>+#define ID4_MPC_OUT3_CSC_MODE_DB__ID4_MPC_OUT3_CSC_MODE_MPC_OCSC_MODE_DB_MASK                                 0x00000003L</div><div class='add'>+#define ID4_MPC_OUT3_CSC_MODE_DB__ID4_MPC_OUT3_CSC_MODE_MPC_OCSC_COEF_FORMAT_MASK                             0x00000008L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc0_mpccdebugind</div><div class='add'>+//MPCC0_ID01_MPCC_SEL_DB</div><div class='add'>+#define MPCC0_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB__SHIFT                                                   0x0</div><div class='add'>+#define MPCC0_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB__SHIFT                                                   0x4</div><div class='add'>+#define MPCC0_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB__SHIFT                                                    0xc</div><div class='add'>+#define MPCC0_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB_MASK                                                     0x0000000FL</div><div class='add'>+#define MPCC0_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB_MASK                                                     0x000000F0L</div><div class='add'>+#define MPCC0_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB_MASK                                                      0x0000F000L</div><div class='add'>+//MPCC0_ID02_MPCC_TOP_GAIN_DB</div><div class='add'>+#define MPCC0_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB__SHIFT                                             0x0</div><div class='add'>+#define MPCC0_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB</div><div class='add'>+#define MPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB__SHIFT                               0x0</div><div class='add'>+#define MPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB_MASK                                 0x0007FFFFL</div><div class='add'>+//MPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB</div><div class='add'>+#define MPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB__SHIFT                             0x0</div><div class='add'>+#define MPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB_MASK                               0x0007FFFFL</div><div class='add'>+//MPCC0_ID05_MPCC_BG_R_CR_DB</div><div class='add'>+#define MPCC0_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC0_ID06_MPCC_BG_G_Y_DB</div><div class='add'>+#define MPCC0_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB__SHIFT                                                 0x0</div><div class='add'>+#define MPCC0_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB_MASK                                                   0x00000FFFL</div><div class='add'>+//MPCC0_ID07_MPCC_BG_B_CB_DB</div><div class='add'>+#define MPCC0_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC0_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC0_ID08_MPCC_CONTROL_DB</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB__SHIFT                                     0x0</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB__SHIFT                          0x4</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB__SHIFT                    0x6</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB__SHIFT                 0x7</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB__SHIFT                                   0x8</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB__SHIFT                            0xb</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB__SHIFT                             0x10</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB__SHIFT                              0x18</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB_MASK                                       0x00000003L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB_MASK                            0x00000030L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB_MASK                      0x00000040L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB_MASK                   0x00000080L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB_MASK                                     0x00000700L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB_MASK                              0x00000800L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB_MASK                               0x00FF0000L</div><div class='add'>+#define MPCC0_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB_MASK                                0xFF000000L</div><div class='add'>+//MPCC0_ID09_MPCC_SM_CONTROL_DB</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB__SHIFT                              0x0</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB__SHIFT                            0x1</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB__SHIFT                       0x4</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB__SHIFT                       0x5</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB_MASK                                0x00000001L</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB_MASK                              0x0000000EL</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB_MASK                         0x00000010L</div><div class='add'>+#define MPCC0_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB_MASK                         0x00000020L</div><div class='add'>+//MPCC0_ID17_MPCC_TOP_PIX</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC0_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC0_ID18_MPCC_recout_start</div><div class='add'>+#define MPCC0_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x__SHIFT                                     0x0</div><div class='add'>+#define MPCC0_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y__SHIFT                                     0x10</div><div class='add'>+#define MPCC0_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x_MASK                                       0x00003FFFL</div><div class='add'>+#define MPCC0_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y_MASK                                       0x3FFF0000L</div><div class='add'>+//MPCC0_ID19_MPCC_recout_size</div><div class='add'>+#define MPCC0_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width__SHIFT                                        0x0</div><div class='add'>+#define MPCC0_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height__SHIFT                                       0x10</div><div class='add'>+#define MPCC0_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width_MASK                                          0x00003FFFL</div><div class='add'>+#define MPCC0_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height_MASK                                         0x3FFF0000L</div><div class='add'>+//MPCC0_ID20_MPCC_mpc_size</div><div class='add'>+#define MPCC0_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width__SHIFT                                              0x0</div><div class='add'>+#define MPCC0_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height__SHIFT                                             0x10</div><div class='add'>+#define MPCC0_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width_MASK                                                0x00003FFFL</div><div class='add'>+#define MPCC0_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height_MASK                                               0x3FFF0000L</div><div class='add'>+//MPCC0_ID21_MPCC_TOP_sideband</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending__SHIFT                                0x16</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+#define MPCC0_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending_MASK                                  0x00400000L</div><div class='add'>+//MPCC0_ID22_MPCC_BOT_PIX</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC0_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC0_ID23_MPCC_BOT_sideband</div><div class='add'>+#define MPCC0_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status__SHIFT                                         0x0</div><div class='add'>+#define MPCC0_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask__SHIFT                                           0x1</div><div class='add'>+#define MPCC0_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status_MASK                                           0x00000001L</div><div class='add'>+#define MPCC0_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask_MASK                                             0x00000002L</div><div class='add'>+//MPCC0_ID24_MPCC_OPP_PIX</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC0_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC0_ID25_MPCC_OPP_sideband</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask__SHIFT                                           0xb</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask_MASK                                             0x00000800L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC0_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc1_mpccdebugind</div><div class='add'>+//MPCC1_ID01_MPCC_SEL_DB</div><div class='add'>+#define MPCC1_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB__SHIFT                                                   0x0</div><div class='add'>+#define MPCC1_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB__SHIFT                                                   0x4</div><div class='add'>+#define MPCC1_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB__SHIFT                                                    0xc</div><div class='add'>+#define MPCC1_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB_MASK                                                     0x0000000FL</div><div class='add'>+#define MPCC1_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB_MASK                                                     0x000000F0L</div><div class='add'>+#define MPCC1_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB_MASK                                                      0x0000F000L</div><div class='add'>+//MPCC1_ID02_MPCC_TOP_GAIN_DB</div><div class='add'>+#define MPCC1_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB__SHIFT                                             0x0</div><div class='add'>+#define MPCC1_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB</div><div class='add'>+#define MPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB__SHIFT                               0x0</div><div class='add'>+#define MPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB_MASK                                 0x0007FFFFL</div><div class='add'>+//MPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB</div><div class='add'>+#define MPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB__SHIFT                             0x0</div><div class='add'>+#define MPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB_MASK                               0x0007FFFFL</div><div class='add'>+//MPCC1_ID05_MPCC_BG_R_CR_DB</div><div class='add'>+#define MPCC1_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC1_ID06_MPCC_BG_G_Y_DB</div><div class='add'>+#define MPCC1_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB__SHIFT                                                 0x0</div><div class='add'>+#define MPCC1_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB_MASK                                                   0x00000FFFL</div><div class='add'>+//MPCC1_ID07_MPCC_BG_B_CB_DB</div><div class='add'>+#define MPCC1_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC1_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC1_ID08_MPCC_CONTROL_DB</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB__SHIFT                                     0x0</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB__SHIFT                          0x4</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB__SHIFT                    0x6</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB__SHIFT                 0x7</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB__SHIFT                                   0x8</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB__SHIFT                            0xb</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB__SHIFT                             0x10</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB__SHIFT                              0x18</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB_MASK                                       0x00000003L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB_MASK                            0x00000030L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB_MASK                      0x00000040L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB_MASK                   0x00000080L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB_MASK                                     0x00000700L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB_MASK                              0x00000800L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB_MASK                               0x00FF0000L</div><div class='add'>+#define MPCC1_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB_MASK                                0xFF000000L</div><div class='add'>+//MPCC1_ID09_MPCC_SM_CONTROL_DB</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB__SHIFT                              0x0</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB__SHIFT                            0x1</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB__SHIFT                       0x4</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB__SHIFT                       0x5</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB_MASK                                0x00000001L</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB_MASK                              0x0000000EL</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB_MASK                         0x00000010L</div><div class='add'>+#define MPCC1_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB_MASK                         0x00000020L</div><div class='add'>+//MPCC1_ID17_MPCC_TOP_PIX</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC1_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC1_ID18_MPCC_recout_start</div><div class='add'>+#define MPCC1_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x__SHIFT                                     0x0</div><div class='add'>+#define MPCC1_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y__SHIFT                                     0x10</div><div class='add'>+#define MPCC1_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x_MASK                                       0x00003FFFL</div><div class='add'>+#define MPCC1_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y_MASK                                       0x3FFF0000L</div><div class='add'>+//MPCC1_ID19_MPCC_recout_size</div><div class='add'>+#define MPCC1_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width__SHIFT                                        0x0</div><div class='add'>+#define MPCC1_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height__SHIFT                                       0x10</div><div class='add'>+#define MPCC1_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width_MASK                                          0x00003FFFL</div><div class='add'>+#define MPCC1_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height_MASK                                         0x3FFF0000L</div><div class='add'>+//MPCC1_ID20_MPCC_mpc_size</div><div class='add'>+#define MPCC1_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width__SHIFT                                              0x0</div><div class='add'>+#define MPCC1_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height__SHIFT                                             0x10</div><div class='add'>+#define MPCC1_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width_MASK                                                0x00003FFFL</div><div class='add'>+#define MPCC1_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height_MASK                                               0x3FFF0000L</div><div class='add'>+//MPCC1_ID21_MPCC_TOP_sideband</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending__SHIFT                                0x16</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+#define MPCC1_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending_MASK                                  0x00400000L</div><div class='add'>+//MPCC1_ID22_MPCC_BOT_PIX</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC1_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC1_ID23_MPCC_BOT_sideband</div><div class='add'>+#define MPCC1_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status__SHIFT                                         0x0</div><div class='add'>+#define MPCC1_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask__SHIFT                                           0x1</div><div class='add'>+#define MPCC1_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status_MASK                                           0x00000001L</div><div class='add'>+#define MPCC1_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask_MASK                                             0x00000002L</div><div class='add'>+//MPCC1_ID24_MPCC_OPP_PIX</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC1_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC1_ID25_MPCC_OPP_sideband</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask__SHIFT                                           0xb</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask_MASK                                             0x00000800L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC1_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc2_mpccdebugind</div><div class='add'>+//MPCC2_ID01_MPCC_SEL_DB</div><div class='add'>+#define MPCC2_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB__SHIFT                                                   0x0</div><div class='add'>+#define MPCC2_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB__SHIFT                                                   0x4</div><div class='add'>+#define MPCC2_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB__SHIFT                                                    0xc</div><div class='add'>+#define MPCC2_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB_MASK                                                     0x0000000FL</div><div class='add'>+#define MPCC2_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB_MASK                                                     0x000000F0L</div><div class='add'>+#define MPCC2_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB_MASK                                                      0x0000F000L</div><div class='add'>+//MPCC2_ID02_MPCC_TOP_GAIN_DB</div><div class='add'>+#define MPCC2_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB__SHIFT                                             0x0</div><div class='add'>+#define MPCC2_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB</div><div class='add'>+#define MPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB__SHIFT                               0x0</div><div class='add'>+#define MPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB_MASK                                 0x0007FFFFL</div><div class='add'>+//MPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB</div><div class='add'>+#define MPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB__SHIFT                             0x0</div><div class='add'>+#define MPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB_MASK                               0x0007FFFFL</div><div class='add'>+//MPCC2_ID05_MPCC_BG_R_CR_DB</div><div class='add'>+#define MPCC2_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC2_ID06_MPCC_BG_G_Y_DB</div><div class='add'>+#define MPCC2_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB__SHIFT                                                 0x0</div><div class='add'>+#define MPCC2_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB_MASK                                                   0x00000FFFL</div><div class='add'>+//MPCC2_ID07_MPCC_BG_B_CB_DB</div><div class='add'>+#define MPCC2_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC2_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC2_ID08_MPCC_CONTROL_DB</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB__SHIFT                                     0x0</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB__SHIFT                          0x4</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB__SHIFT                    0x6</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB__SHIFT                 0x7</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB__SHIFT                                   0x8</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB__SHIFT                            0xb</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB__SHIFT                             0x10</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB__SHIFT                              0x18</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB_MASK                                       0x00000003L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB_MASK                            0x00000030L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB_MASK                      0x00000040L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB_MASK                   0x00000080L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB_MASK                                     0x00000700L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB_MASK                              0x00000800L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB_MASK                               0x00FF0000L</div><div class='add'>+#define MPCC2_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB_MASK                                0xFF000000L</div><div class='add'>+//MPCC2_ID09_MPCC_SM_CONTROL_DB</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB__SHIFT                              0x0</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB__SHIFT                            0x1</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB__SHIFT                       0x4</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB__SHIFT                       0x5</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB_MASK                                0x00000001L</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB_MASK                              0x0000000EL</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB_MASK                         0x00000010L</div><div class='add'>+#define MPCC2_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB_MASK                         0x00000020L</div><div class='add'>+//MPCC2_ID17_MPCC_TOP_PIX</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC2_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC2_ID18_MPCC_recout_start</div><div class='add'>+#define MPCC2_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x__SHIFT                                     0x0</div><div class='add'>+#define MPCC2_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y__SHIFT                                     0x10</div><div class='add'>+#define MPCC2_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x_MASK                                       0x00003FFFL</div><div class='add'>+#define MPCC2_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y_MASK                                       0x3FFF0000L</div><div class='add'>+//MPCC2_ID19_MPCC_recout_size</div><div class='add'>+#define MPCC2_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width__SHIFT                                        0x0</div><div class='add'>+#define MPCC2_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height__SHIFT                                       0x10</div><div class='add'>+#define MPCC2_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width_MASK                                          0x00003FFFL</div><div class='add'>+#define MPCC2_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height_MASK                                         0x3FFF0000L</div><div class='add'>+//MPCC2_ID20_MPCC_mpc_size</div><div class='add'>+#define MPCC2_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width__SHIFT                                              0x0</div><div class='add'>+#define MPCC2_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height__SHIFT                                             0x10</div><div class='add'>+#define MPCC2_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width_MASK                                                0x00003FFFL</div><div class='add'>+#define MPCC2_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height_MASK                                               0x3FFF0000L</div><div class='add'>+//MPCC2_ID21_MPCC_TOP_sideband</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending__SHIFT                                0x16</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+#define MPCC2_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending_MASK                                  0x00400000L</div><div class='add'>+//MPCC2_ID22_MPCC_BOT_PIX</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC2_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC2_ID23_MPCC_BOT_sideband</div><div class='add'>+#define MPCC2_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status__SHIFT                                         0x0</div><div class='add'>+#define MPCC2_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask__SHIFT                                           0x1</div><div class='add'>+#define MPCC2_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status_MASK                                           0x00000001L</div><div class='add'>+#define MPCC2_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask_MASK                                             0x00000002L</div><div class='add'>+//MPCC2_ID24_MPCC_OPP_PIX</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC2_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC2_ID25_MPCC_OPP_sideband</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask__SHIFT                                           0xb</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask_MASK                                             0x00000800L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC2_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc3_mpccdebugind</div><div class='add'>+//MPCC3_ID01_MPCC_SEL_DB</div><div class='add'>+#define MPCC3_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB__SHIFT                                                   0x0</div><div class='add'>+#define MPCC3_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB__SHIFT                                                   0x4</div><div class='add'>+#define MPCC3_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB__SHIFT                                                    0xc</div><div class='add'>+#define MPCC3_ID01_MPCC_SEL_DB__ID01_MPCC_TOP_SEL_DB_MASK                                                     0x0000000FL</div><div class='add'>+#define MPCC3_ID01_MPCC_SEL_DB__ID01_MPCC_BOT_SEL_DB_MASK                                                     0x000000F0L</div><div class='add'>+#define MPCC3_ID01_MPCC_SEL_DB__ID01_MPCC_OPP_ID_DB_MASK                                                      0x0000F000L</div><div class='add'>+//MPCC3_ID02_MPCC_TOP_GAIN_DB</div><div class='add'>+#define MPCC3_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB__SHIFT                                             0x0</div><div class='add'>+#define MPCC3_ID02_MPCC_TOP_GAIN_DB__ID02_MPCC_TOP_GAIN_DB_MASK                                               0x0007FFFFL</div><div class='add'>+//MPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB</div><div class='add'>+#define MPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB__SHIFT                               0x0</div><div class='add'>+#define MPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB__ID03_MPCC_BOT_GAIN_INSIDE_DB_MASK                                 0x0007FFFFL</div><div class='add'>+//MPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB</div><div class='add'>+#define MPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB__SHIFT                             0x0</div><div class='add'>+#define MPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB__ID04_MPCC_BOT_GAIN_OUTSIDE_DB_MASK                               0x0007FFFFL</div><div class='add'>+//MPCC3_ID05_MPCC_BG_R_CR_DB</div><div class='add'>+#define MPCC3_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_ID05_MPCC_BG_R_CR_DB__ID05_MPCC_BG_R_CR_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC3_ID06_MPCC_BG_G_Y_DB</div><div class='add'>+#define MPCC3_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB__SHIFT                                                 0x0</div><div class='add'>+#define MPCC3_ID06_MPCC_BG_G_Y_DB__ID06_MPCC_BG_G_Y_DB_MASK                                                   0x00000FFFL</div><div class='add'>+//MPCC3_ID07_MPCC_BG_B_CB_DB</div><div class='add'>+#define MPCC3_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB__SHIFT                                               0x0</div><div class='add'>+#define MPCC3_ID07_MPCC_BG_B_CB_DB__ID07_MPCC_BG_B_CB_DB_MASK                                                 0x00000FFFL</div><div class='add'>+//MPCC3_ID08_MPCC_CONTROL_DB</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB__SHIFT                                     0x0</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB__SHIFT                          0x4</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB__SHIFT                    0x6</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB__SHIFT                 0x7</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB__SHIFT                                   0x8</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB__SHIFT                            0xb</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB__SHIFT                             0x10</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB__SHIFT                              0x18</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_MODE_DB_MASK                                       0x00000003L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_DB_MASK                            0x00000030L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_DB_MASK                      0x00000040L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BLND_ACTIVE_OVERLAP_ONLY_DB_MASK                   0x00000080L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BG_BPC_DB_MASK                                     0x00000700L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_BOT_GAIN_MODE_DB_MASK                              0x00000800L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_ALPHA_DB_MASK                               0x00FF0000L</div><div class='add'>+#define MPCC3_ID08_MPCC_CONTROL_DB__ID08_MPCC_CONTROL_MPCC_GLOBAL_GAIN_DB_MASK                                0xFF000000L</div><div class='add'>+//MPCC3_ID09_MPCC_SM_CONTROL_DB</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB__SHIFT                              0x0</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB__SHIFT                            0x1</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB__SHIFT                       0x4</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB__SHIFT                       0x5</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_EN_DB_MASK                                0x00000001L</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_MODE_DB_MASK                              0x0000000EL</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_DB_MASK                         0x00000010L</div><div class='add'>+#define MPCC3_ID09_MPCC_SM_CONTROL_DB__ID09_MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_DB_MASK                         0x00000020L</div><div class='add'>+//MPCC3_ID17_MPCC_TOP_PIX</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC3_ID17_MPCC_TOP_PIX__ID17_MPCC_TOP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC3_ID18_MPCC_recout_start</div><div class='add'>+#define MPCC3_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x__SHIFT                                     0x0</div><div class='add'>+#define MPCC3_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y__SHIFT                                     0x10</div><div class='add'>+#define MPCC3_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_x_MASK                                       0x00003FFFL</div><div class='add'>+#define MPCC3_ID18_MPCC_recout_start__ID18_DPP_MPCC_recout_start_y_MASK                                       0x3FFF0000L</div><div class='add'>+//MPCC3_ID19_MPCC_recout_size</div><div class='add'>+#define MPCC3_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width__SHIFT                                        0x0</div><div class='add'>+#define MPCC3_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height__SHIFT                                       0x10</div><div class='add'>+#define MPCC3_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_width_MASK                                          0x00003FFFL</div><div class='add'>+#define MPCC3_ID19_MPCC_recout_size__ID19_DPP_MPCC_recout_height_MASK                                         0x3FFF0000L</div><div class='add'>+//MPCC3_ID20_MPCC_mpc_size</div><div class='add'>+#define MPCC3_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width__SHIFT                                              0x0</div><div class='add'>+#define MPCC3_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height__SHIFT                                             0x10</div><div class='add'>+#define MPCC3_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_width_MASK                                                0x00003FFFL</div><div class='add'>+#define MPCC3_ID20_MPCC_mpc_size__ID20_DPP_MPCC_mpc_height_MASK                                               0x3FFF0000L</div><div class='add'>+//MPCC3_ID21_MPCC_TOP_sideband</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending__SHIFT                                0x16</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_DPP_MPCC_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_DPP_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+#define MPCC3_ID21_MPCC_TOP_sideband__ID21_MPCC_TOP_mpcc_update_pending_MASK                                  0x00400000L</div><div class='add'>+//MPCC3_ID22_MPCC_BOT_PIX</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC3_ID22_MPCC_BOT_PIX__ID22_MPCC_BOT_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC3_ID23_MPCC_BOT_sideband</div><div class='add'>+#define MPCC3_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status__SHIFT                                         0x0</div><div class='add'>+#define MPCC3_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask__SHIFT                                           0x1</div><div class='add'>+#define MPCC3_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_status_MASK                                           0x00000001L</div><div class='add'>+#define MPCC3_ID23_MPCC_BOT_sideband__ID23_MPCC_BOT_tmz_mask_MASK                                             0x00000002L</div><div class='add'>+//MPCC3_ID24_MPCC_OPP_PIX</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y__SHIFT                                                 0x0</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR__SHIFT                                                     0x14</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS__SHIFT                                                     0x15</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL__SHIFT                                                     0x16</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF__SHIFT                                                     0x17</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_PIX_G_Y_MASK                                                   0x0007FFFFL</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTR_MASK                                                       0x00100000L</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_RTS_MASK                                                       0x00200000L</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOL_MASK                                                       0x00400000L</div><div class='add'>+#define MPCC3_ID24_MPCC_OPP_PIX__ID24_MPCC_OPP_EOF_MASK                                                       0x00800000L</div><div class='add'>+//MPCC3_ID25_MPCC_OPP_sideband</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending__SHIFT                                       0x5</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending__SHIFT                                     0x6</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending__SHIFT                              0x7</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending__SHIFT                                  0x8</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending__SHIFT                                  0x9</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status__SHIFT                                         0xa</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask__SHIFT                                           0xb</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en__SHIFT                                       0xc</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field__SHIFT                                0xd</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select__SHIFT                                      0xe</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi__SHIFT                                                0xf</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger__SHIFT                                   0x10</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip__SHIFT                                     0x11</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock__SHIFT                                0x12</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock__SHIFT                                 0x13</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_flip_pending_MASK                                         0x00000020L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_update_pending_MASK                                       0x00000040L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_cursor_update_pending_MASK                                0x00000080L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_vflip_gsl_pending_MASK                                    0x00000100L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_iflip_gsl_pending_MASK                                    0x00000200L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_status_MASK                                           0x00000400L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_MPCC_OPP_tmz_mask_MASK                                             0x00000800L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_en_MASK                                         0x00001000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_interlace_out_field_MASK                                  0x00002000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_stereo_select_MASK                                        0x00004000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_vbi_MASK                                                  0x00008000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_snapshot_trigger_MASK                                     0x00010000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_allow_flip_MASK                                       0x00020000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_gsl_vupdate_unblock_MASK                                  0x00040000L</div><div class='add'>+#define MPCC3_ID25_MPCC_OPP_sideband__ID25_OPP_MPCC_master_update_lock_MASK                                   0x00080000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam0_mpcc_ogamdebugind</div><div class='add'>+//MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB__SHIFT                                      0x0</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                            0x4</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL__SHIFT                                  0x7</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS__SHIFT                                       0x8</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE__SHIFT                                0x9</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB_MASK                                        0x00000003L</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                              0x00000070L</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL_MASK                                    0x00000080L</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS_MASK                                         0x00000100L</div><div class='add'>+#define MPCC_OGAM0_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE_MASK                                  0x00000600L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm0_mpcc_mcmdebugind</div><div class='add'>+//MPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER</div><div class='add'>+#define MPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER</div><div class='add'>+#define MPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT</div><div class='add'>+#define MPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT_MASK                                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP_MASK                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam1_mpcc_ogamdebugind</div><div class='add'>+//MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB__SHIFT                                      0x0</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                            0x4</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL__SHIFT                                  0x7</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS__SHIFT                                       0x8</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE__SHIFT                                0x9</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB_MASK                                        0x00000003L</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                              0x00000070L</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL_MASK                                    0x00000080L</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS_MASK                                         0x00000100L</div><div class='add'>+#define MPCC_OGAM1_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE_MASK                                  0x00000600L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm1_mpcc_mcmdebugind</div><div class='add'>+//MPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER</div><div class='add'>+#define MPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER</div><div class='add'>+#define MPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT</div><div class='add'>+#define MPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT_MASK                                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP_MASK                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam2_mpcc_ogamdebugind</div><div class='add'>+//MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB__SHIFT                                      0x0</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                            0x4</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL__SHIFT                                  0x7</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS__SHIFT                                       0x8</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE__SHIFT                                0x9</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB_MASK                                        0x00000003L</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                              0x00000070L</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL_MASK                                    0x00000080L</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS_MASK                                         0x00000100L</div><div class='add'>+#define MPCC_OGAM2_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE_MASK                                  0x00000600L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm2_mpcc_mcmdebugind</div><div class='add'>+//MPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER</div><div class='add'>+#define MPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER</div><div class='add'>+#define MPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT</div><div class='add'>+#define MPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT_MASK                                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP_MASK                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_ogam3_mpcc_ogamdebugind</div><div class='add'>+//MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB__SHIFT                                      0x0</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                            0x4</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL__SHIFT                                  0x7</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS__SHIFT                                       0x8</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE__SHIFT                                0x9</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MODE_DB_MASK                                        0x00000003L</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                              0x00000070L</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_LUT_RAM_SEL_MASK                                    0x00000080L</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_BYPASS_MASK                                         0x00000100L</div><div class='add'>+#define MPCC_OGAM3_ID01_MPCC_OGAM_CONTROL__ID01_MPCC_OGAM_MEM_PWR_STATE_MASK                                  0x00000600L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: mpcc_mcm3_mpcc_mcmdebugind</div><div class='add'>+//MPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER</div><div class='add'>+#define MPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER__ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER</div><div class='add'>+#define MPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__SHIFT         0x0</div><div class='add'>+#define MPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER__ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER_MASK           0x0007FFFFL</div><div class='add'>+//MPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT</div><div class='add'>+#define MPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT__SHIFT                                     0x0</div><div class='add'>+#define MPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT__ID10_MPCC_MCM_R2F_3DLUT_MASK                                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP__SHIFT                     0x0</div><div class='add'>+#define MPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP__ID11_MPCC_MCM_FIRST_GAMUT_REMAP_MASK                       0xFFFFFFFFL</div><div class='add'>+//MPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP</div><div class='add'>+#define MPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP__SHIFT                   0x0</div><div class='add'>+#define MPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP__ID12_MPCC_MCM_SECOND_GAMUT_REMAP_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: abm0_abmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: abm1_abmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: abm2_abmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: abm3_abmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dpg0_dpgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dpg1_dpgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dpg2_dpgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dpg3_dpgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: fmt0_fmtdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: fmt1_fmtdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: fmt2_fmtdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: fmt3_fmtdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: oppbuf0_oppbufdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: oppbuf1_oppbufdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: oppbuf2_oppbufdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: oppbuf3_oppbufdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: opp_pipe0_opppipedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: opp_pipe1_opppipedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: opp_pipe2_opppipedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: opp_pipe3_opppipedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: opp_top_opp_topdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: odm0_odmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: odm1_odmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: odm2_odmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: odm3_odmdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg0_otgdebugind</div><div class='add'>+//OTG0_OTG_DBG_DATA1</div><div class='add'>+#define OTG0_OTG_DBG_DATA1__OTG_DBG_DATA1__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA1__OTG_DBG_DATA1_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA2</div><div class='add'>+#define OTG0_OTG_DBG_DATA2__OTG_DBG_DATA2__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA2__OTG_DBG_DATA2_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA3</div><div class='add'>+#define OTG0_OTG_DBG_DATA3__OTG_DBG_DATA3__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA3__OTG_DBG_DATA3_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA4</div><div class='add'>+#define OTG0_OTG_DBG_DATA4__OTG_DBG_DATA4__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA4__OTG_DBG_DATA4_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA5</div><div class='add'>+#define OTG0_OTG_DBG_DATA5__OTG_DBG_DATA5__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA5__OTG_DBG_DATA5_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA6</div><div class='add'>+#define OTG0_OTG_DBG_DATA6__OTG_DBG_DATA6__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA6__OTG_DBG_DATA6_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA7</div><div class='add'>+#define OTG0_OTG_DBG_DATA7__OTG_DBG_DATA7__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA7__OTG_DBG_DATA7_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA8</div><div class='add'>+#define OTG0_OTG_DBG_DATA8__OTG_DBG_DATA8__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA8__OTG_DBG_DATA8_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA9</div><div class='add'>+#define OTG0_OTG_DBG_DATA9__OTG_DBG_DATA9__SHIFT                                                              0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA9__OTG_DBG_DATA9_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_DBG_DATA10</div><div class='add'>+#define OTG0_OTG_DBG_DATA10__OTG_DBG_DATA10__SHIFT                                                            0x0</div><div class='add'>+#define OTG0_OTG_DBG_DATA10__OTG_DBG_DATA10_MASK                                                              0xFFFFFFFFL</div><div class='add'>+//OTG0_OTG_SCL_INTERFACE</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS__SHIFT                                          0x0</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE__SHIFT                                                0x2</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL__SHIFT                                                       0x3</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE__SHIFT                                                  0x4</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL__SHIFT                                                       0x5</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE__SHIFT                                                  0x6</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8__SHIFT                                               0x7</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT__SHIFT                                          0x8</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT__SHIFT                                             0x9</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS_MASK                                            0x00000001L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_MASK                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE_MASK                                                  0x00000004L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL_MASK                                                         0x00000008L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE_MASK                                                    0x00000010L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL_MASK                                                         0x00000020L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8_MASK                                                 0x00000080L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT_MASK                                            0x00000100L</div><div class='add'>+#define OTG0_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT_MASK                                               0x00000200L</div><div class='add'>+//OTG0_OTG_DOUT_INTERFACE_01_A</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE__SHIFT                                        0x0</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE__SHIFT                                         0x2</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE_MASK                                          0x00000001L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK_MASK                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE_MASK                                           0x00000004L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG0_OTG_DOUT_INTERFACE_01_B</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G__SHIFT                                             0x0</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B__SHIFT                                             0x10</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G_MASK                                               0x0000FFFFL</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG0_OTG_DOUT_INTERFACE_02</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A__SHIFT                                              0x0</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A__SHIFT                                              0x1</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A__SHIFT                                       0x2</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE__SHIFT                                          0x3</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK__SHIFT                                                0x4</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC__SHIFT                                           0x5</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER__SHIFT                                         0x6</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE__SHIFT                                               0x7</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B__SHIFT                                              0x8</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B__SHIFT                                              0x9</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B__SHIFT                                       0xa</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL__SHIFT                                          0xb</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A_MASK                                                0x00000001L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A_MASK                                                0x00000002L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A_MASK                                         0x00000004L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE_MASK                                            0x00000008L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK_MASK                                                  0x00000010L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC_MASK                                             0x00000020L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER_MASK                                           0x00000040L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE_MASK                                                 0x00000080L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B_MASK                                                0x00000100L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B_MASK                                                0x00000200L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B_MASK                                         0x00000400L</div><div class='add'>+#define OTG0_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL_MASK                                            0x00000800L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg1_otgdebugind</div><div class='add'>+//OTG1_OTG_DBG_DATA1</div><div class='add'>+#define OTG1_OTG_DBG_DATA1__OTG_DBG_DATA1__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA1__OTG_DBG_DATA1_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA2</div><div class='add'>+#define OTG1_OTG_DBG_DATA2__OTG_DBG_DATA2__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA2__OTG_DBG_DATA2_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA3</div><div class='add'>+#define OTG1_OTG_DBG_DATA3__OTG_DBG_DATA3__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA3__OTG_DBG_DATA3_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA4</div><div class='add'>+#define OTG1_OTG_DBG_DATA4__OTG_DBG_DATA4__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA4__OTG_DBG_DATA4_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA5</div><div class='add'>+#define OTG1_OTG_DBG_DATA5__OTG_DBG_DATA5__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA5__OTG_DBG_DATA5_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA6</div><div class='add'>+#define OTG1_OTG_DBG_DATA6__OTG_DBG_DATA6__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA6__OTG_DBG_DATA6_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA7</div><div class='add'>+#define OTG1_OTG_DBG_DATA7__OTG_DBG_DATA7__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA7__OTG_DBG_DATA7_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA8</div><div class='add'>+#define OTG1_OTG_DBG_DATA8__OTG_DBG_DATA8__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA8__OTG_DBG_DATA8_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA9</div><div class='add'>+#define OTG1_OTG_DBG_DATA9__OTG_DBG_DATA9__SHIFT                                                              0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA9__OTG_DBG_DATA9_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_DBG_DATA10</div><div class='add'>+#define OTG1_OTG_DBG_DATA10__OTG_DBG_DATA10__SHIFT                                                            0x0</div><div class='add'>+#define OTG1_OTG_DBG_DATA10__OTG_DBG_DATA10_MASK                                                              0xFFFFFFFFL</div><div class='add'>+//OTG1_OTG_SCL_INTERFACE</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS__SHIFT                                          0x0</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE__SHIFT                                                0x2</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL__SHIFT                                                       0x3</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE__SHIFT                                                  0x4</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL__SHIFT                                                       0x5</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE__SHIFT                                                  0x6</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8__SHIFT                                               0x7</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT__SHIFT                                          0x8</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT__SHIFT                                             0x9</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS_MASK                                            0x00000001L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_MASK                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE_MASK                                                  0x00000004L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL_MASK                                                         0x00000008L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE_MASK                                                    0x00000010L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL_MASK                                                         0x00000020L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8_MASK                                                 0x00000080L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT_MASK                                            0x00000100L</div><div class='add'>+#define OTG1_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT_MASK                                               0x00000200L</div><div class='add'>+//OTG1_OTG_DOUT_INTERFACE_01_A</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE__SHIFT                                        0x0</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE__SHIFT                                         0x2</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE_MASK                                          0x00000001L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK_MASK                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE_MASK                                           0x00000004L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG1_OTG_DOUT_INTERFACE_01_B</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G__SHIFT                                             0x0</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B__SHIFT                                             0x10</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G_MASK                                               0x0000FFFFL</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG1_OTG_DOUT_INTERFACE_02</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A__SHIFT                                              0x0</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A__SHIFT                                              0x1</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A__SHIFT                                       0x2</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE__SHIFT                                          0x3</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK__SHIFT                                                0x4</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC__SHIFT                                           0x5</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER__SHIFT                                         0x6</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE__SHIFT                                               0x7</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B__SHIFT                                              0x8</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B__SHIFT                                              0x9</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B__SHIFT                                       0xa</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL__SHIFT                                          0xb</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A_MASK                                                0x00000001L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A_MASK                                                0x00000002L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A_MASK                                         0x00000004L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE_MASK                                            0x00000008L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK_MASK                                                  0x00000010L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC_MASK                                             0x00000020L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER_MASK                                           0x00000040L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE_MASK                                                 0x00000080L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B_MASK                                                0x00000100L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B_MASK                                                0x00000200L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B_MASK                                         0x00000400L</div><div class='add'>+#define OTG1_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL_MASK                                            0x00000800L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg2_otgdebugind</div><div class='add'>+//OTG2_OTG_DBG_DATA1</div><div class='add'>+#define OTG2_OTG_DBG_DATA1__OTG_DBG_DATA1__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA1__OTG_DBG_DATA1_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA2</div><div class='add'>+#define OTG2_OTG_DBG_DATA2__OTG_DBG_DATA2__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA2__OTG_DBG_DATA2_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA3</div><div class='add'>+#define OTG2_OTG_DBG_DATA3__OTG_DBG_DATA3__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA3__OTG_DBG_DATA3_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA4</div><div class='add'>+#define OTG2_OTG_DBG_DATA4__OTG_DBG_DATA4__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA4__OTG_DBG_DATA4_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA5</div><div class='add'>+#define OTG2_OTG_DBG_DATA5__OTG_DBG_DATA5__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA5__OTG_DBG_DATA5_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA6</div><div class='add'>+#define OTG2_OTG_DBG_DATA6__OTG_DBG_DATA6__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA6__OTG_DBG_DATA6_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA7</div><div class='add'>+#define OTG2_OTG_DBG_DATA7__OTG_DBG_DATA7__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA7__OTG_DBG_DATA7_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA8</div><div class='add'>+#define OTG2_OTG_DBG_DATA8__OTG_DBG_DATA8__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA8__OTG_DBG_DATA8_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA9</div><div class='add'>+#define OTG2_OTG_DBG_DATA9__OTG_DBG_DATA9__SHIFT                                                              0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA9__OTG_DBG_DATA9_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_DBG_DATA10</div><div class='add'>+#define OTG2_OTG_DBG_DATA10__OTG_DBG_DATA10__SHIFT                                                            0x0</div><div class='add'>+#define OTG2_OTG_DBG_DATA10__OTG_DBG_DATA10_MASK                                                              0xFFFFFFFFL</div><div class='add'>+//OTG2_OTG_SCL_INTERFACE</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS__SHIFT                                          0x0</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE__SHIFT                                                0x2</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL__SHIFT                                                       0x3</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE__SHIFT                                                  0x4</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL__SHIFT                                                       0x5</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE__SHIFT                                                  0x6</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8__SHIFT                                               0x7</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT__SHIFT                                          0x8</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT__SHIFT                                             0x9</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS_MASK                                            0x00000001L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_MASK                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE_MASK                                                  0x00000004L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL_MASK                                                         0x00000008L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE_MASK                                                    0x00000010L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL_MASK                                                         0x00000020L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8_MASK                                                 0x00000080L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT_MASK                                            0x00000100L</div><div class='add'>+#define OTG2_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT_MASK                                               0x00000200L</div><div class='add'>+//OTG2_OTG_DOUT_INTERFACE_01_A</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE__SHIFT                                        0x0</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE__SHIFT                                         0x2</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE_MASK                                          0x00000001L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK_MASK                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE_MASK                                           0x00000004L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG2_OTG_DOUT_INTERFACE_01_B</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G__SHIFT                                             0x0</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B__SHIFT                                             0x10</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G_MASK                                               0x0000FFFFL</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG2_OTG_DOUT_INTERFACE_02</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A__SHIFT                                              0x0</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A__SHIFT                                              0x1</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A__SHIFT                                       0x2</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE__SHIFT                                          0x3</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK__SHIFT                                                0x4</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC__SHIFT                                           0x5</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER__SHIFT                                         0x6</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE__SHIFT                                               0x7</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B__SHIFT                                              0x8</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B__SHIFT                                              0x9</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B__SHIFT                                       0xa</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL__SHIFT                                          0xb</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A_MASK                                                0x00000001L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A_MASK                                                0x00000002L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A_MASK                                         0x00000004L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE_MASK                                            0x00000008L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK_MASK                                                  0x00000010L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC_MASK                                             0x00000020L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER_MASK                                           0x00000040L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE_MASK                                                 0x00000080L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B_MASK                                                0x00000100L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B_MASK                                                0x00000200L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B_MASK                                         0x00000400L</div><div class='add'>+#define OTG2_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL_MASK                                            0x00000800L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: otg3_otgdebugind</div><div class='add'>+//OTG3_OTG_DBG_DATA1</div><div class='add'>+#define OTG3_OTG_DBG_DATA1__OTG_DBG_DATA1__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA1__OTG_DBG_DATA1_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA2</div><div class='add'>+#define OTG3_OTG_DBG_DATA2__OTG_DBG_DATA2__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA2__OTG_DBG_DATA2_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA3</div><div class='add'>+#define OTG3_OTG_DBG_DATA3__OTG_DBG_DATA3__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA3__OTG_DBG_DATA3_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA4</div><div class='add'>+#define OTG3_OTG_DBG_DATA4__OTG_DBG_DATA4__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA4__OTG_DBG_DATA4_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA5</div><div class='add'>+#define OTG3_OTG_DBG_DATA5__OTG_DBG_DATA5__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA5__OTG_DBG_DATA5_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA6</div><div class='add'>+#define OTG3_OTG_DBG_DATA6__OTG_DBG_DATA6__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA6__OTG_DBG_DATA6_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA7</div><div class='add'>+#define OTG3_OTG_DBG_DATA7__OTG_DBG_DATA7__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA7__OTG_DBG_DATA7_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA8</div><div class='add'>+#define OTG3_OTG_DBG_DATA8__OTG_DBG_DATA8__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA8__OTG_DBG_DATA8_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA9</div><div class='add'>+#define OTG3_OTG_DBG_DATA9__OTG_DBG_DATA9__SHIFT                                                              0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA9__OTG_DBG_DATA9_MASK                                                                0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_DBG_DATA10</div><div class='add'>+#define OTG3_OTG_DBG_DATA10__OTG_DBG_DATA10__SHIFT                                                            0x0</div><div class='add'>+#define OTG3_OTG_DBG_DATA10__OTG_DBG_DATA10_MASK                                                              0xFFFFFFFFL</div><div class='add'>+//OTG3_OTG_SCL_INTERFACE</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS__SHIFT                                          0x0</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE__SHIFT                                                0x2</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL__SHIFT                                                       0x3</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE__SHIFT                                                  0x4</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL__SHIFT                                                       0x5</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE__SHIFT                                                  0x6</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8__SHIFT                                               0x7</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT__SHIFT                                          0x8</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT__SHIFT                                             0x9</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_DIS_MASK                                            0x00000001L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_READ_REQUEST_MASK                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_START_LINE_MASK                                                  0x00000004L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_EOL_MASK                                                         0x00000008L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_END_LINE_MASK                                                    0x00000010L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_SOL_MASK                                                         0x00000020L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_V_UPDATE_MASK                                                    0x00000040L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_HTOTAL_BY_8_MASK                                                 0x00000080L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_INTERLACE_SELECT_MASK                                            0x00000100L</div><div class='add'>+#define OTG3_OTG_SCL_INTERFACE__ID42_OTG_SCL_STEREO_SELECT_MASK                                               0x00000200L</div><div class='add'>+//OTG3_OTG_DOUT_INTERFACE_01_A</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE__SHIFT                                        0x0</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE__SHIFT                                         0x2</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_ACTIVE_MASK                                          0x00000001L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_BLANK_MASK                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_CRC_DATA_ACTIVE_MASK                                           0x00000004L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_A__ID43_OTG_DOUT_DATA_R_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG3_OTG_DOUT_INTERFACE_01_B</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G__SHIFT                                             0x0</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B__SHIFT                                             0x10</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_G_MASK                                               0x0000FFFFL</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_01_B__ID43_OTG_DOUT_DATA_B_MASK                                               0xFFFF0000L</div><div class='add'>+//OTG3_OTG_DOUT_INTERFACE_02</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A__SHIFT                                              0x0</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A__SHIFT                                              0x1</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A__SHIFT                                       0x2</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE__SHIFT                                          0x3</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK__SHIFT                                                0x4</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC__SHIFT                                           0x5</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER__SHIFT                                         0x6</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE__SHIFT                                               0x7</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B__SHIFT                                              0x8</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B__SHIFT                                              0x9</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B__SHIFT                                       0xa</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL__SHIFT                                          0xb</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_A_MASK                                                0x00000001L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_A_MASK                                                0x00000002L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_A_MASK                                         0x00000004L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_DATA_ACTIVE_MASK                                            0x00000008L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_BLANK_MASK                                                  0x00000010L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_STEREOSYNC_MASK                                             0x00000020L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FIELD_NUMBER_MASK                                           0x00000040L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_FREEZE_MASK                                                 0x00000080L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_HSYNC_B_MASK                                                0x00000100L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VSYNC_B_MASK                                                0x00000200L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_CAPTURESTART_B_MASK                                         0x00000400L</div><div class='add'>+#define OTG3_OTG_DOUT_INTERFACE_02__ID45_OTG_DOUT_VALID_PIXEL_MASK                                            0x00000800L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dmcub_dmcubdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: rbbmif_rbbmifdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: ihc_ihcdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dmu_misc_dmumiscdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dc_pg_dc_pgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dccg_dccgdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp0_dpdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp0_dpfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp0_dpfe_dprefclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig0_digdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig0_digfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp1_dpdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp1_dpfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp1_dpfe_dprefclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig1_digdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig1_digfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp2_dpdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp2_dpfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp2_dpfe_dprefclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig2_digdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig2_digfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp3_dpdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp3_dpfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp3_dpfe_dprefclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig3_digdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dig3_digfedebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dio_misc_dio_miscdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcoh_top_dcoh_topdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux0_auxdebugdispclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux0_auxdebugrefclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux1_auxdebugdispclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux1_auxdebugrefclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux2_auxdebugdispclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux2_auxdebugrefclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux3_auxdebugdispclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_aux3_auxdebugrefclkind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hpd0_hpddebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hpd1_hpddebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hpd2_hpddebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hpd3_hpddebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hpo_top_hpo_topdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hdmi_link_enc0_linkencdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hdmi_frl_enc0_frldebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_hdmistreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_dispclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: hdmi_tb_enc0_hdmi_tb_encdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc0_dp_stream_enc_dispclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc0_dp_stream_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc0_dp_stream_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc0_dp_sym32_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc0_dp_sym32_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc1_dp_stream_enc_dispclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc1_dp_stream_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc1_dp_stream_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc1_dp_sym32_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc1_dp_sym32_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc2_dp_stream_enc_dispclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc2_dp_stream_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc2_dp_stream_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc2_dp_sym32_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc2_dp_sym32_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc3_dp_stream_enc_dispclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc3_dp_stream_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_stream_enc3_dp_stream_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc3_dp_sym32_enc_symclk32_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_sym32_enc3_dp_sym32_enc_dpstreamclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_link_enc0_dplinkencdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_dphy_sym320_dpdphysym32debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_link_enc1_dplinkencdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_dphy_sym321_dpdphysym32debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_link_enc2_dplinkencdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_dphy_sym322_dpdphysym32debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_link_enc3_dplinkencdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dp_dphy_sym323_dpdphysym32debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: apg_apg_socclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: apg_apg_encclk_debugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: dcio_dciodebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: pwrseq_pwrseqdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_f2codecind</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L</div><div class='add'>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX__SHIFT                                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI__SHIFT                                             0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE__SHIFT                                       0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX_MASK                                                 0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI_MASK                                               0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE_MASK                                         0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA_MASK                                                   0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_HBR</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L</div><div class='add'>+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_descriptorind</div><div class='add'>+//AUDIO_DESCRIPTOR0</div><div class='add'>+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR1</div><div class='add'>+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR2</div><div class='add'>+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR3</div><div class='add'>+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR4</div><div class='add'>+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR5</div><div class='add'>+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR6</div><div class='add'>+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR7</div><div class='add'>+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR8</div><div class='add'>+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR9</div><div class='add'>+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR10</div><div class='add'>+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR11</div><div class='add'>+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR12</div><div class='add'>+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+//AUDIO_DESCRIPTOR13</div><div class='add'>+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8</div><div class='add'>+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18</div><div class='add'>+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L</div><div class='add'>+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L</div><div class='add'>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azendpoint_sinkinfoind</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//SINK_DESCRIPTION0</div><div class='add'>+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION1</div><div class='add'>+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION2</div><div class='add'>+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION3</div><div class='add'>+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION4</div><div class='add'>+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION5</div><div class='add'>+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION6</div><div class='add'>+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION7</div><div class='add'>+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION8</div><div class='add'>+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION9</div><div class='add'>+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0</div><div class='add'>+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION10</div><div class='add'>+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION11</div><div class='add'>+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION12</div><div class='add'>+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION13</div><div class='add'>+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION14</div><div class='add'>+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION15</div><div class='add'>+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION16</div><div class='add'>+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+//SINK_DESCRIPTION17</div><div class='add'>+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0</div><div class='add'>+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc0resultind</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL1</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL2</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL3</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL4</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL5</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL6</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC0_CHANNEL7</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azinputcrc1resultind</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL1</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL2</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL3</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL4</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL5</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL6</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL</div><div class='add'>+//AZALIA_INPUT_CRC1_CHANNEL7</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0</div><div class='add'>+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc0resultind</div><div class='add'>+//AZALIA_CRC0_CHANNEL0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL1</div><div class='add'>+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL2</div><div class='add'>+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL3</div><div class='add'>+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL4</div><div class='add'>+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL5</div><div class='add'>+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL6</div><div class='add'>+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC0_CHANNEL7</div><div class='add'>+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azcrc1resultind</div><div class='add'>+//AZALIA_CRC1_CHANNEL0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL1</div><div class='add'>+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL2</div><div class='add'>+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL3</div><div class='add'>+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL4</div><div class='add'>+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL5</div><div class='add'>+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL6</div><div class='add'>+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL</div><div class='add'>+//AZALIA_CRC1_CHANNEL7</div><div class='add'>+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0</div><div class='add'>+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0controller_azf0controllerdebugind</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azinputendpoint_f2codecind</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L</div><div class='add'>+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L</div><div class='add'>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azroot_f2codecind</div><div class='add'>+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL</div><div class='add'>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L</div><div class='add'>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream0_streamind</div><div class='add'>+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream1_streamind</div><div class='add'>+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream2_streamind</div><div class='add'>+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream3_streamind</div><div class='add'>+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream4_streamind</div><div class='add'>+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream5_streamind</div><div class='add'>+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream6_streamind</div><div class='add'>+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream7_streamind</div><div class='add'>+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream8_streamind</div><div class='add'>+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream9_streamind</div><div class='add'>+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L</div><div class='add'>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L</div><div class='add'>+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L</div><div class='add'>+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0</div><div class='add'>+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream10_streamind</div><div class='add'>+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream11_streamind</div><div class='add'>+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream12_streamind</div><div class='add'>+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream13_streamind</div><div class='add'>+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream14_streamind</div><div class='add'>+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0stream15_streamind</div><div class='add'>+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L</div><div class='add'>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L</div><div class='add'>+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL</div><div class='add'>+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L</div><div class='add'>+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0</div><div class='add'>+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint0_endpointind</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint1_endpointind</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L</div><div class='add'>+//AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK                             0x00000001L</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: azf0endpoint2_endpointind</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT                                  0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT                                0x6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT                          0x7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT                                   0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT                   0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT                   0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK                                    0x0000003FL</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK                                  0x00000040L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK                            0x00000080L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK                                     0x00000300L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK                     0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK                     0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L</div><div class='add'>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1</div><div class='add'>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4